diff -ruw linux-4.4.115/arch/arm/boot/dts/include/dt-bindings/input/linux-event-codes.h linux-4.4.115-fbx/arch/arm/boot/dts/include/dt-bindings/input/linux-event-codes.h --- linux-4.4.115/arch/arm/boot/dts/include/dt-bindings/input/linux-event-codes.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/arch/arm/boot/dts/include/dt-bindings/input/linux-event-codes.h 2019-10-29 09:26:25.545221791 +0100 @@ -611,6 +611,37 @@ #define KEY_KBDINPUTASSIST_ACCEPT 0x264 #define KEY_KBDINPUTASSIST_CANCEL 0x265 +/* Diagonal movement keys */ +#define KEY_RIGHT_UP 0x266 +#define KEY_RIGHT_DOWN 0x267 +#define KEY_LEFT_UP 0x268 +#define KEY_LEFT_DOWN 0x269 + +#define KEY_ROOT_MENU 0x26a /* Show Device's Root Menu */ +/* Show Top Menu of the Media (e.g. DVD) */ +#define KEY_MEDIA_TOP_MENU 0x26b +#define KEY_NUMERIC_11 0x26c +#define KEY_NUMERIC_12 0x26d +/* + * Toggle Audio Description: refers to an audio service that helps blind and + * visually impaired consumers understand the action in a program. Note: in + * some countries this is referred to as "Video Description". + */ +#define KEY_AUDIO_DESC 0x26e +#define KEY_3D_MODE 0x26f +#define KEY_NEXT_FAVORITE 0x270 +#define KEY_STOP_RECORD 0x271 +#define KEY_PAUSE_RECORD 0x272 +#define KEY_VOD 0x273 /* Video on Demand */ +#define KEY_UNMUTE 0x274 +#define KEY_FASTREVERSE 0x275 +#define KEY_SLOWREVERSE 0x276 +/* + * Control a data application associated with the currently viewed channel, + * e.g. teletext or data broadcast application (MHEG, MHP, HbbTV, etc.) + */ +#define KEY_DATA 0x275 + #define BTN_TRIGGER_HAPPY 0x2c0 #define BTN_TRIGGER_HAPPY1 0x2c0 #define BTN_TRIGGER_HAPPY2 0x2c1 @@ -653,6 +684,18 @@ #define BTN_TRIGGER_HAPPY39 0x2e6 #define BTN_TRIGGER_HAPPY40 0x2e7 +#define KEY_APP_TV 0x2f1 +#define KEY_APP_REPLAY 0x2f2 +#define KEY_APP_VIDEOCLUB 0x2f3 +#define KEY_APP_WHATSON 0x2f4 +#define KEY_APP_RECORDS 0x2f5 +#define KEY_APP_MEDIA 0x2f6 +#define KEY_APP_YOUTUBE 0x2f7 +#define KEY_APP_RADIOS 0x2f8 +#define KEY_APP_CANALVOD 0x2f9 +#define KEY_APP_PIP 0x2fa +#define KEY_APP_NETFLIX 0x2fb + /* We avoid low common keys in module aliases so they don't get huge. */ #define KEY_MIN_INTERESTING KEY_MUTE #define KEY_MAX 0x2ff @@ -749,7 +792,11 @@ #define SW_ROTATE_LOCK 0x0c /* set = rotate locked/disabled */ #define SW_LINEIN_INSERT 0x0d /* set = inserted */ #define SW_MUTE_DEVICE 0x0e /* set = device disabled */ -#define SW_MAX 0x0f +#define SW_HPHL_OVERCURRENT 0x0f /* set = over current on left hph */ +#define SW_HPHR_OVERCURRENT 0x10 /* set = over current on right hph */ +#define SW_MICROPHONE2_INSERT 0x11 /* set = inserted */ +#define SW_UNSUPPORT_INSERT 0x12 /* set = unsupported device inserted */ +#define SW_MAX 0x20 #define SW_CNT (SW_MAX+1) /* diff -ruw linux-4.4.115/arch/arm64/boot/dts/include/dt-bindings/input/linux-event-codes.h linux-4.4.115-fbx/arch/arm64/boot/dts/include/dt-bindings/input/linux-event-codes.h --- linux-4.4.115/arch/arm64/boot/dts/include/dt-bindings/input/linux-event-codes.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/arch/arm64/boot/dts/include/dt-bindings/input/linux-event-codes.h 2019-10-29 09:26:25.545221791 +0100 @@ -611,6 +611,37 @@ #define KEY_KBDINPUTASSIST_ACCEPT 0x264 #define KEY_KBDINPUTASSIST_CANCEL 0x265 +/* Diagonal movement keys */ +#define KEY_RIGHT_UP 0x266 +#define KEY_RIGHT_DOWN 0x267 +#define KEY_LEFT_UP 0x268 +#define KEY_LEFT_DOWN 0x269 + +#define KEY_ROOT_MENU 0x26a /* Show Device's Root Menu */ +/* Show Top Menu of the Media (e.g. DVD) */ +#define KEY_MEDIA_TOP_MENU 0x26b +#define KEY_NUMERIC_11 0x26c +#define KEY_NUMERIC_12 0x26d +/* + * Toggle Audio Description: refers to an audio service that helps blind and + * visually impaired consumers understand the action in a program. Note: in + * some countries this is referred to as "Video Description". + */ +#define KEY_AUDIO_DESC 0x26e +#define KEY_3D_MODE 0x26f +#define KEY_NEXT_FAVORITE 0x270 +#define KEY_STOP_RECORD 0x271 +#define KEY_PAUSE_RECORD 0x272 +#define KEY_VOD 0x273 /* Video on Demand */ +#define KEY_UNMUTE 0x274 +#define KEY_FASTREVERSE 0x275 +#define KEY_SLOWREVERSE 0x276 +/* + * Control a data application associated with the currently viewed channel, + * e.g. teletext or data broadcast application (MHEG, MHP, HbbTV, etc.) + */ +#define KEY_DATA 0x275 + #define BTN_TRIGGER_HAPPY 0x2c0 #define BTN_TRIGGER_HAPPY1 0x2c0 #define BTN_TRIGGER_HAPPY2 0x2c1 @@ -653,6 +684,18 @@ #define BTN_TRIGGER_HAPPY39 0x2e6 #define BTN_TRIGGER_HAPPY40 0x2e7 +#define KEY_APP_TV 0x2f1 +#define KEY_APP_REPLAY 0x2f2 +#define KEY_APP_VIDEOCLUB 0x2f3 +#define KEY_APP_WHATSON 0x2f4 +#define KEY_APP_RECORDS 0x2f5 +#define KEY_APP_MEDIA 0x2f6 +#define KEY_APP_YOUTUBE 0x2f7 +#define KEY_APP_RADIOS 0x2f8 +#define KEY_APP_CANALVOD 0x2f9 +#define KEY_APP_PIP 0x2fa +#define KEY_APP_NETFLIX 0x2fb + /* We avoid low common keys in module aliases so they don't get huge. */ #define KEY_MIN_INTERESTING KEY_MUTE #define KEY_MAX 0x2ff @@ -749,7 +792,11 @@ #define SW_ROTATE_LOCK 0x0c /* set = rotate locked/disabled */ #define SW_LINEIN_INSERT 0x0d /* set = inserted */ #define SW_MUTE_DEVICE 0x0e /* set = device disabled */ -#define SW_MAX 0x0f +#define SW_HPHL_OVERCURRENT 0x0f /* set = over current on left hph */ +#define SW_HPHR_OVERCURRENT 0x10 /* set = over current on right hph */ +#define SW_MICROPHONE2_INSERT 0x11 /* set = inserted */ +#define SW_UNSUPPORT_INSERT 0x12 /* set = unsupported device inserted */ +#define SW_MAX 0x20 #define SW_CNT (SW_MAX+1) /* diff -ruw linux-4.4.115/arch/arm64/boot/dts/Makefile linux-4.4.115-fbx/arch/arm64/boot/dts/Makefile --- linux-4.4.115/arch/arm64/boot/dts/Makefile 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/arch/arm64/boot/dts/Makefile 2019-01-22 16:16:21.523228476 +0100 @@ -21,3 +21,4 @@ dtb-$(CONFIG_OF_ALL_DTBS) := $(patsubst $(dtstree)/%.dts,%.dtb, $(foreach d,$(dts-dirs), $(wildcard $(dtstree)/$(d)/*.dts))) always := $(dtb-y) +targets += dtbs diff -ruw linux-4.4.115/arch/arm64/boot/dts/qcom/Makefile linux-4.4.115-fbx/arch/arm64/boot/dts/qcom/Makefile --- linux-4.4.115/arch/arm64/boot/dts/qcom/Makefile 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/arch/arm64/boot/dts/qcom/Makefile 2019-10-29 09:26:22.901195917 +0100 @@ -1,5 +1,263 @@ -dtb-$(CONFIG_ARCH_QCOM) += apq8016-sbc.dtb msm8916-mtp.dtb +dtb-$(CONFIG_ARCH_MSM8996) += msm8996-v2-pmi8994-cdp.dtb \ + msm8996-v2-pmi8994-mtp.dtb \ + msm8996-v2-pmi8994-pmk8001-cdp.dtb \ + msm8996-v2-pmi8994-pmk8001-mtp.dtb \ + msm8996-v2-pmi8994-pm8004-cdp.dtb \ + msm8996-v2-pmi8994-pm8004-mtp.dtb \ + msm8996-v2-pmi8994-pm8004-pmk8001-cdp.dtb \ + msm8996-v2-pmi8994-pm8004-pmk8001-mtp.dtb \ + msm8996-v2-fluid.dtb \ + msm8996-v2-liquid.dtb \ + msm8996-v2-dtp.dtb \ + msm8996-v3-auto-cdp.dtb \ + msm8996-v3-auto-adp.dtb \ + msm8996-v3-pmi8994-cdp.dtb \ + msm8996-v3-pmi8994-mtp.dtb \ + msm8996-v3-pmi8994-pmk8001-cdp.dtb \ + msm8996-v3-pmi8994-pmk8001-mtp.dtb \ + msm8996-v3-pmi8994-pm8004-cdp.dtb \ + msm8996-v3-pmi8994-pm8004-mtp.dtb \ + msm8996-v3-pmi8994-pm8004-pmk8001-cdp.dtb \ + msm8996-v3-pmi8994-pm8004-pmk8001-mtp.dtb \ + msm8996-v3-pmi8996-cdp.dtb \ + msm8996-v3-pmi8996-mtp.dtb \ + msm8996-v3-pmi8996-pmk8001-cdp.dtb \ + msm8996-v3-pmi8996-pmk8001-mtp.dtb \ + msm8996-v3-fluid.dtb \ + msm8996-v3-liquid.dtb \ + msm8996-v3-dtp.dtb \ + msm8996-v3-pm8004-mmxf-adp.dtb \ + msm8996-v3-pm8004-agave-adp.dtb \ + msm8996-v3-pm8004-agave-adp-lite.dtb \ + msm8996pro-auto-adp.dtb \ + msm8996pro-auto-adp-lite.dtb \ + msm8996pro-auto-cdp.dtb \ + msm8996pro-auto-cv2x.dtb \ + msm8996pro-pmi8994-cdp.dtb \ + msm8996pro-pmi8994-mtp.dtb \ + msm8996pro-pmi8994-pmk8001-cdp.dtb \ + msm8996pro-pmi8994-pmk8001-mtp.dtb \ + msm8996pro-pmi8994-pm8004-cdp.dtb \ + msm8996pro-pmi8994-pm8004-mtp.dtb \ + msm8996pro-pmi8994-pm8004-pmk8001-cdp.dtb \ + msm8996pro-pmi8994-pm8004-pmk8001-mtp.dtb \ + msm8996pro-pmi8996-cdp.dtb \ + msm8996pro-pmi8996-mtp.dtb \ + msm8996pro-pmi8996-pmk8001-cdp.dtb \ + msm8996pro-pmi8996-pmk8001-mtp.dtb \ + msm8996pro-v1.1-auto-cdp.dtb \ + msm8996pro-v1.1-pmi8994-cdp.dtb \ + msm8996pro-v1.1-pmi8994-mtp.dtb \ + msm8996pro-v1.1-pmi8994-pmk8001-cdp.dtb \ + msm8996pro-v1.1-pmi8994-pmk8001-mtp.dtb \ + msm8996pro-v1.1-pmi8994-pm8004-cdp.dtb \ + msm8996pro-v1.1-pmi8994-pm8004-mtp.dtb \ + msm8996pro-v1.1-pmi8994-pm8004-pmk8001-cdp.dtb \ + msm8996pro-v1.1-pmi8994-pm8004-pmk8001-mtp.dtb \ + msm8996pro-v1.1-pmi8996-cdp.dtb \ + msm8996pro-v1.1-pmi8996-mtp.dtb \ + msm8996pro-v1.1-pmi8996-pmk8001-cdp.dtb \ + msm8996pro-v1.1-pmi8996-pmk8001-mtp.dtb \ + apq8096pro-auto-cdp.dtb \ + apq8096pro-v1.1-auto-adp.dtb \ + apq8096pro-v1.1-auto-adp-lite.dtb \ + apq8096pro-liquid.dtb \ + apq8096pro-v1.1-auto-cdp.dtb \ + msm8996-v3.0-pmi8994-cdp.dtb \ + msm8996-v3.0-pmi8994-mtp.dtb \ + msm8996-v3.0-pmi8994-pm8004-cdp.dtb \ + msm8996-v3.0-pmi8994-pm8004-mtp.dtb \ + msm8996-v3.0-pmi8994-pm8004-pmk8001-cdp.dtb \ + msm8996-v3.0-pmi8994-pmk8001-cdp.dtb \ + msm8996-v3.0-pmi8996-cdp.dtb \ + msm8996-v3.0-pmi8996-mtp.dtb \ + msm8996-v3.0-fluid.dtb \ + msm8996-v3.0-liquid.dtb \ + msm8996-v3.0-dtp.dtb \ + apq8096-v2-pmi8994-cdp.dtb \ + apq8096-v2-pmi8994-mtp.dtb \ + apq8096-v2-pmi8994-pmk8001-cdp.dtb \ + apq8096-v2-pmi8994-pm8004-cdp.dtb \ + apq8096-v2-pmi8994-pm8004-pmk8001-cdp.dtb \ + apq8096-v2-liquid.dtb \ + apq8096-v2-dragonboard.dtb \ + apq8096-v2-auto-dragonboard.dtb \ + apq8096-v3-pmi8994-cdp.dtb \ + apq8096-v3-pmi8994-mtp.dtb \ + apq8096-v3-pmi8994-pmk8001-cdp.dtb \ + apq8096-v3-pmi8994-pm8004-cdp.dtb \ + apq8096-v3-pmi8994-pm8004-pmk8001-cdp.dtb \ + apq8096-v3-pmi8996-cdp.dtb \ + apq8096-v3-pmi8996-mtp.dtb \ + apq8096-v3-liquid.dtb \ + apq8096-v3-dragonboard.dtb \ + apq8096-v3-sbc.dtb \ + apq8096-v3-auto-dragonboard.dtb \ + apq8096-v3-auto-adp.dtb \ + apq8096-v3-auto-cdp.dtb \ + apq8096-v3.0-pmi8994-cdp.dtb \ + apq8096-v3.0-pmi8994-mtp.dtb \ + apq8096-v3.0-pmi8994-pm8004-cdp.dtb \ + apq8096-v3.0-pmi8994-pm8004-pmk8001-cdp.dtb \ + apq8096-v3.0-pmi8994-pmk8001-cdp.dtb \ + apq8096-v3.0-pmi8996-cdp.dtb \ + apq8096-v3.0-pmi8996-mtp.dtb \ + apq8096-v3.0-liquid.dtb \ + apq8096-v3.0-dragonboard.dtb \ + apq8096-v3-pmi8994-mdm9x55-i2s-cdp.dtb \ + apq8096-v3-pmi8994-pm8004-mdm9x55-i2s-cdp.dtb \ + apq8096-v3-pmi8994-pm8004-pmk8001-mdm9x55-i2s-cdp.dtb \ + apq8096-v3-pmi8994-pmk8001-mdm9x55-i2s-cdp.dtb \ + apq8096-v3-pmi8996-mdm9x55-i2s-cdp.dtb \ + apq8096-v3-pmi8994-mdm9x55-i2s-mtp.dtb \ + apq8096-v3-pmi8994-mdm9x55-slimbus-mtp.dtb \ + apq8096-v3-pmi8996-mdm9x55-i2s-mtp.dtb \ + apq8096-v3-pmi8996-mdm9x55-slimbus-mtp.dtb \ + apq8096-v3-pmi8996-dragonboard.dtb \ + msm8996-auto-mizar.dtb -always := $(dtb-y) +dtb-$(CONFIG_MSM_GVM_QUIN) += vplatform-lfv-msm8996-telematics.dtb \ + vplatform-lfv-msm8996-ivi.dtb \ + vplatform-lfv-msm8996-baseline.dtb \ + vplatform-lfv-msm8996-ivi-la.dtb \ + vplatform-lfv-msm8996-ivi-lv-mt.dtb + +dtb-$(CONFIG_ARCH_MSM8998) += \ + apq8098-v2.1-mediabox.dtb \ + apq8098-freebox-proto.dtb \ + apq8098-freebox-oarfish.dtb \ + apq8098-freebox-batfish.dtb + +dtb-$(CONFIG_ARCH_MSMHAMSTER) += msmhamster-rumi.dtb + +dtb-$(CONFIG_ARCH_SDM660) += sdm660-sim.dtb \ + sdm660-internal-codec-cdp.dtb \ + sdm660-internal-codec-mtp.dtb \ + sdm660-internal-codec-rcm.dtb \ + sdm660-cdp.dtb \ + sdm660-mtp.dtb \ + sdm660-qrd.dtb \ + sdm660-rcm.dtb \ + sdm660-rumi.dtb \ + sdm660-pm660a-cdp.dtb \ + sdm660-pm660a-mtp.dtb \ + sdm660-pm660a-qrd.dtb \ + sdm660-pm660a-rcm.dtb \ + sdm660-pm660a-rumi.dtb \ + sdm660-internal-codec-pm660a-cdp.dtb \ + sdm660-internal-codec-pm660a-mtp.dtb \ + sdm660-internal-codec-pm660a-rcm.dtb \ + sdm660-pm660a-sim.dtb \ + sda660-cdp.dtb \ + sda660-mtp.dtb \ + sda660-rcm.dtb \ + sda660-pm660a-cdp.dtb \ + sda660-pm660a-mtp.dtb \ + sda660-pm660a-rcm.dtb \ + sda660-pm660a-qrd-hdk.dtb \ + sdm660-headset-jacktype-no-cdp.dtb \ + sdm660-headset-jacktype-no-rcm.dtb \ + sdm660-pm660a-headset-jacktype-no-cdp.dtb \ + sdm660-pm660a-headset-jacktype-no-rcm.dtb \ + sdm660-usbc-audio-mtp.dtb \ + sdm660-usbc-audio-rcm.dtb \ + sdm660-fhd-cdp.dtb \ + sdm660-pm660a-fhd-cdp.dtb \ + sdm658-mtp.dtb \ + sdm658-cdp.dtb \ + sdm658-rcm.dtb \ + sdm658-qrd.dtb \ + sdm658-pm660a-mtp.dtb \ + sdm658-pm660a-cdp.dtb \ + sdm658-pm660a-rcm.dtb \ + sdm658-pm660a-qrd.dtb \ + sdm658-internal-codec-mtp.dtb \ + sdm658-internal-codec-cdp.dtb \ + sdm658-internal-codec-rcm.dtb \ + sdm658-internal-codec-pm660a-mtp.dtb \ + sdm658-internal-codec-pm660a-cdp.dtb \ + sdm658-internal-codec-pm660a-rcm.dtb \ + sda658-cdp.dtb \ + sda658-mtp.dtb \ + sda658-rcm.dtb \ + sda658-pm660a-mtp.dtb \ + sda658-pm660a-cdp.dtb \ + sda658-pm660a-rcm.dtb \ + sdm636-cdp.dtb \ + sdm636-mtp.dtb \ + sdm636-qrd.dtb \ + sdm636-rcm.dtb \ + sdm636-headset-jacktype-no-cdp.dtb \ + sdm636-headset-jacktype-no-rcm.dtb \ + sdm636-internal-codec-cdp.dtb \ + sdm636-internal-codec-mtp.dtb \ + sdm636-internal-codec-pm660a-cdp.dtb \ + sdm636-internal-codec-pm660a-mtp.dtb \ + sdm636-internal-codec-pm660a-rcm.dtb \ + sdm636-internal-codec-rcm.dtb \ + sdm636-pm660a-headset-jacktype-no-cdp.dtb \ + sdm636-pm660a-headset-jacktype-no-rcm.dtb \ + sdm636-pm660a-cdp.dtb \ + sdm636-pm660a-mtp.dtb \ + sdm636-pm660a-qrd.dtb \ + sdm636-pm660a-rcm.dtb \ + sdm636-usbc-audio-mtp.dtb \ + sdm636-usbc-audio-rcm.dtb \ + sda636-cdp.dtb \ + sda636-mtp.dtb \ + sda636-rcm.dtb \ + sda636-pm660a-cdp.dtb \ + sda636-pm660a-mtp.dtb \ + sda636-pm660a-qrd-hdk.dtb \ + sda636-pm660a-rcm.dtb + +dtb-$(CONFIG_ARCH_SDM630) += sdm630-rumi.dtb \ + sdm630-pm660a-rumi.dtb \ + sdm630-mtp.dtb \ + sdm630-usbc-audio-mtp.dtb \ + sdm630-usbc-audio-rcm.dtb \ + sdm630-cdp.dtb \ + sdm630-rcm.dtb \ + sdm630-internal-codec-mtp.dtb \ + sdm630-internal-codec-cdp.dtb \ + sdm630-internal-codec-rcm.dtb \ + sdm630-pm660a-cdp.dtb \ + sdm630-pm660a-mtp.dtb \ + sdm630-pm660a-rcm.dtb \ + sdm630-pm660a-qrd.dtb \ + sdm630-internal-codec-pm660a-cdp.dtb \ + sdm630-internal-codec-pm660a-mtp.dtb \ + sdm630-internal-codec-pm660a-rcm.dtb \ + sda630-mtp.dtb \ + sda630-cdp.dtb \ + sda630-rcm.dtb \ + sda630-pm660a-mtp.dtb \ + sda630-pm660a-cdp.dtb \ + sda630-pm660a-rcm.dtb \ + sda630-pm660a-qrd-hdk.dtb \ + sdm630-headset-jacktype-no-cdp.dtb \ + sdm630-headset-jacktype-no-rcm.dtb \ + sdm630-pm660a-headset-jacktype-no-cdp.dtb \ + sdm630-pm660a-headset-jacktype-no-rcm.dtb + +ifeq ($(CONFIG_ARM64),y) +always := $(dtb-y) qcom_dtbs +always += $(dtbo-y) subdir-y := $(dts-dirs) -clean-files := *.dtb +else +targets += dtbs +targets += $(addprefix ../, $(dtb-y)) + +$(obj)/../%.dtb: $(src)/%.dts FORCE + $(call if_changed_dep,dtc) + +dtbs: $(addprefix $(obj)/../,$(dtb-y)) +endif +clean-files := *.dtbo *.dtb qcom_dtbs qcom_dtbs.cmpxz + +cmd_dtbs = ./scripts/dtbs.sh $@ $^ +quiet_cmd_dtbs = DTBS $@ + +DTB_ALIGN=32 +$(obj)/qcom_dtbs: $(addprefix $(obj)/,$(dtb-y)) + $(call cmd,dtbs) diff -ruw linux-4.4.115/arch/arm64/boot/Makefile linux-4.4.115-fbx/arch/arm64/boot/Makefile --- linux-4.4.115/arch/arm64/boot/Makefile 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/arch/arm64/boot/Makefile 2019-01-22 16:16:21.523228476 +0100 @@ -16,12 +16,23 @@ targets := Image Image.gz +DTB_NAMES := $(subst $\",,$(CONFIG_BUILD_ARM64_APPENDED_DTB_IMAGE_NAMES)) +ifneq ($(DTB_NAMES),) +DTB_LIST := $(addsuffix .dtb,$(DTB_NAMES)) +DTB_OBJS := $(addprefix $(obj)/dts/,$(DTB_LIST)) +else +DTB_OBJS := $(shell find -L $(obj)/dts/ -name \*.dtb) +endif + $(obj)/Image: vmlinux FORCE $(call if_changed,objcopy) $(obj)/Image.bz2: $(obj)/Image FORCE $(call if_changed,bzip2) +$(obj)/Image-dtb: $(obj)/Image $(DTB_OBJS) FORCE + $(call if_changed,cat) + $(obj)/Image.gz: $(obj)/Image FORCE $(call if_changed,gzip) @@ -34,6 +45,9 @@ $(obj)/Image.lzo: $(obj)/Image FORCE $(call if_changed,lzo) +$(obj)/Image.gz-dtb: $(obj)/Image.gz $(DTB_OBJS) FORCE + $(call if_changed,cat) + install: $(obj)/Image $(CONFIG_SHELL) $(srctree)/$(src)/install.sh $(KERNELRELEASE) \ $(obj)/Image System.map "$(INSTALL_PATH)" diff -ruw linux-4.4.115/arch/arm64/crypto/aes-glue.c linux-4.4.115-fbx/arch/arm64/crypto/aes-glue.c --- linux-4.4.115/arch/arm64/crypto/aes-glue.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/arch/arm64/crypto/aes-glue.c 2019-01-22 16:16:21.535228585 +0100 @@ -294,7 +294,7 @@ .cra_blkcipher = { .min_keysize = AES_MIN_KEY_SIZE, .max_keysize = AES_MAX_KEY_SIZE, - .ivsize = AES_BLOCK_SIZE, + .ivsize = 0, .setkey = aes_setkey, .encrypt = ecb_encrypt, .decrypt = ecb_decrypt, @@ -371,7 +371,7 @@ .cra_ablkcipher = { .min_keysize = AES_MIN_KEY_SIZE, .max_keysize = AES_MAX_KEY_SIZE, - .ivsize = AES_BLOCK_SIZE, + .ivsize = 0, .setkey = ablk_set_key, .encrypt = ablk_encrypt, .decrypt = ablk_decrypt, diff -ruw linux-4.4.115/arch/arm64/crypto/Kconfig linux-4.4.115-fbx/arch/arm64/crypto/Kconfig --- linux-4.4.115/arch/arm64/crypto/Kconfig 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/arch/arm64/crypto/Kconfig 2019-01-22 16:16:21.531228549 +0100 @@ -23,6 +23,11 @@ depends on ARM64 && KERNEL_MODE_NEON select CRYPTO_HASH +config CRYPTO_POLY_HASH_ARM64_CE + tristate "poly_hash (for HEH encryption mode) using ARMv8 Crypto Extensions" + depends on ARM64 && KERNEL_MODE_NEON + select CRYPTO_HASH + config CRYPTO_AES_ARM64_CE tristate "AES core cipher using ARMv8 Crypto Extensions" depends on ARM64 && KERNEL_MODE_NEON diff -ruw linux-4.4.115/arch/arm64/crypto/Makefile linux-4.4.115-fbx/arch/arm64/crypto/Makefile --- linux-4.4.115/arch/arm64/crypto/Makefile 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/arch/arm64/crypto/Makefile 2019-01-22 16:16:21.531228549 +0100 @@ -17,6 +17,9 @@ obj-$(CONFIG_CRYPTO_GHASH_ARM64_CE) += ghash-ce.o ghash-ce-y := ghash-ce-glue.o ghash-ce-core.o +obj-$(CONFIG_CRYPTO_POLY_HASH_ARM64_CE) += poly-hash-ce.o +poly-hash-ce-y := poly-hash-ce-glue.o poly-hash-ce-core.o + obj-$(CONFIG_CRYPTO_AES_ARM64_CE) += aes-ce-cipher.o CFLAGS_aes-ce-cipher.o += -march=armv8-a+crypto diff -ruw linux-4.4.115/arch/arm64/crypto/sha1-ce-core.S linux-4.4.115-fbx/arch/arm64/crypto/sha1-ce-core.S --- linux-4.4.115/arch/arm64/crypto/sha1-ce-core.S 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/arch/arm64/crypto/sha1-ce-core.S 2019-01-22 16:16:21.535228585 +0100 @@ -82,7 +82,8 @@ ldr dgb, [x0, #16] /* load sha1_ce_state::finalize */ - ldr w4, [x0, #:lo12:sha1_ce_offsetof_finalize] + ldr_l w4, sha1_ce_offsetof_finalize, x4 + ldr w4, [x0, x4] /* load input */ 0: ld1 {v8.4s-v11.4s}, [x1], #64 @@ -132,7 +133,8 @@ * the padding is handled by the C code in that case. */ cbz x4, 3f - ldr x4, [x0, #:lo12:sha1_ce_offsetof_count] + ldr_l w4, sha1_ce_offsetof_count, x4 + ldr x4, [x0, x4] movi v9.2d, #0 mov x8, #0x80000000 movi v10.2d, #0 diff -ruw linux-4.4.115/arch/arm64/crypto/sha1-ce-glue.c linux-4.4.115-fbx/arch/arm64/crypto/sha1-ce-glue.c --- linux-4.4.115/arch/arm64/crypto/sha1-ce-glue.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/arch/arm64/crypto/sha1-ce-glue.c 2019-10-29 09:26:22.993196817 +0100 @@ -17,9 +17,6 @@ #include #include -#define ASM_EXPORT(sym, val) \ - asm(".globl " #sym "; .set " #sym ", %0" :: "I"(val)); - MODULE_DESCRIPTION("SHA1 secure hash using ARMv8 Crypto Extensions"); MODULE_AUTHOR("Ard Biesheuvel "); MODULE_LICENSE("GPL v2"); @@ -32,6 +29,9 @@ asmlinkage void sha1_ce_transform(struct sha1_ce_state *sst, u8 const *src, int blocks); +const u32 sha1_ce_offsetof_count = offsetof(struct sha1_ce_state, sst.count); +const u32 sha1_ce_offsetof_finalize = offsetof(struct sha1_ce_state, finalize); + static int sha1_ce_update(struct shash_desc *desc, const u8 *data, unsigned int len) { @@ -52,11 +52,6 @@ struct sha1_ce_state *sctx = shash_desc_ctx(desc); bool finalize = !sctx->sst.count && !(len % SHA1_BLOCK_SIZE); - ASM_EXPORT(sha1_ce_offsetof_count, - offsetof(struct sha1_ce_state, sst.count)); - ASM_EXPORT(sha1_ce_offsetof_finalize, - offsetof(struct sha1_ce_state, finalize)); - /* * Allow the asm code to perform the finalization if there is no * partial data and the input is a round multiple of the block size. diff -ruw linux-4.4.115/arch/arm64/crypto/sha2-ce-core.S linux-4.4.115-fbx/arch/arm64/crypto/sha2-ce-core.S --- linux-4.4.115/arch/arm64/crypto/sha2-ce-core.S 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/arch/arm64/crypto/sha2-ce-core.S 2019-01-22 16:16:21.535228585 +0100 @@ -88,7 +88,8 @@ ld1 {dgav.4s, dgbv.4s}, [x0] /* load sha256_ce_state::finalize */ - ldr w4, [x0, #:lo12:sha256_ce_offsetof_finalize] + ldr_l w4, sha256_ce_offsetof_finalize, x4 + ldr w4, [x0, x4] /* load input */ 0: ld1 {v16.4s-v19.4s}, [x1], #64 @@ -136,7 +137,8 @@ * the padding is handled by the C code in that case. */ cbz x4, 3f - ldr x4, [x0, #:lo12:sha256_ce_offsetof_count] + ldr_l w4, sha256_ce_offsetof_count, x4 + ldr x4, [x0, x4] movi v17.2d, #0 mov x8, #0x80000000 movi v18.2d, #0 diff -ruw linux-4.4.115/arch/arm64/crypto/sha2-ce-glue.c linux-4.4.115-fbx/arch/arm64/crypto/sha2-ce-glue.c --- linux-4.4.115/arch/arm64/crypto/sha2-ce-glue.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/arch/arm64/crypto/sha2-ce-glue.c 2019-10-29 09:26:22.993196817 +0100 @@ -17,9 +17,6 @@ #include #include -#define ASM_EXPORT(sym, val) \ - asm(".globl " #sym "; .set " #sym ", %0" :: "I"(val)); - MODULE_DESCRIPTION("SHA-224/SHA-256 secure hash using ARMv8 Crypto Extensions"); MODULE_AUTHOR("Ard Biesheuvel "); MODULE_LICENSE("GPL v2"); @@ -32,6 +29,11 @@ asmlinkage void sha2_ce_transform(struct sha256_ce_state *sst, u8 const *src, int blocks); +const u32 sha256_ce_offsetof_count = offsetof(struct sha256_ce_state, + sst.count); +const u32 sha256_ce_offsetof_finalize = offsetof(struct sha256_ce_state, + finalize); + static int sha256_ce_update(struct shash_desc *desc, const u8 *data, unsigned int len) { @@ -52,11 +54,6 @@ struct sha256_ce_state *sctx = shash_desc_ctx(desc); bool finalize = !sctx->sst.count && !(len % SHA256_BLOCK_SIZE); - ASM_EXPORT(sha256_ce_offsetof_count, - offsetof(struct sha256_ce_state, sst.count)); - ASM_EXPORT(sha256_ce_offsetof_finalize, - offsetof(struct sha256_ce_state, finalize)); - /* * Allow the asm code to perform the finalization if there is no * partial data and the input is a round multiple of the block size. diff -ruw linux-4.4.115/arch/arm64/include/asm/acpi.h linux-4.4.115-fbx/arch/arm64/include/asm/acpi.h --- linux-4.4.115/arch/arm64/include/asm/acpi.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/arch/arm64/include/asm/acpi.h 2019-01-22 16:16:21.535228585 +0100 @@ -87,9 +87,26 @@ static inline void acpi_init_cpus(void) { } #endif /* CONFIG_ACPI */ +#ifdef CONFIG_ARM64_ACPI_PARKING_PROTOCOL +bool acpi_parking_protocol_valid(int cpu); +void __init +acpi_set_mailbox_entry(int cpu, struct acpi_madt_generic_interrupt *processor); +#else +static inline bool acpi_parking_protocol_valid(int cpu) { return false; } +static inline void +acpi_set_mailbox_entry(int cpu, struct acpi_madt_generic_interrupt *processor) +{} +#endif + static inline const char *acpi_get_enable_method(int cpu) { - return acpi_psci_present() ? "psci" : NULL; + if (acpi_psci_present()) + return "psci"; + + if (acpi_parking_protocol_valid(cpu)) + return "parking-protocol"; + + return NULL; } #ifdef CONFIG_ACPI_APEI diff -ruw linux-4.4.115/arch/arm64/include/asm/alternative.h linux-4.4.115-fbx/arch/arm64/include/asm/alternative.h --- linux-4.4.115/arch/arm64/include/asm/alternative.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/arch/arm64/include/asm/alternative.h 2019-01-22 16:16:21.535228585 +0100 @@ -1,6 +1,9 @@ #ifndef __ASM_ALTERNATIVE_H #define __ASM_ALTERNATIVE_H +#include +#include + #ifndef __ASSEMBLY__ #include @@ -19,7 +22,6 @@ void __init apply_alternatives_all(void); void apply_alternatives(void *start, size_t length); -void free_alternatives_memory(void); #define ALTINSTR_ENTRY(feature) \ " .word 661b - .\n" /* label */ \ @@ -64,6 +66,8 @@ #else +#include + .macro altinstruction_entry orig_offset alt_offset feature orig_len alt_len .word \orig_offset - . .word \alt_offset - . @@ -87,55 +91,147 @@ .endm /* - * Begin an alternative code sequence. + * Alternative sequences + * + * The code for the case where the capability is not present will be + * assembled and linked as normal. There are no restrictions on this + * code. + * + * The code for the case where the capability is present will be + * assembled into a special section to be used for dynamic patching. + * Code for that case must: * - * The code that follows this macro will be assembled and linked as - * normal. There are no restrictions on this code. + * 1. Be exactly the same length (in bytes) as the default code + * sequence. + * + * 2. Not contain a branch target that is used outside of the + * alternative sequence it is defined in (branches into an + * alternative sequence are not fixed up). */ -.macro alternative_if_not cap, enable = 1 - .if \enable + +/* + * Begin an alternative code sequence. + */ +.macro alternative_if_not cap + .set .Lasm_alt_mode, 0 .pushsection .altinstructions, "a" altinstruction_entry 661f, 663f, \cap, 662f-661f, 664f-663f .popsection 661: - .endif +.endm + +.macro alternative_if cap + .set .Lasm_alt_mode, 1 + .pushsection .altinstructions, "a" + altinstruction_entry 663f, 661f, \cap, 664f-663f, 662f-661f + .popsection + .pushsection .altinstr_replacement, "ax" + .align 2 /* So GAS knows label 661 is suitably aligned */ +661: .endm /* - * Provide the alternative code sequence. - * - * The code that follows this macro is assembled into a special - * section to be used for dynamic patching. Code that follows this - * macro must: - * - * 1. Be exactly the same length (in bytes) as the default code - * sequence. - * - * 2. Not contain a branch target that is used outside of the - * alternative sequence it is defined in (branches into an - * alternative sequence are not fixed up). + * Provide the other half of the alternative code sequence. */ -.macro alternative_else, enable = 1 - .if \enable -662: .pushsection .altinstr_replacement, "ax" -663: +.macro alternative_else +662: + .if .Lasm_alt_mode==0 + .pushsection .altinstr_replacement, "ax" + .else + .popsection .endif +663: .endm /* * Complete an alternative code sequence. */ -.macro alternative_endif, enable = 1 - .if \enable -664: .popsection +.macro alternative_endif +664: + .if .Lasm_alt_mode==0 + .popsection + .endif .org . - (664b-663b) + (662b-661b) .org . - (662b-661b) + (664b-663b) - .endif +.endm + +/* + * Provides a trivial alternative or default sequence consisting solely + * of NOPs. The number of NOPs is chosen automatically to match the + * previous case. + */ +.macro alternative_else_nop_endif +alternative_else + nops (662b-661b) / AARCH64_INSN_SIZE +alternative_endif .endm #define _ALTERNATIVE_CFG(insn1, insn2, cap, cfg, ...) \ alternative_insn insn1, insn2, cap, IS_ENABLED(cfg) +.macro user_alt, label, oldinstr, newinstr, cond +9999: alternative_insn "\oldinstr", "\newinstr", \cond + _ASM_EXTABLE 9999b, \label +.endm + +/* + * Generate the assembly for UAO alternatives with exception table entries. + * This is complicated as there is no post-increment or pair versions of the + * unprivileged instructions, and USER() only works for single instructions. + */ +#ifdef CONFIG_ARM64_UAO + .macro uao_ldp l, reg1, reg2, addr, post_inc + alternative_if_not ARM64_HAS_UAO +8888: ldp \reg1, \reg2, [\addr], \post_inc; +8889: nop; + nop; + alternative_else + ldtr \reg1, [\addr]; + ldtr \reg2, [\addr, #8]; + add \addr, \addr, \post_inc; + alternative_endif + + _asm_extable 8888b,\l; + _asm_extable 8889b,\l; + .endm + + .macro uao_stp l, reg1, reg2, addr, post_inc + alternative_if_not ARM64_HAS_UAO +8888: stp \reg1, \reg2, [\addr], \post_inc; +8889: nop; + nop; + alternative_else + sttr \reg1, [\addr]; + sttr \reg2, [\addr, #8]; + add \addr, \addr, \post_inc; + alternative_endif + + _asm_extable 8888b,\l; + _asm_extable 8889b,\l; + .endm + + .macro uao_user_alternative l, inst, alt_inst, reg, addr, post_inc + alternative_if_not ARM64_HAS_UAO +8888: \inst \reg, [\addr], \post_inc; + nop; + alternative_else + \alt_inst \reg, [\addr]; + add \addr, \addr, \post_inc; + alternative_endif + + _asm_extable 8888b,\l; + .endm +#else + .macro uao_ldp l, reg1, reg2, addr, post_inc + USER(\l, ldp \reg1, \reg2, [\addr], \post_inc) + .endm + .macro uao_stp l, reg1, reg2, addr, post_inc + USER(\l, stp \reg1, \reg2, [\addr], \post_inc) + .endm + .macro uao_user_alternative l, inst, alt_inst, reg, addr, post_inc + USER(\l, \inst \reg, [\addr], \post_inc) + .endm +#endif #endif /* __ASSEMBLY__ */ diff -ruw linux-4.4.115/arch/arm64/include/asm/arch_gicv3.h linux-4.4.115-fbx/arch/arm64/include/asm/arch_gicv3.h --- linux-4.4.115/arch/arm64/include/asm/arch_gicv3.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/arch/arm64/include/asm/arch_gicv3.h 2019-01-22 16:16:21.535228585 +0100 @@ -103,7 +103,8 @@ u64 irqstat; asm volatile("mrs_s %0, " __stringify(ICC_IAR1_EL1) : "=r" (irqstat)); - dsb(sy); + /* As per the architecture specification */ + mb(); return irqstat; } @@ -132,6 +133,9 @@ static inline void gic_write_pmr(u32 val) { asm volatile("msr_s " __stringify(ICC_PMR_EL1) ", %0" : : "r" ((u64)val)); + /* As per the architecture specification */ + isb(); + mb(); } static inline void gic_write_ctlr(u32 val) @@ -149,6 +153,9 @@ static inline void gic_write_sgi1r(u64 val) { asm volatile("msr_s " __stringify(ICC_SGI1R_EL1) ", %0" : : "r" (val)); + /* As per the architecture specification */ + isb(); + mb(); } static inline u32 gic_read_sre(void) @@ -165,8 +172,8 @@ isb(); } -#define gic_read_typer(c) readq_relaxed(c) -#define gic_write_irouter(v, c) writeq_relaxed(v, c) +#define gic_read_typer(c) readq_relaxed_no_log(c) +#define gic_write_irouter(v, c) writeq_relaxed_no_log(v, c) #endif /* __ASSEMBLY__ */ #endif /* __ASM_ARCH_GICV3_H */ diff -ruw linux-4.4.115/arch/arm64/include/asm/arch_timer.h linux-4.4.115-fbx/arch/arm64/include/asm/arch_timer.h --- linux-4.4.115/arch/arm64/include/asm/arch_timer.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/arch/arm64/include/asm/arch_timer.h 2019-01-22 16:16:21.535228585 +0100 @@ -119,7 +119,14 @@ u64 cval; isb(); +#if IS_ENABLED(CONFIG_MSM_TIMER_LEAP) +#define L32_BITS 0x00000000FFFFFFFF + do { asm volatile("mrs %0, cntvct_el0" : "=r" (cval)); + } while ((cval & L32_BITS) == L32_BITS); +#else + asm volatile("mrs %0, cntvct_el0" : "=r" (cval)); +#endif return cval; } diff -ruw linux-4.4.115/arch/arm64/include/asm/assembler.h linux-4.4.115-fbx/arch/arm64/include/asm/assembler.h --- linux-4.4.115/arch/arm64/include/asm/assembler.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/arch/arm64/include/asm/assembler.h 2019-10-29 09:26:22.993196817 +0100 @@ -1,5 +1,5 @@ /* - * Based on arch/arm/include/asm/assembler.h + * Based on arch/arm/include/asm/assembler.h, arch/arm/mm/proc-macros.S * * Copyright (C) 1996-2000 Russell King * Copyright (C) 2012 ARM Ltd. @@ -23,6 +23,10 @@ #ifndef __ASM_ASSEMBLER_H #define __ASM_ASSEMBLER_H +#include +#include +#include +#include #include #include @@ -49,6 +53,27 @@ msr daifclr, #2 .endm + .macro save_and_disable_irq, flags + mrs \flags, daif + msr daifset, #2 + .endm + + .macro restore_irq, flags + msr daif, \flags + .endm + +/* + * Save/disable and restore interrupts. + */ + .macro save_and_disable_irqs, olddaif + mrs \olddaif, daif + disable_irq + .endm + + .macro restore_irqs, olddaif + msr daif, \olddaif + .endm + /* * Enable and disable debug exceptions. */ @@ -94,12 +119,28 @@ dmb \opt .endm +/* + * NOP sequence + */ + .macro nops, num + .rept \num + nop + .endr + .endm + +/* + * Emit an entry into the exception table + */ + .macro _asm_extable, from, to + .pushsection __ex_table, "a" + .align 3 + .long (\from - .), (\to - .) + .popsection + .endm + #define USER(l, x...) \ 9999: x; \ - .section __ex_table,"a"; \ - .align 3; \ - .quad 9999b,l; \ - .previous + _asm_extable 9999b, l /* * Register aliases. @@ -194,6 +235,133 @@ .endm /* + * @dst: Result of per_cpu(sym, smp_processor_id()) + * @sym: The name of the per-cpu variable + * @tmp: scratch register + */ + .macro adr_this_cpu, dst, sym, tmp + adr_l \dst, \sym + mrs \tmp, tpidr_el1 + add \dst, \dst, \tmp + .endm + + /* + * @dst: Result of READ_ONCE(per_cpu(sym, smp_processor_id())) + * @sym: The name of the per-cpu variable + * @tmp: scratch register + */ + .macro ldr_this_cpu dst, sym, tmp + adr_l \dst, \sym + mrs \tmp, tpidr_el1 + ldr \dst, [\dst, \tmp] + .endm + +/* + * vma_vm_mm - get mm pointer from vma pointer (vma->vm_mm) + */ + .macro vma_vm_mm, rd, rn + ldr \rd, [\rn, #VMA_VM_MM] + .endm + +/* + * mmid - get context id from mm pointer (mm->context.id) + */ + .macro mmid, rd, rn + ldr \rd, [\rn, #MM_CONTEXT_ID] + .endm + +/* + * dcache_line_size - get the minimum D-cache line size from the CTR register. + */ + .macro dcache_line_size, reg, tmp + mrs \tmp, ctr_el0 // read CTR + ubfm \tmp, \tmp, #16, #19 // cache line size encoding + mov \reg, #4 // bytes per word + lsl \reg, \reg, \tmp // actual cache line size + .endm + +/* + * icache_line_size - get the minimum I-cache line size from the CTR register. + */ + .macro icache_line_size, reg, tmp + mrs \tmp, ctr_el0 // read CTR + and \tmp, \tmp, #0xf // cache line size encoding + mov \reg, #4 // bytes per word + lsl \reg, \reg, \tmp // actual cache line size + .endm + +/* + * tcr_set_idmap_t0sz - update TCR.T0SZ so that we can load the ID map + */ + .macro tcr_set_idmap_t0sz, valreg, tmpreg +#ifndef CONFIG_ARM64_VA_BITS_48 + ldr_l \tmpreg, idmap_t0sz + bfi \valreg, \tmpreg, #TCR_T0SZ_OFFSET, #TCR_TxSZ_WIDTH +#endif + .endm + +/* + * Macro to perform a data cache maintenance for the interval + * [kaddr, kaddr + size) + * + * op: operation passed to dc instruction + * domain: domain used in dsb instruciton + * kaddr: starting virtual address of the region + * size: size of the region + * Corrupts: kaddr, size, tmp1, tmp2 + */ + .macro dcache_by_line_op op, domain, kaddr, size, tmp1, tmp2 + dcache_line_size \tmp1, \tmp2 + add \size, \kaddr, \size + sub \tmp2, \tmp1, #1 + bic \kaddr, \kaddr, \tmp2 +9998: + .if (\op == cvau || \op == cvac) +alternative_if_not ARM64_WORKAROUND_CLEAN_CACHE + dc \op, \kaddr +alternative_else + dc civac, \kaddr +alternative_endif + .else + dc \op, \kaddr + .endif + add \kaddr, \kaddr, \tmp1 + cmp \kaddr, \size + b.lo 9998b + dsb \domain + .endm + +/* + * reset_pmuserenr_el0 - reset PMUSERENR_EL0 if PMUv3 present + */ + .macro reset_pmuserenr_el0, tmpreg + mrs \tmpreg, id_aa64dfr0_el1 // Check ID_AA64DFR0_EL1 PMUVer + sbfx \tmpreg, \tmpreg, #8, #4 + cmp \tmpreg, #1 // Skip if no PMU present + b.lt 9000f + msr pmuserenr_el0, xzr // Disable PMU access from EL0 +9000: + .endm + +/* + * copy_page - copy src to dest using temp registers t1-t8 + */ + .macro copy_page dest:req src:req t1:req t2:req t3:req t4:req t5:req t6:req t7:req t8:req +9998: ldp \t1, \t2, [\src] + ldp \t3, \t4, [\src, #16] + ldp \t5, \t6, [\src, #32] + ldp \t7, \t8, [\src, #48] + add \src, \src, #64 + stnp \t1, \t2, [\dest] + stnp \t3, \t4, [\dest, #16] + stnp \t5, \t6, [\dest, #32] + stnp \t7, \t8, [\dest, #48] + add \dest, \dest, #64 + tst \src, #(PAGE_SIZE - 1) + b.ne 9998b + .endm + +/* * Annotate a function as position independent, i.e., safe to be called before * the kernel virtual mapping is activated. */ @@ -204,4 +372,42 @@ .size __pi_##x, . - x; \ ENDPROC(x) + /* + * Emit a 64-bit absolute little endian symbol reference in a way that + * ensures that it will be resolved at build time, even when building a + * PIE binary. This requires cooperation from the linker script, which + * must emit the lo32/hi32 halves individually. + */ + .macro le64sym, sym + .long \sym\()_lo32 + .long \sym\()_hi32 + .endm + + /* + * mov_q - move an immediate constant into a 64-bit register using + * between 2 and 4 movz/movk instructions (depending on the + * magnitude and sign of the operand) + */ + .macro mov_q, reg, val + .if (((\val) >> 31) == 0 || ((\val) >> 31) == 0x1ffffffff) + movz \reg, :abs_g1_s:\val + .else + .if (((\val) >> 47) == 0 || ((\val) >> 47) == 0x1ffff) + movz \reg, :abs_g2_s:\val + .else + movz \reg, :abs_g3:\val + movk \reg, :abs_g2_nc:\val + .endif + movk \reg, :abs_g1_nc:\val + .endif + movk \reg, :abs_g0_nc:\val + .endm + +/* + * Return the current thread_info. + */ + .macro get_thread_info, rd + mrs \rd, sp_el0 + .endm + #endif /* __ASM_ASSEMBLER_H */ diff -ruw linux-4.4.115/arch/arm64/include/asm/barrier.h linux-4.4.115-fbx/arch/arm64/include/asm/barrier.h --- linux-4.4.115/arch/arm64/include/asm/barrier.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/arch/arm64/include/asm/barrier.h 2019-01-22 16:16:21.535228585 +0100 @@ -20,6 +20,9 @@ #ifndef __ASSEMBLY__ +#define __nops(n) ".rept " #n "\nnop\n.endr\n" +#define nops(n) asm volatile(__nops(n)) + #define sev() asm volatile("sev" : : : "memory") #define wfe() asm volatile("wfe" : : : "memory") #define wfi() asm volatile("wfi" : : : "memory") diff -ruw linux-4.4.115/arch/arm64/include/asm/boot.h linux-4.4.115-fbx/arch/arm64/include/asm/boot.h --- linux-4.4.115/arch/arm64/include/asm/boot.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/arch/arm64/include/asm/boot.h 2019-01-22 16:16:21.535228585 +0100 @@ -11,4 +11,10 @@ #define MIN_FDT_ALIGN 8 #define MAX_FDT_SIZE SZ_2M +/* + * arm64 requires the kernel image to placed + * TEXT_OFFSET bytes beyond a 2 MB aligned base + */ +#define MIN_KIMG_ALIGN SZ_2M + #endif diff -ruw linux-4.4.115/arch/arm64/include/asm/bug.h linux-4.4.115-fbx/arch/arm64/include/asm/bug.h --- linux-4.4.115/arch/arm64/include/asm/bug.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/arch/arm64/include/asm/bug.h 2019-10-29 09:26:22.993196817 +0100 @@ -18,7 +18,7 @@ #ifndef _ARCH_ARM64_ASM_BUG_H #define _ARCH_ARM64_ASM_BUG_H -#include +#include #ifdef CONFIG_GENERIC_BUG #define HAVE_ARCH_BUG diff -ruw linux-4.4.115/arch/arm64/include/asm/cacheflush.h linux-4.4.115-fbx/arch/arm64/include/asm/cacheflush.h --- linux-4.4.115/arch/arm64/include/asm/cacheflush.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/arch/arm64/include/asm/cacheflush.h 2019-01-22 16:16:21.535228585 +0100 @@ -40,6 +40,10 @@ * the implementation assumes non-aliasing VIPT D-cache and (aliasing) * VIPT or ASID-tagged VIVT I-cache. * + * flush_cache_all() + * + * Unconditionally clean and invalidate the entire cache. + * * flush_cache_mm(mm) * * Clean and invalidate all user space cache entries @@ -65,9 +69,11 @@ * - kaddr - page address * - size - region size */ +extern void flush_cache_all(void); extern void flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end); extern void flush_icache_range(unsigned long start, unsigned long end); extern void __flush_dcache_area(void *addr, size_t len); +extern void __clean_dcache_area_pou(void *addr, size_t len); extern long __flush_cache_user_range(unsigned long start, unsigned long end); static inline void flush_cache_mm(struct mm_struct *mm) @@ -85,6 +91,12 @@ extern void __dma_map_area(const void *, size_t, int); extern void __dma_unmap_area(const void *, size_t, int); extern void __dma_flush_range(const void *, const void *); +extern void __dma_inv_range(const void *, const void *); +extern void __dma_clean_range(const void *, const void *); + +#define dmac_flush_range __dma_flush_range +#define dmac_inv_range __dma_inv_range +#define dmac_clean_range __dma_clean_range /* * Copy user data from/to a page which is mapped into a different @@ -154,9 +166,21 @@ int set_memory_rw(unsigned long addr, int numpages); int set_memory_x(unsigned long addr, int numpages); int set_memory_nx(unsigned long addr, int numpages); +#ifdef CONFIG_KERNEL_TEXT_RDONLY +void set_kernel_text_ro(void); +#else +static inline void set_kernel_text_ro(void) { } +#endif #ifdef CONFIG_DEBUG_RODATA void mark_rodata_ro(void); #endif +#ifdef CONFIG_FREE_PAGES_RDONLY +#define mark_addr_rdonly(a) set_memory_ro((unsigned long)a, 1); +#define mark_addr_rdwrite(a) set_memory_rw((unsigned long)a, 1); +#else +#define mark_addr_rdonly(a) +#define mark_addr_rdwrite(a) +#endif #endif diff -ruw linux-4.4.115/arch/arm64/include/asm/cache.h linux-4.4.115-fbx/arch/arm64/include/asm/cache.h --- linux-4.4.115/arch/arm64/include/asm/cache.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/arch/arm64/include/asm/cache.h 2019-01-22 16:16:21.535228585 +0100 @@ -18,17 +18,17 @@ #include -#define L1_CACHE_SHIFT 7 +#define L1_CACHE_SHIFT 6 #define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT) /* * Memory returned by kmalloc() may be used for DMA, so we must make - * sure that all such allocations are cache aligned. Otherwise, - * unrelated code may cause parts of the buffer to be read into the - * cache before the transfer is done, causing old data to be seen by - * the CPU. + * sure that all such allocations are aligned to the maximum *known* + * cache line size on ARMv8 systems. Otherwise, unrelated code may + * cause parts of the buffer to be read into the cache before the + * transfer is done, causing old data to be seen by the CPU. */ -#define ARCH_DMA_MINALIGN L1_CACHE_BYTES +#define ARCH_DMA_MINALIGN (128) #ifndef __ASSEMBLY__ diff -ruw linux-4.4.115/arch/arm64/include/asm/cmpxchg.h linux-4.4.115-fbx/arch/arm64/include/asm/cmpxchg.h --- linux-4.4.115/arch/arm64/include/asm/cmpxchg.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/arch/arm64/include/asm/cmpxchg.h 2019-01-22 16:16:21.535228585 +0100 @@ -19,7 +19,6 @@ #define __ASM_CMPXCHG_H #include -#include #include #include diff -ruw linux-4.4.115/arch/arm64/include/asm/cpufeature.h linux-4.4.115-fbx/arch/arm64/include/asm/cpufeature.h --- linux-4.4.115/arch/arm64/include/asm/cpufeature.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/arch/arm64/include/asm/cpufeature.h 2019-10-29 09:26:22.997196856 +0100 @@ -30,14 +30,22 @@ #define ARM64_HAS_LSE_ATOMICS 5 #define ARM64_WORKAROUND_CAVIUM_23154 6 #define ARM64_WORKAROUND_834220 7 -#define ARM64_WORKAROUND_CAVIUM_27456 8 - -#define ARM64_NCAPS 9 +#define ARM64_HAS_NO_HW_PREFETCH 8 +#define ARM64_HAS_UAO 9 +#define ARM64_ALT_PAN_NOT_UAO 10 + +#define ARM64_WORKAROUND_CAVIUM_27456 11 +#define ARM64_HAS_VIRT_HOST_EXTN 12 +#define ARM64_HARDEN_BRANCH_PREDICTOR 13 +#define ARM64_UNMAP_KERNEL_AT_EL0 14 +#define ARM64_NCAPS 15 #ifndef __ASSEMBLY__ #include +extern const char *machine_name; + /* CPU feature register tracking */ enum ftr_type { FTR_EXACT, /* Use a predefined safe value */ @@ -163,7 +171,9 @@ void update_cpu_capabilities(const struct arm64_cpu_capabilities *caps, const char *info); +void enable_cpu_capabilities(const struct arm64_cpu_capabilities *caps); void check_local_cpu_errata(void); +void __init enable_errata_workarounds(void); #ifdef CONFIG_HOTPLUG_CPU void verify_local_cpu_capabilities(void); @@ -177,7 +187,7 @@ static inline bool cpu_supports_mixed_endian_el0(void) { - return id_aa64mmfr0_mixed_endian_el0(read_cpuid(ID_AA64MMFR0_EL1)); + return id_aa64mmfr0_mixed_endian_el0(read_cpuid(SYS_ID_AA64MMFR0_EL1)); } static inline bool system_supports_mixed_endian_el0(void) @@ -185,6 +195,12 @@ return id_aa64mmfr0_mixed_endian_el0(read_system_reg(SYS_ID_AA64MMFR0_EL1)); } +static inline bool system_uses_ttbr0_pan(void) +{ + return IS_ENABLED(CONFIG_ARM64_SW_TTBR0_PAN) && + !cpus_have_cap(ARM64_HAS_PAN); +} + #endif /* __ASSEMBLY__ */ #endif diff -ruw linux-4.4.115/arch/arm64/include/asm/cpu.h linux-4.4.115-fbx/arch/arm64/include/asm/cpu.h --- linux-4.4.115/arch/arm64/include/asm/cpu.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/arch/arm64/include/asm/cpu.h 2019-01-22 16:16:21.535228585 +0100 @@ -36,6 +36,7 @@ u64 reg_id_aa64isar1; u64 reg_id_aa64mmfr0; u64 reg_id_aa64mmfr1; + u64 reg_id_aa64mmfr2; u64 reg_id_aa64pfr0; u64 reg_id_aa64pfr1; diff -ruw linux-4.4.115/arch/arm64/include/asm/cputype.h linux-4.4.115-fbx/arch/arm64/include/asm/cputype.h --- linux-4.4.115/arch/arm64/include/asm/cputype.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/arch/arm64/include/asm/cputype.h 2019-10-29 09:26:22.997196856 +0100 @@ -32,11 +32,9 @@ #define MPIDR_AFFINITY_LEVEL(mpidr, level) \ ((mpidr >> MPIDR_LEVEL_SHIFT(level)) & MPIDR_LEVEL_MASK) -#define read_cpuid(reg) ({ \ - u64 __val; \ - asm("mrs %0, " #reg : "=r" (__val)); \ - __val; \ -}) +#define MMFR0_16KGRAN_SIZE 15 +#define MMFR0_16KGRAN_SHFT 20 +#define MMFR0_EL1_16KGRAN_MASK (MMFR0_16KGRAN_SIZE << MMFR0_16KGRAN_SHFT) #define MIDR_REVISION_MASK 0xf #define MIDR_REVISION(midr) ((midr) & MIDR_REVISION_MASK) @@ -57,26 +55,65 @@ #define MIDR_IMPLEMENTOR(midr) \ (((midr) & MIDR_IMPLEMENTOR_MASK) >> MIDR_IMPLEMENTOR_SHIFT) -#define MIDR_CPU_PART(imp, partnum) \ +#define MIDR_CPU_MODEL(imp, partnum) \ (((imp) << MIDR_IMPLEMENTOR_SHIFT) | \ (0xf << MIDR_ARCHITECTURE_SHIFT) | \ ((partnum) << MIDR_PARTNUM_SHIFT)) +#define MIDR_CPU_MODEL_MASK (MIDR_IMPLEMENTOR_MASK | MIDR_PARTNUM_MASK | \ + MIDR_ARCHITECTURE_MASK) + +#define MIDR_IS_CPU_MODEL_RANGE(midr, model, rv_min, rv_max) \ +({ \ + u32 _model = (midr) & MIDR_CPU_MODEL_MASK; \ + u32 rv = (midr) & (MIDR_REVISION_MASK | MIDR_VARIANT_MASK); \ + \ + _model == (model) && rv >= (rv_min) && rv <= (rv_max); \ + }) + #define ARM_CPU_IMP_ARM 0x41 #define ARM_CPU_IMP_APM 0x50 #define ARM_CPU_IMP_CAVIUM 0x43 +#define ARM_CPU_IMP_QCOM 0x51 #define ARM_CPU_PART_AEM_V8 0xD0F #define ARM_CPU_PART_FOUNDATION 0xD00 #define ARM_CPU_PART_CORTEX_A57 0xD07 +#define ARM_CPU_PART_CORTEX_A72 0xD08 #define ARM_CPU_PART_CORTEX_A53 0xD03 +#define ARM_CPU_PART_CORTEX_A72 0xD08 +#define ARM_CPU_PART_CORTEX_A73 0xD09 +#define ARM_CPU_PART_CORTEX_A75 0xD0A +#define ARM_CPU_PART_KRYO2XX_GOLD 0x800 +#define ARM_CPU_PART_KRYO2XX_SILVER 0x801 +#define QCOM_CPU_PART_KRYO 0x200 #define APM_CPU_PART_POTENZA 0x000 #define CAVIUM_CPU_PART_THUNDERX 0x0A1 +#define MIDR_CORTEX_A53 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A53) +#define MIDR_CORTEX_A57 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A57) +#define MIDR_CORTEX_A72 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A72) +#define MIDR_CORTEX_A73 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A73) +#define MIDR_CORTEX_A75 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A75) +#define MIDR_THUNDERX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX) +#define MIDR_KRYO2XX_SILVER \ + MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, ARM_CPU_PART_KRYO2XX_SILVER) +#define MIDR_KRYO2XX_GOLD \ + MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, ARM_CPU_PART_KRYO2XX_GOLD) +#define MIDR_QCOM_KRYO MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_KRYO) + #ifndef __ASSEMBLY__ +#include + +#define read_cpuid(reg) ({ \ + u64 __val; \ + asm("mrs_s %0, " __stringify(reg) : "=r" (__val)); \ + __val; \ +}) + /* * The CPU ID never changes at run time, so we might as well tell the * compiler that it's constant. Use this function to read the CPU ID @@ -84,12 +121,12 @@ */ static inline u32 __attribute_const__ read_cpuid_id(void) { - return read_cpuid(MIDR_EL1); + return read_cpuid(SYS_MIDR_EL1); } static inline u64 __attribute_const__ read_cpuid_mpidr(void) { - return read_cpuid(MPIDR_EL1); + return read_cpuid(SYS_MPIDR_EL1); } static inline unsigned int __attribute_const__ read_cpuid_implementor(void) @@ -104,7 +141,7 @@ static inline u32 __attribute_const__ read_cpuid_cachetype(void) { - return read_cpuid(CTR_EL0); + return read_cpuid(SYS_CTR_EL0); } #endif /* __ASSEMBLY__ */ diff -ruw linux-4.4.115/arch/arm64/include/asm/debug-monitors.h linux-4.4.115-fbx/arch/arm64/include/asm/debug-monitors.h --- linux-4.4.115/arch/arm64/include/asm/debug-monitors.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/arch/arm64/include/asm/debug-monitors.h 2019-01-22 16:16:21.539228621 +0100 @@ -20,6 +20,7 @@ #include #include +#include #include #include #include @@ -47,19 +48,6 @@ #define BREAK_INSTR_SIZE AARCH64_INSN_SIZE /* - * #imm16 values used for BRK instruction generation - * Allowed values for kgbd are 0x400 - 0x7ff - * 0x100: for triggering a fault on purpose (reserved) - * 0x400: for dynamic BRK instruction - * 0x401: for compile time BRK instruction - * 0x800: kernel-mode BUG() and WARN() traps - */ -#define FAULT_BRK_IMM 0x100 -#define KGDB_DYN_DBG_BRK_IMM 0x400 -#define KGDB_COMPILED_DBG_BRK_IMM 0x401 -#define BUG_BRK_IMM 0x800 - -/* * BRK instruction encoding * The #imm16 value should be placed at bits[20:5] within BRK ins */ @@ -78,6 +66,11 @@ #define CACHE_FLUSH_IS_SAFE 1 +/* kprobes BRK opcodes with ESR encoding */ +#define BRK64_ESR_MASK 0xFFFF +#define BRK64_ESR_KPROBES 0x0004 +#define BRK64_OPCODE_KPROBES (AARCH64_BREAK_MON | (BRK64_ESR_KPROBES << 5)) + /* AArch32 */ #define DBG_ESR_EVT_BKPT 0x4 #define DBG_ESR_EVT_VECC 0x5 diff -ruw linux-4.4.115/arch/arm64/include/asm/device.h linux-4.4.115-fbx/arch/arm64/include/asm/device.h --- linux-4.4.115/arch/arm64/include/asm/device.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/arch/arm64/include/asm/device.h 2019-01-22 16:16:21.539228621 +0100 @@ -17,14 +17,24 @@ #define __ASM_DEVICE_H struct dev_archdata { - struct dma_map_ops *dma_ops; + const struct dma_map_ops *dma_ops; #ifdef CONFIG_IOMMU_API void *iommu; /* private IOMMU data */ #endif bool dma_coherent; +#ifdef CONFIG_ARM64_DMA_USE_IOMMU + struct dma_iommu_mapping *mapping; +#endif }; struct pdev_archdata { + u64 dma_mask; }; +#ifdef CONFIG_ARM64_DMA_USE_IOMMU +#define to_dma_iommu_mapping(dev) ((dev)->archdata.mapping) +#else +#define to_dma_iommu_mapping(dev) NULL +#endif + #endif diff -ruw linux-4.4.115/arch/arm64/include/asm/dma-mapping.h linux-4.4.115-fbx/arch/arm64/include/asm/dma-mapping.h --- linux-4.4.115/arch/arm64/include/asm/dma-mapping.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/arch/arm64/include/asm/dma-mapping.h 2019-01-22 16:16:21.539228621 +0100 @@ -27,7 +27,7 @@ #define DMA_ERROR_CODE (~(dma_addr_t)0) extern struct dma_map_ops dummy_dma_ops; -static inline struct dma_map_ops *__generic_dma_ops(struct device *dev) +static inline const struct dma_map_ops *__generic_dma_ops(struct device *dev) { if (dev && dev->archdata.dma_ops) return dev->archdata.dma_ops; @@ -39,7 +39,7 @@ return &dummy_dma_ops; } -static inline struct dma_map_ops *get_dma_ops(struct device *dev) +static inline const struct dma_map_ops *get_dma_ops(struct device *dev) { if (xen_initial_domain()) return xen_dma_ops; @@ -47,6 +47,12 @@ return __generic_dma_ops(dev); } +static inline void set_dma_ops(struct device *dev, + const struct dma_map_ops *dma_ops) +{ + dev->archdata.dma_ops = dma_ops; +} + void arch_setup_dma_ops(struct device *dev, u64 dma_base, u64 size, struct iommu_ops *iommu, bool coherent); #define arch_setup_dma_ops arch_setup_dma_ops diff -ruw linux-4.4.115/arch/arm64/include/asm/efi.h linux-4.4.115-fbx/arch/arm64/include/asm/efi.h --- linux-4.4.115/arch/arm64/include/asm/efi.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/arch/arm64/include/asm/efi.h 2019-01-22 16:16:21.539228621 +0100 @@ -1,8 +1,11 @@ #ifndef _ASM_EFI_H #define _ASM_EFI_H +#include #include +#include #include +#include #ifdef CONFIG_EFI extern void efi_init(void); @@ -10,6 +13,8 @@ #define efi_init() #endif +int efi_create_mapping(struct mm_struct *mm, efi_memory_desc_t *md); + #define efi_call_virt(f, ...) \ ({ \ efi_##f##_t *__f; \ @@ -63,6 +68,34 @@ * Services are enabled and the EFI_RUNTIME_SERVICES bit set. */ +static inline void efi_set_pgd(struct mm_struct *mm) +{ + __switch_mm(mm); + + if (system_uses_ttbr0_pan()) { + if (mm != current->active_mm) { + /* + * Update the current thread's saved ttbr0 since it is + * restored as part of a return from exception. Enable + * access to the valid TTBR0_EL1 and invoke the errata + * workaround directly since there is no return from + * exception when invoking the EFI run-time services. + */ + update_saved_ttbr0(current, mm); + uaccess_ttbr0_enable(); + post_ttbr_update_workaround(); + } else { + /* + * Defer the switch to the current thread's TTBR0_EL1 + * until uaccess_enable(). Restore the current + * thread's saved ttbr0 corresponding to its active_mm + */ + uaccess_ttbr0_disable(); + update_saved_ttbr0(current, current->active_mm); + } + } +} + void efi_virtmap_load(void); void efi_virtmap_unload(void); diff -ruw linux-4.4.115/arch/arm64/include/asm/elf.h linux-4.4.115-fbx/arch/arm64/include/asm/elf.h --- linux-4.4.115/arch/arm64/include/asm/elf.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/arch/arm64/include/asm/elf.h 2019-01-22 16:16:21.539228621 +0100 @@ -23,15 +23,7 @@ */ #include #include - -typedef unsigned long elf_greg_t; - -#define ELF_NGREG (sizeof(struct user_pt_regs) / sizeof(elf_greg_t)) -#define ELF_CORE_COPY_REGS(dest, regs) \ - *(struct user_pt_regs *)&(dest) = (regs)->user_regs; - -typedef elf_greg_t elf_gregset_t[ELF_NGREG]; -typedef struct user_fpsimd_state elf_fpregset_t; +#include /* * AArch64 static relocation types. @@ -86,6 +78,8 @@ #define R_AARCH64_MOVW_PREL_G2_NC 292 #define R_AARCH64_MOVW_PREL_G3 293 +#define R_AARCH64_RELATIVE 1027 + /* * These are used to set parameters in the core dumps. */ @@ -126,6 +120,17 @@ */ #define ELF_ET_DYN_BASE (2 * TASK_SIZE_64 / 3) +#ifndef __ASSEMBLY__ + +typedef unsigned long elf_greg_t; + +#define ELF_NGREG (sizeof(struct user_pt_regs) / sizeof(elf_greg_t)) +#define ELF_CORE_COPY_REGS(dest, regs) \ + *(struct user_pt_regs *)&(dest) = (regs)->user_regs; + +typedef elf_greg_t elf_gregset_t[ELF_NGREG]; +typedef struct user_fpsimd_state elf_fpregset_t; + /* * When the program starts, a1 contains a pointer to a function to be * registered with atexit, as per the SVR4 ABI. A value of 0 means we have no @@ -165,7 +170,7 @@ #ifdef CONFIG_COMPAT /* PIE load location for compat arm. Must match ARM ELF_ET_DYN_BASE. */ -#define COMPAT_ELF_ET_DYN_BASE 0x000400000UL +#define COMPAT_ELF_ET_DYN_BASE (2 * TASK_SIZE_32 / 3) /* AArch32 registers. */ #define COMPAT_ELF_NGREG 18 @@ -178,7 +183,11 @@ ((x)->e_flags & EF_ARM_EABI_MASK)) #define compat_start_thread compat_start_thread -#define COMPAT_SET_PERSONALITY(ex) set_thread_flag(TIF_32BIT); +#define COMPAT_SET_PERSONALITY(ex) \ +do { \ + set_thread_flag(TIF_32BIT); \ +} while (0) + #define COMPAT_ARCH_DLINFO extern int aarch32_setup_vectors_page(struct linux_binprm *bprm, int uses_interp); @@ -187,4 +196,6 @@ #endif /* CONFIG_COMPAT */ +#endif /* !__ASSEMBLY__ */ + #endif diff -ruw linux-4.4.115/arch/arm64/include/asm/esr.h linux-4.4.115-fbx/arch/arm64/include/asm/esr.h --- linux-4.4.115/arch/arm64/include/asm/esr.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/arch/arm64/include/asm/esr.h 2019-01-22 16:16:21.539228621 +0100 @@ -74,6 +74,7 @@ #define ESR_ELx_EC_SHIFT (26) #define ESR_ELx_EC_MASK (UL(0x3F) << ESR_ELx_EC_SHIFT) +#define ESR_ELx_EC(esr) (((esr) & ESR_ELx_EC_MASK) >> ESR_ELx_EC_SHIFT) #define ESR_ELx_IL (UL(1) << 25) #define ESR_ELx_ISS_MASK (ESR_ELx_IL - 1) @@ -108,6 +109,46 @@ ((ESR_ELx_EC_BRK64 << ESR_ELx_EC_SHIFT) | ESR_ELx_IL | \ ((imm) & 0xffff)) +/* ISS field definitions for System instruction traps */ +#define ESR_ELx_SYS64_ISS_RES0_SHIFT 22 +#define ESR_ELx_SYS64_ISS_RES0_MASK (UL(0x7) << ESR_ELx_SYS64_ISS_RES0_SHIFT) +#define ESR_ELx_SYS64_ISS_DIR_MASK 0x1 +#define ESR_ELx_SYS64_ISS_DIR_READ 0x1 +#define ESR_ELx_SYS64_ISS_DIR_WRITE 0x0 + +#define ESR_ELx_SYS64_ISS_RT_SHIFT 5 +#define ESR_ELx_SYS64_ISS_RT_MASK (UL(0x1f) << ESR_ELx_SYS64_ISS_RT_SHIFT) +#define ESR_ELx_SYS64_ISS_CRM_SHIFT 1 +#define ESR_ELx_SYS64_ISS_CRM_MASK (UL(0xf) << ESR_ELx_SYS64_ISS_CRM_SHIFT) +#define ESR_ELx_SYS64_ISS_CRN_SHIFT 10 +#define ESR_ELx_SYS64_ISS_CRN_MASK (UL(0xf) << ESR_ELx_SYS64_ISS_CRN_SHIFT) +#define ESR_ELx_SYS64_ISS_OP1_SHIFT 14 +#define ESR_ELx_SYS64_ISS_OP1_MASK (UL(0x7) << ESR_ELx_SYS64_ISS_OP1_SHIFT) +#define ESR_ELx_SYS64_ISS_OP2_SHIFT 17 +#define ESR_ELx_SYS64_ISS_OP2_MASK (UL(0x7) << ESR_ELx_SYS64_ISS_OP2_SHIFT) +#define ESR_ELx_SYS64_ISS_OP0_SHIFT 20 +#define ESR_ELx_SYS64_ISS_OP0_MASK (UL(0x3) << ESR_ELx_SYS64_ISS_OP0_SHIFT) +#define ESR_ELx_SYS64_ISS_SYS_MASK (ESR_ELx_SYS64_ISS_OP0_MASK | \ + ESR_ELx_SYS64_ISS_OP1_MASK | \ + ESR_ELx_SYS64_ISS_OP2_MASK | \ + ESR_ELx_SYS64_ISS_CRN_MASK | \ + ESR_ELx_SYS64_ISS_CRM_MASK) +#define ESR_ELx_SYS64_ISS_SYS_VAL(op0, op1, op2, crn, crm) \ + (((op0) << ESR_ELx_SYS64_ISS_OP0_SHIFT) | \ + ((op1) << ESR_ELx_SYS64_ISS_OP1_SHIFT) | \ + ((op2) << ESR_ELx_SYS64_ISS_OP2_SHIFT) | \ + ((crn) << ESR_ELx_SYS64_ISS_CRN_SHIFT) | \ + ((crm) << ESR_ELx_SYS64_ISS_CRM_SHIFT)) + +#define ESR_ELx_SYS64_ISS_SYS_OP_MASK (ESR_ELx_SYS64_ISS_SYS_MASK | \ + ESR_ELx_SYS64_ISS_DIR_MASK) + +#define ESR_ELx_SYS64_ISS_SYS_CNTVCT (ESR_ELx_SYS64_ISS_SYS_VAL(3, 3, 2, 14, 0) | \ + ESR_ELx_SYS64_ISS_DIR_READ) + +#define ESR_ELx_SYS64_ISS_SYS_CNTFRQ (ESR_ELx_SYS64_ISS_SYS_VAL(3, 3, 0, 14, 0) | \ + ESR_ELx_SYS64_ISS_DIR_READ) + #ifndef __ASSEMBLY__ #include diff -ruw linux-4.4.115/arch/arm64/include/asm/exception.h linux-4.4.115-fbx/arch/arm64/include/asm/exception.h --- linux-4.4.115/arch/arm64/include/asm/exception.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/arch/arm64/include/asm/exception.h 2019-01-22 16:16:21.539228621 +0100 @@ -18,7 +18,7 @@ #ifndef __ASM_EXCEPTION_H #define __ASM_EXCEPTION_H -#include +#include #define __exception __attribute__((section(".exception.text"))) #ifdef CONFIG_FUNCTION_GRAPH_TRACER diff -ruw linux-4.4.115/arch/arm64/include/asm/exec.h linux-4.4.115-fbx/arch/arm64/include/asm/exec.h --- linux-4.4.115/arch/arm64/include/asm/exec.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/arch/arm64/include/asm/exec.h 2019-01-22 16:16:21.539228621 +0100 @@ -18,6 +18,9 @@ #ifndef __ASM_EXEC_H #define __ASM_EXEC_H +#include + extern unsigned long arch_align_stack(unsigned long sp); +void uao_thread_switch(struct task_struct *next); #endif /* __ASM_EXEC_H */ diff -ruw linux-4.4.115/arch/arm64/include/asm/fixmap.h linux-4.4.115-fbx/arch/arm64/include/asm/fixmap.h --- linux-4.4.115/arch/arm64/include/asm/fixmap.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/arch/arm64/include/asm/fixmap.h 2019-01-22 16:16:21.539228621 +0100 @@ -50,6 +50,11 @@ FIX_EARLYCON_MEM_BASE, FIX_TEXT_POKE0, +#ifdef CONFIG_UNMAP_KERNEL_AT_EL0 + FIX_ENTRY_TRAMP_DATA, + FIX_ENTRY_TRAMP_TEXT, +#define TRAMP_VALIAS (__fix_to_virt(FIX_ENTRY_TRAMP_TEXT)) +#endif /* CONFIG_UNMAP_KERNEL_AT_EL0 */ __end_of_permanent_fixed_addresses, /* @@ -62,6 +67,16 @@ FIX_BTMAP_END = __end_of_permanent_fixed_addresses, FIX_BTMAP_BEGIN = FIX_BTMAP_END + TOTAL_FIX_BTMAPS - 1, + + /* + * Used for kernel page table creation, so unmapped memory may be used + * for tables. + */ + FIX_PTE, + FIX_PMD, + FIX_PUD, + FIX_PGD, + __end_of_fixed_addresses }; diff -ruw linux-4.4.115/arch/arm64/include/asm/fpsimd.h linux-4.4.115-fbx/arch/arm64/include/asm/fpsimd.h --- linux-4.4.115/arch/arm64/include/asm/fpsimd.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/arch/arm64/include/asm/fpsimd.h 2019-01-22 16:16:21.539228621 +0100 @@ -81,6 +81,14 @@ u32 num_regs); extern void fpsimd_load_partial_state(struct fpsimd_partial_state *state); +#ifdef CONFIG_ENABLE_FP_SIMD_SETTINGS +extern void fpsimd_disable_trap(void); +extern void fpsimd_enable_trap(void); +#else +static inline void fpsimd_disable_trap(void) {} +static inline void fpsimd_enable_trap(void) {} +#endif + #endif #endif diff -ruw linux-4.4.115/arch/arm64/include/asm/ftrace.h linux-4.4.115-fbx/arch/arm64/include/asm/ftrace.h --- linux-4.4.115/arch/arm64/include/asm/ftrace.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/arch/arm64/include/asm/ftrace.h 2019-01-22 16:16:21.539228621 +0100 @@ -28,6 +28,8 @@ extern unsigned long ftrace_graph_call; +extern void return_to_handler(void); + static inline unsigned long ftrace_call_adjust(unsigned long addr) { /* diff -ruw linux-4.4.115/arch/arm64/include/asm/futex.h linux-4.4.115-fbx/arch/arm64/include/asm/futex.h --- linux-4.4.115/arch/arm64/include/asm/futex.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/arch/arm64/include/asm/futex.h 2019-10-29 09:26:22.997196856 +0100 @@ -21,15 +21,12 @@ #include #include -#include -#include #include -#include #define __futex_atomic_op(insn, ret, oldval, uaddr, tmp, oparg) \ +do { \ + uaccess_enable(); \ asm volatile( \ - ALTERNATIVE("nop", SET_PSTATE_PAN(0), ARM64_HAS_PAN, \ - CONFIG_ARM64_PAN) \ " prfm pstl1strm, %2\n" \ "1: ldxr %w1, %2\n" \ insn "\n" \ @@ -42,15 +39,13 @@ "4: mov %w0, %w5\n" \ " b 3b\n" \ " .popsection\n" \ -" .pushsection __ex_table,\"a\"\n" \ -" .align 3\n" \ -" .quad 1b, 4b, 2b, 4b\n" \ -" .popsection\n" \ - ALTERNATIVE("nop", SET_PSTATE_PAN(1), ARM64_HAS_PAN, \ - CONFIG_ARM64_PAN) \ + _ASM_EXTABLE(1b, 4b) \ + _ASM_EXTABLE(2b, 4b) \ : "=&r" (ret), "=&r" (oldval), "+Q" (*uaddr), "=&r" (tmp) \ : "r" (oparg), "Ir" (-EFAULT) \ - : "memory") + : "memory"); \ + uaccess_disable(); \ +} while (0) static inline int futex_atomic_op_inuser (int encoded_op, u32 __user *uaddr) @@ -120,8 +115,8 @@ if (!access_ok(VERIFY_WRITE, uaddr, sizeof(u32))) return -EFAULT; + uaccess_enable(); asm volatile("// futex_atomic_cmpxchg_inatomic\n" -ALTERNATIVE("nop", SET_PSTATE_PAN(0), ARM64_HAS_PAN, CONFIG_ARM64_PAN) " prfm pstl1strm, %2\n" "1: ldxr %w1, %2\n" " sub %w3, %w1, %w4\n" @@ -134,14 +129,12 @@ "4: mov %w0, %w6\n" " b 3b\n" " .popsection\n" -" .pushsection __ex_table,\"a\"\n" -" .align 3\n" -" .quad 1b, 4b, 2b, 4b\n" -" .popsection\n" -ALTERNATIVE("nop", SET_PSTATE_PAN(1), ARM64_HAS_PAN, CONFIG_ARM64_PAN) + _ASM_EXTABLE(1b, 4b) + _ASM_EXTABLE(2b, 4b) : "+r" (ret), "=&r" (val), "+Q" (*uaddr), "=&r" (tmp) : "r" (oldval), "r" (newval), "Ir" (-EFAULT) : "memory"); + uaccess_disable(); *uval = val; return ret; diff -ruw linux-4.4.115/arch/arm64/include/asm/hardirq.h linux-4.4.115-fbx/arch/arm64/include/asm/hardirq.h --- linux-4.4.115/arch/arm64/include/asm/hardirq.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/arch/arm64/include/asm/hardirq.h 2019-01-22 16:16:21.539228621 +0100 @@ -20,7 +20,7 @@ #include #include -#define NR_IPI 5 +#define NR_IPI 7 typedef struct { unsigned int __softirq_pending; diff -ruw linux-4.4.115/arch/arm64/include/asm/hw_breakpoint.h linux-4.4.115-fbx/arch/arm64/include/asm/hw_breakpoint.h --- linux-4.4.115/arch/arm64/include/asm/hw_breakpoint.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/arch/arm64/include/asm/hw_breakpoint.h 2019-01-22 16:16:21.539228621 +0100 @@ -68,7 +68,11 @@ /* Lengths */ #define ARM_BREAKPOINT_LEN_1 0x1 #define ARM_BREAKPOINT_LEN_2 0x3 +#define ARM_BREAKPOINT_LEN_3 0x7 #define ARM_BREAKPOINT_LEN_4 0xf +#define ARM_BREAKPOINT_LEN_5 0x1f +#define ARM_BREAKPOINT_LEN_6 0x3f +#define ARM_BREAKPOINT_LEN_7 0x7f #define ARM_BREAKPOINT_LEN_8 0xff /* Kernel stepping */ @@ -110,7 +114,7 @@ struct pmu; extern int arch_bp_generic_fields(struct arch_hw_breakpoint_ctrl ctrl, - int *gen_len, int *gen_type); + int *gen_len, int *gen_type, int *offset); extern int arch_check_bp_in_kernelspace(struct perf_event *bp); extern int arch_validate_hwbkpt_settings(struct perf_event *bp); extern int hw_breakpoint_exceptions_notify(struct notifier_block *unused, diff -ruw linux-4.4.115/arch/arm64/include/asm/insn.h linux-4.4.115-fbx/arch/arm64/include/asm/insn.h --- linux-4.4.115/arch/arm64/include/asm/insn.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/arch/arm64/include/asm/insn.h 2019-01-22 16:16:21.539228621 +0100 @@ -120,6 +120,29 @@ AARCH64_INSN_REG_SP = 31 /* Stack pointer: as load/store base reg */ }; +enum aarch64_insn_special_register { + AARCH64_INSN_SPCLREG_SPSR_EL1 = 0xC200, + AARCH64_INSN_SPCLREG_ELR_EL1 = 0xC201, + AARCH64_INSN_SPCLREG_SP_EL0 = 0xC208, + AARCH64_INSN_SPCLREG_SPSEL = 0xC210, + AARCH64_INSN_SPCLREG_CURRENTEL = 0xC212, + AARCH64_INSN_SPCLREG_DAIF = 0xDA11, + AARCH64_INSN_SPCLREG_NZCV = 0xDA10, + AARCH64_INSN_SPCLREG_FPCR = 0xDA20, + AARCH64_INSN_SPCLREG_DSPSR_EL0 = 0xDA28, + AARCH64_INSN_SPCLREG_DLR_EL0 = 0xDA29, + AARCH64_INSN_SPCLREG_SPSR_EL2 = 0xE200, + AARCH64_INSN_SPCLREG_ELR_EL2 = 0xE201, + AARCH64_INSN_SPCLREG_SP_EL1 = 0xE208, + AARCH64_INSN_SPCLREG_SPSR_INQ = 0xE218, + AARCH64_INSN_SPCLREG_SPSR_ABT = 0xE219, + AARCH64_INSN_SPCLREG_SPSR_UND = 0xE21A, + AARCH64_INSN_SPCLREG_SPSR_FIQ = 0xE21B, + AARCH64_INSN_SPCLREG_SPSR_EL3 = 0xF200, + AARCH64_INSN_SPCLREG_ELR_EL3 = 0xF201, + AARCH64_INSN_SPCLREG_SP_EL2 = 0xF210 +}; + enum aarch64_insn_variant { AARCH64_INSN_VARIANT_32BIT, AARCH64_INSN_VARIANT_64BIT @@ -223,8 +246,15 @@ static __always_inline u32 aarch64_insn_get_##abbr##_value(void) \ { return (val); } +__AARCH64_INSN_FUNCS(adr_adrp, 0x1F000000, 0x10000000) +__AARCH64_INSN_FUNCS(prfm_lit, 0xFF000000, 0xD8000000) __AARCH64_INSN_FUNCS(str_reg, 0x3FE0EC00, 0x38206800) __AARCH64_INSN_FUNCS(ldr_reg, 0x3FE0EC00, 0x38606800) +__AARCH64_INSN_FUNCS(ldr_lit, 0xBF000000, 0x18000000) +__AARCH64_INSN_FUNCS(ldrsw_lit, 0xFF000000, 0x98000000) +__AARCH64_INSN_FUNCS(exclusive, 0x3F800000, 0x08000000) +__AARCH64_INSN_FUNCS(load_ex, 0x3F400000, 0x08400000) +__AARCH64_INSN_FUNCS(store_ex, 0x3F400000, 0x08000000) __AARCH64_INSN_FUNCS(stp_post, 0x7FC00000, 0x28800000) __AARCH64_INSN_FUNCS(ldp_post, 0x7FC00000, 0x28C00000) __AARCH64_INSN_FUNCS(stp_pre, 0x7FC00000, 0x29800000) @@ -273,10 +303,15 @@ __AARCH64_INSN_FUNCS(hvc, 0xFFE0001F, 0xD4000002) __AARCH64_INSN_FUNCS(smc, 0xFFE0001F, 0xD4000003) __AARCH64_INSN_FUNCS(brk, 0xFFE0001F, 0xD4200000) +__AARCH64_INSN_FUNCS(exception, 0xFF000000, 0xD4000000) __AARCH64_INSN_FUNCS(hint, 0xFFFFF01F, 0xD503201F) __AARCH64_INSN_FUNCS(br, 0xFFFFFC1F, 0xD61F0000) __AARCH64_INSN_FUNCS(blr, 0xFFFFFC1F, 0xD63F0000) __AARCH64_INSN_FUNCS(ret, 0xFFFFFC1F, 0xD65F0000) +__AARCH64_INSN_FUNCS(eret, 0xFFFFFFFF, 0xD69F03E0) +__AARCH64_INSN_FUNCS(mrs, 0xFFF00000, 0xD5300000) +__AARCH64_INSN_FUNCS(msr_imm, 0xFFF8F01F, 0xD500401F) +__AARCH64_INSN_FUNCS(msr_reg, 0xFFF00000, 0xD5100000) #undef __AARCH64_INSN_FUNCS @@ -286,6 +321,8 @@ int aarch64_insn_read(void *addr, u32 *insnp); int aarch64_insn_write(void *addr, u32 insn); enum aarch64_insn_encoding_class aarch64_get_insn_class(u32 insn); +bool aarch64_insn_uses_literal(u32 insn); +bool aarch64_insn_is_branch(u32 insn); u64 aarch64_insn_decode_immediate(enum aarch64_insn_imm_type type, u32 insn); u32 aarch64_insn_encode_immediate(enum aarch64_insn_imm_type type, u32 insn, u64 imm); @@ -367,9 +404,13 @@ #define A32_RT_OFFSET 12 #define A32_RT2_OFFSET 0 +u32 aarch64_insn_extract_system_reg(u32 insn); u32 aarch32_insn_extract_reg_num(u32 insn, int offset); u32 aarch32_insn_mcr_extract_opc2(u32 insn); u32 aarch32_insn_mcr_extract_crm(u32 insn); + +typedef bool (pstate_check_t)(unsigned long); +extern pstate_check_t * const aarch32_opcode_cond_checks[16]; #endif /* __ASSEMBLY__ */ #endif /* __ASM_INSN_H */ diff -ruw linux-4.4.115/arch/arm64/include/asm/io.h linux-4.4.115-fbx/arch/arm64/include/asm/io.h --- linux-4.4.115/arch/arm64/include/asm/io.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/arch/arm64/include/asm/io.h 2019-01-22 16:16:21.539228621 +0100 @@ -31,38 +31,35 @@ #include #include #include +#include #include /* * Generic IO read/write. These perform native-endian accesses. + * that some architectures will want to re-define __raw_{read,write}w. */ -#define __raw_writeb __raw_writeb -static inline void __raw_writeb(u8 val, volatile void __iomem *addr) +static inline void __raw_writeb_no_log(u8 val, volatile void __iomem *addr) { asm volatile("strb %w0, [%1]" : : "r" (val), "r" (addr)); } -#define __raw_writew __raw_writew -static inline void __raw_writew(u16 val, volatile void __iomem *addr) +static inline void __raw_writew_no_log(u16 val, volatile void __iomem *addr) { asm volatile("strh %w0, [%1]" : : "r" (val), "r" (addr)); } -#define __raw_writel __raw_writel -static inline void __raw_writel(u32 val, volatile void __iomem *addr) +static inline void __raw_writel_no_log(u32 val, volatile void __iomem *addr) { asm volatile("str %w0, [%1]" : : "r" (val), "r" (addr)); } -#define __raw_writeq __raw_writeq -static inline void __raw_writeq(u64 val, volatile void __iomem *addr) +static inline void __raw_writeq_no_log(u64 val, volatile void __iomem *addr) { asm volatile("str %0, [%1]" : : "r" (val), "r" (addr)); } -#define __raw_readb __raw_readb -static inline u8 __raw_readb(const volatile void __iomem *addr) +static inline u8 __raw_readb_no_log(const volatile void __iomem *addr) { u8 val; asm volatile(ALTERNATIVE("ldrb %w0, [%1]", @@ -72,8 +69,7 @@ return val; } -#define __raw_readw __raw_readw -static inline u16 __raw_readw(const volatile void __iomem *addr) +static inline u16 __raw_readw_no_log(const volatile void __iomem *addr) { u16 val; @@ -84,8 +80,7 @@ return val; } -#define __raw_readl __raw_readl -static inline u32 __raw_readl(const volatile void __iomem *addr) +static inline u32 __raw_readl_no_log(const volatile void __iomem *addr) { u32 val; asm volatile(ALTERNATIVE("ldr %w0, [%1]", @@ -95,8 +90,7 @@ return val; } -#define __raw_readq __raw_readq -static inline u64 __raw_readq(const volatile void __iomem *addr) +static inline u64 __raw_readq_no_log(const volatile void __iomem *addr) { u64 val; asm volatile(ALTERNATIVE("ldr %0, [%1]", @@ -106,6 +100,46 @@ return val; } +/* + * There may be cases when clients don't want to support or can't support the + * logging, The appropriate functions can be used but clinets should carefully + * consider why they can't support the logging + */ + +#define __raw_write_logged(v, a, _t) ({ \ + int _ret; \ + volatile void __iomem *_a = (a); \ + void *_addr = (void __force *)(_a); \ + _ret = uncached_logk(LOGK_WRITEL, _addr); \ + ETB_WAYPOINT; \ + __raw_write##_t##_no_log((v), _a); \ + if (_ret) \ + LOG_BARRIER; \ + }) + +#define __raw_writeb(v, a) __raw_write_logged((v), a, b) +#define __raw_writew(v, a) __raw_write_logged((v), a, w) +#define __raw_writel(v, a) __raw_write_logged((v), a, l) +#define __raw_writeq(v, a) __raw_write_logged((v), a, q) + +#define __raw_read_logged(a, _l, _t) ({ \ + _t __a; \ + const volatile void __iomem *_a = (const volatile void __iomem *)(a); \ + void *_addr = (void __force *)(_a); \ + int _ret; \ + _ret = uncached_logk(LOGK_READL, _addr); \ + ETB_WAYPOINT; \ + __a = __raw_read##_l##_no_log(_a); \ + if (_ret) \ + LOG_BARRIER; \ + __a; \ + }) + +#define __raw_readb(a) __raw_read_logged((a), b, u8) +#define __raw_readw(a) __raw_read_logged((a), w, u16) +#define __raw_readl(a) __raw_read_logged((a), l, u32) +#define __raw_readq(a) __raw_read_logged((a), q, u64) + /* IO barriers */ #define __iormb() rmb() #define __iowmb() wmb() @@ -127,6 +161,16 @@ #define writel_relaxed(v,c) ((void)__raw_writel((__force u32)cpu_to_le32(v),(c))) #define writeq_relaxed(v,c) ((void)__raw_writeq((__force u64)cpu_to_le64(v),(c))) +#define readb_relaxed_no_log(c) ({ u8 __v = __raw_readb_no_log(c); __v; }) +#define readw_relaxed_no_log(c) ({ u16 __v = le16_to_cpu((__force __le16)__raw_readw_no_log(c)); __v; }) +#define readl_relaxed_no_log(c) ({ u32 __v = le32_to_cpu((__force __le32)__raw_readl_no_log(c)); __v; }) +#define readq_relaxed_no_log(c) ({ u64 __v = le64_to_cpu((__force __le64)__raw_readq_no_log(c)); __v; }) + +#define writeb_relaxed_no_log(v, c) ((void)__raw_writeb_no_log((v), (c))) +#define writew_relaxed_no_log(v, c) ((void)__raw_writew_no_log((__force u16)cpu_to_le16(v), (c))) +#define writel_relaxed_no_log(v, c) ((void)__raw_writel_no_log((__force u32)cpu_to_le32(v), (c))) +#define writeq_relaxed_no_log(v, c) ((void)__raw_writeq_no_log((__force u64)cpu_to_le64(v), (c))) + /* * I/O memory access primitives. Reads are ordered relative to any * following Normal memory access. Writes are ordered relative to any prior @@ -142,6 +186,16 @@ #define writel(v,c) ({ __iowmb(); writel_relaxed((v),(c)); }) #define writeq(v,c) ({ __iowmb(); writeq_relaxed((v),(c)); }) +#define readb_no_log(c) ({ u8 __v = readb_relaxed_no_log(c); __iormb(); __v; }) +#define readw_no_log(c) ({ u16 __v = readw_relaxed_no_log(c); __iormb(); __v; }) +#define readl_no_log(c) ({ u32 __v = readl_relaxed_no_log(c); __iormb(); __v; }) +#define readq_no_log(c) ({ u64 __v = readq_relaxed_no_log(c); __iormb(); __v; }) + +#define writeb_no_log(v, c) ({ __iowmb(); writeb_relaxed_no_log((v), (c)); }) +#define writew_no_log(v, c) ({ __iowmb(); writew_relaxed_no_log((v), (c)); }) +#define writel_no_log(v, c) ({ __iowmb(); writel_relaxed_no_log((v), (c)); }) +#define writeq_no_log(v, c) ({ __iowmb(); writeq_relaxed_no_log((v), (c)); }) + /* * I/O port access primitives. */ diff -ruw linux-4.4.115/arch/arm64/include/asm/irq.h linux-4.4.115-fbx/arch/arm64/include/asm/irq.h --- linux-4.4.115/arch/arm64/include/asm/irq.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/arch/arm64/include/asm/irq.h 2019-01-22 16:16:21.539228621 +0100 @@ -1,10 +1,45 @@ #ifndef __ASM_IRQ_H #define __ASM_IRQ_H +#define IRQ_STACK_SIZE THREAD_SIZE +#define IRQ_STACK_START_SP THREAD_START_SP + +#ifndef __ASSEMBLER__ + +#include + #include +#include struct pt_regs; +DECLARE_PER_CPU(unsigned long [IRQ_STACK_SIZE/sizeof(long)], irq_stack); + +/* + * The highest address on the stack, and the first to be used. Used to + * find the dummy-stack frame put down by el?_irq() in entry.S, which + * is structured as follows: + * + * ------------ + * | | <- irq_stack_ptr + * top ------------ + * | x19 | <- irq_stack_ptr - 0x08 + * ------------ + * | x29 | <- irq_stack_ptr - 0x10 + * ------------ + * + * where x19 holds a copy of the task stack pointer where the struct pt_regs + * from kernel_entry can be found. + * + */ +#define IRQ_STACK_PTR(cpu) ((unsigned long)per_cpu(irq_stack, cpu) + IRQ_STACK_START_SP) + +/* + * The offset from irq_stack_ptr where entry.S will store the original + * stack pointer. Used by unwind_frame() and dump_backtrace(). + */ +#define IRQ_STACK_TO_TASK_STACK(ptr) (*((unsigned long *)((ptr) - 0x08))) + extern void set_handle_irq(void (*handle_irq)(struct pt_regs *)); static inline int nr_legacy_irqs(void) @@ -12,4 +47,17 @@ return 0; } +void arch_trigger_all_cpu_backtrace(void); +#define arch_trigger_all_cpu_backtrace arch_trigger_all_cpu_backtrace + +static inline bool on_irq_stack(unsigned long sp, int cpu) +{ + /* variable names the same as kernel/stacktrace.c */ + unsigned long low = (unsigned long)per_cpu(irq_stack, cpu); + unsigned long high = low + IRQ_STACK_START_SP; + + return (low <= sp && sp <= high); +} + +#endif /* !__ASSEMBLER__ */ #endif diff -ruw linux-4.4.115/arch/arm64/include/asm/kasan.h linux-4.4.115-fbx/arch/arm64/include/asm/kasan.h --- linux-4.4.115/arch/arm64/include/asm/kasan.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/arch/arm64/include/asm/kasan.h 2019-01-22 16:16:21.539228621 +0100 @@ -7,13 +7,14 @@ #include #include +#include /* * KASAN_SHADOW_START: beginning of the kernel virtual addresses. * KASAN_SHADOW_END: KASAN_SHADOW_START + 1/8 of kernel virtual addresses. */ #define KASAN_SHADOW_START (VA_START) -#define KASAN_SHADOW_END (KASAN_SHADOW_START + (1UL << (VA_BITS - 3))) +#define KASAN_SHADOW_END (KASAN_SHADOW_START + KASAN_SHADOW_SIZE) /* * This value is used to map an address to the corresponding shadow @@ -28,10 +29,12 @@ #define KASAN_SHADOW_OFFSET (KASAN_SHADOW_END - (1ULL << (64 - 3))) void kasan_init(void); +void kasan_copy_shadow(pgd_t *pgdir); asmlinkage void kasan_early_init(void); #else static inline void kasan_init(void) { } +static inline void kasan_copy_shadow(pgd_t *pgdir) { } #endif #endif diff -ruw linux-4.4.115/arch/arm64/include/asm/Kbuild linux-4.4.115-fbx/arch/arm64/include/asm/Kbuild --- linux-4.4.115/arch/arm64/include/asm/Kbuild 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/arch/arm64/include/asm/Kbuild 2019-10-29 09:26:22.993196817 +0100 @@ -2,7 +2,6 @@ generic-y += bug.h generic-y += bugs.h -generic-y += checksum.h generic-y += clkdev.h generic-y += cputime.h generic-y += current.h @@ -14,6 +13,7 @@ generic-y += emergency-restart.h generic-y += errno.h generic-y += ftrace.h +generic-y += hash.h generic-y += hw_irq.h generic-y += ioctl.h generic-y += ioctls.h diff -ruw linux-4.4.115/arch/arm64/include/asm/kernel-pgtable.h linux-4.4.115-fbx/arch/arm64/include/asm/kernel-pgtable.h --- linux-4.4.115/arch/arm64/include/asm/kernel-pgtable.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/arch/arm64/include/asm/kernel-pgtable.h 2019-01-22 16:16:21.539228621 +0100 @@ -19,6 +19,8 @@ #ifndef __ASM_KERNEL_PGTABLE_H #define __ASM_KERNEL_PGTABLE_H +#include +#include /* * The linear mapping and the start of memory are both 2M aligned (per @@ -53,6 +55,12 @@ #define SWAPPER_DIR_SIZE (SWAPPER_PGTABLE_LEVELS * PAGE_SIZE) #define IDMAP_DIR_SIZE (IDMAP_PGTABLE_LEVELS * PAGE_SIZE) +#ifdef CONFIG_ARM64_SW_TTBR0_PAN +#define RESERVED_TTBR0_SIZE (PAGE_SIZE) +#else +#define RESERVED_TTBR0_SIZE (0) +#endif + /* Initial memory map size */ #if ARM64_SWAPPER_USES_SECTION_MAPS #define SWAPPER_BLOCK_SHIFT SECTION_SHIFT @@ -70,8 +78,16 @@ /* * Initial memory map attributes. */ -#define SWAPPER_PTE_FLAGS (PTE_TYPE_PAGE | PTE_AF | PTE_SHARED) -#define SWAPPER_PMD_FLAGS (PMD_TYPE_SECT | PMD_SECT_AF | PMD_SECT_S) +#define _SWAPPER_PTE_FLAGS (PTE_TYPE_PAGE | PTE_AF | PTE_SHARED) +#define _SWAPPER_PMD_FLAGS (PMD_TYPE_SECT | PMD_SECT_AF | PMD_SECT_S) + +#ifdef CONFIG_UNMAP_KERNEL_AT_EL0 +#define SWAPPER_PTE_FLAGS (_SWAPPER_PTE_FLAGS | PTE_NG) +#define SWAPPER_PMD_FLAGS (_SWAPPER_PMD_FLAGS | PMD_SECT_NG) +#else +#define SWAPPER_PTE_FLAGS _SWAPPER_PTE_FLAGS +#define SWAPPER_PMD_FLAGS _SWAPPER_PMD_FLAGS +#endif #if ARM64_SWAPPER_USES_SECTION_MAPS #define SWAPPER_MM_MMUFLAGS (PMD_ATTRINDX(MT_NORMAL) | SWAPPER_PMD_FLAGS) @@ -79,5 +95,31 @@ #define SWAPPER_MM_MMUFLAGS (PTE_ATTRINDX(MT_NORMAL) | SWAPPER_PTE_FLAGS) #endif +/* + * To make optimal use of block mappings when laying out the linear + * mapping, round down the base of physical memory to a size that can + * be mapped efficiently, i.e., either PUD_SIZE (4k granule) or PMD_SIZE + * (64k granule), or a multiple that can be mapped using contiguous bits + * in the page tables: 32 * PMD_SIZE (16k granule) + */ +#if defined(CONFIG_ARM64_4K_PAGES) +#define ARM64_MEMSTART_SHIFT PUD_SHIFT +#elif defined(CONFIG_ARM64_16K_PAGES) +#define ARM64_MEMSTART_SHIFT (PMD_SHIFT + 5) +#else +#define ARM64_MEMSTART_SHIFT PMD_SHIFT +#endif + +/* + * sparsemem vmemmap imposes an additional requirement on the alignment of + * memstart_addr, due to the fact that the base of the vmemmap region + * has a direct correspondence, and needs to appear sufficiently aligned + * in the virtual address space. + */ +#if defined(CONFIG_SPARSEMEM_VMEMMAP) && ARM64_MEMSTART_SHIFT < SECTION_SIZE_BITS +#define ARM64_MEMSTART_ALIGN (1UL << SECTION_SIZE_BITS) +#else +#define ARM64_MEMSTART_ALIGN (1UL << ARM64_MEMSTART_SHIFT) +#endif #endif /* __ASM_KERNEL_PGTABLE_H */ diff -ruw linux-4.4.115/arch/arm64/include/asm/kvm_arm.h linux-4.4.115-fbx/arch/arm64/include/asm/kvm_arm.h --- linux-4.4.115/arch/arm64/include/asm/kvm_arm.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/arch/arm64/include/asm/kvm_arm.h 2019-10-29 09:26:22.997196856 +0100 @@ -83,17 +83,6 @@ #define HCR_INT_OVERRIDE (HCR_FMO | HCR_IMO) -/* Hyp System Control Register (SCTLR_EL2) bits */ -#define SCTLR_EL2_EE (1 << 25) -#define SCTLR_EL2_WXN (1 << 19) -#define SCTLR_EL2_I (1 << 12) -#define SCTLR_EL2_SA (1 << 3) -#define SCTLR_EL2_C (1 << 2) -#define SCTLR_EL2_A (1 << 1) -#define SCTLR_EL2_M 1 -#define SCTLR_EL2_FLAGS (SCTLR_EL2_M | SCTLR_EL2_A | SCTLR_EL2_C | \ - SCTLR_EL2_SA | SCTLR_EL2_I) - /* TCR_EL2 Registers bits */ #define TCR_EL2_RES1 ((1 << 31) | (1 << 23)) #define TCR_EL2_TBI (1 << 20) @@ -123,6 +112,7 @@ #define VTCR_EL2_SL0_LVL1 (1 << 6) #define VTCR_EL2_T0SZ_MASK 0x3f #define VTCR_EL2_T0SZ_40B 24 +#define VTCR_EL2_VS 19 /* * We configure the Stage-2 page tables to always restrict the IPA space to be @@ -166,7 +156,7 @@ #define VTTBR_BADDR_MASK (((UL(1) << (PHYS_MASK_SHIFT - VTTBR_X)) - 1) << VTTBR_X) #define VTTBR_VMID_SHIFT (UL(48)) -#define VTTBR_VMID_MASK (UL(0xFF) << VTTBR_VMID_SHIFT) +#define VTTBR_VMID_MASK(size) (_AT(u64, (1 << size) - 1) << VTTBR_VMID_SHIFT) /* Hyp System Trap Register */ #define HSTR_EL2_T(x) (1 << x) diff -ruw linux-4.4.115/arch/arm64/include/asm/kvm_asm.h linux-4.4.115-fbx/arch/arm64/include/asm/kvm_asm.h --- linux-4.4.115/arch/arm64/include/asm/kvm_asm.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/arch/arm64/include/asm/kvm_asm.h 2019-01-22 16:16:21.539228621 +0100 @@ -20,94 +20,38 @@ #include -/* - * 0 is reserved as an invalid value. - * Order *must* be kept in sync with the hyp switch code. - */ -#define MPIDR_EL1 1 /* MultiProcessor Affinity Register */ -#define CSSELR_EL1 2 /* Cache Size Selection Register */ -#define SCTLR_EL1 3 /* System Control Register */ -#define ACTLR_EL1 4 /* Auxiliary Control Register */ -#define CPACR_EL1 5 /* Coprocessor Access Control */ -#define TTBR0_EL1 6 /* Translation Table Base Register 0 */ -#define TTBR1_EL1 7 /* Translation Table Base Register 1 */ -#define TCR_EL1 8 /* Translation Control Register */ -#define ESR_EL1 9 /* Exception Syndrome Register */ -#define AFSR0_EL1 10 /* Auxilary Fault Status Register 0 */ -#define AFSR1_EL1 11 /* Auxilary Fault Status Register 1 */ -#define FAR_EL1 12 /* Fault Address Register */ -#define MAIR_EL1 13 /* Memory Attribute Indirection Register */ -#define VBAR_EL1 14 /* Vector Base Address Register */ -#define CONTEXTIDR_EL1 15 /* Context ID Register */ -#define TPIDR_EL0 16 /* Thread ID, User R/W */ -#define TPIDRRO_EL0 17 /* Thread ID, User R/O */ -#define TPIDR_EL1 18 /* Thread ID, Privileged */ -#define AMAIR_EL1 19 /* Aux Memory Attribute Indirection Register */ -#define CNTKCTL_EL1 20 /* Timer Control Register (EL1) */ -#define PAR_EL1 21 /* Physical Address Register */ -#define MDSCR_EL1 22 /* Monitor Debug System Control Register */ -#define MDCCINT_EL1 23 /* Monitor Debug Comms Channel Interrupt Enable Reg */ - -/* 32bit specific registers. Keep them at the end of the range */ -#define DACR32_EL2 24 /* Domain Access Control Register */ -#define IFSR32_EL2 25 /* Instruction Fault Status Register */ -#define FPEXC32_EL2 26 /* Floating-Point Exception Control Register */ -#define DBGVCR32_EL2 27 /* Debug Vector Catch Register */ -#define NR_SYS_REGS 28 - -/* 32bit mapping */ -#define c0_MPIDR (MPIDR_EL1 * 2) /* MultiProcessor ID Register */ -#define c0_CSSELR (CSSELR_EL1 * 2)/* Cache Size Selection Register */ -#define c1_SCTLR (SCTLR_EL1 * 2) /* System Control Register */ -#define c1_ACTLR (ACTLR_EL1 * 2) /* Auxiliary Control Register */ -#define c1_CPACR (CPACR_EL1 * 2) /* Coprocessor Access Control */ -#define c2_TTBR0 (TTBR0_EL1 * 2) /* Translation Table Base Register 0 */ -#define c2_TTBR0_high (c2_TTBR0 + 1) /* TTBR0 top 32 bits */ -#define c2_TTBR1 (TTBR1_EL1 * 2) /* Translation Table Base Register 1 */ -#define c2_TTBR1_high (c2_TTBR1 + 1) /* TTBR1 top 32 bits */ -#define c2_TTBCR (TCR_EL1 * 2) /* Translation Table Base Control R. */ -#define c3_DACR (DACR32_EL2 * 2)/* Domain Access Control Register */ -#define c5_DFSR (ESR_EL1 * 2) /* Data Fault Status Register */ -#define c5_IFSR (IFSR32_EL2 * 2)/* Instruction Fault Status Register */ -#define c5_ADFSR (AFSR0_EL1 * 2) /* Auxiliary Data Fault Status R */ -#define c5_AIFSR (AFSR1_EL1 * 2) /* Auxiliary Instr Fault Status R */ -#define c6_DFAR (FAR_EL1 * 2) /* Data Fault Address Register */ -#define c6_IFAR (c6_DFAR + 1) /* Instruction Fault Address Register */ -#define c7_PAR (PAR_EL1 * 2) /* Physical Address Register */ -#define c7_PAR_high (c7_PAR + 1) /* PAR top 32 bits */ -#define c10_PRRR (MAIR_EL1 * 2) /* Primary Region Remap Register */ -#define c10_NMRR (c10_PRRR + 1) /* Normal Memory Remap Register */ -#define c12_VBAR (VBAR_EL1 * 2) /* Vector Base Address Register */ -#define c13_CID (CONTEXTIDR_EL1 * 2) /* Context ID Register */ -#define c13_TID_URW (TPIDR_EL0 * 2) /* Thread ID, User R/W */ -#define c13_TID_URO (TPIDRRO_EL0 * 2)/* Thread ID, User R/O */ -#define c13_TID_PRIV (TPIDR_EL1 * 2) /* Thread ID, Privileged */ -#define c10_AMAIR0 (AMAIR_EL1 * 2) /* Aux Memory Attr Indirection Reg */ -#define c10_AMAIR1 (c10_AMAIR0 + 1)/* Aux Memory Attr Indirection Reg */ -#define c14_CNTKCTL (CNTKCTL_EL1 * 2) /* Timer Control Register (PL1) */ - -#define cp14_DBGDSCRext (MDSCR_EL1 * 2) -#define cp14_DBGBCR0 (DBGBCR0_EL1 * 2) -#define cp14_DBGBVR0 (DBGBVR0_EL1 * 2) -#define cp14_DBGBXVR0 (cp14_DBGBVR0 + 1) -#define cp14_DBGWCR0 (DBGWCR0_EL1 * 2) -#define cp14_DBGWVR0 (DBGWVR0_EL1 * 2) -#define cp14_DBGDCCINT (MDCCINT_EL1 * 2) - -#define NR_COPRO_REGS (NR_SYS_REGS * 2) - #define ARM_EXCEPTION_IRQ 0 #define ARM_EXCEPTION_TRAP 1 +/* The hyp-stub will return this for any kvm_call_hyp() call */ +#define ARM_EXCEPTION_HYP_GONE 2 #define KVM_ARM64_DEBUG_DIRTY_SHIFT 0 #define KVM_ARM64_DEBUG_DIRTY (1 << KVM_ARM64_DEBUG_DIRTY_SHIFT) +#define kvm_ksym_ref(sym) phys_to_virt((u64)&sym - kimage_voffset) + #ifndef __ASSEMBLY__ +#if __GNUC__ > 4 +#define kvm_ksym_shift (PAGE_OFFSET - KIMAGE_VADDR) +#else +/* + * GCC versions 4.9 and older will fold the constant below into the addend of + * the reference to 'sym' above if kvm_ksym_shift is declared static or if the + * constant is used directly. However, since we use the small code model for + * the core kernel, the reference to 'sym' will be emitted as a adrp/add pair, + * with a +/- 4 GB range, resulting in linker relocation errors if the shift + * is sufficiently large. So prevent the compiler from folding the shift into + * the addend, by making the shift a variable with external linkage. + */ +__weak u64 kvm_ksym_shift = PAGE_OFFSET - KIMAGE_VADDR; +#endif + struct kvm; struct kvm_vcpu; extern char __kvm_hyp_init[]; extern char __kvm_hyp_init_end[]; +extern char __kvm_hyp_reset[]; extern char __kvm_hyp_vector[]; diff -ruw linux-4.4.115/arch/arm64/include/asm/kvm_host.h linux-4.4.115-fbx/arch/arm64/include/asm/kvm_host.h --- linux-4.4.115/arch/arm64/include/asm/kvm_host.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/arch/arm64/include/asm/kvm_host.h 2019-01-22 16:16:21.539228621 +0100 @@ -25,7 +25,6 @@ #include #include #include -#include #include #define __KVM_HAVE_ARCH_INTC_INITIALIZED @@ -45,6 +44,7 @@ int __attribute_const__ kvm_target_cpu(void); int kvm_reset_vcpu(struct kvm_vcpu *vcpu); int kvm_arch_dev_ioctl_check_extension(long ext); +phys_addr_t kvm_hyp_reset_entry(void); struct kvm_arch { /* The VMID generation used for the virt. memory system */ @@ -85,6 +85,86 @@ u64 hpfar_el2; /* Hyp IPA Fault Address Register */ }; +/* + * 0 is reserved as an invalid value. + * Order should be kept in sync with the save/restore code. + */ +enum vcpu_sysreg { + __INVALID_SYSREG__, + MPIDR_EL1, /* MultiProcessor Affinity Register */ + CSSELR_EL1, /* Cache Size Selection Register */ + SCTLR_EL1, /* System Control Register */ + ACTLR_EL1, /* Auxiliary Control Register */ + CPACR_EL1, /* Coprocessor Access Control */ + TTBR0_EL1, /* Translation Table Base Register 0 */ + TTBR1_EL1, /* Translation Table Base Register 1 */ + TCR_EL1, /* Translation Control Register */ + ESR_EL1, /* Exception Syndrome Register */ + AFSR0_EL1, /* Auxilary Fault Status Register 0 */ + AFSR1_EL1, /* Auxilary Fault Status Register 1 */ + FAR_EL1, /* Fault Address Register */ + MAIR_EL1, /* Memory Attribute Indirection Register */ + VBAR_EL1, /* Vector Base Address Register */ + CONTEXTIDR_EL1, /* Context ID Register */ + TPIDR_EL0, /* Thread ID, User R/W */ + TPIDRRO_EL0, /* Thread ID, User R/O */ + TPIDR_EL1, /* Thread ID, Privileged */ + AMAIR_EL1, /* Aux Memory Attribute Indirection Register */ + CNTKCTL_EL1, /* Timer Control Register (EL1) */ + PAR_EL1, /* Physical Address Register */ + MDSCR_EL1, /* Monitor Debug System Control Register */ + MDCCINT_EL1, /* Monitor Debug Comms Channel Interrupt Enable Reg */ + + /* 32bit specific registers. Keep them at the end of the range */ + DACR32_EL2, /* Domain Access Control Register */ + IFSR32_EL2, /* Instruction Fault Status Register */ + FPEXC32_EL2, /* Floating-Point Exception Control Register */ + DBGVCR32_EL2, /* Debug Vector Catch Register */ + + NR_SYS_REGS /* Nothing after this line! */ +}; + +/* 32bit mapping */ +#define c0_MPIDR (MPIDR_EL1 * 2) /* MultiProcessor ID Register */ +#define c0_CSSELR (CSSELR_EL1 * 2)/* Cache Size Selection Register */ +#define c1_SCTLR (SCTLR_EL1 * 2) /* System Control Register */ +#define c1_ACTLR (ACTLR_EL1 * 2) /* Auxiliary Control Register */ +#define c1_CPACR (CPACR_EL1 * 2) /* Coprocessor Access Control */ +#define c2_TTBR0 (TTBR0_EL1 * 2) /* Translation Table Base Register 0 */ +#define c2_TTBR0_high (c2_TTBR0 + 1) /* TTBR0 top 32 bits */ +#define c2_TTBR1 (TTBR1_EL1 * 2) /* Translation Table Base Register 1 */ +#define c2_TTBR1_high (c2_TTBR1 + 1) /* TTBR1 top 32 bits */ +#define c2_TTBCR (TCR_EL1 * 2) /* Translation Table Base Control R. */ +#define c3_DACR (DACR32_EL2 * 2)/* Domain Access Control Register */ +#define c5_DFSR (ESR_EL1 * 2) /* Data Fault Status Register */ +#define c5_IFSR (IFSR32_EL2 * 2)/* Instruction Fault Status Register */ +#define c5_ADFSR (AFSR0_EL1 * 2) /* Auxiliary Data Fault Status R */ +#define c5_AIFSR (AFSR1_EL1 * 2) /* Auxiliary Instr Fault Status R */ +#define c6_DFAR (FAR_EL1 * 2) /* Data Fault Address Register */ +#define c6_IFAR (c6_DFAR + 1) /* Instruction Fault Address Register */ +#define c7_PAR (PAR_EL1 * 2) /* Physical Address Register */ +#define c7_PAR_high (c7_PAR + 1) /* PAR top 32 bits */ +#define c10_PRRR (MAIR_EL1 * 2) /* Primary Region Remap Register */ +#define c10_NMRR (c10_PRRR + 1) /* Normal Memory Remap Register */ +#define c12_VBAR (VBAR_EL1 * 2) /* Vector Base Address Register */ +#define c13_CID (CONTEXTIDR_EL1 * 2) /* Context ID Register */ +#define c13_TID_URW (TPIDR_EL0 * 2) /* Thread ID, User R/W */ +#define c13_TID_URO (TPIDRRO_EL0 * 2)/* Thread ID, User R/O */ +#define c13_TID_PRIV (TPIDR_EL1 * 2) /* Thread ID, Privileged */ +#define c10_AMAIR0 (AMAIR_EL1 * 2) /* Aux Memory Attr Indirection Reg */ +#define c10_AMAIR1 (c10_AMAIR0 + 1)/* Aux Memory Attr Indirection Reg */ +#define c14_CNTKCTL (CNTKCTL_EL1 * 2) /* Timer Control Register (PL1) */ + +#define cp14_DBGDSCRext (MDSCR_EL1 * 2) +#define cp14_DBGBCR0 (DBGBCR0_EL1 * 2) +#define cp14_DBGBVR0 (DBGBVR0_EL1 * 2) +#define cp14_DBGBXVR0 (cp14_DBGBVR0 + 1) +#define cp14_DBGWCR0 (DBGWCR0_EL1 * 2) +#define cp14_DBGWVR0 (DBGWVR0_EL1 * 2) +#define cp14_DBGDCCINT (MDCCINT_EL1 * 2) + +#define NR_COPRO_REGS (NR_SYS_REGS * 2) + struct kvm_cpu_context { struct kvm_regs gp_regs; union { @@ -222,7 +302,7 @@ struct kvm_vcpu *kvm_arm_get_running_vcpu(void); struct kvm_vcpu * __percpu *kvm_get_running_vcpus(void); -u64 kvm_call_hyp(void *hypfn, ...); +u64 __kvm_call_hyp(void *hypfn, ...); void force_vm_exit(const cpumask_t *mask); void kvm_mmu_wp_memory_region(struct kvm *kvm, int slot); @@ -243,11 +323,25 @@ * Call initialization code, and switch to the full blown * HYP code. */ - kvm_call_hyp((void *)boot_pgd_ptr, pgd_ptr, + __kvm_call_hyp((void *)boot_pgd_ptr, pgd_ptr, hyp_stack_ptr, vector_ptr); } -static inline void kvm_arch_hardware_disable(void) {} +static inline void __cpu_init_stage2(void) +{ +} + +static inline void __cpu_reset_hyp_mode(phys_addr_t boot_pgd_ptr, + phys_addr_t phys_idmap_start) +{ + /* + * Call reset code, and switch back to stub hyp vectors. + * Uses __kvm_call_hyp() to avoid kaslr's kvm_ksym_ref() translation. + */ + __kvm_call_hyp((void *)kvm_hyp_reset_entry(), + boot_pgd_ptr, phys_idmap_start); +} + static inline void kvm_arch_hardware_unsetup(void) {} static inline void kvm_arch_sync_events(struct kvm *kvm) {} static inline void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu) {} @@ -258,4 +352,6 @@ void kvm_arm_clear_debug(struct kvm_vcpu *vcpu); void kvm_arm_reset_debug_ptr(struct kvm_vcpu *vcpu); +#define kvm_call_hyp(f, ...) __kvm_call_hyp(kvm_ksym_ref(f), ##__VA_ARGS__) + #endif /* __ARM64_KVM_HOST_H__ */ diff -ruw linux-4.4.115/arch/arm64/include/asm/kvm_mmio.h linux-4.4.115-fbx/arch/arm64/include/asm/kvm_mmio.h --- linux-4.4.115/arch/arm64/include/asm/kvm_mmio.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/arch/arm64/include/asm/kvm_mmio.h 2019-01-22 16:16:21.539228621 +0100 @@ -19,7 +19,6 @@ #define __ARM64_KVM_MMIO_H__ #include -#include #include /* diff -ruw linux-4.4.115/arch/arm64/include/asm/lse.h linux-4.4.115-fbx/arch/arm64/include/asm/lse.h --- linux-4.4.115/arch/arm64/include/asm/lse.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/arch/arm64/include/asm/lse.h 2019-01-22 16:16:21.539228621 +0100 @@ -26,6 +26,7 @@ /* Macro for constructing calls to out-of-line ll/sc atomics */ #define __LL_SC_CALL(op) "bl\t" __stringify(__LL_SC_PREFIX(op)) "\n" +#define __LL_SC_CLOBBERS "x16", "x17", "x30" /* In-line patching at runtime */ #define ARM64_LSE_ATOMIC_INSN(llsc, lse) \ diff -ruw linux-4.4.115/arch/arm64/include/asm/memory.h linux-4.4.115-fbx/arch/arm64/include/asm/memory.h --- linux-4.4.115/arch/arm64/include/asm/memory.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/arch/arm64/include/asm/memory.h 2019-10-29 09:26:22.997196856 +0100 @@ -24,6 +24,7 @@ #include #include #include +#include #include /* @@ -45,15 +46,15 @@ * VA_START - the first kernel virtual address. * TASK_SIZE - the maximum size of a user space task. * TASK_UNMAPPED_BASE - the lower boundary of the mmap VM area. - * The module space lives between the addresses given by TASK_SIZE - * and PAGE_OFFSET - it must be within 128MB of the kernel text. */ #define VA_BITS (CONFIG_ARM64_VA_BITS) #define VA_START (UL(0xffffffffffffffff) << VA_BITS) #define PAGE_OFFSET (UL(0xffffffffffffffff) << (VA_BITS - 1)) -#define MODULES_END (PAGE_OFFSET) -#define MODULES_VADDR (MODULES_END - SZ_64M) -#define PCI_IO_END (MODULES_VADDR - SZ_2M) +#define KIMAGE_VADDR (MODULES_END) +#define MODULES_END (MODULES_VADDR + MODULES_VSIZE) +#define MODULES_VADDR (VA_START + KASAN_SHADOW_SIZE) +#define MODULES_VSIZE (SZ_128M) +#define PCI_IO_END (PAGE_OFFSET - SZ_2M) #define PCI_IO_START (PCI_IO_END - PCI_IO_SIZE) #define FIXADDR_TOP (PCI_IO_START - SZ_2M) #define TASK_SIZE_64 (UL(1) << VA_BITS) @@ -70,13 +71,31 @@ #define TASK_UNMAPPED_BASE (PAGE_ALIGN(TASK_SIZE / 4)) +#define KERNEL_START _text +#define KERNEL_END _end + +/* + * The size of the KASAN shadow region. This should be 1/8th of the + * size of the entire kernel virtual address space. + */ +#ifdef CONFIG_KASAN +#define KASAN_SHADOW_SIZE (UL(1) << (VA_BITS - 3)) +#else +#define KASAN_SHADOW_SIZE (0) +#endif + /* * Physical vs virtual RAM address space conversion. These are * private definitions which should NOT be used outside memory.h * files. Use virt_to_phys/phys_to_virt/__pa/__va instead. */ -#define __virt_to_phys(x) (((phys_addr_t)(x) - PAGE_OFFSET + PHYS_OFFSET)) -#define __phys_to_virt(x) ((unsigned long)((x) - PHYS_OFFSET + PAGE_OFFSET)) +#define __virt_to_phys(x) ({ \ + phys_addr_t __x = (phys_addr_t)(x); \ + __x & BIT(VA_BITS - 1) ? (__x & ~PAGE_OFFSET) + PHYS_OFFSET : \ + (__x - kimage_voffset); }) + +#define __phys_to_virt(x) ((unsigned long)((x) - PHYS_OFFSET) | PAGE_OFFSET) +#define __phys_to_kimg(x) ((unsigned long)((x) + kimage_voffset)) /* * Convert a page to/from a physical address @@ -100,19 +119,45 @@ #define MT_S2_NORMAL 0xf #define MT_S2_DEVICE_nGnRE 0x1 +#ifdef CONFIG_ARM64_4K_PAGES +#define IOREMAP_MAX_ORDER (PUD_SHIFT) +#else +#define IOREMAP_MAX_ORDER (PMD_SHIFT) +#endif + +#ifdef CONFIG_BLK_DEV_INITRD +#define __early_init_dt_declare_initrd(__start, __end) \ + do { \ + initrd_start = (__start); \ + initrd_end = (__end); \ + } while (0) +#endif + #ifndef __ASSEMBLY__ -extern phys_addr_t memstart_addr; +#include +#include + +extern s64 memstart_addr; /* PHYS_OFFSET - the physical address of the start of memory. */ -#define PHYS_OFFSET ({ memstart_addr; }) +#define PHYS_OFFSET ({ VM_BUG_ON(memstart_addr & 1); memstart_addr; }) + +/* the virtual base of the kernel image (minus TEXT_OFFSET) */ +extern u64 kimage_vaddr; + +/* the offset between the kernel virtual and physical mappings */ +extern u64 kimage_voffset; + +static inline unsigned long kaslr_offset(void) +{ + return kimage_vaddr - KIMAGE_VADDR; +} /* - * The maximum physical address that the linear direct mapping - * of system RAM can cover. (PAGE_OFFSET can be interpreted as - * a 2's complement signed quantity and negated to derive the - * maximum size of the linear mapping.) + * Allow all memory at the discovery stage. We will clip it later. */ -#define MAX_MEMBLOCK_ADDR ({ memstart_addr - PAGE_OFFSET - 1; }) +#define MIN_MEMBLOCK_ADDR 0 +#define MAX_MEMBLOCK_ADDR U64_MAX /* * PFNs are used to describe any physical page; this means @@ -148,6 +193,7 @@ #define __va(x) ((void *)__phys_to_virt((phys_addr_t)(x))) #define pfn_to_kaddr(pfn) __va((pfn) << PAGE_SHIFT) #define virt_to_pfn(x) __phys_to_pfn(__virt_to_phys(x)) +#define sym_to_pfn(x) __phys_to_pfn(__pa_symbol(x)) /* * virt_to_page(k) convert a _valid_ virtual address to struct page * @@ -156,7 +202,11 @@ #define ARCH_PFN_OFFSET ((unsigned long)PHYS_PFN_OFFSET) #define virt_to_page(kaddr) pfn_to_page(__pa(kaddr) >> PAGE_SHIFT) -#define virt_addr_valid(kaddr) pfn_valid(__pa(kaddr) >> PAGE_SHIFT) +#define _virt_addr_valid(kaddr) pfn_valid(__pa(kaddr) >> PAGE_SHIFT) + +#define _virt_addr_is_linear(kaddr) (((u64)(kaddr)) >= PAGE_OFFSET) +#define virt_addr_valid(kaddr) (_virt_addr_is_linear(kaddr) && \ + _virt_addr_valid(kaddr)) #endif diff -ruw linux-4.4.115/arch/arm64/include/asm/mmu_context.h linux-4.4.115-fbx/arch/arm64/include/asm/mmu_context.h --- linux-4.4.115/arch/arm64/include/asm/mmu_context.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/arch/arm64/include/asm/mmu_context.h 2019-01-22 16:16:21.539228621 +0100 @@ -23,23 +23,30 @@ #include #include +#include #include #include #include #include +#include +#include #ifdef CONFIG_PID_IN_CONTEXTIDR static inline void contextidr_thread_switch(struct task_struct *next) { + pid_t pid = task_pid_nr(next); asm( " msr contextidr_el1, %0\n" " isb" : - : "r" (task_pid_nr(next))); + : "r" (pid)); + uncached_logk(LOGK_CTXID, (void *)(u64)pid); + } #else static inline void contextidr_thread_switch(struct task_struct *next) { + uncached_logk(LOGK_CTXID, (void *)(u64)task_pid_nr(next)); } #endif @@ -48,7 +55,7 @@ */ static inline void cpu_set_reserved_ttbr0(void) { - unsigned long ttbr = page_to_phys(empty_zero_page); + unsigned long ttbr = __pa_symbol(empty_zero_page); asm( " msr ttbr0_el1, %0 // set TTBR0\n" @@ -57,6 +64,13 @@ : "r" (ttbr)); } +static inline void cpu_switch_mm(pgd_t *pgd, struct mm_struct *mm) +{ + BUG_ON(pgd == swapper_pg_dir); + cpu_set_reserved_ttbr0(); + cpu_do_switch_mm(virt_to_phys(pgd),mm); +} + /* * TCR.T0SZ value to use when the ID map is active. Usually equals * TCR_T0SZ(VA_BITS), unless system RAM is positioned very high in @@ -73,7 +87,7 @@ /* * Set TCR.T0SZ to its default value (based on VA_BITS) */ -static inline void cpu_set_default_tcr_t0sz(void) +static inline void __cpu_set_tcr_t0sz(unsigned long t0sz) { unsigned long tcr; @@ -86,7 +100,62 @@ " msr tcr_el1, %0 ;" " isb" : "=&r" (tcr) - : "r"(TCR_T0SZ(VA_BITS)), "I"(TCR_T0SZ_OFFSET), "I"(TCR_TxSZ_WIDTH)); + : "r"(t0sz), "I"(TCR_T0SZ_OFFSET), "I"(TCR_TxSZ_WIDTH)); +} + +#define cpu_set_default_tcr_t0sz() __cpu_set_tcr_t0sz(TCR_T0SZ(VA_BITS)) +#define cpu_set_idmap_tcr_t0sz() __cpu_set_tcr_t0sz(idmap_t0sz) + +/* + * Remove the idmap from TTBR0_EL1 and install the pgd of the active mm. + * + * The idmap lives in the same VA range as userspace, but uses global entries + * and may use a different TCR_EL1.T0SZ. To avoid issues resulting from + * speculative TLB fetches, we must temporarily install the reserved page + * tables while we invalidate the TLBs and set up the correct TCR_EL1.T0SZ. + * + * If current is a not a user task, the mm covers the TTBR1_EL1 page tables, + * which should not be installed in TTBR0_EL1. In this case we can leave the + * reserved page tables in place. + */ +static inline void cpu_uninstall_idmap(void) +{ + struct mm_struct *mm = current->active_mm; + + cpu_set_reserved_ttbr0(); + local_flush_tlb_all(); + cpu_set_default_tcr_t0sz(); + + if (mm != &init_mm && !system_uses_ttbr0_pan()) + cpu_switch_mm(mm->pgd, mm); +} + +static inline void cpu_install_idmap(void) +{ + cpu_set_reserved_ttbr0(); + local_flush_tlb_all(); + cpu_set_idmap_tcr_t0sz(); + + cpu_switch_mm(lm_alias(idmap_pg_dir), &init_mm); +} + +/* + * Atomically replaces the active TTBR1_EL1 PGD with a new VA-compatible PGD, + * avoiding the possibility of conflicting TLB entries being allocated. + */ +static inline void cpu_replace_ttbr1(pgd_t *pgd) +{ + typedef void (ttbr_replace_func)(phys_addr_t); + extern ttbr_replace_func idmap_cpu_replace_ttbr1; + ttbr_replace_func *replace_phys; + + phys_addr_t pgd_phys = virt_to_phys(pgd); + + replace_phys = (void *)__pa_symbol(idmap_cpu_replace_ttbr1); + + cpu_install_idmap(); + replace_phys(pgd_phys); + cpu_uninstall_idmap(); } /* @@ -103,35 +172,43 @@ #define init_new_context(tsk,mm) ({ atomic64_set(&(mm)->context.id, 0); 0; }) -/* - * This is called when "tsk" is about to enter lazy TLB mode. - * - * mm: describes the currently active mm context - * tsk: task which is entering lazy tlb - * cpu: cpu number which is entering lazy tlb - * - * tsk->mm will be NULL - */ -static inline void -enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk) +#ifdef CONFIG_ARM64_SW_TTBR0_PAN +static inline void update_saved_ttbr0(struct task_struct *tsk, + struct mm_struct *mm) +{ + u64 ttbr; + + if (!system_uses_ttbr0_pan()) + return; + + if (mm == &init_mm) + ttbr = __pa_symbol(empty_zero_page); + else + ttbr = virt_to_phys(mm->pgd) | ASID(mm) << 48; + + WRITE_ONCE(task_thread_info(tsk)->ttbr0, ttbr); +} +#else +static inline void update_saved_ttbr0(struct task_struct *tsk, + struct mm_struct *mm) { } +#endif +static inline void +enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk) +{ /* - * This is the actual mm switch as far as the scheduler - * is concerned. No registers are touched. We avoid - * calling the CPU specific function when the mm hasn't - * actually changed. + * We don't actually care about the ttbr0 mapping, so point it at the + * zero page. */ -static inline void -switch_mm(struct mm_struct *prev, struct mm_struct *next, - struct task_struct *tsk) + update_saved_ttbr0(tsk, &init_mm); +} + +static inline void __switch_mm(struct mm_struct *next) { unsigned int cpu = smp_processor_id(); - if (prev == next) - return; - /* * init_mm.pgd does not contain any user mappings and it is always * active for kernel addresses in TTBR1. Just set the reserved TTBR0. @@ -144,7 +221,25 @@ check_and_switch_context(next, cpu); } +static inline void +switch_mm(struct mm_struct *prev, struct mm_struct *next, + struct task_struct *tsk) +{ + if (prev != next) + __switch_mm(next); + + /* + * Update the saved TTBR0_EL1 of the scheduled-in task as the previous + * value may have not been initialised yet (activate_mm caller) or the + * ASID has changed since the last run (following the context switch + * of another thread of the same process). + */ + update_saved_ttbr0(tsk, next); +} + #define deactivate_mm(tsk,mm) do { } while (0) -#define activate_mm(prev,next) switch_mm(prev, next, NULL) +#define activate_mm(prev,next) switch_mm(prev, next, current) + +void post_ttbr_update_workaround(void); #endif diff -ruw linux-4.4.115/arch/arm64/include/asm/mmu.h linux-4.4.115-fbx/arch/arm64/include/asm/mmu.h --- linux-4.4.115/arch/arm64/include/asm/mmu.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/arch/arm64/include/asm/mmu.h 2019-01-22 16:16:21.539228621 +0100 @@ -16,6 +16,15 @@ #ifndef __ASM_MMU_H #define __ASM_MMU_H +#define USER_ASID_FLAG (UL(1) << 48) +#define TTBR_ASID_MASK (UL(0xffff) << 48) + +#ifndef __ASSEMBLY__ +#include + +#include +#include + typedef struct { atomic64_t id; void *vdso; @@ -28,6 +37,49 @@ */ #define ASID(mm) ((mm)->context.id.counter & 0xffff) +static inline bool arm64_kernel_unmapped_at_el0(void) +{ + return IS_ENABLED(CONFIG_UNMAP_KERNEL_AT_EL0) && + cpus_have_cap(ARM64_UNMAP_KERNEL_AT_EL0); +} + +typedef void (*bp_hardening_cb_t)(void); + +struct bp_hardening_data { + int hyp_vectors_slot; + bp_hardening_cb_t fn; +}; + +#ifdef CONFIG_HARDEN_BRANCH_PREDICTOR +extern char __bp_harden_hyp_vecs_start[], __bp_harden_hyp_vecs_end[]; + +DECLARE_PER_CPU_READ_MOSTLY(struct bp_hardening_data, bp_hardening_data); + +static inline struct bp_hardening_data *arm64_get_bp_hardening_data(void) +{ + return this_cpu_ptr(&bp_hardening_data); +} + +static inline void arm64_apply_bp_hardening(void) +{ + struct bp_hardening_data *d; + + if (!cpus_have_cap(ARM64_HARDEN_BRANCH_PREDICTOR)) + return; + + d = arm64_get_bp_hardening_data(); + if (d->fn) + d->fn(); +} +#else +static inline struct bp_hardening_data *arm64_get_bp_hardening_data(void) +{ + return NULL; +} + +static inline void arm64_apply_bp_hardening(void) { } +#endif /* CONFIG_HARDEN_BRANCH_PREDICTOR */ + extern void paging_init(void); extern void __iomem *early_io_map(phys_addr_t phys, unsigned long virt); extern void init_mem_pgprot(void); @@ -35,5 +87,13 @@ unsigned long virt, phys_addr_t size, pgprot_t prot); extern void *fixmap_remap_fdt(phys_addr_t dt_phys); +#ifdef CONFIG_MEMORY_HOTPLUG +extern void hotplug_paging(phys_addr_t start, phys_addr_t size); +#ifdef CONFIG_MEMORY_HOTREMOVE +extern void remove_pagetable(unsigned long start, + unsigned long end, bool direct); +#endif +#endif +#endif /* !__ASSEMBLY__ */ #endif diff -ruw linux-4.4.115/arch/arm64/include/asm/module.h linux-4.4.115-fbx/arch/arm64/include/asm/module.h --- linux-4.4.115/arch/arm64/include/asm/module.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/arch/arm64/include/asm/module.h 2019-01-22 16:16:21.539228621 +0100 @@ -17,7 +17,29 @@ #define __ASM_MODULE_H #include +#include #define MODULE_ARCH_VERMAGIC "aarch64" +#ifdef CONFIG_ARM64_MODULE_PLTS +struct mod_arch_specific { + struct elf64_shdr *plt; + int plt_num_entries; + int plt_max_entries; +}; +#endif + +u64 module_emit_plt_entry(struct module *mod, const Elf64_Rela *rela, + Elf64_Sym *sym); + +#ifdef CONFIG_RANDOMIZE_BASE +#ifdef CONFIG_MODVERSIONS +#define ARCH_RELOCATES_KCRCTAB +#define reloc_start (kimage_vaddr - KIMAGE_VADDR) +#endif +extern u64 module_alloc_base; +#else +#define module_alloc_base ((u64)_etext - MODULES_VSIZE) +#endif + #endif /* __ASM_MODULE_H */ diff -ruw linux-4.4.115/arch/arm64/include/asm/page.h linux-4.4.115-fbx/arch/arm64/include/asm/page.h --- linux-4.4.115/arch/arm64/include/asm/page.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/arch/arm64/include/asm/page.h 2019-01-22 16:16:21.539228621 +0100 @@ -19,6 +19,8 @@ #ifndef __ASM_PAGE_H #define __ASM_PAGE_H +#include + /* PAGE_SHIFT determines the page size */ /* CONT_SHIFT determines the number of pages which can be tracked together */ #ifdef CONFIG_ARM64_64K_PAGES diff -ruw linux-4.4.115/arch/arm64/include/asm/pci.h linux-4.4.115-fbx/arch/arm64/include/asm/pci.h --- linux-4.4.115/arch/arm64/include/asm/pci.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/arch/arm64/include/asm/pci.h 2019-01-22 16:16:21.543228657 +0100 @@ -41,3 +41,8 @@ #endif /* __KERNEL__ */ #endif /* __ASM_PCI_H */ + +#ifdef CONFIG_PCI_MSM +#define arch_setup_msi_irqs arch_setup_msi_irqs +#define arch_teardown_msi_irqs arch_teardown_msi_irqs +#endif diff -ruw linux-4.4.115/arch/arm64/include/asm/percpu.h linux-4.4.115-fbx/arch/arm64/include/asm/percpu.h --- linux-4.4.115/arch/arm64/include/asm/percpu.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/arch/arm64/include/asm/percpu.h 2019-10-29 09:26:22.997196856 +0100 @@ -16,6 +16,8 @@ #ifndef __ASM_PERCPU_H #define __ASM_PERCPU_H +#include + static inline void set_my_cpu_offset(unsigned long off) { asm volatile("msr tpidr_el1, %0" :: "r" (off) : "memory"); diff -ruw linux-4.4.115/arch/arm64/include/asm/perf_event.h linux-4.4.115-fbx/arch/arm64/include/asm/perf_event.h --- linux-4.4.115/arch/arm64/include/asm/perf_event.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/arch/arm64/include/asm/perf_event.h 2019-01-22 16:16:21.543228657 +0100 @@ -17,6 +17,8 @@ #ifndef __ASM_PERF_EVENT_H #define __ASM_PERF_EVENT_H +#include + #ifdef CONFIG_PERF_EVENTS struct pt_regs; extern unsigned long perf_instruction_pointer(struct pt_regs *regs); @@ -31,4 +33,91 @@ (regs)->pstate = PSR_MODE_EL1h; \ } +static inline u32 armv8pmu_pmcr_read_reg(void) +{ + u32 val; + + asm volatile("mrs %0, pmcr_el0" : "=r" (val)); + return val; +} + +static inline u32 armv8pmu_pmccntr_read_reg(void) +{ + u32 val; + + asm volatile("mrs %0, pmccntr_el0" : "=r" (val)); + return val; +} + +static inline u32 armv8pmu_pmxevcntr_read_reg(void) +{ + u32 val; + + asm volatile("mrs %0, pmxevcntr_el0" : "=r" (val)); + return val; +} + +static inline u32 armv8pmu_pmovsclr_read_reg(void) +{ + u32 val; + + asm volatile("mrs %0, pmovsclr_el0" : "=r" (val)); + return val; +} + +static inline void armv8pmu_pmcr_write_reg(u32 val) +{ + asm volatile("msr pmcr_el0, %0" :: "r" (val)); +} + +static inline void armv8pmu_pmselr_write_reg(u32 val) +{ + asm volatile("msr pmselr_el0, %0" :: "r" (val)); +} + +static inline void armv8pmu_pmccntr_write_reg(u32 val) +{ + asm volatile("msr pmccntr_el0, %0" :: "r" (val)); +} + +static inline void armv8pmu_pmxevcntr_write_reg(u32 val) +{ + asm volatile("msr pmxevcntr_el0, %0" :: "r" (val)); +} + +static inline void armv8pmu_pmxevtyper_write_reg(u32 val) +{ + asm volatile("msr pmxevtyper_el0, %0" :: "r" (val)); +} + +static inline void armv8pmu_pmcntenset_write_reg(u32 val) +{ + asm volatile("msr pmcntenset_el0, %0" :: "r" (val)); +} + +static inline void armv8pmu_pmcntenclr_write_reg(u32 val) +{ + asm volatile("msr pmcntenclr_el0, %0" :: "r" (val)); +} + +static inline void armv8pmu_pmintenset_write_reg(u32 val) +{ + asm volatile("msr pmintenset_el1, %0" :: "r" (val)); +} + +static inline void armv8pmu_pmintenclr_write_reg(u32 val) +{ + asm volatile("msr pmintenclr_el1, %0" :: "r" (val)); +} + +static inline void armv8pmu_pmovsclr_write_reg(u32 val) +{ + asm volatile("msr pmovsclr_el0, %0" :: "r" (val)); +} + +static inline void armv8pmu_pmuserenr_write_reg(u32 val) +{ + asm volatile("msr pmuserenr_el0, %0" :: "r" (val)); +} + #endif diff -ruw linux-4.4.115/arch/arm64/include/asm/pgalloc.h linux-4.4.115-fbx/arch/arm64/include/asm/pgalloc.h --- linux-4.4.115/arch/arm64/include/asm/pgalloc.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/arch/arm64/include/asm/pgalloc.h 2019-01-22 16:16:21.543228657 +0100 @@ -42,11 +42,20 @@ free_page((unsigned long)pmd); } -static inline void pud_populate(struct mm_struct *mm, pud_t *pud, pmd_t *pmd) +static inline void __pud_populate(pud_t *pud, phys_addr_t pmd, pudval_t prot) { - set_pud(pud, __pud(__pa(pmd) | PMD_TYPE_TABLE)); + set_pud(pud, __pud(pmd | prot)); } +static inline void pud_populate(struct mm_struct *mm, pud_t *pud, pmd_t *pmd) +{ + __pud_populate(pud, __pa(pmd), PMD_TYPE_TABLE); +} +#else +static inline void __pud_populate(pud_t *pud, phys_addr_t pmd, pudval_t prot) +{ + BUILD_BUG(); +} #endif /* CONFIG_PGTABLE_LEVELS > 2 */ #if CONFIG_PGTABLE_LEVELS > 3 @@ -62,11 +71,20 @@ free_page((unsigned long)pud); } -static inline void pgd_populate(struct mm_struct *mm, pgd_t *pgd, pud_t *pud) +static inline void __pgd_populate(pgd_t *pgdp, phys_addr_t pud, pgdval_t prot) { - set_pgd(pgd, __pgd(__pa(pud) | PUD_TYPE_TABLE)); + set_pgd(pgdp, __pgd(pud | prot)); } +static inline void pgd_populate(struct mm_struct *mm, pgd_t *pgd, pud_t *pud) +{ + __pgd_populate(pgd, __pa(pud), PUD_TYPE_TABLE); +} +#else +static inline void __pgd_populate(pgd_t *pgdp, phys_addr_t pud, pgdval_t prot) +{ + BUILD_BUG(); +} #endif /* CONFIG_PGTABLE_LEVELS > 3 */ extern pgd_t *pgd_alloc(struct mm_struct *mm); diff -ruw linux-4.4.115/arch/arm64/include/asm/pgtable.h linux-4.4.115-fbx/arch/arm64/include/asm/pgtable.h --- linux-4.4.115/arch/arm64/include/asm/pgtable.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/arch/arm64/include/asm/pgtable.h 2019-10-29 09:26:22.997196856 +0100 @@ -19,6 +19,7 @@ #include #include +#include #include #include @@ -36,19 +37,13 @@ * * VMEMAP_SIZE: allows the whole linear region to be covered by a struct page array * (rounded up to PUD_SIZE). - * VMALLOC_START: beginning of the kernel VA space + * VMALLOC_START: beginning of the kernel vmalloc space * VMALLOC_END: extends to the available space below vmmemmap, PCI I/O space, * fixed mappings and modules */ #define VMEMMAP_SIZE ALIGN((1UL << (VA_BITS - PAGE_SHIFT)) * sizeof(struct page), PUD_SIZE) -#ifndef CONFIG_KASAN -#define VMALLOC_START (VA_START) -#else -#include -#define VMALLOC_START (KASAN_SHADOW_END + SZ_64K) -#endif - +#define VMALLOC_START (MODULES_END) #define VMALLOC_END (PAGE_OFFSET - PUD_SIZE - VMEMMAP_SIZE - SZ_64K) #define VMEMMAP_START (VMALLOC_END + SZ_64K) @@ -59,6 +54,7 @@ #ifndef __ASSEMBLY__ +#include #include extern void __pte_error(const char *file, int line, unsigned long val); @@ -66,8 +62,16 @@ extern void __pud_error(const char *file, int line, unsigned long val); extern void __pgd_error(const char *file, int line, unsigned long val); -#define PROT_DEFAULT (PTE_TYPE_PAGE | PTE_AF | PTE_SHARED) -#define PROT_SECT_DEFAULT (PMD_TYPE_SECT | PMD_SECT_AF | PMD_SECT_S) +#define _PROT_DEFAULT (PTE_TYPE_PAGE | PTE_AF | PTE_SHARED) +#define _PROT_SECT_DEFAULT (PMD_TYPE_SECT | PMD_SECT_AF | PMD_SECT_S) + +#ifdef CONFIG_UNMAP_KERNEL_AT_EL0 +#define PROT_DEFAULT (_PROT_DEFAULT | PTE_NG) +#define PROT_SECT_DEFAULT (_PROT_SECT_DEFAULT | PMD_SECT_NG) +#else +#define PROT_DEFAULT _PROT_DEFAULT +#define PROT_SECT_DEFAULT _PROT_SECT_DEFAULT +#endif /* CONFIG_UNMAP_KERNEL_AT_EL0 */ #define PROT_DEVICE_nGnRnE (PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_DIRTY | PTE_WRITE | PTE_ATTRINDX(MT_DEVICE_nGnRnE)) #define PROT_DEVICE_nGnRE (PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_DIRTY | PTE_WRITE | PTE_ATTRINDX(MT_DEVICE_nGnRE)) @@ -80,6 +84,7 @@ #define PROT_SECT_NORMAL_EXEC (PROT_SECT_DEFAULT | PMD_SECT_UXN | PMD_ATTRINDX(MT_NORMAL)) #define _PAGE_DEFAULT (PROT_DEFAULT | PTE_ATTRINDX(MT_NORMAL)) +#define _HYP_PAGE_DEFAULT (_PAGE_DEFAULT & ~PTE_NG) #define PAGE_KERNEL __pgprot(_PAGE_DEFAULT | PTE_PXN | PTE_UXN | PTE_DIRTY | PTE_WRITE) #define PAGE_KERNEL_RO __pgprot(_PAGE_DEFAULT | PTE_PXN | PTE_UXN | PTE_DIRTY | PTE_RDONLY) @@ -87,13 +92,13 @@ #define PAGE_KERNEL_EXEC __pgprot(_PAGE_DEFAULT | PTE_UXN | PTE_DIRTY | PTE_WRITE) #define PAGE_KERNEL_EXEC_CONT __pgprot(_PAGE_DEFAULT | PTE_UXN | PTE_DIRTY | PTE_WRITE | PTE_CONT) -#define PAGE_HYP __pgprot(_PAGE_DEFAULT | PTE_HYP) +#define PAGE_HYP __pgprot(_HYP_PAGE_DEFAULT | PTE_HYP) #define PAGE_HYP_DEVICE __pgprot(PROT_DEVICE_nGnRE | PTE_HYP) #define PAGE_S2 __pgprot(PROT_DEFAULT | PTE_S2_MEMATTR(MT_S2_NORMAL) | PTE_S2_RDONLY) #define PAGE_S2_DEVICE __pgprot(PROT_DEFAULT | PTE_S2_MEMATTR(MT_S2_DEVICE_nGnRE) | PTE_S2_RDONLY | PTE_UXN) -#define PAGE_NONE __pgprot(((_PAGE_DEFAULT) & ~PTE_VALID) | PTE_PROT_NONE | PTE_PXN | PTE_UXN) +#define PAGE_NONE __pgprot(((_PAGE_DEFAULT) & ~PTE_VALID) | PTE_PROT_NONE | PTE_NG | PTE_PXN | PTE_UXN) #define PAGE_SHARED __pgprot(_PAGE_DEFAULT | PTE_USER | PTE_NG | PTE_PXN | PTE_UXN | PTE_WRITE) #define PAGE_SHARED_EXEC __pgprot(_PAGE_DEFAULT | PTE_USER | PTE_NG | PTE_PXN | PTE_WRITE) #define PAGE_COPY __pgprot(_PAGE_DEFAULT | PTE_USER | PTE_NG | PTE_PXN | PTE_UXN) @@ -123,8 +128,8 @@ * ZERO_PAGE is a global shared page that is always zero: used * for zero-mapped memory areas etc.. */ -extern struct page *empty_zero_page; -#define ZERO_PAGE(vaddr) (empty_zero_page) +extern unsigned long empty_zero_page[PAGE_SIZE / sizeof(unsigned long)]; +#define ZERO_PAGE(vaddr) phys_to_page(__pa_symbol(empty_zero_page)) #define pte_ERROR(pte) __pte_error(__FILE__, __LINE__, pte_val(pte)) @@ -136,16 +141,6 @@ #define pte_clear(mm,addr,ptep) set_pte(ptep, __pte(0)) #define pte_page(pte) (pfn_to_page(pte_pfn(pte))) -/* Find an entry in the third-level page table. */ -#define pte_index(addr) (((addr) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1)) - -#define pte_offset_kernel(dir,addr) (pmd_page_vaddr(*(dir)) + pte_index(addr)) - -#define pte_offset_map(dir,addr) pte_offset_kernel((dir), (addr)) -#define pte_offset_map_nested(dir,addr) pte_offset_kernel((dir), (addr)) -#define pte_unmap(pte) do { } while (0) -#define pte_unmap_nested(pte) do { } while (0) - /* * The following only work if pte_present(). Undefined behaviour otherwise. */ @@ -168,6 +163,16 @@ #define pte_valid(pte) (!!(pte_val(pte) & PTE_VALID)) #define pte_valid_not_user(pte) \ ((pte_val(pte) & (PTE_VALID | PTE_USER)) == PTE_VALID) +#define pte_valid_young(pte) \ + ((pte_val(pte) & (PTE_VALID | PTE_AF)) == (PTE_VALID | PTE_AF)) + +/* + * Could the pte be present in the TLB? We must check mm_tlb_flush_pending + * so that we don't erroneously return false for pages that have been + * remapped as PROT_NONE but are yet to be flushed from the TLB. + */ +#define pte_accessible(mm, pte) \ + (mm_tlb_flush_pending(mm) ? pte_present(pte) : pte_valid_young(pte)) static inline pte_t clear_pte_bit(pte_t pte, pgprot_t prot) { @@ -218,7 +223,8 @@ static inline pte_t pte_mkcont(pte_t pte) { - return set_pte_bit(pte, __pgprot(PTE_CONT)); + pte = set_pte_bit(pte, __pgprot(PTE_CONT)); + return set_pte_bit(pte, __pgprot(PTE_TYPE_PAGE)); } static inline pte_t pte_mknoncont(pte_t pte) @@ -226,8 +232,41 @@ return clear_pte_bit(pte, __pgprot(PTE_CONT)); } +static inline pmd_t pmd_mkcont(pmd_t pmd) +{ + return __pmd(pmd_val(pmd) | PMD_SECT_CONT); +} + static inline void set_pte(pte_t *ptep, pte_t pte) { +#ifdef CONFIG_ARM64_STRICT_BREAK_BEFORE_MAKE + pteval_t old = pte_val(*ptep); + pteval_t new = pte_val(pte); + + /* Only problematic if valid -> valid */ + if (!(old & new & PTE_VALID)) + goto pte_ok; + + /* Changing attributes should go via an invalid entry */ + if (WARN_ON((old & PTE_ATTRINDX_MASK) != (new & PTE_ATTRINDX_MASK))) + goto pte_bad; + + /* Change of OA is only an issue if one mapping is writable */ + if (!(old & new & PTE_RDONLY) && + WARN_ON(pte_pfn(*ptep) != pte_pfn(pte))) + goto pte_bad; + + goto pte_ok; + +pte_bad: + *ptep = __pte(0); + dsb(ishst); + asm("tlbi vmalle1is"); + dsb(ish); + isb(); +pte_ok: +#endif + *ptep = pte; /* @@ -299,7 +338,7 @@ /* * Hugetlb definitions. */ -#define HUGE_MAX_HSTATE 2 +#define HUGE_MAX_HSTATE 4 #define HPAGE_SHIFT PMD_SHIFT #define HPAGE_SIZE (_AC(1, UL) << HPAGE_SHIFT) #define HPAGE_MASK (~(HPAGE_SIZE - 1)) @@ -354,6 +393,7 @@ #define pmd_mksplitting(pmd) pte_pmd(pte_mkspecial(pmd_pte(pmd))) #define pmd_mkold(pmd) pte_pmd(pte_mkold(pmd_pte(pmd))) #define pmd_mkwrite(pmd) pte_pmd(pte_mkwrite(pmd_pte(pmd))) +#define pmd_mkclean(pmd) pte_pmd(pte_mkclean(pmd_pte(pmd))) #define pmd_mkdirty(pmd) pte_pmd(pte_mkdirty(pmd_pte(pmd))) #define pmd_mkyoung(pmd) pte_pmd(pte_mkyoung(pmd_pte(pmd))) #define pmd_mknotpresent(pmd) (__pmd(pmd_val(pmd) & ~PMD_SECT_VALID)) @@ -425,13 +465,36 @@ set_pmd(pmdp, __pmd(0)); } -static inline pte_t *pmd_page_vaddr(pmd_t pmd) +static inline phys_addr_t pmd_page_paddr(pmd_t pmd) +{ + return pmd_val(pmd) & PHYS_MASK & (s32)PAGE_MASK; +} + +static inline unsigned long pmd_page_vaddr(pmd_t pmd) { - return __va(pmd_val(pmd) & PHYS_MASK & (s32)PAGE_MASK); + return (unsigned long) __va(pmd_page_paddr(pmd)); } +/* Find an entry in the third-level page table. */ +#define pte_index(addr) (((addr) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1)) + +#define pte_offset_phys(dir,addr) (pmd_page_paddr(*(dir)) + pte_index(addr) * sizeof(pte_t)) +#define pte_offset_kernel(dir,addr) ((pte_t *)__va(pte_offset_phys((dir), (addr)))) + +#define pte_offset_map(dir,addr) pte_offset_kernel((dir), (addr)) +#define pte_offset_map_nested(dir,addr) pte_offset_kernel((dir), (addr)) +#define pte_unmap(pte) do { } while (0) +#define pte_unmap_nested(pte) do { } while (0) + +#define pte_set_fixmap(addr) ((pte_t *)set_fixmap_offset(FIX_PTE, addr)) +#define pte_set_fixmap_offset(pmd, addr) pte_set_fixmap(pte_offset_phys(pmd, addr)) +#define pte_clear_fixmap() clear_fixmap(FIX_PTE) + #define pmd_page(pmd) pfn_to_page(__phys_to_pfn(pmd_val(pmd) & PHYS_MASK)) +/* use ONLY for statically allocated translation tables */ +#define pte_offset_kimg(dir,addr) ((pte_t *)__phys_to_kimg(pte_offset_phys((dir), (addr)))) + /* * Conversion functions: convert a page and protection to a page entry, * and a page entry and page directory to the page they refer to. @@ -458,21 +521,42 @@ set_pud(pudp, __pud(0)); } -static inline pmd_t *pud_page_vaddr(pud_t pud) +static inline phys_addr_t pud_page_paddr(pud_t pud) { - return __va(pud_val(pud) & PHYS_MASK & (s32)PAGE_MASK); + return pud_val(pud) & PHYS_MASK & (s32)PAGE_MASK; +} + +static inline unsigned long pud_page_vaddr(pud_t pud) +{ + return (unsigned long) __va(pud_page_paddr(pud)); } /* Find an entry in the second-level page table. */ #define pmd_index(addr) (((addr) >> PMD_SHIFT) & (PTRS_PER_PMD - 1)) -static inline pmd_t *pmd_offset(pud_t *pud, unsigned long addr) -{ - return (pmd_t *)pud_page_vaddr(*pud) + pmd_index(addr); -} +#define pmd_offset_phys(dir, addr) (pud_page_paddr(*(dir)) + pmd_index(addr) * sizeof(pmd_t)) +#define pmd_offset(dir, addr) ((pmd_t *)__va(pmd_offset_phys((dir), (addr)))) + +#define pmd_set_fixmap(addr) ((pmd_t *)set_fixmap_offset(FIX_PMD, addr)) +#define pmd_set_fixmap_offset(pud, addr) pmd_set_fixmap(pmd_offset_phys(pud, addr)) +#define pmd_clear_fixmap() clear_fixmap(FIX_PMD) #define pud_page(pud) pfn_to_page(__phys_to_pfn(pud_val(pud) & PHYS_MASK)) +/* use ONLY for statically allocated translation tables */ +#define pmd_offset_kimg(dir,addr) ((pmd_t *)__phys_to_kimg(pmd_offset_phys((dir), (addr)))) + +#else + +#define pud_page_paddr(pud) ({ BUILD_BUG(); 0; }) + +/* Match pmd_offset folding in */ +#define pmd_set_fixmap(addr) NULL +#define pmd_set_fixmap_offset(pudp, addr) ((pmd_t *)pudp) +#define pmd_clear_fixmap() + +#define pmd_offset_kimg(dir,addr) ((pmd_t *)dir) + #endif /* CONFIG_PGTABLE_LEVELS > 2 */ #if CONFIG_PGTABLE_LEVELS > 3 @@ -494,21 +578,42 @@ set_pgd(pgdp, __pgd(0)); } -static inline pud_t *pgd_page_vaddr(pgd_t pgd) +static inline phys_addr_t pgd_page_paddr(pgd_t pgd) +{ + return pgd_val(pgd) & PHYS_MASK & (s32)PAGE_MASK; +} + +static inline unsigned long pgd_page_vaddr(pgd_t pgd) { - return __va(pgd_val(pgd) & PHYS_MASK & (s32)PAGE_MASK); + return (unsigned long) __va(pgd_page_paddr(pgd)); } /* Find an entry in the frst-level page table. */ #define pud_index(addr) (((addr) >> PUD_SHIFT) & (PTRS_PER_PUD - 1)) -static inline pud_t *pud_offset(pgd_t *pgd, unsigned long addr) -{ - return (pud_t *)pgd_page_vaddr(*pgd) + pud_index(addr); -} +#define pud_offset_phys(dir, addr) (pgd_page_paddr(*(dir)) + pud_index(addr) * sizeof(pud_t)) +#define pud_offset(dir, addr) ((pud_t *)__va(pud_offset_phys((dir), (addr)))) + +#define pud_set_fixmap(addr) ((pud_t *)set_fixmap_offset(FIX_PUD, addr)) +#define pud_set_fixmap_offset(pgd, addr) pud_set_fixmap(pud_offset_phys(pgd, addr)) +#define pud_clear_fixmap() clear_fixmap(FIX_PUD) #define pgd_page(pgd) pfn_to_page(__phys_to_pfn(pgd_val(pgd) & PHYS_MASK)) +/* use ONLY for statically allocated translation tables */ +#define pud_offset_kimg(dir,addr) ((pud_t *)__phys_to_kimg(pud_offset_phys((dir), (addr)))) + +#else + +#define pgd_page_paddr(pgd) ({ BUILD_BUG(); 0;}) + +/* Match pud_offset folding in */ +#define pud_set_fixmap(addr) NULL +#define pud_set_fixmap_offset(pgdp, addr) ((pud_t *)pgdp) +#define pud_clear_fixmap() + +#define pud_offset_kimg(dir,addr) ((pud_t *)dir) + #endif /* CONFIG_PGTABLE_LEVELS > 3 */ #define pgd_ERROR(pgd) __pgd_error(__FILE__, __LINE__, pgd_val(pgd)) @@ -516,11 +621,16 @@ /* to find an entry in a page-table-directory */ #define pgd_index(addr) (((addr) >> PGDIR_SHIFT) & (PTRS_PER_PGD - 1)) -#define pgd_offset(mm, addr) ((mm)->pgd+pgd_index(addr)) +#define pgd_offset_raw(pgd, addr) ((pgd) + pgd_index(addr)) + +#define pgd_offset(mm, addr) (pgd_offset_raw((mm)->pgd, (addr))) /* to find an entry in a kernel page-table-directory */ #define pgd_offset_k(addr) pgd_offset(&init_mm, addr) +#define pgd_set_fixmap(addr) ((pgd_t *)set_fixmap_offset(FIX_PGD, addr)) +#define pgd_clear_fixmap() clear_fixmap(FIX_PGD) + static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) { const pteval_t mask = PTE_USER | PTE_PXN | PTE_UXN | PTE_RDONLY | @@ -649,6 +759,7 @@ extern pgd_t swapper_pg_dir[PTRS_PER_PGD]; extern pgd_t idmap_pg_dir[PTRS_PER_PGD]; +extern pgd_t tramp_pg_dir[PTRS_PER_PGD]; /* * Encode and decode a swap entry: @@ -681,7 +792,8 @@ #include -#define pgtable_cache_init() do { } while (0) +void pgd_cache_init(void); +#define pgtable_cache_init pgd_cache_init /* * On AArch64, the cache coherency is handled via the set_pte_at() function. diff -ruw linux-4.4.115/arch/arm64/include/asm/pgtable-hwdef.h linux-4.4.115-fbx/arch/arm64/include/asm/pgtable-hwdef.h --- linux-4.4.115/arch/arm64/include/asm/pgtable-hwdef.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/arch/arm64/include/asm/pgtable-hwdef.h 2019-01-22 16:16:21.543228657 +0100 @@ -90,7 +90,23 @@ /* * Contiguous page definitions. */ -#define CONT_PTES (_AC(1, UL) << CONT_SHIFT) +#ifdef CONFIG_ARM64_64K_PAGES +#define CONT_PTE_SHIFT 5 +#define CONT_PMD_SHIFT 5 +#elif defined(CONFIG_ARM64_16K_PAGES) +#define CONT_PTE_SHIFT 7 +#define CONT_PMD_SHIFT 5 +#else +#define CONT_PTE_SHIFT 4 +#define CONT_PMD_SHIFT 4 +#endif + +#define CONT_PTES (1 << CONT_PTE_SHIFT) +#define CONT_PTE_SIZE (CONT_PTES * PAGE_SIZE) +#define CONT_PTE_MASK (~(CONT_PTE_SIZE - 1)) +#define CONT_PMDS (1 << CONT_PMD_SHIFT) +#define CONT_PMD_SIZE (CONT_PMDS * PMD_SIZE) +#define CONT_PMD_MASK (~(CONT_PMD_SIZE - 1)) /* the the numerical offset of the PTE within a range of CONT_PTES */ #define CONT_RANGE_OFFSET(addr) (((addr)>>PAGE_SHIFT)&(CONT_PTES-1)) @@ -208,6 +224,8 @@ #define TCR_TG1_16K (UL(1) << 30) #define TCR_TG1_4K (UL(2) << 30) #define TCR_TG1_64K (UL(3) << 30) + +#define TCR_A1 (UL(1) << 22) #define TCR_ASID16 (UL(1) << 36) #define TCR_TBI0 (UL(1) << 37) #define TCR_HA (UL(1) << 39) diff -ruw linux-4.4.115/arch/arm64/include/asm/processor.h linux-4.4.115-fbx/arch/arm64/include/asm/processor.h --- linux-4.4.115/arch/arm64/include/asm/processor.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/arch/arm64/include/asm/processor.h 2019-01-22 16:16:21.543228657 +0100 @@ -29,8 +29,10 @@ #include +#include #include #include +#include #include #include #include @@ -49,6 +51,9 @@ #define ARCH_LOW_ADDRESS_LIMIT (arm64_dma_phys_limit - 1) #endif /* __KERNEL__ */ +extern unsigned int boot_reason; +extern unsigned int cold_boot; + struct debug_info { /* Have we suspended stepping by a debugger? */ int suspended_step; @@ -177,9 +182,11 @@ } #define ARCH_HAS_SPINLOCK_PREFETCH -static inline void spin_lock_prefetch(const void *x) +static inline void spin_lock_prefetch(const void *ptr) { - prefetchw(x); + asm volatile(ARM64_LSE_ATOMIC_INSN( + "prfm pstl1strm, %a0", + "nop") : : "p" (ptr)); } #define HAVE_ARCH_PICK_MMAP_LAYOUT @@ -187,5 +194,6 @@ #endif int cpu_enable_pan(void *__unused); +int cpu_enable_uao(void *__unused); #endif /* __ASM_PROCESSOR_H */ diff -ruw linux-4.4.115/arch/arm64/include/asm/proc-fns.h linux-4.4.115-fbx/arch/arm64/include/asm/proc-fns.h --- linux-4.4.115/arch/arm64/include/asm/proc-fns.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/arch/arm64/include/asm/proc-fns.h 2019-01-22 16:16:21.543228657 +0100 @@ -28,19 +28,17 @@ struct mm_struct; struct cpu_suspend_ctx; +extern void cpu_cache_off(void); extern void cpu_do_idle(void); extern void cpu_do_switch_mm(unsigned long pgd_phys, struct mm_struct *mm); +extern void cpu_reset(unsigned long addr) __attribute__((noreturn)); +void cpu_soft_restart(phys_addr_t cpu_reset, + unsigned long addr) __attribute__((noreturn)); extern void cpu_do_suspend(struct cpu_suspend_ctx *ptr); extern u64 cpu_do_resume(phys_addr_t ptr, u64 idmap_ttbr); #include -#define cpu_switch_mm(pgd,mm) \ -do { \ - BUG_ON(pgd == swapper_pg_dir); \ - cpu_do_switch_mm(virt_to_phys(pgd),mm); \ -} while (0) - #endif /* __ASSEMBLY__ */ #endif /* __KERNEL__ */ #endif /* __ASM_PROCFNS_H */ diff -ruw linux-4.4.115/arch/arm64/include/asm/ptrace.h linux-4.4.115-fbx/arch/arm64/include/asm/ptrace.h --- linux-4.4.115/arch/arm64/include/asm/ptrace.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/arch/arm64/include/asm/ptrace.h 2019-01-22 16:16:21.543228657 +0100 @@ -121,6 +121,8 @@ u64 unused; // maintain 16 byte alignment }; +#define MAX_REG_OFFSET offsetof(struct pt_regs, pstate) + #define arch_has_single_step() (1) #ifdef CONFIG_COMPAT @@ -146,9 +148,57 @@ #define fast_interrupts_enabled(regs) \ (!((regs)->pstate & PSR_F_BIT)) -#define user_stack_pointer(regs) \ +#define GET_USP(regs) \ (!compat_user_mode(regs) ? (regs)->sp : (regs)->compat_sp) +#define SET_USP(ptregs, value) \ + (!compat_user_mode(regs) ? ((regs)->sp = value) : ((regs)->compat_sp = value)) + +extern int regs_query_register_offset(const char *name); +extern const char *regs_query_register_name(unsigned int offset); +extern unsigned long regs_get_kernel_stack_nth(struct pt_regs *regs, + unsigned int n); + +/** + * regs_get_register() - get register value from its offset + * @regs: pt_regs from which register value is gotten + * @offset: offset of the register. + * + * regs_get_register returns the value of a register whose offset from @regs. + * The @offset is the offset of the register in struct pt_regs. + * If @offset is bigger than MAX_REG_OFFSET, this returns 0. + */ +static inline u64 regs_get_register(struct pt_regs *regs, unsigned int offset) +{ + u64 val = 0; + + offset >>= 3; + switch (offset) { + case 0 ... 30: + val = regs->regs[offset]; + break; + case offsetof(struct pt_regs, sp) >> 3: + val = regs->sp; + break; + case offsetof(struct pt_regs, pc) >> 3: + val = regs->pc; + break; + case offsetof(struct pt_regs, pstate) >> 3: + val = regs->pstate; + break; + default: + val = 0; + } + + return val; +} + +/* Valid only for Kernel mode traps. */ +static inline unsigned long kernel_stack_pointer(struct pt_regs *regs) +{ + return regs->sp; +} + static inline unsigned long regs_return_value(struct pt_regs *regs) { return regs->regs[0]; @@ -158,8 +208,15 @@ struct task_struct; int valid_user_regs(struct user_pt_regs *regs, struct task_struct *task); -#define instruction_pointer(regs) ((unsigned long)(regs)->pc) +#define GET_IP(regs) ((unsigned long)(regs)->pc) +#define SET_IP(regs, value) ((regs)->pc = ((u64) (value))) + +#define GET_FP(ptregs) ((unsigned long)(ptregs)->regs[29]) +#define SET_FP(ptregs, value) ((ptregs)->regs[29] = ((u64) (value))) + +#include +#undef profile_pc extern unsigned long profile_pc(struct pt_regs *regs); #endif /* __ASSEMBLY__ */ diff -ruw linux-4.4.115/arch/arm64/include/asm/shmparam.h linux-4.4.115-fbx/arch/arm64/include/asm/shmparam.h --- linux-4.4.115/arch/arm64/include/asm/shmparam.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/arch/arm64/include/asm/shmparam.h 2019-01-22 16:16:21.543228657 +0100 @@ -21,7 +21,7 @@ * alignment value. Since we don't have aliasing D-caches, the rest of * the time we can safely use PAGE_SIZE. */ -#define COMPAT_SHMLBA 0x4000 +#define COMPAT_SHMLBA (4 * PAGE_SIZE) #include diff -ruw linux-4.4.115/arch/arm64/include/asm/signal32.h linux-4.4.115-fbx/arch/arm64/include/asm/signal32.h --- linux-4.4.115/arch/arm64/include/asm/signal32.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/arch/arm64/include/asm/signal32.h 2019-01-22 16:16:21.543228657 +0100 @@ -22,8 +22,6 @@ #define AARCH32_KERN_SIGRET_CODE_OFFSET 0x500 -extern const compat_ulong_t aarch32_sigret_code[6]; - int compat_setup_frame(int usig, struct ksignal *ksig, sigset_t *set, struct pt_regs *regs); int compat_setup_rt_frame(int usig, struct ksignal *ksig, sigset_t *set, diff -ruw linux-4.4.115/arch/arm64/include/asm/smp.h linux-4.4.115-fbx/arch/arm64/include/asm/smp.h --- linux-4.4.115/arch/arm64/include/asm/smp.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/arch/arm64/include/asm/smp.h 2019-01-22 16:16:21.543228657 +0100 @@ -16,11 +16,22 @@ #ifndef __ASM_SMP_H #define __ASM_SMP_H +#include + #include #include #include -#define raw_smp_processor_id() (current_thread_info()->cpu) +DECLARE_PER_CPU_READ_MOSTLY(int, cpu_number); + +/* + * We don't use this_cpu_read(cpu_number) as that has implicit writes to + * preempt_count, and associated (compiler) barriers, that we'd like to avoid + * the expense of. If we're preemptible, the value can be stale at use anyway. + * And we can't use this_cpu_ptr() either, as that winds up recursing back + * here under CONFIG_DEBUG_PREEMPT=y. + */ +#define raw_smp_processor_id() (*raw_cpu_ptr(&cpu_number)) struct seq_file; @@ -57,6 +68,9 @@ */ struct secondary_data { void *stack; +#ifdef CONFIG_THREAD_INFO_IN_TASK + struct task_struct *task; +#endif }; extern struct secondary_data secondary_data; extern void secondary_entry(void); @@ -64,6 +78,15 @@ extern void arch_send_call_function_single_ipi(int cpu); extern void arch_send_call_function_ipi_mask(const struct cpumask *mask); +#ifdef CONFIG_ARM64_ACPI_PARKING_PROTOCOL +extern void arch_send_wakeup_ipi_mask(const struct cpumask *mask); +#else +static inline void arch_send_wakeup_ipi_mask(const struct cpumask *mask) +{ + BUILD_BUG(); +} +#endif + extern int __cpu_disable(void); extern void __cpu_die(unsigned int cpu); diff -ruw linux-4.4.115/arch/arm64/include/asm/spinlock.h linux-4.4.115-fbx/arch/arm64/include/asm/spinlock.h --- linux-4.4.115/arch/arm64/include/asm/spinlock.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/arch/arm64/include/asm/spinlock.h 2019-10-29 09:26:22.997196856 +0100 @@ -26,9 +26,32 @@ * The memory barriers are implicit with the load-acquire and store-release * instructions. */ +static inline void arch_spin_unlock_wait(arch_spinlock_t *lock) +{ + unsigned int tmp; + arch_spinlock_t lockval; -#define arch_spin_unlock_wait(lock) \ - do { while (arch_spin_is_locked(lock)) cpu_relax(); } while (0) + asm volatile( +" sevl\n" +"1: wfe\n" +"2: ldaxr %w0, %2\n" +" eor %w1, %w0, %w0, ror #16\n" +" cbnz %w1, 1b\n" + /* Serialise against any concurrent lockers */ + ARM64_LSE_ATOMIC_INSN( + /* LL/SC */ +" stxr %w1, %w0, %2\n" +" nop\n" +" nop\n", + /* LSE atomics */ +" mov %w1, %w0\n" +" cas %w0, %w0, %2\n" +" eor %w1, %w1, %w0\n") +" cbnz %w1, 2b\n" + : "=&r" (lockval), "=&r" (tmp), "+Q" (*lock) + : + : "memory"); +} #define arch_spin_lock_flags(lock, flags) arch_spin_lock(lock) @@ -80,7 +103,6 @@ asm volatile(ARM64_LSE_ATOMIC_INSN( /* LL/SC */ - " prfm pstl1strm, %2\n" "1: ldaxr %w0, %2\n" " eor %w1, %w0, %w0, ror #16\n" " cbnz %w1, 2f\n" diff -ruw linux-4.4.115/arch/arm64/include/asm/stacktrace.h linux-4.4.115-fbx/arch/arm64/include/asm/stacktrace.h --- linux-4.4.115/arch/arm64/include/asm/stacktrace.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/arch/arm64/include/asm/stacktrace.h 2019-01-22 16:16:21.543228657 +0100 @@ -16,14 +16,19 @@ #ifndef __ASM_STACKTRACE_H #define __ASM_STACKTRACE_H +struct task_struct; + struct stackframe { unsigned long fp; unsigned long sp; unsigned long pc; +#ifdef CONFIG_FUNCTION_GRAPH_TRACER + unsigned int graph; +#endif }; -extern int unwind_frame(struct stackframe *frame); -extern void walk_stackframe(struct stackframe *frame, +extern int unwind_frame(struct task_struct *tsk, struct stackframe *frame); +extern void walk_stackframe(struct task_struct *tsk, struct stackframe *frame, int (*fn)(struct stackframe *, void *), void *data); #endif /* __ASM_STACKTRACE_H */ diff -ruw linux-4.4.115/arch/arm64/include/asm/suspend.h linux-4.4.115-fbx/arch/arm64/include/asm/suspend.h --- linux-4.4.115/arch/arm64/include/asm/suspend.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/arch/arm64/include/asm/suspend.h 2019-01-22 16:16:21.543228657 +0100 @@ -1,7 +1,8 @@ #ifndef __ASM_SUSPEND_H #define __ASM_SUSPEND_H -#define NR_CTX_REGS 11 +#define NR_CTX_REGS 12 +#define NR_CALLEE_SAVED_REGS 12 /* * struct cpu_suspend_ctx must be 16-byte aligned since it is allocated on @@ -16,11 +17,34 @@ u64 sp; } __aligned(16); -struct sleep_save_sp { - phys_addr_t *save_ptr_stash; - phys_addr_t save_ptr_stash_phys; +/* + * Memory to save the cpu state is allocated on the stack by + * __cpu_suspend_enter()'s caller, and populated by __cpu_suspend_enter(). + * This data must survive until cpu_resume() is called. + * + * This struct desribes the size and the layout of the saved cpu state. + * The layout of the callee_saved_regs is defined by the implementation + * of __cpu_suspend_enter(), and cpu_resume(). This struct must be passed + * in by the caller as __cpu_suspend_enter()'s stack-frame is gone once it + * returns, and the data would be subsequently corrupted by the call to the + * finisher. + */ +struct sleep_stack_data { + struct cpu_suspend_ctx system_regs; + unsigned long callee_saved_regs[NR_CALLEE_SAVED_REGS]; }; +extern unsigned long *sleep_save_stash; + extern int cpu_suspend(unsigned long arg, int (*fn)(unsigned long)); extern void cpu_resume(void); +int __cpu_suspend_enter(struct sleep_stack_data *state); +void __cpu_suspend_exit(void); +void _cpu_resume(void); + +int swsusp_arch_suspend(void); +int swsusp_arch_resume(void); +int arch_hibernation_header_save(void *addr, unsigned int max_size); +int arch_hibernation_header_restore(void *addr); + #endif diff -ruw linux-4.4.115/arch/arm64/include/asm/sysreg.h linux-4.4.115-fbx/arch/arm64/include/asm/sysreg.h --- linux-4.4.115/arch/arm64/include/asm/sysreg.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/arch/arm64/include/asm/sysreg.h 2019-10-29 09:26:23.001196895 +0100 @@ -20,6 +20,8 @@ #ifndef __ASM_SYSREG_H #define __ASM_SYSREG_H +#include + #include /* @@ -70,20 +72,35 @@ #define SYS_ID_AA64MMFR0_EL1 sys_reg(3, 0, 0, 7, 0) #define SYS_ID_AA64MMFR1_EL1 sys_reg(3, 0, 0, 7, 1) +#define SYS_ID_AA64MMFR2_EL1 sys_reg(3, 0, 0, 7, 2) #define SYS_CNTFRQ_EL0 sys_reg(3, 3, 14, 0, 0) #define SYS_CTR_EL0 sys_reg(3, 3, 0, 0, 1) #define SYS_DCZID_EL0 sys_reg(3, 3, 0, 0, 7) #define REG_PSTATE_PAN_IMM sys_reg(0, 0, 4, 0, 4) +#define REG_PSTATE_UAO_IMM sys_reg(0, 0, 4, 0, 3) #define SET_PSTATE_PAN(x) __inst_arm(0xd5000000 | REG_PSTATE_PAN_IMM |\ (!!x)<<8 | 0x1f) +#define SET_PSTATE_UAO(x) __inst_arm(0xd5000000 | REG_PSTATE_UAO_IMM |\ + (!!x)<<8 | 0x1f) -/* SCTLR_EL1 */ -#define SCTLR_EL1_CP15BEN (0x1 << 5) -#define SCTLR_EL1_SED (0x1 << 8) -#define SCTLR_EL1_SPAN (0x1 << 23) +/* Common SCTLR_ELx flags. */ +#define SCTLR_ELx_EE (1 << 25) +#define SCTLR_ELx_I (1 << 12) +#define SCTLR_ELx_SA (1 << 3) +#define SCTLR_ELx_C (1 << 2) +#define SCTLR_ELx_A (1 << 1) +#define SCTLR_ELx_M 1 + +#define SCTLR_ELx_FLAGS (SCTLR_ELx_M | SCTLR_ELx_A | SCTLR_ELx_C | \ + SCTLR_ELx_SA | SCTLR_ELx_I) + +/* SCTLR_EL1 specific flags. */ +#define SCTLR_EL1_SPAN (1 << 23) +#define SCTLR_EL1_SED (1 << 8) +#define SCTLR_EL1_CP15BEN (1 << 5) /* id_aa64isar0 */ @@ -95,6 +112,7 @@ #define ID_AA64ISAR0_AES_SHIFT 4 /* id_aa64pfr0 */ +#define ID_AA64PFR0_CSV2_SHIFT 56 #define ID_AA64PFR0_GIC_SHIFT 24 #define ID_AA64PFR0_ASIMD_SHIFT 20 #define ID_AA64PFR0_FP_SHIFT 16 @@ -135,6 +153,9 @@ #define ID_AA64MMFR1_VMIDBITS_SHIFT 4 #define ID_AA64MMFR1_HADBS_SHIFT 0 +/* id_aa64mmfr2 */ +#define ID_AA64MMFR2_UAO_SHIFT 4 + /* id_aa64dfr0 */ #define ID_AA64DFR0_CTX_CMPS_SHIFT 28 #define ID_AA64DFR0_WRPS_SHIFT 20 @@ -194,32 +215,34 @@ #ifdef __ASSEMBLY__ .irp num,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30 - .equ __reg_num_x\num, \num + .equ .L__reg_num_x\num, \num .endr - .equ __reg_num_xzr, 31 + .equ .L__reg_num_xzr, 31 .macro mrs_s, rt, sreg - .inst 0xd5200000|(\sreg)|(__reg_num_\rt) + .inst 0xd5200000|(\sreg)|(.L__reg_num_\rt) .endm .macro msr_s, sreg, rt - .inst 0xd5000000|(\sreg)|(__reg_num_\rt) + .inst 0xd5000000|(\sreg)|(.L__reg_num_\rt) .endm #else +#include + asm( " .irp num,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30\n" -" .equ __reg_num_x\\num, \\num\n" +" .equ .L__reg_num_x\\num, \\num\n" " .endr\n" -" .equ __reg_num_xzr, 31\n" +" .equ .L__reg_num_xzr, 31\n" "\n" " .macro mrs_s, rt, sreg\n" -" .inst 0xd5200000|(\\sreg)|(__reg_num_\\rt)\n" +" .inst 0xd5200000|(\\sreg)|(.L__reg_num_\\rt)\n" " .endm\n" "\n" " .macro msr_s, sreg, rt\n" -" .inst 0xd5000000|(\\sreg)|(__reg_num_\\rt)\n" +" .inst 0xd5000000|(\\sreg)|(.L__reg_num_\\rt)\n" " .endm\n" ); @@ -232,6 +255,23 @@ val |= set; asm volatile("msr sctlr_el1, %0" : : "r" (val)); } + +/* + * Unlike read_cpuid, calls to read_sysreg are never expected to be + * optimized away or replaced with synthetic values. + */ +#define read_sysreg(r) ({ \ + u64 __val; \ + asm volatile("mrs %0, " __stringify(r) : "=r" (__val)); \ + __val; \ +}) + +#define write_sysreg(v, r) do { \ + u64 __val = (u64)v; \ + asm volatile("msr " __stringify(r) ", %0" \ + : : "r" (__val)); \ +} while (0) + #endif #endif /* __ASM_SYSREG_H */ diff -ruw linux-4.4.115/arch/arm64/include/asm/system_misc.h linux-4.4.115-fbx/arch/arm64/include/asm/system_misc.h --- linux-4.4.115/arch/arm64/include/asm/system_misc.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/arch/arm64/include/asm/system_misc.h 2019-01-22 16:16:21.543228657 +0100 @@ -44,6 +44,7 @@ extern void __show_regs(struct pt_regs *); extern void (*arm_pm_restart)(enum reboot_mode reboot_mode, const char *cmd); +extern char* (*arch_read_hardware_id)(void); #define show_unhandled_signals_ratelimited() \ ({ \ diff -ruw linux-4.4.115/arch/arm64/include/asm/thread_info.h linux-4.4.115-fbx/arch/arm64/include/asm/thread_info.h --- linux-4.4.115/arch/arm64/include/asm/thread_info.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/arch/arm64/include/asm/thread_info.h 2019-10-29 09:26:23.001196895 +0100 @@ -36,22 +36,36 @@ struct task_struct; +#include #include typedef unsigned long mm_segment_t; /* * low level task data that entry.S needs immediate access to. - * __switch_to() assumes cpu_context follows immediately after cpu_domain. */ struct thread_info { unsigned long flags; /* low level flags */ mm_segment_t addr_limit; /* address limit */ +#ifndef CONFIG_THREAD_INFO_IN_TASK struct task_struct *task; /* main task structure */ +#endif +#ifdef CONFIG_ARM64_SW_TTBR0_PAN + u64 ttbr0; /* saved TTBR0_EL1 */ +#endif int preempt_count; /* 0 => preemptable, <0 => bug */ +#ifndef CONFIG_THREAD_INFO_IN_TASK int cpu; /* cpu */ +#endif }; +#ifdef CONFIG_THREAD_INFO_IN_TASK +#define INIT_THREAD_INFO(tsk) \ +{ \ + .preempt_count = INIT_PREEMPT_COUNT, \ + .addr_limit = KERNEL_DS, \ +} +#else #define INIT_THREAD_INFO(tsk) \ { \ .task = &tsk, \ @@ -60,25 +74,28 @@ .addr_limit = KERNEL_DS, \ } -#define init_thread_info (init_thread_union.thread_info) -#define init_stack (init_thread_union.stack) - -/* - * how to get the current stack pointer from C - */ -register unsigned long current_stack_pointer asm ("sp"); - /* * how to get the thread information struct from C */ static inline struct thread_info *current_thread_info(void) __attribute_const__; +/* + * struct thread_info can be accessed directly via sp_el0. + */ static inline struct thread_info *current_thread_info(void) { - return (struct thread_info *) - (current_stack_pointer & ~(THREAD_SIZE - 1)); + unsigned long sp_el0; + + asm ("mrs %0, sp_el0" : "=r" (sp_el0)); + + return (struct thread_info *)sp_el0; } +#define init_thread_info (init_thread_union.thread_info) +#endif + +#define init_stack (init_thread_union.stack) + #define thread_saved_pc(tsk) \ ((unsigned long)(tsk->thread.cpu_context.pc)) #define thread_saved_sp(tsk) \ @@ -113,6 +130,7 @@ #define TIF_RESTORE_SIGMASK 20 #define TIF_SINGLESTEP 21 #define TIF_32BIT 22 /* 32bit process */ +#define TIF_MM_RELEASED 24 #define _TIF_SIGPENDING (1 << TIF_SIGPENDING) #define _TIF_NEED_RESCHED (1 << TIF_NEED_RESCHED) diff -ruw linux-4.4.115/arch/arm64/include/asm/tlbflush.h linux-4.4.115-fbx/arch/arm64/include/asm/tlbflush.h --- linux-4.4.115/arch/arm64/include/asm/tlbflush.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/arch/arm64/include/asm/tlbflush.h 2019-01-22 16:16:21.543228657 +0100 @@ -23,6 +23,30 @@ #include #include +#include + +/* + * Raw TLBI operations. + * + * Where necessary, use the __tlbi() macro to avoid asm() + * boilerplate. Drivers and most kernel code should use the TLB + * management routines in preference to the macro below. + * + * The macro can be used as __tlbi(op) or __tlbi(op, arg), depending + * on whether a particular TLBI operation takes an argument or + * not. The macros handles invoking the asm with or without the + * register argument as appropriate. + */ +#define __TLBI_0(op, arg) asm ("tlbi " #op) +#define __TLBI_1(op, arg) asm ("tlbi " #op ", %0" : : "r" (arg)) +#define __TLBI_N(op, arg, n, ...) __TLBI_##n(op, arg) + +#define __tlbi(op, ...) __TLBI_N(op, ##__VA_ARGS__, 1, 0) + +#define __tlbi_user(op, arg) do { \ + if (arm64_kernel_unmapped_at_el0()) \ + __tlbi(op, (arg) | USER_ASID_FLAG); \ +} while (0) /* * TLB Management @@ -66,7 +90,7 @@ static inline void local_flush_tlb_all(void) { dsb(nshst); - asm("tlbi vmalle1"); + __tlbi(vmalle1); dsb(nsh); isb(); } @@ -74,7 +98,7 @@ static inline void flush_tlb_all(void) { dsb(ishst); - asm("tlbi vmalle1is"); + __tlbi(vmalle1is); dsb(ish); isb(); } @@ -84,7 +108,8 @@ unsigned long asid = ASID(mm) << 48; dsb(ishst); - asm("tlbi aside1is, %0" : : "r" (asid)); + __tlbi(aside1is, asid); + __tlbi_user(aside1is, asid); dsb(ish); } @@ -94,7 +119,8 @@ unsigned long addr = uaddr >> 12 | (ASID(vma->vm_mm) << 48); dsb(ishst); - asm("tlbi vale1is, %0" : : "r" (addr)); + __tlbi(vale1is, addr); + __tlbi_user(vale1is, addr); dsb(ish); } @@ -121,10 +147,13 @@ dsb(ishst); for (addr = start; addr < end; addr += 1 << (PAGE_SHIFT - 12)) { - if (last_level) - asm("tlbi vale1is, %0" : : "r"(addr)); - else - asm("tlbi vae1is, %0" : : "r"(addr)); + if (last_level) { + __tlbi(vale1is, addr); + __tlbi_user(vale1is, addr); + } else { + __tlbi(vae1is, addr); + __tlbi_user(vae1is, addr); + } } dsb(ish); } @@ -149,7 +178,7 @@ dsb(ishst); for (addr = start; addr < end; addr += 1 << (PAGE_SHIFT - 12)) - asm("tlbi vaae1is, %0" : : "r"(addr)); + __tlbi(vaae1is, addr); dsb(ish); isb(); } @@ -163,7 +192,8 @@ { unsigned long addr = uaddr >> 12 | (ASID(mm) << 48); - asm("tlbi vae1is, %0" : : "r" (addr)); + __tlbi(vae1is, addr); + __tlbi_user(vae1is, addr); dsb(ish); } diff -ruw linux-4.4.115/arch/arm64/include/asm/topology.h linux-4.4.115-fbx/arch/arm64/include/asm/topology.h --- linux-4.4.115/arch/arm64/include/asm/topology.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/arch/arm64/include/asm/topology.h 2019-01-22 16:16:21.543228657 +0100 @@ -21,6 +21,16 @@ void init_cpu_topology(void); void store_cpu_topology(unsigned int cpuid); const struct cpumask *cpu_coregroup_mask(int cpu); +unsigned long arch_get_cpu_efficiency(int cpu); + +struct sched_domain; +#ifdef CONFIG_CPU_FREQ +#define arch_scale_freq_capacity cpufreq_scale_freq_capacity +extern unsigned long cpufreq_scale_freq_capacity(struct sched_domain *sd, int cpu); +extern unsigned long cpufreq_scale_max_freq_capacity(int cpu); +#endif +#define arch_scale_cpu_capacity scale_cpu_capacity +extern unsigned long scale_cpu_capacity(struct sched_domain *sd, int cpu); #include diff -ruw linux-4.4.115/arch/arm64/include/asm/traps.h linux-4.4.115-fbx/arch/arm64/include/asm/traps.h --- linux-4.4.115/arch/arm64/include/asm/traps.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/arch/arm64/include/asm/traps.h 2019-10-29 09:26:23.001196895 +0100 @@ -34,7 +34,6 @@ void register_undef_hook(struct undef_hook *hook); void unregister_undef_hook(struct undef_hook *hook); -#ifdef CONFIG_FUNCTION_GRAPH_TRACER static inline int __in_irqentry_text(unsigned long ptr) { extern char __irqentry_text_start[]; @@ -43,12 +42,6 @@ return ptr >= (unsigned long)&__irqentry_text_start && ptr < (unsigned long)&__irqentry_text_end; } -#else -static inline int __in_irqentry_text(unsigned long ptr) -{ - return 0; -} -#endif static inline int in_exception_text(unsigned long ptr) { @@ -62,4 +55,5 @@ return in ? : __in_irqentry_text(ptr); } +static inline void get_pct_hook_init(void) {} #endif diff -ruw linux-4.4.115/arch/arm64/include/asm/uaccess.h linux-4.4.115-fbx/arch/arm64/include/asm/uaccess.h --- linux-4.4.115/arch/arm64/include/asm/uaccess.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/arch/arm64/include/asm/uaccess.h 2019-10-29 09:26:23.001196895 +0100 @@ -18,6 +18,13 @@ #ifndef __ASM_UACCESS_H #define __ASM_UACCESS_H +#include +#include +#include +#include + +#ifndef __ASSEMBLY__ + /* * User space memory access functions */ @@ -25,10 +32,8 @@ #include #include -#include #include #include -#include #include #include #include @@ -37,11 +42,11 @@ #define VERIFY_WRITE 1 /* - * The exception table consists of pairs of addresses: the first is the - * address of an instruction that is allowed to fault, and the second is - * the address at which the program should continue. No registers are - * modified, so it is entirely up to the continuation code to figure out - * what to do. + * The exception table consists of pairs of relative offsets: the first + * is the relative offset to an instruction that is allowed to fault, + * and the second is the relative offset at which the program should + * continue. No registers are modified, so it is entirely up to the + * continuation code to figure out what to do. * * All the routines below use bits of fixup code that are out of line * with the main instruction path. This means when everything is well, @@ -51,9 +56,11 @@ struct exception_table_entry { - unsigned long insn, fixup; + int insn, fixup; }; +#define ARCH_HAS_RELATIVE_EXTABLE + extern int fixup_exception(struct pt_regs *regs); #define KERNEL_DS (-1UL) @@ -65,6 +72,16 @@ static inline void set_fs(mm_segment_t fs) { current_thread_info()->addr_limit = fs; + + /* + * Enable/disable UAO so that copy_to_user() etc can access + * kernel memory with the unprivileged instructions. + */ + if (IS_ENABLED(CONFIG_ARM64_UAO) && fs == KERNEL_DS) + asm(ALTERNATIVE("nop", SET_PSTATE_UAO(1), ARM64_HAS_UAO)); + else + asm(ALTERNATIVE("nop", SET_PSTATE_UAO(0), ARM64_HAS_UAO, + CONFIG_ARM64_UAO)); } #define segment_eq(a, b) ((a) == (b)) @@ -114,6 +131,121 @@ #define access_ok(type, addr, size) __range_ok(addr, size) #define user_addr_max get_fs +#define _ASM_EXTABLE(from, to) \ + " .pushsection __ex_table, \"a\"\n" \ + " .align 3\n" \ + " .long (" #from " - .), (" #to " - .)\n" \ + " .popsection\n" + +/* + * User access enabling/disabling. + */ +#ifdef CONFIG_ARM64_SW_TTBR0_PAN +static inline void __uaccess_ttbr0_disable(void) +{ + unsigned long flags, ttbr; + + local_irq_save(flags); + ttbr = read_sysreg(ttbr1_el1); + ttbr &= ~TTBR_ASID_MASK; + /* reserved_ttbr0 placed at the end of swapper_pg_dir */ + write_sysreg(ttbr + SWAPPER_DIR_SIZE, ttbr0_el1); + isb(); + /* Set reserved ASID */ + write_sysreg(ttbr, ttbr1_el1); + isb(); + local_irq_restore(flags); +} + +static inline void __uaccess_ttbr0_enable(void) +{ + unsigned long flags, ttbr0, ttbr1; + + /* + * Disable interrupts to avoid preemption between reading the 'ttbr0' + * variable and the MSR. A context switch could trigger an ASID + * roll-over and an update of 'ttbr0'. + */ + local_irq_save(flags); + ttbr0 = READ_ONCE(current_thread_info()->ttbr0); + + /* Restore active ASID */ + ttbr1 = read_sysreg(ttbr1_el1); + ttbr1 &= ~TTBR_ASID_MASK; /* safety measure */ + ttbr1 |= ttbr0 & TTBR_ASID_MASK; + write_sysreg(ttbr1, ttbr1_el1); + isb(); + + /* Restore user page table */ + write_sysreg(ttbr0, ttbr0_el1); + isb(); + local_irq_restore(flags); +} + +static inline bool uaccess_ttbr0_disable(void) +{ + if (!system_uses_ttbr0_pan()) + return false; + __uaccess_ttbr0_disable(); + return true; +} + +static inline bool uaccess_ttbr0_enable(void) +{ + if (!system_uses_ttbr0_pan()) + return false; + __uaccess_ttbr0_enable(); + return true; +} +#else +static inline bool uaccess_ttbr0_disable(void) +{ + return false; +} + +static inline bool uaccess_ttbr0_enable(void) +{ + return false; +} +#endif + +#define __uaccess_disable(alt) \ +do { \ + if (!uaccess_ttbr0_disable()) \ + asm(ALTERNATIVE("nop", SET_PSTATE_PAN(1), alt, \ + CONFIG_ARM64_PAN)); \ +} while (0) + +#define __uaccess_enable(alt) \ +do { \ + if (!uaccess_ttbr0_enable()) \ + asm(ALTERNATIVE("nop", SET_PSTATE_PAN(0), alt, \ + CONFIG_ARM64_PAN)); \ +} while (0) + +static inline void uaccess_disable(void) +{ + __uaccess_disable(ARM64_HAS_PAN); +} + +static inline void uaccess_enable(void) +{ + __uaccess_enable(ARM64_HAS_PAN); +} + +/* + * These functions are no-ops when UAO is present. + */ +static inline void uaccess_disable_not_uao(void) +{ + __uaccess_disable(ARM64_ALT_PAN_NOT_UAO); +} + +static inline void uaccess_enable_not_uao(void) +{ + __uaccess_enable(ARM64_ALT_PAN_NOT_UAO); +} + /* * The "__xxx" versions of the user access functions do not verify the address * space - it must have been done previously with a separate "access_ok()" @@ -122,9 +254,10 @@ * The "__xxx_error" versions set the third argument to -EFAULT if an error * occurs, and leave it unchanged on success. */ -#define __get_user_asm(instr, reg, x, addr, err) \ +#define __get_user_asm(instr, alt_instr, reg, x, addr, err, feature) \ asm volatile( \ - "1: " instr " " reg "1, [%2]\n" \ + "1:"ALTERNATIVE(instr " " reg "1, [%2]\n", \ + alt_instr " " reg "1, [%2]\n", feature) \ "2:\n" \ " .section .fixup, \"ax\"\n" \ " .align 2\n" \ @@ -132,10 +265,7 @@ " mov %1, #0\n" \ " b 2b\n" \ " .previous\n" \ - " .section __ex_table,\"a\"\n" \ - " .align 3\n" \ - " .quad 1b, 3b\n" \ - " .previous" \ + _ASM_EXTABLE(1b, 3b) \ : "+r" (err), "=&r" (x) \ : "r" (addr), "i" (-EFAULT)) @@ -143,27 +273,29 @@ do { \ unsigned long __gu_val; \ __chk_user_ptr(ptr); \ - asm(ALTERNATIVE("nop", SET_PSTATE_PAN(0), ARM64_HAS_PAN, \ - CONFIG_ARM64_PAN)); \ + uaccess_enable_not_uao(); \ switch (sizeof(*(ptr))) { \ case 1: \ - __get_user_asm("ldrb", "%w", __gu_val, (ptr), (err)); \ + __get_user_asm("ldrb", "ldtrb", "%w", __gu_val, (ptr), \ + (err), ARM64_HAS_UAO); \ break; \ case 2: \ - __get_user_asm("ldrh", "%w", __gu_val, (ptr), (err)); \ + __get_user_asm("ldrh", "ldtrh", "%w", __gu_val, (ptr), \ + (err), ARM64_HAS_UAO); \ break; \ case 4: \ - __get_user_asm("ldr", "%w", __gu_val, (ptr), (err)); \ + __get_user_asm("ldr", "ldtr", "%w", __gu_val, (ptr), \ + (err), ARM64_HAS_UAO); \ break; \ case 8: \ - __get_user_asm("ldr", "%", __gu_val, (ptr), (err)); \ + __get_user_asm("ldr", "ldtr", "%", __gu_val, (ptr), \ + (err), ARM64_HAS_UAO); \ break; \ default: \ BUILD_BUG(); \ } \ + uaccess_disable_not_uao(); \ (x) = (__force __typeof__(*(ptr)))__gu_val; \ - asm(ALTERNATIVE("nop", SET_PSTATE_PAN(1), ARM64_HAS_PAN, \ - CONFIG_ARM64_PAN)); \ } while (0) #define __get_user(x, ptr) \ @@ -190,19 +322,17 @@ ((x) = 0, -EFAULT); \ }) -#define __put_user_asm(instr, reg, x, addr, err) \ +#define __put_user_asm(instr, alt_instr, reg, x, addr, err, feature) \ asm volatile( \ - "1: " instr " " reg "1, [%2]\n" \ + "1:"ALTERNATIVE(instr " " reg "1, [%2]\n", \ + alt_instr " " reg "1, [%2]\n", feature) \ "2:\n" \ " .section .fixup,\"ax\"\n" \ " .align 2\n" \ "3: mov %w0, %3\n" \ " b 2b\n" \ " .previous\n" \ - " .section __ex_table,\"a\"\n" \ - " .align 3\n" \ - " .quad 1b, 3b\n" \ - " .previous" \ + _ASM_EXTABLE(1b, 3b) \ : "+r" (err) \ : "r" (x), "r" (addr), "i" (-EFAULT)) @@ -210,26 +340,28 @@ do { \ __typeof__(*(ptr)) __pu_val = (x); \ __chk_user_ptr(ptr); \ - asm(ALTERNATIVE("nop", SET_PSTATE_PAN(0), ARM64_HAS_PAN, \ - CONFIG_ARM64_PAN)); \ + uaccess_enable_not_uao(); \ switch (sizeof(*(ptr))) { \ case 1: \ - __put_user_asm("strb", "%w", __pu_val, (ptr), (err)); \ + __put_user_asm("strb", "sttrb", "%w", __pu_val, (ptr), \ + (err), ARM64_HAS_UAO); \ break; \ case 2: \ - __put_user_asm("strh", "%w", __pu_val, (ptr), (err)); \ + __put_user_asm("strh", "sttrh", "%w", __pu_val, (ptr), \ + (err), ARM64_HAS_UAO); \ break; \ case 4: \ - __put_user_asm("str", "%w", __pu_val, (ptr), (err)); \ + __put_user_asm("str", "sttr", "%w", __pu_val, (ptr), \ + (err), ARM64_HAS_UAO); \ break; \ case 8: \ - __put_user_asm("str", "%", __pu_val, (ptr), (err)); \ + __put_user_asm("str", "sttr", "%", __pu_val, (ptr), \ + (err), ARM64_HAS_UAO); \ break; \ default: \ BUILD_BUG(); \ } \ - asm(ALTERNATIVE("nop", SET_PSTATE_PAN(1), ARM64_HAS_PAN, \ - CONFIG_ARM64_PAN)); \ + uaccess_disable_not_uao(); \ } while (0) #define __put_user(x, ptr) \ @@ -256,24 +388,39 @@ -EFAULT; \ }) -extern unsigned long __must_check __copy_from_user(void *to, const void __user *from, unsigned long n); -extern unsigned long __must_check __copy_to_user(void __user *to, const void *from, unsigned long n); +extern unsigned long __must_check __arch_copy_from_user(void *to, const void __user *from, unsigned long n); +extern unsigned long __must_check __arch_copy_to_user(void __user *to, const void *from, unsigned long n); extern unsigned long __must_check __copy_in_user(void __user *to, const void __user *from, unsigned long n); extern unsigned long __must_check __clear_user(void __user *addr, unsigned long n); +static inline unsigned long __must_check __copy_from_user(void *to, const void __user *from, unsigned long n) +{ + check_object_size(to, n, false); + return __arch_copy_from_user(to, from, n); +} + +static inline unsigned long __must_check __copy_to_user(void __user *to, const void *from, unsigned long n) +{ + check_object_size(from, n, true); + return __arch_copy_to_user(to, from, n); +} + static inline unsigned long __must_check copy_from_user(void *to, const void __user *from, unsigned long n) { - if (access_ok(VERIFY_READ, from, n)) - n = __copy_from_user(to, from, n); - else /* security hole - plug it */ + if (access_ok(VERIFY_READ, from, n)) { + check_object_size(to, n, false); + n = __arch_copy_from_user(to, from, n); + } else /* security hole - plug it */ memset(to, 0, n); return n; } static inline unsigned long __must_check copy_to_user(void __user *to, const void *from, unsigned long n) { - if (access_ok(VERIFY_WRITE, to, n)) - n = __copy_to_user(to, from, n); + if (access_ok(VERIFY_WRITE, to, n)) { + check_object_size(from, n, true); + n = __arch_copy_to_user(to, from, n); + } return n; } @@ -299,4 +446,77 @@ extern __must_check long strlen_user(const char __user *str); extern __must_check long strnlen_user(const char __user *str, long n); +#else /* __ASSEMBLY__ */ + +#include + +/* + * User access enabling/disabling macros. + */ +#ifdef CONFIG_ARM64_SW_TTBR0_PAN + .macro __uaccess_ttbr0_disable, tmp1 + mrs \tmp1, ttbr1_el1 // swapper_pg_dir + bic \tmp1, \tmp1, #TTBR_ASID_MASK + add \tmp1, \tmp1, #SWAPPER_DIR_SIZE // reserved_ttbr0 at the end of swapper_pg_dir + msr ttbr0_el1, \tmp1 // set reserved TTBR0_EL1 + isb + sub \tmp1, \tmp1, #SWAPPER_DIR_SIZE + msr ttbr1_el1, \tmp1 // set reserved ASID + isb + .endm + + .macro __uaccess_ttbr0_enable, tmp1, tmp2 + get_thread_info \tmp1 + ldr \tmp1, [\tmp1, #TSK_TI_TTBR0] // load saved TTBR0_EL1 + mrs \tmp2, ttbr1_el1 + extr \tmp2, \tmp2, \tmp1, #48 + ror \tmp2, \tmp2, #16 + msr ttbr1_el1, \tmp2 // set the active ASID + isb + msr ttbr0_el1, \tmp1 // set the non-PAN TTBR0_EL1 + isb + .endm + + .macro uaccess_ttbr0_disable, tmp1, tmp2 +alternative_if_not ARM64_HAS_PAN + save_and_disable_irq \tmp2 // avoid preemption + __uaccess_ttbr0_disable \tmp1 + restore_irq \tmp2 +alternative_else_nop_endif + .endm + + .macro uaccess_ttbr0_enable, tmp1, tmp2, tmp3 +alternative_if_not ARM64_HAS_PAN + save_and_disable_irq \tmp3 // avoid preemption + __uaccess_ttbr0_enable \tmp1, \tmp2 + restore_irq \tmp3 +alternative_else_nop_endif + .endm +#else + .macro uaccess_ttbr0_disable, tmp1, tmp2 + .endm + + .macro uaccess_ttbr0_enable, tmp1, tmp2, tmp3 + .endm +#endif + +/* + * These macros are no-ops when UAO is present. + */ + .macro uaccess_disable_not_uao, tmp1, tmp2 + uaccess_ttbr0_disable \tmp1, \tmp2 +alternative_if ARM64_ALT_PAN_NOT_UAO + SET_PSTATE_PAN(1) +alternative_else_nop_endif + .endm + + .macro uaccess_enable_not_uao, tmp1, tmp2, tmp3 + uaccess_ttbr0_enable \tmp1, \tmp2, \tmp3 +alternative_if ARM64_ALT_PAN_NOT_UAO + SET_PSTATE_PAN(0) +alternative_else_nop_endif + .endm + +#endif /* __ASSEMBLY__ */ + #endif /* __ASM_UACCESS_H */ diff -ruw linux-4.4.115/arch/arm64/include/asm/vdso_datapage.h linux-4.4.115-fbx/arch/arm64/include/asm/vdso_datapage.h --- linux-4.4.115/arch/arm64/include/asm/vdso_datapage.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/arch/arm64/include/asm/vdso_datapage.h 2019-01-22 16:16:21.543228657 +0100 @@ -22,6 +22,8 @@ struct vdso_data { __u64 cs_cycle_last; /* Timebase at clocksource init */ + __u64 raw_time_sec; /* Raw time */ + __u64 raw_time_nsec; __u64 xtime_clock_sec; /* Kernel time */ __u64 xtime_clock_nsec; __u64 xtime_coarse_sec; /* Coarse time */ @@ -29,8 +31,10 @@ __u64 wtm_clock_sec; /* Wall to monotonic time */ __u64 wtm_clock_nsec; __u32 tb_seq_count; /* Timebase sequence counter */ - __u32 cs_mult; /* Clocksource multiplier */ - __u32 cs_shift; /* Clocksource shift */ + /* cs_* members must be adjacent and in this order (ldp accesses) */ + __u32 cs_mono_mult; /* NTP-adjusted clocksource multiplier */ + __u32 cs_shift; /* Clocksource shift (mono = raw) */ + __u32 cs_raw_mult; /* Raw clocksource multiplier */ __u32 tz_minuteswest; /* Whacky timezone stuff */ __u32 tz_dsttime; __u32 use_syscall; diff -ruw linux-4.4.115/arch/arm64/include/asm/virt.h linux-4.4.115-fbx/arch/arm64/include/asm/virt.h --- linux-4.4.115/arch/arm64/include/asm/virt.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/arch/arm64/include/asm/virt.h 2019-10-29 09:26:23.001196895 +0100 @@ -18,11 +18,29 @@ #ifndef __ASM__VIRT_H #define __ASM__VIRT_H +/* + * The arm64 hcall implementation uses x0 to specify the hcall type. A value + * less than 0xfff indicates a special hcall, such as get/set vector. + * Any other value is used as a pointer to the function to call. + */ + +/* HVC_GET_VECTORS - Return the value of the vbar_el2 register. */ +#define HVC_GET_VECTORS 0 + +/* + * HVC_SET_VECTORS - Set the value of the vbar_el2 register. + * + * @x1: Physical address of the new vector table. + */ +#define HVC_SET_VECTORS 1 + #define BOOT_CPU_MODE_EL1 (0xe11) #define BOOT_CPU_MODE_EL2 (0xe12) #ifndef __ASSEMBLY__ +#include + /* * __boot_cpu_mode records what mode CPUs were booted in. * A correctly-implemented bootloader must start all CPUs in the same mode: @@ -50,6 +68,14 @@ return __boot_cpu_mode[0] != __boot_cpu_mode[1]; } +static inline bool is_kernel_in_hyp_mode(void) +{ + u64 el; + + asm("mrs %0, CurrentEL" : "=r" (el)); + return el == CurrentEL_EL2; +} + /* The section containing the hypervisor text */ extern char __hyp_text_start[]; extern char __hyp_text_end[]; diff -ruw linux-4.4.115/arch/arm64/include/asm/word-at-a-time.h linux-4.4.115-fbx/arch/arm64/include/asm/word-at-a-time.h --- linux-4.4.115/arch/arm64/include/asm/word-at-a-time.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/arch/arm64/include/asm/word-at-a-time.h 2019-01-22 16:16:21.543228657 +0100 @@ -16,6 +16,8 @@ #ifndef __ASM_WORD_AT_A_TIME_H #define __ASM_WORD_AT_A_TIME_H +#include + #ifndef __AARCH64EB__ #include @@ -81,10 +83,7 @@ #endif " b 2b\n" " .popsection\n" - " .pushsection __ex_table,\"a\"\n" - " .align 3\n" - " .quad 1b, 3b\n" - " .popsection" + _ASM_EXTABLE(1b, 3b) : "=&r" (ret), "=&r" (offset) : "r" (addr), "Q" (*(unsigned long *)addr)); diff -ruw linux-4.4.115/arch/arm64/include/uapi/asm/ptrace.h linux-4.4.115-fbx/arch/arm64/include/uapi/asm/ptrace.h --- linux-4.4.115/arch/arm64/include/uapi/asm/ptrace.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/arch/arm64/include/uapi/asm/ptrace.h 2019-01-22 16:16:21.547228694 +0100 @@ -45,6 +45,7 @@ #define PSR_A_BIT 0x00000100 #define PSR_D_BIT 0x00000200 #define PSR_PAN_BIT 0x00400000 +#define PSR_UAO_BIT 0x00800000 #define PSR_Q_BIT 0x08000000 #define PSR_V_BIT 0x10000000 #define PSR_C_BIT 0x20000000 diff -ruw linux-4.4.115/arch/arm64/Kconfig linux-4.4.115-fbx/arch/arm64/Kconfig --- linux-4.4.115/arch/arm64/Kconfig 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/arch/arm64/Kconfig 2019-10-29 09:32:37.124855595 +0100 @@ -13,6 +13,8 @@ select ARCH_WANT_OPTIONAL_GPIOLIB select ARCH_WANT_COMPAT_IPC_PARSE_VERSION select ARCH_WANT_FRAME_POINTERS + select ARCH_HAVE_CUSTOM_GPIO_H + select ARCH_HAS_UBSAN_SANITIZE_ALL select ARM_AMBA select ARM_ARCH_TIMER select ARM_GIC @@ -23,12 +25,13 @@ select ARM_PSCI_FW select BUILDTIME_EXTABLE_SORT select CLONE_BACKWARDS - select COMMON_CLK + select COMMON_CLK if !ARCH_QCOM select CPU_PM if (SUSPEND || CPU_IDLE) select DCACHE_WORD_ACCESS select EDAC_SUPPORT select FRAME_POINTER select GENERIC_ALLOCATOR + select EDAC_SUPPORT select GENERIC_CLOCKEVENTS select GENERIC_CLOCKEVENTS_BROADCAST select GENERIC_CPU_AUTOPROBE @@ -48,9 +51,13 @@ select HAVE_ALIGNED_STRUCT_PAGE if SLUB select HAVE_ARCH_AUDITSYSCALL select HAVE_ARCH_BITREVERSE + select HAVE_ARCH_HARDENED_USERCOPY + select HAVE_ARCH_HUGE_VMAP select HAVE_ARCH_JUMP_LABEL select HAVE_ARCH_KASAN if SPARSEMEM_VMEMMAP && !(ARM64_16K_PAGES && ARM64_VA_BITS_48) select HAVE_ARCH_KGDB + select HAVE_ARCH_MMAP_RND_BITS + select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT select HAVE_ARCH_SECCOMP_FILTER select HAVE_ARCH_TRACEHOOK select HAVE_BPF_JIT @@ -70,15 +77,18 @@ select HAVE_FUNCTION_TRACER select HAVE_FUNCTION_GRAPH_TRACER select HAVE_GENERIC_DMA_COHERENT - select HAVE_HW_BREAKPOINT if PERF_EVENTS + select HAVE_IRQ_TIME_ACCOUNTING select HAVE_MEMBLOCK select HAVE_PATA_PLATFORM select HAVE_PERF_EVENTS select HAVE_PERF_REGS select HAVE_PERF_USER_STACK_DUMP + select HAVE_REGS_AND_STACK_ACCESS_API select HAVE_RCU_TABLE_FREE select HAVE_SYSCALL_TRACEPOINTS - select IOMMU_DMA if IOMMU_SUPPORT + select IOMMU_DMA if (IOMMU_SUPPORT && !ARCH_QCOM) + select HAVE_KPROBES + select HAVE_KRETPROBES if HAVE_KPROBES select IRQ_DOMAIN select IRQ_FORCED_THREADING select MODULES_USE_ELF_RELA @@ -93,6 +103,8 @@ select SPARSE_IRQ select SYSCTL_EXCEPTION_TRACE select HAVE_CONTEXT_TRACKING + select HAVE_ARM_SMCCC + select THREAD_INFO_IN_TASK help ARM 64-bit (AArch64) Linux support. @@ -105,9 +117,40 @@ config MMU def_bool y +config ARCH_MMAP_RND_BITS_MIN + default 14 if ARM64_64K_PAGES + default 16 if ARM64_16K_PAGES + default 18 + +# max bits determined by the following formula: +# VA_BITS - PAGE_SHIFT - 3 +config ARCH_MMAP_RND_BITS_MAX + default 19 if ARM64_VA_BITS=36 + default 24 if ARM64_VA_BITS=39 + default 27 if ARM64_VA_BITS=42 + default 30 if ARM64_VA_BITS=47 + default 29 if ARM64_VA_BITS=48 && ARM64_64K_PAGES + default 31 if ARM64_VA_BITS=48 && ARM64_16K_PAGES + default 33 if ARM64_VA_BITS=48 + default 14 if ARM64_64K_PAGES + default 16 if ARM64_16K_PAGES + default 18 + +config ARCH_MMAP_RND_COMPAT_BITS_MIN + default 7 if ARM64_64K_PAGES + default 9 if ARM64_16K_PAGES + default 11 + +config ARCH_MMAP_RND_COMPAT_BITS_MAX + default 16 + config NO_IOPORT_MAP def_bool y if !PCI +config ILLEGAL_POINTER_VALUE + hex + default 0xdead000000000000 + config STACKTRACE_SUPPORT def_bool y @@ -159,6 +202,32 @@ config SMP def_bool y +config ARM64_DMA_USE_IOMMU + bool + select ARM_HAS_SG_CHAIN + select NEED_SG_DMA_LENGTH + +if ARM64_DMA_USE_IOMMU + +config ARM64_DMA_IOMMU_ALIGNMENT + int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers" + range 4 9 + default 9 + help + DMA mapping framework by default aligns all buffers to the smallest + PAGE_SIZE order which is greater than or equal to the requested buffer + size. This works well for buffers up to a few hundreds kilobytes, but + for larger buffers it just a waste of address space. Drivers which has + relatively small addressing window (like 64Mib) might run out of + virtual space with just a few allocations. + + With this parameter you can specify the maximum PAGE_SIZE order for + DMA IOMMU buffers. Larger buffers will be aligned only to this + specified order. The order is expressed as a power of two multiplied + by the PAGE_SIZE. + +endif + config SWIOTLB def_bool y @@ -180,6 +249,15 @@ default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47 default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48 +config MSM_GVM_QUIN + bool "Enable virtualization Support for MSM kernel required for QUIN platform" + help + This enables support for MSM Kernel based virtual + machine for QUIN platform. + This helps to enable virtual driver support. + This should work on 64bit machine. + If you don't know what to do here, say N. + source "init/Kconfig" source "kernel/Kconfig.freezer" @@ -363,6 +441,7 @@ bool "Cortex-A53: 843419: A load or store might access an incorrect address" depends on MODULES default y + select ARM64_MODULE_CMODEL_LARGE help This option builds kernel modules using the large memory model in order to avoid the use of the ADRP instruction, which can cause @@ -443,6 +522,25 @@ requires applications compiled with 16K (or a multiple of 16K) aligned segments. +config ARM64_DCACHE_DISABLE + bool "Disable CPU Data Caches" + help + Disable CPU data cache usage by setting the SCTLR[C] bit during + kernel initialization. This will result in a considerable + performance impact, but may be useful in certain situations. + + If you are not sure what to do, select 'N' here. + +config ARM64_ICACHE_DISABLE + bool "Disable CPU Instruction Caches" + help + Disable CPU instruction cache usage by setting the SCTLR[I] + bit during kernel initialization. This will result in a + considerable performance impact, but may be useful in certain + situations. + + If you are not sure what to do, select 'N' here. + config ARM64_64K_PAGES bool "64KB" help @@ -453,6 +551,37 @@ endchoice +config MSM_APP_API + bool "API support to enable / disable app settings for MSM8996" + depends on ARCH_MSM8996 && (ENABLE_FP_SIMD_SETTINGS || MSM_APP_SETTINGS) + help + Add API support to enable / disable the app settings to be used + at runtime. These APIs are used to enable / disable app setting + when specific aarch32 or aarch64 processes are running. + + If you are not sure what to do, select 'N' here. + +config ENABLE_FP_SIMD_SETTINGS + bool "Enable FP(Floating Point) Settings for Qualcomm MSM8996" + depends on ARCH_MSM8996 + select MSM_APP_API + help + Enable FP(Floating Point) and SIMD settings for the MSM8996 during + the execution of the aarch32 processes and disable these settings + when you switch to the aarch64 processes. + + If you are not sure what to do, select 'N' here. + +config MSM_APP_SETTINGS + bool "Support to enable / disable app settings for MSM8996" + depends on ARCH_MSM8996 + select MSM_APP_API + help + Expose an interface used by the userspace at runtime to + enable / disable the app specific settings. + + If you are not sure what to do, select 'N' here. + choice prompt "Virtual address space size" default ARM64_VA_BITS_39 if ARM64_4K_PAGES @@ -524,9 +653,38 @@ Say Y here to experiment with turning CPUs off and on. CPUs can be controlled through /sys/devices/system/cpu. +config ARCH_ENABLE_MEMORY_HOTPLUG + depends on !NUMA + def_bool y + +config ARCH_ENABLE_MEMORY_HOTREMOVE + def_bool y + +# The GPIO number here must be sorted by descending number. In case of +# a multiplatform kernel, we just want the highest value required by the +# selected platforms. +config ARCH_NR_GPIO + int + default 1024 if ARCH_TEGRA + default 1024 if ARCH_QCOM + default 256 + help + Maximum number of GPIOs in the system. + + If unsure, leave the default value. + +config QCOM_TLB_EL2_HANDLER + bool "Raise TLB conflict exception to EL2" + help + This option enables TLB conflict to be handled + by EL2. + source kernel/Kconfig.preempt source kernel/Kconfig.hz +config ARCH_SUPPORTS_DEBUG_PAGEALLOC + def_bool y + config ARCH_HAS_HOLES_MEMORYMODEL def_bool y if SPARSEMEM @@ -547,10 +705,34 @@ def_bool y depends on ARM_PMU -config SYS_SUPPORTS_HUGETLBFS - def_bool y +config ARM64_REG_REBALANCE_ON_CTX_SW + bool "Rebalance registers during context switches." + def_bool ARCH_MSM8996 + help + Forcefully re-balance register rename pools on context switches for + improved performance on some devices. + +config PERF_EVENTS_USERMODE + bool "Enable usermode access for perf events" + depends on PERF_EVENTS + help + Enable user-mode access to performance counters for perf events. + If enabled, the access permissions allowing CPU performance + counters to be accessed from user-mode are set. + + If you want user-mode programs to access perf events, say Y + +config PERF_EVENTS_RESET_PMU_DEBUGFS + bool "Reset PMU via debugfs node" + depends on PERF_EVENTS + help + Enable the debugfs node that can be used to reset PMUs and all + state variables associated with PMUs. If enabled, PMU and internal + state variable are cleared. + If you want to reset PMU and PMU related internal Perf variables + via debugfs then say Y. -config ARCH_WANT_GENERAL_HUGETLB +config SYS_SUPPORTS_HUGETLBFS def_bool y config ARCH_WANT_HUGE_PMD_SHARE @@ -564,6 +746,10 @@ source "mm/Kconfig" +config ARCH_MEMORY_PROBE + def_bool y + depends on MEMORY_HOTPLUG + config SECCOMP bool "Enable seccomp to safely compute untrusted bytecode" ---help--- @@ -611,6 +797,35 @@ However for 4K, we choose a higher default value, 11 as opposed to 10, giving us 4M allocations matching the default size used by generic code. +config UNMAP_KERNEL_AT_EL0 + bool "Unmap kernel when running in userspace (aka \"KAISER\")" if EXPERT + default y + help + Speculation attacks against some high-performance processors can + be used to bypass MMU permission checks and leak kernel data to + userspace. This can be defended against by unmapping the kernel + when running in userspace, mapping it back in on exception entry + via a trampoline page in the vector table. + + If unsure, say Y. + +config HARDEN_BRANCH_PREDICTOR + bool "Harden the branch predictor against aliasing attacks" if EXPERT + default y + help + Speculation attacks against some high-performance processors rely on + being able to manipulate the branch predictor for a victim context by + executing aliasing branches in the attacker context. Such attacks + can be partially mitigated against by clearing internal branch + predictor state and limiting the prediction logic in some situations. + + This config option will take CPU-specific actions to harden the + branch predictor against aliasing attacks and may rely on specific + instruction sequences or control bits being set by the system + firmware. + + If unsure, say Y. + menuconfig ARMV8_DEPRECATED bool "Emulate deprecated/obsolete ARMv8 instructions" depends on COMPAT @@ -678,11 +893,18 @@ If unsure, say Y endif +config ARM64_SW_TTBR0_PAN + bool "Emulate Privileged Access Never using TTBR0_EL1 switching" + help + Enabling this option prevents the kernel from accessing + user-space memory directly by pointing TTBR0_EL1 to a reserved + zeroed area and reserved ASID. The user access routines + restore the valid TTBR0_EL1 temporarily. + menu "ARMv8.1 architectural features" config ARM64_HW_AFDBM bool "Support for hardware updates of the Access and Dirty page flags" - default y help The ARMv8.1 architecture extensions introduce support for hardware updates of the access and dirty information in page @@ -699,7 +921,6 @@ config ARM64_PAN bool "Enable support for Privileged Access Never (PAN)" - default y help Privileged Access Never (PAN; part of the ARMv8.1 Extensions) prevents the kernel or hypervisor from accessing user-space (EL0) @@ -725,10 +946,92 @@ endmenu +config ARM64_UAO + bool "Enable support for User Access Override (UAO)" + help + User Access Override (UAO; part of the ARMv8.2 Extensions) + causes the 'unprivileged' variant of the load/store instructions to + be overriden to be privileged. + + This option changes get_user() and friends to use the 'unprivileged' + variant of the load/store instructions. This ensures that user-space + really did have access to the supplied memory. When addr_limit is + set to kernel memory the UAO bit will be set, allowing privileged + access to kernel memory. + + Choosing this option will cause copy_to_user() et al to use user-space + memory permissions. + + The feature is detected at runtime, the kernel will use the + regular load/store instructions if the cpu does not implement the + feature. + +config ARM64_MODULE_CMODEL_LARGE + bool + +config ARM64_MODULE_PLTS + bool + select ARM64_MODULE_CMODEL_LARGE + select HAVE_MOD_ARCH_SPECIFIC + +config RELOCATABLE + bool + help + This builds the kernel as a Position Independent Executable (PIE), + which retains all relocation metadata required to relocate the + kernel binary at runtime to a different virtual address than the + address it was linked at. + Since AArch64 uses the RELA relocation format, this requires a + relocation pass at runtime even if the kernel is loaded at the + same address it was linked at. + +config RANDOMIZE_BASE + bool "Randomize the address of the kernel image" + select ARM64_MODULE_PLTS if MODULES + select RELOCATABLE + help + Randomizes the virtual address at which the kernel image is + loaded, as a security feature that deters exploit attempts + relying on knowledge of the location of kernel internals. + + It is the bootloader's job to provide entropy, by passing a + random u64 value in /chosen/kaslr-seed at kernel entry. + + When booting via the UEFI stub, it will invoke the firmware's + EFI_RNG_PROTOCOL implementation (if available) to supply entropy + to the kernel proper. In addition, it will randomise the physical + location of the kernel Image as well. + + If unsure, say N. + +config RANDOMIZE_MODULE_REGION_FULL + bool "Randomize the module region independently from the core kernel" + depends on RANDOMIZE_BASE && !DYNAMIC_FTRACE + default y + help + Randomizes the location of the module region without considering the + location of the core kernel. This way, it is impossible for modules + to leak information about the location of core kernel data structures + but it does imply that function calls between modules and the core + kernel will need to be resolved via veneers in the module PLT. + + When this option is not set, the module region will be randomized over + a limited range that contains the [_stext, _etext] interval of the + core kernel, so branch relocations are always in range. + endmenu menu "Boot options" +config ARM64_ACPI_PARKING_PROTOCOL + bool "Enable support for the ARM64 ACPI parking protocol" + depends on ACPI + help + Enable support for the ARM64 ACPI parking protocol. If disabled + the kernel will not allow booting through the ARM64 ACPI parking + protocol even if the corresponding data is present in the ACPI + MADT table. + config CMDLINE string "Default kernel command string" default "" @@ -737,6 +1040,23 @@ entering them here. As a minimum, you should specify the the root device (e.g. root=/dev/nfs). +choice + prompt "Kernel command line type" if CMDLINE != "" + default CMDLINE_FROM_BOOTLOADER + +config CMDLINE_FROM_BOOTLOADER + bool "Use bootloader kernel arguments if available" + help + Uses the command-line options passed by the boot loader. If + the boot loader doesn't provide any, the default kernel command + string provided in CMDLINE will be used. + +config CMDLINE_EXTEND + bool "Extend bootloader kernel arguments" + help + The command-line arguments provided by the boot loader will be + appended to the default kernel command string. + config CMDLINE_FORCE bool "Always use the default kernel command string" help @@ -744,6 +1064,7 @@ loader passes other arguments to the kernel. This is useful if you cannot or don't want to change the command-line options your boot loader passes to the kernel. +endchoice config EFI_STUB bool @@ -776,6 +1097,46 @@ However, even with this option, the resultant kernel should continue to boot on existing non-UEFI platforms. +config BUILD_ARM64_APPENDED_DTB_IMAGE + bool "Build a concatenated Image.gz/dtb by default" + depends on OF + help + Enabling this option will cause a concatenated Image.gz and list of + DTBs to be built by default (instead of a standalone Image.gz.) + The image will built in arch/arm64/boot/Image.gz-dtb + +choice + prompt "Appended DTB Kernel Image name" + depends on BUILD_ARM64_APPENDED_DTB_IMAGE + help + Enabling this option will cause a specific kernel image Image or + Image.gz to be used for final image creation. + The image will built in arch/arm64/boot/IMAGE-NAME-dtb + + config IMG_GZ_DTB + bool "Image.gz-dtb" + config IMG_DTB + bool "Image-dtb" +endchoice + +config BUILD_ARM64_APPENDED_KERNEL_IMAGE_NAME + string + depends on BUILD_ARM64_APPENDED_DTB_IMAGE + default "Image.gz-dtb" if IMG_GZ_DTB + default "Image-dtb" if IMG_DTB + +config BUILD_ARM64_APPENDED_DTB_IMAGE_NAMES + string "Default dtb names" + depends on BUILD_ARM64_APPENDED_DTB_IMAGE + help + Space separated list of names of dtbs to append when + building a concatenated Image.gz-dtb. + +config BUILD_ARM64_DT_OVERLAY + bool "enable DT overlay compilation support" + depends on OF + help + This option enables support for DT overlay compilation. endmenu menu "Userspace binary formats" @@ -811,6 +1172,14 @@ source "kernel/power/Kconfig" +config ARCH_HIBERNATION_POSSIBLE + def_bool y + depends on CPU_PM + +config ARCH_HIBERNATION_HEADER + def_bool y + depends on HIBERNATION + config ARCH_SUSPEND_POSSIBLE def_bool y diff -ruw linux-4.4.115/arch/arm64/Kconfig.debug linux-4.4.115-fbx/arch/arm64/Kconfig.debug --- linux-4.4.115/arch/arm64/Kconfig.debug 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/arch/arm64/Kconfig.debug 2019-01-22 16:16:21.523228476 +0100 @@ -64,16 +64,16 @@ config DEBUG_RODATA bool "Make kernel text and rodata read-only" + default y help If this is set, kernel text and rodata will be made read-only. This is to help catch accidental or malicious attempts to change the - kernel's executable code. Additionally splits rodata from kernel - text so it can be made explicitly non-executable. + kernel's executable code. If in doubt, say Y config DEBUG_ALIGN_RODATA - depends on DEBUG_RODATA && ARM64_4K_PAGES + depends on DEBUG_RODATA bool "Align linker sections up to SECTION_SIZE" help If this option is enabled, sections that may potentially be marked as @@ -85,6 +85,46 @@ If in doubt, say N +config FORCE_PAGES + bool "Force lowmem to be mapped with 4K pages" + help + There are some advanced debug features that can only be done when + memory is mapped with pages instead of sections. Enable this option + to always map lowmem pages with pages. This may have a performance + cost due to increased TLB pressure. + + If unsure say N. + +config FREE_PAGES_RDONLY + bool "Set pages as read only while on the buddy list" + select FORCE_PAGES + select DEBUG_PAGEALLOC + help + Pages are always mapped in the kernel. This means that anyone + can write to the page if they have the address. Enable this option + to mark pages as read only to trigger a fault if any code attempts + to write to a page on the buddy list. This may have a performance + impact. + + If unsure, say N. + +config KERNEL_TEXT_RDONLY + bool "Set kernel text section pages as read only" + depends on FREE_PAGES_RDONLY + depends on !DEBUG_RODATA + help + The kernel text pages are always mapped in the kernel. + This means that anyone can write to the page if they have + the address. Enable this option to mark the kernel text pages + as read only to trigger a fault if any code attempts to write + to a page part of the kernel text section. This may have a + performance impact. + + If unsure, say N. + +config ARM64_STRICT_BREAK_BEFORE_MAKE + bool "Enforce strict break-before-make on page table updates " + source "drivers/hwtracing/coresight/Kconfig" endmenu diff -ruw linux-4.4.115/arch/arm64/Kconfig.platforms linux-4.4.115-fbx/arch/arm64/Kconfig.platforms --- linux-4.4.115/arch/arm64/Kconfig.platforms 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/arch/arm64/Kconfig.platforms 2019-10-29 09:26:22.989196778 +0100 @@ -49,9 +49,65 @@ config ARCH_QCOM bool "Qualcomm Platforms" select PINCTRL + select CLKDEV_LOOKUP + select HAVE_CLK + select HAVE_CLK_PREPARE + select PM_OPP + select SOC_BUS + select MSM_IRQ + select THERMAL_WRITABLE_TRIPS + select RATIONAL + select ARCH_HAS_RESET_CONTROLLER help This enables support for the ARMv8 based Qualcomm chipsets. +config ARCH_MSM8996 + bool "Enable Support for Qualcomm MSM8996" + depends on ARCH_QCOM + select COMMON_CLK_MSM + help + This enables support for the MSM8996 chipset. If you do not + wish to build a kernel that runs on this chipset, say 'N' here. + +config ARCH_MSM8998 + bool "Enable Support for Qualcomm MSM8998" + depends on ARCH_QCOM + select COMMON_CLK_MSM + help + This enables support for the MSM8998 chipset. If you do not + wish to build a kernel that runs on this chipset, say 'N' here. + +config ARCH_MSMHAMSTER + bool "Enable Support for Qualcomm Technologies Inc MSMHAMSTER" + depends on ARCH_QCOM + select COMMON_CLK_MSM + help + This enables support for the MSMHAMSTER chipset. + If you do not wish to build a kernel that runs + on this chipset,say 'N' here. + +config ARCH_SDM660 + bool "Enable Support for Qualcomm Technologies Inc SDM660" + depends on ARCH_QCOM + select COMMON_CLK + select COMMON_CLK_QCOM + select QCOM_GDSC + help + This enables support for the SDM660 chipset. + If you do not wish to build a kernel that runs + on this chipset,say 'N' here. + +config ARCH_SDM630 + bool "Enable Support for Qualcomm Technologies Inc SDM630" + depends on ARCH_QCOM + select COMMON_CLK + select COMMON_CLK_QCOM + select QCOM_GDSC + help + This enables support for the SDM630 chipset. + If you do not wish to build a kernel that runs + on this chipset,say 'N' here. + config ARCH_ROCKCHIP bool "Rockchip Platforms" select ARCH_HAS_RESET_CONTROLLER diff -ruw linux-4.4.115/arch/arm64/kernel/alternative.c linux-4.4.115-fbx/arch/arm64/kernel/alternative.c --- linux-4.4.115/arch/arm64/kernel/alternative.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/arch/arm64/kernel/alternative.c 2019-10-29 09:26:23.001196895 +0100 @@ -108,7 +108,7 @@ for (i = 0; i < nr_inst; i++) { insn = get_alt_insn(alt, origptr + i, replptr + i); - *(origptr + i) = cpu_to_le32(insn); + BUG_ON(aarch64_insn_patch_text_nosync(origptr + i, insn)); } flush_icache_range((uintptr_t)origptr, @@ -158,9 +158,3 @@ __apply_alternatives(®ion); } - -void free_alternatives_memory(void) -{ - free_reserved_area(__alt_instructions, __alt_instructions_end, - 0, "alternatives"); -} diff -ruw linux-4.4.115/arch/arm64/kernel/arm64ksyms.c linux-4.4.115-fbx/arch/arm64/kernel/arm64ksyms.c --- linux-4.4.115/arch/arm64/kernel/arm64ksyms.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/arch/arm64/kernel/arm64ksyms.c 2019-01-22 16:16:21.547228694 +0100 @@ -26,15 +26,18 @@ #include #include #include +#include +#include +#include #include EXPORT_SYMBOL(copy_page); EXPORT_SYMBOL(clear_page); /* user mem (segment) */ -EXPORT_SYMBOL(__copy_from_user); -EXPORT_SYMBOL(__copy_to_user); +EXPORT_SYMBOL(__arch_copy_from_user); +EXPORT_SYMBOL(__arch_copy_to_user); EXPORT_SYMBOL(__clear_user); EXPORT_SYMBOL(__copy_in_user); @@ -67,4 +70,13 @@ #ifdef CONFIG_FUNCTION_TRACER EXPORT_SYMBOL(_mcount); +NOKPROBE_SYMBOL(_mcount); #endif + /* caching functions */ +EXPORT_SYMBOL(__dma_inv_range); +EXPORT_SYMBOL(__dma_clean_range); +EXPORT_SYMBOL(__dma_flush_range); + + /* arm-smccc */ +EXPORT_SYMBOL(arm_smccc_smc); +EXPORT_SYMBOL(arm_smccc_hvc); diff -ruw linux-4.4.115/arch/arm64/kernel/armv8_deprecated.c linux-4.4.115-fbx/arch/arm64/kernel/armv8_deprecated.c --- linux-4.4.115/arch/arm64/kernel/armv8_deprecated.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/arch/arm64/kernel/armv8_deprecated.c 2019-01-22 16:16:21.547228694 +0100 @@ -14,7 +14,6 @@ #include #include -#include #include #include #include @@ -62,7 +61,7 @@ }; static LIST_HEAD(insn_emulation); -static int nr_insn_emulated; +static int nr_insn_emulated __initdata; static DEFINE_RAW_SPINLOCK(insn_emulation_lock); static void register_emulation_hooks(struct insn_emulation_ops *ops) @@ -173,7 +172,7 @@ return ret; } -static void register_insn_emulation(struct insn_emulation_ops *ops) +static void __init register_insn_emulation(struct insn_emulation_ops *ops) { unsigned long flags; struct insn_emulation *insn; @@ -237,7 +236,7 @@ { } }; -static void register_insn_emulation_sysctl(struct ctl_table *table) +static void __init register_insn_emulation_sysctl(struct ctl_table *table) { unsigned long flags; int i = 0; @@ -281,9 +280,9 @@ * Error-checking SWP macros implemented using ldxr{b}/stxr{b} */ #define __user_swpX_asm(data, addr, res, temp, B) \ +do { \ + uaccess_enable(); \ __asm__ __volatile__( \ - ALTERNATIVE("nop", SET_PSTATE_PAN(0), ARM64_HAS_PAN, \ - CONFIG_ARM64_PAN) \ "0: ldxr"B" %w2, [%3]\n" \ "1: stxr"B" %w0, %w1, [%3]\n" \ " cbz %w0, 2f\n" \ @@ -297,17 +296,14 @@ "4: mov %w0, %w5\n" \ " b 3b\n" \ " .popsection" \ - " .pushsection __ex_table,\"a\"\n" \ - " .align 3\n" \ - " .quad 0b, 4b\n" \ - " .quad 1b, 4b\n" \ - " .popsection\n" \ - ALTERNATIVE("nop", SET_PSTATE_PAN(1), ARM64_HAS_PAN, \ - CONFIG_ARM64_PAN) \ + _ASM_EXTABLE(0b, 4b) \ + _ASM_EXTABLE(1b, 4b) \ : "=&r" (res), "+r" (data), "=&r" (temp) \ : "r" ((unsigned long)addr), "i" (-EAGAIN), \ "i" (-EFAULT) \ - : "memory") + : "memory"); \ + uaccess_disable(); \ +} while (0) #define __user_swp_asm(data, addr, res, temp) \ __user_swpX_asm(data, addr, res, temp, "") @@ -370,6 +366,21 @@ return res; } +#define ARM_OPCODE_CONDITION_UNCOND 0xf + +static unsigned int __kprobes aarch32_check_condition(u32 opcode, u32 psr) +{ + u32 cc_bits = opcode >> 28; + + if (cc_bits != ARM_OPCODE_CONDITION_UNCOND) { + if ((*aarch32_opcode_cond_checks[cc_bits])(psr)) + return ARM_OPCODE_CONDTEST_PASS; + else + return ARM_OPCODE_CONDTEST_FAIL; + } + return ARM_OPCODE_CONDTEST_UNCOND; +} + /* * swp_handler logs the id of calling process, dissects the instruction, sanity * checks the memory location, calls emulate_swpX for the actual operation and @@ -384,7 +395,7 @@ type = instr & TYPE_SWPB; - switch (arm_check_condition(instr, regs->pstate)) { + switch (aarch32_check_condition(instr, regs->pstate)) { case ARM_OPCODE_CONDTEST_PASS: break; case ARM_OPCODE_CONDTEST_FAIL: @@ -465,7 +476,7 @@ { perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, regs, regs->pc); - switch (arm_check_condition(instr, regs->pstate)) { + switch (aarch32_check_condition(instr, regs->pstate)) { case ARM_OPCODE_CONDTEST_PASS: break; case ARM_OPCODE_CONDTEST_FAIL: diff -ruw linux-4.4.115/arch/arm64/kernel/asm-offsets.c linux-4.4.115-fbx/arch/arm64/kernel/asm-offsets.c --- linux-4.4.115/arch/arm64/kernel/asm-offsets.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/arch/arm64/kernel/asm-offsets.c 2019-01-22 16:16:21.547228694 +0100 @@ -22,22 +22,33 @@ #include #include #include +#include +#include #include #include #include #include #include #include +#include int main(void) { DEFINE(TSK_ACTIVE_MM, offsetof(struct task_struct, active_mm)); BLANK(); +#ifdef CONFIG_THREAD_INFO_IN_TASK + DEFINE(TSK_TI_FLAGS, offsetof(struct task_struct, thread_info.flags)); + DEFINE(TSK_TI_PREEMPT, offsetof(struct task_struct, thread_info.preempt_count)); + DEFINE(TSK_TI_ADDR_LIMIT, offsetof(struct task_struct, thread_info.addr_limit)); + DEFINE(TSK_STACK, offsetof(struct task_struct, stack)); +#else DEFINE(TI_FLAGS, offsetof(struct thread_info, flags)); DEFINE(TI_PREEMPT, offsetof(struct thread_info, preempt_count)); DEFINE(TI_ADDR_LIMIT, offsetof(struct thread_info, addr_limit)); - DEFINE(TI_TASK, offsetof(struct thread_info, task)); - DEFINE(TI_CPU, offsetof(struct thread_info, cpu)); +#endif +#ifdef CONFIG_ARM64_SW_TTBR0_PAN + DEFINE(TSK_TI_TTBR0, offsetof(struct thread_info, ttbr0)); +#endif BLANK(); DEFINE(THREAD_CPU_CONTEXT, offsetof(struct task_struct, thread.cpu_context)); BLANK(); @@ -49,6 +60,17 @@ DEFINE(S_X5, offsetof(struct pt_regs, regs[5])); DEFINE(S_X6, offsetof(struct pt_regs, regs[6])); DEFINE(S_X7, offsetof(struct pt_regs, regs[7])); + DEFINE(S_X8, offsetof(struct pt_regs, regs[8])); + DEFINE(S_X10, offsetof(struct pt_regs, regs[10])); + DEFINE(S_X12, offsetof(struct pt_regs, regs[12])); + DEFINE(S_X14, offsetof(struct pt_regs, regs[14])); + DEFINE(S_X16, offsetof(struct pt_regs, regs[16])); + DEFINE(S_X18, offsetof(struct pt_regs, regs[18])); + DEFINE(S_X20, offsetof(struct pt_regs, regs[20])); + DEFINE(S_X22, offsetof(struct pt_regs, regs[22])); + DEFINE(S_X24, offsetof(struct pt_regs, regs[24])); + DEFINE(S_X26, offsetof(struct pt_regs, regs[26])); + DEFINE(S_X28, offsetof(struct pt_regs, regs[28])); DEFINE(S_LR, offsetof(struct pt_regs, regs[30])); DEFINE(S_SP, offsetof(struct pt_regs, sp)); #ifdef CONFIG_COMPAT @@ -76,6 +98,7 @@ BLANK(); DEFINE(CLOCK_REALTIME, CLOCK_REALTIME); DEFINE(CLOCK_MONOTONIC, CLOCK_MONOTONIC); + DEFINE(CLOCK_MONOTONIC_RAW, CLOCK_MONOTONIC_RAW); DEFINE(CLOCK_REALTIME_RES, MONOTONIC_RES_NSEC); DEFINE(CLOCK_REALTIME_COARSE, CLOCK_REALTIME_COARSE); DEFINE(CLOCK_MONOTONIC_COARSE,CLOCK_MONOTONIC_COARSE); @@ -83,6 +106,8 @@ DEFINE(NSEC_PER_SEC, NSEC_PER_SEC); BLANK(); DEFINE(VDSO_CS_CYCLE_LAST, offsetof(struct vdso_data, cs_cycle_last)); + DEFINE(VDSO_RAW_TIME_SEC, offsetof(struct vdso_data, raw_time_sec)); + DEFINE(VDSO_RAW_TIME_NSEC, offsetof(struct vdso_data, raw_time_nsec)); DEFINE(VDSO_XTIME_CLK_SEC, offsetof(struct vdso_data, xtime_clock_sec)); DEFINE(VDSO_XTIME_CLK_NSEC, offsetof(struct vdso_data, xtime_clock_nsec)); DEFINE(VDSO_XTIME_CRS_SEC, offsetof(struct vdso_data, xtime_coarse_sec)); @@ -90,7 +115,8 @@ DEFINE(VDSO_WTM_CLK_SEC, offsetof(struct vdso_data, wtm_clock_sec)); DEFINE(VDSO_WTM_CLK_NSEC, offsetof(struct vdso_data, wtm_clock_nsec)); DEFINE(VDSO_TB_SEQ_COUNT, offsetof(struct vdso_data, tb_seq_count)); - DEFINE(VDSO_CS_MULT, offsetof(struct vdso_data, cs_mult)); + DEFINE(VDSO_CS_MONO_MULT, offsetof(struct vdso_data, cs_mono_mult)); + DEFINE(VDSO_CS_RAW_MULT, offsetof(struct vdso_data, cs_raw_mult)); DEFINE(VDSO_CS_SHIFT, offsetof(struct vdso_data, cs_shift)); DEFINE(VDSO_TZ_MINWEST, offsetof(struct vdso_data, tz_minuteswest)); DEFINE(VDSO_TZ_DSTTIME, offsetof(struct vdso_data, tz_dsttime)); @@ -104,63 +130,39 @@ DEFINE(TZ_MINWEST, offsetof(struct timezone, tz_minuteswest)); DEFINE(TZ_DSTTIME, offsetof(struct timezone, tz_dsttime)); BLANK(); +#ifdef CONFIG_THREAD_INFO_IN_TASK + DEFINE(CPU_BOOT_STACK, offsetof(struct secondary_data, stack)); + DEFINE(CPU_BOOT_TASK, offsetof(struct secondary_data, task)); + BLANK(); +#endif #ifdef CONFIG_KVM_ARM_HOST DEFINE(VCPU_CONTEXT, offsetof(struct kvm_vcpu, arch.ctxt)); DEFINE(CPU_GP_REGS, offsetof(struct kvm_cpu_context, gp_regs)); DEFINE(CPU_USER_PT_REGS, offsetof(struct kvm_regs, regs)); DEFINE(CPU_FP_REGS, offsetof(struct kvm_regs, fp_regs)); - DEFINE(CPU_SP_EL1, offsetof(struct kvm_regs, sp_el1)); - DEFINE(CPU_ELR_EL1, offsetof(struct kvm_regs, elr_el1)); - DEFINE(CPU_SPSR, offsetof(struct kvm_regs, spsr)); - DEFINE(CPU_SYSREGS, offsetof(struct kvm_cpu_context, sys_regs)); + DEFINE(VCPU_FPEXC32_EL2, offsetof(struct kvm_vcpu, arch.ctxt.sys_regs[FPEXC32_EL2])); DEFINE(VCPU_ESR_EL2, offsetof(struct kvm_vcpu, arch.fault.esr_el2)); DEFINE(VCPU_FAR_EL2, offsetof(struct kvm_vcpu, arch.fault.far_el2)); DEFINE(VCPU_HPFAR_EL2, offsetof(struct kvm_vcpu, arch.fault.hpfar_el2)); - DEFINE(VCPU_DEBUG_FLAGS, offsetof(struct kvm_vcpu, arch.debug_flags)); - DEFINE(VCPU_DEBUG_PTR, offsetof(struct kvm_vcpu, arch.debug_ptr)); - DEFINE(DEBUG_BCR, offsetof(struct kvm_guest_debug_arch, dbg_bcr)); - DEFINE(DEBUG_BVR, offsetof(struct kvm_guest_debug_arch, dbg_bvr)); - DEFINE(DEBUG_WCR, offsetof(struct kvm_guest_debug_arch, dbg_wcr)); - DEFINE(DEBUG_WVR, offsetof(struct kvm_guest_debug_arch, dbg_wvr)); - DEFINE(VCPU_HCR_EL2, offsetof(struct kvm_vcpu, arch.hcr_el2)); - DEFINE(VCPU_MDCR_EL2, offsetof(struct kvm_vcpu, arch.mdcr_el2)); - DEFINE(VCPU_IRQ_LINES, offsetof(struct kvm_vcpu, arch.irq_lines)); DEFINE(VCPU_HOST_CONTEXT, offsetof(struct kvm_vcpu, arch.host_cpu_context)); - DEFINE(VCPU_HOST_DEBUG_STATE, offsetof(struct kvm_vcpu, arch.host_debug_state)); - DEFINE(VCPU_TIMER_CNTV_CTL, offsetof(struct kvm_vcpu, arch.timer_cpu.cntv_ctl)); - DEFINE(VCPU_TIMER_CNTV_CVAL, offsetof(struct kvm_vcpu, arch.timer_cpu.cntv_cval)); - DEFINE(KVM_TIMER_CNTVOFF, offsetof(struct kvm, arch.timer.cntvoff)); - DEFINE(KVM_TIMER_ENABLED, offsetof(struct kvm, arch.timer.enabled)); - DEFINE(VCPU_KVM, offsetof(struct kvm_vcpu, kvm)); - DEFINE(VCPU_VGIC_CPU, offsetof(struct kvm_vcpu, arch.vgic_cpu)); - DEFINE(VGIC_V2_CPU_HCR, offsetof(struct vgic_cpu, vgic_v2.vgic_hcr)); - DEFINE(VGIC_V2_CPU_VMCR, offsetof(struct vgic_cpu, vgic_v2.vgic_vmcr)); - DEFINE(VGIC_V2_CPU_MISR, offsetof(struct vgic_cpu, vgic_v2.vgic_misr)); - DEFINE(VGIC_V2_CPU_EISR, offsetof(struct vgic_cpu, vgic_v2.vgic_eisr)); - DEFINE(VGIC_V2_CPU_ELRSR, offsetof(struct vgic_cpu, vgic_v2.vgic_elrsr)); - DEFINE(VGIC_V2_CPU_APR, offsetof(struct vgic_cpu, vgic_v2.vgic_apr)); - DEFINE(VGIC_V2_CPU_LR, offsetof(struct vgic_cpu, vgic_v2.vgic_lr)); - DEFINE(VGIC_V3_CPU_SRE, offsetof(struct vgic_cpu, vgic_v3.vgic_sre)); - DEFINE(VGIC_V3_CPU_HCR, offsetof(struct vgic_cpu, vgic_v3.vgic_hcr)); - DEFINE(VGIC_V3_CPU_VMCR, offsetof(struct vgic_cpu, vgic_v3.vgic_vmcr)); - DEFINE(VGIC_V3_CPU_MISR, offsetof(struct vgic_cpu, vgic_v3.vgic_misr)); - DEFINE(VGIC_V3_CPU_EISR, offsetof(struct vgic_cpu, vgic_v3.vgic_eisr)); - DEFINE(VGIC_V3_CPU_ELRSR, offsetof(struct vgic_cpu, vgic_v3.vgic_elrsr)); - DEFINE(VGIC_V3_CPU_AP0R, offsetof(struct vgic_cpu, vgic_v3.vgic_ap0r)); - DEFINE(VGIC_V3_CPU_AP1R, offsetof(struct vgic_cpu, vgic_v3.vgic_ap1r)); - DEFINE(VGIC_V3_CPU_LR, offsetof(struct vgic_cpu, vgic_v3.vgic_lr)); - DEFINE(VGIC_CPU_NR_LR, offsetof(struct vgic_cpu, nr_lr)); - DEFINE(KVM_VTTBR, offsetof(struct kvm, arch.vttbr)); - DEFINE(KVM_VGIC_VCTRL, offsetof(struct kvm, arch.vgic.vctrl_base)); #endif #ifdef CONFIG_CPU_PM DEFINE(CPU_SUSPEND_SZ, sizeof(struct cpu_suspend_ctx)); DEFINE(CPU_CTX_SP, offsetof(struct cpu_suspend_ctx, sp)); DEFINE(MPIDR_HASH_MASK, offsetof(struct mpidr_hash, mask)); DEFINE(MPIDR_HASH_SHIFTS, offsetof(struct mpidr_hash, shift_aff)); - DEFINE(SLEEP_SAVE_SP_SZ, sizeof(struct sleep_save_sp)); - DEFINE(SLEEP_SAVE_SP_PHYS, offsetof(struct sleep_save_sp, save_ptr_stash_phys)); - DEFINE(SLEEP_SAVE_SP_VIRT, offsetof(struct sleep_save_sp, save_ptr_stash)); + DEFINE(SLEEP_STACK_DATA_SYSTEM_REGS, offsetof(struct sleep_stack_data, system_regs)); + DEFINE(SLEEP_STACK_DATA_CALLEE_REGS, offsetof(struct sleep_stack_data, callee_saved_regs)); +#endif + DEFINE(ARM_SMCCC_RES_X0_OFFS, offsetof(struct arm_smccc_res, a0)); + DEFINE(ARM_SMCCC_RES_X2_OFFS, offsetof(struct arm_smccc_res, a2)); + BLANK(); + DEFINE(HIBERN_PBE_ORIG, offsetof(struct pbe, orig_address)); + DEFINE(HIBERN_PBE_ADDR, offsetof(struct pbe, address)); + DEFINE(HIBERN_PBE_NEXT, offsetof(struct pbe, next)); + BLANK(); +#ifdef CONFIG_UNMAP_KERNEL_AT_EL0 + DEFINE(TRAMP_VALIAS, TRAMP_VALIAS); #endif return 0; } diff -ruw linux-4.4.115/arch/arm64/kernel/cpu_errata.c linux-4.4.115-fbx/arch/arm64/kernel/cpu_errata.c --- linux-4.4.115/arch/arm64/kernel/cpu_errata.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/arch/arm64/kernel/cpu_errata.c 2019-01-22 16:16:21.547228694 +0100 @@ -21,32 +21,168 @@ #include #include -#define MIDR_CORTEX_A53 MIDR_CPU_PART(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A53) -#define MIDR_CORTEX_A57 MIDR_CPU_PART(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A57) -#define MIDR_THUNDERX MIDR_CPU_PART(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX) - -#define CPU_MODEL_MASK (MIDR_IMPLEMENTOR_MASK | MIDR_PARTNUM_MASK | \ - MIDR_ARCHITECTURE_MASK) - static bool __maybe_unused is_affected_midr_range(const struct arm64_cpu_capabilities *entry) { - u32 midr = read_cpuid_id(); + return MIDR_IS_CPU_MODEL_RANGE(read_cpuid_id(), entry->midr_model, + entry->midr_range_min, + entry->midr_range_max); +} + +static bool __maybe_unused +is_kryo_midr(const struct arm64_cpu_capabilities *entry) +{ + u32 model; + + model = read_cpuid_id(); + model &= MIDR_IMPLEMENTOR_MASK | (0xf00 << MIDR_PARTNUM_SHIFT) | + MIDR_ARCHITECTURE_MASK; + + return model == entry->midr_model; +} + +#ifdef CONFIG_HARDEN_BRANCH_PREDICTOR +#include +#include + +DEFINE_PER_CPU_READ_MOSTLY(struct bp_hardening_data, bp_hardening_data); + +#ifdef CONFIG_KVM +extern char __psci_hyp_bp_inval_start[], __psci_hyp_bp_inval_end[]; +extern char __qcom_hyp_sanitize_link_stack_start[]; +extern char __qcom_hyp_sanitize_link_stack_end[]; + +static void __copy_hyp_vect_bpi(int slot, const char *hyp_vecs_start, + const char *hyp_vecs_end) +{ + void *dst = lm_alias(__bp_harden_hyp_vecs_start + slot * SZ_2K); + int i; + + for (i = 0; i < SZ_2K; i += 0x80) + memcpy(dst + i, hyp_vecs_start, hyp_vecs_end - hyp_vecs_start); + + flush_icache_range((uintptr_t)dst, (uintptr_t)dst + SZ_2K); +} + +static void __install_bp_hardening_cb(bp_hardening_cb_t fn, + const char *hyp_vecs_start, + const char *hyp_vecs_end) +{ + static int last_slot = -1; + static DEFINE_SPINLOCK(bp_lock); + int cpu, slot = -1; + + spin_lock(&bp_lock); + for_each_possible_cpu(cpu) { + if (per_cpu(bp_hardening_data.fn, cpu) == fn) { + slot = per_cpu(bp_hardening_data.hyp_vectors_slot, cpu); + break; + } + } + + if (slot == -1) { + last_slot++; + BUG_ON(((__bp_harden_hyp_vecs_end - __bp_harden_hyp_vecs_start) + / SZ_2K) <= last_slot); + slot = last_slot; + __copy_hyp_vect_bpi(slot, hyp_vecs_start, hyp_vecs_end); + } + + __this_cpu_write(bp_hardening_data.hyp_vectors_slot, slot); + __this_cpu_write(bp_hardening_data.fn, fn); + spin_unlock(&bp_lock); +} +#else +#define __psci_hyp_bp_inval_start NULL +#define __psci_hyp_bp_inval_end NULL +#define __qcom_hyp_sanitize_link_stack_start NULL +#define __qcom_hyp_sanitize_link_stack_end NULL + +static void __maybe_unused __install_bp_hardening_cb(bp_hardening_cb_t fn, + const char *hyp_vecs_start, + const char *hyp_vecs_end) +{ + __this_cpu_write(bp_hardening_data.fn, fn); +} +#endif /* CONFIG_KVM */ - if ((midr & CPU_MODEL_MASK) != entry->midr_model) - return false; +static void __maybe_unused install_bp_hardening_cb( + const struct arm64_cpu_capabilities *entry, + bp_hardening_cb_t fn, + const char *hyp_vecs_start, + const char *hyp_vecs_end) +{ + u64 pfr0; - midr &= MIDR_REVISION_MASK | MIDR_VARIANT_MASK; + if (!entry->matches(entry)) + return; - return (midr >= entry->midr_range_min && midr <= entry->midr_range_max); + pfr0 = read_cpuid(SYS_ID_AA64PFR0_EL1); + if (cpuid_feature_extract_unsigned_field(pfr0, ID_AA64PFR0_CSV2_SHIFT)) + return; + + __install_bp_hardening_cb(fn, hyp_vecs_start, hyp_vecs_end); } +#include + +static int enable_psci_bp_hardening(void *data) +{ + const struct arm64_cpu_capabilities *entry = data; + + if (psci_ops.get_version) + install_bp_hardening_cb(entry, + (bp_hardening_cb_t)psci_ops.get_version, + __psci_hyp_bp_inval_start, + __psci_hyp_bp_inval_end); + + return 0; +} + +static void __maybe_unused qcom_link_stack_sanitization(void) +{ + u64 tmp; + + asm volatile("mov %0, x30 \n" + ".rept 16 \n" + "bl . + 4 \n" + ".endr \n" + "mov x30, %0 \n" + : "=&r" (tmp)); +} + +static void __maybe_unused qcom_bp_hardening(void) +{ + qcom_link_stack_sanitization(); + if (psci_ops.get_version) + psci_ops.get_version(); +} + +static int __maybe_unused enable_qcom_bp_hardening(void *data) +{ + const struct arm64_cpu_capabilities *entry = data; + + install_bp_hardening_cb(entry, + (bp_hardening_cb_t)qcom_bp_hardening, + __psci_hyp_bp_inval_start, + __psci_hyp_bp_inval_end); + return 0; +} + +#endif /* CONFIG_HARDEN_BRANCH_PREDICTOR */ + #define MIDR_RANGE(model, min, max) \ .matches = is_affected_midr_range, \ .midr_model = model, \ .midr_range_min = min, \ .midr_range_max = max +#define MIDR_ALL_VERSIONS(model) \ + .matches = is_affected_midr_range, \ + .midr_model = model, \ + .midr_range_min = 0, \ + .midr_range_max = (MIDR_VARIANT_MASK | MIDR_REVISION_MASK) + const struct arm64_cpu_capabilities arm64_errata[] = { #if defined(CONFIG_ARM64_ERRATUM_826319) || \ defined(CONFIG_ARM64_ERRATUM_827319) || \ @@ -91,6 +227,12 @@ .capability = ARM64_WORKAROUND_845719, MIDR_RANGE(MIDR_CORTEX_A53, 0x00, 0x04), }, + { + /* Kryo2xx Silver rAp4 */ + .desc = "Kryo2xx Silver erratum 845719", + .capability = ARM64_WORKAROUND_845719, + MIDR_RANGE(MIDR_KRYO2XX_SILVER, 0xA00004, 0xA00004), + }, #endif #ifdef CONFIG_CAVIUM_ERRATUM_23154 { @@ -109,6 +251,39 @@ (1 << MIDR_VARIANT_SHIFT) | 1), }, #endif +#ifdef CONFIG_HARDEN_BRANCH_PREDICTOR + { + .capability = ARM64_HARDEN_BRANCH_PREDICTOR, + MIDR_ALL_VERSIONS(MIDR_CORTEX_A57), + .enable = enable_psci_bp_hardening, + }, + { + .capability = ARM64_HARDEN_BRANCH_PREDICTOR, + MIDR_ALL_VERSIONS(MIDR_CORTEX_A72), + .enable = enable_psci_bp_hardening, + }, + { + .capability = ARM64_HARDEN_BRANCH_PREDICTOR, + MIDR_ALL_VERSIONS(MIDR_CORTEX_A73), + .enable = enable_psci_bp_hardening, + }, + { + .capability = ARM64_HARDEN_BRANCH_PREDICTOR, + MIDR_ALL_VERSIONS(MIDR_CORTEX_A75), + .enable = enable_psci_bp_hardening, + }, + { + .capability = ARM64_HARDEN_BRANCH_PREDICTOR, + MIDR_ALL_VERSIONS(MIDR_KRYO2XX_GOLD), + .enable = enable_psci_bp_hardening, + }, + { + .capability = ARM64_HARDEN_BRANCH_PREDICTOR, + .midr_model = MIDR_QCOM_KRYO, + .matches = is_kryo_midr, + .enable = enable_qcom_bp_hardening, + }, +#endif { } }; @@ -117,3 +292,8 @@ { update_cpu_capabilities(arm64_errata, "enabling workaround for"); } + +void __init enable_errata_workarounds(void) +{ + enable_cpu_capabilities(arm64_errata); +} diff -ruw linux-4.4.115/arch/arm64/kernel/cpufeature.c linux-4.4.115-fbx/arch/arm64/kernel/cpufeature.c --- linux-4.4.115/arch/arm64/kernel/cpufeature.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/arch/arm64/kernel/cpufeature.c 2019-10-29 09:26:23.001196895 +0100 @@ -23,11 +23,13 @@ #include #include #include +#include #include #include #include #include #include +#include unsigned long elf_hwcap __read_mostly; EXPORT_SYMBOL_GPL(elf_hwcap); @@ -45,6 +47,7 @@ #endif DECLARE_BITMAP(cpu_hwcaps, ARM64_NCAPS); +EXPORT_SYMBOL(cpu_hwcaps); #define __ARM64_FTR_BITS(SIGNED, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \ { \ @@ -69,6 +72,10 @@ .width = 0, \ } +/* meta feature for alternatives */ +static bool __maybe_unused +cpufeature_pan_not_uao(const struct arm64_cpu_capabilities *entry); + static struct arm64_ftr_bits ftr_id_aa64isar0[] = { ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 32, 32, 0), ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64ISAR0_RDM_SHIFT, 4, 0), @@ -85,6 +92,7 @@ static struct arm64_ftr_bits ftr_id_aa64pfr0[] = { ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 32, 32, 0), ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 28, 4, 0), + ARM64_FTR_BITS(FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_CSV2_SHIFT, 4, 0), ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64PFR0_GIC_SHIFT, 4, 0), ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_ASIMD_SHIFT, 4, ID_AA64PFR0_ASIMD_NI), ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_FP_SHIFT, 4, ID_AA64PFR0_FP_NI), @@ -125,6 +133,11 @@ ARM64_FTR_END, }; +static struct arm64_ftr_bits ftr_id_aa64mmfr2[] = { + ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR2_UAO_SHIFT, 4, 0), + ARM64_FTR_END, +}; + static struct arm64_ftr_bits ftr_ctr[] = { U_ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 31, 1, 1), /* RAO */ ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 28, 3, 0), @@ -286,6 +299,7 @@ /* Op1 = 0, CRn = 0, CRm = 7 */ ARM64_FTR_REG(SYS_ID_AA64MMFR0_EL1, ftr_id_aa64mmfr0), ARM64_FTR_REG(SYS_ID_AA64MMFR1_EL1, ftr_id_aa64mmfr1), + ARM64_FTR_REG(SYS_ID_AA64MMFR2_EL1, ftr_id_aa64mmfr2), /* Op1 = 3, CRn = 0, CRm = 0 */ ARM64_FTR_REG(SYS_CTR_EL0, ftr_ctr), @@ -410,6 +424,7 @@ init_cpu_ftr_reg(SYS_ID_AA64ISAR1_EL1, info->reg_id_aa64isar1); init_cpu_ftr_reg(SYS_ID_AA64MMFR0_EL1, info->reg_id_aa64mmfr0); init_cpu_ftr_reg(SYS_ID_AA64MMFR1_EL1, info->reg_id_aa64mmfr1); + init_cpu_ftr_reg(SYS_ID_AA64MMFR2_EL1, info->reg_id_aa64mmfr2); init_cpu_ftr_reg(SYS_ID_AA64PFR0_EL1, info->reg_id_aa64pfr0); init_cpu_ftr_reg(SYS_ID_AA64PFR1_EL1, info->reg_id_aa64pfr1); init_cpu_ftr_reg(SYS_ID_DFR0_EL1, info->reg_id_dfr0); @@ -519,6 +534,8 @@ info->reg_id_aa64mmfr0, boot->reg_id_aa64mmfr0); taint |= check_update_ftr_reg(SYS_ID_AA64MMFR1_EL1, cpu, info->reg_id_aa64mmfr1, boot->reg_id_aa64mmfr1); + taint |= check_update_ftr_reg(SYS_ID_AA64MMFR2_EL1, cpu, + info->reg_id_aa64mmfr2, boot->reg_id_aa64mmfr2); /* * EL3 is not our concern. @@ -623,6 +640,56 @@ return has_sre; } +static bool has_no_hw_prefetch(const struct arm64_cpu_capabilities *entry) +{ + u32 midr = read_cpuid_id(); + u32 rv_min, rv_max; + + /* Cavium ThunderX pass 1.x and 2.x */ + rv_min = 0; + rv_max = (1 << MIDR_VARIANT_SHIFT) | MIDR_REVISION_MASK; + + return MIDR_IS_CPU_MODEL_RANGE(midr, MIDR_THUNDERX, rv_min, rv_max); +} + +static bool runs_at_el2(const struct arm64_cpu_capabilities *entry) +{ + return is_kernel_in_hyp_mode(); +} + +#ifdef CONFIG_UNMAP_KERNEL_AT_EL0 +static int __kpti_forced; /* 0: not forced, >0: forced on, <0: forced off */ + +static bool unmap_kernel_at_el0(const struct arm64_cpu_capabilities *entry) +{ + /* Forced on command line? */ + if (__kpti_forced) { + pr_info_once("kernel page table isolation forced %s by command line option\n", + __kpti_forced > 0 ? "ON" : "OFF"); + return __kpti_forced > 0; + } + + /* Useful for KASLR robustness */ + if (IS_ENABLED(CONFIG_RANDOMIZE_BASE)) + return true; + + return false; +} + +static int __init parse_kpti(char *str) +{ + bool enabled; + int ret = strtobool(str, &enabled); + + if (ret) + return ret; + + __kpti_forced = enabled ? 1 : -1; + return 0; +} +__setup("kpti=", parse_kpti); +#endif /* CONFIG_UNMAP_KERNEL_AT_EL0 */ + static const struct arm64_cpu_capabilities arm64_features[] = { { .desc = "GIC system register CPU interface", @@ -653,6 +720,39 @@ .min_field_value = 2, }, #endif /* CONFIG_AS_LSE && CONFIG_ARM64_LSE_ATOMICS */ + { + .desc = "Software prefetching using PRFM", + .capability = ARM64_HAS_NO_HW_PREFETCH, + .matches = has_no_hw_prefetch, + }, +#ifdef CONFIG_ARM64_UAO + { + .desc = "User Access Override", + .capability = ARM64_HAS_UAO, + .matches = has_cpuid_feature, + .sys_reg = SYS_ID_AA64MMFR2_EL1, + .field_pos = ID_AA64MMFR2_UAO_SHIFT, + .min_field_value = 1, + .enable = cpu_enable_uao, + }, +#endif /* CONFIG_ARM64_UAO */ +#ifdef CONFIG_ARM64_PAN + { + .capability = ARM64_ALT_PAN_NOT_UAO, + .matches = cpufeature_pan_not_uao, + }, +#endif /* CONFIG_ARM64_PAN */ + { + .desc = "Virtualization Host Extensions", + .capability = ARM64_HAS_VIRT_HOST_EXTN, + .matches = runs_at_el2, + }, +#ifdef CONFIG_UNMAP_KERNEL_AT_EL0 + { + .capability = ARM64_UNMAP_KERNEL_AT_EL0, + .matches = unmap_kernel_at_el0, + }, +#endif {}, }; @@ -686,7 +786,7 @@ {}, }; -static void cap_set_hwcap(const struct arm64_cpu_capabilities *cap) +static void __init cap_set_hwcap(const struct arm64_cpu_capabilities *cap) { switch (cap->hwcap_type) { case CAP_HWCAP: @@ -731,12 +831,12 @@ return rc; } -static void setup_cpu_hwcaps(void) +static void __init setup_cpu_hwcaps(void) { int i; const struct arm64_cpu_capabilities *hwcaps = arm64_hwcaps; - for (i = 0; hwcaps[i].desc; i++) + for (i = 0; hwcaps[i].matches; i++) if (hwcaps[i].matches(&hwcaps[i])) cap_set_hwcap(&hwcaps[i]); } @@ -746,11 +846,11 @@ { int i; - for (i = 0; caps[i].desc; i++) { + for (i = 0; caps[i].matches; i++) { if (!caps[i].matches(&caps[i])) continue; - if (!cpus_have_cap(caps[i].capability)) + if (!cpus_have_cap(caps[i].capability) && caps[i].desc) pr_info("%s %s\n", info, caps[i].desc); cpus_set_cap(caps[i].capability); } @@ -760,11 +860,11 @@ * Run through the enabled capabilities and enable() it on all active * CPUs */ -static void enable_cpu_capabilities(const struct arm64_cpu_capabilities *caps) +void __init enable_cpu_capabilities(const struct arm64_cpu_capabilities *caps) { int i; - for (i = 0; caps[i].desc; i++) + for (i = 0; caps[i].matches; i++) if (caps[i].enable && cpus_have_cap(caps[i].capability)) /* * Use stop_machine() as it schedules the work allowing @@ -772,7 +872,8 @@ * uses an IPI, giving us a PSTATE that disappears when * we return. */ - stop_machine(caps[i].enable, NULL, cpu_online_mask); + stop_machine(caps[i].enable, (void *)&caps[i], + cpu_online_mask); } #ifdef CONFIG_HOTPLUG_CPU @@ -798,35 +899,36 @@ static u64 __raw_read_system_reg(u32 sys_id) { switch (sys_id) { - case SYS_ID_PFR0_EL1: return (u64)read_cpuid(ID_PFR0_EL1); - case SYS_ID_PFR1_EL1: return (u64)read_cpuid(ID_PFR1_EL1); - case SYS_ID_DFR0_EL1: return (u64)read_cpuid(ID_DFR0_EL1); - case SYS_ID_MMFR0_EL1: return (u64)read_cpuid(ID_MMFR0_EL1); - case SYS_ID_MMFR1_EL1: return (u64)read_cpuid(ID_MMFR1_EL1); - case SYS_ID_MMFR2_EL1: return (u64)read_cpuid(ID_MMFR2_EL1); - case SYS_ID_MMFR3_EL1: return (u64)read_cpuid(ID_MMFR3_EL1); - case SYS_ID_ISAR0_EL1: return (u64)read_cpuid(ID_ISAR0_EL1); - case SYS_ID_ISAR1_EL1: return (u64)read_cpuid(ID_ISAR1_EL1); - case SYS_ID_ISAR2_EL1: return (u64)read_cpuid(ID_ISAR2_EL1); - case SYS_ID_ISAR3_EL1: return (u64)read_cpuid(ID_ISAR3_EL1); - case SYS_ID_ISAR4_EL1: return (u64)read_cpuid(ID_ISAR4_EL1); - case SYS_ID_ISAR5_EL1: return (u64)read_cpuid(ID_ISAR4_EL1); - case SYS_MVFR0_EL1: return (u64)read_cpuid(MVFR0_EL1); - case SYS_MVFR1_EL1: return (u64)read_cpuid(MVFR1_EL1); - case SYS_MVFR2_EL1: return (u64)read_cpuid(MVFR2_EL1); - - case SYS_ID_AA64PFR0_EL1: return (u64)read_cpuid(ID_AA64PFR0_EL1); - case SYS_ID_AA64PFR1_EL1: return (u64)read_cpuid(ID_AA64PFR0_EL1); - case SYS_ID_AA64DFR0_EL1: return (u64)read_cpuid(ID_AA64DFR0_EL1); - case SYS_ID_AA64DFR1_EL1: return (u64)read_cpuid(ID_AA64DFR0_EL1); - case SYS_ID_AA64MMFR0_EL1: return (u64)read_cpuid(ID_AA64MMFR0_EL1); - case SYS_ID_AA64MMFR1_EL1: return (u64)read_cpuid(ID_AA64MMFR1_EL1); - case SYS_ID_AA64ISAR0_EL1: return (u64)read_cpuid(ID_AA64ISAR0_EL1); - case SYS_ID_AA64ISAR1_EL1: return (u64)read_cpuid(ID_AA64ISAR1_EL1); - - case SYS_CNTFRQ_EL0: return (u64)read_cpuid(CNTFRQ_EL0); - case SYS_CTR_EL0: return (u64)read_cpuid(CTR_EL0); - case SYS_DCZID_EL0: return (u64)read_cpuid(DCZID_EL0); + case SYS_ID_PFR0_EL1: return read_cpuid(SYS_ID_PFR0_EL1); + case SYS_ID_PFR1_EL1: return read_cpuid(SYS_ID_PFR1_EL1); + case SYS_ID_DFR0_EL1: return read_cpuid(SYS_ID_DFR0_EL1); + case SYS_ID_MMFR0_EL1: return read_cpuid(SYS_ID_MMFR0_EL1); + case SYS_ID_MMFR1_EL1: return read_cpuid(SYS_ID_MMFR1_EL1); + case SYS_ID_MMFR2_EL1: return read_cpuid(SYS_ID_MMFR2_EL1); + case SYS_ID_MMFR3_EL1: return read_cpuid(SYS_ID_MMFR3_EL1); + case SYS_ID_ISAR0_EL1: return read_cpuid(SYS_ID_ISAR0_EL1); + case SYS_ID_ISAR1_EL1: return read_cpuid(SYS_ID_ISAR1_EL1); + case SYS_ID_ISAR2_EL1: return read_cpuid(SYS_ID_ISAR2_EL1); + case SYS_ID_ISAR3_EL1: return read_cpuid(SYS_ID_ISAR3_EL1); + case SYS_ID_ISAR4_EL1: return read_cpuid(SYS_ID_ISAR4_EL1); + case SYS_ID_ISAR5_EL1: return read_cpuid(SYS_ID_ISAR4_EL1); + case SYS_MVFR0_EL1: return read_cpuid(SYS_MVFR0_EL1); + case SYS_MVFR1_EL1: return read_cpuid(SYS_MVFR1_EL1); + case SYS_MVFR2_EL1: return read_cpuid(SYS_MVFR2_EL1); + + case SYS_ID_AA64PFR0_EL1: return read_cpuid(SYS_ID_AA64PFR0_EL1); + case SYS_ID_AA64PFR1_EL1: return read_cpuid(SYS_ID_AA64PFR0_EL1); + case SYS_ID_AA64DFR0_EL1: return read_cpuid(SYS_ID_AA64DFR0_EL1); + case SYS_ID_AA64DFR1_EL1: return read_cpuid(SYS_ID_AA64DFR0_EL1); + case SYS_ID_AA64MMFR0_EL1: return read_cpuid(SYS_ID_AA64MMFR0_EL1); + case SYS_ID_AA64MMFR1_EL1: return read_cpuid(SYS_ID_AA64MMFR1_EL1); + case SYS_ID_AA64MMFR2_EL1: return read_cpuid(SYS_ID_AA64MMFR2_EL1); + case SYS_ID_AA64ISAR0_EL1: return read_cpuid(SYS_ID_AA64ISAR0_EL1); + case SYS_ID_AA64ISAR1_EL1: return read_cpuid(SYS_ID_AA64ISAR1_EL1); + + case SYS_CNTFRQ_EL0: return read_cpuid(SYS_CNTFRQ_EL0); + case SYS_CTR_EL0: return read_cpuid(SYS_CTR_EL0); + case SYS_DCZID_EL0: return read_cpuid(SYS_DCZID_EL0); default: BUG(); return 0; @@ -876,7 +978,7 @@ return; caps = arm64_features; - for (i = 0; caps[i].desc; i++) { + for (i = 0; caps[i].matches; i++) { if (!cpus_have_cap(caps[i].capability) || !caps[i].sys_reg) continue; /* @@ -886,10 +988,10 @@ if (!feature_matches(__raw_read_system_reg(caps[i].sys_reg), &caps[i])) fail_incapable_cpu("arm64_features", &caps[i]); if (caps[i].enable) - caps[i].enable(NULL); + caps[i].enable((void *)&caps[i]); } - for (i = 0, caps = arm64_hwcaps; caps[i].desc; i++) { + for (i = 0, caps = arm64_hwcaps; caps[i].matches; i++) { if (!cpus_have_hwcap(&caps[i])) continue; if (!feature_matches(__raw_read_system_reg(caps[i].sys_reg), &caps[i])) @@ -905,7 +1007,7 @@ #endif /* CONFIG_HOTPLUG_CPU */ -static void setup_feature_capabilities(void) +static void __init setup_feature_capabilities(void) { update_cpu_capabilities(arm64_features, "detected feature:"); enable_cpu_capabilities(arm64_features); @@ -918,6 +1020,7 @@ /* Set the CPU feature capabilies */ setup_feature_capabilities(); + enable_errata_workarounds(); setup_cpu_hwcaps(); /* Advertise that we have computed the system capabilities */ @@ -931,7 +1034,13 @@ if (!cwg) pr_warn("No Cache Writeback Granule information, assuming cache line size %d\n", cls); - if (L1_CACHE_BYTES < cls) - pr_warn("L1_CACHE_BYTES smaller than the Cache Writeback Granule (%d < %d)\n", - L1_CACHE_BYTES, cls); + if (ARCH_DMA_MINALIGN < cls) + pr_warn("ARCH_DMA_MINALIGN smaller than the Cache Writeback Granule (%d < %d)\n", + ARCH_DMA_MINALIGN, cls); +} + +static bool __maybe_unused +cpufeature_pan_not_uao(const struct arm64_cpu_capabilities *entry) +{ + return (cpus_have_cap(ARM64_HAS_PAN) && !cpus_have_cap(ARM64_HAS_UAO)); } diff -ruw linux-4.4.115/arch/arm64/kernel/cpuinfo.c linux-4.4.115-fbx/arch/arm64/kernel/cpuinfo.c --- linux-4.4.115/arch/arm64/kernel/cpuinfo.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/arch/arm64/kernel/cpuinfo.c 2019-01-22 16:16:21.547228694 +0100 @@ -19,6 +19,7 @@ #include #include #include +#include #include #include @@ -33,6 +34,10 @@ #include #include #include +#include + +char* (*arch_read_hardware_id)(void); +EXPORT_SYMBOL(arch_read_hardware_id); /* * In case the boot CPU is hotpluggable, we record its initial state and @@ -106,7 +111,9 @@ int i, j; bool compat = personality(current->personality) == PER_LINUX32; - for_each_online_cpu(i) { + seq_printf(m, "Processor\t: AArch64 Processor rev %d (%s)\n", + read_cpuid_id() & 15, ELF_PLATFORM); + for_each_present_cpu(i) { struct cpuinfo_arm64 *cpuinfo = &per_cpu(cpu_data, i); u32 midr = cpuinfo->reg_midr; @@ -156,6 +163,11 @@ seq_printf(m, "CPU revision\t: %d\n\n", MIDR_REVISION(midr)); } + if (!arch_read_hardware_id) + seq_printf(m, "Hardware\t: %s\n", machine_name); + else + seq_printf(m, "Hardware\t: %s\n", arch_read_hardware_id()); + return 0; } @@ -201,42 +213,48 @@ if (l1ip == ICACHE_POLICY_AIVIVT) set_bit(ICACHEF_AIVIVT, &__icache_flags); - pr_info("Detected %s I-cache on CPU%d\n", icache_policy_str[l1ip], cpu); + pr_debug("Detected %s I-cache on CPU%d\n", icache_policy_str[l1ip], cpu); } static void __cpuinfo_store_cpu(struct cpuinfo_arm64 *info) { info->reg_cntfrq = arch_timer_get_cntfrq(); info->reg_ctr = read_cpuid_cachetype(); - info->reg_dczid = read_cpuid(DCZID_EL0); + info->reg_dczid = read_cpuid(SYS_DCZID_EL0); info->reg_midr = read_cpuid_id(); - info->reg_id_aa64dfr0 = read_cpuid(ID_AA64DFR0_EL1); - info->reg_id_aa64dfr1 = read_cpuid(ID_AA64DFR1_EL1); - info->reg_id_aa64isar0 = read_cpuid(ID_AA64ISAR0_EL1); - info->reg_id_aa64isar1 = read_cpuid(ID_AA64ISAR1_EL1); - info->reg_id_aa64mmfr0 = read_cpuid(ID_AA64MMFR0_EL1); - info->reg_id_aa64mmfr1 = read_cpuid(ID_AA64MMFR1_EL1); - info->reg_id_aa64pfr0 = read_cpuid(ID_AA64PFR0_EL1); - info->reg_id_aa64pfr1 = read_cpuid(ID_AA64PFR1_EL1); - - info->reg_id_dfr0 = read_cpuid(ID_DFR0_EL1); - info->reg_id_isar0 = read_cpuid(ID_ISAR0_EL1); - info->reg_id_isar1 = read_cpuid(ID_ISAR1_EL1); - info->reg_id_isar2 = read_cpuid(ID_ISAR2_EL1); - info->reg_id_isar3 = read_cpuid(ID_ISAR3_EL1); - info->reg_id_isar4 = read_cpuid(ID_ISAR4_EL1); - info->reg_id_isar5 = read_cpuid(ID_ISAR5_EL1); - info->reg_id_mmfr0 = read_cpuid(ID_MMFR0_EL1); - info->reg_id_mmfr1 = read_cpuid(ID_MMFR1_EL1); - info->reg_id_mmfr2 = read_cpuid(ID_MMFR2_EL1); - info->reg_id_mmfr3 = read_cpuid(ID_MMFR3_EL1); - info->reg_id_pfr0 = read_cpuid(ID_PFR0_EL1); - info->reg_id_pfr1 = read_cpuid(ID_PFR1_EL1); - - info->reg_mvfr0 = read_cpuid(MVFR0_EL1); - info->reg_mvfr1 = read_cpuid(MVFR1_EL1); - info->reg_mvfr2 = read_cpuid(MVFR2_EL1); + info->reg_id_aa64dfr0 = read_cpuid(SYS_ID_AA64DFR0_EL1); + info->reg_id_aa64dfr1 = read_cpuid(SYS_ID_AA64DFR1_EL1); + info->reg_id_aa64isar0 = read_cpuid(SYS_ID_AA64ISAR0_EL1); + info->reg_id_aa64isar1 = read_cpuid(SYS_ID_AA64ISAR1_EL1); + /* + * Explicitly mask out 16KB granule since we donot + * want to support it + */ + info->reg_id_aa64mmfr0 = read_cpuid(SYS_ID_AA64MMFR0_EL1) & + (~MMFR0_EL1_16KGRAN_MASK); + info->reg_id_aa64mmfr1 = read_cpuid(SYS_ID_AA64MMFR1_EL1); + info->reg_id_aa64mmfr2 = read_cpuid(SYS_ID_AA64MMFR2_EL1); + info->reg_id_aa64pfr0 = read_cpuid(SYS_ID_AA64PFR0_EL1); + info->reg_id_aa64pfr1 = read_cpuid(SYS_ID_AA64PFR1_EL1); + + info->reg_id_dfr0 = read_cpuid(SYS_ID_DFR0_EL1); + info->reg_id_isar0 = read_cpuid(SYS_ID_ISAR0_EL1); + info->reg_id_isar1 = read_cpuid(SYS_ID_ISAR1_EL1); + info->reg_id_isar2 = read_cpuid(SYS_ID_ISAR2_EL1); + info->reg_id_isar3 = read_cpuid(SYS_ID_ISAR3_EL1); + info->reg_id_isar4 = read_cpuid(SYS_ID_ISAR4_EL1); + info->reg_id_isar5 = read_cpuid(SYS_ID_ISAR5_EL1); + info->reg_id_mmfr0 = read_cpuid(SYS_ID_MMFR0_EL1); + info->reg_id_mmfr1 = read_cpuid(SYS_ID_MMFR1_EL1); + info->reg_id_mmfr2 = read_cpuid(SYS_ID_MMFR2_EL1); + info->reg_id_mmfr3 = read_cpuid(SYS_ID_MMFR3_EL1); + info->reg_id_pfr0 = read_cpuid(SYS_ID_PFR0_EL1); + info->reg_id_pfr1 = read_cpuid(SYS_ID_PFR1_EL1); + + info->reg_mvfr0 = read_cpuid(SYS_MVFR0_EL1); + info->reg_mvfr1 = read_cpuid(SYS_MVFR1_EL1); + info->reg_mvfr2 = read_cpuid(SYS_MVFR2_EL1); cpuinfo_detect_icache_policy(info); diff -ruw linux-4.4.115/arch/arm64/kernel/cpu_ops.c linux-4.4.115-fbx/arch/arm64/kernel/cpu_ops.c --- linux-4.4.115/arch/arm64/kernel/cpu_ops.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/arch/arm64/kernel/cpu_ops.c 2019-10-29 09:26:23.001196895 +0100 @@ -25,19 +25,30 @@ #include extern const struct cpu_operations smp_spin_table_ops; +extern const struct cpu_operations acpi_parking_protocol_ops; extern const struct cpu_operations cpu_psci_ops; const struct cpu_operations *cpu_ops[NR_CPUS]; -static const struct cpu_operations *supported_cpu_ops[] __initconst = { +static const struct cpu_operations *dt_supported_cpu_ops[] __initconst = { &smp_spin_table_ops, &cpu_psci_ops, NULL, }; +static const struct cpu_operations *acpi_supported_cpu_ops[] __initconst = { +#ifdef CONFIG_ARM64_ACPI_PARKING_PROTOCOL + &acpi_parking_protocol_ops, +#endif + &cpu_psci_ops, + NULL, +}; + static const struct cpu_operations * __init cpu_get_ops(const char *name) { - const struct cpu_operations **ops = supported_cpu_ops; + const struct cpu_operations **ops; + + ops = acpi_disabled ? dt_supported_cpu_ops : acpi_supported_cpu_ops; while (*ops) { if (!strcmp(name, (*ops)->name)) @@ -75,9 +86,17 @@ } } else { enable_method = acpi_get_enable_method(cpu); - if (!enable_method) + if (!enable_method) { + /* + * In ACPI systems the boot CPU does not require + * checking the enable method since for some + * boot protocol (ie parking protocol) it need not + * be initialized. Don't warn spuriously. + */ + if (cpu != 0) pr_err("Unsupported ACPI enable-method\n"); } + } return enable_method; } diff -ruw linux-4.4.115/arch/arm64/kernel/debug-monitors.c linux-4.4.115-fbx/arch/arm64/kernel/debug-monitors.c --- linux-4.4.115/arch/arm64/kernel/debug-monitors.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/arch/arm64/kernel/debug-monitors.c 2019-01-22 16:16:21.547228694 +0100 @@ -23,6 +23,7 @@ #include #include #include +#include #include #include @@ -48,6 +49,7 @@ asm volatile("msr mdscr_el1, %0" :: "r" (mdscr)); local_dbg_restore(flags); } +NOKPROBE_SYMBOL(mdscr_write); static u32 mdscr_read(void) { @@ -55,6 +57,7 @@ asm volatile("mrs %0, mdscr_el1" : "=r" (mdscr)); return mdscr; } +NOKPROBE_SYMBOL(mdscr_read); /* * Allow root to disable self-hosted debug from userspace. @@ -103,6 +106,7 @@ mdscr_write(mdscr); } } +NOKPROBE_SYMBOL(enable_debug_monitors); void disable_debug_monitors(enum dbg_active_el el) { @@ -123,6 +127,7 @@ mdscr_write(mdscr); } } +NOKPROBE_SYMBOL(disable_debug_monitors); /* * OS lock clearing. @@ -173,6 +178,7 @@ spsr |= DBG_SPSR_SS; regs->pstate = spsr; } +NOKPROBE_SYMBOL(set_regs_spsr_ss); static void clear_regs_spsr_ss(struct pt_regs *regs) { @@ -182,6 +188,7 @@ spsr &= ~DBG_SPSR_SS; regs->pstate = spsr; } +NOKPROBE_SYMBOL(clear_regs_spsr_ss); /* EL1 Single Step Handler hooks */ static LIST_HEAD(step_hook); @@ -225,6 +232,7 @@ return retval; } +NOKPROBE_SYMBOL(call_step_hook); static int single_step_handler(unsigned long addr, unsigned int esr, struct pt_regs *regs) @@ -253,6 +261,10 @@ */ user_rewind_single_step(current); } else { +#ifdef CONFIG_KPROBES + if (kprobe_single_step_handler(regs, esr) == DBG_HOOK_HANDLED) + return 0; +#endif if (call_step_hook(regs, esr) == DBG_HOOK_HANDLED) return 0; @@ -266,6 +278,7 @@ return 0; } +NOKPROBE_SYMBOL(single_step_handler); /* * Breakpoint handler is re-entrant as another breakpoint can @@ -303,6 +316,7 @@ return fn ? fn(regs, esr) : DBG_HOOK_ERROR; } +NOKPROBE_SYMBOL(call_break_hook); static int brk_handler(unsigned long addr, unsigned int esr, struct pt_regs *regs) @@ -318,13 +332,21 @@ }; force_sig_info(SIGTRAP, &info, current); - } else if (call_break_hook(regs, esr) != DBG_HOOK_HANDLED) { - pr_warning("Unexpected kernel BRK exception at EL1\n"); + } +#ifdef CONFIG_KPROBES + else if ((esr & BRK64_ESR_MASK) == BRK64_ESR_KPROBES) { + if (kprobe_breakpoint_handler(regs, esr) != DBG_HOOK_HANDLED) + return -EFAULT; + } +#endif + else if (call_break_hook(regs, esr) != DBG_HOOK_HANDLED) { + pr_warn("Unexpected kernel BRK exception at EL1\n"); return -EFAULT; } return 0; } +NOKPROBE_SYMBOL(brk_handler); int aarch32_break_handler(struct pt_regs *regs) { @@ -369,6 +391,7 @@ force_sig_info(SIGTRAP, &info, current); return 0; } +NOKPROBE_SYMBOL(aarch32_break_handler); static int __init debug_traps_init(void) { @@ -390,6 +413,7 @@ if (test_ti_thread_flag(task_thread_info(task), TIF_SINGLESTEP)) set_regs_spsr_ss(task_pt_regs(task)); } +NOKPROBE_SYMBOL(user_rewind_single_step); void user_fastforward_single_step(struct task_struct *task) { @@ -405,6 +429,7 @@ mdscr_write(mdscr_read() | DBG_MDSCR_SS); enable_debug_monitors(DBG_ACTIVE_EL1); } +NOKPROBE_SYMBOL(kernel_enable_single_step); void kernel_disable_single_step(void) { @@ -412,12 +437,14 @@ mdscr_write(mdscr_read() & ~DBG_MDSCR_SS); disable_debug_monitors(DBG_ACTIVE_EL1); } +NOKPROBE_SYMBOL(kernel_disable_single_step); int kernel_active_single_step(void) { WARN_ON(!irqs_disabled()); return mdscr_read() & DBG_MDSCR_SS; } +NOKPROBE_SYMBOL(kernel_active_single_step); /* ptrace API */ void user_enable_single_step(struct task_struct *task) @@ -427,8 +454,10 @@ if (!test_and_set_ti_thread_flag(ti, TIF_SINGLESTEP)) set_regs_spsr_ss(task_pt_regs(task)); } +NOKPROBE_SYMBOL(user_enable_single_step); void user_disable_single_step(struct task_struct *task) { clear_ti_thread_flag(task_thread_info(task), TIF_SINGLESTEP); } +NOKPROBE_SYMBOL(user_disable_single_step); diff -ruw linux-4.4.115/arch/arm64/kernel/entry-fpsimd.S linux-4.4.115-fbx/arch/arm64/kernel/entry-fpsimd.S --- linux-4.4.115/arch/arm64/kernel/entry-fpsimd.S 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/arch/arm64/kernel/entry-fpsimd.S 2019-01-22 16:16:21.547228694 +0100 @@ -64,4 +64,20 @@ ret ENDPROC(fpsimd_load_partial_state) +#ifdef CONFIG_ENABLE_FP_SIMD_SETTINGS +ENTRY(fpsimd_enable_trap) + mrs x0, cpacr_el1 + bic x0, x0, #(3 << 20) + orr x0, x0, #(1 << 20) + msr cpacr_el1, x0 + ret +ENDPROC(fpsimd_enable_trap) +ENTRY(fpsimd_disable_trap) + mrs x0, cpacr_el1 + orr x0, x0, #(3 << 20) + msr cpacr_el1, x0 + ret +ENDPROC(fpsimd_disable_trap) +#endif + #endif diff -ruw linux-4.4.115/arch/arm64/kernel/entry.S linux-4.4.115-fbx/arch/arm64/kernel/entry.S --- linux-4.4.115/arch/arm64/kernel/entry.S 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/arch/arm64/kernel/entry.S 2019-01-22 16:16:21.547228694 +0100 @@ -27,8 +27,12 @@ #include #include #include +#include #include +#include +#include #include +#include #include #include @@ -67,8 +71,31 @@ #define BAD_FIQ 2 #define BAD_ERROR 3 - .macro kernel_entry, el, regsize = 64 + .macro kernel_ventry, el, label, regsize = 64 + .align 7 +#ifdef CONFIG_UNMAP_KERNEL_AT_EL0 +alternative_if ARM64_UNMAP_KERNEL_AT_EL0 + .if \el == 0 + .if \regsize == 64 + mrs x30, tpidrro_el0 + msr tpidrro_el0, xzr + .else + mov x30, xzr + .endif + .endif +alternative_else_nop_endif +#endif + sub sp, sp, #S_FRAME_SIZE + b el\()\el\()_\label + .endm + + .macro tramp_alias, dst, sym + mov_q \dst, TRAMP_VALIAS + add \dst, \dst, #(\sym - .entry.tramp.text) + .endm + + .macro kernel_entry, el, regsize = 64 .if \regsize == 32 mov w0, w0 // zero upper 32 bits of x0 .endif @@ -90,21 +117,64 @@ .if \el == 0 mrs x21, sp_el0 - get_thread_info tsk // Ensure MDSCR_EL1.SS is clear, +#ifdef CONFIG_THREAD_INFO_IN_TASK + ldr_this_cpu tsk, __entry_task, x20 // Ensure MDSCR_EL1.SS is clear, + ldr x19, [tsk, #TSK_TI_FLAGS] // since we can unmask debug +#else + mov tsk, sp + and tsk, tsk, #~(THREAD_SIZE - 1) // Ensure MDSCR_EL1.SS is clear, ldr x19, [tsk, #TI_FLAGS] // since we can unmask debug +#endif disable_step_tsk x19, x20 // exceptions when scheduling. + + mov x29, xzr // fp pointed to user-space .else add x21, sp, #S_FRAME_SIZE get_thread_info tsk /* Save the task's original addr_limit and set USER_DS (TASK_SIZE_64) */ +#ifdef CONFIG_THREAD_INFO_IN_TASK + ldr x20, [tsk, #TSK_TI_ADDR_LIMIT] +#else ldr x20, [tsk, #TI_ADDR_LIMIT] +#endif str x20, [sp, #S_ORIG_ADDR_LIMIT] mov x20, #TASK_SIZE_64 +#ifdef CONFIG_THREAD_INFO_IN_TASK + str x20, [tsk, #TSK_TI_ADDR_LIMIT] +#else str x20, [tsk, #TI_ADDR_LIMIT] +#endif + ALTERNATIVE(nop, SET_PSTATE_UAO(0), ARM64_HAS_UAO, CONFIG_ARM64_UAO) .endif /* \el == 0 */ mrs x22, elr_el1 mrs x23, spsr_el1 stp lr, x21, [sp, #S_LR] + +#ifdef CONFIG_ARM64_SW_TTBR0_PAN + /* + * Set the TTBR0 PAN bit in SPSR. When the exception is taken from + * EL0, there is no need to check the state of TTBR0_EL1 since + * accesses are always enabled. + * Note that the meaning of this bit differs from the ARMv8.1 PAN + * feature as all TTBR0_EL1 accesses are disabled, not just those to + * user mappings. + */ +alternative_if ARM64_HAS_PAN + b 1f // skip TTBR0 PAN +alternative_else_nop_endif + + .if \el != 0 + mrs x21, ttbr0_el1 + tst x21, #TTBR_ASID_MASK // Check for the reserved ASID + orr x23, x23, #PSR_PAN_BIT // Set the emulated PAN in the saved SPSR + b.eq 1f // TTBR0 access already disabled + and x23, x23, #~PSR_PAN_BIT // Clear the emulated PAN in the saved SPSR + .endif + + __uaccess_ttbr0_disable x21 +1: +#endif + stp x22, x23, [sp, #S_PC] /* @@ -116,6 +186,13 @@ .endif /* + * Set sp_el0 to current thread_info. + */ + .if \el == 0 + msr sp_el0, tsk + .endif + + /* * Registers that may be useful after this macro is invoked: * * x21 - aborted SP @@ -128,33 +205,70 @@ .if \el != 0 /* Restore the task's original addr_limit. */ ldr x20, [sp, #S_ORIG_ADDR_LIMIT] +#ifdef CONFIG_THREAD_INFO_IN_TASK + str x20, [tsk, #TSK_TI_ADDR_LIMIT] +#else str x20, [tsk, #TI_ADDR_LIMIT] +#endif + + /* No need to restore UAO, it will be restored from SPSR_EL1 */ .endif ldp x21, x22, [sp, #S_PC] // load ELR, SPSR .if \el == 0 ct_user_enter + .endif + +#ifdef CONFIG_ARM64_SW_TTBR0_PAN + /* + * Restore access to TTBR0_EL1. If returning to EL0, no need for SPSR + * PAN bit checking. + */ +alternative_if ARM64_HAS_PAN + b 2f // skip TTBR0 PAN +alternative_else_nop_endif + + .if \el != 0 + tbnz x22, #22, 1f // Skip re-enabling TTBR0 access if the PSR_PAN_BIT is set + .endif + + __uaccess_ttbr0_enable x0, x1 + + .if \el == 0 + /* + * Enable errata workarounds only if returning to user. The only + * workaround currently required for TTBR0_EL1 changes are for the + * Cavium erratum 27456 (broadcast TLBI instructions may cause I-cache + * corruption). + */ + bl post_ttbr_update_workaround + .endif +1: + .if \el != 0 + and x22, x22, #~PSR_PAN_BIT // ARMv8.0 CPUs do not understand this bit + .endif +2: +#endif + + .if \el == 0 ldr x23, [sp, #S_SP] // load return stack pointer msr sp_el0, x23 + tst x22, #PSR_MODE32_BIT // native task? + b.eq 3f + #ifdef CONFIG_ARM64_ERRATUM_845719 -alternative_if_not ARM64_WORKAROUND_845719 - nop - nop -#ifdef CONFIG_PID_IN_CONTEXTIDR - nop -#endif -alternative_else - tbz x22, #4, 1f +alternative_if ARM64_WORKAROUND_845719 #ifdef CONFIG_PID_IN_CONTEXTIDR mrs x29, contextidr_el1 msr contextidr_el1, x29 #else msr contextidr_el1, xzr #endif -1: -alternative_endif +alternative_else_nop_endif #endif +3: .endif + msr elr_el1, x21 // set up the return data msr spsr_el1, x22 ldp x0, x1, [sp, #16 * 0] @@ -174,12 +288,65 @@ ldp x28, x29, [sp, #16 * 14] ldr lr, [sp, #S_LR] add sp, sp, #S_FRAME_SIZE // restore sp - eret // return to kernel + + .if \el == 0 +alternative_insn eret, nop, ARM64_UNMAP_KERNEL_AT_EL0 +#ifdef CONFIG_UNMAP_KERNEL_AT_EL0 + bne 4f + msr far_el1, x30 + tramp_alias x30, tramp_exit_native + br x30 +4: + tramp_alias x30, tramp_exit_compat + br x30 +#endif + .else + eret + .endif .endm - .macro get_thread_info, rd - mov \rd, sp - and \rd, \rd, #~(THREAD_SIZE - 1) // top of stack + .macro irq_stack_entry + mov x19, sp // preserve the original sp + + /* + * Compare sp with the base of the task stack. + * If the top ~(THREAD_SIZE - 1) bits match, we are on a task stack, + * and should switch to the irq stack. + */ +#ifdef CONFIG_THREAD_INFO_IN_TASK + ldr x25, [tsk, TSK_STACK] + eor x25, x25, x19 + and x25, x25, #~(THREAD_SIZE - 1) + cbnz x25, 9998f +#else + and x25, x19, #~(THREAD_SIZE - 1) + cmp x25, tsk + b.ne 9998f +#endif + + adr_this_cpu x25, irq_stack, x26 + mov x26, #IRQ_STACK_START_SP + add x26, x25, x26 + + /* switch to the irq stack */ + mov sp, x26 + + /* + * Add a dummy stack frame, this non-standard format is fixed up + * by unwind_frame() + */ + stp x29, x19, [sp, #-16]! + mov x29, sp + +9998: + .endm + + /* + * x19 should be preserved between irq_stack_entry and + * irq_stack_exit. + */ + .macro irq_stack_exit + mov sp, x19 .endm /* @@ -197,10 +364,11 @@ * Interrupt handling. */ .macro irq_handler - adrp x1, handle_arch_irq - ldr x1, [x1, #:lo12:handle_arch_irq] + ldr_l x1, handle_arch_irq mov x0, sp + irq_stack_entry blr x1 + irq_stack_exit .endm .text @@ -208,34 +376,35 @@ /* * Exception vectors. */ + .pushsection ".entry.text", "ax" .align 11 ENTRY(vectors) - ventry el1_sync_invalid // Synchronous EL1t - ventry el1_irq_invalid // IRQ EL1t - ventry el1_fiq_invalid // FIQ EL1t - ventry el1_error_invalid // Error EL1t - - ventry el1_sync // Synchronous EL1h - ventry el1_irq // IRQ EL1h - ventry el1_fiq_invalid // FIQ EL1h - ventry el1_error_invalid // Error EL1h - - ventry el0_sync // Synchronous 64-bit EL0 - ventry el0_irq // IRQ 64-bit EL0 - ventry el0_fiq_invalid // FIQ 64-bit EL0 - ventry el0_error_invalid // Error 64-bit EL0 + kernel_ventry 1, sync_invalid // Synchronous EL1t + kernel_ventry 1, irq_invalid // IRQ EL1t + kernel_ventry 1, fiq_invalid // FIQ EL1t + kernel_ventry 1, error_invalid // Error EL1t + + kernel_ventry 1, sync // Synchronous EL1h + kernel_ventry 1, irq // IRQ EL1h + kernel_ventry 1, fiq_invalid // FIQ EL1h + kernel_ventry 1, error_invalid // Error EL1h + + kernel_ventry 0, sync // Synchronous 64-bit EL0 + kernel_ventry 0, irq // IRQ 64-bit EL0 + kernel_ventry 0, fiq_invalid // FIQ 64-bit EL0 + kernel_ventry 0, error_invalid // Error 64-bit EL0 #ifdef CONFIG_COMPAT - ventry el0_sync_compat // Synchronous 32-bit EL0 - ventry el0_irq_compat // IRQ 32-bit EL0 - ventry el0_fiq_invalid_compat // FIQ 32-bit EL0 - ventry el0_error_invalid_compat // Error 32-bit EL0 -#else - ventry el0_sync_invalid // Synchronous 32-bit EL0 - ventry el0_irq_invalid // IRQ 32-bit EL0 - ventry el0_fiq_invalid // FIQ 32-bit EL0 - ventry el0_error_invalid // Error 32-bit EL0 + kernel_ventry 0, sync_compat, 32 // Synchronous 32-bit EL0 + kernel_ventry 0, irq_compat, 32 // IRQ 32-bit EL0 + kernel_ventry 0, fiq_invalid_compat, 32 // FIQ 32-bit EL0 + kernel_ventry 0, error_invalid_compat, 32 // Error 32-bit EL0 +#else + kernel_ventry 0, sync_invalid, 32 // Synchronous 32-bit EL0 + kernel_ventry 0, irq_invalid, 32 // IRQ 32-bit EL0 + kernel_ventry 0, fiq_invalid, 32 // FIQ 32-bit EL0 + kernel_ventry 0, error_invalid, 32 // Error 32-bit EL0 #endif END(vectors) @@ -243,7 +412,7 @@ * Invalid mode handlers */ .macro inv_entry, el, reason, regsize = 64 - kernel_entry el, \regsize + kernel_entry \el, \regsize mov x0, sp mov x1, #\reason mrs x2, esr_el1 @@ -297,11 +466,16 @@ */ .align 6 el1_sync: +#ifdef CONFIG_QCOM_TLB_EL2_HANDLER + smc #0xffff +#endif kernel_entry 1 mrs x1, esr_el1 // read the syndrome register lsr x24, x1, #ESR_ELx_EC_SHIFT // exception class cmp x24, #ESR_ELx_EC_DABT_CUR // data abort in EL1 b.eq el1_da + cmp x24, #ESR_ELx_EC_IABT_CUR // instruction abort in EL1 + b.eq el1_ia cmp x24, #ESR_ELx_EC_SYS64 // configurable trap b.eq el1_undef cmp x24, #ESR_ELx_EC_SP_ALIGN // stack alignment exception @@ -313,6 +487,11 @@ cmp x24, #ESR_ELx_EC_BREAKPT_CUR // debug exception in EL1 b.ge el1_dbg b el1_inv + +el1_ia: + /* + * Fall through to the Data abort case + */ el1_da: /* * Data abort handling @@ -373,13 +552,21 @@ bl trace_hardirqs_off #endif + get_thread_info tsk irq_handler #ifdef CONFIG_PREEMPT - get_thread_info tsk +#ifdef CONFIG_THREAD_INFO_IN_TASK + ldr w24, [tsk, #TSK_TI_PREEMPT] // get preempt count +#else ldr w24, [tsk, #TI_PREEMPT] // get preempt count +#endif cbnz w24, 1f // preempt count != 0 +#ifdef CONFIG_THREAD_INFO_IN_TASK + ldr x0, [tsk, #TSK_TI_FLAGS] // get flags +#else ldr x0, [tsk, #TI_FLAGS] // get flags +#endif tbz x0, #TIF_NEED_RESCHED, 1f // needs rescheduling? bl el1_preempt 1: @@ -394,7 +581,11 @@ el1_preempt: mov x24, lr 1: bl preempt_schedule_irq // irq en/disable is done inside +#ifdef CONFIG_THREAD_INFO_IN_TASK + ldr x0, [tsk, #TSK_TI_FLAGS] // get new tasks TI_FLAGS +#else ldr x0, [tsk, #TI_FLAGS] // get new tasks TI_FLAGS +#endif tbnz x0, #TIF_NEED_RESCHED, 1b // needs rescheduling? ret x24 #endif @@ -418,7 +609,7 @@ cmp x24, #ESR_ELx_EC_FP_EXC64 // FP/ASIMD exception b.eq el0_fpsimd_exc cmp x24, #ESR_ELx_EC_SYS64 // configurable trap - b.eq el0_undef + b.eq el0_sys cmp x24, #ESR_ELx_EC_SP_ALIGN // stack alignment exception b.eq el0_sp_pc cmp x24, #ESR_ELx_EC_PC_ALIGN // pc alignment exception @@ -442,7 +633,7 @@ cmp x24, #ESR_ELx_EC_IABT_LOW // instruction abort in EL0 b.eq el0_ia cmp x24, #ESR_ELx_EC_FP_ASIMD // FP/ASIMD access - b.eq el0_fpsimd_acc + b.eq el0_fpsimd_acc_compat cmp x24, #ESR_ELx_EC_FP_EXC32 // FP/ASIMD exception b.eq el0_fpsimd_exc cmp x24, #ESR_ELx_EC_PC_ALIGN // pc alignment exception @@ -495,13 +686,15 @@ * Instruction abort handling */ mrs x26, far_el1 - // enable interrupts before calling the main handler - enable_dbg_and_irq + enable_dbg +#ifdef CONFIG_TRACE_IRQFLAGS + bl trace_hardirqs_off +#endif ct_user_exit mov x0, x26 - orr x1, x25, #1 << 24 // use reserved ISS bit for instruction aborts + mov x1, x25 mov x2, sp - bl do_mem_abort + bl do_el0_ia_bp_hardening b ret_to_user el0_fpsimd_acc: /* @@ -513,6 +706,17 @@ mov x1, sp bl do_fpsimd_acc b ret_to_user +el0_fpsimd_acc_compat: + /* + * Floating Point or Advanced SIMD access + */ + enable_dbg + ct_user_exit + mov x0, x25 + mov x1, sp + bl do_fpsimd_acc_compat + b ret_to_user + el0_fpsimd_exc: /* * Floating Point or Advanced SIMD exception @@ -546,6 +750,16 @@ mov x0, sp bl do_undefinstr b ret_to_user +el0_sys: + /* + * System instructions, for trapped cache maintenance instructions + */ + enable_dbg_and_irq + ct_user_exit + mov x0, x25 + mov x1, sp + bl do_sysinstr + b ret_to_user el0_dbg: /* * Debug exception handling @@ -613,7 +827,40 @@ ldp x27, x28, [x8], #16 ldp x29, x9, [x8], #16 ldr lr, [x8] +#ifdef CONFIG_ARM64_REG_REBALANCE_ON_CTX_SW + orr x13, x13, x13 + orr x14, x14, x14 + orr x15, x15, x15 + orr x16, x16, x16 + orr x17, x17, x17 + orr x18, x18, x18 + orr x19, x19, x19 + orr x20, x20, x20 + orr x21, x21, x21 + mov v0.16b, v0.16b + mov v1.16b, v1.16b + mov v2.16b, v2.16b + mov v3.16b, v3.16b + mov v4.16b, v4.16b + mov v5.16b, v5.16b + mov v6.16b, v6.16b + mov v7.16b, v7.16b + mov v8.16b, v8.16b + mov v9.16b, v9.16b + mov v10.16b, v10.16b + mov v11.16b, v11.16b + mov v12.16b, v12.16b + mov v13.16b, v13.16b + mov v14.16b, v14.16b + mov v15.16b, v15.16b +#endif mov sp, x9 +#ifdef CONFIG_THREAD_INFO_IN_TASK + msr sp_el0, x1 +#else + and x9, x9, #~(THREAD_SIZE - 1) + msr sp_el0, x9 +#endif ret ENDPROC(cpu_switch_to) @@ -624,7 +871,11 @@ ret_fast_syscall: disable_irq // disable interrupts str x0, [sp, #S_X0] // returned x0 +#ifdef CONFIG_THREAD_INFO_IN_TASK + ldr x1, [tsk, #TSK_TI_FLAGS] // re-check for syscall tracing +#else ldr x1, [tsk, #TI_FLAGS] // re-check for syscall tracing +#endif and x2, x1, #_TIF_SYSCALL_WORK cbnz x2, ret_fast_syscall_trace and x2, x1, #_TIF_WORK_MASK @@ -641,14 +892,14 @@ work_pending: tbnz x1, #TIF_NEED_RESCHED, work_resched /* TIF_SIGPENDING, TIF_NOTIFY_RESUME or TIF_FOREIGN_FPSTATE case */ - ldr x2, [sp, #S_PSTATE] mov x0, sp // 'regs' - tst x2, #PSR_MODE_MASK // user mode regs? - b.ne no_work_pending // returning to kernel enable_irq // enable interrupts for do_notify_resume() bl do_notify_resume b ret_to_user work_resched: +#ifdef CONFIG_TRACE_IRQFLAGS + bl trace_hardirqs_off // the IRQs are off here, inform the tracing code +#endif bl schedule /* @@ -656,11 +907,14 @@ */ ret_to_user: disable_irq // disable interrupts +#ifdef CONFIG_THREAD_INFO_IN_TASK + ldr x1, [tsk, #TSK_TI_FLAGS] +#else ldr x1, [tsk, #TI_FLAGS] +#endif and x2, x1, #_TIF_WORK_MASK cbnz x2, work_pending enable_step_tsk x1, x2 -no_work_pending: kernel_exit 0 ENDPROC(ret_to_user) @@ -689,7 +943,11 @@ enable_dbg_and_irq ct_user_exit 1 +#ifdef CONFIG_THREAD_INFO_IN_TASK + ldr x16, [tsk, #TSK_TI_FLAGS] // check for syscall hooks +#else ldr x16, [tsk, #TI_FLAGS] // check for syscall hooks +#endif tst x16, #_TIF_SYSCALL_WORK b.ne __sys_trace cmp scno, sc_nr // check upper syscall limit @@ -740,6 +998,120 @@ bl do_ni_syscall b __sys_trace_return + .popsection // .entry.text +#ifdef CONFIG_UNMAP_KERNEL_AT_EL0 +/* + * Exception vectors trampoline. + */ + .pushsection ".entry.tramp.text", "ax" + + .macro tramp_map_kernel, tmp + mrs \tmp, ttbr1_el1 + sub \tmp, \tmp, #(SWAPPER_DIR_SIZE + RESERVED_TTBR0_SIZE) + bic \tmp, \tmp, #USER_ASID_FLAG + msr ttbr1_el1, \tmp +#ifdef CONFIG_ARCH_MSM8996 + /* ASID already in \tmp[63:48] */ + movk \tmp, #:abs_g2_nc:(TRAMP_VALIAS >> 12) + movk \tmp, #:abs_g1_nc:(TRAMP_VALIAS >> 12) + /* 2MB boundary containing the vectors, so we nobble the walk cache */ + movk \tmp, #:abs_g0_nc:((TRAMP_VALIAS & ~(SZ_2M - 1)) >> 12) + isb + tlbi vae1, \tmp + dsb nsh +#endif /* CONFIG_ARCH_MSM8996 */ + .endm + + .macro tramp_unmap_kernel, tmp + mrs \tmp, ttbr1_el1 + add \tmp, \tmp, #(SWAPPER_DIR_SIZE + RESERVED_TTBR0_SIZE) + orr \tmp, \tmp, #USER_ASID_FLAG + msr ttbr1_el1, \tmp + /* + * We avoid running the post_ttbr_update_workaround here because the + * user and kernel ASIDs don't have conflicting mappings, so any + * "blessing" as described in: + * + * http://lkml.kernel.org/r/56BB848A.6060603@caviumnetworks.com + * + * will not hurt correctness. Whilst this may partially defeat the + * point of using split ASIDs in the first place, it avoids + * the hit of invalidating the entire I-cache on every return to + * userspace. + */ + .endm + + .macro tramp_ventry, regsize = 64 + .align 7 +1: + .if \regsize == 64 + msr tpidrro_el0, x30 // Restored in kernel_ventry + .endif + bl 2f + b . +2: + tramp_map_kernel x30 +#ifdef CONFIG_RANDOMIZE_BASE + adr x30, tramp_vectors + PAGE_SIZE +#ifndef CONFIG_ARCH_MSM8996 + isb +#endif + ldr x30, [x30] +#else + ldr x30, =vectors +#endif + prfm plil1strm, [x30, #(1b - tramp_vectors)] + msr vbar_el1, x30 + add x30, x30, #(1b - tramp_vectors) + isb + ret + .endm + + .macro tramp_exit, regsize = 64 + adr x30, tramp_vectors + msr vbar_el1, x30 + tramp_unmap_kernel x30 + .if \regsize == 64 + mrs x30, far_el1 + .endif + eret + .endm + + .align 11 +ENTRY(tramp_vectors) + .space 0x400 + + tramp_ventry + tramp_ventry + tramp_ventry + tramp_ventry + + tramp_ventry 32 + tramp_ventry 32 + tramp_ventry 32 + tramp_ventry 32 +END(tramp_vectors) + +ENTRY(tramp_exit_native) + tramp_exit +END(tramp_exit_native) + +ENTRY(tramp_exit_compat) + tramp_exit 32 +END(tramp_exit_compat) + + .ltorg + .popsection // .entry.tramp.text +#ifdef CONFIG_RANDOMIZE_BASE + .pushsection ".rodata", "a" + .align PAGE_SHIFT + .globl __entry_tramp_data_start +__entry_tramp_data_start: + .quad vectors + .popsection // .rodata +#endif /* CONFIG_RANDOMIZE_BASE */ +#endif /* CONFIG_UNMAP_KERNEL_AT_EL0 */ + /* * Special system call wrappers. */ diff -ruw linux-4.4.115/arch/arm64/kernel/fpsimd.c linux-4.4.115-fbx/arch/arm64/kernel/fpsimd.c --- linux-4.4.115/arch/arm64/kernel/fpsimd.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/arch/arm64/kernel/fpsimd.c 2019-01-22 16:16:21.551228730 +0100 @@ -20,6 +20,7 @@ #include #include #include +#include #include #include #include @@ -27,6 +28,7 @@ #include #include +#include #define FPEXC_IOF (1 << 0) #define FPEXC_DZF (1 << 1) @@ -35,6 +37,8 @@ #define FPEXC_IXF (1 << 4) #define FPEXC_IDF (1 << 7) +#define FP_SIMD_BIT 31 + /* * In order to reduce the number of times the FPSIMD state is needlessly saved * and restored, we need to keep track of two things: @@ -88,14 +92,42 @@ * whatever is in the FPSIMD registers is not saved to memory, but discarded. */ static DEFINE_PER_CPU(struct fpsimd_state *, fpsimd_last_state); +static DEFINE_PER_CPU(int, fpsimd_stg_enable); + +static int fpsimd_settings = 0x1; /* default = 0x1 */ +module_param(fpsimd_settings, int, 0644); + +void fpsimd_settings_enable(void) +{ + set_app_setting_bit(FP_SIMD_BIT); +} + +void fpsimd_settings_disable(void) +{ + clear_app_setting_bit(FP_SIMD_BIT); +} /* * Trapped FP/ASIMD access. */ void do_fpsimd_acc(unsigned int esr, struct pt_regs *regs) { - /* TODO: implement lazy context saving/restoring */ - WARN_ON(1); + if (!fpsimd_settings) + return; + + fpsimd_disable_trap(); + fpsimd_settings_disable(); + this_cpu_write(fpsimd_stg_enable, 0); +} + +void do_fpsimd_acc_compat(unsigned int esr, struct pt_regs *regs) +{ + if (!fpsimd_settings) + return; + + fpsimd_disable_trap(); + fpsimd_settings_enable(); + this_cpu_write(fpsimd_stg_enable, 1); } /* @@ -135,6 +167,11 @@ if (current->mm && !test_thread_flag(TIF_FOREIGN_FPSTATE)) fpsimd_save_state(¤t->thread.fpsimd_state); + if (fpsimd_settings && __this_cpu_read(fpsimd_stg_enable)) { + fpsimd_settings_disable(); + this_cpu_write(fpsimd_stg_enable, 0); + } + if (next->mm) { /* * If we are switching to a task whose most recent userland @@ -152,6 +189,14 @@ else set_ti_thread_flag(task_thread_info(next), TIF_FOREIGN_FPSTATE); + + if (!fpsimd_settings) + return; + + if (test_ti_thread_flag(task_thread_info(next), TIF_32BIT)) + fpsimd_enable_trap(); + else + fpsimd_disable_trap(); } } @@ -291,7 +336,7 @@ .notifier_call = fpsimd_cpu_pm_notifier, }; -static void fpsimd_pm_init(void) +static void __init fpsimd_pm_init(void) { cpu_pm_register_notifier(&fpsimd_cpu_pm_notifier_block); } diff -ruw linux-4.4.115/arch/arm64/kernel/head.S linux-4.4.115-fbx/arch/arm64/kernel/head.S --- linux-4.4.115/arch/arm64/kernel/head.S 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/arch/arm64/kernel/head.S 2019-10-29 09:26:23.001196895 +0100 @@ -25,10 +25,12 @@ #include #include +#include #include #include #include #include +#include #include #include #include @@ -48,9 +50,6 @@ #error TEXT_OFFSET must be less than 2MB #endif -#define KERNEL_START _text -#define KERNEL_END _end - /* * Kernel startup entry point. * --------------------------- @@ -67,12 +66,11 @@ * in the entry routines. */ __HEAD - +_head: /* * DO NOT MODIFY. Image header expected by Linux boot-loaders. */ #ifdef CONFIG_EFI -efi_head: /* * This add instruction has no meaningful effect except that * its opcode forms the magic "MZ" signature required by UEFI. @@ -83,9 +81,9 @@ b stext // branch to kernel start, magic .long 0 // reserved #endif - .quad _kernel_offset_le // Image load offset from start of RAM, little-endian - .quad _kernel_size_le // Effective size of kernel image, little-endian - .quad _kernel_flags_le // Informative flags, little-endian + le64sym _kernel_offset_le // Image load offset from start of RAM, little-endian + le64sym _kernel_size_le // Effective size of kernel image, little-endian + le64sym _kernel_flags_le // Informative flags, little-endian .quad 0 // reserved .quad 0 // reserved .quad 0 // reserved @@ -94,14 +92,12 @@ .byte 0x4d .byte 0x64 #ifdef CONFIG_EFI - .long pe_header - efi_head // Offset to the PE header. + .long pe_header - _head // Offset to the PE header. #else .word 0 // reserved #endif #ifdef CONFIG_EFI - .globl __efistub_stext_offset - .set __efistub_stext_offset, stext - efi_head .align 3 pe_header: .ascii "PE" @@ -121,11 +117,11 @@ .short 0x20b // PE32+ format .byte 0x02 // MajorLinkerVersion .byte 0x14 // MinorLinkerVersion - .long _end - stext // SizeOfCode + .long _end - efi_header_end // SizeOfCode .long 0 // SizeOfInitializedData .long 0 // SizeOfUninitializedData - .long __efistub_entry - efi_head // AddressOfEntryPoint - .long __efistub_stext_offset // BaseOfCode + .long __efistub_entry - _head // AddressOfEntryPoint + .long efi_header_end - _head // BaseOfCode extra_header_fields: .quad 0 // ImageBase @@ -139,10 +135,10 @@ .short 0 // MinorSubsystemVersion .long 0 // Win32VersionValue - .long _end - efi_head // SizeOfImage + .long _end - _head // SizeOfImage // Everything before the kernel image is considered part of the header - .long __efistub_stext_offset // SizeOfHeaders + .long efi_header_end - _head // SizeOfHeaders .long 0 // CheckSum .short 0xa // Subsystem (EFI application) .short 0 // DllCharacteristics @@ -186,10 +182,10 @@ .byte 0 .byte 0 .byte 0 // end of 0 padding of section name - .long _end - stext // VirtualSize - .long __efistub_stext_offset // VirtualAddress - .long _edata - stext // SizeOfRawData - .long __efistub_stext_offset // PointerToRawData + .long _end - efi_header_end // VirtualSize + .long efi_header_end - _head // VirtualAddress + .long _edata - efi_header_end // SizeOfRawData + .long efi_header_end - _head // PointerToRawData .long 0 // PointerToRelocations (0 for executables) .long 0 // PointerToLineNumbers (0 for executables) @@ -198,19 +194,23 @@ .long 0xe0500020 // Characteristics (section flags) /* - * EFI will load stext onwards at the 4k section alignment + * EFI will load .text onwards at the 4k section alignment * described in the PE/COFF header. To ensure that instruction * sequences using an adrp and a :lo12: immediate will function - * correctly at this alignment, we must ensure that stext is + * correctly at this alignment, we must ensure that .text is * placed at a 4k boundary in the Image to begin with. */ .align 12 +efi_header_end: #endif + __INIT + ENTRY(stext) bl preserve_boot_args bl el2_setup // Drop to EL1, w20=cpu_boot_mode adrp x24, __PHYS_OFFSET + and x23, x24, MIN_KIMG_ALIGN - 1 // KASLR offset, defaults to 0 bl set_cpu_boot_mode_flag bl __create_page_tables // x25=TTBR0, x26=TTBR1 /* @@ -219,10 +219,10 @@ * On return, the CPU will be ready for the MMU to be turned on and * the TCR will have been set. */ - ldr x27, =__mmap_switched // address to jump to after + bl __cpu_setup // initialise processor + adr_l x27, __primary_switch // address to jump to after // MMU has been enabled - adr_l lr, __enable_mmu // return (PIC) address - b __cpu_setup // initialise processor + b __enable_mmu ENDPROC(stext) /* @@ -311,21 +311,21 @@ __create_page_tables: adrp x25, idmap_pg_dir adrp x26, swapper_pg_dir - mov x27, lr + mov x28, lr /* * Invalidate the idmap and swapper page tables to avoid potential * dirty cache lines being evicted. */ mov x0, x25 - add x1, x26, #SWAPPER_DIR_SIZE + add x1, x26, #SWAPPER_DIR_SIZE + RESERVED_TTBR0_SIZE bl __inval_cache_range /* * Clear the idmap and swapper page tables. */ mov x0, x25 - add x6, x26, #SWAPPER_DIR_SIZE + add x6, x26, #SWAPPER_DIR_SIZE + RESERVED_TTBR0_SIZE 1: stp xzr, xzr, [x0], #16 stp xzr, xzr, [x0], #16 stp xzr, xzr, [x0], #16 @@ -333,7 +333,7 @@ cmp x0, x6 b.lo 1b - ldr x7, =SWAPPER_MM_MMUFLAGS + mov x7, SWAPPER_MM_MMUFLAGS /* * Create the identity mapping. @@ -389,10 +389,13 @@ * Map the kernel image (starting with PHYS_OFFSET). */ mov x0, x26 // swapper_pg_dir - mov x5, #PAGE_OFFSET + mov_q x5, KIMAGE_VADDR + TEXT_OFFSET // compile time __va(_text) + add x5, x5, x23 // add KASLR displacement create_pgd_entry x0, x5, x3, x6 - ldr x6, =KERNEL_END // __va(KERNEL_END) - mov x3, x24 // phys offset + adrp x6, _end // runtime __pa(_end) + adrp x3, _text // runtime __pa(_text) + sub x6, x6, x3 // _end - _text + add x6, x6, x5 // runtime __va(_end) create_block_map x0, x7, x3, x5, x6 /* @@ -401,12 +404,11 @@ * tables again to remove any speculatively loaded cache lines. */ mov x0, x25 - add x1, x26, #SWAPPER_DIR_SIZE + add x1, x26, #SWAPPER_DIR_SIZE + RESERVED_TTBR0_SIZE dmb sy bl __inval_cache_range - mov lr, x27 - ret + ret x28 ENDPROC(__create_page_tables) .ltorg @@ -414,30 +416,67 @@ * The following fragment of code is executed with the MMU enabled. */ .set initial_sp, init_thread_union + THREAD_START_SP -__mmap_switched: - adr_l x6, __bss_start - adr_l x7, __bss_stop - -1: cmp x6, x7 - b.hs 2f - str xzr, [x6], #8 // Clear BSS - b 1b -2: +__primary_switched: + mov x28, lr // preserve LR + + adr_l x8, vectors // load VBAR_EL1 with virtual + msr vbar_el1, x8 // vector table address + isb + + // Clear BSS + adr_l x0, __bss_start + mov x1, xzr + adr_l x2, __bss_stop + sub x2, x2, x0 + bl __pi_memset + dsb ishst // Make zero page visible to PTW + +#ifdef CONFIG_THREAD_INFO_IN_TASK + adrp x4, init_thread_union + add sp, x4, #THREAD_SIZE + adr_l x5, init_task + msr sp_el0, x5 // Save thread_info +#else adr_l sp, initial_sp, x4 + mov x4, sp + and x4, x4, #~(THREAD_SIZE - 1) + msr sp_el0, x4 // Save thread_info +#endif + str_l x21, __fdt_pointer, x5 // Save FDT pointer - str_l x24, memstart_addr, x6 // Save PHYS_OFFSET + + ldr_l x4, kimage_vaddr // Save the offset between + sub x4, x4, x24 // the kernel virtual and + str_l x4, kimage_voffset, x5 // physical mappings + mov x29, #0 #ifdef CONFIG_KASAN bl kasan_early_init #endif +#ifdef CONFIG_RANDOMIZE_BASE + tst x23, ~(MIN_KIMG_ALIGN - 1) // already running randomized? + b.ne 0f + mov x0, x21 // pass FDT address in x0 + mov x1, x23 // pass modulo offset in x1 + bl kaslr_early_init // parse FDT for KASLR options + cbz x0, 0f // KASLR disabled? just proceed + orr x23, x23, x0 // record KASLR offset + ret x28 // we must enable KASLR, return + // to __enable_mmu() +0: +#endif b start_kernel -ENDPROC(__mmap_switched) +ENDPROC(__primary_switched) /* * end early head section, begin head code that is also used for * hotplug and needs to have the same protections as the text region */ .section ".text","ax" + +ENTRY(kimage_vaddr) + .quad _text - TEXT_OFFSET + /* * If we're fortunate enough to boot at EL2, ensure that the world is * sane before dropping to EL1. @@ -544,7 +583,7 @@ * Sets the __boot_cpu_mode flag depending on the CPU boot mode passed * in x20. See arch/arm64/include/asm/virt.h for more info. */ -ENTRY(set_cpu_boot_mode_flag) +set_cpu_boot_mode_flag: adr_l x1, __boot_cpu_mode cmp w20, #BOOT_CPU_MODE_EL2 b.ne 1f @@ -577,7 +616,7 @@ bl el2_setup // Drop to EL1, w20=cpu_boot_mode bl set_cpu_boot_mode_flag mrs x0, mpidr_el1 - ldr x1, =MPIDR_HWID_BITMASK + mov_q x1, MPIDR_HWID_BITMASK and x0, x0, x1 adr_l x3, secondary_holding_pen_release pen: ldr x4, [x3] @@ -597,7 +636,7 @@ b secondary_startup ENDPROC(secondary_entry) -ENTRY(secondary_startup) +secondary_startup: /* * Common entry point for secondary CPUs. */ @@ -605,14 +644,26 @@ adrp x26, swapper_pg_dir bl __cpu_setup // initialise processor - ldr x21, =secondary_data - ldr x27, =__secondary_switched // address to jump to after enabling the MMU + adr_l x27, __secondary_switch // address to jump to after enabling the MMU b __enable_mmu ENDPROC(secondary_startup) -ENTRY(__secondary_switched) - ldr x0, [x21] // get secondary_data.stack +__secondary_switched: + adr_l x5, vectors + msr vbar_el1, x5 + isb +#ifdef CONFIG_THREAD_INFO_IN_TASK + adr_l x0, secondary_data + ldr x1, [x0, #CPU_BOOT_STACK] // get secondary_data.stack + mov sp, x1 + ldr x2, [x0, #CPU_BOOT_TASK] + msr sp_el0, x2 +#else + ldr_l x0, secondary_data // get secondary_data.stack mov sp, x0 + and x0, x0, #~(THREAD_SIZE - 1) + msr sp_el0, x0 // save thread_info +#endif mov x29, #0 b secondary_start_kernel ENDPROC(__secondary_switched) @@ -629,13 +680,12 @@ * If it isn't, park the CPU */ .section ".idmap.text", "ax" -__enable_mmu: +ENTRY(__enable_mmu) + mrs x22, sctlr_el1 // preserve old SCTLR_EL1 value mrs x1, ID_AA64MMFR0_EL1 ubfx x2, x1, #ID_AA64MMFR0_TGRAN_SHIFT, 4 cmp x2, #ID_AA64MMFR0_TGRAN_SUPPORTED b.ne __no_granule_support - ldr x5, =vectors - msr vbar_el1, x5 msr ttbr0_el1, x25 // load TTBR0 msr ttbr1_el1, x26 // load TTBR1 isb @@ -649,6 +699,28 @@ ic iallu dsb nsh isb +#ifdef CONFIG_RANDOMIZE_BASE + mov x19, x0 // preserve new SCTLR_EL1 value + blr x27 + + /* + * If we return here, we have a KASLR displacement in x23 which we need + * to take into account by discarding the current kernel mapping and + * creating a new one. + */ + msr sctlr_el1, x22 // disable the MMU + isb + bl __create_page_tables // recreate kernel mapping + + tlbi vmalle1 // Remove any stale TLB entries + dsb nsh + + msr sctlr_el1, x19 // re-enable the MMU + isb + ic iallu // flush instructions fetched + dsb nsh // via old mapping + isb +#endif br x27 ENDPROC(__enable_mmu) @@ -656,3 +728,38 @@ wfe b __no_granule_support ENDPROC(__no_granule_support) + +__primary_switch: +#ifdef CONFIG_RELOCATABLE + /* + * Iterate over each entry in the relocation table, and apply the + * relocations in place. + */ + ldr w9, =__rela_offset // offset to reloc table + ldr w10, =__rela_size // size of reloc table + + mov_q x11, KIMAGE_VADDR // default virtual offset + add x11, x11, x23 // actual virtual offset + add x9, x9, x11 // __va(.rela) + add x10, x9, x10 // __va(.rela) + sizeof(.rela) + +0: cmp x9, x10 + b.hs 1f + ldp x11, x12, [x9], #24 + ldr x13, [x9, #-8] + cmp w12, #R_AARCH64_RELATIVE + b.ne 0b + add x13, x13, x23 // relocate + str x13, [x11, x23] + b 0b + +1: +#endif + ldr x8, =__primary_switched + br x8 +ENDPROC(__primary_switch) + +__secondary_switch: + ldr x8, =__secondary_switched + br x8 +ENDPROC(__secondary_switch) diff -ruw linux-4.4.115/arch/arm64/kernel/hyp-stub.S linux-4.4.115-fbx/arch/arm64/kernel/hyp-stub.S --- linux-4.4.115/arch/arm64/kernel/hyp-stub.S 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/arch/arm64/kernel/hyp-stub.S 2019-10-29 09:26:23.005196935 +0100 @@ -22,6 +22,8 @@ #include #include +#include +#include #include #include @@ -53,15 +55,26 @@ .align 11 el1_sync: - mrs x1, esr_el2 - lsr x1, x1, #26 - cmp x1, #0x16 - b.ne 2f // Not an HVC trap - cbz x0, 1f - msr vbar_el2, x0 // Set vbar_el2 - b 2f -1: mrs x0, vbar_el2 // Return vbar_el2 -2: eret + mrs x30, esr_el2 + lsr x30, x30, #ESR_ELx_EC_SHIFT + + cmp x30, #ESR_ELx_EC_HVC64 + b.ne 9f // Not an HVC trap + + cmp x0, #HVC_GET_VECTORS + b.ne 1f + mrs x0, vbar_el2 + b 9f + +1: cmp x0, #HVC_SET_VECTORS + b.ne 2f + msr vbar_el2, x1 + b 9f + + /* Someone called kvm_call_hyp() against the hyp-stub... */ +2: mov x0, #ARM_EXCEPTION_HYP_GONE + +9: eret ENDPROC(el1_sync) .macro invalid_vector label @@ -101,10 +114,18 @@ */ ENTRY(__hyp_get_vectors) - mov x0, xzr - // fall through -ENTRY(__hyp_set_vectors) + str lr, [sp, #-16]! + mov x0, #HVC_GET_VECTORS hvc #0 + ldr lr, [sp], #16 ret ENDPROC(__hyp_get_vectors) + +ENTRY(__hyp_set_vectors) + str lr, [sp, #-16]! + mov x1, x0 + mov x0, #HVC_SET_VECTORS + hvc #0 + ldr lr, [sp], #16 + ret ENDPROC(__hyp_set_vectors) diff -ruw linux-4.4.115/arch/arm64/kernel/image.h linux-4.4.115-fbx/arch/arm64/kernel/image.h --- linux-4.4.115/arch/arm64/kernel/image.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/arch/arm64/kernel/image.h 2019-10-29 09:26:23.005196935 +0100 @@ -26,21 +26,27 @@ * There aren't any ELF relocations we can use to endian-swap values known only * at link time (e.g. the subtraction of two symbol addresses), so we must get * the linker to endian-swap certain values before emitting them. + * + * Note that, in order for this to work when building the ELF64 PIE executable + * (for KASLR), these values should not be referenced via R_AARCH64_ABS64 + * relocations, since these are fixed up at runtime rather than at build time + * when PIE is in effect. So we need to split them up in 32-bit high and low + * words. */ #ifdef CONFIG_CPU_BIG_ENDIAN -#define DATA_LE64(data) \ - ((((data) & 0x00000000000000ff) << 56) | \ - (((data) & 0x000000000000ff00) << 40) | \ - (((data) & 0x0000000000ff0000) << 24) | \ - (((data) & 0x00000000ff000000) << 8) | \ - (((data) & 0x000000ff00000000) >> 8) | \ - (((data) & 0x0000ff0000000000) >> 24) | \ - (((data) & 0x00ff000000000000) >> 40) | \ - (((data) & 0xff00000000000000) >> 56)) +#define DATA_LE32(data) \ + ((((data) & 0x000000ff) << 24) | \ + (((data) & 0x0000ff00) << 8) | \ + (((data) & 0x00ff0000) >> 8) | \ + (((data) & 0xff000000) >> 24)) #else -#define DATA_LE64(data) ((data) & 0xffffffffffffffff) +#define DATA_LE32(data) ((data) & 0xffffffff) #endif +#define DEFINE_IMAGE_LE64(sym, data) \ + sym##_lo32 = DATA_LE32((data) & 0xffffffff); \ + sym##_hi32 = DATA_LE32((data) >> 32) + #ifdef CONFIG_CPU_BIG_ENDIAN #define __HEAD_FLAG_BE 1 #else @@ -49,8 +55,11 @@ #define __HEAD_FLAG_PAGE_SIZE ((PAGE_SHIFT - 10) / 2) +#define __HEAD_FLAG_PHYS_BASE 1 + #define __HEAD_FLAGS ((__HEAD_FLAG_BE << 0) | \ - (__HEAD_FLAG_PAGE_SIZE << 1)) + (__HEAD_FLAG_PAGE_SIZE << 1) | \ + (__HEAD_FLAG_PHYS_BASE << 3)) /* * These will output as part of the Image header, which should be little-endian @@ -58,12 +67,24 @@ * endian swapped in head.S, all are done here for consistency. */ #define HEAD_SYMBOLS \ - _kernel_size_le = DATA_LE64(_end - _text); \ - _kernel_offset_le = DATA_LE64(TEXT_OFFSET); \ - _kernel_flags_le = DATA_LE64(__HEAD_FLAGS); + DEFINE_IMAGE_LE64(_kernel_size_le, _end - _text); \ + DEFINE_IMAGE_LE64(_kernel_offset_le, TEXT_OFFSET); \ + DEFINE_IMAGE_LE64(_kernel_flags_le, __HEAD_FLAGS); #ifdef CONFIG_EFI +__efistub_stext_offset = stext - _text; + +/* + * Prevent the symbol aliases below from being emitted into the kallsyms + * table, by forcing them to be absolute symbols (which are conveniently + * ignored by scripts/kallsyms) rather than section relative symbols. + * The distinction is only relevant for partial linking, and only for symbols + * that are defined within a section declaration (which is not the case for + * the definitions below) so the resulting values will be identical. + */ +#define KALLSYMS_HIDE(sym) ABSOLUTE(sym) + /* * The EFI stub has its own symbol namespace prefixed by __efistub_, to * isolate it from the kernel proper. The following symbols are legally @@ -73,25 +94,25 @@ * linked at. The routines below are all implemented in assembler in a * position independent manner */ -__efistub_memcmp = __pi_memcmp; -__efistub_memchr = __pi_memchr; -__efistub_memcpy = __pi_memcpy; -__efistub_memmove = __pi_memmove; -__efistub_memset = __pi_memset; -__efistub_strlen = __pi_strlen; -__efistub_strcmp = __pi_strcmp; -__efistub_strncmp = __pi_strncmp; -__efistub___flush_dcache_area = __pi___flush_dcache_area; +__efistub_memcmp = KALLSYMS_HIDE(__pi_memcmp); +__efistub_memchr = KALLSYMS_HIDE(__pi_memchr); +__efistub_memcpy = KALLSYMS_HIDE(__pi_memcpy); +__efistub_memmove = KALLSYMS_HIDE(__pi_memmove); +__efistub_memset = KALLSYMS_HIDE(__pi_memset); +__efistub_strlen = KALLSYMS_HIDE(__pi_strlen); +__efistub_strcmp = KALLSYMS_HIDE(__pi_strcmp); +__efistub_strncmp = KALLSYMS_HIDE(__pi_strncmp); +__efistub___flush_dcache_area = KALLSYMS_HIDE(__pi___flush_dcache_area); #ifdef CONFIG_KASAN -__efistub___memcpy = __pi_memcpy; -__efistub___memmove = __pi_memmove; -__efistub___memset = __pi_memset; +__efistub___memcpy = KALLSYMS_HIDE(__pi_memcpy); +__efistub___memmove = KALLSYMS_HIDE(__pi_memmove); +__efistub___memset = KALLSYMS_HIDE(__pi_memset); #endif -__efistub__text = _text; -__efistub__end = _end; -__efistub__edata = _edata; +__efistub__text = KALLSYMS_HIDE(_text); +__efistub__end = KALLSYMS_HIDE(_end); +__efistub__edata = KALLSYMS_HIDE(_edata); #endif diff -ruw linux-4.4.115/arch/arm64/kernel/insn.c linux-4.4.115-fbx/arch/arm64/kernel/insn.c --- linux-4.4.115/arch/arm64/kernel/insn.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/arch/arm64/kernel/insn.c 2019-01-22 16:16:21.551228730 +0100 @@ -2,7 +2,7 @@ * Copyright (C) 2013 Huawei Ltd. * Author: Jiang Liu * - * Copyright (C) 2014 Zi Shen Lim + * Copyright (C) 2014-2016 Zi Shen Lim * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as @@ -30,6 +30,7 @@ #include #include #include +#include #include #define AARCH64_INSN_SF_BIT BIT(31) @@ -95,8 +96,9 @@ if (module && IS_ENABLED(CONFIG_DEBUG_SET_MODULE_RONX)) page = vmalloc_to_page(addr); - else if (!module && IS_ENABLED(CONFIG_DEBUG_RODATA)) - page = virt_to_page(addr); + else if (!module && (IS_ENABLED(CONFIG_DEBUG_RODATA) + || IS_ENABLED(CONFIG_KERNEL_TEXT_RDONLY))) + page = phys_to_page(__pa_symbol(addr)); else return addr; @@ -162,6 +164,32 @@ aarch64_insn_is_nop(insn); } +bool __kprobes aarch64_insn_uses_literal(u32 insn) +{ + /* ldr/ldrsw (literal), prfm */ + + return aarch64_insn_is_ldr_lit(insn) || + aarch64_insn_is_ldrsw_lit(insn) || + aarch64_insn_is_adr_adrp(insn) || + aarch64_insn_is_prfm_lit(insn); +} + +bool __kprobes aarch64_insn_is_branch(u32 insn) +{ + /* b, bl, cb*, tb*, b.cond, br, blr */ + + return aarch64_insn_is_b(insn) || + aarch64_insn_is_bl(insn) || + aarch64_insn_is_cbz(insn) || + aarch64_insn_is_cbnz(insn) || + aarch64_insn_is_tbz(insn) || + aarch64_insn_is_tbnz(insn) || + aarch64_insn_is_ret(insn) || + aarch64_insn_is_br(insn) || + aarch64_insn_is_blr(insn) || + aarch64_insn_is_bcond(insn); +} + /* * ARM Architecture Reference Manual for ARMv8 Profile-A, Issue A.a * Section B2.6.5 "Concurrent modification and execution of instructions": @@ -363,6 +391,9 @@ u32 immlo, immhi, mask; int shift; + if (insn == AARCH64_BREAK_FAULT) + return AARCH64_BREAK_FAULT; + switch (type) { case AARCH64_INSN_IMM_ADR: shift = 0; @@ -377,7 +408,7 @@ if (aarch64_get_imm_shift_mask(type, &mask, &shift) < 0) { pr_err("aarch64_insn_encode_immediate: unknown immediate encoding %d\n", type); - return 0; + return AARCH64_BREAK_FAULT; } } @@ -394,9 +425,12 @@ { int shift; + if (insn == AARCH64_BREAK_FAULT) + return AARCH64_BREAK_FAULT; + if (reg < AARCH64_INSN_REG_0 || reg > AARCH64_INSN_REG_SP) { pr_err("%s: unknown register encoding %d\n", __func__, reg); - return 0; + return AARCH64_BREAK_FAULT; } switch (type) { @@ -417,7 +451,7 @@ default: pr_err("%s: unknown register type encoding %d\n", __func__, type); - return 0; + return AARCH64_BREAK_FAULT; } insn &= ~(GENMASK(4, 0) << shift); @@ -446,7 +480,7 @@ break; default: pr_err("%s: unknown size encoding %d\n", __func__, type); - return 0; + return AARCH64_BREAK_FAULT; } insn &= ~GENMASK(31, 30); @@ -460,14 +494,17 @@ { long offset; - /* - * PC: A 64-bit Program Counter holding the address of the current - * instruction. A64 instructions must be word-aligned. - */ - BUG_ON((pc & 0x3) || (addr & 0x3)); + if ((pc & 0x3) || (addr & 0x3)) { + pr_err("%s: A64 instructions must be word aligned\n", __func__); + return range; + } offset = ((long)addr - (long)pc); - BUG_ON(offset < -range || offset >= range); + + if (offset < -range || offset >= range) { + pr_err("%s: offset out of range\n", __func__); + return range; + } return offset; } @@ -484,6 +521,8 @@ * texts are within +/-128M. */ offset = branch_imm_common(pc, addr, SZ_128M); + if (offset >= SZ_128M) + return AARCH64_BREAK_FAULT; switch (type) { case AARCH64_INSN_BRANCH_LINK: @@ -493,7 +532,7 @@ insn = aarch64_insn_get_b_value(); break; default: - BUG_ON(1); + pr_err("%s: unknown branch encoding %d\n", __func__, type); return AARCH64_BREAK_FAULT; } @@ -510,6 +549,8 @@ long offset; offset = branch_imm_common(pc, addr, SZ_1M); + if (offset >= SZ_1M) + return AARCH64_BREAK_FAULT; switch (type) { case AARCH64_INSN_BRANCH_COMP_ZERO: @@ -519,7 +560,7 @@ insn = aarch64_insn_get_cbnz_value(); break; default: - BUG_ON(1); + pr_err("%s: unknown branch encoding %d\n", __func__, type); return AARCH64_BREAK_FAULT; } @@ -530,7 +571,7 @@ insn |= AARCH64_INSN_SF_BIT; break; default: - BUG_ON(1); + pr_err("%s: unknown variant encoding %d\n", __func__, variant); return AARCH64_BREAK_FAULT; } @@ -550,7 +591,10 @@ insn = aarch64_insn_get_bcond_value(); - BUG_ON(cond < AARCH64_INSN_COND_EQ || cond > AARCH64_INSN_COND_AL); + if (cond < AARCH64_INSN_COND_EQ || cond > AARCH64_INSN_COND_AL) { + pr_err("%s: unknown condition encoding %d\n", __func__, cond); + return AARCH64_BREAK_FAULT; + } insn |= cond; return aarch64_insn_encode_immediate(AARCH64_INSN_IMM_19, insn, @@ -583,7 +627,7 @@ insn = aarch64_insn_get_ret_value(); break; default: - BUG_ON(1); + pr_err("%s: unknown branch encoding %d\n", __func__, type); return AARCH64_BREAK_FAULT; } @@ -606,7 +650,7 @@ insn = aarch64_insn_get_str_reg_value(); break; default: - BUG_ON(1); + pr_err("%s: unknown load/store encoding %d\n", __func__, type); return AARCH64_BREAK_FAULT; } @@ -645,26 +689,30 @@ insn = aarch64_insn_get_stp_post_value(); break; default: - BUG_ON(1); + pr_err("%s: unknown load/store encoding %d\n", __func__, type); return AARCH64_BREAK_FAULT; } switch (variant) { case AARCH64_INSN_VARIANT_32BIT: - /* offset must be multiples of 4 in the range [-256, 252] */ - BUG_ON(offset & 0x3); - BUG_ON(offset < -256 || offset > 252); + if ((offset & 0x3) || (offset < -256) || (offset > 252)) { + pr_err("%s: offset must be multiples of 4 in the range of [-256, 252] %d\n", + __func__, offset); + return AARCH64_BREAK_FAULT; + } shift = 2; break; case AARCH64_INSN_VARIANT_64BIT: - /* offset must be multiples of 8 in the range [-512, 504] */ - BUG_ON(offset & 0x7); - BUG_ON(offset < -512 || offset > 504); + if ((offset & 0x7) || (offset < -512) || (offset > 504)) { + pr_err("%s: offset must be multiples of 8 in the range of [-512, 504] %d\n", + __func__, offset); + return AARCH64_BREAK_FAULT; + } shift = 3; insn |= AARCH64_INSN_SF_BIT; break; default: - BUG_ON(1); + pr_err("%s: unknown variant encoding %d\n", __func__, variant); return AARCH64_BREAK_FAULT; } @@ -702,7 +750,7 @@ insn = aarch64_insn_get_subs_imm_value(); break; default: - BUG_ON(1); + pr_err("%s: unknown add/sub encoding %d\n", __func__, type); return AARCH64_BREAK_FAULT; } @@ -713,11 +761,14 @@ insn |= AARCH64_INSN_SF_BIT; break; default: - BUG_ON(1); + pr_err("%s: unknown variant encoding %d\n", __func__, variant); return AARCH64_BREAK_FAULT; } - BUG_ON(imm & ~(SZ_4K - 1)); + if (imm & ~(SZ_4K - 1)) { + pr_err("%s: invalid immediate encoding %d\n", __func__, imm); + return AARCH64_BREAK_FAULT; + } insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RD, insn, dst); @@ -746,7 +797,7 @@ insn = aarch64_insn_get_sbfm_value(); break; default: - BUG_ON(1); + pr_err("%s: unknown bitfield encoding %d\n", __func__, type); return AARCH64_BREAK_FAULT; } @@ -759,12 +810,18 @@ mask = GENMASK(5, 0); break; default: - BUG_ON(1); + pr_err("%s: unknown variant encoding %d\n", __func__, variant); return AARCH64_BREAK_FAULT; } - BUG_ON(immr & ~mask); - BUG_ON(imms & ~mask); + if (immr & ~mask) { + pr_err("%s: invalid immr encoding %d\n", __func__, immr); + return AARCH64_BREAK_FAULT; + } + if (imms & ~mask) { + pr_err("%s: invalid imms encoding %d\n", __func__, imms); + return AARCH64_BREAK_FAULT; + } insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RD, insn, dst); @@ -793,23 +850,33 @@ insn = aarch64_insn_get_movn_value(); break; default: - BUG_ON(1); + pr_err("%s: unknown movewide encoding %d\n", __func__, type); return AARCH64_BREAK_FAULT; } - BUG_ON(imm & ~(SZ_64K - 1)); + if (imm & ~(SZ_64K - 1)) { + pr_err("%s: invalid immediate encoding %d\n", __func__, imm); + return AARCH64_BREAK_FAULT; + } switch (variant) { case AARCH64_INSN_VARIANT_32BIT: - BUG_ON(shift != 0 && shift != 16); + if (shift != 0 && shift != 16) { + pr_err("%s: invalid shift encoding %d\n", __func__, + shift); + return AARCH64_BREAK_FAULT; + } break; case AARCH64_INSN_VARIANT_64BIT: insn |= AARCH64_INSN_SF_BIT; - BUG_ON(shift != 0 && shift != 16 && shift != 32 && - shift != 48); + if (shift != 0 && shift != 16 && shift != 32 && shift != 48) { + pr_err("%s: invalid shift encoding %d\n", __func__, + shift); + return AARCH64_BREAK_FAULT; + } break; default: - BUG_ON(1); + pr_err("%s: unknown variant encoding %d\n", __func__, variant); return AARCH64_BREAK_FAULT; } @@ -843,20 +910,28 @@ insn = aarch64_insn_get_subs_value(); break; default: - BUG_ON(1); + pr_err("%s: unknown add/sub encoding %d\n", __func__, type); return AARCH64_BREAK_FAULT; } switch (variant) { case AARCH64_INSN_VARIANT_32BIT: - BUG_ON(shift & ~(SZ_32 - 1)); + if (shift & ~(SZ_32 - 1)) { + pr_err("%s: invalid shift encoding %d\n", __func__, + shift); + return AARCH64_BREAK_FAULT; + } break; case AARCH64_INSN_VARIANT_64BIT: insn |= AARCH64_INSN_SF_BIT; - BUG_ON(shift & ~(SZ_64 - 1)); + if (shift & ~(SZ_64 - 1)) { + pr_err("%s: invalid shift encoding %d\n", __func__, + shift); + return AARCH64_BREAK_FAULT; + } break; default: - BUG_ON(1); + pr_err("%s: unknown variant encoding %d\n", __func__, variant); return AARCH64_BREAK_FAULT; } @@ -885,11 +960,15 @@ insn = aarch64_insn_get_rev32_value(); break; case AARCH64_INSN_DATA1_REVERSE_64: - BUG_ON(variant != AARCH64_INSN_VARIANT_64BIT); + if (variant != AARCH64_INSN_VARIANT_64BIT) { + pr_err("%s: invalid variant for reverse64 %d\n", + __func__, variant); + return AARCH64_BREAK_FAULT; + } insn = aarch64_insn_get_rev64_value(); break; default: - BUG_ON(1); + pr_err("%s: unknown data1 encoding %d\n", __func__, type); return AARCH64_BREAK_FAULT; } @@ -900,7 +979,7 @@ insn |= AARCH64_INSN_SF_BIT; break; default: - BUG_ON(1); + pr_err("%s: unknown variant encoding %d\n", __func__, variant); return AARCH64_BREAK_FAULT; } @@ -937,7 +1016,7 @@ insn = aarch64_insn_get_rorv_value(); break; default: - BUG_ON(1); + pr_err("%s: unknown data2 encoding %d\n", __func__, type); return AARCH64_BREAK_FAULT; } @@ -948,7 +1027,7 @@ insn |= AARCH64_INSN_SF_BIT; break; default: - BUG_ON(1); + pr_err("%s: unknown variant encoding %d\n", __func__, variant); return AARCH64_BREAK_FAULT; } @@ -976,7 +1055,7 @@ insn = aarch64_insn_get_msub_value(); break; default: - BUG_ON(1); + pr_err("%s: unknown data3 encoding %d\n", __func__, type); return AARCH64_BREAK_FAULT; } @@ -987,7 +1066,7 @@ insn |= AARCH64_INSN_SF_BIT; break; default: - BUG_ON(1); + pr_err("%s: unknown variant encoding %d\n", __func__, variant); return AARCH64_BREAK_FAULT; } @@ -1037,20 +1116,28 @@ insn = aarch64_insn_get_bics_value(); break; default: - BUG_ON(1); + pr_err("%s: unknown logical encoding %d\n", __func__, type); return AARCH64_BREAK_FAULT; } switch (variant) { case AARCH64_INSN_VARIANT_32BIT: - BUG_ON(shift & ~(SZ_32 - 1)); + if (shift & ~(SZ_32 - 1)) { + pr_err("%s: invalid shift encoding %d\n", __func__, + shift); + return AARCH64_BREAK_FAULT; + } break; case AARCH64_INSN_VARIANT_64BIT: insn |= AARCH64_INSN_SF_BIT; - BUG_ON(shift & ~(SZ_64 - 1)); + if (shift & ~(SZ_64 - 1)) { + pr_err("%s: invalid shift encoding %d\n", __func__, + shift); + return AARCH64_BREAK_FAULT; + } break; default: - BUG_ON(1); + pr_err("%s: unknown variant encoding %d\n", __func__, variant); return AARCH64_BREAK_FAULT; } @@ -1116,6 +1203,14 @@ BUG(); } +/* + * Extract the Op/CR data from a msr/mrs instruction. + */ +u32 aarch64_insn_extract_system_reg(u32 insn) +{ + return (insn & 0x1FFFE0) >> 5; +} + bool aarch32_insn_is_wide(u32 insn) { return insn >= 0xe800; @@ -1141,3 +1236,101 @@ { return insn & CRM_MASK; } + +static bool __kprobes __check_eq(unsigned long pstate) +{ + return (pstate & PSR_Z_BIT) != 0; +} + +static bool __kprobes __check_ne(unsigned long pstate) +{ + return (pstate & PSR_Z_BIT) == 0; +} + +static bool __kprobes __check_cs(unsigned long pstate) +{ + return (pstate & PSR_C_BIT) != 0; +} + +static bool __kprobes __check_cc(unsigned long pstate) +{ + return (pstate & PSR_C_BIT) == 0; +} + +static bool __kprobes __check_mi(unsigned long pstate) +{ + return (pstate & PSR_N_BIT) != 0; +} + +static bool __kprobes __check_pl(unsigned long pstate) +{ + return (pstate & PSR_N_BIT) == 0; +} + +static bool __kprobes __check_vs(unsigned long pstate) +{ + return (pstate & PSR_V_BIT) != 0; +} + +static bool __kprobes __check_vc(unsigned long pstate) +{ + return (pstate & PSR_V_BIT) == 0; +} + +static bool __kprobes __check_hi(unsigned long pstate) +{ + pstate &= ~(pstate >> 1); /* PSR_C_BIT &= ~PSR_Z_BIT */ + return (pstate & PSR_C_BIT) != 0; +} + +static bool __kprobes __check_ls(unsigned long pstate) +{ + pstate &= ~(pstate >> 1); /* PSR_C_BIT &= ~PSR_Z_BIT */ + return (pstate & PSR_C_BIT) == 0; +} + +static bool __kprobes __check_ge(unsigned long pstate) +{ + pstate ^= (pstate << 3); /* PSR_N_BIT ^= PSR_V_BIT */ + return (pstate & PSR_N_BIT) == 0; +} + +static bool __kprobes __check_lt(unsigned long pstate) +{ + pstate ^= (pstate << 3); /* PSR_N_BIT ^= PSR_V_BIT */ + return (pstate & PSR_N_BIT) != 0; +} + +static bool __kprobes __check_gt(unsigned long pstate) +{ + /*PSR_N_BIT ^= PSR_V_BIT */ + unsigned long temp = pstate ^ (pstate << 3); + + temp |= (pstate << 1); /*PSR_N_BIT |= PSR_Z_BIT */ + return (temp & PSR_N_BIT) == 0; +} + +static bool __kprobes __check_le(unsigned long pstate) +{ + /*PSR_N_BIT ^= PSR_V_BIT */ + unsigned long temp = pstate ^ (pstate << 3); + + temp |= (pstate << 1); /*PSR_N_BIT |= PSR_Z_BIT */ + return (temp & PSR_N_BIT) != 0; +} + +static bool __kprobes __check_al(unsigned long pstate) +{ + return true; +} + +/* + * Note that the ARMv8 ARM calls condition code 0b1111 "nv", but states that + * it behaves identically to 0b1110 ("al"). + */ +pstate_check_t * const aarch32_opcode_cond_checks[16] = { + __check_eq, __check_ne, __check_cs, __check_cc, + __check_mi, __check_pl, __check_vs, __check_vc, + __check_hi, __check_ls, __check_ge, __check_lt, + __check_gt, __check_le, __check_al, __check_al +}; diff -ruw linux-4.4.115/arch/arm64/kernel/io.c linux-4.4.115-fbx/arch/arm64/kernel/io.c --- linux-4.4.115/arch/arm64/kernel/io.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/arch/arm64/kernel/io.c 2019-01-22 16:16:21.551228730 +0100 @@ -19,29 +19,29 @@ #include #include #include +#include /* * Copy data from IO memory space to "real" memory space. */ void __memcpy_fromio(void *to, const volatile void __iomem *from, size_t count) { - while (count && (!IS_ALIGNED((unsigned long)from, 8) || - !IS_ALIGNED((unsigned long)to, 8))) { - *(u8 *)to = __raw_readb(from); + while (count && !IS_ALIGNED((unsigned long)from, 8)) { + *(u8 *)to = __raw_readb_no_log(from); from++; to++; count--; } while (count >= 8) { - *(u64 *)to = __raw_readq(from); + *(u64 *)to = __raw_readq_no_log(from); from += 8; to += 8; count -= 8; } while (count) { - *(u8 *)to = __raw_readb(from); + *(u8 *)to = __raw_readb_no_log(from); from++; to++; count--; @@ -54,23 +54,22 @@ */ void __memcpy_toio(volatile void __iomem *to, const void *from, size_t count) { - while (count && (!IS_ALIGNED((unsigned long)to, 8) || - !IS_ALIGNED((unsigned long)from, 8))) { - __raw_writeb(*(volatile u8 *)from, to); + while (count && !IS_ALIGNED((unsigned long)to, 8)) { + __raw_writeb_no_log(*(u8 *)from, to); from++; to++; count--; } while (count >= 8) { - __raw_writeq(*(volatile u64 *)from, to); + __raw_writeq_no_log(*(u64 *)from, to); from += 8; to += 8; count -= 8; } while (count) { - __raw_writeb(*(volatile u8 *)from, to); + __raw_writeb_no_log(*(u8 *)from, to); from++; to++; count--; @@ -90,19 +89,19 @@ qc |= qc << 32; while (count && !IS_ALIGNED((unsigned long)dst, 8)) { - __raw_writeb(c, dst); + __raw_writeb_no_log(c, dst); dst++; count--; } while (count >= 8) { - __raw_writeq(qc, dst); + __raw_writeq_no_log(qc, dst); dst += 8; count -= 8; } while (count) { - __raw_writeb(c, dst); + __raw_writeb_no_log(c, dst); dst++; count--; } diff -ruw linux-4.4.115/arch/arm64/kernel/irq.c linux-4.4.115-fbx/arch/arm64/kernel/irq.c --- linux-4.4.115/arch/arm64/kernel/irq.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/arch/arm64/kernel/irq.c 2019-01-22 16:16:21.551228730 +0100 @@ -30,6 +30,9 @@ unsigned long irq_err_count; +/* irq stack only needs to be 16 byte aligned - not IRQ_STACK_SIZE aligned. */ +DEFINE_PER_CPU(unsigned long [IRQ_STACK_SIZE/sizeof(long)], irq_stack) __aligned(16); + int arch_show_interrupts(struct seq_file *p, int prec) { show_ipi_list(p, prec); diff -ruw linux-4.4.115/arch/arm64/kernel/Makefile linux-4.4.115-fbx/arch/arm64/kernel/Makefile --- linux-4.4.115/arch/arm64/kernel/Makefile 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/arch/arm64/kernel/Makefile 2019-01-22 16:16:21.547228694 +0100 @@ -14,10 +14,10 @@ arm64-obj-y := debug-monitors.o entry.o irq.o fpsimd.o \ entry-fpsimd.o process.o ptrace.o setup.o signal.o \ sys.o stacktrace.o time.o traps.o io.o vdso.o \ - hyp-stub.o psci.o psci-call.o cpu_ops.o insn.o \ + hyp-stub.o psci.o cpu_ops.o insn.o \ return_address.o cpuinfo.o cpu_errata.o \ cpufeature.o alternative.o cacheinfo.o \ - smp.o smp_spin_table.o topology.o + smp.o smp_spin_table.o topology.o smccc-call.o extra-$(CONFIG_EFI) := efi-entry.o @@ -26,12 +26,13 @@ $(call if_changed,objcopy) arm64-obj-$(CONFIG_COMPAT) += sys32.o kuser32.o signal32.o \ - sys_compat.o entry32.o \ - ../../arm/kernel/opcodes.o + sys_compat.o entry32.o arm64-obj-$(CONFIG_FUNCTION_TRACER) += ftrace.o entry-ftrace.o arm64-obj-$(CONFIG_MODULES) += arm64ksyms.o module.o +arm64-obj-$(CONFIG_ARM64_MODULE_PLTS) += module-plts.o arm64-obj-$(CONFIG_PERF_EVENTS) += perf_regs.o perf_callchain.o -arm64-obj-$(CONFIG_HW_PERF_EVENTS) += perf_event.o +arm64-obj-$(CONFIG_HW_PERF_EVENTS) += perf_debug.o perf_trace_counters.o \ + perf_trace_user.o arm64-obj-$(CONFIG_HAVE_HW_BREAKPOINT) += hw_breakpoint.o arm64-obj-$(CONFIG_CPU_PM) += sleep.o suspend.o arm64-obj-$(CONFIG_CPU_IDLE) += cpuidle.o @@ -41,12 +42,18 @@ arm64-obj-$(CONFIG_PCI) += pci.o arm64-obj-$(CONFIG_ARMV8_DEPRECATED) += armv8_deprecated.o arm64-obj-$(CONFIG_ACPI) += acpi.o +arm64-obj-$(CONFIG_RANDOMIZE_BASE) += kaslr.o +arm64-obj-$(CONFIG_MSM_APP_API) += app_api.o +arm64-obj-$(CONFIG_MSM_APP_SETTINGS) += app_setting.o +arm64-obj-$(CONFIG_HIBERNATION) += hibernate.o hibernate-asm.o +arm64-obj-$(CONFIG_ARM64_ACPI_PARKING_PROTOCOL) += acpi_parking_protocol.o +arm64-obj-$(CONFIG_PARAVIRT) += paravirt.o -obj-y += $(arm64-obj-y) vdso/ +ifeq ($(CONFIG_KVM),y) +arm64-obj-$(CONFIG_HARDEN_BRANCH_PREDICTOR) += bpi.o +endif + +obj-y += $(arm64-obj-y) vdso/ probes/ obj-m += $(arm64-obj-m) head-y := head.o extra-y += $(head-y) vmlinux.lds - -# vDSO - this must be built first to generate the symbol offsets -$(call objectify,$(arm64-obj-y)): $(obj)/vdso/vdso-offsets.h -$(obj)/vdso/vdso-offsets.h: $(obj)/vdso diff -ruw linux-4.4.115/arch/arm64/kernel/module.c linux-4.4.115-fbx/arch/arm64/kernel/module.c --- linux-4.4.115/arch/arm64/kernel/module.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/arch/arm64/kernel/module.c 2019-10-29 09:26:23.005196935 +0100 @@ -30,17 +30,30 @@ #include #include -#define AARCH64_INSN_IMM_MOVNZ AARCH64_INSN_IMM_MAX -#define AARCH64_INSN_IMM_MOVK AARCH64_INSN_IMM_16 - void *module_alloc(unsigned long size) { void *p; - p = __vmalloc_node_range(size, MODULE_ALIGN, MODULES_VADDR, MODULES_END, + p = __vmalloc_node_range(size, MODULE_ALIGN, module_alloc_base, + module_alloc_base + MODULES_VSIZE, GFP_KERNEL, PAGE_KERNEL_EXEC, 0, NUMA_NO_NODE, __builtin_return_address(0)); + if (!p && IS_ENABLED(CONFIG_ARM64_MODULE_PLTS) && + !IS_ENABLED(CONFIG_KASAN)) + /* + * KASAN can only deal with module allocations being served + * from the reserved module region, since the remainder of + * the vmalloc region is already backed by zero shadow pages, + * and punching holes into it is non-trivial. Since the module + * region is not randomized when KASAN is enabled, it is even + * less likely that the module region gets exhausted, so we + * can simply omit this fallback in that case. + */ + p = __vmalloc_node_range(size, MODULE_ALIGN, VMALLOC_START, + VMALLOC_END, GFP_KERNEL, PAGE_KERNEL_EXEC, 0, + NUMA_NO_NODE, __builtin_return_address(0)); + if (p && (kasan_module_alloc(p, size) < 0)) { vfree(p); return NULL; @@ -75,15 +88,18 @@ static int reloc_data(enum aarch64_reloc_op op, void *place, u64 val, int len) { - u64 imm_mask = (1 << len) - 1; s64 sval = do_reloc(op, place, val); switch (len) { case 16: *(s16 *)place = sval; + if (sval < S16_MIN || sval > U16_MAX) + return -ERANGE; break; case 32: *(s32 *)place = sval; + if (sval < S32_MIN || sval > U32_MAX) + return -ERANGE; break; case 64: *(s64 *)place = sval; @@ -92,34 +108,23 @@ pr_err("Invalid length (%d) for data relocation\n", len); return 0; } - - /* - * Extract the upper value bits (including the sign bit) and - * shift them to bit 0. - */ - sval = (s64)(sval & ~(imm_mask >> 1)) >> (len - 1); - - /* - * Overflow has occurred if the value is not representable in - * len bits (i.e the bottom len bits are not sign-extended and - * the top bits are not all zero). - */ - if ((u64)(sval + 1) > 2) - return -ERANGE; - return 0; } +enum aarch64_insn_movw_imm_type { + AARCH64_INSN_IMM_MOVNZ, + AARCH64_INSN_IMM_MOVKZ, +}; + static int reloc_insn_movw(enum aarch64_reloc_op op, void *place, u64 val, - int lsb, enum aarch64_insn_imm_type imm_type) + int lsb, enum aarch64_insn_movw_imm_type imm_type) { - u64 imm, limit = 0; + u64 imm; s64 sval; u32 insn = le32_to_cpu(*(u32 *)place); sval = do_reloc(op, place, val); - sval >>= lsb; - imm = sval & 0xffff; + imm = sval >> lsb; if (imm_type == AARCH64_INSN_IMM_MOVNZ) { /* @@ -128,7 +133,7 @@ * immediate is less than zero. */ insn &= ~(3 << 29); - if ((s64)imm >= 0) { + if (sval >= 0) { /* >=0: Set the instruction to MOVZ (opcode 10b). */ insn |= 2 << 29; } else { @@ -140,29 +145,13 @@ */ imm = ~imm; } - imm_type = AARCH64_INSN_IMM_MOVK; } /* Update the instruction with the new encoding. */ - insn = aarch64_insn_encode_immediate(imm_type, insn, imm); + insn = aarch64_insn_encode_immediate(AARCH64_INSN_IMM_16, insn, imm); *(u32 *)place = cpu_to_le32(insn); - /* Shift out the immediate field. */ - sval >>= 16; - - /* - * For unsigned immediates, the overflow check is straightforward. - * For signed immediates, the sign bit is actually the bit past the - * most significant bit of the field. - * The AARCH64_INSN_IMM_16 immediate type is unsigned. - */ - if (imm_type != AARCH64_INSN_IMM_16) { - sval++; - limit++; - } - - /* Check the upper bits depending on the sign of the immediate. */ - if ((u64)sval > limit) + if (imm > U16_MAX) return -ERANGE; return 0; @@ -267,25 +256,25 @@ overflow_check = false; case R_AARCH64_MOVW_UABS_G0: ovf = reloc_insn_movw(RELOC_OP_ABS, loc, val, 0, - AARCH64_INSN_IMM_16); + AARCH64_INSN_IMM_MOVKZ); break; case R_AARCH64_MOVW_UABS_G1_NC: overflow_check = false; case R_AARCH64_MOVW_UABS_G1: ovf = reloc_insn_movw(RELOC_OP_ABS, loc, val, 16, - AARCH64_INSN_IMM_16); + AARCH64_INSN_IMM_MOVKZ); break; case R_AARCH64_MOVW_UABS_G2_NC: overflow_check = false; case R_AARCH64_MOVW_UABS_G2: ovf = reloc_insn_movw(RELOC_OP_ABS, loc, val, 32, - AARCH64_INSN_IMM_16); + AARCH64_INSN_IMM_MOVKZ); break; case R_AARCH64_MOVW_UABS_G3: /* We're using the top bits so we can't overflow. */ overflow_check = false; ovf = reloc_insn_movw(RELOC_OP_ABS, loc, val, 48, - AARCH64_INSN_IMM_16); + AARCH64_INSN_IMM_MOVKZ); break; case R_AARCH64_MOVW_SABS_G0: ovf = reloc_insn_movw(RELOC_OP_ABS, loc, val, 0, @@ -302,7 +291,7 @@ case R_AARCH64_MOVW_PREL_G0_NC: overflow_check = false; ovf = reloc_insn_movw(RELOC_OP_PREL, loc, val, 0, - AARCH64_INSN_IMM_MOVK); + AARCH64_INSN_IMM_MOVKZ); break; case R_AARCH64_MOVW_PREL_G0: ovf = reloc_insn_movw(RELOC_OP_PREL, loc, val, 0, @@ -311,7 +300,7 @@ case R_AARCH64_MOVW_PREL_G1_NC: overflow_check = false; ovf = reloc_insn_movw(RELOC_OP_PREL, loc, val, 16, - AARCH64_INSN_IMM_MOVK); + AARCH64_INSN_IMM_MOVKZ); break; case R_AARCH64_MOVW_PREL_G1: ovf = reloc_insn_movw(RELOC_OP_PREL, loc, val, 16, @@ -320,7 +309,7 @@ case R_AARCH64_MOVW_PREL_G2_NC: overflow_check = false; ovf = reloc_insn_movw(RELOC_OP_PREL, loc, val, 32, - AARCH64_INSN_IMM_MOVK); + AARCH64_INSN_IMM_MOVKZ); break; case R_AARCH64_MOVW_PREL_G2: ovf = reloc_insn_movw(RELOC_OP_PREL, loc, val, 32, @@ -388,6 +377,13 @@ case R_AARCH64_CALL26: ovf = reloc_insn_imm(RELOC_OP_PREL, loc, val, 2, 26, AARCH64_INSN_IMM_26); + + if (IS_ENABLED(CONFIG_ARM64_MODULE_PLTS) && + ovf == -ERANGE) { + val = module_emit_plt_entry(me, &rel[i], sym); + ovf = reloc_insn_imm(RELOC_OP_PREL, loc, val, 2, + 26, AARCH64_INSN_IMM_26); + } break; default: diff -ruw linux-4.4.115/arch/arm64/kernel/perf_callchain.c linux-4.4.115-fbx/arch/arm64/kernel/perf_callchain.c --- linux-4.4.115/arch/arm64/kernel/perf_callchain.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/arch/arm64/kernel/perf_callchain.c 2019-01-22 16:16:21.551228730 +0100 @@ -164,8 +164,11 @@ frame.fp = regs->regs[29]; frame.sp = regs->sp; frame.pc = regs->pc; +#ifdef CONFIG_FUNCTION_GRAPH_TRACER + frame.graph = current->curr_ret_stack; +#endif - walk_stackframe(&frame, callchain_trace, entry); + walk_stackframe(current, &frame, callchain_trace, entry); } unsigned long perf_instruction_pointer(struct pt_regs *regs) diff -ruw linux-4.4.115/arch/arm64/kernel/process.c linux-4.4.115-fbx/arch/arm64/kernel/process.c --- linux-4.4.115/arch/arm64/kernel/process.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/arch/arm64/kernel/process.c 2019-10-29 09:26:23.005196935 +0100 @@ -45,9 +45,14 @@ #include #include #include +#ifdef CONFIG_THREAD_INFO_IN_TASK +#include +#endif +#include #include #include +#include #include #include #include @@ -82,6 +87,16 @@ trace_cpu_idle_rcuidle(PWR_EVENT_EXIT, smp_processor_id()); } +void arch_cpu_idle_enter(void) +{ + idle_notifier_call_chain(IDLE_START); +} + +void arch_cpu_idle_exit(void) +{ + idle_notifier_call_chain(IDLE_END); +} + #ifdef CONFIG_HOTPLUG_CPU void arch_cpu_idle_dead(void) { @@ -164,6 +179,64 @@ while (1); } +/* + * dump a block of kernel memory from around the given address + */ +static void show_data(unsigned long addr, int nbytes, const char *name) +{ + int i, j; + int nlines; + u32 *p; + + /* + * don't attempt to dump non-kernel addresses or + * values that are probably just small negative numbers + */ + if (addr < KIMAGE_VADDR || addr > -256UL) + return; + + printk("\n%s: %#lx:\n", name, addr); + + /* + * round address down to a 32 bit boundary + * and always dump a multiple of 32 bytes + */ + p = (u32 *)(addr & ~(sizeof(u32) - 1)); + nbytes += (addr & (sizeof(u32) - 1)); + nlines = (nbytes + 31) / 32; + + + for (i = 0; i < nlines; i++) { + /* + * just display low 16 bits of address to keep + * each line of the dump < 80 characters + */ + printk("%04lx ", (unsigned long)p & 0xffff); + for (j = 0; j < 8; j++) { + u32 data; + if (probe_kernel_address(p, data)) { + printk(" ********"); + } else { + pr_cont(" %08x", data); + } + ++p; + } + pr_cont("\n"); + } +} + +static void show_extra_register_data(struct pt_regs *regs, int nbytes) +{ + mm_segment_t fs; + + fs = get_fs(); + set_fs(KERNEL_DS); + show_data(regs->pc - nbytes, nbytes * 2, "PC"); + show_data(regs->regs[30] - nbytes, nbytes * 2, "LR"); + show_data(regs->sp - nbytes, nbytes * 2, "SP"); + set_fs(fs); +} + void __show_regs(struct pt_regs *regs) { int i, top_reg; @@ -190,6 +263,8 @@ if (i % 2 == 0) printk("\n"); } + if (!user_mode(regs)) + show_extra_register_data(regs, 64); printk("\n"); } @@ -289,6 +364,9 @@ } else { memset(childregs, 0, sizeof(struct pt_regs)); childregs->pstate = PSR_MODE_EL1h; + if (IS_ENABLED(CONFIG_ARM64_UAO) && + cpus_have_cap(ARM64_HAS_UAO)) + childregs->pstate |= PSR_UAO_BIT; p->thread.cpu_context.x19 = stack_start; p->thread.cpu_context.x20 = stk_sz; } @@ -302,20 +380,45 @@ static void tls_thread_switch(struct task_struct *next) { - unsigned long tpidr, tpidrro; + unsigned long tpidr; asm("mrs %0, tpidr_el0" : "=r" (tpidr)); *task_user_tls(current) = tpidr; - tpidr = *task_user_tls(next); - tpidrro = is_compat_thread(task_thread_info(next)) ? - next->thread.tp_value : 0; - - asm( - " msr tpidr_el0, %0\n" - " msr tpidrro_el0, %1" - : : "r" (tpidr), "r" (tpidrro)); + if (is_compat_thread(task_thread_info(next))) + write_sysreg(next->thread.tp_value, tpidrro_el0); + else if (!arm64_kernel_unmapped_at_el0()) + write_sysreg(0, tpidrro_el0); + + write_sysreg(*task_user_tls(next), tpidr_el0); +} + +/* Restore the UAO state depending on next's addr_limit */ +void uao_thread_switch(struct task_struct *next) +{ + if (IS_ENABLED(CONFIG_ARM64_UAO)) { + if (task_thread_info(next)->addr_limit == KERNEL_DS) + asm(ALTERNATIVE("nop", SET_PSTATE_UAO(1), ARM64_HAS_UAO)); + else + asm(ALTERNATIVE("nop", SET_PSTATE_UAO(0), ARM64_HAS_UAO)); + } +} + +#ifdef CONFIG_THREAD_INFO_IN_TASK +/* + * We store our current task in sp_el0, which is clobbered by userspace. Keep a + * shadow copy so that we can restore this upon entry from userspace. + * + * This is *only* for exception entry from EL0, and is not valid until we + * __switch_to() a user task. + */ +DEFINE_PER_CPU(struct task_struct *, __entry_task); + +static void entry_task_switch(struct task_struct *next) +{ + __this_cpu_write(__entry_task, next); } +#endif /* * Thread switching. @@ -329,6 +432,10 @@ tls_thread_switch(next); hw_breakpoint_thread_switch(next); contextidr_thread_switch(next); +#ifdef CONFIG_THREAD_INFO_IN_TASK + entry_task_switch(next); +#endif + uao_thread_switch(next); /* * Complete any pending TLB or cache maintenance on this CPU in case @@ -345,24 +452,35 @@ unsigned long get_wchan(struct task_struct *p) { struct stackframe frame; - unsigned long stack_page; + unsigned long stack_page, ret = 0; int count = 0; if (!p || p == current || p->state == TASK_RUNNING) return 0; + stack_page = (unsigned long)try_get_task_stack(p); + if (!stack_page) + return 0; + frame.fp = thread_saved_fp(p); frame.sp = thread_saved_sp(p); frame.pc = thread_saved_pc(p); - stack_page = (unsigned long)task_stack_page(p); +#ifdef CONFIG_FUNCTION_GRAPH_TRACER + frame.graph = p->curr_ret_stack; +#endif do { if (frame.sp < stack_page || frame.sp >= stack_page + THREAD_SIZE || - unwind_frame(&frame)) - return 0; - if (!in_sched_functions(frame.pc)) - return frame.pc; + unwind_frame(p, &frame)) + goto out; + if (!in_sched_functions(frame.pc)) { + ret = frame.pc; + goto out; + } } while (count ++ < 16); - return 0; + +out: + put_task_stack(p); + return ret; } unsigned long arch_align_stack(unsigned long sp) diff -ruw linux-4.4.115/arch/arm64/kernel/psci.c linux-4.4.115-fbx/arch/arm64/kernel/psci.c --- linux-4.4.115/arch/arm64/kernel/psci.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/arch/arm64/kernel/psci.c 2019-01-22 16:16:21.551228730 +0100 @@ -19,8 +19,8 @@ #include #include #include +#include #include -#include #include @@ -28,76 +28,10 @@ #include #include #include -#include - -static DEFINE_PER_CPU_READ_MOSTLY(u32 *, psci_power_state); - -static int __maybe_unused cpu_psci_cpu_init_idle(unsigned int cpu) -{ - int i, ret, count = 0; - u32 *psci_states; - struct device_node *state_node, *cpu_node; - - cpu_node = of_get_cpu_node(cpu, NULL); - if (!cpu_node) - return -ENODEV; - - /* - * If the PSCI cpu_suspend function hook has not been initialized - * idle states must not be enabled, so bail out - */ - if (!psci_ops.cpu_suspend) - return -EOPNOTSUPP; - - /* Count idle states */ - while ((state_node = of_parse_phandle(cpu_node, "cpu-idle-states", - count))) { - count++; - of_node_put(state_node); - } - - if (!count) - return -ENODEV; - - psci_states = kcalloc(count, sizeof(*psci_states), GFP_KERNEL); - if (!psci_states) - return -ENOMEM; - - for (i = 0; i < count; i++) { - u32 state; - - state_node = of_parse_phandle(cpu_node, "cpu-idle-states", i); - - ret = of_property_read_u32(state_node, - "arm,psci-suspend-param", - &state); - if (ret) { - pr_warn(" * %s missing arm,psci-suspend-param property\n", - state_node->full_name); - of_node_put(state_node); - goto free_mem; - } - - of_node_put(state_node); - pr_debug("psci-power-state %#x index %d\n", state, i); - if (!psci_power_state_is_valid(state)) { - pr_warn("Invalid PSCI power state %#x\n", state); - ret = -EINVAL; - goto free_mem; - } - psci_states[i] = state; - } - /* Idle states parsed correctly, initialize per-cpu pointer */ - per_cpu(psci_power_state, cpu) = psci_states; - return 0; - -free_mem: - kfree(psci_states); - return ret; -} static int __init cpu_psci_cpu_init(unsigned int cpu) { + pr_info("Initializing psci_cpu_init\n"); return 0; } @@ -113,7 +47,8 @@ static int cpu_psci_cpu_boot(unsigned int cpu) { - int err = psci_ops.cpu_on(cpu_logical_map(cpu), __pa(secondary_entry)); + int err = psci_ops.cpu_on(cpu_logical_map(cpu), + __pa_symbol(secondary_entry)); if (err) pr_err("failed to boot CPU%d (%d)\n", cpu, err); @@ -164,12 +99,12 @@ for (i = 0; i < 10; i++) { err = psci_ops.affinity_info(cpu_logical_map(cpu), 0); if (err == PSCI_0_2_AFFINITY_LEVEL_OFF) { - pr_info("CPU%d killed.\n", cpu); + pr_debug("CPU%d killed.\n", cpu); return 0; } msleep(10); - pr_info("Retrying again to check for CPU kill\n"); + pr_debug("Retrying again to check for CPU kill\n"); } pr_warn("CPU%d may not have shut down cleanly (AFFINITY_INFO reports %d)\n", @@ -178,38 +113,11 @@ } #endif -static int psci_suspend_finisher(unsigned long index) -{ - u32 *state = __this_cpu_read(psci_power_state); - - return psci_ops.cpu_suspend(state[index - 1], - virt_to_phys(cpu_resume)); -} - -static int __maybe_unused cpu_psci_cpu_suspend(unsigned long index) -{ - int ret; - u32 *state = __this_cpu_read(psci_power_state); - /* - * idle state index 0 corresponds to wfi, should never be called - * from the cpu_suspend operations - */ - if (WARN_ON_ONCE(!index)) - return -EINVAL; - - if (!psci_power_state_loses_context(state[index - 1])) - ret = psci_ops.cpu_suspend(state[index - 1], 0); - else - ret = cpu_suspend(index, psci_suspend_finisher); - - return ret; -} - const struct cpu_operations cpu_psci_ops = { .name = "psci", #ifdef CONFIG_CPU_IDLE - .cpu_init_idle = cpu_psci_cpu_init_idle, - .cpu_suspend = cpu_psci_cpu_suspend, + .cpu_init_idle = psci_cpu_init_idle, + .cpu_suspend = psci_cpu_suspend_enter, #endif .cpu_init = cpu_psci_cpu_init, .cpu_prepare = cpu_psci_cpu_prepare, diff -ruw linux-4.4.115/arch/arm64/kernel/ptrace.c linux-4.4.115-fbx/arch/arm64/kernel/ptrace.c --- linux-4.4.115/arch/arm64/kernel/ptrace.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/arch/arm64/kernel/ptrace.c 2019-10-29 09:26:23.005196935 +0100 @@ -49,6 +49,106 @@ #define CREATE_TRACE_POINTS #include +struct pt_regs_offset { + const char *name; + int offset; +}; + +#define REG_OFFSET_NAME(r) {.name = #r, .offset = offsetof(struct pt_regs, r)} +#define REG_OFFSET_END {.name = NULL, .offset = 0} +#define GPR_OFFSET_NAME(r) \ + {.name = "x" #r, .offset = offsetof(struct pt_regs, regs[r])} + +static const struct pt_regs_offset regoffset_table[] = { + GPR_OFFSET_NAME(0), + GPR_OFFSET_NAME(1), + GPR_OFFSET_NAME(2), + GPR_OFFSET_NAME(3), + GPR_OFFSET_NAME(4), + GPR_OFFSET_NAME(5), + GPR_OFFSET_NAME(6), + GPR_OFFSET_NAME(7), + GPR_OFFSET_NAME(8), + GPR_OFFSET_NAME(9), + GPR_OFFSET_NAME(10), + GPR_OFFSET_NAME(11), + GPR_OFFSET_NAME(12), + GPR_OFFSET_NAME(13), + GPR_OFFSET_NAME(14), + GPR_OFFSET_NAME(15), + GPR_OFFSET_NAME(16), + GPR_OFFSET_NAME(17), + GPR_OFFSET_NAME(18), + GPR_OFFSET_NAME(19), + GPR_OFFSET_NAME(20), + GPR_OFFSET_NAME(21), + GPR_OFFSET_NAME(22), + GPR_OFFSET_NAME(23), + GPR_OFFSET_NAME(24), + GPR_OFFSET_NAME(25), + GPR_OFFSET_NAME(26), + GPR_OFFSET_NAME(27), + GPR_OFFSET_NAME(28), + GPR_OFFSET_NAME(29), + GPR_OFFSET_NAME(30), + {.name = "lr", .offset = offsetof(struct pt_regs, regs[30])}, + REG_OFFSET_NAME(sp), + REG_OFFSET_NAME(pc), + REG_OFFSET_NAME(pstate), + REG_OFFSET_END, +}; + +/** + * regs_query_register_offset() - query register offset from its name + * @name: the name of a register + * + * regs_query_register_offset() returns the offset of a register in struct + * pt_regs from its name. If the name is invalid, this returns -EINVAL; + */ +int regs_query_register_offset(const char *name) +{ + const struct pt_regs_offset *roff; + + for (roff = regoffset_table; roff->name != NULL; roff++) + if (!strcmp(roff->name, name)) + return roff->offset; + return -EINVAL; +} + +/** + * regs_within_kernel_stack() - check the address in the stack + * @regs: pt_regs which contains kernel stack pointer. + * @addr: address which is checked. + * + * regs_within_kernel_stack() checks @addr is within the kernel stack page(s). + * If @addr is within the kernel stack, it returns true. If not, returns false. + */ +static bool regs_within_kernel_stack(struct pt_regs *regs, unsigned long addr) +{ + return ((addr & ~(THREAD_SIZE - 1)) == + (kernel_stack_pointer(regs) & ~(THREAD_SIZE - 1))); +} + +/** + * regs_get_kernel_stack_nth() - get Nth entry of the stack + * @regs: pt_regs which contains kernel stack pointer. + * @n: stack entry number. + * + * regs_get_kernel_stack_nth() returns @n th entry of the kernel stack which + * is specified by @regs. If the @n th entry is NOT in the kernel stack, + * this returns 0. + */ +unsigned long regs_get_kernel_stack_nth(struct pt_regs *regs, unsigned int n) +{ + unsigned long *addr = (unsigned long *)kernel_stack_pointer(regs); + + addr += n; + if (regs_within_kernel_stack(regs, (unsigned long)addr)) + return *addr; + else + return 0; +} + /* * TODO: does not yet catch signals sent when the child dies. * in exit.c or in signal.c. @@ -227,13 +327,13 @@ struct arch_hw_breakpoint_ctrl ctrl, struct perf_event_attr *attr) { - int err, len, type, disabled = !ctrl.enabled; + int err, len, type, offset, disabled = !ctrl.enabled; attr->disabled = disabled; if (disabled) return 0; - err = arch_bp_generic_fields(ctrl, &len, &type); + err = arch_bp_generic_fields(ctrl, &len, &type, &offset); if (err) return err; @@ -252,6 +352,7 @@ attr->bp_len = len; attr->bp_type = type; + attr->bp_addr += offset; return 0; } @@ -304,7 +405,7 @@ if (IS_ERR(bp)) return PTR_ERR(bp); - *addr = bp ? bp->attr.bp_addr : 0; + *addr = bp ? counter_arch_bp(bp)->address : 0; return 0; } diff -ruw linux-4.4.115/arch/arm64/kernel/return_address.c linux-4.4.115-fbx/arch/arm64/kernel/return_address.c --- linux-4.4.115/arch/arm64/kernel/return_address.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/arch/arm64/kernel/return_address.c 2019-01-22 16:16:21.555228766 +0100 @@ -12,6 +12,7 @@ #include #include +#include #include struct return_address_data { @@ -43,8 +44,11 @@ frame.fp = (unsigned long)__builtin_frame_address(0); frame.sp = current_stack_pointer; frame.pc = (unsigned long)return_address; /* dummy */ +#ifdef CONFIG_FUNCTION_GRAPH_TRACER + frame.graph = current->curr_ret_stack; +#endif - walk_stackframe(&frame, save_return_addr, &data); + walk_stackframe(current, &frame, save_return_addr, &data); if (!data.level) return data.addr; diff -ruw linux-4.4.115/arch/arm64/kernel/setup.c linux-4.4.115-fbx/arch/arm64/kernel/setup.c --- linux-4.4.115/arch/arm64/kernel/setup.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/arch/arm64/kernel/setup.c 2019-01-22 16:16:21.555228766 +0100 @@ -44,6 +44,8 @@ #include #include #include +#include +#include #include #include @@ -62,9 +64,17 @@ #include #include #include +#include + +unsigned int boot_reason; +EXPORT_SYMBOL(boot_reason); + +unsigned int cold_boot; +EXPORT_SYMBOL(cold_boot); phys_addr_t __fdt_pointer __initdata; +const char *machine_name; /* * Standard memory resources */ @@ -174,7 +184,6 @@ */ if (mpidr_hash_size() > 4 * num_possible_cpus()) pr_warn("Large number of MPIDR hash buckets detected\n"); - __flush_dcache_area(&mpidr_hash, sizeof(struct mpidr_hash)); } static void __init setup_machine_fdt(phys_addr_t dt_phys) @@ -192,7 +201,11 @@ cpu_relax(); } - dump_stack_set_arch_desc("%s (DT)", of_flat_dt_get_machine_name()); + machine_name = of_flat_dt_get_machine_name(); + if (machine_name) { + dump_stack_set_arch_desc("%s (DT)", machine_name); + pr_info("Machine: %s\n", machine_name); + } } static void __init request_standard_resources(void) @@ -200,10 +213,10 @@ struct memblock_region *region; struct resource *res; - kernel_code.start = virt_to_phys(_text); - kernel_code.end = virt_to_phys(_etext - 1); - kernel_data.start = virt_to_phys(_sdata); - kernel_data.end = virt_to_phys(_end - 1); + kernel_code.start = __pa_symbol(_text); + kernel_code.end = __pa_symbol(__init_begin - 1); + kernel_data.start = __pa_symbol(_sdata); + kernel_data.end = __pa_symbol(_end - 1); for_each_memblock(memory, region) { res = alloc_bootmem_low(sizeof(*res)); @@ -288,6 +301,8 @@ u64 __cpu_logical_map[NR_CPUS] = { [0 ... NR_CPUS-1] = INVALID_HWID }; +void __init __weak init_random_pool(void) { } + void __init setup_arch(char **cmdline_p) { pr_info("Boot CPU: AArch64 Processor [%08x]\n", read_cpuid_id()); @@ -313,6 +328,12 @@ */ local_async_enable(); + /* + * TTBR0 is only used for the identity mapping at this stage. Make it + * point to zero page to avoid speculatively fetching new entries. + */ + cpu_uninstall_idmap(); + efi_init(); arm64_memblock_init(); @@ -340,6 +361,19 @@ smp_init_cpus(); smp_build_mpidr_hash(); +#ifdef CONFIG_ARM64_SW_TTBR0_PAN + /* + * Make sure thread_info.ttbr0 always generates translation + * faults in case uaccess_enable() is inadvertently called by the init + * thread. + */ +#ifdef CONFIG_THREAD_INFO_IN_TASK + init_task.thread_info.ttbr0 = __pa_symbol(empty_zero_page); +#else + init_thread_info.ttbr0 = __pa_symbol(empty_zero_page); +#endif +#endif + #ifdef CONFIG_VT #if defined(CONFIG_VGA_CONSOLE) conswitchp = &vga_con; @@ -347,6 +381,7 @@ conswitchp = &dummy_con; #endif #endif + init_random_pool(); if (boot_args[1] || boot_args[2] || boot_args[3]) { pr_err("WARNING: x1-x3 nonzero in violation of boot protocol:\n" "\tx1: %016llx\n\tx2: %016llx\n\tx3: %016llx\n" @@ -380,4 +415,39 @@ return 0; } -subsys_initcall(topology_init); +postcore_initcall(topology_init); + +void arch_setup_pdev_archdata(struct platform_device *pdev) +{ + pdev->archdata.dma_mask = DMA_BIT_MASK(32); + pdev->dev.dma_mask = &pdev->archdata.dma_mask; +} + +/* + * Dump out kernel offset information on panic. + */ +static int dump_kernel_offset(struct notifier_block *self, unsigned long v, + void *p) +{ + const unsigned long offset = kaslr_offset(); + + if (IS_ENABLED(CONFIG_RANDOMIZE_BASE) && offset > 0) { + pr_emerg("Kernel Offset: 0x%lx from 0x%lx\n", + offset, KIMAGE_VADDR); + } else { + pr_emerg("Kernel Offset: disabled\n"); + } + return 0; +} + +static struct notifier_block kernel_offset_notifier = { + .notifier_call = dump_kernel_offset +}; + +static int __init register_kernel_offset_dumper(void) +{ + atomic_notifier_chain_register(&panic_notifier_list, + &kernel_offset_notifier); + return 0; +} +__initcall(register_kernel_offset_dumper); diff -ruw linux-4.4.115/arch/arm64/kernel/sleep.S linux-4.4.115-fbx/arch/arm64/kernel/sleep.S --- linux-4.4.115/arch/arm64/kernel/sleep.S 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/arch/arm64/kernel/sleep.S 2019-10-29 09:26:23.005196935 +0100 @@ -49,39 +49,32 @@ orr \dst, \dst, \mask // dst|=(aff3>>rs3) .endm /* - * Save CPU state for a suspend and execute the suspend finisher. - * On success it will return 0 through cpu_resume - ie through a CPU - * soft/hard reboot from the reset vector. - * On failure it returns the suspend finisher return value or force - * -EOPNOTSUPP if the finisher erroneously returns 0 (the suspend finisher - * is not allowed to return, if it does this must be considered failure). - * It saves callee registers, and allocates space on the kernel stack - * to save the CPU specific registers + some other data for resume. + * Save CPU state in the provided sleep_stack_data area, and publish its + * location for cpu_resume()'s use in sleep_save_stash. * - * x0 = suspend finisher argument - * x1 = suspend finisher function pointer + * cpu_resume() will restore this saved state, and return. Because the + * link-register is saved and restored, it will appear to return from this + * function. So that the caller can tell the suspend/resume paths apart, + * __cpu_suspend_enter() will always return a non-zero value, whereas the + * path through cpu_resume() will return 0. + * + * x0 = struct sleep_stack_data area */ ENTRY(__cpu_suspend_enter) - stp x29, lr, [sp, #-96]! - stp x19, x20, [sp,#16] - stp x21, x22, [sp,#32] - stp x23, x24, [sp,#48] - stp x25, x26, [sp,#64] - stp x27, x28, [sp,#80] - /* - * Stash suspend finisher and its argument in x20 and x19 - */ - mov x19, x0 - mov x20, x1 + stp x29, lr, [x0, #SLEEP_STACK_DATA_CALLEE_REGS] + stp x19, x20, [x0,#SLEEP_STACK_DATA_CALLEE_REGS+16] + stp x21, x22, [x0,#SLEEP_STACK_DATA_CALLEE_REGS+32] + stp x23, x24, [x0,#SLEEP_STACK_DATA_CALLEE_REGS+48] + stp x25, x26, [x0,#SLEEP_STACK_DATA_CALLEE_REGS+64] + stp x27, x28, [x0,#SLEEP_STACK_DATA_CALLEE_REGS+80] + + /* save the sp in cpu_suspend_ctx */ mov x2, sp - sub sp, sp, #CPU_SUSPEND_SZ // allocate cpu_suspend_ctx - mov x0, sp - /* - * x0 now points to struct cpu_suspend_ctx allocated on the stack - */ - str x2, [x0, #CPU_CTX_SP] - ldr x1, =sleep_save_sp - ldr x1, [x1, #SLEEP_SAVE_SP_VIRT] + str x2, [x0, #SLEEP_STACK_DATA_SYSTEM_REGS + CPU_CTX_SP] + + /* find the mpidr_hash */ + ldr x1, =sleep_save_stash + ldr x1, [x1] mrs x7, mpidr_el1 ldr x9, =mpidr_hash ldr x10, [x9, #MPIDR_HASH_MASK] @@ -93,70 +86,28 @@ ldp w5, w6, [x9, #(MPIDR_HASH_SHIFTS + 8)] compute_mpidr_hash x8, x3, x4, x5, x6, x7, x10 add x1, x1, x8, lsl #3 - bl __cpu_suspend_save - /* - * Grab suspend finisher in x20 and its argument in x19 - */ - mov x0, x19 - mov x1, x20 - /* - * We are ready for power down, fire off the suspend finisher - * in x1, with argument in x0 - */ - blr x1 - /* - * Never gets here, unless suspend finisher fails. - * Successful cpu_suspend should return from cpu_resume, returning - * through this code path is considered an error - * If the return value is set to 0 force x0 = -EOPNOTSUPP - * to make sure a proper error condition is propagated - */ - cmp x0, #0 - mov x3, #-EOPNOTSUPP - csel x0, x3, x0, eq - add sp, sp, #CPU_SUSPEND_SZ // rewind stack pointer - ldp x19, x20, [sp, #16] - ldp x21, x22, [sp, #32] - ldp x23, x24, [sp, #48] - ldp x25, x26, [sp, #64] - ldp x27, x28, [sp, #80] - ldp x29, lr, [sp], #96 + + str x0, [x1] + add x0, x0, #SLEEP_STACK_DATA_SYSTEM_REGS + stp x29, lr, [sp, #-16]! + bl cpu_do_suspend + ldp x29, lr, [sp], #16 + mov x0, #1 ret ENDPROC(__cpu_suspend_enter) .ltorg -/* - * x0 must contain the sctlr value retrieved from restored context - */ - .pushsection ".idmap.text", "ax" -ENTRY(cpu_resume_mmu) - ldr x3, =cpu_resume_after_mmu - msr sctlr_el1, x0 // restore sctlr_el1 - isb - /* - * Invalidate the local I-cache so that any instructions fetched - * speculatively from the PoC are discarded, since they may have - * been dynamically patched at the PoU. - */ - ic iallu - dsb nsh - isb - br x3 // global jump to virtual address -ENDPROC(cpu_resume_mmu) - .popsection -cpu_resume_after_mmu: - mov x0, #0 // return zero on success - ldp x19, x20, [sp, #16] - ldp x21, x22, [sp, #32] - ldp x23, x24, [sp, #48] - ldp x25, x26, [sp, #64] - ldp x27, x28, [sp, #80] - ldp x29, lr, [sp], #96 - ret -ENDPROC(cpu_resume_after_mmu) - ENTRY(cpu_resume) bl el2_setup // if in EL2 drop to EL1 cleanly + /* enable the MMU early - so we can access sleep_save_stash by va */ + adr_l lr, __enable_mmu /* __cpu_setup will return here */ + ldr x27, =_cpu_resume /* __enable_mmu will branch here */ + adrp x25, idmap_pg_dir + adrp x26, swapper_pg_dir + b __cpu_setup +ENDPROC(cpu_resume) + +ENTRY(_cpu_resume) mrs x1, mpidr_el1 adrp x8, mpidr_hash add x8, x8, #:lo12:mpidr_hash // x8 = struct mpidr_hash phys address @@ -166,17 +117,29 @@ ldp w5, w6, [x8, #(MPIDR_HASH_SHIFTS + 8)] compute_mpidr_hash x7, x3, x4, x5, x6, x1, x2 /* x7 contains hash index, let's use it to grab context pointer */ - ldr_l x0, sleep_save_sp + SLEEP_SAVE_SP_PHYS + ldr_l x0, sleep_save_stash ldr x0, [x0, x7, lsl #3] + add x29, x0, #SLEEP_STACK_DATA_CALLEE_REGS + add x0, x0, #SLEEP_STACK_DATA_SYSTEM_REGS /* load sp from context */ ldr x2, [x0, #CPU_CTX_SP] - /* load physical address of identity map page table in x1 */ - adrp x1, idmap_pg_dir mov sp, x2 /* - * cpu_do_resume expects x0 to contain context physical address - * pointer and x1 to contain physical address of 1:1 page tables + * cpu_do_resume expects x0 to contain context address pointer */ - bl cpu_do_resume // PC relative jump, MMU off - b cpu_resume_mmu // Resume MMU, never returns -ENDPROC(cpu_resume) + bl cpu_do_resume + +#ifdef CONFIG_KASAN + mov x0, sp + bl kasan_unpoison_task_stack_below +#endif + + ldp x19, x20, [x29, #16] + ldp x21, x22, [x29, #32] + ldp x23, x24, [x29, #48] + ldp x25, x26, [x29, #64] + ldp x27, x28, [x29, #80] + ldp x29, lr, [x29] + mov x0, #0 + ret +ENDPROC(_cpu_resume) diff -ruw linux-4.4.115/arch/arm64/kernel/smp.c linux-4.4.115-fbx/arch/arm64/kernel/smp.c --- linux-4.4.115/arch/arm64/kernel/smp.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/arch/arm64/kernel/smp.c 2019-10-29 09:26:23.005196935 +0100 @@ -53,10 +53,15 @@ #include #include #include +#include +#include #define CREATE_TRACE_POINTS #include +DEFINE_PER_CPU_READ_MOSTLY(int, cpu_number); +EXPORT_PER_CPU_SYMBOL(cpu_number); + /* * as from 2.5, kernels no longer have an init_tasks structure * so we need some other way of telling a new secondary core @@ -70,6 +75,8 @@ IPI_CPU_STOP, IPI_TIMER, IPI_IRQ_WORK, + IPI_WAKEUP, + IPI_CPU_BACKTRACE, }; /* @@ -94,6 +101,9 @@ * We need to tell the secondary core where to find its stack and the * page tables. */ +#ifdef CONFIG_THREAD_INFO_IN_TASK + secondary_data.task = idle; +#endif secondary_data.stack = task_stack_page(idle) + THREAD_START_SP; __flush_dcache_area(&secondary_data, sizeof(secondary_data)); @@ -117,6 +127,9 @@ pr_err("CPU%u: failed to boot: %d\n", cpu, ret); } +#ifdef CONFIG_THREAD_INFO_IN_TASK + secondary_data.task = NULL; +#endif secondary_data.stack = NULL; return ret; @@ -134,7 +147,12 @@ asmlinkage void secondary_start_kernel(void) { struct mm_struct *mm = &init_mm; - unsigned int cpu = smp_processor_id(); + unsigned int cpu; + + cpu = task_cpu(current); + set_my_cpu_offset(per_cpu_offset(cpu)); + + pr_debug("CPU%u: Booted secondary processor\n", cpu); /* * All kernel threads share the same mm context; grab a @@ -143,15 +161,11 @@ atomic_inc(&mm->mm_count); current->active_mm = mm; - set_my_cpu_offset(per_cpu_offset(smp_processor_id())); - /* * TTBR0 is only used for the identity mapping at this stage. Make it * point to zero page to avoid speculatively fetching new entries. */ - cpu_set_reserved_ttbr0(); - local_flush_tlb_all(); - cpu_set_default_tcr_t0sz(); + cpu_uninstall_idmap(); preempt_disable(); trace_hardirqs_off(); @@ -174,10 +188,10 @@ /* * Enable GIC and timers. */ - notify_cpu_starting(cpu); - smp_store_cpu_info(cpu); + notify_cpu_starting(cpu); + /* * OK, now it's safe to let the boot CPU continue. Wait for * the CPU migration code to notice that the CPU is online @@ -268,7 +282,7 @@ pr_crit("CPU%u: cpu didn't die\n", cpu); return; } - pr_notice("CPU%u: shutdown\n", cpu); + pr_debug("CPU%u: shutdown\n", cpu); /* * Now that the dying CPU is beyond the point of no return w.r.t. @@ -290,7 +304,7 @@ * of the other hotplug-cpu capable cores, so presumably coming * out of idle fixes this. */ -void cpu_die(void) +void __ref cpu_die(void) { unsigned int cpu = smp_processor_id(); @@ -308,7 +322,16 @@ */ cpu_ops[cpu]->cpu_die(cpu); - BUG(); + /* + * Do not return to the idle loop - jump back to the secondary + * cpu initialisation. There's some initialisation which needs + * to be repeated to undo the effects of taking the CPU offline. + */ + + asm volatile("mov sp, %0\n" + "mov x29, #0\n" + "b secondary_start_kernel" + : : "r" (task_stack_page(current) + THREAD_START_SP)); } #endif @@ -444,6 +467,17 @@ /* map the logical cpu id to cpu MPIDR */ cpu_logical_map(cpu_count) = hwid; + /* + * Set-up the ACPI parking protocol cpu entries + * while initializing the cpu_logical_map to + * avoid parsing MADT entries multiple times for + * nothing (ie a valid cpu_logical_map entry should + * contain a valid parking protocol data set to + * initialize the cpu if the parking protocol is + * the only available enable method). + */ + acpi_set_mailbox_entry(cpu_count, processor); + cpu_count++; } @@ -466,6 +500,18 @@ #else #define acpi_table_parse_madt(...) do { } while (0) #endif +void (*__smp_cross_call)(const struct cpumask *, unsigned int); +DEFINE_PER_CPU(bool, pending_ipi); + +void smp_cross_call_common(const struct cpumask *cpumask, unsigned int func) +{ + unsigned int cpu; + + for_each_cpu(cpu, cpumask) + per_cpu(pending_ipi, cpu) = true; + + __smp_cross_call(cpumask, func); +} /* * Enumerate the possible CPU set from the device tree and build the @@ -597,6 +643,8 @@ if (max_cpus == 0) break; + per_cpu(cpu_number, cpu) = cpu; + if (cpu == smp_processor_id()) continue; @@ -612,8 +660,6 @@ } } -void (*__smp_cross_call)(const struct cpumask *, unsigned int); - void __init set_smp_cross_call(void (*fn)(const struct cpumask *, unsigned int)) { __smp_cross_call = fn; @@ -626,10 +672,17 @@ S(IPI_CPU_STOP, "CPU stop interrupts"), S(IPI_TIMER, "Timer broadcast interrupts"), S(IPI_IRQ_WORK, "IRQ work interrupts"), + S(IPI_WAKEUP, "CPU wakeup interrupts"), + S(IPI_CPU_BACKTRACE, "CPU backtrace"), }; static void smp_cross_call(const struct cpumask *target, unsigned int ipinr) { + unsigned int cpu; + + for_each_cpu(cpu, target) + per_cpu(pending_ipi, cpu) = true; + trace_ipi_raise(target, ipi_types[ipinr]); __smp_cross_call(target, ipinr); } @@ -661,14 +714,21 @@ void arch_send_call_function_ipi_mask(const struct cpumask *mask) { - smp_cross_call(mask, IPI_CALL_FUNC); + smp_cross_call_common(mask, IPI_CALL_FUNC); } void arch_send_call_function_single_ipi(int cpu) { - smp_cross_call(cpumask_of(cpu), IPI_CALL_FUNC); + smp_cross_call_common(cpumask_of(cpu), IPI_CALL_FUNC); } +#ifdef CONFIG_ARM64_ACPI_PARKING_PROTOCOL +void arch_send_wakeup_ipi_mask(const struct cpumask *mask) +{ + smp_cross_call(mask, IPI_WAKEUP); +} +#endif + #ifdef CONFIG_IRQ_WORK void arch_irq_work_raise(void) { @@ -677,29 +737,86 @@ } #endif -static DEFINE_RAW_SPINLOCK(stop_lock); - /* * ipi_cpu_stop - handle IPI from smp_send_stop() */ static void ipi_cpu_stop(unsigned int cpu) { - if (system_state == SYSTEM_BOOTING || - system_state == SYSTEM_RUNNING) { - raw_spin_lock(&stop_lock); - pr_crit("CPU%u: stopping\n", cpu); - dump_stack(); - raw_spin_unlock(&stop_lock); - } - - set_cpu_online(cpu, false); + set_cpu_active(cpu, false); + flush_cache_all(); local_irq_disable(); while (1) cpu_relax(); } +static cpumask_t backtrace_mask; +static DEFINE_RAW_SPINLOCK(backtrace_lock); + +/* "in progress" flag of arch_trigger_all_cpu_backtrace */ +static unsigned long backtrace_flag; + +static void smp_send_all_cpu_backtrace(void) +{ + unsigned int this_cpu = smp_processor_id(); + int i; + + if (test_and_set_bit(0, &backtrace_flag)) + /* + * If there is already a trigger_all_cpu_backtrace() in progress + * (backtrace_flag == 1), don't output double cpu dump infos. + */ + return; + + cpumask_copy(&backtrace_mask, cpu_online_mask); + cpumask_clear_cpu(this_cpu, &backtrace_mask); + + pr_info("Backtrace for cpu %d (current):\n", this_cpu); + dump_stack(); + + pr_info("\nsending IPI to all other CPUs:\n"); + if (!cpumask_empty(&backtrace_mask)) + smp_cross_call_common(&backtrace_mask, IPI_CPU_BACKTRACE); + + /* Wait for up to 10 seconds for all other CPUs to do the backtrace */ + for (i = 0; i < 10 * 1000; i++) { + if (cpumask_empty(&backtrace_mask)) + break; + mdelay(1); + } + + clear_bit(0, &backtrace_flag); + smp_mb__after_atomic(); +} + +/* + * ipi_cpu_backtrace - handle IPI from smp_send_all_cpu_backtrace() + */ +static void ipi_cpu_backtrace(unsigned int cpu, struct pt_regs *regs) +{ + if (cpumask_test_cpu(cpu, &backtrace_mask)) { + raw_spin_lock(&backtrace_lock); + pr_warn("IPI backtrace for cpu %d\n", cpu); + show_regs(regs); + raw_spin_unlock(&backtrace_lock); + cpumask_clear_cpu(cpu, &backtrace_mask); + } +} + +#ifdef CONFIG_SMP +void arch_trigger_all_cpu_backtrace(void) +{ + smp_send_all_cpu_backtrace(); +} +#else +void arch_trigger_all_cpu_backtrace(void) +{ + dump_stack(); +} +#endif + + /* * Main handler for inter-processor interrupts */ @@ -746,6 +863,18 @@ break; #endif + case IPI_CPU_BACKTRACE: + ipi_cpu_backtrace(cpu, regs); + break; + +#ifdef CONFIG_ARM64_ACPI_PARKING_PROTOCOL + case IPI_WAKEUP: + WARN_ONCE(!acpi_parking_protocol_valid(cpu), + "CPU%u: Wake-up IPI outside the ACPI parking protocol\n", + cpu); + break; +#endif + default: pr_crit("CPU%u: Unknown IPI message 0x%x\n", cpu, ipinr); break; @@ -753,18 +882,21 @@ if ((unsigned)ipinr < NR_IPI) trace_ipi_exit_rcuidle(ipi_types[ipinr]); + + per_cpu(pending_ipi, cpu) = false; set_irq_regs(old_regs); } void smp_send_reschedule(int cpu) { - smp_cross_call(cpumask_of(cpu), IPI_RESCHEDULE); + BUG_ON(cpu_is_offline(cpu)); + smp_cross_call_common(cpumask_of(cpu), IPI_RESCHEDULE); } #ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST void tick_broadcast(const struct cpumask *mask) { - smp_cross_call(mask, IPI_TIMER); + smp_cross_call_common(mask, IPI_TIMER); } #endif @@ -778,16 +910,20 @@ cpumask_copy(&mask, cpu_online_mask); cpumask_clear_cpu(smp_processor_id(), &mask); - smp_cross_call(&mask, IPI_CPU_STOP); + if (system_state == SYSTEM_BOOTING || + system_state == SYSTEM_RUNNING) + pr_crit("SMP: stopping secondary CPUs\n"); + smp_cross_call_common(&mask, IPI_CPU_STOP); } /* Wait up to one second for other CPUs to stop */ timeout = USEC_PER_SEC; - while (num_online_cpus() > 1 && timeout--) + while (num_active_cpus() > 1 && timeout--) udelay(1); - if (num_online_cpus() > 1) - pr_warning("SMP: failed to stop secondary CPUs\n"); + if (num_active_cpus() > 1) + pr_warning("SMP: failed to stop secondary CPUs %*pbl\n", + cpumask_pr_args(cpu_online_mask)); } /* diff -ruw linux-4.4.115/arch/arm64/kernel/smp_spin_table.c linux-4.4.115-fbx/arch/arm64/kernel/smp_spin_table.c --- linux-4.4.115/arch/arm64/kernel/smp_spin_table.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/arch/arm64/kernel/smp_spin_table.c 2019-10-29 09:26:23.005196935 +0100 @@ -21,6 +21,7 @@ #include #include #include +#include #include #include @@ -96,7 +97,7 @@ * boot-loader's endianess before jumping. This is mandated by * the boot protocol. */ - writeq_relaxed(__pa(secondary_holding_pen), release_addr); + writeq_relaxed(__pa_symbol(secondary_holding_pen), release_addr); __flush_dcache_area((__force void *)release_addr, sizeof(*release_addr)); diff -ruw linux-4.4.115/arch/arm64/kernel/stacktrace.c linux-4.4.115-fbx/arch/arm64/kernel/stacktrace.c --- linux-4.4.115/arch/arm64/kernel/stacktrace.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/arch/arm64/kernel/stacktrace.c 2019-01-22 16:16:21.555228766 +0100 @@ -15,11 +15,15 @@ * You should have received a copy of the GNU General Public License * along with this program. If not, see . */ +#include #include #include +#include #include #include +#include +#include #include /* @@ -35,25 +39,86 @@ * ldp x29, x30, [sp] * add sp, sp, #0x10 */ -int notrace unwind_frame(struct stackframe *frame) +int notrace unwind_frame(struct task_struct *tsk, struct stackframe *frame) { unsigned long high, low; unsigned long fp = frame->fp; + unsigned long irq_stack_ptr; + + /* + * Switching between stacks is valid when tracing current and in + * non-preemptible context. + */ + if (tsk == current && !preemptible()) + irq_stack_ptr = IRQ_STACK_PTR(smp_processor_id()); + else + irq_stack_ptr = 0; low = frame->sp; - high = ALIGN(low, THREAD_SIZE); + /* irq stacks are not THREAD_SIZE aligned */ + if (on_irq_stack(frame->sp, raw_smp_processor_id())) + high = irq_stack_ptr; + else + high = ALIGN(low, THREAD_SIZE) - 0x20; - if (fp < low || fp > high - 0x18 || fp & 0xf) + if (fp < low || fp > high || fp & 0xf) return -EINVAL; + kasan_disable_current(); + frame->sp = fp + 0x10; frame->fp = *(unsigned long *)(fp); frame->pc = *(unsigned long *)(fp + 8); + kasan_enable_current(); + +#ifdef CONFIG_FUNCTION_GRAPH_TRACER + if (tsk && tsk->ret_stack && + (frame->pc == (unsigned long)return_to_handler)) { + /* + * This is a case where function graph tracer has + * modified a return address (LR) in a stack frame + * to hook a function return. + * So replace it to an original value. + */ + frame->pc = tsk->ret_stack[frame->graph--].ret; + } +#endif /* CONFIG_FUNCTION_GRAPH_TRACER */ + + /* + * Check whether we are going to walk through from interrupt stack + * to task stack. + * If we reach the end of the stack - and its an interrupt stack, + * unpack the dummy frame to find the original elr. + * + * Check the frame->fp we read from the bottom of the irq_stack, + * and the original task stack pointer are both in current->stack. + */ + if (frame->sp == irq_stack_ptr) { + struct pt_regs *irq_args; + unsigned long orig_sp = IRQ_STACK_TO_TASK_STACK(irq_stack_ptr); + + if (object_is_on_stack((void *)orig_sp) && + object_is_on_stack((void *)frame->fp)) { + frame->sp = orig_sp; + + /* orig_sp is the saved pt_regs, find the elr */ + irq_args = (struct pt_regs *)orig_sp; + frame->pc = irq_args->pc; + } else { + /* + * This frame has a non-standard format, and we + * didn't fix it, because the data looked wrong. + * Refuse to output this frame. + */ + return -EINVAL; + } + } + return 0; } -void notrace walk_stackframe(struct stackframe *frame, +void notrace walk_stackframe(struct task_struct *tsk, struct stackframe *frame, int (*fn)(struct stackframe *, void *), void *data) { while (1) { @@ -61,12 +126,11 @@ if (fn(frame, data)) break; - ret = unwind_frame(frame); + ret = unwind_frame(tsk, frame); if (ret < 0) break; } } -EXPORT_SYMBOL(walk_stackframe); #ifdef CONFIG_STACKTRACE struct stack_trace_data { @@ -93,34 +157,51 @@ return trace->nr_entries >= trace->max_entries; } -void save_stack_trace_tsk(struct task_struct *tsk, struct stack_trace *trace) +static noinline void __save_stack_trace(struct task_struct *tsk, + struct stack_trace *trace, unsigned int nosched) { struct stack_trace_data data; struct stackframe frame; + if (!try_get_task_stack(tsk)) + return; + data.trace = trace; data.skip = trace->skip; + data.no_sched_functions = nosched; if (tsk != current) { - data.no_sched_functions = 1; frame.fp = thread_saved_fp(tsk); frame.sp = thread_saved_sp(tsk); frame.pc = thread_saved_pc(tsk); } else { - data.no_sched_functions = 0; + /* We don't want this function nor the caller */ + data.skip += 2; frame.fp = (unsigned long)__builtin_frame_address(0); frame.sp = current_stack_pointer; - frame.pc = (unsigned long)save_stack_trace_tsk; + frame.pc = (unsigned long)__save_stack_trace; } +#ifdef CONFIG_FUNCTION_GRAPH_TRACER + frame.graph = tsk->curr_ret_stack; +#endif - walk_stackframe(&frame, save_trace, &data); + walk_stackframe(tsk, &frame, save_trace, &data); if (trace->nr_entries < trace->max_entries) trace->entries[trace->nr_entries++] = ULONG_MAX; + + put_task_stack(tsk); +} +EXPORT_SYMBOL(save_stack_trace_tsk); + +void save_stack_trace_tsk(struct task_struct *tsk, struct stack_trace *trace) +{ + __save_stack_trace(tsk, trace, 1); } void save_stack_trace(struct stack_trace *trace) { - save_stack_trace_tsk(current, trace); + __save_stack_trace(current, trace, 0); } + EXPORT_SYMBOL_GPL(save_stack_trace); #endif diff -ruw linux-4.4.115/arch/arm64/kernel/suspend.c linux-4.4.115-fbx/arch/arm64/kernel/suspend.c --- linux-4.4.115/arch/arm64/kernel/suspend.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/arch/arm64/kernel/suspend.c 2019-01-22 16:16:21.555228766 +0100 @@ -5,6 +5,7 @@ #include #include #include +#include #include #include #include @@ -12,30 +13,11 @@ #include #include -extern int __cpu_suspend_enter(unsigned long arg, int (*fn)(unsigned long)); /* - * This is called by __cpu_suspend_enter() to save the state, and do whatever - * flushing is required to ensure that when the CPU goes to sleep we have - * the necessary data available when the caches are not searched. - * - * ptr: CPU context virtual address - * save_ptr: address of the location where the context physical address - * must be saved - */ -void notrace __cpu_suspend_save(struct cpu_suspend_ctx *ptr, - phys_addr_t *save_ptr) -{ - *save_ptr = virt_to_phys(ptr); - - cpu_do_suspend(ptr); - /* - * Only flush the context that must be retrieved with the MMU - * off. VA primitives ensure the flush is applied to all - * cache levels so context is pushed to DRAM. + * This is allocated by cpu_suspend_init(), and used to store a pointer to + * the 'struct sleep_stack_data' the contains a particular CPUs state. */ - __flush_dcache_area(ptr, sizeof(*ptr)); - __flush_dcache_area(save_ptr, sizeof(*save_ptr)); -} +unsigned long *sleep_save_stash; /* * This hook is provided so that cpu_suspend code can restore HW @@ -53,6 +35,24 @@ hw_breakpoint_restore = hw_bp_restore; } +void notrace __cpu_suspend_exit(void) +{ + /* + * We are resuming from reset with the idmap active in TTBR0_EL1. + * We must uninstall the idmap and restore the expected MMU + * state before we can possibly return to userspace. + */ + cpu_uninstall_idmap(); + + /* + * Restore HW breakpoint registers to sane values + * before debug exceptions are possibly reenabled + * through local_dbg_restore. + */ + if (hw_breakpoint_restore) + hw_breakpoint_restore(NULL); +} + /* * cpu_suspend * @@ -62,9 +62,9 @@ */ int cpu_suspend(unsigned long arg, int (*fn)(unsigned long)) { - struct mm_struct *mm = current->active_mm; - int ret; + int ret = 0; unsigned long flags; + struct sleep_stack_data state; /* * From this point debug exceptions are disabled to prevent @@ -80,37 +80,9 @@ */ pause_graph_tracing(); - /* - * mm context saved on the stack, it will be restored when - * the cpu comes out of reset through the identity mapped - * page tables, so that the thread address space is properly - * set-up on function return. - */ - ret = __cpu_suspend_enter(arg, fn); - if (ret == 0) { - /* - * We are resuming from reset with TTBR0_EL1 set to the - * idmap to enable the MMU; set the TTBR0 to the reserved - * page tables to prevent speculative TLB allocations, flush - * the local tlb and set the default tcr_el1.t0sz so that - * the TTBR0 address space set-up is properly restored. - * If the current active_mm != &init_mm we entered cpu_suspend - * with mappings in TTBR0 that must be restored, so we switch - * them back to complete the address space configuration - * restoration before returning. - */ - cpu_set_reserved_ttbr0(); - local_flush_tlb_all(); - cpu_set_default_tcr_t0sz(); - - if (mm != &init_mm) - cpu_switch_mm(mm->pgd, mm); - - /* - * Restore per-cpu offset before any kernel - * subsystem relying on it has a chance to run. - */ - set_my_cpu_offset(per_cpu_offset(smp_processor_id())); + if (__cpu_suspend_enter(&state)) { + /* Call the suspend finisher */ + ret = fn(arg); /* * PSTATE was not saved over suspend/resume, re-enable any @@ -118,14 +90,17 @@ */ asm(ALTERNATIVE("nop", SET_PSTATE_PAN(1), ARM64_HAS_PAN, CONFIG_ARM64_PAN)); + uao_thread_switch(current); /* * Restore HW breakpoint registers to sane values * before debug exceptions are possibly reenabled * through local_dbg_restore. */ - if (hw_breakpoint_restore) - hw_breakpoint_restore(NULL); + if (!ret) + ret = -EOPNOTSUPP; + } else { + __cpu_suspend_exit(); } unpause_graph_tracing(); @@ -140,22 +115,15 @@ return ret; } -struct sleep_save_sp sleep_save_sp; - static int __init cpu_suspend_init(void) { - void *ctx_ptr; - /* ctx_ptr is an array of physical addresses */ - ctx_ptr = kcalloc(mpidr_hash_size(), sizeof(phys_addr_t), GFP_KERNEL); + sleep_save_stash = kcalloc(mpidr_hash_size(), sizeof(*sleep_save_stash), + GFP_KERNEL); - if (WARN_ON(!ctx_ptr)) + if (WARN_ON(!sleep_save_stash)) return -ENOMEM; - sleep_save_sp.save_ptr_stash = ctx_ptr; - sleep_save_sp.save_ptr_stash_phys = virt_to_phys(ctx_ptr); - __flush_dcache_area(&sleep_save_sp, sizeof(struct sleep_save_sp)); - return 0; } early_initcall(cpu_suspend_init); diff -ruw linux-4.4.115/arch/arm64/kernel/time.c linux-4.4.115-fbx/arch/arm64/kernel/time.c --- linux-4.4.115/arch/arm64/kernel/time.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/arch/arm64/kernel/time.c 2019-01-22 16:16:21.555228766 +0100 @@ -52,8 +52,11 @@ frame.fp = regs->regs[29]; frame.sp = regs->sp; frame.pc = regs->pc; +#ifdef CONFIG_FUNCTION_GRAPH_TRACER + frame.graph = -1; /* no task info */ +#endif do { - int ret = unwind_frame(&frame); + int ret = unwind_frame(NULL, &frame); if (ret < 0) return 0; } while (in_lock_functions(frame.pc)); diff -ruw linux-4.4.115/arch/arm64/kernel/topology.c linux-4.4.115-fbx/arch/arm64/kernel/topology.c --- linux-4.4.115/arch/arm64/kernel/topology.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/arch/arm64/kernel/topology.c 2019-01-22 16:16:21.555228766 +0100 @@ -19,10 +19,52 @@ #include #include #include +#include +#include +#include #include #include +/* + * cpu power table + * This per cpu data structure describes the relative capacity of each core. + * On a heteregenous system, cores don't have the same computation capacity + * and we reflect that difference in the cpu_power field so the scheduler can + * take this difference into account during load balance. A per cpu structure + * is preferred because each CPU updates its own cpu_power field during the + * load balance except for idle cores. One idle core is selected to run the + * rebalance_domains for all idle cores and the cpu_power can be updated + * during this sequence. + */ +static DEFINE_PER_CPU(unsigned long, cpu_scale) = SCHED_CAPACITY_SCALE; + +unsigned long arch_scale_freq_power(struct sched_domain *sd, int cpu) +{ + return per_cpu(cpu_scale, cpu); +} + +static void set_power_scale(unsigned int cpu, unsigned long power) +{ + per_cpu(cpu_scale, cpu) = power; +} + +unsigned long scale_cpu_capacity(struct sched_domain *sd, int cpu) +{ +#ifdef CONFIG_CPU_FREQ + unsigned long max_freq_scale = cpufreq_scale_max_freq_capacity(cpu); + + return per_cpu(cpu_scale, cpu) * max_freq_scale >> SCHED_CAPACITY_SHIFT; +#else + return per_cpu(cpu_scale, cpu); +#endif +} + +static void set_capacity_scale(unsigned int cpu, unsigned long capacity) +{ + per_cpu(cpu_scale, cpu) = capacity; +} + static int __init get_cpu_for_node(struct device_node *node) { struct device_node *cpu_node; @@ -161,6 +203,46 @@ return 0; } +struct cpu_efficiency { + const char *compatible; + unsigned long efficiency; +}; + +/* + * Table of relative efficiency of each processors + * The efficiency value must fit in 20bit and the final + * cpu_scale value must be in the range + * 0 < cpu_scale < 3*SCHED_CAPACITY_SCALE/2 + * in order to return at most 1 when DIV_ROUND_CLOSEST + * is used to compute the capacity of a CPU. + * Processors that are not defined in the table, + * use the default SCHED_CAPACITY_SCALE value for cpu_scale. + */ +static const struct cpu_efficiency table_efficiency[] = { + { NULL, }, +}; + +static unsigned long *__cpu_capacity; +#define cpu_capacity(cpu) __cpu_capacity[cpu] + +static unsigned long middle_capacity = 1; + +static DEFINE_PER_CPU(unsigned long, cpu_efficiency) = SCHED_CAPACITY_SCALE; + +unsigned long arch_get_cpu_efficiency(int cpu) +{ + return per_cpu(cpu_efficiency, cpu); +} +EXPORT_SYMBOL(arch_get_cpu_efficiency); + +/* + * Iterate all CPUs' descriptor in DT and compute the efficiency + * (as per table_efficiency). Also calculate a middle efficiency + * as close as possible to (max{eff_i} - min{eff_i}) / 2 + * This is later used to scale the cpu_power field such that an + * 'average' CPU is of middle power. Also see the comments near + * table_efficiency[] and update_cpu_power(). + */ static int __init parse_dt_topology(void) { struct device_node *cn, *map; @@ -200,17 +282,179 @@ return ret; } +static void __init parse_dt_cpu_power(void) +{ + const struct cpu_efficiency *cpu_eff; + struct device_node *cn; + unsigned long min_capacity = ULONG_MAX; + unsigned long max_capacity = 0; + unsigned long capacity = 0; + int cpu; + + __cpu_capacity = kcalloc(nr_cpu_ids, sizeof(*__cpu_capacity), + GFP_NOWAIT); + + for_each_possible_cpu(cpu) { + const u32 *rate; + int len; + u32 efficiency; + + /* Too early to use cpu->of_node */ + cn = of_get_cpu_node(cpu, NULL); + if (!cn) { + pr_err("Missing device node for CPU %d\n", cpu); + continue; + } + + /* + * The CPU efficiency value passed from the device tree + * overrides the value defined in the table_efficiency[] + */ + if (of_property_read_u32(cn, "efficiency", &efficiency) < 0) { + + for (cpu_eff = table_efficiency; + cpu_eff->compatible; cpu_eff++) + + if (of_device_is_compatible(cn, + cpu_eff->compatible)) + break; + + if (cpu_eff->compatible == NULL) { + pr_warn("%s: Unknown CPU type\n", + cn->full_name); + continue; + } + + efficiency = cpu_eff->efficiency; + } + + per_cpu(cpu_efficiency, cpu) = efficiency; + + rate = of_get_property(cn, "clock-frequency", &len); + if (!rate || len != 4) { + pr_err("%s: Missing clock-frequency property\n", + cn->full_name); + continue; + } + + capacity = ((be32_to_cpup(rate)) >> 20) * efficiency; + + /* Save min capacity of the system */ + if (capacity < min_capacity) + min_capacity = capacity; + + /* Save max capacity of the system */ + if (capacity > max_capacity) + max_capacity = capacity; + + cpu_capacity(cpu) = capacity; + } + + /* If min and max capacities are equal we bypass the update of the + * cpu_scale because all CPUs have the same capacity. Otherwise, we + * compute a middle_capacity factor that will ensure that the capacity + * of an 'average' CPU of the system will be as close as possible to + * SCHED_CAPACITY_SCALE, which is the default value, but with the + * constraint explained near table_efficiency[]. + */ + if (min_capacity == max_capacity) + return; + else if (4 * max_capacity < (3 * (max_capacity + min_capacity))) + middle_capacity = (min_capacity + max_capacity) + >> (SCHED_CAPACITY_SHIFT+1); + else + middle_capacity = ((max_capacity / 3) + >> (SCHED_CAPACITY_SHIFT-1)) + 1; +} + +/* + * Look for a customed capacity of a CPU in the cpu_topo_data table during the + * boot. The update of all CPUs is in O(n^2) for heteregeneous system but the + * function returns directly for SMP system. + */ +static void update_cpu_power(unsigned int cpu) +{ + if (!cpu_capacity(cpu)) + return; + + set_power_scale(cpu, cpu_capacity(cpu) / middle_capacity); + + pr_info("CPU%u: update cpu_power %lu\n", + cpu, arch_scale_freq_power(NULL, cpu)); +} + /* * cpu topology table */ struct cpu_topology cpu_topology[NR_CPUS]; EXPORT_SYMBOL_GPL(cpu_topology); +/* sd energy functions */ +static inline +const struct sched_group_energy * const cpu_cluster_energy(int cpu) +{ + struct sched_group_energy *sge = sge_array[cpu][SD_LEVEL1]; + + if (!sge) { + pr_warn("Invalid sched_group_energy for Cluster%d\n", cpu); + return NULL; + } + + return sge; +} + +static inline +const struct sched_group_energy * const cpu_core_energy(int cpu) +{ + struct sched_group_energy *sge = sge_array[cpu][SD_LEVEL0]; + + if (!sge) { + pr_warn("Invalid sched_group_energy for CPU%d\n", cpu); + return NULL; + } + + return sge; +} + const struct cpumask *cpu_coregroup_mask(int cpu) { return &cpu_topology[cpu].core_sibling; } +static int cpu_cpu_flags(void) +{ + return SD_ASYM_CPUCAPACITY; +} + +static inline int cpu_corepower_flags(void) +{ + return SD_SHARE_PKG_RESOURCES | SD_SHARE_POWERDOMAIN | \ + SD_SHARE_CAP_STATES; +} + +static struct sched_domain_topology_level arm64_topology[] = { +#ifdef CONFIG_SCHED_MC + { cpu_coregroup_mask, cpu_corepower_flags, cpu_core_energy, SD_INIT_NAME(MC) }, +#endif + { cpu_cpu_mask, cpu_cpu_flags, cpu_cluster_energy, SD_INIT_NAME(DIE) }, + { NULL, }, +}; + +static void update_cpu_capacity(unsigned int cpu) +{ + unsigned long capacity = SCHED_CAPACITY_SCALE; + + if (sched_energy_aware && cpu_core_energy(cpu)) { + int max_cap_idx = cpu_core_energy(cpu)->nr_cap_states - 1; + capacity = cpu_core_energy(cpu)->cap_states[max_cap_idx].cap; + } + + set_capacity_scale(cpu, capacity); + + pr_info("CPU%d: update cpu_capacity %lu\n", + cpu, arch_scale_cpu_capacity(NULL, cpu)); +} + static void update_siblings_masks(unsigned int cpuid) { struct cpu_topology *cpu_topo, *cpuid_topo = &cpu_topology[cpuid]; @@ -272,6 +516,8 @@ topology_populated: update_siblings_masks(cpuid); + update_cpu_power(cpuid); + update_cpu_capacity(cpuid); } static void __init reset_cpu_topology(void) @@ -292,14 +538,33 @@ } } +static void __init reset_cpu_power(void) +{ + unsigned int cpu; + + for_each_possible_cpu(cpu) + set_power_scale(cpu, SCHED_CAPACITY_SCALE); +} + void __init init_cpu_topology(void) { + int cpu; + reset_cpu_topology(); /* * Discard anything that was parsed if we hit an error so we * don't use partial information. */ - if (of_have_populated_dt() && parse_dt_topology()) + if (of_have_populated_dt() && parse_dt_topology()) { reset_cpu_topology(); + } else { + set_sched_topology(arm64_topology); + for_each_possible_cpu(cpu) + update_siblings_masks(cpu); + } + + reset_cpu_power(); + parse_dt_cpu_power(); + init_sched_energy_costs(); } diff -ruw linux-4.4.115/arch/arm64/kernel/traps.c linux-4.4.115-fbx/arch/arm64/kernel/traps.c --- linux-4.4.115/arch/arm64/kernel/traps.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/arch/arm64/kernel/traps.c 2019-10-29 09:26:23.009196974 +0100 @@ -33,14 +33,20 @@ #include #include +#include #include #include #include #include #include +#include #include #include #include +#include +#include + +#include static const char *handler[]= { "Synchronous Abort", @@ -146,17 +152,32 @@ static void dump_backtrace(struct pt_regs *regs, struct task_struct *tsk) { struct stackframe frame; + unsigned long irq_stack_ptr; + int skip; + + pr_debug("%s(regs = %pK tsk = %pK)\n", __func__, regs, tsk); + + if (!tsk) + tsk = current; + + if (!try_get_task_stack(tsk)) + return; + + /* + * Switching between stacks is valid when tracing current and in + * non-preemptible context. + */ + if (tsk == current && !preemptible()) + irq_stack_ptr = IRQ_STACK_PTR(smp_processor_id()); + else + irq_stack_ptr = 0; pr_debug("%s(regs = %p tsk = %p)\n", __func__, regs, tsk); if (!tsk) tsk = current; - if (regs) { - frame.fp = regs->regs[29]; - frame.sp = regs->sp; - frame.pc = regs->pc; - } else if (tsk == current) { + if (tsk == current) { frame.fp = (unsigned long)__builtin_frame_address(0); frame.sp = current_stack_pointer; frame.pc = (unsigned long)dump_backtrace; @@ -168,24 +189,54 @@ frame.sp = thread_saved_sp(tsk); frame.pc = thread_saved_pc(tsk); } +#ifdef CONFIG_FUNCTION_GRAPH_TRACER + frame.graph = tsk->curr_ret_stack; +#endif - pr_emerg("Call trace:\n"); + skip = !!regs; + printk("Call trace:\n"); while (1) { unsigned long where = frame.pc; unsigned long stack; int ret; + /* skip until specified stack frame */ + if (!skip) { dump_backtrace_entry(where); - ret = unwind_frame(&frame); + } else if (frame.fp == regs->regs[29]) { + skip = 0; + /* + * Mostly, this is the case where this function is + * called in panic/abort. As exception handler's + * stack frame does not contain the corresponding pc + * at which an exception has taken place, use regs->pc + * instead. + */ + dump_backtrace_entry(regs->pc); + } + ret = unwind_frame(tsk, &frame); if (ret < 0) break; stack = frame.sp; - if (in_exception_text(where)) + if (in_exception_text(where)) { + /* + * If we switched to the irq_stack before calling this + * exception handler, then the pt_regs will be on the + * task stack. The easiest way to tell is if the large + * pt_regs would overlap with the end of the irq_stack. + */ + if (stack < irq_stack_ptr && + (stack + sizeof(struct pt_regs)) > irq_stack_ptr) + stack = IRQ_STACK_TO_TASK_STACK(irq_stack_ptr); + dump_mem("", "Exception stack", stack, stack + sizeof(struct pt_regs), false); } } + put_task_stack(tsk); +} + void show_stack(struct task_struct *tsk, unsigned long *sp) { dump_backtrace(NULL, tsk); @@ -199,10 +250,9 @@ #endif #define S_SMP " SMP" -static int __die(const char *str, int err, struct thread_info *thread, - struct pt_regs *regs) +static int __die(const char *str, int err, struct pt_regs *regs) { - struct task_struct *tsk = thread->task; + struct task_struct *tsk = current; static int die_counter; int ret; @@ -217,12 +267,10 @@ print_modules(); __show_regs(regs); pr_emerg("Process %.*s (pid: %d, stack limit = 0x%p)\n", - TASK_COMM_LEN, tsk->comm, task_pid_nr(tsk), thread + 1); + TASK_COMM_LEN, tsk->comm, task_pid_nr(tsk), + end_of_stack(tsk)); if (!user_mode(regs) || in_interrupt()) { - dump_mem(KERN_EMERG, "Stack: ", regs->sp, - THREAD_SIZE + (unsigned long)task_stack_page(tsk), - compat_user_mode(regs)); dump_backtrace(regs, tsk); dump_instr(KERN_EMERG, regs); } @@ -230,39 +278,75 @@ return ret; } -static DEFINE_RAW_SPINLOCK(die_lock); +static arch_spinlock_t die_lock = __ARCH_SPIN_LOCK_UNLOCKED; +static int die_owner = -1; +static unsigned int die_nest_count; -/* - * This function is protected against re-entrancy. - */ -void die(const char *str, struct pt_regs *regs, int err) +static unsigned long oops_begin(void) { - struct thread_info *thread = current_thread_info(); - int ret; + int cpu; + unsigned long flags; oops_enter(); - raw_spin_lock_irq(&die_lock); + /* racy, but better than risking deadlock. */ + raw_local_irq_save(flags); + cpu = smp_processor_id(); + if (!arch_spin_trylock(&die_lock)) { + if (cpu == die_owner) + /* nested oops. should stop eventually */; + else + arch_spin_lock(&die_lock); + } + die_nest_count++; + die_owner = cpu; console_verbose(); bust_spinlocks(1); - ret = __die(str, err, thread, regs); + return flags; +} - if (regs && kexec_should_crash(thread->task)) +static void oops_end(unsigned long flags, struct pt_regs *regs, int notify) +{ + if (regs && kexec_should_crash(current)) crash_kexec(regs); bust_spinlocks(0); + die_owner = -1; add_taint(TAINT_DIE, LOCKDEP_NOW_UNRELIABLE); - raw_spin_unlock_irq(&die_lock); + die_nest_count--; + if (!die_nest_count) + /* Nest count reaches zero, release the lock. */ + arch_spin_unlock(&die_lock); + raw_local_irq_restore(flags); oops_exit(); if (in_interrupt()) panic("Fatal exception in interrupt"); if (panic_on_oops) panic("Fatal exception"); - if (ret != NOTIFY_STOP) + if (notify != NOTIFY_STOP) do_exit(SIGSEGV); } +/* + * This function is protected against re-entrancy. + */ +void die(const char *str, struct pt_regs *regs, int err) +{ + enum bug_trap_type bug_type = BUG_TRAP_TYPE_NONE; + unsigned long flags = oops_begin(); + int ret; + + if (!user_mode(regs)) + bug_type = report_bug(regs->pc, regs); + if (bug_type != BUG_TRAP_TYPE_NONE) + str = "Oops - BUG"; + + ret = __die(str, err, regs); + + oops_end(flags, regs, ret); +} + void arm64_notify_die(const char *str, struct pt_regs *regs, struct siginfo *info, int err) { @@ -350,6 +434,8 @@ if (call_undef_hook(regs) == 0) return; + trace_undef_instr(regs, (void *)pc); + if (unhandled_signal(current, SIGILL) && show_unhandled_signals_ratelimited()) { pr_info("%s[%d]: undefined instruction: pc=%p\n", current->comm, task_pid_nr(current), pc); @@ -364,6 +450,38 @@ arm64_notify_die("Oops - undefined instruction", regs, &info, 0); } +static void cntvct_read_handler(unsigned int esr, struct pt_regs *regs) +{ + int rt = (esr & ESR_ELx_SYS64_ISS_RT_MASK) >> ESR_ELx_SYS64_ISS_RT_SHIFT; + + isb(); + if (rt != 31) + regs->regs[rt] = arch_counter_get_cntvct(); + regs->pc += 4; +} + +static void cntfrq_read_handler(unsigned int esr, struct pt_regs *regs) +{ + int rt = (esr & ESR_ELx_SYS64_ISS_RT_MASK) >> ESR_ELx_SYS64_ISS_RT_SHIFT; + + if (rt != 31) + regs->regs[rt] = read_sysreg(cntfrq_el0); + regs->pc += 4; +} + +asmlinkage void __exception do_sysinstr(unsigned int esr, struct pt_regs *regs) +{ + if ((esr & ESR_ELx_SYS64_ISS_SYS_OP_MASK) == ESR_ELx_SYS64_ISS_SYS_CNTVCT) { + cntvct_read_handler(esr, regs); + return; + } else if ((esr & ESR_ELx_SYS64_ISS_SYS_OP_MASK) == ESR_ELx_SYS64_ISS_SYS_CNTFRQ) { + cntfrq_read_handler(esr, regs); + return; + } + + do_undefinstr(regs); +} + long compat_arm_syscall(struct pt_regs *regs); asmlinkage long do_ni_syscall(struct pt_regs *regs) @@ -430,7 +548,7 @@ const char *esr_get_class_string(u32 esr) { - return esr_class_str[esr >> ESR_ELx_EC_SHIFT]; + return esr_class_str[ESR_ELx_EC(esr)]; } /* @@ -444,6 +562,12 @@ pr_crit("Bad mode in %s handler detected, code 0x%08x -- %s\n", handler[reason], esr, esr_get_class_string(esr)); + if (esr >> ESR_ELx_EC_SHIFT == ESR_ELx_EC_SERROR) { + pr_crit("System error detected. ESR.ISS = %08x\n", + esr & 0xffffff); + arm64_check_cache_ecc(NULL); + } + die("Oops - bad mode", regs, 0); local_irq_disable(); panic("bad mode"); @@ -476,22 +600,22 @@ void __pte_error(const char *file, int line, unsigned long val) { - pr_crit("%s:%d: bad pte %016lx.\n", file, line, val); + pr_err("%s:%d: bad pte %016lx.\n", file, line, val); } void __pmd_error(const char *file, int line, unsigned long val) { - pr_crit("%s:%d: bad pmd %016lx.\n", file, line, val); + pr_err("%s:%d: bad pmd %016lx.\n", file, line, val); } void __pud_error(const char *file, int line, unsigned long val) { - pr_crit("%s:%d: bad pud %016lx.\n", file, line, val); + pr_err("%s:%d: bad pud %016lx.\n", file, line, val); } void __pgd_error(const char *file, int line, unsigned long val) { - pr_crit("%s:%d: bad pgd %016lx.\n", file, line, val); + pr_err("%s:%d: bad pgd %016lx.\n", file, line, val); } /* GENERIC_BUG traps */ diff -ruw linux-4.4.115/arch/arm64/kernel/vdso/gettimeofday.S linux-4.4.115-fbx/arch/arm64/kernel/vdso/gettimeofday.S --- linux-4.4.115/arch/arm64/kernel/vdso/gettimeofday.S 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/arch/arm64/kernel/vdso/gettimeofday.S 2019-10-29 09:26:23.009196974 +0100 @@ -26,24 +26,109 @@ #define NSEC_PER_SEC_HI16 0x3b9a vdso_data .req x6 -use_syscall .req w7 -seqcnt .req w8 +seqcnt .req w7 +w_tmp .req w8 +x_tmp .req x8 + +/* + * Conventions for macro arguments: + * - An argument is write-only if its name starts with "res". + * - All other arguments are read-only, unless otherwise specified. + */ .macro seqcnt_acquire 9999: ldr seqcnt, [vdso_data, #VDSO_TB_SEQ_COUNT] tbnz seqcnt, #0, 9999b dmb ishld - ldr use_syscall, [vdso_data, #VDSO_USE_SYSCALL] .endm - .macro seqcnt_read, cnt + .macro seqcnt_check fail dmb ishld - ldr \cnt, [vdso_data, #VDSO_TB_SEQ_COUNT] + ldr w_tmp, [vdso_data, #VDSO_TB_SEQ_COUNT] + cmp w_tmp, seqcnt + b.ne \fail .endm - .macro seqcnt_check, cnt, fail - cmp \cnt, seqcnt - b.ne \fail + .macro syscall_check fail + ldr w_tmp, [vdso_data, #VDSO_USE_SYSCALL] + cbnz w_tmp, \fail + .endm + + .macro get_nsec_per_sec res + mov \res, #NSEC_PER_SEC_LO16 + movk \res, #NSEC_PER_SEC_HI16, lsl #16 + .endm + + /* + * Returns the clock delta, in nanoseconds left-shifted by the clock + * shift. + */ + .macro get_clock_shifted_nsec res, cycle_last, mult + /* Read the virtual counter. */ + isb + mrs x_tmp, cntvct_el0 + /* Calculate cycle delta and convert to ns. */ + sub \res, x_tmp, \cycle_last + /* We can only guarantee 56 bits of precision. */ + movn x_tmp, #0xff00, lsl #48 + and \res, x_tmp, \res + mul \res, \res, \mult + .endm + + /* + * Returns in res_{sec,nsec} the REALTIME timespec, based on the + * "wall time" (xtime) and the clock_mono delta. + */ + .macro get_ts_realtime res_sec, res_nsec, \ + clock_nsec, xtime_sec, xtime_nsec, nsec_to_sec + add \res_nsec, \clock_nsec, \xtime_nsec + udiv x_tmp, \res_nsec, \nsec_to_sec + add \res_sec, \xtime_sec, x_tmp + msub \res_nsec, x_tmp, \nsec_to_sec, \res_nsec + .endm + + /* + * Returns in res_{sec,nsec} the timespec based on the clock_raw delta, + * used for CLOCK_MONOTONIC_RAW. + */ + .macro get_ts_clock_raw res_sec, res_nsec, clock_nsec, nsec_to_sec + udiv \res_sec, \clock_nsec, \nsec_to_sec + msub \res_nsec, \res_sec, \nsec_to_sec, \clock_nsec + .endm + + /* sec and nsec are modified in place. */ + .macro add_ts sec, nsec, ts_sec, ts_nsec, nsec_to_sec + /* Add timespec. */ + add \sec, \sec, \ts_sec + add \nsec, \nsec, \ts_nsec + + /* Normalise the new timespec. */ + cmp \nsec, \nsec_to_sec + b.lt 9999f + sub \nsec, \nsec, \nsec_to_sec + add \sec, \sec, #1 +9999: + cmp \nsec, #0 + b.ge 9998f + add \nsec, \nsec, \nsec_to_sec + sub \sec, \sec, #1 +9998: + .endm + + .macro clock_gettime_return, shift=0 + .if \shift == 1 + lsr x11, x11, x12 + .endif + stp x10, x11, [x1, #TSPEC_TV_SEC] + mov x0, xzr + ret + .endm + + .macro jump_slot jumptable, index, label + .if (. - \jumptable) != 4 * (\index) + .error "Jump slot index mismatch" + .endif + b \label .endm .text @@ -51,18 +136,25 @@ /* int __kernel_gettimeofday(struct timeval *tv, struct timezone *tz); */ ENTRY(__kernel_gettimeofday) .cfi_startproc - mov x2, x30 - .cfi_register x30, x2 - - /* Acquire the sequence counter and get the timespec. */ adr vdso_data, _vdso_data -1: seqcnt_acquire - cbnz use_syscall, 4f - /* If tv is NULL, skip to the timezone code. */ cbz x0, 2f - bl __do_get_tspec - seqcnt_check w9, 1b + + /* Compute the time of day. */ +1: seqcnt_acquire + syscall_check fail=4f + ldr x10, [vdso_data, #VDSO_CS_CYCLE_LAST] + /* w11 = cs_mono_mult, w12 = cs_shift */ + ldp w11, w12, [vdso_data, #VDSO_CS_MONO_MULT] + ldp x13, x14, [vdso_data, #VDSO_XTIME_CLK_SEC] + seqcnt_check fail=1b + + get_nsec_per_sec res=x9 + lsl x9, x9, x12 + + get_clock_shifted_nsec res=x15, cycle_last=x10, mult=x11 + get_ts_realtime res_sec=x10, res_nsec=x11, \ + clock_nsec=x15, xtime_sec=x13, xtime_nsec=x14, nsec_to_sec=x9 /* Convert ns to us. */ mov x13, #1000 @@ -76,95 +168,126 @@ stp w4, w5, [x1, #TZ_MINWEST] 3: mov x0, xzr - ret x2 + ret 4: /* Syscall fallback. */ mov x8, #__NR_gettimeofday svc #0 - ret x2 + ret .cfi_endproc ENDPROC(__kernel_gettimeofday) +#define JUMPSLOT_MAX CLOCK_MONOTONIC_COARSE + /* int __kernel_clock_gettime(clockid_t clock_id, struct timespec *tp); */ ENTRY(__kernel_clock_gettime) .cfi_startproc - cmp w0, #CLOCK_REALTIME - ccmp w0, #CLOCK_MONOTONIC, #0x4, ne - b.ne 2f - - mov x2, x30 - .cfi_register x30, x2 - - /* Get kernel timespec. */ + cmp w0, #JUMPSLOT_MAX + b.hi syscall adr vdso_data, _vdso_data -1: seqcnt_acquire - cbnz use_syscall, 7f - - bl __do_get_tspec - seqcnt_check w9, 1b - - mov x30, x2 - - cmp w0, #CLOCK_MONOTONIC - b.ne 6f + adr x_tmp, jumptable + add x_tmp, x_tmp, w0, uxtw #2 + br x_tmp + + ALIGN +jumptable: + jump_slot jumptable, CLOCK_REALTIME, realtime + jump_slot jumptable, CLOCK_MONOTONIC, monotonic + b syscall + b syscall + jump_slot jumptable, CLOCK_MONOTONIC_RAW, monotonic_raw + jump_slot jumptable, CLOCK_REALTIME_COARSE, realtime_coarse + jump_slot jumptable, CLOCK_MONOTONIC_COARSE, monotonic_coarse + + .if (. - jumptable) != 4 * (JUMPSLOT_MAX + 1) + .error "Wrong jumptable size" + .endif + + ALIGN +realtime: + seqcnt_acquire + syscall_check fail=syscall + ldr x10, [vdso_data, #VDSO_CS_CYCLE_LAST] + /* w11 = cs_mono_mult, w12 = cs_shift */ + ldp w11, w12, [vdso_data, #VDSO_CS_MONO_MULT] + ldp x13, x14, [vdso_data, #VDSO_XTIME_CLK_SEC] + seqcnt_check fail=realtime - /* Get wtm timespec. */ - ldp x13, x14, [vdso_data, #VDSO_WTM_CLK_SEC] + /* All computations are done with left-shifted nsecs. */ + get_nsec_per_sec res=x9 + lsl x9, x9, x12 + + get_clock_shifted_nsec res=x15, cycle_last=x10, mult=x11 + get_ts_realtime res_sec=x10, res_nsec=x11, \ + clock_nsec=x15, xtime_sec=x13, xtime_nsec=x14, nsec_to_sec=x9 + clock_gettime_return, shift=1 + + ALIGN +monotonic: + seqcnt_acquire + syscall_check fail=syscall + ldr x10, [vdso_data, #VDSO_CS_CYCLE_LAST] + /* w11 = cs_mono_mult, w12 = cs_shift */ + ldp w11, w12, [vdso_data, #VDSO_CS_MONO_MULT] + ldp x13, x14, [vdso_data, #VDSO_XTIME_CLK_SEC] + ldp x3, x4, [vdso_data, #VDSO_WTM_CLK_SEC] + seqcnt_check fail=monotonic - /* Check the sequence counter. */ - seqcnt_read w9 - seqcnt_check w9, 1b - b 4f -2: - cmp w0, #CLOCK_REALTIME_COARSE - ccmp w0, #CLOCK_MONOTONIC_COARSE, #0x4, ne - b.ne 8f + /* All computations are done with left-shifted nsecs. */ + lsl x4, x4, x12 + get_nsec_per_sec res=x9 + lsl x9, x9, x12 + + get_clock_shifted_nsec res=x15, cycle_last=x10, mult=x11 + get_ts_realtime res_sec=x10, res_nsec=x11, \ + clock_nsec=x15, xtime_sec=x13, xtime_nsec=x14, nsec_to_sec=x9 + + add_ts sec=x10, nsec=x11, ts_sec=x3, ts_nsec=x4, nsec_to_sec=x9 + clock_gettime_return, shift=1 + + ALIGN +monotonic_raw: + seqcnt_acquire + syscall_check fail=syscall + ldr x10, [vdso_data, #VDSO_CS_CYCLE_LAST] + /* w11 = cs_raw_mult, w12 = cs_shift */ + ldp w12, w11, [vdso_data, #VDSO_CS_SHIFT] + ldp x13, x14, [vdso_data, #VDSO_RAW_TIME_SEC] + seqcnt_check fail=monotonic_raw - /* xtime_coarse_nsec is already right-shifted */ - mov x12, #0 + /* All computations are done with left-shifted nsecs. */ + lsl x14, x14, x12 + get_nsec_per_sec res=x9 + lsl x9, x9, x12 - /* Get coarse timespec. */ - adr vdso_data, _vdso_data -3: seqcnt_acquire + get_clock_shifted_nsec res=x15, cycle_last=x10, mult=x11 + get_ts_clock_raw res_sec=x10, res_nsec=x11, \ + clock_nsec=x15, nsec_to_sec=x9 + + add_ts sec=x10, nsec=x11, ts_sec=x13, ts_nsec=x14, nsec_to_sec=x9 + clock_gettime_return, shift=1 + + ALIGN +realtime_coarse: + seqcnt_acquire ldp x10, x11, [vdso_data, #VDSO_XTIME_CRS_SEC] + seqcnt_check fail=realtime_coarse + clock_gettime_return - /* Get wtm timespec. */ + ALIGN +monotonic_coarse: + seqcnt_acquire + ldp x10, x11, [vdso_data, #VDSO_XTIME_CRS_SEC] ldp x13, x14, [vdso_data, #VDSO_WTM_CLK_SEC] + seqcnt_check fail=monotonic_coarse - /* Check the sequence counter. */ - seqcnt_read w9 - seqcnt_check w9, 3b - - cmp w0, #CLOCK_MONOTONIC_COARSE - b.ne 6f -4: - /* Add on wtm timespec. */ - add x10, x10, x13 - lsl x14, x14, x12 - add x11, x11, x14 + /* Computations are done in (non-shifted) nsecs. */ + get_nsec_per_sec res=x9 + add_ts sec=x10, nsec=x11, ts_sec=x13, ts_nsec=x14, nsec_to_sec=x9 + clock_gettime_return - /* Normalise the new timespec. */ - mov x15, #NSEC_PER_SEC_LO16 - movk x15, #NSEC_PER_SEC_HI16, lsl #16 - lsl x15, x15, x12 - cmp x11, x15 - b.lt 5f - sub x11, x11, x15 - add x10, x10, #1 -5: - cmp x11, #0 - b.ge 6f - add x11, x11, x15 - sub x10, x10, #1 - -6: /* Store to the user timespec. */ - lsr x11, x11, x12 - stp x10, x11, [x1, #TSPEC_TV_SEC] - mov x0, xzr - ret -7: - mov x30, x2 -8: /* Syscall fallback. */ + ALIGN +syscall: /* Syscall fallback. */ mov x8, #__NR_clock_gettime svc #0 ret @@ -176,6 +299,7 @@ .cfi_startproc cmp w0, #CLOCK_REALTIME ccmp w0, #CLOCK_MONOTONIC, #0x4, ne + ccmp w0, #CLOCK_MONOTONIC_RAW, #0x4, ne b.ne 1f ldr x2, 5f @@ -186,7 +310,7 @@ b.ne 4f ldr x2, 6f 2: - cbz w1, 3f + cbz x1, 3f stp xzr, x2, [x1] 3: /* res == NULL. */ @@ -203,46 +327,3 @@ .quad CLOCK_COARSE_RES .cfi_endproc ENDPROC(__kernel_clock_getres) - -/* - * Read the current time from the architected counter. - * Expects vdso_data to be initialised. - * Clobbers the temporary registers (x9 - x15). - * Returns: - * - w9 = vDSO sequence counter - * - (x10, x11) = (ts->tv_sec, shifted ts->tv_nsec) - * - w12 = cs_shift - */ -ENTRY(__do_get_tspec) - .cfi_startproc - - /* Read from the vDSO data page. */ - ldr x10, [vdso_data, #VDSO_CS_CYCLE_LAST] - ldp x13, x14, [vdso_data, #VDSO_XTIME_CLK_SEC] - ldp w11, w12, [vdso_data, #VDSO_CS_MULT] - seqcnt_read w9 - - /* Read the virtual counter. */ - isb - mrs x15, cntvct_el0 - - /* Calculate cycle delta and convert to ns. */ - sub x10, x15, x10 - /* We can only guarantee 56 bits of precision. */ - movn x15, #0xff00, lsl #48 - and x10, x15, x10 - mul x10, x10, x11 - - /* Use the kernel time to calculate the new timespec. */ - mov x11, #NSEC_PER_SEC_LO16 - movk x11, #NSEC_PER_SEC_HI16, lsl #16 - lsl x11, x11, x12 - add x15, x10, x14 - udiv x14, x15, x11 - add x10, x13, x14 - mul x13, x14, x11 - sub x11, x15, x13 - - ret - .cfi_endproc -ENDPROC(__do_get_tspec) diff -ruw linux-4.4.115/arch/arm64/kernel/vdso/Makefile linux-4.4.115-fbx/arch/arm64/kernel/vdso/Makefile --- linux-4.4.115/arch/arm64/kernel/vdso/Makefile 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/arch/arm64/kernel/vdso/Makefile 2019-01-22 16:16:21.555228766 +0100 @@ -23,7 +23,7 @@ ccflags-y += -Wl,-shared obj-y += vdso.o -extra-y += vdso.lds vdso-offsets.h +extra-y += vdso.lds CPPFLAGS_vdso.lds += -P -C -U$(ARCH) # Force dependency (incbin is bad) @@ -42,11 +42,10 @@ gen-vdsosym := $(srctree)/$(src)/gen_vdso_offsets.sh quiet_cmd_vdsosym = VDSOSYM $@ define cmd_vdsosym - $(NM) $< | $(gen-vdsosym) | LC_ALL=C sort > $@ && \ - cp $@ include/generated/ + $(NM) $< | $(gen-vdsosym) | LC_ALL=C sort > $@ endef -$(obj)/vdso-offsets.h: $(obj)/vdso.so.dbg FORCE +include/generated/vdso-offsets.h: $(obj)/vdso.so.dbg FORCE $(call if_changed,vdsosym) # Assembly rules for the .S files diff -ruw linux-4.4.115/arch/arm64/kernel/vdso/vdso.S linux-4.4.115-fbx/arch/arm64/kernel/vdso/vdso.S --- linux-4.4.115/arch/arm64/kernel/vdso/vdso.S 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/arch/arm64/kernel/vdso/vdso.S 2019-01-22 16:16:21.555228766 +0100 @@ -21,9 +21,8 @@ #include #include - __PAGE_ALIGNED_DATA - .globl vdso_start, vdso_end + .section .rodata .balign PAGE_SIZE vdso_start: .incbin "arch/arm64/kernel/vdso/vdso.so" diff -ruw linux-4.4.115/arch/arm64/kernel/vdso.c linux-4.4.115-fbx/arch/arm64/kernel/vdso.c --- linux-4.4.115/arch/arm64/kernel/vdso.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/arch/arm64/kernel/vdso.c 2019-10-29 09:26:23.009196974 +0100 @@ -55,7 +55,7 @@ */ static struct page *vectors_page[1]; -static int alloc_vectors_page(void) +static int __init alloc_vectors_page(void) { extern char __kuser_helper_start[], __kuser_helper_end[]; extern char __aarch32_sigret_code_start[], __aarch32_sigret_code_end[]; @@ -88,7 +88,7 @@ { struct mm_struct *mm = current->mm; unsigned long addr = AARCH32_VECTORS_BASE; - static struct vm_special_mapping spec = { + static const struct vm_special_mapping spec = { .name = "[vectors]", .pages = vectors_page, @@ -114,6 +114,7 @@ static int __init vdso_init(void) { int i; + unsigned long pfn; if (memcmp(&vdso_start, "\177ELF", 4)) { pr_err("vDSO is not a valid ELF object!\n"); @@ -131,11 +132,14 @@ return -ENOMEM; /* Grab the vDSO data page. */ - vdso_pagelist[0] = virt_to_page(vdso_data); + vdso_pagelist[0] = phys_to_page(__pa_symbol(vdso_data)); + /* Grab the vDSO code pages. */ + pfn = sym_to_pfn(&vdso_start); + for (i = 0; i < vdso_pages; i++) - vdso_pagelist[i + 1] = virt_to_page(&vdso_start + i * PAGE_SIZE); + vdso_pagelist[i + 1] = pfn_to_page(pfn + i); /* Populate the special mapping structures */ vdso_spec[0] = (struct vm_special_mapping) { @@ -212,10 +216,16 @@ vdso_data->wtm_clock_nsec = tk->wall_to_monotonic.tv_nsec; if (!use_syscall) { + /* tkr_mono.cycle_last == tkr_raw.cycle_last */ vdso_data->cs_cycle_last = tk->tkr_mono.cycle_last; + vdso_data->raw_time_sec = tk->raw_sec; + vdso_data->raw_time_nsec = tk->tkr_raw.xtime_nsec; vdso_data->xtime_clock_sec = tk->xtime_sec; vdso_data->xtime_clock_nsec = tk->tkr_mono.xtime_nsec; - vdso_data->cs_mult = tk->tkr_mono.mult; + /* tkr_raw.xtime_nsec == 0 */ + vdso_data->cs_mono_mult = tk->tkr_mono.mult; + vdso_data->cs_raw_mult = tk->tkr_raw.mult; + /* tkr_mono.shift == tkr_raw.shift */ vdso_data->cs_shift = tk->tkr_mono.shift; } diff -ruw linux-4.4.115/arch/arm64/kernel/vmlinux.lds.S linux-4.4.115-fbx/arch/arm64/kernel/vmlinux.lds.S --- linux-4.4.115/arch/arm64/kernel/vmlinux.lds.S 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/arch/arm64/kernel/vmlinux.lds.S 2019-10-29 09:26:23.009196974 +0100 @@ -11,6 +11,7 @@ #include #include #include +#include #include "image.h" @@ -46,6 +47,27 @@ *(.idmap.text) \ VMLINUX_SYMBOL(__idmap_text_end) = .; +#ifdef CONFIG_HIBERNATION +#define HIBERNATE_TEXT \ + . = ALIGN(SZ_4K); \ + VMLINUX_SYMBOL(__hibernate_exit_text_start) = .;\ + *(.hibernate_exit.text) \ + VMLINUX_SYMBOL(__hibernate_exit_text_end) = .; +#else +#define HIBERNATE_TEXT +#endif + +#ifdef CONFIG_UNMAP_KERNEL_AT_EL0 +#define TRAMP_TEXT \ + . = ALIGN(PAGE_SIZE); \ + VMLINUX_SYMBOL(__entry_tramp_text_start) = .; \ + *(.entry.tramp.text) \ + . = ALIGN(PAGE_SIZE); \ + VMLINUX_SYMBOL(__entry_tramp_text_end) = .; +#else +#define TRAMP_TEXT +#endif + /* * The size of the PE/COFF section that covers the kernel image, which * runs from stext to _edata, must be a round multiple of the PE/COFF @@ -63,14 +85,19 @@ #endif #if defined(CONFIG_DEBUG_ALIGN_RODATA) -#define ALIGN_DEBUG_RO . = ALIGN(1<phys conversions will fail. */ -ASSERT(_text == (PAGE_OFFSET + TEXT_OFFSET), "HEAD is misaligned") +ASSERT(_text == (KIMAGE_VADDR + TEXT_OFFSET), "HEAD is misaligned") diff -ruw linux-4.4.115/arch/arm64/kvm/Makefile linux-4.4.115-fbx/arch/arm64/kvm/Makefile --- linux-4.4.115/arch/arm64/kvm/Makefile 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/arch/arm64/kvm/Makefile 2019-01-22 16:16:21.555228766 +0100 @@ -10,6 +10,7 @@ ARM=../../../arch/arm/kvm obj-$(CONFIG_KVM_ARM_HOST) += kvm.o +obj-$(CONFIG_KVM_ARM_HOST) += hyp/ kvm-$(CONFIG_KVM_ARM_HOST) += $(KVM)/kvm_main.o $(KVM)/coalesced_mmio.o $(KVM)/eventfd.o $(KVM)/vfio.o kvm-$(CONFIG_KVM_ARM_HOST) += $(ARM)/arm.o $(ARM)/mmu.o $(ARM)/mmio.o @@ -22,8 +23,6 @@ kvm-$(CONFIG_KVM_ARM_HOST) += $(KVM)/arm/vgic.o kvm-$(CONFIG_KVM_ARM_HOST) += $(KVM)/arm/vgic-v2.o kvm-$(CONFIG_KVM_ARM_HOST) += $(KVM)/arm/vgic-v2-emul.o -kvm-$(CONFIG_KVM_ARM_HOST) += vgic-v2-switch.o kvm-$(CONFIG_KVM_ARM_HOST) += $(KVM)/arm/vgic-v3.o kvm-$(CONFIG_KVM_ARM_HOST) += $(KVM)/arm/vgic-v3-emul.o -kvm-$(CONFIG_KVM_ARM_HOST) += vgic-v3-switch.o kvm-$(CONFIG_KVM_ARM_HOST) += $(KVM)/arm/arch_timer.o diff -ruw linux-4.4.115/arch/arm64/lib/clear_user.S linux-4.4.115-fbx/arch/arm64/lib/clear_user.S --- linux-4.4.115/arch/arm64/lib/clear_user.S 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/arch/arm64/lib/clear_user.S 2019-01-22 16:16:21.559228802 +0100 @@ -17,10 +17,7 @@ */ #include -#include -#include -#include -#include +#include .text @@ -33,29 +30,27 @@ * Alignment fixed up by hardware. */ ENTRY(__clear_user) -ALTERNATIVE("nop", __stringify(SET_PSTATE_PAN(0)), ARM64_HAS_PAN, \ - CONFIG_ARM64_PAN) + uaccess_enable_not_uao x2, x3, x4 mov x2, x1 // save the size for fixup return subs x1, x1, #8 b.mi 2f 1: -USER(9f, str xzr, [x0], #8 ) +uao_user_alternative 9f, str, sttr, xzr, x0, 8 subs x1, x1, #8 b.pl 1b 2: adds x1, x1, #4 b.mi 3f -USER(9f, str wzr, [x0], #4 ) +uao_user_alternative 9f, str, sttr, wzr, x0, 4 sub x1, x1, #4 3: adds x1, x1, #2 b.mi 4f -USER(9f, strh wzr, [x0], #2 ) +uao_user_alternative 9f, strh, sttrh, wzr, x0, 2 sub x1, x1, #2 4: adds x1, x1, #1 b.mi 5f -USER(9f, strb wzr, [x0] ) +uao_user_alternative 9f, strb, sttrb, wzr, x0, 0 5: mov x0, #0 -ALTERNATIVE("nop", __stringify(SET_PSTATE_PAN(1)), ARM64_HAS_PAN, \ - CONFIG_ARM64_PAN) + uaccess_disable_not_uao x2, x3 ret ENDPROC(__clear_user) diff -ruw linux-4.4.115/arch/arm64/lib/copy_from_user.S linux-4.4.115-fbx/arch/arm64/lib/copy_from_user.S --- linux-4.4.115/arch/arm64/lib/copy_from_user.S 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/arch/arm64/lib/copy_from_user.S 2019-01-22 16:16:21.559228802 +0100 @@ -16,11 +16,8 @@ #include -#include -#include #include -#include -#include +#include /* * Copy from user space to a kernel buffer (alignment handled by the hardware) @@ -34,7 +31,7 @@ */ .macro ldrb1 ptr, regB, val - USER(9998f, ldrb \ptr, [\regB], \val) + uao_user_alternative 9998f, ldrb, ldtrb, \ptr, \regB, \val .endm .macro strb1 ptr, regB, val @@ -42,7 +39,7 @@ .endm .macro ldrh1 ptr, regB, val - USER(9998f, ldrh \ptr, [\regB], \val) + uao_user_alternative 9998f, ldrh, ldtrh, \ptr, \regB, \val .endm .macro strh1 ptr, regB, val @@ -50,7 +47,7 @@ .endm .macro ldr1 ptr, regB, val - USER(9998f, ldr \ptr, [\regB], \val) + uao_user_alternative 9998f, ldr, ldtr, \ptr, \regB, \val .endm .macro str1 ptr, regB, val @@ -58,7 +55,7 @@ .endm .macro ldp1 ptr, regB, regC, val - USER(9998f, ldp \ptr, \regB, [\regC], \val) + uao_ldp 9998f, \ptr, \regB, \regC, \val .endm .macro stp1 ptr, regB, regC, val @@ -66,16 +63,14 @@ .endm end .req x5 -ENTRY(__copy_from_user) -ALTERNATIVE("nop", __stringify(SET_PSTATE_PAN(0)), ARM64_HAS_PAN, \ - CONFIG_ARM64_PAN) +ENTRY(__arch_copy_from_user) + uaccess_enable_not_uao x3, x4, x5 add end, x0, x2 #include "copy_template.S" -ALTERNATIVE("nop", __stringify(SET_PSTATE_PAN(1)), ARM64_HAS_PAN, \ - CONFIG_ARM64_PAN) + uaccess_disable_not_uao x3, x4 mov x0, #0 // Nothing to copy ret -ENDPROC(__copy_from_user) +ENDPROC(__arch_copy_from_user) .section .fixup,"ax" .align 2 diff -ruw linux-4.4.115/arch/arm64/lib/copy_in_user.S linux-4.4.115-fbx/arch/arm64/lib/copy_in_user.S --- linux-4.4.115/arch/arm64/lib/copy_in_user.S 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/arch/arm64/lib/copy_in_user.S 2019-01-22 16:16:21.559228802 +0100 @@ -18,11 +18,8 @@ #include -#include -#include #include -#include -#include +#include /* * Copy from user space to user space (alignment handled by the hardware) @@ -35,45 +32,43 @@ * x0 - bytes not copied */ .macro ldrb1 ptr, regB, val - USER(9998f, ldrb \ptr, [\regB], \val) + uao_user_alternative 9998f, ldrb, ldtrb, \ptr, \regB, \val .endm .macro strb1 ptr, regB, val - USER(9998f, strb \ptr, [\regB], \val) + uao_user_alternative 9998f, strb, sttrb, \ptr, \regB, \val .endm .macro ldrh1 ptr, regB, val - USER(9998f, ldrh \ptr, [\regB], \val) + uao_user_alternative 9998f, ldrh, ldtrh, \ptr, \regB, \val .endm .macro strh1 ptr, regB, val - USER(9998f, strh \ptr, [\regB], \val) + uao_user_alternative 9998f, strh, sttrh, \ptr, \regB, \val .endm .macro ldr1 ptr, regB, val - USER(9998f, ldr \ptr, [\regB], \val) + uao_user_alternative 9998f, ldr, ldtr, \ptr, \regB, \val .endm .macro str1 ptr, regB, val - USER(9998f, str \ptr, [\regB], \val) + uao_user_alternative 9998f, str, sttr, \ptr, \regB, \val .endm .macro ldp1 ptr, regB, regC, val - USER(9998f, ldp \ptr, \regB, [\regC], \val) + uao_ldp 9998f, \ptr, \regB, \regC, \val .endm .macro stp1 ptr, regB, regC, val - USER(9998f, stp \ptr, \regB, [\regC], \val) + uao_stp 9998f, \ptr, \regB, \regC, \val .endm end .req x5 ENTRY(__copy_in_user) -ALTERNATIVE("nop", __stringify(SET_PSTATE_PAN(0)), ARM64_HAS_PAN, \ - CONFIG_ARM64_PAN) + uaccess_enable_not_uao x3, x4, x5 add end, x0, x2 #include "copy_template.S" -ALTERNATIVE("nop", __stringify(SET_PSTATE_PAN(1)), ARM64_HAS_PAN, \ - CONFIG_ARM64_PAN) + uaccess_disable_not_uao x3, x4 mov x0, #0 ret ENDPROC(__copy_in_user) diff -ruw linux-4.4.115/arch/arm64/lib/copy_page.S linux-4.4.115-fbx/arch/arm64/lib/copy_page.S --- linux-4.4.115/arch/arm64/lib/copy_page.S 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/arch/arm64/lib/copy_page.S 2019-01-22 16:16:21.559228802 +0100 @@ -18,6 +18,8 @@ #include #include #include +#include +#include /* * Copy a page from src to dest (both are page aligned) @@ -27,20 +29,65 @@ * x1 - src */ ENTRY(copy_page) - /* Assume cache line size is 64 bytes. */ - prfm pldl1strm, [x1, #64] -1: ldp x2, x3, [x1] +alternative_if_not ARM64_HAS_NO_HW_PREFETCH + nop + nop +alternative_else + # Prefetch two cache lines ahead. + prfm pldl1strm, [x1, #128] + prfm pldl1strm, [x1, #256] +alternative_endif + + ldp x2, x3, [x1] ldp x4, x5, [x1, #16] ldp x6, x7, [x1, #32] ldp x8, x9, [x1, #48] - add x1, x1, #64 - prfm pldl1strm, [x1, #64] + ldp x10, x11, [x1, #64] + ldp x12, x13, [x1, #80] + ldp x14, x15, [x1, #96] + ldp x16, x17, [x1, #112] + + mov x18, #(PAGE_SIZE - 128) + add x1, x1, #128 +1: + subs x18, x18, #128 + +alternative_if_not ARM64_HAS_NO_HW_PREFETCH + nop +alternative_else + prfm pldl1strm, [x1, #384] +alternative_endif + stnp x2, x3, [x0] + ldp x2, x3, [x1] stnp x4, x5, [x0, #16] + ldp x4, x5, [x1, #16] stnp x6, x7, [x0, #32] + ldp x6, x7, [x1, #32] stnp x8, x9, [x0, #48] - add x0, x0, #64 - tst x1, #(PAGE_SIZE - 1) - b.ne 1b + ldp x8, x9, [x1, #48] + stnp x10, x11, [x0, #64] + ldp x10, x11, [x1, #64] + stnp x12, x13, [x0, #80] + ldp x12, x13, [x1, #80] + stnp x14, x15, [x0, #96] + ldp x14, x15, [x1, #96] + stnp x16, x17, [x0, #112] + ldp x16, x17, [x1, #112] + + add x0, x0, #128 + add x1, x1, #128 + + b.gt 1b + + stnp x2, x3, [x0] + stnp x4, x5, [x0, #16] + stnp x6, x7, [x0, #32] + stnp x8, x9, [x0, #48] + stnp x10, x11, [x0, #64] + stnp x12, x13, [x0, #80] + stnp x14, x15, [x0, #96] + stnp x16, x17, [x0, #112] + ret ENDPROC(copy_page) diff -ruw linux-4.4.115/arch/arm64/lib/copy_to_user.S linux-4.4.115-fbx/arch/arm64/lib/copy_to_user.S --- linux-4.4.115/arch/arm64/lib/copy_to_user.S 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/arch/arm64/lib/copy_to_user.S 2019-01-22 16:16:21.559228802 +0100 @@ -16,11 +16,8 @@ #include -#include -#include #include -#include -#include +#include /* * Copy to user space from a kernel buffer (alignment handled by the hardware) @@ -37,7 +34,7 @@ .endm .macro strb1 ptr, regB, val - USER(9998f, strb \ptr, [\regB], \val) + uao_user_alternative 9998f, strb, sttrb, \ptr, \regB, \val .endm .macro ldrh1 ptr, regB, val @@ -45,7 +42,7 @@ .endm .macro strh1 ptr, regB, val - USER(9998f, strh \ptr, [\regB], \val) + uao_user_alternative 9998f, strh, sttrh, \ptr, \regB, \val .endm .macro ldr1 ptr, regB, val @@ -53,7 +50,7 @@ .endm .macro str1 ptr, regB, val - USER(9998f, str \ptr, [\regB], \val) + uao_user_alternative 9998f, str, sttr, \ptr, \regB, \val .endm .macro ldp1 ptr, regB, regC, val @@ -61,20 +58,18 @@ .endm .macro stp1 ptr, regB, regC, val - USER(9998f, stp \ptr, \regB, [\regC], \val) + uao_stp 9998f, \ptr, \regB, \regC, \val .endm end .req x5 -ENTRY(__copy_to_user) -ALTERNATIVE("nop", __stringify(SET_PSTATE_PAN(0)), ARM64_HAS_PAN, \ - CONFIG_ARM64_PAN) +ENTRY(__arch_copy_to_user) + uaccess_enable_not_uao x3, x4, x5 add end, x0, x2 #include "copy_template.S" -ALTERNATIVE("nop", __stringify(SET_PSTATE_PAN(1)), ARM64_HAS_PAN, \ - CONFIG_ARM64_PAN) + uaccess_disable_not_uao x3, x4 mov x0, #0 ret -ENDPROC(__copy_to_user) +ENDPROC(__arch_copy_to_user) .section .fixup,"ax" .align 2 diff -ruw linux-4.4.115/arch/arm64/lib/Makefile linux-4.4.115-fbx/arch/arm64/lib/Makefile --- linux-4.4.115/arch/arm64/lib/Makefile 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/arch/arm64/lib/Makefile 2019-01-22 16:16:21.559228802 +0100 @@ -4,15 +4,16 @@ memcmp.o strcmp.o strncmp.o strlen.o strnlen.o \ strchr.o strrchr.o -# Tell the compiler to treat all general purpose registers as -# callee-saved, which allows for efficient runtime patching of the bl -# instruction in the caller with an atomic instruction when supported by -# the CPU. Result and argument registers are handled correctly, based on -# the function prototype. +# Tell the compiler to treat all general purpose registers (with the +# exception of the IP registers, which are already handled by the caller +# in case of a PLT) as callee-saved, which allows for efficient runtime +# patching of the bl instruction in the caller with an atomic instruction +# when supported by the CPU. Result and argument registers are handled +# correctly, based on the function prototype. lib-$(CONFIG_ARM64_LSE_ATOMICS) += atomic_ll_sc.o CFLAGS_atomic_ll_sc.o := -fcall-used-x0 -ffixed-x1 -ffixed-x2 \ -ffixed-x3 -ffixed-x4 -ffixed-x5 -ffixed-x6 \ -ffixed-x7 -fcall-saved-x8 -fcall-saved-x9 \ -fcall-saved-x10 -fcall-saved-x11 -fcall-saved-x12 \ -fcall-saved-x13 -fcall-saved-x14 -fcall-saved-x15 \ - -fcall-saved-x16 -fcall-saved-x17 -fcall-saved-x18 + -fcall-saved-x18 diff -ruw linux-4.4.115/arch/arm64/Makefile linux-4.4.115-fbx/arch/arm64/Makefile --- linux-4.4.115/arch/arm64/Makefile 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/arch/arm64/Makefile 2019-10-29 09:26:22.989196778 +0100 @@ -15,6 +15,10 @@ OBJCOPYFLAGS :=-O binary -R .note -R .note.gnu.build-id -R .comment -S GZFLAGS :=-9 +ifneq ($(CONFIG_RELOCATABLE),) +LDFLAGS_vmlinux += -pie -Bsymbolic +endif + KBUILD_DEFCONFIG := defconfig # Check for binutils support for specific extensions @@ -26,8 +30,17 @@ endif endif -KBUILD_CFLAGS += -mgeneral-regs-only $(lseinstr) +ifeq ($(cc-name),clang) +# This is a workaround for https://bugs.llvm.org/show_bug.cgi?id=30792. +# TODO: revert when this is fixed in LLVM. +KBUILD_CFLAGS += -mno-implicit-float +else +KBUILD_CFLAGS += -mgeneral-regs-only +endif +KBUILD_CFLAGS += $(lseinstr) +KBUILD_CFLAGS += -fno-pic KBUILD_CFLAGS += $(call cc-option, -mpc-relative-literal-loads) +KBUILD_CFLAGS += -fno-asynchronous-unwind-tables KBUILD_AFLAGS += $(lseinstr) ifeq ($(CONFIG_CPU_BIG_ENDIAN), y) @@ -42,10 +55,14 @@ CHECKFLAGS += -D__aarch64__ -ifeq ($(CONFIG_ARM64_ERRATUM_843419), y) +ifeq ($(CONFIG_ARM64_MODULE_CMODEL_LARGE), y) KBUILD_CFLAGS_MODULE += -mcmodel=large endif +ifeq ($(CONFIG_ARM64_MODULE_PLTS),y) +KBUILD_LDFLAGS_MODULE += -T $(srctree)/arch/arm64/kernel/module.lds +endif + # Default value head-y := arch/arm64/kernel/head.o @@ -56,6 +73,10 @@ TEXT_OFFSET := 0x00080000 endif +ifeq ($(cc-name),clang) +KBUILD_CFLAGS += $(call cc-disable-warning, asm-operand-widths) +endif + # KASAN_SHADOW_OFFSET = VA_START + (1 << (VA_BITS - 3)) - (1 << 61) # in 32-bit arithmetic KASAN_SHADOW_OFFSET := $(shell printf "0x%08x00000000\n" $$(( \ @@ -74,9 +95,18 @@ core-$(CONFIG_EFI_STUB) += $(objtree)/drivers/firmware/efi/libstub/lib.a # Default target when executing plain make +ifeq ($(CONFIG_BUILD_ARM64_APPENDED_DTB_IMAGE),y) +KBUILD_IMAGE := $(subst $\",,$(CONFIG_BUILD_ARM64_APPENDED_KERNEL_IMAGE_NAME)) +else KBUILD_IMAGE := Image.gz +endif + KBUILD_DTBS := dtbs +ifeq ($(CONFIG_BUILD_ARM64_DT_OVERLAY),y) +export DTC_FLAGS := -@ +endif + all: $(KBUILD_IMAGE) $(KBUILD_DTBS) boot := arch/arm64/boot @@ -101,6 +131,9 @@ dtbs_install: $(Q)$(MAKE) $(dtbinst)=$(boot)/dts +Image-dtb Image.gz-dtb: vmlinux scripts dtbs + $(Q)$(MAKE) $(build)=$(boot) $(boot)/$@ + PHONY += vdso_install vdso_install: $(Q)$(MAKE) $(build)=arch/arm64/kernel/vdso $@ @@ -110,6 +143,16 @@ $(Q)$(MAKE) $(clean)=$(boot) $(Q)$(MAKE) $(clean)=$(boot)/dts +# We need to generate vdso-offsets.h before compiling certain files in kernel/. +# In order to do that, we should use the archprepare target, but we can't since +# asm-offsets.h is included in some files used to generate vdso-offsets.h, and +# asm-offsets.h is built in prepare0, for which archprepare is a dependency. +# Therefore we need to generate the header after prepare0 has been made, hence +# this hack. +prepare: vdso_prepare +vdso_prepare: prepare0 + $(Q)$(MAKE) $(build)=arch/arm64/kernel/vdso include/generated/vdso-offsets.h + define archhelp echo '* Image.gz - Compressed kernel image (arch/$(ARCH)/boot/Image.gz)' echo ' Image - Uncompressed kernel image (arch/$(ARCH)/boot/Image)' diff -ruw linux-4.4.115/arch/arm64/mm/cache.S linux-4.4.115-fbx/arch/arm64/mm/cache.S --- linux-4.4.115/arch/arm64/mm/cache.S 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/arch/arm64/mm/cache.S 2019-01-22 16:16:21.559228802 +0100 @@ -23,8 +23,80 @@ #include #include #include +#include -#include "proc-macros.S" +/* + * __flush_dcache_all() + * + * Flush the whole D-cache. + * + * Corrupted registers: x0-x7, x9-x11 + */ +__flush_dcache_all: + dmb sy // ensure ordering with previous memory accesses + mrs x0, clidr_el1 // read clidr + and x3, x0, #0x7000000 // extract loc from clidr + lsr x3, x3, #23 // left align loc bit field + cbz x3, finished // if loc is 0, then no need to clean + mov x10, #0 // start clean at cache level 0 +loop1: + add x2, x10, x10, lsr #1 // work out 3x current cache level + lsr x1, x0, x2 // extract cache type bits from clidr + and x1, x1, #7 // mask of the bits for current cache only + cmp x1, #2 // see what cache we have at this level + b.lt skip // skip if no cache, or just i-cache + save_and_disable_irqs x9 // make CSSELR and CCSIDR access atomic + msr csselr_el1, x10 // select current cache level in csselr + isb // isb to sych the new cssr&csidr + mrs x1, ccsidr_el1 // read the new ccsidr + restore_irqs x9 + and x2, x1, #7 // extract the length of the cache lines + add x2, x2, #4 // add 4 (line length offset) + mov x4, #0x3ff + and x4, x4, x1, lsr #3 // find maximum number on the way size + clz w5, w4 // find bit position of way size increment + mov x7, #0x7fff + and x7, x7, x1, lsr #13 // extract max number of the index size +loop2: + mov x9, x4 // create working copy of max way size +loop3: + lsl x6, x9, x5 + orr x11, x10, x6 // factor way and cache number into x11 + lsl x6, x7, x2 + orr x11, x11, x6 // factor index number into x11 + dc cisw, x11 // clean & invalidate by set/way + subs x9, x9, #1 // decrement the way + b.ge loop3 + subs x7, x7, #1 // decrement the index + b.ge loop2 +skip: + add x10, x10, #2 // increment cache number + cmp x3, x10 + b.gt loop1 +finished: + mov x10, #0 // swith back to cache level 0 + msr csselr_el1, x10 // select current cache level in csselr + dsb sy + isb + ret +ENDPROC(__flush_dcache_all) + +/* + * flush_cache_all() + * + * Flush the entire cache system. The data cache flush is now achieved + * using atomic clean / invalidates working outwards from L1 cache. This + * is done using Set/Way based cache maintainance instructions. The + * instruction cache can still be invalidated back to the point of + * unification in a single instruction. + */ +ENTRY(flush_cache_all) + mov x12, lr + bl __flush_dcache_all + mov x0, #0 + ic ialluis // I+BTB cache invalidate + ret x12 +ENDPROC(flush_cache_all) /* * flush_icache_range(start,end) @@ -50,11 +122,12 @@ * - end - virtual end address of region */ ENTRY(__flush_cache_user_range) + uaccess_ttbr0_enable x2, x3, x4 dcache_line_size x2, x3 sub x3, x2, #1 bic x4, x0, x3 1: -USER(9f, dc cvau, x4 ) // clean D line to PoU +user_alt 9f, "dc cvau, x4", "dc civac, x4", ARM64_WORKAROUND_CLEAN_CACHE add x4, x4, x2 cmp x4, x1 b.lo 1b @@ -71,36 +144,44 @@ dsb ish isb mov x0, #0 +1: + uaccess_ttbr0_disable x1, x2 ret 9: mov x0, #-EFAULT - ret + b 1b ENDPROC(flush_icache_range) ENDPROC(__flush_cache_user_range) /* * __flush_dcache_area(kaddr, size) * - * Ensure that the data held in the page kaddr is written back to the - * page in question. + * Ensure that any D-cache lines for the interval [kaddr, kaddr+size) + * are cleaned and invalidated to the PoC. * * - kaddr - kernel address * - size - size in question */ ENTRY(__flush_dcache_area) - dcache_line_size x2, x3 - add x1, x0, x1 - sub x3, x2, #1 - bic x0, x0, x3 -1: dc civac, x0 // clean & invalidate D line / unified line - add x0, x0, x2 - cmp x0, x1 - b.lo 1b - dsb sy + dcache_by_line_op civac, sy, x0, x1, x2, x3 ret ENDPIPROC(__flush_dcache_area) /* + * __clean_dcache_area_pou(kaddr, size) + * + * Ensure that any D-cache lines for the interval [kaddr, kaddr+size) + * are cleaned to the PoU. + * + * - kaddr - kernel address + * - size - size in question + */ +ENTRY(__clean_dcache_area_pou) + dcache_by_line_op cvau, ish, x0, x1, x2, x3 + ret +ENDPROC(__clean_dcache_area_pou) + +/* * __inval_cache_range(start, end) * - start - start address of region * - end - end address of region @@ -113,7 +194,7 @@ * - start - virtual start address of region * - end - virtual end address of region */ -__dma_inv_range: +ENTRY(__dma_inv_range) dcache_line_size x2, x3 sub x3, x2, #1 tst x1, x3 // end cache line aligned? @@ -139,7 +220,7 @@ * - start - virtual start address of region * - end - virtual end address of region */ -__dma_clean_range: +ENTRY(__dma_clean_range) dcache_line_size x2, x3 sub x3, x2, #1 bic x0, x0, x3 diff -ruw linux-4.4.115/arch/arm64/mm/context.c linux-4.4.115-fbx/arch/arm64/mm/context.c --- linux-4.4.115/arch/arm64/mm/context.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/arch/arm64/mm/context.c 2019-01-22 16:16:21.559228802 +0100 @@ -38,7 +38,16 @@ #define ASID_MASK (~GENMASK(asid_bits - 1, 0)) #define ASID_FIRST_VERSION (1UL << asid_bits) -#define NUM_USER_ASIDS ASID_FIRST_VERSION + +#ifdef CONFIG_UNMAP_KERNEL_AT_EL0 +#define NUM_USER_ASIDS (ASID_FIRST_VERSION >> 1) +#define asid2idx(asid) (((asid) & ~ASID_MASK) >> 1) +#define idx2asid(idx) (((idx) << 1) & ~ASID_MASK) +#else +#define NUM_USER_ASIDS (ASID_FIRST_VERSION) +#define asid2idx(asid) ((asid) & ~ASID_MASK) +#define idx2asid(idx) asid2idx(idx) +#endif static void flush_context(unsigned int cpu) { @@ -65,7 +74,7 @@ */ if (asid == 0) asid = per_cpu(reserved_asids, i); - __set_bit(asid & ~ASID_MASK, asid_map); + __set_bit(asid2idx(asid), asid_map); per_cpu(reserved_asids, i) = asid; } @@ -120,16 +129,16 @@ * We had a valid ASID in a previous life, so try to re-use * it if possible. */ - asid &= ~ASID_MASK; - if (!__test_and_set_bit(asid, asid_map)) + if (!__test_and_set_bit(asid2idx(asid), asid_map)) return newasid; } /* * Allocate a free ASID. If we can't find one, take a note of the - * currently active ASIDs and mark the TLBs as requiring flushes. - * We always count from ASID #1, as we use ASID #0 when setting a - * reserved TTBR0 for the init_mm. + * currently active ASIDs and mark the TLBs as requiring flushes. We + * always count from ASID #2 (index 1), as we use ASID #0 when setting + * a reserved TTBR0 for the init_mm and we allocate ASIDs in even/odd + * pairs. */ asid = find_next_zero_bit(asid_map, NUM_USER_ASIDS, cur_idx); if (asid != NUM_USER_ASIDS) @@ -146,7 +155,7 @@ set_asid: __set_bit(asid, asid_map); cur_idx = asid; - return asid | generation; + return idx2asid(asid) | generation; } void check_and_switch_context(struct mm_struct *mm, unsigned int cpu) @@ -182,12 +191,29 @@ raw_spin_unlock_irqrestore(&cpu_asid_lock, flags); switch_mm_fastpath: + + arm64_apply_bp_hardening(); + + /* + * Defer TTBR0_EL1 setting for user threads to uaccess_enable() when + * emulating PAN. + */ + if (!system_uses_ttbr0_pan()) cpu_switch_mm(mm->pgd, mm); } +/* Errata workaround post TTBRx_EL1 update. */ +asmlinkage void post_ttbr_update_workaround(void) +{ + asm(ALTERNATIVE("nop; nop; nop", + "ic iallu; dsb nsh; isb", + ARM64_WORKAROUND_CAVIUM_27456, + CONFIG_CAVIUM_ERRATUM_27456)); +} + static int asids_init(void) { - int fld = cpuid_feature_extract_field(read_cpuid(ID_AA64MMFR0_EL1), 4); + int fld = cpuid_feature_extract_field(read_cpuid(SYS_ID_AA64MMFR0_EL1), 4); switch (fld) { default: diff -ruw linux-4.4.115/arch/arm64/mm/copypage.c linux-4.4.115-fbx/arch/arm64/mm/copypage.c --- linux-4.4.115/arch/arm64/mm/copypage.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/arch/arm64/mm/copypage.c 2019-01-22 16:16:21.559228802 +0100 @@ -24,8 +24,9 @@ void __cpu_copy_user_page(void *kto, const void *kfrom, unsigned long vaddr) { + struct page *page = virt_to_page(kto); copy_page(kto, kfrom); - __flush_dcache_area(kto, PAGE_SIZE); + flush_dcache_page(page); } EXPORT_SYMBOL_GPL(__cpu_copy_user_page); diff -ruw linux-4.4.115/arch/arm64/mm/dma-mapping.c linux-4.4.115-fbx/arch/arm64/mm/dma-mapping.c --- linux-4.4.115/arch/arm64/mm/dma-mapping.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/arch/arm64/mm/dma-mapping.c 2019-01-22 16:16:21.563228839 +0100 @@ -3,6 +3,7 @@ * * Copyright (C) 2012 ARM Ltd. * Author: Catalin Marinas + * Copyright (c) 2017, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as @@ -24,23 +25,51 @@ #include #include #include +#include +#include #include #include #include +#include +#include +#include +#include +#include + +#include "mm.h" + static pgprot_t __get_dma_pgprot(struct dma_attrs *attrs, pgprot_t prot, bool coherent) { - if (!coherent || dma_get_attr(DMA_ATTR_WRITE_COMBINE, attrs)) + if (dma_get_attr(DMA_ATTR_STRONGLY_ORDERED, attrs)) + return pgprot_noncached(prot); + else if (!coherent || dma_get_attr(DMA_ATTR_WRITE_COMBINE, attrs)) return pgprot_writecombine(prot); return prot; } -static struct gen_pool *atomic_pool; +static bool is_dma_coherent(struct device *dev, struct dma_attrs *attrs) +{ + bool is_coherent; + + if (dma_get_attr(DMA_ATTR_FORCE_COHERENT, attrs)) + is_coherent = true; + else if (dma_get_attr(DMA_ATTR_FORCE_NON_COHERENT, attrs)) + is_coherent = false; + else if (is_device_dma_coherent(dev)) + is_coherent = true; + else + is_coherent = false; + + return is_coherent; +} +static struct gen_pool *atomic_pool; +#define NO_KERNEL_MAPPING_DUMMY 0x2222 #define DEFAULT_DMA_COHERENT_POOL_SIZE SZ_256K -static size_t atomic_pool_size = DEFAULT_DMA_COHERENT_POOL_SIZE; +static size_t atomic_pool_size __initdata = DEFAULT_DMA_COHERENT_POOL_SIZE; static int __init early_coherent_pool(char *p) { @@ -86,10 +115,47 @@ return 1; } +static int __dma_update_pte(pte_t *pte, pgtable_t token, unsigned long addr, + void *data) +{ + struct page *page = virt_to_page(addr); + pgprot_t prot = *(pgprot_t *)data; + + set_pte(pte, mk_pte(page, prot)); + return 0; +} + +static int __dma_clear_pte(pte_t *pte, pgtable_t token, unsigned long addr, + void *data) +{ + pte_clear(&init_mm, addr, pte); + return 0; +} + +static void __dma_remap(struct page *page, size_t size, pgprot_t prot, + bool no_kernel_map) +{ + unsigned long start = (unsigned long) page_address(page); + unsigned end = start + size; + int (*func)(pte_t *pte, pgtable_t token, unsigned long addr, + void *data); + + if (no_kernel_map) + func = __dma_clear_pte; + else + func = __dma_update_pte; + + apply_to_page_range(&init_mm, start, size, func, &prot); + mb(); + flush_tlb_kernel_range(start, end); +} + static void *__dma_alloc_coherent(struct device *dev, size_t size, dma_addr_t *dma_handle, gfp_t flags, struct dma_attrs *attrs) { + void *addr; + if (dev == NULL) { WARN_ONCE(1, "Use an actual device structure for DMA allocation\n"); return NULL; @@ -100,7 +166,6 @@ flags |= GFP_DMA; if (dev_get_cma_area(dev) && gfpflags_allow_blocking(flags)) { struct page *page; - void *addr; page = dma_alloc_from_contiguous(dev, size >> PAGE_SHIFT, get_order(size)); @@ -110,10 +175,20 @@ *dma_handle = phys_to_dma(dev, page_to_phys(page)); addr = page_address(page); memset(addr, 0, size); - return addr; } else { - return swiotlb_alloc_coherent(dev, size, dma_handle, flags); + addr = swiotlb_alloc_coherent(dev, size, dma_handle, flags); } + + if (addr && (dma_get_attr(DMA_ATTR_NO_KERNEL_MAPPING, attrs) || + dma_get_attr(DMA_ATTR_STRONGLY_ORDERED, attrs))) { + /* + * flush the caches here because we can't later + */ + __dma_flush_range(addr, addr + size); + __dma_remap(virt_to_page(addr), size, 0, true); + } + + return addr; } static void __dma_free_coherent(struct device *dev, size_t size, @@ -123,11 +198,16 @@ bool freed; phys_addr_t paddr = dma_to_phys(dev, dma_handle); + size = PAGE_ALIGN(size); if (dev == NULL) { WARN_ONCE(1, "Use an actual device structure for DMA allocation\n"); return; } + if (dma_get_attr(DMA_ATTR_NO_KERNEL_MAPPING, attrs) || + dma_get_attr(DMA_ATTR_STRONGLY_ORDERED, attrs)) + __dma_remap(phys_to_page(paddr), size, PAGE_KERNEL, false); + freed = dma_release_from_contiguous(dev, phys_to_page(paddr), size >> PAGE_SHIFT); @@ -141,8 +221,7 @@ { struct page *page; void *ptr, *coherent_ptr; - bool coherent = is_device_dma_coherent(dev); - pgprot_t prot = __get_dma_pgprot(attrs, PAGE_KERNEL, false); + bool coherent = is_dma_coherent(dev, attrs); size = PAGE_ALIGN(size); @@ -164,16 +243,22 @@ if (coherent) return ptr; + if (dma_get_attr(DMA_ATTR_NO_KERNEL_MAPPING, attrs)) { + coherent_ptr = (void *)NO_KERNEL_MAPPING_DUMMY; + } else { + if (!dma_get_attr(DMA_ATTR_STRONGLY_ORDERED, attrs)) /* remove any dirty cache lines on the kernel alias */ __dma_flush_range(ptr, ptr + size); /* create a coherent mapping */ page = virt_to_page(ptr); coherent_ptr = dma_common_contiguous_remap(page, size, VM_USERMAP, - prot, NULL); + __get_dma_pgprot(attrs, + __pgprot(PROT_NORMAL_NC), false), + NULL); if (!coherent_ptr) goto no_map; - + } return coherent_ptr; no_map: @@ -191,9 +276,10 @@ size = PAGE_ALIGN(size); - if (!is_device_dma_coherent(dev)) { + if (!is_dma_coherent(dev, attrs)) { if (__free_from_pool(vaddr, size)) return; + if (!dma_get_attr(DMA_ATTR_NO_KERNEL_MAPPING, attrs)) vunmap(vaddr); } __dma_free_coherent(dev, size, swiotlb_addr, dma_handle, attrs); @@ -207,7 +293,7 @@ dma_addr_t dev_addr; dev_addr = swiotlb_map_page(dev, page, offset, size, dir, attrs); - if (!is_device_dma_coherent(dev)) + if (!is_dma_coherent(dev, attrs)) __dma_map_area(phys_to_virt(dma_to_phys(dev, dev_addr)), size, dir); return dev_addr; @@ -218,7 +304,7 @@ size_t size, enum dma_data_direction dir, struct dma_attrs *attrs) { - if (!is_device_dma_coherent(dev)) + if (!is_dma_coherent(dev, attrs)) __dma_unmap_area(phys_to_virt(dma_to_phys(dev, dev_addr)), size, dir); swiotlb_unmap_page(dev, dev_addr, size, dir, attrs); } @@ -231,7 +317,7 @@ int i, ret; ret = swiotlb_map_sg_attrs(dev, sgl, nelems, dir, attrs); - if (!is_device_dma_coherent(dev)) + if (!is_dma_coherent(dev, attrs)) for_each_sg(sgl, sg, ret, i) __dma_map_area(phys_to_virt(dma_to_phys(dev, sg->dma_address)), sg->length, dir); @@ -247,7 +333,7 @@ struct scatterlist *sg; int i; - if (!is_device_dma_coherent(dev)) + if (!is_dma_coherent(dev, attrs)) for_each_sg(sgl, sg, nelems, i) __dma_unmap_area(phys_to_virt(dma_to_phys(dev, sg->dma_address)), sg->length, dir); @@ -313,7 +399,7 @@ unsigned long off = vma->vm_pgoff; vma->vm_page_prot = __get_dma_pgprot(attrs, vma->vm_page_prot, - is_device_dma_coherent(dev)); + is_dma_coherent(dev, attrs)); if (dma_mmap_from_coherent(dev, vma, cpu_addr, size, &ret)) return ret; @@ -341,6 +427,55 @@ return ret; } +static void *arm64_dma_remap(struct device *dev, void *cpu_addr, + dma_addr_t handle, size_t size, + struct dma_attrs *attrs) +{ + struct page *page = phys_to_page(dma_to_phys(dev, handle)); + pgprot_t prot = __get_dma_pgprot(attrs, PAGE_KERNEL, false); + unsigned long offset = handle & ~PAGE_MASK; + struct vm_struct *area; + unsigned long addr; + + size = PAGE_ALIGN(size + offset); + + /* + * DMA allocation can be mapped to user space, so lets + * set VM_USERMAP flags too. + */ + area = get_vm_area(size, VM_USERMAP); + if (!area) + return NULL; + + addr = (unsigned long)area->addr; + area->phys_addr = __pfn_to_phys(page_to_pfn(page)); + + if (ioremap_page_range(addr, addr + size, area->phys_addr, prot)) { + vunmap((void *)addr); + return NULL; + } + return (void *)addr + offset; +} + +static void arm64_dma_unremap(struct device *dev, void *remapped_addr, + size_t size) +{ + struct vm_struct *area; + + size = PAGE_ALIGN(size); + remapped_addr = (void *)((unsigned long)remapped_addr & PAGE_MASK); + + area = find_vm_area(remapped_addr); + if (!area) { + WARN(1, "trying to free invalid coherent area: %p\n", + remapped_addr); + return; + } + vunmap(remapped_addr); + flush_tlb_kernel_range((unsigned long)remapped_addr, + (unsigned long)(remapped_addr + size)); +} + static struct dma_map_ops swiotlb_dma_ops = { .alloc = __dma_alloc, .free = __dma_free, @@ -356,6 +491,8 @@ .sync_sg_for_device = __swiotlb_sync_sg_for_device, .dma_supported = swiotlb_dma_supported, .mapping_error = swiotlb_dma_mapping_error, + .remap = arm64_dma_remap, + .unremap = arm64_dma_unremap, }; static int __init atomic_pool_init(void) @@ -406,7 +543,7 @@ goto out; remove_mapping: - dma_common_free_remap(addr, atomic_pool_size, VM_USERMAP); + dma_common_free_remap(addr, atomic_pool_size, VM_USERMAP, true); destroy_genpool: gen_pool_destroy(atomic_pool); atomic_pool = NULL; @@ -427,6 +564,7 @@ dma_addr_t *dma_handle, gfp_t flags, struct dma_attrs *attrs) { + WARN(1, "dma alloc failure, device may be missing a call to arch_setup_dma_ops"); return NULL; } @@ -542,7 +680,7 @@ dma_addr_t *handle, gfp_t gfp, struct dma_attrs *attrs) { - bool coherent = is_device_dma_coherent(dev); + bool coherent = is_dma_coherent(dev, attrs); int ioprot = dma_direction_to_prot(DMA_BIDIRECTIONAL, coherent); size_t iosize = size; void *addr; @@ -624,7 +762,7 @@ if (WARN_ON(!area || !area->pages)) return; iommu_dma_free(dev, area->pages, iosize, &handle); - dma_common_free_remap(cpu_addr, size, VM_USERMAP); + dma_common_free_remap(cpu_addr, size, VM_USERMAP, true); } else { iommu_dma_unmap_page(dev, handle, iosize, 0, NULL); __free_pages(virt_to_page(cpu_addr), get_order(size)); @@ -639,7 +777,7 @@ int ret; vma->vm_page_prot = __get_dma_pgprot(attrs, vma->vm_page_prot, - is_device_dma_coherent(dev)); + is_dma_coherent(dev, attrs)); if (dma_mmap_from_coherent(dev, vma, cpu_addr, size, &ret)) return ret; @@ -696,7 +834,7 @@ enum dma_data_direction dir, struct dma_attrs *attrs) { - bool coherent = is_device_dma_coherent(dev); + bool coherent = is_dma_coherent(dev, attrs); int prot = dma_direction_to_prot(dir, coherent); dma_addr_t dev_addr = iommu_dma_map_page(dev, page, offset, size, prot); @@ -749,7 +887,7 @@ int nelems, enum dma_data_direction dir, struct dma_attrs *attrs) { - bool coherent = is_device_dma_coherent(dev); + bool coherent = is_dma_coherent(dev, attrs); if (!dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs)) __iommu_sync_sg_for_device(dev, sgl, nelems, dir); @@ -782,7 +920,6 @@ .sync_single_for_device = __iommu_sync_single_for_device, .sync_sg_for_cpu = __iommu_sync_sg_for_cpu, .sync_sg_for_device = __iommu_sync_sg_for_device, - .dma_supported = iommu_dma_supported, .mapping_error = iommu_dma_mapping_error, }; @@ -896,7 +1033,7 @@ return 0; } -static int register_iommu_dma_ops_notifier(struct bus_type *bus) +static int __init register_iommu_dma_ops_notifier(struct bus_type *bus) { struct notifier_block *nb = kzalloc(sizeof(*nb), GFP_KERNEL); int ret; @@ -993,3 +1130,922 @@ dev->archdata.dma_coherent = coherent; __iommu_setup_dma_ops(dev, dma_base, size, iommu); } +EXPORT_SYMBOL(arch_setup_dma_ops); + +#ifdef CONFIG_ARM64_DMA_USE_IOMMU + +static int __get_iommu_pgprot(struct dma_attrs *attrs, int prot, + bool coherent) +{ + if (!dma_get_attr(DMA_ATTR_EXEC_MAPPING, attrs)) + prot |= IOMMU_NOEXEC; + if (coherent) + prot |= IOMMU_CACHE; + + return prot; +} + +/* + * Make an area consistent for devices. + * Note: Drivers should NOT use this function directly, as it will break + * platforms with CONFIG_DMABOUNCE. + * Use the driver DMA support - see dma-mapping.h (dma_sync_*) + */ +static void __dma_page_cpu_to_dev(struct page *page, unsigned long off, + size_t size, enum dma_data_direction dir) +{ + __dma_map_area(page_address(page) + off, size, dir); +} + +static void __dma_page_dev_to_cpu(struct page *page, unsigned long off, + size_t size, enum dma_data_direction dir) +{ + __dma_unmap_area(page_address(page) + off, size, dir); + + /* + * Mark the D-cache clean for this page to avoid extra flushing. + */ + if (dir != DMA_TO_DEVICE && off == 0 && size >= PAGE_SIZE) + set_bit(PG_dcache_clean, &page->flags); +} + +static int arm_dma_set_mask(struct device *dev, u64 dma_mask) +{ + if (!dev->dma_mask || !dma_supported(dev, dma_mask)) + return -EIO; + + *dev->dma_mask = dma_mask; + + return 0; +} + +/* IOMMU */ + +static void __dma_clear_buffer(struct page *page, size_t size, + struct dma_attrs *attrs, bool is_coherent) +{ + /* + * Ensure that the allocated pages are zeroed, and that any data + * lurking in the kernel direct-mapped region is invalidated. + */ + void *ptr = page_address(page); + if (!dma_get_attr(DMA_ATTR_SKIP_ZEROING, attrs)) + memset(ptr, 0, size); + if (!is_coherent) + dmac_flush_range(ptr, ptr + size); +} + +static inline dma_addr_t __alloc_iova(struct dma_iommu_mapping *mapping, + size_t size) +{ + unsigned int order = get_order(size); + unsigned int align = 0; + unsigned int count, start; + unsigned long flags; + + if (order > CONFIG_ARM64_DMA_IOMMU_ALIGNMENT) + order = CONFIG_ARM64_DMA_IOMMU_ALIGNMENT; + + count = PAGE_ALIGN(size) >> PAGE_SHIFT; + align = (1 << order) - 1; + + spin_lock_irqsave(&mapping->lock, flags); + start = bitmap_find_next_zero_area(mapping->bitmap, mapping->bits, 0, + count, align); + if (start > mapping->bits) { + spin_unlock_irqrestore(&mapping->lock, flags); + return DMA_ERROR_CODE; + } + + bitmap_set(mapping->bitmap, start, count); + spin_unlock_irqrestore(&mapping->lock, flags); + + return mapping->base + (start << PAGE_SHIFT); +} + +static inline void __free_iova(struct dma_iommu_mapping *mapping, + dma_addr_t addr, size_t size) +{ + unsigned int start = (addr - mapping->base) >> PAGE_SHIFT; + unsigned int count = size >> PAGE_SHIFT; + unsigned long flags; + + spin_lock_irqsave(&mapping->lock, flags); + bitmap_clear(mapping->bitmap, start, count); + spin_unlock_irqrestore(&mapping->lock, flags); +} + +static struct page **__iommu_alloc_buffer(struct device *dev, size_t size, + gfp_t gfp, struct dma_attrs *attrs) +{ + struct page **pages; + size_t count = size >> PAGE_SHIFT; + size_t array_size = count * sizeof(struct page *); + int i = 0; + bool is_coherent = is_dma_coherent(dev, attrs); + + if (array_size <= PAGE_SIZE) + pages = kzalloc(array_size, gfp); + else + pages = vzalloc(array_size); + if (!pages) + return NULL; + + if (dma_get_attr(DMA_ATTR_FORCE_CONTIGUOUS, attrs)) { + unsigned long order = get_order(size); + struct page *page; + + page = dma_alloc_from_contiguous(dev, count, order); + if (!page) + goto error; + + __dma_clear_buffer(page, size, attrs, is_coherent); + + for (i = 0; i < count; i++) + pages[i] = page + i; + + return pages; + } + + /* + * IOMMU can map any pages, so himem can also be used here + */ + gfp |= __GFP_NOWARN | __GFP_HIGHMEM; + + while (count) { + int j, order = __fls(count); + + pages[i] = alloc_pages(gfp, order); + while (!pages[i] && order) + pages[i] = alloc_pages(gfp, --order); + if (!pages[i]) + goto error; + + if (order) { + split_page(pages[i], order); + j = 1 << order; + while (--j) + pages[i + j] = pages[i] + j; + } + + __dma_clear_buffer(pages[i], PAGE_SIZE << order, attrs, + is_coherent); + i += 1 << order; + count -= 1 << order; + } + + return pages; +error: + while (i--) + if (pages[i]) + __free_pages(pages[i], 0); + if (array_size <= PAGE_SIZE) + kfree(pages); + else + vfree(pages); + return NULL; +} + +static int __iommu_free_buffer(struct device *dev, struct page **pages, + size_t size, struct dma_attrs *attrs) +{ + int count = size >> PAGE_SHIFT; + int array_size = count * sizeof(struct page *); + int i; + + if (dma_get_attr(DMA_ATTR_FORCE_CONTIGUOUS, attrs)) { + dma_release_from_contiguous(dev, pages[0], count); + } else { + for (i = 0; i < count; i++) + if (pages[i]) + __free_pages(pages[i], 0); + } + + if (array_size <= PAGE_SIZE) + kfree(pages); + else + vfree(pages); + return 0; +} + +/* + * Create a CPU mapping for a specified pages + */ +static void * +__iommu_alloc_remap(struct page **pages, size_t size, gfp_t gfp, pgprot_t prot, + const void *caller) +{ + return dma_common_pages_remap(pages, size, VM_USERMAP, prot, caller); +} + +/* + * Create a mapping in device IO address space for specified pages + */ +static dma_addr_t __iommu_create_mapping(struct device *dev, + struct page **pages, size_t size, + struct dma_attrs *attrs) +{ + struct dma_iommu_mapping *mapping = dev->archdata.mapping; + unsigned int count = PAGE_ALIGN(size) >> PAGE_SHIFT; + dma_addr_t dma_addr, iova; + int i, ret; + int prot = IOMMU_READ | IOMMU_WRITE; + + dma_addr = __alloc_iova(mapping, size); + if (dma_addr == DMA_ERROR_CODE) + return dma_addr; + prot = __get_iommu_pgprot(attrs, prot, + is_dma_coherent(dev, attrs)); + + iova = dma_addr; + for (i = 0; i < count; ) { + unsigned int next_pfn = page_to_pfn(pages[i]) + 1; + phys_addr_t phys = page_to_phys(pages[i]); + unsigned int len, j; + + for (j = i + 1; j < count; j++, next_pfn++) + if (page_to_pfn(pages[j]) != next_pfn) + break; + + len = (j - i) << PAGE_SHIFT; + ret = iommu_map(mapping->domain, iova, phys, len, prot); + if (ret < 0) + goto fail; + iova += len; + i = j; + } + return dma_addr; +fail: + iommu_unmap(mapping->domain, dma_addr, iova-dma_addr); + __free_iova(mapping, dma_addr, size); + return DMA_ERROR_CODE; +} + +static int __iommu_remove_mapping(struct device *dev, dma_addr_t iova, + size_t size) +{ + struct dma_iommu_mapping *mapping = dev->archdata.mapping; + + /* + * add optional in-page offset from iova to size and align + * result to page size + */ + size = PAGE_ALIGN((iova & ~PAGE_MASK) + size); + iova &= PAGE_MASK; + + iommu_unmap(mapping->domain, iova, size); + __free_iova(mapping, iova, size); + return 0; +} + +static struct page **__atomic_get_pages(void *addr) +{ + struct page *page; + phys_addr_t phys; + + phys = gen_pool_virt_to_phys(atomic_pool, (unsigned long)addr); + page = phys_to_page(phys); + + return (struct page **)page; +} + +static struct page **__iommu_get_pages(void *cpu_addr, struct dma_attrs *attrs) +{ + struct vm_struct *area; + + if (__in_atomic_pool(cpu_addr, PAGE_SIZE)) + return __atomic_get_pages(cpu_addr); + + if (dma_get_attr(DMA_ATTR_NO_KERNEL_MAPPING, attrs)) + return cpu_addr; + + area = find_vm_area(cpu_addr); + if (area) + return area->pages; + return NULL; +} + +static void *__iommu_alloc_atomic(struct device *dev, size_t size, + dma_addr_t *handle, gfp_t gfp, + struct dma_attrs *attrs) +{ + struct page *page; + struct page **pages; + size_t count = size >> PAGE_SHIFT; + size_t array_size = count * sizeof(struct page *); + int i; + void *addr; + bool coherent = is_dma_coherent(dev, attrs); + + if (array_size <= PAGE_SIZE) + pages = kzalloc(array_size, gfp); + else + pages = vzalloc(array_size); + + if (!pages) + return NULL; + + if (coherent) { + page = alloc_pages(gfp, get_order(size)); + addr = page ? page_address(page) : NULL; + } else { + addr = __alloc_from_pool(size, &page, gfp); + } + + if (!addr) + goto err_free; + + for (i = 0; i < count ; i++) + pages[i] = page + i; + + *handle = __iommu_create_mapping(dev, pages, size, attrs); + if (*handle == DMA_ERROR_CODE) + goto err_mapping; + + kvfree(pages); + return addr; + +err_mapping: + if (coherent) + __free_pages(page, get_order(size)); + else + __free_from_pool(addr, size); +err_free: + kvfree(pages); + return NULL; +} + +static void __iommu_free_atomic(struct device *dev, void *cpu_addr, + dma_addr_t handle, size_t size) +{ + __iommu_remove_mapping(dev, handle, size); + __free_from_pool(cpu_addr, size); +} + +static void *arm_iommu_alloc_attrs(struct device *dev, size_t size, + dma_addr_t *handle, gfp_t gfp, struct dma_attrs *attrs) +{ + bool coherent = is_dma_coherent(dev, attrs); + pgprot_t prot = __get_dma_pgprot(attrs, PAGE_KERNEL, coherent); + struct page **pages; + void *addr = NULL; + + *handle = DMA_ERROR_CODE; + size = PAGE_ALIGN(size); + + if (!gfpflags_allow_blocking(gfp)) + return __iommu_alloc_atomic(dev, size, handle, gfp, attrs); + + /* + * Following is a work-around (a.k.a. hack) to prevent pages + * with __GFP_COMP being passed to split_page() which cannot + * handle them. The real problem is that this flag probably + * should be 0 on ARM as it is not supported on this + * platform; see CONFIG_HUGETLBFS. + */ + gfp &= ~(__GFP_COMP); + + pages = __iommu_alloc_buffer(dev, size, gfp, attrs); + if (!pages) + return NULL; + + *handle = __iommu_create_mapping(dev, pages, size, attrs); + if (*handle == DMA_ERROR_CODE) + goto err_buffer; + + if (dma_get_attr(DMA_ATTR_NO_KERNEL_MAPPING, attrs)) + return pages; + + addr = __iommu_alloc_remap(pages, size, gfp, prot, + __builtin_return_address(0)); + if (!addr) + goto err_mapping; + + return addr; + +err_mapping: + __iommu_remove_mapping(dev, *handle, size); +err_buffer: + __iommu_free_buffer(dev, pages, size, attrs); + return NULL; +} + +static int arm_iommu_mmap_attrs(struct device *dev, struct vm_area_struct *vma, + void *cpu_addr, dma_addr_t dma_addr, size_t size, + struct dma_attrs *attrs) +{ + unsigned long uaddr = vma->vm_start; + unsigned long usize = vma->vm_end - vma->vm_start; + struct page **pages = __iommu_get_pages(cpu_addr, attrs); + bool coherent = is_dma_coherent(dev, attrs); + + vma->vm_page_prot = __get_dma_pgprot(attrs, vma->vm_page_prot, + coherent); + + if (!pages) + return -ENXIO; + + do { + int ret = vm_insert_page(vma, uaddr, *pages++); + if (ret) { + pr_err("Remapping memory failed: %d\n", ret); + return ret; + } + uaddr += PAGE_SIZE; + usize -= PAGE_SIZE; + } while (usize > 0); + + return 0; +} + +/* + * free a page as defined by the above mapping. + * Must not be called with IRQs disabled. + */ +void arm_iommu_free_attrs(struct device *dev, size_t size, void *cpu_addr, + dma_addr_t handle, struct dma_attrs *attrs) +{ + struct page **pages; + size = PAGE_ALIGN(size); + + if (__in_atomic_pool(cpu_addr, size)) { + __iommu_free_atomic(dev, cpu_addr, handle, size); + return; + } + + pages = __iommu_get_pages(cpu_addr, attrs); + if (!pages) { + WARN(1, "trying to free invalid coherent area: %p\n", cpu_addr); + return; + } + + if (!dma_get_attr(DMA_ATTR_NO_KERNEL_MAPPING, attrs)) + dma_common_free_remap(cpu_addr, size, VM_USERMAP, true); + + __iommu_remove_mapping(dev, handle, size); + __iommu_free_buffer(dev, pages, size, attrs); +} + +int arm_iommu_get_sgtable(struct device *dev, struct sg_table *sgt, + void *cpu_addr, dma_addr_t dma_addr, + size_t size, struct dma_attrs *attrs) +{ + unsigned int count = PAGE_ALIGN(size) >> PAGE_SHIFT; + struct page **pages = __iommu_get_pages(cpu_addr, attrs); + + if (!pages) + return -ENXIO; + + return sg_alloc_table_from_pages(sgt, pages, count, 0, size, + GFP_KERNEL); +} + +static int __dma_direction_to_prot(enum dma_data_direction dir) +{ + int prot; + + switch (dir) { + case DMA_BIDIRECTIONAL: + prot = IOMMU_READ | IOMMU_WRITE; + break; + case DMA_TO_DEVICE: + prot = IOMMU_READ; + break; + case DMA_FROM_DEVICE: + prot = IOMMU_WRITE; + break; + default: + prot = 0; + } + + return prot; +} + +/** + * arm_iommu_map_sg - map a set of SG buffers for streaming mode DMA + * @dev: valid struct device pointer + * @sg: list of buffers + * @nents: number of buffers to map + * @dir: DMA transfer direction + * + * Map a set of buffers described by scatterlist in streaming mode for DMA. + * The scatter gather list elements are merged together (if possible) and + * tagged with the appropriate dma address and length. They are obtained via + * sg_dma_{address,length}. + */ +int arm_iommu_map_sg(struct device *dev, struct scatterlist *sg, + int nents, enum dma_data_direction dir, struct dma_attrs *attrs) +{ + struct scatterlist *s; + int ret, i; + struct dma_iommu_mapping *mapping = dev->archdata.mapping; + unsigned int total_length = 0, current_offset = 0; + dma_addr_t iova; + int prot = __dma_direction_to_prot(dir); + + for_each_sg(sg, s, nents, i) + total_length += s->length; + + iova = __alloc_iova(mapping, total_length); + if (iova == DMA_ERROR_CODE) { + dev_err(dev, "Couldn't allocate iova for sg %p\n", sg); + return 0; + } + prot = __get_iommu_pgprot(attrs, prot, + is_dma_coherent(dev, attrs)); + + ret = iommu_map_sg(mapping->domain, iova, sg, nents, prot); + if (ret != total_length) { + __free_iova(mapping, iova, total_length); + return 0; + } + + for_each_sg(sg, s, nents, i) { + s->dma_address = iova + current_offset; + s->dma_length = total_length - current_offset; + current_offset += s->length; + } + + return nents; +} + +/** + * arm_iommu_unmap_sg - unmap a set of SG buffers mapped by dma_map_sg + * @dev: valid struct device pointer + * @sg: list of buffers + * @nents: number of buffers to unmap (same as was passed to dma_map_sg) + * @dir: DMA transfer direction (same as was passed to dma_map_sg) + * + * Unmap a set of streaming mode DMA translations. Again, CPU access + * rules concerning calls here are the same as for dma_unmap_single(). + */ +void arm_iommu_unmap_sg(struct device *dev, struct scatterlist *sg, int nents, + enum dma_data_direction dir, struct dma_attrs *attrs) +{ + struct dma_iommu_mapping *mapping = dev->archdata.mapping; + unsigned int total_length = sg_dma_len(sg); + dma_addr_t iova = sg_dma_address(sg); + + total_length = PAGE_ALIGN((iova & ~PAGE_MASK) + total_length); + iova &= PAGE_MASK; + + iommu_unmap(mapping->domain, iova, total_length); + __free_iova(mapping, iova, total_length); +} + +/** + * arm_iommu_sync_sg_for_cpu + * @dev: valid struct device pointer + * @sg: list of buffers + * @nents: number of buffers to map (returned from dma_map_sg) + * @dir: DMA transfer direction (same as was passed to dma_map_sg) + */ +void arm_iommu_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg, + int nents, enum dma_data_direction dir) +{ + struct scatterlist *s; + int i; + struct dma_iommu_mapping *mapping = dev->archdata.mapping; + dma_addr_t iova = sg_dma_address(sg); + bool iova_coherent = iommu_is_iova_coherent(mapping->domain, iova); + + if (iova_coherent) + return; + + for_each_sg(sg, s, nents, i) + __dma_page_dev_to_cpu(sg_page(s), s->offset, s->length, dir); + +} + +/** + * arm_iommu_sync_sg_for_device + * @dev: valid struct device pointer + * @sg: list of buffers + * @nents: number of buffers to map (returned from dma_map_sg) + * @dir: DMA transfer direction (same as was passed to dma_map_sg) + */ +void arm_iommu_sync_sg_for_device(struct device *dev, struct scatterlist *sg, + int nents, enum dma_data_direction dir) +{ + struct scatterlist *s; + int i; + struct dma_iommu_mapping *mapping = dev->archdata.mapping; + dma_addr_t iova = sg_dma_address(sg); + bool iova_coherent = iommu_is_iova_coherent(mapping->domain, iova); + + if (iova_coherent) + return; + + for_each_sg(sg, s, nents, i) + __dma_page_cpu_to_dev(sg_page(s), s->offset, s->length, dir); +} + + +/** + * arm_coherent_iommu_map_page + * @dev: valid struct device pointer + * @page: page that buffer resides in + * @offset: offset into page for start of buffer + * @size: size of buffer to map + * @dir: DMA transfer direction + * + * Coherent IOMMU aware version of arm_dma_map_page() + */ +static dma_addr_t arm_coherent_iommu_map_page(struct device *dev, + struct page *page, unsigned long offset, size_t size, + enum dma_data_direction dir, struct dma_attrs *attrs) +{ + struct dma_iommu_mapping *mapping = dev->archdata.mapping; + dma_addr_t dma_addr; + int ret, prot, len, start_offset, map_offset; + + map_offset = offset & ~PAGE_MASK; + start_offset = offset & PAGE_MASK; + len = PAGE_ALIGN(map_offset + size); + + dma_addr = __alloc_iova(mapping, len); + if (dma_addr == DMA_ERROR_CODE) + return dma_addr; + + prot = __dma_direction_to_prot(dir); + prot = __get_iommu_pgprot(attrs, prot, + is_dma_coherent(dev, attrs)); + + ret = iommu_map(mapping->domain, dma_addr, page_to_phys(page) + + start_offset, len, prot); + if (ret < 0) + goto fail; + + return dma_addr + map_offset; +fail: + __free_iova(mapping, dma_addr, len); + return DMA_ERROR_CODE; +} + +/** + * arm_iommu_map_page + * @dev: valid struct device pointer + * @page: page that buffer resides in + * @offset: offset into page for start of buffer + * @size: size of buffer to map + * @dir: DMA transfer direction + * + * IOMMU aware version of arm_dma_map_page() + */ +static dma_addr_t arm_iommu_map_page(struct device *dev, struct page *page, + unsigned long offset, size_t size, enum dma_data_direction dir, + struct dma_attrs *attrs) +{ + if (!is_dma_coherent(dev, attrs) && + !dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs)) + __dma_page_cpu_to_dev(page, offset, size, dir); + + return arm_coherent_iommu_map_page(dev, page, offset, size, dir, attrs); +} + +/** + * arm_iommu_unmap_page + * @dev: valid struct device pointer + * @handle: DMA address of buffer + * @size: size of buffer (same as passed to dma_map_page) + * @dir: DMA transfer direction (same as passed to dma_map_page) + * + * IOMMU aware version of arm_dma_unmap_page() + */ +static void arm_iommu_unmap_page(struct device *dev, dma_addr_t handle, + size_t size, enum dma_data_direction dir, + struct dma_attrs *attrs) +{ + struct dma_iommu_mapping *mapping = dev->archdata.mapping; + dma_addr_t iova = handle & PAGE_MASK; + struct page *page = phys_to_page(iommu_iova_to_phys( + mapping->domain, iova)); + int offset = handle & ~PAGE_MASK; + int len = PAGE_ALIGN(size + offset); + + if (!(is_dma_coherent(dev, attrs) || + dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs))) + __dma_page_dev_to_cpu(page, offset, size, dir); + + iommu_unmap(mapping->domain, iova, len); + __free_iova(mapping, iova, len); +} + +static void arm_iommu_sync_single_for_cpu(struct device *dev, + dma_addr_t handle, size_t size, enum dma_data_direction dir) +{ + struct dma_iommu_mapping *mapping = dev->archdata.mapping; + dma_addr_t iova = handle & PAGE_MASK; + struct page *page = phys_to_page(iommu_iova_to_phys( + mapping->domain, iova)); + unsigned int offset = handle & ~PAGE_MASK; + bool iova_coherent = iommu_is_iova_coherent(mapping->domain, handle); + + if (!iova_coherent) + __dma_page_dev_to_cpu(page, offset, size, dir); +} + +static void arm_iommu_sync_single_for_device(struct device *dev, + dma_addr_t handle, size_t size, enum dma_data_direction dir) +{ + struct dma_iommu_mapping *mapping = dev->archdata.mapping; + dma_addr_t iova = handle & PAGE_MASK; + struct page *page = phys_to_page(iommu_iova_to_phys( + mapping->domain, iova)); + unsigned int offset = handle & ~PAGE_MASK; + bool iova_coherent = iommu_is_iova_coherent(mapping->domain, handle); + + if (!iova_coherent) + __dma_page_cpu_to_dev(page, offset, size, dir); +} + +static int arm_iommu_dma_supported(struct device *dev, u64 mask) +{ + struct dma_iommu_mapping *mapping = to_dma_iommu_mapping(dev); + + if (!mapping) { + dev_warn(dev, "No IOMMU mapping for device\n"); + return 0; + } + + return iommu_dma_supported(mapping->domain, dev, mask); +} + +static int arm_iommu_mapping_error(struct device *dev, + dma_addr_t dma_addr) +{ + return dma_addr == DMA_ERROR_CODE; +} + +const struct dma_map_ops iommu_ops = { + .alloc = arm_iommu_alloc_attrs, + .free = arm_iommu_free_attrs, + .mmap = arm_iommu_mmap_attrs, + .get_sgtable = arm_iommu_get_sgtable, + + .map_page = arm_iommu_map_page, + .unmap_page = arm_iommu_unmap_page, + .sync_single_for_cpu = arm_iommu_sync_single_for_cpu, + .sync_single_for_device = arm_iommu_sync_single_for_device, + + .map_sg = arm_iommu_map_sg, + .unmap_sg = arm_iommu_unmap_sg, + .sync_sg_for_cpu = arm_iommu_sync_sg_for_cpu, + .sync_sg_for_device = arm_iommu_sync_sg_for_device, + + .set_dma_mask = arm_dma_set_mask, + .dma_supported = arm_iommu_dma_supported, + .mapping_error = arm_iommu_mapping_error, +}; + +/** + * arm_iommu_create_mapping + * @bus: pointer to the bus holding the client device (for IOMMU calls) + * @base: start address of the valid IO address space + * @size: maximum size of the valid IO address space + * + * Creates a mapping structure which holds information about used/unused + * IO address ranges, which is required to perform memory allocation and + * mapping with IOMMU aware functions. + * + * The client device need to be attached to the mapping with + * arm_iommu_attach_device function. + */ +struct dma_iommu_mapping * +arm_iommu_create_mapping(struct bus_type *bus, dma_addr_t base, size_t size) +{ + unsigned int bits = size >> PAGE_SHIFT; + unsigned int bitmap_size = BITS_TO_LONGS(bits) * sizeof(long); + struct dma_iommu_mapping *mapping; + int err = -ENOMEM; + + if (!bitmap_size) + return ERR_PTR(-EINVAL); + + mapping = kzalloc(sizeof(struct dma_iommu_mapping), GFP_KERNEL); + if (!mapping) + goto err; + + mapping->bitmap = kzalloc(bitmap_size, GFP_KERNEL | __GFP_NOWARN | + __GFP_NORETRY); + if (!mapping->bitmap) + mapping->bitmap = vzalloc(bitmap_size); + + if (!mapping->bitmap) + goto err2; + + mapping->base = base; + mapping->bits = bits; + spin_lock_init(&mapping->lock); + + mapping->domain = iommu_domain_alloc(bus); + if (!mapping->domain) + goto err3; + + kref_init(&mapping->kref); + return mapping; +err3: + kvfree(mapping->bitmap); +err2: + kfree(mapping); +err: + return ERR_PTR(err); +} +EXPORT_SYMBOL(arm_iommu_create_mapping); + +static void release_iommu_mapping(struct kref *kref) +{ + struct dma_iommu_mapping *mapping = + container_of(kref, struct dma_iommu_mapping, kref); + + iommu_domain_free(mapping->domain); + kvfree(mapping->bitmap); + kfree(mapping); +} + +void arm_iommu_release_mapping(struct dma_iommu_mapping *mapping) +{ + if (mapping) + kref_put(&mapping->kref, release_iommu_mapping); +} +EXPORT_SYMBOL(arm_iommu_release_mapping); + +/** + * arm_iommu_attach_device + * @dev: valid struct device pointer + * @mapping: io address space mapping structure (returned from + * arm_iommu_create_mapping) + * + * Attaches specified io address space mapping to the provided device, + * this replaces the dma operations (dma_map_ops pointer) with the + * IOMMU aware version. More than one client might be attached to + * the same io address space mapping. + */ +int arm_iommu_attach_device(struct device *dev, + struct dma_iommu_mapping *mapping) +{ + int err; + int s1_bypass = 0, is_fast = 0; + + iommu_domain_get_attr(mapping->domain, DOMAIN_ATTR_FAST, &is_fast); + if (is_fast) + return fast_smmu_attach_device(dev, mapping); + + err = iommu_attach_device(mapping->domain, dev); + if (err) + return err; + + iommu_domain_get_attr(mapping->domain, DOMAIN_ATTR_S1_BYPASS, + &s1_bypass); + + kref_get(&mapping->kref); + dev->archdata.mapping = mapping; + if (!s1_bypass) + set_dma_ops(dev, &iommu_ops); + + pr_debug("Attached IOMMU controller to %s device.\n", dev_name(dev)); + return 0; +} +EXPORT_SYMBOL(arm_iommu_attach_device); + +/** + * arm_iommu_detach_device + * @dev: valid struct device pointer + * + * Detaches the provided device from a previously attached map. + * This voids the dma operations (dma_map_ops pointer) + */ +void arm_iommu_detach_device(struct device *dev) +{ + struct dma_iommu_mapping *mapping; + int is_fast, s1_bypass = 0; + + mapping = to_dma_iommu_mapping(dev); + if (!mapping) { + dev_warn(dev, "Not attached\n"); + return; + } + + iommu_domain_get_attr(mapping->domain, DOMAIN_ATTR_FAST, &is_fast); + if (is_fast) { + fast_smmu_detach_device(dev, mapping); + return; + } + + iommu_domain_get_attr(mapping->domain, DOMAIN_ATTR_S1_BYPASS, + &s1_bypass); + + if (msm_dma_unmap_all_for_dev(dev)) + dev_warn(dev, "IOMMU detach with outstanding mappings\n"); + + iommu_detach_device(mapping->domain, dev); + kref_put(&mapping->kref, release_iommu_mapping); + dev->archdata.mapping = NULL; + if (!s1_bypass) + set_dma_ops(dev, NULL); + + pr_debug("Detached IOMMU controller from %s device.\n", dev_name(dev)); +} +EXPORT_SYMBOL(arm_iommu_detach_device); + +#endif diff -ruw linux-4.4.115/arch/arm64/mm/extable.c linux-4.4.115-fbx/arch/arm64/mm/extable.c --- linux-4.4.115/arch/arm64/mm/extable.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/arch/arm64/mm/extable.c 2019-01-22 16:16:21.563228839 +0100 @@ -11,7 +11,7 @@ fixup = search_exception_tables(instruction_pointer(regs)); if (fixup) - regs->pc = fixup->fixup; + regs->pc = (unsigned long)&fixup->fixup + fixup->fixup; return fixup != NULL; } diff -ruw linux-4.4.115/arch/arm64/mm/fault.c linux-4.4.115-fbx/arch/arm64/mm/fault.c --- linux-4.4.115/arch/arm64/mm/fault.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/arch/arm64/mm/fault.c 2019-10-29 09:26:23.009196974 +0100 @@ -40,9 +40,35 @@ #include #include #include +#include +#include + +#include static const char *fault_name(unsigned int esr); +#ifdef CONFIG_KPROBES +static inline int notify_page_fault(struct pt_regs *regs, unsigned int esr) +{ + int ret = 0; + + /* kprobe_running() needs smp_processor_id() */ + if (!user_mode(regs)) { + preempt_disable(); + if (kprobe_running() && kprobe_fault_handler(regs, esr)) + ret = 1; + preempt_enable(); + } + + return ret; +} +#else +static inline int notify_page_fault(struct pt_regs *regs, unsigned int esr) +{ + return 0; +} +#endif + /* * Dump out the page tables associated with 'addr' in mm 'mm'. */ @@ -133,6 +159,11 @@ } #endif +static bool is_el1_instruction_abort(unsigned int esr) +{ + return ESR_ELx_EC(esr) == ESR_ELx_EC_IABT_CUR; +} + /* * The kernel tried to access some page that wasn't present. */ @@ -141,8 +172,9 @@ { /* * Are we prepared to handle this kernel fault? + * We are almost certainly not prepared to handle instruction faults. */ - if (fixup_exception(regs)) + if (!is_el1_instruction_abort(esr) && fixup_exception(regs)) return; /* @@ -169,6 +201,8 @@ { struct siginfo si; + trace_user_fault(tsk, addr, esr); + if (unhandled_signal(tsk, sig) && show_unhandled_signals_ratelimited()) { pr_info("%s[%d]: unhandled %s (%d) at 0x%08lx, esr 0x%03x\n", tsk->comm, task_pid_nr(tsk), fault_name(esr), sig, @@ -204,8 +238,6 @@ #define VM_FAULT_BADMAP 0x010000 #define VM_FAULT_BADACCESS 0x020000 -#define ESR_LNX_EXEC (1 << 24) - static int __do_page_fault(struct mm_struct *mm, unsigned long addr, unsigned int mm_flags, unsigned long vm_flags, struct task_struct *tsk) @@ -244,6 +276,26 @@ return fault; } +static inline bool is_permission_fault(unsigned int esr, struct pt_regs *regs) +{ + unsigned int ec = ESR_ELx_EC(esr); + unsigned int fsc_type = esr & ESR_ELx_FSC_TYPE; + + if (ec != ESR_ELx_EC_DABT_CUR && ec != ESR_ELx_EC_IABT_CUR) + return false; + + if (system_uses_ttbr0_pan()) + return fsc_type == ESR_ELx_FSC_FAULT && + (regs->pstate & PSR_PAN_BIT); + else + return fsc_type == ESR_ELx_FSC_PERM; +} + +static bool is_el0_instruction_abort(unsigned int esr) +{ + return ESR_ELx_EC(esr) == ESR_ELx_EC_IABT_LOW; +} + static int __kprobes do_page_fault(unsigned long addr, unsigned int esr, struct pt_regs *regs) { @@ -253,6 +305,9 @@ unsigned long vm_flags = VM_READ | VM_WRITE | VM_EXEC; unsigned int mm_flags = FAULT_FLAG_ALLOW_RETRY | FAULT_FLAG_KILLABLE; + if (notify_page_fault(regs, esr)) + return 0; + tsk = current; mm = tsk->mm; @@ -270,19 +325,21 @@ if (user_mode(regs)) mm_flags |= FAULT_FLAG_USER; - if (esr & ESR_LNX_EXEC) { + if (is_el0_instruction_abort(esr)) { vm_flags = VM_EXEC; - } else if ((esr & ESR_ELx_WNR) && !(esr & ESR_ELx_CM)) { + } else if (((esr & ESR_ELx_WNR) && !(esr & ESR_ELx_CM)) || + ((esr & ESR_ELx_CM) && !(mm_flags & FAULT_FLAG_USER))) { vm_flags = VM_WRITE; mm_flags |= FAULT_FLAG_WRITE; } - /* - * PAN bit set implies the fault happened in kernel space, but not - * in the arch's user access functions. - */ - if (IS_ENABLED(CONFIG_ARM64_PAN) && (regs->pstate & PSR_PAN_BIT)) - goto no_context; + if (addr < USER_DS && is_permission_fault(esr, regs)) { + if (is_el1_instruction_abort(esr)) + die("Attempting to execute userspace memory", regs, esr); + + if (!search_exception_tables(regs->pc)) + die("Accessing user space memory outside uaccess.h routines", regs, esr); + } /* * As per x86, we may deadlock here. However, since the kernel only @@ -399,6 +456,19 @@ } /* + * TLB conflict is already handled in EL2. This rourtine should return zero + * so that, do_mem_abort would not crash kernel thinking TLB conflict not + * handled. +*/ +#ifdef CONFIG_QCOM_TLB_EL2_HANDLER +static int do_tlb_conf_fault(unsigned long addr, + unsigned int esr, + struct pt_regs *regs) +{ + return 0; +} +#endif +/* * First Level Translation Fault Handler * * We enter here because the first level page table doesn't contain a valid @@ -431,10 +501,11 @@ */ static int do_bad(unsigned long addr, unsigned int esr, struct pt_regs *regs) { + arm64_check_cache_ecc(NULL); return 1; } -static struct fault_info { +static const struct fault_info { int (*fn)(unsigned long addr, unsigned int esr, struct pt_regs *regs); int sig; int code; @@ -488,7 +559,11 @@ { do_bad, SIGBUS, 0, "unknown 45" }, { do_bad, SIGBUS, 0, "unknown 46" }, { do_bad, SIGBUS, 0, "unknown 47" }, +#ifdef CONFIG_QCOM_TLB_EL2_HANDLER + { do_tlb_conf_fault, SIGBUS, 0, "TLB conflict abort" }, +#else { do_bad, SIGBUS, 0, "TLB conflict abort" }, +#endif { do_bad, SIGBUS, 0, "unknown 49" }, { do_bad, SIGBUS, 0, "unknown 50" }, { do_bad, SIGBUS, 0, "unknown 51" }, @@ -534,6 +609,22 @@ arm64_notify_die("", regs, &info, esr); } +asmlinkage void __exception do_el0_ia_bp_hardening(unsigned long addr, + unsigned int esr, + struct pt_regs *regs) +{ + /* + * We've taken an instruction abort from userspace and not yet + * re-enabled IRQs. If the address is a kernel address, apply + * BP hardening prior to enabling IRQs and pre-emption. + */ + if (addr > TASK_SIZE) + arm64_apply_bp_hardening(); + + local_irq_enable(); + do_mem_abort(addr, esr, regs); +} + /* * Handle stack alignment exceptions. */ @@ -609,6 +700,7 @@ return 0; } +NOKPROBE_SYMBOL(do_debug_exception); #ifdef CONFIG_ARM64_PAN int cpu_enable_pan(void *__unused) @@ -624,3 +716,17 @@ return 0; } #endif /* CONFIG_ARM64_PAN */ + +#ifdef CONFIG_ARM64_UAO +/* + * Kernel threads have fs=KERNEL_DS by default, and don't need to call + * set_fs(), devtmpfs in particular relies on this behaviour. + * We need to enable the feature at runtime (instead of adding it to + * PSR_MODE_EL1h) as the feature may not be implemented by the cpu. + */ +int cpu_enable_uao(void *__unused) +{ + asm(SET_PSTATE_UAO(1)); + return 0; +} +#endif /* CONFIG_ARM64_UAO */ diff -ruw linux-4.4.115/arch/arm64/mm/flush.c linux-4.4.115-fbx/arch/arm64/mm/flush.c --- linux-4.4.115/arch/arm64/mm/flush.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/arch/arm64/mm/flush.c 2019-10-29 09:26:23.013197013 +0100 @@ -34,19 +34,24 @@ __flush_icache_all(); } -static void flush_ptrace_access(struct vm_area_struct *vma, struct page *page, - unsigned long uaddr, void *kaddr, - unsigned long len) +static void sync_icache_aliases(void *kaddr, unsigned long len) { - if (vma->vm_flags & VM_EXEC) { unsigned long addr = (unsigned long)kaddr; + if (icache_is_aliasing()) { - __flush_dcache_area(kaddr, len); + __clean_dcache_area_pou(kaddr, len); __flush_icache_all(); } else { flush_icache_range(addr, addr + len); } } + +static void flush_ptrace_access(struct vm_area_struct *vma, struct page *page, + unsigned long uaddr, void *kaddr, + unsigned long len) +{ + if (vma->vm_flags & VM_EXEC) + sync_icache_aliases(kaddr, len); } /* @@ -74,13 +79,11 @@ if (!page_mapping(page)) return; - if (!test_and_set_bit(PG_dcache_clean, &page->flags)) { - __flush_dcache_area(page_address(page), + if (!test_and_set_bit(PG_dcache_clean, &page->flags)) + sync_icache_aliases(page_address(page), PAGE_SIZE << compound_order(page)); + else if (icache_is_aivivt()) __flush_icache_all(); - } else if (icache_is_aivivt()) { - __flush_icache_all(); - } } /* @@ -98,6 +101,7 @@ /* * Additional functions defined in assembly. */ +EXPORT_SYMBOL(flush_cache_all); EXPORT_SYMBOL(flush_icache_range); #ifdef CONFIG_TRANSPARENT_HUGEPAGE diff -ruw linux-4.4.115/arch/arm64/mm/init.c linux-4.4.115-fbx/arch/arm64/mm/init.c --- linux-4.4.115/arch/arm64/mm/init.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/arch/arm64/mm/init.c 2019-10-29 09:26:23.013197013 +0100 @@ -34,8 +34,12 @@ #include #include #include +#include +#include #include +#include +#include #include #include #include @@ -45,7 +49,13 @@ #include "mm.h" -phys_addr_t memstart_addr __read_mostly = 0; +/* + * We need to be able to catch inadvertent references to memstart_addr + * that occur (potentially in generic code) before arm64_memblock_init() + * executes, which assigns it its actual value. So use a default value + * that cannot be mistaken for a real physical address. + */ +s64 memstart_addr __read_mostly = -1; phys_addr_t arm64_dma_phys_limit __read_mostly; #ifdef CONFIG_BLK_DEV_INITRD @@ -58,8 +68,8 @@ if (*endp == ',') { size = memparse(endp + 1, NULL); - initrd_start = (unsigned long)__va(start); - initrd_end = (unsigned long)__va(start + size); + initrd_start = start; + initrd_end = start + size; } return 0; } @@ -71,7 +81,7 @@ * currently assumes that for memory starting above 4G, 32-bit devices will * use a DMA offset. */ -static phys_addr_t max_zone_dma_phys(void) +static phys_addr_t __init max_zone_dma_phys(void) { phys_addr_t offset = memblock_start_of_DRAM() & GENMASK_ULL(63, 32); return min(offset + (1ULL << 32), memblock_end_of_DRAM()); @@ -118,19 +128,21 @@ } #ifdef CONFIG_HAVE_ARCH_PFN_VALID +#define PFN_MASK ((1UL << (64 - PAGE_SHIFT)) - 1) + int pfn_valid(unsigned long pfn) { - return memblock_is_memory(pfn << PAGE_SHIFT); + return (pfn & PFN_MASK) == pfn && memblock_is_map_memory(pfn << PAGE_SHIFT); } EXPORT_SYMBOL(pfn_valid); #endif #ifndef CONFIG_SPARSEMEM -static void arm64_memory_present(void) +static void __init arm64_memory_present(void) { } #else -static void arm64_memory_present(void) +static void __init arm64_memory_present(void) { struct memblock_region *reg; @@ -141,6 +153,7 @@ #endif static phys_addr_t memory_limit = (phys_addr_t)ULLONG_MAX; +static phys_addr_t bootloader_memory_limit; /* * Limit the memory size that was specified via FDT. @@ -159,16 +172,80 @@ void __init arm64_memblock_init(void) { + const s64 linear_region_size = -(s64)PAGE_OFFSET; + + /* + * Ensure that the linear region takes up exactly half of the kernel + * virtual address space. This way, we can distinguish a linear address + * from a kernel/module/vmalloc address by testing a single bit. + */ + BUILD_BUG_ON(linear_region_size != BIT(VA_BITS - 1)); + + /* + * Select a suitable value for the base of physical memory. + */ + memstart_addr = round_down(memblock_start_of_DRAM(), + ARM64_MEMSTART_ALIGN); + + /* + * Remove the memory that we will not be able to cover with the + * linear mapping. Take care not to clip the kernel which may be + * high in memory. + */ + memblock_remove(max_t(u64, memstart_addr + linear_region_size, + __pa_symbol(_end)), ULLONG_MAX); + if (memstart_addr + linear_region_size < memblock_end_of_DRAM()) { + /* ensure that memstart_addr remains sufficiently aligned */ + memstart_addr = round_up(memblock_end_of_DRAM() - linear_region_size, + ARM64_MEMSTART_ALIGN); + memblock_remove(0, memstart_addr); + } + + /* + * Apply the memory limit if it was set. Since the kernel may be loaded + * high up in memory, add back the kernel region that must be accessible + * via the linear mapping. + */ + if (memory_limit != (phys_addr_t)ULLONG_MAX) { + /* + * Save bootloader imposed memory limit before we overwirte + * memblock. + */ + bootloader_memory_limit = memblock_end_of_DRAM(); memblock_enforce_memory_limit(memory_limit); + memblock_add(__pa_symbol(_text), (u64)(_end - _text)); + } + + if (IS_ENABLED(CONFIG_RANDOMIZE_BASE)) { + extern u16 memstart_offset_seed; + u64 range = linear_region_size - + (memblock_end_of_DRAM() - memblock_start_of_DRAM()); + + /* + * If the size of the linear region exceeds, by a sufficient + * margin, the size of the region that the available physical + * memory spans, randomize the linear region as well. + */ + if (memstart_offset_seed > 0 && range >= ARM64_MEMSTART_ALIGN) { + range = range / ARM64_MEMSTART_ALIGN + 1; + memstart_addr -= ARM64_MEMSTART_ALIGN * + ((range * memstart_offset_seed) >> 16); + } + } /* * Register the kernel text, kernel data, initrd, and initial * pagetables with memblock. */ - memblock_reserve(__pa(_text), _end - _text); + memblock_reserve(__pa_symbol(_text), _end - _text); #ifdef CONFIG_BLK_DEV_INITRD - if (initrd_start) - memblock_reserve(__virt_to_phys(initrd_start), initrd_end - initrd_start); + if (initrd_start) { + memblock_reserve(initrd_start, initrd_end - initrd_start); + + /* the generic initrd code expects virtual addresses */ + initrd_start = __phys_to_virt(initrd_start); + initrd_end = __phys_to_virt(initrd_end); + } #endif early_init_fdt_scan_reserved_mem(); @@ -302,35 +379,38 @@ #ifdef CONFIG_KASAN " kasan : 0x%16lx - 0x%16lx (%6ld GB)\n" #endif + " modules : 0x%16lx - 0x%16lx (%6ld MB)\n" " vmalloc : 0x%16lx - 0x%16lx (%6ld GB)\n" + " .init : 0x%p" " - 0x%p" " (%6ld KB)\n" + " .text : 0x%p" " - 0x%p" " (%6ld KB)\n" + " .rodata : 0x%p" " - 0x%p" " (%6ld KB)\n" + " .data : 0x%p" " - 0x%p" " (%6ld KB)\n" #ifdef CONFIG_SPARSEMEM_VMEMMAP " vmemmap : 0x%16lx - 0x%16lx (%6ld GB maximum)\n" " 0x%16lx - 0x%16lx (%6ld MB actual)\n" #endif " fixed : 0x%16lx - 0x%16lx (%6ld KB)\n" " PCI I/O : 0x%16lx - 0x%16lx (%6ld MB)\n" - " modules : 0x%16lx - 0x%16lx (%6ld MB)\n" - " memory : 0x%16lx - 0x%16lx (%6ld MB)\n" - " .init : 0x%p" " - 0x%p" " (%6ld KB)\n" - " .text : 0x%p" " - 0x%p" " (%6ld KB)\n" - " .data : 0x%p" " - 0x%p" " (%6ld KB)\n", + " memory : 0x%16lx - 0x%16lx (%6ld MB)\n", #ifdef CONFIG_KASAN MLG(KASAN_SHADOW_START, KASAN_SHADOW_END), #endif + MLM(MODULES_VADDR, MODULES_END), MLG(VMALLOC_START, VMALLOC_END), + MLK_ROUNDUP(__init_begin, __init_end), + MLK_ROUNDUP(_text, _etext), + MLK_ROUNDUP(__start_rodata, __init_begin), + MLK_ROUNDUP(_sdata, _edata), #ifdef CONFIG_SPARSEMEM_VMEMMAP MLG(VMEMMAP_START, VMEMMAP_START + VMEMMAP_SIZE), - MLM((unsigned long)virt_to_page(PAGE_OFFSET), + MLM((unsigned long)phys_to_page(memblock_start_of_DRAM()), (unsigned long)virt_to_page(high_memory)), #endif MLK(FIXADDR_START, FIXADDR_TOP), MLM(PCI_IO_START, PCI_IO_END), - MLM(MODULES_VADDR, MODULES_END), - MLM(PAGE_OFFSET, (unsigned long)high_memory), - MLK_ROUNDUP(__init_begin, __init_end), - MLK_ROUNDUP(_text, _etext), - MLK_ROUNDUP(_sdata, _edata)); + MLM(__phys_to_virt(memblock_start_of_DRAM()), + (unsigned long)high_memory)); #undef MLK #undef MLM @@ -356,11 +436,15 @@ } } +static inline void poison_init_mem(void *s, size_t count) +{ + memset(s, 0, count); +} + void free_initmem(void) { - fixup_init(); free_initmem_default(0); - free_alternatives_memory(); + fixup_init(); } #ifdef CONFIG_BLK_DEV_INITRD @@ -381,3 +465,174 @@ __setup("keepinitrd", keepinitrd_setup); #endif + +#ifdef CONFIG_KERNEL_TEXT_RDONLY +void set_kernel_text_ro(void) +{ + unsigned long start = PFN_ALIGN(_stext); + unsigned long end = PFN_ALIGN(_etext); + + /* + * Set the kernel identity mapping for text RO. + */ + set_memory_ro(start, (end - start) >> PAGE_SHIFT); +} +#endif +/* + * Dump out memory limit information on panic. + */ +static int dump_mem_limit(struct notifier_block *self, unsigned long v, void *p) +{ + if (memory_limit != (phys_addr_t)ULLONG_MAX) { + pr_emerg("Memory Limit: %llu MB\n", memory_limit >> 20); + } else { + pr_emerg("Memory Limit: none\n"); + } + return 0; +} + +static struct notifier_block mem_limit_notifier = { + .notifier_call = dump_mem_limit, +}; + +static int __init register_mem_limit_dumper(void) +{ + atomic_notifier_chain_register(&panic_notifier_list, + &mem_limit_notifier); + return 0; +} +__initcall(register_mem_limit_dumper); + +#ifdef CONFIG_MEMORY_HOTPLUG +int arch_add_memory(int nid, u64 start, u64 size, bool for_device) +{ + pg_data_t *pgdat; + struct zone *zone; + unsigned long start_pfn = start >> PAGE_SHIFT; + unsigned long nr_pages = size >> PAGE_SHIFT; + unsigned long end_pfn = start_pfn + nr_pages; + unsigned long max_sparsemem_pfn = 1UL << (MAX_PHYSMEM_BITS-PAGE_SHIFT); + int ret; + + if (end_pfn > max_sparsemem_pfn) { + pr_err("end_pfn too big"); + return -1; + } + hotplug_paging(start, size); + + /* + * Mark the first page in the range as unusable. This is needed + * because __add_section (within __add_pages) wants pfn_valid + * of it to be false, and in arm64 pfn falid is implemented by + * just checking at the nomap flag for existing blocks. + * + * A small trick here is that __add_section() requires only + * phys_start_pfn (that is the first pfn of a section) to be + * invalid. Regardless of whether it was assumed (by the function + * author) that all pfns within a section are either all valid + * or all invalid, it allows to avoid looping twice (once here, + * second when memblock_clear_nomap() is called) through all + * pfns of the section and modify only one pfn. Thanks to that, + * further, in __add_zone() only this very first pfn is skipped + * and corresponding page is not flagged reserved. Therefore it + * is enough to correct this setup only for it. + * + * When arch_add_memory() returns the walk_memory_range() function + * is called and passed with online_memory_block() callback, + * which execution finally reaches the memory_block_action() + * function, where also only the first pfn of a memory block is + * checked to be reserved. Above, it was first pfn of a section, + * here it is a block but + * (drivers/base/memory.c): + * sections_per_block = block_sz / MIN_MEMORY_BLOCK_SIZE; + * (include/linux/memory.h): + * #define MIN_MEMORY_BLOCK_SIZE (1UL << SECTION_SIZE_BITS) + * so we can consider block and section equivalently + */ + memblock_mark_nomap(start, 1<node_zones + + zone_for_memory(nid, start, size, ZONE_NORMAL, for_device); + ret = __add_pages(nid, zone, start_pfn, nr_pages); + + /* + * Make the pages usable after they have been added. + * This will make pfn_valid return true + */ + memblock_clear_nomap(start, 1<> PAGE_SHIFT; + unsigned long nr_pages = size >> PAGE_SHIFT; + struct page *page = pfn_to_page(start_pfn); + struct zone *zone; + int ret = 0; + + zone = page_zone(page); + ret = __remove_pages(zone, start_pfn, nr_pages); + WARN_ON_ONCE(ret); + + kernel_physical_mapping_remove(start, start + size); + + return ret; +} + +#endif /* CONFIG_MEMORY_HOTREMOVE */ +static int arm64_online_page(struct page *page) +{ + unsigned long target_pfn = page_to_pfn(page); + unsigned long limit = __phys_to_pfn(bootloader_memory_limit); + + if (target_pfn >= limit) + return -EINVAL; + + __online_page_set_limits(page); + __online_page_increment_counters(page); + __online_page_free(page); + + return 0; +} + +static int __init arm64_memory_hotplug_init(void) +{ + set_online_page_callback(&arm64_online_page); + return 0; +} +subsys_initcall(arm64_memory_hotplug_init); +#endif /* CONFIG_MEMORY_HOTPLUG */ diff -ruw linux-4.4.115/arch/arm64/mm/mmap.c linux-4.4.115-fbx/arch/arm64/mm/mmap.c --- linux-4.4.115/arch/arm64/mm/mmap.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/arch/arm64/mm/mmap.c 2019-01-22 16:16:21.563228839 +0100 @@ -51,8 +51,12 @@ { unsigned long rnd; - rnd = (unsigned long)get_random_int() & STACK_RND_MASK; - +#ifdef CONFIG_COMPAT + if (test_thread_flag(TIF_32BIT)) + rnd = get_random_long() & ((1UL << mmap_rnd_compat_bits) - 1); + else +#endif + rnd = get_random_long() & ((1UL << mmap_rnd_bits) - 1); return rnd << PAGE_SHIFT; } diff -ruw linux-4.4.115/arch/arm64/mm/mmu.c linux-4.4.115-fbx/arch/arm64/mm/mmu.c --- linux-4.4.115/arch/arm64/mm/mmu.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/arch/arm64/mm/mmu.c 2019-10-29 09:26:23.013197013 +0100 @@ -29,9 +29,14 @@ #include #include #include +#include +#include +#include +#include #include #include +#include #include #include #include @@ -44,13 +49,22 @@ u64 idmap_t0sz = TCR_T0SZ(VA_BITS); +u64 kimage_voffset __read_mostly; +EXPORT_SYMBOL(kimage_voffset); + /* * Empty_zero_page is a special page that is used for zero-initialized data * and COW. */ -struct page *empty_zero_page; +unsigned long empty_zero_page[PAGE_SIZE / sizeof(unsigned long)] __page_aligned_bss; EXPORT_SYMBOL(empty_zero_page); +static pte_t bm_pte[PTRS_PER_PTE] __page_aligned_bss; +static pmd_t bm_pmd[PTRS_PER_PMD] __page_aligned_bss __maybe_unused; +static pud_t bm_pud[PTRS_PER_PUD] __page_aligned_bss __maybe_unused; + +static bool dma_overlap(phys_addr_t start, phys_addr_t end); + pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn, unsigned long size, pgprot_t vma_prot) { @@ -62,16 +76,30 @@ } EXPORT_SYMBOL(phys_mem_access_prot); -static void __init *early_alloc(unsigned long sz) +static phys_addr_t __init early_pgtable_alloc(void) { phys_addr_t phys; void *ptr; - phys = memblock_alloc(sz, sz); + phys = memblock_alloc(PAGE_SIZE, PAGE_SIZE); BUG_ON(!phys); - ptr = __va(phys); - memset(ptr, 0, sz); - return ptr; + + /* + * The FIX_{PGD,PUD,PMD} slots may be in active use, but the FIX_PTE + * slot will be free, so we can (ab)use the FIX_PTE slot to initialise + * any level of table. + */ + ptr = pte_set_fixmap(phys); + + memset(ptr, 0, PAGE_SIZE); + + /* + * Implicit barriers also ensure the zeroed page is visible to the page + * table walker + */ + pte_clear_fixmap(); + + return phys; } /* @@ -95,24 +123,30 @@ static void alloc_init_pte(pmd_t *pmd, unsigned long addr, unsigned long end, unsigned long pfn, pgprot_t prot, - void *(*alloc)(unsigned long size)) + phys_addr_t (*pgtable_alloc)(void)) { pte_t *pte; if (pmd_none(*pmd) || pmd_sect(*pmd)) { - pte = alloc(PTRS_PER_PTE * sizeof(pte_t)); + phys_addr_t pte_phys; + BUG_ON(!pgtable_alloc); + pte_phys = pgtable_alloc(); + pte = pte_set_fixmap(pte_phys); if (pmd_sect(*pmd)) split_pmd(pmd, pte); - __pmd_populate(pmd, __pa(pte), PMD_TYPE_TABLE); + __pmd_populate(pmd, pte_phys, PMD_TYPE_TABLE); flush_tlb_all(); + pte_clear_fixmap(); } BUG_ON(pmd_bad(*pmd)); - pte = pte_offset_kernel(pmd, addr); + pte = pte_set_fixmap_offset(pmd, addr); do { set_pte(pte, pfn_pte(pfn, prot)); pfn++; } while (pte++, addr += PAGE_SIZE, addr != end); + + pte_clear_fixmap(); } static void split_pud(pud_t *old_pud, pmd_t *pmd) @@ -127,10 +161,29 @@ } while (pmd++, i++, i < PTRS_PER_PMD); } -static void alloc_init_pmd(struct mm_struct *mm, pud_t *pud, - unsigned long addr, unsigned long end, +#ifdef CONFIG_DEBUG_PAGEALLOC +static bool block_mappings_allowed(phys_addr_t (*pgtable_alloc)(void)) +{ + + /* + * If debug_page_alloc is enabled we must map the linear map + * using pages. However, other mappings created by + * create_mapping_noalloc must use sections in some cases. Allow + * sections to be used in those cases, where no pgtable_alloc + * function is provided. + */ + return !pgtable_alloc || !debug_pagealloc_enabled(); +} +#else +static bool block_mappings_allowed(phys_addr_t (*pgtable_alloc)(void)) +{ + return true; +} +#endif + +static void alloc_init_pmd(pud_t *pud, unsigned long addr, unsigned long end, phys_addr_t phys, pgprot_t prot, - void *(*alloc)(unsigned long size)) + phys_addr_t (*pgtable_alloc)(void)) { pmd_t *pmd; unsigned long next; @@ -139,7 +192,10 @@ * Check for initial section mappings in the pgd/pud and remove them. */ if (pud_none(*pud) || pud_sect(*pud)) { - pmd = alloc(PTRS_PER_PMD * sizeof(pmd_t)); + phys_addr_t pmd_phys; + BUG_ON(!pgtable_alloc); + pmd_phys = pgtable_alloc(); + pmd = pmd_set_fixmap(pmd_phys); if (pud_sect(*pud)) { /* * need to have the 1G of mappings continue to be @@ -147,19 +203,21 @@ */ split_pud(pud, pmd); } - pud_populate(mm, pud, pmd); + __pud_populate(pud, pmd_phys, PUD_TYPE_TABLE); flush_tlb_all(); + pmd_clear_fixmap(); } BUG_ON(pud_bad(*pud)); - pmd = pmd_offset(pud, addr); + pmd = pmd_set_fixmap_offset(pud, addr); do { next = pmd_addr_end(addr, end); /* try section mapping first */ - if (((addr | next | phys) & ~SECTION_MASK) == 0) { + if (((addr | next | phys) & ~SECTION_MASK) == 0 && + block_mappings_allowed(pgtable_alloc) && + !dma_overlap(phys, phys + next - addr)) { pmd_t old_pmd =*pmd; - set_pmd(pmd, __pmd(phys | - pgprot_val(mk_sect_prot(prot)))); + pmd_set_huge(pmd, phys, prot); /* * Check for previous table entries created during * boot (__create_page_tables) and flush them. @@ -167,17 +225,19 @@ if (!pmd_none(old_pmd)) { flush_tlb_all(); if (pmd_table(old_pmd)) { - phys_addr_t table = __pa(pte_offset_map(&old_pmd, 0)); + phys_addr_t table = pmd_page_paddr(old_pmd); if (!WARN_ON_ONCE(slab_is_available())) memblock_free(table, PAGE_SIZE); } } } else { alloc_init_pte(pmd, addr, next, __phys_to_pfn(phys), - prot, alloc); + prot, pgtable_alloc); } phys += next - addr; } while (pmd++, addr = next, addr != end); + + pmd_clear_fixmap(); } static inline bool use_1G_block(unsigned long addr, unsigned long next, @@ -192,31 +252,33 @@ return true; } -static void alloc_init_pud(struct mm_struct *mm, pgd_t *pgd, - unsigned long addr, unsigned long end, +static void alloc_init_pud(pgd_t *pgd, unsigned long addr, unsigned long end, phys_addr_t phys, pgprot_t prot, - void *(*alloc)(unsigned long size)) + phys_addr_t (*pgtable_alloc)(void)) { pud_t *pud; unsigned long next; if (pgd_none(*pgd)) { - pud = alloc(PTRS_PER_PUD * sizeof(pud_t)); - pgd_populate(mm, pgd, pud); + phys_addr_t pud_phys; + BUG_ON(!pgtable_alloc); + pud_phys = pgtable_alloc(); + __pgd_populate(pgd, pud_phys, PUD_TYPE_TABLE); } BUG_ON(pgd_bad(*pgd)); - pud = pud_offset(pgd, addr); + pud = pud_set_fixmap_offset(pgd, addr); do { next = pud_addr_end(addr, end); /* * For 4K granule only, attempt to put down a 1GB block */ - if (use_1G_block(addr, next, phys)) { + if (use_1G_block(addr, next, phys) && + block_mappings_allowed(pgtable_alloc) && + !dma_overlap(phys, phys + next - addr)) { pud_t old_pud = *pud; - set_pud(pud, __pud(phys | - pgprot_val(mk_sect_prot(prot)))); + pud_set_huge(pud, phys, prot); /* * If we have an old value for a pud, it will @@ -228,51 +290,74 @@ if (!pud_none(old_pud)) { flush_tlb_all(); if (pud_table(old_pud)) { - phys_addr_t table = __pa(pmd_offset(&old_pud, 0)); + phys_addr_t table = pud_page_paddr(old_pud); if (!WARN_ON_ONCE(slab_is_available())) memblock_free(table, PAGE_SIZE); } } } else { - alloc_init_pmd(mm, pud, addr, next, phys, prot, alloc); + alloc_init_pmd(pud, addr, next, phys, prot, + pgtable_alloc); } phys += next - addr; } while (pud++, addr = next, addr != end); + + pud_clear_fixmap(); } /* * Create the page directory entries and any necessary page tables for the * mapping specified by 'md'. */ -static void __create_mapping(struct mm_struct *mm, pgd_t *pgd, - phys_addr_t phys, unsigned long virt, +static void init_pgd(pgd_t *pgd, phys_addr_t phys, unsigned long virt, phys_addr_t size, pgprot_t prot, - void *(*alloc)(unsigned long size)) + phys_addr_t (*pgtable_alloc)(void)) { unsigned long addr, length, end, next; + /* + * If the virtual and physical address don't have the same offset + * within a page, we cannot map the region as the caller expects. + */ + if (WARN_ON((phys ^ virt) & ~PAGE_MASK)) + return; + + phys &= PAGE_MASK; addr = virt & PAGE_MASK; length = PAGE_ALIGN(size + (virt & ~PAGE_MASK)); end = addr + length; do { next = pgd_addr_end(addr, end); - alloc_init_pud(mm, pgd, addr, next, phys, prot, alloc); + alloc_init_pud(pgd, addr, next, phys, prot, pgtable_alloc); phys += next - addr; } while (pgd++, addr = next, addr != end); } -static void *late_alloc(unsigned long size) +static phys_addr_t late_pgtable_alloc(void) { - void *ptr; - - BUG_ON(size > PAGE_SIZE); - ptr = (void *)__get_free_page(PGALLOC_GFP); + void *ptr = (void *)__get_free_page(PGALLOC_GFP); BUG_ON(!ptr); - return ptr; + + /* Ensure the zeroed page is visible to the page table walker */ + dsb(ishst); + return __pa(ptr); } -static void __init create_mapping(phys_addr_t phys, unsigned long virt, +static void __create_pgd_mapping(pgd_t *pgdir, phys_addr_t phys, + unsigned long virt, phys_addr_t size, + pgprot_t prot, + phys_addr_t (*alloc)(void)) +{ + init_pgd(pgd_offset_raw(pgdir, virt), phys, virt, size, prot, alloc); +} + +/* + * This function can only be used to modify existing table entries, + * without allocating new levels of table. Note that this permits the + * creation of new section or page entries. + */ +static void __init create_mapping_noalloc(phys_addr_t phys, unsigned long virt, phys_addr_t size, pgprot_t prot) { if (virt < VMALLOC_START) { @@ -280,16 +365,16 @@ &phys, virt); return; } - __create_mapping(&init_mm, pgd_offset_k(virt & PAGE_MASK), phys, virt, - size, prot, early_alloc); + __create_pgd_mapping(init_mm.pgd, phys, virt, size, prot, + NULL); } void __init create_pgd_mapping(struct mm_struct *mm, phys_addr_t phys, unsigned long virt, phys_addr_t size, pgprot_t prot) { - __create_mapping(mm, pgd_offset(mm, virt), phys, virt, size, prot, - late_alloc); + __create_pgd_mapping(mm->pgd, phys, virt, size, prot, + late_pgtable_alloc); } static void create_mapping_late(phys_addr_t phys, unsigned long virt, @@ -301,69 +386,57 @@ return; } - return __create_mapping(&init_mm, pgd_offset_k(virt & PAGE_MASK), - phys, virt, size, prot, late_alloc); + __create_pgd_mapping(init_mm.pgd, phys, virt, size, prot, + late_pgtable_alloc); } -#ifdef CONFIG_DEBUG_RODATA -static void __init __map_memblock(phys_addr_t start, phys_addr_t end) +static void __init __map_memblock(pgd_t *pgd, phys_addr_t start, phys_addr_t end) { + unsigned long kernel_start = __pa_symbol(_text); + unsigned long kernel_end = __pa_symbol(__init_begin); + /* - * Set up the executable regions using the existing section mappings - * for now. This will get more fine grained later once all memory - * is mapped + * Take care not to create a writable alias for the + * read-only text and rodata sections of the kernel image. */ - unsigned long kernel_x_start = round_down(__pa(_stext), SWAPPER_BLOCK_SIZE); - unsigned long kernel_x_end = round_up(__pa(__init_end), SWAPPER_BLOCK_SIZE); - if (end < kernel_x_start) { - create_mapping(start, __phys_to_virt(start), - end - start, PAGE_KERNEL); - } else if (start >= kernel_x_end) { - create_mapping(start, __phys_to_virt(start), - end - start, PAGE_KERNEL); - } else { - if (start < kernel_x_start) - create_mapping(start, __phys_to_virt(start), - kernel_x_start - start, - PAGE_KERNEL); - create_mapping(kernel_x_start, - __phys_to_virt(kernel_x_start), - kernel_x_end - kernel_x_start, - PAGE_KERNEL_EXEC); - if (kernel_x_end < end) - create_mapping(kernel_x_end, - __phys_to_virt(kernel_x_end), - end - kernel_x_end, - PAGE_KERNEL); + /* No overlap with the kernel text/rodata */ + if (end < kernel_start || start >= kernel_end) { + __create_pgd_mapping(pgd, start, __phys_to_virt(start), + end - start, PAGE_KERNEL, + early_pgtable_alloc); + return; } + /* + * This block overlaps the kernel text/rodata mappings. + * Map the portion(s) which don't overlap. + */ + if (start < kernel_start) + __create_pgd_mapping(pgd, start, + __phys_to_virt(start), + kernel_start - start, PAGE_KERNEL, + early_pgtable_alloc); + if (kernel_end < end) + __create_pgd_mapping(pgd, kernel_end, + __phys_to_virt(kernel_end), + end - kernel_end, PAGE_KERNEL, + early_pgtable_alloc); + + /* + * Map the linear alias of the [_text, __init_begin) interval as + * read-only/non-executable. This makes the contents of the + * region accessible to subsystems such as hibernate, but + * protects it from inadvertent modification or execution. + */ + __create_pgd_mapping(pgd, kernel_start, __phys_to_virt(kernel_start), + kernel_end - kernel_start, PAGE_KERNEL_RO, + early_pgtable_alloc); } -#else -static void __init __map_memblock(phys_addr_t start, phys_addr_t end) -{ - create_mapping(start, __phys_to_virt(start), end - start, - PAGE_KERNEL_EXEC); -} -#endif -static void __init map_mem(void) +static void __init map_mem(pgd_t *pgd) { struct memblock_region *reg; - phys_addr_t limit; - - /* - * Temporarily limit the memblock range. We need to do this as - * create_mapping requires puds, pmds and ptes to be allocated from - * memory addressable from the initial direct kernel mapping. - * - * The initial direct kernel mapping, located at swapper_pg_dir, gives - * us PUD_SIZE (with SECTION maps) or PMD_SIZE (without SECTION maps, - * memory starting from PHYS_OFFSET (which must be aligned to 2MB as - * per Documentation/arm64/booting.txt). - */ - limit = PHYS_OFFSET + SWAPPER_INIT_MAP_SIZE; - memblock_set_current_limit(limit); /* map all the memory banks */ for_each_memblock(memory, reg) { @@ -372,70 +445,160 @@ if (start >= end) break; + if (memblock_is_nomap(reg)) + continue; + + __map_memblock(pgd, start, end); + } +} + +void mark_rodata_ro(void) +{ + unsigned long section_size; - if (ARM64_SWAPPER_USES_SECTION_MAPS) { + section_size = (unsigned long)_etext - (unsigned long)_text; + create_mapping_late(__pa_symbol(_text), (unsigned long)_text, + section_size, PAGE_KERNEL_ROX); /* - * For the first memory bank align the start address and - * current memblock limit to prevent create_mapping() from - * allocating pte page tables from unmapped memory. With - * the section maps, if the first block doesn't end on section - * size boundary, create_mapping() will try to allocate a pte - * page, which may be returned from an unmapped area. - * When section maps are not used, the pte page table for the - * current limit is already present in swapper_pg_dir. + * mark .rodata as read only. Use __init_begin rather than __end_rodata + * to cover NOTES and EXCEPTION_TABLE. */ - if (start < limit) - start = ALIGN(start, SECTION_SIZE); - if (end < limit) { - limit = end & SECTION_MASK; - memblock_set_current_limit(limit); + section_size = (unsigned long)__init_begin - (unsigned long)__start_rodata; + create_mapping_late(__pa_symbol(__start_rodata), + (unsigned long)__start_rodata, + section_size, PAGE_KERNEL_RO); } + +void fixup_init(void) +{ + /* + * Unmap the __init region but leave the VM area in place. This + * prevents the region from being reused for kernel modules, which + * is not supported by kallsyms. + */ + unmap_kernel_range((u64)__init_begin, (u64)(__init_end - __init_begin)); } - __map_memblock(start, end); - } - /* Limit no longer required. */ - memblock_set_current_limit(MEMBLOCK_ALLOC_ANYWHERE); +static void __init map_kernel_segment(pgd_t *pgd, void *va_start, void *va_end, + pgprot_t prot, struct vm_struct *vma) +{ + phys_addr_t pa_start = __pa_symbol(va_start); + unsigned long size = va_end - va_start; + + BUG_ON(!PAGE_ALIGNED(pa_start)); + BUG_ON(!PAGE_ALIGNED(size)); + + __create_pgd_mapping(pgd, pa_start, (unsigned long)va_start, size, prot, + early_pgtable_alloc); + + vma->addr = va_start; + vma->phys_addr = pa_start; + vma->size = size; + vma->flags = VM_MAP; + vma->caller = __builtin_return_address(0); + + vm_area_add_early(vma); } -static void __init fixup_executable(void) +#ifdef CONFIG_UNMAP_KERNEL_AT_EL0 +static int __init map_entry_trampoline(void) { -#ifdef CONFIG_DEBUG_RODATA - /* now that we are actually fully mapped, make the start/end more fine grained */ - if (!IS_ALIGNED((unsigned long)_stext, SWAPPER_BLOCK_SIZE)) { - unsigned long aligned_start = round_down(__pa(_stext), - SWAPPER_BLOCK_SIZE); + extern char __entry_tramp_text_start[]; + + pgprot_t prot = PAGE_KERNEL_EXEC; + phys_addr_t pa_start = __pa_symbol(__entry_tramp_text_start); + + /* The trampoline is always mapped and can therefore be global */ + pgprot_val(prot) &= ~PTE_NG; + + /* Map only the text into the trampoline page table */ + memset(tramp_pg_dir, 0, PGD_SIZE); + __create_pgd_mapping(tramp_pg_dir, pa_start, TRAMP_VALIAS, PAGE_SIZE, + prot, late_pgtable_alloc); + + /* Map both the text and data into the kernel page table */ + __set_fixmap(FIX_ENTRY_TRAMP_TEXT, pa_start, prot); + if (IS_ENABLED(CONFIG_RANDOMIZE_BASE)) { + extern char __entry_tramp_data_start[]; - create_mapping(aligned_start, __phys_to_virt(aligned_start), - __pa(_stext) - aligned_start, - PAGE_KERNEL); + __set_fixmap(FIX_ENTRY_TRAMP_DATA, + __pa_symbol(__entry_tramp_data_start), + PAGE_KERNEL_RO); } - if (!IS_ALIGNED((unsigned long)__init_end, SWAPPER_BLOCK_SIZE)) { - unsigned long aligned_end = round_up(__pa(__init_end), - SWAPPER_BLOCK_SIZE); - create_mapping(__pa(__init_end), (unsigned long)__init_end, - aligned_end - __pa(__init_end), - PAGE_KERNEL); + return 0; } +core_initcall(map_entry_trampoline); #endif -} -#ifdef CONFIG_DEBUG_RODATA -void mark_rodata_ro(void) +/* + * Create fine-grained mappings for the kernel. + */ +static void __init map_kernel(pgd_t *pgd) { - create_mapping_late(__pa(_stext), (unsigned long)_stext, - (unsigned long)_etext - (unsigned long)_stext, - PAGE_KERNEL_ROX); + static struct vm_struct vmlinux_text, vmlinux_rodata, vmlinux_init, vmlinux_data; + + map_kernel_segment(pgd, _text, _etext, PAGE_KERNEL_EXEC, &vmlinux_text); + map_kernel_segment(pgd, __start_rodata, __init_begin, PAGE_KERNEL, &vmlinux_rodata); + map_kernel_segment(pgd, __init_begin, __init_end, PAGE_KERNEL_EXEC, + &vmlinux_init); + map_kernel_segment(pgd, _data, _end, PAGE_KERNEL, &vmlinux_data); + if (!pgd_val(*pgd_offset_raw(pgd, FIXADDR_START))) { + /* + * The fixmap falls in a separate pgd to the kernel, and doesn't + * live in the carveout for the swapper_pg_dir. We can simply + * re-use the existing dir for the fixmap. + */ + set_pgd(pgd_offset_raw(pgd, FIXADDR_START), + *pgd_offset_k(FIXADDR_START)); + } else if (CONFIG_PGTABLE_LEVELS > 3) { + /* + * The fixmap shares its top level pgd entry with the kernel + * mapping. This can really only occur when we are running + * with 16k/4 levels, so we can simply reuse the pud level + * entry instead. + */ + BUG_ON(!IS_ENABLED(CONFIG_ARM64_16K_PAGES)); + set_pud(pud_set_fixmap_offset(pgd, FIXADDR_START), + __pud(__pa_symbol(bm_pmd) | PUD_TYPE_TABLE)); + pud_clear_fixmap(); + } else { + BUG(); } -#endif -void fixup_init(void) + kasan_copy_shadow(pgd); +} + +struct dma_contig_early_reserve { + phys_addr_t base; + unsigned long size; +}; + +static struct dma_contig_early_reserve dma_mmu_remap[MAX_CMA_AREAS]; + +static int dma_mmu_remap_num; + +void __init dma_contiguous_early_fixup(phys_addr_t base, unsigned long size) { - create_mapping_late(__pa(__init_begin), (unsigned long)__init_begin, - (unsigned long)__init_end - (unsigned long)__init_begin, - PAGE_KERNEL); + dma_mmu_remap[dma_mmu_remap_num].base = base; + dma_mmu_remap[dma_mmu_remap_num].size = size; + dma_mmu_remap_num++; +} + +static bool dma_overlap(phys_addr_t start, phys_addr_t end) +{ + int i; + + for (i = 0; i < dma_mmu_remap_num; i++) { + phys_addr_t dma_base = dma_mmu_remap[i].base; + phys_addr_t dma_end = dma_mmu_remap[i].base + + dma_mmu_remap[i].size; + + if ((dma_base < end) && (dma_end > start)) + return true; + } + return false; } /* @@ -444,31 +607,455 @@ */ void __init paging_init(void) { - void *zero_page; + phys_addr_t pgd_phys = early_pgtable_alloc(); + pgd_t *pgd = pgd_set_fixmap(pgd_phys); + + map_kernel(pgd); + map_mem(pgd); + + /* + * We want to reuse the original swapper_pg_dir so we don't have to + * communicate the new address to non-coherent secondaries in + * secondary_entry, and so cpu_switch_mm can generate the address with + * adrp+add rather than a load from some global variable. + * + * To do this we need to go via a temporary pgd. + */ + cpu_replace_ttbr1(__va(pgd_phys)); + memcpy(swapper_pg_dir, pgd, PAGE_SIZE); + cpu_replace_ttbr1(lm_alias(swapper_pg_dir)); - map_mem(); - fixup_executable(); + pgd_clear_fixmap(); + memblock_free(pgd_phys, PAGE_SIZE); - /* allocate the zero page. */ - zero_page = early_alloc(PAGE_SIZE); + /* + * We only reuse the PGD from the swapper_pg_dir, not the pud + pmd + * allocated with it. + */ + memblock_free(__pa_symbol(swapper_pg_dir) + PAGE_SIZE, + SWAPPER_DIR_SIZE - PAGE_SIZE); bootmem_init(); +} - empty_zero_page = virt_to_page(zero_page); +#ifdef CONFIG_MEMORY_HOTPLUG +static phys_addr_t pgd_pgtable_alloc(void) +{ + void *ptr = (void *)__get_free_page(PGALLOC_GFP); + if (!ptr || !pgtable_page_ctor(virt_to_page(ptr))) + BUG(); - /* Ensure the zero page is visible to the page table walker */ + /* Ensure the zeroed page is visible to the page table walker */ dsb(ishst); + return __pa(ptr); +} /* - * TTBR0 is only used for the identity mapping at this stage. Make it - * point to zero page to avoid speculatively fetching new entries. + * hotplug_paging() is used by memory hotplug to build new page tables + * for hot added memory. */ - cpu_set_reserved_ttbr0(); - local_flush_tlb_all(); - cpu_set_default_tcr_t0sz(); +void hotplug_paging(phys_addr_t start, phys_addr_t size) +{ + + struct page *pg; + phys_addr_t pgd_phys = pgd_pgtable_alloc(); + pgd_t *pgd = pgd_set_fixmap(pgd_phys); + + memcpy(pgd, swapper_pg_dir, PAGE_SIZE); + + __create_pgd_mapping(pgd, start, __phys_to_virt(start), size, + PAGE_KERNEL, pgd_pgtable_alloc); + + cpu_replace_ttbr1(__va(pgd_phys)); + memcpy(swapper_pg_dir, pgd, PAGE_SIZE); + cpu_replace_ttbr1(swapper_pg_dir); + + pgd_clear_fixmap(); + + pg = phys_to_page(pgd_phys); + pgtable_page_dtor(pg); + __free_pages(pg, 0); +} + +#ifdef CONFIG_MEMORY_HOTREMOVE +#define PAGE_INUSE 0xFD + +static void free_pagetable(struct page *page, int order, bool direct) +{ + unsigned long magic; + unsigned int nr_pages = 1 << order; + + /* bootmem page has reserved flag */ + if (PageReserved(page)) { + __ClearPageReserved(page); + + magic = (unsigned long)page->lru.next; + if (magic == SECTION_INFO || magic == MIX_SECTION_INFO) { + while (nr_pages--) + put_page_bootmem(page++); + } else { + while (nr_pages--) + free_reserved_page(page++); + } + } else { + /* + * Only direct pagetable allocation (those allocated via + * hotplug) call the pgtable_page_ctor; vmemmap pgtable + * allocations don't. + */ + if (direct) + pgtable_page_dtor(page); + + free_pages((unsigned long)page_address(page), order); + } +} + +static void free_pte_table(pmd_t *pmd, bool direct) +{ + pte_t *pte_start, *pte; + struct page *page; + int i; + + pte_start = (pte_t *) pmd_page_vaddr(*pmd); + /* Check if there is no valid entry in the PMD */ + for (i = 0; i < PTRS_PER_PTE; i++) { + pte = pte_start + i; + if (!pte_none(*pte)) + return; + } + + page = pmd_page(*pmd); + + free_pagetable(page, 0, direct); + + /* + * This spin lock could be only taken in _pte_aloc_kernel + * in mm/memory.c and nowhere else (for arm64). Not sure if + * the function above can be called concurrently. In doubt, + * I am living it here for now, but it probably can be removed + */ + spin_lock(&init_mm.page_table_lock); + pmd_clear(pmd); + spin_unlock(&init_mm.page_table_lock); +} + +static void free_pmd_table(pud_t *pud, bool direct) +{ + pmd_t *pmd_start, *pmd; + struct page *page; + int i; + + pmd_start = (pmd_t *) pud_page_vaddr(*pud); + /* Check if there is no valid entry in the PMD */ + for (i = 0; i < PTRS_PER_PMD; i++) { + pmd = pmd_start + i; + if (!pmd_none(*pmd)) + return; + } + + page = pud_page(*pud); + + free_pagetable(page, 0, direct); + + /* + * This spin lock could be only taken in _pte_aloc_kernel + * in mm/memory.c and nowhere else (for arm64). Not sure if + * the function above can be called concurrently. In doubt, + * I am living it here for now, but it probably can be removed + */ + spin_lock(&init_mm.page_table_lock); + pud_clear(pud); + spin_unlock(&init_mm.page_table_lock); } /* + * When the PUD is folded on the PGD (three levels of paging), + * there's no need to free PUDs + */ +#if CONFIG_PGTABLE_LEVELS > 3 +static void free_pud_table(pgd_t *pgd, bool direct) +{ + pud_t *pud_start, *pud; + struct page *page; + int i; + + pud_start = (pud_t *) pgd_page_vaddr(*pgd); + /* Check if there is no valid entry in the PUD */ + for (i = 0; i < PTRS_PER_PUD; i++) { + pud = pud_start + i; + if (!pud_none(*pud)) + return; + } + + page = pgd_page(*pgd); + + free_pagetable(page, 0, direct); + + /* + * This spin lock could be only + * taken in _pte_aloc_kernel in + * mm/memory.c and nowhere else + * (for arm64). Not sure if the + * function above can be called + * concurrently. In doubt, + * I am living it here for now, + * but it probably can be removed. + */ + spin_lock(&init_mm.page_table_lock); + pgd_clear(pgd); + spin_unlock(&init_mm.page_table_lock); +} +#endif + +static void remove_pte_table(pte_t *pte, unsigned long addr, + unsigned long end, bool direct) +{ + unsigned long next; + void *page_addr; + + for (; addr < end; addr = next, pte++) { + next = (addr + PAGE_SIZE) & PAGE_MASK; + if (next > end) + next = end; + + if (!pte_present(*pte)) + continue; + + if (PAGE_ALIGNED(addr) && PAGE_ALIGNED(next)) { + /* + * Do not free direct mapping pages since they were + * freed when offlining, or simplely not in use. + */ + if (!direct) + free_pagetable(pte_page(*pte), 0, direct); + + /* + * This spin lock could be only + * taken in _pte_aloc_kernel in + * mm/memory.c and nowhere else + * (for arm64). Not sure if the + * function above can be called + * concurrently. In doubt, + * I am living it here for now, + * but it probably can be removed. + */ + spin_lock(&init_mm.page_table_lock); + pte_clear(&init_mm, addr, pte); + spin_unlock(&init_mm.page_table_lock); + } else { + /* + * If we are here, we are freeing vmemmap pages since + * direct mapped memory ranges to be freed are aligned. + * + * If we are not removing the whole page, it means + * other page structs in this page are being used and + * we canot remove them. So fill the unused page_structs + * with 0xFD, and remove the page when it is wholly + * filled with 0xFD. + */ + memset((void *)addr, PAGE_INUSE, next - addr); + + page_addr = page_address(pte_page(*pte)); + if (!memchr_inv(page_addr, PAGE_INUSE, PAGE_SIZE)) { + free_pagetable(pte_page(*pte), 0, direct); + + /* + * This spin lock could be only + * taken in _pte_aloc_kernel in + * mm/memory.c and nowhere else + * (for arm64). Not sure if the + * function above can be called + * concurrently. In doubt, + * I am living it here for now, + * but it probably can be removed. + */ + spin_lock(&init_mm.page_table_lock); + pte_clear(&init_mm, addr, pte); + spin_unlock(&init_mm.page_table_lock); + } + } + } + + // I am adding this flush here in simmetry to the x86 code. + // Why do I need to call it here and not in remove_p[mu]d + flush_tlb_all(); +} + +static void remove_pmd_table(pmd_t *pmd, unsigned long addr, + unsigned long end, bool direct) +{ + unsigned long next; + void *page_addr; + pte_t *pte; + + for (; addr < end; addr = next, pmd++) { + next = pmd_addr_end(addr, end); + + if (!pmd_present(*pmd)) + continue; + + // check if we are using 2MB section mappings + if (pmd_sect(*pmd)) { + if (PAGE_ALIGNED(addr) && PAGE_ALIGNED(next)) { + if (!direct) { + free_pagetable(pmd_page(*pmd), + get_order(PMD_SIZE), direct); + } + /* + * This spin lock could be only + * taken in _pte_aloc_kernel in + * mm/memory.c and nowhere else + * (for arm64). Not sure if the + * function above can be called + * concurrently. In doubt, + * I am living it here for now, + * but it probably can be removed. + */ + spin_lock(&init_mm.page_table_lock); + pmd_clear(pmd); + spin_unlock(&init_mm.page_table_lock); + } else { + /* If here, we are freeing vmemmap pages. */ + memset((void *)addr, PAGE_INUSE, next - addr); + + page_addr = page_address(pmd_page(*pmd)); + if (!memchr_inv(page_addr, PAGE_INUSE, + PMD_SIZE)) { + free_pagetable(pmd_page(*pmd), + get_order(PMD_SIZE), direct); + + /* + * This spin lock could be only + * taken in _pte_aloc_kernel in + * mm/memory.c and nowhere else + * (for arm64). Not sure if the + * function above can be called + * concurrently. In doubt, + * I am living it here for now, + * but it probably can be removed. + */ + spin_lock(&init_mm.page_table_lock); + pmd_clear(pmd); + spin_unlock(&init_mm.page_table_lock); + } + } + continue; + } + + BUG_ON(!pmd_table(*pmd)); + + pte = pte_offset_map(pmd, addr); + remove_pte_table(pte, addr, next, direct); + free_pte_table(pmd, direct); + } +} + +static void remove_pud_table(pud_t *pud, unsigned long addr, + unsigned long end, bool direct) +{ + unsigned long next; + pmd_t *pmd; + void *page_addr; + + for (; addr < end; addr = next, pud++) { + next = pud_addr_end(addr, end); + if (!pud_present(*pud)) + continue; + /* + * If we are using 4K granules, check if we are using + * 1GB section mapping. + */ + if (pud_sect(*pud)) { + if (PAGE_ALIGNED(addr) && PAGE_ALIGNED(next)) { + if (!direct) { + free_pagetable(pud_page(*pud), + get_order(PUD_SIZE), direct); + } + + /* + * This spin lock could be only + * taken in _pte_aloc_kernel in + * mm/memory.c and nowhere else + * (for arm64). Not sure if the + * function above can be called + * concurrently. In doubt, + * I am living it here for now, + * but it probably can be removed. + */ + spin_lock(&init_mm.page_table_lock); + pud_clear(pud); + spin_unlock(&init_mm.page_table_lock); + } else { + /* If here, we are freeing vmemmap pages. */ + memset((void *)addr, PAGE_INUSE, next - addr); + + page_addr = page_address(pud_page(*pud)); + if (!memchr_inv(page_addr, PAGE_INUSE, + PUD_SIZE)) { + + free_pagetable(pud_page(*pud), + get_order(PUD_SIZE), direct); + + /* + * This spin lock could be only + * taken in _pte_aloc_kernel in + * mm/memory.c and nowhere else + * (for arm64). Not sure if the + * function above can be called + * concurrently. In doubt, + * I am living it here for now, + * but it probably can be removed. + */ + spin_lock(&init_mm.page_table_lock); + pud_clear(pud); + spin_unlock(&init_mm.page_table_lock); + } + } + continue; + } + + BUG_ON(!pud_table(*pud)); + + pmd = pmd_offset(pud, addr); + remove_pmd_table(pmd, addr, next, direct); + free_pmd_table(pud, direct); + } +} + +void remove_pagetable(unsigned long start, unsigned long end, bool direct) +{ + unsigned long next; + unsigned long addr; + pgd_t *pgd; + pud_t *pud; + + for (addr = start; addr < end; addr = next) { + next = pgd_addr_end(addr, end); + + pgd = pgd_offset_k(addr); + if (pgd_none(*pgd)) + continue; + + pud = pud_offset(pgd, addr); + remove_pud_table(pud, addr, next, direct); + /* + * When the PUD is folded on the PGD (three levels of paging), + * I did already clear the PMD page in free_pmd_table, + * and reset the corresponding PGD==PUD entry. + */ +#if CONFIG_PGTABLE_LEVELS > 3 + free_pud_table(pgd, direct); +#endif + } + + flush_tlb_all(); +} + + +#endif /* CONFIG_MEMORY_HOTREMOVE */ +#endif /* CONFIG_MEMORY_HOTPLUG */ + +/* * Check whether a kernel address is valid (derived from arch/x86/). */ int kern_addr_valid(unsigned long addr) @@ -519,6 +1106,7 @@ pgd_t *pgd; pud_t *pud; pmd_t *pmd; + int ret = 0; do { next = pmd_addr_end(addr, end); @@ -536,37 +1124,40 @@ void *p = NULL; p = vmemmap_alloc_block_buf(PMD_SIZE, node); - if (!p) - return -ENOMEM; + if (!p) { +#ifdef CONFIG_MEMORY_HOTPLUG + vmemmap_free(start, end); +#endif + ret = -ENOMEM; + break; + } set_pmd(pmd, __pmd(__pa(p) | PROT_SECT_NORMAL)); } else vmemmap_verify((pte_t *)pmd, node, addr, next); } while (addr = next, addr != end); - return 0; + if (ret) + return vmemmap_populate_basepages(start, end, node); + else + return ret; } #endif /* CONFIG_ARM64_64K_PAGES */ void vmemmap_free(unsigned long start, unsigned long end) { +#ifdef CONFIG_MEMORY_HOTREMOVE + remove_pagetable(start, end, false); +#endif } #endif /* CONFIG_SPARSEMEM_VMEMMAP */ -static pte_t bm_pte[PTRS_PER_PTE] __page_aligned_bss; -#if CONFIG_PGTABLE_LEVELS > 2 -static pmd_t bm_pmd[PTRS_PER_PMD] __page_aligned_bss; -#endif -#if CONFIG_PGTABLE_LEVELS > 3 -static pud_t bm_pud[PTRS_PER_PUD] __page_aligned_bss; -#endif - static inline pud_t * fixmap_pud(unsigned long addr) { pgd_t *pgd = pgd_offset_k(addr); BUG_ON(pgd_none(*pgd) || pgd_bad(*pgd)); - return pud_offset(pgd, addr); + return pud_offset_kimg(pgd, addr); } static inline pmd_t * fixmap_pmd(unsigned long addr) @@ -575,18 +1166,20 @@ BUG_ON(pud_none(*pud) || pud_bad(*pud)); - return pmd_offset(pud, addr); + return pmd_offset_kimg(pud, addr); } static inline pte_t * fixmap_pte(unsigned long addr) { - pmd_t *pmd = fixmap_pmd(addr); - - BUG_ON(pmd_none(*pmd) || pmd_bad(*pmd)); - - return pte_offset_kernel(pmd, addr); + return &bm_pte[pte_index(addr)]; } +/* + * The p*d_populate functions call virt_to_phys implicitly so they can't be used + * directly on kernel symbols (bm_p*d). This function is called too early to use + * lm_alias so __p*d_populate functions must be used to populate with the + * physical address from __pa_symbol. + */ void __init early_fixmap_init(void) { pgd_t *pgd; @@ -595,15 +1188,29 @@ unsigned long addr = FIXADDR_START; pgd = pgd_offset_k(addr); - pgd_populate(&init_mm, pgd, bm_pud); - pud = pud_offset(pgd, addr); - pud_populate(&init_mm, pud, bm_pmd); - pmd = pmd_offset(pud, addr); - pmd_populate_kernel(&init_mm, pmd, bm_pte); + if (CONFIG_PGTABLE_LEVELS > 3 && + !(pgd_none(*pgd) || pgd_page_paddr(*pgd) == __pa_symbol(bm_pud))) { + /* + * We only end up here if the kernel mapping and the fixmap + * share the top level pgd entry, which should only happen on + * 16k/4 levels configurations. + */ + BUG_ON(!IS_ENABLED(CONFIG_ARM64_16K_PAGES)); + pud = pud_offset_kimg(pgd, addr); + } else { + if (pgd_none(*pgd)) + __pgd_populate(pgd, __pa_symbol(bm_pud), + PUD_TYPE_TABLE); + pud = fixmap_pud(addr); + } + if (pud_none(*pud)) + __pud_populate(pud, __pa_symbol(bm_pmd), PMD_TYPE_TABLE); + pmd = fixmap_pmd(addr); + __pmd_populate(pmd, __pa_symbol(bm_pte), PMD_TYPE_TABLE); /* * The boot-ioremap range spans multiple pmds, for which - * we are not preparted: + * we are not prepared: */ BUILD_BUG_ON((__fix_to_virt(FIX_BTMAP_BEGIN) >> PMD_SHIFT) != (__fix_to_virt(FIX_BTMAP_END) >> PMD_SHIFT)); @@ -642,11 +1249,10 @@ } } -void *__init fixmap_remap_fdt(phys_addr_t dt_phys) +void *__init __fixmap_remap_fdt(phys_addr_t dt_phys, int *size, pgprot_t prot) { const u64 dt_virt_base = __fix_to_virt(FIX_FDT); - pgprot_t prot = PAGE_KERNEL_RO; - int size, offset; + int offset; void *dt_virt; /* @@ -663,7 +1269,7 @@ /* * Make sure that the FDT region can be mapped without the need to * allocate additional translation table pages, so that it is safe - * to call create_mapping() this early. + * to call create_mapping_noalloc() this early. * * On 64k pages, the FDT will be mapped using PTEs, so we need to * be in the same PMD as the rest of the fixmap. @@ -679,21 +1285,73 @@ dt_virt = (void *)dt_virt_base + offset; /* map the first chunk so we can read the size from the header */ - create_mapping(round_down(dt_phys, SWAPPER_BLOCK_SIZE), dt_virt_base, - SWAPPER_BLOCK_SIZE, prot); + create_mapping_noalloc(round_down(dt_phys, SWAPPER_BLOCK_SIZE), + dt_virt_base, SWAPPER_BLOCK_SIZE, prot); if (fdt_magic(dt_virt) != FDT_MAGIC) return NULL; - size = fdt_totalsize(dt_virt); - if (size > MAX_FDT_SIZE) + *size = fdt_totalsize(dt_virt); + if (*size > MAX_FDT_SIZE) return NULL; - if (offset + size > SWAPPER_BLOCK_SIZE) - create_mapping(round_down(dt_phys, SWAPPER_BLOCK_SIZE), dt_virt_base, - round_up(offset + size, SWAPPER_BLOCK_SIZE), prot); + if (offset + *size > SWAPPER_BLOCK_SIZE) + create_mapping_noalloc(round_down(dt_phys, SWAPPER_BLOCK_SIZE), dt_virt_base, + round_up(offset + *size, SWAPPER_BLOCK_SIZE), prot); - memblock_reserve(dt_phys, size); + return dt_virt; +} + +void *__init fixmap_remap_fdt(phys_addr_t dt_phys) +{ + void *dt_virt; + int size; + dt_virt = __fixmap_remap_fdt(dt_phys, &size, PAGE_KERNEL_RO); + if (!dt_virt) + return NULL; + + memblock_reserve(dt_phys, size); return dt_virt; } + +int __init arch_ioremap_pud_supported(void) +{ + /* only 4k granule supports level 1 block mappings */ + return IS_ENABLED(CONFIG_ARM64_4K_PAGES); +} + +int __init arch_ioremap_pmd_supported(void) +{ + return 1; +} + +int pud_set_huge(pud_t *pud, phys_addr_t phys, pgprot_t prot) +{ + BUG_ON(phys & ~PUD_MASK); + set_pud(pud, __pud(phys | PUD_TYPE_SECT | pgprot_val(mk_sect_prot(prot)))); + return 1; +} + +int pmd_set_huge(pmd_t *pmd, phys_addr_t phys, pgprot_t prot) +{ + BUG_ON(phys & ~PMD_MASK); + set_pmd(pmd, __pmd(phys | PMD_TYPE_SECT | pgprot_val(mk_sect_prot(prot)))); + return 1; +} + +int pud_clear_huge(pud_t *pud) +{ + if (!pud_sect(*pud)) + return 0; + pud_clear(pud); + return 1; +} + +int pmd_clear_huge(pmd_t *pmd) +{ + if (!pmd_sect(*pmd)) + return 0; + pmd_clear(pmd); + return 1; +} diff -ruw linux-4.4.115/arch/arm64/mm/pageattr.c linux-4.4.115-fbx/arch/arm64/mm/pageattr.c --- linux-4.4.115/arch/arm64/mm/pageattr.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/arch/arm64/mm/pageattr.c 2019-10-29 09:26:23.013197013 +0100 @@ -14,6 +14,7 @@ #include #include #include +#include #include #include @@ -36,14 +37,32 @@ return 0; } +/* + * This function assumes that the range is mapped with PAGE_SIZE pages. + */ +static int __change_memory_common(unsigned long start, unsigned long size, + pgprot_t set_mask, pgprot_t clear_mask) +{ + struct page_change_data data; + int ret; + + data.set_mask = set_mask; + data.clear_mask = clear_mask; + + ret = apply_to_page_range(&init_mm, start, size, change_page_range, + &data); + + flush_tlb_kernel_range(start, start + size); + return ret; +} + static int change_memory_common(unsigned long addr, int numpages, pgprot_t set_mask, pgprot_t clear_mask) { unsigned long start = addr; unsigned long size = PAGE_SIZE*numpages; unsigned long end = start + size; - int ret; - struct page_change_data data; + struct vm_struct *area; if (!PAGE_ALIGNED(addr)) { start &= PAGE_MASK; @@ -51,23 +70,36 @@ WARN_ON_ONCE(1); } + if (!IS_ENABLED(CONFIG_FORCE_PAGES)) { if (start < MODULES_VADDR || start >= MODULES_END) return -EINVAL; if (end < MODULES_VADDR || end >= MODULES_END) return -EINVAL; + } + /* + * Kernel VA mappings are always live, and splitting live section + * mappings into page mappings may cause TLB conflicts. This means + * we have to ensure that changing the permission bits of the range + * we are operating on does not result in such splitting. + * + * Let's restrict ourselves to mappings created by vmalloc (or vmap). + * Those are guaranteed to consist entirely of page mappings, and + * splitting is never needed. + * + * So check whether the [addr, addr + size) interval is entirely + * covered by precisely one VM area that has the VM_ALLOC flag set. + */ + area = find_vm_area((void *)addr); + if (!area || + end > (unsigned long)area->addr + area->size || + !(area->flags & VM_ALLOC)) + return -EINVAL; if (!numpages) return 0; - data.set_mask = set_mask; - data.clear_mask = clear_mask; - - ret = apply_to_page_range(&init_mm, start, size, change_page_range, - &data); - - flush_tlb_kernel_range(start, end); - return ret; + return __change_memory_common(start, size, set_mask, clear_mask); } int set_memory_ro(unsigned long addr, int numpages) @@ -99,3 +131,19 @@ __pgprot(PTE_PXN)); } EXPORT_SYMBOL_GPL(set_memory_x); + +#ifdef CONFIG_DEBUG_PAGEALLOC +void __kernel_map_pages(struct page *page, int numpages, int enable) +{ + unsigned long addr = (unsigned long) page_address(page); + + if (enable) + __change_memory_common(addr, PAGE_SIZE * numpages, + __pgprot(PTE_VALID), + __pgprot(0)); + else + __change_memory_common(addr, PAGE_SIZE * numpages, + __pgprot(0), + __pgprot(PTE_VALID)); +} +#endif diff -ruw linux-4.4.115/arch/arm64/mm/pgd.c linux-4.4.115-fbx/arch/arm64/mm/pgd.c --- linux-4.4.115/arch/arm64/mm/pgd.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/arch/arm64/mm/pgd.c 2019-01-22 16:16:21.563228839 +0100 @@ -46,14 +46,14 @@ kmem_cache_free(pgd_cache, pgd); } -static int __init pgd_cache_init(void) +void __init pgd_cache_init(void) { + if (PGD_SIZE == PAGE_SIZE) + return; + /* * Naturally aligned pgds required by the architecture. */ - if (PGD_SIZE != PAGE_SIZE) pgd_cache = kmem_cache_create("pgd_cache", PGD_SIZE, PGD_SIZE, SLAB_PANIC, NULL); - return 0; } -core_initcall(pgd_cache_init); diff -ruw linux-4.4.115/arch/arm64/mm/proc.S linux-4.4.115-fbx/arch/arm64/mm/proc.S --- linux-4.4.115/arch/arm64/mm/proc.S 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/arch/arm64/mm/proc.S 2019-10-29 09:26:23.013197013 +0100 @@ -23,13 +23,11 @@ #include #include #include -#include #include +#include #include #include -#include "proc-macros.S" - #ifdef CONFIG_ARM64_64K_PAGES #define TCR_TG_FLAGS TCR_TG0_64K | TCR_TG1_64K #elif defined(CONFIG_ARM64_16K_PAGES) @@ -46,6 +44,52 @@ #define MAIR(attr, mt) ((attr) << ((mt) * 8)) /* + * cpu_cache_off() + * + * Turn the CPU D-cache off. + */ +ENTRY(cpu_cache_off) + mrs x0, sctlr_el1 + bic x0, x0, #1 << 2 // clear SCTLR.C + msr sctlr_el1, x0 + isb + ret +ENDPROC(cpu_cache_off) + +/* + * cpu_reset(loc) + * + * Perform a soft reset of the system. Put the CPU into the same state + * as it would be if it had been reset, and branch to what would be the + * reset vector. It must be executed with the flat identity mapping. + * + * - loc - location to jump to for soft reset + */ + .align 5 +ENTRY(cpu_reset) + mrs x1, sctlr_el1 + bic x1, x1, #1 + msr sctlr_el1, x1 // disable the MMU + isb + ret x0 +ENDPROC(cpu_reset) + +ENTRY(cpu_soft_restart) + /* Save address of cpu_reset() and reset address */ + mov x19, x0 + mov x20, x1 + + /* Turn D-cache off */ + bl cpu_cache_off + + /* Push out all dirty data, and ensure cache is empty */ + bl flush_cache_all + + mov x0, x20 + ret x19 +ENDPROC(cpu_soft_restart) + +/* * cpu_do_idle() * * Idle the processor (wait for interrupt). @@ -66,62 +110,56 @@ mrs x2, tpidr_el0 mrs x3, tpidrro_el0 mrs x4, contextidr_el1 - mrs x5, mair_el1 - mrs x6, cpacr_el1 - mrs x7, ttbr1_el1 - mrs x8, tcr_el1 - mrs x9, vbar_el1 - mrs x10, mdscr_el1 - mrs x11, oslsr_el1 - mrs x12, sctlr_el1 + mrs x5, cpacr_el1 + mrs x6, tcr_el1 + mrs x7, vbar_el1 + mrs x8, mdscr_el1 + mrs x9, oslsr_el1 + mrs x10, sctlr_el1 + mrs x11, tpidr_el1 + mrs x12, sp_el0 stp x2, x3, [x0] - stp x4, x5, [x0, #16] - stp x6, x7, [x0, #32] - stp x8, x9, [x0, #48] - stp x10, x11, [x0, #64] - str x12, [x0, #80] + stp x4, xzr, [x0, #16] + stp x5, x6, [x0, #32] + stp x7, x8, [x0, #48] + stp x9, x10, [x0, #64] + stp x11, x12, [x0, #80] ret ENDPROC(cpu_do_suspend) /** * cpu_do_resume - restore CPU register context * - * x0: Physical address of context pointer - * x1: ttbr0_el1 to be restored - * - * Returns: - * sctlr_el1 value in x0 + * x0: Address of context pointer */ ENTRY(cpu_do_resume) - /* - * Invalidate local tlb entries before turning on MMU - */ - tlbi vmalle1 ldp x2, x3, [x0] ldp x4, x5, [x0, #16] - ldp x6, x7, [x0, #32] - ldp x8, x9, [x0, #48] - ldp x10, x11, [x0, #64] - ldr x12, [x0, #80] + ldp x6, x8, [x0, #32] + ldp x9, x10, [x0, #48] + ldp x11, x12, [x0, #64] + ldp x13, x14, [x0, #80] msr tpidr_el0, x2 msr tpidrro_el0, x3 msr contextidr_el1, x4 - msr mair_el1, x5 msr cpacr_el1, x6 - msr ttbr0_el1, x1 - msr ttbr1_el1, x7 - tcr_set_idmap_t0sz x8, x7 + + /* Don't change t0sz here, mask those bits when restoring */ + mrs x5, tcr_el1 + bfi x8, x5, TCR_T0SZ_OFFSET, TCR_TxSZ_WIDTH + msr tcr_el1, x8 msr vbar_el1, x9 msr mdscr_el1, x10 + msr sctlr_el1, x12 + msr tpidr_el1, x13 + msr sp_el0, x14 /* * Restore oslsr_el1 by writing oslar_el1 */ ubfx x11, x11, #1, #1 msr oslar_el1, x11 reset_pmuserenr_el0 x0 // Disable PMU access from EL0 - mov x0, x12 - dsb nsh // Make sure local tlb invalidation completed isb ret ENDPROC(cpu_do_resume) @@ -135,24 +173,46 @@ * - pgd_phys - physical address of new TTB */ ENTRY(cpu_do_switch_mm) + mrs x2, ttbr1_el1 mmid x1, x1 // get mm->context.id - bfi x0, x1, #48, #16 // set the ASID - msr ttbr0_el1, x0 // set TTBR0 +#ifdef CONFIG_ARM64_SW_TTBR0_PAN + bfi x0, x1, #48, #16 // set the ASID field in TTBR0 +#endif + bfi x2, x1, #48, #16 // set the ASID + msr ttbr1_el1, x2 // in TTBR1 (since TCR.A1 is set) isb -alternative_if_not ARM64_WORKAROUND_CAVIUM_27456 - ret - nop - nop - nop -alternative_else - ic iallu - dsb nsh + msr ttbr0_el1, x0 // now update TTBR0 isb - ret -alternative_endif + b post_ttbr_update_workaround // Back to C code... ENDPROC(cpu_do_switch_mm) - .section ".text.init", #alloc, #execinstr + .pushsection ".idmap.text", "ax" +/* + * void idmap_cpu_replace_ttbr1(phys_addr_t new_pgd) + * + * This is the low-level counterpart to cpu_replace_ttbr1, and should not be + * called by anything else. It can only be executed from a TTBR0 mapping. + */ +ENTRY(idmap_cpu_replace_ttbr1) + mrs x2, daif + msr daifset, #0xf + + adrp x1, empty_zero_page + msr ttbr1_el1, x1 + isb + + tlbi vmalle1 + dsb nsh + isb + + msr ttbr1_el1, x0 + isb + + msr daif, x2 + + ret +ENDPROC(idmap_cpu_replace_ttbr1) + .popsection /* * __cpu_setup @@ -203,7 +263,7 @@ * both user and kernel. */ ldr x10, =TCR_TxSZ(VA_BITS) | TCR_CACHE_FLAGS | TCR_SMP_FLAGS | \ - TCR_TG_FLAGS | TCR_ASID16 | TCR_TBI0 + TCR_TG_FLAGS | TCR_ASID16 | TCR_TBI0 | TCR_A1 tcr_set_idmap_t0sz x10, x9 /* @@ -243,5 +303,16 @@ */ .type crval, #object crval: +#ifdef CONFIG_ARM64_ICACHE_DISABLE +#define CR_IBIT 0 +#else +#define CR_IBIT 0x1000 +#endif + +#ifdef CONFIG_ARM64_DCACHE_DISABLE +#define CR_CBIT 0 +#else +#define CR_CBIT 0x4 +#endif .word 0xfcffffff // clear - .word 0x34d5d91d // set + .word 0x34d5d91d | CR_IBIT | CR_CBIT // set diff -ruw linux-4.4.115/arch/cris/boot/dts/include/dt-bindings/input/linux-event-codes.h linux-4.4.115-fbx/arch/cris/boot/dts/include/dt-bindings/input/linux-event-codes.h --- linux-4.4.115/arch/cris/boot/dts/include/dt-bindings/input/linux-event-codes.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/arch/cris/boot/dts/include/dt-bindings/input/linux-event-codes.h 2019-10-29 09:26:25.545221791 +0100 @@ -611,6 +611,37 @@ #define KEY_KBDINPUTASSIST_ACCEPT 0x264 #define KEY_KBDINPUTASSIST_CANCEL 0x265 +/* Diagonal movement keys */ +#define KEY_RIGHT_UP 0x266 +#define KEY_RIGHT_DOWN 0x267 +#define KEY_LEFT_UP 0x268 +#define KEY_LEFT_DOWN 0x269 + +#define KEY_ROOT_MENU 0x26a /* Show Device's Root Menu */ +/* Show Top Menu of the Media (e.g. DVD) */ +#define KEY_MEDIA_TOP_MENU 0x26b +#define KEY_NUMERIC_11 0x26c +#define KEY_NUMERIC_12 0x26d +/* + * Toggle Audio Description: refers to an audio service that helps blind and + * visually impaired consumers understand the action in a program. Note: in + * some countries this is referred to as "Video Description". + */ +#define KEY_AUDIO_DESC 0x26e +#define KEY_3D_MODE 0x26f +#define KEY_NEXT_FAVORITE 0x270 +#define KEY_STOP_RECORD 0x271 +#define KEY_PAUSE_RECORD 0x272 +#define KEY_VOD 0x273 /* Video on Demand */ +#define KEY_UNMUTE 0x274 +#define KEY_FASTREVERSE 0x275 +#define KEY_SLOWREVERSE 0x276 +/* + * Control a data application associated with the currently viewed channel, + * e.g. teletext or data broadcast application (MHEG, MHP, HbbTV, etc.) + */ +#define KEY_DATA 0x275 + #define BTN_TRIGGER_HAPPY 0x2c0 #define BTN_TRIGGER_HAPPY1 0x2c0 #define BTN_TRIGGER_HAPPY2 0x2c1 @@ -653,6 +684,18 @@ #define BTN_TRIGGER_HAPPY39 0x2e6 #define BTN_TRIGGER_HAPPY40 0x2e7 +#define KEY_APP_TV 0x2f1 +#define KEY_APP_REPLAY 0x2f2 +#define KEY_APP_VIDEOCLUB 0x2f3 +#define KEY_APP_WHATSON 0x2f4 +#define KEY_APP_RECORDS 0x2f5 +#define KEY_APP_MEDIA 0x2f6 +#define KEY_APP_YOUTUBE 0x2f7 +#define KEY_APP_RADIOS 0x2f8 +#define KEY_APP_CANALVOD 0x2f9 +#define KEY_APP_PIP 0x2fa +#define KEY_APP_NETFLIX 0x2fb + /* We avoid low common keys in module aliases so they don't get huge. */ #define KEY_MIN_INTERESTING KEY_MUTE #define KEY_MAX 0x2ff @@ -749,7 +792,11 @@ #define SW_ROTATE_LOCK 0x0c /* set = rotate locked/disabled */ #define SW_LINEIN_INSERT 0x0d /* set = inserted */ #define SW_MUTE_DEVICE 0x0e /* set = device disabled */ -#define SW_MAX 0x0f +#define SW_HPHL_OVERCURRENT 0x0f /* set = over current on left hph */ +#define SW_HPHR_OVERCURRENT 0x10 /* set = over current on right hph */ +#define SW_MICROPHONE2_INSERT 0x11 /* set = inserted */ +#define SW_UNSUPPORT_INSERT 0x12 /* set = unsupported device inserted */ +#define SW_MAX 0x20 #define SW_CNT (SW_MAX+1) /* diff -ruw linux-4.4.115/arch/Kconfig linux-4.4.115-fbx/arch/Kconfig --- linux-4.4.115/arch/Kconfig 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/arch/Kconfig 2019-10-29 09:26:22.861195525 +0100 @@ -225,8 +225,8 @@ config ARCH_TASK_STRUCT_ALLOCATOR bool -# Select if arch has its private alloc_thread_info() function -config ARCH_THREAD_INFO_ALLOCATOR +# Select if arch has its private alloc_thread_stack() function +config ARCH_THREAD_STACK_ALLOCATOR bool # Select if arch wants to size task_struct dynamically via arch_task_struct_size: @@ -423,6 +423,15 @@ endchoice +config HAVE_ARCH_WITHIN_STACK_FRAMES + bool + help + An architecture should select this if it can walk the kernel stack + frames to determine if an object is part of either the arguments + or local variables (i.e. that it excludes saved return addresses, + and similar) by implementing an inline arch_within_stack_frames(), + which is used by CONFIG_HARDENED_USERCOPY. + config HAVE_CONTEXT_TRACKING bool help @@ -518,6 +527,74 @@ normal C parameter passing, rather than extracting the syscall argument from pt_regs. +config HAVE_ARCH_MMAP_RND_BITS + bool + help + An arch should select this symbol if it supports setting a variable + number of bits for use in establishing the base address for mmap + allocations, has MMU enabled and provides values for both: + - ARCH_MMAP_RND_BITS_MIN + - ARCH_MMAP_RND_BITS_MAX + +config ARCH_MMAP_RND_BITS_MIN + int + +config ARCH_MMAP_RND_BITS_MAX + int + +config ARCH_MMAP_RND_BITS_DEFAULT + int + +config ARCH_MMAP_RND_BITS + int "Number of bits to use for ASLR of mmap base address" if EXPERT + range ARCH_MMAP_RND_BITS_MIN ARCH_MMAP_RND_BITS_MAX + default ARCH_MMAP_RND_BITS_DEFAULT if ARCH_MMAP_RND_BITS_DEFAULT + default ARCH_MMAP_RND_BITS_MIN + depends on HAVE_ARCH_MMAP_RND_BITS + help + This value can be used to select the number of bits to use to + determine the random offset to the base address of vma regions + resulting from mmap allocations. This value will be bounded + by the architecture's minimum and maximum supported values. + + This value can be changed after boot using the + /proc/sys/vm/mmap_rnd_bits tunable + +config HAVE_ARCH_MMAP_RND_COMPAT_BITS + bool + help + An arch should select this symbol if it supports running applications + in compatibility mode, supports setting a variable number of bits for + use in establishing the base address for mmap allocations, has MMU + enabled and provides values for both: + - ARCH_MMAP_RND_COMPAT_BITS_MIN + - ARCH_MMAP_RND_COMPAT_BITS_MAX + +config ARCH_MMAP_RND_COMPAT_BITS_MIN + int + +config ARCH_MMAP_RND_COMPAT_BITS_MAX + int + +config ARCH_MMAP_RND_COMPAT_BITS_DEFAULT + int + +config ARCH_MMAP_RND_COMPAT_BITS + int "Number of bits to use for ASLR of mmap base address for compatible applications" if EXPERT + range ARCH_MMAP_RND_COMPAT_BITS_MIN ARCH_MMAP_RND_COMPAT_BITS_MAX + default ARCH_MMAP_RND_COMPAT_BITS_DEFAULT if ARCH_MMAP_RND_COMPAT_BITS_DEFAULT + default ARCH_MMAP_RND_COMPAT_BITS_MIN + depends on HAVE_ARCH_MMAP_RND_COMPAT_BITS + help + This value can be used to select the number of bits to use to + determine the random offset to the base address of vma regions + resulting from mmap allocations for compatible applications This + value will be bounded by the architecture's minimum and maximum + supported values. + + This value can be changed after boot using the + /proc/sys/vm/mmap_rnd_compat_bits tunable + # # ABI hall of shame # diff -ruw linux-4.4.115/arch/metag/boot/dts/include/dt-bindings/input/linux-event-codes.h linux-4.4.115-fbx/arch/metag/boot/dts/include/dt-bindings/input/linux-event-codes.h --- linux-4.4.115/arch/metag/boot/dts/include/dt-bindings/input/linux-event-codes.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/arch/metag/boot/dts/include/dt-bindings/input/linux-event-codes.h 2019-10-29 09:26:25.545221791 +0100 @@ -611,6 +611,37 @@ #define KEY_KBDINPUTASSIST_ACCEPT 0x264 #define KEY_KBDINPUTASSIST_CANCEL 0x265 +/* Diagonal movement keys */ +#define KEY_RIGHT_UP 0x266 +#define KEY_RIGHT_DOWN 0x267 +#define KEY_LEFT_UP 0x268 +#define KEY_LEFT_DOWN 0x269 + +#define KEY_ROOT_MENU 0x26a /* Show Device's Root Menu */ +/* Show Top Menu of the Media (e.g. DVD) */ +#define KEY_MEDIA_TOP_MENU 0x26b +#define KEY_NUMERIC_11 0x26c +#define KEY_NUMERIC_12 0x26d +/* + * Toggle Audio Description: refers to an audio service that helps blind and + * visually impaired consumers understand the action in a program. Note: in + * some countries this is referred to as "Video Description". + */ +#define KEY_AUDIO_DESC 0x26e +#define KEY_3D_MODE 0x26f +#define KEY_NEXT_FAVORITE 0x270 +#define KEY_STOP_RECORD 0x271 +#define KEY_PAUSE_RECORD 0x272 +#define KEY_VOD 0x273 /* Video on Demand */ +#define KEY_UNMUTE 0x274 +#define KEY_FASTREVERSE 0x275 +#define KEY_SLOWREVERSE 0x276 +/* + * Control a data application associated with the currently viewed channel, + * e.g. teletext or data broadcast application (MHEG, MHP, HbbTV, etc.) + */ +#define KEY_DATA 0x275 + #define BTN_TRIGGER_HAPPY 0x2c0 #define BTN_TRIGGER_HAPPY1 0x2c0 #define BTN_TRIGGER_HAPPY2 0x2c1 @@ -653,6 +684,18 @@ #define BTN_TRIGGER_HAPPY39 0x2e6 #define BTN_TRIGGER_HAPPY40 0x2e7 +#define KEY_APP_TV 0x2f1 +#define KEY_APP_REPLAY 0x2f2 +#define KEY_APP_VIDEOCLUB 0x2f3 +#define KEY_APP_WHATSON 0x2f4 +#define KEY_APP_RECORDS 0x2f5 +#define KEY_APP_MEDIA 0x2f6 +#define KEY_APP_YOUTUBE 0x2f7 +#define KEY_APP_RADIOS 0x2f8 +#define KEY_APP_CANALVOD 0x2f9 +#define KEY_APP_PIP 0x2fa +#define KEY_APP_NETFLIX 0x2fb + /* We avoid low common keys in module aliases so they don't get huge. */ #define KEY_MIN_INTERESTING KEY_MUTE #define KEY_MAX 0x2ff @@ -749,7 +792,11 @@ #define SW_ROTATE_LOCK 0x0c /* set = rotate locked/disabled */ #define SW_LINEIN_INSERT 0x0d /* set = inserted */ #define SW_MUTE_DEVICE 0x0e /* set = device disabled */ -#define SW_MAX 0x0f +#define SW_HPHL_OVERCURRENT 0x0f /* set = over current on left hph */ +#define SW_HPHR_OVERCURRENT 0x10 /* set = over current on right hph */ +#define SW_MICROPHONE2_INSERT 0x11 /* set = inserted */ +#define SW_UNSUPPORT_INSERT 0x12 /* set = unsupported device inserted */ +#define SW_MAX 0x20 #define SW_CNT (SW_MAX+1) /* diff -ruw linux-4.4.115/arch/mips/boot/dts/include/dt-bindings/input/linux-event-codes.h linux-4.4.115-fbx/arch/mips/boot/dts/include/dt-bindings/input/linux-event-codes.h --- linux-4.4.115/arch/mips/boot/dts/include/dt-bindings/input/linux-event-codes.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/arch/mips/boot/dts/include/dt-bindings/input/linux-event-codes.h 2019-10-29 09:26:25.545221791 +0100 @@ -611,6 +611,37 @@ #define KEY_KBDINPUTASSIST_ACCEPT 0x264 #define KEY_KBDINPUTASSIST_CANCEL 0x265 +/* Diagonal movement keys */ +#define KEY_RIGHT_UP 0x266 +#define KEY_RIGHT_DOWN 0x267 +#define KEY_LEFT_UP 0x268 +#define KEY_LEFT_DOWN 0x269 + +#define KEY_ROOT_MENU 0x26a /* Show Device's Root Menu */ +/* Show Top Menu of the Media (e.g. DVD) */ +#define KEY_MEDIA_TOP_MENU 0x26b +#define KEY_NUMERIC_11 0x26c +#define KEY_NUMERIC_12 0x26d +/* + * Toggle Audio Description: refers to an audio service that helps blind and + * visually impaired consumers understand the action in a program. Note: in + * some countries this is referred to as "Video Description". + */ +#define KEY_AUDIO_DESC 0x26e +#define KEY_3D_MODE 0x26f +#define KEY_NEXT_FAVORITE 0x270 +#define KEY_STOP_RECORD 0x271 +#define KEY_PAUSE_RECORD 0x272 +#define KEY_VOD 0x273 /* Video on Demand */ +#define KEY_UNMUTE 0x274 +#define KEY_FASTREVERSE 0x275 +#define KEY_SLOWREVERSE 0x276 +/* + * Control a data application associated with the currently viewed channel, + * e.g. teletext or data broadcast application (MHEG, MHP, HbbTV, etc.) + */ +#define KEY_DATA 0x275 + #define BTN_TRIGGER_HAPPY 0x2c0 #define BTN_TRIGGER_HAPPY1 0x2c0 #define BTN_TRIGGER_HAPPY2 0x2c1 @@ -653,6 +684,18 @@ #define BTN_TRIGGER_HAPPY39 0x2e6 #define BTN_TRIGGER_HAPPY40 0x2e7 +#define KEY_APP_TV 0x2f1 +#define KEY_APP_REPLAY 0x2f2 +#define KEY_APP_VIDEOCLUB 0x2f3 +#define KEY_APP_WHATSON 0x2f4 +#define KEY_APP_RECORDS 0x2f5 +#define KEY_APP_MEDIA 0x2f6 +#define KEY_APP_YOUTUBE 0x2f7 +#define KEY_APP_RADIOS 0x2f8 +#define KEY_APP_CANALVOD 0x2f9 +#define KEY_APP_PIP 0x2fa +#define KEY_APP_NETFLIX 0x2fb + /* We avoid low common keys in module aliases so they don't get huge. */ #define KEY_MIN_INTERESTING KEY_MUTE #define KEY_MAX 0x2ff @@ -749,7 +792,11 @@ #define SW_ROTATE_LOCK 0x0c /* set = rotate locked/disabled */ #define SW_LINEIN_INSERT 0x0d /* set = inserted */ #define SW_MUTE_DEVICE 0x0e /* set = device disabled */ -#define SW_MAX 0x0f +#define SW_HPHL_OVERCURRENT 0x0f /* set = over current on left hph */ +#define SW_HPHR_OVERCURRENT 0x10 /* set = over current on right hph */ +#define SW_MICROPHONE2_INSERT 0x11 /* set = inserted */ +#define SW_UNSUPPORT_INSERT 0x12 /* set = unsupported device inserted */ +#define SW_MAX 0x20 #define SW_CNT (SW_MAX+1) /* diff -ruw linux-4.4.115/arch/powerpc/boot/dts/include/dt-bindings/input/linux-event-codes.h linux-4.4.115-fbx/arch/powerpc/boot/dts/include/dt-bindings/input/linux-event-codes.h --- linux-4.4.115/arch/powerpc/boot/dts/include/dt-bindings/input/linux-event-codes.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/arch/powerpc/boot/dts/include/dt-bindings/input/linux-event-codes.h 2019-10-29 09:26:25.545221791 +0100 @@ -611,6 +611,37 @@ #define KEY_KBDINPUTASSIST_ACCEPT 0x264 #define KEY_KBDINPUTASSIST_CANCEL 0x265 +/* Diagonal movement keys */ +#define KEY_RIGHT_UP 0x266 +#define KEY_RIGHT_DOWN 0x267 +#define KEY_LEFT_UP 0x268 +#define KEY_LEFT_DOWN 0x269 + +#define KEY_ROOT_MENU 0x26a /* Show Device's Root Menu */ +/* Show Top Menu of the Media (e.g. DVD) */ +#define KEY_MEDIA_TOP_MENU 0x26b +#define KEY_NUMERIC_11 0x26c +#define KEY_NUMERIC_12 0x26d +/* + * Toggle Audio Description: refers to an audio service that helps blind and + * visually impaired consumers understand the action in a program. Note: in + * some countries this is referred to as "Video Description". + */ +#define KEY_AUDIO_DESC 0x26e +#define KEY_3D_MODE 0x26f +#define KEY_NEXT_FAVORITE 0x270 +#define KEY_STOP_RECORD 0x271 +#define KEY_PAUSE_RECORD 0x272 +#define KEY_VOD 0x273 /* Video on Demand */ +#define KEY_UNMUTE 0x274 +#define KEY_FASTREVERSE 0x275 +#define KEY_SLOWREVERSE 0x276 +/* + * Control a data application associated with the currently viewed channel, + * e.g. teletext or data broadcast application (MHEG, MHP, HbbTV, etc.) + */ +#define KEY_DATA 0x275 + #define BTN_TRIGGER_HAPPY 0x2c0 #define BTN_TRIGGER_HAPPY1 0x2c0 #define BTN_TRIGGER_HAPPY2 0x2c1 @@ -653,6 +684,18 @@ #define BTN_TRIGGER_HAPPY39 0x2e6 #define BTN_TRIGGER_HAPPY40 0x2e7 +#define KEY_APP_TV 0x2f1 +#define KEY_APP_REPLAY 0x2f2 +#define KEY_APP_VIDEOCLUB 0x2f3 +#define KEY_APP_WHATSON 0x2f4 +#define KEY_APP_RECORDS 0x2f5 +#define KEY_APP_MEDIA 0x2f6 +#define KEY_APP_YOUTUBE 0x2f7 +#define KEY_APP_RADIOS 0x2f8 +#define KEY_APP_CANALVOD 0x2f9 +#define KEY_APP_PIP 0x2fa +#define KEY_APP_NETFLIX 0x2fb + /* We avoid low common keys in module aliases so they don't get huge. */ #define KEY_MIN_INTERESTING KEY_MUTE #define KEY_MAX 0x2ff @@ -749,7 +792,11 @@ #define SW_ROTATE_LOCK 0x0c /* set = rotate locked/disabled */ #define SW_LINEIN_INSERT 0x0d /* set = inserted */ #define SW_MUTE_DEVICE 0x0e /* set = device disabled */ -#define SW_MAX 0x0f +#define SW_HPHL_OVERCURRENT 0x0f /* set = over current on left hph */ +#define SW_HPHR_OVERCURRENT 0x10 /* set = over current on right hph */ +#define SW_MICROPHONE2_INSERT 0x11 /* set = inserted */ +#define SW_UNSUPPORT_INSERT 0x12 /* set = unsupported device inserted */ +#define SW_MAX 0x20 #define SW_CNT (SW_MAX+1) /* diff -ruw linux-4.4.115/block/bio.c linux-4.4.115-fbx/block/bio.c --- linux-4.4.115/block/bio.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/block/bio.c 2019-10-29 09:26:23.329200105 +0100 @@ -31,6 +31,8 @@ #include +#include "blk.h" + /* * Test patch to inline a certain number of bi_io_vec's inside the bio * itself, to shrink a bio data allocation from two mempool calls to one @@ -590,6 +592,7 @@ bio->bi_rw = bio_src->bi_rw; bio->bi_iter = bio_src->bi_iter; bio->bi_io_vec = bio_src->bi_io_vec; + bio->bi_dio_inode = bio_src->bi_dio_inode; bio_clone_blkcg_association(bio, bio_src); } @@ -1782,8 +1785,10 @@ bio_put(bio); bio = parent; } else { - if (bio->bi_end_io) + if (bio->bi_end_io) { + blk_update_perf_stats(bio); bio->bi_end_io(bio); + } bio = NULL; } } diff -ruw linux-4.4.115/block/blk-core.c linux-4.4.115-fbx/block/blk-core.c --- linux-4.4.115/block/blk-core.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/block/blk-core.c 2019-10-29 09:26:23.333200144 +0100 @@ -11,6 +11,12 @@ /* * This handles all read/write requests to block devices */ + +#ifdef CONFIG_BLOCK_PERF_FRAMEWORK +#define DRIVER_NAME "Block" +#define pr_fmt(fmt) DRIVER_NAME ": %s: " fmt, __func__ +#endif + #include #include #include @@ -34,12 +40,20 @@ #include #include +#ifdef CONFIG_BLOCK_PERF_FRAMEWORK +#include +#include +#include +#endif + #define CREATE_TRACE_POINTS #include #include "blk.h" #include "blk-mq.h" +#include + EXPORT_TRACEPOINT_SYMBOL_GPL(block_bio_remap); EXPORT_TRACEPOINT_SYMBOL_GPL(block_rq_remap); EXPORT_TRACEPOINT_SYMBOL_GPL(block_bio_complete); @@ -73,7 +87,7 @@ * flip its congestion state for events on other blkcgs. */ if (rl == &rl->q->root_rl) - clear_wb_congested(rl->q->backing_dev_info.wb.congested, sync); + clear_wb_congested(rl->q->backing_dev_info->wb.congested, sync); #endif } @@ -84,7 +98,7 @@ #else /* see blk_clear_congested() */ if (rl == &rl->q->root_rl) - set_wb_congested(rl->q->backing_dev_info.wb.congested, sync); + set_wb_congested(rl->q->backing_dev_info->wb.congested, sync); #endif } @@ -108,14 +122,12 @@ * @bdev: device * * Locates the passed device's request queue and returns the address of its - * backing_dev_info. This function can only be called if @bdev is opened - * and the return value is never NULL. + * backing_dev_info. The return value is never NULL however we may return + * &noop_backing_dev_info if the bdev is not currently open. */ struct backing_dev_info *blk_get_backing_dev_info(struct block_device *bdev) { - struct request_queue *q = bdev_get_queue(bdev); - - return &q->backing_dev_info; + return bdev->bd_bdi; } EXPORT_SYMBOL(blk_get_backing_dev_info); @@ -583,7 +595,7 @@ blk_flush_integrity(); /* @q won't process any more request, flush async actions */ - del_timer_sync(&q->backing_dev_info.laptop_mode_wb_timer); + del_timer_sync(&q->backing_dev_info->laptop_mode_wb_timer); blk_sync_queue(q); if (q->mq_ops) @@ -595,8 +607,6 @@ q->queue_lock = &q->__queue_lock; spin_unlock_irq(lock); - bdi_unregister(&q->backing_dev_info); - /* @q is and will stay empty, shutdown and put */ blk_put_queue(q); } @@ -685,7 +695,6 @@ struct request_queue *blk_alloc_queue_node(gfp_t gfp_mask, int node_id) { struct request_queue *q; - int err; q = kmem_cache_alloc_node(blk_requestq_cachep, gfp_mask | __GFP_ZERO, node_id); @@ -700,17 +709,17 @@ if (!q->bio_split) goto fail_id; - q->backing_dev_info.ra_pages = + q->backing_dev_info = bdi_alloc_node(gfp_mask, node_id); + if (!q->backing_dev_info) + goto fail_split; + + q->backing_dev_info->ra_pages = (VM_MAX_READAHEAD * 1024) / PAGE_CACHE_SIZE; - q->backing_dev_info.capabilities = BDI_CAP_CGROUP_WRITEBACK; - q->backing_dev_info.name = "block"; + q->backing_dev_info->capabilities = BDI_CAP_CGROUP_WRITEBACK; + q->backing_dev_info->name = "block"; q->node = node_id; - err = bdi_init(&q->backing_dev_info); - if (err) - goto fail_split; - - setup_timer(&q->backing_dev_info.laptop_mode_wb_timer, + setup_timer(&q->backing_dev_info->laptop_mode_wb_timer, laptop_mode_timer_fn, (unsigned long) q); setup_timer(&q->timeout, blk_rq_timed_out_timer, (unsigned long) q); INIT_LIST_HEAD(&q->queue_head); @@ -760,7 +769,7 @@ fail_ref: percpu_ref_exit(&q->q_usage_counter); fail_bdi: - bdi_destroy(&q->backing_dev_info); + bdi_put(q->backing_dev_info); fail_split: bioset_free(q->bio_split); fail_id: @@ -1183,7 +1192,7 @@ * disturb iosched and blkcg but weird is bettern than dead. */ printk_ratelimited(KERN_WARNING "%s: dev %s: request aux data allocation failed, iosched may be disturbed\n", - __func__, dev_name(q->backing_dev_info.dev)); + __func__, dev_name(q->backing_dev_info->dev)); rq->cmd_flags &= ~REQ_ELVPRIV; rq->elv.icq = NULL; @@ -1277,8 +1286,6 @@ { struct request *rq; - BUG_ON(rw != READ && rw != WRITE); - /* create ioc upfront */ create_io_context(gfp_mask, q->node); @@ -1450,9 +1457,11 @@ #ifdef CONFIG_PM static void blk_pm_put_request(struct request *rq) { - if (rq->q->dev && !(rq->cmd_flags & REQ_PM) && !--rq->q->nr_pending) + if (rq->q->dev && !(rq->cmd_flags & REQ_PM) && rq->q->nr_pending) { + if (!--rq->q->nr_pending) pm_runtime_mark_last_busy(rq->q->dev); } +} #else static inline void blk_pm_put_request(struct request *rq) {} #endif @@ -1477,6 +1486,9 @@ /* this is a bio leak */ WARN_ON(req->bio != NULL); + /* this is a bio leak if the bio is not tagged with BIO_DONTFREE */ + WARN_ON(req->bio && !bio_flagged(req->bio, BIO_DONTFREE)); + /* * Request may not have originated from ll_rw_blk. if not, * it didn't come out of our reserved rq pools @@ -1698,6 +1710,7 @@ req->ioprio = bio_prio(bio); blk_rq_bio_prep(req->q, req, bio); } +EXPORT_SYMBOL(init_request_from_bio); static blk_qc_t blk_queue_bio(struct request_queue *q, struct bio *bio) { @@ -1722,7 +1735,8 @@ return BLK_QC_T_NONE; } - if (bio->bi_rw & (REQ_FLUSH | REQ_FUA)) { + if (bio->bi_rw & (REQ_FLUSH | REQ_FUA | REQ_POST_FLUSH_BARRIER | + REQ_BARRIER)) { spin_lock_irq(q->queue_lock); where = ELEVATOR_INSERT_FLUSH; goto get_rq; @@ -2105,6 +2119,477 @@ } EXPORT_SYMBOL(generic_make_request); +#ifdef CONFIG_BLK_DEV_IO_TRACE +static inline struct task_struct *get_dirty_task(struct bio *bio) +{ + /* + * Not all the pages in the bio are dirtied by the + * same task but most likely it will be, since the + * sectors accessed on the device must be adjacent. + */ + if (bio->bi_io_vec && bio->bi_io_vec->bv_page && + bio->bi_io_vec->bv_page->tsk_dirty) + return bio->bi_io_vec->bv_page->tsk_dirty; + else + return current; +} +#else +static inline struct task_struct *get_dirty_task(struct bio *bio) +{ + return current; +} +#endif + +#ifdef CONFIG_BLOCK_PERF_FRAMEWORK +#define BLK_PERF_SIZE (1024 * 15) +#define BLK_PERF_HIST_SIZE (sizeof(u32) * BLK_PERF_SIZE) + +struct blk_perf_stats { + u32 *read_hist; + u32 *write_hist; + u32 *flush_hist; + int buffers_alloced; + ktime_t max_read_time; + ktime_t max_write_time; + ktime_t max_flush_time; + ktime_t min_write_time; + ktime_t min_read_time; + ktime_t min_flush_time; + ktime_t total_write_time; + ktime_t total_read_time; + u64 total_read_size; + u64 total_write_size; + spinlock_t lock; + int is_enabled; +}; + +static struct blk_perf_stats blk_perf; +static struct dentry *blk_perf_debug_dir; + +static int alloc_histogram_buffers(void) +{ + int ret = 0; + + if (!blk_perf.read_hist) + blk_perf.read_hist = kzalloc(BLK_PERF_HIST_SIZE, GFP_KERNEL); + + if (!blk_perf.write_hist) + blk_perf.write_hist = kzalloc(BLK_PERF_HIST_SIZE, GFP_KERNEL); + + if (!blk_perf.flush_hist) + blk_perf.flush_hist = kzalloc(BLK_PERF_HIST_SIZE, GFP_KERNEL); + + if (!blk_perf.read_hist || !blk_perf.write_hist || !blk_perf.flush_hist) + ret = -ENOMEM; + + if (!ret) + blk_perf.buffers_alloced = 1; + return ret; +} + +static void clear_histogram_buffers(void) +{ + if (!blk_perf.buffers_alloced) + return; + memset(blk_perf.read_hist, 0, BLK_PERF_HIST_SIZE); + memset(blk_perf.write_hist, 0, BLK_PERF_HIST_SIZE); + memset(blk_perf.flush_hist, 0, BLK_PERF_HIST_SIZE); +} + +static int enable_perf(void *data, u64 val) +{ + int ret; + + if (!blk_perf.buffers_alloced) + ret = alloc_histogram_buffers(); + + if (ret) + return ret; + + spin_lock(&blk_perf.lock); + blk_perf.is_enabled = val; + spin_unlock(&blk_perf.lock); + return 0; +} + +static int is_perf_enabled(void *data, u64 *val) +{ + spin_lock(&blk_perf.lock); + *val = blk_perf.is_enabled; + spin_unlock(&blk_perf.lock); + return 0; +} + +DEFINE_SIMPLE_ATTRIBUTE(enable_perf_fops, is_perf_enabled, enable_perf, + "%llu\n"); + +static char *blk_debug_buffer; +static u32 blk_debug_data_size; +static DEFINE_MUTEX(blk_perf_debug_buffer_mutex); + +static ssize_t blk_perf_read(struct file *file, char __user *buf, + size_t count, loff_t *file_pos) +{ + ssize_t ret = 0; + + mutex_lock(&blk_perf_debug_buffer_mutex); + ret = simple_read_from_buffer(buf, count, file_pos, blk_debug_buffer, + blk_debug_data_size); + mutex_unlock(&blk_perf_debug_buffer_mutex); + + return ret; +} + +static int blk_debug_buffer_alloc(u32 buffer_size) +{ + int ret = 0; + + mutex_lock(&blk_perf_debug_buffer_mutex); + if (blk_debug_buffer != NULL) { + pr_err("blk_debug_buffer is in use\n"); + ret = -EBUSY; + goto end; + } + blk_debug_buffer = kzalloc(buffer_size, GFP_KERNEL); + if (!blk_debug_buffer) + ret = -ENOMEM; +end: + mutex_unlock(&blk_perf_debug_buffer_mutex); + return ret; +} + +static int blk_perf_close(struct inode *inode, struct file *file) +{ + mutex_lock(&blk_perf_debug_buffer_mutex); + blk_debug_data_size = 0; + kfree(blk_debug_buffer); + blk_debug_buffer = NULL; + mutex_unlock(&blk_perf_debug_buffer_mutex); + return 0; +} + +static u32 fill_basic_perf_info(char *buffer, u32 buffer_size) +{ + u32 size = 0; + + size += scnprintf(buffer + size, buffer_size - size, "\n"); + + spin_lock(&blk_perf.lock); + size += scnprintf(buffer + size, buffer_size - size, + "max_read_time_ms: %llu\n", + ktime_to_ms(blk_perf.max_read_time)); + + size += scnprintf(buffer + size, buffer_size - size, + "min_read_time_ms: %llu\n", + ktime_to_ms(blk_perf.min_read_time)); + + size += scnprintf(buffer + size, buffer_size - size, + "total_read_time_ms: %llu\n", + ktime_to_ms(blk_perf.total_read_time)); + + size += scnprintf(buffer + size, buffer_size - size, + "total_read_size: %llu\n\n", + blk_perf.total_read_size); + + size += scnprintf(buffer + size, buffer_size - size, + "max_write_time_ms: %llu\n", + ktime_to_ms(blk_perf.max_write_time)); + + size += scnprintf(buffer + size, buffer_size - size, + "min_write_time_ms: %llu\n", + ktime_to_ms(blk_perf.min_write_time)); + + size += scnprintf(buffer + size, buffer_size - size, + "total_write_time_ms: %llu\n", + ktime_to_ms(blk_perf.total_write_time)); + + size += scnprintf(buffer + size, buffer_size - size, + "total_write_size: %llu\n\n", + blk_perf.total_write_size); + + size += scnprintf(buffer + size, buffer_size - size, + "max_flush_time_ms: %llu\n", + ktime_to_ms(blk_perf.max_flush_time)); + + size += scnprintf(buffer + size, buffer_size - size, + "min_flush_time_ms: %llu\n\n", + ktime_to_ms(blk_perf.min_flush_time)); + + spin_unlock(&blk_perf.lock); + + return size; +} + +static int basic_perf_open(struct inode *inode, struct file *file) +{ + u32 buffer_size; + int ret; + + buffer_size = BLK_PERF_HIST_SIZE; + ret = blk_debug_buffer_alloc(buffer_size); + if (ret) + return ret; + + mutex_lock(&blk_perf_debug_buffer_mutex); + blk_debug_data_size = fill_basic_perf_info(blk_debug_buffer, + buffer_size); + mutex_unlock(&blk_perf_debug_buffer_mutex); + return 0; +} + + +static const struct file_operations basic_perf_ops = { + .read = blk_perf_read, + .release = blk_perf_close, + .open = basic_perf_open, +}; + +static int hist_open_helper(void *hist_buf) +{ + int ret; + + if (!blk_perf.buffers_alloced) + return -EINVAL; + + ret = blk_debug_buffer_alloc(BLK_PERF_HIST_SIZE); + if (ret) + return ret; + + spin_lock(&blk_perf.lock); + memcpy(blk_debug_buffer, hist_buf, BLK_PERF_HIST_SIZE); + spin_unlock(&blk_perf.lock); + + mutex_lock(&blk_perf_debug_buffer_mutex); + blk_debug_data_size = BLK_PERF_HIST_SIZE; + mutex_unlock(&blk_perf_debug_buffer_mutex); + return 0; +} + +static int write_hist_open(struct inode *inode, struct file *file) +{ + return hist_open_helper(blk_perf.write_hist); +} + +static const struct file_operations write_hist_ops = { + .read = blk_perf_read, + .release = blk_perf_close, + .open = write_hist_open, +}; + + +static int read_hist_open(struct inode *inode, struct file *file) +{ + return hist_open_helper(blk_perf.read_hist); +} + +static const struct file_operations read_hist_ops = { + .read = blk_perf_read, + .release = blk_perf_close, + .open = read_hist_open, +}; + +static int flush_hist_open(struct inode *inode, struct file *file) +{ + return hist_open_helper(blk_perf.flush_hist); +} + +static const struct file_operations flush_hist_ops = { + .read = blk_perf_read, + .release = blk_perf_close, + .open = flush_hist_open, +}; + +static void clear_perf_stats_helper(void) +{ + spin_lock(&blk_perf.lock); + blk_perf.max_write_time = ktime_set(0, 0); + blk_perf.max_read_time = ktime_set(0, 0); + blk_perf.max_flush_time = ktime_set(0, 0); + blk_perf.min_write_time = ktime_set(KTIME_MAX, 0); + blk_perf.min_read_time = ktime_set(KTIME_MAX, 0); + blk_perf.min_flush_time = ktime_set(KTIME_MAX, 0); + blk_perf.total_write_time = ktime_set(0, 0); + blk_perf.total_read_time = ktime_set(0, 0); + blk_perf.total_read_size = 0; + blk_perf.total_write_size = 0; + blk_perf.is_enabled = 0; + clear_histogram_buffers(); + spin_unlock(&blk_perf.lock); +} + +static int clear_perf_stats(void *data, u64 val) +{ + clear_perf_stats_helper(); + return 0; +} + +DEFINE_SIMPLE_ATTRIBUTE(clear_perf_stats_fops, NULL, clear_perf_stats, + "%llu\n"); + +static void blk_debugfs_init(void) +{ + struct dentry *f_ent; + + blk_perf_debug_dir = debugfs_create_dir("block_perf", NULL); + if (IS_ERR(blk_perf_debug_dir)) { + pr_err("Failed to create block_perf debug_fs directory\n"); + return; + } + + f_ent = debugfs_create_file("basic_perf", 0400, blk_perf_debug_dir, + NULL, &basic_perf_ops); + if (IS_ERR(f_ent)) { + pr_err("Failed to create debug_fs basic_perf file\n"); + return; + } + + f_ent = debugfs_create_file("write_hist", 0400, blk_perf_debug_dir, + NULL, &write_hist_ops); + if (IS_ERR(f_ent)) { + pr_err("Failed to create debug_fs write_hist file\n"); + return; + } + + f_ent = debugfs_create_file("read_hist", 0400, blk_perf_debug_dir, + NULL, &read_hist_ops); + if (IS_ERR(f_ent)) { + pr_err("Failed to create debug_fs read_hist file\n"); + return; + } + + f_ent = debugfs_create_file("flush_hist", 0400, blk_perf_debug_dir, + NULL, &flush_hist_ops); + if (IS_ERR(f_ent)) { + pr_err("Failed to create debug_fs flush_hist file\n"); + return; + } + + f_ent = debugfs_create_file("enable_perf", 0600, blk_perf_debug_dir, + NULL, &enable_perf_fops); + if (IS_ERR(f_ent)) { + pr_err("Failed to create debug_fs enable_perf file\n"); + return; + } + + f_ent = debugfs_create_file("clear_perf_stats", 0200, + blk_perf_debug_dir, NULL, + &clear_perf_stats_fops); + if (IS_ERR(f_ent)) { + pr_err("Failed to create debug_fs clear_perf_stats file\n"); + return; + } +} + +static void blk_init_perf(void) +{ + blk_debugfs_init(); + spin_lock_init(&blk_perf.lock); + + clear_perf_stats_helper(); +} + + +static void set_submit_info(struct bio *bio, unsigned int count) +{ + ktime_t submit_time; + + if (unlikely(blk_perf.is_enabled)) { + submit_time = ktime_get(); + bio->submit_time.tv64 = submit_time.tv64; + bio->blk_sector_count = count; + return; + } + + bio->submit_time.tv64 = 0; + bio->blk_sector_count = 0; +} + +void blk_update_perf_read_write_stats(ktime_t bio_process_time, int is_write, + int count) +{ + u32 bio_process_time_ms; + + bio_process_time_ms = ktime_to_ms(bio_process_time); + if (bio_process_time_ms >= BLK_PERF_SIZE) + bio_process_time_ms = BLK_PERF_SIZE - 1; + + if (is_write) { + if (ktime_after(bio_process_time, blk_perf.max_write_time)) + blk_perf.max_write_time = bio_process_time; + + if (ktime_before(bio_process_time, blk_perf.min_write_time)) + blk_perf.min_write_time = bio_process_time; + blk_perf.total_write_time = + ktime_add(blk_perf.total_write_time, bio_process_time); + blk_perf.total_write_size += count; + blk_perf.write_hist[bio_process_time_ms] += count; + + } else { + if (ktime_after(bio_process_time, blk_perf.max_read_time)) + blk_perf.max_read_time = bio_process_time; + + if (ktime_before(bio_process_time, blk_perf.min_read_time)) + blk_perf.min_read_time = bio_process_time; + blk_perf.total_read_time = + ktime_add(blk_perf.total_read_time, bio_process_time); + blk_perf.total_read_size += count; + blk_perf.read_hist[bio_process_time_ms] += count; + } +} +void blk_update_perf_stats(struct bio *bio) +{ + ktime_t bio_process_time; + u32 bio_process_time_ms; + u32 count; + + spin_lock(&blk_perf.lock); + if (likely(!blk_perf.is_enabled)) + goto end; + if (!bio->submit_time.tv64) + goto end; + bio_process_time = ktime_sub(ktime_get(), bio->submit_time); + + count = bio->blk_sector_count; + + if (count) { + int is_write = 0; + + if (bio->bi_rw & WRITE || + unlikely(bio->bi_rw & REQ_WRITE_SAME)) + is_write = 1; + + blk_update_perf_read_write_stats(bio_process_time, is_write, + count); + } else { + + bio_process_time_ms = ktime_to_ms(bio_process_time); + if (bio_process_time_ms >= BLK_PERF_SIZE) + bio_process_time_ms = BLK_PERF_SIZE - 1; + + if (ktime_after(bio_process_time, blk_perf.max_flush_time)) + blk_perf.max_flush_time = bio_process_time; + + if (ktime_before(bio_process_time, blk_perf.min_flush_time)) + blk_perf.min_flush_time = bio_process_time; + + blk_perf.flush_hist[bio_process_time_ms] += 1; + } +end: + spin_unlock(&blk_perf.lock); + +} +#else +static inline void set_submit_info(struct bio *bio, unsigned int count) +{ + (void) bio; + (void) count; +} + +static inline void blk_init_perf(void) +{ +} +#endif /* #ifdef CONFIG_BLOCK_PERF_FRAMEWORK */ + /** * submit_bio - submit a bio to the block device layer for I/O * @rw: whether to %READ or %WRITE, or maybe to %READA (read ahead) @@ -2117,6 +2602,7 @@ */ blk_qc_t submit_bio(int rw, struct bio *bio) { + unsigned int count = 0; bio->bi_rw |= rw; /* @@ -2124,8 +2610,6 @@ * go through the normal accounting stuff before submission. */ if (bio_has_data(bio)) { - unsigned int count; - if (unlikely(rw & REQ_WRITE_SAME)) count = bdev_logical_block_size(bio->bi_bdev) >> 9; else @@ -2140,8 +2624,11 @@ if (unlikely(block_dump)) { char b[BDEVNAME_SIZE]; + struct task_struct *tsk; + + tsk = get_dirty_task(bio); printk(KERN_DEBUG "%s(%d): %s block %Lu on %s (%u sectors)\n", - current->comm, task_pid_nr(current), + tsk->comm, task_pid_nr(tsk), (rw & WRITE) ? "WRITE" : "READ", (unsigned long long)bio->bi_iter.bi_sector, bdevname(bio->bi_bdev, b), @@ -2149,6 +2636,7 @@ } } + set_submit_info(bio, count); return generic_make_request(bio); } EXPORT_SYMBOL(submit_bio); @@ -2645,6 +3133,15 @@ blk_account_io_completion(req, nr_bytes); total_bytes = 0; + + /* + * Check for this if flagged, Req based dm needs to perform + * post processing, hence dont end bios or request.DM + * layer takes care. + */ + if (bio_flagged(req->bio, BIO_DONTFREE)) + return false; + while (req->bio) { struct bio *bio = req->bio; unsigned bio_bytes = min(bio->bi_iter.bi_size, nr_bytes); @@ -2751,7 +3248,7 @@ BUG_ON(blk_queued_rq(req)); if (unlikely(laptop_mode) && req->cmd_type == REQ_TYPE_FS) - laptop_io_completion(&req->q->backing_dev_info); + laptop_io_completion(req->q->backing_dev_info); blk_delete_timer(req); @@ -3560,6 +4057,55 @@ blk_requestq_cachep = kmem_cache_create("blkdev_queue", sizeof(struct request_queue), 0, SLAB_PANIC, NULL); - + blk_init_perf(); return 0; } + +/* + * Blk IO latency support. We want this to be as cheap as possible, so doing + * this lockless (and avoiding atomics), a few off by a few errors in this + * code is not harmful, and we don't want to do anything that is + * perf-impactful. + * TODO : If necessary, we can make the histograms per-cpu and aggregate + * them when printing them out. + */ +ssize_t +blk_latency_hist_show(char* name, struct io_latency_state *s, char *buf, + int buf_size) +{ + int i; + int bytes_written = 0; + u_int64_t num_elem, elem; + int pct; + u_int64_t average; + + num_elem = s->latency_elems; + if (num_elem > 0) { + average = div64_u64(s->latency_sum, s->latency_elems); + bytes_written += scnprintf(buf + bytes_written, + buf_size - bytes_written, + "IO svc_time %s Latency Histogram (n = %llu," + " average = %llu):\n", name, num_elem, average); + for (i = 0; + i < ARRAY_SIZE(latency_x_axis_us); + i++) { + elem = s->latency_y_axis[i]; + pct = div64_u64(elem * 100, num_elem); + bytes_written += scnprintf(buf + bytes_written, + PAGE_SIZE - bytes_written, + "\t< %6lluus%15llu%15d%%\n", + latency_x_axis_us[i], + elem, pct); + } + /* Last element in y-axis table is overflow */ + elem = s->latency_y_axis[i]; + pct = div64_u64(elem * 100, num_elem); + bytes_written += scnprintf(buf + bytes_written, + PAGE_SIZE - bytes_written, + "\t>=%6lluus%15llu%15d%%\n", + latency_x_axis_us[i - 1], elem, pct); + } + + return bytes_written; +} +EXPORT_SYMBOL(blk_latency_hist_show); diff -ruw linux-4.4.115/block/blk-flush.c linux-4.4.115-fbx/block/blk-flush.c --- linux-4.4.115/block/blk-flush.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/block/blk-flush.c 2019-01-22 16:16:22.715239271 +0100 @@ -62,6 +62,45 @@ * The above peculiarity requires that each FLUSH/FUA request has only one * bio attached to it, which is guaranteed as they aren't allowed to be * merged in the usual way. + * + * Cache Barrier support: + * + * Cache barrier is a requests that instruct the storage devices to apply some + * ordering when writing data from the device's cache to the medium. Write + * requests arriving before a 'cache barrier' request will be written to the + * medium before write requests that will arrive after the 'cache barrier'. + * Since the barrier request is not supported by all block devices, the + * appropriate fallback is flush request. This will make sure application using + * it can relay on correct functionality without consider the specification of + * the device. + * + * If a barrier request is queued, it will follow the same path as a flush + * request. When its time to issue the request, the flush pending list will + * be scanned and if it contains only requests marked with barrier, a barrier + * request will be issued. Otherwise, if at least one flush is pending - flush + * will be issued. + * A barrier request is a flush request marked with the REQ_BARRIER flag. It + * is the LLD responsibility to test this flag if it supports the barrier + * feature and decide whether to issue a flush or a barrier request. + * + * When considering a barrier request, three sequences must be addressed: + * 1. (A)Barrier -> (B)Data, This sequence will be marked with + * WRITE_FLUSH_BARRIER or (REQ_FLUSH | REQ_BARRIER). + * This scenario will be split to a PREFLUSH and DATA and no additional + * execution phase are required. If barrier is not supported, a flush + * will be issued instead (A). + * 2. (A)Data -> (B)Barrier, This sequence will be marked with + * WRITE_POST_FLUSH_BARRIER or (REQ_POST_FLUSH_BARRIER | REQ_BARRIER). + * This request, when barrier is supported, this request will execute DATA + * and than POSTFLUSH. + * If barrier is not supported, but FUA is. The barrier may be replaced + * with DATA+FUA. + * If barrier and FUA are not supported, a flush must be issued instead of + * (B). This is similar to current FUA fallback. + * 3. (A)Barrier -> (B)Data -> (C)Barrier, This sequence will be marked with + * WRITE_ORDERED_FLUSH_BARRIER or (REQ_FLUSH | REQ_POST_FLUSH_BARRIER | + * REQ_BARRIER). This scenario is just a combination of the previous two, + * and no additional logic is required. */ #include @@ -105,8 +144,26 @@ if (fflags & REQ_FLUSH) { if (rq->cmd_flags & REQ_FLUSH) policy |= REQ_FSEQ_PREFLUSH; - if (!(fflags & REQ_FUA) && (rq->cmd_flags & REQ_FUA)) + /* + * Use post flush when: + * 1. If FUA is desired but not supported, + * 2. If post barrier is desired and supported + * 3. If post barrier is desired and not supported and FUA is + * not supported. + */ + if ((!(fflags & REQ_FUA) && (rq->cmd_flags & REQ_FUA)) || + ((fflags & REQ_BARRIER) && (rq->cmd_flags & + REQ_POST_FLUSH_BARRIER)) || + ((!(fflags & REQ_BARRIER) && !(fflags & REQ_FUA) && + (rq->cmd_flags & REQ_POST_FLUSH_BARRIER)))) policy |= REQ_FSEQ_POSTFLUSH; + /* + * If post barrier is desired and not supported but FUA is + * supported append FUA flag. + */ + if ((rq->cmd_flags & REQ_POST_FLUSH_BARRIER) && + !(fflags & REQ_BARRIER) && (fflags & REQ_FUA)) + rq->cmd_flags |= REQ_FUA; } return policy; } @@ -290,9 +347,10 @@ static bool blk_kick_flush(struct request_queue *q, struct blk_flush_queue *fq) { struct list_head *pending = &fq->flush_queue[fq->flush_pending_idx]; - struct request *first_rq = + struct request *rq, *n, *first_rq = list_first_entry(pending, struct request, flush.list); struct request *flush_rq = fq->flush_rq; + u64 barrier_flag = REQ_BARRIER; /* C1 described at the top of this file */ if (fq->flush_pending_idx != fq->flush_running_idx || list_empty(pending)) @@ -330,6 +388,12 @@ flush_rq->cmd_type = REQ_TYPE_FS; flush_rq->cmd_flags = WRITE_FLUSH | REQ_FLUSH_SEQ; + /* Issue a barrier only if all pending flushes request it */ + list_for_each_entry_safe(rq, n, pending, flush.list) { + barrier_flag &= rq->cmd_flags; + } + flush_rq->cmd_flags |= barrier_flag; + flush_rq->rq_disk = first_rq->rq_disk; flush_rq->end_io = flush_end_io; @@ -388,6 +452,8 @@ unsigned int policy = blk_flush_policy(fflags, rq); struct blk_flush_queue *fq = blk_get_flush_queue(q, rq->mq_ctx); + WARN_ON((rq->cmd_flags & REQ_POST_FLUSH_BARRIER) && + !blk_rq_sectors(rq)); /* * @policy now records what operations need to be done. Adjust * REQ_FLUSH and FUA for the driver. @@ -447,20 +513,8 @@ blk_flush_complete_seq(rq, fq, REQ_FSEQ_ACTIONS & ~policy, 0); } -/** - * blkdev_issue_flush - queue a flush - * @bdev: blockdev to issue flush for - * @gfp_mask: memory allocation flags (for bio_alloc) - * @error_sector: error sector - * - * Description: - * Issue a flush for the block device in question. Caller can supply - * room for storing the error offset in case of a flush error, if they - * wish to. If WAIT flag is not passed then caller may check only what - * request was pushed in some internal queue for later handling. - */ -int blkdev_issue_flush(struct block_device *bdev, gfp_t gfp_mask, - sector_t *error_sector) +static int __blkdev_issue_flush(struct block_device *bdev, gfp_t gfp_mask, + sector_t *error_sector, int flush_type) { struct request_queue *q; struct bio *bio; @@ -485,7 +539,7 @@ bio = bio_alloc(gfp_mask, 0); bio->bi_bdev = bdev; - ret = submit_bio_wait(WRITE_FLUSH, bio); + ret = submit_bio_wait(flush_type, bio); /* * The driver must store the error location in ->bi_sector, if @@ -498,6 +552,45 @@ bio_put(bio); return ret; } + +/** + * blkdev_issue_barrier - queue a barrier + * @bdev: blockdev to issue barrier for + * @gfp_mask: memory allocation flags (for bio_alloc) + * @error_sector: error sector + * + * Description: + * If blkdev supports the barrier API, issue barrier, otherwise issue a + * flush Caller can supply room for storing the error offset in case of a + * flush error, if they wish to. If WAIT flag is not passed then caller may + * check only what request was pushed in some internal queue for later + * handling. + */ +int blkdev_issue_barrier(struct block_device *bdev, gfp_t gfp_mask, + sector_t *error_sector) +{ + return __blkdev_issue_flush(bdev, gfp_mask, error_sector, + WRITE_FLUSH_BARRIER); +} +EXPORT_SYMBOL(blkdev_issue_barrier); + +/** + * blkdev_issue_flush - queue a flush + * @bdev: blockdev to issue flush for + * @gfp_mask: memory allocation flags (for bio_alloc) + * @error_sector: error sector + * + * Description: + * Issue a flush for the block device in question. Caller can supply + * room for storing the error offset in case of a flush error, if they + * wish to. If WAIT flag is not passed then caller may check only what + * request was pushed in some internal queue for later handling. + */ +int blkdev_issue_flush(struct block_device *bdev, gfp_t gfp_mask, + sector_t *error_sector) +{ + return __blkdev_issue_flush(bdev, gfp_mask, error_sector, WRITE_FLUSH); +} EXPORT_SYMBOL(blkdev_issue_flush); struct blk_flush_queue *blk_alloc_flush_queue(struct request_queue *q, diff -ruw linux-4.4.115/block/blk.h linux-4.4.115-fbx/block/blk.h --- linux-4.4.115/block/blk.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/block/blk.h 2019-01-22 16:16:22.723239343 +0100 @@ -112,6 +112,15 @@ void blk_account_io_completion(struct request *req, unsigned int bytes); void blk_account_io_done(struct request *req); +#ifdef CONFIG_BLOCK_PERF_FRAMEWORK +void blk_update_perf_stats(struct bio *bio); +#else +static inline void blk_update_perf_stats(struct bio *bio) +{ + (void) bio; +} +#endif + /* * Internal atomic flags for request handling */ @@ -214,7 +223,6 @@ int attempt_front_merge(struct request_queue *q, struct request *rq); int blk_attempt_req_merge(struct request_queue *q, struct request *rq, struct request *next); -void blk_recalc_rq_segments(struct request *rq); void blk_rq_set_mixed_merge(struct request *rq); bool blk_rq_merge_ok(struct request *rq, struct bio *bio); int blk_try_merge(struct request *rq, struct bio *bio); diff -ruw linux-4.4.115/block/blk-merge.c linux-4.4.115-fbx/block/blk-merge.c --- linux-4.4.115/block/blk-merge.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/block/blk-merge.c 2019-01-22 16:16:22.719239307 +0100 @@ -6,6 +6,8 @@ #include #include #include +#include +#include #include "blk.h" @@ -488,6 +490,93 @@ } EXPORT_SYMBOL(blk_rq_map_sg); +/* + * map a request to scatterlist without combining PHY CONT + * blocks, return number of sg entries setup. Caller + * must make sure sg can hold rq->nr_phys_segments entries + */ +int blk_rq_map_sg_no_cluster(struct request_queue *q, struct request *rq, + struct scatterlist *sglist) +{ + struct bio_vec bvec, bvprv = { NULL }; + struct req_iterator iter; + struct scatterlist *sg; + int nsegs, cluster = 0; + + nsegs = 0; + + /* + * for each bio in rq + */ + sg = NULL; + rq_for_each_segment(bvec, rq, iter) { + __blk_segment_map_sg(q, &bvec, sglist, &bvprv, &sg, + &nsegs, &cluster); + } /* segments in rq */ + + + if (!sg) + return nsegs; + + if (unlikely(rq->cmd_flags & REQ_COPY_USER) && + (blk_rq_bytes(rq) & q->dma_pad_mask)) { + unsigned int pad_len = + (q->dma_pad_mask & ~blk_rq_bytes(rq)) + 1; + + sg->length += pad_len; + rq->extra_len += pad_len; + } + + if (q->dma_drain_size && q->dma_drain_needed(rq)) { + if (rq->cmd_flags & REQ_WRITE) + memset(q->dma_drain_buffer, 0, q->dma_drain_size); + + sg->page_link &= ~0x02; + sg = sg_next(sg); + sg_set_page(sg, virt_to_page(q->dma_drain_buffer), + q->dma_drain_size, + ((unsigned long)q->dma_drain_buffer) & + (PAGE_SIZE - 1)); + nsegs++; + rq->extra_len += q->dma_drain_size; + } + + if (sg) + sg_mark_end(sg); + + return nsegs; +} +EXPORT_SYMBOL(blk_rq_map_sg_no_cluster); + +/** + * blk_bio_map_sg - map a bio to a scatterlist + * @q: request_queue in question + * @bio: bio being mapped + * @sglist: scatterlist being mapped + * + * Note: + * Caller must make sure sg can hold bio->bi_phys_segments entries + * + * Will return the number of sg entries setup + */ +int blk_bio_map_sg(struct request_queue *q, struct bio *bio, + struct scatterlist *sglist) +{ + struct scatterlist *sg = NULL; + int nsegs; + struct bio *next = bio->bi_next; + + bio->bi_next = NULL; + nsegs = __blk_bios_map_sg(q, bio, sglist, &sg); + bio->bi_next = next; + if (sg) + sg_mark_end(sg); + + WARN_ON(bio->bi_phys_segments && nsegs > bio->bi_phys_segments); + return nsegs; +} +EXPORT_SYMBOL(blk_bio_map_sg); + static inline int ll_new_hw_segment(struct request_queue *q, struct request *req, struct bio *bio) @@ -663,6 +752,12 @@ } } +static bool crypto_not_mergeable(const struct bio *bio, const struct bio *nxt) +{ + return (!pft_allow_merge_bio(bio, nxt) || + !pfk_allow_merge_bio(bio, nxt)); +} + /* * Has to be called with the request spinlock acquired */ @@ -690,6 +785,9 @@ !blk_write_same_mergeable(req->bio, next->bio)) return 0; + if (crypto_not_mergeable(req->bio, next->bio)) + return 0; + /* * If we are allowed to merge, then append bio list * from next to rq and release next. merge_requests_fn @@ -794,6 +892,9 @@ !blk_write_same_mergeable(rq->bio, bio)) return false; + if (crypto_not_mergeable(rq->bio, bio)) + return false; + return true; } diff -ruw linux-4.4.115/block/blk-mq.c linux-4.4.115-fbx/block/blk-mq.c --- linux-4.4.115/block/blk-mq.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/block/blk-mq.c 2019-10-29 09:26:23.333200144 +0100 @@ -1782,10 +1782,6 @@ INIT_LIST_HEAD(&__ctx->rq_list); __ctx->queue = q; - /* If the cpu isn't online, the cpu is mapped to first hctx */ - if (!cpu_online(i)) - continue; - hctx = q->mq_ops->map_queue(q, i); /* @@ -1819,11 +1815,8 @@ * Map software to hardware queues */ queue_for_each_ctx(q, ctx, i) { - /* If the cpu isn't online, the cpu is mapped to first hctx */ - if (!cpumask_test_cpu(i, online_mask)) - continue; - hctx = q->mq_ops->map_queue(q, i); + if (cpumask_test_cpu(i, online_mask)) cpumask_set_cpu(i, hctx->cpumask); ctx->index_hw = hctx->nr_ctx; hctx->ctxs[hctx->nr_ctx++] = ctx; @@ -1862,16 +1855,21 @@ /* * Initialize batch roundrobin counts + * Set next_cpu for only those hctxs that have an online CPU + * in their cpumask field. For hctxs that belong to few online + * and few offline CPUs, this will always provide one CPU from + * online ones. For hctxs belonging to all offline CPUs, their + * cpumask will be updated in reinit_notify. */ + if (cpumask_first(hctx->cpumask) < nr_cpu_ids) { hctx->next_cpu = cpumask_first(hctx->cpumask); hctx->next_cpu_batch = BLK_MQ_CPU_WORK_BATCH; } + } queue_for_each_ctx(q, ctx, i) { - if (!cpumask_test_cpu(i, online_mask)) - continue; - hctx = q->mq_ops->map_queue(q, i); + if (cpumask_test_cpu(i, online_mask)) cpumask_set_cpu(i, hctx->tags->cpumask); } } @@ -2100,38 +2098,13 @@ blk_mq_free_hw_queues(q, set); } -/* Basically redo blk_mq_init_queue with queue frozen */ -static void blk_mq_queue_reinit(struct request_queue *q, - const struct cpumask *online_mask) -{ - WARN_ON_ONCE(!atomic_read(&q->mq_freeze_depth)); - - blk_mq_sysfs_unregister(q); - - blk_mq_update_queue_map(q->mq_map, q->nr_hw_queues, online_mask); - - /* - * redo blk_mq_init_cpu_queues and blk_mq_init_hw_queues. FIXME: maybe - * we should change hctx numa_node according to new topology (this - * involves free and re-allocate memory, worthy doing?) - */ - - blk_mq_map_swqueue(q, online_mask); - - blk_mq_sysfs_register(q); -} - static int blk_mq_queue_reinit_notify(struct notifier_block *nb, unsigned long action, void *hcpu) { struct request_queue *q; + struct blk_mq_hw_ctx *hctx; + int i; int cpu = (unsigned long)hcpu; - /* - * New online cpumask which is going to be set in this hotplug event. - * Declare this cpumasks as global as cpu-hotplug operation is invoked - * one-by-one and dynamically allocating this could result in a failure. - */ - static struct cpumask online_new; /* * Before hotadded cpu starts handling requests, new mappings must @@ -2153,44 +2126,31 @@ switch (action & ~CPU_TASKS_FROZEN) { case CPU_DEAD: case CPU_UP_CANCELED: - cpumask_copy(&online_new, cpu_online_mask); + mutex_lock(&all_q_mutex); + list_for_each_entry(q, &all_q_list, all_q_node) { + queue_for_each_hw_ctx(q, hctx, i) { + cpumask_clear_cpu(cpu, hctx->cpumask); + cpumask_clear_cpu(cpu, hctx->tags->cpumask); + } + } + mutex_unlock(&all_q_mutex); break; case CPU_UP_PREPARE: - cpumask_copy(&online_new, cpu_online_mask); - cpumask_set_cpu(cpu, &online_new); + /* Update hctx->cpumask for newly onlined CPUs */ + mutex_lock(&all_q_mutex); + list_for_each_entry(q, &all_q_list, all_q_node) { + queue_for_each_hw_ctx(q, hctx, i) { + cpumask_set_cpu(cpu, hctx->cpumask); + hctx->next_cpu_batch = BLK_MQ_CPU_WORK_BATCH; + cpumask_set_cpu(cpu, hctx->tags->cpumask); + } + } + mutex_unlock(&all_q_mutex); break; default: return NOTIFY_OK; } - mutex_lock(&all_q_mutex); - - /* - * We need to freeze and reinit all existing queues. Freezing - * involves synchronous wait for an RCU grace period and doing it - * one by one may take a long time. Start freezing all queues in - * one swoop and then wait for the completions so that freezing can - * take place in parallel. - */ - list_for_each_entry(q, &all_q_list, all_q_node) - blk_mq_freeze_queue_start(q); - list_for_each_entry(q, &all_q_list, all_q_node) { - blk_mq_freeze_queue_wait(q); - - /* - * timeout handler can't touch hw queue during the - * reinitialization - */ - del_timer_sync(&q->timeout); - } - - list_for_each_entry(q, &all_q_list, all_q_node) - blk_mq_queue_reinit(q, &online_new); - - list_for_each_entry(q, &all_q_list, all_q_node) - blk_mq_unfreeze_queue(q); - - mutex_unlock(&all_q_mutex); return NOTIFY_OK; } diff -ruw linux-4.4.115/block/blk-mq-cpumap.c linux-4.4.115-fbx/block/blk-mq-cpumap.c --- linux-4.4.115/block/blk-mq-cpumap.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/block/blk-mq-cpumap.c 2019-01-22 16:16:22.719239307 +0100 @@ -31,8 +31,8 @@ return cpu; } -int blk_mq_update_queue_map(unsigned int *map, unsigned int nr_queues, - const struct cpumask *online_mask) +static int blk_mq_update_queue_map(unsigned int *map, + unsigned int nr_queues, const struct cpumask *online_mask) { unsigned int i, nr_cpus, nr_uniq_cpus, queue, first_sibling; cpumask_var_t cpus; @@ -52,18 +52,14 @@ queue = 0; for_each_possible_cpu(i) { - if (!cpumask_test_cpu(i, online_mask)) { - map[i] = 0; - continue; - } - /* * Easy case - we have equal or more hardware queues. Or * there are no thread siblings to take into account. Do * 1:1 if enough, or sequential mapping if less. */ - if (nr_queues >= nr_cpus || nr_cpus == nr_uniq_cpus) { - map[i] = cpu_to_queue_index(nr_cpus, nr_queues, queue); + if (nr_queues >= nr_cpu_ids) { + map[i] = cpu_to_queue_index(nr_cpu_ids, nr_queues, + queue); queue++; continue; } @@ -75,7 +71,7 @@ */ first_sibling = get_first_sibling(i); if (first_sibling == i) { - map[i] = cpu_to_queue_index(nr_uniq_cpus, nr_queues, + map[i] = cpu_to_queue_index(nr_cpu_ids, nr_queues, queue); queue++; } else diff -ruw linux-4.4.115/block/blk-mq.h linux-4.4.115-fbx/block/blk-mq.h --- linux-4.4.115/block/blk-mq.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/block/blk-mq.h 2019-01-22 16:16:22.719239307 +0100 @@ -48,8 +48,6 @@ * CPU -> queue mappings */ extern unsigned int *blk_mq_make_queue_map(struct blk_mq_tag_set *set); -extern int blk_mq_update_queue_map(unsigned int *map, unsigned int nr_queues, - const struct cpumask *online_mask); extern int blk_mq_hw_queue_to_node(unsigned int *map, unsigned int); /* diff -ruw linux-4.4.115/block/blk-settings.c linux-4.4.115-fbx/block/blk-settings.c --- linux-4.4.115/block/blk-settings.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/block/blk-settings.c 2019-10-29 09:26:23.337200184 +0100 @@ -823,20 +823,24 @@ /** * blk_queue_flush - configure queue's cache flush capability * @q: the request queue for the device - * @flush: 0, REQ_FLUSH or REQ_FLUSH | REQ_FUA + * @flush: 0, REQ_FLUSH or REQ_FLUSH | REQ_FUA | REQ_BARRIER * * Tell block layer cache flush capability of @q. If it supports * flushing, REQ_FLUSH should be set. If it supports bypassing - * write cache for individual writes, REQ_FUA should be set. + * write cache for individual writes, REQ_FUA should be set. If cache + * barrier is supported set REQ_BARRIER. */ void blk_queue_flush(struct request_queue *q, unsigned int flush) { - WARN_ON_ONCE(flush & ~(REQ_FLUSH | REQ_FUA)); + WARN_ON_ONCE(flush & ~(REQ_FLUSH | REQ_FUA | REQ_BARRIER)); - if (WARN_ON_ONCE(!(flush & REQ_FLUSH) && (flush & REQ_FUA))) + if (WARN_ON_ONCE(!(flush & REQ_FLUSH) && ((flush & REQ_FUA) || + (flush & REQ_BARRIER)))) { flush &= ~REQ_FUA; + flush &= ~REQ_BARRIER; + } - q->flush_flags = flush & (REQ_FLUSH | REQ_FUA); + q->flush_flags = flush & (REQ_FLUSH | REQ_FUA | REQ_BARRIER); } EXPORT_SYMBOL_GPL(blk_queue_flush); diff -ruw linux-4.4.115/block/blk-sysfs.c linux-4.4.115-fbx/block/blk-sysfs.c --- linux-4.4.115/block/blk-sysfs.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/block/blk-sysfs.c 2019-10-29 09:26:23.337200184 +0100 @@ -75,7 +75,7 @@ static ssize_t queue_ra_show(struct request_queue *q, char *page) { - unsigned long ra_kb = q->backing_dev_info.ra_pages << + unsigned long ra_kb = q->backing_dev_info->ra_pages << (PAGE_CACHE_SHIFT - 10); return queue_var_show(ra_kb, (page)); @@ -90,7 +90,7 @@ if (ret < 0) return ret; - q->backing_dev_info.ra_pages = ra_kb >> (PAGE_CACHE_SHIFT - 10); + q->backing_dev_info->ra_pages = ra_kb >> (PAGE_CACHE_SHIFT - 10); return ret; } @@ -578,7 +578,7 @@ struct request_queue *q = container_of(kobj, struct request_queue, kobj); - bdi_exit(&q->backing_dev_info); + bdi_put(q->backing_dev_info); blkcg_exit_queue(q); if (q->elevator) { diff -ruw linux-4.4.115/block/elevator.c linux-4.4.115-fbx/block/elevator.c --- linux-4.4.115/block/elevator.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/block/elevator.c 2019-01-22 16:16:22.727239379 +0100 @@ -538,7 +538,7 @@ #ifdef CONFIG_PM static void blk_pm_requeue_request(struct request *rq) { - if (rq->q->dev && !(rq->cmd_flags & REQ_PM)) + if (rq->q->dev && !(rq->cmd_flags & REQ_PM) && rq->q->nr_pending) rq->q->nr_pending--; } diff -ruw linux-4.4.115/block/genhd.c linux-4.4.115-fbx/block/genhd.c --- linux-4.4.115/block/genhd.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/block/genhd.c 2019-01-22 16:16:22.727239379 +0100 @@ -611,7 +611,7 @@ disk_alloc_events(disk); /* Register BDI before referencing it from bdev */ - bdi = &disk->queue->backing_dev_info; + bdi = disk->queue->backing_dev_info; bdi_register_owner(bdi, disk_to_dev(disk)); blk_register_region(disk_devt(disk), disk->minors, NULL, @@ -646,6 +646,8 @@ disk_part_iter_init(&piter, disk, DISK_PITER_INCL_EMPTY | DISK_PITER_REVERSE); while ((part = disk_part_iter_next(&piter))) { + bdev_unhash_inode(MKDEV(disk->major, + disk->first_minor + part->partno)); invalidate_partition(disk, part->partno); delete_partition(disk, part->partno); } @@ -656,7 +658,16 @@ disk->flags &= ~GENHD_FL_UP; sysfs_remove_link(&disk_to_dev(disk)->kobj, "bdi"); + if (disk->queue) { + /* + * Unregister bdi before releasing device numbers (as they can + * get reused and we'd get clashes in sysfs). + */ + bdi_unregister(disk->queue->backing_dev_info); blk_unregister_queue(disk); + } else { + WARN_ON(1); + } blk_unregister_region(disk_devt(disk), disk->minors); part_stat_set_all(&disk->part0, 0); @@ -1117,6 +1128,22 @@ blk_put_queue(disk->queue); kfree(disk); } + +static int disk_uevent(struct device *dev, struct kobj_uevent_env *env) +{ + struct gendisk *disk = dev_to_disk(dev); + struct disk_part_iter piter; + struct hd_struct *part; + int cnt = 0; + + disk_part_iter_init(&piter, disk, 0); + while((part = disk_part_iter_next(&piter))) + cnt++; + disk_part_iter_exit(&piter); + add_uevent_var(env, "NPARTS=%u", cnt); + return 0; +} + struct class block_class = { .name = "block", }; @@ -1136,6 +1163,7 @@ .groups = disk_attr_groups, .release = disk_release, .devnode = block_devnode, + .uevent = disk_uevent, }; #ifdef CONFIG_PROC_FS diff -ruw linux-4.4.115/block/Kconfig linux-4.4.115-fbx/block/Kconfig --- linux-4.4.115/block/Kconfig 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/block/Kconfig 2019-01-22 16:16:22.707239198 +0100 @@ -111,6 +111,13 @@ See Documentation/block/cmdline-partition.txt for more information. +config BLOCK_PERF_FRAMEWORK + bool "Enable Block device performance measurement framework" + default n + ---help--- + Enabling this option allows you to measure the performance at the + block layer. + menu "Partition Types" source "block/partitions/Kconfig" diff -ruw linux-4.4.115/block/Kconfig.iosched linux-4.4.115-fbx/block/Kconfig.iosched --- linux-4.4.115/block/Kconfig.iosched 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/block/Kconfig.iosched 2019-01-22 16:16:22.711239234 +0100 @@ -12,6 +12,17 @@ that do their own scheduling and require only minimal assistance from the kernel. +config IOSCHED_TEST + tristate "Test I/O scheduler" + depends on DEBUG_FS + default m + ---help--- + The test I/O scheduler is a duplicate of the noop scheduler with + addition of test utlity. + It allows testing a block device by dispatching specific requests + according to the test case and declare PASS/FAIL according to the + requests completion error code. + config IOSCHED_DEADLINE tristate "Deadline I/O scheduler" default y diff -ruw linux-4.4.115/block/Makefile linux-4.4.115-fbx/block/Makefile --- linux-4.4.115/block/Makefile 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/block/Makefile 2019-01-22 16:16:22.711239234 +0100 @@ -18,6 +18,7 @@ obj-$(CONFIG_IOSCHED_NOOP) += noop-iosched.o obj-$(CONFIG_IOSCHED_DEADLINE) += deadline-iosched.o obj-$(CONFIG_IOSCHED_CFQ) += cfq-iosched.o +obj-$(CONFIG_IOSCHED_TEST) += test-iosched.o obj-$(CONFIG_BLOCK_COMPAT) += compat_ioctl.o obj-$(CONFIG_BLK_CMDLINE_PARSER) += cmdline-parser.o diff -ruw linux-4.4.115/block/partition-generic.c linux-4.4.115-fbx/block/partition-generic.c --- linux-4.4.115/block/partition-generic.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/block/partition-generic.c 2019-10-29 09:26:23.341200223 +0100 @@ -216,10 +216,21 @@ kfree(p); } +static int part_uevent(struct device *dev, struct kobj_uevent_env *env) +{ + struct hd_struct *part = dev_to_part(dev); + + add_uevent_var(env, "PARTN=%u", part->partno); + if (part->info && part->info->volname[0]) + add_uevent_var(env, "PARTNAME=%s", part->info->volname); + return 0; +} + struct device_type part_type = { .name = "partition", .groups = part_attr_groups, .release = part_release, + .uevent = part_uevent, }; static void delete_partition_rcu_cb(struct rcu_head *head) diff -ruw linux-4.4.115/certs/Makefile linux-4.4.115-fbx/certs/Makefile --- linux-4.4.115/certs/Makefile 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/certs/Makefile 2019-10-29 09:26:23.341200223 +0100 @@ -17,6 +17,10 @@ quiet_cmd_extract_certs = EXTRACT_CERTS $(patsubst "%",%,$(2)) cmd_extract_certs = scripts/extract-cert $(2) $@ || ( rm $@; exit 1) +ifeq ($(CONFIG_SYSTEM_TRUSTED_KEYS),"verity.x509.pem") +SYSTEM_TRUSTED_KEYS_SRCPREFIX := $(srctree)/certs/ +endif + targets += x509_certificate_list $(obj)/x509_certificate_list: scripts/extract-cert $(SYSTEM_TRUSTED_KEYS_SRCPREFIX)$(SYSTEM_TRUSTED_KEYS_FILENAME) FORCE $(call if_changed,extract_certs,$(SYSTEM_TRUSTED_KEYS_SRCPREFIX)$(CONFIG_SYSTEM_TRUSTED_KEYS)) diff -ruw linux-4.4.115/crypto/api.c linux-4.4.115-fbx/crypto/api.c --- linux-4.4.115/crypto/api.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/crypto/api.c 2019-01-22 16:16:22.739239488 +0100 @@ -24,6 +24,7 @@ #include #include #include +#include #include "internal.h" LIST_HEAD(crypto_alg_list); @@ -611,5 +612,17 @@ } EXPORT_SYMBOL_GPL(crypto_has_alg); +void crypto_req_done(struct crypto_async_request *req, int err) +{ + struct crypto_wait *wait = req->data; + + if (err == -EINPROGRESS) + return; + + wait->err = err; + complete(&wait->completion); +} +EXPORT_SYMBOL_GPL(crypto_req_done); + MODULE_DESCRIPTION("Cryptographic core API"); MODULE_LICENSE("GPL"); diff -ruw linux-4.4.115/crypto/blkcipher.c linux-4.4.115-fbx/crypto/blkcipher.c --- linux-4.4.115/crypto/blkcipher.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/crypto/blkcipher.c 2019-10-29 09:26:23.345200262 +0100 @@ -373,6 +373,27 @@ } EXPORT_SYMBOL_GPL(blkcipher_aead_walk_virt_block); +/* + * This function allows ablkcipher algorithms to use the blkcipher_walk API to + * walk over their data. The specified crypto_ablkcipher tfm is used to + * initialize the struct blkcipher_walk, and the crypto_blkcipher specified in + * desc->tfm is never used so it can be left NULL. (Yes, this design is ugly, + * but it parallels blkcipher_aead_walk_virt_block() above. In the 4.10 kernel + * this is starting to be cleaned up...) + */ +int blkcipher_ablkcipher_walk_virt(struct blkcipher_desc *desc, + struct blkcipher_walk *walk, + struct crypto_ablkcipher *tfm) +{ + walk->flags &= ~BLKCIPHER_WALK_PHYS; + walk->walk_blocksize = crypto_ablkcipher_blocksize(tfm); + walk->cipher_blocksize = walk->walk_blocksize; + walk->ivsize = crypto_ablkcipher_ivsize(tfm); + walk->alignmask = crypto_ablkcipher_alignmask(tfm); + return blkcipher_walk_first(desc, walk); +} +EXPORT_SYMBOL_GPL(blkcipher_ablkcipher_walk_virt); + static int setkey_unaligned(struct crypto_tfm *tfm, const u8 *key, unsigned int keylen) { diff -ruw linux-4.4.115/crypto/gf128mul.c linux-4.4.115-fbx/crypto/gf128mul.c --- linux-4.4.115/crypto/gf128mul.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/crypto/gf128mul.c 2019-01-22 16:16:22.747239560 +0100 @@ -44,7 +44,7 @@ --------------------------------------------------------------------------- Issue 31/01/2006 - This file provides fast multiplication in GF(128) as required by several + This file provides fast multiplication in GF(2^128) as required by several cryptographic authentication modes */ @@ -88,37 +88,52 @@ q(0xf8), q(0xf9), q(0xfa), q(0xfb), q(0xfc), q(0xfd), q(0xfe), q(0xff) \ } -/* Given the value i in 0..255 as the byte overflow when a field element - in GHASH is multiplied by x^8, this function will return the values that - are generated in the lo 16-bit word of the field value by applying the - modular polynomial. The values lo_byte and hi_byte are returned via the - macro xp_fun(lo_byte, hi_byte) so that the values can be assembled into - memory as required by a suitable definition of this macro operating on - the table above +/* + * Given a value i in 0..255 as the byte overflow when a field element + * in GF(2^128) is multiplied by x^8, the following macro returns the + * 16-bit value that must be XOR-ed into the low-degree end of the + * product to reduce it modulo the irreducible polynomial x^128 + x^7 + + * x^2 + x + 1. + * + * There are two versions of the macro, and hence two tables: one for + * the "be" convention where the highest-order bit is the coefficient of + * the highest-degree polynomial term, and one for the "le" convention + * where the highest-order bit is the coefficient of the lowest-degree + * polynomial term. In both cases the values are stored in CPU byte + * endianness such that the coefficients are ordered consistently across + * bytes, i.e. in the "be" table bits 15..0 of the stored value + * correspond to the coefficients of x^15..x^0, and in the "le" table + * bits 15..0 correspond to the coefficients of x^0..x^15. + * + * Therefore, provided that the appropriate byte endianness conversions + * are done by the multiplication functions (and these must be in place + * anyway to support both little endian and big endian CPUs), the "be" + * table can be used for multiplications of both "bbe" and "ble" + * elements, and the "le" table can be used for multiplications of both + * "lle" and "lbe" elements. */ -#define xx(p, q) 0x##p##q - -#define xda_bbe(i) ( \ - (i & 0x80 ? xx(43, 80) : 0) ^ (i & 0x40 ? xx(21, c0) : 0) ^ \ - (i & 0x20 ? xx(10, e0) : 0) ^ (i & 0x10 ? xx(08, 70) : 0) ^ \ - (i & 0x08 ? xx(04, 38) : 0) ^ (i & 0x04 ? xx(02, 1c) : 0) ^ \ - (i & 0x02 ? xx(01, 0e) : 0) ^ (i & 0x01 ? xx(00, 87) : 0) \ +#define xda_be(i) ( \ + (i & 0x80 ? 0x4380 : 0) ^ (i & 0x40 ? 0x21c0 : 0) ^ \ + (i & 0x20 ? 0x10e0 : 0) ^ (i & 0x10 ? 0x0870 : 0) ^ \ + (i & 0x08 ? 0x0438 : 0) ^ (i & 0x04 ? 0x021c : 0) ^ \ + (i & 0x02 ? 0x010e : 0) ^ (i & 0x01 ? 0x0087 : 0) \ ) -#define xda_lle(i) ( \ - (i & 0x80 ? xx(e1, 00) : 0) ^ (i & 0x40 ? xx(70, 80) : 0) ^ \ - (i & 0x20 ? xx(38, 40) : 0) ^ (i & 0x10 ? xx(1c, 20) : 0) ^ \ - (i & 0x08 ? xx(0e, 10) : 0) ^ (i & 0x04 ? xx(07, 08) : 0) ^ \ - (i & 0x02 ? xx(03, 84) : 0) ^ (i & 0x01 ? xx(01, c2) : 0) \ +#define xda_le(i) ( \ + (i & 0x80 ? 0xe100 : 0) ^ (i & 0x40 ? 0x7080 : 0) ^ \ + (i & 0x20 ? 0x3840 : 0) ^ (i & 0x10 ? 0x1c20 : 0) ^ \ + (i & 0x08 ? 0x0e10 : 0) ^ (i & 0x04 ? 0x0708 : 0) ^ \ + (i & 0x02 ? 0x0384 : 0) ^ (i & 0x01 ? 0x01c2 : 0) \ ) -static const u16 gf128mul_table_lle[256] = gf128mul_dat(xda_lle); -static const u16 gf128mul_table_bbe[256] = gf128mul_dat(xda_bbe); +static const u16 gf128mul_table_le[256] = gf128mul_dat(xda_le); +static const u16 gf128mul_table_be[256] = gf128mul_dat(xda_be); -/* These functions multiply a field element by x, by x^4 and by x^8 - * in the polynomial field representation. It uses 32-bit word operations - * to gain speed but compensates for machine endianess and hence works +/* + * The following functions multiply a field element by x or by x^8 in + * the polynomial field representation. They use 64-bit word operations + * to gain speed but compensate for machine endianness and hence work * correctly on both styles of machine. */ @@ -126,7 +141,7 @@ { u64 a = be64_to_cpu(x->a); u64 b = be64_to_cpu(x->b); - u64 _tt = gf128mul_table_lle[(b << 7) & 0xff]; + u64 _tt = gf128mul_table_le[(b << 7) & 0xff]; r->b = cpu_to_be64((b >> 1) | (a << 63)); r->a = cpu_to_be64((a >> 1) ^ (_tt << 48)); @@ -136,7 +151,7 @@ { u64 a = be64_to_cpu(x->a); u64 b = be64_to_cpu(x->b); - u64 _tt = gf128mul_table_bbe[a >> 63]; + u64 _tt = gf128mul_table_be[a >> 63]; r->a = cpu_to_be64((a << 1) | (b >> 63)); r->b = cpu_to_be64((b << 1) ^ _tt); @@ -146,7 +161,7 @@ { u64 a = le64_to_cpu(x->a); u64 b = le64_to_cpu(x->b); - u64 _tt = gf128mul_table_bbe[b >> 63]; + u64 _tt = gf128mul_table_be[b >> 63]; r->a = cpu_to_le64((a << 1) ^ _tt); r->b = cpu_to_le64((b << 1) | (a >> 63)); @@ -157,7 +172,7 @@ { u64 a = be64_to_cpu(x->a); u64 b = be64_to_cpu(x->b); - u64 _tt = gf128mul_table_lle[b & 0xff]; + u64 _tt = gf128mul_table_le[b & 0xff]; x->b = cpu_to_be64((b >> 8) | (a << 56)); x->a = cpu_to_be64((a >> 8) ^ (_tt << 48)); @@ -167,12 +182,22 @@ { u64 a = be64_to_cpu(x->a); u64 b = be64_to_cpu(x->b); - u64 _tt = gf128mul_table_bbe[a >> 56]; + u64 _tt = gf128mul_table_be[a >> 56]; x->a = cpu_to_be64((a << 8) | (b >> 56)); x->b = cpu_to_be64((b << 8) ^ _tt); } +static void gf128mul_x8_ble(be128 *x) +{ + u64 a = le64_to_cpu(x->b); + u64 b = le64_to_cpu(x->a); + u64 _tt = gf128mul_table_be[a >> 56]; + + x->b = cpu_to_le64((a << 8) | (b >> 56)); + x->a = cpu_to_le64((b << 8) ^ _tt); +} + void gf128mul_lle(be128 *r, const be128 *b) { be128 p[8]; @@ -249,9 +274,48 @@ } EXPORT_SYMBOL(gf128mul_bbe); +void gf128mul_ble(be128 *r, const be128 *b) +{ + be128 p[8]; + int i; + + p[0] = *r; + for (i = 0; i < 7; ++i) + gf128mul_x_ble((be128 *)&p[i + 1], (be128 *)&p[i]); + + memset(r, 0, sizeof(*r)); + for (i = 0;;) { + u8 ch = ((u8 *)b)[15 - i]; + + if (ch & 0x80) + be128_xor(r, r, &p[7]); + if (ch & 0x40) + be128_xor(r, r, &p[6]); + if (ch & 0x20) + be128_xor(r, r, &p[5]); + if (ch & 0x10) + be128_xor(r, r, &p[4]); + if (ch & 0x08) + be128_xor(r, r, &p[3]); + if (ch & 0x04) + be128_xor(r, r, &p[2]); + if (ch & 0x02) + be128_xor(r, r, &p[1]); + if (ch & 0x01) + be128_xor(r, r, &p[0]); + + if (++i >= 16) + break; + + gf128mul_x8_ble(r); + } +} +EXPORT_SYMBOL(gf128mul_ble); + + /* This version uses 64k bytes of table space. A 16 byte buffer has to be multiplied by a 16 byte key - value in GF(128). If we consider a GF(128) value in + value in GF(2^128). If we consider a GF(2^128) value in the buffer's lowest byte, we can construct a table of the 256 16 byte values that result from the 256 values of this byte. This requires 4096 bytes. But we also @@ -352,8 +416,8 @@ int i; for (i = 0; i < 16; i++) - kfree(t->t[i]); - kfree(t); + kzfree(t->t[i]); + kzfree(t); } EXPORT_SYMBOL(gf128mul_free_64k); @@ -385,7 +449,7 @@ /* This version uses 4k bytes of table space. A 16 byte buffer has to be multiplied by a 16 byte key - value in GF(128). If we consider a GF(128) value in a + value in GF(2^128). If we consider a GF(2^128) value in a single byte, we can construct a table of the 256 16 byte values that result from the 256 values of this byte. This requires 4096 bytes. If we take the highest byte in @@ -443,6 +507,28 @@ } EXPORT_SYMBOL(gf128mul_init_4k_bbe); +struct gf128mul_4k *gf128mul_init_4k_ble(const be128 *g) +{ + struct gf128mul_4k *t; + int j, k; + + t = kzalloc(sizeof(*t), GFP_KERNEL); + if (!t) + goto out; + + t->t[1] = *g; + for (j = 1; j <= 64; j <<= 1) + gf128mul_x_ble(&t->t[j + j], &t->t[j]); + + for (j = 2; j < 256; j += j) + for (k = 1; k < j; ++k) + be128_xor(&t->t[j + k], &t->t[j], &t->t[k]); + +out: + return t; +} +EXPORT_SYMBOL(gf128mul_init_4k_ble); + void gf128mul_4k_lle(be128 *a, struct gf128mul_4k *t) { u8 *ap = (u8 *)a; @@ -473,5 +559,20 @@ } EXPORT_SYMBOL(gf128mul_4k_bbe); +void gf128mul_4k_ble(be128 *a, struct gf128mul_4k *t) +{ + u8 *ap = (u8 *)a; + be128 r[1]; + int i = 15; + + *r = t->t[ap[15]]; + while (i--) { + gf128mul_x8_ble(r); + be128_xor(r, r, &t->t[ap[i]]); + } + *a = *r; +} +EXPORT_SYMBOL(gf128mul_4k_ble); + MODULE_LICENSE("GPL"); MODULE_DESCRIPTION("Functions for multiplying elements of GF(2^128)"); diff -ruw linux-4.4.115/crypto/Kconfig linux-4.4.115-fbx/crypto/Kconfig --- linux-4.4.115/crypto/Kconfig 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/crypto/Kconfig 2019-10-29 09:26:23.345200262 +0100 @@ -289,6 +289,24 @@ CBC: Cipher Block Chaining mode This block cipher algorithm is required for IPSec. +config CRYPTO_HEH + tristate "HEH support" + select CRYPTO_CMAC + select CRYPTO_ECB + select CRYPTO_GF128MUL + select CRYPTO_MANAGER + select CRYPTO_POLY_HASH_ARM64_CE if ARM64 && KERNEL_MODE_NEON + help + HEH: Hash-Encrypt-Hash mode + HEH is a proposed block cipher mode of operation which extends the + strong pseudo-random permutation (SPRP) property of block ciphers to + arbitrary-length input strings. This provides a stronger notion of + security than existing block cipher modes of operation (e.g. CBC, CTR, + XTS), though it is usually less performant. Applications include disk + encryption and encryption of file names and contents. Currently, this + implementation only provides a symmetric cipher interface, so it can't + yet be used as an AEAD. + config CRYPTO_CTR tristate "CTR support" select CRYPTO_BLKCIPHER diff -ruw linux-4.4.115/crypto/Makefile linux-4.4.115-fbx/crypto/Makefile --- linux-4.4.115/crypto/Makefile 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/crypto/Makefile 2019-10-29 09:26:23.345200262 +0100 @@ -67,6 +67,7 @@ obj-$(CONFIG_CRYPTO_GF128MUL) += gf128mul.o obj-$(CONFIG_CRYPTO_ECB) += ecb.o obj-$(CONFIG_CRYPTO_CBC) += cbc.o +obj-$(CONFIG_CRYPTO_HEH) += heh.o obj-$(CONFIG_CRYPTO_PCBC) += pcbc.o obj-$(CONFIG_CRYPTO_CTS) += cts.o obj-$(CONFIG_CRYPTO_LRW) += lrw.o diff -ruw linux-4.4.115/crypto/shash.c linux-4.4.115-fbx/crypto/shash.c --- linux-4.4.115/crypto/shash.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/crypto/shash.c 2019-10-29 09:26:23.349200301 +0100 @@ -686,6 +686,14 @@ } EXPORT_SYMBOL_GPL(shash_free_instance); +int crypto_grab_shash(struct crypto_shash_spawn *spawn, + const char *name, u32 type, u32 mask) +{ + spawn->base.frontend = &crypto_shash_type; + return crypto_grab_spawn(&spawn->base, name, type, mask); +} +EXPORT_SYMBOL_GPL(crypto_grab_shash); + int crypto_init_shash_spawn(struct crypto_shash_spawn *spawn, struct shash_alg *alg, struct crypto_instance *inst) diff -ruw linux-4.4.115/crypto/testmgr.c linux-4.4.115-fbx/crypto/testmgr.c --- linux-4.4.115/crypto/testmgr.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/crypto/testmgr.c 2019-10-29 09:26:23.353200340 +0100 @@ -3215,6 +3215,21 @@ } } }, { + .alg = "heh(aes)", + .test = alg_test_skcipher, + .suite = { + .cipher = { + .enc = { + .vecs = aes_heh_enc_tv_template, + .count = AES_HEH_ENC_TEST_VECTORS + }, + .dec = { + .vecs = aes_heh_dec_tv_template, + .count = AES_HEH_DEC_TEST_VECTORS + } + } + } + }, { .alg = "hmac(crc32)", .test = alg_test_hash, .suite = { diff -ruw linux-4.4.115/drivers/amba/bus.c linux-4.4.115-fbx/drivers/amba/bus.c --- linux-4.4.115/drivers/amba/bus.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/amba/bus.c 2019-10-29 09:26:23.381200614 +0100 @@ -82,7 +82,8 @@ struct amba_device *dev = to_amba_device(_dev); char *driver_override, *old = dev->driver_override, *cp; - if (count > PATH_MAX) + /* We need to keep extra room for a newline */ + if (count >= (PAGE_SIZE - 1)) return -EINVAL; driver_override = kstrndup(buf, count, GFP_KERNEL); diff -ruw linux-4.4.115/drivers/android/Kconfig linux-4.4.115-fbx/drivers/android/Kconfig --- linux-4.4.115/drivers/android/Kconfig 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/android/Kconfig 2019-10-29 09:26:23.381200614 +0100 @@ -19,6 +19,18 @@ Android process, using Binder to identify, invoke and pass arguments between said processes. +config ANDROID_BINDER_DEVICES + string "Android Binder devices" + depends on ANDROID_BINDER_IPC + default "binder,hwbinder,vndbinder" + ---help--- + Default value for the binder.devices parameter. + + The binder.devices parameter is a comma-separated list of strings + that specifies the names of the binder device nodes that will be + created. Each binder device has its own context manager, and is + therefore logically separated from the other devices. + config ANDROID_BINDER_IPC_32BIT bool depends on !64BIT && ANDROID_BINDER_IPC @@ -32,6 +44,16 @@ Note that enabling this will break newer Android user-space. +config ANDROID_BINDER_IPC_SELFTEST + bool "Android Binder IPC Driver Selftest" + depends on ANDROID_BINDER_IPC + ---help--- + This feature allows binder selftest to run. + + Binder selftest checks the allocation and free of binder buffers + exhaustively with combinations of various buffer sizes and + alignments. + endif # if ANDROID endmenu diff -ruw linux-4.4.115/drivers/android/Makefile linux-4.4.115-fbx/drivers/android/Makefile --- linux-4.4.115/drivers/android/Makefile 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/android/Makefile 2019-01-22 16:16:22.823240249 +0100 @@ -1,3 +1,4 @@ ccflags-y += -I$(src) # needed for trace events -obj-$(CONFIG_ANDROID_BINDER_IPC) += binder.o +obj-$(CONFIG_ANDROID_BINDER_IPC) += binder.o binder_alloc.o +obj-$(CONFIG_ANDROID_BINDER_IPC_SELFTEST) += binder_alloc_selftest.o diff -ruw linux-4.4.115/drivers/base/core.c linux-4.4.115-fbx/drivers/base/core.c --- linux-4.4.115/drivers/base/core.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/base/core.c 2019-10-29 09:26:23.409200888 +0100 @@ -72,6 +72,11 @@ return restart_syscall(); } +void lock_device_hotplug_assert(void) +{ + lockdep_assert_held(&device_hotplug_lock); +} + #ifdef CONFIG_BLOCK static inline int device_is_not_partition(struct device *dev) { diff -ruw linux-4.4.115/drivers/base/cpu.c linux-4.4.115-fbx/drivers/base/cpu.c --- linux-4.4.115/drivers/base/cpu.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/base/cpu.c 2019-10-29 09:26:23.409200888 +0100 @@ -180,10 +180,177 @@ }; #endif +#ifdef CONFIG_HOTPLUG_CPU + +static ssize_t isolate_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct cpu *cpu = container_of(dev, struct cpu, dev); + ssize_t rc; + int cpuid = cpu->dev.id; + unsigned int isolated = cpu_isolated(cpuid); + + rc = snprintf(buf, PAGE_SIZE-2, "%d\n", isolated); + + return rc; +} + +static DEVICE_ATTR_RO(isolate); + +static struct attribute *cpu_isolated_attrs[] = { + &dev_attr_isolate.attr, + NULL +}; + +static struct attribute_group cpu_isolated_attr_group = { + .attrs = cpu_isolated_attrs, +}; + +#endif + +#ifdef CONFIG_SCHED_HMP + +static ssize_t show_sched_static_cpu_pwr_cost(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct cpu *cpu = container_of(dev, struct cpu, dev); + ssize_t rc; + int cpuid = cpu->dev.id; + unsigned int pwr_cost; + + pwr_cost = sched_get_static_cpu_pwr_cost(cpuid); + + rc = snprintf(buf, PAGE_SIZE-2, "%d\n", pwr_cost); + + return rc; +} + +static ssize_t __ref store_sched_static_cpu_pwr_cost(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + struct cpu *cpu = container_of(dev, struct cpu, dev); + int err; + int cpuid = cpu->dev.id; + unsigned int pwr_cost; + + err = kstrtouint(strstrip((char *)buf), 0, &pwr_cost); + if (err) + return err; + + err = sched_set_static_cpu_pwr_cost(cpuid, pwr_cost); + + if (err >= 0) + err = count; + + return err; +} + +static ssize_t show_sched_static_cluster_pwr_cost(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct cpu *cpu = container_of(dev, struct cpu, dev); + ssize_t rc; + int cpuid = cpu->dev.id; + unsigned int pwr_cost; + + pwr_cost = sched_get_static_cluster_pwr_cost(cpuid); + + rc = snprintf(buf, PAGE_SIZE-2, "%d\n", pwr_cost); + + return rc; +} + +static ssize_t __ref store_sched_static_cluster_pwr_cost(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + struct cpu *cpu = container_of(dev, struct cpu, dev); + int err; + int cpuid = cpu->dev.id; + unsigned int pwr_cost; + + err = kstrtouint(strstrip((char *)buf), 0, &pwr_cost); + if (err) + return err; + + err = sched_set_static_cluster_pwr_cost(cpuid, pwr_cost); + + if (err >= 0) + err = count; + + return err; +} + +static ssize_t show_sched_cluser_wake_idle(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct cpu *cpu = container_of(dev, struct cpu, dev); + ssize_t rc; + int cpuid = cpu->dev.id; + unsigned int wake_up_idle; + + wake_up_idle = sched_get_cluster_wake_idle(cpuid); + + rc = scnprintf(buf, PAGE_SIZE-2, "%d\n", wake_up_idle); + + return rc; +} + +static ssize_t __ref store_sched_cluster_wake_idle(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + struct cpu *cpu = container_of(dev, struct cpu, dev); + int err; + int cpuid = cpu->dev.id; + unsigned int wake_up_idle; + + err = kstrtouint(strstrip((char *)buf), 0, &wake_up_idle); + if (err) + return err; + + err = sched_set_cluster_wake_idle(cpuid, wake_up_idle); + + if (err >= 0) + err = count; + + return err; +} + +static DEVICE_ATTR(sched_static_cpu_pwr_cost, 0644, + show_sched_static_cpu_pwr_cost, + store_sched_static_cpu_pwr_cost); +static DEVICE_ATTR(sched_static_cluster_pwr_cost, 0644, + show_sched_static_cluster_pwr_cost, + store_sched_static_cluster_pwr_cost); +static DEVICE_ATTR(sched_cluster_wake_up_idle, 0644, + show_sched_cluser_wake_idle, + store_sched_cluster_wake_idle); + +static struct attribute *hmp_sched_cpu_attrs[] = { + &dev_attr_sched_static_cpu_pwr_cost.attr, + &dev_attr_sched_static_cluster_pwr_cost.attr, + &dev_attr_sched_cluster_wake_up_idle.attr, + NULL +}; + +static struct attribute_group sched_hmp_cpu_attr_group = { + .attrs = hmp_sched_cpu_attrs, +}; + +#endif /* CONFIG_SCHED_HMP */ + static const struct attribute_group *common_cpu_attr_groups[] = { #ifdef CONFIG_KEXEC &crash_note_cpu_attr_group, #endif +#ifdef CONFIG_SCHED_HMP + &sched_hmp_cpu_attr_group, +#endif +#ifdef CONFIG_HOTPLUG_CPU + &cpu_isolated_attr_group, +#endif NULL }; @@ -191,6 +358,12 @@ #ifdef CONFIG_KEXEC &crash_note_cpu_attr_group, #endif +#ifdef CONFIG_SCHED_HMP + &sched_hmp_cpu_attr_group, +#endif +#ifdef CONFIG_HOTPLUG_CPU + &cpu_isolated_attr_group, +#endif NULL }; @@ -220,6 +393,7 @@ _CPU_ATTR(online, &cpu_online_mask), _CPU_ATTR(possible, &cpu_possible_mask), _CPU_ATTR(present, &cpu_present_mask), + _CPU_ATTR(core_ctl_isolated, &cpu_isolated_mask), }; /* @@ -454,6 +628,7 @@ &cpu_attrs[0].attr.attr, &cpu_attrs[1].attr.attr, &cpu_attrs[2].attr.attr, + &cpu_attrs[3].attr.attr, &dev_attr_kernel_max.attr, &dev_attr_offline.attr, &dev_attr_isolated.attr, diff -ruw linux-4.4.115/drivers/base/dd.c linux-4.4.115-fbx/drivers/base/dd.c --- linux-4.4.115/drivers/base/dd.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/base/dd.c 2019-10-29 09:26:23.409200888 +0100 @@ -171,26 +171,49 @@ queue_work(deferred_wq, &deferred_probe_work); } +static void enable_trigger_defer_cycle(void) +{ + driver_deferred_probe_enable = true; + driver_deferred_probe_trigger(); + /* + * Sort as many dependencies as possible before the next initcall + * level + */ + flush_workqueue(deferred_wq); +} + /** * deferred_probe_initcall() - Enable probing of deferred devices * * We don't want to get in the way when the bulk of drivers are getting probed. * Instead, this initcall makes sure that deferred probing is delayed until - * late_initcall time. + * all the registered initcall functions at a particular level are completed. + * This function is invoked at every *_initcall_sync level. */ static int deferred_probe_initcall(void) { + if (!deferred_wq) { deferred_wq = create_singlethread_workqueue("deferwq"); if (WARN_ON(!deferred_wq)) return -ENOMEM; + } - driver_deferred_probe_enable = true; - driver_deferred_probe_trigger(); - /* Sort as many dependencies as possible before exiting initcalls */ - flush_workqueue(deferred_wq); + enable_trigger_defer_cycle(); + driver_deferred_probe_enable = false; + return 0; +} +arch_initcall_sync(deferred_probe_initcall); +subsys_initcall_sync(deferred_probe_initcall); +fs_initcall_sync(deferred_probe_initcall); +device_initcall_sync(deferred_probe_initcall); + +static int deferred_probe_enable_fn(void) +{ + /* Enable deferred probing for all time */ + enable_trigger_defer_cycle(); return 0; } -late_initcall(deferred_probe_initcall); +late_initcall(deferred_probe_enable_fn); static void driver_bound(struct device *dev) { @@ -205,6 +228,8 @@ klist_add_tail(&dev->p->knode_driver, &dev->driver->p->klist_devices); + device_pm_check_callbacks(dev); + /* * Make sure the device is no longer in one of the deferred lists and * kick off retrying all pending devices @@ -697,6 +722,7 @@ dev->pm_domain->dismiss(dev); klist_remove(&dev->p->knode_driver); + device_pm_check_callbacks(dev); if (dev->bus) blocking_notifier_call_chain(&dev->bus->p->bus_notifier, BUS_NOTIFY_UNBOUND_DRIVER, diff -ruw linux-4.4.115/drivers/base/dma-mapping.c linux-4.4.115-fbx/drivers/base/dma-mapping.c --- linux-4.4.115/drivers/base/dma-mapping.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/base/dma-mapping.c 2019-01-22 16:16:22.875240720 +0100 @@ -309,7 +309,12 @@ void *ptr; unsigned long pfn; - pages = kmalloc(sizeof(struct page *) << get_order(size), GFP_KERNEL); + pages = kmalloc(sizeof(struct page *) << get_order(size), + GFP_KERNEL | __GFP_NOWARN); + + if (!pages) + pages = vmalloc(sizeof(struct page *) << get_order(size)); + if (!pages) return NULL; @@ -318,20 +323,24 @@ ptr = dma_common_pages_remap(pages, size, vm_flags, prot, caller); - kfree(pages); + kvfree(pages); return ptr; } /* + area->pages = pages; + * unmaps a range previously mapped by dma_common_*_remap */ -void dma_common_free_remap(void *cpu_addr, size_t size, unsigned long vm_flags) +void dma_common_free_remap(void *cpu_addr, size_t size, unsigned long vm_flags, + bool no_warn) { struct vm_struct *area = find_vm_area(cpu_addr); if (!area || (area->flags & vm_flags) != vm_flags) { - WARN(1, "trying to free invalid coherent area: %p\n", cpu_addr); + WARN(!no_warn, "trying to free invalid coherent area: %p\n", + cpu_addr); return; } diff -ruw linux-4.4.115/drivers/base/firmware_class.c linux-4.4.115-fbx/drivers/base/firmware_class.c --- linux-4.4.115/drivers/base/firmware_class.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/base/firmware_class.c 2019-10-29 09:26:23.413200927 +0100 @@ -29,6 +29,7 @@ #include #include #include +#include #include @@ -111,6 +112,7 @@ #define FW_OPT_FALLBACK 0 #endif #define FW_OPT_NO_WARN (1U << 3) +#define FW_OPT_NOCACHE (1U << 4) struct firmware_cache { /* firmware_buf instance will be added into the below list */ @@ -142,6 +144,11 @@ unsigned long status; void *data; size_t size; + phys_addr_t dest_addr; + size_t dest_size; + void * (*map_fw_mem)(phys_addr_t phys, size_t size, void *data); + void (*unmap_fw_mem)(void *virt, size_t size, void *data); + void *map_data; #ifdef CONFIG_FW_LOADER_USER_HELPER bool is_paged_buf; bool need_uevent; @@ -163,6 +170,22 @@ const char *name; }; +struct fw_desc { + struct work_struct work; + const struct firmware **firmware_p; + const char *name; + struct device *device; + unsigned int opt_flags; + phys_addr_t dest_addr; + size_t dest_size; + void * (*map_fw_mem)(phys_addr_t phys, size_t size, void *data); + void (*unmap_fw_mem)(void *virt, size_t size, void *data); + void *map_data; + struct module *module; + void *context; + void (*cont)(const struct firmware *fw, void *context); +}; + #define to_fwbuf(d) container_of(d, struct firmware_buf, ref) #define FW_LOADER_NO_CACHE 0 @@ -249,6 +272,9 @@ (unsigned int)buf->size); list_del(&buf->list); +#ifdef CONFIG_FW_LOADER_USER_HELPER + list_del(&buf->pending_list); +#endif spin_unlock(&fwc->lock); #ifdef CONFIG_FW_LOADER_USER_HELPER @@ -268,6 +294,11 @@ static void fw_free_buf(struct firmware_buf *buf) { struct firmware_cache *fwc = buf->fwc; + if (!fwc) { + kfree_const(buf->fw_id); + kfree(buf); + return; + } spin_lock(&fwc->lock); if (!kref_put(&buf->ref, __fw_free_buf)) spin_unlock(&fwc->lock); @@ -280,7 +311,10 @@ "/lib/firmware/updates/" UTS_RELEASE, "/lib/firmware/updates", "/lib/firmware/" UTS_RELEASE, - "/lib/firmware" + "/lib/firmware", + "/lib64/firmware", + "/usr/lib/hotplug/firmware", + "/firmware/image" }; /* @@ -302,6 +336,13 @@ size = i_size_read(file_inode(file)); if (size <= 0) return -EINVAL; + if (fw_buf->dest_size > 0 && fw_buf->dest_size < size) + return -EINVAL; + + if (fw_buf->dest_addr) + buf = fw_buf->map_fw_mem(fw_buf->dest_addr, + fw_buf->dest_size, fw_buf->map_data); + else buf = vmalloc(size); if (!buf) return -ENOMEM; @@ -316,14 +357,20 @@ goto fail; fw_buf->data = buf; fw_buf->size = size; + if (fw_buf->dest_addr) + fw_buf->unmap_fw_mem(buf, fw_buf->size, fw_buf->map_data); return 0; fail: + if (fw_buf->dest_addr) + fw_buf->unmap_fw_mem(buf, fw_buf->size, fw_buf->map_data); + else vfree(buf); return rc; } static int fw_get_filesystem_firmware(struct device *device, - struct firmware_buf *buf) + struct firmware_buf *buf, + phys_addr_t dest_addr, size_t dest_size) { int i, len; int rc = -ENOENT; @@ -658,6 +705,10 @@ case 1: /* discarding any previous partial load */ if (!test_bit(FW_STATUS_DONE, &fw_buf->status)) { + if (fw_buf->dest_addr) { + set_bit(FW_STATUS_LOADING, &fw_buf->status); + break; + } for (i = 0; i < fw_buf->nr_pages; i++) __free_page(fw_buf->pages[i]); kfree(fw_buf->pages); @@ -715,6 +766,102 @@ static DEVICE_ATTR(loading, 0644, firmware_loading_show, firmware_loading_store); +static int __firmware_data_rw(struct firmware_priv *fw_priv, char *buffer, + loff_t *offset, size_t count, int read) +{ + u8 __iomem *fw_buf; + struct firmware_buf *buf = fw_priv->buf; + int retval = count; + + if ((*offset + count) > buf->dest_size) { + pr_debug("%s: Failed size check.\n", __func__); + retval = -EINVAL; + goto out; + } + + fw_buf = buf->map_fw_mem(buf->dest_addr + *offset, count, + buf->map_data); + if (!fw_buf) { + pr_debug("%s: Failed ioremap.\n", __func__); + retval = -ENOMEM; + goto out; + } + + if (read) + memcpy(buffer, fw_buf, count); + else + memcpy(fw_buf, buffer, count); + + *offset += count; + buf->unmap_fw_mem(fw_buf, count, buf->map_data); + +out: + return retval; +} + +static ssize_t firmware_direct_read(struct file *filp, struct kobject *kobj, + struct bin_attribute *bin_attr, + char *buffer, loff_t offset, size_t count) +{ + struct device *dev = kobj_to_dev(kobj); + struct firmware_priv *fw_priv = to_firmware_priv(dev); + struct firmware *fw; + ssize_t ret_count; + + if (!fw_priv->fw) + return -ENODEV; + + mutex_lock(&fw_lock); + fw = fw_priv->fw; + + if (offset > fw->size) { + ret_count = 0; + goto out; + } + if (count > fw->size - offset) + count = fw->size - offset; + + if (test_bit(FW_STATUS_DONE, &fw_priv->buf->status)) { + ret_count = -ENODEV; + goto out; + } + + ret_count = __firmware_data_rw(fw_priv, buffer, &offset, count, 1); +out: + mutex_unlock(&fw_lock); + return ret_count; +} + +static ssize_t firmware_direct_write(struct file *filp, struct kobject *kobj, + struct bin_attribute *bin_attr, + char *buffer, loff_t offset, size_t count) +{ + struct device *dev = kobj_to_dev(kobj); + struct firmware_priv *fw_priv = to_firmware_priv(dev); + struct firmware *fw; + ssize_t retval; + + if (!capable(CAP_SYS_RAWIO)) + return -EPERM; + + mutex_lock(&fw_lock); + fw = fw_priv->fw; + if (!fw || !fw_priv->buf || + test_bit(FW_STATUS_DONE, &fw_priv->buf->status)) { + retval = -ENODEV; + goto out; + } + + retval = __firmware_data_rw(fw_priv, buffer, &offset, count, 0); + if (retval < 0) + goto out; + + fw_priv->buf->size = max_t(size_t, offset, fw_priv->buf->size); +out: + mutex_unlock(&fw_lock); + return retval; +} + static ssize_t firmware_data_read(struct file *filp, struct kobject *kobj, struct bin_attribute *bin_attr, char *buffer, loff_t offset, size_t count) @@ -864,6 +1011,13 @@ .write = firmware_data_write, }; +static struct bin_attribute firmware_direct_attr_data = { + .attr = { .name = "data", .mode = 0644 }, + .size = 0, + .read = firmware_direct_read, + .write = firmware_direct_write, +}; + static struct attribute *fw_dev_attrs[] = { &dev_attr_loading.attr, NULL @@ -879,31 +1033,47 @@ .bin_attrs = fw_dev_bin_attrs, }; +static struct bin_attribute *fw_dev_direct_bin_attrs[] = { + &firmware_direct_attr_data, + NULL +}; + +static const struct attribute_group fw_dev_direct_attr_group = { + .attrs = fw_dev_attrs, + .bin_attrs = fw_dev_direct_bin_attrs, +}; + static const struct attribute_group *fw_dev_attr_groups[] = { &fw_dev_attr_group, NULL }; +static const struct attribute_group *fw_dev_direct_attr_groups[] = { + &fw_dev_direct_attr_group, + NULL +}; + static struct firmware_priv * -fw_create_instance(struct firmware *firmware, const char *fw_name, - struct device *device, unsigned int opt_flags) +fw_create_instance(struct firmware *firmware, struct fw_desc *desc) { struct firmware_priv *fw_priv; struct device *f_dev; fw_priv = kzalloc(sizeof(*fw_priv), GFP_KERNEL); if (!fw_priv) { + dev_err(desc->device, "%s: kmalloc failed\n", __func__); fw_priv = ERR_PTR(-ENOMEM); goto exit; } - fw_priv->nowait = !!(opt_flags & FW_OPT_NOWAIT); + fw_priv->nowait = !!(desc->opt_flags & FW_OPT_NOWAIT); fw_priv->fw = firmware; + f_dev = &fw_priv->dev; device_initialize(f_dev); - dev_set_name(f_dev, "%s", fw_name); - f_dev->parent = device; + dev_set_name(f_dev, "%s", desc->name); + f_dev->parent = desc->device; f_dev->class = &firmware_class; f_dev->groups = fw_dev_attr_groups; exit: @@ -919,7 +1089,10 @@ struct firmware_buf *buf = fw_priv->buf; /* fall back on userspace loading */ - buf->is_paged_buf = true; + buf->is_paged_buf = buf->dest_addr ? false : true; + + if (buf->dest_addr) + f_dev->groups = fw_dev_direct_attr_groups; dev_set_uevent_suppress(f_dev, true); @@ -942,7 +1115,7 @@ timeout = MAX_JIFFY_OFFSET; } - timeout = wait_for_completion_interruptible_timeout(&buf->completion, + timeout = wait_for_completion_killable_timeout(&buf->completion, timeout); if (timeout == -ERESTARTSYS || !timeout) { retval = timeout; @@ -955,7 +1128,7 @@ if (is_fw_load_aborted(buf)) retval = -EAGAIN; - else if (!buf->data) + else if (!buf->data && buf->is_paged_buf) retval = -ENOMEM; device_del(f_dev); @@ -965,17 +1138,16 @@ } static int fw_load_from_user_helper(struct firmware *firmware, - const char *name, struct device *device, - unsigned int opt_flags, long timeout) + struct fw_desc *desc, long timeout) { struct firmware_priv *fw_priv; - fw_priv = fw_create_instance(firmware, name, device, opt_flags); + fw_priv = fw_create_instance(firmware, desc); if (IS_ERR(fw_priv)) return PTR_ERR(fw_priv); fw_priv->buf = firmware->priv; - return _request_firmware_load(fw_priv, opt_flags, timeout); + return _request_firmware_load(fw_priv, desc->opt_flags, timeout); } #ifdef CONFIG_PM_SLEEP @@ -996,9 +1168,8 @@ #else /* CONFIG_FW_LOADER_USER_HELPER */ static inline int -fw_load_from_user_helper(struct firmware *firmware, const char *name, - struct device *device, unsigned int opt_flags, - long timeout) +fw_load_from_user_helper(struct firmware *firmware, + struct fw_desc *desc, long timeout) { return -ENOENT; } @@ -1037,8 +1208,7 @@ * or a negative error code */ static int -_request_firmware_prepare(struct firmware **firmware_p, const char *name, - struct device *device) +_request_firmware_prepare(struct firmware **firmware_p, struct fw_desc *desc) { struct firmware *firmware; struct firmware_buf *buf; @@ -1046,17 +1216,31 @@ *firmware_p = firmware = kzalloc(sizeof(*firmware), GFP_KERNEL); if (!firmware) { - dev_err(device, "%s: kmalloc(struct firmware) failed\n", + dev_err(desc->device, "%s: kmalloc(struct firmware) failed\n", __func__); return -ENOMEM; } - if (fw_get_builtin_firmware(firmware, name)) { - dev_dbg(device, "firmware: using built-in firmware %s\n", name); + if (fw_get_builtin_firmware(firmware, desc->name)) { + dev_dbg(desc->device, "firmware: using built-in firmware %s\n", + desc->name); return 0; /* assigned */ } - ret = fw_lookup_and_allocate_buf(name, &fw_cache, &buf); + if (desc->opt_flags & FW_OPT_NOCACHE) { + buf = __allocate_fw_buf(desc->name, NULL); + if (!buf) + return -ENOMEM; + buf->dest_addr = desc->dest_addr; + buf->dest_size = desc->dest_size; + buf->map_fw_mem = desc->map_fw_mem; + buf->unmap_fw_mem = desc->unmap_fw_mem; + buf->map_data = desc->map_data; + firmware->priv = buf; + return 1; + } + + ret = fw_lookup_and_allocate_buf(desc->name, &fw_cache, &buf); /* * bind with 'buf' now to avoid warning in failure path @@ -1095,15 +1279,19 @@ * device may has been deleted already, but the problem * should be fixed in devres or driver core. */ - /* don't cache firmware handled without uevent */ - if (device && (opt_flags & FW_OPT_UEVENT)) + /* don't cache firmware handled without uevent, or when explicitly + * disabled + */ + if (device && (opt_flags & FW_OPT_UEVENT) + && !(opt_flags & FW_OPT_NOCACHE)) fw_add_devm_name(device, buf->fw_id); /* * After caching firmware image is started, let it piggyback * on request firmware. */ - if (buf->fwc->state == FW_LOADER_START_CACHE) { + if (!(opt_flags & FW_OPT_NOCACHE) + && (buf->fwc->state == FW_LOADER_START_CACHE)) { if (fw_cache_piggyback_on_request(buf->fw_id)) kref_get(&buf->ref); } @@ -1115,58 +1303,56 @@ } /* called from request_firmware() and request_firmware_work_func() */ -static int -_request_firmware(const struct firmware **firmware_p, const char *name, - struct device *device, unsigned int opt_flags) +static int _request_firmware(struct fw_desc *desc) { struct firmware *fw; long timeout; int ret; - if (!firmware_p) + if (!desc->firmware_p) return -EINVAL; - if (!name || name[0] == '\0') + if (!desc->name || desc->name[0] == '\0') return -EINVAL; - ret = _request_firmware_prepare(&fw, name, device); + ret = _request_firmware_prepare(&fw, desc); if (ret <= 0) /* error or already assigned */ goto out; ret = 0; timeout = firmware_loading_timeout(); - if (opt_flags & FW_OPT_NOWAIT) { + if (desc->opt_flags & FW_OPT_NOWAIT) { timeout = usermodehelper_read_lock_wait(timeout); if (!timeout) { - dev_dbg(device, "firmware: %s loading timed out\n", - name); + dev_dbg(desc->device, "firmware: %s loading timed out\n", + desc->name); ret = -EBUSY; goto out; } } else { ret = usermodehelper_read_trylock(); if (WARN_ON(ret)) { - dev_err(device, "firmware: %s will not be loaded\n", - name); + dev_err(desc->device, "firmware: %s will not be loaded\n", + desc->name); goto out; } } - ret = fw_get_filesystem_firmware(device, fw->priv); + ret = fw_get_filesystem_firmware(desc->device, fw->priv, + desc->dest_addr, desc->dest_size); if (ret) { - if (!(opt_flags & FW_OPT_NO_WARN)) - dev_warn(device, + if (!(desc->opt_flags & FW_OPT_NO_WARN)) + dev_dbg(desc->device, "Direct firmware load for %s failed with error %d\n", - name, ret); - if (opt_flags & FW_OPT_USERHELPER) { - dev_warn(device, "Falling back to user helper\n"); - ret = fw_load_from_user_helper(fw, name, device, - opt_flags, timeout); + desc->name, ret); + if (desc->opt_flags & FW_OPT_USERHELPER) { + dev_dbg(desc->device, "Falling back to user helper\n"); + ret = fw_load_from_user_helper(fw, desc, timeout); } } if (!ret) - ret = assign_firmware_buf(fw, device, opt_flags); + ret = assign_firmware_buf(fw, desc->device, desc->opt_flags); usermodehelper_read_unlock(); @@ -1176,7 +1362,7 @@ fw = NULL; } - *firmware_p = fw; + *desc->firmware_p = fw; return ret; } @@ -1204,13 +1390,21 @@ request_firmware(const struct firmware **firmware_p, const char *name, struct device *device) { + struct fw_desc desc; int ret; + desc.firmware_p = firmware_p; + desc.name = name; + desc.device = device; + desc.dest_addr = 0; + desc.dest_size = 0; + desc.opt_flags = FW_OPT_UEVENT | FW_OPT_FALLBACK; + /* Need to pin this module until return */ __module_get(THIS_MODULE); - ret = _request_firmware(firmware_p, name, device, - FW_OPT_UEVENT | FW_OPT_FALLBACK); + ret = _request_firmware(&desc); module_put(THIS_MODULE); + return ret; } EXPORT_SYMBOL(request_firmware); @@ -1229,17 +1423,70 @@ int request_firmware_direct(const struct firmware **firmware_p, const char *name, struct device *device) { + struct fw_desc desc; int ret; + desc.firmware_p = firmware_p; + desc.name = name; + desc.device = device; + desc.opt_flags = FW_OPT_UEVENT | FW_OPT_NO_WARN; + + /* Need to pin this module until return */ __module_get(THIS_MODULE); - ret = _request_firmware(firmware_p, name, device, - FW_OPT_UEVENT | FW_OPT_NO_WARN); + ret = _request_firmware(&desc); module_put(THIS_MODULE); + return ret; } EXPORT_SYMBOL_GPL(request_firmware_direct); /** + * request_firmware_into_buf: - send firmware request and wait for it + * @dest_addr: Destination address for the firmware + * @dest_size: Size of destination buffer + * + * Similar to request_firmware, except takes in a buffer address and + * copies firmware data directly to that buffer. Returns the size of + * the firmware that was loaded at dest_addr. This API prevents the + * caching of images. +*/ +int +request_firmware_into_buf(const char *name, struct device *device, + phys_addr_t dest_addr, size_t dest_size, + void * (*map_fw_mem)(phys_addr_t phys, size_t size, + void *data), + void (*unmap_fw_mem)(void *virt, size_t sz, void *data), + void *map_data) +{ + struct fw_desc desc; + const struct firmware *fp = NULL; + int ret; + + if (dest_addr && !map_fw_mem) + return -EINVAL; + if (dest_addr && dest_size <= 0) + return -EINVAL; + + desc.firmware_p = &fp; + desc.name = name; + desc.device = device; + desc.opt_flags = FW_OPT_FALLBACK | FW_OPT_UEVENT | FW_OPT_NOCACHE; + desc.dest_addr = dest_addr; + desc.dest_size = dest_size; + desc.map_fw_mem = map_fw_mem; + desc.unmap_fw_mem = unmap_fw_mem; + desc.map_data = map_data; + + ret = _request_firmware(&desc); + if (ret) + return ret; + ret = fp->size; + release_firmware(fp); + return ret; +} +EXPORT_SYMBOL_GPL(request_firmware_into_buf); + +/** * release_firmware: - release the resource associated with a firmware image * @fw: firmware resource to release **/ @@ -1254,31 +1501,70 @@ EXPORT_SYMBOL(release_firmware); /* Async support */ -struct firmware_work { - struct work_struct work; - struct module *module; - const char *name; - struct device *device; - void *context; - void (*cont)(const struct firmware *fw, void *context); - unsigned int opt_flags; -}; - static void request_firmware_work_func(struct work_struct *work) { - struct firmware_work *fw_work; const struct firmware *fw; + struct fw_desc *desc; + + desc = container_of(work, struct fw_desc, work); + desc->firmware_p = &fw; + _request_firmware(desc); + desc->cont(fw, desc->context); + put_device(desc->device); /* taken in request_firmware_nowait() */ + + module_put(desc->module); + kfree(desc); +} + +int +_request_firmware_nowait( + struct module *module, bool uevent, + const char *name, struct device *device, gfp_t gfp, void *context, + void (*cont)(const struct firmware *fw, void *context), + bool nocache, phys_addr_t dest_addr, size_t dest_size, + void * (*map_fw_mem)(phys_addr_t phys, size_t size, void *data), + void (*unmap_fw_mem)(void *virt, size_t size, void *data), + void *map_data) +{ + struct fw_desc *desc; + + if (dest_addr && !map_fw_mem) + return -EINVAL; + if (dest_addr && dest_size <= 0) + return -EINVAL; + + desc = kzalloc(sizeof(struct fw_desc), gfp); + if (!desc) + return -ENOMEM; + + desc->module = module; + desc->name = name; + desc->device = device; + desc->context = context; + desc->cont = cont; + desc->dest_addr = dest_addr; + desc->dest_size = dest_size; + desc->map_fw_mem = map_fw_mem; + desc->unmap_fw_mem = unmap_fw_mem; + desc->map_data = map_data; + desc->opt_flags = FW_OPT_FALLBACK | FW_OPT_NOWAIT; + + if (uevent) + desc->opt_flags |= FW_OPT_UEVENT; + else + desc->opt_flags |= FW_OPT_USERHELPER; + if (nocache) + desc->opt_flags |= FW_OPT_NOCACHE; - fw_work = container_of(work, struct firmware_work, work); + if (!try_module_get(module)) { + kfree(desc); + return -EFAULT; + } - _request_firmware(&fw, fw_work->name, fw_work->device, - fw_work->opt_flags); - fw_work->cont(fw, fw_work->context); - put_device(fw_work->device); /* taken in request_firmware_nowait() */ - - module_put(fw_work->module); - kfree_const(fw_work->name); - kfree(fw_work); + get_device(desc->device); + INIT_WORK(&desc->work, request_firmware_work_func); + schedule_work(&desc->work); + return 0; } /** @@ -1310,36 +1596,37 @@ const char *name, struct device *device, gfp_t gfp, void *context, void (*cont)(const struct firmware *fw, void *context)) { - struct firmware_work *fw_work; - - fw_work = kzalloc(sizeof(struct firmware_work), gfp); - if (!fw_work) - return -ENOMEM; - - fw_work->module = module; - fw_work->name = kstrdup_const(name, gfp); - if (!fw_work->name) { - kfree(fw_work); - return -ENOMEM; - } - fw_work->device = device; - fw_work->context = context; - fw_work->cont = cont; - fw_work->opt_flags = FW_OPT_NOWAIT | FW_OPT_FALLBACK | - (uevent ? FW_OPT_UEVENT : FW_OPT_USERHELPER); - - if (!try_module_get(module)) { - kfree_const(fw_work->name); - kfree(fw_work); - return -EFAULT; + return _request_firmware_nowait(module, uevent, name, device, gfp, + context, cont, false, 0, 0, NULL, NULL, NULL); } +EXPORT_SYMBOL(request_firmware_nowait); - get_device(fw_work->device); - INIT_WORK(&fw_work->work, request_firmware_work_func); - schedule_work(&fw_work->work); - return 0; +/** + * request_firmware_nowait_into_buf - asynchronous version of request_firmware + * @dest_addr: Destination address for the firmware + * @dest_size: Size of destination buffer + * + * Similar to request_firmware_nowait, except loads the firmware + * directly to a destination address without using an intermediate + * buffer. + * + **/ +int +request_firmware_nowait_into_buf( + struct module *module, bool uevent, + const char *name, struct device *device, gfp_t gfp, void *context, + void (*cont)(const struct firmware *fw, void *context), + phys_addr_t dest_addr, size_t dest_size, + void * (*map_fw_mem)(phys_addr_t phys, size_t size, void *data), + void (*unmap_fw_mem)(void *virt, size_t size, void *data), + void *map_data) +{ + return _request_firmware_nowait(module, uevent, name, device, gfp, + context, cont, true, dest_addr, + dest_size, map_fw_mem, unmap_fw_mem, + map_data); } -EXPORT_SYMBOL(request_firmware_nowait); +EXPORT_SYMBOL_GPL(request_firmware_nowait_into_buf); #ifdef CONFIG_PM_SLEEP static ASYNC_DOMAIN_EXCLUSIVE(fw_cache_domain); diff -ruw linux-4.4.115/drivers/base/Makefile linux-4.4.115-fbx/drivers/base/Makefile --- linux-4.4.115/drivers/base/Makefile 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/base/Makefile 2019-01-22 16:16:22.871240683 +0100 @@ -9,7 +9,7 @@ obj-$(CONFIG_DMA_CMA) += dma-contiguous.o obj-y += power/ obj-$(CONFIG_HAS_DMA) += dma-mapping.o -obj-$(CONFIG_HAVE_GENERIC_DMA_COHERENT) += dma-coherent.o +obj-$(CONFIG_HAVE_GENERIC_DMA_COHERENT) += dma-coherent.o dma-removed.o obj-$(CONFIG_ISA) += isa.o obj-$(CONFIG_FW_LOADER) += firmware_class.o obj-$(CONFIG_NUMA) += node.o diff -ruw linux-4.4.115/drivers/base/platform.c linux-4.4.115-fbx/drivers/base/platform.c --- linux-4.4.115/drivers/base/platform.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/base/platform.c 2019-01-22 16:16:22.875240720 +0100 @@ -117,6 +117,26 @@ EXPORT_SYMBOL_GPL(platform_get_irq); /** + * platform_irq_count - Count the number of IRQs a platform device uses + * @dev: platform device + * + * Return: Number of IRQs a platform device uses or EPROBE_DEFER + */ +int platform_irq_count(struct platform_device *dev) +{ + int ret, nr = 0; + + while ((ret = platform_get_irq(dev, nr)) >= 0) + nr++; + + if (ret == -EPROBE_DEFER) + return ret; + + return nr; +} +EXPORT_SYMBOL_GPL(platform_irq_count); + +/** * platform_get_resource_byname - get a resource for a device by name * @dev: platform device * @type: resource type diff -ruw linux-4.4.115/drivers/base/power/main.c linux-4.4.115-fbx/drivers/base/power/main.c --- linux-4.4.115/drivers/base/power/main.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/base/power/main.c 2019-10-29 09:26:23.413200927 +0100 @@ -33,6 +33,7 @@ #include #include #include +#include #include "../base.h" #include "power.h" @@ -125,6 +126,7 @@ { pr_debug("PM: Adding info for %s:%s\n", dev->bus ? dev->bus->name : "No Bus", dev_name(dev)); + device_pm_check_callbacks(dev); mutex_lock(&dpm_list_mtx); if (dev->parent && dev->parent->power.is_prepared) dev_warn(dev, "parent %s should not be sleeping\n", @@ -147,6 +149,7 @@ mutex_unlock(&dpm_list_mtx); device_wakeup_disable(dev); pm_runtime_remove(dev); + device_pm_check_callbacks(dev); } /** @@ -1348,6 +1351,7 @@ pm_callback_t callback = NULL; char *info = NULL; int error = 0; + char suspend_abort[MAX_SUSPEND_ABORT_LEN]; DECLARE_DPM_WATCHDOG_ON_STACK(wd); TRACE_DEVICE(dev); @@ -1368,6 +1372,9 @@ pm_wakeup_event(dev, 0); if (pm_wakeup_pending()) { + pm_get_active_wakeup_sources(suspend_abort, + MAX_SUSPEND_ABORT_LEN); + log_suspend_abort_reason(suspend_abort); async_error = -EBUSY; goto Complete; } @@ -1570,6 +1577,11 @@ dev->power.wakeup_path = device_may_wakeup(dev); + if (dev->power.no_pm_callbacks) { + ret = 1; /* Let device go direct_complete */ + goto unlock; + } + if (dev->pm_domain) { info = "preparing power domain "; callback = dev->pm_domain->ops.prepare; @@ -1592,6 +1604,7 @@ if (callback) ret = callback(dev); +unlock: device_unlock(dev); if (ret < 0) { @@ -1720,3 +1733,30 @@ device_pm_unlock(); } EXPORT_SYMBOL_GPL(dpm_for_each_dev); + +static bool pm_ops_is_empty(const struct dev_pm_ops *ops) +{ + if (!ops) + return true; + + return !ops->prepare && + !ops->suspend && + !ops->suspend_late && + !ops->suspend_noirq && + !ops->resume_noirq && + !ops->resume_early && + !ops->resume && + !ops->complete; +} + +void device_pm_check_callbacks(struct device *dev) +{ + spin_lock_irq(&dev->power.lock); + dev->power.no_pm_callbacks = + (!dev->bus || pm_ops_is_empty(dev->bus->pm)) && + (!dev->class || pm_ops_is_empty(dev->class->pm)) && + (!dev->type || pm_ops_is_empty(dev->type->pm)) && + (!dev->pm_domain || pm_ops_is_empty(&dev->pm_domain->ops)) && + (!dev->driver || pm_ops_is_empty(dev->driver->pm)); + spin_unlock_irq(&dev->power.lock); +} diff -ruw linux-4.4.115/drivers/base/power/opp/core.c linux-4.4.115-fbx/drivers/base/power/opp/core.c --- linux-4.4.115/drivers/base/power/opp/core.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/base/power/opp/core.c 2019-01-22 16:16:22.879240756 +0100 @@ -13,50 +13,52 @@ #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt +#include #include #include #include #include #include #include +#include #include "opp.h" /* - * The root of the list of all devices. All device_opp structures branch off - * from here, with each device_opp containing the list of opp it supports in + * The root of the list of all opp-tables. All opp_table structures branch off + * from here, with each opp_table containing the list of opps it supports in * various states of availability. */ -static LIST_HEAD(dev_opp_list); +static LIST_HEAD(opp_tables); /* Lock to allow exclusive modification to the device and opp lists */ -DEFINE_MUTEX(dev_opp_list_lock); +DEFINE_MUTEX(opp_table_lock); #define opp_rcu_lockdep_assert() \ do { \ RCU_LOCKDEP_WARN(!rcu_read_lock_held() && \ - !lockdep_is_held(&dev_opp_list_lock), \ + !lockdep_is_held(&opp_table_lock), \ "Missing rcu_read_lock() or " \ - "dev_opp_list_lock protection"); \ + "opp_table_lock protection"); \ } while (0) -static struct device_list_opp *_find_list_dev(const struct device *dev, - struct device_opp *dev_opp) +static struct opp_device *_find_opp_dev(const struct device *dev, + struct opp_table *opp_table) { - struct device_list_opp *list_dev; + struct opp_device *opp_dev; - list_for_each_entry(list_dev, &dev_opp->dev_list, node) - if (list_dev->dev == dev) - return list_dev; + list_for_each_entry(opp_dev, &opp_table->dev_list, node) + if (opp_dev->dev == dev) + return opp_dev; return NULL; } -static struct device_opp *_managed_opp(const struct device_node *np) +static struct opp_table *_managed_opp(const struct device_node *np) { - struct device_opp *dev_opp; + struct opp_table *opp_table; - list_for_each_entry_rcu(dev_opp, &dev_opp_list, node) { - if (dev_opp->np == np) { + list_for_each_entry_rcu(opp_table, &opp_tables, node) { + if (opp_table->np == np) { /* * Multiple devices can point to the same OPP table and * so will have same node-pointer, np. @@ -64,7 +66,7 @@ * But the OPPs will be considered as shared only if the * OPP table contains a "opp-shared" property. */ - return dev_opp->shared_opp ? dev_opp : NULL; + return opp_table->shared_opp ? opp_table : NULL; } } @@ -72,24 +74,24 @@ } /** - * _find_device_opp() - find device_opp struct using device pointer - * @dev: device pointer used to lookup device OPPs + * _find_opp_table() - find opp_table struct using device pointer + * @dev: device pointer used to lookup OPP table * - * Search list of device OPPs for one containing matching device. Does a RCU - * reader operation to grab the pointer needed. + * Search OPP table for one containing matching device. Does a RCU reader + * operation to grab the pointer needed. * - * Return: pointer to 'struct device_opp' if found, otherwise -ENODEV or + * Return: pointer to 'struct opp_table' if found, otherwise -ENODEV or * -EINVAL based on type of error. * * Locking: For readers, this function must be called under rcu_read_lock(). - * device_opp is a RCU protected pointer, which means that device_opp is valid + * opp_table is a RCU protected pointer, which means that opp_table is valid * as long as we are under RCU lock. * - * For Writers, this function must be called with dev_opp_list_lock held. + * For Writers, this function must be called with opp_table_lock held. */ -struct device_opp *_find_device_opp(struct device *dev) +struct opp_table *_find_opp_table(struct device *dev) { - struct device_opp *dev_opp; + struct opp_table *opp_table; opp_rcu_lockdep_assert(); @@ -98,9 +100,9 @@ return ERR_PTR(-EINVAL); } - list_for_each_entry_rcu(dev_opp, &dev_opp_list, node) - if (_find_list_dev(dev, dev_opp)) - return dev_opp; + list_for_each_entry_rcu(opp_table, &opp_tables, node) + if (_find_opp_dev(dev, opp_table)) + return opp_table; return ERR_PTR(-ENODEV); } @@ -213,16 +215,16 @@ */ unsigned long dev_pm_opp_get_max_clock_latency(struct device *dev) { - struct device_opp *dev_opp; + struct opp_table *opp_table; unsigned long clock_latency_ns; rcu_read_lock(); - dev_opp = _find_device_opp(dev); - if (IS_ERR(dev_opp)) + opp_table = _find_opp_table(dev); + if (IS_ERR(opp_table)) clock_latency_ns = 0; else - clock_latency_ns = dev_opp->clock_latency_ns_max; + clock_latency_ns = opp_table->clock_latency_ns_max; rcu_read_unlock(); return clock_latency_ns; @@ -230,6 +232,82 @@ EXPORT_SYMBOL_GPL(dev_pm_opp_get_max_clock_latency); /** + * dev_pm_opp_get_max_volt_latency() - Get max voltage latency in nanoseconds + * @dev: device for which we do this operation + * + * Return: This function returns the max voltage latency in nanoseconds. + * + * Locking: This function takes rcu_read_lock(). + */ +unsigned long dev_pm_opp_get_max_volt_latency(struct device *dev) +{ + struct opp_table *opp_table; + struct dev_pm_opp *opp; + struct regulator *reg; + unsigned long latency_ns = 0; + unsigned long min_uV = ~0, max_uV = 0; + int ret; + + rcu_read_lock(); + + opp_table = _find_opp_table(dev); + if (IS_ERR(opp_table)) { + rcu_read_unlock(); + return 0; + } + + reg = opp_table->regulator; + if (IS_ERR(reg)) { + /* Regulator may not be required for device */ + if (reg) + dev_err(dev, "%s: Invalid regulator (%ld)\n", __func__, + PTR_ERR(reg)); + rcu_read_unlock(); + return 0; + } + + list_for_each_entry_rcu(opp, &opp_table->opp_list, node) { + if (!opp->available) + continue; + + if (opp->u_volt_min < min_uV) + min_uV = opp->u_volt_min; + if (opp->u_volt_max > max_uV) + max_uV = opp->u_volt_max; + } + + rcu_read_unlock(); + + /* + * The caller needs to ensure that opp_table (and hence the regulator) + * isn't freed, while we are executing this routine. + */ + ret = regulator_set_voltage_time(reg, min_uV, max_uV); + if (ret > 0) + latency_ns = ret * 1000; + + return latency_ns; +} +EXPORT_SYMBOL_GPL(dev_pm_opp_get_max_volt_latency); + +/** + * dev_pm_opp_get_max_transition_latency() - Get max transition latency in + * nanoseconds + * @dev: device for which we do this operation + * + * Return: This function returns the max transition latency, in nanoseconds, to + * switch from one OPP to other. + * + * Locking: This function takes rcu_read_lock(). + */ +unsigned long dev_pm_opp_get_max_transition_latency(struct device *dev) +{ + return dev_pm_opp_get_max_volt_latency(dev) + + dev_pm_opp_get_max_clock_latency(dev); +} +EXPORT_SYMBOL_GPL(dev_pm_opp_get_max_transition_latency); + +/** * dev_pm_opp_get_suspend_opp() - Get suspend opp * @dev: device for which we do this operation * @@ -244,21 +322,21 @@ */ struct dev_pm_opp *dev_pm_opp_get_suspend_opp(struct device *dev) { - struct device_opp *dev_opp; + struct opp_table *opp_table; opp_rcu_lockdep_assert(); - dev_opp = _find_device_opp(dev); - if (IS_ERR(dev_opp) || !dev_opp->suspend_opp || - !dev_opp->suspend_opp->available) + opp_table = _find_opp_table(dev); + if (IS_ERR(opp_table) || !opp_table->suspend_opp || + !opp_table->suspend_opp->available) return NULL; - return dev_opp->suspend_opp; + return opp_table->suspend_opp; } EXPORT_SYMBOL_GPL(dev_pm_opp_get_suspend_opp); /** - * dev_pm_opp_get_opp_count() - Get number of opps available in the opp list + * dev_pm_opp_get_opp_count() - Get number of opps available in the opp table * @dev: device for which we do this operation * * Return: This function returns the number of available opps if there are any, @@ -268,21 +346,21 @@ */ int dev_pm_opp_get_opp_count(struct device *dev) { - struct device_opp *dev_opp; + struct opp_table *opp_table; struct dev_pm_opp *temp_opp; int count = 0; rcu_read_lock(); - dev_opp = _find_device_opp(dev); - if (IS_ERR(dev_opp)) { - count = PTR_ERR(dev_opp); - dev_err(dev, "%s: device OPP not found (%d)\n", + opp_table = _find_opp_table(dev); + if (IS_ERR(opp_table)) { + count = PTR_ERR(opp_table); + dev_err(dev, "%s: OPP table not found (%d)\n", __func__, count); goto out_unlock; } - list_for_each_entry_rcu(temp_opp, &dev_opp->opp_list, node) { + list_for_each_entry_rcu(temp_opp, &opp_table->opp_list, node) { if (temp_opp->available) count++; } @@ -299,7 +377,7 @@ * @freq: frequency to search for * @available: true/false - match for available opp * - * Return: Searches for exact match in the opp list and returns pointer to the + * Return: Searches for exact match in the opp table and returns pointer to the * matching opp if found, else returns ERR_PTR in case of error and should * be handled using IS_ERR. Error return values can be: * EINVAL: for bad pointer @@ -323,19 +401,20 @@ unsigned long freq, bool available) { - struct device_opp *dev_opp; + struct opp_table *opp_table; struct dev_pm_opp *temp_opp, *opp = ERR_PTR(-ERANGE); opp_rcu_lockdep_assert(); - dev_opp = _find_device_opp(dev); - if (IS_ERR(dev_opp)) { - int r = PTR_ERR(dev_opp); - dev_err(dev, "%s: device OPP not found (%d)\n", __func__, r); + opp_table = _find_opp_table(dev); + if (IS_ERR(opp_table)) { + int r = PTR_ERR(opp_table); + + dev_err(dev, "%s: OPP table not found (%d)\n", __func__, r); return ERR_PTR(r); } - list_for_each_entry_rcu(temp_opp, &dev_opp->opp_list, node) { + list_for_each_entry_rcu(temp_opp, &opp_table->opp_list, node) { if (temp_opp->available == available && temp_opp->rate == freq) { opp = temp_opp; @@ -371,7 +450,7 @@ struct dev_pm_opp *dev_pm_opp_find_freq_ceil(struct device *dev, unsigned long *freq) { - struct device_opp *dev_opp; + struct opp_table *opp_table; struct dev_pm_opp *temp_opp, *opp = ERR_PTR(-ERANGE); opp_rcu_lockdep_assert(); @@ -381,11 +460,11 @@ return ERR_PTR(-EINVAL); } - dev_opp = _find_device_opp(dev); - if (IS_ERR(dev_opp)) - return ERR_CAST(dev_opp); + opp_table = _find_opp_table(dev); + if (IS_ERR(opp_table)) + return ERR_CAST(opp_table); - list_for_each_entry_rcu(temp_opp, &dev_opp->opp_list, node) { + list_for_each_entry_rcu(temp_opp, &opp_table->opp_list, node) { if (temp_opp->available && temp_opp->rate >= *freq) { opp = temp_opp; *freq = opp->rate; @@ -421,7 +500,7 @@ struct dev_pm_opp *dev_pm_opp_find_freq_floor(struct device *dev, unsigned long *freq) { - struct device_opp *dev_opp; + struct opp_table *opp_table; struct dev_pm_opp *temp_opp, *opp = ERR_PTR(-ERANGE); opp_rcu_lockdep_assert(); @@ -431,11 +510,11 @@ return ERR_PTR(-EINVAL); } - dev_opp = _find_device_opp(dev); - if (IS_ERR(dev_opp)) - return ERR_CAST(dev_opp); + opp_table = _find_opp_table(dev); + if (IS_ERR(opp_table)) + return ERR_CAST(opp_table); - list_for_each_entry_rcu(temp_opp, &dev_opp->opp_list, node) { + list_for_each_entry_rcu(temp_opp, &opp_table->opp_list, node) { if (temp_opp->available) { /* go to the next node, before choosing prev */ if (temp_opp->rate > *freq) @@ -451,116 +530,343 @@ } EXPORT_SYMBOL_GPL(dev_pm_opp_find_freq_floor); -/* List-dev Helpers */ -static void _kfree_list_dev_rcu(struct rcu_head *head) +/* + * The caller needs to ensure that opp_table (and hence the clk) isn't freed, + * while clk returned here is used. + */ +static struct clk *_get_opp_clk(struct device *dev) { - struct device_list_opp *list_dev; + struct opp_table *opp_table; + struct clk *clk; - list_dev = container_of(head, struct device_list_opp, rcu_head); - kfree_rcu(list_dev, rcu_head); + rcu_read_lock(); + + opp_table = _find_opp_table(dev); + if (IS_ERR(opp_table)) { + dev_err(dev, "%s: device opp doesn't exist\n", __func__); + clk = ERR_CAST(opp_table); + goto unlock; } -static void _remove_list_dev(struct device_list_opp *list_dev, - struct device_opp *dev_opp) + clk = opp_table->clk; + if (IS_ERR(clk)) + dev_err(dev, "%s: No clock available for the device\n", + __func__); + +unlock: + rcu_read_unlock(); + return clk; +} + +static int _set_opp_voltage(struct device *dev, struct regulator *reg, + unsigned long u_volt, unsigned long u_volt_min, + unsigned long u_volt_max) { - list_del(&list_dev->node); - call_srcu(&dev_opp->srcu_head.srcu, &list_dev->rcu_head, - _kfree_list_dev_rcu); + int ret; + + /* Regulator not available for device */ + if (IS_ERR(reg)) { + dev_dbg(dev, "%s: regulator not available: %ld\n", __func__, + PTR_ERR(reg)); + return 0; } -struct device_list_opp *_add_list_dev(const struct device *dev, - struct device_opp *dev_opp) + dev_dbg(dev, "%s: voltages (mV): %lu %lu %lu\n", __func__, u_volt_min, + u_volt, u_volt_max); + + ret = regulator_set_voltage_triplet(reg, u_volt_min, u_volt, + u_volt_max); + if (ret) + dev_err(dev, "%s: failed to set voltage (%lu %lu %lu mV): %d\n", + __func__, u_volt_min, u_volt, u_volt_max, ret); + + return ret; +} + +/** + * dev_pm_opp_set_rate() - Configure new OPP based on frequency + * @dev: device for which we do this operation + * @target_freq: frequency to achieve + * + * This configures the power-supplies and clock source to the levels specified + * by the OPP corresponding to the target_freq. + * + * Locking: This function takes rcu_read_lock(). + */ +int dev_pm_opp_set_rate(struct device *dev, unsigned long target_freq) { - struct device_list_opp *list_dev; + struct opp_table *opp_table; + struct dev_pm_opp *old_opp, *opp; + struct regulator *reg; + struct clk *clk; + unsigned long freq, old_freq; + unsigned long u_volt, u_volt_min, u_volt_max; + unsigned long ou_volt, ou_volt_min, ou_volt_max; + int ret; + + if (unlikely(!target_freq)) { + dev_err(dev, "%s: Invalid target frequency %lu\n", __func__, + target_freq); + return -EINVAL; + } - list_dev = kzalloc(sizeof(*list_dev), GFP_KERNEL); - if (!list_dev) + clk = _get_opp_clk(dev); + if (IS_ERR(clk)) + return PTR_ERR(clk); + + freq = clk_round_rate(clk, target_freq); + if ((long)freq <= 0) + freq = target_freq; + + old_freq = clk_get_rate(clk); + + /* Return early if nothing to do */ + if (old_freq == freq) { + dev_dbg(dev, "%s: old/new frequencies (%lu Hz) are same, nothing to do\n", + __func__, freq); + return 0; + } + + rcu_read_lock(); + + opp_table = _find_opp_table(dev); + if (IS_ERR(opp_table)) { + dev_err(dev, "%s: device opp doesn't exist\n", __func__); + rcu_read_unlock(); + return PTR_ERR(opp_table); + } + + old_opp = dev_pm_opp_find_freq_ceil(dev, &old_freq); + if (!IS_ERR(old_opp)) { + ou_volt = old_opp->u_volt; + ou_volt_min = old_opp->u_volt_min; + ou_volt_max = old_opp->u_volt_max; + } else { + dev_err(dev, "%s: failed to find current OPP for freq %lu (%ld)\n", + __func__, old_freq, PTR_ERR(old_opp)); + } + + opp = dev_pm_opp_find_freq_ceil(dev, &freq); + if (IS_ERR(opp)) { + ret = PTR_ERR(opp); + dev_err(dev, "%s: failed to find OPP for freq %lu (%d)\n", + __func__, freq, ret); + rcu_read_unlock(); + return ret; + } + + u_volt = opp->u_volt; + u_volt_min = opp->u_volt_min; + u_volt_max = opp->u_volt_max; + + reg = opp_table->regulator; + + rcu_read_unlock(); + + /* Scaling up? Scale voltage before frequency */ + if (freq > old_freq) { + ret = _set_opp_voltage(dev, reg, u_volt, u_volt_min, + u_volt_max); + if (ret) + goto restore_voltage; + } + + /* Change frequency */ + + dev_dbg(dev, "%s: switching OPP: %lu Hz --> %lu Hz\n", + __func__, old_freq, freq); + + ret = clk_set_rate(clk, freq); + if (ret) { + dev_err(dev, "%s: failed to set clock rate: %d\n", __func__, + ret); + goto restore_voltage; + } + + /* Scaling down? Scale voltage after frequency */ + if (freq < old_freq) { + ret = _set_opp_voltage(dev, reg, u_volt, u_volt_min, + u_volt_max); + if (ret) + goto restore_freq; + } + + return 0; + +restore_freq: + if (clk_set_rate(clk, old_freq)) + dev_err(dev, "%s: failed to restore old-freq (%lu Hz)\n", + __func__, old_freq); +restore_voltage: + /* This shouldn't harm even if the voltages weren't updated earlier */ + if (!IS_ERR(old_opp)) + _set_opp_voltage(dev, reg, ou_volt, ou_volt_min, ou_volt_max); + + return ret; +} +EXPORT_SYMBOL_GPL(dev_pm_opp_set_rate); + +/* OPP-dev Helpers */ +static void _kfree_opp_dev_rcu(struct rcu_head *head) +{ + struct opp_device *opp_dev; + + opp_dev = container_of(head, struct opp_device, rcu_head); + kfree_rcu(opp_dev, rcu_head); +} + +static void _remove_opp_dev(struct opp_device *opp_dev, + struct opp_table *opp_table) +{ + opp_debug_unregister(opp_dev, opp_table); + list_del(&opp_dev->node); + call_srcu(&opp_table->srcu_head.srcu, &opp_dev->rcu_head, + _kfree_opp_dev_rcu); +} + +struct opp_device *_add_opp_dev(const struct device *dev, + struct opp_table *opp_table) +{ + struct opp_device *opp_dev; + int ret; + + opp_dev = kzalloc(sizeof(*opp_dev), GFP_KERNEL); + if (!opp_dev) return NULL; - /* Initialize list-dev */ - list_dev->dev = dev; - list_add_rcu(&list_dev->node, &dev_opp->dev_list); + /* Initialize opp-dev */ + opp_dev->dev = dev; + list_add_rcu(&opp_dev->node, &opp_table->dev_list); - return list_dev; + /* Create debugfs entries for the opp_table */ + ret = opp_debug_register(opp_dev, opp_table); + if (ret) + dev_err(dev, "%s: Failed to register opp debugfs (%d)\n", + __func__, ret); + + return opp_dev; } /** - * _add_device_opp() - Find device OPP table or allocate a new one + * _add_opp_table() - Find OPP table or allocate a new one * @dev: device for which we do this operation * * It tries to find an existing table first, if it couldn't find one, it * allocates a new OPP table and returns that. * - * Return: valid device_opp pointer if success, else NULL. + * Return: valid opp_table pointer if success, else NULL. */ -static struct device_opp *_add_device_opp(struct device *dev) +static struct opp_table *_add_opp_table(struct device *dev) { - struct device_opp *dev_opp; - struct device_list_opp *list_dev; + struct opp_table *opp_table; + struct opp_device *opp_dev; + struct device_node *np; + int ret; - /* Check for existing list for 'dev' first */ - dev_opp = _find_device_opp(dev); - if (!IS_ERR(dev_opp)) - return dev_opp; + /* Check for existing table for 'dev' first */ + opp_table = _find_opp_table(dev); + if (!IS_ERR(opp_table)) + return opp_table; /* - * Allocate a new device OPP table. In the infrequent case where a new + * Allocate a new OPP table. In the infrequent case where a new * device is needed to be added, we pay this penalty. */ - dev_opp = kzalloc(sizeof(*dev_opp), GFP_KERNEL); - if (!dev_opp) + opp_table = kzalloc(sizeof(*opp_table), GFP_KERNEL); + if (!opp_table) return NULL; - INIT_LIST_HEAD(&dev_opp->dev_list); + INIT_LIST_HEAD(&opp_table->dev_list); - list_dev = _add_list_dev(dev, dev_opp); - if (!list_dev) { - kfree(dev_opp); + opp_dev = _add_opp_dev(dev, opp_table); + if (!opp_dev) { + kfree(opp_table); return NULL; } - srcu_init_notifier_head(&dev_opp->srcu_head); - INIT_LIST_HEAD(&dev_opp->opp_list); + /* + * Only required for backward compatibility with v1 bindings, but isn't + * harmful for other cases. And so we do it unconditionally. + */ + np = of_node_get(dev->of_node); + if (np) { + u32 val; + + if (!of_property_read_u32(np, "clock-latency", &val)) + opp_table->clock_latency_ns_max = val; + of_property_read_u32(np, "voltage-tolerance", + &opp_table->voltage_tolerance_v1); + of_node_put(np); + } + + /* Set regulator to a non-NULL error value */ + opp_table->regulator = ERR_PTR(-ENXIO); - /* Secure the device list modification */ - list_add_rcu(&dev_opp->node, &dev_opp_list); - return dev_opp; + /* Find clk for the device */ + opp_table->clk = clk_get(dev, NULL); + if (IS_ERR(opp_table->clk)) { + ret = PTR_ERR(opp_table->clk); + if (ret != -EPROBE_DEFER) + dev_dbg(dev, "%s: Couldn't find clock: %d\n", __func__, + ret); + } + + srcu_init_notifier_head(&opp_table->srcu_head); + INIT_LIST_HEAD(&opp_table->opp_list); + + /* Secure the device table modification */ + list_add_rcu(&opp_table->node, &opp_tables); + return opp_table; } /** - * _kfree_device_rcu() - Free device_opp RCU handler + * _kfree_device_rcu() - Free opp_table RCU handler * @head: RCU head */ static void _kfree_device_rcu(struct rcu_head *head) { - struct device_opp *device_opp = container_of(head, struct device_opp, rcu_head); + struct opp_table *opp_table = container_of(head, struct opp_table, + rcu_head); - kfree_rcu(device_opp, rcu_head); + kfree_rcu(opp_table, rcu_head); } /** - * _remove_device_opp() - Removes a device OPP table - * @dev_opp: device OPP table to be removed. + * _remove_opp_table() - Removes a OPP table + * @opp_table: OPP table to be removed. * - * Removes/frees device OPP table it it doesn't contain any OPPs. + * Removes/frees OPP table if it doesn't contain any OPPs. */ -static void _remove_device_opp(struct device_opp *dev_opp) +static void _remove_opp_table(struct opp_table *opp_table) { - struct device_list_opp *list_dev; + struct opp_device *opp_dev; + + if (!list_empty(&opp_table->opp_list)) + return; + + if (opp_table->supported_hw) + return; - if (!list_empty(&dev_opp->opp_list)) + if (opp_table->prop_name) return; - list_dev = list_first_entry(&dev_opp->dev_list, struct device_list_opp, + if (!IS_ERR(opp_table->regulator)) + return; + + /* Release clk */ + if (!IS_ERR(opp_table->clk)) + clk_put(opp_table->clk); + + opp_dev = list_first_entry(&opp_table->dev_list, struct opp_device, node); - _remove_list_dev(list_dev, dev_opp); + _remove_opp_dev(opp_dev, opp_table); /* dev_list must be empty now */ - WARN_ON(!list_empty(&dev_opp->dev_list)); + WARN_ON(!list_empty(&opp_table->dev_list)); - list_del_rcu(&dev_opp->node); - call_srcu(&dev_opp->srcu_head.srcu, &dev_opp->rcu_head, + list_del_rcu(&opp_table->node); + call_srcu(&opp_table->srcu_head.srcu, &opp_table->rcu_head, _kfree_device_rcu); } @@ -577,17 +883,17 @@ /** * _opp_remove() - Remove an OPP from a table definition - * @dev_opp: points back to the device_opp struct this opp belongs to + * @opp_table: points back to the opp_table struct this opp belongs to * @opp: pointer to the OPP to remove * @notify: OPP_EVENT_REMOVE notification should be sent or not * - * This function removes an opp definition from the opp list. + * This function removes an opp definition from the opp table. * - * Locking: The internal device_opp and opp structures are RCU protected. + * Locking: The internal opp_table and opp structures are RCU protected. * It is assumed that the caller holds required mutex for an RCU updater * strategy. */ -static void _opp_remove(struct device_opp *dev_opp, +static void _opp_remove(struct opp_table *opp_table, struct dev_pm_opp *opp, bool notify) { /* @@ -595,21 +901,23 @@ * frequency/voltage list. */ if (notify) - srcu_notifier_call_chain(&dev_opp->srcu_head, OPP_EVENT_REMOVE, opp); + srcu_notifier_call_chain(&opp_table->srcu_head, + OPP_EVENT_REMOVE, opp); + opp_debug_remove_one(opp); list_del_rcu(&opp->node); - call_srcu(&dev_opp->srcu_head.srcu, &opp->rcu_head, _kfree_opp_rcu); + call_srcu(&opp_table->srcu_head.srcu, &opp->rcu_head, _kfree_opp_rcu); - _remove_device_opp(dev_opp); + _remove_opp_table(opp_table); } /** - * dev_pm_opp_remove() - Remove an OPP from OPP list + * dev_pm_opp_remove() - Remove an OPP from OPP table * @dev: device for which we do this operation * @freq: OPP to remove with matching 'freq' * - * This function removes an opp from the opp list. + * This function removes an opp from the opp table. * - * Locking: The internal device_opp and opp structures are RCU protected. + * Locking: The internal opp_table and opp structures are RCU protected. * Hence this function internally uses RCU updater strategy with mutex locks * to keep the integrity of the internal data structures. Callers should ensure * that this function is *NOT* called under RCU protection or in contexts where @@ -618,17 +926,17 @@ void dev_pm_opp_remove(struct device *dev, unsigned long freq) { struct dev_pm_opp *opp; - struct device_opp *dev_opp; + struct opp_table *opp_table; bool found = false; - /* Hold our list modification lock here */ - mutex_lock(&dev_opp_list_lock); + /* Hold our table modification lock here */ + mutex_lock(&opp_table_lock); - dev_opp = _find_device_opp(dev); - if (IS_ERR(dev_opp)) + opp_table = _find_opp_table(dev); + if (IS_ERR(opp_table)) goto unlock; - list_for_each_entry(opp, &dev_opp->opp_list, node) { + list_for_each_entry(opp, &opp_table->opp_list, node) { if (opp->rate == freq) { found = true; break; @@ -641,14 +949,14 @@ goto unlock; } - _opp_remove(dev_opp, opp, true); + _opp_remove(opp_table, opp, true); unlock: - mutex_unlock(&dev_opp_list_lock); + mutex_unlock(&opp_table_lock); } EXPORT_SYMBOL_GPL(dev_pm_opp_remove); static struct dev_pm_opp *_allocate_opp(struct device *dev, - struct device_opp **dev_opp) + struct opp_table **opp_table) { struct dev_pm_opp *opp; @@ -659,8 +967,8 @@ INIT_LIST_HEAD(&opp->node); - *dev_opp = _add_device_opp(dev); - if (!*dev_opp) { + *opp_table = _add_opp_table(dev); + if (!*opp_table) { kfree(opp); return NULL; } @@ -668,21 +976,38 @@ return opp; } +static bool _opp_supported_by_regulators(struct dev_pm_opp *opp, + struct opp_table *opp_table) +{ + struct regulator *reg = opp_table->regulator; + + if (!IS_ERR(reg) && + !regulator_is_supported_voltage(reg, opp->u_volt_min, + opp->u_volt_max)) { + pr_warn("%s: OPP minuV: %lu maxuV: %lu, not supported by regulator\n", + __func__, opp->u_volt_min, opp->u_volt_max); + return false; + } + + return true; +} + static int _opp_add(struct device *dev, struct dev_pm_opp *new_opp, - struct device_opp *dev_opp) + struct opp_table *opp_table) { struct dev_pm_opp *opp; - struct list_head *head = &dev_opp->opp_list; + struct list_head *head = &opp_table->opp_list; + int ret; /* * Insert new OPP in order of increasing frequency and discard if * already present. * - * Need to use &dev_opp->opp_list in the condition part of the 'for' + * Need to use &opp_table->opp_list in the condition part of the 'for' * loop, don't replace it with head otherwise it will become an infinite * loop. */ - list_for_each_entry_rcu(opp, &dev_opp->opp_list, node) { + list_for_each_entry_rcu(opp, &opp_table->opp_list, node) { if (new_opp->rate > opp->rate) { head = &opp->node; continue; @@ -700,9 +1025,20 @@ 0 : -EEXIST; } - new_opp->dev_opp = dev_opp; + new_opp->opp_table = opp_table; list_add_rcu(&new_opp->node, head); + ret = opp_debug_create_one(new_opp, opp_table); + if (ret) + dev_err(dev, "%s: Failed to register opp to debugfs (%d)\n", + __func__, ret); + + if (!_opp_supported_by_regulators(new_opp, opp_table)) { + new_opp->available = false; + dev_warn(dev, "%s: OPP not supported by regulators (%lu)\n", + __func__, new_opp->rate); + } + return 0; } @@ -713,14 +1049,14 @@ * @u_volt: Voltage in uVolts for this OPP * @dynamic: Dynamically added OPPs. * - * This function adds an opp definition to the opp list and returns status. + * This function adds an opp definition to the opp table and returns status. * The opp is made available by default and it can be controlled using * dev_pm_opp_enable/disable functions and may be removed by dev_pm_opp_remove. * * NOTE: "dynamic" parameter impacts OPPs added by the dev_pm_opp_of_add_table * and freed by dev_pm_opp_of_remove_table. * - * Locking: The internal device_opp and opp structures are RCU protected. + * Locking: The internal opp_table and opp structures are RCU protected. * Hence this function internally uses RCU updater strategy with mutex locks * to keep the integrity of the internal data structures. Callers should ensure * that this function is *NOT* called under RCU protection or in contexts where @@ -736,14 +1072,15 @@ static int _opp_add_v1(struct device *dev, unsigned long freq, long u_volt, bool dynamic) { - struct device_opp *dev_opp; + struct opp_table *opp_table; struct dev_pm_opp *new_opp; + unsigned long tol; int ret; - /* Hold our list modification lock here */ - mutex_lock(&dev_opp_list_lock); + /* Hold our table modification lock here */ + mutex_lock(&opp_table_lock); - new_opp = _allocate_opp(dev, &dev_opp); + new_opp = _allocate_opp(dev, &opp_table); if (!new_opp) { ret = -ENOMEM; goto unlock; @@ -751,60 +1088,77 @@ /* populate the opp table */ new_opp->rate = freq; + tol = u_volt * opp_table->voltage_tolerance_v1 / 100; new_opp->u_volt = u_volt; + new_opp->u_volt_min = u_volt - tol; + new_opp->u_volt_max = u_volt + tol; new_opp->available = true; new_opp->dynamic = dynamic; - ret = _opp_add(dev, new_opp, dev_opp); + ret = _opp_add(dev, new_opp, opp_table); if (ret) goto free_opp; - mutex_unlock(&dev_opp_list_lock); + mutex_unlock(&opp_table_lock); /* * Notify the changes in the availability of the operable * frequency/voltage list. */ - srcu_notifier_call_chain(&dev_opp->srcu_head, OPP_EVENT_ADD, new_opp); + srcu_notifier_call_chain(&opp_table->srcu_head, OPP_EVENT_ADD, new_opp); return 0; free_opp: - _opp_remove(dev_opp, new_opp, false); + _opp_remove(opp_table, new_opp, false); unlock: - mutex_unlock(&dev_opp_list_lock); + mutex_unlock(&opp_table_lock); return ret; } /* TODO: Support multiple regulators */ -static int opp_parse_supplies(struct dev_pm_opp *opp, struct device *dev) +static int opp_parse_supplies(struct dev_pm_opp *opp, struct device *dev, + struct opp_table *opp_table) { u32 microvolt[3] = {0}; u32 val; int count, ret; + struct property *prop = NULL; + char name[NAME_MAX]; + + /* Search for "opp-microvolt-" */ + if (opp_table->prop_name) { + snprintf(name, sizeof(name), "opp-microvolt-%s", + opp_table->prop_name); + prop = of_find_property(opp->np, name, NULL); + } + + if (!prop) { + /* Search for "opp-microvolt" */ + sprintf(name, "opp-microvolt"); + prop = of_find_property(opp->np, name, NULL); /* Missing property isn't a problem, but an invalid entry is */ - if (!of_find_property(opp->np, "opp-microvolt", NULL)) + if (!prop) return 0; + } - count = of_property_count_u32_elems(opp->np, "opp-microvolt"); + count = of_property_count_u32_elems(opp->np, name); if (count < 0) { - dev_err(dev, "%s: Invalid opp-microvolt property (%d)\n", - __func__, count); + dev_err(dev, "%s: Invalid %s property (%d)\n", + __func__, name, count); return count; } /* There can be one or three elements here */ if (count != 1 && count != 3) { - dev_err(dev, "%s: Invalid number of elements in opp-microvolt property (%d)\n", - __func__, count); + dev_err(dev, "%s: Invalid number of elements in %s property (%d)\n", + __func__, name, count); return -EINVAL; } - ret = of_property_read_u32_array(opp->np, "opp-microvolt", microvolt, - count); + ret = of_property_read_u32_array(opp->np, name, microvolt, count); if (ret) { - dev_err(dev, "%s: error parsing opp-microvolt: %d\n", __func__, - ret); + dev_err(dev, "%s: error parsing %s: %d\n", __func__, name, ret); return -EINVAL; } @@ -818,22 +1172,391 @@ opp->u_volt_max = microvolt[2]; } - if (!of_property_read_u32(opp->np, "opp-microamp", &val)) + /* Search for "opp-microamp-" */ + prop = NULL; + if (opp_table->prop_name) { + snprintf(name, sizeof(name), "opp-microamp-%s", + opp_table->prop_name); + prop = of_find_property(opp->np, name, NULL); + } + + if (!prop) { + /* Search for "opp-microamp" */ + sprintf(name, "opp-microamp"); + prop = of_find_property(opp->np, name, NULL); + } + + if (prop && !of_property_read_u32(opp->np, name, &val)) opp->u_amp = val; return 0; } /** + * dev_pm_opp_set_supported_hw() - Set supported platforms + * @dev: Device for which supported-hw has to be set. + * @versions: Array of hierarchy of versions to match. + * @count: Number of elements in the array. + * + * This is required only for the V2 bindings, and it enables a platform to + * specify the hierarchy of versions it supports. OPP layer will then enable + * OPPs, which are available for those versions, based on its 'opp-supported-hw' + * property. + * + * Locking: The internal opp_table and opp structures are RCU protected. + * Hence this function internally uses RCU updater strategy with mutex locks + * to keep the integrity of the internal data structures. Callers should ensure + * that this function is *NOT* called under RCU protection or in contexts where + * mutex cannot be locked. + */ +int dev_pm_opp_set_supported_hw(struct device *dev, const u32 *versions, + unsigned int count) +{ + struct opp_table *opp_table; + int ret = 0; + + /* Hold our table modification lock here */ + mutex_lock(&opp_table_lock); + + opp_table = _add_opp_table(dev); + if (!opp_table) { + ret = -ENOMEM; + goto unlock; + } + + /* Make sure there are no concurrent readers while updating opp_table */ + WARN_ON(!list_empty(&opp_table->opp_list)); + + /* Do we already have a version hierarchy associated with opp_table? */ + if (opp_table->supported_hw) { + dev_err(dev, "%s: Already have supported hardware list\n", + __func__); + ret = -EBUSY; + goto err; + } + + opp_table->supported_hw = kmemdup(versions, count * sizeof(*versions), + GFP_KERNEL); + if (!opp_table->supported_hw) { + ret = -ENOMEM; + goto err; + } + + opp_table->supported_hw_count = count; + mutex_unlock(&opp_table_lock); + return 0; + +err: + _remove_opp_table(opp_table); +unlock: + mutex_unlock(&opp_table_lock); + + return ret; +} +EXPORT_SYMBOL_GPL(dev_pm_opp_set_supported_hw); + +/** + * dev_pm_opp_put_supported_hw() - Releases resources blocked for supported hw + * @dev: Device for which supported-hw has to be put. + * + * This is required only for the V2 bindings, and is called for a matching + * dev_pm_opp_set_supported_hw(). Until this is called, the opp_table structure + * will not be freed. + * + * Locking: The internal opp_table and opp structures are RCU protected. + * Hence this function internally uses RCU updater strategy with mutex locks + * to keep the integrity of the internal data structures. Callers should ensure + * that this function is *NOT* called under RCU protection or in contexts where + * mutex cannot be locked. + */ +void dev_pm_opp_put_supported_hw(struct device *dev) +{ + struct opp_table *opp_table; + + /* Hold our table modification lock here */ + mutex_lock(&opp_table_lock); + + /* Check for existing table for 'dev' first */ + opp_table = _find_opp_table(dev); + if (IS_ERR(opp_table)) { + dev_err(dev, "Failed to find opp_table: %ld\n", + PTR_ERR(opp_table)); + goto unlock; + } + + /* Make sure there are no concurrent readers while updating opp_table */ + WARN_ON(!list_empty(&opp_table->opp_list)); + + if (!opp_table->supported_hw) { + dev_err(dev, "%s: Doesn't have supported hardware list\n", + __func__); + goto unlock; + } + + kfree(opp_table->supported_hw); + opp_table->supported_hw = NULL; + opp_table->supported_hw_count = 0; + + /* Try freeing opp_table if this was the last blocking resource */ + _remove_opp_table(opp_table); + +unlock: + mutex_unlock(&opp_table_lock); +} +EXPORT_SYMBOL_GPL(dev_pm_opp_put_supported_hw); + +/** + * dev_pm_opp_set_prop_name() - Set prop-extn name + * @dev: Device for which the prop-name has to be set. + * @name: name to postfix to properties. + * + * This is required only for the V2 bindings, and it enables a platform to + * specify the extn to be used for certain property names. The properties to + * which the extension will apply are opp-microvolt and opp-microamp. OPP core + * should postfix the property name with - while looking for them. + * + * Locking: The internal opp_table and opp structures are RCU protected. + * Hence this function internally uses RCU updater strategy with mutex locks + * to keep the integrity of the internal data structures. Callers should ensure + * that this function is *NOT* called under RCU protection or in contexts where + * mutex cannot be locked. + */ +int dev_pm_opp_set_prop_name(struct device *dev, const char *name) +{ + struct opp_table *opp_table; + int ret = 0; + + /* Hold our table modification lock here */ + mutex_lock(&opp_table_lock); + + opp_table = _add_opp_table(dev); + if (!opp_table) { + ret = -ENOMEM; + goto unlock; + } + + /* Make sure there are no concurrent readers while updating opp_table */ + WARN_ON(!list_empty(&opp_table->opp_list)); + + /* Do we already have a prop-name associated with opp_table? */ + if (opp_table->prop_name) { + dev_err(dev, "%s: Already have prop-name %s\n", __func__, + opp_table->prop_name); + ret = -EBUSY; + goto err; + } + + opp_table->prop_name = kstrdup(name, GFP_KERNEL); + if (!opp_table->prop_name) { + ret = -ENOMEM; + goto err; + } + + mutex_unlock(&opp_table_lock); + return 0; + +err: + _remove_opp_table(opp_table); +unlock: + mutex_unlock(&opp_table_lock); + + return ret; +} +EXPORT_SYMBOL_GPL(dev_pm_opp_set_prop_name); + +/** + * dev_pm_opp_put_prop_name() - Releases resources blocked for prop-name + * @dev: Device for which the prop-name has to be put. + * + * This is required only for the V2 bindings, and is called for a matching + * dev_pm_opp_set_prop_name(). Until this is called, the opp_table structure + * will not be freed. + * + * Locking: The internal opp_table and opp structures are RCU protected. + * Hence this function internally uses RCU updater strategy with mutex locks + * to keep the integrity of the internal data structures. Callers should ensure + * that this function is *NOT* called under RCU protection or in contexts where + * mutex cannot be locked. + */ +void dev_pm_opp_put_prop_name(struct device *dev) +{ + struct opp_table *opp_table; + + /* Hold our table modification lock here */ + mutex_lock(&opp_table_lock); + + /* Check for existing table for 'dev' first */ + opp_table = _find_opp_table(dev); + if (IS_ERR(opp_table)) { + dev_err(dev, "Failed to find opp_table: %ld\n", + PTR_ERR(opp_table)); + goto unlock; + } + + /* Make sure there are no concurrent readers while updating opp_table */ + WARN_ON(!list_empty(&opp_table->opp_list)); + + if (!opp_table->prop_name) { + dev_err(dev, "%s: Doesn't have a prop-name\n", __func__); + goto unlock; + } + + kfree(opp_table->prop_name); + opp_table->prop_name = NULL; + + /* Try freeing opp_table if this was the last blocking resource */ + _remove_opp_table(opp_table); + +unlock: + mutex_unlock(&opp_table_lock); +} +EXPORT_SYMBOL_GPL(dev_pm_opp_put_prop_name); + +/** + * dev_pm_opp_set_regulator() - Set regulator name for the device + * @dev: Device for which regulator name is being set. + * @name: Name of the regulator. + * + * In order to support OPP switching, OPP layer needs to know the name of the + * device's regulator, as the core would be required to switch voltages as well. + * + * This must be called before any OPPs are initialized for the device. + * + * Locking: The internal opp_table and opp structures are RCU protected. + * Hence this function internally uses RCU updater strategy with mutex locks + * to keep the integrity of the internal data structures. Callers should ensure + * that this function is *NOT* called under RCU protection or in contexts where + * mutex cannot be locked. + */ +int dev_pm_opp_set_regulator(struct device *dev, const char *name) +{ + struct opp_table *opp_table; + struct regulator *reg; + int ret; + + mutex_lock(&opp_table_lock); + + opp_table = _add_opp_table(dev); + if (!opp_table) { + ret = -ENOMEM; + goto unlock; + } + + /* This should be called before OPPs are initialized */ + if (WARN_ON(!list_empty(&opp_table->opp_list))) { + ret = -EBUSY; + goto err; + } + + /* Already have a regulator set */ + if (WARN_ON(!IS_ERR(opp_table->regulator))) { + ret = -EBUSY; + goto err; + } + /* Allocate the regulator */ + reg = regulator_get_optional(dev, name); + if (IS_ERR(reg)) { + ret = PTR_ERR(reg); + if (ret != -EPROBE_DEFER) + dev_err(dev, "%s: no regulator (%s) found: %d\n", + __func__, name, ret); + goto err; + } + + opp_table->regulator = reg; + + mutex_unlock(&opp_table_lock); + return 0; + +err: + _remove_opp_table(opp_table); +unlock: + mutex_unlock(&opp_table_lock); + + return ret; +} +EXPORT_SYMBOL_GPL(dev_pm_opp_set_regulator); + +/** + * dev_pm_opp_put_regulator() - Releases resources blocked for regulator + * @dev: Device for which regulator was set. + * + * Locking: The internal opp_table and opp structures are RCU protected. + * Hence this function internally uses RCU updater strategy with mutex locks + * to keep the integrity of the internal data structures. Callers should ensure + * that this function is *NOT* called under RCU protection or in contexts where + * mutex cannot be locked. + */ +void dev_pm_opp_put_regulator(struct device *dev) +{ + struct opp_table *opp_table; + + mutex_lock(&opp_table_lock); + + /* Check for existing table for 'dev' first */ + opp_table = _find_opp_table(dev); + if (IS_ERR(opp_table)) { + dev_err(dev, "Failed to find opp_table: %ld\n", + PTR_ERR(opp_table)); + goto unlock; + } + + if (IS_ERR(opp_table->regulator)) { + dev_err(dev, "%s: Doesn't have regulator set\n", __func__); + goto unlock; + } + + /* Make sure there are no concurrent readers while updating opp_table */ + WARN_ON(!list_empty(&opp_table->opp_list)); + + regulator_put(opp_table->regulator); + opp_table->regulator = ERR_PTR(-ENXIO); + + /* Try freeing opp_table if this was the last blocking resource */ + _remove_opp_table(opp_table); + +unlock: + mutex_unlock(&opp_table_lock); +} +EXPORT_SYMBOL_GPL(dev_pm_opp_put_regulator); + +static bool _opp_is_supported(struct device *dev, struct opp_table *opp_table, + struct device_node *np) +{ + unsigned int count = opp_table->supported_hw_count; + u32 version; + int ret; + + if (!opp_table->supported_hw) + return true; + + while (count--) { + ret = of_property_read_u32_index(np, "opp-supported-hw", count, + &version); + if (ret) { + dev_warn(dev, "%s: failed to read opp-supported-hw property at index %d: %d\n", + __func__, count, ret); + return false; + } + + /* Both of these are bitwise masks of the versions */ + if (!(version & opp_table->supported_hw[count])) + return false; + } + + return true; +} + +/** * _opp_add_static_v2() - Allocate static OPPs (As per 'v2' DT bindings) * @dev: device for which we do this operation * @np: device node * - * This function adds an opp definition to the opp list and returns status. The + * This function adds an opp definition to the opp table and returns status. The * opp can be controlled using dev_pm_opp_enable/disable functions and may be * removed by dev_pm_opp_remove. * - * Locking: The internal device_opp and opp structures are RCU protected. + * Locking: The internal opp_table and opp structures are RCU protected. * Hence this function internally uses RCU updater strategy with mutex locks * to keep the integrity of the internal data structures. Callers should ensure * that this function is *NOT* called under RCU protection or in contexts where @@ -849,16 +1572,16 @@ */ static int _opp_add_static_v2(struct device *dev, struct device_node *np) { - struct device_opp *dev_opp; + struct opp_table *opp_table; struct dev_pm_opp *new_opp; u64 rate; u32 val; int ret; - /* Hold our list modification lock here */ - mutex_lock(&dev_opp_list_lock); + /* Hold our table modification lock here */ + mutex_lock(&opp_table_lock); - new_opp = _allocate_opp(dev, &dev_opp); + new_opp = _allocate_opp(dev, &opp_table); if (!new_opp) { ret = -ENOMEM; goto unlock; @@ -870,6 +1593,12 @@ goto free_opp; } + /* Check if the OPP supports hardware's hierarchy of versions or not */ + if (!_opp_is_supported(dev, opp_table, np)) { + dev_dbg(dev, "OPP not supported by hardware: %llu\n", rate); + goto free_opp; + } + /* * Rate is defined as an unsigned long in clk API, and so casting * explicitly to its type. Must be fixed once rate is 64 bit @@ -885,28 +1614,30 @@ if (!of_property_read_u32(np, "clock-latency-ns", &val)) new_opp->clock_latency_ns = val; - ret = opp_parse_supplies(new_opp, dev); + ret = opp_parse_supplies(new_opp, dev, opp_table); if (ret) goto free_opp; - ret = _opp_add(dev, new_opp, dev_opp); + ret = _opp_add(dev, new_opp, opp_table); if (ret) goto free_opp; /* OPP to select on device suspend */ if (of_property_read_bool(np, "opp-suspend")) { - if (dev_opp->suspend_opp) + if (opp_table->suspend_opp) { dev_warn(dev, "%s: Multiple suspend OPPs found (%lu %lu)\n", - __func__, dev_opp->suspend_opp->rate, + __func__, opp_table->suspend_opp->rate, new_opp->rate); - else - dev_opp->suspend_opp = new_opp; + } else { + new_opp->suspend = true; + opp_table->suspend_opp = new_opp; + } } - if (new_opp->clock_latency_ns > dev_opp->clock_latency_ns_max) - dev_opp->clock_latency_ns_max = new_opp->clock_latency_ns; + if (new_opp->clock_latency_ns > opp_table->clock_latency_ns_max) + opp_table->clock_latency_ns_max = new_opp->clock_latency_ns; - mutex_unlock(&dev_opp_list_lock); + mutex_unlock(&opp_table_lock); pr_debug("%s: turbo:%d rate:%lu uv:%lu uvmin:%lu uvmax:%lu latency:%lu\n", __func__, new_opp->turbo, new_opp->rate, new_opp->u_volt, @@ -917,13 +1648,13 @@ * Notify the changes in the availability of the operable * frequency/voltage list. */ - srcu_notifier_call_chain(&dev_opp->srcu_head, OPP_EVENT_ADD, new_opp); + srcu_notifier_call_chain(&opp_table->srcu_head, OPP_EVENT_ADD, new_opp); return 0; free_opp: - _opp_remove(dev_opp, new_opp, false); + _opp_remove(opp_table, new_opp, false); unlock: - mutex_unlock(&dev_opp_list_lock); + mutex_unlock(&opp_table_lock); return ret; } @@ -933,11 +1664,11 @@ * @freq: Frequency in Hz for this OPP * @u_volt: Voltage in uVolts for this OPP * - * This function adds an opp definition to the opp list and returns status. + * This function adds an opp definition to the opp table and returns status. * The opp is made available by default and it can be controlled using * dev_pm_opp_enable/disable functions. * - * Locking: The internal device_opp and opp structures are RCU protected. + * Locking: The internal opp_table and opp structures are RCU protected. * Hence this function internally uses RCU updater strategy with mutex locks * to keep the integrity of the internal data structures. Callers should ensure * that this function is *NOT* called under RCU protection or in contexts where @@ -969,7 +1700,7 @@ * copy operation, returns 0 if no modification was done OR modification was * successful. * - * Locking: The internal device_opp and opp structures are RCU protected. + * Locking: The internal opp_table and opp structures are RCU protected. * Hence this function internally uses RCU updater strategy with mutex locks to * keep the integrity of the internal data structures. Callers should ensure * that this function is *NOT* called under RCU protection or in contexts where @@ -978,7 +1709,7 @@ static int _opp_set_availability(struct device *dev, unsigned long freq, bool availability_req) { - struct device_opp *dev_opp; + struct opp_table *opp_table; struct dev_pm_opp *new_opp, *tmp_opp, *opp = ERR_PTR(-ENODEV); int r = 0; @@ -987,18 +1718,18 @@ if (!new_opp) return -ENOMEM; - mutex_lock(&dev_opp_list_lock); + mutex_lock(&opp_table_lock); - /* Find the device_opp */ - dev_opp = _find_device_opp(dev); - if (IS_ERR(dev_opp)) { - r = PTR_ERR(dev_opp); + /* Find the opp_table */ + opp_table = _find_opp_table(dev); + if (IS_ERR(opp_table)) { + r = PTR_ERR(opp_table); dev_warn(dev, "%s: Device OPP not found (%d)\n", __func__, r); goto unlock; } /* Do we have the frequency? */ - list_for_each_entry(tmp_opp, &dev_opp->opp_list, node) { + list_for_each_entry(tmp_opp, &opp_table->opp_list, node) { if (tmp_opp->rate == freq) { opp = tmp_opp; break; @@ -1019,21 +1750,21 @@ new_opp->available = availability_req; list_replace_rcu(&opp->node, &new_opp->node); - mutex_unlock(&dev_opp_list_lock); - call_srcu(&dev_opp->srcu_head.srcu, &opp->rcu_head, _kfree_opp_rcu); + mutex_unlock(&opp_table_lock); + call_srcu(&opp_table->srcu_head.srcu, &opp->rcu_head, _kfree_opp_rcu); /* Notify the change of the OPP availability */ if (availability_req) - srcu_notifier_call_chain(&dev_opp->srcu_head, OPP_EVENT_ENABLE, - new_opp); + srcu_notifier_call_chain(&opp_table->srcu_head, + OPP_EVENT_ENABLE, new_opp); else - srcu_notifier_call_chain(&dev_opp->srcu_head, OPP_EVENT_DISABLE, - new_opp); + srcu_notifier_call_chain(&opp_table->srcu_head, + OPP_EVENT_DISABLE, new_opp); return 0; unlock: - mutex_unlock(&dev_opp_list_lock); + mutex_unlock(&opp_table_lock); kfree(new_opp); return r; } @@ -1047,7 +1778,7 @@ * corresponding error value. It is meant to be used for users an OPP available * after being temporarily made unavailable with dev_pm_opp_disable. * - * Locking: The internal device_opp and opp structures are RCU protected. + * Locking: The internal opp_table and opp structures are RCU protected. * Hence this function indirectly uses RCU and mutex locks to keep the * integrity of the internal data structures. Callers should ensure that * this function is *NOT* called under RCU protection or in contexts where @@ -1073,7 +1804,7 @@ * control by users to make this OPP not available until the circumstances are * right to make it available again (with a call to dev_pm_opp_enable). * - * Locking: The internal device_opp and opp structures are RCU protected. + * Locking: The internal opp_table and opp structures are RCU protected. * Hence this function indirectly uses RCU and mutex locks to keep the * integrity of the internal data structures. Callers should ensure that * this function is *NOT* called under RCU protection or in contexts where @@ -1091,26 +1822,26 @@ /** * dev_pm_opp_get_notifier() - find notifier_head of the device with opp - * @dev: device pointer used to lookup device OPPs. + * @dev: device pointer used to lookup OPP table. * * Return: pointer to notifier head if found, otherwise -ENODEV or * -EINVAL based on type of error casted as pointer. value must be checked * with IS_ERR to determine valid pointer or error result. * - * Locking: This function must be called under rcu_read_lock(). dev_opp is a RCU - * protected pointer. The reason for the same is that the opp pointer which is - * returned will remain valid for use with opp_get_{voltage, freq} only while + * Locking: This function must be called under rcu_read_lock(). opp_table is a + * RCU protected pointer. The reason for the same is that the opp pointer which + * is returned will remain valid for use with opp_get_{voltage, freq} only while * under the locked area. The pointer returned must be used prior to unlocking * with rcu_read_unlock() to maintain the integrity of the pointer. */ struct srcu_notifier_head *dev_pm_opp_get_notifier(struct device *dev) { - struct device_opp *dev_opp = _find_device_opp(dev); + struct opp_table *opp_table = _find_opp_table(dev); - if (IS_ERR(dev_opp)) - return ERR_CAST(dev_opp); /* matching type */ + if (IS_ERR(opp_table)) + return ERR_CAST(opp_table); /* matching type */ - return &dev_opp->srcu_head; + return &opp_table->srcu_head; } EXPORT_SYMBOL_GPL(dev_pm_opp_get_notifier); @@ -1118,11 +1849,11 @@ /** * dev_pm_opp_of_remove_table() - Free OPP table entries created from static DT * entries - * @dev: device pointer used to lookup device OPPs. + * @dev: device pointer used to lookup OPP table. * * Free OPPs created using static entries present in DT. * - * Locking: The internal device_opp and opp structures are RCU protected. + * Locking: The internal opp_table and opp structures are RCU protected. * Hence this function indirectly uses RCU updater strategy with mutex locks * to keep the integrity of the internal data structures. Callers should ensure * that this function is *NOT* called under RCU protection or in contexts where @@ -1130,38 +1861,38 @@ */ void dev_pm_opp_of_remove_table(struct device *dev) { - struct device_opp *dev_opp; + struct opp_table *opp_table; struct dev_pm_opp *opp, *tmp; - /* Hold our list modification lock here */ - mutex_lock(&dev_opp_list_lock); + /* Hold our table modification lock here */ + mutex_lock(&opp_table_lock); - /* Check for existing list for 'dev' */ - dev_opp = _find_device_opp(dev); - if (IS_ERR(dev_opp)) { - int error = PTR_ERR(dev_opp); + /* Check for existing table for 'dev' */ + opp_table = _find_opp_table(dev); + if (IS_ERR(opp_table)) { + int error = PTR_ERR(opp_table); if (error != -ENODEV) - WARN(1, "%s: dev_opp: %d\n", + WARN(1, "%s: opp_table: %d\n", IS_ERR_OR_NULL(dev) ? "Invalid device" : dev_name(dev), error); goto unlock; } - /* Find if dev_opp manages a single device */ - if (list_is_singular(&dev_opp->dev_list)) { + /* Find if opp_table manages a single device */ + if (list_is_singular(&opp_table->dev_list)) { /* Free static OPPs */ - list_for_each_entry_safe(opp, tmp, &dev_opp->opp_list, node) { + list_for_each_entry_safe(opp, tmp, &opp_table->opp_list, node) { if (!opp->dynamic) - _opp_remove(dev_opp, opp, true); + _opp_remove(opp_table, opp, true); } } else { - _remove_list_dev(_find_list_dev(dev, dev_opp), dev_opp); + _remove_opp_dev(_find_opp_dev(dev, opp_table), opp_table); } unlock: - mutex_unlock(&dev_opp_list_lock); + mutex_unlock(&opp_table_lock); } EXPORT_SYMBOL_GPL(dev_pm_opp_of_remove_table); @@ -1182,22 +1913,22 @@ static int _of_add_opp_table_v2(struct device *dev, struct device_node *opp_np) { struct device_node *np; - struct device_opp *dev_opp; + struct opp_table *opp_table; int ret = 0, count = 0; - mutex_lock(&dev_opp_list_lock); + mutex_lock(&opp_table_lock); - dev_opp = _managed_opp(opp_np); - if (dev_opp) { + opp_table = _managed_opp(opp_np); + if (opp_table) { /* OPPs are already managed */ - if (!_add_list_dev(dev, dev_opp)) + if (!_add_opp_dev(dev, opp_table)) ret = -ENOMEM; - mutex_unlock(&dev_opp_list_lock); + mutex_unlock(&opp_table_lock); return ret; } - mutex_unlock(&dev_opp_list_lock); + mutex_unlock(&opp_table_lock); - /* We have opp-list node now, iterate over it and add OPPs */ + /* We have opp-table node now, iterate over it and add OPPs */ for_each_available_child_of_node(opp_np, np) { count++; @@ -1214,19 +1945,19 @@ if (WARN_ON(!count)) return -ENOENT; - mutex_lock(&dev_opp_list_lock); + mutex_lock(&opp_table_lock); - dev_opp = _find_device_opp(dev); - if (WARN_ON(IS_ERR(dev_opp))) { - ret = PTR_ERR(dev_opp); - mutex_unlock(&dev_opp_list_lock); + opp_table = _find_opp_table(dev); + if (WARN_ON(IS_ERR(opp_table))) { + ret = PTR_ERR(opp_table); + mutex_unlock(&opp_table_lock); goto free_table; } - dev_opp->np = opp_np; - dev_opp->shared_opp = of_property_read_bool(opp_np, "opp-shared"); + opp_table->np = opp_np; + opp_table->shared_opp = of_property_read_bool(opp_np, "opp-shared"); - mutex_unlock(&dev_opp_list_lock); + mutex_unlock(&opp_table_lock); return 0; @@ -1255,7 +1986,7 @@ */ nr = prop->length / sizeof(u32); if (nr % 2) { - dev_err(dev, "%s: Invalid OPP list\n", __func__); + dev_err(dev, "%s: Invalid OPP table\n", __func__); return -EINVAL; } @@ -1275,11 +2006,11 @@ /** * dev_pm_opp_of_add_table() - Initialize opp table from device tree - * @dev: device pointer used to lookup device OPPs. + * @dev: device pointer used to lookup OPP table. * * Register the initial OPP table with the OPP library for given device. * - * Locking: The internal device_opp and opp structures are RCU protected. + * Locking: The internal opp_table and opp structures are RCU protected. * Hence this function indirectly uses RCU updater strategy with mutex locks * to keep the integrity of the internal data structures. Callers should ensure * that this function is *NOT* called under RCU protection or in contexts where diff -ruw linux-4.4.115/drivers/base/power/opp/cpu.c linux-4.4.115-fbx/drivers/base/power/opp/cpu.c --- linux-4.4.115/drivers/base/power/opp/cpu.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/base/power/opp/cpu.c 2019-01-22 16:16:22.879240756 +0100 @@ -31,7 +31,7 @@ * @table: Cpufreq table returned back to caller * * Generate a cpufreq table for a provided device- this assumes that the - * opp list is already initialized and ready for usage. + * opp table is already initialized and ready for usage. * * This function allocates required memory for the cpufreq table. It is * expected that the caller does the required maintenance such as freeing @@ -44,7 +44,7 @@ * WARNING: It is important for the callers to ensure refreshing their copy of * the table if any of the mentioned functions have been invoked in the interim. * - * Locking: The internal device_opp and opp structures are RCU protected. + * Locking: The internal opp_table and opp structures are RCU protected. * Since we just use the regular accessor functions to access the internal data * structures, we use RCU read lock inside this function. As a result, users of * this function DONOT need to use explicit locks for invoking. @@ -122,15 +122,15 @@ /* Required only for V1 bindings, as v2 can manage it from DT itself */ int dev_pm_opp_set_sharing_cpus(struct device *cpu_dev, cpumask_var_t cpumask) { - struct device_list_opp *list_dev; - struct device_opp *dev_opp; + struct opp_device *opp_dev; + struct opp_table *opp_table; struct device *dev; int cpu, ret = 0; - mutex_lock(&dev_opp_list_lock); + mutex_lock(&opp_table_lock); - dev_opp = _find_device_opp(cpu_dev); - if (IS_ERR(dev_opp)) { + opp_table = _find_opp_table(cpu_dev); + if (IS_ERR(opp_table)) { ret = -EINVAL; goto unlock; } @@ -146,15 +146,15 @@ continue; } - list_dev = _add_list_dev(dev, dev_opp); - if (!list_dev) { - dev_err(dev, "%s: failed to add list-dev for cpu%d device\n", + opp_dev = _add_opp_dev(dev, opp_table); + if (!opp_dev) { + dev_err(dev, "%s: failed to add opp-dev for cpu%d device\n", __func__, cpu); continue; } } unlock: - mutex_unlock(&dev_opp_list_lock); + mutex_unlock(&opp_table_lock); return ret; } @@ -214,7 +214,6 @@ /* * Works only for OPP v2 bindings. * - * cpumask should be already set to mask of cpu_dev->id. * Returns -ENOENT if operating-points-v2 bindings aren't supported. */ int dev_pm_opp_of_get_sharing_cpus(struct device *cpu_dev, cpumask_var_t cpumask) @@ -230,6 +229,8 @@ return -ENOENT; } + cpumask_set_cpu(cpu_dev->id, cpumask); + /* OPPs are shared ? */ if (!of_property_read_bool(np, "opp-shared")) goto put_cpu_node; diff -ruw linux-4.4.115/drivers/base/power/opp/Makefile linux-4.4.115-fbx/drivers/base/power/opp/Makefile --- linux-4.4.115/drivers/base/power/opp/Makefile 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/base/power/opp/Makefile 2019-01-22 16:16:22.879240756 +0100 @@ -1,2 +1,3 @@ ccflags-$(CONFIG_DEBUG_DRIVER) := -DDEBUG obj-y += core.o cpu.o +obj-$(CONFIG_DEBUG_FS) += debugfs.o diff -ruw linux-4.4.115/drivers/base/power/opp/opp.h linux-4.4.115-fbx/drivers/base/power/opp/opp.h --- linux-4.4.115/drivers/base/power/opp/opp.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/base/power/opp/opp.h 2019-01-22 16:16:22.879240756 +0100 @@ -17,17 +17,21 @@ #include #include #include +#include #include #include #include +struct clk; +struct regulator; + /* Lock to allow exclusive modification to the device and opp lists */ -extern struct mutex dev_opp_list_lock; +extern struct mutex opp_table_lock; /* * Internal data structure organization with the OPP layer library is as * follows: - * dev_opp_list (root) + * opp_tables (root) * |- device 1 (represents voltage domain 1) * | |- opp 1 (availability, freq, voltage) * | |- opp 2 .. @@ -36,23 +40,24 @@ * |- device 2 (represents the next voltage domain) * ... * `- device m (represents mth voltage domain) - * device 1, 2.. are represented by dev_opp structure while each opp + * device 1, 2.. are represented by opp_table structure while each opp * is represented by the opp structure. */ /** * struct dev_pm_opp - Generic OPP description structure - * @node: opp list node. The nodes are maintained throughout the lifetime + * @node: opp table node. The nodes are maintained throughout the lifetime * of boot. It is expected only an optimal set of OPPs are * added to the library by the SoC framework. - * RCU usage: opp list is traversed with RCU locks. node + * RCU usage: opp table is traversed with RCU locks. node * modification is possible realtime, hence the modifications - * are protected by the dev_opp_list_lock for integrity. + * are protected by the opp_table_lock for integrity. * IMPORTANT: the opp nodes should be maintained in increasing * order. - * @dynamic: not-created from static DT entries. * @available: true/false - marks if this OPP as available or not + * @dynamic: not-created from static DT entries. * @turbo: true if turbo (boost) OPP + * @suspend: true if suspend OPP * @rate: Frequency in hertz * @u_volt: Target voltage in microvolts corresponding to this OPP * @u_volt_min: Minimum voltage in microvolts corresponding to this OPP @@ -60,9 +65,10 @@ * @u_amp: Maximum current drawn by the device in microamperes * @clock_latency_ns: Latency (in nanoseconds) of switching to this OPP's * frequency from any other OPP's frequency. - * @dev_opp: points back to the device_opp struct this opp belongs to + * @opp_table: points back to the opp_table struct this opp belongs to * @rcu_head: RCU callback head used for deferred freeing * @np: OPP's device node. + * @dentry: debugfs dentry pointer (per opp) * * This structure stores the OPP information for a given device. */ @@ -72,6 +78,7 @@ bool available; bool dynamic; bool turbo; + bool suspend; unsigned long rate; unsigned long u_volt; @@ -80,40 +87,60 @@ unsigned long u_amp; unsigned long clock_latency_ns; - struct device_opp *dev_opp; + struct opp_table *opp_table; struct rcu_head rcu_head; struct device_node *np; + +#ifdef CONFIG_DEBUG_FS + struct dentry *dentry; +#endif }; /** - * struct device_list_opp - devices managed by 'struct device_opp' + * struct opp_device - devices managed by 'struct opp_table' * @node: list node * @dev: device to which the struct object belongs * @rcu_head: RCU callback head used for deferred freeing + * @dentry: debugfs dentry pointer (per device) * - * This is an internal data structure maintaining the list of devices that are - * managed by 'struct device_opp'. + * This is an internal data structure maintaining the devices that are managed + * by 'struct opp_table'. */ -struct device_list_opp { +struct opp_device { struct list_head node; const struct device *dev; struct rcu_head rcu_head; + +#ifdef CONFIG_DEBUG_FS + struct dentry *dentry; +#endif }; /** - * struct device_opp - Device opp structure - * @node: list node - contains the devices with OPPs that + * struct opp_table - Device opp structure + * @node: table node - contains the devices with OPPs that * have been registered. Nodes once added are not modified in this - * list. - * RCU usage: nodes are not modified in the list of device_opp, - * however addition is possible and is secured by dev_opp_list_lock + * table. + * RCU usage: nodes are not modified in the table of opp_table, + * however addition is possible and is secured by opp_table_lock * @srcu_head: notifier head to notify the OPP availability changes. * @rcu_head: RCU callback head used for deferred freeing * @dev_list: list of devices that share these OPPs - * @opp_list: list of opps + * @opp_list: table of opps * @np: struct device_node pointer for opp's DT node. + * @clock_latency_ns_max: Max clock latency in nanoseconds. * @shared_opp: OPP is shared between multiple devices. + * @suspend_opp: Pointer to OPP to be used during device suspend. + * @supported_hw: Array of version number to support. + * @supported_hw_count: Number of elements in supported_hw array. + * @prop_name: A name to postfix to many DT properties, while parsing them. + * @clk: Device's clock handle + * @regulator: Supply regulator + * @dentry: debugfs dentry pointer of the real device directory (not links). + * @dentry_name: Name of the real dentry. + * + * @voltage_tolerance_v1: In percentage, for v1 bindings only. * * This is an internal data structure maintaining the link to opps attached to * a device. This structure is not meant to be shared to users as it is @@ -123,7 +150,7 @@ * need to wait for the grace period of both of them before freeing any * resources. And so we have used kfree_rcu() from within call_srcu() handlers. */ -struct device_opp { +struct opp_table { struct list_head node; struct srcu_notifier_head srcu_head; @@ -133,14 +160,48 @@ struct device_node *np; unsigned long clock_latency_ns_max; + + /* For backward compatibility with v1 bindings */ + unsigned int voltage_tolerance_v1; + bool shared_opp; struct dev_pm_opp *suspend_opp; + + unsigned int *supported_hw; + unsigned int supported_hw_count; + const char *prop_name; + struct clk *clk; + struct regulator *regulator; + +#ifdef CONFIG_DEBUG_FS + struct dentry *dentry; + char dentry_name[NAME_MAX]; +#endif }; /* Routines internal to opp core */ -struct device_opp *_find_device_opp(struct device *dev); -struct device_list_opp *_add_list_dev(const struct device *dev, - struct device_opp *dev_opp); +struct opp_table *_find_opp_table(struct device *dev); +struct opp_device *_add_opp_dev(const struct device *dev, struct opp_table *opp_table); struct device_node *_of_get_opp_desc_node(struct device *dev); +#ifdef CONFIG_DEBUG_FS +void opp_debug_remove_one(struct dev_pm_opp *opp); +int opp_debug_create_one(struct dev_pm_opp *opp, struct opp_table *opp_table); +int opp_debug_register(struct opp_device *opp_dev, struct opp_table *opp_table); +void opp_debug_unregister(struct opp_device *opp_dev, struct opp_table *opp_table); +#else +static inline void opp_debug_remove_one(struct dev_pm_opp *opp) {} + +static inline int opp_debug_create_one(struct dev_pm_opp *opp, + struct opp_table *opp_table) +{ return 0; } +static inline int opp_debug_register(struct opp_device *opp_dev, + struct opp_table *opp_table) +{ return 0; } + +static inline void opp_debug_unregister(struct opp_device *opp_dev, + struct opp_table *opp_table) +{ } +#endif /* DEBUG_FS */ + #endif /* __DRIVER_OPP_H__ */ diff -ruw linux-4.4.115/drivers/base/power/power.h linux-4.4.115-fbx/drivers/base/power/power.h --- linux-4.4.115/drivers/base/power/power.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/base/power/power.h 2019-01-22 16:16:22.879240756 +0100 @@ -140,6 +140,7 @@ extern void device_pm_move_before(struct device *, struct device *); extern void device_pm_move_after(struct device *, struct device *); extern void device_pm_move_last(struct device *); +extern void device_pm_check_callbacks(struct device *dev); #else /* !CONFIG_PM_SLEEP */ @@ -158,6 +159,8 @@ struct device *devb) {} static inline void device_pm_move_last(struct device *dev) {} +static inline void device_pm_check_callbacks(struct device *dev) {} + #endif /* !CONFIG_PM_SLEEP */ static inline void device_pm_init(struct device *dev) diff -ruw linux-4.4.115/drivers/base/power/qos.c linux-4.4.115-fbx/drivers/base/power/qos.c --- linux-4.4.115/drivers/base/power/qos.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/base/power/qos.c 2019-01-22 16:16:22.879240756 +0100 @@ -147,7 +147,7 @@ switch(req->type) { case DEV_PM_QOS_RESUME_LATENCY: ret = pm_qos_update_target(&qos->resume_latency, - &req->data.pnode, action, value); + &req->data.lat, action, value); if (ret) { value = pm_qos_read_value(&qos->resume_latency); blocking_notifier_call_chain(&dev_pm_notifiers, @@ -157,7 +157,7 @@ break; case DEV_PM_QOS_LATENCY_TOLERANCE: ret = pm_qos_update_target(&qos->latency_tolerance, - &req->data.pnode, action, value); + &req->data.lat, action, value); if (ret) { value = pm_qos_read_value(&qos->latency_tolerance); req->dev->power.set_latency_tolerance(req->dev, value); @@ -258,7 +258,7 @@ /* Flush the constraints lists for the device. */ c = &qos->resume_latency; - plist_for_each_entry_safe(req, tmp, &c->list, data.pnode) { + plist_for_each_entry_safe(req, tmp, &c->list, data.lat.node) { /* * Update constraints list and call the notification * callbacks if needed @@ -266,8 +266,11 @@ apply_constraint(req, PM_QOS_REMOVE_REQ, PM_QOS_DEFAULT_VALUE); memset(req, 0, sizeof(*req)); } + + kfree(c->notifiers); + c = &qos->latency_tolerance; - plist_for_each_entry_safe(req, tmp, &c->list, data.pnode) { + plist_for_each_entry_safe(req, tmp, &c->list, data.lat.node) { apply_constraint(req, PM_QOS_REMOVE_REQ, PM_QOS_DEFAULT_VALUE); memset(req, 0, sizeof(*req)); } @@ -382,7 +385,7 @@ switch(req->type) { case DEV_PM_QOS_RESUME_LATENCY: case DEV_PM_QOS_LATENCY_TOLERANCE: - curr_value = req->data.pnode.prio; + curr_value = req->data.lat.node.prio; break; case DEV_PM_QOS_FLAGS: curr_value = req->data.flr.flags; @@ -835,7 +838,7 @@ ret = IS_ERR_OR_NULL(dev->power.qos) || !dev->power.qos->latency_tolerance_req ? PM_QOS_LATENCY_TOLERANCE_NO_CONSTRAINT : - dev->power.qos->latency_tolerance_req->data.pnode.prio; + dev->power.qos->latency_tolerance_req->data.lat.node.prio; mutex_unlock(&dev_pm_qos_mtx); return ret; } diff -ruw linux-4.4.115/drivers/base/power/wakeup.c linux-4.4.115-fbx/drivers/base/power/wakeup.c --- linux-4.4.115/drivers/base/power/wakeup.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/base/power/wakeup.c 2019-10-29 09:26:23.413200927 +0100 @@ -15,6 +15,7 @@ #include #include #include +#include #include #include "power.h" @@ -808,6 +809,37 @@ } EXPORT_SYMBOL_GPL(pm_wakeup_event); +void pm_get_active_wakeup_sources(char *pending_wakeup_source, size_t max) +{ + struct wakeup_source *ws, *last_active_ws = NULL; + int len = 0; + bool active = false; + + rcu_read_lock(); + list_for_each_entry_rcu(ws, &wakeup_sources, entry) { + if (ws->active && len < max) { + if (!active) + len += scnprintf(pending_wakeup_source, max, + "Pending Wakeup Sources: "); + len += scnprintf(pending_wakeup_source + len, max - len, + "%s ", ws->name); + active = true; + } else if (!active && + (!last_active_ws || + ktime_to_ns(ws->last_time) > + ktime_to_ns(last_active_ws->last_time))) { + last_active_ws = ws; + } + } + if (!active && last_active_ws) { + scnprintf(pending_wakeup_source, max, + "Last active Wakeup Source: %s", + last_active_ws->name); + } + rcu_read_unlock(); +} +EXPORT_SYMBOL_GPL(pm_get_active_wakeup_sources); + void pm_print_active_wakeup_sources(void) { struct wakeup_source *ws; @@ -1015,7 +1047,7 @@ active_time = ktime_set(0, 0); } - seq_printf(m, "%-12s\t%lu\t\t%lu\t\t%lu\t\t%lu\t\t%lld\t\t%lld\t\t%lld\t\t%lld\t\t%lld\n", + seq_printf(m, "%-32s\t%lu\t\t%lu\t\t%lu\t\t%lu\t\t%lld\t\t%lld\t\t%lld\t\t%lld\t\t%lld\n", ws->name, active_count, ws->event_count, ws->wakeup_count, ws->expire_count, ktime_to_ms(active_time), ktime_to_ms(total_time), @@ -1036,7 +1068,7 @@ struct wakeup_source *ws; int srcuidx; - seq_puts(m, "name\t\tactive_count\tevent_count\twakeup_count\t" + seq_puts(m, "name\t\t\t\t\tactive_count\tevent_count\twakeup_count\t" "expire_count\tactive_since\ttotal_time\tmax_time\t" "last_change\tprevent_suspend_time\n"); diff -ruw linux-4.4.115/drivers/base/regmap/internal.h linux-4.4.115-fbx/drivers/base/regmap/internal.h --- linux-4.4.115/drivers/base/regmap/internal.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/base/regmap/internal.h 2019-01-22 16:16:22.883240792 +0100 @@ -85,6 +85,9 @@ struct list_head debugfs_off_cache; struct mutex cache_lock; + + unsigned int dump_address; + unsigned int dump_count; #endif unsigned int max_register; @@ -245,6 +248,10 @@ int _regmap_raw_write(struct regmap *map, unsigned int reg, const void *val, size_t val_len); +int _regmap_raw_multi_reg_write(struct regmap *map, + const struct reg_sequence *regs, + size_t num_regs); + void regmap_async_complete_cb(struct regmap_async *async, int ret); enum regmap_endian regmap_get_val_endian(struct device *dev, diff -ruw linux-4.4.115/drivers/base/regmap/Kconfig linux-4.4.115-fbx/drivers/base/regmap/Kconfig --- linux-4.4.115/drivers/base/regmap/Kconfig 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/base/regmap/Kconfig 2019-01-22 16:16:22.883240792 +0100 @@ -3,7 +3,7 @@ # subsystems should select the appropriate symbols. config REGMAP - default y if (REGMAP_I2C || REGMAP_SPI || REGMAP_SPMI || REGMAP_AC97 || REGMAP_MMIO || REGMAP_IRQ) + default y if (REGMAP_I2C || REGMAP_SPI || REGMAP_SPMI || REGMAP_AC97 || REGMAP_MMIO || REGMAP_IRQ || REGMAP_SWR) select LZO_COMPRESS select LZO_DECOMPRESS select IRQ_DOMAIN if REGMAP_IRQ @@ -29,3 +29,15 @@ config REGMAP_IRQ bool + +config REGMAP_SWR + tristate + +config REGMAP_ALLOW_WRITE_DEBUGFS + depends on REGMAP && DEBUG_FS + bool "Allow REGMAP debugfs write" + default n + help + Say 'y' here to allow the regmap debugfs write. Regmap debugfs write + could be risky when accessing some essential hardwares, so it is not + recommended to enable this option on any production device. diff -ruw linux-4.4.115/drivers/base/regmap/Makefile linux-4.4.115-fbx/drivers/base/regmap/Makefile --- linux-4.4.115/drivers/base/regmap/Makefile 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/base/regmap/Makefile 2019-01-22 16:16:22.883240792 +0100 @@ -10,3 +10,4 @@ obj-$(CONFIG_REGMAP_SPMI) += regmap-spmi.o obj-$(CONFIG_REGMAP_MMIO) += regmap-mmio.o obj-$(CONFIG_REGMAP_IRQ) += regmap-irq.o +obj-$(CONFIG_REGMAP_SWR) += regmap-swr.o diff -ruw linux-4.4.115/drivers/base/regmap/regcache.c linux-4.4.115-fbx/drivers/base/regmap/regcache.c --- linux-4.4.115/drivers/base/regmap/regcache.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/base/regmap/regcache.c 2019-01-22 16:16:22.883240792 +0100 @@ -682,6 +682,53 @@ return ret; } +static int regcache_sync_block_raw_multi_reg(struct regmap *map, void *block, + unsigned long *cache_present, + unsigned int block_base, + unsigned int start, + unsigned int end) +{ + unsigned int i, val; + unsigned int regtmp = 0; + int ret = 0; + struct reg_sequence *regs; + size_t num_regs = ((end - start) + 1); + + regs = kcalloc(num_regs, sizeof(struct reg_default), GFP_KERNEL); + if (!regs) + return -ENOMEM; + + num_regs = 0; + for (i = start; i < end; i++) { + regtmp = block_base + (i * map->reg_stride); + + /* skip registers that are not defined/available */ + if (!regcache_reg_present(cache_present, i)) + continue; + + val = regcache_get_val(map, block, i); + + /* Is this the hardware default? If so skip. */ + ret = regcache_lookup_reg(map, regtmp); + if (ret >= 0 && val == map->reg_defaults[ret].def) { + continue; + } else { + regs[num_regs].reg = regtmp; + regs[num_regs].def = val; + regs[num_regs].delay_us = 0; + num_regs += 1; + } + } + ret = 0; + if (num_regs) { + dev_dbg(map->dev, "%s: start: 0x%x - end: 0x%x\n", + __func__, regs[0].reg, regs[num_regs-1].reg); + ret = _regmap_raw_multi_reg_write(map, regs, num_regs); + } + kfree(regs); + return ret; +} + static int regcache_sync_block_raw(struct regmap *map, void *block, unsigned long *cache_present, unsigned int block_base, unsigned int start, @@ -729,7 +776,12 @@ unsigned int block_base, unsigned int start, unsigned int end) { - if (regmap_can_raw_write(map) && !map->use_single_write) + if (regmap_can_raw_write(map) && map->can_multi_write) + return regcache_sync_block_raw_multi_reg(map, block, + cache_present, + block_base, start, + end); + else if (regmap_can_raw_write(map) && !map->use_single_write) return regcache_sync_block_raw(map, block, cache_present, block_base, start, end); else diff -ruw linux-4.4.115/drivers/base/regmap/regmap.c linux-4.4.115-fbx/drivers/base/regmap/regmap.c --- linux-4.4.115/drivers/base/regmap/regmap.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/base/regmap/regmap.c 2019-10-29 09:26:23.413200927 +0100 @@ -1822,7 +1822,7 @@ * they are all in the same page and have been changed to being page * relative. The page register has been written if that was necessary. */ -static int _regmap_raw_multi_reg_write(struct regmap *map, +int _regmap_raw_multi_reg_write(struct regmap *map, const struct reg_sequence *regs, size_t num_regs) { diff -ruw linux-4.4.115/drivers/base/regmap/regmap-debugfs.c linux-4.4.115-fbx/drivers/base/regmap/regmap-debugfs.c --- linux-4.4.115/drivers/base/regmap/regmap-debugfs.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/base/regmap/regmap-debugfs.c 2019-01-22 16:16:22.883240792 +0100 @@ -259,8 +259,7 @@ count, ppos); } -#undef REGMAP_ALLOW_WRITE_DEBUGFS -#ifdef REGMAP_ALLOW_WRITE_DEBUGFS +#ifdef CONFIG_REGMAP_ALLOW_WRITE_DEBUGFS /* * This can be dangerous especially when we have clients such as * PMICs, therefore don't provide any real compile time configuration option @@ -310,6 +309,67 @@ .llseek = default_llseek, }; +static ssize_t regmap_data_read_file(struct file *file, char __user *user_buf, + size_t count, loff_t *ppos) +{ + struct regmap *map = file->private_data; + int new_count; + + regmap_calc_tot_len(map, NULL, 0); + new_count = map->dump_count * map->debugfs_tot_len; + if (new_count > count) + new_count = count; + + if (*ppos == 0) + *ppos = map->dump_address * map->debugfs_tot_len; + else if (*ppos >= map->dump_address * map->debugfs_tot_len + + map->dump_count * map->debugfs_tot_len) + return 0; + return regmap_read_debugfs(map, 0, map->max_register, user_buf, + new_count, ppos); +} + +#ifdef CONFIG_REGMAP_ALLOW_WRITE_DEBUGFS +static ssize_t regmap_data_write_file(struct file *file, + const char __user *user_buf, + size_t count, loff_t *ppos) +{ + char buf[32]; + size_t buf_size; + char *start = buf; + unsigned long value; + struct regmap *map = file->private_data; + int ret; + + buf_size = min(count, (sizeof(buf)-1)); + if (copy_from_user(buf, user_buf, buf_size)) + return -EFAULT; + buf[buf_size] = 0; + + while (*start == ' ') + start++; + if (kstrtoul(start, 16, &value)) + return -EINVAL; + + /* Userspace has been fiddling around behind the kernel's back */ + add_taint(TAINT_USER, LOCKDEP_STILL_OK); + + ret = regmap_write(map, map->dump_address, value); + if (ret < 0) + return ret; + return buf_size; +} +#else +#define regmap_data_write_file NULL +#endif + +static const struct file_operations regmap_data_fops = { + .open = simple_open, + .read = regmap_data_read_file, + .write = regmap_data_write_file, + .llseek = default_llseek, +}; + static ssize_t regmap_range_read_file(struct file *file, char __user *user_buf, size_t count, loff_t *ppos) { @@ -595,7 +655,7 @@ if (map->max_register || regmap_readable(map, 0)) { umode_t registers_mode; -#if defined(REGMAP_ALLOW_WRITE_DEBUGFS) +#ifdef CONFIG_REGMAP_ALLOW_WRITE_DEBUGFS registers_mode = 0600; #else registers_mode = 0400; @@ -603,6 +663,15 @@ debugfs_create_file("registers", registers_mode, map->debugfs, map, ®map_map_fops); + + debugfs_create_x32("address", 0600, map->debugfs, + &map->dump_address); + map->dump_count = 1; + debugfs_create_u32("count", 0600, map->debugfs, + &map->dump_count); + debugfs_create_file("data", registers_mode, map->debugfs, + map, ®map_data_fops); + debugfs_create_file("access", 0400, map->debugfs, map, ®map_access_fops); } diff -ruw linux-4.4.115/drivers/base/regmap/regmap-spmi.c linux-4.4.115-fbx/drivers/base/regmap/regmap-spmi.c --- linux-4.4.115/drivers/base/regmap/regmap-spmi.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/base/regmap/regmap-spmi.c 2019-01-22 16:16:22.883240792 +0100 @@ -1,7 +1,7 @@ /* * Register map access API - SPMI support * - * Copyright (c) 2012-2013, The Linux Foundation. All rights reserved. + * Copyright (c) 2012-2013,2016 The Linux Foundation. All rights reserved. * * Based on regmap-i2c.c: * Copyright 2011 Wolfson Microelectronics plc diff -ruw linux-4.4.115/drivers/base/syscore.c linux-4.4.115-fbx/drivers/base/syscore.c --- linux-4.4.115/drivers/base/syscore.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/base/syscore.c 2019-01-22 16:16:22.883240792 +0100 @@ -11,6 +11,7 @@ #include #include #include +#include static LIST_HEAD(syscore_ops_list); static DEFINE_MUTEX(syscore_ops_lock); @@ -75,6 +76,8 @@ return 0; err_out: + log_suspend_abort_reason("System core suspend callback %pF failed", + ops->suspend); pr_err("PM: System core suspend callback %pF failed.\n", ops->suspend); list_for_each_entry_continue(ops, &syscore_ops_list, node) diff -ruw linux-4.4.115/drivers/bluetooth/hci_h4.c linux-4.4.115-fbx/drivers/bluetooth/hci_h4.c --- linux-4.4.115/drivers/bluetooth/hci_h4.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/bluetooth/hci_h4.c 2019-01-22 16:16:22.935241263 +0100 @@ -57,7 +57,7 @@ { struct h4_struct *h4; - BT_DBG("hu %p", hu); + BT_DBG("hu %pK", hu); h4 = kzalloc(sizeof(*h4), GFP_KERNEL); if (!h4) @@ -74,7 +74,7 @@ { struct h4_struct *h4 = hu->priv; - BT_DBG("hu %p", hu); + BT_DBG("hu %pK", hu); skb_queue_purge(&h4->txq); @@ -88,7 +88,7 @@ hu->priv = NULL; - BT_DBG("hu %p", hu); + BT_DBG("hu %pK", hu); skb_queue_purge(&h4->txq); @@ -105,7 +105,7 @@ { struct h4_struct *h4 = hu->priv; - BT_DBG("hu %p skb %p", hu, skb); + BT_DBG("hu %pK skb %pK", hu, skb); /* Prepend skb with frame type */ memcpy(skb_push(skb, 1), &bt_cb(skb)->pkt_type, 1); diff -ruw linux-4.4.115/drivers/bluetooth/hci_ldisc.c linux-4.4.115-fbx/drivers/bluetooth/hci_ldisc.c --- linux-4.4.115/drivers/bluetooth/hci_ldisc.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/bluetooth/hci_ldisc.c 2019-10-29 09:26:23.437201162 +0100 @@ -142,6 +142,8 @@ struct hci_dev *hdev = hu->hdev; struct sk_buff *skb; + BT_DBG("hu %pK hdev %pK tty %pK", hu, hdev, tty); + /* REVISIT: should we cope with bad skbs or ->write() returning * and error value ? */ @@ -205,7 +207,7 @@ /* Initialize device */ static int hci_uart_open(struct hci_dev *hdev) { - BT_DBG("%s %p", hdev->name, hdev); + BT_DBG("%s %pK", hdev->name, hdev); /* Nothing to do for UART driver */ return 0; @@ -217,7 +219,7 @@ struct hci_uart *hu = hci_get_drvdata(hdev); struct tty_struct *tty = hu->tty; - BT_DBG("hdev %p tty %p", hdev, tty); + BT_DBG("hdev %pK tty %pK", hdev, tty); if (hu->tx_skb) { kfree_skb(hu->tx_skb); hu->tx_skb = NULL; @@ -236,7 +238,7 @@ /* Close device */ static int hci_uart_close(struct hci_dev *hdev) { - BT_DBG("hdev %p", hdev); + BT_DBG("hdev %pK", hdev); hci_uart_flush(hdev); hdev->flush = NULL; @@ -441,7 +443,7 @@ { struct hci_uart *hu; - BT_DBG("tty %p", tty); + BT_DBG("tty %pK", tty); /* Error if the tty has no write op instead of leaving an exploitable hole */ @@ -483,7 +485,7 @@ struct hci_uart *hu = tty->disc_data; struct hci_dev *hdev; - BT_DBG("tty %p", tty); + BT_DBG("tty %pK", tty); /* Detach from the tty */ tty->disc_data = NULL; diff -ruw linux-4.4.115/drivers/bluetooth/Kconfig linux-4.4.115-fbx/drivers/bluetooth/Kconfig --- linux-4.4.115/drivers/bluetooth/Kconfig 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/bluetooth/Kconfig 2019-01-22 16:16:22.927241190 +0100 @@ -320,4 +320,32 @@ Say Y here to compile support for Texas Instrument's WiLink7 driver into the kernel or say M to compile it as module (btwilink). +config MSM_BT_POWER + tristate "MSM Bluetooth Power Control" + depends on ARCH_QCOM && RFKILL + default m + help + Provides a parameter to switch on/off power from PMIC + to Bluetooth device. + +config BTFM_SLIM + tristate "MSM Bluetooth/FM Slimbus Driver" + depends on MSM_BT_POWER + help + This enables BT/FM slimbus driver to get multiple audio channel. + This will make use of slimbus platform driver and slimbus codec + driver to communicate with slimbus machine driver and LPSS which + is Slimbus master. + + Slimbus slave initialization and configuration will be done through + this driver. + +config BTFM_SLIM_WCN3990 + tristate "MSM Bluetooth/FM WCN3990 Device" + depends on BTFM_SLIM + help + This enables specific driver handle for WCN3990 device. + It is designed to adapt any future BT/FM device to implement a specific + chip initialization process and control. + endmenu diff -ruw linux-4.4.115/drivers/bluetooth/Makefile linux-4.4.115-fbx/drivers/bluetooth/Makefile --- linux-4.4.115/drivers/bluetooth/Makefile 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/bluetooth/Makefile 2019-01-22 16:16:22.927241190 +0100 @@ -23,6 +23,11 @@ obj-$(CONFIG_BT_BCM) += btbcm.o obj-$(CONFIG_BT_RTL) += btrtl.o obj-$(CONFIG_BT_QCA) += btqca.o +obj-$(CONFIG_MSM_BT_POWER) += bluetooth-power.o + +obj-$(CONFIG_BTFM_SLIM) += btfm_slim.o +obj-$(CONFIG_BTFM_SLIM) += btfm_slim_codec.o +obj-$(CONFIG_BTFM_SLIM_WCN3990) += btfm_slim_wcn3990.o btmrvl-y := btmrvl_main.o btmrvl-$(CONFIG_DEBUG_FS) += btmrvl_debugfs.o diff -ruw linux-4.4.115/drivers/char/hw_random/Kconfig linux-4.4.115-fbx/drivers/char/hw_random/Kconfig --- linux-4.4.115/drivers/char/hw_random/Kconfig 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/char/hw_random/Kconfig 2019-01-22 16:16:22.967241553 +0100 @@ -333,10 +333,25 @@ If unsure, say Y. +config HW_RANDOM_MSM_LEGACY + tristate "Qualcomm MSM Random Number Generator support (LEGACY)" + depends on HW_RANDOM && ARCH_QCOM + select CRYPTO_AES + select CRYPTO_ECB + default n + ---help--- + This driver provides kernel-side support for the Random Number + Generator hardware found on Qualcomm MSM SoCs. + + To compile this driver as a module, choose M here: the + module will be called msm_rng. + + If unsure, say Y. + config HW_RANDOM_MSM tristate "Qualcomm SoCs Random Number Generator support" depends on HW_RANDOM && ARCH_QCOM - default HW_RANDOM + default n ---help--- This driver provides kernel-side support for the Random Number Generator hardware found on Qualcomm SoCs. diff -ruw linux-4.4.115/drivers/char/hw_random/Makefile linux-4.4.115-fbx/drivers/char/hw_random/Makefile --- linux-4.4.115/drivers/char/hw_random/Makefile 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/char/hw_random/Makefile 2019-01-22 16:16:22.967241553 +0100 @@ -32,4 +32,5 @@ obj-$(CONFIG_HW_RANDOM_MSM) += msm-rng.o obj-$(CONFIG_HW_RANDOM_ST) += st-rng.o obj-$(CONFIG_HW_RANDOM_XGENE) += xgene-rng.o +obj-$(CONFIG_HW_RANDOM_MSM_LEGACY) += msm_rng.o obj-$(CONFIG_HW_RANDOM_STM32) += stm32-rng.o diff -ruw linux-4.4.115/drivers/char/Kconfig linux-4.4.115-fbx/drivers/char/Kconfig --- linux-4.4.115/drivers/char/Kconfig 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/char/Kconfig 2019-10-29 09:26:23.441201201 +0100 @@ -48,6 +48,8 @@ source "drivers/tty/serial/Kconfig" +source "drivers/char/diag/Kconfig" + config TTY_PRINTK tristate "TTY driver to output user messages via printk" depends on EXPERT && TTY @@ -592,6 +594,16 @@ source "drivers/s390/char/Kconfig" +config MSM_SMD_PKT + bool "Enable device interface for some SMD packet ports" + default n + depends on MSM_SMD + help + smd_pkt driver provides the interface for the userspace clients + to communicate over smd via device nodes. This enable the + usersapce clients to read and write to some smd packets channel + for MSM chipset. + config TILE_SROM bool "Character-device access via hypervisor to the Tilera SPI ROM" depends on TILE @@ -605,5 +617,21 @@ source "drivers/char/xillybus/Kconfig" +config MSM_ADSPRPC + tristate "QTI ADSP RPC driver" + depends on MSM_SMD + help + Provides a communication mechanism that allows for clients to + make remote method invocations across processor boundary to + applications DSP processor. Say M if you want to enable this + module. + +config MSM_RDBG + tristate "QTI Remote debug driver" + help + Implements a shared memory based transport mechanism that allows + for a debugger running on a host PC to communicate with a remote + stub running on peripheral subsystems such as the ADSP, MODEM etc. + endmenu diff -ruw linux-4.4.115/drivers/char/Makefile linux-4.4.115-fbx/drivers/char/Makefile --- linux-4.4.115/drivers/char/Makefile 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/char/Makefile 2019-10-29 09:26:23.441201201 +0100 @@ -9,6 +9,7 @@ obj-$(CONFIG_VIRTIO_CONSOLE) += virtio_console.o obj-$(CONFIG_RAW_DRIVER) += raw.o obj-$(CONFIG_SGI_SNSC) += snsc.o snsc_event.o +obj-$(CONFIG_MSM_SMD_PKT) += msm_smd_pkt.o obj-$(CONFIG_MSPEC) += mspec.o obj-$(CONFIG_MMTIMER) += mmtimer.o obj-$(CONFIG_UV_MMTIMER) += uv_mmtimer.o @@ -59,4 +60,10 @@ js-rtc-y = rtc.o obj-$(CONFIG_TILE_SROM) += tile-srom.o +obj-$(CONFIG_DIAG_CHAR) += diag/ obj-$(CONFIG_XILLYBUS) += xillybus/ +obj-$(CONFIG_MSM_ADSPRPC) += adsprpc.o +ifdef CONFIG_COMPAT +obj-$(CONFIG_MSM_ADSPRPC) += adsprpc_compat.o +endif +obj-$(CONFIG_MSM_RDBG) += rdbg.o diff -ruw linux-4.4.115/drivers/char/misc.c linux-4.4.115-fbx/drivers/char/misc.c --- linux-4.4.115/drivers/char/misc.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/char/misc.c 2019-01-22 16:16:22.975241625 +0100 @@ -59,7 +59,7 @@ /* * Assigned numbers, used for dynamic minors */ -#define DYNAMIC_MINORS 64 /* like dynamic majors */ +#define DYNAMIC_MINORS 96 /* like dynamic majors */ static DECLARE_BITMAP(misc_minors, DYNAMIC_MINORS); #ifdef CONFIG_PROC_FS diff -ruw linux-4.4.115/drivers/clk/clk.c linux-4.4.115-fbx/drivers/clk/clk.c --- linux-4.4.115/drivers/clk/clk.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/clk/clk.c 2019-10-29 09:26:23.469201475 +0100 @@ -1,6 +1,7 @@ /* * Copyright (C) 2010-2011 Canonical Ltd * Copyright (C) 2011-2012 Linaro Ltd + * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as @@ -23,9 +24,12 @@ #include #include #include +#include #include "clk.h" +#if defined(CONFIG_COMMON_CLK) + static DEFINE_SPINLOCK(enable_lock); static DEFINE_MUTEX(prepare_lock); @@ -39,6 +43,13 @@ static HLIST_HEAD(clk_orphan_list); static LIST_HEAD(clk_notifier_list); +struct clk_handoff_vdd { + struct list_head list; + struct clk_vdd_class *vdd_class; +}; + +static LIST_HEAD(clk_handoff_vdd_list); + /*** private data structures ***/ struct clk_core { @@ -60,6 +71,8 @@ bool orphan; unsigned int enable_count; unsigned int prepare_count; + bool need_handoff_enable; + bool need_handoff_prepare; unsigned long min_rate; unsigned long max_rate; unsigned long accuracy; @@ -73,6 +86,9 @@ struct hlist_node debug_node; #endif struct kref ref; + struct clk_vdd_class *vdd_class; + unsigned long *rate_max; + int num_rate_max; }; #define CREATE_TRACE_POINTS @@ -172,6 +188,9 @@ return core->ops->is_enabled(core->hw); } +static void clk_core_unprepare(struct clk_core *core); +static void clk_core_disable(struct clk_core *core); + static void clk_unprepare_unused_subtree(struct clk_core *core) { struct clk_core *child; @@ -181,6 +200,19 @@ hlist_for_each_entry(child, &core->children, child_node) clk_unprepare_unused_subtree(child); + /* + * setting CLK_ENABLE_HAND_OFF flag triggers this conditional + * + * need_handoff_prepare implies this clk was already prepared by + * __clk_init. now we have a proper user, so unset the flag in our + * internal bookkeeping. See CLK_ENABLE_HAND_OFF flag in clk-provider.h + * for details. + */ + if (core->need_handoff_prepare) { + core->need_handoff_prepare = false; + clk_core_unprepare(core); + } + if (core->prepare_count) return; @@ -207,6 +239,21 @@ hlist_for_each_entry(child, &core->children, child_node) clk_disable_unused_subtree(child); + /* + * setting CLK_ENABLE_HAND_OFF flag triggers this conditional + * + * need_handoff_enable implies this clk was already enabled by + * __clk_init. now we have a proper user, so unset the flag in our + * internal bookkeeping. See CLK_ENABLE_HAND_OFF flag in clk-provider.h + * for details. + */ + if (core->need_handoff_enable) { + core->need_handoff_enable = false; + flags = clk_enable_lock(); + clk_core_disable(core); + clk_enable_unlock(flags); + } + flags = clk_enable_lock(); if (core->enable_count) @@ -241,9 +288,12 @@ } __setup("clk_ignore_unused", clk_ignore_unused_setup); +static int clk_unvote_vdd_level(struct clk_vdd_class *vdd_class, int level); + static int clk_disable_unused(void) { struct clk_core *core; + struct clk_handoff_vdd *v, *v_temp; if (clk_ignore_unused) { pr_warn("clk: Not disabling unused clocks\n"); @@ -264,6 +314,13 @@ hlist_for_each_entry(core, &clk_orphan_list, child_node) clk_unprepare_unused_subtree(core); + list_for_each_entry_safe(v, v_temp, &clk_handoff_vdd_list, list) { + clk_unvote_vdd_level(v->vdd_class, + v->vdd_class->num_levels - 1); + list_del(&v->list); + kfree(v); + }; + clk_prepare_unlock(); return 0; @@ -545,6 +602,26 @@ EXPORT_SYMBOL_GPL(clk_hw_set_rate_range); /* + * Aggregate the rate of all child nodes which are enabled and exclude the + * child node which requests for clk_aggregate_rate. + */ +unsigned long clk_aggregate_rate(struct clk_hw *hw, + const struct clk_core *parent) +{ + struct clk_core *child; + unsigned long aggre_rate = 0; + + hlist_for_each_entry(child, &parent->children, child_node) { + if (child->enable_count && + strcmp(child->name, hw->init->name)) + aggre_rate = max(child->rate, aggre_rate); + } + + return aggre_rate; +} +EXPORT_SYMBOL_GPL(clk_aggregate_rate); + +/* * Helper for finding best parent to provide a given frequency. This can be used * directly as a determine_rate callback (e.g. for a mux), or from a more * complex clock that may combine a mux with other operations. @@ -563,6 +640,217 @@ } EXPORT_SYMBOL_GPL(__clk_mux_determine_rate_closest); +/* + * Find the voltage level required for a given clock rate. + */ +static int clk_find_vdd_level(struct clk_core *clk, unsigned long rate) +{ + int level; + + for (level = 0; level < clk->num_rate_max; level++) + if (rate <= clk->rate_max[level]) + break; + + if (level == clk->num_rate_max) { + pr_err("Rate %lu for %s is greater than highest Fmax\n", rate, + clk->name); + return -EINVAL; + } + + return level; +} + +/* + * Update voltage level given the current votes. + */ +static int clk_update_vdd(struct clk_vdd_class *vdd_class) +{ + int level, rc = 0, i, ignore; + struct regulator **r = vdd_class->regulator; + int *uv = vdd_class->vdd_uv; + int n_reg = vdd_class->num_regulators; + int cur_lvl = vdd_class->cur_level; + int max_lvl = vdd_class->num_levels - 1; + int cur_base = cur_lvl * n_reg; + int new_base; + + /* aggregate votes */ + for (level = max_lvl; level > 0; level--) + if (vdd_class->level_votes[level]) + break; + + if (level == cur_lvl) + return 0; + + max_lvl = max_lvl * n_reg; + new_base = level * n_reg; + + for (i = 0; i < vdd_class->num_regulators; i++) { + pr_debug("Set Voltage level Min %d, Max %d\n", uv[new_base + i], + uv[max_lvl + i]); + rc = regulator_set_voltage(r[i], uv[new_base + i], + vdd_class->use_max_uV ? INT_MAX : uv[max_lvl + i]); + if (rc) + goto set_voltage_fail; + + if (cur_lvl == 0 || cur_lvl == vdd_class->num_levels) + rc = regulator_enable(r[i]); + else if (level == 0) + rc = regulator_disable(r[i]); + if (rc) + goto enable_disable_fail; + } + + if (vdd_class->set_vdd && !vdd_class->num_regulators) + rc = vdd_class->set_vdd(vdd_class, level); + + if (!rc) + vdd_class->cur_level = level; + + return rc; + +enable_disable_fail: + regulator_set_voltage(r[i], uv[cur_base + i], + vdd_class->use_max_uV ? INT_MAX : uv[max_lvl + i]); + +set_voltage_fail: + for (i--; i >= 0; i--) { + regulator_set_voltage(r[i], uv[cur_base + i], + vdd_class->use_max_uV ? INT_MAX : uv[max_lvl + i]); + if (cur_lvl == 0 || cur_lvl == vdd_class->num_levels) + regulator_disable(r[i]); + else if (level == 0) + ignore = regulator_enable(r[i]); + } + + return rc; +} + +/* + * Vote for a voltage level. + */ +static int clk_vote_vdd_level(struct clk_vdd_class *vdd_class, int level) +{ + int rc = 0; + + if (level >= vdd_class->num_levels) + return -EINVAL; + + mutex_lock(&vdd_class->lock); + + vdd_class->level_votes[level]++; + + rc = clk_update_vdd(vdd_class); + if (rc) + vdd_class->level_votes[level]--; + + mutex_unlock(&vdd_class->lock); + + return rc; +} + +/* + * Remove vote for a voltage level. + */ +static int clk_unvote_vdd_level(struct clk_vdd_class *vdd_class, int level) +{ + int rc = 0; + + if (level >= vdd_class->num_levels) + return -EINVAL; + + mutex_lock(&vdd_class->lock); + + if (WARN(!vdd_class->level_votes[level], + "Reference counts are incorrect for %s level %d\n", + vdd_class->class_name, level)) + goto out; + + vdd_class->level_votes[level]--; + + rc = clk_update_vdd(vdd_class); + if (rc) + vdd_class->level_votes[level]++; + +out: + mutex_unlock(&vdd_class->lock); + return rc; +} + +/* + * Vote for a voltage level corresponding to a clock's rate. + */ +static int clk_vote_rate_vdd(struct clk_core *core, unsigned long rate) +{ + int level; + + if (!core->vdd_class) + return 0; + + level = clk_find_vdd_level(core, rate); + if (level < 0) + return level; + + return clk_vote_vdd_level(core->vdd_class, level); +} + +/* + * Remove vote for a voltage level corresponding to a clock's rate. + */ +static void clk_unvote_rate_vdd(struct clk_core *core, unsigned long rate) +{ + int level; + + if (!core->vdd_class) + return; + + level = clk_find_vdd_level(core, rate); + if (level < 0) + return; + + clk_unvote_vdd_level(core->vdd_class, level); +} + +static bool clk_is_rate_level_valid(struct clk_core *core, unsigned long rate) +{ + int level; + + if (!core->vdd_class) + return true; + + level = clk_find_vdd_level(core, rate); + + return level >= 0; +} + +static int clk_vdd_class_init(struct clk_vdd_class *vdd) +{ + struct clk_handoff_vdd *v; + + if (vdd->skip_handoff) + return 0; + + list_for_each_entry(v, &clk_handoff_vdd_list, list) { + if (v->vdd_class == vdd) + return 0; + } + + pr_debug("voting for vdd_class %s\n", vdd->class_name); + + if (clk_vote_vdd_level(vdd, vdd->num_levels - 1)) + pr_err("failed to vote for %s\n", vdd->class_name); + + v = kmalloc(sizeof(*v), GFP_KERNEL); + if (!v) + return -ENOMEM; + + v->vdd_class = vdd; + + list_add_tail(&v->list, &clk_handoff_vdd_list); + + return 0; +} + /*** clk api ***/ static void clk_core_unprepare(struct clk_core *core) @@ -575,6 +863,9 @@ if (WARN_ON(core->prepare_count == 0)) return; + if (WARN_ON(core->prepare_count == 1 && core->flags & CLK_IS_CRITICAL)) + return; + if (--core->prepare_count > 0) return; @@ -586,6 +877,9 @@ core->ops->unprepare(core->hw); trace_clk_unprepare_complete(core); + + clk_unvote_rate_vdd(core, core->rate); + clk_core_unprepare(core->parent); } @@ -627,12 +921,19 @@ trace_clk_prepare(core); + ret = clk_vote_rate_vdd(core, core->rate); + if (ret) { + clk_core_unprepare(core->parent); + return ret; + } + if (core->ops->prepare) ret = core->ops->prepare(core->hw); trace_clk_prepare_complete(core); if (ret) { + clk_unvote_rate_vdd(core, core->rate); clk_core_unprepare(core->parent); return ret; } @@ -657,7 +958,7 @@ */ int clk_prepare(struct clk *clk) { - int ret; + int ret = 0; if (!clk) return 0; @@ -680,6 +981,9 @@ if (WARN_ON(core->enable_count == 0)) return; + if (WARN_ON(core->enable_count == 1 && core->flags & CLK_IS_CRITICAL)) + return; + if (--core->enable_count > 0) return; @@ -769,7 +1073,7 @@ int clk_enable(struct clk *clk) { unsigned long flags; - int ret; + int ret = 0; if (!clk) return 0; @@ -1379,6 +1683,9 @@ top = clk_calc_new_rates(parent, best_parent_rate); out: + if (!clk_is_rate_level_valid(core, rate)) + return NULL; + clk_calc_subtree(core, new_rate, parent, p_index); return top; @@ -1427,7 +1734,7 @@ * walk down a subtree and set the new rates notifying the rate * change on the way */ -static void clk_change_rate(struct clk_core *core) +static int clk_change_rate(struct clk_core *core) { struct clk_core *child; struct hlist_node *tmp; @@ -1435,6 +1742,7 @@ unsigned long best_parent_rate = 0; bool skip_set_rate = false; struct clk_core *old_parent; + int rc = 0; old_rate = core->rate; @@ -1443,6 +1751,15 @@ else if (core->parent) best_parent_rate = core->parent->rate; + trace_clk_set_rate(core, core->new_rate); + + /* Enforce vdd requirements for new frequency. */ + if (core->prepare_count) { + rc = clk_vote_rate_vdd(core, core->new_rate); + if (rc) + goto out; + } + if (core->new_parent && core->new_parent != core->parent) { old_parent = __clk_set_parent_before(core, core->new_parent); trace_clk_set_parent(core, core->new_parent); @@ -1460,13 +1777,19 @@ __clk_set_parent_after(core, core->new_parent, old_parent); } - trace_clk_set_rate(core, core->new_rate); - - if (!skip_set_rate && core->ops->set_rate) - core->ops->set_rate(core->hw, core->new_rate, best_parent_rate); + if (!skip_set_rate && core->ops->set_rate) { + rc = core->ops->set_rate(core->hw, core->new_rate, + best_parent_rate); + if (rc) + goto err_set_rate; + } trace_clk_set_rate_complete(core, core->new_rate); + /* Release vdd requirements for old frequency. */ + if (core->prepare_count) + clk_unvote_rate_vdd(core, old_rate); + core->rate = clk_recalc(core, best_parent_rate); if (core->notifier_count && old_rate != core->rate) @@ -1489,6 +1812,16 @@ /* handle the new child who might not be in core->children yet */ if (core->new_child) clk_change_rate(core->new_child); + + return rc; + +err_set_rate: + if (core->prepare_count) + clk_unvote_rate_vdd(core, core->new_rate); +out: + trace_clk_set_rate_complete(core, core->new_rate); + + return rc; } static int clk_core_set_rate_nolock(struct clk_core *core, @@ -1523,7 +1856,13 @@ } /* change the rates */ - clk_change_rate(top); + ret = clk_change_rate(top); + if (ret) { + pr_err("%s: failed to set %s rate\n", __func__, + top->name); + clk_propagate_rate_change(top, ABORT_RATE_CHANGE); + return ret; + } core->req_rate = req_rate; @@ -1953,6 +2292,18 @@ } EXPORT_SYMBOL_GPL(clk_is_match); +int clk_set_flags(struct clk *clk, unsigned long flags) +{ + if (!clk) + return 0; + + if (!clk->core->ops->set_flags) + return -EINVAL; + + return clk->core->ops->set_flags(clk->core->hw, flags); +} +EXPORT_SYMBOL_GPL(clk_set_flags); + /*** debugfs support ***/ #ifdef CONFIG_DEBUG_FS @@ -1960,6 +2311,7 @@ static struct dentry *rootdir; static int inited = 0; +static u32 debug_suspend; static DEFINE_MUTEX(clk_debug_lock); static HLIST_HEAD(clk_debug_list); @@ -1974,6 +2326,56 @@ NULL, }; +static void clk_state_subtree(struct clk_core *c) +{ + int vdd_level = 0; + struct clk_core *child; + + if (!c) + return; + + if (c->vdd_class) { + vdd_level = clk_find_vdd_level(c, c->rate); + if (vdd_level < 0) + vdd_level = 0; + } + + trace_clk_state(c->name, c->prepare_count, c->enable_count, + c->rate, vdd_level); + + hlist_for_each_entry(child, &c->children, child_node) + clk_state_subtree(child); +} + +static int clk_state_show(struct seq_file *s, void *data) +{ + struct clk_core *c; + struct hlist_head **lists = (struct hlist_head **)s->private; + + clk_prepare_lock(); + + for (; *lists; lists++) + hlist_for_each_entry(c, *lists, child_node) + clk_state_subtree(c); + + clk_prepare_unlock(); + + return 0; +} + + +static int clk_state_open(struct inode *inode, struct file *file) +{ + return single_open(file, clk_state_show, inode->i_private); +} + +static const struct file_operations clk_state_fops = { + .open = clk_state_open, + .read = seq_read, + .llseek = seq_lseek, + .release = single_release, +}; + static void clk_summary_show_one(struct seq_file *s, struct clk_core *c, int level) { @@ -2102,6 +2504,349 @@ .release = single_release, }; +static int clock_debug_rate_set(void *data, u64 val) +{ + struct clk_core *core = data; + int ret; + + ret = clk_set_rate(core->hw->clk, val); + if (ret) + pr_err("clk_set_rate(%lu) failed (%d)\n", + (unsigned long)val, ret); + + return ret; +} + +static int clock_debug_rate_get(void *data, u64 *val) +{ + struct clk_core *core = data; + + *val = core->hw->core->rate; + + return 0; +} + +DEFINE_SIMPLE_ATTRIBUTE(clock_rate_fops, clock_debug_rate_get, + clock_debug_rate_set, "%llu\n"); + +static ssize_t clock_parent_read(struct file *filp, char __user *ubuf, + size_t cnt, loff_t *ppos) +{ + char name[256] = {0}; + struct clk_core *core = filp->private_data; + struct clk_core *p = core->hw->core->parent; + + snprintf(name, sizeof(name), "%s\n", p ? p->name : "None\n"); + + return simple_read_from_buffer(ubuf, cnt, ppos, name, strlen(name)); +} + +static const struct file_operations clock_parent_fops = { + .open = simple_open, + .read = clock_parent_read, +}; + +static int clock_debug_enable_set(void *data, u64 val) +{ + struct clk_core *core = data; + int rc = 0; + + if (val) + rc = clk_prepare_enable(core->hw->clk); + else + clk_disable_unprepare(core->hw->clk); + + return rc; +} + +static int clock_debug_enable_get(void *data, u64 *val) +{ + struct clk_core *core = data; + int enabled = 0; + + enabled = core->enable_count; + + *val = enabled; + + return 0; +} + +DEFINE_SIMPLE_ATTRIBUTE(clock_enable_fops, clock_debug_enable_get, + clock_debug_enable_set, "%lld\n"); + +#define clock_debug_output(m, c, fmt, ...) \ +do { \ + if (m) \ + seq_printf(m, fmt, ##__VA_ARGS__); \ + else if (c) \ + pr_cont(fmt, ##__VA_ARGS__); \ + else \ + pr_info(fmt, ##__VA_ARGS__); \ +} while (0) + +/* + * clock_debug_print_enabled_debug_suspend() - Print names of enabled clocks + * during suspend. + */ +static void clock_debug_print_enabled_debug_suspend(struct seq_file *s) +{ + struct clk_core *core; + int cnt = 0; + + if (!mutex_trylock(&clk_debug_lock)) + return; + + clock_debug_output(s, 0, "Enabled clocks:\n"); + + hlist_for_each_entry(core, &clk_debug_list, debug_node) { + if (!core || !core->prepare_count) + continue; + + if (core->vdd_class) + clock_debug_output(s, 0, " %s:%u:%u [%ld, %d]", + core->name, core->prepare_count, + core->enable_count, core->rate, + clk_find_vdd_level(core, core->rate)); + + else + clock_debug_output(s, 0, " %s:%u:%u [%ld]", + core->name, core->prepare_count, + core->enable_count, core->rate); + cnt++; + } + + mutex_unlock(&clk_debug_lock); + + if (cnt) + clock_debug_output(s, 0, "Enabled clock count: %d\n", cnt); + else + clock_debug_output(s, 0, "No clocks enabled.\n"); +} + +static int clock_debug_print_clock(struct clk_core *c, struct seq_file *s) +{ + char *start = ""; + struct clk *clk; + + if (!c || !c->prepare_count) + return 0; + + clk = c->hw->clk; + + clock_debug_output(s, 0, "\t"); + + do { + if (clk->core->vdd_class) + clock_debug_output(s, 1, "%s%s:%u:%u [%ld, %d]", start, + clk->core->name, + clk->core->prepare_count, + clk->core->enable_count, + clk->core->rate, + clk_find_vdd_level(clk->core, clk->core->rate)); + else + clock_debug_output(s, 1, "%s%s:%u:%u [%ld]", start, + clk->core->name, + clk->core->prepare_count, + clk->core->enable_count, + clk->core->rate); + start = " -> "; + } while ((clk = clk_get_parent(clk))); + + clock_debug_output(s, 1, "\n"); + + return 1; +} + +/* + * clock_debug_print_enabled_clocks() - Print names of enabled clocks + */ +static void clock_debug_print_enabled_clocks(struct seq_file *s) +{ + struct clk_core *core; + int cnt = 0; + + clock_debug_output(s, 0, "Enabled clocks:\n"); + + mutex_lock(&clk_debug_lock); + + hlist_for_each_entry(core, &clk_debug_list, debug_node) + cnt += clock_debug_print_clock(core, s); + + mutex_unlock(&clk_debug_lock); + + if (cnt) + clock_debug_output(s, 0, "Enabled clock count: %d\n", cnt); + else + clock_debug_output(s, 0, "No clocks enabled.\n"); +} + +static int enabled_clocks_show(struct seq_file *s, void *unused) +{ + clock_debug_print_enabled_clocks(s); + + return 0; +} + +static int enabled_clocks_open(struct inode *inode, struct file *file) +{ + return single_open(file, enabled_clocks_show, inode->i_private); +} + +static const struct file_operations clk_enabled_list_fops = { + .open = enabled_clocks_open, + .read = seq_read, + .llseek = seq_lseek, + .release = seq_release, +}; + +void clk_debug_print_hw(struct clk_core *clk, struct seq_file *f) +{ + if (IS_ERR_OR_NULL(clk)) + return; + + clk_debug_print_hw(clk->parent, f); + + clock_debug_output(f, false, "%s\n", clk->name); + + if (!clk->ops->list_registers) + return; + + clk->ops->list_registers(f, clk->hw); +} +EXPORT_SYMBOL(clk_debug_print_hw); + +static int print_hw_show(struct seq_file *m, void *unused) +{ + struct clk_core *c = m->private; + + clk_debug_print_hw(c, m); + + return 0; +} + +static int print_hw_open(struct inode *inode, struct file *file) +{ + return single_open(file, print_hw_show, inode->i_private); +} + +static const struct file_operations clock_print_hw_fops = { + .open = print_hw_open, + .read = seq_read, + .llseek = seq_lseek, + .release = seq_release, +}; + +static int list_rates_show(struct seq_file *s, void *unused) +{ + struct clk_core *core = s->private; + int level = 0, i = 0; + unsigned long rate, rate_max = 0; + + /* Find max frequency supported within voltage constraints. */ + if (!core->vdd_class) { + rate_max = ULONG_MAX; + } else { + for (level = 0; level < core->num_rate_max; level++) + if (core->rate_max[level]) + rate_max = core->rate_max[level]; + } + + /* + * List supported frequencies <= rate_max. Higher frequencies may + * appear in the frequency table, but are not valid and should not + * be listed. + */ + while (!IS_ERR_VALUE(rate = + core->ops->list_rate(core->hw, i++, rate_max))) { + if (rate <= 0) + break; + if (rate <= rate_max) + seq_printf(s, "%lu\n", rate); + } + + return 0; +} + +static int list_rates_open(struct inode *inode, struct file *file) +{ + return single_open(file, list_rates_show, inode->i_private); +} + +static const struct file_operations list_rates_fops = { + .open = list_rates_open, + .read = seq_read, + .llseek = seq_lseek, + .release = seq_release, +}; + +static void clock_print_rate_max_by_level(struct seq_file *s, int level) +{ + struct clk_core *core = s->private; + struct clk_vdd_class *vdd_class = core->vdd_class; + int off, i, vdd_level, nregs = vdd_class->num_regulators; + + vdd_level = clk_find_vdd_level(core, core->rate); + + seq_printf(s, "%2s%10lu", vdd_level == level ? "[" : "", + core->rate_max[level]); + + for (i = 0; i < nregs; i++) { + off = nregs*level + i; + if (vdd_class->vdd_uv) + seq_printf(s, "%10u", vdd_class->vdd_uv[off]); + } + + if (vdd_level == level) + seq_puts(s, "]"); + + seq_puts(s, "\n"); +} + +static int rate_max_show(struct seq_file *s, void *unused) +{ + struct clk_core *core = s->private; + struct clk_vdd_class *vdd_class = core->vdd_class; + int level = 0, i, nregs = vdd_class->num_regulators; + char reg_name[10]; + + int vdd_level = clk_find_vdd_level(core, core->rate); + + if (vdd_level < 0) { + seq_printf(s, "could not find_vdd_level for %s, %ld\n", + core->name, core->rate); + return 0; + } + + seq_printf(s, "%12s", ""); + for (i = 0; i < nregs; i++) { + snprintf(reg_name, ARRAY_SIZE(reg_name), "reg %d", i); + seq_printf(s, "%10s", reg_name); + } + + seq_printf(s, "\n%12s", "freq"); + for (i = 0; i < nregs; i++) + seq_printf(s, "%10s", "uV"); + + seq_puts(s, "\n"); + + for (level = 0; level < core->num_rate_max; level++) + clock_print_rate_max_by_level(s, level); + + return 0; +} + +static int rate_max_open(struct inode *inode, struct file *file) +{ + return single_open(file, rate_max_show, inode->i_private); +} + +static const struct file_operations rate_max_fops = { + .open = rate_max_open, + .read = seq_read, + .llseek = seq_lseek, + .release = seq_release, +}; + static int clk_debug_create_one(struct clk_core *core, struct dentry *pdentry) { struct dentry *d; @@ -2118,11 +2863,21 @@ core->dentry = d; - d = debugfs_create_u32("clk_rate", S_IRUGO, core->dentry, - (u32 *)&core->rate); + d = debugfs_create_file("clk_rate", S_IRUGO, core->dentry, core, + &clock_rate_fops); if (!d) goto err_out; + if (core->ops->list_rate) { + if (!debugfs_create_file("clk_list_rates", + S_IRUGO, core->dentry, core, &list_rates_fops)) + goto err_out; + } + + if (core->vdd_class && !debugfs_create_file("clk_rate_max", + S_IRUGO, core->dentry, core, &rate_max_fops)) + goto err_out; + d = debugfs_create_u32("clk_accuracy", S_IRUGO, core->dentry, (u32 *)&core->accuracy); if (!d) @@ -2143,8 +2898,8 @@ if (!d) goto err_out; - d = debugfs_create_u32("clk_enable_count", S_IRUGO, core->dentry, - (u32 *)&core->enable_count); + d = debugfs_create_file("clk_enable_count", S_IRUGO, core->dentry, + core, &clock_enable_fops); if (!d) goto err_out; @@ -2153,6 +2908,16 @@ if (!d) goto err_out; + d = debugfs_create_file("clk_parent", S_IRUGO, core->dentry, core, + &clock_parent_fops); + if (!d) + goto err_out; + + d = debugfs_create_file("clk_print_regs", S_IRUGO, core->dentry, + core, &clock_print_hw_fops); + if (!d) + goto err_out; + if (core->ops->debug_init) { ret = core->ops->debug_init(core->hw, core->dentry); if (ret) @@ -2224,6 +2989,19 @@ } EXPORT_SYMBOL_GPL(clk_debugfs_add_file); +/* + * Print the names of all enabled clocks and their parents if + * debug_suspend is set from debugfs. + */ +void clock_debug_print_enabled(void) +{ + if (likely(!debug_suspend)) + return; + + clock_debug_print_enabled_debug_suspend(NULL); +} +EXPORT_SYMBOL_GPL(clock_debug_print_enabled); + /** * clk_debug_init - lazily populate the debugfs clk directory * @@ -2263,6 +3041,22 @@ if (!d) return -ENOMEM; + d = debugfs_create_file("clk_enabled_list", S_IRUGO, rootdir, + &clk_debug_list, &clk_enabled_list_fops); + if (!d) + return -ENOMEM; + + + d = debugfs_create_u32("debug_suspend", S_IRUGO | S_IWUSR, + rootdir, &debug_suspend); + if (!d) + return -ENOMEM; + + d = debugfs_create_file("trace_clocks", S_IRUGO, rootdir, &all_lists, + &clk_state_fops); + if (!d) + return -ENOMEM; + mutex_lock(&clk_debug_lock); hlist_for_each_entry(core, &clk_debug_list, debug_node) clk_debug_create_one(core, rootdir); @@ -2466,6 +3260,47 @@ if (core->ops->init) core->ops->init(core->hw); + if (core->flags & CLK_IS_CRITICAL) { + unsigned long flags; + + clk_core_prepare(core); + + flags = clk_enable_lock(); + clk_core_enable(core); + clk_enable_unlock(flags); + } + + /* + * enable clocks with the CLK_ENABLE_HAND_OFF flag set + * + * This flag causes the framework to enable the clock at registration + * time, which is sometimes necessary for clocks that would cause a + * system crash when gated (e.g. cpu, memory, etc). The prepare_count + * is migrated over to the first clk consumer to call clk_prepare(). + * Similarly the clk's enable_count is migrated to the first consumer + * to call clk_enable(). + */ + if (core->flags & CLK_ENABLE_HAND_OFF) { + unsigned long flags; + + /* + * Few clocks might have hardware gating which would be required + * to be ON before prepare/enabling the clocks. So check if the + * clock has been turned ON earlier and we should + * prepare/enable those clocks. + */ + if (clk_core_is_enabled(core)) { + core->need_handoff_prepare = true; + core->need_handoff_enable = true; + ret = clk_core_prepare(core); + if (ret) + goto out; + flags = clk_enable_lock(); + clk_core_enable(core); + clk_enable_unlock(flags); + } + } + kref_init(&core->ref); out: clk_prepare_unlock(); @@ -2545,8 +3380,19 @@ core->num_parents = hw->init->num_parents; core->min_rate = 0; core->max_rate = ULONG_MAX; + core->vdd_class = hw->init->vdd_class; + core->rate_max = hw->init->rate_max; + core->num_rate_max = hw->init->num_rate_max; hw->core = core; + if (core->vdd_class) { + ret = clk_vdd_class_init(core->vdd_class); + if (ret) { + pr_err("Failed to initialize vdd class\n"); + goto fail_parent_names; + } + } + /* allocate local copy in case parent_names is __initdata */ core->parent_names = kcalloc(core->num_parents, sizeof(char *), GFP_KERNEL); @@ -2901,6 +3747,8 @@ } EXPORT_SYMBOL_GPL(clk_notifier_unregister); +#endif /* CONFIG_COMMON_CLK */ + #ifdef CONFIG_OF /** * struct of_clk_provider - Clock provider registration structure @@ -2931,6 +3779,8 @@ } EXPORT_SYMBOL_GPL(of_clk_src_simple_get); +#if defined(CONFIG_COMMON_CLK) + struct clk *of_clk_src_onecell_get(struct of_phandle_args *clkspec, void *data) { struct clk_onecell_data *clk_data = data; @@ -2945,6 +3795,11 @@ } EXPORT_SYMBOL_GPL(of_clk_src_onecell_get); +#endif /* CONFIG_COMMON_CLK */ + +/* forward declaration */ +void of_clk_del_provider(struct device_node *np); + /** * of_clk_add_provider() - Register a clock provider for a node * @np: Device node pointer associated with clock provider @@ -3100,8 +3955,10 @@ else clk_name = NULL; } else { +#if defined(CONFIG_COMMON_CLK) clk_name = __clk_get_name(clk); clk_put(clk); +#endif } } @@ -3132,6 +3989,8 @@ } EXPORT_SYMBOL_GPL(of_clk_parent_fill); +#if defined(CONFIG_COMMON_CLK) + struct clock_provider { of_clk_init_cb_t clk_init_cb; struct device_node *np; @@ -3174,6 +4033,41 @@ } /** + * of_clk_detect_critical() - set CLK_IS_CRITICAL flag from Device Tree + * @np: Device node pointer associated with clock provider + * @index: clock index + * @flags: pointer to clk_core->flags + * + * Detects if the clock-critical property exists and, if so, sets the + * corresponding CLK_IS_CRITICAL flag. + * + * Do not use this function. It exists only for legacy Device Tree + * bindings, such as the one-clock-per-node style that are outdated. + * Those bindings typically put all clock data into .dts and the Linux + * driver has no clock data, thus making it impossible to set this flag + * correctly from the driver. Only those drivers may call + * of_clk_detect_critical from their setup functions. + * + * Return: error code or zero on success + */ +int of_clk_detect_critical(struct device_node *np, + int index, unsigned long *flags) +{ + struct property *prop; + const __be32 *cur; + uint32_t idx; + + if (!np || !flags) + return -EINVAL; + + of_property_for_each_u32(np, "clock-critical", prop, cur, idx) + if (index == idx) + *flags |= CLK_IS_CRITICAL; + + return 0; +} + +/** * of_clk_init() - Scan and init clock providers from the DT * @matches: array of compatible values and init functions for providers. * @@ -3240,4 +4134,7 @@ force = true; } } + +#endif /* CONFIG_COMMON_CLK */ + #endif diff -ruw linux-4.4.115/drivers/clk/clkdev.c linux-4.4.115-fbx/drivers/clk/clkdev.c --- linux-4.4.115/drivers/clk/clkdev.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/clk/clkdev.c 2019-01-22 16:16:23.007241915 +0100 @@ -27,7 +27,7 @@ static LIST_HEAD(clocks); static DEFINE_MUTEX(clocks_mutex); -#if defined(CONFIG_OF) && defined(CONFIG_COMMON_CLK) +#if defined(CONFIG_OF) static struct clk *__of_clk_get(struct device_node *np, int index, const char *dev_id, const char *con_id) { @@ -73,14 +73,10 @@ if (name) index = of_property_match_string(np, "clock-names", name); clk = __of_clk_get(np, index, dev_id, name); - if (!IS_ERR(clk)) { + if (!IS_ERR(clk)) break; - } else if (name && index >= 0) { - if (PTR_ERR(clk) != -EPROBE_DEFER) - pr_err("ERROR: could not get clock %s:%s(%i)\n", - np->full_name, name ? name : "", index); + else if (name && index >= 0) return clk; - } /* * No matching clock found on this node. If the parent node @@ -190,7 +186,7 @@ out: mutex_unlock(&clocks_mutex); - return cl ? clk : ERR_PTR(-ENOENT); + return cl ? cl->clk : ERR_PTR(-ENOENT); } EXPORT_SYMBOL(clk_get_sys); diff -ruw linux-4.4.115/drivers/clk/clk.h linux-4.4.115-fbx/drivers/clk/clk.h --- linux-4.4.115/drivers/clk/clk.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/clk/clk.h 2019-01-22 16:16:23.007241915 +0100 @@ -11,7 +11,7 @@ struct clk_hw; -#if defined(CONFIG_OF) && defined(CONFIG_COMMON_CLK) +#if defined(CONFIG_OF) struct clk *__of_clk_get_from_provider(struct of_phandle_args *clkspec, const char *dev_id, const char *con_id); #endif @@ -20,6 +20,11 @@ struct clk *__clk_create_clk(struct clk_hw *hw, const char *dev_id, const char *con_id); void __clk_free_clk(struct clk *clk); + +/* Debugfs API to print the enabled clocks */ +void clock_debug_print_enabled(void); +void clk_debug_print_hw(struct clk_core *clk, struct seq_file *f); + #else /* All these casts to avoid ifdefs in clkdev... */ static inline struct clk * diff -ruw linux-4.4.115/drivers/clk/Kconfig linux-4.4.115-fbx/drivers/clk/Kconfig --- linux-4.4.115/drivers/clk/Kconfig 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/clk/Kconfig 2019-01-22 16:16:22.995241806 +0100 @@ -198,3 +198,4 @@ source "drivers/clk/samsung/Kconfig" source "drivers/clk/tegra/Kconfig" +source "drivers/clk/msm/Kconfig" diff -ruw linux-4.4.115/drivers/clk/Makefile linux-4.4.115-fbx/drivers/clk/Makefile --- linux-4.4.115/drivers/clk/Makefile 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/clk/Makefile 2019-01-22 16:16:22.995241806 +0100 @@ -1,7 +1,7 @@ # common clock types obj-$(CONFIG_HAVE_CLK) += clk-devres.o obj-$(CONFIG_CLKDEV_LOOKUP) += clkdev.o -obj-$(CONFIG_COMMON_CLK) += clk.o +obj-$(CONFIG_OF) += clk.o obj-$(CONFIG_COMMON_CLK) += clk-divider.o obj-$(CONFIG_COMMON_CLK) += clk-fixed-factor.o obj-$(CONFIG_COMMON_CLK) += clk-fixed-rate.o @@ -84,3 +84,4 @@ obj-$(CONFIG_ARCH_ZX) += zte/ obj-$(CONFIG_ARCH_ZYNQ) += zynq/ obj-$(CONFIG_H8300) += h8300/ +obj-$(CONFIG_ARCH_QCOM) += msm/ diff -ruw linux-4.4.115/drivers/clk/qcom/Kconfig linux-4.4.115-fbx/drivers/clk/qcom/Kconfig --- linux-4.4.115/drivers/clk/qcom/Kconfig 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/clk/qcom/Kconfig 2019-01-22 16:16:23.027242096 +0100 @@ -2,6 +2,9 @@ bool select PM_GENERIC_DOMAINS if PM +config QCOM_RPMCC + bool + config COMMON_CLK_QCOM tristate "Support for Qualcomm's clock controllers" depends on OF @@ -9,6 +12,32 @@ select REGMAP_MMIO select RESET_CONTROLLER +config QCOM_CLK_RPM + tristate "RPM based Clock Controller" + depends on COMMON_CLK_QCOM && MFD_QCOM_RPM + select QCOM_RPMCC + help + The RPM (Resource Power Manager) is a dedicated hardware engine for + managing the shared SoC resources in order to keep the lowest power + profile. It communicates with other hardware subsystems via shared + memory and accepts clock requests, aggregates the requests and turns + the clocks on/off or scales them on demand. + Say Y if you want to support the clocks exposed by the RPM on + platforms such as apq8064, msm8660, msm8960 etc. + +config QCOM_CLK_SMD_RPM + tristate "RPM over SMD based Clock Controller" + depends on COMMON_CLK_QCOM + select QCOM_RPMCC + help + The RPM (Resource Power Manager) is a dedicated hardware engine for + managing the shared SoC resources in order to keep the lowest power + profile. It communicates with other hardware subsystems via shared + memory and accepts clock requests, aggregates the requests and turns + the clocks on/off or scales them on demand. + Say Y if you want to support the clocks exposed by the RPM on + platforms such as apq8016, apq8084, msm8974 etc. + config APQ_GCC_8084 tristate "APQ8084 Global Clock Controller" select QCOM_GDSC @@ -106,3 +135,109 @@ Support for the multimedia clock controller on msm8974 devices. Say Y if you want to support multimedia devices such as display, graphics, video encode/decode, camera, etc. + +config MSM_GCC_8996 + tristate "MSM8996 Global Clock Controller" + depends on COMMON_CLK_QCOM + help + Support for the global clock controller on msm8996 devices. + Say Y if you want to use peripheral devices such as UART, SPI, + i2c, USB, UFS, SD/eMMC, PCIe, etc. + +config MSM_MMCC_8996 + tristate "MSM8996 Multimedia Clock Controller" + select MSM_GCC_8996 + depends on COMMON_CLK_QCOM + help + Support for the multimedia clock controller on msm8996 devices. + Say Y if you want to support multimedia devices such as display, + graphics, video encode/decode, camera, etc. + +config MSM_GCC_660 + tristate "SDM660 Global Clock Controller" + select QCOM_GDSC + depends on COMMON_CLK_QCOM + ---help--- + Support for the global clock controller on Qualcomm Technologies, Inc + SDM660 devices. + Say Y if you want to use peripheral devices such as UART, SPI, I2C, + USB, UFS, SD/eMMC, PCIe, etc. + +config MSM_GPUCC_660 + tristate "SDM660 Graphics Clock Controller" + select MSM_GCC_660 + depends on COMMON_CLK_QCOM + help + Support for the graphics clock controller on Qualcomm Technologies, Inc + SDM660 devices. + Say Y if you want to support graphics controller devices which will + be required to enable those device. + +config MSM_MMCC_660 + tristate "SDM660 Multimedia Clock Controller" + select MSM_GCC_660 + depends on COMMON_CLK_QCOM + help + Support for the multimedia clock controller on Qualcomm Technologies, Inc + SDM660 devices. + Say Y if you want to support multimedia devices such as display, + video encode/decode, camera, etc. + +config QCOM_HFPLL + tristate "High-Frequency PLL (HFPLL) Clock Controller" + depends on COMMON_CLK_QCOM + help + Support for the high-frequency PLLs present on MSM devices. + Say Y if you want to support CPU frequency scaling on devices + such as MSM8974, APQ8084, etc. + +config KPSS_XCC + tristate "KPSS Clock Controller" + depends on COMMON_CLK_QCOM + help + Support for the Krait ACC and GCC clock controllers. Say Y + if you want to support CPU frequency scaling on devices such + as MSM8960, APQ8064, etc. + +config KRAITCC + tristate "Krait Clock Controller" + depends on COMMON_CLK_QCOM && ARM + select KRAIT_CLOCKS + help + Support for the Krait CPU clocks on MSM devices. + Say Y if you want to support CPU frequency scaling. + +config KRAIT_CLOCKS + bool + select KRAIT_L2_ACCESSORS + +config QCOM_A53 + tristate "A53 Clock Controller" + depends on COMMON_CLK_QCOM + help + Support for the A53 clock controller on MSM devices. + Say Y if you want to support CPU frequency scaling on devices + such as MSM8916. + +config CLOCK_CPU_OSM + tristate "OSM CPU Clock Controller" + depends on COMMON_CLK_QCOM + help + Support for the osm clock controller. + Operating State Manager (OSM) is a hardware engine used by some + Qualcomm Technologies, Inc. (QTI) SoCs to manage frequency and + voltage scaling in hardware. OSM is capable of controlling + frequency and voltage requests for multiple clusters via the + existence of multiple OSM domains. + Say Y if you want to support osm clocks. + +config CLOCK_QPNP_DIV + tristate "QPNP PMIC clkdiv driver" + depends on COMMON_CLK_QCOM && SPMI + help + This driver supports the clkdiv functionality on the Qualcomm + Technologies, Inc. QPNP PMIC. It configures the frequency of + clkdiv outputs on the PMIC. These clocks are typically wired + through alternate functions on gpio pins. + +source "drivers/clk/qcom/mdss/Kconfig" diff -ruw linux-4.4.115/drivers/clk/qcom/Makefile linux-4.4.115-fbx/drivers/clk/qcom/Makefile --- linux-4.4.115/drivers/clk/qcom/Makefile 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/clk/qcom/Makefile 2019-01-22 16:16:23.027242096 +0100 @@ -2,14 +2,19 @@ clk-qcom-y += common.o clk-qcom-y += clk-regmap.o +clk-qcom-y += clk-alpha-pll.o clk-qcom-y += clk-pll.o clk-qcom-y += clk-rcg.o clk-qcom-y += clk-rcg2.o clk-qcom-y += clk-branch.o clk-qcom-y += clk-regmap-divider.o clk-qcom-y += clk-regmap-mux.o -clk-qcom-y += reset.o -clk-qcom-$(CONFIG_QCOM_GDSC) += gdsc.o +clk-qcom-y += clk-regmap-mux-div.o +clk-qcom-$(CONFIG_KRAIT_CLOCKS) += clk-krait.o +clk-qcom-y += clk-hfpll.o +clk-qcom-y += reset.o clk-voter.o +clk-qcom-y += clk-dummy.o clk-debug.o +clk-qcom-$(CONFIG_QCOM_GDSC) += gdsc.o gdsc-regulator.o obj-$(CONFIG_APQ_GCC_8084) += gcc-apq8084.o obj-$(CONFIG_APQ_MMCC_8084) += mmcc-apq8084.o @@ -20,5 +25,20 @@ obj-$(CONFIG_MSM_GCC_8960) += gcc-msm8960.o obj-$(CONFIG_MSM_LCC_8960) += lcc-msm8960.o obj-$(CONFIG_MSM_GCC_8974) += gcc-msm8974.o +obj-$(CONFIG_MSM_GCC_8996) += gcc-msm8996.o +obj-$(CONFIG_MSM_GCC_660) += gcc-sdm660.o obj-$(CONFIG_MSM_MMCC_8960) += mmcc-msm8960.o obj-$(CONFIG_MSM_MMCC_8974) += mmcc-msm8974.o +obj-$(CONFIG_MSM_MMCC_8996) += mmcc-msm8996.o +obj-$(CONFIG_MSM_GPUCC_660) += gpucc-sdm660.o +obj-$(CONFIG_MSM_MMCC_660) += mmcc-sdm660.o +obj-$(CONFIG_KPSS_XCC) += kpss-xcc.o +obj-$(CONFIG_QCOM_HFPLL) += hfpll.o +obj-$(CONFIG_KRAITCC) += krait-cc.o +obj-$(CONFIG_QCOM_A53) += clk-a53.o +obj-$(CONFIG_QCOM_CLK_RPM) += clk-rpm.o +obj-$(CONFIG_QCOM_CLK_SMD_RPM) += clk-smd-rpm.o +obj-$(CONFIG_CLOCK_CPU_OSM) += clk-cpu-osm.o +obj-$(CONFIG_CLOCK_QPNP_DIV) += clk-qpnp-div.o + +obj-y += mdss/ diff -ruw linux-4.4.115/drivers/clocksource/arm_arch_timer.c linux-4.4.115-fbx/drivers/clocksource/arm_arch_timer.c --- linux-4.4.115/drivers/clocksource/arm_arch_timer.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/clocksource/arm_arch_timer.c 2019-10-29 09:26:23.489201671 +0100 @@ -25,6 +25,7 @@ #include #include +#include #include #include @@ -83,20 +84,20 @@ struct arch_timer *timer = to_arch_timer(clk); switch (reg) { case ARCH_TIMER_REG_CTRL: - writel_relaxed(val, timer->base + CNTP_CTL); + writel_relaxed_no_log(val, timer->base + CNTP_CTL); break; case ARCH_TIMER_REG_TVAL: - writel_relaxed(val, timer->base + CNTP_TVAL); + writel_relaxed_no_log(val, timer->base + CNTP_TVAL); break; } } else if (access == ARCH_TIMER_MEM_VIRT_ACCESS) { struct arch_timer *timer = to_arch_timer(clk); switch (reg) { case ARCH_TIMER_REG_CTRL: - writel_relaxed(val, timer->base + CNTV_CTL); + writel_relaxed_no_log(val, timer->base + CNTV_CTL); break; case ARCH_TIMER_REG_TVAL: - writel_relaxed(val, timer->base + CNTV_TVAL); + writel_relaxed_no_log(val, timer->base + CNTV_TVAL); break; } } else { @@ -114,20 +115,20 @@ struct arch_timer *timer = to_arch_timer(clk); switch (reg) { case ARCH_TIMER_REG_CTRL: - val = readl_relaxed(timer->base + CNTP_CTL); + val = readl_relaxed_no_log(timer->base + CNTP_CTL); break; case ARCH_TIMER_REG_TVAL: - val = readl_relaxed(timer->base + CNTP_TVAL); + val = readl_relaxed_no_log(timer->base + CNTP_TVAL); break; } } else if (access == ARCH_TIMER_MEM_VIRT_ACCESS) { struct arch_timer *timer = to_arch_timer(clk); switch (reg) { case ARCH_TIMER_REG_CTRL: - val = readl_relaxed(timer->base + CNTV_CTL); + val = readl_relaxed_no_log(timer->base + CNTV_CTL); break; case ARCH_TIMER_REG_TVAL: - val = readl_relaxed(timer->base + CNTV_TVAL); + val = readl_relaxed_no_log(timer->base + CNTV_TVAL); break; } } else { @@ -328,12 +329,16 @@ /* Disable user access to the timers and the physical counter */ /* Also disable virtual event stream */ cntkctl &= ~(ARCH_TIMER_USR_PT_ACCESS_EN - | ARCH_TIMER_USR_VT_ACCESS_EN | ARCH_TIMER_VIRT_EVT_EN | ARCH_TIMER_USR_PCT_ACCESS_EN); /* Enable user access to the virtual counter */ + cntkctl |= ARCH_TIMER_USR_VT_ACCESS_EN; + + if (IS_ENABLED(CONFIG_ARM_ARCH_TIMER_VCT_ACCESS)) cntkctl |= ARCH_TIMER_USR_VCT_ACCESS_EN; + else + cntkctl &= ~ARCH_TIMER_USR_VCT_ACCESS_EN; arch_timer_set_cntkctl(cntkctl); } @@ -371,7 +376,8 @@ if (!acpi_disabled || of_property_read_u32(np, "clock-frequency", &arch_timer_rate)) { if (cntbase) - arch_timer_rate = readl_relaxed(cntbase + CNTFRQ); + arch_timer_rate = readl_relaxed_no_log(cntbase + + CNTFRQ); else arch_timer_rate = arch_timer_get_cntfrq(); } @@ -408,9 +414,9 @@ u32 vct_lo, vct_hi, tmp_hi; do { - vct_hi = readl_relaxed(arch_counter_base + CNTVCT_HI); - vct_lo = readl_relaxed(arch_counter_base + CNTVCT_LO); - tmp_hi = readl_relaxed(arch_counter_base + CNTVCT_HI); + vct_hi = readl_relaxed_no_log(arch_counter_base + CNTVCT_HI); + vct_lo = readl_relaxed_no_log(arch_counter_base + CNTVCT_LO); + tmp_hi = readl_relaxed_no_log(arch_counter_base + CNTVCT_HI); } while (vct_hi != tmp_hi); return ((u64) vct_hi << 32) | vct_lo; @@ -686,6 +692,7 @@ arch_timer_banner(arch_timers_present); arch_counter_register(arch_timers_present); arch_timer_arch_init(); + clocksource_select_force(); } static void __init arch_timer_init(void) @@ -756,7 +763,7 @@ return; } - cnttidr = readl_relaxed(cntctlbase + CNTTIDR); + cnttidr = readl_relaxed_no_log(cntctlbase + CNTTIDR); iounmap(cntctlbase); /* @@ -804,6 +811,7 @@ arch_timer_detect_rate(base, np); arch_timer_mem_register(base, irq); arch_timer_common_init(); + get_pct_hook_init(); } CLOCKSOURCE_OF_DECLARE(armv7_arch_timer_mem, "arm,armv7-timer-mem", arch_timer_mem_init); diff -ruw linux-4.4.115/drivers/clocksource/Kconfig linux-4.4.115-fbx/drivers/clocksource/Kconfig --- linux-4.4.115/drivers/clocksource/Kconfig 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/clocksource/Kconfig 2019-01-22 16:16:23.067242458 +0100 @@ -158,6 +158,23 @@ This must be disabled for hardware validation purposes to detect any hardware anomalies of missing events. +config MSM_TIMER_LEAP + bool "ARCH TIMER counter rollover" + default n + depends on ARM_ARCH_TIMER && ARM64 + help + This option enables a check for least significant 32 bits of + counter rollover. On every counter read if least significant + 32 bits are set, reread counter. + +config ARM_ARCH_TIMER_VCT_ACCESS + bool "Support for ARM architected timer virtual counter access in userspace" + default !ARM64 + depends on ARM_ARCH_TIMER + help + This option enables support for reading the ARM architected timer's + virtual counter in userspace. + config ARM_GLOBAL_TIMER bool select CLKSRC_OF if OF diff -ruw linux-4.4.115/drivers/cpufreq/cpufreq.c linux-4.4.115-fbx/drivers/cpufreq/cpufreq.c --- linux-4.4.115/drivers/cpufreq/cpufreq.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/cpufreq/cpufreq.c 2019-10-29 09:26:23.493201710 +0100 @@ -29,6 +29,9 @@ #include #include #include +#ifdef CONFIG_SMP +#include +#endif #include static LIST_HEAD(cpufreq_policy_list); @@ -127,6 +130,7 @@ */ static BLOCKING_NOTIFIER_HEAD(cpufreq_policy_notifier_list); static struct srcu_notifier_head cpufreq_transition_notifier_list; +struct atomic_notifier_head cpufreq_govinfo_notifier_list; static bool init_cpufreq_transition_notifier_list_called; static int __init init_cpufreq_transition_notifier_list(void) @@ -137,6 +141,15 @@ } pure_initcall(init_cpufreq_transition_notifier_list); +static bool init_cpufreq_govinfo_notifier_list_called; +static int __init init_cpufreq_govinfo_notifier_list(void) +{ + ATOMIC_INIT_NOTIFIER_HEAD(&cpufreq_govinfo_notifier_list); + init_cpufreq_govinfo_notifier_list_called = true; + return 0; +} +pure_initcall(init_cpufreq_govinfo_notifier_list); + static int off __read_mostly; static int cpufreq_disabled(void) { @@ -154,6 +167,12 @@ } EXPORT_SYMBOL_GPL(have_governor_per_policy); +bool cpufreq_driver_is_slow(void) +{ + return !(cpufreq_driver->flags & CPUFREQ_DRIVER_FAST); +} +EXPORT_SYMBOL_GPL(cpufreq_driver_is_slow); + struct kobject *get_governor_parent_kobj(struct cpufreq_policy *policy) { if (have_governor_per_policy()) @@ -347,6 +366,50 @@ #endif } +/********************************************************************* + * FREQUENCY INVARIANT CPU CAPACITY * + *********************************************************************/ + +static DEFINE_PER_CPU(unsigned long, freq_scale) = SCHED_CAPACITY_SCALE; +static DEFINE_PER_CPU(unsigned long, max_freq_scale) = SCHED_CAPACITY_SCALE; + +static void +scale_freq_capacity(struct cpufreq_policy *policy, struct cpufreq_freqs *freqs) +{ + unsigned long cur = freqs ? freqs->new : policy->cur; + unsigned long scale = (cur << SCHED_CAPACITY_SHIFT) / policy->max; + struct cpufreq_cpuinfo *cpuinfo = &policy->cpuinfo; + int cpu; + + pr_debug("cpus %*pbl cur/cur max freq %lu/%u kHz freq scale %lu\n", + cpumask_pr_args(policy->cpus), cur, policy->max, scale); + + for_each_cpu(cpu, policy->cpus) + per_cpu(freq_scale, cpu) = scale; + + if (freqs) + return; + + scale = (policy->max << SCHED_CAPACITY_SHIFT) / cpuinfo->max_freq; + + pr_debug("cpus %*pbl cur max/max freq %u/%u kHz max freq scale %lu\n", + cpumask_pr_args(policy->cpus), policy->max, cpuinfo->max_freq, + scale); + + for_each_cpu(cpu, policy->cpus) + per_cpu(max_freq_scale, cpu) = scale; +} + +unsigned long cpufreq_scale_freq_capacity(struct sched_domain *sd, int cpu) +{ + return per_cpu(freq_scale, cpu); +} + +unsigned long cpufreq_scale_max_freq_capacity(int cpu) +{ + return per_cpu(max_freq_scale, cpu); +} + static void __cpufreq_notify_transition(struct cpufreq_policy *policy, struct cpufreq_freqs *freqs, unsigned int state) { @@ -423,6 +486,9 @@ void cpufreq_freq_transition_begin(struct cpufreq_policy *policy, struct cpufreq_freqs *freqs) { +#ifdef CONFIG_SMP + int cpu; +#endif /* * Catch double invocations of _begin() which lead to self-deadlock. @@ -450,6 +516,12 @@ spin_unlock(&policy->transition_lock); + scale_freq_capacity(policy, freqs); +#ifdef CONFIG_SMP + for_each_cpu(cpu, policy->cpus) + trace_cpu_capacity(capacity_curr_of(cpu), cpu); +#endif + cpufreq_notify_transition(policy, freqs, CPUFREQ_PRECHANGE); } EXPORT_SYMBOL_GPL(cpufreq_freq_transition_begin); @@ -469,6 +541,38 @@ } EXPORT_SYMBOL_GPL(cpufreq_freq_transition_end); +/** + * cpufreq_driver_resolve_freq - Map a target frequency to a driver-supported + * one. + * @target_freq: target frequency to resolve. + * + * The target to driver frequency mapping is cached in the policy. + * + * Return: Lowest driver-supported frequency greater than or equal to the + * given target_freq, subject to policy (min/max) and driver limitations. + */ +unsigned int cpufreq_driver_resolve_freq(struct cpufreq_policy *policy, + unsigned int target_freq) +{ + target_freq = clamp_val(target_freq, policy->min, policy->max); + policy->cached_target_freq = target_freq; + + if (cpufreq_driver->target_index) { + int idx, rv; + + rv = cpufreq_frequency_table_target(policy, policy->freq_table, + target_freq, + CPUFREQ_RELATION_L, + &idx); + if (rv) + return target_freq; + policy->cached_resolved_idx = idx; + return policy->freq_table[idx].frequency; + } + + return target_freq; +} +EXPORT_SYMBOL_GPL(cpufreq_driver_resolve_freq); /********************************************************************* * SYSFS INTERFACE * @@ -1001,7 +1105,8 @@ if (has_target()) { ret = __cpufreq_governor(policy, CPUFREQ_GOV_STOP); if (ret) { - pr_err("%s: Failed to stop governor\n", __func__); + pr_err("%s: Failed to stop governor for CPU%u, policy CPU%u\n", + __func__, cpu, policy->cpu); return ret; } } @@ -1016,7 +1121,8 @@ ret = __cpufreq_governor(policy, CPUFREQ_GOV_LIMITS); if (ret) { - pr_err("%s: Failed to start governor\n", __func__); + pr_err("%s: Failed to start governor for CPU%u, policy CPU%u\n", + __func__, cpu, policy->cpu); return ret; } } @@ -1329,7 +1435,8 @@ if (has_target()) { int ret = __cpufreq_governor(policy, CPUFREQ_GOV_STOP); if (ret) - pr_err("%s: Failed to stop governor\n", __func__); + pr_err("%s: Failed to stop governor for CPU%u\n", + __func__, cpu); } down_write(&policy->rwsem); @@ -1379,7 +1486,8 @@ if (has_target()) { int ret = __cpufreq_governor(policy, CPUFREQ_GOV_POLICY_EXIT); if (ret) - pr_err("%s: Failed to exit governor\n", __func__); + pr_err("%s: Failed to start governor for CPU%u, policy CPU%u\n", + __func__, cpu, policy->cpu); } /* @@ -1708,7 +1816,8 @@ if (cpufreq_disabled()) return -EINVAL; - WARN_ON(!init_cpufreq_transition_notifier_list_called); + WARN_ON(!init_cpufreq_transition_notifier_list_called || + !init_cpufreq_govinfo_notifier_list_called); switch (list) { case CPUFREQ_TRANSITION_NOTIFIER: @@ -1719,6 +1828,10 @@ ret = blocking_notifier_chain_register( &cpufreq_policy_notifier_list, nb); break; + case CPUFREQ_GOVINFO_NOTIFIER: + ret = atomic_notifier_chain_register( + &cpufreq_govinfo_notifier_list, nb); + break; default: ret = -EINVAL; } @@ -1753,6 +1866,10 @@ ret = blocking_notifier_chain_unregister( &cpufreq_policy_notifier_list, nb); break; + case CPUFREQ_GOVINFO_NOTIFIER: + ret = atomic_notifier_chain_unregister( + &cpufreq_govinfo_notifier_list, nb); + break; default: ret = -EINVAL; } @@ -1865,15 +1982,6 @@ pr_debug("target for CPU %u: %u kHz, relation %u, requested %u kHz\n", policy->cpu, target_freq, relation, old_target_freq); - /* - * This might look like a redundant call as we are checking it again - * after finding index. But it is left intentionally for cases where - * exactly same freq is called again and so we can save on few function - * calls. - */ - if (target_freq == policy->cur) - return 0; - /* Save last value to restore later on errors */ policy->restore_freq = policy->cur; @@ -2131,8 +2239,11 @@ blocking_notifier_call_chain(&cpufreq_policy_notifier_list, CPUFREQ_NOTIFY, new_policy); + scale_freq_capacity(new_policy, NULL); + policy->min = new_policy->min; policy->max = new_policy->max; + trace_cpu_frequency_limits(policy->max, policy->min, policy->cpu); pr_debug("new min and max freqs are %u - %u kHz\n", policy->min, policy->max); @@ -2259,6 +2370,9 @@ { unsigned int cpu = (unsigned long)hcpu; + if (!cpufreq_driver) + return NOTIFY_OK; + switch (action & ~CPU_TASKS_FROZEN) { case CPU_ONLINE: cpufreq_online(cpu); @@ -2425,6 +2539,9 @@ pr_debug("trying to register driver %s\n", driver_data->name); + /* Register for hotplug notifers before blocking hotplug. */ + register_hotcpu_notifier(&cpufreq_cpu_notifier); + /* Protect against concurrent CPU online/offline. */ get_online_cpus(); @@ -2457,8 +2574,7 @@ goto err_if_unreg; } - register_hotcpu_notifier(&cpufreq_cpu_notifier); - pr_debug("driver %s up and running\n", driver_data->name); + pr_info("driver %s up and running\n", driver_data->name); out: put_online_cpus(); @@ -2491,7 +2607,7 @@ if (!cpufreq_driver || (driver != cpufreq_driver)) return -EINVAL; - pr_debug("unregistering driver %s\n", driver->name); + pr_info("unregistering driver %s\n", driver->name); /* Protect against concurrent cpu hotplug */ get_online_cpus(); diff -ruw linux-4.4.115/drivers/cpufreq/Kconfig linux-4.4.115-fbx/drivers/cpufreq/Kconfig --- linux-4.4.115/drivers/cpufreq/Kconfig 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/cpufreq/Kconfig 2019-10-29 09:26:23.493201710 +0100 @@ -102,6 +102,33 @@ Be aware that not all cpufreq drivers support the conservative governor. If unsure have a look at the help section of the driver. Fallback governor will be the performance governor. + +config CPU_FREQ_DEFAULT_GOV_INTERACTIVE + bool "interactive" + select CPU_FREQ_GOV_INTERACTIVE + help + Use the CPUFreq governor 'interactive' as default. This allows + you to get a full dynamic cpu frequency capable system by simply + loading your cpufreq low-level hardware driver, using the + 'interactive' governor for latency-sensitive workloads. + +config CPU_FREQ_DEFAULT_GOV_SCHED + bool "sched" + select CPU_FREQ_GOV_SCHED + help + Use the CPUfreq governor 'sched' as default. This scales + cpu frequency using CPU utilization estimates from the + scheduler. + +config CPU_FREQ_DEFAULT_GOV_SCHEDUTIL + bool "schedutil" + depends on SMP + select CPU_FREQ_GOV_SCHEDUTIL + select CPU_FREQ_GOV_PERFORMANCE + help + Use the 'schedutil' CPUFreq governor by default. If unsure, + have a look at the help section of that governor. The fallback + governor will be 'performance'. endchoice config CPU_FREQ_GOV_PERFORMANCE @@ -159,6 +186,20 @@ If in doubt, say N. +config CPU_FREQ_GOV_INTERACTIVE + bool "'interactive' cpufreq policy governor" + help + 'interactive' - This driver adds a dynamic cpufreq policy governor + designed for latency-sensitive workloads. + + This governor attempts to reduce the latency of clock + increases so that the system is more responsive to + interactive workloads. + + For details, take a look at linux/Documentation/cpu-freq. + + If in doubt, say N. + config CPU_FREQ_GOV_CONSERVATIVE tristate "'conservative' cpufreq governor" depends on CPU_FREQ @@ -183,6 +224,34 @@ If in doubt, say N. +config CPU_BOOST + tristate "Event base short term CPU freq boost" + depends on CPU_FREQ + help + This driver boosts the frequency of one or more CPUs based on + various events that might occur in the system. As of now, the + events it reacts to are: + - Migration of important threads from one CPU to another. + + If in doubt, say N. + +config CPU_FREQ_GOV_SCHEDUTIL + bool "'schedutil' cpufreq policy governor" + depends on CPU_FREQ && SMP + select CPU_FREQ_GOV_ATTR_SET + select IRQ_WORK + help + This governor makes decisions based on the utilization data provided + by the scheduler. It sets the CPU frequency to be proportional to + the utilization/capacity ratio coming from the scheduler. If the + utilization is frequency-invariant, the new frequency is also + proportional to the maximum available frequency. If that is not the + case, it is proportional to the current frequency of the CPU. The + frequency tipping point is at utilization/capacity equal to 80% in + both cases. + + If in doubt, say N. + comment "CPU frequency scaling drivers" config CPUFREQ_DT diff -ruw linux-4.4.115/drivers/cpufreq/Kconfig.arm linux-4.4.115-fbx/drivers/cpufreq/Kconfig.arm --- linux-4.4.115/drivers/cpufreq/Kconfig.arm 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/cpufreq/Kconfig.arm 2019-01-22 16:16:23.075242531 +0100 @@ -255,3 +255,10 @@ support for its operation. If in doubt, say N. + +config CPU_FREQ_MSM + bool "MSM CPUFreq support" + depends on CPU_FREQ + default y + help + This enables the CPUFreq driver for Qualcomm CPUs. diff -ruw linux-4.4.115/drivers/cpufreq/Makefile linux-4.4.115-fbx/drivers/cpufreq/Makefile --- linux-4.4.115/drivers/cpufreq/Makefile 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/cpufreq/Makefile 2019-10-29 09:26:23.493201710 +0100 @@ -1,5 +1,5 @@ # CPUfreq core -obj-$(CONFIG_CPU_FREQ) += cpufreq.o freq_table.o +obj-$(CONFIG_CPU_FREQ) += cpufreq.o freq_table.o cpufreq_governor_attr_set.o # CPUfreq stats obj-$(CONFIG_CPU_FREQ_STAT) += cpufreq_stats.o @@ -10,7 +10,9 @@ obj-$(CONFIG_CPU_FREQ_GOV_USERSPACE) += cpufreq_userspace.o obj-$(CONFIG_CPU_FREQ_GOV_ONDEMAND) += cpufreq_ondemand.o obj-$(CONFIG_CPU_FREQ_GOV_CONSERVATIVE) += cpufreq_conservative.o +obj-$(CONFIG_CPU_FREQ_GOV_INTERACTIVE) += cpufreq_interactive.o obj-$(CONFIG_CPU_FREQ_GOV_COMMON) += cpufreq_governor.o +obj-$(CONFIG_CPU_BOOST) += cpu-boost.o obj-$(CONFIG_CPUFREQ_DT) += cpufreq-dt.o @@ -77,7 +79,7 @@ obj-$(CONFIG_ARM_TEGRA124_CPUFREQ) += tegra124-cpufreq.o obj-$(CONFIG_ARM_VEXPRESS_SPC_CPUFREQ) += vexpress-spc-cpufreq.o obj-$(CONFIG_ACPI_CPPC_CPUFREQ) += cppc_cpufreq.o - +obj-$(CONFIG_CPU_FREQ_MSM) += qcom-cpufreq.o ################################################################################## # PowerPC platform drivers diff -ruw linux-4.4.115/drivers/cpuidle/cpuidle.c linux-4.4.115-fbx/drivers/cpuidle/cpuidle.c --- linux-4.4.115/drivers/cpuidle/cpuidle.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/cpuidle/cpuidle.c 2019-01-22 16:16:23.095242712 +0100 @@ -193,7 +193,7 @@ } /* Take note of the planned idle state. */ - sched_idle_set_state(target_state); + sched_idle_set_state(target_state, index); trace_cpu_idle_rcuidle(index, dev->cpu); time_start = ktime_get(); @@ -206,7 +206,7 @@ trace_cpu_idle_rcuidle(PWR_EVENT_EXIT, dev->cpu); /* The cpu is no longer idle or about to enter idle. */ - sched_idle_set_state(NULL); + sched_idle_set_state(NULL, -1); if (broadcast) { if (WARN_ON_ONCE(!irqs_disabled())) @@ -614,16 +614,31 @@ #ifdef CONFIG_SMP +static void smp_callback(void *v) +{ + /* we already woke the CPU up, nothing more to do */ +} + /* * This function gets called when a part of the kernel has a new latency - * requirement. This means we need to get all processors out of their C-state, - * and then recalculate a new suitable C-state. Just do a cross-cpu IPI; that - * wakes them all right up. + * requirement. This means we need to get only those processors out of their + * C-state for which qos requirement is changed, and then recalculate a new + * suitable C-state. Just do a cross-cpu IPI; that wakes them all right up. */ static int cpuidle_latency_notify(struct notifier_block *b, unsigned long l, void *v) { - wake_up_all_idle_cpus(); + struct cpumask cpus; + + if (v) + cpumask_andnot(&cpus, v, cpu_isolated_mask); + else + cpumask_andnot(&cpus, cpu_online_mask, cpu_isolated_mask); + + preempt_disable(); + smp_call_function_many(&cpus, smp_callback, NULL, 1); + preempt_enable(); + return NOTIFY_OK; } diff -ruw linux-4.4.115/drivers/cpuidle/governors/menu.c linux-4.4.115-fbx/drivers/cpuidle/governors/menu.c --- linux-4.4.115/drivers/cpuidle/governors/menu.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/cpuidle/governors/menu.c 2019-01-22 16:16:23.095242712 +0100 @@ -178,7 +178,12 @@ /* for higher loadavg, we are more reluctant */ - mult += 2 * get_loadavg(load); + /* + * this doesn't work as intended - it is almost always 0, but can + * sometimes, depending on workload, spike very high into the hundreds + * even when the average cpu load is under 10%. + */ + /* mult += 2 * get_loadavg(); */ /* for IO wait tasks (per cpu!) we add 5x each */ mult += 10 * nr_iowaiters; diff -ruw linux-4.4.115/drivers/cpuidle/Makefile linux-4.4.115-fbx/drivers/cpuidle/Makefile --- linux-4.4.115/drivers/cpuidle/Makefile 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/cpuidle/Makefile 2019-01-22 16:16:23.091242676 +0100 @@ -27,3 +27,4 @@ # POWERPC drivers obj-$(CONFIG_PSERIES_CPUIDLE) += cpuidle-pseries.o obj-$(CONFIG_POWERNV_CPUIDLE) += cpuidle-powernv.o +obj-$(CONFIG_MSM_PM) += lpm-levels.o lpm-levels-of.o lpm-workarounds.o diff -ruw linux-4.4.115/drivers/crypto/Kconfig linux-4.4.115-fbx/drivers/crypto/Kconfig --- linux-4.4.115/drivers/crypto/Kconfig 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/crypto/Kconfig 2019-01-22 16:16:23.095242712 +0100 @@ -346,6 +346,64 @@ Select this to offload Samsung S5PV210 or S5PC110, Exynos from AES algorithms execution. +config CRYPTO_DEV_QCE50 + bool + +config FIPS_ENABLE + bool "FIPS140-2 compliant build" + default n + help + This flag is used to make current build FIPS140-2 + compliant. This flag will enable the patch of code + which will perform this task. Please select Y here + to enable. + +config CRYPTO_DEV_QCRYPTO + tristate "Qualcomm Crypto accelerator" + select CRYPTO_DES + select CRYPTO_ALGAPI + select CRYPTO_AUTHENC + select CRYPTO_BLKCIPHER + default n + help + This driver supports Qualcomm crypto acceleration. + To compile this driver as a module, choose M here: the + module will be called qcrypto. + +config CRYPTO_DEV_QCOM_MSM_QCE + tristate "Qualcomm Crypto Engine (QCE) module" + select CRYPTO_DEV_QCE50 if ARCH_APQ8084 || ARCH_MSM8916 || ARCH_MSM8994 || ARCH_MSM8996 || ARCH_MSM8992 || ARCH_MSMTITANIUM || ARCH_MSM8909 || ARCH_MSM8998 || ARCH_SDM660 || ARCH_SDM630 + default n + help + This driver supports Qualcomm Crypto Engine in MSM7x30, MSM8660 + MSM8x55, MSM8960, MSM9615, MSM8916, MSM8994, MSM8996, FSM9900, + MSMTITANINUM, APQ8084, MSM8998, SDM660 and SDM630. + + To compile this driver as a module, choose M here: the + For MSM7x30 MSM8660 and MSM8x55 the module is called qce + For MSM8960, APQ8064 and MSM9615 the module is called qce40 + For MSM8974, MSM8916, MSM8994, MSM8996, MSM8992, MSMTITANIUM, + APQ8084, MSM8998, SDM660 and SDM630 the module is called qce50. + +config CRYPTO_DEV_QCEDEV + tristate "QCEDEV Interface to CE module" + default n + help + This driver supports Qualcomm QCEDEV Crypto in MSM7x30, MSM8660, + MSM8960, MSM9615, APQ8064, MSM8974, MSM8916, MSM8994, MSM8996, + APQ8084, MSM8998, SDM660, SDM630. This exposes the + interface to the QCE hardware accelerator via IOCTLs. + + To compile this driver as a module, choose M here: the + module will be called qcedev. + +config CRYPTO_DEV_OTA_CRYPTO + tristate "OTA Crypto module" + help + This driver supports Qualcomm OTA Crypto in the FSM9xxx. + To compile this driver as a module, choose M here: the + module will be called ota_crypto. + config CRYPTO_DEV_NX bool "Support for IBM PowerPC Nest (NX) cryptographic acceleration" depends on PPC64 @@ -498,4 +556,9 @@ To compile this driver as a module, choose M here: the module will be called sun4i-ss. +if ARCH_QCOM +source drivers/crypto/msm/Kconfig +endif # ARCH_QCOM + + endif # CRYPTO_HW diff -ruw linux-4.4.115/drivers/crypto/Makefile linux-4.4.115-fbx/drivers/crypto/Makefile --- linux-4.4.115/drivers/crypto/Makefile 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/crypto/Makefile 2019-01-22 16:16:23.095242712 +0100 @@ -29,3 +29,4 @@ obj-$(CONFIG_CRYPTO_DEV_QCE) += qce/ obj-$(CONFIG_CRYPTO_DEV_VMX) += vmx/ obj-$(CONFIG_CRYPTO_DEV_SUN4I_SS) += sunxi-ss/ +obj-$(CONFIG_ARCH_QCOM) += msm/ diff -ruw linux-4.4.115/drivers/devfreq/devfreq.c linux-4.4.115-fbx/drivers/devfreq/devfreq.c --- linux-4.4.115/drivers/devfreq/devfreq.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/devfreq/devfreq.c 2019-10-29 09:26:23.513201906 +0100 @@ -69,11 +69,34 @@ } /** + * devfreq_set_freq_limits() - Set min and max frequency from freq_table + * @devfreq: the devfreq instance + */ +static void devfreq_set_freq_limits(struct devfreq *devfreq) +{ + int idx; + unsigned long min = ~0, max = 0; + + if (!devfreq->profile->freq_table) + return; + + for (idx = 0; idx < devfreq->profile->max_state; idx++) { + if (min > devfreq->profile->freq_table[idx]) + min = devfreq->profile->freq_table[idx]; + if (max < devfreq->profile->freq_table[idx]) + max = devfreq->profile->freq_table[idx]; + } + + devfreq->min_freq = min; + devfreq->max_freq = max; +} + +/** * devfreq_get_freq_level() - Lookup freq_table for the frequency * @devfreq: the devfreq instance * @freq: the target frequency */ -static int devfreq_get_freq_level(struct devfreq *devfreq, unsigned long freq) +int devfreq_get_freq_level(struct devfreq *devfreq, unsigned long freq) { int lev; @@ -83,6 +106,7 @@ return -EINVAL; } +EXPORT_SYMBOL(devfreq_get_freq_level); /** * devfreq_update_status() - Update statistics of devfreq behavior @@ -172,7 +196,7 @@ return -EINVAL; /* Reevaluate the proper frequency */ - err = devfreq->governor->get_target_freq(devfreq, &freq); + err = devfreq->governor->get_target_freq(devfreq, &freq, &flags); if (err) return err; @@ -486,6 +510,7 @@ devfreq->profile->max_state, GFP_KERNEL); devfreq->last_stat_updated = jiffies; + devfreq_set_freq_limits(devfreq); dev_set_name(&devfreq->dev, "%s", dev_name(dev)); err = device_register(&devfreq->dev); @@ -536,7 +561,6 @@ return -EINVAL; device_unregister(&devfreq->dev); - put_device(&devfreq->dev); return 0; } @@ -782,7 +806,7 @@ struct devfreq *df = to_devfreq(dev); int ret; char str_governor[DEVFREQ_NAME_LEN + 1]; - struct devfreq_governor *governor; + const struct devfreq_governor *governor, *prev_gov; ret = sscanf(buf, "%" __stringify(DEVFREQ_NAME_LEN) "s", str_governor); if (ret != 1) @@ -807,12 +831,21 @@ goto out; } } + prev_gov = df->governor; df->governor = governor; strncpy(df->governor_name, governor->name, DEVFREQ_NAME_LEN); ret = df->governor->event_handler(df, DEVFREQ_GOV_START, NULL); - if (ret) + if (ret) { dev_warn(dev, "%s: Governor %s not started(%d)\n", __func__, df->governor->name, ret); + if (prev_gov) { + df->governor = prev_gov; + strncpy(df->governor_name, prev_gov->name, + DEVFREQ_NAME_LEN); + df->governor->event_handler(df, DEVFREQ_GOV_START, + NULL); + } + } out: mutex_unlock(&devfreq_list_lock); @@ -969,19 +1002,26 @@ struct devfreq *df = to_devfreq(d); struct device *dev = df->dev.parent; struct dev_pm_opp *opp; + unsigned int i = 0, max_state = df->profile->max_state; + bool use_opp; ssize_t count = 0; unsigned long freq = 0; rcu_read_lock(); - do { + use_opp = dev_pm_opp_get_opp_count(dev) > 0; + while (use_opp || (!use_opp && i < max_state)) { + if (use_opp) { opp = dev_pm_opp_find_freq_ceil(dev, &freq); if (IS_ERR(opp)) break; + } else { + freq = df->profile->freq_table[i++]; + } count += scnprintf(&buf[count], (PAGE_SIZE - count - 2), "%lu ", freq); freq++; - } while (1); + } rcu_read_unlock(); /* Truncate the trailing space */ diff -ruw linux-4.4.115/drivers/devfreq/governor.h linux-4.4.115-fbx/drivers/devfreq/governor.h --- linux-4.4.115/drivers/devfreq/governor.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/devfreq/governor.h 2019-01-22 16:16:23.135243074 +0100 @@ -4,6 +4,8 @@ * Copyright (C) 2011 Samsung Electronics * MyungJoo Ham * + * Copyright (c) 2018 The Linux Foundation. All rights reserved. + * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. @@ -25,9 +27,6 @@ #define DEVFREQ_GOV_SUSPEND 0x4 #define DEVFREQ_GOV_RESUME 0x5 -/* Caution: devfreq->lock must be locked before calling update_devfreq */ -extern int update_devfreq(struct devfreq *devfreq); - extern void devfreq_monitor_start(struct devfreq *devfreq); extern void devfreq_monitor_stop(struct devfreq *devfreq); extern void devfreq_monitor_suspend(struct devfreq *devfreq); @@ -38,4 +37,5 @@ extern int devfreq_add_governor(struct devfreq_governor *governor); extern int devfreq_remove_governor(struct devfreq_governor *governor); +extern int devfreq_get_freq_level(struct devfreq *devfreq, unsigned long freq); #endif /* _GOVERNOR_H */ diff -ruw linux-4.4.115/drivers/devfreq/governor_performance.c linux-4.4.115-fbx/drivers/devfreq/governor_performance.c --- linux-4.4.115/drivers/devfreq/governor_performance.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/devfreq/governor_performance.c 2019-01-22 16:16:23.135243074 +0100 @@ -14,7 +14,8 @@ #include "governor.h" static int devfreq_performance_func(struct devfreq *df, - unsigned long *freq) + unsigned long *freq, + u32 *flag) { /* * target callback should be able to get floor value as @@ -31,13 +32,26 @@ unsigned int event, void *data) { int ret = 0; + unsigned long freq; - if (event == DEVFREQ_GOV_START) { mutex_lock(&devfreq->lock); + freq = devfreq->previous_freq; + switch (event) { + case DEVFREQ_GOV_START: + devfreq->profile->target(devfreq->dev.parent, + &freq, + DEVFREQ_FLAG_WAKEUP_MAXFREQ); + /* fall through */ + case DEVFREQ_GOV_RESUME: ret = update_devfreq(devfreq); - mutex_unlock(&devfreq->lock); + break; + case DEVFREQ_GOV_SUSPEND: + devfreq->profile->target(devfreq->dev.parent, + &freq, + DEVFREQ_FLAG_WAKEUP_MAXFREQ); + break; } - + mutex_unlock(&devfreq->lock); return ret; } diff -ruw linux-4.4.115/drivers/devfreq/governor_powersave.c linux-4.4.115-fbx/drivers/devfreq/governor_powersave.c --- linux-4.4.115/drivers/devfreq/governor_powersave.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/devfreq/governor_powersave.c 2019-01-22 16:16:23.135243074 +0100 @@ -14,7 +14,8 @@ #include "governor.h" static int devfreq_powersave_func(struct devfreq *df, - unsigned long *freq) + unsigned long *freq, + u32 *flag) { /* * target callback should be able to get ceiling value as @@ -29,7 +30,7 @@ { int ret = 0; - if (event == DEVFREQ_GOV_START) { + if (event == DEVFREQ_GOV_START || event == DEVFREQ_GOV_RESUME) { mutex_lock(&devfreq->lock); ret = update_devfreq(devfreq); mutex_unlock(&devfreq->lock); diff -ruw linux-4.4.115/drivers/devfreq/governor_simpleondemand.c linux-4.4.115-fbx/drivers/devfreq/governor_simpleondemand.c --- linux-4.4.115/drivers/devfreq/governor_simpleondemand.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/devfreq/governor_simpleondemand.c 2019-01-22 16:16:23.135243074 +0100 @@ -19,7 +19,8 @@ #define DFSO_UPTHRESHOLD (90) #define DFSO_DOWNDIFFERENCTIAL (5) static int devfreq_simple_ondemand_func(struct devfreq *df, - unsigned long *freq) + unsigned long *freq, + u32 *flag) { int err; struct devfreq_dev_status *stat; @@ -28,6 +29,7 @@ unsigned int dfso_downdifferential = DFSO_DOWNDIFFERENCTIAL; struct devfreq_simple_ondemand_data *data = df->data; unsigned long max = (df->max_freq) ? df->max_freq : UINT_MAX; + unsigned long min = (df->min_freq) ? df->min_freq : 0; err = devfreq_update_stats(df); if (err) @@ -45,18 +47,31 @@ dfso_upthreshold < dfso_downdifferential) return -EINVAL; - /* Assume MAX if it is going to be divided by zero */ - if (stat->total_time == 0) { - *freq = max; - return 0; - } - /* Prevent overflow */ if (stat->busy_time >= (1 << 24) || stat->total_time >= (1 << 24)) { stat->busy_time >>= 7; stat->total_time >>= 7; } + if (data && data->simple_scaling) { + if (stat->busy_time * 100 > + stat->total_time * dfso_upthreshold) + *freq = max; + else if (stat->busy_time * 100 < + stat->total_time * + (dfso_upthreshold - dfso_downdifferential)) + *freq = min; + else + *freq = df->previous_freq; + return 0; + } + + /* Assume MAX if it is going to be divided by zero */ + if (stat->total_time == 0) { + *freq = max; + return 0; + } + /* Set MAX if it's busy enough */ if (stat->busy_time * 100 > stat->total_time * dfso_upthreshold) { diff -ruw linux-4.4.115/drivers/devfreq/governor_userspace.c linux-4.4.115-fbx/drivers/devfreq/governor_userspace.c --- linux-4.4.115/drivers/devfreq/governor_userspace.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/devfreq/governor_userspace.c 2019-01-22 16:16:23.135243074 +0100 @@ -22,7 +22,8 @@ bool valid; }; -static int devfreq_userspace_func(struct devfreq *df, unsigned long *freq) +static int devfreq_userspace_func(struct devfreq *df, unsigned long *freq, + u32 *flag) { struct userspace_data *data = df->data; diff -ruw linux-4.4.115/drivers/devfreq/Kconfig linux-4.4.115-fbx/drivers/devfreq/Kconfig --- linux-4.4.115/drivers/devfreq/Kconfig 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/devfreq/Kconfig 2019-01-22 16:16:23.131243038 +0100 @@ -64,6 +64,114 @@ Otherwise, the governor does not change the frequnecy given at the initialization. +config DEVFREQ_GOV_QCOM_ADRENO_TZ + tristate "Qualcom Adreno Trustzone" + depends on QCOM_KGSL && QCOM_SCM + help + Trustzone based governor for the Adreno GPU. + Sets the frequency using a "on-demand" algorithm. + This governor is unlikely to be useful for other devices. + +config DEVFREQ_GOV_CPUFREQ + tristate "CPUfreq" + depends on CPU_FREQ + help + Chooses frequency based on the online CPUs' current frequency and a + CPU frequency to device frequency mapping table(s). This governor + can be useful for controlling devices such as DDR, cache, CCI, etc. + +config QCOM_BIMC_BWMON + tristate "QCOM BIMC Bandwidth monitor hardware" + depends on ARCH_QCOM + help + The BIMC Bandwidth monitor hardware allows for monitoring the + traffic coming from each master port connected to the BIMC. It also + has the capability to raise an IRQ when the count exceeds a + programmable limit. + +config DEVFREQ_GOV_QCOM_GPUBW_MON + tristate "GPU BW voting governor" + depends on DEVFREQ_GOV_QCOM_ADRENO_TZ + help + QTI GPU governor for GPU bus bandwidth voting. + This governor works together with QTI Adreno Trustzone governor, + and select bus frequency votes using an "on-demand" alorithm. + This governor is unlikely to be useful for non-QTI devices. + +config ARMBW_HWMON + tristate "ARM PMU Bandwidth monitor hardware" + depends on ARCH_QCOM + help + The PMU present on these ARM cores allow for the use of counters to + monitor the traffic coming from each core to the bus. It also has the + capability to raise an IRQ when the counter overflows, which can be + used to get an IRQ when the count exceeds a certain value + +config ARM_MEMLAT_MON + tristate "ARM CPU Memory Latency monitor hardware" + depends on ARCH_QCOM + help + The PMU present on these ARM cores allow for the use of counters to + monitor the memory latency characteristics of an ARM CPU workload. + This driver uses these counters to implement the APIs needed by + the mem_latency devfreq governor. + +config QCOMCCI_HWMON + tristate "QCOM CCI Cache monitor hardware" + depends on ARCH_QCOM + help + QCOM CCI has additional PMU counters that can be used to monitor + cache requests. QCOM CCI hardware monitor device configures these + registers to monitor cache and inform governor. It can also set an + IRQ when count exceeds a programmable limit. + +config QCOM_M4M_HWMON + tristate "QCOM M4M cache monitor hardware" + depends on ARCH_QCOM + help + QCOM M4M has counters that can be used to monitor requests coming to + M4M. QCOM M4M hardware monitor device programs corresponding registers + to monitor cache and inform governor. It can also set an IRQ when + count exceeds a programmable limit. + +config DEVFREQ_GOV_QCOM_BW_HWMON + tristate "HW monitor based governor for device BW" + depends on QCOM_BIMC_BWMON + help + HW monitor based governor for device to DDR bandwidth voting. + This governor sets the CPU BW vote by using BIMC counters to monitor + the CPU's use of DDR. Since this uses target specific counters it + can conflict with existing profiling tools. This governor is unlikely + to be useful for non-QCOM devices. + +config DEVFREQ_GOV_QCOM_CACHE_HWMON + tristate "HW monitor based governor for cache frequency" + help + HW monitor based governor for cache frequency scaling. This + governor sets the cache frequency by using PM counters to monitor the + CPU's use of cache. Since this governor uses some of the PM counters + it can conflict with existing profiling tools. This governor is + unlikely to be useful for other devices. + +config DEVFREQ_GOV_SPDM_HYP + bool "QCOM SPDM Hypervisor Governor" + depends on ARCH_QCOM + help + Hypervisor based governor for CPU bandwidth voting + for QCOM chipsets. + Sets the frequency using a "on-demand" algorithm. + This governor is unlikely to be useful for other devices. + +config DEVFREQ_GOV_MEMLAT + tristate "HW monitor based governor for device BW" + depends on ARM_MEMLAT_MON + help + HW monitor based governor for device to DDR bandwidth voting. + This governor sets the CPU BW vote based on stats obtained from memalat + monitor if it determines that a workload is memory latency bound. Since + this uses target specific counters it can conflict with existing profiling + tools. + comment "DEVFREQ Drivers" config ARM_EXYNOS4_BUS_DEVFREQ @@ -98,6 +206,48 @@ It reads ACTMON counters of memory controllers and adjusts the operating frequencies and voltages with OPP support. +config DEVFREQ_SIMPLE_DEV + tristate "Device driver for simple clock device with no status info" + select DEVFREQ_GOV_PERFORMANCE + select DEVFREQ_GOV_POWERSAVE + select DEVFREQ_GOV_USERSPACE + select DEVFREQ_GOV_CPUFREQ + help + Device driver for simple devices that control their frequency using + clock APIs and don't have any form of status reporting. + +config QCOM_DEVFREQ_DEVBW + bool "QCOM DEVFREQ device for device master <-> slave IB/AB BW voting" + depends on ARCH_QCOM + select DEVFREQ_GOV_PERFORMANCE + select DEVFREQ_GOV_POWERSAVE + select DEVFREQ_GOV_USERSPACE + select DEVFREQ_GOV_CPUFREQ + default n + help + Different devfreq governors use this devfreq device to make CPU to + DDR IB/AB bandwidth votes. This driver provides a SoC topology + agnostic interface to so that some of the devfreq governors can be + shared across SoCs. + +config SPDM_SCM + bool "QCOM SPDM SCM based call support" + depends on DEVFREQ_SPDM + help + SPDM driver support the dcvs algorithm logic being accessed via + scm or hvc calls. This adds the support for SPDM interaction to + tz via SCM based call. If not selected then Hypervior interaction + will be activated. + +config DEVFREQ_SPDM + bool "QCOM SPDM based bandwidth voting" + depends on ARCH_QCOM + select DEVFREQ_GOV_SPDM_HYP + help + This adds the support for SPDM based bandwidth voting on QCOM chipsets. + This driver allows any SPDM based client to vote for bandwidth. + Used with the QCOM SPDM Hypervisor Governor. + source "drivers/devfreq/event/Kconfig" endif # PM_DEVFREQ diff -ruw linux-4.4.115/drivers/devfreq/Makefile linux-4.4.115-fbx/drivers/devfreq/Makefile --- linux-4.4.115/drivers/devfreq/Makefile 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/devfreq/Makefile 2019-01-22 16:16:23.131243038 +0100 @@ -4,11 +4,27 @@ obj-$(CONFIG_DEVFREQ_GOV_PERFORMANCE) += governor_performance.o obj-$(CONFIG_DEVFREQ_GOV_POWERSAVE) += governor_powersave.o obj-$(CONFIG_DEVFREQ_GOV_USERSPACE) += governor_userspace.o +obj-$(CONFIG_DEVFREQ_GOV_QCOM_ADRENO_TZ) += governor_msm_adreno_tz.o +obj-$(CONFIG_DEVFREQ_GOV_CPUFREQ) += governor_cpufreq.o +obj-$(CONFIG_QCOM_BIMC_BWMON) += bimc-bwmon.o +obj-$(CONFIG_ARMBW_HWMON) += armbw-pm.o +obj-$(CONFIG_ARM_MEMLAT_MON) += arm-memlat-mon.o +obj-$(CONFIG_QCOMCCI_HWMON) += msmcci-hwmon.o +obj-$(CONFIG_QCOM_M4M_HWMON) += m4m-hwmon.o +obj-$(CONFIG_DEVFREQ_GOV_QCOM_BW_HWMON) += governor_bw_hwmon.o +obj-$(CONFIG_DEVFREQ_GOV_QCOM_CACHE_HWMON) += governor_cache_hwmon.o +obj-$(CONFIG_DEVFREQ_GOV_SPDM_HYP) += governor_spdm_bw_hyp.o +obj-$(CONFIG_DEVFREQ_GOV_QCOM_GPUBW_MON) += governor_gpubw_mon.o +obj-$(CONFIG_DEVFREQ_GOV_QCOM_GPUBW_MON) += governor_bw_vbif.o +obj-$(CONFIG_DEVFREQ_GOV_MEMLAT) += governor_memlat.o # DEVFREQ Drivers obj-$(CONFIG_ARM_EXYNOS4_BUS_DEVFREQ) += exynos/ obj-$(CONFIG_ARM_EXYNOS5_BUS_DEVFREQ) += exynos/ obj-$(CONFIG_ARM_TEGRA_DEVFREQ) += tegra-devfreq.o +obj-$(CONFIG_QCOM_DEVFREQ_DEVBW) += devfreq_devbw.o +obj-$(CONFIG_DEVFREQ_SIMPLE_DEV) += devfreq_simple_dev.o +obj-$(CONFIG_DEVFREQ_SPDM) += devfreq_spdm.o devfreq_spdm_debugfs.o # DEVFREQ Event Drivers obj-$(CONFIG_PM_DEVFREQ_EVENT) += event/ diff -ruw linux-4.4.115/drivers/dma/Kconfig linux-4.4.115-fbx/drivers/dma/Kconfig --- linux-4.4.115/drivers/dma/Kconfig 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/dma/Kconfig 2019-01-22 16:16:23.139243110 +0100 @@ -417,6 +417,16 @@ Enable support for the QCOM BAM DMA controller. This controller provides DMA capabilities for a variety of on-chip devices. +config QCOM_SPS_DMA + tristate "Qualcomm technologies inc DMA driver for sps-BAM" + depends on ARCH_QCOM + select DMA_ENGINE + help + Enable support for Qualcomm technologies inc, BAM DMA engine. + This DMA-engine-driver is a wrapper of the sps-BAM library. DMA + engine callbacks are implemented using the sps-BAM functionality + to access HW. + config SIRF_DMA tristate "CSR SiRFprimaII/SiRFmarco DMA support" depends on ARCH_SIRF diff -ruw linux-4.4.115/drivers/dma/Makefile linux-4.4.115-fbx/drivers/dma/Makefile --- linux-4.4.115/drivers/dma/Makefile 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/dma/Makefile 2019-01-22 16:16:23.139243110 +0100 @@ -65,5 +65,6 @@ obj-$(CONFIG_TI_EDMA) += edma.o obj-$(CONFIG_XGENE_DMA) += xgene-dma.o obj-$(CONFIG_ZX_DMA) += zx296702_dma.o +obj-$(CONFIG_QCOM_SPS_DMA) += qcom-sps-dma.o obj-y += xilinx/ diff -ruw linux-4.4.115/drivers/dma-buf/fence.c linux-4.4.115-fbx/drivers/dma-buf/fence.c --- linux-4.4.115/drivers/dma-buf/fence.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/dma-buf/fence.c 2019-01-22 16:16:23.139243110 +0100 @@ -304,8 +304,12 @@ spin_lock_irqsave(fence->lock, flags); ret = !list_empty(&cb->node); - if (ret) + if (ret) { list_del_init(&cb->node); + if (list_empty(&fence->cb_list)) + if (fence->ops->disable_signaling) + fence->ops->disable_signaling(fence); + } spin_unlock_irqrestore(fence->lock, flags); diff -ruw linux-4.4.115/drivers/edac/edac_core.h linux-4.4.115-fbx/drivers/edac/edac_core.h --- linux-4.4.115/drivers/edac/edac_core.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/edac/edac_core.h 2019-01-22 16:16:23.171243400 +0100 @@ -223,9 +223,11 @@ /* Per instance controls for this edac_device */ int log_ue; /* boolean for logging UEs */ int log_ce; /* boolean for logging CEs */ + int panic_on_ce; /* boolean for panic'ing on an CE */ int panic_on_ue; /* boolean for panic'ing on an UE */ unsigned poll_msec; /* number of milliseconds to poll interval */ unsigned long delay; /* number of jiffies for poll_msec */ + bool defer_work; /* Create a deferrable work for polling */ /* Additional top controller level attributes, but specified * by the low level driver. diff -ruw linux-4.4.115/drivers/edac/edac_device.c linux-4.4.115-fbx/drivers/edac/edac_device.c --- linux-4.4.115/drivers/edac/edac_device.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/edac/edac_device.c 2019-01-22 16:16:23.171243400 +0100 @@ -411,9 +411,15 @@ * to used in the time period calculation * then calc the number of jiffies that represents */ + if (!msec) + msec = 1000; edac_dev->poll_msec = msec; edac_dev->delay = msecs_to_jiffies(msec); + if (edac_dev->defer_work) + INIT_DEFERRABLE_WORK(&edac_dev->work, + edac_device_workq_function); + else INIT_DELAYED_WORK(&edac_dev->work, edac_device_workq_function); /* optimize here for the 1 second case, which will be normal value, to @@ -523,7 +529,7 @@ * enable workq processing on this instance, * default = 1000 msec */ - edac_device_workq_setup(edac_dev, 1000); + edac_device_workq_setup(edac_dev, edac_dev->poll_msec); } else { edac_dev->op_state = OP_RUNNING_INTERRUPT; } @@ -608,6 +614,12 @@ return edac_dev->log_ue; } +static inline int edac_device_get_panic_on_ce(struct edac_device_ctl_info + *edac_dev) +{ + return edac_dev->panic_on_ce; +} + static inline int edac_device_get_panic_on_ue(struct edac_device_ctl_info *edac_dev) { @@ -657,6 +669,11 @@ "CE: %s instance: %s block: %s '%s'\n", edac_dev->ctl_name, instance->name, block ? block->name : "N/A", msg); + + if (edac_device_get_panic_on_ce(edac_dev)) + panic("EDAC %s: CE instance: %s block %s '%s'\n", + edac_dev->ctl_name, instance->name, + block ? block->name : "N/A", msg); } EXPORT_SYMBOL_GPL(edac_device_handle_ce); diff -ruw linux-4.4.115/drivers/edac/edac_device_sysfs.c linux-4.4.115-fbx/drivers/edac/edac_device_sysfs.c --- linux-4.4.115/drivers/edac/edac_device_sysfs.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/edac/edac_device_sysfs.c 2019-01-22 16:16:23.171243400 +0100 @@ -62,6 +62,13 @@ return count; } +/* 'panic_on_ce' */ +static ssize_t edac_device_ctl_panic_on_ce_show(struct edac_device_ctl_info + *ctl_info, char *data) +{ + return snprintf(data, PAGE_SIZE, "%u\n", ctl_info->panic_on_ce); +} + /* 'panic_on_ue' */ static ssize_t edac_device_ctl_panic_on_ue_show(struct edac_device_ctl_info *ctl_info, char *data) @@ -69,6 +76,21 @@ return sprintf(data, "%u\n", ctl_info->panic_on_ue); } +static ssize_t edac_device_ctl_panic_on_ce_store(struct edac_device_ctl_info + *ctl_info, const char *data, + size_t count) +{ + unsigned long val; + + /* if parameter is zero, turn off flag, if non-zero turn on flag */ + if (kstrtoul(data, 0, &val) < 0) + return -EINVAL; + + ctl_info->panic_on_ce = !!val; + + return count; +} + static ssize_t edac_device_ctl_panic_on_ue_store(struct edac_device_ctl_info *ctl_info, const char *data, size_t count) @@ -156,6 +178,9 @@ edac_device_ctl_log_ue_show, edac_device_ctl_log_ue_store); CTL_INFO_ATTR(log_ce, S_IRUGO | S_IWUSR, edac_device_ctl_log_ce_show, edac_device_ctl_log_ce_store); +CTL_INFO_ATTR(panic_on_ce, S_IRUGO | S_IWUSR, + edac_device_ctl_panic_on_ce_show, + edac_device_ctl_panic_on_ce_store); CTL_INFO_ATTR(panic_on_ue, S_IRUGO | S_IWUSR, edac_device_ctl_panic_on_ue_show, edac_device_ctl_panic_on_ue_store); @@ -164,6 +189,7 @@ /* Base Attributes of the EDAC_DEVICE ECC object */ static struct ctl_info_attribute *device_ctrl_attr[] = { + &attr_ctl_info_panic_on_ce, &attr_ctl_info_panic_on_ue, &attr_ctl_info_log_ue, &attr_ctl_info_log_ce, diff -ruw linux-4.4.115/drivers/edac/Kconfig linux-4.4.115-fbx/drivers/edac/Kconfig --- linux-4.4.115/drivers/edac/Kconfig 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/edac/Kconfig 2019-01-22 16:16:23.167243364 +0100 @@ -390,4 +390,44 @@ Support for error detection and correction on the APM X-Gene family of SOCs. +config EDAC_CORTEX_ARM64 + depends on EDAC_MM_EDAC && ARM64 + bool "ARM Cortex A CPUs L1/L2 Caches" + help + Support for error detection and correction on the + ARM Cortex A53 and A57 CPUs. For debugging issues having to do with + stability and overall system health, you should probably say 'Y' + here. + +config EDAC_CORTEX_ARM64_PANIC_ON_CE + depends on EDAC_CORTEX_ARM64 + bool "Panic on correctable errors" + help + Forcibly cause a kernel panic if an correctable error (CE) is + detected, even though the error is (by definition) correctable and + would otherwise result in no adverse system effects. This can reduce + debugging times on hardware which may be operating at voltages or + frequencies outside normal specification. + + For production builds, you should definitely say 'N' here. + +config EDAC_CORTEX_ARM64_DBE_IRQ_ONLY + depends on EDAC_CORTEX_ARM64 + bool "Only check for parity errors when an irq is generated" + help + In ARM64, parity errors will cause an interrupt + to be triggered but may also cause a data abort to + occur. Only check for EDAC errors for the interrupt. + If unsure, say no. + +config EDAC_CORTEX_ARM64_PANIC_ON_UE + depends on EDAC_CORTEX_ARM64 + bool "Panic on uncorrectable errors" + help + Forcibly cause a kernel panic if an uncorrectable error (UE) is + detected. This can reduce debugging times on hardware which may be + operating at voltages or frequencies outside normal specification. + + For production builds, you should probably say 'N' here. + endif # EDAC diff -ruw linux-4.4.115/drivers/edac/Makefile linux-4.4.115-fbx/drivers/edac/Makefile --- linux-4.4.115/drivers/edac/Makefile 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/edac/Makefile 2019-01-22 16:16:23.167243364 +0100 @@ -70,3 +70,4 @@ obj-$(CONFIG_EDAC_ALTERA_MC) += altera_edac.o obj-$(CONFIG_EDAC_SYNOPSYS) += synopsys_edac.o obj-$(CONFIG_EDAC_XGENE) += xgene_edac.o +obj-$(CONFIG_EDAC_CORTEX_ARM64) += cortex_arm64_edac.o diff -ruw linux-4.4.115/drivers/extcon/extcon.c linux-4.4.115-fbx/drivers/extcon/extcon.c --- linux-4.4.115/drivers/extcon/extcon.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/extcon/extcon.c 2019-01-22 16:16:23.183243509 +0100 @@ -63,6 +63,12 @@ [EXTCON_JACK_SPDIF_IN] = "SPDIF-IN", [EXTCON_JACK_SPDIF_OUT] = "SPDIF-OUT", + /* connector orientation 0 - CC1, 1 - CC2 */ + [EXTCON_USB_CC] = "USB-CC", + + /* connector speed 0 - High Speed, 1 - Super Speed */ + [EXTCON_USB_SPEED] = "USB-SPEED", + /* Display external connector */ [EXTCON_DISP_HDMI] = "HDMI", [EXTCON_DISP_MHL] = "MHL", @@ -78,7 +84,7 @@ }; static struct class *extcon_class; -#if defined(CONFIG_ANDROID) +#if defined(CONFIG_ANDROID) && !IS_ENABLED(CONFIG_SWITCH) static struct class_compat *switch_class; #endif /* CONFIG_ANDROID */ @@ -635,7 +641,7 @@ return PTR_ERR(extcon_class); extcon_class->dev_groups = extcon_groups; -#if defined(CONFIG_ANDROID) +#if defined(CONFIG_ANDROID) && !IS_ENABLED(CONFIG_SWITCH) switch_class = class_compat_register("switch"); if (WARN(!switch_class, "cannot allocate")) return -ENOMEM; @@ -921,7 +927,7 @@ put_device(&edev->dev); goto err_dev; } -#if defined(CONFIG_ANDROID) +#if defined(CONFIG_ANDROID) && !IS_ENABLED(CONFIG_SWITCH) if (switch_class) ret = class_compat_create_link(switch_class, &edev->dev, NULL); #endif /* CONFIG_ANDROID */ @@ -1010,7 +1016,7 @@ kfree(edev->cables); } -#if defined(CONFIG_ANDROID) +#if defined(CONFIG_ANDROID) && !IS_ENABLED(CONFIG_SWITCH) if (switch_class) class_compat_remove_link(switch_class, &edev->dev, NULL); #endif @@ -1139,7 +1145,7 @@ static void __exit extcon_class_exit(void) { -#if defined(CONFIG_ANDROID) +#if defined(CONFIG_ANDROID) && !IS_ENABLED(CONFIG_SWITCH) class_compat_unregister(switch_class); #endif class_destroy(extcon_class); diff -ruw linux-4.4.115/drivers/firmware/efi/libstub/Makefile linux-4.4.115-fbx/drivers/firmware/efi/libstub/Makefile --- linux-4.4.115/drivers/firmware/efi/libstub/Makefile 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/firmware/efi/libstub/Makefile 2019-01-22 16:16:23.191243581 +0100 @@ -8,20 +8,24 @@ cflags-$(CONFIG_X86_64) := -mcmodel=small cflags-$(CONFIG_X86) += -m$(BITS) -D__KERNEL__ $(LINUX_INCLUDE) -O2 \ -fPIC -fno-strict-aliasing -mno-red-zone \ - -mno-mmx -mno-sse -DDISABLE_BRANCH_PROFILING + -mno-mmx -mno-sse -cflags-$(CONFIG_ARM64) := $(subst -pg,,$(KBUILD_CFLAGS)) +cflags-$(CONFIG_ARM64) := $(subst -pg,,$(KBUILD_CFLAGS)) -fpie cflags-$(CONFIG_ARM) := $(subst -pg,,$(KBUILD_CFLAGS)) \ -fno-builtin -fpic -mno-single-pic-base cflags-$(CONFIG_EFI_ARMSTUB) += -I$(srctree)/scripts/dtc/libfdt -KBUILD_CFLAGS := $(cflags-y) \ +KBUILD_CFLAGS := $(cflags-y) -DDISABLE_BRANCH_PROFILING \ $(call cc-option,-ffreestanding) \ $(call cc-option,-fno-stack-protector) GCOV_PROFILE := n KASAN_SANITIZE := n +UBSAN_SANITIZE := n + +# Prevents link failures: __sanitizer_cov_trace_pc() is not linked in. +KCOV_INSTRUMENT := n lib-y := efi-stub-helper.o @@ -34,7 +38,8 @@ lib-$(CONFIG_EFI_ARMSTUB) += arm-stub.o fdt.o string.o \ $(patsubst %.c,lib-%.o,$(arm-deps)) -lib-$(CONFIG_ARM64) += arm64-stub.o +lib-$(CONFIG_ARM) += arm32-stub.o +lib-$(CONFIG_ARM64) += arm64-stub.o random.o CFLAGS_arm64-stub.o := -DTEXT_OFFSET=$(TEXT_OFFSET) # diff -ruw linux-4.4.115/drivers/firmware/efi/Makefile linux-4.4.115-fbx/drivers/firmware/efi/Makefile --- linux-4.4.115/drivers/firmware/efi/Makefile 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/firmware/efi/Makefile 2019-01-22 16:16:23.191243581 +0100 @@ -18,3 +18,6 @@ obj-$(CONFIG_EFI_RUNTIME_WRAPPERS) += runtime-wrappers.o obj-$(CONFIG_EFI_STUB) += libstub/ obj-$(CONFIG_EFI_FAKE_MEMMAP) += fake_mem.o + +arm-obj-$(CONFIG_EFI) := arm-init.o arm-runtime.o +obj-$(CONFIG_ARM64) += $(arm-obj-y) diff -ruw linux-4.4.115/drivers/firmware/Kconfig linux-4.4.115-fbx/drivers/firmware/Kconfig --- linux-4.4.115/drivers/firmware/Kconfig 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/firmware/Kconfig 2019-10-29 09:26:23.537202141 +0100 @@ -173,8 +173,12 @@ def_bool y depends on QCOM_SCM && ARM64 +config HAVE_ARM_SMCCC + bool + source "drivers/firmware/broadcom/Kconfig" source "drivers/firmware/google/Kconfig" source "drivers/firmware/efi/Kconfig" +source "drivers/firmware/qcom/Kconfig" endmenu diff -ruw linux-4.4.115/drivers/firmware/Makefile linux-4.4.115-fbx/drivers/firmware/Makefile --- linux-4.4.115/drivers/firmware/Makefile 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/firmware/Makefile 2019-01-22 16:16:23.187243545 +0100 @@ -23,3 +23,4 @@ obj-$(CONFIG_GOOGLE_FIRMWARE) += google/ obj-$(CONFIG_EFI) += efi/ obj-$(CONFIG_UEFI_CPER) += efi/ +obj-$(CONFIG_MSM_TZ_LOG) += qcom/ \ No newline at end of file diff -ruw linux-4.4.115/drivers/firmware/psci.c linux-4.4.115-fbx/drivers/firmware/psci.c --- linux-4.4.115/drivers/firmware/psci.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/firmware/psci.c 2019-01-22 16:16:23.195243617 +0100 @@ -13,6 +13,8 @@ #define pr_fmt(fmt) "psci: " fmt +#include +#include #include #include #include @@ -20,10 +22,12 @@ #include #include #include +#include #include #include +#include #include #include #include @@ -58,8 +62,6 @@ typedef unsigned long (psci_fn)(unsigned long, unsigned long, unsigned long, unsigned long); -asmlinkage psci_fn __invoke_psci_fn_hvc; -asmlinkage psci_fn __invoke_psci_fn_smc; static psci_fn *invoke_psci_fn; enum psci_function { @@ -225,6 +227,130 @@ psci_func_id, 0, 0); } +#ifdef CONFIG_CPU_IDLE +static DEFINE_PER_CPU_READ_MOSTLY(u32 *, psci_power_state); + +#ifdef CONFIG_ARM_PSCI +static int psci_cpu_init(struct device_node *cpu_node, int cpu) +{ + return 0; +} +#endif + +static int psci_dt_cpu_init_idle(struct device_node *cpu_node, int cpu) +{ + int i, ret, count = 0; + u32 *psci_states; + struct device_node *state_node; + + /* + * If the PSCI cpu_suspend function hook has not been initialized + * idle states must not be enabled, so bail out + */ + if (!psci_ops.cpu_suspend) + return -EOPNOTSUPP; + + /* Count idle states */ + while ((state_node = of_parse_phandle(cpu_node, "cpu-idle-states", + count))) { + count++; + of_node_put(state_node); + } + + if (!count) + return -ENODEV; + + psci_states = kcalloc(count, sizeof(*psci_states), GFP_KERNEL); + if (!psci_states) + return -ENOMEM; + + for (i = 0; i < count; i++) { + u32 state; + + state_node = of_parse_phandle(cpu_node, "cpu-idle-states", i); + + ret = of_property_read_u32(state_node, + "arm,psci-suspend-param", + &state); + if (ret) { + pr_warn(" * %s missing arm,psci-suspend-param property\n", + state_node->full_name); + of_node_put(state_node); + goto free_mem; + } + + of_node_put(state_node); + pr_debug("psci-power-state %#x index %d\n", state, i); + if (!psci_power_state_is_valid(state)) { + pr_warn("Invalid PSCI power state %#x\n", state); + ret = -EINVAL; + goto free_mem; + } + psci_states[i] = state; + } + /* Idle states parsed correctly, initialize per-cpu pointer */ + per_cpu(psci_power_state, cpu) = psci_states; + return 0; + +free_mem: + kfree(psci_states); + return ret; +} + +int psci_cpu_init_idle(unsigned int cpu) +{ + struct device_node *cpu_node; + int ret; + + cpu_node = of_get_cpu_node(cpu, NULL); + if (!cpu_node) + return -ENODEV; + + ret = psci_dt_cpu_init_idle(cpu_node, cpu); + + of_node_put(cpu_node); + + return ret; +} + +static int psci_suspend_finisher(unsigned long state_id) +{ + return psci_ops.cpu_suspend(state_id, virt_to_phys(cpu_resume)); +} + +int psci_cpu_suspend_enter(unsigned long state_id) +{ + int ret; + /* + * idle state_id 0 corresponds to wfi, should never be called + * from the cpu_suspend operations + */ + if (WARN_ON_ONCE(!state_id)) + return -EINVAL; + + if (!psci_power_state_loses_context(state_id)) + ret = psci_ops.cpu_suspend(state_id, 0); + else + ret = cpu_suspend(state_id, psci_suspend_finisher); + + return ret; +} + +/* ARM specific CPU idle operations */ +#ifdef CONFIG_ARM +static struct cpuidle_ops psci_cpuidle_ops __initdata = { + .suspend = psci_cpu_suspend_enter, +#ifdef CONFIG_ARM_PSCI + .init = psci_cpu_init, +#else + .init = psci_dt_cpu_init_idle, +#endif +}; + +CPUIDLE_METHOD_OF_DECLARE(psci, "psci", &psci_cpuidle_ops); +#endif +#endif + static int psci_system_suspend(unsigned long unused) { return invoke_psci_fn(PSCI_FN_NATIVE(1_0, SYSTEM_SUSPEND), @@ -305,6 +431,8 @@ static void __init psci_0_2_set_functions(void) { pr_info("Using standard PSCI v0.2 function IDs\n"); + psci_ops.get_version = psci_get_version; + psci_function_id[PSCI_FN_CPU_SUSPEND] = PSCI_FN_NATIVE(0_2, CPU_SUSPEND); psci_ops.cpu_suspend = psci_cpu_suspend; diff -ruw linux-4.4.115/drivers/gpio/gpiolib-acpi.c linux-4.4.115-fbx/drivers/gpio/gpiolib-acpi.c --- linux-4.4.115/drivers/gpio/gpiolib-acpi.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/gpio/gpiolib-acpi.c 2019-01-22 16:16:23.211243762 +0100 @@ -597,7 +597,7 @@ int idx, i; for (i = 0, idx = 0; idx <= index; i++) { - struct acpi_gpio_info info; + struct acpi_gpio_info info = {0, 0}; struct gpio_desc *desc; desc = acpi_get_gpiod_by_index(adev, NULL, i, &info); diff -ruw linux-4.4.115/drivers/gpio/gpio-pca953x.c linux-4.4.115-fbx/drivers/gpio/gpio-pca953x.c --- linux-4.4.115/drivers/gpio/gpio-pca953x.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/gpio/gpio-pca953x.c 2019-01-22 16:16:23.207243726 +0100 @@ -14,6 +14,7 @@ #include #include #include +#include #include #include #include @@ -681,8 +682,16 @@ invert = pdata->invert; chip->names = pdata->names; } else { + struct gpio_desc *reset_gpio; + chip->gpio_start = -1; irq_base = 0; + + /* See if we need to de-assert a reset pin */ + reset_gpio = devm_gpiod_get_optional(&client->dev, "reset", + GPIOD_OUT_LOW); + if (IS_ERR(reset_gpio)) + return PTR_ERR(reset_gpio); } chip->client = client; diff -ruw linux-4.4.115/drivers/gpio/Kconfig linux-4.4.115-fbx/drivers/gpio/Kconfig --- linux-4.4.115/drivers/gpio/Kconfig 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/gpio/Kconfig 2019-10-29 09:26:23.541202180 +0100 @@ -338,6 +338,25 @@ help Say yes here to support the PXA GPIO device +config GPIO_QPNP_PIN + tristate "Qualcomm Technologies, Inc. QPNP GPIO support" + depends on SPMI + help + Say 'y' here to include support for the Qualcomm Technologies, Inc. + QPNP GPIO driver. This driver supports Device Tree and allows a + device_node to be registered as a gpio-controller. It does not handle + GPIO interrupts directly; they are handled via the SPMI arbiter + interrupt driver. + +config GPIO_QPNP_PIN_DEBUG + bool "Qualcomm Technologies, Inc. QPNP GPIO debug support" + depends on GPIO_QPNP_PIN && DEBUG_FS + help + Say 'y' here to include debug support for the Qualcomm Technologies, + Inc. QPNP GPIO driver. This provides a userspace debug interface to + get and set all of the supported features of PMIC GPIO and MPP pins + including those which are managed by the gpio framework. + config GPIO_RCAR tristate "Renesas R-Car GPIO" depends on ARCH_SHMOBILE || COMPILE_TEST diff -ruw linux-4.4.115/drivers/gpio/Makefile linux-4.4.115-fbx/drivers/gpio/Makefile --- linux-4.4.115/drivers/gpio/Makefile 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/gpio/Makefile 2019-04-24 19:28:47.284498086 +0200 @@ -76,6 +76,7 @@ obj-$(CONFIG_GPIO_PCH) += gpio-pch.o obj-$(CONFIG_GPIO_PL061) += gpio-pl061.o obj-$(CONFIG_GPIO_PXA) += gpio-pxa.o +obj-$(CONFIG_GPIO_QPNP_PIN) += qpnp-pin.o obj-$(CONFIG_GPIO_RC5T583) += gpio-rc5t583.o obj-$(CONFIG_GPIO_RDC321X) += gpio-rdc321x.o obj-$(CONFIG_GPIO_RCAR) += gpio-rcar.o @@ -119,3 +120,4 @@ obj-$(CONFIG_GPIO_ZEVIO) += gpio-zevio.o obj-$(CONFIG_GPIO_ZYNQ) += gpio-zynq.o obj-$(CONFIG_GPIO_ZX) += gpio-zx.o +obj-$(CONFIG_MSM_SMP2P) += gpio-msm-smp2p.o diff -ruw linux-4.4.115/drivers/gpu/drm/drm_edid.c linux-4.4.115-fbx/drivers/gpu/drm/drm_edid.c --- linux-4.4.115/drivers/gpu/drm/drm_edid.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/gpu/drm/drm_edid.c 2019-10-29 09:26:23.601202767 +0100 @@ -91,6 +91,14 @@ #define LEVEL_GTF2 2 #define LEVEL_CVT 3 +/*Enum storing luminance types for HDR blocks in EDID*/ +enum luminance_value { + NO_LUMINANCE_DATA = 3, + MAXIMUM_LUMINANCE = 4, + FRAME_AVERAGE_LUMINANCE = 5, + MINIMUM_LUMINANCE = 6 +}; + static struct edid_quirk { char vendor[4]; int product_id; @@ -994,9 +1002,224 @@ .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, /* 64 - 1920x1080@100Hz */ { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448, - 2492, 2640, 0, 1080, 1084, 1094, 1125, 0, + 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, + /* 65 - 1280x720@24Hz */ + { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040, + 3080, 3300, 0, 720, 725, 730, 750, 0, + DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), + .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, + /* 66 - 1280x720@25Hz */ + { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700, + 3740, 3960, 0, 720, 725, 730, 750, 0, + DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), + .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, + /* 67 - 1280x720@30Hz */ + { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040, + 3080, 3300, 0, 720, 725, 730, 750, 0, + DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), + .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, + /* 68 - 1280x720@50Hz */ + { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720, + 1760, 1980, 0, 720, 725, 730, 750, 0, + DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), + .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, + /* 69 - 1280x720@60Hz */ + { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390, + 1430, 1650, 0, 720, 725, 730, 750, 0, + DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), + .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, + /* 70 - 1280x720@100Hz */ + { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720, + 1760, 1980, 0, 720, 725, 730, 750, 0, + DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), + .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, + /* 71 - 1280x720@120Hz */ + { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390, + 1430, 1650, 0, 720, 725, 730, 750, 0, + DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), + .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, + /* 72 - 1920x1080@24Hz */ + { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558, + 2602, 2750, 0, 1080, 1084, 1089, 1125, 0, + DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), + .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, + /* 73 - 1920x1080@25Hz */ + { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, + 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, + DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), + .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, + /* 74 - 1920x1080@30Hz */ + { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, + 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, + DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), + .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, + /* 75 - 1920x1080@50Hz */ + { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, + 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, + DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), + .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, + /* 76 - 1920x1080@60Hz */ + { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, + 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, + DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), + .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, + /* 77 - 1920x1080@100Hz */ + { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448, + 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, + DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), + .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, + /* 78 - 1920x1080@120Hz */ + { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008, + 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, + DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), + .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, + /* 79 - 1680x720@24Hz */ + { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 3040, + 3080, 3300, 0, 720, 725, 730, 750, 0, + DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), + .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, + /* 80 - 1680x720@25Hz */ + { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2908, + 2948, 3168, 0, 720, 725, 730, 750, 0, + DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), + .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, + /* 81 - 1680x720@30Hz */ + { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2380, + 2420, 2640, 0, 720, 725, 730, 750, 0, + DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), + .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, + /* 82 - 1680x720@50Hz */ + { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 82500, 1680, 1940, + 1980, 2200, 0, 720, 725, 730, 750, 0, + DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), + .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, + /* 83 - 1680x720@60Hz */ + { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 99000, 1680, 1940, + 1980, 2200, 0, 720, 725, 730, 750, 0, + DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), + .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, + /* 84 - 1680x720@100Hz */ + { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 165000, 1680, 1740, + 1780, 2000, 0, 720, 725, 730, 825, 0, + DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), + .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, + /* 85 - 1680x720@120Hz */ + { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 198000, 1680, 1740, + 1780, 2000, 0, 720, 725, 730, 825, 0, + DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), + .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, + /* 86 - 2560x1080@24Hz */ + { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 99000, 2560, 3558, + 3602, 3750, 0, 1080, 1084, 1089, 1100, 0, + DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), + .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, + /* 87 - 2560x1080@25Hz */ + { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 90000, 2560, 3008, + 3052, 3200, 0, 1080, 1084, 1089, 1125, 0, + DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), + .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, + /* 88 - 2560x1080@30Hz */ + { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 118800, 2560, 3328, + 3372, 3520, 0, 1080, 1084, 1089, 1125, 0, + DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), + .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, + /* 89 - 2560x1080@50Hz */ + { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 185625, 2560, 3108, + 3152, 3300, 0, 1080, 1084, 1089, 1125, 0, + DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), + .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, + /* 90 - 2560x1080@60Hz */ + { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 198000, 2560, 2808, + 2852, 3000, 0, 1080, 1084, 1089, 1100, 0, + DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), + .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, + /* 91 - 2560x1080@100Hz */ + { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 371250, 2560, 2778, + 2822, 2970, 0, 1080, 1084, 1089, 1250, 0, + DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), + .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, + /* 92 - 2560x1080@120Hz */ + { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 495000, 2560, 3108, + 3152, 3300, 0, 1080, 1084, 1089, 1250, 0, + DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), + .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, + /* 93 - 3840x2160p@24Hz 16:9 */ + { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116, + 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, + DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), + .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, + /* 94 - 3840x2160p@25Hz 16:9 */ + { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896, + 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, + DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), + .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, + /* 95 - 3840x2160p@30Hz 16:9 */ + { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016, + 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, + DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), + .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, + /* 96 - 3840x2160p@50Hz 16:9 */ + { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896, + 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, + DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), + .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, + /* 97 - 3840x2160p@60Hz 16:9 */ + { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016, + 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, + DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), + .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, + /* 98 - 4096x2160p@24Hz 256:135 */ + { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5116, + 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, + DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), + .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, + /* 99 - 4096x2160p@25Hz 256:135 */ + { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5064, + 5152, 5280, 0, 2160, 2168, 2178, 2250, 0, + DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), + .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, + /* 100 - 4096x2160p@30Hz 256:135 */ + { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 4184, + 4272, 4400, 0, 2160, 2168, 2178, 2250, 0, + DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), + .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, + /* 101 - 4096x2160p@50Hz 256:135 */ + { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 5064, + 5152, 5280, 0, 2160, 2168, 2178, 2250, 0, + DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), + .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, + /* 102 - 4096x2160p@60Hz 256:135 */ + { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 4184, + 4272, 4400, 0, 2160, 2168, 2178, 2250, 0, + DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), + .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, + /* 103 - 3840x2160p@24Hz 64:27 */ + { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116, + 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, + DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), + .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, + /* 104 - 3840x2160p@25Hz 64:27 */ + { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896, + 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, + DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), + .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, + /* 105 - 3840x2160p@30Hz 64:27 */ + { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016, + 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, + DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), + .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, + /* 106 - 3840x2160p@50Hz 64:27 */ + { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896, + 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, + DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), + .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, + /* 107 - 3840x2160p@60Hz 64:27 */ + { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016, + 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, + DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), + .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, }; /* @@ -1275,6 +1498,10 @@ * level, drivers must make all reasonable efforts to expose it as an I2C * adapter and use drm_get_edid() instead of abusing this function. * + * The EDID may be overridden using debugfs override_edid or firmare EDID + * (drm_load_edid_firmware() and drm.edid_firmware parameter), in this priority + * order. Having either of them bypasses actual EDID reads. + * * Return: Pointer to valid EDID or NULL if we couldn't find any. */ struct edid *drm_do_get_edid(struct drm_connector *connector, @@ -1285,6 +1512,19 @@ int i, j = 0, valid_extensions = 0; u8 *block, *new; bool print_bad_edid = !connector->bad_edid_counter || (drm_debug & DRM_UT_KMS); + struct edid *override = NULL; + + if (connector->override_edid) + override = drm_edid_duplicate((const struct edid *) + connector->edid_blob_ptr->data); + +#ifdef CONFIG_DRM_LOAD_EDID_FIRMWARE + if (!override) + override = drm_load_edid_firmware(connector); +#endif + + if (!IS_ERR_OR_NULL(override)) + return override; if ((block = kmalloc(EDID_LENGTH, GFP_KERNEL)) == NULL) return NULL; @@ -2487,12 +2727,16 @@ return closure.modes; } - +#define VIDEO_CAPABILITY_EXTENDED_DATA_BLOCK 0x0 #define AUDIO_BLOCK 0x01 #define VIDEO_BLOCK 0x02 #define VENDOR_BLOCK 0x03 #define SPEAKER_BLOCK 0x04 +#define HDR_STATIC_METADATA_EXTENDED_DATA_BLOCK 0x06 +#define COLORIMETRY_EXTENDED_DATA_BLOCK 0x05 +#define EXTENDED_TAG 0x07 #define VIDEO_CAPABILITY_BLOCK 0x07 +#define Y420_VIDEO_DATA_BLOCK 0x0E #define EDID_BASIC_AUDIO (1 << 6) #define EDID_CEA_YCRCB444 (1 << 5) #define EDID_CEA_YCRCB422 (1 << 4) @@ -3081,6 +3325,21 @@ return hdmi_id == HDMI_IEEE_OUI; } +static bool cea_db_is_hdmi_hf_vsdb(const u8 *db) +{ + int hdmi_id; + + if (cea_db_tag(db) != VENDOR_BLOCK) + return false; + + if (cea_db_payload_len(db) < 7) + return false; + + hdmi_id = db[1] | (db[2] << 8) | (db[3] << 16); + + return hdmi_id == HDMI_IEEE_OUI_HF; +} + #define for_each_cea_db(cea, i, start, end) \ for ((i) = (start); (i) < (end) && (i) + cea_db_payload_len(&(cea)[(i)]) < (end); (i) += cea_db_payload_len(&(cea)[(i)]) + 1) @@ -3204,6 +3463,311 @@ } static void +parse_hdmi_hf_vsdb(struct drm_connector *connector, const u8 *db) +{ + u8 len = cea_db_payload_len(db); + + if (len < 7) + return; + + if (db[4] != 1) + return; /* invalid version */ + + connector->max_tmds_char = db[5] * 5; + connector->scdc_present = db[6] & (1 << 7); + connector->rr_capable = db[6] & (1 << 6); + connector->flags_3d = db[6] & 0x7; + connector->supports_scramble = connector->scdc_present && + (db[6] & (1 << 3)); + + DRM_DEBUG_KMS("HDMI v2: max TMDS char %d, " + "scdc %s, " + "rr %s, " + "3D flags 0x%x, " + "scramble %s\n", + connector->max_tmds_char, + connector->scdc_present ? "available" : "not available", + connector->rr_capable ? "capable" : "not capable", + connector->flags_3d, + connector->supports_scramble ? + "supported" : "not supported"); +} + +static void +drm_hdmi_extract_vsdbs_info(struct drm_connector *connector, struct edid *edid) +{ + const u8 *cea = drm_find_cea_extension(edid); + const u8 *db = NULL; + + if (cea && cea_revision(cea) >= 3) { + int i, start, end; + + if (cea_db_offsets(cea, &start, &end)) + return; + + for_each_cea_db(cea, i, start, end) { + db = &cea[i]; + + if (cea_db_tag(db) == VENDOR_BLOCK) { + /* HDMI Vendor-Specific Data Block */ + if (cea_db_is_hdmi_vsdb(db)) + parse_hdmi_vsdb(connector, db); + /* HDMI Forum Vendor-Specific Data Block */ + else if (cea_db_is_hdmi_hf_vsdb(db)) + parse_hdmi_hf_vsdb(connector, db); + } + } + } +} + +/* + * drm_extract_vcdb_info - Parse the HDMI Video Capability Data Block + * @connector: connector corresponding to the HDMI sink + * @db: start of the CEA vendor specific block + * + * Parses the HDMI VCDB to extract sink info for @connector. + */ +static void +drm_extract_vcdb_info(struct drm_connector *connector, const u8 *db) +{ + /* + * Check if the sink specifies underscan + * support for: + * BIT 5: preferred video format + * BIT 3: IT video format + * BIT 1: CE video format + */ + + connector->pt_scan_info = + (db[2] & (BIT(4) | BIT(5))) >> 4; + connector->it_scan_info = + (db[2] & (BIT(3) | BIT(2))) >> 2; + connector->ce_scan_info = + db[2] & (BIT(1) | BIT(0)); + connector->rgb_qs = + db[2] & BIT(6); + connector->yuv_qs = + db[2] & BIT(7); + + DRM_DEBUG_KMS("Scan Info (pt|it|ce): (%d|%d|%d)", + (int) connector->pt_scan_info, + (int) connector->it_scan_info, + (int) connector->ce_scan_info); + DRM_DEBUG_KMS("rgb_quant_range_select %d", connector->rgb_qs); + DRM_DEBUG_KMS("ycc_quant_range_select %d", connector->yuv_qs); +} + +static bool drm_edid_is_luminance_value_present( +u32 block_length, enum luminance_value value) +{ + return block_length > NO_LUMINANCE_DATA && value <= block_length; +} + +/* + * drm_extract_hdr_db - Parse the HDMI HDR extended block + * @connector: connector corresponding to the HDMI sink + * @db: start of the HDMI HDR extended block + * + * Parses the HDMI HDR extended block to extract sink info for @connector. + */ +static void +drm_extract_hdr_db(struct drm_connector *connector, const u8 *db) +{ + + u8 len = 0; + + if (!db) { + DRM_ERROR("invalid db\n"); + return; + } + + len = db[0] & 0x1f; + /* Byte 3: Electro-Optical Transfer Functions */ + connector->hdr_eotf = db[2] & 0x3F; + + /* Byte 4: Static Metadata Descriptor Type 1 */ + connector->hdr_metadata_type_one = (db[3] & BIT(0)); + + /* Byte 5: Desired Content Maximum Luminance */ + if (drm_edid_is_luminance_value_present(len, MAXIMUM_LUMINANCE)) + connector->hdr_max_luminance = + db[MAXIMUM_LUMINANCE]; + + /* Byte 6: Desired Content Max Frame-average Luminance */ + if (drm_edid_is_luminance_value_present(len, FRAME_AVERAGE_LUMINANCE)) + connector->hdr_avg_luminance = + db[FRAME_AVERAGE_LUMINANCE]; + + /* Byte 7: Desired Content Min Luminance */ + if (drm_edid_is_luminance_value_present(len, MINIMUM_LUMINANCE)) + connector->hdr_min_luminance = + db[MINIMUM_LUMINANCE]; + + connector->hdr_supported = true; + + DRM_DEBUG_KMS("HDR electro-optical %d\n", connector->hdr_eotf); + DRM_DEBUG_KMS("metadata desc 1 %d\n", connector->hdr_metadata_type_one); + DRM_DEBUG_KMS("max luminance %d\n", connector->hdr_max_luminance); + DRM_DEBUG_KMS("avg luminance %d\n", connector->hdr_avg_luminance); + DRM_DEBUG_KMS("min luminance %d\n", connector->hdr_min_luminance); +} + +/* + * drm_extract_colorimetry_db - Parse the HDMI colorimetry extended block + * @connector: connector corresponding to the HDMI sink + * @db: start of the HDMI colorimetry extended block + * + * Parses the HDMI colorimetry block to extract sink info for @connector. + */ +static void +drm_extract_clrmetry_db(struct drm_connector *connector, const u8 *db) +{ + + if (!db) { + DRM_ERROR("invalid db\n"); + return; + } + + /* Bit 0: xvYCC_601 */ + if (db[2] & BIT(0)) + connector->color_enc_fmt |= DRM_EDID_COLORIMETRY_xvYCC_601; + /* Bit 0: xvYCC_709 */ + if (db[2] & BIT(1)) + connector->color_enc_fmt |= DRM_EDID_COLORIMETRY_xvYCC_709; + /* Bit 0: sYCC_601 */ + if (db[2] & BIT(2)) + connector->color_enc_fmt |= DRM_EDID_COLORIMETRY_sYCC_601; + /* Bit 0: ADBYCC_601 */ + if (db[2] & BIT(3)) + connector->color_enc_fmt |= DRM_EDID_COLORIMETRY_ADBYCC_601; + /* Bit 0: ADB_RGB */ + if (db[2] & BIT(4)) + connector->color_enc_fmt |= DRM_EDID_COLORIMETRY_ADB_RGB; + /* Bit 0: BT2020_CYCC */ + if (db[2] & BIT(5)) + connector->color_enc_fmt |= DRM_EDID_COLORIMETRY_BT2020_CYCC; + /* Bit 0: BT2020_YCC */ + if (db[2] & BIT(6)) + connector->color_enc_fmt |= DRM_EDID_COLORIMETRY_BT2020_YCC; + /* Bit 0: BT2020_RGB */ + if (db[2] & BIT(7)) + connector->color_enc_fmt |= DRM_EDID_COLORIMETRY_BT2020_RGB; + + DRM_DEBUG_KMS("colorimetry fmt 0x%x\n", connector->color_enc_fmt); +} + +/* + * drm_hdmi_extract_extended_blk_info - Parse the HDMI extended tag blocks + * @connector: connector corresponding to the HDMI sink + * @edid: handle to the EDID structure + * Parses the all extended tag blocks extract sink info for @connector. + */ +static void +drm_hdmi_extract_extended_blk_info(struct drm_connector *connector, +struct edid *edid) +{ + const u8 *cea = drm_find_cea_extension(edid); + const u8 *db = NULL; + + if (cea && cea_revision(cea) >= 3) { + int i, start, end; + + if (cea_db_offsets(cea, &start, &end)) + return; + + for_each_cea_db(cea, i, start, end) { + db = &cea[i]; + + if (cea_db_tag(db) == EXTENDED_TAG) { + DRM_DEBUG_KMS("found extended tag block = %d\n", + db[1]); + switch (db[1]) { + case VIDEO_CAPABILITY_EXTENDED_DATA_BLOCK: + drm_extract_vcdb_info(connector, db); + break; + case HDR_STATIC_METADATA_EXTENDED_DATA_BLOCK: + drm_extract_hdr_db(connector, db); + break; + case COLORIMETRY_EXTENDED_DATA_BLOCK: + drm_extract_clrmetry_db(connector, db); + break; + default: + break; + } + } + } + } +} + +static u8 * +drm_edid_find_extended_tag_block(struct edid *edid, int blk_id) +{ + u8 *db = NULL; + u8 *cea = NULL; + + if (!edid) { + pr_err("%s: invalid input\n", __func__); + return NULL; + } + + cea = drm_find_cea_extension(edid); + + if (cea && cea_revision(cea) >= 3) { + int i, start, end; + + if (cea_db_offsets(cea, &start, &end)) + return NULL; + + for_each_cea_db(cea, i, start, end) { + db = &cea[i]; + if ((cea_db_tag(db) == EXTENDED_TAG) && + (db[1] == blk_id)) + return db; + } + } + return NULL; +} + +/* + * add_YCbCr420VDB_modes - add the modes found in Ycbcr420 VDB block + * @connector: connector corresponding to the HDMI sink + * @edid: handle to the EDID structure + * Parses the YCbCr420 VDB block and adds the modes to @connector. + */ +static int +add_YCbCr420VDB_modes(struct drm_connector *connector, struct edid *edid) +{ + + const u8 *db = NULL; + u32 i = 0; + u32 modes = 0; + u32 video_format = 0; + u8 len = 0; + + /*Find the YCbCr420 VDB*/ + db = drm_edid_find_extended_tag_block(edid, Y420_VIDEO_DATA_BLOCK); + /* Offset to byte 3 */ + if (db) { + len = db[0] & 0x1F; + db += 2; + for (i = 0; i < len - 1; i++) { + struct drm_display_mode *mode; + + video_format = *(db + i) & 0x7F; + mode = drm_display_mode_from_vic_index(connector, + db, len-1, i); + if (mode) { + DRM_DEBUG_KMS("Adding mode for vic = %d\n", + video_format); + drm_mode_probed_add(connector, mode); + modes++; + } + } + } + return modes; +} + +static void monitor_name(struct detailed_timing *t, void *data) { if (t->data.other_data.type == EDID_DETAIL_MONITOR_NAME) @@ -3282,6 +3846,9 @@ /* HDMI Vendor-Specific Data Block */ if (cea_db_is_hdmi_vsdb(db)) parse_hdmi_vsdb(connector, db); + /* HDMI Forum Vendor-Specific Data Block */ + else if (cea_db_is_hdmi_hf_vsdb(db)) + parse_hdmi_hf_vsdb(connector, db); break; default: break; @@ -3738,6 +4305,10 @@ info->color_formats |= DRM_COLOR_FORMAT_YCRCB422; } + /* Extract audio and video latency fields for the sink */ + drm_hdmi_extract_vsdbs_info(connector, edid); + /* Extract info from extended tag blocks */ + drm_hdmi_extract_extended_blk_info(connector, edid); /* HDMI deep color modes supported? Assign to info, if so */ drm_assign_hdmi_deep_color_info(edid, info, connector); @@ -3780,6 +4351,148 @@ info->color_formats |= DRM_COLOR_FORMAT_YCRCB422; } +static int validate_displayid(u8 *displayid, int length, int idx) +{ + int i; + u8 csum = 0; + struct displayid_hdr *base; + + base = (struct displayid_hdr *)&displayid[idx]; + + DRM_DEBUG_KMS("base revision 0x%x, length %d, %d %d\n", + base->rev, base->bytes, base->prod_id, base->ext_count); + + if (base->bytes + 5 > length - idx) + return -EINVAL; + for (i = idx; i <= base->bytes + 5; i++) + csum += displayid[i]; + + if (csum) { + DRM_ERROR("DisplayID checksum invalid, remainder is %d\n", + csum); + return -EINVAL; + } + return 0; +} + +static struct drm_display_mode * +drm_mode_displayid_detailed(struct drm_device *dev, +struct displayid_detailed_timings_1 *timings) +{ + struct drm_display_mode *mode; + unsigned pixel_clock = (timings->pixel_clock[0] | + (timings->pixel_clock[1] << 8) | + (timings->pixel_clock[2] << 16)); + unsigned hactive = (timings->hactive[0] | timings->hactive[1] << 8) + 1; + unsigned hblank = + (timings->hblank[0] | + timings->hblank[1] << 8) + 1; + unsigned hsync = (timings->hsync[0] | + (timings->hsync[1] & 0x7f) << 8) + 1; + unsigned hsync_width = (timings->hsw[0] | timings->hsw[1] << 8) + 1; + unsigned vactive = (timings->vactive[0] | timings->vactive[1] << 8) + 1; + unsigned vblank = + (timings->vblank[0] | + timings->vblank[1] << 8) + 1; + unsigned vsync = + (timings->vsync[0] | + (timings->vsync[1] & 0x7f) << 8) + 1; + unsigned vsync_width = (timings->vsw[0] | timings->vsw[1] << 8) + 1; + bool hsync_positive = (timings->hsync[1] >> 7) & 0x1; + bool vsync_positive = (timings->vsync[1] >> 7) & 0x1; + + mode = drm_mode_create(dev); + if (!mode) + return NULL; + + mode->clock = pixel_clock * 10; + mode->hdisplay = hactive; + mode->hsync_start = mode->hdisplay + hsync; + mode->hsync_end = mode->hsync_start + hsync_width; + mode->htotal = mode->hdisplay + hblank; + + mode->vdisplay = vactive; + mode->vsync_start = mode->vdisplay + vsync; + mode->vsync_end = mode->vsync_start + vsync_width; + mode->vtotal = mode->vdisplay + vblank; + + mode->flags = 0; + mode->flags |= hsync_positive ? + DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC; + mode->flags |= vsync_positive ? + DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC; + mode->type = DRM_MODE_TYPE_DRIVER; + + if (timings->flags & 0x80) + mode->type |= DRM_MODE_TYPE_PREFERRED; + mode->vrefresh = drm_mode_vrefresh(mode); + drm_mode_set_name(mode); + + return mode; +} + +static int add_displayid_detailed_1_modes(struct drm_connector *connector, + struct displayid_block *block) +{ + struct displayid_detailed_timing_block *det = + (struct displayid_detailed_timing_block *)block; + int i; + int num_timings; + struct drm_display_mode *newmode; + int num_modes = 0; + /* blocks must be multiple of 20 bytes length */ + if (block->num_bytes % 20) + return 0; + + num_timings = block->num_bytes / 20; + for (i = 0; i < num_timings; i++) { + struct displayid_detailed_timings_1 *timings = &det->timings[i]; + + newmode = drm_mode_displayid_detailed(connector->dev, timings); + if (!newmode) + continue; + + drm_mode_probed_add(connector, newmode); + num_modes++; + } + return num_modes; +} + +static int add_displayid_detailed_modes(struct drm_connector *connector, + struct edid *edid) +{ + u8 *displayid; + int ret; + int idx = 1; + int length = EDID_LENGTH; + struct displayid_block *block; + int num_modes = 0; + + displayid = drm_find_displayid_extension(edid); + if (!displayid) + return 0; + + ret = validate_displayid(displayid, length, idx); + if (ret) + return 0; + + idx += sizeof(struct displayid_hdr); + while (block = (struct displayid_block *)&displayid[idx], + idx + sizeof(struct displayid_block) <= length && + idx + sizeof(struct displayid_block) + + block->num_bytes <= length && + block->num_bytes > 0) { + idx += block->num_bytes + sizeof(struct displayid_block); + switch (block->tag) { + case DATA_BLOCK_TYPE_1_DETAILED_TIMING: + num_modes += add_displayid_detailed_1_modes(connector, + block); + break; + } + } + return num_modes; +} + /** * drm_add_edid_modes - add modes from EDID data, if available * @connector: connector we're probing @@ -3825,6 +4538,8 @@ num_modes += add_established_modes(connector, edid); num_modes += add_cea_modes(connector, edid); num_modes += add_alternate_cea_modes(connector, edid); + num_modes += add_displayid_detailed_modes(connector, edid); + num_modes += add_YCbCr420VDB_modes(connector, edid); if (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF) num_modes += add_inferred_modes(connector, edid); @@ -4037,44 +4752,11 @@ } EXPORT_SYMBOL(drm_hdmi_vendor_infoframe_from_display_mode); -static int drm_parse_display_id(struct drm_connector *connector, - u8 *displayid, int length, - bool is_edid_extension) +static int drm_parse_tiled_block(struct drm_connector *connector, + struct displayid_block *block) { - /* if this is an EDID extension the first byte will be 0x70 */ - int idx = 0; - struct displayid_hdr *base; - struct displayid_block *block; - u8 csum = 0; - int i; - - if (is_edid_extension) - idx = 1; - - base = (struct displayid_hdr *)&displayid[idx]; - - DRM_DEBUG_KMS("base revision 0x%x, length %d, %d %d\n", - base->rev, base->bytes, base->prod_id, base->ext_count); - - if (base->bytes + 5 > length - idx) - return -EINVAL; - - for (i = idx; i <= base->bytes + 5; i++) { - csum += displayid[i]; - } - if (csum) { - DRM_ERROR("DisplayID checksum invalid, remainder is %d\n", csum); - return -EINVAL; - } - - block = (struct displayid_block *)&displayid[idx + 4]; - DRM_DEBUG_KMS("block id %d, rev %d, len %d\n", - block->tag, block->rev, block->num_bytes); - - switch (block->tag) { - case DATA_BLOCK_TILED_DISPLAY: { - struct displayid_tiled_block *tile = (struct displayid_tiled_block *)block; - + struct displayid_tiled_block *tile = + (struct displayid_tiled_block *)block; u16 w, h; u8 tile_v_loc, tile_h_loc; u8 num_v_tile, num_h_tile; @@ -4103,31 +4785,73 @@ DRM_DEBUG_KMS("tile_size %d x %d\n", w + 1, h + 1); DRM_DEBUG_KMS("topo num tiles %dx%d, location %dx%d\n", num_h_tile + 1, num_v_tile + 1, tile_h_loc, tile_v_loc); - DRM_DEBUG_KMS("vend %c%c%c\n", tile->topology_id[0], tile->topology_id[1], tile->topology_id[2]); + DRM_DEBUG_KMS("vend %c%c%c\n", tile->topology_id[0], + tile->topology_id[1], tile->topology_id[2]); tg = drm_mode_get_tile_group(connector->dev, tile->topology_id); - if (!tg) { - tg = drm_mode_create_tile_group(connector->dev, tile->topology_id); - } + if (!tg) + tg = drm_mode_create_tile_group(connector->dev, + tile->topology_id); + if (!tg) return -ENOMEM; if (connector->tile_group != tg) { /* if we haven't got a pointer, - take the reference, drop ref to old tile group */ - if (connector->tile_group) { - drm_mode_put_tile_group(connector->dev, connector->tile_group); - } + * take the reference, drop ref to old tile group + */ + if (connector->tile_group) + drm_mode_put_tile_group(connector->dev, + connector->tile_group); + connector->tile_group = tg; } else /* if same tile group, then release the ref we just took. */ drm_mode_put_tile_group(connector->dev, tg); + return 0; } + +static int drm_parse_display_id(struct drm_connector *connector, + u8 *displayid, int length, + bool is_edid_extension) +{ + /* if this is an EDID extension the first byte will be 0x70 */ + int idx = 0; + struct displayid_block *block; + int ret; + + if (is_edid_extension) + idx = 1; + + ret = validate_displayid(displayid, length, idx); + if (ret) + return ret; + + idx += sizeof(struct displayid_hdr); + while (block = (struct displayid_block *)&displayid[idx], + idx + sizeof(struct displayid_block) <= length && + idx + sizeof(struct displayid_block) + + block->num_bytes <= length && + block->num_bytes > 0) { + idx += block->num_bytes + sizeof(struct displayid_block); + DRM_DEBUG_KMS("block id 0x%x, rev %d, len %d\n", + block->tag, block->rev, block->num_bytes); + + switch (block->tag) { + case DATA_BLOCK_TILED_DISPLAY: + ret = drm_parse_tiled_block(connector, block); + if (ret) + return ret; + break; + case DATA_BLOCK_TYPE_1_DETAILED_TIMING: + /* handled in mode gathering code. */ break; default: - printk("unknown displayid tag %d\n", block->tag); + DRM_DEBUG_KMS("found DisplayID tag 0x%x, unhandled\n", + block->tag); break; } + } return 0; } diff -ruw linux-4.4.115/drivers/gpu/drm/drm_ioctl.c linux-4.4.115-fbx/drivers/gpu/drm/drm_ioctl.c --- linux-4.4.115/drivers/gpu/drm/drm_ioctl.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/gpu/drm/drm_ioctl.c 2019-10-29 09:26:23.605202806 +0100 @@ -312,6 +312,9 @@ case DRM_CAP_ADDFB2_MODIFIERS: req->value = dev->mode_config.allow_fb_modifiers; break; + case DRM_CAP_CRTC_IN_VBLANK_EVENT: + req->value = 1; + break; default: return -EINVAL; } diff -ruw linux-4.4.115/drivers/gpu/drm/drm_irq.c linux-4.4.115-fbx/drivers/gpu/drm/drm_irq.c --- linux-4.4.115/drivers/gpu/drm/drm_irq.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/gpu/drm/drm_irq.c 2019-10-29 09:26:23.605202806 +0100 @@ -1075,6 +1075,7 @@ e->pipe = pipe; e->event.sequence = drm_vblank_count(dev, pipe); + e->event.crtc_id = 0; list_add_tail(&e->base.link, &dev->vblank_event_list); } EXPORT_SYMBOL(drm_arm_vblank_event); @@ -1098,7 +1099,15 @@ void drm_crtc_arm_vblank_event(struct drm_crtc *crtc, struct drm_pending_vblank_event *e) { - drm_arm_vblank_event(crtc->dev, drm_crtc_index(crtc), e); + struct drm_device *dev = crtc->dev; + unsigned int pipe = drm_crtc_index(crtc); + + assert_spin_locked(&dev->event_lock); + + e->pipe = pipe; + e->event.sequence = drm_vblank_count(dev, pipe); + e->event.crtc_id = crtc->base.id; + list_add_tail(&e->base.link, &dev->vblank_event_list); } EXPORT_SYMBOL(drm_crtc_arm_vblank_event); @@ -1127,6 +1136,7 @@ now = get_drm_timestamp(); } e->pipe = pipe; + e->event.crtc_id = 0; send_vblank_event(dev, e, seq, &now); } EXPORT_SYMBOL(drm_send_vblank_event); @@ -1144,7 +1154,20 @@ void drm_crtc_send_vblank_event(struct drm_crtc *crtc, struct drm_pending_vblank_event *e) { - drm_send_vblank_event(crtc->dev, drm_crtc_index(crtc), e); + struct drm_device *dev = crtc->dev; + unsigned int seq, pipe = drm_crtc_index(crtc); + struct timeval now; + + if (dev->num_crtcs > 0) { + seq = drm_vblank_count_and_time(dev, pipe, &now); + } else { + seq = 0; + + now = get_drm_timestamp(); + } + e->pipe = pipe; + e->event.crtc_id = crtc->base.id; + send_vblank_event(dev, e, seq, &now); } EXPORT_SYMBOL(drm_crtc_send_vblank_event); diff -ruw linux-4.4.115/drivers/gpu/drm/drm_mipi_dsi.c linux-4.4.115-fbx/drivers/gpu/drm/drm_mipi_dsi.c --- linux-4.4.115/drivers/gpu/drm/drm_mipi_dsi.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/gpu/drm/drm_mipi_dsi.c 2019-01-22 16:16:23.375245247 +0100 @@ -335,7 +335,7 @@ return -EINVAL; memset(packet, 0, sizeof(*packet)); - packet->header[0] = ((msg->channel & 0x3) << 6) | (msg->type & 0x3f); + packet->header[2] = ((msg->channel & 0x3) << 6) | (msg->type & 0x3f); /* TODO: compute ECC if hardware support is not available */ @@ -347,16 +347,16 @@ * and 2. */ if (mipi_dsi_packet_format_is_long(msg->type)) { - packet->header[1] = (msg->tx_len >> 0) & 0xff; - packet->header[2] = (msg->tx_len >> 8) & 0xff; + packet->header[0] = (msg->tx_len >> 0) & 0xff; + packet->header[1] = (msg->tx_len >> 8) & 0xff; packet->payload_length = msg->tx_len; packet->payload = msg->tx_buf; } else { const u8 *tx = msg->tx_buf; - packet->header[1] = (msg->tx_len > 0) ? tx[0] : 0; - packet->header[2] = (msg->tx_len > 1) ? tx[1] : 0; + packet->header[0] = (msg->tx_len > 0) ? tx[0] : 0; + packet->header[1] = (msg->tx_len > 1) ? tx[1] : 0; } packet->size = sizeof(packet->header) + packet->payload_length; diff -ruw linux-4.4.115/drivers/gpu/drm/drm_mm.c linux-4.4.115-fbx/drivers/gpu/drm/drm_mm.c --- linux-4.4.115/drivers/gpu/drm/drm_mm.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/gpu/drm/drm_mm.c 2019-01-22 16:16:23.375245247 +0100 @@ -46,6 +46,8 @@ #include #include #include +#include +#include /** * DOC: Overview @@ -73,7 +75,8 @@ * allocations and avoiding too much fragmentation. This means free space * searches are O(num_holes). Given that all the fancy features drm_mm supports * something better would be fairly complex and since gfx thrashing is a fairly - * steep cliff not a real concern. Removing a node again is O(1). + * steep cliff not a real concern. Removing a node again is O(1). With the + * rbtree to track free holes, free hole search becomes O(log(num_holes)). * * drm_mm supports a few features: Alignment and range restrictions can be * supplied. Further more every &drm_mm_node has a color value (which is just an @@ -103,6 +106,98 @@ u64 end, enum drm_mm_search_flags flags); +#define START(node) ((node)->start) +#define LAST(node) ((node)->start + (node)->size - 1) + +INTERVAL_TREE_DEFINE(struct drm_mm_node, rb, + u64, __subtree_last, + START, LAST, static inline, drm_mm_interval_tree) + +struct drm_mm_node * +drm_mm_interval_first(struct drm_mm *mm, u64 start, u64 last) +{ + return drm_mm_interval_tree_iter_first(&mm->interval_tree, + start, last); +} +EXPORT_SYMBOL(drm_mm_interval_first); + +struct drm_mm_node * +drm_mm_interval_next(struct drm_mm_node *node, u64 start, u64 last) +{ + return drm_mm_interval_tree_iter_next(node, start, last); +} +EXPORT_SYMBOL(drm_mm_interval_next); + +static void drm_mm_interval_tree_add_node(struct drm_mm_node *hole_node, + struct drm_mm_node *node) +{ + struct drm_mm *mm = hole_node->mm; + struct rb_node **link, *rb; + struct drm_mm_node *parent; + + node->__subtree_last = LAST(node); + + if (hole_node->allocated) { + rb = &hole_node->rb; + while (rb) { + parent = rb_entry(rb, struct drm_mm_node, rb); + if (parent->__subtree_last >= node->__subtree_last) + break; + + parent->__subtree_last = node->__subtree_last; + rb = rb_parent(rb); + } + + rb = &hole_node->rb; + link = &hole_node->rb.rb_right; + } else { + rb = NULL; + link = &mm->interval_tree.rb_node; + } + + while (*link) { + rb = *link; + parent = rb_entry(rb, struct drm_mm_node, rb); + if (parent->__subtree_last < node->__subtree_last) + parent->__subtree_last = node->__subtree_last; + if (node->start < parent->start) + link = &parent->rb.rb_left; + else + link = &parent->rb.rb_right; + } + + rb_link_node(&node->rb, rb, link); + rb_insert_augmented(&node->rb, + &mm->interval_tree, + &drm_mm_interval_tree_augment); +} + +static void +rb_insert_hole_node(struct drm_mm_node *hole_node, struct drm_mm *mm) +{ + struct rb_node **new = &(mm->holes_tree.rb_node); + struct rb_node *parent = NULL; + struct drm_mm_node *cur; + + while (*new) { + parent = *new; + cur = rb_entry(parent, struct drm_mm_node, hole_node); + + if (__drm_mm_hole_node_start(hole_node) + < __drm_mm_hole_node_start(cur)) + new = &parent->rb_left; + else + new = &parent->rb_right; + } + rb_link_node(&hole_node->hole_node, parent, new); + rb_insert_color(&hole_node->hole_node, &mm->holes_tree); +} + +static void rb_erase_hole_node(struct drm_mm_node *hole_node, struct drm_mm *mm) +{ + rb_erase(&hole_node->hole_node, &mm->holes_tree); +} + static void drm_mm_insert_helper(struct drm_mm_node *hole_node, struct drm_mm_node *node, u64 size, unsigned alignment, @@ -142,6 +237,7 @@ if (adj_start == hole_start) { hole_node->hole_follows = 0; list_del(&hole_node->hole_stack); + rb_erase_hole_node(hole_node, mm); } node->start = adj_start; @@ -150,14 +246,16 @@ node->color = color; node->allocated = 1; - INIT_LIST_HEAD(&node->hole_stack); list_add(&node->node_list, &hole_node->node_list); + drm_mm_interval_tree_add_node(hole_node, node); + BUG_ON(node->start + node->size > adj_end); node->hole_follows = 0; if (__drm_mm_hole_node_start(node) < hole_end) { list_add(&node->hole_stack, &mm->hole_stack); + rb_insert_hole_node(node, mm); node->hole_follows = 1; } } @@ -178,40 +276,55 @@ */ int drm_mm_reserve_node(struct drm_mm *mm, struct drm_mm_node *node) { - struct drm_mm_node *hole; u64 end = node->start + node->size; - u64 hole_start; - u64 hole_end; + struct drm_mm_node *hole; + u64 hole_start, hole_end; - BUG_ON(node == NULL); + if (WARN_ON(node->size == 0)) + return -EINVAL; /* Find the relevant hole to add our node to */ - drm_mm_for_each_hole(hole, mm, hole_start, hole_end) { + hole = drm_mm_interval_tree_iter_first(&mm->interval_tree, + node->start, ~(u64)0); + if (hole) { + if (hole->start < end) + return -ENOSPC; + } else { + hole = list_entry(&mm->head_node.node_list, + typeof(*hole), node_list); + } + + hole = list_last_entry(&hole->node_list, typeof(*hole), node_list); + if (!hole->hole_follows) + return -ENOSPC; + + hole_start = __drm_mm_hole_node_start(hole); + hole_end = __drm_mm_hole_node_end(hole); if (hole_start > node->start || hole_end < end) - continue; + return -ENOSPC; node->mm = mm; node->allocated = 1; - INIT_LIST_HEAD(&node->hole_stack); list_add(&node->node_list, &hole->node_list); + drm_mm_interval_tree_add_node(hole, node); + if (node->start == hole_start) { hole->hole_follows = 0; - list_del_init(&hole->hole_stack); + list_del(&hole->hole_stack); + rb_erase_hole_node(hole, mm); } node->hole_follows = 0; if (end != hole_end) { list_add(&node->hole_stack, &mm->hole_stack); + rb_insert_hole_node(node, mm); node->hole_follows = 1; } return 0; } - - return -ENOSPC; -} EXPORT_SYMBOL(drm_mm_reserve_node); /** @@ -237,6 +350,9 @@ { struct drm_mm_node *hole_node; + if (WARN_ON(size == 0)) + return -EINVAL; + hole_node = drm_mm_search_free_generic(mm, size, alignment, color, sflags); if (!hole_node) @@ -287,6 +403,7 @@ if (adj_start == hole_start) { hole_node->hole_follows = 0; list_del(&hole_node->hole_stack); + rb_erase_hole_node(hole_node, mm); } node->start = adj_start; @@ -295,9 +412,10 @@ node->color = color; node->allocated = 1; - INIT_LIST_HEAD(&node->hole_stack); list_add(&node->node_list, &hole_node->node_list); + drm_mm_interval_tree_add_node(hole_node, node); + BUG_ON(node->start < start); BUG_ON(node->start < adj_start); BUG_ON(node->start + node->size > adj_end); @@ -306,6 +424,7 @@ node->hole_follows = 0; if (__drm_mm_hole_node_start(node) < hole_end) { list_add(&node->hole_stack, &mm->hole_stack); + rb_insert_hole_node(node, mm); node->hole_follows = 1; } } @@ -336,6 +455,9 @@ { struct drm_mm_node *hole_node; + if (WARN_ON(size == 0)) + return -EINVAL; + hole_node = drm_mm_search_free_in_range_generic(mm, size, alignment, color, start, end, sflags); @@ -375,6 +497,7 @@ BUG_ON(__drm_mm_hole_node_start(node) == __drm_mm_hole_node_end(node)); list_del(&node->hole_stack); + rb_erase_hole_node(node, mm); } else BUG_ON(__drm_mm_hole_node_start(node) != __drm_mm_hole_node_end(node)); @@ -383,9 +506,11 @@ if (!prev_node->hole_follows) { prev_node->hole_follows = 1; list_add(&prev_node->hole_stack, &mm->hole_stack); + rb_insert_hole_node(prev_node, mm); } else list_move(&prev_node->hole_stack, &mm->hole_stack); + drm_mm_interval_tree_remove(node, &mm->interval_tree); list_del(&node->node_list); node->allocated = 0; } @@ -408,6 +533,53 @@ return end >= start + size; } +static struct drm_mm_node *get_first_hole(const struct drm_mm *mm, + enum drm_mm_search_flags flags) +{ + if (flags & DRM_MM_SEARCH_BOTTOM_UP) { + struct rb_node *node = rb_first(&mm->holes_tree); + + if (!node) + return NULL; + + return rb_entry(node, struct drm_mm_node, hole_node); + } else if (flags & DRM_MM_SEARCH_BELOW) { + return list_entry((mm)->hole_stack.prev, + struct drm_mm_node, hole_stack); + } else { + return list_entry((mm)->hole_stack.next, + struct drm_mm_node, hole_stack); + } +} + +static struct drm_mm_node *get_next_hole(struct drm_mm_node *entry, + enum drm_mm_search_flags flags) +{ + if (flags & DRM_MM_SEARCH_BOTTOM_UP) { + struct rb_node *node = rb_next(&entry->hole_node); + + if (!node) + return NULL; + + return rb_entry(node, struct drm_mm_node, hole_node); + } else if (flags & DRM_MM_SEARCH_BELOW) { + return list_entry(entry->hole_stack.prev, + struct drm_mm_node, hole_stack); + } else { + return list_entry(entry->hole_stack.next, + struct drm_mm_node, hole_stack); + } +} + +static bool drm_mm_hole_traversal_condition(const struct drm_mm *mm, + struct drm_mm_node *entry, enum drm_mm_search_flags flags) +{ + if (flags & DRM_MM_SEARCH_BOTTOM_UP) + return entry ? 1 : 0; + else + return (&entry->hole_stack != &(mm)->hole_stack) ? 1 : 0; +} + static struct drm_mm_node *drm_mm_search_free_generic(const struct drm_mm *mm, u64 size, unsigned alignment, @@ -425,9 +597,14 @@ best = NULL; best_size = ~0UL; - __drm_mm_for_each_hole(entry, mm, adj_start, adj_end, - flags & DRM_MM_SEARCH_BELOW) { - u64 hole_size = adj_end - adj_start; + for (entry = get_first_hole(mm, flags); + drm_mm_hole_traversal_condition(mm, entry, flags); + entry = get_next_hole(entry, flags)) { + u64 hole_size; + + adj_start = drm_mm_hole_node_start(entry); + adj_end = drm_mm_hole_node_end(entry); + hole_size = adj_end - adj_start; if (mm->color_adjust) { mm->color_adjust(entry, color, &adj_start, &adj_end); @@ -469,9 +646,14 @@ best = NULL; best_size = ~0UL; - __drm_mm_for_each_hole(entry, mm, adj_start, adj_end, - flags & DRM_MM_SEARCH_BELOW) { - u64 hole_size = adj_end - adj_start; + for (entry = get_first_hole(mm, flags); + drm_mm_hole_traversal_condition(mm, entry, flags); + entry = get_next_hole(entry, flags)) { + u64 hole_size; + + adj_start = drm_mm_hole_node_start(entry); + adj_end = drm_mm_hole_node_end(entry); + hole_size = adj_end - adj_start; if (mm->color_adjust) { mm->color_adjust(entry, color, &adj_start, &adj_end); @@ -510,14 +692,21 @@ { list_replace(&old->node_list, &new->node_list); list_replace(&old->hole_stack, &new->hole_stack); + rb_replace_node(&old->rb, &new->rb, &old->mm->interval_tree); new->hole_follows = old->hole_follows; new->mm = old->mm; new->start = old->start; new->size = old->size; new->color = old->color; + new->__subtree_last = old->__subtree_last; old->allocated = 0; new->allocated = 1; + + if (old->hole_follows) + rb_replace_node(&old->hole_node, &new->hole_node, + &old->mm->holes_tree); + } EXPORT_SYMBOL(drm_mm_replace_node); @@ -742,7 +931,6 @@ /* Clever trick to avoid a special case in the free hole tracking. */ INIT_LIST_HEAD(&mm->head_node.node_list); - INIT_LIST_HEAD(&mm->head_node.hole_stack); mm->head_node.hole_follows = 1; mm->head_node.scanned_block = 0; mm->head_node.scanned_prev_free = 0; @@ -752,7 +940,10 @@ mm->head_node.size = start - mm->head_node.start; list_add_tail(&mm->head_node.hole_stack, &mm->hole_stack); + mm->interval_tree = RB_ROOT; mm->color_adjust = NULL; + mm->holes_tree = RB_ROOT; + rb_insert_hole_node(&mm->head_node, mm); } EXPORT_SYMBOL(drm_mm_init); diff -ruw linux-4.4.115/drivers/gpu/drm/drm_probe_helper.c linux-4.4.115-fbx/drivers/gpu/drm/drm_probe_helper.c --- linux-4.4.115/drivers/gpu/drm/drm_probe_helper.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/gpu/drm/drm_probe_helper.c 2019-10-29 09:26:23.605202806 +0100 @@ -199,20 +199,7 @@ goto prune; } -#ifdef CONFIG_DRM_LOAD_EDID_FIRMWARE - count = drm_load_edid_firmware(connector); - if (count == 0) -#endif - { - if (connector->override_edid) { - struct edid *edid = (struct edid *) connector->edid_blob_ptr->data; - - count = drm_add_edid_modes(connector, edid); - drm_edid_to_eld(connector, edid); - } else count = (*connector_funcs->get_modes)(connector); - } - if (count == 0 && connector->status == connector_status_connected) count = drm_add_modes_noedid(connector, 1024, 768); count += drm_helper_probe_add_cmdline_mode(connector); diff -ruw linux-4.4.115/drivers/gpu/drm/Kconfig linux-4.4.115-fbx/drivers/gpu/drm/Kconfig --- linux-4.4.115/drivers/gpu/drm/Kconfig 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/gpu/drm/Kconfig 2019-07-19 15:49:45.457091212 +0200 @@ -8,6 +8,7 @@ tristate "Direct Rendering Manager (XFree86 4.1.0 and higher DRI support)" depends on (AGP || AGP=n) && !EMULATED_CMPXCHG && MMU && HAS_DMA select HDMI + select FB select FB_CMDLINE select I2C select I2C_ALGOBIT @@ -52,7 +53,7 @@ depends on DRM select DRM_KMS_HELPER select DRM_KMS_FB_HELPER - default y + default n help Choose this option if you have a need for the legacy fbdev support. Note that this support also provides the linux console @@ -62,7 +63,7 @@ config DRM_LOAD_EDID_FIRMWARE bool "Allow to specify an EDID data set instead of probing for it" - depends on DRM_KMS_HELPER + depends on DRM help Say Y here, if you want to use EDID data to be loaded from the /lib/firmware directory or one of the provided built-in @@ -266,3 +267,5 @@ source "drivers/gpu/drm/imx/Kconfig" source "drivers/gpu/drm/vc4/Kconfig" + +source "drivers/gpu/drm/msm-hyp/Kconfig" diff -ruw linux-4.4.115/drivers/gpu/drm/Makefile linux-4.4.115-fbx/drivers/gpu/drm/Makefile --- linux-4.4.115/drivers/gpu/drm/Makefile 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/gpu/drm/Makefile 2019-07-19 15:49:45.461091250 +0200 @@ -20,12 +20,12 @@ drm-$(CONFIG_DRM_PANEL) += drm_panel.o drm-$(CONFIG_OF) += drm_of.o drm-$(CONFIG_AGP) += drm_agpsupport.o +drm-$(CONFIG_DRM_LOAD_EDID_FIRMWARE) += drm_edid_load.o drm-y += $(drm-m) drm_kms_helper-y := drm_crtc_helper.o drm_dp_helper.o drm_probe_helper.o \ drm_plane_helper.o drm_dp_mst_topology.o drm_atomic_helper.o -drm_kms_helper-$(CONFIG_DRM_LOAD_EDID_FIRMWARE) += drm_edid_load.o drm_kms_helper-$(CONFIG_DRM_FBDEV_EMULATION) += drm_fb_helper.o drm_kms_helper-$(CONFIG_DRM_KMS_CMA_HELPER) += drm_fb_cma_helper.o @@ -68,6 +68,7 @@ obj-$(CONFIG_DRM_BOCHS) += bochs/ obj-$(CONFIG_DRM_VIRTIO_GPU) += virtio/ obj-$(CONFIG_DRM_MSM) += msm/ +obj-$(CONFIG_DRM_MSM_HYP) += msm-hyp/ obj-$(CONFIG_DRM_TEGRA) += tegra/ obj-$(CONFIG_DRM_STI) += sti/ obj-$(CONFIG_DRM_IMX) += imx/ diff -ruw linux-4.4.115/drivers/gpu/drm/msm/adreno/a3xx_gpu.c linux-4.4.115-fbx/drivers/gpu/drm/msm/adreno/a3xx_gpu.c --- linux-4.4.115/drivers/gpu/drm/msm/adreno/a3xx_gpu.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/gpu/drm/msm/adreno/a3xx_gpu.c 2019-01-22 16:16:23.479246189 +0100 @@ -2,7 +2,7 @@ * Copyright (C) 2013 Red Hat * Author: Rob Clark * - * Copyright (c) 2014 The Linux Foundation. All rights reserved. + * Copyright (c) 2014,2018 The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License version 2 as published by @@ -40,10 +40,11 @@ extern bool hang_debug; static void a3xx_dump(struct msm_gpu *gpu); +static bool a3xx_idle(struct msm_gpu *gpu); -static void a3xx_me_init(struct msm_gpu *gpu) +static bool a3xx_me_init(struct msm_gpu *gpu) { - struct msm_ringbuffer *ring = gpu->rb; + struct msm_ringbuffer *ring = gpu->rb[0]; OUT_PKT3(ring, CP_ME_INIT, 17); OUT_RING(ring, 0x000003f7); @@ -64,8 +65,8 @@ OUT_RING(ring, 0x00000000); OUT_RING(ring, 0x00000000); - gpu->funcs->flush(gpu); - gpu->funcs->idle(gpu); + gpu->funcs->flush(gpu, ring); + return a3xx_idle(gpu); } static int a3xx_hw_init(struct msm_gpu *gpu) @@ -294,9 +295,7 @@ /* clear ME_HALT to start micro engine */ gpu_write(gpu, REG_AXXX_CP_ME_CNTL, 0); - a3xx_me_init(gpu); - - return 0; + return a3xx_me_init(gpu) ? 0 : -EINVAL; } static void a3xx_recover(struct msm_gpu *gpu) @@ -330,17 +329,22 @@ kfree(a3xx_gpu); } -static void a3xx_idle(struct msm_gpu *gpu) +static bool a3xx_idle(struct msm_gpu *gpu) { /* wait for ringbuffer to drain: */ - adreno_idle(gpu); + if (!adreno_idle(gpu, gpu->rb[0])) + return false; /* then wait for GPU to finish: */ if (spin_until(!(gpu_read(gpu, REG_A3XX_RBBM_STATUS) & - A3XX_RBBM_STATUS_GPU_BUSY))) + A3XX_RBBM_STATUS_GPU_BUSY))) { DRM_ERROR("%s: timeout waiting for GPU to idle!\n", gpu->name); /* TODO maybe we need to reset GPU here to recover from hang? */ + return false; + } + + return true; } static irqreturn_t a3xx_irq(struct msm_gpu *gpu) @@ -402,10 +406,8 @@ #ifdef CONFIG_DEBUG_FS static void a3xx_show(struct msm_gpu *gpu, struct seq_file *m) { - gpu->funcs->pm_resume(gpu); seq_printf(m, "status: %08x\n", gpu_read(gpu, REG_A3XX_RBBM_STATUS)); - gpu->funcs->pm_suspend(gpu); adreno_show(gpu, m); } #endif @@ -419,91 +421,13 @@ } /* Register offset defines for A3XX */ static const unsigned int a3xx_register_offsets[REG_ADRENO_REGISTER_MAX] = { - REG_ADRENO_DEFINE(REG_ADRENO_CP_DEBUG, REG_AXXX_CP_DEBUG), - REG_ADRENO_DEFINE(REG_ADRENO_CP_ME_RAM_WADDR, REG_AXXX_CP_ME_RAM_WADDR), - REG_ADRENO_DEFINE(REG_ADRENO_CP_ME_RAM_DATA, REG_AXXX_CP_ME_RAM_DATA), - REG_ADRENO_DEFINE(REG_ADRENO_CP_PFP_UCODE_DATA, - REG_A3XX_CP_PFP_UCODE_DATA), - REG_ADRENO_DEFINE(REG_ADRENO_CP_PFP_UCODE_ADDR, - REG_A3XX_CP_PFP_UCODE_ADDR), - REG_ADRENO_DEFINE(REG_ADRENO_CP_WFI_PEND_CTR, REG_A3XX_CP_WFI_PEND_CTR), REG_ADRENO_DEFINE(REG_ADRENO_CP_RB_BASE, REG_AXXX_CP_RB_BASE), + REG_ADRENO_SKIP(REG_ADRENO_CP_RB_BASE_HI), REG_ADRENO_DEFINE(REG_ADRENO_CP_RB_RPTR_ADDR, REG_AXXX_CP_RB_RPTR_ADDR), + REG_ADRENO_SKIP(REG_ADRENO_CP_RB_RPTR_ADDR_HI), REG_ADRENO_DEFINE(REG_ADRENO_CP_RB_RPTR, REG_AXXX_CP_RB_RPTR), REG_ADRENO_DEFINE(REG_ADRENO_CP_RB_WPTR, REG_AXXX_CP_RB_WPTR), - REG_ADRENO_DEFINE(REG_ADRENO_CP_PROTECT_CTRL, REG_A3XX_CP_PROTECT_CTRL), - REG_ADRENO_DEFINE(REG_ADRENO_CP_ME_CNTL, REG_AXXX_CP_ME_CNTL), REG_ADRENO_DEFINE(REG_ADRENO_CP_RB_CNTL, REG_AXXX_CP_RB_CNTL), - REG_ADRENO_DEFINE(REG_ADRENO_CP_IB1_BASE, REG_AXXX_CP_IB1_BASE), - REG_ADRENO_DEFINE(REG_ADRENO_CP_IB1_BUFSZ, REG_AXXX_CP_IB1_BUFSZ), - REG_ADRENO_DEFINE(REG_ADRENO_CP_IB2_BASE, REG_AXXX_CP_IB2_BASE), - REG_ADRENO_DEFINE(REG_ADRENO_CP_IB2_BUFSZ, REG_AXXX_CP_IB2_BUFSZ), - REG_ADRENO_DEFINE(REG_ADRENO_CP_TIMESTAMP, REG_AXXX_CP_SCRATCH_REG0), - REG_ADRENO_DEFINE(REG_ADRENO_CP_ME_RAM_RADDR, REG_AXXX_CP_ME_RAM_RADDR), - REG_ADRENO_DEFINE(REG_ADRENO_SCRATCH_ADDR, REG_AXXX_SCRATCH_ADDR), - REG_ADRENO_DEFINE(REG_ADRENO_SCRATCH_UMSK, REG_AXXX_SCRATCH_UMSK), - REG_ADRENO_DEFINE(REG_ADRENO_CP_ROQ_ADDR, REG_A3XX_CP_ROQ_ADDR), - REG_ADRENO_DEFINE(REG_ADRENO_CP_ROQ_DATA, REG_A3XX_CP_ROQ_DATA), - REG_ADRENO_DEFINE(REG_ADRENO_CP_MERCIU_ADDR, REG_A3XX_CP_MERCIU_ADDR), - REG_ADRENO_DEFINE(REG_ADRENO_CP_MERCIU_DATA, REG_A3XX_CP_MERCIU_DATA), - REG_ADRENO_DEFINE(REG_ADRENO_CP_MERCIU_DATA2, REG_A3XX_CP_MERCIU_DATA2), - REG_ADRENO_DEFINE(REG_ADRENO_CP_MEQ_ADDR, REG_A3XX_CP_MEQ_ADDR), - REG_ADRENO_DEFINE(REG_ADRENO_CP_MEQ_DATA, REG_A3XX_CP_MEQ_DATA), - REG_ADRENO_DEFINE(REG_ADRENO_CP_HW_FAULT, REG_A3XX_CP_HW_FAULT), - REG_ADRENO_DEFINE(REG_ADRENO_CP_PROTECT_STATUS, - REG_A3XX_CP_PROTECT_STATUS), - REG_ADRENO_DEFINE(REG_ADRENO_RBBM_STATUS, REG_A3XX_RBBM_STATUS), - REG_ADRENO_DEFINE(REG_ADRENO_RBBM_PERFCTR_CTL, - REG_A3XX_RBBM_PERFCTR_CTL), - REG_ADRENO_DEFINE(REG_ADRENO_RBBM_PERFCTR_LOAD_CMD0, - REG_A3XX_RBBM_PERFCTR_LOAD_CMD0), - REG_ADRENO_DEFINE(REG_ADRENO_RBBM_PERFCTR_LOAD_CMD1, - REG_A3XX_RBBM_PERFCTR_LOAD_CMD1), - REG_ADRENO_DEFINE(REG_ADRENO_RBBM_PERFCTR_PWR_1_LO, - REG_A3XX_RBBM_PERFCTR_PWR_1_LO), - REG_ADRENO_DEFINE(REG_ADRENO_RBBM_INT_0_MASK, REG_A3XX_RBBM_INT_0_MASK), - REG_ADRENO_DEFINE(REG_ADRENO_RBBM_INT_0_STATUS, - REG_A3XX_RBBM_INT_0_STATUS), - REG_ADRENO_DEFINE(REG_ADRENO_RBBM_AHB_ERROR_STATUS, - REG_A3XX_RBBM_AHB_ERROR_STATUS), - REG_ADRENO_DEFINE(REG_ADRENO_RBBM_AHB_CMD, REG_A3XX_RBBM_AHB_CMD), - REG_ADRENO_DEFINE(REG_ADRENO_RBBM_INT_CLEAR_CMD, - REG_A3XX_RBBM_INT_CLEAR_CMD), - REG_ADRENO_DEFINE(REG_ADRENO_RBBM_CLOCK_CTL, REG_A3XX_RBBM_CLOCK_CTL), - REG_ADRENO_DEFINE(REG_ADRENO_VPC_DEBUG_RAM_SEL, - REG_A3XX_VPC_VPC_DEBUG_RAM_SEL), - REG_ADRENO_DEFINE(REG_ADRENO_VPC_DEBUG_RAM_READ, - REG_A3XX_VPC_VPC_DEBUG_RAM_READ), - REG_ADRENO_DEFINE(REG_ADRENO_VSC_SIZE_ADDRESS, - REG_A3XX_VSC_SIZE_ADDRESS), - REG_ADRENO_DEFINE(REG_ADRENO_VFD_CONTROL_0, REG_A3XX_VFD_CONTROL_0), - REG_ADRENO_DEFINE(REG_ADRENO_VFD_INDEX_MAX, REG_A3XX_VFD_INDEX_MAX), - REG_ADRENO_DEFINE(REG_ADRENO_SP_VS_PVT_MEM_ADDR_REG, - REG_A3XX_SP_VS_PVT_MEM_ADDR_REG), - REG_ADRENO_DEFINE(REG_ADRENO_SP_FS_PVT_MEM_ADDR_REG, - REG_A3XX_SP_FS_PVT_MEM_ADDR_REG), - REG_ADRENO_DEFINE(REG_ADRENO_SP_VS_OBJ_START_REG, - REG_A3XX_SP_VS_OBJ_START_REG), - REG_ADRENO_DEFINE(REG_ADRENO_SP_FS_OBJ_START_REG, - REG_A3XX_SP_FS_OBJ_START_REG), - REG_ADRENO_DEFINE(REG_ADRENO_PA_SC_AA_CONFIG, REG_A3XX_PA_SC_AA_CONFIG), - REG_ADRENO_DEFINE(REG_ADRENO_RBBM_PM_OVERRIDE2, - REG_A3XX_RBBM_PM_OVERRIDE2), - REG_ADRENO_DEFINE(REG_ADRENO_SCRATCH_REG2, REG_AXXX_CP_SCRATCH_REG2), - REG_ADRENO_DEFINE(REG_ADRENO_SQ_GPR_MANAGEMENT, - REG_A3XX_SQ_GPR_MANAGEMENT), - REG_ADRENO_DEFINE(REG_ADRENO_SQ_INST_STORE_MANAGMENT, - REG_A3XX_SQ_INST_STORE_MANAGMENT), - REG_ADRENO_DEFINE(REG_ADRENO_TP0_CHICKEN, REG_A3XX_TP0_CHICKEN), - REG_ADRENO_DEFINE(REG_ADRENO_RBBM_RBBM_CTL, REG_A3XX_RBBM_RBBM_CTL), - REG_ADRENO_DEFINE(REG_ADRENO_RBBM_SW_RESET_CMD, - REG_A3XX_RBBM_SW_RESET_CMD), - REG_ADRENO_DEFINE(REG_ADRENO_UCHE_INVALIDATE0, - REG_A3XX_UCHE_CACHE_INVALIDATE0_REG), - REG_ADRENO_DEFINE(REG_ADRENO_RBBM_PERFCTR_LOAD_VALUE_LO, - REG_A3XX_RBBM_PERFCTR_LOAD_VALUE_LO), - REG_ADRENO_DEFINE(REG_ADRENO_RBBM_PERFCTR_LOAD_VALUE_HI, - REG_A3XX_RBBM_PERFCTR_LOAD_VALUE_HI), }; static const struct adreno_gpu_funcs funcs = { @@ -513,10 +437,10 @@ .pm_suspend = msm_gpu_pm_suspend, .pm_resume = msm_gpu_pm_resume, .recover = a3xx_recover, - .last_fence = adreno_last_fence, + .submitted_fence = adreno_submitted_fence, .submit = adreno_submit, .flush = adreno_flush, - .idle = a3xx_idle, + .active_ring = adreno_active_ring, .irq = a3xx_irq, .destroy = a3xx_destroy, #ifdef CONFIG_DEBUG_FS @@ -539,6 +463,7 @@ struct msm_gpu *gpu; struct msm_drm_private *priv = dev->dev_private; struct platform_device *pdev = priv->gpu_pdev; + struct msm_gpu_config a3xx_config = { 0 }; int ret; if (!pdev) { @@ -556,15 +481,19 @@ adreno_gpu = &a3xx_gpu->base; gpu = &adreno_gpu->base; - a3xx_gpu->pdev = pdev; - gpu->perfcntrs = perfcntrs; gpu->num_perfcntrs = ARRAY_SIZE(perfcntrs); adreno_gpu->registers = a3xx_registers; adreno_gpu->reg_offsets = a3xx_register_offsets; - ret = adreno_gpu_init(dev, pdev, adreno_gpu, &funcs); + a3xx_config.ioname = MSM_GPU_DEFAULT_IONAME; + a3xx_config.irqname = MSM_GPU_DEFAULT_IRQNAME; + a3xx_config.nr_rings = 1; + a3xx_config.va_start = 0x300000; + a3xx_config.va_end = 0xffffffff; + + ret = adreno_gpu_init(dev, pdev, adreno_gpu, &funcs, &a3xx_config); if (ret) goto fail; @@ -583,7 +512,7 @@ #endif } - if (!gpu->mmu) { + if (!gpu->aspace) { /* TODO we think it is possible to configure the GPU to * restrict access to VRAM carveout. But the required * registers are unknown. For now just bail out and diff -ruw linux-4.4.115/drivers/gpu/drm/msm/adreno/a3xx_gpu.h linux-4.4.115-fbx/drivers/gpu/drm/msm/adreno/a3xx_gpu.h --- linux-4.4.115/drivers/gpu/drm/msm/adreno/a3xx_gpu.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/gpu/drm/msm/adreno/a3xx_gpu.h 2019-01-22 16:16:23.479246189 +0100 @@ -2,6 +2,8 @@ * Copyright (C) 2013 Red Hat * Author: Rob Clark * + * Copyright (c) 2018 The Linux Foundation. All rights reserved. + * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License version 2 as published by * the Free Software Foundation. @@ -28,7 +30,6 @@ struct a3xx_gpu { struct adreno_gpu base; - struct platform_device *pdev; /* if OCMEM is used for GMEM: */ uint32_t ocmem_base; diff -ruw linux-4.4.115/drivers/gpu/drm/msm/adreno/a3xx.xml.h linux-4.4.115-fbx/drivers/gpu/drm/msm/adreno/a3xx.xml.h --- linux-4.4.115/drivers/gpu/drm/msm/adreno/a3xx.xml.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/gpu/drm/msm/adreno/a3xx.xml.h 2019-01-22 16:16:23.479246189 +0100 @@ -8,17 +8,19 @@ git clone https://github.com/freedreno/envytools.git The rules-ng-ng source files this header was generated from are: -- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 398 bytes, from 2015-09-24 17:25:31) -- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2015-05-20 20:03:07) -- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 32901 bytes, from 2015-05-20 20:03:14) -- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 10755 bytes, from 2015-09-14 20:46:55) -- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 14968 bytes, from 2015-05-20 20:12:27) -- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 67771 bytes, from 2015-09-14 20:46:55) -- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 63970 bytes, from 2015-09-14 20:50:12) -- /home/robclark/src/freedreno/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2015-09-24 17:30:00) +- ./adreno.xml ( 431 bytes, from 2016-10-24 21:12:27) +- ./freedreno_copyright.xml ( 1572 bytes, from 2016-10-24 21:12:27) +- ./adreno/a2xx.xml ( 32901 bytes, from 2016-10-24 21:12:27) +- ./adreno/adreno_common.xml ( 12025 bytes, from 2016-10-24 21:12:27) +- ./adreno/adreno_pm4.xml ( 19684 bytes, from 2016-10-24 21:12:27) +- ./adreno/a3xx.xml ( 83840 bytes, from 2016-10-24 21:12:27) +- ./adreno/a4xx.xml ( 110708 bytes, from 2016-10-24 21:12:27) +- ./adreno/a5xx.xml ( 81207 bytes, from 2016-10-26 19:36:59) +- ./adreno/ocmem.xml ( 1773 bytes, from 2016-10-24 21:12:27) -Copyright (C) 2013-2015 by the following authors: +Copyright (C) 2013-2016 by the following authors: - Rob Clark (robclark) +- Ilia Mirkin (imirkin) Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the @@ -111,10 +113,14 @@ VFMT_8_8_SNORM = 53, VFMT_8_8_8_SNORM = 54, VFMT_8_8_8_8_SNORM = 55, - VFMT_10_10_10_2_UINT = 60, - VFMT_10_10_10_2_UNORM = 61, - VFMT_10_10_10_2_SINT = 62, - VFMT_10_10_10_2_SNORM = 63, + VFMT_10_10_10_2_UINT = 56, + VFMT_10_10_10_2_UNORM = 57, + VFMT_10_10_10_2_SINT = 58, + VFMT_10_10_10_2_SNORM = 59, + VFMT_2_10_10_10_UINT = 60, + VFMT_2_10_10_10_UNORM = 61, + VFMT_2_10_10_10_SINT = 62, + VFMT_2_10_10_10_SNORM = 63, }; enum a3xx_tex_fmt { @@ -124,10 +130,14 @@ TFMT_Z16_UNORM = 9, TFMT_X8Z24_UNORM = 10, TFMT_Z32_FLOAT = 11, - TFMT_NV12_UV_TILED = 17, - TFMT_NV12_Y_TILED = 19, - TFMT_NV12_UV = 21, - TFMT_NV12_Y = 23, + TFMT_UV_64X32 = 16, + TFMT_VU_64X32 = 17, + TFMT_Y_64X32 = 18, + TFMT_NV12_64X32 = 19, + TFMT_UV_LINEAR = 20, + TFMT_VU_LINEAR = 21, + TFMT_Y_LINEAR = 22, + TFMT_NV12_LINEAR = 23, TFMT_I420_Y = 24, TFMT_I420_U = 26, TFMT_I420_V = 27, @@ -138,10 +148,12 @@ TFMT_DXT1 = 36, TFMT_DXT3 = 37, TFMT_DXT5 = 38, + TFMT_2_10_10_10_UNORM = 40, TFMT_10_10_10_2_UNORM = 41, TFMT_9_9_9_E5_FLOAT = 42, TFMT_11_11_10_FLOAT = 43, TFMT_A8_UNORM = 44, + TFMT_L8_UNORM = 45, TFMT_L8_A8_UNORM = 47, TFMT_8_UNORM = 48, TFMT_8_8_UNORM = 49, @@ -183,6 +195,8 @@ TFMT_32_SINT = 92, TFMT_32_32_SINT = 93, TFMT_32_32_32_32_SINT = 95, + TFMT_2_10_10_10_UINT = 96, + TFMT_10_10_10_2_UINT = 97, TFMT_ETC2_RG11_SNORM = 112, TFMT_ETC2_RG11_UNORM = 113, TFMT_ETC2_R11_SNORM = 114, @@ -215,6 +229,9 @@ RB_R8_UINT = 14, RB_R8_SINT = 15, RB_R10G10B10A2_UNORM = 16, + RB_A2R10G10B10_UNORM = 17, + RB_R10G10B10A2_UINT = 18, + RB_A2R10G10B10_UINT = 19, RB_A8_UNORM = 20, RB_R8_UNORM = 21, RB_R16_FLOAT = 24, @@ -244,38 +261,273 @@ RB_R32G32B32A32_UINT = 59, }; +enum a3xx_cp_perfcounter_select { + CP_ALWAYS_COUNT = 0, + CP_AHB_PFPTRANS_WAIT = 3, + CP_AHB_NRTTRANS_WAIT = 6, + CP_CSF_NRT_READ_WAIT = 8, + CP_CSF_I1_FIFO_FULL = 9, + CP_CSF_I2_FIFO_FULL = 10, + CP_CSF_ST_FIFO_FULL = 11, + CP_RESERVED_12 = 12, + CP_CSF_RING_ROQ_FULL = 13, + CP_CSF_I1_ROQ_FULL = 14, + CP_CSF_I2_ROQ_FULL = 15, + CP_CSF_ST_ROQ_FULL = 16, + CP_RESERVED_17 = 17, + CP_MIU_TAG_MEM_FULL = 18, + CP_MIU_NRT_WRITE_STALLED = 22, + CP_MIU_NRT_READ_STALLED = 23, + CP_ME_REGS_RB_DONE_FIFO_FULL = 26, + CP_ME_REGS_VS_EVENT_FIFO_FULL = 27, + CP_ME_REGS_PS_EVENT_FIFO_FULL = 28, + CP_ME_REGS_CF_EVENT_FIFO_FULL = 29, + CP_ME_MICRO_RB_STARVED = 30, + CP_AHB_RBBM_DWORD_SENT = 40, + CP_ME_BUSY_CLOCKS = 41, + CP_ME_WAIT_CONTEXT_AVAIL = 42, + CP_PFP_TYPE0_PACKET = 43, + CP_PFP_TYPE3_PACKET = 44, + CP_CSF_RB_WPTR_NEQ_RPTR = 45, + CP_CSF_I1_SIZE_NEQ_ZERO = 46, + CP_CSF_I2_SIZE_NEQ_ZERO = 47, + CP_CSF_RBI1I2_FETCHING = 48, +}; + +enum a3xx_gras_tse_perfcounter_select { + GRAS_TSEPERF_INPUT_PRIM = 0, + GRAS_TSEPERF_INPUT_NULL_PRIM = 1, + GRAS_TSEPERF_TRIVAL_REJ_PRIM = 2, + GRAS_TSEPERF_CLIPPED_PRIM = 3, + GRAS_TSEPERF_NEW_PRIM = 4, + GRAS_TSEPERF_ZERO_AREA_PRIM = 5, + GRAS_TSEPERF_FACENESS_CULLED_PRIM = 6, + GRAS_TSEPERF_ZERO_PIXEL_PRIM = 7, + GRAS_TSEPERF_OUTPUT_NULL_PRIM = 8, + GRAS_TSEPERF_OUTPUT_VISIBLE_PRIM = 9, + GRAS_TSEPERF_PRE_CLIP_PRIM = 10, + GRAS_TSEPERF_POST_CLIP_PRIM = 11, + GRAS_TSEPERF_WORKING_CYCLES = 12, + GRAS_TSEPERF_PC_STARVE = 13, + GRAS_TSERASPERF_STALL = 14, +}; + +enum a3xx_gras_ras_perfcounter_select { + GRAS_RASPERF_16X16_TILES = 0, + GRAS_RASPERF_8X8_TILES = 1, + GRAS_RASPERF_4X4_TILES = 2, + GRAS_RASPERF_WORKING_CYCLES = 3, + GRAS_RASPERF_STALL_CYCLES_BY_RB = 4, + GRAS_RASPERF_STALL_CYCLES_BY_VSC = 5, + GRAS_RASPERF_STARVE_CYCLES_BY_TSE = 6, +}; + +enum a3xx_hlsq_perfcounter_select { + HLSQ_PERF_SP_VS_CONSTANT = 0, + HLSQ_PERF_SP_VS_INSTRUCTIONS = 1, + HLSQ_PERF_SP_FS_CONSTANT = 2, + HLSQ_PERF_SP_FS_INSTRUCTIONS = 3, + HLSQ_PERF_TP_STATE = 4, + HLSQ_PERF_QUADS = 5, + HLSQ_PERF_PIXELS = 6, + HLSQ_PERF_VERTICES = 7, + HLSQ_PERF_FS8_THREADS = 8, + HLSQ_PERF_FS16_THREADS = 9, + HLSQ_PERF_FS32_THREADS = 10, + HLSQ_PERF_VS8_THREADS = 11, + HLSQ_PERF_VS16_THREADS = 12, + HLSQ_PERF_SP_VS_DATA_BYTES = 13, + HLSQ_PERF_SP_FS_DATA_BYTES = 14, + HLSQ_PERF_ACTIVE_CYCLES = 15, + HLSQ_PERF_STALL_CYCLES_SP_STATE = 16, + HLSQ_PERF_STALL_CYCLES_SP_VS = 17, + HLSQ_PERF_STALL_CYCLES_SP_FS = 18, + HLSQ_PERF_STALL_CYCLES_UCHE = 19, + HLSQ_PERF_RBBM_LOAD_CYCLES = 20, + HLSQ_PERF_DI_TO_VS_START_SP0 = 21, + HLSQ_PERF_DI_TO_FS_START_SP0 = 22, + HLSQ_PERF_VS_START_TO_DONE_SP0 = 23, + HLSQ_PERF_FS_START_TO_DONE_SP0 = 24, + HLSQ_PERF_SP_STATE_COPY_CYCLES_VS = 25, + HLSQ_PERF_SP_STATE_COPY_CYCLES_FS = 26, + HLSQ_PERF_UCHE_LATENCY_CYCLES = 27, + HLSQ_PERF_UCHE_LATENCY_COUNT = 28, +}; + +enum a3xx_pc_perfcounter_select { + PC_PCPERF_VISIBILITY_STREAMS = 0, + PC_PCPERF_TOTAL_INSTANCES = 1, + PC_PCPERF_PRIMITIVES_PC_VPC = 2, + PC_PCPERF_PRIMITIVES_KILLED_BY_VS = 3, + PC_PCPERF_PRIMITIVES_VISIBLE_BY_VS = 4, + PC_PCPERF_DRAWCALLS_KILLED_BY_VS = 5, + PC_PCPERF_DRAWCALLS_VISIBLE_BY_VS = 6, + PC_PCPERF_VERTICES_TO_VFD = 7, + PC_PCPERF_REUSED_VERTICES = 8, + PC_PCPERF_CYCLES_STALLED_BY_VFD = 9, + PC_PCPERF_CYCLES_STALLED_BY_TSE = 10, + PC_PCPERF_CYCLES_STALLED_BY_VBIF = 11, + PC_PCPERF_CYCLES_IS_WORKING = 12, +}; + +enum a3xx_rb_perfcounter_select { + RB_RBPERF_ACTIVE_CYCLES_ANY = 0, + RB_RBPERF_ACTIVE_CYCLES_ALL = 1, + RB_RBPERF_STARVE_CYCLES_BY_SP = 2, + RB_RBPERF_STARVE_CYCLES_BY_RAS = 3, + RB_RBPERF_STARVE_CYCLES_BY_MARB = 4, + RB_RBPERF_STALL_CYCLES_BY_MARB = 5, + RB_RBPERF_STALL_CYCLES_BY_HLSQ = 6, + RB_RBPERF_RB_MARB_DATA = 7, + RB_RBPERF_SP_RB_QUAD = 8, + RB_RBPERF_RAS_EARLY_Z_QUADS = 9, + RB_RBPERF_GMEM_CH0_READ = 10, + RB_RBPERF_GMEM_CH1_READ = 11, + RB_RBPERF_GMEM_CH0_WRITE = 12, + RB_RBPERF_GMEM_CH1_WRITE = 13, + RB_RBPERF_CP_CONTEXT_DONE = 14, + RB_RBPERF_CP_CACHE_FLUSH = 15, + RB_RBPERF_CP_ZPASS_DONE = 16, +}; + +enum a3xx_rbbm_perfcounter_select { + RBBM_ALAWYS_ON = 0, + RBBM_VBIF_BUSY = 1, + RBBM_TSE_BUSY = 2, + RBBM_RAS_BUSY = 3, + RBBM_PC_DCALL_BUSY = 4, + RBBM_PC_VSD_BUSY = 5, + RBBM_VFD_BUSY = 6, + RBBM_VPC_BUSY = 7, + RBBM_UCHE_BUSY = 8, + RBBM_VSC_BUSY = 9, + RBBM_HLSQ_BUSY = 10, + RBBM_ANY_RB_BUSY = 11, + RBBM_ANY_TEX_BUSY = 12, + RBBM_ANY_USP_BUSY = 13, + RBBM_ANY_MARB_BUSY = 14, + RBBM_ANY_ARB_BUSY = 15, + RBBM_AHB_STATUS_BUSY = 16, + RBBM_AHB_STATUS_STALLED = 17, + RBBM_AHB_STATUS_TXFR = 18, + RBBM_AHB_STATUS_TXFR_SPLIT = 19, + RBBM_AHB_STATUS_TXFR_ERROR = 20, + RBBM_AHB_STATUS_LONG_STALL = 21, + RBBM_RBBM_STATUS_MASKED = 22, +}; + enum a3xx_sp_perfcounter_select { + SP_LM_LOAD_INSTRUCTIONS = 0, + SP_LM_STORE_INSTRUCTIONS = 1, + SP_LM_ATOMICS = 2, + SP_UCHE_LOAD_INSTRUCTIONS = 3, + SP_UCHE_STORE_INSTRUCTIONS = 4, + SP_UCHE_ATOMICS = 5, + SP_VS_TEX_INSTRUCTIONS = 6, + SP_VS_CFLOW_INSTRUCTIONS = 7, + SP_VS_EFU_INSTRUCTIONS = 8, + SP_VS_FULL_ALU_INSTRUCTIONS = 9, + SP_VS_HALF_ALU_INSTRUCTIONS = 10, + SP_FS_TEX_INSTRUCTIONS = 11, SP_FS_CFLOW_INSTRUCTIONS = 12, + SP_FS_EFU_INSTRUCTIONS = 13, SP_FS_FULL_ALU_INSTRUCTIONS = 14, - SP0_ICL1_MISSES = 26, + SP_FS_HALF_ALU_INSTRUCTIONS = 15, + SP_FS_BARY_INSTRUCTIONS = 16, + SP_VS_INSTRUCTIONS = 17, + SP_FS_INSTRUCTIONS = 18, + SP_ADDR_LOCK_COUNT = 19, + SP_UCHE_READ_TRANS = 20, + SP_UCHE_WRITE_TRANS = 21, + SP_EXPORT_VPC_TRANS = 22, + SP_EXPORT_RB_TRANS = 23, + SP_PIXELS_KILLED = 24, + SP_ICL1_REQUESTS = 25, + SP_ICL1_MISSES = 26, + SP_ICL0_REQUESTS = 27, + SP_ICL0_MISSES = 28, SP_ALU_ACTIVE_CYCLES = 29, + SP_EFU_ACTIVE_CYCLES = 30, + SP_STALL_CYCLES_BY_VPC = 31, + SP_STALL_CYCLES_BY_TP = 32, + SP_STALL_CYCLES_BY_UCHE = 33, + SP_STALL_CYCLES_BY_RB = 34, + SP_ACTIVE_CYCLES_ANY = 35, + SP_ACTIVE_CYCLES_ALL = 36, +}; + +enum a3xx_tp_perfcounter_select { + TPL1_TPPERF_L1_REQUESTS = 0, + TPL1_TPPERF_TP0_L1_REQUESTS = 1, + TPL1_TPPERF_TP0_L1_MISSES = 2, + TPL1_TPPERF_TP1_L1_REQUESTS = 3, + TPL1_TPPERF_TP1_L1_MISSES = 4, + TPL1_TPPERF_TP2_L1_REQUESTS = 5, + TPL1_TPPERF_TP2_L1_MISSES = 6, + TPL1_TPPERF_TP3_L1_REQUESTS = 7, + TPL1_TPPERF_TP3_L1_MISSES = 8, + TPL1_TPPERF_OUTPUT_TEXELS_POINT = 9, + TPL1_TPPERF_OUTPUT_TEXELS_BILINEAR = 10, + TPL1_TPPERF_OUTPUT_TEXELS_MIP = 11, + TPL1_TPPERF_OUTPUT_TEXELS_ANISO = 12, + TPL1_TPPERF_BILINEAR_OPS = 13, + TPL1_TPPERF_QUADSQUADS_OFFSET = 14, + TPL1_TPPERF_QUADQUADS_SHADOW = 15, + TPL1_TPPERF_QUADS_ARRAY = 16, + TPL1_TPPERF_QUADS_PROJECTION = 17, + TPL1_TPPERF_QUADS_GRADIENT = 18, + TPL1_TPPERF_QUADS_1D2D = 19, + TPL1_TPPERF_QUADS_3DCUBE = 20, + TPL1_TPPERF_ZERO_LOD = 21, + TPL1_TPPERF_OUTPUT_TEXELS = 22, + TPL1_TPPERF_ACTIVE_CYCLES_ANY = 23, + TPL1_TPPERF_ACTIVE_CYCLES_ALL = 24, + TPL1_TPPERF_STALL_CYCLES_BY_ARB = 25, + TPL1_TPPERF_LATENCY = 26, + TPL1_TPPERF_LATENCY_TRANS = 27, }; -enum a3xx_rop_code { - ROP_CLEAR = 0, - ROP_NOR = 1, - ROP_AND_INVERTED = 2, - ROP_COPY_INVERTED = 3, - ROP_AND_REVERSE = 4, - ROP_INVERT = 5, - ROP_XOR = 6, - ROP_NAND = 7, - ROP_AND = 8, - ROP_EQUIV = 9, - ROP_NOOP = 10, - ROP_OR_INVERTED = 11, - ROP_COPY = 12, - ROP_OR_REVERSE = 13, - ROP_OR = 14, - ROP_SET = 15, -}; - -enum a3xx_rb_blend_opcode { - BLEND_DST_PLUS_SRC = 0, - BLEND_SRC_MINUS_DST = 1, - BLEND_DST_MINUS_SRC = 2, - BLEND_MIN_DST_SRC = 3, - BLEND_MAX_DST_SRC = 4, +enum a3xx_vfd_perfcounter_select { + VFD_PERF_UCHE_BYTE_FETCHED = 0, + VFD_PERF_UCHE_TRANS = 1, + VFD_PERF_VPC_BYPASS_COMPONENTS = 2, + VFD_PERF_FETCH_INSTRUCTIONS = 3, + VFD_PERF_DECODE_INSTRUCTIONS = 4, + VFD_PERF_ACTIVE_CYCLES = 5, + VFD_PERF_STALL_CYCLES_UCHE = 6, + VFD_PERF_STALL_CYCLES_HLSQ = 7, + VFD_PERF_STALL_CYCLES_VPC_BYPASS = 8, + VFD_PERF_STALL_CYCLES_VPC_ALLOC = 9, +}; + +enum a3xx_vpc_perfcounter_select { + VPC_PERF_SP_LM_PRIMITIVES = 0, + VPC_PERF_COMPONENTS_FROM_SP = 1, + VPC_PERF_SP_LM_COMPONENTS = 2, + VPC_PERF_ACTIVE_CYCLES = 3, + VPC_PERF_STALL_CYCLES_LM = 4, + VPC_PERF_STALL_CYCLES_RAS = 5, +}; + +enum a3xx_uche_perfcounter_select { + UCHE_UCHEPERF_VBIF_READ_BEATS_TP = 0, + UCHE_UCHEPERF_VBIF_READ_BEATS_VFD = 1, + UCHE_UCHEPERF_VBIF_READ_BEATS_HLSQ = 2, + UCHE_UCHEPERF_VBIF_READ_BEATS_MARB = 3, + UCHE_UCHEPERF_VBIF_READ_BEATS_SP = 4, + UCHE_UCHEPERF_READ_REQUESTS_TP = 8, + UCHE_UCHEPERF_READ_REQUESTS_VFD = 9, + UCHE_UCHEPERF_READ_REQUESTS_HLSQ = 10, + UCHE_UCHEPERF_READ_REQUESTS_MARB = 11, + UCHE_UCHEPERF_READ_REQUESTS_SP = 12, + UCHE_UCHEPERF_WRITE_REQUESTS_MARB = 13, + UCHE_UCHEPERF_WRITE_REQUESTS_SP = 14, + UCHE_UCHEPERF_TAG_CHECK_FAILS = 15, + UCHE_UCHEPERF_EVICTS = 16, + UCHE_UCHEPERF_FLUSHES = 17, + UCHE_UCHEPERF_VBIF_LATENCY_CYCLES = 18, + UCHE_UCHEPERF_VBIF_LATENCY_SAMPLES = 19, + UCHE_UCHEPERF_ACTIVE_CYCLES = 20, }; enum a3xx_intp_mode { @@ -1138,13 +1390,14 @@ { return ((val) << A3XX_RB_COPY_CONTROL_MODE__SHIFT) & A3XX_RB_COPY_CONTROL_MODE__MASK; } +#define A3XX_RB_COPY_CONTROL_MSAA_SRGB_DOWNSAMPLE 0x00000080 #define A3XX_RB_COPY_CONTROL_FASTCLEAR__MASK 0x00000f00 #define A3XX_RB_COPY_CONTROL_FASTCLEAR__SHIFT 8 static inline uint32_t A3XX_RB_COPY_CONTROL_FASTCLEAR(uint32_t val) { return ((val) << A3XX_RB_COPY_CONTROL_FASTCLEAR__SHIFT) & A3XX_RB_COPY_CONTROL_FASTCLEAR__MASK; } -#define A3XX_RB_COPY_CONTROL_UNK12 0x00001000 +#define A3XX_RB_COPY_CONTROL_DEPTH32_RESOLVE 0x00001000 #define A3XX_RB_COPY_CONTROL_GMEM_BASE__MASK 0xffffc000 #define A3XX_RB_COPY_CONTROL_GMEM_BASE__SHIFT 14 static inline uint32_t A3XX_RB_COPY_CONTROL_GMEM_BASE(uint32_t val) @@ -1217,7 +1470,7 @@ { return ((val) << A3XX_RB_DEPTH_CONTROL_ZFUNC__SHIFT) & A3XX_RB_DEPTH_CONTROL_ZFUNC__MASK; } -#define A3XX_RB_DEPTH_CONTROL_BF_ENABLE 0x00000080 +#define A3XX_RB_DEPTH_CONTROL_Z_CLAMP_ENABLE 0x00000080 #define A3XX_RB_DEPTH_CONTROL_Z_TEST_ENABLE 0x80000000 #define REG_A3XX_RB_DEPTH_CLEAR 0x00002101 @@ -1429,15 +1682,23 @@ #define REG_A3XX_PC_RESTART_INDEX 0x000021ed #define REG_A3XX_HLSQ_CONTROL_0_REG 0x00002200 -#define A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__MASK 0x00000010 +#define A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__MASK 0x00000030 #define A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__SHIFT 4 static inline uint32_t A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE(enum a3xx_threadsize val) { return ((val) << A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__SHIFT) & A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__MASK; } #define A3XX_HLSQ_CONTROL_0_REG_FSSUPERTHREADENABLE 0x00000040 +#define A3XX_HLSQ_CONTROL_0_REG_COMPUTEMODE 0x00000100 #define A3XX_HLSQ_CONTROL_0_REG_SPSHADERRESTART 0x00000200 #define A3XX_HLSQ_CONTROL_0_REG_RESERVED2 0x00000400 +#define A3XX_HLSQ_CONTROL_0_REG_CYCLETIMEOUTLIMITVPC__MASK 0x00fff000 +#define A3XX_HLSQ_CONTROL_0_REG_CYCLETIMEOUTLIMITVPC__SHIFT 12 +static inline uint32_t A3XX_HLSQ_CONTROL_0_REG_CYCLETIMEOUTLIMITVPC(uint32_t val) +{ + return ((val) << A3XX_HLSQ_CONTROL_0_REG_CYCLETIMEOUTLIMITVPC__SHIFT) & A3XX_HLSQ_CONTROL_0_REG_CYCLETIMEOUTLIMITVPC__MASK; +} +#define A3XX_HLSQ_CONTROL_0_REG_FSONLYTEX 0x02000000 #define A3XX_HLSQ_CONTROL_0_REG_CHUNKDISABLE 0x04000000 #define A3XX_HLSQ_CONTROL_0_REG_CONSTMODE__MASK 0x08000000 #define A3XX_HLSQ_CONTROL_0_REG_CONSTMODE__SHIFT 27 @@ -1451,17 +1712,39 @@ #define A3XX_HLSQ_CONTROL_0_REG_SINGLECONTEXT 0x80000000 #define REG_A3XX_HLSQ_CONTROL_1_REG 0x00002201 -#define A3XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__MASK 0x00000040 +#define A3XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__MASK 0x000000c0 #define A3XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__SHIFT 6 static inline uint32_t A3XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE(enum a3xx_threadsize val) { return ((val) << A3XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__SHIFT) & A3XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__MASK; } #define A3XX_HLSQ_CONTROL_1_REG_VSSUPERTHREADENABLE 0x00000100 -#define A3XX_HLSQ_CONTROL_1_REG_RESERVED1 0x00000200 -#define A3XX_HLSQ_CONTROL_1_REG_ZWCOORD 0x02000000 +#define A3XX_HLSQ_CONTROL_1_REG_FRAGCOORDXYREGID__MASK 0x00ff0000 +#define A3XX_HLSQ_CONTROL_1_REG_FRAGCOORDXYREGID__SHIFT 16 +static inline uint32_t A3XX_HLSQ_CONTROL_1_REG_FRAGCOORDXYREGID(uint32_t val) +{ + return ((val) << A3XX_HLSQ_CONTROL_1_REG_FRAGCOORDXYREGID__SHIFT) & A3XX_HLSQ_CONTROL_1_REG_FRAGCOORDXYREGID__MASK; +} +#define A3XX_HLSQ_CONTROL_1_REG_FRAGCOORDZWREGID__MASK 0xff000000 +#define A3XX_HLSQ_CONTROL_1_REG_FRAGCOORDZWREGID__SHIFT 24 +static inline uint32_t A3XX_HLSQ_CONTROL_1_REG_FRAGCOORDZWREGID(uint32_t val) +{ + return ((val) << A3XX_HLSQ_CONTROL_1_REG_FRAGCOORDZWREGID__SHIFT) & A3XX_HLSQ_CONTROL_1_REG_FRAGCOORDZWREGID__MASK; +} #define REG_A3XX_HLSQ_CONTROL_2_REG 0x00002202 +#define A3XX_HLSQ_CONTROL_2_REG_FACENESSREGID__MASK 0x000003fc +#define A3XX_HLSQ_CONTROL_2_REG_FACENESSREGID__SHIFT 2 +static inline uint32_t A3XX_HLSQ_CONTROL_2_REG_FACENESSREGID(uint32_t val) +{ + return ((val) << A3XX_HLSQ_CONTROL_2_REG_FACENESSREGID__SHIFT) & A3XX_HLSQ_CONTROL_2_REG_FACENESSREGID__MASK; +} +#define A3XX_HLSQ_CONTROL_2_REG_COVVALUEREGID__MASK 0x03fc0000 +#define A3XX_HLSQ_CONTROL_2_REG_COVVALUEREGID__SHIFT 18 +static inline uint32_t A3XX_HLSQ_CONTROL_2_REG_COVVALUEREGID(uint32_t val) +{ + return ((val) << A3XX_HLSQ_CONTROL_2_REG_COVVALUEREGID__SHIFT) & A3XX_HLSQ_CONTROL_2_REG_COVVALUEREGID__MASK; +} #define A3XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__MASK 0xfc000000 #define A3XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__SHIFT 26 static inline uint32_t A3XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD(uint32_t val) @@ -1478,13 +1761,13 @@ } #define REG_A3XX_HLSQ_VS_CONTROL_REG 0x00002204 -#define A3XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__MASK 0x00000fff +#define A3XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__MASK 0x000003ff #define A3XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__SHIFT 0 static inline uint32_t A3XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH(uint32_t val) { return ((val) << A3XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__SHIFT) & A3XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__MASK; } -#define A3XX_HLSQ_VS_CONTROL_REG_CONSTSTARTOFFSET__MASK 0x00fff000 +#define A3XX_HLSQ_VS_CONTROL_REG_CONSTSTARTOFFSET__MASK 0x001ff000 #define A3XX_HLSQ_VS_CONTROL_REG_CONSTSTARTOFFSET__SHIFT 12 static inline uint32_t A3XX_HLSQ_VS_CONTROL_REG_CONSTSTARTOFFSET(uint32_t val) { @@ -1498,13 +1781,13 @@ } #define REG_A3XX_HLSQ_FS_CONTROL_REG 0x00002205 -#define A3XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__MASK 0x00000fff +#define A3XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__MASK 0x000003ff #define A3XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__SHIFT 0 static inline uint32_t A3XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH(uint32_t val) { return ((val) << A3XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__SHIFT) & A3XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__MASK; } -#define A3XX_HLSQ_FS_CONTROL_REG_CONSTSTARTOFFSET__MASK 0x00fff000 +#define A3XX_HLSQ_FS_CONTROL_REG_CONSTSTARTOFFSET__MASK 0x001ff000 #define A3XX_HLSQ_FS_CONTROL_REG_CONSTSTARTOFFSET__SHIFT 12 static inline uint32_t A3XX_HLSQ_FS_CONTROL_REG_CONSTSTARTOFFSET(uint32_t val) { @@ -1518,13 +1801,13 @@ } #define REG_A3XX_HLSQ_CONST_VSPRESV_RANGE_REG 0x00002206 -#define A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_STARTENTRY__MASK 0x0000ffff +#define A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_STARTENTRY__MASK 0x000001ff #define A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_STARTENTRY__SHIFT 0 static inline uint32_t A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_STARTENTRY(uint32_t val) { return ((val) << A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_STARTENTRY__SHIFT) & A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_STARTENTRY__MASK; } -#define A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_ENDENTRY__MASK 0xffff0000 +#define A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_ENDENTRY__MASK 0x01ff0000 #define A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_ENDENTRY__SHIFT 16 static inline uint32_t A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_ENDENTRY(uint32_t val) { @@ -1532,13 +1815,13 @@ } #define REG_A3XX_HLSQ_CONST_FSPRESV_RANGE_REG 0x00002207 -#define A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_STARTENTRY__MASK 0x0000ffff +#define A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_STARTENTRY__MASK 0x000001ff #define A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_STARTENTRY__SHIFT 0 static inline uint32_t A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_STARTENTRY(uint32_t val) { return ((val) << A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_STARTENTRY__SHIFT) & A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_STARTENTRY__MASK; } -#define A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY__MASK 0xffff0000 +#define A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY__MASK 0x01ff0000 #define A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY__SHIFT 16 static inline uint32_t A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY(uint32_t val) { @@ -1620,12 +1903,24 @@ } #define REG_A3XX_VFD_CONTROL_1 0x00002241 -#define A3XX_VFD_CONTROL_1_MAXSTORAGE__MASK 0x0000ffff +#define A3XX_VFD_CONTROL_1_MAXSTORAGE__MASK 0x0000000f #define A3XX_VFD_CONTROL_1_MAXSTORAGE__SHIFT 0 static inline uint32_t A3XX_VFD_CONTROL_1_MAXSTORAGE(uint32_t val) { return ((val) << A3XX_VFD_CONTROL_1_MAXSTORAGE__SHIFT) & A3XX_VFD_CONTROL_1_MAXSTORAGE__MASK; } +#define A3XX_VFD_CONTROL_1_MAXTHRESHOLD__MASK 0x000000f0 +#define A3XX_VFD_CONTROL_1_MAXTHRESHOLD__SHIFT 4 +static inline uint32_t A3XX_VFD_CONTROL_1_MAXTHRESHOLD(uint32_t val) +{ + return ((val) << A3XX_VFD_CONTROL_1_MAXTHRESHOLD__SHIFT) & A3XX_VFD_CONTROL_1_MAXTHRESHOLD__MASK; +} +#define A3XX_VFD_CONTROL_1_MINTHRESHOLD__MASK 0x00000f00 +#define A3XX_VFD_CONTROL_1_MINTHRESHOLD__SHIFT 8 +static inline uint32_t A3XX_VFD_CONTROL_1_MINTHRESHOLD(uint32_t val) +{ + return ((val) << A3XX_VFD_CONTROL_1_MINTHRESHOLD__SHIFT) & A3XX_VFD_CONTROL_1_MINTHRESHOLD__MASK; +} #define A3XX_VFD_CONTROL_1_REGID4VTX__MASK 0x00ff0000 #define A3XX_VFD_CONTROL_1_REGID4VTX__SHIFT 16 static inline uint32_t A3XX_VFD_CONTROL_1_REGID4VTX(uint32_t val) @@ -2008,24 +2303,19 @@ return ((val) << A3XX_SP_VS_CTRL_REG0_INSTRBUFFERMODE__SHIFT) & A3XX_SP_VS_CTRL_REG0_INSTRBUFFERMODE__MASK; } #define A3XX_SP_VS_CTRL_REG0_CACHEINVALID 0x00000004 +#define A3XX_SP_VS_CTRL_REG0_ALUSCHMODE 0x00000008 #define A3XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x000003f0 #define A3XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 4 static inline uint32_t A3XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) { return ((val) << A3XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A3XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK; } -#define A3XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x0003fc00 +#define A3XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x0000fc00 #define A3XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 10 static inline uint32_t A3XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) { return ((val) << A3XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A3XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK; } -#define A3XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP__MASK 0x000c0000 -#define A3XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP__SHIFT 18 -static inline uint32_t A3XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP(uint32_t val) -{ - return ((val) << A3XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP__SHIFT) & A3XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP__MASK; -} #define A3XX_SP_VS_CTRL_REG0_THREADSIZE__MASK 0x00100000 #define A3XX_SP_VS_CTRL_REG0_THREADSIZE__SHIFT 20 static inline uint32_t A3XX_SP_VS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val) @@ -2033,8 +2323,6 @@ return ((val) << A3XX_SP_VS_CTRL_REG0_THREADSIZE__SHIFT) & A3XX_SP_VS_CTRL_REG0_THREADSIZE__MASK; } #define A3XX_SP_VS_CTRL_REG0_SUPERTHREADMODE 0x00200000 -#define A3XX_SP_VS_CTRL_REG0_PIXLODENABLE 0x00400000 -#define A3XX_SP_VS_CTRL_REG0_COMPUTEMODE 0x00800000 #define A3XX_SP_VS_CTRL_REG0_LENGTH__MASK 0xff000000 #define A3XX_SP_VS_CTRL_REG0_LENGTH__SHIFT 24 static inline uint32_t A3XX_SP_VS_CTRL_REG0_LENGTH(uint32_t val) @@ -2075,7 +2363,8 @@ { return ((val) << A3XX_SP_VS_PARAM_REG_PSIZEREGID__SHIFT) & A3XX_SP_VS_PARAM_REG_PSIZEREGID__MASK; } -#define A3XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__MASK 0xfff00000 +#define A3XX_SP_VS_PARAM_REG_POS2DMODE 0x00010000 +#define A3XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__MASK 0x01f00000 #define A3XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__SHIFT 20 static inline uint32_t A3XX_SP_VS_PARAM_REG_TOTALVSOUTVAR(uint32_t val) { @@ -2085,24 +2374,26 @@ static inline uint32_t REG_A3XX_SP_VS_OUT(uint32_t i0) { return 0x000022c7 + 0x1*i0; } static inline uint32_t REG_A3XX_SP_VS_OUT_REG(uint32_t i0) { return 0x000022c7 + 0x1*i0; } -#define A3XX_SP_VS_OUT_REG_A_REGID__MASK 0x000001ff +#define A3XX_SP_VS_OUT_REG_A_REGID__MASK 0x000000ff #define A3XX_SP_VS_OUT_REG_A_REGID__SHIFT 0 static inline uint32_t A3XX_SP_VS_OUT_REG_A_REGID(uint32_t val) { return ((val) << A3XX_SP_VS_OUT_REG_A_REGID__SHIFT) & A3XX_SP_VS_OUT_REG_A_REGID__MASK; } +#define A3XX_SP_VS_OUT_REG_A_HALF 0x00000100 #define A3XX_SP_VS_OUT_REG_A_COMPMASK__MASK 0x00001e00 #define A3XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT 9 static inline uint32_t A3XX_SP_VS_OUT_REG_A_COMPMASK(uint32_t val) { return ((val) << A3XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT) & A3XX_SP_VS_OUT_REG_A_COMPMASK__MASK; } -#define A3XX_SP_VS_OUT_REG_B_REGID__MASK 0x01ff0000 +#define A3XX_SP_VS_OUT_REG_B_REGID__MASK 0x00ff0000 #define A3XX_SP_VS_OUT_REG_B_REGID__SHIFT 16 static inline uint32_t A3XX_SP_VS_OUT_REG_B_REGID(uint32_t val) { return ((val) << A3XX_SP_VS_OUT_REG_B_REGID__SHIFT) & A3XX_SP_VS_OUT_REG_B_REGID__MASK; } +#define A3XX_SP_VS_OUT_REG_B_HALF 0x01000000 #define A3XX_SP_VS_OUT_REG_B_COMPMASK__MASK 0x1e000000 #define A3XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT 25 static inline uint32_t A3XX_SP_VS_OUT_REG_B_COMPMASK(uint32_t val) @@ -2113,25 +2404,25 @@ static inline uint32_t REG_A3XX_SP_VS_VPC_DST(uint32_t i0) { return 0x000022d0 + 0x1*i0; } static inline uint32_t REG_A3XX_SP_VS_VPC_DST_REG(uint32_t i0) { return 0x000022d0 + 0x1*i0; } -#define A3XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK 0x000000ff +#define A3XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK 0x0000007f #define A3XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT 0 static inline uint32_t A3XX_SP_VS_VPC_DST_REG_OUTLOC0(uint32_t val) { return ((val) << A3XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT) & A3XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK; } -#define A3XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK 0x0000ff00 +#define A3XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK 0x00007f00 #define A3XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT 8 static inline uint32_t A3XX_SP_VS_VPC_DST_REG_OUTLOC1(uint32_t val) { return ((val) << A3XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT) & A3XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK; } -#define A3XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK 0x00ff0000 +#define A3XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK 0x007f0000 #define A3XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT 16 static inline uint32_t A3XX_SP_VS_VPC_DST_REG_OUTLOC2(uint32_t val) { return ((val) << A3XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT) & A3XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK; } -#define A3XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK 0xff000000 +#define A3XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK 0x7f000000 #define A3XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT 24 static inline uint32_t A3XX_SP_VS_VPC_DST_REG_OUTLOC3(uint32_t val) { @@ -2139,6 +2430,12 @@ } #define REG_A3XX_SP_VS_OBJ_OFFSET_REG 0x000022d4 +#define A3XX_SP_VS_OBJ_OFFSET_REG_FIRSTEXECINSTROFFSET__MASK 0x0000ffff +#define A3XX_SP_VS_OBJ_OFFSET_REG_FIRSTEXECINSTROFFSET__SHIFT 0 +static inline uint32_t A3XX_SP_VS_OBJ_OFFSET_REG_FIRSTEXECINSTROFFSET(uint32_t val) +{ + return ((val) << A3XX_SP_VS_OBJ_OFFSET_REG_FIRSTEXECINSTROFFSET__SHIFT) & A3XX_SP_VS_OBJ_OFFSET_REG_FIRSTEXECINSTROFFSET__MASK; +} #define A3XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK 0x01ff0000 #define A3XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT 16 static inline uint32_t A3XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val) @@ -2155,8 +2452,38 @@ #define REG_A3XX_SP_VS_OBJ_START_REG 0x000022d5 #define REG_A3XX_SP_VS_PVT_MEM_PARAM_REG 0x000022d6 +#define A3XX_SP_VS_PVT_MEM_PARAM_REG_MEMSIZEPERITEM__MASK 0x000000ff +#define A3XX_SP_VS_PVT_MEM_PARAM_REG_MEMSIZEPERITEM__SHIFT 0 +static inline uint32_t A3XX_SP_VS_PVT_MEM_PARAM_REG_MEMSIZEPERITEM(uint32_t val) +{ + return ((val) << A3XX_SP_VS_PVT_MEM_PARAM_REG_MEMSIZEPERITEM__SHIFT) & A3XX_SP_VS_PVT_MEM_PARAM_REG_MEMSIZEPERITEM__MASK; +} +#define A3XX_SP_VS_PVT_MEM_PARAM_REG_HWSTACKOFFSET__MASK 0x00ffff00 +#define A3XX_SP_VS_PVT_MEM_PARAM_REG_HWSTACKOFFSET__SHIFT 8 +static inline uint32_t A3XX_SP_VS_PVT_MEM_PARAM_REG_HWSTACKOFFSET(uint32_t val) +{ + return ((val) << A3XX_SP_VS_PVT_MEM_PARAM_REG_HWSTACKOFFSET__SHIFT) & A3XX_SP_VS_PVT_MEM_PARAM_REG_HWSTACKOFFSET__MASK; +} +#define A3XX_SP_VS_PVT_MEM_PARAM_REG_HWSTACKSIZEPERTHREAD__MASK 0xff000000 +#define A3XX_SP_VS_PVT_MEM_PARAM_REG_HWSTACKSIZEPERTHREAD__SHIFT 24 +static inline uint32_t A3XX_SP_VS_PVT_MEM_PARAM_REG_HWSTACKSIZEPERTHREAD(uint32_t val) +{ + return ((val) << A3XX_SP_VS_PVT_MEM_PARAM_REG_HWSTACKSIZEPERTHREAD__SHIFT) & A3XX_SP_VS_PVT_MEM_PARAM_REG_HWSTACKSIZEPERTHREAD__MASK; +} #define REG_A3XX_SP_VS_PVT_MEM_ADDR_REG 0x000022d7 +#define A3XX_SP_VS_PVT_MEM_ADDR_REG_BURSTLEN__MASK 0x0000001f +#define A3XX_SP_VS_PVT_MEM_ADDR_REG_BURSTLEN__SHIFT 0 +static inline uint32_t A3XX_SP_VS_PVT_MEM_ADDR_REG_BURSTLEN(uint32_t val) +{ + return ((val) << A3XX_SP_VS_PVT_MEM_ADDR_REG_BURSTLEN__SHIFT) & A3XX_SP_VS_PVT_MEM_ADDR_REG_BURSTLEN__MASK; +} +#define A3XX_SP_VS_PVT_MEM_ADDR_REG_SHADERSTARTADDRESS__MASK 0xffffffe0 +#define A3XX_SP_VS_PVT_MEM_ADDR_REG_SHADERSTARTADDRESS__SHIFT 5 +static inline uint32_t A3XX_SP_VS_PVT_MEM_ADDR_REG_SHADERSTARTADDRESS(uint32_t val) +{ + return ((val >> 5) << A3XX_SP_VS_PVT_MEM_ADDR_REG_SHADERSTARTADDRESS__SHIFT) & A3XX_SP_VS_PVT_MEM_ADDR_REG_SHADERSTARTADDRESS__MASK; +} #define REG_A3XX_SP_VS_PVT_MEM_SIZE_REG 0x000022d8 @@ -2182,24 +2509,22 @@ return ((val) << A3XX_SP_FS_CTRL_REG0_INSTRBUFFERMODE__SHIFT) & A3XX_SP_FS_CTRL_REG0_INSTRBUFFERMODE__MASK; } #define A3XX_SP_FS_CTRL_REG0_CACHEINVALID 0x00000004 +#define A3XX_SP_FS_CTRL_REG0_ALUSCHMODE 0x00000008 #define A3XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x000003f0 #define A3XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 4 static inline uint32_t A3XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) { return ((val) << A3XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A3XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK; } -#define A3XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x0003fc00 +#define A3XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x0000fc00 #define A3XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 10 static inline uint32_t A3XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) { return ((val) << A3XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A3XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK; } -#define A3XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP__MASK 0x000c0000 -#define A3XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP__SHIFT 18 -static inline uint32_t A3XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP(uint32_t val) -{ - return ((val) << A3XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP__SHIFT) & A3XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP__MASK; -} +#define A3XX_SP_FS_CTRL_REG0_FSBYPASSENABLE 0x00020000 +#define A3XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP 0x00040000 +#define A3XX_SP_FS_CTRL_REG0_OUTORDERED 0x00080000 #define A3XX_SP_FS_CTRL_REG0_THREADSIZE__MASK 0x00100000 #define A3XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT 20 static inline uint32_t A3XX_SP_FS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val) @@ -2235,7 +2560,7 @@ { return ((val) << A3XX_SP_FS_CTRL_REG1_INITIALOUTSTANDING__SHIFT) & A3XX_SP_FS_CTRL_REG1_INITIALOUTSTANDING__MASK; } -#define A3XX_SP_FS_CTRL_REG1_HALFPRECVAROFFSET__MASK 0x3f000000 +#define A3XX_SP_FS_CTRL_REG1_HALFPRECVAROFFSET__MASK 0x7f000000 #define A3XX_SP_FS_CTRL_REG1_HALFPRECVAROFFSET__SHIFT 24 static inline uint32_t A3XX_SP_FS_CTRL_REG1_HALFPRECVAROFFSET(uint32_t val) { @@ -2243,6 +2568,12 @@ } #define REG_A3XX_SP_FS_OBJ_OFFSET_REG 0x000022e2 +#define A3XX_SP_FS_OBJ_OFFSET_REG_FIRSTEXECINSTROFFSET__MASK 0x0000ffff +#define A3XX_SP_FS_OBJ_OFFSET_REG_FIRSTEXECINSTROFFSET__SHIFT 0 +static inline uint32_t A3XX_SP_FS_OBJ_OFFSET_REG_FIRSTEXECINSTROFFSET(uint32_t val) +{ + return ((val) << A3XX_SP_FS_OBJ_OFFSET_REG_FIRSTEXECINSTROFFSET__SHIFT) & A3XX_SP_FS_OBJ_OFFSET_REG_FIRSTEXECINSTROFFSET__MASK; +} #define A3XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK 0x01ff0000 #define A3XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT 16 static inline uint32_t A3XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val) @@ -2259,8 +2590,38 @@ #define REG_A3XX_SP_FS_OBJ_START_REG 0x000022e3 #define REG_A3XX_SP_FS_PVT_MEM_PARAM_REG 0x000022e4 +#define A3XX_SP_FS_PVT_MEM_PARAM_REG_MEMSIZEPERITEM__MASK 0x000000ff +#define A3XX_SP_FS_PVT_MEM_PARAM_REG_MEMSIZEPERITEM__SHIFT 0 +static inline uint32_t A3XX_SP_FS_PVT_MEM_PARAM_REG_MEMSIZEPERITEM(uint32_t val) +{ + return ((val) << A3XX_SP_FS_PVT_MEM_PARAM_REG_MEMSIZEPERITEM__SHIFT) & A3XX_SP_FS_PVT_MEM_PARAM_REG_MEMSIZEPERITEM__MASK; +} +#define A3XX_SP_FS_PVT_MEM_PARAM_REG_HWSTACKOFFSET__MASK 0x00ffff00 +#define A3XX_SP_FS_PVT_MEM_PARAM_REG_HWSTACKOFFSET__SHIFT 8 +static inline uint32_t A3XX_SP_FS_PVT_MEM_PARAM_REG_HWSTACKOFFSET(uint32_t val) +{ + return ((val) << A3XX_SP_FS_PVT_MEM_PARAM_REG_HWSTACKOFFSET__SHIFT) & A3XX_SP_FS_PVT_MEM_PARAM_REG_HWSTACKOFFSET__MASK; +} +#define A3XX_SP_FS_PVT_MEM_PARAM_REG_HWSTACKSIZEPERTHREAD__MASK 0xff000000 +#define A3XX_SP_FS_PVT_MEM_PARAM_REG_HWSTACKSIZEPERTHREAD__SHIFT 24 +static inline uint32_t A3XX_SP_FS_PVT_MEM_PARAM_REG_HWSTACKSIZEPERTHREAD(uint32_t val) +{ + return ((val) << A3XX_SP_FS_PVT_MEM_PARAM_REG_HWSTACKSIZEPERTHREAD__SHIFT) & A3XX_SP_FS_PVT_MEM_PARAM_REG_HWSTACKSIZEPERTHREAD__MASK; +} #define REG_A3XX_SP_FS_PVT_MEM_ADDR_REG 0x000022e5 +#define A3XX_SP_FS_PVT_MEM_ADDR_REG_BURSTLEN__MASK 0x0000001f +#define A3XX_SP_FS_PVT_MEM_ADDR_REG_BURSTLEN__SHIFT 0 +static inline uint32_t A3XX_SP_FS_PVT_MEM_ADDR_REG_BURSTLEN(uint32_t val) +{ + return ((val) << A3XX_SP_FS_PVT_MEM_ADDR_REG_BURSTLEN__SHIFT) & A3XX_SP_FS_PVT_MEM_ADDR_REG_BURSTLEN__MASK; +} +#define A3XX_SP_FS_PVT_MEM_ADDR_REG_SHADERSTARTADDRESS__MASK 0xffffffe0 +#define A3XX_SP_FS_PVT_MEM_ADDR_REG_SHADERSTARTADDRESS__SHIFT 5 +static inline uint32_t A3XX_SP_FS_PVT_MEM_ADDR_REG_SHADERSTARTADDRESS(uint32_t val) +{ + return ((val >> 5) << A3XX_SP_FS_PVT_MEM_ADDR_REG_SHADERSTARTADDRESS__SHIFT) & A3XX_SP_FS_PVT_MEM_ADDR_REG_SHADERSTARTADDRESS__MASK; +} #define REG_A3XX_SP_FS_PVT_MEM_SIZE_REG 0x000022e6 diff -ruw linux-4.4.115/drivers/gpu/drm/msm/adreno/a4xx_gpu.c linux-4.4.115-fbx/drivers/gpu/drm/msm/adreno/a4xx_gpu.c --- linux-4.4.115/drivers/gpu/drm/msm/adreno/a4xx_gpu.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/gpu/drm/msm/adreno/a4xx_gpu.c 2019-01-22 16:16:23.483246225 +0100 @@ -1,4 +1,4 @@ -/* Copyright (c) 2014 The Linux Foundation. All rights reserved. +/* Copyright (c) 2014,2018 The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -31,6 +31,7 @@ extern bool hang_debug; static void a4xx_dump(struct msm_gpu *gpu); +static bool a4xx_idle(struct msm_gpu *gpu); /* * a4xx_enable_hwcg() - Program the clock control registers @@ -102,14 +103,20 @@ gpu_write(gpu, REG_A4XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00000222); gpu_write(gpu, REG_A4XX_RBBM_CLOCK_CTL_HLSQ , 0x00000000); gpu_write(gpu, REG_A4XX_RBBM_CLOCK_HYST_HLSQ, 0x00000000); - gpu_write(gpu, REG_A4XX_RBBM_CLOCK_DELAY_HLSQ, 0x00020000); + gpu_write(gpu, REG_A4XX_RBBM_CLOCK_DELAY_HLSQ, 0x00220000); + /* Early A430's have a timing issue with SP/TP power collapse; + disabling HW clock gating prevents it. */ + if (adreno_is_a430(adreno_gpu) && adreno_gpu->rev.patchid < 2) + gpu_write(gpu, REG_A4XX_RBBM_CLOCK_CTL, 0); + else gpu_write(gpu, REG_A4XX_RBBM_CLOCK_CTL, 0xAAAAAAAA); gpu_write(gpu, REG_A4XX_RBBM_CLOCK_CTL2, 0); } -static void a4xx_me_init(struct msm_gpu *gpu) + +static bool a4xx_me_init(struct msm_gpu *gpu) { - struct msm_ringbuffer *ring = gpu->rb; + struct msm_ringbuffer *ring = gpu->rb[0]; OUT_PKT3(ring, CP_ME_INIT, 17); OUT_RING(ring, 0x000003f7); @@ -130,8 +137,8 @@ OUT_RING(ring, 0x00000000); OUT_RING(ring, 0x00000000); - gpu->funcs->flush(gpu); - gpu->funcs->idle(gpu); + gpu->funcs->flush(gpu, ring); + return a4xx_idle(gpu); } static int a4xx_hw_init(struct msm_gpu *gpu) @@ -141,7 +148,7 @@ uint32_t *ptr, len; int i, ret; - if (adreno_is_a4xx(adreno_gpu)) { + if (adreno_is_a420(adreno_gpu)) { gpu_write(gpu, REG_A4XX_VBIF_ABIT_SORT, 0x0001001F); gpu_write(gpu, REG_A4XX_VBIF_ABIT_SORT_CONF, 0x000000A4); gpu_write(gpu, REG_A4XX_VBIF_GATE_OFF_WRREQ_EN, 0x00000001); @@ -150,6 +157,13 @@ gpu_write(gpu, REG_A4XX_VBIF_IN_WR_LIM_CONF0, 0x18181818); gpu_write(gpu, REG_A4XX_VBIF_IN_WR_LIM_CONF1, 0x00000018); gpu_write(gpu, REG_A4XX_VBIF_ROUND_ROBIN_QOS_ARB, 0x00000003); + } else if (adreno_is_a430(adreno_gpu)) { + gpu_write(gpu, REG_A4XX_VBIF_GATE_OFF_WRREQ_EN, 0x00000001); + gpu_write(gpu, REG_A4XX_VBIF_IN_RD_LIM_CONF0, 0x18181818); + gpu_write(gpu, REG_A4XX_VBIF_IN_RD_LIM_CONF1, 0x00000018); + gpu_write(gpu, REG_A4XX_VBIF_IN_WR_LIM_CONF0, 0x18181818); + gpu_write(gpu, REG_A4XX_VBIF_IN_WR_LIM_CONF1, 0x00000018); + gpu_write(gpu, REG_A4XX_VBIF_ROUND_ROBIN_QOS_ARB, 0x00000003); } else { BUG(); } @@ -161,6 +175,10 @@ gpu_write(gpu, REG_A4XX_RBBM_SP_HYST_CNT, 0x10); gpu_write(gpu, REG_A4XX_RBBM_WAIT_IDLE_CLOCKS_CTL, 0x10); + if (adreno_is_a430(adreno_gpu)) { + gpu_write(gpu, REG_A4XX_RBBM_WAIT_IDLE_CLOCKS_CTL2, 0x30); + } + /* Enable the RBBM error reporting bits */ gpu_write(gpu, REG_A4XX_RBBM_AHB_CTL0, 0x00000001); @@ -183,6 +201,14 @@ /* Turn on performance counters: */ gpu_write(gpu, REG_A4XX_RBBM_PERFCTR_CTL, 0x01); + /* use the first CP counter for timestamp queries.. userspace may set + * this as well but it selects the same counter/countable: + */ + gpu_write(gpu, REG_A4XX_CP_PERFCTR_CP_SEL_0, CP_ALWAYS_COUNT); + + if (adreno_is_a430(adreno_gpu)) + gpu_write(gpu, REG_A4XX_UCHE_CACHE_WAYS_VFD, 0x07); + /* Disable L2 bypass to avoid UCHE out of bounds errors */ gpu_write(gpu, REG_A4XX_UCHE_TRAP_BASE_LO, 0xffff0000); gpu_write(gpu, REG_A4XX_UCHE_TRAP_BASE_HI, 0xffff0000); @@ -190,6 +216,15 @@ gpu_write(gpu, REG_A4XX_CP_DEBUG, (1 << 25) | (adreno_is_a420(adreno_gpu) ? (1 << 29) : 0)); + /* On A430 enable SP regfile sleep for power savings */ + /* TODO downstream does this for !420, so maybe applies for 405 too? */ + if (!adreno_is_a420(adreno_gpu)) { + gpu_write(gpu, REG_A4XX_RBBM_SP_REGFILE_SLEEP_CNTL_0, + 0x00000441); + gpu_write(gpu, REG_A4XX_RBBM_SP_REGFILE_SLEEP_CNTL_1, + 0x00000441); + } + a4xx_enable_hwcg(gpu); /* @@ -204,10 +239,6 @@ gpu_write(gpu, REG_A4XX_RBBM_CLOCK_DELAY_HLSQ, val); } - ret = adreno_hw_init(gpu); - if (ret) - return ret; - /* setup access protection: */ gpu_write(gpu, REG_A4XX_CP_PROTECT_CTRL, 0x00000007); @@ -262,8 +293,7 @@ /* clear ME_HALT to start micro engine */ gpu_write(gpu, REG_A4XX_CP_ME_CNTL, 0); - a4xx_me_init(gpu); - return 0; + return a4xx_me_init(gpu) ? 0 : -EINVAL; } static void a4xx_recover(struct msm_gpu *gpu) @@ -297,17 +327,21 @@ kfree(a4xx_gpu); } -static void a4xx_idle(struct msm_gpu *gpu) +static bool a4xx_idle(struct msm_gpu *gpu) { /* wait for ringbuffer to drain: */ - adreno_idle(gpu); + if (!adreno_idle(gpu, gpu->rb[0])) + return false; /* then wait for GPU to finish: */ if (spin_until(!(gpu_read(gpu, REG_A4XX_RBBM_STATUS) & - A4XX_RBBM_STATUS_GPU_BUSY))) + A4XX_RBBM_STATUS_GPU_BUSY))) { DRM_ERROR("%s: timeout waiting for GPU to idle!\n", gpu->name); - /* TODO maybe we need to reset GPU here to recover from hang? */ + return false; + } + + return true; } static irqreturn_t a4xx_irq(struct msm_gpu *gpu) @@ -409,12 +443,8 @@ #ifdef CONFIG_DEBUG_FS static void a4xx_show(struct msm_gpu *gpu, struct seq_file *m) { - gpu->funcs->pm_resume(gpu); - seq_printf(m, "status: %08x\n", gpu_read(gpu, REG_A4XX_RBBM_STATUS)); - gpu->funcs->pm_suspend(gpu); - adreno_show(gpu, m); } @@ -422,87 +452,13 @@ /* Register offset defines for A4XX, in order of enum adreno_regs */ static const unsigned int a4xx_register_offsets[REG_ADRENO_REGISTER_MAX] = { - REG_ADRENO_DEFINE(REG_ADRENO_CP_DEBUG, REG_A4XX_CP_DEBUG), - REG_ADRENO_DEFINE(REG_ADRENO_CP_ME_RAM_WADDR, REG_A4XX_CP_ME_RAM_WADDR), - REG_ADRENO_DEFINE(REG_ADRENO_CP_ME_RAM_DATA, REG_A4XX_CP_ME_RAM_DATA), - REG_ADRENO_DEFINE(REG_ADRENO_CP_PFP_UCODE_DATA, - REG_A4XX_CP_PFP_UCODE_DATA), - REG_ADRENO_DEFINE(REG_ADRENO_CP_PFP_UCODE_ADDR, - REG_A4XX_CP_PFP_UCODE_ADDR), - REG_ADRENO_DEFINE(REG_ADRENO_CP_WFI_PEND_CTR, REG_A4XX_CP_WFI_PEND_CTR), REG_ADRENO_DEFINE(REG_ADRENO_CP_RB_BASE, REG_A4XX_CP_RB_BASE), + REG_ADRENO_SKIP(REG_ADRENO_CP_RB_BASE_HI), REG_ADRENO_DEFINE(REG_ADRENO_CP_RB_RPTR_ADDR, REG_A4XX_CP_RB_RPTR_ADDR), + REG_ADRENO_SKIP(REG_ADRENO_CP_RB_RPTR_ADDR_HI), REG_ADRENO_DEFINE(REG_ADRENO_CP_RB_RPTR, REG_A4XX_CP_RB_RPTR), REG_ADRENO_DEFINE(REG_ADRENO_CP_RB_WPTR, REG_A4XX_CP_RB_WPTR), - REG_ADRENO_DEFINE(REG_ADRENO_CP_PROTECT_CTRL, REG_A4XX_CP_PROTECT_CTRL), - REG_ADRENO_DEFINE(REG_ADRENO_CP_ME_CNTL, REG_A4XX_CP_ME_CNTL), REG_ADRENO_DEFINE(REG_ADRENO_CP_RB_CNTL, REG_A4XX_CP_RB_CNTL), - REG_ADRENO_DEFINE(REG_ADRENO_CP_IB1_BASE, REG_A4XX_CP_IB1_BASE), - REG_ADRENO_DEFINE(REG_ADRENO_CP_IB1_BUFSZ, REG_A4XX_CP_IB1_BUFSZ), - REG_ADRENO_DEFINE(REG_ADRENO_CP_IB2_BASE, REG_A4XX_CP_IB2_BASE), - REG_ADRENO_DEFINE(REG_ADRENO_CP_IB2_BUFSZ, REG_A4XX_CP_IB2_BUFSZ), - REG_ADRENO_DEFINE(REG_ADRENO_CP_TIMESTAMP, REG_AXXX_CP_SCRATCH_REG0), - REG_ADRENO_DEFINE(REG_ADRENO_CP_ME_RAM_RADDR, REG_A4XX_CP_ME_RAM_RADDR), - REG_ADRENO_DEFINE(REG_ADRENO_CP_ROQ_ADDR, REG_A4XX_CP_ROQ_ADDR), - REG_ADRENO_DEFINE(REG_ADRENO_CP_ROQ_DATA, REG_A4XX_CP_ROQ_DATA), - REG_ADRENO_DEFINE(REG_ADRENO_CP_MERCIU_ADDR, REG_A4XX_CP_MERCIU_ADDR), - REG_ADRENO_DEFINE(REG_ADRENO_CP_MERCIU_DATA, REG_A4XX_CP_MERCIU_DATA), - REG_ADRENO_DEFINE(REG_ADRENO_CP_MERCIU_DATA2, REG_A4XX_CP_MERCIU_DATA2), - REG_ADRENO_DEFINE(REG_ADRENO_CP_MEQ_ADDR, REG_A4XX_CP_MEQ_ADDR), - REG_ADRENO_DEFINE(REG_ADRENO_CP_MEQ_DATA, REG_A4XX_CP_MEQ_DATA), - REG_ADRENO_DEFINE(REG_ADRENO_CP_HW_FAULT, REG_A4XX_CP_HW_FAULT), - REG_ADRENO_DEFINE(REG_ADRENO_CP_PROTECT_STATUS, - REG_A4XX_CP_PROTECT_STATUS), - REG_ADRENO_DEFINE(REG_ADRENO_SCRATCH_ADDR, REG_A4XX_CP_SCRATCH_ADDR), - REG_ADRENO_DEFINE(REG_ADRENO_SCRATCH_UMSK, REG_A4XX_CP_SCRATCH_UMASK), - REG_ADRENO_DEFINE(REG_ADRENO_RBBM_STATUS, REG_A4XX_RBBM_STATUS), - REG_ADRENO_DEFINE(REG_ADRENO_RBBM_PERFCTR_CTL, - REG_A4XX_RBBM_PERFCTR_CTL), - REG_ADRENO_DEFINE(REG_ADRENO_RBBM_PERFCTR_LOAD_CMD0, - REG_A4XX_RBBM_PERFCTR_LOAD_CMD0), - REG_ADRENO_DEFINE(REG_ADRENO_RBBM_PERFCTR_LOAD_CMD1, - REG_A4XX_RBBM_PERFCTR_LOAD_CMD1), - REG_ADRENO_DEFINE(REG_ADRENO_RBBM_PERFCTR_LOAD_CMD2, - REG_A4XX_RBBM_PERFCTR_LOAD_CMD2), - REG_ADRENO_DEFINE(REG_ADRENO_RBBM_PERFCTR_PWR_1_LO, - REG_A4XX_RBBM_PERFCTR_PWR_1_LO), - REG_ADRENO_DEFINE(REG_ADRENO_RBBM_INT_0_MASK, REG_A4XX_RBBM_INT_0_MASK), - REG_ADRENO_DEFINE(REG_ADRENO_RBBM_INT_0_STATUS, - REG_A4XX_RBBM_INT_0_STATUS), - REG_ADRENO_DEFINE(REG_ADRENO_RBBM_AHB_ERROR_STATUS, - REG_A4XX_RBBM_AHB_ERROR_STATUS), - REG_ADRENO_DEFINE(REG_ADRENO_RBBM_AHB_CMD, REG_A4XX_RBBM_AHB_CMD), - REG_ADRENO_DEFINE(REG_ADRENO_RBBM_CLOCK_CTL, REG_A4XX_RBBM_CLOCK_CTL), - REG_ADRENO_DEFINE(REG_ADRENO_RBBM_AHB_ME_SPLIT_STATUS, - REG_A4XX_RBBM_AHB_ME_SPLIT_STATUS), - REG_ADRENO_DEFINE(REG_ADRENO_RBBM_AHB_PFP_SPLIT_STATUS, - REG_A4XX_RBBM_AHB_PFP_SPLIT_STATUS), - REG_ADRENO_DEFINE(REG_ADRENO_VPC_DEBUG_RAM_SEL, - REG_A4XX_VPC_DEBUG_RAM_SEL), - REG_ADRENO_DEFINE(REG_ADRENO_VPC_DEBUG_RAM_READ, - REG_A4XX_VPC_DEBUG_RAM_READ), - REG_ADRENO_DEFINE(REG_ADRENO_RBBM_INT_CLEAR_CMD, - REG_A4XX_RBBM_INT_CLEAR_CMD), - REG_ADRENO_DEFINE(REG_ADRENO_VSC_SIZE_ADDRESS, - REG_A4XX_VSC_SIZE_ADDRESS), - REG_ADRENO_DEFINE(REG_ADRENO_VFD_CONTROL_0, REG_A4XX_VFD_CONTROL_0), - REG_ADRENO_DEFINE(REG_ADRENO_SP_VS_PVT_MEM_ADDR_REG, - REG_A4XX_SP_VS_PVT_MEM_ADDR), - REG_ADRENO_DEFINE(REG_ADRENO_SP_FS_PVT_MEM_ADDR_REG, - REG_A4XX_SP_FS_PVT_MEM_ADDR), - REG_ADRENO_DEFINE(REG_ADRENO_SP_VS_OBJ_START_REG, - REG_A4XX_SP_VS_OBJ_START), - REG_ADRENO_DEFINE(REG_ADRENO_SP_FS_OBJ_START_REG, - REG_A4XX_SP_FS_OBJ_START), - REG_ADRENO_DEFINE(REG_ADRENO_RBBM_RBBM_CTL, REG_A4XX_RBBM_RBBM_CTL), - REG_ADRENO_DEFINE(REG_ADRENO_RBBM_SW_RESET_CMD, - REG_A4XX_RBBM_SW_RESET_CMD), - REG_ADRENO_DEFINE(REG_ADRENO_UCHE_INVALIDATE0, - REG_A4XX_UCHE_INVALIDATE0), - REG_ADRENO_DEFINE(REG_ADRENO_RBBM_PERFCTR_LOAD_VALUE_LO, - REG_A4XX_RBBM_PERFCTR_LOAD_VALUE_LO), - REG_ADRENO_DEFINE(REG_ADRENO_RBBM_PERFCTR_LOAD_VALUE_HI, - REG_A4XX_RBBM_PERFCTR_LOAD_VALUE_HI), }; static void a4xx_dump(struct msm_gpu *gpu) @@ -512,23 +468,67 @@ adreno_dump(gpu); } +static int a4xx_pm_resume(struct msm_gpu *gpu) { + struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); + int ret; + + ret = msm_gpu_pm_resume(gpu); + if (ret) + return ret; + + if (adreno_is_a430(adreno_gpu)) { + unsigned int reg; + /* Set the default register values; set SW_COLLAPSE to 0 */ + gpu_write(gpu, REG_A4XX_RBBM_POWER_CNTL_IP, 0x778000); + do { + udelay(5); + reg = gpu_read(gpu, REG_A4XX_RBBM_POWER_STATUS); + } while (!(reg & A4XX_RBBM_POWER_CNTL_IP_SP_TP_PWR_ON)); + } + return 0; +} + +static int a4xx_pm_suspend(struct msm_gpu *gpu) { + struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); + int ret; + + ret = msm_gpu_pm_suspend(gpu); + if (ret) + return ret; + + if (adreno_is_a430(adreno_gpu)) { + /* Set the default register values; set SW_COLLAPSE to 1 */ + gpu_write(gpu, REG_A4XX_RBBM_POWER_CNTL_IP, 0x778001); + } + return 0; +} + +static int a4xx_get_timestamp(struct msm_gpu *gpu, uint64_t *value) +{ + *value = gpu_read64(gpu, REG_A4XX_RBBM_PERFCTR_CP_0_LO, + REG_A4XX_RBBM_PERFCTR_CP_0_HI); + + return 0; +} + static const struct adreno_gpu_funcs funcs = { .base = { .get_param = adreno_get_param, .hw_init = a4xx_hw_init, - .pm_suspend = msm_gpu_pm_suspend, - .pm_resume = msm_gpu_pm_resume, + .pm_suspend = a4xx_pm_suspend, + .pm_resume = a4xx_pm_resume, .recover = a4xx_recover, - .last_fence = adreno_last_fence, + .submitted_fence = adreno_submitted_fence, .submit = adreno_submit, .flush = adreno_flush, - .idle = a4xx_idle, + .active_ring = adreno_active_ring, .irq = a4xx_irq, .destroy = a4xx_destroy, #ifdef CONFIG_DEBUG_FS .show = a4xx_show, #endif }, + .get_timestamp = a4xx_get_timestamp, }; struct msm_gpu *a4xx_gpu_init(struct drm_device *dev) @@ -538,6 +538,7 @@ struct msm_gpu *gpu; struct msm_drm_private *priv = dev->dev_private; struct platform_device *pdev = priv->gpu_pdev; + struct msm_gpu_config a4xx_config = { 0 }; int ret; if (!pdev) { @@ -555,15 +556,19 @@ adreno_gpu = &a4xx_gpu->base; gpu = &adreno_gpu->base; - a4xx_gpu->pdev = pdev; - gpu->perfcntrs = NULL; gpu->num_perfcntrs = 0; adreno_gpu->registers = a4xx_registers; adreno_gpu->reg_offsets = a4xx_register_offsets; - ret = adreno_gpu_init(dev, pdev, adreno_gpu, &funcs); + a4xx_config.ioname = MSM_GPU_DEFAULT_IONAME; + a4xx_config.irqname = MSM_GPU_DEFAULT_IRQNAME; + a4xx_config.nr_rings = 1; + a4xx_config.va_start = 0x300000; + a4xx_config.va_end = 0xffffffff; + + ret = adreno_gpu_init(dev, pdev, adreno_gpu, &funcs, &a4xx_config); if (ret) goto fail; @@ -582,7 +587,7 @@ #endif } - if (!gpu->mmu) { + if (!gpu->aspace) { /* TODO we think it is possible to configure the GPU to * restrict access to VRAM carveout. But the required * registers are unknown. For now just bail out and diff -ruw linux-4.4.115/drivers/gpu/drm/msm/adreno/a4xx_gpu.h linux-4.4.115-fbx/drivers/gpu/drm/msm/adreno/a4xx_gpu.h --- linux-4.4.115/drivers/gpu/drm/msm/adreno/a4xx_gpu.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/gpu/drm/msm/adreno/a4xx_gpu.h 2019-01-22 16:16:23.483246225 +0100 @@ -1,4 +1,4 @@ -/* Copyright (c) 2014 The Linux Foundation. All rights reserved. +/* Copyright (c) 2014,2018 The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -23,7 +23,6 @@ struct a4xx_gpu { struct adreno_gpu base; - struct platform_device *pdev; /* if OCMEM is used for GMEM: */ uint32_t ocmem_base; diff -ruw linux-4.4.115/drivers/gpu/drm/msm/adreno/a4xx.xml.h linux-4.4.115-fbx/drivers/gpu/drm/msm/adreno/a4xx.xml.h --- linux-4.4.115/drivers/gpu/drm/msm/adreno/a4xx.xml.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/gpu/drm/msm/adreno/a4xx.xml.h 2019-01-22 16:16:23.479246189 +0100 @@ -8,17 +8,19 @@ git clone https://github.com/freedreno/envytools.git The rules-ng-ng source files this header was generated from are: -- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 398 bytes, from 2015-09-24 17:25:31) -- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2015-05-20 20:03:07) -- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 32901 bytes, from 2015-05-20 20:03:14) -- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 10755 bytes, from 2015-09-14 20:46:55) -- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 14968 bytes, from 2015-05-20 20:12:27) -- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 67771 bytes, from 2015-09-14 20:46:55) -- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 63970 bytes, from 2015-09-14 20:50:12) -- /home/robclark/src/freedreno/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2015-09-24 17:30:00) +- ./adreno.xml ( 431 bytes, from 2016-10-24 21:12:27) +- ./freedreno_copyright.xml ( 1572 bytes, from 2016-10-24 21:12:27) +- ./adreno/a2xx.xml ( 32901 bytes, from 2016-10-24 21:12:27) +- ./adreno/adreno_common.xml ( 12025 bytes, from 2016-10-24 21:12:27) +- ./adreno/adreno_pm4.xml ( 19684 bytes, from 2016-10-24 21:12:27) +- ./adreno/a3xx.xml ( 83840 bytes, from 2016-10-24 21:12:27) +- ./adreno/a4xx.xml ( 110708 bytes, from 2016-10-24 21:12:27) +- ./adreno/a5xx.xml ( 81207 bytes, from 2016-10-26 19:36:59) +- ./adreno/ocmem.xml ( 1773 bytes, from 2016-10-24 21:12:27) -Copyright (C) 2013-2015 by the following authors: +Copyright (C) 2013-2016 by the following authors: - Rob Clark (robclark) +- Ilia Mirkin (imirkin) Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the @@ -45,13 +47,18 @@ enum a4xx_color_fmt { RB4_A8_UNORM = 1, RB4_R8_UNORM = 2, + RB4_R8_SNORM = 3, + RB4_R8_UINT = 4, + RB4_R8_SINT = 5, RB4_R4G4B4A4_UNORM = 8, RB4_R5G5B5A1_UNORM = 10, - RB4_R5G6R5_UNORM = 14, + RB4_R5G6B5_UNORM = 14, RB4_R8G8_UNORM = 15, RB4_R8G8_SNORM = 16, RB4_R8G8_UINT = 17, RB4_R8G8_SINT = 18, + RB4_R16_UNORM = 19, + RB4_R16_SNORM = 20, RB4_R16_FLOAT = 21, RB4_R16_UINT = 22, RB4_R16_SINT = 23, @@ -63,12 +70,16 @@ RB4_R10G10B10A2_UNORM = 31, RB4_R10G10B10A2_UINT = 34, RB4_R11G11B10_FLOAT = 39, + RB4_R16G16_UNORM = 40, + RB4_R16G16_SNORM = 41, RB4_R16G16_FLOAT = 42, RB4_R16G16_UINT = 43, RB4_R16G16_SINT = 44, RB4_R32_FLOAT = 45, RB4_R32_UINT = 46, RB4_R32_SINT = 47, + RB4_R16G16B16A16_UNORM = 52, + RB4_R16G16B16A16_SNORM = 53, RB4_R16G16B16A16_FLOAT = 54, RB4_R16G16B16A16_UINT = 55, RB4_R16G16B16A16_SINT = 56, @@ -82,17 +93,10 @@ enum a4xx_tile_mode { TILE4_LINEAR = 0, + TILE4_2 = 2, TILE4_3 = 3, }; -enum a4xx_rb_blend_opcode { - BLEND_DST_PLUS_SRC = 0, - BLEND_SRC_MINUS_DST = 1, - BLEND_DST_MINUS_SRC = 2, - BLEND_MIN_DST_SRC = 3, - BLEND_MAX_DST_SRC = 4, -}; - enum a4xx_vtx_fmt { VFMT4_32_FLOAT = 1, VFMT4_32_32_FLOAT = 2, @@ -106,6 +110,7 @@ VFMT4_32_32_FIXED = 10, VFMT4_32_32_32_FIXED = 11, VFMT4_32_32_32_32_FIXED = 12, + VFMT4_11_11_10_FLOAT = 13, VFMT4_16_SINT = 16, VFMT4_16_16_SINT = 17, VFMT4_16_16_16_SINT = 18, @@ -146,52 +151,76 @@ VFMT4_8_8_SNORM = 53, VFMT4_8_8_8_SNORM = 54, VFMT4_8_8_8_8_SNORM = 55, - VFMT4_10_10_10_2_UINT = 60, - VFMT4_10_10_10_2_UNORM = 61, - VFMT4_10_10_10_2_SINT = 62, - VFMT4_10_10_10_2_SNORM = 63, + VFMT4_10_10_10_2_UINT = 56, + VFMT4_10_10_10_2_UNORM = 57, + VFMT4_10_10_10_2_SINT = 58, + VFMT4_10_10_10_2_SNORM = 59, + VFMT4_2_10_10_10_UINT = 60, + VFMT4_2_10_10_10_UNORM = 61, + VFMT4_2_10_10_10_SINT = 62, + VFMT4_2_10_10_10_SNORM = 63, }; enum a4xx_tex_fmt { - TFMT4_5_6_5_UNORM = 11, - TFMT4_5_5_5_1_UNORM = 10, - TFMT4_4_4_4_4_UNORM = 8, - TFMT4_X8Z24_UNORM = 71, - TFMT4_10_10_10_2_UNORM = 33, TFMT4_A8_UNORM = 3, - TFMT4_L8_A8_UNORM = 13, TFMT4_8_UNORM = 4, - TFMT4_8_8_UNORM = 14, - TFMT4_8_8_8_8_UNORM = 28, TFMT4_8_SNORM = 5, - TFMT4_8_8_SNORM = 15, - TFMT4_8_8_8_8_SNORM = 29, TFMT4_8_UINT = 6, - TFMT4_8_8_UINT = 16, - TFMT4_8_8_8_8_UINT = 30, TFMT4_8_SINT = 7, + TFMT4_4_4_4_4_UNORM = 8, + TFMT4_5_5_5_1_UNORM = 9, + TFMT4_5_6_5_UNORM = 11, + TFMT4_L8_A8_UNORM = 13, + TFMT4_8_8_UNORM = 14, + TFMT4_8_8_SNORM = 15, + TFMT4_8_8_UINT = 16, TFMT4_8_8_SINT = 17, - TFMT4_8_8_8_8_SINT = 31, + TFMT4_16_UNORM = 18, + TFMT4_16_SNORM = 19, + TFMT4_16_FLOAT = 20, TFMT4_16_UINT = 21, - TFMT4_16_16_UINT = 41, - TFMT4_16_16_16_16_UINT = 54, TFMT4_16_SINT = 22, + TFMT4_8_8_8_8_UNORM = 28, + TFMT4_8_8_8_8_SNORM = 29, + TFMT4_8_8_8_8_UINT = 30, + TFMT4_8_8_8_8_SINT = 31, + TFMT4_9_9_9_E5_FLOAT = 32, + TFMT4_10_10_10_2_UNORM = 33, + TFMT4_10_10_10_2_UINT = 34, + TFMT4_11_11_10_FLOAT = 37, + TFMT4_16_16_UNORM = 38, + TFMT4_16_16_SNORM = 39, + TFMT4_16_16_FLOAT = 40, + TFMT4_16_16_UINT = 41, TFMT4_16_16_SINT = 42, - TFMT4_16_16_16_16_SINT = 55, + TFMT4_32_FLOAT = 43, TFMT4_32_UINT = 44, - TFMT4_32_32_UINT = 57, - TFMT4_32_32_32_32_UINT = 64, TFMT4_32_SINT = 45, - TFMT4_32_32_SINT = 58, - TFMT4_32_32_32_32_SINT = 65, - TFMT4_16_FLOAT = 20, - TFMT4_16_16_FLOAT = 40, + TFMT4_16_16_16_16_UNORM = 51, + TFMT4_16_16_16_16_SNORM = 52, TFMT4_16_16_16_16_FLOAT = 53, - TFMT4_32_FLOAT = 43, + TFMT4_16_16_16_16_UINT = 54, + TFMT4_16_16_16_16_SINT = 55, TFMT4_32_32_FLOAT = 56, + TFMT4_32_32_UINT = 57, + TFMT4_32_32_SINT = 58, + TFMT4_32_32_32_FLOAT = 59, + TFMT4_32_32_32_UINT = 60, + TFMT4_32_32_32_SINT = 61, TFMT4_32_32_32_32_FLOAT = 63, - TFMT4_9_9_9_E5_FLOAT = 32, - TFMT4_11_11_10_FLOAT = 37, + TFMT4_32_32_32_32_UINT = 64, + TFMT4_32_32_32_32_SINT = 65, + TFMT4_X8Z24_UNORM = 71, + TFMT4_DXT1 = 86, + TFMT4_DXT3 = 87, + TFMT4_DXT5 = 88, + TFMT4_RGTC1_UNORM = 90, + TFMT4_RGTC1_SNORM = 91, + TFMT4_RGTC2_UNORM = 94, + TFMT4_RGTC2_SNORM = 95, + TFMT4_BPTC_UFLOAT = 97, + TFMT4_BPTC_FLOAT = 98, + TFMT4_BPTC = 99, TFMT4_ATC_RGB = 100, TFMT4_ATC_RGBA_EXPLICIT = 101, TFMT4_ATC_RGBA_INTERPOLATED = 102, @@ -240,6 +269,545 @@ EVEN_SPACING = 3, }; +enum a4xx_ccu_perfcounter_select { + CCU_BUSY_CYCLES = 0, + CCU_RB_DEPTH_RETURN_STALL = 2, + CCU_RB_COLOR_RETURN_STALL = 3, + CCU_DEPTH_BLOCKS = 6, + CCU_COLOR_BLOCKS = 7, + CCU_DEPTH_BLOCK_HIT = 8, + CCU_COLOR_BLOCK_HIT = 9, + CCU_DEPTH_FLAG1_COUNT = 10, + CCU_DEPTH_FLAG2_COUNT = 11, + CCU_DEPTH_FLAG3_COUNT = 12, + CCU_DEPTH_FLAG4_COUNT = 13, + CCU_COLOR_FLAG1_COUNT = 14, + CCU_COLOR_FLAG2_COUNT = 15, + CCU_COLOR_FLAG3_COUNT = 16, + CCU_COLOR_FLAG4_COUNT = 17, + CCU_PARTIAL_BLOCK_READ = 18, +}; + +enum a4xx_cp_perfcounter_select { + CP_ALWAYS_COUNT = 0, + CP_BUSY = 1, + CP_PFP_IDLE = 2, + CP_PFP_BUSY_WORKING = 3, + CP_PFP_STALL_CYCLES_ANY = 4, + CP_PFP_STARVE_CYCLES_ANY = 5, + CP_PFP_STARVED_PER_LOAD_ADDR = 6, + CP_PFP_STALLED_PER_STORE_ADDR = 7, + CP_PFP_PC_PROFILE = 8, + CP_PFP_MATCH_PM4_PKT_PROFILE = 9, + CP_PFP_COND_INDIRECT_DISCARDED = 10, + CP_LONG_RESUMPTIONS = 11, + CP_RESUME_CYCLES = 12, + CP_RESUME_TO_BOUNDARY_CYCLES = 13, + CP_LONG_PREEMPTIONS = 14, + CP_PREEMPT_CYCLES = 15, + CP_PREEMPT_TO_BOUNDARY_CYCLES = 16, + CP_ME_FIFO_EMPTY_PFP_IDLE = 17, + CP_ME_FIFO_EMPTY_PFP_BUSY = 18, + CP_ME_FIFO_NOT_EMPTY_NOT_FULL = 19, + CP_ME_FIFO_FULL_ME_BUSY = 20, + CP_ME_FIFO_FULL_ME_NON_WORKING = 21, + CP_ME_WAITING_FOR_PACKETS = 22, + CP_ME_BUSY_WORKING = 23, + CP_ME_STARVE_CYCLES_ANY = 24, + CP_ME_STARVE_CYCLES_PER_PROFILE = 25, + CP_ME_STALL_CYCLES_PER_PROFILE = 26, + CP_ME_PC_PROFILE = 27, + CP_RCIU_FIFO_EMPTY = 28, + CP_RCIU_FIFO_NOT_EMPTY_NOT_FULL = 29, + CP_RCIU_FIFO_FULL = 30, + CP_RCIU_FIFO_FULL_NO_CONTEXT = 31, + CP_RCIU_FIFO_FULL_AHB_MASTER = 32, + CP_RCIU_FIFO_FULL_OTHER = 33, + CP_AHB_IDLE = 34, + CP_AHB_STALL_ON_GRANT_NO_SPLIT = 35, + CP_AHB_STALL_ON_GRANT_SPLIT = 36, + CP_AHB_STALL_ON_GRANT_SPLIT_PROFILE = 37, + CP_AHB_BUSY_WORKING = 38, + CP_AHB_BUSY_STALL_ON_HRDY = 39, + CP_AHB_BUSY_STALL_ON_HRDY_PROFILE = 40, +}; + +enum a4xx_gras_ras_perfcounter_select { + RAS_SUPER_TILES = 0, + RAS_8X8_TILES = 1, + RAS_4X4_TILES = 2, + RAS_BUSY_CYCLES = 3, + RAS_STALL_CYCLES_BY_RB = 4, + RAS_STALL_CYCLES_BY_VSC = 5, + RAS_STARVE_CYCLES_BY_TSE = 6, + RAS_SUPERTILE_CYCLES = 7, + RAS_TILE_CYCLES = 8, + RAS_FULLY_COVERED_SUPER_TILES = 9, + RAS_FULLY_COVERED_8X8_TILES = 10, + RAS_4X4_PRIM = 11, + RAS_8X4_4X8_PRIM = 12, + RAS_8X8_PRIM = 13, +}; + +enum a4xx_gras_tse_perfcounter_select { + TSE_INPUT_PRIM = 0, + TSE_INPUT_NULL_PRIM = 1, + TSE_TRIVAL_REJ_PRIM = 2, + TSE_CLIPPED_PRIM = 3, + TSE_NEW_PRIM = 4, + TSE_ZERO_AREA_PRIM = 5, + TSE_FACENESS_CULLED_PRIM = 6, + TSE_ZERO_PIXEL_PRIM = 7, + TSE_OUTPUT_NULL_PRIM = 8, + TSE_OUTPUT_VISIBLE_PRIM = 9, + TSE_PRE_CLIP_PRIM = 10, + TSE_POST_CLIP_PRIM = 11, + TSE_BUSY_CYCLES = 12, + TSE_PC_STARVE = 13, + TSE_RAS_STALL = 14, + TSE_STALL_BARYPLANE_FIFO_FULL = 15, + TSE_STALL_ZPLANE_FIFO_FULL = 16, +}; + +enum a4xx_hlsq_perfcounter_select { + HLSQ_SP_VS_STAGE_CONSTANT = 0, + HLSQ_SP_VS_STAGE_INSTRUCTIONS = 1, + HLSQ_SP_FS_STAGE_CONSTANT = 2, + HLSQ_SP_FS_STAGE_INSTRUCTIONS = 3, + HLSQ_TP_STATE = 4, + HLSQ_QUADS = 5, + HLSQ_PIXELS = 6, + HLSQ_VERTICES = 7, + HLSQ_SP_VS_STAGE_DATA_BYTES = 13, + HLSQ_SP_FS_STAGE_DATA_BYTES = 14, + HLSQ_BUSY_CYCLES = 15, + HLSQ_STALL_CYCLES_SP_STATE = 16, + HLSQ_STALL_CYCLES_SP_VS_STAGE = 17, + HLSQ_STALL_CYCLES_SP_FS_STAGE = 18, + HLSQ_STALL_CYCLES_UCHE = 19, + HLSQ_RBBM_LOAD_CYCLES = 20, + HLSQ_DI_TO_VS_START_SP = 21, + HLSQ_DI_TO_FS_START_SP = 22, + HLSQ_VS_STAGE_START_TO_DONE_SP = 23, + HLSQ_FS_STAGE_START_TO_DONE_SP = 24, + HLSQ_SP_STATE_COPY_CYCLES_VS_STAGE = 25, + HLSQ_SP_STATE_COPY_CYCLES_FS_STAGE = 26, + HLSQ_UCHE_LATENCY_CYCLES = 27, + HLSQ_UCHE_LATENCY_COUNT = 28, + HLSQ_STARVE_CYCLES_VFD = 29, +}; + +enum a4xx_pc_perfcounter_select { + PC_VIS_STREAMS_LOADED = 0, + PC_VPC_PRIMITIVES = 2, + PC_DEAD_PRIM = 3, + PC_LIVE_PRIM = 4, + PC_DEAD_DRAWCALLS = 5, + PC_LIVE_DRAWCALLS = 6, + PC_VERTEX_MISSES = 7, + PC_STALL_CYCLES_VFD = 9, + PC_STALL_CYCLES_TSE = 10, + PC_STALL_CYCLES_UCHE = 11, + PC_WORKING_CYCLES = 12, + PC_IA_VERTICES = 13, + PC_GS_PRIMITIVES = 14, + PC_HS_INVOCATIONS = 15, + PC_DS_INVOCATIONS = 16, + PC_DS_PRIMITIVES = 17, + PC_STARVE_CYCLES_FOR_INDEX = 20, + PC_STARVE_CYCLES_FOR_TESS_FACTOR = 21, + PC_STARVE_CYCLES_FOR_VIZ_STREAM = 22, + PC_STALL_CYCLES_TESS = 23, + PC_STARVE_CYCLES_FOR_POSITION = 24, + PC_MODE0_DRAWCALL = 25, + PC_MODE1_DRAWCALL = 26, + PC_MODE2_DRAWCALL = 27, + PC_MODE3_DRAWCALL = 28, + PC_MODE4_DRAWCALL = 29, + PC_PREDICATED_DEAD_DRAWCALL = 30, + PC_STALL_CYCLES_BY_TSE_ONLY = 31, + PC_STALL_CYCLES_BY_VPC_ONLY = 32, + PC_VPC_POS_DATA_TRANSACTION = 33, + PC_BUSY_CYCLES = 34, + PC_STARVE_CYCLES_DI = 35, + PC_STALL_CYCLES_VPC = 36, + TESS_WORKING_CYCLES = 37, + TESS_NUM_CYCLES_SETUP_WORKING = 38, + TESS_NUM_CYCLES_PTGEN_WORKING = 39, + TESS_NUM_CYCLES_CONNGEN_WORKING = 40, + TESS_BUSY_CYCLES = 41, + TESS_STARVE_CYCLES_PC = 42, + TESS_STALL_CYCLES_PC = 43, +}; + +enum a4xx_pwr_perfcounter_select { + PWR_CORE_CLOCK_CYCLES = 0, + PWR_BUSY_CLOCK_CYCLES = 1, +}; + +enum a4xx_rb_perfcounter_select { + RB_BUSY_CYCLES = 0, + RB_BUSY_CYCLES_BINNING = 1, + RB_BUSY_CYCLES_RENDERING = 2, + RB_BUSY_CYCLES_RESOLVE = 3, + RB_STARVE_CYCLES_BY_SP = 4, + RB_STARVE_CYCLES_BY_RAS = 5, + RB_STARVE_CYCLES_BY_MARB = 6, + RB_STALL_CYCLES_BY_MARB = 7, + RB_STALL_CYCLES_BY_HLSQ = 8, + RB_RB_RB_MARB_DATA = 9, + RB_SP_RB_QUAD = 10, + RB_RAS_RB_Z_QUADS = 11, + RB_GMEM_CH0_READ = 12, + RB_GMEM_CH1_READ = 13, + RB_GMEM_CH0_WRITE = 14, + RB_GMEM_CH1_WRITE = 15, + RB_CP_CONTEXT_DONE = 16, + RB_CP_CACHE_FLUSH = 17, + RB_CP_ZPASS_DONE = 18, + RB_STALL_FIFO0_FULL = 19, + RB_STALL_FIFO1_FULL = 20, + RB_STALL_FIFO2_FULL = 21, + RB_STALL_FIFO3_FULL = 22, + RB_RB_HLSQ_TRANSACTIONS = 23, + RB_Z_READ = 24, + RB_Z_WRITE = 25, + RB_C_READ = 26, + RB_C_WRITE = 27, + RB_C_READ_LATENCY = 28, + RB_Z_READ_LATENCY = 29, + RB_STALL_BY_UCHE = 30, + RB_MARB_UCHE_TRANSACTIONS = 31, + RB_CACHE_STALL_MISS = 32, + RB_CACHE_STALL_FIFO_FULL = 33, + RB_8BIT_BLENDER_UNITS_ACTIVE = 34, + RB_16BIT_BLENDER_UNITS_ACTIVE = 35, + RB_SAMPLER_UNITS_ACTIVE = 36, + RB_TOTAL_PASS = 38, + RB_Z_PASS = 39, + RB_Z_FAIL = 40, + RB_S_FAIL = 41, + RB_POWER0 = 42, + RB_POWER1 = 43, + RB_POWER2 = 44, + RB_POWER3 = 45, + RB_POWER4 = 46, + RB_POWER5 = 47, + RB_POWER6 = 48, + RB_POWER7 = 49, +}; + +enum a4xx_rbbm_perfcounter_select { + RBBM_ALWAYS_ON = 0, + RBBM_VBIF_BUSY = 1, + RBBM_TSE_BUSY = 2, + RBBM_RAS_BUSY = 3, + RBBM_PC_DCALL_BUSY = 4, + RBBM_PC_VSD_BUSY = 5, + RBBM_VFD_BUSY = 6, + RBBM_VPC_BUSY = 7, + RBBM_UCHE_BUSY = 8, + RBBM_VSC_BUSY = 9, + RBBM_HLSQ_BUSY = 10, + RBBM_ANY_RB_BUSY = 11, + RBBM_ANY_TPL1_BUSY = 12, + RBBM_ANY_SP_BUSY = 13, + RBBM_ANY_MARB_BUSY = 14, + RBBM_ANY_ARB_BUSY = 15, + RBBM_AHB_STATUS_BUSY = 16, + RBBM_AHB_STATUS_STALLED = 17, + RBBM_AHB_STATUS_TXFR = 18, + RBBM_AHB_STATUS_TXFR_SPLIT = 19, + RBBM_AHB_STATUS_TXFR_ERROR = 20, + RBBM_AHB_STATUS_LONG_STALL = 21, + RBBM_STATUS_MASKED = 22, + RBBM_CP_BUSY_GFX_CORE_IDLE = 23, + RBBM_TESS_BUSY = 24, + RBBM_COM_BUSY = 25, + RBBM_DCOM_BUSY = 32, + RBBM_ANY_CCU_BUSY = 33, + RBBM_DPM_BUSY = 34, +}; + +enum a4xx_sp_perfcounter_select { + SP_LM_LOAD_INSTRUCTIONS = 0, + SP_LM_STORE_INSTRUCTIONS = 1, + SP_LM_ATOMICS = 2, + SP_GM_LOAD_INSTRUCTIONS = 3, + SP_GM_STORE_INSTRUCTIONS = 4, + SP_GM_ATOMICS = 5, + SP_VS_STAGE_TEX_INSTRUCTIONS = 6, + SP_VS_STAGE_CFLOW_INSTRUCTIONS = 7, + SP_VS_STAGE_EFU_INSTRUCTIONS = 8, + SP_VS_STAGE_FULL_ALU_INSTRUCTIONS = 9, + SP_VS_STAGE_HALF_ALU_INSTRUCTIONS = 10, + SP_FS_STAGE_TEX_INSTRUCTIONS = 11, + SP_FS_STAGE_CFLOW_INSTRUCTIONS = 12, + SP_FS_STAGE_EFU_INSTRUCTIONS = 13, + SP_FS_STAGE_FULL_ALU_INSTRUCTIONS = 14, + SP_FS_STAGE_HALF_ALU_INSTRUCTIONS = 15, + SP_VS_INSTRUCTIONS = 17, + SP_FS_INSTRUCTIONS = 18, + SP_ADDR_LOCK_COUNT = 19, + SP_UCHE_READ_TRANS = 20, + SP_UCHE_WRITE_TRANS = 21, + SP_EXPORT_VPC_TRANS = 22, + SP_EXPORT_RB_TRANS = 23, + SP_PIXELS_KILLED = 24, + SP_ICL1_REQUESTS = 25, + SP_ICL1_MISSES = 26, + SP_ICL0_REQUESTS = 27, + SP_ICL0_MISSES = 28, + SP_ALU_WORKING_CYCLES = 29, + SP_EFU_WORKING_CYCLES = 30, + SP_STALL_CYCLES_BY_VPC = 31, + SP_STALL_CYCLES_BY_TP = 32, + SP_STALL_CYCLES_BY_UCHE = 33, + SP_STALL_CYCLES_BY_RB = 34, + SP_BUSY_CYCLES = 35, + SP_HS_INSTRUCTIONS = 36, + SP_DS_INSTRUCTIONS = 37, + SP_GS_INSTRUCTIONS = 38, + SP_CS_INSTRUCTIONS = 39, + SP_SCHEDULER_NON_WORKING = 40, + SP_WAVE_CONTEXTS = 41, + SP_WAVE_CONTEXT_CYCLES = 42, + SP_POWER0 = 43, + SP_POWER1 = 44, + SP_POWER2 = 45, + SP_POWER3 = 46, + SP_POWER4 = 47, + SP_POWER5 = 48, + SP_POWER6 = 49, + SP_POWER7 = 50, + SP_POWER8 = 51, + SP_POWER9 = 52, + SP_POWER10 = 53, + SP_POWER11 = 54, + SP_POWER12 = 55, + SP_POWER13 = 56, + SP_POWER14 = 57, + SP_POWER15 = 58, +}; + +enum a4xx_tp_perfcounter_select { + TP_L1_REQUESTS = 0, + TP_L1_MISSES = 1, + TP_QUADS_OFFSET = 8, + TP_QUAD_SHADOW = 9, + TP_QUADS_ARRAY = 10, + TP_QUADS_GRADIENT = 11, + TP_QUADS_1D2D = 12, + TP_QUADS_3DCUBE = 13, + TP_BUSY_CYCLES = 16, + TP_STALL_CYCLES_BY_ARB = 17, + TP_STATE_CACHE_REQUESTS = 20, + TP_STATE_CACHE_MISSES = 21, + TP_POWER0 = 22, + TP_POWER1 = 23, + TP_POWER2 = 24, + TP_POWER3 = 25, + TP_POWER4 = 26, + TP_POWER5 = 27, + TP_POWER6 = 28, + TP_POWER7 = 29, +}; + +enum a4xx_uche_perfcounter_select { + UCHE_VBIF_READ_BEATS_TP = 0, + UCHE_VBIF_READ_BEATS_VFD = 1, + UCHE_VBIF_READ_BEATS_HLSQ = 2, + UCHE_VBIF_READ_BEATS_MARB = 3, + UCHE_VBIF_READ_BEATS_SP = 4, + UCHE_READ_REQUESTS_TP = 5, + UCHE_READ_REQUESTS_VFD = 6, + UCHE_READ_REQUESTS_HLSQ = 7, + UCHE_READ_REQUESTS_MARB = 8, + UCHE_READ_REQUESTS_SP = 9, + UCHE_WRITE_REQUESTS_MARB = 10, + UCHE_WRITE_REQUESTS_SP = 11, + UCHE_TAG_CHECK_FAILS = 12, + UCHE_EVICTS = 13, + UCHE_FLUSHES = 14, + UCHE_VBIF_LATENCY_CYCLES = 15, + UCHE_VBIF_LATENCY_SAMPLES = 16, + UCHE_BUSY_CYCLES = 17, + UCHE_VBIF_READ_BEATS_PC = 18, + UCHE_READ_REQUESTS_PC = 19, + UCHE_WRITE_REQUESTS_VPC = 20, + UCHE_STALL_BY_VBIF = 21, + UCHE_WRITE_REQUESTS_VSC = 22, + UCHE_POWER0 = 23, + UCHE_POWER1 = 24, + UCHE_POWER2 = 25, + UCHE_POWER3 = 26, + UCHE_POWER4 = 27, + UCHE_POWER5 = 28, + UCHE_POWER6 = 29, + UCHE_POWER7 = 30, +}; + +enum a4xx_vbif_perfcounter_select { + AXI_READ_REQUESTS_ID_0 = 0, + AXI_READ_REQUESTS_ID_1 = 1, + AXI_READ_REQUESTS_ID_2 = 2, + AXI_READ_REQUESTS_ID_3 = 3, + AXI_READ_REQUESTS_ID_4 = 4, + AXI_READ_REQUESTS_ID_5 = 5, + AXI_READ_REQUESTS_ID_6 = 6, + AXI_READ_REQUESTS_ID_7 = 7, + AXI_READ_REQUESTS_ID_8 = 8, + AXI_READ_REQUESTS_ID_9 = 9, + AXI_READ_REQUESTS_ID_10 = 10, + AXI_READ_REQUESTS_ID_11 = 11, + AXI_READ_REQUESTS_ID_12 = 12, + AXI_READ_REQUESTS_ID_13 = 13, + AXI_READ_REQUESTS_ID_14 = 14, + AXI_READ_REQUESTS_ID_15 = 15, + AXI0_READ_REQUESTS_TOTAL = 16, + AXI1_READ_REQUESTS_TOTAL = 17, + AXI2_READ_REQUESTS_TOTAL = 18, + AXI3_READ_REQUESTS_TOTAL = 19, + AXI_READ_REQUESTS_TOTAL = 20, + AXI_WRITE_REQUESTS_ID_0 = 21, + AXI_WRITE_REQUESTS_ID_1 = 22, + AXI_WRITE_REQUESTS_ID_2 = 23, + AXI_WRITE_REQUESTS_ID_3 = 24, + AXI_WRITE_REQUESTS_ID_4 = 25, + AXI_WRITE_REQUESTS_ID_5 = 26, + AXI_WRITE_REQUESTS_ID_6 = 27, + AXI_WRITE_REQUESTS_ID_7 = 28, + AXI_WRITE_REQUESTS_ID_8 = 29, + AXI_WRITE_REQUESTS_ID_9 = 30, + AXI_WRITE_REQUESTS_ID_10 = 31, + AXI_WRITE_REQUESTS_ID_11 = 32, + AXI_WRITE_REQUESTS_ID_12 = 33, + AXI_WRITE_REQUESTS_ID_13 = 34, + AXI_WRITE_REQUESTS_ID_14 = 35, + AXI_WRITE_REQUESTS_ID_15 = 36, + AXI0_WRITE_REQUESTS_TOTAL = 37, + AXI1_WRITE_REQUESTS_TOTAL = 38, + AXI2_WRITE_REQUESTS_TOTAL = 39, + AXI3_WRITE_REQUESTS_TOTAL = 40, + AXI_WRITE_REQUESTS_TOTAL = 41, + AXI_TOTAL_REQUESTS = 42, + AXI_READ_DATA_BEATS_ID_0 = 43, + AXI_READ_DATA_BEATS_ID_1 = 44, + AXI_READ_DATA_BEATS_ID_2 = 45, + AXI_READ_DATA_BEATS_ID_3 = 46, + AXI_READ_DATA_BEATS_ID_4 = 47, + AXI_READ_DATA_BEATS_ID_5 = 48, + AXI_READ_DATA_BEATS_ID_6 = 49, + AXI_READ_DATA_BEATS_ID_7 = 50, + AXI_READ_DATA_BEATS_ID_8 = 51, + AXI_READ_DATA_BEATS_ID_9 = 52, + AXI_READ_DATA_BEATS_ID_10 = 53, + AXI_READ_DATA_BEATS_ID_11 = 54, + AXI_READ_DATA_BEATS_ID_12 = 55, + AXI_READ_DATA_BEATS_ID_13 = 56, + AXI_READ_DATA_BEATS_ID_14 = 57, + AXI_READ_DATA_BEATS_ID_15 = 58, + AXI0_READ_DATA_BEATS_TOTAL = 59, + AXI1_READ_DATA_BEATS_TOTAL = 60, + AXI2_READ_DATA_BEATS_TOTAL = 61, + AXI3_READ_DATA_BEATS_TOTAL = 62, + AXI_READ_DATA_BEATS_TOTAL = 63, + AXI_WRITE_DATA_BEATS_ID_0 = 64, + AXI_WRITE_DATA_BEATS_ID_1 = 65, + AXI_WRITE_DATA_BEATS_ID_2 = 66, + AXI_WRITE_DATA_BEATS_ID_3 = 67, + AXI_WRITE_DATA_BEATS_ID_4 = 68, + AXI_WRITE_DATA_BEATS_ID_5 = 69, + AXI_WRITE_DATA_BEATS_ID_6 = 70, + AXI_WRITE_DATA_BEATS_ID_7 = 71, + AXI_WRITE_DATA_BEATS_ID_8 = 72, + AXI_WRITE_DATA_BEATS_ID_9 = 73, + AXI_WRITE_DATA_BEATS_ID_10 = 74, + AXI_WRITE_DATA_BEATS_ID_11 = 75, + AXI_WRITE_DATA_BEATS_ID_12 = 76, + AXI_WRITE_DATA_BEATS_ID_13 = 77, + AXI_WRITE_DATA_BEATS_ID_14 = 78, + AXI_WRITE_DATA_BEATS_ID_15 = 79, + AXI0_WRITE_DATA_BEATS_TOTAL = 80, + AXI1_WRITE_DATA_BEATS_TOTAL = 81, + AXI2_WRITE_DATA_BEATS_TOTAL = 82, + AXI3_WRITE_DATA_BEATS_TOTAL = 83, + AXI_WRITE_DATA_BEATS_TOTAL = 84, + AXI_DATA_BEATS_TOTAL = 85, + CYCLES_HELD_OFF_ID_0 = 86, + CYCLES_HELD_OFF_ID_1 = 87, + CYCLES_HELD_OFF_ID_2 = 88, + CYCLES_HELD_OFF_ID_3 = 89, + CYCLES_HELD_OFF_ID_4 = 90, + CYCLES_HELD_OFF_ID_5 = 91, + CYCLES_HELD_OFF_ID_6 = 92, + CYCLES_HELD_OFF_ID_7 = 93, + CYCLES_HELD_OFF_ID_8 = 94, + CYCLES_HELD_OFF_ID_9 = 95, + CYCLES_HELD_OFF_ID_10 = 96, + CYCLES_HELD_OFF_ID_11 = 97, + CYCLES_HELD_OFF_ID_12 = 98, + CYCLES_HELD_OFF_ID_13 = 99, + CYCLES_HELD_OFF_ID_14 = 100, + CYCLES_HELD_OFF_ID_15 = 101, + AXI_READ_REQUEST_HELD_OFF = 102, + AXI_WRITE_REQUEST_HELD_OFF = 103, + AXI_REQUEST_HELD_OFF = 104, + AXI_WRITE_DATA_HELD_OFF = 105, + OCMEM_AXI_READ_REQUEST_HELD_OFF = 106, + OCMEM_AXI_WRITE_REQUEST_HELD_OFF = 107, + OCMEM_AXI_REQUEST_HELD_OFF = 108, + OCMEM_AXI_WRITE_DATA_HELD_OFF = 109, + ELAPSED_CYCLES_DDR = 110, + ELAPSED_CYCLES_OCMEM = 111, +}; + +enum a4xx_vfd_perfcounter_select { + VFD_UCHE_BYTE_FETCHED = 0, + VFD_UCHE_TRANS = 1, + VFD_FETCH_INSTRUCTIONS = 3, + VFD_BUSY_CYCLES = 5, + VFD_STALL_CYCLES_UCHE = 6, + VFD_STALL_CYCLES_HLSQ = 7, + VFD_STALL_CYCLES_VPC_BYPASS = 8, + VFD_STALL_CYCLES_VPC_ALLOC = 9, + VFD_MODE_0_FIBERS = 13, + VFD_MODE_1_FIBERS = 14, + VFD_MODE_2_FIBERS = 15, + VFD_MODE_3_FIBERS = 16, + VFD_MODE_4_FIBERS = 17, + VFD_BFIFO_STALL = 18, + VFD_NUM_VERTICES_TOTAL = 19, + VFD_PACKER_FULL = 20, + VFD_UCHE_REQUEST_FIFO_FULL = 21, + VFD_STARVE_CYCLES_PC = 22, + VFD_STARVE_CYCLES_UCHE = 23, +}; + +enum a4xx_vpc_perfcounter_select { + VPC_SP_LM_COMPONENTS = 2, + VPC_SP0_LM_BYTES = 3, + VPC_SP1_LM_BYTES = 4, + VPC_SP2_LM_BYTES = 5, + VPC_SP3_LM_BYTES = 6, + VPC_WORKING_CYCLES = 7, + VPC_STALL_CYCLES_LM = 8, + VPC_STARVE_CYCLES_RAS = 9, + VPC_STREAMOUT_CYCLES = 10, + VPC_UCHE_TRANSACTIONS = 12, + VPC_STALL_CYCLES_UCHE = 13, + VPC_BUSY_CYCLES = 14, + VPC_STARVE_CYCLES_SP = 15, +}; + +enum a4xx_vsc_perfcounter_select { + VSC_BUSY_CYCLES = 0, + VSC_WORKING_CYCLES = 1, + VSC_STALL_CYCLES_UCHE = 2, + VSC_STARVE_CYCLES_RAS = 3, + VSC_EOT_NUM = 4, +}; + enum a4xx_tex_filter { A4XX_TEX_NEAREST = 0, A4XX_TEX_LINEAR = 1, @@ -326,6 +894,12 @@ #define REG_A4XX_RB_PERFCTR_RB_SEL_7 0x00000cce +#define REG_A4XX_RB_PERFCTR_CCU_SEL_0 0x00000ccf + +#define REG_A4XX_RB_PERFCTR_CCU_SEL_1 0x00000cd0 + +#define REG_A4XX_RB_PERFCTR_CCU_SEL_2 0x00000cd1 + #define REG_A4XX_RB_PERFCTR_CCU_SEL_3 0x00000cd2 #define REG_A4XX_RB_FRAME_BUFFER_DIMENSION 0x00000ce0 @@ -363,6 +937,7 @@ { return ((val >> 5) << A4XX_RB_MODE_CONTROL_HEIGHT__SHIFT) & A4XX_RB_MODE_CONTROL_HEIGHT__MASK; } +#define A4XX_RB_MODE_CONTROL_ENABLE_GMEM 0x00010000 #define REG_A4XX_RB_RENDER_CONTROL 0x000020a1 #define A4XX_RB_RENDER_CONTROL_BINNING_PASS 0x00000001 @@ -400,8 +975,13 @@ #define A4XX_RB_MRT_CONTROL_READ_DEST_ENABLE 0x00000008 #define A4XX_RB_MRT_CONTROL_BLEND 0x00000010 #define A4XX_RB_MRT_CONTROL_BLEND2 0x00000020 -#define A4XX_RB_MRT_CONTROL_FASTCLEAR 0x00000400 -#define A4XX_RB_MRT_CONTROL_B11 0x00000800 +#define A4XX_RB_MRT_CONTROL_ROP_ENABLE 0x00000040 +#define A4XX_RB_MRT_CONTROL_ROP_CODE__MASK 0x00000f00 +#define A4XX_RB_MRT_CONTROL_ROP_CODE__SHIFT 8 +static inline uint32_t A4XX_RB_MRT_CONTROL_ROP_CODE(enum a3xx_rop_code val) +{ + return ((val) << A4XX_RB_MRT_CONTROL_ROP_CODE__SHIFT) & A4XX_RB_MRT_CONTROL_ROP_CODE__MASK; +} #define A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK 0x0f000000 #define A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT 24 static inline uint32_t A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE(uint32_t val) @@ -461,7 +1041,7 @@ } #define A4XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK 0x000000e0 #define A4XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT 5 -static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(enum a4xx_rb_blend_opcode val) +static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(enum a3xx_rb_blend_opcode val) { return ((val) << A4XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT) & A4XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK; } @@ -479,7 +1059,7 @@ } #define A4XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK 0x00e00000 #define A4XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT 21 -static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(enum a4xx_rb_blend_opcode val) +static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(enum a3xx_rb_blend_opcode val) { return ((val) << A4XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT) & A4XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK; } @@ -490,13 +1070,19 @@ return ((val) << A4XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT) & A4XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK; } -#define REG_A4XX_RB_BLEND_RED 0x000020f3 -#define A4XX_RB_BLEND_RED_UINT__MASK 0x00007fff +#define REG_A4XX_RB_BLEND_RED 0x000020f0 +#define A4XX_RB_BLEND_RED_UINT__MASK 0x000000ff #define A4XX_RB_BLEND_RED_UINT__SHIFT 0 static inline uint32_t A4XX_RB_BLEND_RED_UINT(uint32_t val) { return ((val) << A4XX_RB_BLEND_RED_UINT__SHIFT) & A4XX_RB_BLEND_RED_UINT__MASK; } +#define A4XX_RB_BLEND_RED_SINT__MASK 0x0000ff00 +#define A4XX_RB_BLEND_RED_SINT__SHIFT 8 +static inline uint32_t A4XX_RB_BLEND_RED_SINT(uint32_t val) +{ + return ((val) << A4XX_RB_BLEND_RED_SINT__SHIFT) & A4XX_RB_BLEND_RED_SINT__MASK; +} #define A4XX_RB_BLEND_RED_FLOAT__MASK 0xffff0000 #define A4XX_RB_BLEND_RED_FLOAT__SHIFT 16 static inline uint32_t A4XX_RB_BLEND_RED_FLOAT(float val) @@ -504,13 +1090,27 @@ return ((util_float_to_half(val)) << A4XX_RB_BLEND_RED_FLOAT__SHIFT) & A4XX_RB_BLEND_RED_FLOAT__MASK; } -#define REG_A4XX_RB_BLEND_GREEN 0x000020f4 -#define A4XX_RB_BLEND_GREEN_UINT__MASK 0x00007fff +#define REG_A4XX_RB_BLEND_RED_F32 0x000020f1 +#define A4XX_RB_BLEND_RED_F32__MASK 0xffffffff +#define A4XX_RB_BLEND_RED_F32__SHIFT 0 +static inline uint32_t A4XX_RB_BLEND_RED_F32(float val) +{ + return ((fui(val)) << A4XX_RB_BLEND_RED_F32__SHIFT) & A4XX_RB_BLEND_RED_F32__MASK; +} + +#define REG_A4XX_RB_BLEND_GREEN 0x000020f2 +#define A4XX_RB_BLEND_GREEN_UINT__MASK 0x000000ff #define A4XX_RB_BLEND_GREEN_UINT__SHIFT 0 static inline uint32_t A4XX_RB_BLEND_GREEN_UINT(uint32_t val) { return ((val) << A4XX_RB_BLEND_GREEN_UINT__SHIFT) & A4XX_RB_BLEND_GREEN_UINT__MASK; } +#define A4XX_RB_BLEND_GREEN_SINT__MASK 0x0000ff00 +#define A4XX_RB_BLEND_GREEN_SINT__SHIFT 8 +static inline uint32_t A4XX_RB_BLEND_GREEN_SINT(uint32_t val) +{ + return ((val) << A4XX_RB_BLEND_GREEN_SINT__SHIFT) & A4XX_RB_BLEND_GREEN_SINT__MASK; +} #define A4XX_RB_BLEND_GREEN_FLOAT__MASK 0xffff0000 #define A4XX_RB_BLEND_GREEN_FLOAT__SHIFT 16 static inline uint32_t A4XX_RB_BLEND_GREEN_FLOAT(float val) @@ -518,13 +1118,27 @@ return ((util_float_to_half(val)) << A4XX_RB_BLEND_GREEN_FLOAT__SHIFT) & A4XX_RB_BLEND_GREEN_FLOAT__MASK; } -#define REG_A4XX_RB_BLEND_BLUE 0x000020f5 -#define A4XX_RB_BLEND_BLUE_UINT__MASK 0x00007fff +#define REG_A4XX_RB_BLEND_GREEN_F32 0x000020f3 +#define A4XX_RB_BLEND_GREEN_F32__MASK 0xffffffff +#define A4XX_RB_BLEND_GREEN_F32__SHIFT 0 +static inline uint32_t A4XX_RB_BLEND_GREEN_F32(float val) +{ + return ((fui(val)) << A4XX_RB_BLEND_GREEN_F32__SHIFT) & A4XX_RB_BLEND_GREEN_F32__MASK; +} + +#define REG_A4XX_RB_BLEND_BLUE 0x000020f4 +#define A4XX_RB_BLEND_BLUE_UINT__MASK 0x000000ff #define A4XX_RB_BLEND_BLUE_UINT__SHIFT 0 static inline uint32_t A4XX_RB_BLEND_BLUE_UINT(uint32_t val) { return ((val) << A4XX_RB_BLEND_BLUE_UINT__SHIFT) & A4XX_RB_BLEND_BLUE_UINT__MASK; } +#define A4XX_RB_BLEND_BLUE_SINT__MASK 0x0000ff00 +#define A4XX_RB_BLEND_BLUE_SINT__SHIFT 8 +static inline uint32_t A4XX_RB_BLEND_BLUE_SINT(uint32_t val) +{ + return ((val) << A4XX_RB_BLEND_BLUE_SINT__SHIFT) & A4XX_RB_BLEND_BLUE_SINT__MASK; +} #define A4XX_RB_BLEND_BLUE_FLOAT__MASK 0xffff0000 #define A4XX_RB_BLEND_BLUE_FLOAT__SHIFT 16 static inline uint32_t A4XX_RB_BLEND_BLUE_FLOAT(float val) @@ -532,13 +1146,27 @@ return ((util_float_to_half(val)) << A4XX_RB_BLEND_BLUE_FLOAT__SHIFT) & A4XX_RB_BLEND_BLUE_FLOAT__MASK; } +#define REG_A4XX_RB_BLEND_BLUE_F32 0x000020f5 +#define A4XX_RB_BLEND_BLUE_F32__MASK 0xffffffff +#define A4XX_RB_BLEND_BLUE_F32__SHIFT 0 +static inline uint32_t A4XX_RB_BLEND_BLUE_F32(float val) +{ + return ((fui(val)) << A4XX_RB_BLEND_BLUE_F32__SHIFT) & A4XX_RB_BLEND_BLUE_F32__MASK; +} + #define REG_A4XX_RB_BLEND_ALPHA 0x000020f6 -#define A4XX_RB_BLEND_ALPHA_UINT__MASK 0x00007fff +#define A4XX_RB_BLEND_ALPHA_UINT__MASK 0x000000ff #define A4XX_RB_BLEND_ALPHA_UINT__SHIFT 0 static inline uint32_t A4XX_RB_BLEND_ALPHA_UINT(uint32_t val) { return ((val) << A4XX_RB_BLEND_ALPHA_UINT__SHIFT) & A4XX_RB_BLEND_ALPHA_UINT__MASK; } +#define A4XX_RB_BLEND_ALPHA_SINT__MASK 0x0000ff00 +#define A4XX_RB_BLEND_ALPHA_SINT__SHIFT 8 +static inline uint32_t A4XX_RB_BLEND_ALPHA_SINT(uint32_t val) +{ + return ((val) << A4XX_RB_BLEND_ALPHA_SINT__SHIFT) & A4XX_RB_BLEND_ALPHA_SINT__MASK; +} #define A4XX_RB_BLEND_ALPHA_FLOAT__MASK 0xffff0000 #define A4XX_RB_BLEND_ALPHA_FLOAT__SHIFT 16 static inline uint32_t A4XX_RB_BLEND_ALPHA_FLOAT(float val) @@ -546,6 +1174,14 @@ return ((util_float_to_half(val)) << A4XX_RB_BLEND_ALPHA_FLOAT__SHIFT) & A4XX_RB_BLEND_ALPHA_FLOAT__MASK; } +#define REG_A4XX_RB_BLEND_ALPHA_F32 0x000020f7 +#define A4XX_RB_BLEND_ALPHA_F32__MASK 0xffffffff +#define A4XX_RB_BLEND_ALPHA_F32__SHIFT 0 +static inline uint32_t A4XX_RB_BLEND_ALPHA_F32(float val) +{ + return ((fui(val)) << A4XX_RB_BLEND_ALPHA_F32__SHIFT) & A4XX_RB_BLEND_ALPHA_F32__MASK; +} + #define REG_A4XX_RB_ALPHA_CONTROL 0x000020f8 #define A4XX_RB_ALPHA_CONTROL_ALPHA_REF__MASK 0x000000ff #define A4XX_RB_ALPHA_CONTROL_ALPHA_REF__SHIFT 0 @@ -568,7 +1204,7 @@ { return ((val) << A4XX_RB_FS_OUTPUT_ENABLE_BLEND__SHIFT) & A4XX_RB_FS_OUTPUT_ENABLE_BLEND__MASK; } -#define A4XX_RB_FS_OUTPUT_FAST_CLEAR 0x00000100 +#define A4XX_RB_FS_OUTPUT_INDEPENDENT_BLEND 0x00000100 #define A4XX_RB_FS_OUTPUT_SAMPLE_MASK__MASK 0xffff0000 #define A4XX_RB_FS_OUTPUT_SAMPLE_MASK__SHIFT 16 static inline uint32_t A4XX_RB_FS_OUTPUT_SAMPLE_MASK(uint32_t val) @@ -734,8 +1370,9 @@ { return ((val) << A4XX_RB_DEPTH_CONTROL_ZFUNC__SHIFT) & A4XX_RB_DEPTH_CONTROL_ZFUNC__MASK; } -#define A4XX_RB_DEPTH_CONTROL_BF_ENABLE 0x00000080 +#define A4XX_RB_DEPTH_CONTROL_Z_CLAMP_ENABLE 0x00000080 #define A4XX_RB_DEPTH_CONTROL_EARLY_Z_DISABLE 0x00010000 +#define A4XX_RB_DEPTH_CONTROL_FORCE_FRAGZ_TO_FS 0x00020000 #define A4XX_RB_DEPTH_CONTROL_Z_TEST_ENABLE 0x80000000 #define REG_A4XX_RB_DEPTH_CLEAR 0x00002102 @@ -996,8 +1633,386 @@ #define REG_A4XX_RBBM_CFG_DEBBUS_SEL_D 0x0000004d +#define REG_A4XX_RBBM_POWER_CNTL_IP 0x00000098 +#define A4XX_RBBM_POWER_CNTL_IP_SW_COLLAPSE 0x00000001 +#define A4XX_RBBM_POWER_CNTL_IP_SP_TP_PWR_ON 0x00100000 + #define REG_A4XX_RBBM_PERFCTR_CP_0_LO 0x0000009c +#define REG_A4XX_RBBM_PERFCTR_CP_0_HI 0x0000009d + +#define REG_A4XX_RBBM_PERFCTR_CP_1_LO 0x0000009e + +#define REG_A4XX_RBBM_PERFCTR_CP_1_HI 0x0000009f + +#define REG_A4XX_RBBM_PERFCTR_CP_2_LO 0x000000a0 + +#define REG_A4XX_RBBM_PERFCTR_CP_2_HI 0x000000a1 + +#define REG_A4XX_RBBM_PERFCTR_CP_3_LO 0x000000a2 + +#define REG_A4XX_RBBM_PERFCTR_CP_3_HI 0x000000a3 + +#define REG_A4XX_RBBM_PERFCTR_CP_4_LO 0x000000a4 + +#define REG_A4XX_RBBM_PERFCTR_CP_4_HI 0x000000a5 + +#define REG_A4XX_RBBM_PERFCTR_CP_5_LO 0x000000a6 + +#define REG_A4XX_RBBM_PERFCTR_CP_5_HI 0x000000a7 + +#define REG_A4XX_RBBM_PERFCTR_CP_6_LO 0x000000a8 + +#define REG_A4XX_RBBM_PERFCTR_CP_6_HI 0x000000a9 + +#define REG_A4XX_RBBM_PERFCTR_CP_7_LO 0x000000aa + +#define REG_A4XX_RBBM_PERFCTR_CP_7_HI 0x000000ab + +#define REG_A4XX_RBBM_PERFCTR_RBBM_0_LO 0x000000ac + +#define REG_A4XX_RBBM_PERFCTR_RBBM_0_HI 0x000000ad + +#define REG_A4XX_RBBM_PERFCTR_RBBM_1_LO 0x000000ae + +#define REG_A4XX_RBBM_PERFCTR_RBBM_1_HI 0x000000af + +#define REG_A4XX_RBBM_PERFCTR_RBBM_2_LO 0x000000b0 + +#define REG_A4XX_RBBM_PERFCTR_RBBM_2_HI 0x000000b1 + +#define REG_A4XX_RBBM_PERFCTR_RBBM_3_LO 0x000000b2 + +#define REG_A4XX_RBBM_PERFCTR_RBBM_3_HI 0x000000b3 + +#define REG_A4XX_RBBM_PERFCTR_PC_0_LO 0x000000b4 + +#define REG_A4XX_RBBM_PERFCTR_PC_0_HI 0x000000b5 + +#define REG_A4XX_RBBM_PERFCTR_PC_1_LO 0x000000b6 + +#define REG_A4XX_RBBM_PERFCTR_PC_1_HI 0x000000b7 + +#define REG_A4XX_RBBM_PERFCTR_PC_2_LO 0x000000b8 + +#define REG_A4XX_RBBM_PERFCTR_PC_2_HI 0x000000b9 + +#define REG_A4XX_RBBM_PERFCTR_PC_3_LO 0x000000ba + +#define REG_A4XX_RBBM_PERFCTR_PC_3_HI 0x000000bb + +#define REG_A4XX_RBBM_PERFCTR_PC_4_LO 0x000000bc + +#define REG_A4XX_RBBM_PERFCTR_PC_4_HI 0x000000bd + +#define REG_A4XX_RBBM_PERFCTR_PC_5_LO 0x000000be + +#define REG_A4XX_RBBM_PERFCTR_PC_5_HI 0x000000bf + +#define REG_A4XX_RBBM_PERFCTR_PC_6_LO 0x000000c0 + +#define REG_A4XX_RBBM_PERFCTR_PC_6_HI 0x000000c1 + +#define REG_A4XX_RBBM_PERFCTR_PC_7_LO 0x000000c2 + +#define REG_A4XX_RBBM_PERFCTR_PC_7_HI 0x000000c3 + +#define REG_A4XX_RBBM_PERFCTR_VFD_0_LO 0x000000c4 + +#define REG_A4XX_RBBM_PERFCTR_VFD_0_HI 0x000000c5 + +#define REG_A4XX_RBBM_PERFCTR_VFD_1_LO 0x000000c6 + +#define REG_A4XX_RBBM_PERFCTR_VFD_1_HI 0x000000c7 + +#define REG_A4XX_RBBM_PERFCTR_VFD_2_LO 0x000000c8 + +#define REG_A4XX_RBBM_PERFCTR_VFD_2_HI 0x000000c9 + +#define REG_A4XX_RBBM_PERFCTR_VFD_3_LO 0x000000ca + +#define REG_A4XX_RBBM_PERFCTR_VFD_3_HI 0x000000cb + +#define REG_A4XX_RBBM_PERFCTR_VFD_4_LO 0x000000cc + +#define REG_A4XX_RBBM_PERFCTR_VFD_4_HI 0x000000cd + +#define REG_A4XX_RBBM_PERFCTR_VFD_5_LO 0x000000ce + +#define REG_A4XX_RBBM_PERFCTR_VFD_5_HI 0x000000cf + +#define REG_A4XX_RBBM_PERFCTR_VFD_6_LO 0x000000d0 + +#define REG_A4XX_RBBM_PERFCTR_VFD_6_HI 0x000000d1 + +#define REG_A4XX_RBBM_PERFCTR_VFD_7_LO 0x000000d2 + +#define REG_A4XX_RBBM_PERFCTR_VFD_7_HI 0x000000d3 + +#define REG_A4XX_RBBM_PERFCTR_HLSQ_0_LO 0x000000d4 + +#define REG_A4XX_RBBM_PERFCTR_HLSQ_0_HI 0x000000d5 + +#define REG_A4XX_RBBM_PERFCTR_HLSQ_1_LO 0x000000d6 + +#define REG_A4XX_RBBM_PERFCTR_HLSQ_1_HI 0x000000d7 + +#define REG_A4XX_RBBM_PERFCTR_HLSQ_2_LO 0x000000d8 + +#define REG_A4XX_RBBM_PERFCTR_HLSQ_2_HI 0x000000d9 + +#define REG_A4XX_RBBM_PERFCTR_HLSQ_3_LO 0x000000da + +#define REG_A4XX_RBBM_PERFCTR_HLSQ_3_HI 0x000000db + +#define REG_A4XX_RBBM_PERFCTR_HLSQ_4_LO 0x000000dc + +#define REG_A4XX_RBBM_PERFCTR_HLSQ_4_HI 0x000000dd + +#define REG_A4XX_RBBM_PERFCTR_HLSQ_5_LO 0x000000de + +#define REG_A4XX_RBBM_PERFCTR_HLSQ_5_HI 0x000000df + +#define REG_A4XX_RBBM_PERFCTR_HLSQ_6_LO 0x000000e0 + +#define REG_A4XX_RBBM_PERFCTR_HLSQ_6_HI 0x000000e1 + +#define REG_A4XX_RBBM_PERFCTR_HLSQ_7_LO 0x000000e2 + +#define REG_A4XX_RBBM_PERFCTR_HLSQ_7_HI 0x000000e3 + +#define REG_A4XX_RBBM_PERFCTR_VPC_0_LO 0x000000e4 + +#define REG_A4XX_RBBM_PERFCTR_VPC_0_HI 0x000000e5 + +#define REG_A4XX_RBBM_PERFCTR_VPC_1_LO 0x000000e6 + +#define REG_A4XX_RBBM_PERFCTR_VPC_1_HI 0x000000e7 + +#define REG_A4XX_RBBM_PERFCTR_VPC_2_LO 0x000000e8 + +#define REG_A4XX_RBBM_PERFCTR_VPC_2_HI 0x000000e9 + +#define REG_A4XX_RBBM_PERFCTR_VPC_3_LO 0x000000ea + +#define REG_A4XX_RBBM_PERFCTR_VPC_3_HI 0x000000eb + +#define REG_A4XX_RBBM_PERFCTR_CCU_0_LO 0x000000ec + +#define REG_A4XX_RBBM_PERFCTR_CCU_0_HI 0x000000ed + +#define REG_A4XX_RBBM_PERFCTR_CCU_1_LO 0x000000ee + +#define REG_A4XX_RBBM_PERFCTR_CCU_1_HI 0x000000ef + +#define REG_A4XX_RBBM_PERFCTR_CCU_2_LO 0x000000f0 + +#define REG_A4XX_RBBM_PERFCTR_CCU_2_HI 0x000000f1 + +#define REG_A4XX_RBBM_PERFCTR_CCU_3_LO 0x000000f2 + +#define REG_A4XX_RBBM_PERFCTR_CCU_3_HI 0x000000f3 + +#define REG_A4XX_RBBM_PERFCTR_TSE_0_LO 0x000000f4 + +#define REG_A4XX_RBBM_PERFCTR_TSE_0_HI 0x000000f5 + +#define REG_A4XX_RBBM_PERFCTR_TSE_1_LO 0x000000f6 + +#define REG_A4XX_RBBM_PERFCTR_TSE_1_HI 0x000000f7 + +#define REG_A4XX_RBBM_PERFCTR_TSE_2_LO 0x000000f8 + +#define REG_A4XX_RBBM_PERFCTR_TSE_2_HI 0x000000f9 + +#define REG_A4XX_RBBM_PERFCTR_TSE_3_LO 0x000000fa + +#define REG_A4XX_RBBM_PERFCTR_TSE_3_HI 0x000000fb + +#define REG_A4XX_RBBM_PERFCTR_RAS_0_LO 0x000000fc + +#define REG_A4XX_RBBM_PERFCTR_RAS_0_HI 0x000000fd + +#define REG_A4XX_RBBM_PERFCTR_RAS_1_LO 0x000000fe + +#define REG_A4XX_RBBM_PERFCTR_RAS_1_HI 0x000000ff + +#define REG_A4XX_RBBM_PERFCTR_RAS_2_LO 0x00000100 + +#define REG_A4XX_RBBM_PERFCTR_RAS_2_HI 0x00000101 + +#define REG_A4XX_RBBM_PERFCTR_RAS_3_LO 0x00000102 + +#define REG_A4XX_RBBM_PERFCTR_RAS_3_HI 0x00000103 + +#define REG_A4XX_RBBM_PERFCTR_UCHE_0_LO 0x00000104 + +#define REG_A4XX_RBBM_PERFCTR_UCHE_0_HI 0x00000105 + +#define REG_A4XX_RBBM_PERFCTR_UCHE_1_LO 0x00000106 + +#define REG_A4XX_RBBM_PERFCTR_UCHE_1_HI 0x00000107 + +#define REG_A4XX_RBBM_PERFCTR_UCHE_2_LO 0x00000108 + +#define REG_A4XX_RBBM_PERFCTR_UCHE_2_HI 0x00000109 + +#define REG_A4XX_RBBM_PERFCTR_UCHE_3_LO 0x0000010a + +#define REG_A4XX_RBBM_PERFCTR_UCHE_3_HI 0x0000010b + +#define REG_A4XX_RBBM_PERFCTR_UCHE_4_LO 0x0000010c + +#define REG_A4XX_RBBM_PERFCTR_UCHE_4_HI 0x0000010d + +#define REG_A4XX_RBBM_PERFCTR_UCHE_5_LO 0x0000010e + +#define REG_A4XX_RBBM_PERFCTR_UCHE_5_HI 0x0000010f + +#define REG_A4XX_RBBM_PERFCTR_UCHE_6_LO 0x00000110 + +#define REG_A4XX_RBBM_PERFCTR_UCHE_6_HI 0x00000111 + +#define REG_A4XX_RBBM_PERFCTR_UCHE_7_LO 0x00000112 + +#define REG_A4XX_RBBM_PERFCTR_UCHE_7_HI 0x00000113 + +#define REG_A4XX_RBBM_PERFCTR_TP_0_LO 0x00000114 + +#define REG_A4XX_RBBM_PERFCTR_TP_0_HI 0x00000115 + +#define REG_A4XX_RBBM_PERFCTR_TP_0_LO 0x00000114 + +#define REG_A4XX_RBBM_PERFCTR_TP_0_HI 0x00000115 + +#define REG_A4XX_RBBM_PERFCTR_TP_1_LO 0x00000116 + +#define REG_A4XX_RBBM_PERFCTR_TP_1_HI 0x00000117 + +#define REG_A4XX_RBBM_PERFCTR_TP_2_LO 0x00000118 + +#define REG_A4XX_RBBM_PERFCTR_TP_2_HI 0x00000119 + +#define REG_A4XX_RBBM_PERFCTR_TP_3_LO 0x0000011a + +#define REG_A4XX_RBBM_PERFCTR_TP_3_HI 0x0000011b + +#define REG_A4XX_RBBM_PERFCTR_TP_4_LO 0x0000011c + +#define REG_A4XX_RBBM_PERFCTR_TP_4_HI 0x0000011d + +#define REG_A4XX_RBBM_PERFCTR_TP_5_LO 0x0000011e + +#define REG_A4XX_RBBM_PERFCTR_TP_5_HI 0x0000011f + +#define REG_A4XX_RBBM_PERFCTR_TP_6_LO 0x00000120 + +#define REG_A4XX_RBBM_PERFCTR_TP_6_HI 0x00000121 + +#define REG_A4XX_RBBM_PERFCTR_TP_7_LO 0x00000122 + +#define REG_A4XX_RBBM_PERFCTR_TP_7_HI 0x00000123 + +#define REG_A4XX_RBBM_PERFCTR_SP_0_LO 0x00000124 + +#define REG_A4XX_RBBM_PERFCTR_SP_0_HI 0x00000125 + +#define REG_A4XX_RBBM_PERFCTR_SP_1_LO 0x00000126 + +#define REG_A4XX_RBBM_PERFCTR_SP_1_HI 0x00000127 + +#define REG_A4XX_RBBM_PERFCTR_SP_2_LO 0x00000128 + +#define REG_A4XX_RBBM_PERFCTR_SP_2_HI 0x00000129 + +#define REG_A4XX_RBBM_PERFCTR_SP_3_LO 0x0000012a + +#define REG_A4XX_RBBM_PERFCTR_SP_3_HI 0x0000012b + +#define REG_A4XX_RBBM_PERFCTR_SP_4_LO 0x0000012c + +#define REG_A4XX_RBBM_PERFCTR_SP_4_HI 0x0000012d + +#define REG_A4XX_RBBM_PERFCTR_SP_5_LO 0x0000012e + +#define REG_A4XX_RBBM_PERFCTR_SP_5_HI 0x0000012f + +#define REG_A4XX_RBBM_PERFCTR_SP_6_LO 0x00000130 + +#define REG_A4XX_RBBM_PERFCTR_SP_6_HI 0x00000131 + +#define REG_A4XX_RBBM_PERFCTR_SP_7_LO 0x00000132 + +#define REG_A4XX_RBBM_PERFCTR_SP_7_HI 0x00000133 + +#define REG_A4XX_RBBM_PERFCTR_SP_8_LO 0x00000134 + +#define REG_A4XX_RBBM_PERFCTR_SP_8_HI 0x00000135 + +#define REG_A4XX_RBBM_PERFCTR_SP_9_LO 0x00000136 + +#define REG_A4XX_RBBM_PERFCTR_SP_9_HI 0x00000137 + +#define REG_A4XX_RBBM_PERFCTR_SP_10_LO 0x00000138 + +#define REG_A4XX_RBBM_PERFCTR_SP_10_HI 0x00000139 + +#define REG_A4XX_RBBM_PERFCTR_SP_11_LO 0x0000013a + +#define REG_A4XX_RBBM_PERFCTR_SP_11_HI 0x0000013b + +#define REG_A4XX_RBBM_PERFCTR_RB_0_LO 0x0000013c + +#define REG_A4XX_RBBM_PERFCTR_RB_0_HI 0x0000013d + +#define REG_A4XX_RBBM_PERFCTR_RB_1_LO 0x0000013e + +#define REG_A4XX_RBBM_PERFCTR_RB_1_HI 0x0000013f + +#define REG_A4XX_RBBM_PERFCTR_RB_2_LO 0x00000140 + +#define REG_A4XX_RBBM_PERFCTR_RB_2_HI 0x00000141 + +#define REG_A4XX_RBBM_PERFCTR_RB_3_LO 0x00000142 + +#define REG_A4XX_RBBM_PERFCTR_RB_3_HI 0x00000143 + +#define REG_A4XX_RBBM_PERFCTR_RB_4_LO 0x00000144 + +#define REG_A4XX_RBBM_PERFCTR_RB_4_HI 0x00000145 + +#define REG_A4XX_RBBM_PERFCTR_RB_5_LO 0x00000146 + +#define REG_A4XX_RBBM_PERFCTR_RB_5_HI 0x00000147 + +#define REG_A4XX_RBBM_PERFCTR_RB_6_LO 0x00000148 + +#define REG_A4XX_RBBM_PERFCTR_RB_6_HI 0x00000149 + +#define REG_A4XX_RBBM_PERFCTR_RB_7_LO 0x0000014a + +#define REG_A4XX_RBBM_PERFCTR_RB_7_HI 0x0000014b + +#define REG_A4XX_RBBM_PERFCTR_VSC_0_LO 0x0000014c + +#define REG_A4XX_RBBM_PERFCTR_VSC_0_HI 0x0000014d + +#define REG_A4XX_RBBM_PERFCTR_VSC_1_LO 0x0000014e + +#define REG_A4XX_RBBM_PERFCTR_VSC_1_HI 0x0000014f + +#define REG_A4XX_RBBM_PERFCTR_PWR_0_LO 0x00000166 + +#define REG_A4XX_RBBM_PERFCTR_PWR_0_HI 0x00000167 + +#define REG_A4XX_RBBM_PERFCTR_PWR_1_LO 0x00000168 + +#define REG_A4XX_RBBM_PERFCTR_PWR_1_HI 0x00000169 + +#define REG_A4XX_RBBM_ALWAYSON_COUNTER_LO 0x0000016e + +#define REG_A4XX_RBBM_ALWAYSON_COUNTER_HI 0x0000016f + static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_SP(uint32_t i0) { return 0x00000068 + 0x1*i0; } static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_SP_REG(uint32_t i0) { return 0x00000068 + 0x1*i0; } @@ -1046,6 +2061,10 @@ static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_RB_MARB_CCU_L1_REG(uint32_t i0) { return 0x0000008e + 0x1*i0; } +#define REG_A4XX_RBBM_SP_REGFILE_SLEEP_CNTL_0 0x00000099 + +#define REG_A4XX_RBBM_SP_REGFILE_SLEEP_CNTL_1 0x0000009a + #define REG_A4XX_RBBM_PERFCTR_PWR_1_LO 0x00000168 #define REG_A4XX_RBBM_PERFCTR_CTL 0x00000170 @@ -1060,6 +2079,14 @@ #define REG_A4XX_RBBM_PERFCTR_LOAD_VALUE_HI 0x00000175 +#define REG_A4XX_RBBM_PERFCTR_RBBM_SEL_0 0x00000176 + +#define REG_A4XX_RBBM_PERFCTR_RBBM_SEL_1 0x00000177 + +#define REG_A4XX_RBBM_PERFCTR_RBBM_SEL_2 0x00000178 + +#define REG_A4XX_RBBM_PERFCTR_RBBM_SEL_3 0x00000179 + #define REG_A4XX_RBBM_GPU_BUSY_MASKED 0x0000017a #define REG_A4XX_RBBM_INT_0_STATUS 0x0000017d @@ -1099,6 +2126,11 @@ #define REG_A4XX_RBBM_INTERFACE_RRDY_STATUS5 0x0000019f +#define REG_A4XX_RBBM_POWER_STATUS 0x000001b0 +#define A4XX_RBBM_POWER_STATUS_SP_TP_PWR_ON 0x00100000 + +#define REG_A4XX_RBBM_WAIT_IDLE_CLOCKS_CTL2 0x000001b8 + #define REG_A4XX_CP_SCRATCH_UMASK 0x00000228 #define REG_A4XX_CP_SCRATCH_ADDR 0x00000229 @@ -1167,11 +2199,23 @@ #define REG_A4XX_CP_DRAW_STATE_ADDR 0x00000232 -#define REG_A4XX_CP_PROTECT_REG_0 0x00000240 - static inline uint32_t REG_A4XX_CP_PROTECT(uint32_t i0) { return 0x00000240 + 0x1*i0; } static inline uint32_t REG_A4XX_CP_PROTECT_REG(uint32_t i0) { return 0x00000240 + 0x1*i0; } +#define A4XX_CP_PROTECT_REG_BASE_ADDR__MASK 0x0001ffff +#define A4XX_CP_PROTECT_REG_BASE_ADDR__SHIFT 0 +static inline uint32_t A4XX_CP_PROTECT_REG_BASE_ADDR(uint32_t val) +{ + return ((val) << A4XX_CP_PROTECT_REG_BASE_ADDR__SHIFT) & A4XX_CP_PROTECT_REG_BASE_ADDR__MASK; +} +#define A4XX_CP_PROTECT_REG_MASK_LEN__MASK 0x1f000000 +#define A4XX_CP_PROTECT_REG_MASK_LEN__SHIFT 24 +static inline uint32_t A4XX_CP_PROTECT_REG_MASK_LEN(uint32_t val) +{ + return ((val) << A4XX_CP_PROTECT_REG_MASK_LEN__SHIFT) & A4XX_CP_PROTECT_REG_MASK_LEN__MASK; +} +#define A4XX_CP_PROTECT_REG_TRAP_WRITE 0x20000000 +#define A4XX_CP_PROTECT_REG_TRAP_READ 0x40000000 #define REG_A4XX_CP_PROTECT_CTRL 0x00000250 @@ -1191,6 +2235,20 @@ #define REG_A4XX_CP_PERFCTR_CP_SEL_0 0x00000500 +#define REG_A4XX_CP_PERFCTR_CP_SEL_1 0x00000501 + +#define REG_A4XX_CP_PERFCTR_CP_SEL_2 0x00000502 + +#define REG_A4XX_CP_PERFCTR_CP_SEL_3 0x00000503 + +#define REG_A4XX_CP_PERFCTR_CP_SEL_4 0x00000504 + +#define REG_A4XX_CP_PERFCTR_CP_SEL_5 0x00000505 + +#define REG_A4XX_CP_PERFCTR_CP_SEL_6 0x00000506 + +#define REG_A4XX_CP_PERFCTR_CP_SEL_7 0x00000507 + #define REG_A4XX_CP_PERFCOMBINER_SELECT 0x0000050b static inline uint32_t REG_A4XX_CP_SCRATCH(uint32_t i0) { return 0x00000578 + 0x1*i0; } @@ -1201,6 +2259,28 @@ #define REG_A4XX_SP_MODE_CONTROL 0x00000ec3 +#define REG_A4XX_SP_PERFCTR_SP_SEL_0 0x00000ec4 + +#define REG_A4XX_SP_PERFCTR_SP_SEL_1 0x00000ec5 + +#define REG_A4XX_SP_PERFCTR_SP_SEL_2 0x00000ec6 + +#define REG_A4XX_SP_PERFCTR_SP_SEL_3 0x00000ec7 + +#define REG_A4XX_SP_PERFCTR_SP_SEL_4 0x00000ec8 + +#define REG_A4XX_SP_PERFCTR_SP_SEL_5 0x00000ec9 + +#define REG_A4XX_SP_PERFCTR_SP_SEL_6 0x00000eca + +#define REG_A4XX_SP_PERFCTR_SP_SEL_7 0x00000ecb + +#define REG_A4XX_SP_PERFCTR_SP_SEL_8 0x00000ecc + +#define REG_A4XX_SP_PERFCTR_SP_SEL_9 0x00000ecd + +#define REG_A4XX_SP_PERFCTR_SP_SEL_10 0x00000ece + #define REG_A4XX_SP_PERFCTR_SP_SEL_11 0x00000ecf #define REG_A4XX_SP_SP_CTRL_REG 0x000022c0 @@ -1226,7 +2306,7 @@ { return ((val) << A4XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A4XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK; } -#define A4XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x0003fc00 +#define A4XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x0000fc00 #define A4XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 10 static inline uint32_t A4XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) { @@ -1374,7 +2454,7 @@ { return ((val) << A4XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A4XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK; } -#define A4XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x0003fc00 +#define A4XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x0000fc00 #define A4XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 10 static inline uint32_t A4XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) { @@ -1699,6 +2779,12 @@ #define REG_A4XX_VPC_DEBUG_ECO_CONTROL 0x00000e64 +#define REG_A4XX_VPC_PERFCTR_VPC_SEL_0 0x00000e65 + +#define REG_A4XX_VPC_PERFCTR_VPC_SEL_1 0x00000e66 + +#define REG_A4XX_VPC_PERFCTR_VPC_SEL_2 0x00000e67 + #define REG_A4XX_VPC_PERFCTR_VPC_SEL_3 0x00000e68 #define REG_A4XX_VPC_ATTR 0x00002140 @@ -1811,6 +2897,20 @@ #define REG_A4XX_VFD_DEBUG_CONTROL 0x00000e40 +#define REG_A4XX_VFD_PERFCTR_VFD_SEL_0 0x00000e43 + +#define REG_A4XX_VFD_PERFCTR_VFD_SEL_1 0x00000e44 + +#define REG_A4XX_VFD_PERFCTR_VFD_SEL_2 0x00000e45 + +#define REG_A4XX_VFD_PERFCTR_VFD_SEL_3 0x00000e46 + +#define REG_A4XX_VFD_PERFCTR_VFD_SEL_4 0x00000e47 + +#define REG_A4XX_VFD_PERFCTR_VFD_SEL_5 0x00000e48 + +#define REG_A4XX_VFD_PERFCTR_VFD_SEL_6 0x00000e49 + #define REG_A4XX_VFD_PERFCTR_VFD_SEL_7 0x00000e4a #define REG_A4XX_VGT_CL_INITIATOR 0x000021d0 @@ -1967,6 +3067,20 @@ #define REG_A4XX_TPL1_TP_MODE_CONTROL 0x00000f03 +#define REG_A4XX_TPL1_PERFCTR_TP_SEL_0 0x00000f04 + +#define REG_A4XX_TPL1_PERFCTR_TP_SEL_1 0x00000f05 + +#define REG_A4XX_TPL1_PERFCTR_TP_SEL_2 0x00000f06 + +#define REG_A4XX_TPL1_PERFCTR_TP_SEL_3 0x00000f07 + +#define REG_A4XX_TPL1_PERFCTR_TP_SEL_4 0x00000f08 + +#define REG_A4XX_TPL1_PERFCTR_TP_SEL_5 0x00000f09 + +#define REG_A4XX_TPL1_PERFCTR_TP_SEL_6 0x00000f0a + #define REG_A4XX_TPL1_PERFCTR_TP_SEL_7 0x00000f0b #define REG_A4XX_TPL1_TP_TEX_OFFSET 0x00002380 @@ -2021,9 +3135,25 @@ #define REG_A4XX_GRAS_PERFCTR_TSE_SEL_0 0x00000c88 +#define REG_A4XX_GRAS_PERFCTR_TSE_SEL_1 0x00000c89 + +#define REG_A4XX_GRAS_PERFCTR_TSE_SEL_2 0x00000c8a + #define REG_A4XX_GRAS_PERFCTR_TSE_SEL_3 0x00000c8b +#define REG_A4XX_GRAS_PERFCTR_RAS_SEL_0 0x00000c8c + +#define REG_A4XX_GRAS_PERFCTR_RAS_SEL_1 0x00000c8d + +#define REG_A4XX_GRAS_PERFCTR_RAS_SEL_2 0x00000c8e + +#define REG_A4XX_GRAS_PERFCTR_RAS_SEL_3 0x00000c8f + #define REG_A4XX_GRAS_CL_CLIP_CNTL 0x00002000 +#define A4XX_GRAS_CL_CLIP_CNTL_CLIP_DISABLE 0x00008000 +#define A4XX_GRAS_CL_CLIP_CNTL_ZNEAR_CLIP_DISABLE 0x00010000 +#define A4XX_GRAS_CL_CLIP_CNTL_ZFAR_CLIP_DISABLE 0x00020000 +#define A4XX_GRAS_CL_CLIP_CNTL_ZERO_GB_SCALE_Z 0x00400000 #define REG_A4XX_GRAS_CLEAR_CNTL 0x00002003 #define A4XX_GRAS_CLEAR_CNTL_NOT_FASTCLEAR 0x00000001 @@ -2114,6 +3244,7 @@ #define REG_A4XX_GRAS_ALPHA_CONTROL 0x00002073 #define A4XX_GRAS_ALPHA_CONTROL_ALPHA_TEST_ENABLE 0x00000004 +#define A4XX_GRAS_ALPHA_CONTROL_FORCE_FRAGZ_TO_FS 0x00000008 #define REG_A4XX_GRAS_SU_POLY_OFFSET_SCALE 0x00002074 #define A4XX_GRAS_SU_POLY_OFFSET_SCALE__MASK 0xffffffff @@ -2285,6 +3416,20 @@ #define REG_A4XX_UCHE_CACHE_WAYS_VFD 0x00000e8c +#define REG_A4XX_UCHE_PERFCTR_UCHE_SEL_0 0x00000e8e + +#define REG_A4XX_UCHE_PERFCTR_UCHE_SEL_1 0x00000e8f + +#define REG_A4XX_UCHE_PERFCTR_UCHE_SEL_2 0x00000e90 + +#define REG_A4XX_UCHE_PERFCTR_UCHE_SEL_3 0x00000e91 + +#define REG_A4XX_UCHE_PERFCTR_UCHE_SEL_4 0x00000e92 + +#define REG_A4XX_UCHE_PERFCTR_UCHE_SEL_5 0x00000e93 + +#define REG_A4XX_UCHE_PERFCTR_UCHE_SEL_6 0x00000e94 + #define REG_A4XX_UCHE_PERFCTR_UCHE_SEL_7 0x00000e95 #define REG_A4XX_HLSQ_TIMEOUT_THRESHOLD 0x00000e00 @@ -2295,6 +3440,22 @@ #define REG_A4XX_HLSQ_PERF_PIPE_MASK 0x00000e0e +#define REG_A4XX_HLSQ_PERFCTR_HLSQ_SEL_0 0x00000e06 + +#define REG_A4XX_HLSQ_PERFCTR_HLSQ_SEL_1 0x00000e07 + +#define REG_A4XX_HLSQ_PERFCTR_HLSQ_SEL_2 0x00000e08 + +#define REG_A4XX_HLSQ_PERFCTR_HLSQ_SEL_3 0x00000e09 + +#define REG_A4XX_HLSQ_PERFCTR_HLSQ_SEL_4 0x00000e0a + +#define REG_A4XX_HLSQ_PERFCTR_HLSQ_SEL_5 0x00000e0b + +#define REG_A4XX_HLSQ_PERFCTR_HLSQ_SEL_6 0x00000e0c + +#define REG_A4XX_HLSQ_PERFCTR_HLSQ_SEL_7 0x00000e0d + #define REG_A4XX_HLSQ_CONTROL_0_REG 0x000023c0 #define A4XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__MASK 0x00000010 #define A4XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__SHIFT 4 @@ -2545,14 +3706,42 @@ #define REG_A4XX_PC_BINNING_COMMAND 0x00000d00 #define A4XX_PC_BINNING_COMMAND_BINNING_ENABLE 0x00000001 +#define REG_A4XX_PC_TESSFACTOR_ADDR 0x00000d08 + #define REG_A4XX_PC_DRAWCALL_SETUP_OVERRIDE 0x00000d0c #define REG_A4XX_PC_PERFCTR_PC_SEL_0 0x00000d10 +#define REG_A4XX_PC_PERFCTR_PC_SEL_1 0x00000d11 + +#define REG_A4XX_PC_PERFCTR_PC_SEL_2 0x00000d12 + +#define REG_A4XX_PC_PERFCTR_PC_SEL_3 0x00000d13 + +#define REG_A4XX_PC_PERFCTR_PC_SEL_4 0x00000d14 + +#define REG_A4XX_PC_PERFCTR_PC_SEL_5 0x00000d15 + +#define REG_A4XX_PC_PERFCTR_PC_SEL_6 0x00000d16 + #define REG_A4XX_PC_PERFCTR_PC_SEL_7 0x00000d17 #define REG_A4XX_PC_BIN_BASE 0x000021c0 +#define REG_A4XX_PC_VSTREAM_CONTROL 0x000021c2 +#define A4XX_PC_VSTREAM_CONTROL_SIZE__MASK 0x003f0000 +#define A4XX_PC_VSTREAM_CONTROL_SIZE__SHIFT 16 +static inline uint32_t A4XX_PC_VSTREAM_CONTROL_SIZE(uint32_t val) +{ + return ((val) << A4XX_PC_VSTREAM_CONTROL_SIZE__SHIFT) & A4XX_PC_VSTREAM_CONTROL_SIZE__MASK; +} +#define A4XX_PC_VSTREAM_CONTROL_N__MASK 0x07c00000 +#define A4XX_PC_VSTREAM_CONTROL_N__SHIFT 22 +static inline uint32_t A4XX_PC_VSTREAM_CONTROL_N(uint32_t val) +{ + return ((val) << A4XX_PC_VSTREAM_CONTROL_N__SHIFT) & A4XX_PC_VSTREAM_CONTROL_N__MASK; +} + #define REG_A4XX_PC_PRIM_VTX_CNTL 0x000021c4 #define A4XX_PC_PRIM_VTX_CNTL_VAROUT__MASK 0x0000000f #define A4XX_PC_PRIM_VTX_CNTL_VAROUT__SHIFT 0 @@ -2564,7 +3753,20 @@ #define A4XX_PC_PRIM_VTX_CNTL_PROVOKING_VTX_LAST 0x02000000 #define A4XX_PC_PRIM_VTX_CNTL_PSIZE 0x04000000 -#define REG_A4XX_UNKNOWN_21C5 0x000021c5 +#define REG_A4XX_PC_PRIM_VTX_CNTL2 0x000021c5 +#define A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_FRONT_PTYPE__MASK 0x00000007 +#define A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_FRONT_PTYPE__SHIFT 0 +static inline uint32_t A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_FRONT_PTYPE(enum adreno_pa_su_sc_draw val) +{ + return ((val) << A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_FRONT_PTYPE__SHIFT) & A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_FRONT_PTYPE__MASK; +} +#define A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_BACK_PTYPE__MASK 0x00000038 +#define A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_BACK_PTYPE__SHIFT 3 +static inline uint32_t A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_BACK_PTYPE(enum adreno_pa_su_sc_draw val) +{ + return ((val) << A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_BACK_PTYPE__SHIFT) & A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_BACK_PTYPE__MASK; +} +#define A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_ENABLE 0x00000040 #define REG_A4XX_PC_RESTART_INDEX 0x000021c6 @@ -2602,12 +3804,8 @@ { return ((val) << A4XX_PC_HS_PARAM_SPACING__SHIFT) & A4XX_PC_HS_PARAM_SPACING__MASK; } -#define A4XX_PC_HS_PARAM_PRIMTYPE__MASK 0x01800000 -#define A4XX_PC_HS_PARAM_PRIMTYPE__SHIFT 23 -static inline uint32_t A4XX_PC_HS_PARAM_PRIMTYPE(enum adreno_pa_su_sc_draw val) -{ - return ((val) << A4XX_PC_HS_PARAM_PRIMTYPE__SHIFT) & A4XX_PC_HS_PARAM_PRIMTYPE__MASK; -} +#define A4XX_PC_HS_PARAM_CW 0x00800000 +#define A4XX_PC_HS_PARAM_CONNECTED 0x01000000 #define REG_A4XX_VBIF_VERSION 0x00003000 @@ -2646,20 +3844,6 @@ #define REG_A4XX_UNKNOWN_20EF 0x000020ef -#define REG_A4XX_UNKNOWN_20F0 0x000020f0 - -#define REG_A4XX_UNKNOWN_20F1 0x000020f1 - -#define REG_A4XX_UNKNOWN_20F2 0x000020f2 - -#define REG_A4XX_UNKNOWN_20F7 0x000020f7 -#define A4XX_UNKNOWN_20F7__MASK 0xffffffff -#define A4XX_UNKNOWN_20F7__SHIFT 0 -static inline uint32_t A4XX_UNKNOWN_20F7(float val) -{ - return ((fui(val)) << A4XX_UNKNOWN_20F7__SHIFT) & A4XX_UNKNOWN_20F7__MASK; -} - #define REG_A4XX_UNKNOWN_2152 0x00002152 #define REG_A4XX_UNKNOWN_2153 0x00002153 @@ -2720,6 +3904,12 @@ { return ((val) << A4XX_TEX_SAMP_0_ANISO__SHIFT) & A4XX_TEX_SAMP_0_ANISO__MASK; } +#define A4XX_TEX_SAMP_0_LOD_BIAS__MASK 0xfff80000 +#define A4XX_TEX_SAMP_0_LOD_BIAS__SHIFT 19 +static inline uint32_t A4XX_TEX_SAMP_0_LOD_BIAS(float val) +{ + return ((((int32_t)(val * 256.0))) << A4XX_TEX_SAMP_0_LOD_BIAS__SHIFT) & A4XX_TEX_SAMP_0_LOD_BIAS__MASK; +} #define REG_A4XX_TEX_SAMP_1 0x00000001 #define A4XX_TEX_SAMP_1_COMPARE_FUNC__MASK 0x0000000e @@ -2728,6 +3918,7 @@ { return ((val) << A4XX_TEX_SAMP_1_COMPARE_FUNC__SHIFT) & A4XX_TEX_SAMP_1_COMPARE_FUNC__MASK; } +#define A4XX_TEX_SAMP_1_CUBEMAPSEAMLESSFILTOFF 0x00000010 #define A4XX_TEX_SAMP_1_UNNORM_COORDS 0x00000020 #define A4XX_TEX_SAMP_1_MIPFILTER_LINEAR_FAR 0x00000040 #define A4XX_TEX_SAMP_1_MAX_LOD__MASK 0x000fff00 @@ -2796,7 +3987,7 @@ { return ((val) << A4XX_TEX_CONST_1_HEIGHT__SHIFT) & A4XX_TEX_CONST_1_HEIGHT__MASK; } -#define A4XX_TEX_CONST_1_WIDTH__MASK 0x1fff8000 +#define A4XX_TEX_CONST_1_WIDTH__MASK 0x3fff8000 #define A4XX_TEX_CONST_1_WIDTH__SHIFT 15 static inline uint32_t A4XX_TEX_CONST_1_WIDTH(uint32_t val) { diff -ruw linux-4.4.115/drivers/gpu/drm/msm/adreno/adreno_common.xml.h linux-4.4.115-fbx/drivers/gpu/drm/msm/adreno/adreno_common.xml.h --- linux-4.4.115/drivers/gpu/drm/msm/adreno/adreno_common.xml.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/gpu/drm/msm/adreno/adreno_common.xml.h 2019-01-22 16:16:23.483246225 +0100 @@ -8,17 +8,19 @@ git clone https://github.com/freedreno/envytools.git The rules-ng-ng source files this header was generated from are: -- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 398 bytes, from 2015-09-24 17:25:31) -- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2015-05-20 20:03:07) -- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 32901 bytes, from 2015-05-20 20:03:14) -- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 10755 bytes, from 2015-09-14 20:46:55) -- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 14968 bytes, from 2015-05-20 20:12:27) -- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 67771 bytes, from 2015-09-14 20:46:55) -- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 63970 bytes, from 2015-09-14 20:50:12) -- /home/robclark/src/freedreno/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2015-09-24 17:30:00) +- ./adreno.xml ( 431 bytes, from 2016-10-24 21:12:27) +- ./freedreno_copyright.xml ( 1572 bytes, from 2016-10-24 21:12:27) +- ./adreno/a2xx.xml ( 32901 bytes, from 2016-10-24 21:12:27) +- ./adreno/adreno_common.xml ( 12025 bytes, from 2016-10-24 21:12:27) +- ./adreno/adreno_pm4.xml ( 19684 bytes, from 2016-10-24 21:12:27) +- ./adreno/a3xx.xml ( 83840 bytes, from 2016-10-24 21:12:27) +- ./adreno/a4xx.xml ( 110708 bytes, from 2016-10-24 21:12:27) +- ./adreno/a5xx.xml ( 81207 bytes, from 2016-10-26 19:36:59) +- ./adreno/ocmem.xml ( 1773 bytes, from 2016-10-24 21:12:27) -Copyright (C) 2013-2015 by the following authors: +Copyright (C) 2013-2016 by the following authors: - Rob Clark (robclark) +- Ilia Mirkin (imirkin) Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the @@ -119,6 +121,25 @@ RB_COPY_DEPTH_STENCIL = 5, }; +enum a3xx_rop_code { + ROP_CLEAR = 0, + ROP_NOR = 1, + ROP_AND_INVERTED = 2, + ROP_COPY_INVERTED = 3, + ROP_AND_REVERSE = 4, + ROP_INVERT = 5, + ROP_XOR = 6, + ROP_NAND = 7, + ROP_AND = 8, + ROP_EQUIV = 9, + ROP_NOOP = 10, + ROP_OR_INVERTED = 11, + ROP_COPY = 12, + ROP_OR_REVERSE = 13, + ROP_OR = 14, + ROP_SET = 15, +}; + enum a3xx_render_mode { RB_RENDERING_PASS = 0, RB_TILING_PASS = 1, @@ -154,6 +175,14 @@ XYZW = 3, }; +enum a3xx_rb_blend_opcode { + BLEND_DST_PLUS_SRC = 0, + BLEND_SRC_MINUS_DST = 1, + BLEND_DST_MINUS_SRC = 2, + BLEND_MIN_DST_SRC = 3, + BLEND_MAX_DST_SRC = 4, +}; + #define REG_AXXX_CP_RB_BASE 0x000001c0 #define REG_AXXX_CP_RB_CNTL 0x000001c1 diff -ruw linux-4.4.115/drivers/gpu/drm/msm/adreno/adreno_device.c linux-4.4.115-fbx/drivers/gpu/drm/msm/adreno/adreno_device.c --- linux-4.4.115/drivers/gpu/drm/msm/adreno/adreno_device.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/gpu/drm/msm/adreno/adreno_device.c 2019-01-22 16:16:23.487246262 +0100 @@ -19,10 +19,6 @@ #include "adreno_gpu.h" -#if defined(DOWNSTREAM_CONFIG_MSM_BUS_SCALING) && !defined(CONFIG_OF) -# include -#endif - #define ANY_ID 0xff bool hang_debug = false; @@ -31,6 +27,7 @@ struct msm_gpu *a3xx_gpu_init(struct drm_device *dev); struct msm_gpu *a4xx_gpu_init(struct drm_device *dev); +struct msm_gpu *a5xx_gpu_init(struct drm_device *dev); static const struct adreno_info gpulist[] = { { @@ -73,6 +70,30 @@ .pfpfw = "a420_pfp.fw", .gmem = (SZ_1M + SZ_512K), .init = a4xx_gpu_init, + }, { + .rev = ADRENO_REV(4, 3, 0, ANY_ID), + .revn = 430, + .name = "A430", + .pm4fw = "a420_pm4.fw", + .pfpfw = "a420_pfp.fw", + .gmem = (SZ_1M + SZ_512K), + .init = a4xx_gpu_init, + }, { + .rev = ADRENO_REV(5, 3, 0, ANY_ID), + .revn = 530, + .name = "A530", + .pm4fw = "a530_pm4.fw", + .pfpfw = "a530_pfp.fw", + .gmem = SZ_1M, + .init = a5xx_gpu_init, + }, { + .rev = ADRENO_REV(5, 4, 0, ANY_ID), + .revn = 540, + .name = "A540", + .pm4fw = "a530_pm4.fw", + .pfpfw = "a530_pfp.fw", + .gmem = SZ_1M, + .init = a5xx_gpu_init, }, }; @@ -82,6 +103,8 @@ MODULE_FIRMWARE("a330_pfp.fw"); MODULE_FIRMWARE("a420_pm4.fw"); MODULE_FIRMWARE("a420_pfp.fw"); +MODULE_FIRMWARE("a530_fm4.fw"); +MODULE_FIRMWARE("a530_pfp.fw"); static inline bool _rev_match(uint8_t entry, uint8_t id) { @@ -141,17 +164,17 @@ if (gpu) { int ret; - mutex_lock(&dev->struct_mutex); - gpu->funcs->pm_resume(gpu); - mutex_unlock(&dev->struct_mutex); - ret = gpu->funcs->hw_init(gpu); + + pm_runtime_get_sync(&pdev->dev); + ret = msm_gpu_hw_init(gpu); + pm_runtime_put_sync_autosuspend(&pdev->dev); if (ret) { dev_err(dev->dev, "gpu hw init failed: %d\n", ret); + mutex_lock(&dev->struct_mutex); + gpu->funcs->pm_suspend(gpu); + mutex_unlock(&dev->struct_mutex); gpu->funcs->destroy(gpu); gpu = NULL; - } else { - /* give inactive pm a chance to kick in: */ - msm_gpu_retire(gpu); } } @@ -168,12 +191,16 @@ static int adreno_bind(struct device *dev, struct device *master, void *data) { static struct adreno_platform_config config = {}; -#ifdef CONFIG_OF - struct device_node *child, *node = dev->of_node; - u32 val; + uint32_t val = 0; int ret; - ret = of_property_read_u32(node, "qcom,chipid", &val); + /* + * Read the chip ID from the device tree at bind time - we use this + * information to load the correct functions. All the rest of the + * (extensive) device tree probing should happen in the GPU specific + * code + */ + ret = of_property_read_u32(dev->of_node, "qcom,chipid", &val); if (ret) { dev_err(dev, "could not find chipid: %d\n", ret); return ret; @@ -182,76 +209,6 @@ config.rev = ADRENO_REV((val >> 24) & 0xff, (val >> 16) & 0xff, (val >> 8) & 0xff, val & 0xff); - /* find clock rates: */ - config.fast_rate = 0; - config.slow_rate = ~0; - for_each_child_of_node(node, child) { - if (of_device_is_compatible(child, "qcom,gpu-pwrlevels")) { - struct device_node *pwrlvl; - for_each_child_of_node(child, pwrlvl) { - ret = of_property_read_u32(pwrlvl, "qcom,gpu-freq", &val); - if (ret) { - dev_err(dev, "could not find gpu-freq: %d\n", ret); - return ret; - } - config.fast_rate = max(config.fast_rate, val); - config.slow_rate = min(config.slow_rate, val); - } - } - } - - if (!config.fast_rate) { - dev_err(dev, "could not find clk rates\n"); - return -ENXIO; - } - -#else - struct kgsl_device_platform_data *pdata = dev->platform_data; - uint32_t version = socinfo_get_version(); - if (cpu_is_apq8064ab()) { - config.fast_rate = 450000000; - config.slow_rate = 27000000; - config.bus_freq = 4; - config.rev = ADRENO_REV(3, 2, 1, 0); - } else if (cpu_is_apq8064()) { - config.fast_rate = 400000000; - config.slow_rate = 27000000; - config.bus_freq = 4; - - if (SOCINFO_VERSION_MAJOR(version) == 2) - config.rev = ADRENO_REV(3, 2, 0, 2); - else if ((SOCINFO_VERSION_MAJOR(version) == 1) && - (SOCINFO_VERSION_MINOR(version) == 1)) - config.rev = ADRENO_REV(3, 2, 0, 1); - else - config.rev = ADRENO_REV(3, 2, 0, 0); - - } else if (cpu_is_msm8960ab()) { - config.fast_rate = 400000000; - config.slow_rate = 320000000; - config.bus_freq = 4; - - if (SOCINFO_VERSION_MINOR(version) == 0) - config.rev = ADRENO_REV(3, 2, 1, 0); - else - config.rev = ADRENO_REV(3, 2, 1, 1); - - } else if (cpu_is_msm8930()) { - config.fast_rate = 400000000; - config.slow_rate = 27000000; - config.bus_freq = 3; - - if ((SOCINFO_VERSION_MAJOR(version) == 1) && - (SOCINFO_VERSION_MINOR(version) == 2)) - config.rev = ADRENO_REV(3, 0, 5, 2); - else - config.rev = ADRENO_REV(3, 0, 5, 0); - - } -# ifdef DOWNSTREAM_CONFIG_MSM_BUS_SCALING - config.bus_scale_table = pdata->bus_scale_table; -# endif -#endif dev->platform_data = &config; set_gpu_pdev(dev_get_drvdata(master), to_platform_device(dev)); return 0; @@ -286,12 +243,35 @@ {} }; +#ifdef CONFIG_PM +static int adreno_resume(struct device *dev) +{ + struct platform_device *pdev = to_platform_device(dev); + struct msm_gpu *gpu = platform_get_drvdata(pdev); + + return gpu->funcs->pm_resume(gpu); +} + +static int adreno_suspend(struct device *dev) +{ + struct platform_device *pdev = to_platform_device(dev); + struct msm_gpu *gpu = platform_get_drvdata(pdev); + + return gpu->funcs->pm_suspend(gpu); +} +#endif + +static const struct dev_pm_ops adreno_pm_ops = { + SET_RUNTIME_PM_OPS(adreno_suspend, adreno_resume, NULL) +}; + static struct platform_driver adreno_driver = { .probe = adreno_probe, .remove = adreno_remove, .driver = { .name = "adreno", .of_match_table = dt_match, + .pm = &adreno_pm_ops, }, }; diff -ruw linux-4.4.115/drivers/gpu/drm/msm/adreno/adreno_gpu.c linux-4.4.115-fbx/drivers/gpu/drm/msm/adreno/adreno_gpu.c --- linux-4.4.115/drivers/gpu/drm/msm/adreno/adreno_gpu.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/gpu/drm/msm/adreno/adreno_gpu.c 2019-01-22 16:16:23.487246262 +0100 @@ -2,7 +2,7 @@ * Copyright (C) 2013 Red Hat * Author: Rob Clark * - * Copyright (c) 2014 The Linux Foundation. All rights reserved. + * Copyright (c) 2014,2016-2018 The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License version 2 as published by @@ -17,12 +17,12 @@ * this program. If not, see . */ +#include #include "adreno_gpu.h" +#include "msm_snapshot.h" #include "msm_gem.h" #include "msm_mmu.h" -#define RB_SIZE SZ_32K -#define RB_BLKSIZE 16 int adreno_get_param(struct msm_gpu *gpu, uint32_t param, uint64_t *value) { @@ -35,123 +35,167 @@ case MSM_PARAM_GMEM_SIZE: *value = adreno_gpu->gmem; return 0; + case MSM_PARAM_GMEM_BASE: + *value = 0x100000; + return 0; case MSM_PARAM_CHIP_ID: *value = adreno_gpu->rev.patchid | (adreno_gpu->rev.minor << 8) | (adreno_gpu->rev.major << 16) | (adreno_gpu->rev.core << 24); return 0; + case MSM_PARAM_MAX_FREQ: + *value = gpu->gpufreq[0]; + return 0; + case MSM_PARAM_TIMESTAMP: + if (adreno_gpu->funcs->get_timestamp) { + int ret; + + pm_runtime_get_sync(&gpu->pdev->dev); + ret = adreno_gpu->funcs->get_timestamp(gpu, value); + pm_runtime_put_autosuspend(&gpu->pdev->dev); + + return ret; + } + return -EINVAL; + case MSM_PARAM_NR_RINGS: + *value = gpu->nr_rings; + return 0; + case MSM_PARAM_GPU_HANG_TIMEOUT: + *value = DRM_MSM_HANGCHECK_PERIOD; + return 0; default: DBG("%s: invalid param: %u", gpu->name, param); return -EINVAL; } } -#define rbmemptr(adreno_gpu, member) \ - ((adreno_gpu)->memptrs_iova + offsetof(struct adreno_rbmemptrs, member)) - int adreno_hw_init(struct msm_gpu *gpu) { struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); - int ret; + int i; DBG("%s", gpu->name); - ret = msm_gem_get_iova(gpu->rb->bo, gpu->id, &gpu->rb_iova); + for (i = 0; i < gpu->nr_rings; i++) { + struct msm_ringbuffer *ring = gpu->rb[i]; + + int ret = msm_gem_get_iova(ring->bo, gpu->aspace, + &ring->iova); if (ret) { - gpu->rb_iova = 0; - dev_err(gpu->dev->dev, "could not map ringbuffer: %d\n", ret); + ring->iova = 0; + dev_err(gpu->dev->dev, + "could not map ringbuffer %d: %d\n", i, ret); return ret; } - /* Setup REG_CP_RB_CNTL: */ - adreno_gpu_write(adreno_gpu, REG_ADRENO_CP_RB_CNTL, - /* size is log2(quad-words): */ - AXXX_CP_RB_CNTL_BUFSZ(ilog2(gpu->rb->size / 8)) | - AXXX_CP_RB_CNTL_BLKSZ(ilog2(RB_BLKSIZE / 8))); + /* reset ringbuffer(s): */ + /* No need for a lock here, nobody else is peeking in */ + ring->cur = ring->start; + ring->next = ring->start; + + /* reset completed fence seqno, discard anything pending: */ + ring->memptrs->fence = adreno_submitted_fence(gpu, ring); + ring->memptrs->rptr = 0; + } - /* Setup ringbuffer address: */ - adreno_gpu_write(adreno_gpu, REG_ADRENO_CP_RB_BASE, gpu->rb_iova); - adreno_gpu_write(adreno_gpu, REG_ADRENO_CP_RB_RPTR_ADDR, - rbmemptr(adreno_gpu, rptr)); + /* + * Setup REG_CP_RB_CNTL. The same value is used across targets (with + * the excpetion of A430 that disables the RPTR shadow) - the cacluation + * for the ringbuffer size and block size is moved to msm_gpu.h for the + * pre-processor to deal with and the A430 variant is ORed in here + */ + adreno_gpu_write(adreno_gpu, REG_ADRENO_CP_RB_CNTL, + MSM_GPU_RB_CNTL_DEFAULT | + (adreno_is_a430(adreno_gpu) ? AXXX_CP_RB_CNTL_NO_UPDATE : 0)); - /* Setup scratch/timestamp: */ - adreno_gpu_write(adreno_gpu, REG_ADRENO_SCRATCH_ADDR, - rbmemptr(adreno_gpu, fence)); + /* Setup ringbuffer address - use ringbuffer[0] for GPU init */ + adreno_gpu_write64(adreno_gpu, REG_ADRENO_CP_RB_BASE, + REG_ADRENO_CP_RB_BASE_HI, gpu->rb[0]->iova); - adreno_gpu_write(adreno_gpu, REG_ADRENO_SCRATCH_UMSK, 0x1); + adreno_gpu_write64(adreno_gpu, REG_ADRENO_CP_RB_RPTR_ADDR, + REG_ADRENO_CP_RB_RPTR_ADDR_HI, rbmemptr(gpu->rb[0], rptr)); return 0; } -static uint32_t get_wptr(struct msm_ringbuffer *ring) +/* Use this helper to read rptr, since a430 doesn't update rptr in memory */ +static uint32_t get_rptr(struct adreno_gpu *adreno_gpu, + struct msm_ringbuffer *ring) { - return ring->cur - ring->start; + if (adreno_is_a430(adreno_gpu)) { + /* + * If index is anything but 0 this will probably break horribly, + * but I think that we have enough infrastructure in place to + * ensure that it won't be. If not then this is why your + * a430 stopped working. + */ + return ring->memptrs->rptr = + adreno_gpu_read(adreno_gpu, REG_ADRENO_CP_RB_RPTR); + } + + return ring->memptrs->rptr; } -uint32_t adreno_last_fence(struct msm_gpu *gpu) +struct msm_ringbuffer *adreno_active_ring(struct msm_gpu *gpu) { - struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); - return adreno_gpu->memptrs->fence; + return gpu->rb[0]; +} + +uint32_t adreno_submitted_fence(struct msm_gpu *gpu, + struct msm_ringbuffer *ring) +{ + if (!ring) + return 0; + + return ring->submitted_fence; } void adreno_recover(struct msm_gpu *gpu) { - struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); struct drm_device *dev = gpu->dev; int ret; - gpu->funcs->pm_suspend(gpu); - - /* reset ringbuffer: */ - gpu->rb->cur = gpu->rb->start; + /* + * XXX pm-runtime?? we *need* the device to be off after this + * so maybe continuing to call ->pm_suspend/resume() is better? + */ - /* reset completed fence seqno, just discard anything pending: */ - adreno_gpu->memptrs->fence = gpu->submitted_fence; - adreno_gpu->memptrs->rptr = 0; - adreno_gpu->memptrs->wptr = 0; + gpu->funcs->pm_suspend(gpu); gpu->funcs->pm_resume(gpu); - ret = gpu->funcs->hw_init(gpu); + + ret = msm_gpu_hw_init(gpu); if (ret) { dev_err(dev->dev, "gpu hw init failed: %d\n", ret); /* hmm, oh well? */ } } -int adreno_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit, - struct msm_file_private *ctx) +void adreno_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit) { struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); - struct msm_drm_private *priv = gpu->dev->dev_private; - struct msm_ringbuffer *ring = gpu->rb; - unsigned i, ibs = 0; + struct msm_ringbuffer *ring = gpu->rb[submit->ring]; + unsigned i; for (i = 0; i < submit->nr_cmds; i++) { switch (submit->cmd[i].type) { case MSM_SUBMIT_CMD_IB_TARGET_BUF: /* ignore IB-targets */ break; + case MSM_SUBMIT_CMD_PROFILE_BUF: case MSM_SUBMIT_CMD_CTX_RESTORE_BUF: - /* ignore if there has not been a ctx switch: */ - if (priv->lastctx == ctx) break; case MSM_SUBMIT_CMD_BUF: - OUT_PKT3(ring, CP_INDIRECT_BUFFER_PFD, 2); - OUT_RING(ring, submit->cmd[i].iova); + OUT_PKT3(ring, adreno_is_a430(adreno_gpu) ? + CP_INDIRECT_BUFFER_PFE : CP_INDIRECT_BUFFER_PFD, 2); + OUT_RING(ring, lower_32_bits(submit->cmd[i].iova)); OUT_RING(ring, submit->cmd[i].size); - ibs++; + OUT_PKT2(ring); break; } } - /* on a320, at least, we seem to need to pad things out to an - * even number of qwords to avoid issue w/ CP hanging on wrap- - * around: - */ - if (ibs % 2) - OUT_PKT2(ring); - OUT_PKT0(ring, REG_AXXX_CP_SCRATCH_REG2, 1); OUT_RING(ring, submit->fence); @@ -169,7 +213,7 @@ OUT_PKT3(ring, CP_EVENT_WRITE, 3); OUT_RING(ring, CACHE_FLUSH_TS); - OUT_RING(ring, rbmemptr(adreno_gpu, fence)); + OUT_RING(ring, rbmemptr(ring, fence)); OUT_RING(ring, submit->fence); /* we could maybe be clever and only CP_COND_EXEC the interrupt: */ @@ -196,22 +240,23 @@ } #endif - gpu->funcs->flush(gpu); - - return 0; + gpu->funcs->flush(gpu, ring); } -void adreno_flush(struct msm_gpu *gpu) +void adreno_flush(struct msm_gpu *gpu, struct msm_ringbuffer *ring) { struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); uint32_t wptr; + /* Copy the shadow to the actual register */ + ring->cur = ring->next; + /* - * Mask wptr value that we calculate to fit in the HW range. This is + * Mask the wptr value that we calculate to fit in the HW range. This is * to account for the possibility that the last command fit exactly into * the ringbuffer and rb->next hasn't wrapped to zero yet */ - wptr = get_wptr(gpu->rb) & ((gpu->rb->size / 4) - 1); + wptr = get_wptr(ring); /* ensure writes to ringbuffer have hit system memory: */ mb(); @@ -219,22 +264,27 @@ adreno_gpu_write(adreno_gpu, REG_ADRENO_CP_RB_WPTR, wptr); } -void adreno_idle(struct msm_gpu *gpu) +bool adreno_idle(struct msm_gpu *gpu, struct msm_ringbuffer *ring) { struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); - uint32_t wptr = get_wptr(gpu->rb); + uint32_t wptr = get_wptr(ring); /* wait for CP to drain ringbuffer: */ - if (spin_until(adreno_gpu->memptrs->rptr == wptr)) - DRM_ERROR("%s: timeout waiting to drain ringbuffer!\n", gpu->name); + if (!spin_until(get_rptr(adreno_gpu, ring) == wptr)) + return true; /* TODO maybe we need to reset GPU here to recover from hang? */ + DRM_ERROR("%s: timeout waiting to drain ringbuffer %d rptr/wptr = %X/%X\n", + gpu->name, ring->id, get_rptr(adreno_gpu, ring), wptr); + + return false; } #ifdef CONFIG_DEBUG_FS void adreno_show(struct msm_gpu *gpu, struct seq_file *m) { struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); + struct msm_ringbuffer *ring; int i; seq_printf(m, "revision: %d (%d.%d.%d.%d)\n", @@ -242,13 +292,18 @@ adreno_gpu->rev.major, adreno_gpu->rev.minor, adreno_gpu->rev.patchid); - seq_printf(m, "fence: %d/%d\n", adreno_gpu->memptrs->fence, - gpu->submitted_fence); - seq_printf(m, "rptr: %d\n", adreno_gpu->memptrs->rptr); - seq_printf(m, "wptr: %d\n", adreno_gpu->memptrs->wptr); - seq_printf(m, "rb wptr: %d\n", get_wptr(gpu->rb)); - - gpu->funcs->pm_resume(gpu); + FOR_EACH_RING(gpu, ring, i) { + if (!ring) + continue; + + seq_printf(m, "rb %d: fence: %d/%d\n", i, + ring->memptrs->fence, + adreno_submitted_fence(gpu, ring)); + + seq_printf(m, " rptr: %d\n", + get_rptr(adreno_gpu, ring)); + seq_printf(m, "rb wptr: %d\n", get_wptr(ring)); + } /* dump these out in a form that can be parsed by demsm: */ seq_printf(m, "IO:region %s 00000000 00020000\n", gpu->name); @@ -262,8 +317,6 @@ seq_printf(m, "IO:R %08x %08x\n", addr<<2, val); } } - - gpu->funcs->pm_suspend(gpu); } #endif @@ -275,22 +328,29 @@ */ void adreno_dump_info(struct msm_gpu *gpu) { + struct drm_device *dev = gpu->dev; struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); + struct msm_ringbuffer *ring; int i; - printk("revision: %d (%d.%d.%d.%d)\n", + dev_err(dev->dev, "revision: %d (%d.%d.%d.%d)\n", adreno_gpu->info->revn, adreno_gpu->rev.core, adreno_gpu->rev.major, adreno_gpu->rev.minor, adreno_gpu->rev.patchid); - printk("fence: %d/%d\n", adreno_gpu->memptrs->fence, - gpu->submitted_fence); - printk("rptr: %d\n", adreno_gpu->memptrs->rptr); - printk("wptr: %d\n", adreno_gpu->memptrs->wptr); - printk("rb wptr: %d\n", get_wptr(gpu->rb)); + FOR_EACH_RING(gpu, ring, i) { + if (!ring) + continue; + + dev_err(dev->dev, " ring %d: fence %d/%d rptr/wptr %x/%x\n", i, + ring->memptrs->fence, + adreno_submitted_fence(gpu, ring), + get_rptr(adreno_gpu, ring), + get_wptr(ring)); + } for (i = 0; i < 8; i++) { - printk("CP_SCRATCH_REG%d: %u\n", i, + pr_err("CP_SCRATCH_REG%d: %u\n", i, gpu_read(gpu, REG_AXXX_CP_SCRATCH_REG0 + i)); } } @@ -315,32 +375,135 @@ } } -static uint32_t ring_freewords(struct msm_gpu *gpu) +static uint32_t ring_freewords(struct msm_ringbuffer *ring) { - struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); - uint32_t size = gpu->rb->size / 4; - uint32_t wptr = get_wptr(gpu->rb); - uint32_t rptr = adreno_gpu->memptrs->rptr; + struct adreno_gpu *adreno_gpu = to_adreno_gpu(ring->gpu); + uint32_t size = MSM_GPU_RINGBUFFER_SZ >> 2; + /* Use ring->next to calculate free size */ + uint32_t wptr = ring->next - ring->start; + uint32_t rptr = get_rptr(adreno_gpu, ring); return (rptr + (size - 1) - wptr) % size; } -void adreno_wait_ring(struct msm_gpu *gpu, uint32_t ndwords) +void adreno_wait_ring(struct msm_ringbuffer *ring, uint32_t ndwords) { - if (spin_until(ring_freewords(gpu) >= ndwords)) - DRM_ERROR("%s: timeout waiting for ringbuffer space\n", gpu->name); + if (spin_until(ring_freewords(ring) >= ndwords)) + DRM_ERROR("%s: timeout waiting for space in ringubffer %d\n", + ring->gpu->name, ring->id); } -static const char *iommu_ports[] = { - "gfx3d_user", "gfx3d_priv", - "gfx3d1_user", "gfx3d1_priv", +/* Read the set of powerlevels */ +static int _adreno_get_pwrlevels(struct msm_gpu *gpu, struct device_node *node) +{ + struct device_node *child; + + for_each_child_of_node(node, child) { + unsigned int index; + + if (of_property_read_u32(child, "reg", &index)) + return -EINVAL; + + if (index >= ARRAY_SIZE(gpu->gpufreq)) + continue; + + gpu->nr_pwrlevels = max(gpu->nr_pwrlevels, index + 1); + + of_property_read_u32(child, "qcom,gpu-freq", + &gpu->gpufreq[index]); + of_property_read_u32(child, "qcom,bus-freq", + &gpu->busfreq[index]); + } + + DBG("fast_rate=%u, slow_rate=%u, bus_freq=%u", + gpu->gpufreq[0], + gpu->gpufreq[gpu->nr_pwrlevels - 1], + gpu->busfreq[0]); + + return 0; +} + +/* + * Escape valve for targets that don't define the binning nodes. Get the + * first powerlevel node and parse it + */ +static int adreno_get_legacy_pwrlevels(struct msm_gpu *gpu, + struct device_node *parent) +{ + struct device_node *child; + + child = of_find_node_by_name(parent, "qcom,gpu-pwrlevels"); + if (child) + return _adreno_get_pwrlevels(gpu, child); + + dev_err(gpu->dev->dev, "Unable to parse any powerlevels\n"); + return -EINVAL; +} + +/* Get the powerlevels for the target */ +static int adreno_get_pwrlevels(struct msm_gpu *gpu, struct device_node *parent) +{ + struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); + struct device_node *node, *child; + + /* See if the target has defined a number of power bins */ + node = of_find_node_by_name(parent, "qcom,gpu-pwrlevel-bins"); + if (!node) { + /* If not look for the qcom,gpu-pwrlevels node */ + return adreno_get_legacy_pwrlevels(gpu, parent); + } + + for_each_child_of_node(node, child) { + unsigned int bin; + + if (of_property_read_u32(child, "qcom,speed-bin", &bin)) + continue; + + /* + * If the bin matches the bin specified by the fuses, then we + * have a winner - parse it + */ + if (adreno_gpu->speed_bin == bin) + return _adreno_get_pwrlevels(gpu, child); + } + + return -ENODEV; +} + +static const struct { + const char *str; + uint32_t flag; +} quirks[] = { + { "qcom,gpu-quirk-two-pass-use-wfi", ADRENO_QUIRK_TWO_PASS_USE_WFI }, + { "qcom,gpu-quirk-fault-detect-mask", ADRENO_QUIRK_FAULT_DETECT_MASK }, }; +/* Parse the statistics from the device tree */ +static int adreno_of_parse(struct platform_device *pdev, struct msm_gpu *gpu) +{ + struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); + struct device_node *node = pdev->dev.of_node; + int i, ret; + + /* Probe the powerlevels */ + ret = adreno_get_pwrlevels(gpu, node); + if (ret) + return ret; + + /* Check to see if any quirks were specified in the device tree */ + for (i = 0; i < ARRAY_SIZE(quirks); i++) + if (of_property_read_bool(node, quirks[i].str)) + adreno_gpu->quirks |= quirks[i].flag; + + return 0; +} + int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev, - struct adreno_gpu *adreno_gpu, const struct adreno_gpu_funcs *funcs) + struct adreno_gpu *adreno_gpu, + const struct adreno_gpu_funcs *funcs, + struct msm_gpu_config *gpu_config) { struct adreno_platform_config *config = pdev->dev.platform_data; struct msm_gpu *gpu = &adreno_gpu->base; - struct msm_mmu *mmu; int ret; adreno_gpu->funcs = funcs; @@ -349,22 +512,18 @@ adreno_gpu->revn = adreno_gpu->info->revn; adreno_gpu->rev = config->rev; - gpu->fast_rate = config->fast_rate; - gpu->slow_rate = config->slow_rate; - gpu->bus_freq = config->bus_freq; -#ifdef DOWNSTREAM_CONFIG_MSM_BUS_SCALING - gpu->bus_scale_table = config->bus_scale_table; -#endif - - DBG("fast_rate=%u, slow_rate=%u, bus_freq=%u", - gpu->fast_rate, gpu->slow_rate, gpu->bus_freq); + /* Get the rest of the target configuration from the device tree */ + adreno_of_parse(pdev, gpu); ret = msm_gpu_init(drm, pdev, &adreno_gpu->base, &funcs->base, - adreno_gpu->info->name, "kgsl_3d0_reg_memory", "kgsl_3d0_irq", - RB_SIZE); + adreno_gpu->info->name, gpu_config); if (ret) return ret; + pm_runtime_set_autosuspend_delay(&pdev->dev, DRM_MSM_INACTIVE_PERIOD); + pm_runtime_use_autosuspend(&pdev->dev); + pm_runtime_enable(&pdev->dev); + ret = request_firmware(&adreno_gpu->pm4, adreno_gpu->info->pm4fw, drm->dev); if (ret) { dev_err(drm->dev, "failed to load %s PM4 firmware: %d\n", @@ -373,55 +532,150 @@ } ret = request_firmware(&adreno_gpu->pfp, adreno_gpu->info->pfpfw, drm->dev); - if (ret) { + if (ret) dev_err(drm->dev, "failed to load %s PFP firmware: %d\n", adreno_gpu->info->pfpfw, ret); + return ret; } - mmu = gpu->mmu; - if (mmu) { - ret = mmu->funcs->attach(mmu, iommu_ports, - ARRAY_SIZE(iommu_ports)); - if (ret) - return ret; +void adreno_gpu_cleanup(struct adreno_gpu *adreno_gpu) +{ + struct msm_gpu *gpu = &adreno_gpu->base; + struct drm_device *dev = gpu->dev; + struct msm_drm_private *priv = dev->dev_private; + struct platform_device *pdev = priv->gpu_pdev; + + release_firmware(adreno_gpu->pm4); + release_firmware(adreno_gpu->pfp); + + pm_runtime_disable(&pdev->dev); + msm_gpu_cleanup(gpu); } - mutex_lock(&drm->struct_mutex); - adreno_gpu->memptrs_bo = msm_gem_new(drm, sizeof(*adreno_gpu->memptrs), - MSM_BO_UNCACHED); - mutex_unlock(&drm->struct_mutex); - if (IS_ERR(adreno_gpu->memptrs_bo)) { - ret = PTR_ERR(adreno_gpu->memptrs_bo); - adreno_gpu->memptrs_bo = NULL; - dev_err(drm->dev, "could not allocate memptrs: %d\n", ret); - return ret; +static void adreno_snapshot_os(struct msm_gpu *gpu, + struct msm_snapshot *snapshot) +{ + struct msm_snapshot_linux header; + + memset(&header, 0, sizeof(header)); + + header.osid = SNAPSHOT_OS_LINUX_V3; + strlcpy(header.release, utsname()->release, sizeof(header.release)); + strlcpy(header.version, utsname()->version, sizeof(header.version)); + + header.seconds = get_seconds(); + header.ctxtcount = 0; + + SNAPSHOT_HEADER(snapshot, header, SNAPSHOT_SECTION_OS, 0); } - adreno_gpu->memptrs = msm_gem_vaddr(adreno_gpu->memptrs_bo); - if (!adreno_gpu->memptrs) { - dev_err(drm->dev, "could not vmap memptrs\n"); - return -ENOMEM; +static void adreno_snapshot_ringbuffer(struct msm_gpu *gpu, + struct msm_snapshot *snapshot, struct msm_ringbuffer *ring) +{ + struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); + struct msm_snapshot_ringbuffer header; + unsigned int i, end = 0; + unsigned int *data = ring->start; + + memset(&header, 0, sizeof(header)); + + /* + * We only want to copy the active contents of each ring, so find the + * last valid entry in the ringbuffer + */ + for (i = 0; i < MSM_GPU_RINGBUFFER_SZ >> 2; i++) { + if (data[i]) + end = i; } - ret = msm_gem_get_iova(adreno_gpu->memptrs_bo, gpu->id, - &adreno_gpu->memptrs_iova); - if (ret) { - dev_err(drm->dev, "could not map memptrs: %d\n", ret); - return ret; + /* The dump always starts at 0 */ + header.start = 0; + header.end = end; + + /* This is the number of dwords being dumped */ + header.count = end + 1; + + /* This is the size of the actual ringbuffer */ + header.rbsize = MSM_GPU_RINGBUFFER_SZ >> 2; + + header.id = ring->id; + header.gpuaddr = ring->iova; + header.rptr = get_rptr(adreno_gpu, ring); + header.wptr = get_wptr(ring); + header.timestamp_queued = adreno_submitted_fence(gpu, ring); + header.timestamp_retired = ring->memptrs->fence; + + /* Write the header even if the ringbuffer data is empty */ + if (!SNAPSHOT_HEADER(snapshot, header, SNAPSHOT_SECTION_RB_V2, + header.count)) + return; + + SNAPSHOT_MEMCPY(snapshot, ring->start, header.count * sizeof(u32)); +} + +static void adreno_snapshot_ringbuffers(struct msm_gpu *gpu, + struct msm_snapshot *snapshot) +{ + struct msm_ringbuffer *ring; + int i; + + /* Write a new section for each ringbuffer */ + FOR_EACH_RING(gpu, ring, i) + adreno_snapshot_ringbuffer(gpu, snapshot, ring); +} + +void adreno_snapshot(struct msm_gpu *gpu, struct msm_snapshot *snapshot) +{ + adreno_snapshot_os(gpu, snapshot); + adreno_snapshot_ringbuffers(gpu, snapshot); +} + +/* Return the group struct associated with the counter id */ + +static struct adreno_counter_group *get_counter_group(struct msm_gpu *gpu, + u32 groupid) +{ + struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); + + if (!adreno_gpu->counter_groups) + return ERR_PTR(-ENODEV); + + if (groupid >= adreno_gpu->nr_counter_groups) + return ERR_PTR(-ENODEV); + + return (struct adreno_counter_group *) + adreno_gpu->counter_groups[groupid]; } +int adreno_get_counter(struct msm_gpu *gpu, u32 groupid, u32 countable, + u32 *lo, u32 *hi) +{ + struct adreno_counter_group *group = + get_counter_group(gpu, groupid); + + if (!IS_ERR_OR_NULL(group) && group->funcs.get) + return group->funcs.get(gpu, group, countable, lo, hi); + + return -ENODEV; +} + +u64 adreno_read_counter(struct msm_gpu *gpu, u32 groupid, int counterid) +{ + struct adreno_counter_group *group = + get_counter_group(gpu, groupid); + + if (!IS_ERR_OR_NULL(group) && group->funcs.read) + return group->funcs.read(gpu, group, counterid); + return 0; } -void adreno_gpu_cleanup(struct adreno_gpu *gpu) +void adreno_put_counter(struct msm_gpu *gpu, u32 groupid, int counterid) { - if (gpu->memptrs_bo) { - if (gpu->memptrs_iova) - msm_gem_put_iova(gpu->memptrs_bo, gpu->base.id); - drm_gem_object_unreference_unlocked(gpu->memptrs_bo); - } - release_firmware(gpu->pm4); - release_firmware(gpu->pfp); - msm_gpu_cleanup(&gpu->base); + struct adreno_counter_group *group = + get_counter_group(gpu, groupid); + + if (!IS_ERR_OR_NULL(group) && group->funcs.put) + group->funcs.put(gpu, group, counterid); } diff -ruw linux-4.4.115/drivers/gpu/drm/msm/adreno/adreno_gpu.h linux-4.4.115-fbx/drivers/gpu/drm/msm/adreno/adreno_gpu.h --- linux-4.4.115/drivers/gpu/drm/msm/adreno/adreno_gpu.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/gpu/drm/msm/adreno/adreno_gpu.h 2019-01-22 16:16:23.487246262 +0100 @@ -2,7 +2,7 @@ * Copyright (C) 2013 Red Hat * Author: Rob Clark * - * Copyright (c) 2014 The Linux Foundation. All rights reserved. + * Copyright (c) 2014,2016-2017 The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License version 2 as published by @@ -24,10 +24,17 @@ #include "msm_gpu.h" +/* arrg, somehow fb.h is getting pulled in: */ +#undef ROP_COPY +#undef ROP_XOR + #include "adreno_common.xml.h" #include "adreno_pm4.xml.h" #define REG_ADRENO_DEFINE(_offset, _reg) [_offset] = (_reg) + 1 +#define REG_SKIP ~0 +#define REG_ADRENO_SKIP(_offset) [_offset] = REG_SKIP + /** * adreno_regs: List of registers that are used in across all * 3D devices. Each device type has different offset value for the same @@ -35,73 +42,21 @@ * and are indexed by the enumeration values defined in this enum */ enum adreno_regs { - REG_ADRENO_CP_DEBUG, - REG_ADRENO_CP_ME_RAM_WADDR, - REG_ADRENO_CP_ME_RAM_DATA, - REG_ADRENO_CP_PFP_UCODE_DATA, - REG_ADRENO_CP_PFP_UCODE_ADDR, - REG_ADRENO_CP_WFI_PEND_CTR, REG_ADRENO_CP_RB_BASE, + REG_ADRENO_CP_RB_BASE_HI, REG_ADRENO_CP_RB_RPTR_ADDR, + REG_ADRENO_CP_RB_RPTR_ADDR_HI, REG_ADRENO_CP_RB_RPTR, REG_ADRENO_CP_RB_WPTR, - REG_ADRENO_CP_PROTECT_CTRL, - REG_ADRENO_CP_ME_CNTL, REG_ADRENO_CP_RB_CNTL, - REG_ADRENO_CP_IB1_BASE, - REG_ADRENO_CP_IB1_BUFSZ, - REG_ADRENO_CP_IB2_BASE, - REG_ADRENO_CP_IB2_BUFSZ, - REG_ADRENO_CP_TIMESTAMP, - REG_ADRENO_CP_ME_RAM_RADDR, - REG_ADRENO_CP_ROQ_ADDR, - REG_ADRENO_CP_ROQ_DATA, - REG_ADRENO_CP_MERCIU_ADDR, - REG_ADRENO_CP_MERCIU_DATA, - REG_ADRENO_CP_MERCIU_DATA2, - REG_ADRENO_CP_MEQ_ADDR, - REG_ADRENO_CP_MEQ_DATA, - REG_ADRENO_CP_HW_FAULT, - REG_ADRENO_CP_PROTECT_STATUS, - REG_ADRENO_SCRATCH_ADDR, - REG_ADRENO_SCRATCH_UMSK, - REG_ADRENO_SCRATCH_REG2, - REG_ADRENO_RBBM_STATUS, - REG_ADRENO_RBBM_PERFCTR_CTL, - REG_ADRENO_RBBM_PERFCTR_LOAD_CMD0, - REG_ADRENO_RBBM_PERFCTR_LOAD_CMD1, - REG_ADRENO_RBBM_PERFCTR_LOAD_CMD2, - REG_ADRENO_RBBM_PERFCTR_PWR_1_LO, - REG_ADRENO_RBBM_INT_0_MASK, - REG_ADRENO_RBBM_INT_0_STATUS, - REG_ADRENO_RBBM_AHB_ERROR_STATUS, - REG_ADRENO_RBBM_PM_OVERRIDE2, - REG_ADRENO_RBBM_AHB_CMD, - REG_ADRENO_RBBM_INT_CLEAR_CMD, - REG_ADRENO_RBBM_SW_RESET_CMD, - REG_ADRENO_RBBM_CLOCK_CTL, - REG_ADRENO_RBBM_AHB_ME_SPLIT_STATUS, - REG_ADRENO_RBBM_AHB_PFP_SPLIT_STATUS, - REG_ADRENO_VPC_DEBUG_RAM_SEL, - REG_ADRENO_VPC_DEBUG_RAM_READ, - REG_ADRENO_VSC_SIZE_ADDRESS, - REG_ADRENO_VFD_CONTROL_0, - REG_ADRENO_VFD_INDEX_MAX, - REG_ADRENO_SP_VS_PVT_MEM_ADDR_REG, - REG_ADRENO_SP_FS_PVT_MEM_ADDR_REG, - REG_ADRENO_SP_VS_OBJ_START_REG, - REG_ADRENO_SP_FS_OBJ_START_REG, - REG_ADRENO_PA_SC_AA_CONFIG, - REG_ADRENO_SQ_GPR_MANAGEMENT, - REG_ADRENO_SQ_INST_STORE_MANAGMENT, - REG_ADRENO_TP0_CHICKEN, - REG_ADRENO_RBBM_RBBM_CTL, - REG_ADRENO_UCHE_INVALIDATE0, - REG_ADRENO_RBBM_PERFCTR_LOAD_VALUE_LO, - REG_ADRENO_RBBM_PERFCTR_LOAD_VALUE_HI, REG_ADRENO_REGISTER_MAX, }; +enum adreno_quirks { + ADRENO_QUIRK_TWO_PASS_USE_WFI = 1, + ADRENO_QUIRK_FAULT_DETECT_MASK = 2, +}; + struct adreno_rev { uint8_t core; uint8_t major; @@ -114,6 +69,7 @@ struct adreno_gpu_funcs { struct msm_gpu_funcs base; + int (*get_timestamp)(struct msm_gpu *gpu, uint64_t *value); }; struct adreno_info { @@ -127,10 +83,34 @@ const struct adreno_info *adreno_info(struct adreno_rev rev); -struct adreno_rbmemptrs { - volatile uint32_t rptr; - volatile uint32_t wptr; - volatile uint32_t fence; +struct adreno_counter { + u32 lo; + u32 hi; + u32 sel; + int load_bit; + u32 countable; + u32 refcount; + u64 value; +}; + +struct adreno_counter_group { + struct adreno_counter *counters; + size_t nr_counters; + spinlock_t lock; + struct { + int (*get)(struct msm_gpu *, + struct adreno_counter_group *, u32, u32 *, u32 *); + void (*enable)(struct msm_gpu *, + struct adreno_counter_group *, int, bool); + u64 (*read)(struct msm_gpu *, + struct adreno_counter_group *, int); + void (*put)(struct msm_gpu *, + struct adreno_counter_group *, int); + void (*save)(struct msm_gpu *, + struct adreno_counter_group *); + void (*restore)(struct msm_gpu *, + struct adreno_counter_group *); + } funcs; }; struct adreno_gpu { @@ -147,29 +127,24 @@ /* firmware: */ const struct firmware *pm4, *pfp; - /* ringbuffer rptr/wptr: */ - // TODO should this be in msm_ringbuffer? I think it would be - // different for z180.. - struct adreno_rbmemptrs *memptrs; - struct drm_gem_object *memptrs_bo; - uint32_t memptrs_iova; - /* * Register offsets are different between some GPUs. * GPU specific offsets will be exported by GPU specific * code (a3xx_gpu.c) and stored in this common location. */ const unsigned int *reg_offsets; + + uint32_t quirks; + uint32_t speed_bin; + + const struct adreno_counter_group **counter_groups; + int nr_counter_groups; }; #define to_adreno_gpu(x) container_of(x, struct adreno_gpu, base) /* platform config data (ie. from DT, or pdata) */ struct adreno_platform_config { struct adreno_rev rev; - uint32_t fast_rate, slow_rate, bus_freq; -#ifdef DOWNSTREAM_CONFIG_MSM_BUS_SCALING - struct msm_bus_scale_pdata *bus_scale_table; -#endif }; #define ADRENO_IDLE_TIMEOUT msecs_to_jiffies(1000) @@ -186,6 +161,9 @@ __ret; \ }) +#define GPU_OF_NODE(_g) \ + (((struct msm_drm_private *) \ + ((_g)->dev->dev_private))->gpu_pdev->dev.of_node) static inline bool adreno_is_a3xx(struct adreno_gpu *gpu) { @@ -228,32 +206,55 @@ return gpu->revn == 420; } +static inline int adreno_is_a430(struct adreno_gpu *gpu) +{ + return gpu->revn == 430; +} + +static inline int adreno_is_a530(struct adreno_gpu *gpu) +{ + return gpu->revn == 530; +} + +static inline int adreno_is_a540(struct adreno_gpu *gpu) +{ + return gpu->revn == 540; +} + int adreno_get_param(struct msm_gpu *gpu, uint32_t param, uint64_t *value); int adreno_hw_init(struct msm_gpu *gpu); -uint32_t adreno_last_fence(struct msm_gpu *gpu); +uint32_t adreno_submitted_fence(struct msm_gpu *gpu, + struct msm_ringbuffer *ring); void adreno_recover(struct msm_gpu *gpu); -int adreno_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit, - struct msm_file_private *ctx); -void adreno_flush(struct msm_gpu *gpu); -void adreno_idle(struct msm_gpu *gpu); +void adreno_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit); +void adreno_flush(struct msm_gpu *gpu, struct msm_ringbuffer *ring); +bool adreno_idle(struct msm_gpu *gpu, struct msm_ringbuffer *ring); #ifdef CONFIG_DEBUG_FS void adreno_show(struct msm_gpu *gpu, struct seq_file *m); #endif void adreno_dump_info(struct msm_gpu *gpu); void adreno_dump(struct msm_gpu *gpu); -void adreno_wait_ring(struct msm_gpu *gpu, uint32_t ndwords); +void adreno_wait_ring(struct msm_ringbuffer *ring, uint32_t ndwords); +struct msm_ringbuffer *adreno_active_ring(struct msm_gpu *gpu); int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev, - struct adreno_gpu *gpu, const struct adreno_gpu_funcs *funcs); + struct adreno_gpu *gpu, const struct adreno_gpu_funcs *funcs, + struct msm_gpu_config *config); void adreno_gpu_cleanup(struct adreno_gpu *gpu); +void adreno_snapshot(struct msm_gpu *gpu, struct msm_snapshot *snapshot); + +int adreno_get_counter(struct msm_gpu *gpu, u32 groupid, u32 countable, + u32 *lo, u32 *hi); +u64 adreno_read_counter(struct msm_gpu *gpu, u32 groupid, int counterid); +void adreno_put_counter(struct msm_gpu *gpu, u32 groupid, int counterid); /* ringbuffer helpers (the parts that are adreno specific) */ static inline void OUT_PKT0(struct msm_ringbuffer *ring, uint16_t regindx, uint16_t cnt) { - adreno_wait_ring(ring->gpu, cnt+1); + adreno_wait_ring(ring, cnt+1); OUT_RING(ring, CP_TYPE0_PKT | ((cnt-1) << 16) | (regindx & 0x7FFF)); } @@ -261,19 +262,49 @@ static inline void OUT_PKT2(struct msm_ringbuffer *ring) { - adreno_wait_ring(ring->gpu, 1); + adreno_wait_ring(ring, 1); OUT_RING(ring, CP_TYPE2_PKT); } static inline void OUT_PKT3(struct msm_ringbuffer *ring, uint8_t opcode, uint16_t cnt) { - adreno_wait_ring(ring->gpu, cnt+1); + adreno_wait_ring(ring, cnt+1); OUT_RING(ring, CP_TYPE3_PKT | ((cnt-1) << 16) | ((opcode & 0xFF) << 8)); } +static inline u32 PM4_PARITY(u32 val) +{ + return (0x9669 >> (0xF & (val ^ + (val >> 4) ^ (val >> 8) ^ (val >> 12) ^ + (val >> 16) ^ ((val) >> 20) ^ (val >> 24) ^ + (val >> 28)))) & 1; +} + +/* Maximum number of values that can be executed for one opcode */ +#define TYPE4_MAX_PAYLOAD 127 + +#define PKT4(_reg, _cnt) \ + (CP_TYPE4_PKT | ((_cnt) << 0) | (PM4_PARITY((_cnt)) << 7) | \ + (((_reg) & 0x3FFFF) << 8) | (PM4_PARITY((_reg)) << 27)) + +static inline void +OUT_PKT4(struct msm_ringbuffer *ring, uint16_t regindx, uint16_t cnt) +{ + adreno_wait_ring(ring, cnt + 1); + OUT_RING(ring, PKT4(regindx, cnt)); +} + +static inline void +OUT_PKT7(struct msm_ringbuffer *ring, uint8_t opcode, uint16_t cnt) +{ + adreno_wait_ring(ring, cnt + 1); + OUT_RING(ring, CP_TYPE7_PKT | (cnt << 0) | (PM4_PARITY(cnt) << 15) | + ((opcode & 0x7F) << 16) | (PM4_PARITY(opcode) << 23)); +} + /* - * adreno_checkreg_off() - Checks the validity of a register enum + * adreno_reg_check() - Checks the validity of a register enum * @gpu: Pointer to struct adreno_gpu * @offset_name: The register enum that is checked */ @@ -284,6 +315,16 @@ !gpu->reg_offsets[offset_name]) { BUG(); } + + /* + * REG_SKIP is a special value that tell us that the register in + * question isn't implemented on target but don't trigger a BUG(). This + * is used to cleanly implement adreno_gpu_write64() and + * adreno_gpu_read64() in a generic fashion + */ + if (gpu->reg_offsets[offset_name] == REG_SKIP) + return false; + return true; } @@ -305,4 +346,40 @@ gpu_write(&gpu->base, reg - 1, data); } +static inline void adreno_gpu_write64(struct adreno_gpu *gpu, + enum adreno_regs lo, enum adreno_regs hi, u64 data) +{ + adreno_gpu_write(gpu, lo, lower_32_bits(data)); + adreno_gpu_write(gpu, hi, upper_32_bits(data)); +} + +static inline uint32_t get_wptr(struct msm_ringbuffer *ring) +{ + return (ring->cur - ring->start) % (MSM_GPU_RINGBUFFER_SZ >> 2); +} + +/* + * Given a register and a count, return a value to program into + * REG_CP_PROTECT_REG(n) - this will block both reads and writes for _len + * registers starting at _reg. + * + * The register base needs to be a multiple of the length. If it is not, the + * hardware will quietly mask off the bits for you and shift the size. For + * example, if you intend the protection to start at 0x07 for a length of 4 + * (0x07-0x0A) the hardware will actually protect (0x04-0x07) which might + * expose registers you intended to protect! + */ +#define ADRENO_PROTECT_RW(_reg, _len) \ + ((1 << 30) | (1 << 29) | \ + ((ilog2((_len)) & 0x1F) << 24) | (((_reg) << 2) & 0xFFFFF)) + +/* + * Same as above, but allow reads over the range. For areas of mixed use (such + * as performance counters) this allows us to protect a much larger range with a + * single register + */ +#define ADRENO_PROTECT_RDONLY(_reg, _len) \ + ((1 << 29) \ + ((ilog2((_len)) & 0x1F) << 24) | (((_reg) << 2) & 0xFFFFF)) + #endif /* __ADRENO_GPU_H__ */ diff -ruw linux-4.4.115/drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h linux-4.4.115-fbx/drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h --- linux-4.4.115/drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h 2019-01-22 16:16:23.487246262 +0100 @@ -8,17 +8,19 @@ git clone https://github.com/freedreno/envytools.git The rules-ng-ng source files this header was generated from are: -- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 398 bytes, from 2015-09-24 17:25:31) -- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2015-05-20 20:03:07) -- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 32901 bytes, from 2015-05-20 20:03:14) -- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 10755 bytes, from 2015-09-14 20:46:55) -- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 14968 bytes, from 2015-05-20 20:12:27) -- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 67771 bytes, from 2015-09-14 20:46:55) -- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 63970 bytes, from 2015-09-14 20:50:12) -- /home/robclark/src/freedreno/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2015-09-24 17:30:00) +- ./adreno.xml ( 431 bytes, from 2016-10-24 21:12:27) +- ./freedreno_copyright.xml ( 1572 bytes, from 2016-10-24 21:12:27) +- ./adreno/a2xx.xml ( 32901 bytes, from 2016-10-24 21:12:27) +- ./adreno/adreno_common.xml ( 12025 bytes, from 2016-10-24 21:12:27) +- ./adreno/adreno_pm4.xml ( 19684 bytes, from 2016-10-24 21:12:27) +- ./adreno/a3xx.xml ( 83840 bytes, from 2016-10-24 21:12:27) +- ./adreno/a4xx.xml ( 110708 bytes, from 2016-10-24 21:12:27) +- ./adreno/a5xx.xml ( 81207 bytes, from 2016-10-26 19:36:59) +- ./adreno/ocmem.xml ( 1773 bytes, from 2016-10-24 21:12:27) -Copyright (C) 2013-2015 by the following authors: +Copyright (C) 2013-2016 by the following authors: - Rob Clark (robclark) +- Ilia Mirkin (imirkin) Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the @@ -57,6 +59,7 @@ RST_PIX_CNT = 13, RST_VTX_CNT = 14, TILE_FLUSH = 15, + STAT_EVENT = 16, CACHE_FLUSH_AND_INV_TS_EVENT = 20, ZPASS_DONE = 21, CACHE_FLUSH_AND_INV_EVENT = 22, @@ -81,7 +84,6 @@ DI_PT_LINESTRIP_ADJ = 11, DI_PT_TRI_ADJ = 12, DI_PT_TRISTRIP_ADJ = 13, - DI_PT_PATCHES = 34, }; enum pc_di_src_sel { @@ -109,11 +111,15 @@ CP_TYPE1_PKT = 0x40000000, CP_TYPE2_PKT = 0x80000000, CP_TYPE3_PKT = 0xc0000000, + CP_TYPE4_PKT = 0x40000000, + CP_TYPE7_PKT = 0x70000000, }; enum adreno_pm4_type3_packets { CP_ME_INIT = 72, CP_NOP = 16, + CP_PREEMPT_ENABLE = 28, + CP_PREEMPT_TOKEN = 30, CP_INDIRECT_BUFFER = 63, CP_INDIRECT_BUFFER_PFD = 55, CP_WAIT_FOR_IDLE = 38, @@ -162,6 +168,7 @@ CP_TEST_TWO_MEMS = 113, CP_REG_WR_NO_CTXT = 120, CP_RECORD_PFP_TIMESTAMP = 17, + CP_SET_SECURE_MODE = 102, CP_WAIT_FOR_ME = 19, CP_SET_DRAW_STATE = 67, CP_DRAW_INDX_OFFSET = 56, @@ -172,6 +179,26 @@ CP_UNKNOWN_1A = 26, CP_UNKNOWN_4E = 78, CP_WIDE_REG_WRITE = 116, + CP_SCRATCH_TO_REG = 77, + CP_REG_TO_SCRATCH = 74, + CP_WAIT_MEM_WRITES = 18, + CP_COND_REG_EXEC = 71, + CP_MEM_TO_REG = 66, + CP_EXEC_CS = 51, + CP_PERFCOUNTER_ACTION = 80, + CP_SMMU_TABLE_UPDATE = 83, + CP_CONTEXT_REG_BUNCH = 92, + CP_YIELD_ENABLE = 28, + CP_SKIP_IB2_ENABLE_GLOBAL = 29, + CP_SKIP_IB2_ENABLE_LOCAL = 35, + CP_SET_SUBDRAW_SIZE = 53, + CP_SET_VISIBILITY_OVERRIDE = 100, + CP_PREEMPT_ENABLE_GLOBAL = 105, + CP_PREEMPT_ENABLE_LOCAL = 106, + CP_CONTEXT_SWITCH_YIELD = 107, + CP_SET_RENDER_MODE = 108, + CP_COMPUTE_CHECKPOINT = 110, + CP_MEM_TO_MEM = 115, IN_IB_PREFETCH_END = 23, IN_SUBBLK_PREFETCH = 31, IN_INSTR_PREFETCH = 32, @@ -190,6 +217,7 @@ SB_VERT_SHADER = 4, SB_GEOM_SHADER = 5, SB_FRAG_SHADER = 6, + SB_COMPUTE_SHADER = 7, }; enum adreno_state_type { @@ -199,7 +227,11 @@ enum adreno_state_src { SS_DIRECT = 0, + SS_INVALID_ALL_IC = 2, + SS_INVALID_PART_IC = 3, SS_INDIRECT = 4, + SS_INDIRECT_TCM = 5, + SS_INDIRECT_STM = 6, }; enum a4xx_index_size { @@ -227,7 +259,7 @@ { return ((val) << CP_LOAD_STATE_0_STATE_BLOCK__SHIFT) & CP_LOAD_STATE_0_STATE_BLOCK__MASK; } -#define CP_LOAD_STATE_0_NUM_UNIT__MASK 0x7fc00000 +#define CP_LOAD_STATE_0_NUM_UNIT__MASK 0xffc00000 #define CP_LOAD_STATE_0_NUM_UNIT__SHIFT 22 static inline uint32_t CP_LOAD_STATE_0_NUM_UNIT(uint32_t val) { @@ -379,7 +411,12 @@ { return ((val) << CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__SHIFT) & CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__MASK; } -#define CP_DRAW_INDX_OFFSET_0_TESSELLATE 0x00000100 +#define CP_DRAW_INDX_OFFSET_0_VIS_CULL__MASK 0x00000300 +#define CP_DRAW_INDX_OFFSET_0_VIS_CULL__SHIFT 8 +static inline uint32_t CP_DRAW_INDX_OFFSET_0_VIS_CULL(enum pc_di_vis_cull_mode val) +{ + return ((val) << CP_DRAW_INDX_OFFSET_0_VIS_CULL__SHIFT) & CP_DRAW_INDX_OFFSET_0_VIS_CULL__MASK; +} #define CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__MASK 0x00000c00 #define CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__SHIFT 10 static inline uint32_t CP_DRAW_INDX_OFFSET_0_INDEX_SIZE(enum a4xx_index_size val) @@ -499,5 +536,102 @@ return ((val) << CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS__SHIFT) & CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS__MASK; } +#define REG_CP_REG_TO_MEM_0 0x00000000 +#define CP_REG_TO_MEM_0_REG__MASK 0x0000ffff +#define CP_REG_TO_MEM_0_REG__SHIFT 0 +static inline uint32_t CP_REG_TO_MEM_0_REG(uint32_t val) +{ + return ((val) << CP_REG_TO_MEM_0_REG__SHIFT) & CP_REG_TO_MEM_0_REG__MASK; +} +#define CP_REG_TO_MEM_0_CNT__MASK 0x3ff80000 +#define CP_REG_TO_MEM_0_CNT__SHIFT 19 +static inline uint32_t CP_REG_TO_MEM_0_CNT(uint32_t val) +{ + return ((val) << CP_REG_TO_MEM_0_CNT__SHIFT) & CP_REG_TO_MEM_0_CNT__MASK; +} +#define CP_REG_TO_MEM_0_64B 0x40000000 +#define CP_REG_TO_MEM_0_ACCUMULATE 0x80000000 + +#define REG_CP_REG_TO_MEM_1 0x00000001 +#define CP_REG_TO_MEM_1_DEST__MASK 0xffffffff +#define CP_REG_TO_MEM_1_DEST__SHIFT 0 +static inline uint32_t CP_REG_TO_MEM_1_DEST(uint32_t val) +{ + return ((val) << CP_REG_TO_MEM_1_DEST__SHIFT) & CP_REG_TO_MEM_1_DEST__MASK; +} + +#define REG_CP_DISPATCH_COMPUTE_0 0x00000000 + +#define REG_CP_DISPATCH_COMPUTE_1 0x00000001 +#define CP_DISPATCH_COMPUTE_1_X__MASK 0xffffffff +#define CP_DISPATCH_COMPUTE_1_X__SHIFT 0 +static inline uint32_t CP_DISPATCH_COMPUTE_1_X(uint32_t val) +{ + return ((val) << CP_DISPATCH_COMPUTE_1_X__SHIFT) & CP_DISPATCH_COMPUTE_1_X__MASK; +} + +#define REG_CP_DISPATCH_COMPUTE_2 0x00000002 +#define CP_DISPATCH_COMPUTE_2_Y__MASK 0xffffffff +#define CP_DISPATCH_COMPUTE_2_Y__SHIFT 0 +static inline uint32_t CP_DISPATCH_COMPUTE_2_Y(uint32_t val) +{ + return ((val) << CP_DISPATCH_COMPUTE_2_Y__SHIFT) & CP_DISPATCH_COMPUTE_2_Y__MASK; +} + +#define REG_CP_DISPATCH_COMPUTE_3 0x00000003 +#define CP_DISPATCH_COMPUTE_3_Z__MASK 0xffffffff +#define CP_DISPATCH_COMPUTE_3_Z__SHIFT 0 +static inline uint32_t CP_DISPATCH_COMPUTE_3_Z(uint32_t val) +{ + return ((val) << CP_DISPATCH_COMPUTE_3_Z__SHIFT) & CP_DISPATCH_COMPUTE_3_Z__MASK; +} + +#define REG_CP_SET_RENDER_MODE_0 0x00000000 + +#define REG_CP_SET_RENDER_MODE_1 0x00000001 +#define CP_SET_RENDER_MODE_1_ADDR_0_LO__MASK 0xffffffff +#define CP_SET_RENDER_MODE_1_ADDR_0_LO__SHIFT 0 +static inline uint32_t CP_SET_RENDER_MODE_1_ADDR_0_LO(uint32_t val) +{ + return ((val) << CP_SET_RENDER_MODE_1_ADDR_0_LO__SHIFT) & CP_SET_RENDER_MODE_1_ADDR_0_LO__MASK; +} + +#define REG_CP_SET_RENDER_MODE_2 0x00000002 +#define CP_SET_RENDER_MODE_2_ADDR_0_HI__MASK 0xffffffff +#define CP_SET_RENDER_MODE_2_ADDR_0_HI__SHIFT 0 +static inline uint32_t CP_SET_RENDER_MODE_2_ADDR_0_HI(uint32_t val) +{ + return ((val) << CP_SET_RENDER_MODE_2_ADDR_0_HI__SHIFT) & CP_SET_RENDER_MODE_2_ADDR_0_HI__MASK; +} + +#define REG_CP_SET_RENDER_MODE_3 0x00000003 +#define CP_SET_RENDER_MODE_3_GMEM_ENABLE 0x00000010 + +#define REG_CP_SET_RENDER_MODE_4 0x00000004 + +#define REG_CP_SET_RENDER_MODE_5 0x00000005 +#define CP_SET_RENDER_MODE_5_ADDR_1_LEN__MASK 0xffffffff +#define CP_SET_RENDER_MODE_5_ADDR_1_LEN__SHIFT 0 +static inline uint32_t CP_SET_RENDER_MODE_5_ADDR_1_LEN(uint32_t val) +{ + return ((val) << CP_SET_RENDER_MODE_5_ADDR_1_LEN__SHIFT) & CP_SET_RENDER_MODE_5_ADDR_1_LEN__MASK; +} + +#define REG_CP_SET_RENDER_MODE_6 0x00000006 +#define CP_SET_RENDER_MODE_6_ADDR_1_LO__MASK 0xffffffff +#define CP_SET_RENDER_MODE_6_ADDR_1_LO__SHIFT 0 +static inline uint32_t CP_SET_RENDER_MODE_6_ADDR_1_LO(uint32_t val) +{ + return ((val) << CP_SET_RENDER_MODE_6_ADDR_1_LO__SHIFT) & CP_SET_RENDER_MODE_6_ADDR_1_LO__MASK; +} + +#define REG_CP_SET_RENDER_MODE_7 0x00000007 +#define CP_SET_RENDER_MODE_7_ADDR_1_HI__MASK 0xffffffff +#define CP_SET_RENDER_MODE_7_ADDR_1_HI__SHIFT 0 +static inline uint32_t CP_SET_RENDER_MODE_7_ADDR_1_HI(uint32_t val) +{ + return ((val) << CP_SET_RENDER_MODE_7_ADDR_1_HI__SHIFT) & CP_SET_RENDER_MODE_7_ADDR_1_HI__MASK; +} + #endif /* ADRENO_PM4_XML */ diff -ruw linux-4.4.115/drivers/gpu/drm/msm/dsi/dsi.h linux-4.4.115-fbx/drivers/gpu/drm/msm/dsi/dsi.h --- linux-4.4.115/drivers/gpu/drm/msm/dsi/dsi.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/gpu/drm/msm/dsi/dsi.h 2019-01-22 16:16:23.491246298 +0100 @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015, The Linux Foundation. All rights reserved. + * Copyright (c) 2015,2017, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -89,7 +89,7 @@ u32 *clk_pre, u32 *clk_post); void msm_dsi_manager_phy_disable(int id); int msm_dsi_manager_cmd_xfer(int id, const struct mipi_dsi_msg *msg); -bool msm_dsi_manager_cmd_xfer_trigger(int id, u32 iova, u32 len); +bool msm_dsi_manager_cmd_xfer_trigger(int id, u64 iova, u32 len); int msm_dsi_manager_register(struct msm_dsi *msm_dsi); void msm_dsi_manager_unregister(struct msm_dsi *msm_dsi); @@ -143,7 +143,7 @@ int msm_dsi_host_cmd_rx(struct mipi_dsi_host *host, const struct mipi_dsi_msg *msg); void msm_dsi_host_cmd_xfer_commit(struct mipi_dsi_host *host, - u32 iova, u32 len); + u64 iova, u32 len); int msm_dsi_host_enable(struct mipi_dsi_host *host); int msm_dsi_host_disable(struct mipi_dsi_host *host); int msm_dsi_host_power_on(struct mipi_dsi_host *host); diff -ruw linux-4.4.115/drivers/gpu/drm/msm/dsi/dsi_host.c linux-4.4.115-fbx/drivers/gpu/drm/msm/dsi/dsi_host.c --- linux-4.4.115/drivers/gpu/drm/msm/dsi/dsi_host.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/gpu/drm/msm/dsi/dsi_host.c 2019-10-29 09:26:23.625203002 +0100 @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015, The Linux Foundation. All rights reserved. + * Copyright (c) 2015,2017 The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -836,24 +836,21 @@ { struct drm_device *dev = msm_host->dev; int ret; - u32 iova; + u64 iova; - mutex_lock(&dev->struct_mutex); msm_host->tx_gem_obj = msm_gem_new(dev, size, MSM_BO_UNCACHED); if (IS_ERR(msm_host->tx_gem_obj)) { ret = PTR_ERR(msm_host->tx_gem_obj); pr_err("%s: failed to allocate gem, %d\n", __func__, ret); msm_host->tx_gem_obj = NULL; - mutex_unlock(&dev->struct_mutex); return ret; } - ret = msm_gem_get_iova_locked(msm_host->tx_gem_obj, 0, &iova); + ret = msm_gem_get_iova(msm_host->tx_gem_obj, NULL, &iova); if (ret) { pr_err("%s: failed to get iova, %d\n", __func__, ret); return ret; } - mutex_unlock(&dev->struct_mutex); if (iova & 0x07) { pr_err("%s: buf NOT 8 bytes aligned\n", __func__); @@ -974,7 +971,7 @@ static int dsi_cmd_dma_tx(struct msm_dsi_host *msm_host, int len) { int ret; - u32 iova; + uint64_t iova; bool triggered; ret = msm_gem_get_iova(msm_host->tx_gem_obj, 0, &iova); @@ -1750,11 +1747,12 @@ return ret; } -void msm_dsi_host_cmd_xfer_commit(struct mipi_dsi_host *host, u32 iova, u32 len) +void msm_dsi_host_cmd_xfer_commit(struct mipi_dsi_host *host, u64 iova, u32 len) { struct msm_dsi_host *msm_host = to_msm_dsi_host(host); - dsi_write(msm_host, REG_DSI_DMA_BASE, iova); + /* FIXME: Verify that the iova < 32 bits? */ + dsi_write(msm_host, REG_DSI_DMA_BASE, lower_32_bits(iova)); dsi_write(msm_host, REG_DSI_DMA_LEN, len); dsi_write(msm_host, REG_DSI_TRIG_DMA, 1); diff -ruw linux-4.4.115/drivers/gpu/drm/msm/dsi/dsi_manager.c linux-4.4.115-fbx/drivers/gpu/drm/msm/dsi/dsi_manager.c --- linux-4.4.115/drivers/gpu/drm/msm/dsi/dsi_manager.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/gpu/drm/msm/dsi/dsi_manager.c 2019-10-29 09:26:23.625203002 +0100 @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015, The Linux Foundation. All rights reserved. + * Copyright (c) 2015,2017 The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -774,7 +774,7 @@ return ret; } -bool msm_dsi_manager_cmd_xfer_trigger(int id, u32 iova, u32 len) +bool msm_dsi_manager_cmd_xfer_trigger(int id, u64 iova, u32 len) { struct msm_dsi *msm_dsi = dsi_mgr_get_dsi(id); struct msm_dsi *msm_dsi0 = dsi_mgr_get_dsi(DSI_0); diff -ruw linux-4.4.115/drivers/gpu/drm/msm/dsi/dsi.xml.h linux-4.4.115-fbx/drivers/gpu/drm/msm/dsi/dsi.xml.h --- linux-4.4.115/drivers/gpu/drm/msm/dsi/dsi.xml.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/gpu/drm/msm/dsi/dsi.xml.h 2019-01-22 16:16:23.491246298 +0100 @@ -9,7 +9,7 @@ The rules-ng-ng source files this header was generated from are: - /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 676 bytes, from 2015-05-20 20:03:14) -- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2015-05-20 20:03:07) +- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2016-02-10 17:07:21) - /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2015-05-20 20:03:14) - /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2015-09-18 12:07:28) - /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 37194 bytes, from 2015-09-18 12:07:28) @@ -17,11 +17,12 @@ - /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2015-10-22 16:35:02) - /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2015-05-20 20:03:14) - /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2015-05-20 20:03:07) -- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 29154 bytes, from 2015-08-10 21:25:43) +- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 41472 bytes, from 2016-01-22 18:18:18) - /home/robclark/src/freedreno/envytools/rnndb/edp/edp.xml ( 10416 bytes, from 2015-05-20 20:03:14) Copyright (C) 2013-2015 by the following authors: - Rob Clark (robclark) +- Ilia Mirkin (imirkin) Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the diff -ruw linux-4.4.115/drivers/gpu/drm/msm/edp/edp.c linux-4.4.115-fbx/drivers/gpu/drm/msm/edp/edp.c --- linux-4.4.115/drivers/gpu/drm/msm/edp/edp.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/gpu/drm/msm/edp/edp.c 2019-01-22 16:16:23.495246334 +0100 @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014-2015, The Linux Foundation. All rights reserved. + * Copyright (c) 2014-2015,2018 The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -54,7 +54,7 @@ ret = -ENOMEM; goto fail; } - DBG("eDP probed=%p", edp); + DBG("eDP probed=%pK", edp); edp->pdev = pdev; platform_set_drvdata(pdev, edp); diff -ruw linux-4.4.115/drivers/gpu/drm/msm/edp/edp.xml.h linux-4.4.115-fbx/drivers/gpu/drm/msm/edp/edp.xml.h --- linux-4.4.115/drivers/gpu/drm/msm/edp/edp.xml.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/gpu/drm/msm/edp/edp.xml.h 2019-01-22 16:16:23.495246334 +0100 @@ -9,7 +9,7 @@ The rules-ng-ng source files this header was generated from are: - /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 676 bytes, from 2015-05-20 20:03:14) -- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2015-05-20 20:03:07) +- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2016-02-10 17:07:21) - /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2015-05-20 20:03:14) - /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2015-09-18 12:07:28) - /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 37194 bytes, from 2015-09-18 12:07:28) @@ -17,11 +17,12 @@ - /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2015-10-22 16:35:02) - /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2015-05-20 20:03:14) - /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2015-05-20 20:03:07) -- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 29154 bytes, from 2015-08-10 21:25:43) +- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 41472 bytes, from 2016-01-22 18:18:18) - /home/robclark/src/freedreno/envytools/rnndb/edp/edp.xml ( 10416 bytes, from 2015-05-20 20:03:14) Copyright (C) 2013-2015 by the following authors: - Rob Clark (robclark) +- Ilia Mirkin (imirkin) Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the diff -ruw linux-4.4.115/drivers/gpu/drm/msm/hdmi/hdmi_bridge.c linux-4.4.115-fbx/drivers/gpu/drm/msm/hdmi/hdmi_bridge.c --- linux-4.4.115/drivers/gpu/drm/msm/hdmi/hdmi_bridge.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/gpu/drm/msm/hdmi/hdmi_bridge.c 2019-01-22 16:16:23.499246370 +0100 @@ -106,7 +106,7 @@ hdmi_set_mode(hdmi, true); if (hdmi->hdcp_ctrl) - hdmi_hdcp_on(hdmi->hdcp_ctrl); + hdmi_hdcp_ctrl_on(hdmi->hdcp_ctrl); } static void hdmi_bridge_enable(struct drm_bridge *bridge) @@ -124,7 +124,7 @@ struct hdmi_phy *phy = hdmi->phy; if (hdmi->hdcp_ctrl) - hdmi_hdcp_off(hdmi->hdcp_ctrl); + hdmi_hdcp_ctrl_off(hdmi->hdcp_ctrl); DBG("power down"); hdmi_set_mode(hdmi, false); diff -ruw linux-4.4.115/drivers/gpu/drm/msm/hdmi/hdmi.c linux-4.4.115-fbx/drivers/gpu/drm/msm/hdmi/hdmi.c --- linux-4.4.115/drivers/gpu/drm/msm/hdmi/hdmi.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/gpu/drm/msm/hdmi/hdmi.c 2019-01-22 16:16:23.499246370 +0100 @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014 The Linux Foundation. All rights reserved. + * Copyright (c) 2014, 2016-2017 The Linux Foundation. All rights reserved. * Copyright (C) 2013 Red Hat * Author: Rob Clark * @@ -56,7 +56,7 @@ /* Process HDCP: */ if (hdmi->hdcp_ctrl) - hdmi_hdcp_irq(hdmi->hdcp_ctrl); + hdmi_hdcp_ctrl_irq(hdmi->hdcp_ctrl); /* TODO audio.. */ @@ -75,7 +75,8 @@ flush_workqueue(hdmi->workq); destroy_workqueue(hdmi->workq); } - hdmi_hdcp_destroy(hdmi); + + hdmi_hdcp_ctrl_destroy(hdmi); if (phy) phy->funcs->destroy(phy); @@ -94,7 +95,7 @@ struct hdmi_platform_config *config = pdev->dev.platform_data; struct hdmi *hdmi = NULL; struct resource *res; - int i, ret; + int i, ret = 0; hdmi = devm_kzalloc(&pdev->dev, sizeof(*hdmi), GFP_KERNEL); if (!hdmi) { @@ -118,9 +119,19 @@ } } + res = platform_get_resource_byname(pdev, + IORESOURCE_MEM, config->mmio_name); + if (!res) { + dev_err(&pdev->dev, "failed to find ctrl resource\n"); + ret = -ENOMEM; + goto fail; + } + hdmi->mmio_len = (u32)resource_size(res); hdmi->mmio = msm_ioremap(pdev, config->mmio_name, "HDMI"); if (IS_ERR(hdmi->mmio)) { ret = PTR_ERR(hdmi->mmio); + dev_info(&pdev->dev, "can't map hdmi resource\n"); + hdmi->mmio = NULL; goto fail; } @@ -129,13 +140,39 @@ config->mmio_name); hdmi->mmio_phy_addr = res->start; + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, + config->qfprom_mmio_name); + + if (!res) { + dev_err(&pdev->dev, "failed to find qfprom resource\n"); + ret = -ENOMEM; + goto fail; + } + hdmi->qfprom_mmio_len = (u32)resource_size(res); + hdmi->qfprom_mmio = msm_ioremap(pdev, config->qfprom_mmio_name, "HDMI_QFPROM"); + if (IS_ERR(hdmi->qfprom_mmio)) { - dev_info(&pdev->dev, "can't find qfprom resource\n"); + dev_info(&pdev->dev, "can't map qfprom resource\n"); hdmi->qfprom_mmio = NULL; } + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, + config->hdcp_mmio_name); + if (!res) { + dev_err(&pdev->dev, "failed to find hdcp resource: %d\n", ret); + ret = -ENOMEM; + goto fail; + } + hdmi->hdcp_mmio_len = (u32)resource_size(res); + hdmi->hdcp_mmio = msm_ioremap(pdev, + config->hdcp_mmio_name, "HDMI_HDCP"); + if (IS_ERR(hdmi->hdcp_mmio)) { + dev_info(&pdev->dev, "can't map hdcp resource\n"); + hdmi->hdcp_mmio = NULL; + } + hdmi->hpd_regs = devm_kzalloc(&pdev->dev, sizeof(hdmi->hpd_regs[0]) * config->hpd_reg_cnt, GFP_KERNEL); if (!hdmi->hpd_regs) { @@ -228,11 +265,16 @@ goto fail; } - hdmi->hdcp_ctrl = hdmi_hdcp_init(hdmi); + hdmi->hdcp_ctrl = hdmi_hdcp_ctrl_init(hdmi); if (IS_ERR(hdmi->hdcp_ctrl)) { dev_warn(&pdev->dev, "failed to init hdcp: disabled\n"); hdmi->hdcp_ctrl = NULL; } + /*making it false currently to avoid ifdefs + *will get rid of this flag when HDCP SW + *support gets added to HDMI DRM driver + */ + hdmi->is_hdcp_supported = false; return hdmi; @@ -382,13 +424,40 @@ static struct hdmi_platform_config hdmi_tx_8996_config = { .phy_init = NULL, HDMI_CFG(pwr_reg, none), - HDMI_CFG(hpd_reg, none), + HDMI_CFG(hpd_reg, 8x74), HDMI_CFG(pwr_clk, 8x74), HDMI_CFG(hpd_clk, 8x74), .hpd_freq = hpd_clk_freq_8x74, }; +/*TO DO*/ +static const char *pwr_reg_names_8x98[] = {"core-vdda", "core-vcc"}; +/*TO DO*/ +static const char *hpd_reg_names_8x98[] = {"hpd-gdsc", "hpd-5v"}; + +static const char *pwr_clk_names_8x98[] = {"core_extp_clk", + "hpd_alt_iface_clk"}; + +static const char *hpd_clk_names_8x98[] = {"hpd_iface_clk", + "hpd_core_clk", + "hpd_mdp_core_clk", + "mnoc_clk", + "hpd_misc_ahb_clk", + "hpd_bus_clk"}; + +static unsigned long hpd_clk_freq_8x98[] = {0, 19200000, 0, 0, 0, 0}; + +static struct hdmi_platform_config hdmi_tx_8998_config = { + .phy_init = NULL, + HDMI_CFG(pwr_reg, 8x98), + HDMI_CFG(hpd_reg, 8x98), + HDMI_CFG(pwr_clk, 8x98), + HDMI_CFG(hpd_clk, 8x98), + .hpd_freq = hpd_clk_freq_8x98, +}; + static const struct of_device_id dt_match[] = { + { .compatible = "qcom,hdmi-tx-8998", .data = &hdmi_tx_8998_config }, { .compatible = "qcom,hdmi-tx-8996", .data = &hdmi_tx_8996_config }, { .compatible = "qcom,hdmi-tx-8994", .data = &hdmi_tx_8994_config }, { .compatible = "qcom,hdmi-tx-8084", .data = &hdmi_tx_8084_config }, @@ -424,7 +493,6 @@ #ifdef CONFIG_OF struct device_node *of_node = dev->of_node; const struct of_device_id *match; - match = of_match_node(dt_match, of_node); if (match && match->data) { hdmi_cfg = (struct hdmi_platform_config *)match->data; @@ -436,18 +504,20 @@ hdmi_cfg->mmio_name = "core_physical"; hdmi_cfg->qfprom_mmio_name = "qfprom_physical"; + hdmi_cfg->hdcp_mmio_name = "hdcp_physical"; hdmi_cfg->ddc_clk_gpio = get_gpio(dev, of_node, "qcom,hdmi-tx-ddc-clk"); hdmi_cfg->ddc_data_gpio = get_gpio(dev, of_node, "qcom,hdmi-tx-ddc-data"); hdmi_cfg->hpd_gpio = get_gpio(dev, of_node, "qcom,hdmi-tx-hpd"); hdmi_cfg->mux_en_gpio = get_gpio(dev, of_node, "qcom,hdmi-tx-mux-en"); hdmi_cfg->mux_sel_gpio = get_gpio(dev, of_node, "qcom,hdmi-tx-mux-sel"); hdmi_cfg->mux_lpm_gpio = get_gpio(dev, of_node, "qcom,hdmi-tx-mux-lpm"); - + hdmi_cfg->hpd5v_gpio = get_gpio(dev, of_node, "qcom,hdmi-tx-hpd5v"); #else static struct hdmi_platform_config config = {}; static const char *hpd_clk_names[] = { "core_clk", "master_iface_clk", "slave_iface_clk", }; + if (cpu_is_apq8064()) { static const char *hpd_reg_names[] = {"8921_hdmi_mvs"}; config.phy_init = hdmi_phy_8960_init; diff -ruw linux-4.4.115/drivers/gpu/drm/msm/hdmi/hdmi.h linux-4.4.115-fbx/drivers/gpu/drm/msm/hdmi/hdmi.h --- linux-4.4.115/drivers/gpu/drm/msm/hdmi/hdmi.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/gpu/drm/msm/hdmi/hdmi.h 2019-01-22 16:16:23.499246370 +0100 @@ -27,6 +27,11 @@ #include "msm_drv.h" #include "hdmi.xml.h" +#define HDMI_SEC_TO_MS 1000 +#define HDMI_MS_TO_US 1000 +#define HDMI_SEC_TO_US (HDMI_SEC_TO_MS * HDMI_MS_TO_US) +#define HDMI_KHZ_TO_HZ 1000 +#define HDMI_BUSY_WAIT_DELAY_US 100 struct hdmi_phy; struct hdmi_platform_config; @@ -45,15 +50,23 @@ const struct hdmi_platform_config *config; + /* hpd state: */ + bool hpd_off; + /* audio state: */ struct hdmi_audio audio; /* video state: */ bool power_on; unsigned long int pixclock; + unsigned long int actual_pixclock; void __iomem *mmio; void __iomem *qfprom_mmio; + void __iomem *hdcp_mmio; + u32 mmio_len; + u32 qfprom_mmio_len; + u32 hdcp_mmio_len; phys_addr_t mmio_phy_addr; struct regulator **hpd_regs; @@ -70,12 +83,16 @@ struct drm_encoder *encoder; bool hdmi_mode; /* are we in hdmi mode? */ - + bool is_hdcp_supported; int irq; + void (*ddc_sw_done_cb)(void *data); + void *sw_done_cb_data; struct workqueue_struct *workq; struct hdmi_hdcp_ctrl *hdcp_ctrl; - + bool use_hard_timeout; + int busy_wait_us; + u32 timeout_count; /* * spinlock to protect registers shared by different execution * REG_HDMI_CTRL @@ -91,7 +108,7 @@ struct hdmi_phy *(*phy_init)(struct hdmi *hdmi); const char *mmio_name; const char *qfprom_mmio_name; - + const char *hdcp_mmio_name; /* regulators that need to be on for hpd: */ const char **hpd_reg_names; int hpd_reg_cnt; @@ -110,12 +127,26 @@ int pwr_clk_cnt; /* gpio's: */ - int ddc_clk_gpio, ddc_data_gpio, hpd_gpio, mux_en_gpio, mux_sel_gpio; + int ddc_clk_gpio, ddc_data_gpio; + int hpd_gpio, mux_en_gpio; + int mux_sel_gpio, hpd5v_gpio; int mux_lpm_gpio; }; +struct hdmi_i2c_adapter { + struct i2c_adapter base; + struct hdmi *hdmi; + bool sw_done; + wait_queue_head_t ddc_event; +}; + void hdmi_set_mode(struct hdmi *hdmi, bool power_on); +#define to_hdmi_i2c_adapter(x) container_of(x, struct hdmi_i2c_adapter, base) + +int ddc_clear_irq(struct hdmi *hdmi); +void init_ddc(struct hdmi *hdmi); + static inline void hdmi_write(struct hdmi *hdmi, u32 reg, u32 data) { msm_writel(data, hdmi->mmio + reg); @@ -185,12 +216,19 @@ struct i2c_adapter *hdmi_i2c_init(struct hdmi *hdmi); /* + * DDC utility functions + */ +int hdmi_ddc_read(struct hdmi *hdmi, u16 addr, u8 offset, + u8 *data, u16 data_len, bool self_retry); +int hdmi_ddc_write(struct hdmi *hdmi, u16 addr, u8 offset, + u8 *data, u16 data_len, bool self_retry); +/* * hdcp */ -struct hdmi_hdcp_ctrl *hdmi_hdcp_init(struct hdmi *hdmi); -void hdmi_hdcp_destroy(struct hdmi *hdmi); -void hdmi_hdcp_on(struct hdmi_hdcp_ctrl *hdcp_ctrl); -void hdmi_hdcp_off(struct hdmi_hdcp_ctrl *hdcp_ctrl); -void hdmi_hdcp_irq(struct hdmi_hdcp_ctrl *hdcp_ctrl); +struct hdmi_hdcp_ctrl *hdmi_hdcp_ctrl_init(struct hdmi *hdmi); +void hdmi_hdcp_ctrl_destroy(struct hdmi *hdmi); +void hdmi_hdcp_ctrl_on(struct hdmi_hdcp_ctrl *hdcp_ctrl); +void hdmi_hdcp_ctrl_off(struct hdmi_hdcp_ctrl *hdcp_ctrl); +void hdmi_hdcp_ctrl_irq(struct hdmi_hdcp_ctrl *hdcp_ctrl); #endif /* __HDMI_CONNECTOR_H__ */ diff -ruw linux-4.4.115/drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c linux-4.4.115-fbx/drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c --- linux-4.4.115/drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c 2019-01-22 16:16:23.499246370 +0100 @@ -1,4 +1,4 @@ -/* Copyright (c) 2010-2015, The Linux Foundation. All rights reserved. +/* Copyright (c) 2010-2017, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -14,6 +14,7 @@ #include "hdmi.h" #include +#ifdef CONFIG_DRM_MSM_HDCP #define HDCP_REG_ENABLE 0x01 #define HDCP_REG_DISABLE 0x00 #define HDCP_PORT_ADDR 0x74 @@ -84,84 +85,6 @@ bool max_dev_exceeded; }; -static int hdmi_ddc_read(struct hdmi *hdmi, u16 addr, u8 offset, - u8 *data, u16 data_len) -{ - int rc; - int retry = 5; - struct i2c_msg msgs[] = { - { - .addr = addr >> 1, - .flags = 0, - .len = 1, - .buf = &offset, - }, { - .addr = addr >> 1, - .flags = I2C_M_RD, - .len = data_len, - .buf = data, - } - }; - - DBG("Start DDC read"); -retry: - rc = i2c_transfer(hdmi->i2c, msgs, 2); - - retry--; - if (rc == 2) - rc = 0; - else if (retry > 0) - goto retry; - else - rc = -EIO; - - DBG("End DDC read %d", rc); - - return rc; -} - -#define HDCP_DDC_WRITE_MAX_BYTE_NUM 32 - -static int hdmi_ddc_write(struct hdmi *hdmi, u16 addr, u8 offset, - u8 *data, u16 data_len) -{ - int rc; - int retry = 10; - u8 buf[HDCP_DDC_WRITE_MAX_BYTE_NUM]; - struct i2c_msg msgs[] = { - { - .addr = addr >> 1, - .flags = 0, - .len = 1, - } - }; - - DBG("Start DDC write"); - if (data_len > (HDCP_DDC_WRITE_MAX_BYTE_NUM - 1)) { - pr_err("%s: write size too big\n", __func__); - return -ERANGE; - } - - buf[0] = offset; - memcpy(&buf[1], data, data_len); - msgs[0].buf = buf; - msgs[0].len = data_len + 1; -retry: - rc = i2c_transfer(hdmi->i2c, msgs, 1); - - retry--; - if (rc == 1) - rc = 0; - else if (retry > 0) - goto retry; - else - rc = -EIO; - - DBG("End DDC write %d", rc); - - return rc; -} - static int hdmi_hdcp_scm_wr(struct hdmi_hdcp_ctrl *hdcp_ctrl, u32 *preg, u32 *pdata, u32 count) { @@ -202,7 +125,7 @@ return ret; } -void hdmi_hdcp_irq(struct hdmi_hdcp_ctrl *hdcp_ctrl) +void hdmi_hdcp_ctrl_irq(struct hdmi_hdcp_ctrl *hdcp_ctrl) { struct hdmi *hdmi = hdcp_ctrl->hdmi; u32 reg_val, hdcp_int_status; @@ -1310,7 +1233,7 @@ } } -void hdmi_hdcp_on(struct hdmi_hdcp_ctrl *hdcp_ctrl) +void hdmi_hdcp_ctrl_on(struct hdmi_hdcp_ctrl *hdcp_ctrl) { struct hdmi *hdmi = hdcp_ctrl->hdmi; u32 reg_val; @@ -1335,7 +1258,7 @@ queue_work(hdmi->workq, &hdcp_ctrl->hdcp_auth_work); } -void hdmi_hdcp_off(struct hdmi_hdcp_ctrl *hdcp_ctrl) +void hdmi_hdcp_ctrl_off(struct hdmi_hdcp_ctrl *hdcp_ctrl) { struct hdmi *hdmi = hdcp_ctrl->hdmi; unsigned long flags; @@ -1399,7 +1322,7 @@ DBG("HDCP: Off"); } -struct hdmi_hdcp_ctrl *hdmi_hdcp_init(struct hdmi *hdmi) +struct hdmi_hdcp_ctrl *hdmi_hdcp_ctrl_init(struct hdmi *hdmi) { struct hdmi_hdcp_ctrl *hdcp_ctrl = NULL; @@ -1428,10 +1351,33 @@ return hdcp_ctrl; } -void hdmi_hdcp_destroy(struct hdmi *hdmi) +void hdmi_hdcp_ctrl_destroy(struct hdmi *hdmi) { if (hdmi && hdmi->hdcp_ctrl) { kfree(hdmi->hdcp_ctrl); hdmi->hdcp_ctrl = NULL; } } + +#else +struct hdmi_hdcp_ctrl *hdmi_hdcp_ctrl_init(struct hdmi *hdmi) +{ + return NULL; +} + +void hdmi_hdcp_ctrl_destroy(struct hdmi *hdmi) +{ +} + +void hdmi_hdcp_ctrl_on(struct hdmi_hdcp_ctrl *hdcp_ctrl) +{ +} + +void hdmi_hdcp_ctrl_off(struct hdmi_hdcp_ctrl *hdcp_ctrl) +{ +} + +void hdmi_hdcp_ctrl_irq(struct hdmi_hdcp_ctrl *hdcp_ctrl) +{ +} +#endif diff -ruw linux-4.4.115/drivers/gpu/drm/msm/hdmi/hdmi_i2c.c linux-4.4.115-fbx/drivers/gpu/drm/msm/hdmi/hdmi_i2c.c --- linux-4.4.115/drivers/gpu/drm/msm/hdmi/hdmi_i2c.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/gpu/drm/msm/hdmi/hdmi_i2c.c 2019-01-22 16:16:23.499246370 +0100 @@ -17,66 +17,16 @@ #include "hdmi.h" -struct hdmi_i2c_adapter { - struct i2c_adapter base; - struct hdmi *hdmi; - bool sw_done; - wait_queue_head_t ddc_event; -}; -#define to_hdmi_i2c_adapter(x) container_of(x, struct hdmi_i2c_adapter, base) - -static void init_ddc(struct hdmi_i2c_adapter *hdmi_i2c) -{ - struct hdmi *hdmi = hdmi_i2c->hdmi; - - hdmi_write(hdmi, REG_HDMI_DDC_CTRL, - HDMI_DDC_CTRL_SW_STATUS_RESET); - hdmi_write(hdmi, REG_HDMI_DDC_CTRL, - HDMI_DDC_CTRL_SOFT_RESET); - - hdmi_write(hdmi, REG_HDMI_DDC_SPEED, - HDMI_DDC_SPEED_THRESHOLD(2) | - HDMI_DDC_SPEED_PRESCALE(10)); - - hdmi_write(hdmi, REG_HDMI_DDC_SETUP, - HDMI_DDC_SETUP_TIMEOUT(0xff)); +#define MAX_TRANSACTIONS 4 - /* enable reference timer for 27us */ - hdmi_write(hdmi, REG_HDMI_DDC_REF, - HDMI_DDC_REF_REFTIMER_ENABLE | - HDMI_DDC_REF_REFTIMER(27)); -} +#define SDE_DDC_TXN_CNT_MASK 0x07ff0000 +#define SDE_DDC_TXN_CNT_SHIFT 16 -static int ddc_clear_irq(struct hdmi_i2c_adapter *hdmi_i2c) +static inline uint32_t SDE_HDMI_I2C_TRANSACTION_REG_CNT(uint32_t val) { - struct hdmi *hdmi = hdmi_i2c->hdmi; - struct drm_device *dev = hdmi->dev; - uint32_t retry = 0xffff; - uint32_t ddc_int_ctrl; - - do { - --retry; - - hdmi_write(hdmi, REG_HDMI_DDC_INT_CTRL, - HDMI_DDC_INT_CTRL_SW_DONE_ACK | - HDMI_DDC_INT_CTRL_SW_DONE_MASK); - - ddc_int_ctrl = hdmi_read(hdmi, REG_HDMI_DDC_INT_CTRL); - - } while ((ddc_int_ctrl & HDMI_DDC_INT_CTRL_SW_DONE_INT) && retry); - - if (!retry) { - dev_err(dev->dev, "timeout waiting for DDC\n"); - return -ETIMEDOUT; - } - - hdmi_i2c->sw_done = false; - - return 0; + return ((val) << SDE_DDC_TXN_CNT_SHIFT) & SDE_DDC_TXN_CNT_MASK; } -#define MAX_TRANSACTIONS 4 - static bool sw_done(struct hdmi_i2c_adapter *hdmi_i2c) { struct hdmi *hdmi = hdmi_i2c->hdmi; @@ -115,12 +65,13 @@ WARN_ON(!(hdmi_read(hdmi, REG_HDMI_CTRL) & HDMI_CTRL_ENABLE)); + if (num == 0) return num; - init_ddc(hdmi_i2c); + init_ddc(hdmi); - ret = ddc_clear_irq(hdmi_i2c); + ret = ddc_clear_irq(hdmi); if (ret) return ret; @@ -155,7 +106,7 @@ } } - i2c_trans = HDMI_I2C_TRANSACTION_REG_CNT(p->len) | + i2c_trans = SDE_HDMI_I2C_TRANSACTION_REG_CNT(p->len) | HDMI_I2C_TRANSACTION_REG_RW( (p->flags & I2C_M_RD) ? DDC_READ : DDC_WRITE) | HDMI_I2C_TRANSACTION_REG_START; @@ -180,6 +131,10 @@ hdmi_read(hdmi, REG_HDMI_DDC_SW_STATUS), hdmi_read(hdmi, REG_HDMI_DDC_HW_STATUS), hdmi_read(hdmi, REG_HDMI_DDC_INT_CTRL)); + if (hdmi->use_hard_timeout) { + hdmi->use_hard_timeout = false; + hdmi->timeout_count = 0; + } return ret; } @@ -213,6 +168,10 @@ } } + if (hdmi->use_hard_timeout) { + hdmi->use_hard_timeout = false; + hdmi->timeout_count = jiffies_to_msecs(ret); + } return i; } diff -ruw linux-4.4.115/drivers/gpu/drm/msm/hdmi/hdmi.xml.h linux-4.4.115-fbx/drivers/gpu/drm/msm/hdmi/hdmi.xml.h --- linux-4.4.115/drivers/gpu/drm/msm/hdmi/hdmi.xml.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/gpu/drm/msm/hdmi/hdmi.xml.h 2019-01-22 16:16:23.499246370 +0100 @@ -9,7 +9,7 @@ The rules-ng-ng source files this header was generated from are: - /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 676 bytes, from 2015-05-20 20:03:14) -- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2015-05-20 20:03:07) +- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2016-02-10 17:07:21) - /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2015-05-20 20:03:14) - /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2015-09-18 12:07:28) - /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 37194 bytes, from 2015-09-18 12:07:28) @@ -17,11 +17,12 @@ - /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2015-10-22 16:35:02) - /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2015-05-20 20:03:14) - /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2015-05-20 20:03:07) -- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 29154 bytes, from 2015-08-10 21:25:43) +- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 41472 bytes, from 2016-01-22 18:18:18) - /home/robclark/src/freedreno/envytools/rnndb/edp/edp.xml ( 10416 bytes, from 2015-05-20 20:03:14) -Copyright (C) 2013-2015 by the following authors: +Copyright (C) 2013-2016 by the following authors: - Rob Clark (robclark) +- Ilia Mirkin (imirkin) Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the @@ -110,6 +111,8 @@ #define HDMI_INFOFRAME_CTRL0_AUDIO_INFO_SOURCE 0x00000040 #define HDMI_INFOFRAME_CTRL0_AUDIO_INFO_UPDATE 0x00000080 +#define REG_HDMI_INFOFRAME_CTRL1 0x00000030 + #define REG_HDMI_GEN_PKT_CTRL 0x00000034 #define HDMI_GEN_PKT_CTRL_GENERIC0_SEND 0x00000001 #define HDMI_GEN_PKT_CTRL_GENERIC0_CONT 0x00000002 @@ -149,6 +152,7 @@ #define REG_HDMI_GENERIC1_HDR 0x000000a4 +#define MAX_REG_HDMI_GENERIC1_INDEX 6 static inline uint32_t REG_HDMI_GENERIC1(uint32_t i0) { return 0x000000a8 + 0x4*i0; } static inline uint32_t REG_HDMI_ACR(enum hdmi_acr_cts i0) { return 0x000000c4 + 0x8*i0; } @@ -462,13 +466,13 @@ #define REG_HDMI_CEC_RD_FILTER 0x000002b0 #define REG_HDMI_ACTIVE_HSYNC 0x000002b4 -#define HDMI_ACTIVE_HSYNC_START__MASK 0x00000fff +#define HDMI_ACTIVE_HSYNC_START__MASK 0x00001fff #define HDMI_ACTIVE_HSYNC_START__SHIFT 0 static inline uint32_t HDMI_ACTIVE_HSYNC_START(uint32_t val) { return ((val) << HDMI_ACTIVE_HSYNC_START__SHIFT) & HDMI_ACTIVE_HSYNC_START__MASK; } -#define HDMI_ACTIVE_HSYNC_END__MASK 0x0fff0000 +#define HDMI_ACTIVE_HSYNC_END__MASK 0x1fff0000 #define HDMI_ACTIVE_HSYNC_END__SHIFT 16 static inline uint32_t HDMI_ACTIVE_HSYNC_END(uint32_t val) { @@ -476,13 +480,13 @@ } #define REG_HDMI_ACTIVE_VSYNC 0x000002b8 -#define HDMI_ACTIVE_VSYNC_START__MASK 0x00000fff +#define HDMI_ACTIVE_VSYNC_START__MASK 0x00001fff #define HDMI_ACTIVE_VSYNC_START__SHIFT 0 static inline uint32_t HDMI_ACTIVE_VSYNC_START(uint32_t val) { return ((val) << HDMI_ACTIVE_VSYNC_START__SHIFT) & HDMI_ACTIVE_VSYNC_START__MASK; } -#define HDMI_ACTIVE_VSYNC_END__MASK 0x0fff0000 +#define HDMI_ACTIVE_VSYNC_END__MASK 0x1fff0000 #define HDMI_ACTIVE_VSYNC_END__SHIFT 16 static inline uint32_t HDMI_ACTIVE_VSYNC_END(uint32_t val) { @@ -490,13 +494,13 @@ } #define REG_HDMI_VSYNC_ACTIVE_F2 0x000002bc -#define HDMI_VSYNC_ACTIVE_F2_START__MASK 0x00000fff +#define HDMI_VSYNC_ACTIVE_F2_START__MASK 0x00001fff #define HDMI_VSYNC_ACTIVE_F2_START__SHIFT 0 static inline uint32_t HDMI_VSYNC_ACTIVE_F2_START(uint32_t val) { return ((val) << HDMI_VSYNC_ACTIVE_F2_START__SHIFT) & HDMI_VSYNC_ACTIVE_F2_START__MASK; } -#define HDMI_VSYNC_ACTIVE_F2_END__MASK 0x0fff0000 +#define HDMI_VSYNC_ACTIVE_F2_END__MASK 0x1fff0000 #define HDMI_VSYNC_ACTIVE_F2_END__SHIFT 16 static inline uint32_t HDMI_VSYNC_ACTIVE_F2_END(uint32_t val) { @@ -504,13 +508,13 @@ } #define REG_HDMI_TOTAL 0x000002c0 -#define HDMI_TOTAL_H_TOTAL__MASK 0x00000fff +#define HDMI_TOTAL_H_TOTAL__MASK 0x00001fff #define HDMI_TOTAL_H_TOTAL__SHIFT 0 static inline uint32_t HDMI_TOTAL_H_TOTAL(uint32_t val) { return ((val) << HDMI_TOTAL_H_TOTAL__SHIFT) & HDMI_TOTAL_H_TOTAL__MASK; } -#define HDMI_TOTAL_V_TOTAL__MASK 0x0fff0000 +#define HDMI_TOTAL_V_TOTAL__MASK 0x1fff0000 #define HDMI_TOTAL_V_TOTAL__SHIFT 16 static inline uint32_t HDMI_TOTAL_V_TOTAL(uint32_t val) { @@ -518,7 +522,7 @@ } #define REG_HDMI_VSYNC_TOTAL_F2 0x000002c4 -#define HDMI_VSYNC_TOTAL_F2_V_TOTAL__MASK 0x00000fff +#define HDMI_VSYNC_TOTAL_F2_V_TOTAL__MASK 0x00001fff #define HDMI_VSYNC_TOTAL_F2_V_TOTAL__SHIFT 0 static inline uint32_t HDMI_VSYNC_TOTAL_F2_V_TOTAL(uint32_t val) { @@ -559,6 +563,20 @@ #define REG_HDMI_CEC_WR_CHECK_CONFIG 0x00000370 +#define REG_HDMI_DDC_INT_CTRL0 0x00000430 +#define REG_HDMI_DDC_INT_CTRL1 0x00000434 +#define REG_HDMI_DDC_INT_CTRL2 0x00000438 +#define REG_HDMI_DDC_INT_CTRL3 0x0000043C +#define REG_HDMI_DDC_INT_CTRL4 0x00000440 +#define REG_HDMI_DDC_INT_CTRL5 0x00000444 +#define REG_HDMI_SCRAMBLER_STATUS_DDC_CTRL 0x00000464 +#define REG_HDMI_SCRAMBLER_STATUS_DDC_TIMER_CTRL 0x00000468 +#define REG_HDMI_SCRAMBLER_STATUS_DDC_TIMER_CTRL2 0x0000046C +#define REG_HDMI_SCRAMBLER_STATUS_DDC_STATUS 0x00000470 +#define REG_HDMI_SCRAMBLER_STATUS_DDC_TIMER_STATUS 0x00000474 +#define REG_HDMI_SCRAMBLER_STATUS_DDC_TIMER_STATUS2 0x00000478 +#define REG_HDMI_HW_DDC_CTRL 0x000004CC + #define REG_HDMI_8x60_PHY_REG0 0x00000300 #define HDMI_8x60_PHY_REG0_DESER_DEL_CTRL__MASK 0x0000001c #define HDMI_8x60_PHY_REG0_DESER_DEL_CTRL__SHIFT 2 diff -ruw linux-4.4.115/drivers/gpu/drm/msm/Kconfig linux-4.4.115-fbx/drivers/gpu/drm/msm/Kconfig --- linux-4.4.115/drivers/gpu/drm/msm/Kconfig 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/gpu/drm/msm/Kconfig 2019-10-29 09:26:23.621202963 +0100 @@ -3,13 +3,17 @@ tristate "MSM DRM" depends on DRM depends on ARCH_QCOM || (ARM && COMPILE_TEST) - depends on OF && COMMON_CLK + depends on OF select REGULATOR select DRM_KMS_HELPER select DRM_PANEL select SHMEM select TMPFS select QCOM_SCM + select BACKLIGHT_CLASS_DEVICE + select MSM_EXT_DISPLAY + select MMU_NOTIFIER + select INTERVAL_TREE default y help DRM/KMS driver for MSM/snapdragon. @@ -33,6 +37,18 @@ Choose this option if you have a need for MIPI DSI connector support. +config DRM_MSM_DSI_STAGING + bool "Enable new DSI driver support in MSM DRM driver" + depends on DRM_MSM + select DRM_PANEL + select DRM_MIPI_DSI + default y + help + Choose this option if you need MIPI DSI connector support on MSM + which conforms to DRM. MIPI stands for Mobile Industry Processor + Interface and DSI stands for Display Serial Interface which powers + the primary display of your mobile device. + config DRM_MSM_DSI_PLL bool "Enable DSI PLL driver in MSM DRM" depends on DRM_MSM_DSI && COMMON_CLK @@ -54,3 +70,41 @@ default y help Choose this option if the 20nm DSI PHY is used on the platform. + +config DRM_MSM_MDP4 + tristate "MSM MDP4 DRM driver" + depends on DRM_MSM + default n + help + Choose this option if MSM MDP4 revision support is needed in DRM/KMS. + +config DRM_MSM_HDCP + tristate "HDCP for MSM DRM" + depends on DRM_MSM + default n + help + Chose this option if HDCP supported is needed in DRM/KMS driver. + +config DRM_SDE_WB + bool "Enable Writeback support in SDE DRM" + depends on DRM_MSM + default y + help + Choose this option for writeback connector support. + +config DRM_SDE_HDMI + bool "Enable HDMI driver support in DRM SDE driver" + depends on DRM_MSM + default y + help + Choose this option if HDMI connector support is needed in SDE driver. + +config DRM_SDE_EVTLOG_DEBUG + bool "Enable event logging in MSM DRM" + depends on DRM_MSM + help + The SDE DRM debugging provides support to enable display debugging + features to: dump SDE registers during driver errors, panic + driver during fatal errors and enable some display-driver logging + into an internal buffer (this avoids logging overhead). + diff -ruw linux-4.4.115/drivers/gpu/drm/msm/Makefile linux-4.4.115-fbx/drivers/gpu/drm/msm/Makefile --- linux-4.4.115/drivers/gpu/drm/msm/Makefile 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/gpu/drm/msm/Makefile 2019-01-22 16:16:23.479246189 +0100 @@ -1,17 +1,19 @@ -ccflags-y := -Iinclude/drm -Idrivers/gpu/drm/msm +ccflags-y := -Iinclude/drm -Idrivers/gpu/drm/msm -Idrivers/gpu/drm/msm/dsi-staging +ccflags-y += -Idrivers/gpu/drm/msm/hdmi +ccflags-y += -Idrivers/gpu/drm/msm/hdmi-staging ccflags-$(CONFIG_DRM_MSM_DSI) += -Idrivers/gpu/drm/msm/dsi +ccflags-$(CONFIG_SYNC) += -Idrivers/staging/android +ccflags-$(CONFIG_DRM_MSM_DSI_PLL) += -Idrivers/gpu/drm/msm/dsi +ccflags-y += -Idrivers/gpu/drm/msm/sde -msm-y := \ - adreno/adreno_device.o \ - adreno/adreno_gpu.o \ - adreno/a3xx_gpu.o \ - adreno/a4xx_gpu.o \ +msm_drm-y := \ hdmi/hdmi.o \ hdmi/hdmi_audio.o \ hdmi/hdmi_bridge.o \ hdmi/hdmi_connector.o \ hdmi/hdmi_hdcp.o \ hdmi/hdmi_i2c.o \ + hdmi/hdmi_util.o \ hdmi/hdmi_phy_8960.o \ hdmi/hdmi_phy_8x60.o \ hdmi/hdmi_phy_8x74.o \ @@ -23,13 +25,6 @@ edp/edp_phy.o \ mdp/mdp_format.o \ mdp/mdp_kms.o \ - mdp/mdp4/mdp4_crtc.o \ - mdp/mdp4/mdp4_dtv_encoder.o \ - mdp/mdp4/mdp4_lcdc_encoder.o \ - mdp/mdp4/mdp4_lvds_connector.o \ - mdp/mdp4/mdp4_irq.o \ - mdp/mdp4/mdp4_kms.o \ - mdp/mdp4/mdp4_plane.o \ mdp/mdp5/mdp5_cfg.o \ mdp/mdp5/mdp5_ctl.o \ mdp/mdp5/mdp5_crtc.o \ @@ -38,34 +33,125 @@ mdp/mdp5/mdp5_kms.o \ mdp/mdp5/mdp5_plane.o \ mdp/mdp5/mdp5_smp.o \ + sde/sde_crtc.o \ + sde/sde_encoder.o \ + sde/sde_encoder_phys_vid.o \ + sde/sde_encoder_phys_cmd.o \ + sde/sde_irq.o \ + sde/sde_core_irq.o \ + sde/sde_core_perf.o \ + sde/sde_rm.o \ + sde/sde_kms_utils.o \ + sde/sde_kms.o \ + sde/sde_plane.o \ + sde/sde_connector.o \ + sde/sde_backlight.o \ + sde/sde_color_processing.o \ + sde/sde_vbif.o \ + sde/sde_splash.o \ + sde_dbg.o \ + sde_dbg_evtlog.o \ + sde_io_util.o \ + dba_bridge.o \ + sde_edid_parser.o \ + sde_hdcp_1x.o + +# use drm gpu driver only if qcom_kgsl driver not available +ifneq ($(CONFIG_QCOM_KGSL),y) +msm_drm-y += adreno/adreno_device.o \ + adreno/adreno_gpu.o \ + adreno/a3xx_gpu.o \ + adreno/a4xx_gpu.o \ + adreno/a5xx_gpu.o \ + adreno/a5xx_power.o \ + adreno/a5xx_preempt.o \ + adreno/a5xx_snapshot.o \ + adreno/a5xx_counters.o +endif + +msm_drm-$(CONFIG_DRM_MSM_MDP4) += mdp/mdp4/mdp4_crtc.o \ + mdp/mdp4/mdp4_dtv_encoder.o \ + mdp/mdp4/mdp4_lcdc_encoder.o \ + mdp/mdp4/mdp4_lvds_connector.o \ + mdp/mdp4/mdp4_irq.o \ + mdp/mdp4/mdp4_kms.o \ + mdp/mdp4/mdp4_plane.o + +msm_drm-$(CONFIG_DRM_FBDEV_EMULATION) += msm_fbdev.o +msm_drm-$(CONFIG_SYNC) += sde/sde_fence.o +msm_drm-$(CONFIG_COMMON_CLK) += mdp/mdp4/mdp4_lvds_pll.o + +msm_drm-$(CONFIG_DRM_MSM_DSI) += dsi/dsi.o \ + dsi/dsi_cfg.o \ + dsi/dsi_host.o \ + dsi/dsi_manager.o \ + dsi/phy/dsi_phy.o \ + dsi/dsi_manager.o \ + mdp/mdp5/mdp5_cmd_encoder.o + +msm_drm-$(CONFIG_DRM_MSM_DSI_28NM_PHY) += dsi/phy/dsi_phy_28nm.o +msm_drm-$(CONFIG_DRM_MSM_DSI_20NM_PHY) += dsi/phy/dsi_phy_20nm.o + +msm_drm-$(CONFIG_DRM_MSM_DSI_STAGING) += dsi-staging/dsi_phy.o \ + dsi-staging/dsi_clk_pwr.o \ + dsi-staging/dsi_phy.o \ + dsi-staging/dsi_phy_hw_v4_0.o \ + dsi-staging/dsi_ctrl_hw_1_4.o \ + dsi-staging/dsi_ctrl.o \ + dsi-staging/dsi_catalog.o \ + dsi-staging/dsi_drm.o \ + dsi-staging/dsi_display.o \ + dsi-staging/dsi_panel.o \ + dsi-staging/dsi_display_test.o + +msm_drm-$(CONFIG_DRM_SDE_HDMI) += \ + hdmi-staging/sde_hdmi_util.o \ + hdmi-staging/sde_hdmi.o \ + hdmi-staging/sde_hdmi_bridge.o \ + hdmi-staging/sde_hdmi_audio.o \ + hdmi-staging/sde_hdmi_hdcp2p2.o \ + +msm_drm-$(CONFIG_DRM_MSM_DSI_PLL) += dsi/pll/dsi_pll.o \ + dsi/pll/dsi_pll_28nm.o + +msm_drm-$(CONFIG_DRM_MSM) += \ + sde/sde_hw_catalog.o \ + sde/sde_hw_cdm.o \ + sde/sde_hw_dspp.o \ + sde/sde_hw_intf.o \ + sde/sde_hw_lm.o \ + sde/sde_hw_ctl.o \ + sde/sde_hw_util.o \ + sde/sde_hw_sspp.o \ + sde/sde_hw_wb.o \ + sde/sde_hw_pingpong.o \ + sde/sde_hw_top.o \ + sde/sde_hw_interrupts.o \ + sde/sde_hw_vbif.o \ + sde/sde_formats.o \ + sde_power_handle.o \ + sde/sde_hw_color_processing_v1_7.o + +msm_drm-$(CONFIG_DRM_SDE_WB) += sde/sde_wb.o \ + sde/sde_encoder_phys_wb.o + +msm_drm-$(CONFIG_DRM_MSM) += \ msm_atomic.o \ msm_drv.o \ msm_fb.o \ msm_gem.o \ msm_gem_prime.o \ msm_gem_submit.o \ + msm_gem_vma.o \ msm_gpu.o \ msm_iommu.o \ + msm_smmu.o \ msm_perf.o \ msm_rd.o \ - msm_ringbuffer.o - -msm-$(CONFIG_DRM_FBDEV_EMULATION) += msm_fbdev.o -msm-$(CONFIG_COMMON_CLK) += mdp/mdp4/mdp4_lvds_pll.o - -msm-$(CONFIG_DRM_MSM_DSI) += dsi/dsi.o \ - dsi/dsi_cfg.o \ - dsi/dsi_host.o \ - dsi/dsi_manager.o \ - dsi/phy/dsi_phy.o \ - mdp/mdp5/mdp5_cmd_encoder.o - -msm-$(CONFIG_DRM_MSM_DSI_28NM_PHY) += dsi/phy/dsi_phy_28nm.o -msm-$(CONFIG_DRM_MSM_DSI_20NM_PHY) += dsi/phy/dsi_phy_20nm.o - -ifeq ($(CONFIG_DRM_MSM_DSI_PLL),y) -msm-y += dsi/pll/dsi_pll.o -msm-$(CONFIG_DRM_MSM_DSI_28NM_PHY) += dsi/pll/dsi_pll_28nm.o -endif + msm_ringbuffer.o \ + msm_prop.o \ + msm_snapshot.o \ + msm_submitqueue.o \ + msm_trace_points.o -obj-$(CONFIG_DRM_MSM) += msm.o +obj-$(CONFIG_DRM_MSM) += msm_drm.o diff -ruw linux-4.4.115/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.c linux-4.4.115-fbx/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.c --- linux-4.4.115/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.c 2019-01-22 16:16:23.503246407 +0100 @@ -547,7 +547,7 @@ if (cfg_handler) mdp5_cfg_destroy(cfg_handler); - return NULL; + return ERR_PTR(ret); } static struct mdp5_cfg_platform *mdp5_get_config(struct platform_device *dev) diff -ruw linux-4.4.115/drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c linux-4.4.115-fbx/drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c --- linux-4.4.115/drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c 2019-10-29 09:26:23.633203080 +0100 @@ -171,7 +171,7 @@ container_of(work, struct mdp5_crtc, unref_cursor_work); struct mdp5_kms *mdp5_kms = get_kms(&mdp5_crtc->base); - msm_gem_put_iova(val, mdp5_kms->id); + msm_gem_put_iova(val, mdp5_kms->aspace); drm_gem_object_unreference_unlocked(val); } @@ -509,7 +509,8 @@ struct drm_device *dev = crtc->dev; struct mdp5_kms *mdp5_kms = get_kms(crtc); struct drm_gem_object *cursor_bo, *old_bo = NULL; - uint32_t blendcfg, cursor_addr, stride; + uint32_t blendcfg, stride; + uint64_t cursor_addr; int ret, bpp, lm; unsigned int depth; enum mdp5_cursor_alpha cur_alpha = CURSOR_ALPHA_PER_PIXEL; @@ -536,7 +537,7 @@ if (!cursor_bo) return -ENOENT; - ret = msm_gem_get_iova(cursor_bo, mdp5_kms->id, &cursor_addr); + ret = msm_gem_get_iova(cursor_bo, mdp5_kms->aspace, &cursor_addr); if (ret) return -EINVAL; diff -ruw linux-4.4.115/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c linux-4.4.115-fbx/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c --- linux-4.4.115/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c 2019-01-22 16:16:23.503246407 +0100 @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014, The Linux Foundation. All rights reserved. + * Copyright (c) 2014, 2016-2017 The Linux Foundation. All rights reserved. * Copyright (C) 2013 Red Hat * Author: Rob Clark * @@ -18,13 +18,10 @@ #include "msm_drv.h" +#include "msm_gem.h" #include "msm_mmu.h" #include "mdp5_kms.h" -static const char *iommu_ports[] = { - "mdp_0", -}; - static int mdp5_hw_init(struct msm_kms *kms) { struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms)); @@ -130,13 +127,13 @@ static void mdp5_destroy(struct msm_kms *kms) { struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms)); - struct msm_mmu *mmu = mdp5_kms->mmu; + struct msm_gem_address_space *aspace = mdp5_kms->aspace; mdp5_irq_domain_fini(mdp5_kms); - if (mmu) { - mmu->funcs->detach(mmu, iommu_ports, ARRAY_SIZE(iommu_ports)); - mmu->funcs->destroy(mmu); + if (aspace) { + aspace->mmu->funcs->detach(aspace->mmu); + msm_gem_address_space_put(aspace); } if (mdp5_kms->ctlm) @@ -474,7 +471,7 @@ struct mdp5_cfg *config; struct mdp5_kms *mdp5_kms; struct msm_kms *kms = NULL; - struct msm_mmu *mmu; + struct msm_gem_address_space *aspace; uint32_t major, minor; int i, ret; @@ -595,33 +592,33 @@ mdelay(16); if (config->platform.iommu) { - mmu = msm_iommu_new(&pdev->dev, config->platform.iommu); + struct msm_mmu *mmu = msm_smmu_new(&pdev->dev, + MSM_SMMU_DOMAIN_UNSECURE); if (IS_ERR(mmu)) { ret = PTR_ERR(mmu); dev_err(dev->dev, "failed to init iommu: %d\n", ret); iommu_domain_free(config->platform.iommu); + } + + aspace = msm_gem_smmu_address_space_create(&pdev->dev, + mmu, "mdp5"); + if (IS_ERR(aspace)) { + ret = PTR_ERR(aspace); goto fail; } - ret = mmu->funcs->attach(mmu, iommu_ports, - ARRAY_SIZE(iommu_ports)); + mdp5_kms->aspace = aspace; + + ret = aspace->mmu->funcs->attach(aspace->mmu, NULL, 0); if (ret) { - dev_err(dev->dev, "failed to attach iommu: %d\n", ret); - mmu->funcs->destroy(mmu); + dev_err(&pdev->dev, "failed to attach iommu: %d\n", + ret); goto fail; } } else { - dev_info(dev->dev, "no iommu, fallback to phys " - "contig buffers for scanout\n"); - mmu = NULL; - } - mdp5_kms->mmu = mmu; - - mdp5_kms->id = msm_register_mmu(dev, mmu); - if (mdp5_kms->id < 0) { - ret = mdp5_kms->id; - dev_err(dev->dev, "failed to register mdp5 iommu: %d\n", ret); - goto fail; + dev_info(&pdev->dev, + "no iommu, fallback to phys contig buffers for scanout\n"); + aspace = NULL; } ret = modeset_init(mdp5_kms); diff -ruw linux-4.4.115/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.h linux-4.4.115-fbx/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.h --- linux-4.4.115/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.h 2019-01-22 16:16:23.503246407 +0100 @@ -36,8 +36,7 @@ /* mapper-id used to request GEM buffer mapped for scanout: */ - int id; - struct msm_mmu *mmu; + struct msm_gem_address_space *aspace; struct mdp5_smp *smp; struct mdp5_ctl_manager *ctlm; diff -ruw linux-4.4.115/drivers/gpu/drm/msm/mdp/mdp5/mdp5_plane.c linux-4.4.115-fbx/drivers/gpu/drm/msm/mdp/mdp5/mdp5_plane.c --- linux-4.4.115/drivers/gpu/drm/msm/mdp/mdp5/mdp5_plane.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/gpu/drm/msm/mdp/mdp5/mdp5_plane.c 2019-10-29 09:26:23.633203080 +0100 @@ -260,7 +260,7 @@ return 0; DBG("%s: prepare: FB[%u]", mdp5_plane->name, fb->base.id); - return msm_framebuffer_prepare(fb, mdp5_kms->id); + return msm_framebuffer_prepare(fb, mdp5_kms->aspace); } static void mdp5_plane_cleanup_fb(struct drm_plane *plane, @@ -274,7 +274,7 @@ return; DBG("%s: cleanup: FB[%u]", mdp5_plane->name, fb->base.id); - msm_framebuffer_cleanup(fb, mdp5_kms->id); + msm_framebuffer_cleanup(fb, mdp5_kms->aspace); } static int mdp5_plane_atomic_check(struct drm_plane *plane, @@ -400,13 +400,13 @@ MDP5_PIPE_SRC_STRIDE_B_P3(fb->pitches[3])); mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC0_ADDR(pipe), - msm_framebuffer_iova(fb, mdp5_kms->id, 0)); + msm_framebuffer_iova(fb, mdp5_kms->aspace, 0)); mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC1_ADDR(pipe), - msm_framebuffer_iova(fb, mdp5_kms->id, 1)); + msm_framebuffer_iova(fb, mdp5_kms->aspace, 1)); mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC2_ADDR(pipe), - msm_framebuffer_iova(fb, mdp5_kms->id, 2)); + msm_framebuffer_iova(fb, mdp5_kms->aspace, 2)); mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC3_ADDR(pipe), - msm_framebuffer_iova(fb, mdp5_kms->id, 3)); + msm_framebuffer_iova(fb, mdp5_kms->aspace, 3)); plane->fb = fb; } diff -ruw linux-4.4.115/drivers/gpu/drm/msm/mdp/mdp5/mdp5.xml.h linux-4.4.115-fbx/drivers/gpu/drm/msm/mdp/mdp5/mdp5.xml.h --- linux-4.4.115/drivers/gpu/drm/msm/mdp/mdp5/mdp5.xml.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/gpu/drm/msm/mdp/mdp5/mdp5.xml.h 2019-01-22 16:16:23.503246407 +0100 @@ -9,7 +9,7 @@ The rules-ng-ng source files this header was generated from are: - /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 676 bytes, from 2015-05-20 20:03:14) -- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2015-05-20 20:03:07) +- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2016-02-10 17:07:21) - /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2015-05-20 20:03:14) - /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2015-09-18 12:07:28) - /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 37194 bytes, from 2015-09-18 12:07:28) @@ -17,11 +17,12 @@ - /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2015-10-22 16:35:02) - /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2015-05-20 20:03:14) - /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2015-05-20 20:03:07) -- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 29154 bytes, from 2015-08-10 21:25:43) +- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 41472 bytes, from 2016-01-22 18:18:18) - /home/robclark/src/freedreno/envytools/rnndb/edp/edp.xml ( 10416 bytes, from 2015-05-20 20:03:14) Copyright (C) 2013-2015 by the following authors: - Rob Clark (robclark) +- Ilia Mirkin (imirkin) Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the diff -ruw linux-4.4.115/drivers/gpu/drm/msm/mdp/mdp_common.xml.h linux-4.4.115-fbx/drivers/gpu/drm/msm/mdp/mdp_common.xml.h --- linux-4.4.115/drivers/gpu/drm/msm/mdp/mdp_common.xml.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/gpu/drm/msm/mdp/mdp_common.xml.h 2019-01-22 16:16:23.503246407 +0100 @@ -9,7 +9,7 @@ The rules-ng-ng source files this header was generated from are: - /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 676 bytes, from 2015-05-20 20:03:14) -- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2015-05-20 20:03:07) +- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2016-02-10 17:07:21) - /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2015-05-20 20:03:14) - /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2015-09-18 12:07:28) - /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 37194 bytes, from 2015-09-18 12:07:28) @@ -17,11 +17,12 @@ - /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2015-10-22 16:35:02) - /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2015-05-20 20:03:14) - /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2015-05-20 20:03:07) -- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 29154 bytes, from 2015-08-10 21:25:43) +- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 41472 bytes, from 2016-01-22 18:18:18) - /home/robclark/src/freedreno/envytools/rnndb/edp/edp.xml ( 10416 bytes, from 2015-05-20 20:03:14) Copyright (C) 2013-2015 by the following authors: - Rob Clark (robclark) +- Ilia Mirkin (imirkin) Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the diff -ruw linux-4.4.115/drivers/gpu/drm/msm/mdp/mdp_format.c linux-4.4.115-fbx/drivers/gpu/drm/msm/mdp/mdp_format.c --- linux-4.4.115/drivers/gpu/drm/msm/mdp/mdp_format.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/gpu/drm/msm/mdp/mdp_format.c 2019-01-22 16:16:23.503246407 +0100 @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014 The Linux Foundation. All rights reserved. + * Copyright (c) 2014,2016 The Linux Foundation. All rights reserved. * Copyright (C) 2013 Red Hat * Author: Rob Clark * @@ -165,7 +165,11 @@ return i; } -const struct msm_format *mdp_get_format(struct msm_kms *kms, uint32_t format) +const struct msm_format *mdp_get_format( + struct msm_kms *kms, + uint32_t format, + const uint64_t *modifiers, + uint32_t modifiers_len) { int i; for (i = 0; i < ARRAY_SIZE(formats); i++) { diff -ruw linux-4.4.115/drivers/gpu/drm/msm/mdp/mdp_kms.h linux-4.4.115-fbx/drivers/gpu/drm/msm/mdp/mdp_kms.h --- linux-4.4.115/drivers/gpu/drm/msm/mdp/mdp_kms.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/gpu/drm/msm/mdp/mdp_kms.h 2019-01-22 16:16:23.503246407 +0100 @@ -98,7 +98,9 @@ #define MDP_FORMAT_IS_YUV(mdp_format) ((mdp_format)->is_yuv) uint32_t mdp_get_formats(uint32_t *formats, uint32_t max_formats, bool rgb_only); -const struct msm_format *mdp_get_format(struct msm_kms *kms, uint32_t format); +const struct msm_format *mdp_get_format(struct msm_kms *kms, + uint32_t format, const uint64_t *modifiers, + uint32_t modifiers_len); /* MDP capabilities */ #define MDP_CAP_SMP BIT(0) /* Shared Memory Pool */ diff -ruw linux-4.4.115/drivers/gpu/drm/msm/msm_atomic.c linux-4.4.115-fbx/drivers/gpu/drm/msm/msm_atomic.c --- linux-4.4.115/drivers/gpu/drm/msm/msm_atomic.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/gpu/drm/msm/msm_atomic.c 2019-10-29 09:26:23.633203080 +0100 @@ -1,4 +1,5 @@ /* + * Copyright (c) 2016-2018, The Linux Foundation. All rights reserved. * Copyright (C) 2014 Red Hat * Author: Rob Clark * @@ -18,6 +19,7 @@ #include "msm_drv.h" #include "msm_kms.h" #include "msm_gem.h" +#include "sde_trace.h" struct msm_commit { struct drm_device *dev; @@ -25,10 +27,9 @@ uint32_t fence; struct msm_fence_cb fence_cb; uint32_t crtc_mask; + struct kthread_work commit_work; }; -static void fence_cb(struct msm_fence_cb *cb); - /* block until specified crtcs are no longer pending update, and * atomically mark them as pending update */ @@ -59,75 +60,357 @@ spin_unlock(&priv->pending_crtcs_event.lock); } -static struct msm_commit *commit_init(struct drm_atomic_state *state) +static void commit_destroy(struct msm_commit *commit) { - struct msm_commit *c = kzalloc(sizeof(*c), GFP_KERNEL); + end_atomic(commit->dev->dev_private, commit->crtc_mask); + kfree(commit); +} - if (!c) - return NULL; +static void msm_atomic_wait_for_commit_done( + struct drm_device *dev, + struct drm_atomic_state *old_state, + int modeset_flags) +{ + struct drm_crtc *crtc; + struct msm_drm_private *priv = old_state->dev->dev_private; + struct msm_kms *kms = priv->kms; + int ncrtcs = old_state->dev->mode_config.num_crtc; + int i; - c->dev = state->dev; - c->state = state; + for (i = 0; i < ncrtcs; i++) { + int private_flags; - /* TODO we might need a way to indicate to run the cb on a - * different wq so wait_for_vblanks() doesn't block retiring - * bo's.. + crtc = old_state->crtcs[i]; + + if (!crtc || !crtc->state || !crtc->state->enable) + continue; + + /* If specified, only wait if requested flag is true */ + private_flags = crtc->state->adjusted_mode.private_flags; + if (modeset_flags && !(modeset_flags & private_flags)) + continue; + + /* Legacy cursor ioctls are completely unsynced, and userspace + * relies on that (by doing tons of cursor updates). */ + if (old_state->legacy_cursor_update) + continue; + + if (kms->funcs->wait_for_crtc_commit_done) + kms->funcs->wait_for_crtc_commit_done(kms, crtc); + } +} + +static void +msm_disable_outputs(struct drm_device *dev, struct drm_atomic_state *old_state) +{ + struct drm_connector *connector; + struct drm_connector_state *old_conn_state; + struct drm_crtc *crtc; + struct drm_crtc_state *old_crtc_state; + int i; + + SDE_ATRACE_BEGIN("msm_disable"); + for_each_connector_in_state(old_state, connector, old_conn_state, i) { + const struct drm_encoder_helper_funcs *funcs; + struct drm_encoder *encoder; + struct drm_crtc_state *old_crtc_state; + unsigned int crtc_idx; + + /* + * Shut down everything that's in the changeset and currently + * still on. So need to check the old, saved state. + */ + if (!old_conn_state->crtc) + continue; + + crtc_idx = drm_crtc_index(old_conn_state->crtc); + old_crtc_state = old_state->crtc_states[crtc_idx]; + + if (!old_crtc_state->active || + !drm_atomic_crtc_needs_modeset(old_conn_state->crtc->state)) + continue; + + encoder = old_conn_state->best_encoder; + + /* We shouldn't get this far if we didn't previously have + * an encoder.. but WARN_ON() rather than explode. + */ + if (WARN_ON(!encoder)) + continue; + + if (msm_is_mode_seamless( + &connector->encoder->crtc->state->mode)) + continue; + + funcs = encoder->helper_private; + + DRM_DEBUG_ATOMIC("disabling [ENCODER:%d:%s]\n", + encoder->base.id, encoder->name); + + /* + * Each encoder has at most one connector (since we always steal + * it away), so we won't call disable hooks twice. */ - INIT_FENCE_CB(&c->fence_cb, fence_cb); + drm_bridge_disable(encoder->bridge); + + /* Right function depends upon target state. */ + if (connector->state->crtc && funcs->prepare) + funcs->prepare(encoder); + else if (funcs->disable) + funcs->disable(encoder); + else + funcs->dpms(encoder, DRM_MODE_DPMS_OFF); - return c; + drm_bridge_post_disable(encoder->bridge); } -static void commit_destroy(struct msm_commit *c) + for_each_crtc_in_state(old_state, crtc, old_crtc_state, i) { + const struct drm_crtc_helper_funcs *funcs; + + /* Shut down everything that needs a full modeset. */ + if (!drm_atomic_crtc_needs_modeset(crtc->state)) + continue; + + if (!old_crtc_state->active) + continue; + + if (msm_is_mode_seamless(&crtc->state->mode)) + continue; + + funcs = crtc->helper_private; + + DRM_DEBUG_ATOMIC("disabling [CRTC:%d]\n", + crtc->base.id); + + /* Right function depends upon target state. */ + if (crtc->state->enable && funcs->prepare) + funcs->prepare(crtc); + else if (funcs->disable) + funcs->disable(crtc); + else + funcs->dpms(crtc, DRM_MODE_DPMS_OFF); + } + SDE_ATRACE_END("msm_disable"); +} + +static void +msm_crtc_set_mode(struct drm_device *dev, struct drm_atomic_state *old_state) +{ + struct drm_crtc *crtc; + struct drm_crtc_state *old_crtc_state; + struct drm_connector *connector; + struct drm_connector_state *old_conn_state; + int i; + + for_each_crtc_in_state(old_state, crtc, old_crtc_state, i) { + const struct drm_crtc_helper_funcs *funcs; + + if (!crtc->state->mode_changed) + continue; + + funcs = crtc->helper_private; + + if (crtc->state->enable && funcs->mode_set_nofb) { + DRM_DEBUG_ATOMIC("modeset on [CRTC:%d]\n", + crtc->base.id); + + funcs->mode_set_nofb(crtc); + } + } + + for_each_connector_in_state(old_state, connector, old_conn_state, i) { + const struct drm_encoder_helper_funcs *funcs; + struct drm_crtc_state *new_crtc_state; + struct drm_encoder *encoder; + struct drm_display_mode *mode, *adjusted_mode; + + if (!connector->state->best_encoder) + continue; + + encoder = connector->state->best_encoder; + funcs = encoder->helper_private; + new_crtc_state = connector->state->crtc->state; + mode = &new_crtc_state->mode; + adjusted_mode = &new_crtc_state->adjusted_mode; + + if (!new_crtc_state->mode_changed) + continue; + + DRM_DEBUG_ATOMIC("modeset on [ENCODER:%d:%s]\n", + encoder->base.id, encoder->name); + + /* + * Each encoder has at most one connector (since we always steal + * it away), so we won't call mode_set hooks twice. + */ + if (funcs->mode_set) + funcs->mode_set(encoder, mode, adjusted_mode); + + drm_bridge_mode_set(encoder->bridge, mode, adjusted_mode); + } +} + +/** + * msm_atomic_helper_commit_modeset_disables - modeset commit to disable outputs + * @dev: DRM device + * @old_state: atomic state object with old state structures + * + * This function shuts down all the outputs that need to be shut down and + * prepares them (if required) with the new mode. + * + * For compatibility with legacy crtc helpers this should be called before + * drm_atomic_helper_commit_planes(), which is what the default commit function + * does. But drivers with different needs can group the modeset commits together + * and do the plane commits at the end. This is useful for drivers doing runtime + * PM since planes updates then only happen when the CRTC is actually enabled. + */ +static void msm_atomic_helper_commit_modeset_disables(struct drm_device *dev, + struct drm_atomic_state *old_state) { - end_atomic(c->dev->dev_private, c->crtc_mask); - kfree(c); + msm_disable_outputs(dev, old_state); + + drm_atomic_helper_update_legacy_modeset_state(dev, old_state); + + msm_crtc_set_mode(dev, old_state); } -static void msm_atomic_wait_for_commit_done(struct drm_device *dev, +/** + * msm_atomic_helper_commit_modeset_enables - modeset commit to enable outputs + * @dev: DRM device + * @old_state: atomic state object with old state structures + * + * This function enables all the outputs with the new configuration which had to + * be turned off for the update. + * + * For compatibility with legacy crtc helpers this should be called after + * drm_atomic_helper_commit_planes(), which is what the default commit function + * does. But drivers with different needs can group the modeset commits together + * and do the plane commits at the end. This is useful for drivers doing runtime + * PM since planes updates then only happen when the CRTC is actually enabled. + */ +static void msm_atomic_helper_commit_modeset_enables(struct drm_device *dev, struct drm_atomic_state *old_state) { struct drm_crtc *crtc; - struct msm_drm_private *priv = old_state->dev->dev_private; + struct drm_crtc_state *old_crtc_state; + struct drm_connector *connector; + struct drm_connector_state *old_conn_state; + struct msm_drm_private *priv = dev->dev_private; struct msm_kms *kms = priv->kms; - int ncrtcs = old_state->dev->mode_config.num_crtc; + int bridge_enable_count = 0; int i; - for (i = 0; i < ncrtcs; i++) { - crtc = old_state->crtcs[i]; + SDE_ATRACE_BEGIN("msm_enable"); + for_each_crtc_in_state(old_state, crtc, old_crtc_state, i) { + const struct drm_crtc_helper_funcs *funcs; - if (!crtc) + /* Need to filter out CRTCs where only planes change. */ + if (!drm_atomic_crtc_needs_modeset(crtc->state)) continue; - if (!crtc->state->enable) + if (!crtc->state->active) continue; - /* Legacy cursor ioctls are completely unsynced, and userspace - * relies on that (by doing tons of cursor updates). */ - if (old_state->legacy_cursor_update) + if (msm_is_mode_seamless(&crtc->state->mode)) continue; - kms->funcs->wait_for_crtc_commit_done(kms, crtc); + funcs = crtc->helper_private; + + if (crtc->state->enable) { + DRM_DEBUG_ATOMIC("enabling [CRTC:%d]\n", + crtc->base.id); + + if (funcs->enable) + funcs->enable(crtc); + else + funcs->commit(crtc); + } + } + + /* ensure bridge/encoder updates happen on same vblank */ + msm_atomic_wait_for_commit_done(dev, old_state, + MSM_MODE_FLAG_VBLANK_PRE_MODESET); + + for_each_connector_in_state(old_state, connector, old_conn_state, i) { + const struct drm_encoder_helper_funcs *funcs; + struct drm_encoder *encoder; + + if (!connector->state->best_encoder) + continue; + + if (!connector->state->crtc->state->active || + !drm_atomic_crtc_needs_modeset( + connector->state->crtc->state)) + continue; + + encoder = connector->state->best_encoder; + funcs = encoder->helper_private; + + DRM_DEBUG_ATOMIC("enabling [ENCODER:%d:%s]\n", + encoder->base.id, encoder->name); + + /* + * Each encoder has at most one connector (since we always steal + * it away), so we won't call enable hooks twice. + */ + drm_bridge_pre_enable(encoder->bridge); + ++bridge_enable_count; + + if (funcs->enable) + funcs->enable(encoder); + else + funcs->commit(encoder); + } + + if (kms->funcs->commit) { + DRM_DEBUG_ATOMIC("triggering commit\n"); + kms->funcs->commit(kms, old_state); + } + + /* If no bridges were pre_enabled, skip iterating over them again */ + if (bridge_enable_count == 0) { + SDE_ATRACE_END("msm_enable"); + return; + } + + for_each_connector_in_state(old_state, connector, old_conn_state, i) { + struct drm_encoder *encoder; + + if (!connector->state->best_encoder) + continue; + + if (!connector->state->crtc->state->active || + !drm_atomic_crtc_needs_modeset( + connector->state->crtc->state)) + continue; + + encoder = connector->state->best_encoder; + + DRM_DEBUG_ATOMIC("bridge enable enabling [ENCODER:%d:%s]\n", + encoder->base.id, encoder->name); + + drm_bridge_enable(encoder->bridge); } + SDE_ATRACE_END("msm_enable"); } /* The (potentially) asynchronous part of the commit. At this point * nothing can fail short of armageddon. */ -static void complete_commit(struct msm_commit *c) +static void complete_commit(struct msm_commit *commit) { - struct drm_atomic_state *state = c->state; + struct drm_atomic_state *state = commit->state; struct drm_device *dev = state->dev; struct msm_drm_private *priv = dev->dev_private; struct msm_kms *kms = priv->kms; kms->funcs->prepare_commit(kms, state); - drm_atomic_helper_commit_modeset_disables(dev, state); + msm_atomic_helper_commit_modeset_disables(dev, state); drm_atomic_helper_commit_planes(dev, state, false); - drm_atomic_helper_commit_modeset_enables(dev, state); + msm_atomic_helper_commit_modeset_enables(dev, state); /* NOTE: _wait_for_vblanks() only waits for vblank on * enabled CRTCs. So we end up faulting when disabling @@ -142,7 +425,7 @@ * not be critical path) */ - msm_atomic_wait_for_commit_done(dev, state); + msm_atomic_wait_for_commit_done(dev, state, 0); drm_atomic_helper_cleanup_planes(dev, state); @@ -150,38 +433,109 @@ drm_atomic_state_free(state); - commit_destroy(c); + commit_destroy(commit); } +static int msm_atomic_commit_dispatch(struct drm_device *dev, + struct drm_atomic_state *state, struct msm_commit *commit); + static void fence_cb(struct msm_fence_cb *cb) { - struct msm_commit *c = + struct msm_commit *commit = container_of(cb, struct msm_commit, fence_cb); - complete_commit(c); + int ret = -EINVAL; + + ret = msm_atomic_commit_dispatch(commit->dev, commit->state, commit); + if (ret) { + DRM_ERROR("%s: atomic commit failed\n", __func__); + drm_atomic_state_free(commit->state); + commit_destroy(commit); + } } -static void add_fb(struct msm_commit *c, struct drm_framebuffer *fb) +static void _msm_drm_commit_work_cb(struct kthread_work *work) { - struct drm_gem_object *obj = msm_framebuffer_bo(fb, 0); - c->fence = max(c->fence, msm_gem_fence(to_msm_bo(obj), MSM_PREP_READ)); + struct msm_commit *commit = NULL; + + if (!work) { + DRM_ERROR("%s: Invalid commit work data!\n", __func__); + return; } -int msm_atomic_check(struct drm_device *dev, - struct drm_atomic_state *state) + commit = container_of(work, struct msm_commit, commit_work); + + SDE_ATRACE_BEGIN("complete_commit"); + complete_commit(commit); + SDE_ATRACE_END("complete_commit"); +} + +static struct msm_commit *commit_init(struct drm_atomic_state *state) { - int ret; + struct msm_commit *commit = kzalloc(sizeof(*commit), GFP_KERNEL); - /* - * msm ->atomic_check can update ->mode_changed for pixel format - * changes, hence must be run before we check the modeset changes. + if (!commit) { + DRM_ERROR("invalid commit\n"); + return ERR_PTR(-ENOMEM); + } + + commit->dev = state->dev; + commit->state = state; + + /* TODO we might need a way to indicate to run the cb on a + * different wq so wait_for_vblanks() doesn't block retiring + * bo's.. */ - ret = drm_atomic_helper_check_planes(dev, state); - if (ret) - return ret; + INIT_FENCE_CB(&commit->fence_cb, fence_cb); + init_kthread_work(&commit->commit_work, _msm_drm_commit_work_cb); - ret = drm_atomic_helper_check_modeset(dev, state); - if (ret) - return ret; + return commit; +} + +static void commit_set_fence(struct msm_commit *commit, + struct drm_framebuffer *fb) +{ + struct drm_gem_object *obj = msm_framebuffer_bo(fb, 0); + commit->fence = max(commit->fence, + msm_gem_fence(to_msm_bo(obj), MSM_PREP_READ)); +} + +/* Start display thread function */ +static int msm_atomic_commit_dispatch(struct drm_device *dev, + struct drm_atomic_state *state, struct msm_commit *commit) +{ + struct msm_drm_private *priv = dev->dev_private; + struct drm_crtc *crtc = NULL; + struct drm_crtc_state *crtc_state = NULL; + int ret = -EINVAL, i = 0, j = 0; + + for_each_crtc_in_state(state, crtc, crtc_state, i) { + for (j = 0; j < priv->num_crtcs; j++) { + if (priv->disp_thread[j].crtc_id == + crtc->base.id) { + if (priv->disp_thread[j].thread) { + queue_kthread_work( + &priv->disp_thread[j].worker, + &commit->commit_work); + /* only return zero if work is + * queued successfully. + */ + ret = 0; + } else { + DRM_ERROR(" Error for crtc_id: %d\n", + priv->disp_thread[j].crtc_id); + } + break; + } + } + /* + * TODO: handle cases where there will be more than + * one crtc per commit cycle. Remove this check then. + * Current assumption is there will be only one crtc + * per commit cycle. + */ + if (j < priv->num_crtcs) + break; + } return ret; } @@ -192,9 +546,8 @@ * @state: the driver state object * @async: asynchronous commit * - * This function commits a with drm_atomic_helper_check() pre-validated state - * object. This can still fail when e.g. the framebuffer reservation fails. For - * now this doesn't implement asynchronous commits. + * This function commits with drm_atomic_helper_check() pre-validated state + * object. This can still fail when e.g. the framebuffer reservation fails. * * RETURNS * Zero for success or -errno. @@ -202,19 +555,29 @@ int msm_atomic_commit(struct drm_device *dev, struct drm_atomic_state *state, bool async) { + struct msm_drm_private *priv = dev->dev_private; int nplanes = dev->mode_config.num_total_plane; int ncrtcs = dev->mode_config.num_crtc; ktime_t timeout; - struct msm_commit *c; + struct msm_commit *commit; int i, ret; + if (!priv || priv->shutdown_in_progress) { + DRM_ERROR("priv is null or shutdown is in-progress\n"); + return -EINVAL; + } + + SDE_ATRACE_BEGIN("atomic_commit"); ret = drm_atomic_helper_prepare_planes(dev, state); - if (ret) + if (ret) { + SDE_ATRACE_END("atomic_commit"); return ret; + } - c = commit_init(state); - if (!c) { - ret = -ENOMEM; + commit = commit_init(state); + if (IS_ERR_OR_NULL(commit)) { + ret = PTR_ERR(commit); + DRM_ERROR("commit_init failed: %d\n", ret); goto error; } @@ -225,7 +588,7 @@ struct drm_crtc *crtc = state->crtcs[i]; if (!crtc) continue; - c->crtc_mask |= (1 << drm_crtc_index(crtc)); + commit->crtc_mask |= (1 << drm_crtc_index(crtc)); } /* @@ -239,16 +602,17 @@ continue; if ((plane->state->fb != new_state->fb) && new_state->fb) - add_fb(c, new_state->fb); + commit_set_fence(commit, new_state->fb); } /* * Wait for pending updates on any of the same crtc's and then * mark our set of crtc's as busy: */ - ret = start_atomic(dev->dev_private, c->crtc_mask); + ret = start_atomic(dev->dev_private, commit->crtc_mask); if (ret) { - kfree(c); + DRM_ERROR("start_atomic failed: %d\n", ret); + commit_destroy(commit); goto error; } @@ -261,6 +625,16 @@ drm_atomic_helper_swap_state(dev, state); /* + * Provide the driver a chance to prepare for output fences. This is + * done after the point of no return, but before asynchronous commits + * are dispatched to work queues, so that the fence preparation is + * finished before the .atomic_commit returns. + */ + if (priv && priv->kms && priv->kms->funcs && + priv->kms->funcs->prepare_fence) + priv->kms->funcs->prepare_fence(priv->kms, state); + + /* * Everything below can be run asynchronously without the need to grab * any modeset locks at all under one conditions: It must be guaranteed * that the asynchronous work has either been cancelled (if the driver @@ -277,20 +651,23 @@ */ if (async) { - msm_queue_fence_cb(dev, &c->fence_cb, c->fence); + msm_queue_fence_cb(dev, &commit->fence_cb, commit->fence); + SDE_ATRACE_END("atomic_commit"); return 0; } timeout = ktime_add_ms(ktime_get(), 1000); /* uninterruptible wait */ - msm_wait_fence(dev, c->fence, &timeout, false); + msm_wait_fence(dev, commit->fence, &timeout, false); - complete_commit(c); + complete_commit(commit); + SDE_ATRACE_END("atomic_commit"); return 0; error: drm_atomic_helper_cleanup_planes(dev, state); + SDE_ATRACE_END("atomic_commit"); return ret; } diff -ruw linux-4.4.115/drivers/gpu/drm/msm/msm_drv.c linux-4.4.115-fbx/drivers/gpu/drm/msm/msm_drv.c --- linux-4.4.115/drivers/gpu/drm/msm/msm_drv.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/gpu/drm/msm/msm_drv.c 2019-01-22 16:16:23.507246443 +0100 @@ -1,4 +1,5 @@ /* + * Copyright (c) 2016-2018, The Linux Foundation. All rights reserved. * Copyright (C) 2013 Red Hat * Author: Rob Clark * @@ -15,9 +16,15 @@ * this program. If not, see . */ +#include #include "msm_drv.h" #include "msm_gpu.h" #include "msm_kms.h" +#include "sde_wb.h" + +#define TEARDOWN_DEADLOCK_RETRY_MAX 5 +#include "msm_gem.h" +#include "msm_mmu.h" static void msm_fb_output_poll_changed(struct drm_device *dev) { @@ -29,23 +36,10 @@ static const struct drm_mode_config_funcs mode_config_funcs = { .fb_create = msm_framebuffer_create, .output_poll_changed = msm_fb_output_poll_changed, - .atomic_check = msm_atomic_check, + .atomic_check = drm_atomic_helper_check, .atomic_commit = msm_atomic_commit, }; -int msm_register_mmu(struct drm_device *dev, struct msm_mmu *mmu) -{ - struct msm_drm_private *priv = dev->dev_private; - int idx = priv->num_mmus++; - - if (WARN_ON(idx >= ARRAY_SIZE(priv->mmus))) - return -EINVAL; - - priv->mmus[idx] = mmu; - - return idx; -} - #ifdef CONFIG_DRM_MSM_REGISTER_LOGGING static bool reglog = false; MODULE_PARM_DESC(reglog, "Enable register read/write logging"); @@ -94,15 +88,21 @@ } if (reglog) - printk(KERN_DEBUG "IO:region %s %p %08lx\n", dbgname, ptr, size); + dev_dbg(&pdev->dev, "IO:region %s %pK %08lx\n", + dbgname, ptr, size); return ptr; } +void msm_iounmap(struct platform_device *pdev, void __iomem *addr) +{ + devm_iounmap(&pdev->dev, addr); +} + void msm_writel(u32 data, void __iomem *addr) { if (reglog) - printk(KERN_DEBUG "IO:W %p %08x\n", addr, data); + pr_debug("IO:W %pK %08x\n", addr, data); writel(data, addr); } @@ -110,7 +110,7 @@ { u32 val = readl(addr); if (reglog) - printk(KERN_ERR "IO:R %p %08x\n", addr, val); + pr_err("IO:R %pK %08x\n", addr, val); return val; } @@ -120,7 +120,7 @@ bool enable; }; -static void vblank_ctrl_worker(struct work_struct *work) +static void vblank_ctrl_worker(struct kthread_work *work) { struct msm_vblank_ctrl *vbl_ctrl = container_of(work, struct msm_vblank_ctrl, work); @@ -129,12 +129,16 @@ struct msm_kms *kms = priv->kms; struct vblank_event *vbl_ev, *tmp; unsigned long flags; + LIST_HEAD(tmp_head); spin_lock_irqsave(&vbl_ctrl->lock, flags); list_for_each_entry_safe(vbl_ev, tmp, &vbl_ctrl->event_list, node) { list_del(&vbl_ev->node); + list_add_tail(&vbl_ev->node, &tmp_head); + } spin_unlock_irqrestore(&vbl_ctrl->lock, flags); + list_for_each_entry_safe(vbl_ev, tmp, &tmp_head, node) { if (vbl_ev->enable) kms->funcs->enable_vblank(kms, priv->crtcs[vbl_ev->crtc_id]); @@ -143,11 +147,7 @@ priv->crtcs[vbl_ev->crtc_id]); kfree(vbl_ev); - - spin_lock_irqsave(&vbl_ctrl->lock, flags); } - - spin_unlock_irqrestore(&vbl_ctrl->lock, flags); } static int vblank_ctrl_queue_work(struct msm_drm_private *priv, @@ -168,7 +168,7 @@ list_add_tail(&vbl_ev->node, &vbl_ctrl->event_list); spin_unlock_irqrestore(&vbl_ctrl->lock, flags); - queue_work(priv->wq, &vbl_ctrl->work); + queue_kthread_work(&priv->disp_thread[crtc_id].worker, &vbl_ctrl->work); return 0; } @@ -180,21 +180,32 @@ static int msm_unload(struct drm_device *dev) { struct msm_drm_private *priv = dev->dev_private; + struct platform_device *pdev = dev->platformdev; struct msm_kms *kms = priv->kms; struct msm_gpu *gpu = priv->gpu; struct msm_vblank_ctrl *vbl_ctrl = &priv->vblank_ctrl; struct vblank_event *vbl_ev, *tmp; + int i; /* We must cancel and cleanup any pending vblank enable/disable * work before drm_irq_uninstall() to avoid work re-enabling an * irq after uninstall has disabled it. */ - cancel_work_sync(&vbl_ctrl->work); + flush_kthread_work(&vbl_ctrl->work); list_for_each_entry_safe(vbl_ev, tmp, &vbl_ctrl->event_list, node) { list_del(&vbl_ev->node); kfree(vbl_ev); } + /* clean up display commit worker threads */ + for (i = 0; i < priv->num_crtcs; i++) { + if (priv->disp_thread[i].thread) { + flush_kthread_worker(&priv->disp_thread[i].worker); + kthread_stop(priv->disp_thread[i].thread); + priv->disp_thread[i].thread = NULL; + } + } + drm_kms_helper_poll_fini(dev); drm_mode_config_cleanup(dev); drm_vblank_cleanup(dev); @@ -213,6 +224,10 @@ if (gpu) { mutex_lock(&dev->struct_mutex); + /* + * XXX what do we do here? + * pm_runtime_enable(&pdev->dev); + */ gpu->funcs->pm_suspend(gpu); mutex_unlock(&dev->struct_mutex); gpu->funcs->destroy(gpu); @@ -226,6 +241,11 @@ priv->vram.paddr, &attrs); } + sde_dbg_destroy(); + + sde_power_client_destroy(&priv->phandle, priv->pclient); + sde_power_resource_deinit(pdev, &priv->phandle); + component_unbind_all(dev->dev, dev); dev->dev_private = NULL; @@ -235,26 +255,26 @@ return 0; } +#define KMS_MDP4 0 +#define KMS_SDE 1 + static int get_mdp_ver(struct platform_device *pdev) { #ifdef CONFIG_OF static const struct of_device_id match_types[] = { { - .compatible = "qcom,mdss_mdp", - .data = (void *)5, - }, { - /* end node */ - } }; + .compatible = "qcom,sde-kms", + .data = (void *)KMS_SDE, + }, + {} }; struct device *dev = &pdev->dev; const struct of_device_id *match; match = of_match_node(match_types, dev->of_node); if (match) return (int)(unsigned long)match->data; #endif - return 4; + return KMS_MDP4; } -#include - static int msm_init_vram(struct drm_device *dev) { struct msm_drm_private *priv = dev->dev_private; @@ -307,6 +327,7 @@ priv->vram.size = size; drm_mm_init(&priv->vram.mm, 0, (size >> PAGE_SHIFT) - 1); + spin_lock_init(&priv->vram.lock); dma_set_attr(DMA_ATTR_NO_KERNEL_MAPPING, &attrs); dma_set_attr(DMA_ATTR_WRITE_COMBINE, &attrs); @@ -330,12 +351,39 @@ return ret; } +#ifdef CONFIG_OF +static int msm_component_bind_all(struct device *dev, + struct drm_device *drm_dev) +{ + int ret; + + ret = component_bind_all(dev, drm_dev); + if (ret) + DRM_ERROR("component_bind_all failed: %d\n", ret); + + return ret; +} +#else +static int msm_component_bind_all(struct device *dev, + struct drm_device *drm_dev) +{ + return 0; +} +#endif + +static int msm_power_enable_wrapper(void *handle, void *client, bool enable) +{ + return sde_power_resource_enable(handle, client, enable); +} + static int msm_load(struct drm_device *dev, unsigned long flags) { struct platform_device *pdev = dev->platformdev; struct msm_drm_private *priv; struct msm_kms *kms; - int ret; + struct sde_dbg_power_ctrl dbg_power_ctrl = { NULL }; + int ret, i; + struct sched_param param; priv = kzalloc(sizeof(*priv), GFP_KERNEL); if (!priv) { @@ -345,22 +393,38 @@ dev->dev_private = priv; - priv->wq = alloc_ordered_workqueue("msm", 0); + priv->wq = alloc_ordered_workqueue("msm_drm", 0); init_waitqueue_head(&priv->fence_event); init_waitqueue_head(&priv->pending_crtcs_event); + INIT_LIST_HEAD(&priv->client_event_list); INIT_LIST_HEAD(&priv->inactive_list); INIT_LIST_HEAD(&priv->fence_cbs); INIT_LIST_HEAD(&priv->vblank_ctrl.event_list); - INIT_WORK(&priv->vblank_ctrl.work, vblank_ctrl_worker); + init_kthread_work(&priv->vblank_ctrl.work, vblank_ctrl_worker); spin_lock_init(&priv->vblank_ctrl.lock); + hash_init(priv->mn_hash); + mutex_init(&priv->mn_lock); drm_mode_config_init(dev); platform_set_drvdata(pdev, dev); + ret = sde_power_resource_init(pdev, &priv->phandle); + if (ret) { + pr_err("sde power resource init failed\n"); + goto fail; + } + + priv->pclient = sde_power_client_create(&priv->phandle, "sde"); + if (IS_ERR_OR_NULL(priv->pclient)) { + pr_err("sde power client create failed\n"); + ret = -EINVAL; + goto fail; + } + /* Bind all our sub-components: */ - ret = component_bind_all(dev->dev, dev); + ret = msm_component_bind_all(dev->dev, dev); if (ret) return ret; @@ -368,12 +432,22 @@ if (ret) goto fail; + dbg_power_ctrl.handle = &priv->phandle; + dbg_power_ctrl.client = priv->pclient; + dbg_power_ctrl.enable_fn = msm_power_enable_wrapper; + ret = sde_dbg_init(dev->primary->debugfs_root, &pdev->dev, + &dbg_power_ctrl); + if (ret) { + dev_err(dev->dev, "failed to init sde dbg: %d\n", ret); + goto fail; + } + switch (get_mdp_ver(pdev)) { - case 4: + case KMS_MDP4: kms = mdp4_kms_init(dev); break; - case 5: - kms = mdp5_kms_init(dev); + case KMS_SDE: + kms = sde_kms_init(dev); break; default: kms = ERR_PTR(-ENODEV); @@ -387,21 +461,55 @@ * and (for example) use dmabuf/prime to share buffers with * imx drm driver on iMX5 */ + priv->kms = NULL; dev_err(dev->dev, "failed to load kms\n"); ret = PTR_ERR(kms); goto fail; } priv->kms = kms; - - if (kms) { pm_runtime_enable(dev->dev); + + if (kms && kms->funcs && kms->funcs->hw_init) { ret = kms->funcs->hw_init(kms); if (ret) { dev_err(dev->dev, "kms hw init failed: %d\n", ret); goto fail; } } + /** + * this priority was found during empiric testing to have appropriate + * realtime scheduling to process display updates and interact with + * other real time and normal priority task + */ + param.sched_priority = 16; + /* initialize commit thread structure */ + for (i = 0; i < priv->num_crtcs; i++) { + priv->disp_thread[i].crtc_id = priv->crtcs[i]->base.id; + init_kthread_worker(&priv->disp_thread[i].worker); + priv->disp_thread[i].dev = dev; + priv->disp_thread[i].thread = + kthread_run(kthread_worker_fn, + &priv->disp_thread[i].worker, + "crtc_commit:%d", + priv->disp_thread[i].crtc_id); + ret = sched_setscheduler(priv->disp_thread[i].thread, + SCHED_FIFO, ¶m); + if (ret) + pr_warn("display thread priority update failed: %d\n", + ret); + + if (IS_ERR(priv->disp_thread[i].thread)) { + dev_err(dev->dev, "failed to create kthread\n"); + priv->disp_thread[i].thread = NULL; + /* clean up previously created threads if any */ + for (i -= 1; i >= 0; i--) { + kthread_stop(priv->disp_thread[i].thread); + priv->disp_thread[i].thread = NULL; + } + goto fail; + } + } dev->mode_config.funcs = &mode_config_funcs; @@ -430,6 +538,15 @@ if (ret) goto fail; + /* perform subdriver post initialization */ + if (kms && kms->funcs && kms->funcs->postinit) { + ret = kms->funcs->postinit(kms); + if (ret) { + dev_err(dev->dev, "kms post init failed: %d\n", ret); + goto fail; + } + } + drm_kms_helper_poll_init(dev); return 0; @@ -439,6 +556,11 @@ return ret; } +#ifdef CONFIG_QCOM_KGSL +static void load_gpu(struct drm_device *dev) +{ +} +#else static void load_gpu(struct drm_device *dev) { static DEFINE_MUTEX(init_lock); @@ -451,47 +573,231 @@ mutex_unlock(&init_lock); } +#endif -static int msm_open(struct drm_device *dev, struct drm_file *file) +static struct msm_file_private *setup_pagetable(struct msm_drm_private *priv) { struct msm_file_private *ctx; + if (!priv || !priv->gpu) + return NULL; + + ctx = kzalloc(sizeof(*ctx), GFP_KERNEL); + if (!ctx) + return ERR_PTR(-ENOMEM); + + ctx->aspace = msm_gem_address_space_create_instance( + priv->gpu->aspace->mmu, "gpu", 0x100000000ULL, + TASK_SIZE_64 - 1); + + if (IS_ERR(ctx->aspace)) { + int ret = PTR_ERR(ctx->aspace); + + /* + * If dynamic domains are not supported, everybody uses the + * same pagetable + */ + if (ret != -EOPNOTSUPP) { + kfree(ctx); + return ERR_PTR(ret); + } + + ctx->aspace = priv->gpu->aspace; + } + + ctx->aspace->mmu->funcs->attach(ctx->aspace->mmu, NULL, 0); + return ctx; +} + +static int msm_open(struct drm_device *dev, struct drm_file *file) +{ + struct msm_file_private *ctx = NULL; + struct msm_drm_private *priv; + struct msm_kms *kms; + + if (!dev || !dev->dev_private) + return -ENODEV; + + priv = dev->dev_private; /* For now, load gpu on open.. to avoid the requirement of having * firmware in the initrd. */ load_gpu(dev); - ctx = kzalloc(sizeof(*ctx), GFP_KERNEL); - if (!ctx) - return -ENOMEM; + ctx = setup_pagetable(priv); + if (IS_ERR(ctx)) + return PTR_ERR(ctx); + + if (ctx) { + INIT_LIST_HEAD(&ctx->counters); + msm_submitqueue_init(ctx); + } file->driver_priv = ctx; + kms = priv->kms; + + if (kms && kms->funcs && kms->funcs->postopen) + kms->funcs->postopen(kms, file); + return 0; } static void msm_preclose(struct drm_device *dev, struct drm_file *file) { struct msm_drm_private *priv = dev->dev_private; - struct msm_file_private *ctx = file->driver_priv; struct msm_kms *kms = priv->kms; - if (kms) + if (kms && kms->funcs && kms->funcs->preclose) kms->funcs->preclose(kms, file); +} - mutex_lock(&dev->struct_mutex); - if (ctx == priv->lastctx) - priv->lastctx = NULL; - mutex_unlock(&dev->struct_mutex); +static void msm_postclose(struct drm_device *dev, struct drm_file *file) +{ + struct msm_drm_private *priv = dev->dev_private; + struct msm_file_private *ctx = file->driver_priv; + struct msm_kms *kms = priv->kms; + + if (kms && kms->funcs && kms->funcs->postclose) + kms->funcs->postclose(kms, file); + + if (!ctx) + return; + + msm_submitqueue_close(ctx); + + if (priv->gpu) { + msm_gpu_cleanup_counters(priv->gpu, ctx); + + if (ctx->aspace && ctx->aspace != priv->gpu->aspace) { + ctx->aspace->mmu->funcs->detach(ctx->aspace->mmu); + msm_gem_address_space_put(ctx->aspace); + } + } kfree(ctx); } +static int msm_disable_all_modes_commit( + struct drm_device *dev, + struct drm_atomic_state *state) +{ + struct drm_plane *plane; + struct drm_crtc *crtc; + unsigned plane_mask; + int ret; + + plane_mask = 0; + drm_for_each_plane(plane, dev) { + struct drm_plane_state *plane_state; + + plane_state = drm_atomic_get_plane_state(state, plane); + if (IS_ERR(plane_state)) { + ret = PTR_ERR(plane_state); + goto fail; + } + + plane_state->rotation = BIT(DRM_ROTATE_0); + + plane->old_fb = plane->fb; + plane_mask |= 1 << drm_plane_index(plane); + + /* disable non-primary: */ + if (plane->type == DRM_PLANE_TYPE_PRIMARY) + continue; + + DRM_DEBUG("disabling plane %d\n", plane->base.id); + + ret = __drm_atomic_helper_disable_plane(plane, plane_state); + if (ret != 0) + DRM_ERROR("error %d disabling plane %d\n", ret, + plane->base.id); + } + + drm_for_each_crtc(crtc, dev) { + struct drm_mode_set mode_set; + + memset(&mode_set, 0, sizeof(struct drm_mode_set)); + mode_set.crtc = crtc; + + DRM_DEBUG("disabling crtc %d\n", crtc->base.id); + + ret = __drm_atomic_helper_set_config(&mode_set, state); + if (ret != 0) + DRM_ERROR("error %d disabling crtc %d\n", ret, + crtc->base.id); + } + + DRM_DEBUG("committing disables\n"); + ret = drm_atomic_commit(state); + +fail: + drm_atomic_clean_old_fb(dev, plane_mask, ret); + DRM_DEBUG("disables result %d\n", ret); + return ret; +} + +/** + * msm_clear_all_modes - disables all planes and crtcs via an atomic commit + * based on restore_fbdev_mode_atomic in drm_fb_helper.c + * @dev: device pointer + * @Return: 0 on success, otherwise -error + */ +static int msm_disable_all_modes(struct drm_device *dev) +{ + struct drm_atomic_state *state; + int ret, i; + + state = drm_atomic_state_alloc(dev); + if (!state) + return -ENOMEM; + + state->acquire_ctx = dev->mode_config.acquire_ctx; + + for (i = 0; i < TEARDOWN_DEADLOCK_RETRY_MAX; i++) { + ret = msm_disable_all_modes_commit(dev, state); + if (ret != -EDEADLK) + break; + drm_atomic_state_clear(state); + drm_atomic_legacy_backoff(state); + } + + /* on successful atomic commit state ownership transfers to framework */ + if (ret != 0) + drm_atomic_state_free(state); + + return ret; +} + static void msm_lastclose(struct drm_device *dev) { struct msm_drm_private *priv = dev->dev_private; - if (priv->fbdev) + struct msm_kms *kms = priv->kms; + int i; + + /* + * clean up vblank disable immediately as this is the last close. + */ + for (i = 0; i < dev->num_crtcs; i++) { + struct drm_vblank_crtc *vblank = &dev->vblank[i]; + struct timer_list *disable_timer = &vblank->disable_timer; + + if (del_timer_sync(disable_timer)) + disable_timer->function(disable_timer->data); + } + + /* wait for pending vblank requests to be executed by worker thread */ + flush_workqueue(priv->wq); + + if (priv->fbdev) { drm_fb_helper_restore_fbdev_mode_unlocked(priv->fbdev); + } else { + drm_modeset_lock_all(dev); + msm_disable_all_modes(dev); + drm_modeset_unlock_all(dev); + if (kms && kms->funcs && kms->funcs->lastclose) + kms->funcs->lastclose(kms); + } } static irqreturn_t msm_irq(int irq, void *arg) @@ -533,7 +839,7 @@ struct msm_kms *kms = priv->kms; if (!kms) return -ENXIO; - DBG("dev=%p, crtc=%u", dev, pipe); + DBG("dev=%pK, crtc=%u", dev, pipe); return vblank_ctrl_queue_work(priv, pipe, true); } @@ -543,7 +849,7 @@ struct msm_kms *kms = priv->kms; if (!kms) return; - DBG("dev=%p, crtc=%u", dev, pipe); + DBG("dev=%pK, crtc=%u", dev, pipe); vblank_ctrl_queue_work(priv, pipe, false); } @@ -559,12 +865,21 @@ if (gpu) { seq_printf(m, "%s Status:\n", gpu->name); + pm_runtime_get_sync(&gpu->pdev->dev); gpu->funcs->show(gpu, m); + pm_runtime_put_sync(&gpu->pdev->dev); } return 0; } +static int msm_snapshot_show(struct drm_device *dev, struct seq_file *m) +{ + struct msm_drm_private *priv = dev->dev_private; + + return msm_snapshot_write(priv->gpu, m); +} + static int msm_gem_show(struct drm_device *dev, struct seq_file *m) { struct msm_drm_private *priv = dev->dev_private; @@ -629,11 +944,22 @@ return ret; } +static int show_unlocked(struct seq_file *m, void *arg) +{ + struct drm_info_node *node = (struct drm_info_node *) m->private; + struct drm_device *dev = node->minor->dev; + int (*show)(struct drm_device *dev, struct seq_file *m) = + node->info_ent->data; + + return show(dev, m); +} + static struct drm_info_list msm_debugfs_list[] = { {"gpu", show_locked, 0, msm_gpu_show}, {"gem", show_locked, 0, msm_gem_show}, { "mm", show_locked, 0, msm_mm_show }, { "fb", show_locked, 0, msm_fb_show }, + { "snapshot", show_unlocked, 0, msm_snapshot_show }, }; static int late_init_minor(struct drm_minor *minor) @@ -707,14 +1033,23 @@ ktime_t *timeout , bool interruptible) { struct msm_drm_private *priv = dev->dev_private; + struct msm_gpu *gpu = priv->gpu; + int index = FENCE_RING(fence); + uint32_t submitted; int ret; - if (!priv->gpu) - return 0; + if (!gpu) + return -ENXIO; - if (fence > priv->gpu->submitted_fence) { + if (index > MSM_GPU_MAX_RINGS || index >= gpu->nr_rings || + !gpu->rb[index]) + return -EINVAL; + + submitted = gpu->funcs->submitted_fence(gpu, gpu->rb[index]); + + if (fence > submitted) { DRM_ERROR("waiting on invalid fence: %u (of %u)\n", - fence, priv->gpu->submitted_fence); + fence, submitted); return -EINVAL; } @@ -744,7 +1079,7 @@ if (ret == 0) { DBG("timeout waiting for fence: %u (completed: %u)", - fence, priv->completed_fence); + fence, priv->completed_fence[index]); ret = -ETIMEDOUT; } else if (ret != -ERESTARTSYS) { ret = 0; @@ -758,12 +1093,13 @@ struct msm_fence_cb *cb, uint32_t fence) { struct msm_drm_private *priv = dev->dev_private; + int index = FENCE_RING(fence); int ret = 0; mutex_lock(&dev->struct_mutex); if (!list_empty(&cb->work.entry)) { ret = -EINVAL; - } else if (fence > priv->completed_fence) { + } else if (fence > priv->completed_fence[index]) { cb->fence = fence; list_add_tail(&cb->work.entry, &priv->fence_cbs); } else { @@ -778,22 +1114,22 @@ void msm_update_fence(struct drm_device *dev, uint32_t fence) { struct msm_drm_private *priv = dev->dev_private; + struct msm_fence_cb *cb, *tmp; + int index = FENCE_RING(fence); - mutex_lock(&dev->struct_mutex); - priv->completed_fence = max(fence, priv->completed_fence); - - while (!list_empty(&priv->fence_cbs)) { - struct msm_fence_cb *cb; - - cb = list_first_entry(&priv->fence_cbs, - struct msm_fence_cb, work.entry); + if (index >= MSM_GPU_MAX_RINGS) + return; - if (cb->fence > priv->completed_fence) - break; + mutex_lock(&dev->struct_mutex); + priv->completed_fence[index] = max(fence, priv->completed_fence[index]); + list_for_each_entry_safe(cb, tmp, &priv->fence_cbs, work.entry) { + if (COMPARE_FENCE_LTE(cb->fence, + priv->completed_fence[index])) { list_del_init(&cb->work.entry); queue_work(priv->wq, &cb->work); } + } mutex_unlock(&dev->struct_mutex); @@ -845,6 +1181,20 @@ args->flags, &args->handle); } +static int msm_ioctl_gem_svm_new(struct drm_device *dev, void *data, + struct drm_file *file) +{ + struct drm_msm_gem_svm_new *args = data; + + if (args->flags & ~MSM_BO_FLAGS) { + DRM_ERROR("invalid flags: %08x\n", args->flags); + return -EINVAL; + } + + return msm_gem_svm_new_handle(dev, file, args->hostptr, args->size, + args->flags, &args->handle); +} + static inline ktime_t to_ktime(struct drm_msm_timespec timeout) { return ktime_set(timeout.tv_sec, timeout.tv_nsec); @@ -897,17 +1247,49 @@ { struct drm_msm_gem_info *args = data; struct drm_gem_object *obj; + struct msm_gem_object *msm_obj; + struct msm_file_private *ctx = file->driver_priv; int ret = 0; - if (args->pad) + if (args->flags & ~MSM_INFO_FLAGS) return -EINVAL; obj = drm_gem_object_lookup(dev, file, args->handle); if (!obj) return -ENOENT; + msm_obj = to_msm_bo(obj); + if (args->flags & MSM_INFO_IOVA) { + struct msm_gem_address_space *aspace = NULL; + struct msm_drm_private *priv = dev->dev_private; + uint64_t iova; + + if (msm_obj->flags & MSM_BO_SECURE && priv->gpu) + aspace = priv->gpu->secure_aspace; + else if (ctx) + aspace = ctx->aspace; + + if (!aspace) { + ret = -EINVAL; + goto out; + } + + ret = msm_gem_get_iova(obj, aspace, &iova); + if (!ret) + args->offset = iova; + } else { + if (msm_obj->flags & MSM_BO_SVM) { + /* + * Offset for an SVM object is not needed as they are + * already mmap'ed before the SVM ioctl is invoked. + */ + ret = -EACCES; + goto out; + } args->offset = msm_gem_mmap_offset(obj); + } +out: drm_gem_object_unreference_unlocked(obj); return ret; @@ -917,16 +1299,495 @@ struct drm_file *file) { struct drm_msm_wait_fence *args = data; - ktime_t timeout = to_ktime(args->timeout); + ktime_t timeout; + if (args->pad) { DRM_ERROR("invalid pad: %08x\n", args->pad); return -EINVAL; } + /* + * Special case - if the user passes a timeout of 0.0 just return the + * current fence status (0 for retired, -EBUSY for active) with no + * accompanying kernel logs. This can be a poor man's way of + * determining the status of a fence. + */ + if (args->timeout.tv_sec == 0 && args->timeout.tv_nsec == 0) + return msm_wait_fence(dev, args->fence, NULL, true); + + timeout = to_ktime(args->timeout); return msm_wait_fence(dev, args->fence, &timeout, true); } +static int msm_event_supported(struct drm_device *dev, + struct drm_msm_event_req *req) +{ + int ret = -EINVAL; + struct drm_mode_object *arg_obj; + struct drm_crtc *crtc; + + arg_obj = drm_mode_object_find(dev, req->object_id, req->object_type); + if (!arg_obj) + return -ENOENT; + + if (arg_obj->type == DRM_MODE_OBJECT_CRTC) { + crtc = obj_to_crtc(arg_obj); + req->index = drm_crtc_index(crtc); + } + + switch (req->event) { + case DRM_EVENT_VBLANK: + case DRM_EVENT_HISTOGRAM: + case DRM_EVENT_AD: + if (arg_obj->type == DRM_MODE_OBJECT_CRTC) + ret = 0; + break; + default: + break; + } + return ret; +} + +static void msm_vblank_read_cb(struct drm_pending_event *e) +{ + struct drm_pending_vblank_event *vblank; + struct msm_drm_private *priv; + struct drm_file *file_priv; + struct drm_device *dev; + struct msm_drm_event *v; + int ret = 0; + bool need_vblank = false; + + if (!e) { + DRM_ERROR("invalid pending event payload\n"); + return; + } + + vblank = container_of(e, struct drm_pending_vblank_event, base); + file_priv = vblank->base.file_priv; + dev = (file_priv && file_priv->minor) ? file_priv->minor->dev : NULL; + priv = (dev) ? dev->dev_private : NULL; + if (!priv) { + DRM_ERROR("invalid msm private\n"); + return; + } + + list_for_each_entry(v, &priv->client_event_list, base.link) { + if (v->base.file_priv != file_priv || + (v->event.type != DRM_EVENT_VBLANK && + v->event.type != DRM_EVENT_AD)) + continue; + need_vblank = true; + /** + * User-space client requests for N vsyncs when event + * requested is DRM_EVENT_AD. Once the count reaches zero, + * notify stop requesting for additional vsync's. + */ + if (v->event.type == DRM_EVENT_AD) { + if (vblank->event.user_data) + vblank->event.user_data--; + need_vblank = (vblank->event.user_data) ? true : false; + } + break; + } + + if (!need_vblank) { + kfree(vblank); + } else { + ret = drm_vblank_get(dev, vblank->pipe); + if (!ret) { + list_add(&vblank->base.link, &dev->vblank_event_list); + } else { + DRM_ERROR("vblank enable failed ret %d\n", ret); + kfree(vblank); + } + } +} + +static int msm_enable_vblank_event(struct drm_device *dev, + struct drm_msm_event_req *req, struct drm_file *file) +{ + struct drm_pending_vblank_event *e; + int ret = 0; + unsigned long flags; + struct drm_vblank_crtc *vblank; + + if (WARN_ON(req->index >= dev->num_crtcs)) + return -EINVAL; + + vblank = &dev->vblank[req->index]; + e = kzalloc(sizeof(*e), GFP_KERNEL); + if (!e) + return -ENOMEM; + + e->pipe = req->index; + e->base.pid = current->pid; + e->event.base.type = DRM_EVENT_VBLANK; + e->event.base.length = sizeof(e->event); + e->event.user_data = req->client_context; + e->base.event = &e->event.base; + e->base.file_priv = file; + e->base.destroy = msm_vblank_read_cb; + + ret = drm_vblank_get(dev, e->pipe); + if (ret) { + DRM_ERROR("failed to enable the vblank\n"); + goto free; + } + + spin_lock_irqsave(&dev->event_lock, flags); + if (!vblank->enabled) { + ret = -EINVAL; + goto err_unlock; + } + + if (file->event_space < sizeof(e->event)) { + ret = -EBUSY; + goto err_unlock; + } + file->event_space -= sizeof(e->event); + list_add_tail(&e->base.link, &dev->vblank_event_list); +err_unlock: + spin_unlock_irqrestore(&dev->event_lock, flags); +free: + if (ret) + kfree(e); + return ret; +} + +static int msm_enable_event(struct drm_device *dev, + struct drm_msm_event_req *req, struct drm_file *file) +{ + int ret = -EINVAL; + + switch (req->event) { + case DRM_EVENT_AD: + case DRM_EVENT_VBLANK: + ret = msm_enable_vblank_event(dev, req, file); + break; + default: + break; + } + return ret; +} + +static int msm_disable_vblank_event(struct drm_device *dev, + struct drm_msm_event_req *req, + struct drm_file *file) +{ + struct drm_pending_vblank_event *e, *t; + + list_for_each_entry_safe(e, t, &dev->vblank_event_list, base.link) { + if (e->pipe != req->index || file != e->base.file_priv) + continue; + list_del(&e->base.link); + drm_vblank_put(dev, req->index); + kfree(e); + } + return 0; +} + +static int msm_disable_event(struct drm_device *dev, + struct drm_msm_event_req *req, + struct drm_file *file) +{ + int ret = -EINVAL; + + switch (req->event) { + case DRM_EVENT_AD: + case DRM_EVENT_VBLANK: + ret = msm_disable_vblank_event(dev, req, file); + break; + default: + break; + } + return ret; +} + + +static int msm_ioctl_register_event(struct drm_device *dev, void *data, + struct drm_file *file) +{ + struct msm_drm_private *priv = dev->dev_private; + struct drm_msm_event_req *req_event = data; + struct msm_drm_event *client; + struct msm_drm_event *v; + unsigned long flag = 0; + bool dup_request = false; + int ret = 0; + + if (msm_event_supported(dev, req_event)) { + DRM_ERROR("unsupported event %x object %x object id %d\n", + req_event->event, req_event->object_type, + req_event->object_id); + return -EINVAL; + } + + spin_lock_irqsave(&dev->event_lock, flag); + list_for_each_entry(v, &priv->client_event_list, base.link) { + if (v->base.file_priv != file) + continue; + if (v->event.type == req_event->event && + v->info.object_id == req_event->object_id) { + DRM_ERROR("duplicate request for event %x obj id %d\n", + v->event.type, v->info.object_id); + dup_request = true; + break; + } + } + spin_unlock_irqrestore(&dev->event_lock, flag); + + if (dup_request) + return -EINVAL; + + client = kzalloc(sizeof(*client), GFP_KERNEL); + if (!client) + return -ENOMEM; + + client->base.file_priv = file; + client->base.pid = current->pid; + client->base.event = &client->event; + client->base.destroy = (void (*) (struct drm_pending_event *)) kfree; + client->event.type = req_event->event; + memcpy(&client->info, req_event, sizeof(client->info)); + + spin_lock_irqsave(&dev->event_lock, flag); + list_add_tail(&client->base.link, &priv->client_event_list); + spin_unlock_irqrestore(&dev->event_lock, flag); + + ret = msm_enable_event(dev, req_event, file); + if (ret) { + DRM_ERROR("failed to enable event %x object %x object id %d\n", + req_event->event, req_event->object_type, + req_event->object_id); + spin_lock_irqsave(&dev->event_lock, flag); + list_del(&client->base.link); + spin_unlock_irqrestore(&dev->event_lock, flag); + kfree(client); + } + return ret; +} + +static int msm_ioctl_deregister_event(struct drm_device *dev, void *data, + struct drm_file *file) +{ + struct msm_drm_private *priv = dev->dev_private; + struct drm_msm_event_req *req_event = data; + struct msm_drm_event *client = NULL; + struct msm_drm_event *v, *vt; + unsigned long flag = 0; + + if (msm_event_supported(dev, req_event)) { + DRM_ERROR("unsupported event %x object %x object id %d\n", + req_event->event, req_event->object_type, + req_event->object_id); + return -EINVAL; + } + + spin_lock_irqsave(&dev->event_lock, flag); + msm_disable_event(dev, req_event, file); + list_for_each_entry_safe(v, vt, &priv->client_event_list, base.link) { + if (v->event.type == req_event->event && + v->info.object_id == req_event->object_id && + v->base.file_priv == file) { + client = v; + list_del(&client->base.link); + client->base.destroy(&client->base); + break; + } + } + spin_unlock_irqrestore(&dev->event_lock, flag); + + return 0; +} + +static int msm_ioctl_gem_sync(struct drm_device *dev, void *data, + struct drm_file *file) +{ + + struct drm_msm_gem_sync *arg = data; + int i; + + for (i = 0; i < arg->nr_ops; i++) { + struct drm_msm_gem_syncop syncop; + struct drm_gem_object *obj; + int ret; + void __user *ptr = + (void __user *)(uintptr_t) + (arg->ops + (i * sizeof(syncop))); + + ret = copy_from_user(&syncop, ptr, sizeof(syncop)); + if (ret) + return -EFAULT; + + obj = drm_gem_object_lookup(dev, file, syncop.handle); + if (!obj) + return -ENOENT; + + msm_gem_sync(obj, syncop.op); + + drm_gem_object_unreference_unlocked(obj); + } + + return 0; +} + +void msm_send_crtc_notification(struct drm_crtc *crtc, + struct drm_event *event, u8 *payload) +{ + struct drm_device *dev = NULL; + struct msm_drm_private *priv = NULL; + unsigned long flags; + struct msm_drm_event *notify, *v; + int len = 0; + + if (!crtc || !event || !event->length || !payload) { + DRM_ERROR("err param crtc %pK event %pK len %d payload %pK\n", + crtc, event, ((event) ? (event->length) : -1), + payload); + return; + } + dev = crtc->dev; + priv = (dev) ? dev->dev_private : NULL; + if (!dev || !priv) { + DRM_ERROR("invalid dev %pK priv %pK\n", dev, priv); + return; + } + + spin_lock_irqsave(&dev->event_lock, flags); + list_for_each_entry(v, &priv->client_event_list, base.link) { + if (v->event.type != event->type || + crtc->base.id != v->info.object_id) + continue; + len = event->length + sizeof(struct drm_msm_event_resp); + if (v->base.file_priv->event_space < len) { + DRM_ERROR("Insufficient space to notify\n"); + continue; + } + notify = kzalloc(len, GFP_ATOMIC); + if (!notify) + continue; + notify->base.file_priv = v->base.file_priv; + notify->base.event = ¬ify->event; + notify->base.pid = v->base.pid; + notify->base.destroy = + (void (*)(struct drm_pending_event *)) kfree; + notify->event.type = v->event.type; + notify->event.length = len; + list_add(¬ify->base.link, + ¬ify->base.file_priv->event_list); + notify->base.file_priv->event_space -= len; + memcpy(¬ify->info, &v->info, sizeof(notify->info)); + memcpy(notify->data, payload, event->length); + wake_up_interruptible(¬ify->base.file_priv->event_wait); + } + spin_unlock_irqrestore(&dev->event_lock, flags); +} + +static int msm_ioctl_counter_get(struct drm_device *dev, void *data, + struct drm_file *file) +{ + struct msm_file_private *ctx = file->driver_priv; + struct msm_drm_private *priv = dev->dev_private; + + if (priv->gpu) + return msm_gpu_counter_get(priv->gpu, data, ctx); + + return -ENODEV; +} + +static int msm_ioctl_counter_put(struct drm_device *dev, void *data, + struct drm_file *file) +{ + struct msm_file_private *ctx = file->driver_priv; + struct msm_drm_private *priv = dev->dev_private; + + if (priv->gpu) + return msm_gpu_counter_put(priv->gpu, data, ctx); + + return -ENODEV; +} + +static int msm_ioctl_counter_read(struct drm_device *dev, void *data, + struct drm_file *file) +{ + struct msm_drm_private *priv = dev->dev_private; + + if (priv->gpu) + return msm_gpu_counter_read(priv->gpu, data); + + return -ENODEV; +} + + +static int msm_ioctl_submitqueue_new(struct drm_device *dev, void *data, + struct drm_file *file) +{ + struct drm_msm_submitqueue *args = data; + struct msm_drm_private *priv = dev->dev_private; + struct msm_gpu *gpu = priv->gpu; + + if (args->flags & ~MSM_SUBMITQUEUE_FLAGS) + return -EINVAL; + + if ((gpu->nr_rings > 1) && + (!file->is_master && args->prio == 0)) { + DRM_ERROR("Only DRM master can set highest priority ringbuffer\n"); + return -EPERM; + } + + if (args->flags & MSM_SUBMITQUEUE_BYPASS_QOS_TIMEOUT && + !capable(CAP_SYS_ADMIN)) { + DRM_ERROR( + "Only CAP_SYS_ADMIN processes can bypass the timer\n"); + return -EPERM; + } + + return msm_submitqueue_create(file->driver_priv, args->prio, + args->flags, &args->id); +} + +static int msm_ioctl_submitqueue_query(struct drm_device *dev, void *data, + struct drm_file *file) +{ + struct drm_msm_submitqueue_query *args = data; + void __user *ptr = (void __user *)(uintptr_t) args->data; + + return msm_submitqueue_query(file->driver_priv, args->id, + args->param, ptr, args->len); +} + +static int msm_ioctl_submitqueue_close(struct drm_device *dev, void *data, + struct drm_file *file) +{ + struct drm_msm_submitqueue *args = data; + + return msm_submitqueue_remove(file->driver_priv, args->id); +} + +int msm_release(struct inode *inode, struct file *filp) +{ + struct drm_file *file_priv = filp->private_data; + struct drm_minor *minor = file_priv->minor; + struct drm_device *dev = minor->dev; + struct msm_drm_private *priv = dev->dev_private; + struct msm_drm_event *v, *vt; + unsigned long flags; + + spin_lock_irqsave(&dev->event_lock, flags); + list_for_each_entry_safe(v, vt, &priv->client_event_list, base.link) { + if (v->base.file_priv != file_priv) + continue; + list_del(&v->base.link); + msm_disable_event(dev, &v->info, file_priv); + v->base.destroy(&v->base); + } + spin_unlock_irqrestore(&dev->event_lock, flags); + + return drm_release(inode, filp); +} + static const struct drm_ioctl_desc msm_ioctls[] = { DRM_IOCTL_DEF_DRV(MSM_GET_PARAM, msm_ioctl_get_param, DRM_AUTH|DRM_RENDER_ALLOW), DRM_IOCTL_DEF_DRV(MSM_GEM_NEW, msm_ioctl_gem_new, DRM_AUTH|DRM_RENDER_ALLOW), @@ -935,6 +1796,27 @@ DRM_IOCTL_DEF_DRV(MSM_GEM_CPU_FINI, msm_ioctl_gem_cpu_fini, DRM_AUTH|DRM_RENDER_ALLOW), DRM_IOCTL_DEF_DRV(MSM_GEM_SUBMIT, msm_ioctl_gem_submit, DRM_AUTH|DRM_RENDER_ALLOW), DRM_IOCTL_DEF_DRV(MSM_WAIT_FENCE, msm_ioctl_wait_fence, DRM_AUTH|DRM_RENDER_ALLOW), + DRM_IOCTL_DEF_DRV(SDE_WB_CONFIG, sde_wb_config, DRM_UNLOCKED|DRM_AUTH), + DRM_IOCTL_DEF_DRV(MSM_REGISTER_EVENT, msm_ioctl_register_event, + DRM_UNLOCKED|DRM_CONTROL_ALLOW), + DRM_IOCTL_DEF_DRV(MSM_DEREGISTER_EVENT, msm_ioctl_deregister_event, + DRM_UNLOCKED|DRM_CONTROL_ALLOW), + DRM_IOCTL_DEF_DRV(MSM_COUNTER_GET, msm_ioctl_counter_get, + DRM_AUTH|DRM_RENDER_ALLOW), + DRM_IOCTL_DEF_DRV(MSM_COUNTER_PUT, msm_ioctl_counter_put, + DRM_AUTH|DRM_RENDER_ALLOW), + DRM_IOCTL_DEF_DRV(MSM_COUNTER_READ, msm_ioctl_counter_read, + DRM_AUTH|DRM_RENDER_ALLOW), + DRM_IOCTL_DEF_DRV(MSM_GEM_SYNC, msm_ioctl_gem_sync, + DRM_AUTH|DRM_RENDER_ALLOW), + DRM_IOCTL_DEF_DRV(MSM_GEM_SVM_NEW, msm_ioctl_gem_svm_new, + DRM_AUTH|DRM_RENDER_ALLOW), + DRM_IOCTL_DEF_DRV(MSM_SUBMITQUEUE_NEW, msm_ioctl_submitqueue_new, + DRM_AUTH|DRM_RENDER_ALLOW), + DRM_IOCTL_DEF_DRV(MSM_SUBMITQUEUE_CLOSE, msm_ioctl_submitqueue_close, + DRM_AUTH|DRM_RENDER_ALLOW), + DRM_IOCTL_DEF_DRV(MSM_SUBMITQUEUE_QUERY, msm_ioctl_submitqueue_query, + DRM_AUTH|DRM_RENDER_ALLOW), }; static const struct vm_operations_struct vm_ops = { @@ -946,7 +1828,7 @@ static const struct file_operations fops = { .owner = THIS_MODULE, .open = drm_open, - .release = drm_release, + .release = msm_release, .unlocked_ioctl = drm_ioctl, #ifdef CONFIG_COMPAT .compat_ioctl = drm_compat_ioctl, @@ -968,6 +1850,7 @@ .unload = msm_unload, .open = msm_open, .preclose = msm_preclose, + .postclose = msm_postclose, .lastclose = msm_lastclose, .set_busid = drm_platform_set_busid, .irq_handler = msm_irq, @@ -999,9 +1882,9 @@ .debugfs_cleanup = msm_debugfs_cleanup, #endif .ioctls = msm_ioctls, - .num_ioctls = DRM_MSM_NUM_IOCTLS, + .num_ioctls = ARRAY_SIZE(msm_ioctls), .fops = &fops, - .name = "msm", + .name = "msm_drm", .desc = "MSM Snapdragon DRM", .date = "20130625", .major = 1, @@ -1011,8 +1894,75 @@ #ifdef CONFIG_PM_SLEEP static int msm_pm_suspend(struct device *dev) { - struct drm_device *ddev = dev_get_drvdata(dev); + struct drm_device *ddev; + struct drm_modeset_acquire_ctx *ctx; + struct drm_connector *conn; + struct drm_atomic_state *state; + struct drm_crtc_state *crtc_state; + struct msm_drm_private *priv; + int ret = 0; + + if (!dev) + return -EINVAL; + + ddev = dev_get_drvdata(dev); + if (!ddev || !ddev->dev_private) + return -EINVAL; + + priv = ddev->dev_private; + SDE_EVT32(0); + + /* acquire modeset lock(s) */ + drm_modeset_lock_all(ddev); + ctx = ddev->mode_config.acquire_ctx; + + /* save current state for resume */ + if (priv->suspend_state) + drm_atomic_state_free(priv->suspend_state); + priv->suspend_state = drm_atomic_helper_duplicate_state(ddev, ctx); + if (IS_ERR_OR_NULL(priv->suspend_state)) { + DRM_ERROR("failed to back up suspend state\n"); + priv->suspend_state = NULL; + goto unlock; + } + + /* create atomic state to disable all CRTCs */ + state = drm_atomic_state_alloc(ddev); + if (IS_ERR_OR_NULL(state)) { + DRM_ERROR("failed to allocate crtc disable state\n"); + goto unlock; + } + + state->acquire_ctx = ctx; + drm_for_each_connector(conn, ddev) { + + if (!conn->state || !conn->state->crtc || + conn->dpms != DRM_MODE_DPMS_ON) + continue; + + /* force CRTC to be inactive */ + crtc_state = drm_atomic_get_crtc_state(state, + conn->state->crtc); + if (IS_ERR_OR_NULL(crtc_state)) { + DRM_ERROR("failed to get crtc %d state\n", + conn->state->crtc->base.id); + drm_atomic_state_free(state); + goto unlock; + } + crtc_state->active = false; + } + + /* commit the "disable all" state */ + ret = drm_atomic_commit(state); + if (ret < 0) { + DRM_ERROR("failed to disable crtcs, %d\n", ret); + drm_atomic_state_free(state); + } +unlock: + drm_modeset_unlock_all(ddev); + + /* disable hot-plug polling */ drm_kms_helper_poll_disable(ddev); return 0; @@ -1020,8 +1970,38 @@ static int msm_pm_resume(struct device *dev) { - struct drm_device *ddev = dev_get_drvdata(dev); + struct drm_device *ddev; + struct msm_drm_private *priv; + int ret; + + if (!dev) + return -EINVAL; + + ddev = dev_get_drvdata(dev); + if (!ddev || !ddev->dev_private) + return -EINVAL; + + priv = ddev->dev_private; + + SDE_EVT32(priv->suspend_state != NULL); + drm_mode_config_reset(ddev); + + drm_modeset_lock_all(ddev); + + if (priv->suspend_state) { + priv->suspend_state->acquire_ctx = + ddev->mode_config.acquire_ctx; + ret = drm_atomic_commit(priv->suspend_state); + if (ret < 0) { + DRM_ERROR("failed to restore state, %d\n", ret); + drm_atomic_state_free(priv->suspend_state); + } + priv->suspend_state = NULL; + } + drm_modeset_unlock_all(ddev); + + /* enable hot-plug polling */ drm_kms_helper_poll_enable(ddev); return 0; @@ -1032,6 +2012,27 @@ SET_SYSTEM_SLEEP_PM_OPS(msm_pm_suspend, msm_pm_resume) }; +static int msm_drm_bind(struct device *dev) +{ + int ret; + + ret = drm_platform_init(&msm_driver, to_platform_device(dev)); + if (ret) + DRM_ERROR("drm_platform_init failed: %d\n", ret); + + return ret; +} + +static void msm_drm_unbind(struct device *dev) +{ + drm_put_dev(platform_get_drvdata(to_platform_device(dev))); +} + +static const struct component_master_ops msm_drm_ops = { + .bind = msm_drm_bind, + .unbind = msm_drm_unbind, +}; + /* * Componentized driver support: */ @@ -1063,27 +2064,31 @@ return 0; } -#else -static int compare_dev(struct device *dev, void *data) + +static int msm_add_master_component(struct device *dev, + struct component_match *match) { - return dev == data; + int ret; + + ret = component_master_add_with_match(dev, &msm_drm_ops, match); + if (ret) + DRM_ERROR("component add match failed: %d\n", ret); + + return ret; } -#endif -static int msm_drm_bind(struct device *dev) +#else +static int compare_dev(struct device *dev, void *data) { - return drm_platform_init(&msm_driver, to_platform_device(dev)); + return dev == data; } -static void msm_drm_unbind(struct device *dev) +static int msm_add_master_component(struct device *dev, + struct component_match *match) { - drm_put_dev(platform_get_drvdata(to_platform_device(dev))); + return 0; } - -static const struct component_master_ops msm_drm_ops = { - .bind = msm_drm_bind, - .unbind = msm_drm_unbind, -}; +#endif /* * Platform driver: @@ -1091,10 +2096,14 @@ static int msm_pdev_probe(struct platform_device *pdev) { + int ret; struct component_match *match = NULL; + #ifdef CONFIG_OF add_components(&pdev->dev, &match, "connectors"); +#ifndef CONFIG_QCOM_KGSL add_components(&pdev->dev, &match, "gpus"); +#endif #else /* For non-DT case, it kinda sucks. We don't actually have a way * to know whether or not we are waiting for certain devices (or if @@ -1121,15 +2130,22 @@ component_match_add(&pdev->dev, &match, compare_dev, dev); } #endif + /* on all devices that I am aware of, iommu's which cna map + * any address the cpu can see are used: + */ + ret = dma_set_mask_and_coherent(&pdev->dev, ~0); + if (ret) + return ret; + + ret = msm_add_master_component(&pdev->dev, match); - pdev->dev.coherent_dma_mask = DMA_BIT_MASK(32); - return component_master_add_with_match(&pdev->dev, &msm_drm_ops, match); + return ret; } static int msm_pdev_remove(struct platform_device *pdev) { + msm_drm_unbind(&pdev->dev); component_master_del(&pdev->dev, &msm_drm_ops); - return 0; } @@ -1138,9 +2154,31 @@ { } }; +static void msm_pdev_shutdown(struct platform_device *pdev) +{ + struct drm_device *ddev = platform_get_drvdata(pdev); + struct msm_drm_private *priv = NULL; + + if (!ddev) { + DRM_ERROR("invalid drm device node\n"); + return; + } + + priv = ddev->dev_private; + if (!priv) { + DRM_ERROR("invalid msm drm private node\n"); + return; + } + + msm_lastclose(ddev); + + /* set this after lastclose to allow kickoff from lastclose */ + priv->shutdown_in_progress = true; +} + static const struct of_device_id dt_match[] = { { .compatible = "qcom,mdp" }, /* mdp4 */ - { .compatible = "qcom,mdss_mdp" }, /* mdp5 */ + { .compatible = "qcom,sde-kms" }, /* sde */ {} }; MODULE_DEVICE_TABLE(of, dt_match); @@ -1148,17 +2186,30 @@ static struct platform_driver msm_platform_driver = { .probe = msm_pdev_probe, .remove = msm_pdev_remove, + .shutdown = msm_pdev_shutdown, .driver = { - .name = "msm", + .name = "msm_drm", .of_match_table = dt_match, .pm = &msm_pm_ops, + .probe_type = PROBE_PREFER_ASYNCHRONOUS, }, .id_table = msm_id, }; +#ifdef CONFIG_QCOM_KGSL +void __init adreno_register(void) +{ +} + +void __exit adreno_unregister(void) +{ +} +#endif + static int __init msm_drm_register(void) { DBG("init"); + msm_smmu_driver_init(); msm_dsi_register(); msm_edp_register(); hdmi_register(); @@ -1174,6 +2225,7 @@ adreno_unregister(); msm_edp_unregister(); msm_dsi_unregister(); + msm_smmu_driver_cleanup(); } module_init(msm_drm_register); diff -ruw linux-4.4.115/drivers/gpu/drm/msm/msm_drv.h linux-4.4.115-fbx/drivers/gpu/drm/msm/msm_drv.h --- linux-4.4.115/drivers/gpu/drm/msm/msm_drv.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/gpu/drm/msm/msm_drv.h 2019-10-29 09:26:23.633203080 +0100 @@ -1,4 +1,5 @@ /* + * Copyright (c) 2016-2018, The Linux Foundation. All rights reserved. * Copyright (C) 2013 Red Hat * Author: Rob Clark * @@ -31,7 +32,11 @@ #include #include #include +#include +#include +#include #include +#include #ifndef CONFIG_OF #include @@ -48,40 +53,231 @@ #include #include +#include "sde_power_handle.h" + +#define GET_MAJOR_REV(rev) ((rev) >> 28) +#define GET_MINOR_REV(rev) (((rev) >> 16) & 0xFFF) +#define GET_STEP_REV(rev) ((rev) & 0xFFFF) + struct msm_kms; struct msm_gpu; struct msm_mmu; struct msm_rd_state; struct msm_perf_state; struct msm_gem_submit; +struct msm_gem_address_space; +struct msm_gem_vma; -#define NUM_DOMAINS 2 /* one for KMS, then one per gpu core (?) */ +#define NUM_DOMAINS 4 /* one for KMS, then one per gpu core (?) */ +#define MAX_CRTCS 8 +#define MAX_PLANES 12 +#define MAX_ENCODERS 8 +#define MAX_BRIDGES 8 +#define MAX_CONNECTORS 8 struct msm_file_private { - /* currently we don't do anything useful with this.. but when - * per-context address spaces are supported we'd keep track of - * the context's page-tables here. - */ - int dummy; + struct msm_gem_address_space *aspace; + struct list_head counters; + rwlock_t queuelock; + struct list_head submitqueues; + int queueid; }; enum msm_mdp_plane_property { - PLANE_PROP_ZPOS, + /* blob properties, always put these first */ + PLANE_PROP_SCALER_V1, + PLANE_PROP_SCALER_V2, + PLANE_PROP_CSC_V1, + PLANE_PROP_INFO, + PLANE_PROP_SCALER_LUT_ED, + PLANE_PROP_SCALER_LUT_CIR, + PLANE_PROP_SCALER_LUT_SEP, + PLANE_PROP_SKIN_COLOR, + PLANE_PROP_SKY_COLOR, + PLANE_PROP_FOLIAGE_COLOR, + + /* # of blob properties */ + PLANE_PROP_BLOBCOUNT, + + /* range properties */ + PLANE_PROP_ZPOS = PLANE_PROP_BLOBCOUNT, PLANE_PROP_ALPHA, - PLANE_PROP_PREMULTIPLIED, - PLANE_PROP_MAX_NUM + PLANE_PROP_COLOR_FILL, + PLANE_PROP_H_DECIMATE, + PLANE_PROP_V_DECIMATE, + PLANE_PROP_INPUT_FENCE, + PLANE_PROP_HUE_ADJUST, + PLANE_PROP_SATURATION_ADJUST, + PLANE_PROP_VALUE_ADJUST, + PLANE_PROP_CONTRAST_ADJUST, + + /* enum/bitmask properties */ + PLANE_PROP_ROTATION, + PLANE_PROP_BLEND_OP, + PLANE_PROP_SRC_CONFIG, + PLANE_PROP_FB_TRANSLATION_MODE, + + /* total # of properties */ + PLANE_PROP_COUNT +}; + +enum msm_mdp_crtc_property { + CRTC_PROP_INFO, + + /* # of blob properties */ + CRTC_PROP_BLOBCOUNT, + + /* range properties */ + CRTC_PROP_INPUT_FENCE_TIMEOUT = CRTC_PROP_BLOBCOUNT, + CRTC_PROP_OUTPUT_FENCE, + CRTC_PROP_OUTPUT_FENCE_OFFSET, + CRTC_PROP_CORE_CLK, + CRTC_PROP_CORE_AB, + CRTC_PROP_CORE_IB, + CRTC_PROP_SECURITY_LEVEL, + + /* total # of properties */ + CRTC_PROP_COUNT +}; + +enum msm_mdp_conn_property { + /* blob properties, always put these first */ + CONNECTOR_PROP_SDE_INFO, + CONNECTOR_PROP_HDR_INFO, + CONNECTOR_PROP_HDR_CONTROL, + + /* # of blob properties */ + CONNECTOR_PROP_BLOBCOUNT, + + /* range properties */ + CONNECTOR_PROP_OUT_FB = CONNECTOR_PROP_BLOBCOUNT, + CONNECTOR_PROP_RETIRE_FENCE, + CONNECTOR_PROP_DST_X, + CONNECTOR_PROP_DST_Y, + CONNECTOR_PROP_DST_W, + CONNECTOR_PROP_DST_H, + CONNECTOR_PROP_PLL_DELTA, + CONNECTOR_PROP_PLL_ENABLE, + CONNECTOR_PROP_HDCP_VERSION, + + /* enum/bitmask properties */ + CONNECTOR_PROP_TOPOLOGY_NAME, + CONNECTOR_PROP_TOPOLOGY_CONTROL, + CONNECTOR_PROP_LP, + CONNECTOR_PROP_HPD_OFF, + + /* total # of properties */ + CONNECTOR_PROP_COUNT }; struct msm_vblank_ctrl { - struct work_struct work; + struct kthread_work work; struct list_head event_list; spinlock_t lock; }; +#define MAX_H_TILES_PER_DISPLAY 2 + +/** + * enum msm_display_compression - compression method used for pixel stream + * @MSM_DISPLAY_COMPRESS_NONE: Pixel data is not compressed + * @MSM_DISPLAY_COMPRESS_DSC: DSC compresison is used + * @MSM_DISPLAY_COMPRESS_FBC: FBC compression is used + */ +enum msm_display_compression { + MSM_DISPLAY_COMPRESS_NONE, + MSM_DISPLAY_COMPRESS_DSC, + MSM_DISPLAY_COMPRESS_FBC, +}; + +/** + * enum msm_display_caps - features/capabilities supported by displays + * @MSM_DISPLAY_CAP_VID_MODE: Video or "active" mode supported + * @MSM_DISPLAY_CAP_CMD_MODE: Command mode supported + * @MSM_DISPLAY_CAP_HOT_PLUG: Hot plug detection supported + * @MSM_DISPLAY_CAP_EDID: EDID supported + */ +enum msm_display_caps { + MSM_DISPLAY_CAP_VID_MODE = BIT(0), + MSM_DISPLAY_CAP_CMD_MODE = BIT(1), + MSM_DISPLAY_CAP_HOT_PLUG = BIT(2), + MSM_DISPLAY_CAP_EDID = BIT(3), +}; + +/** + * struct msm_display_info - defines display properties + * @intf_type: DRM_MODE_CONNECTOR_ display type + * @capabilities: Bitmask of display flags + * @num_of_h_tiles: Number of horizontal tiles in case of split interface + * @h_tile_instance: Controller instance used per tile. Number of elements is + * based on num_of_h_tiles + * @is_connected: Set to true if display is connected + * @width_mm: Physical width + * @height_mm: Physical height + * @max_width: Max width of display. In case of hot pluggable display + * this is max width supported by controller + * @max_height: Max height of display. In case of hot pluggable display + * this is max height supported by controller + * @compression: Compression supported by the display + */ +struct msm_display_info { + int intf_type; + uint32_t capabilities; + + uint32_t num_of_h_tiles; + uint32_t h_tile_instance[MAX_H_TILES_PER_DISPLAY]; + + bool is_connected; + + unsigned int width_mm; + unsigned int height_mm; + + uint32_t max_width; + uint32_t max_height; + + enum msm_display_compression compression; +}; + +/** + * struct - msm_display_kickoff_params - info for display features at kickoff + * @hdr_ctrl: HDR control info passed from userspace + */ +struct msm_display_kickoff_params { + struct drm_msm_ext_panel_hdr_ctrl *hdr_ctrl; +}; + +/** + * struct msm_drm_event - defines custom event notification struct + * @base: base object required for event notification by DRM framework. + * @event: event object required for event notification by DRM framework. + * @info: contains information of DRM object for which events has been + * requested. + * @data: memory location which contains response payload for event. + */ +struct msm_drm_event { + struct drm_pending_event base; + struct drm_event event; + struct drm_msm_event_req info; + u8 data[]; +}; + +/* Commit thread specific structure */ +struct msm_drm_commit { + struct drm_device *dev; + struct task_struct *thread; + unsigned int crtc_id; + struct kthread_worker worker; +}; + +#define MSM_GPU_MAX_RINGS 4 + struct msm_drm_private { struct msm_kms *kms; + struct sde_power_handle phandle; + struct sde_power_client *pclient; + /* subordinate devices, if present: */ struct platform_device *gpu_pdev; @@ -101,11 +297,11 @@ /* when we have more than one 'msm_gpu' these need to be an array: */ struct msm_gpu *gpu; - struct msm_file_private *lastctx; struct drm_fb_helper *fbdev; - uint32_t next_fence, completed_fence; + uint32_t completed_fence[MSM_GPU_MAX_RINGS]; + wait_queue_head_t fence_event; struct msm_rd_state *rd; @@ -123,27 +319,43 @@ uint32_t pending_crtcs; wait_queue_head_t pending_crtcs_event; - /* registered MMUs: */ - unsigned int num_mmus; - struct msm_mmu *mmus[NUM_DOMAINS]; + /* Registered address spaces.. currently this is fixed per # of + * iommu's. Ie. one for display block and one for gpu block. + * Eventually, to do per-process gpu pagetables, we'll want one + * of these per-process. + */ + unsigned int num_aspaces; + struct msm_gem_address_space *aspace[NUM_DOMAINS]; unsigned int num_planes; - struct drm_plane *planes[8]; + struct drm_plane *planes[MAX_PLANES]; unsigned int num_crtcs; - struct drm_crtc *crtcs[8]; + struct drm_crtc *crtcs[MAX_CRTCS]; + + struct msm_drm_commit disp_thread[MAX_CRTCS]; unsigned int num_encoders; - struct drm_encoder *encoders[8]; + struct drm_encoder *encoders[MAX_ENCODERS]; unsigned int num_bridges; - struct drm_bridge *bridges[8]; + struct drm_bridge *bridges[MAX_BRIDGES]; unsigned int num_connectors; - struct drm_connector *connectors[8]; + struct drm_connector *connectors[MAX_CONNECTORS]; + + /* hash to store mm_struct to msm_mmu_notifier mappings */ + DECLARE_HASHTABLE(mn_hash, 7); + /* protects mn_hash and the msm_mmu_notifier for the process */ + struct mutex mn_lock; /* Properties */ - struct drm_property *plane_property[PLANE_PROP_MAX_NUM]; + struct drm_property *plane_property[PLANE_PROP_COUNT]; + struct drm_property *crtc_property[CRTC_PROP_COUNT]; + struct drm_property *conn_property[CONNECTOR_PROP_COUNT]; + + /* Color processing properties for the crtc */ + struct drm_property **cp_property; /* VRAM carveout, used when no IOMMU: */ struct { @@ -153,15 +365,50 @@ * and position mm_node->start is in # of pages: */ struct drm_mm mm; + spinlock_t lock; /* Protects drm_mm node allocation/removal */ } vram; struct msm_vblank_ctrl vblank_ctrl; + + /* saved atomic state during system suspend */ + struct drm_atomic_state *suspend_state; + + /* list of clients waiting for events */ + struct list_head client_event_list; + + /* update the flag when msm driver receives shutdown notification */ + bool shutdown_in_progress; }; struct msm_format { uint32_t pixel_format; }; +/* + * Some GPU targets can support multiple ringbuffers and preempt between them. + * In order to do this without massive API changes we will steal two bits from + * the top of the fence and use them to identify the ringbuffer, (0x00000001 for + * riug 0, 0x40000001 for ring 1, 0x50000001 for ring 2, etc). If you are going + * to do a fence comparision you have to make sure you are only comparing + * against fences from the same ring, but since fences within a ringbuffer are + * still contigious you can still use straight comparisons (i.e 0x40000001 is + * older than 0x40000002). Mathmatically there will be 0x3FFFFFFF timestamps + * per ring or ~103 days of 120 interrupts per second (two interrupts per frame + * at 60 FPS). + */ +#define FENCE_RING(_fence) ((_fence >> 30) & 3) +#define FENCE(_ring, _fence) ((((_ring) & 3) << 30) | ((_fence) & 0x3FFFFFFF)) + +static inline bool COMPARE_FENCE_LTE(uint32_t a, uint32_t b) +{ + return ((FENCE_RING(a) == FENCE_RING(b)) && a <= b); +} + +static inline bool COMPARE_FENCE_LT(uint32_t a, uint32_t b) +{ + return ((FENCE_RING(a) == FENCE_RING(b)) && a < b); +} + /* callback from wq once fence has passed: */ struct msm_fence_cb { struct work_struct work; @@ -176,19 +423,52 @@ (_cb)->func = _func; \ } while (0) -int msm_atomic_check(struct drm_device *dev, - struct drm_atomic_state *state); +static inline bool msm_is_suspend_state(struct drm_device *dev) +{ + if (!dev || !dev->dev_private) + return false; + + return ((struct msm_drm_private *)dev->dev_private)->suspend_state != + NULL; +} + int msm_atomic_commit(struct drm_device *dev, struct drm_atomic_state *state, bool async); -int msm_register_mmu(struct drm_device *dev, struct msm_mmu *mmu); - int msm_wait_fence(struct drm_device *dev, uint32_t fence, ktime_t *timeout, bool interruptible); int msm_queue_fence_cb(struct drm_device *dev, struct msm_fence_cb *cb, uint32_t fence); void msm_update_fence(struct drm_device *dev, uint32_t fence); +void msm_gem_unmap_vma(struct msm_gem_address_space *aspace, + struct msm_gem_vma *vma, struct sg_table *sgt, + void *priv, bool invalidated); +int msm_gem_map_vma(struct msm_gem_address_space *aspace, + struct msm_gem_vma *vma, struct sg_table *sgt, + void *priv, unsigned int flags); +int msm_gem_reserve_iova(struct msm_gem_address_space *aspace, + struct msm_gem_vma *domain, + uint64_t hostptr, uint64_t size); +void msm_gem_release_iova(struct msm_gem_address_space *aspace, + struct msm_gem_vma *vma); + +void msm_gem_address_space_put(struct msm_gem_address_space *aspace); + +/* For GPU and legacy display */ +struct msm_gem_address_space * +msm_gem_address_space_create(struct device *dev, struct iommu_domain *domain, + int type, const char *name); +struct msm_gem_address_space * +msm_gem_address_space_create_instance(struct msm_mmu *parent, const char *name, + uint64_t start, uint64_t end); + +/* For SDE display */ +struct msm_gem_address_space * +msm_gem_smmu_address_space_create(struct device *dev, struct msm_mmu *mmu, + const char *name); + +void msm_gem_submit_free(struct msm_gem_submit *submit); int msm_ioctl_gem_submit(struct drm_device *dev, void *data, struct drm_file *file); @@ -197,13 +477,14 @@ int msm_gem_mmap(struct file *filp, struct vm_area_struct *vma); int msm_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf); uint64_t msm_gem_mmap_offset(struct drm_gem_object *obj); -int msm_gem_get_iova_locked(struct drm_gem_object *obj, int id, - uint32_t *iova); -int msm_gem_get_iova(struct drm_gem_object *obj, int id, uint32_t *iova); -uint32_t msm_gem_iova(struct drm_gem_object *obj, int id); +int msm_gem_get_iova(struct drm_gem_object *obj, + struct msm_gem_address_space *aspace, uint64_t *iova); +uint64_t msm_gem_iova(struct drm_gem_object *obj, + struct msm_gem_address_space *aspace); struct page **msm_gem_get_pages(struct drm_gem_object *obj); void msm_gem_put_pages(struct drm_gem_object *obj); -void msm_gem_put_iova(struct drm_gem_object *obj, int id); +void msm_gem_put_iova(struct drm_gem_object *obj, + struct msm_gem_address_space *aspace); int msm_gem_dumb_create(struct drm_file *file, struct drm_device *dev, struct drm_mode_create_dumb *args); int msm_gem_dumb_map_offset(struct drm_file *file, struct drm_device *dev, @@ -217,7 +498,6 @@ struct dma_buf_attachment *attach, struct sg_table *sg); int msm_gem_prime_pin(struct drm_gem_object *obj); void msm_gem_prime_unpin(struct drm_gem_object *obj); -void *msm_gem_vaddr_locked(struct drm_gem_object *obj); void *msm_gem_vaddr(struct drm_gem_object *obj); int msm_gem_queue_inactive_cb(struct drm_gem_object *obj, struct msm_fence_cb *cb); @@ -232,12 +512,29 @@ uint32_t size, uint32_t flags, uint32_t *handle); struct drm_gem_object *msm_gem_new(struct drm_device *dev, uint32_t size, uint32_t flags); +struct drm_gem_object *msm_gem_new_locked(struct drm_device *dev, + uint32_t size, uint32_t flags); struct drm_gem_object *msm_gem_import(struct drm_device *dev, - uint32_t size, struct sg_table *sgt); - -int msm_framebuffer_prepare(struct drm_framebuffer *fb, int id); -void msm_framebuffer_cleanup(struct drm_framebuffer *fb, int id); -uint32_t msm_framebuffer_iova(struct drm_framebuffer *fb, int id, int plane); + uint32_t size, struct sg_table *sgt, u32 flags); +void msm_gem_sync(struct drm_gem_object *obj, u32 op); +int msm_gem_svm_new_handle(struct drm_device *dev, struct drm_file *file, + uint64_t hostptr, uint64_t size, + uint32_t flags, uint32_t *handle); +struct drm_gem_object *msm_gem_svm_new(struct drm_device *dev, + struct drm_file *file, uint64_t hostptr, + uint64_t size, uint32_t flags); +void *msm_gem_kernel_new(struct drm_device *dev, uint32_t size, + uint32_t flags, struct msm_gem_address_space *aspace, + struct drm_gem_object **bo, uint64_t *iova); +void *msm_gem_kernel_new_locked(struct drm_device *dev, uint32_t size, + uint32_t flags, struct msm_gem_address_space *aspace, + struct drm_gem_object **bo, uint64_t *iova); +int msm_framebuffer_prepare(struct drm_framebuffer *fb, + struct msm_gem_address_space *aspace); +void msm_framebuffer_cleanup(struct drm_framebuffer *fb, + struct msm_gem_address_space *aspace); +uint32_t msm_framebuffer_iova(struct drm_framebuffer *fb, + struct msm_gem_address_space *aspace, int plane); struct drm_gem_object *msm_framebuffer_bo(struct drm_framebuffer *fb, int plane); const struct msm_format *msm_framebuffer_format(struct drm_framebuffer *fb); struct drm_framebuffer *msm_framebuffer_init(struct drm_device *dev, @@ -247,6 +544,19 @@ struct drm_fb_helper *msm_fbdev_init(struct drm_device *dev); +struct msm_gpu_submitqueue; +int msm_submitqueue_init(struct msm_file_private *ctx); +struct msm_gpu_submitqueue *msm_submitqueue_get(struct msm_file_private *ctx, + u32 id); +int msm_submitqueue_create(struct msm_file_private *ctx, u32 prio, + u32 flags, u32 *id); +int msm_submitqueue_query(struct msm_file_private *ctx, u32 id, u32 param, + void __user *data, u32 len); +int msm_submitqueue_remove(struct msm_file_private *ctx, u32 id); +void msm_submitqueue_close(struct msm_file_private *ctx); + +void msm_submitqueue_destroy(struct kref *kref); + struct hdmi; int hdmi_modeset_init(struct hdmi *hdmi, struct drm_device *dev, struct drm_encoder *encoder); @@ -265,6 +575,15 @@ MSM_DSI_CMD_ENCODER_ID = 1, MSM_DSI_ENCODER_NUM = 2 }; + +/* * + * msm_send_crtc_notification - notify user-space clients of crtc events. + * @crtc: crtc that is generating the event. + * @event: event that needs to be notified. + * @payload: payload for the event. + */ +void msm_send_crtc_notification(struct drm_crtc *crtc, + struct drm_event *event, u8 *payload); #ifdef CONFIG_DRM_MSM_DSI void __init msm_dsi_register(void); void __exit msm_dsi_unregister(void); @@ -302,6 +621,7 @@ void __iomem *msm_ioremap(struct platform_device *pdev, const char *name, const char *dbgname); +void msm_iounmap(struct platform_device *dev, void __iomem *addr); void msm_writel(u32 data, void __iomem *addr); u32 msm_readl(const void __iomem *addr); @@ -311,7 +631,8 @@ static inline bool fence_completed(struct drm_device *dev, uint32_t fence) { struct msm_drm_private *priv = dev->dev_private; - return priv->completed_fence >= fence; + + return priv->completed_fence[FENCE_RING(fence)] >= fence; } static inline int align_pitch(int width, int bpp) @@ -332,5 +653,4 @@ /* for conditionally setting boolean flag(s): */ #define COND(bool, val) ((bool) ? (val) : 0) - #endif /* __MSM_DRV_H__ */ diff -ruw linux-4.4.115/drivers/gpu/drm/msm/msm_fb.c linux-4.4.115-fbx/drivers/gpu/drm/msm/msm_fb.c --- linux-4.4.115/drivers/gpu/drm/msm/msm_fb.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/gpu/drm/msm/msm_fb.c 2019-01-22 16:16:23.507246443 +0100 @@ -1,4 +1,5 @@ /* + * Copyright (c) 2016-2018, The Linux Foundation. All rights reserved. * Copyright (C) 2013 Red Hat * Author: Rob Clark * @@ -33,17 +34,33 @@ struct drm_file *file_priv, unsigned int *handle) { - struct msm_framebuffer *msm_fb = to_msm_framebuffer(fb); + struct msm_framebuffer *msm_fb; + + if (!fb) { + DRM_ERROR("from:%pS null fb\n", __builtin_return_address(0)); + return -EINVAL; + } + + msm_fb = to_msm_framebuffer(fb); + return drm_gem_handle_create(file_priv, msm_fb->planes[0], handle); } static void msm_framebuffer_destroy(struct drm_framebuffer *fb) { - struct msm_framebuffer *msm_fb = to_msm_framebuffer(fb); - int i, n = drm_format_num_planes(fb->pixel_format); + struct msm_framebuffer *msm_fb; + int i, n; + + if (!fb) { + DRM_ERROR("from:%pS null fb\n", __builtin_return_address(0)); + return; + } + + msm_fb = to_msm_framebuffer(fb); + n = drm_format_num_planes(fb->pixel_format); - DBG("destroy: FB ID: %d (%p)", fb->base.id, fb); + DBG("destroy: FB ID: %d (%pK)", fb->base.id, fb); drm_framebuffer_cleanup(fb); @@ -72,9 +89,16 @@ #ifdef CONFIG_DEBUG_FS void msm_framebuffer_describe(struct drm_framebuffer *fb, struct seq_file *m) { - struct msm_framebuffer *msm_fb = to_msm_framebuffer(fb); - int i, n = drm_format_num_planes(fb->pixel_format); + struct msm_framebuffer *msm_fb; + int i, n; + if (!fb) { + DRM_ERROR("from:%pS null fb\n", __builtin_return_address(0)); + return; + } + + msm_fb = to_msm_framebuffer(fb); + n = drm_format_num_planes(fb->pixel_format); seq_printf(m, "fb: %dx%d@%4.4s (%2d, ID:%d)\n", fb->width, fb->height, (char *)&fb->pixel_format, fb->refcount.refcount.counter, fb->base.id); @@ -92,15 +116,23 @@ * should be fine, since only the scanout (mdpN) side of things needs * this, the gpu doesn't care about fb's. */ -int msm_framebuffer_prepare(struct drm_framebuffer *fb, int id) +int msm_framebuffer_prepare(struct drm_framebuffer *fb, + struct msm_gem_address_space *aspace) { - struct msm_framebuffer *msm_fb = to_msm_framebuffer(fb); - int ret, i, n = drm_format_num_planes(fb->pixel_format); - uint32_t iova; + struct msm_framebuffer *msm_fb; + int ret, i, n; + uint64_t iova; + if (!fb) { + DRM_ERROR("from:%pS null fb\n", __builtin_return_address(0)); + return -EINVAL; + } + + msm_fb = to_msm_framebuffer(fb); + n = drm_format_num_planes(fb->pixel_format); for (i = 0; i < n; i++) { - ret = msm_gem_get_iova(msm_fb->planes[i], id, &iova); - DBG("FB[%u]: iova[%d]: %08x (%d)", fb->base.id, i, iova, ret); + ret = msm_gem_get_iova(msm_fb->planes[i], aspace, &iova); + DBG("FB[%u]: iova[%d]: %08llx (%d)", fb->base.id, i, iova, ret); if (ret) return ret; } @@ -108,33 +140,62 @@ return 0; } -void msm_framebuffer_cleanup(struct drm_framebuffer *fb, int id) +void msm_framebuffer_cleanup(struct drm_framebuffer *fb, + struct msm_gem_address_space *aspace) { - struct msm_framebuffer *msm_fb = to_msm_framebuffer(fb); - int i, n = drm_format_num_planes(fb->pixel_format); + struct msm_framebuffer *msm_fb; + int i, n; + + if (fb == NULL) { + DRM_ERROR("from:%pS null fb\n", __builtin_return_address(0)); + return; + } + + msm_fb = to_msm_framebuffer(fb); + n = drm_format_num_planes(fb->pixel_format); for (i = 0; i < n; i++) - msm_gem_put_iova(msm_fb->planes[i], id); + msm_gem_put_iova(msm_fb->planes[i], aspace); } -uint32_t msm_framebuffer_iova(struct drm_framebuffer *fb, int id, int plane) +/* FIXME: Leave this as a uint32_t and just return the lower 32 bits? */ +uint32_t msm_framebuffer_iova(struct drm_framebuffer *fb, + struct msm_gem_address_space *aspace, int plane) { - struct msm_framebuffer *msm_fb = to_msm_framebuffer(fb); + struct msm_framebuffer *msm_fb; + uint64_t iova; + + if (!fb) { + DRM_ERROR("from:%pS null fb\n", __builtin_return_address(0)); + return -EINVAL; + } + + msm_fb = to_msm_framebuffer(fb); if (!msm_fb->planes[plane]) return 0; - return msm_gem_iova(msm_fb->planes[plane], id) + fb->offsets[plane]; + + iova = msm_gem_iova(msm_fb->planes[plane], aspace) + fb->offsets[plane]; + + /* FIXME: Make sure it is < 32 bits */ + return lower_32_bits(iova); } struct drm_gem_object *msm_framebuffer_bo(struct drm_framebuffer *fb, int plane) { - struct msm_framebuffer *msm_fb = to_msm_framebuffer(fb); + struct msm_framebuffer *msm_fb; + + if (!fb) { + DRM_ERROR("from:%pS null fb\n", __builtin_return_address(0)); + return ERR_PTR(-EINVAL); + } + + msm_fb = to_msm_framebuffer(fb); return msm_fb->planes[plane]; } const struct msm_format *msm_framebuffer_format(struct drm_framebuffer *fb) { - struct msm_framebuffer *msm_fb = to_msm_framebuffer(fb); - return msm_fb->format; + return fb ? (to_msm_framebuffer(fb))->format : NULL; } struct drm_framebuffer *msm_framebuffer_create(struct drm_device *dev, @@ -175,18 +236,20 @@ struct msm_framebuffer *msm_fb = NULL; struct drm_framebuffer *fb; const struct msm_format *format; - int ret, i, n; + int ret, i, num_planes; unsigned int hsub, vsub; + bool is_modified = false; - DBG("create framebuffer: dev=%p, mode_cmd=%p (%dx%d@%4.4s)", + DBG("create framebuffer: dev=%pK, mode_cmd=%pK (%dx%d@%4.4s)", dev, mode_cmd, mode_cmd->width, mode_cmd->height, (char *)&mode_cmd->pixel_format); - n = drm_format_num_planes(mode_cmd->pixel_format); + num_planes = drm_format_num_planes(mode_cmd->pixel_format); hsub = drm_format_horz_chroma_subsampling(mode_cmd->pixel_format); vsub = drm_format_vert_chroma_subsampling(mode_cmd->pixel_format); - format = kms->funcs->get_format(kms, mode_cmd->pixel_format); + format = kms->funcs->get_format(kms, mode_cmd->pixel_format, + mode_cmd->modifier, num_planes); if (!format) { dev_err(dev->dev, "unsupported pixel format: %4.4s\n", (char *)&mode_cmd->pixel_format); @@ -204,27 +267,53 @@ msm_fb->format = format; - if (n > ARRAY_SIZE(msm_fb->planes)) { + if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) { + for (i = 0; i < ARRAY_SIZE(mode_cmd->modifier); i++) { + if (mode_cmd->modifier[i]) { + is_modified = true; + break; + } + } + } + + if (num_planes > ARRAY_SIZE(msm_fb->planes)) { ret = -EINVAL; goto fail; } - for (i = 0; i < n; i++) { + if (is_modified) { + if (!kms->funcs->check_modified_format) { + dev_err(dev->dev, "can't check modified fb format\n"); + ret = -EINVAL; + goto fail; + } else { + ret = kms->funcs->check_modified_format( + kms, msm_fb->format, mode_cmd, bos); + if (ret) + goto fail; + } + } else { + for (i = 0; i < num_planes; i++) { unsigned int width = mode_cmd->width / (i ? hsub : 1); unsigned int height = mode_cmd->height / (i ? vsub : 1); unsigned int min_size; + unsigned int cpp; + + cpp = drm_format_plane_cpp(mode_cmd->pixel_format, i); min_size = (height - 1) * mode_cmd->pitches[i] - + width * drm_format_plane_cpp(mode_cmd->pixel_format, i) + + width * cpp + mode_cmd->offsets[i]; if (bos[i]->size < min_size) { ret = -EINVAL; goto fail; } + } + } + for (i = 0; i < num_planes; i++) msm_fb->planes[i] = bos[i]; - } drm_helper_mode_fill_fb_struct(fb, mode_cmd); @@ -234,7 +323,7 @@ goto fail; } - DBG("create: FB ID: %d (%p)", fb->base.id, fb); + DBG("create: FB ID: %d (%pK)", fb->base.id, fb); return fb; diff -ruw linux-4.4.115/drivers/gpu/drm/msm/msm_gem.c linux-4.4.115-fbx/drivers/gpu/drm/msm/msm_gem.c --- linux-4.4.115/drivers/gpu/drm/msm/msm_gem.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/gpu/drm/msm/msm_gem.c 2019-01-22 16:16:23.507246443 +0100 @@ -18,12 +18,159 @@ #include #include #include +#include #include "msm_drv.h" #include "msm_gem.h" #include "msm_gpu.h" #include "msm_mmu.h" +static void msm_gem_mn_free(struct kref *refcount) +{ + struct msm_mmu_notifier *msm_mn = container_of(refcount, + struct msm_mmu_notifier, refcount); + + mmu_notifier_unregister(&msm_mn->mn, msm_mn->mm); + hash_del(&msm_mn->node); + + kfree(msm_mn); +} + +static int msm_gem_mn_get(struct msm_mmu_notifier *msm_mn) +{ + if (msm_mn) + return kref_get_unless_zero(&msm_mn->refcount); + return 0; +} + +static void msm_gem_mn_put(struct msm_mmu_notifier *msm_mn) +{ + if (msm_mn) { + struct msm_drm_private *msm_dev = msm_mn->msm_dev; + + mutex_lock(&msm_dev->mn_lock); + kref_put(&msm_mn->refcount, msm_gem_mn_free); + mutex_unlock(&msm_dev->mn_lock); + } +} + +void msm_mn_invalidate_range_start(struct mmu_notifier *mn, + struct mm_struct *mm, unsigned long start, unsigned long end); + +static const struct mmu_notifier_ops msm_mn_ops = { + .invalidate_range_start = msm_mn_invalidate_range_start, +}; + +static struct msm_mmu_notifier * +msm_gem_mn_find(struct msm_drm_private *msm_dev, struct mm_struct *mm, + struct msm_gem_address_space *aspace) +{ + struct msm_mmu_notifier *msm_mn; + int ret = 0; + + mutex_lock(&msm_dev->mn_lock); + hash_for_each_possible(msm_dev->mn_hash, msm_mn, node, + (unsigned long) mm) { + if (msm_mn->mm == mm) { + if (!msm_gem_mn_get(msm_mn)) { + ret = -EINVAL; + goto fail; + } + mutex_unlock(&msm_dev->mn_lock); + return msm_mn; + } + } + + msm_mn = kzalloc(sizeof(*msm_mn), GFP_KERNEL); + if (!msm_mn) { + ret = -ENOMEM; + goto fail; + } + + msm_mn->mm = current->mm; + msm_mn->mn.ops = &msm_mn_ops; + ret = mmu_notifier_register(&msm_mn->mn, msm_mn->mm); + if (ret) { + kfree(msm_mn); + goto fail; + } + + msm_mn->svm_tree = RB_ROOT; + spin_lock_init(&msm_mn->svm_tree_lock); + kref_init(&msm_mn->refcount); + msm_mn->msm_dev = msm_dev; + + /* Insert the msm_mn into the hash */ + hash_add(msm_dev->mn_hash, &msm_mn->node, (unsigned long) msm_mn->mm); + mutex_unlock(&msm_dev->mn_lock); + + return msm_mn; + +fail: + mutex_unlock(&msm_dev->mn_lock); + return ERR_PTR(ret); +} + +static int msm_gem_mn_register(struct msm_gem_svm_object *msm_svm_obj, + struct msm_gem_address_space *aspace) +{ + struct drm_gem_object *obj = &msm_svm_obj->msm_obj_base.base; + struct msm_drm_private *msm_dev = obj->dev->dev_private; + struct msm_mmu_notifier *msm_mn; + + msm_svm_obj->mm = current->mm; + msm_svm_obj->svm_node.start = msm_svm_obj->hostptr; + msm_svm_obj->svm_node.last = msm_svm_obj->hostptr + obj->size - 1; + + msm_mn = msm_gem_mn_find(msm_dev, msm_svm_obj->mm, aspace); + if (IS_ERR(msm_mn)) + return PTR_ERR(msm_mn); + + msm_svm_obj->msm_mn = msm_mn; + + spin_lock(&msm_mn->svm_tree_lock); + interval_tree_insert(&msm_svm_obj->svm_node, &msm_mn->svm_tree); + spin_unlock(&msm_mn->svm_tree_lock); + + return 0; +} + +static void msm_gem_mn_unregister(struct msm_gem_svm_object *msm_svm_obj) +{ + struct msm_mmu_notifier *msm_mn = msm_svm_obj->msm_mn; + + /* invalid: bo already unregistered */ + if (!msm_mn || msm_svm_obj->invalid) + return; + + spin_lock(&msm_mn->svm_tree_lock); + interval_tree_remove(&msm_svm_obj->svm_node, &msm_mn->svm_tree); + spin_unlock(&msm_mn->svm_tree_lock); +} + +static int protect_pages(struct msm_gem_object *msm_obj) +{ + int perm = PERM_READ | PERM_WRITE; + int src = VMID_HLOS; + int dst = VMID_CP_PIXEL; + + return hyp_assign_table(msm_obj->sgt, &src, 1, &dst, &perm, 1); +} + +static int unprotect_pages(struct msm_gem_object *msm_obj) +{ + int perm = PERM_READ | PERM_WRITE | PERM_EXEC; + int src = VMID_CP_PIXEL; + int dst = VMID_HLOS; + + return hyp_assign_table(msm_obj->sgt, &src, 1, &dst, &perm, 1); +} + +static void *get_dmabuf_ptr(struct drm_gem_object *obj) +{ + return (obj && obj->import_attach) ? obj->import_attach->dmabuf : NULL; +} + static dma_addr_t physaddr(struct drm_gem_object *obj) { struct msm_gem_object *msm_obj = to_msm_bo(obj); @@ -39,8 +186,7 @@ } /* allocate pages from VRAM carveout, used when no IOMMU: */ -static struct page **get_pages_vram(struct drm_gem_object *obj, - int npages) +static struct page **get_pages_vram(struct drm_gem_object *obj, int npages) { struct msm_gem_object *msm_obj = to_msm_bo(obj); struct msm_drm_private *priv = obj->dev->dev_private; @@ -52,8 +198,10 @@ if (!p) return ERR_PTR(-ENOMEM); + spin_lock(&priv->vram.lock); ret = drm_mm_insert_node(&priv->vram.mm, msm_obj->vram_node, npages, 0, DRM_MM_SEARCH_DEFAULT); + spin_unlock(&priv->vram.lock); if (ret) { drm_free_large(p); return ERR_PTR(ret); @@ -68,7 +216,6 @@ return p; } -/* called with dev->struct_mutex held */ static struct page **get_pages(struct drm_gem_object *obj) { struct msm_gem_object *msm_obj = to_msm_bo(obj); @@ -89,44 +236,80 @@ return p; } + msm_obj->pages = p; + msm_obj->sgt = drm_prime_pages_to_sg(p, npages); if (IS_ERR(msm_obj->sgt)) { - dev_err(dev->dev, "failed to allocate sgt\n"); - return ERR_CAST(msm_obj->sgt); - } + void *ptr = ERR_CAST(msm_obj->sgt); - msm_obj->pages = p; + msm_obj->sgt = NULL; + return ptr; + } - /* For non-cached buffers, ensure the new pages are clean - * because display controller, GPU, etc. are not coherent: + /* + * Make sure to flush the CPU cache for newly allocated memory + * so we don't get ourselves into trouble with a dirty cache */ if (msm_obj->flags & (MSM_BO_WC|MSM_BO_UNCACHED)) - dma_map_sg(dev->dev, msm_obj->sgt->sgl, + dma_sync_sg_for_device(dev->dev, msm_obj->sgt->sgl, msm_obj->sgt->nents, DMA_BIDIRECTIONAL); + + /* Secure the pages if we need to */ + if (use_pages(obj) && msm_obj->flags & MSM_BO_SECURE) { + int ret = protect_pages(msm_obj); + + if (ret) + return ERR_PTR(ret); + + /* + * Set a flag to indicate the pages are locked by us and + * need to be unlocked when the pages get freed + */ + msm_obj->flags |= MSM_BO_LOCKED; + } } return msm_obj->pages; } +static void put_pages_vram(struct drm_gem_object *obj) +{ + struct msm_gem_object *msm_obj = to_msm_bo(obj); + struct msm_drm_private *priv = obj->dev->dev_private; + + spin_lock(&priv->vram.lock); + drm_mm_remove_node(msm_obj->vram_node); + spin_unlock(&priv->vram.lock); + + drm_free_large(msm_obj->pages); +} + static void put_pages(struct drm_gem_object *obj) { struct msm_gem_object *msm_obj = to_msm_bo(obj); if (msm_obj->pages) { - /* For non-cached buffers, ensure the new pages are clean - * because display controller, GPU, etc. are not coherent: - */ - if (msm_obj->flags & (MSM_BO_WC|MSM_BO_UNCACHED)) - dma_unmap_sg(obj->dev->dev, msm_obj->sgt->sgl, - msm_obj->sgt->nents, DMA_BIDIRECTIONAL); + if (msm_obj->flags & MSM_BO_LOCKED) { + unprotect_pages(msm_obj); + msm_obj->flags &= ~MSM_BO_LOCKED; + } + + if (msm_obj->sgt) sg_free_table(msm_obj->sgt); kfree(msm_obj->sgt); - if (use_pages(obj)) - drm_gem_put_pages(obj, msm_obj->pages, true, false); - else { - drm_mm_remove_node(msm_obj->vram_node); - drm_free_large(msm_obj->pages); + if (use_pages(obj)) { + if (msm_obj->flags & MSM_BO_SVM) { + int npages = obj->size >> PAGE_SHIFT; + + release_pages(msm_obj->pages, npages, 0); + kfree(msm_obj->pages); + } else { + drm_gem_put_pages(obj, msm_obj->pages, + true, false); + } + } else { + put_pages_vram(obj); } msm_obj->pages = NULL; @@ -135,11 +318,12 @@ struct page **msm_gem_get_pages(struct drm_gem_object *obj) { - struct drm_device *dev = obj->dev; + struct msm_gem_object *msm_obj = to_msm_bo(obj); struct page **p; - mutex_lock(&dev->struct_mutex); + + mutex_lock(&msm_obj->lock); p = get_pages(obj); - mutex_unlock(&dev->struct_mutex); + mutex_unlock(&msm_obj->lock); return p; } @@ -153,6 +337,12 @@ { struct msm_gem_object *msm_obj = to_msm_bo(obj); + /* We can't mmap secure objects or SVM objects */ + if (msm_obj->flags & (MSM_BO_SECURE | MSM_BO_SVM)) { + drm_gem_vm_close(vma); + return -EACCES; + } + vma->vm_flags &= ~VM_PFNMAP; vma->vm_flags |= VM_MIXEDMAP; @@ -193,16 +383,17 @@ int msm_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf) { struct drm_gem_object *obj = vma->vm_private_data; - struct drm_device *dev = obj->dev; + struct msm_gem_object *msm_obj = to_msm_bo(obj); struct page **pages; unsigned long pfn; pgoff_t pgoff; int ret; - /* Make sure we don't parallel update on a fault, nor move or remove - * something from beneath our feet + /* + * vm_ops.open and close get and put a reference on obj. + * So, we dont need to hold one here. */ - ret = mutex_lock_interruptible(&dev->struct_mutex); + ret = mutex_lock_interruptible(&msm_obj->lock); if (ret) goto out; @@ -219,13 +410,13 @@ pfn = page_to_pfn(pages[pgoff]); - VERB("Inserting %p pfn %lx, pa %lx", vmf->virtual_address, + VERB("Inserting %pK pfn %lx, pa %lx", vmf->virtual_address, pfn, pfn << PAGE_SHIFT); ret = vm_insert_mixed(vma, (unsigned long)vmf->virtual_address, pfn); out_unlock: - mutex_unlock(&dev->struct_mutex); + mutex_unlock(&msm_obj->lock); out: switch (ret) { case -EAGAIN: @@ -249,9 +440,10 @@ static uint64_t mmap_offset(struct drm_gem_object *obj) { struct drm_device *dev = obj->dev; + struct msm_gem_object *msm_obj = to_msm_bo(obj); int ret; - WARN_ON(!mutex_is_locked(&dev->struct_mutex)); + WARN_ON(!mutex_is_locked(&msm_obj->lock)); /* Make it mmapable */ ret = drm_gem_create_mmap_offset(obj); @@ -267,85 +459,156 @@ uint64_t msm_gem_mmap_offset(struct drm_gem_object *obj) { uint64_t offset; - mutex_lock(&obj->dev->struct_mutex); + struct msm_gem_object *msm_obj = to_msm_bo(obj); + + mutex_lock(&msm_obj->lock); offset = mmap_offset(obj); - mutex_unlock(&obj->dev->struct_mutex); + mutex_unlock(&msm_obj->lock); return offset; } -/* should be called under struct_mutex.. although it can be called - * from atomic context without struct_mutex to acquire an extra - * iova ref if you know one is already held. - * - * That means when I do eventually need to add support for unpinning - * the refcnt counter needs to be atomic_t. - */ -int msm_gem_get_iova_locked(struct drm_gem_object *obj, int id, - uint32_t *iova) +static void obj_remove_domain(struct msm_gem_vma *domain) +{ + if (domain) { + list_del(&domain->list); + kfree(domain); + } +} + +/* Called with msm_obj->lock locked */ +static void +put_iova(struct drm_gem_object *obj) { struct msm_gem_object *msm_obj = to_msm_bo(obj); - int ret = 0; + struct msm_gem_svm_object *msm_svm_obj; + struct msm_gem_vma *domain, *tmp; + bool invalid = false; - if (!msm_obj->domain[id].iova) { - struct msm_drm_private *priv = obj->dev->dev_private; - struct page **pages = get_pages(obj); + WARN_ON(!mutex_is_locked(&msm_obj->lock)); - if (IS_ERR(pages)) - return PTR_ERR(pages); + if (msm_obj->flags & MSM_BO_SVM) { + msm_svm_obj = to_msm_svm_obj(msm_obj); + invalid = msm_svm_obj->invalid; + } + list_for_each_entry_safe(domain, tmp, &msm_obj->domains, list) { if (iommu_present(&platform_bus_type)) { - struct msm_mmu *mmu = priv->mmus[id]; - uint32_t offset; - - if (WARN_ON(!mmu)) - return -EINVAL; + msm_gem_unmap_vma(domain->aspace, domain, + msm_obj->sgt, get_dmabuf_ptr(obj), invalid); + } - offset = (uint32_t)mmap_offset(obj); - ret = mmu->funcs->map(mmu, offset, msm_obj->sgt, - obj->size, IOMMU_READ | IOMMU_WRITE); - msm_obj->domain[id].iova = offset; - } else { - msm_obj->domain[id].iova = physaddr(obj); + obj_remove_domain(domain); } } - if (!ret) - *iova = msm_obj->domain[id].iova; +static struct msm_gem_vma *obj_add_domain(struct drm_gem_object *obj, + struct msm_gem_address_space *aspace) +{ + struct msm_gem_object *msm_obj = to_msm_bo(obj); + struct msm_gem_vma *domain = kzalloc(sizeof(*domain), GFP_KERNEL); - return ret; + if (!domain) + return ERR_PTR(-ENOMEM); + + domain->aspace = aspace; + + list_add_tail(&domain->list, &msm_obj->domains); + + return domain; } -/* get iova, taking a reference. Should have a matching put */ -int msm_gem_get_iova(struct drm_gem_object *obj, int id, uint32_t *iova) +static struct msm_gem_vma *obj_get_domain(struct drm_gem_object *obj, + struct msm_gem_address_space *aspace) { struct msm_gem_object *msm_obj = to_msm_bo(obj); - int ret; + struct msm_gem_vma *domain; - /* this is safe right now because we don't unmap until the - * bo is deleted: - */ - if (msm_obj->domain[id].iova) { - *iova = msm_obj->domain[id].iova; + list_for_each_entry(domain, &msm_obj->domains, list) { + if (domain->aspace == aspace) + return domain; + } + + return NULL; +} + +#ifndef IOMMU_PRIV +#define IOMMU_PRIV 0 +#endif + +/* A reference to obj must be held before calling this function. */ +int msm_gem_get_iova(struct drm_gem_object *obj, + struct msm_gem_address_space *aspace, uint64_t *iova) +{ + struct msm_gem_object *msm_obj = to_msm_bo(obj); + struct page **pages; + struct msm_gem_vma *domain; + int ret = 0; + + mutex_lock(&msm_obj->lock); + + if (!iommu_present(&platform_bus_type)) { + pages = get_pages(obj); + + if (IS_ERR(pages)) { + mutex_unlock(&msm_obj->lock); + return PTR_ERR(pages); + } + + *iova = (uint64_t) physaddr(obj); + mutex_unlock(&msm_obj->lock); return 0; } - mutex_lock(&obj->dev->struct_mutex); - ret = msm_gem_get_iova_locked(obj, id, iova); - mutex_unlock(&obj->dev->struct_mutex); + domain = obj_get_domain(obj, aspace); + + if (!domain) { + domain = obj_add_domain(obj, aspace); + if (IS_ERR(domain)) { + mutex_unlock(&msm_obj->lock); + return PTR_ERR(domain); + } + + pages = get_pages(obj); + if (IS_ERR(pages)) { + obj_remove_domain(domain); + mutex_unlock(&msm_obj->lock); + return PTR_ERR(pages); + } + + ret = msm_gem_map_vma(aspace, domain, msm_obj->sgt, + get_dmabuf_ptr(obj), msm_obj->flags); + } + + if (!ret) + *iova = domain->iova; + else + obj_remove_domain(domain); + + mutex_unlock(&msm_obj->lock); return ret; } /* get iova without taking a reference, used in places where you have * already done a 'msm_gem_get_iova()'. */ -uint32_t msm_gem_iova(struct drm_gem_object *obj, int id) +uint64_t msm_gem_iova(struct drm_gem_object *obj, + struct msm_gem_address_space *aspace) { struct msm_gem_object *msm_obj = to_msm_bo(obj); - WARN_ON(!msm_obj->domain[id].iova); - return msm_obj->domain[id].iova; + struct msm_gem_vma *domain; + uint64_t iova; + + mutex_lock(&msm_obj->lock); + domain = obj_get_domain(obj, aspace); + WARN_ON(!domain); + iova = domain ? domain->iova : 0; + mutex_unlock(&msm_obj->lock); + + return iova; } -void msm_gem_put_iova(struct drm_gem_object *obj, int id) +void msm_gem_put_iova(struct drm_gem_object *obj, + struct msm_gem_address_space *aspace) { // XXX TODO .. // NOTE: probably don't need a _locked() version.. we wouldn't @@ -385,27 +648,31 @@ return ret; } -void *msm_gem_vaddr_locked(struct drm_gem_object *obj) +void *msm_gem_vaddr(struct drm_gem_object *obj) { struct msm_gem_object *msm_obj = to_msm_bo(obj); - WARN_ON(!mutex_is_locked(&obj->dev->struct_mutex)); - if (!msm_obj->vaddr) { + + mutex_lock(&msm_obj->lock); + + if (msm_obj->vaddr) { + mutex_unlock(&msm_obj->lock); + return msm_obj->vaddr; + } + + if (obj->import_attach) { + msm_obj->vaddr = dma_buf_vmap(obj->import_attach->dmabuf); + } else { struct page **pages = get_pages(obj); - if (IS_ERR(pages)) + if (IS_ERR(pages)) { + mutex_unlock(&msm_obj->lock); return ERR_CAST(pages); + } msm_obj->vaddr = vmap(pages, obj->size >> PAGE_SHIFT, VM_MAP, pgprot_writecombine(PAGE_KERNEL)); } - return msm_obj->vaddr; -} + mutex_unlock(&msm_obj->lock); -void *msm_gem_vaddr(struct drm_gem_object *obj) -{ - void *ret; - mutex_lock(&obj->dev->struct_mutex); - ret = msm_gem_vaddr_locked(obj); - mutex_unlock(&obj->dev->struct_mutex); - return ret; + return msm_obj->vaddr; } /* setup callback for when bo is no longer busy.. @@ -474,19 +741,46 @@ return 0; } +void msm_gem_sync(struct drm_gem_object *obj, u32 op) +{ + struct drm_device *dev = obj->dev; + struct msm_gem_object *msm_obj = to_msm_bo(obj); + + if (msm_obj->flags & (MSM_BO_WC|MSM_BO_UNCACHED)) + return; + + switch (op) { + case MSM_GEM_SYNC_TO_CPU: + dma_sync_sg_for_cpu(dev->dev, msm_obj->sgt->sgl, + msm_obj->sgt->nents, DMA_BIDIRECTIONAL); + break; + case MSM_GEM_SYNC_TO_DEV: + dma_sync_sg_for_device(dev->dev, msm_obj->sgt->sgl, + msm_obj->sgt->nents, DMA_BIDIRECTIONAL); + break; + } +} + #ifdef CONFIG_DEBUG_FS void msm_gem_describe(struct drm_gem_object *obj, struct seq_file *m) { struct drm_device *dev = obj->dev; struct msm_gem_object *msm_obj = to_msm_bo(obj); + struct msm_gem_vma *domain; uint64_t off = drm_vma_node_start(&obj->vma_node); WARN_ON(!mutex_is_locked(&dev->struct_mutex)); - seq_printf(m, "%08x: %c(r=%u,w=%u) %2d (%2d) %08llx %p %zu\n", + seq_printf(m, "%08x: %c(r=%u,w=%u) %2d (%2d) %08llx %pK\t", msm_obj->flags, is_active(msm_obj) ? 'A' : 'I', msm_obj->read_fence, msm_obj->write_fence, obj->name, obj->refcount.refcount.counter, - off, msm_obj->vaddr, obj->size); + off, msm_obj->vaddr); + + /* FIXME: we need to print the address space here too */ + list_for_each_entry(domain, &msm_obj->domains, list) + seq_printf(m, " %08llx", domain->iova); + + seq_puts(m, "\n"); } void msm_gem_describe_objects(struct list_head *list, struct seq_file *m) @@ -510,29 +804,33 @@ void msm_gem_free_object(struct drm_gem_object *obj) { struct drm_device *dev = obj->dev; - struct msm_drm_private *priv = obj->dev->dev_private; struct msm_gem_object *msm_obj = to_msm_bo(obj); - int id; + struct msm_gem_svm_object *msm_svm_obj = NULL; WARN_ON(!mutex_is_locked(&dev->struct_mutex)); /* object should not be on active list: */ WARN_ON(is_active(msm_obj)); + if (msm_obj->flags & MSM_BO_SVM) + msm_svm_obj = to_msm_svm_obj(msm_obj); + list_del(&msm_obj->mm_list); - for (id = 0; id < ARRAY_SIZE(msm_obj->domain); id++) { - struct msm_mmu *mmu = priv->mmus[id]; - if (mmu && msm_obj->domain[id].iova) { - uint32_t offset = msm_obj->domain[id].iova; - mmu->funcs->unmap(mmu, offset, msm_obj->sgt, obj->size); - } + /* Unregister SVM object from mmu notifications */ + if (msm_obj->flags & MSM_BO_SVM) { + msm_gem_mn_unregister(msm_svm_obj); + msm_gem_mn_put(msm_svm_obj->msm_mn); + msm_svm_obj->msm_mn = NULL; } + mutex_lock(&msm_obj->lock); + put_iova(obj); + if (obj->import_attach) { if (msm_obj->vaddr) - dma_buf_vunmap(obj->import_attach->dmabuf, msm_obj->vaddr); - + dma_buf_vunmap(obj->import_attach->dmabuf, + msm_obj->vaddr); /* Don't drop the pages for imported dmabuf, as they are not * ours, just free the array we allocated: */ @@ -549,7 +847,11 @@ reservation_object_fini(msm_obj->resv); drm_gem_object_release(obj); + mutex_unlock(&msm_obj->lock); + if (msm_obj->flags & MSM_BO_SVM) + kfree(msm_svm_obj); + else kfree(msm_obj); } @@ -560,13 +862,28 @@ struct drm_gem_object *obj; int ret; - ret = mutex_lock_interruptible(&dev->struct_mutex); - if (ret) + obj = msm_gem_new(dev, size, flags); + + if (IS_ERR(obj)) + return PTR_ERR(obj); + + ret = drm_gem_handle_create(file, obj, handle); + + /* drop reference from allocate - handle holds it now */ + drm_gem_object_unreference_unlocked(obj); + return ret; +} - obj = msm_gem_new(dev, size, flags); +/* convenience method to construct an SVM buffer object, and userspace handle */ +int msm_gem_svm_new_handle(struct drm_device *dev, struct drm_file *file, + uint64_t hostptr, uint64_t size, + uint32_t flags, uint32_t *handle) +{ + struct drm_gem_object *obj; + int ret; - mutex_unlock(&dev->struct_mutex); + obj = msm_gem_svm_new(dev, file, hostptr, size, flags); if (IS_ERR(obj)) return PTR_ERR(obj); @@ -579,13 +896,11 @@ return ret; } -static int msm_gem_new_impl(struct drm_device *dev, +static int msm_gem_obj_init(struct drm_device *dev, uint32_t size, uint32_t flags, - struct drm_gem_object **obj) + struct msm_gem_object *msm_obj, bool struct_mutex_locked) { struct msm_drm_private *priv = dev->dev_private; - struct msm_gem_object *msm_obj; - unsigned sz; bool use_vram = false; switch (flags & MSM_BO_CACHE_MASK) { @@ -607,43 +922,72 @@ if (WARN_ON(use_vram && !priv->vram.size)) return -EINVAL; - sz = sizeof(*msm_obj); - if (use_vram) - sz += sizeof(struct drm_mm_node); + mutex_init(&msm_obj->lock); - msm_obj = kzalloc(sz, GFP_KERNEL); - if (!msm_obj) - return -ENOMEM; + if (use_vram) { + struct msm_gem_vma *domain = obj_add_domain(&msm_obj->base, 0); - if (use_vram) - msm_obj->vram_node = (void *)&msm_obj[1]; + if (!IS_ERR(domain)) + msm_obj->vram_node = &domain->node; + } msm_obj->flags = flags; msm_obj->resv = &msm_obj->_resv; reservation_object_init(msm_obj->resv); + INIT_LIST_HEAD(&msm_obj->mm_list); INIT_LIST_HEAD(&msm_obj->submit_entry); - list_add_tail(&msm_obj->mm_list, &priv->inactive_list); + INIT_LIST_HEAD(&msm_obj->domains); - *obj = &msm_obj->base; + if (struct_mutex_locked) { + list_add_tail(&msm_obj->mm_list, &priv->inactive_list); + } else { + mutex_lock(&dev->struct_mutex); + list_add_tail(&msm_obj->mm_list, &priv->inactive_list); + mutex_unlock(&dev->struct_mutex); + } return 0; } -struct drm_gem_object *msm_gem_new(struct drm_device *dev, - uint32_t size, uint32_t flags) +static struct drm_gem_object *msm_gem_new_impl(struct drm_device *dev, + uint32_t size, uint32_t flags, bool struct_mutex_locked) { - struct drm_gem_object *obj = NULL; + struct msm_gem_object *msm_obj; int ret; - WARN_ON(!mutex_is_locked(&dev->struct_mutex)); + msm_obj = kzalloc(sizeof(*msm_obj), GFP_KERNEL); + if (!msm_obj) + return ERR_PTR(-ENOMEM); + + ret = msm_gem_obj_init(dev, size, flags, msm_obj, struct_mutex_locked); + if (ret) { + kfree(msm_obj); + return ERR_PTR(ret); + } + + return &msm_obj->base; +} + +static struct drm_gem_object *_msm_gem_new(struct drm_device *dev, + uint32_t size, uint32_t flags, bool struct_mutex_locked) +{ + struct drm_gem_object *obj; + int ret; size = PAGE_ALIGN(size); - ret = msm_gem_new_impl(dev, size, flags, &obj); - if (ret) - goto fail; + /* + * Disallow zero sized objects as they make the underlying + * infrastructure grumpy + */ + if (!size) + return ERR_PTR(-EINVAL); + + obj = msm_gem_new_impl(dev, size, flags, struct_mutex_locked); + if (IS_ERR(obj)) + return obj; if (use_pages(obj)) { ret = drm_gem_object_init(dev, obj, size); @@ -656,14 +1000,166 @@ return obj; fail: - if (obj) - drm_gem_object_unreference(obj); + drm_gem_object_unreference_unlocked(obj); + + return ERR_PTR(ret); +} + +struct drm_gem_object *msm_gem_new_locked(struct drm_device *dev, + uint32_t size, uint32_t flags) +{ + return _msm_gem_new(dev, size, flags, true); +} + +struct drm_gem_object *msm_gem_new(struct drm_device *dev, + uint32_t size, uint32_t flags) +{ + return _msm_gem_new(dev, size, flags, false); +} + +static struct drm_gem_object *msm_svm_gem_new_impl(struct drm_device *dev, + uint32_t size, uint32_t flags) +{ + struct msm_gem_svm_object *msm_svm_obj; + struct msm_gem_object *msm_obj; + int ret; + + msm_svm_obj = kzalloc(sizeof(*msm_svm_obj), GFP_KERNEL); + if (!msm_svm_obj) + return ERR_PTR(-ENOMEM); + + msm_obj = &msm_svm_obj->msm_obj_base; + + ret = msm_gem_obj_init(dev, size, flags | MSM_BO_SVM, msm_obj, false); + if (ret) { + kfree(msm_svm_obj); + return ERR_PTR(ret); + } + + return &msm_obj->base; +} + +/* convenience method to construct an SVM GEM bo, and userspace handle */ +struct drm_gem_object *msm_gem_svm_new(struct drm_device *dev, + struct drm_file *file, uint64_t hostptr, + uint64_t size, uint32_t flags) +{ + struct drm_gem_object *obj; + struct msm_file_private *ctx = file->driver_priv; + struct msm_gem_address_space *aspace; + struct msm_gem_object *msm_obj; + struct msm_gem_svm_object *msm_svm_obj; + struct msm_gem_vma *domain = NULL; + struct page **p; + int npages; + int num_pinned = 0; + int write; + int ret; + + if (!ctx) + return ERR_PTR(-ENODEV); + + /* if we don't have IOMMU, don't bother pretending we can import: */ + if (!iommu_present(&platform_bus_type)) { + dev_err_once(dev->dev, "cannot import without IOMMU\n"); + return ERR_PTR(-EINVAL); + } + + /* hostptr and size must be page-aligned */ + if (offset_in_page(hostptr | size)) + return ERR_PTR(-EINVAL); + + /* Only CPU cached SVM objects are allowed */ + if ((flags & MSM_BO_CACHE_MASK) != MSM_BO_CACHED) + return ERR_PTR(-EINVAL); + + /* Allocate and initialize a new msm_gem_object */ + obj = msm_svm_gem_new_impl(dev, size, flags); + if (IS_ERR(obj)) + return obj; + + drm_gem_private_object_init(dev, obj, size); + + msm_obj = to_msm_bo(obj); + aspace = ctx->aspace; + domain = obj_add_domain(&msm_obj->base, aspace); + if (IS_ERR(domain)) { + drm_gem_object_unreference_unlocked(obj); + return ERR_CAST(domain); + } + + /* Reserve iova if not already in use, else fail */ + ret = msm_gem_reserve_iova(aspace, domain, hostptr, size); + if (ret) { + obj_remove_domain(domain); + drm_gem_object_unreference_unlocked(obj); + return ERR_PTR(ret); + } + + msm_svm_obj = to_msm_svm_obj(msm_obj); + msm_svm_obj->hostptr = hostptr; + msm_svm_obj->invalid = false; + + ret = msm_gem_mn_register(msm_svm_obj, aspace); + if (ret) + goto fail; + + /* + * Get physical pages and map into smmu in the ioctl itself. + * The driver handles iova allocation, physical page allocation and + * SMMU map all in one go. If we break this, then we have to maintain + * state to tell if physical pages allocation/map needs to happen. + * For SVM, iova reservation needs to happen in the ioctl itself, + * so do the rest right here as well. + */ + npages = size >> PAGE_SHIFT; + p = kcalloc(npages, sizeof(struct page *), GFP_KERNEL); + if (!p) { + ret = -ENOMEM; + goto fail; + } + + write = (msm_obj->flags & MSM_BO_GPU_READONLY) ? 0 : 1; + /* This may hold mm->mmap_sem */ + num_pinned = get_user_pages_fast(hostptr, npages, write, p); + if (num_pinned != npages) { + ret = -EINVAL; + goto free_pages; + } + + msm_obj->sgt = drm_prime_pages_to_sg(p, npages); + if (IS_ERR(msm_obj->sgt)) { + ret = PTR_ERR(msm_obj->sgt); + goto free_pages; + } + + msm_obj->pages = p; + + ret = aspace->mmu->funcs->map(aspace->mmu, domain->iova, + msm_obj->sgt, msm_obj->flags, get_dmabuf_ptr(obj)); + if (ret) + goto free_pages; + + kref_get(&aspace->kref); + + return obj; + +free_pages: + release_pages(p, num_pinned, 0); + kfree(p); + +fail: + if (domain) + msm_gem_release_iova(aspace, domain); + + obj_remove_domain(domain); + drm_gem_object_unreference_unlocked(obj); return ERR_PTR(ret); } struct drm_gem_object *msm_gem_import(struct drm_device *dev, - uint32_t size, struct sg_table *sgt) + uint32_t size, struct sg_table *sgt, u32 flags) { struct msm_gem_object *msm_obj; struct drm_gem_object *obj; @@ -677,31 +1173,167 @@ size = PAGE_ALIGN(size); - ret = msm_gem_new_impl(dev, size, MSM_BO_WC, &obj); - if (ret) - goto fail; + obj = msm_gem_new_impl(dev, size, MSM_BO_WC, false); + if (IS_ERR(obj)) + return obj; drm_gem_private_object_init(dev, obj, size); npages = size / PAGE_SIZE; msm_obj = to_msm_bo(obj); + mutex_lock(&msm_obj->lock); msm_obj->sgt = sgt; msm_obj->pages = drm_malloc_ab(npages, sizeof(struct page *)); if (!msm_obj->pages) { + mutex_unlock(&msm_obj->lock); ret = -ENOMEM; goto fail; } - ret = drm_prime_sg_to_page_addr_arrays(sgt, msm_obj->pages, NULL, npages); - if (ret) + /* OR the passed in flags */ + msm_obj->flags |= flags; + + ret = drm_prime_sg_to_page_addr_arrays(sgt, msm_obj->pages, + NULL, npages); + if (ret) { + mutex_unlock(&msm_obj->lock); goto fail; + } + + mutex_unlock(&msm_obj->lock); return obj; fail: - if (obj) drm_gem_object_unreference_unlocked(obj); return ERR_PTR(ret); } + +/* Timeout in ms, long enough so we are sure the GPU is hung */ +#define SVM_OBJ_WAIT_TIMEOUT 10000 +static void invalidate_svm_object(struct msm_gem_svm_object *msm_svm_obj) +{ + struct msm_gem_object *msm_obj = &msm_svm_obj->msm_obj_base; + struct drm_device *dev = msm_obj->base.dev; + struct msm_gem_vma *domain, *tmp; + uint32_t fence; + int ret; + + if (is_active(msm_obj)) { + ktime_t timeout = ktime_add_ms(ktime_get(), + SVM_OBJ_WAIT_TIMEOUT); + + /* Get the most recent fence that touches the object */ + fence = msm_gem_fence(msm_obj, MSM_PREP_READ | MSM_PREP_WRITE); + + /* Wait for the fence to retire */ + ret = msm_wait_fence(dev, fence, &timeout, true); + if (ret) + /* The GPU could be hung! Not much we can do */ + dev_err(dev->dev, "drm: Error (%d) waiting for svm object: 0x%llx", + ret, msm_svm_obj->hostptr); + } + + /* GPU is done, unmap object from SMMU */ + mutex_lock(&msm_obj->lock); + list_for_each_entry_safe(domain, tmp, &msm_obj->domains, list) { + struct msm_gem_address_space *aspace = domain->aspace; + + if (domain->iova) + aspace->mmu->funcs->unmap(aspace->mmu, + domain->iova, msm_obj->sgt, + get_dmabuf_ptr(&msm_obj->base)); + } + /* Let go of the physical pages */ + put_pages(&msm_obj->base); + mutex_unlock(&msm_obj->lock); +} + +void msm_mn_invalidate_range_start(struct mmu_notifier *mn, + struct mm_struct *mm, unsigned long start, unsigned long end) +{ + struct msm_mmu_notifier *msm_mn = + container_of(mn, struct msm_mmu_notifier, mn); + struct interval_tree_node *itn = NULL; + struct msm_gem_svm_object *msm_svm_obj; + struct drm_gem_object *obj; + LIST_HEAD(inv_list); + + if (!msm_gem_mn_get(msm_mn)) + return; + + spin_lock(&msm_mn->svm_tree_lock); + itn = interval_tree_iter_first(&msm_mn->svm_tree, start, end - 1); + while (itn) { + msm_svm_obj = container_of(itn, + struct msm_gem_svm_object, svm_node); + obj = &msm_svm_obj->msm_obj_base.base; + + if (kref_get_unless_zero(&obj->refcount)) + list_add(&msm_svm_obj->lnode, &inv_list); + + itn = interval_tree_iter_next(itn, start, end - 1); + } + spin_unlock(&msm_mn->svm_tree_lock); + + list_for_each_entry(msm_svm_obj, &inv_list, lnode) { + obj = &msm_svm_obj->msm_obj_base.base; + /* Unregister SVM object from mmu notifications */ + msm_gem_mn_unregister(msm_svm_obj); + msm_svm_obj->invalid = true; + invalidate_svm_object(msm_svm_obj); + drm_gem_object_unreference_unlocked(obj); + } + + msm_gem_mn_put(msm_mn); +} + +/* + * Helper function to consolidate in-kernel buffer allocations that usually need + * to allocate a buffer object, iova and a virtual address all in one shot + */ +static void *_msm_gem_kernel_new(struct drm_device *dev, uint32_t size, + uint32_t flags, struct msm_gem_address_space *aspace, + struct drm_gem_object **bo, uint64_t *iova, bool locked) +{ + void *vaddr; + struct drm_gem_object *obj = _msm_gem_new(dev, size, flags, locked); + int ret; + + if (IS_ERR(obj)) + return ERR_CAST(obj); + + ret = msm_gem_get_iova(obj, aspace, iova); + if (ret) { + drm_gem_object_unreference(obj); + return ERR_PTR(ret); + } + + vaddr = msm_gem_vaddr(obj); + if (!vaddr) { + msm_gem_put_iova(obj, aspace); + drm_gem_object_unreference(obj); + return ERR_PTR(-ENOMEM); + } + + *bo = obj; + return vaddr; +} + +void *msm_gem_kernel_new(struct drm_device *dev, uint32_t size, + uint32_t flags, struct msm_gem_address_space *aspace, + struct drm_gem_object **bo, uint64_t *iova) +{ + return _msm_gem_kernel_new(dev, size, flags, aspace, bo, iova, + false); +} + +void *msm_gem_kernel_new_locked(struct drm_device *dev, uint32_t size, + uint32_t flags, struct msm_gem_address_space *aspace, + struct drm_gem_object **bo, uint64_t *iova) +{ + return _msm_gem_kernel_new(dev, size, flags, aspace, bo, iova, + true); +} diff -ruw linux-4.4.115/drivers/gpu/drm/msm/msm_gem.h linux-4.4.115-fbx/drivers/gpu/drm/msm/msm_gem.h --- linux-4.4.115/drivers/gpu/drm/msm/msm_gem.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/gpu/drm/msm/msm_gem.h 2019-01-22 16:16:23.507246443 +0100 @@ -18,11 +18,33 @@ #ifndef __MSM_GEM_H__ #define __MSM_GEM_H__ +#include #include +#include +#include #include "msm_drv.h" /* Additional internal-use only BO flags: */ #define MSM_BO_STOLEN 0x10000000 /* try to use stolen/splash memory */ +#define MSM_BO_LOCKED 0x20000000 /* Pages have been securely locked */ +#define MSM_BO_SVM 0x40000000 /* bo is SVM */ + +struct msm_gem_address_space { + const char *name; + struct msm_mmu *mmu; + struct kref kref; + struct drm_mm mm; + spinlock_t lock; /* Protects drm_mm node allocation/removal */ + u64 va_len; +}; + +struct msm_gem_vma { + /* Node used by the GPU address space, but not the SDE address space */ + struct drm_mm_node node; + struct msm_gem_address_space *aspace; + uint64_t iova; + struct list_head list; +}; struct msm_gem_object { struct drm_gem_object base; @@ -52,10 +74,7 @@ struct sg_table *sgt; void *vaddr; - struct { - // XXX - uint32_t iova; - } domain[NUM_DOMAINS]; + struct list_head domains; /* normally (resv == &_resv) except for imported bo's */ struct reservation_object *resv; @@ -65,9 +84,36 @@ * an IOMMU. Also used for stolen/splashscreen buffer. */ struct drm_mm_node *vram_node; + struct mutex lock; /* Protects resources associated with bo */ }; #define to_msm_bo(x) container_of(x, struct msm_gem_object, base) +struct msm_mmu_notifier { + struct mmu_notifier mn; + struct mm_struct *mm; /* mm_struct owning the mmu notifier mn */ + struct hlist_node node; + struct rb_root svm_tree; /* interval tree holding all svm bos */ + spinlock_t svm_tree_lock; /* Protects svm_tree*/ + struct msm_drm_private *msm_dev; + struct kref refcount; +}; + +struct msm_gem_svm_object { + struct msm_gem_object msm_obj_base; + uint64_t hostptr; + struct mm_struct *mm; /* mm_struct the svm bo belongs to */ + struct interval_tree_node svm_node; + struct msm_mmu_notifier *msm_mn; + struct list_head lnode; + /* bo has been unmapped on CPU, cannot be part of GPU submits */ + bool invalid; +}; + +#define to_msm_svm_obj(x) \ + ((struct msm_gem_svm_object *) \ + container_of(x, struct msm_gem_svm_object, msm_obj_base)) + + static inline bool is_active(struct msm_gem_object *msm_obj) { return msm_obj->gpu != NULL; @@ -86,7 +132,8 @@ return fence; } -#define MAX_CMDS 4 +/* Internal submit flags */ +#define SUBMIT_FLAG_SKIP_HANGCHECK 0x00000001 /* Created per submit-ioctl, to track bo's and cmdstream bufs, etc, * associated with the cmdstream submission for synchronization (and @@ -95,24 +142,30 @@ */ struct msm_gem_submit { struct drm_device *dev; - struct msm_gpu *gpu; - struct list_head node; /* node in gpu submit_list */ + struct msm_gem_address_space *aspace; + struct list_head node; /* node in ring submit list */ struct list_head bo_list; struct ww_acquire_ctx ticket; uint32_t fence; - bool valid; + int ring; + u32 flags; + uint64_t profile_buf_iova; + struct drm_msm_gem_submit_profile_buffer *profile_buf; + bool secure; + struct msm_gpu_submitqueue *queue; + int tick_index; unsigned int nr_cmds; unsigned int nr_bos; struct { uint32_t type; uint32_t size; /* in dwords */ - uint32_t iova; + uint64_t iova; uint32_t idx; /* cmdstream buffer idx in bos[] */ - } cmd[MAX_CMDS]; + } *cmd; /* array of size nr_cmds */ struct { uint32_t flags; struct msm_gem_object *obj; - uint32_t iova; + uint64_t iova; } bos[0]; }; diff -ruw linux-4.4.115/drivers/gpu/drm/msm/msm_gem_prime.c linux-4.4.115-fbx/drivers/gpu/drm/msm/msm_gem_prime.c --- linux-4.4.115/drivers/gpu/drm/msm/msm_gem_prime.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/gpu/drm/msm/msm_gem_prime.c 2019-01-22 16:16:23.507246443 +0100 @@ -19,6 +19,7 @@ #include "msm_gem.h" #include +#include struct sg_table *msm_gem_prime_get_sg_table(struct drm_gem_object *obj) { @@ -55,7 +56,16 @@ struct drm_gem_object *msm_gem_prime_import_sg_table(struct drm_device *dev, struct dma_buf_attachment *attach, struct sg_table *sg) { - return msm_gem_import(dev, attach->dmabuf->size, sg); + u32 flags = 0; + + /* + * Check to see if this is a secure buffer by way of Ion and set the + * appropriate flag if so. + */ + if (ion_dma_buf_is_secure(attach->dmabuf)) + flags |= MSM_BO_SECURE; + + return msm_gem_import(dev, attach->dmabuf->size, sg, flags); } int msm_gem_prime_pin(struct drm_gem_object *obj) diff -ruw linux-4.4.115/drivers/gpu/drm/msm/msm_gem_submit.c linux-4.4.115-fbx/drivers/gpu/drm/msm/msm_gem_submit.c --- linux-4.4.115/drivers/gpu/drm/msm/msm_gem_submit.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/gpu/drm/msm/msm_gem_submit.c 2019-10-29 09:26:23.633203080 +0100 @@ -18,6 +18,7 @@ #include "msm_drv.h" #include "msm_gpu.h" #include "msm_gem.h" +#include "msm_trace.h" /* * Cmdstream submission: @@ -28,16 +29,14 @@ #define BO_LOCKED 0x4000 #define BO_PINNED 0x2000 -static inline void __user *to_user_ptr(u64 address) -{ - return (void __user *)(uintptr_t)address; -} - static struct msm_gem_submit *submit_create(struct drm_device *dev, - struct msm_gpu *gpu, uint32_t nr) + struct msm_gem_address_space *aspace, + uint32_t nr_bos, uint32_t nr_cmds, + struct msm_gpu_submitqueue *queue) { struct msm_gem_submit *submit; - uint64_t sz = sizeof(*submit) + ((u64)nr * sizeof(submit->bos[0])); + uint64_t sz = sizeof(*submit) + ((u64)nr_bos * sizeof(submit->bos[0])) + + ((u64)nr_cmds * sizeof(submit->cmd[0])); if (sz > SIZE_MAX) return NULL; @@ -45,12 +44,24 @@ submit = kmalloc(sz, GFP_TEMPORARY | __GFP_NOWARN | __GFP_NORETRY); if (submit) { submit->dev = dev; - submit->gpu = gpu; + submit->aspace = aspace; + submit->queue = queue; /* initially, until copy_from_user() and bo lookup succeeds: */ submit->nr_bos = 0; submit->nr_cmds = 0; + submit->profile_buf = NULL; + submit->profile_buf_iova = 0; + submit->cmd = (void *)&submit->bos[nr_bos]; + + submit->secure = false; + + /* + * Initalize node so we can safely list_del() on it if + * we fail in the submit path + */ + INIT_LIST_HEAD(&submit->node); INIT_LIST_HEAD(&submit->bo_list); ww_acquire_init(&submit->ticket, &reservation_ww_class); } @@ -66,7 +77,18 @@ return -EFAULT; } -static int submit_lookup_objects(struct msm_gem_submit *submit, +void msm_gem_submit_free(struct msm_gem_submit *submit) +{ + if (!submit) + return; + + msm_submitqueue_put(submit->queue); + list_del(&submit->node); + kfree(submit); +} + +static int submit_lookup_objects(struct msm_gpu *gpu, + struct msm_gem_submit *submit, struct drm_msm_gem_submit *args, struct drm_file *file) { unsigned i; @@ -80,15 +102,18 @@ struct drm_gem_object *obj; struct msm_gem_object *msm_obj; void __user *userptr = - to_user_ptr(args->bos + (i * sizeof(submit_bo))); + u64_to_user_ptr(args->bos + (i * sizeof(submit_bo))); - ret = copy_from_user_inatomic(&submit_bo, userptr, sizeof(submit_bo)); - if (unlikely(ret)) { + if (copy_from_user_inatomic(&submit_bo, userptr, + sizeof(submit_bo))) { pagefault_enable(); spin_unlock(&file->table_lock); - ret = copy_from_user(&submit_bo, userptr, sizeof(submit_bo)); - if (ret) + if (copy_from_user(&submit_bo, userptr, + sizeof(submit_bo))) { + ret = -EFAULT; goto out; + } + spin_lock(&file->table_lock); pagefault_disable(); } @@ -116,6 +141,20 @@ msm_obj = to_msm_bo(obj); + /* + * If the buffer is marked as secure make sure that we can + * handle secure buffers and then mark the submission as secure + */ + if (msm_obj->flags & MSM_BO_SECURE) { + if (!gpu->secure_aspace) { + DRM_ERROR("Cannot handle secure buffers\n"); + ret = -EINVAL; + goto out_unlock; + } + + submit->secure = true; + } + if (!list_empty(&msm_obj->submit_entry)) { DRM_ERROR("handle %u at index %u already on submit list\n", submit_bo.handle, i); @@ -140,12 +179,17 @@ return ret; } -static void submit_unlock_unpin_bo(struct msm_gem_submit *submit, int i) +static void submit_unlock_unpin_bo(struct msm_gpu *gpu, + struct msm_gem_submit *submit, int i) { struct msm_gem_object *msm_obj = submit->bos[i].obj; + struct msm_gem_address_space *aspace; + + aspace = (msm_obj->flags & MSM_BO_SECURE) ? + gpu->secure_aspace : submit->aspace; if (submit->bos[i].flags & BO_PINNED) - msm_gem_put_iova(&msm_obj->base, submit->gpu->id); + msm_gem_put_iova(&msm_obj->base, aspace); if (submit->bos[i].flags & BO_LOCKED) ww_mutex_unlock(&msm_obj->resv->lock); @@ -157,16 +201,14 @@ } /* This is where we make sure all the bo's are reserved and pin'd: */ -static int submit_validate_objects(struct msm_gem_submit *submit) +static int submit_validate_objects(struct msm_gpu *gpu, + struct msm_gem_submit *submit) { int contended, slow_locked = -1, i, ret = 0; retry: - submit->valid = true; - for (i = 0; i < submit->nr_bos; i++) { struct msm_gem_object *msm_obj = submit->bos[i].obj; - uint32_t iova; if (slow_locked == i) slow_locked = -1; @@ -181,28 +223,17 @@ submit->bos[i].flags |= BO_LOCKED; } - - /* if locking succeeded, pin bo: */ - ret = msm_gem_get_iova_locked(&msm_obj->base, - submit->gpu->id, &iova); - - /* this would break the logic in the fail path.. there is no - * reason for this to happen, but just to be on the safe side - * let's notice if this starts happening in the future: + /* + * An invalid SVM object is part of + * this submit's buffer list, fail. */ - WARN_ON(ret == -EDEADLK); - - if (ret) + if (msm_obj->flags & MSM_BO_SVM) { + struct msm_gem_svm_object *msm_svm_obj = + to_msm_svm_obj(msm_obj); + if (msm_svm_obj->invalid) { + ret = -EINVAL; goto fail; - - submit->bos[i].flags |= BO_PINNED; - - if (iova == submit->bos[i].iova) { - submit->bos[i].flags |= BO_VALID; - } else { - submit->bos[i].iova = iova; - submit->bos[i].flags &= ~BO_VALID; - submit->valid = false; + } } } @@ -212,10 +243,10 @@ fail: for (; i >= 0; i--) - submit_unlock_unpin_bo(submit, i); + submit_unlock_unpin_bo(gpu, submit, i); if (slow_locked > 0) - submit_unlock_unpin_bo(submit, slow_locked); + submit_unlock_unpin_bo(gpu, submit, slow_locked); if (ret == -EDEADLK) { struct msm_gem_object *msm_obj = submit->bos[contended].obj; @@ -232,9 +263,14 @@ return ret; } -static int submit_bo(struct msm_gem_submit *submit, uint32_t idx, - struct msm_gem_object **obj, uint32_t *iova, bool *valid) +static int submit_bo(struct msm_gpu *gpu, + struct msm_gem_submit *submit, uint32_t idx, + struct msm_gem_object **obj, uint64_t *iova, bool *valid) { + struct msm_gem_object *msm_obj; + struct msm_gem_address_space *aspace; + int ret; + if (idx >= submit->nr_bos) { DRM_ERROR("invalid buffer index: %u (out of %u)\n", idx, submit->nr_bos); @@ -243,6 +279,39 @@ if (obj) *obj = submit->bos[idx].obj; + + /* Only map and pin if the caller needs either the iova or valid */ + if (!iova && !valid) + return 0; + + if (!(submit->bos[idx].flags & BO_PINNED)) { + uint64_t buf_iova; + + msm_obj = submit->bos[idx].obj; + aspace = (msm_obj->flags & MSM_BO_SECURE) ? + gpu->secure_aspace : submit->aspace; + + ret = msm_gem_get_iova(&msm_obj->base, aspace, &buf_iova); + + /* this would break the logic in the fail path.. there is no + * reason for this to happen, but just to be on the safe side + * let's notice if this starts happening in the future: + */ + WARN_ON(ret == -EDEADLK); + + if (ret) + return ret; + + submit->bos[idx].flags |= BO_PINNED; + + if (buf_iova == submit->bos[idx].iova) { + submit->bos[idx].flags |= BO_VALID; + } else { + submit->bos[idx].iova = buf_iova; + submit->bos[idx].flags &= ~BO_VALID; + } + } + if (iova) *iova = submit->bos[idx].iova; if (valid) @@ -252,8 +321,10 @@ } /* process the reloc's and patch up the cmdstream as needed: */ -static int submit_reloc(struct msm_gem_submit *submit, struct msm_gem_object *obj, - uint32_t offset, uint32_t nr_relocs, uint64_t relocs) +static int submit_reloc(struct msm_gpu *gpu, + struct msm_gem_submit *submit, + struct msm_gem_object *obj, uint32_t offset, + uint32_t nr_relocs, uint64_t relocs) { uint32_t i, last_offset = 0; uint32_t *ptr; @@ -264,10 +335,18 @@ return -EINVAL; } + if (obj->flags & MSM_BO_SECURE) { + DRM_ERROR("cannot do relocs on a secure buffer\n"); + return -EINVAL; + } + + if (nr_relocs == 0) + return 0; + /* For now, just map the entire thing. Eventually we probably * to do it page-by-page, w/ kmap() if not vmap()d.. */ - ptr = msm_gem_vaddr_locked(&obj->base); + ptr = msm_gem_vaddr(&obj->base); if (IS_ERR(ptr)) { ret = PTR_ERR(ptr); @@ -278,12 +357,13 @@ for (i = 0; i < nr_relocs; i++) { struct drm_msm_gem_submit_reloc submit_reloc; void __user *userptr = - to_user_ptr(relocs + (i * sizeof(submit_reloc))); - uint32_t iova, off; + u64_to_user_ptr(relocs + (i * sizeof(submit_reloc))); + uint64_t iova; + uint32_t off; bool valid; - ret = copy_from_user(&submit_reloc, userptr, sizeof(submit_reloc)); - if (ret) + if (copy_from_user(&submit_reloc, userptr, + sizeof(submit_reloc))) return -EFAULT; if (submit_reloc.submit_offset % 4) { @@ -301,7 +381,8 @@ return -EINVAL; } - ret = submit_bo(submit, submit_reloc.reloc_idx, NULL, &iova, &valid); + ret = submit_bo(gpu, submit, submit_reloc.reloc_idx, + NULL, &iova, &valid); if (ret) return ret; @@ -323,13 +404,17 @@ return 0; } -static void submit_cleanup(struct msm_gem_submit *submit, bool fail) +static void submit_cleanup(struct msm_gpu *gpu, struct msm_gem_submit *submit, + bool fail) { unsigned i; + if (!submit) + return; + for (i = 0; i < submit->nr_bos; i++) { struct msm_gem_object *msm_obj = submit->bos[i].obj; - submit_unlock_unpin_bo(submit, i); + submit_unlock_unpin_bo(gpu, submit, i); list_del_init(&msm_obj->submit_entry); drm_gem_object_unreference(&msm_obj->base); } @@ -344,6 +429,7 @@ struct drm_msm_gem_submit *args = data; struct msm_file_private *ctx = file->driver_priv; struct msm_gem_submit *submit; + struct msm_gpu_submitqueue *queue; struct msm_gpu *gpu; unsigned i; int ret; @@ -351,36 +437,41 @@ /* for now, we just have 3d pipe.. eventually this would need to * be more clever to dispatch to appropriate gpu module: */ - if (args->pipe != MSM_PIPE_3D0) + if (MSM_PIPE_ID(args->flags) != MSM_PIPE_3D0) return -EINVAL; gpu = priv->gpu; + if (!gpu || !ctx) + return -ENXIO; - if (args->nr_cmds > MAX_CMDS) - return -EINVAL; + queue = msm_submitqueue_get(ctx, args->queueid); + if (!queue) + return -ENOENT; mutex_lock(&dev->struct_mutex); - submit = submit_create(dev, gpu, args->nr_bos); + submit = submit_create(dev, ctx->aspace, args->nr_bos, args->nr_cmds, + queue); if (!submit) { ret = -ENOMEM; goto out; } - ret = submit_lookup_objects(submit, args, file); + ret = submit_lookup_objects(gpu, submit, args, file); if (ret) goto out; - ret = submit_validate_objects(submit); + ret = submit_validate_objects(gpu, submit); if (ret) goto out; for (i = 0; i < args->nr_cmds; i++) { struct drm_msm_gem_submit_cmd submit_cmd; void __user *userptr = - to_user_ptr(args->cmds + (i * sizeof(submit_cmd))); + u64_to_user_ptr(args->cmds + (i * sizeof(submit_cmd))); struct msm_gem_object *msm_obj; - uint32_t iova; + uint64_t iova; + size_t size; ret = copy_from_user(&submit_cmd, userptr, sizeof(submit_cmd)); if (ret) { @@ -393,6 +484,7 @@ case MSM_SUBMIT_CMD_BUF: case MSM_SUBMIT_CMD_IB_TARGET_BUF: case MSM_SUBMIT_CMD_CTX_RESTORE_BUF: + case MSM_SUBMIT_CMD_PROFILE_BUF: break; default: DRM_ERROR("invalid type: %08x\n", submit_cmd.type); @@ -400,7 +492,7 @@ goto out; } - ret = submit_bo(submit, submit_cmd.submit_idx, + ret = submit_bo(gpu, submit, submit_cmd.submit_idx, &msm_obj, &iova, NULL); if (ret) goto out; @@ -412,9 +504,12 @@ goto out; } - if ((submit_cmd.size + submit_cmd.submit_offset) >= - msm_obj->base.size) { - DRM_ERROR("invalid cmdstream size: %u\n", submit_cmd.size); + size = submit_cmd.size + submit_cmd.submit_offset; + + if (!submit_cmd.size || (size < submit_cmd.size) || + (size > msm_obj->base.size)) { + DRM_ERROR("invalid cmdstream offset/size: %u/%u\n", + submit_cmd.submit_offset, submit_cmd.size); ret = -EINVAL; goto out; } @@ -424,24 +519,32 @@ submit->cmd[i].iova = iova + submit_cmd.submit_offset; submit->cmd[i].idx = submit_cmd.submit_idx; - if (submit->valid) - continue; + if (submit_cmd.type == MSM_SUBMIT_CMD_PROFILE_BUF) { + submit->profile_buf_iova = submit->cmd[i].iova; + submit->profile_buf = msm_gem_vaddr(&msm_obj->base) + + submit_cmd.submit_offset; + } - ret = submit_reloc(submit, msm_obj, submit_cmd.submit_offset, - submit_cmd.nr_relocs, submit_cmd.relocs); + ret = submit_reloc(gpu, submit, msm_obj, + submit_cmd.submit_offset, submit_cmd.nr_relocs, + submit_cmd.relocs); if (ret) goto out; } submit->nr_cmds = i; - ret = msm_gpu_submit(gpu, submit, ctx); + /* Clamp the user submitted ring to the range of available rings */ + submit->ring = clamp_t(uint32_t, queue->prio, 0, gpu->nr_rings - 1); + + ret = msm_gpu_submit(gpu, submit); args->fence = submit->fence; out: - if (submit) - submit_cleanup(submit, !!ret); + submit_cleanup(gpu, submit, !!ret); + if (ret) + msm_gem_submit_free(submit); mutex_unlock(&dev->struct_mutex); return ret; } diff -ruw linux-4.4.115/drivers/gpu/drm/msm/msm_gpu.c linux-4.4.115-fbx/drivers/gpu/drm/msm/msm_gpu.c --- linux-4.4.115/drivers/gpu/drm/msm/msm_gpu.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/gpu/drm/msm/msm_gpu.c 2019-10-29 09:26:23.633203080 +0100 @@ -2,6 +2,8 @@ * Copyright (C) 2013 Red Hat * Author: Rob Clark * + * Copyright (c) 2018 The Linux Foundation. All rights reserved. + * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License version 2 as published by * the Free Software Foundation. @@ -15,15 +17,19 @@ * this program. If not, see . */ +#include +#include #include "msm_gpu.h" #include "msm_gem.h" #include "msm_mmu.h" - +#include "msm_trace.h" /* * Power Management: */ +#define ACTIVE_POWER_LEVEL(gpu) min_t(unsigned int, 2, gpu->nr_pwrlevels - 3) + #ifdef DOWNSTREAM_CONFIG_MSM_BUS_SCALING #include static void bs_init(struct msm_gpu *gpu) @@ -55,6 +61,138 @@ static void bs_set(struct msm_gpu *gpu, int idx) {} #endif +static int msm_devfreq_target(struct device *dev, unsigned long *freq, + u32 flags) +{ + struct msm_gpu *gpu = platform_get_drvdata(to_platform_device(dev)); + struct dev_pm_opp *opp; + + opp = devfreq_recommended_opp(dev, freq, flags); + + if (IS_ERR(opp)) + return PTR_ERR(opp); + + clk_set_rate(gpu->core_clk, *freq); + + return 0; +} + +static int msm_devfreq_get_dev_status(struct device *dev, + struct devfreq_dev_status *status) +{ + struct msm_gpu *gpu = platform_get_drvdata(to_platform_device(dev)); + uint64_t cycles; + ktime_t time; + u32 freq; + + status->current_frequency = (unsigned long) clk_get_rate(gpu->core_clk); + + cycles = gpu->funcs->gpu_busy(gpu); + freq = ((u32) status->current_frequency) / 1000000; + status->busy_time = ((u32) (cycles - gpu->devfreq.busy_cycles)) / freq; + gpu->devfreq.busy_cycles = cycles; + + time = ktime_get(); + status->total_time = ktime_us_delta(time, gpu->devfreq.time); + gpu->devfreq.time = time; + + return 0; +} + +static int msm_devfreq_get_cur_freq(struct device *dev, unsigned long *freq) +{ + struct msm_gpu *gpu = platform_get_drvdata(to_platform_device(dev)); + + *freq = clk_get_rate(gpu->core_clk); + return 0; +} + +static void msm_devfreq_manage_opp_notifier(struct device *dev, + struct notifier_block *nb, bool subscribe) +{ + struct srcu_notifier_head *nh; + + rcu_read_lock(); + nh = dev_pm_opp_get_notifier(dev); + if (IS_ERR(nh)) { + rcu_read_unlock(); + return; + } + rcu_read_unlock(); + + if (subscribe) + srcu_notifier_chain_register(nh, nb); + else + srcu_notifier_chain_unregister(nh, nb); +} + +static int msm_opp_notify(struct notifier_block *nb, unsigned long type, + void *in_opp) +{ + struct msm_gpu *gpu = container_of(nb, struct msm_gpu, nb); + + if (type != OPP_EVENT_ENABLE && type != OPP_EVENT_DISABLE) + return -EINVAL; + + /* + * The opp table for the GPU device changed, call update_devfreq() + * to adjust the GPU frequency if needed + */ + mutex_lock(&gpu->devfreq.devfreq->lock); + update_devfreq(gpu->devfreq.devfreq); + mutex_unlock(&gpu->devfreq.devfreq->lock); + + return 0; +} + +static struct devfreq_dev_profile msm_devfreq_profile = { + .polling_ms = 10, + .target = msm_devfreq_target, + .get_dev_status = msm_devfreq_get_dev_status, + .get_cur_freq = msm_devfreq_get_cur_freq, +}; + +static void msm_devfreq_init(struct msm_gpu *gpu) +{ + struct msm_drm_private *priv = gpu->dev->dev_private; + struct device *dev = &priv->gpu_pdev->dev; + unsigned int level = min_t(unsigned int, 2, gpu->nr_pwrlevels - 3); + + /* Don't do devfreq if the GPU doesn't implement statistics gathering */ + if (!gpu->funcs->gpu_busy) + return; + + msm_devfreq_profile.initial_freq = gpu->gpufreq[level]; + msm_devfreq_profile.freq_table = gpu->gpufreq; + msm_devfreq_profile.max_state = gpu->nr_pwrlevels - 1; + + gpu->devfreq.devfreq = devm_devfreq_add_device(dev, + &msm_devfreq_profile, "simple_ondemand", NULL); + + if (IS_ERR(gpu->devfreq.devfreq)) { + dev_err(dev, "Couldn't initialize GPU devfreq\n"); + gpu->devfreq.devfreq = NULL; + return; + } + + gpu->devfreq.cooling_dev = of_devfreq_cooling_register(dev->of_node, + gpu->devfreq.devfreq); + + if (IS_ERR(gpu->devfreq.cooling_dev)) { + dev_err(dev, "Couldn't register GPU devfreq cooling device\n"); + gpu->devfreq.cooling_dev = NULL; + return; + } + + gpu->nb.notifier_call = msm_opp_notify; + + /* + * register for OPP notifcations so we can adjust the + * GPU device power levels appropriately + */ + msm_devfreq_manage_opp_notifier(dev, &gpu->nb, true); +} + static int enable_pwrrail(struct msm_gpu *gpu) { struct drm_device *dev = gpu->dev; @@ -90,21 +228,21 @@ static int enable_clk(struct msm_gpu *gpu) { - struct clk *rate_clk = NULL; + unsigned int level = ACTIVE_POWER_LEVEL(gpu); + uint32_t rate = gpu->gpufreq[level]; int i; - /* NOTE: kgsl_pwrctrl_clk() ignores grp_clks[0].. */ - for (i = ARRAY_SIZE(gpu->grp_clks) - 1; i > 0; i--) { - if (gpu->grp_clks[i]) { - clk_prepare(gpu->grp_clks[i]); - rate_clk = gpu->grp_clks[i]; - } - } + if (gpu->core_clk) + clk_set_rate(gpu->core_clk, rate); + + if (gpu->rbbmtimer_clk) + clk_set_rate(gpu->rbbmtimer_clk, 19200000); - if (rate_clk && gpu->fast_rate) - clk_set_rate(rate_clk, gpu->fast_rate); + for (i = gpu->nr_clocks - 1; i >= 0; i--) + if (gpu->grp_clks[i]) + clk_prepare(gpu->grp_clks[i]); - for (i = ARRAY_SIZE(gpu->grp_clks) - 1; i > 0; i--) + for (i = gpu->nr_clocks - 1; i >= 0; i--) if (gpu->grp_clks[i]) clk_enable(gpu->grp_clks[i]); @@ -113,33 +251,34 @@ static int disable_clk(struct msm_gpu *gpu) { - struct clk *rate_clk = NULL; + uint32_t rate = gpu->gpufreq[gpu->nr_pwrlevels - 1]; int i; - /* NOTE: kgsl_pwrctrl_clk() ignores grp_clks[0].. */ - for (i = ARRAY_SIZE(gpu->grp_clks) - 1; i > 0; i--) { - if (gpu->grp_clks[i]) { + for (i = gpu->nr_clocks - 1; i >= 0; i--) + if (gpu->grp_clks[i]) clk_disable(gpu->grp_clks[i]); - rate_clk = gpu->grp_clks[i]; - } - } - if (rate_clk && gpu->slow_rate) - clk_set_rate(rate_clk, gpu->slow_rate); - - for (i = ARRAY_SIZE(gpu->grp_clks) - 1; i > 0; i--) + for (i = gpu->nr_clocks - 1; i >= 0; i--) if (gpu->grp_clks[i]) clk_unprepare(gpu->grp_clks[i]); + if (gpu->core_clk) + clk_set_rate(gpu->core_clk, rate); + + if (gpu->rbbmtimer_clk) + clk_set_rate(gpu->rbbmtimer_clk, 0); + return 0; } static int enable_axi(struct msm_gpu *gpu) { + unsigned int level = ACTIVE_POWER_LEVEL(gpu); if (gpu->ebi1_clk) clk_prepare_enable(gpu->ebi1_clk); - if (gpu->bus_freq) - bs_set(gpu, gpu->bus_freq); + + if (gpu->busfreq[level]) + bs_set(gpu, gpu->busfreq[level]); return 0; } @@ -147,25 +286,27 @@ { if (gpu->ebi1_clk) clk_disable_unprepare(gpu->ebi1_clk); - if (gpu->bus_freq) + + if (gpu->busfreq[gpu->nr_pwrlevels - 1]) bs_set(gpu, 0); return 0; } -int msm_gpu_pm_resume(struct msm_gpu *gpu) +static void msm_devfreq_resume(struct msm_gpu *gpu) { - struct drm_device *dev = gpu->dev; - int ret; + if (gpu->devfreq.devfreq) { + gpu->devfreq.busy_cycles = 0; + gpu->devfreq.time = ktime_get(); - DBG("%s: active_cnt=%d", gpu->name, gpu->active_cnt); - - WARN_ON(!mutex_is_locked(&dev->struct_mutex)); + devfreq_resume_device(gpu->devfreq.devfreq); + } +} - if (gpu->active_cnt++ > 0) - return 0; +int msm_gpu_pm_resume(struct msm_gpu *gpu) +{ + int ret; - if (WARN_ON(gpu->active_cnt <= 0)) - return -EINVAL; + DBG("%s", gpu->name); ret = enable_pwrrail(gpu); if (ret) @@ -179,23 +320,26 @@ if (ret) return ret; + if (gpu->aspace && gpu->aspace->mmu) + msm_mmu_enable(gpu->aspace->mmu); + + gpu->needs_hw_init = true; + msm_devfreq_resume(gpu); + return 0; } int msm_gpu_pm_suspend(struct msm_gpu *gpu) { - struct drm_device *dev = gpu->dev; int ret; - DBG("%s: active_cnt=%d", gpu->name, gpu->active_cnt); + DBG("%s", gpu->name); - WARN_ON(!mutex_is_locked(&dev->struct_mutex)); + if (gpu->devfreq.devfreq) + devfreq_suspend_device(gpu->devfreq.devfreq); - if (--gpu->active_cnt > 0) - return 0; - - if (WARN_ON(gpu->active_cnt < 0)) - return -EINVAL; + if (gpu->aspace && gpu->aspace->mmu) + msm_mmu_disable(gpu->aspace->mmu); ret = disable_axi(gpu); if (ret) @@ -212,82 +356,71 @@ return 0; } -/* - * Inactivity detection (for suspend): - */ - -static void inactive_worker(struct work_struct *work) +int msm_gpu_hw_init(struct msm_gpu *gpu) { - struct msm_gpu *gpu = container_of(work, struct msm_gpu, inactive_work); - struct drm_device *dev = gpu->dev; + int ret; - if (gpu->inactive) - return; + if (!gpu->needs_hw_init) + return 0; - DBG("%s: inactive!\n", gpu->name); - mutex_lock(&dev->struct_mutex); - if (!(msm_gpu_active(gpu) || gpu->inactive)) { - disable_axi(gpu); - disable_clk(gpu); - gpu->inactive = true; - } - mutex_unlock(&dev->struct_mutex); + disable_irq(gpu->irq); + ret = gpu->funcs->hw_init(gpu); + if (!ret) + gpu->needs_hw_init = false; + enable_irq(gpu->irq); + + return ret; } -static void inactive_handler(unsigned long data) +static void retire_guilty_submit(struct msm_gpu *gpu, + struct msm_ringbuffer *ring) { - struct msm_gpu *gpu = (struct msm_gpu *)data; - struct msm_drm_private *priv = gpu->dev->dev_private; + struct msm_gem_submit *submit = list_first_entry_or_null(&ring->submits, + struct msm_gem_submit, node); - queue_work(priv->wq, &gpu->inactive_work); -} + if (!submit) + return; -/* cancel inactive timer and make sure we are awake: */ -static void inactive_cancel(struct msm_gpu *gpu) -{ - DBG("%s", gpu->name); - del_timer(&gpu->inactive_timer); - if (gpu->inactive) { - enable_clk(gpu); - enable_axi(gpu); - gpu->inactive = false; - } -} + submit->queue->faults++; -static void inactive_start(struct msm_gpu *gpu) -{ - DBG("%s", gpu->name); - mod_timer(&gpu->inactive_timer, - round_jiffies_up(jiffies + DRM_MSM_INACTIVE_JIFFIES)); + msm_gem_submit_free(submit); } /* * Hangcheck detection for locked gpu: */ -static void retire_submits(struct msm_gpu *gpu, uint32_t fence); +static void retire_submits(struct msm_gpu *gpu, struct msm_ringbuffer *ring, + uint32_t fence); static void recover_worker(struct work_struct *work) { struct msm_gpu *gpu = container_of(work, struct msm_gpu, recover_work); struct drm_device *dev = gpu->dev; - dev_err(dev->dev, "%s: hangcheck recover!\n", gpu->name); - mutex_lock(&dev->struct_mutex); if (msm_gpu_active(gpu)) { struct msm_gem_submit *submit; - uint32_t fence = gpu->funcs->last_fence(gpu); + struct msm_ringbuffer *ring; + int i; - /* retire completed submits, plus the one that hung: */ - retire_submits(gpu, fence + 1); + /* Retire all events that have already passed */ + FOR_EACH_RING(gpu, ring, i) + retire_submits(gpu, ring, ring->memptrs->fence); - inactive_cancel(gpu); + retire_guilty_submit(gpu, gpu->funcs->active_ring(gpu)); + + /* Recover the GPU */ gpu->funcs->recover(gpu); + /* Decrement the device usage count for the guilty submit */ + pm_runtime_put_sync_autosuspend(&gpu->pdev->dev); + + /* Replay the remaining on all rings, highest priority first */ + for (i = 0; i < gpu->nr_rings; i++) { + struct msm_ringbuffer *ring = gpu->rb[i]; - /* replay the remaining submits after the one that hung: */ - list_for_each_entry(submit, &gpu->submit_list, node) { - gpu->funcs->submit(gpu, submit, NULL); + list_for_each_entry(submit, &ring->submits, node) + gpu->funcs->submit(gpu, submit); } } mutex_unlock(&dev->struct_mutex); @@ -307,25 +440,43 @@ struct msm_gpu *gpu = (struct msm_gpu *)data; struct drm_device *dev = gpu->dev; struct msm_drm_private *priv = dev->dev_private; - uint32_t fence = gpu->funcs->last_fence(gpu); + struct msm_ringbuffer *ring = gpu->funcs->active_ring(gpu); + uint32_t fence = ring->memptrs->fence; + uint32_t submitted = gpu->funcs->submitted_fence(gpu, ring); - if (fence != gpu->hangcheck_fence) { + if (fence != ring->hangcheck_fence) { /* some progress has been made.. ya! */ - gpu->hangcheck_fence = fence; - } else if (fence < gpu->submitted_fence) { - /* no progress and not done.. hung! */ - gpu->hangcheck_fence = fence; - dev_err(dev->dev, "%s: hangcheck detected gpu lockup!\n", - gpu->name); + ring->hangcheck_fence = fence; + } else if (fence < submitted) { + struct msm_gem_submit *submit; + + ring->hangcheck_fence = fence; + + /* + * No progress done, but see if the current submit is + * intentionally skipping the hangcheck + */ + submit = list_first_entry_or_null(&ring->submits, + struct msm_gem_submit, node); + + if (!submit || (submit->queue->flags & + MSM_SUBMITQUEUE_BYPASS_QOS_TIMEOUT)) + goto out; + + /* no progress and not done and not special .. hung! */ + dev_err(dev->dev, "%s: hangcheck detected gpu lockup rb %d!\n", + gpu->name, ring->id); dev_err(dev->dev, "%s: completed fence: %u\n", gpu->name, fence); dev_err(dev->dev, "%s: submitted fence: %u\n", - gpu->name, gpu->submitted_fence); + gpu->name, submitted); + queue_work(priv->wq, &gpu->recover_work); } +out: /* if still more pending work, reset the hangcheck timer: */ - if (gpu->submitted_fence > gpu->hangcheck_fence) + if (submitted > ring->hangcheck_fence) hangcheck_timer_reset(gpu); /* workaround for missing irq: */ @@ -385,6 +536,8 @@ { unsigned long flags; + pm_runtime_get_sync(&gpu->pdev->dev); + spin_lock_irqsave(&gpu->perf_lock, flags); /* we could dynamically enable/disable perfcntr registers too.. */ gpu->last_sample.active = msm_gpu_active(gpu); @@ -398,6 +551,7 @@ void msm_gpu_perfcntr_stop(struct msm_gpu *gpu) { gpu->perfcntr_active = false; + pm_runtime_put_sync(&gpu->pdev->dev); } /* returns -errno or # of cntrs sampled */ @@ -431,60 +585,74 @@ * Cmdstream submission/retirement: */ -static void retire_submits(struct msm_gpu *gpu, uint32_t fence) +static void retire_submits(struct msm_gpu *gpu, struct msm_ringbuffer *ring, + uint32_t fence) { struct drm_device *dev = gpu->dev; + struct msm_gem_submit *submit, *tmp; WARN_ON(!mutex_is_locked(&dev->struct_mutex)); - while (!list_empty(&gpu->submit_list)) { - struct msm_gem_submit *submit; - - submit = list_first_entry(&gpu->submit_list, - struct msm_gem_submit, node); + list_for_each_entry_safe(submit, tmp, &ring->submits, node) { + struct msm_memptr_ticks *ticks; - if (submit->fence <= fence) { - list_del(&submit->node); - kfree(submit); - } else { + if (submit->fence > fence) break; - } + + ticks = &(ring->memptrs->ticks[submit->tick_index]); + + /* Add memory barrier to ensure the timer ticks are posted */ + rmb(); + + trace_msm_retired(submit, ticks->started, ticks->retired); + + pm_runtime_mark_last_busy(&gpu->pdev->dev); + pm_runtime_put_autosuspend(&gpu->pdev->dev); + msm_gem_submit_free(submit); } } -static void retire_worker(struct work_struct *work) +static bool _fence_signaled(struct msm_gem_object *obj, uint32_t fence) { - struct msm_gpu *gpu = container_of(work, struct msm_gpu, retire_work); - struct drm_device *dev = gpu->dev; - uint32_t fence = gpu->funcs->last_fence(gpu); - - msm_update_fence(gpu->dev, fence); + if (obj->write_fence & 0x3FFFFFFF) + return COMPARE_FENCE_LTE(obj->write_fence, fence); - mutex_lock(&dev->struct_mutex); - - retire_submits(gpu, fence); + return COMPARE_FENCE_LTE(obj->read_fence, fence); +} - while (!list_empty(&gpu->active_list)) { - struct msm_gem_object *obj; +static void _retire_ring(struct msm_gpu *gpu, struct msm_ringbuffer *ring, + uint32_t fence) +{ + struct msm_gem_object *obj, *tmp; - obj = list_first_entry(&gpu->active_list, - struct msm_gem_object, mm_list); + retire_submits(gpu, ring, fence); - if ((obj->read_fence <= fence) && - (obj->write_fence <= fence)) { - /* move to inactive: */ + list_for_each_entry_safe(obj, tmp, &gpu->active_list, mm_list) { + if (_fence_signaled(obj, fence)) { msm_gem_move_to_inactive(&obj->base); - msm_gem_put_iova(&obj->base, gpu->id); + msm_gem_put_iova(&obj->base, gpu->aspace); drm_gem_object_unreference(&obj->base); - } else { - break; + } } } - mutex_unlock(&dev->struct_mutex); +static void retire_worker(struct work_struct *work) +{ + struct msm_gpu *gpu = container_of(work, struct msm_gpu, retire_work); + struct drm_device *dev = gpu->dev; + struct msm_ringbuffer *ring; + int i; + + FOR_EACH_RING(gpu, ring, i) { + if (!ring) + continue; - if (!msm_gpu_active(gpu)) - inactive_start(gpu); + msm_update_fence(gpu->dev, ring->memptrs->fence); + + mutex_lock(&dev->struct_mutex); + _retire_ring(gpu, ring, ring->memptrs->fence); + mutex_unlock(&dev->struct_mutex); + } } /* call from irq handler to schedule work to retire bo's */ @@ -496,26 +664,29 @@ } /* add bo's to gpu's ring, and kick gpu: */ -int msm_gpu_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit, - struct msm_file_private *ctx) +int msm_gpu_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit) { struct drm_device *dev = gpu->dev; - struct msm_drm_private *priv = dev->dev_private; - int i, ret; + struct msm_ringbuffer *ring = gpu->rb[submit->ring]; + int i; WARN_ON(!mutex_is_locked(&dev->struct_mutex)); - submit->fence = ++priv->next_fence; + submit->fence = FENCE(submit->ring, ++ring->seqno); - gpu->submitted_fence = submit->fence; + pm_runtime_get_sync(&gpu->pdev->dev); - inactive_cancel(gpu); + msm_gpu_hw_init(gpu); - list_add_tail(&submit->node, &gpu->submit_list); + list_add_tail(&submit->node, &ring->submits); - msm_rd_dump_submit(submit); + ring->submitted_fence = submit->fence; + + submit->tick_index = ring->tick_index; + ring->tick_index = (ring->tick_index + 1) % + ARRAY_SIZE(ring->memptrs->ticks); - gpu->submitted_fence = submit->fence; + trace_msm_queued(submit); update_sw_cntrs(gpu); @@ -528,27 +699,147 @@ WARN_ON(is_active(msm_obj) && (msm_obj->gpu != gpu)); if (!is_active(msm_obj)) { - uint32_t iova; + struct msm_gem_address_space *aspace; + uint64_t iova; + + aspace = (msm_obj->flags & MSM_BO_SECURE) ? + gpu->secure_aspace : submit->aspace; /* ring takes a reference to the bo and iova: */ drm_gem_object_reference(&msm_obj->base); - msm_gem_get_iova_locked(&msm_obj->base, - submit->gpu->id, &iova); + msm_gem_get_iova(&msm_obj->base, aspace, &iova); + + submit->bos[i].iova = iova; } if (submit->bos[i].flags & MSM_SUBMIT_BO_READ) msm_gem_move_to_active(&msm_obj->base, gpu, false, submit->fence); - - if (submit->bos[i].flags & MSM_SUBMIT_BO_WRITE) + else if (submit->bos[i].flags & MSM_SUBMIT_BO_WRITE) msm_gem_move_to_active(&msm_obj->base, gpu, true, submit->fence); } - ret = gpu->funcs->submit(gpu, submit, ctx); - priv->lastctx = ctx; + msm_rd_dump_submit(submit); + + gpu->funcs->submit(gpu, submit); hangcheck_timer_reset(gpu); - return ret; + return 0; +} + +struct msm_context_counter { + u32 groupid; + int counterid; + struct list_head node; +}; + +int msm_gpu_counter_get(struct msm_gpu *gpu, struct drm_msm_counter *data, + struct msm_file_private *ctx) +{ + struct msm_context_counter *entry; + int counterid; + u32 lo = 0, hi = 0; + + if (!ctx || !gpu->funcs->get_counter) + return -ENODEV; + + counterid = gpu->funcs->get_counter(gpu, data->groupid, data->countable, + &lo, &hi); + + if (counterid < 0) + return counterid; + + /* + * Check to see if the counter in question is already held by this + * process. If it does, put it back and return an error. + */ + list_for_each_entry(entry, &ctx->counters, node) { + if (entry->groupid == data->groupid && + entry->counterid == counterid) { + gpu->funcs->put_counter(gpu, data->groupid, counterid); + return -EBUSY; + } + } + + entry = kmalloc(sizeof(*entry), GFP_KERNEL); + if (!entry) { + gpu->funcs->put_counter(gpu, data->groupid, counterid); + return -ENOMEM; + } + + entry->groupid = data->groupid; + entry->counterid = counterid; + list_add_tail(&entry->node, &ctx->counters); + + data->counterid = counterid; + data->counter_lo = lo; + data->counter_hi = hi; + + return 0; +} + +int msm_gpu_counter_put(struct msm_gpu *gpu, struct drm_msm_counter *data, + struct msm_file_private *ctx) +{ + struct msm_context_counter *entry; + + if (!gpu || !ctx) + return -ENODEV; + + list_for_each_entry(entry, &ctx->counters, node) { + if (entry->groupid == data->groupid && + entry->counterid == data->counterid) { + gpu->funcs->put_counter(gpu, data->groupid, + data->counterid); + + list_del(&entry->node); + kfree(entry); + + return 0; + } + } + + return -EINVAL; +} + +void msm_gpu_cleanup_counters(struct msm_gpu *gpu, + struct msm_file_private *ctx) +{ + struct msm_context_counter *entry, *tmp; + + if (!ctx) + return; + + list_for_each_entry_safe(entry, tmp, &ctx->counters, node) { + gpu->funcs->put_counter(gpu, entry->groupid, entry->counterid); + list_del(&entry->node); + kfree(entry); + } +} + +u64 msm_gpu_counter_read(struct msm_gpu *gpu, struct drm_msm_counter_read *data) +{ + int i; + + if (!gpu->funcs->read_counter) + return 0; + + for (i = 0; i < data->nr_ops; i++) { + struct drm_msm_counter_read_op op; + void __user *ptr = (void __user *)(uintptr_t) + (data->ops + (i * sizeof(op))); + + if (copy_from_user(&op, ptr, sizeof(op))) + return -EFAULT; + + op.value = gpu->funcs->read_counter(gpu, op.groupid, + op.counterid); + + if (copy_to_user(ptr, &op, sizeof(op))) + return -EFAULT; + } + + return 0; } /* @@ -561,17 +852,114 @@ return gpu->funcs->irq(gpu); } -static const char *clk_names[] = { - "src_clk", "core_clk", "iface_clk", "mem_clk", "mem_iface_clk", - "alt_mem_iface_clk", -}; +static struct clk *get_clock(struct device *dev, const char *name) +{ + struct clk *clk = devm_clk_get(dev, name); + + DBG("clks[%s]: %p", name, clk); + + return IS_ERR(clk) ? NULL : clk; +} + +static int get_clocks(struct platform_device *pdev, struct msm_gpu *gpu) +{ + struct device *dev = &pdev->dev; + struct property *prop; + const char *name; + int i = 0; + + gpu->nr_clocks = of_property_count_strings(dev->of_node, "clock-names"); + if (gpu->nr_clocks < 1) { + gpu->nr_clocks = 0; + return 0; + } + + gpu->grp_clks = devm_kcalloc(dev, sizeof(struct clk *), gpu->nr_clocks, + GFP_KERNEL); + if (!gpu->grp_clks) + return -ENOMEM; + + of_property_for_each_string(dev->of_node, "clock-names", prop, name) { + gpu->grp_clks[i] = get_clock(dev, name); + + /* Remember the key clocks that we need to control later */ + if (!strcmp(name, "core_clk")) + gpu->core_clk = gpu->grp_clks[i]; + else if (!strcmp(name, "rbbmtimer_clk")) + gpu->rbbmtimer_clk = gpu->grp_clks[i]; + + ++i; + } + + return 0; +} + +static struct msm_gem_address_space * +msm_gpu_create_address_space(struct msm_gpu *gpu, struct device *dev, + int type, u64 start, u64 end, const char *name) +{ + struct msm_gem_address_space *aspace; + struct iommu_domain *iommu; + + /* + * If start == end then assume we don't want an address space; this is + * mainly for targets to opt out of secure + */ + if (start == end) + return NULL; + + iommu = iommu_domain_alloc(&platform_bus_type); + if (!iommu) { + dev_info(gpu->dev->dev, + "%s: no IOMMU, fallback to VRAM carveout!\n", + gpu->name); + return NULL; + } + + iommu->geometry.aperture_start = start; + iommu->geometry.aperture_end = end; + + dev_info(gpu->dev->dev, "%s: using IOMMU '%s'\n", gpu->name, name); + + aspace = msm_gem_address_space_create(dev, iommu, type, name); + if (IS_ERR(aspace)) { + dev_err(gpu->dev->dev, "%s: failed to init IOMMU '%s': %ld\n", + gpu->name, name, PTR_ERR(aspace)); + + iommu_domain_free(iommu); + return NULL; + } + + if (aspace->mmu) { + int ret = aspace->mmu->funcs->attach(aspace->mmu, NULL, 0); + + if (ret) { + dev_err(gpu->dev->dev, + "%s: failed to atach IOMMU '%s': %d\n", + gpu->name, name, ret); + msm_gem_address_space_put(aspace); + aspace = ERR_PTR(ret); + } + } + + return aspace; +} + +static void msm_gpu_destroy_address_space(struct msm_gem_address_space *aspace) +{ + if (!IS_ERR_OR_NULL(aspace) && aspace->mmu) + aspace->mmu->funcs->detach(aspace->mmu); + + msm_gem_address_space_put(aspace); +} int msm_gpu_init(struct drm_device *drm, struct platform_device *pdev, struct msm_gpu *gpu, const struct msm_gpu_funcs *funcs, - const char *name, const char *ioname, const char *irqname, int ringsz) + const char *name, struct msm_gpu_config *config) { - struct iommu_domain *iommu; - int i, ret; + int i, ret, nr_rings; + void *memptrs; + uint64_t memptrs_iova; if (WARN_ON(gpu->num_perfcntrs > ARRAY_SIZE(gpu->last_cntrs))) gpu->num_perfcntrs = ARRAY_SIZE(gpu->last_cntrs); @@ -579,33 +967,27 @@ gpu->dev = drm; gpu->funcs = funcs; gpu->name = name; - gpu->inactive = true; INIT_LIST_HEAD(&gpu->active_list); INIT_WORK(&gpu->retire_work, retire_worker); - INIT_WORK(&gpu->inactive_work, inactive_worker); INIT_WORK(&gpu->recover_work, recover_worker); - INIT_LIST_HEAD(&gpu->submit_list); - setup_timer(&gpu->inactive_timer, inactive_handler, - (unsigned long)gpu); setup_timer(&gpu->hangcheck_timer, hangcheck_handler, (unsigned long)gpu); spin_lock_init(&gpu->perf_lock); - BUG_ON(ARRAY_SIZE(clk_names) != ARRAY_SIZE(gpu->grp_clks)); /* Map registers: */ - gpu->mmio = msm_ioremap(pdev, ioname, name); + gpu->mmio = msm_ioremap(pdev, config->ioname, name); if (IS_ERR(gpu->mmio)) { ret = PTR_ERR(gpu->mmio); goto fail; } /* Get Interrupt: */ - gpu->irq = platform_get_irq_byname(pdev, irqname); + gpu->irq = platform_get_irq_byname(pdev, config->irqname); if (gpu->irq < 0) { ret = gpu->irq; dev_err(drm->dev, "failed to get irq: %d\n", ret); @@ -615,17 +997,14 @@ ret = devm_request_irq(&pdev->dev, gpu->irq, irq_handler, IRQF_TRIGGER_HIGH, gpu->name, gpu); if (ret) { + gpu->irq = ret; dev_err(drm->dev, "failed to request IRQ%u: %d\n", gpu->irq, ret); goto fail; } - /* Acquire clocks: */ - for (i = 0; i < ARRAY_SIZE(clk_names); i++) { - gpu->grp_clks[i] = devm_clk_get(&pdev->dev, clk_names[i]); - DBG("grp_clks[%s]: %p", clk_names[i], gpu->grp_clks[i]); - if (IS_ERR(gpu->grp_clks[i])) - gpu->grp_clks[i] = NULL; - } + ret = get_clocks(pdev, gpu); + if (ret) + goto fail; gpu->ebi1_clk = devm_clk_get(&pdev->dev, "bus_clk"); DBG("ebi1_clk: %p", gpu->ebi1_clk); @@ -643,61 +1022,136 @@ if (IS_ERR(gpu->gpu_cx)) gpu->gpu_cx = NULL; - /* Setup IOMMU.. eventually we will (I think) do this once per context - * and have separate page tables per context. For now, to keep things - * simple and to get something working, just use a single address space: - */ - iommu = iommu_domain_alloc(&platform_bus_type); - if (iommu) { - dev_info(drm->dev, "%s: using IOMMU\n", name); - gpu->mmu = msm_iommu_new(&pdev->dev, iommu); - if (IS_ERR(gpu->mmu)) { - ret = PTR_ERR(gpu->mmu); - dev_err(drm->dev, "failed to init iommu: %d\n", ret); - gpu->mmu = NULL; - iommu_domain_free(iommu); - goto fail; - } + platform_set_drvdata(pdev, gpu); + + msm_devfreq_init(gpu); + + gpu->aspace = msm_gpu_create_address_space(gpu, &pdev->dev, + MSM_IOMMU_DOMAIN_USER, config->va_start, config->va_end, + "gpu"); + + gpu->secure_aspace = msm_gpu_create_address_space(gpu, &pdev->dev, + MSM_IOMMU_DOMAIN_SECURE, config->secure_va_start, + config->secure_va_end, "gpu_secure"); - } else { - dev_info(drm->dev, "%s: no IOMMU, fallback to VRAM carveout!\n", name); + nr_rings = config->nr_rings; + + if (nr_rings > ARRAY_SIZE(gpu->rb)) { + WARN(1, "Only creating %lu ringbuffers\n", ARRAY_SIZE(gpu->rb)); + nr_rings = ARRAY_SIZE(gpu->rb); } - gpu->id = msm_register_mmu(drm, gpu->mmu); + /* Allocate one buffer to hold all the memptr records for the rings */ + memptrs = msm_gem_kernel_new(drm, sizeof(struct msm_memptrs) * nr_rings, + MSM_BO_UNCACHED, gpu->aspace, &gpu->memptrs_bo, &memptrs_iova); - /* Create ringbuffer: */ - mutex_lock(&drm->struct_mutex); - gpu->rb = msm_ringbuffer_new(gpu, ringsz); - mutex_unlock(&drm->struct_mutex); - if (IS_ERR(gpu->rb)) { - ret = PTR_ERR(gpu->rb); - gpu->rb = NULL; - dev_err(drm->dev, "could not create ringbuffer: %d\n", ret); + if (IS_ERR(memptrs)) { + ret = PTR_ERR(memptrs); goto fail; } + /* Create ringbuffer(s): */ + for (i = 0; i < nr_rings; i++) { + gpu->rb[i] = msm_ringbuffer_new(gpu, i, memptrs, memptrs_iova); + if (IS_ERR(gpu->rb[i])) { + ret = PTR_ERR(gpu->rb[i]); + gpu->rb[i] = NULL; + dev_err(drm->dev, + "could not create ringbuffer %d: %d\n", i, ret); + goto fail; + } + + memptrs += sizeof(struct msm_memptrs); + memptrs_iova += sizeof(struct msm_memptrs); + } + + gpu->nr_rings = nr_rings; + +#ifdef CONFIG_SMP + gpu->pm_qos_req_dma.type = PM_QOS_REQ_AFFINE_IRQ; + gpu->pm_qos_req_dma.irq = gpu->irq; +#endif + + pm_qos_add_request(&gpu->pm_qos_req_dma, PM_QOS_CPU_DMA_LATENCY, + PM_QOS_DEFAULT_VALUE); + gpu->pdev = pdev; + platform_set_drvdata(pdev, gpu); + bs_init(gpu); + gpu->snapshot = msm_snapshot_new(gpu); + if (IS_ERR(gpu->snapshot)) + gpu->snapshot = NULL; + return 0; fail: + for (i = 0; i < ARRAY_SIZE(gpu->rb); i++) + msm_ringbuffer_destroy(gpu->rb[i]); + + if (gpu->memptrs_bo) { + msm_gem_put_iova(gpu->memptrs_bo, gpu->aspace); + drm_gem_object_unreference_unlocked(gpu->memptrs_bo); + } + + msm_gpu_destroy_address_space(gpu->aspace); + msm_gpu_destroy_address_space(gpu->secure_aspace); + return ret; } void msm_gpu_cleanup(struct msm_gpu *gpu) { + struct drm_device *dev = gpu->dev; + struct msm_drm_private *priv = dev->dev_private; + struct platform_device *pdev = priv->gpu_pdev; + int i; + DBG("%s", gpu->name); WARN_ON(!list_empty(&gpu->active_list)); + if (gpu->devfreq.devfreq) { + msm_devfreq_manage_opp_notifier(&pdev->dev, &gpu->nb, false); + devfreq_cooling_unregister(gpu->devfreq.cooling_dev); + devfreq_remove_device(gpu->devfreq.devfreq); + } + + if (gpu->irq >= 0) { + disable_irq(gpu->irq); + devm_free_irq(&pdev->dev, gpu->irq, gpu); + } + bs_fini(gpu); - if (gpu->rb) { - if (gpu->rb_iova) - msm_gem_put_iova(gpu->rb->bo, gpu->id); - msm_ringbuffer_destroy(gpu->rb); + for (i = 0; i < ARRAY_SIZE(gpu->rb); i++) + msm_ringbuffer_destroy(gpu->rb[i]); + + if (gpu->memptrs_bo) { + msm_gem_put_iova(gpu->memptrs_bo, gpu->aspace); + drm_gem_object_unreference_unlocked(gpu->memptrs_bo); } - if (gpu->mmu) - gpu->mmu->funcs->destroy(gpu->mmu); + msm_snapshot_destroy(gpu, gpu->snapshot); + + msm_gpu_destroy_address_space(gpu->aspace); + msm_gpu_destroy_address_space(gpu->secure_aspace); + + if (gpu->gpu_reg) + devm_regulator_put(gpu->gpu_reg); + + if (gpu->gpu_cx) + devm_regulator_put(gpu->gpu_cx); + + if (gpu->ebi1_clk) + devm_clk_put(&pdev->dev, gpu->ebi1_clk); + + for (i = gpu->nr_clocks - 1; i >= 0; i--) + if (gpu->grp_clks[i]) + devm_clk_put(&pdev->dev, gpu->grp_clks[i]); + + devm_kfree(&pdev->dev, gpu->grp_clks); + + if (gpu->mmio) + devm_iounmap(&pdev->dev, gpu->mmio); } diff -ruw linux-4.4.115/drivers/gpu/drm/msm/msm_gpu.h linux-4.4.115-fbx/drivers/gpu/drm/msm/msm_gpu.h --- linux-4.4.115/drivers/gpu/drm/msm/msm_gpu.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/gpu/drm/msm/msm_gpu.h 2019-01-22 16:16:23.507246443 +0100 @@ -2,6 +2,8 @@ * Copyright (C) 2013 Red Hat * Author: Rob Clark * + * Copyright (c) 2018 The Linux Foundation. All rights reserved. + * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License version 2 as published by * the Free Software Foundation. @@ -19,14 +21,30 @@ #define __MSM_GPU_H__ #include +#include #include +#include #include "msm_drv.h" #include "msm_ringbuffer.h" +#include "msm_snapshot.h" struct msm_gem_submit; struct msm_gpu_perfcntr; +#define MSM_GPU_DEFAULT_IONAME "kgsl_3d0_reg_memory" +#define MSM_GPU_DEFAULT_IRQNAME "kgsl_3d0_irq" + +struct msm_gpu_config { + const char *ioname; + const char *irqname; + int nr_rings; + uint64_t va_start; + uint64_t va_end; + uint64_t secure_va_start; + uint64_t secure_va_end; +}; + /* So far, with hardware that I've seen to date, we can have: * + zero, one, or two z180 2d cores * + a3xx or a2xx 3d core, which share a common CP (the firmware @@ -46,23 +64,30 @@ int (*hw_init)(struct msm_gpu *gpu); int (*pm_suspend)(struct msm_gpu *gpu); int (*pm_resume)(struct msm_gpu *gpu); - int (*submit)(struct msm_gpu *gpu, struct msm_gem_submit *submit, - struct msm_file_private *ctx); - void (*flush)(struct msm_gpu *gpu); - void (*idle)(struct msm_gpu *gpu); + void (*submit)(struct msm_gpu *gpu, struct msm_gem_submit *submit); + void (*flush)(struct msm_gpu *gpu, struct msm_ringbuffer *ring); irqreturn_t (*irq)(struct msm_gpu *irq); - uint32_t (*last_fence)(struct msm_gpu *gpu); + uint32_t (*submitted_fence)(struct msm_gpu *gpu, + struct msm_ringbuffer *ring); + struct msm_ringbuffer *(*active_ring)(struct msm_gpu *gpu); void (*recover)(struct msm_gpu *gpu); void (*destroy)(struct msm_gpu *gpu); #ifdef CONFIG_DEBUG_FS /* show GPU status in debugfs: */ void (*show)(struct msm_gpu *gpu, struct seq_file *m); #endif + int (*snapshot)(struct msm_gpu *gpu, struct msm_snapshot *snapshot); + int (*get_counter)(struct msm_gpu *gpu, u32 groupid, u32 countable, + u32 *lo, u32 *hi); + void (*put_counter)(struct msm_gpu *gpu, u32 groupid, int counterid); + u64 (*read_counter)(struct msm_gpu *gpu, u32 groupid, int counterid); + u64 (*gpu_busy)(struct msm_gpu *gpu); }; struct msm_gpu { const char *name; struct drm_device *dev; + struct platform_device *pdev; const struct msm_gpu_funcs *funcs; /* performance counters (hw & sw): */ @@ -77,17 +102,14 @@ const struct msm_gpu_perfcntr *perfcntrs; uint32_t num_perfcntrs; - struct msm_ringbuffer *rb; - uint32_t rb_iova; + struct msm_ringbuffer *rb[MSM_GPU_MAX_RINGS]; + int nr_rings; /* list of GEM active objects: */ struct list_head active_list; - uint32_t submitted_fence; - - /* is gpu powered/active? */ - int active_cnt; - bool inactive; + /* does gpu need hw_init? */ + bool needs_hw_init; /* worker for handling active-list retiring: */ struct work_struct retire_work; @@ -95,13 +117,22 @@ void __iomem *mmio; int irq; - struct msm_mmu *mmu; - int id; + struct msm_gem_address_space *aspace; + struct msm_gem_address_space *secure_aspace; /* Power Control: */ struct regulator *gpu_reg, *gpu_cx; - struct clk *ebi1_clk, *grp_clks[6]; - uint32_t fast_rate, slow_rate, bus_freq; + struct clk **grp_clks; + struct clk *ebi1_clk, *core_clk, *rbbmtimer_clk; + int nr_clocks; + + uint32_t gpufreq[10]; + uint32_t busfreq[10]; + uint32_t nr_pwrlevels; + + struct pm_qos_request pm_qos_req_dma; + + struct drm_gem_object *memptrs_bo; #ifdef DOWNSTREAM_CONFIG_MSM_BUS_SCALING struct msm_bus_scale_pdata *bus_scale_table; @@ -111,21 +142,62 @@ /* Hang and Inactivity Detection: */ #define DRM_MSM_INACTIVE_PERIOD 66 /* in ms (roughly four frames) */ -#define DRM_MSM_INACTIVE_JIFFIES msecs_to_jiffies(DRM_MSM_INACTIVE_PERIOD) - struct timer_list inactive_timer; - struct work_struct inactive_work; + #define DRM_MSM_HANGCHECK_PERIOD 500 /* in ms */ #define DRM_MSM_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_MSM_HANGCHECK_PERIOD) struct timer_list hangcheck_timer; - uint32_t hangcheck_fence; struct work_struct recover_work; + struct msm_snapshot *snapshot; + + struct { + struct devfreq *devfreq; + u64 busy_cycles; + ktime_t time; + struct thermal_cooling_device *cooling_dev; + } devfreq; - struct list_head submit_list; + struct notifier_block nb; }; +struct msm_gpu_submitqueue { + int id; + u32 flags; + u32 prio; + int faults; + struct list_head node; + struct kref ref; +}; + +/* It turns out that all targets use the same ringbuffer size. */ +#define MSM_GPU_RINGBUFFER_SZ SZ_32K +#define MSM_GPU_RINGBUFFER_BLKSIZE 32 + +#define MSM_GPU_RB_CNTL_DEFAULT \ + (AXXX_CP_RB_CNTL_BUFSZ(ilog2(MSM_GPU_RINGBUFFER_SZ / 8)) | \ + AXXX_CP_RB_CNTL_BLKSZ(ilog2(MSM_GPU_RINGBUFFER_BLKSIZE / 8))) + +static inline struct msm_ringbuffer *__get_ring(struct msm_gpu *gpu, int index) +{ + return (index < ARRAY_SIZE(gpu->rb) ? gpu->rb[index] : NULL); +} + +#define FOR_EACH_RING(gpu, ring, index) \ + for (index = 0, ring = (gpu)->rb[0]; \ + index < (gpu)->nr_rings && index < ARRAY_SIZE((gpu)->rb); \ + index++, ring = __get_ring(gpu, index)) + static inline bool msm_gpu_active(struct msm_gpu *gpu) { - return gpu->submitted_fence > gpu->funcs->last_fence(gpu); + struct msm_ringbuffer *ring; + int i; + + FOR_EACH_RING(gpu, ring, i) { + if (gpu->funcs->submitted_fence(gpu, ring) > + ring->memptrs->fence) + return true; + } + + return false; } /* Perf-Counters: @@ -151,25 +223,84 @@ return msm_readl(gpu->mmio + (reg << 2)); } +static inline void gpu_rmw(struct msm_gpu *gpu, u32 reg, u32 mask, u32 or) +{ + uint32_t val = gpu_read(gpu, reg); + + val &= ~mask; + gpu_write(gpu, reg, val | or); +} + +static inline u64 gpu_read64(struct msm_gpu *gpu, u32 lo, u32 hi) +{ + u64 val; + + /* + * Why not a readq here? Two reasons: 1) many of the LO registers are + * not quad word aligned and 2) the GPU hardware designers have a bit + * of a history of putting registers where they fit, especially in + * spins. The longer a GPU family goes the higher the chance that + * we'll get burned. We could do a series of validity checks if we + * wanted to, but really is a readq() that much better? Nah. + */ + + /* + * For some lo/hi registers (like perfcounters), the hi value is latched + * when the lo is read, so make sure to read the lo first to trigger + * that + */ + val = (u64) msm_readl(gpu->mmio + (lo << 2)); + val |= ((u64) msm_readl(gpu->mmio + (hi << 2)) << 32); + + return val; +} + +static inline void gpu_write64(struct msm_gpu *gpu, u32 lo, u32 hi, u64 val) +{ + /* Why not a writeq here? Read the screed above */ + msm_writel(lower_32_bits(val), gpu->mmio + (lo << 2)); + msm_writel(upper_32_bits(val), gpu->mmio + (hi << 2)); +} + int msm_gpu_pm_suspend(struct msm_gpu *gpu); int msm_gpu_pm_resume(struct msm_gpu *gpu); +int msm_gpu_hw_init(struct msm_gpu *gpu); + void msm_gpu_perfcntr_start(struct msm_gpu *gpu); void msm_gpu_perfcntr_stop(struct msm_gpu *gpu); int msm_gpu_perfcntr_sample(struct msm_gpu *gpu, uint32_t *activetime, uint32_t *totaltime, uint32_t ncntrs, uint32_t *cntrs); void msm_gpu_retire(struct msm_gpu *gpu); -int msm_gpu_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit, - struct msm_file_private *ctx); +int msm_gpu_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit); int msm_gpu_init(struct drm_device *drm, struct platform_device *pdev, struct msm_gpu *gpu, const struct msm_gpu_funcs *funcs, - const char *name, const char *ioname, const char *irqname, int ringsz); + const char *name, struct msm_gpu_config *config); + void msm_gpu_cleanup(struct msm_gpu *gpu); struct msm_gpu *adreno_load_gpu(struct drm_device *dev); void __init adreno_register(void); void __exit adreno_unregister(void); +int msm_gpu_counter_get(struct msm_gpu *gpu, struct drm_msm_counter *data, + struct msm_file_private *ctx); + +int msm_gpu_counter_put(struct msm_gpu *gpu, struct drm_msm_counter *data, + struct msm_file_private *ctx); + +void msm_gpu_cleanup_counters(struct msm_gpu *gpu, + struct msm_file_private *ctx); + +u64 msm_gpu_counter_read(struct msm_gpu *gpu, + struct drm_msm_counter_read *data); + +static inline void msm_submitqueue_put(struct msm_gpu_submitqueue *queue) +{ + if (queue) + kref_put(&queue->ref, msm_submitqueue_destroy); +} + #endif /* __MSM_GPU_H__ */ diff -ruw linux-4.4.115/drivers/gpu/drm/msm/msm_iommu.c linux-4.4.115-fbx/drivers/gpu/drm/msm/msm_iommu.c --- linux-4.4.115/drivers/gpu/drm/msm/msm_iommu.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/gpu/drm/msm/msm_iommu.c 2019-10-29 09:26:23.633203080 +0100 @@ -15,98 +15,206 @@ * this program. If not, see . */ +#include +#include +#include #include "msm_drv.h" -#include "msm_mmu.h" - -struct msm_iommu { - struct msm_mmu base; - struct iommu_domain *domain; -}; -#define to_msm_iommu(x) container_of(x, struct msm_iommu, base) +#include "msm_iommu.h" static int msm_fault_handler(struct iommu_domain *iommu, struct device *dev, unsigned long iova, int flags, void *arg) { - pr_warn_ratelimited("*** fault: iova=%08lx, flags=%d\n", iova, flags); + pr_warn_ratelimited("*** fault: iova=%16llX, flags=%d\n", (u64) iova, flags); return 0; } -static int msm_iommu_attach(struct msm_mmu *mmu, const char **names, int cnt) +static void iommu_get_clocks(struct msm_iommu *iommu, struct device *dev) +{ + struct property *prop; + const char *name; + int i = 0; + + iommu->nr_clocks = + of_property_count_strings(dev->of_node, "clock-names"); + + if (iommu->nr_clocks < 0) + return; + + if (WARN_ON(iommu->nr_clocks > ARRAY_SIZE(iommu->clocks))) + iommu->nr_clocks = ARRAY_SIZE(iommu->clocks); + + of_property_for_each_string(dev->of_node, "clock-names", prop, name) { + if (i == iommu->nr_clocks) + break; + + iommu->clocks[i++] = clk_get(dev, name); + } +} + + +static void msm_iommu_clocks_enable(struct msm_mmu *mmu) { struct msm_iommu *iommu = to_msm_iommu(mmu); - return iommu_attach_device(iommu->domain, mmu->dev); + int i; + + if (!iommu->nr_clocks) + iommu_get_clocks(iommu, mmu->dev->parent); + + for (i = 0; i < iommu->nr_clocks; i++) { + if (iommu->clocks[i]) + clk_prepare_enable(iommu->clocks[i]); + } } -static void msm_iommu_detach(struct msm_mmu *mmu, const char **names, int cnt) +static void msm_iommu_clocks_disable(struct msm_mmu *mmu) { struct msm_iommu *iommu = to_msm_iommu(mmu); - iommu_detach_device(iommu->domain, mmu->dev); + int i; + + for (i = 0; i < iommu->nr_clocks; i++) { + if (iommu->clocks[i]) + clk_disable_unprepare(iommu->clocks[i]); + } } -static int msm_iommu_map(struct msm_mmu *mmu, uint32_t iova, - struct sg_table *sgt, unsigned len, int prot) +static int msm_iommu_attach(struct msm_mmu *mmu, const char **names, + int cnt) { struct msm_iommu *iommu = to_msm_iommu(mmu); - struct iommu_domain *domain = iommu->domain; - struct scatterlist *sg; - unsigned int da = iova; - unsigned int i, j; - int ret; - if (!domain || !sgt) - return -EINVAL; + return iommu_attach_device(iommu->domain, mmu->dev); +} + +static int msm_iommu_attach_user(struct msm_mmu *mmu, const char **names, + int cnt) +{ + struct msm_iommu *iommu = to_msm_iommu(mmu); + int ret, val = 1; - for_each_sg(sgt->sgl, sg, sgt->nents, i) { - u32 pa = sg_phys(sg) - sg->offset; - size_t bytes = sg->length + sg->offset; + /* Hope springs eternal */ + iommu->allow_dynamic = !iommu_domain_set_attr(iommu->domain, + DOMAIN_ATTR_ENABLE_TTBR1, &val) ? true : false; - VERB("map[%d]: %08x %08x(%zx)", i, iova, pa, bytes); + /* Mark the GPU as I/O coherent if it is supported */ + iommu->is_coherent = of_dma_is_coherent(mmu->dev->of_node); - ret = iommu_map(domain, da, pa, bytes, prot); + ret = iommu_attach_device(iommu->domain, mmu->dev); if (ret) - goto fail; + return ret; - da += bytes; - } + /* + * Get the context bank for the base domain; this will be shared with + * the children. + */ + iommu->cb = -1; + if (iommu_domain_get_attr(iommu->domain, DOMAIN_ATTR_CONTEXT_BANK, + &iommu->cb)) + iommu->allow_dynamic = false; return 0; +} + +static int msm_iommu_attach_dynamic(struct msm_mmu *mmu, const char **names, + int cnt) +{ + static unsigned int procid; + struct msm_iommu *iommu = to_msm_iommu(mmu); + int ret; + unsigned int id; + + /* Assign a unique procid for the domain to cut down on TLB churn */ + id = ++procid; + + iommu_domain_set_attr(iommu->domain, DOMAIN_ATTR_PROCID, &id); + + ret = iommu_attach_device(iommu->domain, mmu->dev); + if (ret) + return ret; -fail: - da = iova; + /* + * Get the TTBR0 and the CONTEXTIDR - these will be used by the GPU to + * switch the pagetable on its own. + */ + iommu_domain_get_attr(iommu->domain, DOMAIN_ATTR_TTBR0, + &iommu->ttbr0); + iommu_domain_get_attr(iommu->domain, DOMAIN_ATTR_CONTEXTIDR, + &iommu->contextidr); - for_each_sg(sgt->sgl, sg, i, j) { - size_t bytes = sg->length + sg->offset; - iommu_unmap(domain, da, bytes); - da += bytes; + return 0; } + +static int msm_iommu_attach_secure(struct msm_mmu *mmu, const char **names, + int cnt) +{ + struct msm_iommu *iommu = to_msm_iommu(mmu); + int ret, vmid = VMID_CP_PIXEL; + + ret = iommu_domain_set_attr(iommu->domain, DOMAIN_ATTR_SECURE_VMID, + &vmid); + if (ret) return ret; + + return iommu_attach_device(iommu->domain, mmu->dev); +} + +static void msm_iommu_detach(struct msm_mmu *mmu) +{ + struct msm_iommu *iommu = to_msm_iommu(mmu); + + iommu_detach_device(iommu->domain, mmu->dev); +} + +static void msm_iommu_detach_dynamic(struct msm_mmu *mmu) +{ + struct msm_iommu *iommu = to_msm_iommu(mmu); + iommu_detach_device(iommu->domain, mmu->dev); } -static int msm_iommu_unmap(struct msm_mmu *mmu, uint32_t iova, - struct sg_table *sgt, unsigned len) +static int msm_iommu_map(struct msm_mmu *mmu, uint64_t iova, + struct sg_table *sgt, u32 flags, void *priv) { struct msm_iommu *iommu = to_msm_iommu(mmu); struct iommu_domain *domain = iommu->domain; - struct scatterlist *sg; - unsigned int da = iova; - int i; + int ret; + u32 prot = IOMMU_READ; + + if (!domain || !sgt) + return -EINVAL; - for_each_sg(sgt->sgl, sg, sgt->nents, i) { - size_t bytes = sg->length + sg->offset; - size_t unmapped; + if (!(flags & MSM_BO_GPU_READONLY)) + prot |= IOMMU_WRITE; - unmapped = iommu_unmap(domain, da, bytes); - if (unmapped < bytes) - return unmapped; + if (flags & MSM_BO_PRIVILEGED) + prot |= IOMMU_PRIV; - VERB("unmap[%d]: %08x(%zx)", i, iova, bytes); + if ((flags & MSM_BO_CACHED) && msm_iommu_coherent(mmu)) + prot |= IOMMU_CACHE; - BUG_ON(!PAGE_ALIGNED(bytes)); + /* iommu_map_sg returns the number of bytes mapped */ + ret = iommu_map_sg(domain, iova, sgt->sgl, sgt->nents, prot); + if (ret) + sgt->sgl->dma_address = iova; - da += bytes; + return ret ? 0 : -ENOMEM; } - return 0; +static void msm_iommu_unmap(struct msm_mmu *mmu, uint64_t iova, + struct sg_table *sgt, void *priv) +{ + struct msm_iommu *iommu = to_msm_iommu(mmu); + struct iommu_domain *domain = iommu->domain; + struct scatterlist *sg; + size_t len = 0; + int ret, i; + + for_each_sg(sgt->sgl, sg, sgt->nents, i) + len += sg->length; + + ret = iommu_unmap(domain, iova, len); + if (ret != len) + dev_warn(mmu->dev, "could not unmap iova %llx\n", iova); + + sgt->sgl->dma_address = 0; } static void msm_iommu_destroy(struct msm_mmu *mmu) @@ -116,7 +224,30 @@ kfree(iommu); } -static const struct msm_mmu_funcs funcs = { +static struct device *find_context_bank(const char *name) +{ + struct device_node *node = of_find_node_by_name(NULL, name); + struct platform_device *pdev, *parent; + + if (!node) + return ERR_PTR(-ENODEV); + + if (!of_find_property(node, "iommus", NULL)) + return ERR_PTR(-ENODEV); + + /* Get the parent device */ + parent = of_find_device_by_node(node->parent); + + /* Populate the sub nodes */ + of_platform_populate(parent->dev.of_node, NULL, NULL, &parent->dev); + + /* Get the context bank device */ + pdev = of_find_device_by_node(node); + + return pdev ? &pdev->dev : ERR_PTR(-ENODEV); +} + +static const struct msm_mmu_funcs default_funcs = { .attach = msm_iommu_attach, .detach = msm_iommu_detach, .map = msm_iommu_map, @@ -124,7 +255,52 @@ .destroy = msm_iommu_destroy, }; -struct msm_mmu *msm_iommu_new(struct device *dev, struct iommu_domain *domain) +static const struct msm_mmu_funcs user_funcs = { + .attach = msm_iommu_attach_user, + .detach = msm_iommu_detach, + .map = msm_iommu_map, + .unmap = msm_iommu_unmap, + .destroy = msm_iommu_destroy, + .enable = msm_iommu_clocks_enable, + .disable = msm_iommu_clocks_disable, +}; + +static const struct msm_mmu_funcs secure_funcs = { + .attach = msm_iommu_attach_secure, + .detach = msm_iommu_detach, + .map = msm_iommu_map, + .unmap = msm_iommu_unmap, + .destroy = msm_iommu_destroy, +}; + +static const struct msm_mmu_funcs dynamic_funcs = { + .attach = msm_iommu_attach_dynamic, + .detach = msm_iommu_detach_dynamic, + .map = msm_iommu_map, + .unmap = msm_iommu_unmap, + .destroy = msm_iommu_destroy, +}; + +static const struct { + const char *cbname; + const struct msm_mmu_funcs *funcs; +} msm_iommu_domains[] = { + [MSM_IOMMU_DOMAIN_DEFAULT] = { + .cbname = NULL, + .funcs = &default_funcs, + }, + [MSM_IOMMU_DOMAIN_USER] = { + .cbname = "gfx3d_user", + .funcs = &user_funcs, + }, + [MSM_IOMMU_DOMAIN_SECURE] = { + .cbname = "gfx3d_secure", + .funcs = &secure_funcs + }, +}; + +static struct msm_mmu *iommu_create(struct device *dev, + struct iommu_domain *domain, const struct msm_mmu_funcs *funcs) { struct msm_iommu *iommu; @@ -133,8 +309,73 @@ return ERR_PTR(-ENOMEM); iommu->domain = domain; - msm_mmu_init(&iommu->base, dev, &funcs); + msm_mmu_init(&iommu->base, dev, funcs); iommu_set_fault_handler(domain, msm_fault_handler, dev); return &iommu->base; } + +struct msm_mmu *msm_iommu_new(struct device *parent, + enum msm_iommu_domain_type type, struct iommu_domain *domain) +{ + struct device *dev = parent; + + if (type >= ARRAY_SIZE(msm_iommu_domains) || + !msm_iommu_domains[type].funcs) + return ERR_PTR(-ENODEV); + + if (msm_iommu_domains[type].cbname) { + dev = find_context_bank(msm_iommu_domains[type].cbname); + if (IS_ERR(dev)) + return ERR_CAST(dev); + } + + return iommu_create(dev, domain, msm_iommu_domains[type].funcs); +} + +/* + * Given a base domain that is attached to a IOMMU device try to create a + * dynamic domain that is also attached to the same device but allocates a new + * pagetable. This is used to allow multiple pagetables to be attached to the + * same device. + */ +struct msm_mmu *msm_iommu_new_dynamic(struct msm_mmu *base) +{ + struct msm_iommu *base_iommu = to_msm_iommu(base); + struct iommu_domain *domain; + struct msm_mmu *mmu; + int ret, val = 1; + struct msm_iommu *child_iommu; + + /* Don't continue if the base domain didn't have the support we need */ + if (!base || base_iommu->allow_dynamic == false) + return ERR_PTR(-EOPNOTSUPP); + + domain = iommu_domain_alloc(&platform_bus_type); + if (!domain) + return ERR_PTR(-ENODEV); + + mmu = iommu_create(base->dev, domain, &dynamic_funcs); + + if (IS_ERR(mmu)) { + if (domain) + iommu_domain_free(domain); + return mmu; + } + + ret = iommu_domain_set_attr(domain, DOMAIN_ATTR_DYNAMIC, &val); + if (ret) { + msm_iommu_destroy(mmu); + return ERR_PTR(ret); + } + + /* Set the context bank to match the base domain */ + iommu_domain_set_attr(domain, DOMAIN_ATTR_CONTEXT_BANK, + &base_iommu->cb); + + /* Mark the dynamic domain as I/O coherent if the base domain is */ + child_iommu = to_msm_iommu(mmu); + child_iommu->is_coherent = base_iommu->is_coherent; + + return mmu; +} diff -ruw linux-4.4.115/drivers/gpu/drm/msm/msm_kms.h linux-4.4.115-fbx/drivers/gpu/drm/msm/msm_kms.h --- linux-4.4.115/drivers/gpu/drm/msm/msm_kms.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/gpu/drm/msm/msm_kms.h 2019-10-29 09:26:23.633203080 +0100 @@ -1,4 +1,5 @@ /* + * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. * Copyright (C) 2013 Red Hat * Author: Rob Clark * @@ -25,6 +26,33 @@ #define MAX_PLANE 4 +/** + * Device Private DRM Mode Flags + * drm_mode->private_flags + */ +/* Connector has interpreted seamless transition request as dynamic fps */ +#define MSM_MODE_FLAG_SEAMLESS_DYNAMIC_FPS (1<<0) +/* Transition to new mode requires a wait-for-vblank before the modeset */ +#define MSM_MODE_FLAG_VBLANK_PRE_MODESET (1<<1) +/* + * We need setting some flags in bridge, and using them in encoder. Add them in + * private_flags would be better for use. DRM_MODE_FLAG_SUPPORTS_RGB/YUV are + * flags that indicating the SINK supported color formats read from EDID. While, + * these flags defined here indicate the best color/bit depth foramt we choosed + * that would be better for display. For example the best mode display like: + * RGB+RGB_DC,YUV+YUV_DC, RGB,YUV. And we could not set RGB and YUV format at + * the same time. And also RGB_DC only set when RGB format is set,the same for + * YUV_DC. + */ +/* Enable RGB444 30 bit deep color */ +#define MSM_MODE_FLAG_RGB444_DC_ENABLE (1<<2) +/* Enable YUV420 30 bit deep color */ +#define MSM_MODE_FLAG_YUV420_DC_ENABLE (1<<3) +/* Choose RGB444 format to display */ +#define MSM_MODE_FLAG_COLOR_FORMAT_RGB444 (1<<4) +/* Choose YUV420 format to display */ +#define MSM_MODE_FLAG_COLOR_FORMAT_YCBCR420 (1<<5) + /* As there are different display controller blocks depending on the * snapdragon version, the kms support is split out and the appropriate * implementation is loaded at runtime. The kms module is responsible @@ -33,6 +61,7 @@ struct msm_kms_funcs { /* hw initialization: */ int (*hw_init)(struct msm_kms *kms); + int (*postinit)(struct msm_kms *kms); /* irq handling: */ void (*irq_preinstall)(struct msm_kms *kms); int (*irq_postinstall)(struct msm_kms *kms); @@ -41,21 +70,38 @@ int (*enable_vblank)(struct msm_kms *kms, struct drm_crtc *crtc); void (*disable_vblank)(struct msm_kms *kms, struct drm_crtc *crtc); /* modeset, bracketing atomic_commit(): */ - void (*prepare_commit)(struct msm_kms *kms, struct drm_atomic_state *state); - void (*complete_commit)(struct msm_kms *kms, struct drm_atomic_state *state); + void (*prepare_fence)(struct msm_kms *kms, + struct drm_atomic_state *state); + void (*prepare_commit)(struct msm_kms *kms, + struct drm_atomic_state *state); + void (*commit)(struct msm_kms *kms, struct drm_atomic_state *state); + void (*complete_commit)(struct msm_kms *kms, + struct drm_atomic_state *state); /* functions to wait for atomic commit completed on each CRTC */ void (*wait_for_crtc_commit_done)(struct msm_kms *kms, struct drm_crtc *crtc); + /* get msm_format w/ optional format modifiers from drm_mode_fb_cmd2 */ + const struct msm_format *(*get_format)(struct msm_kms *kms, + const uint32_t format, + const uint64_t *modifiers, + const uint32_t modifiers_len); + /* do format checking on format modified through fb_cmd2 modifiers */ + int (*check_modified_format)(const struct msm_kms *kms, + const struct msm_format *msm_fmt, + const struct drm_mode_fb_cmd2 *cmd, + struct drm_gem_object **bos); /* misc: */ - const struct msm_format *(*get_format)(struct msm_kms *kms, uint32_t format); long (*round_pixclk)(struct msm_kms *kms, unsigned long rate, struct drm_encoder *encoder); int (*set_split_display)(struct msm_kms *kms, struct drm_encoder *encoder, struct drm_encoder *slave_encoder, bool is_cmd_mode); + void (*postopen)(struct msm_kms *kms, struct drm_file *file); /* cleanup: */ void (*preclose)(struct msm_kms *kms, struct drm_file *file); + void (*postclose)(struct msm_kms *kms, struct drm_file *file); + void (*lastclose)(struct msm_kms *kms); void (*destroy)(struct msm_kms *kms); }; @@ -74,7 +120,33 @@ kms->funcs = funcs; } +#ifdef CONFIG_DRM_MSM_MDP4 struct msm_kms *mdp4_kms_init(struct drm_device *dev); +#else +static inline +struct msm_kms *mdp4_kms_init(struct drm_device *dev) { return NULL; }; +#endif struct msm_kms *mdp5_kms_init(struct drm_device *dev); +struct msm_kms *sde_kms_init(struct drm_device *dev); + +/** + * Mode Set Utility Functions + */ +static inline bool msm_is_mode_seamless(const struct drm_display_mode *mode) +{ + return (mode->flags & DRM_MODE_FLAG_SEAMLESS); +} + +static inline bool msm_is_mode_dynamic_fps(const struct drm_display_mode *mode) +{ + return ((mode->flags & DRM_MODE_FLAG_SEAMLESS) && + (mode->private_flags & MSM_MODE_FLAG_SEAMLESS_DYNAMIC_FPS)); +} + +static inline bool msm_needs_vblank_pre_modeset( + const struct drm_display_mode *mode) +{ + return (mode->private_flags & MSM_MODE_FLAG_VBLANK_PRE_MODESET); +} #endif /* __MSM_KMS_H__ */ diff -ruw linux-4.4.115/drivers/gpu/drm/msm/msm_mmu.h linux-4.4.115-fbx/drivers/gpu/drm/msm/msm_mmu.h --- linux-4.4.115/drivers/gpu/drm/msm/msm_mmu.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/gpu/drm/msm/msm_mmu.h 2019-01-22 16:16:23.507246443 +0100 @@ -20,14 +20,34 @@ #include +struct msm_mmu; + +enum msm_mmu_domain_type { + MSM_SMMU_DOMAIN_UNSECURE, + MSM_SMMU_DOMAIN_NRT_UNSECURE, + MSM_SMMU_DOMAIN_SECURE, + MSM_SMMU_DOMAIN_NRT_SECURE, + MSM_SMMU_DOMAIN_MAX, +}; + +enum msm_iommu_domain_type { + MSM_IOMMU_DOMAIN_DEFAULT, + MSM_IOMMU_DOMAIN_USER, + MSM_IOMMU_DOMAIN_SECURE, +}; + struct msm_mmu_funcs { int (*attach)(struct msm_mmu *mmu, const char **names, int cnt); - void (*detach)(struct msm_mmu *mmu, const char **names, int cnt); - int (*map)(struct msm_mmu *mmu, uint32_t iova, struct sg_table *sgt, - unsigned len, int prot); - int (*unmap)(struct msm_mmu *mmu, uint32_t iova, struct sg_table *sgt, - unsigned len); + void (*detach)(struct msm_mmu *mmu); + int (*map)(struct msm_mmu *mmu, uint64_t iova, struct sg_table *sgt, + u32 flags, void *priv); + void (*unmap)(struct msm_mmu *mmu, uint64_t iova, struct sg_table *sgt, + void *priv); void (*destroy)(struct msm_mmu *mmu); + void (*enable)(struct msm_mmu *mmu); + void (*disable)(struct msm_mmu *mmu); + int (*set_property)(struct msm_mmu *mmu, + enum iommu_attr attr, void *data); }; struct msm_mmu { @@ -42,7 +62,31 @@ mmu->funcs = funcs; } -struct msm_mmu *msm_iommu_new(struct device *dev, struct iommu_domain *domain); -struct msm_mmu *msm_gpummu_new(struct device *dev, struct msm_gpu *gpu); +/* Create a new SDE mmu device */ +struct msm_mmu *msm_smmu_new(struct device *dev, + enum msm_mmu_domain_type domain); + +/* Create a new legacy MDP4 or GPU mmu device */ +struct msm_mmu *msm_iommu_new(struct device *parent, + enum msm_iommu_domain_type type, struct iommu_domain *domain); + +/* Create a new dynamic domain for GPU */ +struct msm_mmu *msm_iommu_new_dynamic(struct msm_mmu *orig); + +static inline void msm_mmu_enable(struct msm_mmu *mmu) +{ + if (mmu->funcs->enable) + mmu->funcs->enable(mmu); +} + +static inline void msm_mmu_disable(struct msm_mmu *mmu) +{ + if (mmu->funcs->disable) + mmu->funcs->disable(mmu); +} + +/* SDE smmu driver initialize and cleanup functions */ +int __init msm_smmu_driver_init(void); +void __exit msm_smmu_driver_cleanup(void); #endif /* __MSM_MMU_H__ */ diff -ruw linux-4.4.115/drivers/gpu/drm/msm/msm_rd.c linux-4.4.115-fbx/drivers/gpu/drm/msm/msm_rd.c --- linux-4.4.115/drivers/gpu/drm/msm/msm_rd.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/gpu/drm/msm/msm_rd.c 2019-10-29 09:26:23.637203119 +0100 @@ -27,6 +27,11 @@ * This bypasses drm_debugfs_create_files() mainly because we need to use * our own fops for a bit more control. In particular, we don't want to * do anything if userspace doesn't have the debugfs file open. + * + * The module-param "rd_full", which defaults to false, enables snapshotting + * all (non-written) buffers in the submit, rather than just cmdstream bo's. + * This is useful to capture the contents of (for example) vbo's or textures, + * or shader programs (if not emitted inline in cmdstream). */ #ifdef CONFIG_DEBUG_FS @@ -40,6 +45,10 @@ #include "msm_gpu.h" #include "msm_gem.h" +static bool rd_full = false; +MODULE_PARM_DESC(rd_full, "If true, $debugfs/.../rd will snapshot all buffer contents"); +module_param_named(rd_full, rd_full, bool, 0600); + enum rd_sect_type { RD_NONE, RD_TEST, /* ascii text */ @@ -277,6 +286,36 @@ kfree(rd); } +static void snapshot_buf(struct msm_rd_state *rd, + struct msm_gem_submit *submit, int idx, + uint64_t iova, uint32_t size) +{ + struct msm_gem_object *obj = submit->bos[idx].obj; + uint64_t offset = 0; + + if (iova) { + offset = iova - submit->bos[idx].iova; + } else { + iova = submit->bos[idx].iova; + size = obj->base.size; + } + + /* Always write the RD_GPUADDR so we know how big the buffer is */ + rd_write_section(rd, RD_GPUADDR, + (uint64_t[2]) { iova, size }, 16); + + /* But only dump contents for buffers marked as read and not secure */ + if (submit->bos[idx].flags & MSM_SUBMIT_BO_READ && + !(obj->flags & MSM_BO_SECURE)) { + const char *buf = msm_gem_vaddr(&obj->base); + + if (IS_ERR_OR_NULL(buf)) + return; + + rd_write_section(rd, RD_BUFFER_CONTENTS, buf + offset, size); + } +} + /* called under struct_mutex */ void msm_rd_dump_submit(struct msm_gem_submit *submit) { @@ -300,24 +339,20 @@ rd_write_section(rd, RD_CMD, msg, ALIGN(n, 4)); - /* could be nice to have an option (module-param?) to snapshot - * all the bo's associated with the submit. Handy to see vtx - * buffers, etc. For now just the cmdstream bo's is enough. - */ + if (rd_full) { + for (i = 0; i < submit->nr_bos; i++) + snapshot_buf(rd, submit, i, 0, 0); + } for (i = 0; i < submit->nr_cmds; i++) { - uint32_t idx = submit->cmd[i].idx; - uint32_t iova = submit->cmd[i].iova; + uint64_t iova = submit->cmd[i].iova; uint32_t szd = submit->cmd[i].size; /* in dwords */ - struct msm_gem_object *obj = submit->bos[idx].obj; - const char *buf = msm_gem_vaddr_locked(&obj->base); - - buf += iova - submit->bos[idx].iova; - rd_write_section(rd, RD_GPUADDR, - (uint32_t[2]){ iova, szd * 4 }, 8); - rd_write_section(rd, RD_BUFFER_CONTENTS, - buf, szd * 4); + /* snapshot cmdstream bo's (if we haven't already): */ + if (!rd_full) { + snapshot_buf(rd, submit, submit->cmd[i].idx, + submit->cmd[i].iova, szd * 4); + } switch (submit->cmd[i].type) { case MSM_SUBMIT_CMD_IB_TARGET_BUF: @@ -329,7 +364,7 @@ case MSM_SUBMIT_CMD_CTX_RESTORE_BUF: case MSM_SUBMIT_CMD_BUF: rd_write_section(rd, RD_CMDSTREAM_ADDR, - (uint32_t[2]){ iova, szd }, 8); + (uint64_t[2]) { iova, szd }, 16); break; } } diff -ruw linux-4.4.115/drivers/gpu/drm/msm/msm_ringbuffer.c linux-4.4.115-fbx/drivers/gpu/drm/msm/msm_ringbuffer.c --- linux-4.4.115/drivers/gpu/drm/msm/msm_ringbuffer.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/gpu/drm/msm/msm_ringbuffer.c 2019-01-22 16:16:23.511246479 +0100 @@ -18,13 +18,14 @@ #include "msm_ringbuffer.h" #include "msm_gpu.h" -struct msm_ringbuffer *msm_ringbuffer_new(struct msm_gpu *gpu, int size) +struct msm_ringbuffer *msm_ringbuffer_new(struct msm_gpu *gpu, int id, + struct msm_memptrs *memptrs, uint64_t memptrs_iova) { struct msm_ringbuffer *ring; int ret; - if (WARN_ON(!is_power_of_2(size))) - return ERR_PTR(-EINVAL); + /* We assume everwhere that MSM_GPU_RINGBUFFER_SZ is a power of 2 */ + BUILD_BUG_ON(!is_power_of_2(MSM_GPU_RINGBUFFER_SZ)); ring = kzalloc(sizeof(*ring), GFP_KERNEL); if (!ring) { @@ -33,18 +34,26 @@ } ring->gpu = gpu; - ring->bo = msm_gem_new(gpu->dev, size, MSM_BO_WC); + ring->id = id; + ring->bo = msm_gem_new(gpu->dev, MSM_GPU_RINGBUFFER_SZ, + MSM_BO_WC); if (IS_ERR(ring->bo)) { ret = PTR_ERR(ring->bo); ring->bo = NULL; goto fail; } - ring->start = msm_gem_vaddr_locked(ring->bo); - ring->end = ring->start + (size / 4); + ring->memptrs = memptrs; + ring->memptrs_iova = memptrs_iova; + + + ring->start = msm_gem_vaddr(ring->bo); + ring->end = ring->start + (MSM_GPU_RINGBUFFER_SZ >> 2); + ring->next = ring->start; ring->cur = ring->start; - ring->size = size; + INIT_LIST_HEAD(&ring->submits); + spin_lock_init(&ring->lock); return ring; @@ -56,7 +65,10 @@ void msm_ringbuffer_destroy(struct msm_ringbuffer *ring) { - if (ring->bo) + if (ring && ring->bo) { + msm_gem_put_iova(ring->bo, ring->gpu->aspace); drm_gem_object_unreference_unlocked(ring->bo); + } + kfree(ring); } diff -ruw linux-4.4.115/drivers/gpu/drm/msm/msm_ringbuffer.h linux-4.4.115-fbx/drivers/gpu/drm/msm/msm_ringbuffer.h --- linux-4.4.115/drivers/gpu/drm/msm/msm_ringbuffer.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/gpu/drm/msm/msm_ringbuffer.h 2019-01-22 16:16:23.511246479 +0100 @@ -20,14 +20,46 @@ #include "msm_drv.h" +#define rbmemptr(ring, member) \ + ((ring)->memptrs_iova + offsetof(struct msm_memptrs, member)) + +struct msm_memptr_ticks { + uint64_t started; + uint64_t retired; +}; + +struct msm_memptrs { + volatile uint32_t rptr; + volatile uint32_t fence; + volatile uint64_t ttbr0; + volatile unsigned int contextidr; + struct msm_memptr_ticks ticks[128]; +}; + +#define RING_TICKS_IOVA(ring, index, field) \ + ((ring)->memptrs_iova + offsetof(struct msm_memptrs, ticks) + \ + ((index) * sizeof(struct msm_memptr_ticks)) + \ + offsetof(struct msm_memptr_ticks, field)) + struct msm_ringbuffer { struct msm_gpu *gpu; - int size; + int id; struct drm_gem_object *bo; - uint32_t *start, *end, *cur; + uint32_t *start, *end, *cur, *next; + uint64_t iova; + uint32_t seqno; + uint32_t submitted_fence; + spinlock_t lock; + struct list_head submits; + uint32_t hangcheck_fence; + + struct msm_memptrs *memptrs; + uint64_t memptrs_iova; + int tick_index; }; -struct msm_ringbuffer *msm_ringbuffer_new(struct msm_gpu *gpu, int size); +struct msm_ringbuffer *msm_ringbuffer_new(struct msm_gpu *gpu, int id, + struct msm_memptrs *memptrs, uint64_t memptrs_iova); void msm_ringbuffer_destroy(struct msm_ringbuffer *ring); /* ringbuffer helpers (the parts that are same for a3xx/a2xx/z180..) */ @@ -35,9 +67,13 @@ static inline void OUT_RING(struct msm_ringbuffer *ring, uint32_t data) { - if (ring->cur == ring->end) - ring->cur = ring->start; - *(ring->cur++) = data; + /* + * ring->next points to the current command being written - it won't be + * committed as ring->cur until the flush + */ + if (ring->next == ring->end) + ring->next = ring->start; + *(ring->next++) = data; } #endif /* __MSM_RINGBUFFER_H__ */ diff -ruw linux-4.4.115/drivers/gpu/Makefile linux-4.4.115-fbx/drivers/gpu/Makefile --- linux-4.4.115/drivers/gpu/Makefile 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/gpu/Makefile 2019-01-22 16:16:23.215243798 +0100 @@ -4,3 +4,4 @@ obj-$(CONFIG_TEGRA_HOST1X) += host1x/ obj-y += drm/ vga/ obj-$(CONFIG_IMX_IPUV3_CORE) += ipu-v3/ +obj-$(CONFIG_QCOM_KGSL) += msm/ diff -ruw linux-4.4.115/drivers/hid/hid-apple.c linux-4.4.115-fbx/drivers/hid/hid-apple.c --- linux-4.4.115/drivers/hid/hid-apple.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/hid/hid-apple.c 2019-01-22 16:16:23.731248471 +0100 @@ -440,6 +440,9 @@ .driver_data = APPLE_HAS_FN }, { HID_USB_DEVICE(USB_VENDOR_ID_APPLE, USB_DEVICE_ID_APPLE_ALU_ANSI), .driver_data = APPLE_HAS_FN }, + { HID_BLUETOOTH_DEVICE(USB_VENDOR_ID_APPLE, + USB_DEVICE_ID_APPLE_ALU_ANSI), + .driver_data = APPLE_HAS_FN }, { HID_USB_DEVICE(USB_VENDOR_ID_APPLE, USB_DEVICE_ID_APPLE_ALU_ISO), .driver_data = APPLE_HAS_FN | APPLE_ISO_KEYBOARD }, { HID_USB_DEVICE(USB_VENDOR_ID_APPLE, USB_DEVICE_ID_APPLE_ALU_JIS), diff -ruw linux-4.4.115/drivers/hid/hid-core.c linux-4.4.115-fbx/drivers/hid/hid-core.c --- linux-4.4.115/drivers/hid/hid-core.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/hid/hid-core.c 2019-10-29 09:26:23.697203707 +0100 @@ -1757,6 +1757,8 @@ { HID_USB_DEVICE(USB_VENDOR_ID_APPLE, USB_DEVICE_ID_APPLE_ALU_MINI_ISO) }, { HID_USB_DEVICE(USB_VENDOR_ID_APPLE, USB_DEVICE_ID_APPLE_ALU_MINI_JIS) }, { HID_USB_DEVICE(USB_VENDOR_ID_APPLE, USB_DEVICE_ID_APPLE_ALU_ANSI) }, + { HID_BLUETOOTH_DEVICE(USB_VENDOR_ID_APPLE, + USB_DEVICE_ID_APPLE_ALU_ANSI) }, { HID_USB_DEVICE(USB_VENDOR_ID_APPLE, USB_DEVICE_ID_APPLE_ALU_ISO) }, { HID_USB_DEVICE(USB_VENDOR_ID_APPLE, USB_DEVICE_ID_APPLE_ALU_JIS) }, { HID_USB_DEVICE(USB_VENDOR_ID_APPLE, USB_DEVICE_ID_APPLE_GEYSER4_HF_ANSI) }, @@ -2010,7 +2012,6 @@ { HID_USB_DEVICE(USB_VENDOR_ID_SONY, USB_DEVICE_ID_SONY_PS3_CONTROLLER) }, { HID_BLUETOOTH_DEVICE(USB_VENDOR_ID_SONY, USB_DEVICE_ID_SONY_PS3_CONTROLLER) }, { HID_USB_DEVICE(USB_VENDOR_ID_SONY, USB_DEVICE_ID_SONY_PS4_CONTROLLER) }, - { HID_BLUETOOTH_DEVICE(USB_VENDOR_ID_SONY, USB_DEVICE_ID_SONY_PS4_CONTROLLER) }, { HID_USB_DEVICE(USB_VENDOR_ID_SONY, USB_DEVICE_ID_SONY_VAIO_VGX_MOUSE) }, { HID_USB_DEVICE(USB_VENDOR_ID_SONY, USB_DEVICE_ID_SONY_VAIO_VGP_MOUSE) }, { HID_USB_DEVICE(USB_VENDOR_ID_STEELSERIES, USB_DEVICE_ID_STEELSERIES_SRWS1) }, @@ -2062,6 +2063,8 @@ { HID_BLUETOOTH_DEVICE(USB_VENDOR_ID_NINTENDO, USB_DEVICE_ID_NINTENDO_WIIMOTE) }, { HID_BLUETOOTH_DEVICE(USB_VENDOR_ID_NINTENDO, USB_DEVICE_ID_NINTENDO_WIIMOTE2) }, { HID_USB_DEVICE(USB_VENDOR_ID_RAZER, USB_DEVICE_ID_RAZER_BLADE_14) }, + { HID_BLUETOOTH_DEVICE(0x10eb, 0x0023) }, + { HID_BLUETOOTH_DEVICE(0x10eb, 0x0024) }, { } }; diff -ruw linux-4.4.115/drivers/hid/Kconfig linux-4.4.115-fbx/drivers/hid/Kconfig --- linux-4.4.115/drivers/hid/Kconfig 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/hid/Kconfig 2019-01-22 16:16:23.731248471 +0100 @@ -338,6 +338,10 @@ ---help--- Support for Waltop tablets. +config HID_FBX_REMOTE_AUDIO + tristate "Freebox BLE remote audio driver" + depends on HID && SND + config HID_GYRATION tristate "Gyration remote control" depends on HID diff -ruw linux-4.4.115/drivers/hid/Makefile linux-4.4.115-fbx/drivers/hid/Makefile --- linux-4.4.115/drivers/hid/Makefile 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/hid/Makefile 2019-01-22 16:16:23.731248471 +0100 @@ -40,6 +40,7 @@ obj-$(CONFIG_HID_GEMBIRD) += hid-gembird.o obj-$(CONFIG_HID_GFRM) += hid-gfrm.o obj-$(CONFIG_HID_GT683R) += hid-gt683r.o +obj-$(CONFIG_HID_FBX_REMOTE_AUDIO) += hid-fbx-remote-audio.o obj-$(CONFIG_HID_GYRATION) += hid-gyration.o obj-$(CONFIG_HID_HOLTEK) += hid-holtek-kbd.o obj-$(CONFIG_HID_HOLTEK) += hid-holtek-mouse.o diff -ruw linux-4.4.115/drivers/hid/uhid.c linux-4.4.115-fbx/drivers/hid/uhid.c --- linux-4.4.115/drivers/hid/uhid.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/hid/uhid.c 2019-10-29 09:26:23.705203785 +0100 @@ -28,6 +28,8 @@ #define UHID_NAME "uhid" #define UHID_BUFSIZE 32 +static DEFINE_MUTEX(uhid_open_mutex); + struct uhid_device { struct mutex devlock; bool running; @@ -142,15 +144,26 @@ static int uhid_hid_open(struct hid_device *hid) { struct uhid_device *uhid = hid->driver_data; + int retval = 0; - return uhid_queue_event(uhid, UHID_OPEN); + mutex_lock(&uhid_open_mutex); + if (!hid->open++) { + retval = uhid_queue_event(uhid, UHID_OPEN); + if (retval) + hid->open--; + } + mutex_unlock(&uhid_open_mutex); + return retval; } static void uhid_hid_close(struct hid_device *hid) { struct uhid_device *uhid = hid->driver_data; + mutex_lock(&uhid_open_mutex); + if (!--hid->open) uhid_queue_event(uhid, UHID_CLOSE); + mutex_unlock(&uhid_open_mutex); } static int uhid_hid_parse(struct hid_device *hid) diff -ruw linux-4.4.115/drivers/hid/usbhid/hiddev.c linux-4.4.115-fbx/drivers/hid/usbhid/hiddev.c --- linux-4.4.115/drivers/hid/usbhid/hiddev.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/hid/usbhid/hiddev.c 2019-10-29 09:26:23.705203785 +0100 @@ -510,13 +510,13 @@ goto inval; field = report->field[uref->field_index]; + } if (cmd == HIDIOCGCOLLECTIONINDEX) { if (uref->usage_index >= field->maxusage) goto inval; } else if (uref->usage_index >= field->report_count) goto inval; - } if ((cmd == HIDIOCGUSAGES || cmd == HIDIOCSUSAGES) && (uref_multi->num_values > HID_MAX_MULTI_USAGES || diff -ruw linux-4.4.115/drivers/hwmon/Kconfig linux-4.4.115-fbx/drivers/hwmon/Kconfig --- linux-4.4.115/drivers/hwmon/Kconfig 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/hwmon/Kconfig 2019-01-22 16:16:23.763248761 +0100 @@ -1200,6 +1200,34 @@ These devices are hard to detect and rarely found on mainstream hardware. If unsure, say N. +config SENSORS_EPM_ADC + tristate "EPM ADC Driver for power measurement" + depends on I2C && SPI_MASTER + default n + help + Provides interface for measuring the current on specific power rails + through the channels on ADC1158 ADC + +config SENSORS_QPNP_ADC_VOLTAGE + tristate "Support for Qualcomm QPNP Voltage ADC" + depends on SPMI + help + This is the VADC arbiter driver for Qualcomm QPNP ADC Chip. + + The driver supports reading the HKADC, XOADC through the ADC AMUX arbiter. + The VADC includes support for the conversion sequencer. The driver supports + reading the ADC through the AMUX channels for external pull-ups simultaneously. + +config SENSORS_QPNP_ADC_CURRENT + tristate "Support for Qualcomm QPNP current ADC" + depends on SPMI + help + This is the IADC driver for Qualcomm QPNP ADC Chip. + + The driver supports single mode operation to read from upto seven channel + configuration that include reading the external/internal Rsense, CSP_EX, + CSN_EX pair along with the gain and offset calibration. + source drivers/hwmon/pmbus/Kconfig config SENSORS_PWM_FAN diff -ruw linux-4.4.115/drivers/hwmon/Makefile linux-4.4.115-fbx/drivers/hwmon/Makefile --- linux-4.4.115/drivers/hwmon/Makefile 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/hwmon/Makefile 2019-01-22 16:16:23.763248761 +0100 @@ -160,6 +160,9 @@ obj-$(CONFIG_SENSORS_W83L786NG) += w83l786ng.o obj-$(CONFIG_SENSORS_WM831X) += wm831x-hwmon.o obj-$(CONFIG_SENSORS_WM8350) += wm8350-hwmon.o +obj-$(CONFIG_SENSORS_EPM_ADC) += epm_adc.o +obj-$(CONFIG_SENSORS_QPNP_ADC_VOLTAGE) += qpnp-adc-voltage.o qpnp-adc-common.o +obj-$(CONFIG_SENSORS_QPNP_ADC_CURRENT) += qpnp-adc-current.o qpnp-adc-common.o obj-$(CONFIG_PMBUS) += pmbus/ diff -ruw linux-4.4.115/drivers/hwspinlock/Kconfig linux-4.4.115-fbx/drivers/hwspinlock/Kconfig --- linux-4.4.115/drivers/hwspinlock/Kconfig 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/hwspinlock/Kconfig 2019-01-22 16:16:23.807249159 +0100 @@ -53,4 +53,15 @@ If unsure, say N. +config REMOTE_SPINLOCK_MSM + bool "MSM Remote Spinlock Functionality" + depends on ARCH_QCOM + select HWSPINLOCK + help + Say y here to support the MSM Remote Spinlock functionality, which + provides a synchronisation mechanism for the various processor on the + SoC. + + If unsure, say N. + endmenu diff -ruw linux-4.4.115/drivers/hwspinlock/Makefile linux-4.4.115-fbx/drivers/hwspinlock/Makefile --- linux-4.4.115/drivers/hwspinlock/Makefile 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/hwspinlock/Makefile 2019-01-22 16:16:23.807249159 +0100 @@ -7,3 +7,4 @@ obj-$(CONFIG_HWSPINLOCK_QCOM) += qcom_hwspinlock.o obj-$(CONFIG_HWSPINLOCK_SIRF) += sirf_hwspinlock.o obj-$(CONFIG_HSEM_U8500) += u8500_hsem.o +obj-$(CONFIG_REMOTE_SPINLOCK_MSM) += msm_remote_spinlock.o diff -ruw linux-4.4.115/drivers/hwtracing/coresight/Kconfig linux-4.4.115-fbx/drivers/hwtracing/coresight/Kconfig --- linux-4.4.115/drivers/hwtracing/coresight/Kconfig 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/hwtracing/coresight/Kconfig 2019-01-22 16:16:23.807249159 +0100 @@ -12,6 +12,23 @@ trace source gets enabled. if CORESIGHT + +config CORESIGHT_EVENT + tristate "CoreSight Event driver" + help + This driver provides support for registering with various events + and performing CoreSight actions like aborting trace on their + occurrence. These events can be controlled by using module + parameters. + +config CORESIGHT_CSR + bool "CoreSight Slave Register driver" + help + This driver provides support for CoreSight Slave Register block + that hosts miscellaneous configuration registers. + Those configuration registers can be used to control, various + coresight configurations. + config CORESIGHT_LINKS_AND_SINKS bool "CoreSight Link and Sink drivers" help @@ -23,6 +40,7 @@ config CORESIGHT_LINK_AND_SINK_TMC bool "Coresight generic TMC driver" depends on CORESIGHT_LINKS_AND_SINKS + select CORESIGHT_CSR help This enables support for the Trace Memory Controller driver. Depending on its configuration the device can act as a link (embedded @@ -61,7 +79,6 @@ config CORESIGHT_SOURCE_ETM4X bool "CoreSight Embedded Trace Macrocell 4.x driver" - depends on ARM64 select CORESIGHT_LINKS_AND_SINKS help This driver provides support for the ETM4.x tracer module, tracing the @@ -69,6 +86,22 @@ for instruction level tracing. Depending on the implemented version data tracing may also be available. +config CORESIGHT_REMOTE_ETM + bool "Remote processor ETM trace support" + depends on MSM_QMI_INTERFACE + help + Enables support for ETM trace collection on remote processor using + CoreSight framework. Enabling this will allow turning on ETM + tracing on remote processor via sysfs by configuring the required + CoreSight components. + +config CORESIGHT_REMOTE_ETM_DEFAULT_ENABLE + int "default enable bits for Remote processor ETM" + depends on CORESIGHT_REMOTE_ETM + help + Support for enabling separated Remote processor ETM tracing. Depends + on if instance id bit is set. + config CORESIGHT_QCOM_REPLICATOR bool "Qualcomm CoreSight Replicator driver" depends on CORESIGHT_LINKS_AND_SINKS @@ -77,4 +110,83 @@ programmable ATB replicator sends the ATB trace stream from the ETB/ETF to the TPIUi and ETR. +config CORESIGHT_STM + bool "CoreSight System Trace Macrocell driver" + select CORESIGHT_LINKS_AND_SINKS + help + This driver provides support for hardware assisted software + instrumentation based tracing. This is primarily useful for + logging useful software events or data. + +config CORESIGHT_HWEVENT + bool "CoreSight Hardware Event driver" + depends on CORESIGHT_STM + select CORESIGHT_CSR + help + This driver provides support for monitoring and tracing CoreSight + Hardware Event across STM interface. It configures Coresight + Hardware Event mux control registers to select hardware events + based on user input. + +config CORESIGHT_CTI + bool "CoreSight Cross Trigger Interface driver" + help + This driver provides support for Cross Trigger Interface that is + used to input or output i.e. pass cross trigger events from one + hardware component to another. It can also be used to pass + software generated events. + +config CORESIGHT_CTI_SAVE_DISABLE + bool "Turn off CTI save and restore" + depends on CORESIGHT_CTI + help + Turns off CoreSight CTI save and restore support for cpu CTIs. This + avoids voting for the clocks during probe as well as the associated + save and restore latency at the cost of breaking cpu CTI support on + targets where cpu CTIs have to be preserved across power collapse. + + If unsure, say 'N' here to avoid breaking cpu CTI support. + +config CORESIGHT_TPDA + bool "CoreSight Trace, Profiling & Diagnostics Aggregator driver" + help + This driver provides support for configuring aggregator. This is + primarily useful for pulling the data sets from one or more + attached monitors and pushing the resultant data out. Multiple + monitors are connected on different input ports of TPDA. + +config CORESIGHT_TPDM + bool "CoreSight Trace, Profiling & Diagnostics Monitor driver" + help + This driver provides support for configuring monitor. Monitors are + primarily responsible for data set collection and support the + ability to collect any permutation of data set types. Monitors are + also responsible for interaction with system cross triggering. + +config CORESIGHT_TPDM_DEFAULT_ENABLE + bool "Turn on TPDM tracing by default" + depends on CORESIGHT_TPDM + help + Turns on CoreSight TPDM tracing for different data set types by + default. Otherwise, tracing is disabled by default but can be + enabled via sysfs. + + If unsure, say 'N' here to avoid potential power and performance + penalty. + +config CORESIGHT_QPDI + bool "CoreSight PMIC debug interface support" + help + This driver provides support for controlling the PMIC debug interface + feature. When enabled via sysfs it allows disagnostic access to the + PMIC. Similarly this debug feature can be disabled via sysfs which + prevents debug dongle detection. + +config CORESIGHT_SOURCE_DUMMY + bool "Dummy source support" + help + Enables support for dummy source devices. Dummy source driver can be + used for CoreSight sources that are owned and configured by some other + subsystem and use Linux drivers to configure rest of trace path. + endif diff -ruw linux-4.4.115/drivers/hwtracing/coresight/Makefile linux-4.4.115-fbx/drivers/hwtracing/coresight/Makefile --- linux-4.4.115/drivers/hwtracing/coresight/Makefile 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/hwtracing/coresight/Makefile 2019-01-22 16:16:23.807249159 +0100 @@ -3,6 +3,9 @@ # obj-$(CONFIG_CORESIGHT) += coresight.o obj-$(CONFIG_OF) += of_coresight.o +obj-$(CONFIG_CORESIGHT_CSR) += coresight-csr.o +obj-$(CONFIG_CORESIGHT_EVENT) += coresight-event.o +obj-$(CONFIG_CORESIGHT_CTI) += coresight-cti.o obj-$(CONFIG_CORESIGHT_LINK_AND_SINK_TMC) += coresight-tmc.o obj-$(CONFIG_CORESIGHT_SINK_TPIU) += coresight-tpiu.o obj-$(CONFIG_CORESIGHT_SINK_ETBV10) += coresight-etb10.o @@ -11,3 +14,10 @@ obj-$(CONFIG_CORESIGHT_SOURCE_ETM3X) += coresight-etm3x.o coresight-etm-cp14.o obj-$(CONFIG_CORESIGHT_SOURCE_ETM4X) += coresight-etm4x.o obj-$(CONFIG_CORESIGHT_QCOM_REPLICATOR) += coresight-replicator-qcom.o +obj-$(CONFIG_CORESIGHT_STM) += coresight-stm.o +obj-$(CONFIG_CORESIGHT_TPDA) += coresight-tpda.o +obj-$(CONFIG_CORESIGHT_TPDM) += coresight-tpdm.o +obj-$(CONFIG_CORESIGHT_REMOTE_ETM) += coresight-remote-etm.o +obj-$(CONFIG_CORESIGHT_QPDI) += coresight-qpdi.o +obj-$(CONFIG_CORESIGHT_HWEVENT) += coresight-hwevent.o +obj-$(CONFIG_CORESIGHT_SOURCE_DUMMY) += coresight-dummy.o diff -ruw linux-4.4.115/drivers/hwtracing/stm/Kconfig linux-4.4.115-fbx/drivers/hwtracing/stm/Kconfig --- linux-4.4.115/drivers/hwtracing/stm/Kconfig 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/hwtracing/stm/Kconfig 2019-01-22 16:16:23.815249232 +0100 @@ -9,6 +9,8 @@ Say Y here to enable System Trace Module device support. +if STM + config STM_DUMMY tristate "Dummy STM driver" help @@ -25,3 +27,16 @@ If you want to send kernel console messages over STM devices, say Y. + +config STM_SOURCE_HEARTBEAT + tristate "Heartbeat over STM devices" + help + This is a kernel space trace source that sends periodic + heartbeat messages to trace hosts over STM devices. It is + also useful for testing stm class drivers and the stm class + framework itself. + + If you want to send heartbeat messages over STM devices, + say Y. + +endif diff -ruw linux-4.4.115/drivers/hwtracing/stm/Makefile linux-4.4.115-fbx/drivers/hwtracing/stm/Makefile --- linux-4.4.115/drivers/hwtracing/stm/Makefile 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/hwtracing/stm/Makefile 2019-01-22 16:16:23.815249232 +0100 @@ -5,5 +5,7 @@ obj-$(CONFIG_STM_DUMMY) += dummy_stm.o obj-$(CONFIG_STM_SOURCE_CONSOLE) += stm_console.o +obj-$(CONFIG_STM_SOURCE_HEARTBEAT) += stm_heartbeat.o stm_console-y := console.o +stm_heartbeat-y := heartbeat.o diff -ruw linux-4.4.115/drivers/i2c/algos/i2c-algo-bit.c linux-4.4.115-fbx/drivers/i2c/algos/i2c-algo-bit.c --- linux-4.4.115/drivers/i2c/algos/i2c-algo-bit.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/i2c/algos/i2c-algo-bit.c 2019-01-22 16:16:23.815249232 +0100 @@ -381,7 +381,8 @@ * the SMBus PEC was wrong. */ } else if (retval == 0) { - dev_err(&i2c_adap->dev, "sendbytes: NAK bailout.\n"); + dev_err(&i2c_adap->dev, "sendbytes: %02x NAK " + "bailout.\n", msg->addr); return -EIO; /* Timeout; or (someday) lost arbitration diff -ruw linux-4.4.115/drivers/i2c/busses/Kconfig linux-4.4.115-fbx/drivers/i2c/busses/Kconfig --- linux-4.4.115/drivers/i2c/busses/Kconfig 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/i2c/busses/Kconfig 2019-10-29 09:26:23.729204020 +0100 @@ -1198,4 +1198,16 @@ This driver can also be built as a module. If so, the module will be called as i2c-opal. +config I2C_MSM_V2 + tristate "I2C_MSM_V2" + depends on ARCH_QCOM + help + If you say yes to this option, support will be included for the + built-in I2C interface and its DMA engine on the MSM family + processors. + + This driver can also be built as a module. If so, the module + will be called i2c-msm-v2. + + endmenu diff -ruw linux-4.4.115/drivers/i2c/busses/Makefile linux-4.4.115-fbx/drivers/i2c/busses/Makefile --- linux-4.4.115/drivers/i2c/busses/Makefile 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/i2c/busses/Makefile 2019-10-29 09:26:23.729204020 +0100 @@ -96,6 +96,7 @@ obj-$(CONFIG_I2C_XLR) += i2c-xlr.o obj-$(CONFIG_I2C_XLP9XX) += i2c-xlp9xx.o obj-$(CONFIG_I2C_RCAR) += i2c-rcar.o +obj-$(CONFIG_I2C_MSM_V2) += i2c-msm-v2.o # External I2C/SMBus adapter drivers obj-$(CONFIG_I2C_DIOLAN_U2C) += i2c-diolan-u2c.o diff -ruw linux-4.4.115/drivers/iio/adc/Kconfig linux-4.4.115-fbx/drivers/iio/adc/Kconfig --- linux-4.4.115/drivers/iio/adc/Kconfig 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/iio/adc/Kconfig 2019-01-22 16:16:23.875249775 +0100 @@ -303,6 +303,33 @@ To compile this driver as a module, choose M here: the module will be called qcom-spmi-vadc. +config QCOM_RRADC + tristate "Qualcomm Technologies Inc. PMIC Round robin ADC" + depends on SPMI + select REGMAP_SPMI + help + This is the PMIC Round Robin ADC driver. + + The driver supports multiple channels read used for telemetry + and supports clients to read batt_id, batt_therm, PMIC die + temperature, USB_IN and DC_IN voltage and current. + The RRADC is a 10-bit ADC. + + To compile this driver as a module, choose M here: the module will + be called qcom-rradc. + +config QCOM_TADC + tristate "Qualcomm Technologies Inc. TADC driver" + depends on MFD_I2C_PMIC + help + Say yes here to support the Qualcomm Technologies Inc. telemetry ADC. + The TADC provides battery temperature, skin temperature, + die temperature, battery voltage, battery current, input voltage, + input current, and OTG current. + + The driver can also be built as a module. If so, the module will be + called qcom-tadc. + config ROCKCHIP_SARADC tristate "Rockchip SARADC driver" depends on ARCH_ROCKCHIP || (ARM && COMPILE_TEST) diff -ruw linux-4.4.115/drivers/iio/adc/Makefile linux-4.4.115-fbx/drivers/iio/adc/Makefile --- linux-4.4.115/drivers/iio/adc/Makefile 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/iio/adc/Makefile 2019-01-22 16:16:23.875249775 +0100 @@ -29,6 +29,8 @@ obj-$(CONFIG_NAU7802) += nau7802.o obj-$(CONFIG_QCOM_SPMI_IADC) += qcom-spmi-iadc.o obj-$(CONFIG_QCOM_SPMI_VADC) += qcom-spmi-vadc.o +obj-$(CONFIG_QCOM_RRADC) += qcom-rradc.o +obj-$(CONFIG_QCOM_TADC) += qcom-tadc.o obj-$(CONFIG_ROCKCHIP_SARADC) += rockchip_saradc.o obj-$(CONFIG_TI_ADC081C) += ti-adc081c.o obj-$(CONFIG_TI_ADC128S052) += ti-adc128s052.o diff -ruw linux-4.4.115/drivers/iio/inkern.c linux-4.4.115-fbx/drivers/iio/inkern.c --- linux-4.4.115/drivers/iio/inkern.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/iio/inkern.c 2019-01-22 16:16:23.891249920 +0100 @@ -664,3 +664,21 @@ return ret; } EXPORT_SYMBOL_GPL(iio_write_channel_raw); + +int iio_write_channel_processed(struct iio_channel *chan, int val) +{ + int ret; + + mutex_lock(&chan->indio_dev->info_exist_lock); + if (chan->indio_dev->info == NULL) { + ret = -ENODEV; + goto err_unlock; + } + + ret = iio_channel_write(chan, val, 0, IIO_CHAN_INFO_PROCESSED); +err_unlock: + mutex_unlock(&chan->indio_dev->info_exist_lock); + + return ret; +} +EXPORT_SYMBOL_GPL(iio_write_channel_processed); diff -ruw linux-4.4.115/drivers/input/input.c linux-4.4.115-fbx/drivers/input/input.c --- linux-4.4.115/drivers/input/input.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/input/input.c 2019-01-22 16:16:23.975250681 +0100 @@ -1667,8 +1667,14 @@ mutex_lock(&dev->mutex); spin_lock_irqsave(&dev->event_lock, flags); + /* + * Keys that have been pressed at suspend time are unlikely + * to be still pressed when we resume. + */ + if (!test_bit(INPUT_PROP_NO_DUMMY_RELEASE, dev->propbit)) { input_dev_toggle(dev, true); input_dev_release_keys(dev); + } spin_unlock_irqrestore(&dev->event_lock, flags); mutex_unlock(&dev->mutex); diff -ruw linux-4.4.115/drivers/input/Kconfig linux-4.4.115-fbx/drivers/input/Kconfig --- linux-4.4.115/drivers/input/Kconfig 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/input/Kconfig 2019-01-22 16:16:23.971250645 +0100 @@ -187,6 +187,19 @@ To compile this driver as a module, choose M here: the module will be called apm-power. +config INPUT_KEYRESET + bool "Reset key" + depends on INPUT + select INPUT_KEYCOMBO + ---help--- + Say Y here if you want to reboot when some keys are pressed; + +config INPUT_KEYCOMBO + bool "Key combo" + depends on INPUT + ---help--- + Say Y here if you want to take action when some keys are pressed; + comment "Input Device Drivers" source "drivers/input/keyboard/Kconfig" diff -ruw linux-4.4.115/drivers/input/Makefile linux-4.4.115-fbx/drivers/input/Makefile --- linux-4.4.115/drivers/input/Makefile 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/input/Makefile 2019-01-22 16:16:23.971250645 +0100 @@ -26,3 +26,6 @@ obj-$(CONFIG_INPUT_MISC) += misc/ obj-$(CONFIG_INPUT_APMPOWER) += apm-power.o +obj-$(CONFIG_INPUT_KEYRESET) += keyreset.o +obj-$(CONFIG_INPUT_KEYCOMBO) += keycombo.o + diff -ruw linux-4.4.115/drivers/input/misc/Kconfig linux-4.4.115-fbx/drivers/input/misc/Kconfig --- linux-4.4.115/drivers/input/misc/Kconfig 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/input/misc/Kconfig 2019-01-22 16:16:23.991250826 +0100 @@ -103,6 +103,17 @@ To compile this driver as a module, choose M here: the module will be called e3x0_button. +config INPUT_HBTP_INPUT + tristate "HBTP input driver support" + help + This option enables an input driver for the host based touch + processing. + + Say Y to enable HBTP input driver. + + To compile this driver as a module, choose M here: the + module will be called hbtp_input. + config INPUT_PCSPKR tristate "PC Speaker support" depends on PCSPKR_PLATFORM @@ -150,6 +161,15 @@ To compile this driver as a module, choose M here: the module will be called pmic8xxx-pwrkey. +config INPUT_QPNP_POWER_ON + tristate "QPNP PMIC Power-on support" + depends on SPMI + help + This option enables device driver support for the power-on + functionality of Qualcomm Technologies, Inc. PNP PMICs. It supports + reporting the change in status of the KPDPWR_N line (connected to the + power-key) as well as reset features. + config INPUT_SPARCSPKR tristate "SPARC Speaker support" depends on PCI && SPARC64 @@ -341,6 +361,17 @@ To compile this driver as a module, choose M here: the module will be called ati_remote2. +config INPUT_KEYCHORD + tristate "Key chord input driver support" + help + Say Y here if you want to enable the key chord driver + accessible at /dev/keychord. This driver can be used + for receiving notifications when client specified key + combinations are pressed. + + To compile this driver as a module, choose M here: the + module will be called keychord. + config INPUT_KEYSPAN_REMOTE tristate "Keyspan DMR USB remote control" depends on USB_ARCH_HAS_HCD @@ -509,6 +540,11 @@ To compile this driver as a module, choose M here: the module will be called sgi_btns. +config INPUT_GPIO + tristate "GPIO driver support" + help + Say Y here if you want to support gpio based keys, wheels etc... + config HP_SDC_RTC tristate "HP SDC Real Time Clock" depends on (GSC || HP300) && SERIO @@ -796,4 +832,16 @@ To compile this driver as a module, choose M here: the module will be called drv2667-haptics. +source "drivers/input/misc/ots_pat9125/Kconfig" + +config INPUT_STMVL53L0 + tristate "STM VL53L0 Proximity support" + depends on INPUT && I2C + help + Say Y here if you want to use STMicroelectronics's proximity sensor + through I2C interface. + + To compile this driver as a module, choose M here: the + module will be called stmvl53l0. + endif diff -ruw linux-4.4.115/drivers/input/misc/Makefile linux-4.4.115-fbx/drivers/input/misc/Makefile --- linux-4.4.115/drivers/input/misc/Makefile 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/input/misc/Makefile 2019-01-22 16:16:23.991250826 +0100 @@ -34,9 +34,12 @@ obj-$(CONFIG_INPUT_GP2A) += gp2ap002a00f.o obj-$(CONFIG_INPUT_GPIO_BEEPER) += gpio-beeper.o obj-$(CONFIG_INPUT_GPIO_TILT_POLLED) += gpio_tilt_polled.o +obj-$(CONFIG_INPUT_GPIO) += gpio_event.o gpio_matrix.o gpio_input.o gpio_output.o gpio_axis.o +obj-$(CONFIG_INPUT_HBTP_INPUT) += hbtp_input.o hbtp_vm.o obj-$(CONFIG_HP_SDC_RTC) += hp_sdc_rtc.o obj-$(CONFIG_INPUT_IMS_PCU) += ims-pcu.o obj-$(CONFIG_INPUT_IXP4XX_BEEPER) += ixp4xx-beeper.o +obj-$(CONFIG_INPUT_KEYCHORD) += keychord.o obj-$(CONFIG_INPUT_KEYSPAN_REMOTE) += keyspan_remote.o obj-$(CONFIG_INPUT_KXTJ9) += kxtj9.o obj-$(CONFIG_INPUT_M68K_BEEP) += m68kspkr.o @@ -54,6 +57,7 @@ obj-$(CONFIG_INPUT_PM8941_PWRKEY) += pm8941-pwrkey.o obj-$(CONFIG_INPUT_PM8XXX_VIBRATOR) += pm8xxx-vibrator.o obj-$(CONFIG_INPUT_PMIC8XXX_PWRKEY) += pmic8xxx-pwrkey.o +obj-$(CONFIG_INPUT_QPNP_POWER_ON) += qpnp-power-on.o obj-$(CONFIG_INPUT_POWERMATE) += powermate.o obj-$(CONFIG_INPUT_PWM_BEEPER) += pwm-beeper.o obj-$(CONFIG_INPUT_RB532_BUTTON) += rb532_button.o @@ -75,3 +79,5 @@ obj-$(CONFIG_INPUT_XEN_KBDDEV_FRONTEND) += xen-kbdfront.o obj-$(CONFIG_INPUT_YEALINK) += yealink.o obj-$(CONFIG_INPUT_IDEAPAD_SLIDEBAR) += ideapad_slidebar.o +obj-$(CONFIG_INPUT_PIXART_OTS_PAT9125_SWITCH) += ots_pat9125/ +obj-$(CONFIG_INPUT_STMVL53L0) += vl53L0/ diff -ruw linux-4.4.115/drivers/input/touchscreen/Kconfig linux-4.4.115-fbx/drivers/input/touchscreen/Kconfig --- linux-4.4.115/drivers/input/touchscreen/Kconfig 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/input/touchscreen/Kconfig 2019-01-22 16:16:24.027251152 +0100 @@ -11,7 +11,9 @@ if INPUT_TOUCHSCREEN -config TOUCHSCREEN_PROPERTIES +source "drivers/input/touchscreen/synaptics_dsx/Kconfig" + +config OF_TOUCHSCREEN def_tristate INPUT depends on INPUT @@ -115,6 +117,18 @@ To compile this driver as a module, choose M here: the module will be called atmel_mxt_ts. +config TOUCHSCREEN_ATMEL_MAXTOUCH_TS + tristate "Atmel Maxtouch Touchscreen Family" + depends on I2C + help + Say Y here if you have Atmel MaXTouch Touchscreen + using i2c connected to your system. + + If unsure, say N. + + To compile this driver as a module, choose M here: the + module will be called atmel_maxtouch_ts. + config TOUCHSCREEN_AUO_PIXCIR tristate "AUO in-cell touchscreen using Pixcir ICs" depends on I2C @@ -1095,6 +1109,34 @@ To compile this driver as a module, choose M here: the module will be called colibri_vf50_ts. +config TOUCHSCREEN_FT5X06_PSENSOR + tristate "FocalTech proximity feature support" + depends on TOUCHSCREEN_FT5X06 && SENSORS + help + Say Y here if you want to support ft5x06's proximity + feature. + + If unsure, say N. + +config TOUCHSCREEN_FT5X06_GESTURE + tristate "FocalTech gesture feature support" + depends on TOUCHSCREEN_FT5X06 + help + Say Y here if you want to support ft5x06's gesture + feature. + + If unsure, say N. + +config TOUCHSCREEN_SYNAPTICS_DSX_FW_UPDATE_EXTRA_SYSFS + bool "Synaptics DSX firmware update extra sysfs attributes" + depends on TOUCHSCREEN_SYNAPTICS_DSX_FW_UPDATE + help + Say Y here to enable support for extra sysfs attributes + supporting firmware update in a development environment. + This does not affect the core or other subsystem attributes. + + If unsure, say N. + config TOUCHSCREEN_ROHM_BU21023 tristate "ROHM BU21023/24 Dual touch support resistive touchscreens" depends on I2C @@ -1106,4 +1148,81 @@ To compile this driver as a module, choose M here: the module will be called bu21023_ts. +config TOUCHSCREEN_MAXIM_STI + tristate "Maxim based STI touchscreens" + depends on SPI_MASTER + help + Say Y here if you have a touchscreen interface using the + Maxim STI based touch controller. + + If unsure, say N + + To compile this driver as a module, choose M here: the + module will be called maxim_sti. + +config SECURE_TOUCH + bool "Secure Touch" + depends on (TOUCHSCREEN_SYNAPTICS_I2C_RMI4 || \ + TOUCHSCREEN_SYNAPTICS_DSX_I2C_v21) + help + Say Y here to enable Secure Touch in supported drivers. + + If unsure, say N. + +config TOUCHSCREEN_GEN_VKEYS + tristate "Touchscreen Virtual Keys Driver" + help + Say Y here if you want to generate a sysfs entry for virtual + keys on Android. + + If unsure, say N. + + To compile this driver as a module, choose M here: the + module will be called gen_vkeys. + +config TOUCHSCREEN_FT5X06 + tristate "FocalTech touchscreens" + depends on I2C + help + Say Y here if you have a ft5X06 touchscreen. + Ft5x06 controllers are multi touch controllers which can + report 5 touches at a time. + + If unsure, say N. + + To compile this driver as a module, choose M here: the + module will be called ft5x06_ts. + +config FT_SECURE_TOUCH + bool "Secure Touch support for Focaltech Touchscreen" + depends on TOUCHSCREEN_FT5X06 + help + Say Y here + -Focaltech touch driver is connected + -To enable secure touch for Focaltech touch driver + + If unsure, say N. + +config TOUCHSCREEN_IT7260_I2C + tristate "IT7260 Touchscreen Driver" + depends on I2C + help + Say Y here if you have a IT7260 Touchscreen Driver + connected to your system. + + If unsure, say N. + + To compile this driver as a module, choose M here: the + module will be called it7258_ts_i2c. + +config TOUCHSCREEN_ST + bool "STMicroelectronics Touchscreen Driver" + depends on I2C + help + Say Y here if you have a STMicroelectronics Touchscreen. + + If unsure, say N. + +source "drivers/input/touchscreen/st/Kconfig" + endif diff -ruw linux-4.4.115/drivers/input/touchscreen/Makefile linux-4.4.115-fbx/drivers/input/touchscreen/Makefile --- linux-4.4.115/drivers/input/touchscreen/Makefile 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/input/touchscreen/Makefile 2019-01-22 16:16:24.027251152 +0100 @@ -15,6 +15,7 @@ obj-$(CONFIG_TOUCHSCREEN_ADS7846) += ads7846.o obj-$(CONFIG_TOUCHSCREEN_AR1021_I2C) += ar1021_i2c.o obj-$(CONFIG_TOUCHSCREEN_ATMEL_MXT) += atmel_mxt_ts.o +obj-$(CONFIG_TOUCHSCREEN_ATMEL_MAXTOUCH_TS) += atmel_maxtouch_ts.o obj-$(CONFIG_TOUCHSCREEN_AUO_PIXCIR) += auo-pixcir-ts.o obj-$(CONFIG_TOUCHSCREEN_BU21013) += bu21013_ts.o obj-$(CONFIG_TOUCHSCREEN_CHIPONE_ICN8318) += chipone_icn8318.o @@ -36,15 +37,19 @@ obj-$(CONFIG_TOUCHSCREEN_ELO) += elo.o obj-$(CONFIG_TOUCHSCREEN_EGALAX) += egalax_ts.o obj-$(CONFIG_TOUCHSCREEN_FT6236) += ft6236.o +obj-$(CONFIG_TOUCHSCREEN_FT5X06) += ft5x06_ts.o obj-$(CONFIG_TOUCHSCREEN_FUJITSU) += fujitsu_ts.o obj-$(CONFIG_TOUCHSCREEN_GOODIX) += goodix.o +obj-$(CONFIG_TOUCHSCREEN_GEN_VKEYS) += gen_vkeys.o obj-$(CONFIG_TOUCHSCREEN_ILI210X) += ili210x.o obj-$(CONFIG_TOUCHSCREEN_IMX6UL_TSC) += imx6ul_tsc.o obj-$(CONFIG_TOUCHSCREEN_INEXIO) += inexio.o obj-$(CONFIG_TOUCHSCREEN_INTEL_MID) += intel-mid-touch.o +obj-$(CONFIG_TOUCHSCREEN_IT7260_I2C) += it7258_ts_i2c.o obj-$(CONFIG_TOUCHSCREEN_IPROC) += bcm_iproc_tsc.o obj-$(CONFIG_TOUCHSCREEN_LPC32XX) += lpc32xx_ts.o obj-$(CONFIG_TOUCHSCREEN_MAX11801) += max11801_ts.o +obj-$(CONFIG_TOUCHSCREEN_MAXIM_STI) += maxim_sti.o obj-$(CONFIG_TOUCHSCREEN_MC13783) += mc13783_ts.o obj-$(CONFIG_TOUCHSCREEN_MCS5000) += mcs5000_ts.o obj-$(CONFIG_TOUCHSCREEN_MIGOR) += migor_ts.o @@ -64,6 +69,7 @@ obj-$(CONFIG_TOUCHSCREEN_STMPE) += stmpe-ts.o obj-$(CONFIG_TOUCHSCREEN_SUN4I) += sun4i-ts.o obj-$(CONFIG_TOUCHSCREEN_SUR40) += sur40.o +obj-$(CONFIG_TOUCHSCREEN_SYNAPTICS_DSX_v21) += synaptics_dsx/ obj-$(CONFIG_TOUCHSCREEN_TI_AM335X_TSC) += ti_am335x_tsc.o obj-$(CONFIG_TOUCHSCREEN_TOUCHIT213) += touchit213.o obj-$(CONFIG_TOUCHSCREEN_TOUCHRIGHT) += touchright.o @@ -91,3 +97,4 @@ obj-$(CONFIG_TOUCHSCREEN_ZFORCE) += zforce_ts.o obj-$(CONFIG_TOUCHSCREEN_COLIBRI_VF50) += colibri-vf50-ts.o obj-$(CONFIG_TOUCHSCREEN_ROHM_BU21023) += rohm_bu21023.o +obj-$(CONFIG_TOUCHSCREEN_ST) += st/ diff -ruw linux-4.4.115/drivers/iommu/arm-smmu.c linux-4.4.115-fbx/drivers/iommu/arm-smmu.c --- linux-4.4.115/drivers/iommu/arm-smmu.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/iommu/arm-smmu.c 2019-10-29 09:26:23.813204842 +0100 @@ -42,13 +42,21 @@ #include #include #include +#include #include +#include +#include +#include +#include +#include +#include +#include #include "io-pgtable.h" /* Maximum number of stream IDs assigned to a single device */ -#define MAX_MASTER_STREAMIDS MAX_PHANDLE_ARGS +#define MAX_MASTER_STREAMIDS 45 /* Maximum number of context banks per SMMU */ #define ARM_SMMU_MAX_CBS 128 @@ -148,7 +156,7 @@ #define ARM_SMMU_GR0_sTLBGSYNC 0x70 #define ARM_SMMU_GR0_sTLBGSTATUS 0x74 #define sTLBGSTATUS_GSACTIVE (1 << 0) -#define TLB_LOOP_TIMEOUT 1000000 /* 1s! */ +#define TLB_LOOP_TIMEOUT 500000 /* 500ms */ /* Stream mapping registers */ #define ARM_SMMU_GR0_SMR(n) (0x800 + ((n) << 2)) @@ -195,29 +203,38 @@ #define ARM_SMMU_CB(smmu, n) ((n) * (1 << (smmu)->pgshift)) #define ARM_SMMU_CB_SCTLR 0x0 +#define ARM_SMMU_CB_ACTLR 0x4 #define ARM_SMMU_CB_RESUME 0x8 #define ARM_SMMU_CB_TTBCR2 0x10 #define ARM_SMMU_CB_TTBR0 0x20 #define ARM_SMMU_CB_TTBR1 0x28 #define ARM_SMMU_CB_TTBCR 0x30 +#define ARM_SMMU_CB_CONTEXTIDR 0x34 #define ARM_SMMU_CB_S1_MAIR0 0x38 #define ARM_SMMU_CB_S1_MAIR1 0x3c #define ARM_SMMU_CB_PAR_LO 0x50 #define ARM_SMMU_CB_PAR_HI 0x54 #define ARM_SMMU_CB_FSR 0x58 +#define ARM_SMMU_CB_FSRRESTORE 0x5c #define ARM_SMMU_CB_FAR_LO 0x60 #define ARM_SMMU_CB_FAR_HI 0x64 #define ARM_SMMU_CB_FSYNR0 0x68 #define ARM_SMMU_CB_S1_TLBIVA 0x600 #define ARM_SMMU_CB_S1_TLBIASID 0x610 +#define ARM_SMMU_CB_S1_TLBIALL 0x618 #define ARM_SMMU_CB_S1_TLBIVAL 0x620 #define ARM_SMMU_CB_S2_TLBIIPAS2 0x630 #define ARM_SMMU_CB_S2_TLBIIPAS2L 0x638 +#define ARM_SMMU_CB_TLBSYNC 0x7f0 +#define ARM_SMMU_CB_TLBSTATUS 0x7f4 +#define TLBSTATUS_SACTIVE (1 << 0) #define ARM_SMMU_CB_ATS1PR 0x800 #define ARM_SMMU_CB_ATSR 0x8f0 +#define ARM_SMMU_GR1_CBFRSYNRA(n) (0x400 + ((n) << 2)) #define SCTLR_S1_ASIDPNE (1 << 12) #define SCTLR_CFCFG (1 << 7) +#define SCTLR_HUPCF (1 << 8) #define SCTLR_CFIE (1 << 6) #define SCTLR_CFRE (1 << 5) #define SCTLR_E (1 << 4) @@ -233,9 +250,6 @@ #define RESUME_RETRY (0 << 0) #define RESUME_TERMINATE (1 << 0) -#define TTBCR2_SEP_SHIFT 15 -#define TTBCR2_SEP_UPSTREAM (0x7 << TTBCR2_SEP_SHIFT) - #define TTBRn_ASID_SHIFT 48 #define FSR_MULTI (1 << 31) @@ -249,6 +263,24 @@ #define FSR_AFF (1 << 2) #define FSR_TF (1 << 1) +/* Definitions for implementation-defined registers */ +#define ACTLR_QCOM_OSH_SHIFT 28 +#define ACTLR_QCOM_OSH 1 + +#define ACTLR_QCOM_ISH_SHIFT 29 +#define ACTLR_QCOM_ISH 1 + +#define ACTLR_QCOM_NSH_SHIFT 30 +#define ACTLR_QCOM_NSH 1 + +#define ARM_SMMU_IMPL_DEF0(smmu) \ + ((smmu)->base + (2 * (1 << (smmu)->pgshift))) +#define ARM_SMMU_IMPL_DEF1(smmu) \ + ((smmu)->base + (6 * (1 << (smmu)->pgshift))) +#define IMPL_DEF1_MICRO_MMU_CTRL 0 +#define MICRO_MMU_CTRL_LOCAL_HALT_REQ (1 << 2) +#define MICRO_MMU_CTRL_IDLE (1 << 3) + #define FSR_IGN (FSR_AFF | FSR_ASF | \ FSR_TLBMCF | FSR_TLBLKF) #define FSR_FAULT (FSR_MULTI | FSR_SS | FSR_UUT | \ @@ -284,11 +316,24 @@ struct arm_smmu_master_cfg cfg; }; +enum smmu_model_id { + SMMU_MODEL_DEFAULT, + SMMU_MODEL_QCOM_V2, +}; + +struct arm_smmu_impl_def_reg { + u32 offset; + u32 value; +}; + struct arm_smmu_device { struct device *dev; + enum smmu_model_id model; + void __iomem *base; unsigned long size; + phys_addr_t phys_addr; unsigned long pgshift; #define ARM_SMMU_FEAT_COHERENT_WALK (1 << 0) @@ -300,6 +345,17 @@ u32 features; #define ARM_SMMU_OPT_SECURE_CFG_ACCESS (1 << 0) +#define ARM_SMMU_OPT_INVALIDATE_ON_MAP (1 << 1) +#define ARM_SMMU_OPT_HALT_AND_TLB_ON_ATOS (1 << 2) +#define ARM_SMMU_OPT_REGISTER_SAVE (1 << 3) +#define ARM_SMMU_OPT_SKIP_INIT (1 << 4) +#define ARM_SMMU_OPT_ERRATA_CTX_FAULT_HANG (1 << 5) +#define ARM_SMMU_OPT_FATAL_ASF (1 << 6) +#define ARM_SMMU_OPT_ERRATA_TZ_ATOS (1 << 7) +#define ARM_SMMU_OPT_NO_SMR_CHECK (1 << 9) +#define ARM_SMMU_OPT_DYNAMIC (1 << 10) +#define ARM_SMMU_OPT_HALT (1 << 11) +#define ARM_SMMU_OPT_STATIC_CB (1 << 12) u32 options; enum arm_smmu_arch_version version; @@ -311,6 +367,8 @@ u32 num_mapping_groups; DECLARE_BITMAP(smr_map, ARM_SMMU_MAX_SMRS); + u32 ubs; + unsigned long va_size; unsigned long ipa_size; unsigned long pa_size; @@ -320,18 +378,57 @@ unsigned int *irqs; struct list_head list; + struct list_head static_cbndx_list; struct rb_root masters; + + int num_clocks; + struct clk **clocks; + + struct regulator *gdsc; + struct notifier_block regulator_nb; + + /* Protects against domains attaching to the same SMMU concurrently */ + struct mutex attach_lock; + unsigned int attach_count; + struct idr asid_idr; + + struct arm_smmu_impl_def_reg *impl_def_attach_registers; + unsigned int num_impl_def_attach_registers; + + spinlock_t atos_lock; + unsigned int clock_refs_count; + spinlock_t clock_refs_lock; + + struct mutex power_lock; + unsigned int power_count; + + u32 bus_client; + struct msm_bus_scale_pdata *bus_pdata; + + enum tz_smmu_device_id sec_id; + int regulator_defer; }; struct arm_smmu_cfg { u8 cbndx; u8 irptndx; u32 cbar; + u32 procid; + u16 asid; + u8 vmid; }; #define INVALID_IRPTNDX 0xff +#define INVALID_CBNDX 0xff +#define INVALID_ASID 0xffff +#define INVALID_VMID 0xff +/* + * In V7L and V8L with TTBCR2.AS == 0, ASID is 8 bits. + * V8L 16 with TTBCR2.AS == 1 (16 bit ASID) isn't supported yet. + */ +#define MAX_ASID 0xff -#define ARM_SMMU_CB_ASID(cfg) ((cfg)->cbndx) -#define ARM_SMMU_CB_VMID(cfg) ((cfg)->cbndx + 1) +#define ARM_SMMU_CB_ASID(cfg) ((cfg)->asid) +#define ARM_SMMU_CB_VMID(cfg) ((cfg)->vmid) enum arm_smmu_domain_stage { ARM_SMMU_DOMAIN_S1 = 0, @@ -339,13 +436,29 @@ ARM_SMMU_DOMAIN_NESTED, }; +struct arm_smmu_pte_info { + void *virt_addr; + size_t size; + struct list_head entry; +}; + struct arm_smmu_domain { struct arm_smmu_device *smmu; struct io_pgtable_ops *pgtbl_ops; - spinlock_t pgtbl_lock; + struct io_pgtable_cfg pgtbl_cfg; + spinlock_t pgtbl_spin_lock; + struct mutex pgtbl_mutex_lock; struct arm_smmu_cfg cfg; enum arm_smmu_domain_stage stage; struct mutex init_mutex; /* Protects smmu pointer */ + u32 attributes; + bool slave_side_secure; + u32 secure_vmid; + struct list_head pte_info_list; + struct list_head unassign_list; + struct mutex assign_lock; + struct list_head secure_pool_list; + bool non_fatal_faults; struct iommu_domain domain; }; @@ -361,9 +474,75 @@ static struct arm_smmu_option_prop arm_smmu_options[] = { { ARM_SMMU_OPT_SECURE_CFG_ACCESS, "calxeda,smmu-secure-config-access" }, + { ARM_SMMU_OPT_INVALIDATE_ON_MAP, "qcom,smmu-invalidate-on-map" }, + { ARM_SMMU_OPT_HALT_AND_TLB_ON_ATOS, "qcom,halt-and-tlb-on-atos" }, + { ARM_SMMU_OPT_REGISTER_SAVE, "qcom,register-save" }, + { ARM_SMMU_OPT_SKIP_INIT, "qcom,skip-init" }, + { ARM_SMMU_OPT_ERRATA_CTX_FAULT_HANG, "qcom,errata-ctx-fault-hang" }, + { ARM_SMMU_OPT_FATAL_ASF, "qcom,fatal-asf" }, + { ARM_SMMU_OPT_ERRATA_TZ_ATOS, "qcom,errata-tz-atos" }, + { ARM_SMMU_OPT_NO_SMR_CHECK, "qcom,no-smr-check" }, + { ARM_SMMU_OPT_DYNAMIC, "qcom,dynamic" }, + { ARM_SMMU_OPT_HALT, "qcom,enable-smmu-halt"}, + { ARM_SMMU_OPT_STATIC_CB, "qcom,enable-static-cb"}, { 0, NULL}, }; +#define TYPE_TRANS (S2CR_TYPE_TRANS >> S2CR_TYPE_SHIFT) +#define TYPE_BYPASS (S2CR_TYPE_BYPASS >> S2CR_TYPE_SHIFT) +#define TYPE_FAULT (S2CR_TYPE_FAULT >> S2CR_TYPE_SHIFT) + +struct static_cbndx_entry { + struct list_head list; + u8 cbndx; + u8 smr_idx; + u16 sid; + u8 type; +}; + +struct arm_iommus_node { + struct device_node *master; + struct list_head list; + struct list_head iommuspec_list; +}; + +struct arm_iommus_spec { + struct of_phandle_args iommu_spec; + struct list_head list; +}; + +static LIST_HEAD(iommus_nodes); + +static int arm_smmu_enable_clocks_atomic(struct arm_smmu_device *smmu); +static void arm_smmu_disable_clocks_atomic(struct arm_smmu_device *smmu); +static void arm_smmu_prepare_pgtable(void *addr, void *cookie); +static void arm_smmu_unprepare_pgtable(void *cookie, void *addr, size_t size); +static phys_addr_t arm_smmu_iova_to_phys_hard(struct iommu_domain *domain, + dma_addr_t iova); +static phys_addr_t arm_smmu_iova_to_phys_hard_no_halt( + struct iommu_domain *domain, dma_addr_t iova); +static int arm_smmu_wait_for_halt(struct arm_smmu_device *smmu); +static int arm_smmu_halt_nowait(struct arm_smmu_device *smmu); +static void arm_smmu_resume(struct arm_smmu_device *smmu); +static phys_addr_t arm_smmu_iova_to_phys(struct iommu_domain *domain, + dma_addr_t iova); +static int arm_smmu_assign_table(struct arm_smmu_domain *smmu_domain); +static void arm_smmu_unassign_table(struct arm_smmu_domain *smmu_domain); +static int arm_smmu_halt(struct arm_smmu_device *smmu); +static void arm_smmu_device_reset(struct arm_smmu_device *smmu); +static size_t arm_smmu_unmap(struct iommu_domain *domain, unsigned long iova, + size_t size); +static bool arm_smmu_is_master_side_secure(struct arm_smmu_domain *smmu_domain); +static bool arm_smmu_is_static_cb(struct arm_smmu_device *smmu); +static bool arm_smmu_is_slave_side_secure(struct arm_smmu_domain *smmu_domain); +static bool arm_smmu_has_secure_vmid(struct arm_smmu_domain *smmu_domain); +static bool arm_smmu_is_iova_coherent(struct iommu_domain *domain, + dma_addr_t iova); +static uint64_t arm_smmu_iova_to_pte(struct iommu_domain *domain, + dma_addr_t iova); + +static int arm_smmu_enable_s1_translations(struct arm_smmu_domain *smmu_domain); + static struct arm_smmu_domain *to_smmu_domain(struct iommu_domain *dom) { return container_of(dom, struct arm_smmu_domain, domain); @@ -377,7 +556,7 @@ if (of_property_read_bool(smmu->dev->of_node, arm_smmu_options[i].prop)) { smmu->options |= arm_smmu_options[i].opt; - dev_notice(smmu->dev, "option %s\n", + dev_dbg(smmu->dev, "option %s\n", arm_smmu_options[i].prop); } } while (arm_smmu_options[++i].opt); @@ -417,6 +596,28 @@ return NULL; } +static struct arm_smmu_master *find_smmu_master_by_sid( + struct arm_smmu_device *smmu, u32 sid) +{ + struct rb_node *next; + struct arm_smmu_master *master; + struct arm_smmu_master_cfg *cfg; + int i; + + next = rb_first(&smmu->masters); + for (; next; next = rb_next(next)) { + master = container_of(next, struct arm_smmu_master, node); + cfg = &master->cfg; + + for (i = 0; i < cfg->num_streamids; i++) { + if (cfg->streamids[i] == sid) + return master; + } + } + + return NULL; +} + static struct arm_smmu_master_cfg * find_smmu_master_cfg(struct device *dev) { @@ -456,25 +657,32 @@ return 0; } +struct iommus_entry { + struct list_head list; + struct device_node *node; + u16 streamids[MAX_MASTER_STREAMIDS]; + int num_sids; +}; + static int register_smmu_master(struct arm_smmu_device *smmu, - struct device *dev, - struct of_phandle_args *masterspec) + struct iommus_entry *entry) { int i; struct arm_smmu_master *master; + struct device *dev = smmu->dev; - master = find_smmu_master(smmu, masterspec->np); + master = find_smmu_master(smmu, entry->node); if (master) { dev_err(dev, "rejecting multiple registrations for master device %s\n", - masterspec->np->name); + entry->node->name); return -EBUSY; } - if (masterspec->args_count > MAX_MASTER_STREAMIDS) { + if (entry->num_sids > MAX_MASTER_STREAMIDS) { dev_err(dev, "reached maximum number (%d) of stream IDs for master device %s\n", - MAX_MASTER_STREAMIDS, masterspec->np->name); + MAX_MASTER_STREAMIDS, entry->node->name); return -ENOSPC; } @@ -482,22 +690,84 @@ if (!master) return -ENOMEM; - master->of_node = masterspec->np; - master->cfg.num_streamids = masterspec->args_count; + master->of_node = entry->node; + master->cfg.num_streamids = entry->num_sids; - for (i = 0; i < master->cfg.num_streamids; ++i) { - u16 streamid = masterspec->args[i]; + for (i = 0; i < master->cfg.num_streamids; ++i) + master->cfg.streamids[i] = entry->streamids[i]; - if (!(smmu->features & ARM_SMMU_FEAT_STREAM_MATCH) && - (streamid >= smmu->num_mapping_groups)) { - dev_err(dev, - "stream ID for master device %s greater than maximum allowed (%d)\n", - masterspec->np->name, smmu->num_mapping_groups); - return -ERANGE; + return insert_smmu_master(smmu, master); } - master->cfg.streamids[i] = streamid; + +static int arm_smmu_parse_iommus_properties(struct arm_smmu_device *smmu) +{ + struct arm_iommus_node *node, *nex; + + list_for_each_entry_safe(node, nex, &iommus_nodes, list) { + struct iommus_entry *entry, *next; + struct arm_iommus_spec *iommuspec_node, *n; + LIST_HEAD(iommus); + int node_found = 0; + + list_for_each_entry_safe(iommuspec_node, n, + &node->iommuspec_list, list) { + if (iommuspec_node->iommu_spec.np != smmu->dev->of_node) + continue; + + /* + * Since each master node will have iommu spec(s) of the + * same device, we can delete this master node after + * the devices are registered. + */ + node_found = 1; + + list_for_each_entry(entry, &iommus, list) + if (entry->node == node->master) + break; + if (&entry->list == &iommus) { + entry = devm_kzalloc(smmu->dev, sizeof(*entry), + GFP_KERNEL); + if (!entry) + return -ENOMEM; + entry->node = node->master; + list_add(&entry->list, &iommus); } - return insert_smmu_master(smmu, master); + switch (iommuspec_node->iommu_spec.args_count) { + case 0: + /* + * For pci-e devices the SIDs are provided + * at device attach time. + */ + break; + case 1: + entry->num_sids++; + entry->streamids[entry->num_sids - 1] + = iommuspec_node->iommu_spec.args[0]; + break; + default: + BUG(); + } + list_del(&iommuspec_node->list); + kfree(iommuspec_node); + } + + list_for_each_entry_safe(entry, next, &iommus, list) { + int rc = register_smmu_master(smmu, entry); + + if (rc) + dev_err(smmu->dev, "Couldn't register %s\n", + entry->node->name); + list_del(&entry->list); + devm_kfree(smmu->dev, entry); + } + + if (node_found) { + list_del(&node->list); + kfree(node); + } + } + + return 0; } static struct arm_smmu_device *find_smmu_for_device(struct device *dev) @@ -530,11 +800,272 @@ return idx; } +static int __arm_smmu_set_bitmap(unsigned long *map, int idx) +{ + return test_and_set_bit(idx, map); +} + +static struct static_cbndx_entry *arm_smmu_get_static_entry_from_sid( + struct arm_smmu_device *smmu, int sid) +{ + struct static_cbndx_entry *entry; + + list_for_each_entry(entry, &smmu->static_cbndx_list, list) { + if (entry->sid == sid) + return entry; + } + + return NULL; +} + +static struct static_cbndx_entry *arm_smmu_get_static_entry_from_context( + struct arm_smmu_device *smmu, int idx) +{ + struct static_cbndx_entry *entry; + + list_for_each_entry(entry, &smmu->static_cbndx_list, list) { + if (entry->type == TYPE_TRANS && entry->cbndx == idx) + return entry; + } + + return NULL; +} + +static struct static_cbndx_entry *arm_smmu_get_static_entry_from_smr( + struct arm_smmu_device *smmu, int idx) +{ + struct static_cbndx_entry *entry; + + list_for_each_entry(entry, &smmu->static_cbndx_list, list) { + if (entry->smr_idx == idx) + return entry; + } + + return NULL; +} + +static int arm_smmu_alloc_smr_idx(struct arm_smmu_device *smmu, int start, + int end, int sid) +{ + struct static_cbndx_entry *entry = arm_smmu_get_static_entry_from_sid( + smmu, sid); + + if (entry) + return entry->smr_idx; + else + return __arm_smmu_alloc_bitmap(smmu->smr_map, start, end); +} + +static int arm_smmu_alloc_context_idx(struct arm_smmu_device *smmu, int start, + int end, u16 *streamids, int num_streamids) +{ + struct static_cbndx_entry *entry = NULL; + int i; + + for (i = 0; i < num_streamids; ++i) { + entry = arm_smmu_get_static_entry_from_sid(smmu, streamids[i]); + if (entry && entry->type == TYPE_TRANS) + break; + } + + if (entry && entry->type == TYPE_TRANS) + return entry->cbndx; + else + return __arm_smmu_alloc_bitmap(smmu->context_map, start, end); +} + static void __arm_smmu_free_bitmap(unsigned long *map, int idx) { clear_bit(idx, map); } +static void arm_smmu_free_smr_idx(struct arm_smmu_device *smmu, int idx) +{ + struct static_cbndx_entry *entry = arm_smmu_get_static_entry_from_smr( + smmu, idx); + + if (!entry) + __arm_smmu_free_bitmap(smmu->smr_map, idx); +} + +static void arm_smmu_free_context_idx(struct arm_smmu_device *smmu, int idx) +{ + struct static_cbndx_entry *entry = + arm_smmu_get_static_entry_from_context(smmu, idx); + + if (!entry) + __arm_smmu_free_bitmap(smmu->context_map, idx); +} + +static void arm_smmu_unprepare_clocks(struct arm_smmu_device *smmu) +{ + int i; + + for (i = smmu->num_clocks; i; --i) + clk_unprepare(smmu->clocks[i - 1]); +} + +static int arm_smmu_prepare_clocks(struct arm_smmu_device *smmu) +{ + int i, ret = 0; + + for (i = 0; i < smmu->num_clocks; ++i) { + ret = clk_prepare(smmu->clocks[i]); + if (ret) { + dev_err(smmu->dev, "Couldn't prepare clock #%d\n", i); + while (i--) + clk_unprepare(smmu->clocks[i]); + break; + } + } + return ret; +} + +static int arm_smmu_request_bus(struct arm_smmu_device *smmu) +{ + if (!smmu->bus_client) + return 0; + return msm_bus_scale_client_update_request(smmu->bus_client, 1); +} + +static int arm_smmu_unrequest_bus(struct arm_smmu_device *smmu) +{ + if (!smmu->bus_client) + return 0; + return msm_bus_scale_client_update_request(smmu->bus_client, 0); +} + +static int arm_smmu_disable_regulators(struct arm_smmu_device *smmu) +{ + int ret = 0; + + mutex_lock(&smmu->power_lock); + if (smmu->power_count == 0) { + WARN(1, "%s: Mismatched power count\n", dev_name(smmu->dev)); + mutex_unlock(&smmu->power_lock); + return -EINVAL; + } else if (smmu->power_count > 1) { + smmu->power_count -= 1; + mutex_unlock(&smmu->power_lock); + return 0; + } + + arm_smmu_unprepare_clocks(smmu); + arm_smmu_unrequest_bus(smmu); + if (smmu->gdsc) { + ret = regulator_disable_deferred(smmu->gdsc, + smmu->regulator_defer); + WARN(ret, "%s: Regulator disable failed\n", + dev_name(smmu->dev)); + } + + smmu->power_count = 0; + mutex_unlock(&smmu->power_lock); + return ret; +} + +static int arm_smmu_enable_regulators(struct arm_smmu_device *smmu) +{ + int ret; + + mutex_lock(&smmu->power_lock); + if (smmu->power_count) { + smmu->power_count++; + mutex_unlock(&smmu->power_lock); + return 0; + } + + if (smmu->gdsc) { + ret = regulator_enable(smmu->gdsc); + if (WARN_ON_ONCE(ret)) + goto out; + } + + ret = arm_smmu_request_bus(smmu); + if (WARN_ON_ONCE(ret)) + goto out_reg; + + ret = arm_smmu_prepare_clocks(smmu); + if (WARN_ON_ONCE(ret)) + goto out_bus; + + smmu->power_count = 1; + mutex_unlock(&smmu->power_lock); + return ret; + +out_bus: + arm_smmu_unrequest_bus(smmu); +out_reg: + if (smmu->gdsc) + regulator_disable(smmu->gdsc); +out: + mutex_unlock(&smmu->power_lock); + return ret; +} + +static int arm_smmu_enable_clocks(struct arm_smmu_device *smmu) +{ + int ret = 0; + + ret = arm_smmu_enable_regulators(smmu); + if (unlikely(ret)) + return ret; + ret = arm_smmu_enable_clocks_atomic(smmu); + if (unlikely(ret)) + arm_smmu_disable_regulators(smmu); + + return ret; +} + +static void arm_smmu_disable_clocks(struct arm_smmu_device *smmu) +{ + arm_smmu_disable_clocks_atomic(smmu); + arm_smmu_disable_regulators(smmu); +} + +/* Clocks must be prepared before this (arm_smmu_prepare_clocks) */ +static int arm_smmu_enable_clocks_atomic(struct arm_smmu_device *smmu) +{ + int i, ret = 0; + unsigned long flags; + + spin_lock_irqsave(&smmu->clock_refs_lock, flags); + if (smmu->clock_refs_count++ > 0) { + spin_unlock_irqrestore(&smmu->clock_refs_lock, flags); + return 0; + } + + for (i = 0; i < smmu->num_clocks; ++i) { + ret = clk_enable(smmu->clocks[i]); + if (WARN_ON_ONCE(ret)) { + dev_err(smmu->dev, "Couldn't enable clock #%d\n", i); + while (i--) + clk_disable(smmu->clocks[i]); + smmu->clock_refs_count--; + break; + } + } + spin_unlock_irqrestore(&smmu->clock_refs_lock, flags); + return ret; +} + +/* Clocks should be unprepared after this (arm_smmu_unprepare_clocks) */ +static void arm_smmu_disable_clocks_atomic(struct arm_smmu_device *smmu) +{ + int i; + unsigned long flags; + + spin_lock_irqsave(&smmu->clock_refs_lock, flags); + if (smmu->clock_refs_count-- > 1) { + spin_unlock_irqrestore(&smmu->clock_refs_lock, flags); + return; + } + + for (i = smmu->num_clocks; i; --i) + clk_disable(smmu->clocks[i - 1]); + spin_unlock_irqrestore(&smmu->clock_refs_lock, flags); +} + /* Wait for any pending TLB invalidations to complete */ static void __arm_smmu_tlb_sync(struct arm_smmu_device *smmu) { @@ -554,12 +1085,30 @@ } } +static void arm_smmu_tlb_sync_cb(struct arm_smmu_device *smmu, + int cbndx) +{ + void __iomem *base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, cbndx); + u32 val; + + writel_relaxed(0, base + ARM_SMMU_CB_TLBSYNC); + if (readl_poll_timeout_atomic(base + ARM_SMMU_CB_TLBSTATUS, val, + !(val & TLBSTATUS_SACTIVE), + 0, TLB_LOOP_TIMEOUT)) + dev_err(smmu->dev, "TLBSYNC timeout!\n"); +} + static void arm_smmu_tlb_sync(void *cookie) { struct arm_smmu_domain *smmu_domain = cookie; - __arm_smmu_tlb_sync(smmu_domain->smmu); + + if (smmu_domain->smmu == NULL) + return; + + arm_smmu_tlb_sync_cb(smmu_domain->smmu, smmu_domain->cfg.cbndx); } +/* Must be called with clocks/regulators enabled */ static void arm_smmu_tlb_inv_context(void *cookie) { struct arm_smmu_domain *smmu_domain = cookie; @@ -568,19 +1117,23 @@ bool stage1 = cfg->cbar != CBAR_TYPE_S2_TRANS; void __iomem *base; + if (!smmu) + return; + if (stage1) { base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, cfg->cbndx); writel_relaxed(ARM_SMMU_CB_ASID(cfg), base + ARM_SMMU_CB_S1_TLBIASID); + arm_smmu_tlb_sync_cb(smmu, cfg->cbndx); } else { base = ARM_SMMU_GR0(smmu); writel_relaxed(ARM_SMMU_CB_VMID(cfg), base + ARM_SMMU_GR0_TLBIVMID); - } - __arm_smmu_tlb_sync(smmu); } +} +/* Must be called with clocks/regulators enabled */ static void arm_smmu_tlb_inv_range_nosync(unsigned long iova, size_t size, bool leaf, void *cookie) { @@ -589,6 +1142,11 @@ struct arm_smmu_device *smmu = smmu_domain->smmu; bool stage1 = cfg->cbar != CBAR_TYPE_S2_TRANS; void __iomem *reg; + int atomic_ctx = smmu_domain->attributes & (1 << DOMAIN_ATTR_ATOMIC); + + BUG_ON(atomic_ctx && !smmu); + if (!smmu) + return; if (stage1) { reg = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, cfg->cbndx); @@ -618,61 +1176,331 @@ } } +static void arm_smmu_tlbi_domain(struct iommu_domain *domain) +{ + arm_smmu_tlb_inv_context(to_smmu_domain(domain)); +} + +static int arm_smmu_enable_config_clocks(struct iommu_domain *domain) +{ + struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain); + + return arm_smmu_enable_clocks(smmu_domain->smmu); +} + +static void arm_smmu_disable_config_clocks(struct iommu_domain *domain) +{ + struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain); + + arm_smmu_disable_clocks(smmu_domain->smmu); +} + +struct arm_smmu_secure_pool_chunk { + void *addr; + size_t size; + struct list_head list; +}; + +static void *arm_smmu_secure_pool_remove(struct arm_smmu_domain *smmu_domain, + size_t size) +{ + struct arm_smmu_secure_pool_chunk *it; + + list_for_each_entry(it, &smmu_domain->secure_pool_list, list) { + if (it->size == size) { + void *addr = it->addr; + + list_del(&it->list); + kfree(it); + return addr; + } + } + + return NULL; +} + +static int arm_smmu_secure_pool_add(struct arm_smmu_domain *smmu_domain, + void *addr, size_t size) +{ + struct arm_smmu_secure_pool_chunk *chunk; + + chunk = kmalloc(sizeof(*chunk), GFP_ATOMIC); + if (!chunk) + return -ENOMEM; + + chunk->addr = addr; + chunk->size = size; + memset(addr, 0, size); + list_add(&chunk->list, &smmu_domain->secure_pool_list); + + return 0; +} + +static void arm_smmu_secure_pool_destroy(struct arm_smmu_domain *smmu_domain) +{ + struct arm_smmu_secure_pool_chunk *it, *i; + + list_for_each_entry_safe(it, i, &smmu_domain->secure_pool_list, list) { + arm_smmu_unprepare_pgtable(smmu_domain, it->addr, it->size); + /* pages will be freed later (after being unassigned) */ + list_del(&it->list); + kfree(it); + } +} + +static void *arm_smmu_alloc_pages_exact(void *cookie, + size_t size, gfp_t gfp_mask) +{ + void *ret; + struct arm_smmu_domain *smmu_domain = cookie; + + if (!arm_smmu_is_master_side_secure(smmu_domain)) + return alloc_pages_exact(size, gfp_mask); + + ret = arm_smmu_secure_pool_remove(smmu_domain, size); + if (ret) + return ret; + + ret = alloc_pages_exact(size, gfp_mask); + if (ret) + arm_smmu_prepare_pgtable(ret, cookie); + + return ret; +} + +static void arm_smmu_free_pages_exact(void *cookie, void *virt, size_t size) +{ + struct arm_smmu_domain *smmu_domain = cookie; + + if (!arm_smmu_is_master_side_secure(smmu_domain)) { + free_pages_exact(virt, size); + return; + } + + if (arm_smmu_secure_pool_add(smmu_domain, virt, size)) + arm_smmu_unprepare_pgtable(smmu_domain, virt, size); +} + static struct iommu_gather_ops arm_smmu_gather_ops = { .tlb_flush_all = arm_smmu_tlb_inv_context, .tlb_add_flush = arm_smmu_tlb_inv_range_nosync, .tlb_sync = arm_smmu_tlb_sync, + .alloc_pages_exact = arm_smmu_alloc_pages_exact, + .free_pages_exact = arm_smmu_free_pages_exact, }; +static phys_addr_t arm_smmu_verify_fault(struct iommu_domain *domain, + dma_addr_t iova, u32 fsr) +{ + struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain); + struct arm_smmu_cfg *cfg = &smmu_domain->cfg; + struct arm_smmu_device *smmu; + void __iomem *cb_base; + u64 sctlr, sctlr_orig; + phys_addr_t phys; + + smmu = smmu_domain->smmu; + cb_base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, cfg->cbndx); + + arm_smmu_halt_nowait(smmu); + + writel_relaxed(RESUME_TERMINATE, cb_base + ARM_SMMU_CB_RESUME); + + arm_smmu_wait_for_halt(smmu); + + /* clear FSR to allow ATOS to log any faults */ + writel_relaxed(fsr, cb_base + ARM_SMMU_CB_FSR); + + /* disable stall mode momentarily */ + sctlr_orig = readl_relaxed(cb_base + ARM_SMMU_CB_SCTLR); + sctlr = sctlr_orig & ~SCTLR_CFCFG; + writel_relaxed(sctlr, cb_base + ARM_SMMU_CB_SCTLR); + + phys = arm_smmu_iova_to_phys_hard_no_halt(domain, iova); + + if (!phys) { + dev_err(smmu->dev, + "ATOS failed. Will issue a TLBIALL and try again...\n"); + arm_smmu_tlb_inv_context(smmu_domain); + phys = arm_smmu_iova_to_phys_hard_no_halt(domain, iova); + if (phys) + dev_err(smmu->dev, + "ATOS succeeded this time. Maybe we missed a TLB invalidation while messing with page tables earlier??\n"); + else + dev_err(smmu->dev, + "ATOS still failed. If the page tables look good (check the software table walk) then hardware might be misbehaving.\n"); + } + + /* restore SCTLR */ + writel_relaxed(sctlr_orig, cb_base + ARM_SMMU_CB_SCTLR); + + arm_smmu_resume(smmu); + + return phys; +} + static irqreturn_t arm_smmu_context_fault(int irq, void *dev) { - int flags, ret; - u32 fsr, far, fsynr, resume; - unsigned long iova; + int flags, ret, tmp; + u32 fsr, fsynr, resume; + unsigned long iova, far; struct iommu_domain *domain = dev; struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain); struct arm_smmu_cfg *cfg = &smmu_domain->cfg; - struct arm_smmu_device *smmu = smmu_domain->smmu; + struct arm_smmu_device *smmu; void __iomem *cb_base; + bool ctx_hang_errata; + bool fatal_asf; + void __iomem *gr1_base; + phys_addr_t phys_soft; + u32 sid; + bool non_fatal_fault = smmu_domain->non_fatal_faults; + struct arm_smmu_master *master; + + static DEFINE_RATELIMIT_STATE(_rs, + DEFAULT_RATELIMIT_INTERVAL, + DEFAULT_RATELIMIT_BURST); + + mutex_lock(&smmu_domain->init_mutex); + smmu = smmu_domain->smmu; + if (!smmu) { + ret = IRQ_HANDLED; + pr_err("took a fault on a detached domain (%p)\n", domain); + goto out_unlock; + } + ctx_hang_errata = smmu->options & ARM_SMMU_OPT_ERRATA_CTX_FAULT_HANG; + fatal_asf = smmu->options & ARM_SMMU_OPT_FATAL_ASF; + + if (arm_smmu_enable_clocks(smmu)) { + ret = IRQ_NONE; + goto out_unlock; + } + gr1_base = ARM_SMMU_GR1(smmu); cb_base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, cfg->cbndx); fsr = readl_relaxed(cb_base + ARM_SMMU_CB_FSR); - if (!(fsr & FSR_FAULT)) - return IRQ_NONE; + if (!(fsr & FSR_FAULT)) { + arm_smmu_disable_clocks(smmu); + ret = IRQ_NONE; + goto out_unlock; + } - if (fsr & FSR_IGN) - dev_err_ratelimited(smmu->dev, - "Unexpected context fault (fsr 0x%x)\n", - fsr); + if (fatal_asf && (fsr & FSR_ASF)) { + dev_err(smmu->dev, + "Took an address size fault. Refusing to recover.\n"); + BUG(); + } fsynr = readl_relaxed(cb_base + ARM_SMMU_CB_FSYNR0); flags = fsynr & FSYNR0_WNR ? IOMMU_FAULT_WRITE : IOMMU_FAULT_READ; + if (fsr & FSR_TF) + flags |= IOMMU_FAULT_TRANSLATION; + if (fsr & FSR_PF) + flags |= IOMMU_FAULT_PERMISSION; + if (fsr & FSR_EF) + flags |= IOMMU_FAULT_EXTERNAL; + if (fsr & FSR_SS) + flags |= IOMMU_FAULT_TRANSACTION_STALLED; far = readl_relaxed(cb_base + ARM_SMMU_CB_FAR_LO); - iova = far; #ifdef CONFIG_64BIT - far = readl_relaxed(cb_base + ARM_SMMU_CB_FAR_HI); - iova |= ((unsigned long)far << 32); + far |= ((u64)readl_relaxed(cb_base + ARM_SMMU_CB_FAR_HI)) << 32; #endif + iova = far; - if (!report_iommu_fault(domain, smmu->dev, iova, flags)) { + phys_soft = arm_smmu_iova_to_phys(domain, iova); + sid = readl_relaxed(gr1_base + ARM_SMMU_GR1_CBFRSYNRA(cfg->cbndx)); + sid &= 0xffff; + master = find_smmu_master_by_sid(smmu, sid); + tmp = report_iommu_fault(domain, smmu->dev, iova, flags); + if (!tmp || (tmp == -EBUSY)) { + dev_dbg(smmu->dev, + "Context fault handled by client: iova=0x%08lx, fsr=0x%x, fsynr=0x%x, cb=%d\n", + iova, fsr, fsynr, cfg->cbndx); + dev_dbg(smmu->dev, + "soft iova-to-phys=%pa\n", &phys_soft); ret = IRQ_HANDLED; - resume = RESUME_RETRY; + resume = RESUME_TERMINATE; } else { - dev_err_ratelimited(smmu->dev, - "Unhandled context fault: iova=0x%08lx, fsynr=0x%x, cb=%d\n", - iova, fsynr, cfg->cbndx); + phys_addr_t phys_atos = arm_smmu_verify_fault(domain, iova, + fsr); + + if (__ratelimit(&_rs)) { + dev_err(smmu->dev, "Context Fault for %s\n", + master ? master->of_node->name : "Unknown SID"); + + dev_err(smmu->dev, + "Unhandled context fault: iova=0x%08lx, fsr=0x%x, fsynr=0x%x, cb=%d\n", + iova, fsr, fsynr, cfg->cbndx); + dev_err(smmu->dev, "FAR = %016lx\n", + (unsigned long)far); + dev_err(smmu->dev, + "FSR = %08x [%s%s%s%s%s%s%s%s%s]\n", + fsr, + (fsr & 0x02) ? "TF " : "", + (fsr & 0x04) ? "AFF " : "", + (fsr & 0x08) ? "PF " : "", + (fsr & 0x10) ? "EF " : "", + (fsr & 0x20) ? "TLBMCF " : "", + (fsr & 0x40) ? "TLBLKF " : "", + (fsr & 0x80) ? "MHF " : "", + (fsr & 0x40000000) ? "SS " : "", + (fsr & 0x80000000) ? "MULTI " : ""); + dev_err(smmu->dev, + "soft iova-to-phys=%pa\n", &phys_soft); + if (!phys_soft) + dev_err(smmu->dev, + "SOFTWARE TABLE WALK FAILED! Looks like %s accessed an unmapped address!\n", + dev_name(smmu->dev)); + dev_err(smmu->dev, + "hard iova-to-phys (ATOS)=%pa\n", &phys_atos); + dev_err(smmu->dev, "SID=0x%x\n", sid); + } ret = IRQ_NONE; resume = RESUME_TERMINATE; + if (!non_fatal_fault) { + dev_err(smmu->dev, + "Unhandled context faults are fatal on this domain. Going down now...\n"); + BUG(); + } } + /* + * If the client returns -EBUSY, do not clear FSR and do not RESUME + * if stalled. This is required to keep the IOMMU client stalled on + * the outstanding fault. This gives the client a chance to take any + * debug action and then terminate the stalled transaction. + * So, the sequence in case of stall on fault should be: + * 1) Do not clear FSR or write to RESUME here + * 2) Client takes any debug action + * 3) Client terminates the stalled transaction and resumes the IOMMU + * 4) Client clears FSR. The FSR should only be cleared after 3) and + * not before so that the fault remains outstanding. This ensures + * SCTLR.HUPCF has the desired effect if subsequent transactions also + * need to be terminated. + */ + if (tmp != -EBUSY) { /* Clear the faulting FSR */ - writel(fsr, cb_base + ARM_SMMU_CB_FSR); + writel_relaxed(fsr, cb_base + ARM_SMMU_CB_FSR); + + /* + * Barrier required to ensure that the FSR is cleared + * before resuming SMMU operation + */ + wmb(); /* Retry or terminate any stalled transactions */ - if (fsr & FSR_SS) + if (fsr & FSR_SS) { + if (ctx_hang_errata) + arm_smmu_tlb_sync_cb(smmu, cfg->cbndx); writel_relaxed(resume, cb_base + ARM_SMMU_CB_RESUME); + } + } + + arm_smmu_disable_clocks(smmu); +out_unlock: + mutex_unlock(&smmu_domain->init_mutex); return ret; } @@ -683,13 +1511,18 @@ struct arm_smmu_device *smmu = dev; void __iomem *gr0_base = ARM_SMMU_GR0_NS(smmu); + if (arm_smmu_enable_clocks(smmu)) + return IRQ_NONE; + gfsr = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSR); gfsynr0 = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSYNR0); gfsynr1 = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSYNR1); gfsynr2 = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSYNR2); - if (!gfsr) + if (!gfsr) { + arm_smmu_disable_clocks(smmu); return IRQ_NONE; + } dev_err_ratelimited(smmu->dev, "Unexpected global fault, this could be serious\n"); @@ -698,9 +1531,36 @@ gfsr, gfsynr0, gfsynr1, gfsynr2); writel(gfsr, gr0_base + ARM_SMMU_GR0_sGFSR); + arm_smmu_disable_clocks(smmu); return IRQ_HANDLED; } +static void arm_smmu_trigger_fault(struct iommu_domain *domain, + unsigned long flags) +{ + struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain); + struct arm_smmu_cfg *cfg = &smmu_domain->cfg; + struct arm_smmu_device *smmu; + void __iomem *cb_base; + + if (!smmu_domain->smmu) { + pr_err("Can't trigger faults on non-attached domains\n"); + return; + } + + smmu = smmu_domain->smmu; + + cb_base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, cfg->cbndx); + if (arm_smmu_enable_clocks(smmu)) + return; + dev_err(smmu->dev, "Writing 0x%lx to FSRRESTORE on cb %d\n", + flags, cfg->cbndx); + writel_relaxed(flags, cb_base + ARM_SMMU_CB_FSRRESTORE); + /* give the interrupt time to fire... */ + msleep(1000); + arm_smmu_disable_clocks(smmu); +} + static void arm_smmu_init_context_bank(struct arm_smmu_domain *smmu_domain, struct io_pgtable_cfg *pgtbl_cfg) { @@ -723,6 +1583,9 @@ */ #ifdef CONFIG_64BIT reg = CBA2R_RW64_64BIT; + if (!arm_smmu_has_secure_vmid(smmu_domain) && + arm_smmu_is_static_cb(smmu)) + msm_tz_set_cb_format(smmu->sec_id, cfg->cbndx); #else reg = CBA2R_RW64_32BIT; #endif @@ -741,9 +1604,8 @@ if (stage1) { reg |= (CBAR_S1_BPSHCFG_NSH << CBAR_S1_BPSHCFG_SHIFT) | (CBAR_S1_MEMATTR_WB << CBAR_S1_MEMATTR_SHIFT); - } else { - reg |= ARM_SMMU_CB_VMID(cfg) << CBAR_VMID_SHIFT; } + reg |= ARM_SMMU_CB_VMID(cfg) << CBAR_VMID_SHIFT; writel_relaxed(reg, gr1_base + ARM_SMMU_GR1_CBAR(cfg->cbndx)); /* TTBRs */ @@ -767,7 +1629,6 @@ writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBCR); if (smmu->version > ARM_SMMU_V1) { reg = pgtbl_cfg->arm_lpae_s1_cfg.tcr >> 32; - reg |= TTBCR2_SEP_UPSTREAM; writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBCR2); } } else { @@ -783,8 +1644,25 @@ writel_relaxed(reg, cb_base + ARM_SMMU_CB_S1_MAIR1); } + if (smmu->model == SMMU_MODEL_QCOM_V2) { + reg = ACTLR_QCOM_ISH << ACTLR_QCOM_ISH_SHIFT | + ACTLR_QCOM_OSH << ACTLR_QCOM_OSH_SHIFT | + ACTLR_QCOM_NSH << ACTLR_QCOM_NSH_SHIFT; + writel_relaxed(reg, cb_base + ARM_SMMU_CB_ACTLR); + } + /* SCTLR */ - reg = SCTLR_CFCFG | SCTLR_CFIE | SCTLR_CFRE | SCTLR_M | SCTLR_EAE_SBOP; + reg = SCTLR_CFCFG | SCTLR_CFIE | SCTLR_CFRE | SCTLR_EAE_SBOP; + + if (smmu_domain->attributes & (1 << DOMAIN_ATTR_CB_STALL_DISABLE)) { + reg &= ~SCTLR_CFCFG; + reg |= SCTLR_HUPCF; + } + + if ((!(smmu_domain->attributes & (1 << DOMAIN_ATTR_S1_BYPASS)) && + !(smmu_domain->attributes & (1 << DOMAIN_ATTR_EARLY_MAP))) || + !stage1) + reg |= SCTLR_M; if (stage1) reg |= SCTLR_S1_ASIDPNE; #ifdef __BIG_ENDIAN @@ -793,20 +1671,107 @@ writel_relaxed(reg, cb_base + ARM_SMMU_CB_SCTLR); } +static bool arm_smmu_is_static_cb(struct arm_smmu_device *smmu) +{ + return smmu->options & ARM_SMMU_OPT_STATIC_CB; +} + +static bool arm_smmu_has_secure_vmid(struct arm_smmu_domain *smmu_domain) +{ + return smmu_domain->secure_vmid != VMID_INVAL; +} + +static bool arm_smmu_is_slave_side_secure(struct arm_smmu_domain *smmu_domain) +{ + return arm_smmu_has_secure_vmid(smmu_domain) + && smmu_domain->slave_side_secure; +} + +static bool arm_smmu_is_master_side_secure(struct arm_smmu_domain *smmu_domain) +{ + return arm_smmu_has_secure_vmid(smmu_domain) + && !smmu_domain->slave_side_secure; +} + +static void arm_smmu_secure_domain_lock(struct arm_smmu_domain *smmu_domain) +{ + if (arm_smmu_is_master_side_secure(smmu_domain)) + mutex_lock(&smmu_domain->assign_lock); +} + +static void arm_smmu_secure_domain_unlock(struct arm_smmu_domain *smmu_domain) +{ + if (arm_smmu_is_master_side_secure(smmu_domain)) + mutex_unlock(&smmu_domain->assign_lock); +} + +static unsigned long arm_smmu_pgtbl_lock(struct arm_smmu_domain *smmu_domain) +{ + unsigned long flags = 0; + + if (arm_smmu_is_slave_side_secure(smmu_domain)) + mutex_lock(&smmu_domain->pgtbl_mutex_lock); + else + spin_lock_irqsave(&smmu_domain->pgtbl_spin_lock, flags); + + return flags; +} + +static void arm_smmu_pgtbl_unlock(struct arm_smmu_domain *smmu_domain, + unsigned long flags) +{ + if (arm_smmu_is_slave_side_secure(smmu_domain)) + mutex_unlock(&smmu_domain->pgtbl_mutex_lock); + else + spin_unlock_irqrestore(&smmu_domain->pgtbl_spin_lock, flags); +} + +static int arm_smmu_restore_sec_cfg(struct arm_smmu_device *smmu) +{ + int ret; + u64 scm_ret = 0; + + if (!arm_smmu_is_static_cb(smmu)) + return 0; + + ret = scm_restore_sec_cfg(smmu->sec_id, 0x0, &scm_ret); + if (ret || scm_ret) { + pr_err("scm call IOMMU_SECURE_CFG failed\n"); + return -EINVAL; + } + + return 0; +} + +static bool is_iommu_pt_coherent(struct arm_smmu_domain *smmu_domain) +{ + if (smmu_domain->attributes & + (1 << DOMAIN_ATTR_PAGE_TABLE_FORCE_COHERENT)) + return true; + else if (smmu_domain->smmu && smmu_domain->smmu->dev) + return smmu_domain->smmu->dev->archdata.dma_coherent; + else + return false; +} + static int arm_smmu_init_domain_context(struct iommu_domain *domain, - struct arm_smmu_device *smmu) + struct arm_smmu_device *smmu, + struct arm_smmu_master_cfg *master_cfg) { int irq, start, ret = 0; unsigned long ias, oas; + int sep = 0; struct io_pgtable_ops *pgtbl_ops; - struct io_pgtable_cfg pgtbl_cfg; enum io_pgtable_fmt fmt; struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain); struct arm_smmu_cfg *cfg = &smmu_domain->cfg; + bool is_fast = smmu_domain->attributes & (1 << DOMAIN_ATTR_FAST); + unsigned long quirks = + smmu_domain->attributes & (1 << DOMAIN_ATTR_ENABLE_TTBR1) ? + IO_PGTABLE_QUIRK_ARM_TTBR1 : 0; - mutex_lock(&smmu_domain->init_mutex); if (smmu_domain->smmu) - goto out_unlock; + goto out; /* * Mapping the requested stage onto what we support is surprisingly @@ -837,9 +1802,27 @@ start = smmu->num_s2_context_banks; ias = smmu->va_size; oas = smmu->ipa_size; - if (IS_ENABLED(CONFIG_64BIT)) + if (IS_ENABLED(CONFIG_64BIT)) { fmt = ARM_64_LPAE_S1; - else + + if (quirks & IO_PGTABLE_QUIRK_ARM_TTBR1) { + + /* + * When the UBS id is 5 we know that the bus + * size is 49 bits and that bit 48 is the fixed + * sign extension bit. For any other bus size + * we need to specify the sign extension bit + * and adjust the input size accordingly + */ + + if (smmu->ubs == 5) { + sep = 48; + } else { + sep = ias - 1; + ias--; + } + } + } else fmt = ARM_32_LPAE_S1; break; case ARM_SMMU_DOMAIN_NESTED: @@ -859,15 +1842,18 @@ break; default: ret = -EINVAL; - goto out_unlock; + goto out; } - ret = __arm_smmu_alloc_bitmap(smmu->context_map, start, - smmu->num_context_banks); + if (cfg->cbndx == INVALID_CBNDX) { + ret = arm_smmu_alloc_context_idx(smmu, start, + smmu->num_context_banks, master_cfg->streamids, + master_cfg->num_streamids); if (IS_ERR_VALUE(ret)) - goto out_unlock; - + goto out; cfg->cbndx = ret; + } + if (smmu->version == ARM_SMMU_V1) { cfg->irptndx = atomic_inc_return(&smmu->irptndx); cfg->irptndx %= smmu->num_context_irqs; @@ -875,33 +1861,68 @@ cfg->irptndx = cfg->cbndx; } - pgtbl_cfg = (struct io_pgtable_cfg) { + smmu_domain->smmu = smmu; + + if (is_iommu_pt_coherent(smmu_domain)) + quirks |= IO_PGTABLE_QUIRK_PAGE_TABLE_COHERENT; + + if (arm_smmu_is_slave_side_secure(smmu_domain)) { + smmu_domain->pgtbl_cfg = (struct io_pgtable_cfg) { + .quirks = quirks, + .pgsize_bitmap = arm_smmu_ops.pgsize_bitmap, + .arm_msm_secure_cfg = { + .sec_id = smmu->sec_id, + .cbndx = cfg->cbndx, + }, + .iommu_dev = smmu->dev, + }; + fmt = ARM_MSM_SECURE; + } else { + + smmu_domain->pgtbl_cfg = (struct io_pgtable_cfg) { + .quirks = quirks, .pgsize_bitmap = arm_smmu_ops.pgsize_bitmap, .ias = ias, .oas = oas, + .sep = sep, .tlb = &arm_smmu_gather_ops, .iommu_dev = smmu->dev, + .iova_base = domain->geometry.aperture_start, + .iova_end = domain->geometry.aperture_end, }; + } - smmu_domain->smmu = smmu; - pgtbl_ops = alloc_io_pgtable_ops(fmt, &pgtbl_cfg, smmu_domain); + if (is_fast) + fmt = ARM_V8L_FAST; + + cfg->asid = cfg->cbndx + 1; + cfg->vmid = cfg->cbndx + 2; + pgtbl_ops = alloc_io_pgtable_ops(fmt, &smmu_domain->pgtbl_cfg, + smmu_domain); if (!pgtbl_ops) { ret = -ENOMEM; goto out_clear_smmu; } - - /* Update our support page sizes to reflect the page table format */ - arm_smmu_ops.pgsize_bitmap = pgtbl_cfg.pgsize_bitmap; + /* + * assign any page table memory that might have been allocated + * during alloc_io_pgtable_ops + */ + if (arm_smmu_is_master_side_secure(smmu_domain)) { + arm_smmu_secure_domain_lock(smmu_domain); + arm_smmu_assign_table(smmu_domain); + arm_smmu_secure_domain_unlock(smmu_domain); + } /* Initialise the context bank with our page table cfg */ - arm_smmu_init_context_bank(smmu_domain, &pgtbl_cfg); + arm_smmu_init_context_bank(smmu_domain, &smmu_domain->pgtbl_cfg); /* * Request context fault interrupt. Do this last to avoid the * handler seeing a half-initialised domain state. */ irq = smmu->irqs[smmu->num_global_irqs + cfg->irptndx]; - ret = request_irq(irq, arm_smmu_context_fault, IRQF_SHARED, + ret = request_threaded_irq(irq, NULL, arm_smmu_context_fault, + IRQF_ONESHOT | IRQF_SHARED, "arm-smmu-context-fault", domain); if (IS_ERR_VALUE(ret)) { dev_err(smmu->dev, "failed to request context IRQ %d (%u)\n", @@ -909,16 +1930,13 @@ cfg->irptndx = INVALID_IRPTNDX; } - mutex_unlock(&smmu_domain->init_mutex); - /* Publish page table ops for map/unmap */ smmu_domain->pgtbl_ops = pgtbl_ops; return 0; out_clear_smmu: smmu_domain->smmu = NULL; -out_unlock: - mutex_unlock(&smmu_domain->init_mutex); +out: return ret; } @@ -930,9 +1948,8 @@ void __iomem *cb_base; int irq; - if (!smmu) - return; - + if (arm_smmu_enable_clocks(smmu_domain->smmu)) + goto free_irqs; /* * Disable the context bank and free the page tables before freeing * it. @@ -940,15 +1957,32 @@ cb_base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, cfg->cbndx); writel_relaxed(0, cb_base + ARM_SMMU_CB_SCTLR); + arm_smmu_disable_clocks(smmu_domain->smmu); + + if (smmu_domain->pgtbl_ops) { + free_io_pgtable_ops(smmu_domain->pgtbl_ops); + /* unassign any freed page table memory */ + if (arm_smmu_is_master_side_secure(smmu_domain)) { + arm_smmu_secure_domain_lock(smmu_domain); + arm_smmu_secure_pool_destroy(smmu_domain); + arm_smmu_unassign_table(smmu_domain); + arm_smmu_secure_domain_unlock(smmu_domain); + } + smmu_domain->pgtbl_ops = NULL; + } + +free_irqs: if (cfg->irptndx != INVALID_IRPTNDX) { irq = smmu->irqs[smmu->num_global_irqs + cfg->irptndx]; free_irq(irq, domain); } - if (smmu_domain->pgtbl_ops) - free_io_pgtable_ops(smmu_domain->pgtbl_ops); - - __arm_smmu_free_bitmap(smmu->context_map, cfg->cbndx); + arm_smmu_free_context_idx(smmu, cfg->cbndx); + smmu_domain->smmu = NULL; + cfg->cbndx = INVALID_CBNDX; + cfg->irptndx = INVALID_IRPTNDX; + cfg->asid = INVALID_ASID; + cfg->vmid = INVALID_VMID; } static struct iommu_domain *arm_smmu_domain_alloc(unsigned type) @@ -966,8 +2000,19 @@ if (!smmu_domain) return NULL; + smmu_domain->secure_vmid = VMID_INVAL; + INIT_LIST_HEAD(&smmu_domain->pte_info_list); + INIT_LIST_HEAD(&smmu_domain->unassign_list); + INIT_LIST_HEAD(&smmu_domain->secure_pool_list); + smmu_domain->cfg.cbndx = INVALID_CBNDX; + smmu_domain->cfg.irptndx = INVALID_IRPTNDX; + smmu_domain->cfg.asid = INVALID_ASID; + smmu_domain->cfg.vmid = INVALID_VMID; + mutex_init(&smmu_domain->init_mutex); - spin_lock_init(&smmu_domain->pgtbl_lock); + spin_lock_init(&smmu_domain->pgtbl_spin_lock); + mutex_init(&smmu_domain->assign_lock); + mutex_init(&smmu_domain->pgtbl_mutex_lock); return &smmu_domain->domain; } @@ -980,7 +2025,18 @@ * Free the domain resources. We assume that all devices have * already been detached. */ - arm_smmu_destroy_domain_context(domain); + if (smmu_domain->pgtbl_ops) { + free_io_pgtable_ops(smmu_domain->pgtbl_ops); + /* unassign any freed page table memory */ + if (arm_smmu_is_master_side_secure(smmu_domain)) { + arm_smmu_secure_domain_lock(smmu_domain); + arm_smmu_secure_pool_destroy(smmu_domain); + arm_smmu_unassign_table(smmu_domain); + arm_smmu_secure_domain_unlock(smmu_domain); + } + smmu_domain->pgtbl_ops = NULL; + } + kfree(smmu_domain); } @@ -1006,8 +2062,8 @@ /* Allocate the SMRs on the SMMU */ for (i = 0; i < cfg->num_streamids; ++i) { - int idx = __arm_smmu_alloc_bitmap(smmu->smr_map, 0, - smmu->num_mapping_groups); + int idx = arm_smmu_alloc_smr_idx(smmu, 0, + smmu->num_mapping_groups, cfg->streamids[i]); if (IS_ERR_VALUE(idx)) { dev_err(smmu->dev, "failed to allocate free SMR\n"); goto err_free_smrs; @@ -1032,7 +2088,7 @@ err_free_smrs: while (--i >= 0) - __arm_smmu_free_bitmap(smmu->smr_map, smrs[i].idx); + arm_smmu_free_smr_idx(smmu, smrs[i].idx); kfree(smrs); return -ENOSPC; } @@ -1052,7 +2108,7 @@ u8 idx = smrs[i].idx; writel_relaxed(~SMR_VALID, gr0_base + ARM_SMMU_GR0_SMR(idx)); - __arm_smmu_free_bitmap(smmu->smr_map, idx); + arm_smmu_free_smr_idx(smmu, idx); } cfg->smrs = NULL; @@ -1098,6 +2154,8 @@ * We *must* clear the S2CR first, because freeing the SMR means * that it can be re-allocated immediately. */ + if (arm_smmu_enable_clocks(smmu)) + return; for (i = 0; i < cfg->num_streamids; ++i) { u32 idx = cfg->smrs ? cfg->smrs[i].idx : cfg->streamids[i]; @@ -1106,6 +2164,123 @@ } arm_smmu_master_free_smrs(smmu, cfg); + arm_smmu_disable_clocks(smmu); +} + +static void arm_smmu_impl_def_programming(struct arm_smmu_device *smmu) +{ + int i; + struct arm_smmu_impl_def_reg *regs = smmu->impl_def_attach_registers; + + arm_smmu_halt(smmu); + for (i = 0; i < smmu->num_impl_def_attach_registers; ++i) + writel_relaxed(regs[i].value, + ARM_SMMU_GR0(smmu) + regs[i].offset); + arm_smmu_resume(smmu); +} + +static int arm_smmu_attach_dynamic(struct iommu_domain *domain, + struct arm_smmu_device *smmu) +{ + int ret; + struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain); + enum io_pgtable_fmt fmt; + struct io_pgtable_ops *pgtbl_ops = NULL; + struct arm_smmu_cfg *cfg = &smmu_domain->cfg; + + if (!(smmu->options & ARM_SMMU_OPT_DYNAMIC)) { + dev_err(smmu->dev, "dynamic domains not supported\n"); + return -EPERM; + } + + if (smmu_domain->smmu != NULL) { + dev_err(smmu->dev, "domain is already attached\n"); + return -EBUSY; + } + + if (smmu_domain->cfg.cbndx >= smmu->num_context_banks) { + dev_err(smmu->dev, "invalid context bank\n"); + return -ENODEV; + } + + if (smmu->features & ARM_SMMU_FEAT_TRANS_NESTED) { + smmu_domain->cfg.cbar = CBAR_TYPE_S1_TRANS_S2_BYPASS; + } else if (smmu->features & ARM_SMMU_FEAT_TRANS_S1) { + smmu_domain->cfg.cbar = CBAR_TYPE_S1_TRANS_S2_BYPASS; + } else { + /* dynamic only makes sense for S1. */ + return -EINVAL; + } + + smmu_domain->pgtbl_cfg = (struct io_pgtable_cfg) { + .pgsize_bitmap = arm_smmu_ops.pgsize_bitmap, + .ias = smmu->va_size, + .oas = smmu->ipa_size, + .tlb = &arm_smmu_gather_ops, + .iommu_dev = smmu->dev, + }; + + fmt = IS_ENABLED(CONFIG_64BIT) ? ARM_64_LPAE_S1 : ARM_32_LPAE_S1; + + pgtbl_ops = alloc_io_pgtable_ops(fmt, &smmu_domain->pgtbl_cfg, + smmu_domain); + if (!pgtbl_ops) + return -ENOMEM; + + /* + * assign any page table memory that might have been allocated + * during alloc_io_pgtable_ops + */ + if (arm_smmu_is_master_side_secure(smmu_domain)) { + arm_smmu_secure_domain_lock(smmu_domain); + arm_smmu_assign_table(smmu_domain); + arm_smmu_secure_domain_unlock(smmu_domain); + } + + cfg->vmid = cfg->cbndx + 2; + smmu_domain->smmu = smmu; + + mutex_lock(&smmu->attach_lock); + /* try to avoid reusing an old ASID right away */ + ret = idr_alloc_cyclic(&smmu->asid_idr, domain, + smmu->num_context_banks + 2, + MAX_ASID + 1, GFP_KERNEL); + if (ret < 0) { + dev_err_ratelimited(smmu->dev, + "dynamic ASID allocation failed: %d\n", ret); + goto out; + } + + smmu_domain->cfg.asid = ret; + smmu_domain->smmu = smmu; + smmu_domain->pgtbl_ops = pgtbl_ops; + ret = 0; +out: + if (ret) + free_io_pgtable_ops(pgtbl_ops); + mutex_unlock(&smmu->attach_lock); + + return ret; +} + +static int arm_smmu_populate_cb(struct arm_smmu_device *smmu, + struct arm_smmu_domain *smmu_domain, struct device *dev) +{ + struct arm_smmu_master_cfg *cfg; + struct arm_smmu_cfg *smmu_cfg = &smmu_domain->cfg; + struct static_cbndx_entry *entry; + + cfg = find_smmu_master_cfg(dev); + if (!cfg) + return -ENODEV; + + entry = arm_smmu_get_static_entry_from_sid(smmu, cfg->streamids[0]); + if (entry && entry->type == TYPE_TRANS) { + smmu_cfg->cbndx = entry->cbndx; + return 0; + } + + return -EINVAL; } static int arm_smmu_attach_dev(struct iommu_domain *domain, struct device *dev) @@ -1114,22 +2289,83 @@ struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain); struct arm_smmu_device *smmu; struct arm_smmu_master_cfg *cfg; + int atomic_ctx = smmu_domain->attributes & (1 << DOMAIN_ATTR_ATOMIC); + mutex_lock(&smmu_domain->init_mutex); smmu = find_smmu_for_device(dev); if (!smmu) { dev_err(dev, "cannot attach to SMMU, is it on the same bus?\n"); + mutex_unlock(&smmu_domain->init_mutex); return -ENXIO; } + if (smmu_domain->attributes & (1 << DOMAIN_ATTR_DYNAMIC)) { + ret = arm_smmu_attach_dynamic(domain, smmu); + mutex_unlock(&smmu_domain->init_mutex); + return ret; + } + + mutex_lock(&smmu->attach_lock); + if (dev->archdata.iommu) { dev_err(dev, "already attached to IOMMU domain\n"); - return -EEXIST; + ret = -EEXIST; + goto err_unlock; + } + + if (!smmu->attach_count) { + /* + * We need an extra power vote if we can't retain register + * settings across a power collapse, or if this is an + * atomic domain (since atomic domains can't sleep during + * unmap, so regulators already need to be on to enable tlb + * invalidation). The result (due to regulator + * refcounting) is that we never disable regulators while a + * client is attached in these cases. + */ + if (!(smmu->options & ARM_SMMU_OPT_REGISTER_SAVE)) { + ret = arm_smmu_enable_regulators(smmu); + if (ret) + goto err_unlock; + } + ret = arm_smmu_enable_clocks(smmu); + if (ret) + goto err_disable_regulators; + arm_smmu_device_reset(smmu); + arm_smmu_impl_def_programming(smmu); + } else { + ret = arm_smmu_enable_clocks(smmu); + if (ret) + goto err_unlock; + } + smmu->attach_count++; + + if (atomic_ctx) { + ret = arm_smmu_enable_regulators(smmu); + if (ret) + goto err_disable_clocks; + } + + if (arm_smmu_is_static_cb(smmu)) { + ret = arm_smmu_populate_cb(smmu, smmu_domain, dev); + + if (ret) { + dev_err(dev, "Failed to get valid context bank\n"); + goto err_atomic_ctx; + } + smmu_domain->slave_side_secure = true; + } + + cfg = find_smmu_master_cfg(dev); + if (!cfg) { + ret = -ENODEV; + goto err_atomic_ctx; } /* Ensure that the domain is finalised */ - ret = arm_smmu_init_domain_context(domain, smmu); + ret = arm_smmu_init_domain_context(domain, smmu, cfg); if (IS_ERR_VALUE(ret)) - return ret; + goto err_atomic_ctx; /* * Sanity check the domain. We don't support domains across @@ -1139,31 +2375,196 @@ dev_err(dev, "cannot attach to SMMU %s whilst already attached to domain on SMMU %s\n", dev_name(smmu_domain->smmu->dev), dev_name(smmu->dev)); - return -EINVAL; + ret = -EINVAL; + goto err_destroy_domain_context; } /* Looks ok, so add the device to the domain */ - cfg = find_smmu_master_cfg(dev); - if (!cfg) - return -ENODEV; - ret = arm_smmu_domain_add_master(smmu_domain, cfg); - if (!ret) + if (ret) + goto err_destroy_domain_context; dev->archdata.iommu = domain; + arm_smmu_disable_clocks(smmu); + mutex_unlock(&smmu->attach_lock); + mutex_unlock(&smmu_domain->init_mutex); + return ret; + +err_destroy_domain_context: + arm_smmu_destroy_domain_context(domain); +err_atomic_ctx: + if (atomic_ctx) + arm_smmu_disable_regulators(smmu); +err_disable_clocks: + arm_smmu_disable_clocks(smmu); + --smmu->attach_count; +err_disable_regulators: + if (!smmu->attach_count && + (!(smmu->options & ARM_SMMU_OPT_REGISTER_SAVE))) + arm_smmu_disable_regulators(smmu); +err_unlock: + mutex_unlock(&smmu->attach_lock); + mutex_unlock(&smmu_domain->init_mutex); return ret; } +static void arm_smmu_power_off(struct arm_smmu_device *smmu) +{ + /* Turn the thing off */ + if (arm_smmu_enable_clocks(smmu)) + return; + writel_relaxed(sCR0_CLIENTPD, + ARM_SMMU_GR0_NS(smmu) + ARM_SMMU_GR0_sCR0); + arm_smmu_disable_clocks(smmu); + if (!(smmu->options & ARM_SMMU_OPT_REGISTER_SAVE)) + arm_smmu_disable_regulators(smmu); +} + +static void arm_smmu_detach_dynamic(struct iommu_domain *domain, + struct arm_smmu_device *smmu) +{ + struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain); + + mutex_lock(&smmu->attach_lock); + if (smmu->attach_count > 0) { + if (arm_smmu_enable_clocks(smmu_domain->smmu)) + goto idr_remove; + arm_smmu_tlb_inv_context(smmu_domain); + arm_smmu_disable_clocks(smmu_domain->smmu); + } +idr_remove: + idr_remove(&smmu->asid_idr, smmu_domain->cfg.asid); + smmu_domain->cfg.asid = INVALID_ASID; + smmu_domain->smmu = NULL; + mutex_unlock(&smmu->attach_lock); +} + static void arm_smmu_detach_dev(struct iommu_domain *domain, struct device *dev) { struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain); struct arm_smmu_master_cfg *cfg; + struct arm_smmu_device *smmu; + int atomic_ctx = smmu_domain->attributes & (1 << DOMAIN_ATTR_ATOMIC); + + mutex_lock(&smmu_domain->init_mutex); + smmu = smmu_domain->smmu; + if (!smmu) { + dev_err(dev, "Domain already detached!\n"); + mutex_unlock(&smmu_domain->init_mutex); + return; + } + + + if (smmu_domain->attributes & (1 << DOMAIN_ATTR_DYNAMIC)) { + arm_smmu_detach_dynamic(domain, smmu); + mutex_unlock(&smmu_domain->init_mutex); + if (atomic_ctx) + arm_smmu_disable_regulators(smmu); + return; + } + + mutex_lock(&smmu->attach_lock); cfg = find_smmu_master_cfg(dev); if (!cfg) - return; + goto unlock; dev->archdata.iommu = NULL; arm_smmu_domain_remove_master(smmu_domain, cfg); + arm_smmu_destroy_domain_context(domain); + if (!--smmu->attach_count) + arm_smmu_power_off(smmu); + if (atomic_ctx) + arm_smmu_disable_regulators(smmu); +unlock: + mutex_unlock(&smmu->attach_lock); + mutex_unlock(&smmu_domain->init_mutex); +} + + +static int arm_smmu_assign_table(struct arm_smmu_domain *smmu_domain) +{ + int ret = 0; + int dest_vmids[2] = {VMID_HLOS, smmu_domain->secure_vmid}; + int dest_perms[2] = {PERM_READ | PERM_WRITE, PERM_READ}; + int source_vmid = VMID_HLOS; + struct arm_smmu_pte_info *pte_info, *temp; + + if (!arm_smmu_is_master_side_secure(smmu_domain)) + return ret; + + list_for_each_entry(pte_info, &smmu_domain->pte_info_list, entry) { + ret = hyp_assign_phys(virt_to_phys(pte_info->virt_addr), + PAGE_SIZE, &source_vmid, 1, + dest_vmids, dest_perms, 2); + if (WARN_ON(ret)) + break; + } + + list_for_each_entry_safe(pte_info, temp, &smmu_domain->pte_info_list, + entry) { + list_del(&pte_info->entry); + kfree(pte_info); + } + return ret; +} + +static void arm_smmu_unassign_table(struct arm_smmu_domain *smmu_domain) +{ + int ret; + int dest_vmids = VMID_HLOS; + int dest_perms = PERM_READ | PERM_WRITE | PERM_EXEC; + int source_vmlist[2] = {smmu_domain->secure_vmid, VMID_HLOS}; + struct arm_smmu_pte_info *pte_info, *temp; + + if (!arm_smmu_is_master_side_secure(smmu_domain)) + return; + + list_for_each_entry(pte_info, &smmu_domain->unassign_list, entry) { + ret = hyp_assign_phys(virt_to_phys(pte_info->virt_addr), + PAGE_SIZE, source_vmlist, 2, + &dest_vmids, &dest_perms, 1); + if (WARN_ON(ret)) + break; + + free_pages_exact(pte_info->virt_addr, pte_info->size); + } + + list_for_each_entry_safe(pte_info, temp, &smmu_domain->unassign_list, + entry) { + list_del(&pte_info->entry); + kfree(pte_info); + } + return; +} + +static void arm_smmu_unprepare_pgtable(void *cookie, void *addr, size_t size) +{ + struct arm_smmu_domain *smmu_domain = cookie; + struct arm_smmu_pte_info *pte_info; + + BUG_ON(!arm_smmu_is_master_side_secure(smmu_domain)); + + pte_info = kzalloc(sizeof(struct arm_smmu_pte_info), GFP_ATOMIC); + if (!pte_info) + return; + + pte_info->virt_addr = addr; + pte_info->size = size; + list_add_tail(&pte_info->entry, &smmu_domain->unassign_list); +} + +static void arm_smmu_prepare_pgtable(void *addr, void *cookie) +{ + struct arm_smmu_domain *smmu_domain = cookie; + struct arm_smmu_pte_info *pte_info; + + BUG_ON(!arm_smmu_is_master_side_secure(smmu_domain)); + + pte_info = kzalloc(sizeof(struct arm_smmu_pte_info), GFP_ATOMIC); + if (!pte_info) + return; + pte_info->virt_addr = addr; + list_add_tail(&pte_info->entry, &smmu_domain->pte_info_list); } static int arm_smmu_map(struct iommu_domain *domain, unsigned long iova, @@ -1177,9 +2578,87 @@ if (!ops) return -ENODEV; - spin_lock_irqsave(&smmu_domain->pgtbl_lock, flags); + arm_smmu_secure_domain_lock(smmu_domain); + + flags = arm_smmu_pgtbl_lock(smmu_domain); ret = ops->map(ops, iova, paddr, size, prot); - spin_unlock_irqrestore(&smmu_domain->pgtbl_lock, flags); + arm_smmu_pgtbl_unlock(smmu_domain, flags); + + if (!ret) + ret = arm_smmu_assign_table(smmu_domain); + + arm_smmu_secure_domain_unlock(smmu_domain); + + return ret; +} + +static uint64_t arm_smmu_iova_to_pte(struct iommu_domain *domain, + dma_addr_t iova) +{ + uint64_t ret; + unsigned long flags; + struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain); + struct io_pgtable_ops *ops = smmu_domain->pgtbl_ops; + + if (!ops) + return 0; + + flags = arm_smmu_pgtbl_lock(smmu_domain); + ret = ops->iova_to_pte(ops, iova); + arm_smmu_pgtbl_unlock(smmu_domain, flags); + return ret; +} + +static size_t arm_smmu_map_sg(struct iommu_domain *domain, unsigned long iova, + struct scatterlist *sg, unsigned int nents, int prot) +{ + int ret; + size_t size; + unsigned long flags; + struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain); + struct io_pgtable_ops *ops = smmu_domain->pgtbl_ops; + struct arm_smmu_device *smmu = smmu_domain->smmu; + int atomic_ctx = smmu_domain->attributes & (1 << DOMAIN_ATTR_ATOMIC); + + if (!ops) + return -ENODEV; + + if (arm_smmu_is_slave_side_secure(smmu_domain) && atomic_ctx) { + dev_err(smmu->dev, "Slave side atomic context not supported\n"); + return 0; + } + + if (arm_smmu_is_slave_side_secure(smmu_domain)) { + mutex_lock(&smmu_domain->init_mutex); + + if (arm_smmu_enable_clocks(smmu)) { + mutex_unlock(&smmu_domain->init_mutex); + return 0; + } + } + + arm_smmu_secure_domain_lock(smmu_domain); + + flags = arm_smmu_pgtbl_lock(smmu_domain); + ret = ops->map_sg(ops, iova, sg, nents, prot, &size); + arm_smmu_pgtbl_unlock(smmu_domain, flags); + + if (ret) { + if (arm_smmu_assign_table(smmu_domain)) { + ret = 0; + goto out; + } + } else { + arm_smmu_secure_domain_unlock(smmu_domain); + arm_smmu_unmap(domain, iova, size); + } + +out: + arm_smmu_secure_domain_unlock(smmu_domain); + if (arm_smmu_is_slave_side_secure(smmu_domain)) { + arm_smmu_disable_clocks(smmu_domain->smmu); + mutex_unlock(&smmu_domain->init_mutex); + } return ret; } @@ -1190,31 +2669,206 @@ unsigned long flags; struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain); struct io_pgtable_ops *ops= smmu_domain->pgtbl_ops; + int atomic_ctx = smmu_domain->attributes & (1 << DOMAIN_ATTR_ATOMIC); if (!ops) return 0; - spin_lock_irqsave(&smmu_domain->pgtbl_lock, flags); + if (arm_smmu_is_slave_side_secure(smmu_domain) && atomic_ctx) { + dev_err(smmu_domain->smmu->dev, + "Slave side atomic context not supported\n"); + return 0; + } + + /* + * The contract here is that if you set DOMAIN_ATTR_ATOMIC your + * domain *must* must be attached an SMMU during unmap. This + * function calls other functions that try to use smmu_domain->smmu + * if it's not NULL (like the tlb invalidation routines). So if + * the client sets DOMAIN_ATTR_ATOMIC and detaches in the middle of + * the unmap the smmu instance could go away and we could + * dereference NULL. This little BUG_ON should catch most gross + * offenders but if atomic clients violate this contract then this + * code is racy. + */ + BUG_ON(atomic_ctx && !smmu_domain->smmu); + + if (atomic_ctx) { + if (arm_smmu_enable_clocks_atomic(smmu_domain->smmu)) + return 0; + } else { + mutex_lock(&smmu_domain->init_mutex); + arm_smmu_secure_domain_lock(smmu_domain); + if (smmu_domain->smmu && + arm_smmu_enable_clocks(smmu_domain->smmu)) { + arm_smmu_secure_domain_unlock(smmu_domain); + mutex_unlock(&smmu_domain->init_mutex); + return 0; + } + } + + flags = arm_smmu_pgtbl_lock(smmu_domain); ret = ops->unmap(ops, iova, size); - spin_unlock_irqrestore(&smmu_domain->pgtbl_lock, flags); + arm_smmu_pgtbl_unlock(smmu_domain, flags); + + /* + * While splitting up block mappings, we might allocate page table + * memory during unmap, so the vmids needs to be assigned to the + * memory here as well. + */ + if (arm_smmu_assign_table(smmu_domain)) { + arm_smmu_unassign_table(smmu_domain); + arm_smmu_secure_domain_unlock(smmu_domain); + mutex_unlock(&smmu_domain->init_mutex); + return 0; + } + + /* Also unassign any pages that were free'd during unmap */ + arm_smmu_unassign_table(smmu_domain); + + if (atomic_ctx) { + arm_smmu_disable_clocks_atomic(smmu_domain->smmu); + } else { + if (smmu_domain->smmu) + arm_smmu_disable_clocks(smmu_domain->smmu); + arm_smmu_secure_domain_unlock(smmu_domain); + mutex_unlock(&smmu_domain->init_mutex); + } + return ret; } -static phys_addr_t arm_smmu_iova_to_phys_hard(struct iommu_domain *domain, +static phys_addr_t arm_smmu_iova_to_phys(struct iommu_domain *domain, dma_addr_t iova) { + phys_addr_t ret; + unsigned long flags; + struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain); + struct io_pgtable_ops *ops= smmu_domain->pgtbl_ops; + + if (!ops) + return 0; + + flags = arm_smmu_pgtbl_lock(smmu_domain); + ret = ops->iova_to_phys(ops, iova); + arm_smmu_pgtbl_unlock(smmu_domain, flags); + return ret; +} + +static bool arm_smmu_is_iova_coherent(struct iommu_domain *domain, + dma_addr_t iova) +{ + bool ret; + unsigned long flags; + struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain); + struct io_pgtable_ops *ops = smmu_domain->pgtbl_ops; + + if (!ops) + return false; + + flags = arm_smmu_pgtbl_lock(smmu_domain); + ret = ops->is_iova_coherent(ops, iova); + arm_smmu_pgtbl_unlock(smmu_domain, flags); + return ret; +} + +static int arm_smmu_wait_for_halt(struct arm_smmu_device *smmu) +{ + void __iomem *impl_def1_base = ARM_SMMU_IMPL_DEF1(smmu); + u32 tmp; + + if (readl_poll_timeout_atomic(impl_def1_base + IMPL_DEF1_MICRO_MMU_CTRL, + tmp, (tmp & MICRO_MMU_CTRL_IDLE), + 0, 30000)) { + dev_err(smmu->dev, "Couldn't halt SMMU!\n"); + return -EBUSY; + } + + return 0; +} + +static int __arm_smmu_halt(struct arm_smmu_device *smmu, bool wait) +{ + u32 reg; + void __iomem *impl_def1_base = ARM_SMMU_IMPL_DEF1(smmu); + + reg = readl_relaxed(impl_def1_base + IMPL_DEF1_MICRO_MMU_CTRL); + reg |= MICRO_MMU_CTRL_LOCAL_HALT_REQ; + + if (arm_smmu_is_static_cb(smmu)) { + phys_addr_t impl_def1_base_phys = impl_def1_base - smmu->base + + smmu->phys_addr; + + if (scm_io_write(impl_def1_base_phys + + IMPL_DEF1_MICRO_MMU_CTRL, reg)) { + dev_err(smmu->dev, + "scm_io_write fail. SMMU might not be halted"); + return -EINVAL; + } + } else { + writel_relaxed(reg, impl_def1_base + IMPL_DEF1_MICRO_MMU_CTRL); + } + + return wait ? arm_smmu_wait_for_halt(smmu) : 0; +} + +static int arm_smmu_halt(struct arm_smmu_device *smmu) +{ + return __arm_smmu_halt(smmu, true); +} + +static int arm_smmu_halt_nowait(struct arm_smmu_device *smmu) +{ + return __arm_smmu_halt(smmu, false); +} + +static void arm_smmu_resume(struct arm_smmu_device *smmu) +{ + void __iomem *impl_def1_base = ARM_SMMU_IMPL_DEF1(smmu); + u32 reg; + + if (arm_smmu_restore_sec_cfg(smmu)) + return; + + reg = readl_relaxed(impl_def1_base + IMPL_DEF1_MICRO_MMU_CTRL); + reg &= ~MICRO_MMU_CTRL_LOCAL_HALT_REQ; + + if (arm_smmu_is_static_cb(smmu)) { + phys_addr_t impl_def1_base_phys = impl_def1_base - smmu->base + + smmu->phys_addr; + + if (scm_io_write(impl_def1_base_phys + + IMPL_DEF1_MICRO_MMU_CTRL, reg)) + dev_err(smmu->dev, + "scm_io_write fail. SMMU might not be resumed"); + } else { + writel_relaxed(reg, impl_def1_base + IMPL_DEF1_MICRO_MMU_CTRL); + } +} + +static phys_addr_t __arm_smmu_iova_to_phys_hard(struct iommu_domain *domain, + dma_addr_t iova, bool do_halt) +{ struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain); struct arm_smmu_device *smmu = smmu_domain->smmu; struct arm_smmu_cfg *cfg = &smmu_domain->cfg; - struct io_pgtable_ops *ops= smmu_domain->pgtbl_ops; struct device *dev = smmu->dev; void __iomem *cb_base; u32 tmp; u64 phys; unsigned long va; + unsigned long flags; + + if (arm_smmu_enable_clocks(smmu)) + return 0; cb_base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, cfg->cbndx); + spin_lock_irqsave(&smmu->atos_lock, flags); + + if (do_halt && arm_smmu_halt(smmu)) + goto err_unlock; + /* ATS1 registers can only be written atomically */ va = iova & ~0xfffUL; if (smmu->version == ARM_SMMU_V2) @@ -1224,46 +2878,115 @@ if (readl_poll_timeout_atomic(cb_base + ARM_SMMU_CB_ATSR, tmp, !(tmp & ATSR_ACTIVE), 5, 50)) { - dev_err(dev, - "iova to phys timed out on %pad. Falling back to software table walk.\n", - &iova); - return ops->iova_to_phys(ops, iova); + dev_err(dev, "iova to phys timed out\n"); + goto err_resume; } phys = readl_relaxed(cb_base + ARM_SMMU_CB_PAR_LO); phys |= ((u64)readl_relaxed(cb_base + ARM_SMMU_CB_PAR_HI)) << 32; + if (do_halt) + arm_smmu_resume(smmu); + spin_unlock_irqrestore(&smmu->atos_lock, flags); + if (phys & CB_PAR_F) { - dev_err(dev, "translation fault!\n"); + dev_err(dev, "translation fault on %s!\n", dev_name(dev)); dev_err(dev, "PAR = 0x%llx\n", phys); - return 0; + phys = 0; + } else { + phys = (phys & (PHYS_MASK & ~0xfffULL)) | (iova & 0xfff); } - return (phys & GENMASK_ULL(39, 12)) | (iova & 0xfff); + arm_smmu_disable_clocks(smmu); + return phys; + +err_resume: + if (do_halt) + arm_smmu_resume(smmu); +err_unlock: + spin_unlock_irqrestore(&smmu->atos_lock, flags); + arm_smmu_disable_clocks(smmu); + phys = arm_smmu_iova_to_phys(domain, iova); + dev_err(dev, + "iova to phys failed 0x%pa. software table walk result=%pa.\n", + &iova, &phys); + return 0; } -static phys_addr_t arm_smmu_iova_to_phys(struct iommu_domain *domain, +static phys_addr_t arm_smmu_iova_to_phys_hard(struct iommu_domain *domain, dma_addr_t iova) { - phys_addr_t ret; - unsigned long flags; + return __arm_smmu_iova_to_phys_hard(domain, iova, true); +} + +static phys_addr_t arm_smmu_iova_to_phys_hard_no_halt( + struct iommu_domain *domain, dma_addr_t iova) +{ + return __arm_smmu_iova_to_phys_hard(domain, iova, false); +} + +static unsigned long arm_smmu_reg_read(struct iommu_domain *domain, + unsigned long offset) +{ struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain); - struct io_pgtable_ops *ops= smmu_domain->pgtbl_ops; + struct arm_smmu_device *smmu; + struct arm_smmu_cfg *cfg = &smmu_domain->cfg; + void __iomem *cb_base; + unsigned long val; - if (!ops) + if (offset >= SZ_4K) { + pr_err("Invalid offset: 0x%lx\n", offset); return 0; + } - spin_lock_irqsave(&smmu_domain->pgtbl_lock, flags); - if (smmu_domain->smmu->features & ARM_SMMU_FEAT_TRANS_OPS && - smmu_domain->stage == ARM_SMMU_DOMAIN_S1) { - ret = arm_smmu_iova_to_phys_hard(domain, iova); - } else { - ret = ops->iova_to_phys(ops, iova); + mutex_lock(&smmu_domain->init_mutex); + smmu = smmu_domain->smmu; + if (!smmu) { + WARN(1, "Can't read registers of a detached domain\n"); + val = 0; + goto unlock; } - spin_unlock_irqrestore(&smmu_domain->pgtbl_lock, flags); + cb_base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, cfg->cbndx); + if (arm_smmu_enable_clocks(smmu)) { + val = 0; + goto unlock; + } + val = readl_relaxed(cb_base + offset); + arm_smmu_disable_clocks(smmu); - return ret; +unlock: + mutex_unlock(&smmu_domain->init_mutex); + return val; +} + +static void arm_smmu_reg_write(struct iommu_domain *domain, + unsigned long offset, unsigned long val) +{ + struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain); + struct arm_smmu_device *smmu; + struct arm_smmu_cfg *cfg = &smmu_domain->cfg; + void __iomem *cb_base; + + if (offset >= SZ_4K) { + pr_err("Invalid offset: 0x%lx\n", offset); + return; + } + + mutex_lock(&smmu_domain->init_mutex); + smmu = smmu_domain->smmu; + if (!smmu) { + WARN(1, "Can't read registers of a detached domain\n"); + goto unlock; + } + + cb_base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, cfg->cbndx); + if (arm_smmu_enable_clocks(smmu)) + goto unlock; + writel_relaxed(val, cb_base + offset); + arm_smmu_disable_clocks(smmu); +unlock: + mutex_unlock(&smmu_domain->init_mutex); } static bool arm_smmu_capable(enum iommu_cap cap) @@ -1284,12 +3007,6 @@ } } -static int __arm_smmu_get_pci_sid(struct pci_dev *pdev, u16 alias, void *data) -{ - *((u16 *)data) = alias; - return 0; /* Continue walking */ -} - static void __arm_smmu_release_pci_iommudata(void *data) { kfree(data); @@ -1299,8 +3016,9 @@ struct iommu_group *group) { struct arm_smmu_master_cfg *cfg; - u16 sid; - int i; + u32 sid; + int tmp, ret; + struct device *dev = &pdev->dev; cfg = iommu_group_get_iommudata(group); if (!cfg) { @@ -1315,17 +3033,13 @@ if (cfg->num_streamids >= MAX_MASTER_STREAMIDS) return -ENOSPC; - /* - * Assume Stream ID == Requester ID for now. - * We need a way to describe the ID mappings in FDT. - */ - pci_for_each_dma_alias(pdev, __arm_smmu_get_pci_sid, &sid); - for (i = 0; i < cfg->num_streamids; ++i) - if (cfg->streamids[i] == sid) - break; - - /* Avoid duplicate SIDs, as this can lead to SMR conflicts */ - if (i == cfg->num_streamids) + ret = msm_pcie_configure_sid(dev, &sid, &tmp); + if (ret) { + dev_err(dev, + "Couldn't configure SID through PCI-e driver: %d\n", + ret); + return ret; + } cfg->streamids[cfg->num_streamids++] = sid; return 0; @@ -1370,12 +3084,18 @@ struct iommu_group *group; int ret; - if (dev_is_pci(dev)) - group = pci_device_group(dev); - else + /* + * We used to call pci_device_group here for dev_is_pci(dev) + * devices. However, that causes the root complex device to be + * placed in the same group as endpoint devices (and probably puts + * all endpoint devices in the same group as well), which makes + * things tricky in the DMA layer since we don't actually want to + * attach *everybody* in the group when one client calls attach. + * Instead, we'll just allocate a new group for everybody here. + */ group = generic_device_group(dev); - if (IS_ERR(group)) + if (IS_ERR_OR_NULL(group)) return group; if (dev_is_pci(dev)) @@ -1394,15 +3114,120 @@ static int arm_smmu_domain_get_attr(struct iommu_domain *domain, enum iommu_attr attr, void *data) { + int ret; struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain); + mutex_lock(&smmu_domain->init_mutex); switch (attr) { case DOMAIN_ATTR_NESTING: *(int *)data = (smmu_domain->stage == ARM_SMMU_DOMAIN_NESTED); - return 0; - default: + ret = 0; + break; + case DOMAIN_ATTR_SECURE_VMID: + *((int *)data) = smmu_domain->secure_vmid; + ret = 0; + break; + case DOMAIN_ATTR_PT_BASE_ADDR: + *((phys_addr_t *)data) = + smmu_domain->pgtbl_cfg.arm_lpae_s1_cfg.ttbr[0]; + ret = 0; + break; + case DOMAIN_ATTR_CONTEXT_BANK: + /* context bank index isn't valid until we are attached */ + if (smmu_domain->smmu == NULL) + return -ENODEV; + + *((unsigned int *) data) = smmu_domain->cfg.cbndx; + ret = 0; + break; + case DOMAIN_ATTR_TTBR0: { + u64 val; + /* not valid until we are attached */ + if (smmu_domain->smmu == NULL) return -ENODEV; + + val = smmu_domain->pgtbl_cfg.arm_lpae_s1_cfg.ttbr[0]; + if (smmu_domain->cfg.cbar != CBAR_TYPE_S2_TRANS) + val |= (u64)ARM_SMMU_CB_ASID(&smmu_domain->cfg) + << TTBRn_ASID_SHIFT; + *((u64 *)data) = val; + ret = 0; + break; } + case DOMAIN_ATTR_CONTEXTIDR: + /* not valid until attached */ + if (smmu_domain->smmu == NULL) + return -ENODEV; + *((u32 *)data) = smmu_domain->cfg.procid; + ret = 0; + break; + case DOMAIN_ATTR_PROCID: + *((u32 *)data) = smmu_domain->cfg.procid; + ret = 0; + break; + case DOMAIN_ATTR_DYNAMIC: + *((int *)data) = !!(smmu_domain->attributes + & (1 << DOMAIN_ATTR_DYNAMIC)); + ret = 0; + break; + case DOMAIN_ATTR_NON_FATAL_FAULTS: + *((int *)data) = !!(smmu_domain->attributes + & (1 << DOMAIN_ATTR_NON_FATAL_FAULTS)); + ret = 0; + break; + case DOMAIN_ATTR_S1_BYPASS: + *((int *)data) = !!(smmu_domain->attributes + & (1 << DOMAIN_ATTR_S1_BYPASS)); + ret = 0; + break; + case DOMAIN_ATTR_FAST: + *((int *)data) = !!(smmu_domain->attributes + & (1 << DOMAIN_ATTR_FAST)); + ret = 0; + break; + case DOMAIN_ATTR_PGTBL_INFO: { + struct iommu_pgtbl_info *info = data; + + if (!(smmu_domain->attributes & (1 << DOMAIN_ATTR_FAST))) { + ret = -ENODEV; + break; + } + info->pmds = smmu_domain->pgtbl_cfg.av8l_fast_cfg.pmds; + ret = 0; + break; + } + case DOMAIN_ATTR_EARLY_MAP: + *((int *)data) = !!(smmu_domain->attributes + & (1 << DOMAIN_ATTR_EARLY_MAP)); + ret = 0; + break; + case DOMAIN_ATTR_PAGE_TABLE_IS_COHERENT: + if (!smmu_domain->smmu) + return -ENODEV; + *((int *)data) = is_iommu_pt_coherent(smmu_domain); + ret = 0; + break; + case DOMAIN_ATTR_PAGE_TABLE_FORCE_COHERENT: + *((int *)data) = !!(smmu_domain->attributes + & (1 << DOMAIN_ATTR_PAGE_TABLE_FORCE_COHERENT)); + ret = 0; + break; + case DOMAIN_ATTR_ENABLE_TTBR1: + *((int *)data) = !!(smmu_domain->attributes + & (1 << DOMAIN_ATTR_ENABLE_TTBR1)); + ret = 0; + break; + case DOMAIN_ATTR_CB_STALL_DISABLE: + *((int *)data) = !!(smmu_domain->attributes + & (1 << DOMAIN_ATTR_CB_STALL_DISABLE)); + ret = 0; + break; + default: + ret = -ENODEV; + break; + } + mutex_unlock(&smmu_domain->init_mutex); + return ret; } static int arm_smmu_domain_set_attr(struct iommu_domain *domain, @@ -1424,10 +3249,174 @@ smmu_domain->stage = ARM_SMMU_DOMAIN_NESTED; else smmu_domain->stage = ARM_SMMU_DOMAIN_S1; + break; + case DOMAIN_ATTR_SECURE_VMID: + BUG_ON(smmu_domain->secure_vmid != VMID_INVAL); + smmu_domain->secure_vmid = *((int *)data); + break; + case DOMAIN_ATTR_ATOMIC: + { + int atomic_ctx = *((int *)data); + if (atomic_ctx) + smmu_domain->attributes |= (1 << DOMAIN_ATTR_ATOMIC); + else + smmu_domain->attributes &= ~(1 << DOMAIN_ATTR_ATOMIC); + break; + } + case DOMAIN_ATTR_PROCID: + if (smmu_domain->smmu != NULL) { + dev_err(smmu_domain->smmu->dev, + "cannot change procid attribute while attached\n"); + ret = -EBUSY; + break; + } + smmu_domain->cfg.procid = *((u32 *)data); + ret = 0; + break; + case DOMAIN_ATTR_DYNAMIC: { + int dynamic = *((int *)data); + + if (smmu_domain->smmu != NULL) { + dev_err(smmu_domain->smmu->dev, + "cannot change dynamic attribute while attached\n"); + ret = -EBUSY; + break; + } + + if (dynamic) + smmu_domain->attributes |= 1 << DOMAIN_ATTR_DYNAMIC; + else + smmu_domain->attributes &= ~(1 << DOMAIN_ATTR_DYNAMIC); + ret = 0; + break; + } + case DOMAIN_ATTR_CONTEXT_BANK: + /* context bank can't be set while attached */ + if (smmu_domain->smmu != NULL) { + ret = -EBUSY; + break; + } + /* ... and it can only be set for dynamic contexts. */ + if (!(smmu_domain->attributes & (1 << DOMAIN_ATTR_DYNAMIC))) { + ret = -EINVAL; + break; + } + + /* this will be validated during attach */ + smmu_domain->cfg.cbndx = *((unsigned int *)data); + ret = 0; + break; + case DOMAIN_ATTR_NON_FATAL_FAULTS: + smmu_domain->non_fatal_faults = *((int *)data); + ret = 0; + break; + case DOMAIN_ATTR_S1_BYPASS: { + int bypass = *((int *)data); + if (bypass) + smmu_domain->attributes |= 1 << DOMAIN_ATTR_S1_BYPASS; + else + smmu_domain->attributes &= + ~(1 << DOMAIN_ATTR_S1_BYPASS); + + ret = 0; + break; + } + case DOMAIN_ATTR_FAST: + if (*((int *)data)) + smmu_domain->attributes |= 1 << DOMAIN_ATTR_FAST; + ret = 0; + break; + case DOMAIN_ATTR_EARLY_MAP: { + int early_map = *((int *)data); + + ret = 0; + if (early_map) { + smmu_domain->attributes |= + 1 << DOMAIN_ATTR_EARLY_MAP; + } else { + if (smmu_domain->smmu) + ret = arm_smmu_enable_s1_translations( + smmu_domain); + + if (!ret) + smmu_domain->attributes &= + ~(1 << DOMAIN_ATTR_EARLY_MAP); + } + break; + } + case DOMAIN_ATTR_PAGE_TABLE_FORCE_COHERENT: { + int force_coherent = *((int *)data); + + if (smmu_domain->smmu != NULL) { + dev_err(smmu_domain->smmu->dev, + "cannot change force coherent attribute while attached\n"); + ret = -EBUSY; + break; + } + + if (force_coherent) + smmu_domain->attributes |= + 1 << DOMAIN_ATTR_PAGE_TABLE_FORCE_COHERENT; + else + smmu_domain->attributes &= + ~(1 << DOMAIN_ATTR_PAGE_TABLE_FORCE_COHERENT); + + ret = 0; + break; + } + case DOMAIN_ATTR_ENABLE_TTBR1: + if (*((int *)data)) + smmu_domain->attributes |= + 1 << DOMAIN_ATTR_ENABLE_TTBR1; + ret = 0; + break; + case DOMAIN_ATTR_GEOMETRY: { + struct iommu_domain_geometry *geometry = + (struct iommu_domain_geometry *)data; + + if (smmu_domain->smmu != NULL) { + dev_err(smmu_domain->smmu->dev, + "cannot set geometry attribute while attached\n"); + ret = -EBUSY; + break; + } + + if (geometry->aperture_start >= SZ_1G * 4ULL || + geometry->aperture_end >= SZ_1G * 4ULL) { + pr_err("fastmap does not support IOVAs >= 4GB\n"); + ret = -EINVAL; + break; + } + if (smmu_domain->attributes + & (1 << DOMAIN_ATTR_GEOMETRY)) { + if (geometry->aperture_start + < domain->geometry.aperture_start) + domain->geometry.aperture_start = + geometry->aperture_start; + + if (geometry->aperture_end + > domain->geometry.aperture_end) + domain->geometry.aperture_end = + geometry->aperture_end; + } else { + smmu_domain->attributes |= 1 << DOMAIN_ATTR_GEOMETRY; + domain->geometry.aperture_start = + geometry->aperture_start; + domain->geometry.aperture_end = geometry->aperture_end; + } + ret = 0; + break; + } + case DOMAIN_ATTR_CB_STALL_DISABLE: + if (*((int *)data)) + smmu_domain->attributes |= + 1 << DOMAIN_ATTR_CB_STALL_DISABLE; + ret = 0; break; default: ret = -ENODEV; + break; } out_unlock: @@ -1435,6 +3424,66 @@ return ret; } + +static int arm_smmu_enable_s1_translations(struct arm_smmu_domain *smmu_domain) +{ + struct arm_smmu_cfg *cfg = &smmu_domain->cfg; + struct arm_smmu_device *smmu = smmu_domain->smmu; + void __iomem *cb_base; + u32 reg; + int ret; + + cb_base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, cfg->cbndx); + ret = arm_smmu_enable_clocks(smmu); + if (ret) + return ret; + + reg = readl_relaxed(cb_base + ARM_SMMU_CB_SCTLR); + reg |= SCTLR_M; + + writel_relaxed(reg, cb_base + ARM_SMMU_CB_SCTLR); + arm_smmu_disable_clocks(smmu); + return ret; +} + +static int arm_smmu_dma_supported(struct iommu_domain *domain, + struct device *dev, u64 mask) +{ + struct arm_smmu_device *smmu; + struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain); + int ret; + + mutex_lock(&smmu_domain->init_mutex); + smmu = smmu_domain->smmu; + if (!smmu) { + dev_err(dev, + "Can't call dma_supported on an unattached domain\n"); + mutex_unlock(&smmu_domain->init_mutex); + return 0; + } + + ret = ((1ULL << smmu->va_size) - 1) <= mask ? 0 : 1; + mutex_unlock(&smmu_domain->init_mutex); + return ret; +} + +static unsigned long arm_smmu_get_pgsize_bitmap(struct iommu_domain *domain) +{ + struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain); + + /* + * if someone is calling map before attach just return the + * supported page sizes for the hardware itself. + */ + if (!smmu_domain->pgtbl_cfg.pgsize_bitmap) + return arm_smmu_ops.pgsize_bitmap; + /* + * otherwise return the page sizes supported by this specific page + * table configuration + */ + return smmu_domain->pgtbl_cfg.pgsize_bitmap; +} + static struct iommu_ops arm_smmu_ops = { .capable = arm_smmu_capable, .domain_alloc = arm_smmu_domain_alloc, @@ -1443,14 +3492,25 @@ .detach_dev = arm_smmu_detach_dev, .map = arm_smmu_map, .unmap = arm_smmu_unmap, - .map_sg = default_iommu_map_sg, + .map_sg = arm_smmu_map_sg, .iova_to_phys = arm_smmu_iova_to_phys, + .iova_to_phys_hard = arm_smmu_iova_to_phys_hard, .add_device = arm_smmu_add_device, .remove_device = arm_smmu_remove_device, .device_group = arm_smmu_device_group, .domain_get_attr = arm_smmu_domain_get_attr, .domain_set_attr = arm_smmu_domain_set_attr, .pgsize_bitmap = -1UL, /* Restricted during device attach */ + .get_pgsize_bitmap = arm_smmu_get_pgsize_bitmap, + .dma_supported = arm_smmu_dma_supported, + .trigger_fault = arm_smmu_trigger_fault, + .reg_read = arm_smmu_reg_read, + .reg_write = arm_smmu_reg_write, + .tlbi_domain = arm_smmu_tlbi_domain, + .enable_config_clocks = arm_smmu_enable_config_clocks, + .disable_config_clocks = arm_smmu_disable_config_clocks, + .is_iova_coherent = arm_smmu_is_iova_coherent, + .iova_to_pte = arm_smmu_iova_to_pte, }; static void arm_smmu_device_reset(struct arm_smmu_device *smmu) @@ -1464,9 +3524,11 @@ reg = readl_relaxed(ARM_SMMU_GR0_NS(smmu) + ARM_SMMU_GR0_sGFSR); writel(reg, ARM_SMMU_GR0_NS(smmu) + ARM_SMMU_GR0_sGFSR); + if (!(smmu->options & ARM_SMMU_OPT_SKIP_INIT)) { /* Mark all SMRn as invalid and all S2CRn as bypass */ for (i = 0; i < smmu->num_mapping_groups; ++i) { - writel_relaxed(0, gr0_base + ARM_SMMU_GR0_SMR(i)); + writel_relaxed(0, + gr0_base + ARM_SMMU_GR0_SMR(i)); writel_relaxed(S2CR_TYPE_BYPASS, gr0_base + ARM_SMMU_GR0_S2CR(i)); } @@ -1477,6 +3539,7 @@ writel_relaxed(0, cb_base + ARM_SMMU_CB_SCTLR); writel_relaxed(FSR_FAULT, cb_base + ARM_SMMU_CB_FSR); } + } /* Invalidate the TLB, just in case */ writel_relaxed(0, gr0_base + ARM_SMMU_GR0_TLBIALLH); @@ -1490,8 +3553,11 @@ /* Disable TLB broadcasting. */ reg |= (sCR0_VMIDPNE | sCR0_PTM); - /* Enable client access, but bypass when no mapping is found */ - reg &= ~(sCR0_CLIENTPD | sCR0_USFCFG); + /* Enable client access */ + reg &= ~sCR0_CLIENTPD; + + /* Raise an unidentified stream fault on unmapped access */ + reg |= sCR0_USFCFG; /* Disable forced broadcasting */ reg &= ~sCR0_FB; @@ -1523,6 +3589,203 @@ } } +static int regulator_notifier(struct notifier_block *nb, + unsigned long event, void *data) +{ + int ret = 0; + struct arm_smmu_device *smmu = container_of(nb, + struct arm_smmu_device, regulator_nb); + + /* Ignore EVENT DISABLE as no clocks could be turned on + * at this notification. + */ + if (event != REGULATOR_EVENT_PRE_DISABLE && + event != REGULATOR_EVENT_ENABLE) + return NOTIFY_OK; + + ret = arm_smmu_prepare_clocks(smmu); + if (ret) + goto out; + + ret = arm_smmu_enable_clocks_atomic(smmu); + if (ret) + goto unprepare_clock; + + if (event == REGULATOR_EVENT_PRE_DISABLE) + arm_smmu_halt(smmu); + else if (event == REGULATOR_EVENT_ENABLE) + arm_smmu_resume(smmu); + + arm_smmu_disable_clocks_atomic(smmu); +unprepare_clock: + arm_smmu_unprepare_clocks(smmu); +out: + return NOTIFY_OK; +} + +static int register_regulator_notifier(struct arm_smmu_device *smmu) +{ + struct device *dev = smmu->dev; + int ret = 0; + + if (smmu->options & ARM_SMMU_OPT_HALT) { + smmu->regulator_nb.notifier_call = regulator_notifier; + ret = regulator_register_notifier(smmu->gdsc, + &smmu->regulator_nb); + + if (ret) + dev_err(dev, "Regulator notifier request failed\n"); + } + return ret; +} + +static int arm_smmu_init_regulators(struct arm_smmu_device *smmu) +{ + struct device *dev = smmu->dev; + + if (!of_get_property(dev->of_node, "vdd-supply", NULL)) + return 0; + + if (!of_property_read_u32(dev->of_node, + "qcom,deferred-regulator-disable-delay", + &(smmu->regulator_defer))) + dev_info(dev, "regulator defer delay %d\n", + smmu->regulator_defer); + + smmu->gdsc = devm_regulator_get(dev, "vdd"); + if (IS_ERR(smmu->gdsc)) + return PTR_ERR(smmu->gdsc); + + return 0; +} + +static int arm_smmu_init_clocks(struct arm_smmu_device *smmu) +{ + const char *cname; + struct property *prop; + int i; + struct device *dev = smmu->dev; + + smmu->num_clocks = + of_property_count_strings(dev->of_node, "clock-names"); + + if (smmu->num_clocks < 1) { + smmu->num_clocks = 0; + return 0; + } + + smmu->clocks = devm_kzalloc( + dev, sizeof(*smmu->clocks) * smmu->num_clocks, + GFP_KERNEL); + + if (!smmu->clocks) { + dev_err(dev, + "Failed to allocate memory for clocks\n"); + return -ENODEV; + } + + i = 0; + of_property_for_each_string(dev->of_node, "clock-names", + prop, cname) { + struct clk *c = devm_clk_get(dev, cname); + if (IS_ERR(c)) { + dev_err(dev, "Couldn't get clock: %s", + cname); + return PTR_ERR(c); + } + + if (clk_get_rate(c) == 0) { + long rate = clk_round_rate(c, 1000); + clk_set_rate(c, rate); + } + + smmu->clocks[i] = c; + + ++i; + } + return 0; +} + +static int arm_smmu_init_bus_scaling(struct platform_device *pdev, + struct arm_smmu_device *smmu) +{ + if (!of_find_property(pdev->dev.of_node, "qcom,msm-bus,name", NULL)) { + dev_dbg(&pdev->dev, "No bus scaling info\n"); + return 0; + } + + smmu->bus_pdata = msm_bus_cl_get_pdata(pdev); + if (!smmu->bus_pdata) { + dev_err(&pdev->dev, "Unable to read bus-scaling from DT\n"); + return -EINVAL; + } + + smmu->bus_client = msm_bus_scale_register_client(smmu->bus_pdata); + if (!smmu->bus_client) { + dev_err(&pdev->dev, "Bus client registration failed\n"); + return -EINVAL; + } + + return 0; +} + +static void arm_smmu_exit_bus_scaling(struct arm_smmu_device *smmu) +{ + if (smmu->bus_client) + msm_bus_scale_unregister_client(smmu->bus_client); + if (smmu->bus_pdata) + msm_bus_cl_clear_pdata(smmu->bus_pdata); + + smmu->bus_client = 0; + smmu->bus_pdata = NULL; +} + +static int arm_smmu_parse_impl_def_registers(struct arm_smmu_device *smmu) +{ + struct device *dev = smmu->dev; + int i, ntuples, ret; + u32 *tuples; + struct arm_smmu_impl_def_reg *regs, *regit; + + if (!of_find_property(dev->of_node, "attach-impl-defs", &ntuples)) + return 0; + + ntuples /= sizeof(u32); + if (ntuples % 2) { + dev_err(dev, + "Invalid number of attach-impl-defs registers: %d\n", + ntuples); + return -EINVAL; + } + + regs = devm_kmalloc( + dev, sizeof(*smmu->impl_def_attach_registers) * ntuples, + GFP_KERNEL); + if (!regs) + return -ENOMEM; + + tuples = devm_kmalloc(dev, sizeof(u32) * ntuples * 2, GFP_KERNEL); + if (!tuples) + return -ENOMEM; + + ret = of_property_read_u32_array(dev->of_node, "attach-impl-defs", + tuples, ntuples); + if (ret) + return ret; + + for (i = 0, regit = regs; i < ntuples; i += 2, ++regit) { + regit->offset = tuples[i]; + regit->value = tuples[i + 1]; + } + + devm_kfree(dev, tuples); + + smmu->impl_def_attach_registers = regs; + smmu->num_impl_def_attach_registers = ntuples / 2; + + return 0; +} + static int arm_smmu_device_cfg_probe(struct arm_smmu_device *smmu) { unsigned long size; @@ -1530,8 +3793,11 @@ u32 id; bool cttw_dt, cttw_reg; - dev_notice(smmu->dev, "probing hardware configuration...\n"); - dev_notice(smmu->dev, "SMMUv%d with:\n", smmu->version); + if (arm_smmu_restore_sec_cfg(smmu)) + return -ENODEV; + + dev_dbg(smmu->dev, "probing hardware configuration...\n"); + dev_dbg(smmu->dev, "SMMUv%d with:\n", smmu->version); /* ID0 */ id = readl_relaxed(gr0_base + ARM_SMMU_GR0_ID0); @@ -1544,28 +3810,28 @@ if (id & ID0_S1TS) { smmu->features |= ARM_SMMU_FEAT_TRANS_S1; - dev_notice(smmu->dev, "\tstage 1 translation\n"); + dev_dbg(smmu->dev, "\tstage 1 translation\n"); } if (id & ID0_S2TS) { smmu->features |= ARM_SMMU_FEAT_TRANS_S2; - dev_notice(smmu->dev, "\tstage 2 translation\n"); + dev_dbg(smmu->dev, "\tstage 2 translation\n"); } if (id & ID0_NTS) { smmu->features |= ARM_SMMU_FEAT_TRANS_NESTED; - dev_notice(smmu->dev, "\tnested translation\n"); + dev_dbg(smmu->dev, "\tnested translation\n"); } if (!(smmu->features & (ARM_SMMU_FEAT_TRANS_S1 | ARM_SMMU_FEAT_TRANS_S2))) { - dev_err(smmu->dev, "\tno translation support!\n"); + dev_err(smmu->dev, "\tno translation support (id0=%x)!\n", id); return -ENODEV; } if ((id & ID0_S1TS) && ((smmu->version == 1) || !(id & ID0_ATOSNS))) { smmu->features |= ARM_SMMU_FEAT_TRANS_OPS; - dev_notice(smmu->dev, "\taddress translation ops\n"); + dev_dbg(smmu->dev, "\taddress translation ops\n"); } /* @@ -1579,14 +3845,14 @@ if (cttw_dt) smmu->features |= ARM_SMMU_FEAT_COHERENT_WALK; if (cttw_dt || cttw_reg) - dev_notice(smmu->dev, "\t%scoherent table walk\n", + dev_dbg(smmu->dev, "\t%scoherent table walk\n", cttw_dt ? "" : "non-"); if (cttw_dt != cttw_reg) - dev_notice(smmu->dev, + dev_dbg(smmu->dev, "\t(IDR0.CTTW overridden by dma-coherent property)\n"); if (id & ID0_SMS) { - u32 smr, sid, mask; + u32 smr, sid, mask = 0; smmu->features |= ARM_SMMU_FEAT_STREAM_MATCH; smmu->num_mapping_groups = (id >> ID0_NUMSMRG_SHIFT) & @@ -1597,6 +3863,7 @@ return -ENODEV; } + if (!(smmu->options & ARM_SMMU_OPT_NO_SMR_CHECK)) { smr = SMR_MASK_MASK << SMR_MASK_SHIFT; smr |= (SMR_ID_MASK << SMR_ID_SHIFT); writel_relaxed(smr, gr0_base + ARM_SMMU_GR0_SMR(0)); @@ -1610,8 +3877,9 @@ mask, sid); return -ENODEV; } + } - dev_notice(smmu->dev, + dev_dbg(smmu->dev, "\tstream matching with %u register groups, mask 0x%x", smmu->num_mapping_groups, mask); } else { @@ -1637,7 +3905,7 @@ dev_err(smmu->dev, "impossible number of S2 context banks!\n"); return -ENODEV; } - dev_notice(smmu->dev, "\t%u context banks (%u stage-2 only)\n", + dev_dbg(smmu->dev, "\t%u context banks (%u stage-2 only)\n", smmu->num_context_banks, smmu->num_s2_context_banks); /* ID2 */ @@ -1662,11 +3930,13 @@ smmu->va_size = smmu->ipa_size; size = SZ_4K | SZ_2M | SZ_1G; } else { - size = (id >> ID2_UBS_SHIFT) & ID2_UBS_MASK; - smmu->va_size = arm_smmu_id_size_to_bits(size); + smmu->ubs = (id >> ID2_UBS_SHIFT) & ID2_UBS_MASK; + + smmu->va_size = arm_smmu_id_size_to_bits(smmu->ubs); #ifndef CONFIG_64BIT smmu->va_size = min(32UL, smmu->va_size); #endif + smmu->va_size = min(39UL, smmu->va_size); size = 0; if (id & ID2_PTFS_4K) size |= SZ_4K | SZ_2M | SZ_1G; @@ -1677,25 +3947,82 @@ } arm_smmu_ops.pgsize_bitmap &= size; - dev_notice(smmu->dev, "\tSupported page sizes: 0x%08lx\n", size); + dev_dbg(smmu->dev, "\tSupported page sizes: 0x%08lx\n", size); if (smmu->features & ARM_SMMU_FEAT_TRANS_S1) - dev_notice(smmu->dev, "\tStage-1: %lu-bit VA -> %lu-bit IPA\n", + dev_dbg(smmu->dev, "\tStage-1: %lu-bit VA -> %lu-bit IPA\n", smmu->va_size, smmu->ipa_size); if (smmu->features & ARM_SMMU_FEAT_TRANS_S2) - dev_notice(smmu->dev, "\tStage-2: %lu-bit IPA -> %lu-bit PA\n", + dev_dbg(smmu->dev, "\tStage-2: %lu-bit IPA -> %lu-bit PA\n", smmu->ipa_size, smmu->pa_size); return 0; } +static int arm_smmu_add_static_cbndx(struct arm_smmu_device *smmu, int sid, + int smr_idx) +{ + void __iomem *gr0_base; + u32 s2cr_reg; + struct static_cbndx_entry *entry; + + entry = devm_kzalloc(smmu->dev, sizeof(*entry), GFP_KERNEL); + if (!entry) + return -ENOMEM; + + gr0_base = ARM_SMMU_GR0(smmu); + s2cr_reg = readl_relaxed(gr0_base + ARM_SMMU_GR0_S2CR(smr_idx)); + entry->type = (s2cr_reg >> S2CR_TYPE_SHIFT) & S2CR_TYPE_MASK; + entry->smr_idx = smr_idx; + entry->sid = sid; + + if (entry->type == TYPE_TRANS) { + entry->cbndx = (s2cr_reg >> S2CR_CBNDX_SHIFT) & + S2CR_CBNDX_MASK; + __arm_smmu_set_bitmap(smmu->context_map, entry->cbndx); + pr_debug("Static context bank: smr:%d, sid:%d, cbndx:%d\n", + smr_idx, sid, entry->cbndx); + } + __arm_smmu_set_bitmap(smmu->smr_map, smr_idx); + list_add(&entry->list, &smmu->static_cbndx_list); + + return 0; +} + +static int arm_smmu_init_static_cbndx_list(struct arm_smmu_device *smmu) +{ + int i, ret = 0; + void __iomem *gr0_base = ARM_SMMU_GR0(smmu); + + for (i = 0; i < smmu->num_mapping_groups; ++i) { + u32 smr_reg, sid; + + smr_reg = readl_relaxed(gr0_base + ARM_SMMU_GR0_SMR(i)); + if (smr_reg & SMR_VALID) { + u32 smr_mask = (smr_reg >> SMR_MASK_SHIFT) & + SMR_MASK_MASK; + + if (smr_mask != 0) + dev_warn(smmu->dev, + "Static smr mask not supported\n"); + sid = ((smr_reg >> SMR_ID_SHIFT) & SMR_ID_MASK); + ret = arm_smmu_add_static_cbndx(smmu, sid, i); + if (ret) + break; + } + } + + return ret; +} + static const struct of_device_id arm_smmu_of_match[] = { { .compatible = "arm,smmu-v1", .data = (void *)ARM_SMMU_V1 }, { .compatible = "arm,smmu-v2", .data = (void *)ARM_SMMU_V2 }, { .compatible = "arm,mmu-400", .data = (void *)ARM_SMMU_V1 }, { .compatible = "arm,mmu-401", .data = (void *)ARM_SMMU_V1 }, { .compatible = "arm,mmu-500", .data = (void *)ARM_SMMU_V2 }, + { .compatible = "qcom,smmu-v2", .data = (void *)ARM_SMMU_V2 }, { }, }; MODULE_DEVICE_TABLE(of, arm_smmu_of_match); @@ -1707,7 +4034,6 @@ struct arm_smmu_device *smmu; struct device *dev = &pdev->dev; struct rb_node *node; - struct of_phandle_args masterspec; int num_irqs, i, err; smmu = devm_kzalloc(dev, sizeof(*smmu), GFP_KERNEL); @@ -1716,11 +4042,19 @@ return -ENOMEM; } smmu->dev = dev; + mutex_init(&smmu->attach_lock); + mutex_init(&smmu->power_lock); + spin_lock_init(&smmu->atos_lock); + spin_lock_init(&smmu->clock_refs_lock); + INIT_LIST_HEAD(&smmu->static_cbndx_list); of_id = of_match_node(arm_smmu_of_match, dev->of_node); + if (!of_id) + return -ENODEV; smmu->version = (enum arm_smmu_arch_version)of_id->data; res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + smmu->phys_addr = res->start; smmu->base = devm_ioremap_resource(dev, res); if (IS_ERR(smmu->base)) return PTR_ERR(smmu->base); @@ -1762,43 +4096,62 @@ smmu->irqs[i] = irq; } - err = arm_smmu_device_cfg_probe(smmu); + i = 0; + + err = arm_smmu_parse_impl_def_registers(smmu); if (err) - return err; + goto out; - i = 0; + err = arm_smmu_init_regulators(smmu); + if (err) + goto out; + + err = arm_smmu_init_clocks(smmu); + if (err) + goto out; + + err = arm_smmu_init_bus_scaling(pdev, smmu); + if (err) + goto out; + + parse_driver_options(smmu); + + err = arm_smmu_enable_clocks(smmu); + if (err) + goto out; + + /* No probe deferral occurred! Proceed with iommu property parsing. */ smmu->masters = RB_ROOT; - while (!of_parse_phandle_with_args(dev->of_node, "mmu-masters", - "#stream-id-cells", i, - &masterspec)) { - err = register_smmu_master(smmu, dev, &masterspec); - if (err) { - dev_err(dev, "failed to add master %s\n", - masterspec.np->name); + err = arm_smmu_parse_iommus_properties(smmu); + if (err) goto out_put_masters; - } - i++; - } - dev_notice(dev, "registered %d master devices\n", i); + smmu->sec_id = msm_dev_to_device_id(dev); + err = arm_smmu_device_cfg_probe(smmu); + if (!err) + err = arm_smmu_init_static_cbndx_list(smmu); - parse_driver_options(smmu); + arm_smmu_disable_clocks(smmu); + if (err) + goto out_put_masters; + + if (of_device_is_compatible(dev->of_node, "qcom,smmu-v2")) + smmu->model = SMMU_MODEL_QCOM_V2; if (smmu->version > ARM_SMMU_V1 && smmu->num_context_banks != smmu->num_context_irqs) { dev_err(dev, - "found only %d context interrupt(s) but %d required\n", - smmu->num_context_irqs, smmu->num_context_banks); - err = -ENODEV; - goto out_put_masters; + "found %d context interrupt(s) but have %d context banks. assuming %d context interrupts.\n", + smmu->num_context_irqs, smmu->num_context_banks, + smmu->num_context_banks); + smmu->num_context_irqs = smmu->num_context_banks; } for (i = 0; i < smmu->num_global_irqs; ++i) { - err = request_irq(smmu->irqs[i], - arm_smmu_global_fault, - IRQF_SHARED, - "arm-smmu global fault", - smmu); + err = request_threaded_irq(smmu->irqs[i], + NULL, arm_smmu_global_fault, + IRQF_ONESHOT | IRQF_SHARED, + "arm-smmu global fault", smmu); if (err) { dev_err(dev, "failed to request global IRQ %d (%u)\n", i, smmu->irqs[i]); @@ -1806,12 +4159,17 @@ } } + idr_init(&smmu->asid_idr); + + err = register_regulator_notifier(smmu); + if (err) + goto out_free_irqs; + INIT_LIST_HEAD(&smmu->list); spin_lock(&arm_smmu_devices_lock); list_add(&smmu->list, &arm_smmu_devices); spin_unlock(&arm_smmu_devices_lock); - arm_smmu_device_reset(smmu); return 0; out_free_irqs: @@ -1819,12 +4177,13 @@ free_irq(smmu->irqs[i], smmu); out_put_masters: + arm_smmu_exit_bus_scaling(smmu); for (node = rb_first(&smmu->masters); node; node = rb_next(node)) { struct arm_smmu_master *master = container_of(node, struct arm_smmu_master, node); of_node_put(master->of_node); } - +out: return err; } @@ -1860,11 +4219,73 @@ for (i = 0; i < smmu->num_global_irqs; ++i) free_irq(smmu->irqs[i], smmu); - /* Turn the thing off */ - writel(sCR0_CLIENTPD, ARM_SMMU_GR0_NS(smmu) + ARM_SMMU_GR0_sCR0); + mutex_lock(&smmu->attach_lock); + idr_destroy(&smmu->asid_idr); + /* + * If all devices weren't detached for some reason, we're + * still powered on. Power off now. + */ + if (smmu->attach_count) + arm_smmu_power_off(smmu); + mutex_unlock(&smmu->attach_lock); + + arm_smmu_exit_bus_scaling(smmu); + return 0; } +static void arm_smmu_free_master_nodes(void) +{ + struct arm_iommus_node *node, *nex; + struct arm_iommus_spec *entry, *n; + + list_for_each_entry_safe(node, nex, &iommus_nodes, list) { + list_for_each_entry_safe(entry, n, + &node->iommuspec_list, list) { + list_del(&entry->list); + kfree(entry); + } + list_del(&node->list); + kfree(node); + } +} + +static int arm_smmu_get_master_nodes(void) +{ + struct arm_iommus_node *node; + struct device_node *master; + struct of_phandle_args iommuspec; + struct arm_iommus_spec *entry; + + for_each_node_with_property(master, "iommus") { + int arg_ind = 0; + + node = kzalloc(sizeof(*node), GFP_KERNEL); + if (!node) + goto release_memory; + node->master = master; + list_add(&node->list, &iommus_nodes); + + INIT_LIST_HEAD(&node->iommuspec_list); + + while (!of_parse_phandle_with_args(master, "iommus", + "#iommu-cells", arg_ind, &iommuspec)) { + entry = kzalloc(sizeof(*entry), GFP_KERNEL); + if (!entry) + goto release_memory; + entry->iommu_spec = iommuspec; + list_add(&entry->list, &node->iommuspec_list); + arg_ind++; + } + } + + return 0; + +release_memory: + arm_smmu_free_master_nodes(); + return -ENOMEM; +} + static struct platform_driver arm_smmu_driver = { .driver = { .name = "arm-smmu", @@ -1890,10 +4311,15 @@ of_node_put(np); - ret = platform_driver_register(&arm_smmu_driver); + ret = arm_smmu_get_master_nodes(); if (ret) return ret; + ret = platform_driver_register(&arm_smmu_driver); + if (ret) { + arm_smmu_free_master_nodes(); + return ret; + } /* Oh, for a proper bus abstraction */ if (!iommu_present(&platform_bus_type)) bus_set_iommu(&platform_bus_type, &arm_smmu_ops); diff -ruw linux-4.4.115/drivers/iommu/iommu.c linux-4.4.115-fbx/drivers/iommu/iommu.c --- linux-4.4.115/drivers/iommu/iommu.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/iommu/iommu.c 2019-01-22 16:16:24.063251478 +0100 @@ -31,8 +31,11 @@ #include #include #include +#include #include +#include "iommu-debug.h" + static struct kset *iommu_group_kset; static struct ida iommu_group_ida; static struct mutex iommu_group_mutex; @@ -1034,6 +1037,8 @@ bool iommu_present(struct bus_type *bus) { + if (!bus) + return false; return bus->iommu_ops != NULL; } EXPORT_SYMBOL_GPL(iommu_present); @@ -1070,6 +1075,45 @@ } EXPORT_SYMBOL_GPL(iommu_set_fault_handler); +/** + * iommu_trigger_fault() - trigger an IOMMU fault + * @domain: iommu domain + * + * Triggers a fault on the device to which this domain is attached. + * + * This function should only be used for debugging purposes, for obvious + * reasons. + */ +void iommu_trigger_fault(struct iommu_domain *domain, unsigned long flags) +{ + if (domain->ops->trigger_fault) + domain->ops->trigger_fault(domain, flags); +} + +/** + * iommu_reg_read() - read an IOMMU register + * + * Reads the IOMMU register at the given offset. + */ +unsigned long iommu_reg_read(struct iommu_domain *domain, unsigned long offset) +{ + if (domain->ops->reg_read) + return domain->ops->reg_read(domain, offset); + return 0; +} + +/** + * iommu_reg_write() - write an IOMMU register + * + * Writes the given value to the IOMMU register at the given offset. + */ +void iommu_reg_write(struct iommu_domain *domain, unsigned long offset, + unsigned long val) +{ + if (domain->ops->reg_write) + domain->ops->reg_write(domain, offset, val); +} + static struct iommu_domain *__iommu_domain_alloc(struct bus_type *bus, unsigned type) { @@ -1096,6 +1140,7 @@ void iommu_domain_free(struct iommu_domain *domain) { + iommu_debug_domain_remove(domain); domain->ops->domain_free(domain); } EXPORT_SYMBOL_GPL(iommu_domain_free); @@ -1108,8 +1153,10 @@ return -ENODEV; ret = domain->ops->attach_dev(domain, dev); - if (!ret) + if (!ret) { trace_attach_device_to_domain(dev); + iommu_debug_attach_device(domain, dev); + } return ret; } @@ -1288,7 +1335,39 @@ } EXPORT_SYMBOL_GPL(iommu_iova_to_phys); -static size_t iommu_pgsize(struct iommu_domain *domain, +phys_addr_t iommu_iova_to_phys_hard(struct iommu_domain *domain, + dma_addr_t iova) +{ + if (unlikely(domain->ops->iova_to_phys_hard == NULL)) + return 0; + + return domain->ops->iova_to_phys_hard(domain, iova); +} + +uint64_t iommu_iova_to_pte(struct iommu_domain *domain, + dma_addr_t iova) +{ + if (unlikely(domain->ops->iova_to_pte == NULL)) + return 0; + + return domain->ops->iova_to_pte(domain, iova); +} + +bool iommu_is_iova_coherent(struct iommu_domain *domain, dma_addr_t iova) +{ + if (unlikely(domain->ops->is_iova_coherent == NULL)) + return 0; + + return domain->ops->is_iova_coherent(domain, iova); +} +static unsigned long iommu_get_pgsize_bitmap(struct iommu_domain *domain) +{ + if (domain->ops->get_pgsize_bitmap) + return domain->ops->get_pgsize_bitmap(domain); + return domain->ops->pgsize_bitmap; +} + +size_t iommu_pgsize(unsigned long pgsize_bitmap, unsigned long addr_merge, size_t size) { unsigned int pgsize_idx; @@ -1308,10 +1387,14 @@ pgsize = (1UL << (pgsize_idx + 1)) - 1; /* throw away page sizes not supported by the hardware */ - pgsize &= domain->ops->pgsize_bitmap; + pgsize &= pgsize_bitmap; /* make sure we're still sane */ - BUG_ON(!pgsize); + if (!pgsize) { + pr_err("invalid pgsize/addr/size! 0x%lx 0x%lx 0x%zx\n", + pgsize_bitmap, addr_merge, size); + BUG(); + } /* pick the biggest page */ pgsize_idx = __fls(pgsize); @@ -1323,20 +1406,25 @@ int iommu_map(struct iommu_domain *domain, unsigned long iova, phys_addr_t paddr, size_t size, int prot) { - unsigned long orig_iova = iova; + unsigned long orig_iova = iova, pgsize_bitmap; unsigned int min_pagesz; size_t orig_size = size; int ret = 0; + trace_map_start(iova, paddr, size); if (unlikely(domain->ops->map == NULL || - domain->ops->pgsize_bitmap == 0UL)) + (domain->ops->pgsize_bitmap == 0UL && + !domain->ops->get_pgsize_bitmap))) { + trace_map_end(iova, paddr, size); return -ENODEV; + } if (unlikely(!(domain->type & __IOMMU_DOMAIN_PAGING))) return -EINVAL; + pgsize_bitmap = iommu_get_pgsize_bitmap(domain); /* find out the minimum page size supported */ - min_pagesz = 1 << __ffs(domain->ops->pgsize_bitmap); + min_pagesz = 1 << __ffs(pgsize_bitmap); /* * both the virtual address and the physical one, as well as @@ -1346,13 +1434,14 @@ if (!IS_ALIGNED(iova | paddr | size, min_pagesz)) { pr_err("unaligned: iova 0x%lx pa %pa size 0x%zx min_pagesz 0x%x\n", iova, &paddr, size, min_pagesz); + trace_map_end(iova, paddr, size); return -EINVAL; } pr_debug("map: iova 0x%lx pa %pa size 0x%zx\n", iova, &paddr, size); while (size) { - size_t pgsize = iommu_pgsize(domain, iova | paddr, size); + size_t pgsize = iommu_pgsize(pgsize_bitmap, iova | paddr, size); pr_debug("mapping: iova 0x%lx pa %pa pgsize 0x%zx\n", iova, &paddr, pgsize); @@ -1372,6 +1461,7 @@ else trace_map(orig_iova, paddr, orig_size); + trace_map_end(iova, paddr, size); return ret; } EXPORT_SYMBOL_GPL(iommu_map); @@ -1382,15 +1472,21 @@ unsigned int min_pagesz; unsigned long orig_iova = iova; + trace_unmap_start(iova, 0, size); if (unlikely(domain->ops->unmap == NULL || - domain->ops->pgsize_bitmap == 0UL)) + (domain->ops->pgsize_bitmap == 0UL && + !domain->ops->get_pgsize_bitmap))) { + trace_unmap_end(iova, 0, size); return -ENODEV; + } - if (unlikely(!(domain->type & __IOMMU_DOMAIN_PAGING))) + if (unlikely(!(domain->type & __IOMMU_DOMAIN_PAGING))) { + trace_unmap_end(iova, 0, size); return -EINVAL; + } /* find out the minimum page size supported */ - min_pagesz = 1 << __ffs(domain->ops->pgsize_bitmap); + min_pagesz = 1 << __ffs(iommu_get_pgsize_bitmap(domain)); /* * The virtual address, as well as the size of the mapping, must be @@ -1400,6 +1496,7 @@ if (!IS_ALIGNED(iova | size, min_pagesz)) { pr_err("unaligned: iova 0x%lx size 0x%zx min_pagesz 0x%x\n", iova, size, min_pagesz); + trace_unmap_end(iova, 0, size); return -EINVAL; } @@ -1410,9 +1507,9 @@ * or we hit an area that isn't mapped. */ while (unmapped < size) { - size_t pgsize = iommu_pgsize(domain, iova, size - unmapped); + size_t left = size - unmapped; - unmapped_page = domain->ops->unmap(domain, iova, pgsize); + unmapped_page = domain->ops->unmap(domain, iova, left); if (!unmapped_page) break; @@ -1424,6 +1521,7 @@ } trace_unmap(orig_iova, size, unmapped); + trace_unmap_end(orig_iova, 0, size); return unmapped; } EXPORT_SYMBOL_GPL(iommu_unmap); @@ -1435,11 +1533,14 @@ size_t mapped = 0; unsigned int i, min_pagesz; int ret; + unsigned long pgsize_bitmap; - if (unlikely(domain->ops->pgsize_bitmap == 0UL)) + if (unlikely(domain->ops->pgsize_bitmap == 0UL && + !domain->ops->get_pgsize_bitmap)) return 0; - min_pagesz = 1 << __ffs(domain->ops->pgsize_bitmap); + pgsize_bitmap = iommu_get_pgsize_bitmap(domain); + min_pagesz = 1 << __ffs(pgsize_bitmap); for_each_sg(sg, s, nents, i) { phys_addr_t phys = page_to_phys(sg_page(s)) + s->offset; @@ -1471,6 +1572,20 @@ } EXPORT_SYMBOL_GPL(default_iommu_map_sg); +/* DEPRECATED */ +int iommu_map_range(struct iommu_domain *domain, unsigned int iova, + struct scatterlist *sg, unsigned int len, int opt) +{ + return -ENODEV; +} + +/* DEPRECATED */ +int iommu_unmap_range(struct iommu_domain *domain, unsigned int iova, + unsigned int len) +{ + return -ENODEV; +} + int iommu_domain_window_enable(struct iommu_domain *domain, u32 wnd_nr, phys_addr_t paddr, u64 size, int prot) { @@ -1491,6 +1606,8 @@ } EXPORT_SYMBOL_GPL(iommu_domain_window_disable); +struct dentry *iommu_debugfs_top; + static int __init iommu_init(void) { iommu_group_kset = kset_create_and_add("iommu_groups", @@ -1500,6 +1617,12 @@ BUG_ON(!iommu_group_kset); + iommu_debugfs_top = debugfs_create_dir("iommu", NULL); + if (!iommu_debugfs_top) { + pr_err("Couldn't create iommu debugfs directory\n"); + return -ENODEV; + } + return 0; } core_initcall(iommu_init); @@ -1520,7 +1643,7 @@ break; case DOMAIN_ATTR_PAGING: paging = data; - *paging = (domain->ops->pgsize_bitmap != 0UL); + *paging = (iommu_get_pgsize_bitmap(domain) != 0UL); break; case DOMAIN_ATTR_WINDOWS: count = data; @@ -1569,6 +1692,14 @@ } EXPORT_SYMBOL_GPL(iommu_domain_set_attr); +int iommu_dma_supported(struct iommu_domain *domain, struct device *dev, + u64 mask) +{ + if (domain->ops->dma_supported) + return domain->ops->dma_supported(domain, dev, mask); + return 0; +} + void iommu_get_dm_regions(struct device *dev, struct list_head *list) { const struct iommu_ops *ops = dev->bus->iommu_ops; diff -ruw linux-4.4.115/drivers/iommu/io-pgtable-arm.c linux-4.4.115-fbx/drivers/iommu/io-pgtable-arm.c --- linux-4.4.115/drivers/iommu/io-pgtable-arm.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/iommu/io-pgtable-arm.c 2019-01-22 16:16:24.059251441 +0100 @@ -22,6 +22,7 @@ #include #include +#include #include #include #include @@ -68,9 +69,12 @@ #define ARM_LPAE_PGD_IDX(l,d) \ ((l) == ARM_LPAE_START_LVL(d) ? ilog2(ARM_LPAE_PAGES_PER_PGD(d)) : 0) +#define ARM_LPAE_LVL_MASK(l, d) \ + ((l) == ARM_LPAE_START_LVL(d) ? (1 << (d)->pgd_bits) - 1 : \ + (1 << (d)->bits_per_level) - 1) #define ARM_LPAE_LVL_IDX(a,l,d) \ (((u64)(a) >> ARM_LPAE_LVL_SHIFT(l,d)) & \ - ((1 << ((d)->bits_per_level + ARM_LPAE_PGD_IDX(l,d))) - 1)) + ARM_LPAE_LVL_MASK(l, d)) /* Calculate the block/page mapping size at level l for pagetable in d. */ #define ARM_LPAE_BLOCK_SIZE(l,d) \ @@ -85,6 +89,7 @@ #define ARM_LPAE_PTE_TYPE_TABLE 3 #define ARM_LPAE_PTE_TYPE_PAGE 3 +#define ARM_LPAE_PTE_SH_MASK (((arm_lpae_iopte)0x3) << 8) #define ARM_LPAE_PTE_NSTABLE (((arm_lpae_iopte)1) << 63) #define ARM_LPAE_PTE_XN (((arm_lpae_iopte)3) << 53) #define ARM_LPAE_PTE_AF (((arm_lpae_iopte)1) << 10) @@ -101,8 +106,11 @@ ARM_LPAE_PTE_ATTR_HI_MASK) /* Stage-1 PTE */ -#define ARM_LPAE_PTE_AP_UNPRIV (((arm_lpae_iopte)1) << 6) -#define ARM_LPAE_PTE_AP_RDONLY (((arm_lpae_iopte)2) << 6) +#define ARM_LPAE_PTE_AP_PRIV_RW (((arm_lpae_iopte)0) << 6) +#define ARM_LPAE_PTE_AP_RW (((arm_lpae_iopte)1) << 6) +#define ARM_LPAE_PTE_AP_PRIV_RO (((arm_lpae_iopte)2) << 6) +#define ARM_LPAE_PTE_AP_RO (((arm_lpae_iopte)3) << 6) +#define ARM_LPAE_PTE_ATTRINDX_MASK 0x7 #define ARM_LPAE_PTE_ATTRINDX_SHIFT 2 #define ARM_LPAE_PTE_nG (((arm_lpae_iopte)1) << 11) @@ -124,14 +132,21 @@ #define ARM_LPAE_TCR_TG0_64K (1 << 14) #define ARM_LPAE_TCR_TG0_16K (2 << 14) +#define ARM_LPAE_TCR_TG1_16K 1ULL +#define ARM_LPAE_TCR_TG1_4K 2ULL +#define ARM_LPAE_TCR_TG1_64K 3ULL + #define ARM_LPAE_TCR_SH0_SHIFT 12 #define ARM_LPAE_TCR_SH0_MASK 0x3 +#define ARM_LPAE_TCR_SH1_SHIFT 28 #define ARM_LPAE_TCR_SH_NS 0 #define ARM_LPAE_TCR_SH_OS 2 #define ARM_LPAE_TCR_SH_IS 3 #define ARM_LPAE_TCR_ORGN0_SHIFT 10 +#define ARM_LPAE_TCR_ORGN1_SHIFT 26 #define ARM_LPAE_TCR_IRGN0_SHIFT 8 +#define ARM_LPAE_TCR_IRGN1_SHIFT 24 #define ARM_LPAE_TCR_RGN_MASK 0x3 #define ARM_LPAE_TCR_RGN_NC 0 #define ARM_LPAE_TCR_RGN_WBWA 1 @@ -144,6 +159,9 @@ #define ARM_LPAE_TCR_T0SZ_SHIFT 0 #define ARM_LPAE_TCR_SZ_MASK 0xf +#define ARM_LPAE_TCR_T1SZ_SHIFT 16 +#define ARM_LPAE_TCR_T1SZ_MASK 0x3f + #define ARM_LPAE_TCR_PS_SHIFT 16 #define ARM_LPAE_TCR_PS_MASK 0x7 @@ -157,6 +175,19 @@ #define ARM_LPAE_TCR_PS_44_BIT 0x4ULL #define ARM_LPAE_TCR_PS_48_BIT 0x5ULL +#define ARM_LPAE_TCR_EPD1_SHIFT 23 +#define ARM_LPAE_TCR_EPD1_FAULT 1 + +#define ARM_LPAE_TCR_SEP_SHIFT (15 + 32) + +#define ARM_LPAE_TCR_SEP_31 0ULL +#define ARM_LPAE_TCR_SEP_35 1ULL +#define ARM_LPAE_TCR_SEP_39 2ULL +#define ARM_LPAE_TCR_SEP_41 3ULL +#define ARM_LPAE_TCR_SEP_43 4ULL +#define ARM_LPAE_TCR_SEP_47 5ULL +#define ARM_LPAE_TCR_SEP_UPSTREAM 7ULL + #define ARM_LPAE_MAIR_ATTR_SHIFT(n) ((n) << 3) #define ARM_LPAE_MAIR_ATTR_MASK 0xff #define ARM_LPAE_MAIR_ATTR_DEVICE 0x04 @@ -168,7 +199,7 @@ /* IOPTE accessors */ #define iopte_deref(pte,d) \ - (__va((pte) & ((1ULL << ARM_LPAE_MAX_ADDR_BITS) - 1) \ + (__va(iopte_val(pte) & ((1ULL << ARM_LPAE_MAX_ADDR_BITS) - 1) \ & ~((1ULL << (d)->pg_shift) - 1))) #define iopte_type(pte,l) \ @@ -191,28 +222,113 @@ struct io_pgtable iop; int levels; + unsigned int pgd_bits; size_t pgd_size; unsigned long pg_shift; unsigned long bits_per_level; - void *pgd; + void *pgd[2]; }; typedef u64 arm_lpae_iopte; static bool selftest_running = false; +/* + * We'll use some ignored bits in table entries to keep track of the number + * of page mappings beneath the table. The maximum number of entries + * beneath any table mapping in armv8 is 8192 (which is possible at the + * 2nd- and 3rd-level when using a 64K granule size). The bits at our + * disposal are: + * + * 4k granule: [58..52], [11..2] + * 64k granule: [58..52], [15..2] + * + * [58..52], [11..2] is enough bits for tracking table mappings at any + * level for any granule, so we'll use those. + */ +#define BOTTOM_IGNORED_MASK 0x3ff +#define BOTTOM_IGNORED_SHIFT 2 +#define BOTTOM_IGNORED_NUM_BITS 10 +#define TOP_IGNORED_MASK 0x7fULL +#define TOP_IGNORED_SHIFT 52 +#define IOPTE_RESERVED_MASK ((BOTTOM_IGNORED_MASK << BOTTOM_IGNORED_SHIFT) | \ + (TOP_IGNORED_MASK << TOP_IGNORED_SHIFT)) + +static arm_lpae_iopte iopte_val(arm_lpae_iopte table_pte) +{ + return table_pte & ~IOPTE_RESERVED_MASK; +} + +static arm_lpae_iopte _iopte_bottom_ignored_val(arm_lpae_iopte table_pte) +{ + return (table_pte & (BOTTOM_IGNORED_MASK << BOTTOM_IGNORED_SHIFT)) + >> BOTTOM_IGNORED_SHIFT; +} + +static arm_lpae_iopte _iopte_top_ignored_val(arm_lpae_iopte table_pte) +{ + return (table_pte & (TOP_IGNORED_MASK << TOP_IGNORED_SHIFT)) + >> TOP_IGNORED_SHIFT; +} + +static int iopte_tblcnt(arm_lpae_iopte table_pte) +{ + return (_iopte_bottom_ignored_val(table_pte) | + (_iopte_top_ignored_val(table_pte) << BOTTOM_IGNORED_NUM_BITS)); +} + +static void iopte_tblcnt_set(arm_lpae_iopte *table_pte, int val) +{ + arm_lpae_iopte pte = iopte_val(*table_pte); + + pte |= ((val & BOTTOM_IGNORED_MASK) << BOTTOM_IGNORED_SHIFT) | + (((val & (TOP_IGNORED_MASK << BOTTOM_IGNORED_NUM_BITS)) + >> BOTTOM_IGNORED_NUM_BITS) << TOP_IGNORED_SHIFT); + *table_pte = pte; +} + +static void iopte_tblcnt_sub(arm_lpae_iopte *table_ptep, int cnt) +{ + arm_lpae_iopte current_cnt = iopte_tblcnt(*table_ptep); + + current_cnt -= cnt; + iopte_tblcnt_set(table_ptep, current_cnt); +} + +static void iopte_tblcnt_add(arm_lpae_iopte *table_ptep, int cnt) +{ + arm_lpae_iopte current_cnt = iopte_tblcnt(*table_ptep); + + current_cnt += cnt; + iopte_tblcnt_set(table_ptep, current_cnt); +} + +static bool suppress_map_failures; + static dma_addr_t __arm_lpae_dma_addr(void *pages) { return (dma_addr_t)virt_to_phys(pages); } +static inline void pgtable_dma_sync_single_for_device( + struct io_pgtable_cfg *cfg, + dma_addr_t addr, size_t size, + enum dma_data_direction dir) +{ + if (!(cfg->quirks & IO_PGTABLE_QUIRK_PAGE_TABLE_COHERENT)) + dma_sync_single_for_device(cfg->iommu_dev, addr, size, + dir); +} + static void *__arm_lpae_alloc_pages(size_t size, gfp_t gfp, - struct io_pgtable_cfg *cfg) + struct io_pgtable_cfg *cfg, + void *cookie) { struct device *dev = cfg->iommu_dev; dma_addr_t dma; - void *pages = alloc_pages_exact(size, gfp | __GFP_ZERO); + void *pages = io_pgtable_alloc_pages_exact(cfg, cookie, + size, gfp | __GFP_ZERO); if (!pages) return NULL; @@ -236,17 +352,17 @@ dev_err(dev, "Cannot accommodate DMA translation for IOMMU page tables\n"); dma_unmap_single(dev, dma, size, DMA_TO_DEVICE); out_free: - free_pages_exact(pages, size); + io_pgtable_free_pages_exact(cfg, cookie, pages, size); return NULL; } static void __arm_lpae_free_pages(void *pages, size_t size, - struct io_pgtable_cfg *cfg) + struct io_pgtable_cfg *cfg, void *cookie) { if (!selftest_running) dma_unmap_single(cfg->iommu_dev, __arm_lpae_dma_addr(pages), size, DMA_TO_DEVICE); - free_pages_exact(pages, size); + io_pgtable_free_pages_exact(cfg, cookie, pages, size); } static void __arm_lpae_set_pte(arm_lpae_iopte *ptep, arm_lpae_iopte pte, @@ -255,38 +371,24 @@ *ptep = pte; if (!selftest_running) - dma_sync_single_for_device(cfg->iommu_dev, + pgtable_dma_sync_single_for_device(cfg, __arm_lpae_dma_addr(ptep), sizeof(pte), DMA_TO_DEVICE); } -static int __arm_lpae_unmap(struct arm_lpae_io_pgtable *data, - unsigned long iova, size_t size, int lvl, - arm_lpae_iopte *ptep); - static int arm_lpae_init_pte(struct arm_lpae_io_pgtable *data, unsigned long iova, phys_addr_t paddr, arm_lpae_iopte prot, int lvl, - arm_lpae_iopte *ptep) + arm_lpae_iopte *ptep, arm_lpae_iopte *prev_ptep, + bool flush) { arm_lpae_iopte pte = prot; struct io_pgtable_cfg *cfg = &data->iop.cfg; - if (iopte_leaf(*ptep, lvl)) { /* We require an unmap first */ - WARN_ON(!selftest_running); + if (*ptep & ARM_LPAE_PTE_VALID) { + BUG_ON(!suppress_map_failures); return -EEXIST; - } else if (iopte_type(*ptep, lvl) == ARM_LPAE_PTE_TYPE_TABLE) { - /* - * We need to unmap and free the old table before - * overwriting it with a block entry. - */ - arm_lpae_iopte *tblp; - size_t sz = ARM_LPAE_BLOCK_SIZE(lvl, data); - - tblp = ptep - ARM_LPAE_LVL_IDX(iova, lvl, data); - if (WARN_ON(__arm_lpae_unmap(data, iova, sz, lvl, tblp) != sz)) - return -EINVAL; } if (cfg->quirks & IO_PGTABLE_QUIRK_ARM_NS) @@ -297,27 +399,82 @@ else pte |= ARM_LPAE_PTE_TYPE_BLOCK; - pte |= ARM_LPAE_PTE_AF | ARM_LPAE_PTE_SH_IS; + pte |= ARM_LPAE_PTE_AF | ARM_LPAE_PTE_SH_OS; pte |= pfn_to_iopte(paddr >> data->pg_shift, data); + *ptep = pte; + + if (flush) __arm_lpae_set_pte(ptep, pte, cfg); + + if (prev_ptep) + iopte_tblcnt_add(prev_ptep, 1); + return 0; } +struct map_state { + unsigned long iova_end; + unsigned int pgsize; + arm_lpae_iopte *pgtable; + arm_lpae_iopte *prev_pgtable; + arm_lpae_iopte *pte_start; + unsigned int num_pte; +}; +/* map state optimization works at level 3 (the 2nd-to-last level) */ +#define MAP_STATE_LVL 3 + static int __arm_lpae_map(struct arm_lpae_io_pgtable *data, unsigned long iova, phys_addr_t paddr, size_t size, arm_lpae_iopte prot, - int lvl, arm_lpae_iopte *ptep) + int lvl, arm_lpae_iopte *ptep, + arm_lpae_iopte *prev_ptep, struct map_state *ms) { arm_lpae_iopte *cptep, pte; + void *cookie = data->iop.cookie; size_t block_size = ARM_LPAE_BLOCK_SIZE(lvl, data); + arm_lpae_iopte *pgtable = ptep; struct io_pgtable_cfg *cfg = &data->iop.cfg; /* Find our entry at the current level */ ptep += ARM_LPAE_LVL_IDX(iova, lvl, data); /* If we can install a leaf entry at this level, then do so */ - if (size == block_size && (size & cfg->pgsize_bitmap)) - return arm_lpae_init_pte(data, iova, paddr, prot, lvl, ptep); + if (size == block_size && (size & cfg->pgsize_bitmap)) { + if (!ms) + return arm_lpae_init_pte(data, iova, paddr, prot, lvl, + ptep, prev_ptep, true); + + if (lvl == MAP_STATE_LVL) { + if (ms->pgtable) + pgtable_dma_sync_single_for_device(cfg, + __arm_lpae_dma_addr(ms->pte_start), + ms->num_pte * sizeof(*ptep), + DMA_TO_DEVICE); + + ms->iova_end = round_down(iova, SZ_2M) + SZ_2M; + ms->pgtable = pgtable; + ms->prev_pgtable = prev_ptep; + ms->pgsize = size; + ms->pte_start = ptep; + ms->num_pte = 1; + } else { + /* + * We have some map state from previous page + * mappings, but we're about to set up a block + * mapping. Flush out the previous page mappings. + */ + if (ms->pgtable) + pgtable_dma_sync_single_for_device(cfg, + __arm_lpae_dma_addr(ms->pte_start), + ms->num_pte * sizeof(*ptep), + DMA_TO_DEVICE); + memset(ms, 0, sizeof(*ms)); + ms = NULL; + } + + return arm_lpae_init_pte(data, iova, paddr, prot, lvl, ptep, + prev_ptep, ms == NULL); + } /* We can't allocate tables at the final level */ if (WARN_ON(lvl >= ARM_LPAE_MAX_LEVELS - 1)) @@ -327,7 +484,7 @@ pte = *ptep; if (!pte) { cptep = __arm_lpae_alloc_pages(1UL << data->pg_shift, - GFP_ATOMIC, cfg); + GFP_ATOMIC, cfg, cookie); if (!cptep) return -ENOMEM; @@ -344,7 +501,8 @@ } /* Rinse, repeat */ - return __arm_lpae_map(data, iova, paddr, size, prot, lvl + 1, cptep); + return __arm_lpae_map(data, iova, paddr, size, prot, lvl + 1, cptep, + ptep, ms); } static arm_lpae_iopte arm_lpae_prot_to_pte(struct arm_lpae_io_pgtable *data, @@ -354,14 +512,22 @@ if (data->iop.fmt == ARM_64_LPAE_S1 || data->iop.fmt == ARM_32_LPAE_S1) { - pte = ARM_LPAE_PTE_AP_UNPRIV | ARM_LPAE_PTE_nG; + pte = ARM_LPAE_PTE_nG; - if (!(prot & IOMMU_WRITE) && (prot & IOMMU_READ)) - pte |= ARM_LPAE_PTE_AP_RDONLY; + if (prot & IOMMU_WRITE) + pte |= (prot & IOMMU_PRIV) ? ARM_LPAE_PTE_AP_PRIV_RW + : ARM_LPAE_PTE_AP_RW; + else + pte |= (prot & IOMMU_PRIV) ? ARM_LPAE_PTE_AP_PRIV_RO + : ARM_LPAE_PTE_AP_RO; if (prot & IOMMU_CACHE) pte |= (ARM_LPAE_MAIR_ATTR_IDX_CACHE << ARM_LPAE_PTE_ATTRINDX_SHIFT); + + if (prot & IOMMU_DEVICE) + pte |= (ARM_LPAE_MAIR_ATTR_IDX_DEV << + ARM_LPAE_PTE_ATTRINDX_SHIFT); } else { pte = ARM_LPAE_PTE_HAP_FAULT; if (prot & IOMMU_READ) @@ -372,6 +538,9 @@ pte |= ARM_LPAE_PTE_MEMATTR_OIWB; else pte |= ARM_LPAE_PTE_MEMATTR_NC; + + if (prot & IOMMU_DEVICE) + pte |= ARM_LPAE_PTE_MEMATTR_DEV; } if (prot & IOMMU_NOEXEC) @@ -380,20 +549,42 @@ return pte; } +static inline arm_lpae_iopte *arm_lpae_get_table( + struct arm_lpae_io_pgtable *data, unsigned long iova) +{ + struct io_pgtable_cfg *cfg = &data->iop.cfg; + + /* + * iovas for TTBR1 will have all the bits set between the input address + * region and the sign extension bit + */ + if (unlikely(cfg->quirks & IO_PGTABLE_QUIRK_ARM_TTBR1)) { + unsigned long mask = GENMASK(cfg->sep, cfg->ias); + + if ((iova & mask) == mask) + return data->pgd[1]; + } + + return data->pgd[0]; +} + static int arm_lpae_map(struct io_pgtable_ops *ops, unsigned long iova, phys_addr_t paddr, size_t size, int iommu_prot) { struct arm_lpae_io_pgtable *data = io_pgtable_ops_to_data(ops); - arm_lpae_iopte *ptep = data->pgd; + arm_lpae_iopte *ptep; int ret, lvl = ARM_LPAE_START_LVL(data); arm_lpae_iopte prot; + ptep = arm_lpae_get_table(data, iova); + /* If no access, then nothing to do */ if (!(iommu_prot & (IOMMU_READ | IOMMU_WRITE))) return 0; prot = arm_lpae_prot_to_pte(data, iommu_prot); - ret = __arm_lpae_map(data, iova, paddr, size, prot, lvl, ptep); + ret = __arm_lpae_map(data, iova, paddr, size, prot, lvl, ptep, NULL, + NULL); /* * Synchronise all PTE updates for the new mapping before there's * a chance for anything to kick off a table walk for the new iova. @@ -403,6 +594,91 @@ return ret; } +static int arm_lpae_map_sg(struct io_pgtable_ops *ops, unsigned long iova, + struct scatterlist *sg, unsigned int nents, + int iommu_prot, size_t *size) +{ + struct arm_lpae_io_pgtable *data = io_pgtable_ops_to_data(ops); + struct io_pgtable_cfg *cfg = &data->iop.cfg; + arm_lpae_iopte *ptep; + int lvl = ARM_LPAE_START_LVL(data); + arm_lpae_iopte prot; + struct scatterlist *s; + size_t mapped = 0; + int i, ret; + unsigned int min_pagesz; + struct map_state ms; + + ptep = arm_lpae_get_table(data, iova); + + /* If no access, then nothing to do */ + if (!(iommu_prot & (IOMMU_READ | IOMMU_WRITE))) + goto out_err; + + prot = arm_lpae_prot_to_pte(data, iommu_prot); + + min_pagesz = 1 << __ffs(data->iop.cfg.pgsize_bitmap); + + memset(&ms, 0, sizeof(ms)); + + for_each_sg(sg, s, nents, i) { + phys_addr_t phys = page_to_phys(sg_page(s)) + s->offset; + size_t size = s->length; + + /* + * We are mapping on IOMMU page boundaries, so offset within + * the page must be 0. However, the IOMMU may support pages + * smaller than PAGE_SIZE, so s->offset may still represent + * an offset of that boundary within the CPU page. + */ + if (!IS_ALIGNED(s->offset, min_pagesz)) + goto out_err; + + while (size) { + size_t pgsize = iommu_pgsize( + data->iop.cfg.pgsize_bitmap, iova | phys, size); + + if (ms.pgtable && (iova < ms.iova_end)) { + arm_lpae_iopte *ptep = ms.pgtable + + ARM_LPAE_LVL_IDX(iova, MAP_STATE_LVL, + data); + arm_lpae_init_pte( + data, iova, phys, prot, MAP_STATE_LVL, + ptep, ms.prev_pgtable, false); + ms.num_pte++; + } else { + ret = __arm_lpae_map(data, iova, phys, pgsize, + prot, lvl, ptep, NULL, &ms); + if (ret) + goto out_err; + } + + iova += pgsize; + mapped += pgsize; + phys += pgsize; + size -= pgsize; + } + } + + if (ms.pgtable) + pgtable_dma_sync_single_for_device(cfg, + __arm_lpae_dma_addr(ms.pte_start), + ms.num_pte * sizeof(*ms.pte_start), + DMA_TO_DEVICE); + /* + * Synchronise all PTE updates for the new mapping before there's + * a chance for anything to kick off a table walk for the new iova. + */ + wmb(); + + return mapped; + +out_err: + /* Return the size of the partial mapping so that they can be undone */ + *size = mapped; + return 0; +} + static void __arm_lpae_free_pgtable(struct arm_lpae_io_pgtable *data, int lvl, arm_lpae_iopte *ptep) { @@ -422,6 +698,10 @@ else end = (void *)ptep + table_size; + /* Only leaf entries at the last level */ + if (lvl == ARM_LPAE_MAX_LEVELS - 1) + goto end; + while (ptep != end) { arm_lpae_iopte pte = *ptep++; @@ -431,21 +711,27 @@ __arm_lpae_free_pgtable(data, lvl + 1, iopte_deref(pte, data)); } - __arm_lpae_free_pages(start, table_size, &data->iop.cfg); +end: + __arm_lpae_free_pages(start, table_size, &data->iop.cfg, + data->iop.cookie); } static void arm_lpae_free_pgtable(struct io_pgtable *iop) { struct arm_lpae_io_pgtable *data = io_pgtable_to_data(iop); - __arm_lpae_free_pgtable(data, ARM_LPAE_START_LVL(data), data->pgd); + __arm_lpae_free_pgtable(data, ARM_LPAE_START_LVL(data), data->pgd[0]); + if (data->pgd[1]) + __arm_lpae_free_pgtable(data, ARM_LPAE_START_LVL(data), + data->pgd[1]); kfree(data); } static int arm_lpae_split_blk_unmap(struct arm_lpae_io_pgtable *data, unsigned long iova, size_t size, arm_lpae_iopte prot, int lvl, - arm_lpae_iopte *ptep, size_t blk_size) + arm_lpae_iopte *ptep, + arm_lpae_iopte *prev_ptep, size_t blk_size) { unsigned long blk_start, blk_end; phys_addr_t blk_paddr; @@ -455,6 +741,7 @@ blk_start = iova & ~(blk_size - 1); blk_end = blk_start + blk_size; blk_paddr = iopte_to_pfn(*ptep, data) << data->pg_shift; + size = ARM_LPAE_BLOCK_SIZE(lvl + 1, data); for (; blk_start < blk_end; blk_start += size, blk_paddr += size) { arm_lpae_iopte *tablep; @@ -466,7 +753,7 @@ /* __arm_lpae_map expects a pointer to the start of the table */ tablep = &table - ARM_LPAE_LVL_IDX(blk_start, lvl, data); if (__arm_lpae_map(data, blk_start, blk_paddr, size, prot, lvl, - tablep) < 0) { + tablep, prev_ptep, NULL) < 0) { if (table) { /* Free the table we allocated */ tablep = iopte_deref(table, data); @@ -477,17 +764,15 @@ } __arm_lpae_set_pte(ptep, table, cfg); - iova &= ~(blk_size - 1); - cfg->tlb->tlb_add_flush(iova, blk_size, true, data->iop.cookie); return size; } static int __arm_lpae_unmap(struct arm_lpae_io_pgtable *data, unsigned long iova, size_t size, int lvl, - arm_lpae_iopte *ptep) + arm_lpae_iopte *ptep, arm_lpae_iopte *prev_ptep) { arm_lpae_iopte pte; - const struct iommu_gather_ops *tlb = data->iop.cfg.tlb; + struct io_pgtable_cfg *cfg = &data->iop.cfg; void *cookie = data->iop.cookie; size_t blk_size = ARM_LPAE_BLOCK_SIZE(lvl, data); @@ -504,15 +789,45 @@ if (!iopte_leaf(pte, lvl)) { /* Also flush any partial walks */ - tlb->tlb_add_flush(iova, size, false, cookie); - tlb->tlb_sync(cookie); ptep = iopte_deref(pte, data); __arm_lpae_free_pgtable(data, lvl + 1, ptep); - } else { - tlb->tlb_add_flush(iova, size, true, cookie); } return size; + } else if ((lvl == ARM_LPAE_MAX_LEVELS - 2) && !iopte_leaf(pte, lvl)) { + arm_lpae_iopte *table = iopte_deref(pte, data); + arm_lpae_iopte *table_base = table; + int tl_offset = ARM_LPAE_LVL_IDX(iova, lvl + 1, data); + int entry_size = (1 << data->pg_shift); + int max_entries = ARM_LPAE_BLOCK_SIZE(lvl, data) / entry_size; + int entries = min_t(int, size / entry_size, + max_entries - tl_offset); + int table_len = entries * sizeof(*table); + + /* + * This isn't a block mapping so it must be a table mapping + * and since it's the 2nd-to-last level the next level has + * to be all page mappings. Zero them all out in one fell + * swoop. + */ + + table += tl_offset; + + memset(table, 0, table_len); + pgtable_dma_sync_single_for_device(cfg, + __arm_lpae_dma_addr(table), + table_len, DMA_TO_DEVICE); + + iopte_tblcnt_sub(ptep, entries); + if (!iopte_tblcnt(*ptep)) { + /* no valid mappings left under this table. free it. */ + __arm_lpae_set_pte(ptep, 0, cfg); + io_pgtable_free_pages_exact( + &data->iop.cfg, cookie, table_base, + max_entries * sizeof(*table_base)); + } + + return entries * entry_size; } else if (iopte_leaf(pte, lvl)) { /* * Insert a table at the next level to map the old region, @@ -520,63 +835,150 @@ */ return arm_lpae_split_blk_unmap(data, iova, size, iopte_prot(pte), lvl, ptep, + prev_ptep, blk_size); } /* Keep on walkin' */ + prev_ptep = ptep; ptep = iopte_deref(pte, data); - return __arm_lpae_unmap(data, iova, size, lvl + 1, ptep); + return __arm_lpae_unmap(data, iova, size, lvl + 1, ptep, prev_ptep); } -static int arm_lpae_unmap(struct io_pgtable_ops *ops, unsigned long iova, +static size_t arm_lpae_unmap(struct io_pgtable_ops *ops, unsigned long iova, size_t size) { - size_t unmapped; + size_t unmapped = 0; struct arm_lpae_io_pgtable *data = io_pgtable_ops_to_data(ops); struct io_pgtable *iop = &data->iop; - arm_lpae_iopte *ptep = data->pgd; + arm_lpae_iopte *ptep; int lvl = ARM_LPAE_START_LVL(data); - unmapped = __arm_lpae_unmap(data, iova, size, lvl, ptep); + ptep = arm_lpae_get_table(data, iova); + + while (unmapped < size) { + size_t ret, size_to_unmap, remaining; + + remaining = (size - unmapped); + size_to_unmap = remaining < SZ_2M + ? remaining + : iommu_pgsize(data->iop.cfg.pgsize_bitmap, iova, + remaining); + ret = __arm_lpae_unmap(data, iova, size_to_unmap, lvl, ptep, + NULL); + if (ret == 0) + break; + unmapped += ret; + iova += ret; + } if (unmapped) - iop->cfg.tlb->tlb_sync(iop->cookie); + iop->cfg.tlb->tlb_flush_all(iop->cookie); return unmapped; } -static phys_addr_t arm_lpae_iova_to_phys(struct io_pgtable_ops *ops, - unsigned long iova) +static int arm_lpae_iova_to_pte(struct arm_lpae_io_pgtable *data, + unsigned long iova, int *plvl_ret, + arm_lpae_iopte *ptep_ret) { - struct arm_lpae_io_pgtable *data = io_pgtable_ops_to_data(ops); - arm_lpae_iopte pte, *ptep = data->pgd; - int lvl = ARM_LPAE_START_LVL(data); + arm_lpae_iopte pte, *ptep; + + ptep = arm_lpae_get_table(data, iova); + + *plvl_ret = ARM_LPAE_START_LVL(data); + *ptep_ret = 0; do { /* Valid IOPTE pointer? */ if (!ptep) - return 0; + return -EINVAL; /* Grab the IOPTE we're interested in */ - pte = *(ptep + ARM_LPAE_LVL_IDX(iova, lvl, data)); + pte = *(ptep + ARM_LPAE_LVL_IDX(iova, *plvl_ret, data)); /* Valid entry? */ if (!pte) - return 0; + return -EINVAL; /* Leaf entry? */ - if (iopte_leaf(pte,lvl)) + if (iopte_leaf(pte, *plvl_ret)) goto found_translation; /* Take it to the next level */ ptep = iopte_deref(pte, data); - } while (++lvl < ARM_LPAE_MAX_LEVELS); + } while (++(*plvl_ret) < ARM_LPAE_MAX_LEVELS); /* Ran out of page tables to walk */ - return 0; + return -EINVAL; found_translation: - iova &= ((1 << data->pg_shift) - 1); - return ((phys_addr_t)iopte_to_pfn(pte,data) << data->pg_shift) | iova; + *ptep_ret = pte; + return 0; +} + +static uint64_t arm_lpae_iova_get_pte(struct io_pgtable_ops *ops, + unsigned long iova) +{ + struct arm_lpae_io_pgtable *data = io_pgtable_ops_to_data(ops); + arm_lpae_iopte pte; + int lvl; + + if (!arm_lpae_iova_to_pte(data, iova, &lvl, &pte)) + return pte; + + return 0; +} + +static phys_addr_t arm_lpae_iova_to_phys(struct io_pgtable_ops *ops, + unsigned long iova) +{ + struct arm_lpae_io_pgtable *data = io_pgtable_ops_to_data(ops); + arm_lpae_iopte pte; + int lvl; + phys_addr_t phys = 0; + + if (!arm_lpae_iova_to_pte(data, iova, &lvl, &pte)) { + iova &= ((1 << ARM_LPAE_LVL_SHIFT(lvl, data)) - 1); + phys = ((phys_addr_t)iopte_to_pfn(pte, data) + << data->pg_shift) | iova; + } + + return phys; +} + +static bool __arm_lpae_is_iova_coherent(struct arm_lpae_io_pgtable *data, + arm_lpae_iopte *ptep) +{ + if (data->iop.fmt == ARM_64_LPAE_S1 || + data->iop.fmt == ARM_32_LPAE_S1) { + int attr_idx = (*ptep & (ARM_LPAE_PTE_ATTRINDX_MASK << + ARM_LPAE_PTE_ATTRINDX_SHIFT)) >> + ARM_LPAE_PTE_ATTRINDX_SHIFT; + if ((attr_idx == ARM_LPAE_MAIR_ATTR_IDX_CACHE) && + (((*ptep & ARM_LPAE_PTE_SH_MASK) == ARM_LPAE_PTE_SH_IS) + || + (*ptep & ARM_LPAE_PTE_SH_MASK) == ARM_LPAE_PTE_SH_OS)) + return true; + } else { + if (*ptep & ARM_LPAE_PTE_MEMATTR_OIWB) + return true; + } + + return false; +} + +static bool arm_lpae_is_iova_coherent(struct io_pgtable_ops *ops, + unsigned long iova) +{ + struct arm_lpae_io_pgtable *data = io_pgtable_ops_to_data(ops); + arm_lpae_iopte pte; + int lvl; + bool ret = false; + + if (!arm_lpae_iova_to_pte(data, iova, &lvl, &pte)) + ret = __arm_lpae_is_iova_coherent(data, &pte); + + return ret; } static void arm_lpae_restrict_pgsizes(struct io_pgtable_cfg *cfg) @@ -648,17 +1050,86 @@ /* Calculate the actual size of our pgd (without concatenation) */ pgd_bits = va_bits - (data->bits_per_level * (data->levels - 1)); + data->pgd_bits = pgd_bits; data->pgd_size = 1UL << (pgd_bits + ilog2(sizeof(arm_lpae_iopte))); data->iop.ops = (struct io_pgtable_ops) { .map = arm_lpae_map, + .map_sg = arm_lpae_map_sg, .unmap = arm_lpae_unmap, .iova_to_phys = arm_lpae_iova_to_phys, + .is_iova_coherent = arm_lpae_is_iova_coherent, + .iova_to_pte = arm_lpae_iova_get_pte, }; return data; } +static u64 arm64_lpae_setup_ttbr1(struct io_pgtable_cfg *cfg, + struct arm_lpae_io_pgtable *data) + +{ + u64 reg; + + /* If TTBR1 is disabled, disable speculative walks through the TTBR1 */ + if (!(cfg->quirks & IO_PGTABLE_QUIRK_ARM_TTBR1)) { + reg = ARM_LPAE_TCR_EPD1; + reg |= (ARM_LPAE_TCR_SEP_UPSTREAM << ARM_LPAE_TCR_SEP_SHIFT); + return reg; + } + + if (cfg->iommu_dev && cfg->iommu_dev->archdata.dma_coherent) + reg = (ARM_LPAE_TCR_SH_OS << ARM_LPAE_TCR_SH1_SHIFT) | + (ARM_LPAE_TCR_RGN_WBWA << ARM_LPAE_TCR_IRGN1_SHIFT) | + (ARM_LPAE_TCR_RGN_WBWA << ARM_LPAE_TCR_ORGN1_SHIFT); + else + reg = (ARM_LPAE_TCR_SH_OS << ARM_LPAE_TCR_SH1_SHIFT) | + (ARM_LPAE_TCR_RGN_NC << ARM_LPAE_TCR_IRGN1_SHIFT) | + (ARM_LPAE_TCR_RGN_NC << ARM_LPAE_TCR_ORGN1_SHIFT); + + switch (1 << data->pg_shift) { + case SZ_4K: + reg |= (ARM_LPAE_TCR_TG1_4K << 30); + break; + case SZ_16K: + reg |= (ARM_LPAE_TCR_TG1_16K << 30); + break; + case SZ_64K: + reg |= (ARM_LPAE_TCR_TG1_64K << 30); + break; + } + + /* Set T1SZ */ + reg |= (64ULL - cfg->ias) << ARM_LPAE_TCR_T1SZ_SHIFT; + + switch (cfg->sep) { + case 31: + reg |= (ARM_LPAE_TCR_SEP_31 << ARM_LPAE_TCR_SEP_SHIFT); + break; + case 35: + reg |= (ARM_LPAE_TCR_SEP_35 << ARM_LPAE_TCR_SEP_SHIFT); + break; + case 39: + reg |= (ARM_LPAE_TCR_SEP_39 << ARM_LPAE_TCR_SEP_SHIFT); + break; + case 41: + reg |= (ARM_LPAE_TCR_SEP_41 << ARM_LPAE_TCR_SEP_SHIFT); + break; + case 43: + reg |= (ARM_LPAE_TCR_SEP_43 << ARM_LPAE_TCR_SEP_SHIFT); + break; + case 47: + reg |= (ARM_LPAE_TCR_SEP_47 << ARM_LPAE_TCR_SEP_SHIFT); + break; + case 48: + default: + reg |= (ARM_LPAE_TCR_SEP_UPSTREAM << ARM_LPAE_TCR_SEP_SHIFT); + break; + } + + return reg; +} + static struct io_pgtable * arm_64_lpae_alloc_pgtable_s1(struct io_pgtable_cfg *cfg, void *cookie) { @@ -669,9 +1140,14 @@ return NULL; /* TCR */ - reg = (ARM_LPAE_TCR_SH_IS << ARM_LPAE_TCR_SH0_SHIFT) | + if (cfg->quirks & IO_PGTABLE_QUIRK_PAGE_TABLE_COHERENT) + reg = (ARM_LPAE_TCR_SH_OS << ARM_LPAE_TCR_SH0_SHIFT) | (ARM_LPAE_TCR_RGN_WBWA << ARM_LPAE_TCR_IRGN0_SHIFT) | (ARM_LPAE_TCR_RGN_WBWA << ARM_LPAE_TCR_ORGN0_SHIFT); + else + reg = (ARM_LPAE_TCR_SH_OS << ARM_LPAE_TCR_SH0_SHIFT) | + (ARM_LPAE_TCR_RGN_NC << ARM_LPAE_TCR_IRGN0_SHIFT) | + (ARM_LPAE_TCR_RGN_NC << ARM_LPAE_TCR_ORGN0_SHIFT); switch (1 << data->pg_shift) { case SZ_4K: @@ -710,8 +1186,9 @@ reg |= (64ULL - cfg->ias) << ARM_LPAE_TCR_T0SZ_SHIFT; - /* Disable speculative walks through TTBR1 */ - reg |= ARM_LPAE_TCR_EPD1; + /* Bring in the TTBR1 configuration */ + reg |= arm64_lpae_setup_ttbr1(cfg, data); + cfg->arm_lpae_s1_cfg.tcr = reg; /* MAIRs */ @@ -726,16 +1203,33 @@ cfg->arm_lpae_s1_cfg.mair[1] = 0; /* Looking good; allocate a pgd */ - data->pgd = __arm_lpae_alloc_pages(data->pgd_size, GFP_KERNEL, cfg); - if (!data->pgd) + data->pgd[0] = __arm_lpae_alloc_pages(data->pgd_size, GFP_KERNEL, cfg, + cookie); + if (!data->pgd[0]) goto out_free_data; + + if (cfg->quirks & IO_PGTABLE_QUIRK_ARM_TTBR1) { + data->pgd[1] = __arm_lpae_alloc_pages(data->pgd_size, + GFP_KERNEL, cfg, cookie); + if (!data->pgd[1]) { + __arm_lpae_free_pages(data->pgd[0], data->pgd_size, cfg, + cookie); + goto out_free_data; + } + } else { + data->pgd[1] = NULL; + } + /* Ensure the empty pgd is visible before any actual TTBR write */ wmb(); /* TTBRs */ - cfg->arm_lpae_s1_cfg.ttbr[0] = virt_to_phys(data->pgd); - cfg->arm_lpae_s1_cfg.ttbr[1] = 0; + cfg->arm_lpae_s1_cfg.ttbr[0] = virt_to_phys(data->pgd[0]); + + if (data->pgd[1]) + cfg->arm_lpae_s1_cfg.ttbr[1] = virt_to_phys(data->pgd[1]); + return &data->iop; out_free_data: @@ -815,15 +1309,16 @@ cfg->arm_lpae_s2_cfg.vtcr = reg; /* Allocate pgd pages */ - data->pgd = __arm_lpae_alloc_pages(data->pgd_size, GFP_KERNEL, cfg); - if (!data->pgd) + data->pgd[0] = __arm_lpae_alloc_pages(data->pgd_size, GFP_KERNEL, cfg, + cookie); + if (!data->pgd[0]) goto out_free_data; /* Ensure the empty pgd is visible before any actual TTBR write */ wmb(); /* VTTBR */ - cfg->arm_lpae_s2_cfg.vttbr = virt_to_phys(data->pgd); + cfg->arm_lpae_s2_cfg.vttbr = virt_to_phys(data->pgd[0]); return &data->iop; out_free_data: @@ -921,16 +1416,54 @@ cfg->pgsize_bitmap, cfg->ias); pr_err("data: %d levels, 0x%zx pgd_size, %lu pg_shift, %lu bits_per_level, pgd @ %p\n", data->levels, data->pgd_size, data->pg_shift, - data->bits_per_level, data->pgd); + data->bits_per_level, data->pgd[0]); } #define __FAIL(ops, i) ({ \ WARN(1, "selftest: test failed for fmt idx %d\n", (i)); \ arm_lpae_dump_ops(ops); \ selftest_running = false; \ + suppress_map_failures = false; \ -EFAULT; \ }) +/* + * Returns true if there's any mapping in the given iova range in ops. + */ +static bool arm_lpae_range_has_mapping(struct io_pgtable_ops *ops, + unsigned long iova_start, size_t size) +{ + unsigned long iova = iova_start; + + while (iova < (iova_start + size)) { + if (ops->iova_to_phys(ops, iova + 42)) + return true; + iova += SZ_4K; + } + return false; +} + +/* + * Returns true if the iova range is successfully mapped to the contiguous + * phys range in ops. + */ +static bool arm_lpae_range_has_specific_mapping(struct io_pgtable_ops *ops, + const unsigned long iova_start, + const phys_addr_t phys_start, + const size_t size) +{ + unsigned long iova = iova_start; + phys_addr_t phys = phys_start; + + while (iova < (iova_start + size)) { + if (ops->iova_to_phys(ops, iova + 42) != (phys + 42)) + return false; + iova += SZ_4K; + phys += SZ_4K; + } + return true; +} + static int __init arm_lpae_run_tests(struct io_pgtable_cfg *cfg) { static const enum io_pgtable_fmt fmts[] = { @@ -938,7 +1471,7 @@ ARM_64_LPAE_S2, }; - int i, j; + int i, j, k; unsigned long iova; size_t size; struct io_pgtable_ops *ops; @@ -946,6 +1479,9 @@ selftest_running = true; for (i = 0; i < ARRAY_SIZE(fmts); ++i) { + unsigned long test_sg_sizes[] = { SZ_4K, SZ_64K, SZ_2M, + SZ_1M * 12, SZ_1M * 20 }; + cfg_cookie = cfg; ops = alloc_io_pgtable_ops(fmts[i], cfg, cfg); if (!ops) { @@ -954,16 +1490,11 @@ } /* - * Initial sanity checks. - * Empty page tables shouldn't provide any translations. + * Initial sanity checks. Empty page tables shouldn't + * provide any translations. TODO: check entire supported + * range for these ops rather than first 2G */ - if (ops->iova_to_phys(ops, 42)) - return __FAIL(ops, i); - - if (ops->iova_to_phys(ops, SZ_1G + 42)) - return __FAIL(ops, i); - - if (ops->iova_to_phys(ops, SZ_2G + 42)) + if (arm_lpae_range_has_mapping(ops, 0, SZ_2G)) return __FAIL(ops, i); /* @@ -980,12 +1511,15 @@ IOMMU_CACHE)) return __FAIL(ops, i); + suppress_map_failures = true; /* Overlapping mappings */ if (!ops->map(ops, iova, iova + size, size, IOMMU_READ | IOMMU_NOEXEC)) return __FAIL(ops, i); + suppress_map_failures = false; - if (ops->iova_to_phys(ops, iova + 42) != (iova + 42)) + if (!arm_lpae_range_has_specific_mapping(ops, iova, + iova, size)) return __FAIL(ops, i); iova += SZ_1G; @@ -998,11 +1532,15 @@ if (ops->unmap(ops, SZ_1G + size, size) != size) return __FAIL(ops, i); + if (arm_lpae_range_has_mapping(ops, SZ_1G + size, size)) + return __FAIL(ops, i); + /* Remap of partial unmap */ if (ops->map(ops, SZ_1G + size, size, size, IOMMU_READ)) return __FAIL(ops, i); - if (ops->iova_to_phys(ops, SZ_1G + size + 42) != (size + 42)) + if (!arm_lpae_range_has_specific_mapping(ops, SZ_1G + size, + size, size)) return __FAIL(ops, i); /* Full unmap */ @@ -1024,15 +1562,107 @@ if (ops->iova_to_phys(ops, iova + 42) != (iova + 42)) return __FAIL(ops, i); + if (ops->unmap(ops, iova, size) != size) + return __FAIL(ops, i); + iova += SZ_1G; j++; j = find_next_bit(&cfg->pgsize_bitmap, BITS_PER_LONG, j); } + if (arm_lpae_range_has_mapping(ops, 0, SZ_2G)) + return __FAIL(ops, i); + + if ((cfg->pgsize_bitmap & SZ_2M) && + (cfg->pgsize_bitmap & SZ_4K)) { + /* mixed block + page mappings */ + iova = 0; + if (ops->map(ops, iova, iova, SZ_2M, IOMMU_READ)) + return __FAIL(ops, i); + + if (ops->map(ops, iova + SZ_2M, iova + SZ_2M, SZ_4K, + IOMMU_READ)) + return __FAIL(ops, i); + + if (ops->iova_to_phys(ops, iova + 42) != (iova + 42)) + return __FAIL(ops, i); + + if (ops->iova_to_phys(ops, iova + SZ_2M + 42) != + (iova + SZ_2M + 42)) + return __FAIL(ops, i); + + /* unmap both mappings at once */ + if (ops->unmap(ops, iova, SZ_2M + SZ_4K) != + (SZ_2M + SZ_4K)) + return __FAIL(ops, i); + + if (arm_lpae_range_has_mapping(ops, 0, SZ_2G)) + return __FAIL(ops, i); + } + + /* map_sg */ + for (j = 0; j < ARRAY_SIZE(test_sg_sizes); ++j) { + size_t mapped; + size_t unused; + struct page *page; + phys_addr_t page_phys; + struct sg_table table; + struct scatterlist *sg; + unsigned long total_size = test_sg_sizes[j]; + int chunk_size = 1UL << find_first_bit( + &cfg->pgsize_bitmap, BITS_PER_LONG); + int nents = total_size / chunk_size; + + if (total_size < chunk_size) + continue; + + page = alloc_pages(GFP_KERNEL, get_order(chunk_size)); + page_phys = page_to_phys(page); + + iova = 0; + BUG_ON(sg_alloc_table(&table, nents, GFP_KERNEL)); + BUG_ON(!page); + for_each_sg(table.sgl, sg, table.nents, k) + sg_set_page(sg, page, chunk_size, 0); + + mapped = ops->map_sg(ops, iova, table.sgl, table.nents, + IOMMU_READ | IOMMU_WRITE, &unused); + + if (mapped != total_size) + return __FAIL(ops, i); + + if (!arm_lpae_range_has_mapping(ops, iova, total_size)) + return __FAIL(ops, i); + + if (arm_lpae_range_has_mapping(ops, iova + total_size, + SZ_2G - (iova + total_size))) + return __FAIL(ops, i); + + for_each_sg(table.sgl, sg, table.nents, k) { + dma_addr_t newphys = + ops->iova_to_phys(ops, iova + 42); + if (newphys != (page_phys + 42)) + return __FAIL(ops, i); + iova += chunk_size; + } + + if (ops->unmap(ops, 0, total_size) != total_size) + return __FAIL(ops, i); + + if (arm_lpae_range_has_mapping(ops, 0, SZ_2G)) + return __FAIL(ops, i); + + sg_free_table(&table); + __free_pages(page, get_order(chunk_size)); + } + + if (arm_lpae_range_has_mapping(ops, 0, SZ_2G)) + return __FAIL(ops, i); + free_io_pgtable_ops(ops); } - selftest_running = false; + suppress_map_failures = false; return 0; } diff -ruw linux-4.4.115/drivers/iommu/io-pgtable.c linux-4.4.115-fbx/drivers/iommu/io-pgtable.c --- linux-4.4.115/drivers/iommu/io-pgtable.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/iommu/io-pgtable.c 2019-01-22 16:16:24.063251478 +0100 @@ -18,12 +18,25 @@ * Author: Will Deacon */ +#define pr_fmt(fmt) "io-pgtable: " fmt + #include #include #include +#include +#include +#include +#include #include "io-pgtable.h" +extern struct io_pgtable_init_fns io_pgtable_arm_32_lpae_s1_init_fns; +extern struct io_pgtable_init_fns io_pgtable_arm_32_lpae_s2_init_fns; +extern struct io_pgtable_init_fns io_pgtable_arm_64_lpae_s1_init_fns; +extern struct io_pgtable_init_fns io_pgtable_arm_64_lpae_s2_init_fns; +extern struct io_pgtable_init_fns io_pgtable_arm_msm_secure_init_fns; +extern struct io_pgtable_init_fns io_pgtable_av8l_fast_init_fns; + static const struct io_pgtable_init_fns * io_pgtable_init_table[IO_PGTABLE_NUM_FMTS] = { @@ -33,8 +46,16 @@ [ARM_64_LPAE_S1] = &io_pgtable_arm_64_lpae_s1_init_fns, [ARM_64_LPAE_S2] = &io_pgtable_arm_64_lpae_s2_init_fns, #endif +#ifdef CONFIG_MSM_TZ_SMMU + [ARM_MSM_SECURE] = &io_pgtable_arm_msm_secure_init_fns, +#endif +#ifdef CONFIG_IOMMU_IO_PGTABLE_FAST + [ARM_V8L_FAST] = &io_pgtable_av8l_fast_init_fns, +#endif }; +static struct dentry *io_pgtable_top; + struct io_pgtable_ops *alloc_io_pgtable_ops(enum io_pgtable_fmt fmt, struct io_pgtable_cfg *cfg, void *cookie) @@ -72,6 +93,58 @@ return; iop = container_of(ops, struct io_pgtable, ops); - iop->cfg.tlb->tlb_flush_all(iop->cookie); io_pgtable_init_table[iop->fmt]->free(iop); } + +static atomic_t pages_allocated; + +void *io_pgtable_alloc_pages_exact(struct io_pgtable_cfg *cfg, void *cookie, + size_t size, gfp_t gfp_mask) +{ + void *ret; + + if (cfg->tlb->alloc_pages_exact) + ret = cfg->tlb->alloc_pages_exact(cookie, size, gfp_mask); + else + ret = alloc_pages_exact(size, gfp_mask); + + if (likely(ret)) + atomic_add(1 << get_order(size), &pages_allocated); + + return ret; +} + +void io_pgtable_free_pages_exact(struct io_pgtable_cfg *cfg, void *cookie, + void *virt, size_t size) +{ + if (cfg->tlb->free_pages_exact) + cfg->tlb->free_pages_exact(cookie, virt, size); + else + free_pages_exact(virt, size); + + atomic_sub(1 << get_order(size), &pages_allocated); +} + +static int io_pgtable_init(void) +{ + io_pgtable_top = debugfs_create_dir("io-pgtable", iommu_debugfs_top); + + if (!io_pgtable_top) + return -ENODEV; + + if (!debugfs_create_atomic_t("pages", 0600, + io_pgtable_top, &pages_allocated)) { + debugfs_remove_recursive(io_pgtable_top); + return -ENODEV; + } + + return 0; +} + +static void io_pgtable_exit(void) +{ + debugfs_remove_recursive(io_pgtable_top); +} + +module_init(io_pgtable_init); +module_exit(io_pgtable_exit); diff -ruw linux-4.4.115/drivers/iommu/io-pgtable.h linux-4.4.115-fbx/drivers/iommu/io-pgtable.h --- linux-4.4.115/drivers/iommu/io-pgtable.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/iommu/io-pgtable.h 2019-01-22 16:16:24.063251478 +0100 @@ -1,6 +1,9 @@ #ifndef __IO_PGTABLE_H #define __IO_PGTABLE_H +#include +#include + /* * Public API for use by IOMMU drivers */ @@ -9,6 +12,8 @@ ARM_32_LPAE_S2, ARM_64_LPAE_S1, ARM_64_LPAE_S2, + ARM_MSM_SECURE, + ARM_V8L_FAST, IO_PGTABLE_NUM_FMTS, }; @@ -20,6 +25,10 @@ * @tlb_sync: Ensure any queued TLB invalidation has taken effect, and * any corresponding page table updates are visible to the * IOMMU. + * @alloc_pages_exact: Allocate page table memory (optional, defaults to + * alloc_pages_exact) + * @free_pages_exact: Free page table memory (optional, defaults to + * free_pages_exact) * * Note that these can all be called in atomic context and must therefore * not block. @@ -29,6 +38,8 @@ void (*tlb_add_flush)(unsigned long iova, size_t size, bool leaf, void *cookie); void (*tlb_sync)(void *cookie); + void *(*alloc_pages_exact)(void *cookie, size_t size, gfp_t gfp_mask); + void (*free_pages_exact)(void *cookie, void *virt, size_t size); }; /** @@ -45,13 +56,22 @@ * page table walker. */ struct io_pgtable_cfg { + /* + * IO_PGTABLE_QUIRK_PAGE_TABLE_COHERENT: Set the page table as + * coherent. + */ #define IO_PGTABLE_QUIRK_ARM_NS (1 << 0) /* Set NS bit in PTEs */ + #define IO_PGTABLE_QUIRK_PAGE_TABLE_COHERENT (1 << 1) + #define IO_PGTABLE_QUIRK_ARM_TTBR1 (1 << 2) /* Allocate TTBR1 PT */ int quirks; unsigned long pgsize_bitmap; unsigned int ias; unsigned int oas; + int sep; const struct iommu_gather_ops *tlb; struct device *iommu_dev; + dma_addr_t iova_base; + dma_addr_t iova_end; /* Low-level data specific to the table format */ union { @@ -65,6 +85,18 @@ u64 vttbr; u64 vtcr; } arm_lpae_s2_cfg; + + struct { + enum tz_smmu_device_id sec_id; + int cbndx; + } arm_msm_secure_cfg; + + struct { + u64 ttbr[2]; + u64 tcr; + u64 mair[2]; + void *pmds; + } av8l_fast_cfg; }; }; @@ -72,6 +104,9 @@ * struct io_pgtable_ops - Page table manipulation API for IOMMU drivers. * * @map: Map a physically contiguous memory region. + * @map_sg: Map a scatterlist. Returns the number of bytes mapped, + * or 0 on failure. The size parameter contains the size + * of the partial mapping in case of failure. * @unmap: Unmap a physically contiguous memory region. * @iova_to_phys: Translate iova to physical address. * @@ -81,10 +116,18 @@ struct io_pgtable_ops { int (*map)(struct io_pgtable_ops *ops, unsigned long iova, phys_addr_t paddr, size_t size, int prot); - int (*unmap)(struct io_pgtable_ops *ops, unsigned long iova, + int (*map_sg)(struct io_pgtable_ops *ops, unsigned long iova, + struct scatterlist *sg, unsigned int nents, + int prot, size_t *size); + size_t (*unmap)(struct io_pgtable_ops *ops, unsigned long iova, size_t size); phys_addr_t (*iova_to_phys)(struct io_pgtable_ops *ops, unsigned long iova); + bool (*is_iova_coherent)(struct io_pgtable_ops *ops, + unsigned long iova); + uint64_t (*iova_to_pte)(struct io_pgtable_ops *ops, + unsigned long iova); + }; /** @@ -143,6 +186,28 @@ void (*free)(struct io_pgtable *iop); }; +/** + * io_pgtable_alloc_pages_exact - allocate an exact number physically-contiguous pages. + * @size: the number of bytes to allocate + * @gfp_mask: GFP flags for the allocation + * + * Like alloc_pages_exact(), but with some additional accounting for debug + * purposes. + */ +void *io_pgtable_alloc_pages_exact(struct io_pgtable_cfg *cfg, void *cookie, + size_t size, gfp_t gfp_mask); + +/** + * io_pgtable_free_pages_exact - release memory allocated via io_pgtable_alloc_pages_exact() + * @virt: the value returned by alloc_pages_exact. + * @size: size of allocation, same value as passed to alloc_pages_exact(). + * + * Like free_pages_exact(), but with some additional accounting for debug + * purposes. + */ +void io_pgtable_free_pages_exact(struct io_pgtable_cfg *cfg, void *cookie, + void *virt, size_t size); + extern struct io_pgtable_init_fns io_pgtable_arm_32_lpae_s1_init_fns; extern struct io_pgtable_init_fns io_pgtable_arm_32_lpae_s2_init_fns; extern struct io_pgtable_init_fns io_pgtable_arm_64_lpae_s1_init_fns; diff -ruw linux-4.4.115/drivers/iommu/Kconfig linux-4.4.115-fbx/drivers/iommu/Kconfig --- linux-4.4.115/drivers/iommu/Kconfig 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/iommu/Kconfig 2019-01-22 16:16:24.051251369 +0100 @@ -39,6 +39,42 @@ If unsure, say N here. +config IOMMU_IO_PGTABLE_FAST + bool "Fast ARMv7/v8 Long Descriptor Format" + depends on ARM64_DMA_USE_IOMMU + help + Enable support for a subset of the ARM long descriptor pagetable + format. This allocator achieves fast performance by + pre-allocating and pre-populating page table memory up front. + only supports a 32 bit virtual address space. + + This implementation is mainly optimized for use cases where the + buffers are small (<= 64K) since it only supports 4K page sizes. + +config IOMMU_IO_PGTABLE_FAST_SELFTEST + bool "Fast IO pgtable selftests" + depends on IOMMU_IO_PGTABLE_FAST + help + Enable self-tests for "fast" page table allocator. This performs + a series of page-table consistency checks during boot. + + If unsure, say N here. + +config IOMMU_IO_PGTABLE_FAST_PROVE_TLB + bool "Prove correctness of TLB maintenance in the Fast DMA mapper" + depends on IOMMU_IO_PGTABLE_FAST + help + Enables some debug features that help prove correctness of TLB + maintenance routines in the Fast DMA mapper. This option will + slow things down considerably, so should only be used in a debug + configuration. This relies on the ability to set bits in an + invalid page table entry, which is disallowed on some hardware + due to errata. If you're running on such a platform then this + option can only be used with unit tests. It will break real use + cases. + + If unsure, say N here. + endmenu config IOMMU_IOVA @@ -66,24 +102,6 @@ PAMU can authorize memory access, remap the memory address, and remap I/O transaction types. -# MSM IOMMU support -config MSM_IOMMU - bool "MSM IOMMU Support" - depends on ARM - depends on ARCH_MSM8X60 || ARCH_MSM8960 || COMPILE_TEST - depends on BROKEN - select IOMMU_API - help - Support for the IOMMUs found on certain Qualcomm SOCs. - These IOMMUs allow virtualization of the address space used by most - cores within the multimedia subsystem. - - If unsure, say N here. - -config IOMMU_PGTABLES_L2 - def_bool y - depends on MSM_IOMMU && MMU && SMP && CPU_DCACHE_DISABLE=n - # AMD IOMMU support config AMD_IOMMU bool "AMD IOMMU support" @@ -366,6 +384,7 @@ select IOMMU_API select IOMMU_IO_PGTABLE_LPAE select ARM_DMA_USE_IOMMU if ARM + select ARM64_DMA_USE_IOMMU if ARM64 help Support for implementations of the ARM System MMU architecture versions 1 and 2. @@ -393,4 +412,34 @@ help Support for the IOMMU API for s390 PCI devices. +menuconfig IOMMU_DEBUG + bool "IOMMU Profiling and Debugging" + help + Makes available some additional IOMMU profiling and debugging + options. + +if IOMMU_DEBUG + +config IOMMU_DEBUG_TRACKING + bool "Track key IOMMU events" + select IOMMU_API + help + Enables additional debug tracking in the IOMMU framework code. + Tracking information and tests can be accessed through various + debugfs files. + + Say Y here if you need to debug IOMMU issues and are okay with + the performance penalty of the tracking. + +config IOMMU_TESTS + bool "Interactive IOMMU performance/functional tests" + select IOMMU_API + help + Enables a suite of IOMMU unit tests. The tests are runnable + through debugfs. Unlike the IOMMU_DEBUG_TRACKING option, the + impact of enabling this option to overal system performance + should be minimal. + +endif # IOMMU_DEBUG + endif # IOMMU_SUPPORT diff -ruw linux-4.4.115/drivers/iommu/Makefile linux-4.4.115-fbx/drivers/iommu/Makefile --- linux-4.4.115/drivers/iommu/Makefile 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/iommu/Makefile 2019-01-22 16:16:24.051251369 +0100 @@ -2,11 +2,14 @@ obj-$(CONFIG_IOMMU_API) += iommu-traces.o obj-$(CONFIG_IOMMU_API) += iommu-sysfs.o obj-$(CONFIG_IOMMU_DMA) += dma-iommu.o +obj-$(CONFIG_IOMMU_API) += msm_dma_iommu_mapping.o obj-$(CONFIG_IOMMU_IO_PGTABLE) += io-pgtable.o obj-$(CONFIG_IOMMU_IO_PGTABLE_LPAE) += io-pgtable-arm.o obj-$(CONFIG_IOMMU_IOVA) += iova.o +obj-$(CONFIG_MSM_TZ_SMMU) += io-pgtable-msm-secure.o +obj-$(CONFIG_IOMMU_IO_PGTABLE_FAST) += io-pgtable-fast.o dma-mapping-fast.o obj-$(CONFIG_OF_IOMMU) += of_iommu.o -obj-$(CONFIG_MSM_IOMMU) += msm_iommu.o msm_iommu_dev.o +obj-$(CONFIG_IOMMU_DEBUG) += iommu-debug.o obj-$(CONFIG_AMD_IOMMU) += amd_iommu.o amd_iommu_init.o obj-$(CONFIG_AMD_IOMMU_V2) += amd_iommu_v2.o obj-$(CONFIG_ARM_SMMU) += arm-smmu.o diff -ruw linux-4.4.115/drivers/irqchip/irq-gic.c linux-4.4.115-fbx/drivers/irqchip/irq-gic.c --- linux-4.4.115/drivers/irqchip/irq-gic.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/irqchip/irq-gic.c 2019-10-29 09:26:23.825204959 +0100 @@ -98,6 +98,11 @@ static u8 gic_cpu_map[NR_GIC_CPU_IF] __read_mostly; static struct static_key supports_deactivate = STATIC_KEY_INIT_TRUE; +/* + * Supported arch specific GIC irq extension. + * Default make them NULL. + */ +extern struct irq_chip gic_arch_extn; #ifndef MAX_GIC_NR #define MAX_GIC_NR 1 @@ -182,7 +187,13 @@ static void gic_mask_irq(struct irq_data *d) { + unsigned long flags; + + raw_spin_lock_irqsave(&irq_controller_lock, flags); gic_poke_irq(d, GIC_DIST_ENABLE_CLEAR); + if (gic_arch_extn.irq_mask) + gic_arch_extn.irq_mask(d); + raw_spin_unlock_irqrestore(&irq_controller_lock, flags); } static void gic_eoimode1_mask_irq(struct irq_data *d) @@ -202,11 +213,23 @@ static void gic_unmask_irq(struct irq_data *d) { + unsigned long flags; + + raw_spin_lock_irqsave(&irq_controller_lock, flags); + if (gic_arch_extn.irq_unmask) + gic_arch_extn.irq_unmask(d); gic_poke_irq(d, GIC_DIST_ENABLE_SET); + raw_spin_unlock_irqrestore(&irq_controller_lock, flags); } static void gic_eoi_irq(struct irq_data *d) { + if (gic_arch_extn.irq_eoi) { + raw_spin_lock(&irq_controller_lock); + gic_arch_extn.irq_eoi(d); + raw_spin_unlock(&irq_controller_lock); + } + writel_relaxed(gic_irq(d), gic_cpu_base(d) + GIC_CPU_EOI); } @@ -272,6 +295,8 @@ { void __iomem *base = gic_dist_base(d); unsigned int gicirq = gic_irq(d); + unsigned long flags; + int ret; /* Interrupt configuration for SGIs can't be changed */ if (gicirq < 16) @@ -282,7 +307,25 @@ type != IRQ_TYPE_EDGE_RISING) return -EINVAL; - return gic_configure_irq(gicirq, type, base, NULL); + raw_spin_lock_irqsave(&irq_controller_lock, flags); + + if (gic_arch_extn.irq_set_type) + gic_arch_extn.irq_set_type(d, type); + + ret = gic_configure_irq(gicirq, type, base, NULL); + + raw_spin_unlock_irqrestore(&irq_controller_lock, flags); + + return ret; +} + +static int gic_retrigger(struct irq_data *d) +{ + if (gic_arch_extn.irq_retrigger) + return gic_arch_extn.irq_retrigger(d); + + /* the genirq layer expects 0 if we can't retrigger in hardware */ + return 0; } static int gic_irq_set_vcpu_affinity(struct irq_data *d, void *vcpu) @@ -326,6 +369,21 @@ } #endif +#ifdef CONFIG_PM +static int gic_set_wake(struct irq_data *d, unsigned int on) +{ + int ret = -ENXIO; + + if (gic_arch_extn.irq_set_wake) + ret = gic_arch_extn.irq_set_wake(d, on); + + return ret; +} + +#else +#define gic_set_wake NULL +#endif + static void __exception_irq_entry gic_handle_irq(struct pt_regs *regs) { u32 irqstat, irqnr; @@ -396,9 +454,11 @@ .irq_unmask = gic_unmask_irq, .irq_eoi = gic_eoi_irq, .irq_set_type = gic_set_type, + .irq_retrigger = gic_retrigger, #ifdef CONFIG_SMP .irq_set_affinity = gic_set_affinity, #endif + .irq_set_wake = gic_set_wake, .irq_get_irqchip_state = gic_irq_get_irqchip_state, .irq_set_irqchip_state = gic_irq_set_irqchip_state, .flags = IRQCHIP_SET_TYPE_MASKED | @@ -707,7 +767,8 @@ gic_cpu_if_up(&gic_data[gic_nr]); } -static int gic_notifier(struct notifier_block *self, unsigned long cmd, void *v) +static int gic_notifier(struct notifier_block *self, unsigned long cmd, + void *aff_level) { int i; @@ -726,10 +787,19 @@ gic_cpu_restore(i); break; case CPU_CLUSTER_PM_ENTER: + /* + * Affinity level of the node + * eg: + * cpu level = 0 + * l2 level = 1 + * cci level = 2 + */ + if (!(unsigned long)aff_level) gic_dist_save(i); break; case CPU_CLUSTER_PM_ENTER_FAILED: case CPU_CLUSTER_PM_EXIT: + if (!(unsigned long)aff_level) gic_dist_restore(i); break; } @@ -1147,6 +1217,7 @@ pr_info("GIC: Using split EOI/Deactivate mode\n"); } + gic_chip.flags |= gic_arch_extn.flags; gic_dist_init(gic); gic_cpu_init(gic); gic_pm_init(gic); diff -ruw linux-4.4.115/drivers/irqchip/irq-gic-common.c linux-4.4.115-fbx/drivers/irqchip/irq-gic-common.c --- linux-4.4.115/drivers/irqchip/irq-gic-common.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/irqchip/irq-gic-common.c 2019-01-22 16:16:24.071251550 +0100 @@ -32,6 +32,19 @@ } } +/* + * Supported arch specific GIC irq extension. + * Default make them NULL. + */ +struct irq_chip gic_arch_extn = { + .irq_eoi = NULL, + .irq_mask = NULL, + .irq_unmask = NULL, + .irq_retrigger = NULL, + .irq_set_type = NULL, + .irq_set_wake = NULL, +}; + int gic_configure_irq(unsigned int irq, unsigned int type, void __iomem *base, void (*sync_access)(void)) { diff -ruw linux-4.4.115/drivers/irqchip/irq-gic-common.h linux-4.4.115-fbx/drivers/irqchip/irq-gic-common.h --- linux-4.4.115/drivers/irqchip/irq-gic-common.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/irqchip/irq-gic-common.h 2019-01-22 16:16:24.071251550 +0100 @@ -26,6 +26,9 @@ u32 iidr; u32 mask; }; +extern bool from_suspend; +extern struct irq_chip gic_arch_extn; +extern int msm_show_resume_irq_mask; int gic_configure_irq(unsigned int irq, unsigned int type, void __iomem *base, void (*sync_access)(void)); diff -ruw linux-4.4.115/drivers/irqchip/irq-gic-v3.c linux-4.4.115-fbx/drivers/irqchip/irq-gic-v3.c --- linux-4.4.115/drivers/irqchip/irq-gic-v3.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/irqchip/irq-gic-v3.c 2019-10-29 09:26:23.821204920 +0100 @@ -24,9 +24,12 @@ #include #include #include +#include #include #include +#include +#include #include #include @@ -48,6 +51,14 @@ u64 redist_stride; u32 nr_redist_regions; unsigned int irq_nr; +#ifdef CONFIG_PM + unsigned int wakeup_irqs[32]; + unsigned int enabled_irqs[32]; +#endif +#ifdef CONFIG_ARM_GIC_PANIC_HANDLER + u32 saved_dist_regs[0x400]; + u32 saved_router_regs[0x800]; +#endif }; static struct gic_chip_data gic_data __read_mostly; @@ -85,7 +96,7 @@ { u32 count = 1000000; /* 1s! */ - while (readl_relaxed(base + GICD_CTLR) & GICD_CTLR_RWP) { + while (readl_relaxed_no_log(base + GICD_CTLR) & GICD_CTLR_RWP) { count--; if (!count) { pr_err_ratelimited("RWP timeout, gone fishing\n"); @@ -120,6 +131,7 @@ } #endif +#ifdef CONFIG_ARM_GIC_V3_NO_ACCESS_CONTROL static void gic_enable_redist(bool enable) { void __iomem *rbase; @@ -153,6 +165,9 @@ pr_err_ratelimited("redistributor failed to %s...\n", enable ? "wakeup" : "sleep"); } +#else +static void gic_enable_redist(bool enable) { } +#endif /* * Routines to disable, enable, EOI and route interrupts @@ -167,7 +182,7 @@ else base = gic_data.dist_base; - return !!(readl_relaxed(base + offset + (gic_irq(d) / 32) * 4) & mask); + return !!(readl_relaxed_no_log(base + offset + (gic_irq(d) / 32) * 4) & mask); } static void gic_poke_irq(struct irq_data *d, u32 offset) @@ -184,12 +199,15 @@ rwp_wait = gic_dist_wait_for_rwp; } - writel_relaxed(mask, base + offset + (gic_irq(d) / 32) * 4); + writel_relaxed_no_log(mask, base + offset + (gic_irq(d) / 32) * 4); rwp_wait(); } static void gic_mask_irq(struct irq_data *d) { + if (gic_arch_extn.irq_mask) + gic_arch_extn.irq_mask(d); + gic_poke_irq(d, GICD_ICENABLER); } @@ -210,6 +228,8 @@ static void gic_unmask_irq(struct irq_data *d) { + if (gic_arch_extn.irq_unmask) + gic_arch_extn.irq_unmask(d); gic_poke_irq(d, GICD_ISENABLER); } @@ -267,9 +287,20 @@ return 0; } +static void gic_disable_irq(struct irq_data *d) +{ + /* don't lazy-disable PPIs */ + if (gic_irq(d) < 32) + gic_mask_irq(d); + if (gic_arch_extn.irq_disable) + gic_arch_extn.irq_disable(d); +} static void gic_eoi_irq(struct irq_data *d) { + if (gic_arch_extn.irq_eoi) + gic_arch_extn.irq_eoi(d); + gic_write_eoir(gic_irq(d)); } @@ -307,6 +338,9 @@ rwp_wait = gic_dist_wait_for_rwp; } + if (gic_arch_extn.irq_set_type) + gic_arch_extn.irq_set_type(d, type); + return gic_configure_irq(irq, type, base, rwp_wait); } @@ -319,6 +353,134 @@ return 0; } +static int gic_retrigger(struct irq_data *d) +{ + if (gic_arch_extn.irq_retrigger) + return gic_arch_extn.irq_retrigger(d); + + /* the genirq layer expects 0 if we can't retrigger in hardware */ + return 0; +} + +static inline void __iomem *gic_data_dist_base(struct gic_chip_data *data) +{ + return data->dist_base; +} + +#ifdef CONFIG_ARM_GIC_PANIC_HANDLER +static int gic_panic_handler(struct notifier_block *this, + unsigned long event, void *ptr) +{ + int i; + void __iomem *base; + + base = gic_data.dist_base; + for (i = 0; i < 0x400; i += 1) + gic_data.saved_dist_regs[i] = readl_relaxed(base + 4 * i); + + base = gic_data.dist_base + GICD_IROUTER; + for (i = 0; i < 0x800; i += 1) + gic_data.saved_router_regs[i] = readl_relaxed(base + 4 * i); + + return NOTIFY_DONE; +} + +static struct notifier_block gic_panic_blk = { + .notifier_call = gic_panic_handler, +}; +#endif + +#ifdef CONFIG_PM +static int gic_suspend_one(struct gic_chip_data *gic) +{ + unsigned int i; + void __iomem *base = gic_data_dist_base(gic); + + for (i = 0; i * 32 < gic->irq_nr; i++) { + gic->enabled_irqs[i] + = readl_relaxed(base + GICD_ISENABLER + i * 4); + /* disable all of them */ + writel_relaxed(0xffffffff, base + GICD_ICENABLER + i * 4); + /* enable the wakeup set */ + writel_relaxed(gic->wakeup_irqs[i], + base + GICD_ISENABLER + i * 4); + } + return 0; +} + +static int gic_suspend(void) +{ + gic_suspend_one(&gic_data); + return 0; +} + +static void gic_show_resume_irq(struct gic_chip_data *gic) +{ + unsigned int i; + u32 enabled; + u32 pending[32]; + void __iomem *base = gic_data_dist_base(gic); + + if (!msm_show_resume_irq_mask) + return; + + for (i = 0; i * 32 < gic->irq_nr; i++) { + enabled = readl_relaxed(base + GICD_ICENABLER + i * 4); + pending[i] = readl_relaxed(base + GICD_ISPENDR + i * 4); + pending[i] &= enabled; + } + + for (i = find_first_bit((unsigned long *)pending, gic->irq_nr); + i < gic->irq_nr; + i = find_next_bit((unsigned long *)pending, gic->irq_nr, i+1)) { + unsigned int irq = irq_find_mapping(gic->domain, i); + struct irq_desc *desc = irq_to_desc(irq); + const char *name = "null"; + + if (desc == NULL) + name = "stray irq"; + else if (desc->action && desc->action->name) + name = desc->action->name; + + pr_warn("%s: %d triggered %s\n", __func__, irq, name); + } +} + +static void gic_resume_one(struct gic_chip_data *gic) +{ + unsigned int i; + void __iomem *base = gic_data_dist_base(gic); + + gic_show_resume_irq(gic); + + for (i = 0; i * 32 < gic->irq_nr; i++) { + /* disable all of them */ + writel_relaxed(0xffffffff, base + GICD_ICENABLER + i * 4); + /* enable the enabled set */ + writel_relaxed(gic->enabled_irqs[i], + base + GICD_ISENABLER + i * 4); + } +} + +static void gic_resume(void) +{ + gic_resume_one(&gic_data); +} + +static struct syscore_ops gic_syscore_ops = { + .suspend = gic_suspend, + .resume = gic_resume, +}; + +static int __init gic_init_sys(void) +{ + register_syscore_ops(&gic_syscore_ops); + return 0; +} +arch_initcall(gic_init_sys); + +#endif + static u64 gic_mpidr_to_affinity(unsigned long mpidr) { u64 aff; @@ -340,7 +502,7 @@ if (likely(irqnr > 15 && irqnr < 1020) || irqnr >= 8192) { int err; - + uncached_logk(LOGK_IRQ, (void *)(uintptr_t)irqnr); if (static_key_true(&supports_deactivate)) gic_write_eoir(irqnr); @@ -357,6 +519,7 @@ continue; } if (irqnr < 16) { + uncached_logk(LOGK_IRQ, (void *)(uintptr_t)irqnr); gic_write_eoir(irqnr); if (static_key_true(&supports_deactivate)) gic_write_dir(irqnr); @@ -444,9 +607,6 @@ u64 offset = ptr - gic_data.redist_regions[i].redist_base; gic_data_rdist_rd_base() = ptr; gic_data_rdist()->phys_base = gic_data.redist_regions[i].phys_base + offset; - pr_info("CPU%d: found redistributor %lx region %d:%pa\n", - smp_processor_id(), mpidr, i, - &gic_data_rdist()->phys_base); return 0; } @@ -516,7 +676,8 @@ gic_cpu_config(rbase, gic_redist_wait_for_rwp); /* Give LPIs a spin */ - if (IS_ENABLED(CONFIG_ARM_GIC_V3_ITS) && gic_dist_supports_lpis()) + if (IS_ENABLED(CONFIG_ARM_GIC_V3_ITS) && gic_dist_supports_lpis() && + !IS_ENABLED(CONFIG_ARM_GIC_V3_ACL)) its_cpu_init(); /* initialise system registers */ @@ -649,6 +810,14 @@ gic_write_irouter(val, reg); /* + * It is possible that irq is disabled from SW perspective only, + * because kernel takes lazy disable approach. Therefore check irq + * descriptor if it should kept disabled. + */ + if (irqd_irq_disabled(d)) + enabled = 0; + + /* * If the interrupt was enabled, enabled it again. Otherwise, * just wait for the distributor to have digested our changes. */ @@ -664,10 +833,44 @@ #define gic_smp_init() do { } while(0) #endif +#ifdef CONFIG_PM +int gic_set_wake(struct irq_data *d, unsigned int on) +{ + int ret = -ENXIO; + unsigned int reg_offset, bit_offset; + unsigned int gicirq = gic_irq(d); + struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d); + + /* per-cpu interrupts cannot be wakeup interrupts */ + WARN_ON(gicirq < 32); + + reg_offset = gicirq / 32; + bit_offset = gicirq % 32; + + if (on) + gic_data->wakeup_irqs[reg_offset] |= 1 << bit_offset; + else + gic_data->wakeup_irqs[reg_offset] &= ~(1 << bit_offset); + + if (gic_arch_extn.irq_set_wake) + ret = gic_arch_extn.irq_set_wake(d, on); + else + pr_err("mpm: set wake is null\n"); + + return ret; +} + +#else +#define gic_set_wake NULL +#endif + #ifdef CONFIG_CPU_PM static int gic_cpu_pm_notifier(struct notifier_block *self, unsigned long cmd, void *v) { + if (from_suspend) + return NOTIFY_OK; + if (cmd == CPU_PM_EXIT) { gic_enable_redist(true); gic_cpu_sys_reg_init(); @@ -691,13 +894,16 @@ static inline void gic_cpu_pm_init(void) { } #endif /* CONFIG_CPU_PM */ -static struct irq_chip gic_chip = { +struct irq_chip gic_chip = { .name = "GICv3", .irq_mask = gic_mask_irq, .irq_unmask = gic_unmask_irq, .irq_eoi = gic_eoi_irq, .irq_set_type = gic_set_type, + .irq_retrigger = gic_retrigger, .irq_set_affinity = gic_set_affinity, + .irq_disable = gic_disable_irq, + .irq_set_wake = gic_set_wake, .irq_get_irqchip_state = gic_irq_get_irqchip_state, .irq_set_irqchip_state = gic_irq_set_irqchip_state, .flags = IRQCHIP_SET_TYPE_MASKED, @@ -714,6 +920,7 @@ .irq_set_irqchip_state = gic_irq_set_irqchip_state, .irq_set_vcpu_affinity = gic_irq_set_vcpu_affinity, .flags = IRQCHIP_SET_TYPE_MASKED, + .irq_set_wake = gic_set_wake, }; #define GIC_ID_NR (1U << gic_data.rdists.id_bits) @@ -923,13 +1130,20 @@ set_handle_irq(gic_handle_irq); - if (IS_ENABLED(CONFIG_ARM_GIC_V3_ITS) && gic_dist_supports_lpis()) + if (IS_ENABLED(CONFIG_ARM_GIC_V3_ITS) && gic_dist_supports_lpis() && + !IS_ENABLED(CONFIG_ARM_GIC_V3_ACL)) its_init(node, &gic_data.rdists, gic_data.domain); + gic_chip.flags |= gic_arch_extn.flags; gic_smp_init(); gic_dist_init(); gic_cpu_init(); gic_cpu_pm_init(); + of_mpm_init(); + +#ifdef CONFIG_ARM_GIC_PANIC_HANDLER + atomic_notifier_chain_register(&panic_notifier_list, &gic_panic_blk); +#endif return 0; diff -ruw linux-4.4.115/drivers/irqchip/Kconfig linux-4.4.115-fbx/drivers/irqchip/Kconfig --- linux-4.4.115/drivers/irqchip/Kconfig 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/irqchip/Kconfig 2019-10-29 09:26:23.821204920 +0100 @@ -7,6 +7,7 @@ select IRQ_DOMAIN select IRQ_DOMAIN_HIERARCHY select MULTI_IRQ_HANDLER + select QCOM_SHOW_RESUME_IRQ config ARM_GIC_V2M bool @@ -27,6 +28,25 @@ bool select PCI_MSI_IRQ_DOMAIN +config ARM_GIC_V3_ACL + bool "GICv3 Access control" + depends on ARM_GIC_V3 + help + Access to GIC ITS address space is controlled by EL2. + Kernel has no permission to access ITS + +config ARM_GIC_V3_NO_ACCESS_CONTROL + bool "GICv3 No Access Control Configuration" + depends on ARM_GIC_V3 + help + On some SOCs with the access control configurations it is + not allowed to access certain set of the GIC registers + from non-secure world. Provide a common flag to protect + those functionalities and compile them out for such + configurations, so that specific registers are not touched. + + For production kernels, you should say 'N' here. + config ARM_NVIC bool select IRQ_DOMAIN @@ -80,6 +100,16 @@ select GENERIC_IRQ_CHIP select IRQ_DOMAIN +config QCOM_SHOW_RESUME_IRQ + bool "Enable logging of interrupts that could have caused resume" + depends on ARM_GIC + default n + help + This option logs wake up interrupts that have triggered just before + the resume loop unrolls. It helps to debug to know any unnecessary + wake up interrupts that causes system to come out of low power modes. + Say Y if you want to debug why the system resumed. + config DW_APB_ICTL bool select GENERIC_IRQ_CHIP @@ -193,3 +223,7 @@ def_bool y if MACH_ASM9260 || ARCH_MXS select IRQ_DOMAIN select STMP_DEVICE + +config MSM_IRQ + bool + select IRQ_DOMAIN diff -ruw linux-4.4.115/drivers/irqchip/Makefile linux-4.4.115-fbx/drivers/irqchip/Makefile --- linux-4.4.115/drivers/irqchip/Makefile 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/irqchip/Makefile 2019-10-29 09:26:23.821204920 +0100 @@ -55,3 +55,4 @@ obj-$(CONFIG_ARCH_SA1100) += irq-sa11x0.o obj-$(CONFIG_INGENIC_IRQ) += irq-ingenic.o obj-$(CONFIG_IMX_GPCV2) += irq-imx-gpcv2.o +obj-$(CONFIG_QCOM_SHOW_RESUME_IRQ) += msm_show_resume_irq.o diff -ruw linux-4.4.115/drivers/Kconfig linux-4.4.115-fbx/drivers/Kconfig --- linux-4.4.115/drivers/Kconfig 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/Kconfig 2019-01-22 16:16:22.767239742 +0100 @@ -8,6 +8,8 @@ source "drivers/connector/Kconfig" +source "drivers/fbxprocfs/Kconfig" + source "drivers/mtd/Kconfig" source "drivers/of/Kconfig" @@ -54,6 +56,10 @@ source "drivers/i2c/Kconfig" +source "drivers/slimbus/Kconfig" + +source "drivers/soundwire/Kconfig" + source "drivers/spi/Kconfig" source "drivers/spmi/Kconfig" @@ -68,6 +74,8 @@ source "drivers/gpio/Kconfig" +source "drivers/fbxgpio/Kconfig" + source "drivers/w1/Kconfig" source "drivers/power/Kconfig" @@ -104,6 +112,8 @@ source "drivers/leds/Kconfig" +source "drivers/switch/Kconfig" + source "drivers/accessibility/Kconfig" source "drivers/infiniband/Kconfig" @@ -112,6 +122,8 @@ source "drivers/rtc/Kconfig" +source "drivers/esoc/Kconfig" + source "drivers/dma/Kconfig" source "drivers/dca/Kconfig" @@ -198,4 +210,12 @@ source "drivers/fpga/Kconfig" +source "drivers/firmware/Kconfig" + +source "drivers/bif/Kconfig" + +source "drivers/sensors/Kconfig" + +source "drivers/tee/Kconfig" + endmenu diff -ruw linux-4.4.115/drivers/leds/Kconfig linux-4.4.115-fbx/drivers/leds/Kconfig --- linux-4.4.115/drivers/leds/Kconfig 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/leds/Kconfig 2019-10-29 09:26:23.841205116 +0100 @@ -587,6 +587,43 @@ To compile this driver as a module, choose 'm' here: the module will be called leds-powernv. +config LEDS_QPNP + tristate "Support for QPNP LEDs" + depends on LEDS_CLASS && SPMI + help + This driver supports the LED functionality of Qualcomm Technologies, + Inc. QPNP PMICs. It primarily supports controlling tri-color RGB + LEDs in both PWM and light pattern generator (LPG) modes. For older + PMICs, it also supports WLEDs and flash LEDs. + +config LEDS_QPNP_FLASH + tristate "Support for QPNP Flash LEDs" + depends on LEDS_CLASS && SPMI + help + This driver supports the flash LED functionality of Qualcomm + Technologies, Inc. QPNP PMICs. This driver supports PMICs up through + PM8994. It can configure the flash LED target current for several + independent channels. + +config LEDS_QPNP_FLASH_V2 + tristate "Support for QPNP V2 Flash LEDs" + depends on LEDS_CLASS && MFD_SPMI_PMIC && !LEDS_QPNP_FLASH + help + This driver supports the flash V2 LED functionality of Qualcomm + Technologies, Inc. QPNP PMICs. This driver supports PMICs starting + from PMI8998. It can configure the flash LED target current for + several independent channels. It also supports various over current + and over temperature mitigation features. + +config LEDS_QPNP_WLED + tristate "Support for QPNP WLED" + depends on LEDS_CLASS && SPMI + help + This driver supports the WLED (White LED) functionality of Qualcomm + Technologies, Inc. QPNP PMICs. WLED is used for LCD backlight with + variable brightness. It also supports outputting the Avdd supply for + AMOLED displays. + config LEDS_SYSCON bool "LED support for LEDs on system controllers" depends on LEDS_CLASS=y diff -ruw linux-4.4.115/drivers/leds/led-class.c linux-4.4.115-fbx/drivers/leds/led-class.c --- linux-4.4.115/drivers/leds/led-class.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/leds/led-class.c 2019-10-29 09:26:23.841205116 +0100 @@ -53,9 +53,10 @@ if (ret) goto unlock; - if (state == LED_OFF) + if (state == LED_OFF && !(led_cdev->flags & LED_KEEP_TRIGGER)) led_trigger_remove(led_cdev); led_set_brightness(led_cdev, state); + led_cdev->usr_brightness_req = state; ret = size; unlock: @@ -71,7 +72,24 @@ return sprintf(buf, "%u\n", led_cdev->max_brightness); } -static DEVICE_ATTR_RO(max_brightness); + +static ssize_t max_brightness_store(struct device *dev, + struct device_attribute *attr, const char *buf, size_t size) +{ + struct led_classdev *led_cdev = dev_get_drvdata(dev); + unsigned long state; + ssize_t ret = -EINVAL; + + ret = kstrtoul(buf, 10, &state); + if (ret) + return ret; + + led_cdev->max_brightness = state; + led_set_brightness(led_cdev, led_cdev->usr_brightness_req); + + return size; +} +static DEVICE_ATTR_RW(max_brightness); #ifdef CONFIG_LEDS_TRIGGERS static DEVICE_ATTR(trigger, 0644, led_trigger_show, led_trigger_store); diff -ruw linux-4.4.115/drivers/leds/leds.h linux-4.4.115-fbx/drivers/leds/leds.h --- linux-4.4.115/drivers/leds/leds.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/leds/leds.h 2019-01-22 16:16:24.151252275 +0100 @@ -44,6 +44,22 @@ return led_cdev->brightness; } +static inline struct led_classdev *trigger_to_lcdev(struct led_trigger *trig) +{ + struct led_classdev *led_cdev; + + read_lock(&trig->leddev_list_lock); + list_for_each_entry(led_cdev, &trig->led_cdevs, trig_list) { + if (!strcmp(led_cdev->default_trigger, trig->name)) { + read_unlock(&trig->leddev_list_lock); + return led_cdev; + } + } + + read_unlock(&trig->leddev_list_lock); + return NULL; +} + void led_init_core(struct led_classdev *led_cdev); void led_stop_software_blink(struct led_classdev *led_cdev); diff -ruw linux-4.4.115/drivers/leds/Makefile linux-4.4.115-fbx/drivers/leds/Makefile --- linux-4.4.115/drivers/leds/Makefile 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/leds/Makefile 2019-10-29 09:26:23.841205116 +0100 @@ -60,6 +60,10 @@ obj-$(CONFIG_LEDS_MAX8997) += leds-max8997.o obj-$(CONFIG_LEDS_LM355x) += leds-lm355x.o obj-$(CONFIG_LEDS_BLINKM) += leds-blinkm.o +obj-$(CONFIG_LEDS_QPNP) += leds-qpnp.o +obj-$(CONFIG_LEDS_QPNP_FLASH) += leds-qpnp-flash.o +obj-$(CONFIG_LEDS_QPNP_FLASH_V2) += leds-qpnp-flash-v2.o +obj-$(CONFIG_LEDS_QPNP_WLED) += leds-qpnp-wled.o obj-$(CONFIG_LEDS_SYSCON) += leds-syscon.o obj-$(CONFIG_LEDS_VERSATILE) += leds-versatile.o obj-$(CONFIG_LEDS_MENF21BMC) += leds-menf21bmc.o diff -ruw linux-4.4.115/drivers/Makefile linux-4.4.115-fbx/drivers/Makefile --- linux-4.4.115/drivers/Makefile 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/Makefile 2019-10-29 09:26:23.369200497 +0100 @@ -50,8 +50,6 @@ obj-y += tty/ obj-y += char/ -# iommu/ comes before gpu as gpu are using iommu controllers -obj-$(CONFIG_IOMMU_SUPPORT) += iommu/ # gpu/ comes after char for AGP vs DRM startup and after iommu obj-y += gpu/ @@ -64,12 +62,13 @@ obj-$(CONFIG_PARPORT) += parport/ obj-$(CONFIG_NVM) += lightnvm/ -obj-y += base/ block/ misc/ mfd/ nfc/ +obj-y += base/ block/ misc/ mfd/ nfc/ soc/ obj-$(CONFIG_LIBNVDIMM) += nvdimm/ obj-$(CONFIG_DMA_SHARED_BUFFER) += dma-buf/ obj-$(CONFIG_NUBUS) += nubus/ obj-y += macintosh/ obj-$(CONFIG_IDE) += ide/ +obj-$(CONFIG_CRYPTO) += crypto/ obj-$(CONFIG_SCSI) += scsi/ obj-y += nvme/ obj-$(CONFIG_ATA) += ata/ @@ -77,6 +76,8 @@ obj-$(CONFIG_MTD) += mtd/ obj-$(CONFIG_SPI) += spi/ obj-$(CONFIG_SPMI) += spmi/ +obj-$(CONFIG_SLIMBUS) += slimbus/ +obj-$(CONFIG_SOUNDWIRE) += soundwire/ obj-y += hsi/ obj-y += net/ obj-$(CONFIG_ATM) += atm/ @@ -123,10 +124,10 @@ obj-y += mmc/ obj-$(CONFIG_MEMSTICK) += memstick/ obj-y += leds/ +obj-$(CONFIG_SWITCH) += switch/ obj-$(CONFIG_INFINIBAND) += infiniband/ obj-$(CONFIG_SGI_SN) += sn/ obj-y += firmware/ -obj-$(CONFIG_CRYPTO) += crypto/ obj-$(CONFIG_SUPERH) += sh/ obj-$(CONFIG_ARCH_SHMOBILE) += sh/ ifndef CONFIG_ARCH_USES_GETTIMEOFFSET @@ -145,6 +146,9 @@ #common clk code obj-y += clk/ +# iommu/ comes before gpu as gpu are using iommu controllers +obj-$(CONFIG_IOMMU_SUPPORT) += iommu/ + obj-$(CONFIG_MAILBOX) += mailbox/ obj-$(CONFIG_HWSPINLOCK) += hwspinlock/ obj-$(CONFIG_REMOTEPROC) += remoteproc/ @@ -173,3 +177,12 @@ obj-$(CONFIG_ANDROID) += android/ obj-$(CONFIG_NVMEM) += nvmem/ obj-$(CONFIG_FPGA) += fpga/ + +obj-$(CONFIG_BIF) += bif/ + +obj-$(CONFIG_SENSORS_SSC) += sensors/ +obj-$(CONFIG_ESOC) += esoc/ +obj-$(CONFIG_TEE) += tee/ + +obj-$(CONFIG_FREEBOX_GPIO) += fbxgpio/ +obj-$(CONFIG_FREEBOX_PROCFS) += fbxprocfs/ diff -ruw linux-4.4.115/drivers/md/dm.c linux-4.4.115-fbx/drivers/md/dm.c --- linux-4.4.115/drivers/md/dm.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/md/dm.c 2019-10-29 09:26:23.869205390 +0100 @@ -1146,7 +1146,7 @@ * Must be called without clone's queue lock held, * see end_clone_request() for more details. */ -static void dm_end_request(struct request *clone, int error) +void dm_end_request(struct request *clone, int error) { int rw = rq_data_dir(clone); struct dm_rq_target_io *tio = clone->end_io_data; @@ -1344,7 +1344,7 @@ * Target's rq_end_io() function isn't called. * This may be used when the target's map_rq() or clone_and_map_rq() functions fail. */ -static void dm_kill_unmapped_request(struct request *rq, int error) +void dm_kill_unmapped_request(struct request *rq, int error) { rq->cmd_flags |= REQ_FAILED; dm_complete_request(rq, error); @@ -1861,6 +1861,13 @@ dm_complete_request(rq, r); } +void dm_dispatch_request(struct request *rq) +{ + struct dm_rq_target_io *tio = tio_from_request(rq); + + dm_dispatch_clone_request(tio->clone, rq); +} + static int dm_rq_bio_constructor(struct bio *bio, struct bio *bio_orig, void *data) { @@ -2184,8 +2191,11 @@ tio = tio_from_request(rq); /* Establish tio->ti before queuing work (map_tio_request) */ tio->ti = ti; - queue_kthread_work(&md->kworker, &tio->work); + spin_unlock(q->queue_lock); + if (map_request(tio, rq, md) == DM_MAPIO_REQUEUE) + dm_requeue_original_request(md, rq); BUG_ON(!irqs_disabled()); + spin_lock(q->queue_lock); } goto out; @@ -2210,7 +2220,7 @@ * the query about congestion status of request_queue */ if (dm_request_based(md)) - r = md->queue->backing_dev_info.wb.state & + r = md->queue->backing_dev_info->wb.state & bdi_bits; else r = dm_table_any_congested(map, bdi_bits); @@ -2292,7 +2302,7 @@ * - must do so here (in alloc_dev callchain) before queue is used */ md->queue->queuedata = md; - md->queue->backing_dev_info.congested_data = md; + md->queue->backing_dev_info->congested_data = md; } static void dm_init_old_md_queue(struct mapped_device *md) @@ -2303,7 +2313,7 @@ /* * Initialize aspects of queue that aren't relevant for blk-mq */ - md->queue->backing_dev_info.congested_fn = dm_any_congested; + md->queue->backing_dev_info->congested_fn = dm_any_congested; blk_queue_bounce_limit(md->queue, BLK_BOUNCE_ANY); } diff -ruw linux-4.4.115/drivers/md/dm-crypt.c linux-4.4.115-fbx/drivers/md/dm-crypt.c --- linux-4.4.115/drivers/md/dm-crypt.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/md/dm-crypt.c 2019-01-22 16:16:24.175252492 +0100 @@ -1863,16 +1863,24 @@ } ret = -ENOMEM; - cc->io_queue = alloc_workqueue("kcryptd_io", WQ_MEM_RECLAIM, 1); + cc->io_queue = alloc_workqueue("kcryptd_io", + WQ_HIGHPRI | + WQ_MEM_RECLAIM, + 1); if (!cc->io_queue) { ti->error = "Couldn't create kcryptd io queue"; goto bad; } if (test_bit(DM_CRYPT_SAME_CPU, &cc->flags)) - cc->crypt_queue = alloc_workqueue("kcryptd", WQ_CPU_INTENSIVE | WQ_MEM_RECLAIM, 1); + cc->crypt_queue = alloc_workqueue("kcryptd", + WQ_HIGHPRI | + WQ_MEM_RECLAIM, 1); else - cc->crypt_queue = alloc_workqueue("kcryptd", WQ_CPU_INTENSIVE | WQ_MEM_RECLAIM | WQ_UNBOUND, + cc->crypt_queue = alloc_workqueue("kcryptd", + WQ_HIGHPRI | + WQ_MEM_RECLAIM | + WQ_UNBOUND, num_online_cpus()); if (!cc->crypt_queue) { ti->error = "Couldn't create kcryptd queue"; diff -ruw linux-4.4.115/drivers/md/dm-ioctl.c linux-4.4.115-fbx/drivers/md/dm-ioctl.c --- linux-4.4.115/drivers/md/dm-ioctl.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/md/dm-ioctl.c 2019-10-29 09:26:23.861205311 +0100 @@ -1923,6 +1923,45 @@ dm_hash_exit(); } + +/** + * dm_ioctl_export - Permanently export a mapped device via the ioctl interface + * @md: Pointer to mapped_device + * @name: Buffer (size DM_NAME_LEN) for name + * @uuid: Buffer (size DM_UUID_LEN) for uuid or NULL if not desired + */ +int dm_ioctl_export(struct mapped_device *md, const char *name, + const char *uuid) +{ + int r = 0; + struct hash_cell *hc; + + if (!md) { + r = -ENXIO; + goto out; + } + + /* The name and uuid can only be set once. */ + mutex_lock(&dm_hash_cells_mutex); + hc = dm_get_mdptr(md); + mutex_unlock(&dm_hash_cells_mutex); + if (hc) { + DMERR("%s: already exported", dm_device_name(md)); + r = -ENXIO; + goto out; + } + + r = dm_hash_insert(name, uuid, md); + if (r) { + DMERR("%s: could not bind to '%s'", dm_device_name(md), name); + goto out; + } + + /* Let udev know we've changed. */ + dm_kobject_uevent(md, KOBJ_CHANGE, dm_get_event_nr(md)); +out: + return r; +} /** * dm_copy_name_and_uuid - Copy mapped device name & uuid into supplied buffers * @md: Pointer to mapped_device diff -ruw linux-4.4.115/drivers/md/dm-linear.c linux-4.4.115-fbx/drivers/md/dm-linear.c --- linux-4.4.115/drivers/md/dm-linear.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/md/dm-linear.c 2019-01-22 16:16:24.179252528 +0100 @@ -25,7 +25,7 @@ /* * Construct a linear mapping: */ -static int linear_ctr(struct dm_target *ti, unsigned int argc, char **argv) +int dm_linear_ctr(struct dm_target *ti, unsigned int argc, char **argv) { struct linear_c *lc; unsigned long long tmp; @@ -66,14 +66,16 @@ kfree(lc); return ret; } +EXPORT_SYMBOL_GPL(dm_linear_ctr); -static void linear_dtr(struct dm_target *ti) +void dm_linear_dtr(struct dm_target *ti) { struct linear_c *lc = (struct linear_c *) ti->private; dm_put_device(ti, lc->dev); kfree(lc); } +EXPORT_SYMBOL_GPL(dm_linear_dtr); static sector_t linear_map_sector(struct dm_target *ti, sector_t bi_sector) { @@ -92,14 +94,15 @@ linear_map_sector(ti, bio->bi_iter.bi_sector); } -static int linear_map(struct dm_target *ti, struct bio *bio) +int dm_linear_map(struct dm_target *ti, struct bio *bio) { linear_map_bio(ti, bio); return DM_MAPIO_REMAPPED; } +EXPORT_SYMBOL_GPL(dm_linear_map); -static void linear_status(struct dm_target *ti, status_type_t type, +void dm_linear_status(struct dm_target *ti, status_type_t type, unsigned status_flags, char *result, unsigned maxlen) { struct linear_c *lc = (struct linear_c *) ti->private; @@ -115,8 +118,9 @@ break; } } +EXPORT_SYMBOL_GPL(dm_linear_status); -static int linear_prepare_ioctl(struct dm_target *ti, +int dm_linear_prepare_ioctl(struct dm_target *ti, struct block_device **bdev, fmode_t *mode) { struct linear_c *lc = (struct linear_c *) ti->private; @@ -132,25 +136,27 @@ return 1; return 0; } +EXPORT_SYMBOL_GPL(dm_linear_prepare_ioctl); -static int linear_iterate_devices(struct dm_target *ti, +int dm_linear_iterate_devices(struct dm_target *ti, iterate_devices_callout_fn fn, void *data) { struct linear_c *lc = ti->private; return fn(ti, lc->dev, lc->start, ti->len, data); } +EXPORT_SYMBOL_GPL(dm_linear_iterate_devices); static struct target_type linear_target = { .name = "linear", .version = {1, 2, 1}, .module = THIS_MODULE, - .ctr = linear_ctr, - .dtr = linear_dtr, - .map = linear_map, - .status = linear_status, - .prepare_ioctl = linear_prepare_ioctl, - .iterate_devices = linear_iterate_devices, + .ctr = dm_linear_ctr, + .dtr = dm_linear_dtr, + .map = dm_linear_map, + .status = dm_linear_status, + .prepare_ioctl = dm_linear_prepare_ioctl, + .iterate_devices = dm_linear_iterate_devices, }; int __init dm_linear_init(void) diff -ruw linux-4.4.115/drivers/md/dm-table.c linux-4.4.115-fbx/drivers/md/dm-table.c --- linux-4.4.115/drivers/md/dm-table.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/md/dm-table.c 2019-10-29 09:26:23.865205351 +0100 @@ -11,6 +11,7 @@ #include #include #include +#include #include #include #include @@ -1659,7 +1660,7 @@ char b[BDEVNAME_SIZE]; if (likely(q)) - r |= bdi_congested(&q->backing_dev_info, bdi_bits); + r |= bdi_congested(q->backing_dev_info, bdi_bits); else DMWARN_LIMIT("%s: any_congested: nonexistent device %s", dm_device_name(t->md), diff -ruw linux-4.4.115/drivers/md/Kconfig linux-4.4.115-fbx/drivers/md/Kconfig --- linux-4.4.115/drivers/md/Kconfig 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/md/Kconfig 2019-10-29 09:26:23.849205194 +0100 @@ -267,6 +267,23 @@ If unsure, say N. +config DM_REQ_CRYPT + tristate "Req Crypt target support" + depends on BLK_DEV_DM + select XTS + select CRYPTO_XTS + ---help--- + This request based device-mapper target allows you to create a device that + transparently encrypts the data on it. You'll need to activate + the ciphers you're going to use in the cryptoapi configuration. + The DM REQ CRYPT operates on requests (bigger payloads) to utilize + crypto hardware better. + + To compile this code as a module, choose M here: the module will + be called dm-req-crypt. + + If unsure, say N. + config DM_SNAPSHOT tristate "Snapshot target" depends on BLK_DEV_DM @@ -459,6 +476,33 @@ If unsure, say N. +config DM_VERITY_HASH_PREFETCH_MIN_SIZE_128 + bool "Prefetch size 128" + +config DM_VERITY_HASH_PREFETCH_MIN_SIZE + int "Verity hash prefetch minimum size" + depends on DM_VERITY + range 1 4096 + default 128 if DM_VERITY_HASH_PREFETCH_MIN_SIZE_128 + default 1 + ---help--- + This sets minimum number of hash blocks to prefetch for dm-verity. + For devices like eMMC, having larger prefetch size like 128 can improve + performance with increased memory consumption for keeping more hashes + in RAM. + +config DM_VERITY_FEC + bool "Verity forward error correction support" + depends on DM_VERITY + select REED_SOLOMON + select REED_SOLOMON_DEC8 + ---help--- + Add forward error correction support to dm-verity. This option + makes it possible to use pre-generated error correction data to + recover from corrupted blocks. + + If unsure, say N. + config DM_SWITCH tristate "Switch target support (EXPERIMENTAL)" depends on BLK_DEV_DM @@ -489,4 +533,33 @@ If unsure, say N. +config DM_VERITY_AVB + tristate "Support AVB specific verity error behavior" + depends on DM_VERITY + ---help--- + Enables Android Verified Boot platform-specific error + behavior. In particular, it will modify the vbmeta partition + specified on the kernel command-line when non-transient error + occurs (followed by a panic). + + If unsure, say N. + +config DM_ANDROID_VERITY + bool "Android verity target support" + depends on DM_VERITY=y + depends on X509_CERTIFICATE_PARSER + depends on SYSTEM_TRUSTED_KEYRING + depends on PUBLIC_KEY_ALGO_RSA + depends on KEYS + depends on ASYMMETRIC_KEY_TYPE + depends on ASYMMETRIC_PUBLIC_KEY_SUBTYPE + depends on MD_LINEAR=y + select DM_VERITY_HASH_PREFETCH_MIN_SIZE_128 + ---help--- + This device-mapper target is virtually a VERITY target. This + target is setup by reading the metadata contents piggybacked + to the actual data blocks in the block device. The signature + of the metadata contents are verified against the key included + in the system keyring. Upon success, the underlying verity + target is setup. endif # MD diff -ruw linux-4.4.115/drivers/md/Makefile linux-4.4.115-fbx/drivers/md/Makefile --- linux-4.4.115/drivers/md/Makefile 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/md/Makefile 2019-01-22 16:16:24.167252419 +0100 @@ -16,6 +16,7 @@ dm-cache-smq-y += dm-cache-policy-smq.o dm-cache-cleaner-y += dm-cache-policy-cleaner.o dm-era-y += dm-era-target.o +dm-verity-y += dm-verity-target.o md-mod-y += md.o bitmap.o raid456-y += raid5.o raid5-cache.o @@ -59,7 +60,17 @@ obj-$(CONFIG_DM_CACHE_CLEANER) += dm-cache-cleaner.o obj-$(CONFIG_DM_ERA) += dm-era.o obj-$(CONFIG_DM_LOG_WRITES) += dm-log-writes.o +obj-$(CONFIG_DM_REQ_CRYPT) += dm-req-crypt.o +obj-$(CONFIG_DM_ANDROID_VERITY) += dm-android-verity.o ifeq ($(CONFIG_DM_UEVENT),y) dm-mod-objs += dm-uevent.o endif + +ifeq ($(CONFIG_DM_VERITY_FEC),y) +dm-verity-objs += dm-verity-fec.o +endif + +ifeq ($(CONFIG_DM_VERITY_AVB),y) +dm-verity-objs += dm-verity-avb.o +endif diff -ruw linux-4.4.115/drivers/media/dvb-frontends/si2168.c linux-4.4.115-fbx/drivers/media/dvb-frontends/si2168.c --- linux-4.4.115/drivers/media/dvb-frontends/si2168.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/media/dvb-frontends/si2168.c 2019-01-22 16:16:24.267253325 +0100 @@ -14,6 +14,8 @@ * GNU General Public License for more details. */ +#include + #include "si2168_priv.h" static const struct dvb_frontend_ops si2168_ops; @@ -120,12 +122,37 @@ return ret; } +static int si2168_ts_bus_ctrl(struct dvb_frontend *fe, int acquire) +{ + struct i2c_client *client = fe->demodulator_priv; + struct si2168_dev *dev = i2c_get_clientdata(client); + struct si2168_cmd cmd; + int ret = 0; + + dev_dbg(&client->dev, "%s acquire: %d\n", __func__, acquire); + + /* set TS_MODE property */ + memcpy(cmd.args, "\x14\x00\x01\x10\x10\x00", 6); + if (acquire) + cmd.args[4] |= dev->ts_mode; + else + cmd.args[4] |= SI2168_TS_TRISTATE; + if (dev->ts_clock_gapped) + cmd.args[4] |= 0x40; + cmd.wlen = 6; + cmd.rlen = 4; + ret = si2168_cmd_execute(client, &cmd); + + return ret; +} + static int si2168_read_status(struct dvb_frontend *fe, enum fe_status *status) { struct i2c_client *client = fe->demodulator_priv; struct si2168_dev *dev = i2c_get_clientdata(client); struct dtv_frontend_properties *c = &fe->dtv_property_cache; - int ret; + int ret, i; + unsigned int utmp, utmp1, utmp2; struct si2168_cmd cmd; *status = 0; @@ -184,6 +211,61 @@ dev_dbg(&client->dev, "status=%02x args=%*ph\n", *status, cmd.rlen, cmd.args); + /* BER */ + if (*status & FE_HAS_VITERBI) { + memcpy(cmd.args, "\x82\x00", 2); + cmd.wlen = 2; + cmd.rlen = 3; + ret = si2168_cmd_execute(client, &cmd); + if (ret) + goto err; + + /* + * Firmware returns [0, 255] mantissa and [0, 8] exponent. + * Convert to DVB API: mantissa * 10^(8 - exponent) / 10^8 + */ + utmp = clamp(8 - cmd.args[1], 0, 8); + for (i = 0, utmp1 = 1; i < utmp; i++) + utmp1 = utmp1 * 10; + + utmp1 = cmd.args[2] * utmp1; + utmp2 = 100000000; /* 10^8 */ + + dev_dbg(&client->dev, + "post_bit_error=%u post_bit_count=%u ber=%u*10^-%u\n", + utmp1, utmp2, cmd.args[2], cmd.args[1]); + + c->post_bit_error.stat[0].scale = FE_SCALE_COUNTER; + c->post_bit_error.stat[0].uvalue += utmp1; + c->post_bit_count.stat[0].scale = FE_SCALE_COUNTER; + c->post_bit_count.stat[0].uvalue += utmp2; + } else { + c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; + c->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; + } + + /* UCB */ + if (*status & FE_HAS_SYNC) { + memcpy(cmd.args, "\x84\x01", 2); + cmd.wlen = 2; + cmd.rlen = 3; + ret = si2168_cmd_execute(client, &cmd); + if (ret) + goto err; + + utmp1 = cmd.args[2] << 8 | cmd.args[1] << 0; + dev_dbg(&client->dev, "block_error=%u\n", utmp1); + + /* Sometimes firmware returns bogus value */ + if (utmp1 == 0xffff) + utmp1 = 0; + + c->block_error.stat[0].scale = FE_SCALE_COUNTER; + c->block_error.stat[0].uvalue += utmp1; + } else { + c->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; + } + return 0; err: dev_dbg(&client->dev, "failed=%d\n", ret); @@ -321,6 +403,8 @@ memcpy(cmd.args, "\x14\x00\x0a\x10\x00\x00", 6); cmd.args[4] = delivery_system | bandwidth; + if (dev->spectral_inversion) + cmd.args[5] |= 1; cmd.wlen = 6; cmd.rlen = 4; ret = si2168_cmd_execute(client, &cmd); @@ -385,6 +469,11 @@ dev->delivery_system = c->delivery_system; + /* enable ts bus */ + ret = si2168_ts_bus_ctrl(fe, 1); + if (ret) + goto err; + return 0; err: dev_dbg(&client->dev, "failed=%d\n", ret); @@ -395,11 +484,10 @@ { struct i2c_client *client = fe->demodulator_priv; struct si2168_dev *dev = i2c_get_clientdata(client); + struct dtv_frontend_properties *c = &fe->dtv_property_cache; int ret, len, remaining; const struct firmware *fw; - const char *fw_name; struct si2168_cmd cmd; - unsigned int chip_id; dev_dbg(&client->dev, "\n"); @@ -411,7 +499,7 @@ if (ret) goto err; - if (dev->fw_loaded) { + if (dev->warm) { /* resume */ memcpy(cmd.args, "\xc0\x06\x08\x0f\x00\x20\x21\x01", 8); cmd.wlen = 8; @@ -420,6 +508,7 @@ if (ret) goto err; + udelay(100); memcpy(cmd.args, "\x85", 1); cmd.wlen = 1; cmd.rlen = 1; @@ -438,49 +527,14 @@ if (ret) goto err; - /* query chip revision */ - memcpy(cmd.args, "\x02", 1); - cmd.wlen = 1; - cmd.rlen = 13; - ret = si2168_cmd_execute(client, &cmd); - if (ret) - goto err; - - chip_id = cmd.args[1] << 24 | cmd.args[2] << 16 | cmd.args[3] << 8 | - cmd.args[4] << 0; - - #define SI2168_A20 ('A' << 24 | 68 << 16 | '2' << 8 | '0' << 0) - #define SI2168_A30 ('A' << 24 | 68 << 16 | '3' << 8 | '0' << 0) - #define SI2168_B40 ('B' << 24 | 68 << 16 | '4' << 8 | '0' << 0) - - switch (chip_id) { - case SI2168_A20: - fw_name = SI2168_A20_FIRMWARE; - break; - case SI2168_A30: - fw_name = SI2168_A30_FIRMWARE; - break; - case SI2168_B40: - fw_name = SI2168_B40_FIRMWARE; - break; - default: - dev_err(&client->dev, "unknown chip version Si21%d-%c%c%c\n", - cmd.args[2], cmd.args[1], - cmd.args[3], cmd.args[4]); - ret = -EINVAL; - goto err; - } - - dev_info(&client->dev, "found a 'Silicon Labs Si21%d-%c%c%c'\n", - cmd.args[2], cmd.args[1], cmd.args[3], cmd.args[4]); - /* request the firmware, this will block and timeout */ - ret = request_firmware(&fw, fw_name, &client->dev); + ret = request_firmware(&fw, dev->firmware_name, &client->dev); if (ret) { /* fallback mechanism to handle old name for Si2168 B40 fw */ - if (chip_id == SI2168_B40) { - fw_name = SI2168_B40_FIRMWARE_FALLBACK; - ret = request_firmware(&fw, fw_name, &client->dev); + if (dev->chip_id == SI2168_CHIP_ID_B40) { + dev->firmware_name = SI2168_B40_FIRMWARE_FALLBACK; + ret = request_firmware(&fw, dev->firmware_name, + &client->dev); } if (ret == 0) { @@ -490,13 +544,13 @@ } else { dev_err(&client->dev, "firmware file '%s' not found\n", - fw_name); + dev->firmware_name); goto err_release_firmware; } } dev_info(&client->dev, "downloading firmware from file '%s'\n", - fw_name); + dev->firmware_name); if ((fw->size % 17 == 0) && (fw->data[0] > 5)) { /* firmware is in the new format */ @@ -551,26 +605,32 @@ if (ret) goto err; - dev_info(&client->dev, "firmware version: %c.%c.%d\n", - cmd.args[6], cmd.args[7], cmd.args[8]); + dev->version = (cmd.args[9] + '@') << 24 | (cmd.args[6] - '0') << 16 | + (cmd.args[7] - '0') << 8 | (cmd.args[8]) << 0; + dev_info(&client->dev, "firmware version: %c %d.%d.%d\n", + dev->version >> 24 & 0xff, dev->version >> 16 & 0xff, + dev->version >> 8 & 0xff, dev->version >> 0 & 0xff); /* set ts mode */ - memcpy(cmd.args, "\x14\x00\x01\x10\x10\x00", 6); - cmd.args[4] |= dev->ts_mode; - if (dev->ts_clock_gapped) - cmd.args[4] |= 0x40; - cmd.wlen = 6; - cmd.rlen = 4; - ret = si2168_cmd_execute(client, &cmd); + ret = si2168_ts_bus_ctrl(fe, 1); if (ret) goto err; - dev->fw_loaded = true; + dev->warm = true; warm: + /* Init stats here to indicate which stats are supported */ + c->cnr.len = 1; + c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE; + c->post_bit_error.len = 1; + c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; + c->post_bit_count.len = 1; + c->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; + c->block_error.len = 1; + c->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; + dev->active = true; return 0; - err_release_firmware: release_firmware(fw); err: @@ -589,6 +649,15 @@ dev->active = false; + /* tri-state data bus */ + ret = si2168_ts_bus_ctrl(fe, 0); + if (ret) + goto err; + + /* Firmware B 4.0-11 or later loses warm state during sleep */ + if (dev->version > ('B' << 24 | 4 << 16 | 0 << 8 | 11 << 0)) + dev->warm = false; + memcpy(cmd.args, "\x13", 1); cmd.wlen = 1; cmd.rlen = 0; @@ -698,6 +767,7 @@ struct si2168_config *config = client->dev.platform_data; struct si2168_dev *dev; int ret; + struct si2168_cmd cmd; dev_dbg(&client->dev, "\n"); @@ -708,6 +778,58 @@ goto err; } + i2c_set_clientdata(client, dev); + + /* Initialize */ + memcpy(cmd.args, "\xc0\x12\x00\x0c\x00\x0d\x16\x00\x00\x00\x00\x00\x00", 13); + cmd.wlen = 13; + cmd.rlen = 0; + ret = si2168_cmd_execute(client, &cmd); + if (ret) + goto err_kfree; + + /* Power up */ + memcpy(cmd.args, "\xc0\x06\x01\x0f\x00\x20\x20\x01", 8); + cmd.wlen = 8; + cmd.rlen = 1; + ret = si2168_cmd_execute(client, &cmd); + if (ret) + goto err_kfree; + + /* Query chip revision */ + memcpy(cmd.args, "\x02", 1); + cmd.wlen = 1; + cmd.rlen = 13; + ret = si2168_cmd_execute(client, &cmd); + if (ret) + goto err_kfree; + + dev->chip_id = cmd.args[1] << 24 | cmd.args[2] << 16 | + cmd.args[3] << 8 | cmd.args[4] << 0; + + switch (dev->chip_id) { + case SI2168_CHIP_ID_A20: + dev->firmware_name = SI2168_A20_FIRMWARE; + break; + case SI2168_CHIP_ID_A30: + dev->firmware_name = SI2168_A30_FIRMWARE; + break; + case SI2168_CHIP_ID_B40: + dev->firmware_name = SI2168_B40_FIRMWARE; + break; + case SI2168_CHIP_ID_D60: + dev->firmware_name = SI2168_D60_FIRMWARE; + break; + default: + dev_dbg(&client->dev, "unknown chip version Si21%d-%c%c%c\n", + cmd.args[2], cmd.args[1], cmd.args[3], cmd.args[4]); + ret = -ENODEV; + goto err_kfree; + } + + dev->version = (cmd.args[1]) << 24 | (cmd.args[3] - '0') << 16 | + (cmd.args[4] - '0') << 8 | (cmd.args[5]) << 0; + /* create mux i2c adapter for tuner */ dev->adapter = i2c_add_mux_adapter(client->adapter, &client->dev, client, 0, 0, 0, si2168_select, si2168_deselect); @@ -724,16 +846,20 @@ dev->ts_mode = config->ts_mode; dev->ts_clock_inv = config->ts_clock_inv; dev->ts_clock_gapped = config->ts_clock_gapped; - dev->fw_loaded = false; + dev->spectral_inversion = config->spectral_inversion; - i2c_set_clientdata(client, dev); + dev_info(&client->dev, "Silicon Labs Si2168-%c%d%d successfully identified\n", + dev->version >> 24 & 0xff, dev->version >> 16 & 0xff, + dev->version >> 8 & 0xff); + dev_info(&client->dev, "firmware version: %c %d.%d.%d\n", + dev->version >> 24 & 0xff, dev->version >> 16 & 0xff, + dev->version >> 8 & 0xff, dev->version >> 0 & 0xff); - dev_info(&client->dev, "Silicon Labs Si2168 successfully attached\n"); return 0; err_kfree: kfree(dev); err: - dev_dbg(&client->dev, "failed=%d\n", ret); + dev_warn(&client->dev, "probe failed = %d\n", ret); return ret; } @@ -762,6 +888,7 @@ static struct i2c_driver si2168_driver = { .driver = { .name = "si2168", + .suppress_bind_attrs = true, }, .probe = si2168_probe, .remove = si2168_remove, @@ -776,3 +903,4 @@ MODULE_FIRMWARE(SI2168_A20_FIRMWARE); MODULE_FIRMWARE(SI2168_A30_FIRMWARE); MODULE_FIRMWARE(SI2168_B40_FIRMWARE); +MODULE_FIRMWARE(SI2168_D60_FIRMWARE); diff -ruw linux-4.4.115/drivers/media/dvb-frontends/si2168.h linux-4.4.115-fbx/drivers/media/dvb-frontends/si2168.h --- linux-4.4.115/drivers/media/dvb-frontends/si2168.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/media/dvb-frontends/si2168.h 2019-01-22 16:16:24.267253325 +0100 @@ -38,6 +38,7 @@ /* TS mode */ #define SI2168_TS_PARALLEL 0x06 #define SI2168_TS_SERIAL 0x03 +#define SI2168_TS_TRISTATE 0x00 u8 ts_mode; /* TS clock inverted */ @@ -45,6 +46,9 @@ /* TS clock gapped */ bool ts_clock_gapped; + + /* Inverted spectrum */ + bool spectral_inversion; }; #endif diff -ruw linux-4.4.115/drivers/media/dvb-frontends/si2168_priv.h linux-4.4.115-fbx/drivers/media/dvb-frontends/si2168_priv.h --- linux-4.4.115/drivers/media/dvb-frontends/si2168_priv.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/media/dvb-frontends/si2168_priv.h 2019-01-22 16:16:24.267253325 +0100 @@ -21,10 +21,12 @@ #include "dvb_frontend.h" #include #include +#include #define SI2168_A20_FIRMWARE "dvb-demod-si2168-a20-01.fw" #define SI2168_A30_FIRMWARE "dvb-demod-si2168-a30-01.fw" #define SI2168_B40_FIRMWARE "dvb-demod-si2168-b40-01.fw" +#define SI2168_D60_FIRMWARE "dvb-demod-si2168-d60-01.fw" #define SI2168_B40_FIRMWARE_FALLBACK "dvb-demod-si2168-02.fw" /* state struct */ @@ -33,11 +35,19 @@ struct dvb_frontend fe; enum fe_delivery_system delivery_system; enum fe_status fe_status; + #define SI2168_CHIP_ID_A20 ('A' << 24 | 68 << 16 | '2' << 8 | '0' << 0) + #define SI2168_CHIP_ID_A30 ('A' << 24 | 68 << 16 | '3' << 8 | '0' << 0) + #define SI2168_CHIP_ID_B40 ('B' << 24 | 68 << 16 | '4' << 8 | '0' << 0) + #define SI2168_CHIP_ID_D60 ('D' << 24 | 68 << 16 | '6' << 8 | '0' << 0) + unsigned int chip_id; + unsigned int version; + const char *firmware_name; bool active; - bool fw_loaded; + bool warm; u8 ts_mode; bool ts_clock_inv; bool ts_clock_gapped; + bool spectral_inversion; }; /* firmware command struct */ diff -ruw linux-4.4.115/drivers/media/i2c/Kconfig linux-4.4.115-fbx/drivers/media/i2c/Kconfig --- linux-4.4.115/drivers/media/i2c/Kconfig 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/media/i2c/Kconfig 2019-01-22 16:16:24.283253470 +0100 @@ -221,6 +221,30 @@ To compile this driver as a module, choose M here: the module will be called adv7842. +config VIDEO_ADV7481 + tristate "Analog Devices ADV7481 decoder" + depends on VIDEO_V4L2 && I2C && VIDEO_V4L2_SUBDEV_API && MEDIA_CONTROLLER + ---help--- + Support for the Analog Devices ADV7481 video decoder. + + This is a Analog Devices Component/Graphics/SD Digitizer + with HDMI Receiver. + + To compile this driver as a module, choose M here: the + module will be called adv7481. + +config VIDEO_TVTUNER + tristate "Analog Tv Tuner driver" + depends on VIDEO_V4L2 && I2C && VIDEO_V4L2_SUBDEV_API + ---help--- + Support for the Dummy TV Tuner. + + This is a Dummy TV Tuner Driver to Validate call flow + from tv_input_test unit-test app. + + To compile this driver as a module, choose M here: the + module will be called tv-tuner. + config VIDEO_BT819 tristate "BT819A VideoStream decoder" depends on VIDEO_V4L2 && I2C @@ -726,6 +750,7 @@ menu "Sensors used on soc_camera driver" if SOC_CAMERA + source "drivers/media/i2c/soc_camera/Kconfig" endif diff -ruw linux-4.4.115/drivers/media/i2c/Makefile linux-4.4.115-fbx/drivers/media/i2c/Makefile --- linux-4.4.115/drivers/media/i2c/Makefile 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/media/i2c/Makefile 2019-10-29 09:26:23.901205703 +0100 @@ -27,6 +27,19 @@ obj-$(CONFIG_VIDEO_ADV7393) += adv7393.o obj-$(CONFIG_VIDEO_ADV7604) += adv7604.o obj-$(CONFIG_VIDEO_ADV7842) += adv7842.o +ifeq ($(CONFIG_MSM_AIS),y) +ccflags-y += -Idrivers/media/platform/msm/ais +ccflags-y += -Idrivers/media/platform/msm/ais/common +ccflags-y += -Idrivers/media/platform/msm/ais/sensor/io +ccflags-y += -Idrivers/media/platform/msm/ais/sensor/cci +else +ccflags-y += -Idrivers/media/platform/msm/camera_v2 +ccflags-y += -Idrivers/media/platform/msm/camera_v2/common +ccflags-y += -Idrivers/media/platform/msm/camera_v2/sensor/io +ccflags-y += -Idrivers/media/platform/msm/camera_v2/sensor/cci +endif +obj-$(CONFIG_VIDEO_ADV7481) += adv7481.o +obj-$(CONFIG_VIDEO_TVTUNER) += tvtuner.o obj-$(CONFIG_VIDEO_AD9389B) += ad9389b.o obj-$(CONFIG_VIDEO_ADV7511) += adv7511.o obj-$(CONFIG_VIDEO_VPX3220) += vpx3220.o diff -ruw linux-4.4.115/drivers/media/Kconfig linux-4.4.115-fbx/drivers/media/Kconfig --- linux-4.4.115/drivers/media/Kconfig 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/media/Kconfig 2019-10-29 09:26:23.885205546 +0100 @@ -2,6 +2,12 @@ # Multimedia device configuration # +config CEC_CORE + tristate + +config CEC_NOTIFIER + bool + menuconfig MEDIA_SUPPORT tristate "Multimedia support" depends on HAS_IOMEM @@ -80,6 +86,17 @@ Say Y when you have a TV or an IR device. +config MEDIA_CEC_SUPPORT + bool "HDMI CEC support" + ---help--- + Enable support for HDMI CEC (Consumer Electronics Control), + which is an optional HDMI feature. + + Say Y when you have an HDMI receiver, transmitter or a USB CEC + adapter that supports HDMI CEC. + +source "drivers/media/cec/Kconfig" + # # Media controller # Selectable only for webcam/grabbers, as other drivers don't use it diff -ruw linux-4.4.115/drivers/media/Makefile linux-4.4.115-fbx/drivers/media/Makefile --- linux-4.4.115/drivers/media/Makefile 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/media/Makefile 2019-10-29 09:26:23.885205546 +0100 @@ -24,6 +24,8 @@ # There are both core and drivers at RC subtree - merge before drivers obj-y += rc/ +obj-$(CONFIG_CEC_CORE) += cec/ + # # Finally, merge the drivers that require the core # diff -ruw linux-4.4.115/drivers/media/platform/Kconfig linux-4.4.115-fbx/drivers/media/platform/Kconfig --- linux-4.4.115/drivers/media/platform/Kconfig 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/media/platform/Kconfig 2019-01-22 16:16:24.387254412 +0100 @@ -303,3 +303,5 @@ if DVB_PLATFORM_DRIVERS source "drivers/media/platform/sti/c8sectpfe/Kconfig" endif #DVB_PLATFORM_DRIVERS + +source "drivers/media/platform/msm/Kconfig" diff -ruw linux-4.4.115/drivers/media/platform/Makefile linux-4.4.115-fbx/drivers/media/platform/Makefile --- linux-4.4.115/drivers/media/platform/Makefile 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/media/platform/Makefile 2019-01-22 16:16:24.387254412 +0100 @@ -55,3 +55,4 @@ obj-$(CONFIG_VIDEO_XILINX) += xilinx/ ccflags-y += -I$(srctree)/drivers/media/i2c +obj-y += msm/ diff -ruw linux-4.4.115/drivers/media/rc/ir-rc6-decoder.c linux-4.4.115-fbx/drivers/media/rc/ir-rc6-decoder.c --- linux-4.4.115/drivers/media/rc/ir-rc6-decoder.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/media/rc/ir-rc6-decoder.c 2019-01-22 16:16:24.523255643 +0100 @@ -260,7 +260,6 @@ if ((scancode & RC6_6A_LCC_MASK) == RC6_6A_MCE_CC) { protocol = RC_TYPE_RC6_MCE; toggle = !!(scancode & RC6_6A_MCE_TOGGLE_MASK); - scancode &= ~RC6_6A_MCE_TOGGLE_MASK; } else { protocol = RC_BIT_RC6_6A_32; toggle = 0; @@ -271,6 +270,7 @@ goto out; } + scancode &= ~RC6_6A_MCE_TOGGLE_MASK; IR_dprintk(1, "RC6(6A) proto 0x%04x, scancode 0x%08x (toggle: %u)\n", protocol, scancode, toggle); break; diff -ruw linux-4.4.115/drivers/media/rc/keymaps/Makefile linux-4.4.115-fbx/drivers/media/rc/keymaps/Makefile --- linux-4.4.115/drivers/media/rc/keymaps/Makefile 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/media/rc/keymaps/Makefile 2019-10-29 09:26:23.977206447 +0100 @@ -18,6 +18,7 @@ rc-behold.o \ rc-behold-columbus.o \ rc-budget-ci-old.o \ + rc-cec.o \ rc-cinergy-1400.o \ rc-cinergy.o \ rc-delock-61959.o \ @@ -79,6 +80,7 @@ rc-pv951.o \ rc-hauppauge.o \ rc-rc6-mce.o \ + rc-rc6-freebox.o \ rc-real-audio-220-32-keys.o \ rc-reddo.o \ rc-snapstream-firefly.o \ diff -ruw linux-4.4.115/drivers/media/rc/mceusb.c linux-4.4.115-fbx/drivers/media/rc/mceusb.c --- linux-4.4.115/drivers/media/rc/mceusb.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/media/rc/mceusb.c 2019-10-29 09:26:23.981206486 +0100 @@ -200,6 +200,7 @@ TIVO_KIT, MCE_GEN2_NO_TX, HAUPPAUGE_CX_HYBRID_TV, + MCE_FREEBOX, }; struct mceusb_model { @@ -259,6 +260,11 @@ .mce_gen2 = 1, .rc_map = RC_MAP_TIVO, }, + [MCE_FREEBOX] = { + .mce_gen2 = 1, + .no_tx = 1, + .rc_map = "rc-rc6-freebox", + } }; static struct usb_device_id mceusb_dev_table[] = { @@ -354,7 +360,8 @@ /* Formosa Industrial Computing AIM IR605/A */ { USB_DEVICE(VENDOR_FORMOSA, 0xe03c) }, /* Formosa Industrial Computing */ - { USB_DEVICE(VENDOR_FORMOSA, 0xe03e) }, + { USB_DEVICE(VENDOR_FORMOSA, 0xe03e), + .driver_info = MCE_FREEBOX }, /* Formosa Industrial Computing */ { USB_DEVICE(VENDOR_FORMOSA, 0xe042) }, /* Fintek eHome Infrared Transceiver (HP branded) */ @@ -953,7 +960,7 @@ /* 2-byte return value commands */ case MCE_RSP_EQIRTIMEOUT: - ir->rc->timeout = US_TO_NS((hi << 8 | lo) * MCE_TIME_UNIT); + ir->rc->timeout = US_TO_NS((hi << 8 | lo) * MCE_TIME_UNIT / 1000); break; case MCE_RSP_EQIRNUMPORTS: ir->num_txports = hi; @@ -1231,7 +1238,7 @@ rc->priv = ir; rc->driver_type = RC_DRIVER_IR_RAW; rc->allowed_protocols = RC_BIT_ALL; - rc->timeout = MS_TO_NS(100); + rc->timeout = MS_TO_NS(50); if (!ir->flags.no_tx) { rc->s_tx_mask = mceusb_set_tx_mask; rc->s_tx_carrier = mceusb_set_tx_carrier; diff -ruw linux-4.4.115/drivers/media/rc/rc-main.c linux-4.4.115-fbx/drivers/media/rc/rc-main.c --- linux-4.4.115/drivers/media/rc/rc-main.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/media/rc/rc-main.c 2019-10-29 09:26:23.981206486 +0100 @@ -801,6 +801,7 @@ { RC_BIT_SHARP, "sharp" }, { RC_BIT_MCE_KBD, "mce_kbd" }, { RC_BIT_XMP, "xmp" }, + { RC_BIT_CEC, "cec", }, }; /** diff -ruw linux-4.4.115/drivers/media/tuners/si2157.c linux-4.4.115-fbx/drivers/media/tuners/si2157.c --- linux-4.4.115/drivers/media/tuners/si2157.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/media/tuners/si2157.c 2019-01-22 16:16:24.543255824 +0100 @@ -84,17 +84,31 @@ struct si2157_cmd cmd; const struct firmware *fw; const char *fw_name; - unsigned int chip_id; + unsigned int uitmp, chip_id; dev_dbg(&client->dev, "\n"); - if (dev->fw_loaded) + /* Returned IF frequency is garbage when firmware is not running */ + memcpy(cmd.args, "\x15\x00\x06\x07", 4); + cmd.wlen = 4; + cmd.rlen = 4; + ret = si2157_cmd_execute(client, &cmd); + if (ret) + goto err; + + uitmp = cmd.args[2] << 0 | cmd.args[3] << 8; + dev_dbg(&client->dev, "if_frequency kHz=%u\n", uitmp); + + if (uitmp == dev->if_frequency / 1000) goto warm; /* power up */ if (dev->chiptype == SI2157_CHIPTYPE_SI2146) { memcpy(cmd.args, "\xc0\x05\x01\x00\x00\x0b\x00\x00\x01", 9); cmd.wlen = 9; + } else if (dev->chiptype == SI2157_CHIPTYPE_SI2141) { + memcpy(cmd.args, "\xc0\x00\x0d\x0e\x00\x01\x01\x01\x01\x03", 10); + cmd.wlen = 10; } else { memcpy(cmd.args, "\xc0\x00\x0c\x00\x00\x01\x01\x01\x01\x01\x01\x02\x00\x00\x01", 15); cmd.wlen = 15; @@ -104,6 +118,15 @@ if (ret) goto err; + /* Si2141 needs a second command before it answers the revision query */ + if (dev->chiptype == SI2157_CHIPTYPE_SI2141) { + memcpy(cmd.args, "\xc0\x08\x01\x02\x00\x00\x01", 7); + cmd.wlen = 7; + ret = si2157_cmd_execute(client, &cmd); + if (ret) + goto err; + } + /* query chip revision */ memcpy(cmd.args, "\x02", 1); cmd.wlen = 1; @@ -120,12 +143,16 @@ #define SI2157_A30 ('A' << 24 | 57 << 16 | '3' << 8 | '0' << 0) #define SI2147_A30 ('A' << 24 | 47 << 16 | '3' << 8 | '0' << 0) #define SI2146_A10 ('A' << 24 | 46 << 16 | '1' << 8 | '0' << 0) + #define SI2141_A10 ('A' << 24 | 41 << 16 | '1' << 8 | '0' << 0) switch (chip_id) { case SI2158_A20: case SI2148_A20: fw_name = SI2158_A20_FIRMWARE; break; + case SI2141_A10: + fw_name = SI2141_A10_FIRMWARE; + break; case SI2157_A30: case SI2147_A30: case SI2146_A10: @@ -203,9 +230,6 @@ dev_info(&client->dev, "firmware version: %c.%c.%d\n", cmd.args[6], cmd.args[7], cmd.args[8]); - - dev->fw_loaded = true; - warm: /* init statistics in order signal app which are supported */ c->strength.len = 1; @@ -363,9 +387,9 @@ static const struct dvb_tuner_ops si2157_ops = { .info = { - .name = "Silicon Labs Si2146/2147/2148/2157/2158", - .frequency_min = 55000000, - .frequency_max = 862000000, + .name = "Silicon Labs Si2141/Si2146/2147/2148/2157/2158", + .frequency_min = 42000000, + .frequency_max = 870000000, }, .init = si2157_init, @@ -422,7 +446,6 @@ dev->fe = cfg->fe; dev->inversion = cfg->inversion; dev->if_port = cfg->if_port; - dev->fw_loaded = false; dev->chiptype = (u8)id->driver_data; dev->if_frequency = 5000000; /* default value of property 0x0706 */ mutex_init(&dev->i2c_mutex); @@ -439,6 +462,7 @@ fe->tuner_priv = client; dev_info(&client->dev, "Silicon Labs %s successfully attached\n", + dev->chiptype == SI2157_CHIPTYPE_SI2141 ? "Si2141" : dev->chiptype == SI2157_CHIPTYPE_SI2146 ? "Si2146" : "Si2147/2148/2157/2158"); @@ -458,6 +482,9 @@ dev_dbg(&client->dev, "\n"); + /* stop statistics polling */ + cancel_delayed_work_sync(&dev->stat_work); + memset(&fe->ops.tuner_ops, 0, sizeof(struct dvb_tuner_ops)); fe->tuner_priv = NULL; kfree(dev); @@ -468,6 +495,7 @@ static const struct i2c_device_id si2157_id_table[] = { {"si2157", SI2157_CHIPTYPE_SI2157}, {"si2146", SI2157_CHIPTYPE_SI2146}, + {"si2141", SI2157_CHIPTYPE_SI2141}, {} }; MODULE_DEVICE_TABLE(i2c, si2157_id_table); @@ -475,6 +503,7 @@ static struct i2c_driver si2157_driver = { .driver = { .name = "si2157", + .suppress_bind_attrs = true, }, .probe = si2157_probe, .remove = si2157_remove, @@ -483,7 +512,8 @@ module_i2c_driver(si2157_driver); -MODULE_DESCRIPTION("Silicon Labs Si2146/2147/2148/2157/2158 silicon tuner driver"); +MODULE_DESCRIPTION("Silicon Labs Si2141/Si2146/2147/2148/2157/2158 silicon tuner driver"); MODULE_AUTHOR("Antti Palosaari "); MODULE_LICENSE("GPL"); MODULE_FIRMWARE(SI2158_A20_FIRMWARE); +MODULE_FIRMWARE(SI2141_A10_FIRMWARE); diff -ruw linux-4.4.115/drivers/media/tuners/si2157_priv.h linux-4.4.115-fbx/drivers/media/tuners/si2157_priv.h --- linux-4.4.115/drivers/media/tuners/si2157_priv.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/media/tuners/si2157_priv.h 2019-01-22 16:16:24.543255824 +0100 @@ -25,7 +25,6 @@ struct mutex i2c_mutex; struct dvb_frontend *fe; bool active; - bool fw_loaded; bool inversion; u8 chiptype; u8 if_port; @@ -35,6 +34,7 @@ #define SI2157_CHIPTYPE_SI2157 0 #define SI2157_CHIPTYPE_SI2146 1 +#define SI2157_CHIPTYPE_SI2141 2 /* firmware command struct */ #define SI2157_ARGLEN 30 @@ -45,5 +45,6 @@ }; #define SI2158_A20_FIRMWARE "dvb-tuner-si2158-a20-01.fw" +#define SI2141_A10_FIRMWARE "dvb-tuner-si2141-a10-01.fw" #endif diff -ruw linux-4.4.115/drivers/media/v4l2-core/v4l2-compat-ioctl32.c linux-4.4.115-fbx/drivers/media/v4l2-core/v4l2-compat-ioctl32.c --- linux-4.4.115/drivers/media/v4l2-core/v4l2-compat-ioctl32.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/media/v4l2-core/v4l2-compat-ioctl32.c 2019-10-29 09:26:24.009206760 +0100 @@ -20,6 +20,13 @@ #include #include +#define convert_in_user(srcptr, dstptr) \ +({ \ + typeof(*srcptr) val; \ + \ + get_user(val, srcptr) || put_user(val, dstptr); \ +}) + static long native_ioctl(struct file *file, unsigned int cmd, unsigned long arg) { long ret = -ENOIOCTLCMD; @@ -45,27 +52,45 @@ compat_caddr_t bitmap; }; -static int get_v4l2_window32(struct v4l2_window *kp, struct v4l2_window32 __user *up) +static int bufsize_v4l2_window32(struct v4l2_window32 __user *up) { + __u32 clipcount; + + if (get_user(clipcount, &up->clipcount)) + return -EFAULT; + if (clipcount > 2048) + return -EINVAL; + return clipcount * sizeof(struct v4l2_clip); +} + +static int get_v4l2_window32(struct v4l2_window __user *kp, struct + v4l2_window32 __user *up, void __user *aux_buf, int aux_space) +{ + __u32 clipcount; + if (!access_ok(VERIFY_READ, up, sizeof(struct v4l2_window32)) || - copy_from_user(&kp->w, &up->w, sizeof(up->w)) || - get_user(kp->field, &up->field) || - get_user(kp->chromakey, &up->chromakey) || - get_user(kp->clipcount, &up->clipcount)) + copy_in_user(&kp->w, &up->w, sizeof(up->w)) || + convert_in_user(&up->field, &kp->field) || + convert_in_user(&up->chromakey, &kp->chromakey) || + get_user(clipcount, &up->clipcount) || + put_user(clipcount, &kp->clipcount)) return -EFAULT; - if (kp->clipcount > 2048) + if (clipcount > 2048) return -EINVAL; - if (kp->clipcount) { + if (clipcount) { struct v4l2_clip32 __user *uclips; struct v4l2_clip __user *kclips; - int n = kp->clipcount; + int n = clipcount; compat_caddr_t p; if (get_user(p, &up->clips)) return -EFAULT; uclips = compat_ptr(p); - kclips = compat_alloc_user_space(n * sizeof(struct v4l2_clip)); - kp->clips = kclips; + if (aux_space < n * sizeof(struct v4l2_clip)) + return -EFAULT; + kclips = aux_buf; + if (put_user(kclips, &kp->clips)) + return -EFAULT; while (--n >= 0) { if (copy_in_user(&kclips->c, &uclips->c, sizeof(uclips->c))) return -EFAULT; @@ -74,89 +99,91 @@ uclips += 1; kclips += 1; } - } else - kp->clips = NULL; + } else { + if (put_user(NULL, &kp->clips)) + return -EFAULT; + } return 0; } -static int put_v4l2_window32(struct v4l2_window *kp, struct v4l2_window32 __user *up) +static int put_v4l2_window32(struct v4l2_window __user *kp, struct v4l2_window32 __user *up) { - if (copy_to_user(&up->w, &kp->w, sizeof(kp->w)) || - put_user(kp->field, &up->field) || - put_user(kp->chromakey, &up->chromakey) || - put_user(kp->clipcount, &up->clipcount)) + if (copy_in_user(&up->w, &kp->w, sizeof(kp->w)) || + convert_in_user(&kp->field, &up->field) || + convert_in_user(&kp->chromakey, &up->chromakey) || + convert_in_user(&kp->clipcount, &up->clipcount)) return -EFAULT; return 0; } -static inline int get_v4l2_pix_format(struct v4l2_pix_format *kp, struct v4l2_pix_format __user *up) +static inline int get_v4l2_pix_format(struct v4l2_pix_format __user *kp, struct v4l2_pix_format __user *up) { - if (copy_from_user(kp, up, sizeof(struct v4l2_pix_format))) + if (copy_in_user(kp, up, sizeof(struct v4l2_pix_format))) return -EFAULT; return 0; } -static inline int get_v4l2_pix_format_mplane(struct v4l2_pix_format_mplane *kp, +static inline int get_v4l2_pix_format_mplane(struct v4l2_pix_format_mplane __user *kp, struct v4l2_pix_format_mplane __user *up) { - if (copy_from_user(kp, up, sizeof(struct v4l2_pix_format_mplane))) + if (copy_in_user(kp, up, sizeof(struct v4l2_pix_format_mplane))) return -EFAULT; return 0; } -static inline int put_v4l2_pix_format(struct v4l2_pix_format *kp, struct v4l2_pix_format __user *up) +static inline int put_v4l2_pix_format(struct v4l2_pix_format __user *kp, struct v4l2_pix_format __user *up) { - if (copy_to_user(up, kp, sizeof(struct v4l2_pix_format))) + if (copy_in_user(up, kp, sizeof(struct v4l2_pix_format))) return -EFAULT; return 0; } -static inline int put_v4l2_pix_format_mplane(struct v4l2_pix_format_mplane *kp, +static inline int put_v4l2_pix_format_mplane(struct v4l2_pix_format_mplane __user *kp, struct v4l2_pix_format_mplane __user *up) { - if (copy_to_user(up, kp, sizeof(struct v4l2_pix_format_mplane))) + if (copy_in_user(up, kp, sizeof(struct v4l2_pix_format_mplane))) return -EFAULT; return 0; } -static inline int get_v4l2_vbi_format(struct v4l2_vbi_format *kp, struct v4l2_vbi_format __user *up) +static inline int get_v4l2_vbi_format(struct v4l2_vbi_format __user *kp, struct v4l2_vbi_format __user *up) { - if (copy_from_user(kp, up, sizeof(struct v4l2_vbi_format))) + if (copy_in_user(kp, up, sizeof(struct v4l2_vbi_format))) return -EFAULT; return 0; } -static inline int put_v4l2_vbi_format(struct v4l2_vbi_format *kp, struct v4l2_vbi_format __user *up) +static inline int put_v4l2_vbi_format(struct v4l2_vbi_format __user *kp, struct v4l2_vbi_format __user *up) { - if (copy_to_user(up, kp, sizeof(struct v4l2_vbi_format))) + if (copy_in_user(up, kp, sizeof(struct v4l2_vbi_format))) return -EFAULT; return 0; } -static inline int get_v4l2_sliced_vbi_format(struct v4l2_sliced_vbi_format *kp, struct v4l2_sliced_vbi_format __user *up) +static inline int get_v4l2_sliced_vbi_format(struct v4l2_sliced_vbi_format __user *kp, struct v4l2_sliced_vbi_format __user *up) { - if (copy_from_user(kp, up, sizeof(struct v4l2_sliced_vbi_format))) + if (copy_in_user(kp, up, sizeof(struct v4l2_sliced_vbi_format))) return -EFAULT; return 0; } -static inline int put_v4l2_sliced_vbi_format(struct v4l2_sliced_vbi_format *kp, struct v4l2_sliced_vbi_format __user *up) +static inline int put_v4l2_sliced_vbi_format(struct v4l2_sliced_vbi_format __user *kp, struct v4l2_sliced_vbi_format __user *up) { - if (copy_to_user(up, kp, sizeof(struct v4l2_sliced_vbi_format))) + if (copy_in_user(up, kp, sizeof(struct v4l2_sliced_vbi_format))) return -EFAULT; return 0; } -static inline int get_v4l2_sdr_format(struct v4l2_sdr_format *kp, struct v4l2_sdr_format __user *up) +static inline int get_v4l2_sdr_format(struct v4l2_sdr_format __user *kp, struct v4l2_sdr_format __user *up) { - if (copy_from_user(kp, up, sizeof(struct v4l2_sdr_format))) + if (copy_in_user(kp, up, sizeof(struct v4l2_sdr_format))) return -EFAULT; return 0; } -static inline int put_v4l2_sdr_format(struct v4l2_sdr_format *kp, struct v4l2_sdr_format __user *up) +static inline int put_v4l2_sdr_format(struct v4l2_sdr_format __user *kp, struct v4l2_sdr_format __user *up) { - if (copy_to_user(up, kp, sizeof(struct v4l2_sdr_format))) + if (copy_in_user(up, kp, sizeof(struct v4l2_sdr_format))) return -EFAULT; return 0; } @@ -191,12 +218,31 @@ __u32 reserved[8]; }; -static int __get_v4l2_format32(struct v4l2_format *kp, struct v4l2_format32 __user *up) +static int __bufsize_v4l2_format32(struct v4l2_format32 __user *up) { - if (get_user(kp->type, &up->type)) + __u32 type; + + if (get_user(type, &up->type)) return -EFAULT; - switch (kp->type) { + switch (type) { + case V4L2_BUF_TYPE_VIDEO_OVERLAY: + case V4L2_BUF_TYPE_VIDEO_OUTPUT_OVERLAY: + return bufsize_v4l2_window32(&up->fmt.win); + default: + return 0; + } +} + +static int __get_v4l2_format32(struct v4l2_format __user *kp, struct + v4l2_format32 __user *up, void __user *aux_buf, int aux_space) +{ + __u32 type; + + if (get_user(type, &up->type) || put_user(type, &kp->type)) + return -EFAULT; + + switch (type) { case V4L2_BUF_TYPE_VIDEO_CAPTURE: case V4L2_BUF_TYPE_VIDEO_OUTPUT: return get_v4l2_pix_format(&kp->fmt.pix, &up->fmt.pix); @@ -206,7 +252,7 @@ &up->fmt.pix_mp); case V4L2_BUF_TYPE_VIDEO_OVERLAY: case V4L2_BUF_TYPE_VIDEO_OUTPUT_OVERLAY: - return get_v4l2_window32(&kp->fmt.win, &up->fmt.win); + return get_v4l2_window32(&kp->fmt.win, &up->fmt.win, aux_buf, aux_space); case V4L2_BUF_TYPE_VBI_CAPTURE: case V4L2_BUF_TYPE_VBI_OUTPUT: return get_v4l2_vbi_format(&kp->fmt.vbi, &up->fmt.vbi); @@ -223,27 +269,51 @@ } } -static int get_v4l2_format32(struct v4l2_format *kp, struct v4l2_format32 __user *up) +static int bufsize_v4l2_format32(struct v4l2_format32 __user *up) { if (!access_ok(VERIFY_READ, up, sizeof(struct v4l2_format32))) return -EFAULT; - return __get_v4l2_format32(kp, up); + return __bufsize_v4l2_format32(up); } -static int get_v4l2_create32(struct v4l2_create_buffers *kp, struct v4l2_create_buffers32 __user *up) +static int get_v4l2_format32(struct v4l2_format __user *kp, struct + v4l2_format32 __user *up, void __user *aux_buf, int aux_space) +{ + if (!access_ok(VERIFY_READ, up, sizeof(struct v4l2_format32))) + return -EFAULT; + return __get_v4l2_format32(kp, up, aux_buf, aux_space); +} + +static int bufsize_v4l2_create32(struct v4l2_create_buffers32 __user *up) +{ + if (!access_ok(VERIFY_READ, up, sizeof(struct v4l2_create_buffers32))) + return -EFAULT; + return __bufsize_v4l2_format32(&up->format); +} + +static int get_v4l2_create32(struct v4l2_create_buffers __user *kp, struct + v4l2_create_buffers32 __user *up, void __user *aux_buf, + int aux_space) { if (!access_ok(VERIFY_READ, up, sizeof(struct v4l2_create_buffers32)) || - copy_from_user(kp, up, offsetof(struct v4l2_create_buffers32, format))) + copy_in_user(kp, up, offsetof(struct v4l2_create_buffers32, format))) return -EFAULT; - return __get_v4l2_format32(&kp->format, &up->format); + return __get_v4l2_format32(&kp->format, &up->format, aux_buf, aux_space); } -static int __put_v4l2_format32(struct v4l2_format *kp, struct v4l2_format32 __user *up) +static int __put_v4l2_format32(struct v4l2_format __user *kp, struct v4l2_format32 __user *up) { - if (put_user(kp->type, &up->type)) + __u32 type; + + if (kp == NULL) + return -EFAULT; + + if (get_user(type, &kp->type)) + return -EFAULT; + if (put_user(type, &up->type)) return -EFAULT; - switch (kp->type) { + switch (type) { case V4L2_BUF_TYPE_VIDEO_CAPTURE: case V4L2_BUF_TYPE_VIDEO_OUTPUT: return put_v4l2_pix_format(&kp->fmt.pix, &up->fmt.pix); @@ -270,18 +340,18 @@ } } -static int put_v4l2_format32(struct v4l2_format *kp, struct v4l2_format32 __user *up) +static int put_v4l2_format32(struct v4l2_format __user *kp, struct v4l2_format32 __user *up) { if (!access_ok(VERIFY_WRITE, up, sizeof(struct v4l2_format32))) return -EFAULT; return __put_v4l2_format32(kp, up); } -static int put_v4l2_create32(struct v4l2_create_buffers *kp, struct v4l2_create_buffers32 __user *up) +static int put_v4l2_create32(struct v4l2_create_buffers __user *kp, struct v4l2_create_buffers32 __user *up) { if (!access_ok(VERIFY_WRITE, up, sizeof(struct v4l2_create_buffers32)) || - copy_to_user(up, kp, offsetof(struct v4l2_create_buffers32, format)) || - copy_to_user(up->reserved, kp->reserved, sizeof(kp->reserved))) + copy_in_user(up, kp, offsetof(struct v4l2_create_buffers32, format)) || + copy_in_user(up->reserved, kp->reserved, sizeof(kp->reserved))) return -EFAULT; return __put_v4l2_format32(&kp->format, &up->format); } @@ -295,24 +365,24 @@ __u32 reserved[4]; }; -static int get_v4l2_standard32(struct v4l2_standard *kp, struct v4l2_standard32 __user *up) +static int get_v4l2_standard32(struct v4l2_standard __user *kp, struct v4l2_standard32 __user *up) { /* other fields are not set by the user, nor used by the driver */ if (!access_ok(VERIFY_READ, up, sizeof(struct v4l2_standard32)) || - get_user(kp->index, &up->index)) + convert_in_user(&up->index, &kp->index)) return -EFAULT; return 0; } -static int put_v4l2_standard32(struct v4l2_standard *kp, struct v4l2_standard32 __user *up) +static int put_v4l2_standard32(struct v4l2_standard __user *kp, struct v4l2_standard32 __user *up) { if (!access_ok(VERIFY_WRITE, up, sizeof(struct v4l2_standard32)) || - put_user(kp->index, &up->index) || - put_user(kp->id, &up->id) || - copy_to_user(up->name, kp->name, 24) || - copy_to_user(&up->frameperiod, &kp->frameperiod, sizeof(kp->frameperiod)) || - put_user(kp->framelines, &up->framelines) || - copy_to_user(up->reserved, kp->reserved, 4 * sizeof(__u32))) + convert_in_user(&kp->index, &up->index) || + copy_in_user((void __user *)up->id, &kp->id, sizeof(__u64)) || + copy_in_user(up->name, kp->name, 24) || + copy_in_user(&up->frameperiod, &kp->frameperiod, sizeof(kp->frameperiod)) || + convert_in_user(&kp->framelines, &up->framelines) || + copy_in_user(up->reserved, kp->reserved, 4 * sizeof(__u32))) return -EFAULT; return 0; } @@ -355,19 +425,21 @@ static int get_v4l2_plane32(struct v4l2_plane __user *up, struct v4l2_plane32 __user *up32, enum v4l2_memory memory) { - void __user *up_pln; compat_long_t p; if (copy_in_user(up, up32, 2 * sizeof(__u32)) || copy_in_user(&up->data_offset, &up32->data_offset, + sizeof(__u32)) || + copy_in_user(up->reserved, up32->reserved, + sizeof(up->reserved)) || + copy_in_user(&up->length, &up32->length, sizeof(__u32))) return -EFAULT; if (memory == V4L2_MEMORY_USERPTR) { - if (get_user(p, &up32->m.userptr)) - return -EFAULT; - up_pln = compat_ptr(p); - if (put_user((unsigned long)up_pln, &up->m.userptr)) + if (get_user(p, &up32->m.userptr) || + put_user((unsigned long) compat_ptr(p), + &up->m.userptr)) return -EFAULT; } else if (memory == V4L2_MEMORY_DMABUF) { if (copy_in_user(&up->m.fd, &up32->m.fd, sizeof(int))) @@ -385,6 +457,8 @@ enum v4l2_memory memory) { if (copy_in_user(up32, up, 2 * sizeof(__u32)) || + copy_in_user(up32->reserved, up->reserved, + sizeof(up32->reserved)) || copy_in_user(&up32->data_offset, &up->data_offset, sizeof(__u32))) return -EFAULT; @@ -400,12 +474,42 @@ if (copy_in_user(&up32->m.fd, &up->m.fd, sizeof(int))) return -EFAULT; + if (memory == V4L2_MEMORY_USERPTR) + if (copy_in_user(&up32->m.userptr, &up->m.userptr, + sizeof(compat_long_t))) + return -EFAULT; return 0; } -static int get_v4l2_buffer32(struct v4l2_buffer *kp, struct v4l2_buffer32 __user *up) +static int bufsize_v4l2_buffer32(struct v4l2_buffer32 __user *up) { + __u32 type; + __u32 length; + + if (!access_ok(VERIFY_READ, up, sizeof(struct v4l2_buffer32)) || + get_user(type, &up->type) || + get_user(length, &up->length)) + return -EFAULT; + + if (V4L2_TYPE_IS_MULTIPLANAR(type)) { + if (length > VIDEO_MAX_PLANES) + return -EINVAL; + + /* We don't really care if userspace decides to kill itself + * by passing a very big length value + */ + return length * sizeof(struct v4l2_plane); + } + return 0; +} + +static int get_v4l2_buffer32(struct v4l2_buffer __user *kp, struct + v4l2_buffer32 __user *up, void __user *aux_buf, int aux_space) +{ + __u32 type; + __u32 length; + enum v4l2_memory memory; struct v4l2_plane32 __user *uplane32; struct v4l2_plane __user *uplane; compat_caddr_t p; @@ -413,28 +517,39 @@ int ret; if (!access_ok(VERIFY_READ, up, sizeof(struct v4l2_buffer32)) || - get_user(kp->index, &up->index) || - get_user(kp->type, &up->type) || - get_user(kp->flags, &up->flags) || - get_user(kp->memory, &up->memory) || - get_user(kp->length, &up->length)) - return -EFAULT; - - if (V4L2_TYPE_IS_OUTPUT(kp->type)) - if (get_user(kp->bytesused, &up->bytesused) || - get_user(kp->field, &up->field) || - get_user(kp->timestamp.tv_sec, &up->timestamp.tv_sec) || - get_user(kp->timestamp.tv_usec, - &up->timestamp.tv_usec)) + convert_in_user(&up->index, &kp->index) || + get_user(type, &up->type) || + put_user(type, &kp->type) || + convert_in_user(&up->flags, &kp->flags) || + get_user(memory, &up->memory) || + put_user(memory, &kp->memory) || + convert_in_user(&up->length, &kp->length) || + get_user(length, &up->length) || + put_user(length, &kp->length)) + return -EFAULT; + + if (V4L2_TYPE_IS_OUTPUT(type)) + if (convert_in_user(&up->bytesused, &kp->bytesused) || + convert_in_user(&up->field, &kp->field) || + convert_in_user(&up->timestamp.tv_sec, &kp->timestamp.tv_sec) || + convert_in_user(&up->timestamp.tv_usec, + &kp->timestamp.tv_usec)) return -EFAULT; - if (V4L2_TYPE_IS_MULTIPLANAR(kp->type)) { - num_planes = kp->length; + if (type == V4L2_BUF_TYPE_PRIVATE) { + compat_long_t tmp; + + if (get_user(tmp, &up->m.userptr) || + put_user((unsigned long) compat_ptr(tmp), + &kp->m.userptr)) + return put_user(NULL, &kp->m.planes);; + } + if (V4L2_TYPE_IS_MULTIPLANAR(type)) { + num_planes = length; if (num_planes == 0) { - kp->m.planes = NULL; /* num_planes == 0 is legal, e.g. when userspace doesn't * need planes array on DQBUF*/ - return 0; + return put_user(NULL, &kp->m.planes); } if (get_user(p, &up->m.planes)) @@ -447,39 +562,44 @@ /* We don't really care if userspace decides to kill itself * by passing a very big num_planes value */ - uplane = compat_alloc_user_space(num_planes * - sizeof(struct v4l2_plane)); - kp->m.planes = (__force struct v4l2_plane *)uplane; + if (aux_space < num_planes * sizeof(struct v4l2_plane)) + return -EFAULT; + + uplane = aux_buf; + if (put_user((__force struct v4l2_plane *)uplane, + &kp->m.planes)) + return -EFAULT; while (--num_planes >= 0) { - ret = get_v4l2_plane32(uplane, uplane32, kp->memory); + ret = get_v4l2_plane32(uplane, uplane32, memory); if (ret) return ret; ++uplane; ++uplane32; } } else { - switch (kp->memory) { + switch (memory) { case V4L2_MEMORY_MMAP: - if (get_user(kp->m.offset, &up->m.offset)) + if (convert_in_user(&up->m.offset, &kp->m.offset)) return -EFAULT; break; case V4L2_MEMORY_USERPTR: { compat_long_t tmp; - if (get_user(tmp, &up->m.userptr)) + if (get_user(tmp, &up->m.userptr) || + put_user((unsigned long) + compat_ptr(tmp), + &kp->m.userptr)) return -EFAULT; - - kp->m.userptr = (unsigned long)compat_ptr(tmp); } break; case V4L2_MEMORY_OVERLAY: - if (get_user(kp->m.offset, &up->m.offset)) + if (convert_in_user(&up->m.offset, &kp->m.offset)) return -EFAULT; break; case V4L2_MEMORY_DMABUF: - if (get_user(kp->m.fd, &up->m.fd)) + if (convert_in_user(&up->m.fd, &kp->m.fd)) return -EFAULT; break; } @@ -488,8 +608,11 @@ return 0; } -static int put_v4l2_buffer32(struct v4l2_buffer *kp, struct v4l2_buffer32 __user *up) +static int put_v4l2_buffer32(struct v4l2_buffer __user *kp, struct v4l2_buffer32 __user *up) { + __u32 type; + __u32 length; + enum v4l2_memory memory; struct v4l2_plane32 __user *uplane32; struct v4l2_plane __user *uplane; compat_caddr_t p; @@ -497,56 +620,63 @@ int ret; if (!access_ok(VERIFY_WRITE, up, sizeof(struct v4l2_buffer32)) || - put_user(kp->index, &up->index) || - put_user(kp->type, &up->type) || - put_user(kp->flags, &up->flags) || - put_user(kp->memory, &up->memory)) - return -EFAULT; - - if (put_user(kp->bytesused, &up->bytesused) || - put_user(kp->field, &up->field) || - put_user(kp->timestamp.tv_sec, &up->timestamp.tv_sec) || - put_user(kp->timestamp.tv_usec, &up->timestamp.tv_usec) || - copy_to_user(&up->timecode, &kp->timecode, sizeof(struct v4l2_timecode)) || - put_user(kp->sequence, &up->sequence) || - put_user(kp->reserved2, &up->reserved2) || - put_user(kp->reserved, &up->reserved) || - put_user(kp->length, &up->length)) + convert_in_user(&kp->index, &up->index) || + get_user(type, &kp->type) || + put_user(type, &up->type) || + convert_in_user(&kp->flags, &up->flags) || + get_user(memory, &kp->memory) || + put_user(memory, &up->memory)) + return -EFAULT; + + if (convert_in_user(&kp->bytesused, &up->bytesused) || + convert_in_user(&kp->field, &up->field) || + convert_in_user(&kp->timestamp.tv_sec, &up->timestamp.tv_sec) || + convert_in_user(&kp->timestamp.tv_usec, &up->timestamp.tv_usec) || + copy_in_user(&up->timecode, &kp->timecode, sizeof(struct v4l2_timecode)) || + convert_in_user(&kp->sequence, &up->sequence) || + convert_in_user(&kp->reserved2, &up->reserved2) || + convert_in_user(&kp->reserved, &up->reserved) || + get_user(length, &kp->length) || + put_user(length, &up->length)) + return -EFAULT; + if (type == V4L2_BUF_TYPE_PRIVATE) + if (convert_in_user(&kp->m.userptr, &up->m.userptr)) return -EFAULT; - if (V4L2_TYPE_IS_MULTIPLANAR(kp->type)) { - num_planes = kp->length; + if (V4L2_TYPE_IS_MULTIPLANAR(type)) { + num_planes = length; if (num_planes == 0) return 0; - uplane = (__force struct v4l2_plane __user *)kp->m.planes; + if (get_user(uplane, ((__force struct v4l2_plane __user **)&kp->m.planes))) + return -EFAULT; if (get_user(p, &up->m.planes)) return -EFAULT; uplane32 = compat_ptr(p); while (--num_planes >= 0) { - ret = put_v4l2_plane32(uplane, uplane32, kp->memory); + ret = put_v4l2_plane32(uplane, uplane32, memory); if (ret) return ret; ++uplane; ++uplane32; } } else { - switch (kp->memory) { + switch (memory) { case V4L2_MEMORY_MMAP: - if (put_user(kp->m.offset, &up->m.offset)) + if (convert_in_user(&kp->m.offset, &up->m.offset)) return -EFAULT; break; case V4L2_MEMORY_USERPTR: - if (put_user(kp->m.userptr, &up->m.userptr)) + if (convert_in_user(&kp->m.userptr, &up->m.userptr)) return -EFAULT; break; case V4L2_MEMORY_OVERLAY: - if (put_user(kp->m.offset, &up->m.offset)) + if (convert_in_user(&kp->m.offset, &up->m.offset)) return -EFAULT; break; case V4L2_MEMORY_DMABUF: - if (put_user(kp->m.fd, &up->m.fd)) + if (convert_in_user(&kp->m.fd, &up->m.fd)) return -EFAULT; break; } @@ -571,33 +701,35 @@ } fmt; }; -static int get_v4l2_framebuffer32(struct v4l2_framebuffer *kp, struct v4l2_framebuffer32 __user *up) +static int get_v4l2_framebuffer32(struct v4l2_framebuffer __user *kp, struct v4l2_framebuffer32 __user *up) { - u32 tmp; + compat_caddr_t tmp; if (!access_ok(VERIFY_READ, up, sizeof(struct v4l2_framebuffer32)) || get_user(tmp, &up->base) || - get_user(kp->capability, &up->capability) || - get_user(kp->flags, &up->flags) || - copy_from_user(&kp->fmt, &up->fmt, sizeof(up->fmt))) + put_user((__force void *)compat_ptr(tmp), &kp->base) || + convert_in_user(&up->capability, &kp->capability) || + convert_in_user(&up->flags, &kp->flags) || + get_v4l2_pix_format((struct v4l2_pix_format *)&kp->fmt, (struct v4l2_pix_format *)&up->fmt)) return -EFAULT; - kp->base = (__force void *)compat_ptr(tmp); return 0; } -static int put_v4l2_framebuffer32(struct v4l2_framebuffer *kp, struct v4l2_framebuffer32 __user *up) +static int put_v4l2_framebuffer32(struct v4l2_framebuffer __user *kp, struct v4l2_framebuffer32 __user *up) { - u32 tmp = (u32)((unsigned long)kp->base); + void *base; if (!access_ok(VERIFY_WRITE, up, sizeof(struct v4l2_framebuffer32)) || - put_user(tmp, &up->base) || - put_user(kp->capability, &up->capability) || - put_user(kp->flags, &up->flags) || - copy_to_user(&up->fmt, &kp->fmt, sizeof(up->fmt))) + get_user(base, &kp->base) || + put_user(ptr_to_compat(base), &up->base) || + convert_in_user(&kp->capability, &up->capability) || + convert_in_user(&kp->flags, &up->flags) || + put_v4l2_pix_format((struct v4l2_pix_format *)&kp->fmt, (struct v4l2_pix_format *)&up->fmt)) return -EFAULT; return 0; } + struct v4l2_input32 { __u32 index; /* Which input */ __u8 name[32]; /* Label */ @@ -611,16 +743,16 @@ /* The 64-bit v4l2_input struct has extra padding at the end of the struct. Otherwise it is identical to the 32-bit version. */ -static inline int get_v4l2_input32(struct v4l2_input *kp, struct v4l2_input32 __user *up) +static inline int get_v4l2_input32(struct v4l2_input __user *kp, struct v4l2_input32 __user *up) { - if (copy_from_user(kp, up, sizeof(struct v4l2_input32))) + if (copy_in_user(kp, up, sizeof(struct v4l2_input32))) return -EFAULT; return 0; } -static inline int put_v4l2_input32(struct v4l2_input *kp, struct v4l2_input32 __user *up) +static inline int put_v4l2_input32(struct v4l2_input __user *kp, struct v4l2_input32 __user *up) { - if (copy_to_user(up, kp, sizeof(struct v4l2_input32))) + if (copy_in_user(up, kp, sizeof(struct v4l2_input32))) return -EFAULT; return 0; } @@ -661,34 +793,50 @@ } } -static int get_v4l2_ext_controls32(struct v4l2_ext_controls *kp, struct v4l2_ext_controls32 __user *up) +static int bufsize_v4l2_ext_controls32(struct v4l2_ext_controls32 __user *up) +{ + __u32 count; + + if (!access_ok(VERIFY_READ, up, sizeof(struct v4l2_ext_controls32)) || + get_user(count, &up->count)) + return -EFAULT; + if (count > V4L2_CID_MAX_CTRLS) + return -EINVAL; + return count * sizeof(struct v4l2_ext_control); +} + +static int get_v4l2_ext_controls32(struct v4l2_ext_controls __user *kp, struct + v4l2_ext_controls32 __user *up, void __user *aux_buf, + int aux_space) { struct v4l2_ext_control32 __user *ucontrols; struct v4l2_ext_control __user *kcontrols; - int n; + __u32 count; + unsigned int n; compat_caddr_t p; if (!access_ok(VERIFY_READ, up, sizeof(struct v4l2_ext_controls32)) || - get_user(kp->ctrl_class, &up->ctrl_class) || - get_user(kp->count, &up->count) || - get_user(kp->error_idx, &up->error_idx) || - copy_from_user(kp->reserved, up->reserved, - sizeof(kp->reserved))) - return -EFAULT; - n = kp->count; - if (n == 0) { - kp->controls = NULL; - return 0; - } + convert_in_user(&up->ctrl_class, &kp->ctrl_class) || + get_user(count, &up->count) || + put_user(count, &kp->count) || + convert_in_user(&up->error_idx, &kp->error_idx) || + copy_in_user(kp->reserved, up->reserved, sizeof(kp->reserved))) + return -EFAULT; + if (count == 0) + return put_user(NULL, &kp->controls); if (get_user(p, &up->controls)) return -EFAULT; ucontrols = compat_ptr(p); if (!access_ok(VERIFY_READ, ucontrols, - n * sizeof(struct v4l2_ext_control32))) + count * sizeof(struct v4l2_ext_control32))) return -EFAULT; - kcontrols = compat_alloc_user_space(n * sizeof(struct v4l2_ext_control)); - kp->controls = (__force struct v4l2_ext_control *)kcontrols; - while (--n >= 0) { + if (aux_space < count * sizeof(struct v4l2_ext_control)) + return -EFAULT; + kcontrols = aux_buf; + if (put_user((__force struct v4l2_ext_control *)kcontrols, + &kp->controls)) + return -EFAULT; + for (n = 0; n < count; n++) { u32 id; if (copy_in_user(kcontrols, ucontrols, sizeof(*ucontrols))) @@ -710,31 +858,33 @@ return 0; } -static int put_v4l2_ext_controls32(struct v4l2_ext_controls *kp, struct v4l2_ext_controls32 __user *up) +static int put_v4l2_ext_controls32(struct v4l2_ext_controls __user *kp, struct v4l2_ext_controls32 __user *up) { struct v4l2_ext_control32 __user *ucontrols; - struct v4l2_ext_control __user *kcontrols = - (__force struct v4l2_ext_control __user *)kp->controls; - int n = kp->count; + struct v4l2_ext_control __user *kcontrols; + __u32 count; + unsigned int n; compat_caddr_t p; if (!access_ok(VERIFY_WRITE, up, sizeof(struct v4l2_ext_controls32)) || - put_user(kp->ctrl_class, &up->ctrl_class) || - put_user(kp->count, &up->count) || - put_user(kp->error_idx, &up->error_idx) || - copy_to_user(up->reserved, kp->reserved, sizeof(up->reserved))) + get_user(kcontrols, &kp->controls) || + convert_in_user(&kp->ctrl_class, &up->ctrl_class) || + get_user(count, &kp->count) || + put_user(count, &up->count) || + convert_in_user(&kp->error_idx, &up->error_idx) || + copy_in_user(up->reserved, kp->reserved, sizeof(up->reserved))) return -EFAULT; - if (!kp->count) + if (!count) return 0; if (get_user(p, &up->controls)) return -EFAULT; ucontrols = compat_ptr(p); if (!access_ok(VERIFY_WRITE, ucontrols, - n * sizeof(struct v4l2_ext_control32))) + count * sizeof(struct v4l2_ext_control32))) return -EFAULT; - while (--n >= 0) { + for (n = 0; n < count; n++) { unsigned size = sizeof(*ucontrols); u32 id; @@ -756,6 +906,11 @@ struct v4l2_event32 { __u32 type; union { + struct v4l2_event_vsync vsync; + struct v4l2_event_ctrl ctrl; + struct v4l2_event_frame_sync frame_sync; + struct v4l2_event_src_change src_change; + struct v4l2_event_motion_det motion_det; compat_s64 value64; __u8 data[64]; } u; @@ -769,14 +924,14 @@ static int put_v4l2_event32(struct v4l2_event *kp, struct v4l2_event32 __user *up) { if (!access_ok(VERIFY_WRITE, up, sizeof(struct v4l2_event32)) || - put_user(kp->type, &up->type) || - copy_to_user(&up->u, &kp->u, sizeof(kp->u)) || - put_user(kp->pending, &up->pending) || - put_user(kp->sequence, &up->sequence) || - put_user(kp->timestamp.tv_sec, &up->timestamp.tv_sec) || - put_user(kp->timestamp.tv_nsec, &up->timestamp.tv_nsec) || - put_user(kp->id, &up->id) || - copy_to_user(up->reserved, kp->reserved, 8 * sizeof(__u32))) + convert_in_user(&kp->type, &up->type) || + copy_in_user(&up->u, &kp->u, sizeof(kp->u)) || + convert_in_user(&kp->pending, &up->pending) || + convert_in_user(&kp->sequence, &up->sequence) || + convert_in_user(&kp->timestamp.tv_sec, &up->timestamp.tv_sec) || + convert_in_user(&kp->timestamp.tv_nsec, &up->timestamp.tv_nsec) || + convert_in_user(&kp->id, &up->id) || + copy_in_user(up->reserved, kp->reserved, 8 * sizeof(__u32))) return -EFAULT; return 0; } @@ -789,31 +944,34 @@ compat_caddr_t edid; }; -static int get_v4l2_edid32(struct v4l2_edid *kp, struct v4l2_edid32 __user *up) +#define v4l2_subdev_edid32 v4l2_edid32 + +static int get_v4l2_subdev_edid32(struct v4l2_subdev_edid __user *kp, struct v4l2_subdev_edid32 __user *up) { - u32 tmp; + compat_uptr_t tmp; - if (!access_ok(VERIFY_READ, up, sizeof(struct v4l2_edid32)) || - get_user(kp->pad, &up->pad) || - get_user(kp->start_block, &up->start_block) || - get_user(kp->blocks, &up->blocks) || + if (!access_ok(VERIFY_READ, up, sizeof(struct v4l2_subdev_edid32)) || + convert_in_user(&up->pad, &kp->pad) || + convert_in_user(&up->start_block, &kp->start_block) || + convert_in_user(&up->blocks, &kp->blocks) || get_user(tmp, &up->edid) || - copy_from_user(kp->reserved, up->reserved, sizeof(kp->reserved))) + put_user(compat_ptr(tmp), &kp->edid) || + copy_in_user(kp->reserved, up->reserved, sizeof(kp->reserved))) return -EFAULT; - kp->edid = (__force u8 *)compat_ptr(tmp); return 0; } -static int put_v4l2_edid32(struct v4l2_edid *kp, struct v4l2_edid32 __user *up) +static int put_v4l2_subdev_edid32(struct v4l2_subdev_edid __user *kp, struct v4l2_subdev_edid32 __user *up) { - u32 tmp = (u32)((unsigned long)kp->edid); + void *edid; - if (!access_ok(VERIFY_WRITE, up, sizeof(struct v4l2_edid32)) || - put_user(kp->pad, &up->pad) || - put_user(kp->start_block, &up->start_block) || - put_user(kp->blocks, &up->blocks) || - put_user(tmp, &up->edid) || - copy_to_user(up->reserved, kp->reserved, sizeof(up->reserved))) + if (!access_ok(VERIFY_WRITE, up, sizeof(struct v4l2_subdev_edid32)) || + convert_in_user(&kp->pad, &up->pad) || + convert_in_user(&kp->start_block, &up->start_block) || + convert_in_user(&kp->blocks, &up->blocks) || + get_user(edid, &kp->edid) || + put_user(ptr_to_compat(edid), &up->edid) || + copy_in_user(up->reserved, kp->reserved, sizeof(up->reserved))) return -EFAULT; return 0; } @@ -846,22 +1004,37 @@ #define VIDIOC_G_OUTPUT32 _IOR ('V', 46, s32) #define VIDIOC_S_OUTPUT32 _IOWR('V', 47, s32) +/* + * Note that these macros contain return statements to avoid the need for the + * "caller" to check return values. + */ +#define ALLOC_USER_SPACE(size) \ +({ \ + void __user *up_native; \ + up_native = compat_alloc_user_space(size); \ + if (!up_native) \ + return -ENOMEM; \ + if (clear_user(up_native, size)) \ + return -EFAULT; \ + up_native; \ +}) + +#define ALLOC_AND_GET(bufsizefunc, getfunc, structname) \ + do { \ + aux_space = bufsizefunc(up); \ + if (aux_space < 0) \ + return aux_space; \ + up_native = ALLOC_USER_SPACE(sizeof(struct structname) + aux_space); \ + aux_buf = up_native + sizeof(struct structname); \ + err = getfunc(up_native, up, aux_buf, aux_space); \ + } while (0) + static long do_video_ioctl(struct file *file, unsigned int cmd, unsigned long arg) { - union { - struct v4l2_format v2f; - struct v4l2_buffer v2b; - struct v4l2_framebuffer v2fb; - struct v4l2_input v2i; - struct v4l2_standard v2s; - struct v4l2_ext_controls v2ecs; - struct v4l2_event v2ev; - struct v4l2_create_buffers v2crt; - struct v4l2_edid v2edid; - unsigned long vx; - int vi; - } karg; void __user *up = compat_ptr(arg); + void __user *up_native = NULL; + void __user *aux_buf; + int aux_space; int compatible_arg = 1; long err = 0; @@ -900,30 +1073,35 @@ case VIDIOC_STREAMOFF: case VIDIOC_S_INPUT: case VIDIOC_S_OUTPUT: - err = get_user(karg.vi, (s32 __user *)up); + up_native = ALLOC_USER_SPACE(sizeof(unsigned __user)); + if (convert_in_user((compat_uint_t __user *)up, + (unsigned __user *) up_native)) + return -EFAULT; compatible_arg = 0; break; case VIDIOC_G_INPUT: case VIDIOC_G_OUTPUT: + up_native = ALLOC_USER_SPACE(sizeof(unsigned __user)); compatible_arg = 0; break; case VIDIOC_G_EDID: case VIDIOC_S_EDID: - err = get_v4l2_edid32(&karg.v2edid, up); + up_native = ALLOC_USER_SPACE(sizeof(struct v4l2_subdev_edid)); + err = get_v4l2_subdev_edid32(up_native, up); compatible_arg = 0; break; case VIDIOC_G_FMT: case VIDIOC_S_FMT: case VIDIOC_TRY_FMT: - err = get_v4l2_format32(&karg.v2f, up); + ALLOC_AND_GET(bufsize_v4l2_format32, get_v4l2_format32, v4l2_format); compatible_arg = 0; break; case VIDIOC_CREATE_BUFS: - err = get_v4l2_create32(&karg.v2crt, up); + ALLOC_AND_GET(bufsize_v4l2_create32, get_v4l2_create32, v4l2_create_buffers); compatible_arg = 0; break; @@ -931,36 +1109,41 @@ case VIDIOC_QUERYBUF: case VIDIOC_QBUF: case VIDIOC_DQBUF: - err = get_v4l2_buffer32(&karg.v2b, up); + ALLOC_AND_GET(bufsize_v4l2_buffer32, get_v4l2_buffer32, v4l2_buffer); compatible_arg = 0; break; case VIDIOC_S_FBUF: - err = get_v4l2_framebuffer32(&karg.v2fb, up); + up_native = ALLOC_USER_SPACE(sizeof(struct v4l2_framebuffer)); + err = get_v4l2_framebuffer32(up_native, up); compatible_arg = 0; break; case VIDIOC_G_FBUF: + up_native = ALLOC_USER_SPACE(sizeof(struct v4l2_framebuffer)); compatible_arg = 0; break; case VIDIOC_ENUMSTD: - err = get_v4l2_standard32(&karg.v2s, up); + up_native = ALLOC_USER_SPACE(sizeof(struct v4l2_standard)); + err = get_v4l2_standard32(up_native, up); compatible_arg = 0; break; case VIDIOC_ENUMINPUT: - err = get_v4l2_input32(&karg.v2i, up); + up_native = ALLOC_USER_SPACE(sizeof(struct v4l2_input)); + err = get_v4l2_input32(up_native, up); compatible_arg = 0; break; case VIDIOC_G_EXT_CTRLS: case VIDIOC_S_EXT_CTRLS: case VIDIOC_TRY_EXT_CTRLS: - err = get_v4l2_ext_controls32(&karg.v2ecs, up); + ALLOC_AND_GET(bufsize_v4l2_ext_controls32, get_v4l2_ext_controls32, v4l2_ext_controls); compatible_arg = 0; break; case VIDIOC_DQEVENT: + up_native = ALLOC_USER_SPACE(sizeof(struct v4l2_event)); compatible_arg = 0; break; } @@ -969,13 +1152,8 @@ if (compatible_arg) err = native_ioctl(file, cmd, (unsigned long)up); - else { - mm_segment_t old_fs = get_fs(); - - set_fs(KERNEL_DS); - err = native_ioctl(file, cmd, (unsigned long)&karg); - set_fs(old_fs); - } + else + err = native_ioctl(file, cmd, (unsigned long)up_native); /* Special case: even after an error we need to put the results back for these ioctls since the error_idx will @@ -984,7 +1162,7 @@ case VIDIOC_G_EXT_CTRLS: case VIDIOC_S_EXT_CTRLS: case VIDIOC_TRY_EXT_CTRLS: - if (put_v4l2_ext_controls32(&karg.v2ecs, up)) + if (put_v4l2_ext_controls32(up_native, up)) err = -EFAULT; break; } @@ -996,44 +1174,44 @@ case VIDIOC_S_OUTPUT: case VIDIOC_G_INPUT: case VIDIOC_G_OUTPUT: - err = put_user(((s32)karg.vi), (s32 __user *)up); + err = convert_in_user(((unsigned __user *)up_native), + (compat_uint_t __user *)up); break; - case VIDIOC_G_FBUF: - err = put_v4l2_framebuffer32(&karg.v2fb, up); + err = put_v4l2_framebuffer32(up_native, up); break; case VIDIOC_DQEVENT: - err = put_v4l2_event32(&karg.v2ev, up); + err = put_v4l2_event32(up_native, up); break; case VIDIOC_G_EDID: case VIDIOC_S_EDID: - err = put_v4l2_edid32(&karg.v2edid, up); + err = put_v4l2_subdev_edid32(up_native, up); break; case VIDIOC_G_FMT: case VIDIOC_S_FMT: case VIDIOC_TRY_FMT: - err = put_v4l2_format32(&karg.v2f, up); + err = put_v4l2_format32(up_native, up); break; case VIDIOC_CREATE_BUFS: - err = put_v4l2_create32(&karg.v2crt, up); + err = put_v4l2_create32(up_native, up); break; case VIDIOC_QUERYBUF: case VIDIOC_QBUF: case VIDIOC_DQBUF: - err = put_v4l2_buffer32(&karg.v2b, up); + err = put_v4l2_buffer32(up_native, up); break; case VIDIOC_ENUMSTD: - err = put_v4l2_standard32(&karg.v2s, up); + err = put_v4l2_standard32(up_native, up); break; case VIDIOC_ENUMINPUT: - err = put_v4l2_input32(&karg.v2i, up); + err = put_v4l2_input32(up_native, up); break; } return err; diff -ruw linux-4.4.115/drivers/media/v4l2-core/v4l2-ctrls.c linux-4.4.115-fbx/drivers/media/v4l2-core/v4l2-ctrls.c --- linux-4.4.115/drivers/media/v4l2-core/v4l2-ctrls.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/media/v4l2-core/v4l2-ctrls.c 2019-10-29 09:26:24.009206760 +0100 @@ -307,12 +307,14 @@ static const char * const header_mode[] = { "Separate Buffer", "Joined With 1st Frame", + "Joined With I frame", NULL, }; static const char * const multi_slice[] = { "Single", "Max Macroblocks", "Max Bytes", + "GOB", NULL, }; static const char * const entropy_mode[] = { @@ -337,6 +339,7 @@ "4.2", "5", "5.1", + "5.2", NULL, }; static const char * const h264_loop_filter[] = { @@ -361,7 +364,9 @@ "Scalable Baseline", "Scalable High", "Scalable High Intra", + "Stereo High", "Multiview High", + "Constrained High", NULL, }; static const char * const vui_sar_idc[] = { diff -ruw linux-4.4.115/drivers/media/v4l2-core/v4l2-ioctl.c linux-4.4.115-fbx/drivers/media/v4l2-core/v4l2-ioctl.c --- linux-4.4.115/drivers/media/v4l2-core/v4l2-ioctl.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/media/v4l2-core/v4l2-ioctl.c 2019-10-29 09:26:24.013206799 +0100 @@ -1229,6 +1229,84 @@ case V4L2_SDR_FMT_CS8: descr = "Complex S8"; break; case V4L2_SDR_FMT_CS14LE: descr = "Complex S14LE"; break; case V4L2_SDR_FMT_RU12LE: descr = "Real U12LE"; break; + case V4L2_PIX_FMT_NV12_UBWC: + descr = "NV12 UBWC"; break; + case V4L2_PIX_FMT_RGBA8888_UBWC: + descr = "RGBA8888 UBWC"; break; + case V4L2_PIX_FMT_SDE_ABGR_8888: + descr = "32-bit ABGR 8-8-8-8"; break; + case V4L2_PIX_FMT_SDE_RGBA_8888: + descr = "32-bit RGBA 8-8-8-8"; break; + case V4L2_PIX_FMT_SDE_RGBX_8888: + descr = "32-bit RGBX 8-8-8-8"; break; + case V4L2_PIX_FMT_SDE_XBGR_8888: + descr = "32-bit XBGR 8-8-8-8"; break; + case V4L2_PIX_FMT_SDE_RGBA_5551: + descr = "16-bit RGBA 5-5-5-1"; break; + case V4L2_PIX_FMT_SDE_ABGR_1555: + descr = "16-bit ABGR 1-5-5-5"; break; + case V4L2_PIX_FMT_SDE_BGRA_5551: + descr = "16-bit BGRA 5-5-5-1"; break; + case V4L2_PIX_FMT_SDE_BGRX_5551: + descr = "16-bit BGRX 5-5-5-1"; break; + case V4L2_PIX_FMT_SDE_RGBX_5551: + descr = "16-bit RGBX 5-5-5-1"; break; + case V4L2_PIX_FMT_SDE_XBGR_1555: + descr = "16-bit XBGR 1-5-5-5"; break; + case V4L2_PIX_FMT_SDE_RGBA_4444: + descr = "16-bit RGBA 4-4-4-4"; break; + case V4L2_PIX_FMT_SDE_BGRA_4444: + descr = "16-bit BGRA 4-4-4-4"; break; + case V4L2_PIX_FMT_SDE_ABGR_4444: + descr = "16-bit ABGR 4-4-4-4"; break; + case V4L2_PIX_FMT_SDE_RGBX_4444: + descr = "16-bit RGBX 4-4-4-4"; break; + case V4L2_PIX_FMT_SDE_BGRX_4444: + descr = "16-bit BGRX 4-4-4-4"; break; + case V4L2_PIX_FMT_SDE_XBGR_4444: + descr = "16-bit XBGR 4-4-4-4"; break; + case V4L2_PIX_FMT_SDE_BGR_565: + descr = "16-bit BGR 5-6-5"; break; + case V4L2_PIX_FMT_SDE_Y_CR_CB_GH2V2: + descr = "Planar YVU 4:2:0 A16"; break; + case V4L2_PIX_FMT_SDE_Y_CBCR_H1V2: + descr = "Y/CbCr 4:2:2"; break; + case V4L2_PIX_FMT_SDE_Y_CRCB_H1V2: + descr = "Y/CrCb 4:2:2"; break; + case V4L2_PIX_FMT_SDE_Y_CBCR_H2V2_VENUS: + descr = "Y/CbCr 4:2:0 Venus"; break; + case V4L2_PIX_FMT_SDE_Y_CRCB_H2V2_VENUS: + descr = "Y/CrCb 4:2:0 Venus"; break; + case V4L2_PIX_FMT_SDE_RGBX_8888_UBWC: + descr = "RGBX 8:8:8:8 UBWC"; break; + case V4L2_PIX_FMT_SDE_RGB_565_UBWC: + descr = "RGB 5:6:5 UBWC"; break; + case V4L2_PIX_FMT_SDE_RGBA_1010102: + descr = "RGBA 10:10:10:2"; break; + case V4L2_PIX_FMT_SDE_RGBX_1010102: + descr = "RGBX 10:10:10:2"; break; + case V4L2_PIX_FMT_SDE_ARGB_2101010: + descr = "ARGB 2:10:10:10"; break; + case V4L2_PIX_FMT_SDE_XRGB_2101010: + descr = "XRGB 2:10:10:10"; break; + case V4L2_PIX_FMT_SDE_BGRA_1010102: + descr = "BGRA 10:10:10:2"; break; + case V4L2_PIX_FMT_SDE_BGRX_1010102: + descr = "BGRX 10:10:10:2"; break; + case V4L2_PIX_FMT_SDE_ABGR_2101010: + descr = "ABGR 2:10:10:10"; break; + case V4L2_PIX_FMT_SDE_XBGR_2101010: + descr = "XBGR 2:10:10:10"; break; + case V4L2_PIX_FMT_SDE_RGBA_1010102_UBWC: + descr = "RGBA 10:10:10:2 UBWC"; break; + case V4L2_PIX_FMT_SDE_RGBX_1010102_UBWC: + descr = "RGBX 10:10:10:2 UBWC"; break; + case V4L2_PIX_FMT_SDE_Y_CBCR_H2V2_TP10: + descr = "Y/CbCr 4:2:0 TP10"; break; + case V4L2_PIX_FMT_SDE_Y_CBCR_H2V2_P010: + descr = "Y/CbCr 4:2:0 P10"; break; + case V4L2_PIX_FMT_NV12_TP10_UBWC: + descr = "Y/CbCr 4:2:0 TP10 UBWC"; break; default: /* Compressed formats */ @@ -1268,6 +1346,16 @@ case V4L2_PIX_FMT_JPGL: descr = "JPEG Lite"; break; case V4L2_PIX_FMT_SE401: descr = "GSPCA SE401"; break; case V4L2_PIX_FMT_S5C_UYVY_JPG: descr = "S5C73MX interleaved UYVY/JPEG"; break; + case V4L2_PIX_FMT_HEVC: + descr = "HEVC"; break; + case V4L2_PIX_FMT_HEVC_HYBRID: + descr = "HEVC Hybrid"; break; + case V4L2_PIX_FMT_VP9: + descr = "VP9"; break; + case V4L2_PIX_FMT_DIVX_311: + descr = "DIVX311"; break; + case V4L2_PIX_FMT_DIVX: + descr = "DIVX"; break; default: WARN(1, "Unknown pixelformat 0x%08x\n", fmt->pixelformat); if (fmt->description[0]) diff -ruw linux-4.4.115/drivers/media/v4l2-core/videobuf2-v4l2.c linux-4.4.115-fbx/drivers/media/v4l2-core/videobuf2-v4l2.c --- linux-4.4.115/drivers/media/v4l2-core/videobuf2-v4l2.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/media/v4l2-core/videobuf2-v4l2.c 2019-10-29 09:26:24.017206838 +0100 @@ -133,23 +133,6 @@ return 0; }; -static void vb2_warn_zero_bytesused(struct vb2_buffer *vb) -{ - static bool check_once; - - if (check_once) - return; - - check_once = true; - WARN_ON(1); - - pr_warn("use of bytesused == 0 is deprecated and will be removed in the future,\n"); - if (vb->vb2_queue->allow_zero_bytesused) - pr_warn("use VIDIOC_DECODER_CMD(V4L2_DEC_CMD_STOP) instead.\n"); - else - pr_warn("use the actual size instead.\n"); -} - static int vb2_queue_or_prepare_buf(struct vb2_queue *q, struct v4l2_buffer *b, const char *opname) { @@ -357,9 +340,6 @@ struct vb2_plane *pdst = &planes[plane]; struct v4l2_plane *psrc = &b->m.planes[plane]; - if (psrc->bytesused == 0) - vb2_warn_zero_bytesused(vb); - if (vb->vb2_queue->allow_zero_bytesused) pdst->bytesused = psrc->bytesused; else @@ -394,9 +374,6 @@ } if (V4L2_TYPE_IS_OUTPUT(b->type)) { - if (b->bytesused == 0) - vb2_warn_zero_bytesused(vb); - if (vb->vb2_queue->allow_zero_bytesused) planes[0].bytesused = b->bytesused; else diff -ruw linux-4.4.115/drivers/mfd/Kconfig linux-4.4.115-fbx/drivers/mfd/Kconfig --- linux-4.4.115/drivers/mfd/Kconfig 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/mfd/Kconfig 2019-01-22 16:16:24.663256911 +0100 @@ -708,7 +708,7 @@ config MFD_SPMI_PMIC tristate "Qualcomm SPMI PMICs" - depends on ARCH_QCOM || COMPILE_TEST + depends on ARCH_QCOM || COMPILE_TEST || ARCH_MSM depends on OF depends on SPMI select REGMAP_SPMI @@ -721,6 +721,20 @@ Say M here if you want to include support for the SPMI PMIC series as a module. The module will be called "qcom-spmi-pmic". +config MFD_I2C_PMIC + tristate "QTI I2C PMICs" + depends on OF + depends on I2C + select IRQ_DOMAIN + select REGMAP_I2C + help + This enables support for controlling Qualcomm Technologies, Inc. + PMICs over I2C. The driver controls interrupts, and provides register + access for all of the device's peripherals. + + Say M here if you want to include support for the I2C PMIC series as + a module. The module will be called "qcom-i2c-pmic". + config MFD_RDC321X tristate "RDC R-321x southbridge" select MFD_CORE @@ -1325,6 +1339,11 @@ additional drivers must be enabled in order to use the functionality of the device. +config MFD_FBX7HD_TOP_PSOC + tristate "Freebox fbx7hd top psoc" + depends on SPI_MASTER + depends on OF + config MFD_TMIO bool default n @@ -1493,6 +1512,77 @@ in various ST Microelectronics and ST-Ericsson embedded Nomadik series. +config MSM_CDC_PINCTRL + tristate "MSM Codec Pinctrl" + select MFD_CORE + help + Enables msm codec pinctrl driver. The pinctrl driver + provides support for handling WCD and WSA MSM gpios. This + pinctrl driver will handle WCD and WSA gpios pinctrl states. + This driver acts as interface between codec and pinctrl + framework. + +config MSM_CDC_SUPPLY + tristate "MSM Codec Power Supply" + help + Enables msm codec power supply driver. The power supply + driver provides API support for handling WCD and WSA codec + power supply enable or disable. This driver acts as interface + between codec and regulator framework. + +config WCD9XXX_CODEC_UTIL + tristate "WCD9XXX Codec Utils" + select MFD_CORE + help + WCD9XXX Util driver provides APIs for WCD drivers to reset, + suspend/resume, regmap bus callback functions and read/write + functions. This driver also hides the underlying bus related + functionalities. + +config WCD9330_CODEC + tristate "WCD9330 Codec" + select SLIMBUS + select MFD_CORE + select WCD9XXX_CODEC_UTIL + select MSM_CDC_SUPPLY + help + Enables the WCD9xxx codec core driver. The core driver provides + read/write capability to registers which are part of the + WCD9330 core and gives the ability to use the WCD9330 codec. + The WCD9330 codec support either I2C/I2S or Slimbus for + control and data exchnage with master processor. + +config WCD9335_CODEC + tristate "WCD9335 Codec" + select SLIMBUS + select SOUNDWIRE_WCD_CTRL + select MFD_CORE + select WCD9XXX_CODEC_UTIL + select MSM_CDC_SUPPLY + select MSM_CDC_PINCTRL + help + Enables the WCD9xxx codec core driver. The core driver provides + read/write capability to registers which are part of the + WCD9335 core and gives the ability to use the WCD9335 codec. + The WCD9335 codec support either I2C/I2S or Slimbus for + control and data exchnage with master processor. + +config WCD934X_CODEC + tristate "WCD934X Codec" + depends on SLIMBUS + select SOUNDWIRE_WCD_CTRL + select MFD_CORE + select WCD9XXX_CODEC_UTIL + select MSM_CDC_SUPPLY + select MSM_CDC_PINCTRL + select PINCTRL_WCD + help + Enables the WCD9xxx codec core driver. The core driver provides + read/write capability to registers which are part of the + WCD934X core and gives the ability to use the WCD934X codec. + The WCD934X codec supports either I2C/I2S or Slimbus for + control and data exchange with master processor. + menu "Multimedia Capabilities Port drivers" depends on ARCH_SA1100 diff -ruw linux-4.4.115/drivers/mfd/Makefile linux-4.4.115-fbx/drivers/mfd/Makefile --- linux-4.4.115/drivers/mfd/Makefile 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/mfd/Makefile 2019-01-22 16:16:24.663256911 +0100 @@ -63,6 +63,8 @@ obj-$(CONFIG_MFD_WM8350_I2C) += wm8350-i2c.o obj-$(CONFIG_MFD_WM8994) += wm8994-core.o wm8994-irq.o wm8994-regmap.o +obj-$(CONFIG_MFD_FBX7HD_TOP_PSOC) += fbx7hd-top-psoc.o + obj-$(CONFIG_TPS6105X) += tps6105x.o obj-$(CONFIG_TPS65010) += tps65010.o obj-$(CONFIG_TPS6507X) += tps6507x.o @@ -161,6 +163,7 @@ obj-$(CONFIG_MFD_PM8921_CORE) += pm8921-core.o ssbi.o obj-$(CONFIG_MFD_QCOM_RPM) += qcom_rpm.o obj-$(CONFIG_MFD_SPMI_PMIC) += qcom-spmi-pmic.o +obj-$(CONFIG_MFD_I2C_PMIC) += qcom-i2c-pmic.o obj-$(CONFIG_TPS65911_COMPARATOR) += tps65911-comparator.o obj-$(CONFIG_MFD_TPS65090) += tps65090.o obj-$(CONFIG_MFD_AAT2870_CORE) += aat2870-core.o @@ -189,7 +192,15 @@ obj-$(CONFIG_MFD_DLN2) += dln2.o obj-$(CONFIG_MFD_RT5033) += rt5033.o obj-$(CONFIG_MFD_SKY81452) += sky81452.o - +obj-$(CONFIG_MSM_CDC_PINCTRL) += msm-cdc-pinctrl.o +obj-$(CONFIG_MSM_CDC_SUPPLY) += msm-cdc-supply.o +obj-$(CONFIG_WCD9XXX_CODEC_UTIL) += wcd9xxx-utils.o +obj-$(CONFIG_WCD9330_CODEC) += wcd9xxx-core.o wcd9xxx-irq.o wcd9xxx-slimslave.o\ + wcd9330-regmap.o +obj-$(CONFIG_WCD9335_CODEC) += wcd9xxx-core.o wcd9xxx-irq.o wcd9xxx-slimslave.o\ + wcd9335-regmap.o wcd9335-tables.o +obj-$(CONFIG_WCD934X_CODEC) += wcd9xxx-core.o wcd9xxx-irq.o wcd9xxx-slimslave.o\ + wcd934x-regmap.o wcd934x-tables.o intel-soc-pmic-objs := intel_soc_pmic_core.o intel_soc_pmic_crc.o intel-soc-pmic-$(CONFIG_INTEL_PMC_IPC) += intel_soc_pmic_bxtwc.o obj-$(CONFIG_INTEL_SOC_PMIC) += intel-soc-pmic.o diff -ruw linux-4.4.115/drivers/mfd/qcom-spmi-pmic.c linux-4.4.115-fbx/drivers/mfd/qcom-spmi-pmic.c --- linux-4.4.115/drivers/mfd/qcom-spmi-pmic.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/mfd/qcom-spmi-pmic.c 2019-01-22 16:16:24.679257056 +0100 @@ -147,7 +147,12 @@ .of_match_table = pmic_spmi_id_table, }, }; -module_spmi_driver(pmic_spmi_driver); + +int __init pmic_spmi_init(void) +{ + return spmi_driver_register(&pmic_spmi_driver); +} +arch_initcall(pmic_spmi_init); MODULE_DESCRIPTION("Qualcomm SPMI PMIC driver"); MODULE_ALIAS("spmi:spmi-pmic"); diff -ruw linux-4.4.115/drivers/misc/Kconfig linux-4.4.115-fbx/drivers/misc/Kconfig --- linux-4.4.115/drivers/misc/Kconfig 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/misc/Kconfig 2019-05-31 20:58:54.922934968 +0200 @@ -487,6 +487,11 @@ To compile this driver as a module, choose M here: the module will be called pch_phub. +config FBXSERIAL_OF + bool "read fbxserial through DT chosen node" + depends on OF + select ARCH_HAS_FBXSERIAL + config USB_SWITCH_FSA9480 tristate "FSA9480 USB Switch" depends on I2C @@ -516,6 +521,30 @@ the genalloc API. It is supposed to be used for small on-chip SRAM areas found on many SoCs. +config QSEECOM + tristate "QTI Secure Execution Communicator driver" + help + Provides a communication interface between userspace and + QTI Secure Execution Environment (QSEE) using Secure Channel + Manager (SCM) interface. It exposes APIs for both userspace and + kernel clients. + +config HDCP_QSEECOM + tristate "QTI High-Bandwidth Digital Content Protection Module" + help + This module implements HDCP 2.2 features over HDMI. It exposes APIs + for HDMI driver to communicate with QTI Secure Execution + Environment (QSEE) via the QSEECOM Driver and also calls the APIs + exposed by the HDMI driver to communicate with the Receiver. + +config PROFILER + tristate "Qualcomm Technologies, Inc. trustzone Communicator driver" + help + Provides a communication interface between userspace and + trustzone using Secure Channel Manager (SCM) interface. + It exposes APIs for userspace to get system profiling + information. + config VEXPRESS_SYSCFG bool "Versatile Express System Configuration driver" depends on VEXPRESS_CONFIG @@ -525,6 +554,36 @@ bus. System Configuration interface is one of the possible means of generating transactions on this bus. +config UID_SYS_STATS + bool "Per-UID statistics" + depends on PROFILING && TASK_XACCT && TASK_IO_ACCOUNTING + help + Per UID based cpu time statistics exported to /proc/uid_cputime + Per UID based io statistics exported to /proc/uid_io + Per UID based procstat control in /proc/uid_procstat + +config QPNP_MISC + tristate "QPNP Misc Peripheral" + depends on SPMI || MSM_SPMI + help + Say 'y' here to include support for the QTI QPNP MISC + peripheral. The MISC peripheral holds the USB ID interrupt + and the driver provides an API to check if this interrupt + is available on the current PMIC chip. + +config UID_SYS_STATS_DEBUG + bool "Per-TASK statistics" + depends on UID_SYS_STATS + default n + help + Per TASK based io statistics exported to /proc/uid_io + +config MEMORY_STATE_TIME + tristate "Memory freq/bandwidth time statistics" + depends on PROFILING + help + Memory time statistics exported to /sys/kernel/memory_state_time + source "drivers/misc/c2port/Kconfig" source "drivers/misc/eeprom/Kconfig" source "drivers/misc/cb710/Kconfig" @@ -533,8 +592,11 @@ source "drivers/misc/altera-stapl/Kconfig" source "drivers/misc/mei/Kconfig" source "drivers/misc/vmw_vmci/Kconfig" +source "drivers/misc/qcom/Kconfig" source "drivers/misc/mic/Kconfig" source "drivers/misc/genwqe/Kconfig" source "drivers/misc/echo/Kconfig" source "drivers/misc/cxl/Kconfig" +source "drivers/misc/freebox/Kconfig" +source "drivers/misc/hdmi-cec/Kconfig" endmenu diff -ruw linux-4.4.115/drivers/misc/Makefile linux-4.4.115-fbx/drivers/misc/Makefile --- linux-4.4.115/drivers/misc/Makefile 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/misc/Makefile 2019-05-31 20:58:54.922934968 +0200 @@ -25,6 +25,7 @@ obj-$(CONFIG_SGI_IOC4) += ioc4.o obj-$(CONFIG_ENCLOSURE_SERVICES) += enclosure.o obj-$(CONFIG_KGDB_TESTS) += kgdbts.o +obj-$(CONFIG_FBXSERIAL_OF) += fbxserial_of.o obj-$(CONFIG_SGI_XP) += sgi-xp/ obj-$(CONFIG_SGI_GRU) += sgi-gru/ obj-$(CONFIG_CS5535_MFGPT) += cs5535-mfgpt.o @@ -53,6 +54,18 @@ obj-$(CONFIG_SRAM) += sram.o obj-y += mic/ obj-$(CONFIG_GENWQE) += genwqe/ +obj-$(CONFIG_QSEECOM) += qseecom.o +obj-$(CONFIG_PROFILER) += profiler.o +obj-$(CONFIG_HDCP_QSEECOM) += hdcp.o +ifdef CONFIG_COMPAT +obj-$(CONFIG_QSEECOM) += compat_qseecom.o +endif obj-$(CONFIG_ECHO) += echo/ obj-$(CONFIG_VEXPRESS_SYSCFG) += vexpress-syscfg.o obj-$(CONFIG_CXL_BASE) += cxl/ +obj-$(CONFIG_UID_SYS_STATS) += uid_sys_stats.o +obj-y += qcom/ +obj-$(CONFIG_QPNP_MISC) += qpnp-misc.o +obj-$(CONFIG_MEMORY_STATE_TIME) += memory_state_time.o +obj-y += freebox/ +obj-y += hdmi-cec/ diff -ruw linux-4.4.115/drivers/mmc/card/block.c linux-4.4.115-fbx/drivers/mmc/card/block.c --- linux-4.4.115/drivers/mmc/card/block.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/mmc/card/block.c 2019-10-29 09:26:24.053207190 +0100 @@ -30,14 +30,19 @@ #include #include #include +#include #include #include #include #include #include +#include + +#include #include #include +#include #include #include #include @@ -47,13 +52,10 @@ #include "queue.h" MODULE_ALIAS("mmc:block"); - -#ifdef KERNEL #ifdef MODULE_PARAM_PREFIX #undef MODULE_PARAM_PREFIX #endif #define MODULE_PARAM_PREFIX "mmcblk." -#endif #define INAND_CMD38_ARG_EXT_CSD 113 #define INAND_CMD38_ARG_ERASE 0x00 @@ -61,15 +63,33 @@ #define INAND_CMD38_ARG_SECERASE 0x80 #define INAND_CMD38_ARG_SECTRIM1 0x81 #define INAND_CMD38_ARG_SECTRIM2 0x88 -#define MMC_BLK_TIMEOUT_MS (10 * 60 * 1000) /* 10 minute timeout */ +#define MMC_BLK_TIMEOUT_MS (30 * 1000) /* 30 sec timeout */ #define MMC_SANITIZE_REQ_TIMEOUT 240000 #define MMC_EXTRACT_INDEX_FROM_ARG(x) ((x & 0x00FF0000) >> 16) +#define MMC_CMDQ_STOP_TIMEOUT_MS 100 #define mmc_req_rel_wr(req) ((req->cmd_flags & REQ_FUA) && \ (rq_data_dir(req) == WRITE)) #define PACKED_CMD_VER 0x01 #define PACKED_CMD_WR 0x02 +#define PACKED_TRIGGER_MAX_ELEMENTS 5000 + +#define MMC_BLK_MAX_RETRIES 5 /* max # of retries before aborting a command */ +#define MMC_BLK_UPDATE_STOP_REASON(stats, reason) \ + do { \ + if (stats->enabled) \ + stats->pack_stop_reason[reason]++; \ + } while (0) + +#define MAX_RETRIES 5 +#define PCKD_TRGR_INIT_MEAN_POTEN 17 +#define PCKD_TRGR_POTEN_LOWER_BOUND 5 +#define PCKD_TRGR_URGENT_PENALTY 2 +#define PCKD_TRGR_LOWER_BOUND 5 +#define PCKD_TRGR_PRECISION_MULTIPLIER 100 +static struct mmc_cmdq_req *mmc_cmdq_prep_dcmd( + struct mmc_queue_req *mqrq, struct mmc_queue *mq); static DEFINE_MUTEX(block_mutex); /* @@ -104,6 +124,7 @@ #define MMC_BLK_CMD23 (1 << 0) /* Can do SET_BLOCK_COUNT for multiblock */ #define MMC_BLK_REL_WR (1 << 1) /* MMC Reliable write support */ #define MMC_BLK_PACKED_CMD (1 << 2) /* MMC packed command support */ +#define MMC_BLK_CMD_QUEUE (1 << 3) /* MMC command queue support */ unsigned int usage; unsigned int read_only; @@ -114,6 +135,8 @@ #define MMC_BLK_WRITE BIT(1) #define MMC_BLK_DISCARD BIT(2) #define MMC_BLK_SECDISCARD BIT(3) +#define MMC_BLK_FLUSH BIT(4) +#define MMC_BLK_PARTSWITCH BIT(5) /* * Only set in main mmc_blk_data associated @@ -123,6 +146,8 @@ unsigned int part_curr; struct device_attribute force_ro; struct device_attribute power_ro_lock; + struct device_attribute num_wr_reqs_to_start_packing; + struct device_attribute no_pack_for_random; int area_type; }; @@ -140,6 +165,8 @@ static inline int mmc_blk_part_switch(struct mmc_card *card, struct mmc_blk_data *md); static int get_card_status(struct mmc_card *card, u32 *status, int retries); +static int mmc_blk_cmdq_switch(struct mmc_card *card, + struct mmc_blk_data *md, bool enable); static inline void mmc_blk_clear_packed(struct mmc_queue_req *mqrq) { @@ -171,11 +198,7 @@ static inline int mmc_get_devidx(struct gendisk *disk) { - int devmaj = MAJOR(disk_devt(disk)); - int devidx = MINOR(disk_devt(disk)) / perdev_minors; - - if (!devmaj) - devidx = disk->first_minor / perdev_minors; + int devidx = disk->first_minor / perdev_minors; return devidx; } @@ -200,9 +223,13 @@ { int ret; struct mmc_blk_data *md = mmc_blk_get(dev_to_disk(dev)); - struct mmc_card *card = md->queue.card; + struct mmc_card *card; int locked = 0; + if (!md) + return -EINVAL; + + card = md->queue.card; if (card->ext_csd.boot_ro_lock & EXT_CSD_BOOT_WP_B_PERM_WP_EN) locked = 2; else if (card->ext_csd.boot_ro_lock & EXT_CSD_BOOT_WP_B_PWR_WP_EN) @@ -230,6 +257,8 @@ return count; md = mmc_blk_get(dev_to_disk(dev)); + if (!md) + return -EINVAL; card = md->queue.card; mmc_get_card(card); @@ -267,6 +296,9 @@ int ret; struct mmc_blk_data *md = mmc_blk_get(dev_to_disk(dev)); + if (!md) + return -EINVAL; + ret = snprintf(buf, PAGE_SIZE, "%d\n", get_disk_ro(dev_to_disk(dev)) ^ md->read_only); @@ -281,6 +313,10 @@ char *end; struct mmc_blk_data *md = mmc_blk_get(dev_to_disk(dev)); unsigned long set = simple_strtoul(buf, &end, 0); + + if (!md) + return -EINVAL; + if (end == buf) { ret = -EINVAL; goto out; @@ -293,6 +329,362 @@ return ret; } +#ifdef CONFIG_MMC_SIMULATE_MAX_SPEED + +static int max_read_speed, max_write_speed, cache_size = 4; + +module_param(max_read_speed, int, S_IRUSR | S_IRGRP); +MODULE_PARM_DESC(max_read_speed, "maximum KB/s read speed 0=off"); +module_param(max_write_speed, int, S_IRUSR | S_IRGRP); +MODULE_PARM_DESC(max_write_speed, "maximum KB/s write speed 0=off"); +module_param(cache_size, int, S_IRUSR | S_IRGRP); +MODULE_PARM_DESC(cache_size, "MB high speed memory or SLC cache"); + +/* + * helper macros and expectations: + * size - unsigned long number of bytes + * jiffies - unsigned long HZ timestamp difference + * speed - unsigned KB/s transfer rate + */ +#define size_and_speed_to_jiffies(size, speed) \ + ((size) * HZ / (speed) / 1024UL) +#define jiffies_and_speed_to_size(jiffies, speed) \ + (((speed) * (jiffies) * 1024UL) / HZ) +#define jiffies_and_size_to_speed(jiffies, size) \ + ((size) * HZ / (jiffies) / 1024UL) + +/* Limits to report warning */ +/* jiffies_and_size_to_speed(10*HZ, queue_max_hw_sectors(q) * 512UL) ~ 25 */ +#define MIN_SPEED(q) 250 /* 10 times faster than a floppy disk */ +#define MAX_SPEED(q) jiffies_and_size_to_speed(1, queue_max_sectors(q) * 512UL) + +#define speed_valid(speed) ((speed) > 0) + +static const char off[] = "off\n"; + +static int max_speed_show(int speed, char *buf) +{ + if (speed) + return scnprintf(buf, PAGE_SIZE, "%uKB/s\n", speed); + else + return scnprintf(buf, PAGE_SIZE, off); +} + +static int max_speed_store(const char *buf, struct request_queue *q) +{ + unsigned int limit, set = 0; + + if (!strncasecmp(off, buf, sizeof(off) - 2)) + return set; + if (kstrtouint(buf, 0, &set) || (set > INT_MAX)) + return -EINVAL; + if (set == 0) + return set; + limit = MAX_SPEED(q); + if (set > limit) + pr_warn("max speed %u ineffective above %u\n", set, limit); + limit = MIN_SPEED(q); + if (set < limit) + pr_warn("max speed %u painful below %u\n", set, limit); + return set; +} + +static ssize_t max_write_speed_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct mmc_blk_data *md = mmc_blk_get(dev_to_disk(dev)); + int ret = max_speed_show(atomic_read(&md->queue.max_write_speed), buf); + + mmc_blk_put(md); + return ret; +} + +static ssize_t max_write_speed_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + struct mmc_blk_data *md = mmc_blk_get(dev_to_disk(dev)); + int set = max_speed_store(buf, md->queue.queue); + + if (set < 0) { + mmc_blk_put(md); + return set; + } + + atomic_set(&md->queue.max_write_speed, set); + mmc_blk_put(md); + return count; +} + +static const DEVICE_ATTR(max_write_speed, S_IRUGO | S_IWUSR, + max_write_speed_show, max_write_speed_store); + +static ssize_t max_read_speed_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct mmc_blk_data *md = mmc_blk_get(dev_to_disk(dev)); + int ret = max_speed_show(atomic_read(&md->queue.max_read_speed), buf); + + mmc_blk_put(md); + return ret; +} + +static ssize_t max_read_speed_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + struct mmc_blk_data *md = mmc_blk_get(dev_to_disk(dev)); + int set = max_speed_store(buf, md->queue.queue); + + if (set < 0) { + mmc_blk_put(md); + return set; + } + + atomic_set(&md->queue.max_read_speed, set); + mmc_blk_put(md); + return count; +} + +static const DEVICE_ATTR(max_read_speed, S_IRUGO | S_IWUSR, + max_read_speed_show, max_read_speed_store); + +static ssize_t cache_size_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct mmc_blk_data *md = mmc_blk_get(dev_to_disk(dev)); + struct mmc_queue *mq = &md->queue; + int cache_size = atomic_read(&mq->cache_size); + int ret; + + if (!cache_size) + ret = scnprintf(buf, PAGE_SIZE, off); + else { + int speed = atomic_read(&mq->max_write_speed); + + if (!speed_valid(speed)) + ret = scnprintf(buf, PAGE_SIZE, "%uMB\n", cache_size); + else { /* We accept race between cache_jiffies and cache_used */ + unsigned long size = jiffies_and_speed_to_size( + jiffies - mq->cache_jiffies, speed); + long used = atomic_long_read(&mq->cache_used); + + if (size >= used) + size = 0; + else + size = (used - size) * 100 / cache_size + / 1024UL / 1024UL; + + ret = scnprintf(buf, PAGE_SIZE, "%uMB %lu%% used\n", + cache_size, size); + } + } + + mmc_blk_put(md); + return ret; +} + +static ssize_t cache_size_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + struct mmc_blk_data *md; + unsigned int set = 0; + + if (strncasecmp(off, buf, sizeof(off) - 2) + && (kstrtouint(buf, 0, &set) || (set > INT_MAX))) + return -EINVAL; + + md = mmc_blk_get(dev_to_disk(dev)); + atomic_set(&md->queue.cache_size, set); + mmc_blk_put(md); + return count; +} + +static const DEVICE_ATTR(cache_size, S_IRUGO | S_IWUSR, + cache_size_show, cache_size_store); + +/* correct for write-back */ +static long mmc_blk_cache_used(struct mmc_queue *mq, unsigned long waitfor) +{ + long used = 0; + int speed = atomic_read(&mq->max_write_speed); + + if (speed_valid(speed)) { + unsigned long size = jiffies_and_speed_to_size( + waitfor - mq->cache_jiffies, speed); + used = atomic_long_read(&mq->cache_used); + + if (size >= used) + used = 0; + else + used -= size; + } + + atomic_long_set(&mq->cache_used, used); + mq->cache_jiffies = waitfor; + + return used; +} + +static void mmc_blk_simulate_delay( + struct mmc_queue *mq, + struct request *req, + unsigned long waitfor) +{ + int max_speed; + + if (!req) + return; + + max_speed = (rq_data_dir(req) == READ) + ? atomic_read(&mq->max_read_speed) + : atomic_read(&mq->max_write_speed); + if (speed_valid(max_speed)) { + unsigned long bytes = blk_rq_bytes(req); + + if (rq_data_dir(req) != READ) { + int cache_size = atomic_read(&mq->cache_size); + + if (cache_size) { + unsigned long size = cache_size * 1024L * 1024L; + long used = mmc_blk_cache_used(mq, waitfor); + + used += bytes; + atomic_long_set(&mq->cache_used, used); + bytes = 0; + if (used > size) + bytes = used - size; + } + } + waitfor += size_and_speed_to_jiffies(bytes, max_speed); + if (time_is_after_jiffies(waitfor)) { + long msecs = jiffies_to_msecs(waitfor - jiffies); + + if (likely(msecs > 0)) + msleep(msecs); + } + } +} + +#else + +#define mmc_blk_simulate_delay(mq, req, waitfor) + +#endif +static ssize_t +num_wr_reqs_to_start_packing_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct mmc_blk_data *md = mmc_blk_get(dev_to_disk(dev)); + int num_wr_reqs_to_start_packing; + int ret; + + if (!md) + return -EINVAL; + num_wr_reqs_to_start_packing = md->queue.num_wr_reqs_to_start_packing; + + ret = snprintf(buf, PAGE_SIZE, "%d\n", num_wr_reqs_to_start_packing); + + mmc_blk_put(md); + return ret; +} + +static ssize_t +num_wr_reqs_to_start_packing_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + int value; + struct mmc_blk_data *md = mmc_blk_get(dev_to_disk(dev)); + struct mmc_card *card; + int ret = count; + + if (!md) + return -EINVAL; + + card = md->queue.card; + if (!card) { + ret = -EINVAL; + goto exit; + } + + sscanf(buf, "%d", &value); + + if (value >= 0) { + md->queue.num_wr_reqs_to_start_packing = + min_t(int, value, (int)card->ext_csd.max_packed_writes); + + pr_debug("%s: trigger to pack: new value = %d", + mmc_hostname(card->host), + md->queue.num_wr_reqs_to_start_packing); + } else { + pr_err("%s: value %d is not valid. old value remains = %d", + mmc_hostname(card->host), value, + md->queue.num_wr_reqs_to_start_packing); + ret = -EINVAL; + } + +exit: + mmc_blk_put(md); + return ret; +} + +static ssize_t +no_pack_for_random_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct mmc_blk_data *md = mmc_blk_get(dev_to_disk(dev)); + int ret; + + if (!md) + return -EINVAL; + ret = snprintf(buf, PAGE_SIZE, "%d\n", md->queue.no_pack_for_random); + + mmc_blk_put(md); + return ret; +} + +static ssize_t +no_pack_for_random_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + int value; + struct mmc_blk_data *md = mmc_blk_get(dev_to_disk(dev)); + struct mmc_card *card; + int ret = count; + + if (!md) + return -EINVAL; + + card = md->queue.card; + if (!card) { + ret = -EINVAL; + goto exit; + } + + sscanf(buf, "%d", &value); + + if (value < 0) { + pr_err("%s: value %d is not valid. old value remains = %d", + mmc_hostname(card->host), value, + md->queue.no_pack_for_random); + ret = -EINVAL; + goto exit; + } + + md->queue.no_pack_for_random = (value > 0) ? true : false; + + pr_debug("%s: no_pack_for_random: new value = %d", + mmc_hostname(card->host), + md->queue.no_pack_for_random); + +exit: + mmc_blk_put(md); + return ret; +} + static int mmc_blk_open(struct block_device *bdev, fmode_t mode) { struct mmc_blk_data *md = mmc_blk_get(bdev->bd_disk); @@ -440,7 +832,8 @@ { int err; - if (!mmc_can_sanitize(card)) { + if (!mmc_can_sanitize(card) && + (card->host->caps2 & MMC_CAP2_SANITIZE)) { pr_warn("%s: %s - SANITIZE is not supported\n", mmc_hostname(card->host), __func__); err = -EOPNOTSUPP; @@ -450,9 +843,11 @@ pr_debug("%s: %s - SANITIZE IN PROGRESS...\n", mmc_hostname(card->host), __func__); + trace_mmc_blk_erase_start(EXT_CSD_SANITIZE_START, 0, 0); err = mmc_switch(card, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_SANITIZE_START, 1, MMC_SANITIZE_REQ_TIMEOUT); + trace_mmc_blk_erase_end(EXT_CSD_SANITIZE_START, 0, 0); if (err) pr_err("%s: %s - EXT_CSD_SANITIZE_START failed. err=%d\n", @@ -472,19 +867,22 @@ struct mmc_request mrq = {NULL}; struct scatterlist sg; int err; - int is_rpmb = false; - u32 status = 0; if (!card || !md || !idata) return -EINVAL; - if (md->area_type & MMC_BLK_DATA_AREA_RPMB) - is_rpmb = true; - cmd.opcode = idata->ic.opcode; cmd.arg = idata->ic.arg; cmd.flags = idata->ic.flags; + if (idata->ic.postsleep_max_us < idata->ic.postsleep_min_us) { + pr_err("%s: min value: %u must not be greater than max value: %u\n", + __func__, idata->ic.postsleep_min_us, + idata->ic.postsleep_max_us); + WARN_ON(1); + return -EPERM; + } + if (idata->buf_bytes) { data.sg = &sg; data.sg_len = 1; @@ -523,6 +921,15 @@ mrq.cmd = &cmd; + if (mmc_card_doing_bkops(card)) { + err = mmc_stop_bkops(card); + if (err) { + dev_err(mmc_dev(card->host), + "%s: stop_bkops failed %d\n", __func__, err); + return err; + } + } + err = mmc_blk_part_switch(card, md); if (err) return err; @@ -533,13 +940,6 @@ return err; } - if (is_rpmb) { - err = mmc_set_blockcount(card, data.blocks, - idata->ic.write_flag & (1 << 31)); - if (err) - return err; - } - if ((MMC_EXTRACT_INDEX_FROM_ARG(cmd.arg) == EXT_CSD_SANITIZE_START) && (cmd.opcode == MMC_SWITCH)) { err = ioctl_do_sanitize(card); @@ -573,7 +973,183 @@ memcpy(&(idata->ic.response), cmd.resp, sizeof(cmd.resp)); - if (is_rpmb) { + return err; +} + +struct mmc_blk_ioc_rpmb_data { + struct mmc_blk_ioc_data *data[MMC_IOC_MAX_RPMB_CMD]; +}; + +static struct mmc_blk_ioc_rpmb_data *mmc_blk_ioctl_rpmb_copy_from_user( + struct mmc_ioc_rpmb __user *user) +{ + struct mmc_blk_ioc_rpmb_data *idata; + int err, i; + + idata = kzalloc(sizeof(*idata), GFP_KERNEL); + if (!idata) { + err = -ENOMEM; + goto out; + } + + for (i = 0; i < MMC_IOC_MAX_RPMB_CMD; i++) { + idata->data[i] = mmc_blk_ioctl_copy_from_user(&(user->cmds[i])); + if (IS_ERR(idata->data[i])) { + err = PTR_ERR(idata->data[i]); + goto copy_err; + } + } + + return idata; + +copy_err: + while (--i >= 0) { + kfree(idata->data[i]->buf); + kfree(idata->data[i]); + } + kfree(idata); +out: + return ERR_PTR(err); +} + +static int mmc_blk_ioctl_rpmb_cmd(struct block_device *bdev, + struct mmc_ioc_rpmb __user *ic_ptr) +{ + struct mmc_blk_ioc_rpmb_data *idata; + struct mmc_blk_data *md; + struct mmc_card *card = NULL; + struct mmc_command cmd = {0}; + struct mmc_data data = {0}; + struct mmc_request mrq = {NULL}; + struct scatterlist sg; + int err = 0, i = 0; + u32 status = 0; + + /* The caller must have CAP_SYS_RAWIO */ + if (!capable(CAP_SYS_RAWIO)) + return -EPERM; + + md = mmc_blk_get(bdev->bd_disk); + /* make sure this is a rpmb partition */ + if ((!md) || (!(md->area_type & MMC_BLK_DATA_AREA_RPMB))) { + err = -EINVAL; + return err; + } + + idata = mmc_blk_ioctl_rpmb_copy_from_user(ic_ptr); + if (IS_ERR(idata)) { + err = PTR_ERR(idata); + goto cmd_done; + } + + card = md->queue.card; + if (IS_ERR(card)) { + err = PTR_ERR(card); + goto idata_free; + } + + mmc_get_card(card); + + if (mmc_card_doing_bkops(card)) { + if (mmc_card_cmdq(card)) { + err = mmc_cmdq_halt(card->host, true); + if (err) + goto cmd_rel_host; + } + err = mmc_stop_bkops(card); + if (err) { + dev_err(mmc_dev(card->host), + "%s: stop_bkops failed %d\n", __func__, err); + goto cmd_rel_host; + } + if (mmc_card_cmdq(card)) { + err = mmc_cmdq_halt(card->host, false); + if (err) + goto cmd_rel_host; + } + } + + err = mmc_blk_part_switch(card, md); + if (err) + goto cmd_rel_host; + + for (i = 0; i < MMC_IOC_MAX_RPMB_CMD; i++) { + struct mmc_blk_ioc_data *curr_data; + struct mmc_ioc_cmd *curr_cmd; + + curr_data = idata->data[i]; + curr_cmd = &curr_data->ic; + if (!curr_cmd->opcode) + break; + + cmd.opcode = curr_cmd->opcode; + cmd.arg = curr_cmd->arg; + cmd.flags = curr_cmd->flags; + + if (curr_data->buf_bytes) { + data.sg = &sg; + data.sg_len = 1; + data.blksz = curr_cmd->blksz; + data.blocks = curr_cmd->blocks; + + sg_init_one(data.sg, curr_data->buf, + curr_data->buf_bytes); + + if (curr_cmd->write_flag) + data.flags = MMC_DATA_WRITE; + else + data.flags = MMC_DATA_READ; + + /* data.flags must already be set before doing this. */ + mmc_set_data_timeout(&data, card); + + /* + * Allow overriding the timeout_ns for empirical tuning. + */ + if (curr_cmd->data_timeout_ns) + data.timeout_ns = curr_cmd->data_timeout_ns; + + mrq.data = &data; + } + + mrq.cmd = &cmd; + + err = mmc_set_blockcount(card, data.blocks, + curr_cmd->write_flag & (1 << 31)); + if (err) + goto cmd_rel_host; + + mmc_wait_for_req(card->host, &mrq); + + if (cmd.error) { + dev_err(mmc_dev(card->host), "%s: cmd error %d\n", + __func__, cmd.error); + err = cmd.error; + goto cmd_rel_host; + } + if (data.error) { + dev_err(mmc_dev(card->host), "%s: data error %d\n", + __func__, data.error); + err = data.error; + goto cmd_rel_host; + } + + if (copy_to_user(&(ic_ptr->cmds[i].response), cmd.resp, + sizeof(cmd.resp))) { + err = -EFAULT; + goto cmd_rel_host; + } + + if (!curr_cmd->write_flag) { + if (copy_to_user((void __user *)(unsigned long) + curr_cmd->data_ptr, + curr_data->buf, + curr_data->buf_bytes)) { + err = -EFAULT; + goto cmd_rel_host; + } + } + /* * Ensure RPMB command has completed by polling CMD13 * "Send Status". @@ -585,6 +1161,20 @@ __func__, status, err); } +cmd_rel_host: + mmc_put_card(card); + +idata_free: + for (i = 0; i < MMC_IOC_MAX_RPMB_CMD; i++) { + kfree(idata->data[i]->buf); + kfree(idata->data[i]); + } + kfree(idata); + +cmd_done: + mmc_blk_put(md); + if (card && card->cmdq_init) + wake_up(&card->host->cmdq_ctx.wait); return err; } @@ -605,9 +1195,8 @@ return -EPERM; idata = mmc_blk_ioctl_copy_from_user(ic_ptr); - if (IS_ERR(idata)) + if (IS_ERR_OR_NULL(idata)) return PTR_ERR(idata); - md = mmc_blk_get(bdev->bd_disk); if (!md) { err = -EINVAL; @@ -615,15 +1204,32 @@ } card = md->queue.card; - if (IS_ERR(card)) { + if (IS_ERR_OR_NULL(card)) { err = PTR_ERR(card); goto cmd_done; } mmc_get_card(card); + if (mmc_card_cmdq(card)) { + err = mmc_cmdq_halt_on_empty_queue(card->host); + if (err) { + pr_err("%s: halt failed while doing %s err (%d)\n", + mmc_hostname(card->host), + __func__, err); + mmc_put_card(card); + goto cmd_done; + } + } + ioc_err = __mmc_blk_ioctl_cmd(card, md, idata); + if (mmc_card_cmdq(card)) { + if (mmc_cmdq_halt(card->host, false)) + pr_err("%s: %s: cmdq unhalt failed\n", + mmc_hostname(card->host), __func__); + } + mmc_put_card(card); err = mmc_blk_ioctl_copy_to_user(ic_ptr, idata); @@ -713,6 +1319,9 @@ case MMC_IOC_CMD: return mmc_blk_ioctl_cmd(bdev, (struct mmc_ioc_cmd __user *)arg); + case MMC_IOC_RPMB_CMD: + return mmc_blk_ioctl_rpmb_cmd(bdev, + (struct mmc_ioc_rpmb __user *)arg); case MMC_IOC_MULTI_CMD: return mmc_blk_ioctl_multi_cmd(bdev, (struct mmc_ioc_multi_cmd __user *)arg); @@ -740,28 +1349,92 @@ #endif }; +static int mmc_blk_cmdq_switch(struct mmc_card *card, + struct mmc_blk_data *md, bool enable) +{ + int ret = 0; + bool cmdq_mode = !!mmc_card_cmdq(card); + struct mmc_host *host = card->host; + struct mmc_cmdq_context_info *ctx = &host->cmdq_ctx; + + if (!(card->host->caps2 & MMC_CAP2_CMD_QUEUE) || + !card->ext_csd.cmdq_support || + (enable && !(md->flags & MMC_BLK_CMD_QUEUE)) || + (cmdq_mode == enable)) + return 0; + + if (enable) { + ret = mmc_set_blocklen(card, MMC_CARD_CMDQ_BLK_SIZE); + if (ret) { + pr_err("%s: failed (%d) to set block-size to %d\n", + __func__, ret, MMC_CARD_CMDQ_BLK_SIZE); + goto out; + } + + } else { + if (!test_bit(CMDQ_STATE_HALT, &ctx->curr_state)) { + ret = mmc_cmdq_halt(host, true); + if (ret) { + pr_err("%s: halt: failed: %d\n", + mmc_hostname(host), ret); + goto out; + } + } + } + + ret = mmc_switch(card, EXT_CSD_CMD_SET_NORMAL, + EXT_CSD_CMDQ, enable, + card->ext_csd.generic_cmd6_time); + if (ret) { + pr_err("%s: cmdq mode %sable failed %d\n", + md->disk->disk_name, enable ? "en" : "dis", ret); + goto out; + } + + if (enable) + mmc_card_set_cmdq(card); + else + mmc_card_clr_cmdq(card); +out: + return ret; +} + static inline int mmc_blk_part_switch(struct mmc_card *card, struct mmc_blk_data *md) { int ret; struct mmc_blk_data *main_md = dev_get_drvdata(&card->dev); - if (main_md->part_curr == md->part_type) + if ((main_md->part_curr == md->part_type) && + (card->part_curr == md->part_type)) return 0; if (mmc_card_mmc(card)) { u8 part_config = card->ext_csd.part_config; + if (md->part_type) { + /* disable CQ mode for non-user data partitions */ + ret = mmc_blk_cmdq_switch(card, md, false); + if (ret) + return ret; + } + part_config &= ~EXT_CSD_PART_CONFIG_ACC_MASK; part_config |= md->part_type; ret = mmc_switch(card, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_PART_CONFIG, part_config, card->ext_csd.part_time); - if (ret) + + if (ret) { + pr_err("%s: mmc_blk_part_switch failure, %d -> %d\n", + mmc_hostname(card->host), main_md->part_curr, + md->part_type); return ret; + } card->ext_csd.part_config = part_config; + card->part_curr = md->part_type; } main_md->part_curr = md->part_type; @@ -942,33 +1615,45 @@ switch (error) { case -EILSEQ: /* response crc error, retry the r/w cmd */ - pr_err("%s: %s sending %s command, card status %#x\n", - req->rq_disk->disk_name, "response CRC error", + pr_err_ratelimited( + "%s: response CRC error sending %s command, card status %#x\n", + req->rq_disk->disk_name, name, status); return ERR_RETRY; case -ETIMEDOUT: - pr_err("%s: %s sending %s command, card status %#x\n", - req->rq_disk->disk_name, "timed out", name, status); + pr_err_ratelimited( + "%s: timed out sending %s command, card status %#x\n", + req->rq_disk->disk_name, name, status); /* If the status cmd initially failed, retry the r/w cmd */ - if (!status_valid) + if (!status_valid) { + pr_err_ratelimited("%s: status not valid, retrying timeout\n", + req->rq_disk->disk_name); return ERR_RETRY; - + } /* * If it was a r/w cmd crc error, or illegal command * (eg, issued in wrong state) then retry - we should * have corrected the state problem above. */ - if (status & (R1_COM_CRC_ERROR | R1_ILLEGAL_COMMAND)) + if (status & (R1_COM_CRC_ERROR | R1_ILLEGAL_COMMAND)) { + pr_err_ratelimited( + "%s: command error, retrying timeout\n", + req->rq_disk->disk_name); return ERR_RETRY; + } /* Otherwise abort the command */ + pr_err_ratelimited( + "%s: not retrying timeout\n", + req->rq_disk->disk_name); return ERR_ABORT; default: /* We don't understand the error code the driver gave us */ - pr_err("%s: unknown error %d sending read/write command, card status %#x\n", + pr_err_ratelimited( + "%s: unknown error %d sending read/write command, card status %#x\n", req->rq_disk->disk_name, error, status); return ERR_ABORT; } @@ -1016,12 +1701,14 @@ mmc_retune_recheck(card->host); prev_cmd_status_valid = false; - pr_err("%s: error %d sending status command, %sing\n", + pr_err_ratelimited("%s: error %d sending status command, %sing\n", req->rq_disk->disk_name, err, retry ? "retry" : "abort"); } /* We couldn't get a response from the card. Give up. */ if (err) { + if (card->err_in_sdr104) + return ERR_RETRY; /* Check if the card is removed */ if (mmc_detect_card_removed(card->host)) return ERR_NOMEDIUM; @@ -1107,8 +1794,15 @@ md->reset_done |= type; err = mmc_hw_reset(host); + if (err && err != -EOPNOTSUPP) { + /* We failed to reset so we need to abort the request */ + pr_err("%s: %s: failed to reset %d\n", mmc_hostname(host), + __func__, err); + return -ENODEV; + } + /* Ensure we switch back to the correct partition */ - if (err != -EOPNOTSUPP) { + if (host->card) { struct mmc_blk_data *main_md = dev_get_drvdata(&host->card->dev); int part_err; @@ -1143,6 +1837,77 @@ return false; } +static struct mmc_cmdq_req *mmc_blk_cmdq_prep_discard_req(struct mmc_queue *mq, + struct request *req) +{ + struct mmc_blk_data *md = mq->data; + struct mmc_card *card = md->queue.card; + struct mmc_host *host = card->host; + struct mmc_cmdq_context_info *ctx_info = &host->cmdq_ctx; + struct mmc_cmdq_req *cmdq_req; + struct mmc_queue_req *active_mqrq; + + BUG_ON(req->tag > card->ext_csd.cmdq_depth); + BUG_ON(test_and_set_bit(req->tag, &host->cmdq_ctx.active_reqs)); + + set_bit(CMDQ_STATE_DCMD_ACTIVE, &ctx_info->curr_state); + + active_mqrq = &mq->mqrq_cmdq[req->tag]; + active_mqrq->req = req; + + cmdq_req = mmc_cmdq_prep_dcmd(active_mqrq, mq); + cmdq_req->cmdq_req_flags |= QBR; + cmdq_req->mrq.cmd = &cmdq_req->cmd; + cmdq_req->tag = req->tag; + return cmdq_req; +} + +static int mmc_blk_cmdq_issue_discard_rq(struct mmc_queue *mq, + struct request *req) +{ + struct mmc_blk_data *md = mq->data; + struct mmc_card *card = md->queue.card; + struct mmc_cmdq_req *cmdq_req = NULL; + unsigned int from, nr, arg; + int err = 0; + + if (!mmc_can_erase(card)) { + err = -EOPNOTSUPP; + blk_end_request(req, err, blk_rq_bytes(req)); + goto out; + } + + from = blk_rq_pos(req); + nr = blk_rq_sectors(req); + + if (mmc_can_discard(card)) + arg = MMC_DISCARD_ARG; + else if (mmc_can_trim(card)) + arg = MMC_TRIM_ARG; + else + arg = MMC_ERASE_ARG; + + cmdq_req = mmc_blk_cmdq_prep_discard_req(mq, req); + if (card->quirks & MMC_QUIRK_INAND_CMD38) { + __mmc_switch_cmdq_mode(cmdq_req->mrq.cmd, + EXT_CSD_CMD_SET_NORMAL, + INAND_CMD38_ARG_EXT_CSD, + arg == MMC_TRIM_ARG ? + INAND_CMD38_ARG_TRIM : + INAND_CMD38_ARG_ERASE, + 0, true, false); + err = mmc_cmdq_wait_for_dcmd(card->host, cmdq_req); + if (err) + goto clear_dcmd; + } + err = mmc_cmdq_erase(cmdq_req, card, from, nr, arg); +clear_dcmd: + mmc_host_clk_hold(card->host); + blk_complete_request(req); +out: + return err ? 1 : 0; +} + static int mmc_blk_issue_discard_rq(struct mmc_queue *mq, struct request *req) { struct mmc_blk_data *md = mq->data; @@ -1186,6 +1951,69 @@ return err ? 0 : 1; } +static int mmc_blk_cmdq_issue_secdiscard_rq(struct mmc_queue *mq, + struct request *req) +{ + struct mmc_blk_data *md = mq->data; + struct mmc_card *card = md->queue.card; + struct mmc_cmdq_req *cmdq_req = NULL; + unsigned int from, nr, arg; + int err = 0; + + if (!(mmc_can_secure_erase_trim(card))) { + err = -EOPNOTSUPP; + blk_end_request(req, err, blk_rq_bytes(req)); + goto out; + } + + from = blk_rq_pos(req); + nr = blk_rq_sectors(req); + + if (mmc_can_trim(card) && !mmc_erase_group_aligned(card, from, nr)) + arg = MMC_SECURE_TRIM1_ARG; + else + arg = MMC_SECURE_ERASE_ARG; + + cmdq_req = mmc_blk_cmdq_prep_discard_req(mq, req); + if (card->quirks & MMC_QUIRK_INAND_CMD38) { + __mmc_switch_cmdq_mode(cmdq_req->mrq.cmd, + EXT_CSD_CMD_SET_NORMAL, + INAND_CMD38_ARG_EXT_CSD, + arg == MMC_SECURE_TRIM1_ARG ? + INAND_CMD38_ARG_SECTRIM1 : + INAND_CMD38_ARG_SECERASE, + 0, true, false); + err = mmc_cmdq_wait_for_dcmd(card->host, cmdq_req); + if (err) + goto clear_dcmd; + } + + err = mmc_cmdq_erase(cmdq_req, card, from, nr, arg); + if (err) + goto clear_dcmd; + + if (arg == MMC_SECURE_TRIM1_ARG) { + if (card->quirks & MMC_QUIRK_INAND_CMD38) { + __mmc_switch_cmdq_mode(cmdq_req->mrq.cmd, + EXT_CSD_CMD_SET_NORMAL, + INAND_CMD38_ARG_EXT_CSD, + INAND_CMD38_ARG_SECTRIM2, + 0, true, false); + err = mmc_cmdq_wait_for_dcmd(card->host, cmdq_req); + if (err) + goto clear_dcmd; + } + + err = mmc_cmdq_erase(cmdq_req, card, from, nr, + MMC_SECURE_TRIM2_ARG); + } +clear_dcmd: + mmc_host_clk_hold(card->host); + blk_complete_request(req); +out: + return err ? 1 : 0; +} + static int mmc_blk_issue_secdiscard_rq(struct mmc_queue *mq, struct request *req) { @@ -1259,10 +2087,64 @@ struct mmc_card *card = md->queue.card; int ret = 0; - ret = mmc_flush_cache(card); + if (!req) + return 0; + + if (req->cmd_flags & REQ_BARRIER) { + /* + * If eMMC cache flush policy is set to 1, then the device + * shall flush the requests in First-In-First-Out (FIFO) order. + * In this case, as per spec, the host must not send any cache + * barrier requests as they are redundant and add unnecessary + * overhead to both device and host. + */ + if (card->ext_csd.cache_flush_policy & 1) + goto end_req; + + /* + * In case barrier is not supported or enabled in the device, + * use flush as a fallback option. + */ + ret = mmc_cache_barrier(card); if (ret) + ret = mmc_flush_cache(card); + } else if (req->cmd_flags & REQ_FLUSH) { + ret = mmc_flush_cache(card); + } + if (ret == -ENODEV) { + pr_err("%s: %s: restart mmc card", + req->rq_disk->disk_name, __func__); + if (mmc_blk_reset(md, card->host, MMC_BLK_FLUSH)) + pr_err("%s: %s: fail to restart mmc", + req->rq_disk->disk_name, __func__); + else + mmc_blk_reset_success(md, MMC_BLK_FLUSH); + } + + if (ret) { + pr_err("%s: %s: notify flush error to upper layers", + req->rq_disk->disk_name, __func__); ret = -EIO; + } +end_req: +#ifdef CONFIG_MMC_SIMULATE_MAX_SPEED + else if (atomic_read(&mq->cache_size)) { + long used = mmc_blk_cache_used(mq, jiffies); + + if (used) { + int speed = atomic_read(&mq->max_write_speed); + + if (speed_valid(speed)) { + unsigned long msecs = jiffies_to_msecs( + size_and_speed_to_jiffies( + used, speed)); + if (msecs) + msleep(msecs); + } + } + } +#endif blk_end_request_all(req, ret); return ret ? 0 : 1; @@ -1309,6 +2191,18 @@ int need_retune = card->host->need_retune; int ecc_err = 0, gen_err = 0; + if (card->host->sdr104_wa && mmc_card_sd(card) && + (card->host->ios.timing == MMC_TIMING_UHS_SDR104) && + !card->sdr104_blocked && + (brq->data.error == -EILSEQ || + brq->data.error == -EIO || + brq->data.error == -ETIMEDOUT || + brq->cmd.error == -EILSEQ || + brq->cmd.error == -EIO || + brq->cmd.error == -ETIMEDOUT || + brq->sbc.error)) + card->err_in_sdr104 = true; + /* * sbc.error indicates a problem with the set block count * command. No data will have been transferred. @@ -1493,6 +2387,7 @@ brq->stop.arg = 0; brq->data.blocks = blk_rq_sectors(req); + brq->data.fault_injected = false; /* * The block layer doesn't support all sector count * restrictions, so we need to be prepared for too big @@ -1616,6 +2511,7 @@ } mqrq->mmc_active.mrq = &brq->mrq; + mqrq->mmc_active.mrq->req = mqrq->req; mqrq->mmc_active.err_check = mmc_blk_err_check; mmc_queue_bounce_pre(mqrq); @@ -1637,6 +2533,178 @@ return nr_segs; } +/** + * mmc_blk_disable_wr_packing() - disables packing mode + * @mq: MMC queue. + * + */ +void mmc_blk_disable_wr_packing(struct mmc_queue *mq) +{ + if (mq) { + mq->wr_packing_enabled = false; + mq->num_of_potential_packed_wr_reqs = 0; + } +} +EXPORT_SYMBOL(mmc_blk_disable_wr_packing); + +static int get_packed_trigger(int potential, struct mmc_card *card, + struct request *req, int curr_trigger) +{ + static int num_mean_elements = 1; + static unsigned long mean_potential = PCKD_TRGR_INIT_MEAN_POTEN; + unsigned int trigger = curr_trigger; + unsigned int pckd_trgr_upper_bound = card->ext_csd.max_packed_writes; + + /* scale down the upper bound to 75% */ + pckd_trgr_upper_bound = (pckd_trgr_upper_bound * 3) / 4; + + /* + * since the most common calls for this function are with small + * potential write values and since we don't want these calls to affect + * the packed trigger, set a lower bound and ignore calls with + * potential lower than that bound + */ + if (potential <= PCKD_TRGR_POTEN_LOWER_BOUND) + return trigger; + + /* + * this is to prevent integer overflow in the following calculation: + * once every PACKED_TRIGGER_MAX_ELEMENTS reset the algorithm + */ + if (num_mean_elements > PACKED_TRIGGER_MAX_ELEMENTS) { + num_mean_elements = 1; + mean_potential = PCKD_TRGR_INIT_MEAN_POTEN; + } + + /* + * get next mean value based on previous mean value and current + * potential packed writes. Calculation is as follows: + * mean_pot[i+1] = + * ((mean_pot[i] * num_mean_elem) + potential)/(num_mean_elem + 1) + */ + mean_potential *= num_mean_elements; + /* + * add num_mean_elements so that the division of two integers doesn't + * lower mean_potential too much + */ + if (potential > mean_potential) + mean_potential += num_mean_elements; + mean_potential += potential; + /* this is for gaining more precision when dividing two integers */ + mean_potential *= PCKD_TRGR_PRECISION_MULTIPLIER; + /* this completes the mean calculation */ + mean_potential /= ++num_mean_elements; + mean_potential /= PCKD_TRGR_PRECISION_MULTIPLIER; + + /* + * if current potential packed writes is greater than the mean potential + * then the heuristic is that the following workload will contain many + * write requests, therefore we lower the packed trigger. In the + * opposite case we want to increase the trigger in order to get less + * packing events. + */ + if (potential >= mean_potential) + trigger = (trigger <= PCKD_TRGR_LOWER_BOUND) ? + PCKD_TRGR_LOWER_BOUND : trigger - 1; + else + trigger = (trigger >= pckd_trgr_upper_bound) ? + pckd_trgr_upper_bound : trigger + 1; + + /* + * an urgent read request indicates a packed list being interrupted + * by this read, therefore we aim for less packing, hence the trigger + * gets increased + */ + if (req && (req->cmd_flags & REQ_URGENT) && (rq_data_dir(req) == READ)) + trigger += PCKD_TRGR_URGENT_PENALTY; + + return trigger; +} + +static void mmc_blk_write_packing_control(struct mmc_queue *mq, + struct request *req) +{ + struct mmc_host *host = mq->card->host; + int data_dir; + + if (!(host->caps2 & MMC_CAP2_PACKED_WR)) + return; + + /* Support for the write packing on eMMC 4.5 or later */ + if (mq->card->ext_csd.rev <= 5) + return; + + /* + * In case the packing control is not supported by the host, it should + * not have an effect on the write packing. Therefore we have to enable + * the write packing + */ + if (!(host->caps2 & MMC_CAP2_PACKED_WR_CONTROL)) { + mq->wr_packing_enabled = true; + return; + } + + if (!req || (req && (req->cmd_flags & REQ_FLUSH))) { + if (mq->num_of_potential_packed_wr_reqs > + mq->num_wr_reqs_to_start_packing) + mq->wr_packing_enabled = true; + mq->num_wr_reqs_to_start_packing = + get_packed_trigger(mq->num_of_potential_packed_wr_reqs, + mq->card, req, + mq->num_wr_reqs_to_start_packing); + mq->num_of_potential_packed_wr_reqs = 0; + return; + } + + data_dir = rq_data_dir(req); + + if (data_dir == READ) { + mmc_blk_disable_wr_packing(mq); + mq->num_wr_reqs_to_start_packing = + get_packed_trigger(mq->num_of_potential_packed_wr_reqs, + mq->card, req, + mq->num_wr_reqs_to_start_packing); + mq->num_of_potential_packed_wr_reqs = 0; + mq->wr_packing_enabled = false; + return; + } else if (data_dir == WRITE) { + mq->num_of_potential_packed_wr_reqs++; + } + + if (mq->num_of_potential_packed_wr_reqs > + mq->num_wr_reqs_to_start_packing) + mq->wr_packing_enabled = true; +} + +struct mmc_wr_pack_stats *mmc_blk_get_packed_statistics(struct mmc_card *card) +{ + if (!card) + return NULL; + + return &card->wr_pack_stats; +} +EXPORT_SYMBOL(mmc_blk_get_packed_statistics); + +void mmc_blk_init_packed_statistics(struct mmc_card *card) +{ + int max_num_of_packed_reqs = 0; + + if (!card || !card->wr_pack_stats.packing_events) + return; + + max_num_of_packed_reqs = card->ext_csd.max_packed_writes; + + spin_lock(&card->wr_pack_stats.lock); + memset(card->wr_pack_stats.packing_events, 0, + (max_num_of_packed_reqs + 1) * + sizeof(*card->wr_pack_stats.packing_events)); + memset(&card->wr_pack_stats.pack_stop_reason, 0, + sizeof(card->wr_pack_stats.pack_stop_reason)); + card->wr_pack_stats.enabled = true; + spin_unlock(&card->wr_pack_stats.lock); +} +EXPORT_SYMBOL(mmc_blk_init_packed_statistics); + static u8 mmc_blk_prep_packed_list(struct mmc_queue *mq, struct request *req) { struct request_queue *q = mq->queue; @@ -1650,10 +2718,14 @@ bool put_back = true; u8 max_packed_rw = 0; u8 reqs = 0; + struct mmc_wr_pack_stats *stats = &card->wr_pack_stats; if (!(md->flags & MMC_BLK_PACKED_CMD)) goto no_packed; + if (!mq->wr_packing_enabled) + goto no_packed; + if ((rq_data_dir(cur) == WRITE) && mmc_host_packed_wr(card->host)) max_packed_rw = card->ext_csd.max_packed_writes; @@ -1669,6 +2741,9 @@ !IS_ALIGNED(blk_rq_sectors(cur), 8)) goto no_packed; + if (cur->cmd_flags & REQ_FUA) + goto no_packed; + mmc_blk_clear_packed(mqrq); max_blk_count = min(card->host->max_blk_count, @@ -1685,6 +2760,7 @@ phys_segments += mmc_calc_packed_hdr_segs(q, card); } + spin_lock(&stats->lock); do { if (reqs >= max_packed_rw - 1) { put_back = false; @@ -1695,33 +2771,63 @@ next = blk_fetch_request(q); spin_unlock_irq(q->queue_lock); if (!next) { + MMC_BLK_UPDATE_STOP_REASON(stats, EMPTY_QUEUE); put_back = false; break; } if (mmc_large_sector(card) && - !IS_ALIGNED(blk_rq_sectors(next), 8)) + !IS_ALIGNED(blk_rq_sectors(next), 8)) { + MMC_BLK_UPDATE_STOP_REASON(stats, LARGE_SEC_ALIGN); break; + } if (next->cmd_flags & REQ_DISCARD || - next->cmd_flags & REQ_FLUSH) + next->cmd_flags & REQ_FLUSH) { + MMC_BLK_UPDATE_STOP_REASON(stats, FLUSH_OR_DISCARD); + break; + } + + if (next->cmd_flags & REQ_FUA) { + MMC_BLK_UPDATE_STOP_REASON(stats, FUA); break; + } - if (rq_data_dir(cur) != rq_data_dir(next)) + if (rq_data_dir(cur) != rq_data_dir(next)) { + MMC_BLK_UPDATE_STOP_REASON(stats, WRONG_DATA_DIR); break; + } if (mmc_req_rel_wr(next) && - (md->flags & MMC_BLK_REL_WR) && !en_rel_wr) + (md->flags & MMC_BLK_REL_WR) && !en_rel_wr) { + MMC_BLK_UPDATE_STOP_REASON(stats, REL_WRITE); break; + } req_sectors += blk_rq_sectors(next); - if (req_sectors > max_blk_count) + if (req_sectors > max_blk_count) { + if (stats->enabled) + stats->pack_stop_reason[EXCEEDS_SECTORS]++; break; + } phys_segments += next->nr_phys_segments; - if (phys_segments > max_phys_segs) + if (phys_segments > max_phys_segs) { + MMC_BLK_UPDATE_STOP_REASON(stats, EXCEEDS_SEGMENTS); + break; + } + + if (mq->no_pack_for_random) { + if ((blk_rq_pos(cur) + blk_rq_sectors(cur)) != + blk_rq_pos(next)) { + MMC_BLK_UPDATE_STOP_REASON(stats, RANDOM); + put_back = 1; break; + } + } + if (rq_data_dir(next) == WRITE) + mq->num_of_potential_packed_wr_reqs++; list_add_tail(&next->queuelist, &mqrq->packed->list); cur = next; reqs++; @@ -1733,6 +2839,15 @@ spin_unlock_irq(q->queue_lock); } + if (stats->enabled) { + if (reqs + 1 <= card->ext_csd.max_packed_writes) + stats->packing_events[reqs + 1]++; + if (reqs + 1 == max_packed_rw) + MMC_BLK_UPDATE_STOP_REASON(stats, THRESHOLD); + } + + spin_unlock(&stats->lock); + if (reqs > 0) { list_add(&req->queuelist, &mqrq->packed->list); mqrq->packed->nr_entries = ++reqs; @@ -1813,6 +2928,7 @@ brq->data.blksz = 512; brq->data.blocks = packed->blocks + hdr_blocks; brq->data.flags |= MMC_DATA_WRITE; + brq->data.fault_injected = false; brq->stop.opcode = MMC_STOP_TRANSMISSION; brq->stop.arg = 0; @@ -1824,8 +2940,19 @@ brq->data.sg_len = mmc_queue_map_sg(mq, mqrq); mqrq->mmc_active.mrq = &brq->mrq; + + /* + * This is intended for packed commands tests usage - in case these + * functions are not in use the respective pointers are NULL + */ + if (mq->err_check_fn) + mqrq->mmc_active.err_check = mq->err_check_fn; + else mqrq->mmc_active.err_check = mmc_blk_packed_err_check; + if (mq->packed_test_fn) + mq->packed_test_fn(mq->queue, mqrq); + mmc_queue_bounce_pre(mqrq); } @@ -1846,11 +2973,12 @@ */ if (mmc_card_sd(card)) { u32 blocks; - + if (!brq->data.fault_injected) { blocks = mmc_sd_num_wr_blocks(card); - if (blocks != (u32)-1) { + if (blocks != (u32)-1) ret = blk_end_request(req, 0, blocks << 9); - } + } else + ret = blk_end_request(req, 0, brq->data.bytes_xfered); } else { if (!mmc_packed_cmd(mq_rq->cmd_type)) ret = blk_end_request(req, 0, brq->data.bytes_xfered); @@ -1930,6 +3058,614 @@ mmc_blk_clear_packed(mq_rq); } +static int mmc_blk_cmdq_start_req(struct mmc_host *host, + struct mmc_cmdq_req *cmdq_req) +{ + struct mmc_request *mrq = &cmdq_req->mrq; + + mrq->done = mmc_blk_cmdq_req_done; + return mmc_cmdq_start_req(host, cmdq_req); +} + +/* prepare for non-data commands */ +static struct mmc_cmdq_req *mmc_cmdq_prep_dcmd( + struct mmc_queue_req *mqrq, struct mmc_queue *mq) +{ + struct request *req = mqrq->req; + struct mmc_cmdq_req *cmdq_req = &mqrq->cmdq_req; + + memset(&mqrq->cmdq_req, 0, sizeof(struct mmc_cmdq_req)); + + cmdq_req->mrq.data = NULL; + cmdq_req->cmd_flags = req->cmd_flags; + cmdq_req->mrq.req = mqrq->req; + req->special = mqrq; + cmdq_req->cmdq_req_flags |= DCMD; + cmdq_req->mrq.cmdq_req = cmdq_req; + + return &mqrq->cmdq_req; +} + + +#define IS_RT_CLASS_REQ(x) \ + (IOPRIO_PRIO_CLASS(req_get_ioprio(x)) == IOPRIO_CLASS_RT) + +static struct mmc_cmdq_req *mmc_blk_cmdq_rw_prep( + struct mmc_queue_req *mqrq, struct mmc_queue *mq) +{ + struct mmc_card *card = mq->card; + struct request *req = mqrq->req; + struct mmc_blk_data *md = mq->data; + bool do_rel_wr = mmc_req_rel_wr(req) && (md->flags & MMC_BLK_REL_WR); + bool do_data_tag; + bool read_dir = (rq_data_dir(req) == READ); + bool prio = IS_RT_CLASS_REQ(req); + struct mmc_cmdq_req *cmdq_rq = &mqrq->cmdq_req; + + memset(&mqrq->cmdq_req, 0, sizeof(struct mmc_cmdq_req)); + + cmdq_rq->tag = req->tag; + if (read_dir) { + cmdq_rq->cmdq_req_flags |= DIR; + cmdq_rq->data.flags = MMC_DATA_READ; + } else { + cmdq_rq->data.flags = MMC_DATA_WRITE; + } + if (prio) + cmdq_rq->cmdq_req_flags |= PRIO; + + if (do_rel_wr) + cmdq_rq->cmdq_req_flags |= REL_WR; + + cmdq_rq->data.blocks = blk_rq_sectors(req); + cmdq_rq->blk_addr = blk_rq_pos(req); + cmdq_rq->data.blksz = MMC_CARD_CMDQ_BLK_SIZE; + + mmc_set_data_timeout(&cmdq_rq->data, card); + + do_data_tag = (card->ext_csd.data_tag_unit_size) && + (req->cmd_flags & REQ_META) && + (rq_data_dir(req) == WRITE) && + ((cmdq_rq->data.blocks * cmdq_rq->data.blksz) >= + card->ext_csd.data_tag_unit_size); + if (do_data_tag) + cmdq_rq->cmdq_req_flags |= DAT_TAG; + cmdq_rq->data.sg = mqrq->sg; + cmdq_rq->data.sg_len = mmc_queue_map_sg(mq, mqrq); + + /* + * Adjust the sg list so it is the same size as the + * request. + */ + if (cmdq_rq->data.blocks > card->host->max_blk_count) + cmdq_rq->data.blocks = card->host->max_blk_count; + + if (cmdq_rq->data.blocks != blk_rq_sectors(req)) { + int i, data_size = cmdq_rq->data.blocks << 9; + struct scatterlist *sg; + + for_each_sg(cmdq_rq->data.sg, sg, cmdq_rq->data.sg_len, i) { + data_size -= sg->length; + if (data_size <= 0) { + sg->length += data_size; + i++; + break; + } + } + cmdq_rq->data.sg_len = i; + } + + mqrq->cmdq_req.cmd_flags = req->cmd_flags; + mqrq->cmdq_req.mrq.req = mqrq->req; + mqrq->cmdq_req.mrq.cmdq_req = &mqrq->cmdq_req; + mqrq->cmdq_req.mrq.data = &mqrq->cmdq_req.data; + mqrq->req->special = mqrq; + + pr_debug("%s: %s: mrq: 0x%p req: 0x%p mqrq: 0x%p bytes to xf: %d mmc_cmdq_req: 0x%p card-addr: 0x%08x dir(r-1/w-0): %d\n", + mmc_hostname(card->host), __func__, &mqrq->cmdq_req.mrq, + mqrq->req, mqrq, (cmdq_rq->data.blocks * cmdq_rq->data.blksz), + cmdq_rq, cmdq_rq->blk_addr, + (cmdq_rq->cmdq_req_flags & DIR) ? 1 : 0); + + return &mqrq->cmdq_req; +} + +static void mmc_blk_cmdq_requeue_rw_rq(struct mmc_queue *mq, + struct request *req) +{ + struct mmc_card *card = mq->card; + struct mmc_host *host = card->host; + + blk_requeue_request(req->q, req); + mmc_put_card(host->card); +} + +static int mmc_blk_cmdq_issue_rw_rq(struct mmc_queue *mq, struct request *req) +{ + struct mmc_queue_req *active_mqrq; + struct mmc_card *card = mq->card; + struct mmc_host *host = card->host; + struct mmc_cmdq_context_info *ctx = &host->cmdq_ctx; + struct mmc_cmdq_req *mc_rq; + u8 active_small_sector_read = 0; + int ret = 0; + + mmc_deferred_scaling(host); + mmc_cmdq_clk_scaling_start_busy(host, true); + + BUG_ON((req->tag < 0) || (req->tag > card->ext_csd.cmdq_depth)); + BUG_ON(test_and_set_bit(req->tag, &host->cmdq_ctx.data_active_reqs)); + BUG_ON(test_and_set_bit(req->tag, &host->cmdq_ctx.active_reqs)); + + active_mqrq = &mq->mqrq_cmdq[req->tag]; + active_mqrq->req = req; + + mc_rq = mmc_blk_cmdq_rw_prep(active_mqrq, mq); + + if (card->quirks & MMC_QUIRK_CMDQ_EMPTY_BEFORE_DCMD) { + unsigned int sectors = blk_rq_sectors(req); + + if (((sectors > 0) && (sectors < 8)) + && (rq_data_dir(req) == READ)) + active_small_sector_read = 1; + } + ret = mmc_blk_cmdq_start_req(card->host, mc_rq); + if (!ret && active_small_sector_read) + host->cmdq_ctx.active_small_sector_read_reqs++; + /* + * When in SVS2 on low load scenario and there are lots of requests + * queued for CMDQ we need to wait till the queue is empty to scale + * back up to Nominal even if there is a sudden increase in load. + * This impacts performance where lots of IO get executed in SVS2 + * frequency since the queue is full. As SVS2 is a low load use case + * we can serialize the requests and not queue them in parallel + * without impacting other use cases. This makes sure the queue gets + * empty faster and we will be able to scale up to Nominal frequency + * when needed. + */ + if (!ret && (host->clk_scaling.state == MMC_LOAD_LOW)) + wait_event_interruptible(ctx->queue_empty_wq, + (!ctx->active_reqs)); + + if (ret) { + /* clear pending request */ + WARN_ON(!test_and_clear_bit(req->tag, + &host->cmdq_ctx.data_active_reqs)); + WARN_ON(!test_and_clear_bit(req->tag, + &host->cmdq_ctx.active_reqs)); + mmc_cmdq_clk_scaling_stop_busy(host, true, false); + } + + return ret; +} + +/* + * Issues a flush (dcmd) request + */ +int mmc_blk_cmdq_issue_flush_rq(struct mmc_queue *mq, struct request *req) +{ + int err; + struct mmc_queue_req *active_mqrq; + struct mmc_card *card = mq->card; + struct mmc_host *host; + struct mmc_cmdq_req *cmdq_req; + struct mmc_cmdq_context_info *ctx_info; + + BUG_ON(!card); + host = card->host; + BUG_ON(!host); + BUG_ON(req->tag > card->ext_csd.cmdq_depth); + BUG_ON(test_and_set_bit(req->tag, &host->cmdq_ctx.active_reqs)); + + ctx_info = &host->cmdq_ctx; + + set_bit(CMDQ_STATE_DCMD_ACTIVE, &ctx_info->curr_state); + + active_mqrq = &mq->mqrq_cmdq[req->tag]; + active_mqrq->req = req; + + cmdq_req = mmc_cmdq_prep_dcmd(active_mqrq, mq); + cmdq_req->cmdq_req_flags |= QBR; + cmdq_req->mrq.cmd = &cmdq_req->cmd; + cmdq_req->tag = req->tag; + + err = mmc_cmdq_prepare_flush(cmdq_req->mrq.cmd); + if (err) { + pr_err("%s: failed (%d) preparing flush req\n", + mmc_hostname(host), err); + return err; + } + err = mmc_blk_cmdq_start_req(card->host, cmdq_req); + return err; +} +EXPORT_SYMBOL(mmc_blk_cmdq_issue_flush_rq); + +static void mmc_blk_cmdq_reset(struct mmc_host *host, bool clear_all) +{ + int err = 0; + + if (mmc_cmdq_halt(host, true)) { + pr_err("%s: halt failed\n", mmc_hostname(host)); + goto reset; + } + + if (clear_all) + mmc_cmdq_discard_queue(host, 0); +reset: + mmc_host_clk_hold(host); + host->cmdq_ops->disable(host, true); + mmc_host_clk_release(host); + err = mmc_cmdq_hw_reset(host); + if (err && err != -EOPNOTSUPP) { + pr_err("%s: failed to cmdq_hw_reset err = %d\n", + mmc_hostname(host), err); + mmc_host_clk_hold(host); + host->cmdq_ops->enable(host); + mmc_host_clk_release(host); + mmc_cmdq_halt(host, false); + goto out; + } + /* + * CMDQ HW reset would have already made CQE + * in unhalted state, but reflect the same + * in software state of cmdq_ctx. + */ + mmc_host_clr_halt(host); +out: + return; +} + +/** + * is_cmdq_dcmd_req - Checks if tag belongs to DCMD request. + * @q: request_queue pointer. + * @tag: tag number of request to check. + * + * This function checks if the request with tag number "tag" + * is a DCMD request or not based on cmdq_req_flags set. + * + * returns true if DCMD req, otherwise false. + */ +static bool is_cmdq_dcmd_req(struct request_queue *q, int tag) +{ + struct request *req; + struct mmc_queue_req *mq_rq; + struct mmc_cmdq_req *cmdq_req; + + req = blk_queue_find_tag(q, tag); + if (WARN_ON(!req)) + goto out; + mq_rq = req->special; + if (WARN_ON(!mq_rq)) + goto out; + cmdq_req = &(mq_rq->cmdq_req); + return (cmdq_req->cmdq_req_flags & DCMD); +out: + return -ENOENT; +} + +/** + * mmc_blk_cmdq_reset_all - Reset everything for CMDQ block request. + * @host: mmc_host pointer. + * @err: error for which reset is performed. + * + * This function implements reset_all functionality for + * cmdq. It resets the controller, power cycle the card, + * and invalidate all busy tags(requeue all request back to + * elevator). + */ +static void mmc_blk_cmdq_reset_all(struct mmc_host *host, int err) +{ + struct mmc_request *mrq = host->err_mrq; + struct mmc_card *card = host->card; + struct mmc_cmdq_context_info *ctx_info = &host->cmdq_ctx; + struct request_queue *q; + int itag = 0; + int ret = 0; + + if (WARN_ON(!mrq)) + return; + + q = mrq->req->q; + WARN_ON(!test_bit(CMDQ_STATE_ERR, &ctx_info->curr_state)); + + #ifdef CONFIG_MMC_CLKGATE + pr_debug("%s: %s: active_reqs = %lu, clk_requests = %d\n", + mmc_hostname(host), __func__, + ctx_info->active_reqs, host->clk_requests); + #endif + + mmc_blk_cmdq_reset(host, false); + + for_each_set_bit(itag, &ctx_info->active_reqs, + host->num_cq_slots) { + ret = is_cmdq_dcmd_req(q, itag); + if (WARN_ON(ret == -ENOENT)) + continue; + if (!ret) { + WARN_ON(!test_and_clear_bit(itag, + &ctx_info->data_active_reqs)); + mmc_cmdq_post_req(host, itag, err); + } else { + clear_bit(CMDQ_STATE_DCMD_ACTIVE, + &ctx_info->curr_state); + } + WARN_ON(!test_and_clear_bit(itag, + &ctx_info->active_reqs)); + mmc_host_clk_release(host); + mmc_put_card(card); + } + + spin_lock_irq(q->queue_lock); + blk_queue_invalidate_tags(q); + spin_unlock_irq(q->queue_lock); +} + +static void mmc_blk_cmdq_shutdown(struct mmc_queue *mq) +{ + int err; + struct mmc_card *card = mq->card; + struct mmc_host *host = card->host; + + mmc_get_card(card); + mmc_host_clk_hold(host); + err = mmc_cmdq_halt(host, true); + if (err) { + pr_err("%s: halt: failed: %d\n", __func__, err); + goto out; + } + + /* disable CQ mode in card */ + if (mmc_card_cmdq(card)) { + err = mmc_switch(card, EXT_CSD_CMD_SET_NORMAL, + EXT_CSD_CMDQ, 0, + card->ext_csd.generic_cmd6_time); + if (err) { + pr_err("%s: failed to switch card to legacy mode: %d\n", + __func__, err); + goto out; + } + mmc_card_clr_cmdq(card); + } + host->cmdq_ops->disable(host, false); + host->card->cmdq_init = false; +out: + mmc_host_clk_release(host); + mmc_put_card(card); +} + +static enum blk_eh_timer_return mmc_blk_cmdq_req_timed_out(struct request *req) +{ + struct mmc_queue *mq = req->q->queuedata; + struct mmc_host *host = mq->card->host; + struct mmc_queue_req *mq_rq = req->special; + struct mmc_request *mrq; + struct mmc_cmdq_req *cmdq_req; + struct mmc_cmdq_context_info *ctx_info = &host->cmdq_ctx; + + BUG_ON(!host); + + /* + * The mmc_queue_req will be present only if the request + * is issued to the LLD. The request could be fetched from + * block layer queue but could be waiting to be issued + * (for e.g. clock scaling is waiting for an empty cmdq queue) + * Reset the timer in such cases to give LLD more time + */ + if (!mq_rq) { + pr_warn("%s: restart timer for tag: %d\n", __func__, req->tag); + return BLK_EH_RESET_TIMER; + } + + mrq = &mq_rq->cmdq_req.mrq; + cmdq_req = &mq_rq->cmdq_req; + + BUG_ON(!mrq || !cmdq_req); + + if (cmdq_req->cmdq_req_flags & DCMD) + mrq->cmd->error = -ETIMEDOUT; + else + mrq->data->error = -ETIMEDOUT; + + if (mrq->cmd && mrq->cmd->error) { + if (!(mrq->req->cmd_flags & REQ_FLUSH)) { + /* + * Notify completion for non flush commands like + * discard that wait for DCMD finish. + */ + set_bit(CMDQ_STATE_REQ_TIMED_OUT, + &ctx_info->curr_state); + complete(&mrq->completion); + return BLK_EH_NOT_HANDLED; + } + } + + if (test_bit(CMDQ_STATE_REQ_TIMED_OUT, &ctx_info->curr_state) || + test_bit(CMDQ_STATE_ERR, &ctx_info->curr_state)) + return BLK_EH_NOT_HANDLED; + + set_bit(CMDQ_STATE_REQ_TIMED_OUT, &ctx_info->curr_state); + return BLK_EH_HANDLED; +} + +/* + * mmc_blk_cmdq_err: error handling of cmdq error requests. + * Function should be called in context of error out request + * which has claim_host and rpm acquired. + * This may be called with CQ engine halted. Make sure to + * unhalt it after error recovery. + * + * TODO: Currently cmdq error handler does reset_all in case + * of any erorr. Need to optimize error handling. + */ +static void mmc_blk_cmdq_err(struct mmc_queue *mq) +{ + struct mmc_host *host = mq->card->host; + struct mmc_request *mrq = host->err_mrq; + struct mmc_cmdq_context_info *ctx_info = &host->cmdq_ctx; + struct request_queue *q; + int err, ret; + u32 status = 0; + + mmc_host_clk_hold(host); + host->cmdq_ops->dumpstate(host); + mmc_host_clk_release(host); + + if (WARN_ON(!mrq)) + return; + + q = mrq->req->q; + err = mmc_cmdq_halt(host, true); + if (err) { + pr_err("halt: failed: %d\n", err); + goto reset; + } + + /* RED error - Fatal: requires reset */ + if (mrq->cmdq_req->resp_err) { + err = mrq->cmdq_req->resp_err; + goto reset; + } + + /* + * TIMEOUT errrors can happen because of execution error + * in the last command. So send cmd 13 to get device status + */ + if ((mrq->cmd && (mrq->cmd->error == -ETIMEDOUT)) || + (mrq->data && (mrq->data->error == -ETIMEDOUT))) { + if (mmc_host_halt(host) || mmc_host_cq_disable(host)) { + ret = get_card_status(host->card, &status, 0); + if (ret) + pr_err("%s: CMD13 failed with err %d\n", + mmc_hostname(host), ret); + } + pr_err("%s: Timeout error detected with device status 0x%08x\n", + mmc_hostname(host), status); + } + + /* + * In case of software request time-out, we schedule err work only for + * the first error out request and handles all other request in flight + * here. + */ + if (test_bit(CMDQ_STATE_REQ_TIMED_OUT, &ctx_info->curr_state)) { + err = -ETIMEDOUT; + } else if (mrq->data && mrq->data->error) { + err = mrq->data->error; + } else if (mrq->cmd && mrq->cmd->error) { + /* DCMD commands */ + err = mrq->cmd->error; + } + +reset: + mmc_blk_cmdq_reset_all(host, err); + if (mrq->cmdq_req->resp_err) + mrq->cmdq_req->resp_err = false; + mmc_cmdq_halt(host, false); + + host->err_mrq = NULL; + clear_bit(CMDQ_STATE_REQ_TIMED_OUT, &ctx_info->curr_state); + WARN_ON(!test_and_clear_bit(CMDQ_STATE_ERR, &ctx_info->curr_state)); + wake_up(&ctx_info->wait); +} + +/* invoked by block layer in softirq context */ +void mmc_blk_cmdq_complete_rq(struct request *rq) +{ + struct mmc_queue_req *mq_rq = rq->special; + struct mmc_request *mrq = &mq_rq->cmdq_req.mrq; + struct mmc_host *host = mrq->host; + struct mmc_cmdq_context_info *ctx_info = &host->cmdq_ctx; + struct mmc_cmdq_req *cmdq_req = &mq_rq->cmdq_req; + struct mmc_queue *mq = (struct mmc_queue *)rq->q->queuedata; + int err = 0; + bool is_dcmd = false; + + if (mrq->cmd && mrq->cmd->error) + err = mrq->cmd->error; + else if (mrq->data && mrq->data->error) + err = mrq->data->error; + + if ((err || cmdq_req->resp_err) && !cmdq_req->skip_err_handling) { + pr_err("%s: %s: txfr error(%d)/resp_err(%d)\n", + mmc_hostname(mrq->host), __func__, err, + cmdq_req->resp_err); + if (test_bit(CMDQ_STATE_ERR, &ctx_info->curr_state)) { + pr_err("%s: CQ in error state, ending current req: %d\n", + __func__, err); + } else { + set_bit(CMDQ_STATE_ERR, &ctx_info->curr_state); + BUG_ON(host->err_mrq != NULL); + host->err_mrq = mrq; + schedule_work(&mq->cmdq_err_work); + } + goto out; + } + /* + * In case of error CMDQ is expected to be either in halted + * or disable state so cannot receive any completion of + * other requests. + */ + BUG_ON(test_bit(CMDQ_STATE_ERR, &ctx_info->curr_state)); + + /* clear pending request */ + BUG_ON(!test_and_clear_bit(cmdq_req->tag, + &ctx_info->active_reqs)); + if (cmdq_req->cmdq_req_flags & DCMD) + is_dcmd = true; + else + BUG_ON(!test_and_clear_bit(cmdq_req->tag, + &ctx_info->data_active_reqs)); + if (!is_dcmd) + mmc_cmdq_post_req(host, cmdq_req->tag, err); + if (cmdq_req->cmdq_req_flags & DCMD) { + clear_bit(CMDQ_STATE_DCMD_ACTIVE, &ctx_info->curr_state); + blk_end_request_all(rq, err); + goto out; + } + /* + * In case of error, cmdq_req->data.bytes_xfered is set to 0. + * If we call blk_end_request() with nr_bytes as 0 then the request + * never gets completed. So in case of error, to complete a request + * with error we should use blk_end_request_all(). + */ + if (err && cmdq_req->skip_err_handling) { + cmdq_req->skip_err_handling = false; + blk_end_request_all(rq, err); + goto out; + } + + blk_end_request(rq, err, cmdq_req->data.bytes_xfered); + +out: + + mmc_cmdq_clk_scaling_stop_busy(host, true, is_dcmd); + if (!test_bit(CMDQ_STATE_ERR, &ctx_info->curr_state)) { + mmc_host_clk_release(host); + wake_up(&ctx_info->wait); + mmc_put_card(host->card); + } + + if (!ctx_info->active_reqs) + wake_up_interruptible(&host->cmdq_ctx.queue_empty_wq); + + if (blk_queue_stopped(mq->queue) && !ctx_info->active_reqs) + complete(&mq->cmdq_shutdown_complete); + + return; +} + +/* + * Complete reqs from block layer softirq context + * Invoked in irq context + */ +void mmc_blk_cmdq_req_done(struct mmc_request *mrq) +{ + struct request *req = mrq->req; + + blk_complete_request(req); +} +EXPORT_SYMBOL(mmc_blk_cmdq_req_done); + static int mmc_blk_issue_rw_rq(struct mmc_queue *mq, struct request *rqc) { struct mmc_blk_data *md = mq->data; @@ -1942,6 +3678,10 @@ struct mmc_async_req *areq; const u8 packed_nr = 2; u8 reqs = 0; + bool reset = false; +#ifdef CONFIG_MMC_SIMULATE_MAX_SPEED + unsigned long waitfor = jiffies; +#endif if (!rqc && !mq->mqrq_prev->req) return 0; @@ -1974,7 +3714,7 @@ areq = mmc_start_req(card->host, areq, (int *) &status); if (!areq) { if (status == MMC_BLK_NEW_REQUEST) - mq->flags |= MMC_QUEUE_NEW_REQUEST; + set_bit(MMC_QUEUE_NEW_REQUEST, &mq->flags); return 0; } @@ -1984,6 +3724,26 @@ type = rq_data_dir(req) == READ ? MMC_BLK_READ : MMC_BLK_WRITE; mmc_queue_bounce_post(mq_rq); + if (card->err_in_sdr104) { + /* + * Data CRC/timeout errors will manifest as CMD/DATA + * ERR. But we'd like to retry these too. + * Moreover, no harm done if this fails too for multiple + * times, we anyway reduce the bus-speed and retry the + * same request. + * If that fails too, we don't override this status. + */ + if (status == MMC_BLK_ABORT || + status == MMC_BLK_CMD_ERR || + status == MMC_BLK_DATA_ERR || + status == MMC_BLK_RETRY) + /* reset on all of these errors and retry */ + reset = true; + + status = MMC_BLK_RETRY; + card->err_in_sdr104 = false; + } + switch (status) { case MMC_BLK_SUCCESS: case MMC_BLK_PARTIAL: @@ -1992,6 +3752,8 @@ */ mmc_blk_reset_success(md, type); + mmc_blk_simulate_delay(mq, rqc, waitfor); + if (mmc_packed_cmd(mq_rq->cmd_type)) { ret = mmc_blk_end_packed_req(mq_rq); break; @@ -2022,11 +3784,36 @@ break; case MMC_BLK_RETRY: retune_retry_done = brq->retune_retry_done; - if (retry++ < 5) + if (retry++ < MMC_BLK_MAX_RETRIES) { + break; + } else if (reset) { + reset = false; + /* + * If we exhaust all the retries due to + * CRC/timeout errors in SDR140 mode with UHS SD + * cards, re-configure the card in SDR50 + * bus-speed mode. + * All subsequent re-init of this card will be + * in SDR50 mode, unless it is removed and + * re-inserted. When new UHS SD cards are + * inserted, it may start at SDR104 mode if + * supported by the card. + */ + pr_err("%s: blocked SDR104, lower the bus-speed (SDR50 / DDR50)\n", + req->rq_disk->disk_name); + mmc_host_clear_sdr104(card->host); + mmc_suspend_clk_scaling(card->host); + mmc_blk_reset(md, card->host, type); + /* SDR104 mode is blocked from now on */ + card->sdr104_blocked = true; + /* retry 5 times again */ + retry = 0; break; + } /* Fall through */ case MMC_BLK_ABORT: - if (!mmc_blk_reset(md, card->host, type)) + if (!mmc_blk_reset(md, card->host, type) && + (retry++ < (MMC_BLK_MAX_RETRIES + 1))) break; goto cmd_abort; case MMC_BLK_DATA_ERR: { @@ -2035,10 +3822,7 @@ err = mmc_blk_reset(md, card->host, type); if (!err) break; - if (err == -ENODEV || - mmc_packed_cmd(mq_rq->cmd_type)) goto cmd_abort; - /* Fall through */ } case MMC_BLK_ECC_ERR: if (brq->data.blocks > 1) { @@ -2122,6 +3906,181 @@ return 0; } +static inline int mmc_blk_cmdq_part_switch(struct mmc_card *card, + struct mmc_blk_data *md) +{ + struct mmc_blk_data *main_md = mmc_get_drvdata(card); + struct mmc_host *host = card->host; + struct mmc_cmdq_context_info *ctx = &host->cmdq_ctx; + u8 part_config = card->ext_csd.part_config; + int ret = 0, err = 0; + + if ((main_md->part_curr == md->part_type) && + (card->part_curr == md->part_type)) + return 0; + + WARN_ON(!((card->host->caps2 & MMC_CAP2_CMD_QUEUE) && + card->ext_csd.cmdq_support && + (md->flags & MMC_BLK_CMD_QUEUE))); + + if (!test_bit(CMDQ_STATE_HALT, &ctx->curr_state)) { + ret = mmc_cmdq_halt(host, true); + if (ret) { + pr_err("%s: %s: halt: failed: %d\n", + mmc_hostname(host), __func__, ret); + goto out; + } + } + + /* disable CQ mode in card */ + if (mmc_card_cmdq(card)) { + ret = mmc_switch(card, EXT_CSD_CMD_SET_NORMAL, + EXT_CSD_CMDQ, 0, + card->ext_csd.generic_cmd6_time); + if (ret) { + pr_err("%s: %s: cmdq mode disable failed %d\n", + mmc_hostname(host), __func__, ret); + goto cmdq_unhalt; + } + mmc_card_clr_cmdq(card); + } + + part_config &= ~EXT_CSD_PART_CONFIG_ACC_MASK; + part_config |= md->part_type; + + ret = mmc_switch(card, EXT_CSD_CMD_SET_NORMAL, + EXT_CSD_PART_CONFIG, part_config, + card->ext_csd.part_time); + if (ret) { + pr_err("%s: %s: mmc_switch failure, %d -> %d , err = %d\n", + mmc_hostname(host), __func__, main_md->part_curr, + md->part_type, ret); + goto cmdq_switch; + } + + card->ext_csd.part_config = part_config; + card->part_curr = md->part_type; + + main_md->part_curr = md->part_type; + +cmdq_switch: + err = mmc_blk_cmdq_switch(card, md, true); + if (err) { + pr_err("%s: %s: mmc_blk_cmdq_switch failed: %d\n", + mmc_hostname(host), __func__, err); + ret = err; + } +cmdq_unhalt: + err = mmc_cmdq_halt(host, false); + if (err) { + pr_err("%s: %s: unhalt: failed: %d\n", + mmc_hostname(host), __func__, err); + ret = err; + } +out: + return ret; +} + +static int mmc_blk_cmdq_issue_rq(struct mmc_queue *mq, struct request *req) +{ + int ret, err = 0; + struct mmc_blk_data *md = mq->data; + struct mmc_card *card = md->queue.card; + struct mmc_host *host = card->host; + unsigned int cmd_flags = req ? req->cmd_flags : 0; + + mmc_get_card(card); + + if (!card->host->cmdq_ctx.active_reqs && mmc_card_doing_bkops(card)) { + ret = mmc_cmdq_halt(card->host, true); + if (ret) + goto out; + ret = mmc_stop_bkops(card); + if (ret) { + pr_err("%s: %s: mmc_stop_bkops failed %d\n", + md->disk->disk_name, __func__, ret); + goto out; + } + ret = mmc_cmdq_halt(card->host, false); + if (ret) + goto out; + } + + ret = mmc_blk_cmdq_part_switch(card, md); + if (ret) { + pr_err("%s: %s: partition switch failed %d, resetting cmdq\n", + md->disk->disk_name, __func__, ret); + + mmc_blk_cmdq_reset(host, false); + err = mmc_blk_cmdq_part_switch(card, md); + if (!err) { + pr_err("%s: %s: partition switch success err = %d\n", + md->disk->disk_name, __func__, err); + } else { + pr_err("%s: %s: partition switch failed err = %d\n", + md->disk->disk_name, __func__, err); + ret = err; + goto out; + } + } + + if (req) { + struct mmc_host *host = card->host; + struct mmc_cmdq_context_info *ctx = &host->cmdq_ctx; + + if ((cmd_flags & (REQ_FLUSH | REQ_DISCARD)) && + (card->quirks & MMC_QUIRK_CMDQ_EMPTY_BEFORE_DCMD) && + ctx->active_small_sector_read_reqs) { + ret = wait_event_interruptible(ctx->queue_empty_wq, + !ctx->active_reqs); + if (ret) { + pr_err("%s: failed while waiting for the CMDQ to be empty %s err (%d)\n", + mmc_hostname(host), + __func__, ret); + BUG_ON(1); + } + /* clear the counter now */ + ctx->active_small_sector_read_reqs = 0; + /* + * If there were small sector (less than 8 sectors) read + * operations in progress then we have to wait for the + * outstanding requests to finish and should also have + * atleast 6 microseconds delay before queuing the DCMD + * request. + */ + udelay(MMC_QUIRK_CMDQ_DELAY_BEFORE_DCMD); + } + + if (cmd_flags & REQ_DISCARD) { + if (cmd_flags & REQ_SECURE && + !(card->quirks & MMC_QUIRK_SEC_ERASE_TRIM_BROKEN)) + ret = mmc_blk_cmdq_issue_secdiscard_rq(mq, req); + else + ret = mmc_blk_cmdq_issue_discard_rq(mq, req); + } else if (cmd_flags & REQ_FLUSH) { + ret = mmc_blk_cmdq_issue_flush_rq(mq, req); + } else { + ret = mmc_blk_cmdq_issue_rw_rq(mq, req); + /* + * If issuing of the request fails with eitehr EBUSY or + * EAGAIN error, re-queue the request. + * This case would occur with ICE calls. + */ + if (ret == -EBUSY || ret == -EAGAIN) + mmc_blk_cmdq_requeue_rw_rq(mq, req); + } + } + + return ret; + +out: + if (req) + blk_end_request_all(req, ret); + mmc_put_card(card); + + return ret; +} + static int mmc_blk_issue_rq(struct mmc_queue *mq, struct request *req) { int ret; @@ -2130,13 +4089,31 @@ struct mmc_host *host = card->host; unsigned long flags; unsigned int cmd_flags = req ? req->cmd_flags : 0; + int err; - if (req && !mq->mqrq_prev->req) + if (req && !mq->mqrq_prev->req) { /* claim host only for the first request */ mmc_get_card(card); + if (mmc_card_doing_bkops(host->card)) { + ret = mmc_stop_bkops(host->card); + if (ret) + goto out; + } + } + ret = mmc_blk_part_switch(card, md); + if (ret) { + err = mmc_blk_reset(md, card->host, MMC_BLK_PARTSWITCH); + if (!err) { + pr_err("%s: mmc_blk_reset(MMC_BLK_PARTSWITCH) succeeded.\n", + mmc_hostname(host)); + mmc_blk_reset_success(md, MMC_BLK_PARTSWITCH); + } else + pr_err("%s: mmc_blk_reset(MMC_BLK_PARTSWITCH) failed.\n", + mmc_hostname(host)); + if (req) { blk_end_request_all(req, -EIO); } @@ -2144,16 +4121,19 @@ goto out; } - mq->flags &= ~MMC_QUEUE_NEW_REQUEST; + mmc_blk_write_packing_control(mq, req); + + clear_bit(MMC_QUEUE_NEW_REQUEST, &mq->flags); if (cmd_flags & REQ_DISCARD) { /* complete ongoing async transfer before issuing discard */ if (card->host->areq) mmc_blk_issue_rw_rq(mq, NULL); - if (req->cmd_flags & REQ_SECURE) + if (cmd_flags & REQ_SECURE && + !(card->quirks & MMC_QUIRK_SEC_ERASE_TRIM_BROKEN)) ret = mmc_blk_issue_secdiscard_rq(mq, req); else ret = mmc_blk_issue_discard_rq(mq, req); - } else if (cmd_flags & REQ_FLUSH) { + } else if (cmd_flags & (REQ_FLUSH | REQ_BARRIER)) { /* complete ongoing async transfer before issuing flush */ if (card->host->areq) mmc_blk_issue_rw_rq(mq, NULL); @@ -2168,7 +4148,7 @@ } out: - if ((!req && !(mq->flags & MMC_QUEUE_NEW_REQUEST)) || + if ((!req && !(test_bit(MMC_QUEUE_NEW_REQUEST, &mq->flags))) || (cmd_flags & MMC_REQ_SPECIAL_MASK)) /* * Release host when there are no more requests @@ -2238,7 +4218,7 @@ INIT_LIST_HEAD(&md->part); md->usage = 1; - ret = mmc_init_queue(&md->queue, card, &md->lock, subname); + ret = mmc_init_queue(&md->queue, card, NULL, subname, area_type); if (ret) goto err_putdisk; @@ -2252,6 +4232,7 @@ md->disk->queue = md->queue.queue; md->disk->driverfs_dev = parent; set_disk_ro(md->disk, md->read_only || default_ro); + md->disk->flags = GENHD_FL_EXT_DEVT; if (area_type & (MMC_BLK_DATA_AREA_RPMB | MMC_BLK_DATA_AREA_BOOT)) md->disk->flags |= GENHD_FL_NO_PART_SCAN; @@ -2294,7 +4275,16 @@ blk_queue_flush(md->queue.queue, REQ_FLUSH | REQ_FUA); } - if (mmc_card_mmc(card) && + if (card->cmdq_init) { + md->flags |= MMC_BLK_CMD_QUEUE; + md->queue.cmdq_complete_fn = mmc_blk_cmdq_complete_rq; + md->queue.cmdq_issue_fn = mmc_blk_cmdq_issue_rq; + md->queue.cmdq_error_fn = mmc_blk_cmdq_err; + md->queue.cmdq_req_timed_out = mmc_blk_cmdq_req_timed_out; + md->queue.cmdq_shutdown = mmc_blk_cmdq_shutdown; + } + + if (mmc_card_mmc(card) && !card->cmdq_init && (area_type == MMC_BLK_DATA_AREA_MAIN) && (md->flags & MMC_BLK_CMD23) && card->ext_csd.packed_event_en) { @@ -2307,8 +4297,11 @@ err_putdisk: put_disk(md->disk); err_kfree: + if (!subname) + __clear_bit(md->name_idx, name_use); kfree(md); out: + __clear_bit(devidx, dev_use); return ERR_PTR(ret); } @@ -2404,12 +4397,24 @@ mmc_cleanup_queue(&md->queue); if (md->flags & MMC_BLK_PACKED_CMD) mmc_packed_clean(&md->queue); + if (md->flags & MMC_BLK_CMD_QUEUE) + mmc_cmdq_clean(&md->queue, card); + device_remove_file(disk_to_dev(md->disk), + &md->num_wr_reqs_to_start_packing); if (md->disk->flags & GENHD_FL_UP) { device_remove_file(disk_to_dev(md->disk), &md->force_ro); if ((md->area_type & MMC_BLK_DATA_AREA_BOOT) && card->ext_csd.boot_ro_lockable) device_remove_file(disk_to_dev(md->disk), &md->power_ro_lock); +#ifdef CONFIG_MMC_SIMULATE_MAX_SPEED + device_remove_file(disk_to_dev(md->disk), + &dev_attr_max_write_speed); + device_remove_file(disk_to_dev(md->disk), + &dev_attr_max_read_speed); + device_remove_file(disk_to_dev(md->disk), + &dev_attr_cache_size); +#endif del_gendisk(md->disk); } @@ -2445,6 +4450,24 @@ ret = device_create_file(disk_to_dev(md->disk), &md->force_ro); if (ret) goto force_ro_fail; +#ifdef CONFIG_MMC_SIMULATE_MAX_SPEED + atomic_set(&md->queue.max_write_speed, max_write_speed); + ret = device_create_file(disk_to_dev(md->disk), + &dev_attr_max_write_speed); + if (ret) + goto max_write_speed_fail; + atomic_set(&md->queue.max_read_speed, max_read_speed); + ret = device_create_file(disk_to_dev(md->disk), + &dev_attr_max_read_speed); + if (ret) + goto max_read_speed_fail; + atomic_set(&md->queue.cache_size, cache_size); + atomic_long_set(&md->queue.cache_used, 0); + md->queue.cache_jiffies = jiffies; + ret = device_create_file(disk_to_dev(md->disk), &dev_attr_cache_size); + if (ret) + goto cache_size_fail; +#endif if ((md->area_type & MMC_BLK_DATA_AREA_BOOT) && card->ext_csd.boot_ro_lockable) { @@ -2466,9 +4489,46 @@ if (ret) goto power_ro_lock_fail; } + + md->num_wr_reqs_to_start_packing.show = + num_wr_reqs_to_start_packing_show; + md->num_wr_reqs_to_start_packing.store = + num_wr_reqs_to_start_packing_store; + sysfs_attr_init(&md->num_wr_reqs_to_start_packing.attr); + md->num_wr_reqs_to_start_packing.attr.name = + "num_wr_reqs_to_start_packing"; + md->num_wr_reqs_to_start_packing.attr.mode = S_IRUGO | S_IWUSR; + ret = device_create_file(disk_to_dev(md->disk), + &md->num_wr_reqs_to_start_packing); + if (ret) + goto num_wr_reqs_to_start_packing_fail; + + md->no_pack_for_random.show = no_pack_for_random_show; + md->no_pack_for_random.store = no_pack_for_random_store; + sysfs_attr_init(&md->no_pack_for_random.attr); + md->no_pack_for_random.attr.name = "no_pack_for_random"; + md->no_pack_for_random.attr.mode = S_IRUGO | S_IWUSR; + ret = device_create_file(disk_to_dev(md->disk), + &md->no_pack_for_random); + if (ret) + goto no_pack_for_random_fails; + return ret; +no_pack_for_random_fails: + device_remove_file(disk_to_dev(md->disk), + &md->num_wr_reqs_to_start_packing); +num_wr_reqs_to_start_packing_fail: + device_remove_file(disk_to_dev(md->disk), &md->power_ro_lock); power_ro_lock_fail: +#ifdef CONFIG_MMC_SIMULATE_MAX_SPEED + device_remove_file(disk_to_dev(md->disk), &dev_attr_cache_size); +cache_size_fail: + device_remove_file(disk_to_dev(md->disk), &dev_attr_max_read_speed); +max_read_speed_fail: + device_remove_file(disk_to_dev(md->disk), &dev_attr_max_write_speed); +max_write_speed_fail: +#endif device_remove_file(disk_to_dev(md->disk), &md->force_ro); force_ro_fail: del_gendisk(md->disk); @@ -2482,6 +4542,11 @@ #define CID_MANFID_SAMSUNG 0x15 #define CID_MANFID_KINGSTON 0x70 +#define CID_MANFID_SANDISK 0x2 +#define CID_MANFID_TOSHIBA 0x11 +#define CID_MANFID_MICRON 0x13 +#define CID_MANFID_SAMSUNG 0x15 + static const struct mmc_fixup blk_fixups[] = { MMC_FIXUP("SEM02G", CID_MANFID_SANDISK, 0x100, add_quirk, @@ -2513,6 +4578,8 @@ MMC_QUIRK_BLK_NO_CMD23), MMC_FIXUP("MMC32G", CID_MANFID_TOSHIBA, CID_OEMID_ANY, add_quirk_mmc, MMC_QUIRK_BLK_NO_CMD23), + MMC_FIXUP(CID_NAME_ANY, CID_MANFID_TOSHIBA, CID_OEMID_ANY, + add_quirk_mmc, MMC_QUIRK_CMDQ_EMPTY_BEFORE_DCMD), /* * Some MMC cards need longer data read timeout than indicated in CSD. @@ -2523,6 +4590,20 @@ MMC_QUIRK_LONG_READ_TIME), /* + * Some Samsung MMC cards need longer data read timeout than + * indicated in CSD. + */ + MMC_FIXUP("Q7XSAB", CID_MANFID_SAMSUNG, 0x100, add_quirk_mmc, + MMC_QUIRK_LONG_READ_TIME), + + /* + * Hynix eMMC cards need longer data read timeout than + * indicated in CSD. + */ + MMC_FIXUP(CID_NAME_ANY, CID_MANFID_HYNIX, CID_OEMID_ANY, add_quirk_mmc, + MMC_QUIRK_LONG_READ_TIME), + + /* * On these Samsung MoviNAND parts, performing secure erase or * secure trim can result in unrecoverable corruption due to a * firmware bug. @@ -2553,6 +4634,32 @@ MMC_FIXUP("V10016", CID_MANFID_KINGSTON, CID_OEMID_ANY, add_quirk_mmc, MMC_QUIRK_TRIM_BROKEN), + /* Some INAND MCP devices advertise incorrect timeout values */ + MMC_FIXUP("SEM04G", 0x45, CID_OEMID_ANY, add_quirk_mmc, + MMC_QUIRK_INAND_DATA_TIMEOUT), + + /* + * On these Samsung MoviNAND parts, performing secure erase or + * secure trim can result in unrecoverable corruption due to a + * firmware bug. + */ + MMC_FIXUP("M8G2FA", CID_MANFID_SAMSUNG, CID_OEMID_ANY, add_quirk_mmc, + MMC_QUIRK_SEC_ERASE_TRIM_BROKEN), + MMC_FIXUP("MAG4FA", CID_MANFID_SAMSUNG, CID_OEMID_ANY, add_quirk_mmc, + MMC_QUIRK_SEC_ERASE_TRIM_BROKEN), + MMC_FIXUP("MBG8FA", CID_MANFID_SAMSUNG, CID_OEMID_ANY, add_quirk_mmc, + MMC_QUIRK_SEC_ERASE_TRIM_BROKEN), + MMC_FIXUP("MCGAFA", CID_MANFID_SAMSUNG, CID_OEMID_ANY, add_quirk_mmc, + MMC_QUIRK_SEC_ERASE_TRIM_BROKEN), + MMC_FIXUP("VAL00M", CID_MANFID_SAMSUNG, CID_OEMID_ANY, add_quirk_mmc, + MMC_QUIRK_SEC_ERASE_TRIM_BROKEN), + MMC_FIXUP("VYL00M", CID_MANFID_SAMSUNG, CID_OEMID_ANY, add_quirk_mmc, + MMC_QUIRK_SEC_ERASE_TRIM_BROKEN), + MMC_FIXUP("KYL00M", CID_MANFID_SAMSUNG, CID_OEMID_ANY, add_quirk_mmc, + MMC_QUIRK_SEC_ERASE_TRIM_BROKEN), + MMC_FIXUP("VZL00M", CID_MANFID_SAMSUNG, CID_OEMID_ANY, add_quirk_mmc, + MMC_QUIRK_SEC_ERASE_TRIM_BROKEN), + END_FIXUP }; @@ -2584,6 +4691,10 @@ dev_set_drvdata(&card->dev, md); +#ifdef CONFIG_MMC_BLOCK_DEFERRED_RESUME + mmc_set_bus_resume_policy(card->host, 1); +#endif + if (mmc_add_disk(md)) goto out; @@ -2592,7 +4703,8 @@ goto out; } - pm_runtime_set_autosuspend_delay(&card->dev, 3000); + pm_runtime_use_autosuspend(&card->dev); + pm_runtime_set_autosuspend_delay(&card->dev, MMC_AUTOSUSPEND_DELAY_MS); pm_runtime_use_autosuspend(&card->dev); /* @@ -2626,25 +4738,41 @@ pm_runtime_put_noidle(&card->dev); mmc_blk_remove_req(md); dev_set_drvdata(&card->dev, NULL); +#ifdef CONFIG_MMC_BLOCK_DEFERRED_RESUME + mmc_set_bus_resume_policy(card->host, 0); +#endif } -static int _mmc_blk_suspend(struct mmc_card *card) +static int _mmc_blk_suspend(struct mmc_card *card, bool wait) { struct mmc_blk_data *part_md; struct mmc_blk_data *md = dev_get_drvdata(&card->dev); + int rc = 0; if (md) { - mmc_queue_suspend(&md->queue); + rc = mmc_queue_suspend(&md->queue, wait); + if (rc) + goto out; list_for_each_entry(part_md, &md->part, part) { - mmc_queue_suspend(&part_md->queue); + rc = mmc_queue_suspend(&part_md->queue, wait); + if (rc) + goto out_resume; } } - return 0; + goto out; + + out_resume: + mmc_queue_resume(&md->queue); + list_for_each_entry(part_md, &md->part, part) { + mmc_queue_resume(&part_md->queue); + } + out: + return rc; } static void mmc_blk_shutdown(struct mmc_card *card) { - _mmc_blk_suspend(card); + _mmc_blk_suspend(card, 1); } #ifdef CONFIG_PM_SLEEP @@ -2652,7 +4780,7 @@ { struct mmc_card *card = mmc_dev_to_card(dev); - return _mmc_blk_suspend(card); + return _mmc_blk_suspend(card, 0); } static int mmc_blk_resume(struct device *dev) diff -ruw linux-4.4.115/drivers/mmc/card/Kconfig linux-4.4.115-fbx/drivers/mmc/card/Kconfig --- linux-4.4.115/drivers/mmc/card/Kconfig 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/mmc/card/Kconfig 2019-01-22 16:16:24.763257817 +0100 @@ -50,6 +50,17 @@ If unsure, say Y here. +config MMC_BLOCK_DEFERRED_RESUME + bool "Defer MMC layer resume until I/O is requested" + depends on MMC_BLOCK + default n + help + Say Y here to enable deferred MMC resume until I/O + is requested. + + This will reduce overall resume latency and + save power when there is an SD card inserted but not being used. + config SDIO_UART tristate "SDIO UART/GPS class support" depends on TTY @@ -68,3 +79,15 @@ This driver is only of interest to those developing or testing a host driver. Most people should say N here. + +config MMC_SIMULATE_MAX_SPEED + bool "Turn on maximum speed control per block device" + depends on MMC_BLOCK + help + Say Y here to enable MMC device speed limiting. Used to test and + simulate the behavior of the system when confronted with a slow MMC. + + Enables max_read_speed, max_write_speed and cache_size attributes to + control the write or read maximum KB/second speed behaviors. + + If unsure, say N here. diff -ruw linux-4.4.115/drivers/mmc/card/Makefile linux-4.4.115-fbx/drivers/mmc/card/Makefile --- linux-4.4.115/drivers/mmc/card/Makefile 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/mmc/card/Makefile 2019-01-22 16:16:24.763257817 +0100 @@ -8,3 +8,4 @@ obj-$(CONFIG_SDIO_UART) += sdio_uart.o +obj-$(CONFIG_MMC_BLOCK_TEST) += mmc_block_test.o diff -ruw linux-4.4.115/drivers/mmc/card/queue.c linux-4.4.115-fbx/drivers/mmc/card/queue.c --- linux-4.4.115/drivers/mmc/card/queue.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/mmc/card/queue.c 2019-10-29 09:26:24.053207190 +0100 @@ -16,14 +16,24 @@ #include #include #include +#include +#include #include #include +#include #include "queue.h" #define MMC_QUEUE_BOUNCESZ 65536 /* + * Based on benchmark tests the default num of requests to trigger the write + * packing was determined, to keep the read latency as low as possible and + * manage to keep the high write throughput. + */ +#define DEFAULT_NUM_REQS_TO_START_PACK 17 + +/* * Prepare a MMC request. This just filters out odd stuff. */ static int mmc_prep_request(struct request_queue *q, struct request *req) @@ -46,12 +56,102 @@ return BLKPREP_OK; } +static struct request *mmc_peek_request(struct mmc_queue *mq) +{ + struct request_queue *q = mq->queue; + mq->cmdq_req_peeked = NULL; + + spin_lock_irq(q->queue_lock); + if (!blk_queue_stopped(q)) + mq->cmdq_req_peeked = blk_peek_request(q); + spin_unlock_irq(q->queue_lock); + + return mq->cmdq_req_peeked; +} + +static bool mmc_check_blk_queue_start_tag(struct request_queue *q, + struct request *req) +{ + int ret; + + spin_lock_irq(q->queue_lock); + ret = blk_queue_start_tag(q, req); + spin_unlock_irq(q->queue_lock); + + return !!ret; +} + +static inline void mmc_cmdq_ready_wait(struct mmc_host *host, + struct mmc_queue *mq) +{ + struct mmc_cmdq_context_info *ctx = &host->cmdq_ctx; + struct request_queue *q = mq->queue; + + /* + * Wait until all of the following conditions are true: + * 1. There is a request pending in the block layer queue + * to be processed. + * 2. If the peeked request is flush/discard then there shouldn't + * be any other direct command active. + * 3. cmdq state should be unhalted. + * 4. cmdq state shouldn't be in error state. + * 5. free tag available to process the new request. + */ + wait_event(ctx->wait, kthread_should_stop() + || (mmc_peek_request(mq) && + !((mq->cmdq_req_peeked->cmd_flags & (REQ_FLUSH | REQ_DISCARD)) + && test_bit(CMDQ_STATE_DCMD_ACTIVE, &ctx->curr_state)) + && !(!host->card->part_curr && !mmc_card_suspended(host->card) + && mmc_host_halt(host)) + && !(!host->card->part_curr && mmc_host_cq_disable(host) && + !mmc_card_suspended(host->card)) + && !test_bit(CMDQ_STATE_ERR, &ctx->curr_state) + && !mmc_check_blk_queue_start_tag(q, mq->cmdq_req_peeked))); +} + +static int mmc_cmdq_thread(void *d) +{ + struct mmc_queue *mq = d; + struct mmc_card *card = mq->card; + struct mmc_host *host = card->host; + + current->flags |= PF_MEMALLOC; + if (card->host->wakeup_on_idle) + set_wake_up_idle(true); + + while (1) { + int ret = 0; + + mmc_cmdq_ready_wait(host, mq); + if (kthread_should_stop()) + break; + + ret = mq->cmdq_issue_fn(mq, mq->cmdq_req_peeked); + /* + * Don't requeue if issue_fn fails. + * Recovery will be come by completion softirq + * Also we end the request if there is a partition switch error, + * so we should not requeue the request here. + */ + } /* loop */ + + return 0; +} + static int mmc_queue_thread(void *d) { struct mmc_queue *mq = d; struct request_queue *q = mq->queue; + struct mmc_card *card = mq->card; + struct sched_param scheduler_params = {0}; + + scheduler_params.sched_priority = 1; + + sched_setscheduler(current, SCHED_FIFO, &scheduler_params); current->flags |= PF_MEMALLOC; + if (card->host->wakeup_on_idle) + set_wake_up_idle(true); down(&mq->thread_sem); do { @@ -69,8 +169,8 @@ cmd_flags = req ? req->cmd_flags : 0; mq->issue_fn(mq, req); cond_resched(); - if (mq->flags & MMC_QUEUE_NEW_REQUEST) { - mq->flags &= ~MMC_QUEUE_NEW_REQUEST; + if (test_bit(MMC_QUEUE_NEW_REQUEST, &mq->flags)) { + clear_bit(MMC_QUEUE_NEW_REQUEST, &mq->flags); continue; /* fetch again */ } @@ -102,6 +202,13 @@ return 0; } +static void mmc_cmdq_dispatch_req(struct request_queue *q) +{ + struct mmc_queue *mq = q->queuedata; + + wake_up(&mq->card->host->cmdq_ctx.wait); +} + /* * Generic MMC request handler. This is called for any queue on a * particular host. When the host is not busy, we look for a request @@ -177,6 +284,32 @@ } /** + * mmc_blk_cmdq_setup_queue + * @mq: mmc queue + * @card: card to attach to this queue + * + * Setup queue for CMDQ supporting MMC card + */ +void mmc_cmdq_setup_queue(struct mmc_queue *mq, struct mmc_card *card) +{ + u64 limit = BLK_BOUNCE_HIGH; + struct mmc_host *host = card->host; + + if (mmc_dev(host)->dma_mask && *mmc_dev(host)->dma_mask) + limit = *mmc_dev(host)->dma_mask; + + queue_flag_set_unlocked(QUEUE_FLAG_NONROT, mq->queue); + if (mmc_can_erase(card)) + mmc_queue_setup_discard(mq->queue, card); + + blk_queue_bounce_limit(mq->queue, limit); + blk_queue_max_hw_sectors(mq->queue, min(host->max_blk_count, + host->max_req_size / 512)); + blk_queue_max_segment_size(mq->queue, host->max_seg_size); + blk_queue_max_segments(mq->queue, host->max_segs); +} + +/** * mmc_init_queue - initialise a queue structure. * @mq: mmc queue * @card: mmc card to attach this queue @@ -186,7 +319,7 @@ * Initialise a MMC card request queue. */ int mmc_init_queue(struct mmc_queue *mq, struct mmc_card *card, - spinlock_t *lock, const char *subname) + spinlock_t *lock, const char *subname, int area_type) { struct mmc_host *host = card->host; u64 limit = BLK_BOUNCE_HIGH; @@ -198,6 +331,37 @@ limit = (u64)dma_max_pfn(mmc_dev(host)) << PAGE_SHIFT; mq->card = card; + if (card->ext_csd.cmdq_support && + (area_type == MMC_BLK_DATA_AREA_MAIN)) { + mq->queue = blk_init_queue(mmc_cmdq_dispatch_req, lock); + if (!mq->queue) + return -ENOMEM; + mmc_cmdq_setup_queue(mq, card); + ret = mmc_cmdq_init(mq, card); + if (ret) { + pr_err("%s: %d: cmdq: unable to set-up\n", + mmc_hostname(card->host), ret); + blk_cleanup_queue(mq->queue); + } else { + sema_init(&mq->thread_sem, 1); + /* hook for pm qos cmdq init */ + if (card->host->cmdq_ops->init) + card->host->cmdq_ops->init(card->host); + mq->queue->queuedata = mq; + mq->thread = kthread_run(mmc_cmdq_thread, mq, + "mmc-cmdqd/%d%s", + host->index, + subname ? subname : ""); + if (IS_ERR(mq->thread)) { + pr_err("%s: %d: cmdq: failed to start mmc-cmdqd thread\n", + mmc_hostname(card->host), ret); + ret = PTR_ERR(mq->thread); + } + + return ret; + } + } + mq->queue = blk_init_queue(mmc_request_fn, lock); if (!mq->queue) return -ENOMEM; @@ -205,6 +369,9 @@ mq->mqrq_cur = mqrq_cur; mq->mqrq_prev = mqrq_prev; mq->queue->queuedata = mq; + mq->num_wr_reqs_to_start_packing = + min_t(int, (int)card->ext_csd.max_packed_writes, + DEFAULT_NUM_REQS_TO_START_PACK); blk_queue_prep_rq(mq->queue, mmc_prep_request); queue_flag_set_unlocked(QUEUE_FLAG_NONROT, mq->queue); @@ -270,24 +437,49 @@ #endif if (!mqrq_cur->bounce_buf && !mqrq_prev->bounce_buf) { + unsigned int max_segs = host->max_segs; + blk_queue_bounce_limit(mq->queue, limit); blk_queue_max_hw_sectors(mq->queue, min(host->max_blk_count, host->max_req_size / 512)); - blk_queue_max_segments(mq->queue, host->max_segs); blk_queue_max_segment_size(mq->queue, host->max_seg_size); +retry: + blk_queue_max_segments(mq->queue, host->max_segs); mqrq_cur->sg = mmc_alloc_sg(host->max_segs, &ret); - if (ret) + if (ret == -ENOMEM) + goto cur_sg_alloc_failed; + else if (ret) goto cleanup_queue; - mqrq_prev->sg = mmc_alloc_sg(host->max_segs, &ret); - if (ret) + if (ret == -ENOMEM) + goto prev_sg_alloc_failed; + else if (ret) + goto cleanup_queue; + + goto success; + +prev_sg_alloc_failed: + kfree(mqrq_cur->sg); + mqrq_cur->sg = NULL; +cur_sg_alloc_failed: + host->max_segs /= 2; + if (host->max_segs) { + goto retry; + } else { + host->max_segs = max_segs; goto cleanup_queue; } + } +success: sema_init(&mq->thread_sem, 1); + /* hook for pm qos legacy init */ + if (card->host->ops->init) + card->host->ops->init(card->host); + mq->thread = kthread_run(mmc_queue_thread, mq, "mmcqd/%d%s", host->index, subname ? subname : ""); @@ -402,29 +594,193 @@ mqrq_prev->packed = NULL; } +static void mmc_cmdq_softirq_done(struct request *rq) +{ + struct mmc_queue *mq = rq->q->queuedata; + mq->cmdq_complete_fn(rq); +} + +static void mmc_cmdq_error_work(struct work_struct *work) +{ + struct mmc_queue *mq = container_of(work, struct mmc_queue, + cmdq_err_work); + + mq->cmdq_error_fn(mq); +} + +enum blk_eh_timer_return mmc_cmdq_rq_timed_out(struct request *req) +{ + struct mmc_queue *mq = req->q->queuedata; + + pr_err("%s: request with tag: %d flags: 0x%llx timed out\n", + mmc_hostname(mq->card->host), req->tag, req->cmd_flags); + + return mq->cmdq_req_timed_out(req); +} + +int mmc_cmdq_init(struct mmc_queue *mq, struct mmc_card *card) +{ + int i, ret = 0; + /* one slot is reserved for dcmd requests */ + int q_depth = card->ext_csd.cmdq_depth - 1; + + card->cmdq_init = false; + if (!(card->host->caps2 & MMC_CAP2_CMD_QUEUE)) { + ret = -ENOTSUPP; + goto out; + } + + init_waitqueue_head(&card->host->cmdq_ctx.queue_empty_wq); + init_waitqueue_head(&card->host->cmdq_ctx.wait); + + mq->mqrq_cmdq = kzalloc( + sizeof(struct mmc_queue_req) * q_depth, GFP_KERNEL); + if (!mq->mqrq_cmdq) { + pr_warn("%s: unable to allocate mqrq's for q_depth %d\n", + mmc_card_name(card), q_depth); + ret = -ENOMEM; + goto out; + } + + /* sg is allocated for data request slots only */ + for (i = 0; i < q_depth; i++) { + mq->mqrq_cmdq[i].sg = mmc_alloc_sg(card->host->max_segs, &ret); + if (ret) { + pr_warn("%s: unable to allocate cmdq sg of size %d\n", + mmc_card_name(card), + card->host->max_segs); + goto free_mqrq_sg; + } + } + + ret = blk_queue_init_tags(mq->queue, q_depth, NULL, BLK_TAG_ALLOC_FIFO); + if (ret) { + pr_warn("%s: unable to allocate cmdq tags %d\n", + mmc_card_name(card), q_depth); + goto free_mqrq_sg; + } + + blk_queue_softirq_done(mq->queue, mmc_cmdq_softirq_done); + INIT_WORK(&mq->cmdq_err_work, mmc_cmdq_error_work); + init_completion(&mq->cmdq_shutdown_complete); + init_completion(&mq->cmdq_pending_req_done); + + blk_queue_rq_timed_out(mq->queue, mmc_cmdq_rq_timed_out); + blk_queue_rq_timeout(mq->queue, 120 * HZ); + card->cmdq_init = true; + + goto out; + +free_mqrq_sg: + for (i = 0; i < q_depth; i++) + kfree(mq->mqrq_cmdq[i].sg); + kfree(mq->mqrq_cmdq); + mq->mqrq_cmdq = NULL; +out: + return ret; +} + +void mmc_cmdq_clean(struct mmc_queue *mq, struct mmc_card *card) +{ + int i; + int q_depth = card->ext_csd.cmdq_depth - 1; + + blk_free_tags(mq->queue->queue_tags); + mq->queue->queue_tags = NULL; + blk_queue_free_tags(mq->queue); + + for (i = 0; i < q_depth; i++) + kfree(mq->mqrq_cmdq[i].sg); + kfree(mq->mqrq_cmdq); + mq->mqrq_cmdq = NULL; +} + /** * mmc_queue_suspend - suspend a MMC request queue * @mq: MMC queue to suspend + * @wait: Wait till MMC request queue is empty * * Stop the block request queue, and wait for our thread to * complete any outstanding requests. This ensures that we * won't suspend while a request is being processed. */ -void mmc_queue_suspend(struct mmc_queue *mq) +int mmc_queue_suspend(struct mmc_queue *mq, int wait) { struct request_queue *q = mq->queue; unsigned long flags; + int rc = 0; + struct mmc_card *card = mq->card; + struct request *req; + + if (card->cmdq_init && blk_queue_tagged(q)) { + struct mmc_host *host = card->host; + + if (test_and_set_bit(MMC_QUEUE_SUSPENDED, &mq->flags)) + goto out; + + if (wait) { + + /* + * After blk_cleanup_queue is called, wait for all + * active_reqs to complete. + * Then wait for cmdq thread to exit before calling + * cmdq shutdown to avoid race between issuing + * requests and shutdown of cmdq. + */ + blk_cleanup_queue(q); - if (!(mq->flags & MMC_QUEUE_SUSPENDED)) { - mq->flags |= MMC_QUEUE_SUSPENDED; + if (host->cmdq_ctx.active_reqs) + wait_for_completion( + &mq->cmdq_shutdown_complete); + kthread_stop(mq->thread); + mq->cmdq_shutdown(mq); + } else { + spin_lock_irqsave(q->queue_lock, flags); + blk_stop_queue(q); + wake_up(&host->cmdq_ctx.wait); + req = blk_peek_request(q); + if (req || mq->cmdq_req_peeked || + host->cmdq_ctx.active_reqs) { + clear_bit(MMC_QUEUE_SUSPENDED, &mq->flags); + blk_start_queue(q); + rc = -EBUSY; + } + spin_unlock_irqrestore(q->queue_lock, flags); + } + + goto out; + } + if (!(test_and_set_bit(MMC_QUEUE_SUSPENDED, &mq->flags))) { + if (!wait) { + /* suspend/stop the queue in case of suspend */ spin_lock_irqsave(q->queue_lock, flags); blk_stop_queue(q); spin_unlock_irqrestore(q->queue_lock, flags); + } else { + /* shutdown the queue in case of shutdown/reboot */ + blk_cleanup_queue(q); + } + rc = down_trylock(&mq->thread_sem); + if (rc && !wait) { + /* + * Failed to take the lock so better to abort the + * suspend because mmcqd thread is processing requests. + */ + clear_bit(MMC_QUEUE_SUSPENDED, &mq->flags); + spin_lock_irqsave(q->queue_lock, flags); + blk_start_queue(q); + spin_unlock_irqrestore(q->queue_lock, flags); + rc = -EBUSY; + } else if (rc && wait) { down(&mq->thread_sem); + rc = 0; } } +out: + return rc; +} /** * mmc_queue_resume - resume a previously suspended MMC request queue @@ -433,11 +789,12 @@ void mmc_queue_resume(struct mmc_queue *mq) { struct request_queue *q = mq->queue; + struct mmc_card *card = mq->card; unsigned long flags; - if (mq->flags & MMC_QUEUE_SUSPENDED) { - mq->flags &= ~MMC_QUEUE_SUSPENDED; + if (test_and_clear_bit(MMC_QUEUE_SUSPENDED, &mq->flags)) { + if (!(card->cmdq_init && blk_queue_tagged(q))) up(&mq->thread_sem); spin_lock_irqsave(q->queue_lock, flags); diff -ruw linux-4.4.115/drivers/mmc/card/queue.h linux-4.4.115-fbx/drivers/mmc/card/queue.h --- linux-4.4.115/drivers/mmc/card/queue.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/mmc/card/queue.h 2019-01-22 16:16:24.763257817 +0100 @@ -42,28 +42,55 @@ struct mmc_async_req mmc_active; enum mmc_packed_type cmd_type; struct mmc_packed *packed; + struct mmc_cmdq_req cmdq_req; }; struct mmc_queue { struct mmc_card *card; struct task_struct *thread; struct semaphore thread_sem; - unsigned int flags; -#define MMC_QUEUE_SUSPENDED (1 << 0) -#define MMC_QUEUE_NEW_REQUEST (1 << 1) + unsigned long flags; +#define MMC_QUEUE_SUSPENDED 0 +#define MMC_QUEUE_NEW_REQUEST 1 int (*issue_fn)(struct mmc_queue *, struct request *); + int (*cmdq_issue_fn)(struct mmc_queue *, + struct request *); + void (*cmdq_complete_fn)(struct request *); + void (*cmdq_error_fn)(struct mmc_queue *); + enum blk_eh_timer_return (*cmdq_req_timed_out)(struct request *); void *data; struct request_queue *queue; struct mmc_queue_req mqrq[2]; struct mmc_queue_req *mqrq_cur; struct mmc_queue_req *mqrq_prev; + struct mmc_queue_req *mqrq_cmdq; + bool wr_packing_enabled; + int num_of_potential_packed_wr_reqs; + int num_wr_reqs_to_start_packing; + bool no_pack_for_random; + struct work_struct cmdq_err_work; + + struct completion cmdq_pending_req_done; + struct completion cmdq_shutdown_complete; + struct request *cmdq_req_peeked; + int (*err_check_fn) (struct mmc_card *, struct mmc_async_req *); + void (*packed_test_fn) (struct request_queue *, struct mmc_queue_req *); + void (*cmdq_shutdown)(struct mmc_queue *); +#ifdef CONFIG_MMC_SIMULATE_MAX_SPEED + atomic_t max_write_speed; + atomic_t max_read_speed; + atomic_t cache_size; + /* i/o tracking */ + atomic_long_t cache_used; + unsigned long cache_jiffies; +#endif }; extern int mmc_init_queue(struct mmc_queue *, struct mmc_card *, spinlock_t *, - const char *); + const char *, int); extern void mmc_cleanup_queue(struct mmc_queue *); -extern void mmc_queue_suspend(struct mmc_queue *); +extern int mmc_queue_suspend(struct mmc_queue *, int); extern void mmc_queue_resume(struct mmc_queue *); extern unsigned int mmc_queue_map_sg(struct mmc_queue *, @@ -76,4 +103,9 @@ extern int mmc_access_rpmb(struct mmc_queue *); +extern void print_mmc_packing_stats(struct mmc_card *card); + +extern int mmc_cmdq_init(struct mmc_queue *mq, struct mmc_card *card); +extern void mmc_cmdq_clean(struct mmc_queue *mq, struct mmc_card *card); + #endif diff -ruw linux-4.4.115/drivers/mmc/core/bus.c linux-4.4.115-fbx/drivers/mmc/core/bus.c --- linux-4.4.115/drivers/mmc/core/bus.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/mmc/core/bus.c 2019-10-29 09:26:24.057207230 +0100 @@ -132,6 +132,16 @@ struct mmc_host *host = card->host; int ret; + if (!drv) { + pr_debug("%s: %s: drv is NULL\n", dev_name(dev), __func__); + return; + } + + if (!card) { + pr_debug("%s: %s: card is NULL\n", dev_name(dev), __func__); + return; + } + if (dev->driver && drv->shutdown) drv->shutdown(card); @@ -154,10 +164,22 @@ if (ret) return ret; + if (mmc_bus_needs_resume(host)) + return 0; ret = host->bus_ops->suspend(host); + + /* + * bus_ops->suspend may fail due to some reason + * In such cases if we return error to PM framework + * from here without calling pm_generic_resume then mmc + * request may get stuck since PM framework will assume + * that mmc bus is not suspended (because of error) and + * it won't call resume again. + * + * So in case of error call pm_generic_resume(). + */ if (ret) pm_generic_resume(dev); - return ret; } @@ -167,11 +189,17 @@ struct mmc_host *host = card->host; int ret; + if (mmc_bus_manual_resume(host)) { + host->bus_resume_flags |= MMC_BUSRESUME_NEEDS_RESUME; + goto skip_full_resume; + } + ret = host->bus_ops->resume(host); if (ret) pr_warn("%s: error %d during resume (card was removed?)\n", mmc_hostname(host), ret); +skip_full_resume: ret = pm_generic_resume(dev); return ret; } @@ -183,6 +211,9 @@ struct mmc_card *card = mmc_dev_to_card(dev); struct mmc_host *host = card->host; + if (mmc_bus_needs_resume(host)) + return 0; + return host->bus_ops->runtime_suspend(host); } @@ -191,8 +222,12 @@ struct mmc_card *card = mmc_dev_to_card(dev); struct mmc_host *host = card->host; + if (mmc_bus_needs_resume(host)) + host->bus_resume_flags &= ~MMC_BUSRESUME_NEEDS_RESUME; + return host->bus_ops->runtime_resume(host); } + #endif /* !CONFIG_PM */ static const struct dev_pm_ops mmc_bus_pm_ops = { @@ -276,6 +311,9 @@ card->dev.release = mmc_release_card; card->dev.type = type; + spin_lock_init(&card->wr_pack_stats.lock); + spin_lock_init(&card->bkops.stats.lock); + return card; } @@ -352,11 +390,18 @@ card->dev.of_node = mmc_of_find_child_device(card->host, 0); + if (mmc_card_sdio(card)) { + ret = device_init_wakeup(&card->dev, true); + if (ret) + pr_err("%s: %s: failed to init wakeup: %d\n", + mmc_hostname(card->host), __func__, ret); + } ret = device_add(&card->dev); if (ret) return ret; mmc_card_set_present(card); + device_enable_async_suspend(&card->dev); return 0; } @@ -383,6 +428,8 @@ of_node_put(card->dev.of_node); } + kfree(card->wr_pack_stats.packing_events); + put_device(&card->dev); } diff -ruw linux-4.4.115/drivers/mmc/core/bus.h linux-4.4.115-fbx/drivers/mmc/core/bus.h --- linux-4.4.115/drivers/mmc/core/bus.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/mmc/core/bus.h 2019-01-22 16:16:24.767257853 +0100 @@ -15,7 +15,7 @@ static ssize_t mmc_##name##_show (struct device *dev, struct device_attribute *attr, char *buf) \ { \ struct mmc_card *card = mmc_dev_to_card(dev); \ - return sprintf(buf, fmt, args); \ + return snprintf(buf, PAGE_SIZE, fmt, args); \ } \ static DEVICE_ATTR(name, S_IRUGO, mmc_##name##_show, NULL) diff -ruw linux-4.4.115/drivers/mmc/core/core.c linux-4.4.115-fbx/drivers/mmc/core/core.c --- linux-4.4.115/drivers/mmc/core/core.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/mmc/core/core.c 2019-10-29 09:26:24.057207230 +0100 @@ -14,6 +14,7 @@ #include #include #include +#include #include #include #include @@ -29,6 +30,11 @@ #include #include #include +#include +#include + +#define CREATE_TRACE_POINTS +#include #include #include @@ -46,6 +52,11 @@ #include "sd_ops.h" #include "sdio_ops.h" +EXPORT_TRACEPOINT_SYMBOL_GPL(mmc_blk_erase_start); +EXPORT_TRACEPOINT_SYMBOL_GPL(mmc_blk_erase_end); +EXPORT_TRACEPOINT_SYMBOL_GPL(mmc_blk_rw_start); +EXPORT_TRACEPOINT_SYMBOL_GPL(mmc_blk_rw_end); + /* If the device is not responding */ #define MMC_CORE_TIMEOUT_MS (10 * 60 * 1000) /* 10 minute timeout */ @@ -109,6 +120,7 @@ data->error = data_errors[prandom_u32() % ARRAY_SIZE(data_errors)]; data->bytes_xfered = (prandom_u32() % (data->bytes_xfered >> 9)) << 9; + data->fault_injected = true; } #else /* CONFIG_FAIL_MMC_REQUEST */ @@ -120,6 +132,816 @@ #endif /* CONFIG_FAIL_MMC_REQUEST */ +static bool mmc_is_data_request(struct mmc_request *mmc_request) +{ + switch (mmc_request->cmd->opcode) { + case MMC_READ_SINGLE_BLOCK: + case MMC_READ_MULTIPLE_BLOCK: + case MMC_WRITE_BLOCK: + case MMC_WRITE_MULTIPLE_BLOCK: + return true; + default: + return false; + } +} + +static void mmc_clk_scaling_start_busy(struct mmc_host *host, bool lock_needed) +{ + struct mmc_devfeq_clk_scaling *clk_scaling = &host->clk_scaling; + + if (!clk_scaling->enable) + return; + + if (lock_needed) + spin_lock_bh(&clk_scaling->lock); + + clk_scaling->start_busy = ktime_get(); + clk_scaling->is_busy_started = true; + + if (lock_needed) + spin_unlock_bh(&clk_scaling->lock); +} + +static void mmc_clk_scaling_stop_busy(struct mmc_host *host, bool lock_needed) +{ + struct mmc_devfeq_clk_scaling *clk_scaling = &host->clk_scaling; + + if (!clk_scaling->enable) + return; + + if (lock_needed) + spin_lock_bh(&clk_scaling->lock); + + if (!clk_scaling->is_busy_started) { + WARN_ON(1); + goto out; + } + + clk_scaling->total_busy_time_us += + ktime_to_us(ktime_sub(ktime_get(), + clk_scaling->start_busy)); + pr_debug("%s: accumulated busy time is %lu usec\n", + mmc_hostname(host), clk_scaling->total_busy_time_us); + clk_scaling->is_busy_started = false; + +out: + if (lock_needed) + spin_unlock_bh(&clk_scaling->lock); +} + +/** + * mmc_cmdq_clk_scaling_start_busy() - start busy timer for data requests + * @host: pointer to mmc host structure + * @lock_needed: flag indication if locking is needed + * + * This function starts the busy timer in case it was not already started. + */ +void mmc_cmdq_clk_scaling_start_busy(struct mmc_host *host, + bool lock_needed) +{ + if (!host->clk_scaling.enable) + return; + + if (lock_needed) + spin_lock_bh(&host->clk_scaling.lock); + + if (!host->clk_scaling.is_busy_started && + !test_bit(CMDQ_STATE_DCMD_ACTIVE, + &host->cmdq_ctx.curr_state)) { + host->clk_scaling.start_busy = ktime_get(); + host->clk_scaling.is_busy_started = true; + } + + if (lock_needed) + spin_unlock_bh(&host->clk_scaling.lock); +} +EXPORT_SYMBOL(mmc_cmdq_clk_scaling_start_busy); + +/** + * mmc_cmdq_clk_scaling_stop_busy() - stop busy timer for last data requests + * @host: pointer to mmc host structure + * @lock_needed: flag indication if locking is needed + * + * This function stops the busy timer in case it is the last data request. + * In case the current request is not the last one, the busy time till + * now will be accumulated and the counter will be restarted. + */ +void mmc_cmdq_clk_scaling_stop_busy(struct mmc_host *host, + bool lock_needed, bool is_cmdq_dcmd) +{ + if (!host->clk_scaling.enable) + return; + + if (lock_needed) + spin_lock_bh(&host->clk_scaling.lock); + + /* + * For CQ mode: In completion of DCMD request, start busy time in + * case of pending data requests + */ + if (is_cmdq_dcmd) { + if (host->cmdq_ctx.data_active_reqs) { + host->clk_scaling.is_busy_started = true; + host->clk_scaling.start_busy = ktime_get(); + } + goto out; + } + + host->clk_scaling.total_busy_time_us += + ktime_to_us(ktime_sub(ktime_get(), + host->clk_scaling.start_busy)); + + if (host->cmdq_ctx.data_active_reqs) { + host->clk_scaling.is_busy_started = true; + host->clk_scaling.start_busy = ktime_get(); + } else { + host->clk_scaling.is_busy_started = false; + } +out: + if (lock_needed) + spin_unlock_bh(&host->clk_scaling.lock); + +} +EXPORT_SYMBOL(mmc_cmdq_clk_scaling_stop_busy); + +/** + * mmc_can_scale_clk() - Check clock scaling capability + * @host: pointer to mmc host structure + */ +bool mmc_can_scale_clk(struct mmc_host *host) +{ + if (!host) { + pr_err("bad host parameter\n"); + WARN_ON(1); + return false; + } + + return host->caps2 & MMC_CAP2_CLK_SCALE; +} +EXPORT_SYMBOL(mmc_can_scale_clk); + +static int mmc_devfreq_get_dev_status(struct device *dev, + struct devfreq_dev_status *status) +{ + struct mmc_host *host = container_of(dev, struct mmc_host, class_dev); + struct mmc_devfeq_clk_scaling *clk_scaling; + + if (!host) { + pr_err("bad host parameter\n"); + WARN_ON(1); + return -EINVAL; + } + + clk_scaling = &host->clk_scaling; + + if (!clk_scaling->enable) + return 0; + + spin_lock_bh(&clk_scaling->lock); + + /* accumulate the busy time of ongoing work */ + memset(status, 0, sizeof(*status)); + if (clk_scaling->is_busy_started) { + if (mmc_card_cmdq(host->card)) { + /* the "busy-timer" will be restarted in case there + * are pending data requests */ + mmc_cmdq_clk_scaling_stop_busy(host, false, false); + } else { + mmc_clk_scaling_stop_busy(host, false); + mmc_clk_scaling_start_busy(host, false); + } + } + + status->busy_time = clk_scaling->total_busy_time_us; + status->total_time = ktime_to_us(ktime_sub(ktime_get(), + clk_scaling->measure_interval_start)); + clk_scaling->total_busy_time_us = 0; + status->current_frequency = clk_scaling->curr_freq; + clk_scaling->measure_interval_start = ktime_get(); + + pr_debug("%s: status: load = %lu%% - total_time=%lu busy_time = %lu, clk=%lu\n", + mmc_hostname(host), + (status->busy_time*100)/status->total_time, + status->total_time, status->busy_time, + status->current_frequency); + + spin_unlock_bh(&clk_scaling->lock); + + return 0; +} + +static bool mmc_is_valid_state_for_clk_scaling(struct mmc_host *host) +{ + struct mmc_card *card = host->card; + u32 status; + + /* + * If the current partition type is RPMB, clock switching may not + * work properly as sending tuning command (CMD21) is illegal in + * this mode. + */ + if (!card || (mmc_card_mmc(card) && + (card->part_curr == EXT_CSD_PART_CONFIG_ACC_RPMB || + mmc_card_doing_bkops(card)))) + return false; + + if (mmc_send_status(card, &status)) { + pr_err("%s: Get card status fail\n", mmc_hostname(card->host)); + return false; + } + + return R1_CURRENT_STATE(status) == R1_STATE_TRAN; +} + +int mmc_cmdq_halt_on_empty_queue(struct mmc_host *host) +{ + int err = 0; + + err = wait_event_interruptible(host->cmdq_ctx.queue_empty_wq, + (!host->cmdq_ctx.active_reqs)); + if (host->cmdq_ctx.active_reqs) { + pr_err("%s: %s: unexpected active requests (%lu)\n", + mmc_hostname(host), __func__, + host->cmdq_ctx.active_reqs); + return -EPERM; + } + + err = mmc_cmdq_halt(host, true); + if (err) { + pr_err("%s: %s: mmc_cmdq_halt failed (%d)\n", + mmc_hostname(host), __func__, err); + goto out; + } + +out: + return err; +} +EXPORT_SYMBOL(mmc_cmdq_halt_on_empty_queue); + +int mmc_clk_update_freq(struct mmc_host *host, + unsigned long freq, enum mmc_load state) +{ + int err = 0; + bool cmdq_mode; + + if (!host) { + pr_err("bad host parameter\n"); + WARN_ON(1); + return -EINVAL; + } + + mmc_host_clk_hold(host); + cmdq_mode = mmc_card_cmdq(host->card); + + /* make sure the card supports the frequency we want */ + if (unlikely(freq > host->card->clk_scaling_highest)) { + freq = host->card->clk_scaling_highest; + pr_warn("%s: %s: frequency was overridden to %lu\n", + mmc_hostname(host), __func__, + host->card->clk_scaling_highest); + } + + if (unlikely(freq < host->card->clk_scaling_lowest)) { + freq = host->card->clk_scaling_lowest; + pr_warn("%s: %s: frequency was overridden to %lu\n", + mmc_hostname(host), __func__, + host->card->clk_scaling_lowest); + } + + if (freq == host->clk_scaling.curr_freq) + goto out; + + if (host->ops->notify_load) { + err = host->ops->notify_load(host, state); + if (err) { + pr_err("%s: %s: fail on notify_load\n", + mmc_hostname(host), __func__); + goto out; + } + } + + if (cmdq_mode) { + err = mmc_cmdq_halt_on_empty_queue(host); + if (err) { + pr_err("%s: %s: failed halting queue (%d)\n", + mmc_hostname(host), __func__, err); + goto halt_failed; + } + } + + if (!mmc_is_valid_state_for_clk_scaling(host)) { + pr_debug("%s: invalid state for clock scaling - skipping", + mmc_hostname(host)); + goto invalid_state; + } + + err = host->bus_ops->change_bus_speed(host, &freq); + if (!err) + host->clk_scaling.curr_freq = freq; + else + pr_err("%s: %s: failed (%d) at freq=%lu\n", + mmc_hostname(host), __func__, err, freq); + +invalid_state: + if (cmdq_mode) { + if (mmc_cmdq_halt(host, false)) + pr_err("%s: %s: cmdq unhalt failed\n", + mmc_hostname(host), __func__); + } + +halt_failed: + if (err) { + /* restore previous state */ + if (host->ops->notify_load) + if (host->ops->notify_load(host, + host->clk_scaling.state)) + pr_err("%s: %s: fail on notify_load restore\n", + mmc_hostname(host), __func__); + } +out: + mmc_host_clk_release(host); + return err; +} +EXPORT_SYMBOL(mmc_clk_update_freq); + +int mmc_recovery_fallback_lower_speed(struct mmc_host *host) +{ + int err = 0; + if (!host->card) + return -EINVAL; + + if (host->sdr104_wa && mmc_card_sd(host->card) && + (host->ios.timing == MMC_TIMING_UHS_SDR104) && + !host->card->sdr104_blocked) { + pr_err("%s: %s: blocked SDR104, lower the bus-speed (SDR50 / DDR50)\n", + mmc_hostname(host), __func__); + mmc_host_clear_sdr104(host); + err = mmc_hw_reset(host); + host->card->sdr104_blocked = true; + } else { + /* If sdr104_wa is not present, just return status */ + err = host->bus_ops->alive(host); + } + if (err) + pr_err("%s: %s: Fallback to lower speed mode failed with err=%d\n", + mmc_hostname(host), __func__, err); + + return err; +} + +static int mmc_devfreq_set_target(struct device *dev, + unsigned long *freq, u32 devfreq_flags) +{ + struct mmc_host *host = container_of(dev, struct mmc_host, class_dev); + struct mmc_devfeq_clk_scaling *clk_scaling; + int err = 0; + int abort; + unsigned long pflags = current->flags; + + /* Ensure scaling would happen even in memory pressure conditions */ + current->flags |= PF_MEMALLOC; + + if (!(host && freq)) { + pr_err("%s: unexpected host/freq parameter\n", __func__); + err = -EINVAL; + goto out; + } + + clk_scaling = &host->clk_scaling; + + if (!clk_scaling->enable) + goto out; + + pr_debug("%s: target freq = %lu (%s)\n", mmc_hostname(host), + *freq, current->comm); + + if ((clk_scaling->curr_freq == *freq) || + clk_scaling->skip_clk_scale_freq_update) + goto out; + + /* No need to scale the clocks if they are gated */ + if (!host->ios.clock) + goto out; + + spin_lock_bh(&clk_scaling->lock); + if (clk_scaling->clk_scaling_in_progress) { + pr_debug("%s: clocks scaling is already in-progress by mmc thread\n", + mmc_hostname(host)); + spin_unlock_bh(&clk_scaling->lock); + goto out; + } + clk_scaling->need_freq_change = true; + clk_scaling->target_freq = *freq; + clk_scaling->state = *freq < clk_scaling->curr_freq ? + MMC_LOAD_LOW : MMC_LOAD_HIGH; + spin_unlock_bh(&clk_scaling->lock); + + abort = __mmc_claim_host(host, &clk_scaling->devfreq_abort); + if (abort) + goto out; + + if (mmc_card_sd(host->card) && host->card->sdr104_blocked) + goto rel_host; + + /* + * In case we were able to claim host there is no need to + * defer the frequency change. It will be done now + */ + clk_scaling->need_freq_change = false; + + mmc_host_clk_hold(host); + err = mmc_clk_update_freq(host, *freq, clk_scaling->state); + if (err && err != -EAGAIN) { + pr_err("%s: clock scale to %lu failed with error %d\n", + mmc_hostname(host), *freq, err); + err = mmc_recovery_fallback_lower_speed(host); + } else { + pr_debug("%s: clock change to %lu finished successfully (%s)\n", + mmc_hostname(host), *freq, current->comm); + } + + + mmc_host_clk_release(host); +rel_host: + mmc_release_host(host); +out: + tsk_restore_flags(current, pflags, PF_MEMALLOC); + return err; +} + +/** + * mmc_deferred_scaling() - scale clocks from data path (mmc thread context) + * @host: pointer to mmc host structure + * + * This function does clock scaling in case "need_freq_change" flag was set + * by the clock scaling logic. + */ +void mmc_deferred_scaling(struct mmc_host *host) +{ + unsigned long target_freq; + int err; + + if (!host->clk_scaling.enable) + return; + + if (mmc_card_sd(host->card) && host->card->sdr104_blocked) + return; + + spin_lock_bh(&host->clk_scaling.lock); + + if (host->clk_scaling.clk_scaling_in_progress || + !(host->clk_scaling.need_freq_change)) { + spin_unlock_bh(&host->clk_scaling.lock); + return; + } + + + atomic_inc(&host->clk_scaling.devfreq_abort); + target_freq = host->clk_scaling.target_freq; + host->clk_scaling.clk_scaling_in_progress = true; + host->clk_scaling.need_freq_change = false; + spin_unlock_bh(&host->clk_scaling.lock); + pr_debug("%s: doing deferred frequency change (%lu) (%s)\n", + mmc_hostname(host), + target_freq, current->comm); + + err = mmc_clk_update_freq(host, target_freq, + host->clk_scaling.state); + if (err && err != -EAGAIN) { + pr_err("%s: failed on deferred scale clocks (%d)\n", + mmc_hostname(host), err); + mmc_recovery_fallback_lower_speed(host); + } else { + pr_debug("%s: clocks were successfully scaled to %lu (%s)\n", + mmc_hostname(host), + target_freq, current->comm); + } + host->clk_scaling.clk_scaling_in_progress = false; + atomic_dec(&host->clk_scaling.devfreq_abort); +} +EXPORT_SYMBOL(mmc_deferred_scaling); + +static int mmc_devfreq_create_freq_table(struct mmc_host *host) +{ + int i; + struct mmc_devfeq_clk_scaling *clk_scaling = &host->clk_scaling; + + pr_debug("%s: supported: lowest=%lu, highest=%lu\n", + mmc_hostname(host), + host->card->clk_scaling_lowest, + host->card->clk_scaling_highest); + + /* + * Create the frequency table and initialize it with default values. + * Initialize it with platform specific frequencies if the frequency + * table supplied by platform driver is present, otherwise initialize + * it with min and max frequencies supported by the card. + */ + if (!clk_scaling->freq_table) { + if (clk_scaling->pltfm_freq_table_sz) + clk_scaling->freq_table_sz = + clk_scaling->pltfm_freq_table_sz; + else + clk_scaling->freq_table_sz = 2; + + clk_scaling->freq_table = kzalloc( + (clk_scaling->freq_table_sz * + sizeof(*(clk_scaling->freq_table))), GFP_KERNEL); + if (!clk_scaling->freq_table) + return -ENOMEM; + + if (clk_scaling->pltfm_freq_table) { + memcpy(clk_scaling->freq_table, + clk_scaling->pltfm_freq_table, + (clk_scaling->pltfm_freq_table_sz * + sizeof(*(clk_scaling->pltfm_freq_table)))); + } else { + pr_debug("%s: no frequency table defined - setting default\n", + mmc_hostname(host)); + clk_scaling->freq_table[0] = + host->card->clk_scaling_lowest; + clk_scaling->freq_table[1] = + host->card->clk_scaling_highest; + goto out; + } + } + + if (host->card->clk_scaling_lowest > + clk_scaling->freq_table[0]) + pr_debug("%s: frequency table undershot possible freq\n", + mmc_hostname(host)); + + for (i = 0; i < clk_scaling->freq_table_sz; i++) { + if (clk_scaling->freq_table[i] <= + host->card->clk_scaling_highest) + continue; + clk_scaling->freq_table[i] = + host->card->clk_scaling_highest; + clk_scaling->freq_table_sz = i + 1; + pr_debug("%s: frequency table overshot possible freq (%d)\n", + mmc_hostname(host), clk_scaling->freq_table[i]); + break; + } + +out: + clk_scaling->devfreq_profile.freq_table = clk_scaling->freq_table; + clk_scaling->devfreq_profile.max_state = clk_scaling->freq_table_sz; + + for (i = 0; i < clk_scaling->freq_table_sz; i++) + pr_debug("%s: freq[%d] = %u\n", + mmc_hostname(host), i, clk_scaling->freq_table[i]); + + return 0; +} + +/** + * mmc_init_devfreq_clk_scaling() - Initialize clock scaling + * @host: pointer to mmc host structure + * + * Initialize clock scaling for supported hosts. It is assumed that the caller + * ensure clock is running at maximum possible frequency before calling this + * function. Shall use struct devfreq_simple_ondemand_data to configure + * governor. + */ +int mmc_init_clk_scaling(struct mmc_host *host) +{ + int err; + + if (!host || !host->card) { + pr_err("%s: unexpected host/card parameters\n", + __func__); + return -EINVAL; + } + + if (!mmc_can_scale_clk(host) || + !host->bus_ops->change_bus_speed) { + pr_debug("%s: clock scaling is not supported\n", + mmc_hostname(host)); + return 0; + } + + pr_debug("registering %s dev (%p) to devfreq", + mmc_hostname(host), + mmc_classdev(host)); + + if (host->clk_scaling.devfreq) { + pr_err("%s: dev is already registered for dev %p\n", + mmc_hostname(host), + mmc_dev(host)); + return -EPERM; + } + spin_lock_init(&host->clk_scaling.lock); + atomic_set(&host->clk_scaling.devfreq_abort, 0); + host->clk_scaling.curr_freq = host->ios.clock; + host->clk_scaling.clk_scaling_in_progress = false; + host->clk_scaling.need_freq_change = false; + host->clk_scaling.is_busy_started = false; + + host->clk_scaling.devfreq_profile.polling_ms = + host->clk_scaling.polling_delay_ms; + host->clk_scaling.devfreq_profile.get_dev_status = + mmc_devfreq_get_dev_status; + host->clk_scaling.devfreq_profile.target = mmc_devfreq_set_target; + host->clk_scaling.devfreq_profile.initial_freq = host->ios.clock; + + host->clk_scaling.ondemand_gov_data.simple_scaling = true; + host->clk_scaling.ondemand_gov_data.upthreshold = + host->clk_scaling.upthreshold; + host->clk_scaling.ondemand_gov_data.downdifferential = + host->clk_scaling.upthreshold - host->clk_scaling.downthreshold; + + err = mmc_devfreq_create_freq_table(host); + if (err) { + pr_err("%s: fail to create devfreq frequency table\n", + mmc_hostname(host)); + return err; + } + + pr_debug("%s: adding devfreq with: upthreshold=%u downthreshold=%u polling=%u\n", + mmc_hostname(host), + host->clk_scaling.ondemand_gov_data.upthreshold, + host->clk_scaling.ondemand_gov_data.downdifferential, + host->clk_scaling.devfreq_profile.polling_ms); + host->clk_scaling.devfreq = devfreq_add_device( + mmc_classdev(host), + &host->clk_scaling.devfreq_profile, + "simple_ondemand", + &host->clk_scaling.ondemand_gov_data); + if (!host->clk_scaling.devfreq) { + pr_err("%s: unable to register with devfreq\n", + mmc_hostname(host)); + return -EPERM; + } + + pr_debug("%s: clk scaling is enabled for device %s (%p) with devfreq %p (clock = %uHz)\n", + mmc_hostname(host), + dev_name(mmc_classdev(host)), + mmc_classdev(host), + host->clk_scaling.devfreq, + host->ios.clock); + + host->clk_scaling.enable = true; + + return err; +} +EXPORT_SYMBOL(mmc_init_clk_scaling); + +/** + * mmc_suspend_clk_scaling() - suspend clock scaling + * @host: pointer to mmc host structure + * + * This API will suspend devfreq feature for the specific host. + * The statistics collected by mmc will be cleared. + * This function is intended to be called by the pm callbacks + * (e.g. runtime_suspend, suspend) of the mmc device + */ +int mmc_suspend_clk_scaling(struct mmc_host *host) +{ + int err; + + if (!host) { + WARN(1, "bad host parameter\n"); + return -EINVAL; + } + + if (!mmc_can_scale_clk(host) || !host->clk_scaling.enable) + return 0; + + if (!host->clk_scaling.devfreq) { + pr_err("%s: %s: no devfreq is assosiated with this device\n", + mmc_hostname(host), __func__); + return -EPERM; + } + + atomic_inc(&host->clk_scaling.devfreq_abort); + wake_up(&host->wq); + err = devfreq_suspend_device(host->clk_scaling.devfreq); + if (err) { + pr_err("%s: %s: failed to suspend devfreq\n", + mmc_hostname(host), __func__); + return err; + } + host->clk_scaling.enable = false; + + host->clk_scaling.total_busy_time_us = 0; + + pr_debug("%s: devfreq suspended\n", mmc_hostname(host)); + + return 0; +} +EXPORT_SYMBOL(mmc_suspend_clk_scaling); + +/** + * mmc_resume_clk_scaling() - resume clock scaling + * @host: pointer to mmc host structure + * + * This API will resume devfreq feature for the specific host. + * This API is intended to be called by the pm callbacks + * (e.g. runtime_suspend, suspend) of the mmc device + */ +int mmc_resume_clk_scaling(struct mmc_host *host) +{ + int err = 0; + u32 max_clk_idx = 0; + u32 devfreq_max_clk = 0; + u32 devfreq_min_clk = 0; + + if (!host) { + WARN(1, "bad host parameter\n"); + return -EINVAL; + } + + if (!mmc_can_scale_clk(host)) + return 0; + + /* + * If clock scaling is already exited when resume is called, like + * during mmc shutdown, it is not an error and should not fail the + * API calling this. + */ + if (!host->clk_scaling.devfreq) { + pr_warn("%s: %s: no devfreq is assosiated with this device\n", + mmc_hostname(host), __func__); + return 0; + } + + atomic_set(&host->clk_scaling.devfreq_abort, 0); + + max_clk_idx = host->clk_scaling.freq_table_sz - 1; + devfreq_max_clk = host->clk_scaling.freq_table[max_clk_idx]; + devfreq_min_clk = host->clk_scaling.freq_table[0]; + + host->clk_scaling.curr_freq = devfreq_max_clk; + if (host->ios.clock < host->clk_scaling.freq_table[max_clk_idx]) + host->clk_scaling.curr_freq = devfreq_min_clk; + + host->clk_scaling.clk_scaling_in_progress = false; + host->clk_scaling.need_freq_change = false; + + err = devfreq_resume_device(host->clk_scaling.devfreq); + if (err) { + pr_err("%s: %s: failed to resume devfreq (%d)\n", + mmc_hostname(host), __func__, err); + } else { + host->clk_scaling.enable = true; + pr_debug("%s: devfreq resumed\n", mmc_hostname(host)); + } + + return err; +} +EXPORT_SYMBOL(mmc_resume_clk_scaling); + +/** + * mmc_exit_devfreq_clk_scaling() - Disable clock scaling + * @host: pointer to mmc host structure + * + * Disable clock scaling permanently. + */ +int mmc_exit_clk_scaling(struct mmc_host *host) +{ + int err; + + if (!host) { + pr_err("%s: bad host parameter\n", __func__); + WARN_ON(1); + return -EINVAL; + } + + if (!mmc_can_scale_clk(host)) + return 0; + + if (!host->clk_scaling.devfreq) { + pr_err("%s: %s: no devfreq is assosiated with this device\n", + mmc_hostname(host), __func__); + return -EPERM; + } + + err = mmc_suspend_clk_scaling(host); + if (err) { + pr_err("%s: %s: fail to suspend clock scaling (%d)\n", + mmc_hostname(host), __func__, err); + return err; + } + + err = devfreq_remove_device(host->clk_scaling.devfreq); + if (err) { + pr_err("%s: remove devfreq failed (%d)\n", + mmc_hostname(host), err); + return err; + } + + host->clk_scaling.devfreq = NULL; + atomic_set(&host->clk_scaling.devfreq_abort, 1); + + kfree(host->clk_scaling.freq_table); + host->clk_scaling.freq_table = NULL; + + pr_debug("%s: devfreq was removed\n", mmc_hostname(host)); + + return 0; +} +EXPORT_SYMBOL(mmc_exit_clk_scaling); + /** * mmc_request_done - finish processing an MMC request * @host: MMC host which completed request @@ -132,6 +954,12 @@ { struct mmc_command *cmd = mrq->cmd; int err = cmd->error; +#ifdef CONFIG_MMC_PERF_PROFILING + ktime_t diff; +#endif + + if (host->clk_scaling.is_busy_started) + mmc_clk_scaling_stop_busy(host, true); /* Flag re-tuning needed on CRC errors */ if ((cmd->opcode != MMC_SEND_TUNING_BLOCK && @@ -172,9 +1000,42 @@ cmd->resp[2], cmd->resp[3]); if (mrq->data) { +#ifdef CONFIG_MMC_PERF_PROFILING + if (host->perf_enable) { + diff = ktime_sub(ktime_get(), host->perf.start); + if (mrq->data->flags == MMC_DATA_READ) { + host->perf.rbytes_drv += + mrq->data->bytes_xfered; + host->perf.rtime_drv = + ktime_add(host->perf.rtime_drv, + diff); + } else { + host->perf.wbytes_drv += + mrq->data->bytes_xfered; + host->perf.wtime_drv = + ktime_add(host->perf.wtime_drv, + diff); + } + } +#endif pr_debug("%s: %d bytes transferred: %d\n", mmc_hostname(host), mrq->data->bytes_xfered, mrq->data->error); +#ifdef CONFIG_BLOCK + if (mrq->lat_hist_enabled) { + ktime_t completion; + u_int64_t delta_us; + + completion = ktime_get(); + delta_us = ktime_us_delta(completion, + mrq->io_start); + blk_update_latency_hist( + (mrq->data->flags & MMC_DATA_READ) ? + &host->io_lat_read : + &host->io_lat_write, delta_us); + } +#endif + trace_mmc_blk_rw_end(cmd->opcode, cmd->arg, mrq->data); } if (mrq->stop) { @@ -187,6 +1048,8 @@ if (mrq->done) mrq->done(mrq); + + mmc_host_clk_release(host); } } @@ -289,32 +1152,206 @@ mrq->stop->error = 0; mrq->stop->mrq = mrq; } +#ifdef CONFIG_MMC_PERF_PROFILING + if (host->perf_enable) + host->perf.start = ktime_get(); +#endif } + mmc_host_clk_hold(host); led_trigger_event(host->led, LED_FULL); + + if (mmc_is_data_request(mrq)) { + mmc_deferred_scaling(host); + mmc_clk_scaling_start_busy(host, true); + } + __mmc_start_request(host, mrq); return 0; } +static int mmc_start_cmdq_request(struct mmc_host *host, + struct mmc_request *mrq) +{ + int ret = 0; + + if (mrq->data) { + pr_debug("%s: blksz %d blocks %d flags %08x tsac %lu ms nsac %d\n", + mmc_hostname(host), mrq->data->blksz, + mrq->data->blocks, mrq->data->flags, + mrq->data->timeout_ns / NSEC_PER_MSEC, + mrq->data->timeout_clks); + + BUG_ON(mrq->data->blksz > host->max_blk_size); + BUG_ON(mrq->data->blocks > host->max_blk_count); + BUG_ON(mrq->data->blocks * mrq->data->blksz > + host->max_req_size); + mrq->data->error = 0; + mrq->data->mrq = mrq; + } + + if (mrq->cmd) { + mrq->cmd->error = 0; + mrq->cmd->mrq = mrq; + } + + mmc_host_clk_hold(host); + if (likely(host->cmdq_ops->request)) { + ret = host->cmdq_ops->request(host, mrq); + } else { + ret = -ENOENT; + pr_err("%s: %s: cmdq request host op is not available\n", + mmc_hostname(host), __func__); + } + + if (ret) { + mmc_host_clk_release(host); + pr_err("%s: %s: issue request failed, err=%d\n", + mmc_hostname(host), __func__, ret); + } + + return ret; +} + +/** + * mmc_blk_init_bkops_statistics - initialize bkops statistics + * @card: MMC card to start BKOPS + * + * Initialize and enable the bkops statistics + */ +void mmc_blk_init_bkops_statistics(struct mmc_card *card) +{ + int i; + struct mmc_bkops_stats *stats; + + if (!card) + return; + + stats = &card->bkops.stats; + spin_lock(&stats->lock); + + stats->manual_start = 0; + stats->hpi = 0; + stats->auto_start = 0; + stats->auto_stop = 0; + for (i = 0 ; i < MMC_BKOPS_NUM_SEVERITY_LEVELS ; i++) + stats->level[i] = 0; + stats->enabled = true; + + spin_unlock(&stats->lock); +} +EXPORT_SYMBOL(mmc_blk_init_bkops_statistics); + +static void mmc_update_bkops_hpi(struct mmc_bkops_stats *stats) +{ + spin_lock_irq(&stats->lock); + if (stats->enabled) + stats->hpi++; + spin_unlock_irq(&stats->lock); +} + +static void mmc_update_bkops_start(struct mmc_bkops_stats *stats) +{ + spin_lock_irq(&stats->lock); + if (stats->enabled) + stats->manual_start++; + spin_unlock_irq(&stats->lock); +} + +static void mmc_update_bkops_auto_on(struct mmc_bkops_stats *stats) +{ + spin_lock_irq(&stats->lock); + if (stats->enabled) + stats->auto_start++; + spin_unlock_irq(&stats->lock); +} + +static void mmc_update_bkops_auto_off(struct mmc_bkops_stats *stats) +{ + spin_lock_irq(&stats->lock); + if (stats->enabled) + stats->auto_stop++; + spin_unlock_irq(&stats->lock); +} + +static void mmc_update_bkops_level(struct mmc_bkops_stats *stats, + unsigned level) +{ + BUG_ON(level >= MMC_BKOPS_NUM_SEVERITY_LEVELS); + spin_lock_irq(&stats->lock); + if (stats->enabled) + stats->level[level]++; + spin_unlock_irq(&stats->lock); +} + /** - * mmc_start_bkops - start BKOPS for supported cards + * mmc_set_auto_bkops - set auto BKOPS for supported cards * @card: MMC card to start BKOPS - * @form_exception: A flag to indicate if this function was - * called due to an exception raised by the card + * @enable: enable/disable flag + * Configure the card to run automatic BKOPS. + * + * Should be called when host is claimed. +*/ +int mmc_set_auto_bkops(struct mmc_card *card, bool enable) +{ + int ret = 0; + u8 bkops_en; + + BUG_ON(!card); + enable = !!enable; + + if (unlikely(!mmc_card_support_auto_bkops(card))) { + pr_err("%s: %s: card doesn't support auto bkops\n", + mmc_hostname(card->host), __func__); + return -EPERM; + } + + if (enable) { + if (mmc_card_doing_auto_bkops(card)) + goto out; + bkops_en = card->ext_csd.bkops_en | EXT_CSD_BKOPS_AUTO_EN; + } else { + if (!mmc_card_doing_auto_bkops(card)) + goto out; + bkops_en = card->ext_csd.bkops_en & ~EXT_CSD_BKOPS_AUTO_EN; + } + + ret = mmc_switch(card, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_BKOPS_EN, + bkops_en, 0); + if (ret) { + pr_err("%s: %s: error in setting auto bkops to %d (%d)\n", + mmc_hostname(card->host), __func__, enable, ret); + } else { + if (enable) { + mmc_card_set_auto_bkops(card); + mmc_update_bkops_auto_on(&card->bkops.stats); + } else { + mmc_card_clr_auto_bkops(card); + mmc_update_bkops_auto_off(&card->bkops.stats); + } + card->ext_csd.bkops_en = bkops_en; + pr_debug("%s: %s: bkops state %x\n", + mmc_hostname(card->host), __func__, bkops_en); + } +out: + return ret; +} +EXPORT_SYMBOL(mmc_set_auto_bkops); + +/** + * mmc_check_bkops - check BKOPS for supported cards + * @card: MMC card to check BKOPS * - * Start background operations whenever requested. - * When the urgent BKOPS bit is set in a R1 command response - * then background operations should be started immediately. + * Read the BKOPS status in order to determine whether the + * card requires bkops to be started. */ -void mmc_start_bkops(struct mmc_card *card, bool from_exception) +void mmc_check_bkops(struct mmc_card *card) { int err; - int timeout; - bool use_busy_signal; BUG_ON(!card); - if (!card->ext_csd.man_bkops_en || mmc_card_doing_bkops(card)) + if (mmc_card_doing_bkops(card)) return; err = mmc_read_bkops_status(card); @@ -324,47 +1361,50 @@ return; } - if (!card->ext_csd.raw_bkops_status) - return; + card->bkops.needs_check = false; - if (card->ext_csd.raw_bkops_status < EXT_CSD_BKOPS_LEVEL_2 && - from_exception) - return; + mmc_update_bkops_level(&card->bkops.stats, + card->ext_csd.raw_bkops_status); - mmc_claim_host(card->host); - if (card->ext_csd.raw_bkops_status >= EXT_CSD_BKOPS_LEVEL_2) { - timeout = MMC_BKOPS_MAX_TIMEOUT; - use_busy_signal = true; - } else { - timeout = 0; - use_busy_signal = false; + card->bkops.needs_bkops = card->ext_csd.raw_bkops_status > 0; } +EXPORT_SYMBOL(mmc_check_bkops); + +/** + * mmc_start_manual_bkops - start BKOPS for supported cards + * @card: MMC card to start BKOPS + * + * Send START_BKOPS to the card. + * The function should be called with claimed host. +*/ +void mmc_start_manual_bkops(struct mmc_card *card) +{ + int err; + + BUG_ON(!card); + + if (unlikely(!mmc_card_configured_manual_bkops(card))) + return; + + if (mmc_card_doing_bkops(card)) + return; mmc_retune_hold(card->host); - err = __mmc_switch(card, EXT_CSD_CMD_SET_NORMAL, - EXT_CSD_BKOPS_START, 1, timeout, - use_busy_signal, true, false); + err = __mmc_switch(card, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_BKOPS_START, + 1, 0, false, true, false); if (err) { - pr_warn("%s: Error %d starting bkops\n", + pr_err("%s: Error %d starting manual bkops\n", mmc_hostname(card->host), err); - mmc_retune_release(card->host); - goto out; + } else { + mmc_card_set_doing_bkops(card); + mmc_update_bkops_start(&card->bkops.stats); + card->bkops.needs_bkops = false; } - /* - * For urgent bkops status (LEVEL_2 and more) - * bkops executed synchronously, otherwise - * the operation is in progress - */ - if (!use_busy_signal) - mmc_card_set_doing_bkops(card); - else mmc_retune_release(card->host); -out: - mmc_release_host(card->host); } -EXPORT_SYMBOL(mmc_start_bkops); +EXPORT_SYMBOL(mmc_start_manual_bkops); /* * mmc_wait_data_done() - done callback for data request @@ -374,10 +1414,13 @@ */ static void mmc_wait_data_done(struct mmc_request *mrq) { + unsigned long flags; struct mmc_context_info *context_info = &mrq->host->context_info; + spin_lock_irqsave(&context_info->lock, flags); context_info->is_done_rcv = true; wake_up_interruptible(&context_info->wait); + spin_unlock_irqrestore(&context_info->lock, flags); } static void mmc_wait_done(struct mmc_request *mrq) @@ -443,6 +1486,7 @@ struct mmc_command *cmd; struct mmc_context_info *context_info = &host->context_info; int err; + bool is_done_rcv = false; unsigned long flags; while (1) { @@ -450,9 +1494,10 @@ (context_info->is_done_rcv || context_info->is_new_req)); spin_lock_irqsave(&context_info->lock, flags); + is_done_rcv = context_info->is_done_rcv; context_info->is_waiting_last_req = false; spin_unlock_irqrestore(&context_info->lock, flags); - if (context_info->is_done_rcv) { + if (is_done_rcv) { context_info->is_done_rcv = false; context_info->is_new_req = false; cmd = mrq->cmd; @@ -488,19 +1533,19 @@ struct mmc_command *cmd; while (1) { - wait_for_completion(&mrq->completion); + wait_for_completion_io(&mrq->completion); cmd = mrq->cmd; /* - * If host has timed out waiting for the sanitize + * If host has timed out waiting for the sanitize/bkops * to complete, card might be still in programming state * so let's try to bring the card out of programming * state. */ - if (cmd->sanitize_busy && cmd->error == -ETIMEDOUT) { + if ((cmd->bkops_busy || cmd->sanitize_busy) && cmd->error == -ETIMEDOUT) { if (!mmc_interrupt_hpi(host->card)) { - pr_warn("%s: %s: Interrupted sanitize\n", + pr_warn("%s: %s: Interrupted sanitize/bkops\n", mmc_hostname(host), __func__); cmd->error = 0; break; @@ -510,8 +1555,13 @@ } } if (!cmd->error || !cmd->retries || - mmc_card_removed(host->card)) + mmc_card_removed(host->card)) { + if (cmd->error && !cmd->retries && + cmd->opcode != MMC_SEND_STATUS && + cmd->opcode != MMC_SEND_TUNING_BLOCK) + mmc_recovery_fallback_lower_speed(host); break; + } mmc_retune_recheck(host); @@ -539,8 +1589,11 @@ static void mmc_pre_req(struct mmc_host *host, struct mmc_request *mrq, bool is_first_req) { - if (host->ops->pre_req) + if (host->ops->pre_req) { + mmc_host_clk_hold(host); host->ops->pre_req(host, mrq, is_first_req); + mmc_host_clk_release(host); + } } /** @@ -555,10 +1608,140 @@ static void mmc_post_req(struct mmc_host *host, struct mmc_request *mrq, int err) { - if (host->ops->post_req) + if (host->ops->post_req) { + mmc_host_clk_hold(host); host->ops->post_req(host, mrq, err); + mmc_host_clk_release(host); + } +} + +/** + * mmc_cmdq_discard_card_queue - discard the task[s] in the device + * @host: host instance + * @tasks: mask of tasks to be knocked off + * 0: remove all queued tasks + */ +int mmc_cmdq_discard_queue(struct mmc_host *host, u32 tasks) +{ + return mmc_discard_queue(host, tasks); +} +EXPORT_SYMBOL(mmc_cmdq_discard_queue); + + +/** + * mmc_cmdq_post_req - post process of a completed request + * @host: host instance + * @tag: the request tag. + * @err: non-zero is error, success otherwise + */ +void mmc_cmdq_post_req(struct mmc_host *host, int tag, int err) +{ + if (likely(host->cmdq_ops->post_req)) + host->cmdq_ops->post_req(host, tag, err); +} +EXPORT_SYMBOL(mmc_cmdq_post_req); + +/** + * mmc_cmdq_halt - halt/un-halt the command queue engine + * @host: host instance + * @halt: true - halt, un-halt otherwise + * + * Host halts the command queue engine. It should complete + * the ongoing transfer and release the bus. + * All legacy commands can be sent upon successful + * completion of this function. + * Returns 0 on success, negative otherwise + */ +int mmc_cmdq_halt(struct mmc_host *host, bool halt) +{ + int err = 0; + + if (mmc_host_cq_disable(host)) { + pr_debug("%s: %s: CQE is already disabled\n", + mmc_hostname(host), __func__); + return 0; + } + + if ((halt && mmc_host_halt(host)) || + (!halt && !mmc_host_halt(host))) { + pr_debug("%s: %s: CQE is already %s\n", mmc_hostname(host), + __func__, halt ? "halted" : "un-halted"); + return 0; } + mmc_host_clk_hold(host); + if (host->cmdq_ops->halt) { + err = host->cmdq_ops->halt(host, halt); + if (!err && host->ops->notify_halt) + host->ops->notify_halt(host, halt); + if (!err && halt) + mmc_host_set_halt(host); + else if (!err && !halt) { + mmc_host_clr_halt(host); + wake_up(&host->cmdq_ctx.wait); + } + } else { + err = -ENOSYS; + } + mmc_host_clk_release(host); + return err; +} +EXPORT_SYMBOL(mmc_cmdq_halt); + +int mmc_cmdq_start_req(struct mmc_host *host, struct mmc_cmdq_req *cmdq_req) +{ + struct mmc_request *mrq = &cmdq_req->mrq; + + mrq->host = host; + if (mmc_card_removed(host->card)) { + mrq->cmd->error = -ENOMEDIUM; + return -ENOMEDIUM; + } + return mmc_start_cmdq_request(host, mrq); +} +EXPORT_SYMBOL(mmc_cmdq_start_req); + +static void mmc_cmdq_dcmd_req_done(struct mmc_request *mrq) +{ + mmc_host_clk_release(mrq->host); + complete(&mrq->completion); +} + +int mmc_cmdq_wait_for_dcmd(struct mmc_host *host, + struct mmc_cmdq_req *cmdq_req) +{ + struct mmc_request *mrq = &cmdq_req->mrq; + struct mmc_command *cmd = mrq->cmd; + int err = 0; + + init_completion(&mrq->completion); + mrq->done = mmc_cmdq_dcmd_req_done; + err = mmc_cmdq_start_req(host, cmdq_req); + if (err) + return err; + + wait_for_completion_io(&mrq->completion); + if (cmd->error) { + pr_err("%s: DCMD %d failed with err %d\n", + mmc_hostname(host), cmd->opcode, + cmd->error); + err = cmd->error; + mmc_host_clk_hold(host); + host->cmdq_ops->dumpstate(host); + mmc_host_clk_release(host); + } + return err; +} +EXPORT_SYMBOL(mmc_cmdq_wait_for_dcmd); + +int mmc_cmdq_prepare_flush(struct mmc_command *cmd) +{ + return __mmc_switch_cmdq_mode(cmd, EXT_CSD_CMD_SET_NORMAL, + EXT_CSD_FLUSH_CACHE, 1, + 0, true, true); +} +EXPORT_SYMBOL(mmc_cmdq_prepare_flush); + /** * mmc_start_req - start a non-blocking request * @host: MMC host to start command @@ -579,7 +1762,6 @@ struct mmc_async_req *areq, int *error) { int err = 0; - int start_err = 0; struct mmc_async_req *data = host->areq; /* Prepare a new request */ @@ -609,7 +1791,7 @@ if (areq) mmc_post_req(host, areq->mrq, -EINVAL); - mmc_start_bkops(host->card, true); + mmc_check_bkops(host->card); /* prepare the request again */ if (areq) @@ -617,14 +1799,24 @@ } } - if (!err && areq) - start_err = __mmc_start_data_req(host, areq->mrq); + if (!err && areq) { +#ifdef CONFIG_BLOCK + if (host->latency_hist_enabled) { + areq->mrq->io_start = ktime_get(); + areq->mrq->lat_hist_enabled = 1; + } else + areq->mrq->lat_hist_enabled = 0; +#endif + trace_mmc_blk_rw_start(areq->mrq->cmd->opcode, + areq->mrq->cmd->arg, + areq->mrq->data); + __mmc_start_data_req(host, areq->mrq); + } if (host->areq) mmc_post_req(host, host->areq->mrq, 0); - /* Cancel a prepared request if it was not started. */ - if ((err || start_err) && areq) + if (err && areq) mmc_post_req(host, areq->mrq, -EINVAL); if (err) @@ -649,6 +1841,10 @@ */ void mmc_wait_for_req(struct mmc_host *host, struct mmc_request *mrq) { +#ifdef CONFIG_MMC_BLOCK_DEFERRED_RESUME + if (mmc_bus_needs_resume(host)) + mmc_resume_bus(host); +#endif __mmc_start_req(host, mrq); mmc_wait_for_req_done(host, mrq); } @@ -702,8 +1898,6 @@ } err = mmc_send_hpi_cmd(card, &status); - if (err) - goto out; prg_wait = jiffies + msecs_to_jiffies(card->ext_csd.out_of_int_time); do { @@ -711,8 +1905,13 @@ if (!err && R1_CURRENT_STATE(status) == R1_STATE_TRAN) break; - if (time_after(jiffies, prg_wait)) + if (time_after(jiffies, prg_wait)) { + err = mmc_send_status(card, &status); + if (!err && R1_CURRENT_STATE(status) != R1_STATE_TRAN) err = -ETIMEDOUT; + else + break; + } } while (!err); out: @@ -764,6 +1963,11 @@ int err = 0; BUG_ON(!card); + if (unlikely(!mmc_card_configured_manual_bkops(card))) + goto out; + if (!mmc_card_doing_bkops(card)) + goto out; + err = mmc_interrupt_hpi(card); /* @@ -772,10 +1976,11 @@ */ if (!err || (err == -EINVAL)) { mmc_card_clr_doing_bkops(card); + mmc_update_bkops_hpi(&card->bkops.stats); mmc_retune_release(card->host); err = 0; } - +out: return err; } EXPORT_SYMBOL(mmc_stop_bkops); @@ -791,8 +1996,14 @@ if (err) return err; - card->ext_csd.raw_bkops_status = ext_csd[EXT_CSD_BKOPS_STATUS]; - card->ext_csd.raw_exception_status = ext_csd[EXT_CSD_EXP_EVENTS_STATUS]; + card->ext_csd.raw_bkops_status = ext_csd[EXT_CSD_BKOPS_STATUS] & + MMC_BKOPS_URGENCY_MASK; + card->ext_csd.raw_exception_status = + ext_csd[EXT_CSD_EXP_EVENTS_STATUS] & (EXT_CSD_URGENT_BKOPS | + EXT_CSD_DYNCAP_NEEDED | + EXT_CSD_SYSPOOL_EXHAUSTED + | EXT_CSD_PACKED_FAILURE); + kfree(ext_csd); return 0; } @@ -810,6 +2021,10 @@ { unsigned int mult; + if (!card) { + WARN_ON(1); + return; + } /* * SDIO cards only define an upper 1 s limit on access. */ @@ -841,9 +2056,9 @@ unsigned int timeout_us, limit_us; timeout_us = data->timeout_ns / 1000; - if (card->host->ios.clock) + if (mmc_host_clk_rate(card->host)) timeout_us += data->timeout_clks * 1000 / - (card->host->ios.clock / 1000); + (mmc_host_clk_rate(card->host) / 1000); if (data->flags & MMC_DATA_WRITE) /* @@ -876,9 +2091,11 @@ * Address this by setting the read timeout to a "reasonably high" * value. For the cards tested, 600ms has proven enough. If necessary, * this value can be increased if other problematic cards require this. + * Certain Hynix 5.x cards giving read timeout even with 300ms. + * Increasing further to max value (4s). */ if (mmc_card_long_read_time(card) && data->flags & MMC_DATA_READ) { - data->timeout_ns = 600000000; + data->timeout_ns = 4000000000u; data->timeout_clks = 0; } @@ -897,6 +2114,11 @@ data->timeout_ns = 100000000; /* 100ms */ } } + /* Increase the timeout values for some bad INAND MCP devices */ + if (card->quirks & MMC_QUIRK_INAND_DATA_TIMEOUT) { + data->timeout_ns = 4000000000u; /* 4s */ + data->timeout_clks = 0; + } } EXPORT_SYMBOL(mmc_set_data_timeout); @@ -947,6 +2169,7 @@ might_sleep(); add_wait_queue(&host->wq, &wait); + spin_lock_irqsave(&host->lock, flags); while (1) { set_current_state(TASK_UNINTERRUPTIBLE); @@ -972,11 +2195,53 @@ if (pm) pm_runtime_get_sync(mmc_dev(host)); + if (host->ops->enable && !stop && host->claim_cnt == 1) + host->ops->enable(host); + return stop; } EXPORT_SYMBOL(__mmc_claim_host); /** + * mmc_try_claim_host - try exclusively to claim a host + * and keep trying for given time, with a gap of 10ms + * @host: mmc host to claim + * @dealy_ms: delay in ms + * + * Returns %1 if the host is claimed, %0 otherwise. + */ +int mmc_try_claim_host(struct mmc_host *host, unsigned int delay_ms) +{ + int claimed_host = 0; + unsigned long flags; + int retry_cnt = delay_ms/10; + bool pm = false; + + do { + spin_lock_irqsave(&host->lock, flags); + if (!host->claimed || host->claimer == current) { + host->claimed = 1; + host->claimer = current; + host->claim_cnt += 1; + claimed_host = 1; + if (host->claim_cnt == 1) + pm = true; + } + spin_unlock_irqrestore(&host->lock, flags); + if (!claimed_host) + mmc_delay(10); + } while (!claimed_host && retry_cnt--); + + if (pm) + pm_runtime_get_sync(mmc_dev(host)); + + if (host->ops->enable && claimed_host && host->claim_cnt == 1) + host->ops->enable(host); + return claimed_host; +} +EXPORT_SYMBOL(mmc_try_claim_host); + +/** * mmc_release_host - release a host * @host: mmc host to release * @@ -989,6 +2254,9 @@ WARN_ON(!host->claimed); + if (host->ops->disable && host->claim_cnt == 1) + host->ops->disable(host); + spin_lock_irqsave(&host->lock, flags); if (--host->claim_cnt) { /* Release for nested claim */ @@ -1012,9 +2280,14 @@ { pm_runtime_get_sync(&card->dev); mmc_claim_host(card->host); +#ifdef CONFIG_MMC_BLOCK_DEFERRED_RESUME + if (mmc_bus_needs_resume(card->host)) + mmc_resume_bus(card->host); +#endif } EXPORT_SYMBOL(mmc_get_card); + /* * This is a helper function, which releases the host and drops the runtime * pm reference for the card device. @@ -1031,7 +2304,7 @@ * Internal function that does the actual ios call to the host driver, * optionally printing some debug output. */ -static inline void mmc_set_ios(struct mmc_host *host) +void mmc_set_ios(struct mmc_host *host) { struct mmc_ios *ios = &host->ios; @@ -1041,23 +2314,41 @@ ios->power_mode, ios->chip_select, ios->vdd, ios->bus_width, ios->timing); + if (ios->clock > 0) + mmc_set_ungated(host); host->ops->set_ios(host, ios); + if (ios->old_rate != ios->clock) { + if (likely(ios->clk_ts)) { + char trace_info[80]; + snprintf(trace_info, 80, + "%s: freq_KHz %d --> %d | t = %d", + mmc_hostname(host), ios->old_rate / 1000, + ios->clock / 1000, jiffies_to_msecs( + (long)jiffies - (long)ios->clk_ts)); + trace_mmc_clk(trace_info); + } + ios->old_rate = ios->clock; + ios->clk_ts = jiffies; } +} +EXPORT_SYMBOL(mmc_set_ios); /* * Control chip select pin on a host. */ void mmc_set_chip_select(struct mmc_host *host, int mode) { + mmc_host_clk_hold(host); host->ios.chip_select = mode; mmc_set_ios(host); + mmc_host_clk_release(host); } /* * Sets the host clock to the highest possible frequency that * is below "hz". */ -void mmc_set_clock(struct mmc_host *host, unsigned int hz) +static void __mmc_set_clock(struct mmc_host *host, unsigned int hz) { WARN_ON(hz && hz < host->f_min); @@ -1068,6 +2359,81 @@ mmc_set_ios(host); } +void mmc_set_clock(struct mmc_host *host, unsigned int hz) +{ + mmc_host_clk_hold(host); + __mmc_set_clock(host, hz); + mmc_host_clk_release(host); +} + +#ifdef CONFIG_MMC_CLKGATE +/* + * This gates the clock by setting it to 0 Hz. + */ +void mmc_gate_clock(struct mmc_host *host) +{ + unsigned long flags; + + WARN_ON(!host->ios.clock); + + spin_lock_irqsave(&host->clk_lock, flags); + host->clk_old = host->ios.clock; + host->ios.clock = 0; + host->clk_gated = true; + spin_unlock_irqrestore(&host->clk_lock, flags); + mmc_set_ios(host); +} + +/* + * This restores the clock from gating by using the cached + * clock value. + */ +void mmc_ungate_clock(struct mmc_host *host) +{ + /* + * We should previously have gated the clock, so the clock shall + * be 0 here! The clock may however be 0 during initialization, + * when some request operations are performed before setting + * the frequency. When ungate is requested in that situation + * we just ignore the call. + */ + if (host->clk_old) { + WARN_ON(host->ios.clock); + /* This call will also set host->clk_gated to false */ + __mmc_set_clock(host, host->clk_old); + /* + * We have seen that host controller's clock tuning circuit may + * go out of sync if controller clocks are gated. + * To workaround this issue, we are triggering retuning of the + * tuning circuit after ungating the controller clocks. + */ + mmc_retune_needed(host); + } +} + +void mmc_set_ungated(struct mmc_host *host) +{ + unsigned long flags; + + /* + * We've been given a new frequency while the clock is gated, + * so make sure we regard this as ungating it. + */ + spin_lock_irqsave(&host->clk_lock, flags); + host->clk_gated = false; + spin_unlock_irqrestore(&host->clk_lock, flags); +} + +#else +void mmc_set_ungated(struct mmc_host *host) +{ +} + +void mmc_gate_clock(struct mmc_host *host) +{ +} +#endif + int mmc_execute_tuning(struct mmc_card *card) { struct mmc_host *host = card->host; @@ -1082,7 +2448,9 @@ else opcode = MMC_SEND_TUNING_BLOCK; + mmc_host_clk_hold(host); err = host->ops->execute_tuning(host, opcode); + mmc_host_clk_release(host); if (err) pr_err("%s: tuning execution failed\n", mmc_hostname(host)); @@ -1097,8 +2465,10 @@ */ void mmc_set_bus_mode(struct mmc_host *host, unsigned int mode) { + mmc_host_clk_hold(host); host->ios.bus_mode = mode; mmc_set_ios(host); + mmc_host_clk_release(host); } /* @@ -1106,8 +2476,10 @@ */ void mmc_set_bus_width(struct mmc_host *host, unsigned int width) { + mmc_host_clk_hold(host); host->ios.bus_width = width; mmc_set_ios(host); + mmc_host_clk_release(host); } /* @@ -1119,9 +2491,10 @@ if (mmc_host_is_spi(host)) host->ios.chip_select = MMC_CS_HIGH; - else + else { host->ios.chip_select = MMC_CS_DONTCARE; - host->ios.bus_mode = MMC_BUSMODE_PUSHPULL; + host->ios.bus_mode = MMC_BUSMODE_OPENDRAIN; + } host->ios.bus_width = MMC_BUS_WIDTH_1; host->ios.timing = MMC_TIMING_LEGACY; host->ios.drv_type = 0; @@ -1548,8 +2921,11 @@ int old_signal_voltage = host->ios.signal_voltage; host->ios.signal_voltage = signal_voltage; - if (host->ops->start_signal_voltage_switch) + if (host->ops->start_signal_voltage_switch) { + mmc_host_clk_hold(host); err = host->ops->start_signal_voltage_switch(host, &host->ios); + mmc_host_clk_release(host); + } if (err) host->ios.signal_voltage = old_signal_voltage; @@ -1587,13 +2963,27 @@ cmd.arg = 0; cmd.flags = MMC_RSP_R1 | MMC_CMD_AC; + /* + * Hold the clock reference so clock doesn't get auto gated during this + * voltage switch sequence. + */ + mmc_host_clk_hold(host); err = mmc_wait_for_cmd(host, &cmd, 0); - if (err) - return err; - - if (!mmc_host_is_spi(host) && (cmd.resp[0] & R1_ERROR)) - return -EIO; + if (err) { + if (err == -ETIMEDOUT) { + pr_debug("%s: voltage switching failed with err %d\n", + mmc_hostname(host), err); + err = -EAGAIN; + goto power_cycle; + } else { + goto err_command; + } + } + if (!mmc_host_is_spi(host) && (cmd.resp[0] & R1_ERROR)) { + err = -EIO; + goto err_command; + } /* * The card should drive cmd and dat[0:3] low immediately * after the response of cmd11, but wait 1 ms to be sure @@ -1607,6 +2997,7 @@ * During a signal voltage level switch, the clock must be gated * for 5 ms according to the SD spec */ + host->card_clock_off = true; clock = host->ios.clock; host->ios.clock = 0; mmc_set_ios(host); @@ -1617,6 +3008,9 @@ * sent CMD11, so a power cycle is required anyway */ err = -EAGAIN; + host->ios.clock = clock; + mmc_set_ios(host); + host->card_clock_off = false; goto power_cycle; } @@ -1625,6 +3019,7 @@ host->ios.clock = clock; mmc_set_ios(host); + host->card_clock_off = false; /* Wait for at least 1 ms according to spec */ mmc_delay(1); @@ -1642,6 +3037,9 @@ mmc_power_cycle(host, ocr); } +err_command: + mmc_host_clk_release(host); + return err; } @@ -1650,8 +3048,10 @@ */ void mmc_set_timing(struct mmc_host *host, unsigned int timing) { + mmc_host_clk_hold(host); host->ios.timing = timing; mmc_set_ios(host); + mmc_host_clk_release(host); } /* @@ -1659,8 +3059,10 @@ */ void mmc_set_driver_type(struct mmc_host *host, unsigned int drv_type) { + mmc_host_clk_hold(host); host->ios.drv_type = drv_type; mmc_set_ios(host); + mmc_host_clk_release(host); } int mmc_select_drive_strength(struct mmc_card *card, unsigned int max_dtr, @@ -1668,6 +3070,7 @@ { struct mmc_host *host = card->host; int host_drv_type = SD_DRIVER_TYPE_B; + int drive_strength; *drv_type = 0; @@ -1690,10 +3093,14 @@ * information and let the hardware specific code * return what is possible given the options */ - return host->ops->select_drive_strength(card, max_dtr, + mmc_host_clk_hold(host); + drive_strength = host->ops->select_drive_strength(card, max_dtr, host_drv_type, card_drv_type, drv_type); + mmc_host_clk_release(host); + + return drive_strength; } /* @@ -1712,6 +3119,8 @@ if (host->ios.power_mode == MMC_POWER_ON) return; + mmc_host_clk_hold(host); + mmc_pwrseq_pre_power_on(host); host->ios.vdd = fls(ocr) - 1; @@ -1745,6 +3154,8 @@ * time required to reach a stable voltage. */ mmc_delay(10); + + mmc_host_clk_release(host); } void mmc_power_off(struct mmc_host *host) @@ -1752,6 +3163,8 @@ if (host->ios.power_mode == MMC_POWER_OFF) return; + mmc_host_clk_hold(host); + mmc_pwrseq_power_off(host); host->ios.clock = 0; @@ -1767,6 +3180,8 @@ * can be successfully turned on again. */ mmc_delay(1); + + mmc_host_clk_release(host); } void mmc_power_cycle(struct mmc_host *host, u32 ocr) @@ -1816,6 +3231,51 @@ spin_unlock_irqrestore(&host->lock, flags); } +int mmc_resume_bus(struct mmc_host *host) +{ + unsigned long flags; + int err = 0; + + if (!mmc_bus_needs_resume(host)) + return -EINVAL; + + pr_debug("%s: Starting deferred resume\n", mmc_hostname(host)); + spin_lock_irqsave(&host->lock, flags); + host->bus_resume_flags &= ~MMC_BUSRESUME_NEEDS_RESUME; + spin_unlock_irqrestore(&host->lock, flags); + + mmc_bus_get(host); + if (host->bus_ops && !host->bus_dead && host->card) { + mmc_power_up(host, host->card->ocr); + BUG_ON(!host->bus_ops->resume); + err = host->bus_ops->resume(host); + if (err) { + pr_err("%s: bus resume: failed: %d\n", + mmc_hostname(host), err); + err = mmc_hw_reset(host); + if (err) { + pr_err("%s: reset: failed: %d\n", + mmc_hostname(host), err); + goto err_reset; + } else { + mmc_card_clr_suspended(host->card); + } + } + if (mmc_card_cmdq(host->card)) { + err = mmc_cmdq_halt(host, false); + if (err) + pr_err("%s: %s: unhalt failed: %d\n", + mmc_hostname(host), __func__, err); + } + } + +err_reset: + mmc_bus_put(host); + pr_debug("%s: Deferred resume completed\n", mmc_hostname(host)); + return err; +} +EXPORT_SYMBOL(mmc_resume_bus); + /* * Assign a mmc bus handler to a host. Only one bus handler may control a * host at any given time. @@ -1881,6 +3341,13 @@ pm_wakeup_event(mmc_dev(host), 5000); host->detect_change = 1; + /* + * Change in cd_gpio state, so make sure detection part is + * not overided because of manual resume. + */ + if (cd_irq && mmc_bus_manual_resume(host)) + host->ignore_bus_resume_flags = true; + mmc_schedule_delayed_work(&host->detect, delay); } @@ -1982,7 +3449,7 @@ */ timeout_clks <<= 1; timeout_us += (timeout_clks * 1000) / - (card->host->ios.clock / 1000); + (mmc_host_clk_rate(card->host) / 1000); erase_timeout = timeout_us / 1000; @@ -2049,15 +3516,9 @@ return mmc_mmc_erase_timeout(card, arg, qty); } -static int mmc_do_erase(struct mmc_card *card, unsigned int from, - unsigned int to, unsigned int arg) +static u32 mmc_get_erase_qty(struct mmc_card *card, u32 from, u32 to) { - struct mmc_command cmd = {0}; - unsigned int qty = 0; - unsigned long timeout; - int err; - - mmc_retune_hold(card->host); + u32 qty = 0; /* * qty is used to calculate the erase timeout which depends on how many @@ -2083,12 +3544,122 @@ else qty += ((to / card->erase_size) - (from / card->erase_size)) + 1; + return qty; +} + +static int mmc_cmdq_send_erase_cmd(struct mmc_cmdq_req *cmdq_req, + struct mmc_card *card, u32 opcode, u32 arg, u32 qty) +{ + struct mmc_command *cmd = cmdq_req->mrq.cmd; + int err; + + memset(cmd, 0, sizeof(struct mmc_command)); + + cmd->opcode = opcode; + cmd->arg = arg; + if (cmd->opcode == MMC_ERASE) { + cmd->flags = MMC_RSP_SPI_R1B | MMC_RSP_R1B | MMC_CMD_AC; + cmd->busy_timeout = mmc_erase_timeout(card, arg, qty); + } else { + cmd->flags = MMC_RSP_SPI_R1 | MMC_RSP_R1 | MMC_CMD_AC; + } + + err = mmc_cmdq_wait_for_dcmd(card->host, cmdq_req); + if (err) { + pr_err("mmc_erase: group start error %d, status %#x\n", + err, cmd->resp[0]); + return -EIO; + } + return 0; +} + +static int mmc_cmdq_do_erase(struct mmc_cmdq_req *cmdq_req, + struct mmc_card *card, unsigned int from, + unsigned int to, unsigned int arg) +{ + struct mmc_command *cmd = cmdq_req->mrq.cmd; + unsigned int qty = 0; + unsigned long timeout; + unsigned int fr, nr; + int err; + + fr = from; + nr = to - from + 1; + trace_mmc_blk_erase_start(arg, fr, nr); + + qty = mmc_get_erase_qty(card, from, to); + + if (!mmc_card_blockaddr(card)) { + from <<= 9; + to <<= 9; + } + + err = mmc_cmdq_send_erase_cmd(cmdq_req, card, MMC_ERASE_GROUP_START, + from, qty); + if (err) + goto out; + + err = mmc_cmdq_send_erase_cmd(cmdq_req, card, MMC_ERASE_GROUP_END, + to, qty); + if (err) + goto out; + + err = mmc_cmdq_send_erase_cmd(cmdq_req, card, MMC_ERASE, + arg, qty); + if (err) + goto out; + + timeout = jiffies + msecs_to_jiffies(MMC_CORE_TIMEOUT_MS); + do { + memset(cmd, 0, sizeof(struct mmc_command)); + cmd->opcode = MMC_SEND_STATUS; + cmd->arg = card->rca << 16; + cmd->flags = MMC_RSP_R1 | MMC_CMD_AC; + /* Do not retry else we can't see errors */ + err = mmc_cmdq_wait_for_dcmd(card->host, cmdq_req); + if (err || (cmd->resp[0] & 0xFDF92000)) { + pr_err("error %d requesting status %#x\n", + err, cmd->resp[0]); + err = -EIO; + goto out; + } + /* Timeout if the device never becomes ready for data and + * never leaves the program state. + */ + if (time_after(jiffies, timeout)) { + pr_err("%s: Card stuck in programming state! %s\n", + mmc_hostname(card->host), __func__); + err = -EIO; + goto out; + } + } while (!(cmd->resp[0] & R1_READY_FOR_DATA) || + (R1_CURRENT_STATE(cmd->resp[0]) == R1_STATE_PRG)); +out: + trace_mmc_blk_erase_end(arg, fr, nr); + return err; +} + +static int mmc_do_erase(struct mmc_card *card, unsigned int from, + unsigned int to, unsigned int arg) +{ + struct mmc_command cmd = {0}; + unsigned int qty = 0; + unsigned long timeout; + unsigned int fr, nr; + int err; + + fr = from; + nr = to - from + 1; + trace_mmc_blk_erase_start(arg, fr, nr); + + qty = mmc_get_erase_qty(card, from, to); if (!mmc_card_blockaddr(card)) { from <<= 9; to <<= 9; } + mmc_retune_hold(card->host); if (mmc_card_sd(card)) cmd.opcode = SD_ERASE_WR_BLK_START; else @@ -2163,24 +3734,13 @@ (R1_CURRENT_STATE(cmd.resp[0]) == R1_STATE_PRG)); out: mmc_retune_release(card->host); + trace_mmc_blk_erase_end(arg, fr, nr); return err; } -/** - * mmc_erase - erase sectors. - * @card: card to erase - * @from: first sector to erase - * @nr: number of sectors to erase - * @arg: erase command argument (SD supports only %MMC_ERASE_ARG) - * - * Caller must claim host before calling this function. - */ -int mmc_erase(struct mmc_card *card, unsigned int from, unsigned int nr, - unsigned int arg) +int mmc_erase_sanity_check(struct mmc_card *card, unsigned int from, + unsigned int nr, unsigned int arg) { - unsigned int rem, to = from + nr; - int err; - if (!(card->host->caps & MMC_CAP_ERASE) || !(card->csd.cmdclass & CCC_ERASE)) return -EOPNOTSUPP; @@ -2203,6 +3763,68 @@ if (from % card->erase_size || nr % card->erase_size) return -EINVAL; } + return 0; +} + +int mmc_cmdq_erase(struct mmc_cmdq_req *cmdq_req, + struct mmc_card *card, unsigned int from, unsigned int nr, + unsigned int arg) +{ + unsigned int rem, to = from + nr; + int ret; + + ret = mmc_erase_sanity_check(card, from, nr, arg); + if (ret) + return ret; + + if (arg == MMC_ERASE_ARG) { + rem = from % card->erase_size; + if (rem) { + rem = card->erase_size - rem; + from += rem; + if (nr > rem) + nr -= rem; + else + return 0; + } + rem = nr % card->erase_size; + if (rem) + nr -= rem; + } + + if (nr == 0) + return 0; + + to = from + nr; + + if (to <= from) + return -EINVAL; + + /* 'from' and 'to' are inclusive */ + to -= 1; + + return mmc_cmdq_do_erase(cmdq_req, card, from, to, arg); +} +EXPORT_SYMBOL(mmc_cmdq_erase); + +/** + * mmc_erase - erase sectors. + * @card: card to erase + * @from: first sector to erase + * @nr: number of sectors to erase + * @arg: erase command argument (SD supports only %MMC_ERASE_ARG) + * + * Caller must claim host before calling this function. + */ +int mmc_erase(struct mmc_card *card, unsigned int from, unsigned int nr, + unsigned int arg) +{ + unsigned int rem, to = from + nr; + int ret; + + ret = mmc_erase_sanity_check(card, from, nr, arg); + if (ret) + return ret; if (arg == MMC_ERASE_ARG) { rem = from % card->erase_size; @@ -2240,10 +3862,10 @@ */ rem = card->erase_size - (from % card->erase_size); if ((arg & MMC_TRIM_ARGS) && (card->eg_boundary) && (nr > rem)) { - err = mmc_do_erase(card, from, from + rem - 1, arg); + ret = mmc_do_erase(card, from, from + rem - 1, arg); from += rem; - if ((err) || (to <= from)) - return err; + if ((ret) || (to <= from)) + return ret; } return mmc_do_erase(card, from, to, arg); @@ -2373,7 +3995,8 @@ struct mmc_host *host = card->host; unsigned int max_discard, max_trim; - if (!host->max_busy_timeout) + if (!host->max_busy_timeout || + (host->caps2 & MMC_CAP2_MAX_DISCARD_SIZE)) return UINT_MAX; /* @@ -2430,9 +4053,26 @@ { if (!(host->caps & MMC_CAP_HW_RESET) || !host->ops->hw_reset) return; + mmc_host_clk_hold(host); host->ops->hw_reset(host); + mmc_host_clk_release(host); } +/* + * mmc_cmdq_hw_reset: Helper API for doing + * reset_all of host and reinitializing card. + * This must be called with mmc_claim_host + * acquired by the caller. + */ +int mmc_cmdq_hw_reset(struct mmc_host *host) +{ + if (!host->bus_ops->reset) + return -EOPNOTSUPP; + + return host->bus_ops->reset(host); +} +EXPORT_SYMBOL(mmc_cmdq_hw_reset); + int mmc_hw_reset(struct mmc_host *host) { int ret; @@ -2449,8 +4089,9 @@ ret = host->bus_ops->reset(host); mmc_bus_put(host); - if (ret != -EOPNOTSUPP) - pr_warn("%s: tried to reset card\n", mmc_hostname(host)); + if (ret) + pr_warn("%s: tried to reset card, got error %d\n", + mmc_hostname(host), ret); return ret; } @@ -2519,8 +4160,17 @@ } if (ret) { + if (host->ops->get_cd && host->ops->get_cd(host)) { + ret = mmc_recovery_fallback_lower_speed(host); + } else { mmc_card_set_removed(host->card); - pr_debug("%s: card remove detected\n", mmc_hostname(host)); + if (host->card->sdr104_blocked) { + mmc_host_set_sdr104(host); + host->card->sdr104_blocked = false; + } + pr_debug("%s: card remove detected\n", + mmc_hostname(host)); + } } return ret; @@ -2561,19 +4211,35 @@ } EXPORT_SYMBOL(mmc_detect_card_removed); +/* + * This should be called to make sure that detect work(mmc_rescan) + * is completed.Drivers may use this function from async schedule/probe + * contexts to make sure that the bootdevice detection is completed on + * completion of async_schedule. + */ +void mmc_flush_detect_work(struct mmc_host *host) +{ + flush_delayed_work(&host->detect); +} +EXPORT_SYMBOL(mmc_flush_detect_work); + void mmc_rescan(struct work_struct *work) { + unsigned long flags; struct mmc_host *host = container_of(work, struct mmc_host, detect.work); - int i; if (host->trigger_card_event && host->ops->card_event) { host->ops->card_event(host); host->trigger_card_event = false; } - if (host->rescan_disable) + spin_lock_irqsave(&host->lock, flags); + if (host->rescan_disable) { + spin_unlock_irqrestore(&host->lock, flags); return; + } + spin_unlock_irqrestore(&host->lock, flags); /* If there is a non-removable card registered, only scan once */ if ((host->caps & MMC_CAP_NONREMOVABLE) && host->rescan_entered) @@ -2591,6 +4257,8 @@ host->bus_ops->detect(host); host->detect_change = 0; + if (host->ignore_bus_resume_flags) + host->ignore_bus_resume_flags = false; /* * Let mmc_bus_put() free the bus/bus_ops if we've found that @@ -2620,12 +4288,7 @@ } mmc_claim_host(host); - for (i = 0; i < ARRAY_SIZE(freqs); i++) { - if (!mmc_rescan_try_freq(host, max(freqs[i], host->f_min))) - break; - if (freqs[i] <= host->f_min) - break; - } + mmc_rescan_try_freq(host, host->f_min); mmc_release_host(host); out: @@ -2635,18 +4298,18 @@ void mmc_start_host(struct mmc_host *host) { + mmc_claim_host(host); host->f_init = max(freqs[0], host->f_min); host->rescan_disable = 0; host->ios.power_mode = MMC_POWER_UNDEFINED; - mmc_claim_host(host); if (host->caps2 & MMC_CAP2_NO_PRESCAN_POWERUP) mmc_power_off(host); else mmc_power_up(host, host->ocr_avail); - mmc_release_host(host); mmc_gpiod_request_cd_irq(host); + mmc_release_host(host); _mmc_detect_change(host, 0, false); } @@ -2730,7 +4393,9 @@ } mmc_power_up(host, host->card->ocr); + mmc_claim_host(host); ret = host->bus_ops->power_restore(host); + mmc_release_host(host); mmc_bus_put(host); @@ -2739,6 +4404,40 @@ EXPORT_SYMBOL(mmc_power_restore_host); /* + * Add barrier request to the requests in cache + */ +int mmc_cache_barrier(struct mmc_card *card) +{ + struct mmc_host *host = card->host; + int err = 0; + + if (!card->ext_csd.cache_ctrl || + (card->quirks & MMC_QUIRK_CACHE_DISABLE)) + goto out; + + if (!mmc_card_mmc(card)) + goto out; + + if (!card->ext_csd.barrier_en) + return -ENOTSUPP; + + /* + * If a device receives maximum supported barrier + * requests, a barrier command is treated as a + * flush command. Hence, it is betetr to use + * flush timeout instead a generic CMD6 timeout + */ + err = mmc_switch(card, EXT_CSD_CMD_SET_NORMAL, + EXT_CSD_FLUSH_CACHE, 0x2, 0); + if (err) + pr_err("%s: cache barrier error %d\n", + mmc_hostname(host), err); +out: + return err; +} +EXPORT_SYMBOL(mmc_cache_barrier); + +/* * Flush the cache to the non-volatile storage. */ int mmc_flush_cache(struct mmc_card *card) @@ -2747,13 +4446,24 @@ if (mmc_card_mmc(card) && (card->ext_csd.cache_size > 0) && - (card->ext_csd.cache_ctrl & 1)) { + (card->ext_csd.cache_ctrl & 1) && + (!(card->quirks & MMC_QUIRK_CACHE_DISABLE))) { err = mmc_switch(card, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_FLUSH_CACHE, 1, 0); - if (err) + if (err == -ETIMEDOUT) { + pr_err("%s: cache flush timeout\n", + mmc_hostname(card->host)); + err = mmc_interrupt_hpi(card); + if (err) { + pr_err("%s: mmc_interrupt_hpi() failed (%d)\n", + mmc_hostname(card->host), err); + err = -ENODEV; + } + } else if (err) { pr_err("%s: cache flush error %d\n", mmc_hostname(card->host), err); } + } return err; } @@ -2806,6 +4516,11 @@ spin_lock_irqsave(&host->lock, flags); host->rescan_disable = 0; + if (mmc_bus_manual_resume(host) && + !host->ignore_bus_resume_flags) { + spin_unlock_irqrestore(&host->lock, flags); + break; + } spin_unlock_irqrestore(&host->lock, flags); _mmc_detect_change(host, 0, false); @@ -2832,6 +4547,22 @@ init_waitqueue_head(&host->context_info.wait); } +#ifdef CONFIG_MMC_EMBEDDED_SDIO +void mmc_set_embedded_sdio_data(struct mmc_host *host, + struct sdio_cis *cis, + struct sdio_cccr *cccr, + struct sdio_embedded_func *funcs, + int num_funcs) +{ + host->embedded_sdio_data.cis = cis; + host->embedded_sdio_data.cccr = cccr; + host->embedded_sdio_data.funcs = funcs; + host->embedded_sdio_data.num_funcs = num_funcs; +} + +EXPORT_SYMBOL(mmc_set_embedded_sdio_data); +#endif + static int __init mmc_init(void) { int ret; @@ -2872,6 +4603,63 @@ destroy_workqueue(workqueue); } +#ifdef CONFIG_BLOCK +static ssize_t +latency_hist_show(struct device *dev, struct device_attribute *attr, char *buf) +{ + struct mmc_host *host = cls_dev_to_mmc_host(dev); + size_t written_bytes; + + written_bytes = blk_latency_hist_show("Read", &host->io_lat_read, + buf, PAGE_SIZE); + written_bytes += blk_latency_hist_show("Write", &host->io_lat_write, + buf + written_bytes, PAGE_SIZE - written_bytes); + + return written_bytes; +} + +/* + * Values permitted 0, 1, 2. + * 0 -> Disable IO latency histograms (default) + * 1 -> Enable IO latency histograms + * 2 -> Zero out IO latency histograms + */ +static ssize_t +latency_hist_store(struct device *dev, struct device_attribute *attr, + const char *buf, size_t count) +{ + struct mmc_host *host = cls_dev_to_mmc_host(dev); + long value; + + if (kstrtol(buf, 0, &value)) + return -EINVAL; + if (value == BLK_IO_LAT_HIST_ZERO) { + memset(&host->io_lat_read, 0, sizeof(host->io_lat_read)); + memset(&host->io_lat_write, 0, sizeof(host->io_lat_write)); + } else if (value == BLK_IO_LAT_HIST_ENABLE || + value == BLK_IO_LAT_HIST_DISABLE) + host->latency_hist_enabled = value; + return count; +} + +static DEVICE_ATTR(latency_hist, S_IRUGO | S_IWUSR, + latency_hist_show, latency_hist_store); + +void +mmc_latency_hist_sysfs_init(struct mmc_host *host) +{ + if (device_create_file(&host->class_dev, &dev_attr_latency_hist)) + dev_err(&host->class_dev, + "Failed to create latency_hist sysfs entry\n"); +} + +void +mmc_latency_hist_sysfs_exit(struct mmc_host *host) +{ + device_remove_file(&host->class_dev, &dev_attr_latency_hist); +} +#endif + subsys_initcall(mmc_init); module_exit(mmc_exit); diff -ruw linux-4.4.115/drivers/mmc/core/core.h linux-4.4.115-fbx/drivers/mmc/core/core.h --- linux-4.4.115/drivers/mmc/core/core.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/mmc/core/core.h 2019-01-22 16:16:24.767257853 +0100 @@ -15,21 +15,6 @@ #define MMC_CMD_RETRIES 3 -struct mmc_bus_ops { - void (*remove)(struct mmc_host *); - void (*detect)(struct mmc_host *); - int (*pre_suspend)(struct mmc_host *); - int (*suspend)(struct mmc_host *); - int (*resume)(struct mmc_host *); - int (*runtime_suspend)(struct mmc_host *); - int (*runtime_resume)(struct mmc_host *); - int (*power_save)(struct mmc_host *); - int (*power_restore)(struct mmc_host *); - int (*alive)(struct mmc_host *); - int (*shutdown)(struct mmc_host *); - int (*reset)(struct mmc_host *); -}; - void mmc_attach_bus(struct mmc_host *host, const struct mmc_bus_ops *ops); void mmc_detach_bus(struct mmc_host *host); @@ -40,6 +25,11 @@ void mmc_set_chip_select(struct mmc_host *host, int mode); void mmc_set_clock(struct mmc_host *host, unsigned int hz); +int mmc_clk_update_freq(struct mmc_host *host, + unsigned long freq, enum mmc_load state); +void mmc_gate_clock(struct mmc_host *host); +void mmc_ungate_clock(struct mmc_host *host); +void mmc_set_ungated(struct mmc_host *host); void mmc_set_bus_mode(struct mmc_host *host, unsigned int mode); void mmc_set_bus_width(struct mmc_host *host, unsigned int width); u32 mmc_select_voltage(struct mmc_host *host, u32 ocr); @@ -59,6 +49,8 @@ if (ms < 1000 / HZ) { cond_resched(); mdelay(ms); + } else if (ms < jiffies_to_msecs(2)) { + usleep_range(ms * 1000, (ms + 1) * 1000); } else { msleep(ms); } @@ -86,6 +78,12 @@ void mmc_init_context_info(struct mmc_host *host); +extern bool mmc_can_scale_clk(struct mmc_host *host); +extern int mmc_init_clk_scaling(struct mmc_host *host); +extern int mmc_resume_clk_scaling(struct mmc_host *host); +extern int mmc_exit_clk_scaling(struct mmc_host *host); +extern unsigned long mmc_get_max_frequency(struct mmc_host *host); + int mmc_execute_tuning(struct mmc_card *card); int mmc_hs200_to_hs400(struct mmc_card *card); int mmc_hs400_to_hs200(struct mmc_card *card); diff -ruw linux-4.4.115/drivers/mmc/core/debugfs.c linux-4.4.115-fbx/drivers/mmc/core/debugfs.c --- linux-4.4.115/drivers/mmc/core/debugfs.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/mmc/core/debugfs.c 2019-10-29 09:26:24.057207230 +0100 @@ -15,6 +15,7 @@ #include #include #include +#include #include #include @@ -31,6 +32,26 @@ #endif /* CONFIG_FAIL_MMC_REQUEST */ /* The debugfs functions are optimized away when CONFIG_DEBUG_FS isn't set. */ +static int mmc_ring_buffer_show(struct seq_file *s, void *data) +{ + struct mmc_host *mmc = s->private; + + mmc_dump_trace_buffer(mmc, s); + return 0; +} + +static int mmc_ring_buffer_open(struct inode *inode, struct file *file) +{ + return single_open(file, mmc_ring_buffer_show, inode->i_private); +} + +static const struct file_operations mmc_ring_buffer_fops = { + .open = mmc_ring_buffer_open, + .read = seq_read, + .llseek = seq_lseek, + .release = single_release, +}; + static int mmc_ios_show(struct seq_file *s, void *data) { static const char *vdd_str[] = { @@ -233,6 +254,132 @@ DEFINE_SIMPLE_ATTRIBUTE(mmc_clock_fops, mmc_clock_opt_get, mmc_clock_opt_set, "%llu\n"); +#include + +static int mmc_scale_get(void *data, u64 *val) +{ + struct mmc_host *host = data; + + *val = host->clk_scaling.curr_freq; + + return 0; +} + +static int mmc_scale_set(void *data, u64 val) +{ + int err = 0; + struct mmc_host *host = data; + + mmc_claim_host(host); + mmc_host_clk_hold(host); + + /* change frequency from sysfs manually */ + err = mmc_clk_update_freq(host, val, host->clk_scaling.state); + if (err == -EAGAIN) + err = 0; + else if (err) + pr_err("%s: clock scale to %llu failed with error %d\n", + mmc_hostname(host), val, err); + else + pr_debug("%s: clock change to %llu finished successfully (%s)\n", + mmc_hostname(host), val, current->comm); + + mmc_host_clk_release(host); + mmc_release_host(host); + + return err; +} + +DEFINE_SIMPLE_ATTRIBUTE(mmc_scale_fops, mmc_scale_get, mmc_scale_set, + "%llu\n"); + +static int mmc_max_clock_get(void *data, u64 *val) +{ + struct mmc_host *host = data; + + if (!host) + return -EINVAL; + + *val = host->f_max; + + return 0; +} + +static int mmc_max_clock_set(void *data, u64 val) +{ + struct mmc_host *host = data; + int err = -EINVAL; + unsigned long freq = val; + unsigned int old_freq; + + if (!host || (val < host->f_min)) + goto out; + + mmc_claim_host(host); + if (host->bus_ops && host->bus_ops->change_bus_speed) { + old_freq = host->f_max; + host->f_max = freq; + + err = host->bus_ops->change_bus_speed(host, &freq); + + if (err) + host->f_max = old_freq; + } + mmc_release_host(host); +out: + return err; +} + +DEFINE_SIMPLE_ATTRIBUTE(mmc_max_clock_fops, mmc_max_clock_get, + mmc_max_clock_set, "%llu\n"); + +static int mmc_force_err_set(void *data, u64 val) +{ + struct mmc_host *host = data; + + if (host && host->card && host->ops && + host->ops->force_err_irq) { + /* + * To access the force error irq reg, we need to make + * sure the host is powered up and host clock is ticking. + */ + mmc_get_card(host->card); + host->ops->force_err_irq(host, val); + mmc_put_card(host->card); + } + + return 0; +} + +DEFINE_SIMPLE_ATTRIBUTE(mmc_force_err_fops, NULL, mmc_force_err_set, "%llu\n"); + +static int mmc_err_state_get(void *data, u64 *val) +{ + struct mmc_host *host = data; + + if (!host) + return -EINVAL; + + *val = host->err_occurred ? 1 : 0; + + return 0; +} + +static int mmc_err_state_clear(void *data, u64 val) +{ + struct mmc_host *host = data; + + if (!host) + return -EINVAL; + + host->err_occurred = false; + + return 0; +} + +DEFINE_SIMPLE_ATTRIBUTE(mmc_err_state, mmc_err_state_get, + mmc_err_state_clear, "%llu\n"); + void mmc_add_host_debugfs(struct mmc_host *host) { struct dentry *root; @@ -255,6 +402,38 @@ &mmc_clock_fops)) goto err_node; + if (!debugfs_create_file("max_clock", S_IRUSR | S_IWUSR, root, host, + &mmc_max_clock_fops)) + goto err_node; + + if (!debugfs_create_file("scale", S_IRUSR | S_IWUSR, root, host, + &mmc_scale_fops)) + goto err_node; + + if (!debugfs_create_bool("skip_clk_scale_freq_update", + S_IRUSR | S_IWUSR, root, + &host->clk_scaling.skip_clk_scale_freq_update)) + goto err_node; + + if (!debugfs_create_bool("cmdq_task_history", + S_IRUSR | S_IWUSR, root, + &host->cmdq_thist_enabled)) + goto err_node; + +#ifdef CONFIG_MMC_RING_BUFFER + if (!debugfs_create_file("ring_buffer", S_IRUSR, + root, host, &mmc_ring_buffer_fops)) + goto err_node; +#endif + if (!debugfs_create_file("err_state", S_IRUSR | S_IWUSR, root, host, + &mmc_err_state)) + goto err_node; + +#ifdef CONFIG_MMC_CLKGATE + if (!debugfs_create_u32("clk_delay", (S_IRUSR | S_IWUSR), + root, &host->clk_delay)) + goto err_node; +#endif #ifdef CONFIG_FAIL_MMC_REQUEST if (fail_request) setup_fault_attr(&fail_default_attr, fail_request); @@ -264,6 +443,10 @@ &host->fail_mmc_request))) goto err_node; #endif + if (!debugfs_create_file("force_error", S_IWUSR, root, host, + &mmc_force_err_fops)) + goto err_node; + return; err_node: @@ -285,11 +468,26 @@ int ret; mmc_get_card(card); + if (mmc_card_cmdq(card)) { + ret = mmc_cmdq_halt_on_empty_queue(card->host); + if (ret) { + pr_err("%s: halt failed while doing %s err (%d)\n", + mmc_hostname(card->host), __func__, + ret); + goto out; + } + } ret = mmc_send_status(data, &status); if (!ret) *val = status; + if (mmc_card_cmdq(card)) { + if (mmc_cmdq_halt(card->host, false)) + pr_err("%s: %s: cmdq unhalt failed\n", + mmc_hostname(card->host), __func__); + } +out: mmc_put_card(card); return ret; @@ -312,8 +510,18 @@ return -ENOMEM; mmc_get_card(card); - err = mmc_get_ext_csd(card, &ext_csd); + if (mmc_card_cmdq(card)) { + err = mmc_cmdq_halt_on_empty_queue(card->host); + if (err) { + pr_err("%s: halt failed while doing %s err (%d)\n", + mmc_hostname(card->host), __func__, + err); mmc_put_card(card); + goto out_free_halt; + } + } + + err = mmc_get_ext_csd(card, &ext_csd); if (err) goto out_free; @@ -323,10 +531,25 @@ BUG_ON(n != EXT_CSD_STR_LEN); filp->private_data = buf; + + if (mmc_card_cmdq(card)) { + if (mmc_cmdq_halt(card->host, false)) + pr_err("%s: %s: cmdq unhalt failed\n", + mmc_hostname(card->host), __func__); + } + + mmc_put_card(card); kfree(ext_csd); return 0; out_free: + if (mmc_card_cmdq(card)) { + if (mmc_cmdq_halt(card->host, false)) + pr_err("%s: %s: cmdq unhalt failed\n", + mmc_hostname(card->host), __func__); + } + mmc_put_card(card); +out_free_halt: kfree(buf); return err; } @@ -353,6 +576,296 @@ .llseek = default_llseek, }; +static int mmc_wr_pack_stats_open(struct inode *inode, struct file *filp) +{ + struct mmc_card *card = inode->i_private; + + filp->private_data = card; + card->wr_pack_stats.print_in_read = 1; + return 0; +} + +#define TEMP_BUF_SIZE 256 +static ssize_t mmc_wr_pack_stats_read(struct file *filp, char __user *ubuf, + size_t cnt, loff_t *ppos) +{ + struct mmc_card *card = filp->private_data; + struct mmc_wr_pack_stats *pack_stats; + int i, ret = 0; + int max_num_of_packed_reqs = 0; + char *temp_buf, *temp_ubuf; + size_t tubuf_cnt = 0; + + if (!card) + return cnt; + + if (!access_ok(VERIFY_WRITE, ubuf, cnt)) + return cnt; + + if (!card->wr_pack_stats.print_in_read) + return 0; + + if (!card->wr_pack_stats.enabled) { + pr_info("%s: write packing statistics are disabled\n", + mmc_hostname(card->host)); + goto exit; + } + + pack_stats = &card->wr_pack_stats; + + if (!pack_stats->packing_events) { + pr_info("%s: NULL packing_events\n", mmc_hostname(card->host)); + goto exit; + } + + max_num_of_packed_reqs = card->ext_csd.max_packed_writes; + + if (cnt <= (strlen_user(ubuf) + 1)) + goto exit; + + temp_buf = kzalloc(TEMP_BUF_SIZE, GFP_KERNEL); + if (!temp_buf) + goto exit; + + tubuf_cnt = cnt - strlen_user(ubuf) - 1; + + temp_ubuf = kzalloc(tubuf_cnt, GFP_KERNEL); + if (!temp_ubuf) + goto cleanup; + + spin_lock(&pack_stats->lock); + + snprintf(temp_buf, TEMP_BUF_SIZE, "%s: write packing statistics:\n", + mmc_hostname(card->host)); + strlcat(temp_ubuf, temp_buf, tubuf_cnt); + + for (i = 1 ; i <= max_num_of_packed_reqs ; ++i) { + if (pack_stats->packing_events[i]) { + snprintf(temp_buf, TEMP_BUF_SIZE, + "%s: Packed %d reqs - %d times\n", + mmc_hostname(card->host), i, + pack_stats->packing_events[i]); + strlcat(temp_ubuf, temp_buf, tubuf_cnt); + } + } + + snprintf(temp_buf, TEMP_BUF_SIZE, + "%s: stopped packing due to the following reasons:\n", + mmc_hostname(card->host)); + strlcat(temp_ubuf, temp_buf, tubuf_cnt); + + if (pack_stats->pack_stop_reason[EXCEEDS_SEGMENTS]) { + snprintf(temp_buf, TEMP_BUF_SIZE, + "%s: %d times: exceed max num of segments\n", + mmc_hostname(card->host), + pack_stats->pack_stop_reason[EXCEEDS_SEGMENTS]); + strlcat(temp_ubuf, temp_buf, tubuf_cnt); + } + if (pack_stats->pack_stop_reason[EXCEEDS_SECTORS]) { + snprintf(temp_buf, TEMP_BUF_SIZE, + "%s: %d times: exceed max num of sectors\n", + mmc_hostname(card->host), + pack_stats->pack_stop_reason[EXCEEDS_SECTORS]); + strlcat(temp_ubuf, temp_buf, tubuf_cnt); + } + if (pack_stats->pack_stop_reason[WRONG_DATA_DIR]) { + snprintf(temp_buf, TEMP_BUF_SIZE, + "%s: %d times: wrong data direction\n", + mmc_hostname(card->host), + pack_stats->pack_stop_reason[WRONG_DATA_DIR]); + strlcat(temp_ubuf, temp_buf, tubuf_cnt); + } + if (pack_stats->pack_stop_reason[FLUSH_OR_DISCARD]) { + snprintf(temp_buf, TEMP_BUF_SIZE, + "%s: %d times: flush or discard\n", + mmc_hostname(card->host), + pack_stats->pack_stop_reason[FLUSH_OR_DISCARD]); + strlcat(temp_ubuf, temp_buf, tubuf_cnt); + } + if (pack_stats->pack_stop_reason[EMPTY_QUEUE]) { + snprintf(temp_buf, TEMP_BUF_SIZE, + "%s: %d times: empty queue\n", + mmc_hostname(card->host), + pack_stats->pack_stop_reason[EMPTY_QUEUE]); + strlcat(temp_ubuf, temp_buf, tubuf_cnt); + } + if (pack_stats->pack_stop_reason[REL_WRITE]) { + snprintf(temp_buf, TEMP_BUF_SIZE, + "%s: %d times: rel write\n", + mmc_hostname(card->host), + pack_stats->pack_stop_reason[REL_WRITE]); + strlcat(temp_ubuf, temp_buf, tubuf_cnt); + } + if (pack_stats->pack_stop_reason[THRESHOLD]) { + snprintf(temp_buf, TEMP_BUF_SIZE, + "%s: %d times: Threshold\n", + mmc_hostname(card->host), + pack_stats->pack_stop_reason[THRESHOLD]); + strlcat(temp_ubuf, temp_buf, tubuf_cnt); + } + + if (pack_stats->pack_stop_reason[LARGE_SEC_ALIGN]) { + snprintf(temp_buf, TEMP_BUF_SIZE, + "%s: %d times: Large sector alignment\n", + mmc_hostname(card->host), + pack_stats->pack_stop_reason[LARGE_SEC_ALIGN]); + strlcat(temp_ubuf, temp_buf, tubuf_cnt); + } + if (pack_stats->pack_stop_reason[RANDOM]) { + snprintf(temp_buf, TEMP_BUF_SIZE, + "%s: %d times: random request\n", + mmc_hostname(card->host), + pack_stats->pack_stop_reason[RANDOM]); + strlcat(temp_ubuf, temp_buf, tubuf_cnt); + } + if (pack_stats->pack_stop_reason[FUA]) { + snprintf(temp_buf, TEMP_BUF_SIZE, + "%s: %d times: fua request\n", + mmc_hostname(card->host), + pack_stats->pack_stop_reason[FUA]); + strlcat(temp_ubuf, temp_buf, tubuf_cnt); + } + if (strlen_user(ubuf) < cnt - strlen(temp_ubuf)) + ret = copy_to_user((ubuf + strlen_user(ubuf)), + temp_ubuf, tubuf_cnt); + else + ret = -EFAULT; + if (ret) + pr_err("%s: %s: Copy to userspace failed: %s\n", + mmc_hostname(card->host), __func__, ubuf); + + spin_unlock(&pack_stats->lock); + + kfree(temp_ubuf); + +cleanup: + kfree(temp_buf); + + pr_info("%s", ubuf); + +exit: + if (card->wr_pack_stats.print_in_read == 1) { + card->wr_pack_stats.print_in_read = 0; + return strnlen(ubuf, cnt); + } + + return 0; +} + +static ssize_t mmc_wr_pack_stats_write(struct file *filp, + const char __user *ubuf, size_t cnt, + loff_t *ppos) +{ + struct mmc_card *card = filp->private_data; + int value; + + if (!card) + return cnt; + + if (!access_ok(VERIFY_READ, ubuf, cnt)) + return cnt; + + sscanf(ubuf, "%d", &value); + if (value) { + mmc_blk_init_packed_statistics(card); + } else { + spin_lock(&card->wr_pack_stats.lock); + card->wr_pack_stats.enabled = false; + spin_unlock(&card->wr_pack_stats.lock); + } + + return cnt; +} + +static const struct file_operations mmc_dbg_wr_pack_stats_fops = { + .open = mmc_wr_pack_stats_open, + .read = mmc_wr_pack_stats_read, + .write = mmc_wr_pack_stats_write, +}; + +static int mmc_bkops_stats_read(struct seq_file *file, void *data) +{ + struct mmc_card *card = file->private; + struct mmc_bkops_stats *stats; + int i; + + if (!card) + return -EINVAL; + + stats = &card->bkops.stats; + + if (!stats->enabled) { + pr_info("%s: bkops statistics are disabled\n", + mmc_hostname(card->host)); + goto exit; + } + + spin_lock(&stats->lock); + + seq_printf(file, "%s: bkops statistics:\n", + mmc_hostname(card->host)); + seq_printf(file, "%s: BKOPS: sent START_BKOPS to device: %u\n", + mmc_hostname(card->host), stats->manual_start); + seq_printf(file, "%s: BKOPS: stopped due to HPI: %u\n", + mmc_hostname(card->host), stats->hpi); + seq_printf(file, "%s: BKOPS: sent AUTO_EN set to 1: %u\n", + mmc_hostname(card->host), stats->auto_start); + seq_printf(file, "%s: BKOPS: sent AUTO_EN set to 0: %u\n", + mmc_hostname(card->host), stats->auto_stop); + + for (i = 0 ; i < MMC_BKOPS_NUM_SEVERITY_LEVELS ; ++i) + seq_printf(file, "%s: BKOPS: due to level %d: %u\n", + mmc_hostname(card->host), i, stats->level[i]); + + spin_unlock(&stats->lock); + +exit: + + return 0; +} + +static ssize_t mmc_bkops_stats_write(struct file *filp, + const char __user *ubuf, size_t cnt, + loff_t *ppos) +{ + struct mmc_card *card = filp->f_mapping->host->i_private; + int value; + struct mmc_bkops_stats *stats; + int err; + + if (!card) + return cnt; + + stats = &card->bkops.stats; + + err = kstrtoint_from_user(ubuf, cnt, 0, &value); + if (err) { + pr_err("%s: %s: error parsing input from user (%d)\n", + mmc_hostname(card->host), __func__, err); + return err; + } + if (value) { + mmc_blk_init_bkops_statistics(card); + } else { + spin_lock(&stats->lock); + stats->enabled = false; + spin_unlock(&stats->lock); + } + + return cnt; +} + +static int mmc_bkops_stats_open(struct inode *inode, struct file *file) +{ + return single_open(file, mmc_bkops_stats_read, inode->i_private); +} + +static const struct file_operations mmc_dbg_bkops_stats_fops = { + .open = mmc_bkops_stats_open, + .read = seq_read, + .write = mmc_bkops_stats_write, +}; + void mmc_add_card_debugfs(struct mmc_card *card) { struct mmc_host *host = card->host; @@ -385,6 +898,19 @@ &mmc_dbg_ext_csd_fops)) goto err; + if (mmc_card_mmc(card) && (card->ext_csd.rev >= 6) && + (card->host->caps2 & MMC_CAP2_PACKED_WR)) + if (!debugfs_create_file("wr_pack_stats", S_IRUSR, root, card, + &mmc_dbg_wr_pack_stats_fops)) + goto err; + + if (mmc_card_mmc(card) && (card->ext_csd.rev >= 5) && + (mmc_card_configured_auto_bkops(card) || + mmc_card_configured_manual_bkops(card))) + if (!debugfs_create_file("bkops_stats", S_IRUSR, root, card, + &mmc_dbg_bkops_stats_fops)) + goto err; + return; err: diff -ruw linux-4.4.115/drivers/mmc/core/host.c linux-4.4.115-fbx/drivers/mmc/core/host.c --- linux-4.4.115/drivers/mmc/core/host.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/mmc/core/host.c 2019-10-29 09:26:24.057207230 +0100 @@ -4,6 +4,7 @@ * Copyright (C) 2003 Russell King, All Rights Reserved. * Copyright (C) 2007-2008 Pierre Ossman * Copyright (C) 2010 Linus Walleij + * Copyright (c) 2012, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as @@ -25,6 +26,8 @@ #include #include +#include + #include #include "core.h" @@ -33,6 +36,9 @@ #include "pwrseq.h" #define cls_dev_to_mmc_host(d) container_of(d, struct mmc_host, class_dev) +#define MMC_DEVFRQ_DEFAULT_UP_THRESHOLD 35 +#define MMC_DEVFRQ_DEFAULT_DOWN_THRESHOLD 5 +#define MMC_DEVFRQ_DEFAULT_POLLING_MSEC 100 static DEFINE_IDR(mmc_host_idr); static DEFINE_SPINLOCK(mmc_host_lock); @@ -46,9 +52,28 @@ kfree(host); } +static int mmc_host_prepare(struct device *dev) +{ + /* + * Since mmc_host is a virtual device, we don't have to do anything. + * If we return a positive value, the pm framework will consider that + * the runtime suspend and system suspend of this device is same and + * will set direct_complete flag as true. We don't want this as the + * mmc_host always has positive disable_depth and setting the flag + * will not speed up the suspend process. + * So return 0. + */ + return 0; +} + +static const struct dev_pm_ops mmc_pm_ops = { + .prepare = mmc_host_prepare, +}; + static struct class mmc_host_class = { .name = "mmc_host", .dev_release = mmc_host_classdev_release, + .pm = &mmc_pm_ops, }; int mmc_register_host_class(void) @@ -61,6 +86,259 @@ class_unregister(&mmc_host_class); } +#ifdef CONFIG_MMC_CLKGATE +static ssize_t clkgate_delay_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct mmc_host *host = cls_dev_to_mmc_host(dev); + return snprintf(buf, PAGE_SIZE, "%lu\n", host->clkgate_delay); +} + +static ssize_t clkgate_delay_store(struct device *dev, + struct device_attribute *attr, const char *buf, size_t count) +{ + struct mmc_host *host = cls_dev_to_mmc_host(dev); + unsigned long flags, value; + + if (kstrtoul(buf, 0, &value)) + return -EINVAL; + + spin_lock_irqsave(&host->clk_lock, flags); + host->clkgate_delay = value; + spin_unlock_irqrestore(&host->clk_lock, flags); + return count; +} + +/* + * Enabling clock gating will make the core call out to the host + * once up and once down when it performs a request or card operation + * intermingled in any fashion. The driver will see this through + * set_ios() operations with ios.clock field set to 0 to gate (disable) + * the block clock, and to the old frequency to enable it again. + */ +static void mmc_host_clk_gate_delayed(struct mmc_host *host) +{ + unsigned long tick_ns; + unsigned long freq = host->ios.clock; + unsigned long flags; + + if (!freq) { + pr_debug("%s: frequency set to 0 in disable function, " + "this means the clock is already disabled.\n", + mmc_hostname(host)); + return; + } + /* + * New requests may have appeared while we were scheduling, + * then there is no reason to delay the check before + * clk_disable(). + */ + spin_lock_irqsave(&host->clk_lock, flags); + + /* + * Delay n bus cycles (at least 8 from MMC spec) before attempting + * to disable the MCI block clock. The reference count may have + * gone up again after this delay due to rescheduling! + */ + if (!host->clk_requests) { + spin_unlock_irqrestore(&host->clk_lock, flags); + tick_ns = DIV_ROUND_UP(1000000000, freq); + ndelay(host->clk_delay * tick_ns); + } else { + /* New users appeared while waiting for this work */ + spin_unlock_irqrestore(&host->clk_lock, flags); + return; + } + mutex_lock(&host->clk_gate_mutex); + spin_lock_irqsave(&host->clk_lock, flags); + if (!host->clk_requests) { + spin_unlock_irqrestore(&host->clk_lock, flags); + /* This will set host->ios.clock to 0 */ + mmc_gate_clock(host); + spin_lock_irqsave(&host->clk_lock, flags); + pr_debug("%s: gated MCI clock\n", mmc_hostname(host)); + } + spin_unlock_irqrestore(&host->clk_lock, flags); + mutex_unlock(&host->clk_gate_mutex); +} + +/* + * Internal work. Work to disable the clock at some later point. + */ +static void mmc_host_clk_gate_work(struct work_struct *work) +{ + struct mmc_host *host = container_of(work, struct mmc_host, + clk_gate_work.work); + + mmc_host_clk_gate_delayed(host); +} + +/** + * mmc_host_clk_hold - ungate hardware MCI clocks + * @host: host to ungate. + * + * Makes sure the host ios.clock is restored to a non-zero value + * past this call. Increase clock reference count and ungate clock + * if we're the first user. + */ +void mmc_host_clk_hold(struct mmc_host *host) +{ + unsigned long flags; + + /* cancel any clock gating work scheduled by mmc_host_clk_release() */ + cancel_delayed_work_sync(&host->clk_gate_work); + mutex_lock(&host->clk_gate_mutex); + spin_lock_irqsave(&host->clk_lock, flags); + if (host->clk_gated) { + spin_unlock_irqrestore(&host->clk_lock, flags); + mmc_ungate_clock(host); + + spin_lock_irqsave(&host->clk_lock, flags); + pr_debug("%s: ungated MCI clock\n", mmc_hostname(host)); + } + host->clk_requests++; + spin_unlock_irqrestore(&host->clk_lock, flags); + mutex_unlock(&host->clk_gate_mutex); +} + +/** + * mmc_host_may_gate_card - check if this card may be gated + * @card: card to check. + */ +bool mmc_host_may_gate_card(struct mmc_card *card) +{ + /* If there is no card we may gate it */ + if (!card) + return true; + + /* + * SDIO3.0 card allows the clock to be gated off so check if + * that is the case or not. + */ + if (mmc_card_sdio(card) && card->cccr.async_intr_sup) + return true; + + /* + * Don't gate SDIO cards! These need to be clocked at all times + * since they may be independent systems generating interrupts + * and other events. The clock requests counter from the core will + * go down to zero since the core does not need it, but we will not + * gate the clock, because there is somebody out there that may still + * be using it. + */ + return !(card->quirks & MMC_QUIRK_BROKEN_CLK_GATING); +} + +/** + * mmc_host_clk_release - gate off hardware MCI clocks + * @host: host to gate. + * + * Calls the host driver with ios.clock set to zero as often as possible + * in order to gate off hardware MCI clocks. Decrease clock reference + * count and schedule disabling of clock. + */ +void mmc_host_clk_release(struct mmc_host *host) +{ + unsigned long flags; + + spin_lock_irqsave(&host->clk_lock, flags); + host->clk_requests--; + if (mmc_host_may_gate_card(host->card) && + !host->clk_requests) + schedule_delayed_work(&host->clk_gate_work, + msecs_to_jiffies(host->clkgate_delay)); + spin_unlock_irqrestore(&host->clk_lock, flags); +} + +/** + * mmc_host_clk_rate - get current clock frequency setting + * @host: host to get the clock frequency for. + * + * Returns current clock frequency regardless of gating. + */ +unsigned int mmc_host_clk_rate(struct mmc_host *host) +{ + unsigned long freq; + unsigned long flags; + + spin_lock_irqsave(&host->clk_lock, flags); + if (host->clk_gated) + freq = host->clk_old; + else + freq = host->ios.clock; + spin_unlock_irqrestore(&host->clk_lock, flags); + return freq; +} + +/** + * mmc_host_clk_init - set up clock gating code + * @host: host with potential clock to control + */ +static inline void mmc_host_clk_init(struct mmc_host *host) +{ + host->clk_requests = 0; + /* Hold MCI clock for 8 cycles by default */ + host->clk_delay = 8; + /* + * Default clock gating delay is 0ms to avoid wasting power. + * This value can be tuned by writing into sysfs entry. + */ + host->clkgate_delay = 0; + host->clk_gated = false; + INIT_DELAYED_WORK(&host->clk_gate_work, mmc_host_clk_gate_work); + spin_lock_init(&host->clk_lock); + mutex_init(&host->clk_gate_mutex); +} + +/** + * mmc_host_clk_exit - shut down clock gating code + * @host: host with potential clock to control + */ +static inline void mmc_host_clk_exit(struct mmc_host *host) +{ + /* + * Wait for any outstanding gate and then make sure we're + * ungated before exiting. + */ + if (cancel_delayed_work_sync(&host->clk_gate_work)) + mmc_host_clk_gate_delayed(host); + if (host->clk_gated) + mmc_host_clk_hold(host); + /* There should be only one user now */ + WARN_ON(host->clk_requests > 1); +} + +static inline void mmc_host_clk_sysfs_init(struct mmc_host *host) +{ + host->clkgate_delay_attr.show = clkgate_delay_show; + host->clkgate_delay_attr.store = clkgate_delay_store; + sysfs_attr_init(&host->clkgate_delay_attr.attr); + host->clkgate_delay_attr.attr.name = "clkgate_delay"; + host->clkgate_delay_attr.attr.mode = S_IRUGO | S_IWUSR; + if (device_create_file(&host->class_dev, &host->clkgate_delay_attr)) + pr_err("%s: Failed to create clkgate_delay sysfs entry\n", + mmc_hostname(host)); +} +#else + +static inline void mmc_host_clk_init(struct mmc_host *host) +{ +} + +static inline void mmc_host_clk_exit(struct mmc_host *host) +{ +} + +static inline void mmc_host_clk_sysfs_init(struct mmc_host *host) +{ +} + +bool mmc_host_may_gate_card(struct mmc_card *card) +{ + return false; +} +#endif + void mmc_retune_enable(struct mmc_host *host) { host->can_retune = 1; @@ -68,6 +346,7 @@ mod_timer(&host->retune_timer, jiffies + host->retune_period * HZ); } +EXPORT_SYMBOL(mmc_retune_enable); void mmc_retune_disable(struct mmc_host *host) { @@ -76,6 +355,7 @@ host->retune_now = 0; host->need_retune = 0; } +EXPORT_SYMBOL(mmc_retune_disable); void mmc_retune_timer_stop(struct mmc_host *host) { @@ -345,6 +625,8 @@ return NULL; } + mmc_host_clk_init(host); + spin_lock_init(&host->lock); init_waitqueue_head(&host->wq); INIT_DELAYED_WORK(&host->detect, mmc_rescan); @@ -369,6 +651,217 @@ EXPORT_SYMBOL(mmc_alloc_host); +static ssize_t show_enable(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct mmc_host *host = cls_dev_to_mmc_host(dev); + + if (!host) + return -EINVAL; + + return snprintf(buf, PAGE_SIZE, "%d\n", mmc_can_scale_clk(host)); +} + +static ssize_t store_enable(struct device *dev, + struct device_attribute *attr, const char *buf, size_t count) +{ + struct mmc_host *host = cls_dev_to_mmc_host(dev); + unsigned long value; + + if (!host || !host->card || kstrtoul(buf, 0, &value)) + return -EINVAL; + + mmc_get_card(host->card); + + if (!value) { + /* Suspend the clock scaling and mask host capability */ + if (host->clk_scaling.enable) + mmc_suspend_clk_scaling(host); + host->caps2 &= ~MMC_CAP2_CLK_SCALE; + host->clk_scaling.state = MMC_LOAD_HIGH; + /* Set to max. frequency when disabling */ + mmc_clk_update_freq(host, host->card->clk_scaling_highest, + host->clk_scaling.state); + } else if (value) { + /* Unmask host capability and resume scaling */ + host->caps2 |= MMC_CAP2_CLK_SCALE; + if (!host->clk_scaling.enable) + mmc_resume_clk_scaling(host); + } + + mmc_put_card(host->card); + + return count; +} + +static ssize_t show_up_threshold(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct mmc_host *host = cls_dev_to_mmc_host(dev); + + if (!host) + return -EINVAL; + + return snprintf(buf, PAGE_SIZE, "%d\n", host->clk_scaling.upthreshold); +} + +#define MAX_PERCENTAGE 100 +static ssize_t store_up_threshold(struct device *dev, + struct device_attribute *attr, const char *buf, size_t count) +{ + struct mmc_host *host = cls_dev_to_mmc_host(dev); + unsigned long value; + + if (!host || kstrtoul(buf, 0, &value) || (value > MAX_PERCENTAGE)) + return -EINVAL; + + host->clk_scaling.upthreshold = value; + + pr_debug("%s: clkscale_up_thresh set to %lu\n", + mmc_hostname(host), value); + return count; +} + +static ssize_t show_down_threshold(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct mmc_host *host = cls_dev_to_mmc_host(dev); + + if (!host) + return -EINVAL; + + return snprintf(buf, PAGE_SIZE, "%d\n", + host->clk_scaling.downthreshold); +} + +static ssize_t store_down_threshold(struct device *dev, + struct device_attribute *attr, const char *buf, size_t count) +{ + struct mmc_host *host = cls_dev_to_mmc_host(dev); + unsigned long value; + + if (!host || kstrtoul(buf, 0, &value) || (value > MAX_PERCENTAGE)) + return -EINVAL; + + host->clk_scaling.downthreshold = value; + + pr_debug("%s: clkscale_down_thresh set to %lu\n", + mmc_hostname(host), value); + return count; +} + +static ssize_t show_polling(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct mmc_host *host = cls_dev_to_mmc_host(dev); + + if (!host) + return -EINVAL; + + return snprintf(buf, PAGE_SIZE, "%lu milliseconds\n", + host->clk_scaling.polling_delay_ms); +} + +static ssize_t store_polling(struct device *dev, + struct device_attribute *attr, const char *buf, size_t count) +{ + struct mmc_host *host = cls_dev_to_mmc_host(dev); + unsigned long value; + + if (!host || kstrtoul(buf, 0, &value)) + return -EINVAL; + + host->clk_scaling.polling_delay_ms = value; + + pr_debug("%s: clkscale_polling_delay_ms set to %lu\n", + mmc_hostname(host), value); + return count; +} + +DEVICE_ATTR(enable, S_IRUGO | S_IWUSR, + show_enable, store_enable); +DEVICE_ATTR(polling_interval, S_IRUGO | S_IWUSR, + show_polling, store_polling); +DEVICE_ATTR(up_threshold, S_IRUGO | S_IWUSR, + show_up_threshold, store_up_threshold); +DEVICE_ATTR(down_threshold, S_IRUGO | S_IWUSR, + show_down_threshold, store_down_threshold); + +static struct attribute *clk_scaling_attrs[] = { + &dev_attr_enable.attr, + &dev_attr_up_threshold.attr, + &dev_attr_down_threshold.attr, + &dev_attr_polling_interval.attr, + NULL, +}; + +static struct attribute_group clk_scaling_attr_grp = { + .name = "clk_scaling", + .attrs = clk_scaling_attrs, +}; + +#ifdef CONFIG_MMC_PERF_PROFILING +static ssize_t +show_perf(struct device *dev, struct device_attribute *attr, char *buf) +{ + struct mmc_host *host = cls_dev_to_mmc_host(dev); + int64_t rtime_drv, wtime_drv; + unsigned long rbytes_drv, wbytes_drv, flags; + + spin_lock_irqsave(&host->lock, flags); + + rbytes_drv = host->perf.rbytes_drv; + wbytes_drv = host->perf.wbytes_drv; + + rtime_drv = ktime_to_us(host->perf.rtime_drv); + wtime_drv = ktime_to_us(host->perf.wtime_drv); + + spin_unlock_irqrestore(&host->lock, flags); + + return snprintf(buf, PAGE_SIZE, "Write performance at driver Level:" + "%lu bytes in %lld microseconds\n" + "Read performance at driver Level:" + "%lu bytes in %lld microseconds\n", + wbytes_drv, wtime_drv, + rbytes_drv, rtime_drv); +} + +static ssize_t +set_perf(struct device *dev, struct device_attribute *attr, + const char *buf, size_t count) +{ + struct mmc_host *host = cls_dev_to_mmc_host(dev); + int64_t value; + unsigned long flags; + + sscanf(buf, "%lld", &value); + spin_lock_irqsave(&host->lock, flags); + if (!value) { + memset(&host->perf, 0, sizeof(host->perf)); + host->perf_enable = false; + } else { + host->perf_enable = true; + } + spin_unlock_irqrestore(&host->lock, flags); + + return count; +} + +static DEVICE_ATTR(perf, S_IRUGO | S_IWUSR, + show_perf, set_perf); + +#endif + +static struct attribute *dev_attrs[] = { +#ifdef CONFIG_MMC_PERF_PROFILING + &dev_attr_perf.attr, +#endif + NULL, +}; +static struct attribute_group dev_attr_grp = { + .attrs = dev_attrs, +}; + /** * mmc_add_host - initialise host hardware * @host: mmc host @@ -390,11 +883,33 @@ led_trigger_register_simple(dev_name(&host->class_dev), &host->led); + host->clk_scaling.upthreshold = MMC_DEVFRQ_DEFAULT_UP_THRESHOLD; + host->clk_scaling.downthreshold = MMC_DEVFRQ_DEFAULT_DOWN_THRESHOLD; + host->clk_scaling.polling_delay_ms = MMC_DEVFRQ_DEFAULT_POLLING_MSEC; + host->clk_scaling.skip_clk_scale_freq_update = false; + #ifdef CONFIG_DEBUG_FS mmc_add_host_debugfs(host); #endif + mmc_host_clk_sysfs_init(host); + mmc_trace_init(host); + + err = sysfs_create_group(&host->class_dev.kobj, &clk_scaling_attr_grp); + if (err) + pr_err("%s: failed to create clk scale sysfs group with err %d\n", + __func__, err); + + err = sysfs_create_group(&host->class_dev.kobj, &dev_attr_grp); + if (err) + pr_err("%s: failed to create sysfs group with err %d\n", + __func__, err); + +#ifdef CONFIG_BLOCK + mmc_latency_hist_sysfs_init(host); +#endif mmc_start_host(host); + if (!(host->pm_flags & MMC_PM_IGNORE_PM_NOTIFY)) register_pm_notifier(&host->pm_notify); return 0; @@ -412,16 +927,26 @@ */ void mmc_remove_host(struct mmc_host *host) { + if (!(host->pm_flags & MMC_PM_IGNORE_PM_NOTIFY)) unregister_pm_notifier(&host->pm_notify); + mmc_stop_host(host); #ifdef CONFIG_DEBUG_FS mmc_remove_host_debugfs(host); #endif + sysfs_remove_group(&host->parent->kobj, &dev_attr_grp); + sysfs_remove_group(&host->class_dev.kobj, &clk_scaling_attr_grp); + +#ifdef CONFIG_BLOCK + mmc_latency_hist_sysfs_exit(host); +#endif device_del(&host->class_dev); led_trigger_unregister_simple(host->led); + + mmc_host_clk_exit(host); } EXPORT_SYMBOL(mmc_remove_host); diff -ruw linux-4.4.115/drivers/mmc/core/host.h linux-4.4.115-fbx/drivers/mmc/core/host.h --- linux-4.4.115/drivers/mmc/core/host.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/mmc/core/host.h 2019-01-22 16:16:24.767257853 +0100 @@ -12,6 +12,8 @@ #define _MMC_CORE_HOST_H #include +#define cls_dev_to_mmc_host(d) container_of(d, struct mmc_host, class_dev) + int mmc_register_host_class(void); void mmc_unregister_host_class(void); @@ -21,5 +23,8 @@ void mmc_retune_release(struct mmc_host *host); int mmc_retune(struct mmc_host *host); +void mmc_latency_hist_sysfs_init(struct mmc_host *host); +void mmc_latency_hist_sysfs_exit(struct mmc_host *host); + #endif diff -ruw linux-4.4.115/drivers/mmc/core/Kconfig linux-4.4.115-fbx/drivers/mmc/core/Kconfig --- linux-4.4.115/drivers/mmc/core/Kconfig 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/mmc/core/Kconfig 2019-01-22 16:16:24.767257853 +0100 @@ -1,3 +1,39 @@ # # MMC core configuration # + +config MMC_RING_BUFFER + bool "MMC_RING_BUFFER" + depends on MMC + default n + help + This enables the ring buffer tracing of significant + events for mmc driver to provide command history for + debugging purpose. + + If unsure, say N. + +config MMC_EMBEDDED_SDIO + boolean "MMC embedded SDIO device support (EXPERIMENTAL)" + help + If you say Y here, support will be added for embedded SDIO + devices which do not contain the necessary enumeration + support in hardware to be properly detected. + +config MMC_PARANOID_SD_INIT + bool "Enable paranoid SD card initialization (EXPERIMENTAL)" + help + If you say Y here, the MMC layer will be extra paranoid + about re-trying SD init requests. This can be a useful + work-around for buggy controllers and hardware. Enable + if you are experiencing issues with SD detection. + +config MMC_CLKGATE + bool "MMC host clock gating" + help + This will attempt to aggressively gate the clock to the MMC card. + This is done to save power due to gating off the logic and bus + noise when the MMC card is not in use. Your host driver has to + support handling this in order for it to be of any use. + + If unsure, say N. diff -ruw linux-4.4.115/drivers/mmc/core/Makefile linux-4.4.115-fbx/drivers/mmc/core/Makefile --- linux-4.4.115/drivers/mmc/core/Makefile 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/mmc/core/Makefile 2019-01-22 16:16:24.767257853 +0100 @@ -10,3 +10,4 @@ quirks.o slot-gpio.o mmc_core-$(CONFIG_OF) += pwrseq.o pwrseq_simple.o pwrseq_emmc.o mmc_core-$(CONFIG_DEBUG_FS) += debugfs.o +obj-$(CONFIG_MMC_RING_BUFFER) += ring_buffer.o diff -ruw linux-4.4.115/drivers/mmc/core/mmc.c linux-4.4.115-fbx/drivers/mmc/core/mmc.c --- linux-4.4.115/drivers/mmc/core/mmc.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/mmc/core/mmc.c 2019-10-29 09:26:24.057207230 +0100 @@ -19,6 +19,8 @@ #include #include #include +#include +#include #include "core.h" #include "host.h" @@ -59,6 +61,7 @@ __res & __mask; \ }) +static int mmc_switch_status(struct mmc_card *card, bool ignore_crc); /* * Given the decoded CSD structure, decode the raw CID to our CID structure. */ @@ -124,6 +127,19 @@ mmc_init_erase(card); } +static const struct mmc_fixup mmc_fixups[] = { + + /* avoid HPI for specific cards */ + MMC_FIXUP_EXT_CSD_REV("MMC16G", CID_MANFID_KINGSTON, CID_OEMID_ANY, + add_quirk, MMC_QUIRK_BROKEN_HPI, MMC_V4_41), + + /* Disable cache for specific cards */ + MMC_FIXUP("MMC16G", CID_MANFID_KINGSTON, CID_OEMID_ANY, + add_quirk_mmc, MMC_QUIRK_CACHE_DISABLE), + + END_FIXUP +}; + /* * Given a 128-bit response, decode to our card CSD structure. */ @@ -494,22 +510,41 @@ ext_csd[EXT_CSD_PWR_CL_DDR_200_360]; } + /* check whether the eMMC card supports HPI */ + if ((ext_csd[EXT_CSD_HPI_FEATURES] & 0x1) && + !(card->quirks & MMC_QUIRK_BROKEN_HPI)) { + card->ext_csd.hpi = 1; + if (ext_csd[EXT_CSD_HPI_FEATURES] & 0x2) + card->ext_csd.hpi_cmd = MMC_STOP_TRANSMISSION; + else + card->ext_csd.hpi_cmd = MMC_SEND_STATUS; + /* + * Indicate the maximum timeout to close + * a command interrupted by HPI + */ + card->ext_csd.out_of_int_time = + ext_csd[EXT_CSD_OUT_OF_INTERRUPT_TIME] * 10; + pr_info("%s: Out-of-interrupt timeout is %d[ms]\n", + mmc_hostname(card->host), + card->ext_csd.out_of_int_time); + } + if (card->ext_csd.rev >= 5) { /* Adjust production date as per JEDEC JESD84-B451 */ if (card->cid.year < 2010) card->cid.year += 16; /* check whether the eMMC card supports BKOPS */ - if (ext_csd[EXT_CSD_BKOPS_SUPPORT] & 0x1) { + if ((ext_csd[EXT_CSD_BKOPS_SUPPORT] & 0x1) && + card->ext_csd.hpi) { card->ext_csd.bkops = 1; - card->ext_csd.man_bkops_en = - (ext_csd[EXT_CSD_BKOPS_EN] & - EXT_CSD_MANUAL_BKOPS_MASK); + card->ext_csd.bkops_en = ext_csd[EXT_CSD_BKOPS_EN]; card->ext_csd.raw_bkops_status = ext_csd[EXT_CSD_BKOPS_STATUS]; - if (!card->ext_csd.man_bkops_en) - pr_info("%s: MAN_BKOPS_EN bit is not set\n", - mmc_hostname(card->host)); + if (!card->ext_csd.bkops_en) + pr_info("%s: BKOPS_EN equals 0x%x\n", + mmc_hostname(card->host), + card->ext_csd.bkops_en); } /* check whether the eMMC card supports HPI */ @@ -531,6 +566,19 @@ card->ext_csd.rst_n_function = ext_csd[EXT_CSD_RST_N_FUNCTION]; /* + * Some eMMC vendors violate eMMC 5.0 spec and set + * REL_WR_SEC_C register to 0x10 to indicate the + * ability of RPMB throughput improvement thus lead + * to failure when TZ module write data to RPMB + * partition. So check bit[4] of EXT_CSD[166] and + * if it is not set then change value of REL_WR_SEC_C + * to 0x1 directly ignoring value of EXT_CSD[222]. + */ + if (!(card->ext_csd.rel_param & + EXT_CSD_WR_REL_PARAM_EN_RPMB_REL_WR)) + card->ext_csd.rel_sectors = 0x1; + + /* * RPMB regions are defined in multiples of 128K. */ card->ext_csd.raw_rpmb_size_mult = ext_csd[EXT_CSD_RPMB_MULT]; @@ -585,6 +633,46 @@ card->ext_csd.data_sector_size = 512; } + if (card->ext_csd.rev >= 7) { + /* Enhance Strobe is supported since v5.1 which rev should be + * 8 but some eMMC devices can support it with rev 7. So handle + * Enhance Strobe here. + */ + card->ext_csd.strobe_support = ext_csd[EXT_CSD_STROBE_SUPPORT]; + card->ext_csd.cmdq_support = ext_csd[EXT_CSD_CMDQ_SUPPORT]; + card->ext_csd.fw_version = ext_csd[EXT_CSD_FIRMWARE_VERSION]; + pr_info("%s: eMMC FW version: 0x%02x\n", + mmc_hostname(card->host), + card->ext_csd.fw_version); + if (card->ext_csd.cmdq_support) { + /* + * Queue Depth = N + 1, + * see JEDEC JESD84-B51 section 7.4.19 + */ + card->ext_csd.cmdq_depth = + ext_csd[EXT_CSD_CMDQ_DEPTH] + 1; + pr_info("%s: CMDQ supported: depth: %d\n", + mmc_hostname(card->host), + card->ext_csd.cmdq_depth); + } + card->ext_csd.barrier_support = + ext_csd[EXT_CSD_BARRIER_SUPPORT]; + card->ext_csd.cache_flush_policy = + ext_csd[EXT_CSD_CACHE_FLUSH_POLICY]; + pr_info("%s: cache barrier support %d flush policy %d\n", + mmc_hostname(card->host), + card->ext_csd.barrier_support, + card->ext_csd.cache_flush_policy); + card->ext_csd.enhanced_rpmb_supported = + (card->ext_csd.rel_param & + EXT_CSD_WR_REL_PARAM_EN_RPMB_REL_WR); + } else { + card->ext_csd.cmdq_support = 0; + card->ext_csd.cmdq_depth = 0; + card->ext_csd.barrier_support = 0; + card->ext_csd.cache_flush_policy = 0; + } + /* eMMC v5 or later */ if (card->ext_csd.rev >= 7) { memcpy(card->ext_csd.fwrev, &ext_csd[EXT_CSD_FIRMWARE_VERSION], @@ -592,6 +680,12 @@ card->ext_csd.ffu_capable = (ext_csd[EXT_CSD_SUPPORTED_MODE] & 0x1) && !(ext_csd[EXT_CSD_FW_CONFIG] & 0x1); + + card->ext_csd.pre_eol_info = ext_csd[EXT_CSD_PRE_EOL_INFO]; + card->ext_csd.device_life_time_est_typ_a = + ext_csd[EXT_CSD_DEVICE_LIFE_TIME_EST_TYP_A]; + card->ext_csd.device_life_time_est_typ_b = + ext_csd[EXT_CSD_DEVICE_LIFE_TIME_EST_TYP_B]; } out: return err; @@ -599,6 +693,7 @@ static int mmc_read_ext_csd(struct mmc_card *card) { + struct mmc_host *host = card->host; u8 *ext_csd; int err; @@ -607,6 +702,9 @@ err = mmc_get_ext_csd(card, &ext_csd); if (err) { + pr_err("%s: %s: mmc_get_ext_csd() fails %d\n", + mmc_hostname(host), __func__, err); + /* If the host or the card can't do the switch, * fail more gracefully. */ if ((err != -EINVAL) @@ -721,11 +819,18 @@ MMC_DEV_ATTR(name, "%s\n", card->cid.prod_name); MMC_DEV_ATTR(oemid, "0x%04x\n", card->cid.oemid); MMC_DEV_ATTR(prv, "0x%x\n", card->cid.prv); +MMC_DEV_ATTR(rev, "0x%x\n", card->ext_csd.rev); +MMC_DEV_ATTR(pre_eol_info, "%02x\n", card->ext_csd.pre_eol_info); +MMC_DEV_ATTR(life_time, "0x%02x 0x%02x\n", + card->ext_csd.device_life_time_est_typ_a, + card->ext_csd.device_life_time_est_typ_b); MMC_DEV_ATTR(serial, "0x%08x\n", card->cid.serial); MMC_DEV_ATTR(enhanced_area_offset, "%llu\n", card->ext_csd.enhanced_area_offset); MMC_DEV_ATTR(enhanced_area_size, "%u\n", card->ext_csd.enhanced_area_size); MMC_DEV_ATTR(raw_rpmb_size_mult, "%#x\n", card->ext_csd.raw_rpmb_size_mult); +MMC_DEV_ATTR(enhanced_rpmb_supported, "%#x\n", + card->ext_csd.enhanced_rpmb_supported); MMC_DEV_ATTR(rel_sectors, "%#x\n", card->ext_csd.rel_sectors); static ssize_t mmc_fwrev_show(struct device *dev, @@ -757,10 +862,14 @@ &dev_attr_name.attr, &dev_attr_oemid.attr, &dev_attr_prv.attr, + &dev_attr_rev.attr, + &dev_attr_pre_eol_info.attr, + &dev_attr_life_time.attr, &dev_attr_serial.attr, &dev_attr_enhanced_area_offset.attr, &dev_attr_enhanced_area_size.attr, &dev_attr_raw_rpmb_size_mult.attr, + &dev_attr_enhanced_rpmb_supported.attr, &dev_attr_rel_sectors.attr, NULL, }; @@ -895,11 +1004,11 @@ */ static int mmc_select_bus_width(struct mmc_card *card) { - static unsigned ext_csd_bits[] = { + static const unsigned ext_csd_bits[] = { EXT_CSD_BUS_WIDTH_8, EXT_CSD_BUS_WIDTH_4, }; - static unsigned bus_widths[] = { + static const unsigned bus_widths[] = { MMC_BUS_WIDTH_8, MMC_BUS_WIDTH_4, }; @@ -969,9 +1078,11 @@ err = __mmc_switch(card, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_HS_TIMING, EXT_CSD_TIMING_HS, card->ext_csd.generic_cmd6_time, - true, true, true); - if (!err) + true, false, true); + if (!err) { mmc_set_timing(card->host, MMC_TIMING_MMC_HS); + err = mmc_switch_status(card, false); + } return err; } @@ -995,10 +1106,11 @@ ext_csd_bits = (bus_width == MMC_BUS_WIDTH_8) ? EXT_CSD_DDR_BUS_WIDTH_8 : EXT_CSD_DDR_BUS_WIDTH_4; - err = mmc_switch(card, EXT_CSD_CMD_SET_NORMAL, + err = __mmc_switch(card, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_BUS_WIDTH, ext_csd_bits, - card->ext_csd.generic_cmd6_time); + card->ext_csd.generic_cmd6_time, + true, false, false); if (err) { pr_err("%s: switch to bus width %d ddr failed\n", mmc_hostname(host), 1 << bus_width); @@ -1041,19 +1153,21 @@ if (err) err = __mmc_set_signal_voltage(host, MMC_SIGNAL_VOLTAGE_330); - if (!err) + if (!err) { mmc_set_timing(host, MMC_TIMING_MMC_DDR52); + err = mmc_switch_status(card, false); + } return err; } /* Caller must hold re-tuning */ -static int mmc_switch_status(struct mmc_card *card) +static int mmc_switch_status(struct mmc_card *card, bool ignore_crc) { u32 status; int err; - err = mmc_send_status(card, &status); + err = __mmc_send_status(card, &status, ignore_crc); if (err) return err; @@ -1071,17 +1185,32 @@ /* * HS400 mode requires 8-bit bus width */ + if (card->ext_csd.strobe_support) { + if (!(card->mmc_avail_type & EXT_CSD_CARD_TYPE_HS400 && + host->caps & MMC_CAP_8_BIT_DATA)) + return 0; + + /* For Enhance Strobe flow. For non Enhance Strobe, signal + * voltage will not be set. + */ + if (card->mmc_avail_type & EXT_CSD_CARD_TYPE_HS200_1_2V) + err = __mmc_set_signal_voltage(host, + MMC_SIGNAL_VOLTAGE_120); + + if (err && card->mmc_avail_type & EXT_CSD_CARD_TYPE_HS200_1_8V) + err = __mmc_set_signal_voltage(host, + MMC_SIGNAL_VOLTAGE_180); + if (err) + return err; + } else { if (!(card->mmc_avail_type & EXT_CSD_CARD_TYPE_HS400 && host->ios.bus_width == MMC_BUS_WIDTH_8)) return 0; + } if (host->caps & MMC_CAP_WAIT_WHILE_BUSY) send_status = false; - /* Reduce frequency to HS frequency */ - max_dtr = card->ext_csd.hs_max_dtr; - mmc_set_clock(host, max_dtr); - /* Switch card to HS mode */ val = EXT_CSD_TIMING_HS; err = __mmc_switch(card, EXT_CSD_CMD_SET_NORMAL, @@ -1097,16 +1226,28 @@ /* Set host controller to HS timing */ mmc_set_timing(card->host, MMC_TIMING_MMC_HS); + /* Reduce frequency to HS frequency */ + max_dtr = card->ext_csd.hs_max_dtr; + mmc_set_clock(host, max_dtr); + if (!send_status) { - err = mmc_switch_status(card); + err = mmc_switch_status(card, false); if (err) goto out_err; } + val = EXT_CSD_DDR_BUS_WIDTH_8; + if (card->ext_csd.strobe_support) { + err = mmc_select_bus_width(card); + if (IS_ERR_VALUE(err)) + return err; + val |= EXT_CSD_BUS_WIDTH_STROBE; + } + /* Switch card to DDR */ err = mmc_switch(card, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_BUS_WIDTH, - EXT_CSD_DDR_BUS_WIDTH_8, + val, card->ext_csd.generic_cmd6_time); if (err) { pr_err("%s: switch to bus width for hs400 failed, err:%d\n", @@ -1131,8 +1272,29 @@ mmc_set_timing(host, MMC_TIMING_MMC_HS400); mmc_set_bus_speed(card); + if (card->ext_csd.strobe_support && host->ops->enhanced_strobe) { + mmc_host_clk_hold(host); + err = host->ops->enhanced_strobe(host); + mmc_host_clk_release(host); + } else if ((host->caps2 & MMC_CAP2_HS400_POST_TUNING) && + host->ops->execute_tuning) { + mmc_host_clk_hold(host); + err = host->ops->execute_tuning(host, + MMC_SEND_TUNING_BLOCK_HS200); + mmc_host_clk_release(host); + + if (err) + pr_warn("%s: tuning execution failed\n", + mmc_hostname(host)); + } + + /* + * Sending of CMD13 should be done after the host calibration + * for enhanced_strobe or HS400 mode is completed. + * Otherwise may see CMD13 timeouts or CRC errors. + */ if (!send_status) { - err = mmc_switch_status(card); + err = mmc_switch_status(card, false); if (err) goto out_err; } @@ -1161,10 +1323,6 @@ if (host->caps & MMC_CAP_WAIT_WHILE_BUSY) send_status = false; - /* Reduce frequency to HS */ - max_dtr = card->ext_csd.hs_max_dtr; - mmc_set_clock(host, max_dtr); - /* Switch HS400 to HS DDR */ val = EXT_CSD_TIMING_HS; err = __mmc_switch(card, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_HS_TIMING, @@ -1175,8 +1333,12 @@ mmc_set_timing(host, MMC_TIMING_MMC_DDR52); + /* Reduce frequency to HS */ + max_dtr = card->ext_csd.hs_max_dtr; + mmc_set_clock(host, max_dtr); + if (!send_status) { - err = mmc_switch_status(card); + err = mmc_switch_status(card, false); if (err) goto out_err; } @@ -1191,7 +1353,7 @@ mmc_set_timing(host, MMC_TIMING_MMC_HS); if (!send_status) { - err = mmc_switch_status(card); + err = mmc_switch_status(card, false); if (err) goto out_err; } @@ -1208,7 +1370,7 @@ mmc_set_timing(host, MMC_TIMING_MMC_HS200); if (!send_status) { - err = mmc_switch_status(card); + err = mmc_switch_status(card, false); if (err) goto out_err; } @@ -1287,7 +1449,12 @@ old_timing = host->ios.timing; mmc_set_timing(host, MMC_TIMING_MMC_HS200); if (!send_status) { - err = mmc_switch_status(card); + /* + * Since after switching to hs200, crc errors might + * occur for commands send before tuning. + * So ignore crc error for cmd13. + */ + err = mmc_switch_status(card, true); /* * mmc_select_timing() assumes timing has not changed if * it is a switch error. @@ -1303,6 +1470,17 @@ return err; } +static int mmc_reboot_notify(struct notifier_block *notify_block, + unsigned long event, void *unused) +{ + struct mmc_card *card = container_of( + notify_block, struct mmc_card, reboot_notify); + + card->pon_type = (event != SYS_RESTART) ? MMC_LONG_PON : MMC_SHRT_PON; + + return NOTIFY_OK; +} + /* * Activate High Speed or HS200 mode if supported. */ @@ -1313,7 +1491,12 @@ if (!mmc_can_ext_csd(card)) goto bus_speed; - if (card->mmc_avail_type & EXT_CSD_CARD_TYPE_HS200) + /* For Enhance Strobe HS400 flow */ + if (card->ext_csd.strobe_support && + card->mmc_avail_type & EXT_CSD_CARD_TYPE_HS400 && + card->host->caps & MMC_CAP_8_BIT_DATA) + err = mmc_select_hs400(card); + else if (card->mmc_avail_type & EXT_CSD_CARD_TYPE_HS200) err = mmc_select_hs200(card); else if (card->mmc_avail_type & EXT_CSD_CARD_TYPE_HS) err = mmc_select_hs(card); @@ -1352,12 +1535,242 @@ */ if (card->mmc_avail_type & EXT_CSD_CARD_TYPE_HS400 && host->ios.bus_width == MMC_BUS_WIDTH_8) - if (host->ops->prepare_hs400_tuning) - host->ops->prepare_hs400_tuning(host, &host->ios); + mmc_set_timing(host, MMC_TIMING_MMC_HS400); return mmc_execute_tuning(card); } +static int mmc_select_cmdq(struct mmc_card *card) +{ + struct mmc_host *host = card->host; + int ret = 0; + + if (!host->cmdq_ops) { + pr_err("%s: host controller doesn't support CMDQ\n", + mmc_hostname(host)); + return 0; + } + + ret = mmc_set_blocklen(card, MMC_CARD_CMDQ_BLK_SIZE); + if (ret) + goto out; + + ret = mmc_switch(card, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_CMDQ, 1, + card->ext_csd.generic_cmd6_time); + if (ret) + goto out; + + mmc_card_set_cmdq(card); + mmc_host_clk_hold(card->host); + ret = host->cmdq_ops->enable(card->host); + if (ret) { + mmc_host_clk_release(card->host); + pr_err("%s: failed (%d) enabling CMDQ on host\n", + mmc_hostname(host), ret); + mmc_card_clr_cmdq(card); + ret = mmc_switch(card, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_CMDQ, 0, + card->ext_csd.generic_cmd6_time); + goto out; + } + + mmc_host_clk_release(card->host); + pr_info_once("%s: CMDQ enabled on card\n", mmc_hostname(host)); +out: + return ret; +} + +static int mmc_select_hs_ddr52(struct mmc_host *host) +{ + int err; + + mmc_select_hs(host->card); + err = mmc_select_bus_width(host->card); + if (err < 0) { + pr_err("%s: %s: select_bus_width failed(%d)\n", + mmc_hostname(host), __func__, err); + return err; + } + + err = mmc_select_hs_ddr(host->card); + mmc_set_clock(host, MMC_HIGH_52_MAX_DTR); + + return err; +} + +/* + * Scale down from HS400 to HS in order to allow frequency change. + * This is needed for cards that doesn't support changing frequency in HS400 + */ +static int mmc_scale_low(struct mmc_host *host, unsigned long freq) +{ + int err = 0; + + mmc_set_timing(host, MMC_TIMING_LEGACY); + mmc_set_clock(host, MMC_HIGH_26_MAX_DTR); + + if (host->clk_scaling.lower_bus_speed_mode & + MMC_SCALING_LOWER_DDR52_MODE) { + err = mmc_select_hs_ddr52(host); + if (err) + pr_err("%s: %s: failed to switch to DDR52: err: %d\n", + mmc_hostname(host), __func__, err); + else + return err; + } + + err = mmc_select_hs(host->card); + if (err) { + pr_err("%s: %s: scaling low: failed (%d)\n", + mmc_hostname(host), __func__, err); + return err; + } + + err = mmc_select_bus_width(host->card); + if (err < 0) { + pr_err("%s: %s: select_bus_width failed(%d)\n", + mmc_hostname(host), __func__, err); + return err; + } + + mmc_set_clock(host, freq); + + return 0; +} + +/* + * Scale UP from HS to HS200/H400 + */ +static int mmc_scale_high(struct mmc_host *host) +{ + int err = 0; + + if (mmc_card_ddr52(host->card)) { + mmc_set_timing(host, MMC_TIMING_LEGACY); + mmc_set_clock(host, MMC_HIGH_26_MAX_DTR); + } + + if (!host->card->ext_csd.strobe_support) { + if (!(host->card->mmc_avail_type & EXT_CSD_CARD_TYPE_HS200)) { + pr_err("%s: %s: card does not support HS200\n", + mmc_hostname(host), __func__); + WARN_ON(1); + return -EPERM; + } + + err = mmc_select_hs200(host->card); + if (err) { + pr_err("%s: %s: selecting HS200 failed (%d)\n", + mmc_hostname(host), __func__, err); + return err; + } + + mmc_set_bus_speed(host->card); + + err = mmc_hs200_tuning(host->card); + if (err) { + pr_err("%s: %s: hs200 tuning failed (%d)\n", + mmc_hostname(host), __func__, err); + return err; + } + + if (!(host->card->mmc_avail_type & EXT_CSD_CARD_TYPE_HS400)) { + pr_debug("%s: card does not support HS400\n", + mmc_hostname(host)); + return 0; + } + } + + err = mmc_select_hs400(host->card); + if (err) { + pr_err("%s: %s: select hs400 failed (%d)\n", + mmc_hostname(host), __func__, err); + return err; + } + + return err; +} + +static int mmc_set_clock_bus_speed(struct mmc_card *card, unsigned long freq) +{ + int err = 0; + + if (freq == MMC_HS200_MAX_DTR) + err = mmc_scale_high(card->host); + else + err = mmc_scale_low(card->host, freq); + + return err; +} + +static inline unsigned long mmc_ddr_freq_accommodation(unsigned long freq) +{ + if (freq == MMC_HIGH_DDR_MAX_DTR) + return freq; + + return freq/2; +} + +/** + * mmc_change_bus_speed() - Change MMC card bus frequency at runtime + * @host: pointer to mmc host structure + * @freq: pointer to desired frequency to be set + * + * Change the MMC card bus frequency at runtime after the card is + * initialized. Callers are expected to make sure of the card's + * state (DATA/RCV/TRANSFER) before changing the frequency at runtime. + * + * If the frequency to change is greater than max. supported by card, + * *freq is changed to max. supported by card. If it is less than min. + * supported by host, *freq is changed to min. supported by host. + * Host is assumed to be calimed while calling this funciton. + */ +static int mmc_change_bus_speed(struct mmc_host *host, unsigned long *freq) +{ + int err = 0; + struct mmc_card *card; + unsigned long actual_freq; + + card = host->card; + + if (!card || !freq) { + err = -EINVAL; + goto out; + } + actual_freq = *freq; + + WARN_ON(!host->claimed); + + /* + * For scaling up/down HS400 we'll need special handling, + * for other timings we can simply do clock frequency change + */ + if (mmc_card_hs400(card) || + (!mmc_card_hs200(host->card) && *freq == MMC_HS200_MAX_DTR)) { + err = mmc_set_clock_bus_speed(card, *freq); + if (err) { + pr_err("%s: %s: failed (%d)to set bus and clock speed (freq=%lu)\n", + mmc_hostname(host), __func__, err, *freq); + goto out; + } + } else if (mmc_card_hs200(host->card)) { + mmc_set_clock(host, *freq); + err = mmc_hs200_tuning(host->card); + if (err) { + pr_warn("%s: %s: tuning execution failed %d\n", + mmc_hostname(card->host), + __func__, err); + mmc_set_clock(host, host->clk_scaling.curr_freq); + } + } else { + if (mmc_card_ddr52(host->card)) + actual_freq = mmc_ddr_freq_accommodation(*freq); + mmc_set_clock(host, actual_freq); + } + +out: + return err; +} + /* * Handle the detection and initialisation of a card. * @@ -1386,21 +1799,28 @@ * respond. * mmc_go_idle is needed for eMMC that are asleep */ +reinit: mmc_go_idle(host); /* The extra bit indicates that we support high capacity */ err = mmc_send_op_cond(host, ocr | (1 << 30), &rocr); - if (err) + if (err) { + pr_err("%s: %s: mmc_send_op_cond() fails %d\n", + mmc_hostname(host), __func__, err); goto err; + } /* * For SPI, enable CRC as appropriate. */ if (mmc_host_is_spi(host)) { err = mmc_spi_set_crc(host, use_spi_crc); - if (err) + if (err) { + pr_err("%s: %s: mmc_spi_set_crc() fails %d\n", + mmc_hostname(host), __func__, err); goto err; } + } /* * Fetch CID from card. @@ -1409,12 +1829,17 @@ err = mmc_send_cid(host, cid); else err = mmc_all_send_cid(host, cid); - if (err) + if (err) { + pr_err("%s: %s: mmc_send_cid() fails %d\n", + mmc_hostname(host), __func__, err); goto err; + } if (oldcard) { if (memcmp(cid, oldcard->raw_cid, sizeof(cid)) != 0) { err = -ENOENT; + pr_err("%s: %s: CID memcmp failed %d\n", + mmc_hostname(host), __func__, err); goto err; } @@ -1426,6 +1851,8 @@ card = mmc_alloc_card(host, &mmc_type); if (IS_ERR(card)) { err = PTR_ERR(card); + pr_err("%s: %s: no memory to allocate for card %d\n", + mmc_hostname(host), __func__, err); goto err; } @@ -1433,6 +1860,8 @@ card->type = MMC_TYPE_MMC; card->rca = 1; memcpy(card->raw_cid, cid, sizeof(card->raw_cid)); + host->card = card; + card->reboot_notify.notifier_call = mmc_reboot_notify; } /* @@ -1446,8 +1875,11 @@ */ if (!mmc_host_is_spi(host)) { err = mmc_set_relative_addr(card); - if (err) + if (err) { + pr_err("%s: %s: mmc_set_relative_addr() fails %d\n", + mmc_hostname(host), __func__, err); goto free_card; + } mmc_set_bus_mode(host, MMC_BUSMODE_PUSHPULL); } @@ -1457,16 +1889,25 @@ * Fetch CSD from card. */ err = mmc_send_csd(card, card->raw_csd); - if (err) + if (err) { + pr_err("%s: %s: mmc_send_csd() fails %d\n", + mmc_hostname(host), __func__, err); goto free_card; + } err = mmc_decode_csd(card); - if (err) + if (err) { + pr_err("%s: %s: mmc_decode_csd() fails %d\n", + mmc_hostname(host), __func__, err); goto free_card; + } err = mmc_decode_cid(card); - if (err) + if (err) { + pr_err("%s: %s: mmc_decode_cid() fails %d\n", + mmc_hostname(host), __func__, err); goto free_card; } + } /* * handling only for cards supporting DSR and hosts requesting @@ -1480,15 +1921,21 @@ */ if (!mmc_host_is_spi(host)) { err = mmc_select_card(card); - if (err) + if (err) { + pr_err("%s: %s: mmc_select_card() fails %d\n", + mmc_hostname(host), __func__, err); goto free_card; } + } if (!oldcard) { /* Read extended CSD. */ err = mmc_read_ext_csd(card); - if (err) + if (err) { + pr_err("%s: %s: mmc_read_ext_csd() fails %d\n", + mmc_hostname(host), __func__, err); goto free_card; + } /* If doing byte addressing, check if required to do sector * addressing. Handle the case of <2GB cards needing sector @@ -1500,6 +1947,9 @@ /* Erase size depends on CSD and Extended CSD */ mmc_set_erase_size(card); + + if (card->ext_csd.sectors && (rocr & MMC_CARD_SECTOR_ADDR)) + mmc_card_set_blockaddr(card); } /* @@ -1512,8 +1962,11 @@ EXT_CSD_ERASE_GROUP_DEF, 1, card->ext_csd.generic_cmd6_time); - if (err && err != -EBADMSG) + if (err && err != -EBADMSG) { + pr_err("%s: %s: mmc_switch() for ERASE_GRP_DEF fails %d\n", + mmc_hostname(host), __func__, err); goto free_card; + } if (err) { err = 0; @@ -1543,9 +1996,14 @@ err = mmc_switch(card, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_PART_CONFIG, card->ext_csd.part_config, card->ext_csd.part_time); - if (err && err != -EBADMSG) + if (err && err != -EBADMSG) { + pr_err("%s: %s: mmc_switch() for PART_CONFIG fails %d\n", + mmc_hostname(host), __func__, err); goto free_card; } + card->part_curr = card->ext_csd.part_config & + EXT_CSD_PART_CONFIG_ACC_MASK; + } /* * Enable power_off_notification byte in the ext_csd register @@ -1555,8 +2013,11 @@ EXT_CSD_POWER_OFF_NOTIFICATION, EXT_CSD_POWER_ON, card->ext_csd.generic_cmd6_time); - if (err && err != -EBADMSG) + if (err && err != -EBADMSG) { + pr_err("%s: %s: mmc_switch() for POWER_ON PON fails %d\n", + mmc_hostname(host), __func__, err); goto free_card; + } /* * The err can be -EBADMSG or 0, @@ -1570,8 +2031,11 @@ * Select timing interface */ err = mmc_select_timing(card); - if (err) + if (err) { + pr_err("%s: %s: mmc_select_timing() fails %d\n", + mmc_hostname(host), __func__, err); goto free_card; + } if (mmc_card_hs200(card)) { err = mmc_hs200_tuning(card); @@ -1581,7 +2045,7 @@ err = mmc_select_hs400(card); if (err) goto free_card; - } else { + } else if (!mmc_card_hs400(card)) { /* Select the desired bus width optionally */ err = mmc_select_bus_width(card); if (!IS_ERR_VALUE(err) && mmc_card_hs(card)) { @@ -1591,6 +2055,16 @@ } } + card->clk_scaling_lowest = host->f_min; + if ((card->mmc_avail_type & EXT_CSD_CARD_TYPE_HS400) || + (card->mmc_avail_type & EXT_CSD_CARD_TYPE_HS200)) + card->clk_scaling_highest = card->ext_csd.hs200_max_dtr; + else if ((card->mmc_avail_type & EXT_CSD_CARD_TYPE_HS) || + (card->mmc_avail_type & EXT_CSD_CARD_TYPE_DDR_52)) + card->clk_scaling_highest = card->ext_csd.hs_max_dtr; + else + card->clk_scaling_highest = card->csd.max_dtr; + /* * Choose the power class with selected bus interface */ @@ -1603,8 +2077,11 @@ err = mmc_switch(card, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_HPI_MGMT, 1, card->ext_csd.generic_cmd6_time); - if (err && err != -EBADMSG) + if (err && err != -EBADMSG) { + pr_err("%s: %s: mmc_switch() for HPI_MGMT fails %d\n", + mmc_hostname(host), __func__, err); goto free_card; + } if (err) { pr_warn("%s: Enabling HPI failed\n", mmc_hostname(card->host)); @@ -1616,13 +2093,19 @@ /* * If cache size is higher than 0, this indicates * the existence of cache and it can be turned on. + * If HPI is not supported then cache shouldn't be enabled. */ if (card->ext_csd.cache_size > 0) { + if (card->ext_csd.hpi_en && + (!(card->quirks & MMC_QUIRK_CACHE_DISABLE))) { err = mmc_switch(card, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_CACHE_CTRL, 1, card->ext_csd.generic_cmd6_time); - if (err && err != -EBADMSG) + if (err && err != -EBADMSG) { + pr_err("%s: %s: fail on CACHE_CTRL ON %d\n", + mmc_hostname(host), __func__, err); goto free_card; + } /* * Only if no error, cache is turned on successfully. @@ -1635,6 +2118,45 @@ } else { card->ext_csd.cache_ctrl = 1; } + /* enable cache barrier if supported by the device */ + if (card->ext_csd.cache_ctrl && + card->ext_csd.barrier_support) { + err = mmc_switch(card, EXT_CSD_CMD_SET_NORMAL, + EXT_CSD_BARRIER_CTRL, 1, + card->ext_csd.generic_cmd6_time); + if (err && err != -EBADMSG) { + pr_err("%s: %s: mmc_switch() for BARRIER_CTRL fails %d\n", + mmc_hostname(host), __func__, + err); + goto free_card; + } + if (err) { + pr_warn("%s: Barrier is supported but failed to turn on (%d)\n", + mmc_hostname(card->host), err); + card->ext_csd.barrier_en = 0; + err = 0; + } else { + card->ext_csd.barrier_en = 1; + } + } + } else { + /* + * mmc standard doesn't say what is the card default + * value for EXT_CSD_CACHE_CTRL. + * Hence, cache may be enabled by default by + * card vendors. + * Thus, it is best to explicitly disable cache in case + * we want to avoid cache. + */ + err = mmc_switch(card, EXT_CSD_CMD_SET_NORMAL, + EXT_CSD_CACHE_CTRL, 0, + card->ext_csd.generic_cmd6_time); + if (err) { + pr_err("%s: %s: fail on CACHE_CTRL OFF %d\n", + mmc_hostname(host), __func__, err); + goto free_card; + } + } } /* @@ -1648,8 +2170,11 @@ EXT_CSD_EXP_EVENTS_CTRL, EXT_CSD_PACKED_EVENT_EN, card->ext_csd.generic_cmd6_time); - if (err && err != -EBADMSG) + if (err && err != -EBADMSG) { + pr_err("%s: %s: mmc_switch() for EXP_EVENTS_CTRL fails %d\n", + mmc_hostname(host), __func__, err); goto free_card; + } if (err) { pr_warn("%s: Enabling packed event failed\n", mmc_hostname(card->host)); @@ -1658,41 +2183,124 @@ } else { card->ext_csd.packed_event_en = 1; } + } - if (!oldcard) - host->card = card; + if (!oldcard) { + if ((host->caps2 & MMC_CAP2_PACKED_CMD) && + (card->ext_csd.max_packed_writes > 0)) { + /* + * We would like to keep the statistics in an index + * that equals the num of packed requests + * (1 to max_packed_writes) + */ + card->wr_pack_stats.packing_events = kzalloc( + (card->ext_csd.max_packed_writes + 1) * + sizeof(*card->wr_pack_stats.packing_events), + GFP_KERNEL); + if (!card->wr_pack_stats.packing_events) { + pr_err("%s: %s: no memory for packing events\n", + mmc_hostname(host), __func__); + goto free_card; + } + } + } + + /* + * Start auto bkops, if supported. + * + * Note: This leaves the possibility of having both manual and + * auto bkops running in parallel. The runtime implementation + * will allow this, but ignore bkops exceptions on the premises + * that auto bkops will eventually kick in and the device will + * handle bkops without START_BKOPS from the host. + */ + if (mmc_card_support_auto_bkops(card)) { + /* + * Ignore the return value of setting auto bkops. + * If it failed, will run in backward compatible mode. + */ + (void)mmc_set_auto_bkops(card, true); + } + + if (card->ext_csd.cmdq_support && (card->host->caps2 & + MMC_CAP2_CMD_QUEUE)) { + err = mmc_select_cmdq(card); + if (err) { + pr_err("%s: selecting CMDQ mode: failed: %d\n", + mmc_hostname(card->host), err); + card->ext_csd.cmdq_support = 0; + oldcard = card; + goto reinit; + } + } return 0; free_card: - if (!oldcard) + if (!oldcard) { + host->card = NULL; mmc_remove_card(card); + } err: return err; } -static int mmc_can_sleep(struct mmc_card *card) +static int mmc_can_sleepawake(struct mmc_host *host) { - return (card && card->ext_csd.rev >= 3); + return host && (host->caps2 & MMC_CAP2_SLEEP_AWAKE) && host->card && + (host->card->ext_csd.rev >= 3); } -static int mmc_sleep(struct mmc_host *host) +static int mmc_sleepawake(struct mmc_host *host, bool sleep) { struct mmc_command cmd = {0}; struct mmc_card *card = host->card; - unsigned int timeout_ms = DIV_ROUND_UP(card->ext_csd.sa_timeout, 10000); + unsigned int timeout_ms; int err; + if (!card) { + pr_err("%s: %s: invalid card\n", mmc_hostname(host), __func__); + return -EINVAL; + } + + timeout_ms = DIV_ROUND_UP(card->ext_csd.sa_timeout, 10000); + if (card->ext_csd.rev >= 3 && + card->part_curr == EXT_CSD_PART_CONFIG_ACC_RPMB) { + u8 part_config = card->ext_csd.part_config; + + /* + * If the last access before suspend is RPMB access, then + * switch to default part config so that sleep command CMD5 + * and deselect CMD7 can be sent to the card. + */ + part_config &= ~EXT_CSD_PART_CONFIG_ACC_MASK; + err = mmc_switch(card, EXT_CSD_CMD_SET_NORMAL, + EXT_CSD_PART_CONFIG, + part_config, + card->ext_csd.part_time); + if (err) { + pr_err("%s: %s: failed to switch to default part config %x\n", + mmc_hostname(host), __func__, part_config); + return err; + } + card->ext_csd.part_config = part_config; + card->part_curr = card->ext_csd.part_config & + EXT_CSD_PART_CONFIG_ACC_MASK; + } + /* Re-tuning can't be done once the card is deselected */ mmc_retune_hold(host); + if (sleep) { err = mmc_deselect_cards(host); if (err) goto out_release; + } cmd.opcode = MMC_SLEEP_AWAKE; cmd.arg = card->rca << 16; + if (sleep) cmd.arg |= 1 << 15; /* @@ -1721,6 +2329,9 @@ if (!cmd.busy_timeout || !(host->caps & MMC_CAP_WAIT_WHILE_BUSY)) mmc_delay(timeout_ms); + if (!sleep) + err = mmc_select_card(card); + out_release: mmc_retune_release(host); return err; @@ -1755,6 +2366,27 @@ return err; } +int mmc_send_pon(struct mmc_card *card) +{ + int err = 0; + struct mmc_host *host = card->host; + + if (!mmc_can_poweroff_notify(card)) + goto out; + + mmc_get_card(card); + if (card->pon_type & MMC_LONG_PON) + err = mmc_poweroff_notify(host->card, EXT_CSD_POWER_OFF_LONG); + else if (card->pon_type & MMC_SHRT_PON) + err = mmc_poweroff_notify(host->card, EXT_CSD_POWER_OFF_SHORT); + if (err) + pr_warn("%s: error %d sending PON type %u", + mmc_hostname(host), err, card->pon_type); + mmc_put_card(card); +out: + return err; +} + /* * Host is being removed. Free up the current card. */ @@ -1763,8 +2395,14 @@ BUG_ON(!host); BUG_ON(!host->card); + unregister_reboot_notifier(&host->card->reboot_notify); + + mmc_exit_clk_scaling(host); mmc_remove_card(host->card); + + mmc_claim_host(host); host->card = NULL; + mmc_release_host(host); } /* @@ -1804,44 +2442,228 @@ } } +static int mmc_cache_card_ext_csd(struct mmc_host *host) +{ + int err; + u8 *ext_csd; + struct mmc_card *card = host->card; + + err = mmc_get_ext_csd(card, &ext_csd); + if (err || !ext_csd) { + pr_err("%s: %s: mmc_get_ext_csd failed (%d)\n", + mmc_hostname(host), __func__, err); + return err; + } + + /* only cache read/write fields that the sw changes */ + card->ext_csd.raw_ext_csd_cmdq = ext_csd[EXT_CSD_CMDQ]; + card->ext_csd.raw_ext_csd_cache_ctrl = ext_csd[EXT_CSD_CACHE_CTRL]; + card->ext_csd.raw_ext_csd_bus_width = ext_csd[EXT_CSD_BUS_WIDTH]; + card->ext_csd.raw_ext_csd_hs_timing = ext_csd[EXT_CSD_HS_TIMING]; + + kfree(ext_csd); + + return 0; +} + +static int mmc_test_awake_ext_csd(struct mmc_host *host) +{ + int err; + u8 *ext_csd; + struct mmc_card *card = host->card; + + err = mmc_get_ext_csd(card, &ext_csd); + if (err || !ext_csd) { + pr_err("%s: %s: mmc_get_ext_csd failed (%d)\n", + mmc_hostname(host), __func__, err); + return err; + } + + /* only compare read/write fields that the sw changes */ + pr_debug("%s: %s: type(cached:current) cmdq(%d:%d) cache_ctrl(%d:%d) bus_width (%d:%d) timing(%d:%d)\n", + mmc_hostname(host), __func__, + card->ext_csd.raw_ext_csd_cmdq, + ext_csd[EXT_CSD_CMDQ], + card->ext_csd.raw_ext_csd_cache_ctrl, + ext_csd[EXT_CSD_CACHE_CTRL], + card->ext_csd.raw_ext_csd_bus_width, + ext_csd[EXT_CSD_BUS_WIDTH], + card->ext_csd.raw_ext_csd_hs_timing, + ext_csd[EXT_CSD_HS_TIMING]); + + err = !((card->ext_csd.raw_ext_csd_cmdq == + ext_csd[EXT_CSD_CMDQ]) && + (card->ext_csd.raw_ext_csd_cache_ctrl == + ext_csd[EXT_CSD_CACHE_CTRL]) && + (card->ext_csd.raw_ext_csd_bus_width == + ext_csd[EXT_CSD_BUS_WIDTH]) && + (card->ext_csd.raw_ext_csd_hs_timing == + ext_csd[EXT_CSD_HS_TIMING])); + + kfree(ext_csd); + + return err; +} + static int _mmc_suspend(struct mmc_host *host, bool is_suspend) { - int err = 0; - unsigned int notify_type = is_suspend ? EXT_CSD_POWER_OFF_SHORT : - EXT_CSD_POWER_OFF_LONG; + int err = 0, ret; BUG_ON(!host); BUG_ON(!host->card); + err = mmc_suspend_clk_scaling(host); + if (err) { + pr_err("%s: %s: fail to suspend clock scaling (%d)\n", + mmc_hostname(host), __func__, err); + if (host->card->cmdq_init) + wake_up(&host->cmdq_ctx.wait); + return err; + } + mmc_claim_host(host); if (mmc_card_suspended(host->card)) goto out; + if (host->card->cmdq_init) { + BUG_ON(host->cmdq_ctx.active_reqs); + + err = mmc_cmdq_halt(host, true); + if (err) { + pr_err("%s: halt: failed: %d\n", __func__, err); + goto out; + } + mmc_host_clk_hold(host); + host->cmdq_ops->disable(host, true); + mmc_host_clk_release(host); + } + if (mmc_card_doing_bkops(host->card)) { err = mmc_stop_bkops(host->card); if (err) - goto out; + goto out_err; } err = mmc_flush_cache(host->card); if (err) - goto out; + goto out_err; - if (mmc_can_poweroff_notify(host->card) && - ((host->caps2 & MMC_CAP2_FULL_PWR_CYCLE) || !is_suspend)) - err = mmc_poweroff_notify(host->card, notify_type); - else if (mmc_can_sleep(host->card)) - err = mmc_sleep(host); - else if (!mmc_host_is_spi(host)) + if (mmc_can_sleepawake(host)) { + /* + * For caching host->ios to cached_ios we need to + * make sure that clocks are not gated otherwise + * cached_ios->clock will be 0. + */ + mmc_host_clk_hold(host); + memcpy(&host->cached_ios, &host->ios, sizeof(host->cached_ios)); + mmc_cache_card_ext_csd(host); + err = mmc_sleepawake(host, true); + mmc_host_clk_release(host); + } else if (!mmc_host_is_spi(host)) { err = mmc_deselect_cards(host); + } - if (!err) { + if (err) + goto out_err; mmc_power_off(host); mmc_card_set_suspended(host->card); + + goto out; + +out_err: + /* + * In case of err let's put controller back in cmdq mode and unhalt + * the controller. + * We expect cmdq_enable and unhalt won't return any error + * since it is anyway enabling few registers. + */ + if (host->card->cmdq_init) { + mmc_host_clk_hold(host); + ret = host->cmdq_ops->enable(host); + if (ret) + pr_err("%s: %s: enabling CMDQ mode failed (%d)\n", + mmc_hostname(host), __func__, ret); + mmc_host_clk_release(host); + mmc_cmdq_halt(host, false); } + out: + /* Kick CMDQ thread to process any requests came in while suspending */ + if (host->card->cmdq_init) + wake_up(&host->cmdq_ctx.wait); + mmc_release_host(host); + if (err) + mmc_resume_clk_scaling(host); + return err; +} + +static int mmc_partial_init(struct mmc_host *host) +{ + int err = 0; + struct mmc_card *card = host->card; + + pr_debug("%s: %s: starting partial init\n", + mmc_hostname(host), __func__); + + mmc_set_bus_width(host, host->cached_ios.bus_width); + mmc_set_timing(host, host->cached_ios.timing); + mmc_set_clock(host, host->cached_ios.clock); + mmc_set_bus_mode(host, host->cached_ios.bus_mode); + + mmc_host_clk_hold(host); + + if (mmc_card_hs400(card)) { + if (card->ext_csd.strobe_support && host->ops->enhanced_strobe) + err = host->ops->enhanced_strobe(host); + else if (host->ops->execute_tuning) + err = host->ops->execute_tuning(host, + MMC_SEND_TUNING_BLOCK_HS200); + } else if (mmc_card_hs200(card) && host->ops->execute_tuning) { + err = host->ops->execute_tuning(host, + MMC_SEND_TUNING_BLOCK_HS200); + if (err) + pr_warn("%s: %s: tuning execution failed (%d)\n", + mmc_hostname(host), __func__, err); + } + + /* + * The ext_csd is read to make sure the card did not went through + * Power-failure during sleep period. + * A subset of the W/E_P, W/C_P register will be tested. In case + * these registers values are different from the values that were + * cached during suspend, we will conclude that a Power-failure occurred + * and will do full initialization sequence. + * In addition, full init sequence also transfer ext_csd before moving + * to CMDQ mode which has a side affect of configuring SDHCI registers + * which needed to be done before moving to CMDQ mode. The same + * registers need to be configured for partial init. + */ + err = mmc_test_awake_ext_csd(host); + if (err) { + pr_debug("%s: %s: fail on ext_csd read (%d)\n", + mmc_hostname(host), __func__, err); + goto out; + } + pr_debug("%s: %s: reading and comparing ext_csd successful\n", + mmc_hostname(host), __func__); + + if (card->ext_csd.cmdq_support && (card->host->caps2 & + MMC_CAP2_CMD_QUEUE)) { + err = mmc_select_cmdq(card); + if (err) { + pr_warn("%s: %s: enabling CMDQ mode failed (%d)\n", + mmc_hostname(card->host), + __func__, err); + } + } +out: + mmc_host_clk_release(host); + + pr_debug("%s: %s: done partial init (%d)\n", + mmc_hostname(host), __func__, err); + return err; } @@ -1851,13 +2673,18 @@ static int mmc_suspend(struct mmc_host *host) { int err; + ktime_t start = ktime_get(); + MMC_TRACE(host, "%s: Enter\n", __func__); err = _mmc_suspend(host, true); if (!err) { pm_runtime_disable(&host->card->dev); pm_runtime_set_suspended(&host->card->dev); } + trace_mmc_suspend(mmc_hostname(host), err, + ktime_to_us(ktime_sub(ktime_get(), start))); + MMC_TRACE(host, "%s: Exit err: %d\n", __func__, err); return err; } @@ -1867,43 +2694,61 @@ */ static int _mmc_resume(struct mmc_host *host) { - int err = 0; + int err = -ENOSYS; + int retries; BUG_ON(!host); BUG_ON(!host->card); mmc_claim_host(host); - if (!mmc_card_suspended(host->card)) + if (!mmc_card_suspended(host->card)) { + mmc_release_host(host); goto out; + } mmc_power_up(host, host->card->ocr); + retries = 3; + while (retries) { + if (mmc_can_sleepawake(host)) { + err = mmc_sleepawake(host, false); + if (!err) + err = mmc_partial_init(host); + if (err) + pr_err("%s: %s: awake failed (%d), fallback to full init\n", + mmc_hostname(host), __func__, err); + } + + if (err) err = mmc_init_card(host, host->card->ocr, host->card); - mmc_card_clr_suspended(host->card); -out: - mmc_release_host(host); - return err; + if (err) { + pr_err("%s: MMC card re-init failed rc = %d (retries = %d)\n", + mmc_hostname(host), err, retries); + retries--; + mmc_power_off(host); + usleep_range(5000, 5500); + mmc_power_up(host, host->card->ocr); + mmc_select_voltage(host, host->card->ocr); + continue; } + break; + } + if (!err && mmc_card_cmdq(host->card)) { + err = mmc_cmdq_halt(host, false); + if (err) + pr_err("%s: un-halt: failed: %d\n", __func__, err); + } + mmc_card_clr_suspended(host->card); -/* - * Shutdown callback - */ -static int mmc_shutdown(struct mmc_host *host) -{ - int err = 0; - - /* - * In a specific case for poweroff notify, we need to resume the card - * before we can shutdown it properly. - */ - if (mmc_can_poweroff_notify(host->card) && - !(host->caps2 & MMC_CAP2_FULL_PWR_CYCLE)) - err = _mmc_resume(host); + mmc_release_host(host); - if (!err) - err = _mmc_suspend(host, false); + err = mmc_resume_clk_scaling(host); + if (err) + pr_err("%s: %s: fail to resume clock scaling (%d)\n", + mmc_hostname(host), __func__, err); +out: return err; } @@ -1913,7 +2758,9 @@ static int mmc_resume(struct mmc_host *host) { int err = 0; + ktime_t start = ktime_get(); + MMC_TRACE(host, "%s: Enter\n", __func__); if (!(host->caps & MMC_CAP_RUNTIME_RESUME)) { err = _mmc_resume(host); pm_runtime_set_active(&host->card->dev); @@ -1921,24 +2768,95 @@ } pm_runtime_enable(&host->card->dev); + trace_mmc_resume(mmc_hostname(host), err, + ktime_to_us(ktime_sub(ktime_get(), start))); + MMC_TRACE(host, "%s: Exit err: %d\n", __func__, err); return err; } +#define MAX_DEFER_SUSPEND_COUNTER 20 +static bool mmc_process_bkops(struct mmc_host *host) +{ + int err = 0; + bool is_running = false; + u32 status; + + mmc_claim_host(host); + if (mmc_card_cmdq(host->card)) { + BUG_ON(host->cmdq_ctx.active_reqs); + + err = mmc_cmdq_halt(host, true); + if (err) { + pr_err("%s: halt: failed: %d\n", __func__, err); + goto unhalt; + } + } + + if (mmc_card_doing_bkops(host->card)) { + /* check that manual bkops finished */ + err = mmc_send_status(host->card, &status); + if (err) { + pr_err("%s: Get card status fail\n", __func__); + goto unhalt; + } + if (R1_CURRENT_STATE(status) != R1_STATE_PRG) { + mmc_card_clr_doing_bkops(host->card); + goto unhalt; + } + } else { + mmc_check_bkops(host->card); + } + + if (host->card->bkops.needs_bkops && + !mmc_card_support_auto_bkops(host->card)) + mmc_start_manual_bkops(host->card); + +unhalt: + if (mmc_card_cmdq(host->card)) { + err = mmc_cmdq_halt(host, false); + if (err) + pr_err("%s: unhalt: failed: %d\n", __func__, err); + } + mmc_release_host(host); + + if (host->card->bkops.needs_bkops || + mmc_card_doing_bkops(host->card)) { + if (host->card->bkops.retry_counter++ < + MAX_DEFER_SUSPEND_COUNTER) { + host->card->bkops.needs_check = true; + is_running = true; + } else { + host->card->bkops.retry_counter = 0; + } + } + return is_running; +} + /* * Callback for runtime_suspend. */ static int mmc_runtime_suspend(struct mmc_host *host) { int err; + ktime_t start = ktime_get(); if (!(host->caps & MMC_CAP_AGGRESSIVE_PM)) return 0; + if (mmc_process_bkops(host)) { + pm_runtime_mark_last_busy(&host->card->dev); + pr_debug("%s: defered, need bkops\n", __func__); + return -EBUSY; + } + + MMC_TRACE(host, "%s\n", __func__); err = _mmc_suspend(host, true); if (err) pr_err("%s: error %d doing aggressive suspend\n", mmc_hostname(host), err); + trace_mmc_runtime_suspend(mmc_hostname(host), err, + ktime_to_us(ktime_sub(ktime_get(), start))); return err; } @@ -1948,16 +2866,21 @@ static int mmc_runtime_resume(struct mmc_host *host) { int err; + ktime_t start = ktime_get(); if (!(host->caps & (MMC_CAP_AGGRESSIVE_PM | MMC_CAP_RUNTIME_RESUME))) return 0; + MMC_TRACE(host, "%s\n", __func__); err = _mmc_resume(host); if (err) pr_err("%s: error %d doing aggressive resume\n", mmc_hostname(host), err); - return 0; + trace_mmc_runtime_resume(mmc_hostname(host), err, + ktime_to_us(ktime_sub(ktime_get(), start))); + + return err; } int mmc_can_reset(struct mmc_card *card) @@ -1974,21 +2897,58 @@ static int mmc_reset(struct mmc_host *host) { struct mmc_card *card = host->card; + int ret; - if (!(host->caps & MMC_CAP_HW_RESET) || !host->ops->hw_reset) - return -EOPNOTSUPP; - - if (!mmc_can_reset(card)) - return -EOPNOTSUPP; - + if ((host->caps & MMC_CAP_HW_RESET) && host->ops->hw_reset && + mmc_can_reset(card)) { + /* If the card accept RST_n signal, send it. */ mmc_set_clock(host, host->f_init); - host->ops->hw_reset(host); - /* Set initial state and call mmc_set_ios */ mmc_set_initial_state(host); + } else { + /* Do a brute force power cycle */ + mmc_power_cycle(host, card->ocr); + } - return mmc_init_card(host, card->ocr, card); + /* Suspend clk scaling to avoid switching frequencies intermittently */ + + ret = mmc_suspend_clk_scaling(host); + if (ret) { + pr_err("%s: %s: fail to suspend clock scaling (%d)\n", + mmc_hostname(host), __func__, ret); + return ret; + } + + ret = mmc_init_card(host, host->card->ocr, host->card); + if (ret) { + pr_err("%s: %s: mmc_init_card failed (%d)\n", + mmc_hostname(host), __func__, ret); + return ret; + } + + ret = mmc_resume_clk_scaling(host); + if (ret) + pr_err("%s: %s: fail to resume clock scaling (%d)\n", + mmc_hostname(host), __func__, ret); + + return ret; +} + +static int mmc_shutdown(struct mmc_host *host) +{ + struct mmc_card *card = host->card; + + /* + * Exit clock scaling so that it doesn't kick in after + * power off notification is sent + */ + if (host->caps2 & MMC_CAP2_CLK_SCALE) + mmc_exit_clk_scaling(card->host); + /* send power off notification */ + if (mmc_card_mmc(card)) + mmc_send_pon(card); + return 0; } static const struct mmc_bus_ops mmc_ops = { @@ -1999,8 +2959,9 @@ .runtime_suspend = mmc_runtime_suspend, .runtime_resume = mmc_runtime_resume, .alive = mmc_alive, - .shutdown = mmc_shutdown, + .change_bus_speed = mmc_change_bus_speed, .reset = mmc_reset, + .shutdown = mmc_shutdown, }; /* @@ -2058,6 +3019,14 @@ goto remove_card; mmc_claim_host(host); + err = mmc_init_clk_scaling(host); + if (err) { + mmc_release_host(host); + goto remove_card; + } + + register_reboot_notifier(&host->card->reboot_notify); + return 0; remove_card: diff -ruw linux-4.4.115/drivers/mmc/core/mmc_ops.c linux-4.4.115-fbx/drivers/mmc/core/mmc_ops.c --- linux-4.4.115/drivers/mmc/core/mmc_ops.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/mmc/core/mmc_ops.c 2019-10-29 09:26:24.061207269 +0100 @@ -54,7 +54,7 @@ 0xff, 0x77, 0x77, 0xff, 0x77, 0xbb, 0xdd, 0xee, }; -static inline int __mmc_send_status(struct mmc_card *card, u32 *status, +int __mmc_send_status(struct mmc_card *card, u32 *status, bool ignore_crc) { int err; @@ -466,6 +466,45 @@ } /** + * mmc_prepare_switch - helper; prepare to modify EXT_CSD register + * @card: the MMC card associated with the data transfer + * @set: cmd set values + * @index: EXT_CSD register index + * @value: value to program into EXT_CSD register + * @tout_ms: timeout (ms) for operation performed by register write, + * timeout of zero implies maximum possible timeout + * @use_busy_signal: use the busy signal as response type + * + * Helper to prepare to modify EXT_CSD register for selected card. + */ + +static inline void mmc_prepare_switch(struct mmc_command *cmd, u8 index, + u8 value, u8 set, unsigned int tout_ms, + bool use_busy_signal) +{ + cmd->opcode = MMC_SWITCH; + cmd->arg = (MMC_SWITCH_MODE_WRITE_BYTE << 24) | + (index << 16) | + (value << 8) | + set; + cmd->flags = MMC_CMD_AC; + cmd->busy_timeout = tout_ms; + if (use_busy_signal) + cmd->flags |= MMC_RSP_SPI_R1B | MMC_RSP_R1B; + else + cmd->flags |= MMC_RSP_SPI_R1 | MMC_RSP_R1; +} + +int __mmc_switch_cmdq_mode(struct mmc_command *cmd, u8 set, u8 index, u8 value, + unsigned int timeout_ms, bool use_busy_signal, + bool ignore_timeout) +{ + mmc_prepare_switch(cmd, index, value, set, timeout_ms, use_busy_signal); + return 0; +} +EXPORT_SYMBOL(__mmc_switch_cmdq_mode); + +/** * __mmc_switch - modify EXT_CSD register * @card: the MMC card associated with the data transfer * @set: cmd set values @@ -489,6 +528,7 @@ unsigned long timeout; u32 status = 0; bool use_r1b_resp = use_busy_signal; + int retries = 5; mmc_retune_hold(host); @@ -502,12 +542,8 @@ (timeout_ms > host->max_busy_timeout)) use_r1b_resp = false; - cmd.opcode = MMC_SWITCH; - cmd.arg = (MMC_SWITCH_MODE_WRITE_BYTE << 24) | - (index << 16) | - (value << 8) | - set; - cmd.flags = MMC_CMD_AC; + mmc_prepare_switch(&cmd, index, value, set, timeout_ms, + use_r1b_resp); if (use_r1b_resp) { cmd.flags |= MMC_RSP_SPI_R1B | MMC_RSP_R1B; /* @@ -521,6 +557,8 @@ if (index == EXT_CSD_SANITIZE_START) cmd.sanitize_busy = true; + else if (index == EXT_CSD_BKOPS_START) + cmd.bkops_busy = true; err = mmc_wait_for_cmd(host, &cmd, MMC_CMD_RETRIES); if (err) @@ -566,11 +604,18 @@ /* Timeout if the device never leaves the program state. */ if (time_after(jiffies, timeout)) { - pr_err("%s: Card stuck in programming state! %s\n", - mmc_hostname(host), __func__); + pr_err("%s: Card stuck in programming state! %s, timeout:%ums, retries:%d\n", + mmc_hostname(host), __func__, + timeout_ms, retries); + if (retries) + timeout = jiffies + + msecs_to_jiffies(timeout_ms); + else { err = -ETIMEDOUT; goto out; } + retries--; + } } while (R1_CURRENT_STATE(status) == R1_STATE_PRG); err = mmc_switch_status_error(host, status); @@ -713,7 +758,10 @@ data.sg = &sg; data.sg_len = 1; + data.timeout_ns = 1000000; + data.timeout_clks = 0; mmc_set_data_timeout(&data, card); + sg_init_one(&sg, data_buf, len); mmc_wait_for_req(host, &mrq); err = 0; @@ -762,7 +810,7 @@ unsigned int opcode; int err; - if (!card->ext_csd.hpi) { + if (!card->ext_csd.hpi_en) { pr_warn("%s: Card didn't support HPI command\n", mmc_hostname(card->host)); return -EINVAL; @@ -779,7 +827,7 @@ err = mmc_wait_for_cmd(card->host, &cmd, 0); if (err) { - pr_warn("%s: error %d interrupting operation. " + pr_debug("%s: error %d interrupting operation. " "HPI command response %#x\n", mmc_hostname(card->host), err, cmd.resp[0]); return err; @@ -794,3 +842,21 @@ { return (card && card->csd.mmca_vsn > CSD_SPEC_VER_3); } + +int mmc_discard_queue(struct mmc_host *host, u32 tasks) +{ + struct mmc_command cmd = {0}; + + cmd.opcode = MMC_CMDQ_TASK_MGMT; + if (tasks) { + cmd.arg = DISCARD_TASK; + cmd.arg |= (tasks << 16); + } else { + cmd.arg = DISCARD_QUEUE; + } + + cmd.flags = MMC_RSP_R1B | MMC_CMD_AC; + + return mmc_wait_for_cmd(host, &cmd, 0); +} +EXPORT_SYMBOL(mmc_discard_queue); diff -ruw linux-4.4.115/drivers/mmc/core/mmc_ops.h linux-4.4.115-fbx/drivers/mmc/core/mmc_ops.h --- linux-4.4.115/drivers/mmc/core/mmc_ops.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/mmc/core/mmc_ops.h 2019-01-22 16:16:24.771257889 +0100 @@ -27,10 +27,12 @@ int mmc_bus_test(struct mmc_card *card, u8 bus_width); int mmc_send_hpi_cmd(struct mmc_card *card, u32 *status); int mmc_can_ext_csd(struct mmc_card *card); +int mmc_discard_queue(struct mmc_host *host, u32 tasks); int mmc_switch_status_error(struct mmc_host *host, u32 status); int __mmc_switch(struct mmc_card *card, u8 set, u8 index, u8 value, unsigned int timeout_ms, bool use_busy_signal, bool send_status, bool ignore_crc); - +int __mmc_send_status(struct mmc_card *card, u32 *status, + bool ignore_crc); #endif diff -ruw linux-4.4.115/drivers/mmc/core/quirks.c linux-4.4.115-fbx/drivers/mmc/core/quirks.c --- linux-4.4.115/drivers/mmc/core/quirks.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/mmc/core/quirks.c 2019-01-22 16:16:24.771257889 +0100 @@ -35,7 +35,85 @@ #define SDIO_DEVICE_ID_MARVELL_8797_F0 0x9128 #endif +#ifndef SDIO_VENDOR_ID_MSM +#define SDIO_VENDOR_ID_MSM 0x0070 +#endif + +#ifndef SDIO_DEVICE_ID_MSM_WCN1314 +#define SDIO_DEVICE_ID_MSM_WCN1314 0x2881 +#endif + +#ifndef SDIO_VENDOR_ID_MSM_QCA +#define SDIO_VENDOR_ID_MSM_QCA 0x271 +#endif + +#ifndef SDIO_DEVICE_ID_MSM_QCA_AR6003_1 +#define SDIO_DEVICE_ID_MSM_QCA_AR6003_1 0x300 +#endif + +#ifndef SDIO_DEVICE_ID_MSM_QCA_AR6003_2 +#define SDIO_DEVICE_ID_MSM_QCA_AR6003_2 0x301 +#endif + +#ifndef SDIO_DEVICE_ID_MSM_QCA_AR6004_1 +#define SDIO_DEVICE_ID_MSM_QCA_AR6004_1 0x400 +#endif + +#ifndef SDIO_DEVICE_ID_MSM_QCA_AR6004_2 +#define SDIO_DEVICE_ID_MSM_QCA_AR6004_2 0x401 +#endif + +#ifndef SDIO_VENDOR_ID_QCA6574 +#define SDIO_VENDOR_ID_QCA6574 0x271 +#endif + +#ifndef SDIO_DEVICE_ID_QCA6574 +#define SDIO_DEVICE_ID_QCA6574 0x50a +#endif + +#ifndef SDIO_VENDOR_ID_QCA9377 +#define SDIO_VENDOR_ID_QCA9377 0x271 +#endif + +#ifndef SDIO_DEVICE_ID_QCA9377 +#define SDIO_DEVICE_ID_QCA9377 0x701 +#endif + + +/* + * This hook just adds a quirk for all sdio devices + */ +static void add_quirk_for_sdio_devices(struct mmc_card *card, int data) +{ + if (mmc_card_sdio(card)) + card->quirks |= data; +} + static const struct mmc_fixup mmc_fixup_methods[] = { + /* by default sdio devices are considered CLK_GATING broken */ + /* good cards will be whitelisted as they are tested */ + SDIO_FIXUP(SDIO_ANY_ID, SDIO_ANY_ID, + add_quirk_for_sdio_devices, + MMC_QUIRK_BROKEN_CLK_GATING), + + SDIO_FIXUP(SDIO_VENDOR_ID_TI, SDIO_DEVICE_ID_TI_WL1271, + remove_quirk, MMC_QUIRK_BROKEN_CLK_GATING), + + SDIO_FIXUP(SDIO_VENDOR_ID_MSM, SDIO_DEVICE_ID_MSM_WCN1314, + remove_quirk, MMC_QUIRK_BROKEN_CLK_GATING), + + SDIO_FIXUP(SDIO_VENDOR_ID_MSM_QCA, SDIO_DEVICE_ID_MSM_QCA_AR6003_1, + remove_quirk, MMC_QUIRK_BROKEN_CLK_GATING), + + SDIO_FIXUP(SDIO_VENDOR_ID_MSM_QCA, SDIO_DEVICE_ID_MSM_QCA_AR6003_2, + remove_quirk, MMC_QUIRK_BROKEN_CLK_GATING), + + SDIO_FIXUP(SDIO_VENDOR_ID_MSM_QCA, SDIO_DEVICE_ID_MSM_QCA_AR6004_1, + remove_quirk, MMC_QUIRK_BROKEN_CLK_GATING), + + SDIO_FIXUP(SDIO_VENDOR_ID_MSM_QCA, SDIO_DEVICE_ID_MSM_QCA_AR6004_2, + remove_quirk, MMC_QUIRK_BROKEN_CLK_GATING), + SDIO_FIXUP(SDIO_VENDOR_ID_TI, SDIO_DEVICE_ID_TI_WL1271, add_quirk, MMC_QUIRK_NONSTD_FUNC_IF), @@ -48,6 +126,11 @@ SDIO_FIXUP(SDIO_VENDOR_ID_MARVELL, SDIO_DEVICE_ID_MARVELL_8797_F0, add_quirk, MMC_QUIRK_BROKEN_IRQ_POLLING), + SDIO_FIXUP(SDIO_VENDOR_ID_QCA6574, SDIO_DEVICE_ID_QCA6574, + add_quirk, MMC_QUIRK_QCA6574_SETTINGS), + + SDIO_FIXUP(SDIO_VENDOR_ID_QCA9377, SDIO_DEVICE_ID_QCA9377, + add_quirk, MMC_QUIRK_QCA9377_SETTINGS), END_FIXUP }; @@ -68,6 +151,8 @@ (f->name == CID_NAME_ANY || !strncmp(f->name, card->cid.prod_name, sizeof(card->cid.prod_name))) && + (f->ext_csd_rev == EXT_CSD_REV_ANY || + f->ext_csd_rev == card->ext_csd.rev) && (f->cis_vendor == card->cis.vendor || f->cis_vendor == (u16) SDIO_ANY_ID) && (f->cis_device == card->cis.device || diff -ruw linux-4.4.115/drivers/mmc/core/sd.c linux-4.4.115-fbx/drivers/mmc/core/sd.c --- linux-4.4.115/drivers/mmc/core/sd.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/mmc/core/sd.c 2019-10-29 09:26:24.061207269 +0100 @@ -27,6 +27,12 @@ #include "sd.h" #include "sd_ops.h" +#define UHS_SDR104_MIN_DTR (100 * 1000 * 1000) +#define UHS_DDR50_MIN_DTR (50 * 1000 * 1000) +#define UHS_SDR50_MIN_DTR (50 * 1000 * 1000) +#define UHS_SDR25_MIN_DTR (25 * 1000 * 1000) +#define UHS_SDR12_MIN_DTR (12.5 * 1000 * 1000) + static const unsigned int tran_exp[] = { 10000, 100000, 1000000, 10000000, 0, 0, 0, 0 @@ -369,9 +375,9 @@ goto out; if ((status[16] & 0xF) != 1) { - pr_warn("%s: Problem switching card into high-speed mode!\n", - mmc_hostname(card->host)); - err = 0; + pr_warn("%s: Problem switching card into high-speed mode!, status:%x\n", + mmc_hostname(card->host), (status[16] & 0xF)); + err = -EBUSY; } else { err = 1; } @@ -425,18 +431,22 @@ } if ((card->host->caps & MMC_CAP_UHS_SDR104) && - (card->sw_caps.sd3_bus_mode & SD_MODE_UHS_SDR104)) { + (card->sw_caps.sd3_bus_mode & SD_MODE_UHS_SDR104) && + (card->host->f_max > UHS_SDR104_MIN_DTR)) { card->sd_bus_speed = UHS_SDR104_BUS_SPEED; - } else if ((card->host->caps & MMC_CAP_UHS_DDR50) && - (card->sw_caps.sd3_bus_mode & SD_MODE_UHS_DDR50)) { - card->sd_bus_speed = UHS_DDR50_BUS_SPEED; } else if ((card->host->caps & (MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50)) && (card->sw_caps.sd3_bus_mode & - SD_MODE_UHS_SDR50)) { + SD_MODE_UHS_SDR50) && + (card->host->f_max > UHS_SDR50_MIN_DTR)) { card->sd_bus_speed = UHS_SDR50_BUS_SPEED; + } else if ((card->host->caps & MMC_CAP_UHS_DDR50) && + (card->sw_caps.sd3_bus_mode & SD_MODE_UHS_DDR50) && + (card->host->f_max > UHS_DDR50_MIN_DTR)) { + card->sd_bus_speed = UHS_DDR50_BUS_SPEED; } else if ((card->host->caps & (MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_SDR25)) && - (card->sw_caps.sd3_bus_mode & SD_MODE_UHS_SDR25)) { + (card->sw_caps.sd3_bus_mode & SD_MODE_UHS_SDR25) && + (card->host->f_max > UHS_SDR25_MIN_DTR)) { card->sd_bus_speed = UHS_SDR25_BUS_SPEED; } else if ((card->host->caps & (MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_SDR25 | @@ -480,15 +490,17 @@ if (err) return err; - if ((status[16] & 0xF) != card->sd_bus_speed) - pr_warn("%s: Problem setting bus speed mode!\n", - mmc_hostname(card->host)); - else { + if ((status[16] & 0xF) != card->sd_bus_speed) { + pr_warn("%s: Problem setting bus speed mode(%u)! max_dtr:%u, timing:%u, status:%x\n", + mmc_hostname(card->host), card->sd_bus_speed, + card->sw_caps.uhs_max_dtr, timing, (status[16] & 0xF)); + err = -EBUSY; + } else { mmc_set_timing(card->host, timing); mmc_set_clock(card->host, card->sw_caps.uhs_max_dtr); } - return 0; + return err; } /* Get host's max current setting at its current voltage */ @@ -569,6 +581,64 @@ return 0; } +/** + * mmc_sd_change_bus_speed() - Change SD card bus frequency at runtime + * @host: pointer to mmc host structure + * @freq: pointer to desired frequency to be set + * + * Change the SD card bus frequency at runtime after the card is + * initialized. Callers are expected to make sure of the card's + * state (DATA/RCV/TRANSFER) beforing changing the frequency at runtime. + * + * If the frequency to change is greater than max. supported by card, + * *freq is changed to max. supported by card and if it is less than min. + * supported by host, *freq is changed to min. supported by host. + */ +static int mmc_sd_change_bus_speed(struct mmc_host *host, unsigned long *freq) +{ + int err = 0; + struct mmc_card *card; + + mmc_claim_host(host); + /* + * Assign card pointer after claiming host to avoid race + * conditions that may arise during removal of the card. + */ + card = host->card; + + /* sanity checks */ + if (!card || !freq) { + err = -EINVAL; + goto out; + } + + mmc_set_clock(host, (unsigned int) (*freq)); + + if (!mmc_host_is_spi(card->host) && mmc_card_uhs(card) + && card->host->ops->execute_tuning) { + /* + * We try to probe host driver for tuning for any + * frequency, it is host driver responsibility to + * perform actual tuning only when required. + */ + mmc_host_clk_hold(card->host); + err = card->host->ops->execute_tuning(card->host, + MMC_SEND_TUNING_BLOCK); + mmc_host_clk_release(card->host); + + if (err) { + pr_warn("%s: %s: tuning execution failed %d. Restoring to previous clock %lu\n", + mmc_hostname(card->host), __func__, err, + host->clk_scaling.curr_freq); + mmc_set_clock(host, host->clk_scaling.curr_freq); + } + } + +out: + mmc_release_host(host); + return err; +} + /* * UHS-I specific initialization procedure */ @@ -800,7 +870,9 @@ if (!host->ops->get_ro) return -1; + mmc_host_clk_hold(host); ro = host->ops->get_ro(host); + mmc_host_clk_release(host); return ro; } @@ -809,6 +881,9 @@ bool reinit) { int err; +#ifdef CONFIG_MMC_PARANOID_SD_INIT + int retries; +#endif if (!reinit) { /* @@ -835,7 +910,26 @@ /* * Fetch switch information from card. */ +#ifdef CONFIG_MMC_PARANOID_SD_INIT + for (retries = 1; retries <= 3; retries++) { + err = mmc_read_switch(card); + if (!err) { + if (retries > 1) { + printk(KERN_WARNING + "%s: recovered\n", + mmc_hostname(host)); + } + break; + } else { + printk(KERN_WARNING + "%s: read switch failed (attempt %d)\n", + mmc_hostname(host), retries); + } + } +#else err = mmc_read_switch(card); +#endif + if (err) return err; } @@ -873,7 +967,10 @@ { unsigned max_dtr = (unsigned int)-1; - if (mmc_card_hs(card)) { + if (mmc_card_uhs(card)) { + if (max_dtr > card->sw_caps.uhs_max_dtr) + max_dtr = card->sw_caps.uhs_max_dtr; + } else if (mmc_card_hs(card)) { if (max_dtr > card->sw_caps.hs_max_dtr) max_dtr = card->sw_caps.hs_max_dtr; } else if (max_dtr > card->csd.max_dtr) { @@ -935,6 +1032,7 @@ err = mmc_send_relative_addr(host, &card->rca); if (err) goto free_card; + host->card = card; } if (!oldcard) { @@ -998,12 +1096,16 @@ } } - host->card = card; + card->clk_scaling_highest = mmc_sd_get_max_clock(card); + card->clk_scaling_lowest = host->f_min; + return 0; free_card: - if (!oldcard) + if (!oldcard) { + host->card = NULL; mmc_remove_card(card); + } return err; } @@ -1016,8 +1118,12 @@ BUG_ON(!host); BUG_ON(!host->card); + mmc_exit_clk_scaling(host); mmc_remove_card(host->card); + + mmc_claim_host(host); host->card = NULL; + mmc_release_host(host); } /* @@ -1033,17 +1139,49 @@ */ static void mmc_sd_detect(struct mmc_host *host) { - int err; + int err = 0; +#ifdef CONFIG_MMC_PARANOID_SD_INIT + int retries = 5; +#endif BUG_ON(!host); BUG_ON(!host->card); - mmc_get_card(host->card); + /* + * Try to acquire claim host. If failed to get the lock in 2 sec, + * just return; This is to ensure that when this call is invoked + * due to pm_suspend, not to block suspend for longer duration. + */ + pm_runtime_get_sync(&host->card->dev); + if (!mmc_try_claim_host(host, 2000)) { + pm_runtime_mark_last_busy(&host->card->dev); + pm_runtime_put_autosuspend(&host->card->dev); + return; + } + + mmc_power_up(host, host->ocr_avail); /* * Just check if our card has been removed. */ +#ifdef CONFIG_MMC_PARANOID_SD_INIT + while(retries) { + err = mmc_send_status(host->card, NULL); + if (err) { + retries--; + udelay(5); + continue; + } + break; + } + if (!retries) { + printk(KERN_ERR "%s(%s): Unable to re-detect card (%d)\n", + __func__, mmc_hostname(host), err); + err = _mmc_detect_card_removed(host); + } +#else err = _mmc_detect_card_removed(host); +#endif mmc_put_card(host->card); @@ -1064,6 +1202,13 @@ BUG_ON(!host); BUG_ON(!host->card); + err = mmc_suspend_clk_scaling(host); + if (err) { + pr_err("%s: %s: fail to suspend clock scaling (%d)\n", + mmc_hostname(host), __func__, err); + return err; + } + mmc_claim_host(host); if (mmc_card_suspended(host->card)) @@ -1089,11 +1234,16 @@ { int err; + MMC_TRACE(host, "%s: Enter\n", __func__); err = _mmc_sd_suspend(host); if (!err) { pm_runtime_disable(&host->card->dev); pm_runtime_set_suspended(&host->card->dev); - } + /* if suspend fails, force mmc_detect_change during resume */ + } else if (mmc_bus_manual_resume(host)) + host->ignore_bus_resume_flags = true; + + MMC_TRACE(host, "%s: Exit err: %d\n", __func__, err); return err; } @@ -1105,6 +1255,9 @@ static int _mmc_sd_resume(struct mmc_host *host) { int err = 0; +#ifdef CONFIG_MMC_PARANOID_SD_INIT + int retries; +#endif BUG_ON(!host); BUG_ON(!host->card); @@ -1115,9 +1268,43 @@ goto out; mmc_power_up(host, host->card->ocr); +#ifdef CONFIG_MMC_PARANOID_SD_INIT + retries = 5; + while (retries) { err = mmc_sd_init_card(host, host->card->ocr, host->card); + + if (err) { + printk(KERN_ERR "%s: Re-init card rc = %d (retries = %d)\n", + mmc_hostname(host), err, retries); + retries--; + mmc_power_off(host); + usleep_range(5000, 5500); + mmc_power_up(host, host->card->ocr); + mmc_select_voltage(host, host->card->ocr); + continue; + } + break; + } +#else + err = mmc_sd_init_card(host, host->card->ocr, host->card); +#endif + if (err) { + pr_err("%s: %s: mmc_sd_init_card_failed (%d)\n", + mmc_hostname(host), __func__, err); + mmc_power_off(host); + goto out; + } mmc_card_clr_suspended(host->card); + if (host->card->sdr104_blocked) + goto out; + err = mmc_resume_clk_scaling(host); + if (err) { + pr_err("%s: %s: fail to resume clock scaling (%d)\n", + mmc_hostname(host), __func__, err); + goto out; + } + out: mmc_release_host(host); return err; @@ -1130,12 +1317,14 @@ { int err = 0; + MMC_TRACE(host, "%s: Enter\n", __func__); if (!(host->caps & MMC_CAP_RUNTIME_RESUME)) { err = _mmc_sd_resume(host); pm_runtime_set_active(&host->card->dev); pm_runtime_mark_last_busy(&host->card->dev); } pm_runtime_enable(&host->card->dev); + MMC_TRACE(host, "%s: Exit err: %d\n", __func__, err); return err; } @@ -1190,7 +1379,7 @@ .suspend = mmc_sd_suspend, .resume = mmc_sd_resume, .alive = mmc_sd_alive, - .shutdown = mmc_sd_suspend, + .change_bus_speed = mmc_sd_change_bus_speed, .reset = mmc_sd_reset, }; @@ -1201,6 +1390,9 @@ { int err; u32 ocr, rocr; +#ifdef CONFIG_MMC_PARANOID_SD_INIT + int retries; +#endif BUG_ON(!host); WARN_ON(!host->claimed); @@ -1237,9 +1429,31 @@ /* * Detect and init the card. */ +#ifdef CONFIG_MMC_PARANOID_SD_INIT + retries = 5; + while (retries) { + err = mmc_sd_init_card(host, rocr, NULL); + if (err) { + retries--; + mmc_power_off(host); + usleep_range(5000, 5500); + mmc_power_up(host, rocr); + mmc_select_voltage(host, rocr); + continue; + } + break; + } + + if (!retries) { + printk(KERN_ERR "%s: mmc_sd_init_card() failure (err = %d)\n", + mmc_hostname(host), err); + goto err; + } +#else err = mmc_sd_init_card(host, rocr, NULL); if (err) goto err; +#endif mmc_release_host(host); err = mmc_add_card(host->card); @@ -1247,6 +1461,13 @@ goto remove_card; mmc_claim_host(host); + + err = mmc_init_clk_scaling(host); + if (err) { + mmc_release_host(host); + goto remove_card; + } + return 0; remove_card: diff -ruw linux-4.4.115/drivers/mmc/core/sdio_bus.c linux-4.4.115-fbx/drivers/mmc/core/sdio_bus.c --- linux-4.4.115/drivers/mmc/core/sdio_bus.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/mmc/core/sdio_bus.c 2019-01-22 16:16:24.775257925 +0100 @@ -28,6 +28,10 @@ #include "sdio_cis.h" #include "sdio_bus.h" +#ifdef CONFIG_MMC_EMBEDDED_SDIO +#include +#endif + #define to_sdio_driver(d) container_of(d, struct sdio_driver, drv) /* show configuration fields */ @@ -263,6 +267,13 @@ { struct sdio_func *func = dev_to_sdio_func(dev); +#ifdef CONFIG_MMC_EMBEDDED_SDIO + /* + * If this device is embedded then we never allocated + * cis tables for this func + */ + if (!func->card->host->embedded_sdio_data.funcs) +#endif sdio_free_func_cis(func); kfree(func->info); diff -ruw linux-4.4.115/drivers/mmc/core/sdio.c linux-4.4.115-fbx/drivers/mmc/core/sdio.c --- linux-4.4.115/drivers/mmc/core/sdio.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/mmc/core/sdio.c 2019-01-22 16:16:24.775257925 +0100 @@ -10,6 +10,7 @@ */ #include +#include #include #include @@ -21,6 +22,7 @@ #include "core.h" #include "bus.h" +#include "host.h" #include "sd.h" #include "sdio_bus.h" #include "mmc_ops.h" @@ -28,6 +30,10 @@ #include "sdio_ops.h" #include "sdio_cis.h" +#ifdef CONFIG_MMC_EMBEDDED_SDIO +#include +#endif + static int sdio_read_fbr(struct sdio_func *func) { int ret; @@ -182,6 +188,23 @@ card->sw_caps.sd3_drv_type |= SD_DRIVER_TYPE_C; if (data & SDIO_DRIVE_SDTD) card->sw_caps.sd3_drv_type |= SD_DRIVER_TYPE_D; + + ret = mmc_io_rw_direct(card, 0, 0, + SDIO_CCCR_INTERRUPT_EXTENSION, 0, &data); + if (ret) + goto out; + if (data & SDIO_SUPPORT_ASYNC_INTR) { + if (card->host->caps2 & + MMC_CAP2_ASYNC_SDIO_IRQ_4BIT_MODE) { + data |= SDIO_ENABLE_ASYNC_INTR; + ret = mmc_io_rw_direct(card, 1, 0, + SDIO_CCCR_INTERRUPT_EXTENSION, + data, NULL); + if (ret) + goto out; + card->cccr.async_intr_sup = 1; + } + } } /* if no uhs mode ensure we check for high speed */ @@ -200,12 +223,60 @@ return ret; } +static void sdio_enable_vendor_specific_settings(struct mmc_card *card) +{ + int ret; + u8 settings; + + if (mmc_enable_qca6574_settings(card) || + mmc_enable_qca9377_settings(card)) { + ret = mmc_io_rw_direct(card, 1, 0, 0xF2, 0x0F, NULL); + if (ret) { + pr_crit("%s: failed to write to fn 0xf2 %d\n", + mmc_hostname(card->host), ret); + goto out; + } + + ret = mmc_io_rw_direct(card, 0, 0, 0xF1, 0, &settings); + if (ret) { + pr_crit("%s: failed to read fn 0xf1 %d\n", + mmc_hostname(card->host), ret); + goto out; + } + + settings |= 0x80; + ret = mmc_io_rw_direct(card, 1, 0, 0xF1, settings, NULL); + if (ret) { + pr_crit("%s: failed to write to fn 0xf1 %d\n", + mmc_hostname(card->host), ret); + goto out; + } + + ret = mmc_io_rw_direct(card, 0, 0, 0xF0, 0, &settings); + if (ret) { + pr_crit("%s: failed to read fn 0xf0 %d\n", + mmc_hostname(card->host), ret); + goto out; + } + + settings |= 0x20; + ret = mmc_io_rw_direct(card, 1, 0, 0xF0, settings, NULL); + if (ret) { + pr_crit("%s: failed to write to fn 0xf0 %d\n", + mmc_hostname(card->host), ret); + goto out; + } + } +out: + return; +} + static int sdio_enable_wide(struct mmc_card *card) { int ret; u8 ctrl; - if (!(card->host->caps & MMC_CAP_4_BIT_DATA)) + if (!(card->host->caps & (MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA))) return 0; if (card->cccr.low_speed && !card->cccr.wide_bus) @@ -221,6 +292,9 @@ /* set as 4-bit bus width */ ctrl &= ~SDIO_BUS_WIDTH_MASK; + if (card->host->caps & MMC_CAP_8_BIT_DATA) + ctrl |= SDIO_BUS_WIDTH_8BIT; + else if (card->host->caps & MMC_CAP_4_BIT_DATA) ctrl |= SDIO_BUS_WIDTH_4BIT; ret = mmc_io_rw_direct(card, 1, 0, SDIO_CCCR_IF, ctrl, NULL); @@ -262,7 +336,7 @@ int ret; u8 ctrl; - if (!(card->host->caps & MMC_CAP_4_BIT_DATA)) + if (!(card->host->caps & (MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA))) return 0; if (card->cccr.low_speed && !card->cccr.wide_bus) @@ -272,10 +346,10 @@ if (ret) return ret; - if (!(ctrl & SDIO_BUS_WIDTH_4BIT)) + if (!(ctrl & (SDIO_BUS_WIDTH_4BIT | SDIO_BUS_WIDTH_8BIT))) return 0; - ctrl &= ~SDIO_BUS_WIDTH_4BIT; + ctrl &= ~(SDIO_BUS_WIDTH_4BIT | SDIO_BUS_WIDTH_8BIT); ctrl |= SDIO_BUS_ASYNC_INT; ret = mmc_io_rw_direct(card, 1, 0, SDIO_CCCR_IF, ctrl, NULL); @@ -492,6 +566,9 @@ if (err) return err; + /* Vendor specific settings based on card quirks */ + sdio_enable_vendor_specific_settings(card); + speed &= ~SDIO_SPEED_BSS_MASK; speed |= bus_speed; err = mmc_io_rw_direct(card, 1, 0, SDIO_CCCR_SPEED, speed, NULL); @@ -618,8 +695,11 @@ /* * Call the optional HC's init_card function to handle quirks. */ - if (host->ops->init_card) + if (host->ops->init_card) { + mmc_host_clk_hold(host); host->ops->init_card(host, card); + mmc_host_clk_release(host); + } /* * If the host and card support UHS-I mode request the card @@ -699,19 +779,35 @@ goto finish; } +#ifdef CONFIG_MMC_EMBEDDED_SDIO + if (host->embedded_sdio_data.cccr) + memcpy(&card->cccr, host->embedded_sdio_data.cccr, sizeof(struct sdio_cccr)); + else { +#endif /* * Read the common registers. */ err = sdio_read_cccr(card, ocr); if (err) goto remove; +#ifdef CONFIG_MMC_EMBEDDED_SDIO + } +#endif +#ifdef CONFIG_MMC_EMBEDDED_SDIO + if (host->embedded_sdio_data.cis) + memcpy(&card->cis, host->embedded_sdio_data.cis, sizeof(struct sdio_cis)); + else { +#endif /* * Read the common CIS tuples. */ err = sdio_read_common_cis(card); if (err) goto remove; +#ifdef CONFIG_MMC_EMBEDDED_SDIO + } +#endif if (oldcard) { int same = (card->cis.vendor == oldcard->cis.vendor && @@ -770,7 +866,12 @@ * Switch to wider bus (if supported). */ err = sdio_enable_4bit_bus(card); - if (err) + if (err > 0) { + if (card->host->caps & MMC_CAP_8_BIT_DATA) + mmc_set_bus_width(card->host, MMC_BUS_WIDTH_8); + else if (card->host->caps & MMC_CAP_4_BIT_DATA) + mmc_set_bus_width(card->host, MMC_BUS_WIDTH_4); + } else if (err) goto remove; } finish: @@ -897,6 +998,7 @@ */ static int mmc_sdio_suspend(struct mmc_host *host) { + MMC_TRACE(host, "%s: Enter\n", __func__); mmc_claim_host(host); if (mmc_card_keep_power(host) && mmc_card_wake_sdio_irq(host)) @@ -904,13 +1006,15 @@ if (!mmc_card_keep_power(host)) { mmc_power_off(host); + } else if (host->ios.clock) { + mmc_gate_clock(host); } else if (host->retune_period) { mmc_retune_timer_stop(host); mmc_retune_needed(host); } mmc_release_host(host); - + MMC_TRACE(host, "%s: Exit\n", __func__); return 0; } @@ -921,6 +1025,7 @@ BUG_ON(!host); BUG_ON(!host->card); + MMC_TRACE(host, "%s: Enter\n", __func__); /* Basic card reinitialization. */ mmc_claim_host(host); @@ -953,18 +1058,30 @@ } else if (mmc_card_keep_power(host) && mmc_card_wake_sdio_irq(host)) { /* We may have switched to 1-bit mode during suspend */ err = sdio_enable_4bit_bus(host->card); + if (err > 0) { + if (host->caps & MMC_CAP_8_BIT_DATA) + mmc_set_bus_width(host, MMC_BUS_WIDTH_8); + else if (host->caps & MMC_CAP_4_BIT_DATA) + mmc_set_bus_width(host, MMC_BUS_WIDTH_4); + err = 0; + } } if (!err && host->sdio_irqs) { - if (!(host->caps2 & MMC_CAP2_SDIO_IRQ_NOTHREAD)) + if (!(host->caps2 & MMC_CAP2_SDIO_IRQ_NOTHREAD)) { wake_up_process(host->sdio_irq_thread); - else if (host->caps & MMC_CAP_SDIO_IRQ) + } else if (host->caps & MMC_CAP_SDIO_IRQ) { + mmc_host_clk_hold(host); host->ops->enable_sdio_irq(host, 1); + mmc_host_clk_release(host); + } } mmc_release_host(host); host->pm_flags &= ~MMC_PM_KEEP_POWER; + host->pm_flags &= ~MMC_PM_WAKE_SDIO_IRQ; + MMC_TRACE(host, "%s: Exit err: %d\n", __func__, err); return err; } @@ -1120,14 +1237,36 @@ funcs = (ocr & 0x70000000) >> 28; card->sdio_funcs = 0; +#ifdef CONFIG_MMC_EMBEDDED_SDIO + if (host->embedded_sdio_data.funcs) + card->sdio_funcs = funcs = host->embedded_sdio_data.num_funcs; +#endif + /* * Initialize (but don't add) all present functions. */ for (i = 0; i < funcs; i++, card->sdio_funcs++) { +#ifdef CONFIG_MMC_EMBEDDED_SDIO + if (host->embedded_sdio_data.funcs) { + struct sdio_func *tmp; + + tmp = sdio_alloc_func(host->card); + if (IS_ERR(tmp)) + goto remove; + tmp->num = (i + 1); + card->sdio_func[i] = tmp; + tmp->class = host->embedded_sdio_data.funcs[i].f_class; + tmp->max_blksize = host->embedded_sdio_data.funcs[i].f_maxblksize; + tmp->vendor = card->cis.vendor; + tmp->device = card->cis.device; + } else { +#endif err = sdio_init_func(host->card, i + 1); if (err) goto remove; - +#ifdef CONFIG_MMC_EMBEDDED_SDIO + } +#endif /* * Enable Runtime PM for this func (if supported) */ @@ -1175,3 +1314,8 @@ return err; } +int sdio_reset_comm(struct mmc_card *card) +{ + return mmc_power_restore_host(card->host); +} +EXPORT_SYMBOL(sdio_reset_comm); diff -ruw linux-4.4.115/drivers/mmc/core/sdio_cis.c linux-4.4.115-fbx/drivers/mmc/core/sdio_cis.c --- linux-4.4.115/drivers/mmc/core/sdio_cis.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/mmc/core/sdio_cis.c 2019-01-22 16:16:24.775257925 +0100 @@ -55,7 +55,7 @@ for (i = 0; i < nr_strings; i++) { buffer[i] = string; - strcpy(string, buf); + strlcpy(string, buf, strlen(buf) + 1); string += strlen(string) + 1; buf += strlen(buf) + 1; } @@ -270,8 +270,16 @@ break; /* null entries have no link field or data */ - if (tpl_code == 0x00) + if (tpl_code == 0x00) { + if (card->cis.vendor == 0x70 && + (card->cis.device == 0x2460 || + card->cis.device == 0x0460 || + card->cis.device == 0x23F1 || + card->cis.device == 0x23F0)) + break; + else continue; + } ret = mmc_io_rw_direct(card, 0, 0, ptr++, 0, &tpl_link); if (ret) diff -ruw linux-4.4.115/drivers/mmc/core/sdio_io.c linux-4.4.115-fbx/drivers/mmc/core/sdio_io.c --- linux-4.4.115/drivers/mmc/core/sdio_io.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/mmc/core/sdio_io.c 2019-01-22 16:16:24.775257925 +0100 @@ -384,6 +384,39 @@ EXPORT_SYMBOL_GPL(sdio_readb); /** + * sdio_readb_ext - read a single byte from a SDIO function + * @func: SDIO function to access + * @addr: address to read + * @err_ret: optional status value from transfer + * @in: value to add to argument + * + * Reads a single byte from the address space of a given SDIO + * function. If there is a problem reading the address, 0xff + * is returned and @err_ret will contain the error code. + */ +unsigned char sdio_readb_ext(struct sdio_func *func, unsigned int addr, + int *err_ret, unsigned in) +{ + int ret; + unsigned char val; + + BUG_ON(!func); + + if (err_ret) + *err_ret = 0; + + ret = mmc_io_rw_direct(func->card, 0, func->num, addr, (u8)in, &val); + if (ret) { + if (err_ret) + *err_ret = ret; + return 0xFF; + } + + return val; +} +EXPORT_SYMBOL_GPL(sdio_readb_ext); + +/** * sdio_writeb - write a single byte to a SDIO function * @func: SDIO function to access * @b: byte to write diff -ruw linux-4.4.115/drivers/mmc/core/sdio_irq.c linux-4.4.115-fbx/drivers/mmc/core/sdio_irq.c --- linux-4.4.115/drivers/mmc/core/sdio_irq.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/mmc/core/sdio_irq.c 2019-01-22 16:16:24.775257925 +0100 @@ -93,7 +93,9 @@ { mmc_claim_host(host); host->sdio_irq_pending = true; + mmc_host_clk_hold(host); process_sdio_pending_irqs(host); + mmc_host_clk_release(host); mmc_release_host(host); } EXPORT_SYMBOL_GPL(sdio_run_irqs); @@ -104,6 +106,7 @@ struct sched_param param = { .sched_priority = 1 }; unsigned long period, idle_period; int ret; + bool ws; sched_setscheduler(current, SCHED_FIFO, ¶m); @@ -137,6 +140,17 @@ ret = __mmc_claim_host(host, &host->sdio_irq_thread_abort); if (ret) break; + ws = false; + /* + * prevent suspend if it has started when scheduled; + * 100 msec (approx. value) should be enough for the system to + * resume and attend to the card's request + */ + if ((host->dev_status == DEV_SUSPENDING) || + (host->dev_status == DEV_SUSPENDED)) { + pm_wakeup_event(&host->card->dev, 100); + ws = true; + } ret = process_sdio_pending_irqs(host); host->sdio_irq_pending = false; mmc_release_host(host); @@ -168,15 +182,27 @@ } set_current_state(TASK_INTERRUPTIBLE); - if (host->caps & MMC_CAP_SDIO_IRQ) + if (host->caps & MMC_CAP_SDIO_IRQ) { + mmc_host_clk_hold(host); host->ops->enable_sdio_irq(host, 1); + mmc_host_clk_release(host); + } + /* + * function drivers would have processed the event from card + * unless suspended, hence release wake source + */ + if (ws && (host->dev_status == DEV_RESUMED)) + pm_relax(&host->card->dev); if (!kthread_should_stop()) schedule_timeout(period); set_current_state(TASK_RUNNING); } while (!kthread_should_stop()); - if (host->caps & MMC_CAP_SDIO_IRQ) + if (host->caps & MMC_CAP_SDIO_IRQ) { + mmc_host_clk_hold(host); host->ops->enable_sdio_irq(host, 0); + mmc_host_clk_release(host); + } pr_debug("%s: IRQ thread exiting with code %d\n", mmc_hostname(host), ret); @@ -202,7 +228,9 @@ return err; } } else if (host->caps & MMC_CAP_SDIO_IRQ) { + mmc_host_clk_hold(host); host->ops->enable_sdio_irq(host, 1); + mmc_host_clk_release(host); } } @@ -221,7 +249,9 @@ atomic_set(&host->sdio_irq_thread_abort, 1); kthread_stop(host->sdio_irq_thread); } else if (host->caps & MMC_CAP_SDIO_IRQ) { + mmc_host_clk_hold(host); host->ops->enable_sdio_irq(host, 0); + mmc_host_clk_release(host); } } diff -ruw linux-4.4.115/drivers/mmc/host/Kconfig linux-4.4.115-fbx/drivers/mmc/host/Kconfig --- linux-4.4.115/drivers/mmc/host/Kconfig 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/mmc/host/Kconfig 2019-01-22 16:16:24.775257925 +0100 @@ -406,18 +406,39 @@ If unsure, say N. config MMC_SDHCI_MSM - tristate "Qualcomm SDHCI Controller Support" - depends on ARCH_QCOM || (ARM && COMPILE_TEST) + tristate "Qualcomm Technologies, Inc. SDHCI Controller Support" + depends on ARCH_QCOM || ARCH_MSM || (ARM && COMPILE_TEST) depends on MMC_SDHCI_PLTFM + select PM_DEVFREQ + select DEVFREQ_GOV_SIMPLE_ONDEMAND help This selects the Secure Digital Host Controller Interface (SDHCI) - support present in Qualcomm SOCs. The controller supports - SD/MMC/SDIO devices. + support present in Qualcomm Technologies, Inc. SOCs. The controller + supports SD/MMC/SDIO devices. If you have a controller with this interface, say Y or M here. If unsure, say N. +config MMC_SDHCI_MSM_ICE + bool "Qualcomm Technologies, Inc Inline Crypto Engine for SDHCI core" + depends on MMC_SDHCI_MSM && CRYPTO_DEV_QCOM_ICE + help + This selects the QTI specific additions to support Inline Crypto + Engine (ICE). ICE accelerates the crypto operations and maintains + the high SDHCI performance. + + Select this if you have ICE supported for SDHCI on QTI chipset. + If unsure, say N. + +config MMC_MSM + tristate "Qualcomm SDCC Controller Support" + depends on MMC && (ARCH_MSM7X00A || ARCH_MSM7X30 || ARCH_QSD8X50) + help + This provides support for the SD/MMC cell found in the + MSM and QSD SOCs from Qualcomm. The controller also has + support for SDIO devices. + config MMC_MXC tristate "Freescale i.MX21/27/31 or MPC512x Multimedia Card support" depends on ARCH_MXC || PPC_MPC512x @@ -773,6 +794,19 @@ This selects support for the SD/MMC Host Controller on Allwinner sunxi SoCs. +config MMC_CQ_HCI + tristate "Command Queue Support" + depends on HAS_DMA + help + This selects the Command Queue Host Controller Interface (CQHCI) + support present in host controllers of Qualcomm Technologies, Inc + amongst others. + This controller supports eMMC devices with command queue support. + + If you have a controller with this interface, say Y or M here. + + If unsure, say N. + config MMC_TOSHIBA_PCI tristate "Toshiba Type A SD/MMC Card Interface Driver" depends on PCI diff -ruw linux-4.4.115/drivers/mmc/host/Makefile linux-4.4.115-fbx/drivers/mmc/host/Makefile --- linux-4.4.115/drivers/mmc/host/Makefile 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/mmc/host/Makefile 2019-01-22 16:16:24.775257925 +0100 @@ -72,9 +72,11 @@ obj-$(CONFIG_MMC_SDHCI_OF_HLWD) += sdhci-of-hlwd.o obj-$(CONFIG_MMC_SDHCI_BCM_KONA) += sdhci-bcm-kona.o obj-$(CONFIG_MMC_SDHCI_BCM2835) += sdhci-bcm2835.o -obj-$(CONFIG_MMC_SDHCI_IPROC) += sdhci-iproc.o obj-$(CONFIG_MMC_SDHCI_MSM) += sdhci-msm.o +obj-$(CONFIG_MMC_SDHCI_MSM_ICE) += sdhci-msm-ice.o +obj-$(CONFIG_MMC_SDHCI_IPROC) += sdhci-iproc.o obj-$(CONFIG_MMC_SDHCI_ST) += sdhci-st.o +obj-$(CONFIG_MMC_CQ_HCI) += cmdq_hci.o ifeq ($(CONFIG_CB710_DEBUG),y) CFLAGS-cb710-mmc += -DDEBUG diff -ruw linux-4.4.115/drivers/mmc/host/sdhci.c linux-4.4.115-fbx/drivers/mmc/host/sdhci.c --- linux-4.4.115/drivers/mmc/host/sdhci.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/mmc/host/sdhci.c 2019-10-29 09:26:24.077207425 +0100 @@ -30,8 +30,12 @@ #include #include #include +#include + +#include #include "sdhci.h" +#include "cmdq_hci.h" #define DRIVER_NAME "sdhci" @@ -45,6 +49,9 @@ #define MAX_TUNING_LOOP 40 +#define SDHCI_DBG_DUMP_RS_INTERVAL (10 * HZ) +#define SDHCI_DBG_DUMP_RS_BURST 2 + static unsigned int debug_quirks = 0; static unsigned int debug_quirks2; @@ -52,10 +59,13 @@ static void sdhci_finish_command(struct sdhci_host *); static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode); +static int sdhci_enhanced_strobe(struct mmc_host *mmc); static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable); static int sdhci_pre_dma_transfer(struct sdhci_host *host, struct mmc_data *data); static int sdhci_do_get_cd(struct sdhci_host *host); +static bool sdhci_check_state(struct sdhci_host *); +static void sdhci_enable_sdio_irq_nolock(struct sdhci_host *host, int enable); #ifdef CONFIG_PM static int sdhci_runtime_pm_get(struct sdhci_host *host); @@ -79,60 +89,102 @@ } #endif +static void sdhci_dump_state(struct sdhci_host *host) +{ + struct mmc_host *mmc = host->mmc; + + #ifdef CONFIG_MMC_CLKGATE + pr_info("%s: clk: %d clk-gated: %d claimer: %s pwr: %d host->irq = %d\n", + mmc_hostname(mmc), host->clock, mmc->clk_gated, + mmc->claimer->comm, host->pwr, + (host->flags & SDHCI_HOST_IRQ_STATUS)); + #else + pr_info("%s: clk: %d claimer: %s pwr: %d\n", + mmc_hostname(mmc), host->clock, + mmc->claimer->comm, host->pwr); + #endif + pr_info("%s: rpmstatus[pltfm](runtime-suspend:usage_count:disable_depth)(%d:%d:%d)\n", + mmc_hostname(mmc), mmc->parent->power.runtime_status, + atomic_read(&mmc->parent->power.usage_count), + mmc->parent->power.disable_depth); +} + static void sdhci_dumpregs(struct sdhci_host *host) { - pr_debug(DRIVER_NAME ": =========== REGISTER DUMP (%s)===========\n", + MMC_TRACE(host->mmc, + "%s: 0x04=0x%08x 0x06=0x%08x 0x0E=0x%08x 0x30=0x%08x 0x34=0x%08x 0x38=0x%08x\n", + __func__, + sdhci_readw(host, SDHCI_BLOCK_SIZE), + sdhci_readw(host, SDHCI_BLOCK_COUNT), + sdhci_readw(host, SDHCI_COMMAND), + sdhci_readl(host, SDHCI_INT_STATUS), + sdhci_readl(host, SDHCI_INT_ENABLE), + sdhci_readl(host, SDHCI_SIGNAL_ENABLE)); + mmc_stop_tracing(host->mmc); + + pr_info(DRIVER_NAME ": =========== REGISTER DUMP (%s)===========\n", mmc_hostname(host->mmc)); - pr_debug(DRIVER_NAME ": Sys addr: 0x%08x | Version: 0x%08x\n", + pr_info(DRIVER_NAME ": Sys addr: 0x%08x | Version: 0x%08x\n", sdhci_readl(host, SDHCI_DMA_ADDRESS), sdhci_readw(host, SDHCI_HOST_VERSION)); - pr_debug(DRIVER_NAME ": Blk size: 0x%08x | Blk cnt: 0x%08x\n", + pr_info(DRIVER_NAME ": Blk size: 0x%08x | Blk cnt: 0x%08x\n", sdhci_readw(host, SDHCI_BLOCK_SIZE), sdhci_readw(host, SDHCI_BLOCK_COUNT)); - pr_debug(DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n", + pr_info(DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n", sdhci_readl(host, SDHCI_ARGUMENT), sdhci_readw(host, SDHCI_TRANSFER_MODE)); - pr_debug(DRIVER_NAME ": Present: 0x%08x | Host ctl: 0x%08x\n", + pr_info(DRIVER_NAME ": Present: 0x%08x | Host ctl: 0x%08x\n", sdhci_readl(host, SDHCI_PRESENT_STATE), sdhci_readb(host, SDHCI_HOST_CONTROL)); - pr_debug(DRIVER_NAME ": Power: 0x%08x | Blk gap: 0x%08x\n", + pr_info(DRIVER_NAME ": Power: 0x%08x | Blk gap: 0x%08x\n", sdhci_readb(host, SDHCI_POWER_CONTROL), sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL)); - pr_debug(DRIVER_NAME ": Wake-up: 0x%08x | Clock: 0x%08x\n", + pr_info(DRIVER_NAME ": Wake-up: 0x%08x | Clock: 0x%08x\n", sdhci_readb(host, SDHCI_WAKE_UP_CONTROL), sdhci_readw(host, SDHCI_CLOCK_CONTROL)); - pr_debug(DRIVER_NAME ": Timeout: 0x%08x | Int stat: 0x%08x\n", + pr_info(DRIVER_NAME ": Timeout: 0x%08x | Int stat: 0x%08x\n", sdhci_readb(host, SDHCI_TIMEOUT_CONTROL), sdhci_readl(host, SDHCI_INT_STATUS)); - pr_debug(DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n", + pr_info(DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n", sdhci_readl(host, SDHCI_INT_ENABLE), sdhci_readl(host, SDHCI_SIGNAL_ENABLE)); - pr_debug(DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n", - sdhci_readw(host, SDHCI_ACMD12_ERR), + pr_info(DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n", + host->auto_cmd_err_sts, sdhci_readw(host, SDHCI_SLOT_INT_STATUS)); - pr_debug(DRIVER_NAME ": Caps: 0x%08x | Caps_1: 0x%08x\n", + pr_info(DRIVER_NAME ": Caps: 0x%08x | Caps_1: 0x%08x\n", sdhci_readl(host, SDHCI_CAPABILITIES), sdhci_readl(host, SDHCI_CAPABILITIES_1)); - pr_debug(DRIVER_NAME ": Cmd: 0x%08x | Max curr: 0x%08x\n", + pr_info(DRIVER_NAME ": Cmd: 0x%08x | Max curr: 0x%08x\n", sdhci_readw(host, SDHCI_COMMAND), sdhci_readl(host, SDHCI_MAX_CURRENT)); - pr_debug(DRIVER_NAME ": Host ctl2: 0x%08x\n", + pr_info(DRIVER_NAME ": Resp 1: 0x%08x | Resp 0: 0x%08x\n", + sdhci_readl(host, SDHCI_RESPONSE + 0x4), + sdhci_readl(host, SDHCI_RESPONSE)); + pr_info(DRIVER_NAME ": Resp 3: 0x%08x | Resp 2: 0x%08x\n", + sdhci_readl(host, SDHCI_RESPONSE + 0xC), + sdhci_readl(host, SDHCI_RESPONSE + 0x8)); + pr_info(DRIVER_NAME ": Host ctl2: 0x%08x\n", sdhci_readw(host, SDHCI_HOST_CONTROL2)); if (host->flags & SDHCI_USE_ADMA) { if (host->flags & SDHCI_USE_64_BIT_DMA) - pr_debug(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x%08x\n", + pr_info(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x%08x\n", readl(host->ioaddr + SDHCI_ADMA_ERROR), readl(host->ioaddr + SDHCI_ADMA_ADDRESS_HI), readl(host->ioaddr + SDHCI_ADMA_ADDRESS)); else - pr_debug(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n", + pr_info(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n", readl(host->ioaddr + SDHCI_ADMA_ERROR), readl(host->ioaddr + SDHCI_ADMA_ADDRESS)); } - pr_debug(DRIVER_NAME ": ===========================================\n"); + host->mmc->err_occurred = true; + + if (host->ops->dump_vendor_regs) + host->ops->dump_vendor_regs(host); + sdhci_dump_state(host); + pr_info(DRIVER_NAME ": ===========================================\n"); } /*****************************************************************************\ @@ -177,6 +229,7 @@ { unsigned long timeout; +retry_reset: sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET); if (mask & SDHCI_RESET_ALL) { @@ -187,19 +240,60 @@ } /* Wait max 100 ms */ - timeout = 100; + timeout = 100000; + + if (host->ops->check_power_status && host->pwr && + (mask & SDHCI_RESET_ALL)) + host->ops->check_power_status(host, REQ_BUS_OFF); + + /* clear pending normal/error interrupt status */ + sdhci_writel(host, sdhci_readl(host, SDHCI_INT_STATUS), + SDHCI_INT_STATUS); /* hw clears the bit when it's done */ while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) { if (timeout == 0) { pr_err("%s: Reset 0x%x never completed.\n", mmc_hostname(host->mmc), (int)mask); + MMC_TRACE(host->mmc, "%s: Reset 0x%x never completed\n", + __func__, (int)mask); + if ((host->quirks2 & SDHCI_QUIRK2_USE_RESET_WORKAROUND) + && host->ops->reset_workaround) { + if (!host->reset_wa_applied) { + /* + * apply the workaround and issue + * reset again. + */ + host->ops->reset_workaround(host, 1); + host->reset_wa_applied = 1; + host->reset_wa_cnt++; + goto retry_reset; + } else { + pr_err("%s: Reset 0x%x failed with workaround\n", + mmc_hostname(host->mmc), + (int)mask); + /* clear the workaround */ + host->ops->reset_workaround(host, 0); + host->reset_wa_applied = 0; + } + } + sdhci_dumpregs(host); return; } timeout--; - mdelay(1); + udelay(1); } + + if ((host->quirks2 & SDHCI_QUIRK2_USE_RESET_WORKAROUND) && + host->ops->reset_workaround && host->reset_wa_applied) { + pr_info("%s: Reset 0x%x successful with workaround\n", + mmc_hostname(host->mmc), (int)mask); + /* clear the workaround */ + host->ops->reset_workaround(host, 0); + host->reset_wa_applied = 0; + } + } EXPORT_SYMBOL_GPL(sdhci_reset); @@ -221,6 +315,8 @@ /* Resetting the controller clears many */ host->preset_enabled = false; } + if (host->is_crypto_en) + host->crypto_reset_reqd = true; } static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios); @@ -236,7 +332,7 @@ SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX | SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT | SDHCI_INT_DATA_END | - SDHCI_INT_RESPONSE; + SDHCI_INT_RESPONSE | SDHCI_INT_AUTO_CMD_ERR; sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); @@ -279,9 +375,12 @@ struct sdhci_host *host = container_of(led, struct sdhci_host, led); unsigned long flags; + if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) + return; + spin_lock_irqsave(&host->lock, flags); - if (host->runtime_suspended) + if (host->runtime_suspended || sdhci_check_state(host)) goto out; if (brightness == LED_OFF) @@ -598,7 +697,10 @@ void *align; char *buffer; unsigned long flags; - bool has_unaligned; + bool has_unaligned = false; + u32 command = SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND)); + + trace_mmc_adma_table_post(command, data->sg_len); if (data->flags & MMC_DATA_READ) direction = DMA_FROM_DEVICE; @@ -648,6 +750,7 @@ u8 count; struct mmc_data *data = cmd->data; unsigned target_timeout, current_timeout; + u32 curr_clk = 0; /* In KHz */ /* * If the host controller provides us with an incorrect timeout @@ -693,7 +796,14 @@ * (1) / (2) > 2^6 */ count = 0; + if (host->quirks2 & SDHCI_QUIRK2_ALWAYS_USE_BASE_CLOCK) { + curr_clk = host->clock / 1000; + if (host->quirks2 & SDHCI_QUIRK2_DIVIDE_TOUT_BY_4) + curr_clk /= 4; + current_timeout = (1 << 13) * 1000 / curr_clk; + } else { current_timeout = (1 << 13) * 1000 / host->timeout_clk; + } while (current_timeout < target_timeout) { count++; current_timeout <<= 1; @@ -701,11 +811,13 @@ break; } + if (!(host->quirks2 & SDHCI_QUIRK2_USE_RESERVED_MAX_TIMEOUT)) { if (count >= 0xF) { DBG("%s: Too large timeout 0x%x requested for CMD%d!\n", mmc_hostname(host->mmc), count, cmd->opcode); count = 0xE; } + } return count; } @@ -736,6 +848,17 @@ } } +static void sdhci_set_blk_size_reg(struct sdhci_host *host, unsigned int blksz, + unsigned int sdma_boundary) +{ + if (host->flags & SDHCI_USE_ADMA) + sdhci_writew(host, SDHCI_MAKE_BLKSZ(0, blksz), + SDHCI_BLOCK_SIZE); + else + sdhci_writew(host, SDHCI_MAKE_BLKSZ(sdma_boundary, blksz), + SDHCI_BLOCK_SIZE); +} + static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd) { u8 ctrl; @@ -751,7 +874,7 @@ return; /* Sanity checks */ - BUG_ON(data->blksz * data->blocks > 524288); + BUG_ON(data->blksz * data->blocks > host->mmc->max_req_size); BUG_ON(data->blksz > host->mmc->max_blk_size); BUG_ON(data->blocks > 65535); @@ -762,6 +885,10 @@ if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) host->flags |= SDHCI_REQ_USE_DMA; + if ((host->quirks2 & SDHCI_QUIRK2_USE_PIO_FOR_EMMC_TUNING) && + cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200) + host->flags &= ~SDHCI_REQ_USE_DMA; + /* * FIXME: This doesn't account for merging when mapping the * scatterlist. @@ -828,6 +955,7 @@ if (host->flags & SDHCI_REQ_USE_DMA) { if (host->flags & SDHCI_USE_ADMA) { + trace_mmc_adma_table_pre(cmd->opcode, data->sg_len); ret = sdhci_adma_table_pre(host, data); if (ret) { /* @@ -898,9 +1026,13 @@ sdhci_set_transfer_irqs(host); /* Set the DMA boundary value and block size */ - sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG, - data->blksz), SDHCI_BLOCK_SIZE); + sdhci_set_blk_size_reg(host, data->blksz, SDHCI_DEFAULT_BOUNDARY_ARG); sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT); + MMC_TRACE(host->mmc, + "%s: 0x28=0x%08x 0x3E=0x%08x 0x06=0x%08x\n", __func__, + sdhci_readb(host, SDHCI_HOST_CONTROL), + sdhci_readw(host, SDHCI_HOST_CONTROL2), + sdhci_readw(host, SDHCI_BLOCK_COUNT)); } static void sdhci_set_transfer_mode(struct sdhci_host *host, @@ -942,12 +1074,26 @@ } } - if (data->flags & MMC_DATA_READ) + if (data->flags & MMC_DATA_READ) { mode |= SDHCI_TRNS_READ; + if (host->ops->toggle_cdr) { + if ((cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200) || + (cmd->opcode == MMC_SEND_TUNING_BLOCK_HS400) || + (cmd->opcode == MMC_SEND_TUNING_BLOCK)) + host->ops->toggle_cdr(host, false); + else + host->ops->toggle_cdr(host, true); + } + } + if (host->ops->toggle_cdr && (data->flags & MMC_DATA_WRITE)) + host->ops->toggle_cdr(host, false); if (host->flags & SDHCI_REQ_USE_DMA) mode |= SDHCI_TRNS_DMA; sdhci_writew(host, mode, SDHCI_TRANSFER_MODE); + MMC_TRACE(host->mmc, "%s: 0x00=0x%08x 0x0C=0x%08x\n", __func__, + sdhci_readw(host, SDHCI_ARGUMENT2), + sdhci_readw(host, SDHCI_TRANSFER_MODE)); } static void sdhci_finish_data(struct sdhci_host *host) @@ -959,6 +1105,8 @@ data = host->data; host->data = NULL; + MMC_TRACE(host->mmc, "%s: 0x24=0x%08x\n", __func__, + sdhci_readl(host, SDHCI_PRESENT_STATE)); if (host->flags & SDHCI_REQ_USE_DMA) { if (host->flags & SDHCI_USE_ADMA) sdhci_adma_table_post(host, data); @@ -1017,7 +1165,7 @@ WARN_ON(host->cmd); /* Wait max 10 ms */ - timeout = 10; + timeout = 10000; mask = SDHCI_CMD_INHIBIT; if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY)) @@ -1032,13 +1180,16 @@ if (timeout == 0) { pr_err("%s: Controller never released " "inhibit bit(s).\n", mmc_hostname(host->mmc)); + MMC_TRACE(host->mmc, + "%s :Controller never released inhibit bit(s)\n", + __func__); sdhci_dumpregs(host); cmd->error = -EIO; tasklet_schedule(&host->finish_tasklet); return; } timeout--; - mdelay(1); + udelay(1); } timeout = jiffies; @@ -1084,7 +1235,15 @@ cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200) flags |= SDHCI_CMD_DATA; + if (cmd->data) + host->data_start_time = ktime_get(); + trace_mmc_cmd_rw_start(cmd->opcode, cmd->arg, cmd->flags); sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND); + MMC_TRACE(host->mmc, + "%s: updated 0x8=0x%08x 0xC=0x%08x 0xE=0x%08x\n", __func__, + sdhci_readl(host, SDHCI_ARGUMENT), + sdhci_readw(host, SDHCI_TRANSFER_MODE), + sdhci_readw(host, SDHCI_COMMAND)); } EXPORT_SYMBOL_GPL(sdhci_send_command); @@ -1105,15 +1264,20 @@ sdhci_readb(host, SDHCI_RESPONSE + (3-i)*4-1); } + MMC_TRACE(host->mmc, + "%s: resp 0: 0x%08x resp 1: 0x%08x resp 2: 0x%08x resp 3: 0x%08x\n", + __func__, host->cmd->resp[0], host->cmd->resp[1], + host->cmd->resp[2], host->cmd->resp[3]); } else { host->cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE); + MMC_TRACE(host->mmc, "%s: resp 0: 0x%08x\n", + __func__, host->cmd->resp[0]); } } - host->cmd->error = 0; - /* Finished CMD23, now send actual command. */ if (host->cmd == host->mrq->sbc) { + host->cmd->error = 0; host->cmd = NULL; sdhci_send_command(host, host->mrq->cmd); } else { @@ -1173,6 +1337,7 @@ host->mmc->actual_clock = 0; + if (host->clock) sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL); if (host->quirks2 & SDHCI_QUIRK2_NEED_DELAY_AFTER_INT_CLK_RST) mdelay(1); @@ -1257,6 +1422,10 @@ clock_set: if (real_div) host->mmc->actual_clock = (host->max_clk * clk_mul) / real_div; + + if (host->quirks2 & SDHCI_QUIRK2_ALWAYS_USE_BASE_CLOCK) + div = 0; + clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT; clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN) << SDHCI_DIVIDER_HI_SHIFT; @@ -1264,19 +1433,19 @@ sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); /* Wait max 20 ms */ - timeout = 20; + timeout = 20000; while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL)) & SDHCI_CLOCK_INT_STABLE)) { if (timeout == 0) { pr_err("%s: Internal clock never " "stabilised.\n", mmc_hostname(host->mmc)); + MMC_TRACE(host->mmc, + "%s: Internal clock never stabilised.\n", __func__); sdhci_dumpregs(host); return; } timeout--; - spin_unlock_irq(&host->lock); - usleep_range(900, 1100); - spin_lock_irq(&host->lock); + udelay(1); } clk |= SDHCI_CLOCK_CARD_EN; @@ -1330,6 +1499,8 @@ if (pwr == 0) { sdhci_writeb(host, 0, SDHCI_POWER_CONTROL); + if (host->ops->check_power_status) + host->ops->check_power_status(host, REQ_BUS_OFF); if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON) sdhci_runtime_pm_bus_off(host); vdd = 0; @@ -1338,20 +1509,27 @@ * Spec says that we should clear the power reg before setting * a new value. Some controllers don't seem to like this though. */ - if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE)) + if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE)) { sdhci_writeb(host, 0, SDHCI_POWER_CONTROL); - + if (host->ops->check_power_status) + host->ops->check_power_status(host, REQ_BUS_OFF); + } /* * At least the Marvell CaFe chip gets confused if we set the * voltage and set turn on power at the same time, so set the * voltage first. */ - if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER) + if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER) { sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL); + if (host->ops->check_power_status) + host->ops->check_power_status(host, REQ_BUS_ON); + } pwr |= SDHCI_POWER_ON; sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL); + if (host->ops->check_power_status) + host->ops->check_power_status(host, REQ_BUS_ON); if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON) sdhci_runtime_pm_bus_on(host); @@ -1371,6 +1549,148 @@ * * \*****************************************************************************/ +static int sdhci_enable(struct mmc_host *mmc) +{ + struct sdhci_host *host = mmc_priv(mmc); + + if (host->ops->platform_bus_voting) + host->ops->platform_bus_voting(host, 1); + + return 0; +} + +static int sdhci_disable(struct mmc_host *mmc) +{ + struct sdhci_host *host = mmc_priv(mmc); + + if (host->ops->platform_bus_voting) + host->ops->platform_bus_voting(host, 0); + + return 0; +} + +static void sdhci_notify_halt(struct mmc_host *mmc, bool halt) +{ + struct sdhci_host *host = mmc_priv(mmc); + + pr_debug("%s: halt notification was sent, halt=%d\n", + mmc_hostname(mmc), halt); + if (host->flags & SDHCI_USE_64_BIT_DMA) { + if (halt) + host->desc_sz = 16; + else + host->desc_sz = SDHCI_ADMA2_64_DESC_SZ; + } +} + +static inline void sdhci_update_power_policy(struct sdhci_host *host, + enum sdhci_power_policy policy) +{ + host->power_policy = policy; +} + +static int sdhci_notify_load(struct mmc_host *mmc, enum mmc_load state) +{ + int err = 0; + struct sdhci_host *host = mmc_priv(mmc); + + switch (state) { + case MMC_LOAD_HIGH: + sdhci_update_power_policy(host, SDHCI_PERFORMANCE_MODE); + break; + case MMC_LOAD_LOW: + sdhci_update_power_policy(host, SDHCI_POWER_SAVE_MODE); + break; + default: + err = -EINVAL; + break; + } + + if (host->ops->notify_load) + err = host->ops->notify_load(host, state); + + return err; +} + +static bool sdhci_check_state(struct sdhci_host *host) +{ + if (!host->clock || !host->pwr) + return true; + else + return false; +} + +static bool sdhci_check_auto_tuning(struct sdhci_host *host, + struct mmc_command *cmd) +{ + if (((cmd->opcode != MMC_READ_SINGLE_BLOCK) && + (cmd->opcode != MMC_READ_MULTIPLE_BLOCK) && + (cmd->opcode != SD_IO_RW_EXTENDED)) || (host->clock < 100000000)) + return false; + else if (host->mmc->ios.timing == MMC_TIMING_MMC_HS200 || + host->mmc->ios.timing == MMC_TIMING_UHS_SDR104) + return true; + else + return false; +} + +static int sdhci_get_tuning_cmd(struct sdhci_host *host) +{ + if (!host->mmc || !host->mmc->card) + return 0; + /* + * If we are here, all conditions have already been true + * and the card can either be an eMMC or SD/SDIO + */ + if (mmc_card_mmc(host->mmc->card)) + return MMC_SEND_TUNING_BLOCK_HS200; + else + return MMC_SEND_TUNING_BLOCK; +} + +static int sdhci_crypto_cfg(struct sdhci_host *host, struct mmc_request *mrq, + u32 slot) +{ + int err = 0; + + if (host->crypto_reset_reqd && host->ops->crypto_engine_reset) { + err = host->ops->crypto_engine_reset(host); + if (err) { + pr_err("%s: crypto reset failed\n", + mmc_hostname(host->mmc)); + goto out; + } + host->crypto_reset_reqd = false; + } + + if (host->ops->crypto_engine_cfg) { + err = host->ops->crypto_engine_cfg(host, mrq, slot); + if (err) { + pr_err("%s: failed to configure crypto\n", + mmc_hostname(host->mmc)); + goto out; + } + } +out: + return err; +} + +static int sdhci_crypto_cfg_end(struct sdhci_host *host, + struct mmc_request *mrq) +{ + int err = 0; + + if (host->ops->crypto_engine_cfg_end) { + err = host->ops->crypto_engine_cfg_end(host, mrq); + if (err) { + pr_err("%s: failed to configure crypto\n", + mmc_hostname(host->mmc)); + return err; + } + } + return 0; +} + static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq) { struct sdhci_host *host; @@ -1380,15 +1700,41 @@ host = mmc_priv(mmc); sdhci_runtime_pm_get(host); + if (sdhci_check_state(host)) { + sdhci_dump_state(host); + pr_err("%s: sdhci in bad state\n", + mmc_hostname(host->mmc)); + mrq->cmd->error = -EIO; + if (mrq->data) + mrq->data->error = -EIO; + mmc_request_done(host->mmc, mrq); + sdhci_runtime_pm_put(host); + return; + } - /* Firstly check card presence */ - present = mmc->ops->get_cd(mmc); + /* + * Firstly check card presence from cd-gpio. The return could + * be one of the following possibilities: + * negative: cd-gpio is not available + * zero: cd-gpio is used, and card is removed + * one: cd-gpio is used, and card is present + */ + present = sdhci_do_get_cd(host); + if (present < 0) { + /* If polling, assume that the card is always present. */ + if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) + present = 1; + else + present = sdhci_readl(host, SDHCI_PRESENT_STATE) & + SDHCI_CARD_PRESENT; + } spin_lock_irqsave(&host->lock, flags); WARN_ON(host->mrq != NULL); #ifndef SDHCI_USE_LEDS_CLASS + if (!(host->quirks2 & SDHCI_QUIRK2_BROKEN_LED_CONTROL)) sdhci_activate_led(host); #endif @@ -1409,6 +1755,22 @@ host->mrq->cmd->error = -ENOMEDIUM; tasklet_schedule(&host->finish_tasklet); } else { + if (host->ops->config_auto_tuning_cmd) { + if (sdhci_check_auto_tuning(host, mrq->cmd)) + host->ops->config_auto_tuning_cmd(host, true, + sdhci_get_tuning_cmd(host)); + else + host->ops->config_auto_tuning_cmd(host, false, + sdhci_get_tuning_cmd(host)); + } + + if (host->is_crypto_en) { + spin_unlock_irqrestore(&host->lock, flags); + if (sdhci_crypto_cfg(host, mrq, 0)) + goto end_req; + spin_lock_irqsave(&host->lock, flags); + } + if (mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23)) sdhci_send_command(host, mrq->sbc); else @@ -1417,6 +1779,16 @@ mmiowb(); spin_unlock_irqrestore(&host->lock, flags); + return; +end_req: + mrq->cmd->error = -EIO; + if (mrq->data) + mrq->data->error = -EIO; + host->mrq = NULL; + MMC_TRACE(host->mmc, "Request failed due to ice config\n"); + sdhci_dumpregs(host); + mmc_request_done(host->mmc, mrq); + sdhci_runtime_pm_put(host); } void sdhci_set_bus_width(struct sdhci_host *host, int width) @@ -1465,38 +1837,50 @@ } EXPORT_SYMBOL_GPL(sdhci_set_uhs_signaling); +void sdhci_cfg_irq(struct sdhci_host *host, bool enable, bool sync) +{ + if (enable && !(host->flags & SDHCI_HOST_IRQ_STATUS)) { + enable_irq(host->irq); + host->flags |= SDHCI_HOST_IRQ_STATUS; + } else if (!enable && (host->flags & SDHCI_HOST_IRQ_STATUS)) { + if (sync) + disable_irq(host->irq); + else + disable_irq_nosync(host->irq); + host->flags &= ~SDHCI_HOST_IRQ_STATUS; + } +} +EXPORT_SYMBOL(sdhci_cfg_irq); + static void sdhci_do_set_ios(struct sdhci_host *host, struct mmc_ios *ios) { unsigned long flags; u8 ctrl; struct mmc_host *mmc = host->mmc; - - spin_lock_irqsave(&host->lock, flags); + int ret; if (host->flags & SDHCI_DEVICE_DEAD) { - spin_unlock_irqrestore(&host->lock, flags); if (!IS_ERR(mmc->supply.vmmc) && ios->power_mode == MMC_POWER_OFF) mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); return; } - /* - * Reset the chip on each power off. - * Should clear out any weird states. - */ - if (ios->power_mode == MMC_POWER_OFF) { - sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE); - sdhci_reinit(host); - } - if (host->version >= SDHCI_SPEC_300 && (ios->power_mode == MMC_POWER_UP) && !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN)) sdhci_enable_preset_value(host, false); - if (!ios->clock || ios->clock != host->clock) { + spin_lock_irqsave(&host->lock, flags); + if (host->mmc && host->mmc->card && + mmc_card_sdio(host->mmc->card)) + sdhci_cfg_irq(host, false, false); + + if (ios->clock && + ((ios->clock != host->clock) || (ios->timing != host->timing))) { + spin_unlock_irqrestore(&host->lock, flags); host->ops->set_clock(host, ios->clock); + spin_lock_irqsave(&host->lock, flags); host->clock = ios->clock; if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK && @@ -1511,8 +1895,45 @@ host->mmc->max_busy_timeout /= host->timeout_clk; } } + if (ios->clock && host->sdio_irq_async_status) + sdhci_enable_sdio_irq_nolock(host, false); + spin_unlock_irqrestore(&host->lock, flags); + /* + * The controller clocks may be off during power-up and we may end up + * enabling card clock before giving power to the card. Hence, during + * MMC_POWER_UP enable the controller clock and turn-on the regulators. + * The mmc_power_up would provide the necessary delay before turning on + * the clocks to the card. + */ + if (ios->power_mode & MMC_POWER_UP) { + if (host->ops->enable_controller_clock) { + ret = host->ops->enable_controller_clock(host); + if (ret) { + pr_err("%s: enabling controller clock: failed: %d\n", + mmc_hostname(host->mmc), ret); + } else { sdhci_set_power(host, ios->power_mode, ios->vdd); + } + } + } + + spin_lock_irqsave(&host->lock, flags); + if (!host->clock) { + if (host->mmc && host->mmc->card && + mmc_card_sdio(host->mmc->card)) + sdhci_cfg_irq(host, true, false); + spin_unlock_irqrestore(&host->lock, flags); + return; + } + spin_unlock_irqrestore(&host->lock, flags); + + if (!host->ops->enable_controller_clock && (ios->power_mode & + (MMC_POWER_UP | + MMC_POWER_ON))) + sdhci_set_power(host, ios->power_mode, ios->vdd); + + spin_lock_irqsave(&host->lock, flags); if (host->ops->platform_send_init_74_clocks) host->ops->platform_send_init_74_clocks(host, ios->power_mode); @@ -1580,7 +2001,11 @@ sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); /* Re-enable SD Clock */ + if (ios->clock) { + spin_unlock_irqrestore(&host->lock, flags); host->ops->set_clock(host, host->clock); + spin_lock_irqsave(&host->lock, flags); + } } /* Reset SD Clock Enable */ @@ -1607,10 +2032,15 @@ } /* Re-enable SD Clock */ + if (ios->clock) { + spin_unlock_irqrestore(&host->lock, flags); host->ops->set_clock(host, host->clock); + spin_lock_irqsave(&host->lock, flags); + } } else sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); + spin_unlock_irqrestore(&host->lock, flags); /* * Some (ENE) controllers go apeshit on some ios operation, * signalling timeout and CRC errors even on CMD0. Resetting @@ -1619,8 +2049,25 @@ if (host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS) sdhci_do_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA); - mmiowb(); + /* + * Reset the chip on each power off. + * Should clear out any weird states. + */ + if (ios->power_mode == MMC_POWER_OFF) { + sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE); + sdhci_reinit(host); + sdhci_set_power(host, ios->power_mode, ios->vdd); + } + if (!ios->clock) + host->ops->set_clock(host, ios->clock); + + spin_lock_irqsave(&host->lock, flags); + if (host->mmc && host->mmc->card && + mmc_card_sdio(host->mmc->card)) + sdhci_cfg_irq(host, true, false); spin_unlock_irqrestore(&host->lock, flags); + + mmiowb(); } static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) @@ -1732,7 +2179,20 @@ static void sdhci_enable_sdio_irq_nolock(struct sdhci_host *host, int enable) { - if (!(host->flags & SDHCI_DEVICE_DEAD)) { + u16 ctrl = 0; + + if (host->flags & SDHCI_DEVICE_DEAD) + return; + + if (mmc_card_and_host_support_async_int(host->mmc)) { + ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); + if (enable) + ctrl |= SDHCI_CTRL_ASYNC_INT_ENABLE; + else + ctrl &= ~SDHCI_CTRL_ASYNC_INT_ENABLE; + sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); + } + if (enable) host->ier |= SDHCI_INT_CARD_INT; else @@ -1742,7 +2202,6 @@ sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); mmiowb(); } -} static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable) { @@ -1784,6 +2243,8 @@ /* Set 1.8V Signal Enable in the Host Control2 register to 0 */ ctrl &= ~SDHCI_CTRL_VDD_180; sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); + if (host->ops->check_power_status) + host->ops->check_power_status(host, REQ_IO_HIGH); if (!IS_ERR(mmc->supply.vqmmc)) { ret = regulator_set_voltage(mmc->supply.vqmmc, 2700000, @@ -1823,6 +2284,8 @@ */ ctrl |= SDHCI_CTRL_VDD_180; sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); + if (host->ops->check_power_status) + host->ops->check_power_status(host, REQ_IO_LOW); /* Some controller need to do more when switching */ if (host->ops->voltage_switch) @@ -1893,6 +2356,19 @@ return 0; } +static int sdhci_enhanced_strobe(struct mmc_host *mmc) +{ + struct sdhci_host *host = mmc_priv(mmc); + int err = 0; + + sdhci_runtime_pm_get(host); + if (host->ops->enhanced_strobe) + err = host->ops->enhanced_strobe(host); + sdhci_runtime_pm_put(host); + + return err; +} + static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode) { struct sdhci_host *host = mmc_priv(mmc); @@ -1922,9 +2398,10 @@ switch (host->timing) { /* HS400 tuning is done in HS200 mode */ case MMC_TIMING_MMC_HS400: + if (!(mmc->caps2 & MMC_CAP2_HS400_POST_TUNING)) { err = -EINVAL; goto out_unlock; - + } case MMC_TIMING_MMC_HS200: /* * Periodic re-tuning for HS400 is not expected to be needed, so @@ -1950,7 +2427,13 @@ if (host->ops->platform_execute_tuning) { spin_unlock_irqrestore(&host->lock, flags); + /* + * Make sure re-tuning won't get triggered for the CRC errors + * occurred while executing tuning + */ + mmc_retune_disable(mmc); err = host->ops->platform_execute_tuning(host, opcode); + mmc_retune_enable(mmc); sdhci_runtime_pm_put(host); return err; } @@ -2002,14 +2485,11 @@ */ if (cmd.opcode == MMC_SEND_TUNING_BLOCK_HS200) { if (mmc->ios.bus_width == MMC_BUS_WIDTH_8) - sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 128), - SDHCI_BLOCK_SIZE); + sdhci_set_blk_size_reg(host, 128, 7); else if (mmc->ios.bus_width == MMC_BUS_WIDTH_4) - sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64), - SDHCI_BLOCK_SIZE); + sdhci_set_blk_size_reg(host, 64, 7); } else { - sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64), - SDHCI_BLOCK_SIZE); + sdhci_set_blk_size_reg(host, 64, 7); } /* @@ -2132,6 +2612,9 @@ if (host->version < SDHCI_SPEC_300) return; + if (host->quirks2 & SDHCI_QUIRK2_BROKEN_PRESET_VALUE) + return; + /* * We only enable or disable Preset Value if they are not already * enabled or disabled respectively. Otherwise, we bail out. @@ -2169,6 +2652,8 @@ DMA_TO_DEVICE : DMA_FROM_DEVICE); data->host_cookie = COOKIE_UNMAPPED; } + if (host->ops->post_req) + host->ops->post_req(host, mrq); } static int sdhci_pre_dma_transfer(struct sdhci_host *host, @@ -2205,6 +2690,9 @@ if (host->flags & SDHCI_REQ_USE_DMA) sdhci_pre_dma_transfer(host, mrq->data); + + if (host->ops->pre_req) + host->ops->pre_req(host, mrq); } static void sdhci_card_event(struct mmc_host *mmc) @@ -2238,7 +2726,29 @@ spin_unlock_irqrestore(&host->lock, flags); } +static int sdhci_late_init(struct mmc_host *mmc) +{ + struct sdhci_host *host = mmc_priv(mmc); + + if (host->ops->init) + host->ops->init(host); + + return 0; +} + +static void sdhci_force_err_irq(struct mmc_host *mmc, u64 errmask) +{ + struct sdhci_host *host = mmc_priv(mmc); + u16 mask = errmask & 0xFFFF; + + pr_err("%s: Force raise error mask:0x%04x\n", __func__, mask); + sdhci_runtime_pm_get(host); + sdhci_writew(host, mask, SDHCI_SET_INT_ERROR); + sdhci_runtime_pm_put(host); +} + static const struct mmc_host_ops sdhci_ops = { + .init = sdhci_late_init, .request = sdhci_request, .post_req = sdhci_post_req, .pre_req = sdhci_pre_req, @@ -2250,9 +2760,15 @@ .start_signal_voltage_switch = sdhci_start_signal_voltage_switch, .prepare_hs400_tuning = sdhci_prepare_hs400_tuning, .execute_tuning = sdhci_execute_tuning, + .enhanced_strobe = sdhci_enhanced_strobe, .select_drive_strength = sdhci_select_drive_strength, .card_event = sdhci_card_event, .card_busy = sdhci_card_busy, + .enable = sdhci_enable, + .disable = sdhci_disable, + .notify_load = sdhci_notify_load, + .notify_halt = sdhci_notify_halt, + .force_err_irq = sdhci_force_err_irq, }; /*****************************************************************************\ @@ -2304,19 +2820,25 @@ controllers do not like that. */ sdhci_do_reset(host, SDHCI_RESET_CMD); sdhci_do_reset(host, SDHCI_RESET_DATA); + } else { + if (host->quirks2 & SDHCI_QUIRK2_RDWR_TX_ACTIVE_EOT) + sdhci_reset(host, SDHCI_RESET_DATA); } host->mrq = NULL; host->cmd = NULL; host->data = NULL; + host->auto_cmd_err_sts = 0; #ifndef SDHCI_USE_LEDS_CLASS + if (!(host->quirks2 & SDHCI_QUIRK2_BROKEN_LED_CONTROL)) sdhci_deactivate_led(host); #endif mmiowb(); spin_unlock_irqrestore(&host->lock, flags); + sdhci_crypto_cfg_end(host, mrq); mmc_request_done(host->mmc, mrq); sdhci_runtime_pm_put(host); } @@ -2333,9 +2855,15 @@ if (host->mrq) { pr_err("%s: Timeout waiting for hardware " "interrupt.\n", mmc_hostname(host->mmc)); + MMC_TRACE(host->mmc, "Timeout waiting for h/w interrupt\n"); sdhci_dumpregs(host); if (host->data) { + pr_info("%s: bytes to transfer: %d transferred: %d\n", + mmc_hostname(host->mmc), + (host->data->blksz * host->data->blocks), + (sdhci_readw(host, SDHCI_BLOCK_SIZE) & 0xFFF) * + sdhci_readw(host, SDHCI_BLOCK_COUNT)); host->data->error = -ETIMEDOUT; sdhci_finish_data(host); } else { @@ -2360,23 +2888,63 @@ static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask, u32 *mask) { + u16 auto_cmd_status; BUG_ON(intmask == 0); if (!host->cmd) { pr_err("%s: Got command interrupt 0x%08x even " "though no command operation was in progress.\n", mmc_hostname(host->mmc), (unsigned)intmask); + MMC_TRACE(host->mmc, + "Got command interrupt 0x%08x even though no command operation was in progress.\n", + (unsigned)intmask); sdhci_dumpregs(host); return; } + trace_mmc_cmd_rw_end(host->cmd->opcode, intmask, + sdhci_readl(host, SDHCI_RESPONSE)); + if (intmask & SDHCI_INT_TIMEOUT) host->cmd->error = -ETIMEDOUT; else if (intmask & (SDHCI_INT_CRC | SDHCI_INT_END_BIT | SDHCI_INT_INDEX)) host->cmd->error = -EILSEQ; + if (intmask & SDHCI_INT_AUTO_CMD_ERR) { + auto_cmd_status = host->auto_cmd_err_sts; + pr_err_ratelimited("%s: %s: AUTO CMD err sts 0x%08x\n", + mmc_hostname(host->mmc), __func__, auto_cmd_status); + if (auto_cmd_status & (SDHCI_AUTO_CMD12_NOT_EXEC | + SDHCI_AUTO_CMD_INDEX_ERR | + SDHCI_AUTO_CMD_ENDBIT_ERR)) + host->cmd->error = -EIO; + else if (auto_cmd_status & SDHCI_AUTO_CMD_TIMEOUT_ERR) + host->cmd->error = -ETIMEDOUT; + else if (auto_cmd_status & SDHCI_AUTO_CMD_CRC_ERR) + host->cmd->error = -EILSEQ; + } + if (host->cmd->error) { + /* + * If this command initiates a data phase and a response + * CRC error is signalled, the card can start transferring + * data - the card may have received the command without + * error. We must not terminate the mmc_request early. + * + * If the card did not receive the command or returned an + * error which prevented it sending data, the data phase + * will time out. + * + * Even in case of cmd INDEX OR ENDBIT error we + * handle it the same way. + */ + if (host->cmd->data && + (((intmask & (SDHCI_INT_CRC | SDHCI_INT_TIMEOUT)) == + SDHCI_INT_CRC) || (host->cmd->error == -EILSEQ))) { + host->cmd = NULL; + return; + } tasklet_schedule(&host->finish_tasklet); return; } @@ -2426,13 +2994,13 @@ struct sdhci_adma2_64_desc *dma_desc = desc; if (host->flags & SDHCI_USE_64_BIT_DMA) - DBG("%s: %p: DMA 0x%08x%08x, LEN 0x%04x, Attr=0x%02x\n", + DBG("%s: %pK: DMA 0x%08x%08x, LEN 0x%04x,Attr=0x%02x\n", name, desc, le32_to_cpu(dma_desc->addr_hi), le32_to_cpu(dma_desc->addr_lo), le16_to_cpu(dma_desc->len), le16_to_cpu(dma_desc->cmd)); else - DBG("%s: %p: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n", + DBG("%s: %pK: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n", name, desc, le32_to_cpu(dma_desc->addr_lo), le16_to_cpu(dma_desc->len), le16_to_cpu(dma_desc->cmd)); @@ -2450,13 +3018,17 @@ static void sdhci_data_irq(struct sdhci_host *host, u32 intmask) { u32 command; + bool pr_msg = false; BUG_ON(intmask == 0); + command = SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND)); + trace_mmc_data_rw_end(command, intmask); + /* CMD19 generates _only_ Buffer Read Ready interrupt */ if (intmask & SDHCI_INT_DATA_AVAIL) { - command = SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND)); - if (command == MMC_SEND_TUNING_BLOCK || - command == MMC_SEND_TUNING_BLOCK_HS200) { + if (!(host->quirks2 & SDHCI_QUIRK2_NON_STANDARD_TUNING) && + (command == MMC_SEND_TUNING_BLOCK || + command == MMC_SEND_TUNING_BLOCK_HS200)) { host->tuning_done = 1; wake_up(&host->buf_ready_int); return; @@ -2470,11 +3042,6 @@ * above in sdhci_cmd_irq(). */ if (host->cmd && (host->cmd->flags & MMC_RSP_BUSY)) { - if (intmask & SDHCI_INT_DATA_TIMEOUT) { - host->cmd->error = -ETIMEDOUT; - tasklet_schedule(&host->finish_tasklet); - return; - } if (intmask & SDHCI_INT_DATA_END) { /* * Some cards handle busy-end interrupt @@ -2487,11 +3054,29 @@ host->busy_handle = 1; return; } + if (host->quirks2 & + SDHCI_QUIRK2_IGNORE_DATATOUT_FOR_R1BCMD) { + pr_err_ratelimited("%s: %s: ignoring interrupt: 0x%08x due to DATATOUT_FOR_R1B quirk\n", + mmc_hostname(host->mmc), + __func__, intmask); + MMC_TRACE(host->mmc, + "%s: Quirk ignoring intr: 0x%08x\n", + __func__, intmask); + return; + } + if (intmask & SDHCI_INT_DATA_TIMEOUT) { + host->cmd->error = -ETIMEDOUT; + tasklet_schedule(&host->finish_tasklet); + return; + } } pr_err("%s: Got data interrupt 0x%08x even " "though no data operation was in progress.\n", mmc_hostname(host->mmc), (unsigned)intmask); + MMC_TRACE(host->mmc, + "Got data interrupt 0x%08x even though no data operation was in progress.\n", + (unsigned)intmask); sdhci_dumpregs(host); return; @@ -2502,8 +3087,7 @@ else if (intmask & SDHCI_INT_DATA_END_BIT) host->data->error = -EILSEQ; else if ((intmask & SDHCI_INT_DATA_CRC) && - SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND)) - != MMC_BUS_TEST_R) + (command != MMC_BUS_TEST_R)) host->data->error = -EILSEQ; else if (intmask & SDHCI_INT_ADMA_ERROR) { pr_err("%s: ADMA error\n", mmc_hostname(host->mmc)); @@ -2512,10 +3096,34 @@ if (host->ops->adma_workaround) host->ops->adma_workaround(host, intmask); } + if (host->data->error) { + if (intmask & (SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT + | SDHCI_INT_DATA_END_BIT)) { + command = SDHCI_GET_CMD(sdhci_readw(host, + SDHCI_COMMAND)); + if ((command != MMC_SEND_TUNING_BLOCK_HS200) && + (command != MMC_SEND_TUNING_BLOCK)) + pr_msg = true; + } else { + pr_msg = true; + } + if (pr_msg && __ratelimit(&host->dbg_dump_rs)) { + pr_err("%s: data txfr (0x%08x) error: %d after %lld ms\n", + mmc_hostname(host->mmc), intmask, + host->data->error, ktime_to_ms(ktime_sub( + ktime_get(), host->data_start_time))); + MMC_TRACE(host->mmc, + "data txfr (0x%08x) error: %d after %lld ms\n", + intmask, host->data->error, + ktime_to_ms(ktime_sub(ktime_get(), + host->data_start_time))); - if (host->data->error) + if (!host->mmc->sdr104_wa || + (host->mmc->ios.timing != MMC_TIMING_UHS_SDR104)) + sdhci_dumpregs(host); + } sdhci_finish_data(host); - else { + } else { if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL)) sdhci_transfer_pio(host); @@ -2561,6 +3169,58 @@ } } +#ifdef CONFIG_MMC_CQ_HCI +static int sdhci_get_cmd_err(u32 intmask) +{ + if (intmask & SDHCI_INT_TIMEOUT) + return -ETIMEDOUT; + else if (intmask & (SDHCI_INT_CRC | SDHCI_INT_END_BIT | + SDHCI_INT_INDEX)) + return -EILSEQ; + return 0; +} + +static int sdhci_get_data_err(u32 intmask) +{ + if (intmask & SDHCI_INT_DATA_TIMEOUT) + return -ETIMEDOUT; + else if (intmask & (SDHCI_INT_DATA_END_BIT | SDHCI_INT_DATA_CRC)) + return -EILSEQ; + else if (intmask & SDHCI_INT_ADMA_ERROR) + return -EIO; + return 0; +} + +static irqreturn_t sdhci_cmdq_irq(struct sdhci_host *host, u32 intmask) +{ + int err = 0; + u32 mask = 0; + irqreturn_t ret; + + if (intmask & SDHCI_INT_CMD_MASK) + err = sdhci_get_cmd_err(intmask); + else if (intmask & SDHCI_INT_DATA_MASK) + err = sdhci_get_data_err(intmask); + + ret = cmdq_irq(host->mmc, err); + if (err) { + /* Clear the error interrupts */ + mask = intmask & SDHCI_INT_ERROR_MASK; + sdhci_writel(host, mask, SDHCI_INT_STATUS); + } + return ret; + +} + +#else +static irqreturn_t sdhci_cmdq_irq(struct sdhci_host *host, u32 intmask) +{ + pr_err("%s: Received cmdq-irq when disabled !!!!\n", + mmc_hostname(host->mmc)); + return IRQ_NONE; +} +#endif + static irqreturn_t sdhci_irq(int irq, void *dev_id) { irqreturn_t result = IRQ_NONE; @@ -2575,6 +3235,31 @@ return IRQ_NONE; } + if (!host->clock && host->mmc->card && + mmc_card_sdio(host->mmc->card)) { + if (!mmc_card_and_host_support_async_int(host->mmc)) { + spin_unlock(&host->lock); + return IRQ_NONE; + } + /* + * async card interrupt is level sensitive and received + * when clocks are off. + * If sdio card has asserted async interrupt, in that + * case we need to disable host->irq. + * Later we can disable card interrupt and re-enable + * host->irq. + */ + + pr_debug("%s: %s: sdio_async intr. received\n", + mmc_hostname(host->mmc), __func__); + sdhci_cfg_irq(host, false, false); + host->sdio_irq_async_status = true; + host->thread_isr |= SDHCI_INT_CARD_INT; + result = IRQ_WAKE_THREAD; + spin_unlock(&host->lock); + return result; + } + intmask = sdhci_readl(host, SDHCI_INT_STATUS); if (!intmask || intmask == 0xffffffff) { result = IRQ_NONE; @@ -2582,6 +3267,22 @@ } do { + if (host->mmc->card && mmc_card_cmdq(host->mmc->card) && + !mmc_host_halt(host->mmc) && !mmc_host_cq_disable(host->mmc)) { + pr_debug("*** %s: cmdq intr: 0x%08x\n", + mmc_hostname(host->mmc), + intmask); + result = sdhci_cmdq_irq(host, intmask); + if (result == IRQ_HANDLED) + goto out; + } + + MMC_TRACE(host->mmc, + "%s: intmask: 0x%x\n", __func__, intmask); + + if (intmask & SDHCI_INT_AUTO_CMD_ERR) + host->auto_cmd_err_sts = sdhci_readw(host, + SDHCI_AUTO_CMD_ERR); /* Clear selected interrupts. */ mask = intmask & (SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK | SDHCI_INT_BUS_POWER); @@ -2620,12 +3321,20 @@ result = IRQ_WAKE_THREAD; } - if (intmask & SDHCI_INT_CMD_MASK) + if (intmask & SDHCI_INT_CMD_MASK) { + if ((host->quirks2 & SDHCI_QUIRK2_SLOW_INT_CLR) && + (host->clock <= 400000)) + udelay(40); sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK, &intmask); + } - if (intmask & SDHCI_INT_DATA_MASK) + if (intmask & SDHCI_INT_DATA_MASK) { + if ((host->quirks2 & SDHCI_QUIRK2_SLOW_INT_CLR) && + (host->clock <= 400000)) + udelay(40); sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK); + } if (intmask & SDHCI_INT_BUS_POWER) pr_err("%s: Card is consuming too much power!\n", @@ -2659,6 +3368,8 @@ if (unexpected) { pr_err("%s: Unexpected interrupt 0x%08x.\n", mmc_hostname(host->mmc), unexpected); + MMC_TRACE(host->mmc, "Unexpected interrupt 0x%08x.\n", + unexpected); sdhci_dumpregs(host); } @@ -2685,8 +3396,11 @@ sdio_run_irqs(host->mmc); spin_lock_irqsave(&host->lock, flags); - if (host->flags & SDHCI_SDIO_IRQ_ENABLED) + if (host->flags & SDHCI_SDIO_IRQ_ENABLED) { + if (host->sdio_irq_async_status) + host->sdio_irq_async_status = false; sdhci_enable_sdio_irq_nolock(host, true); + } spin_unlock_irqrestore(&host->lock, flags); } @@ -2903,11 +3617,255 @@ host->mmc_host_ops = sdhci_ops; mmc->ops = &host->mmc_host_ops; + spin_lock_init(&host->lock); + ratelimit_state_init(&host->dbg_dump_rs, SDHCI_DBG_DUMP_RS_INTERVAL, + SDHCI_DBG_DUMP_RS_BURST); + return host; } EXPORT_SYMBOL_GPL(sdhci_alloc_host); +#ifdef CONFIG_MMC_CQ_HCI +static void sdhci_cmdq_set_transfer_params(struct mmc_host *mmc) +{ + struct sdhci_host *host = mmc_priv(mmc); + u8 ctrl; + + if (host->version >= SDHCI_SPEC_200) { + ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); + ctrl &= ~SDHCI_CTRL_DMA_MASK; + if (host->flags & SDHCI_USE_64_BIT_DMA) + ctrl |= SDHCI_CTRL_ADMA64; + else + ctrl |= SDHCI_CTRL_ADMA32; + sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); + } + if (host->ops->toggle_cdr && !host->cdr_support) + host->ops->toggle_cdr(host, false); +} + +static void sdhci_cmdq_clear_set_irqs(struct mmc_host *mmc, bool clear) +{ + struct sdhci_host *host = mmc_priv(mmc); + u32 ier = 0; + + ier &= ~SDHCI_INT_ALL_MASK; + + if (clear) { + ier = SDHCI_INT_CMDQ_EN | SDHCI_INT_ERROR_MASK; + sdhci_writel(host, ier, SDHCI_INT_ENABLE); + sdhci_writel(host, ier, SDHCI_SIGNAL_ENABLE); + } else { + ier = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT | + SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | + SDHCI_INT_INDEX | SDHCI_INT_END_BIT | + SDHCI_INT_CRC | SDHCI_INT_TIMEOUT | + SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE | + SDHCI_INT_AUTO_CMD_ERR; + sdhci_writel(host, ier, SDHCI_INT_ENABLE); + sdhci_writel(host, ier, SDHCI_SIGNAL_ENABLE); + } +} + +static void sdhci_cmdq_set_data_timeout(struct mmc_host *mmc, u32 val) +{ + struct sdhci_host *host = mmc_priv(mmc); + + sdhci_writeb(host, val, SDHCI_TIMEOUT_CONTROL); +} + +static void sdhci_cmdq_dump_vendor_regs(struct mmc_host *mmc) +{ + struct sdhci_host *host = mmc_priv(mmc); + + sdhci_dumpregs(host); +} + +static int sdhci_cmdq_init(struct sdhci_host *host, struct mmc_host *mmc, + bool dma64) +{ + return cmdq_init(host->cq_host, mmc, dma64); +} + +static void sdhci_cmdq_set_block_size(struct mmc_host *mmc) +{ + struct sdhci_host *host = mmc_priv(mmc); + + sdhci_set_blk_size_reg(host, 512, 0); +} + +static void sdhci_enhanced_strobe_mask(struct mmc_host *mmc, bool set) +{ + struct sdhci_host *host = mmc_priv(mmc); + + if (host->ops->enhanced_strobe_mask) + host->ops->enhanced_strobe_mask(host, set); +} + +static void sdhci_cmdq_clear_set_dumpregs(struct mmc_host *mmc, bool set) +{ + struct sdhci_host *host = mmc_priv(mmc); + + if (host->ops->clear_set_dumpregs) + host->ops->clear_set_dumpregs(host, set); +} +static int sdhci_cmdq_crypto_cfg(struct mmc_host *mmc, + struct mmc_request *mrq, u32 slot, u64 *ice_ctx) +{ + struct sdhci_host *host = mmc_priv(mmc); + int err = 0; + + if (!host->is_crypto_en) + return 0; + + if (host->crypto_reset_reqd && host->ops->crypto_engine_reset) { + err = host->ops->crypto_engine_reset(host); + if (err) { + pr_err("%s: crypto reset failed\n", + mmc_hostname(host->mmc)); + goto out; + } + host->crypto_reset_reqd = false; + } + + if (host->ops->crypto_engine_cmdq_cfg) { + err = host->ops->crypto_engine_cmdq_cfg(host, mrq, + slot, ice_ctx); + if (err) { + pr_err("%s: failed to configure crypto\n", + mmc_hostname(host->mmc)); + goto out; + } + } +out: + return err; +} + +static int sdhci_cmdq_crypto_cfg_end(struct mmc_host *mmc, + struct mmc_request *mrq) +{ + struct sdhci_host *host = mmc_priv(mmc); + + if (!host->is_crypto_en) + return 0; + + return sdhci_crypto_cfg_end(host, mrq); +} + +static void sdhci_cmdq_crypto_cfg_reset(struct mmc_host *mmc, unsigned int slot) +{ + struct sdhci_host *host = mmc_priv(mmc); + + if (!host->is_crypto_en) + return; + + if (host->ops->crypto_cfg_reset) + host->ops->crypto_cfg_reset(host, slot); +} + +static void sdhci_cmdq_post_cqe_halt(struct mmc_host *mmc) +{ + struct sdhci_host *host = mmc_priv(mmc); + + sdhci_writel(host, sdhci_readl(host, SDHCI_INT_ENABLE) | + SDHCI_INT_RESPONSE, SDHCI_INT_ENABLE); + sdhci_writel(host, SDHCI_INT_RESPONSE, SDHCI_INT_STATUS); +} +#else +static void sdhci_cmdq_set_transfer_params(struct mmc_host *mmc) +{ + +} +static void sdhci_cmdq_clear_set_irqs(struct mmc_host *mmc, bool clear) +{ + +} + +static void sdhci_cmdq_set_data_timeout(struct mmc_host *mmc, u32 val) +{ + +} + +static void sdhci_cmdq_dump_vendor_regs(struct mmc_host *mmc) +{ + +} + +static int sdhci_cmdq_init(struct sdhci_host *host, struct mmc_host *mmc, + bool dma64) +{ + return -ENOSYS; +} + +static void sdhci_cmdq_set_block_size(struct mmc_host *mmc) +{ + +} + +static void sdhci_enhanced_strobe_mask(struct mmc_host *mmc, bool set) +{ + +} + +static void sdhci_cmdq_clear_set_dumpregs(struct mmc_host *mmc, bool set) +{ + +} +static int sdhci_cmdq_crypto_cfg(struct mmc_host *mmc, + struct mmc_request *mrq, u32 slot, u64 *ice_ctx) +{ + return 0; +} + +static int sdhci_cmdq_crypto_cfg_end(struct mmc_host *mmc, + struct mmc_request *mrq) +{ + return 0; +} + +static void sdhci_cmdq_crypto_cfg_reset(struct mmc_host *mmc, unsigned int slot) +{ + +} +static void sdhci_cmdq_post_cqe_halt(struct mmc_host *mmc) +{ +} +#endif + +static const struct cmdq_host_ops sdhci_cmdq_ops = { + .clear_set_irqs = sdhci_cmdq_clear_set_irqs, + .set_data_timeout = sdhci_cmdq_set_data_timeout, + .dump_vendor_regs = sdhci_cmdq_dump_vendor_regs, + .set_block_size = sdhci_cmdq_set_block_size, + .clear_set_dumpregs = sdhci_cmdq_clear_set_dumpregs, + .enhanced_strobe_mask = sdhci_enhanced_strobe_mask, + .crypto_cfg = sdhci_cmdq_crypto_cfg, + .crypto_cfg_end = sdhci_cmdq_crypto_cfg_end, + .crypto_cfg_reset = sdhci_cmdq_crypto_cfg_reset, + .post_cqe_halt = sdhci_cmdq_post_cqe_halt, + .set_transfer_params = sdhci_cmdq_set_transfer_params, +}; + +#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT +static int sdhci_is_adma2_64bit(struct sdhci_host *host) +{ + u32 caps; + + caps = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ? host->caps : + sdhci_readl(host, SDHCI_CAPABILITIES); + + if (caps & SDHCI_CAN_64BIT) + return 1; + return 0; +} +#else +static int sdhci_is_adma2_64bit(struct sdhci_host *host) +{ + return 0; +} +#endif + int sdhci_add_host(struct sdhci_host *host) { struct mmc_host *mmc; @@ -2980,7 +3938,7 @@ * SDHCI_QUIRK2_BROKEN_64_BIT_DMA must be left to the drivers to * implement. */ - if (sdhci_readl(host, SDHCI_CAPABILITIES) & SDHCI_CAN_64BIT) + if (sdhci_is_adma2_64bit(host)) host->flags |= SDHCI_USE_64_BIT_DMA; if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) { @@ -3135,6 +4093,9 @@ mmc->caps |= MMC_CAP_SDIO_IRQ | MMC_CAP_ERASE | MMC_CAP_CMD23; mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD; + if (caps[0] & SDHCI_CAN_ASYNC_INT) + mmc->caps2 |= MMC_CAP2_ASYNC_SDIO_IRQ_4BIT_MODE; + if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12) host->flags |= SDHCI_AUTO_CMD12; @@ -3167,7 +4128,8 @@ if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) && !(mmc->caps & MMC_CAP_NONREMOVABLE) && - IS_ERR_VALUE(mmc_gpio_get_cd(host->mmc))) + (IS_ERR_VALUE(mmc_gpio_get_cd(host->mmc)) && + !(mmc->caps2 & MMC_CAP2_NONHOTPLUG))) mmc->caps |= MMC_CAP_NEEDS_POLL; /* If there are external regulators, get them */ @@ -3264,10 +4226,15 @@ * value. */ max_current_caps = sdhci_readl(host, SDHCI_MAX_CURRENT); - if (!max_current_caps && !IS_ERR(mmc->supply.vmmc)) { - int curr = regulator_get_current_limit(mmc->supply.vmmc); - if (curr > 0) { + if (!max_current_caps) { + u32 curr = 0; + + if (!IS_ERR(mmc->supply.vmmc)) + curr = regulator_get_current_limit(mmc->supply.vmmc); + else if (host->ops->get_current_limit) + curr = host->ops->get_current_limit(host); + if (curr > 0) { /* convert to SDHCI_MAX_CURRENT format */ curr = curr/1000; /* convert to mA */ curr = curr/SDHCI_MAX_CURRENT_MULTIPLIER; @@ -3332,8 +4299,6 @@ return -ENODEV; } - spin_lock_init(&host->lock); - /* * Maximum number of segments. Depends on if the hardware * can do scatter/gather or not. @@ -3399,6 +4364,8 @@ init_waitqueue_head(&host->buf_ready_int); + host->flags |= SDHCI_HOST_IRQ_STATUS; + sdhci_init(host, 0); ret = request_threaded_irq(host->irq, sdhci_irq, sdhci_thread_irq, @@ -3414,6 +4381,7 @@ #endif #ifdef SDHCI_USE_LEDS_CLASS + if (!(host->quirks2 & SDHCI_QUIRK2_BROKEN_LED_CONTROL)) { snprintf(host->led_name, sizeof(host->led_name), "%s::", mmc_hostname(mmc)); host->led.name = host->led_name; @@ -3427,20 +4395,40 @@ mmc_hostname(mmc), ret); goto reset; } + } #endif mmiowb(); - mmc_add_host(mmc); + if (host->quirks2 & SDHCI_QUIRK2_IGN_DATA_END_BIT_ERROR) { + host->ier = (host->ier & ~SDHCI_INT_DATA_END_BIT); + sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); + sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); + } + + if (mmc->caps2 & MMC_CAP2_CMD_QUEUE) { + bool dma64 = (host->flags & SDHCI_USE_64_BIT_DMA) ? + true : false; + ret = sdhci_cmdq_init(host, mmc, dma64); + if (ret) + pr_err("%s: CMDQ init: failed (%d)\n", + mmc_hostname(host->mmc), ret); + else + host->cq_host->ops = &sdhci_cmdq_ops; + } - pr_info("%s: SDHCI controller on %s [%s] using %s\n", + pr_info("%s: SDHCI controller on %s [%s] using %s in %s mode\n", mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)), (host->flags & SDHCI_USE_ADMA) ? - (host->flags & SDHCI_USE_64_BIT_DMA) ? "ADMA 64-bit" : "ADMA" : - (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO"); + ((host->flags & SDHCI_USE_64_BIT_DMA) ? + "64-bit ADMA" : "32-bit ADMA") : + ((host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO"), + ((mmc->caps2 & MMC_CAP2_CMD_QUEUE) && !ret) ? + "CMDQ" : "legacy"); sdhci_enable_card_detection(host); + mmc_add_host(mmc); return 0; #ifdef SDHCI_USE_LEDS_CLASS @@ -3481,9 +4469,10 @@ sdhci_disable_card_detection(host); - mmc_remove_host(mmc); + mmc_remove_host(host->mmc); #ifdef SDHCI_USE_LEDS_CLASS + if (!(host->quirks2 & SDHCI_QUIRK2_BROKEN_LED_CONTROL)) led_classdev_unregister(&host->led); #endif diff -ruw linux-4.4.115/drivers/mmc/host/sdhci.h linux-4.4.115-fbx/drivers/mmc/host/sdhci.h --- linux-4.4.115/drivers/mmc/host/sdhci.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/mmc/host/sdhci.h 2019-10-29 09:26:24.077207425 +0100 @@ -17,7 +17,7 @@ #include #include #include - +#include #include /* @@ -137,22 +137,32 @@ #define SDHCI_INT_DATA_CRC 0x00200000 #define SDHCI_INT_DATA_END_BIT 0x00400000 #define SDHCI_INT_BUS_POWER 0x00800000 -#define SDHCI_INT_ACMD12ERR 0x01000000 +#define SDHCI_INT_AUTO_CMD_ERR 0x01000000 #define SDHCI_INT_ADMA_ERROR 0x02000000 #define SDHCI_INT_NORMAL_MASK 0x00007FFF #define SDHCI_INT_ERROR_MASK 0xFFFF8000 #define SDHCI_INT_CMD_MASK (SDHCI_INT_RESPONSE | SDHCI_INT_TIMEOUT | \ - SDHCI_INT_CRC | SDHCI_INT_END_BIT | SDHCI_INT_INDEX) + SDHCI_INT_CRC | SDHCI_INT_END_BIT | SDHCI_INT_INDEX | \ + SDHCI_INT_AUTO_CMD_ERR) + #define SDHCI_INT_DATA_MASK (SDHCI_INT_DATA_END | SDHCI_INT_DMA_END | \ SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | \ SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_DATA_CRC | \ SDHCI_INT_DATA_END_BIT | SDHCI_INT_ADMA_ERROR | \ SDHCI_INT_BLK_GAP) + +#define SDHCI_INT_CMDQ_EN (0x1 << 14) #define SDHCI_INT_ALL_MASK ((unsigned int)-1) -#define SDHCI_ACMD12_ERR 0x3C +#define SDHCI_AUTO_CMD_ERR 0x3C +#define SDHCI_AUTO_CMD12_NOT_EXEC 0x0001 +#define SDHCI_AUTO_CMD_TIMEOUT_ERR 0x0002 +#define SDHCI_AUTO_CMD_CRC_ERR 0x0004 +#define SDHCI_AUTO_CMD_ENDBIT_ERR 0x0008 +#define SDHCI_AUTO_CMD_INDEX_ERR 0x0010 +#define SDHCI_AUTO_CMD12_NOT_ISSUED 0x0080 #define SDHCI_HOST_CONTROL2 0x3E #define SDHCI_CTRL_UHS_MASK 0x0007 @@ -170,6 +180,7 @@ #define SDHCI_CTRL_DRV_TYPE_D 0x0030 #define SDHCI_CTRL_EXEC_TUNING 0x0040 #define SDHCI_CTRL_TUNED_CLK 0x0080 +#define SDHCI_CTRL_ASYNC_INT_ENABLE 0x4000 #define SDHCI_CTRL_PRESET_VAL_ENABLE 0x8000 #define SDHCI_CAPABILITIES 0x40 @@ -190,6 +201,7 @@ #define SDHCI_CAN_VDD_300 0x02000000 #define SDHCI_CAN_VDD_180 0x04000000 #define SDHCI_CAN_64BIT 0x10000000 +#define SDHCI_CAN_ASYNC_INT 0x20000000 #define SDHCI_SUPPORT_SDR50 0x00000001 #define SDHCI_SUPPORT_SDR104 0x00000002 @@ -320,6 +332,12 @@ COOKIE_GIVEN, }; +enum sdhci_power_policy { + SDHCI_PERFORMANCE_MODE, + SDHCI_POWER_SAVE_MODE, + SDHCI_POWER_POLICY_NUM /* Always keep this one last */ +}; + struct sdhci_host { /* Data set by hardware interface driver */ const char *hw_name; /* Hardware bus name */ @@ -423,6 +441,84 @@ */ #define SDHCI_QUIRK2_NEED_DELAY_AFTER_INT_CLK_RST (1<<16) +/* + * Read Transfer Active/ Write Transfer Active may be not + * de-asserted after end of transaction. Issue reset for DAT line. + */ +#define SDHCI_QUIRK2_RDWR_TX_ACTIVE_EOT (1<<17) +/* + * Slow interrupt clearance at 400KHz may cause + * host controller driver interrupt handler to + * be called twice. + */ +#define SDHCI_QUIRK2_SLOW_INT_CLR (1<<18) + +/* + * If the base clock can be scalable, then there should be no further + * clock dividing as the input clock itself will be scaled down to + * required frequency. + */ +#define SDHCI_QUIRK2_ALWAYS_USE_BASE_CLOCK (1<<19) + +/* + * Ignore data timeout error for R1B commands as there will be no + * data associated and the busy timeout value for these commands + * could be lager than the maximum timeout value that controller + * can handle. + */ +#define SDHCI_QUIRK2_IGNORE_DATATOUT_FOR_R1BCMD (1<<20) + +/* + * The preset value registers are not properly initialized by + * some hardware and hence preset value must not be enabled for + * such controllers. + */ +#define SDHCI_QUIRK2_BROKEN_PRESET_VALUE (1<<21) +/* + * Some controllers define the usage of 0xF in data timeout counter + * register (0x2E) which is actually a reserved bit as per + * specification. + */ +#define SDHCI_QUIRK2_USE_RESERVED_MAX_TIMEOUT (1<<22) +/* + * This is applicable for controllers that advertize timeout clock + * value in capabilities register (bit 5-0) as just 50MHz whereas the + * base clock frequency is 200MHz. So, the controller internally + * multiplies the value in timeout control register by 4 with the + * assumption that driver always uses fixed timeout clock value from + * capabilities register to calculate the timeout. But when the driver + * uses SDHCI_QUIRK2_ALWAYS_USE_BASE_CLOCK base clock frequency is directly + * controller by driver and it's rate varies upto max. 200MHz. This new quirk + * will be used in such cases to avoid controller mulplication when timeout is + * calculated based on the base clock. + */ +#define SDHCI_QUIRK2_DIVIDE_TOUT_BY_4 (1 << 23) + +/* + * Some SDHC controllers are unable to handle data-end bit error in + * 1-bit mode of SDIO. + */ +#define SDHCI_QUIRK2_IGN_DATA_END_BIT_ERROR (1<<24) + +/* Controller has nonstandard clock management */ +#define SDHCI_QUIRK_NONSTANDARD_CLOCK (1<<25) +/* Use reset workaround in case sdhci reset timeouts */ +#define SDHCI_QUIRK2_USE_RESET_WORKAROUND (1<<26) +/* Some controllers doesn't have have any LED control */ +#define SDHCI_QUIRK2_BROKEN_LED_CONTROL (1<<27) +/* + * Some controllers doesn't follow the tuning procedure as defined in spec. + * The tuning data has to be compared from SW driver to validate the correct + * phase. + */ +#define SDHCI_QUIRK2_NON_STANDARD_TUNING (1 << 28) +/* + * Some controllers may use PIO mode to workaround HW issues in ADMA for + * eMMC tuning commands. + */ +#define SDHCI_QUIRK2_USE_PIO_FOR_EMMC_TUNING (1 << 29) + + int irq; /* Device IRQ */ void __iomem *ioaddr; /* Mapped address */ @@ -432,6 +528,7 @@ struct mmc_host *mmc; /* MMC structure */ struct mmc_host_ops mmc_host_ops; /* MMC host ops */ u64 dma_mask; /* custom DMA mask */ + u64 coherent_dma_mask; #if defined(CONFIG_LEDS_CLASS) || defined(CONFIG_LEDS_CLASS_MODULE) struct led_classdev led; /* LED control */ @@ -453,6 +550,7 @@ #define SDHCI_SDR104_NEEDS_TUNING (1<<10) /* SDR104/HS200 needs tuning */ #define SDHCI_USE_64_BIT_DMA (1<<12) /* Use 64-bit DMA */ #define SDHCI_HS400_TUNING (1<<13) /* Tuning for HS400 */ +#define SDHCI_HOST_IRQ_STATUS (1<<14) /* host->irq status */ unsigned int version; /* SDHCI spec. version */ @@ -466,6 +564,7 @@ bool runtime_suspended; /* Host is runtime suspended */ bool bus_on; /* Bus power prevents runtime suspend */ bool preset_enabled; /* Preset is enabled */ + bool cdr_support; struct mmc_request *mrq; /* Current request */ struct mmc_command *cmd; /* Current command */ @@ -514,6 +613,20 @@ unsigned int tuning_count; /* Timer count for re-tuning */ unsigned int tuning_mode; /* Re-tuning mode supported by host */ #define SDHCI_TUNING_MODE_1 0 + ktime_t data_start_time; + + enum sdhci_power_policy power_policy; + + bool is_crypto_en; + bool crypto_reset_reqd; + bool sdio_irq_async_status; + + u32 auto_cmd_err_sts; + struct ratelimit_state dbg_dump_rs; + struct cmdq_host *cq_host; + int reset_wa_applied; /* reset workaround status */ + ktime_t reset_wa_t; /* time when the reset workaround is applied */ + int reset_wa_cnt; /* total number of times workaround is used */ unsigned long private[0] ____cacheline_aligned; }; @@ -543,16 +656,46 @@ unsigned int (*get_ro)(struct sdhci_host *host); void (*reset)(struct sdhci_host *host, u8 mask); int (*platform_execute_tuning)(struct sdhci_host *host, u32 opcode); + int (*crypto_engine_cfg)(struct sdhci_host *host, + struct mmc_request *mrq, u32 slot); + int (*crypto_engine_cmdq_cfg)(struct sdhci_host *host, + struct mmc_request *mrq, u32 slot, u64 *ice_ctx); + int (*crypto_engine_cfg_end)(struct sdhci_host *host, + struct mmc_request *mrq); + int (*crypto_engine_reset)(struct sdhci_host *host); + void (*crypto_cfg_reset)(struct sdhci_host *host, unsigned int slot); void (*set_uhs_signaling)(struct sdhci_host *host, unsigned int uhs); void (*hw_reset)(struct sdhci_host *host); void (*adma_workaround)(struct sdhci_host *host, u32 intmask); + unsigned int (*get_max_segments)(void); void (*platform_init)(struct sdhci_host *host); +#define REQ_BUS_OFF (1 << 0) +#define REQ_BUS_ON (1 << 1) +#define REQ_IO_LOW (1 << 2) +#define REQ_IO_HIGH (1 << 3) void (*card_event)(struct sdhci_host *host); + int (*enhanced_strobe)(struct sdhci_host *host); + void (*platform_bus_voting)(struct sdhci_host *host, u32 enable); + void (*check_power_status)(struct sdhci_host *host, u32 req_type); + int (*config_auto_tuning_cmd)(struct sdhci_host *host, + bool enable, + u32 type); + int (*enable_controller_clock)(struct sdhci_host *host); + void (*clear_set_dumpregs)(struct sdhci_host *host, bool set); + void (*enhanced_strobe_mask)(struct sdhci_host *host, bool set); + void (*dump_vendor_regs)(struct sdhci_host *host); + void (*toggle_cdr)(struct sdhci_host *host, bool enable); void (*voltage_switch)(struct sdhci_host *host); int (*select_drive_strength)(struct sdhci_host *host, struct mmc_card *card, unsigned int max_dtr, int host_drv, int card_drv, int *drv_type); + int (*notify_load)(struct sdhci_host *host, enum mmc_load state); + void (*reset_workaround)(struct sdhci_host *host, u32 enable); + void (*init)(struct sdhci_host *host); + void (*pre_req)(struct sdhci_host *host, struct mmc_request *req); + void (*post_req)(struct sdhci_host *host, struct mmc_request *req); + unsigned int (*get_current_limit)(struct sdhci_host *host); }; #ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS @@ -672,4 +815,5 @@ extern int sdhci_runtime_resume_host(struct sdhci_host *host); #endif +void sdhci_cfg_irq(struct sdhci_host *host, bool enable, bool sync); #endif /* __SDHCI_HW_H */ diff -ruw linux-4.4.115/drivers/mmc/host/sdhci-msm.c linux-4.4.115-fbx/drivers/mmc/host/sdhci-msm.c --- linux-4.4.115/drivers/mmc/host/sdhci-msm.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/mmc/host/sdhci-msm.c 2019-10-29 09:26:24.073207386 +0100 @@ -1,7 +1,8 @@ /* - * drivers/mmc/host/sdhci-msm.c - Qualcomm SDHCI Platform driver + * drivers/mmc/host/sdhci-msm.c - Qualcomm Technologies, Inc. MSM SDHCI Platform + * driver source file * - * Copyright (c) 2013-2014, The Linux Foundation. All rights reserved. + * Copyright (c) 2012-2018, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -15,97 +16,498 @@ */ #include +#include +#include +#include +#include +#include #include +#include +#include +#include +#include +#include +#include +#include #include -#include +#include #include +#include +#include +#include +#include +#include +#include +#include + +#include "sdhci-msm.h" +#include "sdhci-msm-ice.h" +#include "cmdq_hci.h" -#include "sdhci-pltfm.h" +#define QOS_REMOVE_DELAY_MS 10 +#define CORE_POWER 0x0 +#define CORE_SW_RST (1 << 7) + +#define SDHCI_VER_100 0x2B -#define CORE_MCI_VERSION 0x50 +#define CORE_VERSION_STEP_MASK 0x0000FFFF +#define CORE_VERSION_MINOR_MASK 0x0FFF0000 +#define CORE_VERSION_MINOR_SHIFT 16 +#define CORE_VERSION_MAJOR_MASK 0xF0000000 #define CORE_VERSION_MAJOR_SHIFT 28 -#define CORE_VERSION_MAJOR_MASK (0xf << CORE_VERSION_MAJOR_SHIFT) -#define CORE_VERSION_MINOR_MASK 0xff +#define CORE_VERSION_TARGET_MASK 0x000000FF +#define SDHCI_MSM_VER_420 0x49 + +#define SWITCHABLE_SIGNALLING_VOL (1 << 29) #define CORE_HC_MODE 0x78 #define HC_MODE_EN 0x1 -#define CORE_POWER 0x0 -#define CORE_SW_RST BIT(7) +#define FF_CLK_SW_RST_DIS (1 << 13) + +#define CORE_PWRCTL_BUS_OFF 0x01 +#define CORE_PWRCTL_BUS_ON (1 << 1) +#define CORE_PWRCTL_IO_LOW (1 << 2) +#define CORE_PWRCTL_IO_HIGH (1 << 3) + +#define CORE_PWRCTL_BUS_SUCCESS 0x01 +#define CORE_PWRCTL_BUS_FAIL (1 << 1) +#define CORE_PWRCTL_IO_SUCCESS (1 << 2) +#define CORE_PWRCTL_IO_FAIL (1 << 3) +#define INT_MASK 0xF #define MAX_PHASES 16 -#define CORE_DLL_LOCK BIT(7) -#define CORE_DLL_EN BIT(16) -#define CORE_CDR_EN BIT(17) -#define CORE_CK_OUT_EN BIT(18) -#define CORE_CDR_EXT_EN BIT(19) -#define CORE_DLL_PDN BIT(29) -#define CORE_DLL_RST BIT(30) -#define CORE_DLL_CONFIG 0x100 -#define CORE_DLL_STATUS 0x108 - -#define CORE_VENDOR_SPEC 0x10c -#define CORE_CLK_PWRSAVE BIT(1) - -#define CORE_VENDOR_SPEC_CAPABILITIES0 0x11c - -#define CDR_SELEXT_SHIFT 20 -#define CDR_SELEXT_MASK (0xf << CDR_SELEXT_SHIFT) -#define CMUX_SHIFT_PHASE_SHIFT 24 -#define CMUX_SHIFT_PHASE_MASK (7 << CMUX_SHIFT_PHASE_SHIFT) - -struct sdhci_msm_host { - struct platform_device *pdev; - void __iomem *core_mem; /* MSM SDCC mapped address */ - struct clk *clk; /* main SD/MMC bus clock */ - struct clk *pclk; /* SDHC peripheral bus clock */ - struct clk *bus_clk; /* SDHC bus voter clock */ - struct mmc_host *mmc; - struct sdhci_pltfm_data sdhci_msm_pdata; + +#define CORE_CMD_DAT_TRACK_SEL (1 << 0) +#define CORE_DLL_EN (1 << 16) +#define CORE_CDR_EN (1 << 17) +#define CORE_CK_OUT_EN (1 << 18) +#define CORE_CDR_EXT_EN (1 << 19) +#define CORE_DLL_PDN (1 << 29) +#define CORE_DLL_RST (1 << 30) + +#define CORE_DLL_LOCK (1 << 7) +#define CORE_DDR_DLL_LOCK (1 << 11) + +#define CORE_CLK_PWRSAVE (1 << 1) +#define CORE_HC_MCLK_SEL_DFLT (2 << 8) +#define CORE_HC_MCLK_SEL_HS400 (3 << 8) +#define CORE_HC_MCLK_SEL_MASK (3 << 8) +#define CORE_HC_AUTO_CMD21_EN (1 << 6) +#define CORE_IO_PAD_PWR_SWITCH_EN (1 << 15) +#define CORE_IO_PAD_PWR_SWITCH (1 << 16) +#define CORE_HC_SELECT_IN_EN (1 << 18) +#define CORE_HC_SELECT_IN_HS400 (6 << 19) +#define CORE_HC_SELECT_IN_MASK (7 << 19) +#define CORE_VENDOR_SPEC_POR_VAL 0xA1C + +#define HC_SW_RST_WAIT_IDLE_DIS (1 << 20) +#define HC_SW_RST_REQ (1 << 21) +#define CORE_ONE_MID_EN (1 << 25) + +#define CORE_8_BIT_SUPPORT (1 << 18) +#define CORE_3_3V_SUPPORT (1 << 24) +#define CORE_3_0V_SUPPORT (1 << 25) +#define CORE_1_8V_SUPPORT (1 << 26) +#define CORE_SYS_BUS_SUPPORT_64_BIT BIT(28) + +#define CORE_CSR_CDC_CTLR_CFG0 0x130 +#define CORE_SW_TRIG_FULL_CALIB (1 << 16) +#define CORE_HW_AUTOCAL_ENA (1 << 17) + +#define CORE_CSR_CDC_CTLR_CFG1 0x134 +#define CORE_CSR_CDC_CAL_TIMER_CFG0 0x138 +#define CORE_TIMER_ENA (1 << 16) + +#define CORE_CSR_CDC_CAL_TIMER_CFG1 0x13C +#define CORE_CSR_CDC_REFCOUNT_CFG 0x140 +#define CORE_CSR_CDC_COARSE_CAL_CFG 0x144 +#define CORE_CDC_OFFSET_CFG 0x14C +#define CORE_CSR_CDC_DELAY_CFG 0x150 +#define CORE_CDC_SLAVE_DDA_CFG 0x160 +#define CORE_CSR_CDC_STATUS0 0x164 +#define CORE_CALIBRATION_DONE (1 << 0) + +#define CORE_CDC_ERROR_CODE_MASK 0x7000000 + +#define CQ_CMD_DBG_RAM 0x110 +#define CQ_CMD_DBG_RAM_WA 0x150 +#define CQ_CMD_DBG_RAM_OL 0x154 + +#define CORE_CSR_CDC_GEN_CFG 0x178 +#define CORE_CDC_SWITCH_BYPASS_OFF (1 << 0) +#define CORE_CDC_SWITCH_RC_EN (1 << 1) + +#define CORE_CDC_T4_DLY_SEL (1 << 0) +#define CORE_CMDIN_RCLK_EN (1 << 1) +#define CORE_START_CDC_TRAFFIC (1 << 6) + +#define CORE_PWRSAVE_DLL (1 << 3) +#define CORE_FIFO_ALT_EN (1 << 10) +#define CORE_CMDEN_HS400_INPUT_MASK_CNT (1 << 13) + +#define CORE_DDR_CAL_EN (1 << 0) +#define CORE_FLL_CYCLE_CNT (1 << 18) +#define CORE_DLL_CLOCK_DISABLE (1 << 21) + +#define DDR_CONFIG_POR_VAL 0x80040853 +#define DDR_CONFIG_PRG_RCLK_DLY_MASK 0x1FF +#define DDR_CONFIG_PRG_RCLK_DLY 115 +#define DDR_CONFIG_2_POR_VAL 0x80040873 + +/* 512 descriptors */ +#define SDHCI_MSM_MAX_SEGMENTS (1 << 9) +#define SDHCI_MSM_MMC_CLK_GATE_DELAY 200 /* msecs */ + +#define CORE_FREQ_100MHZ (100 * 1000 * 1000) +#define TCXO_FREQ 19200000 + +#define INVALID_TUNING_PHASE -1 +#define sdhci_is_valid_gpio_wakeup_int(_h) ((_h)->pdata->sdiowakeup_irq >= 0) + +#define NUM_TUNING_PHASES 16 +#define MAX_DRV_TYPES_SUPPORTED_HS200 4 +#define MSM_AUTOSUSPEND_DELAY_MS 100 + +struct sdhci_msm_offset { + u32 CORE_MCI_DATA_CNT; + u32 CORE_MCI_STATUS; + u32 CORE_MCI_FIFO_CNT; + u32 CORE_MCI_VERSION; + u32 CORE_GENERICS; + u32 CORE_TESTBUS_CONFIG; + u32 CORE_TESTBUS_SEL2_BIT; + u32 CORE_TESTBUS_ENA; + u32 CORE_TESTBUS_SEL2; + u32 CORE_PWRCTL_STATUS; + u32 CORE_PWRCTL_MASK; + u32 CORE_PWRCTL_CLEAR; + u32 CORE_PWRCTL_CTL; + u32 CORE_SDCC_DEBUG_REG; + u32 CORE_DLL_CONFIG; + u32 CORE_DLL_STATUS; + u32 CORE_VENDOR_SPEC; + u32 CORE_VENDOR_SPEC_ADMA_ERR_ADDR0; + u32 CORE_VENDOR_SPEC_ADMA_ERR_ADDR1; + u32 CORE_VENDOR_SPEC_FUNC2; + u32 CORE_VENDOR_SPEC_CAPABILITIES0; + u32 CORE_DDR_200_CFG; + u32 CORE_VENDOR_SPEC3; + u32 CORE_DLL_CONFIG_2; + u32 CORE_DDR_CONFIG; + u32 CORE_DDR_CONFIG_2; }; -/* Platform specific tuning */ -static inline int msm_dll_poll_ck_out_en(struct sdhci_host *host, u8 poll) +struct sdhci_msm_offset sdhci_msm_offset_mci_removed = { + .CORE_MCI_DATA_CNT = 0x35C, + .CORE_MCI_STATUS = 0x324, + .CORE_MCI_FIFO_CNT = 0x308, + .CORE_MCI_VERSION = 0x318, + .CORE_GENERICS = 0x320, + .CORE_TESTBUS_CONFIG = 0x32C, + .CORE_TESTBUS_SEL2_BIT = 3, + .CORE_TESTBUS_ENA = (1 << 31), + .CORE_TESTBUS_SEL2 = (1 << 3), + .CORE_PWRCTL_STATUS = 0x240, + .CORE_PWRCTL_MASK = 0x244, + .CORE_PWRCTL_CLEAR = 0x248, + .CORE_PWRCTL_CTL = 0x24C, + .CORE_SDCC_DEBUG_REG = 0x358, + .CORE_DLL_CONFIG = 0x200, + .CORE_DLL_STATUS = 0x208, + .CORE_VENDOR_SPEC = 0x20C, + .CORE_VENDOR_SPEC_ADMA_ERR_ADDR0 = 0x214, + .CORE_VENDOR_SPEC_ADMA_ERR_ADDR1 = 0x218, + .CORE_VENDOR_SPEC_FUNC2 = 0x210, + .CORE_VENDOR_SPEC_CAPABILITIES0 = 0x21C, + .CORE_DDR_200_CFG = 0x224, + .CORE_VENDOR_SPEC3 = 0x250, + .CORE_DLL_CONFIG_2 = 0x254, + .CORE_DDR_CONFIG = 0x258, + .CORE_DDR_CONFIG_2 = 0x25C, +}; + +struct sdhci_msm_offset sdhci_msm_offset_mci_present = { + .CORE_MCI_DATA_CNT = 0x30, + .CORE_MCI_STATUS = 0x34, + .CORE_MCI_FIFO_CNT = 0x44, + .CORE_MCI_VERSION = 0x050, + .CORE_GENERICS = 0x70, + .CORE_TESTBUS_CONFIG = 0x0CC, + .CORE_TESTBUS_SEL2_BIT = 4, + .CORE_TESTBUS_ENA = (1 << 3), + .CORE_TESTBUS_SEL2 = (1 << 4), + .CORE_PWRCTL_STATUS = 0xDC, + .CORE_PWRCTL_MASK = 0xE0, + .CORE_PWRCTL_CLEAR = 0xE4, + .CORE_PWRCTL_CTL = 0xE8, + .CORE_SDCC_DEBUG_REG = 0x124, + .CORE_DLL_CONFIG = 0x100, + .CORE_DLL_STATUS = 0x108, + .CORE_VENDOR_SPEC = 0x10C, + .CORE_VENDOR_SPEC_ADMA_ERR_ADDR0 = 0x114, + .CORE_VENDOR_SPEC_ADMA_ERR_ADDR1 = 0x118, + .CORE_VENDOR_SPEC_FUNC2 = 0x110, + .CORE_VENDOR_SPEC_CAPABILITIES0 = 0x11C, + .CORE_DDR_200_CFG = 0x184, + .CORE_VENDOR_SPEC3 = 0x1B0, + .CORE_DLL_CONFIG_2 = 0x1B4, + .CORE_DDR_CONFIG = 0x1B8, + .CORE_DDR_CONFIG_2 = 0x1BC, +}; + +u8 sdhci_msm_readb_relaxed(struct sdhci_host *host, u32 offset) +{ + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); + struct sdhci_msm_host *msm_host = pltfm_host->priv; + void __iomem *base_addr; + + if (msm_host->mci_removed) + base_addr = host->ioaddr; + else + base_addr = msm_host->core_mem; + + return readb_relaxed(base_addr + offset); +} + +u32 sdhci_msm_readl_relaxed(struct sdhci_host *host, u32 offset) +{ + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); + struct sdhci_msm_host *msm_host = pltfm_host->priv; + void __iomem *base_addr; + + if (msm_host->mci_removed) + base_addr = host->ioaddr; + else + base_addr = msm_host->core_mem; + + return readl_relaxed(base_addr + offset); +} + +void sdhci_msm_writeb_relaxed(u8 val, struct sdhci_host *host, u32 offset) +{ + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); + struct sdhci_msm_host *msm_host = pltfm_host->priv; + void __iomem *base_addr; + + if (msm_host->mci_removed) + base_addr = host->ioaddr; + else + base_addr = msm_host->core_mem; + + writeb_relaxed(val, base_addr + offset); +} + +void sdhci_msm_writel_relaxed(u32 val, struct sdhci_host *host, u32 offset) { + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); + struct sdhci_msm_host *msm_host = pltfm_host->priv; + void __iomem *base_addr; + + if (msm_host->mci_removed) + base_addr = host->ioaddr; + else + base_addr = msm_host->core_mem; + + writel_relaxed(val, base_addr + offset); +} + +/* Timeout value to avoid infinite waiting for pwr_irq */ +#define MSM_PWR_IRQ_TIMEOUT_MS 5000 + +static const u32 tuning_block_64[] = { + 0x00FF0FFF, 0xCCC3CCFF, 0xFFCC3CC3, 0xEFFEFFFE, + 0xDDFFDFFF, 0xFBFFFBFF, 0xFF7FFFBF, 0xEFBDF777, + 0xF0FFF0FF, 0x3CCCFC0F, 0xCFCC33CC, 0xEEFFEFFF, + 0xFDFFFDFF, 0xFFBFFFDF, 0xFFF7FFBB, 0xDE7B7FF7 +}; + +static const u32 tuning_block_128[] = { + 0xFF00FFFF, 0x0000FFFF, 0xCCCCFFFF, 0xCCCC33CC, + 0xCC3333CC, 0xFFFFCCCC, 0xFFFFEEFF, 0xFFEEEEFF, + 0xFFDDFFFF, 0xDDDDFFFF, 0xBBFFFFFF, 0xBBFFFFFF, + 0xFFFFFFBB, 0xFFFFFF77, 0x77FF7777, 0xFFEEDDBB, + 0x00FFFFFF, 0x00FFFFFF, 0xCCFFFF00, 0xCC33CCCC, + 0x3333CCCC, 0xFFCCCCCC, 0xFFEEFFFF, 0xEEEEFFFF, + 0xDDFFFFFF, 0xDDFFFFFF, 0xFFFFFFDD, 0xFFFFFFBB, + 0xFFFFBBBB, 0xFFFF77FF, 0xFF7777FF, 0xEEDDBB77 +}; + +/* global to hold each slot instance for debug */ +static struct sdhci_msm_host *sdhci_slot[2]; + +static int disable_slots; +/* root can write, others read */ +module_param(disable_slots, int, S_IRUGO|S_IWUSR); + +static bool nocmdq; +module_param(nocmdq, bool, S_IRUGO|S_IWUSR); + +enum vdd_io_level { + /* set vdd_io_data->low_vol_level */ + VDD_IO_LOW, + /* set vdd_io_data->high_vol_level */ + VDD_IO_HIGH, + /* + * set whatever there in voltage_level (third argument) of + * sdhci_msm_set_vdd_io_vol() function. + */ + VDD_IO_SET_LEVEL, +}; + +/* MSM platform specific tuning */ +static inline int msm_dll_poll_ck_out_en(struct sdhci_host *host, + u8 poll) +{ + int rc = 0; u32 wait_cnt = 50; - u8 ck_out_en; + u8 ck_out_en = 0; struct mmc_host *mmc = host->mmc; + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); + struct sdhci_msm_host *msm_host = pltfm_host->priv; + const struct sdhci_msm_offset *msm_host_offset = + msm_host->offset; - /* Poll for CK_OUT_EN bit. max. poll time = 50us */ - ck_out_en = !!(readl_relaxed(host->ioaddr + CORE_DLL_CONFIG) & - CORE_CK_OUT_EN); + /* poll for CK_OUT_EN bit. max. poll time = 50us */ + ck_out_en = !!(readl_relaxed(host->ioaddr + + msm_host_offset->CORE_DLL_CONFIG) & CORE_CK_OUT_EN); while (ck_out_en != poll) { if (--wait_cnt == 0) { - dev_err(mmc_dev(mmc), "%s: CK_OUT_EN bit is not %d\n", - mmc_hostname(mmc), poll); - return -ETIMEDOUT; + pr_err("%s: %s: CK_OUT_EN bit is not %d\n", + mmc_hostname(mmc), __func__, poll); + rc = -ETIMEDOUT; + goto out; } udelay(1); - ck_out_en = !!(readl_relaxed(host->ioaddr + CORE_DLL_CONFIG) & - CORE_CK_OUT_EN); + ck_out_en = !!(readl_relaxed(host->ioaddr + + msm_host_offset->CORE_DLL_CONFIG) & CORE_CK_OUT_EN); + } +out: + return rc; } +/* + * Enable CDR to track changes of DAT lines and adjust sampling + * point according to voltage/temperature variations + */ +static int msm_enable_cdr_cm_sdc4_dll(struct sdhci_host *host) +{ + int rc = 0; + u32 config; + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); + struct sdhci_msm_host *msm_host = pltfm_host->priv; + const struct sdhci_msm_offset *msm_host_offset = + msm_host->offset; + + config = readl_relaxed(host->ioaddr + + msm_host_offset->CORE_DLL_CONFIG); + config |= CORE_CDR_EN; + config &= ~(CORE_CDR_EXT_EN | CORE_CK_OUT_EN); + writel_relaxed(config, host->ioaddr + + msm_host_offset->CORE_DLL_CONFIG); + + rc = msm_dll_poll_ck_out_en(host, 0); + if (rc) + goto err; + + writel_relaxed((readl_relaxed(host->ioaddr + + msm_host_offset->CORE_DLL_CONFIG) | CORE_CK_OUT_EN), + host->ioaddr + msm_host_offset->CORE_DLL_CONFIG); + + rc = msm_dll_poll_ck_out_en(host, 1); + if (rc) + goto err; + goto out; +err: + pr_err("%s: %s: failed\n", mmc_hostname(host->mmc), __func__); +out: + return rc; +} + +static ssize_t store_auto_cmd21(struct device *dev, struct device_attribute + *attr, const char *buf, size_t count) +{ + struct sdhci_host *host = dev_get_drvdata(dev); + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); + struct sdhci_msm_host *msm_host = pltfm_host->priv; + u32 tmp; + unsigned long flags; + + if (!kstrtou32(buf, 0, &tmp)) { + spin_lock_irqsave(&host->lock, flags); + msm_host->en_auto_cmd21 = !!tmp; + spin_unlock_irqrestore(&host->lock, flags); + } + return count; +} + +static ssize_t show_auto_cmd21(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct sdhci_host *host = dev_get_drvdata(dev); + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); + struct sdhci_msm_host *msm_host = pltfm_host->priv; + + return snprintf(buf, PAGE_SIZE, "%d\n", msm_host->en_auto_cmd21); +} + +/* MSM auto-tuning handler */ +static int sdhci_msm_config_auto_tuning_cmd(struct sdhci_host *host, + bool enable, + u32 type) +{ + int rc = 0; + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); + struct sdhci_msm_host *msm_host = pltfm_host->priv; + const struct sdhci_msm_offset *msm_host_offset = + msm_host->offset; + u32 val = 0; + + if (!msm_host->en_auto_cmd21) + return 0; + + if (type == MMC_SEND_TUNING_BLOCK_HS200) + val = CORE_HC_AUTO_CMD21_EN; + else return 0; + + if (enable) { + rc = msm_enable_cdr_cm_sdc4_dll(host); + writel_relaxed(readl_relaxed(host->ioaddr + + msm_host_offset->CORE_VENDOR_SPEC) | val, + host->ioaddr + msm_host_offset->CORE_VENDOR_SPEC); + } else { + writel_relaxed(readl_relaxed(host->ioaddr + + msm_host_offset->CORE_VENDOR_SPEC) & ~val, + host->ioaddr + msm_host_offset->CORE_VENDOR_SPEC); + } + return rc; } static int msm_config_cm_dll_phase(struct sdhci_host *host, u8 phase) { - int rc; - static const u8 grey_coded_phase_table[] = { - 0x0, 0x1, 0x3, 0x2, 0x6, 0x7, 0x5, 0x4, - 0xc, 0xd, 0xf, 0xe, 0xa, 0xb, 0x9, 0x8 - }; + int rc = 0; + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); + struct sdhci_msm_host *msm_host = pltfm_host->priv; + const struct sdhci_msm_offset *msm_host_offset = + msm_host->offset; + u8 grey_coded_phase_table[] = {0x0, 0x1, 0x3, 0x2, 0x6, 0x7, 0x5, 0x4, + 0xC, 0xD, 0xF, 0xE, 0xA, 0xB, 0x9, + 0x8}; unsigned long flags; u32 config; struct mmc_host *mmc = host->mmc; + pr_debug("%s: Enter %s\n", mmc_hostname(mmc), __func__); spin_lock_irqsave(&host->lock, flags); - config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG); + config = readl_relaxed(host->ioaddr + + msm_host_offset->CORE_DLL_CONFIG); config &= ~(CORE_CDR_EN | CORE_CK_OUT_EN); config |= (CORE_CDR_EXT_EN | CORE_DLL_EN); - writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG); + writel_relaxed(config, host->ioaddr + + msm_host_offset->CORE_DLL_CONFIG); /* Wait until CK_OUT_EN bit of DLL_CONFIG register becomes '0' */ rc = msm_dll_poll_ck_out_en(host, 0); @@ -116,31 +518,36 @@ * Write the selected DLL clock output phase (0 ... 15) * to CDR_SELEXT bit field of DLL_CONFIG register. */ - config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG); - config &= ~CDR_SELEXT_MASK; - config |= grey_coded_phase_table[phase] << CDR_SELEXT_SHIFT; - writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG); + writel_relaxed(((readl_relaxed(host->ioaddr + + msm_host_offset->CORE_DLL_CONFIG) + & ~(0xF << 20)) + | (grey_coded_phase_table[phase] << 20)), + host->ioaddr + msm_host_offset->CORE_DLL_CONFIG); /* Set CK_OUT_EN bit of DLL_CONFIG register to 1. */ - writel_relaxed((readl_relaxed(host->ioaddr + CORE_DLL_CONFIG) - | CORE_CK_OUT_EN), host->ioaddr + CORE_DLL_CONFIG); + writel_relaxed((readl_relaxed(host->ioaddr + + msm_host_offset->CORE_DLL_CONFIG) | CORE_CK_OUT_EN), + host->ioaddr + msm_host_offset->CORE_DLL_CONFIG); /* Wait until CK_OUT_EN bit of DLL_CONFIG register becomes '1' */ rc = msm_dll_poll_ck_out_en(host, 1); if (rc) goto err_out; - config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG); + config = readl_relaxed(host->ioaddr + + msm_host_offset->CORE_DLL_CONFIG); config |= CORE_CDR_EN; config &= ~CORE_CDR_EXT_EN; - writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG); + writel_relaxed(config, host->ioaddr + + msm_host_offset->CORE_DLL_CONFIG); goto out; err_out: - dev_err(mmc_dev(mmc), "%s: Failed to set DLL phase: %d\n", - mmc_hostname(mmc), phase); + pr_err("%s: %s: Failed to set DLL phase: %d\n", + mmc_hostname(mmc), __func__, phase); out: spin_unlock_irqrestore(&host->lock, flags); + pr_debug("%s: Exit %s\n", mmc_hostname(mmc), __func__); return rc; } @@ -148,8 +555,8 @@ * Find out the greatest range of consecuitive selected * DLL clock output phases that can be used as sampling * setting for SD3.0 UHS-I card read operation (in SDR104 - * timing mode) or for eMMC4.5 card read operation (in HS200 - * timing mode). + * timing mode) or for eMMC4.5 card read operation (in + * HS400/HS200 timing mode). * Select the 3/4 of the range and configure the DLL with the * selected DLL clock output phase. */ @@ -165,9 +572,10 @@ bool phase_0_found = false, phase_15_found = false; struct mmc_host *mmc = host->mmc; + pr_debug("%s: Enter %s\n", mmc_hostname(mmc), __func__); if (!total_phases || (total_phases > MAX_PHASES)) { - dev_err(mmc_dev(mmc), "%s: Invalid argument: total_phases=%d\n", - mmc_hostname(mmc), total_phases); + pr_err("%s: %s: invalid argument: total_phases=%d\n", + mmc_hostname(mmc), __func__, total_phases); return -EINVAL; } @@ -241,24 +649,29 @@ } } - i = (curr_max * 3) / 4; + i = ((curr_max * 3) / 4); if (i) i--; - ret = ranges[selected_row_index][i]; + ret = (int)ranges[selected_row_index][i]; if (ret >= MAX_PHASES) { ret = -EINVAL; - dev_err(mmc_dev(mmc), "%s: Invalid phase selected=%d\n", - mmc_hostname(mmc), ret); + pr_err("%s: %s: invalid phase selected=%d\n", + mmc_hostname(mmc), __func__, ret); } + pr_debug("%s: Exit %s\n", mmc_hostname(mmc), __func__); return ret; } static inline void msm_cm_dll_set_freq(struct sdhci_host *host) { - u32 mclk_freq = 0, config; + u32 mclk_freq = 0; + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); + struct sdhci_msm_host *msm_host = pltfm_host->priv; + const struct sdhci_msm_offset *msm_host_offset = + msm_host->offset; /* Program the MCLK value to MCLK_FREQ bit field */ if (host->clock <= 112000000) @@ -278,117 +691,639 @@ else if (host->clock <= 200000000) mclk_freq = 7; - config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG); - config &= ~CMUX_SHIFT_PHASE_MASK; - config |= mclk_freq << CMUX_SHIFT_PHASE_SHIFT; - writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG); + writel_relaxed(((readl_relaxed(host->ioaddr + + msm_host_offset->CORE_DLL_CONFIG) + & ~(7 << 24)) | (mclk_freq << 24)), + host->ioaddr + msm_host_offset->CORE_DLL_CONFIG); } /* Initialize the DLL (Programmable Delay Line) */ static int msm_init_cm_dll(struct sdhci_host *host) { + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); + struct sdhci_msm_host *msm_host = pltfm_host->priv; + const struct sdhci_msm_offset *msm_host_offset = + msm_host->offset; struct mmc_host *mmc = host->mmc; - int wait_cnt = 50; + int rc = 0; unsigned long flags; + u32 wait_cnt; + bool prev_pwrsave, curr_pwrsave; + pr_debug("%s: Enter %s\n", mmc_hostname(mmc), __func__); spin_lock_irqsave(&host->lock, flags); - + prev_pwrsave = !!(readl_relaxed(host->ioaddr + + msm_host_offset->CORE_VENDOR_SPEC) & CORE_CLK_PWRSAVE); + curr_pwrsave = prev_pwrsave; /* * Make sure that clock is always enabled when DLL * tuning is in progress. Keeping PWRSAVE ON may - * turn off the clock. + * turn off the clock. So let's disable the PWRSAVE + * here and re-enable it once tuning is completed. */ - writel_relaxed((readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC) - & ~CORE_CLK_PWRSAVE), host->ioaddr + CORE_VENDOR_SPEC); + if (prev_pwrsave) { + writel_relaxed((readl_relaxed(host->ioaddr + + msm_host_offset->CORE_VENDOR_SPEC) + & ~CORE_CLK_PWRSAVE), host->ioaddr + + msm_host_offset->CORE_VENDOR_SPEC); + curr_pwrsave = false; + } + + if (msm_host->use_updated_dll_reset) { + /* Disable the DLL clock */ + writel_relaxed((readl_relaxed(host->ioaddr + + msm_host_offset->CORE_DLL_CONFIG) + & ~CORE_CK_OUT_EN), host->ioaddr + + msm_host_offset->CORE_DLL_CONFIG); + + writel_relaxed((readl_relaxed(host->ioaddr + + msm_host_offset->CORE_DLL_CONFIG_2) + | CORE_DLL_CLOCK_DISABLE), host->ioaddr + + msm_host_offset->CORE_DLL_CONFIG_2); + } /* Write 1 to DLL_RST bit of DLL_CONFIG register */ - writel_relaxed((readl_relaxed(host->ioaddr + CORE_DLL_CONFIG) - | CORE_DLL_RST), host->ioaddr + CORE_DLL_CONFIG); + writel_relaxed((readl_relaxed(host->ioaddr + + msm_host_offset->CORE_DLL_CONFIG) | CORE_DLL_RST), + host->ioaddr + msm_host_offset->CORE_DLL_CONFIG); /* Write 1 to DLL_PDN bit of DLL_CONFIG register */ - writel_relaxed((readl_relaxed(host->ioaddr + CORE_DLL_CONFIG) - | CORE_DLL_PDN), host->ioaddr + CORE_DLL_CONFIG); + writel_relaxed((readl_relaxed(host->ioaddr + + msm_host_offset->CORE_DLL_CONFIG) | CORE_DLL_PDN), + host->ioaddr + msm_host_offset->CORE_DLL_CONFIG); msm_cm_dll_set_freq(host); + if (msm_host->use_updated_dll_reset) { + u32 mclk_freq = 0; + + if ((readl_relaxed(host->ioaddr + + msm_host_offset->CORE_DLL_CONFIG_2) + & CORE_FLL_CYCLE_CNT)) + mclk_freq = (u32) ((host->clock / TCXO_FREQ) * 8); + else + mclk_freq = (u32) ((host->clock / TCXO_FREQ) * 4); + + writel_relaxed(((readl_relaxed(host->ioaddr + + msm_host_offset->CORE_DLL_CONFIG_2) + & ~(0xFF << 10)) | (mclk_freq << 10)), + host->ioaddr + msm_host_offset->CORE_DLL_CONFIG_2); + /* wait for 5us before enabling DLL clock */ + udelay(5); + } + /* Write 0 to DLL_RST bit of DLL_CONFIG register */ - writel_relaxed((readl_relaxed(host->ioaddr + CORE_DLL_CONFIG) - & ~CORE_DLL_RST), host->ioaddr + CORE_DLL_CONFIG); + writel_relaxed((readl_relaxed(host->ioaddr + + msm_host_offset->CORE_DLL_CONFIG) & ~CORE_DLL_RST), + host->ioaddr + msm_host_offset->CORE_DLL_CONFIG); /* Write 0 to DLL_PDN bit of DLL_CONFIG register */ - writel_relaxed((readl_relaxed(host->ioaddr + CORE_DLL_CONFIG) - & ~CORE_DLL_PDN), host->ioaddr + CORE_DLL_CONFIG); + writel_relaxed((readl_relaxed(host->ioaddr + + msm_host_offset->CORE_DLL_CONFIG) & ~CORE_DLL_PDN), + host->ioaddr + msm_host_offset->CORE_DLL_CONFIG); + + if (msm_host->use_updated_dll_reset) { + msm_cm_dll_set_freq(host); + /* Enable the DLL clock */ + writel_relaxed((readl_relaxed(host->ioaddr + + msm_host_offset->CORE_DLL_CONFIG_2) + & ~CORE_DLL_CLOCK_DISABLE), host->ioaddr + + msm_host_offset->CORE_DLL_CONFIG_2); + } /* Set DLL_EN bit to 1. */ - writel_relaxed((readl_relaxed(host->ioaddr + CORE_DLL_CONFIG) - | CORE_DLL_EN), host->ioaddr + CORE_DLL_CONFIG); + writel_relaxed((readl_relaxed(host->ioaddr + + msm_host_offset->CORE_DLL_CONFIG) | CORE_DLL_EN), + host->ioaddr + msm_host_offset->CORE_DLL_CONFIG); /* Set CK_OUT_EN bit to 1. */ - writel_relaxed((readl_relaxed(host->ioaddr + CORE_DLL_CONFIG) - | CORE_CK_OUT_EN), host->ioaddr + CORE_DLL_CONFIG); + writel_relaxed((readl_relaxed(host->ioaddr + + msm_host_offset->CORE_DLL_CONFIG) + | CORE_CK_OUT_EN), host->ioaddr + + msm_host_offset->CORE_DLL_CONFIG); + wait_cnt = 50; /* Wait until DLL_LOCK bit of DLL_STATUS register becomes '1' */ - while (!(readl_relaxed(host->ioaddr + CORE_DLL_STATUS) & - CORE_DLL_LOCK)) { + while (!(readl_relaxed(host->ioaddr + + msm_host_offset->CORE_DLL_STATUS) & CORE_DLL_LOCK)) { /* max. wait for 50us sec for LOCK bit to be set */ if (--wait_cnt == 0) { - dev_err(mmc_dev(mmc), "%s: DLL failed to LOCK\n", - mmc_hostname(mmc)); - spin_unlock_irqrestore(&host->lock, flags); - return -ETIMEDOUT; + pr_err("%s: %s: DLL failed to LOCK\n", + mmc_hostname(mmc), __func__); + rc = -ETIMEDOUT; + goto out; } + /* wait for 1us before polling again */ udelay(1); } +out: + /* Restore the correct PWRSAVE state */ + if (prev_pwrsave ^ curr_pwrsave) { + u32 reg = readl_relaxed(host->ioaddr + + msm_host_offset->CORE_VENDOR_SPEC); + + if (prev_pwrsave) + reg |= CORE_CLK_PWRSAVE; + else + reg &= ~CORE_CLK_PWRSAVE; + + writel_relaxed(reg, host->ioaddr + + msm_host_offset->CORE_VENDOR_SPEC); + } + spin_unlock_irqrestore(&host->lock, flags); + pr_debug("%s: Exit %s\n", mmc_hostname(mmc), __func__); + return rc; +} + +static int sdhci_msm_cdclp533_calibration(struct sdhci_host *host) +{ + u32 calib_done; + int ret = 0; + int cdc_err = 0; + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); + struct sdhci_msm_host *msm_host = pltfm_host->priv; + const struct sdhci_msm_offset *msm_host_offset = + msm_host->offset; + + pr_debug("%s: Enter %s\n", mmc_hostname(host->mmc), __func__); + + /* Write 0 to CDC_T4_DLY_SEL field in VENDOR_SPEC_DDR200_CFG */ + writel_relaxed((readl_relaxed(host->ioaddr + + msm_host_offset->CORE_DDR_200_CFG) + & ~CORE_CDC_T4_DLY_SEL), + host->ioaddr + msm_host_offset->CORE_DDR_200_CFG); + + /* Write 0 to CDC_SWITCH_BYPASS_OFF field in CORE_CSR_CDC_GEN_CFG */ + writel_relaxed((readl_relaxed(host->ioaddr + CORE_CSR_CDC_GEN_CFG) + & ~CORE_CDC_SWITCH_BYPASS_OFF), + host->ioaddr + CORE_CSR_CDC_GEN_CFG); + + /* Write 1 to CDC_SWITCH_RC_EN field in CORE_CSR_CDC_GEN_CFG */ + writel_relaxed((readl_relaxed(host->ioaddr + CORE_CSR_CDC_GEN_CFG) + | CORE_CDC_SWITCH_RC_EN), + host->ioaddr + CORE_CSR_CDC_GEN_CFG); + + /* Write 0 to START_CDC_TRAFFIC field in CORE_DDR200_CFG */ + writel_relaxed((readl_relaxed(host->ioaddr + + msm_host_offset->CORE_DDR_200_CFG) + & ~CORE_START_CDC_TRAFFIC), + host->ioaddr + msm_host_offset->CORE_DDR_200_CFG); + + /* + * Perform CDC Register Initialization Sequence + * + * CORE_CSR_CDC_CTLR_CFG0 0x11800EC + * CORE_CSR_CDC_CTLR_CFG1 0x3011111 + * CORE_CSR_CDC_CAL_TIMER_CFG0 0x1201000 + * CORE_CSR_CDC_CAL_TIMER_CFG1 0x4 + * CORE_CSR_CDC_REFCOUNT_CFG 0xCB732020 + * CORE_CSR_CDC_COARSE_CAL_CFG 0xB19 + * CORE_CSR_CDC_DELAY_CFG 0x3AC + * CORE_CDC_OFFSET_CFG 0x0 + * CORE_CDC_SLAVE_DDA_CFG 0x16334 + */ + + writel_relaxed(0x11800EC, host->ioaddr + CORE_CSR_CDC_CTLR_CFG0); + writel_relaxed(0x3011111, host->ioaddr + CORE_CSR_CDC_CTLR_CFG1); + writel_relaxed(0x1201000, host->ioaddr + CORE_CSR_CDC_CAL_TIMER_CFG0); + writel_relaxed(0x4, host->ioaddr + CORE_CSR_CDC_CAL_TIMER_CFG1); + writel_relaxed(0xCB732020, host->ioaddr + CORE_CSR_CDC_REFCOUNT_CFG); + writel_relaxed(0xB19, host->ioaddr + CORE_CSR_CDC_COARSE_CAL_CFG); + writel_relaxed(0x4E2, host->ioaddr + CORE_CSR_CDC_DELAY_CFG); + writel_relaxed(0x0, host->ioaddr + CORE_CDC_OFFSET_CFG); + writel_relaxed(0x16334, host->ioaddr + CORE_CDC_SLAVE_DDA_CFG); + + /* CDC HW Calibration */ + + /* Write 1 to SW_TRIG_FULL_CALIB field in CORE_CSR_CDC_CTLR_CFG0 */ + writel_relaxed((readl_relaxed(host->ioaddr + CORE_CSR_CDC_CTLR_CFG0) + | CORE_SW_TRIG_FULL_CALIB), + host->ioaddr + CORE_CSR_CDC_CTLR_CFG0); + + /* Write 0 to SW_TRIG_FULL_CALIB field in CORE_CSR_CDC_CTLR_CFG0 */ + writel_relaxed((readl_relaxed(host->ioaddr + CORE_CSR_CDC_CTLR_CFG0) + & ~CORE_SW_TRIG_FULL_CALIB), + host->ioaddr + CORE_CSR_CDC_CTLR_CFG0); + + /* Write 1 to HW_AUTOCAL_ENA field in CORE_CSR_CDC_CTLR_CFG0 */ + writel_relaxed((readl_relaxed(host->ioaddr + CORE_CSR_CDC_CTLR_CFG0) + | CORE_HW_AUTOCAL_ENA), + host->ioaddr + CORE_CSR_CDC_CTLR_CFG0); + + /* Write 1 to TIMER_ENA field in CORE_CSR_CDC_CAL_TIMER_CFG0 */ + writel_relaxed((readl_relaxed(host->ioaddr + + CORE_CSR_CDC_CAL_TIMER_CFG0) | CORE_TIMER_ENA), + host->ioaddr + CORE_CSR_CDC_CAL_TIMER_CFG0); + + mb(); + + /* Poll on CALIBRATION_DONE field in CORE_CSR_CDC_STATUS0 to be 1 */ + ret = readl_poll_timeout(host->ioaddr + CORE_CSR_CDC_STATUS0, + calib_done, (calib_done & CORE_CALIBRATION_DONE), 1, 50); + + if (ret == -ETIMEDOUT) { + pr_err("%s: %s: CDC Calibration was not completed\n", + mmc_hostname(host->mmc), __func__); + goto out; + } + + /* Verify CDC_ERROR_CODE field in CORE_CSR_CDC_STATUS0 is 0 */ + cdc_err = readl_relaxed(host->ioaddr + CORE_CSR_CDC_STATUS0) + & CORE_CDC_ERROR_CODE_MASK; + if (cdc_err) { + pr_err("%s: %s: CDC Error Code %d\n", + mmc_hostname(host->mmc), __func__, cdc_err); + ret = -EINVAL; + goto out; + } + + /* Write 1 to START_CDC_TRAFFIC field in CORE_DDR200_CFG */ + writel_relaxed((readl_relaxed(host->ioaddr + + msm_host_offset->CORE_DDR_200_CFG) + | CORE_START_CDC_TRAFFIC), + host->ioaddr + msm_host_offset->CORE_DDR_200_CFG); +out: + pr_debug("%s: Exit %s, ret:%d\n", mmc_hostname(host->mmc), + __func__, ret); + return ret; +} + +static int sdhci_msm_cm_dll_sdc4_calibration(struct sdhci_host *host) +{ + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); + struct sdhci_msm_host *msm_host = pltfm_host->priv; + const struct sdhci_msm_offset *msm_host_offset = + msm_host->offset; + u32 dll_status, ddr_config; + int ret = 0; + + pr_debug("%s: Enter %s\n", mmc_hostname(host->mmc), __func__); + + /* + * Reprogramming the value in case it might have been modified by + * bootloaders. + */ + if (msm_host->rclk_delay_fix) { + writel_relaxed(DDR_CONFIG_2_POR_VAL, host->ioaddr + + msm_host_offset->CORE_DDR_CONFIG_2); + } else { + ddr_config = DDR_CONFIG_POR_VAL & + ~DDR_CONFIG_PRG_RCLK_DLY_MASK; + ddr_config |= DDR_CONFIG_PRG_RCLK_DLY; + writel_relaxed(ddr_config, host->ioaddr + + msm_host_offset->CORE_DDR_CONFIG); + } + + if (msm_host->enhanced_strobe && mmc_card_strobe(msm_host->mmc->card)) + writel_relaxed((readl_relaxed(host->ioaddr + + msm_host_offset->CORE_DDR_200_CFG) + | CORE_CMDIN_RCLK_EN), host->ioaddr + + msm_host_offset->CORE_DDR_200_CFG); + + /* Write 1 to DDR_CAL_EN field in CORE_DLL_CONFIG_2 */ + writel_relaxed((readl_relaxed(host->ioaddr + + msm_host_offset->CORE_DLL_CONFIG_2) + | CORE_DDR_CAL_EN), + host->ioaddr + msm_host_offset->CORE_DLL_CONFIG_2); + + /* Poll on DDR_DLL_LOCK bit in CORE_DLL_STATUS to be set */ + ret = readl_poll_timeout(host->ioaddr + + msm_host_offset->CORE_DLL_STATUS, + dll_status, (dll_status & CORE_DDR_DLL_LOCK), 10, 1000); + + if (ret == -ETIMEDOUT) { + pr_err("%s: %s: CM_DLL_SDC4 Calibration was not completed\n", + mmc_hostname(host->mmc), __func__); + goto out; + } + + /* + * set CORE_PWRSAVE_DLL bit in CORE_VENDOR_SPEC3. + * when MCLK is gated OFF, it is not gated for less than 0.5us + * and MCLK must be switched on for at-least 1us before DATA + * starts coming. Controllers with 14lpp tech DLL cannot + * guarantee above requirement. So PWRSAVE_DLL should not be + * turned on for host controllers using this DLL. + */ + if (!msm_host->use_14lpp_dll) + writel_relaxed((readl_relaxed(host->ioaddr + + msm_host_offset->CORE_VENDOR_SPEC3) + | CORE_PWRSAVE_DLL), host->ioaddr + + msm_host_offset->CORE_VENDOR_SPEC3); + mb(); +out: + pr_debug("%s: Exit %s, ret:%d\n", mmc_hostname(host->mmc), + __func__, ret); + return ret; +} + +static int sdhci_msm_enhanced_strobe(struct sdhci_host *host) +{ + int ret = 0; + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); + struct sdhci_msm_host *msm_host = pltfm_host->priv; + struct mmc_host *mmc = host->mmc; + + pr_debug("%s: Enter %s\n", mmc_hostname(host->mmc), __func__); + + if (!msm_host->enhanced_strobe || !mmc_card_strobe(mmc->card)) { + pr_debug("%s: host/card does not support hs400 enhanced strobe\n", + mmc_hostname(mmc)); + return -EINVAL; + } + + if (msm_host->calibration_done || + !(mmc->ios.timing == MMC_TIMING_MMC_HS400)) { return 0; } -static int sdhci_msm_execute_tuning(struct sdhci_host *host, u32 opcode) + /* + * Reset the tuning block. + */ + ret = msm_init_cm_dll(host); + if (ret) + goto out; + + ret = sdhci_msm_cm_dll_sdc4_calibration(host); +out: + if (!ret) + msm_host->calibration_done = true; + pr_debug("%s: Exit %s, ret:%d\n", mmc_hostname(host->mmc), + __func__, ret); + return ret; +} + +static int sdhci_msm_hs400_dll_calibration(struct sdhci_host *host) +{ + int ret = 0; + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); + struct sdhci_msm_host *msm_host = pltfm_host->priv; + const struct sdhci_msm_offset *msm_host_offset = + msm_host->offset; + + pr_debug("%s: Enter %s\n", mmc_hostname(host->mmc), __func__); + + /* + * Retuning in HS400 (DDR mode) will fail, just reset the + * tuning block and restore the saved tuning phase. + */ + ret = msm_init_cm_dll(host); + if (ret) + goto out; + + /* Set the selected phase in delay line hw block */ + ret = msm_config_cm_dll_phase(host, msm_host->saved_tuning_phase); + if (ret) + goto out; + + /* Write 1 to CMD_DAT_TRACK_SEL field in DLL_CONFIG */ + writel_relaxed((readl_relaxed(host->ioaddr + + msm_host_offset->CORE_DLL_CONFIG) + | CORE_CMD_DAT_TRACK_SEL), host->ioaddr + + msm_host_offset->CORE_DLL_CONFIG); + + if (msm_host->use_cdclp533) + /* Calibrate CDCLP533 DLL HW */ + ret = sdhci_msm_cdclp533_calibration(host); + else + /* Calibrate CM_DLL_SDC4 HW */ + ret = sdhci_msm_cm_dll_sdc4_calibration(host); +out: + pr_debug("%s: Exit %s, ret:%d\n", mmc_hostname(host->mmc), + __func__, ret); + return ret; +} + +static void sdhci_msm_set_mmc_drv_type(struct sdhci_host *host, u32 opcode, + u8 drv_type) { + struct mmc_command cmd = {0}; + struct mmc_request mrq = {NULL}; + struct mmc_host *mmc = host->mmc; + u8 val = ((drv_type << 4) | 2); + + cmd.opcode = MMC_SWITCH; + cmd.arg = (MMC_SWITCH_MODE_WRITE_BYTE << 24) | + (EXT_CSD_HS_TIMING << 16) | + (val << 8) | + EXT_CSD_CMD_SET_NORMAL; + cmd.flags = MMC_CMD_AC | MMC_RSP_R1B; + /* 1 sec */ + cmd.busy_timeout = 1000 * 1000; + + memset(cmd.resp, 0, sizeof(cmd.resp)); + cmd.retries = 3; + + mrq.cmd = &cmd; + cmd.data = NULL; + + mmc_wait_for_req(mmc, &mrq); + pr_debug("%s: %s: set card drive type to %d\n", + mmc_hostname(mmc), __func__, + drv_type); +} + +int sdhci_msm_execute_tuning(struct sdhci_host *host, u32 opcode) +{ + unsigned long flags; int tuning_seq_cnt = 3; - u8 phase, tuned_phases[16], tuned_phase_cnt = 0; + u8 phase, *data_buf, tuned_phases[NUM_TUNING_PHASES], tuned_phase_cnt; + const u32 *tuning_block_pattern = tuning_block_64; + int size = sizeof(tuning_block_64); /* Tuning pattern size in bytes */ int rc; struct mmc_host *mmc = host->mmc; struct mmc_ios ios = host->mmc->ios; + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); + struct sdhci_msm_host *msm_host = pltfm_host->priv; + u8 drv_type = 0; + bool drv_type_changed = false; + struct mmc_card *card = host->mmc->card; + int sts_retry; + u8 last_good_phase = 0; /* * Tuning is required for SDR104, HS200 and HS400 cards and * if clock frequency is greater than 100MHz in these modes. */ - if (host->clock <= 100 * 1000 * 1000 || - !((ios.timing == MMC_TIMING_MMC_HS200) || + if (host->clock <= CORE_FREQ_100MHZ || + !((ios.timing == MMC_TIMING_MMC_HS400) || + (ios.timing == MMC_TIMING_MMC_HS200) || (ios.timing == MMC_TIMING_UHS_SDR104))) return 0; + /* + * Don't allow re-tuning for CRC errors observed for any commands + * that are sent during tuning sequence itself. + */ + if (msm_host->tuning_in_progress) + return 0; + msm_host->tuning_in_progress = true; + pr_debug("%s: Enter %s\n", mmc_hostname(mmc), __func__); + + /* CDC/SDC4 DLL HW calibration is only required for HS400 mode*/ + if (msm_host->tuning_done && !msm_host->calibration_done && + (mmc->ios.timing == MMC_TIMING_MMC_HS400)) { + rc = sdhci_msm_hs400_dll_calibration(host); + spin_lock_irqsave(&host->lock, flags); + if (!rc) + msm_host->calibration_done = true; + spin_unlock_irqrestore(&host->lock, flags); + goto out; + } + + spin_lock_irqsave(&host->lock, flags); + + if ((opcode == MMC_SEND_TUNING_BLOCK_HS200) && + (mmc->ios.bus_width == MMC_BUS_WIDTH_8)) { + tuning_block_pattern = tuning_block_128; + size = sizeof(tuning_block_128); + } + spin_unlock_irqrestore(&host->lock, flags); + + data_buf = kmalloc(size, GFP_KERNEL); + if (!data_buf) { + rc = -ENOMEM; + goto out; + } + retry: - /* First of all reset the tuning block */ + tuned_phase_cnt = 0; + + /* first of all reset the tuning block */ rc = msm_init_cm_dll(host); if (rc) - return rc; + goto kfree; phase = 0; do { - /* Set the phase in delay line hw block */ + struct mmc_command cmd = {0}; + struct mmc_data data = {0}; + struct mmc_request mrq = { + .cmd = &cmd, + .data = &data + }; + struct scatterlist sg; + struct mmc_command sts_cmd = {0}; + + /* set the phase in delay line hw block */ rc = msm_config_cm_dll_phase(host, phase); if (rc) - return rc; + goto kfree; + + cmd.opcode = opcode; + cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC; + + data.blksz = size; + data.blocks = 1; + data.flags = MMC_DATA_READ; + data.timeout_ns = 1000 * 1000 * 1000; /* 1 sec */ + + data.sg = &sg; + data.sg_len = 1; + sg_init_one(&sg, data_buf, size); + memset(data_buf, 0, size); + mmc_wait_for_req(mmc, &mrq); + + if (card && (cmd.error || data.error)) { + /* + * Set the dll to last known good phase while sending + * status command to ensure that status command won't + * fail due to bad phase. + */ + if (tuned_phase_cnt) + last_good_phase = + tuned_phases[tuned_phase_cnt-1]; + else if (msm_host->saved_tuning_phase != + INVALID_TUNING_PHASE) + last_good_phase = msm_host->saved_tuning_phase; + + rc = msm_config_cm_dll_phase(host, last_good_phase); + if (rc) + goto kfree; + + sts_cmd.opcode = MMC_SEND_STATUS; + sts_cmd.arg = card->rca << 16; + sts_cmd.flags = MMC_RSP_R1 | MMC_CMD_AC; + sts_retry = 5; + while (sts_retry) { + mmc_wait_for_cmd(mmc, &sts_cmd, 0); + + if (sts_cmd.error || + (R1_CURRENT_STATE(sts_cmd.resp[0]) + != R1_STATE_TRAN)) { + sts_retry--; + /* + * wait for at least 146 MCLK cycles for + * the card to move to TRANS state. As + * the MCLK would be min 200MHz for + * tuning, we need max 0.73us delay. To + * be on safer side 1ms delay is given. + */ + usleep_range(1000, 1200); + pr_debug("%s: phase %d sts cmd err %d resp 0x%x\n", + mmc_hostname(mmc), phase, + sts_cmd.error, sts_cmd.resp[0]); + continue; + } + break; + }; + } - rc = mmc_send_tuning(mmc, opcode, NULL); - if (!rc) { - /* Tuning is successful at this tuning point */ + if (!cmd.error && !data.error && + !memcmp(data_buf, tuning_block_pattern, size)) { + /* tuning is successful at this tuning point */ tuned_phases[tuned_phase_cnt++] = phase; - dev_dbg(mmc_dev(mmc), "%s: Found good phase = %d\n", - mmc_hostname(mmc), phase); + pr_debug("%s: %s: found *** good *** phase = %d\n", + mmc_hostname(mmc), __func__, phase); + } else { + pr_debug("%s: %s: found ## bad ## phase = %d\n", + mmc_hostname(mmc), __func__, phase); } - } while (++phase < ARRAY_SIZE(tuned_phases)); + } while (++phase < 16); + + if ((tuned_phase_cnt == NUM_TUNING_PHASES) && + card && mmc_card_mmc(card)) { + /* + * If all phases pass then its a problem. So change the card's + * drive type to a different value, if supported and repeat + * tuning until at least one phase fails. Then set the original + * drive type back. + * + * If all the phases still pass after trying all possible + * drive types, then one of those 16 phases will be picked. + * This is no different from what was going on before the + * modification to change drive type and retune. + */ + pr_debug("%s: tuned phases count: %d\n", mmc_hostname(mmc), + tuned_phase_cnt); + + /* set drive type to other value . default setting is 0x0 */ + while (++drv_type <= MAX_DRV_TYPES_SUPPORTED_HS200) { + pr_debug("%s: trying different drive strength (%d)\n", + mmc_hostname(mmc), drv_type); + if (card->ext_csd.raw_driver_strength & + (1 << drv_type)) { + sdhci_msm_set_mmc_drv_type(host, opcode, + drv_type); + if (!drv_type_changed) + drv_type_changed = true; + goto retry; + } + } + } + + /* reset drive type to default (50 ohm) if changed */ + if (drv_type_changed) + sdhci_msm_set_mmc_drv_type(host, opcode, 0); if (tuned_phase_cnt) { rc = msm_find_most_appropriate_phase(host, tuned_phases, tuned_phase_cnt); if (rc < 0) - return rc; + goto kfree; else - phase = rc; + phase = (u8)rc; /* * Finally set the selected phase in delay @@ -396,70 +1331,3025 @@ */ rc = msm_config_cm_dll_phase(host, phase); if (rc) - return rc; - dev_dbg(mmc_dev(mmc), "%s: Setting the tuning phase to %d\n", - mmc_hostname(mmc), phase); + goto kfree; + msm_host->saved_tuning_phase = phase; + pr_debug("%s: %s: finally setting the tuning phase to %d\n", + mmc_hostname(mmc), __func__, phase); } else { if (--tuning_seq_cnt) goto retry; - /* Tuning failed */ - dev_dbg(mmc_dev(mmc), "%s: No tuning point found\n", - mmc_hostname(mmc)); + /* tuning failed */ + pr_err("%s: %s: no tuning point found\n", + mmc_hostname(mmc), __func__); rc = -EIO; } +kfree: + kfree(data_buf); +out: + spin_lock_irqsave(&host->lock, flags); + if (!rc) + msm_host->tuning_done = true; + spin_unlock_irqrestore(&host->lock, flags); + msm_host->tuning_in_progress = false; + pr_debug("%s: Exit %s, err(%d)\n", mmc_hostname(mmc), __func__, rc); return rc; } -static const struct of_device_id sdhci_msm_dt_match[] = { - { .compatible = "qcom,sdhci-msm-v4" }, - {}, -}; +static int sdhci_msm_setup_gpio(struct sdhci_msm_pltfm_data *pdata, bool enable) +{ + struct sdhci_msm_gpio_data *curr; + int i, ret = 0; -MODULE_DEVICE_TABLE(of, sdhci_msm_dt_match); + curr = pdata->pin_data->gpio_data; + for (i = 0; i < curr->size; i++) { + if (!gpio_is_valid(curr->gpio[i].no)) { + ret = -EINVAL; + pr_err("%s: Invalid gpio = %d\n", __func__, + curr->gpio[i].no); + goto free_gpios; + } + if (enable) { + ret = gpio_request(curr->gpio[i].no, + curr->gpio[i].name); + if (ret) { + pr_err("%s: gpio_request(%d, %s) failed %d\n", + __func__, curr->gpio[i].no, + curr->gpio[i].name, ret); + goto free_gpios; + } + curr->gpio[i].is_enabled = true; + } else { + gpio_free(curr->gpio[i].no); + curr->gpio[i].is_enabled = false; + } + } + return ret; + +free_gpios: + for (i--; i >= 0; i--) { + gpio_free(curr->gpio[i].no); + curr->gpio[i].is_enabled = false; + } + return ret; +} + +static int sdhci_msm_setup_pinctrl(struct sdhci_msm_pltfm_data *pdata, + bool enable) +{ + int ret = 0; + + if (enable) + ret = pinctrl_select_state(pdata->pctrl_data->pctrl, + pdata->pctrl_data->pins_active); + else + ret = pinctrl_select_state(pdata->pctrl_data->pctrl, + pdata->pctrl_data->pins_sleep); + + if (ret < 0) + pr_err("%s state for pinctrl failed with %d\n", + enable ? "Enabling" : "Disabling", ret); + + return ret; +} + +static int sdhci_msm_setup_pins(struct sdhci_msm_pltfm_data *pdata, bool enable) +{ + int ret = 0; + + if (pdata->pin_cfg_sts == enable) { + return 0; + } else if (pdata->pctrl_data) { + ret = sdhci_msm_setup_pinctrl(pdata, enable); + goto out; + } else if (!pdata->pin_data) { + return 0; + } + if (pdata->pin_data->is_gpio) + ret = sdhci_msm_setup_gpio(pdata, enable); +out: + if (!ret) + pdata->pin_cfg_sts = enable; + + return ret; +} + +static int sdhci_msm_dt_get_array(struct device *dev, const char *prop_name, + u32 **out, int *len, u32 size) +{ + int ret = 0; + struct device_node *np = dev->of_node; + size_t sz; + u32 *arr = NULL; + + if (!of_get_property(np, prop_name, len)) { + ret = -EINVAL; + goto out; + } + sz = *len = *len / sizeof(*arr); + if (sz <= 0 || (size > 0 && (sz > size))) { + dev_err(dev, "%s invalid size\n", prop_name); + ret = -EINVAL; + goto out; + } + + arr = devm_kzalloc(dev, sz * sizeof(*arr), GFP_KERNEL); + if (!arr) { + dev_err(dev, "%s failed allocating memory\n", prop_name); + ret = -ENOMEM; + goto out; + } + + ret = of_property_read_u32_array(np, prop_name, arr, sz); + if (ret < 0) { + dev_err(dev, "%s failed reading array %d\n", prop_name, ret); + goto out; + } + *out = arr; +out: + if (ret) + *len = 0; + return ret; +} + +#define MAX_PROP_SIZE 32 +static int sdhci_msm_dt_parse_vreg_info(struct device *dev, + struct sdhci_msm_reg_data **vreg_data, const char *vreg_name) +{ + int len, ret = 0; + const __be32 *prop; + char prop_name[MAX_PROP_SIZE]; + struct sdhci_msm_reg_data *vreg; + struct device_node *np = dev->of_node; + + snprintf(prop_name, MAX_PROP_SIZE, "%s-supply", vreg_name); + if (!of_parse_phandle(np, prop_name, 0)) { + dev_info(dev, "No vreg data found for %s\n", vreg_name); + return ret; + } + + vreg = devm_kzalloc(dev, sizeof(*vreg), GFP_KERNEL); + if (!vreg) { + dev_err(dev, "No memory for vreg: %s\n", vreg_name); + ret = -ENOMEM; + return ret; + } + + vreg->name = vreg_name; + + snprintf(prop_name, MAX_PROP_SIZE, + "qcom,%s-always-on", vreg_name); + if (of_get_property(np, prop_name, NULL)) + vreg->is_always_on = true; + + snprintf(prop_name, MAX_PROP_SIZE, + "qcom,%s-lpm-sup", vreg_name); + if (of_get_property(np, prop_name, NULL)) + vreg->lpm_sup = true; + + snprintf(prop_name, MAX_PROP_SIZE, + "qcom,%s-voltage-level", vreg_name); + prop = of_get_property(np, prop_name, &len); + if (!prop || (len != (2 * sizeof(__be32)))) { + dev_warn(dev, "%s %s property\n", + prop ? "invalid format" : "no", prop_name); + } else { + vreg->low_vol_level = be32_to_cpup(&prop[0]); + vreg->high_vol_level = be32_to_cpup(&prop[1]); + } + + snprintf(prop_name, MAX_PROP_SIZE, + "qcom,%s-current-level", vreg_name); + prop = of_get_property(np, prop_name, &len); + if (!prop || (len != (2 * sizeof(__be32)))) { + dev_warn(dev, "%s %s property\n", + prop ? "invalid format" : "no", prop_name); + } else { + vreg->lpm_uA = be32_to_cpup(&prop[0]); + vreg->hpm_uA = be32_to_cpup(&prop[1]); + } + + *vreg_data = vreg; + dev_dbg(dev, "%s: %s %s vol=[%d %d]uV, curr=[%d %d]uA\n", + vreg->name, vreg->is_always_on ? "always_on," : "", + vreg->lpm_sup ? "lpm_sup," : "", vreg->low_vol_level, + vreg->high_vol_level, vreg->lpm_uA, vreg->hpm_uA); + + return ret; +} + +/* GPIO/Pad data extraction */ +static int sdhci_msm_parse_pinctrl_info(struct device *dev, + struct sdhci_msm_pltfm_data *pdata) +{ + struct sdhci_pinctrl_data *pctrl_data; + struct pinctrl *pctrl; + int ret = 0; + + /* Try to obtain pinctrl handle */ + pctrl = devm_pinctrl_get(dev); + if (IS_ERR(pctrl)) { + ret = PTR_ERR(pctrl); + goto out; + } + pctrl_data = devm_kzalloc(dev, sizeof(*pctrl_data), GFP_KERNEL); + if (!pctrl_data) { + dev_err(dev, "No memory for sdhci_pinctrl_data\n"); + ret = -ENOMEM; + goto out; + } + pctrl_data->pctrl = pctrl; + /* Look-up and keep the states handy to be used later */ + pctrl_data->pins_active = pinctrl_lookup_state( + pctrl_data->pctrl, "active"); + if (IS_ERR(pctrl_data->pins_active)) { + ret = PTR_ERR(pctrl_data->pins_active); + dev_err(dev, "Could not get active pinstates, err:%d\n", ret); + goto out; + } + pctrl_data->pins_sleep = pinctrl_lookup_state( + pctrl_data->pctrl, "sleep"); + if (IS_ERR(pctrl_data->pins_sleep)) { + ret = PTR_ERR(pctrl_data->pins_sleep); + dev_err(dev, "Could not get sleep pinstates, err:%d\n", ret); + goto out; + } + pdata->pctrl_data = pctrl_data; +out: + return ret; +} + +#define GPIO_NAME_MAX_LEN 32 +static int sdhci_msm_dt_parse_gpio_info(struct device *dev, + struct sdhci_msm_pltfm_data *pdata) +{ + int ret = 0, cnt, i; + struct sdhci_msm_pin_data *pin_data; + struct device_node *np = dev->of_node; + + ret = sdhci_msm_parse_pinctrl_info(dev, pdata); + if (!ret) { + goto out; + } else if (ret == -EPROBE_DEFER) { + dev_err(dev, "Pinctrl framework not registered, err:%d\n", ret); + goto out; + } else { + dev_err(dev, "Parsing Pinctrl failed with %d, falling back on GPIO lib\n", + ret); + ret = 0; + } + pin_data = devm_kzalloc(dev, sizeof(*pin_data), GFP_KERNEL); + if (!pin_data) { + dev_err(dev, "No memory for pin_data\n"); + ret = -ENOMEM; + goto out; + } + + cnt = of_gpio_count(np); + if (cnt > 0) { + pin_data->is_gpio = true; + pin_data->gpio_data = devm_kzalloc(dev, + sizeof(struct sdhci_msm_gpio_data), GFP_KERNEL); + if (!pin_data->gpio_data) { + dev_err(dev, "No memory for gpio_data\n"); + ret = -ENOMEM; + goto out; + } + pin_data->gpio_data->size = cnt; + pin_data->gpio_data->gpio = devm_kzalloc(dev, cnt * + sizeof(struct sdhci_msm_gpio), GFP_KERNEL); + + if (!pin_data->gpio_data->gpio) { + dev_err(dev, "No memory for gpio\n"); + ret = -ENOMEM; + goto out; + } + for (i = 0; i < cnt; i++) { + const char *name = NULL; + char result[GPIO_NAME_MAX_LEN]; + pin_data->gpio_data->gpio[i].no = of_get_gpio(np, i); + of_property_read_string_index(np, + "qcom,gpio-names", i, &name); + + snprintf(result, GPIO_NAME_MAX_LEN, "%s-%s", + dev_name(dev), name ? name : "?"); + pin_data->gpio_data->gpio[i].name = result; + dev_dbg(dev, "%s: gpio[%s] = %d\n", __func__, + pin_data->gpio_data->gpio[i].name, + pin_data->gpio_data->gpio[i].no); + } + } + pdata->pin_data = pin_data; +out: + if (ret) + dev_err(dev, "%s failed with err %d\n", __func__, ret); + return ret; +} + +#ifdef CONFIG_SMP +static inline void parse_affine_irq(struct sdhci_msm_pltfm_data *pdata) +{ + pdata->pm_qos_data.irq_req_type = PM_QOS_REQ_AFFINE_IRQ; +} +#else +static inline void parse_affine_irq(struct sdhci_msm_pltfm_data *pdata) { } +#endif + +static int sdhci_msm_pm_qos_parse_irq(struct device *dev, + struct sdhci_msm_pltfm_data *pdata) +{ + struct device_node *np = dev->of_node; + const char *str; + u32 cpu; + int ret = 0; + int i; + + pdata->pm_qos_data.irq_valid = false; + pdata->pm_qos_data.irq_req_type = PM_QOS_REQ_AFFINE_CORES; + if (!of_property_read_string(np, "qcom,pm-qos-irq-type", &str) && + !strcmp(str, "affine_irq")) { + parse_affine_irq(pdata); + } + + /* must specify cpu for "affine_cores" type */ + if (pdata->pm_qos_data.irq_req_type == PM_QOS_REQ_AFFINE_CORES) { + pdata->pm_qos_data.irq_cpu = -1; + ret = of_property_read_u32(np, "qcom,pm-qos-irq-cpu", &cpu); + if (ret) { + dev_err(dev, "%s: error %d reading irq cpu\n", __func__, + ret); + goto out; + } + if (cpu < 0 || cpu >= num_possible_cpus()) { + dev_err(dev, "%s: invalid irq cpu %d (NR_CPUS=%d)\n", + __func__, cpu, num_possible_cpus()); + ret = -EINVAL; + goto out; + } + pdata->pm_qos_data.irq_cpu = cpu; + } + + if (of_property_count_u32_elems(np, "qcom,pm-qos-irq-latency") != + SDHCI_POWER_POLICY_NUM) { + dev_err(dev, "%s: could not read %d values for 'qcom,pm-qos-irq-latency'\n", + __func__, SDHCI_POWER_POLICY_NUM); + ret = -EINVAL; + goto out; + } + + for (i = 0; i < SDHCI_POWER_POLICY_NUM; i++) + of_property_read_u32_index(np, "qcom,pm-qos-irq-latency", i, + &pdata->pm_qos_data.irq_latency.latency[i]); + + pdata->pm_qos_data.irq_valid = true; +out: + return ret; +} + +static int sdhci_msm_pm_qos_parse_cpu_groups(struct device *dev, + struct sdhci_msm_pltfm_data *pdata) +{ + struct device_node *np = dev->of_node; + u32 mask; + int nr_groups; + int ret; + int i; + + /* Read cpu group mapping */ + nr_groups = of_property_count_u32_elems(np, "qcom,pm-qos-cpu-groups"); + if (nr_groups <= 0) { + ret = -EINVAL; + goto out; + } + pdata->pm_qos_data.cpu_group_map.nr_groups = nr_groups; + pdata->pm_qos_data.cpu_group_map.mask = + kcalloc(nr_groups, sizeof(cpumask_t), GFP_KERNEL); + if (!pdata->pm_qos_data.cpu_group_map.mask) { + ret = -ENOMEM; + goto out; + } + + for (i = 0; i < nr_groups; i++) { + of_property_read_u32_index(np, "qcom,pm-qos-cpu-groups", + i, &mask); + + pdata->pm_qos_data.cpu_group_map.mask[i].bits[0] = mask; + if (!cpumask_subset(&pdata->pm_qos_data.cpu_group_map.mask[i], + cpu_possible_mask)) { + dev_err(dev, "%s: invalid mask 0x%x of cpu group #%d\n", + __func__, mask, i); + ret = -EINVAL; + goto free_res; + } + } + return 0; + +free_res: + kfree(pdata->pm_qos_data.cpu_group_map.mask); +out: + return ret; +} + +static int sdhci_msm_pm_qos_parse_latency(struct device *dev, const char *name, + int nr_groups, struct sdhci_msm_pm_qos_latency **latency) +{ + struct device_node *np = dev->of_node; + struct sdhci_msm_pm_qos_latency *values; + int ret; + int i; + int group; + int cfg; + + ret = of_property_count_u32_elems(np, name); + if (ret > 0 && ret != SDHCI_POWER_POLICY_NUM * nr_groups) { + dev_err(dev, "%s: invalid number of values for property %s: expected=%d actual=%d\n", + __func__, name, SDHCI_POWER_POLICY_NUM * nr_groups, + ret); + return -EINVAL; + } else if (ret < 0) { + return ret; + } + + values = kcalloc(nr_groups, sizeof(struct sdhci_msm_pm_qos_latency), + GFP_KERNEL); + if (!values) + return -ENOMEM; + + for (i = 0; i < SDHCI_POWER_POLICY_NUM * nr_groups; i++) { + group = i / SDHCI_POWER_POLICY_NUM; + cfg = i % SDHCI_POWER_POLICY_NUM; + of_property_read_u32_index(np, name, i, + &(values[group].latency[cfg])); + } + + *latency = values; + return 0; +} + +static void sdhci_msm_pm_qos_parse(struct device *dev, + struct sdhci_msm_pltfm_data *pdata) +{ + if (sdhci_msm_pm_qos_parse_irq(dev, pdata)) + dev_notice(dev, "%s: PM QoS voting for IRQ will be disabled\n", + __func__); + + if (!sdhci_msm_pm_qos_parse_cpu_groups(dev, pdata)) { + pdata->pm_qos_data.cmdq_valid = + !sdhci_msm_pm_qos_parse_latency(dev, + "qcom,pm-qos-cmdq-latency-us", + pdata->pm_qos_data.cpu_group_map.nr_groups, + &pdata->pm_qos_data.cmdq_latency); + pdata->pm_qos_data.legacy_valid = + !sdhci_msm_pm_qos_parse_latency(dev, + "qcom,pm-qos-legacy-latency-us", + pdata->pm_qos_data.cpu_group_map.nr_groups, + &pdata->pm_qos_data.latency); + if (!pdata->pm_qos_data.cmdq_valid && + !pdata->pm_qos_data.legacy_valid) { + /* clean-up previously allocated arrays */ + kfree(pdata->pm_qos_data.latency); + kfree(pdata->pm_qos_data.cmdq_latency); + dev_err(dev, "%s: invalid PM QoS latency values. Voting for cpu group will be disabled\n", + __func__); + } + } else { + dev_notice(dev, "%s: PM QoS voting for cpu group will be disabled\n", + __func__); + } +} + +/* Parse platform data */ +static +struct sdhci_msm_pltfm_data *sdhci_msm_populate_pdata(struct device *dev, + struct sdhci_msm_host *msm_host) +{ + struct sdhci_msm_pltfm_data *pdata = NULL; + struct device_node *np = dev->of_node; + u32 bus_width = 0; + int len, i; + int clk_table_len; + u32 *clk_table = NULL; + int ice_clk_table_len; + u32 *ice_clk_table = NULL; + enum of_gpio_flags flags = OF_GPIO_ACTIVE_LOW; + const char *lower_bus_speed = NULL; + + pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL); + if (!pdata) { + dev_err(dev, "failed to allocate memory for platform data\n"); + goto out; + } + + pdata->status_gpio = of_get_named_gpio_flags(np, "cd-gpios", 0, &flags); + if (gpio_is_valid(pdata->status_gpio) && !(flags & OF_GPIO_ACTIVE_LOW)) + pdata->caps2 |= MMC_CAP2_CD_ACTIVE_HIGH; + + of_property_read_u32(np, "qcom,bus-width", &bus_width); + if (bus_width == 8) + pdata->mmc_bus_width = MMC_CAP_8_BIT_DATA; + else if (bus_width == 4) + pdata->mmc_bus_width = MMC_CAP_4_BIT_DATA; + else { + dev_notice(dev, "invalid bus-width, default to 1-bit mode\n"); + pdata->mmc_bus_width = 0; + } + + if (sdhci_msm_dt_get_array(dev, "qcom,devfreq,freq-table", + &msm_host->mmc->clk_scaling.pltfm_freq_table, + &msm_host->mmc->clk_scaling.pltfm_freq_table_sz, 0)) + pr_debug("%s: no clock scaling frequencies were supplied\n", + dev_name(dev)); + else if (!msm_host->mmc->clk_scaling.pltfm_freq_table || + !msm_host->mmc->clk_scaling.pltfm_freq_table_sz) + dev_err(dev, "bad dts clock scaling frequencies\n"); + + /* + * Few hosts can support DDR52 mode at the same lower + * system voltage corner as high-speed mode. In such cases, + * it is always better to put it in DDR mode which will + * improve the performance without any power impact. + */ + if (!of_property_read_string(np, "qcom,scaling-lower-bus-speed-mode", + &lower_bus_speed)) { + if (!strcmp(lower_bus_speed, "DDR52")) + msm_host->mmc->clk_scaling.lower_bus_speed_mode |= + MMC_SCALING_LOWER_DDR52_MODE; + } + + if (sdhci_msm_dt_get_array(dev, "qcom,clk-rates", + &clk_table, &clk_table_len, 0)) { + dev_err(dev, "failed parsing supported clock rates\n"); + goto out; + } + if (!clk_table || !clk_table_len) { + dev_err(dev, "Invalid clock table\n"); + goto out; + } + pdata->sup_clk_table = clk_table; + pdata->sup_clk_cnt = clk_table_len; + + if (msm_host->ice.pdev) { + if (sdhci_msm_dt_get_array(dev, "qcom,ice-clk-rates", + &ice_clk_table, &ice_clk_table_len, 0)) { + dev_err(dev, "failed parsing supported ice clock rates\n"); + goto out; + } + if (!ice_clk_table || !ice_clk_table_len) { + dev_err(dev, "Invalid clock table\n"); + goto out; + } + if (ice_clk_table_len != 2) { + dev_err(dev, "Need max and min frequencies in the table\n"); + goto out; + } + pdata->sup_ice_clk_table = ice_clk_table; + pdata->sup_ice_clk_cnt = ice_clk_table_len; + pdata->ice_clk_max = pdata->sup_ice_clk_table[0]; + pdata->ice_clk_min = pdata->sup_ice_clk_table[1]; + dev_dbg(dev, "supported ICE clock rates (Hz): max: %u min: %u\n", + pdata->ice_clk_max, pdata->ice_clk_min); + } + + pdata->vreg_data = devm_kzalloc(dev, sizeof(struct + sdhci_msm_slot_reg_data), + GFP_KERNEL); + if (!pdata->vreg_data) { + dev_err(dev, "failed to allocate memory for vreg data\n"); + goto out; + } + + if (sdhci_msm_dt_parse_vreg_info(dev, &pdata->vreg_data->vdd_data, + "vdd")) { + dev_err(dev, "failed parsing vdd data\n"); + goto out; + } + if (sdhci_msm_dt_parse_vreg_info(dev, + &pdata->vreg_data->vdd_io_data, + "vdd-io")) { + dev_err(dev, "failed parsing vdd-io data\n"); + goto out; + } + + if (sdhci_msm_dt_parse_gpio_info(dev, pdata)) { + dev_err(dev, "failed parsing gpio data\n"); + goto out; + } + + len = of_property_count_strings(np, "qcom,bus-speed-mode"); + + for (i = 0; i < len; i++) { + const char *name = NULL; + + of_property_read_string_index(np, + "qcom,bus-speed-mode", i, &name); + if (!name) + continue; + + if (!strncmp(name, "HS400_1p8v", sizeof("HS400_1p8v"))) + pdata->caps2 |= MMC_CAP2_HS400_1_8V; + else if (!strncmp(name, "HS400_1p2v", sizeof("HS400_1p2v"))) + pdata->caps2 |= MMC_CAP2_HS400_1_2V; + else if (!strncmp(name, "HS200_1p8v", sizeof("HS200_1p8v"))) + pdata->caps2 |= MMC_CAP2_HS200_1_8V_SDR; + else if (!strncmp(name, "HS200_1p2v", sizeof("HS200_1p2v"))) + pdata->caps2 |= MMC_CAP2_HS200_1_2V_SDR; + else if (!strncmp(name, "DDR_1p8v", sizeof("DDR_1p8v"))) + pdata->caps |= MMC_CAP_1_8V_DDR + | MMC_CAP_UHS_DDR50; + else if (!strncmp(name, "DDR_1p2v", sizeof("DDR_1p2v"))) + pdata->caps |= MMC_CAP_1_2V_DDR + | MMC_CAP_UHS_DDR50; + } + + if (of_get_property(np, "qcom,nonremovable", NULL)) + pdata->nonremovable = true; + + if (of_get_property(np, "qcom,nonhotplug", NULL)) + pdata->nonhotplug = true; + + pdata->largeaddressbus = + of_property_read_bool(np, "qcom,large-address-bus"); + + if (of_property_read_bool(np, "qcom,wakeup-on-idle")) + msm_host->mmc->wakeup_on_idle = true; + + sdhci_msm_pm_qos_parse(dev, pdata); + + if (of_get_property(np, "qcom,core_3_0v_support", NULL)) + msm_host->core_3_0v_support = true; + + pdata->sdr104_wa = of_property_read_bool(np, "qcom,sdr104-wa"); + + return pdata; +out: + return NULL; +} + +/* Returns required bandwidth in Bytes per Sec */ +static unsigned int sdhci_get_bw_required(struct sdhci_host *host, + struct mmc_ios *ios) +{ + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); + struct sdhci_msm_host *msm_host = pltfm_host->priv; + + unsigned int bw; + + bw = msm_host->clk_rate; + /* + * For DDR mode, SDCC controller clock will be at + * the double rate than the actual clock that goes to card. + */ + if (ios->bus_width == MMC_BUS_WIDTH_4) + bw /= 2; + else if (ios->bus_width == MMC_BUS_WIDTH_1) + bw /= 8; + + return bw; +} + +static int sdhci_msm_bus_get_vote_for_bw(struct sdhci_msm_host *host, + unsigned int bw) +{ + unsigned int *table = host->pdata->voting_data->bw_vecs; + unsigned int size = host->pdata->voting_data->bw_vecs_size; + int i; + + if (host->msm_bus_vote.is_max_bw_needed && bw) + return host->msm_bus_vote.max_bw_vote; + + for (i = 0; i < size; i++) { + if (bw <= table[i]) + break; + } + + if (i && (i == size)) + i--; + + return i; +} + +/* + * This function must be called with host lock acquired. + * Caller of this function should also ensure that msm bus client + * handle is not null. + */ +static inline int sdhci_msm_bus_set_vote(struct sdhci_msm_host *msm_host, + int vote, + unsigned long *flags) +{ + struct sdhci_host *host = platform_get_drvdata(msm_host->pdev); + int rc = 0; + + BUG_ON(!flags); + + if (vote != msm_host->msm_bus_vote.curr_vote) { + spin_unlock_irqrestore(&host->lock, *flags); + rc = msm_bus_scale_client_update_request( + msm_host->msm_bus_vote.client_handle, vote); + spin_lock_irqsave(&host->lock, *flags); + if (rc) { + pr_err("%s: msm_bus_scale_client_update_request() failed: bus_client_handle=0x%x, vote=%d, err=%d\n", + mmc_hostname(host->mmc), + msm_host->msm_bus_vote.client_handle, vote, rc); + goto out; + } + msm_host->msm_bus_vote.curr_vote = vote; + } +out: + return rc; +} + +/* + * Internal work. Work to set 0 bandwidth for msm bus. + */ +static void sdhci_msm_bus_work(struct work_struct *work) +{ + struct sdhci_msm_host *msm_host; + struct sdhci_host *host; + unsigned long flags; + + msm_host = container_of(work, struct sdhci_msm_host, + msm_bus_vote.vote_work.work); + host = platform_get_drvdata(msm_host->pdev); + + if (!msm_host->msm_bus_vote.client_handle) + return; + + spin_lock_irqsave(&host->lock, flags); + /* don't vote for 0 bandwidth if any request is in progress */ + if (!host->mrq) { + sdhci_msm_bus_set_vote(msm_host, + msm_host->msm_bus_vote.min_bw_vote, &flags); + } else + pr_warning("%s: %s: Transfer in progress. skipping bus voting to 0 bandwidth\n", + mmc_hostname(host->mmc), __func__); + spin_unlock_irqrestore(&host->lock, flags); +} + +/* + * This function cancels any scheduled delayed work and sets the bus + * vote based on bw (bandwidth) argument. + */ +static void sdhci_msm_bus_cancel_work_and_set_vote(struct sdhci_host *host, + unsigned int bw) +{ + int vote; + unsigned long flags; + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); + struct sdhci_msm_host *msm_host = pltfm_host->priv; + + cancel_delayed_work_sync(&msm_host->msm_bus_vote.vote_work); + spin_lock_irqsave(&host->lock, flags); + vote = sdhci_msm_bus_get_vote_for_bw(msm_host, bw); + sdhci_msm_bus_set_vote(msm_host, vote, &flags); + spin_unlock_irqrestore(&host->lock, flags); +} + +#define MSM_MMC_BUS_VOTING_DELAY 200 /* msecs */ + +/* This function queues a work which will set the bandwidth requiement to 0 */ +static void sdhci_msm_bus_queue_work(struct sdhci_host *host) +{ + unsigned long flags; + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); + struct sdhci_msm_host *msm_host = pltfm_host->priv; + + spin_lock_irqsave(&host->lock, flags); + if (msm_host->msm_bus_vote.min_bw_vote != + msm_host->msm_bus_vote.curr_vote) + queue_delayed_work(system_wq, + &msm_host->msm_bus_vote.vote_work, + msecs_to_jiffies(MSM_MMC_BUS_VOTING_DELAY)); + spin_unlock_irqrestore(&host->lock, flags); +} + +static int sdhci_msm_bus_register(struct sdhci_msm_host *host, + struct platform_device *pdev) +{ + int rc = 0; + struct msm_bus_scale_pdata *bus_pdata; + + struct sdhci_msm_bus_voting_data *data; + struct device *dev = &pdev->dev; + + data = devm_kzalloc(dev, + sizeof(struct sdhci_msm_bus_voting_data), GFP_KERNEL); + if (!data) { + dev_err(&pdev->dev, + "%s: failed to allocate memory\n", __func__); + rc = -ENOMEM; + goto out; + } + data->bus_pdata = msm_bus_cl_get_pdata(pdev); + if (data->bus_pdata) { + rc = sdhci_msm_dt_get_array(dev, "qcom,bus-bw-vectors-bps", + &data->bw_vecs, &data->bw_vecs_size, 0); + if (rc) { + dev_err(&pdev->dev, + "%s: Failed to get bus-bw-vectors-bps\n", + __func__); + goto out; + } + host->pdata->voting_data = data; + } + if (host->pdata->voting_data && + host->pdata->voting_data->bus_pdata && + host->pdata->voting_data->bw_vecs && + host->pdata->voting_data->bw_vecs_size) { + + bus_pdata = host->pdata->voting_data->bus_pdata; + host->msm_bus_vote.client_handle = + msm_bus_scale_register_client(bus_pdata); + if (!host->msm_bus_vote.client_handle) { + dev_err(&pdev->dev, "msm_bus_scale_register_client()\n"); + rc = -EFAULT; + goto out; + } + /* cache the vote index for minimum and maximum bandwidth */ + host->msm_bus_vote.min_bw_vote = + sdhci_msm_bus_get_vote_for_bw(host, 0); + host->msm_bus_vote.max_bw_vote = + sdhci_msm_bus_get_vote_for_bw(host, UINT_MAX); + } else { + devm_kfree(dev, data); + } + +out: + return rc; +} + +static void sdhci_msm_bus_unregister(struct sdhci_msm_host *host) +{ + if (host->msm_bus_vote.client_handle) + msm_bus_scale_unregister_client( + host->msm_bus_vote.client_handle); +} + +static void sdhci_msm_bus_voting(struct sdhci_host *host, u32 enable) +{ + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); + struct sdhci_msm_host *msm_host = pltfm_host->priv; + struct mmc_ios *ios = &host->mmc->ios; + unsigned int bw; + + if (!msm_host->msm_bus_vote.client_handle) + return; + + bw = sdhci_get_bw_required(host, ios); + if (enable) { + sdhci_msm_bus_cancel_work_and_set_vote(host, bw); + } else { + /* + * If clock gating is enabled, then remove the vote + * immediately because clocks will be disabled only + * after SDHCI_MSM_MMC_CLK_GATE_DELAY and thus no + * additional delay is required to remove the bus vote. + */ +#ifdef CONFIG_MMC_CLKGATE + if (host->mmc->clkgate_delay) + sdhci_msm_bus_cancel_work_and_set_vote(host, 0); + else +#endif + sdhci_msm_bus_queue_work(host); + } +} + +/* Regulator utility functions */ +static int sdhci_msm_vreg_init_reg(struct device *dev, + struct sdhci_msm_reg_data *vreg) +{ + int ret = 0; + + /* check if regulator is already initialized? */ + if (vreg->reg) + goto out; + + /* Get the regulator handle */ + vreg->reg = devm_regulator_get(dev, vreg->name); + if (IS_ERR(vreg->reg)) { + ret = PTR_ERR(vreg->reg); + pr_err("%s: devm_regulator_get(%s) failed. ret=%d\n", + __func__, vreg->name, ret); + goto out; + } + + if (regulator_count_voltages(vreg->reg) > 0) { + vreg->set_voltage_sup = true; + /* sanity check */ + if (!vreg->high_vol_level || !vreg->hpm_uA) { + pr_err("%s: %s invalid constraints specified\n", + __func__, vreg->name); + ret = -EINVAL; + } + } + +out: + return ret; +} + +static void sdhci_msm_vreg_deinit_reg(struct sdhci_msm_reg_data *vreg) +{ + if (vreg->reg) + devm_regulator_put(vreg->reg); +} + +static int sdhci_msm_vreg_set_optimum_mode(struct sdhci_msm_reg_data + *vreg, int uA_load) +{ + int ret = 0; + + /* + * regulators that do not support regulator_set_voltage also + * do not support regulator_set_optimum_mode + */ + if (vreg->set_voltage_sup) { + ret = regulator_set_load(vreg->reg, uA_load); + if (ret < 0) + pr_err("%s: regulator_set_load(reg=%s,uA_load=%d) failed. ret=%d\n", + __func__, vreg->name, uA_load, ret); + else + /* + * regulator_set_load() can return non zero + * value even for success case. + */ + ret = 0; + } + return ret; +} + +static int sdhci_msm_vreg_set_voltage(struct sdhci_msm_reg_data *vreg, + int min_uV, int max_uV) +{ + int ret = 0; + if (vreg->set_voltage_sup) { + ret = regulator_set_voltage(vreg->reg, min_uV, max_uV); + if (ret) { + pr_err("%s: regulator_set_voltage(%s)failed. min_uV=%d,max_uV=%d,ret=%d\n", + __func__, vreg->name, min_uV, max_uV, ret); + } + } + + return ret; +} + +static int sdhci_msm_vreg_enable(struct sdhci_msm_reg_data *vreg) +{ + int ret = 0; + + /* Put regulator in HPM (high power mode) */ + ret = sdhci_msm_vreg_set_optimum_mode(vreg, vreg->hpm_uA); + if (ret < 0) + return ret; + + if (!vreg->is_enabled) { + /* Set voltage level */ + ret = sdhci_msm_vreg_set_voltage(vreg, vreg->high_vol_level, + vreg->high_vol_level); + if (ret) + return ret; + } + ret = regulator_enable(vreg->reg); + if (ret) { + pr_err("%s: regulator_enable(%s) failed. ret=%d\n", + __func__, vreg->name, ret); + return ret; + } + vreg->is_enabled = true; + return ret; +} + +static int sdhci_msm_vreg_disable(struct sdhci_msm_reg_data *vreg) +{ + int ret = 0; + + /* Never disable regulator marked as always_on */ + if (vreg->is_enabled && !vreg->is_always_on) { + ret = regulator_disable(vreg->reg); + if (ret) { + pr_err("%s: regulator_disable(%s) failed. ret=%d\n", + __func__, vreg->name, ret); + goto out; + } + vreg->is_enabled = false; + + ret = sdhci_msm_vreg_set_optimum_mode(vreg, 0); + if (ret < 0) + goto out; + + /* Set min. voltage level to 0 */ + ret = sdhci_msm_vreg_set_voltage(vreg, 0, vreg->high_vol_level); + if (ret) + goto out; + } else if (vreg->is_enabled && vreg->is_always_on) { + if (vreg->lpm_sup) { + /* Put always_on regulator in LPM (low power mode) */ + ret = sdhci_msm_vreg_set_optimum_mode(vreg, + vreg->lpm_uA); + if (ret < 0) + goto out; + } + } +out: + return ret; +} + +static int sdhci_msm_setup_vreg(struct sdhci_msm_pltfm_data *pdata, + bool enable, bool is_init) +{ + int ret = 0, i; + struct sdhci_msm_slot_reg_data *curr_slot; + struct sdhci_msm_reg_data *vreg_table[2]; + + curr_slot = pdata->vreg_data; + if (!curr_slot) { + pr_debug("%s: vreg info unavailable,assuming the slot is powered by always on domain\n", + __func__); + goto out; + } + + vreg_table[0] = curr_slot->vdd_data; + vreg_table[1] = curr_slot->vdd_io_data; + + for (i = 0; i < ARRAY_SIZE(vreg_table); i++) { + if (vreg_table[i]) { + if (enable) + ret = sdhci_msm_vreg_enable(vreg_table[i]); + else + ret = sdhci_msm_vreg_disable(vreg_table[i]); + if (ret) + goto out; + } + } +out: + return ret; +} + +/* This init function should be called only once for each SDHC slot */ +static int sdhci_msm_vreg_init(struct device *dev, + struct sdhci_msm_pltfm_data *pdata, + bool is_init) +{ + int ret = 0; + struct sdhci_msm_slot_reg_data *curr_slot; + struct sdhci_msm_reg_data *curr_vdd_reg, *curr_vdd_io_reg; + + curr_slot = pdata->vreg_data; + if (!curr_slot) + goto out; + + curr_vdd_reg = curr_slot->vdd_data; + curr_vdd_io_reg = curr_slot->vdd_io_data; + + if (!is_init) + /* Deregister all regulators from regulator framework */ + goto vdd_io_reg_deinit; + + /* + * Get the regulator handle from voltage regulator framework + * and then try to set the voltage level for the regulator + */ + if (curr_vdd_reg) { + ret = sdhci_msm_vreg_init_reg(dev, curr_vdd_reg); + if (ret) + goto out; + } + if (curr_vdd_io_reg) { + ret = sdhci_msm_vreg_init_reg(dev, curr_vdd_io_reg); + if (ret) + goto vdd_reg_deinit; + } + + if (ret) + dev_err(dev, "vreg reset failed (%d)\n", ret); + goto out; + +vdd_io_reg_deinit: + if (curr_vdd_io_reg) + sdhci_msm_vreg_deinit_reg(curr_vdd_io_reg); +vdd_reg_deinit: + if (curr_vdd_reg) + sdhci_msm_vreg_deinit_reg(curr_vdd_reg); +out: + return ret; +} + + +static int sdhci_msm_set_vdd_io_vol(struct sdhci_msm_pltfm_data *pdata, + enum vdd_io_level level, + unsigned int voltage_level) +{ + int ret = 0; + int set_level; + struct sdhci_msm_reg_data *vdd_io_reg; + + if (!pdata->vreg_data) + return ret; + + vdd_io_reg = pdata->vreg_data->vdd_io_data; + if (vdd_io_reg && vdd_io_reg->is_enabled) { + switch (level) { + case VDD_IO_LOW: + set_level = vdd_io_reg->low_vol_level; + break; + case VDD_IO_HIGH: + set_level = vdd_io_reg->high_vol_level; + break; + case VDD_IO_SET_LEVEL: + set_level = voltage_level; + break; + default: + pr_err("%s: invalid argument level = %d", + __func__, level); + ret = -EINVAL; + return ret; + } + ret = sdhci_msm_vreg_set_voltage(vdd_io_reg, set_level, + set_level); + } + return ret; +} + +/* + * Acquire spin-lock host->lock before calling this function + */ +static void sdhci_msm_cfg_sdiowakeup_gpio_irq(struct sdhci_host *host, + bool enable) +{ + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); + struct sdhci_msm_host *msm_host = pltfm_host->priv; + + if (enable && !msm_host->is_sdiowakeup_enabled) + enable_irq(msm_host->pdata->sdiowakeup_irq); + else if (!enable && msm_host->is_sdiowakeup_enabled) + disable_irq_nosync(msm_host->pdata->sdiowakeup_irq); + else + dev_warn(&msm_host->pdev->dev, "%s: wakeup to config: %d curr: %d\n", + __func__, enable, msm_host->is_sdiowakeup_enabled); + msm_host->is_sdiowakeup_enabled = enable; +} + +static irqreturn_t sdhci_msm_sdiowakeup_irq(int irq, void *data) +{ + struct sdhci_host *host = (struct sdhci_host *)data; + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); + struct sdhci_msm_host *msm_host = pltfm_host->priv; + + unsigned long flags; + + pr_debug("%s: irq (%d) received\n", __func__, irq); + + spin_lock_irqsave(&host->lock, flags); + sdhci_msm_cfg_sdiowakeup_gpio_irq(host, false); + spin_unlock_irqrestore(&host->lock, flags); + msm_host->sdio_pending_processing = true; + + return IRQ_HANDLED; +} + +void sdhci_msm_dump_pwr_ctrl_regs(struct sdhci_host *host) +{ + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); + struct sdhci_msm_host *msm_host = pltfm_host->priv; + const struct sdhci_msm_offset *msm_host_offset = + msm_host->offset; + unsigned int irq_flags = 0; + struct irq_desc *pwr_irq_desc = irq_to_desc(msm_host->pwr_irq); + + if (pwr_irq_desc) + irq_flags = pwr_irq_desc->irq_data.common->state_use_accessors; + + pr_err("%s: PWRCTL_STATUS: 0x%08x | PWRCTL_MASK: 0x%08x | PWRCTL_CTL: 0x%08x, pwr isr state=0x%x\n", + mmc_hostname(host->mmc), + sdhci_msm_readl_relaxed(host, + msm_host_offset->CORE_PWRCTL_STATUS), + sdhci_msm_readl_relaxed(host, + msm_host_offset->CORE_PWRCTL_MASK), + sdhci_msm_readl_relaxed(host, + msm_host_offset->CORE_PWRCTL_CTL), irq_flags); + + MMC_TRACE(host->mmc, + "%s: Sts: 0x%08x | Mask: 0x%08x | Ctrl: 0x%08x, pwr isr state=0x%x\n", + __func__, + sdhci_msm_readb_relaxed(host, + msm_host_offset->CORE_PWRCTL_STATUS), + sdhci_msm_readb_relaxed(host, + msm_host_offset->CORE_PWRCTL_MASK), + sdhci_msm_readb_relaxed(host, + msm_host_offset->CORE_PWRCTL_CTL), irq_flags); +} + +static irqreturn_t sdhci_msm_pwr_irq(int irq, void *data) +{ + struct sdhci_host *host = (struct sdhci_host *)data; + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); + struct sdhci_msm_host *msm_host = pltfm_host->priv; + const struct sdhci_msm_offset *msm_host_offset = + msm_host->offset; + u8 irq_status = 0; + u8 irq_ack = 0; + int ret = 0; + int pwr_state = 0, io_level = 0; + unsigned long flags; + int retry = 10; + + irq_status = sdhci_msm_readb_relaxed(host, + msm_host_offset->CORE_PWRCTL_STATUS); + + pr_debug("%s: Received IRQ(%d), status=0x%x\n", + mmc_hostname(msm_host->mmc), irq, irq_status); + + /* Clear the interrupt */ + sdhci_msm_writeb_relaxed(irq_status, host, + msm_host_offset->CORE_PWRCTL_CLEAR); + + /* + * SDHC has core_mem and hc_mem device memory and these memory + * addresses do not fall within 1KB region. Hence, any update to + * core_mem address space would require an mb() to ensure this gets + * completed before its next update to registers within hc_mem. + */ + mb(); + /* + * There is a rare HW scenario where the first clear pulse could be + * lost when actual reset and clear/read of status register is + * happening at a time. Hence, retry for at least 10 times to make + * sure status register is cleared. Otherwise, this will result in + * a spurious power IRQ resulting in system instability. + */ + while (irq_status & sdhci_msm_readb_relaxed(host, + msm_host_offset->CORE_PWRCTL_STATUS)) { + if (retry == 0) { + pr_err("%s: Timedout clearing (0x%x) pwrctl status register\n", + mmc_hostname(host->mmc), irq_status); + sdhci_msm_dump_pwr_ctrl_regs(host); + BUG_ON(1); + } + sdhci_msm_writeb_relaxed(irq_status, host, + msm_host_offset->CORE_PWRCTL_CLEAR); + retry--; + udelay(10); + } + if (likely(retry < 10)) + pr_debug("%s: success clearing (0x%x) pwrctl status register, retries left %d\n", + mmc_hostname(host->mmc), irq_status, retry); + + /* Handle BUS ON/OFF*/ + if (irq_status & CORE_PWRCTL_BUS_ON) { + ret = sdhci_msm_setup_vreg(msm_host->pdata, true, false); + if (!ret) { + ret = sdhci_msm_setup_pins(msm_host->pdata, true); + ret |= sdhci_msm_set_vdd_io_vol(msm_host->pdata, + VDD_IO_HIGH, 0); + } + if (ret) + irq_ack |= CORE_PWRCTL_BUS_FAIL; + else + irq_ack |= CORE_PWRCTL_BUS_SUCCESS; + + pwr_state = REQ_BUS_ON; + io_level = REQ_IO_HIGH; + } + if (irq_status & CORE_PWRCTL_BUS_OFF) { + if (msm_host->pltfm_init_done) + ret = sdhci_msm_setup_vreg(msm_host->pdata, + false, false); + if (!ret) { + ret = sdhci_msm_setup_pins(msm_host->pdata, false); + ret |= sdhci_msm_set_vdd_io_vol(msm_host->pdata, + VDD_IO_LOW, 0); + } + if (ret) + irq_ack |= CORE_PWRCTL_BUS_FAIL; + else + irq_ack |= CORE_PWRCTL_BUS_SUCCESS; + + pwr_state = REQ_BUS_OFF; + io_level = REQ_IO_LOW; + } + /* Handle IO LOW/HIGH */ + if (irq_status & CORE_PWRCTL_IO_LOW) { + /* Switch voltage Low */ + ret = sdhci_msm_set_vdd_io_vol(msm_host->pdata, VDD_IO_LOW, 0); + if (ret) + irq_ack |= CORE_PWRCTL_IO_FAIL; + else + irq_ack |= CORE_PWRCTL_IO_SUCCESS; + + io_level = REQ_IO_LOW; + } + if (irq_status & CORE_PWRCTL_IO_HIGH) { + /* Switch voltage High */ + ret = sdhci_msm_set_vdd_io_vol(msm_host->pdata, VDD_IO_HIGH, 0); + if (ret) + irq_ack |= CORE_PWRCTL_IO_FAIL; + else + irq_ack |= CORE_PWRCTL_IO_SUCCESS; + + io_level = REQ_IO_HIGH; + } + + /* ACK status to the core */ + sdhci_msm_writeb_relaxed(irq_ack, host, + msm_host_offset->CORE_PWRCTL_CTL); + /* + * SDHC has core_mem and hc_mem device memory and these memory + * addresses do not fall within 1KB region. Hence, any update to + * core_mem address space would require an mb() to ensure this gets + * completed before its next update to registers within hc_mem. + */ + mb(); + + if ((io_level & REQ_IO_HIGH) && + (msm_host->caps_0 & CORE_3_0V_SUPPORT) && + !msm_host->core_3_0v_support) + writel_relaxed((readl_relaxed(host->ioaddr + + msm_host_offset->CORE_VENDOR_SPEC) & + ~CORE_IO_PAD_PWR_SWITCH), host->ioaddr + + msm_host_offset->CORE_VENDOR_SPEC); + else if ((io_level & REQ_IO_LOW) || + (msm_host->caps_0 & CORE_1_8V_SUPPORT)) + writel_relaxed((readl_relaxed(host->ioaddr + + msm_host_offset->CORE_VENDOR_SPEC) | + CORE_IO_PAD_PWR_SWITCH), host->ioaddr + + msm_host_offset->CORE_VENDOR_SPEC); + mb(); + + pr_debug("%s: Handled IRQ(%d), ret=%d, ack=0x%x\n", + mmc_hostname(msm_host->mmc), irq, ret, irq_ack); + spin_lock_irqsave(&host->lock, flags); + if (pwr_state) + msm_host->curr_pwr_state = pwr_state; + if (io_level) + msm_host->curr_io_level = io_level; + complete(&msm_host->pwr_irq_completion); + spin_unlock_irqrestore(&host->lock, flags); + + return IRQ_HANDLED; +} + +static ssize_t +show_polling(struct device *dev, struct device_attribute *attr, char *buf) +{ + struct sdhci_host *host = dev_get_drvdata(dev); + int poll; + unsigned long flags; + + spin_lock_irqsave(&host->lock, flags); + poll = !!(host->mmc->caps & MMC_CAP_NEEDS_POLL); + spin_unlock_irqrestore(&host->lock, flags); + + return snprintf(buf, PAGE_SIZE, "%d\n", poll); +} + +static ssize_t +store_polling(struct device *dev, struct device_attribute *attr, + const char *buf, size_t count) +{ + struct sdhci_host *host = dev_get_drvdata(dev); + int value; + unsigned long flags; + + if (!kstrtou32(buf, 0, &value)) { + spin_lock_irqsave(&host->lock, flags); + if (value) { + host->mmc->caps |= MMC_CAP_NEEDS_POLL; + mmc_detect_change(host->mmc, 0); + } else { + host->mmc->caps &= ~MMC_CAP_NEEDS_POLL; + } + spin_unlock_irqrestore(&host->lock, flags); + } + return count; +} + +static ssize_t +show_sdhci_max_bus_bw(struct device *dev, struct device_attribute *attr, + char *buf) +{ + struct sdhci_host *host = dev_get_drvdata(dev); + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); + struct sdhci_msm_host *msm_host = pltfm_host->priv; + + return snprintf(buf, PAGE_SIZE, "%u\n", + msm_host->msm_bus_vote.is_max_bw_needed); +} + +static ssize_t +store_sdhci_max_bus_bw(struct device *dev, struct device_attribute *attr, + const char *buf, size_t count) +{ + struct sdhci_host *host = dev_get_drvdata(dev); + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); + struct sdhci_msm_host *msm_host = pltfm_host->priv; + uint32_t value; + unsigned long flags; + + if (!kstrtou32(buf, 0, &value)) { + spin_lock_irqsave(&host->lock, flags); + msm_host->msm_bus_vote.is_max_bw_needed = !!value; + spin_unlock_irqrestore(&host->lock, flags); + } + return count; +} + +static void sdhci_msm_check_power_status(struct sdhci_host *host, u32 req_type) +{ + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); + struct sdhci_msm_host *msm_host = pltfm_host->priv; + const struct sdhci_msm_offset *msm_host_offset = + msm_host->offset; + unsigned long flags; + bool done = false; + u32 io_sig_sts = SWITCHABLE_SIGNALLING_VOL; + + spin_lock_irqsave(&host->lock, flags); + pr_debug("%s: %s: request %d curr_pwr_state %x curr_io_level %x\n", + mmc_hostname(host->mmc), __func__, req_type, + msm_host->curr_pwr_state, msm_host->curr_io_level); + if (!msm_host->mci_removed) + io_sig_sts = sdhci_msm_readl_relaxed(host, + msm_host_offset->CORE_GENERICS); + + /* + * The IRQ for request type IO High/Low will be generated when - + * 1. SWITCHABLE_SIGNALLING_VOL is enabled in HW. + * 2. If 1 is true and when there is a state change in 1.8V enable + * bit (bit 3) of SDHCI_HOST_CONTROL2 register. The reset state of + * that bit is 0 which indicates 3.3V IO voltage. So, when MMC core + * layer tries to set it to 3.3V before card detection happens, the + * IRQ doesn't get triggered as there is no state change in this bit. + * The driver already handles this case by changing the IO voltage + * level to high as part of controller power up sequence. Hence, check + * for host->pwr to handle a case where IO voltage high request is + * issued even before controller power up. + */ + if (req_type & (REQ_IO_HIGH | REQ_IO_LOW)) { + if (!(io_sig_sts & SWITCHABLE_SIGNALLING_VOL) || + ((req_type & REQ_IO_HIGH) && !host->pwr)) { + pr_debug("%s: do not wait for power IRQ that never comes\n", + mmc_hostname(host->mmc)); + spin_unlock_irqrestore(&host->lock, flags); + return; + } + } + + if ((req_type & msm_host->curr_pwr_state) || + (req_type & msm_host->curr_io_level)) + done = true; + spin_unlock_irqrestore(&host->lock, flags); + + /* + * This is needed here to hanlde a case where IRQ gets + * triggered even before this function is called so that + * x->done counter of completion gets reset. Otherwise, + * next call to wait_for_completion returns immediately + * without actually waiting for the IRQ to be handled. + */ + if (done) + init_completion(&msm_host->pwr_irq_completion); + else if (!wait_for_completion_timeout(&msm_host->pwr_irq_completion, + msecs_to_jiffies(MSM_PWR_IRQ_TIMEOUT_MS))) { + __WARN_printf("%s: request(%d) timed out waiting for pwr_irq\n", + mmc_hostname(host->mmc), req_type); + MMC_TRACE(host->mmc, + "%s: request(%d) timed out waiting for pwr_irq\n", + __func__, req_type); + sdhci_msm_dump_pwr_ctrl_regs(host); + } + pr_debug("%s: %s: request %d done\n", mmc_hostname(host->mmc), + __func__, req_type); +} + +static void sdhci_msm_toggle_cdr(struct sdhci_host *host, bool enable) +{ + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); + struct sdhci_msm_host *msm_host = pltfm_host->priv; + const struct sdhci_msm_offset *msm_host_offset = + msm_host->offset; + u32 config = readl_relaxed(host->ioaddr + + msm_host_offset->CORE_DLL_CONFIG); + + if (enable) { + config |= CORE_CDR_EN; + config &= ~CORE_CDR_EXT_EN; + writel_relaxed(config, host->ioaddr + + msm_host_offset->CORE_DLL_CONFIG); + } else { + config &= ~CORE_CDR_EN; + config |= CORE_CDR_EXT_EN; + writel_relaxed(config, host->ioaddr + + msm_host_offset->CORE_DLL_CONFIG); + } +} + +static unsigned int sdhci_msm_max_segs(void) +{ + return SDHCI_MSM_MAX_SEGMENTS; +} + +static unsigned int sdhci_msm_get_min_clock(struct sdhci_host *host) +{ + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); + struct sdhci_msm_host *msm_host = pltfm_host->priv; + + return msm_host->pdata->sup_clk_table[0]; +} + +static unsigned int sdhci_msm_get_max_clock(struct sdhci_host *host) +{ + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); + struct sdhci_msm_host *msm_host = pltfm_host->priv; + int max_clk_index = msm_host->pdata->sup_clk_cnt; + + return msm_host->pdata->sup_clk_table[max_clk_index - 1]; +} + +static unsigned int sdhci_msm_get_sup_clk_rate(struct sdhci_host *host, + u32 req_clk) +{ + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); + struct sdhci_msm_host *msm_host = pltfm_host->priv; + unsigned int sel_clk = -1; + unsigned char cnt; + + if (req_clk < sdhci_msm_get_min_clock(host)) { + sel_clk = sdhci_msm_get_min_clock(host); + return sel_clk; + } + + for (cnt = 0; cnt < msm_host->pdata->sup_clk_cnt; cnt++) { + if (msm_host->pdata->sup_clk_table[cnt] > req_clk) { + break; + } else if (msm_host->pdata->sup_clk_table[cnt] == req_clk) { + sel_clk = msm_host->pdata->sup_clk_table[cnt]; + break; + } else { + sel_clk = msm_host->pdata->sup_clk_table[cnt]; + } + } + return sel_clk; +} + +static int sdhci_msm_enable_controller_clock(struct sdhci_host *host) +{ + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); + struct sdhci_msm_host *msm_host = pltfm_host->priv; + int rc = 0; + + if (atomic_read(&msm_host->controller_clock)) + return 0; + + sdhci_msm_bus_voting(host, 1); + + if (!IS_ERR(msm_host->pclk)) { + rc = clk_prepare_enable(msm_host->pclk); + if (rc) { + pr_err("%s: %s: failed to enable the pclk with error %d\n", + mmc_hostname(host->mmc), __func__, rc); + goto remove_vote; + } + } + + rc = clk_prepare_enable(msm_host->clk); + if (rc) { + pr_err("%s: %s: failed to enable the host-clk with error %d\n", + mmc_hostname(host->mmc), __func__, rc); + goto disable_pclk; + } + + if (!IS_ERR(msm_host->ice_clk)) { + rc = clk_prepare_enable(msm_host->ice_clk); + if (rc) { + pr_err("%s: %s: failed to enable the ice-clk with error %d\n", + mmc_hostname(host->mmc), __func__, rc); + goto disable_host_clk; + } + } + atomic_set(&msm_host->controller_clock, 1); + pr_debug("%s: %s: enabled controller clock\n", + mmc_hostname(host->mmc), __func__); + goto out; + +disable_host_clk: + if (!IS_ERR(msm_host->clk)) + clk_disable_unprepare(msm_host->clk); +disable_pclk: + if (!IS_ERR(msm_host->pclk)) + clk_disable_unprepare(msm_host->pclk); +remove_vote: + if (msm_host->msm_bus_vote.client_handle) + sdhci_msm_bus_cancel_work_and_set_vote(host, 0); +out: + return rc; +} + +static void sdhci_msm_disable_controller_clock(struct sdhci_host *host) +{ + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); + struct sdhci_msm_host *msm_host = pltfm_host->priv; + + if (atomic_read(&msm_host->controller_clock)) { + if (!IS_ERR(msm_host->clk)) + clk_disable_unprepare(msm_host->clk); + if (!IS_ERR(msm_host->pclk)) + clk_disable_unprepare(msm_host->pclk); + if (!IS_ERR(msm_host->ice_clk)) + clk_disable_unprepare(msm_host->ice_clk); + sdhci_msm_bus_voting(host, 0); + atomic_set(&msm_host->controller_clock, 0); + pr_debug("%s: %s: disabled controller clock\n", + mmc_hostname(host->mmc), __func__); + } +} + +static int sdhci_msm_prepare_clocks(struct sdhci_host *host, bool enable) +{ + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); + struct sdhci_msm_host *msm_host = pltfm_host->priv; + int rc = 0; + + if (enable && !atomic_read(&msm_host->clks_on)) { + pr_debug("%s: request to enable clocks\n", + mmc_hostname(host->mmc)); + + /* + * The bus-width or the clock rate might have changed + * after controller clocks are enbaled, update bus vote + * in such case. + */ + if (atomic_read(&msm_host->controller_clock)) + sdhci_msm_bus_voting(host, 1); + + rc = sdhci_msm_enable_controller_clock(host); + if (rc) + goto remove_vote; + + if (!IS_ERR_OR_NULL(msm_host->bus_clk)) { + rc = clk_prepare_enable(msm_host->bus_clk); + if (rc) { + pr_err("%s: %s: failed to enable the bus-clock with error %d\n", + mmc_hostname(host->mmc), __func__, rc); + goto disable_controller_clk; + } + } + if (!IS_ERR(msm_host->ff_clk)) { + rc = clk_prepare_enable(msm_host->ff_clk); + if (rc) { + pr_err("%s: %s: failed to enable the ff_clk with error %d\n", + mmc_hostname(host->mmc), __func__, rc); + goto disable_bus_clk; + } + } + if (!IS_ERR(msm_host->sleep_clk)) { + rc = clk_prepare_enable(msm_host->sleep_clk); + if (rc) { + pr_err("%s: %s: failed to enable the sleep_clk with error %d\n", + mmc_hostname(host->mmc), __func__, rc); + goto disable_ff_clk; + } + } + mb(); + + } else if (!enable && atomic_read(&msm_host->clks_on)) { + sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL); + mb(); + /* + * During 1.8V signal switching the clock source must + * still be ON as it requires accessing SDHC + * registers (SDHCi host control2 register bit 3 must + * be written and polled after stopping the SDCLK). + */ + if (host->mmc->card_clock_off) + return 0; + pr_debug("%s: request to disable clocks\n", + mmc_hostname(host->mmc)); + if (!IS_ERR_OR_NULL(msm_host->sleep_clk)) + clk_disable_unprepare(msm_host->sleep_clk); + if (!IS_ERR_OR_NULL(msm_host->ff_clk)) + clk_disable_unprepare(msm_host->ff_clk); + clk_disable_unprepare(msm_host->clk); + if (!IS_ERR(msm_host->ice_clk)) + clk_disable_unprepare(msm_host->ice_clk); + if (!IS_ERR(msm_host->pclk)) + clk_disable_unprepare(msm_host->pclk); + if (!IS_ERR_OR_NULL(msm_host->bus_clk)) + clk_disable_unprepare(msm_host->bus_clk); + + atomic_set(&msm_host->controller_clock, 0); + sdhci_msm_bus_voting(host, 0); + } + atomic_set(&msm_host->clks_on, enable); + goto out; +disable_ff_clk: + if (!IS_ERR_OR_NULL(msm_host->ff_clk)) + clk_disable_unprepare(msm_host->ff_clk); +disable_bus_clk: + if (!IS_ERR_OR_NULL(msm_host->bus_clk)) + clk_disable_unprepare(msm_host->bus_clk); +disable_controller_clk: + if (!IS_ERR_OR_NULL(msm_host->clk)) + clk_disable_unprepare(msm_host->clk); + if (!IS_ERR(msm_host->ice_clk)) + clk_disable_unprepare(msm_host->ice_clk); + if (!IS_ERR_OR_NULL(msm_host->pclk)) + clk_disable_unprepare(msm_host->pclk); + atomic_set(&msm_host->controller_clock, 0); +remove_vote: + if (msm_host->msm_bus_vote.client_handle) + sdhci_msm_bus_cancel_work_and_set_vote(host, 0); +out: + return rc; +} + +static void sdhci_msm_set_clock(struct sdhci_host *host, unsigned int clock) +{ + int rc; + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); + struct sdhci_msm_host *msm_host = pltfm_host->priv; + const struct sdhci_msm_offset *msm_host_offset = + msm_host->offset; + struct mmc_card *card = host->mmc->card; + struct mmc_ios curr_ios = host->mmc->ios; + u32 sup_clock, ddr_clock, dll_lock; + bool curr_pwrsave; + + if (!clock) { + /* + * disable pwrsave to ensure clock is not auto-gated until + * the rate is >400KHz (initialization complete). + */ + writel_relaxed(readl_relaxed(host->ioaddr + + msm_host_offset->CORE_VENDOR_SPEC) & + ~CORE_CLK_PWRSAVE, host->ioaddr + + msm_host_offset->CORE_VENDOR_SPEC); + sdhci_msm_prepare_clocks(host, false); + host->clock = clock; + goto out; + } + + rc = sdhci_msm_prepare_clocks(host, true); + if (rc) + goto out; + + curr_pwrsave = !!(readl_relaxed(host->ioaddr + + msm_host_offset->CORE_VENDOR_SPEC) & CORE_CLK_PWRSAVE); + if ((clock > 400000) && + !curr_pwrsave && card && mmc_host_may_gate_card(card)) + writel_relaxed(readl_relaxed(host->ioaddr + + msm_host_offset->CORE_VENDOR_SPEC) + | CORE_CLK_PWRSAVE, host->ioaddr + + msm_host_offset->CORE_VENDOR_SPEC); + /* + * Disable pwrsave for a newly added card if doesn't allow clock + * gating. + */ + else if (curr_pwrsave && card && !mmc_host_may_gate_card(card)) + writel_relaxed(readl_relaxed(host->ioaddr + + msm_host_offset->CORE_VENDOR_SPEC) + & ~CORE_CLK_PWRSAVE, host->ioaddr + + msm_host_offset->CORE_VENDOR_SPEC); + + sup_clock = sdhci_msm_get_sup_clk_rate(host, clock); + if ((curr_ios.timing == MMC_TIMING_UHS_DDR50) || + (curr_ios.timing == MMC_TIMING_MMC_DDR52) || + (curr_ios.timing == MMC_TIMING_MMC_HS400)) { + /* + * The SDHC requires internal clock frequency to be double the + * actual clock that will be set for DDR mode. The controller + * uses the faster clock(100/400MHz) for some of its parts and + * send the actual required clock (50/200MHz) to the card. + */ + ddr_clock = clock * 2; + sup_clock = sdhci_msm_get_sup_clk_rate(host, + ddr_clock); + } + + /* + * In general all timing modes are controlled via UHS mode select in + * Host Control2 register. eMMC specific HS200/HS400 doesn't have + * their respective modes defined here, hence we use these values. + * + * HS200 - SDR104 (Since they both are equivalent in functionality) + * HS400 - This involves multiple configurations + * Initially SDR104 - when tuning is required as HS200 + * Then when switching to DDR @ 400MHz (HS400) we use + * the vendor specific HC_SELECT_IN to control the mode. + * + * In addition to controlling the modes we also need to select the + * correct input clock for DLL depending on the mode. + * + * HS400 - divided clock (free running MCLK/2) + * All other modes - default (free running MCLK) + */ + if (curr_ios.timing == MMC_TIMING_MMC_HS400) { + /* Select the divided clock (free running MCLK/2) */ + writel_relaxed(((readl_relaxed(host->ioaddr + + msm_host_offset->CORE_VENDOR_SPEC) + & ~CORE_HC_MCLK_SEL_MASK) + | CORE_HC_MCLK_SEL_HS400), host->ioaddr + + msm_host_offset->CORE_VENDOR_SPEC); + /* + * Select HS400 mode using the HC_SELECT_IN from VENDOR SPEC + * register + */ + if ((msm_host->tuning_done || + (card && mmc_card_strobe(card) && + msm_host->enhanced_strobe)) && + !msm_host->calibration_done) { + /* + * Write 0x6 to HC_SELECT_IN and 1 to HC_SELECT_IN_EN + * field in VENDOR_SPEC_FUNC + */ + writel_relaxed((readl_relaxed(host->ioaddr + \ + msm_host_offset->CORE_VENDOR_SPEC) + | CORE_HC_SELECT_IN_HS400 + | CORE_HC_SELECT_IN_EN), host->ioaddr + + msm_host_offset->CORE_VENDOR_SPEC); + } + if (!host->mmc->ios.old_rate && !msm_host->use_cdclp533) { + /* + * Poll on DLL_LOCK and DDR_DLL_LOCK bits in + * CORE_DLL_STATUS to be set. This should get set + * with in 15 us at 200 MHz. + */ + rc = readl_poll_timeout(host->ioaddr + + msm_host_offset->CORE_DLL_STATUS, + dll_lock, (dll_lock & (CORE_DLL_LOCK | + CORE_DDR_DLL_LOCK)), 10, 1000); + if (rc == -ETIMEDOUT) + pr_err("%s: Unable to get DLL_LOCK/DDR_DLL_LOCK, dll_status: 0x%08x\n", + mmc_hostname(host->mmc), + dll_lock); + } + } else { + if (!msm_host->use_cdclp533) + /* set CORE_PWRSAVE_DLL bit in CORE_VENDOR_SPEC3 */ + writel_relaxed((readl_relaxed(host->ioaddr + + msm_host_offset->CORE_VENDOR_SPEC3) + & ~CORE_PWRSAVE_DLL), host->ioaddr + + msm_host_offset->CORE_VENDOR_SPEC3); + + /* Select the default clock (free running MCLK) */ + writel_relaxed(((readl_relaxed(host->ioaddr + + msm_host_offset->CORE_VENDOR_SPEC) + & ~CORE_HC_MCLK_SEL_MASK) + | CORE_HC_MCLK_SEL_DFLT), host->ioaddr + + msm_host_offset->CORE_VENDOR_SPEC); + + /* + * Disable HC_SELECT_IN to be able to use the UHS mode select + * configuration from Host Control2 register for all other + * modes. + * + * Write 0 to HC_SELECT_IN and HC_SELECT_IN_EN field + * in VENDOR_SPEC_FUNC + */ + writel_relaxed((readl_relaxed(host->ioaddr + + msm_host_offset->CORE_VENDOR_SPEC) + & ~CORE_HC_SELECT_IN_EN + & ~CORE_HC_SELECT_IN_MASK), host->ioaddr + + msm_host_offset->CORE_VENDOR_SPEC); + } + mb(); + + if (sup_clock != msm_host->clk_rate) { + pr_debug("%s: %s: setting clk rate to %u\n", + mmc_hostname(host->mmc), __func__, sup_clock); + rc = clk_set_rate(msm_host->clk, sup_clock); + if (rc) { + pr_err("%s: %s: Failed to set rate %u for host-clk : %d\n", + mmc_hostname(host->mmc), __func__, + sup_clock, rc); + goto out; + } + msm_host->clk_rate = sup_clock; + host->clock = clock; + /* + * Update the bus vote in case of frequency change due to + * clock scaling. + */ + sdhci_msm_bus_voting(host, 1); + } +out: + sdhci_set_clock(host, clock); +} + +static void sdhci_msm_set_uhs_signaling(struct sdhci_host *host, + unsigned int uhs) +{ + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); + struct sdhci_msm_host *msm_host = pltfm_host->priv; + const struct sdhci_msm_offset *msm_host_offset = + msm_host->offset; + u16 ctrl_2; + + ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); + /* Select Bus Speed Mode for host */ + ctrl_2 &= ~SDHCI_CTRL_UHS_MASK; + if ((uhs == MMC_TIMING_MMC_HS400) || + (uhs == MMC_TIMING_MMC_HS200) || + (uhs == MMC_TIMING_UHS_SDR104)) + ctrl_2 |= SDHCI_CTRL_UHS_SDR104; + else if (uhs == MMC_TIMING_UHS_SDR12) + ctrl_2 |= SDHCI_CTRL_UHS_SDR12; + else if (uhs == MMC_TIMING_UHS_SDR25) + ctrl_2 |= SDHCI_CTRL_UHS_SDR25; + else if (uhs == MMC_TIMING_UHS_SDR50) + ctrl_2 |= SDHCI_CTRL_UHS_SDR50; + else if ((uhs == MMC_TIMING_UHS_DDR50) || + (uhs == MMC_TIMING_MMC_DDR52)) + ctrl_2 |= SDHCI_CTRL_UHS_DDR50; + /* + * When clock frquency is less than 100MHz, the feedback clock must be + * provided and DLL must not be used so that tuning can be skipped. To + * provide feedback clock, the mode selection can be any value less + * than 3'b011 in bits [2:0] of HOST CONTROL2 register. + */ + if (host->clock <= CORE_FREQ_100MHZ) { + if ((uhs == MMC_TIMING_MMC_HS400) || + (uhs == MMC_TIMING_MMC_HS200) || + (uhs == MMC_TIMING_UHS_SDR104)) + ctrl_2 &= ~SDHCI_CTRL_UHS_MASK; + + /* + * Make sure DLL is disabled when not required + * + * Write 1 to DLL_RST bit of DLL_CONFIG register + */ + writel_relaxed((readl_relaxed(host->ioaddr + + msm_host_offset->CORE_DLL_CONFIG) + | CORE_DLL_RST), host->ioaddr + + msm_host_offset->CORE_DLL_CONFIG); + + /* Write 1 to DLL_PDN bit of DLL_CONFIG register */ + writel_relaxed((readl_relaxed(host->ioaddr + + msm_host_offset->CORE_DLL_CONFIG) + | CORE_DLL_PDN), host->ioaddr + + msm_host_offset->CORE_DLL_CONFIG); + mb(); + + /* + * The DLL needs to be restored and CDCLP533 recalibrated + * when the clock frequency is set back to 400MHz. + */ + msm_host->calibration_done = false; + } + + pr_debug("%s: %s-clock:%u uhs mode:%u ctrl_2:0x%x\n", + mmc_hostname(host->mmc), __func__, host->clock, uhs, ctrl_2); + sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); + +} + +#define MAX_TEST_BUS 60 +#define DRV_NAME "cmdq-host" +static void sdhci_msm_cmdq_dump_debug_ram(struct sdhci_host *host) +{ + int i = 0; + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); + struct sdhci_msm_host *msm_host = pltfm_host->priv; + const struct sdhci_msm_offset *msm_host_offset = + msm_host->offset; + struct cmdq_host *cq_host = host->cq_host; + + u32 version = sdhci_msm_readl_relaxed(host, + msm_host_offset->CORE_MCI_VERSION); + u16 minor = version & CORE_VERSION_TARGET_MASK; + /* registers offset changed starting from 4.2.0 */ + int offset = minor >= SDHCI_MSM_VER_420 ? 0 : 0x48; + + if (cq_host->offset_changed) + offset += CQ_V5_VENDOR_CFG; + pr_err("---- Debug RAM dump ----\n"); + pr_err(DRV_NAME ": Debug RAM wrap-around: 0x%08x | Debug RAM overlap: 0x%08x\n", + cmdq_readl(cq_host, CQ_CMD_DBG_RAM_WA + offset), + cmdq_readl(cq_host, CQ_CMD_DBG_RAM_OL + offset)); + + while (i < 16) { + pr_err(DRV_NAME ": Debug RAM dump [%d]: 0x%08x\n", i, + cmdq_readl(cq_host, CQ_CMD_DBG_RAM + offset + (4 * i))); + i++; + } + pr_err("-------------------------\n"); +} + +static void sdhci_msm_cache_debug_data(struct sdhci_host *host) +{ + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); + struct sdhci_msm_host *msm_host = pltfm_host->priv; + struct sdhci_msm_debug_data *cached_data = &msm_host->cached_data; + + memcpy(&cached_data->copy_mmc, msm_host->mmc, + sizeof(struct mmc_host)); + if (msm_host->mmc->card) + memcpy(&cached_data->copy_card, msm_host->mmc->card, + sizeof(struct mmc_card)); + memcpy(&cached_data->copy_host, host, + sizeof(struct sdhci_host)); +} + +void sdhci_msm_dump_vendor_regs(struct sdhci_host *host) +{ + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); + struct sdhci_msm_host *msm_host = pltfm_host->priv; + const struct sdhci_msm_offset *msm_host_offset = + msm_host->offset; + int tbsel, tbsel2; + int i, index = 0; + u32 test_bus_val = 0; + u32 debug_reg[MAX_TEST_BUS] = {0}; + u32 sts = 0; + + sdhci_msm_cache_debug_data(host); + pr_info("----------- VENDOR REGISTER DUMP -----------\n"); + if (host->cq_host) + sdhci_msm_cmdq_dump_debug_ram(host); + + MMC_TRACE(host->mmc, "Data cnt: 0x%08x | Fifo cnt: 0x%08x\n", + sdhci_msm_readl_relaxed(host, + msm_host_offset->CORE_MCI_DATA_CNT), + sdhci_msm_readl_relaxed(host, + msm_host_offset->CORE_MCI_FIFO_CNT)); + pr_info("Data cnt: 0x%08x | Fifo cnt: 0x%08x | Int sts: 0x%08x\n", + sdhci_msm_readl_relaxed(host, + msm_host_offset->CORE_MCI_DATA_CNT), + sdhci_msm_readl_relaxed(host, + msm_host_offset->CORE_MCI_FIFO_CNT), + sdhci_msm_readl_relaxed(host, + msm_host_offset->CORE_MCI_STATUS)); + pr_info("DLL cfg: 0x%08x | DLL sts: 0x%08x | SDCC ver: 0x%08x\n", + readl_relaxed(host->ioaddr + + msm_host_offset->CORE_DLL_CONFIG), + readl_relaxed(host->ioaddr + + msm_host_offset->CORE_DLL_STATUS), + sdhci_msm_readl_relaxed(host, + msm_host_offset->CORE_MCI_VERSION)); + pr_info("Vndr func: 0x%08x | Vndr adma err : addr0: 0x%08x addr1: 0x%08x\n", + readl_relaxed(host->ioaddr + + msm_host_offset->CORE_VENDOR_SPEC), + readl_relaxed(host->ioaddr + + msm_host_offset->CORE_VENDOR_SPEC_ADMA_ERR_ADDR0), + readl_relaxed(host->ioaddr + + msm_host_offset->CORE_VENDOR_SPEC_ADMA_ERR_ADDR1)); + pr_info("Vndr func2: 0x%08x\n", + readl_relaxed(host->ioaddr + + msm_host_offset->CORE_VENDOR_SPEC_FUNC2)); + + /* + * tbsel indicates [2:0] bits and tbsel2 indicates [7:4] bits + * of CORE_TESTBUS_CONFIG register. + * + * To select test bus 0 to 7 use tbsel and to select any test bus + * above 7 use (tbsel2 | tbsel) to get the test bus number. For eg, + * to select test bus 14, write 0x1E to CORE_TESTBUS_CONFIG register + * i.e., tbsel2[7:4] = 0001, tbsel[2:0] = 110. + */ + for (tbsel2 = 0; tbsel2 < 7; tbsel2++) { + for (tbsel = 0; tbsel < 8; tbsel++) { + if (index >= MAX_TEST_BUS) + break; + test_bus_val = + (tbsel2 << msm_host_offset->CORE_TESTBUS_SEL2_BIT) | + tbsel | msm_host_offset->CORE_TESTBUS_ENA; + sdhci_msm_writel_relaxed(test_bus_val, host, + msm_host_offset->CORE_TESTBUS_CONFIG); + debug_reg[index++] = sdhci_msm_readl_relaxed(host, + msm_host_offset->CORE_SDCC_DEBUG_REG); + } + } + for (i = 0; i < MAX_TEST_BUS; i = i + 4) + pr_info(" Test bus[%d to %d]: 0x%08x 0x%08x 0x%08x 0x%08x\n", + i, i + 3, debug_reg[i], debug_reg[i+1], + debug_reg[i+2], debug_reg[i+3]); + if (host->is_crypto_en) { + sdhci_msm_ice_get_status(host, &sts); + pr_info("%s: ICE status %x\n", mmc_hostname(host->mmc), sts); + sdhci_msm_ice_print_regs(host); + } +} + +void sdhci_msm_reset(struct sdhci_host *host, u8 mask) +{ + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); + struct sdhci_msm_host *msm_host = pltfm_host->priv; + + /* Set ICE core to be reset in sync with SDHC core */ + if (msm_host->ice.pdev) { + if (msm_host->ice_hci_support) + writel_relaxed(1, host->ioaddr + + HC_VENDOR_SPECIFIC_ICE_CTRL); + else + writel_relaxed(1, + host->ioaddr + CORE_VENDOR_SPEC_ICE_CTRL); + } + + sdhci_reset(host, mask); +} + +/* + * sdhci_msm_enhanced_strobe_mask :- + * Before running CMDQ transfers in HS400 Enhanced Strobe mode, + * SW should write 3 to + * HC_VENDOR_SPECIFIC_FUNC3.CMDEN_HS400_INPUT_MASK_CNT register. + * The default reset value of this register is 2. + */ +static void sdhci_msm_enhanced_strobe_mask(struct sdhci_host *host, bool set) +{ + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); + struct sdhci_msm_host *msm_host = pltfm_host->priv; + const struct sdhci_msm_offset *msm_host_offset = + msm_host->offset; + + if (!msm_host->enhanced_strobe || + !mmc_card_strobe(msm_host->mmc->card)) { + pr_debug("%s: host/card does not support hs400 enhanced strobe\n", + mmc_hostname(host->mmc)); + return; + } + + if (set) { + writel_relaxed((readl_relaxed(host->ioaddr + + msm_host_offset->CORE_VENDOR_SPEC3) + | CORE_CMDEN_HS400_INPUT_MASK_CNT), + host->ioaddr + msm_host_offset->CORE_VENDOR_SPEC3); + } else { + writel_relaxed((readl_relaxed(host->ioaddr + + msm_host_offset->CORE_VENDOR_SPEC3) + & ~CORE_CMDEN_HS400_INPUT_MASK_CNT), + host->ioaddr + msm_host_offset->CORE_VENDOR_SPEC3); + } +} + +static void sdhci_msm_clear_set_dumpregs(struct sdhci_host *host, bool set) +{ + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); + struct sdhci_msm_host *msm_host = pltfm_host->priv; + const struct sdhci_msm_offset *msm_host_offset = + msm_host->offset; + + if (set) { + sdhci_msm_writel_relaxed(msm_host_offset->CORE_TESTBUS_ENA, + host, msm_host_offset->CORE_TESTBUS_CONFIG); + } else { + u32 value; + value = sdhci_msm_readl_relaxed(host, + msm_host_offset->CORE_TESTBUS_CONFIG); + value &= ~(msm_host_offset->CORE_TESTBUS_ENA); + sdhci_msm_writel_relaxed(value, host, + msm_host_offset->CORE_TESTBUS_CONFIG); + } +} + +int sdhci_msm_notify_load(struct sdhci_host *host, enum mmc_load state) +{ + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); + struct sdhci_msm_host *msm_host = pltfm_host->priv; + int ret = 0; + u32 clk_rate = 0; + + if (!IS_ERR(msm_host->ice_clk)) { + clk_rate = (state == MMC_LOAD_LOW) ? + msm_host->pdata->ice_clk_min : + msm_host->pdata->ice_clk_max; + if (msm_host->ice_clk_rate == clk_rate) + return 0; + pr_debug("%s: changing ICE clk rate to %u\n", + mmc_hostname(host->mmc), clk_rate); + ret = clk_set_rate(msm_host->ice_clk, clk_rate); + if (ret) { + pr_err("%s: ICE_CLK rate set failed (%d) for %u\n", + mmc_hostname(host->mmc), ret, clk_rate); + return ret; + } + msm_host->ice_clk_rate = clk_rate; + } + return 0; +} + +void sdhci_msm_reset_workaround(struct sdhci_host *host, u32 enable) +{ + u32 vendor_func2; + unsigned long timeout; + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); + struct sdhci_msm_host *msm_host = pltfm_host->priv; + const struct sdhci_msm_offset *msm_host_offset = + msm_host->offset; + + vendor_func2 = readl_relaxed(host->ioaddr + + msm_host_offset->CORE_VENDOR_SPEC_FUNC2); + + if (enable) { + writel_relaxed(vendor_func2 | HC_SW_RST_REQ, host->ioaddr + + msm_host_offset->CORE_VENDOR_SPEC_FUNC2); + timeout = 10000; + while (readl_relaxed(host->ioaddr + + msm_host_offset->CORE_VENDOR_SPEC_FUNC2) & HC_SW_RST_REQ) { + if (timeout == 0) { + pr_info("%s: Applying wait idle disable workaround\n", + mmc_hostname(host->mmc)); + /* + * Apply the reset workaround to not wait for + * pending data transfers on AXI before + * resetting the controller. This could be + * risky if the transfers were stuck on the + * AXI bus. + */ + vendor_func2 = readl_relaxed(host->ioaddr + + msm_host_offset->CORE_VENDOR_SPEC_FUNC2); + writel_relaxed(vendor_func2 | + HC_SW_RST_WAIT_IDLE_DIS, host->ioaddr + + msm_host_offset->CORE_VENDOR_SPEC_FUNC2); + host->reset_wa_t = ktime_get(); + return; + } + timeout--; + udelay(10); + } + pr_info("%s: waiting for SW_RST_REQ is successful\n", + mmc_hostname(host->mmc)); + } else { + writel_relaxed(vendor_func2 & ~HC_SW_RST_WAIT_IDLE_DIS, + host->ioaddr + msm_host_offset->CORE_VENDOR_SPEC_FUNC2); + } +} + +static void sdhci_msm_pm_qos_irq_unvote_work(struct work_struct *work) +{ + struct sdhci_msm_pm_qos_irq *pm_qos_irq = + container_of(work, struct sdhci_msm_pm_qos_irq, + unvote_work.work); + + if (atomic_read(&pm_qos_irq->counter)) + return; + + pm_qos_irq->latency = PM_QOS_DEFAULT_VALUE; + pm_qos_update_request(&pm_qos_irq->req, pm_qos_irq->latency); +} + +void sdhci_msm_pm_qos_irq_vote(struct sdhci_host *host) +{ + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); + struct sdhci_msm_host *msm_host = pltfm_host->priv; + struct sdhci_msm_pm_qos_latency *latency = + &msm_host->pdata->pm_qos_data.irq_latency; + int counter; + + if (!msm_host->pm_qos_irq.enabled) + return; + + counter = atomic_inc_return(&msm_host->pm_qos_irq.counter); + /* Make sure to update the voting in case power policy has changed */ + if (msm_host->pm_qos_irq.latency == latency->latency[host->power_policy] + && counter > 1) + return; + + cancel_delayed_work_sync(&msm_host->pm_qos_irq.unvote_work); + msm_host->pm_qos_irq.latency = latency->latency[host->power_policy]; + pm_qos_update_request(&msm_host->pm_qos_irq.req, + msm_host->pm_qos_irq.latency); +} + +void sdhci_msm_pm_qos_irq_unvote(struct sdhci_host *host, bool async) +{ + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); + struct sdhci_msm_host *msm_host = pltfm_host->priv; + int counter; + + if (!msm_host->pm_qos_irq.enabled) + return; + + if (atomic_read(&msm_host->pm_qos_irq.counter)) { + counter = atomic_dec_return(&msm_host->pm_qos_irq.counter); + } else { + WARN(1, "attempt to decrement pm_qos_irq.counter when it's 0"); + return; + } + + if (counter) + return; + + if (async) { + schedule_delayed_work(&msm_host->pm_qos_irq.unvote_work, + msecs_to_jiffies(QOS_REMOVE_DELAY_MS)); + return; + } + + msm_host->pm_qos_irq.latency = PM_QOS_DEFAULT_VALUE; + pm_qos_update_request(&msm_host->pm_qos_irq.req, + msm_host->pm_qos_irq.latency); +} + +static ssize_t +sdhci_msm_pm_qos_irq_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct sdhci_host *host = dev_get_drvdata(dev); + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); + struct sdhci_msm_host *msm_host = pltfm_host->priv; + struct sdhci_msm_pm_qos_irq *irq = &msm_host->pm_qos_irq; + + return snprintf(buf, PAGE_SIZE, + "IRQ PM QoS: enabled=%d, counter=%d, latency=%d\n", + irq->enabled, atomic_read(&irq->counter), irq->latency); +} + +static ssize_t +sdhci_msm_pm_qos_irq_enable_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct sdhci_host *host = dev_get_drvdata(dev); + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); + struct sdhci_msm_host *msm_host = pltfm_host->priv; + + return snprintf(buf, PAGE_SIZE, "%u\n", msm_host->pm_qos_irq.enabled); +} + +static ssize_t +sdhci_msm_pm_qos_irq_enable_store(struct device *dev, + struct device_attribute *attr, const char *buf, size_t count) +{ + struct sdhci_host *host = dev_get_drvdata(dev); + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); + struct sdhci_msm_host *msm_host = pltfm_host->priv; + uint32_t value; + bool enable; + int ret; + + ret = kstrtou32(buf, 0, &value); + if (ret) + goto out; + enable = !!value; + + if (enable == msm_host->pm_qos_irq.enabled) + goto out; + + msm_host->pm_qos_irq.enabled = enable; + if (!enable) { + cancel_delayed_work_sync(&msm_host->pm_qos_irq.unvote_work); + atomic_set(&msm_host->pm_qos_irq.counter, 0); + msm_host->pm_qos_irq.latency = PM_QOS_DEFAULT_VALUE; + pm_qos_update_request(&msm_host->pm_qos_irq.req, + msm_host->pm_qos_irq.latency); + } + +out: + return count; +} + +#ifdef CONFIG_SMP +static inline void set_affine_irq(struct sdhci_msm_host *msm_host, + struct sdhci_host *host) +{ + msm_host->pm_qos_irq.req.irq = host->irq; +} +#else +static inline void set_affine_irq(struct sdhci_msm_host *msm_host, + struct sdhci_host *host) { } +#endif + +void sdhci_msm_pm_qos_irq_init(struct sdhci_host *host) +{ + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); + struct sdhci_msm_host *msm_host = pltfm_host->priv; + struct sdhci_msm_pm_qos_latency *irq_latency; + int ret; + + if (!msm_host->pdata->pm_qos_data.irq_valid) + return; + + /* Initialize only once as this gets called per partition */ + if (msm_host->pm_qos_irq.enabled) + return; + + atomic_set(&msm_host->pm_qos_irq.counter, 0); + msm_host->pm_qos_irq.req.type = + msm_host->pdata->pm_qos_data.irq_req_type; + if ((msm_host->pm_qos_irq.req.type != PM_QOS_REQ_AFFINE_CORES) && + (msm_host->pm_qos_irq.req.type != PM_QOS_REQ_ALL_CORES)) + set_affine_irq(msm_host, host); + else + cpumask_copy(&msm_host->pm_qos_irq.req.cpus_affine, + cpumask_of(msm_host->pdata->pm_qos_data.irq_cpu)); + + INIT_DELAYED_WORK(&msm_host->pm_qos_irq.unvote_work, + sdhci_msm_pm_qos_irq_unvote_work); + /* For initialization phase, set the performance latency */ + irq_latency = &msm_host->pdata->pm_qos_data.irq_latency; + msm_host->pm_qos_irq.latency = + irq_latency->latency[SDHCI_PERFORMANCE_MODE]; + pm_qos_add_request(&msm_host->pm_qos_irq.req, PM_QOS_CPU_DMA_LATENCY, + msm_host->pm_qos_irq.latency); + msm_host->pm_qos_irq.enabled = true; + + /* sysfs */ + msm_host->pm_qos_irq.enable_attr.show = + sdhci_msm_pm_qos_irq_enable_show; + msm_host->pm_qos_irq.enable_attr.store = + sdhci_msm_pm_qos_irq_enable_store; + sysfs_attr_init(&msm_host->pm_qos_irq.enable_attr.attr); + msm_host->pm_qos_irq.enable_attr.attr.name = "pm_qos_irq_enable"; + msm_host->pm_qos_irq.enable_attr.attr.mode = S_IRUGO | S_IWUSR; + ret = device_create_file(&msm_host->pdev->dev, + &msm_host->pm_qos_irq.enable_attr); + if (ret) + pr_err("%s: fail to create pm_qos_irq_enable (%d)\n", + __func__, ret); + + msm_host->pm_qos_irq.status_attr.show = sdhci_msm_pm_qos_irq_show; + msm_host->pm_qos_irq.status_attr.store = NULL; + sysfs_attr_init(&msm_host->pm_qos_irq.status_attr.attr); + msm_host->pm_qos_irq.status_attr.attr.name = "pm_qos_irq_status"; + msm_host->pm_qos_irq.status_attr.attr.mode = S_IRUGO; + ret = device_create_file(&msm_host->pdev->dev, + &msm_host->pm_qos_irq.status_attr); + if (ret) + pr_err("%s: fail to create pm_qos_irq_status (%d)\n", + __func__, ret); +} + +static ssize_t sdhci_msm_pm_qos_group_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct sdhci_host *host = dev_get_drvdata(dev); + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); + struct sdhci_msm_host *msm_host = pltfm_host->priv; + struct sdhci_msm_pm_qos_group *group; + int i; + int nr_groups = msm_host->pdata->pm_qos_data.cpu_group_map.nr_groups; + int offset = 0; + + for (i = 0; i < nr_groups; i++) { + group = &msm_host->pm_qos[i]; + offset += snprintf(&buf[offset], PAGE_SIZE, + "Group #%d (mask=0x%lx) PM QoS: enabled=%d, counter=%d, latency=%d\n", + i, group->req.cpus_affine.bits[0], + msm_host->pm_qos_group_enable, + atomic_read(&group->counter), + group->latency); + } + + return offset; +} + +static ssize_t sdhci_msm_pm_qos_group_enable_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct sdhci_host *host = dev_get_drvdata(dev); + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); + struct sdhci_msm_host *msm_host = pltfm_host->priv; + + return snprintf(buf, PAGE_SIZE, "%s\n", + msm_host->pm_qos_group_enable ? "enabled" : "disabled"); +} + +static ssize_t sdhci_msm_pm_qos_group_enable_store(struct device *dev, + struct device_attribute *attr, const char *buf, size_t count) +{ + struct sdhci_host *host = dev_get_drvdata(dev); + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); + struct sdhci_msm_host *msm_host = pltfm_host->priv; + int nr_groups = msm_host->pdata->pm_qos_data.cpu_group_map.nr_groups; + uint32_t value; + bool enable; + int ret; + int i; + + ret = kstrtou32(buf, 0, &value); + if (ret) + goto out; + enable = !!value; + + if (enable == msm_host->pm_qos_group_enable) + goto out; + + msm_host->pm_qos_group_enable = enable; + if (!enable) { + for (i = 0; i < nr_groups; i++) { + cancel_delayed_work_sync( + &msm_host->pm_qos[i].unvote_work); + atomic_set(&msm_host->pm_qos[i].counter, 0); + msm_host->pm_qos[i].latency = PM_QOS_DEFAULT_VALUE; + pm_qos_update_request(&msm_host->pm_qos[i].req, + msm_host->pm_qos[i].latency); + } + } + +out: + return count; +} + +static int sdhci_msm_get_cpu_group(struct sdhci_msm_host *msm_host, int cpu) +{ + int i; + struct sdhci_msm_cpu_group_map *map = + &msm_host->pdata->pm_qos_data.cpu_group_map; + + if (cpu < 0) + goto not_found; + + for (i = 0; i < map->nr_groups; i++) + if (cpumask_test_cpu(cpu, &map->mask[i])) + return i; + +not_found: + return -EINVAL; +} + +void sdhci_msm_pm_qos_cpu_vote(struct sdhci_host *host, + struct sdhci_msm_pm_qos_latency *latency, int cpu) +{ + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); + struct sdhci_msm_host *msm_host = pltfm_host->priv; + int group = sdhci_msm_get_cpu_group(msm_host, cpu); + struct sdhci_msm_pm_qos_group *pm_qos_group; + int counter; + + if (!msm_host->pm_qos_group_enable || group < 0) + return; + + pm_qos_group = &msm_host->pm_qos[group]; + counter = atomic_inc_return(&pm_qos_group->counter); + + /* Make sure to update the voting in case power policy has changed */ + if (pm_qos_group->latency == latency->latency[host->power_policy] + && counter > 1) + return; + + cancel_delayed_work_sync(&pm_qos_group->unvote_work); + + pm_qos_group->latency = latency->latency[host->power_policy]; + pm_qos_update_request(&pm_qos_group->req, pm_qos_group->latency); +} + +static void sdhci_msm_pm_qos_cpu_unvote_work(struct work_struct *work) +{ + struct sdhci_msm_pm_qos_group *group = + container_of(work, struct sdhci_msm_pm_qos_group, + unvote_work.work); + + if (atomic_read(&group->counter)) + return; + + group->latency = PM_QOS_DEFAULT_VALUE; + pm_qos_update_request(&group->req, group->latency); +} + +bool sdhci_msm_pm_qos_cpu_unvote(struct sdhci_host *host, int cpu, bool async) +{ + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); + struct sdhci_msm_host *msm_host = pltfm_host->priv; + int group = sdhci_msm_get_cpu_group(msm_host, cpu); + + if (!msm_host->pm_qos_group_enable || group < 0 || + atomic_dec_return(&msm_host->pm_qos[group].counter)) + return false; + + if (async) { + schedule_delayed_work(&msm_host->pm_qos[group].unvote_work, + msecs_to_jiffies(QOS_REMOVE_DELAY_MS)); + return true; + } + + msm_host->pm_qos[group].latency = PM_QOS_DEFAULT_VALUE; + pm_qos_update_request(&msm_host->pm_qos[group].req, + msm_host->pm_qos[group].latency); + return true; +} + +void sdhci_msm_pm_qos_cpu_init(struct sdhci_host *host, + struct sdhci_msm_pm_qos_latency *latency) +{ + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); + struct sdhci_msm_host *msm_host = pltfm_host->priv; + int nr_groups = msm_host->pdata->pm_qos_data.cpu_group_map.nr_groups; + struct sdhci_msm_pm_qos_group *group; + int i; + int ret; + + if (msm_host->pm_qos_group_enable) + return; + + msm_host->pm_qos = kcalloc(nr_groups, sizeof(*msm_host->pm_qos), + GFP_KERNEL); + if (!msm_host->pm_qos) + return; + + for (i = 0; i < nr_groups; i++) { + group = &msm_host->pm_qos[i]; + INIT_DELAYED_WORK(&group->unvote_work, + sdhci_msm_pm_qos_cpu_unvote_work); + atomic_set(&group->counter, 0); + group->req.type = PM_QOS_REQ_AFFINE_CORES; + cpumask_copy(&group->req.cpus_affine, + &msm_host->pdata->pm_qos_data.cpu_group_map.mask[i]); + /* We set default latency here for all pm_qos cpu groups. */ + group->latency = PM_QOS_DEFAULT_VALUE; + pm_qos_add_request(&group->req, PM_QOS_CPU_DMA_LATENCY, + group->latency); + pr_info("%s (): voted for group #%d (mask=0x%lx) latency=%d\n", + __func__, i, + group->req.cpus_affine.bits[0], + group->latency); + } + msm_host->pm_qos_prev_cpu = -1; + msm_host->pm_qos_group_enable = true; + + /* sysfs */ + msm_host->pm_qos_group_status_attr.show = sdhci_msm_pm_qos_group_show; + msm_host->pm_qos_group_status_attr.store = NULL; + sysfs_attr_init(&msm_host->pm_qos_group_status_attr.attr); + msm_host->pm_qos_group_status_attr.attr.name = + "pm_qos_cpu_groups_status"; + msm_host->pm_qos_group_status_attr.attr.mode = S_IRUGO; + ret = device_create_file(&msm_host->pdev->dev, + &msm_host->pm_qos_group_status_attr); + if (ret) + dev_err(&msm_host->pdev->dev, "%s: fail to create pm_qos_group_status_attr (%d)\n", + __func__, ret); + msm_host->pm_qos_group_enable_attr.show = + sdhci_msm_pm_qos_group_enable_show; + msm_host->pm_qos_group_enable_attr.store = + sdhci_msm_pm_qos_group_enable_store; + sysfs_attr_init(&msm_host->pm_qos_group_enable_attr.attr); + msm_host->pm_qos_group_enable_attr.attr.name = + "pm_qos_cpu_groups_enable"; + msm_host->pm_qos_group_enable_attr.attr.mode = S_IRUGO; + ret = device_create_file(&msm_host->pdev->dev, + &msm_host->pm_qos_group_enable_attr); + if (ret) + dev_err(&msm_host->pdev->dev, "%s: fail to create pm_qos_group_enable_attr (%d)\n", + __func__, ret); +} + +static void sdhci_msm_pre_req(struct sdhci_host *host, + struct mmc_request *mmc_req) +{ + int cpu; + int group; + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); + struct sdhci_msm_host *msm_host = pltfm_host->priv; + int prev_group = sdhci_msm_get_cpu_group(msm_host, + msm_host->pm_qos_prev_cpu); + + sdhci_msm_pm_qos_irq_vote(host); + + cpu = get_cpu(); + put_cpu(); + group = sdhci_msm_get_cpu_group(msm_host, cpu); + if (group < 0) + return; + + if (group != prev_group && prev_group >= 0) { + sdhci_msm_pm_qos_cpu_unvote(host, + msm_host->pm_qos_prev_cpu, false); + prev_group = -1; /* make sure to vote for new group */ + } + + if (prev_group < 0) { + sdhci_msm_pm_qos_cpu_vote(host, + msm_host->pdata->pm_qos_data.latency, cpu); + msm_host->pm_qos_prev_cpu = cpu; + } +} + +static void sdhci_msm_post_req(struct sdhci_host *host, + struct mmc_request *mmc_req) +{ + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); + struct sdhci_msm_host *msm_host = pltfm_host->priv; + + sdhci_msm_pm_qos_irq_unvote(host, false); + + if (sdhci_msm_pm_qos_cpu_unvote(host, msm_host->pm_qos_prev_cpu, false)) + msm_host->pm_qos_prev_cpu = -1; +} + +static void sdhci_msm_init(struct sdhci_host *host) +{ + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); + struct sdhci_msm_host *msm_host = pltfm_host->priv; + + sdhci_msm_pm_qos_irq_init(host); + + if (msm_host->pdata->pm_qos_data.legacy_valid) + sdhci_msm_pm_qos_cpu_init(host, + msm_host->pdata->pm_qos_data.latency); +} + +static unsigned int sdhci_msm_get_current_limit(struct sdhci_host *host) +{ + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); + struct sdhci_msm_host *msm_host = pltfm_host->priv; + struct sdhci_msm_slot_reg_data *curr_slot = msm_host->pdata->vreg_data; + u32 max_curr = 0; + + if (curr_slot && curr_slot->vdd_data) + max_curr = curr_slot->vdd_data->hpm_uA; + + return max_curr; +} static struct sdhci_ops sdhci_msm_ops = { + .crypto_engine_cfg = sdhci_msm_ice_cfg, + .crypto_engine_cmdq_cfg = sdhci_msm_ice_cmdq_cfg, + .crypto_engine_cfg_end = sdhci_msm_ice_cfg_end, + .crypto_cfg_reset = sdhci_msm_ice_cfg_reset, + .crypto_engine_reset = sdhci_msm_ice_reset, + .set_uhs_signaling = sdhci_msm_set_uhs_signaling, + .check_power_status = sdhci_msm_check_power_status, .platform_execute_tuning = sdhci_msm_execute_tuning, - .reset = sdhci_reset, - .set_clock = sdhci_set_clock, + .enhanced_strobe = sdhci_msm_enhanced_strobe, + .toggle_cdr = sdhci_msm_toggle_cdr, + .get_max_segments = sdhci_msm_max_segs, + .set_clock = sdhci_msm_set_clock, + .get_min_clock = sdhci_msm_get_min_clock, + .get_max_clock = sdhci_msm_get_max_clock, + .dump_vendor_regs = sdhci_msm_dump_vendor_regs, + .config_auto_tuning_cmd = sdhci_msm_config_auto_tuning_cmd, + .enable_controller_clock = sdhci_msm_enable_controller_clock, .set_bus_width = sdhci_set_bus_width, - .set_uhs_signaling = sdhci_set_uhs_signaling, + .reset = sdhci_msm_reset, + .clear_set_dumpregs = sdhci_msm_clear_set_dumpregs, + .enhanced_strobe_mask = sdhci_msm_enhanced_strobe_mask, + .notify_load = sdhci_msm_notify_load, + .reset_workaround = sdhci_msm_reset_workaround, + .init = sdhci_msm_init, + .pre_req = sdhci_msm_pre_req, + .post_req = sdhci_msm_post_req, + .get_current_limit = sdhci_msm_get_current_limit, }; +static void sdhci_set_default_hw_caps(struct sdhci_msm_host *msm_host, + struct sdhci_host *host) +{ + u32 version, caps = 0; + u16 minor; + u8 major; + u32 val; + const struct sdhci_msm_offset *msm_host_offset = + msm_host->offset; + + version = sdhci_msm_readl_relaxed(host, + msm_host_offset->CORE_MCI_VERSION); + major = (version & CORE_VERSION_MAJOR_MASK) >> + CORE_VERSION_MAJOR_SHIFT; + minor = version & CORE_VERSION_TARGET_MASK; + + caps = readl_relaxed(host->ioaddr + SDHCI_CAPABILITIES); + + /* + * Starting with SDCC 5 controller (core major version = 1) + * controller won't advertise 3.0v, 1.8v and 8-bit features + * except for some targets. + */ + if (major >= 1 && minor != 0x11 && minor != 0x12) { + struct sdhci_msm_reg_data *vdd_io_reg; + /* + * Enable 1.8V support capability on controllers that + * support dual voltage + */ + vdd_io_reg = msm_host->pdata->vreg_data->vdd_io_data; + if (vdd_io_reg && (vdd_io_reg->high_vol_level > 2700000)) + caps |= CORE_3_0V_SUPPORT; + if (vdd_io_reg && (vdd_io_reg->low_vol_level < 1950000)) + caps |= CORE_1_8V_SUPPORT; + if (msm_host->pdata->mmc_bus_width == MMC_CAP_8_BIT_DATA) + caps |= CORE_8_BIT_SUPPORT; + } + + /* + * Enable one MID mode for SDCC5 (major 1) on 8916/8939 (minor 0x2e) and + * on 8992 (minor 0x3e) as a workaround to reset for data stuck issue. + */ + if (major == 1 && (minor == 0x2e || minor == 0x3e)) { + host->quirks2 |= SDHCI_QUIRK2_USE_RESET_WORKAROUND; + val = readl_relaxed(host->ioaddr + + msm_host_offset->CORE_VENDOR_SPEC_FUNC2); + writel_relaxed((val | CORE_ONE_MID_EN), + host->ioaddr + msm_host_offset->CORE_VENDOR_SPEC_FUNC2); + } + /* + * SDCC 5 controller with major version 1, minor version 0x34 and later + * with HS 400 mode support will use CM DLL instead of CDC LP 533 DLL. + */ + if ((major == 1) && (minor < 0x34)) + msm_host->use_cdclp533 = true; + + /* + * SDCC 5 controller with major version 1, minor version 0x42 and later + * will require additional steps when resetting DLL. + * It also supports HS400 enhanced strobe mode. + */ + if ((major == 1) && (minor >= 0x42)) { + msm_host->use_updated_dll_reset = true; + msm_host->enhanced_strobe = true; + } + + /* + * SDCC 5 controller with major version 1 and minor version 0x42, + * 0x46 and 0x49 currently uses 14lpp tech DLL whose internal + * gating cannot guarantee MCLK timing requirement i.e. + * when MCLK is gated OFF, it is not gated for less than 0.5us + * and MCLK must be switched on for at-least 1us before DATA + * starts coming. + */ + if ((major == 1) && ((minor == 0x42) || (minor == 0x46) || + (minor == 0x49) || (minor >= 0x6b))) + msm_host->use_14lpp_dll = true; + + /* Fake 3.0V support for SDIO devices which requires such voltage */ + if (msm_host->core_3_0v_support) { + caps |= CORE_3_0V_SUPPORT; + writel_relaxed((readl_relaxed(host->ioaddr + + SDHCI_CAPABILITIES) | caps), host->ioaddr + + msm_host_offset->CORE_VENDOR_SPEC_CAPABILITIES0); + } + + if ((major == 1) && (minor >= 0x49)) + msm_host->rclk_delay_fix = true; + /* + * Mask 64-bit support for controller with 32-bit address bus so that + * smaller descriptor size will be used and improve memory consumption. + */ + if (!msm_host->pdata->largeaddressbus) + caps &= ~CORE_SYS_BUS_SUPPORT_64_BIT; + + writel_relaxed(caps, host->ioaddr + + msm_host_offset->CORE_VENDOR_SPEC_CAPABILITIES0); + /* keep track of the value in SDHCI_CAPABILITIES */ + msm_host->caps_0 = caps; + + if ((major == 1) && (minor >= 0x6b)) { + msm_host->ice_hci_support = true; + host->cdr_support = true; + } +} + +#ifdef CONFIG_MMC_CQ_HCI +static void sdhci_msm_cmdq_init(struct sdhci_host *host, + struct platform_device *pdev) +{ + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); + struct sdhci_msm_host *msm_host = pltfm_host->priv; + + if (nocmdq) { + dev_dbg(&pdev->dev, "CMDQ disabled via cmdline\n"); + return; + } + + host->cq_host = cmdq_pltfm_init(pdev); + if (IS_ERR(host->cq_host)) { + dev_dbg(&pdev->dev, "cmdq-pltfm init: failed: %ld\n", + PTR_ERR(host->cq_host)); + host->cq_host = NULL; + } else { + msm_host->mmc->caps2 |= MMC_CAP2_CMD_QUEUE; + } +} +#else +static void sdhci_msm_cmdq_init(struct sdhci_host *host, + struct platform_device *pdev) +{ + +} +#endif + +static bool sdhci_msm_is_bootdevice(struct device *dev) +{ + if (strnstr(saved_command_line, "androidboot.bootdevice=", + strlen(saved_command_line))) { + char search_string[50]; + + snprintf(search_string, ARRAY_SIZE(search_string), + "androidboot.bootdevice=%s", dev_name(dev)); + if (strnstr(saved_command_line, search_string, + strlen(saved_command_line))) + return true; + else + return false; + } + + /* + * "androidboot.bootdevice=" argument is not present then + * return true as we don't know the boot device anyways. + */ + return true; +} + static int sdhci_msm_probe(struct platform_device *pdev) { + const struct sdhci_msm_offset *msm_host_offset; struct sdhci_host *host; struct sdhci_pltfm_host *pltfm_host; struct sdhci_msm_host *msm_host; - struct resource *core_memres; - int ret; - u16 host_version, core_minor; - u32 core_version, caps; - u8 core_major; + struct resource *core_memres = NULL; + int ret = 0, dead = 0; + u16 host_version; + u32 irq_status, irq_ctl; + struct resource *tlmm_memres = NULL; + void __iomem *tlmm_mem; + unsigned long flags; + bool force_probe; - msm_host = devm_kzalloc(&pdev->dev, sizeof(*msm_host), GFP_KERNEL); - if (!msm_host) - return -ENOMEM; + pr_debug("%s: Enter %s\n", dev_name(&pdev->dev), __func__); + msm_host = devm_kzalloc(&pdev->dev, sizeof(struct sdhci_msm_host), + GFP_KERNEL); + if (!msm_host) { + ret = -ENOMEM; + goto out; + } + if (of_find_compatible_node(NULL, NULL, "qcom,sdhci-msm-v5")) { + msm_host->mci_removed = true; + msm_host->offset = &sdhci_msm_offset_mci_removed; + } else { + msm_host->mci_removed = false; + msm_host->offset = &sdhci_msm_offset_mci_present; + } + msm_host_offset = msm_host->offset; msm_host->sdhci_msm_pdata.ops = &sdhci_msm_ops; host = sdhci_pltfm_init(pdev, &msm_host->sdhci_msm_pdata, 0); - if (IS_ERR(host)) - return PTR_ERR(host); + if (IS_ERR(host)) { + ret = PTR_ERR(host); + goto out_host_free; + } pltfm_host = sdhci_priv(host); pltfm_host->priv = msm_host; msm_host->mmc = host->mmc; msm_host->pdev = pdev; - ret = mmc_of_parse(host->mmc); - if (ret) + /* get the ice device vops if present */ + ret = sdhci_msm_ice_get_dev(host); + if (ret == -EPROBE_DEFER) { + /* + * SDHCI driver might be probed before ICE driver does. + * In that case we would like to return EPROBE_DEFER code + * in order to delay its probing. + */ + dev_err(&pdev->dev, "%s: required ICE device not probed yet err = %d\n", + __func__, ret); goto pltfm_free; - sdhci_get_of_property(pdev); + } else if (ret == -ENODEV) { + /* + * ICE device is not enabled in DTS file. No need for further + * initialization of ICE driver. + */ + dev_warn(&pdev->dev, "%s: ICE device is not enabled", + __func__); + } else if (ret) { + dev_err(&pdev->dev, "%s: sdhci_msm_ice_get_dev failed %d\n", + __func__, ret); + goto pltfm_free; + } + + /* Extract platform data */ + if (pdev->dev.of_node) { + ret = of_alias_get_id(pdev->dev.of_node, "sdhc"); + if (ret <= 0) { + dev_err(&pdev->dev, "Failed to get slot index %d\n", + ret); + goto pltfm_free; + } + + /* Read property to determine if the probe is forced */ + force_probe = of_find_property(pdev->dev.of_node, + "qcom,force-sdhc1-probe", NULL); + + /* skip the probe if eMMC isn't a boot device */ + if ((ret == 1) && !sdhci_msm_is_bootdevice(&pdev->dev) + && !force_probe) { + ret = -ENODEV; + goto pltfm_free; + } + + if (disable_slots & (1 << (ret - 1))) { + dev_info(&pdev->dev, "%s: Slot %d disabled\n", __func__, + ret); + ret = -ENODEV; + goto pltfm_free; + } + + if (ret <= 2) + sdhci_slot[ret-1] = msm_host; + + msm_host->pdata = sdhci_msm_populate_pdata(&pdev->dev, + msm_host); + if (!msm_host->pdata) { + dev_err(&pdev->dev, "DT parsing error\n"); + goto pltfm_free; + } + } else { + dev_err(&pdev->dev, "No device tree node\n"); + goto pltfm_free; + } + + /* Setup Clocks */ /* Setup SDCC bus voter clock. */ - msm_host->bus_clk = devm_clk_get(&pdev->dev, "bus"); - if (!IS_ERR(msm_host->bus_clk)) { + msm_host->bus_clk = devm_clk_get(&pdev->dev, "bus_clk"); + if (!IS_ERR_OR_NULL(msm_host->bus_clk)) { /* Vote for max. clk rate for max. performance */ ret = clk_set_rate(msm_host->bus_clk, INT_MAX); if (ret) @@ -470,99 +4360,429 @@ } /* Setup main peripheral bus clock */ - msm_host->pclk = devm_clk_get(&pdev->dev, "iface"); - if (IS_ERR(msm_host->pclk)) { - ret = PTR_ERR(msm_host->pclk); - dev_err(&pdev->dev, "Perpheral clk setup failed (%d)\n", ret); + msm_host->pclk = devm_clk_get(&pdev->dev, "iface_clk"); + if (!IS_ERR(msm_host->pclk)) { + ret = clk_prepare_enable(msm_host->pclk); + if (ret) goto bus_clk_disable; } + atomic_set(&msm_host->controller_clock, 1); - ret = clk_prepare_enable(msm_host->pclk); + if (msm_host->ice.pdev) { + /* Setup SDC ICE clock */ + msm_host->ice_clk = devm_clk_get(&pdev->dev, "ice_core_clk"); + if (!IS_ERR(msm_host->ice_clk)) { + /* ICE core has only one clock frequency for now */ + ret = clk_set_rate(msm_host->ice_clk, + msm_host->pdata->ice_clk_max); + if (ret) { + dev_err(&pdev->dev, "ICE_CLK rate set failed (%d) for %u\n", + ret, + msm_host->pdata->ice_clk_max); + goto pclk_disable; + } + ret = clk_prepare_enable(msm_host->ice_clk); if (ret) - goto bus_clk_disable; + goto pclk_disable; + + msm_host->ice_clk_rate = + msm_host->pdata->ice_clk_max; + } + } /* Setup SDC MMC clock */ - msm_host->clk = devm_clk_get(&pdev->dev, "core"); + msm_host->clk = devm_clk_get(&pdev->dev, "core_clk"); if (IS_ERR(msm_host->clk)) { ret = PTR_ERR(msm_host->clk); - dev_err(&pdev->dev, "SDC MMC clk setup failed (%d)\n", ret); goto pclk_disable; } - /* Vote for maximum clock rate for maximum performance */ - ret = clk_set_rate(msm_host->clk, INT_MAX); - if (ret) - dev_warn(&pdev->dev, "core clock boost failed\n"); - + /* Set to the minimum supported clock frequency */ + ret = clk_set_rate(msm_host->clk, sdhci_msm_get_min_clock(host)); + if (ret) { + dev_err(&pdev->dev, "MClk rate set failed (%d)\n", ret); + goto pclk_disable; + } ret = clk_prepare_enable(msm_host->clk); if (ret) goto pclk_disable; - core_memres = platform_get_resource(pdev, IORESOURCE_MEM, 1); - msm_host->core_mem = devm_ioremap_resource(&pdev->dev, core_memres); + msm_host->clk_rate = sdhci_msm_get_min_clock(host); + atomic_set(&msm_host->clks_on, 1); - if (IS_ERR(msm_host->core_mem)) { - dev_err(&pdev->dev, "Failed to remap registers\n"); - ret = PTR_ERR(msm_host->core_mem); + /* Setup CDC calibration fixed feedback clock */ + msm_host->ff_clk = devm_clk_get(&pdev->dev, "cal_clk"); + if (!IS_ERR(msm_host->ff_clk)) { + ret = clk_prepare_enable(msm_host->ff_clk); + if (ret) goto clk_disable; } + /* Setup CDC calibration sleep clock */ + msm_host->sleep_clk = devm_clk_get(&pdev->dev, "sleep_clk"); + if (!IS_ERR(msm_host->sleep_clk)) { + ret = clk_prepare_enable(msm_host->sleep_clk); + if (ret) + goto ff_clk_disable; + } + + msm_host->saved_tuning_phase = INVALID_TUNING_PHASE; + + ret = sdhci_msm_bus_register(msm_host, pdev); + if (ret) + goto sleep_clk_disable; + + if (msm_host->msm_bus_vote.client_handle) + INIT_DELAYED_WORK(&msm_host->msm_bus_vote.vote_work, + sdhci_msm_bus_work); + sdhci_msm_bus_voting(host, 1); + + /* Setup regulators */ + ret = sdhci_msm_vreg_init(&pdev->dev, msm_host->pdata, true); + if (ret) { + dev_err(&pdev->dev, "Regulator setup failed (%d)\n", ret); + goto bus_unregister; + } + /* Reset the core and Enable SDHC mode */ - writel_relaxed(readl_relaxed(msm_host->core_mem + CORE_POWER) | - CORE_SW_RST, msm_host->core_mem + CORE_POWER); + core_memres = platform_get_resource_byname(pdev, + IORESOURCE_MEM, "core_mem"); + if (!msm_host->mci_removed) { + if (!core_memres) { + dev_err(&pdev->dev, "Failed to get iomem resource\n"); + goto vreg_deinit; + } + msm_host->core_mem = devm_ioremap(&pdev->dev, + core_memres->start, resource_size(core_memres)); - /* SW reset can take upto 10HCLK + 15MCLK cycles. (min 40us) */ - usleep_range(1000, 5000); - if (readl(msm_host->core_mem + CORE_POWER) & CORE_SW_RST) { - dev_err(&pdev->dev, "Stuck in reset\n"); - ret = -ETIMEDOUT; - goto clk_disable; + if (!msm_host->core_mem) { + dev_err(&pdev->dev, "Failed to remap registers\n"); + ret = -ENOMEM; + goto vreg_deinit; + } + } + + tlmm_memres = platform_get_resource_byname(pdev, + IORESOURCE_MEM, "tlmm_mem"); + if (tlmm_memres) { + tlmm_mem = devm_ioremap(&pdev->dev, tlmm_memres->start, + resource_size(tlmm_memres)); + + if (!tlmm_mem) { + dev_err(&pdev->dev, "Failed to remap tlmm registers\n"); + ret = -ENOMEM; + goto vreg_deinit; } + writel_relaxed(readl_relaxed(tlmm_mem) | 0x2, tlmm_mem); + } + + /* + * Reset the vendor spec register to power on reset state. + */ + writel_relaxed(CORE_VENDOR_SPEC_POR_VAL, + host->ioaddr + msm_host_offset->CORE_VENDOR_SPEC); + + /* + * Ensure SDHCI FIFO is enabled by disabling alternative FIFO + */ + writel_relaxed((readl_relaxed(host->ioaddr + + msm_host_offset->CORE_VENDOR_SPEC3) & + ~CORE_FIFO_ALT_EN), host->ioaddr + + msm_host_offset->CORE_VENDOR_SPEC3); + if (!msm_host->mci_removed) { /* Set HC_MODE_EN bit in HC_MODE register */ writel_relaxed(HC_MODE_EN, (msm_host->core_mem + CORE_HC_MODE)); + /* Set FF_CLK_SW_RST_DIS bit in HC_MODE register */ + writel_relaxed(readl_relaxed(msm_host->core_mem + + CORE_HC_MODE) | FF_CLK_SW_RST_DIS, + msm_host->core_mem + CORE_HC_MODE); + } + sdhci_set_default_hw_caps(msm_host, host); + + /* + * Set the PAD_PWR_SWTICH_EN bit so that the PAD_PWR_SWITCH bit can + * be used as required later on. + */ + writel_relaxed((readl_relaxed(host->ioaddr + + msm_host_offset->CORE_VENDOR_SPEC) | + CORE_IO_PAD_PWR_SWITCH_EN), host->ioaddr + + msm_host_offset->CORE_VENDOR_SPEC); + /* + * CORE_SW_RST above may trigger power irq if previous status of PWRCTL + * was either BUS_ON or IO_HIGH_V. So before we enable the power irq + * interrupt in GIC (by registering the interrupt handler), we need to + * ensure that any pending power irq interrupt status is acknowledged + * otherwise power irq interrupt handler would be fired prematurely. + */ + irq_status = sdhci_msm_readl_relaxed(host, + msm_host_offset->CORE_PWRCTL_STATUS); + sdhci_msm_writel_relaxed(irq_status, host, + msm_host_offset->CORE_PWRCTL_CLEAR); + irq_ctl = sdhci_msm_readl_relaxed(host, + msm_host_offset->CORE_PWRCTL_CTL); + + if (irq_status & (CORE_PWRCTL_BUS_ON | CORE_PWRCTL_BUS_OFF)) + irq_ctl |= CORE_PWRCTL_BUS_SUCCESS; + if (irq_status & (CORE_PWRCTL_IO_HIGH | CORE_PWRCTL_IO_LOW)) + irq_ctl |= CORE_PWRCTL_IO_SUCCESS; + sdhci_msm_writel_relaxed(irq_ctl, host, + msm_host_offset->CORE_PWRCTL_CTL); + + /* + * Ensure that above writes are propogated before interrupt enablement + * in GIC. + */ + mb(); + + /* + * Following are the deviations from SDHC spec v3.0 - + * 1. Card detection is handled using separate GPIO. + * 2. Bus power control is handled by interacting with PMIC. + */ host->quirks |= SDHCI_QUIRK_BROKEN_CARD_DETECTION; host->quirks |= SDHCI_QUIRK_SINGLE_POWER_WRITE; + host->quirks |= SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN; + host->quirks |= SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC; + host->quirks2 |= SDHCI_QUIRK2_ALWAYS_USE_BASE_CLOCK; + host->quirks2 |= SDHCI_QUIRK2_IGNORE_DATATOUT_FOR_R1BCMD; + host->quirks2 |= SDHCI_QUIRK2_BROKEN_PRESET_VALUE; + host->quirks2 |= SDHCI_QUIRK2_USE_RESERVED_MAX_TIMEOUT; + host->quirks2 |= SDHCI_QUIRK2_NON_STANDARD_TUNING; + host->quirks2 |= SDHCI_QUIRK2_USE_PIO_FOR_EMMC_TUNING; + + if (host->quirks2 & SDHCI_QUIRK2_ALWAYS_USE_BASE_CLOCK) + host->quirks2 |= SDHCI_QUIRK2_DIVIDE_TOUT_BY_4; host_version = readw_relaxed((host->ioaddr + SDHCI_HOST_VERSION)); dev_dbg(&pdev->dev, "Host Version: 0x%x Vendor Version 0x%x\n", host_version, ((host_version & SDHCI_VENDOR_VER_MASK) >> SDHCI_VENDOR_VER_SHIFT)); + if (((host_version & SDHCI_VENDOR_VER_MASK) >> + SDHCI_VENDOR_VER_SHIFT) == SDHCI_VER_100) { + /* + * Add 40us delay in interrupt handler when + * operating at initialization frequency(400KHz). + */ + host->quirks2 |= SDHCI_QUIRK2_SLOW_INT_CLR; + /* + * Set Software Reset for DAT line in Software + * Reset Register (Bit 2). + */ + host->quirks2 |= SDHCI_QUIRK2_RDWR_TX_ACTIVE_EOT; + } - core_version = readl_relaxed(msm_host->core_mem + CORE_MCI_VERSION); - core_major = (core_version & CORE_VERSION_MAJOR_MASK) >> - CORE_VERSION_MAJOR_SHIFT; - core_minor = core_version & CORE_VERSION_MINOR_MASK; - dev_dbg(&pdev->dev, "MCI Version: 0x%08x, major: 0x%04x, minor: 0x%02x\n", - core_version, core_major, core_minor); + host->quirks2 |= SDHCI_QUIRK2_IGN_DATA_END_BIT_ERROR; + + /* Setup PWRCTL irq */ + msm_host->pwr_irq = platform_get_irq_byname(pdev, "pwr_irq"); + if (msm_host->pwr_irq < 0) { + dev_err(&pdev->dev, "Failed to get pwr_irq by name (%d)\n", + msm_host->pwr_irq); + goto vreg_deinit; + } + ret = devm_request_threaded_irq(&pdev->dev, msm_host->pwr_irq, NULL, + sdhci_msm_pwr_irq, IRQF_ONESHOT, + dev_name(&pdev->dev), host); + if (ret) { + dev_err(&pdev->dev, "Request threaded irq(%d) failed (%d)\n", + msm_host->pwr_irq, ret); + goto vreg_deinit; + } + + /* Enable pwr irq interrupts */ + sdhci_msm_writel_relaxed(INT_MASK, host, + msm_host_offset->CORE_PWRCTL_MASK); + +#ifdef CONFIG_MMC_CLKGATE + /* Set clock gating delay to be used when CONFIG_MMC_CLKGATE is set */ + msm_host->mmc->clkgate_delay = SDHCI_MSM_MMC_CLK_GATE_DELAY; +#endif + + /* Set host capabilities */ + msm_host->mmc->caps |= msm_host->pdata->mmc_bus_width; + msm_host->mmc->caps |= msm_host->pdata->caps; + msm_host->mmc->caps |= MMC_CAP_AGGRESSIVE_PM; + msm_host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY; + msm_host->mmc->caps2 |= msm_host->pdata->caps2; + msm_host->mmc->caps2 |= MMC_CAP2_BOOTPART_NOACC; + msm_host->mmc->caps2 |= MMC_CAP2_HS400_POST_TUNING; + msm_host->mmc->caps2 |= MMC_CAP2_CLK_SCALE; + msm_host->mmc->caps2 |= MMC_CAP2_SANITIZE; + msm_host->mmc->caps2 |= MMC_CAP2_MAX_DISCARD_SIZE; + msm_host->mmc->caps2 |= MMC_CAP2_SLEEP_AWAKE; + msm_host->mmc->pm_caps |= MMC_PM_KEEP_POWER | MMC_PM_WAKE_SDIO_IRQ; + + if (msm_host->pdata->nonremovable) + msm_host->mmc->caps |= MMC_CAP_NONREMOVABLE; + + if (msm_host->pdata->nonhotplug) + msm_host->mmc->caps2 |= MMC_CAP2_NONHOTPLUG; + + msm_host->mmc->sdr104_wa = msm_host->pdata->sdr104_wa; + + /* Initialize ICE if present */ + if (msm_host->ice.pdev) { + ret = sdhci_msm_ice_init(host); + if (ret) { + dev_err(&pdev->dev, "%s: SDHCi ICE init failed (%d)\n", + mmc_hostname(host->mmc), ret); + ret = -EINVAL; + goto vreg_deinit; + } + host->is_crypto_en = true; + /* Packed commands cannot be encrypted/decrypted using ICE */ + msm_host->mmc->caps2 &= ~(MMC_CAP2_PACKED_WR | + MMC_CAP2_PACKED_WR_CONTROL); + } + init_completion(&msm_host->pwr_irq_completion); + + if (gpio_is_valid(msm_host->pdata->status_gpio)) { /* - * Support for some capabilities is not advertised by newer - * controller versions and must be explicitly enabled. + * Set up the card detect GPIO in active configuration before + * configuring it as an IRQ. Otherwise, it can be in some + * weird/inconsistent state resulting in flood of interrupts. */ - if (core_major >= 1 && core_minor != 0x11 && core_minor != 0x12) { - caps = readl_relaxed(host->ioaddr + SDHCI_CAPABILITIES); - caps |= SDHCI_CAN_VDD_300 | SDHCI_CAN_DO_8BIT; - writel_relaxed(caps, host->ioaddr + - CORE_VENDOR_SPEC_CAPABILITIES0); + sdhci_msm_setup_pins(msm_host->pdata, true); + + /* + * This delay is needed for stabilizing the card detect GPIO + * line after changing the pull configs. + */ + usleep_range(10000, 10500); + ret = mmc_gpio_request_cd(msm_host->mmc, + msm_host->pdata->status_gpio, 0); + if (ret) { + dev_err(&pdev->dev, "%s: Failed to request card detection IRQ %d\n", + __func__, ret); + goto vreg_deinit; + } + } + + if ((sdhci_readl(host, SDHCI_CAPABILITIES) & SDHCI_CAN_64BIT) && + (dma_supported(mmc_dev(host->mmc), DMA_BIT_MASK(64)))) { + host->dma_mask = DMA_BIT_MASK(64); + mmc_dev(host->mmc)->dma_mask = &host->dma_mask; + mmc_dev(host->mmc)->coherent_dma_mask = host->dma_mask; + } else if (dma_supported(mmc_dev(host->mmc), DMA_BIT_MASK(32))) { + host->dma_mask = DMA_BIT_MASK(32); + mmc_dev(host->mmc)->dma_mask = &host->dma_mask; + mmc_dev(host->mmc)->coherent_dma_mask = host->dma_mask; + } else { + dev_err(&pdev->dev, "%s: Failed to set dma mask\n", __func__); } + msm_host->pdata->sdiowakeup_irq = platform_get_irq_byname(pdev, + "sdiowakeup_irq"); + if (sdhci_is_valid_gpio_wakeup_int(msm_host)) { + dev_info(&pdev->dev, "%s: sdiowakeup_irq = %d\n", __func__, + msm_host->pdata->sdiowakeup_irq); + msm_host->is_sdiowakeup_enabled = true; + ret = request_irq(msm_host->pdata->sdiowakeup_irq, + sdhci_msm_sdiowakeup_irq, + IRQF_SHARED | IRQF_TRIGGER_HIGH, + "sdhci-msm sdiowakeup", host); + if (ret) { + dev_err(&pdev->dev, "%s: request sdiowakeup IRQ %d: failed: %d\n", + __func__, msm_host->pdata->sdiowakeup_irq, ret); + msm_host->pdata->sdiowakeup_irq = -1; + msm_host->is_sdiowakeup_enabled = false; + goto vreg_deinit; + } else { + spin_lock_irqsave(&host->lock, flags); + sdhci_msm_cfg_sdiowakeup_gpio_irq(host, false); + msm_host->sdio_pending_processing = false; + spin_unlock_irqrestore(&host->lock, flags); + } + } + + sdhci_msm_cmdq_init(host, pdev); ret = sdhci_add_host(host); + if (ret) { + dev_err(&pdev->dev, "Add host failed (%d)\n", ret); + goto vreg_deinit; + } + + msm_host->pltfm_init_done = true; + + pm_runtime_set_active(&pdev->dev); + pm_runtime_enable(&pdev->dev); + pm_runtime_set_autosuspend_delay(&pdev->dev, MSM_AUTOSUSPEND_DELAY_MS); + pm_runtime_use_autosuspend(&pdev->dev); + + msm_host->msm_bus_vote.max_bus_bw.show = show_sdhci_max_bus_bw; + msm_host->msm_bus_vote.max_bus_bw.store = store_sdhci_max_bus_bw; + sysfs_attr_init(&msm_host->msm_bus_vote.max_bus_bw.attr); + msm_host->msm_bus_vote.max_bus_bw.attr.name = "max_bus_bw"; + msm_host->msm_bus_vote.max_bus_bw.attr.mode = S_IRUGO | S_IWUSR; + ret = device_create_file(&pdev->dev, + &msm_host->msm_bus_vote.max_bus_bw); if (ret) - goto clk_disable; + goto remove_host; - return 0; + if (!gpio_is_valid(msm_host->pdata->status_gpio)) { + msm_host->polling.show = show_polling; + msm_host->polling.store = store_polling; + sysfs_attr_init(&msm_host->polling.attr); + msm_host->polling.attr.name = "polling"; + msm_host->polling.attr.mode = S_IRUGO | S_IWUSR; + ret = device_create_file(&pdev->dev, &msm_host->polling); + if (ret) + goto remove_max_bus_bw_file; + } + + msm_host->auto_cmd21_attr.show = show_auto_cmd21; + msm_host->auto_cmd21_attr.store = store_auto_cmd21; + sysfs_attr_init(&msm_host->auto_cmd21_attr.attr); + msm_host->auto_cmd21_attr.attr.name = "enable_auto_cmd21"; + msm_host->auto_cmd21_attr.attr.mode = S_IRUGO | S_IWUSR; + ret = device_create_file(&pdev->dev, &msm_host->auto_cmd21_attr); + if (ret) { + pr_err("%s: %s: failed creating auto-cmd21 attr: %d\n", + mmc_hostname(host->mmc), __func__, ret); + device_remove_file(&pdev->dev, &msm_host->auto_cmd21_attr); + } + if (sdhci_msm_is_bootdevice(&pdev->dev)) + mmc_flush_detect_work(host->mmc); + + /* Successful initialization */ + goto out; +remove_max_bus_bw_file: + device_remove_file(&pdev->dev, &msm_host->msm_bus_vote.max_bus_bw); +remove_host: + dead = (readl_relaxed(host->ioaddr + SDHCI_INT_STATUS) == 0xffffffff); + pm_runtime_disable(&pdev->dev); + sdhci_remove_host(host, dead); +vreg_deinit: + sdhci_msm_vreg_init(&pdev->dev, msm_host->pdata, false); +bus_unregister: + if (msm_host->msm_bus_vote.client_handle) + sdhci_msm_bus_cancel_work_and_set_vote(host, 0); + sdhci_msm_bus_unregister(msm_host); +sleep_clk_disable: + if (!IS_ERR(msm_host->sleep_clk)) + clk_disable_unprepare(msm_host->sleep_clk); +ff_clk_disable: + if (!IS_ERR(msm_host->ff_clk)) + clk_disable_unprepare(msm_host->ff_clk); clk_disable: + if (!IS_ERR(msm_host->clk)) clk_disable_unprepare(msm_host->clk); pclk_disable: + if (!IS_ERR(msm_host->pclk)) clk_disable_unprepare(msm_host->pclk); bus_clk_disable: - if (!IS_ERR(msm_host->bus_clk)) + if (!IS_ERR_OR_NULL(msm_host->bus_clk)) clk_disable_unprepare(msm_host->bus_clk); pltfm_free: sdhci_pltfm_free(pdev); +out_host_free: + devm_kfree(&pdev->dev, msm_host); +out: + pr_debug("%s: Exit %s\n", dev_name(&pdev->dev), __func__); return ret; } @@ -571,28 +4791,270 @@ struct sdhci_host *host = platform_get_drvdata(pdev); struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); struct sdhci_msm_host *msm_host = pltfm_host->priv; + struct sdhci_msm_pltfm_data *pdata = msm_host->pdata; int dead = (readl_relaxed(host->ioaddr + SDHCI_INT_STATUS) == 0xffffffff); + pr_debug("%s: %s\n", dev_name(&pdev->dev), __func__); + if (!gpio_is_valid(msm_host->pdata->status_gpio)) + device_remove_file(&pdev->dev, &msm_host->polling); + device_remove_file(&pdev->dev, &msm_host->msm_bus_vote.max_bus_bw); + pm_runtime_disable(&pdev->dev); sdhci_remove_host(host, dead); sdhci_pltfm_free(pdev); - clk_disable_unprepare(msm_host->clk); - clk_disable_unprepare(msm_host->pclk); - if (!IS_ERR(msm_host->bus_clk)) - clk_disable_unprepare(msm_host->bus_clk); + + sdhci_msm_vreg_init(&pdev->dev, msm_host->pdata, false); + + sdhci_msm_setup_pins(pdata, true); + sdhci_msm_setup_pins(pdata, false); + + if (msm_host->msm_bus_vote.client_handle) { + sdhci_msm_bus_cancel_work_and_set_vote(host, 0); + sdhci_msm_bus_unregister(msm_host); + } return 0; } +#ifdef CONFIG_PM +static int sdhci_msm_cfg_sdio_wakeup(struct sdhci_host *host, bool enable) +{ + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); + struct sdhci_msm_host *msm_host = pltfm_host->priv; + unsigned long flags; + int ret = 0; + + if (!(host->mmc->card && mmc_card_sdio(host->mmc->card) && + sdhci_is_valid_gpio_wakeup_int(msm_host) && + mmc_card_wake_sdio_irq(host->mmc))) { + msm_host->sdio_pending_processing = false; + return 1; + } + + spin_lock_irqsave(&host->lock, flags); + if (enable) { + /* configure DAT1 gpio if applicable */ + if (sdhci_is_valid_gpio_wakeup_int(msm_host)) { + msm_host->sdio_pending_processing = false; + ret = enable_irq_wake(msm_host->pdata->sdiowakeup_irq); + if (!ret) + sdhci_msm_cfg_sdiowakeup_gpio_irq(host, true); + goto out; + } else { + pr_err("%s: sdiowakeup_irq(%d) invalid\n", + mmc_hostname(host->mmc), enable); + } + } else { + if (sdhci_is_valid_gpio_wakeup_int(msm_host)) { + ret = disable_irq_wake(msm_host->pdata->sdiowakeup_irq); + sdhci_msm_cfg_sdiowakeup_gpio_irq(host, false); + msm_host->sdio_pending_processing = false; + } else { + pr_err("%s: sdiowakeup_irq(%d)invalid\n", + mmc_hostname(host->mmc), enable); + + } + } +out: + if (ret) + pr_err("%s: %s: %sable wakeup: failed: %d gpio: %d\n", + mmc_hostname(host->mmc), __func__, enable ? "en" : "dis", + ret, msm_host->pdata->sdiowakeup_irq); + spin_unlock_irqrestore(&host->lock, flags); + return ret; +} + + +static int sdhci_msm_runtime_suspend(struct device *dev) +{ + struct sdhci_host *host = dev_get_drvdata(dev); + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); + struct sdhci_msm_host *msm_host = pltfm_host->priv; + ktime_t start = ktime_get(); + int ret; + + if (host->mmc->card && mmc_card_sdio(host->mmc->card)) + goto defer_disable_host_irq; + + sdhci_cfg_irq(host, false, true); + +defer_disable_host_irq: + disable_irq(msm_host->pwr_irq); + + /* + * Remove the vote immediately only if clocks are off in which + * case we might have queued work to remove vote but it may not + * be completed before runtime suspend or system suspend. + */ + if (!atomic_read(&msm_host->clks_on)) { + if (msm_host->msm_bus_vote.client_handle) + sdhci_msm_bus_cancel_work_and_set_vote(host, 0); + } + + if (host->is_crypto_en) { + ret = sdhci_msm_ice_suspend(host); + if (ret < 0) + pr_err("%s: failed to suspend crypto engine %d\n", + mmc_hostname(host->mmc), ret); + } + trace_sdhci_msm_runtime_suspend(mmc_hostname(host->mmc), 0, + ktime_to_us(ktime_sub(ktime_get(), start))); + return 0; +} + +static int sdhci_msm_runtime_resume(struct device *dev) +{ + struct sdhci_host *host = dev_get_drvdata(dev); + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); + struct sdhci_msm_host *msm_host = pltfm_host->priv; + ktime_t start = ktime_get(); + int ret; + + if (host->is_crypto_en) { + ret = sdhci_msm_enable_controller_clock(host); + if (ret) { + pr_err("%s: Failed to enable reqd clocks\n", + mmc_hostname(host->mmc)); + goto skip_ice_resume; + } + ret = sdhci_msm_ice_resume(host); + if (ret) + pr_err("%s: failed to resume crypto engine %d\n", + mmc_hostname(host->mmc), ret); + } +skip_ice_resume: + if (host->mmc->card && mmc_card_sdio(host->mmc->card)) + goto defer_enable_host_irq; + + sdhci_cfg_irq(host, true, true); + +defer_enable_host_irq: + enable_irq(msm_host->pwr_irq); + + trace_sdhci_msm_runtime_resume(mmc_hostname(host->mmc), 0, + ktime_to_us(ktime_sub(ktime_get(), start))); + return 0; +} + +static int sdhci_msm_suspend(struct device *dev) +{ + struct sdhci_host *host = dev_get_drvdata(dev); + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); + struct sdhci_msm_host *msm_host = pltfm_host->priv; + int ret = 0; + int sdio_cfg = 0; + ktime_t start = ktime_get(); + + if (gpio_is_valid(msm_host->pdata->status_gpio) && + (msm_host->mmc->slot.cd_irq >= 0)) + disable_irq(msm_host->mmc->slot.cd_irq); + + if (pm_runtime_suspended(dev)) { + pr_debug("%s: %s: already runtime suspended\n", + mmc_hostname(host->mmc), __func__); + goto out; + } + ret = sdhci_msm_runtime_suspend(dev); +out: + sdhci_msm_disable_controller_clock(host); + if (host->mmc->card && mmc_card_sdio(host->mmc->card)) { + sdio_cfg = sdhci_msm_cfg_sdio_wakeup(host, true); + if (sdio_cfg) + sdhci_cfg_irq(host, false, true); + } + + trace_sdhci_msm_suspend(mmc_hostname(host->mmc), ret, + ktime_to_us(ktime_sub(ktime_get(), start))); + return ret; +} + +static int sdhci_msm_resume(struct device *dev) +{ + struct sdhci_host *host = dev_get_drvdata(dev); + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); + struct sdhci_msm_host *msm_host = pltfm_host->priv; + int ret = 0; + int sdio_cfg = 0; + ktime_t start = ktime_get(); + + if (gpio_is_valid(msm_host->pdata->status_gpio) && + (msm_host->mmc->slot.cd_irq >= 0)) + enable_irq(msm_host->mmc->slot.cd_irq); + + if (pm_runtime_suspended(dev)) { + pr_debug("%s: %s: runtime suspended, defer system resume\n", + mmc_hostname(host->mmc), __func__); + goto out; + } + + ret = sdhci_msm_runtime_resume(dev); +out: + if (host->mmc->card && mmc_card_sdio(host->mmc->card)) { + sdio_cfg = sdhci_msm_cfg_sdio_wakeup(host, false); + if (sdio_cfg) + sdhci_cfg_irq(host, true, true); + } + + trace_sdhci_msm_resume(mmc_hostname(host->mmc), ret, + ktime_to_us(ktime_sub(ktime_get(), start))); + return ret; +} + +static int sdhci_msm_suspend_noirq(struct device *dev) +{ + struct sdhci_host *host = dev_get_drvdata(dev); + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); + struct sdhci_msm_host *msm_host = pltfm_host->priv; + int ret = 0; + + /* + * ksdioirqd may be running, hence retry + * suspend in case the clocks are ON + */ + if (atomic_read(&msm_host->clks_on)) { + pr_warn("%s: %s: clock ON after suspend, aborting suspend\n", + mmc_hostname(host->mmc), __func__); + ret = -EAGAIN; + } + + if (host->mmc->card && mmc_card_sdio(host->mmc->card)) + if (msm_host->sdio_pending_processing) + ret = -EBUSY; + + return ret; +} + +static const struct dev_pm_ops sdhci_msm_pmops = { + SET_LATE_SYSTEM_SLEEP_PM_OPS(sdhci_msm_suspend, sdhci_msm_resume) + SET_RUNTIME_PM_OPS(sdhci_msm_runtime_suspend, sdhci_msm_runtime_resume, + NULL) + .suspend_noirq = sdhci_msm_suspend_noirq, +}; + +#define SDHCI_MSM_PMOPS (&sdhci_msm_pmops) + +#else +#define SDHCI_MSM_PMOPS NULL +#endif +static const struct of_device_id sdhci_msm_dt_match[] = { + {.compatible = "qcom,sdhci-msm"}, + {.compatible = "qcom,sdhci-msm-v5"}, + {}, +}; +MODULE_DEVICE_TABLE(of, sdhci_msm_dt_match); + static struct platform_driver sdhci_msm_driver = { .probe = sdhci_msm_probe, .remove = sdhci_msm_remove, .driver = { .name = "sdhci_msm", + .owner = THIS_MODULE, + .probe_type = PROBE_PREFER_ASYNCHRONOUS, .of_match_table = sdhci_msm_dt_match, + .pm = SDHCI_MSM_PMOPS, }, }; module_platform_driver(sdhci_msm_driver); -MODULE_DESCRIPTION("Qualcomm Secure Digital Host Controller Interface driver"); +MODULE_DESCRIPTION("Qualcomm Technologies, Inc. Secure Digital Host Controller Interface driver"); MODULE_LICENSE("GPL v2"); diff -ruw linux-4.4.115/drivers/mmc/Kconfig linux-4.4.115-fbx/drivers/mmc/Kconfig --- linux-4.4.115/drivers/mmc/Kconfig 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/mmc/Kconfig 2019-01-22 16:16:24.763257817 +0100 @@ -19,6 +19,14 @@ This is an option for use by developers; most people should say N here. This enables MMC core and driver debugging. +config MMC_PERF_PROFILING + bool "MMC performance profiling" + depends on MMC != n + default n + help + If you say Y here, support will be added for collecting + performance numbers at the MMC Queue and Host layers. + if MMC source "drivers/mmc/core/Kconfig" diff -ruw linux-4.4.115/drivers/mtd/nand/Kconfig linux-4.4.115-fbx/drivers/mtd/nand/Kconfig --- linux-4.4.115/drivers/mtd/nand/Kconfig 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/mtd/nand/Kconfig 2019-01-22 16:16:24.819258324 +0100 @@ -1,3 +1,10 @@ +config MTD_NAND_IDS + tristate "Include chip ids for known NAND devices." + depends on MTD + help + Useful for NAND drivers that do not use the NAND subsystem but + still like to take advantage of the known chip information. + config MTD_NAND_ECC tristate @@ -108,9 +115,6 @@ config MTD_NAND_OMAP_BCH_BUILD def_tristate MTD_NAND_OMAP2 && MTD_NAND_OMAP_BCH -config MTD_NAND_IDS - tristate - config MTD_NAND_RICOH tristate "Ricoh xD card reader" default n diff -ruw linux-4.4.115/drivers/net/can/spi/Kconfig linux-4.4.115-fbx/drivers/net/can/spi/Kconfig --- linux-4.4.115/drivers/net/can/spi/Kconfig 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/net/can/spi/Kconfig 2019-10-29 09:26:24.121207856 +0100 @@ -7,4 +7,15 @@ ---help--- Driver for the Microchip MCP251x SPI CAN controllers. +config CAN_RH850 + tristate "Renesas RH850 SPI CAN controller" + depends on HAS_DMA + ---help--- + Driver for the Renesas RH850 SPI CAN controller. + +config CAN_K61 + tristate "Freescale K61 SPI CAN controllers" + depends on SPI + ---help--- + Driver for the Freescale K61 SPI CAN controllers. endmenu diff -ruw linux-4.4.115/drivers/net/can/spi/Makefile linux-4.4.115-fbx/drivers/net/can/spi/Makefile --- linux-4.4.115/drivers/net/can/spi/Makefile 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/net/can/spi/Makefile 2019-10-29 09:26:24.121207856 +0100 @@ -4,3 +4,5 @@ obj-$(CONFIG_CAN_MCP251X) += mcp251x.o +obj-$(CONFIG_CAN_RH850) += rh850.o +obj-${CONFIG_CAN_K61} += k61.o diff -ruw linux-4.4.115/drivers/net/ethernet/atheros/atl1c/Makefile linux-4.4.115-fbx/drivers/net/ethernet/atheros/atl1c/Makefile --- linux-4.4.115/drivers/net/ethernet/atheros/atl1c/Makefile 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/net/ethernet/atheros/atl1c/Makefile 2019-10-29 09:26:24.141208052 +0100 @@ -1,2 +1,3 @@ obj-$(CONFIG_ATL1C) += atl1c.o atl1c-objs := atl1c_main.o atl1c_hw.o atl1c_ethtool.o +ccflags-$(CONFIG_ARCH_MSM8998) := -DAPQ_PLATFORM diff -ruw linux-4.4.115/drivers/net/ethernet/atheros/Kconfig linux-4.4.115-fbx/drivers/net/ethernet/atheros/Kconfig --- linux-4.4.115/drivers/net/ethernet/atheros/Kconfig 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/net/ethernet/atheros/Kconfig 2019-01-22 16:16:24.923259266 +0100 @@ -78,4 +78,11 @@ To compile this driver as a module, choose M here. The module will be called alx. + +config ALX_PROP + tristate "Qualcomm eth prop" + depends on PCI + select CRC32 + select MDIO + endif # NET_VENDOR_ATHEROS diff -ruw linux-4.4.115/drivers/net/ethernet/atheros/Makefile linux-4.4.115-fbx/drivers/net/ethernet/atheros/Makefile --- linux-4.4.115/drivers/net/ethernet/atheros/Makefile 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/net/ethernet/atheros/Makefile 2019-01-22 16:16:24.923259266 +0100 @@ -7,3 +7,4 @@ obj-$(CONFIG_ATL1E) += atl1e/ obj-$(CONFIG_ATL1C) += atl1c/ obj-$(CONFIG_ALX) += alx/ +obj-$(CONFIG_ALX_PROP) += alx_prop/ diff -ruw linux-4.4.115/drivers/net/ethernet/Kconfig linux-4.4.115-fbx/drivers/net/ethernet/Kconfig --- linux-4.4.115/drivers/net/ethernet/Kconfig 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/net/ethernet/Kconfig 2019-01-22 16:16:24.899259048 +0100 @@ -110,6 +110,7 @@ source "drivers/net/ethernet/micrel/Kconfig" source "drivers/net/ethernet/microchip/Kconfig" source "drivers/net/ethernet/moxa/Kconfig" +source "drivers/net/ethernet/msm/Kconfig" source "drivers/net/ethernet/myricom/Kconfig" config FEALNX diff -ruw linux-4.4.115/drivers/net/ethernet/Makefile linux-4.4.115-fbx/drivers/net/ethernet/Makefile --- linux-4.4.115/drivers/net/ethernet/Makefile 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/net/ethernet/Makefile 2019-01-22 16:16:24.899259048 +0100 @@ -50,6 +50,7 @@ obj-$(CONFIG_NET_VENDOR_MICREL) += micrel/ obj-$(CONFIG_NET_VENDOR_MICROCHIP) += microchip/ obj-$(CONFIG_NET_VENDOR_MOXART) += moxa/ +obj-$(CONFIG_ARCH_QCOM) += msm/ obj-$(CONFIG_NET_VENDOR_MYRI) += myricom/ obj-$(CONFIG_FEALNX) += fealnx.o obj-$(CONFIG_NET_VENDOR_NATSEMI) += natsemi/ diff -ruw linux-4.4.115/drivers/net/Kconfig linux-4.4.115-fbx/drivers/net/Kconfig --- linux-4.4.115/drivers/net/Kconfig 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/net/Kconfig 2019-10-29 09:26:24.101207660 +0100 @@ -425,4 +425,6 @@ source "drivers/net/hyperv/Kconfig" +source "drivers/net/rmnet/Kconfig" + endif # NETDEVICES diff -ruw linux-4.4.115/drivers/net/Makefile linux-4.4.115-fbx/drivers/net/Makefile --- linux-4.4.115/drivers/net/Makefile 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/net/Makefile 2019-01-22 16:16:24.851258614 +0100 @@ -70,3 +70,4 @@ obj-$(CONFIG_NTB_NETDEV) += ntb_netdev.o obj-$(CONFIG_FUJITSU_ES) += fjes/ +obj-$(CONFIG_RMNET) += rmnet/ diff -ruw linux-4.4.115/drivers/net/ppp/Kconfig linux-4.4.115-fbx/drivers/net/ppp/Kconfig --- linux-4.4.115/drivers/net/ppp/Kconfig 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/net/ppp/Kconfig 2019-01-22 16:16:25.363263250 +0100 @@ -149,6 +149,23 @@ tunnels. L2TP is replacing PPTP for VPN uses. if TTY +config PPPOLAC + tristate "PPP on L2TP Access Concentrator" + depends on PPP && INET + help + L2TP (RFC 2661) is a tunneling protocol widely used in virtual private + networks. This driver handles L2TP data packets between a UDP socket + and a PPP channel, but only permits one session per socket. Thus it is + fairly simple and suited for clients. + +config PPPOPNS + tristate "PPP on PPTP Network Server" + depends on PPP && INET + help + PPTP (RFC 2637) is a tunneling protocol widely used in virtual private + networks. This driver handles PPTP data packets between a RAW socket + and a PPP channel. It is fairly simple and easy to use. + config PPP_ASYNC tristate "PPP support for async serial ports" depends on PPP diff -ruw linux-4.4.115/drivers/net/ppp/Makefile linux-4.4.115-fbx/drivers/net/ppp/Makefile --- linux-4.4.115/drivers/net/ppp/Makefile 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/net/ppp/Makefile 2019-01-22 16:16:25.363263250 +0100 @@ -11,3 +11,5 @@ obj-$(CONFIG_PPPOE) += pppox.o pppoe.o obj-$(CONFIG_PPPOL2TP) += pppox.o obj-$(CONFIG_PPTP) += pppox.o pptp.o +obj-$(CONFIG_PPPOLAC) += pppox.o pppolac.o +obj-$(CONFIG_PPPOPNS) += pppox.o pppopns.o diff -ruw linux-4.4.115/drivers/net/tun.c linux-4.4.115-fbx/drivers/net/tun.c --- linux-4.4.115/drivers/net/tun.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/net/tun.c 2019-10-29 09:26:24.425210831 +0100 @@ -71,6 +71,10 @@ #include #include #include +#include +#include +#include +#include #include @@ -169,6 +173,31 @@ unsigned long updated; }; +/* + * smalltun definitions + */ +#define SMALLTUN_MAGIC 0x6660 +#define SMALLTUN_VERSION 0x1 + +#define TYPE_MASK 0xf +#define TYPE_CLT (1 << 3) + +#define TYPE_TRIGGER 0x0 +#define TYPE_CHALLENGE 0x1 +#define TYPE_CLIENT_HELLO 0x2 +#define TYPE_SERVER_HELLO 0x3 + +#define TYPE_CLT_DATA (TYPE_CLT | 0x0) +#define TYPE_CLT_GET_PARAMS (TYPE_CLT | 0x1) +#define TYPE_CLT_PARAMS (TYPE_CLT | 0x2) + +struct smalltun_pkt_hdr { + u16 magic; + u8 version; + u8 flag_type; + u8 data[0]; +}; + #define TUN_NUM_FLOW_ENTRIES 1024 /* Since the socket were moved to tun_file, to preserve the behavior of persist @@ -182,6 +211,11 @@ kuid_t owner; kgid_t group; + struct smalltun_fp smalltun_fps[4]; + unsigned int smalltun_valid_count; + unsigned int smalltun_valid[4]; + struct rtable *smalltun_rt_cache[4]; + struct net_device *dev; netdev_features_t set_features; #define TUN_USER_FEATURES (NETIF_F_HW_CSUM|NETIF_F_TSO_ECN|NETIF_F_TSO| \ @@ -806,6 +840,184 @@ return 0; } +static int smalltun_is_fastpath(struct tun_struct *tun, + struct sk_buff *skb) +{ + struct iphdr *iph; + const struct smalltun_fp *fp; + struct rtable **prt_cache, *rt_cache; + struct flowi4 fl; + bool match; + size_t i; + + if (!tun->smalltun_valid_count) + return 0; + + if (skb->protocol != htons(ETH_P_IP)) + return 0; + + if (!pskb_may_pull(skb, sizeof(struct iphdr))) + return 0; + + iph = ip_hdr(skb); + + /* lookup smalltun fastpath */ + fp = NULL; + rt_cache = NULL; + for (i = 0; i < ARRAY_SIZE(tun->smalltun_fps); i++) { + if (!tun->smalltun_valid[i]) + continue; + + if (iph->daddr == tun->smalltun_fps[i].inner_dst) { + fp = &tun->smalltun_fps[i]; + prt_cache = &tun->smalltun_rt_cache[i]; + break; + } + } + + if (!fp) + return 0; + + if (fp->af != AF_INET) { + /* FIXME: implement IPv6 transport */ + return 0; + } + + if (!pskb_may_pull(skb, iph->ihl * 4)) + return 0; + + match = false; + for (i = 0; i < fp->rule_count; i++) { + const struct smalltun_rule *r = &fp->rules[i]; + unsigned int sport, dport; + + if (iph->protocol != r->proto) + continue; + + switch (iph->protocol) { + case IPPROTO_UDP: + { + const struct udphdr *udp; + udp = (struct udphdr *)((u8 *)iph + (iph->ihl << 2)); + sport = udp->source; + dport = udp->dest; + break; + } + case IPPROTO_TCP: + { + const struct tcphdr *tcp; + tcp = (struct tcphdr *)((u8 *)iph + (iph->ihl << 2)); + sport = tcp->source; + dport = tcp->dest; + break; + } + default: + match = true; + break; + } + + if (r->src_port_start && r->src_port_end) { + if (sport < r->src_port_start || + sport > r->src_port_end) + continue; + } + + if (r->dst_port_start && r->dst_port_end) { + if (dport < r->dst_port_start || + dport > r->dst_port_end) + continue; + } + match = true; + } + + if (!match) + return 0; + + if (fp->af == AF_INET) { + struct iphdr *oiph; + struct udphdr *oudph; + struct smalltun_pkt_hdr *pkt; + unsigned int payload_len; + + payload_len = skb->len; + + if (skb_cow_head(skb, + sizeof (struct iphdr) + + sizeof (struct udphdr) + + sizeof (struct smalltun_pkt_hdr))) + return 0; + + pkt = (struct smalltun_pkt_hdr *) + skb_push(skb, sizeof (struct smalltun_pkt_hdr)); + oudph = (struct udphdr *) + skb_push(skb, sizeof (struct udphdr)); + skb_reset_transport_header(skb); + oiph = (struct iphdr *) + skb_push(skb, sizeof (struct iphdr)); + skb_reset_network_header(skb); + + /* ip */ + oiph->version = 4; + oiph->tos = 0; + oiph->id = 0; + oiph->ihl = 5; + oiph->frag_off = 0; + oiph->ttl = 64; + oiph->protocol = IPPROTO_UDP; + memcpy(&oiph->saddr, fp->outer_src, 4); + memcpy(&oiph->daddr, fp->outer_dst, 4); + + /* udp */ + oudph->source = fp->outer_src_port; + oudph->dest = fp->outer_dst_port; + oudph->len = htons(payload_len + sizeof (*oudph) + + sizeof (*pkt)); + oudph->check = 0; + + /* smalltun */ + pkt->magic = htons(SMALLTUN_MAGIC); + pkt->version = SMALLTUN_VERSION; + pkt->flag_type = TYPE_CLT_DATA; + + memset(&fl, 0x00, sizeof (fl)); + memcpy(&fl.saddr, fp->outer_src, 4); + memcpy(&fl.daddr, fp->outer_dst, 4); + + if (*prt_cache && (*prt_cache)->dst.obsolete > 0) { + rt_cache = *prt_cache; + *prt_cache = NULL; + ip_rt_put(rt_cache); + } + + rt_cache = *prt_cache; + if (!rt_cache) { + rt_cache = ip_route_output_key(&init_net, &fl); + if (IS_ERR(rt_cache)) { + pr_err("ip_route_output_key(%pI4): %li\n", + &fl.daddr, PTR_ERR(rt_cache)); + return 0; + } + + if (!rt_cache->dst.dev) { + pr_err("ip_route_output_key(%pI4): no dev\n", + &fl.daddr); + return 0; + } + + *prt_cache = rt_cache; + } + + skb_dst_set(skb, dst_clone(&rt_cache->dst)); + skb->dev = skb_dst(skb)->dev; + ip_local_out(&init_net, NULL, skb); + return 1; + } + + /* find route */ + + return 0; +} + /* Net device start xmit */ static netdev_tx_t tun_net_xmit(struct sk_buff *skb, struct net_device *dev) { @@ -862,16 +1074,18 @@ if (unlikely(skb_orphan_frags(skb, GFP_ATOMIC))) goto drop; - if (skb->sk && sk_fullsock(skb->sk)) { - sock_tx_timestamp(skb->sk, &skb_shinfo(skb)->tx_flags); - sw_tx_timestamp(skb); - } + skb_tx_timestamp(skb); /* Orphan the skb - required as we might hang on to it * for indefinite time. */ skb_orphan(skb); + if (smalltun_is_fastpath(tun, skb)) { + rcu_read_unlock(); + return NETDEV_TX_OK; + } + nf_reset(skb); /* Enqueue packet */ @@ -1192,6 +1406,10 @@ } } + if (!(tun->flags & IFF_NO_PI)) + if (pi.flags & htons(CHECKSUM_UNNECESSARY)) + skb->ip_summed = CHECKSUM_UNNECESSARY; + switch (tun->flags & TUN_TYPE_MASK) { case IFF_TUN: if (tun->flags & IFF_NO_PI) { @@ -1895,6 +2113,12 @@ int le; int ret; +#ifdef CONFIG_ANDROID_PARANOID_NETWORK + if (cmd != TUNGETIFF && !capable(CAP_NET_ADMIN)) { + return -EPERM; + } +#endif + if (cmd == TUNSETIFF || cmd == TUNSETQUEUE || _IOC_TYPE(cmd) == 0x89) { if (copy_from_user(&ifr, argp, ifreq_len)) return -EFAULT; @@ -2152,6 +2376,100 @@ ret = 0; break; + case TUNSMALLTUNSETFP: + { + struct smalltun_fp fp; + unsigned int i; + int free_idx; + + ret = -EFAULT; + if (copy_from_user(&fp, argp, sizeof(fp))) + break; + + /* look for duplicate */ + ret = 0; + free_idx = -1; + for (i = 0; i < ARRAY_SIZE(tun->smalltun_fps); i++) { + if (!tun->smalltun_valid[i]) { + if (free_idx == -1) + free_idx = i; + continue; + } + + if (fp.inner_src == tun->smalltun_fps[i].inner_src && + fp.inner_dst == tun->smalltun_fps[i].inner_dst) { + ret = -EEXIST; + break; + } + } + + if (ret) + break; + + if (free_idx == -1) { + ret = -ENOSPC; + break; + } + + memcpy(&tun->smalltun_fps[free_idx], &fp, sizeof (fp)); + tun->smalltun_valid[free_idx] = 1; + tun->smalltun_valid_count++; + tun_debug(KERN_INFO, tun, "new fp rule for %pI4 <=> %pI4 (%u rules)\n", + &fp.inner_src, + &fp.inner_dst, + fp.rule_count); + + if (fp.af == AF_INET) { + tun_debug(KERN_INFO, tun, "outer %pI4:%u <=> %pI4:%u\n", + fp.outer_src, + ntohs(fp.outer_src_port), + fp.outer_dst, + ntohs(fp.outer_dst_port)); + } else { + tun_debug(KERN_INFO, tun, "outer %pI6:%u <=> %pI6:%u\n", + fp.outer_src, + ntohs(fp.outer_src_port), + fp.outer_dst, + ntohs(fp.outer_dst_port)); + } + break; + } + + case TUNSMALLTUNDELFP: + { + struct smalltun_fp fp; + unsigned int i; + + ret = -EFAULT; + if (copy_from_user(&fp, argp, sizeof(fp))) + break; + + /* lookup */ + ret = -ENOENT; + for (i = 0; i < ARRAY_SIZE(tun->smalltun_fps); i++) { + if (fp.inner_src == tun->smalltun_fps[i].inner_src && + fp.inner_dst == tun->smalltun_fps[i].inner_dst) { + ret = 0; + break; + } + } + + if (ret) + break; + + tun->smalltun_valid[i] = 0; + tun->smalltun_valid_count--; + if (tun->smalltun_rt_cache[i]) { + ip_rt_put(tun->smalltun_rt_cache[i]); + tun->smalltun_rt_cache[i] = NULL; + } + + tun_debug(KERN_INFO, tun, "removed fp rule for %pI4 <=> %pI4\n", + &fp.inner_src, + &fp.inner_dst); + break; + } + default: ret = -EINVAL; break; diff -ruw linux-4.4.115/drivers/net/wireless/ath/ath10k/bmi.c linux-4.4.115-fbx/drivers/net/wireless/ath/ath10k/bmi.c --- linux-4.4.115/drivers/net/wireless/ath/ath10k/bmi.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/net/wireless/ath/ath10k/bmi.c 2019-01-22 16:16:25.411263685 +0100 @@ -221,7 +221,7 @@ u32 txlen; int ret; - ath10k_dbg(ar, ATH10K_DBG_BMI, "bmi lz data buffer 0x%p length %d\n", + ath10k_dbg(ar, ATH10K_DBG_BMI, "bmi lz data buffer 0x%pK length %d\n", buffer, length); if (ar->bmi.done_sent) { @@ -287,7 +287,7 @@ int ret; ath10k_dbg(ar, ATH10K_DBG_BMI, - "bmi fast download address 0x%x buffer 0x%p length %d\n", + "bmi fast download address 0x%x buffer 0x%pK length %d\n", address, buffer, length); ret = ath10k_bmi_lz_stream_start(ar, address); diff -ruw linux-4.4.115/drivers/net/wireless/ath/ath10k/ce.c linux-4.4.115-fbx/drivers/net/wireless/ath/ath10k/ce.c --- linux-4.4.115/drivers/net/wireless/ath/ath10k/ce.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/net/wireless/ath/ath10k/ce.c 2019-01-22 16:16:25.411263685 +0100 @@ -16,13 +16,12 @@ */ #include "hif.h" -#include "pci.h" #include "ce.h" #include "debug.h" /* * Support for Copy Engine hardware, which is mainly used for - * communication between Host and Target over a PCIe interconnect. + * communication between Host and Target over a PCIe/SNOC/AHB interconnect. */ /* @@ -33,13 +32,13 @@ * Each ring consists of a number of descriptors which specify * an address, length, and meta-data. * - * Typically, one side of the PCIe interconnect (Host or Target) + * Typically, one side of the PCIe/AHB/SNOC interconnect (Host or Target) * controls one ring and the other side controls the other ring. * The source side chooses when to initiate a transfer and it * chooses what to send (buffer address, length). The destination * side keeps a supply of "anonymous receive buffers" available and * it handles incoming data as it arrives (when the destination - * recieves an interrupt). + * receives an interrupt). * * The sender may send a simple buffer (address/length) or it may * send a small list of buffers. When a small list is sent, hardware @@ -63,201 +62,401 @@ u32 ce_ctrl_addr, unsigned int n) { - ath10k_pci_write32(ar, ce_ctrl_addr + DST_WR_INDEX_ADDRESS, n); + struct bus_opaque *ar_opaque = ath10k_bus_priv(ar); + + ar_opaque->bus_ops->write32(ar, + ce_ctrl_addr + ar->hw_ce_regs->dst_wr_index_addr, n); } static inline u32 ath10k_ce_dest_ring_write_index_get(struct ath10k *ar, u32 ce_ctrl_addr) { - return ath10k_pci_read32(ar, ce_ctrl_addr + DST_WR_INDEX_ADDRESS); + struct bus_opaque *ar_opaque = ath10k_bus_priv(ar); + + return ar_opaque->bus_ops->read32(ar, + ce_ctrl_addr + ar->hw_ce_regs->dst_wr_index_addr); } static inline void ath10k_ce_src_ring_write_index_set(struct ath10k *ar, u32 ce_ctrl_addr, unsigned int n) { - ath10k_pci_write32(ar, ce_ctrl_addr + SR_WR_INDEX_ADDRESS, n); + struct bus_opaque *ar_opaque = ath10k_bus_priv(ar); + + ar_opaque->bus_ops->write32(ar, + ce_ctrl_addr + ar->hw_ce_regs->sr_wr_index_addr, n); } static inline u32 ath10k_ce_src_ring_write_index_get(struct ath10k *ar, u32 ce_ctrl_addr) { - return ath10k_pci_read32(ar, ce_ctrl_addr + SR_WR_INDEX_ADDRESS); + struct bus_opaque *ar_opaque = ath10k_bus_priv(ar); + + return ar_opaque->bus_ops->read32(ar, + ce_ctrl_addr + ar->hw_ce_regs->sr_wr_index_addr); +} + +static inline u32 ath10k_ce_src_ring_read_index_get_from_ddr( + struct ath10k *ar, u32 ce_id) +{ + struct bus_opaque *ar_opaque = ath10k_bus_priv(ar); + + return ar_opaque->vaddr_rri_on_ddr[ce_id] & CE_DDR_RRI_MASK; } static inline u32 ath10k_ce_src_ring_read_index_get(struct ath10k *ar, u32 ce_ctrl_addr) { - return ath10k_pci_read32(ar, ce_ctrl_addr + CURRENT_SRRI_ADDRESS); + struct bus_opaque *ar_opaque = ath10k_bus_priv(ar); + u32 ce_id = COPY_ENGINE_ID(ce_ctrl_addr); + struct ath10k_ce_pipe *ce_state = &ar_opaque->ce_states[ce_id]; + u32 index; + + if (ar->rri_on_ddr && (ce_state->attr_flags & CE_ATTR_DIS_INTR)) + index = ath10k_ce_src_ring_read_index_get_from_ddr(ar, ce_id); + else + index = ar_opaque->bus_ops->read32(ar, + ce_ctrl_addr + ar->hw_ce_regs->current_srri_addr); + + return index; +} + +static inline void ath10k_ce_shadow_src_ring_write_index_set(struct ath10k *ar, + u32 ce_ctrl_addr, + unsigned int n) +{ + struct bus_opaque *ar_opaque = ath10k_bus_priv(ar); + + ar_opaque->bus_ops->write32(ar, shadow_sr_wr_ind_addr(ar, + ce_ctrl_addr), n); +} + +static inline void ath10k_ce_shadow_dest_ring_write_index_set(struct ath10k *ar, + u32 ce_ctrl_addr, + unsigned int n) +{ + struct bus_opaque *ar_opaque = ath10k_bus_priv(ar); + + ar_opaque->bus_ops->write32(ar, shadow_dst_wr_ind_addr(ar, + ce_ctrl_addr), + n); } static inline void ath10k_ce_src_ring_base_addr_set(struct ath10k *ar, u32 ce_ctrl_addr, unsigned int addr) { - ath10k_pci_write32(ar, ce_ctrl_addr + SR_BA_ADDRESS, addr); + struct bus_opaque *ar_opaque = ath10k_bus_priv(ar); + + ar_opaque->bus_ops->write32(ar, + ce_ctrl_addr + ar->hw_ce_regs->sr_base_addr, addr); } static inline void ath10k_ce_src_ring_size_set(struct ath10k *ar, u32 ce_ctrl_addr, unsigned int n) { - ath10k_pci_write32(ar, ce_ctrl_addr + SR_SIZE_ADDRESS, n); + struct bus_opaque *ar_opaque = ath10k_bus_priv(ar); + + ar_opaque->bus_ops->write32(ar, + ce_ctrl_addr + ar->hw_ce_regs->sr_size_addr, n); } static inline void ath10k_ce_src_ring_dmax_set(struct ath10k *ar, u32 ce_ctrl_addr, unsigned int n) { - u32 ctrl1_addr = ath10k_pci_read32((ar), - (ce_ctrl_addr) + CE_CTRL1_ADDRESS); + struct bus_opaque *ar_opaque = ath10k_bus_priv(ar); + struct ath10k_hw_ce_ctrl1 *ctrl_regs = ar->hw_ce_regs->ctrl1_regs; - ath10k_pci_write32(ar, ce_ctrl_addr + CE_CTRL1_ADDRESS, - (ctrl1_addr & ~CE_CTRL1_DMAX_LENGTH_MASK) | - CE_CTRL1_DMAX_LENGTH_SET(n)); + u32 ctrl1_addr = ar_opaque->bus_ops->read32((ar), + (ce_ctrl_addr) + ctrl_regs->addr); + + ar_opaque->bus_ops->write32(ar, ce_ctrl_addr + ctrl_regs->addr, + (ctrl1_addr & ~(ctrl_regs->dmax->mask)) | + ctrl_regs->dmax->set(n, ctrl_regs->dmax)); } static inline void ath10k_ce_src_ring_byte_swap_set(struct ath10k *ar, u32 ce_ctrl_addr, unsigned int n) { - u32 ctrl1_addr = ath10k_pci_read32(ar, ce_ctrl_addr + CE_CTRL1_ADDRESS); + struct bus_opaque *ar_opaque = ath10k_bus_priv(ar); + struct ath10k_hw_ce_ctrl1 *ctrl_regs = ar->hw_ce_regs->ctrl1_regs; + + u32 ctrl1_addr = ar_opaque->bus_ops->read32(ar, ce_ctrl_addr + + ctrl_regs->addr); - ath10k_pci_write32(ar, ce_ctrl_addr + CE_CTRL1_ADDRESS, - (ctrl1_addr & ~CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK) | - CE_CTRL1_SRC_RING_BYTE_SWAP_EN_SET(n)); + ar_opaque->bus_ops->write32(ar, ce_ctrl_addr + ctrl_regs->addr, + (ctrl1_addr & ~(ctrl_regs->src_ring->mask)) | + ctrl_regs->src_ring->set(n, ctrl_regs->src_ring)); } static inline void ath10k_ce_dest_ring_byte_swap_set(struct ath10k *ar, u32 ce_ctrl_addr, unsigned int n) { - u32 ctrl1_addr = ath10k_pci_read32(ar, ce_ctrl_addr + CE_CTRL1_ADDRESS); + struct bus_opaque *ar_opaque = ath10k_bus_priv(ar); + struct ath10k_hw_ce_ctrl1 *ctrl_regs = ar->hw_ce_regs->ctrl1_regs; - ath10k_pci_write32(ar, ce_ctrl_addr + CE_CTRL1_ADDRESS, - (ctrl1_addr & ~CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK) | - CE_CTRL1_DST_RING_BYTE_SWAP_EN_SET(n)); + u32 ctrl1_addr = ar_opaque->bus_ops->read32(ar, ce_ctrl_addr + + ctrl_regs->addr); + + ar_opaque->bus_ops->write32(ar, ce_ctrl_addr + ctrl_regs->addr, + (ctrl1_addr & ~(ctrl_regs->dst_ring->mask)) | + ctrl_regs->dst_ring->set(n, ctrl_regs->dst_ring)); } static inline u32 ath10k_ce_dest_ring_read_index_get(struct ath10k *ar, u32 ce_ctrl_addr) { - return ath10k_pci_read32(ar, ce_ctrl_addr + CURRENT_DRRI_ADDRESS); + struct bus_opaque *ar_opaque = ath10k_bus_priv(ar); + u32 ce_id = COPY_ENGINE_ID(ce_ctrl_addr); + struct ath10k_ce_pipe *ce_state = &ar_opaque->ce_states[ce_id]; + u32 index; + + if (ar->rri_on_ddr && (ce_state->attr_flags & CE_ATTR_DIS_INTR)) + index = (ar_opaque->vaddr_rri_on_ddr[ce_id] >> + CE_DDR_RRI_SHIFT) & + CE_DDR_RRI_MASK; + else + index = ar_opaque->bus_ops->read32(ar, + ce_ctrl_addr + ar->hw_ce_regs->current_drri_addr); + + return index; } static inline void ath10k_ce_dest_ring_base_addr_set(struct ath10k *ar, u32 ce_ctrl_addr, u32 addr) { - ath10k_pci_write32(ar, ce_ctrl_addr + DR_BA_ADDRESS, addr); + struct bus_opaque *ar_opaque = ath10k_bus_priv(ar); + + ar_opaque->bus_ops->write32(ar, + ce_ctrl_addr + ar->hw_ce_regs->dr_base_addr, addr); } static inline void ath10k_ce_dest_ring_size_set(struct ath10k *ar, u32 ce_ctrl_addr, unsigned int n) { - ath10k_pci_write32(ar, ce_ctrl_addr + DR_SIZE_ADDRESS, n); + struct bus_opaque *ar_opaque = ath10k_bus_priv(ar); + + ar_opaque->bus_ops->write32(ar, + ce_ctrl_addr + ar->hw_ce_regs->dr_size_addr, n); } static inline void ath10k_ce_src_ring_highmark_set(struct ath10k *ar, u32 ce_ctrl_addr, unsigned int n) { - u32 addr = ath10k_pci_read32(ar, ce_ctrl_addr + SRC_WATERMARK_ADDRESS); - - ath10k_pci_write32(ar, ce_ctrl_addr + SRC_WATERMARK_ADDRESS, - (addr & ~SRC_WATERMARK_HIGH_MASK) | - SRC_WATERMARK_HIGH_SET(n)); + struct bus_opaque *ar_opaque = ath10k_bus_priv(ar); + struct ath10k_hw_ce_dst_src_wm_regs *srcr_wm = ar->hw_ce_regs->wm_srcr; + u32 addr = ar_opaque->bus_ops->read32(ar, ce_ctrl_addr + srcr_wm->addr); + + ar_opaque->bus_ops->write32(ar, ce_ctrl_addr + srcr_wm->addr, + (addr & ~(srcr_wm->wm_high->mask)) | + (srcr_wm->wm_high->set(n, srcr_wm->wm_high))); } static inline void ath10k_ce_src_ring_lowmark_set(struct ath10k *ar, u32 ce_ctrl_addr, unsigned int n) { - u32 addr = ath10k_pci_read32(ar, ce_ctrl_addr + SRC_WATERMARK_ADDRESS); - - ath10k_pci_write32(ar, ce_ctrl_addr + SRC_WATERMARK_ADDRESS, - (addr & ~SRC_WATERMARK_LOW_MASK) | - SRC_WATERMARK_LOW_SET(n)); + struct bus_opaque *ar_opaque = ath10k_bus_priv(ar); + struct ath10k_hw_ce_dst_src_wm_regs *srcr_wm = ar->hw_ce_regs->wm_srcr; + u32 addr = ar_opaque->bus_ops->read32(ar, ce_ctrl_addr + srcr_wm->addr); + + ar_opaque->bus_ops->write32(ar, ce_ctrl_addr + srcr_wm->addr, + (addr & ~(srcr_wm->wm_low->mask)) | + (srcr_wm->wm_low->set(n, srcr_wm->wm_low))); } static inline void ath10k_ce_dest_ring_highmark_set(struct ath10k *ar, u32 ce_ctrl_addr, unsigned int n) { - u32 addr = ath10k_pci_read32(ar, ce_ctrl_addr + DST_WATERMARK_ADDRESS); - - ath10k_pci_write32(ar, ce_ctrl_addr + DST_WATERMARK_ADDRESS, - (addr & ~DST_WATERMARK_HIGH_MASK) | - DST_WATERMARK_HIGH_SET(n)); + struct bus_opaque *ar_opaque = ath10k_bus_priv(ar); + struct ath10k_hw_ce_dst_src_wm_regs *dstr_wm = ar->hw_ce_regs->wm_dstr; + u32 addr = ar_opaque->bus_ops->read32(ar, ce_ctrl_addr + dstr_wm->addr); + + ar_opaque->bus_ops->write32(ar, ce_ctrl_addr + dstr_wm->addr, + (addr & ~(dstr_wm->wm_high->mask)) | + (dstr_wm->wm_high->set(n, dstr_wm->wm_high))); } static inline void ath10k_ce_dest_ring_lowmark_set(struct ath10k *ar, u32 ce_ctrl_addr, unsigned int n) { - u32 addr = ath10k_pci_read32(ar, ce_ctrl_addr + DST_WATERMARK_ADDRESS); - - ath10k_pci_write32(ar, ce_ctrl_addr + DST_WATERMARK_ADDRESS, - (addr & ~DST_WATERMARK_LOW_MASK) | - DST_WATERMARK_LOW_SET(n)); + struct bus_opaque *ar_opaque = ath10k_bus_priv(ar); + struct ath10k_hw_ce_dst_src_wm_regs *dstr_wm = ar->hw_ce_regs->wm_dstr; + u32 addr = ar_opaque->bus_ops->read32(ar, ce_ctrl_addr + dstr_wm->addr); + + ar_opaque->bus_ops->write32(ar, ce_ctrl_addr + dstr_wm->addr, + (addr & ~(dstr_wm->wm_low->mask)) | + (dstr_wm->wm_low->set(n, dstr_wm->wm_low))); } static inline void ath10k_ce_copy_complete_inter_enable(struct ath10k *ar, u32 ce_ctrl_addr) { - u32 host_ie_addr = ath10k_pci_read32(ar, - ce_ctrl_addr + HOST_IE_ADDRESS); + struct bus_opaque *ar_opaque = ath10k_bus_priv(ar); + struct ath10k_hw_ce_host_ie *host_ie = ar->hw_ce_regs->host_ie; - ath10k_pci_write32(ar, ce_ctrl_addr + HOST_IE_ADDRESS, - host_ie_addr | HOST_IE_COPY_COMPLETE_MASK); + u32 host_ie_addr = ar_opaque->bus_ops->read32(ar, + ce_ctrl_addr + ar->hw_ce_regs->host_ie_addr); + + ar_opaque->bus_ops->write32(ar, + ce_ctrl_addr + ar->hw_ce_regs->host_ie_addr, + host_ie_addr | host_ie->copy_complete->mask); } static inline void ath10k_ce_copy_complete_intr_disable(struct ath10k *ar, u32 ce_ctrl_addr) { - u32 host_ie_addr = ath10k_pci_read32(ar, - ce_ctrl_addr + HOST_IE_ADDRESS); + struct bus_opaque *ar_opaque = ath10k_bus_priv(ar); + struct ath10k_hw_ce_host_ie *host_ie = ar->hw_ce_regs->host_ie; + + u32 host_ie_addr = ar_opaque->bus_ops->read32(ar, + ce_ctrl_addr + ar->hw_ce_regs->host_ie_addr); - ath10k_pci_write32(ar, ce_ctrl_addr + HOST_IE_ADDRESS, - host_ie_addr & ~HOST_IE_COPY_COMPLETE_MASK); + ar_opaque->bus_ops->write32(ar, + ce_ctrl_addr + ar->hw_ce_regs->host_ie_addr, + host_ie_addr & ~(host_ie->copy_complete->mask)); } static inline void ath10k_ce_watermark_intr_disable(struct ath10k *ar, u32 ce_ctrl_addr) { - u32 host_ie_addr = ath10k_pci_read32(ar, - ce_ctrl_addr + HOST_IE_ADDRESS); + struct bus_opaque *ar_opaque = ath10k_bus_priv(ar); + struct ath10k_hw_ce_host_wm_regs *wm_regs = ar->hw_ce_regs->wm_regs; - ath10k_pci_write32(ar, ce_ctrl_addr + HOST_IE_ADDRESS, - host_ie_addr & ~CE_WATERMARK_MASK); + u32 host_ie_addr = ar_opaque->bus_ops->read32(ar, + ce_ctrl_addr + ar->hw_ce_regs->host_ie_addr); + + ar_opaque->bus_ops->write32(ar, + ce_ctrl_addr + ar->hw_ce_regs->host_ie_addr, + host_ie_addr & ~(wm_regs->wm_mask)); } static inline void ath10k_ce_error_intr_enable(struct ath10k *ar, u32 ce_ctrl_addr) { - u32 misc_ie_addr = ath10k_pci_read32(ar, - ce_ctrl_addr + MISC_IE_ADDRESS); + struct bus_opaque *ar_opaque = ath10k_bus_priv(ar); + struct ath10k_hw_ce_misc_regs *misc_regs = ar->hw_ce_regs->misc_regs; + + u32 misc_ie_addr = ar_opaque->bus_ops->read32(ar, + ce_ctrl_addr + ar->hw_ce_regs->misc_ie_addr); - ath10k_pci_write32(ar, ce_ctrl_addr + MISC_IE_ADDRESS, - misc_ie_addr | CE_ERROR_MASK); + ar_opaque->bus_ops->write32(ar, + ce_ctrl_addr + ar->hw_ce_regs->misc_ie_addr, + misc_ie_addr | misc_regs->err_mask); } static inline void ath10k_ce_error_intr_disable(struct ath10k *ar, u32 ce_ctrl_addr) { - u32 misc_ie_addr = ath10k_pci_read32(ar, - ce_ctrl_addr + MISC_IE_ADDRESS); + struct bus_opaque *ar_opaque = ath10k_bus_priv(ar); + struct ath10k_hw_ce_misc_regs *misc_regs = ar->hw_ce_regs->misc_regs; - ath10k_pci_write32(ar, ce_ctrl_addr + MISC_IE_ADDRESS, - misc_ie_addr & ~CE_ERROR_MASK); + u32 misc_ie_addr = ar_opaque->bus_ops->read32(ar, + ce_ctrl_addr + ar->hw_ce_regs->misc_ie_addr); + + ar_opaque->bus_ops->write32(ar, + ce_ctrl_addr + ar->hw_ce_regs->misc_ie_addr, + misc_ie_addr & ~(misc_regs->err_mask)); } static inline void ath10k_ce_engine_int_status_clear(struct ath10k *ar, u32 ce_ctrl_addr, unsigned int mask) { - ath10k_pci_write32(ar, ce_ctrl_addr + HOST_IS_ADDRESS, mask); + struct bus_opaque *ar_opaque = ath10k_bus_priv(ar); + struct ath10k_hw_ce_host_wm_regs *wm_regs = ar->hw_ce_regs->wm_regs; + + ar_opaque->bus_ops->write32(ar, ce_ctrl_addr + wm_regs->addr, mask); +} + +u32 shadow_sr_wr_ind_addr(struct ath10k *ar, u32 ctrl_addr) +{ + u32 addr = 0; + u32 ce = COPY_ENGINE_ID(ctrl_addr); + + switch (ce) { + case 0: + addr = SHADOW_VALUE0; + break; + case 3: + addr = SHADOW_VALUE3; + break; + case 4: + addr = SHADOW_VALUE4; + break; + case 5: + addr = SHADOW_VALUE5; + break; + case 7: + addr = SHADOW_VALUE7; + break; + default: + ath10k_err(ar, "invalid CE ctrl_addr (CE=%d)", ce); + WARN_ON(1); + } + return addr; +} + +u32 shadow_dst_wr_ind_addr(struct ath10k *ar, u32 ctrl_addr) +{ + u32 addr = 0; + u32 ce = COPY_ENGINE_ID(ctrl_addr); + + switch (ce) { + case 1: + addr = SHADOW_VALUE13; + break; + case 2: + addr = SHADOW_VALUE14; + break; + case 5: + addr = SHADOW_VALUE17; + break; + case 7: + addr = SHADOW_VALUE19; + break; + case 8: + addr = SHADOW_VALUE20; + break; + case 9: + addr = SHADOW_VALUE21; + break; + case 10: + addr = SHADOW_VALUE22; + break; + case 11: + addr = SHADOW_VALUE23; + break; + default: + ath10k_err(ar, "invalid CE ctrl_addr (CE=%d)", ce); + WARN_ON(1); + } + + return addr; +} + +static inline void ath10k_ce_snoc_addr_config(struct ce_desc *sdesc, + dma_addr_t buffer, + unsigned int flags) +{ + __le32 *addr = (__le32 *)&sdesc->addr; + + flags |= upper_32_bits(buffer) & CE_DESC_FLAGS_GET_MASK; + addr[0] = __cpu_to_le32(buffer); + addr[1] = flags; + if (flags & CE_SEND_FLAG_GATHER) + addr[1] |= CE_WCN3990_DESC_FLAGS_GATHER; + else + addr[1] &= ~CE_WCN3990_DESC_FLAGS_GATHER; } /* @@ -267,7 +466,7 @@ */ int ath10k_ce_send_nolock(struct ath10k_ce_pipe *ce_state, void *per_transfer_context, - u32 buffer, + dma_addr_t buffer, unsigned int nbytes, unsigned int transfer_id, unsigned int flags) @@ -276,16 +475,20 @@ struct ath10k_ce_ring *src_ring = ce_state->src_ring; struct ce_desc *desc, sdesc; unsigned int nentries_mask = src_ring->nentries_mask; - unsigned int sw_index = src_ring->sw_index; + unsigned int sw_index; unsigned int write_index = src_ring->write_index; u32 ctrl_addr = ce_state->ctrl_addr; u32 desc_flags = 0; int ret = 0; + if (test_bit(ATH10K_FLAG_CRASH_FLUSH, &ar->dev_flags)) + return -ESHUTDOWN; + if (nbytes > ce_state->src_sz_max) ath10k_warn(ar, "%s: send more we can (nbytes: %d, max: %d)\n", __func__, nbytes, ce_state->src_sz_max); + sw_index = ath10k_ce_src_ring_read_index_get_from_ddr(ar, ce_state->id); if (unlikely(CE_RING_DELTA(nentries_mask, write_index, sw_index - 1) <= 0)) { ret = -ENOSR; @@ -299,10 +502,15 @@ if (flags & CE_SEND_FLAG_GATHER) desc_flags |= CE_DESC_FLAGS_GATHER; + if (flags & CE_SEND_FLAG_BYTE_SWAP) desc_flags |= CE_DESC_FLAGS_BYTE_SWAP; + if (QCA_REV_WCN3990(ar)) + ath10k_ce_snoc_addr_config(&sdesc, buffer, flags); + else sdesc.addr = __cpu_to_le32(buffer); + sdesc.nbytes = __cpu_to_le16(nbytes); sdesc.flags = __cpu_to_le16(desc_flags); @@ -314,8 +522,14 @@ write_index = CE_RING_IDX_INCR(nentries_mask, write_index); /* WORKAROUND */ - if (!(flags & CE_SEND_FLAG_GATHER)) - ath10k_ce_src_ring_write_index_set(ar, ctrl_addr, write_index); + if (!(flags & CE_SEND_FLAG_GATHER)) { + if (QCA_REV_WCN3990(ar)) + ath10k_ce_shadow_src_ring_write_index_set(ar, ctrl_addr, + write_index); + else + ath10k_ce_src_ring_write_index_set(ar, ctrl_addr, + write_index); + } src_ring->write_index = write_index; exit: @@ -325,11 +539,11 @@ void __ath10k_ce_send_revert(struct ath10k_ce_pipe *pipe) { struct ath10k *ar = pipe->ar; - struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); + struct bus_opaque *ar_opaque = ath10k_bus_priv(ar); struct ath10k_ce_ring *src_ring = pipe->src_ring; u32 ctrl_addr = pipe->ctrl_addr; - lockdep_assert_held(&ar_pci->ce_lock); + lockdep_assert_held(&ar_opaque->ce_lock); /* * This function must be called only if there is an incomplete @@ -351,19 +565,19 @@ int ath10k_ce_send(struct ath10k_ce_pipe *ce_state, void *per_transfer_context, - u32 buffer, + dma_addr_t buffer, unsigned int nbytes, unsigned int transfer_id, unsigned int flags) { struct ath10k *ar = ce_state->ar; - struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); + struct bus_opaque *ar_opaque = ath10k_bus_priv(ar); int ret; - spin_lock_bh(&ar_pci->ce_lock); + spin_lock_bh(&ar_opaque->ce_lock); ret = ath10k_ce_send_nolock(ce_state, per_transfer_context, buffer, nbytes, transfer_id, flags); - spin_unlock_bh(&ar_pci->ce_lock); + spin_unlock_bh(&ar_opaque->ce_lock); return ret; } @@ -371,14 +585,14 @@ int ath10k_ce_num_free_src_entries(struct ath10k_ce_pipe *pipe) { struct ath10k *ar = pipe->ar; - struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); + struct bus_opaque *ar_opaque = ath10k_bus_priv(ar); int delta; - spin_lock_bh(&ar_pci->ce_lock); + spin_lock_bh(&ar_opaque->ce_lock); delta = CE_RING_DELTA(pipe->src_ring->nentries_mask, pipe->src_ring->write_index, pipe->src_ring->sw_index - 1); - spin_unlock_bh(&ar_pci->ce_lock); + spin_unlock_bh(&ar_opaque->ce_lock); return delta; } @@ -386,21 +600,22 @@ int __ath10k_ce_rx_num_free_bufs(struct ath10k_ce_pipe *pipe) { struct ath10k *ar = pipe->ar; - struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); + struct bus_opaque *ar_opaque = ath10k_bus_priv(ar); struct ath10k_ce_ring *dest_ring = pipe->dest_ring; unsigned int nentries_mask = dest_ring->nentries_mask; unsigned int write_index = dest_ring->write_index; unsigned int sw_index = dest_ring->sw_index; - lockdep_assert_held(&ar_pci->ce_lock); + lockdep_assert_held(&ar_opaque->ce_lock); return CE_RING_DELTA(nentries_mask, write_index, sw_index - 1); } -int __ath10k_ce_rx_post_buf(struct ath10k_ce_pipe *pipe, void *ctx, u32 paddr) +int __ath10k_ce_rx_post_buf(struct ath10k_ce_pipe *pipe, void *ctx, + dma_addr_t paddr) { struct ath10k *ar = pipe->ar; - struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); + struct bus_opaque *ar_opaque = ath10k_bus_priv(ar); struct ath10k_ce_ring *dest_ring = pipe->dest_ring; unsigned int nentries_mask = dest_ring->nentries_mask; unsigned int write_index = dest_ring->write_index; @@ -409,12 +624,19 @@ struct ce_desc *desc = CE_DEST_RING_TO_DESC(base, write_index); u32 ctrl_addr = pipe->ctrl_addr; - lockdep_assert_held(&ar_pci->ce_lock); + lockdep_assert_held(&ar_opaque->ce_lock); - if (CE_RING_DELTA(nentries_mask, write_index, sw_index - 1) == 0) + if ((pipe->id != 5) && + CE_RING_DELTA(nentries_mask, write_index, sw_index - 1) == 0) return -ENOSPC; + if (QCA_REV_WCN3990(ar)) { + desc->addr = paddr; + desc->addr &= CE_DESC_37BIT_ADDR_MASK; + } else { desc->addr = __cpu_to_le32(paddr); + } + desc->nbytes = 0; dest_ring->per_transfer_context[write_index] = ctx; @@ -425,15 +647,29 @@ return 0; } -int ath10k_ce_rx_post_buf(struct ath10k_ce_pipe *pipe, void *ctx, u32 paddr) +void ath10k_ce_rx_update_write_idx(struct ath10k_ce_pipe *pipe, u32 nentries) { struct ath10k *ar = pipe->ar; - struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); + struct ath10k_ce_ring *dest_ring = pipe->dest_ring; + unsigned int nentries_mask = dest_ring->nentries_mask; + unsigned int write_index = dest_ring->write_index; + u32 ctrl_addr = pipe->ctrl_addr; + + write_index = CE_RING_IDX_ADD(nentries_mask, write_index, nentries); + ath10k_ce_dest_ring_write_index_set(ar, ctrl_addr, write_index); + dest_ring->write_index = write_index; +} + +int ath10k_ce_rx_post_buf(struct ath10k_ce_pipe *pipe, void *ctx, + dma_addr_t paddr) +{ + struct ath10k *ar = pipe->ar; + struct bus_opaque *ar_opaque = ath10k_bus_priv(ar); int ret; - spin_lock_bh(&ar_pci->ce_lock); + spin_lock_bh(&ar_opaque->ce_lock); ret = __ath10k_ce_rx_post_buf(pipe, ctx, paddr); - spin_unlock_bh(&ar_pci->ce_lock); + spin_unlock_bh(&ar_opaque->ce_lock); return ret; } @@ -444,14 +680,10 @@ */ int ath10k_ce_completed_recv_next_nolock(struct ath10k_ce_pipe *ce_state, void **per_transfer_contextp, - u32 *bufferp, - unsigned int *nbytesp, - unsigned int *transfer_idp, - unsigned int *flagsp) + unsigned int *nbytesp) { struct ath10k_ce_ring *dest_ring = ce_state->dest_ring; unsigned int nentries_mask = dest_ring->nentries_mask; - struct ath10k *ar = ce_state->ar; unsigned int sw_index = dest_ring->sw_index; struct ce_desc *base = dest_ring->base_addr_owner_space; @@ -476,20 +708,16 @@ desc->nbytes = 0; /* Return data from completed destination descriptor */ - *bufferp = __le32_to_cpu(sdesc.addr); *nbytesp = nbytes; - *transfer_idp = MS(__le16_to_cpu(sdesc.flags), CE_DESC_FLAGS_META_DATA); - - if (__le16_to_cpu(sdesc.flags) & CE_DESC_FLAGS_BYTE_SWAP) - *flagsp = CE_RECV_FLAG_SWAPPED; - else - *flagsp = 0; if (per_transfer_contextp) *per_transfer_contextp = dest_ring->per_transfer_context[sw_index]; - /* sanity */ + /* Copy engine 5 (HTT Rx) will reuse the same transfer context. + * So update transfer context all CEs except CE5. + */ + if (ce_state->id != 5) dest_ring->per_transfer_context[sw_index] = NULL; /* Update sw_index */ @@ -501,21 +729,17 @@ int ath10k_ce_completed_recv_next(struct ath10k_ce_pipe *ce_state, void **per_transfer_contextp, - u32 *bufferp, - unsigned int *nbytesp, - unsigned int *transfer_idp, - unsigned int *flagsp) + unsigned int *nbytesp) { struct ath10k *ar = ce_state->ar; - struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); + struct bus_opaque *ar_opaque = ath10k_bus_priv(ar); int ret; - spin_lock_bh(&ar_pci->ce_lock); + spin_lock_bh(&ar_opaque->ce_lock); ret = ath10k_ce_completed_recv_next_nolock(ce_state, per_transfer_contextp, - bufferp, nbytesp, - transfer_idp, flagsp); - spin_unlock_bh(&ar_pci->ce_lock); + nbytesp); + spin_unlock_bh(&ar_opaque->ce_lock); return ret; } @@ -530,7 +754,7 @@ unsigned int write_index; int ret; struct ath10k *ar; - struct ath10k_pci *ar_pci; + struct bus_opaque *ar_opaque; dest_ring = ce_state->dest_ring; @@ -538,9 +762,9 @@ return -EIO; ar = ce_state->ar; - ar_pci = ath10k_pci_priv(ar); + ar_opaque = ath10k_bus_priv(ar); - spin_lock_bh(&ar_pci->ce_lock); + spin_lock_bh(&ar_opaque->ce_lock); nentries_mask = dest_ring->nentries_mask; sw_index = dest_ring->sw_index; @@ -568,7 +792,7 @@ ret = -EIO; } - spin_unlock_bh(&ar_pci->ce_lock); + spin_unlock_bh(&ar_opaque->ce_lock); return ret; } @@ -636,7 +860,7 @@ unsigned int write_index; int ret; struct ath10k *ar; - struct ath10k_pci *ar_pci; + struct bus_opaque *ar_opaque; src_ring = ce_state->src_ring; @@ -644,9 +868,9 @@ return -EIO; ar = ce_state->ar; - ar_pci = ath10k_pci_priv(ar); + ar_opaque = ath10k_bus_priv(ar); - spin_lock_bh(&ar_pci->ce_lock); + spin_lock_bh(&ar_opaque->ce_lock); nentries_mask = src_ring->nentries_mask; sw_index = src_ring->sw_index; @@ -677,7 +901,7 @@ ret = -EIO; } - spin_unlock_bh(&ar_pci->ce_lock); + spin_unlock_bh(&ar_opaque->ce_lock); return ret; } @@ -686,13 +910,13 @@ void **per_transfer_contextp) { struct ath10k *ar = ce_state->ar; - struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); + struct bus_opaque *ar_opaque = ath10k_bus_priv(ar); int ret; - spin_lock_bh(&ar_pci->ce_lock); + spin_lock_bh(&ar_opaque->ce_lock); ret = ath10k_ce_completed_send_next_nolock(ce_state, per_transfer_contextp); - spin_unlock_bh(&ar_pci->ce_lock); + spin_unlock_bh(&ar_opaque->ce_lock); return ret; } @@ -705,17 +929,18 @@ */ void ath10k_ce_per_engine_service(struct ath10k *ar, unsigned int ce_id) { - struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); - struct ath10k_ce_pipe *ce_state = &ar_pci->ce_states[ce_id]; + struct bus_opaque *ar_opaque = ath10k_bus_priv(ar); + struct ath10k_ce_pipe *ce_state = &ar_opaque->ce_states[ce_id]; + struct ath10k_hw_ce_host_wm_regs *wm_regs = ar->hw_ce_regs->wm_regs; u32 ctrl_addr = ce_state->ctrl_addr; - spin_lock_bh(&ar_pci->ce_lock); + spin_lock_bh(&ar_opaque->ce_lock); /* Clear the copy-complete interrupts that will be handled here. */ ath10k_ce_engine_int_status_clear(ar, ctrl_addr, - HOST_IS_COPY_COMPLETE_MASK); + wm_regs->cc_mask); - spin_unlock_bh(&ar_pci->ce_lock); + spin_unlock_bh(&ar_opaque->ce_lock); if (ce_state->recv_cb) ce_state->recv_cb(ce_state); @@ -723,15 +948,15 @@ if (ce_state->send_cb) ce_state->send_cb(ce_state); - spin_lock_bh(&ar_pci->ce_lock); + spin_lock_bh(&ar_opaque->ce_lock); /* * Misc CE interrupts are not being handled, but still need * to be cleared. */ - ath10k_ce_engine_int_status_clear(ar, ctrl_addr, CE_WATERMARK_MASK); + ath10k_ce_engine_int_status_clear(ar, ctrl_addr, wm_regs->wm_mask); - spin_unlock_bh(&ar_pci->ce_lock); + spin_unlock_bh(&ar_opaque->ce_lock); } /* @@ -744,8 +969,16 @@ { int ce_id; u32 intr_summary; + struct ath10k_ce_pipe *ce_state; + struct bus_opaque *ar_opaque = ath10k_bus_priv(ar); - intr_summary = CE_INTERRUPT_SUMMARY(ar); + if (test_bit(ATH10K_FLAG_CRASH_FLUSH, &ar->dev_flags)) + return; + + if (ar->target_version == ATH10K_HW_WCN3990) + intr_summary = 0xFFF; + else + intr_summary = CE_INTERRUPT_SUMMARY(ar, ar_opaque); for (ce_id = 0; intr_summary && (ce_id < CE_COUNT); ce_id++) { if (intr_summary & (1 << ce_id)) @@ -754,8 +987,11 @@ /* no intr pending on this CE */ continue; + ce_state = &ar_opaque->ce_states[ce_id]; + if (ce_state->send_cb || ce_state->recv_cb) ath10k_ce_per_engine_service(ar, ce_id); } + } /* @@ -797,22 +1033,53 @@ void ath10k_ce_enable_interrupts(struct ath10k *ar) { - struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); + struct bus_opaque *ar_opaque = ath10k_bus_priv(ar); int ce_id; + struct ath10k_ce_pipe *ce_state; + u8 ce_count; + if (QCA_REV_WCN3990(ar)) + ce_count = CE_COUNT; + else /* Skip the last copy engine, CE7 the diagnostic window, as that * uses polling and isn't initialized for interrupts. */ - for (ce_id = 0; ce_id < CE_COUNT - 1; ce_id++) - ath10k_ce_per_engine_handler_adjust(&ar_pci->ce_states[ce_id]); + ce_count = CE_COUNT - 1; + + for (ce_id = 0; ce_id < ce_count; ce_id++) { + ce_state = &ar_opaque->ce_states[ce_id]; + ath10k_ce_per_engine_handler_adjust(ce_state); + } +} + +void ath10k_ce_enable_per_ce_interrupts(struct ath10k *ar, unsigned int ce_id) +{ + u32 offset; + u32 ctrl_addr = ath10k_ce_base_address(ar, ce_id); + struct bus_opaque *ar_opaque = ath10k_bus_priv(ar); + + offset = ar->hw_ce_regs->host_ie_addr + ctrl_addr; + ar_opaque->bus_ops->write32(ar, offset, 1); + ar_opaque->bus_ops->read32(ar, offset); +} + +void ath10k_ce_disable_per_ce_interrupts(struct ath10k *ar, unsigned int ce_id) +{ + u32 offset; + u32 ctrl_addr = ath10k_ce_base_address(ar, ce_id); + struct bus_opaque *ar_opaque = ath10k_bus_priv(ar); + + offset = ar->hw_ce_regs->host_ie_addr + ctrl_addr; + ar_opaque->bus_ops->write32(ar, offset, 0); + ar_opaque->bus_ops->read32(ar, offset); } static int ath10k_ce_init_src_ring(struct ath10k *ar, unsigned int ce_id, const struct ce_attr *attr) { - struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); - struct ath10k_ce_pipe *ce_state = &ar_pci->ce_states[ce_id]; + struct bus_opaque *ar_opaque = ath10k_bus_priv(ar); + struct ath10k_ce_pipe *ce_state = &ar_opaque->ce_states[ce_id]; struct ath10k_ce_ring *src_ring = ce_state->src_ring; u32 nentries, ctrl_addr = ath10k_ce_base_address(ar, ce_id); @@ -838,7 +1105,7 @@ ath10k_ce_src_ring_highmark_set(ar, ctrl_addr, nentries); ath10k_dbg(ar, ATH10K_DBG_BOOT, - "boot init ce src ring id %d entries %d base_addr %p\n", + "boot init ce src ring id %d entries %d base_addr %pK\n", ce_id, nentries, src_ring->base_addr_owner_space); return 0; @@ -848,8 +1115,8 @@ unsigned int ce_id, const struct ce_attr *attr) { - struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); - struct ath10k_ce_pipe *ce_state = &ar_pci->ce_states[ce_id]; + struct bus_opaque *ar_opaque = ath10k_bus_priv(ar); + struct ath10k_ce_pipe *ce_state = &ar_opaque->ce_states[ce_id]; struct ath10k_ce_ring *dest_ring = ce_state->dest_ring; u32 nentries, ctrl_addr = ath10k_ce_base_address(ar, ce_id); @@ -872,7 +1139,7 @@ ath10k_ce_dest_ring_highmark_set(ar, ctrl_addr, nentries); ath10k_dbg(ar, ATH10K_DBG_BOOT, - "boot ce dest ring id %d entries %d base_addr %p\n", + "boot ce dest ring id %d entries %d base_addr %pK\n", ce_id, nentries, dest_ring->base_addr_owner_space); return 0; @@ -921,6 +1188,24 @@ src_ring->base_addr_ce_space_unaligned, CE_DESC_RING_ALIGN); + src_ring->shadow_base_unaligned = kzalloc( + nentries * sizeof(struct ce_desc), + GFP_KERNEL); + + if (!src_ring->shadow_base_unaligned) { + dma_free_coherent(ar->dev, + (nentries * sizeof(struct ce_desc) + + CE_DESC_RING_ALIGN), + src_ring->base_addr_owner_space_unaligned, + base_addr); + kfree(src_ring); + return ERR_PTR(-ENOMEM); + } + + src_ring->shadow_base = (struct ce_desc *)PTR_ALIGN( + src_ring->shadow_base_unaligned, + CE_DESC_RING_ALIGN); + return src_ring; } @@ -977,6 +1262,52 @@ return dest_ring; } +void ce_config_rri_on_ddr(struct ath10k *ar) +{ + struct bus_opaque *ar_opaque = ath10k_bus_priv(ar); + u32 hi_paddr, low_paddr; + u32 ce_base_addr; + u32 ctrl1_regs; + int i; + + ar_opaque->vaddr_rri_on_ddr = + (u32 *)dma_alloc_coherent(ar->dev, + (CE_COUNT * sizeof(u32)), + &ar_opaque->paddr_rri_on_ddr, GFP_KERNEL); + + if (!ar_opaque->vaddr_rri_on_ddr) + return; + + low_paddr = lower_32_bits(ar_opaque->paddr_rri_on_ddr); + hi_paddr = upper_32_bits(ar_opaque->paddr_rri_on_ddr) & + CE_DESC_FLAGS_GET_MASK; + + ar_opaque->bus_ops->write32(ar, ar->hw_ce_regs->ce_rri_low, low_paddr); + ar_opaque->bus_ops->write32(ar, ar->hw_ce_regs->ce_rri_high, hi_paddr); + + for (i = 0; i < CE_COUNT; i++) { + ctrl1_regs = ar->hw_ce_regs->ctrl1_regs->addr; + ce_base_addr = ath10k_ce_base_address(ar, i); + ar_opaque->bus_ops->write32(ar, ce_base_addr + ctrl1_regs, + ar_opaque->bus_ops->read32(ar, ce_base_addr + ctrl1_regs) | + ar->hw_ce_regs->upd->mask); + } + + memset(ar_opaque->vaddr_rri_on_ddr, 0, CE_COUNT * sizeof(u32)); +} + +void ce_remove_rri_on_ddr(struct ath10k *ar) +{ + struct bus_opaque *ar_opaque = ath10k_bus_priv(ar); + + if (!ar_opaque->vaddr_rri_on_ddr) + return; + + dma_free_coherent(ar->dev, (CE_COUNT * sizeof(u32)), + ar_opaque->vaddr_rri_on_ddr, + ar_opaque->paddr_rri_on_ddr); +} + /* * Initialize a Copy Engine based on caller-supplied attributes. * This may be called once to initialize both source and destination @@ -1038,8 +1369,8 @@ int ath10k_ce_alloc_pipe(struct ath10k *ar, int ce_id, const struct ce_attr *attr) { - struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); - struct ath10k_ce_pipe *ce_state = &ar_pci->ce_states[ce_id]; + struct bus_opaque *ar_opaque = ath10k_bus_priv(ar); + struct ath10k_ce_pipe *ce_state = &ar_opaque->ce_states[ce_id]; int ret; /* @@ -1095,10 +1426,11 @@ void ath10k_ce_free_pipe(struct ath10k *ar, int ce_id) { - struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); - struct ath10k_ce_pipe *ce_state = &ar_pci->ce_states[ce_id]; + struct bus_opaque *ar_opaque = ath10k_bus_priv(ar); + struct ath10k_ce_pipe *ce_state = &ar_opaque->ce_states[ce_id]; if (ce_state->src_ring) { + kfree(ce_state->src_ring->shadow_base_unaligned); dma_free_coherent(ar->dev, (ce_state->src_ring->nentries * sizeof(struct ce_desc) + diff -ruw linux-4.4.115/drivers/net/wireless/ath/ath10k/ce.h linux-4.4.115-fbx/drivers/net/wireless/ath/ath10k/ce.h --- linux-4.4.115/drivers/net/wireless/ath/ath10k/ce.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/net/wireless/ath/ath10k/ce.h 2019-01-22 16:16:25.411263685 +0100 @@ -22,7 +22,7 @@ /* Maximum number of Copy Engine's supported */ #define CE_COUNT_MAX 12 -#define CE_HTT_H2T_MSG_SRC_NENTRIES 4096 +#define CE_HTT_H2T_MSG_SRC_NENTRIES 8192 /* Descriptor rings must be aligned to this boundary */ #define CE_DESC_RING_ALIGN 8 @@ -38,6 +38,12 @@ #define CE_DESC_FLAGS_GATHER (1 << 0) #define CE_DESC_FLAGS_BYTE_SWAP (1 << 1) +#define CE_WCN3990_DESC_FLAGS_GATHER BIT(31) + +#define CE_DESC_FLAGS_GET_MASK 0x1F +#define CE_DESC_37BIT_ADDR_MASK 0x1FFFFFFFFF +#define CE_DDR_RRI_MASK 0xFFFF +#define CE_DDR_RRI_SHIFT 16 /* Following desc flags are used in QCA99X0 */ #define CE_DESC_FLAGS_HOST_INT_DIS (1 << 2) @@ -46,11 +52,20 @@ #define CE_DESC_FLAGS_META_DATA_MASK ar->hw_values->ce_desc_meta_data_mask #define CE_DESC_FLAGS_META_DATA_LSB ar->hw_values->ce_desc_meta_data_lsb +#ifndef CONFIG_ATH10K_SNOC struct ce_desc { __le32 addr; __le16 nbytes; __le16 flags; /* %CE_DESC_FLAGS_ */ }; +#else +struct ce_desc { + __le64 addr; + u16 nbytes; /* length in register map */ + u16 flags; /* fw_metadata_high */ + u32 toeplitz_hash_result; +}; +#endif struct ath10k_ce_ring { /* Number of entries in this ring; must be power of 2 */ @@ -101,6 +116,9 @@ /* CE address space */ u32 base_addr_ce_space; + char *shadow_base_unaligned; + struct ce_desc *shadow_base; + /* keep last */ void *per_transfer_context[0]; }; @@ -124,6 +142,81 @@ /* Copy Engine settable attributes */ struct ce_attr; +#define SHADOW_VALUE0 (ar->shadow_reg_value->shadow_reg_value_0) +#define SHADOW_VALUE1 (ar->shadow_reg_value->shadow_reg_value_1) +#define SHADOW_VALUE2 (ar->shadow_reg_value->shadow_reg_value_2) +#define SHADOW_VALUE3 (ar->shadow_reg_value->shadow_reg_value_3) +#define SHADOW_VALUE4 (ar->shadow_reg_value->shadow_reg_value_4) +#define SHADOW_VALUE5 (ar->shadow_reg_value->shadow_reg_value_5) +#define SHADOW_VALUE6 (ar->shadow_reg_value->shadow_reg_value_6) +#define SHADOW_VALUE7 (ar->shadow_reg_value->shadow_reg_value_7) +#define SHADOW_VALUE8 (ar->shadow_reg_value->shadow_reg_value_8) +#define SHADOW_VALUE9 (ar->shadow_reg_value->shadow_reg_value_9) +#define SHADOW_VALUE10 (ar->shadow_reg_value->shadow_reg_value_10) +#define SHADOW_VALUE11 (ar->shadow_reg_value->shadow_reg_value_11) +#define SHADOW_VALUE12 (ar->shadow_reg_value->shadow_reg_value_12) +#define SHADOW_VALUE13 (ar->shadow_reg_value->shadow_reg_value_13) +#define SHADOW_VALUE14 (ar->shadow_reg_value->shadow_reg_value_14) +#define SHADOW_VALUE15 (ar->shadow_reg_value->shadow_reg_value_15) +#define SHADOW_VALUE16 (ar->shadow_reg_value->shadow_reg_value_16) +#define SHADOW_VALUE17 (ar->shadow_reg_value->shadow_reg_value_17) +#define SHADOW_VALUE18 (ar->shadow_reg_value->shadow_reg_value_18) +#define SHADOW_VALUE19 (ar->shadow_reg_value->shadow_reg_value_19) +#define SHADOW_VALUE20 (ar->shadow_reg_value->shadow_reg_value_20) +#define SHADOW_VALUE21 (ar->shadow_reg_value->shadow_reg_value_21) +#define SHADOW_VALUE22 (ar->shadow_reg_value->shadow_reg_value_22) +#define SHADOW_VALUE23 (ar->shadow_reg_value->shadow_reg_value_23) +#define SHADOW_ADDRESS0 (ar->shadow_reg_address->shadow_reg_address_0) +#define SHADOW_ADDRESS1 (ar->shadow_reg_address->shadow_reg_address_1) +#define SHADOW_ADDRESS2 (ar->shadow_reg_address->shadow_reg_address_2) +#define SHADOW_ADDRESS3 (ar->shadow_reg_address->shadow_reg_address_3) +#define SHADOW_ADDRESS4 (ar->shadow_reg_address->shadow_reg_address_4) +#define SHADOW_ADDRESS5 (ar->shadow_reg_address->shadow_reg_address_5) +#define SHADOW_ADDRESS6 (ar->shadow_reg_address->shadow_reg_address_6) +#define SHADOW_ADDRESS7 (ar->shadow_reg_address->shadow_reg_address_7) +#define SHADOW_ADDRESS8 (ar->shadow_reg_address->shadow_reg_address_8) +#define SHADOW_ADDRESS9 (ar->shadow_reg_address->shadow_reg_address_9) +#define SHADOW_ADDRESS10 (ar->shadow_reg_address->shadow_reg_address_10) +#define SHADOW_ADDRESS11 (ar->shadow_reg_address->shadow_reg_address_11) +#define SHADOW_ADDRESS12 (ar->shadow_reg_address->shadow_reg_address_12) +#define SHADOW_ADDRESS13 (ar->shadow_reg_address->shadow_reg_address_13) +#define SHADOW_ADDRESS14 (ar->shadow_reg_address->shadow_reg_address_14) +#define SHADOW_ADDRESS15 (ar->shadow_reg_address->shadow_reg_address_15) +#define SHADOW_ADDRESS16 (ar->shadow_reg_address->shadow_reg_address_16) +#define SHADOW_ADDRESS17 (ar->shadow_reg_address->shadow_reg_address_17) +#define SHADOW_ADDRESS18 (ar->shadow_reg_address->shadow_reg_address_18) +#define SHADOW_ADDRESS19 (ar->shadow_reg_address->shadow_reg_address_19) +#define SHADOW_ADDRESS20 (ar->shadow_reg_address->shadow_reg_address_20) +#define SHADOW_ADDRESS21 (ar->shadow_reg_address->shadow_reg_address_21) +#define SHADOW_ADDRESS22 (ar->shadow_reg_address->shadow_reg_address_22) +#define SHADOW_ADDRESS23 (ar->shadow_reg_address->shadow_reg_address_23) + +#define SHADOW_ADDRESS(i) (SHADOW_ADDRESS0 + \ + i * (SHADOW_ADDRESS1 - SHADOW_ADDRESS0)) + +u32 shadow_sr_wr_ind_addr(struct ath10k *ar, u32 ctrl_addr); +u32 shadow_dst_wr_ind_addr(struct ath10k *ar, u32 ctrl_addr); + +struct ath10k_bus_ops { + u32 (*read32)(struct ath10k *ar, u32 offset); + void (*write32)(struct ath10k *ar, u32 offset, u32 value); + int (*get_num_banks)(struct ath10k *ar); +}; + +static inline struct bus_opaque *ath10k_bus_priv(struct ath10k *ar) +{ + return (struct bus_opaque *)ar->drv_priv; +} + +struct bus_opaque { + /* protects CE info */ + spinlock_t ce_lock; + const struct ath10k_bus_ops *bus_ops; + struct ath10k_ce_pipe ce_states[CE_COUNT_MAX]; + u32 *vaddr_rri_on_ddr; + dma_addr_t paddr_rri_on_ddr; +}; + /*==================Send====================*/ /* ath10k_ce_send flags */ @@ -144,7 +237,7 @@ */ int ath10k_ce_send(struct ath10k_ce_pipe *ce_state, void *per_transfer_send_context, - u32 buffer, + dma_addr_t buffer, unsigned int nbytes, /* 14 bits */ unsigned int transfer_id, @@ -152,7 +245,7 @@ int ath10k_ce_send_nolock(struct ath10k_ce_pipe *ce_state, void *per_transfer_context, - u32 buffer, + dma_addr_t buffer, unsigned int nbytes, unsigned int transfer_id, unsigned int flags); @@ -164,8 +257,11 @@ /*==================Recv=======================*/ int __ath10k_ce_rx_num_free_bufs(struct ath10k_ce_pipe *pipe); -int __ath10k_ce_rx_post_buf(struct ath10k_ce_pipe *pipe, void *ctx, u32 paddr); -int ath10k_ce_rx_post_buf(struct ath10k_ce_pipe *pipe, void *ctx, u32 paddr); +int __ath10k_ce_rx_post_buf(struct ath10k_ce_pipe *pipe, void *ctx, + dma_addr_t paddr); +int ath10k_ce_rx_post_buf(struct ath10k_ce_pipe *pipe, void *ctx, + dma_addr_t paddr); +void ath10k_ce_rx_update_write_idx(struct ath10k_ce_pipe *pipe, u32 nentries); /* recv flags */ /* Data is byte-swapped */ @@ -177,10 +273,7 @@ */ int ath10k_ce_completed_recv_next(struct ath10k_ce_pipe *ce_state, void **per_transfer_contextp, - u32 *bufferp, - unsigned int *nbytesp, - unsigned int *transfer_idp, - unsigned int *flagsp); + unsigned int *nbytesp); /* * Supply data for the next completed unprocessed send descriptor. * Pops 1 completed send buffer from Source ring. @@ -199,6 +292,8 @@ int ath10k_ce_alloc_pipe(struct ath10k *ar, int ce_id, const struct ce_attr *attr); void ath10k_ce_free_pipe(struct ath10k *ar, int ce_id); +void ce_config_rri_on_ddr(struct ath10k *ar); +void ce_remove_rri_on_ddr(struct ath10k *ar); /*==================CE Engine Shutdown=======================*/ /* @@ -212,10 +307,7 @@ int ath10k_ce_completed_recv_next_nolock(struct ath10k_ce_pipe *ce_state, void **per_transfer_contextp, - u32 *bufferp, - unsigned int *nbytesp, - unsigned int *transfer_idp, - unsigned int *flagsp); + unsigned int *nbytesp); /* * Support clean shutdown by allowing the caller to cancel @@ -233,6 +325,8 @@ void ath10k_ce_per_engine_service(struct ath10k *ar, unsigned int ce_id); int ath10k_ce_disable_interrupts(struct ath10k *ar); void ath10k_ce_enable_interrupts(struct ath10k *ar); +void ath10k_ce_disable_per_ce_interrupts(struct ath10k *ar, unsigned int ce_id); +void ath10k_ce_enable_per_ce_interrupts(struct ath10k *ar, unsigned int ce_id); /* ce_attr.flags values */ /* Use NonSnooping PCIe accesses? */ @@ -268,143 +362,14 @@ void (*recv_cb)(struct ath10k_ce_pipe *); }; -#define SR_BA_ADDRESS 0x0000 -#define SR_SIZE_ADDRESS 0x0004 -#define DR_BA_ADDRESS 0x0008 -#define DR_SIZE_ADDRESS 0x000c -#define CE_CMD_ADDRESS 0x0018 - -#define CE_CTRL1_DST_RING_BYTE_SWAP_EN_MSB 17 -#define CE_CTRL1_DST_RING_BYTE_SWAP_EN_LSB 17 -#define CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK 0x00020000 -#define CE_CTRL1_DST_RING_BYTE_SWAP_EN_SET(x) \ - (((0 | (x)) << CE_CTRL1_DST_RING_BYTE_SWAP_EN_LSB) & \ - CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK) - -#define CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MSB 16 -#define CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB 16 -#define CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK 0x00010000 -#define CE_CTRL1_SRC_RING_BYTE_SWAP_EN_GET(x) \ - (((x) & CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK) >> \ - CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB) -#define CE_CTRL1_SRC_RING_BYTE_SWAP_EN_SET(x) \ - (((0 | (x)) << CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB) & \ - CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK) - -#define CE_CTRL1_DMAX_LENGTH_MSB 15 -#define CE_CTRL1_DMAX_LENGTH_LSB 0 -#define CE_CTRL1_DMAX_LENGTH_MASK 0x0000ffff -#define CE_CTRL1_DMAX_LENGTH_GET(x) \ - (((x) & CE_CTRL1_DMAX_LENGTH_MASK) >> CE_CTRL1_DMAX_LENGTH_LSB) -#define CE_CTRL1_DMAX_LENGTH_SET(x) \ - (((0 | (x)) << CE_CTRL1_DMAX_LENGTH_LSB) & CE_CTRL1_DMAX_LENGTH_MASK) - -#define CE_CTRL1_ADDRESS 0x0010 -#define CE_CTRL1_HW_MASK 0x0007ffff -#define CE_CTRL1_SW_MASK 0x0007ffff -#define CE_CTRL1_HW_WRITE_MASK 0x00000000 -#define CE_CTRL1_SW_WRITE_MASK 0x0007ffff -#define CE_CTRL1_RSTMASK 0xffffffff -#define CE_CTRL1_RESET 0x00000080 - -#define CE_CMD_HALT_STATUS_MSB 3 -#define CE_CMD_HALT_STATUS_LSB 3 -#define CE_CMD_HALT_STATUS_MASK 0x00000008 -#define CE_CMD_HALT_STATUS_GET(x) \ - (((x) & CE_CMD_HALT_STATUS_MASK) >> CE_CMD_HALT_STATUS_LSB) -#define CE_CMD_HALT_STATUS_SET(x) \ - (((0 | (x)) << CE_CMD_HALT_STATUS_LSB) & CE_CMD_HALT_STATUS_MASK) -#define CE_CMD_HALT_STATUS_RESET 0 -#define CE_CMD_HALT_MSB 0 -#define CE_CMD_HALT_MASK 0x00000001 - -#define HOST_IE_COPY_COMPLETE_MSB 0 -#define HOST_IE_COPY_COMPLETE_LSB 0 -#define HOST_IE_COPY_COMPLETE_MASK 0x00000001 -#define HOST_IE_COPY_COMPLETE_GET(x) \ - (((x) & HOST_IE_COPY_COMPLETE_MASK) >> HOST_IE_COPY_COMPLETE_LSB) -#define HOST_IE_COPY_COMPLETE_SET(x) \ - (((0 | (x)) << HOST_IE_COPY_COMPLETE_LSB) & HOST_IE_COPY_COMPLETE_MASK) -#define HOST_IE_COPY_COMPLETE_RESET 0 -#define HOST_IE_ADDRESS 0x002c - -#define HOST_IS_DST_RING_LOW_WATERMARK_MASK 0x00000010 -#define HOST_IS_DST_RING_HIGH_WATERMARK_MASK 0x00000008 -#define HOST_IS_SRC_RING_LOW_WATERMARK_MASK 0x00000004 -#define HOST_IS_SRC_RING_HIGH_WATERMARK_MASK 0x00000002 -#define HOST_IS_COPY_COMPLETE_MASK 0x00000001 -#define HOST_IS_ADDRESS 0x0030 - -#define MISC_IE_ADDRESS 0x0034 - -#define MISC_IS_AXI_ERR_MASK 0x00000400 - -#define MISC_IS_DST_ADDR_ERR_MASK 0x00000200 -#define MISC_IS_SRC_LEN_ERR_MASK 0x00000100 -#define MISC_IS_DST_MAX_LEN_VIO_MASK 0x00000080 -#define MISC_IS_DST_RING_OVERFLOW_MASK 0x00000040 -#define MISC_IS_SRC_RING_OVERFLOW_MASK 0x00000020 - -#define MISC_IS_ADDRESS 0x0038 - -#define SR_WR_INDEX_ADDRESS 0x003c - -#define DST_WR_INDEX_ADDRESS 0x0040 - -#define CURRENT_SRRI_ADDRESS 0x0044 - -#define CURRENT_DRRI_ADDRESS 0x0048 - -#define SRC_WATERMARK_LOW_MSB 31 -#define SRC_WATERMARK_LOW_LSB 16 -#define SRC_WATERMARK_LOW_MASK 0xffff0000 -#define SRC_WATERMARK_LOW_GET(x) \ - (((x) & SRC_WATERMARK_LOW_MASK) >> SRC_WATERMARK_LOW_LSB) -#define SRC_WATERMARK_LOW_SET(x) \ - (((0 | (x)) << SRC_WATERMARK_LOW_LSB) & SRC_WATERMARK_LOW_MASK) -#define SRC_WATERMARK_LOW_RESET 0 -#define SRC_WATERMARK_HIGH_MSB 15 -#define SRC_WATERMARK_HIGH_LSB 0 -#define SRC_WATERMARK_HIGH_MASK 0x0000ffff -#define SRC_WATERMARK_HIGH_GET(x) \ - (((x) & SRC_WATERMARK_HIGH_MASK) >> SRC_WATERMARK_HIGH_LSB) -#define SRC_WATERMARK_HIGH_SET(x) \ - (((0 | (x)) << SRC_WATERMARK_HIGH_LSB) & SRC_WATERMARK_HIGH_MASK) -#define SRC_WATERMARK_HIGH_RESET 0 -#define SRC_WATERMARK_ADDRESS 0x004c - -#define DST_WATERMARK_LOW_LSB 16 -#define DST_WATERMARK_LOW_MASK 0xffff0000 -#define DST_WATERMARK_LOW_SET(x) \ - (((0 | (x)) << DST_WATERMARK_LOW_LSB) & DST_WATERMARK_LOW_MASK) -#define DST_WATERMARK_LOW_RESET 0 -#define DST_WATERMARK_HIGH_MSB 15 -#define DST_WATERMARK_HIGH_LSB 0 -#define DST_WATERMARK_HIGH_MASK 0x0000ffff -#define DST_WATERMARK_HIGH_GET(x) \ - (((x) & DST_WATERMARK_HIGH_MASK) >> DST_WATERMARK_HIGH_LSB) -#define DST_WATERMARK_HIGH_SET(x) \ - (((0 | (x)) << DST_WATERMARK_HIGH_LSB) & DST_WATERMARK_HIGH_MASK) -#define DST_WATERMARK_HIGH_RESET 0 -#define DST_WATERMARK_ADDRESS 0x0050 +#define COPY_ENGINE_ID(COPY_ENGINE_BASE_ADDRESS) ((COPY_ENGINE_BASE_ADDRESS \ + - CE0_BASE_ADDRESS) / (CE1_BASE_ADDRESS - CE0_BASE_ADDRESS)) static inline u32 ath10k_ce_base_address(struct ath10k *ar, unsigned int ce_id) { return CE0_BASE_ADDRESS + (CE1_BASE_ADDRESS - CE0_BASE_ADDRESS) * ce_id; } -#define CE_WATERMARK_MASK (HOST_IS_SRC_RING_LOW_WATERMARK_MASK | \ - HOST_IS_SRC_RING_HIGH_WATERMARK_MASK | \ - HOST_IS_DST_RING_LOW_WATERMARK_MASK | \ - HOST_IS_DST_RING_HIGH_WATERMARK_MASK) - -#define CE_ERROR_MASK (MISC_IS_AXI_ERR_MASK | \ - MISC_IS_DST_ADDR_ERR_MASK | \ - MISC_IS_SRC_LEN_ERR_MASK | \ - MISC_IS_DST_MAX_LEN_VIO_MASK | \ - MISC_IS_DST_RING_OVERFLOW_MASK | \ - MISC_IS_SRC_RING_OVERFLOW_MASK) - #define CE_SRC_RING_TO_DESC(baddr, idx) \ (&(((struct ce_desc *)baddr)[idx])) @@ -416,6 +381,8 @@ (((int)(toidx)-(int)(fromidx)) & (nentries_mask)) #define CE_RING_IDX_INCR(nentries_mask, idx) (((idx) + 1) & (nentries_mask)) +#define CE_RING_IDX_ADD(nentries_mask, idx, num) \ + (((idx) + (num)) & (nentries_mask)) #define CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB \ ar->regs->ce_wrap_intr_sum_host_msi_lsb @@ -426,9 +393,9 @@ CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB) #define CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS 0x0000 -#define CE_INTERRUPT_SUMMARY(ar) \ +#define CE_INTERRUPT_SUMMARY(ar, ar_opaque) \ CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_GET( \ - ath10k_pci_read32((ar), CE_WRAPPER_BASE_ADDRESS + \ + ar_opaque->bus_ops->read32((ar), CE_WRAPPER_BASE_ADDRESS + \ CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS)) #endif /* _CE_H_ */ diff -ruw linux-4.4.115/drivers/net/wireless/ath/ath10k/core.c linux-4.4.115-fbx/drivers/net/wireless/ath/ath10k/core.c --- linux-4.4.115/drivers/net/wireless/ath/ath10k/core.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/net/wireless/ath/ath10k/core.c 2019-01-22 16:16:25.415263721 +0100 @@ -1,6 +1,6 @@ /* * Copyright (c) 2005-2011 Atheros Communications Inc. - * Copyright (c) 2011-2013 Qualcomm Atheros, Inc. + * Copyright (c) 2011-2013, 2017 Qualcomm Atheros, Inc. * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above @@ -18,6 +18,7 @@ #include #include #include +#include #include "core.h" #include "mac.h" @@ -55,18 +56,39 @@ .name = "qca988x hw2.0", .patch_load_addr = QCA988X_HW_2_0_PATCH_LOAD_ADDR, .uart_pin = 7, - .has_shifted_cc_wraparound = true, + .cc_wraparound_type = ATH10K_HW_CC_WRAP_SHIFTED_ALL, .otp_exe_param = 0, .channel_counters_freq_hz = 88000, .max_probe_resp_desc_thres = 0, + .cal_data_len = 2116, .fw = { .dir = QCA988X_HW_2_0_FW_DIR, - .fw = QCA988X_HW_2_0_FW_FILE, - .otp = QCA988X_HW_2_0_OTP_FILE, .board = QCA988X_HW_2_0_BOARD_DATA_FILE, .board_size = QCA988X_BOARD_DATA_SZ, .board_ext_size = QCA988X_BOARD_EXT_DATA_SZ, }, + .hw_ops = &qca988x_ops, + .decap_align_bytes = 4, + }, + { + .id = QCA9887_HW_1_0_VERSION, + .dev_id = QCA9887_1_0_DEVICE_ID, + .name = "qca9887 hw1.0", + .patch_load_addr = QCA9887_HW_1_0_PATCH_LOAD_ADDR, + .uart_pin = 7, + .cc_wraparound_type = ATH10K_HW_CC_WRAP_SHIFTED_ALL, + .otp_exe_param = 0, + .channel_counters_freq_hz = 88000, + .max_probe_resp_desc_thres = 0, + .cal_data_len = 2116, + .fw = { + .dir = QCA9887_HW_1_0_FW_DIR, + .board = QCA9887_HW_1_0_BOARD_DATA_FILE, + .board_size = QCA9887_BOARD_DATA_SZ, + .board_ext_size = QCA9887_BOARD_EXT_DATA_SZ, + }, + .hw_ops = &qca988x_ops, + .decap_align_bytes = 4, }, { .id = QCA6174_HW_2_1_VERSION, @@ -77,14 +99,15 @@ .otp_exe_param = 0, .channel_counters_freq_hz = 88000, .max_probe_resp_desc_thres = 0, + .cal_data_len = 8124, .fw = { .dir = QCA6174_HW_2_1_FW_DIR, - .fw = QCA6174_HW_2_1_FW_FILE, - .otp = QCA6174_HW_2_1_OTP_FILE, .board = QCA6174_HW_2_1_BOARD_DATA_FILE, .board_size = QCA6174_BOARD_DATA_SZ, .board_ext_size = QCA6174_BOARD_EXT_DATA_SZ, }, + .hw_ops = &qca988x_ops, + .decap_align_bytes = 4, }, { .id = QCA6174_HW_2_1_VERSION, @@ -95,14 +118,15 @@ .otp_exe_param = 0, .channel_counters_freq_hz = 88000, .max_probe_resp_desc_thres = 0, + .cal_data_len = 8124, .fw = { .dir = QCA6174_HW_2_1_FW_DIR, - .fw = QCA6174_HW_2_1_FW_FILE, - .otp = QCA6174_HW_2_1_OTP_FILE, .board = QCA6174_HW_2_1_BOARD_DATA_FILE, .board_size = QCA6174_BOARD_DATA_SZ, .board_ext_size = QCA6174_BOARD_EXT_DATA_SZ, }, + .hw_ops = &qca988x_ops, + .decap_align_bytes = 4, }, { .id = QCA6174_HW_3_0_VERSION, @@ -113,14 +137,15 @@ .otp_exe_param = 0, .channel_counters_freq_hz = 88000, .max_probe_resp_desc_thres = 0, + .cal_data_len = 8124, .fw = { .dir = QCA6174_HW_3_0_FW_DIR, - .fw = QCA6174_HW_3_0_FW_FILE, - .otp = QCA6174_HW_3_0_OTP_FILE, .board = QCA6174_HW_3_0_BOARD_DATA_FILE, .board_size = QCA6174_BOARD_DATA_SZ, .board_ext_size = QCA6174_BOARD_EXT_DATA_SZ, }, + .hw_ops = &qca988x_ops, + .decap_align_bytes = 4, }, { .id = QCA6174_HW_3_2_VERSION, @@ -131,15 +156,16 @@ .otp_exe_param = 0, .channel_counters_freq_hz = 88000, .max_probe_resp_desc_thres = 0, + .cal_data_len = 8124, .fw = { /* uses same binaries as hw3.0 */ .dir = QCA6174_HW_3_0_FW_DIR, - .fw = QCA6174_HW_3_0_FW_FILE, - .otp = QCA6174_HW_3_0_OTP_FILE, .board = QCA6174_HW_3_0_BOARD_DATA_FILE, .board_size = QCA6174_BOARD_DATA_SZ, .board_ext_size = QCA6174_BOARD_EXT_DATA_SZ, }, + .hw_ops = &qca988x_ops, + .decap_align_bytes = 4, }, { .id = QCA99X0_HW_2_0_DEV_VERSION, @@ -149,16 +175,71 @@ .uart_pin = 7, .otp_exe_param = 0x00000700, .continuous_frag_desc = true, + .cck_rate_map_rev2 = true, .channel_counters_freq_hz = 150000, .max_probe_resp_desc_thres = 24, + .tx_chain_mask = 0xf, + .rx_chain_mask = 0xf, + .max_spatial_stream = 4, + .cal_data_len = 12064, .fw = { .dir = QCA99X0_HW_2_0_FW_DIR, - .fw = QCA99X0_HW_2_0_FW_FILE, - .otp = QCA99X0_HW_2_0_OTP_FILE, .board = QCA99X0_HW_2_0_BOARD_DATA_FILE, .board_size = QCA99X0_BOARD_DATA_SZ, .board_ext_size = QCA99X0_BOARD_EXT_DATA_SZ, }, + .sw_decrypt_mcast_mgmt = true, + .hw_ops = &qca99x0_ops, + .decap_align_bytes = 1, + }, + { + .id = QCA9984_HW_1_0_DEV_VERSION, + .dev_id = QCA9984_1_0_DEVICE_ID, + .name = "qca9984/qca9994 hw1.0", + .patch_load_addr = QCA9984_HW_1_0_PATCH_LOAD_ADDR, + .uart_pin = 7, + .otp_exe_param = 0x00000700, + .continuous_frag_desc = true, + .cck_rate_map_rev2 = true, + .channel_counters_freq_hz = 150000, + .max_probe_resp_desc_thres = 24, + .tx_chain_mask = 0xf, + .rx_chain_mask = 0xf, + .max_spatial_stream = 4, + .cal_data_len = 12064, + .fw = { + .dir = QCA9984_HW_1_0_FW_DIR, + .board = QCA9984_HW_1_0_BOARD_DATA_FILE, + .board_size = QCA99X0_BOARD_DATA_SZ, + .board_ext_size = QCA99X0_BOARD_EXT_DATA_SZ, + }, + .sw_decrypt_mcast_mgmt = true, + .hw_ops = &qca99x0_ops, + .decap_align_bytes = 1, + }, + { + .id = QCA9888_HW_2_0_DEV_VERSION, + .dev_id = QCA9888_2_0_DEVICE_ID, + .name = "qca9888 hw2.0", + .patch_load_addr = QCA9888_HW_2_0_PATCH_LOAD_ADDR, + .uart_pin = 7, + .otp_exe_param = 0x00000700, + .continuous_frag_desc = true, + .channel_counters_freq_hz = 150000, + .max_probe_resp_desc_thres = 24, + .tx_chain_mask = 3, + .rx_chain_mask = 3, + .max_spatial_stream = 2, + .cal_data_len = 12064, + .fw = { + .dir = QCA9888_HW_2_0_FW_DIR, + .board = QCA9888_HW_2_0_BOARD_DATA_FILE, + .board_size = QCA99X0_BOARD_DATA_SZ, + .board_ext_size = QCA99X0_BOARD_EXT_DATA_SZ, + }, + .sw_decrypt_mcast_mgmt = true, + .hw_ops = &qca99x0_ops, + .decap_align_bytes = 1, }, { .id = QCA9377_HW_1_0_DEV_VERSION, @@ -169,14 +250,15 @@ .otp_exe_param = 0, .channel_counters_freq_hz = 88000, .max_probe_resp_desc_thres = 0, + .cal_data_len = 8124, .fw = { .dir = QCA9377_HW_1_0_FW_DIR, - .fw = QCA9377_HW_1_0_FW_FILE, - .otp = QCA9377_HW_1_0_OTP_FILE, .board = QCA9377_HW_1_0_BOARD_DATA_FILE, .board_size = QCA9377_BOARD_DATA_SZ, .board_ext_size = QCA9377_BOARD_EXT_DATA_SZ, }, + .hw_ops = &qca988x_ops, + .decap_align_bytes = 4, }, { .id = QCA9377_HW_1_1_DEV_VERSION, @@ -187,14 +269,56 @@ .otp_exe_param = 0, .channel_counters_freq_hz = 88000, .max_probe_resp_desc_thres = 0, + .cal_data_len = 8124, .fw = { .dir = QCA9377_HW_1_0_FW_DIR, - .fw = QCA9377_HW_1_0_FW_FILE, - .otp = QCA9377_HW_1_0_OTP_FILE, .board = QCA9377_HW_1_0_BOARD_DATA_FILE, .board_size = QCA9377_BOARD_DATA_SZ, .board_ext_size = QCA9377_BOARD_EXT_DATA_SZ, }, + .hw_ops = &qca988x_ops, + .decap_align_bytes = 4, + }, + { + .id = QCA4019_HW_1_0_DEV_VERSION, + .dev_id = 0, + .name = "qca4019 hw1.0", + .patch_load_addr = QCA4019_HW_1_0_PATCH_LOAD_ADDR, + .uart_pin = 7, + .cc_wraparound_type = ATH10K_HW_CC_WRAP_SHIFTED_EACH, + .otp_exe_param = 0x0010000, + .continuous_frag_desc = true, + .cck_rate_map_rev2 = true, + .channel_counters_freq_hz = 125000, + .max_probe_resp_desc_thres = 24, + .tx_chain_mask = 0x3, + .rx_chain_mask = 0x3, + .max_spatial_stream = 2, + .cal_data_len = 12064, + .fw = { + .dir = QCA4019_HW_1_0_FW_DIR, + .board = QCA4019_HW_1_0_BOARD_DATA_FILE, + .board_size = QCA4019_BOARD_DATA_SZ, + .board_ext_size = QCA4019_BOARD_EXT_DATA_SZ, + }, + .sw_decrypt_mcast_mgmt = true, + .hw_ops = &qca99x0_ops, + .decap_align_bytes = 1, + }, + { + .id = ATH10K_HW_WCN3990, + .dev_id = 0, + .name = "wcn3990 hw1.0", + .continuous_frag_desc = true, + .tx_chain_mask = 0x7, + .rx_chain_mask = 0x7, + .max_spatial_stream = 4, + .fw = { + .dir = WCN3990_HW_1_0_FW_DIR, + }, + .sw_decrypt_mcast_mgmt = true, + .hw_ops = &wcn3990_ops, + .decap_align_bytes = 1, }, }; @@ -211,6 +335,10 @@ [ATH10K_FW_FEATURE_SUPPORTS_SKIP_CLOCK_INIT] = "skip-clock-init", [ATH10K_FW_FEATURE_RAW_MODE_SUPPORT] = "raw-mode", [ATH10K_FW_FEATURE_SUPPORTS_ADAPTIVE_CCA] = "adaptive-cca", + [ATH10K_FW_FEATURE_MFP_SUPPORT] = "mfp", + [ATH10K_FW_FEATURE_PEER_FLOW_CONTROL] = "peer-flow-ctrl", + [ATH10K_FW_FEATURE_BTCOEX_PARAM] = "btcoex-param", + [ATH10K_FW_FEATURE_SKIP_NULL_FUNC_WAR] = "skip-null-func-war", }; static unsigned int ath10k_core_get_fw_feature_str(char *buf, @@ -237,7 +365,7 @@ int i; for (i = 0; i < ATH10K_FW_FEATURE_COUNT; i++) { - if (test_bit(i, ar->fw_features)) { + if (test_bit(i, ar->normal_mode_fw.fw_file.fw_features)) { if (len > 0) len += scnprintf(buf + len, buf_len - len, ","); @@ -429,18 +557,18 @@ return ret; } -static int ath10k_download_cal_file(struct ath10k *ar) +static int ath10k_download_cal_file(struct ath10k *ar, + const struct firmware *file) { int ret; - if (!ar->cal_file) + if (!file) return -ENOENT; - if (IS_ERR(ar->cal_file)) - return PTR_ERR(ar->cal_file); + if (IS_ERR(file)) + return PTR_ERR(file); - ret = ath10k_download_board_data(ar, ar->cal_file->data, - ar->cal_file->size); + ret = ath10k_download_board_data(ar, file->data, file->size); if (ret) { ath10k_err(ar, "failed to download cal_file data: %d\n", ret); return ret; @@ -451,7 +579,7 @@ return 0; } -static int ath10k_download_cal_dt(struct ath10k *ar) +static int ath10k_download_cal_dt(struct ath10k *ar, const char *dt_name) { struct device_node *node; int data_len; @@ -465,13 +593,12 @@ */ return -ENOENT; - if (!of_get_property(node, "qcom,ath10k-calibration-data", - &data_len)) { + if (!of_get_property(node, dt_name, &data_len)) { /* The calibration data node is optional */ return -ENOENT; } - if (data_len != QCA988X_CAL_DATA_LEN) { + if (data_len != ar->hw_params.cal_data_len) { ath10k_warn(ar, "invalid calibration data length in DT: %d\n", data_len); ret = -EMSGSIZE; @@ -484,8 +611,7 @@ goto out; } - ret = of_property_read_u8_array(node, "qcom,ath10k-calibration-data", - data, data_len); + ret = of_property_read_u8_array(node, dt_name, data, data_len); if (ret) { ath10k_warn(ar, "failed to read calibration data from DT: %d\n", ret); @@ -508,6 +634,35 @@ return ret; } +static int ath10k_download_cal_eeprom(struct ath10k *ar) +{ + size_t data_len; + void *data = NULL; + int ret; + + ret = ath10k_hif_fetch_cal_eeprom(ar, &data, &data_len); + if (ret) { + if (ret != -EOPNOTSUPP) + ath10k_warn(ar, "failed to read calibration data from EEPROM: %d\n", + ret); + goto out_free; + } + + ret = ath10k_download_board_data(ar, data, data_len); + if (ret) { + ath10k_warn(ar, "failed to download calibration data from EEPROM: %d\n", + ret); + goto out_free; + } + + ret = 0; + +out_free: + kfree(data); + + return ret; +} + static int ath10k_core_get_board_id_from_otp(struct ath10k *ar) { u32 result, address; @@ -516,7 +671,8 @@ address = ar->hw_params.patch_load_addr; - if (!ar->otp_data || !ar->otp_len) { + if (!ar->normal_mode_fw.fw_file.otp_data || + !ar->normal_mode_fw.fw_file.otp_len) { ath10k_warn(ar, "failed to retrieve board id because of invalid otp\n"); return -ENODATA; @@ -524,9 +680,11 @@ ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot upload otp to 0x%x len %zd for board id\n", - address, ar->otp_len); + address, ar->normal_mode_fw.fw_file.otp_len); - ret = ath10k_bmi_fast_download(ar, address, ar->otp_data, ar->otp_len); + ret = ath10k_bmi_fast_download(ar, address, + ar->normal_mode_fw.fw_file.otp_data, + ar->normal_mode_fw.fw_file.otp_len); if (ret) { ath10k_err(ar, "could not write otp for board id check: %d\n", ret); @@ -567,7 +725,9 @@ u32 bmi_otp_exe_param = ar->hw_params.otp_exe_param; int ret; - ret = ath10k_download_board_data(ar, ar->board_data, ar->board_len); + ret = ath10k_download_board_data(ar, + ar->running_fw->board_data, + ar->running_fw->board_len); if (ret) { ath10k_err(ar, "failed to download board data: %d\n", ret); return ret; @@ -575,16 +735,20 @@ /* OTP is optional */ - if (!ar->otp_data || !ar->otp_len) { - ath10k_warn(ar, "Not running otp, calibration will be incorrect (otp-data %p otp_len %zd)!\n", - ar->otp_data, ar->otp_len); + if (!ar->running_fw->fw_file.otp_data || + !ar->running_fw->fw_file.otp_len) { + ath10k_warn(ar, "Not running otp, calibration will be incorrect (otp-data %pK otp_len %zd)!\n", + ar->running_fw->fw_file.otp_data, + ar->running_fw->fw_file.otp_len); return 0; } ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot upload otp to 0x%x len %zd\n", - address, ar->otp_len); + address, ar->running_fw->fw_file.otp_len); - ret = ath10k_bmi_fast_download(ar, address, ar->otp_data, ar->otp_len); + ret = ath10k_bmi_fast_download(ar, address, + ar->running_fw->fw_file.otp_data, + ar->running_fw->fw_file.otp_len); if (ret) { ath10k_err(ar, "could not write otp (%d)\n", ret); return ret; @@ -599,7 +763,7 @@ ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot otp execute result %d\n", result); if (!(skip_otp || test_bit(ATH10K_FW_FEATURE_IGNORE_OTP_RESULT, - ar->fw_features)) && + ar->running_fw->fw_file.fw_features)) && result != 0) { ath10k_err(ar, "otp calibration failed: %d", result); return -EINVAL; @@ -608,46 +772,32 @@ return 0; } -static int ath10k_download_fw(struct ath10k *ar, enum ath10k_firmware_mode mode) +static int ath10k_download_fw(struct ath10k *ar) { u32 address, data_len; - const char *mode_name; const void *data; int ret; address = ar->hw_params.patch_load_addr; - switch (mode) { - case ATH10K_FIRMWARE_MODE_NORMAL: - data = ar->firmware_data; - data_len = ar->firmware_len; - mode_name = "normal"; - ret = ath10k_swap_code_seg_configure(ar, - ATH10K_SWAP_CODE_SEG_BIN_TYPE_FW); + data = ar->running_fw->fw_file.firmware_data; + data_len = ar->running_fw->fw_file.firmware_len; + + ret = ath10k_swap_code_seg_configure(ar, &ar->running_fw->fw_file); if (ret) { ath10k_err(ar, "failed to configure fw code swap: %d\n", ret); return ret; } - break; - case ATH10K_FIRMWARE_MODE_UTF: - data = ar->testmode.utf_firmware_data; - data_len = ar->testmode.utf_firmware_len; - mode_name = "utf"; - break; - default: - ath10k_err(ar, "unknown firmware mode: %d\n", mode); - return -EINVAL; - } ath10k_dbg(ar, ATH10K_DBG_BOOT, - "boot uploading firmware image %p len %d mode %s\n", - data, data_len, mode_name); + "boot uploading firmware image %pK len %d\n", + data, data_len); ret = ath10k_bmi_fast_download(ar, address, data, data_len); if (ret) { - ath10k_err(ar, "failed to download %s firmware: %d\n", - mode_name, ret); + ath10k_err(ar, "failed to download firmware: %d\n", + ret); return ret; } @@ -656,42 +806,50 @@ static void ath10k_core_free_board_files(struct ath10k *ar) { - if (!IS_ERR(ar->board)) - release_firmware(ar->board); + if (!IS_ERR(ar->normal_mode_fw.board)) + release_firmware(ar->normal_mode_fw.board); - ar->board = NULL; - ar->board_data = NULL; - ar->board_len = 0; + ar->normal_mode_fw.board = NULL; + ar->normal_mode_fw.board_data = NULL; + ar->normal_mode_fw.board_len = 0; } static void ath10k_core_free_firmware_files(struct ath10k *ar) { - if (!IS_ERR(ar->otp)) - release_firmware(ar->otp); - - if (!IS_ERR(ar->firmware)) - release_firmware(ar->firmware); + if (!IS_ERR(ar->normal_mode_fw.fw_file.firmware)) + release_firmware(ar->normal_mode_fw.fw_file.firmware); if (!IS_ERR(ar->cal_file)) release_firmware(ar->cal_file); - ath10k_swap_code_seg_release(ar); + if (!IS_ERR(ar->pre_cal_file)) + release_firmware(ar->pre_cal_file); - ar->otp = NULL; - ar->otp_data = NULL; - ar->otp_len = 0; - - ar->firmware = NULL; - ar->firmware_data = NULL; - ar->firmware_len = 0; + ath10k_swap_code_seg_release(ar, &ar->normal_mode_fw.fw_file); + + ar->normal_mode_fw.fw_file.otp_data = NULL; + ar->normal_mode_fw.fw_file.otp_len = 0; + + ar->normal_mode_fw.fw_file.firmware = NULL; + ar->normal_mode_fw.fw_file.firmware_data = NULL; + ar->normal_mode_fw.fw_file.firmware_len = 0; ar->cal_file = NULL; + ar->pre_cal_file = NULL; } static int ath10k_fetch_cal_file(struct ath10k *ar) { char filename[100]; + /* pre-cal--.bin */ + scnprintf(filename, sizeof(filename), "pre-cal-%s-%s.bin", + ath10k_bus_str(ar->hif.bus), dev_name(ar->dev)); + + ar->pre_cal_file = ath10k_fetch_fw_file(ar, ATH10K_FW_DIR, filename); + if (!IS_ERR(ar->pre_cal_file)) + goto success; + /* cal--.bin */ scnprintf(filename, sizeof(filename), "cal-%s-%s.bin", ath10k_bus_str(ar->hif.bus), dev_name(ar->dev)); @@ -700,7 +858,7 @@ if (IS_ERR(ar->cal_file)) /* calibration file is optional, don't print any warnings */ return PTR_ERR(ar->cal_file); - +success: ath10k_dbg(ar, ATH10K_DBG_BOOT, "found calibration file %s/%s\n", ATH10K_FW_DIR, filename); @@ -714,14 +872,14 @@ return -EINVAL; } - ar->board = ath10k_fetch_fw_file(ar, + ar->normal_mode_fw.board = ath10k_fetch_fw_file(ar, ar->hw_params.fw.dir, ar->hw_params.fw.board); - if (IS_ERR(ar->board)) - return PTR_ERR(ar->board); + if (IS_ERR(ar->normal_mode_fw.board)) + return PTR_ERR(ar->normal_mode_fw.board); - ar->board_data = ar->board->data; - ar->board_len = ar->board->size; + ar->normal_mode_fw.board_data = ar->normal_mode_fw.board->data; + ar->normal_mode_fw.board_len = ar->normal_mode_fw.board->size; return 0; } @@ -781,8 +939,8 @@ "boot found board data for '%s'", boardname); - ar->board_data = board_ie_data; - ar->board_len = board_ie_len; + ar->normal_mode_fw.board_data = board_ie_data; + ar->normal_mode_fw.board_len = board_ie_len; ret = 0; goto out; @@ -815,12 +973,14 @@ const u8 *data; int ret, ie_id; - ar->board = ath10k_fetch_fw_file(ar, ar->hw_params.fw.dir, filename); - if (IS_ERR(ar->board)) - return PTR_ERR(ar->board); + ar->normal_mode_fw.board = ath10k_fetch_fw_file(ar, + ar->hw_params.fw.dir, + filename); + if (IS_ERR(ar->normal_mode_fw.board)) + return PTR_ERR(ar->normal_mode_fw.board); - data = ar->board->data; - len = ar->board->size; + data = ar->normal_mode_fw.board->data; + len = ar->normal_mode_fw.board->size; /* magic has extra null byte padded */ magic_len = strlen(ATH10K_BOARD_MAGIC) + 1; @@ -887,10 +1047,10 @@ } out: - if (!ar->board_data || !ar->board_len) { + if (!ar->normal_mode_fw.board_data || !ar->normal_mode_fw.board_len) { ath10k_err(ar, "failed to fetch board data for %s from %s/%s\n", - ar->hw_params.fw.dir, boardname, filename); + boardname, ar->hw_params.fw.dir, filename); ret = -ENODATA; goto err; } @@ -955,51 +1115,8 @@ return 0; } -static int ath10k_core_fetch_firmware_api_1(struct ath10k *ar) -{ - int ret = 0; - - if (ar->hw_params.fw.fw == NULL) { - ath10k_err(ar, "firmware file not defined\n"); - return -EINVAL; - } - - ar->firmware = ath10k_fetch_fw_file(ar, - ar->hw_params.fw.dir, - ar->hw_params.fw.fw); - if (IS_ERR(ar->firmware)) { - ret = PTR_ERR(ar->firmware); - ath10k_err(ar, "could not fetch firmware (%d)\n", ret); - goto err; - } - - ar->firmware_data = ar->firmware->data; - ar->firmware_len = ar->firmware->size; - - /* OTP may be undefined. If so, don't fetch it at all */ - if (ar->hw_params.fw.otp == NULL) - return 0; - - ar->otp = ath10k_fetch_fw_file(ar, - ar->hw_params.fw.dir, - ar->hw_params.fw.otp); - if (IS_ERR(ar->otp)) { - ret = PTR_ERR(ar->otp); - ath10k_err(ar, "could not fetch otp (%d)\n", ret); - goto err; - } - - ar->otp_data = ar->otp->data; - ar->otp_len = ar->otp->size; - - return 0; - -err: - ath10k_core_free_firmware_files(ar); - return ret; -} - -static int ath10k_core_fetch_firmware_api_n(struct ath10k *ar, const char *name) +int ath10k_core_fetch_firmware_api_n(struct ath10k *ar, const char *name, + struct ath10k_fw_file *fw_file) { size_t magic_len, len, ie_len; int ie_id, i, index, bit, ret; @@ -1008,15 +1125,17 @@ __le32 *timestamp, *version; /* first fetch the firmware file (firmware-*.bin) */ - ar->firmware = ath10k_fetch_fw_file(ar, ar->hw_params.fw.dir, name); - if (IS_ERR(ar->firmware)) { + fw_file->firmware = ath10k_fetch_fw_file(ar, ar->hw_params.fw.dir, + name); + if (IS_ERR(fw_file->firmware)) { ath10k_err(ar, "could not fetch firmware file '%s/%s': %ld\n", - ar->hw_params.fw.dir, name, PTR_ERR(ar->firmware)); - return PTR_ERR(ar->firmware); + ar->hw_params.fw.dir, name, + PTR_ERR(fw_file->firmware)); + return PTR_ERR(fw_file->firmware); } - data = ar->firmware->data; - len = ar->firmware->size; + data = fw_file->firmware->data; + len = fw_file->firmware->size; /* magic also includes the null byte, check that as well */ magic_len = strlen(ATH10K_FIRMWARE_MAGIC) + 1; @@ -1059,15 +1178,15 @@ switch (ie_id) { case ATH10K_FW_IE_FW_VERSION: - if (ie_len > sizeof(ar->hw->wiphy->fw_version) - 1) + if (ie_len > sizeof(fw_file->fw_version) - 1) break; - memcpy(ar->hw->wiphy->fw_version, data, ie_len); - ar->hw->wiphy->fw_version[ie_len] = '\0'; + memcpy(fw_file->fw_version, data, ie_len); + fw_file->fw_version[ie_len] = '\0'; ath10k_dbg(ar, ATH10K_DBG_BOOT, "found fw version %s\n", - ar->hw->wiphy->fw_version); + fw_file->fw_version); break; case ATH10K_FW_IE_TIMESTAMP: if (ie_len != sizeof(u32)) @@ -1094,21 +1213,21 @@ ath10k_dbg(ar, ATH10K_DBG_BOOT, "Enabling feature bit: %i\n", i); - __set_bit(i, ar->fw_features); + __set_bit(i, fw_file->fw_features); } } ath10k_dbg_dump(ar, ATH10K_DBG_BOOT, "features", "", - ar->fw_features, - sizeof(ar->fw_features)); + fw_file->fw_features, + sizeof(fw_file->fw_features)); break; case ATH10K_FW_IE_FW_IMAGE: ath10k_dbg(ar, ATH10K_DBG_BOOT, "found fw image ie (%zd B)\n", ie_len); - ar->firmware_data = data; - ar->firmware_len = ie_len; + fw_file->firmware_data = data; + fw_file->firmware_len = ie_len; break; case ATH10K_FW_IE_OTP_IMAGE: @@ -1116,8 +1235,8 @@ "found otp image ie (%zd B)\n", ie_len); - ar->otp_data = data; - ar->otp_len = ie_len; + fw_file->otp_data = data; + fw_file->otp_len = ie_len; break; case ATH10K_FW_IE_WMI_OP_VERSION: @@ -1126,10 +1245,10 @@ version = (__le32 *)data; - ar->wmi.op_version = le32_to_cpup(version); + fw_file->wmi_op_version = le32_to_cpup(version); ath10k_dbg(ar, ATH10K_DBG_BOOT, "found fw ie wmi op version %d\n", - ar->wmi.op_version); + fw_file->wmi_op_version); break; case ATH10K_FW_IE_HTT_OP_VERSION: if (ie_len != sizeof(u32)) @@ -1137,17 +1256,17 @@ version = (__le32 *)data; - ar->htt.op_version = le32_to_cpup(version); + fw_file->htt_op_version = le32_to_cpup(version); ath10k_dbg(ar, ATH10K_DBG_BOOT, "found fw ie htt op version %d\n", - ar->htt.op_version); + fw_file->htt_op_version); break; case ATH10K_FW_IE_FW_CODE_SWAP_IMAGE: ath10k_dbg(ar, ATH10K_DBG_BOOT, "found fw code swap image ie (%zd B)\n", ie_len); - ar->swap.firmware_codeswap_data = data; - ar->swap.firmware_codeswap_len = ie_len; + fw_file->codeswap_data = data; + fw_file->codeswap_len = ie_len; break; default: ath10k_warn(ar, "Unknown FW IE: %u\n", @@ -1162,12 +1281,15 @@ data += ie_len; } - if (!ar->firmware_data || !ar->firmware_len) { + if (ar->is_bmi) { + if (!fw_file->firmware_data || + !fw_file->firmware_len) { ath10k_warn(ar, "No ATH10K_FW_IE_FW_IMAGE found from '%s/%s', skipping\n", ar->hw_params.fw.dir, name); ret = -ENOMEDIUM; goto err; } + } return 0; @@ -1179,47 +1301,117 @@ static int ath10k_core_fetch_firmware_files(struct ath10k *ar) { int ret; + struct ath10k_fw_file *fw_file; + if (!ar->is_bmi) { + fw_file = &ar->normal_mode_fw.fw_file; + fw_file->wmi_op_version = ATH10K_FW_WMI_OP_VERSION_TLV; + fw_file->htt_op_version = ATH10K_FW_HTT_OP_VERSION_TLV; + __set_bit(ATH10K_FW_FEATURE_WOWLAN_SUPPORT, + fw_file->fw_features); + __set_bit(WMI_SERVICE_WOW, ar->wmi.svc_map); + __set_bit(ATH10K_FW_FEATURE_NO_NWIFI_DECAP_4ADDR_PADDING, + fw_file->fw_features); + return 0; + } + + if (ar->is_bmi) { /* calibration file is optional, don't check for any errors */ ath10k_fetch_cal_file(ar); + } ar->fw_api = 5; ath10k_dbg(ar, ATH10K_DBG_BOOT, "trying fw api %d\n", ar->fw_api); - ret = ath10k_core_fetch_firmware_api_n(ar, ATH10K_FW_API5_FILE); + ret = ath10k_core_fetch_firmware_api_n(ar, ATH10K_FW_API5_FILE, + &ar->normal_mode_fw.fw_file); if (ret == 0) goto success; ar->fw_api = 4; ath10k_dbg(ar, ATH10K_DBG_BOOT, "trying fw api %d\n", ar->fw_api); - ret = ath10k_core_fetch_firmware_api_n(ar, ATH10K_FW_API4_FILE); + ret = ath10k_core_fetch_firmware_api_n(ar, ATH10K_FW_API4_FILE, + &ar->normal_mode_fw.fw_file); if (ret == 0) goto success; ar->fw_api = 3; ath10k_dbg(ar, ATH10K_DBG_BOOT, "trying fw api %d\n", ar->fw_api); - ret = ath10k_core_fetch_firmware_api_n(ar, ATH10K_FW_API3_FILE); + ret = ath10k_core_fetch_firmware_api_n(ar, ATH10K_FW_API3_FILE, + &ar->normal_mode_fw.fw_file); if (ret == 0) goto success; ar->fw_api = 2; ath10k_dbg(ar, ATH10K_DBG_BOOT, "trying fw api %d\n", ar->fw_api); - ret = ath10k_core_fetch_firmware_api_n(ar, ATH10K_FW_API2_FILE); - if (ret == 0) + ret = ath10k_core_fetch_firmware_api_n(ar, ATH10K_FW_API2_FILE, + &ar->normal_mode_fw.fw_file); + if (ret) + return ret; + +success: + ath10k_dbg(ar, ATH10K_DBG_BOOT, "using fw api %d\n", ar->fw_api); + + return 0; +} + +static int ath10k_core_pre_cal_download(struct ath10k *ar) +{ + int ret; + + ret = ath10k_download_cal_file(ar, ar->pre_cal_file); + if (ret == 0) { + ar->cal_mode = ATH10K_PRE_CAL_MODE_FILE; goto success; + } - ar->fw_api = 1; - ath10k_dbg(ar, ATH10K_DBG_BOOT, "trying fw api %d\n", ar->fw_api); + ath10k_dbg(ar, ATH10K_DBG_BOOT, + "boot did not find a pre calibration file, try DT next: %d\n", + ret); - ret = ath10k_core_fetch_firmware_api_1(ar); - if (ret) + ret = ath10k_download_cal_dt(ar, "qcom,ath10k-pre-calibration-data"); + if (ret) { + ath10k_dbg(ar, ATH10K_DBG_BOOT, + "unable to load pre cal data from DT: %d\n", ret); return ret; + } + ar->cal_mode = ATH10K_PRE_CAL_MODE_DT; success: - ath10k_dbg(ar, ATH10K_DBG_BOOT, "using fw api %d\n", ar->fw_api); + ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot using calibration mode %s\n", + ath10k_cal_mode_str(ar->cal_mode)); + + return 0; +} + +static int ath10k_core_pre_cal_config(struct ath10k *ar) +{ + int ret; + + ret = ath10k_core_pre_cal_download(ar); + if (ret) { + ath10k_dbg(ar, ATH10K_DBG_BOOT, + "failed to load pre cal data: %d\n", ret); + return ret; + } + + ret = ath10k_core_get_board_id_from_otp(ar); + if (ret) { + ath10k_err(ar, "failed to get board id: %d\n", ret); + return ret; + } + + ret = ath10k_download_and_run_otp(ar); + if (ret) { + ath10k_err(ar, "failed to run otp: %d\n", ret); + return ret; + } + + ath10k_dbg(ar, ATH10K_DBG_BOOT, + "pre cal configuration done successfully\n"); return 0; } @@ -1228,7 +1420,15 @@ { int ret; - ret = ath10k_download_cal_file(ar); + ret = ath10k_core_pre_cal_config(ar); + if (ret == 0) + return 0; + + ath10k_dbg(ar, ATH10K_DBG_BOOT, + "pre cal download procedure failed, try cal file: %d\n", + ret); + + ret = ath10k_download_cal_file(ar, ar->cal_file); if (ret == 0) { ar->cal_mode = ATH10K_CAL_MODE_FILE; goto done; @@ -1238,14 +1438,24 @@ "boot did not find a calibration file, try DT next: %d\n", ret); - ret = ath10k_download_cal_dt(ar); + ret = ath10k_download_cal_dt(ar, "qcom,ath10k-calibration-data"); if (ret == 0) { ar->cal_mode = ATH10K_CAL_MODE_DT; goto done; } ath10k_dbg(ar, ATH10K_DBG_BOOT, - "boot did not find DT entry, try OTP next: %d\n", + "boot did not find DT entry, try target EEPROM next: %d\n", + ret); + + ret = ath10k_download_cal_eeprom(ar); + if (ret == 0) { + ar->cal_mode = ATH10K_CAL_MODE_EEPROM; + goto done; + } + + ath10k_dbg(ar, ATH10K_DBG_BOOT, + "boot did not find target EEPROM entry, try OTP next: %d\n", ret); ret = ath10k_download_and_run_otp(ar); @@ -1342,13 +1552,15 @@ ieee80211_stop_queues(ar->hw); ath10k_drain_tx(ar); - complete_all(&ar->scan.started); - complete_all(&ar->scan.completed); - complete_all(&ar->scan.on_channel); - complete_all(&ar->offchan_tx_completed); - complete_all(&ar->install_key_done); - complete_all(&ar->vdev_setup_done); - complete_all(&ar->thermal.wmi_sync); + complete(&ar->scan.started); + complete(&ar->scan.completed); + complete(&ar->scan.on_channel); + complete(&ar->offchan_tx_completed); + complete(&ar->install_key_done); + complete(&ar->vdev_setup_done); + complete(&ar->vdev_delete_done); + complete(&ar->thermal.wmi_sync); + complete(&ar->bss_survey_done); wake_up(&ar->htt.empty_tx_wq); wake_up(&ar->wmi.tx_credits_wq); wake_up(&ar->peer_mapping_wq); @@ -1386,15 +1598,17 @@ static int ath10k_core_init_firmware_features(struct ath10k *ar) { - if (test_bit(ATH10K_FW_FEATURE_WMI_10_2, ar->fw_features) && - !test_bit(ATH10K_FW_FEATURE_WMI_10X, ar->fw_features)) { + struct ath10k_fw_file *fw_file = &ar->normal_mode_fw.fw_file; + + if (test_bit(ATH10K_FW_FEATURE_WMI_10_2, fw_file->fw_features) && + !test_bit(ATH10K_FW_FEATURE_WMI_10X, fw_file->fw_features)) { ath10k_err(ar, "feature bits corrupted: 10.2 feature requires 10.x feature to be set as well"); return -EINVAL; } - if (ar->wmi.op_version >= ATH10K_FW_WMI_OP_VERSION_MAX) { + if (fw_file->wmi_op_version >= ATH10K_FW_WMI_OP_VERSION_MAX) { ath10k_err(ar, "unsupported WMI OP version (max %d): %d\n", - ATH10K_FW_WMI_OP_VERSION_MAX, ar->wmi.op_version); + ATH10K_FW_WMI_OP_VERSION_MAX, fw_file->wmi_op_version); return -EINVAL; } @@ -1406,7 +1620,7 @@ break; case ATH10K_CRYPT_MODE_SW: if (!test_bit(ATH10K_FW_FEATURE_RAW_MODE_SUPPORT, - ar->fw_features)) { + fw_file->fw_features)) { ath10k_err(ar, "cryptmode > 0 requires raw mode support from firmware"); return -EINVAL; } @@ -1425,7 +1639,7 @@ if (rawmode) { if (!test_bit(ATH10K_FW_FEATURE_RAW_MODE_SUPPORT, - ar->fw_features)) { + fw_file->fw_features)) { ath10k_err(ar, "rawmode = 1 requires support from firmware"); return -EINVAL; } @@ -1450,19 +1664,19 @@ /* Backwards compatibility for firmwares without * ATH10K_FW_IE_WMI_OP_VERSION. */ - if (ar->wmi.op_version == ATH10K_FW_WMI_OP_VERSION_UNSET) { - if (test_bit(ATH10K_FW_FEATURE_WMI_10X, ar->fw_features)) { + if (fw_file->wmi_op_version == ATH10K_FW_WMI_OP_VERSION_UNSET) { + if (test_bit(ATH10K_FW_FEATURE_WMI_10X, fw_file->fw_features)) { if (test_bit(ATH10K_FW_FEATURE_WMI_10_2, - ar->fw_features)) - ar->wmi.op_version = ATH10K_FW_WMI_OP_VERSION_10_2; + fw_file->fw_features)) + fw_file->wmi_op_version = ATH10K_FW_WMI_OP_VERSION_10_2; else - ar->wmi.op_version = ATH10K_FW_WMI_OP_VERSION_10_1; + fw_file->wmi_op_version = ATH10K_FW_WMI_OP_VERSION_10_1; } else { - ar->wmi.op_version = ATH10K_FW_WMI_OP_VERSION_MAIN; + fw_file->wmi_op_version = ATH10K_FW_WMI_OP_VERSION_MAIN; } } - switch (ar->wmi.op_version) { + switch (fw_file->wmi_op_version) { case ATH10K_FW_WMI_OP_VERSION_MAIN: ar->max_num_peers = TARGET_NUM_PEERS; ar->max_num_stations = TARGET_NUM_STATIONS; @@ -1475,8 +1689,13 @@ case ATH10K_FW_WMI_OP_VERSION_10_1: case ATH10K_FW_WMI_OP_VERSION_10_2: case ATH10K_FW_WMI_OP_VERSION_10_2_4: + if (ath10k_peer_stats_enabled(ar)) { + ar->max_num_peers = TARGET_10X_TX_STATS_NUM_PEERS; + ar->max_num_stations = TARGET_10X_TX_STATS_NUM_STATIONS; + } else { ar->max_num_peers = TARGET_10X_NUM_PEERS; ar->max_num_stations = TARGET_10X_NUM_STATIONS; + } ar->max_num_vdevs = TARGET_10X_NUM_VDEVS; ar->htt.max_num_pending_tx = TARGET_10X_NUM_MSDU_DESC; ar->fw_stats_req_mask = WMI_STAT_PEER; @@ -1487,11 +1706,16 @@ ar->max_num_stations = TARGET_TLV_NUM_STATIONS; ar->max_num_vdevs = TARGET_TLV_NUM_VDEVS; ar->max_num_tdls_vdevs = TARGET_TLV_NUM_TDLS_VDEVS; + if (QCA_REV_WCN3990(ar)) + ar->htt.max_num_pending_tx = + TARGET_HL_1_0_NUM_MSDU_DESC; + else ar->htt.max_num_pending_tx = TARGET_TLV_NUM_MSDU_DESC; ar->wow.max_num_patterns = TARGET_TLV_NUM_WOW_PATTERNS; ar->fw_stats_req_mask = WMI_STAT_PDEV | WMI_STAT_VDEV | WMI_STAT_PEER; ar->max_spatial_stream = WMI_MAX_SPATIAL_STREAM; + ar->wmi.mgmt_max_num_pending_tx = TARGET_TLV_MGMT_NUM_MSDU_DESC; break; case ATH10K_FW_WMI_OP_VERSION_10_4: ar->max_num_peers = TARGET_10_4_NUM_PEERS; @@ -1499,9 +1723,15 @@ ar->num_active_peers = TARGET_10_4_ACTIVE_PEERS; ar->max_num_vdevs = TARGET_10_4_NUM_VDEVS; ar->num_tids = TARGET_10_4_TGT_NUM_TIDS; + ar->fw_stats_req_mask = WMI_10_4_STAT_PEER | + WMI_10_4_STAT_PEER_EXTD; + ar->max_spatial_stream = ar->hw_params.max_spatial_stream; + + if (test_bit(ATH10K_FW_FEATURE_PEER_FLOW_CONTROL, + fw_file->fw_features)) + ar->htt.max_num_pending_tx = TARGET_10_4_NUM_MSDU_DESC_PFC; + else ar->htt.max_num_pending_tx = TARGET_10_4_NUM_MSDU_DESC; - ar->fw_stats_req_mask = WMI_STAT_PEER; - ar->max_spatial_stream = WMI_10_4_MAX_SPATIAL_STREAM; break; case ATH10K_FW_WMI_OP_VERSION_UNSET: case ATH10K_FW_WMI_OP_VERSION_MAX: @@ -1512,23 +1742,23 @@ /* Backwards compatibility for firmwares without * ATH10K_FW_IE_HTT_OP_VERSION. */ - if (ar->htt.op_version == ATH10K_FW_HTT_OP_VERSION_UNSET) { - switch (ar->wmi.op_version) { + if (fw_file->htt_op_version == ATH10K_FW_HTT_OP_VERSION_UNSET) { + switch (fw_file->wmi_op_version) { case ATH10K_FW_WMI_OP_VERSION_MAIN: - ar->htt.op_version = ATH10K_FW_HTT_OP_VERSION_MAIN; + fw_file->htt_op_version = ATH10K_FW_HTT_OP_VERSION_MAIN; break; case ATH10K_FW_WMI_OP_VERSION_10_1: case ATH10K_FW_WMI_OP_VERSION_10_2: case ATH10K_FW_WMI_OP_VERSION_10_2_4: - ar->htt.op_version = ATH10K_FW_HTT_OP_VERSION_10_1; + fw_file->htt_op_version = ATH10K_FW_HTT_OP_VERSION_10_1; break; case ATH10K_FW_WMI_OP_VERSION_TLV: - ar->htt.op_version = ATH10K_FW_HTT_OP_VERSION_TLV; + fw_file->htt_op_version = ATH10K_FW_HTT_OP_VERSION_TLV; break; case ATH10K_FW_WMI_OP_VERSION_10_4: case ATH10K_FW_WMI_OP_VERSION_UNSET: case ATH10K_FW_WMI_OP_VERSION_MAX: - WARN_ON(1); + ath10k_err(ar, "htt op version not found from fw meta data"); return -EINVAL; } } @@ -1536,14 +1766,69 @@ return 0; } -int ath10k_core_start(struct ath10k *ar, enum ath10k_firmware_mode mode) +static int ath10k_core_reset_rx_filter(struct ath10k *ar) +{ + int ret; + int vdev_id; + int vdev_type; + int vdev_subtype; + const u8 *vdev_addr; + + vdev_id = 0; + vdev_type = WMI_VDEV_TYPE_STA; + vdev_subtype = ath10k_wmi_get_vdev_subtype(ar, WMI_VDEV_SUBTYPE_NONE); + vdev_addr = ar->mac_addr; + + ret = ath10k_wmi_vdev_create(ar, vdev_id, vdev_type, vdev_subtype, + vdev_addr); + if (ret) { + ath10k_err(ar, "failed to create dummy vdev: %d\n", ret); + return ret; + } + + ret = ath10k_wmi_vdev_delete(ar, vdev_id); + if (ret) { + ath10k_err(ar, "failed to delete dummy vdev: %d\n", ret); + return ret; + } + + /* WMI and HTT may use separate HIF pipes and are not guaranteed to be + * serialized properly implicitly. + * + * Moreover (most) WMI commands have no explicit acknowledges. It is + * possible to infer it implicitly by poking firmware with echo + * command - getting a reply means all preceding comments have been + * (mostly) processed. + * + * In case of vdev create/delete this is sufficient. + * + * Without this it's possible to end up with a race when HTT Rx ring is + * started before vdev create/delete hack is complete allowing a short + * window of opportunity to receive (and Tx ACK) a bunch of frames. + */ + ret = ath10k_wmi_barrier(ar); + if (ret) { + ath10k_err(ar, "failed to ping firmware: %d\n", ret); + return ret; + } + + return 0; +} + +int ath10k_core_start(struct ath10k *ar, enum ath10k_firmware_mode mode, + const struct ath10k_fw_components *fw) { int status; + u32 val; lockdep_assert_held(&ar->conf_mutex); clear_bit(ATH10K_FLAG_CRASH_FLUSH, &ar->dev_flags); + ar->running_fw = fw; + + if (ar->is_bmi) { + ath10k_bmi_start(ar); if (ath10k_init_configure_target(ar)) { @@ -1558,26 +1843,28 @@ /* Some of of qca988x solutions are having global reset issue * during target initialization. Bypassing PLL setting before * downloading firmware and letting the SoC run on REF_CLK is - * fixing the problem. Corresponding firmware change is also needed - * to set the clock source once the target is initialized. + * fixing the problem. Corresponding firmware change is also + * needed to set the clock source once the target is + * initialized. */ if (test_bit(ATH10K_FW_FEATURE_SUPPORTS_SKIP_CLOCK_INIT, - ar->fw_features)) { + ar->running_fw->fw_file.fw_features)) { status = ath10k_bmi_write32(ar, hi_skip_clock_init, 1); if (status) { - ath10k_err(ar, "could not write to skip_clock_init: %d\n", + ath10k_err(ar, "skip_clock_init failed: %d\n", status); goto err; } } - status = ath10k_download_fw(ar, mode); + status = ath10k_download_fw(ar); if (status) goto err; status = ath10k_init_uart(ar); if (status) goto err; + } ar->htc.htc_ops.target_send_suspend_complete = ath10k_send_suspend_complete; @@ -1588,9 +1875,11 @@ goto err; } + if (ar->is_bmi) { status = ath10k_bmi_done(ar); if (status) goto err; + } status = ath10k_wmi_attach(ar); if (status) { @@ -1648,6 +1937,12 @@ goto err_hif_stop; } + status = ath10k_pktlog_connect(ar); + if (status) { + ath10k_err(ar, "could not connect pktlog: %d\n", status); + goto err_hif_stop; + } + status = ath10k_htc_start(&ar->htc); if (status) { ath10k_err(ar, "failed to start htc: %d\n", status); @@ -1665,6 +1960,33 @@ ath10k_dbg(ar, ATH10K_DBG_BOOT, "firmware %s booted\n", ar->hw->wiphy->fw_version); + if (test_bit(WMI_SERVICE_EXT_RES_CFG_SUPPORT, ar->wmi.svc_map)) { + val = 0; + if (ath10k_peer_stats_enabled(ar)) + val = WMI_10_4_PEER_STATS; + + if (test_bit(WMI_SERVICE_BSS_CHANNEL_INFO_64, ar->wmi.svc_map)) + val |= WMI_10_4_BSS_CHANNEL_INFO_64; + + /* 10.4 firmware supports BT-Coex without reloading firmware + * via pdev param. To support Bluetooth coexistence pdev param, + * WMI_COEX_GPIO_SUPPORT of extended resource config should be + * enabled always. + */ + if (test_bit(WMI_SERVICE_COEX_GPIO, ar->wmi.svc_map) && + test_bit(ATH10K_FW_FEATURE_BTCOEX_PARAM, + ar->running_fw->fw_file.fw_features)) + val |= WMI_10_4_COEX_GPIO_SUPPORT; + + status = ath10k_mac_ext_resource_config(ar, val); + if (status) { + ath10k_err(ar, + "failed to send ext resource cfg command : %d\n", + status); + goto err_hif_stop; + } + } + status = ath10k_wmi_cmd_init(ar); if (status) { ath10k_err(ar, "could not send WMI init command (%d)\n", @@ -1678,12 +2000,37 @@ goto err_hif_stop; } + /* Some firmware revisions do not properly set up hardware rx filter + * registers. + * + * A known example from QCA9880 and 10.2.4 is that MAC_PCU_ADDR1_MASK + * is filled with 0s instead of 1s allowing HW to respond with ACKs to + * any frames that matches MAC_PCU_RX_FILTER which is also + * misconfigured to accept anything. + * + * The ADDR1 is programmed using internal firmware structure field and + * can't be (easily/sanely) reached from the driver explicitly. It is + * possible to implicitly make it correct by creating a dummy vdev and + * then deleting it. + */ + if (!QCA_REV_WCN3990(ar)) { + status = ath10k_core_reset_rx_filter(ar); + if (status) { + ath10k_err(ar, "failed to reset rx filter: %d\n", + status); + goto err_hif_stop; + } + } + status = ath10k_htt_rx_ring_refill(ar); if (status) { ath10k_err(ar, "failed to refill htt rx ring: %d\n", status); goto err_hif_stop; } + if (ar->max_num_vdevs >= 64) + ar->free_vdev_map = 0xFFFFFFFFFFFFFFFFLL; + else ar->free_vdev_map = (1LL << ar->max_num_vdevs) - 1; INIT_LIST_HEAD(&ar->arvifs); @@ -1747,7 +2094,7 @@ /* try to suspend target */ if (ar->state != ATH10K_STATE_RESTARTING && ar->state != ATH10K_STATE_UTF) - ath10k_wait_for_suspend(ar, WMI_PDEV_SUSPEND_AND_DISABLE_INTR); + ath10k_wait_for_suspend(ar, ar->hw_values->pdev_suspend_option); ath10k_hif_stop(ar); ath10k_htt_tx_free(&ar->htt); @@ -1771,15 +2118,16 @@ return ret; } + if (ar->is_bmi) { memset(&target_info, 0, sizeof(target_info)); ret = ath10k_bmi_get_target_info(ar, &target_info); if (ret) { ath10k_err(ar, "could not get target info (%d)\n", ret); goto err_power_down; } - ar->target_version = target_info.version; ar->hw->wiphy->hw_version = target_info.version; + } ret = ath10k_init_hw_params(ar); if (ret) { @@ -1793,11 +2141,28 @@ goto err_power_down; } + BUILD_BUG_ON(sizeof(ar->hw->wiphy->fw_version) != + sizeof(ar->normal_mode_fw.fw_file.fw_version)); + memcpy(ar->hw->wiphy->fw_version, + ar->normal_mode_fw.fw_file.fw_version, + sizeof(ar->hw->wiphy->fw_version)); + ath10k_debug_print_hwfw_info(ar); + + if (ar->is_bmi) { + ret = ath10k_core_pre_cal_download(ar); + if (ret) { + /* pre calibration data download is not necessary + * for all the chipsets. Ignore failures and continue. + */ + ath10k_dbg(ar, ATH10K_DBG_BOOT, + "could not load pre cal data: %d\n", ret); + } + ret = ath10k_core_get_board_id_from_otp(ar); if (ret && ret != -EOPNOTSUPP) { - ath10k_err(ar, "failed to get board id from otp for qca99x0: %d\n", + ath10k_err(ar, "failed to get board id from otp: %d\n", ret); - return ret; + goto err_free_firmware_files; } ret = ath10k_core_fetch_board_file(ar); @@ -1806,6 +2171,9 @@ goto err_free_firmware_files; } + ath10k_debug_print_board_info(ar); + } + ret = ath10k_core_init_firmware_features(ar); if (ret) { ath10k_err(ar, "fatal problem with firmware features: %d\n", @@ -1813,22 +2181,26 @@ goto err_free_firmware_files; } - ret = ath10k_swap_code_seg_init(ar); + if (ar->is_bmi) { + ret = ath10k_swap_code_seg_init(ar, + &ar->normal_mode_fw.fw_file); if (ret) { - ath10k_err(ar, "failed to initialize code swap segment: %d\n", + ath10k_err(ar, "failed to init code swap segment: %d\n", ret); goto err_free_firmware_files; } + } mutex_lock(&ar->conf_mutex); - ret = ath10k_core_start(ar, ATH10K_FIRMWARE_MODE_NORMAL); + ret = ath10k_core_start(ar, ATH10K_FIRMWARE_MODE_NORMAL, + &ar->normal_mode_fw); if (ret) { ath10k_err(ar, "could not init core (%d)\n", ret); goto err_unlock; } - ath10k_print_driver_info(ar); + ath10k_debug_print_boot_info(ar); ath10k_core_stop(ar); mutex_unlock(&ar->conf_mutex); @@ -1853,6 +2225,9 @@ struct ath10k *ar = container_of(work, struct ath10k, register_work); int status; + /* peer stats are enabled by default */ + set_bit(ATH10K_FLAG_PEER_STATS, &ar->dev_flags); + status = ath10k_core_probe_fw(ar); if (status) { ath10k_err(ar, "could not probe fw (%d)\n", status); @@ -1958,20 +2333,52 @@ ar->hif.ops = hif_ops; ar->hif.bus = bus; + /* By default, assume bmi is set, as most of the existing + * chip sets are based on this, set to false explicitly + * when current chip set does not support. + */ + ar->is_bmi = true; + switch (hw_rev) { case ATH10K_HW_QCA988X: + case ATH10K_HW_QCA9887: ar->regs = &qca988x_regs; + ar->hw_ce_regs = &qcax_ce_regs; ar->hw_values = &qca988x_values; break; case ATH10K_HW_QCA6174: case ATH10K_HW_QCA9377: ar->regs = &qca6174_regs; + ar->hw_ce_regs = &qcax_ce_regs; ar->hw_values = &qca6174_values; break; case ATH10K_HW_QCA99X0: + case ATH10K_HW_QCA9984: ar->regs = &qca99x0_regs; + ar->hw_ce_regs = &qcax_ce_regs; ar->hw_values = &qca99x0_values; break; + case ATH10K_HW_QCA9888: + ar->regs = &qca99x0_regs; + ar->hw_ce_regs = &qcax_ce_regs; + ar->hw_values = &qca9888_values; + break; + case ATH10K_HW_QCA4019: + ar->regs = &qca4019_regs; + ar->hw_ce_regs = &qcax_ce_regs; + ar->hw_values = &qca4019_values; + break; + case ATH10K_HW_WCN3990: + ar->regs = &wcn3990_regs; + ar->hw_ce_regs = &wcn3990_ce_regs; + ar->hw_values = &wcn3990_values; + /* WCN3990 chip set is non bmi based */ + ar->is_bmi = false; + ar->fw_flags = &wcn3990_fw_flags; + ar->shadow_reg_value = &wcn3990_shadow_reg_value; + ar->shadow_reg_address = &wcn3990_shadow_reg_address; + ar->rri_on_ddr = true; + break; default: ath10k_err(ar, "unsupported core hardware revision %d\n", hw_rev); @@ -1987,7 +2394,10 @@ init_completion(&ar->install_key_done); init_completion(&ar->vdev_setup_done); + init_completion(&ar->vdev_delete_done); init_completion(&ar->thermal.wmi_sync); + init_completion(&ar->bss_survey_done); + init_completion(&ar->peer_delete_done); INIT_DELAYED_WORK(&ar->scan.timeout, ath10k_scan_timeout_work); @@ -2001,7 +2411,10 @@ mutex_init(&ar->conf_mutex); spin_lock_init(&ar->data_lock); + spin_lock_init(&ar->txqs_lock); + spin_lock_init(&ar->datapath_rx_stat_lock); + INIT_LIST_HEAD(&ar->txqs); INIT_LIST_HEAD(&ar->peers); init_waitqueue_head(&ar->peer_mapping_wq); init_waitqueue_head(&ar->htt.empty_tx_wq); @@ -2017,6 +2430,8 @@ INIT_WORK(&ar->register_work, ath10k_core_register_work); INIT_WORK(&ar->restart_work, ath10k_core_restart); + init_dummy_netdev(&ar->napi_dev); + ret = ath10k_debug_create(ar); if (ret) goto err_free_aux_wq; @@ -2050,5 +2465,5 @@ EXPORT_SYMBOL(ath10k_core_destroy); MODULE_AUTHOR("Qualcomm Atheros"); -MODULE_DESCRIPTION("Core module for QCA988X PCIe devices."); +MODULE_DESCRIPTION("Core module for Qualcomm Atheros 802.11ac wireless LAN cards."); MODULE_LICENSE("Dual BSD/GPL"); diff -ruw linux-4.4.115/drivers/net/wireless/ath/ath10k/core.h linux-4.4.115-fbx/drivers/net/wireless/ath/ath10k/core.h --- linux-4.4.115/drivers/net/wireless/ath/ath10k/core.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/net/wireless/ath/ath10k/core.h 2019-01-22 16:16:25.415263721 +0100 @@ -1,6 +1,6 @@ /* * Copyright (c) 2005-2011 Atheros Communications Inc. - * Copyright (c) 2011-2013 Qualcomm Atheros, Inc. + * Copyright (c) 2011-2013, 2017 Qualcomm Atheros, Inc. * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above @@ -24,6 +24,8 @@ #include #include #include +#include +#include #include "htt.h" #include "htc.h" @@ -65,10 +67,30 @@ #define ATH10K_KEEPALIVE_MAX_IDLE 3895 #define ATH10K_KEEPALIVE_MAX_UNRESPONSIVE 3900 +/* NAPI poll budget */ +#define ATH10K_NAPI_BUDGET 64 +#define ATH10K_NAPI_QUOTA_LIMIT 60 + +#define ATH10K_RX_MCS_MIN 0 +#define ATH10K_RX_HT_MCS_MAX 32 +#define ATH10K_RX_VHT_RATEIDX_MAX 9 +#define ATH10K_RX_VHT_MCS_MAX 20 /* For 2x2 */ +#define ATH10K_RX_NSS_MIN 0 +#define ATH10K_RX_NSS_MAX 5 + +enum ath10k_datapath_rx_band { + ATH10K_BAND_MIN, + ATH10K_BAND_2GHZ = ATH10K_BAND_MIN, + ATH10K_BAND_5GHZ, + ATH10K_BAND_MAX, +}; + struct ath10k; enum ath10k_bus { ATH10K_BUS_PCI, + ATH10K_BUS_AHB, + ATH10K_BUS_SNOC, }; static inline const char *ath10k_bus_str(enum ath10k_bus bus) @@ -76,31 +98,30 @@ switch (bus) { case ATH10K_BUS_PCI: return "pci"; + case ATH10K_BUS_AHB: + return "ahb"; + case ATH10K_BUS_SNOC: + return "snoc"; } return "unknown"; } +enum ath10k_skb_flags { + ATH10K_SKB_F_NO_HWCRYPT = BIT(0), + ATH10K_SKB_F_DTIM_ZERO = BIT(1), + ATH10K_SKB_F_DELIVER_CAB = BIT(2), + ATH10K_SKB_F_MGMT = BIT(3), + ATH10K_SKB_F_QOS = BIT(4), +}; + struct ath10k_skb_cb { dma_addr_t paddr; + u8 flags; u8 eid; - u8 vdev_id; - enum ath10k_hw_txrx_mode txmode; - bool is_protected; - - struct { - u8 tid; - u16 freq; - bool is_offchan; - bool nohwcrypt; - struct ath10k_htt_txbuf *txbuf; - u32 txbuf_paddr; - } __packed htt; - - struct { - bool dtim_zero; - bool deliver_cab; - } bcn; + u16 msdu_id; + struct ieee80211_vif *vif; + struct ieee80211_txq *txq; } __packed; struct ath10k_skb_rxcb { @@ -141,17 +162,22 @@ }; struct ath10k_wmi { - enum ath10k_fw_wmi_op_version op_version; enum ath10k_htc_ep_id eid; struct completion service_ready; struct completion unified_ready; + struct completion barrier; wait_queue_head_t tx_credits_wq; DECLARE_BITMAP(svc_map, WMI_SERVICE_MAX); struct wmi_cmd_map *cmd; struct wmi_vdev_param_map *vdev_param; struct wmi_pdev_param_map *pdev_param; const struct wmi_ops *ops; + const struct wmi_peer_flags_map *peer_flags; + u32 mgmt_max_num_pending_tx; + struct idr mgmt_pending_tx; + /* Protects access to mgmt_pending_tx, mgmt_max_num_pending_tx */ + spinlock_t mgmt_tx_lock; u32 num_mem_chunks; u32 rx_decap_mode; struct ath10k_mem_chunk mem_chunks[WMI_MAX_MEM_REQS]; @@ -164,6 +190,14 @@ u32 peer_rssi; u32 peer_tx_rate; u32 peer_rx_rate; /* 10x only */ + u32 rx_duration; +}; + +struct ath10k_fw_extd_stats_peer { + struct list_head list; + + u8 peer_macaddr[ETH_ALEN]; + u32 rx_duration; }; struct ath10k_fw_stats_vdev { @@ -190,10 +224,10 @@ /* PDEV stats */ s32 ch_noise_floor; - u32 tx_frame_count; - u32 rx_frame_count; - u32 rx_clear_count; - u32 cycle_count; + u32 tx_frame_count; /* Cycles spent transmitting frames */ + u32 rx_frame_count; /* Cycles spent receiving frames */ + u32 rx_clear_count; /* Total channel busy time, evidently */ + u32 cycle_count; /* Total on-channel time */ u32 phy_err_count; u32 chan_tx_power; u32 ack_rx_bad; @@ -257,9 +291,11 @@ }; struct ath10k_fw_stats { + bool extended; struct list_head pdevs; struct list_head vdevs; struct list_head peers; + struct list_head peers_extd; }; #define ATH10K_TPC_TABLE_TYPE_FLAG 1 @@ -298,6 +334,9 @@ struct ath10k_peer { struct list_head list; + struct ieee80211_vif *vif; + struct ieee80211_sta *sta; + int vdev_id; u8 addr[ETH_ALEN]; DECLARE_BITMAP(peer_ids, ATH10K_MAX_NUM_PEER_IDS); @@ -306,6 +345,12 @@ struct ieee80211_key_conf *keys[WMI_MAX_KEY_INDEX + 1]; }; +struct ath10k_txq { + struct list_head list; + unsigned long num_fw_queued; + unsigned long num_push_allowed; +}; + struct ath10k_sta { struct ath10k_vif *arvif; @@ -314,16 +359,19 @@ u32 bw; u32 nss; u32 smps; + u16 peer_id; struct work_struct update_wk; #ifdef CONFIG_MAC80211_DEBUGFS /* protected by conf_mutex */ bool aggr_mode; + u64 rx_duration; #endif }; #define ATH10K_VDEV_SETUP_TIMEOUT_HZ (5*HZ) +#define ATH10K_VDEV_DELETE_TIMEOUT_HZ (5 * HZ) enum ath10k_beacon_state { ATH10K_BEACON_SCHEDULED = 0, @@ -335,6 +383,7 @@ struct list_head list; u32 vdev_id; + u16 peer_id; enum wmi_vdev_type vdev_type; enum wmi_vdev_subtype vdev_subtype; u32 beacon_interval; @@ -386,6 +435,9 @@ struct work_struct ap_csa_work; struct delayed_work connection_loss_work; struct cfg80211_bitrate_mask bitrate_mask; + struct wmi_ns_arp_offload_req arp_offload; + struct wmi_ns_arp_offload_req ns_offload; + struct wmi_gtk_rekey_data gtk_rekey_data; }; struct ath10k_vif_iter { @@ -420,11 +472,13 @@ struct completion tpc_complete; /* protected by conf_mutex */ - u32 fw_dbglog_mask; + u64 fw_dbglog_mask; u32 fw_dbglog_level; u32 pktlog_filter; + enum ath10k_htc_ep_id eid; u32 reg_addr; u32 nf_cal_period; + void *cal_data; struct ath10k_fw_crash_data *fw_crash_data; }; @@ -512,6 +566,32 @@ /* Firmware Supports Adaptive CCA*/ ATH10K_FW_FEATURE_SUPPORTS_ADAPTIVE_CCA = 11, + /* Firmware supports management frame protection */ + ATH10K_FW_FEATURE_MFP_SUPPORT = 12, + + /* Firmware supports pull-push model where host shares it's software + * queue state with firmware and firmware generates fetch requests + * telling host which queues to dequeue tx from. + * + * Primary function of this is improved MU-MIMO performance with + * multiple clients. + */ + ATH10K_FW_FEATURE_PEER_FLOW_CONTROL = 13, + + /* Firmware supports BT-Coex without reloading firmware via pdev param. + * To support Bluetooth coexistence pdev param, WMI_COEX_GPIO_SUPPORT of + * extended resource config should be enabled always. This firmware IE + * is used to configure WMI_COEX_GPIO_SUPPORT. + */ + ATH10K_FW_FEATURE_BTCOEX_PARAM = 14, + + /* Older firmware with HTT delivers incorrect tx status for null func + * frames to driver, but this fixed in 10.2 and 10.4 firmware versions. + * Also this workaround results in reporting of incorrect null func + * status for 10.4. This flag is used to skip the workaround. + */ + ATH10K_FW_FEATURE_SKIP_NULL_FUNC_WAR = 15, + /* keep last */ ATH10K_FW_FEATURE_COUNT, }; @@ -534,12 +614,21 @@ /* Disable HW crypto engine */ ATH10K_FLAG_HW_CRYPTO_DISABLED, + + /* Bluetooth coexistance enabled */ + ATH10K_FLAG_BTCOEX, + + /* Per Station statistics service */ + ATH10K_FLAG_PEER_STATS, }; enum ath10k_cal_mode { ATH10K_CAL_MODE_FILE, ATH10K_CAL_MODE_OTP, ATH10K_CAL_MODE_DT, + ATH10K_PRE_CAL_MODE_FILE, + ATH10K_PRE_CAL_MODE_DT, + ATH10K_CAL_MODE_EEPROM, }; enum ath10k_crypt_mode { @@ -558,6 +647,12 @@ return "otp"; case ATH10K_CAL_MODE_DT: return "dt"; + case ATH10K_PRE_CAL_MODE_FILE: + return "pre-cal-file"; + case ATH10K_PRE_CAL_MODE_DT: + return "pre-cal-dt"; + case ATH10K_CAL_MODE_EEPROM: + return "eeprom"; } return "unknown"; @@ -591,11 +686,68 @@ ATH10K_TX_PAUSE_MAX, }; +struct fw_flag { + u32 flags; +}; + +struct ath10k_fw_file { + const struct firmware *firmware; + + char fw_version[ETHTOOL_FWVERS_LEN]; + + DECLARE_BITMAP(fw_features, ATH10K_FW_FEATURE_COUNT); + + enum ath10k_fw_wmi_op_version wmi_op_version; + enum ath10k_fw_htt_op_version htt_op_version; + + const void *firmware_data; + size_t firmware_len; + + const void *otp_data; + size_t otp_len; + + const void *codeswap_data; + size_t codeswap_len; + + /* The original idea of struct ath10k_fw_file was that it only + * contains struct firmware and pointers to various parts (actual + * firmware binary, otp, metadata etc) of the file. This seg_info + * is actually created separate but as this is used similarly as + * the other firmware components it's more convenient to have it + * here. + */ + struct ath10k_swap_code_seg_info *firmware_swap_code_seg_info; +}; + +struct ath10k_fw_components { + const struct firmware *board; + const void *board_data; + size_t board_len; + + struct ath10k_fw_file fw_file; +}; + +struct datapath_rx_stats { + u32 no_of_packets; + u32 short_gi_pkts; + u32 ht_rate_indx[ATH10K_RX_HT_MCS_MAX + 1]; + u32 vht_rate_indx[ATH10K_RX_VHT_MCS_MAX + 1]; + u32 ht_rate_packets; + u32 vht_rate_packets; + u32 legacy_pkt; + u32 nss[ATH10K_RX_NSS_MAX + 1]; + u32 num_pkts_40Mhz; + u32 num_pkts_80Mhz; + u32 band[ATH10K_BAND_MAX + 1]; +}; + struct ath10k { struct ath_common ath_common; struct ieee80211_hw *hw; + struct ieee80211_ops *ops; struct device *dev; u8 mac_addr[ETH_ALEN]; + u8 base_mac_addr[ETH_ALEN]; enum ath10k_hw_rev hw_rev; u16 dev_id; @@ -615,9 +767,7 @@ u32 max_spatial_stream; /* protected by conf_mutex */ bool ani_enabled; - - DECLARE_BITMAP(fw_features, ATH10K_FW_FEATURE_COUNT); - + bool sifs_burst_enabled; bool p2p; struct { @@ -628,71 +778,29 @@ struct completion target_suspend; const struct ath10k_hw_regs *regs; + const struct ath10k_hw_ce_regs *hw_ce_regs; const struct ath10k_hw_values *hw_values; + struct ath10k_shadow_reg_value *shadow_reg_value; + struct ath10k_shadow_reg_address *shadow_reg_address; struct ath10k_bmi bmi; struct ath10k_wmi wmi; struct ath10k_htc htc; struct ath10k_htt htt; - struct ath10k_hw_params { - u32 id; - u16 dev_id; - const char *name; - u32 patch_load_addr; - int uart_pin; - u32 otp_exe_param; - - /* This is true if given HW chip has a quirky Cycle Counter - * wraparound which resets to 0x7fffffff instead of 0. All - * other CC related counters (e.g. Rx Clear Count) are divided - * by 2 so they never wraparound themselves. - */ - bool has_shifted_cc_wraparound; - - /* Some of chip expects fragment descriptor to be continuous - * memory for any TX operation. Set continuous_frag_desc flag - * for the hardware which have such requirement. - */ - bool continuous_frag_desc; - - u32 channel_counters_freq_hz; - - /* Mgmt tx descriptors threshold for limiting probe response - * frames. - */ - u32 max_probe_resp_desc_thres; - - struct ath10k_hw_params_fw { - const char *dir; - const char *fw; - const char *otp; - const char *board; - size_t board_size; - size_t board_ext_size; - } fw; - } hw_params; - - const struct firmware *board; - const void *board_data; - size_t board_len; + struct ath10k_hw_params hw_params; - const struct firmware *otp; - const void *otp_data; - size_t otp_len; + /* contains the firmware images used with ATH10K_FIRMWARE_MODE_NORMAL */ + struct ath10k_fw_components normal_mode_fw; - const struct firmware *firmware; - const void *firmware_data; - size_t firmware_len; + /* READ-ONLY images of the running firmware, which can be either + * normal or UTF. Do not modify, release etc! + */ + const struct ath10k_fw_components *running_fw; + const struct firmware *pre_cal_file; const struct firmware *cal_file; struct { - const void *firmware_codeswap_data; - size_t firmware_codeswap_len; - struct ath10k_swap_code_seg_info *firmware_swap_code_seg_info; - } swap; - - struct { u32 vendor; u32 device; u32 subsystem_vendor; @@ -732,6 +840,9 @@ /* current operating channel definition */ struct cfg80211_chan_def chandef; + /* currently configured operating channel in firmware */ + struct ieee80211_channel *tgt_oper_chan; + unsigned long long free_vdev_map; struct ath10k_vif *monitor_arvif; bool monitor; @@ -752,6 +863,7 @@ struct completion install_key_done; struct completion vdev_setup_done; + struct completion vdev_delete_done; struct workqueue_struct *workqueue; /* Auxiliary workqueue */ @@ -762,9 +874,13 @@ /* protects shared structure data */ spinlock_t data_lock; + /* protects: ar->txqs, artxq->list */ + spinlock_t txqs_lock; + struct list_head txqs; struct list_head arvifs; struct list_head peers; + struct ath10k_peer *peer_map[ATH10K_MAX_NUM_PEER_IDS]; wait_queue_head_t peer_mapping_wq; /* protected by conf_mutex */ @@ -807,6 +923,7 @@ * avoid reporting garbage data. */ bool ch_info_can_report_survey; + struct completion bss_survey_done; struct dfs_pattern_detector *dfs_detector; @@ -814,8 +931,6 @@ #ifdef CONFIG_ATH10K_DEBUGFS struct ath10k_debug debug; -#endif - struct { /* relay(fs) channel for spectral scan */ struct rchan *rfs_chan_spec_scan; @@ -824,16 +939,15 @@ enum ath10k_spectral_mode mode; struct ath10k_spec_scan config; } spectral; + struct datapath_rx_stats *rx_stats; +#endif + /* prevent concurrency histogram for receiving data packet */ + spinlock_t datapath_rx_stat_lock; struct { /* protected by conf_mutex */ - const struct firmware *utf; - char utf_version[32]; - const void *utf_firmware_data; - size_t utf_firmware_len; - DECLARE_BITMAP(orig_fw_features, ATH10K_FW_FEATURE_COUNT); - enum ath10k_fw_wmi_op_version orig_wmi_op_version; - enum ath10k_fw_wmi_op_version op_version; + struct ath10k_fw_components utf_mode_fw; + /* protected by data_lock */ bool utf_monitor; } testmode; @@ -848,10 +962,29 @@ struct ath10k_thermal thermal; struct ath10k_wow wow; + /* NAPI */ + struct net_device napi_dev; + struct napi_struct napi; + + struct fw_flag *fw_flags; + /* set for bmi chip sets */ + struct completion peer_delete_done; + bool is_bmi; + enum ieee80211_sta_state sta_state; + bool rri_on_ddr; /* must be last */ u8 drv_priv[0] __aligned(sizeof(void *)); }; +static inline bool ath10k_peer_stats_enabled(struct ath10k *ar) +{ + if (test_bit(ATH10K_FLAG_PEER_STATS, &ar->dev_flags) && + test_bit(WMI_SERVICE_PEER_STATS, ar->wmi.svc_map)) + return true; + + return false; +} + struct ath10k *ath10k_core_create(size_t priv_size, struct device *dev, enum ath10k_bus bus, enum ath10k_hw_rev hw_rev, @@ -860,8 +993,11 @@ void ath10k_core_get_fw_features_str(struct ath10k *ar, char *buf, size_t max_len); +int ath10k_core_fetch_firmware_api_n(struct ath10k *ar, const char *name, + struct ath10k_fw_file *fw_file); -int ath10k_core_start(struct ath10k *ar, enum ath10k_firmware_mode mode); +int ath10k_core_start(struct ath10k *ar, enum ath10k_firmware_mode mode, + const struct ath10k_fw_components *fw_components); int ath10k_wait_for_suspend(struct ath10k *ar, u32 suspend_opt); void ath10k_core_stop(struct ath10k *ar); int ath10k_core_register(struct ath10k *ar, u32 chip_id); diff -ruw linux-4.4.115/drivers/net/wireless/ath/ath10k/debug.c linux-4.4.115-fbx/drivers/net/wireless/ath/ath10k/debug.c --- linux-4.4.115/drivers/net/wireless/ath/ath10k/debug.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/net/wireless/ath/ath10k/debug.c 2019-10-29 09:26:24.457211144 +0100 @@ -19,15 +19,20 @@ #include #include #include +#include +#include #include "core.h" #include "debug.h" #include "hif.h" +#include "htt.h" #include "wmi-ops.h" /* ms */ #define ATH10K_DEBUG_HTT_STATS_INTERVAL 1000 +#define ATH10K_DEBUG_CAL_DATA_LEN 12064 + #define ATH10K_FW_CRASH_DUMP_VERSION 1 /** @@ -122,43 +127,73 @@ } EXPORT_SYMBOL(ath10k_info); -void ath10k_print_driver_info(struct ath10k *ar) +void ath10k_debug_print_hwfw_info(struct ath10k *ar) { + const struct firmware *firmware; char fw_features[128] = {}; - char boardinfo[100]; + u32 crc = 0; ath10k_core_get_fw_features_str(ar, fw_features, sizeof(fw_features)); - if (ar->id.bmi_ids_valid) - scnprintf(boardinfo, sizeof(boardinfo), "bmi %d:%d", - ar->id.bmi_chip_id, ar->id.bmi_board_id); - else - scnprintf(boardinfo, sizeof(boardinfo), "sub %04x:%04x", - ar->id.subsystem_vendor, ar->id.subsystem_device); - - ath10k_info(ar, "%s (0x%08x, 0x%08x %s) fw %s fwapi %d bdapi %d htt-ver %d.%d wmi-op %d htt-op %d cal %s max-sta %d raw %d hwcrypto %d features %s\n", + ath10k_info(ar, "%s target 0x%08x chip_id 0x%08x sub %04x:%04x", ar->hw_params.name, ar->target_version, ar->chip_id, - boardinfo, + ar->id.subsystem_vendor, ar->id.subsystem_device); + + ath10k_info(ar, "kconfig debug %d debugfs %d tracing %d dfs %d testmode %d\n", + IS_ENABLED(CONFIG_ATH10K_DEBUG), + IS_ENABLED(CONFIG_ATH10K_DEBUGFS), + IS_ENABLED(CONFIG_ATH10K_TRACING), + IS_ENABLED(CONFIG_ATH10K_DFS_CERTIFIED), + IS_ENABLED(CONFIG_NL80211_TESTMODE)); + + firmware = ar->normal_mode_fw.fw_file.firmware; + if (firmware) + crc = crc32_le(0, firmware->data, firmware->size); + + ath10k_info(ar, "firmware ver %s api %d features %s crc32 %08x\n", ar->hw->wiphy->fw_version, ar->fw_api, + fw_features, + crc); +} + +void ath10k_debug_print_board_info(struct ath10k *ar) +{ + char boardinfo[100]; + + if (ar->id.bmi_ids_valid) + scnprintf(boardinfo, sizeof(boardinfo), "%d:%d", + ar->id.bmi_chip_id, ar->id.bmi_board_id); + else + scnprintf(boardinfo, sizeof(boardinfo), "N/A"); + + ath10k_info(ar, "board_file api %d bmi_id %s crc32 %08x", ar->bd_api, + boardinfo, + crc32_le(0, ar->normal_mode_fw.board->data, + ar->normal_mode_fw.board->size)); +} + +void ath10k_debug_print_boot_info(struct ath10k *ar) +{ + ath10k_info(ar, "htt-ver %d.%d wmi-op %d htt-op %d cal %s max-sta %d raw %d hwcrypto %d\n", ar->htt.target_version_major, ar->htt.target_version_minor, - ar->wmi.op_version, - ar->htt.op_version, + ar->normal_mode_fw.fw_file.wmi_op_version, + ar->normal_mode_fw.fw_file.htt_op_version, ath10k_cal_mode_str(ar->cal_mode), ar->max_num_stations, test_bit(ATH10K_FLAG_RAW_MODE, &ar->dev_flags), - !test_bit(ATH10K_FLAG_HW_CRYPTO_DISABLED, &ar->dev_flags), - fw_features); - ath10k_info(ar, "debug %d debugfs %d tracing %d dfs %d testmode %d\n", - config_enabled(CONFIG_ATH10K_DEBUG), - config_enabled(CONFIG_ATH10K_DEBUGFS), - config_enabled(CONFIG_ATH10K_TRACING), - config_enabled(CONFIG_ATH10K_DFS_CERTIFIED), - config_enabled(CONFIG_NL80211_TESTMODE)); + !test_bit(ATH10K_FLAG_HW_CRYPTO_DISABLED, &ar->dev_flags)); +} + +void ath10k_print_driver_info(struct ath10k *ar) +{ + ath10k_debug_print_hwfw_info(ar); + ath10k_debug_print_board_info(ar); + ath10k_debug_print_boot_info(ar); } EXPORT_SYMBOL(ath10k_print_driver_info); @@ -251,7 +286,7 @@ .llseek = default_llseek, }; -static void ath10k_debug_fw_stats_pdevs_free(struct list_head *head) +static void ath10k_fw_stats_pdevs_free(struct list_head *head) { struct ath10k_fw_stats_pdev *i, *tmp; @@ -261,7 +296,7 @@ } } -static void ath10k_debug_fw_stats_vdevs_free(struct list_head *head) +static void ath10k_fw_stats_vdevs_free(struct list_head *head) { struct ath10k_fw_stats_vdev *i, *tmp; @@ -271,7 +306,7 @@ } } -static void ath10k_debug_fw_stats_peers_free(struct list_head *head) +static void ath10k_fw_stats_peers_free(struct list_head *head) { struct ath10k_fw_stats_peer *i, *tmp; @@ -281,13 +316,25 @@ } } +static void ath10k_fw_extd_stats_peers_free(struct list_head *head) +{ + struct ath10k_fw_extd_stats_peer *i, *tmp; + + list_for_each_entry_safe(i, tmp, head, list) { + list_del(&i->list); + kfree(i); + } +} + static void ath10k_debug_fw_stats_reset(struct ath10k *ar) { spin_lock_bh(&ar->data_lock); ar->debug.fw_stats_done = false; - ath10k_debug_fw_stats_pdevs_free(&ar->debug.fw_stats.pdevs); - ath10k_debug_fw_stats_vdevs_free(&ar->debug.fw_stats.vdevs); - ath10k_debug_fw_stats_peers_free(&ar->debug.fw_stats.peers); + ar->debug.fw_stats.extended = false; + ath10k_fw_stats_pdevs_free(&ar->debug.fw_stats.pdevs); + ath10k_fw_stats_vdevs_free(&ar->debug.fw_stats.vdevs); + ath10k_fw_stats_peers_free(&ar->debug.fw_stats.peers); + ath10k_fw_extd_stats_peers_free(&ar->debug.fw_stats.peers_extd); spin_unlock_bh(&ar->data_lock); } @@ -302,6 +349,7 @@ INIT_LIST_HEAD(&stats.pdevs); INIT_LIST_HEAD(&stats.vdevs); INIT_LIST_HEAD(&stats.peers); + INIT_LIST_HEAD(&stats.peers_extd); spin_lock_bh(&ar->data_lock); ret = ath10k_wmi_pull_fw_stats(ar, skb, &stats); @@ -321,9 +369,13 @@ * b) consume stat update events until another one with pdev stats is * delivered which is treated as end-of-data and is itself discarded */ + if (ath10k_peer_stats_enabled(ar)) + ath10k_sta_update_rx_duration(ar, &stats); if (ar->debug.fw_stats_done) { + if (!ath10k_peer_stats_enabled(ar)) ath10k_warn(ar, "received unsolicited stats update event\n"); + goto free; } @@ -347,17 +399,21 @@ /* Although this is unlikely impose a sane limit to * prevent firmware from DoS-ing the host. */ + ath10k_fw_stats_peers_free(&ar->debug.fw_stats.peers); ath10k_warn(ar, "dropping fw peer stats\n"); goto free; } if (num_vdevs >= BITS_PER_LONG) { + ath10k_fw_stats_vdevs_free(&ar->debug.fw_stats.vdevs); ath10k_warn(ar, "dropping fw vdev stats\n"); goto free; } list_splice_tail_init(&stats.peers, &ar->debug.fw_stats.peers); list_splice_tail_init(&stats.vdevs, &ar->debug.fw_stats.vdevs); + list_splice_tail_init(&stats.peers_extd, + &ar->debug.fw_stats.peers_extd); } complete(&ar->debug.fw_stats_complete); @@ -366,9 +422,10 @@ /* In some cases lists have been spliced and cleared. Free up * resources if that is not the case. */ - ath10k_debug_fw_stats_pdevs_free(&stats.pdevs); - ath10k_debug_fw_stats_vdevs_free(&stats.vdevs); - ath10k_debug_fw_stats_peers_free(&stats.peers); + ath10k_fw_stats_pdevs_free(&stats.pdevs); + ath10k_fw_stats_vdevs_free(&stats.vdevs); + ath10k_fw_stats_peers_free(&stats.peers); + ath10k_fw_extd_stats_peers_free(&stats.peers_extd); spin_unlock_bh(&ar->data_lock); } @@ -481,6 +538,230 @@ .llseek = default_llseek, }; +static inline int is_vht_rate_valid(u32 rate_indx) +{ + if ((rate_indx >= ATH10K_RX_MCS_MIN) && + (rate_indx <= ATH10K_RX_VHT_RATEIDX_MAX)) + return 1; + else + return 0; +} + +void fill_datapath_stats(struct ath10k *ar, struct ieee80211_rx_status *status) +{ + struct datapath_rx_stats *stat_cnt = ar->rx_stats; + + spin_lock_bh(&ar->datapath_rx_stat_lock); + + stat_cnt->no_of_packets += 1; + if (!(stat_cnt->no_of_packets)) { + memset(stat_cnt, 0, sizeof(*stat_cnt)); + stat_cnt->no_of_packets += 1; + } + + if (status->flag & RX_FLAG_SHORT_GI) + stat_cnt->short_gi_pkts += 1; + + if ((status->vht_nss >= ATH10K_RX_NSS_MIN) && + (status->vht_nss < ATH10K_RX_NSS_MAX)) { + stat_cnt->nss[status->vht_nss] += 1; + if (status->flag & RX_FLAG_VHT) { + stat_cnt->vht_rate_packets += 1; + if (is_vht_rate_valid(status->rate_idx)) { + stat_cnt->vht_rate_indx[((status->vht_nss - 1) * + 10) + status->rate_idx] += 1; + } else { + /*if we get index other than (>=0 and <=9)*/ + stat_cnt->vht_rate_indx[ATH10K_RX_VHT_MCS_MAX] += 1; + } + } else if (status->flag & RX_FLAG_HT) { + stat_cnt->ht_rate_packets += 1; + if ((status->rate_idx >= ATH10K_RX_MCS_MIN) && + (status->rate_idx < ATH10K_RX_HT_MCS_MAX)) + stat_cnt->ht_rate_indx[status->rate_idx] += 1; + else { + /*if we get index other than (>=0 and <=31)*/ + stat_cnt->ht_rate_indx[ATH10K_RX_HT_MCS_MAX] += 1; + } + } else { + /* if pkt is other than HT and VHT */ + stat_cnt->legacy_pkt += 1; + } + } else { + stat_cnt->nss[ATH10K_RX_NSS_MAX] += 1; + } + + if (status->flag & RX_FLAG_40MHZ) + stat_cnt->num_pkts_40Mhz += 1; + if (status->vht_flag & RX_VHT_FLAG_80MHZ) + stat_cnt->num_pkts_80Mhz += 1; + if ((status->band >= ATH10K_BAND_MIN) && + (status->band < ATH10K_BAND_MAX)) { + stat_cnt->band[status->band] += 1; + } else { + /*if band is other than 0,1 */ + stat_cnt->band[ATH10K_BAND_MAX] += 1; + } + + spin_unlock_bh(&ar->datapath_rx_stat_lock); +} + +size_t get_datapath_stat(char *buf, struct ath10k *ar) +{ + u8 i; + struct datapath_rx_stats *stat_cnt = ar->rx_stats; + size_t j = 0; + + spin_lock(&ar->datapath_rx_stat_lock); + + j = snprintf(buf, ATH10K_DATAPATH_BUF_SIZE, "\nNo of packets: %u\t" + "No of short_gi packets: %u\n" + "\nHT Packets: %u \t VHT Packets: %u\n" + "\n40Mhz Packets: %u \t 80Mhz Packets: %u\n" + "\n2.4GHz: %u \t 5GHz: %u \t band-error: %u\n\n", + stat_cnt->no_of_packets, + stat_cnt->short_gi_pkts, + stat_cnt->ht_rate_packets, + stat_cnt->vht_rate_packets, + stat_cnt->num_pkts_40Mhz, + stat_cnt->num_pkts_80Mhz, + stat_cnt->band[ATH10K_BAND_2GHZ], + stat_cnt->band[ATH10K_BAND_5GHZ], + stat_cnt->band[ATH10K_BAND_MAX]); + + for (i = 0; i <= ATH10K_RX_NSS_MAX; i++) { + j += snprintf(buf + j, (ATH10K_DATAPATH_BUF_SIZE - j), + "NSS-%u: %u\t", i, stat_cnt->nss[i]); + } + + j += snprintf(buf + j, (ATH10K_DATAPATH_BUF_SIZE - j), + "\n\n----HT Rate index------\n"); + + for (i = ATH10K_RX_MCS_MIN; i < ATH10K_RX_HT_MCS_MAX; + i += 4) { + j += snprintf(buf + j, (ATH10K_DATAPATH_BUF_SIZE - j), + "ht_rate_indx[%02u]: %10u\tht_rate_indx[%02u]: %10u\t" + "ht_rate_indx[%02u]: %10u\tht_rate_indx[%02u]: %10u\n", + i, stat_cnt->ht_rate_indx[i], + i + 1, stat_cnt->ht_rate_indx[i + 1], + i + 2, stat_cnt->ht_rate_indx[i + 2], + i + 3, stat_cnt->ht_rate_indx[i + 3]); + } + + j += snprintf(buf + j, (ATH10K_DATAPATH_BUF_SIZE - j), + "ht_rate_indx[OOB]: %10u\n", + stat_cnt->ht_rate_indx[ATH10K_RX_HT_MCS_MAX]); + + j += snprintf(buf + j, (ATH10K_DATAPATH_BUF_SIZE - j), + "\n----VHT Rate index------\n"); + + for (i = ATH10K_RX_MCS_MIN; + i <= ATH10K_RX_VHT_RATEIDX_MAX; i++) { + j += snprintf(buf + j, (ATH10K_DATAPATH_BUF_SIZE - j), + "vht_rate_indx[%02u]: %10u\tvht_rate_indx[%02u]: %10u\n", + i, stat_cnt->vht_rate_indx[i], + i + 10, stat_cnt->vht_rate_indx[i + 10]); + } + + j += snprintf(buf + j, (ATH10K_DATAPATH_BUF_SIZE - j), + "vht_rate_indx[%02u]: %10u\n", + i + 10, stat_cnt->vht_rate_indx[i + 10]); + + j += snprintf(buf + j, (ATH10K_DATAPATH_BUF_SIZE - j), + "\nnumber of pkt other than HT and VHT(legacy) : %u\n" + "----------------------\n", + stat_cnt->legacy_pkt); + + spin_unlock(&ar->datapath_rx_stat_lock); + + return j; +} + +static int ath10k_datapath_stats_open(struct inode *inode, struct file *file) +{ + struct ath10k *ar = inode->i_private; + int ret; + + spin_lock(&ar->datapath_rx_stat_lock); + + if (ar->state != ATH10K_STATE_ON) { + ret = -ENETDOWN; + goto err_unlock; + } + + file->private_data = ar; + + spin_unlock(&ar->datapath_rx_stat_lock); + return 0; + +err_unlock: + spin_unlock(&ar->datapath_rx_stat_lock); + return ret; +} + +static ssize_t ath10k_datapath_stats_read(struct file *file, + char __user *user_buf, + size_t count, loff_t *ppos) +{ + struct ath10k *ar = file->private_data; + size_t buf_len; + unsigned int ret; + void *buf = NULL; + + buf = vmalloc(ATH10K_DATAPATH_BUF_SIZE); + if (!buf) + return 0; + + buf_len = get_datapath_stat(buf, ar); + + ret = simple_read_from_buffer(user_buf, count, ppos, buf, buf_len); + vfree(buf); + + return ret; +} + +static ssize_t ath10k_datapath_stats_write(struct file *file, + const char __user *ubuf, + size_t count, loff_t *ppos) +{ + struct ath10k *ar = file->private_data; + u32 filter; + int ret; + + if (kstrtouint_from_user(ubuf, count, 0, &filter)) + return -EINVAL; + + spin_lock(&ar->datapath_rx_stat_lock); + + if (ar->state != ATH10K_STATE_ON) { + ret = count; + goto err_unlock; + } + + if (!filter) + memset(ar->rx_stats, 0, sizeof(*ar->rx_stats)); + + ret = count; + +err_unlock: + spin_unlock(&ar->datapath_rx_stat_lock); + return ret; +} + +static int ath10k_datapath_stats_release(struct inode *inode, struct file *file) +{ + return 0; +} + +static const struct file_operations fops_datapath_stats = { + .open = ath10k_datapath_stats_open, + .read = ath10k_datapath_stats_read, + .write = ath10k_datapath_stats_write, + .release = ath10k_datapath_stats_release, + .owner = THIS_MODULE, + .llseek = default_llseek, +}; + static ssize_t ath10k_debug_fw_reset_stats_read(struct file *file, char __user *user_buf, size_t count, loff_t *ppos) @@ -571,25 +852,23 @@ char buf[32]; int ret; - mutex_lock(&ar->conf_mutex); - simple_write_to_buffer(buf, sizeof(buf) - 1, ppos, user_buf, count); /* make sure that buf is null terminated */ buf[sizeof(buf) - 1] = 0; + /* drop the possible '\n' from the end */ + if (buf[count - 1] == '\n') + buf[count - 1] = 0; + + mutex_lock(&ar->conf_mutex); + if (ar->state != ATH10K_STATE_ON && ar->state != ATH10K_STATE_RESTARTED) { ret = -ENETDOWN; goto exit; } - /* drop the possible '\n' from the end */ - if (buf[count - 1] == '\n') { - buf[count - 1] = 0; - count--; - } - if (!strcmp(buf, "soft")) { ath10k_info(ar, "simulating soft firmware crash\n"); ret = ath10k_wmi_force_fw_hang(ar, WMI_FORCE_FW_HANG_ASSERT, 0); @@ -1114,7 +1393,7 @@ { struct ath10k *ar = file->private_data; char buf[64]; - u8 amsdu = 3, ampdu = 64; + u8 amsdu, ampdu; unsigned int len; mutex_lock(&ar->conf_mutex); @@ -1176,9 +1455,9 @@ { struct ath10k *ar = file->private_data; unsigned int len; - char buf[64]; + char buf[96]; - len = scnprintf(buf, sizeof(buf), "0x%08x %u\n", + len = scnprintf(buf, sizeof(buf), "0x%16llx %u\n", ar->debug.fw_dbglog_mask, ar->debug.fw_dbglog_level); return simple_read_from_buffer(user_buf, count, ppos, buf, len); @@ -1190,15 +1469,16 @@ { struct ath10k *ar = file->private_data; int ret; - char buf[64]; - unsigned int log_level, mask; + char buf[96]; + unsigned int log_level; + u64 mask; simple_write_to_buffer(buf, sizeof(buf) - 1, ppos, user_buf, count); /* make sure that buf is null terminated */ buf[sizeof(buf) - 1] = 0; - ret = sscanf(buf, "%x %u", &mask, &log_level); + ret = sscanf(buf, "%llx %u", &mask, &log_level); if (!ret) return -EINVAL; @@ -1398,74 +1678,68 @@ .llseek = default_llseek, }; -static int ath10k_debug_cal_data_open(struct inode *inode, struct file *file) +static int ath10k_debug_cal_data_fetch(struct ath10k *ar) { - struct ath10k *ar = inode->i_private; - void *buf; u32 hi_addr; __le32 addr; int ret; - mutex_lock(&ar->conf_mutex); - - if (ar->state != ATH10K_STATE_ON && - ar->state != ATH10K_STATE_UTF) { - ret = -ENETDOWN; - goto err; - } + lockdep_assert_held(&ar->conf_mutex); - buf = vmalloc(QCA988X_CAL_DATA_LEN); - if (!buf) { - ret = -ENOMEM; - goto err; - } + if (WARN_ON(ar->hw_params.cal_data_len > ATH10K_DEBUG_CAL_DATA_LEN)) + return -EINVAL; hi_addr = host_interest_item_address(HI_ITEM(hi_board_data)); ret = ath10k_hif_diag_read(ar, hi_addr, &addr, sizeof(addr)); if (ret) { - ath10k_warn(ar, "failed to read hi_board_data address: %d\n", ret); - goto err_vfree; + ath10k_warn(ar, "failed to read hi_board_data address: %d\n", + ret); + return ret; } - ret = ath10k_hif_diag_read(ar, le32_to_cpu(addr), buf, - QCA988X_CAL_DATA_LEN); + ret = ath10k_hif_diag_read(ar, le32_to_cpu(addr), ar->debug.cal_data, + ar->hw_params.cal_data_len); if (ret) { ath10k_warn(ar, "failed to read calibration data: %d\n", ret); - goto err_vfree; + return ret; } - file->private_data = buf; + return 0; +} - mutex_unlock(&ar->conf_mutex); +static int ath10k_debug_cal_data_open(struct inode *inode, struct file *file) +{ + struct ath10k *ar = inode->i_private; - return 0; + mutex_lock(&ar->conf_mutex); -err_vfree: - vfree(buf); + if (ar->state == ATH10K_STATE_ON || + ar->state == ATH10K_STATE_UTF) { + ath10k_debug_cal_data_fetch(ar); + } -err: + file->private_data = ar; mutex_unlock(&ar->conf_mutex); - return ret; + return 0; } static ssize_t ath10k_debug_cal_data_read(struct file *file, char __user *user_buf, size_t count, loff_t *ppos) { - void *buf = file->private_data; + struct ath10k *ar = file->private_data; - return simple_read_from_buffer(user_buf, count, ppos, - buf, QCA988X_CAL_DATA_LEN); -} + mutex_lock(&ar->conf_mutex); -static int ath10k_debug_cal_data_release(struct inode *inode, - struct file *file) -{ - vfree(file->private_data); + count = simple_read_from_buffer(user_buf, count, ppos, + ar->debug.cal_data, + ar->hw_params.cal_data_len); - return 0; + mutex_unlock(&ar->conf_mutex); + + return count; } static ssize_t ath10k_write_ani_enable(struct file *file, @@ -1523,10 +1797,67 @@ .llseek = default_llseek, }; +static ssize_t ath10k_write_sifs_burst_enable(struct file *file, + const char __user *user_buf, + size_t count, loff_t *ppos) +{ + struct ath10k *ar = file->private_data; + int ret; + u8 enable; + + if (kstrtou8_from_user(user_buf, count, 0, &enable)) + return -EINVAL; + + mutex_lock(&ar->conf_mutex); + + if (ar->sifs_burst_enabled == enable) { + ret = count; + goto exit; + } + + ret = ath10k_wmi_pdev_set_param(ar, ar->wmi.pdev_param->burst_enable, + enable); + if (ret) { + ath10k_warn(ar, "sifs_burst_enable failed: %d\n", ret); + goto exit; + } + ar->sifs_burst_enabled = enable; + + ret = count; + +exit: + mutex_unlock(&ar->conf_mutex); + + return ret; +} + +static ssize_t ath10k_read_sifs_burst_enable(struct file *file, + char __user *user_buf, + size_t count, loff_t *ppos) +{ + struct ath10k *ar = file->private_data; + char buf[32]; + int len; + bool ret = false; + + if (ar->sifs_burst_enabled) + ret = true; + + len = scnprintf(buf, sizeof(buf), "%d\n", ret); + return simple_read_from_buffer(user_buf, count, ppos, buf, len); +} + +static const struct file_operations fops_sifs_burst_enable = { + .read = ath10k_read_sifs_burst_enable, + .write = ath10k_write_sifs_burst_enable, + .open = simple_open, + .owner = THIS_MODULE, + .llseek = default_llseek, +}; + static const struct file_operations fops_cal_data = { .open = ath10k_debug_cal_data_open, .read = ath10k_debug_cal_data_read, - .release = ath10k_debug_cal_data_release, .owner = THIS_MODULE, .llseek = default_llseek, }; @@ -1861,7 +2192,7 @@ ath10k_warn(ar, "failed to disable pktlog: %d\n", ret); } - if (ar->debug.nf_cal_period) { + if (ar->debug.nf_cal_period && !QCA_REV_WCN3990(ar)) { ret = ath10k_wmi_pdev_set_param(ar, ar->wmi.pdev_param->cal_period, ar->debug.nf_cal_period); @@ -1878,6 +2209,9 @@ { lockdep_assert_held(&ar->conf_mutex); + if (!QCA_REV_WCN3990(ar)) + ath10k_debug_cal_data_fetch(ar); + /* Must not use _sync to avoid deadlock, we do that in * ath10k_debug_destroy(). The check for htt_stats_mask is to avoid * warning from del_timer(). */ @@ -2079,17 +2413,410 @@ .open = simple_open }; +static ssize_t ath10k_write_btcoex(struct file *file, + const char __user *ubuf, + size_t count, loff_t *ppos) +{ + struct ath10k *ar = file->private_data; + char buf[32]; + size_t buf_size; + int ret; + bool val; + u32 pdev_param; + + buf_size = min(count, (sizeof(buf) - 1)); + if (copy_from_user(buf, ubuf, buf_size)) + return -EFAULT; + + buf[buf_size] = '\0'; + + if (strtobool(buf, &val) != 0) + return -EINVAL; + + mutex_lock(&ar->conf_mutex); + + if (ar->state != ATH10K_STATE_ON && + ar->state != ATH10K_STATE_RESTARTED) { + ret = -ENETDOWN; + goto exit; + } + + if (!(test_bit(ATH10K_FLAG_BTCOEX, &ar->dev_flags) ^ val)) { + ret = count; + goto exit; + } + + pdev_param = ar->wmi.pdev_param->enable_btcoex; + if (test_bit(ATH10K_FW_FEATURE_BTCOEX_PARAM, + ar->running_fw->fw_file.fw_features)) { + ret = ath10k_wmi_pdev_set_param(ar, pdev_param, val); + if (ret) { + ath10k_warn(ar, "failed to enable btcoex: %d\n", ret); + ret = count; + goto exit; + } + } else { + ath10k_info(ar, "restarting firmware due to btcoex change"); + queue_work(ar->workqueue, &ar->restart_work); + } + + if (val) + set_bit(ATH10K_FLAG_BTCOEX, &ar->dev_flags); + else + clear_bit(ATH10K_FLAG_BTCOEX, &ar->dev_flags); + + ret = count; + +exit: + mutex_unlock(&ar->conf_mutex); + + return ret; +} + +static ssize_t ath10k_read_btcoex(struct file *file, char __user *ubuf, + size_t count, loff_t *ppos) +{ + char buf[32]; + struct ath10k *ar = file->private_data; + int len = 0; + + mutex_lock(&ar->conf_mutex); + len = scnprintf(buf, sizeof(buf) - len, "%d\n", + test_bit(ATH10K_FLAG_BTCOEX, &ar->dev_flags)); + mutex_unlock(&ar->conf_mutex); + + return simple_read_from_buffer(ubuf, count, ppos, buf, len); +} + +static const struct file_operations fops_btcoex = { + .read = ath10k_read_btcoex, + .write = ath10k_write_btcoex, + .open = simple_open +}; + +static ssize_t ath10k_write_peer_stats(struct file *file, + const char __user *ubuf, + size_t count, loff_t *ppos) +{ + struct ath10k *ar = file->private_data; + char buf[32]; + size_t buf_size; + int ret; + bool val; + + buf_size = min(count, (sizeof(buf) - 1)); + if (copy_from_user(buf, ubuf, buf_size)) + return -EFAULT; + + buf[buf_size] = '\0'; + + if (strtobool(buf, &val) != 0) + return -EINVAL; + + mutex_lock(&ar->conf_mutex); + + if (ar->state != ATH10K_STATE_ON && + ar->state != ATH10K_STATE_RESTARTED) { + ret = -ENETDOWN; + goto exit; + } + + if (!(test_bit(ATH10K_FLAG_PEER_STATS, &ar->dev_flags) ^ val)) { + ret = count; + goto exit; + } + + if (val) + set_bit(ATH10K_FLAG_PEER_STATS, &ar->dev_flags); + else + clear_bit(ATH10K_FLAG_PEER_STATS, &ar->dev_flags); + + ath10k_info(ar, "restarting firmware due to Peer stats change"); + + queue_work(ar->workqueue, &ar->restart_work); + ret = count; + +exit: + mutex_unlock(&ar->conf_mutex); + return ret; +} + +static ssize_t ath10k_read_peer_stats(struct file *file, char __user *ubuf, + size_t count, loff_t *ppos) + +{ + char buf[32]; + struct ath10k *ar = file->private_data; + int len = 0; + + mutex_lock(&ar->conf_mutex); + len = scnprintf(buf, sizeof(buf) - len, "%d\n", + test_bit(ATH10K_FLAG_PEER_STATS, &ar->dev_flags)); + mutex_unlock(&ar->conf_mutex); + + return simple_read_from_buffer(ubuf, count, ppos, buf, len); +} + +static const struct file_operations fops_peer_stats = { + .read = ath10k_read_peer_stats, + .write = ath10k_write_peer_stats, + .open = simple_open +}; + +static ssize_t ath10k_debug_fw_checksums_read(struct file *file, + char __user *user_buf, + size_t count, loff_t *ppos) +{ + struct ath10k *ar = file->private_data; + unsigned int len = 0, buf_len = 4096; + ssize_t ret_cnt; + char *buf; + + buf = kzalloc(buf_len, GFP_KERNEL); + if (!buf) + return -ENOMEM; + + mutex_lock(&ar->conf_mutex); + + len += scnprintf(buf + len, buf_len - len, + "firmware-N.bin\t\t%08x\n", + crc32_le(0, ar->normal_mode_fw.fw_file.firmware->data, + ar->normal_mode_fw.fw_file.firmware->size)); + len += scnprintf(buf + len, buf_len - len, + "athwlan\t\t\t%08x\n", + crc32_le(0, ar->normal_mode_fw.fw_file.firmware_data, + ar->normal_mode_fw.fw_file.firmware_len)); + len += scnprintf(buf + len, buf_len - len, + "otp\t\t\t%08x\n", + crc32_le(0, ar->normal_mode_fw.fw_file.otp_data, + ar->normal_mode_fw.fw_file.otp_len)); + len += scnprintf(buf + len, buf_len - len, + "codeswap\t\t%08x\n", + crc32_le(0, ar->normal_mode_fw.fw_file.codeswap_data, + ar->normal_mode_fw.fw_file.codeswap_len)); + len += scnprintf(buf + len, buf_len - len, + "board-N.bin\t\t%08x\n", + crc32_le(0, ar->normal_mode_fw.board->data, + ar->normal_mode_fw.board->size)); + len += scnprintf(buf + len, buf_len - len, + "board\t\t\t%08x\n", + crc32_le(0, ar->normal_mode_fw.board_data, + ar->normal_mode_fw.board_len)); + + ret_cnt = simple_read_from_buffer(user_buf, count, ppos, buf, len); + + mutex_unlock(&ar->conf_mutex); + + kfree(buf); + return ret_cnt; +} + +static const struct file_operations fops_fw_checksums = { + .read = ath10k_debug_fw_checksums_read, + .open = simple_open, + .owner = THIS_MODULE, + .llseek = default_llseek, +}; + +static struct txctl_frm_hdr frm_hdr; + +static void ath10k_extract_frame_header(u8 *addr1, u8 *addr2, u8 *addr3) +{ + frm_hdr.bssid_tail = (addr1[IEEE80211_ADDR_LEN - 2] << BITS_PER_BYTE) + | (addr1[IEEE80211_ADDR_LEN - 1]); + frm_hdr.sa_tail = (addr2[IEEE80211_ADDR_LEN - 2] << BITS_PER_BYTE) + | (addr2[IEEE80211_ADDR_LEN - 1]); + frm_hdr.da_tail = (addr3[IEEE80211_ADDR_LEN - 2] << BITS_PER_BYTE) + | (addr3[IEEE80211_ADDR_LEN - 1]); +} + +static void ath10k_process_ieee_hdr(void *data) +{ + u8 dir; + struct ieee80211_frame *wh; + + if (!data) + return; + + wh = (struct ieee80211_frame *)(data); + frm_hdr.framectrl = *(u_int16_t *)(wh->i_fc); + frm_hdr.seqctrl = *(u_int16_t *)(wh->i_seq); + dir = (wh->i_fc[1] & IEEE80211_FC1_DIR_MASK); + + if (dir == IEEE80211_FC1_DIR_TODS) + ath10k_extract_frame_header(wh->i_addr1, wh->i_addr2, + wh->i_addr3); + else if (dir == IEEE80211_FC1_DIR_FROMDS) + ath10k_extract_frame_header(wh->i_addr2, wh->i_addr3, + wh->i_addr1); + else + ath10k_extract_frame_header(wh->i_addr3, wh->i_addr2, + wh->i_addr1); +} + +static void ath10k_pktlog_process_rx(struct ath10k *ar, struct sk_buff *skb) +{ + struct ath10k_pktlog_hdr *hdr = (void *)skb->data; + struct ath_pktlog_txctl pktlog_tx_ctrl; + + switch (hdr->log_type) { + case ATH10K_PKTLOG_TYPE_TX_CTRL: { + spin_lock_bh(&ar->htt.tx_lock); + + memcpy((void *)(&pktlog_tx_ctrl.hdr), (void *)hdr, + sizeof(pktlog_tx_ctrl.hdr)); + pktlog_tx_ctrl.frm_hdr = frm_hdr; + memcpy((void *)pktlog_tx_ctrl.txdesc_ctl, (void *)hdr->payload, + __le16_to_cpu(hdr->size)); + pktlog_tx_ctrl.hdr.size = sizeof(pktlog_tx_ctrl) - + sizeof(pktlog_tx_ctrl.hdr); + + spin_unlock_bh(&ar->htt.tx_lock); + + trace_ath10k_htt_pktlog(ar, (void *)&pktlog_tx_ctrl, + sizeof(pktlog_tx_ctrl)); + break; + } + case ATH10K_PKTLOG_TYPE_TX_MSDU_ID: + break; + case ATH10K_PKTLOG_TYPE_TX_FRM_HDR: { + ath10k_process_ieee_hdr((void *)(hdr->payload)); + trace_ath10k_htt_pktlog(ar, hdr, sizeof(*hdr) + + __le16_to_cpu(hdr->size)); + break; + } + case ATH10K_PKTLOG_TYPE_RX_STAT: + case ATH10K_PKTLOG_TYPE_RC_FIND: + case ATH10K_PKTLOG_TYPE_RC_UPDATE: + case ATH10K_PKTLOG_TYPE_DBG_PRINT: + case ATH10K_PKTLOG_TYPE_TX_STAT: + case ATH10K_PKTLOG_TYPE_SW_EVENT: + trace_ath10k_htt_pktlog(ar, hdr, sizeof(*hdr) + + __le16_to_cpu(hdr->size)); + break; + case ATH10K_PKTLOG_TYPE_TX_VIRT_ADDR: { + u32 desc_id = (u32)*((u32 *)(hdr->payload)); + struct sk_buff *msdu; + + spin_lock_bh(&ar->htt.tx_lock); + msdu = ath10k_htt_tx_find_msdu_by_id(&ar->htt, desc_id); + + if (!msdu) { + ath10k_info(ar, + "Failed to get msdu, id: %d\n", + desc_id); + spin_unlock_bh(&ar->htt.tx_lock); + return; + } + ath10k_process_ieee_hdr((void *)msdu->data); + spin_unlock_bh(&ar->htt.tx_lock); + trace_ath10k_htt_pktlog(ar, hdr, sizeof(*hdr) + + __le16_to_cpu(hdr->size)); + break; + } + } +} + +int ath10k_rx_record_pktlog(struct ath10k *ar, struct sk_buff *skb) +{ + struct sk_buff *pktlog_skb; + struct ath_pktlog_hdr *pl_hdr; + struct ath_pktlog_rx_info *pktlog_rx_info; + struct htt_rx_desc *rx_desc = (void *)skb->data - sizeof(*rx_desc); + + if (!ar->debug.pktlog_filter) + return 0; + + pktlog_skb = dev_alloc_skb(sizeof(struct ath_pktlog_hdr) + + sizeof(struct htt_rx_desc) - + sizeof(struct htt_host_fw_desc_base)); + if (!pktlog_skb) + return -ENOMEM; + + pktlog_rx_info = (struct ath_pktlog_rx_info *)pktlog_skb->data; + pl_hdr = &pktlog_rx_info->pl_hdr; + + pl_hdr->flags = (1 << ATH10K_PKTLOG_FLG_FRM_TYPE_REMOTE_S); + pl_hdr->missed_cnt = 0; + pl_hdr->mac_id = 0; + pl_hdr->log_type = ATH10K_PKTLOG_TYPE_RX_STAT; + pl_hdr->flags |= ATH10K_PKTLOG_HDR_SIZE_16; + pl_hdr->size = sizeof(*rx_desc) - + sizeof(struct htt_host_fw_desc_base); + + pl_hdr->timestamp = + cpu_to_le32(rx_desc->ppdu_end.wcn3990.rx_pkt_end.phy_timestamp_1); + + pl_hdr->type_specific_data = 0xDEADAA; + memcpy((void *)pktlog_rx_info + sizeof(struct ath_pktlog_hdr), + (void *)rx_desc + sizeof(struct htt_host_fw_desc_base), + pl_hdr->size); + + ath10k_pktlog_process_rx(ar, pktlog_skb); + dev_kfree_skb_any(pktlog_skb); + return 0; +} + +static void ath10k_pktlog_htc_tx_complete(struct ath10k *ar, + struct sk_buff *skb) +{ + ath10k_info(ar, "PKTLOG htc completed\n"); +} + +int ath10k_pktlog_connect(struct ath10k *ar) +{ + int status; + struct ath10k_htc_svc_conn_req conn_req; + struct ath10k_htc_svc_conn_resp conn_resp; + + memset(&conn_req, 0, sizeof(conn_req)); + memset(&conn_resp, 0, sizeof(conn_resp)); + + conn_req.ep_ops.ep_tx_complete = ath10k_pktlog_htc_tx_complete; + conn_req.ep_ops.ep_rx_complete = ath10k_pktlog_process_rx; + conn_req.ep_ops.ep_tx_credits = NULL; + + /* connect to control service */ + conn_req.service_id = ATH10K_HTC_SVC_ID_HTT_LOG_MSG; + status = ath10k_htc_connect_service(&ar->htc, &conn_req, &conn_resp); + if (status) { + ath10k_warn(ar, "failed to connect to PKTLOG service: %d\n", + status); + return status; + } + + ar->debug.eid = conn_resp.eid; + + return 0; +} + int ath10k_debug_create(struct ath10k *ar) { ar->debug.fw_crash_data = vzalloc(sizeof(*ar->debug.fw_crash_data)); if (!ar->debug.fw_crash_data) return -ENOMEM; + ar->debug.cal_data = vzalloc(ATH10K_DEBUG_CAL_DATA_LEN); + if (!ar->debug.cal_data) + goto err_cal_data; + + ar->rx_stats = vzalloc(sizeof(*ar->rx_stats)); + if (!ar->rx_stats) + goto err_rx_stats; + INIT_LIST_HEAD(&ar->debug.fw_stats.pdevs); INIT_LIST_HEAD(&ar->debug.fw_stats.vdevs); INIT_LIST_HEAD(&ar->debug.fw_stats.peers); + INIT_LIST_HEAD(&ar->debug.fw_stats.peers_extd); return 0; + +err_rx_stats: + vfree(ar->debug.cal_data); + +err_cal_data: + vfree(ar->debug.fw_crash_data); + return -ENOMEM; } void ath10k_debug_destroy(struct ath10k *ar) @@ -2097,6 +2824,12 @@ vfree(ar->debug.fw_crash_data); ar->debug.fw_crash_data = NULL; + vfree(ar->debug.cal_data); + ar->debug.cal_data = NULL; + + vfree(ar->rx_stats); + ar->rx_stats = NULL; + ath10k_debug_fw_stats_reset(ar); kfree(ar->debug.tpc_stats); @@ -2119,6 +2852,9 @@ init_completion(&ar->debug.tpc_complete); init_completion(&ar->debug.fw_stats_complete); + debugfs_create_file("datapath_rx_stats", S_IRUSR, ar->debug.debugfs_phy, + ar, &fops_datapath_stats); + debugfs_create_file("fw_stats", S_IRUSR, ar->debug.debugfs_phy, ar, &fops_fw_stats); @@ -2128,8 +2864,8 @@ debugfs_create_file("wmi_services", S_IRUSR, ar->debug.debugfs_phy, ar, &fops_wmi_services); - debugfs_create_file("simulate_fw_crash", S_IRUSR, ar->debug.debugfs_phy, - ar, &fops_simulate_fw_crash); + debugfs_create_file("simulate_fw_crash", S_IRUSR | S_IWUSR, + ar->debug.debugfs_phy, ar, &fops_simulate_fw_crash); debugfs_create_file("fw_crash_dump", S_IRUSR, ar->debug.debugfs_phy, ar, &fops_fw_crash_dump); @@ -2146,26 +2882,32 @@ debugfs_create_file("chip_id", S_IRUSR, ar->debug.debugfs_phy, ar, &fops_chip_id); - debugfs_create_file("htt_stats_mask", S_IRUSR, ar->debug.debugfs_phy, - ar, &fops_htt_stats_mask); + debugfs_create_file("htt_stats_mask", S_IRUSR | S_IWUSR, + ar->debug.debugfs_phy, ar, &fops_htt_stats_mask); debugfs_create_file("htt_max_amsdu_ampdu", S_IRUSR | S_IWUSR, ar->debug.debugfs_phy, ar, &fops_htt_max_amsdu_ampdu); - debugfs_create_file("fw_dbglog", S_IRUSR, ar->debug.debugfs_phy, - ar, &fops_fw_dbglog); + debugfs_create_file("fw_dbglog", S_IRUSR | S_IWUSR, + ar->debug.debugfs_phy, ar, &fops_fw_dbglog); + if (!QCA_REV_WCN3990(ar)) { debugfs_create_file("cal_data", S_IRUSR, ar->debug.debugfs_phy, ar, &fops_cal_data); + debugfs_create_file("nf_cal_period", S_IRUSR | S_IWUSR, + ar->debug.debugfs_phy, ar, + &fops_nf_cal_period); + } + debugfs_create_file("ani_enable", S_IRUSR | S_IWUSR, ar->debug.debugfs_phy, ar, &fops_ani_enable); - debugfs_create_file("nf_cal_period", S_IRUSR | S_IWUSR, - ar->debug.debugfs_phy, ar, &fops_nf_cal_period); + debugfs_create_file("sifs_burst_enable", S_IRUSR | S_IWUSR, + ar->debug.debugfs_phy, ar, &fops_sifs_burst_enable); - if (config_enabled(CONFIG_ATH10K_DFS_CERTIFIED)) { + if (IS_ENABLED(CONFIG_ATH10K_DFS_CERTIFIED)) { debugfs_create_file("dfs_simulate_radar", S_IWUSR, ar->debug.debugfs_phy, ar, &fops_simulate_radar); @@ -2188,6 +2930,18 @@ debugfs_create_file("tpc_stats", S_IRUSR, ar->debug.debugfs_phy, ar, &fops_tpc_stats); + if (test_bit(WMI_SERVICE_COEX_GPIO, ar->wmi.svc_map)) + debugfs_create_file("btcoex", S_IRUGO | S_IWUSR, + ar->debug.debugfs_phy, ar, &fops_btcoex); + + if (test_bit(WMI_SERVICE_PEER_STATS, ar->wmi.svc_map)) + debugfs_create_file("peer_stats", S_IRUGO | S_IWUSR, + ar->debug.debugfs_phy, ar, + &fops_peer_stats); + + debugfs_create_file("fw_checksums", S_IRUSR, + ar->debug.debugfs_phy, ar, &fops_fw_checksums); + return 0; } diff -ruw linux-4.4.115/drivers/net/wireless/ath/ath10k/debug.h linux-4.4.115-fbx/drivers/net/wireless/ath/ath10k/debug.h --- linux-4.4.115/drivers/net/wireless/ath/ath10k/debug.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/net/wireless/ath/ath10k/debug.h 2019-01-22 16:16:25.415263721 +0100 @@ -37,6 +37,8 @@ ATH10K_DBG_TESTMODE = 0x00001000, ATH10K_DBG_WMI_PRINT = 0x00002000, ATH10K_DBG_PCI_PS = 0x00004000, + ATH10K_DBG_AHB = 0x00008000, + ATH10K_DBG_SNOC = 0x00010000, ATH10K_DBG_ANY = 0xffffffff, }; @@ -55,14 +57,97 @@ ATH10K_DBG_AGGR_MODE_MAX, }; +#define IEEE80211_FC1_DIR_MASK 0x03 +#define IEEE80211_FC1_DIR_NODS 0x00 /* STA->STA */ +#define IEEE80211_FC1_DIR_TODS 0x01 /* STA->AP */ +#define IEEE80211_FC1_DIR_FROMDS 0x02 /* AP ->STA */ +#define IEEE80211_FC1_DIR_DSTODS 0x03 /* AP ->AP */ +#define IEEE80211_ADDR_LEN 6 /* size of 802.11 address */ + +#define MAX_PKT_INFO_MSDU_ID 192 +#define MSDU_ID_INFO_ID_OFFSET \ + ((MAX_PKT_INFO_MSDU_ID >> 3) + 4) + +#define PKTLOG_MAX_TXCTL_WORDS 57 /* +2 words for bitmap */ +#define HTT_TX_MSDU_LEN_MASK 0xffff + +struct txctl_frm_hdr { + __le16 framectrl; /* frame control field from header */ + __le16 seqctrl; /* frame control field from header */ + __le16 bssid_tail; /* last two octets of bssid */ + __le16 sa_tail; /* last two octets of SA */ + __le16 da_tail; /* last two octets of DA */ + __le16 resvd; +} __packed; + +struct ath_pktlog_hdr { + __le16 flags; + __le16 missed_cnt; + u8 log_type; + u8 mac_id; + __le16 size; + __le32 timestamp; + __le32 type_specific_data; +} __packed; + +/* generic definitions for IEEE 802.11 frames */ +struct ieee80211_frame { + u8 i_fc[2]; + u8 i_dur[2]; + union { + struct { + u8 i_addr1[IEEE80211_ADDR_LEN]; + u8 i_addr2[IEEE80211_ADDR_LEN]; + u8 i_addr3[IEEE80211_ADDR_LEN]; + }; + u8 i_addr_all[3 * IEEE80211_ADDR_LEN]; + }; + u8 i_seq[2]; +} __packed; + +struct fw_pktlog_msdu_info { + __le32 num_msdu; + u8 bound_bmap[MAX_PKT_INFO_MSDU_ID >> 3]; + __le16 id[MAX_PKT_INFO_MSDU_ID]; +} __packed; + +struct ath_pktlog_txctl { + struct ath_pktlog_hdr hdr; + struct txctl_frm_hdr frm_hdr; + __le32 txdesc_ctl[PKTLOG_MAX_TXCTL_WORDS]; +} __packed; + +struct ath_pktlog_msdu_id { + struct ath_pktlog_hdr hdr; + struct fw_pktlog_msdu_info msdu_info; +} __packed; + +struct ath_pktlog_rx_info { + struct ath_pktlog_hdr pl_hdr; + struct rx_attention attention; + struct rx_frag_info frag_info; + struct rx_mpdu_start mpdu_start; + struct rx_msdu_start msdu_start; + struct rx_msdu_end msdu_end; + struct rx_mpdu_end mpdu_end; + struct rx_ppdu_start ppdu_start; + struct rx_ppdu_end ppdu_end; + u8 rx_hdr_status[RX_HTT_HDR_STATUS_LEN]; +} __packed; + /* FIXME: How to calculate the buffer size sanely? */ #define ATH10K_FW_STATS_BUF_SIZE (1024*1024) +#define ATH10K_DATAPATH_BUF_SIZE (1024 * 1024) extern unsigned int ath10k_debug_mask; __printf(2, 3) void ath10k_info(struct ath10k *ar, const char *fmt, ...); __printf(2, 3) void ath10k_err(struct ath10k *ar, const char *fmt, ...); __printf(2, 3) void ath10k_warn(struct ath10k *ar, const char *fmt, ...); + +void ath10k_debug_print_hwfw_info(struct ath10k *ar); +void ath10k_debug_print_board_info(struct ath10k *ar); +void ath10k_debug_print_boot_info(struct ath10k *ar); void ath10k_print_driver_info(struct ath10k *ar); #ifdef CONFIG_ATH10K_DEBUGFS @@ -79,6 +164,7 @@ ath10k_debug_get_new_fw_crash_data(struct ath10k *ar); void ath10k_debug_dbglog_add(struct ath10k *ar, u8 *buffer, int len); +int ath10k_rx_record_pktlog(struct ath10k *ar, struct sk_buff *skb); #define ATH10K_DFS_STAT_INC(ar, c) (ar->debug.dfs_stats.c++) void ath10k_debug_get_et_strings(struct ieee80211_hw *hw, @@ -89,6 +175,9 @@ void ath10k_debug_get_et_stats(struct ieee80211_hw *hw, struct ieee80211_vif *vif, struct ethtool_stats *stats, u64 *data); +void fill_datapath_stats(struct ath10k *ar, struct ieee80211_rx_status *status); +size_t get_datapath_stat(char *buf, struct ath10k *ar); +int ath10k_pktlog_connect(struct ath10k *ar); #else static inline int ath10k_debug_start(struct ath10k *ar) { @@ -133,12 +222,32 @@ { } +static inline int ath10k_rx_record_pktlog(struct ath10k *ar, + struct sk_buff *skb) +{ + return 0; +} + static inline struct ath10k_fw_crash_data * ath10k_debug_get_new_fw_crash_data(struct ath10k *ar) { return NULL; } +static inline void fill_datapath_stats(struct ath10k *ar, + struct ieee80211_rx_status *status) +{ +} + +static inline size_t get_datapath_stat(char *buf, struct ath10k *ar) +{ + return 0; +} + +static inline int ath10k_pktlog_connect(struct ath10k *ar) +{ + return 0; +} #define ATH10K_DFS_STAT_INC(ar, c) do { } while (0) #define ath10k_debug_get_et_strings NULL @@ -149,6 +258,17 @@ #ifdef CONFIG_MAC80211_DEBUGFS void ath10k_sta_add_debugfs(struct ieee80211_hw *hw, struct ieee80211_vif *vif, struct ieee80211_sta *sta, struct dentry *dir); +void ath10k_sta_update_rx_duration(struct ath10k *ar, + struct ath10k_fw_stats *stats); +void ath10k_sta_statistics(struct ieee80211_hw *hw, struct ieee80211_vif *vif, + struct ieee80211_sta *sta, + struct station_info *sinfo); +#else +static inline +void ath10k_sta_update_rx_duration(struct ath10k *ar, + struct ath10k_fw_stats *stats) +{ +} #endif /* CONFIG_MAC80211_DEBUGFS */ #ifdef CONFIG_ATH10K_DEBUG diff -ruw linux-4.4.115/drivers/net/wireless/ath/ath10k/hif.h linux-4.4.115-fbx/drivers/net/wireless/ath/ath10k/hif.h --- linux-4.4.115/drivers/net/wireless/ath/ath10k/hif.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/net/wireless/ath/ath10k/hif.h 2019-01-22 16:16:25.415263721 +0100 @@ -26,7 +26,7 @@ u16 transfer_id; void *transfer_context; /* NULL = tx completion callback not called */ void *vaddr; /* for debugging mostly */ - u32 paddr; + dma_addr_t paddr; u16 len; }; @@ -87,6 +87,10 @@ int (*suspend)(struct ath10k *ar); int (*resume)(struct ath10k *ar); + + /* fetch calibration data from target eeprom */ + int (*fetch_cal_eeprom)(struct ath10k *ar, void **data, + size_t *data_len); }; static inline int ath10k_hif_tx_sg(struct ath10k *ar, u8 pipe_id, @@ -202,4 +206,14 @@ ar->hif.ops->write32(ar, address, data); } +static inline int ath10k_hif_fetch_cal_eeprom(struct ath10k *ar, + void **data, + size_t *data_len) +{ + if (!ar->hif.ops->fetch_cal_eeprom) + return -EOPNOTSUPP; + + return ar->hif.ops->fetch_cal_eeprom(ar, data, data_len); +} + #endif /* _HIF_H_ */ diff -ruw linux-4.4.115/drivers/net/wireless/ath/ath10k/htc.c linux-4.4.115-fbx/drivers/net/wireless/ath/ath10k/htc.c --- linux-4.4.115/drivers/net/wireless/ath/ath10k/htc.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/net/wireless/ath/ath10k/htc.c 2019-01-22 16:16:25.415263721 +0100 @@ -44,7 +44,7 @@ skb_cb = ATH10K_SKB_CB(skb); memset(skb_cb, 0, sizeof(*skb_cb)); - ath10k_dbg(ar, ATH10K_DBG_HTC, "%s: skb %p\n", __func__, skb); + ath10k_dbg(ar, ATH10K_DBG_HTC, "%s: skb %pK\n", __func__, skb); return skb; } @@ -62,7 +62,7 @@ { struct ath10k *ar = ep->htc->ar; - ath10k_dbg(ar, ATH10K_DBG_HTC, "%s: ep %d skb %p\n", __func__, + ath10k_dbg(ar, ATH10K_DBG_HTC, "%s: ep %d skb %pK\n", __func__, ep->eid, skb); ath10k_htc_restore_tx_skb(ep->htc, skb); @@ -86,6 +86,7 @@ hdr->eid = ep->eid; hdr->len = __cpu_to_le16(skb->len - sizeof(*hdr)); hdr->flags = 0; + if (ep->tx_credit_flow_enabled) hdr->flags |= ATH10K_HTC_FLAG_NEED_CREDIT_UPDATE; spin_lock_bh(&ep->htc->tx_lock); @@ -404,7 +405,7 @@ goto out; } - ath10k_dbg(ar, ATH10K_DBG_HTC, "htc rx completion ep %d skb %p\n", + ath10k_dbg(ar, ATH10K_DBG_HTC, "htc rx completion ep %d skb %pK\n", eid, skb); ep->ep_ops.ep_rx_complete(ar, skb); @@ -451,8 +452,16 @@ return "NMI Data"; case ATH10K_HTC_SVC_ID_HTT_DATA_MSG: return "HTT Data"; + case ATH10K_HTC_SVC_ID_HTT_DATA2_MSG: + return "HTT Data"; + case ATH10K_HTC_SVC_ID_HTT_DATA3_MSG: + return "HTT Data"; + case ATH10K_HTC_SVC_ID_HTT_IPA_MSG: + return "IPA"; case ATH10K_HTC_SVC_ID_TEST_RAW_STREAMS: return "RAW"; + case ATH10K_HTC_SVC_ID_HTT_LOG_MSG: + return "PKTLOG"; } return "Unknown"; diff -ruw linux-4.4.115/drivers/net/wireless/ath/ath10k/htc.h linux-4.4.115-fbx/drivers/net/wireless/ath/ath10k/htc.h --- linux-4.4.115/drivers/net/wireless/ath/ath10k/htc.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/net/wireless/ath/ath10k/htc.h 2019-01-22 16:16:25.415263721 +0100 @@ -22,7 +22,6 @@ #include #include #include -#include #include struct ath10k; @@ -223,7 +222,8 @@ ATH10K_HTC_SVC_GRP_WMI = 1, ATH10K_HTC_SVC_GRP_NMI = 2, ATH10K_HTC_SVC_GRP_HTT = 3, - + ATH10K_IPA_SERVICE_GROUP = 5, + ATH10K_LOG_SERVICE_GROUP = 6, ATH10K_HTC_SVC_GRP_TEST = 254, ATH10K_HTC_SVC_GRP_LAST = 255, }; @@ -247,7 +247,10 @@ ATH10K_HTC_SVC_ID_NMI_DATA = SVC(ATH10K_HTC_SVC_GRP_NMI, 1), ATH10K_HTC_SVC_ID_HTT_DATA_MSG = SVC(ATH10K_HTC_SVC_GRP_HTT, 0), - + ATH10K_HTC_SVC_ID_HTT_DATA2_MSG = SVC(ATH10K_HTC_SVC_GRP_HTT, 1), + ATH10K_HTC_SVC_ID_HTT_DATA3_MSG = SVC(ATH10K_HTC_SVC_GRP_HTT, 2), + ATH10K_HTC_SVC_ID_HTT_IPA_MSG = SVC(ATH10K_IPA_SERVICE_GROUP, 0), + ATH10K_HTC_SVC_ID_HTT_LOG_MSG = SVC(ATH10K_LOG_SERVICE_GROUP, 0), /* raw stream service (i.e. flash, tcmd, calibration apps) */ ATH10K_HTC_SVC_ID_TEST_RAW_STREAMS = SVC(ATH10K_HTC_SVC_GRP_TEST, 0), }; diff -ruw linux-4.4.115/drivers/net/wireless/ath/ath10k/htt.c linux-4.4.115-fbx/drivers/net/wireless/ath/ath10k/htt.c --- linux-4.4.115/drivers/net/wireless/ath/ath10k/htt.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/net/wireless/ath/ath10k/htt.c 2019-01-22 16:16:25.415263721 +0100 @@ -131,12 +131,12 @@ [HTT_10_4_T2H_MSG_TYPE_AGGR_CONF] = HTT_T2H_MSG_TYPE_AGGR_CONF, [HTT_10_4_T2H_MSG_TYPE_TX_FETCH_IND] = HTT_T2H_MSG_TYPE_TX_FETCH_IND, - [HTT_10_4_T2H_MSG_TYPE_TX_FETCH_CONF] = - HTT_T2H_MSG_TYPE_TX_FETCH_CONF, + [HTT_10_4_T2H_MSG_TYPE_TX_FETCH_CONFIRM] = + HTT_T2H_MSG_TYPE_TX_FETCH_CONFIRM, [HTT_10_4_T2H_MSG_TYPE_STATS_NOUPLOAD] = HTT_T2H_MSG_TYPE_STATS_NOUPLOAD, - [HTT_10_4_T2H_MSG_TYPE_TX_LOW_LATENCY_IND] = - HTT_T2H_MSG_TYPE_TX_LOW_LATENCY_IND, + [HTT_10_4_T2H_MSG_TYPE_TX_MODE_SWITCH_IND] = + HTT_T2H_MSG_TYPE_TX_MODE_SWITCH_IND, }; int ath10k_htt_connect(struct ath10k_htt *htt) @@ -149,7 +149,7 @@ memset(&conn_resp, 0, sizeof(conn_resp)); conn_req.ep_ops.ep_tx_complete = ath10k_htt_htc_tx_complete; - conn_req.ep_ops.ep_rx_complete = ath10k_htt_t2h_msg_handler; + conn_req.ep_ops.ep_rx_complete = ath10k_htt_htc_t2h_msg_handler; /* connect to control service */ conn_req.service_id = ATH10K_HTC_SVC_ID_HTT_DATA_MSG; @@ -183,7 +183,7 @@ 8 + /* llc snap */ 2; /* ip4 dscp or ip6 priority */ - switch (ar->htt.op_version) { + switch (ar->running_fw->fw_file.htt_op_version) { case ATH10K_FW_HTT_OP_VERSION_10_4: ar->htt.t2h_msg_types = htt_10_4_t2h_msg_types; ar->htt.t2h_msg_types_max = HTT_10_4_T2H_NUM_MSGS; diff -ruw linux-4.4.115/drivers/net/wireless/ath/ath10k/htt.h linux-4.4.115-fbx/drivers/net/wireless/ath/ath10k/htt.h --- linux-4.4.115/drivers/net/wireless/ath/ath10k/htt.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/net/wireless/ath/ath10k/htt.h 2019-01-22 16:16:25.415263721 +0100 @@ -22,6 +22,7 @@ #include #include #include +#include #include #include "htc.h" @@ -52,6 +53,7 @@ /* This command is used for sending management frames in HTT < 3.0. * HTT >= 3.0 uses TX_FRM for everything. */ HTT_H2T_MSG_TYPE_MGMT_TX = 7, + HTT_H2T_MSG_TYPE_TX_FETCH_RESP = 11, HTT_H2T_NUM_MSGS /* keep this last */ }; @@ -97,7 +99,11 @@ } __packed; struct htt_msdu_ext_desc { +#ifdef CONFIG_ATH10K_SNOC + __le32 tso_flag[5]; +#else __le32 tso_flag[3]; +#endif __le16 ip_identification; u8 flags; u8 reserved; @@ -116,6 +122,19 @@ | HTT_MSDU_EXT_DESC_FLAG_TCP_IPV4_CSUM_ENABLE \ | HTT_MSDU_EXT_DESC_FLAG_TCP_IPV6_CSUM_ENABLE) +#define HTT_TX_IPV4_CSUM_EN BIT(16) +#define HTT_TX_UDP_IPV4_CSUM_EN BIT(17) +#define HTT_TX_UDP_IPV6_CSUM_EN BIT(18) +#define HTT_TX_TCP_IPV4_CSUM_EN BIT(19) +#define HTT_TX_TCP_IPV6_CSUM_EN BIT(20) +#define HTT_TX_PARTIAL_CSUM_EN BIT(21) + +#define HTT_TX_CHECKSUM_ENABLE (HTT_TX_IPV4_CSUM_EN \ + | HTT_TX_UDP_IPV4_CSUM_EN \ + | HTT_TX_UDP_IPV6_CSUM_EN \ + | HTT_TX_TCP_IPV4_CSUM_EN \ + | HTT_TX_TCP_IPV6_CSUM_EN) + enum htt_data_tx_desc_flags0 { HTT_DATA_TX_DESC_FLAGS0_MAC_HDR_PRESENT = 1 << 0, HTT_DATA_TX_DESC_FLAGS0_NO_AGGR = 1 << 1, @@ -165,9 +184,19 @@ __le16 flags1; /* %HTT_DATA_TX_DESC_FLAGS1_ */ __le16 len; __le16 id; +#ifdef CONFIG_ATH10K_SNOC + __le32 frags_paddr_lo; + __le32 frags_paddr_hi; +#else __le32 frags_paddr; +#endif + union { + __le32 peerid; + struct { __le16 peerid; __le16 freq; + } __packed offchan_tx; + } __packed; u8 prefetch[0]; /* start of frame, for FW classification engine */ } __packed; @@ -194,8 +223,15 @@ #define HTT_RX_RING_SIZE_MAX 2048 struct htt_rx_ring_setup_ring { +#ifdef CONFIG_ATH10K_SNOC + __le32 fw_idx_shadow_reg_paddr_low; + __le32 fw_idx_shadow_reg_paddr_high; + __le32 rx_ring_base_paddr_low; + __le32 rx_ring_base_paddr_high; +#else __le32 fw_idx_shadow_reg_paddr; __le32 rx_ring_base_paddr; +#endif __le16 rx_ring_len; /* in 4-byte words */ __le16 rx_ring_bufsize; /* rx skb size - in bytes */ __le16 flags; /* %HTT_RX_RING_FLAGS_ */ @@ -408,10 +444,10 @@ HTT_10_4_T2H_MSG_TYPE_EN_STATS = 0x14, HTT_10_4_T2H_MSG_TYPE_AGGR_CONF = 0x15, HTT_10_4_T2H_MSG_TYPE_TX_FETCH_IND = 0x16, - HTT_10_4_T2H_MSG_TYPE_TX_FETCH_CONF = 0x17, + HTT_10_4_T2H_MSG_TYPE_TX_FETCH_CONFIRM = 0x17, HTT_10_4_T2H_MSG_TYPE_STATS_NOUPLOAD = 0x18, /* 0x19 to 0x2f are reserved */ - HTT_10_4_T2H_MSG_TYPE_TX_LOW_LATENCY_IND = 0x30, + HTT_10_4_T2H_MSG_TYPE_TX_MODE_SWITCH_IND = 0x30, /* keep this last */ HTT_10_4_T2H_NUM_MSGS }; @@ -444,8 +480,8 @@ HTT_T2H_MSG_TYPE_TEST, HTT_T2H_MSG_TYPE_EN_STATS, HTT_T2H_MSG_TYPE_TX_FETCH_IND, - HTT_T2H_MSG_TYPE_TX_FETCH_CONF, - HTT_T2H_MSG_TYPE_TX_LOW_LATENCY_IND, + HTT_T2H_MSG_TYPE_TX_FETCH_CONFIRM, + HTT_T2H_MSG_TYPE_TX_MODE_SWITCH_IND, /* keep this last */ HTT_T2H_NUM_MSGS }; @@ -478,10 +514,10 @@ __le32 status; } __packed; -#define HTT_RX_INDICATION_INFO0_EXT_TID_MASK (0x3F) +#define HTT_RX_INDICATION_INFO0_EXT_TID_MASK (0x1F) #define HTT_RX_INDICATION_INFO0_EXT_TID_LSB (0) -#define HTT_RX_INDICATION_INFO0_FLUSH_VALID (1 << 6) -#define HTT_RX_INDICATION_INFO0_RELEASE_VALID (1 << 7) +#define HTT_RX_INDICATION_INFO0_FLUSH_VALID (1 << 5) +#define HTT_RX_INDICATION_INFO0_RELEASE_VALID (1 << 6) #define HTT_RX_INDICATION_INFO1_FLUSH_START_SEQNO_MASK 0x0000003F #define HTT_RX_INDICATION_INFO1_FLUSH_START_SEQNO_LSB 0 @@ -517,6 +553,9 @@ #define HTT_RX_INDICATION_INFO2_SERVICE_MASK 0xFF000000 #define HTT_RX_INDICATION_INFO2_SERVICE_LSB 24 +#define HTT_WCN3990_PADDR_MASK 0x1F +#define HTT_WCN3990_ARCH_PADDR_MASK 0x1FFFFFFFFF + enum htt_rx_legacy_rate { HTT_RX_OFDM_48 = 0, HTT_RX_OFDM_24 = 1, @@ -588,7 +627,7 @@ /* only accept EAPOL frames */ HTT_RX_IND_MPDU_STATUS_UNAUTH_PEER, HTT_RX_IND_MPDU_STATUS_OUT_OF_SYNC, - /* Non-data in promiscous mode */ + /* Non-data in promiscuous mode */ HTT_RX_IND_MPDU_STATUS_MGMT_CTRL, HTT_RX_IND_MPDU_STATUS_TKIP_MIC_ERR, HTT_RX_IND_MPDU_STATUS_DECRYPT_ERR, @@ -839,7 +878,11 @@ } __packed; struct htt_rx_in_ord_msdu_desc { +#ifdef CONFIG_ATH10K_SNOC + __le64 msdu_paddr; +#else __le32 msdu_paddr; +#endif __le16 msdu_len; u8 fw_desc; u8 reserved; @@ -893,7 +936,7 @@ * Purpose: indicate how many 32-bit integers follow the message header * - NUM_CHARS * Bits 31:16 - * Purpose: indicate how many 8-bit charaters follow the series of integers + * Purpose: indicate how many 8-bit characters follow the series of integers */ struct htt_rx_test { u8 num_ints; @@ -1035,10 +1078,10 @@ /* illegal rate phy errors */ __le32 illgl_rate_phy_err; - /* wal pdev continous xretry */ + /* wal pdev continuous xretry */ __le32 pdev_cont_xretry; - /* wal pdev continous xretry */ + /* wal pdev continuous xretry */ __le32 pdev_tx_timeout; /* wal pdev resets */ @@ -1303,14 +1346,173 @@ #define HTT_FRAG_DESC_BANK_CFG_INFO_PDEV_ID_MASK 0x03 #define HTT_FRAG_DESC_BANK_CFG_INFO_PDEV_ID_LSB 0 -#define HTT_FRAG_DESC_BANK_CFG_INFO_SWAP (1 << 2) +#define HTT_FRAG_DESC_BANK_CFG_INFO_SWAP BIT(2) +#define HTT_FRAG_DESC_BANK_CFG_INFO_Q_STATE_VALID BIT(3) +#define HTT_FRAG_DESC_BANK_CFG_INFO_Q_STATE_DEPTH_TYPE_MASK BIT(4) +#define HTT_FRAG_DESC_BANK_CFG_INFO_Q_STATE_DEPTH_TYPE_LSB 4 + +enum htt_q_depth_type { + HTT_Q_DEPTH_TYPE_BYTES = 0, + HTT_Q_DEPTH_TYPE_MSDUS = 1, +}; + +#define HTT_TX_Q_STATE_NUM_PEERS (TARGET_10_4_NUM_QCACHE_PEERS_MAX + \ + TARGET_10_4_NUM_VDEVS) +#define HTT_TX_Q_STATE_NUM_TIDS 8 +#define HTT_TX_Q_STATE_ENTRY_SIZE 1 +#define HTT_TX_Q_STATE_ENTRY_MULTIPLIER 0 + +/** + * htt_q_state_conf - part of htt_frag_desc_bank_cfg for host q state config + * + * Defines host q state format and behavior. See htt_q_state. + * + * @record_size: Defines the size of each host q entry in bytes. In practice + * however firmware (at least 10.4.3-00191) ignores this host + * configuration value and uses hardcoded value of 1. + * @record_multiplier: This is valid only when q depth type is MSDUs. It + * defines the exponent for the power of 2 multiplication. + */ +struct htt_q_state_conf { + __le32 paddr; + __le16 num_peers; + __le16 num_tids; + u8 record_size; + u8 record_multiplier; + u8 pad[2]; +} __packed; + +struct bank_base_addr { + __le32 low; + __le32 high; +}; struct htt_frag_desc_bank_cfg { u8 info; /* HTT_FRAG_DESC_BANK_CFG_INFO_ */ u8 num_banks; u8 desc_size; +#ifdef CONFIG_ATH10K_SNOC + struct bank_base_addr bank_base_addrs[HTT_FRAG_DESC_BANK_MAX]; +#else __le32 bank_base_addrs[HTT_FRAG_DESC_BANK_MAX]; +#endif struct htt_frag_desc_bank_id bank_id[HTT_FRAG_DESC_BANK_MAX]; + struct htt_q_state_conf q_state; +} __packed; + +#define HTT_TX_Q_STATE_ENTRY_COEFFICIENT 128 +#define HTT_TX_Q_STATE_ENTRY_FACTOR_MASK 0x3f +#define HTT_TX_Q_STATE_ENTRY_FACTOR_LSB 0 +#define HTT_TX_Q_STATE_ENTRY_EXP_MASK 0xc0 +#define HTT_TX_Q_STATE_ENTRY_EXP_LSB 6 + +/** + * htt_q_state - shared between host and firmware via DMA + * + * This structure is used for the host to expose it's software queue state to + * firmware so that its rate control can schedule fetch requests for optimized + * performance. This is most notably used for MU-MIMO aggregation when multiple + * MU clients are connected. + * + * @count: Each element defines the host queue depth. When q depth type was + * configured as HTT_Q_DEPTH_TYPE_BYTES then each entry is defined as: + * FACTOR * 128 * 8^EXP (see HTT_TX_Q_STATE_ENTRY_FACTOR_MASK and + * HTT_TX_Q_STATE_ENTRY_EXP_MASK). When q depth type was configured as + * HTT_Q_DEPTH_TYPE_MSDUS the number of packets is scaled by 2 ** + * record_multiplier (see htt_q_state_conf). + * @map: Used by firmware to quickly check which host queues are not empty. It + * is a bitmap simply saying. + * @seq: Used by firmware to quickly check if the host queues were updated + * since it last checked. + * + * FIXME: Is the q_state map[] size calculation really correct? + */ +struct htt_q_state { + u8 count[HTT_TX_Q_STATE_NUM_TIDS][HTT_TX_Q_STATE_NUM_PEERS]; + u32 map[HTT_TX_Q_STATE_NUM_TIDS][(HTT_TX_Q_STATE_NUM_PEERS + 31) / 32]; + __le32 seq; +} __packed; + +#define HTT_TX_FETCH_RECORD_INFO_PEER_ID_MASK 0x0fff +#define HTT_TX_FETCH_RECORD_INFO_PEER_ID_LSB 0 +#define HTT_TX_FETCH_RECORD_INFO_TID_MASK 0xf000 +#define HTT_TX_FETCH_RECORD_INFO_TID_LSB 12 + +struct htt_tx_fetch_record { + __le16 info; /* HTT_TX_FETCH_IND_RECORD_INFO_ */ + __le16 num_msdus; + __le32 num_bytes; +} __packed; + +struct htt_tx_fetch_ind { + u8 pad0; + __le16 fetch_seq_num; + __le32 token; + __le16 num_resp_ids; + __le16 num_records; + struct htt_tx_fetch_record records[0]; + __le32 resp_ids[0]; /* ath10k_htt_get_tx_fetch_ind_resp_ids() */ +} __packed; + +static inline void * +ath10k_htt_get_tx_fetch_ind_resp_ids(struct htt_tx_fetch_ind *ind) +{ + return (void *)&ind->records[le16_to_cpu(ind->num_records)]; +} + +struct htt_tx_fetch_resp { + u8 pad0; + __le16 resp_id; + __le16 fetch_seq_num; + __le16 num_records; + __le32 token; + struct htt_tx_fetch_record records[0]; +} __packed; + +struct htt_tx_fetch_confirm { + u8 pad0; + __le16 num_resp_ids; + __le32 resp_ids[0]; +} __packed; + +enum htt_tx_mode_switch_mode { + HTT_TX_MODE_SWITCH_PUSH = 0, + HTT_TX_MODE_SWITCH_PUSH_PULL = 1, +}; + +#define HTT_TX_MODE_SWITCH_IND_INFO0_ENABLE BIT(0) +#define HTT_TX_MODE_SWITCH_IND_INFO0_NUM_RECORDS_MASK 0xfffe +#define HTT_TX_MODE_SWITCH_IND_INFO0_NUM_RECORDS_LSB 1 + +#define HTT_TX_MODE_SWITCH_IND_INFO1_MODE_MASK 0x0003 +#define HTT_TX_MODE_SWITCH_IND_INFO1_MODE_LSB 0 +#define HTT_TX_MODE_SWITCH_IND_INFO1_THRESHOLD_MASK 0xfffc +#define HTT_TX_MODE_SWITCH_IND_INFO1_THRESHOLD_LSB 2 + +#define HTT_TX_MODE_SWITCH_RECORD_INFO0_PEER_ID_MASK 0x0fff +#define HTT_TX_MODE_SWITCH_RECORD_INFO0_PEER_ID_LSB 0 +#define HTT_TX_MODE_SWITCH_RECORD_INFO0_TID_MASK 0xf000 +#define HTT_TX_MODE_SWITCH_RECORD_INFO0_TID_LSB 12 + +struct htt_tx_mode_switch_record { + __le16 info0; /* HTT_TX_MODE_SWITCH_RECORD_INFO0_ */ + __le16 num_max_msdus; +} __packed; + +struct htt_tx_mode_switch_ind { + u8 pad0; + __le16 info0; /* HTT_TX_MODE_SWITCH_IND_INFO0_ */ + __le16 info1; /* HTT_TX_MODE_SWITCH_IND_INFO1_ */ + u8 pad1[2]; + struct htt_tx_mode_switch_record records[0]; +} __packed; + +struct htt_channel_change { + u8 pad[3]; + __le32 freq; + __le32 center_freq1; + __le32 center_freq2; + __le32 phymode; } __packed; union htt_rx_pn_t { @@ -1318,10 +1520,10 @@ u32 pn24; /* TKIP or CCMP: 48-bit PN */ - u_int64_t pn48; + u64 pn48; /* WAPI: 128-bit PN */ - u_int64_t pn128[2]; + u64 pn128[2]; }; struct htt_cmd { @@ -1335,6 +1537,7 @@ struct htt_oob_sync_req oob_sync_req; struct htt_aggr_conf aggr_conf; struct htt_frag_desc_bank_cfg frag_desc_bank_cfg; + struct htt_tx_fetch_resp tx_fetch_resp; }; } __packed; @@ -1359,16 +1562,25 @@ struct htt_rx_pn_ind rx_pn_ind; struct htt_rx_offload_ind rx_offload_ind; struct htt_rx_in_ord_ind rx_in_ord_ind; + struct htt_tx_fetch_ind tx_fetch_ind; + struct htt_tx_fetch_confirm tx_fetch_confirm; + struct htt_tx_mode_switch_ind tx_mode_switch_ind; + struct htt_channel_change chan_change; }; } __packed; /*** host side structures follow ***/ struct htt_tx_done { - u32 msdu_id; - bool discard; - bool no_ack; - bool success; + u16 msdu_id; + u16 status; +}; + +enum htt_tx_compl_state { + HTT_TX_COMPL_STATE_NONE, + HTT_TX_COMPL_STATE_ACK, + HTT_TX_COMPL_STATE_NOACK, + HTT_TX_COMPL_STATE_DISCARD, }; struct htt_peer_map_event { @@ -1395,7 +1607,6 @@ u8 target_version_major; u8 target_version_minor; struct completion target_version_received; - enum ath10k_fw_htt_op_version op_version; u8 max_num_amsdu; u8 max_num_ampdu; @@ -1433,7 +1644,11 @@ * rx buffers the host SW provides for the MAC HW to * fill. */ +#ifdef CONFIG_ATH10K_SNOC + __le64 *paddrs_ring; +#else __le32 *paddrs_ring; +#endif /* * Base address of ring, as a "physical" device address @@ -1489,17 +1704,19 @@ struct idr pending_tx; wait_queue_head_t empty_tx_wq; + /* FIFO for storing tx done status {ack, no-ack, discard} and msdu id */ + DECLARE_KFIFO_PTR(txdone_fifo, struct htt_tx_done); + /* set if host-fw communication goes haywire * used to avoid further failures */ bool rx_confused; - struct tasklet_struct rx_replenish_task; + atomic_t num_mpdus_ready; /* This is used to group tx/rx completions separately and process them * in batches to reduce cache stalls */ - struct tasklet_struct txrx_compl_task; - struct sk_buff_head tx_compl_q; struct sk_buff_head rx_compl_q; struct sk_buff_head rx_in_ord_compl_q; + struct sk_buff_head tx_fetch_ind_q; /* rx_status template */ struct ieee80211_rx_status rx_status; @@ -1513,20 +1730,36 @@ dma_addr_t paddr; struct ath10k_htt_txbuf *vaddr; } txbuf; + + struct { + bool enabled; + struct htt_q_state *vaddr; + dma_addr_t paddr; + u16 num_push_allowed; + u16 num_peers; + u16 num_tids; + enum htt_tx_mode_switch_mode mode; + enum htt_q_depth_type type; + } tx_q_state; }; #define RX_HTT_HDR_STATUS_LEN 64 -/* This structure layout is programmed via rx ring setup - * so that FW knows how to transfer the rx descriptor to the host. - * Buffers like this are placed on the rx ring. */ -struct htt_rx_desc { +struct htt_host_fw_desc_base { union { /* This field is filled on the host using the msdu buffer * from htt_rx_indication */ struct fw_rx_desc_base fw_desc; u32 pad; } __packed; +}; + +/* This structure layout is programmed via rx ring setup + * so that FW knows how to transfer the rx descriptor to the host. + * Buffers like this are placed on the rx ring. + */ +struct htt_rx_desc { + struct htt_host_fw_desc_base fw_desc_base; struct { struct rx_attention attention; struct rx_frag_info frag_info; @@ -1555,7 +1788,7 @@ /* Refill a bunch of RX buffers for each refill round so that FW/HW can handle * aggregated traffic more nicely. */ -#define ATH10K_HTT_MAX_NUM_REFILL 16 +#define ATH10K_HTT_MAX_NUM_REFILL 100 /* * DMA_MAP expects the buffer to be an integral number of cache lines. @@ -1583,7 +1816,8 @@ void ath10k_htt_rx_free(struct ath10k_htt *htt); void ath10k_htt_htc_tx_complete(struct ath10k *ar, struct sk_buff *skb); -void ath10k_htt_t2h_msg_handler(struct ath10k *ar, struct sk_buff *skb); +void ath10k_htt_htc_t2h_msg_handler(struct ath10k *ar, struct sk_buff *skb); +bool ath10k_htt_t2h_msg_handler(struct ath10k *ar, struct sk_buff *skb); int ath10k_htt_h2t_ver_req_msg(struct ath10k_htt *htt); int ath10k_htt_h2t_stats_req(struct ath10k_htt *htt, u8 mask, u64 cookie); int ath10k_htt_send_frag_desc_bank_cfg(struct ath10k_htt *htt); @@ -1592,11 +1826,33 @@ u8 max_subfrms_ampdu, u8 max_subfrms_amsdu); void ath10k_htt_hif_tx_complete(struct ath10k *ar, struct sk_buff *skb); +int ath10k_htt_tx_fetch_resp(struct ath10k *ar, + __le32 token, + __le16 fetch_seq_num, + struct htt_tx_fetch_record *records, + size_t num_records); + +void ath10k_htt_tx_txq_update(struct ieee80211_hw *hw, + struct ieee80211_txq *txq); +void ath10k_htt_tx_txq_recalc(struct ieee80211_hw *hw, + struct ieee80211_txq *txq); +void ath10k_htt_tx_txq_sync(struct ath10k *ar); +void ath10k_htt_tx_dec_pending(struct ath10k_htt *htt); +int ath10k_htt_tx_inc_pending(struct ath10k_htt *htt); +void ath10k_htt_tx_mgmt_dec_pending(struct ath10k_htt *htt); +int ath10k_htt_tx_mgmt_inc_pending(struct ath10k_htt *htt, bool is_mgmt, + bool is_presp); -void __ath10k_htt_tx_dec_pending(struct ath10k_htt *htt, bool limit_mgmt_desc); int ath10k_htt_tx_alloc_msdu_id(struct ath10k_htt *htt, struct sk_buff *skb); void ath10k_htt_tx_free_msdu_id(struct ath10k_htt *htt, u16 msdu_id); int ath10k_htt_mgmt_tx(struct ath10k_htt *htt, struct sk_buff *); -int ath10k_htt_tx(struct ath10k_htt *htt, struct sk_buff *); +int ath10k_htt_tx(struct ath10k_htt *htt, + enum ath10k_hw_txrx_mode txmode, + struct sk_buff *msdu); +void ath10k_htt_rx_pktlog_completion_handler(struct ath10k *ar, + struct sk_buff *skb); +int ath10k_htt_txrx_compl_task(struct ath10k *ar, int budget); +struct sk_buff *ath10k_htt_tx_find_msdu_by_id(struct ath10k_htt *htt, + u16 msdu_id); #endif diff -ruw linux-4.4.115/drivers/net/wireless/ath/ath10k/htt_rx.c linux-4.4.115-fbx/drivers/net/wireless/ath/ath10k/htt_rx.c --- linux-4.4.115/drivers/net/wireless/ath/ath10k/htt_rx.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/net/wireless/ath/ath10k/htt_rx.c 2019-10-29 09:26:24.457211144 +0100 @@ -27,15 +27,17 @@ #define HTT_RX_RING_SIZE HTT_RX_RING_SIZE_MAX #define HTT_RX_RING_FILL_LEVEL (((HTT_RX_RING_SIZE) / 2) - 1) +#define HTT_RX_RING_FILL_LEVEL_DUAL_MAC (HTT_RX_RING_SIZE - 1) /* when under memory pressure rx ring refill may fail and needs a retry */ #define HTT_RX_RING_REFILL_RETRY_MS 50 +#define HTT_RX_RING_REFILL_RESCHED_MS 5 + static int ath10k_htt_rx_get_csum_state(struct sk_buff *skb); -static void ath10k_htt_txrx_compl_task(unsigned long ptr); static struct sk_buff * -ath10k_htt_rx_find_skb_paddr(struct ath10k *ar, u32 paddr) +ath10k_htt_rx_find_skb_paddr(struct ath10k *ar, u64 paddr) { struct ath10k_skb_rxcb *rxcb; @@ -128,13 +130,16 @@ rxcb = ATH10K_SKB_RXCB(skb); rxcb->paddr = paddr; htt->rx_ring.netbufs_ring[idx] = skb; + if (QCA_REV_WCN3990(htt->ar)) + htt->rx_ring.paddrs_ring[idx] = __cpu_to_le64(paddr); + else htt->rx_ring.paddrs_ring[idx] = __cpu_to_le32(paddr); htt->rx_ring.fill_cnt++; if (htt->rx_ring.in_ord_rx) { hash_add(htt->rx_ring.skb_table, &ATH10K_SKB_RXCB(skb)->hlist, - (u32)paddr); + paddr); } num--; @@ -192,7 +197,8 @@ mod_timer(&htt->rx_ring.refill_retry_timer, jiffies + msecs_to_jiffies(HTT_RX_RING_REFILL_RETRY_MS)); } else if (num_deficit > 0) { - tasklet_schedule(&htt->rx_replenish_task); + mod_timer(&htt->rx_ring.refill_retry_timer, jiffies + + msecs_to_jiffies(HTT_RX_RING_REFILL_RESCHED_MS)); } spin_unlock_bh(&htt->rx_ring.lock); } @@ -223,12 +229,10 @@ void ath10k_htt_rx_free(struct ath10k_htt *htt) { del_timer_sync(&htt->rx_ring.refill_retry_timer); - tasklet_kill(&htt->rx_replenish_task); - tasklet_kill(&htt->txrx_compl_task); - skb_queue_purge(&htt->tx_compl_q); skb_queue_purge(&htt->rx_compl_q); skb_queue_purge(&htt->rx_in_ord_compl_q); + skb_queue_purge(&htt->tx_fetch_ind_q); ath10k_htt_rx_ring_free(htt); @@ -281,7 +285,6 @@ /* return: < 0 fatal error, 0 - non chained msdu, 1 chained msdu */ static int ath10k_htt_rx_amsdu_pop(struct ath10k_htt *htt, - u8 **fw_desc, int *fw_desc_len, struct sk_buff_head *amsdu) { struct ath10k *ar = htt->ar; @@ -323,48 +326,6 @@ return -EIO; } - /* - * Copy the FW rx descriptor for this MSDU from the rx - * indication message into the MSDU's netbuf. HL uses the - * same rx indication message definition as LL, and simply - * appends new info (fields from the HW rx desc, and the - * MSDU payload itself). So, the offset into the rx - * indication message only has to account for the standard - * offset of the per-MSDU FW rx desc info within the - * message, and how many bytes of the per-MSDU FW rx desc - * info have already been consumed. (And the endianness of - * the host, since for a big-endian host, the rx ind - * message contents, including the per-MSDU rx desc bytes, - * were byteswapped during upload.) - */ - if (*fw_desc_len > 0) { - rx_desc->fw_desc.info0 = **fw_desc; - /* - * The target is expected to only provide the basic - * per-MSDU rx descriptors. Just to be sure, verify - * that the target has not attached extension data - * (e.g. LRO flow ID). - */ - - /* or more, if there's extension data */ - (*fw_desc)++; - (*fw_desc_len)--; - } else { - /* - * When an oversized AMSDU happened, FW will lost - * some of MSDU status - in this case, the FW - * descriptors provided will be less than the - * actual MSDUs inside this MPDU. Mark the FW - * descriptors so that it will still deliver to - * upper stack, if no CRC error for this MPDU. - * - * FIX THIS - the FW descriptors are actually for - * MSDUs in the end of this A-MSDU instead of the - * beginning. - */ - rx_desc->fw_desc.info0 = 0; - } - msdu_len_invalid = !!(__le32_to_cpu(rx_desc->attention.flags) & (RX_ATTENTION_FLAGS_MPDU_LENGTH_ERR | RX_ATTENTION_FLAGS_MSDU_LENGTH_ERR)); @@ -423,15 +384,8 @@ return msdu_chaining; } -static void ath10k_htt_rx_replenish_task(unsigned long ptr) -{ - struct ath10k_htt *htt = (struct ath10k_htt *)ptr; - - ath10k_htt_rx_msdu_buff_replenish(htt); -} - static struct sk_buff *ath10k_htt_rx_pop_paddr(struct ath10k_htt *htt, - u32 paddr) + u64 paddr) { struct ath10k *ar = htt->ar; struct ath10k_skb_rxcb *rxcb; @@ -466,7 +420,7 @@ struct sk_buff *msdu; int msdu_count; bool is_offload; - u32 paddr; + u64 paddr; lockdep_assert_held(&htt->rx_ring.lock); @@ -474,8 +428,12 @@ is_offload = !!(ev->info & HTT_RX_IN_ORD_IND_INFO_OFFLOAD_MASK); while (msdu_count--) { +#ifdef CONFIG_ATH10K_SNOC + paddr = __le64_to_cpu(msdu_desc->msdu_paddr); + paddr &= HTT_WCN3990_ARCH_PADDR_MASK; +#else paddr = __le32_to_cpu(msdu_desc->msdu_paddr); - +#endif msdu = ath10k_htt_rx_pop_paddr(htt, paddr); if (!msdu) { __skb_queue_purge(list); @@ -521,7 +479,15 @@ */ htt->rx_ring.size = HTT_RX_RING_SIZE; htt->rx_ring.size_mask = htt->rx_ring.size - 1; + + switch (ar->hw_rev) { + case ATH10K_HW_WCN3990: + htt->rx_ring.fill_level = HTT_RX_RING_FILL_LEVEL_DUAL_MAC; + break; + default: htt->rx_ring.fill_level = HTT_RX_RING_FILL_LEVEL; + break; + } if (!is_power_of_2(htt->rx_ring.size)) { ath10k_warn(ar, "htt rx ring size is not power of 2\n"); @@ -536,7 +502,7 @@ size = htt->rx_ring.size * sizeof(htt->rx_ring.paddrs_ring); - vaddr = dma_alloc_coherent(htt->ar->dev, size, &paddr, GFP_DMA); + vaddr = dma_alloc_coherent(htt->ar->dev, size, &paddr, GFP_KERNEL); if (!vaddr) goto err_dma_ring; @@ -545,7 +511,7 @@ vaddr = dma_alloc_coherent(htt->ar->dev, sizeof(*htt->rx_ring.alloc_idx.vaddr), - &paddr, GFP_DMA); + &paddr, GFP_KERNEL); if (!vaddr) goto err_dma_idx; @@ -563,15 +529,10 @@ htt->rx_ring.sw_rd_idx.msdu_payld = 0; hash_init(htt->rx_ring.skb_table); - tasklet_init(&htt->rx_replenish_task, ath10k_htt_rx_replenish_task, - (unsigned long)htt); - - skb_queue_head_init(&htt->tx_compl_q); skb_queue_head_init(&htt->rx_compl_q); skb_queue_head_init(&htt->rx_in_ord_compl_q); - - tasklet_init(&htt->txrx_compl_task, ath10k_htt_txrx_compl_task, - (unsigned long)htt); + skb_queue_head_init(&htt->tx_fetch_ind_q); + atomic_set(&htt->num_mpdus_ready, 0); ath10k_dbg(ar, ATH10K_DBG_BOOT, "htt rx ring size %d fill_level %d\n", htt->rx_ring.size, htt->rx_ring.fill_level); @@ -674,7 +635,7 @@ rate &= ~RX_PPDU_START_RATE_FLAG; sband = &ar->mac.sbands[status->band]; - status->rate_idx = ath10k_mac_hw_rate_to_idx(sband, rate); + status->rate_idx = ath10k_mac_hw_rate_to_idx(sband, rate, cck); break; case HTT_RX_HT: case HTT_RX_HT_WITH_TXBF: @@ -798,7 +759,7 @@ if (WARN_ON_ONCE(!arvif)) return NULL; - if (WARN_ON(ath10k_mac_vif_chan(arvif->vif, &def))) + if (ath10k_mac_vif_chan(arvif->vif, &def)) return NULL; return def.chan; @@ -860,6 +821,8 @@ ch = ath10k_htt_rx_h_vdev_channel(ar, vdev_id); if (!ch) ch = ath10k_htt_rx_h_any_channel(ar); + if (!ch) + ch = ar->tgt_oper_chan; spin_unlock_bh(&ar->data_lock); if (!ch) @@ -977,9 +940,9 @@ status = IEEE80211_SKB_RXCB(skb); *status = *rx_status; - + fill_datapath_stats(ar, status); ath10k_dbg(ar, ATH10K_DBG_DATA, - "rx skb %p len %u peer %pM %s %s sn %u %s%s%s%s%s %srate_idx %u vht_nss %u freq %u band %u flag 0x%x fcs-err %i mic-err %i amsdu-more %i\n", + "rx skb %pK len %u peer %pM %s %s sn %u %s%s%s%s%s %srate_idx %u vht_nss %u freq %u band %u flag 0x%x fcs-err %i mic-err %i amsdu-more %i\n", skb, skb->len, ieee80211_get_SA(hdr), @@ -987,7 +950,8 @@ is_multicast_ether_addr(ieee80211_get_DA(hdr)) ? "mcast" : "ucast", (__le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_SEQ) >> 4, - status->flag == 0 ? "legacy" : "", + (status->flag & (RX_FLAG_HT | RX_FLAG_VHT)) == 0 ? + "legacy" : "", status->flag & RX_FLAG_HT ? "ht" : "", status->flag & RX_FLAG_VHT ? "vht" : "", status->flag & RX_FLAG_40MHZ ? "40" : "", @@ -1005,7 +969,8 @@ trace_ath10k_rx_hdr(ar, skb->data, skb->len); trace_ath10k_rx_payload(ar, skb->data, skb->len); - ieee80211_rx(ar->hw, skb); + ath10k_rx_record_pktlog(ar, skb); + ieee80211_rx_napi(ar->hw, NULL, skb, &ar->napi); } static int ath10k_htt_rx_nwifi_hdrlen(struct ath10k *ar, @@ -1014,7 +979,7 @@ int len = ieee80211_hdrlen(hdr->frame_control); if (!test_bit(ATH10K_FW_FEATURE_NO_NWIFI_DECAP_4ADDR_PADDING, - ar->fw_features)) + ar->running_fw->fw_file.fw_features)) len = round_up(len, 4); return len; @@ -1076,14 +1041,18 @@ hdr = (void *)msdu->data; /* Tail */ - skb_trim(msdu, msdu->len - ath10k_htt_rx_crypto_tail_len(ar, enctype)); + if (status->flag & RX_FLAG_IV_STRIPPED) + skb_trim(msdu, msdu->len - + ath10k_htt_rx_crypto_tail_len(ar, enctype)); /* MMIC */ - if (!ieee80211_has_morefrags(hdr->frame_control) && + if ((status->flag & RX_FLAG_MMIC_STRIPPED) && + !ieee80211_has_morefrags(hdr->frame_control) && enctype == HTT_RX_MPDU_ENCRYPT_TKIP_WPA) skb_trim(msdu, msdu->len - 8); /* Head */ + if (status->flag & RX_FLAG_IV_STRIPPED) { hdr_len = ieee80211_hdrlen(hdr->frame_control); crypto_len = ath10k_htt_rx_crypto_param_len(ar, enctype); @@ -1091,6 +1060,7 @@ (void *)msdu->data, hdr_len); skb_pull(msdu, crypto_len); } +} static void ath10k_htt_rx_h_undecap_nwifi(struct ath10k *ar, struct sk_buff *msdu, @@ -1098,9 +1068,11 @@ const u8 first_hdr[64]) { struct ieee80211_hdr *hdr; + struct htt_rx_desc *rxd; size_t hdr_len; u8 da[ETH_ALEN]; u8 sa[ETH_ALEN]; + int l3_pad_bytes; /* Delivered decapped frame: * [nwifi 802.11 header] <-- replaced with 802.11 hdr @@ -1114,7 +1086,13 @@ */ /* pull decapped header and copy SA & DA */ - hdr = (struct ieee80211_hdr *)msdu->data; + rxd = (void *)msdu->data - sizeof(*rxd); + + l3_pad_bytes = ath10k_rx_desc_get_l3_pad_bytes(&ar->hw_params, rxd); + skb_put(msdu, l3_pad_bytes); + + hdr = (struct ieee80211_hdr *)(msdu->data + l3_pad_bytes); + hdr_len = ath10k_htt_rx_nwifi_hdrlen(ar, hdr); ether_addr_copy(da, ieee80211_get_DA(hdr)); ether_addr_copy(sa, ieee80211_get_SA(hdr)); @@ -1142,6 +1120,7 @@ size_t hdr_len, crypto_len; void *rfc1042; bool is_first, is_last, is_amsdu; + int bytes_aligned = ar->hw_params.decap_align_bytes; rxd = (void *)msdu->data - sizeof(*rxd); hdr = (void *)rxd->rx_hdr_status; @@ -1158,8 +1137,8 @@ hdr_len = ieee80211_hdrlen(hdr->frame_control); crypto_len = ath10k_htt_rx_crypto_param_len(ar, enctype); - rfc1042 += round_up(hdr_len, 4) + - round_up(crypto_len, 4); + rfc1042 += round_up(hdr_len, bytes_aligned) + + round_up(crypto_len, bytes_aligned); } if (is_amsdu) @@ -1180,6 +1159,8 @@ void *rfc1042; u8 da[ETH_ALEN]; u8 sa[ETH_ALEN]; + int l3_pad_bytes; + struct htt_rx_desc *rxd; /* Delivered decapped frame: * [eth header] <-- replaced with 802.11 hdr & rfc1042/llc @@ -1190,6 +1171,11 @@ if (WARN_ON_ONCE(!rfc1042)) return; + rxd = (void *)msdu->data - sizeof(*rxd); + l3_pad_bytes = ath10k_rx_desc_get_l3_pad_bytes(&ar->hw_params, rxd); + skb_put(msdu, l3_pad_bytes); + skb_pull(msdu, l3_pad_bytes); + /* pull decapped header and copy SA & DA */ eth = (struct ethhdr *)msdu->data; ether_addr_copy(da, eth->h_dest); @@ -1220,6 +1206,8 @@ { struct ieee80211_hdr *hdr; size_t hdr_len; + int l3_pad_bytes; + struct htt_rx_desc *rxd; /* Delivered decapped frame: * [amsdu header] <-- replaced with 802.11 hdr @@ -1227,7 +1215,11 @@ * [payload] */ - skb_pull(msdu, sizeof(struct amsdu_subframe_hdr)); + rxd = (void *)msdu->data - sizeof(*rxd); + l3_pad_bytes = ath10k_rx_desc_get_l3_pad_bytes(&ar->hw_params, rxd); + + skb_put(msdu, l3_pad_bytes); + skb_pull(msdu, sizeof(struct amsdu_subframe_hdr) + l3_pad_bytes); hdr = (struct ieee80211_hdr *)first_hdr; hdr_len = ieee80211_hdrlen(hdr->frame_control); @@ -1330,6 +1322,7 @@ bool has_tkip_err; bool has_peer_idx_invalid; bool is_decrypted; + bool is_mgmt; u32 attention; if (skb_queue_empty(amsdu)) @@ -1338,6 +1331,9 @@ first = skb_peek(amsdu); rxd = (void *)first->data - sizeof(*rxd); + is_mgmt = !!(rxd->attention.flags & + __cpu_to_le32(RX_ATTENTION_FLAGS_MGMT_TYPE)); + enctype = MS(__le32_to_cpu(rxd->mpdu_start.info0), RX_MPDU_START_INFO0_ENCRYPT_TYPE); @@ -1379,6 +1375,7 @@ RX_FLAG_MMIC_ERROR | RX_FLAG_DECRYPTED | RX_FLAG_IV_STRIPPED | + RX_FLAG_ONLY_MONITOR | RX_FLAG_MMIC_STRIPPED); if (has_fcs_err) @@ -1387,10 +1384,21 @@ if (has_tkip_err) status->flag |= RX_FLAG_MMIC_ERROR; - if (is_decrypted) - status->flag |= RX_FLAG_DECRYPTED | - RX_FLAG_IV_STRIPPED | + /* Firmware reports all necessary management frames via WMI already. + * They are not reported to monitor interfaces at all so pass the ones + * coming via HTT to monitor interfaces instead. This simplifies + * matters a lot. + */ + if (is_mgmt) + status->flag |= RX_FLAG_ONLY_MONITOR; + + if (is_decrypted) { + status->flag |= RX_FLAG_DECRYPTED; + + if (likely(!is_mgmt)) + status->flag |= RX_FLAG_IV_STRIPPED | RX_FLAG_MMIC_STRIPPED; +} skb_queue_walk(amsdu, msdu) { ath10k_htt_rx_h_csum_offload(msdu); @@ -1403,6 +1411,8 @@ */ if (!is_decrypted) continue; + if (is_mgmt) + continue; hdr = (void *)msdu->data; hdr->frame_control &= ~__cpu_to_le16(IEEE80211_FCTL_PROTECTED); @@ -1503,14 +1513,6 @@ struct sk_buff_head *amsdu, struct ieee80211_rx_status *rx_status) { - struct sk_buff *msdu; - struct htt_rx_desc *rxd; - bool is_mgmt; - bool has_fcs_err; - - msdu = skb_peek(amsdu); - rxd = (void *)msdu->data - sizeof(*rxd); - /* FIXME: It might be a good idea to do some fuzzy-testing to drop * invalid/dangerous frames. */ @@ -1520,23 +1522,6 @@ return false; } - is_mgmt = !!(rxd->attention.flags & - __cpu_to_le32(RX_ATTENTION_FLAGS_MGMT_TYPE)); - has_fcs_err = !!(rxd->attention.flags & - __cpu_to_le32(RX_ATTENTION_FLAGS_FCS_ERR)); - - /* Management frames are handled via WMI events. The pros of such - * approach is that channel is explicitly provided in WMI events - * whereas HTT doesn't provide channel information for Rxed frames. - * - * However some firmware revisions don't report corrupted frames via - * WMI so don't drop them. - */ - if (is_mgmt && !has_fcs_err) { - ath10k_dbg(ar, ATH10K_DBG_HTT, "htt rx mgmt ctrl\n"); - return false; - } - if (test_bit(ATH10K_CAC_RUNNING, &ar->dev_flags)) { ath10k_dbg(ar, ATH10K_DBG_HTT, "htt rx cac running\n"); return false; @@ -1558,42 +1543,23 @@ __skb_queue_purge(amsdu); } -static void ath10k_htt_rx_handler(struct ath10k_htt *htt, - struct htt_rx_indication *rx) +static int ath10k_htt_rx_handle_amsdu(struct ath10k_htt *htt) { struct ath10k *ar = htt->ar; struct ieee80211_rx_status *rx_status = &htt->rx_status; - struct htt_rx_indication_mpdu_range *mpdu_ranges; struct sk_buff_head amsdu; - int num_mpdu_ranges; - int fw_desc_len; - u8 *fw_desc; - int i, ret, mpdu_count = 0; + int ret, num_msdus; - lockdep_assert_held(&htt->rx_ring.lock); - - if (htt->rx_confused) - return; - - fw_desc_len = __le16_to_cpu(rx->prefix.fw_rx_desc_bytes); - fw_desc = (u8 *)&rx->fw_desc; - - num_mpdu_ranges = MS(__le32_to_cpu(rx->hdr.info1), - HTT_RX_INDICATION_INFO1_NUM_MPDU_RANGES); - mpdu_ranges = htt_rx_ind_get_mpdu_ranges(rx); - - ath10k_dbg_dump(ar, ATH10K_DBG_HTT_DUMP, NULL, "htt rx ind: ", - rx, sizeof(*rx) + - (sizeof(struct htt_rx_indication_mpdu_range) * - num_mpdu_ranges)); + __skb_queue_head_init(&amsdu); - for (i = 0; i < num_mpdu_ranges; i++) - mpdu_count += mpdu_ranges[i].mpdu_count; + spin_lock_bh(&htt->rx_ring.lock); + if (htt->rx_confused) { + spin_unlock_bh(&htt->rx_ring.lock); + return -EIO; + } + ret = ath10k_htt_rx_amsdu_pop(htt, &amsdu); + spin_unlock_bh(&htt->rx_ring.lock); - while (mpdu_count--) { - __skb_queue_head_init(&amsdu); - ret = ath10k_htt_rx_amsdu_pop(htt, &fw_desc, - &fw_desc_len, &amsdu); if (ret < 0) { ath10k_warn(ar, "rx ring became corrupted: %d\n", ret); __skb_queue_purge(&amsdu); @@ -1601,69 +1567,43 @@ * device instead of leaving it inoperable. */ htt->rx_confused = true; - break; + return ret; } + num_msdus = skb_queue_len(&amsdu); ath10k_htt_rx_h_ppdu(ar, &amsdu, rx_status, 0xffff); ath10k_htt_rx_h_unchain(ar, &amsdu, ret > 0); ath10k_htt_rx_h_filter(ar, &amsdu, rx_status); ath10k_htt_rx_h_mpdu(ar, &amsdu, rx_status); ath10k_htt_rx_h_deliver(ar, &amsdu, rx_status); - } - tasklet_schedule(&htt->rx_replenish_task); + return num_msdus; } -static void ath10k_htt_rx_frag_handler(struct ath10k_htt *htt, - struct htt_rx_fragment_indication *frag) +static void ath10k_htt_rx_proc_rx_ind(struct ath10k_htt *htt, + struct htt_rx_indication *rx) { struct ath10k *ar = htt->ar; - struct ieee80211_rx_status *rx_status = &htt->rx_status; - struct sk_buff_head amsdu; - int ret; - u8 *fw_desc; - int fw_desc_len; - - fw_desc_len = __le16_to_cpu(frag->fw_rx_desc_bytes); - fw_desc = (u8 *)frag->fw_msdu_rx_desc; - - __skb_queue_head_init(&amsdu); - - spin_lock_bh(&htt->rx_ring.lock); - ret = ath10k_htt_rx_amsdu_pop(htt, &fw_desc, &fw_desc_len, - &amsdu); - spin_unlock_bh(&htt->rx_ring.lock); - - tasklet_schedule(&htt->rx_replenish_task); - - ath10k_dbg(ar, ATH10K_DBG_HTT_DUMP, "htt rx frag ahead\n"); + struct htt_rx_indication_mpdu_range *mpdu_ranges; + int num_mpdu_ranges; + int i, mpdu_count = 0; - if (ret) { - ath10k_warn(ar, "failed to pop amsdu from httr rx ring for fragmented rx %d\n", - ret); - __skb_queue_purge(&amsdu); - return; - } + num_mpdu_ranges = MS(__le32_to_cpu(rx->hdr.info1), + HTT_RX_INDICATION_INFO1_NUM_MPDU_RANGES); + mpdu_ranges = htt_rx_ind_get_mpdu_ranges(rx); - if (skb_queue_len(&amsdu) != 1) { - ath10k_warn(ar, "failed to pop frag amsdu: too many msdus\n"); - __skb_queue_purge(&amsdu); - return; - } + ath10k_dbg_dump(ar, ATH10K_DBG_HTT_DUMP, NULL, "htt rx ind: ", + rx, sizeof(*rx) + + (sizeof(struct htt_rx_indication_mpdu_range) * + num_mpdu_ranges)); - ath10k_htt_rx_h_ppdu(ar, &amsdu, rx_status, 0xffff); - ath10k_htt_rx_h_filter(ar, &amsdu, rx_status); - ath10k_htt_rx_h_mpdu(ar, &amsdu, rx_status); - ath10k_htt_rx_h_deliver(ar, &amsdu, rx_status); + for (i = 0; i < num_mpdu_ranges; i++) + mpdu_count += mpdu_ranges[i].mpdu_count; - if (fw_desc_len > 0) { - ath10k_dbg(ar, ATH10K_DBG_HTT, - "expecting more fragmented rx in one indication %d\n", - fw_desc_len); - } + atomic_add(mpdu_count, &htt->num_mpdus_ready); } -static void ath10k_htt_rx_frm_tx_compl(struct ath10k *ar, +static void ath10k_htt_rx_tx_compl_ind(struct ath10k *ar, struct sk_buff *skb) { struct ath10k_htt *htt = &ar->htt; @@ -1675,19 +1615,19 @@ switch (status) { case HTT_DATA_TX_STATUS_NO_ACK: - tx_done.no_ack = true; + tx_done.status = HTT_TX_COMPL_STATE_NOACK; break; case HTT_DATA_TX_STATUS_OK: - tx_done.success = true; + tx_done.status = HTT_TX_COMPL_STATE_ACK; break; case HTT_DATA_TX_STATUS_DISCARD: case HTT_DATA_TX_STATUS_POSTPONE: case HTT_DATA_TX_STATUS_DOWNLOAD_FAIL: - tx_done.discard = true; + tx_done.status = HTT_TX_COMPL_STATE_DISCARD; break; default: ath10k_warn(ar, "unhandled tx completion status %d\n", status); - tx_done.discard = true; + tx_done.status = HTT_TX_COMPL_STATE_DISCARD; break; } @@ -1697,9 +1637,22 @@ for (i = 0; i < resp->data_tx_completion.num_msdus; i++) { msdu_id = resp->data_tx_completion.msdus[i]; tx_done.msdu_id = __le16_to_cpu(msdu_id); + + /* kfifo_put: In practice firmware shouldn't fire off per-CE + * interrupt and main interrupt (MSI/-X range case) for the same + * HTC service so it should be safe to use kfifo_put w/o lock. + * + * From kfifo_put() documentation: + * Note that with only one concurrent reader and one concurrent + * writer, you don't need extra locking to use these macro. + */ + if (!kfifo_put(&htt->txdone_fifo, tx_done)) { + ath10k_warn(ar, "txdone fifo overrun, msdu_id %d status %d\n", + tx_done.msdu_id, tx_done.status); ath10k_txrx_tx_unref(htt, &tx_done); } } +} static void ath10k_htt_rx_addba(struct ath10k *ar, struct htt_resp *resp) { @@ -1781,7 +1734,8 @@ spin_unlock_bh(&ar->data_lock); } -static int ath10k_htt_rx_extract_amsdu(struct sk_buff_head *list, +static int ath10k_htt_rx_extract_amsdu(struct ath10k *ar, + struct sk_buff_head *list, struct sk_buff_head *amsdu) { struct sk_buff *msdu; @@ -1802,6 +1756,9 @@ break; } + if (QCA_REV_WCN3990(ar)) + return 0; + msdu = skb_peek_tail(amsdu); rxd = (void *)msdu->data - sizeof(*rxd); if (!(rxd->msdu_end.common.info0 & @@ -1832,7 +1789,7 @@ RX_FLAG_MMIC_STRIPPED; } -static void ath10k_htt_rx_h_rx_offload(struct ath10k *ar, +static int ath10k_htt_rx_h_rx_offload(struct ath10k *ar, struct sk_buff_head *list) { struct ath10k_htt *htt = &ar->htt; @@ -1840,6 +1797,7 @@ struct htt_rx_offload_msdu *rx; struct sk_buff *msdu; size_t offset; + int num_msdu = 0; while ((msdu = __skb_dequeue(list))) { /* Offloaded frames don't have Rx descriptor. Instead they have @@ -1879,10 +1837,12 @@ ath10k_htt_rx_h_rx_offload_prot(status, msdu); ath10k_htt_rx_h_channel(ar, status, NULL, rx->vdev_id); ath10k_process_rx(ar, status, msdu); + num_msdu++; } + return num_msdu; } -static void ath10k_htt_rx_in_ord_ind(struct ath10k *ar, struct sk_buff *skb) +static int ath10k_htt_rx_in_ord_ind(struct ath10k *ar, struct sk_buff *skb) { struct ath10k_htt *htt = &ar->htt; struct htt_resp *resp = (void *)skb->data; @@ -1895,12 +1855,12 @@ u8 tid; bool offload; bool frag; - int ret; + int ret, num_msdus = 0; lockdep_assert_held(&htt->rx_ring.lock); if (htt->rx_confused) - return; + return -EIO; skb_pull(skb, sizeof(resp->hdr)); skb_pull(skb, sizeof(resp->rx_in_ord_ind)); @@ -1919,7 +1879,7 @@ if (skb->len < msdu_count * sizeof(*resp->rx_in_ord_ind.msdu_descs)) { ath10k_warn(ar, "dropping invalid in order rx indication\n"); - return; + return -EINVAL; } /* The event can deliver more than 1 A-MSDU. Each A-MSDU is later @@ -1930,18 +1890,18 @@ if (ret < 0) { ath10k_warn(ar, "failed to pop paddr list: %d\n", ret); htt->rx_confused = true; - return; + return -EIO; } /* Offloaded frames are very different and need to be handled * separately. */ if (offload) - ath10k_htt_rx_h_rx_offload(ar, &list); + num_msdus = ath10k_htt_rx_h_rx_offload(ar, &list); while (!skb_queue_empty(&list)) { __skb_queue_head_init(&amsdu); - ret = ath10k_htt_rx_extract_amsdu(&list, &amsdu); + ret = ath10k_htt_rx_extract_amsdu(ar, &list, &amsdu); switch (ret) { case 0: /* Note: The in-order indication may report interleaved @@ -1950,6 +1910,7 @@ * better to report something than nothing though. This * should still give an idea about rx rate to the user. */ + num_msdus += skb_queue_len(&amsdu); ath10k_htt_rx_h_ppdu(ar, &amsdu, status, vdev_id); ath10k_htt_rx_h_filter(ar, &amsdu, status); ath10k_htt_rx_h_mpdu(ar, &amsdu, status); @@ -1962,14 +1923,299 @@ ath10k_warn(ar, "failed to extract amsdu: %d\n", ret); htt->rx_confused = true; __skb_queue_purge(&list); + return -EIO; + } + } + return num_msdus; +} + +static void ath10k_htt_rx_tx_fetch_resp_id_confirm(struct ath10k *ar, + const __le32 *resp_ids, + int num_resp_ids) +{ + int i; + u32 resp_id; + + ath10k_dbg(ar, ATH10K_DBG_HTT, "htt rx tx fetch confirm num_resp_ids %d\n", + num_resp_ids); + + for (i = 0; i < num_resp_ids; i++) { + resp_id = le32_to_cpu(resp_ids[i]); + + ath10k_dbg(ar, ATH10K_DBG_HTT, "htt rx tx fetch confirm resp_id %u\n", + resp_id); + + /* TODO: free resp_id */ + } +} + +static void ath10k_htt_rx_tx_fetch_ind(struct ath10k *ar, struct sk_buff *skb) +{ + struct ieee80211_hw *hw = ar->hw; + struct ieee80211_txq *txq; + struct htt_resp *resp = (struct htt_resp *)skb->data; + struct htt_tx_fetch_record *record; + size_t len; + size_t max_num_bytes; + size_t max_num_msdus; + size_t num_bytes; + size_t num_msdus; + const __le32 *resp_ids; + u16 num_records; + u16 num_resp_ids; + u16 peer_id; + u8 tid; + int ret; + int i; + + ath10k_dbg(ar, ATH10K_DBG_HTT, "htt rx tx fetch ind\n"); + + len = sizeof(resp->hdr) + sizeof(resp->tx_fetch_ind); + if (unlikely(skb->len < len)) { + ath10k_warn(ar, "received corrupted tx_fetch_ind event: buffer too short\n"); return; } + + num_records = le16_to_cpu(resp->tx_fetch_ind.num_records); + num_resp_ids = le16_to_cpu(resp->tx_fetch_ind.num_resp_ids); + + len += sizeof(resp->tx_fetch_ind.records[0]) * num_records; + len += sizeof(resp->tx_fetch_ind.resp_ids[0]) * num_resp_ids; + + if (unlikely(skb->len < len)) { + ath10k_warn(ar, "received corrupted tx_fetch_ind event: too many records/resp_ids\n"); + return; + } + + ath10k_dbg(ar, ATH10K_DBG_HTT, "htt rx tx fetch ind num records %hu num resps %hu seq %hu\n", + num_records, num_resp_ids, + le16_to_cpu(resp->tx_fetch_ind.fetch_seq_num)); + + if (!ar->htt.tx_q_state.enabled) { + ath10k_warn(ar, "received unexpected tx_fetch_ind event: not enabled\n"); + return; + } + + if (ar->htt.tx_q_state.mode == HTT_TX_MODE_SWITCH_PUSH) { + ath10k_warn(ar, "received unexpected tx_fetch_ind event: in push mode\n"); + return; + } + + rcu_read_lock(); + + for (i = 0; i < num_records; i++) { + record = &resp->tx_fetch_ind.records[i]; + peer_id = MS(le16_to_cpu(record->info), + HTT_TX_FETCH_RECORD_INFO_PEER_ID); + tid = MS(le16_to_cpu(record->info), + HTT_TX_FETCH_RECORD_INFO_TID); + max_num_msdus = le16_to_cpu(record->num_msdus); + max_num_bytes = le32_to_cpu(record->num_bytes); + + ath10k_dbg(ar, ATH10K_DBG_HTT, "htt rx tx fetch record %i peer_id %hu tid %hhu msdus %zu bytes %zu\n", + i, peer_id, tid, max_num_msdus, max_num_bytes); + + if (unlikely(peer_id >= ar->htt.tx_q_state.num_peers) || + unlikely(tid >= ar->htt.tx_q_state.num_tids)) { + ath10k_warn(ar, "received out of range peer_id %hu tid %hhu\n", + peer_id, tid); + continue; + } + + spin_lock_bh(&ar->data_lock); + txq = ath10k_mac_txq_lookup(ar, peer_id, tid); + spin_unlock_bh(&ar->data_lock); + + /* It is okay to release the lock and use txq because RCU read + * lock is held. + */ + + if (unlikely(!txq)) { + ath10k_warn(ar, "failed to lookup txq for peer_id %hu tid %hhu\n", + peer_id, tid); + continue; + } + + num_msdus = 0; + num_bytes = 0; + + while (num_msdus < max_num_msdus && + num_bytes < max_num_bytes) { + ret = ath10k_mac_tx_push_txq(hw, txq); + if (ret < 0) + break; + + num_msdus++; + num_bytes += ret; + } + + record->num_msdus = cpu_to_le16(num_msdus); + record->num_bytes = cpu_to_le32(num_bytes); + + ath10k_htt_tx_txq_recalc(hw, txq); + } + + rcu_read_unlock(); + + resp_ids = ath10k_htt_get_tx_fetch_ind_resp_ids(&resp->tx_fetch_ind); + ath10k_htt_rx_tx_fetch_resp_id_confirm(ar, resp_ids, num_resp_ids); + + ret = ath10k_htt_tx_fetch_resp(ar, + resp->tx_fetch_ind.token, + resp->tx_fetch_ind.fetch_seq_num, + resp->tx_fetch_ind.records, + num_records); + if (unlikely(ret)) { + ath10k_warn(ar, "failed to submit tx fetch resp for token 0x%08x: %d\n", + le32_to_cpu(resp->tx_fetch_ind.token), ret); + /* FIXME: request fw restart */ + } + + ath10k_htt_tx_txq_sync(ar); +} + +static void ath10k_htt_rx_tx_fetch_confirm(struct ath10k *ar, + struct sk_buff *skb) +{ + const struct htt_resp *resp = (void *)skb->data; + size_t len; + int num_resp_ids; + + ath10k_dbg(ar, ATH10K_DBG_HTT, "htt rx tx fetch confirm\n"); + + len = sizeof(resp->hdr) + sizeof(resp->tx_fetch_confirm); + if (unlikely(skb->len < len)) { + ath10k_warn(ar, "received corrupted tx_fetch_confirm event: buffer too short\n"); + return; + } + + num_resp_ids = le16_to_cpu(resp->tx_fetch_confirm.num_resp_ids); + len += sizeof(resp->tx_fetch_confirm.resp_ids[0]) * num_resp_ids; + + if (unlikely(skb->len < len)) { + ath10k_warn(ar, "received corrupted tx_fetch_confirm event: resp_ids buffer overflow\n"); + return; + } + + ath10k_htt_rx_tx_fetch_resp_id_confirm(ar, + resp->tx_fetch_confirm.resp_ids, + num_resp_ids); +} + +static void ath10k_htt_rx_tx_mode_switch_ind(struct ath10k *ar, + struct sk_buff *skb) +{ + const struct htt_resp *resp = (void *)skb->data; + const struct htt_tx_mode_switch_record *record; + struct ieee80211_txq *txq; + struct ath10k_txq *artxq; + size_t len; + size_t num_records; + enum htt_tx_mode_switch_mode mode; + bool enable; + u16 info0; + u16 info1; + u16 threshold; + u16 peer_id; + u8 tid; + int i; + + ath10k_dbg(ar, ATH10K_DBG_HTT, "htt rx tx mode switch ind\n"); + + len = sizeof(resp->hdr) + sizeof(resp->tx_mode_switch_ind); + if (unlikely(skb->len < len)) { + ath10k_warn(ar, "received corrupted tx_mode_switch_ind event: buffer too short\n"); + return; + } + + info0 = le16_to_cpu(resp->tx_mode_switch_ind.info0); + info1 = le16_to_cpu(resp->tx_mode_switch_ind.info1); + + enable = !!(info0 & HTT_TX_MODE_SWITCH_IND_INFO0_ENABLE); + num_records = MS(info0, HTT_TX_MODE_SWITCH_IND_INFO1_THRESHOLD); + mode = MS(info1, HTT_TX_MODE_SWITCH_IND_INFO1_MODE); + threshold = MS(info1, HTT_TX_MODE_SWITCH_IND_INFO1_THRESHOLD); + + ath10k_dbg(ar, ATH10K_DBG_HTT, + "htt rx tx mode switch ind info0 0x%04hx info1 0x%04hx enable %d num records %zd mode %d threshold %hu\n", + info0, info1, enable, num_records, mode, threshold); + + len += sizeof(resp->tx_mode_switch_ind.records[0]) * num_records; + + if (unlikely(skb->len < len)) { + ath10k_warn(ar, "received corrupted tx_mode_switch_mode_ind event: too many records\n"); + return; + } + + switch (mode) { + case HTT_TX_MODE_SWITCH_PUSH: + case HTT_TX_MODE_SWITCH_PUSH_PULL: + break; + default: + ath10k_warn(ar, "received invalid tx_mode_switch_mode_ind mode %d, ignoring\n", + mode); + return; + } + + if (!enable) + return; + + ar->htt.tx_q_state.enabled = enable; + ar->htt.tx_q_state.mode = mode; + ar->htt.tx_q_state.num_push_allowed = threshold; + + rcu_read_lock(); + + for (i = 0; i < num_records; i++) { + record = &resp->tx_mode_switch_ind.records[i]; + info0 = le16_to_cpu(record->info0); + peer_id = MS(info0, HTT_TX_MODE_SWITCH_RECORD_INFO0_PEER_ID); + tid = MS(info0, HTT_TX_MODE_SWITCH_RECORD_INFO0_TID); + + if (unlikely(peer_id >= ar->htt.tx_q_state.num_peers) || + unlikely(tid >= ar->htt.tx_q_state.num_tids)) { + ath10k_warn(ar, "received out of range peer_id %hu tid %hhu\n", + peer_id, tid); + continue; + } + + spin_lock_bh(&ar->data_lock); + txq = ath10k_mac_txq_lookup(ar, peer_id, tid); + spin_unlock_bh(&ar->data_lock); + + /* It is okay to release the lock and use txq because RCU read + * lock is held. + */ + + if (unlikely(!txq)) { + ath10k_warn(ar, "failed to lookup txq for peer_id %hu tid %hhu\n", + peer_id, tid); + continue; } - tasklet_schedule(&htt->rx_replenish_task); + spin_lock_bh(&ar->htt.tx_lock); + artxq = (void *)txq->drv_priv; + artxq->num_push_allowed = le16_to_cpu(record->num_max_msdus); + spin_unlock_bh(&ar->htt.tx_lock); } -void ath10k_htt_t2h_msg_handler(struct ath10k *ar, struct sk_buff *skb) + rcu_read_unlock(); + + ath10k_mac_tx_push_pending(ar); +} + +void ath10k_htt_htc_t2h_msg_handler(struct ath10k *ar, struct sk_buff *skb) +{ + bool release; + + release = ath10k_htt_t2h_msg_handler(ar, skb); + + /* Free the indication buffer */ + if (release) + dev_kfree_skb_any(skb); +} + +bool ath10k_htt_t2h_msg_handler(struct ath10k *ar, struct sk_buff *skb) { struct ath10k_htt *htt = &ar->htt; struct htt_resp *resp = (struct htt_resp *)skb->data; @@ -1985,8 +2231,7 @@ if (resp->hdr.msg_type >= ar->htt.t2h_msg_types_max) { ath10k_dbg(ar, ATH10K_DBG_HTT, "htt rx, unsupported msg_type: 0x%0X\n max: 0x%0X", resp->hdr.msg_type, ar->htt.t2h_msg_types_max); - dev_kfree_skb_any(skb); - return; + return true; } type = ar->htt.t2h_msg_types[resp->hdr.msg_type]; @@ -1998,11 +2243,8 @@ break; } case HTT_T2H_MSG_TYPE_RX_IND: - spin_lock_bh(&htt->rx_ring.lock); - __skb_queue_tail(&htt->rx_compl_q, skb); - spin_unlock_bh(&htt->rx_ring.lock); - tasklet_schedule(&htt->txrx_compl_task); - return; + ath10k_htt_rx_proc_rx_ind(htt, &resp->rx_ind); + break; case HTT_T2H_MSG_TYPE_PEER_MAP: { struct htt_peer_map_event ev = { .vdev_id = resp->peer_map.vdev_id, @@ -2023,28 +2265,31 @@ struct htt_tx_done tx_done = {}; int status = __le32_to_cpu(resp->mgmt_tx_completion.status); - tx_done.msdu_id = - __le32_to_cpu(resp->mgmt_tx_completion.desc_id); + tx_done.msdu_id = __le32_to_cpu(resp->mgmt_tx_completion.desc_id); switch (status) { case HTT_MGMT_TX_STATUS_OK: - tx_done.success = true; + tx_done.status = HTT_TX_COMPL_STATE_ACK; break; case HTT_MGMT_TX_STATUS_RETRY: - tx_done.no_ack = true; + tx_done.status = HTT_TX_COMPL_STATE_NOACK; break; case HTT_MGMT_TX_STATUS_DROP: - tx_done.discard = true; + tx_done.status = HTT_TX_COMPL_STATE_DISCARD; break; } - ath10k_txrx_tx_unref(htt, &tx_done); + status = ath10k_txrx_tx_unref(htt, &tx_done); + if (!status) { + spin_lock_bh(&htt->tx_lock); + ath10k_htt_tx_mgmt_dec_pending(htt); + spin_unlock_bh(&htt->tx_lock); + } break; } case HTT_T2H_MSG_TYPE_TX_COMPL_IND: - skb_queue_tail(&htt->tx_compl_q, skb); - tasklet_schedule(&htt->txrx_compl_task); - return; + ath10k_htt_rx_tx_compl_ind(htt->ar, skb); + break; case HTT_T2H_MSG_TYPE_SEC_IND: { struct ath10k *ar = htt->ar; struct htt_security_indication *ev = &resp->security_indication; @@ -2060,7 +2305,7 @@ case HTT_T2H_MSG_TYPE_RX_FRAG_IND: { ath10k_dbg_dump(ar, ATH10K_DBG_HTT_DUMP, NULL, "htt event: ", skb->data, skb->len); - ath10k_htt_rx_frag_handler(htt, &resp->rx_frag_ind); + atomic_inc(&htt->num_mpdus_ready); break; } case HTT_T2H_MSG_TYPE_TEST: @@ -2083,12 +2328,10 @@ ath10k_htt_rx_delba(ar, resp); break; case HTT_T2H_MSG_TYPE_PKTLOG: { - struct ath10k_pktlog_hdr *hdr = - (struct ath10k_pktlog_hdr *)resp->pktlog_msg.payload; - trace_ath10k_htt_pktlog(ar, resp->pktlog_msg.payload, - sizeof(*hdr) + - __le16_to_cpu(hdr->size)); + skb->len - + offsetof(struct htt_resp, + pktlog_msg.payload)); break; } case HTT_T2H_MSG_TYPE_RX_FLUSH: { @@ -2098,22 +2341,41 @@ break; } case HTT_T2H_MSG_TYPE_RX_IN_ORD_PADDR_IND: { - spin_lock_bh(&htt->rx_ring.lock); __skb_queue_tail(&htt->rx_in_ord_compl_q, skb); - spin_unlock_bh(&htt->rx_ring.lock); - tasklet_schedule(&htt->txrx_compl_task); - return; + return false; } case HTT_T2H_MSG_TYPE_TX_CREDIT_UPDATE_IND: break; - case HTT_T2H_MSG_TYPE_CHAN_CHANGE: + case HTT_T2H_MSG_TYPE_CHAN_CHANGE: { + u32 phymode = __le32_to_cpu(resp->chan_change.phymode); + u32 freq = __le32_to_cpu(resp->chan_change.freq); + + ar->tgt_oper_chan = + __ieee80211_get_channel(ar->hw->wiphy, freq); + ath10k_dbg(ar, ATH10K_DBG_HTT, + "htt chan change freq %u phymode %s\n", + freq, ath10k_wmi_phymode_str(phymode)); break; + } case HTT_T2H_MSG_TYPE_AGGR_CONF: break; + case HTT_T2H_MSG_TYPE_TX_FETCH_IND: { + struct sk_buff *tx_fetch_ind = skb_copy(skb, GFP_ATOMIC); + + if (!tx_fetch_ind) { + ath10k_warn(ar, "failed to copy htt tx fetch ind\n"); + break; + } + skb_queue_tail(&htt->tx_fetch_ind_q, tx_fetch_ind); + break; + } + case HTT_T2H_MSG_TYPE_TX_FETCH_CONFIRM: + ath10k_htt_rx_tx_fetch_confirm(ar, skb); + break; + case HTT_T2H_MSG_TYPE_TX_MODE_SWITCH_IND: + ath10k_htt_rx_tx_mode_switch_ind(ar, skb); + break; case HTT_T2H_MSG_TYPE_EN_STATS: - case HTT_T2H_MSG_TYPE_TX_FETCH_IND: - case HTT_T2H_MSG_TYPE_TX_FETCH_CONF: - case HTT_T2H_MSG_TYPE_TX_LOW_LATENCY_IND: default: ath10k_warn(ar, "htt event (%d) not handled\n", resp->hdr.msg_type); @@ -2121,34 +2383,116 @@ skb->data, skb->len); break; }; + return true; +} +EXPORT_SYMBOL(ath10k_htt_t2h_msg_handler); - /* Free the indication buffer */ +void ath10k_htt_rx_pktlog_completion_handler(struct ath10k *ar, + struct sk_buff *skb) +{ + trace_ath10k_htt_pktlog(ar, skb->data, skb->len); dev_kfree_skb_any(skb); } -EXPORT_SYMBOL(ath10k_htt_t2h_msg_handler); +EXPORT_SYMBOL(ath10k_htt_rx_pktlog_completion_handler); -static void ath10k_htt_txrx_compl_task(unsigned long ptr) +int ath10k_htt_txrx_compl_task(struct ath10k *ar, int budget) { - struct ath10k_htt *htt = (struct ath10k_htt *)ptr; - struct ath10k *ar = htt->ar; - struct htt_resp *resp; + struct ath10k_htt *htt = &ar->htt; + struct htt_tx_done tx_done = {}; + struct sk_buff_head tx_ind_q; struct sk_buff *skb; + unsigned long flags; + int quota = 0, done, num_rx_msdus; + bool resched_napi = false; - while ((skb = skb_dequeue(&htt->tx_compl_q))) { - ath10k_htt_rx_frm_tx_compl(htt->ar, skb); - dev_kfree_skb_any(skb); + __skb_queue_head_init(&tx_ind_q); + + /* Since in-ord-ind can deliver more than 1 A-MSDU in single event, + * process it first to utilize full available quota. + */ + while (quota < budget) { + if (skb_queue_empty(&htt->rx_in_ord_compl_q)) + break; + + skb = __skb_dequeue(&htt->rx_in_ord_compl_q); + if (!skb) { + resched_napi = true; + goto exit; } spin_lock_bh(&htt->rx_ring.lock); - while ((skb = __skb_dequeue(&htt->rx_compl_q))) { - resp = (struct htt_resp *)skb->data; - ath10k_htt_rx_handler(htt, &resp->rx_ind); + num_rx_msdus = ath10k_htt_rx_in_ord_ind(ar, skb); + spin_unlock_bh(&htt->rx_ring.lock); + if (num_rx_msdus < 0) { + resched_napi = true; + goto exit; + } + dev_kfree_skb_any(skb); + if (num_rx_msdus > 0) + quota += num_rx_msdus; + + if ((quota > ATH10K_NAPI_QUOTA_LIMIT) && + !skb_queue_empty(&htt->rx_in_ord_compl_q)) { + resched_napi = true; + goto exit; } + } + + while (quota < budget) { + /* no more data to receive */ + if (!atomic_read(&htt->num_mpdus_ready)) + break; + + num_rx_msdus = ath10k_htt_rx_handle_amsdu(htt); + if (num_rx_msdus < 0) { + resched_napi = true; + goto exit; + } + + quota += num_rx_msdus; + atomic_dec(&htt->num_mpdus_ready); + if ((quota > ATH10K_NAPI_QUOTA_LIMIT) && + atomic_read(&htt->num_mpdus_ready)) { + resched_napi = true; + goto exit; + } + } + + /* From NAPI documentation: + * The napi poll() function may also process TX completions, in which + * case if it processes the entire TX ring then it should count that + * work as the rest of the budget. + */ + if ((quota < budget) && !kfifo_is_empty(&htt->txdone_fifo)) + quota = budget; - while ((skb = __skb_dequeue(&htt->rx_in_ord_compl_q))) { - ath10k_htt_rx_in_ord_ind(ar, skb); + /* kfifo_get: called only within txrx_tasklet so it's neatly serialized. + * From kfifo_get() documentation: + * Note that with only one concurrent reader and one concurrent writer, + * you don't need extra locking to use these macro. + */ + while (kfifo_get(&htt->txdone_fifo, &tx_done)) + ath10k_txrx_tx_unref(htt, &tx_done); + + ath10k_mac_tx_push_pending(ar); + + spin_lock_irqsave(&htt->tx_fetch_ind_q.lock, flags); + skb_queue_splice_init(&htt->tx_fetch_ind_q, &tx_ind_q); + spin_unlock_irqrestore(&htt->tx_fetch_ind_q.lock, flags); + + while ((skb = __skb_dequeue(&tx_ind_q))) { + ath10k_htt_rx_tx_fetch_ind(ar, skb); dev_kfree_skb_any(skb); } - spin_unlock_bh(&htt->rx_ring.lock); + +exit: + ath10k_htt_rx_msdu_buff_replenish(htt); + /* In case of rx failure or more data to read, report budget + * to reschedule NAPI poll + */ + done = resched_napi ? budget : quota; + + return done; } +EXPORT_SYMBOL(ath10k_htt_txrx_compl_task); diff -ruw linux-4.4.115/drivers/net/wireless/ath/ath10k/htt_tx.c linux-4.4.115-fbx/drivers/net/wireless/ath/ath10k/htt_tx.c --- linux-4.4.115/drivers/net/wireless/ath/ath10k/htt_tx.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/net/wireless/ath/ath10k/htt_tx.c 2019-01-22 16:16:25.415263721 +0100 @@ -22,53 +22,185 @@ #include "txrx.h" #include "debug.h" -void __ath10k_htt_tx_dec_pending(struct ath10k_htt *htt, bool limit_mgmt_desc) +static u8 ath10k_htt_tx_txq_calc_size(size_t count) { - if (limit_mgmt_desc) - htt->num_pending_mgmt_tx--; + int exp; + int factor; - htt->num_pending_tx--; - if (htt->num_pending_tx == htt->max_num_pending_tx - 1) - ath10k_mac_tx_unlock(htt->ar, ATH10K_TX_PAUSE_Q_FULL); + exp = 0; + factor = count >> 7; + + while (factor >= 64 && exp < 4) { + factor >>= 3; + exp++; + } + + if (exp == 4) + return 0xff; + + if (count > 0) + factor = max(1, factor); + + return SM(exp, HTT_TX_Q_STATE_ENTRY_EXP) | + SM(factor, HTT_TX_Q_STATE_ENTRY_FACTOR); } -static void ath10k_htt_tx_dec_pending(struct ath10k_htt *htt, - bool limit_mgmt_desc) +static void __ath10k_htt_tx_txq_recalc(struct ieee80211_hw *hw, + struct ieee80211_txq *txq) { - spin_lock_bh(&htt->tx_lock); - __ath10k_htt_tx_dec_pending(htt, limit_mgmt_desc); - spin_unlock_bh(&htt->tx_lock); + struct ath10k *ar = hw->priv; + struct ath10k_sta *arsta; + struct ath10k_vif *arvif = (void *)txq->vif->drv_priv; + unsigned long frame_cnt; + unsigned long byte_cnt; + int idx; + u32 bit; + u16 peer_id; + u8 tid; + u8 count; + + lockdep_assert_held(&ar->htt.tx_lock); + + if (!ar->htt.tx_q_state.enabled) + return; + + if (ar->htt.tx_q_state.mode != HTT_TX_MODE_SWITCH_PUSH_PULL) + return; + + if (txq->sta) { + arsta = (void *)txq->sta->drv_priv; + peer_id = arsta->peer_id; + } else { + peer_id = arvif->peer_id; + } + + tid = txq->tid; + bit = BIT(peer_id % 32); + idx = peer_id / 32; + + ieee80211_txq_get_depth(txq, &frame_cnt, &byte_cnt); + count = ath10k_htt_tx_txq_calc_size(byte_cnt); + + if (unlikely(peer_id >= ar->htt.tx_q_state.num_peers) || + unlikely(tid >= ar->htt.tx_q_state.num_tids)) { + ath10k_warn(ar, "refusing to update txq for peer_id %hu tid %hhu due to out of bounds\n", + peer_id, tid); + return; + } + + ar->htt.tx_q_state.vaddr->count[tid][peer_id] = count; + ar->htt.tx_q_state.vaddr->map[tid][idx] &= ~bit; + ar->htt.tx_q_state.vaddr->map[tid][idx] |= count ? bit : 0; + + ath10k_dbg(ar, ATH10K_DBG_HTT, "htt tx txq state update peer_id %hu tid %hhu count %hhu\n", + peer_id, tid, count); } -static int ath10k_htt_tx_inc_pending(struct ath10k_htt *htt, - bool limit_mgmt_desc, bool is_probe_resp) +static void __ath10k_htt_tx_txq_sync(struct ath10k *ar) { - struct ath10k *ar = htt->ar; - int ret = 0; + u32 seq; + size_t size; - spin_lock_bh(&htt->tx_lock); + lockdep_assert_held(&ar->htt.tx_lock); + + if (!ar->htt.tx_q_state.enabled) + return; - if (htt->num_pending_tx >= htt->max_num_pending_tx) { - ret = -EBUSY; - goto exit; + if (ar->htt.tx_q_state.mode != HTT_TX_MODE_SWITCH_PUSH_PULL) + return; + + seq = le32_to_cpu(ar->htt.tx_q_state.vaddr->seq); + seq++; + ar->htt.tx_q_state.vaddr->seq = cpu_to_le32(seq); + + ath10k_dbg(ar, ATH10K_DBG_HTT, "htt tx txq state update commit seq %u\n", + seq); + + size = sizeof(*ar->htt.tx_q_state.vaddr); + dma_sync_single_for_device(ar->dev, + ar->htt.tx_q_state.paddr, + size, + DMA_TO_DEVICE); } - if (limit_mgmt_desc) { - if (is_probe_resp && (htt->num_pending_mgmt_tx > - ar->hw_params.max_probe_resp_desc_thres)) { - ret = -EBUSY; - goto exit; +void ath10k_htt_tx_txq_recalc(struct ieee80211_hw *hw, + struct ieee80211_txq *txq) +{ + struct ath10k *ar = hw->priv; + + spin_lock_bh(&ar->htt.tx_lock); + __ath10k_htt_tx_txq_recalc(hw, txq); + spin_unlock_bh(&ar->htt.tx_lock); } - htt->num_pending_mgmt_tx++; + +void ath10k_htt_tx_txq_sync(struct ath10k *ar) +{ + spin_lock_bh(&ar->htt.tx_lock); + __ath10k_htt_tx_txq_sync(ar); + spin_unlock_bh(&ar->htt.tx_lock); } +void ath10k_htt_tx_txq_update(struct ieee80211_hw *hw, + struct ieee80211_txq *txq) +{ + struct ath10k *ar = hw->priv; + + spin_lock_bh(&ar->htt.tx_lock); + __ath10k_htt_tx_txq_recalc(hw, txq); + __ath10k_htt_tx_txq_sync(ar); + spin_unlock_bh(&ar->htt.tx_lock); +} + +void ath10k_htt_tx_dec_pending(struct ath10k_htt *htt) +{ + lockdep_assert_held(&htt->tx_lock); + + htt->num_pending_tx--; + if (htt->num_pending_tx == htt->max_num_pending_tx - 1) + ath10k_mac_tx_unlock(htt->ar, ATH10K_TX_PAUSE_Q_FULL); +} + +int ath10k_htt_tx_inc_pending(struct ath10k_htt *htt) +{ + lockdep_assert_held(&htt->tx_lock); + + if (htt->num_pending_tx >= htt->max_num_pending_tx) + return -EBUSY; + htt->num_pending_tx++; if (htt->num_pending_tx == htt->max_num_pending_tx) ath10k_mac_tx_lock(htt->ar, ATH10K_TX_PAUSE_Q_FULL); -exit: - spin_unlock_bh(&htt->tx_lock); - return ret; + return 0; +} + +int ath10k_htt_tx_mgmt_inc_pending(struct ath10k_htt *htt, bool is_mgmt, + bool is_presp) +{ + struct ath10k *ar = htt->ar; + + lockdep_assert_held(&htt->tx_lock); + + if (!is_mgmt || !ar->hw_params.max_probe_resp_desc_thres) + return 0; + + if (is_presp && + ar->hw_params.max_probe_resp_desc_thres < htt->num_pending_mgmt_tx) + return -EBUSY; + + htt->num_pending_mgmt_tx++; + + return 0; +} + +void ath10k_htt_tx_mgmt_dec_pending(struct ath10k_htt *htt) +{ + lockdep_assert_held(&htt->tx_lock); + + if (!htt->ar->hw_params.max_probe_resp_desc_thres) + return; + + htt->num_pending_mgmt_tx--; } int ath10k_htt_tx_alloc_msdu_id(struct ath10k_htt *htt, struct sk_buff *skb) @@ -86,6 +218,27 @@ return ret; } +struct sk_buff *ath10k_htt_tx_find_msdu_by_id(struct ath10k_htt *htt, + u16 msdu_id) +{ + struct ath10k *ar; + struct sk_buff *ret; + + if (!htt) + return NULL; + + ar = htt->ar; + + lockdep_assert_held(&htt->tx_lock); + + ret = (struct sk_buff *)idr_find(&htt->pending_tx, msdu_id); + + ath10k_dbg(ar, ATH10K_DBG_HTT, "htt tx find msdu by msdu_id %s\n", + !ret ? "Failed" : "Success"); + + return ret; +} + void ath10k_htt_tx_free_msdu_id(struct ath10k_htt *htt, u16 msdu_id) { struct ath10k *ar = htt->ar; @@ -97,6 +250,87 @@ idr_remove(&htt->pending_tx, msdu_id); } +static void ath10k_htt_tx_free_cont_frag_desc(struct ath10k_htt *htt) +{ + size_t size; + + if (!htt->frag_desc.vaddr) + return; + + size = htt->max_num_pending_tx * sizeof(struct htt_msdu_ext_desc); + + dma_free_coherent(htt->ar->dev, + size, + htt->frag_desc.vaddr, + htt->frag_desc.paddr); +} + +static int ath10k_htt_tx_alloc_cont_frag_desc(struct ath10k_htt *htt) +{ + struct ath10k *ar = htt->ar; + size_t size; + + if (!ar->hw_params.continuous_frag_desc) + return 0; + + size = htt->max_num_pending_tx * sizeof(struct htt_msdu_ext_desc); + htt->frag_desc.vaddr = dma_alloc_coherent(ar->dev, size, + &htt->frag_desc.paddr, + GFP_KERNEL); + if (!htt->frag_desc.vaddr) { + ath10k_err(ar, "failed to alloc fragment desc memory\n"); + return -ENOMEM; + } + + return 0; +} + +static void ath10k_htt_tx_free_txq(struct ath10k_htt *htt) +{ + struct ath10k *ar = htt->ar; + size_t size; + + if (!test_bit(ATH10K_FW_FEATURE_PEER_FLOW_CONTROL, + ar->running_fw->fw_file.fw_features)) + return; + + size = sizeof(*htt->tx_q_state.vaddr); + + dma_unmap_single(ar->dev, htt->tx_q_state.paddr, size, DMA_TO_DEVICE); + kfree(htt->tx_q_state.vaddr); +} + +static int ath10k_htt_tx_alloc_txq(struct ath10k_htt *htt) +{ + struct ath10k *ar = htt->ar; + size_t size; + int ret; + + if (!test_bit(ATH10K_FW_FEATURE_PEER_FLOW_CONTROL, + ar->running_fw->fw_file.fw_features)) + return 0; + + htt->tx_q_state.num_peers = HTT_TX_Q_STATE_NUM_PEERS; + htt->tx_q_state.num_tids = HTT_TX_Q_STATE_NUM_TIDS; + htt->tx_q_state.type = HTT_Q_DEPTH_TYPE_BYTES; + + size = sizeof(*htt->tx_q_state.vaddr); + htt->tx_q_state.vaddr = kzalloc(size, GFP_KERNEL); + if (!htt->tx_q_state.vaddr) + return -ENOMEM; + + htt->tx_q_state.paddr = dma_map_single(ar->dev, htt->tx_q_state.vaddr, + size, DMA_TO_DEVICE); + ret = dma_mapping_error(ar->dev, htt->tx_q_state.paddr); + if (ret) { + ath10k_warn(ar, "failed to dma map tx_q_state: %d\n", ret); + kfree(htt->tx_q_state.vaddr); + return -EIO; + } + + return 0; +} + int ath10k_htt_tx_alloc(struct ath10k_htt *htt) { struct ath10k *ar = htt->ar; @@ -111,36 +345,49 @@ size = htt->max_num_pending_tx * sizeof(struct ath10k_htt_txbuf); htt->txbuf.vaddr = dma_alloc_coherent(ar->dev, size, &htt->txbuf.paddr, - GFP_DMA); + GFP_KERNEL); if (!htt->txbuf.vaddr) { ath10k_err(ar, "failed to alloc tx buffer\n"); ret = -ENOMEM; goto free_idr_pending_tx; } - if (!ar->hw_params.continuous_frag_desc) - goto skip_frag_desc_alloc; - - size = htt->max_num_pending_tx * sizeof(struct htt_msdu_ext_desc); - htt->frag_desc.vaddr = dma_alloc_coherent(ar->dev, size, - &htt->frag_desc.paddr, - GFP_DMA); - if (!htt->frag_desc.vaddr) { - ath10k_warn(ar, "failed to alloc fragment desc memory\n"); - ret = -ENOMEM; + ret = ath10k_htt_tx_alloc_cont_frag_desc(htt); + if (ret) { + ath10k_err(ar, "failed to alloc cont frag desc: %d\n", ret); goto free_txbuf; } -skip_frag_desc_alloc: + ret = ath10k_htt_tx_alloc_txq(htt); + if (ret) { + ath10k_err(ar, "failed to alloc txq: %d\n", ret); + goto free_frag_desc; + } + + size = roundup_pow_of_two(htt->max_num_pending_tx); + ret = kfifo_alloc(&htt->txdone_fifo, size, GFP_KERNEL); + if (ret) { + ath10k_err(ar, "failed to alloc txdone fifo: %d\n", ret); + goto free_txq; + } + return 0; +free_txq: + ath10k_htt_tx_free_txq(htt); + +free_frag_desc: + ath10k_htt_tx_free_cont_frag_desc(htt); + free_txbuf: size = htt->max_num_pending_tx * sizeof(struct ath10k_htt_txbuf); dma_free_coherent(htt->ar->dev, size, htt->txbuf.vaddr, htt->txbuf.paddr); + free_idr_pending_tx: idr_destroy(&htt->pending_tx); + return ret; } @@ -152,8 +399,8 @@ ath10k_dbg(ar, ATH10K_DBG_HTT, "force cleanup msdu_id %hu\n", msdu_id); - tx_done.discard = 1; tx_done.msdu_id = msdu_id; + tx_done.status = HTT_TX_COMPL_STATE_DISCARD; ath10k_txrx_tx_unref(htt, &tx_done); @@ -174,12 +421,10 @@ htt->txbuf.paddr); } - if (htt->frag_desc.vaddr) { - size = htt->max_num_pending_tx * - sizeof(struct htt_msdu_ext_desc); - dma_free_coherent(htt->ar->dev, size, htt->frag_desc.vaddr, - htt->frag_desc.paddr); - } + ath10k_htt_tx_free_txq(htt); + ath10k_htt_tx_free_cont_frag_desc(htt); + WARN_ON(!kfifo_is_empty(&htt->txdone_fifo)); + kfifo_free(&htt->txdone_fifo); } void ath10k_htt_htc_tx_complete(struct ath10k *ar, struct sk_buff *skb) @@ -263,12 +508,103 @@ return 0; } +#ifdef CONFIG_ATH10K_SNOC +static inline +void ath10k_htt_fill_rx_ring_cfg(struct ath10k_htt *htt, + struct htt_rx_ring_setup_ring *ring) +{ + ring->fw_idx_shadow_reg_paddr_low = + __cpu_to_le32(htt->rx_ring.alloc_idx.paddr); + ring->fw_idx_shadow_reg_paddr_high = 0; + ring->rx_ring_base_paddr_low = __cpu_to_le32(htt->rx_ring.base_paddr); + ring->rx_ring_base_paddr_high = upper_32_bits(htt->rx_ring.base_paddr) & + HTT_WCN3990_PADDR_MASK; +} + +static inline void ath10k_htt_fill_frags(struct htt_data_tx_desc_frag *frags, + struct sk_buff *msdu, + struct ath10k_skb_cb *skb_cb) +{ + frags[0].tword_addr.paddr_lo = __cpu_to_le32(skb_cb->paddr); + frags[0].tword_addr.paddr_hi = upper_32_bits(skb_cb->paddr) & + HTT_WCN3990_PADDR_MASK; + frags[0].tword_addr.len_16 = __cpu_to_le16(msdu->len); + frags[1].tword_addr.paddr_lo = 0; + frags[1].tword_addr.paddr_hi = 0; + frags[1].tword_addr.len_16 = 0; +} + +static inline void ath10k_htt_fill_frag_desc(struct ath10k_htt_txbuf *txbuf, + dma_addr_t frags_paddr) +{ + txbuf->cmd_tx.frags_paddr_lo = __cpu_to_le32(frags_paddr); + txbuf->cmd_tx.frags_paddr_hi = upper_32_bits(frags_paddr) & + HTT_WCN3990_PADDR_MASK; +} + +static inline +void ath10k_htt_set_bank_base_addr(struct htt_frag_desc_bank_cfg *cfg, + dma_addr_t paddr) +{ + cfg->bank_base_addrs[0].low = __cpu_to_le32(paddr); + cfg->bank_base_addrs[0].high = upper_32_bits(paddr) & + HTT_WCN3990_PADDR_MASK; +} + +static inline +u32 ath10k_htt_get_paddr_hi(dma_addr_t paddr) +{ + return(upper_32_bits(paddr) & + HTT_WCN3990_PADDR_MASK); +} +#else +static inline void ath10k_htt_fill_frags(struct htt_data_tx_desc_frag *frags, + struct sk_buff *msdu, + struct ath10k_skb_cb *skb_cb) +{ + frags[0].dword_addr.paddr = __cpu_to_le32(skb_cb->paddr); + frags[0].dword_addr.len = __cpu_to_le32(msdu->len); + frags[1].dword_addr.paddr = 0; + frags[1].dword_addr.len = 0; +} + +static inline void ath10k_htt_fill_frag_desc(struct ath10k_htt_txbuf *txbuf, + dma_addr_t frags_paddr) +{ + txbuf->cmd_tx.frags_paddr = __cpu_to_le32(frags_paddr); +} + +static inline +void ath10k_htt_set_bank_base_addr(struct htt_frag_desc_bank_cfg *cfg, + dma_addr_t paddr) +{ + cfg->bank_base_addrs[0] = __cpu_to_le32(paddr); +} + +static inline +void ath10k_htt_fill_rx_ring_cfg(struct ath10k_htt *htt, + struct htt_rx_ring_setup_ring *ring) +{ + ring->fw_idx_shadow_reg_paddr = + __cpu_to_le32(htt->rx_ring.alloc_idx.paddr); + ring->rx_ring_base_paddr = __cpu_to_le32(htt->rx_ring.base_paddr); +} + +static inline +u32 ath10k_htt_get_paddr_hi(dma_addr_t paddr) +{ + return 0; +} +#endif + int ath10k_htt_send_frag_desc_bank_cfg(struct ath10k_htt *htt) { struct ath10k *ar = htt->ar; struct sk_buff *skb; struct htt_cmd *cmd; + struct htt_frag_desc_bank_cfg *cfg; int ret, size; + u8 info; if (!ar->hw_params.continuous_frag_desc) return 0; @@ -286,14 +622,31 @@ skb_put(skb, size); cmd = (struct htt_cmd *)skb->data; cmd->hdr.msg_type = HTT_H2T_MSG_TYPE_FRAG_DESC_BANK_CFG; - cmd->frag_desc_bank_cfg.info = 0; - cmd->frag_desc_bank_cfg.num_banks = 1; - cmd->frag_desc_bank_cfg.desc_size = sizeof(struct htt_msdu_ext_desc); - cmd->frag_desc_bank_cfg.bank_base_addrs[0] = - __cpu_to_le32(htt->frag_desc.paddr); - cmd->frag_desc_bank_cfg.bank_id[0].bank_min_id = 0; - cmd->frag_desc_bank_cfg.bank_id[0].bank_max_id = - __cpu_to_le16(htt->max_num_pending_tx - 1); + + info = 0; + info |= SM(htt->tx_q_state.type, + HTT_FRAG_DESC_BANK_CFG_INFO_Q_STATE_DEPTH_TYPE); + + if (test_bit(ATH10K_FW_FEATURE_PEER_FLOW_CONTROL, + ar->running_fw->fw_file.fw_features)) + info |= HTT_FRAG_DESC_BANK_CFG_INFO_Q_STATE_VALID; + + cfg = &cmd->frag_desc_bank_cfg; + cfg->info = info; + cfg->num_banks = 1; + cfg->desc_size = sizeof(struct htt_msdu_ext_desc); + ath10k_htt_set_bank_base_addr(cfg, htt->frag_desc.paddr); + cfg->bank_id[0].bank_min_id = 0; + cfg->bank_id[0].bank_max_id = __cpu_to_le16(htt->max_num_pending_tx - + 1); + + cfg->q_state.paddr = cpu_to_le32(htt->tx_q_state.paddr); + cfg->q_state.num_peers = cpu_to_le16(htt->tx_q_state.num_peers); + cfg->q_state.num_tids = cpu_to_le16(htt->tx_q_state.num_tids); + cfg->q_state.record_size = HTT_TX_Q_STATE_ENTRY_SIZE; + cfg->q_state.record_multiplier = HTT_TX_Q_STATE_ENTRY_MULTIPLIER; + + ath10k_dbg(ar, ATH10K_DBG_HTT, "htt frag desc bank cmd\n"); ret = ath10k_htc_send(&htt->ar->htc, htt->eid, skb); if (ret) { @@ -360,9 +713,7 @@ fw_idx = __le32_to_cpu(*htt->rx_ring.alloc_idx.vaddr); - ring->fw_idx_shadow_reg_paddr = - __cpu_to_le32(htt->rx_ring.alloc_idx.paddr); - ring->rx_ring_base_paddr = __cpu_to_le32(htt->rx_ring.base_paddr); + ath10k_htt_fill_rx_ring_cfg(htt, ring); ring->rx_ring_len = __cpu_to_le16(htt->rx_ring.size); ring->rx_ring_bufsize = __cpu_to_le16(HTT_RX_BUF_SIZE); ring->flags = __cpu_to_le16(flags); @@ -439,6 +790,86 @@ return 0; } +int ath10k_htt_tx_fetch_resp(struct ath10k *ar, + __le32 token, + __le16 fetch_seq_num, + struct htt_tx_fetch_record *records, + size_t num_records) +{ + struct sk_buff *skb; + struct htt_cmd *cmd; + const u16 resp_id = 0; + int len = 0; + int ret; + + /* Response IDs are echo-ed back only for host driver convienence + * purposes. They aren't used for anything in the driver yet so use 0. + */ + + len += sizeof(cmd->hdr); + len += sizeof(cmd->tx_fetch_resp); + len += sizeof(cmd->tx_fetch_resp.records[0]) * num_records; + + skb = ath10k_htc_alloc_skb(ar, len); + if (!skb) + return -ENOMEM; + + skb_put(skb, len); + cmd = (struct htt_cmd *)skb->data; + cmd->hdr.msg_type = HTT_H2T_MSG_TYPE_TX_FETCH_RESP; + cmd->tx_fetch_resp.resp_id = cpu_to_le16(resp_id); + cmd->tx_fetch_resp.fetch_seq_num = fetch_seq_num; + cmd->tx_fetch_resp.num_records = cpu_to_le16(num_records); + cmd->tx_fetch_resp.token = token; + + memcpy(cmd->tx_fetch_resp.records, records, + sizeof(records[0]) * num_records); + + ret = ath10k_htc_send(&ar->htc, ar->htt.eid, skb); + if (ret) { + ath10k_warn(ar, "failed to submit htc command: %d\n", ret); + goto err_free_skb; + } + + return 0; + +err_free_skb: + dev_kfree_skb_any(skb); + + return ret; +} + +static u8 ath10k_htt_tx_get_vdev_id(struct ath10k *ar, struct sk_buff *skb) +{ + struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); + struct ath10k_skb_cb *cb = ATH10K_SKB_CB(skb); + struct ath10k_vif *arvif; + + if (info->flags & IEEE80211_TX_CTL_TX_OFFCHAN) { + return ar->scan.vdev_id; + } else if (cb->vif) { + arvif = (void *)cb->vif->drv_priv; + return arvif->vdev_id; + } else if (ar->monitor_started) { + return ar->monitor_vdev_id; + } else { + return 0; + } +} + +static u8 ath10k_htt_tx_get_tid(struct sk_buff *skb, bool is_eth) +{ + struct ieee80211_hdr *hdr = (void *)skb->data; + struct ath10k_skb_cb *cb = ATH10K_SKB_CB(skb); + + if (!is_eth && ieee80211_is_mgmt(hdr->frame_control)) + return HTT_DATA_TX_EXT_TID_MGMT; + else if (cb->flags & ATH10K_SKB_F_QOS) + return skb->priority % IEEE80211_QOS_CTL_TID_MASK; + else + return HTT_DATA_TX_EXT_TID_NON_QOS_MCAST_BCAST; +} + int ath10k_htt_mgmt_tx(struct ath10k_htt *htt, struct sk_buff *msdu) { struct ath10k *ar = htt->ar; @@ -446,25 +877,11 @@ struct sk_buff *txdesc = NULL; struct htt_cmd *cmd; struct ath10k_skb_cb *skb_cb = ATH10K_SKB_CB(msdu); - u8 vdev_id = skb_cb->vdev_id; + u8 vdev_id = ath10k_htt_tx_get_vdev_id(ar, msdu); int len = 0; int msdu_id = -1; int res; struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)msdu->data; - bool limit_mgmt_desc = false; - bool is_probe_resp = false; - - if (ar->hw_params.max_probe_resp_desc_thres) { - limit_mgmt_desc = true; - - if (ieee80211_is_probe_resp(hdr->frame_control)) - is_probe_resp = true; - } - - res = ath10k_htt_tx_inc_pending(htt, limit_mgmt_desc, is_probe_resp); - - if (res) - goto err; len += sizeof(cmd->hdr); len += sizeof(cmd->mgmt_tx); @@ -473,10 +890,17 @@ res = ath10k_htt_tx_alloc_msdu_id(htt, msdu); spin_unlock_bh(&htt->tx_lock); if (res < 0) - goto err_tx_dec; + goto err; msdu_id = res; + if ((ieee80211_is_action(hdr->frame_control) || + ieee80211_is_deauth(hdr->frame_control) || + ieee80211_is_disassoc(hdr->frame_control)) && + ieee80211_has_protected(hdr->frame_control)) { + skb_put(msdu, IEEE80211_CCMP_MIC_LEN); + } + txdesc = ath10k_htc_alloc_skb(ar, len); if (!txdesc) { res = -ENOMEM; @@ -503,8 +927,6 @@ memcpy(cmd->mgmt_tx.hdr, msdu->data, min_t(int, msdu->len, HTT_MGMT_FRM_HDR_DOWNLOAD_LEN)); - skb_cb->htt.txbuf = NULL; - res = ath10k_htc_send(&htt->ar->htc, htt->eid, txdesc); if (res) goto err_unmap_msdu; @@ -519,56 +941,46 @@ spin_lock_bh(&htt->tx_lock); ath10k_htt_tx_free_msdu_id(htt, msdu_id); spin_unlock_bh(&htt->tx_lock); -err_tx_dec: - ath10k_htt_tx_dec_pending(htt, limit_mgmt_desc); err: return res; } -int ath10k_htt_tx(struct ath10k_htt *htt, struct sk_buff *msdu) +int ath10k_htt_tx(struct ath10k_htt *htt, enum ath10k_hw_txrx_mode txmode, + struct sk_buff *msdu) { struct ath10k *ar = htt->ar; struct device *dev = ar->dev; struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)msdu->data; + struct ieee80211_tx_info *info = IEEE80211_SKB_CB(msdu); struct ath10k_skb_cb *skb_cb = ATH10K_SKB_CB(msdu); struct ath10k_hif_sg_item sg_items[2]; + struct ath10k_htt_txbuf *txbuf; struct htt_data_tx_desc_frag *frags; - u8 vdev_id = skb_cb->vdev_id; - u8 tid = skb_cb->htt.tid; + bool is_eth = (txmode == ATH10K_HW_TXRX_ETHERNET); + u8 vdev_id = ath10k_htt_tx_get_vdev_id(ar, msdu); + u8 tid = ath10k_htt_tx_get_tid(msdu, is_eth); int prefetch_len; int res; u8 flags0 = 0; u16 msdu_id, flags1 = 0; - u32 frags_paddr = 0; + u16 freq = 0; + dma_addr_t frags_paddr = 0; + u32 txbuf_paddr; struct htt_msdu_ext_desc *ext_desc = NULL; - bool limit_mgmt_desc = false; - bool is_probe_resp = false; - - if (unlikely(ieee80211_is_mgmt(hdr->frame_control)) && - ar->hw_params.max_probe_resp_desc_thres) { - limit_mgmt_desc = true; - - if (ieee80211_is_probe_resp(hdr->frame_control)) - is_probe_resp = true; - } - - res = ath10k_htt_tx_inc_pending(htt, limit_mgmt_desc, is_probe_resp); - if (res) - goto err; spin_lock_bh(&htt->tx_lock); res = ath10k_htt_tx_alloc_msdu_id(htt, msdu); spin_unlock_bh(&htt->tx_lock); if (res < 0) - goto err_tx_dec; + goto err; msdu_id = res; prefetch_len = min(htt->prefetch_len, msdu->len); prefetch_len = roundup(prefetch_len, 4); - skb_cb->htt.txbuf = &htt->txbuf.vaddr[msdu_id]; - skb_cb->htt.txbuf_paddr = htt->txbuf.paddr + + txbuf = &htt->txbuf.vaddr[msdu_id]; + txbuf_paddr = htt->txbuf.paddr + (sizeof(struct ath10k_htt_txbuf) * msdu_id); if ((ieee80211_is_action(hdr->frame_control) || @@ -576,8 +988,8 @@ ieee80211_is_disassoc(hdr->frame_control)) && ieee80211_has_protected(hdr->frame_control)) { skb_put(msdu, IEEE80211_CCMP_MIC_LEN); - } else if (!skb_cb->htt.nohwcrypt && - skb_cb->txmode == ATH10K_HW_TXRX_RAW && + } else if (!(skb_cb->flags & ATH10K_SKB_F_NO_HWCRYPT) && + txmode == ATH10K_HW_TXRX_RAW && ieee80211_has_protected(hdr->frame_control)) { skb_put(msdu, IEEE80211_CCMP_MIC_LEN); } @@ -590,7 +1002,10 @@ goto err_free_msdu_id; } - switch (skb_cb->txmode) { + if (unlikely(info->flags & IEEE80211_TX_CTL_TX_OFFCHAN)) + freq = ar->scan.roc_freq; + + switch (txmode) { case ATH10K_HW_TXRX_RAW: case ATH10K_HW_TXRX_NATIVE_WIFI: flags0 |= HTT_DATA_TX_DESC_FLAGS0_MAC_HDR_PRESENT; @@ -604,22 +1019,18 @@ ext_desc = &htt->frag_desc.vaddr[msdu_id]; frags[0].tword_addr.paddr_lo = __cpu_to_le32(skb_cb->paddr); - frags[0].tword_addr.paddr_hi = 0; + frags[0].tword_addr.paddr_hi = + ath10k_htt_get_paddr_hi(skb_cb->paddr); frags[0].tword_addr.len_16 = __cpu_to_le16(msdu->len); frags_paddr = htt->frag_desc.paddr + (sizeof(struct htt_msdu_ext_desc) * msdu_id); } else { - frags = skb_cb->htt.txbuf->frags; - frags[0].dword_addr.paddr = - __cpu_to_le32(skb_cb->paddr); - frags[0].dword_addr.len = __cpu_to_le32(msdu->len); - frags[1].dword_addr.paddr = 0; - frags[1].dword_addr.len = 0; - - frags_paddr = skb_cb->htt.txbuf_paddr; + frags = txbuf->frags; + ath10k_htt_fill_frags(frags, msdu, skb_cb); + frags_paddr = txbuf_paddr; } - flags0 |= SM(skb_cb->txmode, HTT_DATA_TX_DESC_FLAGS0_PKT_TYPE); + flags0 |= SM(txmode, HTT_DATA_TX_DESC_FLAGS0_PKT_TYPE); break; case ATH10K_HW_TXRX_MGMT: flags0 |= SM(ATH10K_HW_TXRX_MGMT, @@ -646,17 +1057,13 @@ * avoid extra memory allocations, compress data structures and thus * improve performance. */ - skb_cb->htt.txbuf->htc_hdr.eid = htt->eid; - skb_cb->htt.txbuf->htc_hdr.len = __cpu_to_le16( - sizeof(skb_cb->htt.txbuf->cmd_hdr) + - sizeof(skb_cb->htt.txbuf->cmd_tx) + + txbuf->htc_hdr.eid = htt->eid; + txbuf->htc_hdr.len = __cpu_to_le16(sizeof(txbuf->cmd_hdr) + + sizeof(txbuf->cmd_tx) + prefetch_len); - skb_cb->htt.txbuf->htc_hdr.flags = 0; - - if (skb_cb->htt.nohwcrypt) - flags0 |= HTT_DATA_TX_DESC_FLAGS0_NO_ENCRYPT; + txbuf->htc_hdr.flags = 0; - if (!skb_cb->is_protected) + if (skb_cb->flags & ATH10K_SKB_F_NO_HWCRYPT) flags0 |= HTT_DATA_TX_DESC_FLAGS0_NO_ENCRYPT; flags1 |= SM((u16)vdev_id, HTT_DATA_TX_DESC_FLAGS1_VDEV_ID); @@ -665,8 +1072,14 @@ !test_bit(ATH10K_FLAG_RAW_MODE, &ar->dev_flags)) { flags1 |= HTT_DATA_TX_DESC_FLAGS1_CKSUM_L3_OFFLOAD; flags1 |= HTT_DATA_TX_DESC_FLAGS1_CKSUM_L4_OFFLOAD; - if (ar->hw_params.continuous_frag_desc) + if (ar->hw_params.continuous_frag_desc) { ext_desc->flags |= HTT_MSDU_CHECKSUM_ENABLE; + if (QCA_REV_WCN3990(ar)) { + memset(ext_desc->tso_flag, 0, + sizeof(ext_desc->tso_flag)); + ext_desc->tso_flag[3] |= HTT_TX_CHECKSUM_ENABLE; + } + } } /* Prevent firmware from sending up tx inspection requests. There's @@ -675,20 +1088,29 @@ */ flags1 |= HTT_DATA_TX_DESC_FLAGS1_POSTPONED; - skb_cb->htt.txbuf->cmd_hdr.msg_type = HTT_H2T_MSG_TYPE_TX_FRM; - skb_cb->htt.txbuf->cmd_tx.flags0 = flags0; - skb_cb->htt.txbuf->cmd_tx.flags1 = __cpu_to_le16(flags1); - skb_cb->htt.txbuf->cmd_tx.len = __cpu_to_le16(msdu->len); - skb_cb->htt.txbuf->cmd_tx.id = __cpu_to_le16(msdu_id); - skb_cb->htt.txbuf->cmd_tx.frags_paddr = __cpu_to_le32(frags_paddr); - skb_cb->htt.txbuf->cmd_tx.peerid = __cpu_to_le16(HTT_INVALID_PEERID); - skb_cb->htt.txbuf->cmd_tx.freq = __cpu_to_le16(skb_cb->htt.freq); + txbuf->cmd_hdr.msg_type = HTT_H2T_MSG_TYPE_TX_FRM; + txbuf->cmd_tx.flags0 = flags0; + txbuf->cmd_tx.flags1 = __cpu_to_le16(flags1); + txbuf->cmd_tx.len = __cpu_to_le16(msdu->len); + txbuf->cmd_tx.id = __cpu_to_le16(msdu_id); + + /* fill fragment descriptor */ + ath10k_htt_fill_frag_desc(txbuf, frags_paddr); + if (ath10k_mac_tx_frm_has_freq(ar)) { + txbuf->cmd_tx.offchan_tx.peerid = + __cpu_to_le16(HTT_INVALID_PEERID); + txbuf->cmd_tx.offchan_tx.freq = + __cpu_to_le16(freq); + } else { + txbuf->cmd_tx.peerid = + __cpu_to_le32(HTT_INVALID_PEERID); + } trace_ath10k_htt_tx(ar, msdu_id, msdu->len, vdev_id, tid); ath10k_dbg(ar, ATH10K_DBG_HTT, - "htt tx flags0 %hhu flags1 %hu len %d id %hu frags_paddr %08x, msdu_paddr %08x vdev %hhu tid %hhu freq %hu\n", - flags0, flags1, msdu->len, msdu_id, frags_paddr, - (u32)skb_cb->paddr, vdev_id, tid, skb_cb->htt.freq); + "htt tx flags0 %hhu flags1 %hu len %d id %hu frags_paddr %pad, msdu_paddr %pad vdev %hhu tid %hhu freq %hu\n", + flags0, flags1, msdu->len, msdu_id, &frags_paddr, + &skb_cb->paddr, vdev_id, tid, freq); ath10k_dbg_dump(ar, ATH10K_DBG_HTT_DUMP, NULL, "htt tx msdu: ", msdu->data, msdu->len); trace_ath10k_tx_hdr(ar, msdu->data, msdu->len); @@ -696,12 +1118,12 @@ sg_items[0].transfer_id = 0; sg_items[0].transfer_context = NULL; - sg_items[0].vaddr = &skb_cb->htt.txbuf->htc_hdr; - sg_items[0].paddr = skb_cb->htt.txbuf_paddr + - sizeof(skb_cb->htt.txbuf->frags); - sg_items[0].len = sizeof(skb_cb->htt.txbuf->htc_hdr) + - sizeof(skb_cb->htt.txbuf->cmd_hdr) + - sizeof(skb_cb->htt.txbuf->cmd_tx); + sg_items[0].vaddr = &txbuf->htc_hdr; + sg_items[0].paddr = txbuf_paddr + + sizeof(txbuf->frags); + sg_items[0].len = sizeof(txbuf->htc_hdr) + + sizeof(txbuf->cmd_hdr) + + sizeof(txbuf->cmd_tx); sg_items[1].transfer_id = 0; sg_items[1].transfer_context = NULL; @@ -720,11 +1142,7 @@ err_unmap_msdu: dma_unmap_single(dev, skb_cb->paddr, msdu->len, DMA_TO_DEVICE); err_free_msdu_id: - spin_lock_bh(&htt->tx_lock); ath10k_htt_tx_free_msdu_id(htt, msdu_id); - spin_unlock_bh(&htt->tx_lock); -err_tx_dec: - ath10k_htt_tx_dec_pending(htt, limit_mgmt_desc); err: return res; } diff -ruw linux-4.4.115/drivers/net/wireless/ath/ath10k/hw.c linux-4.4.115-fbx/drivers/net/wireless/ath/ath10k/hw.c --- linux-4.4.115/drivers/net/wireless/ath/ath10k/hw.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/net/wireless/ath/ath10k/hw.c 2019-10-29 09:26:24.457211144 +0100 @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014-2015 Qualcomm Atheros, Inc. + * Copyright (c) 2014-2015, 2017 Qualcomm Atheros, Inc. * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above @@ -19,7 +19,6 @@ #include "hw.h" const struct ath10k_hw_regs qca988x_regs = { - .rtc_state_cold_reset_mask = 0x00000400, .rtc_soc_base_address = 0x00004000, .rtc_wmac_base_address = 0x00005000, .soc_core_base_address = 0x00009000, @@ -46,7 +45,6 @@ }; const struct ath10k_hw_regs qca6174_regs = { - .rtc_state_cold_reset_mask = 0x00002000, .rtc_soc_base_address = 0x00000800, .rtc_wmac_base_address = 0x00001000, .soc_core_base_address = 0x0003a000, @@ -73,7 +71,6 @@ }; const struct ath10k_hw_regs qca99x0_regs = { - .rtc_state_cold_reset_mask = 0x00000400, .rtc_soc_base_address = 0x00080000, .rtc_wmac_base_address = 0x00000000, .soc_core_base_address = 0x00082000, @@ -88,7 +85,7 @@ .ce7_base_address = 0x0004bc00, /* Note: qca99x0 supports upto 12 Copy Engines. Other than address of * CE0 and CE1 no other copy engine is directly referred in the code. - * It is not really neccessary to assign address for newly supported + * It is not really necessary to assign address for newly supported * CEs in this address table. * Copy Engine Address * CE8 0x0004c000 @@ -109,7 +106,368 @@ .pcie_intr_clr_address = 0x00000010, }; +const struct ath10k_hw_regs qca4019_regs = { + .rtc_soc_base_address = 0x00080000, + .soc_core_base_address = 0x00082000, + .ce_wrapper_base_address = 0x0004d000, + .ce0_base_address = 0x0004a000, + .ce1_base_address = 0x0004a400, + .ce2_base_address = 0x0004a800, + .ce3_base_address = 0x0004ac00, + .ce4_base_address = 0x0004b000, + .ce5_base_address = 0x0004b400, + .ce6_base_address = 0x0004b800, + .ce7_base_address = 0x0004bc00, + /* qca4019 supports upto 12 copy engines. Since base address + * of ce8 to ce11 are not directly referred in the code, + * no need have them in separate members in this table. + * Copy Engine Address + * CE8 0x0004c000 + * CE9 0x0004c400 + * CE10 0x0004c800 + * CE11 0x0004cc00 + */ + .soc_reset_control_si0_rst_mask = 0x00000001, + .soc_reset_control_ce_rst_mask = 0x00000100, + .soc_chip_id_address = 0x000000ec, + .fw_indicator_address = 0x0004f00c, + .ce_wrap_intr_sum_host_msi_lsb = 0x0000000c, + .ce_wrap_intr_sum_host_msi_mask = 0x00fff000, + .pcie_intr_fw_mask = 0x00100000, + .pcie_intr_ce_mask_all = 0x000fff00, + .pcie_intr_clr_address = 0x00000010, +}; + +const struct ath10k_hw_regs wcn3990_regs = { + .rtc_soc_base_address = 0x00000000, + .rtc_wmac_base_address = 0x00000000, + .soc_core_base_address = 0x00000000, + .ce_wrapper_base_address = 0x0024C000, + .soc_global_reset_address = 0x00000008, + .ce0_base_address = 0x00240000, + .ce1_base_address = 0x00241000, + .ce2_base_address = 0x00242000, + .ce3_base_address = 0x00243000, + .ce4_base_address = 0x00244000, + .ce5_base_address = 0x00245000, + .ce6_base_address = 0x00246000, + .ce7_base_address = 0x00247000, + .ce8_base_address = 0x00248000, + .ce9_base_address = 0x00249000, + .ce10_base_address = 0x0024A000, + .ce11_base_address = 0x0024B000, + .soc_chip_id_address = 0x000000f0, + .soc_reset_control_si0_rst_mask = 0x00000001, + .soc_reset_control_ce_rst_mask = 0x00000100, + .ce_wrap_intr_sum_host_msi_lsb = 0x0000000c, + .ce_wrap_intr_sum_host_msi_mask = 0x00fff000, + .pcie_intr_fw_mask = 0x00100000, +}; + +static unsigned int +ath10k_set_ring_byte(unsigned int offset, + struct ath10k_hw_ce_regs_addr_map *addr_map) +{ + return (((0 | (offset)) << addr_map->lsb) & addr_map->mask); +} + +static unsigned int +ath10k_get_ring_byte(unsigned int offset, + struct ath10k_hw_ce_regs_addr_map *addr_map) +{ + return (((offset) & addr_map->mask) >> (addr_map->lsb)); +} + +struct ath10k_hw_ce_regs_addr_map wcn3990_src_ring = { + .msb = 0x00000010, + .lsb = 0x00000010, + .mask = 0x00020000, + .set = &ath10k_set_ring_byte, + .get = &ath10k_get_ring_byte, +}; + +struct ath10k_hw_ce_regs_addr_map wcn3990_dst_ring = { + .msb = 0x00000012, + .lsb = 0x00000012, + .mask = 0x00040000, + .set = &ath10k_set_ring_byte, + .get = &ath10k_get_ring_byte, +}; + +struct ath10k_hw_ce_regs_addr_map wcn3990_dmax = { + .msb = 0x00000000, + .lsb = 0x00000000, + .mask = 0x0000ffff, + .set = &ath10k_set_ring_byte, + .get = &ath10k_get_ring_byte, +}; + +struct ath10k_hw_ce_ctrl1 wcn3990_ctrl1 = { + .addr = 0x00000018, + .src_ring = &wcn3990_src_ring, + .dst_ring = &wcn3990_dst_ring, + .dmax = &wcn3990_dmax, +}; + +struct ath10k_hw_ce_regs_addr_map wcn3990_host_ie_cc = { + .mask = 0x00000001, +}; + +struct ath10k_hw_ce_host_ie wcn3990_host_ie = { + .copy_complete = &wcn3990_host_ie_cc, +}; + +struct ath10k_hw_ce_host_wm_regs wcn3990_wm_reg = { + .dstr_lmask = 0x00000010, + .dstr_hmask = 0x00000008, + .srcr_lmask = 0x00000004, + .srcr_hmask = 0x00000002, + .cc_mask = 0x00000001, + .wm_mask = 0x0000001E, + .addr = 0x00000030, +}; + +struct ath10k_hw_ce_misc_regs wcn3990_misc_reg = { + .axi_err = 0x00000100, + .dstr_add_err = 0x00000200, + .srcr_len_err = 0x00000100, + .dstr_mlen_vio = 0x00000080, + .dstr_overflow = 0x00000040, + .srcr_overflow = 0x00000020, + .err_mask = 0x000003E0, + .addr = 0x00000038, +}; + +struct ath10k_hw_ce_regs_addr_map wcn3990_src_wm_low = { + .msb = 0x00000000, + .lsb = 0x00000010, + .mask = 0xffff0000, + .set = &ath10k_set_ring_byte, + .get = &ath10k_get_ring_byte, +}; + +struct ath10k_hw_ce_regs_addr_map wcn3990_src_wm_high = { + .msb = 0x0000000f, + .lsb = 0x00000000, + .mask = 0x0000ffff, + .set = &ath10k_set_ring_byte, + .get = &ath10k_get_ring_byte, +}; + +struct ath10k_hw_ce_dst_src_wm_regs wcn3990_wm_src_ring = { + .addr = 0x0000004c, + .low_rst = 0x00000000, + .high_rst = 0x00000000, + .wm_low = &wcn3990_src_wm_low, + .wm_high = &wcn3990_src_wm_high, +}; + +struct ath10k_hw_ce_regs_addr_map wcn3990_dst_wm_low = { + .lsb = 0x00000010, + .mask = 0xffff0000, + .set = &ath10k_set_ring_byte, +}; + +struct ath10k_hw_ce_regs_addr_map wcn3990_dst_wm_high = { + .msb = 0x0000000f, + .lsb = 0x00000000, + .mask = 0x0000ffff, + .set = &ath10k_set_ring_byte, + .get = &ath10k_get_ring_byte, +}; + +struct ath10k_hw_ce_dst_src_wm_regs wcn3990_wm_dst_ring = { + .addr = 0x00000050, + .low_rst = 0x00000000, + .high_rst = 0x00000000, + .wm_low = &wcn3990_dst_wm_low, + .wm_high = &wcn3990_dst_wm_high, +}; + +static struct ath10k_hw_ce_ctrl1_upd wcn3990_ctrl1_upd = { + .shift = 19, + .mask = 0x00080000, + .enable = 0x00000000, +}; + +struct ath10k_hw_ce_regs wcn3990_ce_regs = { + .sr_base_addr = 0x00000000, + .sr_size_addr = 0x00000008, + .dr_base_addr = 0x0000000c, + .dr_size_addr = 0x00000014, + .misc_ie_addr = 0x00000034, + .sr_wr_index_addr = 0x0000003c, + .dst_wr_index_addr = 0x00000040, + .current_srri_addr = 0x00000044, + .current_drri_addr = 0x00000048, + .ddr_addr_for_rri_low = 0x00000004, + .ddr_addr_for_rri_high = 0x00000008, + .ce_rri_low = 0x0024C004, + .ce_rri_high = 0x0024C008, + .host_ie_addr = 0x0000002c, + .ctrl1_regs = &wcn3990_ctrl1, + .host_ie = &wcn3990_host_ie, + .wm_regs = &wcn3990_wm_reg, + .misc_regs = &wcn3990_misc_reg, + .wm_srcr = &wcn3990_wm_src_ring, + .wm_dstr = &wcn3990_wm_dst_ring, + .upd = &wcn3990_ctrl1_upd, +}; + +struct ath10k_hw_ce_regs_addr_map qcax_src_ring = { + .msb = 0x00000010, + .lsb = 0x00000010, + .mask = 0x00010000, + .set = &ath10k_set_ring_byte, +}; + +struct ath10k_hw_ce_regs_addr_map qcax_dst_ring = { + .msb = 0x00000011, + .lsb = 0x00000011, + .mask = 0x00020000, + .set = &ath10k_set_ring_byte, + .get = &ath10k_get_ring_byte, +}; + +struct ath10k_hw_ce_regs_addr_map qcax_dmax = { + .msb = 0x0000000f, + .lsb = 0x00000000, + .mask = 0x0000ffff, + .set = &ath10k_set_ring_byte, + .get = &ath10k_get_ring_byte, +}; + +struct ath10k_hw_ce_ctrl1 qcax_ctrl1 = { + .addr = 0x00000010, + .hw_mask = 0x0007ffff, + .sw_mask = 0x0007ffff, + .hw_wr_mask = 0x00000000, + .sw_wr_mask = 0x0007ffff, + .reset_mask = 0xffffffff, + .reset = 0x00000080, + .src_ring = &qcax_src_ring, + .dst_ring = &qcax_dst_ring, + .dmax = &qcax_dmax, +}; + +struct ath10k_hw_ce_regs_addr_map qcax_cmd_halt_status = { + .msb = 0x00000003, + .lsb = 0x00000003, + .mask = 0x00000008, + .set = &ath10k_set_ring_byte, + .get = &ath10k_get_ring_byte, +}; + +struct ath10k_hw_ce_cmd_halt qcax_cmd_halt = { + .msb = 0x00000000, + .mask = 0x00000001, + .status_reset = 0x00000000, + .status = &qcax_cmd_halt_status, +}; + +struct ath10k_hw_ce_regs_addr_map qcax_host_ie_cc = { + .msb = 0x00000000, + .lsb = 0x00000000, + .mask = 0x00000001, + .set = &ath10k_set_ring_byte, + .get = &ath10k_get_ring_byte, +}; + +struct ath10k_hw_ce_host_ie qcax_host_ie = { + .copy_complete_reset = 0x00000000, + .copy_complete = &qcax_host_ie_cc, +}; + +struct ath10k_hw_ce_host_wm_regs qcax_wm_reg = { + .dstr_lmask = 0x00000010, + .dstr_hmask = 0x00000008, + .srcr_lmask = 0x00000004, + .srcr_hmask = 0x00000002, + .cc_mask = 0x00000001, + .wm_mask = 0x0000001E, + .addr = 0x00000030, +}; + +struct ath10k_hw_ce_misc_regs qcax_misc_reg = { + .axi_err = 0x00000400, + .dstr_add_err = 0x00000200, + .srcr_len_err = 0x00000100, + .dstr_mlen_vio = 0x00000080, + .dstr_overflow = 0x00000040, + .srcr_overflow = 0x00000020, + .err_mask = 0x000007E0, + .addr = 0x00000038, +}; + +struct ath10k_hw_ce_regs_addr_map qcax_src_wm_low = { + .msb = 0x0000001f, + .lsb = 0x00000010, + .mask = 0xffff0000, + .set = &ath10k_set_ring_byte, + .get = &ath10k_get_ring_byte, +}; + +struct ath10k_hw_ce_regs_addr_map qcax_src_wm_high = { + .msb = 0x0000000f, + .lsb = 0x00000000, + .mask = 0x0000ffff, + .set = &ath10k_set_ring_byte, + .get = &ath10k_get_ring_byte, +}; + +struct ath10k_hw_ce_dst_src_wm_regs qcax_wm_src_ring = { + .addr = 0x0000004c, + .low_rst = 0x00000000, + .high_rst = 0x00000000, + .wm_low = &qcax_src_wm_low, + .wm_high = &qcax_src_wm_high, +}; + +struct ath10k_hw_ce_regs_addr_map qcax_dst_wm_low = { + .lsb = 0x00000010, + .mask = 0xffff0000, + .set = &ath10k_set_ring_byte, +}; + +struct ath10k_hw_ce_regs_addr_map qcax_dst_wm_high = { + .msb = 0x0000000f, + .lsb = 0x00000000, + .mask = 0x0000ffff, + .set = &ath10k_set_ring_byte, + .get = &ath10k_get_ring_byte, +}; + +struct ath10k_hw_ce_dst_src_wm_regs qcax_wm_dst_ring = { + .addr = 0x00000050, + .low_rst = 0x00000000, + .high_rst = 0x00000000, + .wm_low = &qcax_dst_wm_low, + .wm_high = &qcax_dst_wm_high, +}; + +struct ath10k_hw_ce_regs qcax_ce_regs = { + .sr_base_addr = 0x00000000, + .sr_size_addr = 0x00000004, + .dr_base_addr = 0x00000008, + .dr_size_addr = 0x0000000c, + .ce_cmd_addr = 0x00000018, + .misc_ie_addr = 0x00000034, + .sr_wr_index_addr = 0x0000003c, + .dst_wr_index_addr = 0x00000040, + .current_srri_addr = 0x00000044, + .current_drri_addr = 0x00000048, + .host_ie_addr = 0x0000002c, + .ctrl1_regs = &qcax_ctrl1, + .cmd_halt = &qcax_cmd_halt, + .host_ie = &qcax_host_ie, + .wm_regs = &qcax_wm_reg, + .misc_regs = &qcax_misc_reg, + .wm_srcr = &qcax_wm_src_ring, + .wm_dstr = &qcax_wm_dst_ring, +}; + const struct ath10k_hw_values qca988x_values = { + .pdev_suspend_option = WMI_PDEV_SUSPEND_AND_DISABLE_INTR, .rtc_state_val_on = 3, .ce_count = 8, .msi_assign_ce_max = 7, @@ -119,6 +477,7 @@ }; const struct ath10k_hw_values qca6174_values = { + .pdev_suspend_option = WMI_PDEV_SUSPEND_AND_DISABLE_INTR, .rtc_state_val_on = 3, .ce_count = 8, .msi_assign_ce_max = 7, @@ -128,6 +487,7 @@ }; const struct ath10k_hw_values qca99x0_values = { + .pdev_suspend_option = WMI_PDEV_SUSPEND_AND_DISABLE_INTR, .rtc_state_val_on = 5, .ce_count = 12, .msi_assign_ce_max = 12, @@ -136,22 +496,143 @@ .ce_desc_meta_data_lsb = 4, }; +const struct ath10k_hw_values qca9888_values = { + .pdev_suspend_option = WMI_PDEV_SUSPEND_AND_DISABLE_INTR, + .rtc_state_val_on = 3, + .ce_count = 12, + .msi_assign_ce_max = 12, + .num_target_ce_config_wlan = 10, + .ce_desc_meta_data_mask = 0xFFF0, + .ce_desc_meta_data_lsb = 4, +}; + +const struct ath10k_hw_values qca4019_values = { + .pdev_suspend_option = WMI_PDEV_SUSPEND_AND_DISABLE_INTR, + .ce_count = 12, + .num_target_ce_config_wlan = 10, + .ce_desc_meta_data_mask = 0xFFF0, + .ce_desc_meta_data_lsb = 4, +}; + +const struct ath10k_hw_values wcn3990_values = { + .pdev_suspend_option = WMI_PDEV_SUSPEND, + .rtc_state_val_on = 5, + .ce_count = 12, + .msi_assign_ce_max = 12, + .num_target_ce_config_wlan = 12, + .ce_desc_meta_data_mask = 0xFFF0, + .ce_desc_meta_data_lsb = 4, + .default_listen_interval = 1, +}; + +struct fw_flag wcn3990_fw_flags = { + .flags = 0x82E, +}; + +struct ath10k_shadow_reg_value wcn3990_shadow_reg_value = { + .shadow_reg_value_0 = 0x00032000, + .shadow_reg_value_1 = 0x00032004, + .shadow_reg_value_2 = 0x00032008, + .shadow_reg_value_3 = 0x0003200C, + .shadow_reg_value_4 = 0x00032010, + .shadow_reg_value_5 = 0x00032014, + .shadow_reg_value_6 = 0x00032018, + .shadow_reg_value_7 = 0x0003201C, + .shadow_reg_value_8 = 0x00032020, + .shadow_reg_value_9 = 0x00032024, + .shadow_reg_value_10 = 0x00032028, + .shadow_reg_value_11 = 0x0003202C, + .shadow_reg_value_12 = 0x00032030, + .shadow_reg_value_13 = 0x00032034, + .shadow_reg_value_14 = 0x00032038, + .shadow_reg_value_15 = 0x0003203C, + .shadow_reg_value_16 = 0x00032040, + .shadow_reg_value_17 = 0x00032044, + .shadow_reg_value_18 = 0x00032048, + .shadow_reg_value_19 = 0x0003204C, + .shadow_reg_value_20 = 0x00032050, + .shadow_reg_value_21 = 0x00032054, + .shadow_reg_value_22 = 0x00032058, + .shadow_reg_value_23 = 0x0003205C +}; + +struct ath10k_shadow_reg_address wcn3990_shadow_reg_address = { + .shadow_reg_address_0 = 0x00030020, + .shadow_reg_address_1 = 0x00030024, + .shadow_reg_address_2 = 0x00030028, + .shadow_reg_address_3 = 0x0003002C, + .shadow_reg_address_4 = 0x00030030, + .shadow_reg_address_5 = 0x00030034, + .shadow_reg_address_6 = 0x00030038, + .shadow_reg_address_7 = 0x0003003C, + .shadow_reg_address_8 = 0x00030040, + .shadow_reg_address_9 = 0x00030044, + .shadow_reg_address_10 = 0x00030048, + .shadow_reg_address_11 = 0x0003004C, + .shadow_reg_address_12 = 0x00030050, + .shadow_reg_address_13 = 0x00030054, + .shadow_reg_address_14 = 0x00030058, + .shadow_reg_address_15 = 0x0003005C, + .shadow_reg_address_16 = 0x00030060, + .shadow_reg_address_17 = 0x00030064, + .shadow_reg_address_18 = 0x00030068, + .shadow_reg_address_19 = 0x0003006C, + .shadow_reg_address_20 = 0x00030070, + .shadow_reg_address_21 = 0x00030074, + .shadow_reg_address_22 = 0x00030078, + .shadow_reg_address_23 = 0x0003007C +}; + void ath10k_hw_fill_survey_time(struct ath10k *ar, struct survey_info *survey, u32 cc, u32 rcc, u32 cc_prev, u32 rcc_prev) { u32 cc_fix = 0; + u32 rcc_fix = 0; + enum ath10k_hw_cc_wraparound_type wraparound_type; survey->filled |= SURVEY_INFO_TIME | SURVEY_INFO_TIME_BUSY; - if (ar->hw_params.has_shifted_cc_wraparound && cc < cc_prev) { + wraparound_type = ar->hw_params.cc_wraparound_type; + + if (cc < cc_prev || rcc < rcc_prev) { + switch (wraparound_type) { + case ATH10K_HW_CC_WRAP_SHIFTED_ALL: + if (cc < cc_prev) { cc_fix = 0x7fffffff; survey->filled &= ~SURVEY_INFO_TIME_BUSY; } + break; + case ATH10K_HW_CC_WRAP_SHIFTED_EACH: + if (cc < cc_prev) + cc_fix = 0x7fffffff; + + if (rcc < rcc_prev) + rcc_fix = 0x7fffffff; + break; + case ATH10K_HW_CC_WRAP_DISABLED: + break; + } + } cc -= cc_prev - cc_fix; - rcc -= rcc_prev; + rcc -= rcc_prev - rcc_fix; survey->time = CCNT_TO_MSEC(ar, cc); survey->time_busy = CCNT_TO_MSEC(ar, rcc); } + +const struct ath10k_hw_ops qca988x_ops = { +}; + +static int ath10k_qca99x0_rx_desc_get_l3_pad_bytes(struct htt_rx_desc *rxd) +{ + return MS(__le32_to_cpu(rxd->msdu_end.qca99x0.info1), + RX_MSDU_END_INFO1_L3_HDR_PAD); +} + +const struct ath10k_hw_ops qca99x0_ops = { + .rx_desc_get_l3_pad_bytes = ath10k_qca99x0_rx_desc_get_l3_pad_bytes, +}; + +const struct ath10k_hw_ops wcn3990_ops = {0}; diff -ruw linux-4.4.115/drivers/net/wireless/ath/ath10k/hw.h linux-4.4.115-fbx/drivers/net/wireless/ath/ath10k/hw.h --- linux-4.4.115/drivers/net/wireless/ath/ath10k/hw.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/net/wireless/ath/ath10k/hw.h 2019-01-22 16:16:25.419263757 +0100 @@ -1,6 +1,6 @@ /* * Copyright (c) 2005-2011 Atheros Communications Inc. - * Copyright (c) 2011-2013 Qualcomm Atheros, Inc. + * Copyright (c) 2011-2013,2017 Qualcomm Atheros, Inc. * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above @@ -26,7 +26,10 @@ #define QCA6164_2_1_DEVICE_ID (0x0041) #define QCA6174_2_1_DEVICE_ID (0x003e) #define QCA99X0_2_0_DEVICE_ID (0x0040) +#define QCA9888_2_0_DEVICE_ID (0x0056) +#define QCA9984_1_0_DEVICE_ID (0x0046) #define QCA9377_1_0_DEVICE_ID (0x0042) +#define QCA9887_1_0_DEVICE_ID (0x0050) /* QCA988X 1.0 definitions (unsupported) */ #define QCA988X_HW_1_0_CHIP_ID_REV 0x0 @@ -35,11 +38,16 @@ #define QCA988X_HW_2_0_VERSION 0x4100016c #define QCA988X_HW_2_0_CHIP_ID_REV 0x2 #define QCA988X_HW_2_0_FW_DIR ATH10K_FW_DIR "/QCA988X/hw2.0" -#define QCA988X_HW_2_0_FW_FILE "firmware.bin" -#define QCA988X_HW_2_0_OTP_FILE "otp.bin" #define QCA988X_HW_2_0_BOARD_DATA_FILE "board.bin" #define QCA988X_HW_2_0_PATCH_LOAD_ADDR 0x1234 +/* QCA9887 1.0 definitions */ +#define QCA9887_HW_1_0_VERSION 0x4100016d +#define QCA9887_HW_1_0_CHIP_ID_REV 0 +#define QCA9887_HW_1_0_FW_DIR ATH10K_FW_DIR "/QCA9887/hw1.0" +#define QCA9887_HW_1_0_BOARD_DATA_FILE "board.bin" +#define QCA9887_HW_1_0_PATCH_LOAD_ADDR 0x1234 + /* QCA6174 target BMI version signatures */ #define QCA6174_HW_1_0_VERSION 0x05000000 #define QCA6174_HW_1_1_VERSION 0x05000001 @@ -76,14 +84,10 @@ }; #define QCA6174_HW_2_1_FW_DIR "ath10k/QCA6174/hw2.1" -#define QCA6174_HW_2_1_FW_FILE "firmware.bin" -#define QCA6174_HW_2_1_OTP_FILE "otp.bin" #define QCA6174_HW_2_1_BOARD_DATA_FILE "board.bin" #define QCA6174_HW_2_1_PATCH_LOAD_ADDR 0x1234 #define QCA6174_HW_3_0_FW_DIR "ath10k/QCA6174/hw3.0" -#define QCA6174_HW_3_0_FW_FILE "firmware.bin" -#define QCA6174_HW_3_0_OTP_FILE "otp.bin" #define QCA6174_HW_3_0_BOARD_DATA_FILE "board.bin" #define QCA6174_HW_3_0_PATCH_LOAD_ADDR 0x1234 @@ -94,18 +98,40 @@ #define QCA99X0_HW_2_0_DEV_VERSION 0x01000000 #define QCA99X0_HW_2_0_CHIP_ID_REV 0x1 #define QCA99X0_HW_2_0_FW_DIR ATH10K_FW_DIR "/QCA99X0/hw2.0" -#define QCA99X0_HW_2_0_FW_FILE "firmware.bin" -#define QCA99X0_HW_2_0_OTP_FILE "otp.bin" #define QCA99X0_HW_2_0_BOARD_DATA_FILE "board.bin" #define QCA99X0_HW_2_0_PATCH_LOAD_ADDR 0x1234 +/* QCA9984 1.0 defines */ +#define QCA9984_HW_1_0_DEV_VERSION 0x1000000 +#define QCA9984_HW_DEV_TYPE 0xa +#define QCA9984_HW_1_0_CHIP_ID_REV 0x0 +#define QCA9984_HW_1_0_FW_DIR ATH10K_FW_DIR "/QCA9984/hw1.0" +#define QCA9984_HW_1_0_BOARD_DATA_FILE "board.bin" +#define QCA9984_HW_1_0_PATCH_LOAD_ADDR 0x1234 + +/* QCA9888 2.0 defines */ +#define QCA9888_HW_2_0_DEV_VERSION 0x1000000 +#define QCA9888_HW_DEV_TYPE 0xc +#define QCA9888_HW_2_0_CHIP_ID_REV 0x0 +#define QCA9888_HW_2_0_FW_DIR ATH10K_FW_DIR "/QCA9888/hw2.0" +#define QCA9888_HW_2_0_BOARD_DATA_FILE "board.bin" +#define QCA9888_HW_2_0_PATCH_LOAD_ADDR 0x1234 + /* QCA9377 1.0 definitions */ #define QCA9377_HW_1_0_FW_DIR ATH10K_FW_DIR "/QCA9377/hw1.0" -#define QCA9377_HW_1_0_FW_FILE "firmware.bin" -#define QCA9377_HW_1_0_OTP_FILE "otp.bin" #define QCA9377_HW_1_0_BOARD_DATA_FILE "board.bin" #define QCA9377_HW_1_0_PATCH_LOAD_ADDR 0x1234 +/* QCA4019 1.0 definitions */ +#define QCA4019_HW_1_0_DEV_VERSION 0x01000000 +#define QCA4019_HW_1_0_FW_DIR ATH10K_FW_DIR "/QCA4019/hw1.0" +#define QCA4019_HW_1_0_BOARD_DATA_FILE "board.bin" +#define QCA4019_HW_1_0_PATCH_LOAD_ADDR 0x1234 + +/* WCN3990 1.0 definitions */ +#define WCN3990_HW_1_0_DEV_VERSION ATH10K_HW_WCN3990 +#define WCN3990_HW_1_0_FW_DIR "/etc/firmware" + #define ATH10K_FW_API2_FILE "firmware-2.bin" #define ATH10K_FW_API3_FILE "firmware-3.bin" @@ -126,8 +152,6 @@ #define REG_DUMP_COUNT_QCA988X 60 -#define QCA988X_CAL_DATA_LEN 2116 - struct ath10k_fw_ie { __le32 id; __le32 len; @@ -199,14 +223,19 @@ ATH10K_HW_QCA988X, ATH10K_HW_QCA6174, ATH10K_HW_QCA99X0, + ATH10K_HW_QCA9888, + ATH10K_HW_QCA9984, ATH10K_HW_QCA9377, + ATH10K_HW_QCA4019, + ATH10K_HW_QCA9887, + ATH10K_HW_WCN3990, }; struct ath10k_hw_regs { - u32 rtc_state_cold_reset_mask; u32 rtc_soc_base_address; u32 rtc_wmac_base_address; u32 soc_core_base_address; + u32 soc_global_reset_address; u32 ce_wrapper_base_address; u32 ce0_base_address; u32 ce1_base_address; @@ -216,6 +245,10 @@ u32 ce5_base_address; u32 ce6_base_address; u32 ce7_base_address; + u32 ce8_base_address; + u32 ce9_base_address; + u32 ce10_base_address; + u32 ce11_base_address; u32 soc_reset_control_si0_rst_mask; u32 soc_reset_control_ce_rst_mask; u32 soc_chip_id_address; @@ -232,29 +265,142 @@ extern const struct ath10k_hw_regs qca988x_regs; extern const struct ath10k_hw_regs qca6174_regs; extern const struct ath10k_hw_regs qca99x0_regs; +extern const struct ath10k_hw_regs qca4019_regs; +extern const struct ath10k_hw_regs wcn3990_regs; + +struct ath10k_hw_ce_regs_addr_map { + u32 msb; + u32 lsb; + u32 mask; + unsigned int (*set)(unsigned int offset, + struct ath10k_hw_ce_regs_addr_map *addr_map); + unsigned int (*get)(unsigned int offset, + struct ath10k_hw_ce_regs_addr_map *addr_map); +}; + +struct ath10k_hw_ce_ctrl1 { + u32 addr; + u32 hw_mask; + u32 sw_mask; + u32 hw_wr_mask; + u32 sw_wr_mask; + u32 reset_mask; + u32 reset; + struct ath10k_hw_ce_regs_addr_map *src_ring; + struct ath10k_hw_ce_regs_addr_map *dst_ring; + struct ath10k_hw_ce_regs_addr_map *dmax; +}; + +struct ath10k_hw_ce_cmd_halt { + u32 status_reset; + u32 msb; + u32 mask; + struct ath10k_hw_ce_regs_addr_map *status; +}; + +struct ath10k_hw_ce_host_ie { + u32 copy_complete_reset; + struct ath10k_hw_ce_regs_addr_map *copy_complete; +}; + +struct ath10k_hw_ce_host_wm_regs { + u32 dstr_lmask; + u32 dstr_hmask; + u32 srcr_lmask; + u32 srcr_hmask; + u32 cc_mask; + u32 wm_mask; + u32 addr; +}; + +struct ath10k_hw_ce_misc_regs { + u32 axi_err; + u32 dstr_add_err; + u32 srcr_len_err; + u32 dstr_mlen_vio; + u32 dstr_overflow; + u32 srcr_overflow; + u32 err_mask; + u32 addr; +}; + +struct ath10k_hw_ce_dst_src_wm_regs { + u32 addr; + u32 low_rst; + u32 high_rst; + struct ath10k_hw_ce_regs_addr_map *wm_low; + struct ath10k_hw_ce_regs_addr_map *wm_high; +}; + +struct ath10k_hw_ce_ctrl1_upd { + u32 shift; + u32 mask; + u32 enable; +}; + +struct ath10k_hw_ce_regs { + u32 sr_base_addr; + u32 sr_size_addr; + u32 dr_base_addr; + u32 dr_size_addr; + u32 ce_cmd_addr; + u32 misc_ie_addr; + u32 sr_wr_index_addr; + u32 dst_wr_index_addr; + u32 current_srri_addr; + u32 current_drri_addr; + u32 ddr_addr_for_rri_low; + u32 ddr_addr_for_rri_high; + u32 ce_rri_low; + u32 ce_rri_high; + u32 host_ie_addr; + struct ath10k_hw_ce_host_wm_regs *wm_regs; + struct ath10k_hw_ce_misc_regs *misc_regs; + struct ath10k_hw_ce_ctrl1 *ctrl1_regs; + struct ath10k_hw_ce_cmd_halt *cmd_halt; + struct ath10k_hw_ce_host_ie *host_ie; + struct ath10k_hw_ce_dst_src_wm_regs *wm_srcr; + struct ath10k_hw_ce_dst_src_wm_regs *wm_dstr; + struct ath10k_hw_ce_ctrl1_upd *upd; +}; + +extern struct ath10k_hw_ce_regs wcn3990_ce_regs; +extern struct ath10k_hw_ce_regs qcax_ce_regs; + +extern struct fw_flag wcn3990_fw_flags; struct ath10k_hw_values { + u32 pdev_suspend_option; u32 rtc_state_val_on; u8 ce_count; u8 msi_assign_ce_max; u8 num_target_ce_config_wlan; u16 ce_desc_meta_data_mask; u8 ce_desc_meta_data_lsb; + u8 default_listen_interval; }; extern const struct ath10k_hw_values qca988x_values; extern const struct ath10k_hw_values qca6174_values; extern const struct ath10k_hw_values qca99x0_values; +extern const struct ath10k_hw_values qca9888_values; +extern const struct ath10k_hw_values qca4019_values; +extern const struct ath10k_hw_values wcn3990_values; void ath10k_hw_fill_survey_time(struct ath10k *ar, struct survey_info *survey, u32 cc, u32 rcc, u32 cc_prev, u32 rcc_prev); #define QCA_REV_988X(ar) ((ar)->hw_rev == ATH10K_HW_QCA988X) +#define QCA_REV_9887(ar) ((ar)->hw_rev == ATH10K_HW_QCA9887) #define QCA_REV_6174(ar) ((ar)->hw_rev == ATH10K_HW_QCA6174) #define QCA_REV_99X0(ar) ((ar)->hw_rev == ATH10K_HW_QCA99X0) +#define QCA_REV_9888(ar) ((ar)->hw_rev == ATH10K_HW_QCA9888) +#define QCA_REV_9984(ar) ((ar)->hw_rev == ATH10K_HW_QCA9984) #define QCA_REV_9377(ar) ((ar)->hw_rev == ATH10K_HW_QCA9377) +#define QCA_REV_40XX(ar) ((ar)->hw_rev == ATH10K_HW_QCA4019) +#define QCA_REV_WCN3990(ar) ((ar)->hw_rev == ATH10K_HW_WCN3990) -/* Known pecularities: +/* Known peculiarities: * - raw appears in nwifi decap, raw and nwifi appear in ethernet decap * - raw have FCS, nwifi doesn't * - ethernet frames have 802.11 header decapped and parts (base hdr, cipher @@ -277,15 +423,6 @@ ATH10K_MCAST2UCAST_ENABLED = 1, }; -struct ath10k_pktlog_hdr { - __le16 flags; - __le16 missed_cnt; - __le16 log_type; - __le16 size; - __le32 timestamp; - u8 payload[0]; -} __packed; - enum ath10k_hw_rate_ofdm { ATH10K_HW_RATE_OFDM_48M = 0, ATH10K_HW_RATE_OFDM_24M, @@ -307,6 +444,111 @@ ATH10K_HW_RATE_CCK_SP_2M, }; +enum ath10k_hw_rate_rev2_cck { + ATH10K_HW_RATE_REV2_CCK_LP_1M = 1, + ATH10K_HW_RATE_REV2_CCK_LP_2M, + ATH10K_HW_RATE_REV2_CCK_LP_5_5M, + ATH10K_HW_RATE_REV2_CCK_LP_11M, + ATH10K_HW_RATE_REV2_CCK_SP_2M, + ATH10K_HW_RATE_REV2_CCK_SP_5_5M, + ATH10K_HW_RATE_REV2_CCK_SP_11M, +}; + +enum ath10k_hw_cc_wraparound_type { + ATH10K_HW_CC_WRAP_DISABLED = 0, + + /* This type is when the HW chip has a quirky Cycle Counter + * wraparound which resets to 0x7fffffff instead of 0. All + * other CC related counters (e.g. Rx Clear Count) are divided + * by 2 so they never wraparound themselves. + */ + ATH10K_HW_CC_WRAP_SHIFTED_ALL = 1, + + /* Each hw counter wrapsaround independently. When the + * counter overflows the repestive counter is right shifted + * by 1, i.e reset to 0x7fffffff, and other counters will be + * running unaffected. In this type of wraparound, it should + * be possible to report accurate Rx busy time unlike the + * first type. + */ + ATH10K_HW_CC_WRAP_SHIFTED_EACH = 2, +}; + +struct ath10k_hw_params { + u32 id; + u16 dev_id; + const char *name; + u32 patch_load_addr; + int uart_pin; + u32 otp_exe_param; + + /* Type of hw cycle counter wraparound logic, for more info + * refer enum ath10k_hw_cc_wraparound_type. + */ + enum ath10k_hw_cc_wraparound_type cc_wraparound_type; + + /* Some of chip expects fragment descriptor to be continuous + * memory for any TX operation. Set continuous_frag_desc flag + * for the hardware which have such requirement. + */ + bool continuous_frag_desc; + + /* CCK hardware rate table mapping for the newer chipsets + * like QCA99X0, QCA4019 got revised. The CCK h/w rate values + * are in a proper order with respect to the rate/preamble + */ + bool cck_rate_map_rev2; + + u32 channel_counters_freq_hz; + + /* Mgmt tx descriptors threshold for limiting probe response + * frames. + */ + u32 max_probe_resp_desc_thres; + + u32 tx_chain_mask; + u32 rx_chain_mask; + u32 max_spatial_stream; + u32 cal_data_len; + + struct ath10k_hw_params_fw { + const char *dir; + const char *board; + size_t board_size; + size_t board_ext_size; + } fw; + + /* qca99x0 family chips deliver broadcast/multicast management + * frames encrypted and expect software do decryption. + */ + bool sw_decrypt_mcast_mgmt; + + const struct ath10k_hw_ops *hw_ops; + + /* Number of bytes used for alignment in rx_hdr_status of rx desc. */ + int decap_align_bytes; +}; + +struct htt_rx_desc; + +/* Defines needed for Rx descriptor abstraction */ +struct ath10k_hw_ops { + int (*rx_desc_get_l3_pad_bytes)(struct htt_rx_desc *rxd); +}; + +extern const struct ath10k_hw_ops qca988x_ops; +extern const struct ath10k_hw_ops qca99x0_ops; +extern const struct ath10k_hw_ops wcn3990_ops; + +static inline int +ath10k_rx_desc_get_l3_pad_bytes(struct ath10k_hw_params *hw, + struct htt_rx_desc *rxd) +{ + if (hw->hw_ops->rx_desc_get_l3_pad_bytes) + return hw->hw_ops->rx_desc_get_l3_pad_bytes(rxd); + return 0; +} + /* Target specific defines for MAIN firmware */ #define TARGET_NUM_VDEVS 8 #define TARGET_NUM_PEER_AST 2 @@ -348,14 +590,19 @@ #define TARGET_10X_MAC_AGGR_DELIM 0 #define TARGET_10X_AST_SKID_LIMIT 128 #define TARGET_10X_NUM_STATIONS 128 +#define TARGET_10X_TX_STATS_NUM_STATIONS 118 #define TARGET_10X_NUM_PEERS ((TARGET_10X_NUM_STATIONS) + \ (TARGET_10X_NUM_VDEVS)) +#define TARGET_10X_TX_STATS_NUM_PEERS ((TARGET_10X_TX_STATS_NUM_STATIONS) + \ + (TARGET_10X_NUM_VDEVS)) #define TARGET_10X_NUM_OFFLOAD_PEERS 0 #define TARGET_10X_NUM_OFFLOAD_REORDER_BUFS 0 #define TARGET_10X_NUM_PEER_KEYS 2 #define TARGET_10X_NUM_TIDS_MAX 256 #define TARGET_10X_NUM_TIDS min((TARGET_10X_NUM_TIDS_MAX), \ (TARGET_10X_NUM_PEERS) * 2) +#define TARGET_10X_TX_STATS_NUM_TIDS min((TARGET_10X_NUM_TIDS_MAX), \ + (TARGET_10X_TX_STATS_NUM_PEERS) * 2) #define TARGET_10X_TX_CHAIN_MASK (BIT(0) | BIT(1) | BIT(2)) #define TARGET_10X_RX_CHAIN_MASK (BIT(0) | BIT(1) | BIT(2)) #define TARGET_10X_RX_TIMEOUT_LO_PRI 100 @@ -385,6 +632,14 @@ #define TARGET_TLV_NUM_TIDS ((TARGET_TLV_NUM_PEERS) * 2) #define TARGET_TLV_NUM_MSDU_DESC (1024 + 32) #define TARGET_TLV_NUM_WOW_PATTERNS 22 +/* FW supports max 50 outstanding mgmt cmds */ +#define TARGET_TLV_MGMT_NUM_MSDU_DESC (50) + +/* Target specific defines for WMI-HL-1.0 firmware */ +#define TARGET_HL_10_TLV_NUM_PEERS 14 +#define TARGET_HL_10_TLV_AST_SKID_LIMIT 6 +#define TARGET_HL_10_TLV_NUM_WDS_ENTRIES 2 +#define TARGET_HL_1_0_NUM_MSDU_DESC (3600) /* Diagnostic Window */ #define CE_DIAG_PIPE 7 @@ -400,15 +655,14 @@ #define TARGET_10_4_NUM_QCACHE_PEERS_MAX 512 #define TARGET_10_4_QCACHE_ACTIVE_PEERS 50 +#define TARGET_10_4_QCACHE_ACTIVE_PEERS_PFC 35 #define TARGET_10_4_NUM_OFFLOAD_PEERS 0 #define TARGET_10_4_NUM_OFFLOAD_REORDER_BUFFS 0 #define TARGET_10_4_NUM_PEER_KEYS 2 #define TARGET_10_4_TGT_NUM_TIDS ((TARGET_10_4_NUM_PEERS) * 2) +#define TARGET_10_4_NUM_MSDU_DESC (1024 + 400) +#define TARGET_10_4_NUM_MSDU_DESC_PFC 2500 #define TARGET_10_4_AST_SKID_LIMIT 32 -#define TARGET_10_4_TX_CHAIN_MASK (BIT(0) | BIT(1) | \ - BIT(2) | BIT(3)) -#define TARGET_10_4_RX_CHAIN_MASK (BIT(0) | BIT(1) | \ - BIT(2) | BIT(3)) /* 100 ms for video, best-effort, and background */ #define TARGET_10_4_RX_TIMEOUT_LO_PRI 100 @@ -434,7 +688,6 @@ #define TARGET_10_4_RX_SKIP_DEFRAG_TIMEOUT_DUP_DETECTION_CHECK 1 #define TARGET_10_4_VOW_CONFIG 0 #define TARGET_10_4_GTK_OFFLOAD_MAX_VDEV 3 -#define TARGET_10_4_NUM_MSDU_DESC (1024 + 400) #define TARGET_10_4_11AC_TX_MAX_FRAGS 2 #define TARGET_10_4_MAX_PEER_EXT_STATS 16 #define TARGET_10_4_SMART_ANT_CAP 0 @@ -468,7 +721,6 @@ /* as of IP3.7.1 */ #define RTC_STATE_V_ON ar->hw_values->rtc_state_val_on -#define RTC_STATE_COLD_RESET_MASK ar->regs->rtc_state_cold_reset_mask #define RTC_STATE_V_LSB 0 #define RTC_STATE_V_MASK 0x00000007 #define RTC_STATE_ADDRESS 0x0000 @@ -531,7 +783,10 @@ #define WLAN_SYSTEM_SLEEP_DISABLE_MASK 0x00000001 #define WLAN_GPIO_PIN0_ADDRESS 0x00000028 +#define WLAN_GPIO_PIN0_CONFIG_LSB 11 #define WLAN_GPIO_PIN0_CONFIG_MASK 0x00007800 +#define WLAN_GPIO_PIN0_PAD_PULL_LSB 5 +#define WLAN_GPIO_PIN0_PAD_PULL_MASK 0x00000060 #define WLAN_GPIO_PIN1_ADDRESS 0x0000002c #define WLAN_GPIO_PIN1_CONFIG_MASK 0x00007800 #define WLAN_GPIO_PIN10_ADDRESS 0x00000050 @@ -544,6 +799,8 @@ #define CLOCK_GPIO_BT_CLK_OUT_EN_MASK 0 #define SI_CONFIG_OFFSET 0x00000000 +#define SI_CONFIG_ERR_INT_LSB 19 +#define SI_CONFIG_ERR_INT_MASK 0x00080000 #define SI_CONFIG_BIDIR_OD_DATA_LSB 18 #define SI_CONFIG_BIDIR_OD_DATA_MASK 0x00040000 #define SI_CONFIG_I2C_LSB 16 @@ -557,7 +814,9 @@ #define SI_CONFIG_DIVIDER_LSB 0 #define SI_CONFIG_DIVIDER_MASK 0x0000000f #define SI_CS_OFFSET 0x00000004 +#define SI_CS_DONE_ERR_LSB 10 #define SI_CS_DONE_ERR_MASK 0x00000400 +#define SI_CS_DONE_INT_LSB 9 #define SI_CS_DONE_INT_MASK 0x00000200 #define SI_CS_START_LSB 8 #define SI_CS_START_MASK 0x00000100 @@ -586,6 +845,7 @@ #define FW_INDICATOR_ADDRESS ar->regs->fw_indicator_address #define FW_IND_EVENT_PENDING 1 #define FW_IND_INITIALIZED 2 +#define FW_IND_HOST_READY 0x80000000 /* HOST_REG interrupt from firmware */ #define PCIE_INTR_FIRMWARE_MASK ar->regs->pcie_intr_fw_mask @@ -607,7 +867,10 @@ #define GPIO_BASE_ADDRESS WLAN_GPIO_BASE_ADDRESS #define GPIO_PIN0_OFFSET WLAN_GPIO_PIN0_ADDRESS #define GPIO_PIN1_OFFSET WLAN_GPIO_PIN1_ADDRESS +#define GPIO_PIN0_CONFIG_LSB WLAN_GPIO_PIN0_CONFIG_LSB #define GPIO_PIN0_CONFIG_MASK WLAN_GPIO_PIN0_CONFIG_MASK +#define GPIO_PIN0_PAD_PULL_LSB WLAN_GPIO_PIN0_PAD_PULL_LSB +#define GPIO_PIN0_PAD_PULL_MASK WLAN_GPIO_PIN0_PAD_PULL_MASK #define GPIO_PIN1_CONFIG_MASK WLAN_GPIO_PIN1_CONFIG_MASK #define SI_BASE_ADDRESS WLAN_SI_BASE_ADDRESS #define SCRATCH_BASE_ADDRESS SOC_CORE_BASE_ADDRESS @@ -662,6 +925,108 @@ #define WINDOW_READ_ADDR_ADDRESS MISSING #define WINDOW_WRITE_ADDR_ADDRESS MISSING +#define QCA9887_1_0_I2C_SDA_GPIO_PIN 5 +#define QCA9887_1_0_I2C_SDA_PIN_CONFIG 3 +#define QCA9887_1_0_SI_CLK_GPIO_PIN 17 +#define QCA9887_1_0_SI_CLK_PIN_CONFIG 3 +#define QCA9887_1_0_GPIO_ENABLE_W1TS_LOW_ADDRESS 0x00000010 + +#define QCA9887_EEPROM_SELECT_READ 0xa10000a0 +#define QCA9887_EEPROM_ADDR_HI_MASK 0x0000ff00 +#define QCA9887_EEPROM_ADDR_HI_LSB 8 +#define QCA9887_EEPROM_ADDR_LO_MASK 0x00ff0000 +#define QCA9887_EEPROM_ADDR_LO_LSB 16 + #define RTC_STATE_V_GET(x) (((x) & RTC_STATE_V_MASK) >> RTC_STATE_V_LSB) +struct ath10k_shadow_reg_value { + u32 shadow_reg_value_0; + u32 shadow_reg_value_1; + u32 shadow_reg_value_2; + u32 shadow_reg_value_3; + u32 shadow_reg_value_4; + u32 shadow_reg_value_5; + u32 shadow_reg_value_6; + u32 shadow_reg_value_7; + u32 shadow_reg_value_8; + u32 shadow_reg_value_9; + u32 shadow_reg_value_10; + u32 shadow_reg_value_11; + u32 shadow_reg_value_12; + u32 shadow_reg_value_13; + u32 shadow_reg_value_14; + u32 shadow_reg_value_15; + u32 shadow_reg_value_16; + u32 shadow_reg_value_17; + u32 shadow_reg_value_18; + u32 shadow_reg_value_19; + u32 shadow_reg_value_20; + u32 shadow_reg_value_21; + u32 shadow_reg_value_22; + u32 shadow_reg_value_23; +}; + +struct ath10k_shadow_reg_address { + u32 shadow_reg_address_0; + u32 shadow_reg_address_1; + u32 shadow_reg_address_2; + u32 shadow_reg_address_3; + u32 shadow_reg_address_4; + u32 shadow_reg_address_5; + u32 shadow_reg_address_6; + u32 shadow_reg_address_7; + u32 shadow_reg_address_8; + u32 shadow_reg_address_9; + u32 shadow_reg_address_10; + u32 shadow_reg_address_11; + u32 shadow_reg_address_12; + u32 shadow_reg_address_13; + u32 shadow_reg_address_14; + u32 shadow_reg_address_15; + u32 shadow_reg_address_16; + u32 shadow_reg_address_17; + u32 shadow_reg_address_18; + u32 shadow_reg_address_19; + u32 shadow_reg_address_20; + u32 shadow_reg_address_21; + u32 shadow_reg_address_22; + u32 shadow_reg_address_23; +}; + +extern struct ath10k_shadow_reg_value wcn3990_shadow_reg_value; +extern struct ath10k_shadow_reg_address wcn3990_shadow_reg_address; + +#define ATH10K_PKTLOG_HDR_SIZE_16 0x8000 + +enum { + ATH10k_PKTLOG_FLG_FRM_TYPE_LOCAL_S = 0, + ATH10K_PKTLOG_FLG_FRM_TYPE_REMOTE_S, + ATH10K_PKTLOG_FLG_FRM_TYPE_CLONE_S, + ATH10K_PKTLOG_FLG_FRM_TYPE_CBF_S, + ATH10K_PKTLOG_FLG_FRM_TYPE_UNKNOWN_S +}; + +enum ath10k_pktlog_type { + ATH10K_PKTLOG_TYPE_TX_CTRL = 1, + ATH10K_PKTLOG_TYPE_TX_STAT, + ATH10K_PKTLOG_TYPE_TX_MSDU_ID, + ATH10K_PKTLOG_TYPE_TX_FRM_HDR, + ATH10K_PKTLOG_TYPE_RX_STAT, + ATH10K_PKTLOG_TYPE_RC_FIND, + ATH10K_PKTLOG_TYPE_RC_UPDATE, + ATH10K_PKTLOG_TYPE_TX_VIRT_ADDR, + ATH10K_PKTLOG_TYPE_DBG_PRINT, + ATH10K_PKTLOG_TYPE_SW_EVENT, + ATH10K_PKTLOG_TYPE_MAX, +}; + +struct ath10k_pktlog_hdr { + __le16 flags; + __le16 missed_cnt; + __le16 log_type; + __le16 size; + __le32 timestamp; + u8 payload[0]; +} __packed; + #endif /* _HW_H_ */ diff -ruw linux-4.4.115/drivers/net/wireless/ath/ath10k/Kconfig linux-4.4.115-fbx/drivers/net/wireless/ath/ath10k/Kconfig --- linux-4.4.115/drivers/net/wireless/ath/ath10k/Kconfig 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/net/wireless/ath/ath10k/Kconfig 2019-01-22 16:16:25.411263685 +0100 @@ -2,6 +2,7 @@ tristate "Atheros 802.11ac wireless cards support" depends on MAC80211 && HAS_DMA select ATH_COMMON + select CRC32 ---help--- This module adds support for wireless adapters based on Atheros IEEE 802.11ac family of chipsets. @@ -14,6 +15,32 @@ ---help--- This module adds support for PCIE bus +config ATH10K_AHB + bool "Atheros ath10k AHB support" + depends on ATH10K_PCI && OF && RESET_CONTROLLER + ---help--- + This module adds support for AHB bus + +config ATH10K_TARGET_SNOC + tristate "Atheros ath10k SNOC support" + depends on ATH10K + ---help--- + This module adds support for the Integrated WCN3990 WLAN module, + WCN3990 has integrated 802.11ac chipset with SNOC bus interface. + This module also adds support to register the WCN3990 wlan module + with MAC80211 network subsystem. + +config ATH10K_SNOC + bool "Enable/disable Atheros ath10k SNOC bus interface support" + depends on ATH10K + depends on ATH10K_TARGET_SNOC + ---help--- + This module add support for WLAN SNOC bus registration, WLAN + copy engine configuration for the WCN3990 chipset, WLAN hardware + shadow register configuration, create host to target communication + interface to interact with WLAN firmware, WLAN module interface + control and data receive(RX)/transmit(TX) control. + config ATH10K_DEBUG bool "Atheros ath10k debugging" depends on ATH10K diff -ruw linux-4.4.115/drivers/net/wireless/ath/ath10k/mac.c linux-4.4.115-fbx/drivers/net/wireless/ath/ath10k/mac.c --- linux-4.4.115/drivers/net/wireless/ath/ath10k/mac.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/net/wireless/ath/ath10k/mac.c 2019-10-29 09:26:24.461211183 +0100 @@ -1,6 +1,6 @@ /* * Copyright (c) 2005-2011 Atheros Communications Inc. - * Copyright (c) 2011-2013 Qualcomm Atheros, Inc. + * Copyright (c) 2011-2013, 2017 Qualcomm Atheros, Inc. * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above @@ -32,6 +32,11 @@ #include "wmi-ops.h" #include "wow.h" +static u8 base_mac_addr[18] = "00:00:00:00:00:00"; +module_param_string(base_mac_addr, base_mac_addr, 18, 0); +MODULE_PARM_DESC(ap_base_mac_addr, + "Override EEPROM defined base mac address"); + /*********/ /* Rates */ /*********/ @@ -62,6 +67,32 @@ { .bitrate = 540, .hw_value = ATH10K_HW_RATE_OFDM_54M }, }; +static struct ieee80211_rate ath10k_rates_rev2[] = { + { .bitrate = 10, + .hw_value = ATH10K_HW_RATE_REV2_CCK_LP_1M }, + { .bitrate = 20, + .hw_value = ATH10K_HW_RATE_REV2_CCK_LP_2M, + .hw_value_short = ATH10K_HW_RATE_REV2_CCK_SP_2M, + .flags = IEEE80211_RATE_SHORT_PREAMBLE }, + { .bitrate = 55, + .hw_value = ATH10K_HW_RATE_REV2_CCK_LP_5_5M, + .hw_value_short = ATH10K_HW_RATE_REV2_CCK_SP_5_5M, + .flags = IEEE80211_RATE_SHORT_PREAMBLE }, + { .bitrate = 110, + .hw_value = ATH10K_HW_RATE_REV2_CCK_LP_11M, + .hw_value_short = ATH10K_HW_RATE_REV2_CCK_SP_11M, + .flags = IEEE80211_RATE_SHORT_PREAMBLE }, + + { .bitrate = 60, .hw_value = ATH10K_HW_RATE_OFDM_6M }, + { .bitrate = 90, .hw_value = ATH10K_HW_RATE_OFDM_9M }, + { .bitrate = 120, .hw_value = ATH10K_HW_RATE_OFDM_12M }, + { .bitrate = 180, .hw_value = ATH10K_HW_RATE_OFDM_18M }, + { .bitrate = 240, .hw_value = ATH10K_HW_RATE_OFDM_24M }, + { .bitrate = 360, .hw_value = ATH10K_HW_RATE_OFDM_36M }, + { .bitrate = 480, .hw_value = ATH10K_HW_RATE_OFDM_48M }, + { .bitrate = 540, .hw_value = ATH10K_HW_RATE_OFDM_54M }, +}; + #define ATH10K_MAC_FIRST_OFDM_RATE_IDX 4 #define ath10k_a_rates (ath10k_rates + ATH10K_MAC_FIRST_OFDM_RATE_IDX) @@ -70,6 +101,9 @@ #define ath10k_g_rates (ath10k_rates + 0) #define ath10k_g_rates_size (ARRAY_SIZE(ath10k_rates)) +#define ath10k_g_rates_rev2 (ath10k_rates_rev2 + 0) +#define ath10k_g_rates_rev2_size (ARRAY_SIZE(ath10k_rates_rev2)) + static bool ath10k_mac_bitrate_is_cck(int bitrate) { switch (bitrate) { @@ -90,7 +124,7 @@ } u8 ath10k_mac_hw_rate_to_idx(const struct ieee80211_supported_band *sband, - u8 hw_rate) + u8 hw_rate, bool cck) { const struct ieee80211_rate *rate; int i; @@ -98,6 +132,9 @@ for (i = 0; i < sband->n_bitrates; i++) { rate = &sband->bitrates[i]; + if (ath10k_mac_bitrate_is_cck(rate->bitrate) != cck) + continue; + if (rate->hw_value == hw_rate) return i; else if (rate->flags & IEEE80211_RATE_SHORT_PREAMBLE && @@ -154,6 +191,26 @@ return 1; } +int ath10k_mac_ext_resource_config(struct ath10k *ar, u32 val) +{ + enum wmi_host_platform_type platform_type; + int ret; + + if (test_bit(WMI_SERVICE_TX_MODE_DYNAMIC, ar->wmi.svc_map)) + platform_type = WMI_HOST_PLATFORM_LOW_PERF; + else + platform_type = WMI_HOST_PLATFORM_HIGH_PERF; + + ret = ath10k_wmi_ext_resource_config(ar, platform_type, val); + + if (ret && ret != -EOPNOTSUPP) { + ath10k_warn(ar, "failed to configure ext resource: %d\n", ret); + return ret; + } + + return 0; +} + /**********/ /* Crypto */ /**********/ @@ -247,7 +304,8 @@ lockdep_assert_held(&ar->conf_mutex); if (WARN_ON(arvif->vif->type != NL80211_IFTYPE_AP && - arvif->vif->type != NL80211_IFTYPE_ADHOC)) + arvif->vif->type != NL80211_IFTYPE_ADHOC && + arvif->vif->type != NL80211_IFTYPE_MESH_POINT)) return -EINVAL; spin_lock_bh(&ar->data_lock); @@ -445,10 +503,10 @@ lockdep_assert_held(&ar->conf_mutex); list_for_each_entry(peer, &ar->peers, list) { - if (!memcmp(peer->addr, arvif->vif->addr, ETH_ALEN)) + if (ether_addr_equal(peer->addr, arvif->vif->addr)) continue; - if (!memcmp(peer->addr, arvif->bssid, ETH_ALEN)) + if (ether_addr_equal(peer->addr, arvif->bssid)) continue; if (peer->keys[key->keyidx] == key) @@ -614,10 +672,45 @@ *def = &conf->def; } -static int ath10k_peer_create(struct ath10k *ar, u32 vdev_id, const u8 *addr, +static int ath10k_peer_delete(struct ath10k *ar, u32 vdev_id, const u8 *addr) +{ + int ret; + unsigned long time_left; + + lockdep_assert_held(&ar->conf_mutex); + + ret = ath10k_wmi_peer_delete(ar, vdev_id, addr); + if (ret) + return ret; + + ret = ath10k_wait_for_peer_deleted(ar, vdev_id, addr); + if (ret) + return ret; + + if (QCA_REV_WCN3990(ar)) { + time_left = wait_for_completion_timeout(&ar->peer_delete_done, + 50 * HZ); + + if (time_left == 0) { + ath10k_warn(ar, "Timeout in receiving peer delete response\n"); + return -ETIMEDOUT; + } + } + + ar->num_peers--; + + return 0; +} + +static int ath10k_peer_create(struct ath10k *ar, + struct ieee80211_vif *vif, + struct ieee80211_sta *sta, + u32 vdev_id, + const u8 *addr, enum wmi_peer_type peer_type) { struct ath10k_vif *arvif; + struct ath10k_peer *peer; int num_peers = 0; int ret; @@ -646,6 +739,22 @@ return ret; } + spin_lock_bh(&ar->data_lock); + + peer = ath10k_peer_find(ar, vdev_id, addr); + if (!peer) { + spin_unlock_bh(&ar->data_lock); + ath10k_warn(ar, "failed to find peer %pM on vdev %i after creation\n", + addr, vdev_id); + ath10k_peer_delete(ar, vdev_id, addr); + return -ENOENT; + } + + peer->vif = vif; + peer->sta = sta; + + spin_unlock_bh(&ar->data_lock); + ar->num_peers++; return 0; @@ -705,28 +814,11 @@ return ath10k_wmi_vdev_set_param(ar, arvif->vdev_id, vdev_param, value); } -static int ath10k_peer_delete(struct ath10k *ar, u32 vdev_id, const u8 *addr) -{ - int ret; - - lockdep_assert_held(&ar->conf_mutex); - - ret = ath10k_wmi_peer_delete(ar, vdev_id, addr); - if (ret) - return ret; - - ret = ath10k_wait_for_peer_deleted(ar, vdev_id, addr); - if (ret) - return ret; - - ar->num_peers--; - - return 0; -} - static void ath10k_peer_cleanup(struct ath10k *ar, u32 vdev_id) { struct ath10k_peer *peer, *tmp; + int peer_id; + int i; lockdep_assert_held(&ar->conf_mutex); @@ -738,6 +830,22 @@ ath10k_warn(ar, "removing stale peer %pM from vdev_id %d\n", peer->addr, vdev_id); + for_each_set_bit(peer_id, peer->peer_ids, + ATH10K_MAX_NUM_PEER_IDS) { + ar->peer_map[peer_id] = NULL; + } + + /* Double check that peer is properly un-referenced from + * the peer_map + */ + for (i = 0; i < ARRAY_SIZE(ar->peer_map); i++) { + if (ar->peer_map[i] == peer) { + ath10k_warn(ar, "removing stale peer_map entry for %pM (ptr %pK idx %d)\n", + peer->addr, peer, i); + ar->peer_map[i] = NULL; + } + } + list_del(&peer->list); kfree(peer); ar->num_peers--; @@ -748,6 +856,7 @@ static void ath10k_peer_cleanup_all(struct ath10k *ar) { struct ath10k_peer *peer, *tmp; + int i; lockdep_assert_held(&ar->conf_mutex); @@ -756,6 +865,10 @@ list_del(&peer->list); kfree(peer); } + + for (i = 0; i < ARRAY_SIZE(ar->peer_map); i++) + ar->peer_map[i] = NULL; + spin_unlock_bh(&ar->data_lock); ar->num_peers = 0; @@ -886,6 +999,7 @@ arg.channel.max_antenna_gain = channel->max_antenna_gain * 2; reinit_completion(&ar->vdev_setup_done); + reinit_completion(&ar->vdev_delete_done); ret = ath10k_wmi_vdev_start(ar, &arg); if (ret) { @@ -935,6 +1049,7 @@ ar->monitor_vdev_id, ret); reinit_completion(&ar->vdev_setup_done); + reinit_completion(&ar->vdev_delete_done); ret = ath10k_wmi_vdev_stop(ar, ar->monitor_vdev_id); if (ret) @@ -1187,15 +1302,18 @@ set_bit(ATH10K_CAC_RUNNING, &ar->dev_flags); + if (!QCA_REV_WCN3990(ar)) { ret = ath10k_monitor_recalc(ar); if (ret) { - ath10k_warn(ar, "failed to start monitor (cac): %d\n", ret); + ath10k_warn(ar, "failed to start monitor (cac): %d\n", + ret); clear_bit(ATH10K_CAC_RUNNING, &ar->dev_flags); return ret; } ath10k_dbg(ar, ATH10K_DBG_MAC, "mac cac start monitor vdev %d\n", ar->monitor_vdev_id); + } return 0; } @@ -1209,6 +1327,7 @@ return 0; clear_bit(ATH10K_CAC_RUNNING, &ar->dev_flags); + if (!QCA_REV_WCN3990(ar)) ath10k_monitor_stop(ar); ath10k_dbg(ar, ATH10K_DBG_MAC, "mac cac finished\n"); @@ -1271,6 +1390,7 @@ lockdep_assert_held(&ar->conf_mutex); reinit_completion(&ar->vdev_setup_done); + reinit_completion(&ar->vdev_delete_done); ret = ath10k_wmi_vdev_stop(ar, arvif->vdev_id); if (ret) { @@ -1306,7 +1426,12 @@ lockdep_assert_held(&ar->conf_mutex); + /* Clear arp and ns offload cache */ + memset(&arvif->arp_offload, 0, sizeof(arvif->arp_offload)); + memset(&arvif->ns_offload, 0, sizeof(arvif->ns_offload)); + reinit_completion(&ar->vdev_setup_done); + reinit_completion(&ar->vdev_delete_done); arg.vdev_id = arvif->vdev_id; arg.dtim_period = arvif->dtim_period; @@ -1384,10 +1509,7 @@ const u8 *p2p_ie; int ret; - if (arvif->vdev_type != WMI_VDEV_TYPE_AP) - return 0; - - if (arvif->vdev_subtype != WMI_VDEV_SUBTYPE_P2P_GO) + if (arvif->vif->type != NL80211_IFTYPE_AP || !arvif->vif->p2p) return 0; mgmt = (void *)bcn->data; @@ -1754,7 +1876,7 @@ if (enable_ps && ath10k_mac_num_vifs_started(ar) > 1 && !test_bit(ATH10K_FW_FEATURE_MULTI_VIF_PS_SUPPORT, - ar->fw_features)) { + ar->running_fw->fw_file.fw_features)) { ath10k_warn(ar, "refusing to enable ps on vdev %i: not supported by fw\n", arvif->vdev_id); enable_ps = false; @@ -1990,7 +2112,7 @@ ether_addr_copy(arg->addr, sta->addr); arg->vdev_id = arvif->vdev_id; arg->peer_aid = aid; - arg->peer_flags |= WMI_PEER_AUTH; + arg->peer_flags |= arvif->ar->wmi.peer_flags->auth; arg->peer_listen_intval = ath10k_peer_assoc_h_listen_intval(ar, vif); arg->peer_num_spatial_streams = 1; arg->peer_caps = vif->bss_conf.assoc_capability; @@ -1998,6 +2120,7 @@ static void ath10k_peer_assoc_h_crypto(struct ath10k *ar, struct ieee80211_vif *vif, + struct ieee80211_sta *sta, struct wmi_peer_assoc_complete_arg *arg) { struct ieee80211_bss_conf *info = &vif->bss_conf; @@ -2032,12 +2155,18 @@ /* FIXME: base on RSN IE/WPA IE is a correct idea? */ if (rsnie || wpaie) { ath10k_dbg(ar, ATH10K_DBG_WMI, "%s: rsn ie found\n", __func__); - arg->peer_flags |= WMI_PEER_NEED_PTK_4_WAY; + arg->peer_flags |= ar->wmi.peer_flags->need_ptk_4_way; } if (wpaie) { ath10k_dbg(ar, ATH10K_DBG_WMI, "%s: wpa ie found\n", __func__); - arg->peer_flags |= WMI_PEER_NEED_GTK_2_WAY; + arg->peer_flags |= ar->wmi.peer_flags->need_gtk_2_way; + } + + if (sta->mfp && + test_bit(ATH10K_FW_FEATURE_MFP_SUPPORT, + ar->running_fw->fw_file.fw_features)) { + arg->peer_flags |= ar->wmi.peer_flags->pmf; } } @@ -2134,7 +2263,7 @@ ath10k_peer_assoc_h_vht_masked(vht_mcs_mask)) return; - arg->peer_flags |= WMI_PEER_HT; + arg->peer_flags |= ar->wmi.peer_flags->ht; arg->peer_max_mpdu = (1 << (IEEE80211_HT_MAX_AMPDU_FACTOR + ht_cap->ampdu_factor)) - 1; @@ -2145,10 +2274,10 @@ arg->peer_rate_caps |= WMI_RC_HT_FLAG; if (ht_cap->cap & IEEE80211_HT_CAP_LDPC_CODING) - arg->peer_flags |= WMI_PEER_LDPC; + arg->peer_flags |= ar->wmi.peer_flags->ldbc; if (sta->bandwidth >= IEEE80211_STA_RX_BW_40) { - arg->peer_flags |= WMI_PEER_40MHZ; + arg->peer_flags |= ar->wmi.peer_flags->bw40; arg->peer_rate_caps |= WMI_RC_CW40_FLAG; } @@ -2162,7 +2291,7 @@ if (ht_cap->cap & IEEE80211_HT_CAP_TX_STBC) { arg->peer_rate_caps |= WMI_RC_TX_STBC_FLAG; - arg->peer_flags |= WMI_PEER_STBC; + arg->peer_flags |= ar->wmi.peer_flags->stbc; } if (ht_cap->cap & IEEE80211_HT_CAP_RX_STBC) { @@ -2170,7 +2299,7 @@ stbc = stbc >> IEEE80211_HT_CAP_RX_STBC_SHIFT; stbc = stbc << WMI_RC_RX_STBC_FLAG_S; arg->peer_rate_caps |= stbc; - arg->peer_flags |= WMI_PEER_STBC; + arg->peer_flags |= ar->wmi.peer_flags->stbc; } if (ht_cap->mcs.rx_mask[1] && ht_cap->mcs.rx_mask[2]) @@ -2351,10 +2480,10 @@ if (ath10k_peer_assoc_h_vht_masked(vht_mcs_mask)) return; - arg->peer_flags |= WMI_PEER_VHT; + arg->peer_flags |= ar->wmi.peer_flags->vht; if (def.chan->band == IEEE80211_BAND_2GHZ) - arg->peer_flags |= WMI_PEER_VHT_2G; + arg->peer_flags |= ar->wmi.peer_flags->vht_2g; arg->peer_vht_caps = vht_cap->cap; @@ -2371,7 +2500,7 @@ ampdu_factor)) - 1); if (sta->bandwidth == IEEE80211_STA_RX_BW_80) - arg->peer_flags |= WMI_PEER_80MHZ; + arg->peer_flags |= ar->wmi.peer_flags->bw80; arg->peer_vht_rates.rx_max_rate = __le16_to_cpu(vht_cap->vht_mcs.rx_highest); @@ -2396,27 +2525,28 @@ switch (arvif->vdev_type) { case WMI_VDEV_TYPE_AP: if (sta->wme) - arg->peer_flags |= WMI_PEER_QOS; + arg->peer_flags |= arvif->ar->wmi.peer_flags->qos; if (sta->wme && sta->uapsd_queues) { - arg->peer_flags |= WMI_PEER_APSD; + arg->peer_flags |= arvif->ar->wmi.peer_flags->apsd; arg->peer_rate_caps |= WMI_RC_UAPSD_FLAG; } break; case WMI_VDEV_TYPE_STA: if (vif->bss_conf.qos) - arg->peer_flags |= WMI_PEER_QOS; + arg->peer_flags |= arvif->ar->wmi.peer_flags->qos; break; case WMI_VDEV_TYPE_IBSS: if (sta->wme) - arg->peer_flags |= WMI_PEER_QOS; + arg->peer_flags |= arvif->ar->wmi.peer_flags->qos; break; default: break; } ath10k_dbg(ar, ATH10K_DBG_MAC, "mac peer %pM qos %d\n", - sta->addr, !!(arg->peer_flags & WMI_PEER_QOS)); + sta->addr, !!(arg->peer_flags & + arvif->ar->wmi.peer_flags->qos)); } static bool ath10k_mac_sta_has_ofdm_only(struct ieee80211_sta *sta) @@ -2509,7 +2639,7 @@ memset(arg, 0, sizeof(*arg)); ath10k_peer_assoc_h_basic(ar, vif, sta, arg); - ath10k_peer_assoc_h_crypto(ar, vif, arg); + ath10k_peer_assoc_h_crypto(ar, vif, sta, arg); ath10k_peer_assoc_h_rates(ar, vif, sta, arg); ath10k_peer_assoc_h_ht(ar, vif, sta, arg); ath10k_peer_assoc_h_vht(ar, vif, sta, arg); @@ -2721,17 +2851,19 @@ ret = ath10k_wmi_vdev_down(ar, arvif->vdev_id); if (ret) - ath10k_warn(ar, "faield to down vdev %i: %d\n", + ath10k_warn(ar, "failed to down vdev %i: %d\n", arvif->vdev_id, ret); arvif->def_wep_key_idx = -1; + if (!QCA_REV_WCN3990(ar)) { ret = ath10k_mac_vif_recalc_txbf(ar, vif, vht_cap); if (ret) { ath10k_warn(ar, "failed to recalc txbf for vdev %i: %d\n", arvif->vdev_id, ret); return; } + } arvif->is_up = false; @@ -2967,7 +3099,7 @@ regpair = ar->ath_common.regulatory.regpair; - if (config_enabled(CONFIG_ATH10K_DFS_CERTIFIED) && ar->dfs_detector) { + if (IS_ENABLED(CONFIG_ATH10K_DFS_CERTIFIED) && ar->dfs_detector) { nl_dfs_reg = ar->dfs_detector->region; wmi_dfs_reg = ath10k_mac_get_dfs_region(nl_dfs_reg); } else { @@ -2996,7 +3128,7 @@ ath_reg_notifier_apply(wiphy, request, &ar->ath_common.regulatory); - if (config_enabled(CONFIG_ATH10K_DFS_CERTIFIED) && ar->dfs_detector) { + if (IS_ENABLED(CONFIG_ATH10K_DFS_CERTIFIED) && ar->dfs_detector) { ath10k_dbg(ar, ATH10K_DBG_REGULATORY, "dfs region 0x%x\n", request->dfs_region); result = ar->dfs_detector->set_dfs_domain(ar->dfs_detector, @@ -3016,6 +3148,13 @@ /* TX handlers */ /***************/ +enum ath10k_mac_tx_path { + ATH10K_MAC_TX_HTT, + ATH10K_MAC_TX_HTT_MGMT, + ATH10K_MAC_TX_WMI_MGMT, + ATH10K_MAC_TX_UNKNOWN, +}; + void ath10k_mac_tx_lock(struct ath10k *ar, int reason) { lockdep_assert_held(&ar->htt.tx_lock); @@ -3142,35 +3281,11 @@ spin_unlock_bh(&ar->htt.tx_lock); } -static u8 ath10k_tx_h_get_tid(struct ieee80211_hdr *hdr) -{ - if (ieee80211_is_mgmt(hdr->frame_control)) - return HTT_DATA_TX_EXT_TID_MGMT; - - if (!ieee80211_is_data_qos(hdr->frame_control)) - return HTT_DATA_TX_EXT_TID_NON_QOS_MCAST_BCAST; - - if (!is_unicast_ether_addr(ieee80211_get_DA(hdr))) - return HTT_DATA_TX_EXT_TID_NON_QOS_MCAST_BCAST; - - return ieee80211_get_qos_ctl(hdr)[0] & IEEE80211_QOS_CTL_TID_MASK; -} - -static u8 ath10k_tx_h_get_vdev_id(struct ath10k *ar, struct ieee80211_vif *vif) -{ - if (vif) - return ath10k_vif_to_arvif(vif)->vdev_id; - - if (ar->monitor_started) - return ar->monitor_vdev_id; - - ath10k_warn(ar, "failed to resolve vdev id\n"); - return 0; -} - static enum ath10k_hw_txrx_mode -ath10k_tx_h_get_txmode(struct ath10k *ar, struct ieee80211_vif *vif, - struct ieee80211_sta *sta, struct sk_buff *skb) +ath10k_mac_tx_h_get_txmode(struct ath10k *ar, + struct ieee80211_vif *vif, + struct ieee80211_sta *sta, + struct sk_buff *skb) { const struct ieee80211_hdr *hdr = (void *)skb->data; __le16 fc = hdr->frame_control; @@ -3199,7 +3314,10 @@ */ if (ar->htt.target_version_major < 3 && (ieee80211_is_nullfunc(fc) || ieee80211_is_qos_nullfunc(fc)) && - !test_bit(ATH10K_FW_FEATURE_HAS_WMI_MGMT_TX, ar->fw_features)) + !test_bit(ATH10K_FW_FEATURE_HAS_WMI_MGMT_TX, + ar->running_fw->fw_file.fw_features) && + !test_bit(ATH10K_FW_FEATURE_SKIP_NULL_FUNC_WAR, + ar->running_fw->fw_file.fw_features)) return ATH10K_HW_TXRX_MGMT; /* Workaround: @@ -3220,14 +3338,22 @@ } static bool ath10k_tx_h_use_hwcrypto(struct ieee80211_vif *vif, - struct sk_buff *skb) { - struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); + struct sk_buff *skb) +{ + const struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); + const struct ieee80211_hdr *hdr = (void *)skb->data; const u32 mask = IEEE80211_TX_INTFL_DONT_ENCRYPT | IEEE80211_TX_CTL_INJECTED; + + if (!ieee80211_has_protected(hdr->frame_control)) + return false; + if ((info->flags & mask) == mask) return false; + if (vif) return !ath10k_vif_to_arvif(vif)->nohwcrypt; + return true; } @@ -3254,7 +3380,7 @@ */ hdr = (void *)skb->data; if (ieee80211_is_qos_nullfunc(hdr->frame_control)) - cb->htt.tid = HTT_DATA_TX_EXT_TID_NON_QOS_MCAST_BCAST; + cb->flags &= ~ATH10K_SKB_F_QOS; hdr->frame_control &= ~__cpu_to_le16(IEEE80211_STYPE_QOS_DATA); } @@ -3294,8 +3420,7 @@ struct ath10k_vif *arvif = ath10k_vif_to_arvif(vif); /* This is case only for P2P_GO */ - if (arvif->vdev_type != WMI_VDEV_TYPE_AP || - arvif->vdev_subtype != WMI_VDEV_SUBTYPE_P2P_GO) + if (vif->type != NL80211_IFTYPE_AP || !vif->p2p) return; if (unlikely(ieee80211_is_probe_resp(hdr->frame_control))) { @@ -3310,7 +3435,29 @@ } } -static bool ath10k_mac_need_offchan_tx_work(struct ath10k *ar) +static void ath10k_mac_tx_h_fill_cb(struct ath10k *ar, + struct ieee80211_vif *vif, + struct ieee80211_txq *txq, + struct sk_buff *skb) +{ + struct ieee80211_hdr *hdr = (void *)skb->data; + struct ath10k_skb_cb *cb = ATH10K_SKB_CB(skb); + + cb->flags = 0; + if (!ath10k_tx_h_use_hwcrypto(vif, skb)) + cb->flags |= ATH10K_SKB_F_NO_HWCRYPT; + + if (ieee80211_is_mgmt(hdr->frame_control)) + cb->flags |= ATH10K_SKB_F_MGMT; + + if (ieee80211_is_data_qos(hdr->frame_control)) + cb->flags |= ATH10K_SKB_F_QOS; + + cb->vif = vif; + cb->txq = txq; +} + +bool ath10k_mac_tx_frm_has_freq(struct ath10k *ar) { /* FIXME: Not really sure since when the behaviour changed. At some * point new firmware stopped requiring creation of peer entries for @@ -3318,8 +3465,9 @@ * tx credit replenishment and reliability). Assuming it's at least 3.4 * because that's when the `freq` was introduced to TX_FRM HTT command. */ - return !(ar->htt.target_version_major >= 3 && - ar->htt.target_version_minor >= 4); + return (ar->htt.target_version_major >= 3 && + ar->htt.target_version_minor >= 4 && + ar->running_fw->fw_file.htt_op_version == ATH10K_FW_HTT_OP_VERSION_TLV); } static int ath10k_mac_tx_wmi_mgmt(struct ath10k *ar, struct sk_buff *skb) @@ -3344,27 +3492,53 @@ return ret; } -static void ath10k_mac_tx(struct ath10k *ar, struct sk_buff *skb) +static enum ath10k_mac_tx_path +ath10k_mac_tx_h_get_txpath(struct ath10k *ar, + struct sk_buff *skb, + enum ath10k_hw_txrx_mode txmode) { - struct ath10k_skb_cb *cb = ATH10K_SKB_CB(skb); - struct ath10k_htt *htt = &ar->htt; - int ret = 0; - - switch (cb->txmode) { + switch (txmode) { case ATH10K_HW_TXRX_RAW: case ATH10K_HW_TXRX_NATIVE_WIFI: case ATH10K_HW_TXRX_ETHERNET: - ret = ath10k_htt_tx(htt, skb); - break; + return ATH10K_MAC_TX_HTT; case ATH10K_HW_TXRX_MGMT: if (test_bit(ATH10K_FW_FEATURE_HAS_WMI_MGMT_TX, - ar->fw_features)) - ret = ath10k_mac_tx_wmi_mgmt(ar, skb); + ar->running_fw->fw_file.fw_features) || + test_bit(WMI_SERVICE_MGMT_TX_WMI, + ar->wmi.svc_map)) + return ATH10K_MAC_TX_WMI_MGMT; else if (ar->htt.target_version_major >= 3) - ret = ath10k_htt_tx(htt, skb); + return ATH10K_MAC_TX_HTT; else + return ATH10K_MAC_TX_HTT_MGMT; + } + + return ATH10K_MAC_TX_UNKNOWN; +} + +static int ath10k_mac_tx_submit(struct ath10k *ar, + enum ath10k_hw_txrx_mode txmode, + enum ath10k_mac_tx_path txpath, + struct sk_buff *skb) +{ + struct ath10k_htt *htt = &ar->htt; + int ret = -EINVAL; + + switch (txpath) { + case ATH10K_MAC_TX_HTT: + ret = ath10k_htt_tx(htt, txmode, skb); + break; + case ATH10K_MAC_TX_HTT_MGMT: ret = ath10k_htt_mgmt_tx(htt, skb); break; + case ATH10K_MAC_TX_WMI_MGMT: + ret = ath10k_mac_tx_wmi_mgmt(ar, skb); + break; + case ATH10K_MAC_TX_UNKNOWN: + WARN_ON_ONCE(1); + ret = -EINVAL; + break; } if (ret) { @@ -3372,6 +3546,65 @@ ret); ieee80211_free_txskb(ar->hw, skb); } + + return ret; +} + +/* This function consumes the sk_buff regardless of return value as far as + * caller is concerned so no freeing is necessary afterwards. + */ +static int ath10k_mac_tx(struct ath10k *ar, + struct ieee80211_vif *vif, + struct ieee80211_sta *sta, + enum ath10k_hw_txrx_mode txmode, + enum ath10k_mac_tx_path txpath, + struct sk_buff *skb) +{ + struct ieee80211_hw *hw = ar->hw; + struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); + int ret; + + skb_orphan(skb); + /* We should disable CCK RATE due to P2P */ + if (info->flags & IEEE80211_TX_CTL_NO_CCK_RATE) + ath10k_dbg(ar, ATH10K_DBG_MAC, "IEEE80211_TX_CTL_NO_CCK_RATE\n"); + + switch (txmode) { + case ATH10K_HW_TXRX_MGMT: + case ATH10K_HW_TXRX_NATIVE_WIFI: + ath10k_tx_h_nwifi(hw, skb); + ath10k_tx_h_add_p2p_noa_ie(ar, vif, skb); + ath10k_tx_h_seq_no(vif, skb); + break; + case ATH10K_HW_TXRX_ETHERNET: + ath10k_tx_h_8023(skb); + break; + case ATH10K_HW_TXRX_RAW: + if (!test_bit(ATH10K_FLAG_RAW_MODE, &ar->dev_flags)) { + WARN_ON_ONCE(1); + ieee80211_free_txskb(hw, skb); + return -ENOTSUPP; + } + } + + if (info->flags & IEEE80211_TX_CTL_TX_OFFCHAN) { + if (!ath10k_mac_tx_frm_has_freq(ar)) { + ath10k_dbg(ar, ATH10K_DBG_MAC, "queued offchannel skb %pK\n", + skb); + + skb_queue_tail(&ar->offchan_tx_queue, skb); + ieee80211_queue_work(hw, &ar->offchan_tx_work); + return 0; + } + } + + ret = ath10k_mac_tx_submit(ar, txmode, txpath, skb); + if (ret) { + ath10k_warn(ar, "failed to submit frame: %d\n", ret); + return ret; + } + + return 0; } void ath10k_offchan_tx_purge(struct ath10k *ar) @@ -3391,7 +3624,12 @@ { struct ath10k *ar = container_of(work, struct ath10k, offchan_tx_work); struct ath10k_peer *peer; + struct ath10k_vif *arvif; + enum ath10k_hw_txrx_mode txmode; + enum ath10k_mac_tx_path txpath; struct ieee80211_hdr *hdr; + struct ieee80211_vif *vif; + struct ieee80211_sta *sta; struct sk_buff *skb; const u8 *peer_addr; int vdev_id; @@ -3413,14 +3651,14 @@ mutex_lock(&ar->conf_mutex); - ath10k_dbg(ar, ATH10K_DBG_MAC, "mac offchannel skb %p\n", + ath10k_dbg(ar, ATH10K_DBG_MAC, "mac offchannel skb %pK\n", skb); hdr = (struct ieee80211_hdr *)skb->data; peer_addr = ieee80211_get_DA(hdr); - vdev_id = ATH10K_SKB_CB(skb)->vdev_id; spin_lock_bh(&ar->data_lock); + vdev_id = ar->scan.vdev_id; peer = ath10k_peer_find(ar, vdev_id, peer_addr); spin_unlock_bh(&ar->data_lock); @@ -3430,7 +3668,8 @@ peer_addr, vdev_id); if (!peer) { - ret = ath10k_peer_create(ar, vdev_id, peer_addr, + ret = ath10k_peer_create(ar, NULL, NULL, vdev_id, + peer_addr, WMI_PEER_TYPE_DEFAULT); if (ret) ath10k_warn(ar, "failed to create peer %pM on vdev %d: %d\n", @@ -3443,12 +3682,33 @@ ar->offchan_tx_skb = skb; spin_unlock_bh(&ar->data_lock); - ath10k_mac_tx(ar, skb); + /* It's safe to access vif and sta - conf_mutex guarantees that + * sta_state() and remove_interface() are locked exclusively + * out wrt to this offchannel worker. + */ + arvif = ath10k_get_arvif(ar, vdev_id); + if (arvif) { + vif = arvif->vif; + sta = ieee80211_find_sta(vif, peer_addr); + } else { + vif = NULL; + sta = NULL; + } + + txmode = ath10k_mac_tx_h_get_txmode(ar, vif, sta, skb); + txpath = ath10k_mac_tx_h_get_txpath(ar, skb, txmode); + + ret = ath10k_mac_tx(ar, vif, sta, txmode, txpath, skb); + if (ret) { + ath10k_warn(ar, "failed to transmit offchannel frame: %d\n", + ret); + /* not serious */ + } time_left = wait_for_completion_timeout(&ar->offchan_tx_completed, 3 * HZ); if (time_left == 0) - ath10k_warn(ar, "timed out waiting for offchannel skb %p\n", + ath10k_warn(ar, "timed out waiting for offchannel skb %pK\n", skb); if (!peer && tmp_peer_created) { @@ -3479,6 +3739,7 @@ { struct ath10k *ar = container_of(work, struct ath10k, wmi_mgmt_tx_work); struct sk_buff *skb; + dma_addr_t paddr; int ret; for (;;) { @@ -3486,6 +3747,20 @@ if (!skb) break; + if (QCA_REV_WCN3990(ar)) { + paddr = dma_map_single(ar->dev, skb->data, + skb->len, DMA_TO_DEVICE); + if (!paddr) + continue; + ret = ath10k_wmi_mgmt_tx_send(ar, skb, paddr); + if (ret) { + ath10k_warn(ar, "failed to transmit management frame by ref via WMI: %d\n", + ret); + dma_unmap_single(ar->dev, paddr, skb->len, + DMA_FROM_DEVICE); + ieee80211_free_txskb(ar->hw, skb); + } + } else { ret = ath10k_wmi_mgmt_tx(ar, skb); if (ret) { ath10k_warn(ar, "failed to transmit management frame via WMI: %d\n", @@ -3494,6 +3769,201 @@ } } } +} + +static void ath10k_mac_txq_init(struct ieee80211_txq *txq) +{ + struct ath10k_txq *artxq; + + if (!txq) + return; + + artxq = (void *)txq->drv_priv; + INIT_LIST_HEAD(&artxq->list); +} + +static void ath10k_mac_txq_unref(struct ath10k *ar, struct ieee80211_txq *txq) +{ + struct ath10k_txq *artxq; + struct ath10k_skb_cb *cb; + struct sk_buff *msdu; + int msdu_id; + + if (!txq) + return; + + artxq = (void *)txq->drv_priv; + spin_lock_bh(&ar->txqs_lock); + if (!list_empty(&artxq->list)) + list_del_init(&artxq->list); + spin_unlock_bh(&ar->txqs_lock); + + spin_lock_bh(&ar->htt.tx_lock); + idr_for_each_entry(&ar->htt.pending_tx, msdu, msdu_id) { + cb = ATH10K_SKB_CB(msdu); + if (cb->txq == txq) + cb->txq = NULL; + } + spin_unlock_bh(&ar->htt.tx_lock); +} + +struct ieee80211_txq *ath10k_mac_txq_lookup(struct ath10k *ar, + u16 peer_id, + u8 tid) +{ + struct ath10k_peer *peer; + + lockdep_assert_held(&ar->data_lock); + + peer = ar->peer_map[peer_id]; + if (!peer) + return NULL; + + if (peer->sta) + return peer->sta->txq[tid]; + else if (peer->vif) + return peer->vif->txq; + else + return NULL; +} + +static bool ath10k_mac_tx_can_push(struct ieee80211_hw *hw, + struct ieee80211_txq *txq) +{ + struct ath10k *ar = hw->priv; + struct ath10k_txq *artxq = (void *)txq->drv_priv; + + /* No need to get locks */ + + if (ar->htt.tx_q_state.mode == HTT_TX_MODE_SWITCH_PUSH) + return true; + + if (ar->htt.num_pending_tx < ar->htt.tx_q_state.num_push_allowed) + return true; + + if (artxq->num_fw_queued < artxq->num_push_allowed) + return true; + + return false; +} + +int ath10k_mac_tx_push_txq(struct ieee80211_hw *hw, + struct ieee80211_txq *txq) +{ + struct ath10k *ar = hw->priv; + struct ath10k_htt *htt = &ar->htt; + struct ath10k_txq *artxq = (void *)txq->drv_priv; + struct ieee80211_vif *vif = txq->vif; + struct ieee80211_sta *sta = txq->sta; + enum ath10k_hw_txrx_mode txmode; + enum ath10k_mac_tx_path txpath; + struct sk_buff *skb; + struct ieee80211_hdr *hdr; + size_t skb_len; + bool is_mgmt, is_presp; + int ret; + + spin_lock_bh(&ar->htt.tx_lock); + ret = ath10k_htt_tx_inc_pending(htt); + spin_unlock_bh(&ar->htt.tx_lock); + + if (ret) + return ret; + + skb = ieee80211_tx_dequeue(hw, txq); + if (!skb) { + spin_lock_bh(&ar->htt.tx_lock); + ath10k_htt_tx_dec_pending(htt); + spin_unlock_bh(&ar->htt.tx_lock); + + return -ENOENT; + } + + ath10k_mac_tx_h_fill_cb(ar, vif, txq, skb); + + skb_len = skb->len; + txmode = ath10k_mac_tx_h_get_txmode(ar, vif, sta, skb); + txpath = ath10k_mac_tx_h_get_txpath(ar, skb, txmode); + is_mgmt = (txpath == ATH10K_MAC_TX_HTT_MGMT); + + if (is_mgmt) { + hdr = (struct ieee80211_hdr *)skb->data; + is_presp = ieee80211_is_probe_resp(hdr->frame_control); + + spin_lock_bh(&ar->htt.tx_lock); + ret = ath10k_htt_tx_mgmt_inc_pending(htt, is_mgmt, is_presp); + + if (ret) { + ath10k_htt_tx_dec_pending(htt); + spin_unlock_bh(&ar->htt.tx_lock); + return ret; + } + spin_unlock_bh(&ar->htt.tx_lock); + } + + ret = ath10k_mac_tx(ar, vif, sta, txmode, txpath, skb); + if (unlikely(ret)) { + ath10k_warn(ar, "failed to push frame: %d\n", ret); + + spin_lock_bh(&ar->htt.tx_lock); + ath10k_htt_tx_dec_pending(htt); + if (is_mgmt) + ath10k_htt_tx_mgmt_dec_pending(htt); + spin_unlock_bh(&ar->htt.tx_lock); + + return ret; + } + + spin_lock_bh(&ar->htt.tx_lock); + artxq->num_fw_queued++; + spin_unlock_bh(&ar->htt.tx_lock); + + return skb_len; +} + +void ath10k_mac_tx_push_pending(struct ath10k *ar) +{ + struct ieee80211_hw *hw = ar->hw; + struct ieee80211_txq *txq; + struct ath10k_txq *artxq; + struct ath10k_txq *last; + int ret; + int max; + + if (ar->htt.num_pending_tx >= (ar->htt.max_num_pending_tx / 2)) + return; + + spin_lock_bh(&ar->txqs_lock); + rcu_read_lock(); + + last = list_last_entry(&ar->txqs, struct ath10k_txq, list); + while (!list_empty(&ar->txqs)) { + artxq = list_first_entry(&ar->txqs, struct ath10k_txq, list); + txq = container_of((void *)artxq, struct ieee80211_txq, + drv_priv); + + /* Prevent aggressive sta/tid taking over tx queue */ + max = 16; + ret = 0; + while (ath10k_mac_tx_can_push(hw, txq) && max--) { + ret = ath10k_mac_tx_push_txq(hw, txq); + if (ret < 0) + break; + } + + list_del_init(&artxq->list); + if (ret != -ENOENT) + list_add_tail(&artxq->list, &ar->txqs); + + ath10k_htt_tx_txq_update(hw, txq); + + if (artxq == last || (ret < 0 && ret != -ENOENT)) + break; + } + + rcu_read_unlock(); + spin_unlock_bh(&ar->txqs_lock); +} /************/ /* Scanning */ @@ -3518,9 +3988,10 @@ case ATH10K_SCAN_STARTING: ar->scan.state = ATH10K_SCAN_IDLE; ar->scan_channel = NULL; + ar->scan.roc_freq = 0; ath10k_offchan_tx_purge(ar); cancel_delayed_work(&ar->scan.timeout); - complete_all(&ar->scan.completed); + complete(&ar->scan.completed); break; } } @@ -3656,67 +4127,100 @@ /* mac80211 callbacks */ /**********************/ -static void ath10k_tx(struct ieee80211_hw *hw, +static void ath10k_mac_op_tx(struct ieee80211_hw *hw, struct ieee80211_tx_control *control, struct sk_buff *skb) { struct ath10k *ar = hw->priv; + struct ath10k_htt *htt = &ar->htt; struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); struct ieee80211_vif *vif = info->control.vif; struct ieee80211_sta *sta = control->sta; - struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; - __le16 fc = hdr->frame_control; + struct ieee80211_txq *txq = NULL; + struct ieee80211_hdr *hdr = (void *)skb->data; + enum ath10k_hw_txrx_mode txmode; + enum ath10k_mac_tx_path txpath; + bool is_htt; + bool is_mgmt; + bool is_presp; + int ret; + + ath10k_mac_tx_h_fill_cb(ar, vif, txq, skb); + + txmode = ath10k_mac_tx_h_get_txmode(ar, vif, sta, skb); + txpath = ath10k_mac_tx_h_get_txpath(ar, skb, txmode); + is_htt = (txpath == ATH10K_MAC_TX_HTT || + txpath == ATH10K_MAC_TX_HTT_MGMT); + is_mgmt = (txpath == ATH10K_MAC_TX_HTT_MGMT); - /* We should disable CCK RATE due to P2P */ - if (info->flags & IEEE80211_TX_CTL_NO_CCK_RATE) - ath10k_dbg(ar, ATH10K_DBG_MAC, "IEEE80211_TX_CTL_NO_CCK_RATE\n"); + if (is_htt) { + spin_lock_bh(&ar->htt.tx_lock); + is_presp = ieee80211_is_probe_resp(hdr->frame_control); - ATH10K_SKB_CB(skb)->htt.is_offchan = false; - ATH10K_SKB_CB(skb)->htt.freq = 0; - ATH10K_SKB_CB(skb)->htt.tid = ath10k_tx_h_get_tid(hdr); - ATH10K_SKB_CB(skb)->htt.nohwcrypt = !ath10k_tx_h_use_hwcrypto(vif, skb); - ATH10K_SKB_CB(skb)->vdev_id = ath10k_tx_h_get_vdev_id(ar, vif); - ATH10K_SKB_CB(skb)->txmode = ath10k_tx_h_get_txmode(ar, vif, sta, skb); - ATH10K_SKB_CB(skb)->is_protected = ieee80211_has_protected(fc); + ret = ath10k_htt_tx_inc_pending(htt); + if (ret) { + ath10k_warn(ar, "failed to increase tx pending count: %d, dropping\n", + ret); + spin_unlock_bh(&ar->htt.tx_lock); + ieee80211_free_txskb(ar->hw, skb); + return; + } - switch (ATH10K_SKB_CB(skb)->txmode) { - case ATH10K_HW_TXRX_MGMT: - case ATH10K_HW_TXRX_NATIVE_WIFI: - ath10k_tx_h_nwifi(hw, skb); - ath10k_tx_h_add_p2p_noa_ie(ar, vif, skb); - ath10k_tx_h_seq_no(vif, skb); - break; - case ATH10K_HW_TXRX_ETHERNET: - ath10k_tx_h_8023(skb); - break; - case ATH10K_HW_TXRX_RAW: - if (!test_bit(ATH10K_FLAG_RAW_MODE, &ar->dev_flags)) { - WARN_ON_ONCE(1); - ieee80211_free_txskb(hw, skb); + ret = ath10k_htt_tx_mgmt_inc_pending(htt, is_mgmt, is_presp); + if (ret) { + ath10k_dbg(ar, ATH10K_DBG_MAC, "failed to increase tx mgmt pending count: %d, dropping\n", + ret); + ath10k_htt_tx_dec_pending(htt); + spin_unlock_bh(&ar->htt.tx_lock); + ieee80211_free_txskb(ar->hw, skb); return; } + spin_unlock_bh(&ar->htt.tx_lock); } - if (info->flags & IEEE80211_TX_CTL_TX_OFFCHAN) { - spin_lock_bh(&ar->data_lock); - ATH10K_SKB_CB(skb)->htt.freq = ar->scan.roc_freq; - ATH10K_SKB_CB(skb)->vdev_id = ar->scan.vdev_id; - spin_unlock_bh(&ar->data_lock); + ret = ath10k_mac_tx(ar, vif, sta, txmode, txpath, skb); + if (ret) { + ath10k_warn(ar, "failed to transmit frame: %d\n", ret); + if (is_htt) { + spin_lock_bh(&ar->htt.tx_lock); + ath10k_htt_tx_dec_pending(htt); + if (is_mgmt) + ath10k_htt_tx_mgmt_dec_pending(htt); + spin_unlock_bh(&ar->htt.tx_lock); + } + return; + } +} - if (ath10k_mac_need_offchan_tx_work(ar)) { - ATH10K_SKB_CB(skb)->htt.freq = 0; - ATH10K_SKB_CB(skb)->htt.is_offchan = true; +static void ath10k_mac_op_wake_tx_queue(struct ieee80211_hw *hw, + struct ieee80211_txq *txq) +{ + struct ath10k *ar = hw->priv; + struct ath10k_txq *artxq = (void *)txq->drv_priv; + struct ieee80211_txq *f_txq; + struct ath10k_txq *f_artxq; + int ret = 0; + int max = 16; - ath10k_dbg(ar, ATH10K_DBG_MAC, "queued offchannel skb %p\n", - skb); + spin_lock_bh(&ar->txqs_lock); + if (list_empty(&artxq->list)) + list_add_tail(&artxq->list, &ar->txqs); - skb_queue_tail(&ar->offchan_tx_queue, skb); - ieee80211_queue_work(hw, &ar->offchan_tx_work); - return; - } + f_artxq = list_first_entry(&ar->txqs, struct ath10k_txq, list); + f_txq = container_of((void *)f_artxq, struct ieee80211_txq, drv_priv); + list_del_init(&f_artxq->list); + + while (ath10k_mac_tx_can_push(hw, f_txq) && max--) { + ret = ath10k_mac_tx_push_txq(hw, f_txq); + if (ret) + break; } + if (ret != -ENOENT) + list_add_tail(&f_artxq->list, &ar->txqs); + spin_unlock_bh(&ar->txqs_lock); - ath10k_mac_tx(ar, skb); + ath10k_htt_tx_txq_update(hw, f_txq); + ath10k_htt_tx_txq_update(hw, txq); } /* Must not be called with conf_mutex held as workers can use that also. */ @@ -3856,6 +4360,9 @@ mcs_map |= IEEE80211_VHT_MCS_NOT_SUPPORTED << (i * 2); } + if (ar->cfg_tx_chainmask <= 1) + vht_cap.cap &= ~IEEE80211_VHT_CAP_TXSTBC; + vht_cap.vht_mcs.rx_mcs_map = cpu_to_le16(mcs_map); vht_cap.vht_mcs.tx_mcs_map = cpu_to_le16(mcs_map); @@ -3875,7 +4382,8 @@ ht_cap.ampdu_density = IEEE80211_HT_MPDU_DENSITY_8; ht_cap.cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40; ht_cap.cap |= IEEE80211_HT_CAP_DSSSCCK40; - ht_cap.cap |= WLAN_HT_CAP_SM_PS_STATIC << IEEE80211_HT_CAP_SM_PS_SHIFT; + ht_cap.cap |= + WLAN_HT_CAP_SM_PS_DISABLED << IEEE80211_HT_CAP_SM_PS_SHIFT; if (ar->ht_cap_info & WMI_HT_CAP_HT20_SGI) ht_cap.cap |= IEEE80211_HT_CAP_SGI_20; @@ -3892,7 +4400,7 @@ ht_cap.cap |= smps; } - if (ar->ht_cap_info & WMI_HT_CAP_TX_STBC) + if (ar->ht_cap_info & WMI_HT_CAP_TX_STBC && (ar->cfg_tx_chainmask > 1)) ht_cap.cap |= IEEE80211_HT_CAP_TX_STBC; if (ar->ht_cap_info & WMI_HT_CAP_RX_STBC) { @@ -3939,9 +4447,6 @@ if (ar->phy_capability & WHAL_WLAN_11G_CAPABILITY) { band = &ar->mac.sbands[IEEE80211_BAND_2GHZ]; band->ht_cap = ht_cap; - - /* Enable the VHT support at 2.4 GHz */ - band->vht_cap = vht_cap; } if (ar->phy_capability & WHAL_WLAN_11A_CAPABILITY) { band = &ar->mac.sbands[IEEE80211_BAND_5GHZ]; @@ -4002,12 +4507,12 @@ static int ath10k_start(struct ieee80211_hw *hw) { struct ath10k *ar = hw->priv; - u32 burst_enable; + u32 param; int ret = 0; /* * This makes sense only when restarting hw. It is harmless to call - * uncoditionally. This is necessary to make sure no HTT/WMI tx + * unconditionally. This is necessary to make sure no HTT/WMI tx * commands will be submitted while restarting. */ ath10k_drain_tx(ar); @@ -4019,6 +4524,7 @@ ar->state = ATH10K_STATE_ON; break; case ATH10K_STATE_RESTARTING: + if (!test_bit(ATH10K_FLAG_CRASH_FLUSH, &ar->dev_flags)) ath10k_halt(ar); ar->state = ATH10K_STATE_RESTARTED; break; @@ -4039,24 +4545,34 @@ goto err_off; } - ret = ath10k_core_start(ar, ATH10K_FIRMWARE_MODE_NORMAL); + ret = ath10k_core_start(ar, ATH10K_FIRMWARE_MODE_NORMAL, + &ar->normal_mode_fw); if (ret) { ath10k_err(ar, "Could not init core: %d\n", ret); goto err_power_down; } - ret = ath10k_wmi_pdev_set_param(ar, ar->wmi.pdev_param->pmf_qos, 1); + param = ar->wmi.pdev_param->pmf_qos; + ret = ath10k_wmi_pdev_set_param(ar, param, 1); if (ret) { ath10k_warn(ar, "failed to enable PMF QOS: %d\n", ret); goto err_core_stop; } - ret = ath10k_wmi_pdev_set_param(ar, ar->wmi.pdev_param->dynamic_bw, 1); + param = ar->wmi.pdev_param->dynamic_bw; + ret = ath10k_wmi_pdev_set_param(ar, param, 1); if (ret) { ath10k_warn(ar, "failed to enable dynamic BW: %d\n", ret); goto err_core_stop; } + param = ar->wmi.pdev_param->idle_ps_config; + ret = ath10k_wmi_pdev_set_param(ar, param, 1); + if (ret) { + ath10k_warn(ar, "failed to enable idle_ps_config: %d\n", ret); + goto err_core_stop; + } + if (test_bit(WMI_SERVICE_ADAPTIVE_OCS, ar->wmi.svc_map)) { ret = ath10k_wmi_adaptive_qcs(ar, true); if (ret) { @@ -4067,8 +4583,8 @@ } if (test_bit(WMI_SERVICE_BURST, ar->wmi.svc_map)) { - burst_enable = ar->wmi.pdev_param->burst_enable; - ret = ath10k_wmi_pdev_set_param(ar, burst_enable, 0); + param = ar->wmi.pdev_param->burst_enable; + ret = ath10k_wmi_pdev_set_param(ar, param, 0); if (ret) { ath10k_warn(ar, "failed to disable burst: %d\n", ret); goto err_core_stop; @@ -4086,8 +4602,8 @@ * this problem. */ - ret = ath10k_wmi_pdev_set_param(ar, - ar->wmi.pdev_param->arp_ac_override, 0); + param = ar->wmi.pdev_param->arp_ac_override; + ret = ath10k_wmi_pdev_set_param(ar, param, 0); if (ret) { ath10k_warn(ar, "failed to set arp ac override parameter: %d\n", ret); @@ -4095,7 +4611,7 @@ } if (test_bit(ATH10K_FW_FEATURE_SUPPORTS_ADAPTIVE_CCA, - ar->fw_features)) { + ar->running_fw->fw_file.fw_features)) { ret = ath10k_wmi_pdev_enable_adaptive_cca(ar, 1, WMI_CCA_DETECT_LEVEL_AUTO, WMI_CCA_DETECT_MARGIN_AUTO); @@ -4104,10 +4620,11 @@ ret); goto err_core_stop; } + ar->sifs_burst_enabled = false; } - ret = ath10k_wmi_pdev_set_param(ar, - ar->wmi.pdev_param->ani_enable, 1); + param = ar->wmi.pdev_param->ani_enable; + ret = ath10k_wmi_pdev_set_param(ar, param, 1); if (ret) { ath10k_warn(ar, "failed to enable ani by default: %d\n", ret); @@ -4116,6 +4633,31 @@ ar->ani_enabled = true; + if (ath10k_peer_stats_enabled(ar)) { + param = ar->wmi.pdev_param->peer_stats_update_period; + ret = ath10k_wmi_pdev_set_param(ar, param, + PEER_DEFAULT_STATS_UPDATE_PERIOD); + if (ret) { + ath10k_warn(ar, + "failed to set peer stats period : %d\n", + ret); + goto err_core_stop; + } + } + + param = ar->wmi.pdev_param->enable_btcoex; + if (test_bit(WMI_SERVICE_COEX_GPIO, ar->wmi.svc_map) && + test_bit(ATH10K_FW_FEATURE_BTCOEX_PARAM, + ar->running_fw->fw_file.fw_features)) { + ret = ath10k_wmi_pdev_set_param(ar, param, 0); + if (ret) { + ath10k_warn(ar, + "failed to set btcoex param: %d\n", ret); + goto err_core_stop; + } + clear_bit(ATH10K_FLAG_BTCOEX, &ar->dev_flags); + } + ar->num_started_vdevs = 0; ath10k_regd_update(ar); @@ -4318,6 +4860,7 @@ { struct ath10k *ar = hw->priv; struct ath10k_vif *arvif = ath10k_vif_to_arvif(vif); + struct ath10k_peer *peer; enum wmi_sta_powersave_param param; int ret = 0; u32 value; @@ -4330,6 +4873,7 @@ mutex_lock(&ar->conf_mutex); memset(arvif, 0, sizeof(*arvif)); + ath10k_mac_txq_init(vif->txq); arvif->ar = ar; arvif->vif = vif; @@ -4364,24 +4908,30 @@ bit, ar->free_vdev_map); arvif->vdev_id = bit; - arvif->vdev_subtype = WMI_VDEV_SUBTYPE_NONE; + arvif->vdev_subtype = + ath10k_wmi_get_vdev_subtype(ar, WMI_VDEV_SUBTYPE_NONE); switch (vif->type) { case NL80211_IFTYPE_P2P_DEVICE: arvif->vdev_type = WMI_VDEV_TYPE_STA; - arvif->vdev_subtype = WMI_VDEV_SUBTYPE_P2P_DEVICE; + arvif->vdev_subtype = ath10k_wmi_get_vdev_subtype + (ar, WMI_VDEV_SUBTYPE_P2P_DEVICE); break; case NL80211_IFTYPE_UNSPECIFIED: case NL80211_IFTYPE_STATION: arvif->vdev_type = WMI_VDEV_TYPE_STA; if (vif->p2p) - arvif->vdev_subtype = WMI_VDEV_SUBTYPE_P2P_CLIENT; + arvif->vdev_subtype = ath10k_wmi_get_vdev_subtype + (ar, WMI_VDEV_SUBTYPE_P2P_CLIENT); break; case NL80211_IFTYPE_ADHOC: arvif->vdev_type = WMI_VDEV_TYPE_IBSS; break; case NL80211_IFTYPE_MESH_POINT: - if (!test_bit(ATH10K_FLAG_RAW_MODE, &ar->dev_flags)) { + if (test_bit(WMI_SERVICE_MESH_11S, ar->wmi.svc_map)) { + arvif->vdev_subtype = ath10k_wmi_get_vdev_subtype + (ar, WMI_VDEV_SUBTYPE_MESH_11S); + } else if (!test_bit(ATH10K_FLAG_RAW_MODE, &ar->dev_flags)) { ret = -EINVAL; ath10k_warn(ar, "must load driver with rawmode=1 to add mesh interfaces\n"); goto err; @@ -4392,7 +4942,8 @@ arvif->vdev_type = WMI_VDEV_TYPE_AP; if (vif->p2p) - arvif->vdev_subtype = WMI_VDEV_SUBTYPE_P2P_GO; + arvif->vdev_subtype = ath10k_wmi_get_vdev_subtype + (ar, WMI_VDEV_SUBTYPE_P2P_GO); break; case NL80211_IFTYPE_MONITOR: arvif->vdev_type = WMI_VDEV_TYPE_MONITOR; @@ -4462,6 +5013,15 @@ goto err; } + if ((arvif->vdev_type == WMI_VDEV_TYPE_STA) && QCA_REV_WCN3990(ar)) { + ret = ath10k_wmi_csa_offload(ar, arvif->vdev_id, true); + if (ret) { + ath10k_err(ar, "CSA offload failed for vdev %i: %d\n", + arvif->vdev_id, ret); + goto err_vdev_delete; + } + } + ar->free_vdev_map &= ~(1LL << arvif->vdev_id); list_add(&arvif->list, &ar->arvifs); @@ -4506,13 +5066,31 @@ if (arvif->vdev_type == WMI_VDEV_TYPE_AP || arvif->vdev_type == WMI_VDEV_TYPE_IBSS) { - ret = ath10k_peer_create(ar, arvif->vdev_id, vif->addr, - WMI_PEER_TYPE_DEFAULT); + ret = ath10k_peer_create(ar, vif, NULL, arvif->vdev_id, + vif->addr, WMI_PEER_TYPE_DEFAULT); if (ret) { ath10k_warn(ar, "failed to create vdev %i peer for AP/IBSS: %d\n", arvif->vdev_id, ret); goto err_vdev_delete; } + + spin_lock_bh(&ar->data_lock); + + peer = ath10k_peer_find(ar, arvif->vdev_id, vif->addr); + if (!peer) { + ath10k_warn(ar, "failed to lookup peer %pM on vdev %i\n", + vif->addr, arvif->vdev_id); + spin_unlock_bh(&ar->data_lock); + ret = -ENOENT; + goto err_peer_delete; + } + + arvif->peer_id = find_first_bit(peer->peer_ids, + ATH10K_MAX_NUM_PEER_IDS); + + spin_unlock_bh(&ar->data_lock); + } else { + arvif->peer_id = HTT_INVALID_PEERID; } if (arvif->vdev_type == WMI_VDEV_TYPE_AP) { @@ -4591,7 +5169,7 @@ err_peer_delete: if (arvif->vdev_type == WMI_VDEV_TYPE_AP || arvif->vdev_type == WMI_VDEV_TYPE_IBSS) - ath10k_wmi_peer_delete(ar, arvif->vdev_id, vif->addr); + ath10k_peer_delete(ar, arvif->vdev_id, vif->addr); err_vdev_delete: ath10k_wmi_vdev_delete(ar, arvif->vdev_id); @@ -4623,7 +5201,10 @@ { struct ath10k *ar = hw->priv; struct ath10k_vif *arvif = ath10k_vif_to_arvif(vif); + struct ath10k_peer *peer; + unsigned long time_left; int ret; + int i; cancel_work_sync(&arvif->ap_csa_work); cancel_delayed_work_sync(&arvif->connection_loss_work); @@ -4644,7 +5225,7 @@ if (arvif->vdev_type == WMI_VDEV_TYPE_AP || arvif->vdev_type == WMI_VDEV_TYPE_IBSS) { - ret = ath10k_wmi_peer_delete(arvif->ar, arvif->vdev_id, + ret = ath10k_peer_delete(arvif->ar, arvif->vdev_id, vif->addr); if (ret) ath10k_warn(ar, "failed to submit AP/IBSS self-peer removal on vdev %i: %d\n", @@ -4653,6 +5234,9 @@ kfree(arvif->u.ap.noa_data); } + if ((arvif->vdev_type == WMI_VDEV_TYPE_STA) && QCA_REV_WCN3990(ar)) + ath10k_wmi_csa_offload(ar, arvif->vdev_id, false); + ath10k_dbg(ar, ATH10K_DBG_MAC, "mac vdev %i delete (remove interface)\n", arvif->vdev_id); @@ -4661,6 +5245,16 @@ ath10k_warn(ar, "failed to delete WMI vdev %i: %d\n", arvif->vdev_id, ret); + if (QCA_REV_WCN3990(ar)) { + time_left = wait_for_completion_timeout( + &ar->vdev_delete_done, + ATH10K_VDEV_DELETE_TIMEOUT_HZ); + if (time_left == 0) { + ath10k_warn(ar, "Timeout in receiving vdev delete resp\n"); + return; + } + } + /* Some firmware revisions don't notify host about self-peer removal * until after associated vdev is deleted. */ @@ -4677,7 +5271,22 @@ spin_unlock_bh(&ar->data_lock); } + spin_lock_bh(&ar->data_lock); + for (i = 0; i < ARRAY_SIZE(ar->peer_map); i++) { + peer = ar->peer_map[i]; + if (!peer) + continue; + + if (peer->vif == vif) { + ath10k_warn(ar, "found vif peer %pM entry on vdev %i after it was supposedly removed\n", + vif->addr, arvif->vdev_id); + peer->vif = NULL; + } + } + spin_unlock_bh(&ar->data_lock); + ath10k_peer_cleanup(ar, arvif->vdev_id); + ath10k_mac_txq_unref(ar, vif->txq); if (vif->type == NL80211_IFTYPE_MONITOR) { ar->monitor_arvif = NULL; @@ -4686,13 +5295,39 @@ ath10k_warn(ar, "failed to recalc monitor: %d\n", ret); } + ret = ath10k_mac_txpower_recalc(ar); + if (ret) + ath10k_warn(ar, "failed to recalc tx power: %d\n", ret); + spin_lock_bh(&ar->htt.tx_lock); ath10k_mac_vif_tx_unlock_all(arvif); spin_unlock_bh(&ar->htt.tx_lock); + ath10k_mac_txq_unref(ar, vif->txq); + mutex_unlock(&ar->conf_mutex); } +static int ath10k_change_interface(struct ieee80211_hw *hw, + struct ieee80211_vif *vif, + enum nl80211_iftype new_type, bool p2p) +{ + struct ath10k *ar = hw->priv; + int ret = 0; + + ath10k_dbg(ar, ATH10K_DBG_MAC, + "change_interface new: %d (%d), old: %d (%d)\n", new_type, + p2p, vif->type, vif->p2p); + + if (new_type != vif->type || vif->p2p != p2p) { + ath10k_remove_interface(hw, vif); + vif->type = new_type; + vif->p2p = p2p; + ret = ath10k_add_interface(hw, vif); + } + return ret; +} + /* * FIXME: Has to be verified. */ @@ -4721,7 +5356,7 @@ ret = ath10k_monitor_recalc(ar); if (ret) - ath10k_warn(ar, "failed to recalc montior: %d\n", ret); + ath10k_warn(ar, "failed to recalc monitor: %d\n", ret); mutex_unlock(&ar->conf_mutex); } @@ -4913,7 +5548,8 @@ struct ath10k_vif *arvif = ath10k_vif_to_arvif(vif); struct cfg80211_scan_request *req = &hw_req->req; struct wmi_start_scan_arg arg; - int ret = 0; + const u8 *ptr; + int ret = 0, ie_skip_len = 0; int i; mutex_lock(&ar->conf_mutex); @@ -4945,8 +5581,16 @@ arg.scan_id = ATH10K_SCAN_ID; if (req->ie_len) { - arg.ie_len = req->ie_len; - memcpy(arg.ie, req->ie, arg.ie_len); + if (QCA_REV_WCN3990(ar)) { + ptr = req->ie; + while (ptr[0] == WLAN_EID_SUPP_RATES || + ptr[0] == WLAN_EID_EXT_SUPP_RATES) { + ie_skip_len = ptr[1] + 2; + ptr += ie_skip_len; + } + } + arg.ie_len = req->ie_len - ie_skip_len; + memcpy(arg.ie, req->ie + ie_skip_len, arg.ie_len); } if (req->n_ssids) { @@ -4955,6 +5599,11 @@ arg.ssids[i].len = req->ssids[i].ssid_len; arg.ssids[i].ssid = req->ssids[i].ssid; } + if (QCA_REV_WCN3990(ar)) { + arg.scan_ctrl_flags &= + ~(WMI_SCAN_ADD_BCAST_PROBE_REQ | + WMI_SCAN_CHAN_STAT_EVENT); + } } else { arg.scan_ctrl_flags |= WMI_SCAN_FLAG_PASSIVE; } @@ -5037,6 +5686,22 @@ arvif->vdev_id, ret); } +static void ath10k_set_rekey_data(struct ieee80211_hw *hw, + struct ieee80211_vif *vif, + struct cfg80211_gtk_rekey_data *data) +{ + struct ath10k *ar = hw->priv; + struct ath10k_vif *arvif = ath10k_vif_to_arvif(vif); + + mutex_lock(&ar->conf_mutex); + memcpy(&arvif->gtk_rekey_data.kek, data->kek, NL80211_KEK_LEN); + memcpy(&arvif->gtk_rekey_data.kck, data->kck, NL80211_KCK_LEN); + arvif->gtk_rekey_data.replay_ctr = + be64_to_cpup((__be64 *)data->replay_ctr); + arvif->gtk_rekey_data.valid = true; + mutex_unlock(&ar->conf_mutex); +} + static int ath10k_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd, struct ieee80211_vif *vif, struct ieee80211_sta *sta, struct ieee80211_key_conf *key) @@ -5392,13 +6057,18 @@ struct ath10k *ar = hw->priv; struct ath10k_vif *arvif = ath10k_vif_to_arvif(vif); struct ath10k_sta *arsta = (struct ath10k_sta *)sta->drv_priv; + struct ath10k_peer *peer; int ret = 0; + int i; if (old_state == IEEE80211_STA_NOTEXIST && new_state == IEEE80211_STA_NONE) { memset(arsta, 0, sizeof(*arsta)); arsta->arvif = arvif; INIT_WORK(&arsta->update_wk, ath10k_sta_rc_update_wk); + + for (i = 0; i < ARRAY_SIZE(sta->txq); i++) + ath10k_mac_txq_init(sta->txq[i]); } /* cancel must be done outside the mutex to avoid deadlock */ @@ -5406,6 +6076,9 @@ new_state == IEEE80211_STA_NOTEXIST)) cancel_work_sync(&arsta->update_wk); + if (vif->type == NL80211_IFTYPE_STATION && new_state > ar->sta_state) + ar->sta_state = new_state; + mutex_lock(&ar->conf_mutex); if (old_state == IEEE80211_STA_NOTEXIST && @@ -5433,8 +6106,8 @@ if (sta->tdls) peer_type = WMI_PEER_TYPE_TDLS; - ret = ath10k_peer_create(ar, arvif->vdev_id, sta->addr, - peer_type); + ret = ath10k_peer_create(ar, vif, sta, arvif->vdev_id, + sta->addr, peer_type); if (ret) { ath10k_warn(ar, "failed to add peer %pM for vdev %d when adding a new sta: %i\n", sta->addr, arvif->vdev_id, ret); @@ -5442,6 +6115,24 @@ goto exit; } + spin_lock_bh(&ar->data_lock); + + peer = ath10k_peer_find(ar, arvif->vdev_id, sta->addr); + if (!peer) { + ath10k_warn(ar, "failed to lookup peer %pM on vdev %i\n", + vif->addr, arvif->vdev_id); + spin_unlock_bh(&ar->data_lock); + ath10k_peer_delete(ar, arvif->vdev_id, sta->addr); + ath10k_mac_dec_num_stations(arvif, sta); + ret = -ENOENT; + goto exit; + } + + arsta->peer_id = find_first_bit(peer->peer_ids, + ATH10K_MAX_NUM_PEER_IDS); + + spin_unlock_bh(&ar->data_lock); + if (!sta->tdls) goto exit; @@ -5494,8 +6185,8 @@ * Existing station deletion. */ ath10k_dbg(ar, ATH10K_DBG_MAC, - "mac vdev %d peer delete %pM (sta gone)\n", - arvif->vdev_id, sta->addr); + "mac vdev %d peer delete %pM sta %pK (sta gone)\n", + arvif->vdev_id, sta->addr, sta); ret = ath10k_peer_delete(ar, arvif->vdev_id, sta->addr); if (ret) @@ -5504,6 +6195,31 @@ ath10k_mac_dec_num_stations(arvif, sta); + spin_lock_bh(&ar->data_lock); + for (i = 0; i < ARRAY_SIZE(ar->peer_map); i++) { + peer = ar->peer_map[i]; + if (!peer) + continue; + + if (peer->sta == sta) { + ath10k_warn(ar, "found sta peer %pM (ptr %pK id %d) entry on vdev %i after it was supposedly removed\n", + sta->addr, peer, i, arvif->vdev_id); + peer->sta = NULL; + + /* Clean up the peer object as well since we + * must have failed to do this above. + */ + list_del(&peer->list); + ar->peer_map[i] = NULL; + kfree(peer); + ar->num_peers--; + } + } + spin_unlock_bh(&ar->data_lock); + + for (i = 0; i < ARRAY_SIZE(sta->txq); i++) + ath10k_mac_txq_unref(ar, sta->txq[i]); + if (!sta->tdls) goto exit; @@ -5802,7 +6518,13 @@ arg.dwell_time_passive = scan_time_msec; arg.max_scan_time = scan_time_msec; arg.scan_ctrl_flags |= WMI_SCAN_FLAG_PASSIVE; + if (QCA_REV_WCN3990(ar)) { + arg.scan_ctrl_flags &= ~(WMI_SCAN_FILTER_PROBE_REQ | + WMI_SCAN_CHAN_STAT_EVENT | + WMI_SCAN_ADD_BCAST_PROBE_REQ); + } else { arg.scan_ctrl_flags |= WMI_SCAN_FILTER_PROBE_REQ; + } arg.burst_duration_ms = duration; ret = ath10k_start_scan(ar, &arg); @@ -5966,6 +6688,39 @@ mutex_unlock(&ar->conf_mutex); } +static void +ath10k_mac_update_bss_chan_survey(struct ath10k *ar, + struct ieee80211_channel *channel) +{ + int ret; + enum wmi_bss_survey_req_type type = WMI_BSS_SURVEY_REQ_TYPE_READ_CLEAR; + + lockdep_assert_held(&ar->conf_mutex); + + if (!test_bit(WMI_SERVICE_BSS_CHANNEL_INFO_64, ar->wmi.svc_map) || + (ar->rx_channel != channel)) + return; + + if (ar->scan.state != ATH10K_SCAN_IDLE) { + ath10k_dbg(ar, ATH10K_DBG_MAC, "ignoring bss chan info request while scanning..\n"); + return; + } + + reinit_completion(&ar->bss_survey_done); + + ret = ath10k_wmi_pdev_bss_chan_info_request(ar, type); + if (ret) { + ath10k_warn(ar, "failed to send pdev bss chan info request\n"); + return; + } + + ret = wait_for_completion_timeout(&ar->bss_survey_done, 3 * HZ); + if (!ret) { + ath10k_warn(ar, "bss channel survey timed out\n"); + return; + } +} + static int ath10k_get_survey(struct ieee80211_hw *hw, int idx, struct survey_info *survey) { @@ -5990,6 +6745,9 @@ goto exit; } + if (!QCA_REV_WCN3990(ar)) + ath10k_mac_update_bss_chan_survey(ar, &sband->channels[idx]); + spin_lock_bh(&ar->data_lock); memcpy(survey, ar_survey, sizeof(*survey)); spin_unlock_bh(&ar->data_lock); @@ -6378,6 +7136,32 @@ return 0; } +static void ath10k_set_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif, + u64 tsf) +{ + struct ath10k *ar = hw->priv; + struct ath10k_vif *arvif = ath10k_vif_to_arvif(vif); + u32 tsf_offset, vdev_param = ar->wmi.vdev_param->set_tsf; + int ret; + + /* Workaround: + * + * Given tsf argument is entire TSF value, but firmware accepts + * only TSF offset to current TSF. + * + * get_tsf function is used to get offset value, however since + * ath10k_get_tsf is not implemented properly, it will return 0 always. + * Luckily all the caller functions to set_tsf, as of now, also rely on + * get_tsf function to get entire tsf value such get_tsf() + tsf_delta, + * final tsf offset value to firmware will be arithmetically correct. + */ + tsf_offset = tsf - ath10k_get_tsf(hw, vif); + ret = ath10k_wmi_vdev_set_param(ar, arvif->vdev_id, + vdev_param, tsf_offset); + if (ret && ret != -EOPNOTSUPP) + ath10k_warn(ar, "failed to set tsf offset: %d\n", ret); +} + static int ath10k_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif, struct ieee80211_ampdu_params *params) @@ -6496,7 +7280,19 @@ if (WARN_ON(!arvif->is_up)) continue; + if (QCA_REV_WCN3990(ar)) { + /* In the case of wcn3990 WLAN module we send + * vdev restart only, no need to send vdev down. + */ + ret = ath10k_vdev_restart(arvif, &vifs[i].new_ctx->def); + if (ret) { + ath10k_warn(ar, + "failed to restart vdev %d: %d\n", + arvif->vdev_id, ret); + continue; + } + } else { ret = ath10k_wmi_vdev_down(ar, arvif->vdev_id); if (ret) { ath10k_warn(ar, "failed to down vdev %d: %d\n", @@ -6504,6 +7300,7 @@ continue; } } + } /* All relevant vdevs are downed and associated channel resources * should be available for the channel switch now. @@ -6532,12 +7329,18 @@ ath10k_warn(ar, "failed to update prb tmpl during csa: %d\n", ret); + if (!QCA_REV_WCN3990(ar)) { + /* In case of other than wcn3990 WLAN module we + * send vdev down and vdev restart to the firmware. + */ + ret = ath10k_vdev_restart(arvif, &vifs[i].new_ctx->def); if (ret) { ath10k_warn(ar, "failed to restart vdev %d: %d\n", arvif->vdev_id, ret); continue; } + } ret = ath10k_wmi_vdev_up(arvif->ar, arvif->vdev_id, arvif->aid, arvif->bssid); @@ -6558,7 +7361,7 @@ struct ath10k *ar = hw->priv; ath10k_dbg(ar, ATH10K_DBG_MAC, - "mac chanctx add freq %hu width %d ptr %p\n", + "mac chanctx add freq %hu width %d ptr %pK\n", ctx->def.chan->center_freq, ctx->def.width, ctx); mutex_lock(&ar->conf_mutex); @@ -6582,7 +7385,7 @@ struct ath10k *ar = hw->priv; ath10k_dbg(ar, ATH10K_DBG_MAC, - "mac chanctx remove freq %hu width %d ptr %p\n", + "mac chanctx remove freq %hu width %d ptr %pK\n", ctx->def.chan->center_freq, ctx->def.width, ctx); mutex_lock(&ar->conf_mutex); @@ -6647,7 +7450,7 @@ mutex_lock(&ar->conf_mutex); ath10k_dbg(ar, ATH10K_DBG_MAC, - "mac chanctx change freq %hu width %d ptr %p changed %x\n", + "mac chanctx change freq %hu width %d ptr %pK changed %x\n", ctx->def.chan->center_freq, ctx->def.width, ctx, changed); /* This shouldn't really happen because channel switching should use @@ -6705,7 +7508,7 @@ mutex_lock(&ar->conf_mutex); ath10k_dbg(ar, ATH10K_DBG_MAC, - "mac chanctx assign ptr %p vdev_id %i\n", + "mac chanctx assign ptr %pK vdev_id %i\n", ctx, arvif->vdev_id); if (WARN_ON(arvif->is_started)) { @@ -6773,12 +7576,13 @@ mutex_lock(&ar->conf_mutex); ath10k_dbg(ar, ATH10K_DBG_MAC, - "mac chanctx unassign ptr %p vdev_id %i\n", + "mac chanctx unassign ptr %pK vdev_id %i\n", ctx, arvif->vdev_id); WARN_ON(!arvif->is_started); - - if (vif->type == NL80211_IFTYPE_MONITOR) { + if (vif->type == NL80211_IFTYPE_MONITOR || + (vif->type == NL80211_IFTYPE_STATION && + ar->sta_state < IEEE80211_STA_ASSOC)) { WARN_ON(!arvif->is_up); ret = ath10k_wmi_vdev_down(ar, arvif->vdev_id); @@ -6794,6 +7598,7 @@ ath10k_warn(ar, "failed to stop vdev %i: %d\n", arvif->vdev_id, ret); + ar->sta_state = IEEE80211_STA_NOTEXIST; arvif->is_started = false; mutex_unlock(&ar->conf_mutex); @@ -6819,16 +7624,19 @@ } static const struct ieee80211_ops ath10k_ops = { - .tx = ath10k_tx, + .tx = ath10k_mac_op_tx, + .wake_tx_queue = ath10k_mac_op_wake_tx_queue, .start = ath10k_start, .stop = ath10k_stop, .config = ath10k_config, .add_interface = ath10k_add_interface, + .change_interface = ath10k_change_interface, .remove_interface = ath10k_remove_interface, .configure_filter = ath10k_configure_filter, .bss_info_changed = ath10k_bss_info_changed, .hw_scan = ath10k_hw_scan, .cancel_hw_scan = ath10k_cancel_hw_scan, + .set_rekey_data = ath10k_set_rekey_data, .set_key = ath10k_set_key, .set_default_unicast_key = ath10k_set_default_unicast_key, .sta_state = ath10k_sta_state, @@ -6846,6 +7654,7 @@ .set_bitrate_mask = ath10k_mac_op_set_bitrate_mask, .sta_rc_update = ath10k_sta_rc_update, .get_tsf = ath10k_get_tsf, + .set_tsf = ath10k_set_tsf, .ampdu_action = ath10k_ampdu_action, .get_et_sset_count = ath10k_debug_get_et_sset_count, .get_et_stats = ath10k_debug_get_et_stats, @@ -6862,9 +7671,11 @@ #ifdef CONFIG_PM .suspend = ath10k_wow_op_suspend, .resume = ath10k_wow_op_resume, + .set_wakeup = ath10k_wow_op_set_wakeup, #endif #ifdef CONFIG_MAC80211_DEBUGFS .sta_add_debugfs = ath10k_sta_add_debugfs, + .sta_statistics = ath10k_sta_statistics, #endif }; @@ -6934,21 +7745,32 @@ struct ath10k *ath10k_mac_create(size_t priv_size) { struct ieee80211_hw *hw; + struct ieee80211_ops *ops; struct ath10k *ar; - hw = ieee80211_alloc_hw(sizeof(struct ath10k) + priv_size, &ath10k_ops); - if (!hw) + ops = kmemdup(&ath10k_ops, sizeof(ath10k_ops), GFP_KERNEL); + if (!ops) return NULL; + hw = ieee80211_alloc_hw(sizeof(struct ath10k) + priv_size, ops); + if (!hw) { + kfree(ops); + return NULL; + } + ar = hw->priv; ar->hw = hw; + ar->ops = ops; return ar; } void ath10k_mac_destroy(struct ath10k *ar) { + struct ieee80211_ops *ops = ar->ops; + ieee80211_free_hw(ar->hw); + kfree(ops); } static const struct ieee80211_iface_limit ath10k_if_limits[] = { @@ -6982,6 +7804,10 @@ | BIT(NL80211_IFTYPE_MESH_POINT) #endif }, + { + .max = 1, + .types = BIT(NL80211_IFTYPE_STATION) + }, }; static const struct ieee80211_iface_combination ath10k_if_comb[] = { @@ -7103,6 +7929,85 @@ }, }; +static const struct ieee80211_iface_limit ath10k_wcn3990_if_limit[] = { + { + .max = 2, + .types = BIT(NL80211_IFTYPE_STATION), + }, + { + .max = 2, + .types = BIT(NL80211_IFTYPE_AP) | +#ifdef CONFIG_MAC80211_MESH + BIT(NL80211_IFTYPE_MESH_POINT) | +#endif + BIT(NL80211_IFTYPE_P2P_CLIENT) | + BIT(NL80211_IFTYPE_P2P_GO), + }, +}; + +static const struct ieee80211_iface_limit ath10k_wcn3990_qcs_if_limit[] = { + { + .max = 2, + .types = BIT(NL80211_IFTYPE_STATION), + }, + { + .max = 2, + .types = BIT(NL80211_IFTYPE_P2P_CLIENT), + }, + { + .max = 1, + .types = BIT(NL80211_IFTYPE_AP) | +#ifdef CONFIG_MAC80211_MESH + BIT(NL80211_IFTYPE_MESH_POINT) | +#endif + BIT(NL80211_IFTYPE_P2P_GO), + }, +}; + +static const struct ieee80211_iface_limit ath10k_wcn3990_if_limit_ibss[] = { + { + .max = 1, + .types = BIT(NL80211_IFTYPE_STATION), + }, + { + .max = 1, + .types = BIT(NL80211_IFTYPE_ADHOC), + }, +}; + +static struct ieee80211_iface_combination ath10k_wcn3990_qcs_if_comb[] = { + { + .limits = ath10k_wcn3990_if_limit, + .num_different_channels = 1, + .max_interfaces = 4, + .n_limits = ARRAY_SIZE(ath10k_wcn3990_if_limit), +#ifdef CONFIG_ATH10K_DFS_CERTIFIED + .radar_detect_widths = BIT(NL80211_CHAN_WIDTH_20_NOHT) | + BIT(NL80211_CHAN_WIDTH_20) | + BIT(NL80211_CHAN_WIDTH_40) | + BIT(NL80211_CHAN_WIDTH_80), +#endif + }, + { + .limits = ath10k_wcn3990_qcs_if_limit, + .num_different_channels = 2, + .max_interfaces = 4, + .n_limits = ARRAY_SIZE(ath10k_wcn3990_qcs_if_limit), + }, + { + .limits = ath10k_wcn3990_if_limit_ibss, + .num_different_channels = 1, + .max_interfaces = 2, + .n_limits = ARRAY_SIZE(ath10k_wcn3990_if_limit_ibss), +#ifdef CONFIG_ATH10K_DFS_CERTIFIED + .radar_detect_widths = BIT(NL80211_CHAN_WIDTH_20_NOHT) | + BIT(NL80211_CHAN_WIDTH_20) | + BIT(NL80211_CHAN_WIDTH_40) | + BIT(NL80211_CHAN_WIDTH_80), +#endif + }, +}; + static const struct ieee80211_iface_limit ath10k_10_4_if_limits[] = { { .max = 1, @@ -7176,7 +8081,11 @@ struct ieee80211_supported_band *band; void *channels; int ret; + u8 base_mac[ETH_ALEN]; + if (mac_pton(base_mac_addr, base_mac) && !is_zero_ether_addr(base_mac)) + SET_IEEE80211_PERM_ADDR(ar->hw, base_mac); + else SET_IEEE80211_PERM_ADDR(ar->hw, ar->mac_addr); SET_IEEE80211_DEV(ar->hw, ar->dev); @@ -7197,8 +8106,14 @@ band = &ar->mac.sbands[IEEE80211_BAND_2GHZ]; band->n_channels = ARRAY_SIZE(ath10k_2ghz_channels); band->channels = channels; + + if (ar->hw_params.cck_rate_map_rev2) { + band->n_bitrates = ath10k_g_rates_rev2_size; + band->bitrates = ath10k_g_rates_rev2; + } else { band->n_bitrates = ath10k_g_rates_size; band->bitrates = ath10k_g_rates; + } ar->hw->wiphy->bands[IEEE80211_BAND_2GHZ] = band; } @@ -7230,12 +8145,16 @@ ar->hw->wiphy->available_antennas_rx = ar->cfg_rx_chainmask; ar->hw->wiphy->available_antennas_tx = ar->cfg_tx_chainmask; - if (!test_bit(ATH10K_FW_FEATURE_NO_P2P, ar->fw_features)) + if (!test_bit(ATH10K_FW_FEATURE_NO_P2P, ar->normal_mode_fw.fw_file.fw_features)) ar->hw->wiphy->interface_modes |= BIT(NL80211_IFTYPE_P2P_DEVICE) | BIT(NL80211_IFTYPE_P2P_CLIENT) | BIT(NL80211_IFTYPE_P2P_GO); + if (QCA_REV_WCN3990(ar)) + ar->hw->wiphy->interface_modes &= + ~BIT(NL80211_IFTYPE_P2P_DEVICE); + ieee80211_hw_set(ar->hw, SIGNAL_DBM); ieee80211_hw_set(ar->hw, SUPPORTS_PS); ieee80211_hw_set(ar->hw, SUPPORTS_DYNAMIC_PS); @@ -7270,6 +8189,7 @@ ar->hw->vif_data_size = sizeof(struct ath10k_vif); ar->hw->sta_data_size = sizeof(struct ath10k_sta); + ar->hw->txq_data_size = sizeof(struct ath10k_txq); ar->hw->max_listen_interval = ATH10K_MAX_HW_LISTEN_INTERVAL; @@ -7294,7 +8214,8 @@ ar->hw->wiphy->max_remain_on_channel_duration = 5000; ar->hw->wiphy->flags |= WIPHY_FLAG_AP_UAPSD; - ar->hw->wiphy->features |= NL80211_FEATURE_AP_MODE_CHAN_WIDTH_CHANGE; + ar->hw->wiphy->features |= NL80211_FEATURE_AP_MODE_CHAN_WIDTH_CHANGE | + NL80211_FEATURE_AP_SCAN; ar->hw->wiphy->max_ap_assoc_sta = ar->max_num_stations; @@ -7318,7 +8239,7 @@ */ ar->hw->offchannel_tx_hw_queue = IEEE80211_MAX_QUEUES - 1; - switch (ar->wmi.op_version) { + switch (ar->running_fw->fw_file.wmi_op_version) { case ATH10K_FW_WMI_OP_VERSION_MAIN: ar->hw->wiphy->iface_combinations = ath10k_if_comb; ar->hw->wiphy->n_iface_combinations = @@ -7326,6 +8247,14 @@ ar->hw->wiphy->interface_modes |= BIT(NL80211_IFTYPE_ADHOC); break; case ATH10K_FW_WMI_OP_VERSION_TLV: + ar->hw->wiphy->interface_modes |= BIT(NL80211_IFTYPE_ADHOC); + if (QCA_REV_WCN3990(ar)) { + ar->hw->wiphy->iface_combinations = + ath10k_wcn3990_qcs_if_comb; + ar->hw->wiphy->n_iface_combinations = + ARRAY_SIZE(ath10k_wcn3990_qcs_if_comb); + break; + } if (test_bit(WMI_SERVICE_ADAPTIVE_OCS, ar->wmi.svc_map)) { ar->hw->wiphy->iface_combinations = ath10k_tlv_qcs_if_comb; @@ -7336,7 +8265,6 @@ ar->hw->wiphy->n_iface_combinations = ARRAY_SIZE(ath10k_tlv_if_comb); } - ar->hw->wiphy->interface_modes |= BIT(NL80211_IFTYPE_ADHOC); break; case ATH10K_FW_WMI_OP_VERSION_10_1: case ATH10K_FW_WMI_OP_VERSION_10_2: @@ -7360,7 +8288,7 @@ if (!test_bit(ATH10K_FLAG_RAW_MODE, &ar->dev_flags)) ar->hw->netdev_features = NETIF_F_HW_CSUM; - if (config_enabled(CONFIG_ATH10K_DFS_CERTIFIED)) { + if (IS_ENABLED(CONFIG_ATH10K_DFS_CERTIFIED)) { /* Init ath dfs pattern detector */ ar->ath_common.debug_mask = ATH_DBG_DFS; ar->dfs_detector = dfs_pattern_detector_init(&ar->ath_common, @@ -7370,6 +8298,15 @@ ath10k_warn(ar, "failed to initialise DFS pattern detector\n"); } + /* Current wake_tx_queue implementation imposes a significant + * performance penalty in some setups. The tx scheduling code needs + * more work anyway so disable the wake_tx_queue unless firmware + * supports the pull-push mechanism. + */ + if (!test_bit(ATH10K_FW_FEATURE_PEER_FLOW_CONTROL, + ar->running_fw->fw_file.fw_features)) + ar->ops->wake_tx_queue = NULL; + ret = ath_regd_init(&ar->ath_common.regulatory, ar->hw->wiphy, ath10k_reg_notifier); if (ret) { @@ -7399,7 +8336,7 @@ ieee80211_unregister_hw(ar->hw); err_dfs_detector_exit: - if (config_enabled(CONFIG_ATH10K_DFS_CERTIFIED) && ar->dfs_detector) + if (IS_ENABLED(CONFIG_ATH10K_DFS_CERTIFIED) && ar->dfs_detector) ar->dfs_detector->exit(ar->dfs_detector); err_free: @@ -7412,9 +8349,10 @@ void ath10k_mac_unregister(struct ath10k *ar) { + ath10k_wow_deinit(ar); ieee80211_unregister_hw(ar->hw); - if (config_enabled(CONFIG_ATH10K_DFS_CERTIFIED) && ar->dfs_detector) + if (IS_ENABLED(CONFIG_ATH10K_DFS_CERTIFIED) && ar->dfs_detector) ar->dfs_detector->exit(ar->dfs_detector); kfree(ar->mac.sbands[IEEE80211_BAND_2GHZ].channels); diff -ruw linux-4.4.115/drivers/net/wireless/ath/ath10k/mac.h linux-4.4.115-fbx/drivers/net/wireless/ath/ath10k/mac.h --- linux-4.4.115/drivers/net/wireless/ath/ath10k/mac.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/net/wireless/ath/ath10k/mac.h 2019-01-22 16:16:25.419263757 +0100 @@ -66,7 +66,7 @@ enum wmi_tlv_tx_pause_action action); u8 ath10k_mac_hw_rate_to_idx(const struct ieee80211_supported_band *sband, - u8 hw_rate); + u8 hw_rate, bool cck); u8 ath10k_mac_bitrate_to_idx(const struct ieee80211_supported_band *sband, u32 bitrate); @@ -74,6 +74,14 @@ void ath10k_mac_tx_unlock(struct ath10k *ar, int reason); void ath10k_mac_vif_tx_lock(struct ath10k_vif *arvif, int reason); void ath10k_mac_vif_tx_unlock(struct ath10k_vif *arvif, int reason); +bool ath10k_mac_tx_frm_has_freq(struct ath10k *ar); +void ath10k_mac_tx_push_pending(struct ath10k *ar); +int ath10k_mac_tx_push_txq(struct ieee80211_hw *hw, + struct ieee80211_txq *txq); +struct ieee80211_txq *ath10k_mac_txq_lookup(struct ath10k *ar, + u16 peer_id, + u8 tid); +int ath10k_mac_ext_resource_config(struct ath10k *ar, u32 val); static inline struct ath10k_vif *ath10k_vif_to_arvif(struct ieee80211_vif *vif) { diff -ruw linux-4.4.115/drivers/net/wireless/ath/ath10k/Makefile linux-4.4.115-fbx/drivers/net/wireless/ath/ath10k/Makefile --- linux-4.4.115/drivers/net/wireless/ath/ath10k/Makefile 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/net/wireless/ath/ath10k/Makefile 2019-01-22 16:16:25.411263685 +0100 @@ -24,6 +24,13 @@ obj-$(CONFIG_ATH10K_PCI) += ath10k_pci.o ath10k_pci-y += pci.o \ ce.o +obj-$(CONFIG_ATH10K_TARGET_SNOC) += ath10k_snoc.o +ath10k_snoc-y += snoc.o \ + qmi.o \ + wcn3990_qmi_service_v01.o \ + ce.o + +ath10k_pci-$(CONFIG_ATH10K_AHB) += ahb.o # for tracing framework to find trace.h CFLAGS_trace.o := -I$(src) diff -ruw linux-4.4.115/drivers/net/wireless/ath/ath10k/pci.h linux-4.4.115-fbx/drivers/net/wireless/ath/ath10k/pci.h --- linux-4.4.115/drivers/net/wireless/ath/ath10k/pci.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/net/wireless/ath/ath10k/pci.h 2019-01-22 16:16:25.423263793 +0100 @@ -22,6 +22,7 @@ #include "hw.h" #include "ce.h" +#include "ahb.h" /* * maximum number of bytes that can be handled atomically by DiagRead/DiagWrite @@ -147,9 +148,6 @@ /* protects compl_free and num_send_allowed */ spinlock_t pipe_lock; - - struct ath10k_pci *ar_pci; - struct tasklet_struct intr; }; struct ath10k_pci_supp_chip { @@ -157,32 +155,28 @@ u32 rev_id; }; +enum ath10k_pci_irq_mode { + ATH10K_PCI_IRQ_AUTO = 0, + ATH10K_PCI_IRQ_LEGACY = 1, + ATH10K_PCI_IRQ_MSI = 2, +}; + struct ath10k_pci { + struct bus_opaque opaque_ctx; struct pci_dev *pdev; struct device *dev; struct ath10k *ar; void __iomem *mem; size_t mem_len; - /* - * Number of MSI interrupts granted, 0 --> using legacy PCI line - * interrupts. - */ - int num_msi_intrs; - - struct tasklet_struct intr_tq; - struct tasklet_struct msi_fw_err; + /* Operating interrupt mode */ + enum ath10k_pci_irq_mode oper_irq_mode; struct ath10k_pci_pipe pipe_info[CE_COUNT_MAX]; /* Copy Engine used for Diagnostic Accesses */ struct ath10k_ce_pipe *ce_diag; - /* FIXME: document what this really protects */ - spinlock_t ce_lock; - - /* Map CE id to ce_state */ - struct ath10k_ce_pipe ce_states[CE_COUNT_MAX]; struct timer_list rx_post_retry; /* Due to HW quirks it is recommended to disable ASPM during device @@ -225,6 +219,18 @@ * on MMIO read/write. */ bool pci_ps; + + /* Chip specific pci reset routine used to do a safe reset */ + int (*pci_soft_reset)(struct ath10k *ar); + + /* Chip specific pci full reset function */ + int (*pci_hard_reset)(struct ath10k *ar); + + /* Keep this entry in the last, memory for struct ath10k_ahb is + * allocated (ahb support enabled case) in the continuation of + * this struct. + */ + struct ath10k_ahb ahb[0]; }; static inline struct ath10k_pci *ath10k_pci_priv(struct ath10k *ar) @@ -253,6 +259,40 @@ u32 ath10k_pci_soc_read32(struct ath10k *ar, u32 addr); u32 ath10k_pci_reg_read32(struct ath10k *ar, u32 addr); +int ath10k_pci_hif_tx_sg(struct ath10k *ar, u8 pipe_id, + struct ath10k_hif_sg_item *items, int n_items); +int ath10k_pci_hif_diag_read(struct ath10k *ar, u32 address, void *buf, + size_t buf_len); +int ath10k_pci_diag_write_mem(struct ath10k *ar, u32 address, + const void *data, int nbytes); +int ath10k_pci_hif_exchange_bmi_msg(struct ath10k *ar, void *req, u32 req_len, + void *resp, u32 *resp_len); +int ath10k_pci_hif_map_service_to_pipe(struct ath10k *ar, u16 service_id, + u8 *ul_pipe, u8 *dl_pipe); +void ath10k_pci_hif_get_default_pipe(struct ath10k *ar, u8 *ul_pipe, + u8 *dl_pipe); +void ath10k_pci_hif_send_complete_check(struct ath10k *ar, u8 pipe, + int force); +u16 ath10k_pci_hif_get_free_queue_number(struct ath10k *ar, u8 pipe); +void ath10k_pci_hif_power_down(struct ath10k *ar); +int ath10k_pci_alloc_pipes(struct ath10k *ar); +void ath10k_pci_free_pipes(struct ath10k *ar); +void ath10k_pci_free_pipes(struct ath10k *ar); +void ath10k_pci_rx_replenish_retry(unsigned long ptr); +void ath10k_pci_ce_deinit(struct ath10k *ar); +void ath10k_pci_init_napi(struct ath10k *ar); +int ath10k_pci_init_pipes(struct ath10k *ar); +int ath10k_pci_init_config(struct ath10k *ar); +void ath10k_pci_rx_post(struct ath10k *ar); +void ath10k_pci_flush(struct ath10k *ar); +void ath10k_pci_enable_legacy_irq(struct ath10k *ar); +bool ath10k_pci_irq_pending(struct ath10k *ar); +void ath10k_pci_disable_and_clear_legacy_irq(struct ath10k *ar); +void ath10k_pci_irq_msi_fw_mask(struct ath10k *ar); +int ath10k_pci_wait_for_target_init(struct ath10k *ar); +int ath10k_pci_setup_resource(struct ath10k *ar); +void ath10k_pci_release_resource(struct ath10k *ar); + /* QCA6174 is known to have Tx/Rx issues when SOC_WAKE register is poked too * frequently. To avoid this put SoC to sleep after a very conservative grace * period. Adjust with great care. diff -ruw linux-4.4.115/drivers/net/wireless/ath/ath10k/rx_desc.h linux-4.4.115-fbx/drivers/net/wireless/ath/ath10k/rx_desc.h --- linux-4.4.115/drivers/net/wireless/ath/ath10k/rx_desc.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/net/wireless/ath/ath10k/rx_desc.h 2019-10-29 09:26:24.461211183 +0100 @@ -205,12 +205,25 @@ * descriptor. */ +#ifndef CONFIG_ATH10K_SNOC struct rx_frag_info { u8 ring0_more_count; u8 ring1_more_count; u8 ring2_more_count; u8 ring3_more_count; } __packed; +#else +struct rx_frag_info { + u8 ring0_more_count; + u8 ring1_more_count; + u8 ring2_more_count; + u8 ring3_more_count; + u8 ring4_more_count; + u8 ring5_more_count; + u8 ring6_more_count; + u8 ring7_more_count; +} __packed; +#endif /* * ring0_more_count @@ -465,11 +478,23 @@ __le32 info2; /* %RX_MSDU_START_INFO2_ */ } __packed; +#ifdef CONFIG_ATH10K_SNOC +struct rx_msdu_start_wcn3990 { + __le32 info3; +} __packed; +#else +struct rx_msdu_start_wcn3990 { +} __packed; +#endif + struct rx_msdu_start { struct rx_msdu_start_common common; union { struct rx_msdu_start_qca99x0 qca99x0; } __packed; + union { + struct rx_msdu_start_wcn3990 wcn3990; + } __packed; } __packed; /* @@ -589,11 +614,21 @@ __le32 info2; } __packed; +struct rx_msdu_end_wcn3990 { + __le32 rule_indication_0; + __le32 rule_indication_1; + __le32 rule_indication_2; + __le32 rule_indication_3; +} __packed; + struct rx_msdu_end { struct rx_msdu_end_common common; union { struct rx_msdu_end_qca99x0 qca99x0; } __packed; +#ifdef CONFIG_ATH10K_SNOC + struct rx_msdu_end_wcn3990 wcn3990; +#endif } __packed; /* @@ -656,26 +691,6 @@ * Reserved: HW should fill with zero. FW should ignore. */ -#define RX_PPDU_START_SIG_RATE_SELECT_OFDM 0 -#define RX_PPDU_START_SIG_RATE_SELECT_CCK 1 - -#define RX_PPDU_START_SIG_RATE_OFDM_48 0 -#define RX_PPDU_START_SIG_RATE_OFDM_24 1 -#define RX_PPDU_START_SIG_RATE_OFDM_12 2 -#define RX_PPDU_START_SIG_RATE_OFDM_6 3 -#define RX_PPDU_START_SIG_RATE_OFDM_54 4 -#define RX_PPDU_START_SIG_RATE_OFDM_36 5 -#define RX_PPDU_START_SIG_RATE_OFDM_18 6 -#define RX_PPDU_START_SIG_RATE_OFDM_9 7 - -#define RX_PPDU_START_SIG_RATE_CCK_LP_11 0 -#define RX_PPDU_START_SIG_RATE_CCK_LP_5_5 1 -#define RX_PPDU_START_SIG_RATE_CCK_LP_2 2 -#define RX_PPDU_START_SIG_RATE_CCK_LP_1 3 -#define RX_PPDU_START_SIG_RATE_CCK_SP_11 4 -#define RX_PPDU_START_SIG_RATE_CCK_SP_5_5 5 -#define RX_PPDU_START_SIG_RATE_CCK_SP_2 6 - #define HTT_RX_PPDU_START_PREAMBLE_LEGACY 0x04 #define HTT_RX_PPDU_START_PREAMBLE_HT 0x08 #define HTT_RX_PPDU_START_PREAMBLE_HT_WITH_TXBF 0x09 @@ -711,25 +726,6 @@ /* No idea what this flag means. It seems to be always set in rate. */ #define RX_PPDU_START_RATE_FLAG BIT(3) -enum rx_ppdu_start_rate { - RX_PPDU_START_RATE_OFDM_48M = RX_PPDU_START_RATE_FLAG | ATH10K_HW_RATE_OFDM_48M, - RX_PPDU_START_RATE_OFDM_24M = RX_PPDU_START_RATE_FLAG | ATH10K_HW_RATE_OFDM_24M, - RX_PPDU_START_RATE_OFDM_12M = RX_PPDU_START_RATE_FLAG | ATH10K_HW_RATE_OFDM_12M, - RX_PPDU_START_RATE_OFDM_6M = RX_PPDU_START_RATE_FLAG | ATH10K_HW_RATE_OFDM_6M, - RX_PPDU_START_RATE_OFDM_54M = RX_PPDU_START_RATE_FLAG | ATH10K_HW_RATE_OFDM_54M, - RX_PPDU_START_RATE_OFDM_36M = RX_PPDU_START_RATE_FLAG | ATH10K_HW_RATE_OFDM_36M, - RX_PPDU_START_RATE_OFDM_18M = RX_PPDU_START_RATE_FLAG | ATH10K_HW_RATE_OFDM_18M, - RX_PPDU_START_RATE_OFDM_9M = RX_PPDU_START_RATE_FLAG | ATH10K_HW_RATE_OFDM_9M, - - RX_PPDU_START_RATE_CCK_LP_11M = RX_PPDU_START_RATE_FLAG | ATH10K_HW_RATE_CCK_LP_11M, - RX_PPDU_START_RATE_CCK_LP_5_5M = RX_PPDU_START_RATE_FLAG | ATH10K_HW_RATE_CCK_LP_5_5M, - RX_PPDU_START_RATE_CCK_LP_2M = RX_PPDU_START_RATE_FLAG | ATH10K_HW_RATE_CCK_LP_2M, - RX_PPDU_START_RATE_CCK_LP_1M = RX_PPDU_START_RATE_FLAG | ATH10K_HW_RATE_CCK_LP_1M, - RX_PPDU_START_RATE_CCK_SP_11M = RX_PPDU_START_RATE_FLAG | ATH10K_HW_RATE_CCK_SP_11M, - RX_PPDU_START_RATE_CCK_SP_5_5M = RX_PPDU_START_RATE_FLAG | ATH10K_HW_RATE_CCK_SP_5_5M, - RX_PPDU_START_RATE_CCK_SP_2M = RX_PPDU_START_RATE_FLAG | ATH10K_HW_RATE_CCK_SP_2M, -}; - struct rx_ppdu_start { struct { u8 pri20_mhz; @@ -992,9 +988,51 @@ struct rx_pkt_end { __le32 info0; /* %RX_PKT_END_INFO0_ */ +#ifndef CONFIG_ATH10K_SNOC __le32 phy_timestamp_1; __le32 phy_timestamp_2; - __le32 rx_location_info; /* %RX_LOCATION_INFO_ */ +#else + __le64 phy_timestamp_1; + __le64 phy_timestamp_2; +#endif +} __packed; + +#define RX_LOCATION_INFO0_RTT_FAC_LEGACY_MASK 0x00003fff +#define RX_LOCATION_INFO0_RTT_FAC_LEGACY_LSB 0 +#define RX_LOCATION_INFO0_RTT_FAC_VHT_MASK 0x1fff8000 +#define RX_LOCATION_INFO0_RTT_FAC_VHT_LSB 15 +#define RX_LOCATION_INFO0_RTT_STRONGEST_CHAIN_MASK 0xc0000000 +#define RX_LOCATION_INFO0_RTT_STRONGEST_CHAIN_LSB 30 +#define RX_LOCATION_INFO0_RTT_FAC_LEGACY_STATUS BIT(14) +#define RX_LOCATION_INFO0_RTT_FAC_VHT_STATUS BIT(29) + +#define RX_LOCATION_INFO1_RTT_PREAMBLE_TYPE_MASK 0x0000000c +#define RX_LOCATION_INFO1_RTT_PREAMBLE_TYPE_LSB 2 +#define RX_LOCATION_INFO1_PKT_BW_MASK 0x00000030 +#define RX_LOCATION_INFO1_PKT_BW_LSB 4 +#define RX_LOCATION_INFO1_SKIP_P_SKIP_BTCF_MASK 0x0000ff00 +#define RX_LOCATION_INFO1_SKIP_P_SKIP_BTCF_LSB 8 +#define RX_LOCATION_INFO1_RTT_MSC_RATE_MASK 0x000f0000 +#define RX_LOCATION_INFO1_RTT_MSC_RATE_LSB 16 +#define RX_LOCATION_INFO1_RTT_PBD_LEG_BW_MASK 0x00300000 +#define RX_LOCATION_INFO1_RTT_PBD_LEG_BW_LSB 20 +#define RX_LOCATION_INFO1_TIMING_BACKOFF_MASK 0x07c00000 +#define RX_LOCATION_INFO1_TIMING_BACKOFF_LSB 22 +#define RX_LOCATION_INFO1_RTT_TX_FRAME_PHASE_MASK 0x18000000 +#define RX_LOCATION_INFO1_RTT_TX_FRAME_PHASE_LSB 27 +#define RX_LOCATION_INFO1_RTT_CFR_STATUS BIT(0) +#define RX_LOCATION_INFO1_RTT_CIR_STATUS BIT(1) +#define RX_LOCATION_INFO1_RTT_GI_TYPE BIT(7) +#define RX_LOCATION_INFO1_RTT_MAC_PHY_PHASE BIT(29) +#define RX_LOCATION_INFO1_RTT_TX_DATA_START_X_PHASE BIT(30) +#define RX_LOCATION_INFO1_RX_LOCATION_VALID BIT(31) + +struct rx_location_info { + __le32 rx_location_info0; /* %RX_LOCATION_INFO0_ */ + __le32 rx_location_info1; /* %RX_LOCATION_INFO1_ */ +#ifdef CONFIG_ATH10K_SNOC + __le32 rx_location_info2; /* %RX_LOCATION_INFO2_ */ +#endif } __packed; enum rx_phy_ppdu_end_info0 { @@ -1067,6 +1105,17 @@ struct rx_ppdu_end_qca99x0 { struct rx_pkt_end rx_pkt_end; + __le32 rx_location_info; /* %RX_LOCATION_INFO_ */ + struct rx_phy_ppdu_end rx_phy_ppdu_end; + __le32 rx_timing_offset; /* %RX_PPDU_END_RX_TIMING_OFFSET_ */ + __le32 rx_info; /* %RX_PPDU_END_RX_INFO_ */ + __le16 bb_length; + __le16 info1; /* %RX_PPDU_END_INFO1_ */ +} __packed; + +struct rx_ppdu_end_qca9984 { + struct rx_pkt_end rx_pkt_end; + struct rx_location_info rx_location_info; struct rx_phy_ppdu_end rx_phy_ppdu_end; __le32 rx_timing_offset; /* %RX_PPDU_END_RX_TIMING_OFFSET_ */ __le32 rx_info; /* %RX_PPDU_END_RX_INFO_ */ @@ -1074,12 +1123,34 @@ __le16 info1; /* %RX_PPDU_END_INFO1_ */ } __packed; +struct rx_timing_offset { + __le32 timing_offset; +}; + +struct rx_ppdu_end_wcn3990 { + __le32 reserved_info_0; + __le32 reserved_info_1; + __le32 rx_antenna_info; + __le32 rx_coex_info; + __le32 rx_mpdu_cnt_info; + __le32 rx_bb_length; + __le64 phy_timestamp_tx; + struct rx_pkt_end rx_pkt_end; + struct rx_phy_ppdu_end rx_phy_ppdu_end; + struct rx_timing_offset rx_timing_offset; + struct rx_location_info rx_location_info; +} __packed; + struct rx_ppdu_end { struct rx_ppdu_end_common common; union { struct rx_ppdu_end_qca988x qca988x; struct rx_ppdu_end_qca6174 qca6174; struct rx_ppdu_end_qca99x0 qca99x0; + struct rx_ppdu_end_qca9984 qca9984; +#ifdef CONFIG_ATH10K_SNOC + struct rx_ppdu_end_wcn3990 wcn3990; +#endif } __packed; } __packed; diff -ruw linux-4.4.115/drivers/net/wireless/ath/ath10k/swap.c linux-4.4.115-fbx/drivers/net/wireless/ath/ath10k/swap.c --- linux-4.4.115/drivers/net/wireless/ath/ath10k/swap.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/net/wireless/ath/ath10k/swap.c 2019-01-22 16:16:25.423263793 +0100 @@ -135,26 +135,17 @@ } int ath10k_swap_code_seg_configure(struct ath10k *ar, - enum ath10k_swap_code_seg_bin_type type) + const struct ath10k_fw_file *fw_file) { int ret; struct ath10k_swap_code_seg_info *seg_info = NULL; - switch (type) { - case ATH10K_SWAP_CODE_SEG_BIN_TYPE_FW: - if (!ar->swap.firmware_swap_code_seg_info) + if (!fw_file->firmware_swap_code_seg_info) return 0; ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot found firmware code swap binary\n"); - seg_info = ar->swap.firmware_swap_code_seg_info; - break; - default: - case ATH10K_SWAP_CODE_SEG_BIN_TYPE_OTP: - case ATH10K_SWAP_CODE_SEG_BIN_TYPE_UTF: - ath10k_warn(ar, "ignoring unknown code swap binary type %d\n", - type); - return 0; - } + + seg_info = fw_file->firmware_swap_code_seg_info; ret = ath10k_bmi_write_memory(ar, seg_info->target_addr, &seg_info->seg_hw_info, @@ -168,32 +159,41 @@ return 0; } -void ath10k_swap_code_seg_release(struct ath10k *ar) +void ath10k_swap_code_seg_release(struct ath10k *ar, + struct ath10k_fw_file *fw_file) { - ath10k_swap_code_seg_free(ar, ar->swap.firmware_swap_code_seg_info); - ar->swap.firmware_codeswap_data = NULL; - ar->swap.firmware_codeswap_len = 0; - ar->swap.firmware_swap_code_seg_info = NULL; + ath10k_swap_code_seg_free(ar, fw_file->firmware_swap_code_seg_info); + + /* FIXME: these two assignments look to bein wrong place! Shouldn't + * they be in ath10k_core_free_firmware_files() like the rest? + */ + fw_file->codeswap_data = NULL; + fw_file->codeswap_len = 0; + + fw_file->firmware_swap_code_seg_info = NULL; } -int ath10k_swap_code_seg_init(struct ath10k *ar) +int ath10k_swap_code_seg_init(struct ath10k *ar, struct ath10k_fw_file *fw_file) { int ret; struct ath10k_swap_code_seg_info *seg_info; + const void *codeswap_data; + size_t codeswap_len; + + codeswap_data = fw_file->codeswap_data; + codeswap_len = fw_file->codeswap_len; - if (!ar->swap.firmware_codeswap_len || !ar->swap.firmware_codeswap_data) + if (!codeswap_len || !codeswap_data) return 0; - seg_info = ath10k_swap_code_seg_alloc(ar, - ar->swap.firmware_codeswap_len); + seg_info = ath10k_swap_code_seg_alloc(ar, codeswap_len); if (!seg_info) { ath10k_err(ar, "failed to allocate fw code swap segment\n"); return -ENOMEM; } ret = ath10k_swap_code_seg_fill(ar, seg_info, - ar->swap.firmware_codeswap_data, - ar->swap.firmware_codeswap_len); + codeswap_data, codeswap_len); if (ret) { ath10k_warn(ar, "failed to initialize fw code swap segment: %d\n", @@ -202,7 +202,7 @@ return ret; } - ar->swap.firmware_swap_code_seg_info = seg_info; + fw_file->firmware_swap_code_seg_info = seg_info; return 0; } diff -ruw linux-4.4.115/drivers/net/wireless/ath/ath10k/swap.h linux-4.4.115-fbx/drivers/net/wireless/ath/ath10k/swap.h --- linux-4.4.115/drivers/net/wireless/ath/ath10k/swap.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/net/wireless/ath/ath10k/swap.h 2019-01-22 16:16:25.423263793 +0100 @@ -23,6 +23,8 @@ /* Currently only one swap segment is supported */ #define ATH10K_SWAP_CODE_SEG_NUM_SUPPORTED 1 +struct ath10k_fw_file; + struct ath10k_swap_code_seg_tlv { __le32 address; __le32 length; @@ -39,12 +41,6 @@ struct ath10k_swap_code_seg_tail tail; } __packed; -enum ath10k_swap_code_seg_bin_type { - ATH10K_SWAP_CODE_SEG_BIN_TYPE_OTP, - ATH10K_SWAP_CODE_SEG_BIN_TYPE_FW, - ATH10K_SWAP_CODE_SEG_BIN_TYPE_UTF, -}; - struct ath10k_swap_code_seg_hw_info { /* Swap binary image size */ __le32 swap_size; @@ -65,8 +61,10 @@ }; int ath10k_swap_code_seg_configure(struct ath10k *ar, - enum ath10k_swap_code_seg_bin_type type); -void ath10k_swap_code_seg_release(struct ath10k *ar); -int ath10k_swap_code_seg_init(struct ath10k *ar); + const struct ath10k_fw_file *fw_file); +void ath10k_swap_code_seg_release(struct ath10k *ar, + struct ath10k_fw_file *fw_file); +int ath10k_swap_code_seg_init(struct ath10k *ar, + struct ath10k_fw_file *fw_file); #endif diff -ruw linux-4.4.115/drivers/net/wireless/ath/ath10k/targaddrs.h linux-4.4.115-fbx/drivers/net/wireless/ath/ath10k/targaddrs.h --- linux-4.4.115/drivers/net/wireless/ath/ath10k/targaddrs.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/net/wireless/ath/ath10k/targaddrs.h 2019-01-22 16:16:25.423263793 +0100 @@ -405,7 +405,7 @@ * 1. target firmware would check magic number and if it's a match, firmware * would consider the bits[0:15] are valid and base on that to calculate * the end of DRAM. Early allocation would be located at that area and - * may be reclaimed when necesary + * may be reclaimed when necessary * 2. if no magic number is found, early allocation would happen at "_end" * symbol of ROM which is located before the app-data and might NOT be * re-claimable. If this is adopted, link script should keep this in @@ -447,6 +447,9 @@ #define QCA988X_BOARD_DATA_SZ 7168 #define QCA988X_BOARD_EXT_DATA_SZ 0 +#define QCA9887_BOARD_DATA_SZ 7168 +#define QCA9887_BOARD_EXT_DATA_SZ 0 + #define QCA6174_BOARD_DATA_SZ 8192 #define QCA6174_BOARD_EXT_DATA_SZ 0 @@ -456,4 +459,7 @@ #define QCA99X0_BOARD_DATA_SZ 12288 #define QCA99X0_BOARD_EXT_DATA_SZ 0 +#define QCA4019_BOARD_DATA_SZ 12064 +#define QCA4019_BOARD_EXT_DATA_SZ 0 + #endif /* __TARGADDRS_H__ */ diff -ruw linux-4.4.115/drivers/net/wireless/ath/ath10k/testmode.c linux-4.4.115-fbx/drivers/net/wireless/ath/ath10k/testmode.c --- linux-4.4.115/drivers/net/wireless/ath/ath10k/testmode.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/net/wireless/ath/ath10k/testmode.c 2019-01-22 16:16:25.423263793 +0100 @@ -23,6 +23,7 @@ #include "wmi.h" #include "hif.h" #include "hw.h" +#include "core.h" #include "testmode_i.h" @@ -45,7 +46,7 @@ int ret; ath10k_dbg(ar, ATH10K_DBG_TESTMODE, - "testmode event wmi cmd_id %d skb %p skb->len %d\n", + "testmode event wmi cmd_id %d skb %pK skb->len %d\n", cmd_id, skb, skb->len); ath10k_dbg_dump(ar, ATH10K_DBG_TESTMODE, NULL, "", skb->data, skb->len); @@ -136,130 +137,18 @@ return ret; } - return cfg80211_testmode_reply(skb); -} - -static int ath10k_tm_fetch_utf_firmware_api_2(struct ath10k *ar) -{ - size_t len, magic_len, ie_len; - struct ath10k_fw_ie *hdr; - char filename[100]; - __le32 *version; - const u8 *data; - int ie_id, ret; - - snprintf(filename, sizeof(filename), "%s/%s", - ar->hw_params.fw.dir, ATH10K_FW_UTF_API2_FILE); - - /* load utf firmware image */ - ret = request_firmware(&ar->testmode.utf, filename, ar->dev); + ret = nla_put_u32(skb, ATH10K_TM_ATTR_WMI_OP_VERSION, + ar->normal_mode_fw.fw_file.wmi_op_version); if (ret) { - ath10k_warn(ar, "failed to retrieve utf firmware '%s': %d\n", - filename, ret); + kfree_skb(skb); return ret; } - data = ar->testmode.utf->data; - len = ar->testmode.utf->size; - - /* FIXME: call release_firmware() in error cases */ - - /* magic also includes the null byte, check that as well */ - magic_len = strlen(ATH10K_FIRMWARE_MAGIC) + 1; - - if (len < magic_len) { - ath10k_err(ar, "utf firmware file is too small to contain magic\n"); - ret = -EINVAL; - goto err; - } - - if (memcmp(data, ATH10K_FIRMWARE_MAGIC, magic_len) != 0) { - ath10k_err(ar, "invalid firmware magic\n"); - ret = -EINVAL; - goto err; - } - - /* jump over the padding */ - magic_len = ALIGN(magic_len, 4); - - len -= magic_len; - data += magic_len; - - /* loop elements */ - while (len > sizeof(struct ath10k_fw_ie)) { - hdr = (struct ath10k_fw_ie *)data; - - ie_id = le32_to_cpu(hdr->id); - ie_len = le32_to_cpu(hdr->len); - - len -= sizeof(*hdr); - data += sizeof(*hdr); - - if (len < ie_len) { - ath10k_err(ar, "invalid length for FW IE %d (%zu < %zu)\n", - ie_id, len, ie_len); - ret = -EINVAL; - goto err; - } - - switch (ie_id) { - case ATH10K_FW_IE_FW_VERSION: - if (ie_len > sizeof(ar->testmode.utf_version) - 1) - break; - - memcpy(ar->testmode.utf_version, data, ie_len); - ar->testmode.utf_version[ie_len] = '\0'; - - ath10k_dbg(ar, ATH10K_DBG_TESTMODE, - "testmode found fw utf version %s\n", - ar->testmode.utf_version); - break; - case ATH10K_FW_IE_TIMESTAMP: - /* ignore timestamp, but don't warn about it either */ - break; - case ATH10K_FW_IE_FW_IMAGE: - ath10k_dbg(ar, ATH10K_DBG_TESTMODE, - "testmode found fw image ie (%zd B)\n", - ie_len); - - ar->testmode.utf_firmware_data = data; - ar->testmode.utf_firmware_len = ie_len; - break; - case ATH10K_FW_IE_WMI_OP_VERSION: - if (ie_len != sizeof(u32)) - break; - version = (__le32 *)data; - ar->testmode.op_version = le32_to_cpup(version); - ath10k_dbg(ar, ATH10K_DBG_TESTMODE, "testmode found fw ie wmi op version %d\n", - ar->testmode.op_version); - break; - default: - ath10k_warn(ar, "Unknown testmode FW IE: %u\n", - le32_to_cpu(hdr->id)); - break; - } - /* jump over the padding */ - ie_len = ALIGN(ie_len, 4); - - len -= ie_len; - data += ie_len; - } - - if (!ar->testmode.utf_firmware_data || !ar->testmode.utf_firmware_len) { - ath10k_err(ar, "No ATH10K_FW_IE_FW_IMAGE found\n"); - ret = -EINVAL; - goto err; - } - - return 0; - -err: - release_firmware(ar->testmode.utf); - - return ret; + return cfg80211_testmode_reply(skb); } -static int ath10k_tm_fetch_utf_firmware_api_1(struct ath10k *ar) +static int ath10k_tm_fetch_utf_firmware_api_1(struct ath10k *ar, + struct ath10k_fw_file *fw_file) { char filename[100]; int ret; @@ -268,7 +157,7 @@ ar->hw_params.fw.dir, ATH10K_FW_UTF_FILE); /* load utf firmware image */ - ret = request_firmware(&ar->testmode.utf, filename, ar->dev); + ret = request_firmware(&fw_file->firmware, filename, ar->dev); if (ret) { ath10k_warn(ar, "failed to retrieve utf firmware '%s': %d\n", filename, ret); @@ -281,24 +170,34 @@ * correct WMI interface. */ - ar->testmode.op_version = ATH10K_FW_WMI_OP_VERSION_10_1; - ar->testmode.utf_firmware_data = ar->testmode.utf->data; - ar->testmode.utf_firmware_len = ar->testmode.utf->size; + fw_file->wmi_op_version = ATH10K_FW_WMI_OP_VERSION_10_1; + fw_file->htt_op_version = ATH10K_FW_HTT_OP_VERSION_10_1; + fw_file->firmware_data = fw_file->firmware->data; + fw_file->firmware_len = fw_file->firmware->size; return 0; } static int ath10k_tm_fetch_firmware(struct ath10k *ar) { + struct ath10k_fw_components *utf_mode_fw; + struct ath10k_fw_file *fw_file; int ret; - ret = ath10k_tm_fetch_utf_firmware_api_2(ar); + if (!ar->is_bmi) { + fw_file = &ar->testmode.utf_mode_fw.fw_file; + fw_file->wmi_op_version = ATH10K_FW_WMI_OP_VERSION_TLV; + fw_file->htt_op_version = ATH10K_FW_HTT_OP_VERSION_TLV; + return 0; + } + ret = ath10k_core_fetch_firmware_api_n(ar, ATH10K_FW_UTF_API2_FILE, + &ar->testmode.utf_mode_fw.fw_file); if (ret == 0) { ath10k_dbg(ar, ATH10K_DBG_TESTMODE, "testmode using fw utf api 2"); - return 0; + goto out; } - ret = ath10k_tm_fetch_utf_firmware_api_1(ar); + ret = ath10k_tm_fetch_utf_firmware_api_1(ar, &ar->testmode.utf_mode_fw.fw_file); if (ret) { ath10k_err(ar, "failed to fetch utf firmware binary: %d", ret); return ret; @@ -306,6 +205,21 @@ ath10k_dbg(ar, ATH10K_DBG_TESTMODE, "testmode using utf api 1"); +out: + utf_mode_fw = &ar->testmode.utf_mode_fw; + + /* Use the same board data file as the normal firmware uses (but + * it's still "owned" by normal_mode_fw so we shouldn't free it. + */ + utf_mode_fw->board_data = ar->normal_mode_fw.board_data; + utf_mode_fw->board_len = ar->normal_mode_fw.board_len; + + if (!utf_mode_fw->fw_file.otp_data) { + ath10k_info(ar, "utf.bin didn't contain otp binary, taking it from the normal mode firmware"); + utf_mode_fw->fw_file.otp_data = ar->normal_mode_fw.fw_file.otp_data; + utf_mode_fw->fw_file.otp_len = ar->normal_mode_fw.fw_file.otp_len; + } + return 0; } @@ -329,7 +243,7 @@ goto err; } - if (WARN_ON(ar->testmode.utf != NULL)) { + if (WARN_ON(ar->testmode.utf_mode_fw.fw_file.firmware != NULL)) { /* utf image is already downloaded, it shouldn't be */ ret = -EEXIST; goto err; @@ -341,30 +255,34 @@ goto err; } + if (ar->testmode.utf_mode_fw.fw_file.codeswap_data && + ar->testmode.utf_mode_fw.fw_file.codeswap_len) { + ret = ath10k_swap_code_seg_init(ar, + &ar->testmode.utf_mode_fw.fw_file); + if (ret) { + ath10k_warn(ar, + "failed to init utf code swap segment: %d\n", + ret); + goto err_release_utf_mode_fw; + } + } + spin_lock_bh(&ar->data_lock); ar->testmode.utf_monitor = true; spin_unlock_bh(&ar->data_lock); - BUILD_BUG_ON(sizeof(ar->fw_features) != - sizeof(ar->testmode.orig_fw_features)); - - memcpy(ar->testmode.orig_fw_features, ar->fw_features, - sizeof(ar->fw_features)); - ar->testmode.orig_wmi_op_version = ar->wmi.op_version; - memset(ar->fw_features, 0, sizeof(ar->fw_features)); - - ar->wmi.op_version = ar->testmode.op_version; ath10k_dbg(ar, ATH10K_DBG_TESTMODE, "testmode wmi version %d\n", - ar->wmi.op_version); + ar->testmode.utf_mode_fw.fw_file.wmi_op_version); ret = ath10k_hif_power_up(ar); if (ret) { ath10k_err(ar, "failed to power up hif (testmode): %d\n", ret); ar->state = ATH10K_STATE_OFF; - goto err_fw_features; + goto err_release_utf_mode_fw; } - ret = ath10k_core_start(ar, ATH10K_FIRMWARE_MODE_UTF); + ret = ath10k_core_start(ar, ATH10K_FIRMWARE_MODE_UTF, + &ar->testmode.utf_mode_fw); if (ret) { ath10k_err(ar, "failed to start core (testmode): %d\n", ret); ar->state = ATH10K_STATE_OFF; @@ -373,8 +291,8 @@ ar->state = ATH10K_STATE_UTF; - if (strlen(ar->testmode.utf_version) > 0) - ver = ar->testmode.utf_version; + if (strlen(ar->testmode.utf_mode_fw.fw_file.fw_version) > 0) + ver = ar->testmode.utf_mode_fw.fw_file.fw_version; else ver = "API 1"; @@ -387,14 +305,14 @@ err_power_down: ath10k_hif_power_down(ar); -err_fw_features: - /* return the original firmware features */ - memcpy(ar->fw_features, ar->testmode.orig_fw_features, - sizeof(ar->fw_features)); - ar->wmi.op_version = ar->testmode.orig_wmi_op_version; +err_release_utf_mode_fw: + if (ar->testmode.utf_mode_fw.fw_file.codeswap_data && + ar->testmode.utf_mode_fw.fw_file.codeswap_len) + ath10k_swap_code_seg_release(ar, + &ar->testmode.utf_mode_fw.fw_file); - release_firmware(ar->testmode.utf); - ar->testmode.utf = NULL; + release_firmware(ar->testmode.utf_mode_fw.fw_file.firmware); + ar->testmode.utf_mode_fw.fw_file.firmware = NULL; err: mutex_unlock(&ar->conf_mutex); @@ -415,13 +333,13 @@ spin_unlock_bh(&ar->data_lock); - /* return the original firmware features */ - memcpy(ar->fw_features, ar->testmode.orig_fw_features, - sizeof(ar->fw_features)); - ar->wmi.op_version = ar->testmode.orig_wmi_op_version; + if (ar->testmode.utf_mode_fw.fw_file.codeswap_data && + ar->testmode.utf_mode_fw.fw_file.codeswap_len) + ath10k_swap_code_seg_release(ar, + &ar->testmode.utf_mode_fw.fw_file); - release_firmware(ar->testmode.utf); - ar->testmode.utf = NULL; + release_firmware(ar->testmode.utf_mode_fw.fw_file.firmware); + ar->testmode.utf_mode_fw.fw_file.firmware = NULL; ar->state = ATH10K_STATE_OFF; } @@ -479,7 +397,7 @@ cmd_id = nla_get_u32(tb[ATH10K_TM_ATTR_WMI_CMDID]); ath10k_dbg(ar, ATH10K_DBG_TESTMODE, - "testmode cmd wmi cmd_id %d buf %p buf_len %d\n", + "testmode cmd wmi cmd_id %d buf %pK buf_len %d\n", cmd_id, buf, buf_len); ath10k_dbg_dump(ar, ATH10K_DBG_TESTMODE, NULL, "", buf, buf_len); diff -ruw linux-4.4.115/drivers/net/wireless/ath/ath10k/testmode_i.h linux-4.4.115-fbx/drivers/net/wireless/ath/ath10k/testmode_i.h --- linux-4.4.115/drivers/net/wireless/ath/ath10k/testmode_i.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/net/wireless/ath/ath10k/testmode_i.h 2019-01-22 16:16:25.423263793 +0100 @@ -33,6 +33,7 @@ ATH10K_TM_ATTR_WMI_CMDID = 3, ATH10K_TM_ATTR_VERSION_MAJOR = 4, ATH10K_TM_ATTR_VERSION_MINOR = 5, + ATH10K_TM_ATTR_WMI_OP_VERSION = 6, /* keep last */ __ATH10K_TM_ATTR_AFTER_LAST, diff -ruw linux-4.4.115/drivers/net/wireless/ath/ath10k/thermal.c linux-4.4.115-fbx/drivers/net/wireless/ath/ath10k/thermal.c --- linux-4.4.115/drivers/net/wireless/ath/ath10k/thermal.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/net/wireless/ath/ath10k/thermal.c 2019-01-22 16:16:25.423263793 +0100 @@ -187,12 +187,12 @@ /* Do not register hwmon device when temperature reading is not * supported by firmware */ - if (ar->wmi.op_version != ATH10K_FW_WMI_OP_VERSION_10_2_4) + if (!(ar->wmi.ops->gen_pdev_get_temperature)) return 0; /* Avoid linking error on devm_hwmon_device_register_with_groups, I * guess linux/hwmon.h is missing proper stubs. */ - if (!config_enabled(CONFIG_HWMON)) + if (!IS_REACHABLE(CONFIG_HWMON)) return 0; hwmon_dev = devm_hwmon_device_register_with_groups(ar->dev, diff -ruw linux-4.4.115/drivers/net/wireless/ath/ath10k/thermal.h linux-4.4.115-fbx/drivers/net/wireless/ath/ath10k/thermal.h --- linux-4.4.115/drivers/net/wireless/ath/ath10k/thermal.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/net/wireless/ath/ath10k/thermal.h 2019-01-22 16:16:25.423263793 +0100 @@ -36,7 +36,7 @@ int temperature; }; -#ifdef CONFIG_THERMAL +#if IS_REACHABLE(CONFIG_THERMAL) int ath10k_thermal_register(struct ath10k *ar); void ath10k_thermal_unregister(struct ath10k *ar); void ath10k_thermal_event_temperature(struct ath10k *ar, int temperature); diff -ruw linux-4.4.115/drivers/net/wireless/ath/ath10k/trace.h linux-4.4.115-fbx/drivers/net/wireless/ath/ath10k/trace.h --- linux-4.4.115/drivers/net/wireless/ath/ath10k/trace.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/net/wireless/ath/ath10k/trace.h 2019-10-29 09:26:24.461211183 +0100 @@ -250,6 +250,7 @@ TP_STRUCT__entry( __string(device, dev_name(ar->dev)) __string(driver, dev_driver_string(ar->dev)) + __field(u8, hw_type); __field(size_t, buf_len) __dynamic_array(u8, buf, buf_len) ), @@ -257,14 +258,16 @@ TP_fast_assign( __assign_str(device, dev_name(ar->dev)); __assign_str(driver, dev_driver_string(ar->dev)); + __entry->hw_type = ar->hw_rev; __entry->buf_len = buf_len; memcpy(__get_dynamic_array(buf), buf, buf_len); ), TP_printk( - "%s %s len %zu", + "%s %s %d len %zu", __get_str(driver), __get_str(device), + __entry->hw_type, __entry->buf_len ) ); @@ -277,6 +280,7 @@ TP_STRUCT__entry( __string(device, dev_name(ar->dev)) __string(driver, dev_driver_string(ar->dev)) + __field(u8, hw_type); __field(u16, buf_len) __dynamic_array(u8, pktlog, buf_len) ), @@ -284,14 +288,16 @@ TP_fast_assign( __assign_str(device, dev_name(ar->dev)); __assign_str(driver, dev_driver_string(ar->dev)); + __entry->hw_type = ar->hw_rev; __entry->buf_len = buf_len; memcpy(__get_dynamic_array(pktlog), buf, buf_len); ), TP_printk( - "%s %s size %hu", + "%s %s %d size %hu", __get_str(driver), __get_str(device), + __entry->hw_type, __entry->buf_len ) ); @@ -440,6 +446,7 @@ TP_STRUCT__entry( __string(device, dev_name(ar->dev)) __string(driver, dev_driver_string(ar->dev)) + __field(u8, hw_type); __field(u16, len) __dynamic_array(u8, rxdesc, len) ), @@ -447,14 +454,16 @@ TP_fast_assign( __assign_str(device, dev_name(ar->dev)); __assign_str(driver, dev_driver_string(ar->dev)); + __entry->hw_type = ar->hw_rev; __entry->len = len; memcpy(__get_dynamic_array(rxdesc), data, len); ), TP_printk( - "%s %s rxdesc len %d", + "%s %s %d rxdesc len %d", __get_str(driver), __get_str(device), + __entry->hw_type, __entry->len ) ); diff -ruw linux-4.4.115/drivers/net/wireless/ath/ath10k/txrx.c linux-4.4.115-fbx/drivers/net/wireless/ath/ath10k/txrx.c --- linux-4.4.115/drivers/net/wireless/ath/ath10k/txrx.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/net/wireless/ath/ath10k/txrx.c 2019-01-22 16:16:25.427263830 +0100 @@ -23,7 +23,12 @@ static void ath10k_report_offchan_tx(struct ath10k *ar, struct sk_buff *skb) { - if (!ATH10K_SKB_CB(skb)->htt.is_offchan) + struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); + + if (likely(!(info->flags & IEEE80211_TX_CTL_TX_OFFCHAN))) + return; + + if (ath10k_mac_tx_frm_has_freq(ar)) return; /* If the original wait_for_completion() timed out before @@ -39,32 +44,30 @@ complete(&ar->offchan_tx_completed); ar->offchan_tx_skb = NULL; /* just for sanity */ - ath10k_dbg(ar, ATH10K_DBG_HTT, "completed offchannel skb %p\n", skb); + ath10k_dbg(ar, ATH10K_DBG_HTT, "completed offchannel skb %pK\n", skb); out: spin_unlock_bh(&ar->data_lock); } -void ath10k_txrx_tx_unref(struct ath10k_htt *htt, +int ath10k_txrx_tx_unref(struct ath10k_htt *htt, const struct htt_tx_done *tx_done) { struct ath10k *ar = htt->ar; struct device *dev = ar->dev; struct ieee80211_tx_info *info; + struct ieee80211_txq *txq; struct ath10k_skb_cb *skb_cb; + struct ath10k_txq *artxq; struct sk_buff *msdu; - struct ieee80211_hdr *hdr; - __le16 fc; - bool limit_mgmt_desc = false; ath10k_dbg(ar, ATH10K_DBG_HTT, - "htt tx completion msdu_id %u discard %d no_ack %d success %d\n", - tx_done->msdu_id, !!tx_done->discard, - !!tx_done->no_ack, !!tx_done->success); + "htt tx completion msdu_id %u status %d\n", + tx_done->msdu_id, tx_done->status); if (tx_done->msdu_id >= htt->max_num_pending_tx) { ath10k_warn(ar, "warning: msdu_id %d too big, ignoring\n", tx_done->msdu_id); - return; + return -EINVAL; } spin_lock_bh(&htt->tx_lock); @@ -73,23 +76,23 @@ ath10k_warn(ar, "received tx completion for invalid msdu_id: %d\n", tx_done->msdu_id); spin_unlock_bh(&htt->tx_lock); - return; + return -ENOENT; } - hdr = (struct ieee80211_hdr *)msdu->data; - fc = hdr->frame_control; + skb_cb = ATH10K_SKB_CB(msdu); + txq = skb_cb->txq; - if (unlikely(ieee80211_is_mgmt(fc)) && - ar->hw_params.max_probe_resp_desc_thres) - limit_mgmt_desc = true; + if (txq) { + artxq = (void *)txq->drv_priv; + artxq->num_fw_queued--; + } ath10k_htt_tx_free_msdu_id(htt, tx_done->msdu_id); - __ath10k_htt_tx_dec_pending(htt, limit_mgmt_desc); + ath10k_htt_tx_dec_pending(htt); if (htt->num_pending_tx == 0) wake_up(&htt->empty_tx_wq); spin_unlock_bh(&htt->tx_lock); - skb_cb = ATH10K_SKB_CB(msdu); dma_unmap_single(dev, skb_cb->paddr, msdu->len, DMA_TO_DEVICE); ath10k_report_offchan_tx(htt->ar, msdu); @@ -98,22 +101,25 @@ memset(&info->status, 0, sizeof(info->status)); trace_ath10k_txrx_tx_unref(ar, tx_done->msdu_id); - if (tx_done->discard) { + if (tx_done->status == HTT_TX_COMPL_STATE_DISCARD) { ieee80211_free_txskb(htt->ar->hw, msdu); - return; + return 0; } if (!(info->flags & IEEE80211_TX_CTL_NO_ACK)) info->flags |= IEEE80211_TX_STAT_ACK; - if (tx_done->no_ack) + if (tx_done->status == HTT_TX_COMPL_STATE_NOACK) info->flags &= ~IEEE80211_TX_STAT_ACK; - if (tx_done->success && (info->flags & IEEE80211_TX_CTL_NO_ACK)) + if ((tx_done->status == HTT_TX_COMPL_STATE_ACK) && + (info->flags & IEEE80211_TX_CTL_NO_ACK)) info->flags |= IEEE80211_TX_STAT_NOACK_TRANSMITTED; ieee80211_tx_status(htt->ar->hw, msdu); /* we do not own the msdu anymore */ + + return 0; } struct ath10k_peer *ath10k_peer_find(struct ath10k *ar, int vdev_id, @@ -126,7 +132,7 @@ list_for_each_entry(peer, &ar->peers, list) { if (peer->vdev_id != vdev_id) continue; - if (memcmp(peer->addr, addr, ETH_ALEN)) + if (!ether_addr_equal(peer->addr, addr)) continue; return peer; @@ -186,6 +192,13 @@ struct ath10k *ar = htt->ar; struct ath10k_peer *peer; + if (ev->peer_id >= ATH10K_MAX_NUM_PEER_IDS) { + ath10k_warn(ar, + "received htt peer map event with idx out of bounds: %hu\n", + ev->peer_id); + return; + } + spin_lock_bh(&ar->data_lock); peer = ath10k_peer_find(ar, ev->vdev_id, ev->addr); if (!peer) { @@ -202,6 +215,8 @@ ath10k_dbg(ar, ATH10K_DBG_HTT, "htt peer map vdev %d peer %pM id %d\n", ev->vdev_id, ev->addr, ev->peer_id); + WARN_ON(ar->peer_map[ev->peer_id] && (ar->peer_map[ev->peer_id] != peer)); + ar->peer_map[ev->peer_id] = peer; set_bit(ev->peer_id, peer->peer_ids); exit: spin_unlock_bh(&ar->data_lock); @@ -213,6 +228,13 @@ struct ath10k *ar = htt->ar; struct ath10k_peer *peer; + if (ev->peer_id >= ATH10K_MAX_NUM_PEER_IDS) { + ath10k_warn(ar, + "received htt peer unmap event with idx out of bounds: %hu\n", + ev->peer_id); + return; + } + spin_lock_bh(&ar->data_lock); peer = ath10k_peer_find_by_id(ar, ev->peer_id); if (!peer) { @@ -224,6 +246,7 @@ ath10k_dbg(ar, ATH10K_DBG_HTT, "htt peer unmap vdev %d peer %pM id %d\n", peer->vdev_id, peer->addr, ev->peer_id); + ar->peer_map[ev->peer_id] = NULL; clear_bit(ev->peer_id, peer->peer_ids); if (bitmap_empty(peer->peer_ids, ATH10K_MAX_NUM_PEER_IDS)) { diff -ruw linux-4.4.115/drivers/net/wireless/ath/ath10k/txrx.h linux-4.4.115-fbx/drivers/net/wireless/ath/ath10k/txrx.h --- linux-4.4.115/drivers/net/wireless/ath/ath10k/txrx.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/net/wireless/ath/ath10k/txrx.h 2019-01-22 16:16:25.427263830 +0100 @@ -19,7 +19,7 @@ #include "htt.h" -void ath10k_txrx_tx_unref(struct ath10k_htt *htt, +int ath10k_txrx_tx_unref(struct ath10k_htt *htt, const struct htt_tx_done *tx_done); struct ath10k_peer *ath10k_peer_find(struct ath10k *ar, int vdev_id, diff -ruw linux-4.4.115/drivers/net/wireless/ath/ath10k/wmi.c linux-4.4.115-fbx/drivers/net/wireless/ath/ath10k/wmi.c --- linux-4.4.115/drivers/net/wireless/ath/ath10k/wmi.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/net/wireless/ath/ath10k/wmi.c 2019-10-29 09:26:24.465211222 +0100 @@ -29,6 +29,9 @@ #include "p2p.h" #include "hw.h" +#define ATH10K_WMI_BARRIER_ECHO_ID 0xBA991E9 +#define ATH10K_WMI_BARRIER_TIMEOUT_HZ (3 * HZ) + /* MAIN WMI cmd track */ static struct wmi_cmd_map wmi_cmd_map = { .init_cmdid = WMI_INIT_CMDID, @@ -521,7 +524,8 @@ .vdev_filter_neighbor_rx_packets_cmdid = WMI_CMD_UNSUPPORTED, .mu_cal_start_cmdid = WMI_CMD_UNSUPPORTED, .set_cca_params_cmdid = WMI_CMD_UNSUPPORTED, - .pdev_bss_chan_info_request_cmdid = WMI_CMD_UNSUPPORTED, + .pdev_bss_chan_info_request_cmdid = + WMI_10_2_PDEV_BSS_CHAN_INFO_REQUEST_CMDID, }; /* 10.4 WMI cmd track */ @@ -705,6 +709,7 @@ .set_cca_params_cmdid = WMI_10_4_SET_CCA_PARAMS_CMDID, .pdev_bss_chan_info_request_cmdid = WMI_10_4_PDEV_BSS_CHAN_INFO_REQUEST_CMDID, + .ext_resource_cfg_cmdid = WMI_10_4_EXT_RESOURCE_CFG_CMDID, }; /* MAIN WMI VDEV param map */ @@ -780,6 +785,7 @@ .meru_vc = WMI_VDEV_PARAM_UNSUPPORTED, .rx_decap_type = WMI_VDEV_PARAM_UNSUPPORTED, .bw_nss_ratemask = WMI_VDEV_PARAM_UNSUPPORTED, + .set_tsf = WMI_VDEV_PARAM_UNSUPPORTED, }; /* 10.X WMI VDEV param map */ @@ -855,6 +861,7 @@ .meru_vc = WMI_VDEV_PARAM_UNSUPPORTED, .rx_decap_type = WMI_VDEV_PARAM_UNSUPPORTED, .bw_nss_ratemask = WMI_VDEV_PARAM_UNSUPPORTED, + .set_tsf = WMI_VDEV_PARAM_UNSUPPORTED, }; static struct wmi_vdev_param_map wmi_10_2_4_vdev_param_map = { @@ -929,6 +936,7 @@ .meru_vc = WMI_VDEV_PARAM_UNSUPPORTED, .rx_decap_type = WMI_VDEV_PARAM_UNSUPPORTED, .bw_nss_ratemask = WMI_VDEV_PARAM_UNSUPPORTED, + .set_tsf = WMI_10X_VDEV_PARAM_TSF_INCREMENT, }; static struct wmi_vdev_param_map wmi_10_4_vdev_param_map = { @@ -1004,6 +1012,7 @@ .meru_vc = WMI_10_4_VDEV_PARAM_MERU_VC, .rx_decap_type = WMI_10_4_VDEV_PARAM_RX_DECAP_TYPE, .bw_nss_ratemask = WMI_10_4_VDEV_PARAM_BW_NSS_RATEMASK, + .set_tsf = WMI_10_4_VDEV_PARAM_TSF_INCREMENT, }; static struct wmi_pdev_param_map wmi_pdev_param_map = { @@ -1098,6 +1107,7 @@ .wapi_mbssid_offset = WMI_PDEV_PARAM_UNSUPPORTED, .arp_srcaddr = WMI_PDEV_PARAM_UNSUPPORTED, .arp_dstaddr = WMI_PDEV_PARAM_UNSUPPORTED, + .enable_btcoex = WMI_PDEV_PARAM_UNSUPPORTED, }; static struct wmi_pdev_param_map wmi_10x_pdev_param_map = { @@ -1193,6 +1203,7 @@ .wapi_mbssid_offset = WMI_PDEV_PARAM_UNSUPPORTED, .arp_srcaddr = WMI_PDEV_PARAM_UNSUPPORTED, .arp_dstaddr = WMI_PDEV_PARAM_UNSUPPORTED, + .enable_btcoex = WMI_PDEV_PARAM_UNSUPPORTED, }; static struct wmi_pdev_param_map wmi_10_2_4_pdev_param_map = { @@ -1288,6 +1299,7 @@ .wapi_mbssid_offset = WMI_PDEV_PARAM_UNSUPPORTED, .arp_srcaddr = WMI_PDEV_PARAM_UNSUPPORTED, .arp_dstaddr = WMI_PDEV_PARAM_UNSUPPORTED, + .enable_btcoex = WMI_PDEV_PARAM_UNSUPPORTED, }; /* firmware 10.2 specific mappings */ @@ -1544,6 +1556,62 @@ .wapi_mbssid_offset = WMI_10_4_PDEV_PARAM_WAPI_MBSSID_OFFSET, .arp_srcaddr = WMI_10_4_PDEV_PARAM_ARP_SRCADDR, .arp_dstaddr = WMI_10_4_PDEV_PARAM_ARP_DSTADDR, + .enable_btcoex = WMI_10_4_PDEV_PARAM_ENABLE_BTCOEX, +}; + +static const struct wmi_peer_flags_map wmi_peer_flags_map = { + .auth = WMI_PEER_AUTH, + .qos = WMI_PEER_QOS, + .need_ptk_4_way = WMI_PEER_NEED_PTK_4_WAY, + .need_gtk_2_way = WMI_PEER_NEED_GTK_2_WAY, + .apsd = WMI_PEER_APSD, + .ht = WMI_PEER_HT, + .bw40 = WMI_PEER_40MHZ, + .stbc = WMI_PEER_STBC, + .ldbc = WMI_PEER_LDPC, + .dyn_mimops = WMI_PEER_DYN_MIMOPS, + .static_mimops = WMI_PEER_STATIC_MIMOPS, + .spatial_mux = WMI_PEER_SPATIAL_MUX, + .vht = WMI_PEER_VHT, + .bw80 = WMI_PEER_80MHZ, + .vht_2g = WMI_PEER_VHT_2G, + .pmf = WMI_PEER_PMF, +}; + +static const struct wmi_peer_flags_map wmi_10x_peer_flags_map = { + .auth = WMI_10X_PEER_AUTH, + .qos = WMI_10X_PEER_QOS, + .need_ptk_4_way = WMI_10X_PEER_NEED_PTK_4_WAY, + .need_gtk_2_way = WMI_10X_PEER_NEED_GTK_2_WAY, + .apsd = WMI_10X_PEER_APSD, + .ht = WMI_10X_PEER_HT, + .bw40 = WMI_10X_PEER_40MHZ, + .stbc = WMI_10X_PEER_STBC, + .ldbc = WMI_10X_PEER_LDPC, + .dyn_mimops = WMI_10X_PEER_DYN_MIMOPS, + .static_mimops = WMI_10X_PEER_STATIC_MIMOPS, + .spatial_mux = WMI_10X_PEER_SPATIAL_MUX, + .vht = WMI_10X_PEER_VHT, + .bw80 = WMI_10X_PEER_80MHZ, +}; + +static const struct wmi_peer_flags_map wmi_10_2_peer_flags_map = { + .auth = WMI_10_2_PEER_AUTH, + .qos = WMI_10_2_PEER_QOS, + .need_ptk_4_way = WMI_10_2_PEER_NEED_PTK_4_WAY, + .need_gtk_2_way = WMI_10_2_PEER_NEED_GTK_2_WAY, + .apsd = WMI_10_2_PEER_APSD, + .ht = WMI_10_2_PEER_HT, + .bw40 = WMI_10_2_PEER_40MHZ, + .stbc = WMI_10_2_PEER_STBC, + .ldbc = WMI_10_2_PEER_LDPC, + .dyn_mimops = WMI_10_2_PEER_DYN_MIMOPS, + .static_mimops = WMI_10_2_PEER_STATIC_MIMOPS, + .spatial_mux = WMI_10_2_PEER_SPATIAL_MUX, + .vht = WMI_10_2_PEER_VHT, + .bw80 = WMI_10_2_PEER_80MHZ, + .vht_2g = WMI_10_2_PEER_VHT_2G, + .pmf = WMI_10_2_PEER_PMF, }; void ath10k_wmi_put_wmi_channel(struct wmi_channel *ch, @@ -1573,6 +1641,7 @@ ch->max_power = arg->max_power; ch->reg_power = arg->max_reg_power; ch->antenna_max = arg->max_antenna_gain; + ch->max_tx_power = arg->max_power; /* mode & flags share storage */ ch->mode = arg->mode; @@ -1660,6 +1729,8 @@ struct ath10k *ar = arvif->ar; struct ath10k_skb_cb *cb; struct sk_buff *bcn; + bool dtim_zero; + bool deliver_cab; int ret; spin_lock_bh(&ar->data_lock); @@ -1679,12 +1750,14 @@ arvif->beacon_state = ATH10K_BEACON_SENDING; spin_unlock_bh(&ar->data_lock); + dtim_zero = !!(cb->flags & ATH10K_SKB_F_DTIM_ZERO); + deliver_cab = !!(cb->flags & ATH10K_SKB_F_DELIVER_CAB); ret = ath10k_wmi_beacon_send_ref_nowait(arvif->ar, arvif->vdev_id, bcn->data, bcn->len, cb->paddr, - cb->bcn.dtim_zero, - cb->bcn.deliver_cab); + dtim_zero, + deliver_cab); spin_lock_bh(&ar->data_lock); @@ -1726,6 +1799,9 @@ { int ret = -EOPNOTSUPP; + if (test_bit(ATH10K_FLAG_CRASH_FLUSH, &ar->dev_flags)) + return -ESHUTDOWN; + might_sleep(); if (cmd_id == WMI_CMD_UNSUPPORTED) { @@ -1755,16 +1831,26 @@ static struct sk_buff * ath10k_wmi_op_gen_mgmt_tx(struct ath10k *ar, struct sk_buff *msdu) { + struct ath10k_skb_cb *cb = ATH10K_SKB_CB(msdu); + struct ath10k_vif *arvif; struct wmi_mgmt_tx_cmd *cmd; struct ieee80211_hdr *hdr; struct sk_buff *skb; int len; + u32 vdev_id; u32 buf_len = msdu->len; u16 fc; hdr = (struct ieee80211_hdr *)msdu->data; fc = le16_to_cpu(hdr->frame_control); + if (cb->vif) { + arvif = (void *)cb->vif->drv_priv; + vdev_id = arvif->vdev_id; + } else { + vdev_id = 0; + } + if (WARN_ON_ONCE(!ieee80211_is_mgmt(hdr->frame_control))) return ERR_PTR(-EINVAL); @@ -1786,7 +1872,7 @@ cmd = (struct wmi_mgmt_tx_cmd *)skb->data; - cmd->hdr.vdev_id = __cpu_to_le32(ATH10K_SKB_CB(msdu)->vdev_id); + cmd->hdr.vdev_id = __cpu_to_le32(vdev_id); cmd->hdr.tx_rate = 0; cmd->hdr.tx_power = 0; cmd->hdr.buf_len = __cpu_to_le32(buf_len); @@ -1794,7 +1880,7 @@ ether_addr_copy(cmd->hdr.peer_macaddr.addr, ieee80211_get_DA(hdr)); memcpy(cmd->buf, msdu->data, msdu->len); - ath10k_dbg(ar, ATH10K_DBG_WMI, "wmi mgmt tx skb %p len %d ftype %02x stype %02x\n", + ath10k_dbg(ar, ATH10K_DBG_WMI, "wmi mgmt tx skb %pK len %d ftype %02x stype %02x\n", msdu, skb->len, fc & IEEE80211_FCTL_FTYPE, fc & IEEE80211_FCTL_STYPE); trace_ath10k_tx_hdr(ar, skb->data, skb->len); @@ -2032,34 +2118,6 @@ return 0; } -static inline enum ieee80211_band phy_mode_to_band(u32 phy_mode) -{ - enum ieee80211_band band; - - switch (phy_mode) { - case MODE_11A: - case MODE_11NA_HT20: - case MODE_11NA_HT40: - case MODE_11AC_VHT20: - case MODE_11AC_VHT40: - case MODE_11AC_VHT80: - band = IEEE80211_BAND_5GHZ; - break; - case MODE_11G: - case MODE_11B: - case MODE_11GONLY: - case MODE_11NG_HT20: - case MODE_11NG_HT40: - case MODE_11AC_VHT20_2G: - case MODE_11AC_VHT40_2G: - case MODE_11AC_VHT80_2G: - default: - band = IEEE80211_BAND_2GHZ; - } - - return band; -} - /* If keys are configured, HW decrypts all frames * with protected bit set. Mark such frames as decrypted. */ @@ -2100,10 +2158,13 @@ struct wmi_mgmt_rx_event_v1 *ev_v1; struct wmi_mgmt_rx_event_v2 *ev_v2; struct wmi_mgmt_rx_hdr_v1 *ev_hdr; + struct wmi_mgmt_rx_ext_info *ext_info; size_t pull_len; u32 msdu_len; + u32 len; - if (test_bit(ATH10K_FW_FEATURE_EXT_WMI_MGMT_RX, ar->fw_features)) { + if (test_bit(ATH10K_FW_FEATURE_EXT_WMI_MGMT_RX, + ar->running_fw->fw_file.fw_features)) { ev_v2 = (struct wmi_mgmt_rx_event_v2 *)skb->data; ev_hdr = &ev_v2->hdr.v1; pull_len = sizeof(*ev_v2); @@ -2128,6 +2189,12 @@ if (skb->len < msdu_len) return -EPROTO; + if (le32_to_cpu(arg->status) & WMI_RX_STATUS_EXT_INFO) { + len = ALIGN(le32_to_cpu(arg->buf_len), 4); + ext_info = (struct wmi_mgmt_rx_ext_info *)(skb->data + len); + memcpy(&arg->ext_info, ext_info, + sizeof(struct wmi_mgmt_rx_ext_info)); + } /* the WMI buffer might've ended up being padded to 4 bytes due to HTC * trailer with credit update. Trim the excess garbage. */ @@ -2144,6 +2211,8 @@ struct wmi_10_4_mgmt_rx_hdr *ev_hdr; size_t pull_len; u32 msdu_len; + struct wmi_mgmt_rx_ext_info *ext_info; + u32 len; ev = (struct wmi_10_4_mgmt_rx_event *)skb->data; ev_hdr = &ev->hdr; @@ -2164,12 +2233,113 @@ if (skb->len < msdu_len) return -EPROTO; + if (le32_to_cpu(arg->status) & WMI_RX_STATUS_EXT_INFO) { + len = ALIGN(le32_to_cpu(arg->buf_len), 4); + ext_info = (struct wmi_mgmt_rx_ext_info *)(skb->data + len); + memcpy(&arg->ext_info, ext_info, + sizeof(struct wmi_mgmt_rx_ext_info)); + } + /* Make sure bytes added for padding are removed. */ skb_trim(skb, msdu_len); return 0; } +static bool ath10k_wmi_rx_is_decrypted(struct ath10k *ar, + struct ieee80211_hdr *hdr) +{ + if (!ieee80211_has_protected(hdr->frame_control)) + return false; + + /* FW delivers WEP Shared Auth frame with Protected Bit set and + * encrypted payload. However in case of PMF it delivers decrypted + * frames with Protected Bit set. + */ + if (ieee80211_is_auth(hdr->frame_control)) + return false; + + /* qca99x0 based FW delivers broadcast or multicast management frames + * (ex: group privacy action frames in mesh) as encrypted payload. + */ + if (is_multicast_ether_addr(ieee80211_get_DA(hdr)) && + ar->hw_params.sw_decrypt_mcast_mgmt) + return false; + + return true; +} + +int ath10k_wmi_tlv_event_peer_delete_resp(struct ath10k *ar, + struct sk_buff *skb) +{ + int ret; + struct wmi_peer_delete_resp_ev_arg arg = {}; + + ret = ath10k_wmi_pull_peer_delete_resp(ar, skb, &arg); + if (ret) { + ath10k_warn(ar, "failed to parse peer delete resp: %d\n", ret); + dev_kfree_skb(skb); + return ret; + } + ath10k_dbg(ar, ATH10K_DBG_WMI, "WMI_TLV_PEER_DELETE_RESP_EVENTID\n"); + complete(&ar->peer_delete_done); + + return 0; +} + +static int wmi_tlv_process_mgmt_tx_comp(struct ath10k *ar, u32 desc_id, + u32 status) +{ + struct ath10k_mgmt_tx_pkt_addr *pkt_addr; + struct ath10k_wmi *wmi = &ar->wmi; + struct ieee80211_tx_info *info; + struct sk_buff *msdu; + int ret = 0; + + spin_lock_bh(&wmi->mgmt_tx_lock); + pkt_addr = idr_find(&wmi->mgmt_pending_tx, desc_id); + if (!pkt_addr) { + ath10k_warn(ar, "received mgmt tx completion for invalid msdu_id: %d\n", + desc_id); + ret = -ENOENT; + goto tx_comp_process_done; + } + + msdu = pkt_addr->vaddr; + dma_unmap_single(ar->dev, pkt_addr->paddr, + msdu->len, DMA_FROM_DEVICE); + info = IEEE80211_SKB_CB(msdu); + if (!status) + info->flags |= IEEE80211_TX_STAT_ACK; + else + info->flags |= status; + ieee80211_tx_status_irqsafe(ar->hw, msdu); + ret = 0; + +tx_comp_process_done: + idr_remove(&wmi->mgmt_pending_tx, desc_id); + spin_unlock_bh(&wmi->mgmt_tx_lock); + + return ret; +} + +int ath10k_wmi_tlv_event_mgmt_tx_compl(struct ath10k *ar, struct sk_buff *skb) +{ + int ret; + struct wmi_tlv_mgmt_tx_compl_ev_arg arg; + + ret = ath10k_wmi_pull_mgmt_tx_compl(ar, skb, &arg); + if (ret) { + ath10k_warn(ar, "failed to parse mgmt comp event: %d\n", ret); + return ret; + } + + wmi_tlv_process_mgmt_tx_comp(ar, arg.desc_id, arg.status); + ath10k_dbg(ar, ATH10K_DBG_WMI, "WMI_TLV_MGMT_TX_COMPLETION_EVENTID\n"); + + return 0; +} + int ath10k_wmi_event_mgmt_rx(struct ath10k *ar, struct sk_buff *skb) { struct wmi_mgmt_rx_ev_arg arg = {}; @@ -2204,22 +2374,9 @@ ath10k_dbg(ar, ATH10K_DBG_MGMT, "event mgmt rx status %08x\n", rx_status); - if (test_bit(ATH10K_CAC_RUNNING, &ar->dev_flags)) { - dev_kfree_skb(skb); - return 0; - } - - if (rx_status & WMI_RX_STATUS_ERR_DECRYPT) { - dev_kfree_skb(skb); - return 0; - } - - if (rx_status & WMI_RX_STATUS_ERR_KEY_CACHE_MISS) { - dev_kfree_skb(skb); - return 0; - } - - if (rx_status & WMI_RX_STATUS_ERR_CRC) { + if ((test_bit(ATH10K_CAC_RUNNING, &ar->dev_flags)) || + (rx_status & (WMI_RX_STATUS_ERR_DECRYPT | + WMI_RX_STATUS_ERR_KEY_CACHE_MISS | WMI_RX_STATUS_ERR_CRC))) { dev_kfree_skb(skb); return 0; } @@ -2227,6 +2384,11 @@ if (rx_status & WMI_RX_STATUS_ERR_MIC) status->flag |= RX_FLAG_MMIC_ERROR; + if (rx_status & WMI_RX_STATUS_EXT_INFO) { + status->mactime = + __le64_to_cpu(arg.ext_info.rx_mac_timestamp); + status->flag |= RX_FLAG_MACTIME_END; + } /* Hardware can Rx CCK rates on 5GHz. In that case phy_mode is set to * MODE_11B. This means phy_mode is not a reliable source for the band * of mgmt rx. @@ -2256,13 +2418,15 @@ hdr = (struct ieee80211_hdr *)skb->data; fc = le16_to_cpu(hdr->frame_control); + /* Firmware is guaranteed to report all essential management frames via + * WMI while it can deliver some extra via HTT. Since there can be + * duplicates split the reporting wrt monitor/sniffing. + */ + status->flag |= RX_FLAG_SKIP_MONITOR; + ath10k_wmi_handle_wep_reauth(ar, skb, status); - /* FW delivers WEP Shared Auth frame with Protected Bit set and - * encrypted payload. However in case of PMF it delivers decrypted - * frames with Protected Bit set. */ - if (ieee80211_has_protected(hdr->frame_control) && - !ieee80211_is_auth(hdr->frame_control)) { + if (ath10k_wmi_rx_is_decrypted(ar, hdr)) { status->flag |= RX_FLAG_DECRYPTED; if (!ieee80211_is_action(hdr->frame_control) && @@ -2279,7 +2443,7 @@ ath10k_mac_handle_beacon(ar, skb); ath10k_dbg(ar, ATH10K_DBG_MGMT, - "event mgmt rx skb %p len %d ftype %02x stype %02x\n", + "event mgmt rx skb %pK len %d ftype %02x stype %02x\n", skb, skb->len, fc & IEEE80211_FCTL_FTYPE, fc & IEEE80211_FCTL_STYPE); @@ -2353,6 +2517,31 @@ return 0; } +static void wlan_fill_survey_result(struct ath10k *ar, + struct survey_info *survey, + struct wmi_ch_info_ev_arg arg) +{ + u64 clock_freq; + + if (!arg.mac_clk_mhz || !survey) + return; + + clock_freq = arg.mac_clk_mhz * 1000; + + memset(survey, 0, sizeof(*survey)); + + survey->noise = __le32_to_cpu(arg.noise_floor); + survey->time = __le32_to_cpu(arg.cycle_count) / clock_freq; + survey->time_busy = __le32_to_cpu(arg.rx_clear_count) / clock_freq; + survey->time_tx = __le32_to_cpu(arg.rx_clear_count) / clock_freq; + + survey->filled = SURVEY_INFO_NOISE_DBM; + ar->ch_info_can_report_survey = true; + + survey->filled |= (SURVEY_INFO_TIME | SURVEY_INFO_TIME_BUSY | + SURVEY_INFO_TIME_TX); +} + void ath10k_wmi_event_chan_info(struct ath10k *ar, struct sk_buff *skb) { struct wmi_ch_info_ev_arg arg = {}; @@ -2397,6 +2586,12 @@ goto exit; } + if (QCA_REV_WCN3990(ar)) { + survey = &ar->survey[idx]; + wlan_fill_survey_result(ar, survey, arg); + goto exit; + } + if (cmd_flags & WMI_CHAN_INFO_FLAG_COMPLETE) { if (ar->ch_info_can_report_survey) { survey = &ar->survey[idx]; @@ -2427,7 +2622,21 @@ void ath10k_wmi_event_echo(struct ath10k *ar, struct sk_buff *skb) { - ath10k_dbg(ar, ATH10K_DBG_WMI, "WMI_ECHO_EVENTID\n"); + struct wmi_echo_ev_arg arg = {}; + int ret; + + ret = ath10k_wmi_pull_echo_ev(ar, skb, &arg); + if (ret) { + ath10k_warn(ar, "failed to parse echo: %d\n", ret); + return; + } + + ath10k_dbg(ar, ATH10K_DBG_WMI, + "wmi event echo value 0x%08x\n", + le32_to_cpu(arg.value)); + + if (le32_to_cpu(arg.value) == ATH10K_WMI_BARRIER_ECHO_ID) + complete(&ar->wmi.barrier); } int ath10k_wmi_event_debug_mesg(struct ath10k *ar, struct sk_buff *skb) @@ -2558,6 +2767,16 @@ dst->peer_tx_rate = __le32_to_cpu(src->peer_tx_rate); } +static void +ath10k_wmi_10_4_pull_peer_stats(const struct wmi_10_4_peer_stats *src, + struct ath10k_fw_stats_peer *dst) +{ + ether_addr_copy(dst->peer_macaddr, src->peer_macaddr.addr); + dst->peer_rssi = __le32_to_cpu(src->peer_rssi); + dst->peer_tx_rate = __le32_to_cpu(src->peer_tx_rate); + dst->peer_rx_rate = __le32_to_cpu(src->peer_rx_rate); +} + static int ath10k_wmi_main_op_pull_fw_stats(struct ath10k *ar, struct sk_buff *skb, struct ath10k_fw_stats *stats) @@ -2808,11 +3027,17 @@ /* fw doesn't implement vdev stats */ for (i = 0; i < num_peer_stats; i++) { - const struct wmi_10_2_4_peer_stats *src; + const struct wmi_10_2_4_ext_peer_stats *src; struct ath10k_fw_stats_peer *dst; + int stats_len; + + if (test_bit(WMI_SERVICE_PEER_STATS, ar->wmi.svc_map)) + stats_len = sizeof(struct wmi_10_2_4_ext_peer_stats); + else + stats_len = sizeof(struct wmi_10_2_4_peer_stats); src = (void *)skb->data; - if (!skb_pull(skb, sizeof(*src))) + if (!skb_pull(skb, stats_len)) return -EPROTO; dst = kzalloc(sizeof(*dst), GFP_ATOMIC); @@ -2822,6 +3047,9 @@ ath10k_wmi_pull_peer_stats(&src->common.old, dst); dst->peer_rx_rate = __le32_to_cpu(src->common.peer_rx_rate); + + if (ath10k_peer_stats_enabled(ar)) + dst->rx_duration = __le32_to_cpu(src->rx_duration); /* FIXME: expose 10.2 specific values */ list_add_tail(&dst->list, &stats->peers); @@ -2839,6 +3067,8 @@ u32 num_pdev_ext_stats; u32 num_vdev_stats; u32 num_peer_stats; + u32 num_bcnflt_stats; + u32 stats_id; int i; if (!skb_pull(skb, sizeof(*ev))) @@ -2848,6 +3078,8 @@ num_pdev_ext_stats = __le32_to_cpu(ev->num_pdev_ext_stats); num_vdev_stats = __le32_to_cpu(ev->num_vdev_stats); num_peer_stats = __le32_to_cpu(ev->num_peer_stats); + num_bcnflt_stats = __le32_to_cpu(ev->num_bcnflt_stats); + stats_id = __le32_to_cpu(ev->stats_id); for (i = 0; i < num_pdev_stats; i++) { const struct wmi_10_4_pdev_stats *src; @@ -2898,15 +3130,46 @@ if (!dst) continue; - ether_addr_copy(dst->peer_macaddr, src->peer_macaddr.addr); - dst->peer_rssi = __le32_to_cpu(src->peer_rssi); - dst->peer_tx_rate = __le32_to_cpu(src->peer_tx_rate); - dst->peer_rx_rate = __le32_to_cpu(src->peer_rx_rate); - /* FIXME: expose 10.4 specific values */ - + ath10k_wmi_10_4_pull_peer_stats(src, dst); list_add_tail(&dst->list, &stats->peers); } + for (i = 0; i < num_bcnflt_stats; i++) { + const struct wmi_10_4_bss_bcn_filter_stats *src; + + src = (void *)skb->data; + if (!skb_pull(skb, sizeof(*src))) + return -EPROTO; + + /* FIXME: expose values to userspace + * + * Note: Even though this loop seems to do nothing it is + * required to parse following sub-structures properly. + */ + } + + if ((stats_id & WMI_10_4_STAT_PEER_EXTD) == 0) + return 0; + + stats->extended = true; + + for (i = 0; i < num_peer_stats; i++) { + const struct wmi_10_4_peer_extd_stats *src; + struct ath10k_fw_extd_stats_peer *dst; + + src = (void *)skb->data; + if (!skb_pull(skb, sizeof(*src))) + return -EPROTO; + + dst = kzalloc(sizeof(*dst), GFP_ATOMIC); + if (!dst) + continue; + + ether_addr_copy(dst->peer_macaddr, src->peer_macaddr.addr); + dst->rx_duration = __le32_to_cpu(src->rx_duration); + list_add_tail(&dst->list, &stats->peers_extd); + } + return 0; } @@ -2959,6 +3222,12 @@ complete(&ar->vdev_setup_done); } +void ath10k_wmi_event_vdev_delete_resp(struct ath10k *ar, struct sk_buff *skb) +{ + ath10k_dbg(ar, ATH10K_DBG_WMI, "WMI_VDEV_DELETE_RESP_EVENTID\n"); + complete(&ar->vdev_delete_done); +} + static int ath10k_wmi_op_pull_peer_kick_ev(struct ath10k *ar, struct sk_buff *skb, struct wmi_peer_kick_ev_arg *arg) @@ -3115,10 +3384,10 @@ memcpy(tim->virtual_map, arvif->u.ap.tim_bitmap, pvm_len); if (tim->dtim_count == 0) { - ATH10K_SKB_CB(bcn)->bcn.dtim_zero = true; + ATH10K_SKB_CB(bcn)->flags |= ATH10K_SKB_F_DTIM_ZERO; if (__le32_to_cpu(tim_info->tim_mcast) == 1) - ATH10K_SKB_CB(bcn)->bcn.deliver_cab = true; + ATH10K_SKB_CB(bcn)->flags |= ATH10K_SKB_F_DELIVER_CAB; } ath10k_dbg(ar, ATH10K_DBG_MGMT, "dtim %d/%d mcast %d pvmlen %d\n", @@ -3130,7 +3399,7 @@ struct sk_buff *bcn, const struct wmi_p2p_noa_info *noa) { - if (arvif->vdev_subtype != WMI_VDEV_SUBTYPE_P2P_GO) + if (!arvif->vif->p2p) return; ath10k_dbg(ar, ATH10K_DBG_MGMT, "noa changed: %d\n", noa->changed); @@ -3190,6 +3459,50 @@ return 0; } +static int ath10k_wmi_10_2_4_op_pull_swba_ev(struct ath10k *ar, + struct sk_buff *skb, + struct wmi_swba_ev_arg *arg) +{ + struct wmi_10_2_4_host_swba_event *ev = (void *)skb->data; + u32 map; + size_t i; + + if (skb->len < sizeof(*ev)) + return -EPROTO; + + skb_pull(skb, sizeof(*ev)); + arg->vdev_map = ev->vdev_map; + + for (i = 0, map = __le32_to_cpu(ev->vdev_map); map; map >>= 1) { + if (!(map & BIT(0))) + continue; + + /* If this happens there were some changes in firmware and + * ath10k should update the max size of tim_info array. + */ + if (WARN_ON_ONCE(i == ARRAY_SIZE(arg->tim_info))) + break; + + if (__le32_to_cpu(ev->bcn_info[i].tim_info.tim_len) > + sizeof(ev->bcn_info[i].tim_info.tim_bitmap)) { + ath10k_warn(ar, "refusing to parse invalid swba structure\n"); + return -EPROTO; + } + + arg->tim_info[i].tim_len = ev->bcn_info[i].tim_info.tim_len; + arg->tim_info[i].tim_mcast = ev->bcn_info[i].tim_info.tim_mcast; + arg->tim_info[i].tim_bitmap = + ev->bcn_info[i].tim_info.tim_bitmap; + arg->tim_info[i].tim_changed = + ev->bcn_info[i].tim_info.tim_changed; + arg->tim_info[i].tim_num_ps_pending = + ev->bcn_info[i].tim_info.tim_num_ps_pending; + i++; + } + + return 0; +} + static int ath10k_wmi_10_4_op_pull_swba_ev(struct ath10k *ar, struct sk_buff *skb, struct wmi_swba_ev_arg *arg) @@ -3312,6 +3625,12 @@ continue; } + /* mac80211 would have already asked us to stop beaconing and + * bring the vdev down, so continue in that case + */ + if (!arvif->is_up) + continue; + /* There are no completions for beacons so wait for next SWBA * before telling mac80211 to decrement CSA counter * @@ -3361,7 +3680,6 @@ ath10k_warn(ar, "failed to map beacon: %d\n", ret); dev_kfree_skb_any(bcn); - ret = -EIO; goto skip; } @@ -3538,7 +3856,7 @@ phyerr->tsf_timestamp, tsf, buf_len); /* Skip event if DFS disabled */ - if (!config_enabled(CONFIG_ATH10K_DFS_CERTIFIED)) + if (!IS_ENABLED(CONFIG_ATH10K_DFS_CERTIFIED)) return; ATH10K_DFS_STAT_INC(ar, pulses_total); @@ -3811,19 +4129,20 @@ left_len -= buf_len; - switch (phy_err_code) { - case PHY_ERROR_RADAR: + if ((phy_err_code == PHY_ERROR_RADAR) || + (hdr_arg.phy_err_mask0 & + WMI_PHY_ERROR_MASK0_RADAR)) { ath10k_wmi_event_dfs(ar, &phyerr_arg, tsf); - break; - case PHY_ERROR_SPECTRAL_SCAN: + } else if ((phy_err_code == + WMI_PHY_ERROR_MASK0_SPECTRAL_SCAN) || + (hdr_arg.phy_err_mask0 & + WMI_PHY_ERROR_MASK0_SPECTRAL_SCAN)) { ath10k_wmi_event_spectral_scan(ar, &phyerr_arg, tsf); - break; - case PHY_ERROR_FALSE_RADAR_EXT: + } else if ((phy_err_code == PHY_ERROR_FALSE_RADAR_EXT) || + (hdr_arg.phy_err_mask0 & + WMI_PHY_ERROR_MASK0_FALSE_RADAR_EXT)) { ath10k_wmi_event_dfs(ar, &phyerr_arg, tsf); ath10k_wmi_event_spectral_scan(ar, &phyerr_arg, tsf); - break; - default: - break; } phyerr = phyerr + phyerr_arg.hdr_len + buf_len; @@ -3949,6 +4268,7 @@ return; } + ar->wow.wakeup_reason = ev.wake_reason; ath10k_dbg(ar, ATH10K_DBG_WMI, "wow wakeup host reason %s\n", wow_reason(ev.wake_reason)); } @@ -4258,34 +4578,58 @@ ath10k_dbg(ar, ATH10K_DBG_WMI, "WMI_VDEV_RESUME_REQ_EVENTID\n"); } -static int ath10k_wmi_alloc_host_mem(struct ath10k *ar, u32 req_id, +static int ath10k_wmi_alloc_chunk(struct ath10k *ar, u32 req_id, u32 num_units, u32 unit_len) { dma_addr_t paddr; - u32 pool_size; + u32 pool_size = 0; int idx = ar->wmi.num_mem_chunks; + void *vaddr = NULL; - pool_size = num_units * round_up(unit_len, 4); + if (ar->wmi.num_mem_chunks == ARRAY_SIZE(ar->wmi.mem_chunks)) + return -ENOMEM; + while (!vaddr && num_units) { + pool_size = num_units * round_up(unit_len, 4); if (!pool_size) return -EINVAL; - ar->wmi.mem_chunks[idx].vaddr = dma_alloc_coherent(ar->dev, - pool_size, - &paddr, - GFP_KERNEL); - if (!ar->wmi.mem_chunks[idx].vaddr) { - ath10k_warn(ar, "failed to allocate memory chunk\n"); - return -ENOMEM; + vaddr = kzalloc(pool_size, GFP_KERNEL | __GFP_NOWARN); + if (!vaddr) + num_units /= 2; } - memset(ar->wmi.mem_chunks[idx].vaddr, 0, pool_size); + if (!num_units) + return -ENOMEM; + + paddr = dma_map_single(ar->dev, vaddr, pool_size, DMA_TO_DEVICE); + if (dma_mapping_error(ar->dev, paddr)) { + kfree(vaddr); + return -ENOMEM; + } + ar->wmi.mem_chunks[idx].vaddr = vaddr; ar->wmi.mem_chunks[idx].paddr = paddr; ar->wmi.mem_chunks[idx].len = pool_size; ar->wmi.mem_chunks[idx].req_id = req_id; ar->wmi.num_mem_chunks++; + return num_units; +} + +static int ath10k_wmi_alloc_host_mem(struct ath10k *ar, u32 req_id, + u32 num_units, u32 unit_len) +{ + int ret; + + while (num_units) { + ret = ath10k_wmi_alloc_chunk(ar, req_id, num_units, unit_len); + if (ret < 0) + return ret; + + num_units -= ret; + } + return 0; } @@ -4450,10 +4794,6 @@ ath10k_dbg_dump(ar, ATH10K_DBG_WMI, NULL, "wmi svc: ", arg.service_map, arg.service_map_len); - /* only manually set fw features when not using FW IE format */ - if (ar->fw_api == 1 && ar->fw_version_build > 636) - set_bit(ATH10K_FW_FEATURE_EXT_WMI_MGMT_RX, ar->fw_features); - if (ar->num_rf_chains > ar->max_spatial_stream) { ath10k_warn(ar, "hardware advertises support for more spatial streams than it should (%d > %d)\n", ar->num_rf_chains, ar->max_spatial_stream); @@ -4483,10 +4823,16 @@ } if (test_bit(WMI_SERVICE_PEER_CACHING, ar->wmi.svc_map)) { - ar->max_num_peers = TARGET_10_4_NUM_QCACHE_PEERS_MAX + - TARGET_10_4_NUM_VDEVS; + if (test_bit(ATH10K_FW_FEATURE_PEER_FLOW_CONTROL, + ar->running_fw->fw_file.fw_features)) + ar->num_active_peers = TARGET_10_4_QCACHE_ACTIVE_PEERS_PFC + + ar->max_num_vdevs; + else ar->num_active_peers = TARGET_10_4_QCACHE_ACTIVE_PEERS + - TARGET_10_4_NUM_VDEVS; + ar->max_num_vdevs; + + ar->max_num_peers = TARGET_10_4_NUM_QCACHE_PEERS_MAX + + ar->max_num_vdevs; ar->num_tids = ar->num_active_peers * 2; ar->max_num_stations = TARGET_10_4_NUM_QCACHE_PEERS_MAX; } @@ -4600,6 +4946,50 @@ return 0; } +static int ath10k_wmi_op_pull_echo_ev(struct ath10k *ar, + struct sk_buff *skb, + struct wmi_echo_ev_arg *arg) +{ + struct wmi_echo_event *ev = (void *)skb->data; + + arg->value = ev->value; + + return 0; +} + +void +ath10k_generate_mac_addr_auto(struct ath10k *ar, struct wmi_rdy_ev_arg *arg) +{ + unsigned int soc_serial_num; + u8 bdata_mac_addr[ETH_ALEN]; + u8 udef_mac_addr[] = {0x00, 0x0A, 0xF5, 0x00, 0x00, 0x00}; + + soc_serial_num = socinfo_get_serial_number(); + if (!soc_serial_num) + return; + + if (arg->mac_addr) { + ether_addr_copy(ar->base_mac_addr, arg->mac_addr); + ether_addr_copy(bdata_mac_addr, arg->mac_addr); + soc_serial_num &= 0x00ffffff; + bdata_mac_addr[3] = (soc_serial_num >> 16) & 0xff; + bdata_mac_addr[4] = (soc_serial_num >> 8) & 0xff; + bdata_mac_addr[5] = soc_serial_num & 0xff; + ether_addr_copy(ar->mac_addr, bdata_mac_addr); + } else { + /* If mac address not encoded in wlan board data, + * Auto-generate mac address using device serial + * number and user defined mac address 'udef_mac_addr'. + */ + udef_mac_addr[3] = (soc_serial_num >> 16) & 0xff; + udef_mac_addr[4] = (soc_serial_num >> 8) & 0xff; + udef_mac_addr[5] = soc_serial_num & 0xff; + ether_addr_copy(ar->base_mac_addr, udef_mac_addr); + udef_mac_addr[2] = (soc_serial_num >> 24) & 0xff; + ether_addr_copy(ar->mac_addr, udef_mac_addr); + } +} + int ath10k_wmi_event_ready(struct ath10k *ar, struct sk_buff *skb) { struct wmi_rdy_ev_arg arg = {}; @@ -4618,7 +5008,11 @@ arg.mac_addr, __le32_to_cpu(arg.status)); + if (QCA_REV_WCN3990(ar)) + ath10k_generate_mac_addr_auto(ar, &arg); + else ether_addr_copy(ar->mac_addr, arg.mac_addr); + complete(&ar->wmi.unified_ready); return 0; } @@ -4635,6 +5029,58 @@ return 0; } +static int ath10k_wmi_event_pdev_bss_chan_info(struct ath10k *ar, + struct sk_buff *skb) +{ + struct wmi_pdev_bss_chan_info_event *ev; + struct survey_info *survey; + u64 busy, total, tx, rx, rx_bss; + u32 freq, noise_floor; + u32 cc_freq_hz = ar->hw_params.channel_counters_freq_hz; + int idx; + + ev = (struct wmi_pdev_bss_chan_info_event *)skb->data; + if (WARN_ON(skb->len < sizeof(*ev))) + return -EPROTO; + + freq = __le32_to_cpu(ev->freq); + noise_floor = __le32_to_cpu(ev->noise_floor); + busy = __le64_to_cpu(ev->cycle_busy); + total = __le64_to_cpu(ev->cycle_total); + tx = __le64_to_cpu(ev->cycle_tx); + rx = __le64_to_cpu(ev->cycle_rx); + rx_bss = __le64_to_cpu(ev->cycle_rx_bss); + + ath10k_dbg(ar, ATH10K_DBG_WMI, + "wmi event pdev bss chan info:\n freq: %d noise: %d cycle: busy %llu total %llu tx %llu rx %llu rx_bss %llu\n", + freq, noise_floor, busy, total, tx, rx, rx_bss); + + spin_lock_bh(&ar->data_lock); + idx = freq_to_idx(ar, freq); + if (idx >= ARRAY_SIZE(ar->survey)) { + ath10k_warn(ar, "bss chan info: invalid frequency %d (idx %d out of bounds)\n", + freq, idx); + goto exit; + } + + survey = &ar->survey[idx]; + + survey->noise = noise_floor; + survey->time = div_u64(total, cc_freq_hz); + survey->time_busy = div_u64(busy, cc_freq_hz); + survey->time_rx = div_u64(rx_bss, cc_freq_hz); + survey->time_tx = div_u64(tx, cc_freq_hz); + survey->filled |= (SURVEY_INFO_NOISE_DBM | + SURVEY_INFO_TIME | + SURVEY_INFO_TIME_BUSY | + SURVEY_INFO_TIME_RX | + SURVEY_INFO_TIME_TX); +exit: + spin_unlock_bh(&ar->data_lock); + complete(&ar->bss_survey_done); + return 0; +} + static void ath10k_wmi_op_rx(struct ath10k *ar, struct sk_buff *skb) { struct wmi_cmd_hdr *cmd_hdr; @@ -4880,6 +5326,7 @@ { struct wmi_cmd_hdr *cmd_hdr; enum wmi_10_2_event_id id; + bool consumed; cmd_hdr = (struct wmi_cmd_hdr *)skb->data; id = MS(__le32_to_cpu(cmd_hdr->cmd_id), WMI_CMD_HDR_CMD_ID); @@ -4889,6 +5336,18 @@ trace_ath10k_wmi_event(ar, id, skb->data, skb->len); + consumed = ath10k_tm_event_wmi(ar, id, skb); + + /* Ready event must be handled normally also in UTF mode so that we + * know the UTF firmware has booted, others we are just bypass WMI + * events to testmode. + */ + if (consumed && id != WMI_10_2_READY_EVENTID) { + ath10k_dbg(ar, ATH10K_DBG_WMI, + "wmi testmode consumed 0x%x\n", id); + goto out; + } + switch (id) { case WMI_10_2_MGMT_RX_EVENTID: ath10k_wmi_event_mgmt_rx(ar, skb); @@ -4978,6 +5437,9 @@ case WMI_10_2_PDEV_TEMPERATURE_EVENTID: ath10k_wmi_event_temperature(ar, skb); break; + case WMI_10_2_PDEV_BSS_CHAN_INFO_EVENTID: + ath10k_wmi_event_pdev_bss_chan_info(ar, skb); + break; case WMI_10_2_RTT_KEEPALIVE_EVENTID: case WMI_10_2_GPIO_INPUT_EVENTID: case WMI_10_2_PEER_RATECODE_LIST_EVENTID: @@ -5001,6 +5463,7 @@ { struct wmi_cmd_hdr *cmd_hdr; enum wmi_10_4_event_id id; + bool consumed; cmd_hdr = (struct wmi_cmd_hdr *)skb->data; id = MS(__le32_to_cpu(cmd_hdr->cmd_id), WMI_CMD_HDR_CMD_ID); @@ -5010,6 +5473,18 @@ trace_ath10k_wmi_event(ar, id, skb->data, skb->len); + consumed = ath10k_tm_event_wmi(ar, id, skb); + + /* Ready event must be handled normally also in UTF mode so that we + * know the UTF firmware has booted, others we are just bypass WMI + * events to testmode. + */ + if (consumed && id != WMI_10_4_READY_EVENTID) { + ath10k_dbg(ar, ATH10K_DBG_WMI, + "wmi testmode consumed 0x%x\n", id); + goto out; + } + switch (id) { case WMI_10_4_MGMT_RX_EVENTID: ath10k_wmi_event_mgmt_rx(ar, skb); @@ -5039,6 +5514,9 @@ case WMI_10_4_PEER_STA_KICKOUT_EVENTID: ath10k_wmi_event_peer_sta_kickout(ar, skb); break; + case WMI_10_4_ROAM_EVENTID: + ath10k_wmi_event_roam(ar, skb); + break; case WMI_10_4_HOST_SWBA_EVENTID: ath10k_wmi_event_host_swba(ar, skb); break; @@ -5055,12 +5533,20 @@ ath10k_wmi_event_vdev_stopped(ar, skb); break; case WMI_10_4_WOW_WAKEUP_HOST_EVENTID: + case WMI_10_4_PEER_RATECODE_LIST_EVENTID: + case WMI_10_4_WDS_PEER_EVENTID: ath10k_dbg(ar, ATH10K_DBG_WMI, "received event id %d not implemented\n", id); break; case WMI_10_4_UPDATE_STATS_EVENTID: ath10k_wmi_event_update_stats(ar, skb); break; + case WMI_10_4_PDEV_TEMPERATURE_EVENTID: + ath10k_wmi_event_temperature(ar, skb); + break; + case WMI_10_4_PDEV_BSS_CHAN_INFO_EVENTID: + ath10k_wmi_event_pdev_bss_chan_info(ar, skb); + break; default: ath10k_warn(ar, "Unknown eventid: %d\n", id); break; @@ -5379,9 +5865,16 @@ u32 len, val, features; config.num_vdevs = __cpu_to_le32(TARGET_10X_NUM_VDEVS); - config.num_peers = __cpu_to_le32(TARGET_10X_NUM_PEERS); config.num_peer_keys = __cpu_to_le32(TARGET_10X_NUM_PEER_KEYS); + + if (ath10k_peer_stats_enabled(ar)) { + config.num_peers = __cpu_to_le32(TARGET_10X_TX_STATS_NUM_PEERS); + config.num_tids = __cpu_to_le32(TARGET_10X_TX_STATS_NUM_TIDS); + } else { + config.num_peers = __cpu_to_le32(TARGET_10X_NUM_PEERS); config.num_tids = __cpu_to_le32(TARGET_10X_NUM_TIDS); + } + config.ast_skid_limit = __cpu_to_le32(TARGET_10X_AST_SKID_LIMIT); config.tx_chain_mask = __cpu_to_le32(TARGET_10X_TX_CHAIN_MASK); config.rx_chain_mask = __cpu_to_le32(TARGET_10X_RX_CHAIN_MASK); @@ -5431,8 +5924,17 @@ cmd = (struct wmi_init_cmd_10_2 *)buf->data; features = WMI_10_2_RX_BATCH_MODE; - if (test_bit(WMI_SERVICE_COEX_GPIO, ar->wmi.svc_map)) + + if (test_bit(ATH10K_FLAG_BTCOEX, &ar->dev_flags) && + test_bit(WMI_SERVICE_COEX_GPIO, ar->wmi.svc_map)) features |= WMI_10_2_COEX_GPIO; + + if (ath10k_peer_stats_enabled(ar)) + features |= WMI_10_2_PEER_STATS; + + if (test_bit(WMI_SERVICE_BSS_CHANNEL_INFO_64, ar->wmi.svc_map)) + features |= WMI_10_2_BSS_CHAN_INFO; + cmd->resource_config.feature_mask = __cpu_to_le32(features); memcpy(&cmd->resource_config.common, &config, sizeof(config)); @@ -5459,8 +5961,8 @@ __cpu_to_le32(TARGET_10_4_NUM_OFFLOAD_REORDER_BUFFS); config.num_peer_keys = __cpu_to_le32(TARGET_10_4_NUM_PEER_KEYS); config.ast_skid_limit = __cpu_to_le32(TARGET_10_4_AST_SKID_LIMIT); - config.tx_chain_mask = __cpu_to_le32(TARGET_10_4_TX_CHAIN_MASK); - config.rx_chain_mask = __cpu_to_le32(TARGET_10_4_RX_CHAIN_MASK); + config.tx_chain_mask = __cpu_to_le32(ar->hw_params.tx_chain_mask); + config.rx_chain_mask = __cpu_to_le32(ar->hw_params.rx_chain_mask); config.rx_timeout_pri[0] = __cpu_to_le32(TARGET_10_4_RX_TIMEOUT_LO_PRI); config.rx_timeout_pri[1] = __cpu_to_le32(TARGET_10_4_RX_TIMEOUT_LO_PRI); @@ -5491,7 +5993,7 @@ config.vow_config = __cpu_to_le32(TARGET_10_4_VOW_CONFIG); config.gtk_offload_max_vdev = __cpu_to_le32(TARGET_10_4_GTK_OFFLOAD_MAX_VDEV); - config.num_msdu_desc = __cpu_to_le32(TARGET_10_4_NUM_MSDU_DESC); + config.num_msdu_desc = __cpu_to_le32(ar->htt.max_num_pending_tx); config.max_frag_entries = __cpu_to_le32(TARGET_10_4_11AC_TX_MAX_FRAGS); config.max_peer_ext_stats = __cpu_to_le32(TARGET_10_4_MAX_PEER_EXT_STATS); @@ -5651,9 +6153,8 @@ bssids->num_bssid = __cpu_to_le32(arg->n_bssids); for (i = 0; i < arg->n_bssids; i++) - memcpy(&bssids->bssid_list[i], - arg->bssids[i].bssid, - ETH_ALEN); + ether_addr_copy(bssids->bssid_list[i].addr, + arg->bssids[i].bssid); ptr += sizeof(*bssids); ptr += sizeof(struct wmi_mac_addr) * arg->n_bssids; @@ -5746,6 +6247,8 @@ | WMI_SCAN_EVENT_BSS_CHANNEL | WMI_SCAN_EVENT_FOREIGN_CHANNEL | WMI_SCAN_EVENT_DEQUEUED; + if (QCA_REV_WCN3990(ar)) + arg->scan_ctrl_flags = ar->fw_flags->flags; arg->scan_ctrl_flags |= WMI_SCAN_CHAN_STAT_EVENT; arg->n_bssids = 1; arg->bssids[0].bssid = "\xFF\xFF\xFF\xFF\xFF\xFF"; @@ -6328,6 +6831,16 @@ cmd->info0 = __cpu_to_le32(info0); } +static void +ath10k_wmi_peer_assoc_fill_10_4(struct ath10k *ar, void *buf, + const struct wmi_peer_assoc_complete_arg *arg) +{ + struct wmi_10_4_peer_assoc_complete_cmd *cmd = buf; + + ath10k_wmi_peer_assoc_fill_10_2(ar, buf, arg); + cmd->peer_bw_rxnss_override = 0; +} + static int ath10k_wmi_peer_assoc_check_arg(const struct wmi_peer_assoc_complete_arg *arg) { @@ -6417,6 +6930,31 @@ } static struct sk_buff * +ath10k_wmi_10_4_op_gen_peer_assoc(struct ath10k *ar, + const struct wmi_peer_assoc_complete_arg *arg) +{ + size_t len = sizeof(struct wmi_10_4_peer_assoc_complete_cmd); + struct sk_buff *skb; + int ret; + + ret = ath10k_wmi_peer_assoc_check_arg(arg); + if (ret) + return ERR_PTR(ret); + + skb = ath10k_wmi_alloc_skb(ar, len); + if (!skb) + return ERR_PTR(-ENOMEM); + + ath10k_wmi_peer_assoc_fill_10_4(ar, skb->data, arg); + + ath10k_dbg(ar, ATH10K_DBG_WMI, + "wmi peer assoc vdev %d addr %pM (%s)\n", + arg->vdev_id, arg->addr, + arg->peer_reassoc ? "reassociate" : "new"); + return skb; +} + +static struct sk_buff * ath10k_wmi_10_2_op_gen_pdev_get_temperature(struct ath10k *ar) { struct sk_buff *skb; @@ -6429,6 +6967,26 @@ return skb; } +static struct sk_buff * +ath10k_wmi_10_2_op_gen_pdev_bss_chan_info(struct ath10k *ar, + enum wmi_bss_survey_req_type type) +{ + struct wmi_pdev_chan_info_req_cmd *cmd; + struct sk_buff *skb; + + skb = ath10k_wmi_alloc_skb(ar, sizeof(*cmd)); + if (!skb) + return ERR_PTR(-ENOMEM); + + cmd = (struct wmi_pdev_chan_info_req_cmd *)skb->data; + cmd->type = __cpu_to_le32(type); + + ath10k_dbg(ar, ATH10K_DBG_WMI, + "wmi pdev bss info request type %d\n", type); + + return skb; +} + /* This function assumes the beacon is already DMA mapped */ static struct sk_buff * ath10k_wmi_op_gen_beacon_dma(struct ath10k *ar, u32 vdev_id, const void *bcn, @@ -6536,7 +7094,7 @@ } static struct sk_buff * -ath10k_wmi_op_gen_dbglog_cfg(struct ath10k *ar, u32 module_enable, +ath10k_wmi_op_gen_dbglog_cfg(struct ath10k *ar, u64 module_enable, u32 log_level) { struct wmi_dbglog_cfg_cmd *cmd; @@ -6574,6 +7132,44 @@ } static struct sk_buff * +ath10k_wmi_10_4_op_gen_dbglog_cfg(struct ath10k *ar, u64 module_enable, + u32 log_level) +{ + struct wmi_10_4_dbglog_cfg_cmd *cmd; + struct sk_buff *skb; + u32 cfg; + + skb = ath10k_wmi_alloc_skb(ar, sizeof(*cmd)); + if (!skb) + return ERR_PTR(-ENOMEM); + + cmd = (struct wmi_10_4_dbglog_cfg_cmd *)skb->data; + + if (module_enable) { + cfg = SM(log_level, + ATH10K_DBGLOG_CFG_LOG_LVL); + } else { + /* set back defaults, all modules with WARN level */ + cfg = SM(ATH10K_DBGLOG_LEVEL_WARN, + ATH10K_DBGLOG_CFG_LOG_LVL); + module_enable = ~0; + } + + cmd->module_enable = __cpu_to_le64(module_enable); + cmd->module_valid = __cpu_to_le64(~0); + cmd->config_enable = __cpu_to_le32(cfg); + cmd->config_valid = __cpu_to_le32(ATH10K_DBGLOG_CFG_LOG_LVL_MASK); + + ath10k_dbg(ar, ATH10K_DBG_WMI, + "wmi dbglog cfg modules 0x%016llx 0x%016llx config %08x %08x\n", + __le64_to_cpu(cmd->module_enable), + __le64_to_cpu(cmd->module_valid), + __le32_to_cpu(cmd->config_enable), + __le32_to_cpu(cmd->config_valid)); + return skb; +} + +static struct sk_buff * ath10k_wmi_op_gen_pktlog_enable(struct ath10k *ar, u32 ev_bitmap) { struct wmi_pdev_pktlog_enable_cmd *cmd; @@ -7007,6 +7603,9 @@ "Peer TX rate", peer->peer_tx_rate); len += scnprintf(buf + len, buf_len - len, "%30s %u\n", "Peer RX rate", peer->peer_rx_rate); + len += scnprintf(buf + len, buf_len - len, "%30s %u\n", + "Peer RX duration", peer->rx_duration); + len += scnprintf(buf + len, buf_len - len, "\n"); *length = len; } @@ -7232,6 +7831,135 @@ buf[len] = 0; } +int ath10k_wmi_op_get_vdev_subtype(struct ath10k *ar, + enum wmi_vdev_subtype subtype) +{ + switch (subtype) { + case WMI_VDEV_SUBTYPE_NONE: + return WMI_VDEV_SUBTYPE_LEGACY_NONE; + case WMI_VDEV_SUBTYPE_P2P_DEVICE: + return WMI_VDEV_SUBTYPE_LEGACY_P2P_DEV; + case WMI_VDEV_SUBTYPE_P2P_CLIENT: + return WMI_VDEV_SUBTYPE_LEGACY_P2P_CLI; + case WMI_VDEV_SUBTYPE_P2P_GO: + return WMI_VDEV_SUBTYPE_LEGACY_P2P_GO; + case WMI_VDEV_SUBTYPE_PROXY_STA: + return WMI_VDEV_SUBTYPE_LEGACY_PROXY_STA; + case WMI_VDEV_SUBTYPE_MESH_11S: + case WMI_VDEV_SUBTYPE_MESH_NON_11S: + return -ENOTSUPP; + } + return -ENOTSUPP; +} + +static int ath10k_wmi_10_2_4_op_get_vdev_subtype(struct ath10k *ar, + enum wmi_vdev_subtype subtype) +{ + switch (subtype) { + case WMI_VDEV_SUBTYPE_NONE: + return WMI_VDEV_SUBTYPE_10_2_4_NONE; + case WMI_VDEV_SUBTYPE_P2P_DEVICE: + return WMI_VDEV_SUBTYPE_10_2_4_P2P_DEV; + case WMI_VDEV_SUBTYPE_P2P_CLIENT: + return WMI_VDEV_SUBTYPE_10_2_4_P2P_CLI; + case WMI_VDEV_SUBTYPE_P2P_GO: + return WMI_VDEV_SUBTYPE_10_2_4_P2P_GO; + case WMI_VDEV_SUBTYPE_PROXY_STA: + return WMI_VDEV_SUBTYPE_10_2_4_PROXY_STA; + case WMI_VDEV_SUBTYPE_MESH_11S: + return WMI_VDEV_SUBTYPE_10_2_4_MESH_11S; + case WMI_VDEV_SUBTYPE_MESH_NON_11S: + return -ENOTSUPP; + } + return -ENOTSUPP; +} + +static int ath10k_wmi_10_4_op_get_vdev_subtype(struct ath10k *ar, + enum wmi_vdev_subtype subtype) +{ + switch (subtype) { + case WMI_VDEV_SUBTYPE_NONE: + return WMI_VDEV_SUBTYPE_10_4_NONE; + case WMI_VDEV_SUBTYPE_P2P_DEVICE: + return WMI_VDEV_SUBTYPE_10_4_P2P_DEV; + case WMI_VDEV_SUBTYPE_P2P_CLIENT: + return WMI_VDEV_SUBTYPE_10_4_P2P_CLI; + case WMI_VDEV_SUBTYPE_P2P_GO: + return WMI_VDEV_SUBTYPE_10_4_P2P_GO; + case WMI_VDEV_SUBTYPE_PROXY_STA: + return WMI_VDEV_SUBTYPE_10_4_PROXY_STA; + case WMI_VDEV_SUBTYPE_MESH_11S: + return WMI_VDEV_SUBTYPE_10_4_MESH_11S; + case WMI_VDEV_SUBTYPE_MESH_NON_11S: + return WMI_VDEV_SUBTYPE_10_4_MESH_NON_11S; + } + return -ENOTSUPP; +} + +static struct sk_buff * +ath10k_wmi_10_4_ext_resource_config(struct ath10k *ar, + enum wmi_host_platform_type type, + u32 fw_feature_bitmap) +{ + struct wmi_ext_resource_config_10_4_cmd *cmd; + struct sk_buff *skb; + + skb = ath10k_wmi_alloc_skb(ar, sizeof(*cmd)); + if (!skb) + return ERR_PTR(-ENOMEM); + + cmd = (struct wmi_ext_resource_config_10_4_cmd *)skb->data; + cmd->host_platform_config = __cpu_to_le32(type); + cmd->fw_feature_bitmap = __cpu_to_le32(fw_feature_bitmap); + + ath10k_dbg(ar, ATH10K_DBG_WMI, + "wmi ext resource config host type %d firmware feature bitmap %08x\n", + type, fw_feature_bitmap); + return skb; +} + +static struct sk_buff * +ath10k_wmi_op_gen_echo(struct ath10k *ar, u32 value) +{ + struct wmi_echo_cmd *cmd; + struct sk_buff *skb; + + skb = ath10k_wmi_alloc_skb(ar, sizeof(*cmd)); + if (!skb) + return ERR_PTR(-ENOMEM); + + cmd = (struct wmi_echo_cmd *)skb->data; + cmd->value = cpu_to_le32(value); + + ath10k_dbg(ar, ATH10K_DBG_WMI, + "wmi echo value 0x%08x\n", value); + return skb; +} + +int +ath10k_wmi_barrier(struct ath10k *ar) +{ + int ret; + int time_left; + + spin_lock_bh(&ar->data_lock); + reinit_completion(&ar->wmi.barrier); + spin_unlock_bh(&ar->data_lock); + + ret = ath10k_wmi_echo(ar, ATH10K_WMI_BARRIER_ECHO_ID); + if (ret) { + ath10k_warn(ar, "failed to submit wmi echo: %d\n", ret); + return ret; + } + + time_left = wait_for_completion_timeout(&ar->wmi.barrier, + ATH10K_WMI_BARRIER_TIMEOUT_HZ); + if (!time_left) + return -ETIMEDOUT; + + return 0; +} + static const struct wmi_ops wmi_ops = { .rx = ath10k_wmi_op_rx, .map_svc = wmi_main_svc_map, @@ -7248,6 +7976,7 @@ .pull_rdy = ath10k_wmi_op_pull_rdy_ev, .pull_fw_stats = ath10k_wmi_main_op_pull_fw_stats, .pull_roam_ev = ath10k_wmi_op_pull_roam_ev, + .pull_echo_ev = ath10k_wmi_op_pull_echo_ev, .gen_pdev_suspend = ath10k_wmi_op_gen_pdev_suspend, .gen_pdev_resume = ath10k_wmi_op_gen_pdev_resume, @@ -7291,6 +8020,8 @@ .gen_addba_set_resp = ath10k_wmi_op_gen_addba_set_resp, .gen_delba_send = ath10k_wmi_op_gen_delba_send, .fw_stats_fill = ath10k_wmi_main_op_fw_stats_fill, + .get_vdev_subtype = ath10k_wmi_op_get_vdev_subtype, + .gen_echo = ath10k_wmi_op_gen_echo, /* .gen_bcn_tmpl not implemented */ /* .gen_prb_tmpl not implemented */ /* .gen_p2p_go_bcn_ie not implemented */ @@ -7320,6 +8051,7 @@ .pull_phyerr = ath10k_wmi_op_pull_phyerr_ev, .pull_rdy = ath10k_wmi_op_pull_rdy_ev, .pull_roam_ev = ath10k_wmi_op_pull_roam_ev, + .pull_echo_ev = ath10k_wmi_op_pull_echo_ev, .gen_pdev_suspend = ath10k_wmi_op_gen_pdev_suspend, .gen_pdev_resume = ath10k_wmi_op_gen_pdev_resume, @@ -7358,6 +8090,8 @@ .gen_addba_set_resp = ath10k_wmi_op_gen_addba_set_resp, .gen_delba_send = ath10k_wmi_op_gen_delba_send, .fw_stats_fill = ath10k_wmi_10x_op_fw_stats_fill, + .get_vdev_subtype = ath10k_wmi_op_get_vdev_subtype, + .gen_echo = ath10k_wmi_op_gen_echo, /* .gen_bcn_tmpl not implemented */ /* .gen_prb_tmpl not implemented */ /* .gen_p2p_go_bcn_ie not implemented */ @@ -7377,6 +8111,7 @@ .pull_svc_rdy = ath10k_wmi_10x_op_pull_svc_rdy_ev, .gen_pdev_set_rd = ath10k_wmi_10x_op_gen_pdev_set_rd, .gen_start_scan = ath10k_wmi_10x_op_gen_start_scan, + .gen_echo = ath10k_wmi_op_gen_echo, .pull_scan = ath10k_wmi_op_pull_scan_ev, .pull_mgmt_rx = ath10k_wmi_op_pull_mgmt_rx_ev, @@ -7388,6 +8123,7 @@ .pull_phyerr = ath10k_wmi_op_pull_phyerr_ev, .pull_rdy = ath10k_wmi_op_pull_rdy_ev, .pull_roam_ev = ath10k_wmi_op_pull_roam_ev, + .pull_echo_ev = ath10k_wmi_op_pull_echo_ev, .gen_pdev_suspend = ath10k_wmi_op_gen_pdev_suspend, .gen_pdev_resume = ath10k_wmi_op_gen_pdev_resume, @@ -7426,6 +8162,7 @@ .gen_addba_set_resp = ath10k_wmi_op_gen_addba_set_resp, .gen_delba_send = ath10k_wmi_op_gen_delba_send, .fw_stats_fill = ath10k_wmi_10x_op_fw_stats_fill, + .get_vdev_subtype = ath10k_wmi_op_get_vdev_subtype, /* .gen_pdev_enable_adaptive_cca not implemented */ }; @@ -7435,23 +8172,26 @@ .gen_init = ath10k_wmi_10_2_op_gen_init, .gen_peer_assoc = ath10k_wmi_10_2_op_gen_peer_assoc, .gen_pdev_get_temperature = ath10k_wmi_10_2_op_gen_pdev_get_temperature, + .gen_pdev_bss_chan_info_req = ath10k_wmi_10_2_op_gen_pdev_bss_chan_info, /* shared with 10.1 */ .map_svc = wmi_10x_svc_map, .pull_svc_rdy = ath10k_wmi_10x_op_pull_svc_rdy_ev, .gen_pdev_set_rd = ath10k_wmi_10x_op_gen_pdev_set_rd, .gen_start_scan = ath10k_wmi_10x_op_gen_start_scan, + .gen_echo = ath10k_wmi_op_gen_echo, .pull_scan = ath10k_wmi_op_pull_scan_ev, .pull_mgmt_rx = ath10k_wmi_op_pull_mgmt_rx_ev, .pull_ch_info = ath10k_wmi_op_pull_ch_info_ev, .pull_vdev_start = ath10k_wmi_op_pull_vdev_start_ev, .pull_peer_kick = ath10k_wmi_op_pull_peer_kick_ev, - .pull_swba = ath10k_wmi_op_pull_swba_ev, + .pull_swba = ath10k_wmi_10_2_4_op_pull_swba_ev, .pull_phyerr_hdr = ath10k_wmi_op_pull_phyerr_ev_hdr, .pull_phyerr = ath10k_wmi_op_pull_phyerr_ev, .pull_rdy = ath10k_wmi_op_pull_rdy_ev, .pull_roam_ev = ath10k_wmi_op_pull_roam_ev, + .pull_echo_ev = ath10k_wmi_op_pull_echo_ev, .gen_pdev_suspend = ath10k_wmi_op_gen_pdev_suspend, .gen_pdev_resume = ath10k_wmi_op_gen_pdev_resume, @@ -7492,6 +8232,7 @@ .fw_stats_fill = ath10k_wmi_10x_op_fw_stats_fill, .gen_pdev_enable_adaptive_cca = ath10k_wmi_op_gen_pdev_enable_adaptive_cca, + .get_vdev_subtype = ath10k_wmi_10_2_4_op_get_vdev_subtype, /* .gen_bcn_tmpl not implemented */ /* .gen_prb_tmpl not implemented */ /* .gen_p2p_go_bcn_ie not implemented */ @@ -7513,6 +8254,7 @@ .pull_phyerr = ath10k_wmi_10_4_op_pull_phyerr_ev, .pull_svc_rdy = ath10k_wmi_main_op_pull_svc_rdy_ev, .pull_rdy = ath10k_wmi_op_pull_rdy_ev, + .pull_roam_ev = ath10k_wmi_op_pull_roam_ev, .get_txbf_conf_scheme = ath10k_wmi_10_4_txbf_conf_scheme, .gen_pdev_suspend = ath10k_wmi_op_gen_pdev_suspend, @@ -7536,6 +8278,7 @@ .gen_peer_delete = ath10k_wmi_op_gen_peer_delete, .gen_peer_flush = ath10k_wmi_op_gen_peer_flush, .gen_peer_set_param = ath10k_wmi_op_gen_peer_set_param, + .gen_peer_assoc = ath10k_wmi_10_4_op_gen_peer_assoc, .gen_set_psmode = ath10k_wmi_op_gen_set_psmode, .gen_set_sta_ps = ath10k_wmi_op_gen_set_sta_ps, .gen_set_ap_ps = ath10k_wmi_op_gen_set_ap_ps, @@ -7544,7 +8287,7 @@ .gen_pdev_set_wmm = ath10k_wmi_op_gen_pdev_set_wmm, .gen_force_fw_hang = ath10k_wmi_op_gen_force_fw_hang, .gen_mgmt_tx = ath10k_wmi_op_gen_mgmt_tx, - .gen_dbglog_cfg = ath10k_wmi_op_gen_dbglog_cfg, + .gen_dbglog_cfg = ath10k_wmi_10_4_op_gen_dbglog_cfg, .gen_pktlog_enable = ath10k_wmi_op_gen_pktlog_enable, .gen_pktlog_disable = ath10k_wmi_op_gen_pktlog_disable, .gen_pdev_set_quiet_mode = ath10k_wmi_op_gen_pdev_set_quiet_mode, @@ -7553,44 +8296,54 @@ .gen_addba_set_resp = ath10k_wmi_op_gen_addba_set_resp, .gen_delba_send = ath10k_wmi_op_gen_delba_send, .fw_stats_fill = ath10k_wmi_10_4_op_fw_stats_fill, + .ext_resource_config = ath10k_wmi_10_4_ext_resource_config, /* shared with 10.2 */ - .gen_peer_assoc = ath10k_wmi_10_2_op_gen_peer_assoc, + .pull_echo_ev = ath10k_wmi_op_pull_echo_ev, .gen_request_stats = ath10k_wmi_op_gen_request_stats, + .gen_pdev_get_temperature = ath10k_wmi_10_2_op_gen_pdev_get_temperature, + .get_vdev_subtype = ath10k_wmi_10_4_op_get_vdev_subtype, + .gen_pdev_bss_chan_info_req = ath10k_wmi_10_2_op_gen_pdev_bss_chan_info, + .gen_echo = ath10k_wmi_op_gen_echo, }; int ath10k_wmi_attach(struct ath10k *ar) { - switch (ar->wmi.op_version) { + switch (ar->running_fw->fw_file.wmi_op_version) { case ATH10K_FW_WMI_OP_VERSION_10_4: ar->wmi.ops = &wmi_10_4_ops; ar->wmi.cmd = &wmi_10_4_cmd_map; ar->wmi.vdev_param = &wmi_10_4_vdev_param_map; ar->wmi.pdev_param = &wmi_10_4_pdev_param_map; + ar->wmi.peer_flags = &wmi_10_2_peer_flags_map; break; case ATH10K_FW_WMI_OP_VERSION_10_2_4: ar->wmi.cmd = &wmi_10_2_4_cmd_map; ar->wmi.ops = &wmi_10_2_4_ops; ar->wmi.vdev_param = &wmi_10_2_4_vdev_param_map; ar->wmi.pdev_param = &wmi_10_2_4_pdev_param_map; + ar->wmi.peer_flags = &wmi_10_2_peer_flags_map; break; case ATH10K_FW_WMI_OP_VERSION_10_2: ar->wmi.cmd = &wmi_10_2_cmd_map; ar->wmi.ops = &wmi_10_2_ops; ar->wmi.vdev_param = &wmi_10x_vdev_param_map; ar->wmi.pdev_param = &wmi_10x_pdev_param_map; + ar->wmi.peer_flags = &wmi_10_2_peer_flags_map; break; case ATH10K_FW_WMI_OP_VERSION_10_1: ar->wmi.cmd = &wmi_10x_cmd_map; ar->wmi.ops = &wmi_10_1_ops; ar->wmi.vdev_param = &wmi_10x_vdev_param_map; ar->wmi.pdev_param = &wmi_10x_pdev_param_map; + ar->wmi.peer_flags = &wmi_10x_peer_flags_map; break; case ATH10K_FW_WMI_OP_VERSION_MAIN: ar->wmi.cmd = &wmi_cmd_map; ar->wmi.ops = &wmi_ops; ar->wmi.vdev_param = &wmi_vdev_param_map; ar->wmi.pdev_param = &wmi_pdev_param_map; + ar->wmi.peer_flags = &wmi_peer_flags_map; break; case ATH10K_FW_WMI_OP_VERSION_TLV: ath10k_wmi_tlv_attach(ar); @@ -7598,15 +8351,21 @@ case ATH10K_FW_WMI_OP_VERSION_UNSET: case ATH10K_FW_WMI_OP_VERSION_MAX: ath10k_err(ar, "unsupported WMI op version: %d\n", - ar->wmi.op_version); + ar->running_fw->fw_file.wmi_op_version); return -EINVAL; } init_completion(&ar->wmi.service_ready); init_completion(&ar->wmi.unified_ready); + init_completion(&ar->wmi.barrier); INIT_WORK(&ar->svc_rdy_work, ath10k_wmi_event_service_ready_work); + if (QCA_REV_WCN3990(ar)) { + spin_lock_init(&ar->wmi.mgmt_tx_lock); + idr_init(&ar->wmi.mgmt_pending_tx); + } + return 0; } @@ -7616,17 +8375,42 @@ /* free the host memory chunks requested by firmware */ for (i = 0; i < ar->wmi.num_mem_chunks; i++) { - dma_free_coherent(ar->dev, + dma_unmap_single(ar->dev, + ar->wmi.mem_chunks[i].paddr, ar->wmi.mem_chunks[i].len, - ar->wmi.mem_chunks[i].vaddr, - ar->wmi.mem_chunks[i].paddr); + DMA_TO_DEVICE); + kfree(ar->wmi.mem_chunks[i].vaddr); } ar->wmi.num_mem_chunks = 0; } +static int ath10k_wmi_mgmt_tx_clean_up_pending(int msdu_id, void *ptr, + void *ctx) +{ + struct ath10k_mgmt_tx_pkt_addr *pkt_addr = ptr; + struct ath10k *ar = ctx; + struct sk_buff *msdu; + + ath10k_dbg(ar, ATH10K_DBG_WMI, + "force cleanup mgmt msdu_id %hu\n", msdu_id); + + msdu = pkt_addr->vaddr; + dma_unmap_single(ar->dev, pkt_addr->paddr, + msdu->len, DMA_FROM_DEVICE); + ieee80211_free_txskb(ar->hw, msdu); + + return 0; +} + void ath10k_wmi_detach(struct ath10k *ar) { + if (QCA_REV_WCN3990(ar)) { + idr_for_each(&ar->wmi.mgmt_pending_tx, + ath10k_wmi_mgmt_tx_clean_up_pending, ar); + idr_destroy(&ar->wmi.mgmt_pending_tx); + } + cancel_work_sync(&ar->svc_rdy_work); if (ar->svc_rdy_skb) diff -ruw linux-4.4.115/drivers/net/wireless/ath/ath10k/wmi.h linux-4.4.115-fbx/drivers/net/wireless/ath/ath10k/wmi.h --- linux-4.4.115/drivers/net/wireless/ath/ath10k/wmi.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/net/wireless/ath/ath10k/wmi.h 2019-10-29 09:26:24.465211222 +0100 @@ -1,6 +1,6 @@ /* * Copyright (c) 2005-2011 Atheros Communications Inc. - * Copyright (c) 2011-2013 Qualcomm Atheros, Inc. + * Copyright (c) 2011-2013, 2017 Qualcomm Atheros, Inc. * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above @@ -20,6 +20,9 @@ #include #include +#include +#include +#include /* * This file specifies the WMI interface for the Unified Software @@ -55,7 +58,7 @@ * type. * * 6. Comment each parameter part of the WMI command/event structure by - * using the 2 stars at the begining of C comment instead of one star to + * using the 2 stars at the beginning of C comment instead of one star to * enable HTML document generation using Doxygen. * */ @@ -175,6 +178,16 @@ WMI_SERVICE_AUX_SPECTRAL_INTF, WMI_SERVICE_AUX_CHAN_LOAD_INTF, WMI_SERVICE_BSS_CHANNEL_INFO_64, + WMI_SERVICE_EXT_RES_CFG_SUPPORT, + WMI_SERVICE_MESH_11S, + WMI_SERVICE_MESH_NON_11S, + WMI_SERVICE_PEER_STATS, + WMI_SERVICE_RESTRT_CHNL_SUPPORT, + WMI_SERVICE_PERIODIC_CHAN_STAT_SUPPORT, + WMI_SERVICE_TX_MODE_PUSH_ONLY, + WMI_SERVICE_TX_MODE_PUSH_PULL, + WMI_SERVICE_TX_MODE_DYNAMIC, + WMI_SERVICE_MGMT_TX_WMI, /* keep last */ WMI_SERVICE_MAX, @@ -206,6 +219,12 @@ WMI_10X_SERVICE_SMART_ANTENNA_HW_SUPPORT, WMI_10X_SERVICE_ATF, WMI_10X_SERVICE_COEX_GPIO, + WMI_10X_SERVICE_AUX_SPECTRAL_INTF, + WMI_10X_SERVICE_AUX_CHAN_LOAD_INTF, + WMI_10X_SERVICE_BSS_CHANNEL_INFO_64, + WMI_10X_SERVICE_MESH, + WMI_10X_SERVICE_EXT_RES_CFG_SUPPORT, + WMI_10X_SERVICE_PEER_STATS, }; enum wmi_main_service { @@ -286,6 +305,15 @@ WMI_10_4_SERVICE_AUX_SPECTRAL_INTF, WMI_10_4_SERVICE_AUX_CHAN_LOAD_INTF, WMI_10_4_SERVICE_BSS_CHANNEL_INFO_64, + WMI_10_4_SERVICE_EXT_RES_CFG_SUPPORT, + WMI_10_4_SERVICE_MESH_NON_11S, + WMI_10_4_SERVICE_RESTRT_CHNL_SUPPORT, + WMI_10_4_SERVICE_PEER_STATS, + WMI_10_4_SERVICE_MESH_11S, + WMI_10_4_SERVICE_PERIODIC_CHAN_STAT_SUPPORT, + WMI_10_4_SERVICE_TX_MODE_PUSH_ONLY, + WMI_10_4_SERVICE_TX_MODE_PUSH_PULL, + WMI_10_4_SERVICE_TX_MODE_DYNAMIC, }; static inline char *wmi_service_name(int service_id) @@ -375,6 +403,15 @@ SVCSTR(WMI_SERVICE_AUX_SPECTRAL_INTF); SVCSTR(WMI_SERVICE_AUX_CHAN_LOAD_INTF); SVCSTR(WMI_SERVICE_BSS_CHANNEL_INFO_64); + SVCSTR(WMI_SERVICE_EXT_RES_CFG_SUPPORT); + SVCSTR(WMI_SERVICE_MESH_11S); + SVCSTR(WMI_SERVICE_MESH_NON_11S); + SVCSTR(WMI_SERVICE_PEER_STATS); + SVCSTR(WMI_SERVICE_RESTRT_CHNL_SUPPORT); + SVCSTR(WMI_SERVICE_PERIODIC_CHAN_STAT_SUPPORT); + SVCSTR(WMI_SERVICE_TX_MODE_PUSH_ONLY); + SVCSTR(WMI_SERVICE_TX_MODE_PUSH_PULL); + SVCSTR(WMI_SERVICE_TX_MODE_DYNAMIC); default: return NULL; } @@ -442,6 +479,18 @@ WMI_SERVICE_ATF, len); SVCMAP(WMI_10X_SERVICE_COEX_GPIO, WMI_SERVICE_COEX_GPIO, len); + SVCMAP(WMI_10X_SERVICE_AUX_SPECTRAL_INTF, + WMI_SERVICE_AUX_SPECTRAL_INTF, len); + SVCMAP(WMI_10X_SERVICE_AUX_CHAN_LOAD_INTF, + WMI_SERVICE_AUX_CHAN_LOAD_INTF, len); + SVCMAP(WMI_10X_SERVICE_BSS_CHANNEL_INFO_64, + WMI_SERVICE_BSS_CHANNEL_INFO_64, len); + SVCMAP(WMI_10X_SERVICE_MESH, + WMI_SERVICE_MESH_11S, len); + SVCMAP(WMI_10X_SERVICE_EXT_RES_CFG_SUPPORT, + WMI_SERVICE_EXT_RES_CFG_SUPPORT, len); + SVCMAP(WMI_10X_SERVICE_PEER_STATS, + WMI_SERVICE_PEER_STATS, len); } static inline void wmi_main_svc_map(const __le32 *in, unsigned long *out, @@ -600,6 +649,24 @@ WMI_SERVICE_AUX_CHAN_LOAD_INTF, len); SVCMAP(WMI_10_4_SERVICE_BSS_CHANNEL_INFO_64, WMI_SERVICE_BSS_CHANNEL_INFO_64, len); + SVCMAP(WMI_10_4_SERVICE_EXT_RES_CFG_SUPPORT, + WMI_SERVICE_EXT_RES_CFG_SUPPORT, len); + SVCMAP(WMI_10_4_SERVICE_MESH_NON_11S, + WMI_SERVICE_MESH_NON_11S, len); + SVCMAP(WMI_10_4_SERVICE_RESTRT_CHNL_SUPPORT, + WMI_SERVICE_RESTRT_CHNL_SUPPORT, len); + SVCMAP(WMI_10_4_SERVICE_PEER_STATS, + WMI_SERVICE_PEER_STATS, len); + SVCMAP(WMI_10_4_SERVICE_MESH_11S, + WMI_SERVICE_MESH_11S, len); + SVCMAP(WMI_10_4_SERVICE_PERIODIC_CHAN_STAT_SUPPORT, + WMI_SERVICE_PERIODIC_CHAN_STAT_SUPPORT, len); + SVCMAP(WMI_10_4_SERVICE_TX_MODE_PUSH_ONLY, + WMI_SERVICE_TX_MODE_PUSH_ONLY, len); + SVCMAP(WMI_10_4_SERVICE_TX_MODE_PUSH_PULL, + WMI_SERVICE_TX_MODE_PUSH_PULL, len); + SVCMAP(WMI_10_4_SERVICE_TX_MODE_DYNAMIC, + WMI_SERVICE_TX_MODE_DYNAMIC, len); } #undef SVCMAP @@ -657,6 +724,7 @@ u32 bcn_filter_rx_cmdid; u32 prb_req_filter_rx_cmdid; u32 mgmt_tx_cmdid; + u32 mgmt_tx_send_cmdid; u32 prb_tmpl_cmdid; u32 addba_clear_resp_cmdid; u32 addba_send_cmdid; @@ -773,6 +841,7 @@ u32 set_cca_params_cmdid; u32 pdev_bss_chan_info_request_cmdid; u32 pdev_enable_adaptive_cca_cmdid; + u32 ext_resource_cfg_cmdid; }; /* @@ -1385,6 +1454,7 @@ WMI_10_2_MU_CAL_START_CMDID, WMI_10_2_SET_LTEU_CONFIG_CMDID, WMI_10_2_SET_CCA_PARAMS, + WMI_10_2_PDEV_BSS_CHAN_INFO_REQUEST_CMDID, WMI_10_2_PDEV_UTF_CMDID = WMI_10_2_END_CMDID - 1, }; @@ -1428,6 +1498,8 @@ WMI_10_2_WDS_PEER_EVENTID, WMI_10_2_PEER_STA_PS_STATECHG_EVENTID, WMI_10_2_PDEV_TEMPERATURE_EVENTID, + WMI_10_2_MU_REPORT_EVENTID, + WMI_10_2_PDEV_BSS_CHAN_INFO_EVENTID, WMI_10_2_PDEV_UTF_EVENTID = WMI_10_2_END_EVENTID - 1, }; @@ -1576,6 +1648,9 @@ WMI_10_4_MU_CAL_START_CMDID, WMI_10_4_SET_CCA_PARAMS_CMDID, WMI_10_4_PDEV_BSS_CHAN_INFO_REQUEST_CMDID, + WMI_10_4_EXT_RESOURCE_CFG_CMDID, + WMI_10_4_VDEV_SET_IE_CMDID, + WMI_10_4_SET_LTEU_CONFIG_CMDID, WMI_10_4_PDEV_UTF_CMDID = WMI_10_4_END_CMDID - 1, }; @@ -1638,6 +1713,7 @@ WMI_10_4_PDEV_TEMPERATURE_EVENTID, WMI_10_4_PDEV_NFCAL_POWER_ALL_CHANNELS_EVENTID, WMI_10_4_PDEV_BSS_CHAN_INFO_EVENTID, + WMI_10_4_MU_REPORT_EVENTID, WMI_10_4_PDEV_UTF_EVENTID = WMI_10_4_END_EVENTID - 1, }; @@ -1732,6 +1808,7 @@ __le32 reginfo1; struct { u8 antenna_max; + u8 max_tx_power; } __packed; } __packed; } __packed; @@ -1771,7 +1848,6 @@ #define WMI_CHANNEL_CHANGE_CAUSE_CSA (1 << 13) #define WMI_MAX_SPATIAL_STREAM 3 /* default max ss */ -#define WMI_10_4_MAX_SPATIAL_STREAM 4 /* HT Capabilities*/ #define WMI_HT_CAP_ENABLED 0x0001 /* HT Enabled/ disabled */ @@ -2016,7 +2092,7 @@ * In offload mode target supports features like WOW, chatter and * other protocol offloads. In order to support them some * functionalities like reorder buffering, PN checking need to be - * done in target. This determines maximum number of peers suported + * done in target. This determines maximum number of peers supported * by target in offload mode */ __le32 num_offload_peers; @@ -2197,7 +2273,7 @@ * Max. number of Tx fragments per MSDU * This parameter controls the max number of Tx fragments per MSDU. * This is sent by the target as part of the WMI_SERVICE_READY event - * and is overriden by the OS shim as required. + * and is overridden by the OS shim as required. */ __le32 max_frag_entries; } __packed; @@ -2379,7 +2455,7 @@ * Max. number of Tx fragments per MSDU * This parameter controls the max number of Tx fragments per MSDU. * This is sent by the target as part of the WMI_SERVICE_READY event - * and is overriden by the OS shim as required. + * and is overridden by the OS shim as required. */ __le32 max_frag_entries; } __packed; @@ -2388,6 +2464,8 @@ WMI_10_2_RX_BATCH_MODE = BIT(0), WMI_10_2_ATF_CONFIG = BIT(1), WMI_10_2_COEX_GPIO = BIT(3), + WMI_10_2_BSS_CHAN_INFO = BIT(6), + WMI_10_2_PEER_STATS = BIT(7), }; struct wmi_resource_config_10_2 { @@ -2613,13 +2691,43 @@ */ __le32 iphdr_pad_config; - /* qwrap configuration + /* qwrap configuration (bits 15-0) * 1 - This is qwrap configuration * 0 - This is not qwrap + * + * Bits 31-16 is alloc_frag_desc_for_data_pkt (1 enables, 0 disables) + * In order to get ack-RSSI reporting and to specify the tx-rate for + * individual frames, this option must be enabled. This uses an extra + * 4 bytes per tx-msdu descriptor, so don't enable it unless you need it. */ __le32 qwrap_config; } __packed; +/** + * enum wmi_10_4_feature_mask - WMI 10.4 feature enable/disable flags + * @WMI_10_4_LTEU_SUPPORT: LTEU config + * @WMI_10_4_COEX_GPIO_SUPPORT: COEX GPIO config + * @WMI_10_4_AUX_RADIO_SPECTRAL_INTF: AUX Radio Enhancement for spectral scan + * @WMI_10_4_AUX_RADIO_CHAN_LOAD_INTF: AUX Radio Enhancement for chan load scan + * @WMI_10_4_BSS_CHANNEL_INFO_64: BSS channel info stats + * @WMI_10_4_PEER_STATS: Per station stats + */ +enum wmi_10_4_feature_mask { + WMI_10_4_LTEU_SUPPORT = BIT(0), + WMI_10_4_COEX_GPIO_SUPPORT = BIT(1), + WMI_10_4_AUX_RADIO_SPECTRAL_INTF = BIT(2), + WMI_10_4_AUX_RADIO_CHAN_LOAD_INTF = BIT(3), + WMI_10_4_BSS_CHANNEL_INFO_64 = BIT(4), + WMI_10_4_PEER_STATS = BIT(5), +}; + +struct wmi_ext_resource_config_10_4_cmd { + /* contains enum wmi_host_platform_type */ + __le32 host_platform_config; + /* see enum wmi_10_4_feature_mask */ + __le32 fw_feature_bitmap; +}; + /* strucutre describing host memory chunk. */ struct host_memory_chunk { /* id of the request that is passed up in service ready */ @@ -2641,7 +2749,7 @@ struct wmi_host_mem_chunks mem_chunks; } __packed; -/* _10x stucture is from 10.X FW API */ +/* _10x structure is from 10.X FW API */ struct wmi_init_cmd_10x { struct wmi_resource_config_10x resource_config; struct wmi_host_mem_chunks mem_chunks; @@ -2779,6 +2887,66 @@ __le32 scan_ctrl_flags; } __packed; +/* ARP-NS offload data structure */ +#define WMI_NS_ARP_OFFLOAD 2 +#define WMI_ARP_NS_OFF_FLAGS_VALID BIT(0) +#define WMI_IPV4_ARP_REPLY_OFFLOAD 0 +#define WMI_ARP_NS_OFFLOAD_DISABLE 0 +#define WMI_ARP_NS_OFFLOAD_ENABLE 1 +#define WMI_NSOFF_IPV6_ANYCAST BIT(3) + +struct wmi_ns_offload_info { + struct in6_addr src_addr; + struct in6_addr self_addr[TARGET_NUM_STATIONS]; + struct in6_addr target_addr[TARGET_NUM_STATIONS]; + struct wmi_mac_addr self_macaddr; + u8 src_ipv6_addr_valid; + struct in6_addr target_addr_valid; + struct in6_addr target_ipv6_ac; + u8 slot_idx; +} __packed; + +struct wmi_ns_arp_offload_req { + u8 offload_type; + u8 enable_offload; + __le32 num_ns_offload_count; + union { + struct in_addr ipv4_addr; + struct in6_addr ipv6_addr; + } params; + struct wmi_ns_offload_info info; + struct wmi_mac_addr bssid; +} __packed; + +struct wmi_ns_offload { + __le32 flags; + struct in6_addr target_ipaddr[WMI_NS_ARP_OFFLOAD]; + struct in6_addr solicitation_ipaddr; + struct in6_addr remote_ipaddr; + struct wmi_mac_addr target_mac; +} __packed; + +struct wmi_arp_offload { + __le32 flags; + struct in_addr target_ipaddr; + struct in_addr remote_ipaddr; + struct wmi_mac_addr target_mac; +} __packed; + +/* GTK offload data structure */ +#define WMI_GTK_OFFLOAD_ENABLE_OPCODE BIT(24) +#define WMI_GTK_OFFLOAD_DISABLE_OPCODE BIT(25) +#define WMI_GTK_OFFLOAD_ENABLE 1 +#define WMI_GTK_OFFLOAD_DISABLE 0 + +struct wmi_gtk_rekey_data { + bool valid; + bool enable_offload; + u8 kck[NL80211_KCK_LEN]; + u8 kek[NL80211_KEK_LEN]; + __le64 replay_ctr; +} __packed; + struct wmi_start_scan_tlvs { /* TLV parameters. These includes channel list, ssid list, bssid list, * extra ies. @@ -2855,6 +3023,8 @@ /* Different FW scan engine may choose to bail out on errors. * Allow the driver to have influence over that. */ #define WMI_SCAN_CONTINUE_ON_ERROR 0x80 +/** add DS content in probe req frame */ +#define WMI_SCAN_ADD_DS_IE_IN_PROBE_REQ 0x800 /* WMI_SCAN_CLASS_MASK must be the same value as IEEE80211_SCAN_CLASS_MASK */ #define WMI_SCAN_CLASS_MASK 0xFF000000 @@ -2990,11 +3160,17 @@ u8 buf[0]; } __packed; +struct wmi_mgmt_rx_ext_info { + __le64 rx_mac_timestamp; +} __packed __aligned(4); + #define WMI_RX_STATUS_OK 0x00 #define WMI_RX_STATUS_ERR_CRC 0x01 #define WMI_RX_STATUS_ERR_DECRYPT 0x08 #define WMI_RX_STATUS_ERR_MIC 0x10 #define WMI_RX_STATUS_ERR_KEY_CACHE_MISS 0x20 +/* Extension data at the end of mgmt frame */ +#define WMI_RX_STATUS_EXT_INFO 0x40 #define PHY_ERROR_GEN_SPECTRAL_SCAN 0x26 #define PHY_ERROR_GEN_FALSE_RADAR_EXT 0x24 @@ -3003,6 +3179,10 @@ #define PHY_ERROR_10_4_RADAR_MASK 0x4 #define PHY_ERROR_10_4_SPECTRAL_SCAN_MASK 0x4000000 +#define WMI_PHY_ERROR_MASK0_RADAR BIT(2) +#define WMI_PHY_ERROR_MASK0_FALSE_RADAR_EXT BIT(24) +#define WMI_PHY_ERROR_MASK0_SPECTRAL_SCAN BIT(26) + enum phy_err_type { PHY_ERROR_UNKNOWN, PHY_ERROR_SPECTRAL_SCAN, @@ -3343,6 +3523,7 @@ u32 wapi_mbssid_offset; u32 arp_srcaddr; u32 arp_dstaddr; + u32 enable_btcoex; }; #define WMI_PDEV_PARAM_UNSUPPORTED 0 @@ -3650,6 +3831,15 @@ WMI_10_4_PDEV_PARAM_WAPI_MBSSID_OFFSET, WMI_10_4_PDEV_PARAM_ARP_SRCADDR, WMI_10_4_PDEV_PARAM_ARP_DSTADDR, + WMI_10_4_PDEV_PARAM_TXPOWER_DECR_DB, + WMI_10_4_PDEV_PARAM_RX_BATCHMODE, + WMI_10_4_PDEV_PARAM_PACKET_AGGR_DELAY, + WMI_10_4_PDEV_PARAM_ATF_OBSS_NOISE_SCH, + WMI_10_4_PDEV_PARAM_ATF_OBSS_NOISE_SCALING_FACTOR, + WMI_10_4_PDEV_PARAM_CUST_TXPOWER_SCALE, + WMI_10_4_PDEV_PARAM_ATF_DYNAMIC_ENABLE, + WMI_10_4_PDEV_PARAM_ATF_SSID_GROUP_POLICY, + WMI_10_4_PDEV_PARAM_ENABLE_BTCOEX, }; struct wmi_pdev_set_param_cmd { @@ -3848,7 +4038,7 @@ /* illegal rate phy errors */ __le32 illgl_rate_phy_err; - /* wal pdev continous xretry */ + /* wal pdev continuous xretry */ __le32 pdev_cont_xretry; /* wal pdev continous xretry */ @@ -4019,6 +4209,13 @@ WMI_STAT_VDEV_RATE = BIT(5), }; +enum wmi_10_4_stats_id { + WMI_10_4_STAT_PEER = BIT(0), + WMI_10_4_STAT_AP = BIT(1), + WMI_10_4_STAT_INST = BIT(2), + WMI_10_4_STAT_PEER_EXTD = BIT(3), +}; + struct wlan_inst_rssi_args { __le16 cfg_retry_count; __le16 retry_count; @@ -4096,10 +4293,10 @@ */ struct wmi_pdev_stats_base { __le32 chan_nf; - __le32 tx_frame_count; - __le32 rx_frame_count; - __le32 rx_clear_count; - __le32 cycle_count; + __le32 tx_frame_count; /* Cycles spent transmitting frames */ + __le32 rx_frame_count; /* Cycles spent receiving frames */ + __le32 rx_clear_count; /* Total channel busy time, evidently */ + __le32 cycle_count; /* Total on-channel time */ __le32 phy_err_count; __le32 chan_tx_pwr; } __packed; @@ -4192,7 +4389,13 @@ struct wmi_10_2_4_peer_stats { struct wmi_10_2_peer_stats common; - __le32 unknown_value; /* FIXME: what is this word? */ + __le32 peer_rssi_changed; +} __packed; + +struct wmi_10_2_4_ext_peer_stats { + struct wmi_10_2_peer_stats common; + __le32 peer_rssi_changed; + __le32 rx_duration; } __packed; struct wmi_10_4_peer_stats { @@ -4212,6 +4415,27 @@ __le32 peer_rssi_changed; } __packed; +struct wmi_10_4_peer_extd_stats { + struct wmi_mac_addr peer_macaddr; + __le32 inactive_time; + __le32 peer_chain_rssi; + __le32 rx_duration; + __le32 reserved[10]; +} __packed; + +struct wmi_10_4_bss_bcn_stats { + __le32 vdev_id; + __le32 bss_bcns_dropped; + __le32 bss_bcn_delivered; +} __packed; + +struct wmi_10_4_bss_bcn_filter_stats { + __le32 bcns_dropped; + __le32 bcns_delivered; + __le32 active_filters; + struct wmi_10_4_bss_bcn_stats bss_stats; +} __packed; + struct wmi_10_2_pdev_ext_stats { __le32 rx_rssi_comb; __le32 rx_rssi[4]; @@ -4235,10 +4459,40 @@ }; enum wmi_vdev_subtype { - WMI_VDEV_SUBTYPE_NONE = 0, - WMI_VDEV_SUBTYPE_P2P_DEVICE = 1, - WMI_VDEV_SUBTYPE_P2P_CLIENT = 2, - WMI_VDEV_SUBTYPE_P2P_GO = 3, + WMI_VDEV_SUBTYPE_NONE, + WMI_VDEV_SUBTYPE_P2P_DEVICE, + WMI_VDEV_SUBTYPE_P2P_CLIENT, + WMI_VDEV_SUBTYPE_P2P_GO, + WMI_VDEV_SUBTYPE_PROXY_STA, + WMI_VDEV_SUBTYPE_MESH_11S, + WMI_VDEV_SUBTYPE_MESH_NON_11S, +}; + +enum wmi_vdev_subtype_legacy { + WMI_VDEV_SUBTYPE_LEGACY_NONE = 0, + WMI_VDEV_SUBTYPE_LEGACY_P2P_DEV = 1, + WMI_VDEV_SUBTYPE_LEGACY_P2P_CLI = 2, + WMI_VDEV_SUBTYPE_LEGACY_P2P_GO = 3, + WMI_VDEV_SUBTYPE_LEGACY_PROXY_STA = 4, +}; + +enum wmi_vdev_subtype_10_2_4 { + WMI_VDEV_SUBTYPE_10_2_4_NONE = 0, + WMI_VDEV_SUBTYPE_10_2_4_P2P_DEV = 1, + WMI_VDEV_SUBTYPE_10_2_4_P2P_CLI = 2, + WMI_VDEV_SUBTYPE_10_2_4_P2P_GO = 3, + WMI_VDEV_SUBTYPE_10_2_4_PROXY_STA = 4, + WMI_VDEV_SUBTYPE_10_2_4_MESH_11S = 5, +}; + +enum wmi_vdev_subtype_10_4 { + WMI_VDEV_SUBTYPE_10_4_NONE = 0, + WMI_VDEV_SUBTYPE_10_4_P2P_DEV = 1, + WMI_VDEV_SUBTYPE_10_4_P2P_CLI = 2, + WMI_VDEV_SUBTYPE_10_4_P2P_GO = 3, + WMI_VDEV_SUBTYPE_10_4_PROXY_STA = 4, + WMI_VDEV_SUBTYPE_10_4_MESH_NON_11S = 5, + WMI_VDEV_SUBTYPE_10_4_MESH_11S = 6, }; /* values for vdev_subtype */ @@ -4278,9 +4532,9 @@ __le32 flags; /* ssid field. Only valid for AP/GO/IBSS/BTAmp VDEV type. */ struct wmi_ssid ssid; - /* beacon/probe reponse xmit rate. Applicable for SoftAP. */ + /* beacon/probe response xmit rate. Applicable for SoftAP. */ __le32 bcn_tx_rate; - /* beacon/probe reponse xmit power. Applicable for SoftAP. */ + /* beacon/probe response xmit power. Applicable for SoftAP. */ __le32 bcn_tx_power; /* number of p2p NOA descriptor(s) from scan entry */ __le32 num_noa_descriptors; @@ -4493,6 +4747,7 @@ u32 meru_vc; u32 rx_decap_type; u32 bw_nss_ratemask; + u32 set_tsf; }; #define WMI_VDEV_PARAM_UNSUPPORTED 0 @@ -4507,7 +4762,7 @@ WMI_VDEV_PARAM_BEACON_INTERVAL, /* Listen interval in TUs */ WMI_VDEV_PARAM_LISTEN_INTERVAL, - /* muticast rate in Mbps */ + /* multicast rate in Mbps */ WMI_VDEV_PARAM_MULTICAST_RATE, /* management frame rate in Mbps */ WMI_VDEV_PARAM_MGMT_TX_RATE, @@ -4638,7 +4893,7 @@ WMI_10X_VDEV_PARAM_BEACON_INTERVAL, /* Listen interval in TUs */ WMI_10X_VDEV_PARAM_LISTEN_INTERVAL, - /* muticast rate in Mbps */ + /* multicast rate in Mbps */ WMI_10X_VDEV_PARAM_MULTICAST_RATE, /* management frame rate in Mbps */ WMI_10X_VDEV_PARAM_MGMT_TX_RATE, @@ -4749,6 +5004,7 @@ WMI_10X_VDEV_PARAM_RTS_FIXED_RATE, WMI_10X_VDEV_PARAM_VHT_SGIMASK, WMI_10X_VDEV_PARAM_VHT80_RATEMASK, + WMI_10X_VDEV_PARAM_TSF_INCREMENT, }; enum wmi_10_4_vdev_param { @@ -4818,6 +5074,12 @@ WMI_10_4_VDEV_PARAM_MERU_VC, WMI_10_4_VDEV_PARAM_RX_DECAP_TYPE, WMI_10_4_VDEV_PARAM_BW_NSS_RATEMASK, + WMI_10_4_VDEV_PARAM_SENSOR_AP, + WMI_10_4_VDEV_PARAM_BEACON_RATE, + WMI_10_4_VDEV_PARAM_DTIM_ENABLE_CTS, + WMI_10_4_VDEV_PARAM_STA_KICKOUT, + WMI_10_4_VDEV_PARAM_CAPABILITIES, + WMI_10_4_VDEV_PARAM_TSF_INCREMENT, }; #define WMI_VDEV_PARAM_TXBF_SU_TX_BFEE BIT(0) @@ -4876,7 +5138,7 @@ } __packed; /* VDEV start response status codes */ -/* VDEV succesfully started */ +/* VDEV successfully started */ #define WMI_INIFIED_VDEV_START_RESPONSE_STATUS_SUCCESS 0x0 /* requested VDEV not found */ @@ -5192,7 +5454,7 @@ #define WMI_UAPSD_AC_TYPE_TRIG 1 #define WMI_UAPSD_AC_BIT_MASK(ac, type) \ - ((type == WMI_UAPSD_AC_TYPE_DELI) ? (1<<(ac<<1)) : (1<<((ac<<1)+1))) + (type == WMI_UAPSD_AC_TYPE_DELI ? 1 << (ac << 1) : 1 << ((ac << 1) + 1)) enum wmi_sta_ps_param_uapsd { WMI_STA_PS_UAPSD_AC0_DELIVERY_EN = (1 << 0), @@ -5405,6 +5667,16 @@ struct wmi_bcn_info bcn_info[0]; } __packed; +struct wmi_10_2_4_bcn_info { + struct wmi_tim_info tim_info; + /* The 10.2.4 FW doesn't have p2p NOA info */ +} __packed; + +struct wmi_10_2_4_host_swba_event { + __le32 vdev_map; + struct wmi_10_2_4_bcn_info bcn_info[0]; +} __packed; + /* 16 words = 512 client + 1 word = for guard */ #define WMI_10_4_TIM_BITMAP_ARRAY_SIZE 17 @@ -5641,21 +5913,79 @@ __le32 callback_enable; } __packed; -#define WMI_PEER_AUTH 0x00000001 -#define WMI_PEER_QOS 0x00000002 -#define WMI_PEER_NEED_PTK_4_WAY 0x00000004 -#define WMI_PEER_NEED_GTK_2_WAY 0x00000010 -#define WMI_PEER_APSD 0x00000800 -#define WMI_PEER_HT 0x00001000 -#define WMI_PEER_40MHZ 0x00002000 -#define WMI_PEER_STBC 0x00008000 -#define WMI_PEER_LDPC 0x00010000 -#define WMI_PEER_DYN_MIMOPS 0x00020000 -#define WMI_PEER_STATIC_MIMOPS 0x00040000 -#define WMI_PEER_SPATIAL_MUX 0x00200000 -#define WMI_PEER_VHT 0x02000000 -#define WMI_PEER_80MHZ 0x04000000 -#define WMI_PEER_VHT_2G 0x08000000 +struct wmi_peer_flags_map { + u32 auth; + u32 qos; + u32 need_ptk_4_way; + u32 need_gtk_2_way; + u32 apsd; + u32 ht; + u32 bw40; + u32 stbc; + u32 ldbc; + u32 dyn_mimops; + u32 static_mimops; + u32 spatial_mux; + u32 vht; + u32 bw80; + u32 vht_2g; + u32 pmf; +}; + +enum wmi_peer_flags { + WMI_PEER_AUTH = 0x00000001, + WMI_PEER_QOS = 0x00000002, + WMI_PEER_NEED_PTK_4_WAY = 0x00000004, + WMI_PEER_NEED_GTK_2_WAY = 0x00000010, + WMI_PEER_APSD = 0x00000800, + WMI_PEER_HT = 0x00001000, + WMI_PEER_40MHZ = 0x00002000, + WMI_PEER_STBC = 0x00008000, + WMI_PEER_LDPC = 0x00010000, + WMI_PEER_DYN_MIMOPS = 0x00020000, + WMI_PEER_STATIC_MIMOPS = 0x00040000, + WMI_PEER_SPATIAL_MUX = 0x00200000, + WMI_PEER_VHT = 0x02000000, + WMI_PEER_80MHZ = 0x04000000, + WMI_PEER_VHT_2G = 0x08000000, + WMI_PEER_PMF = 0x10000000, +}; + +enum wmi_10x_peer_flags { + WMI_10X_PEER_AUTH = 0x00000001, + WMI_10X_PEER_QOS = 0x00000002, + WMI_10X_PEER_NEED_PTK_4_WAY = 0x00000004, + WMI_10X_PEER_NEED_GTK_2_WAY = 0x00000010, + WMI_10X_PEER_APSD = 0x00000800, + WMI_10X_PEER_HT = 0x00001000, + WMI_10X_PEER_40MHZ = 0x00002000, + WMI_10X_PEER_STBC = 0x00008000, + WMI_10X_PEER_LDPC = 0x00010000, + WMI_10X_PEER_DYN_MIMOPS = 0x00020000, + WMI_10X_PEER_STATIC_MIMOPS = 0x00040000, + WMI_10X_PEER_SPATIAL_MUX = 0x00200000, + WMI_10X_PEER_VHT = 0x02000000, + WMI_10X_PEER_80MHZ = 0x04000000, +}; + +enum wmi_10_2_peer_flags { + WMI_10_2_PEER_AUTH = 0x00000001, + WMI_10_2_PEER_QOS = 0x00000002, + WMI_10_2_PEER_NEED_PTK_4_WAY = 0x00000004, + WMI_10_2_PEER_NEED_GTK_2_WAY = 0x00000010, + WMI_10_2_PEER_APSD = 0x00000800, + WMI_10_2_PEER_HT = 0x00001000, + WMI_10_2_PEER_40MHZ = 0x00002000, + WMI_10_2_PEER_STBC = 0x00008000, + WMI_10_2_PEER_LDPC = 0x00010000, + WMI_10_2_PEER_DYN_MIMOPS = 0x00020000, + WMI_10_2_PEER_STATIC_MIMOPS = 0x00040000, + WMI_10_2_PEER_SPATIAL_MUX = 0x00200000, + WMI_10_2_PEER_VHT = 0x02000000, + WMI_10_2_PEER_80MHZ = 0x04000000, + WMI_10_2_PEER_VHT_2G = 0x08000000, + WMI_10_2_PEER_PMF = 0x10000000, +}; /* * Peer rate capabilities. @@ -5721,6 +6051,11 @@ __le32 info0; /* WMI_PEER_ASSOC_INFO0_ */ } __packed; +struct wmi_10_4_peer_assoc_complete_cmd { + struct wmi_10_2_peer_assoc_complete_cmd cmd; + __le32 peer_bw_rxnss_override; +} __packed; + struct wmi_peer_assoc_complete_arg { u8 addr[ETH_ALEN]; u32 vdev_id; @@ -5768,6 +6103,13 @@ __le32 noise_floor; __le32 rx_clear_count; __le32 cycle_count; + __le32 chan_tx_pwr_range; + __le32 chan_tx_pwr_tp; + __le32 rx_frame_count; + __le32 my_bss_rx_cycle_count; + __le32 rx_11b_mode_data_duration; + __le32 tx_frame_cnt; + __le32 mac_clk_mhz; } __packed; struct wmi_10_4_chan_info_event { @@ -5910,6 +6252,20 @@ __le32 config_valid; } __packed; +struct wmi_10_4_dbglog_cfg_cmd { + /* bitmask to hold mod id config*/ + __le64 module_enable; + + /* see ATH10K_DBGLOG_CFG_ */ + __le32 config_enable; + + /* mask of module id bits to be changed */ + __le64 module_valid; + + /* mask of config bits to be changed, see ATH10K_DBGLOG_CFG_ */ + __le32 config_valid; +} __packed; + enum wmi_roam_reason { WMI_ROAM_REASON_BETTER_AP = 1, WMI_ROAM_REASON_BEACON_MISS = 2, @@ -5947,6 +6303,17 @@ __le32 vdev_id; }; +struct wmi_peer_delete_resp_ev_arg { + __le32 vdev_id; + struct wmi_mac_addr peer_addr; +}; + +struct wmi_tlv_mgmt_tx_compl_ev_arg { + __le32 desc_id; + __le32 status; + __le32 pdev_id; +}; + struct wmi_mgmt_rx_ev_arg { __le32 channel; __le32 snr; @@ -5954,6 +6321,7 @@ __le32 phy_mode; __le32 buf_len; __le32 status; /* %WMI_RX_STATUS_ */ + struct wmi_mgmt_rx_ext_info ext_info; }; struct wmi_ch_info_ev_arg { @@ -5966,6 +6334,10 @@ __le32 chan_tx_pwr_range; __le32 chan_tx_pwr_tp; __le32 rx_frame_count; + __le32 my_bss_rx_cycle_count; + __le32 rx_11b_mode_data_duration; + __le32 tx_frame_cnt; + __le32 mac_clk_mhz; }; struct wmi_vdev_start_ev_arg { @@ -6004,6 +6376,8 @@ u32 tsf_u32; u32 buf_len; const void *phyerrs; + u32 phy_err_mask0; + u32 phy_err_mask1; }; struct wmi_svc_rdy_ev_arg { @@ -6036,11 +6410,26 @@ __le32 rssi; }; +struct wmi_echo_ev_arg { + __le32 value; +}; + struct wmi_pdev_temperature_event { /* temperature value in Celcius degree */ __le32 temperature; } __packed; +struct wmi_pdev_bss_chan_info_event { + __le32 freq; + __le32 noise_floor; + __le64 cycle_busy; + __le64 cycle_total; + __le64 cycle_tx; + __le64 cycle_rx; + __le64 cycle_rx_bss; + __le32 reserved; +} __packed; + /* WOW structures */ enum wmi_wow_wakeup_event { WOW_BMISS_EVENT = 0, @@ -6239,6 +6628,21 @@ __le32 cca_detect_margin; } __packed; +enum wmi_host_platform_type { + WMI_HOST_PLATFORM_HIGH_PERF, + WMI_HOST_PLATFORM_LOW_PERF, +}; + +enum wmi_bss_survey_req_type { + WMI_BSS_SURVEY_REQ_TYPE_READ = 1, + WMI_BSS_SURVEY_REQ_TYPE_READ_CLEAR, +}; + +struct wmi_pdev_chan_info_req_cmd { + __le32 type; + __le32 reserved; +} __packed; + struct ath10k; struct ath10k_vif; struct ath10k_fw_stats_pdev; @@ -6281,13 +6685,17 @@ int ath10k_wmi_start_scan_verify(const struct wmi_start_scan_arg *arg); int ath10k_wmi_event_scan(struct ath10k *ar, struct sk_buff *skb); +int ath10k_wmi_tlv_event_peer_delete_resp(struct ath10k *ar, + struct sk_buff *skb); int ath10k_wmi_event_mgmt_rx(struct ath10k *ar, struct sk_buff *skb); +int ath10k_wmi_tlv_event_mgmt_tx_compl(struct ath10k *ar, struct sk_buff *skb); void ath10k_wmi_event_chan_info(struct ath10k *ar, struct sk_buff *skb); void ath10k_wmi_event_echo(struct ath10k *ar, struct sk_buff *skb); int ath10k_wmi_event_debug_mesg(struct ath10k *ar, struct sk_buff *skb); void ath10k_wmi_event_update_stats(struct ath10k *ar, struct sk_buff *skb); void ath10k_wmi_event_vdev_start_resp(struct ath10k *ar, struct sk_buff *skb); void ath10k_wmi_event_vdev_stopped(struct ath10k *ar, struct sk_buff *skb); +void ath10k_wmi_event_vdev_delete_resp(struct ath10k *ar, struct sk_buff *skb); void ath10k_wmi_event_peer_sta_kickout(struct ath10k *ar, struct sk_buff *skb); void ath10k_wmi_event_host_swba(struct ath10k *ar, struct sk_buff *skb); void ath10k_wmi_event_tbttoffset_update(struct ath10k *ar, struct sk_buff *skb); @@ -6336,5 +6744,8 @@ void ath10k_wmi_10_4_op_fw_stats_fill(struct ath10k *ar, struct ath10k_fw_stats *fw_stats, char *buf); +int ath10k_wmi_op_get_vdev_subtype(struct ath10k *ar, + enum wmi_vdev_subtype subtype); +int ath10k_wmi_barrier(struct ath10k *ar); #endif /* _WMI_H_ */ diff -ruw linux-4.4.115/drivers/net/wireless/ath/ath10k/wmi-ops.h linux-4.4.115-fbx/drivers/net/wireless/ath/ath10k/wmi-ops.h --- linux-4.4.115/drivers/net/wireless/ath/ath10k/wmi-ops.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/net/wireless/ath/ath10k/wmi-ops.h 2019-01-22 16:16:25.427263830 +0100 @@ -1,6 +1,6 @@ /* * Copyright (c) 2005-2011 Atheros Communications Inc. - * Copyright (c) 2011-2014 Qualcomm Atheros, Inc. + * Copyright (c) 2011-2014, 2017 Qualcomm Atheros, Inc. * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above @@ -29,8 +29,12 @@ struct wmi_scan_ev_arg *arg); int (*pull_mgmt_rx)(struct ath10k *ar, struct sk_buff *skb, struct wmi_mgmt_rx_ev_arg *arg); + int (*pull_mgmt_tx_compl)(struct ath10k *ar, struct sk_buff *skb, + struct wmi_tlv_mgmt_tx_compl_ev_arg *arg); int (*pull_ch_info)(struct ath10k *ar, struct sk_buff *skb, struct wmi_ch_info_ev_arg *arg); + int (*pull_peer_delete_resp)(struct ath10k *ar, struct sk_buff *skb, + struct wmi_peer_delete_resp_ev_arg *arg); int (*pull_vdev_start)(struct ath10k *ar, struct sk_buff *skb, struct wmi_vdev_start_ev_arg *arg); int (*pull_peer_kick)(struct ath10k *ar, struct sk_buff *skb, @@ -51,6 +55,8 @@ struct wmi_roam_ev_arg *arg); int (*pull_wow_event)(struct ath10k *ar, struct sk_buff *skb, struct wmi_wow_ev_arg *arg); + int (*pull_echo_ev)(struct ath10k *ar, struct sk_buff *skb, + struct wmi_echo_ev_arg *arg); enum wmi_txbf_conf (*get_txbf_conf_scheme)(struct ath10k *ar); struct sk_buff *(*gen_pdev_suspend)(struct ath10k *ar, u32 suspend_opt); @@ -123,7 +129,10 @@ enum wmi_force_fw_hang_type type, u32 delay_ms); struct sk_buff *(*gen_mgmt_tx)(struct ath10k *ar, struct sk_buff *skb); - struct sk_buff *(*gen_dbglog_cfg)(struct ath10k *ar, u32 module_enable, + struct sk_buff *(*gen_mgmt_tx_send)(struct ath10k *ar, + struct sk_buff *skb, + dma_addr_t paddr); + struct sk_buff *(*gen_dbglog_cfg)(struct ath10k *ar, u64 module_enable, u32 log_level); struct sk_buff *(*gen_pktlog_enable)(struct ath10k *ar, u32 filter); struct sk_buff *(*gen_pktlog_disable)(struct ath10k *ar); @@ -156,6 +165,10 @@ u32 num_ac); struct sk_buff *(*gen_sta_keepalive)(struct ath10k *ar, const struct wmi_sta_keepalive_arg *arg); + struct sk_buff *(*gen_set_arp_ns_offload)(struct ath10k *ar, + struct ath10k_vif *arvif); + struct sk_buff *(*gen_gtk_offload)(struct ath10k *ar, + struct ath10k_vif *arvif); struct sk_buff *(*gen_wow_enable)(struct ath10k *ar); struct sk_buff *(*gen_wow_add_wakeup_event)(struct ath10k *ar, u32 vdev_id, enum wmi_wow_wakeup_event event, @@ -186,6 +199,20 @@ u8 enable, u32 detect_level, u32 detect_margin); + struct sk_buff *(*gen_set_pdev_mac_addr)(struct ath10k *ar, u32 pdev_id, + u8 *mac_addr); + + struct sk_buff *(*ext_resource_config)(struct ath10k *ar, + enum wmi_host_platform_type type, + u32 fw_feature_bitmap); + int (*get_vdev_subtype)(struct ath10k *ar, + enum wmi_vdev_subtype subtype); + struct sk_buff *(*gen_pdev_bss_chan_info_req) + (struct ath10k *ar, + enum wmi_bss_survey_req_type type); + struct sk_buff *(*gen_echo)(struct ath10k *ar, u32 value); + struct sk_buff *(*gen_csa_offload)(struct ath10k *ar, + u32 vdev_id, bool enable); }; int ath10k_wmi_cmd_send(struct ath10k *ar, struct sk_buff *skb, u32 cmd_id); @@ -222,6 +249,16 @@ } static inline int +ath10k_wmi_pull_mgmt_tx_compl(struct ath10k *ar, struct sk_buff *skb, + struct wmi_tlv_mgmt_tx_compl_ev_arg *arg) +{ + if (!ar->wmi.ops->pull_mgmt_tx_compl) + return -EOPNOTSUPP; + + return ar->wmi.ops->pull_mgmt_tx_compl(ar, skb, arg); +} + +static inline int ath10k_wmi_pull_mgmt_rx(struct ath10k *ar, struct sk_buff *skb, struct wmi_mgmt_rx_ev_arg *arg) { @@ -232,6 +269,16 @@ } static inline int +ath10k_wmi_pull_peer_delete_resp(struct ath10k *ar, struct sk_buff *skb, + struct wmi_peer_delete_resp_ev_arg *arg) +{ + if (!ar->wmi.ops->pull_peer_delete_resp) + return -EOPNOTSUPP; + + return ar->wmi.ops->pull_peer_delete_resp(ar, skb, arg); +} + +static inline int ath10k_wmi_pull_ch_info(struct ath10k *ar, struct sk_buff *skb, struct wmi_ch_info_ev_arg *arg) { @@ -341,6 +388,16 @@ return ar->wmi.ops->pull_wow_event(ar, skb, arg); } +static inline int +ath10k_wmi_pull_echo_ev(struct ath10k *ar, struct sk_buff *skb, + struct wmi_echo_ev_arg *arg) +{ + if (!ar->wmi.ops->pull_echo_ev) + return -EOPNOTSUPP; + + return ar->wmi.ops->pull_echo_ev(ar, skb, arg); +} + static inline enum wmi_txbf_conf ath10k_wmi_get_txbf_conf_scheme(struct ath10k *ar) { @@ -351,6 +408,28 @@ } static inline int +ath10k_wmi_mgmt_tx_send(struct ath10k *ar, struct sk_buff *msdu, + dma_addr_t paddr) +{ + struct sk_buff *skb; + int ret; + + if (!ar->wmi.ops->gen_mgmt_tx_send) + return -EOPNOTSUPP; + + skb = ar->wmi.ops->gen_mgmt_tx_send(ar, msdu, paddr); + if (IS_ERR(skb)) + return PTR_ERR(skb); + + ret = ath10k_wmi_cmd_send(ar, skb, + ar->wmi.cmd->mgmt_tx_send_cmdid); + if (ret) + return ret; + + return 0; +} + +static inline int ath10k_wmi_mgmt_tx(struct ath10k *ar, struct sk_buff *msdu) { struct ieee80211_tx_info *info = IEEE80211_SKB_CB(msdu); @@ -364,7 +443,8 @@ if (IS_ERR(skb)) return PTR_ERR(skb); - ret = ath10k_wmi_cmd_send(ar, skb, ar->wmi.cmd->mgmt_tx_cmdid); + ret = ath10k_wmi_cmd_send(ar, skb, + ar->wmi.cmd->mgmt_tx_cmdid); if (ret) return ret; @@ -930,7 +1010,7 @@ } static inline int -ath10k_wmi_dbglog_cfg(struct ath10k *ar, u32 module_enable, u32 log_level) +ath10k_wmi_dbglog_cfg(struct ath10k *ar, u64 module_enable, u32 log_level) { struct sk_buff *skb; @@ -1145,6 +1225,40 @@ } static inline int +ath10k_wmi_set_arp_ns_offload(struct ath10k *ar, struct ath10k_vif *arvif) +{ + struct sk_buff *skb; + u32 cmd_id; + + if (!ar->wmi.ops->gen_set_arp_ns_offload) + return -EOPNOTSUPP; + + skb = ar->wmi.ops->gen_set_arp_ns_offload(ar, arvif); + if (IS_ERR(skb)) + return PTR_ERR(skb); + + cmd_id = ar->wmi.cmd->set_arp_ns_offload_cmdid; + return ath10k_wmi_cmd_send(ar, skb, cmd_id); +} + +static inline int +ath10k_wmi_gtk_offload(struct ath10k *ar, struct ath10k_vif *arvif) +{ + struct sk_buff *skb; + u32 cmd_id; + + if (!ar->wmi.ops->gen_gtk_offload) + return -EOPNOTSUPP; + + skb = ar->wmi.ops->gen_gtk_offload(ar, arvif); + if (IS_ERR(skb)) + return PTR_ERR(skb); + + cmd_id = ar->wmi.cmd->gtk_offload_cmdid; + return ath10k_wmi_cmd_send(ar, skb, cmd_id); +} + +static inline int ath10k_wmi_wow_enable(struct ath10k *ar) { struct sk_buff *skb; @@ -1333,4 +1447,105 @@ ar->wmi.cmd->pdev_enable_adaptive_cca_cmdid); } +static inline int +ath10k_wmi_ext_resource_config(struct ath10k *ar, + enum wmi_host_platform_type type, + u32 fw_feature_bitmap) +{ + struct sk_buff *skb; + + if (!ar->wmi.ops->ext_resource_config) + return -EOPNOTSUPP; + + skb = ar->wmi.ops->ext_resource_config(ar, type, + fw_feature_bitmap); + + if (IS_ERR(skb)) + return PTR_ERR(skb); + + return ath10k_wmi_cmd_send(ar, skb, + ar->wmi.cmd->ext_resource_cfg_cmdid); +} + +static inline int +ath10k_wmi_get_vdev_subtype(struct ath10k *ar, enum wmi_vdev_subtype subtype) +{ + if (!ar->wmi.ops->get_vdev_subtype) + return -EOPNOTSUPP; + + return ar->wmi.ops->get_vdev_subtype(ar, subtype); +} + +static inline int +ath10k_wmi_pdev_bss_chan_info_request(struct ath10k *ar, + enum wmi_bss_survey_req_type type) +{ + struct ath10k_wmi *wmi = &ar->wmi; + struct sk_buff *skb; + + if (!wmi->ops->gen_pdev_bss_chan_info_req) + return -EOPNOTSUPP; + + skb = wmi->ops->gen_pdev_bss_chan_info_req(ar, type); + if (IS_ERR(skb)) + return PTR_ERR(skb); + + return ath10k_wmi_cmd_send(ar, skb, + wmi->cmd->pdev_bss_chan_info_request_cmdid); +} + +static inline int +ath10k_wmi_csa_offload(struct ath10k *ar, u32 vdev_id, bool enable) +{ + struct sk_buff *skb; + u32 cmd_id; + + if (!ar->wmi.ops->gen_csa_offload) + return -EOPNOTSUPP; + + skb = ar->wmi.ops->gen_csa_offload(ar, vdev_id, enable); + if (IS_ERR(skb)) + return PTR_ERR(skb); + + cmd_id = ar->wmi.cmd->csa_offload_enable_cmdid; + return ath10k_wmi_cmd_send(ar, skb, cmd_id); +} + +static inline int +ath10k_wmi_echo(struct ath10k *ar, u32 value) +{ + struct ath10k_wmi *wmi = &ar->wmi; + struct sk_buff *skb; + + if (!wmi->ops->gen_echo) + return -EOPNOTSUPP; + + skb = wmi->ops->gen_echo(ar, value); + if (IS_ERR(skb)) + return PTR_ERR(skb); + + return ath10k_wmi_cmd_send(ar, skb, wmi->cmd->echo_cmdid); +} + +static inline int +ath10k_gen_set_base_mac_addr(struct ath10k *ar, u8 *mac) +{ + struct sk_buff *skb; + int ret; + + if (!ar->wmi.ops->gen_set_pdev_mac_addr) + return -EOPNOTSUPP; + + skb = ar->wmi.ops->gen_set_pdev_mac_addr(ar, 0, mac); + if (IS_ERR(skb)) + return PTR_ERR(skb); + + ret = ath10k_wmi_cmd_send(ar, skb, + ar->wmi.cmd->pdev_set_base_macaddr_cmdid); + if (ret) + return ret; + + return 0; +} + #endif diff -ruw linux-4.4.115/drivers/net/wireless/ath/ath10k/wmi-tlv.c linux-4.4.115-fbx/drivers/net/wireless/ath/ath10k/wmi-tlv.c --- linux-4.4.115/drivers/net/wireless/ath/ath10k/wmi-tlv.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/net/wireless/ath/ath10k/wmi-tlv.c 2019-10-29 09:26:24.461211183 +0100 @@ -1,6 +1,6 @@ /* * Copyright (c) 2005-2011 Atheros Communications Inc. - * Copyright (c) 2011-2014 Qualcomm Atheros, Inc. + * Copyright (c) 2011-2014, 2017 Qualcomm Atheros, Inc. * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above @@ -468,6 +468,9 @@ case WMI_TLV_VDEV_STOPPED_EVENTID: ath10k_wmi_event_vdev_stopped(ar, skb); break; + case WMI_TLV_VDEV_DELETE_RESP_EVENTID: + ath10k_wmi_event_vdev_delete_resp(ar, skb); + break; case WMI_TLV_PEER_STA_KICKOUT_EVENTID: ath10k_wmi_event_peer_sta_kickout(ar, skb); break; @@ -552,8 +555,14 @@ case WMI_TLV_TX_PAUSE_EVENTID: ath10k_wmi_tlv_event_tx_pause(ar, skb); break; + case WMI_TLV_PEER_DELETE_RESP_EVENTID: + ath10k_wmi_tlv_event_peer_delete_resp(ar, skb); + break; + case WMI_TLV_MGMT_TX_COMPLETION_EVENTID: + ath10k_wmi_tlv_event_mgmt_tx_compl(ar, skb); + break; default: - ath10k_warn(ar, "Unknown eventid: %d\n", id); + ath10k_dbg(ar, ATH10K_DBG_WMI, "Unknown eventid: %d\n", id); break; } @@ -593,6 +602,31 @@ return 0; } +static int ath10k_wmi_tlv_op_pull_mgmt_tx_compl_ev( + struct ath10k *ar, struct sk_buff *skb, + struct wmi_tlv_mgmt_tx_compl_ev_arg *arg) +{ + const void **tb; + const struct wmi_tlv_mgmt_tx_compl_ev *ev; + int ret; + + tb = ath10k_wmi_tlv_parse_alloc(ar, skb->data, skb->len, GFP_ATOMIC); + if (IS_ERR(tb)) { + ret = PTR_ERR(tb); + ath10k_warn(ar, "failed to parse tlv: %d\n", ret); + return ret; + } + + ev = tb[WMI_TLV_TAG_STRUCT_MGMT_TX_COMPL]; + + arg->desc_id = ev->desc_id; + arg->status = ev->status; + arg->pdev_id = ev->pdev_id; + + kfree(tb); + return 0; +} + static int ath10k_wmi_tlv_op_pull_mgmt_rx_ev(struct ath10k *ar, struct sk_buff *skb, struct wmi_mgmt_rx_ev_arg *arg) @@ -642,6 +676,34 @@ return 0; } +static int ath10k_wmi_tlv_op_pull_peer_delete_ev( + struct ath10k *ar, struct sk_buff *skb, + struct wmi_peer_delete_resp_ev_arg *arg) +{ + const void **tb; + const struct wmi_peer_delete_resp_ev_arg *ev; + int ret; + + tb = ath10k_wmi_tlv_parse_alloc(ar, skb->data, skb->len, GFP_ATOMIC); + if (IS_ERR(tb)) { + ret = PTR_ERR(tb); + ath10k_warn(ar, "failed to parse tlv: %d\n", ret); + return ret; + } + + ev = tb[WMI_TLV_TAG_STRUCT_PEER_DELETE_RESP_EVENT]; + if (!ev) { + kfree(tb); + return -EPROTO; + } + + arg->vdev_id = ev->vdev_id; + arg->peer_addr = ev->peer_addr; + + kfree(tb); + return 0; +} + static int ath10k_wmi_tlv_op_pull_ch_info_ev(struct ath10k *ar, struct sk_buff *skb, struct wmi_ch_info_ev_arg *arg) @@ -669,6 +731,13 @@ arg->noise_floor = ev->noise_floor; arg->rx_clear_count = ev->rx_clear_count; arg->cycle_count = ev->cycle_count; + arg->chan_tx_pwr_range = ev->chan_tx_pwr_range; + arg->chan_tx_pwr_tp = ev->chan_tx_pwr_tp; + arg->rx_frame_count = ev->rx_frame_count; + arg->my_bss_rx_cycle_count = ev->my_bss_rx_cycle_count; + arg->rx_11b_mode_data_duration = ev->rx_11b_mode_data_duration; + arg->tx_frame_cnt = ev->tx_frame_cnt; + arg->mac_clk_mhz = ev->mac_clk_mhz; kfree(tb); return 0; @@ -882,6 +951,11 @@ arg->buf_len = __le32_to_cpu(ev->buf_len); arg->phyerrs = phyerrs; + if (QCA_REV_WCN3990(ar)) { + arg->phy_err_mask0 = __le32_to_cpu(ev->rs_phy_err_mask0); + arg->phy_err_mask1 = __le32_to_cpu(ev->rs_phy_err_mask1); + } + kfree(tb); return 0; } @@ -937,7 +1011,12 @@ ev = tb[WMI_TLV_TAG_STRUCT_SERVICE_READY_EVENT]; reg = tb[WMI_TLV_TAG_STRUCT_HAL_REG_CAPABILITIES]; + if (QCA_REV_WCN3990(ar)) { + svc_bmap = (__le32 *)(skb->data + + WMI_TLV_TAG_STRUCT_HL_1_0_SVC_OFFSET); + } else { svc_bmap = tb[WMI_TLV_TAG_ARRAY_UINT32]; + } mem_reqs = tb[WMI_TLV_TAG_ARRAY_STRUCT]; if (!ev || !reg || !svc_bmap || !mem_reqs) { @@ -1229,6 +1308,33 @@ return 0; } +static int ath10k_wmi_tlv_op_pull_echo_ev(struct ath10k *ar, + struct sk_buff *skb, + struct wmi_echo_ev_arg *arg) +{ + const void **tb; + const struct wmi_echo_event *ev; + int ret; + + tb = ath10k_wmi_tlv_parse_alloc(ar, skb->data, skb->len, GFP_ATOMIC); + if (IS_ERR(tb)) { + ret = PTR_ERR(tb); + ath10k_warn(ar, "failed to parse tlv: %d\n", ret); + return ret; + } + + ev = tb[WMI_TLV_TAG_STRUCT_ECHO_EVENT]; + if (!ev) { + kfree(tb); + return -EPROTO; + } + + arg->value = ev->value; + + kfree(tb); + return 0; +} + static struct sk_buff * ath10k_wmi_tlv_op_gen_pdev_suspend(struct ath10k *ar, u32 opt) { @@ -1379,7 +1485,18 @@ cmd->num_host_mem_chunks = __cpu_to_le32(ar->wmi.num_mem_chunks); cfg->num_vdevs = __cpu_to_le32(TARGET_TLV_NUM_VDEVS); + if (QCA_REV_WCN3990(ar)) { + cfg->num_peers = __cpu_to_le32(TARGET_HL_10_TLV_NUM_PEERS); + cfg->ast_skid_limit = + __cpu_to_le32(TARGET_HL_10_TLV_AST_SKID_LIMIT); + cfg->num_wds_entries = + __cpu_to_le32(TARGET_HL_10_TLV_NUM_WDS_ENTRIES); + } else { cfg->num_peers = __cpu_to_le32(TARGET_TLV_NUM_PEERS); + cfg->ast_skid_limit = __cpu_to_le32(0x10); + cfg->num_wds_entries = __cpu_to_le32(0x20); + } + if (test_bit(WMI_SERVICE_RX_FULL_REORDER, ar->wmi.svc_map)) { cfg->num_offload_peers = __cpu_to_le32(TARGET_TLV_NUM_VDEVS); @@ -1391,7 +1508,6 @@ cfg->num_peer_keys = __cpu_to_le32(2); cfg->num_tids = __cpu_to_le32(TARGET_TLV_NUM_TIDS); - cfg->ast_skid_limit = __cpu_to_le32(0x10); cfg->tx_chain_mask = __cpu_to_le32(0x7); cfg->rx_chain_mask = __cpu_to_le32(0x7); cfg->rx_timeout_pri[0] = __cpu_to_le32(0x64); @@ -1407,7 +1523,6 @@ cfg->num_mcast_table_elems = __cpu_to_le32(0); cfg->mcast2ucast_mode = __cpu_to_le32(0); cfg->tx_dbg_log_size = __cpu_to_le32(0x400); - cfg->num_wds_entries = __cpu_to_le32(0x20); cfg->dma_burst_size = __cpu_to_le32(0); cfg->mac_aggr_delim = __cpu_to_le32(0); cfg->rx_skip_defrag_timeout_dup_detection_check = __cpu_to_le32(0); @@ -1424,6 +1539,12 @@ cfg->keep_alive_pattern_size = __cpu_to_le32(0); cfg->max_tdls_concurrent_sleep_sta = __cpu_to_le32(1); cfg->max_tdls_concurrent_buffer_sta = __cpu_to_le32(1); + cfg->wmi_send_separate = __cpu_to_le32(0); + cfg->num_ocb_vdevs = __cpu_to_le32(0); + cfg->num_ocb_channels = __cpu_to_le32(0); + cfg->num_ocb_schedules = __cpu_to_le32(0); + cfg->host_capab = + __cpu_to_le32(WMI_TLV_TX_MSDU_ID_NEW_PARTITION_SUPPORT); ath10k_wmi_put_host_mem_chunks(ar, chunks); @@ -1477,10 +1598,10 @@ cmd->ie_len = __cpu_to_le32(arg->ie_len); cmd->num_probes = __cpu_to_le32(3); - /* FIXME: There are some scan flag inconsistencies across firmwares, - * e.g. WMI-TLV inverts the logic behind the following flag. - */ - cmd->common.scan_ctrl_flags ^= __cpu_to_le32(WMI_SCAN_FILTER_PROBE_REQ); + if (!QCA_REV_WCN3990(ar)) { + cmd->common.scan_ctrl_flags ^= + __cpu_to_le32(WMI_SCAN_FILTER_PROBE_REQ); + } ptr += sizeof(*tlv); ptr += sizeof(*cmd); @@ -2401,6 +2522,30 @@ return skb; } +static int +ath10k_wmi_mgmt_tx_alloc_msdu_id(struct ath10k *ar, struct sk_buff *skb, + dma_addr_t paddr) +{ + struct ath10k_wmi *wmi = &ar->wmi; + struct ath10k_mgmt_tx_pkt_addr *pkt_addr; + int ret; + + pkt_addr = kmalloc(sizeof(*pkt_addr), GFP_ATOMIC); + if (!pkt_addr) + return -ENOMEM; + + pkt_addr->vaddr = skb; + pkt_addr->paddr = paddr; + + spin_lock_bh(&wmi->mgmt_tx_lock); + ret = idr_alloc(&wmi->mgmt_pending_tx, pkt_addr, 0, + wmi->mgmt_max_num_pending_tx, GFP_ATOMIC); + spin_unlock_bh(&wmi->mgmt_tx_lock); + + ath10k_dbg(ar, ATH10K_DBG_WMI, "wmi mgmt tx alloc msdu_id %d\n", ret); + return ret; +} + static struct sk_buff * ath10k_wmi_tlv_op_gen_request_stats(struct ath10k *ar, u32 stats_mask) { @@ -2423,6 +2568,84 @@ } static struct sk_buff * +ath10k_wmi_tlv_op_gen_mgmt_tx_send(struct ath10k *ar, struct sk_buff *msdu, + dma_addr_t paddr) +{ + struct ath10k_skb_cb *cb = ATH10K_SKB_CB(msdu); + struct wmi_tlv_mgmt_tx_cmd *cmd; + struct ieee80211_hdr *hdr; + struct ath10k_vif *arvif; + u32 buf_len = msdu->len; + struct wmi_tlv *tlv; + struct sk_buff *skb; + int desc_id, len; + u32 vdev_id; + void *ptr; + u16 fc; + + hdr = (struct ieee80211_hdr *)msdu->data; + fc = le16_to_cpu(hdr->frame_control); + + if (cb->vif) { + arvif = (void *)cb->vif->drv_priv; + vdev_id = arvif->vdev_id; + } else { + return ERR_PTR(-EINVAL); + } + + if (WARN_ON_ONCE(!ieee80211_is_mgmt(hdr->frame_control))) + return ERR_PTR(-EINVAL); + + len = sizeof(*cmd) + buf_len; + + if ((ieee80211_is_action(hdr->frame_control) || + ieee80211_is_deauth(hdr->frame_control) || + ieee80211_is_disassoc(hdr->frame_control)) && + ieee80211_has_protected(hdr->frame_control)) { + len += IEEE80211_CCMP_MIC_LEN; + buf_len += IEEE80211_CCMP_MIC_LEN; + } + + len += sizeof(*tlv); + len = round_up(len, 4); + skb = ath10k_wmi_alloc_skb(ar, len); + if (!skb) + return ERR_PTR(-ENOMEM); + + desc_id = ath10k_wmi_mgmt_tx_alloc_msdu_id(ar, msdu, paddr); + if (desc_id < 0) + goto msdu_id_alloc_fail; + + ptr = (void *)skb->data; + tlv = ptr; + tlv->tag = __cpu_to_le16(WMI_TLV_TAG_STRUCT_MGMT_TX_CMD); + tlv->len = __cpu_to_le16(sizeof(cmd->hdr)); + cmd = (void *)tlv->value; + cmd->hdr.vdev_id = vdev_id; + cmd->hdr.desc_id = desc_id; + cmd->hdr.chanfreq = 0; + cmd->hdr.buf_len = __cpu_to_le32(buf_len); + cmd->hdr.frame_len = __cpu_to_le32(msdu->len); + cmd->hdr.paddr = __cpu_to_le64(paddr); + cmd->data_len = buf_len; + cmd->data_tag = 0x11; + + ptr += sizeof(*tlv); + ptr += sizeof(*cmd); + + tlv = ptr; + tlv->tag = __cpu_to_le16(WMI_TLV_TAG_ARRAY_UINT32); + tlv->len = __cpu_to_le16(sizeof(msdu->len)); + memcpy(cmd->buf, msdu->data, buf_len); + + return skb; + +msdu_id_alloc_fail: + dev_kfree_skb(skb); + return ERR_PTR(desc_id); +} + +static struct sk_buff * ath10k_wmi_tlv_op_gen_force_fw_hang(struct ath10k *ar, enum wmi_force_fw_hang_type type, u32 delay_ms) @@ -2447,7 +2670,7 @@ } static struct sk_buff * -ath10k_wmi_tlv_op_gen_dbglog_cfg(struct ath10k *ar, u32 module_enable, +ath10k_wmi_tlv_op_gen_dbglog_cfg(struct ath10k *ar, u64 module_enable, u32 log_level) { struct wmi_tlv_dbglog_cmd *cmd; struct wmi_tlv *tlv; @@ -2856,6 +3079,165 @@ } static struct sk_buff * +ath10k_wmi_tlv_op_gen_csa_offload(struct ath10k *ar, u32 vdev_id, bool enable) +{ + struct wmi_csa_offload_enable_cmd *cmd; + struct wmi_tlv *tlv; + struct sk_buff *skb; + int len; + + len = sizeof(*cmd) + sizeof(*tlv); + skb = ath10k_wmi_alloc_skb(ar, len); + if (!skb) + return ERR_PTR(-ENOMEM); + + tlv = (void *)skb->data; + tlv->tag = __cpu_to_le16(WMI_TLV_TAG_STRUCT_CSA_OFFLOAD_ENABLE_CMD); + tlv->len = __cpu_to_le16(sizeof(*cmd)); + cmd = (void *)tlv->value; + + cmd->vdev_id = __cpu_to_le32(vdev_id); + if (enable) + cmd->csa_offload_enable |= + __cpu_to_le32(WMI_CSA_OFFLOAD_ENABLE); + else + cmd->csa_offload_enable |= + __cpu_to_le32(WMI_CSA_OFFLOAD_DISABLE); + + ath10k_dbg(ar, ATH10K_DBG_WMI, + "wmi CSA offload for vdev: %d\n", vdev_id); + return skb; +} + +static struct sk_buff * +ath10k_wmi_op_gen_gtk_offload(struct ath10k *ar, struct ath10k_vif *arvif) +{ + struct wmi_tlv_gtk_offload_cmd *cmd; + struct wmi_tlv *tlv; + struct sk_buff *skb; + struct wmi_gtk_rekey_data *rekey_data = &arvif->gtk_rekey_data; + int len; + + len = sizeof(*cmd) + sizeof(*tlv); + skb = ath10k_wmi_alloc_skb(ar, len); + if (!skb) + return ERR_PTR(-ENOMEM); + + tlv = (void *)skb->data; + tlv->tag = __cpu_to_le16(WMI_TLV_TAG_STRUCT_GTK_OFFLOAD_CMD); + tlv->len = __cpu_to_le16(sizeof(*cmd)); + cmd = (void *)tlv->value; + if (rekey_data->enable_offload) { + cmd->vdev_id = __cpu_to_le32(arvif->vdev_id); + cmd->flags |= __cpu_to_le32(WMI_GTK_OFFLOAD_ENABLE_OPCODE); + memcpy(cmd->kek, rekey_data->kek, NL80211_KEK_LEN); + memcpy(cmd->kck, rekey_data->kck, NL80211_KCK_LEN); + cmd->replay_ctr = __cpu_to_le64(rekey_data->replay_ctr); + } else { + cmd->vdev_id = __cpu_to_le32(arvif->vdev_id); + cmd->flags |= __cpu_to_le32(WMI_GTK_OFFLOAD_DISABLE_OPCODE); + } + + ath10k_dbg(ar, ATH10K_DBG_WMI, + "wmi GTK offload for vdev: %d\n", arvif->vdev_id); + return skb; +} + +static struct sk_buff * +ath10k_wmi_tlv_op_gen_set_arp_ns_offload(struct ath10k *ar, + struct ath10k_vif *arvif) +{ + struct wmi_tlv_arp_ns_offload_cmd *cmd; + struct wmi_tlv *tlv; + struct sk_buff *skb; + size_t len; + void *ptr; + int i; + struct wmi_ns_arp_offload_req *arp = &arvif->arp_offload; + struct wmi_ns_arp_offload_req *ns = &arvif->ns_offload; + struct wmi_ns_offload *ns_tuple; + struct wmi_arp_offload *arp_tuple; + + len = sizeof(*cmd) + sizeof(*tlv) + + sizeof(*tlv) + WMI_NS_ARP_OFFLOAD * + (sizeof(struct wmi_ns_offload) + sizeof(*tlv)) + + sizeof(*tlv) + WMI_NS_ARP_OFFLOAD * + (sizeof(struct wmi_arp_offload) + sizeof(*tlv)); + + skb = ath10k_wmi_alloc_skb(ar, len); + if (!skb) + return ERR_PTR(-ENOMEM); + + ptr = (void *)skb->data; + tlv = ptr; + tlv->tag = __cpu_to_le16(WMI_TLV_TAG_STRUCT_SET_ARP_NS_OFFLOAD_CMD); + tlv->len = __cpu_to_le16(sizeof(*cmd)); + cmd = (struct wmi_tlv_arp_ns_offload_cmd *)tlv->value; + cmd->flags = __cpu_to_le32(0); + cmd->vdev_id = __cpu_to_le32(arvif->vdev_id); + + ptr += (sizeof(*tlv) + sizeof(*cmd)); + tlv = ptr; + tlv->tag = __cpu_to_le16(WMI_TLV_TAG_ARRAY_STRUCT); + tlv->len = __cpu_to_le16(WMI_NS_ARP_OFFLOAD * + (sizeof(struct wmi_ns_offload) + sizeof(*tlv))); + ptr += sizeof(*tlv); + tlv = ptr; + + for (i = 0; i < WMI_NS_ARP_OFFLOAD; i++) { + tlv->tag = __cpu_to_le16(WMI_TLV_TAG_STRUCT_NS_OFFLOAD_TUPLE); + tlv->len = __cpu_to_le16(sizeof(struct wmi_ns_offload)); + ns_tuple = (struct wmi_ns_offload *)tlv->value; + if (ns->enable_offload) { + ns_tuple->flags |= + __cpu_to_le32(WMI_ARP_NS_OFF_FLAGS_VALID); + if (ns->info.target_addr_valid.s6_addr[i]) { + memcpy(&ns_tuple->target_ipaddr[0], + &ns->info.target_addr[i], + sizeof(struct in6_addr)); + } + memcpy(&ns_tuple->solicitation_ipaddr, + &ns->info.self_addr[i], sizeof(struct in6_addr)); + if (ns->info.target_ipv6_ac.s6_addr[i] == IPV6_ADDR_ANY) + ns_tuple->flags |= + __cpu_to_le32(WMI_NSOFF_IPV6_ANYCAST); + } else { + ns_tuple->flags |= + __cpu_to_le32(WMI_ARP_NS_OFFLOAD_DISABLE); + } + ptr += (sizeof(*tlv) + sizeof(struct wmi_ns_offload)); + tlv = ptr; + } + + tlv->tag = __cpu_to_le16(WMI_TLV_TAG_ARRAY_STRUCT); + tlv->len = __cpu_to_le16(WMI_NS_ARP_OFFLOAD * + (sizeof(struct wmi_arp_offload) + sizeof(*tlv))); + ptr += sizeof(*tlv); + tlv = ptr; + + for (i = 0; i < WMI_NS_ARP_OFFLOAD; i++) { + tlv->tag = __cpu_to_le16(WMI_TLV_TAG_STRUCT_ARP_OFFLOAD_TUPLE); + tlv->len = __cpu_to_le16(sizeof(struct wmi_arp_offload)); + arp_tuple = (struct wmi_arp_offload *)tlv->value; + if (arp->enable_offload && (i == 0)) { + arp_tuple->flags |= + __cpu_to_le32(WMI_ARP_NS_OFF_FLAGS_VALID); + memcpy(&arp_tuple->target_ipaddr, + &arp->params.ipv4_addr, + sizeof(arp_tuple->target_ipaddr)); + } else { + arp_tuple->flags |= + __cpu_to_le32(WMI_ARP_NS_OFFLOAD_DISABLE); + } + ptr += (sizeof(*tlv) + sizeof(struct wmi_arp_offload)); + tlv = ptr; + } + + ath10k_dbg(ar, ATH10K_DBG_WMI, "wmi tlv set arp ns offload\n"); + return skb; +} + +static struct sk_buff * ath10k_wmi_tlv_op_gen_wow_enable(struct ath10k *ar) { struct wmi_tlv_wow_enable_cmd *cmd; @@ -2874,6 +3256,8 @@ cmd = (void *)tlv->value; cmd->enable = __cpu_to_le32(1); + if (QCA_REV_WCN3990(ar)) + cmd->pause_iface_config = __cpu_to_le32(1); ath10k_dbg(ar, ATH10K_DBG_WMI, "wmi tlv wow enable\n"); return skb; @@ -3060,6 +3444,33 @@ } static struct sk_buff * +ath10k_wmi_tlv_op_gen_set_base_mac_addr(struct ath10k *ar, u32 pdev_id, + u8 *mac_addr) +{ + struct wmi_tlv_mac_addr_cmd *cmd; + struct wmi_tlv *tlv; + struct sk_buff *skb; + size_t len; + + len = sizeof(*tlv) + sizeof(*cmd); + skb = ath10k_wmi_alloc_skb(ar, len); + if (!skb) + return ERR_PTR(-ENOMEM); + + tlv = (struct wmi_tlv *)skb->data; + tlv->tag = __cpu_to_le16(WMI_TLV_TAG_STRUCT_PDEV_SET_BASE_MACADDR_CMD); + tlv->len = __cpu_to_le16(sizeof(*cmd)); + cmd = (void *)tlv->value; + + cmd->pdev_id = __cpu_to_le32(pdev_id); + ether_addr_copy(cmd->mac_addr.addr, mac_addr); + + ath10k_dbg(ar, ATH10K_DBG_WMI, "wmi tlv set_base_mac addr pdev_id %d mac addr %pM\n", + cmd->pdev_id, cmd->mac_addr.addr); + return skb; +} + +static struct sk_buff * ath10k_wmi_tlv_op_gen_adaptive_qcs(struct ath10k *ar, bool enable) { struct wmi_tlv_adaptive_qcs *cmd; @@ -3087,6 +3498,34 @@ return skb; } +static struct sk_buff * +ath10k_wmi_tlv_op_gen_echo(struct ath10k *ar, u32 value) +{ + struct wmi_echo_cmd *cmd; + struct wmi_tlv *tlv; + struct sk_buff *skb; + void *ptr; + size_t len; + + len = sizeof(*tlv) + sizeof(*cmd); + skb = ath10k_wmi_alloc_skb(ar, len); + if (!skb) + return ERR_PTR(-ENOMEM); + + ptr = (void *)skb->data; + tlv = ptr; + tlv->tag = __cpu_to_le16(WMI_TLV_TAG_STRUCT_ECHO_CMD); + tlv->len = __cpu_to_le16(sizeof(*cmd)); + cmd = (void *)tlv->value; + cmd->value = cpu_to_le32(value); + + ptr += sizeof(*tlv); + ptr += sizeof(*cmd); + + ath10k_dbg(ar, ATH10K_DBG_WMI, "wmi tlv echo value 0x%08x\n", value); + return skb; +} + /****************/ /* TLV mappings */ /****************/ @@ -3133,6 +3572,7 @@ .bcn_filter_rx_cmdid = WMI_TLV_BCN_FILTER_RX_CMDID, .prb_req_filter_rx_cmdid = WMI_TLV_PRB_REQ_FILTER_RX_CMDID, .mgmt_tx_cmdid = WMI_TLV_MGMT_TX_CMDID, + .mgmt_tx_send_cmdid = WMI_TLV_MGMT_TX_SEND_CMD, .prb_tmpl_cmdid = WMI_TLV_PRB_TMPL_CMDID, .addba_clear_resp_cmdid = WMI_TLV_ADDBA_CLEAR_RESP_CMDID, .addba_send_cmdid = WMI_TLV_ADDBA_SEND_CMDID, @@ -3415,6 +3855,7 @@ .meru_vc = WMI_VDEV_PARAM_UNSUPPORTED, .rx_decap_type = WMI_VDEV_PARAM_UNSUPPORTED, .bw_nss_ratemask = WMI_VDEV_PARAM_UNSUPPORTED, + .set_tsf = WMI_VDEV_PARAM_UNSUPPORTED, }; static const struct wmi_ops wmi_tlv_ops = { @@ -3423,7 +3864,9 @@ .pull_scan = ath10k_wmi_tlv_op_pull_scan_ev, .pull_mgmt_rx = ath10k_wmi_tlv_op_pull_mgmt_rx_ev, + .pull_mgmt_tx_compl = ath10k_wmi_tlv_op_pull_mgmt_tx_compl_ev, .pull_ch_info = ath10k_wmi_tlv_op_pull_ch_info_ev, + .pull_peer_delete_resp = ath10k_wmi_tlv_op_pull_peer_delete_ev, .pull_vdev_start = ath10k_wmi_tlv_op_pull_vdev_start_ev, .pull_peer_kick = ath10k_wmi_tlv_op_pull_peer_kick_ev, .pull_swba = ath10k_wmi_tlv_op_pull_swba_ev, @@ -3434,6 +3877,7 @@ .pull_fw_stats = ath10k_wmi_tlv_op_pull_fw_stats, .pull_roam_ev = ath10k_wmi_tlv_op_pull_roam_ev, .pull_wow_event = ath10k_wmi_tlv_op_pull_wow_ev, + .pull_echo_ev = ath10k_wmi_tlv_op_pull_echo_ev, .get_txbf_conf_scheme = ath10k_wmi_tlv_txbf_conf_scheme, .gen_pdev_suspend = ath10k_wmi_tlv_op_gen_pdev_suspend, @@ -3465,7 +3909,7 @@ .gen_pdev_set_wmm = ath10k_wmi_tlv_op_gen_pdev_set_wmm, .gen_request_stats = ath10k_wmi_tlv_op_gen_request_stats, .gen_force_fw_hang = ath10k_wmi_tlv_op_gen_force_fw_hang, - /* .gen_mgmt_tx = not implemented; HTT is used */ + .gen_mgmt_tx_send = ath10k_wmi_tlv_op_gen_mgmt_tx_send, .gen_dbglog_cfg = ath10k_wmi_tlv_op_gen_dbglog_cfg, .gen_pktlog_enable = ath10k_wmi_tlv_op_gen_pktlog_enable, .gen_pktlog_disable = ath10k_wmi_tlv_op_gen_pktlog_disable, @@ -3480,6 +3924,9 @@ .gen_p2p_go_bcn_ie = ath10k_wmi_tlv_op_gen_p2p_go_bcn_ie, .gen_vdev_sta_uapsd = ath10k_wmi_tlv_op_gen_vdev_sta_uapsd, .gen_sta_keepalive = ath10k_wmi_tlv_op_gen_sta_keepalive, + .gen_set_arp_ns_offload = ath10k_wmi_tlv_op_gen_set_arp_ns_offload, + .gen_gtk_offload = ath10k_wmi_op_gen_gtk_offload, + .gen_csa_offload = ath10k_wmi_tlv_op_gen_csa_offload, .gen_wow_enable = ath10k_wmi_tlv_op_gen_wow_enable, .gen_wow_add_wakeup_event = ath10k_wmi_tlv_op_gen_wow_add_wakeup_event, .gen_wow_host_wakeup_ind = ath10k_wmi_tlv_gen_wow_host_wakeup_ind, @@ -3489,9 +3936,29 @@ .gen_tdls_peer_update = ath10k_wmi_tlv_op_gen_tdls_peer_update, .gen_adaptive_qcs = ath10k_wmi_tlv_op_gen_adaptive_qcs, .fw_stats_fill = ath10k_wmi_main_op_fw_stats_fill, + .get_vdev_subtype = ath10k_wmi_op_get_vdev_subtype, + .gen_echo = ath10k_wmi_tlv_op_gen_echo, + .gen_set_pdev_mac_addr = ath10k_wmi_tlv_op_gen_set_base_mac_addr, +}; + +static const struct wmi_peer_flags_map wmi_tlv_peer_flags_map = { + .auth = WMI_TLV_PEER_AUTH, + .qos = WMI_TLV_PEER_QOS, + .need_ptk_4_way = WMI_TLV_PEER_NEED_PTK_4_WAY, + .need_gtk_2_way = WMI_TLV_PEER_NEED_GTK_2_WAY, + .apsd = WMI_TLV_PEER_APSD, + .ht = WMI_TLV_PEER_HT, + .bw40 = WMI_TLV_PEER_40MHZ, + .stbc = WMI_TLV_PEER_STBC, + .ldbc = WMI_TLV_PEER_LDPC, + .dyn_mimops = WMI_TLV_PEER_DYN_MIMOPS, + .static_mimops = WMI_TLV_PEER_STATIC_MIMOPS, + .spatial_mux = WMI_TLV_PEER_SPATIAL_MUX, + .vht = WMI_TLV_PEER_VHT, + .bw80 = WMI_TLV_PEER_80MHZ, + .pmf = WMI_TLV_PEER_PMF, }; -/************/ /* TLV init */ /************/ @@ -3501,4 +3968,5 @@ ar->wmi.vdev_param = &wmi_tlv_vdev_param_map; ar->wmi.pdev_param = &wmi_tlv_pdev_param_map; ar->wmi.ops = &wmi_tlv_ops; + ar->wmi.peer_flags = &wmi_tlv_peer_flags_map; } diff -ruw linux-4.4.115/drivers/net/wireless/ath/ath10k/wmi-tlv.h linux-4.4.115-fbx/drivers/net/wireless/ath/ath10k/wmi-tlv.h --- linux-4.4.115/drivers/net/wireless/ath/ath10k/wmi-tlv.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/net/wireless/ath/ath10k/wmi-tlv.h 2019-01-22 16:16:25.427263830 +0100 @@ -1,6 +1,6 @@ /* * Copyright (c) 2005-2011 Atheros Communications Inc. - * Copyright (c) 2011-2014 Qualcomm Atheros, Inc. + * Copyright (c) 2011-2014, 2017 Qualcomm Atheros, Inc. * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above @@ -22,6 +22,7 @@ #define WMI_TLV_CMD_UNSUPPORTED 0 #define WMI_TLV_PDEV_PARAM_UNSUPPORTED 0 #define WMI_TLV_VDEV_PARAM_UNSUPPORTED 0 +#define WMI_TX_DL_FRM_LEN 64 enum wmi_tlv_grp_id { WMI_TLV_GRP_START = 0x3, @@ -132,6 +133,7 @@ WMI_TLV_PRB_REQ_FILTER_RX_CMDID, WMI_TLV_MGMT_TX_CMDID, WMI_TLV_PRB_TMPL_CMDID, + WMI_TLV_MGMT_TX_SEND_CMD, WMI_TLV_ADDBA_CLEAR_RESP_CMDID = WMI_TLV_CMD(WMI_TLV_GRP_BA_NEG), WMI_TLV_ADDBA_SEND_CMDID, WMI_TLV_ADDBA_STATUS_CMDID, @@ -306,16 +308,21 @@ WMI_TLV_VDEV_STOPPED_EVENTID, WMI_TLV_VDEV_INSTALL_KEY_COMPLETE_EVENTID, WMI_TLV_VDEV_MCC_BCN_INTERVAL_CHANGE_REQ_EVENTID, + WMI_TLV_VDEV_TSF_REPORT_EVENTID, + WMI_TLV_VDEV_DELETE_RESP_EVENTID, WMI_TLV_PEER_STA_KICKOUT_EVENTID = WMI_TLV_EV(WMI_TLV_GRP_PEER), WMI_TLV_PEER_INFO_EVENTID, WMI_TLV_PEER_TX_FAIL_CNT_THR_EVENTID, WMI_TLV_PEER_ESTIMATED_LINKSPEED_EVENTID, WMI_TLV_PEER_STATE_EVENTID, + WMI_TLV_PEER_ASSOC_CONF_EVENTID, + WMI_TLV_PEER_DELETE_RESP_EVENTID, WMI_TLV_MGMT_RX_EVENTID = WMI_TLV_EV(WMI_TLV_GRP_MGMT), WMI_TLV_HOST_SWBA_EVENTID, WMI_TLV_TBTTOFFSET_UPDATE_EVENTID, WMI_TLV_OFFLOAD_BCN_TX_STATUS_EVENTID, WMI_TLV_OFFLOAD_PROB_RESP_TX_STATUS_EVENTID, + WMI_TLV_MGMT_TX_COMPLETION_EVENTID, WMI_TLV_TX_DELBA_COMPLETE_EVENTID = WMI_TLV_EV(WMI_TLV_GRP_BA_NEG), WMI_TLV_TX_ADDBA_COMPLETE_EVENTID, WMI_TLV_BA_RSP_SSN_EVENTID, @@ -527,6 +534,24 @@ WMI_TLV_VDEV_PARAM_IBSS_PS_1RX_CHAIN_IN_ATIM_WINDOW_ENABLE, }; +enum wmi_tlv_peer_flags { + WMI_TLV_PEER_AUTH = 0x00000001, + WMI_TLV_PEER_QOS = 0x00000002, + WMI_TLV_PEER_NEED_PTK_4_WAY = 0x00000004, + WMI_TLV_PEER_NEED_GTK_2_WAY = 0x00000010, + WMI_TLV_PEER_APSD = 0x00000800, + WMI_TLV_PEER_HT = 0x00001000, + WMI_TLV_PEER_40MHZ = 0x00002000, + WMI_TLV_PEER_STBC = 0x00008000, + WMI_TLV_PEER_LDPC = 0x00010000, + WMI_TLV_PEER_DYN_MIMOPS = 0x00020000, + WMI_TLV_PEER_STATIC_MIMOPS = 0x00040000, + WMI_TLV_PEER_SPATIAL_MUX = 0x00200000, + WMI_TLV_PEER_VHT = 0x02000000, + WMI_TLV_PEER_80MHZ = 0x04000000, + WMI_TLV_PEER_PMF = 0x08000000, +}; + enum wmi_tlv_tag { WMI_TLV_TAG_LAST_RESERVED = 15, @@ -871,6 +896,11 @@ WMI_TLV_TAG_STRUCT_SAP_OFL_DEL_STA_EVENT, WMI_TLV_TAG_STRUCT_APFIND_CMD_PARAM, WMI_TLV_TAG_STRUCT_APFIND_EVENT_HDR, + WMI_TLV_TAG_STRUCT_HL_1_0_SVC_OFFSET = 176, + + WMI_TLV_TAG_STRUCT_MGMT_TX_CMD = 0x1A6, + WMI_TLV_TAG_STRUCT_MGMT_TX_COMPL, + WMI_TLV_TAG_STRUCT_PEER_DELETE_RESP_EVENT = 0x1C3, WMI_TLV_TAG_MAX }; @@ -946,6 +976,50 @@ WMI_TLV_SERVICE_STA_RX_IPA_OFFLOAD_SUPPORT, WMI_TLV_SERVICE_MDNS_OFFLOAD, WMI_TLV_SERVICE_SAP_AUTH_OFFLOAD, + WMI_TLV_SERVICE_DUAL_BAND_SIMULTANEOUS_SUPPORT, + WMI_TLV_SERVICE_OCB, + WMI_TLV_SERVICE_AP_ARPNS_OFFLOAD, + WMI_TLV_SERVICE_PER_BAND_CHAINMASK_SUPPORT, + WMI_TLV_SERVICE_PACKET_FILTER_OFFLOAD, + WMI_TLV_SERVICE_MGMT_TX_HTT, + WMI_TLV_SERVICE_MGMT_TX_WMI, + WMI_TLV_SERVICE_EXT_MSG, + WMI_TLV_SERVICE_MAWC, + WMI_TLV_SERVICE_PEER_ASSOC_CONF, + WMI_TLV_SERVICE_EGAP, + WMI_TLV_SERVICE_STA_PMF_OFFLOAD, + WMI_TLV_SERVICE_UNIFIED_WOW_CAPABILITY, + WMI_TLV_SERVICE_ENHANCED_PROXY_STA, + WMI_TLV_SERVICE_ATF, + WMI_TLV_SERVICE_COEX_GPIO, + WMI_TLV_SERVICE_AUX_SPECTRAL_INTF, + WMI_TLV_SERVICE_AUX_CHAN_LOAD_INTF, + WMI_TLV_SERVICE_BSS_CHANNEL_INFO_64, + WMI_TLV_SERVICE_ENTERPRISE_MESH, + WMI_TLV_SERVICE_RESTRT_CHNL_SUPPORT, + WMI_TLV_SERVICE_BPF_OFFLOAD, + WMI_TLV_SERVICE_SYNC_DELETE_CMDS, + WMI_TLV_SERVICE_SMART_ANTENNA_SW_SUPPORT, + WMI_TLV_SERVICE_SMART_ANTENNA_HW_SUPPORT, + WMI_TLV_SERVICE_RATECTRL_LIMIT_MAX_MIN_RATES, + WMI_TLV_SERVICE_NAN_DATA, + WMI_TLV_SERVICE_NAN_RTT, + WMI_TLV_SERVICE_11AX, + WMI_TLV_SERVICE_DEPRECATED_REPLACE, + WMI_TLV_SERVICE_TDLS_CONN_TRACKER_IN_HOST_MODE, + WMI_TLV_SERVICE_ENHANCED_MCAST_FILTER, + WMI_TLV_SERVICE_PERIODIC_CHAN_STAT_SUPPORT, + WMI_TLV_SERVICE_MESH_11S, + WMI_TLV_SERVICE_HALF_RATE_QUARTER_RATE_SUPPORT, + WMI_TLV_SERVICE_VDEV_RX_FILTER, + WMI_TLV_SERVICE_P2P_LISTEN_OFFLOAD_SUPPORT, + WMI_TLV_SERVICE_MARK_FIRST_WAKEUP_PACKET, + WMI_TLV_SERVICE_MULTIPLE_MCAST_FILTER_SET, + WMI_TLV_SERVICE_HOST_MANAGED_RX_REORDER, + WMI_TLV_SERVICE_FLASH_RDWR_SUPPORT, + WMI_TLV_SERVICE_WLAN_STATS_REPORT, + WMI_TLV_SERVICE_TX_MSDU_ID_NEW_PARTITION_SUPPORT, + WMI_TLV_SERVICE_DFS_PHYERR_OFFLOAD, }; #define WMI_SERVICE_IS_ENABLED(wmi_svc_bmap, svc_id, len) \ @@ -1102,6 +1176,8 @@ WMI_SERVICE_MDNS_OFFLOAD, len); SVCMAP(WMI_TLV_SERVICE_SAP_AUTH_OFFLOAD, WMI_SERVICE_SAP_AUTH_OFFLOAD, len); + SVCMAP(WMI_TLV_SERVICE_MGMT_TX_WMI, + WMI_SERVICE_MGMT_TX_WMI, len); } #undef SVCMAP @@ -1112,6 +1188,17 @@ u8 value[0]; } __packed; +struct ath10k_mgmt_tx_pkt_addr { + void *vaddr; + dma_addr_t paddr; +}; + +struct wmi_tlv_mgmt_tx_compl_ev { + __le32 desc_id; + __le32 status; + __le32 pdev_id; +}; + #define WMI_TLV_MGMT_RX_NUM_RSSI 4 struct wmi_tlv_mgmt_rx_ev { @@ -1164,6 +1251,14 @@ __le32 max_num_scan_chans; __le32 hw_bd_id; /* 0 means hw_bd_info is invalid */ struct wmi_tlv_hw_bd_info hw_bd_info[5]; +#ifdef CONFIG_ATH10K_SNOC + __le32 max_supported_macs; + __le32 wmi_fw_sub_feat_caps; + __le32 num_dbs_hw_modes; + __le32 txrx_chainmask; + __le32 default_dbs_hw_mode_index; + __le32 num_msdu_desc; +#endif } __packed; struct wmi_tlv_rdy_ev { @@ -1172,6 +1267,8 @@ __le32 status; } __packed; +#define WMI_TLV_TX_MSDU_ID_NEW_PARTITION_SUPPORT BIT(10) + struct wmi_tlv_resource_config { __le32 num_vdevs; __le32 num_peers; @@ -1209,6 +1306,11 @@ __le32 keep_alive_pattern_size; __le32 max_tdls_concurrent_sleep_sta; __le32 max_tdls_concurrent_buffer_sta; + __le32 wmi_send_separate; + __le32 num_ocb_vdevs; + __le32 num_ocb_channels; + __le32 num_ocb_schedules; + __le32 host_capab; } __packed; struct wmi_tlv_init_cmd { @@ -1317,6 +1419,10 @@ __le32 tsf_l32; __le32 tsf_u32; __le32 buf_len; + __le32 pdev_id; + __le32 rs_phy_err_mask0; + __le32 rs_phy_err_mask1; + __le32 rs_phy_err_mask2; } __packed; enum wmi_tlv_dbglog_param { @@ -1472,6 +1578,21 @@ struct wmi_tlv_wow_enable_cmd { __le32 enable; + __le32 pause_iface_config; +} __packed; + +struct wmi_tlv_arp_ns_offload_cmd { + __le32 flags; + __le32 vdev_id; + __le32 num_ns_ext_tuples; +} __packed; + +struct wmi_tlv_gtk_offload_cmd { + __le32 vdev_id; + __le32 flags; + u8 kek[NL80211_KEK_LEN]; + u8 kck[NL80211_KCK_LEN]; + __le64 replay_ctr; } __packed; struct wmi_tlv_wow_host_wakeup_ind { @@ -1624,4 +1745,24 @@ void ath10k_wmi_tlv_attach(struct ath10k *ar); +struct wmi_tlv_mgmt_tx_hdr { + __le32 vdev_id; + __le32 desc_id; + __le32 chanfreq; + __le64 paddr; + __le32 frame_len; + __le32 buf_len; +} __packed; + +struct wmi_tlv_mgmt_tx_cmd { + struct wmi_tlv_mgmt_tx_hdr hdr; + __le16 data_len; + __le16 data_tag; + u8 buf[0]; +} __packed; + +struct wmi_tlv_mac_addr_cmd { + __le32 pdev_id; + struct wmi_mac_addr mac_addr; +} __packed; #endif diff -ruw linux-4.4.115/drivers/net/wireless/ath/ath10k/wow.c linux-4.4.115-fbx/drivers/net/wireless/ath/ath10k/wow.c --- linux-4.4.115/drivers/net/wireless/ath/ath10k/wow.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/net/wireless/ath/ath10k/wow.c 2019-01-22 16:16:25.431263866 +0100 @@ -17,6 +17,7 @@ #include "mac.h" #include +#include #include "hif.h" #include "core.h" #include "debug.h" @@ -25,7 +26,9 @@ static const struct wiphy_wowlan_support ath10k_wowlan_support = { .flags = WIPHY_WOWLAN_DISCONNECT | - WIPHY_WOWLAN_MAGIC_PKT, + WIPHY_WOWLAN_MAGIC_PKT | + WIPHY_WOWLAN_SUPPORTS_GTK_REKEY | + WIPHY_WOWLAN_GTK_REKEY_FAILURE, .pattern_min_len = WOW_MIN_PATTERN_SIZE, .pattern_max_len = WOW_MAX_PATTERN_SIZE, .max_pkt_offset = WOW_MAX_PKT_OFFSET, @@ -82,6 +85,7 @@ int ret, i; unsigned long wow_mask = 0; struct ath10k *ar = arvif->ar; + struct ieee80211_bss_conf *bss = &arvif->vif->bss_conf; const struct cfg80211_pkt_pattern *patterns = wowlan->patterns; int pattern_id = 0; @@ -100,6 +104,7 @@ __set_bit(WOW_RA_MATCH_EVENT, &wow_mask); break; case WMI_VDEV_TYPE_STA: + if (arvif->is_up && bss->assoc) { if (wowlan->disconnect) { __set_bit(WOW_DEAUTH_RECVD_EVENT, &wow_mask); __set_bit(WOW_DISASSOC_RECVD_EVENT, &wow_mask); @@ -109,6 +114,9 @@ if (wowlan->magic_pkt) __set_bit(WOW_MAGIC_PKT_RECVD_EVENT, &wow_mask); + if (wowlan->gtk_rekey_failure) + __set_bit(WOW_GTK_ERR_EVENT, &wow_mask); + } break; default: break; @@ -224,6 +232,253 @@ return 0; } +static int +ath10k_wow_fill_vdev_ns_offload_struct(struct ath10k_vif *arvif, + bool enable_offload) +{ + struct in6_addr addr[TARGET_NUM_STATIONS]; + struct wmi_ns_arp_offload_req *ns; + struct wireless_dev *wdev; + struct inet6_dev *in6_dev; + struct in6_addr addr_type; + struct inet6_ifaddr *ifa; + struct ifacaddr6 *ifaca; + struct list_head *addr_list; + u32 scope, count = 0; + int i; + + ns = &arvif->ns_offload; + if (!enable_offload) { + ns->offload_type = __cpu_to_le16(WMI_NS_ARP_OFFLOAD); + ns->enable_offload = __cpu_to_le16(WMI_ARP_NS_OFFLOAD_DISABLE); + return 0; + } + + wdev = ieee80211_vif_to_wdev(arvif->vif); + if (!wdev) + return -ENODEV; + + in6_dev = __in6_dev_get(wdev->netdev); + if (!in6_dev) + return -ENODEV; + + memset(&addr, 0, TARGET_NUM_STATIONS * sizeof(struct in6_addr)); + memset(&addr_type, 0, sizeof(struct in6_addr)); + + /* Unicast Addresses */ + read_lock_bh(&in6_dev->lock); + list_for_each(addr_list, &in6_dev->addr_list) { + if (count >= TARGET_NUM_STATIONS) { + read_unlock_bh(&in6_dev->lock); + return -EINVAL; + } + + ifa = list_entry(addr_list, struct inet6_ifaddr, if_list); + if (ifa->flags & IFA_F_DADFAILED) + continue; + scope = ipv6_addr_src_scope(&ifa->addr); + switch (scope) { + case IPV6_ADDR_SCOPE_GLOBAL: + case IPV6_ADDR_SCOPE_LINKLOCAL: + memcpy(&addr[count], &ifa->addr.s6_addr, + sizeof(ifa->addr.s6_addr)); + addr_type.s6_addr[count] = IPV6_ADDR_UNICAST; + count += 1; + break; + } + } + + /* Anycast Addresses */ + for (ifaca = in6_dev->ac_list; ifaca; ifaca = ifaca->aca_next) { + if (count >= TARGET_NUM_STATIONS) { + read_unlock_bh(&in6_dev->lock); + return -EINVAL; + } + + scope = ipv6_addr_src_scope(&ifaca->aca_addr); + switch (scope) { + case IPV6_ADDR_SCOPE_GLOBAL: + case IPV6_ADDR_SCOPE_LINKLOCAL: + memcpy(&addr[count], &ifaca->aca_addr, + sizeof(ifaca->aca_addr)); + addr_type.s6_addr[count] = IPV6_ADDR_ANY; + count += 1; + break; + } + } + read_unlock_bh(&in6_dev->lock); + + /* Filling up the request structure + * Filling the self_addr with solicited address + * A Solicited-Node multicast address is created by + * taking the last 24 bits of a unicast or anycast + * address and appending them to the prefix + * + * FF02:0000:0000:0000:0000:0001:FFXX:XXXX + * + * here XX is the unicast/anycast bits + */ + for (i = 0; i < count; i++) { + ns->info.self_addr[i].s6_addr[0] = 0xFF; + ns->info.self_addr[i].s6_addr[1] = 0x02; + ns->info.self_addr[i].s6_addr[11] = 0x01; + ns->info.self_addr[i].s6_addr[12] = 0xFF; + ns->info.self_addr[i].s6_addr[13] = addr[i].s6_addr[13]; + ns->info.self_addr[i].s6_addr[14] = addr[i].s6_addr[14]; + ns->info.self_addr[i].s6_addr[15] = addr[i].s6_addr[15]; + ns->info.slot_idx = i; + memcpy(&ns->info.target_addr[i], &addr[i], + sizeof(struct in6_addr)); + ns->info.target_addr_valid.s6_addr[i] = 1; + ns->info.target_ipv6_ac.s6_addr[i] = addr_type.s6_addr[i]; + memcpy(&ns->params.ipv6_addr, &ns->info.target_addr[i], + sizeof(struct in6_addr)); + } + + ns->offload_type = __cpu_to_le16(WMI_NS_ARP_OFFLOAD); + ns->enable_offload = __cpu_to_le16(WMI_ARP_NS_OFFLOAD_ENABLE); + ns->num_ns_offload_count = __cpu_to_le16(count); + + return 0; +} + +static int +ath10k_wow_fill_vdev_arp_offload_struct(struct ath10k_vif *arvif, + bool enable_offload) +{ + struct in_device *in_dev; + struct in_ifaddr *ifa; + bool offload_params_found = false; + struct wireless_dev *wdev = ieee80211_vif_to_wdev(arvif->vif); + struct wmi_ns_arp_offload_req *arp = &arvif->arp_offload; + + if (!enable_offload) { + arp->offload_type = __cpu_to_le16(WMI_IPV4_ARP_REPLY_OFFLOAD); + arp->enable_offload = __cpu_to_le16(WMI_ARP_NS_OFFLOAD_DISABLE); + return 0; + } + + if (!wdev) + return -ENODEV; + if (!wdev->netdev) + return -ENODEV; + in_dev = __in_dev_get_rtnl(wdev->netdev); + if (!in_dev) + return -ENODEV; + + arp->offload_type = __cpu_to_le16(WMI_IPV4_ARP_REPLY_OFFLOAD); + arp->enable_offload = __cpu_to_le16(WMI_ARP_NS_OFFLOAD_ENABLE); + for (ifa = in_dev->ifa_list; ifa; ifa = ifa->ifa_next) { + if (!memcmp(ifa->ifa_label, wdev->netdev->name, IFNAMSIZ)) { + offload_params_found = true; + break; + } + } + + if (!offload_params_found) + return -ENODEV; + memcpy(&arp->params.ipv4_addr, &ifa->ifa_local, + sizeof(arp->params.ipv4_addr)); + + return 0; +} + +static int ath10k_wow_enable_ns_arp_offload(struct ath10k *ar, bool offload) +{ + struct ath10k_vif *arvif; + int ret; + + list_for_each_entry(arvif, &ar->arvifs, list) { + if (arvif->vdev_type != WMI_VDEV_TYPE_STA) + continue; + + if (!arvif->is_up) + continue; + + ret = ath10k_wow_fill_vdev_arp_offload_struct(arvif, offload); + if (ret) { + ath10k_err(ar, "ARP-offload config failed, vdev: %d\n", + arvif->vdev_id); + return ret; + } + + ret = ath10k_wow_fill_vdev_ns_offload_struct(arvif, offload); + if (ret) { + ath10k_err(ar, "NS-offload config failed, vdev: %d\n", + arvif->vdev_id); + return ret; + } + + ret = ath10k_wmi_set_arp_ns_offload(ar, arvif); + if (ret) { + ath10k_err(ar, "failed to send offload cmd, vdev: %d\n", + arvif->vdev_id); + return ret; + } + } + + return 0; +} + +static int ath10k_config_wow_listen_interval(struct ath10k *ar) +{ + int ret; + u32 param = ar->wmi.vdev_param->listen_interval; + u8 listen_interval = ar->hw_values->default_listen_interval; + struct ath10k_vif *arvif; + + if (!listen_interval) + return 0; + + list_for_each_entry(arvif, &ar->arvifs, list) { + if (arvif->vdev_type != WMI_VDEV_TYPE_STA) + continue; + ret = ath10k_wmi_vdev_set_param(ar, arvif->vdev_id, + param, listen_interval); + if (ret) { + ath10k_err(ar, "failed to config LI for vdev_id: %d\n", + arvif->vdev_id); + return ret; + } + } + + return 0; +} + +static int ath10k_wow_config_gtk_offload(struct ath10k *ar, bool gtk_offload) +{ + struct ath10k_vif *arvif; + struct ieee80211_bss_conf *bss; + struct wmi_gtk_rekey_data *rekey_data; + int ret; + + list_for_each_entry(arvif, &ar->arvifs, list) { + if (arvif->vdev_type != WMI_VDEV_TYPE_STA) + continue; + + bss = &arvif->vif->bss_conf; + if (!arvif->is_up || !bss->assoc) + continue; + + rekey_data = &arvif->gtk_rekey_data; + if (!rekey_data->valid) + continue; + + if (gtk_offload) + rekey_data->enable_offload = WMI_GTK_OFFLOAD_ENABLE; + else + rekey_data->enable_offload = WMI_GTK_OFFLOAD_DISABLE; + ret = ath10k_wmi_gtk_offload(ar, arvif); + if (ret) { + ath10k_err(ar, "GTK offload failed for vdev_id: %d\n", + arvif->vdev_id); + return ret; + } + } + + return 0; +} + int ath10k_wow_op_suspend(struct ieee80211_hw *hw, struct cfg80211_wowlan *wowlan) { @@ -233,7 +488,7 @@ mutex_lock(&ar->conf_mutex); if (WARN_ON(!test_bit(ATH10K_FW_FEATURE_WOWLAN_SUPPORT, - ar->fw_features))) { + ar->running_fw->fw_file.fw_features))) { ret = 1; goto exit; } @@ -245,10 +500,29 @@ goto exit; } + ret = ath10k_wow_config_gtk_offload(ar, true); + if (ret) { + ath10k_warn(ar, "failed to enable GTK offload: %d\n", ret); + goto exit; + } + + ret = ath10k_wow_enable_ns_arp_offload(ar, true); + if (ret) { + ath10k_warn(ar, "failed to enable ARP-NS offload: %d\n", ret); + goto disable_gtk_offload; + } + ret = ath10k_wow_set_wakeups(ar, wowlan); if (ret) { ath10k_warn(ar, "failed to set wow wakeup events: %d\n", ret); + goto disable_ns_arp_offload; + } + + ret = ath10k_config_wow_listen_interval(ar); + if (ret) { + ath10k_warn(ar, "failed to config wow listen interval: %d\n", + ret); goto cleanup; } @@ -272,11 +546,68 @@ cleanup: ath10k_wow_cleanup(ar); +disable_ns_arp_offload: + ath10k_wow_enable_ns_arp_offload(ar, false); + +disable_gtk_offload: + ath10k_wow_config_gtk_offload(ar, false); exit: mutex_unlock(&ar->conf_mutex); return ret ? 1 : 0; } +void ath10k_wow_op_set_wakeup(struct ieee80211_hw *hw, bool enabled) +{ + struct ath10k *ar = hw->priv; + + mutex_lock(&ar->conf_mutex); + if (test_bit(ATH10K_FW_FEATURE_WOWLAN_SUPPORT, + ar->running_fw->fw_file.fw_features)) { + device_set_wakeup_enable(ar->dev, enabled); + } + mutex_unlock(&ar->conf_mutex); +} + +static void ath10k_wow_op_report_wakeup_reason(struct ath10k *ar) +{ + struct cfg80211_wowlan_wakeup *wakeup = &ar->wow.wakeup; + struct ath10k_vif *arvif; + + memset(wakeup, 0, sizeof(struct cfg80211_wowlan_wakeup)); + switch (ar->wow.wakeup_reason) { + case WOW_REASON_UNSPECIFIED: + wakeup = NULL; + break; + case WOW_REASON_RECV_MAGIC_PATTERN: + wakeup->magic_pkt = true; + break; + case WOW_REASON_DEAUTH_RECVD: + case WOW_REASON_DISASSOC_RECVD: + case WOW_REASON_AP_ASSOC_LOST: + case WOW_REASON_CSA_EVENT: + wakeup->disconnect = true; + break; + case WOW_REASON_GTK_HS_ERR: + wakeup->gtk_rekey_failure = true; + break; + } + ar->wow.wakeup_reason = WOW_REASON_UNSPECIFIED; + + if (wakeup) { + wakeup->pattern_idx = -1; + list_for_each_entry(arvif, &ar->arvifs, list) { + ieee80211_report_wowlan_wakeup(arvif->vif, + wakeup, GFP_KERNEL); + if (wakeup->disconnect) + ieee80211_resume_disconnect(arvif->vif); + } + } else { + list_for_each_entry(arvif, &ar->arvifs, list) + ieee80211_report_wowlan_wakeup(arvif->vif, + NULL, GFP_KERNEL); + } +} + int ath10k_wow_op_resume(struct ieee80211_hw *hw) { struct ath10k *ar = hw->priv; @@ -285,7 +616,7 @@ mutex_lock(&ar->conf_mutex); if (WARN_ON(!test_bit(ATH10K_FW_FEATURE_WOWLAN_SUPPORT, - ar->fw_features))) { + ar->running_fw->fw_file.fw_features))) { ret = 1; goto exit; } @@ -297,8 +628,20 @@ } ret = ath10k_wow_wakeup(ar); - if (ret) + if (ret) { ath10k_warn(ar, "failed to wakeup from wow: %d\n", ret); + goto exit; + } + + ret = ath10k_wow_enable_ns_arp_offload(ar, false); + if (ret) { + ath10k_warn(ar, "failed to disable ARP-NS offload: %d\n", ret); + goto exit; + } + + ret = ath10k_wow_config_gtk_offload(ar, false); + if (ret) + ath10k_warn(ar, "failed to disable GTK offload: %d\n", ret); exit: if (ret) { @@ -319,13 +662,15 @@ } } + ath10k_wow_op_report_wakeup_reason(ar); mutex_unlock(&ar->conf_mutex); return ret; } int ath10k_wow_init(struct ath10k *ar) { - if (!test_bit(ATH10K_FW_FEATURE_WOWLAN_SUPPORT, ar->fw_features)) + if (!test_bit(ATH10K_FW_FEATURE_WOWLAN_SUPPORT, + ar->running_fw->fw_file.fw_features)) return 0; if (WARN_ON(!test_bit(WMI_SERVICE_WOW, ar->wmi.svc_map))) @@ -334,6 +679,15 @@ ar->wow.wowlan_support = ath10k_wowlan_support; ar->wow.wowlan_support.n_patterns = ar->wow.max_num_patterns; ar->hw->wiphy->wowlan = &ar->wow.wowlan_support; + device_init_wakeup(ar->dev, true); return 0; } + +void ath10k_wow_deinit(struct ath10k *ar) +{ + if (test_bit(ATH10K_FW_FEATURE_WOWLAN_SUPPORT, + ar->running_fw->fw_file.fw_features) && + test_bit(WMI_SERVICE_WOW, ar->wmi.svc_map)) + device_init_wakeup(ar->dev, false); +} diff -ruw linux-4.4.115/drivers/net/wireless/ath/ath10k/wow.h linux-4.4.115-fbx/drivers/net/wireless/ath/ath10k/wow.h --- linux-4.4.115/drivers/net/wireless/ath/ath10k/wow.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/net/wireless/ath/ath10k/wow.h 2019-01-22 16:16:25.431263866 +0100 @@ -17,18 +17,21 @@ #define _WOW_H_ struct ath10k_wow { + u32 wakeup_reason; u32 max_num_patterns; struct completion wakeup_completed; + struct cfg80211_wowlan_wakeup wakeup; struct wiphy_wowlan_support wowlan_support; }; #ifdef CONFIG_PM int ath10k_wow_init(struct ath10k *ar); +void ath10k_wow_deinit(struct ath10k *ar); int ath10k_wow_op_suspend(struct ieee80211_hw *hw, struct cfg80211_wowlan *wowlan); int ath10k_wow_op_resume(struct ieee80211_hw *hw); - +void ath10k_wow_op_set_wakeup(struct ieee80211_hw *hw, bool enabled); #else static inline int ath10k_wow_init(struct ath10k *ar) @@ -36,5 +39,8 @@ return 0; } +void ath10k_wow_deinit(struct ath10k *ar) +{ +} #endif /* CONFIG_PM */ #endif /* _WOW_H_ */ diff -ruw linux-4.4.115/drivers/net/wireless/ath/dfs_pattern_detector.c linux-4.4.115-fbx/drivers/net/wireless/ath/dfs_pattern_detector.c --- linux-4.4.115/drivers/net/wireless/ath/dfs_pattern_detector.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/net/wireless/ath/dfs_pattern_detector.c 2019-10-29 09:26:24.473211301 +0100 @@ -37,6 +37,11 @@ #define MIN_PPB_THRESH 50 #define PPB_THRESH_RATE(PPB, RATE) ((PPB * RATE + 100 - RATE) / 100) #define PPB_THRESH(PPB) PPB_THRESH_RATE(PPB, MIN_PPB_THRESH) +/* percentage on ppb threshold, for ETSI type4, to trigger detection */ +#define MIN_PPB_THRESH_TYPE4 30 +#define PPB_THRESH_RATE_TYPE4(PPB, RATE) ((PPB * RATE + 100 - RATE) / 100) +#define PPB_THRESH_TYPE4(PPB) PPB_THRESH_RATE_TYPE4(PPB, MIN_PPB_THRESH_TYPE4) + #define PRF2PRI(PRF) ((1000000 + PRF / 2) / PRF) /* percentage of pulse width tolerance */ #define WIDTH_TOLERANCE 5 @@ -51,13 +56,21 @@ PPB_THRESH(PPB), PRI_TOLERANCE, CHIRP \ } +#define ETSI_PATTERN_TYPE4(ID, WMIN, WMAX, PMIN, PMAX, PRF, PPB, CHIRP) \ +{ \ + ID, WIDTH_LOWER(WMIN), WIDTH_UPPER(WMAX), \ + (PRF2PRI(PMAX) - PRI_TOLERANCE), \ + (PRF2PRI(PMIN) * PRF + PRI_TOLERANCE), PRF, PPB * PRF, \ + PPB_THRESH_TYPE4(PPB), PRI_TOLERANCE, CHIRP \ +} + /* radar types as defined by ETSI EN-301-893 v1.5.1 */ static const struct radar_detector_specs etsi_radar_ref_types_v15[] = { ETSI_PATTERN(0, 0, 1, 700, 700, 1, 18, false), ETSI_PATTERN(1, 0, 5, 200, 1000, 1, 10, false), ETSI_PATTERN(2, 0, 15, 200, 1600, 1, 15, false), ETSI_PATTERN(3, 0, 15, 2300, 4000, 1, 25, false), - ETSI_PATTERN(4, 20, 30, 2000, 4000, 1, 20, false), + ETSI_PATTERN_TYPE4(4, 20, 30, 2000, 4000, 1, 20, false), ETSI_PATTERN(5, 0, 2, 300, 400, 3, 10, false), ETSI_PATTERN(6, 0, 2, 400, 1200, 3, 15, false), }; diff -ruw linux-4.4.115/drivers/net/wireless/ath/regd.c linux-4.4.115-fbx/drivers/net/wireless/ath/regd.c --- linux-4.4.115/drivers/net/wireless/ath/regd.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/net/wireless/ath/regd.c 2019-10-29 09:26:24.473211301 +0100 @@ -38,28 +38,28 @@ /* We enable active scan on these a case by case basis by regulatory domain */ #define ATH9K_2GHZ_CH12_13 REG_RULE(2467-10, 2472+10, 40, 0, 20,\ NL80211_RRF_NO_IR) -#define ATH9K_2GHZ_CH14 REG_RULE(2484-10, 2484+10, 40, 0, 20,\ +#define ATH9K_2GHZ_CH14 REG_RULE(2484 - 10, 2484 + 10, 20, 0, 20,\ NL80211_RRF_NO_IR | \ NL80211_RRF_NO_OFDM) /* We allow IBSS on these on a case by case basis by regulatory domain */ -#define ATH9K_5GHZ_5150_5350 REG_RULE(5150-10, 5350+10, 80, 0, 30,\ +#define ATH9K_5GHZ_5180_5320 REG_RULE(5180 - 10, 5320 + 10, 160, 0, 20,\ NL80211_RRF_NO_IR) -#define ATH9K_5GHZ_5470_5850 REG_RULE(5470-10, 5850+10, 80, 0, 30,\ +#define ATH9K_5GHZ_5500_5825 REG_RULE(5500 - 10, 5825 + 10, 80, 0, 20,\ NL80211_RRF_NO_IR) -#define ATH9K_5GHZ_5725_5850 REG_RULE(5725-10, 5850+10, 80, 0, 30,\ +#define ATH9K_5GHZ_5745_5825 REG_RULE(5745 - 10, 5825 + 10, 80, 0, 20,\ NL80211_RRF_NO_IR) #define ATH9K_2GHZ_ALL ATH9K_2GHZ_CH01_11, \ ATH9K_2GHZ_CH12_13, \ ATH9K_2GHZ_CH14 -#define ATH9K_5GHZ_ALL ATH9K_5GHZ_5150_5350, \ - ATH9K_5GHZ_5470_5850 +#define ATH9K_5GHZ_ALL ATH9K_5GHZ_5180_5320, \ + ATH9K_5GHZ_5500_5825 /* This one skips what we call "mid band" */ -#define ATH9K_5GHZ_NO_MIDBAND ATH9K_5GHZ_5150_5350, \ - ATH9K_5GHZ_5725_5850 +#define ATH9K_5GHZ_NO_MIDBAND ATH9K_5GHZ_5180_5320, \ + ATH9K_5GHZ_5745_5825 /* Can be used for: * 0x60, 0x61, 0x62 */ @@ -256,7 +256,7 @@ /* Frequency is one where radar detection is required */ static bool ath_is_radar_freq(u16 center_freq) { - return (center_freq >= 5260 && center_freq <= 5700); + return (center_freq >= 5260 && center_freq <= 5720); } static void ath_force_clear_no_ir_chan(struct wiphy *wiphy, @@ -631,6 +631,8 @@ struct regulatory_request *request)) { const struct ieee80211_regdomain *regd; + u32 chan_num; + struct ieee80211_channel *chan; wiphy->reg_notifier = reg_notifier; wiphy->regulatory_flags |= REGULATORY_STRICT_REG | @@ -653,6 +655,20 @@ } wiphy_apply_custom_regulatory(wiphy, regd); + + /* For regulatory rules similar to the following: + * REG_RULE(2412-10, 2462+10, 40, 0, 20, 0), channels 12/13 are enabled + * due to support of 5/10 MHz. + * Therefore, disable 2.4 Ghz channels that dont have 20 mhz bw + */ + for (chan_num = 0; + chan_num < wiphy->bands[IEEE80211_BAND_2GHZ]->n_channels; + chan_num++) { + chan = &wiphy->bands[IEEE80211_BAND_2GHZ]->channels[chan_num]; + if (chan->flags & IEEE80211_CHAN_NO_20MHZ) + chan->flags |= IEEE80211_CHAN_DISABLED; + } + ath_reg_apply_radar_flags(wiphy); ath_reg_apply_world_flags(wiphy, NL80211_REGDOM_SET_BY_DRIVER, reg); return 0; diff -ruw linux-4.4.115/drivers/net/wireless/ath/wil6210/Kconfig linux-4.4.115-fbx/drivers/net/wireless/ath/wil6210/Kconfig --- linux-4.4.115/drivers/net/wireless/ath/wil6210/Kconfig 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/net/wireless/ath/wil6210/Kconfig 2019-01-22 16:16:25.491264409 +0100 @@ -40,3 +40,35 @@ option if you are interested in debugging the driver. If unsure, say Y to make it easier to debug problems. + +config WIL6210_WRITE_IOCTL + bool "wil6210 write ioctl to the device" + depends on WIL6210 + default y + ---help--- + Say Y here to allow write-access from user-space to + the device memory through ioctl. This is useful for + debugging purposes only. + + If unsure, say N. + +config WIL6210_PLATFORM_MSM + bool "wil6210 MSM platform specific support" + depends on WIL6210 + depends on ARCH_QCOM + default y + ---help--- + Say Y here to enable wil6210 driver support for MSM + platform specific features + +config WIL6210_DEBUGFS + bool "wil6210 debugfs support" + depends on WIL6210 + depends on DEBUG_FS + default y + ---help--- + Say Y here to enable wil6210 debugfs support, using the + kernel debugfs infrastructure. Select this + option if you are interested in debugging the driver. + + If unsure, say Y to make it easier to debug problems. diff -ruw linux-4.4.115/drivers/net/wireless/ath/wil6210/Makefile linux-4.4.115-fbx/drivers/net/wireless/ath/wil6210/Makefile --- linux-4.4.115/drivers/net/wireless/ath/wil6210/Makefile 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/net/wireless/ath/wil6210/Makefile 2019-01-22 16:16:25.491264409 +0100 @@ -4,7 +4,8 @@ wil6210-y += netdev.o wil6210-y += cfg80211.o wil6210-y += pcie_bus.o -wil6210-y += debugfs.o +wil6210-$(CONFIG_WIL6210_DEBUGFS) += debugfs.o +wil6210-y += sysfs.o wil6210-y += wmi.o wil6210-y += interrupt.o wil6210-y += txrx.o @@ -18,8 +19,13 @@ wil6210-y += wil_platform.o wil6210-y += ethtool.o wil6210-y += wil_crash_dump.o +wil6210-y += p2p.o +wil6210-y += ftm.o # for tracing framework to find trace.h CFLAGS_trace.o := -I$(src) subdir-ccflags-y += -D__CHECK_ENDIAN__ + +MSM_11AD_PATH = drivers/platform/msm/msm_11ad +CFLAGS_wil_platform.o := -I$(MSM_11AD_PATH) diff -ruw linux-4.4.115/drivers/net/wireless/Kconfig linux-4.4.115-fbx/drivers/net/wireless/Kconfig --- linux-4.4.115/drivers/net/wireless/Kconfig 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/net/wireless/Kconfig 2019-10-29 09:26:24.453211105 +0100 @@ -265,6 +265,60 @@ To compile this driver as a module, choose M here: the module will be called mwl8k. If unsure, say N. +config WIFI_CONTROL_FUNC + bool "Enable WiFi control function abstraction" + help + Enables Power/Reset/Carddetect function abstraction + +config WCNSS_CORE + tristate "Qualcomm WCNSS CORE driver" + select WIRELESS_EXT + select WEXT_PRIV + select WEXT_CORE + select WEXT_SPY + ---help--- + Core driver for the Qualcomm WCNSS triple play connectivity subsystem + +config WCNSS_CORE_PRONTO + tristate "Qualcomm WCNSS Pronto Support" + depends on WCNSS_CORE + ---help--- + Pronto Support for the Qualcomm WCNSS triple play connectivity subsystem + +config WCNSS_REGISTER_DUMP_ON_BITE + bool "Enable/disable WCNSS register dump when there is a WCNSS bite" + depends on WCNSS_CORE_PRONTO + ---help--- + When Apps recieves a WDOG bite from WCNSS, collecting a register dump + of WCNSS is helpful to root cause the failure. WCNSS may not be + properly clocked in some WCNSS bite cases, and that may cause unclocked + register access failures. So this feature is to enable/disable the + register dump on WCNSS WDOG bite. + +config WCNSS_MEM_PRE_ALLOC + tristate "WCNSS pre-alloc memory support" + ---help--- + Pre-allocate memory for the WLAN driver module. + This feature enable cld wlan driver to use pre allocated memory + for it's internal usage and release it to back to pre allocated pool. + This memory is allocated at the cold boot time. + +config CNSS_CRYPTO + tristate "Enable CNSS crypto support" + ---help--- + Add crypto support for the WLAN driver module. + This feature enable wlan driver to use the crypto APIs exported + from cnss platform driver. This crypto APIs used to generate cipher + key and add support for the WLAN driver module security protocol. + +config CNSS_QCA6290 + bool "Enable CNSS QCA6290 chipset specific changes" + ---help--- + This enables the changes from WLAN host driver that are specific to + CNSS QCA6290 chipset. + These changes are needed to support the new hardware architecture + for CNSS QCA6290 chipset. + source "drivers/net/wireless/ath/Kconfig" source "drivers/net/wireless/b43/Kconfig" source "drivers/net/wireless/b43legacy/Kconfig" @@ -285,5 +339,9 @@ source "drivers/net/wireless/mwifiex/Kconfig" source "drivers/net/wireless/cw1200/Kconfig" source "drivers/net/wireless/rsi/Kconfig" +source "drivers/net/wireless/cnss/Kconfig" +source "drivers/net/wireless/cnss2/Kconfig" +source "drivers/net/wireless/cnss_genl/Kconfig" +source "drivers/net/wireless/cnss_utils/Kconfig" endif # WLAN diff -ruw linux-4.4.115/drivers/net/wireless/Makefile linux-4.4.115-fbx/drivers/net/wireless/Makefile --- linux-4.4.115/drivers/net/wireless/Makefile 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/net/wireless/Makefile 2019-10-29 09:26:24.453211105 +0100 @@ -60,3 +60,12 @@ obj-$(CONFIG_CW1200) += cw1200/ obj-$(CONFIG_RSI_91X) += rsi/ + +obj-$(CONFIG_WCNSS_CORE) += wcnss/ + +obj-$(CONFIG_CNSS) += cnss/ +obj-$(CONFIG_CNSS2) += cnss2/ +obj-$(CONFIG_WCNSS_MEM_PRE_ALLOC) += cnss_prealloc/ +obj-$(CONFIG_CNSS_CRYPTO) += cnss_crypto/ +obj-$(CONFIG_CNSS_GENL) += cnss_genl/ +obj-$(CONFIG_CNSS_UTILS) += cnss_utils/ diff -ruw linux-4.4.115/drivers/nfc/Kconfig linux-4.4.115-fbx/drivers/nfc/Kconfig --- linux-4.4.115/drivers/nfc/Kconfig 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/nfc/Kconfig 2019-01-22 16:16:25.999269009 +0100 @@ -77,3 +77,11 @@ source "drivers/nfc/nxp-nci/Kconfig" source "drivers/nfc/s3fwrn5/Kconfig" endmenu + +config NFC_NQ + tristate "QTI NCI based NFC Controller Driver for NQx" + depends on I2C + help + This enables the NFC driver for NQx based devices. + This is for i2c connected version. NCI protocol logic + resides in the usermode and it has no other NFC dependencies. diff -ruw linux-4.4.115/drivers/nfc/Makefile linux-4.4.115-fbx/drivers/nfc/Makefile --- linux-4.4.115/drivers/nfc/Makefile 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/nfc/Makefile 2019-01-22 16:16:25.999269009 +0100 @@ -16,3 +16,4 @@ obj-$(CONFIG_NFC_ST_NCI) += st-nci/ obj-$(CONFIG_NFC_NXP_NCI) += nxp-nci/ obj-$(CONFIG_NFC_S3FWRN5) += s3fwrn5/ +obj-$(CONFIG_NFC_NQ) += nq-nci.o diff -ruw linux-4.4.115/drivers/of/address.c linux-4.4.115-fbx/drivers/of/address.c --- linux-4.4.115/drivers/of/address.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/of/address.c 2019-01-22 16:16:26.015269154 +0100 @@ -788,6 +788,22 @@ #endif } +const __be32 *of_get_address_by_name(struct device_node *dev, const char *name, + u64 *size, unsigned int *flags) +{ + int index; + if (!name) + return NULL; + + /* Try to read "reg-names" property and get the index by name */ + index = of_property_match_string(dev, "reg-names", name); + if (index < 0) + return NULL; + + return of_get_address(dev, index, size, flags); +} +EXPORT_SYMBOL(of_get_address_by_name); + static int __of_address_to_resource(struct device_node *dev, const __be32 *addrp, u64 size, unsigned int flags, const char *name, struct resource *r) @@ -1026,3 +1042,19 @@ return false; } EXPORT_SYMBOL_GPL(of_dma_is_coherent); + +void __iomem *of_iomap_by_name(struct device_node *np, const char *name) +{ + int index; + + if (!name) + return NULL; + + /* Try to read "reg-names" property and get the index by name */ + index = of_property_match_string(np, "reg-names", name); + if (index < 0) + return NULL; + + return of_iomap(np, index); +} +EXPORT_SYMBOL(of_iomap_by_name); diff -ruw linux-4.4.115/drivers/of/fdt.c linux-4.4.115-fbx/drivers/of/fdt.c --- linux-4.4.115/drivers/of/fdt.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/of/fdt.c 2019-01-22 16:16:26.015269154 +0100 @@ -496,7 +496,7 @@ if (size && early_init_dt_reserve_memory_arch(base, size, nomap) == 0) - pr_debug("Reserved memory: reserved region for node '%s': base %pa, size %ld MiB\n", + pr_info("Reserved memory: reserved region for node '%s': base %pa, size %ld MiB\n", uname, &base, (unsigned long)size / SZ_1M); else pr_info("Reserved memory: failed to reserve memory for node '%s': base %pa, size %ld MiB\n", @@ -763,6 +763,16 @@ } #ifdef CONFIG_BLK_DEV_INITRD +#ifndef __early_init_dt_declare_initrd +static void __early_init_dt_declare_initrd(unsigned long start, + unsigned long end) +{ + initrd_start = (unsigned long)__va(start); + initrd_end = (unsigned long)__va(end); + initrd_below_start_ok = 1; +} +#endif + /** * early_init_dt_check_for_initrd - Decode initrd location from flat tree * @node: reference to node containing initrd location ('chosen') @@ -785,9 +795,7 @@ return; end = of_read_number(prop, len/4); - initrd_start = (unsigned long)__va(start); - initrd_end = (unsigned long)__va(end); - initrd_below_start_ok = 1; + __early_init_dt_declare_initrd(start, end); pr_debug("initrd_start=0x%llx initrd_end=0x%llx\n", (unsigned long long)start, (unsigned long long)end); @@ -799,14 +807,13 @@ #endif /* CONFIG_BLK_DEV_INITRD */ #ifdef CONFIG_SERIAL_EARLYCON -extern struct of_device_id __earlycon_of_table[]; static int __init early_init_dt_scan_chosen_serial(void) { int offset; const char *p; int l; - const struct of_device_id *match = __earlycon_of_table; + const struct earlycon_id *match; const void *fdt = initial_boot_params; offset = fdt_path_offset(fdt, "/chosen"); @@ -829,19 +836,20 @@ if (offset < 0) return -ENODEV; - while (match->compatible[0]) { + for (match = __earlycon_table; match < __earlycon_table_end; match++) { u64 addr; - if (fdt_node_check_compatible(fdt, offset, match->compatible)) { - match++; + if (!match->compatible[0]) + continue; + + if (fdt_node_check_compatible(fdt, offset, match->compatible)) continue; - } addr = fdt_translate_address(fdt, offset); if (addr == OF_BAD_ADDR) return -ENXIO; - of_setup_earlycon(addr, match->data); + of_setup_earlycon(addr, match->setup); return 0; } return -ENODEV; @@ -941,36 +949,66 @@ return 0; } +/* + * Convert configs to something easy to use in C code + */ +#if defined(CONFIG_CMDLINE_FORCE) +static const int overwrite_incoming_cmdline = 1; +static const int read_dt_cmdline; +static const int concat_cmdline; +#elif defined(CONFIG_CMDLINE_EXTEND) +static const int overwrite_incoming_cmdline; +static const int read_dt_cmdline = 1; +static const int concat_cmdline = 1; +#else /* CMDLINE_FROM_BOOTLOADER */ +static const int overwrite_incoming_cmdline; +static const int read_dt_cmdline = 1; +static const int concat_cmdline; +#endif + +#ifdef CONFIG_CMDLINE +static const char *config_cmdline = CONFIG_CMDLINE; +#else +static const char *config_cmdline = ""; +#endif + int __init early_init_dt_scan_chosen(unsigned long node, const char *uname, int depth, void *data) { - int l; - const char *p; + int l = 0; + const char *p = NULL; + char *cmdline = data; pr_debug("search \"chosen\", depth: %d, uname: %s\n", depth, uname); - if (depth != 1 || !data || + if (depth != 1 || !cmdline || (strcmp(uname, "chosen") != 0 && strcmp(uname, "chosen@0") != 0)) return 0; early_init_dt_check_for_initrd(node); - /* Retrieve command line */ + /* Put CONFIG_CMDLINE in if forced or if data had nothing in it to start */ + if (overwrite_incoming_cmdline || !cmdline[0]) + strlcpy(cmdline, config_cmdline, COMMAND_LINE_SIZE); + + /* Retrieve command line unless forcing */ + if (read_dt_cmdline) p = of_get_flat_dt_prop(node, "bootargs", &l); - if (p != NULL && l > 0) - strlcpy(data, p, min((int)l, COMMAND_LINE_SIZE)); - /* - * CONFIG_CMDLINE is meant to be a default in case nothing else - * managed to set the command line, unless CONFIG_CMDLINE_FORCE - * is set in which case we override whatever was found earlier. - */ -#ifdef CONFIG_CMDLINE -#ifndef CONFIG_CMDLINE_FORCE - if (!((char *)data)[0]) -#endif - strlcpy(data, CONFIG_CMDLINE, COMMAND_LINE_SIZE); -#endif /* CONFIG_CMDLINE */ + if (p != NULL && l > 0) { + if (concat_cmdline) { + int cmdline_len; + int copy_len; + strlcat(cmdline, " ", COMMAND_LINE_SIZE); + cmdline_len = strlen(cmdline); + copy_len = COMMAND_LINE_SIZE - cmdline_len - 1; + copy_len = min((int)l, copy_len); + strncpy(cmdline + cmdline_len, p, copy_len); + cmdline[cmdline_len + copy_len] = '\0'; + } else { + strlcpy(cmdline, p, min((int)l, COMMAND_LINE_SIZE)); + } + } pr_debug("Command line is: %s\n", (char*)data); @@ -979,13 +1017,16 @@ } #ifdef CONFIG_HAVE_MEMBLOCK +#ifndef MIN_MEMBLOCK_ADDR +#define MIN_MEMBLOCK_ADDR __pa(PAGE_OFFSET) +#endif #ifndef MAX_MEMBLOCK_ADDR #define MAX_MEMBLOCK_ADDR ((phys_addr_t)~0) #endif void __init __weak early_init_dt_add_memory_arch(u64 base, u64 size) { - const u64 phys_offset = __pa(PAGE_OFFSET); + const u64 phys_offset = MIN_MEMBLOCK_ADDR; if (!PAGE_ALIGNED(base)) { if (size < PAGE_SIZE - (base & ~PAGE_MASK)) { diff -ruw linux-4.4.115/drivers/of/Kconfig linux-4.4.115-fbx/drivers/of/Kconfig --- linux-4.4.115/drivers/of/Kconfig 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/of/Kconfig 2019-01-22 16:16:26.015269154 +0100 @@ -102,6 +102,12 @@ config OF_RESOLVE bool +config OF_SLIMBUS + def_tristate SLIMBUS + depends on SLIMBUS + help + OpenFirmware SLIMBUS accessors + config OF_OVERLAY bool "Device Tree overlays" select OF_DYNAMIC @@ -112,4 +118,9 @@ While this option is selected automatically when needed, you can enable it manually to improve device tree unit test coverage. +config OF_BATTERYDATA + def_bool y + help + OpenFirmware BatteryData accessors + endif # OF diff -ruw linux-4.4.115/drivers/of/Makefile linux-4.4.115-fbx/drivers/of/Makefile --- linux-4.4.115/drivers/of/Makefile 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/of/Makefile 2019-01-22 16:16:26.015269154 +0100 @@ -14,5 +14,7 @@ obj-$(CONFIG_OF_RESERVED_MEM) += of_reserved_mem.o obj-$(CONFIG_OF_RESOLVE) += resolver.o obj-$(CONFIG_OF_OVERLAY) += overlay.o +obj-$(CONFIG_OF_SLIMBUS) += of_slimbus.o +obj-$(CONFIG_OF_BATTERYDATA) += of_batterydata.o obj-$(CONFIG_OF_UNITTEST) += unittest-data/ diff -ruw linux-4.4.115/drivers/of/of_reserved_mem.c linux-4.4.115-fbx/drivers/of/of_reserved_mem.c --- linux-4.4.115/drivers/of/of_reserved_mem.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/of/of_reserved_mem.c 2019-01-22 16:16:26.019269190 +0100 @@ -153,7 +153,7 @@ ret = early_init_dt_alloc_reserved_memory_arch(size, align, start, end, nomap, &base); if (ret == 0) { - pr_debug("Reserved memory: allocated memory for '%s' node: base %pa, size %ld MiB\n", + pr_info("Reserved memory: allocated memory for '%s' node: base %pa, size %ld MiB\n", uname, &base, (unsigned long)size / SZ_1M); break; @@ -165,7 +165,7 @@ ret = early_init_dt_alloc_reserved_memory_arch(size, align, 0, 0, nomap, &base); if (ret == 0) - pr_debug("Reserved memory: allocated memory for '%s' node: base %pa, size %ld MiB\n", + pr_info("Reserved memory: allocated memory for '%s' node: base %pa, size %ld MiB\n", uname, &base, (unsigned long)size / SZ_1M); } diff -ruw linux-4.4.115/drivers/of/platform.c linux-4.4.115-fbx/drivers/of/platform.c --- linux-4.4.115/drivers/of/platform.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/of/platform.c 2019-01-22 16:16:26.019269190 +0100 @@ -21,6 +21,7 @@ #include #include #include +#include #include const struct of_device_id of_default_bus_match_table[] = { @@ -139,7 +140,7 @@ } dev->dev.of_node = of_node_get(np); - dev->dev.parent = parent ? : &platform_bus; + dev->dev.parent = parent; if (bus_id) dev_set_name(&dev->dev, "%s", bus_id); @@ -185,6 +186,7 @@ dev->dev.platform_data = platform_data; of_dma_configure(&dev->dev, dev->dev.of_node); of_msi_configure(&dev->dev, dev->dev.of_node); + of_reserved_mem_device_init(&dev->dev); if (of_device_add(dev) != 0) { of_dma_deconfigure(&dev->dev); @@ -241,7 +243,7 @@ /* setup generic device info */ dev->dev.of_node = of_node_get(node); - dev->dev.parent = parent ? : &platform_bus; + dev->dev.parent = parent; dev->dev.platform_data = platform_data; if (bus_id) dev_set_name(&dev->dev, "%s", bus_id); diff -ruw linux-4.4.115/drivers/pci/host/Makefile linux-4.4.115-fbx/drivers/pci/host/Makefile --- linux-4.4.115/drivers/pci/host/Makefile 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/pci/host/Makefile 2019-01-22 16:16:26.031269299 +0100 @@ -4,6 +4,7 @@ obj-$(CONFIG_PCI_IMX6) += pci-imx6.o obj-$(CONFIG_PCI_MVEBU) += pci-mvebu.o obj-$(CONFIG_PCI_TEGRA) += pci-tegra.o +obj-$(CONFIG_PCI_MSM) += pci-msm.o obj-$(CONFIG_PCI_RCAR_GEN2) += pci-rcar-gen2.o obj-$(CONFIG_PCI_RCAR_GEN2_PCIE) += pcie-rcar.o obj-$(CONFIG_PCI_HOST_GENERIC) += pci-host-generic.o diff -ruw linux-4.4.115/drivers/pci/Kconfig linux-4.4.115-fbx/drivers/pci/Kconfig --- linux-4.4.115/drivers/pci/Kconfig 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/pci/Kconfig 2019-01-22 16:16:26.031269299 +0100 @@ -114,6 +114,20 @@ If unsure, say N. +config PCI_MSM + bool "MSM PCIe Controller driver" + depends on ARCH_QCOM && PCI + select PCI_DOMAINS + select PCI_DOMAINS_GENERIC + select PCI_MSI + help + Enables the PCIe functionality by configuring PCIe core on + MSM chipset and by enabling the ARM PCI framework extension. + The PCIe core is essential for communication between the host + and an endpoint. + + If unsure, say N. + config PCI_LABEL def_bool y if (DMI || ACPI) select NLS diff -ruw linux-4.4.115/drivers/perf/arm_pmu.c linux-4.4.115-fbx/drivers/perf/arm_pmu.c --- linux-4.4.115/drivers/perf/arm_pmu.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/perf/arm_pmu.c 2019-10-29 09:26:24.577212318 +0100 @@ -13,6 +13,7 @@ #include #include +#include #include #include #include @@ -22,6 +23,7 @@ #include #include #include +#include #include #include @@ -365,6 +367,8 @@ return err; } + armpmu->pmu_state = ARM_PMU_STATE_RUNNING; + return 0; } @@ -548,17 +552,10 @@ .stop = armpmu_stop, .read = armpmu_read, .filter_match = armpmu_filter_match, + .events_across_hotplug = 1, }; } -int armpmu_register(struct arm_pmu *armpmu, int type) -{ - armpmu_init(armpmu); - pr_info("enabled with %s PMU driver, %d counters available\n", - armpmu->name, armpmu->num_events); - return perf_pmu_register(&armpmu->pmu, armpmu->name, type); -} - /* Set at runtime when we know what CPU type we are. */ static struct arm_pmu *__oprofile_cpu_pmu; @@ -606,10 +603,12 @@ struct platform_device *pmu_device = cpu_pmu->plat_device; struct pmu_hw_events __percpu *hw_events = cpu_pmu->hw_events; + cpu_pmu->pmu_state = ARM_PMU_STATE_GOING_DOWN; + irqs = min(pmu_device->num_resources, num_possible_cpus()); irq = platform_get_irq(pmu_device, 0); - if (irq >= 0 && irq_is_percpu(irq)) { + if (irq > 0 && irq_is_percpu(irq)) { on_each_cpu(cpu_pmu_disable_percpu_irq, &irq, 1); free_percpu_irq(irq, &hw_events->percpu_pmu); } else { @@ -622,10 +621,11 @@ if (!cpumask_test_and_clear_cpu(cpu, &cpu_pmu->active_irqs)) continue; irq = platform_get_irq(pmu_device, i); - if (irq >= 0) + if (irq > 0) free_irq(irq, per_cpu_ptr(&hw_events->percpu_pmu, cpu)); } } + cpu_pmu->pmu_state = ARM_PMU_STATE_OFF; } static int cpu_pmu_request_irq(struct arm_pmu *cpu_pmu, irq_handler_t handler) @@ -644,7 +644,7 @@ } irq = platform_get_irq(pmu_device, 0); - if (irq >= 0 && irq_is_percpu(irq)) { + if (irq > 0 && irq_is_percpu(irq)) { err = request_percpu_irq(irq, handler, "arm-pmu", &hw_events->percpu_pmu); if (err) { @@ -653,6 +653,7 @@ return err; } on_each_cpu(cpu_pmu_enable_percpu_irq, &irq, 1); + cpu_pmu->percpu_irq = irq; } else { for (i = 0; i < irqs; ++i) { int cpu = i; @@ -692,6 +693,134 @@ return 0; } +struct cpu_pm_pmu_args { + struct arm_pmu *armpmu; + unsigned long cmd; + int cpu; + int ret; +}; + +#ifdef CONFIG_CPU_PM +static void cpu_pm_pmu_setup(struct arm_pmu *armpmu, unsigned long cmd) +{ + struct pmu_hw_events *hw_events = this_cpu_ptr(armpmu->hw_events); + struct perf_event *event; + int idx; + + for (idx = 0; idx < armpmu->num_events; idx++) { + /* + * If the counter is not used skip it, there is no + * need of stopping/restarting it. + */ + if (!test_bit(idx, hw_events->used_mask)) + continue; + + event = hw_events->events[idx]; + + switch (cmd) { + case CPU_PM_ENTER: + /* + * Stop and update the counter + */ + armpmu_stop(event, PERF_EF_UPDATE); + break; + case CPU_PM_EXIT: + case CPU_PM_ENTER_FAILED: + /* + * Restore and enable the counter. + * armpmu_start() indirectly calls + * + * perf_event_update_userpage() + * + * that requires RCU read locking to be functional, + * wrap the call within RCU_NONIDLE to make the + * RCU subsystem aware this cpu is not idle from + * an RCU perspective for the armpmu_start() call + * duration. + */ + RCU_NONIDLE(armpmu_start(event, PERF_EF_RELOAD)); + break; + default: + break; + } + } +} + +static void cpu_pm_pmu_common(void *info) +{ + struct cpu_pm_pmu_args *data = info; + struct arm_pmu *armpmu = data->armpmu; + unsigned long cmd = data->cmd; + int cpu = data->cpu; + struct pmu_hw_events *hw_events = this_cpu_ptr(armpmu->hw_events); + int enabled = bitmap_weight(hw_events->used_mask, armpmu->num_events); + + if (!cpumask_test_cpu(cpu, &armpmu->supported_cpus)) { + data->ret = NOTIFY_DONE; + return; + } + + if (!enabled) { + data->ret = NOTIFY_OK; + return; + } + + data->ret = NOTIFY_OK; + + switch (cmd) { + case CPU_PM_ENTER: + armpmu->stop(armpmu); + cpu_pm_pmu_setup(armpmu, cmd); + break; + case CPU_PM_EXIT: + case CPU_PM_ENTER_FAILED: + cpu_pm_pmu_setup(armpmu, cmd); + armpmu->start(armpmu); + break; + default: + data->ret = NOTIFY_DONE; + break; + } + + return; +} + +static int cpu_pm_pmu_notify(struct notifier_block *b, unsigned long cmd, + void *v) +{ + struct cpu_pm_pmu_args data = { + .armpmu = container_of(b, struct arm_pmu, cpu_pm_nb), + .cmd = cmd, + .cpu = smp_processor_id(), + }; + + /* + * Always reset the PMU registers on power-up even if + * there are no events running. + */ + if (cmd == CPU_PM_EXIT && data.armpmu->reset) + data.armpmu->reset(data.armpmu); + + cpu_pm_pmu_common(&data); + return data.ret; +} + +static int cpu_pm_pmu_register(struct arm_pmu *cpu_pmu) +{ + cpu_pmu->cpu_pm_nb.notifier_call = cpu_pm_pmu_notify; + return cpu_pm_register_notifier(&cpu_pmu->cpu_pm_nb); +} + +static void cpu_pm_pmu_unregister(struct arm_pmu *cpu_pmu) +{ + cpu_pm_unregister_notifier(&cpu_pmu->cpu_pm_nb); +} +#else +static inline int cpu_pm_pmu_register(struct arm_pmu *cpu_pmu) { return 0; } +static inline void cpu_pm_pmu_unregister(struct arm_pmu *cpu_pmu) { } +static inline void cpu_pm_pmu_common(void *info) { } +#endif + /* * PMU hardware loses all context when a CPU goes offline. * When a CPU is hotplugged back in, since some hardware registers are @@ -701,21 +830,49 @@ static int cpu_pmu_notify(struct notifier_block *b, unsigned long action, void *hcpu) { - int cpu = (unsigned long)hcpu; - struct arm_pmu *pmu = container_of(b, struct arm_pmu, hotplug_nb); - - if ((action & ~CPU_TASKS_FROZEN) != CPU_STARTING) - return NOTIFY_DONE; - - if (!cpumask_test_cpu(cpu, &pmu->supported_cpus)) - return NOTIFY_DONE; + int irq = -1; + unsigned long masked_action = (action & ~CPU_TASKS_FROZEN); + struct cpu_pm_pmu_args data = { + .armpmu = container_of(b, struct arm_pmu, hotplug_nb), + .cpu = (unsigned long)hcpu, + }; - if (pmu->reset) - pmu->reset(pmu); - else + if (!cpumask_test_cpu(data.cpu, &data.armpmu->supported_cpus)) return NOTIFY_DONE; + switch (masked_action) { + case CPU_STARTING: + case CPU_DOWN_FAILED: + /* + * Always reset the PMU registers on power-up even if + * there are no events running. + */ + if (data.armpmu->reset) + data.armpmu->reset(data.armpmu); + if (data.armpmu->pmu_state == ARM_PMU_STATE_RUNNING) { + if (data.armpmu->plat_device) + irq = data.armpmu->percpu_irq; + /* Arm the PMU IRQ before appearing. */ + if (irq > 0 && irq_is_percpu(irq)) + cpu_pmu_enable_percpu_irq(&irq); + data.cmd = CPU_PM_EXIT; + cpu_pm_pmu_common(&data); + } + return NOTIFY_OK; + case CPU_DYING: + if (data.armpmu->pmu_state != ARM_PMU_STATE_OFF) { + data.cmd = CPU_PM_ENTER; + cpu_pm_pmu_common(&data); + /* Disarm the PMU IRQ before disappearing. */ + if (data.armpmu->plat_device) + irq = data.armpmu->percpu_irq; + if (irq > 0 && irq_is_percpu(irq)) + cpu_pmu_disable_percpu_irq(&irq); + } return NOTIFY_OK; + default: + return NOTIFY_DONE; + } } static int cpu_pmu_init(struct arm_pmu *cpu_pmu) @@ -733,6 +890,10 @@ if (err) goto out_hw_events; + err = cpu_pm_pmu_register(cpu_pmu); + if (err) + goto out_unregister; + for_each_possible_cpu(cpu) { struct pmu_hw_events *events = per_cpu_ptr(cpu_hw_events, cpu); raw_spin_lock_init(&events->pmu_lock); @@ -754,6 +915,8 @@ return 0; +out_unregister: + unregister_cpu_notifier(&cpu_pmu->hotplug_nb); out_hw_events: free_percpu(cpu_hw_events); return err; @@ -761,6 +924,7 @@ static void cpu_pmu_destroy(struct arm_pmu *cpu_pmu) { + cpu_pm_pmu_unregister(cpu_pmu); unregister_cpu_notifier(&cpu_pmu->hotplug_nb); free_percpu(cpu_pmu->hw_events); } @@ -809,7 +973,7 @@ /* Check the IRQ type and prohibit a mix of PPIs and SPIs */ irq = platform_get_irq(pdev, i); - if (irq >= 0) { + if (irq > 0) { bool spi = !irq_is_percpu(irq); if (i > 0 && spi != using_spi) { @@ -888,14 +1052,29 @@ return -ENOMEM; } + armpmu_init(pmu); + if (!__oprofile_cpu_pmu) __oprofile_cpu_pmu = pmu; pmu->plat_device = pdev; + ret = cpu_pmu_init(pmu); + if (ret) + goto out_free; + if (node && (of_id = of_match_node(of_table, pdev->dev.of_node))) { init_fn = of_id->data; + pmu->secure_access = of_property_read_bool(pdev->dev.of_node, + "secure-reg-access"); + + /* arm64 systems boot only as non-secure */ + if (IS_ENABLED(CONFIG_ARM64) && pmu->secure_access) { + pr_warn("ignoring \"secure-reg-access\" property for arm64\n"); + pmu->secure_access = false; + } + ret = of_pmu_irq_cfg(pmu); if (!ret) ret = init_fn(pmu); @@ -905,24 +1084,98 @@ } if (ret) { - pr_info("failed to probe PMU!\n"); - goto out_free; + pr_info("%s: failed to probe PMU!\n", of_node_full_name(node)); + goto out_destroy; } - ret = cpu_pmu_init(pmu); - if (ret) - goto out_free; - - ret = armpmu_register(pmu, -1); + ret = perf_pmu_register(&pmu->pmu, pmu->name, -1); if (ret) goto out_destroy; + pmu->pmu_state = ARM_PMU_STATE_OFF; + pmu->percpu_irq = -1; + + pr_info("enabled with %s PMU driver, %d counters available\n", + pmu->name, pmu->num_events); + return 0; out_destroy: cpu_pmu_destroy(pmu); out_free: - pr_info("failed to register PMU devices!\n"); + pr_info("%s: failed to register PMU devices!\n", + of_node_full_name(node)); kfree(pmu); return ret; } + +static struct dentry *perf_debug_dir; + +struct dentry *perf_create_debug_dir(void) +{ + if (!perf_debug_dir) + perf_debug_dir = debugfs_create_dir("msm_perf", NULL); + return perf_debug_dir; +} + +#ifdef CONFIG_PERF_EVENTS_RESET_PMU_DEBUGFS +static __ref void reset_pmu_force(void) +{ + int cpu, ret; + u32 save_online_mask = 0; + + for_each_possible_cpu(cpu) { + if (!cpu_online(cpu)) { + save_online_mask |= BIT(cpu); + ret = cpu_up(cpu); + if (ret) + pr_err("Failed to bring up CPU: %d, ret: %d\n", + cpu, ret); + } + } + if (cpu_pmu && cpu_pmu->reset) + on_each_cpu(cpu_pmu->reset, NULL, 1); + if (cpu_pmu && cpu_pmu->plat_device) + armpmu_release_hardware(cpu_pmu); + for_each_possible_cpu(cpu) { + if ((save_online_mask & BIT(cpu)) && cpu_online(cpu)) { + ret = cpu_down(cpu); + if (ret) + pr_err("Failed to bring down CPU: %d, ret: %d\n", + cpu, ret); + } + } +} + +static int write_enabled_perfpmu_action(void *data, u64 val) +{ + if (val != 0) + reset_pmu_force(); + return 0; +} + +DEFINE_SIMPLE_ATTRIBUTE(fops_pmuaction, + NULL, write_enabled_perfpmu_action, "%llu\n"); + +int __init init_pmu_actions(void) +{ + struct dentry *dir; + struct dentry *file; + unsigned int value = 1; + + dir = perf_create_debug_dir(); + if (!dir) + return -ENOMEM; + file = debugfs_create_file("resetpmu", 0220, dir, + &value, &fops_pmuaction); + if (!file) + return -ENOMEM; + return 0; +} +#else +int __init init_pmu_actions(void) +{ + return 0; +} +#endif +late_initcall(init_pmu_actions); diff -ruw linux-4.4.115/drivers/perf/Makefile linux-4.4.115-fbx/drivers/perf/Makefile --- linux-4.4.115/drivers/perf/Makefile 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/perf/Makefile 2019-01-22 16:16:26.075269698 +0100 @@ -1 +1,2 @@ obj-$(CONFIG_ARM_PMU) += arm_pmu.o +obj-$(CONFIG_HW_PERF_EVENTS) += perf_event_armv8.o diff -ruw linux-4.4.115/drivers/phy/Makefile linux-4.4.115-fbx/drivers/phy/Makefile --- linux-4.4.115/drivers/phy/Makefile 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/phy/Makefile 2019-01-22 16:16:26.075269698 +0100 @@ -44,6 +44,9 @@ obj-$(CONFIG_PHY_QCOM_UFS) += phy-qcom-ufs.o obj-$(CONFIG_PHY_QCOM_UFS) += phy-qcom-ufs-qmp-20nm.o obj-$(CONFIG_PHY_QCOM_UFS) += phy-qcom-ufs-qmp-14nm.o +obj-$(CONFIG_PHY_QCOM_UFS) += phy-qcom-ufs-qmp-v3.o +obj-$(CONFIG_PHY_QCOM_UFS) += phy-qcom-ufs-qrbtc-v2.o +obj-$(CONFIG_PHY_QCOM_UFS) += phy-qcom-ufs-qmp-v3-660.o obj-$(CONFIG_PHY_TUSB1210) += phy-tusb1210.o obj-$(CONFIG_PHY_BRCMSTB_SATA) += phy-brcmstb-sata.o obj-$(CONFIG_PHY_PISTACHIO_USB) += phy-pistachio-usb.o diff -ruw linux-4.4.115/drivers/phy/phy-qcom-ufs.c linux-4.4.115-fbx/drivers/phy/phy-qcom-ufs.c --- linux-4.4.115/drivers/phy/phy-qcom-ufs.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/phy/phy-qcom-ufs.c 2019-01-22 16:16:26.079269734 +0100 @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2015, Linux Foundation. All rights reserved. + * Copyright (c) 2013-2016, Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -15,9 +15,9 @@ #include "phy-qcom-ufs-i.h" #define MAX_PROP_NAME 32 -#define VDDA_PHY_MIN_UV 1000000 -#define VDDA_PHY_MAX_UV 1000000 -#define VDDA_PLL_MIN_UV 1800000 +#define VDDA_PHY_MIN_UV 800000 +#define VDDA_PHY_MAX_UV 925000 +#define VDDA_PLL_MIN_UV 1200000 #define VDDA_PLL_MAX_UV 1800000 #define VDDP_REF_CLK_MIN_UV 1200000 #define VDDP_REF_CLK_MAX_UV 1200000 @@ -29,13 +29,24 @@ static int ufs_qcom_phy_base_init(struct platform_device *pdev, struct ufs_qcom_phy *phy_common); +void ufs_qcom_phy_write_tbl(struct ufs_qcom_phy *ufs_qcom_phy, + struct ufs_qcom_phy_calibration *tbl, + int tbl_size) +{ + int i; + + for (i = 0; i < tbl_size; i++) + writel_relaxed(tbl[i].cfg_value, + ufs_qcom_phy->mmio + tbl[i].reg_offset); +} +EXPORT_SYMBOL(ufs_qcom_phy_write_tbl); + int ufs_qcom_phy_calibrate(struct ufs_qcom_phy *ufs_qcom_phy, struct ufs_qcom_phy_calibration *tbl_A, int tbl_size_A, struct ufs_qcom_phy_calibration *tbl_B, int tbl_size_B, bool is_rate_B) { - int i; int ret = 0; if (!tbl_A) { @@ -44,9 +55,7 @@ goto out; } - for (i = 0; i < tbl_size_A; i++) - writel_relaxed(tbl_A[i].cfg_value, - ufs_qcom_phy->mmio + tbl_A[i].reg_offset); + ufs_qcom_phy_write_tbl(ufs_qcom_phy, tbl_A, tbl_size_A); /* * In case we would like to work in rate B, we need @@ -62,9 +71,7 @@ goto out; } - for (i = 0; i < tbl_size_B; i++) - writel_relaxed(tbl_B[i].cfg_value, - ufs_qcom_phy->mmio + tbl_B[i].reg_offset); + ufs_qcom_phy_write_tbl(ufs_qcom_phy, tbl_B, tbl_size_B); } /* flush buffered writes */ @@ -106,6 +113,14 @@ goto out; } + /* + * UFS PHY power management is managed by its parent (UFS host + * controller) hence set the no the no runtime PM callbacks flag + * on UFS PHY device to avoid any accidental attempt to call the + * PM callbacks for PHY device. + */ + pm_runtime_no_callbacks(&generic_phy->dev); + common_cfg->phy_spec_ops = phy_spec_ops; common_cfg->dev = dev; @@ -135,23 +150,21 @@ int err = 0; res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "phy_mem"); + if (!res) { + dev_err(dev, "%s: phy_mem resource not found\n", __func__); + err = -ENOMEM; + goto out; + } + phy_common->mmio = devm_ioremap_resource(dev, res); if (IS_ERR((void const *)phy_common->mmio)) { err = PTR_ERR((void const *)phy_common->mmio); phy_common->mmio = NULL; dev_err(dev, "%s: ioremap for phy_mem resource failed %d\n", __func__, err); - return err; } - - /* "dev_ref_clk_ctrl_mem" is optional resource */ - res = platform_get_resource_byname(pdev, IORESOURCE_MEM, - "dev_ref_clk_ctrl_mem"); - phy_common->dev_ref_clk_ctrl_mmio = devm_ioremap_resource(dev, res); - if (IS_ERR((void const *)phy_common->dev_ref_clk_ctrl_mmio)) - phy_common->dev_ref_clk_ctrl_mmio = NULL; - - return 0; +out: + return err; } static int __ufs_qcom_phy_clk_get(struct phy *phy, @@ -187,15 +200,19 @@ { int err; - err = ufs_qcom_phy_clk_get(generic_phy, "tx_iface_clk", - &phy_common->tx_iface_clk); - if (err) - goto out; + /* + * tx_iface_clk does not exist in newer version of ufs-phy HW, + * so don't return error if it is not found + */ + __ufs_qcom_phy_clk_get(generic_phy, "tx_iface_clk", + &phy_common->tx_iface_clk, false); - err = ufs_qcom_phy_clk_get(generic_phy, "rx_iface_clk", - &phy_common->rx_iface_clk); - if (err) - goto out; + /* + * rx_iface_clk does not exist in newer version of ufs-phy HW, + * so don't return error if it is not found + */ + __ufs_qcom_phy_clk_get(generic_phy, "rx_iface_clk", + &phy_common->rx_iface_clk, false); err = ufs_qcom_phy_clk_get(generic_phy, "ref_clk_src", &phy_common->ref_clk_src); @@ -211,7 +228,15 @@ err = ufs_qcom_phy_clk_get(generic_phy, "ref_clk", &phy_common->ref_clk); + if (err) + goto out; + /* + * "ref_aux_clk" is optional and only supported by certain + * phy versions, don't abort init if it's not found. + */ + __ufs_qcom_phy_clk_get(generic_phy, "ref_aux_clk", + &phy_common->ref_aux_clk, false); out: return err; } @@ -230,7 +255,6 @@ err = ufs_qcom_phy_init_vreg(generic_phy, &phy_common->vdda_phy, "vdda-phy"); - if (err) goto out; @@ -251,6 +275,14 @@ char prop_name[MAX_PROP_NAME]; + if (dev->of_node) { + snprintf(prop_name, MAX_PROP_NAME, "%s-supply", name); + if (!of_parse_phandle(dev->of_node, prop_name, 0)) { + dev_dbg(dev, "No vreg data found for %s\n", prop_name); + return optional ? err : -ENODATA; + } + } + vreg->name = kstrdup(name, GFP_KERNEL); if (!vreg->name) { err = -ENOMEM; @@ -421,9 +453,26 @@ goto out_disable_parent; } + /* + * "ref_aux_clk" is optional clock and only supported by certain + * phy versions, hence make sure that clk reference is available + * before trying to enable the clock. + */ + if (phy->ref_aux_clk) { + ret = clk_prepare_enable(phy->ref_aux_clk); + if (ret) { + dev_err(phy->dev, "%s: ref_aux_clk enable failed %d\n", + __func__, ret); + goto out_disable_ref; + } + } + phy->is_ref_clk_enabled = true; goto out; +out_disable_ref: + if (phy->ref_clk) + clk_disable_unprepare(phy->ref_clk); out_disable_parent: if (phy->ref_clk_parent) clk_disable_unprepare(phy->ref_clk_parent); @@ -464,6 +513,13 @@ struct ufs_qcom_phy *phy = get_ufs_qcom_phy(generic_phy); if (phy->is_ref_clk_enabled) { + /* + * "ref_aux_clk" is optional clock and only supported by + * certain phy versions, hence make sure that clk reference + * is available before trying to disable the clock. + */ + if (phy->ref_aux_clk) + clk_disable_unprepare(phy->ref_aux_clk); clk_disable_unprepare(phy->ref_clk); /* * "ref_clk_parent" is optional clock hence make sure that clk @@ -477,56 +533,6 @@ } EXPORT_SYMBOL_GPL(ufs_qcom_phy_disable_ref_clk); -#define UFS_REF_CLK_EN (1 << 5) - -static void ufs_qcom_phy_dev_ref_clk_ctrl(struct phy *generic_phy, bool enable) -{ - struct ufs_qcom_phy *phy = get_ufs_qcom_phy(generic_phy); - - if (phy->dev_ref_clk_ctrl_mmio && - (enable ^ phy->is_dev_ref_clk_enabled)) { - u32 temp = readl_relaxed(phy->dev_ref_clk_ctrl_mmio); - - if (enable) - temp |= UFS_REF_CLK_EN; - else - temp &= ~UFS_REF_CLK_EN; - - /* - * If we are here to disable this clock immediately after - * entering into hibern8, we need to make sure that device - * ref_clk is active atleast 1us after the hibern8 enter. - */ - if (!enable) - udelay(1); - - writel_relaxed(temp, phy->dev_ref_clk_ctrl_mmio); - /* ensure that ref_clk is enabled/disabled before we return */ - wmb(); - /* - * If we call hibern8 exit after this, we need to make sure that - * device ref_clk is stable for atleast 1us before the hibern8 - * exit command. - */ - if (enable) - udelay(1); - - phy->is_dev_ref_clk_enabled = enable; - } -} - -void ufs_qcom_phy_enable_dev_ref_clk(struct phy *generic_phy) -{ - ufs_qcom_phy_dev_ref_clk_ctrl(generic_phy, true); -} -EXPORT_SYMBOL_GPL(ufs_qcom_phy_enable_dev_ref_clk); - -void ufs_qcom_phy_disable_dev_ref_clk(struct phy *generic_phy) -{ - ufs_qcom_phy_dev_ref_clk_ctrl(generic_phy, false); -} -EXPORT_SYMBOL_GPL(ufs_qcom_phy_disable_dev_ref_clk); - /* Turn ON M-PHY RMMI interface clocks */ int ufs_qcom_phy_enable_iface_clk(struct phy *generic_phy) { @@ -536,6 +542,9 @@ if (phy->is_iface_clk_enabled) goto out; + if (!phy->tx_iface_clk) + goto out; + ret = clk_prepare_enable(phy->tx_iface_clk); if (ret) { dev_err(phy->dev, "%s: tx_iface_clk enable failed %d\n", @@ -561,6 +570,9 @@ { struct ufs_qcom_phy *phy = get_ufs_qcom_phy(generic_phy); + if (!phy->tx_iface_clk) + return; + if (phy->is_iface_clk_enabled) { clk_disable_unprepare(phy->tx_iface_clk); clk_disable_unprepare(phy->rx_iface_clk); @@ -591,19 +603,26 @@ struct ufs_qcom_phy *ufs_qcom_phy = get_ufs_qcom_phy(generic_phy); int ret = 0; - if (!ufs_qcom_phy->phy_spec_ops->set_tx_lane_enable) { - dev_err(ufs_qcom_phy->dev, "%s: set_tx_lane_enable() callback is not supported\n", - __func__); - ret = -ENOTSUPP; - } else { + if (ufs_qcom_phy->phy_spec_ops->set_tx_lane_enable) ufs_qcom_phy->phy_spec_ops->set_tx_lane_enable(ufs_qcom_phy, tx_lanes); - } return ret; } EXPORT_SYMBOL_GPL(ufs_qcom_phy_set_tx_lane_enable); +int ufs_qcom_phy_ctrl_rx_linecfg(struct phy *generic_phy, bool ctrl) +{ + struct ufs_qcom_phy *ufs_qcom_phy = get_ufs_qcom_phy(generic_phy); + int ret = 0; + + if (ufs_qcom_phy->phy_spec_ops->ctrl_rx_linecfg) + ufs_qcom_phy->phy_spec_ops->ctrl_rx_linecfg(ufs_qcom_phy, ctrl); + + return ret; +} +EXPORT_SYMBOL_GPL(ufs_qcom_phy_ctrl_rx_linecfg); + void ufs_qcom_phy_save_controller_version(struct phy *generic_phy, u8 major, u16 minor, u16 step) { @@ -636,6 +655,14 @@ } EXPORT_SYMBOL_GPL(ufs_qcom_phy_calibrate_phy); +const char *ufs_qcom_phy_name(struct phy *phy) +{ + struct ufs_qcom_phy *ufs_qcom_phy = get_ufs_qcom_phy(phy); + + return ufs_qcom_phy->name; +} +EXPORT_SYMBOL(ufs_qcom_phy_name); + int ufs_qcom_phy_remove(struct phy *generic_phy, struct ufs_qcom_phy *ufs_qcom_phy) { @@ -747,3 +774,39 @@ return 0; } EXPORT_SYMBOL_GPL(ufs_qcom_phy_power_off); + +int ufs_qcom_phy_configure_lpm(struct phy *generic_phy, bool enable) +{ + struct ufs_qcom_phy *ufs_qcom_phy = get_ufs_qcom_phy(generic_phy); + int ret = 0; + + if (ufs_qcom_phy->phy_spec_ops->configure_lpm) { + ret = ufs_qcom_phy->phy_spec_ops-> + configure_lpm(ufs_qcom_phy, enable); + if (ret) + dev_err(ufs_qcom_phy->dev, + "%s: configure_lpm(%s) failed %d\n", + __func__, enable ? "enable" : "disable", ret); + } + + return ret; +} +EXPORT_SYMBOL(ufs_qcom_phy_configure_lpm); + +void ufs_qcom_phy_dump_regs(struct ufs_qcom_phy *phy, int offset, + int len, char *prefix) +{ + print_hex_dump(KERN_ERR, prefix, + len > 4 ? DUMP_PREFIX_OFFSET : DUMP_PREFIX_NONE, + 16, 4, phy->mmio + offset, len, false); +} +EXPORT_SYMBOL(ufs_qcom_phy_dump_regs); + +void ufs_qcom_phy_dbg_register_dump(struct phy *generic_phy) +{ + struct ufs_qcom_phy *ufs_qcom_phy = get_ufs_qcom_phy(generic_phy); + + if (ufs_qcom_phy->phy_spec_ops->dbg_register_dump) + ufs_qcom_phy->phy_spec_ops->dbg_register_dump(ufs_qcom_phy); +} +EXPORT_SYMBOL(ufs_qcom_phy_dbg_register_dump); diff -ruw linux-4.4.115/drivers/phy/phy-qcom-ufs-i.h linux-4.4.115-fbx/drivers/phy/phy-qcom-ufs-i.h --- linux-4.4.115/drivers/phy/phy-qcom-ufs-i.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/phy/phy-qcom-ufs-i.h 2019-01-22 16:16:26.079269734 +0100 @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2015, Linux Foundation. All rights reserved. + * Copyright (c) 2013-2016, Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -91,6 +91,7 @@ struct clk *ref_clk_src; struct clk *ref_clk_parent; struct clk *ref_clk; + struct clk *ref_aux_clk; bool is_ref_clk_enabled; bool is_dev_ref_clk_enabled; struct ufs_qcom_phy_vreg vdda_pll; @@ -107,6 +108,23 @@ */ #define UFS_QCOM_PHY_QUIRK_HIBERN8_EXIT_AFTER_PHY_PWR_COLLAPSE BIT(0) + /* + * On some UFS PHY HW revisions, UFS PHY power up calibration sequence + * cannot have SVS mode configuration otherwise calibration result + * cannot be used in HS-G3. So there are additional register writes must + * be done after the PHY is initialized but before the controller + * requests hibernate exit. + */ + #define UFS_QCOM_PHY_QUIRK_SVS_MODE BIT(1) + + /* + * On some UFS PHY HW revisions, UFS PHY power up calibration sequence + * requires manual VCO tuning code and its better to rely on the VCO + * tuning code programmed by boot loader. Enable this quirk to enable + * programming the manually tuned VCO code. + */ + #define UFS_QCOM_PHY_QUIRK_VCO_MANUAL_TUNING BIT(2) + u8 host_ctrl_rev_major; u16 host_ctrl_rev_minor; u16 host_ctrl_rev_step; @@ -116,6 +134,7 @@ int cached_regs_table_size; bool is_powered_on; struct ufs_qcom_phy_specific_ops *phy_spec_ops; + u32 vco_tune1_mode1; }; /** @@ -127,15 +146,23 @@ * @is_physical_coding_sublayer_ready: pointer to a function that * checks pcs readiness. returns 0 for success and non-zero for error. * @set_tx_lane_enable: pointer to a function that enable tx lanes + * @ctrl_rx_linecfg: pointer to a function that controls the Host Rx LineCfg + * state. * @power_control: pointer to a function that controls analog rail of phy * and writes to QSERDES_RX_SIGDET_CNTRL attribute + * @configure_lpm: pointer to a function that configures the phy + * for low power mode. + * @dbg_register_dump: pointer to a function that dumps phy registers for debug. */ struct ufs_qcom_phy_specific_ops { int (*calibrate_phy)(struct ufs_qcom_phy *phy, bool is_rate_B); void (*start_serdes)(struct ufs_qcom_phy *phy); int (*is_physical_coding_sublayer_ready)(struct ufs_qcom_phy *phy); void (*set_tx_lane_enable)(struct ufs_qcom_phy *phy, u32 val); + void (*ctrl_rx_linecfg)(struct ufs_qcom_phy *phy, bool ctrl); void (*power_control)(struct ufs_qcom_phy *phy, bool val); + int (*configure_lpm)(struct ufs_qcom_phy *phy, bool enable); + void (*dbg_register_dump)(struct ufs_qcom_phy *phy); }; struct ufs_qcom_phy *get_ufs_qcom_phy(struct phy *generic_phy); @@ -156,4 +183,9 @@ struct ufs_qcom_phy_calibration *tbl_A, int tbl_size_A, struct ufs_qcom_phy_calibration *tbl_B, int tbl_size_B, bool is_rate_B); +void ufs_qcom_phy_write_tbl(struct ufs_qcom_phy *ufs_qcom_phy, + struct ufs_qcom_phy_calibration *tbl, + int tbl_size); +void ufs_qcom_phy_dump_regs(struct ufs_qcom_phy *phy, + int offset, int len, char *prefix); #endif diff -ruw linux-4.4.115/drivers/phy/phy-qcom-ufs-qmp-14nm.c linux-4.4.115-fbx/drivers/phy/phy-qcom-ufs-qmp-14nm.c --- linux-4.4.115/drivers/phy/phy-qcom-ufs-qmp-14nm.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/phy/phy-qcom-ufs-qmp-14nm.c 2019-01-22 16:16:26.079269734 +0100 @@ -15,19 +15,49 @@ #include "phy-qcom-ufs-qmp-14nm.h" #define UFS_PHY_NAME "ufs_phy_qmp_14nm" -#define UFS_PHY_VDDA_PHY_UV (925000) static int ufs_qcom_phy_qmp_14nm_phy_calibrate(struct ufs_qcom_phy *ufs_qcom_phy, bool is_rate_B) { - int tbl_size_A = ARRAY_SIZE(phy_cal_table_rate_A); - int tbl_size_B = ARRAY_SIZE(phy_cal_table_rate_B); int err; + int tbl_size_A, tbl_size_B; + struct ufs_qcom_phy_calibration *tbl_A, *tbl_B; + u8 major = ufs_qcom_phy->host_ctrl_rev_major; + u16 minor = ufs_qcom_phy->host_ctrl_rev_minor; + u16 step = ufs_qcom_phy->host_ctrl_rev_step; + + tbl_size_B = ARRAY_SIZE(phy_cal_table_rate_B); + tbl_B = phy_cal_table_rate_B; + + if ((major == 0x2) && (minor == 0x000) && (step == 0x0000)) { + tbl_A = phy_cal_table_rate_A_2_0_0; + tbl_size_A = ARRAY_SIZE(phy_cal_table_rate_A_2_0_0); + } else if ((major == 0x2) && (minor == 0x001) && (step == 0x0000)) { + tbl_A = phy_cal_table_rate_A_2_1_0; + tbl_size_A = ARRAY_SIZE(phy_cal_table_rate_A_2_1_0); + } else if ((major == 0x2) && (minor == 0x002) && (step == 0x0000)) { + tbl_A = phy_cal_table_rate_A_2_2_0; + tbl_size_A = ARRAY_SIZE(phy_cal_table_rate_A_2_2_0); + tbl_B = phy_cal_table_rate_B_2_2_0; + tbl_size_B = ARRAY_SIZE(phy_cal_table_rate_B_2_2_0); + } else { + dev_err(ufs_qcom_phy->dev, + "%s: Unknown UFS-PHY version (major 0x%x minor 0x%x step 0x%x), no calibration values\n", + __func__, major, minor, step); + err = -ENODEV; + goto out; + } - err = ufs_qcom_phy_calibrate(ufs_qcom_phy, phy_cal_table_rate_A, - tbl_size_A, phy_cal_table_rate_B, tbl_size_B, is_rate_B); - + err = ufs_qcom_phy_calibrate(ufs_qcom_phy, + tbl_A, tbl_size_A, + tbl_B, tbl_size_B, + is_rate_B); + + if (ufs_qcom_phy->quirks & UFS_QCOM_PHY_QUIRK_VCO_MANUAL_TUNING) + writel_relaxed(ufs_qcom_phy->vco_tune1_mode1, + ufs_qcom_phy->mmio + QSERDES_COM_VCO_TUNE1_MODE1); +out: if (err) dev_err(ufs_qcom_phy->dev, "%s: ufs_qcom_phy_calibrate() failed %d\n", @@ -38,8 +68,15 @@ static void ufs_qcom_phy_qmp_14nm_advertise_quirks(struct ufs_qcom_phy *phy_common) { + u8 major = phy_common->host_ctrl_rev_major; + u16 minor = phy_common->host_ctrl_rev_minor; + u16 step = phy_common->host_ctrl_rev_step; + + if ((major == 0x2) && (minor == 0x000) && (step == 0x0000)) phy_common->quirks = - UFS_QCOM_PHY_QUIRK_HIBERN8_EXIT_AFTER_PHY_PWR_COLLAPSE; + UFS_QCOM_PHY_QUIRK_HIBERN8_EXIT_AFTER_PHY_PWR_COLLAPSE | + UFS_QCOM_PHY_QUIRK_SVS_MODE | + UFS_QCOM_PHY_QUIRK_VCO_MANUAL_TUNING; } static int ufs_qcom_phy_qmp_14nm_init(struct phy *generic_phy) @@ -61,24 +98,66 @@ __func__, err); goto out; } - phy_common->vdda_phy.max_uV = UFS_PHY_VDDA_PHY_UV; - phy_common->vdda_phy.min_uV = UFS_PHY_VDDA_PHY_UV; ufs_qcom_phy_qmp_14nm_advertise_quirks(phy_common); + if (phy_common->quirks & UFS_QCOM_PHY_QUIRK_VCO_MANUAL_TUNING) { + phy_common->vco_tune1_mode1 = readl_relaxed(phy_common->mmio + + QSERDES_COM_VCO_TUNE1_MODE1); + dev_info(phy_common->dev, "%s: vco_tune1_mode1 0x%x\n", + __func__, phy_common->vco_tune1_mode1); + } + out: return err; } static -void ufs_qcom_phy_qmp_14nm_power_control(struct ufs_qcom_phy *phy, bool val) +void ufs_qcom_phy_qmp_14nm_power_control(struct ufs_qcom_phy *phy, + bool power_ctrl) { - writel_relaxed(val ? 0x1 : 0x0, phy->mmio + UFS_PHY_POWER_DOWN_CONTROL); + bool is_workaround_req = false; + + if (phy->quirks & + UFS_QCOM_PHY_QUIRK_HIBERN8_EXIT_AFTER_PHY_PWR_COLLAPSE) + is_workaround_req = true; + + if (!power_ctrl) { + /* apply PHY analog power collapse */ + if (is_workaround_req) { + /* assert common reset before analog power collapse */ + writel_relaxed(0x1, phy->mmio + QSERDES_COM_SW_RESET); + /* + * make sure that reset is propogated before analog + * power collapse + */ + mb(); + } + /* apply analog power collapse */ + writel_relaxed(0x0, phy->mmio + UFS_PHY_POWER_DOWN_CONTROL); + /* + * Make sure that PHY knows its analog rail is going to be + * powered OFF. + */ + mb(); + } else { + /* bring PHY out of analog power collapse */ + writel_relaxed(0x1, phy->mmio + UFS_PHY_POWER_DOWN_CONTROL); /* * Before any transactions involving PHY, ensure PHY knows - * that it's analog rail is powered ON (or OFF). + * that it's analog rail is powered ON. */ mb(); + if (is_workaround_req) { + /* + * de-assert common reset after coming out of analog + * power collapse + */ + writel_relaxed(0x0, phy->mmio + QSERDES_COM_SW_RESET); + /* make common reset is de-asserted before proceeding */ + mb(); + } + } } static inline @@ -90,6 +169,23 @@ */ } +static +void ufs_qcom_phy_qmp_14nm_ctrl_rx_linecfg(struct ufs_qcom_phy *phy, bool ctrl) +{ + u32 temp; + + temp = readl_relaxed(phy->mmio + UFS_PHY_LINECFG_DISABLE); + + if (ctrl) /* enable RX LineCfg */ + temp &= ~UFS_PHY_RX_LINECFG_DISABLE_BIT; + else /* disable RX LineCfg */ + temp |= UFS_PHY_RX_LINECFG_DISABLE_BIT; + + writel_relaxed(temp, phy->mmio + UFS_PHY_LINECFG_DISABLE); + /* make sure that RX LineCfg config applied before we return */ + mb(); +} + static inline void ufs_qcom_phy_qmp_14nm_start_serdes(struct ufs_qcom_phy *phy) { u32 tmp; @@ -109,9 +205,24 @@ err = readl_poll_timeout(phy_common->mmio + UFS_PHY_PCS_READY_STATUS, val, (val & MASK_PCS_READY), 10, 1000000); - if (err) + if (err) { dev_err(phy_common->dev, "%s: poll for pcs failed err = %d\n", __func__, err); + goto out; + } + + if (phy_common->quirks & UFS_QCOM_PHY_QUIRK_SVS_MODE) { + int i; + + for (i = 0; i < ARRAY_SIZE(phy_svs_mode_config_2_0_0); i++) + writel_relaxed(phy_svs_mode_config_2_0_0[i].cfg_value, + (phy_common->mmio + + phy_svs_mode_config_2_0_0[i].reg_offset)); + /* apply above configuration immediately */ + mb(); + } + +out: return err; } @@ -128,6 +239,7 @@ .start_serdes = ufs_qcom_phy_qmp_14nm_start_serdes, .is_physical_coding_sublayer_ready = ufs_qcom_phy_qmp_14nm_is_pcs_ready, .set_tx_lane_enable = ufs_qcom_phy_qmp_14nm_set_tx_lane_enable, + .ctrl_rx_linecfg = ufs_qcom_phy_qmp_14nm_ctrl_rx_linecfg, .power_control = ufs_qcom_phy_qmp_14nm_power_control, }; diff -ruw linux-4.4.115/drivers/phy/phy-qcom-ufs-qmp-14nm.h linux-4.4.115-fbx/drivers/phy/phy-qcom-ufs-qmp-14nm.h --- linux-4.4.115/drivers/phy/phy-qcom-ufs-qmp-14nm.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/phy/phy-qcom-ufs-qmp-14nm.h 2019-01-22 16:16:26.079269734 +0100 @@ -27,12 +27,14 @@ #define QSERDES_COM_BG_TIMER COM_OFF(0x0C) #define QSERDES_COM_BIAS_EN_CLKBUFLR_EN COM_OFF(0x34) #define QSERDES_COM_SYS_CLK_CTRL COM_OFF(0x3C) +#define QSERDES_COM_PLL_IVCO COM_OFF(0x48) #define QSERDES_COM_LOCK_CMP1_MODE0 COM_OFF(0x4C) #define QSERDES_COM_LOCK_CMP2_MODE0 COM_OFF(0x50) #define QSERDES_COM_LOCK_CMP3_MODE0 COM_OFF(0x54) #define QSERDES_COM_LOCK_CMP1_MODE1 COM_OFF(0x58) #define QSERDES_COM_LOCK_CMP2_MODE1 COM_OFF(0x5C) #define QSERDES_COM_LOCK_CMP3_MODE1 COM_OFF(0x60) +#define QSERDES_COM_BG_TRIM COM_OFF(0x70) #define QSERDES_COM_CP_CTRL_MODE0 COM_OFF(0x78) #define QSERDES_COM_CP_CTRL_MODE1 COM_OFF(0x7C) #define QSERDES_COM_PLL_RCTRL_MODE0 COM_OFF(0x84) @@ -41,6 +43,7 @@ #define QSERDES_COM_PLL_CCTRL_MODE1 COM_OFF(0x94) #define QSERDES_COM_SYSCLK_EN_SEL COM_OFF(0xAC) #define QSERDES_COM_RESETSM_CNTRL COM_OFF(0xB4) +#define QSERDES_COM_RESCODE_DIV_NUM COM_OFF(0xC4) #define QSERDES_COM_LOCK_CMP_EN COM_OFF(0xC8) #define QSERDES_COM_LOCK_CMP_CFG COM_OFF(0xCC) #define QSERDES_COM_DEC_START_MODE0 COM_OFF(0xD0) @@ -61,19 +64,35 @@ #define QSERDES_COM_VCO_TUNE2_MODE0 COM_OFF(0x130) #define QSERDES_COM_VCO_TUNE1_MODE1 COM_OFF(0x134) #define QSERDES_COM_VCO_TUNE2_MODE1 COM_OFF(0x138) +#define QSERDES_COM_VCO_TUNE_INITVAL1 COM_OFF(0x13C) +#define QSERDES_COM_VCO_TUNE_INITVAL2 COM_OFF(0x140) #define QSERDES_COM_VCO_TUNE_TIMER1 COM_OFF(0x144) #define QSERDES_COM_VCO_TUNE_TIMER2 COM_OFF(0x148) #define QSERDES_COM_CLK_SELECT COM_OFF(0x174) #define QSERDES_COM_HSCLK_SEL COM_OFF(0x178) #define QSERDES_COM_CORECLK_DIV COM_OFF(0x184) +#define QSERDES_COM_SW_RESET COM_OFF(0x188) #define QSERDES_COM_CORE_CLK_EN COM_OFF(0x18C) #define QSERDES_COM_CMN_CONFIG COM_OFF(0x194) #define QSERDES_COM_SVS_MODE_CLK_SEL COM_OFF(0x19C) +#define QSERDES_COM_DEBUG_BUS0 COM_OFF(0x1A0) +#define QSERDES_COM_DEBUG_BUS1 COM_OFF(0x1A4) +#define QSERDES_COM_DEBUG_BUS2 COM_OFF(0x1A8) +#define QSERDES_COM_DEBUG_BUS3 COM_OFF(0x1AC) +#define QSERDES_COM_DEBUG_BUS_SEL COM_OFF(0x1B0) +#define QSERDES_COM_CMN_MISC2 COM_OFF(0x1B8) #define QSERDES_COM_CORECLK_DIV_MODE1 COM_OFF(0x1BC) /* UFS PHY registers */ #define UFS_PHY_PHY_START PHY_OFF(0x00) #define UFS_PHY_POWER_DOWN_CONTROL PHY_OFF(0x04) +#define UFS_PHY_TX_LARGE_AMP_DRV_LVL PHY_OFF(0x34) +#define UFS_PHY_TX_SMALL_AMP_DRV_LVL PHY_OFF(0x3C) +#define UFS_PHY_RX_MIN_STALL_NOCONFIG_TIME_CAP PHY_OFF(0xCC) +#define UFS_PHY_LINECFG_DISABLE PHY_OFF(0x138) +#define UFS_PHY_RX_SYM_RESYNC_CTRL PHY_OFF(0x13C) +#define UFS_PHY_RX_SIGDET_CTRL2 PHY_OFF(0x148) +#define UFS_PHY_RX_PWM_GEAR_BAND PHY_OFF(0x154) #define UFS_PHY_PCS_READY_STATUS PHY_OFF(0x168) /* UFS PHY TX registers */ @@ -81,7 +100,12 @@ #define QSERDES_TX_LANE_MODE TX_OFF(0, 0x94) /* UFS PHY RX registers */ +#define QSERDES_RX_UCDR_SVS_SO_GAIN_HALF RX_OFF(0, 0x30) +#define QSERDES_RX_UCDR_SVS_SO_GAIN_QUARTER RX_OFF(0, 0x34) +#define QSERDES_RX_UCDR_SVS_SO_GAIN_EIGHTH RX_OFF(0, 0x38) +#define QSERDES_RX_UCDR_SVS_SO_GAIN RX_OFF(0, 0x3C) #define QSERDES_RX_UCDR_FASTLOCK_FO_GAIN RX_OFF(0, 0x40) +#define QSERDES_RX_UCDR_SO_SATURATION_ENABLE RX_OFF(0, 0x48) #define QSERDES_RX_RX_TERM_BW RX_OFF(0, 0x90) #define QSERDES_RX_RX_EQ_GAIN1_LSB RX_OFF(0, 0xC4) #define QSERDES_RX_RX_EQ_GAIN1_MSB RX_OFF(0, 0xC8) @@ -93,6 +117,8 @@ #define QSERDES_RX_SIGDET_DEGLITCH_CNTRL RX_OFF(0, 0x11C) #define QSERDES_RX_RX_INTERFACE_MODE RX_OFF(0, 0x12C) +#define UFS_PHY_RX_LINECFG_DISABLE_BIT BIT(1) + /* * This structure represents the 14nm specific phy. * common_cfg MUST remain the first field in this structure @@ -105,12 +131,102 @@ struct ufs_qcom_phy common_cfg; }; -static struct ufs_qcom_phy_calibration phy_cal_table_rate_A[] = { +static struct ufs_qcom_phy_calibration phy_cal_table_rate_A_2_0_0[] = { UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_POWER_DOWN_CONTROL, 0x01), UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_CMN_CONFIG, 0x0e), - UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_SYSCLK_EN_SEL, 0xd7), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_SYSCLK_EN_SEL, 0x17), UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_CLK_SELECT, 0x30), - UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_SYS_CLK_CTRL, 0x06), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_SYS_CLK_CTRL, 0x02), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_BG_TIMER, 0x0a), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_HSCLK_SEL, 0x05), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_CORECLK_DIV, 0x0a), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_CORECLK_DIV_MODE1, 0x0a), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP_EN, 0x01), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE_CTRL, 0x1C), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_RESETSM_CNTRL, 0x20), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_CORE_CLK_EN, 0x00), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP_CFG, 0x00), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE_TIMER1, 0xff), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE_TIMER2, 0x3f), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE_MAP, 0x14), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_SVS_MODE_CLK_SEL, 0x05), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DEC_START_MODE0, 0x82), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x00), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x00), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x00), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_CP_CTRL_MODE0, 0x0b), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_RCTRL_MODE0, 0x16), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_CCTRL_MODE0, 0x28), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE1_MODE0, 0x3F), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE2_MODE0, 0x01), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP1_MODE0, 0xff), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP2_MODE0, 0x0c), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP3_MODE0, 0x00), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DEC_START_MODE1, 0x98), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DIV_FRAC_START1_MODE1, 0x00), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DIV_FRAC_START2_MODE1, 0x00), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DIV_FRAC_START3_MODE1, 0x00), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_CP_CTRL_MODE1, 0x0b), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_RCTRL_MODE1, 0x16), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_CCTRL_MODE1, 0x28), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_INTEGLOOP_GAIN0_MODE1, 0x80), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_INTEGLOOP_GAIN1_MODE1, 0x00), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE2_MODE1, 0x00), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP1_MODE1, 0x32), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP2_MODE1, 0x0f), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP3_MODE1, 0x00), + + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX_HIGHZ_TRANSCEIVER_BIAS_DRVR_EN, 0x45), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX_LANE_MODE, 0x06), + + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_SIGDET_LVL, 0x24), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_SIGDET_CNTRL, 0x0F), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_INTERFACE_MODE, 0x00), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x1E), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0B), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_TERM_BW, 0x5B), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN1_LSB, 0xFF), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN1_MSB, 0x3F), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN2_LSB, 0xFF), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN2_MSB, 0x3F), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0D), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_IVCO, 0x0F), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_BG_TRIM, 0x0F), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_RESCODE_DIV_NUM, 0x15), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_CMN_MISC2, 0x1F), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_UCDR_SVS_SO_GAIN_HALF, 0x04), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_UCDR_SVS_SO_GAIN_QUARTER, 0x04), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_UCDR_SVS_SO_GAIN, 0x04), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_UCDR_SO_SATURATION_ENABLE, 0x4B), + UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_RX_SIGDET_CTRL2, 0x6c), + UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TX_LARGE_AMP_DRV_LVL, 0x12), + UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TX_SMALL_AMP_DRV_LVL, 0x06), + UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_RX_MIN_STALL_NOCONFIG_TIME_CAP, 0x28), + UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_RX_SYM_RESYNC_CTRL, 0x03), + + /* + * UFS_PHY_RX_PWM_GEAR_BAND configuration is changed after the power up + * sequence so make sure that this register gets set to power on reset + * value. This is required in case power up sequence is initiated after + * this register value got changed to value other than power on reset + * value. + */ + UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_RX_PWM_GEAR_BAND, 0x55), +}; + +/* + * For 2.1.0 revision, SVS mode configuration can be part of PHY power + * up sequence itself. + */ +static struct ufs_qcom_phy_calibration phy_cal_table_rate_A_2_1_0[] = { + UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_POWER_DOWN_CONTROL, 0x01), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_CMN_CONFIG, 0x0e), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_SYSCLK_EN_SEL, 0x14), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_CLK_SELECT, 0x30), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_SYS_CLK_CTRL, 0x02), UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08), UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_BG_TIMER, 0x0a), UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_HSCLK_SEL, 0x05), @@ -155,23 +271,133 @@ UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP3_MODE1, 0x00), UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX_HIGHZ_TRANSCEIVER_BIAS_DRVR_EN, 0x45), - UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX_LANE_MODE, 0x02), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX_LANE_MODE, 0x06), UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_SIGDET_LVL, 0x24), - UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_SIGDET_CNTRL, 0x02), - UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_INTERFACE_MODE, 0x00), - UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x18), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_SIGDET_CNTRL, 0x0F), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_INTERFACE_MODE, 0x40), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x1E), UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0B), UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_TERM_BW, 0x5B), UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN1_LSB, 0xFF), UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN1_MSB, 0x3F), UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN2_LSB, 0xFF), - UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN2_MSB, 0x0F), - UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0E), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN2_MSB, 0x3F), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0D), + + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_IVCO, 0x0F), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_BG_TRIM, 0x0F), + UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_RX_PWM_GEAR_BAND, 0x15), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_RESCODE_DIV_NUM, 0x15), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_CMN_MISC2, 0x1F), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_UCDR_SVS_SO_GAIN_HALF, 0x04), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_UCDR_SVS_SO_GAIN_QUARTER, 0x04), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_UCDR_SVS_SO_GAIN, 0x04), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_UCDR_SO_SATURATION_ENABLE, 0x4B), + UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_RX_SIGDET_CTRL2, 0x6c), + UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TX_LARGE_AMP_DRV_LVL, 0x12), + UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TX_SMALL_AMP_DRV_LVL, 0x06), + UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_RX_MIN_STALL_NOCONFIG_TIME_CAP, 0x28), + UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_RX_SYM_RESYNC_CTRL, 0x03), +}; + +static struct ufs_qcom_phy_calibration phy_cal_table_rate_A_2_2_0[] = { + UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_POWER_DOWN_CONTROL, 0x01), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_CMN_CONFIG, 0x0e), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_SYSCLK_EN_SEL, 0x14), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_CLK_SELECT, 0x30), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_SYS_CLK_CTRL, 0x02), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_BG_TIMER, 0x0a), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_HSCLK_SEL, 0x00), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_CORECLK_DIV, 0x0a), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_CORECLK_DIV_MODE1, 0x0a), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP_EN, 0x01), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE_CTRL, 0x00), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_RESETSM_CNTRL, 0x20), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_CORE_CLK_EN, 0x00), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP_CFG, 0x00), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE_TIMER1, 0xff), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE_TIMER2, 0x3f), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE_MAP, 0x04), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_SVS_MODE_CLK_SEL, 0x05), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DEC_START_MODE0, 0x82), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x00), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x00), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x00), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_CP_CTRL_MODE0, 0x0b), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_RCTRL_MODE0, 0x16), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_CCTRL_MODE0, 0x28), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE1_MODE0, 0x28), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE2_MODE0, 0x02), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP1_MODE0, 0xff), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP2_MODE0, 0x0c), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP3_MODE0, 0x00), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DEC_START_MODE1, 0x98), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DIV_FRAC_START1_MODE1, 0x00), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DIV_FRAC_START2_MODE1, 0x00), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DIV_FRAC_START3_MODE1, 0x00), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_CP_CTRL_MODE1, 0x0b), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_RCTRL_MODE1, 0x16), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_CCTRL_MODE1, 0x28), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_INTEGLOOP_GAIN0_MODE1, 0x80), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_INTEGLOOP_GAIN1_MODE1, 0x00), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE1_MODE1, 0xd6), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE2_MODE1, 0x00), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP1_MODE1, 0x32), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP2_MODE1, 0x0f), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP3_MODE1, 0x00), + + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX_HIGHZ_TRANSCEIVER_BIAS_DRVR_EN, 0x45), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX_LANE_MODE, 0x06), + + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_SIGDET_LVL, 0x24), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_SIGDET_CNTRL, 0x0F), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_INTERFACE_MODE, 0x40), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x1E), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0B), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_TERM_BW, 0x5B), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN1_LSB, 0xFF), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN1_MSB, 0x3F), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN2_LSB, 0xFF), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN2_MSB, 0x3F), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0D), + + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_IVCO, 0x0F), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_BG_TRIM, 0x0F), + UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_RX_PWM_GEAR_BAND, 0x15), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_RESCODE_DIV_NUM, 0x40), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_CMN_MISC2, 0x63), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_UCDR_SVS_SO_GAIN_HALF, 0x04), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_UCDR_SVS_SO_GAIN_QUARTER, 0x04), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_UCDR_SVS_SO_GAIN, 0x04), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_UCDR_SO_SATURATION_ENABLE, 0x4B), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE_INITVAL1, 0xFF), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE_INITVAL2, 0x00), + UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_RX_SIGDET_CTRL2, 0x6c), + UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TX_LARGE_AMP_DRV_LVL, 0x0A), + UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TX_SMALL_AMP_DRV_LVL, 0x02), + UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_RX_MIN_STALL_NOCONFIG_TIME_CAP, 0x28), + UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_RX_SYM_RESYNC_CTRL, 0x03), }; static struct ufs_qcom_phy_calibration phy_cal_table_rate_B[] = { UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE_MAP, 0x54), }; +static struct ufs_qcom_phy_calibration phy_cal_table_rate_B_2_2_0[] = { + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE_MAP, 0x44), +}; + +/* + * For 2.0.0 revision, apply this SVS mode configuration after PHY power + * up sequence is completed. + */ +static struct ufs_qcom_phy_calibration phy_svs_mode_config_2_0_0[] = { + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_INTERFACE_MODE, 0x40), + UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_RX_PWM_GEAR_BAND, 0x15), +}; + #endif diff -ruw linux-4.4.115/drivers/phy/phy-qcom-ufs-qmp-20nm.c linux-4.4.115-fbx/drivers/phy/phy-qcom-ufs-qmp-20nm.c --- linux-4.4.115/drivers/phy/phy-qcom-ufs-qmp-20nm.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/phy/phy-qcom-ufs-qmp-20nm.c 2019-01-22 16:16:26.079269734 +0100 @@ -147,6 +147,23 @@ mb(); } +static +void ufs_qcom_phy_qmp_20nm_ctrl_rx_linecfg(struct ufs_qcom_phy *phy, bool ctrl) +{ + u32 temp; + + temp = readl_relaxed(phy->mmio + UFS_PHY_LINECFG_DISABLE); + + if (ctrl) /* enable RX LineCfg */ + temp &= ~UFS_PHY_RX_LINECFG_DISABLE_BIT; + else /* disable RX LineCfg */ + temp |= UFS_PHY_RX_LINECFG_DISABLE_BIT; + + writel_relaxed(temp, phy->mmio + UFS_PHY_LINECFG_DISABLE); + /* make sure that RX LineCfg config applied before we return */ + mb(); +} + static inline void ufs_qcom_phy_qmp_20nm_start_serdes(struct ufs_qcom_phy *phy) { u32 tmp; @@ -171,7 +188,7 @@ return err; } -static const struct phy_ops ufs_qcom_phy_qmp_20nm_phy_ops = { +struct phy_ops ufs_qcom_phy_qmp_20nm_phy_ops = { .init = ufs_qcom_phy_qmp_20nm_init, .exit = ufs_qcom_phy_exit, .power_on = ufs_qcom_phy_power_on, @@ -179,11 +196,12 @@ .owner = THIS_MODULE, }; -static struct ufs_qcom_phy_specific_ops phy_20nm_ops = { +struct ufs_qcom_phy_specific_ops phy_20nm_ops = { .calibrate_phy = ufs_qcom_phy_qmp_20nm_phy_calibrate, .start_serdes = ufs_qcom_phy_qmp_20nm_start_serdes, .is_physical_coding_sublayer_ready = ufs_qcom_phy_qmp_20nm_is_pcs_ready, .set_tx_lane_enable = ufs_qcom_phy_qmp_20nm_set_tx_lane_enable, + .ctrl_rx_linecfg = ufs_qcom_phy_qmp_20nm_ctrl_rx_linecfg, .power_control = ufs_qcom_phy_qmp_20nm_power_control, }; diff -ruw linux-4.4.115/drivers/phy/phy-qcom-ufs-qmp-20nm.h linux-4.4.115-fbx/drivers/phy/phy-qcom-ufs-qmp-20nm.h --- linux-4.4.115/drivers/phy/phy-qcom-ufs-qmp-20nm.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/phy/phy-qcom-ufs-qmp-20nm.h 2019-01-22 16:16:26.079269734 +0100 @@ -101,6 +101,7 @@ #define UFS_PHY_RX_MIN_SAVE_CONFIG_TIME_CAPABILITY PHY_OFF(0xE8) #define UFS_PHY_RX_PWM_BURST_CLOSURE_LENGTH_CAPABILITY PHY_OFF(0xFC) #define UFS_PHY_RX_MIN_ACTIVATETIME_CAPABILITY PHY_OFF(0x100) +#define UFS_PHY_LINECFG_DISABLE PHY_OFF(0x134) #define UFS_PHY_RX_SIGDET_CTRL3 PHY_OFF(0x14c) #define UFS_PHY_RMMI_ATTR_CTRL PHY_OFF(0x160) #define UFS_PHY_RMMI_RX_CFGUPDT_L1 (1 << 7) @@ -118,6 +119,7 @@ #define UFS_PHY_PCS_READY_STATUS PHY_OFF(0x174) #define UFS_PHY_TX_LANE_ENABLE_MASK 0x3 +#define UFS_PHY_RX_LINECFG_DISABLE_BIT BIT(1) /* * This structure represents the 20nm specific phy. diff -ruw linux-4.4.115/drivers/pinctrl/devicetree.c linux-4.4.115-fbx/drivers/pinctrl/devicetree.c --- linux-4.4.115/drivers/pinctrl/devicetree.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/pinctrl/devicetree.c 2019-01-22 16:16:26.087269806 +0100 @@ -195,8 +195,13 @@ propname = kasprintf(GFP_KERNEL, "pinctrl-%d", state); prop = of_find_property(np, propname, &size); kfree(propname); - if (!prop) + if (!prop) { + if (!state) { + ret = -EINVAL; + goto err; + } break; + } list = prop->value; size /= sizeof(*list); diff -ruw linux-4.4.115/drivers/pinctrl/qcom/Kconfig linux-4.4.115-fbx/drivers/pinctrl/qcom/Kconfig --- linux-4.4.115/drivers/pinctrl/qcom/Kconfig 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/pinctrl/qcom/Kconfig 2019-01-22 16:16:26.111270024 +0100 @@ -96,4 +96,42 @@ which are using SSBI for communication with SoC. Example PMIC's devices are pm8058 and pm8921. +config PINCTRL_MSM8998 + tristate "Qualcomm MSM8998 pin controller driver" + depends on GPIOLIB && OF + select PINCTRL_MSM + help + This is the pinctrl, pinmux, pinconf and gpiolib driver for the + Qualcomm TLMM block found in the Qualcomm MSM8998 platform. + +config PINCTRL_MSM8996 + tristate "Qualcomm MSM8996 pin controller driver" + depends on GPIOLIB && OF + select PINCTRL_MSM + help + This is the pinctrl, pinmux, pinconf and gpiolib driver for the + Qualcomm TLMM block found in the Qualcomm MSM8996 platform. + +config PINCTRL_SDM660 + tristate "Qualcomm SDM660 pin controller driver" + depends on GPIOLIB && OF + select PINCTRL_MSM + help + This is the pinctrl, pinmux, pinconf and gpiolib driver for the + Qualcomm TLMM block found in the Qualcomm SDM660 platform. + +config PINCTRL_WCD + tristate "Qualcomm Technologies, Inc WCD pin controller driver" + depends on WCD934X_CODEC + help + This is the pinctrl, pinmux, pinconf and gpiolib driver for the + WCD gpio controller block. + +config PINCTRL_LPI + tristate "Qualcomm Technologies, Inc LPI pin controller driver" + depends on GPIOLIB && OF + help + This is the pinctrl, pinmux, pinconf and gpiolib driver for the + LPI gpio controller block. + endif diff -ruw linux-4.4.115/drivers/pinctrl/qcom/Makefile linux-4.4.115-fbx/drivers/pinctrl/qcom/Makefile --- linux-4.4.115/drivers/pinctrl/qcom/Makefile 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/pinctrl/qcom/Makefile 2019-01-22 16:16:26.111270024 +0100 @@ -12,3 +12,8 @@ obj-$(CONFIG_PINCTRL_QCOM_SPMI_PMIC) += pinctrl-spmi-mpp.o obj-$(CONFIG_PINCTRL_QCOM_SSBI_PMIC) += pinctrl-ssbi-gpio.o obj-$(CONFIG_PINCTRL_QCOM_SSBI_PMIC) += pinctrl-ssbi-mpp.o +obj-$(CONFIG_PINCTRL_MSM8996) += pinctrl-msm8996.o +obj-$(CONFIG_PINCTRL_MSM8998) += pinctrl-msm8998.o +obj-$(CONFIG_PINCTRL_SDM660) += pinctrl-sdm660.o +obj-$(CONFIG_PINCTRL_WCD) += pinctrl-wcd.o +obj-$(CONFIG_PINCTRL_LPI) += pinctrl-lpi.o diff -ruw linux-4.4.115/drivers/pinctrl/qcom/pinctrl-msm.c linux-4.4.115-fbx/drivers/pinctrl/qcom/pinctrl-msm.c --- linux-4.4.115/drivers/pinctrl/qcom/pinctrl-msm.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/pinctrl/qcom/pinctrl-msm.c 2019-10-29 09:26:24.585212397 +0100 @@ -1,6 +1,6 @@ /* * Copyright (c) 2013, Sony Mobile Communications AB. - * Copyright (c) 2013, The Linux Foundation. All rights reserved. + * Copyright (c) 2013-2017, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -27,9 +27,9 @@ #include #include #include +#include #include -#include - +#include #include "../core.h" #include "../pinconf.h" #include "pinctrl-msm.h" @@ -44,6 +44,7 @@ * @pctrl: pinctrl handle. * @chip: gpiochip handle. * @restart_nb: restart notifier block. + * @irq_chip_extn: MPM extension of TLMM irqchip. * @irq: parent irq for the TLMM irq_chip. * @lock: Spinlock to protect register resources as well * as msm_pinctrl data structures. @@ -58,6 +59,7 @@ struct pinctrl_dev *pctrl; struct gpio_chip chip; struct notifier_block restart_nb; + struct irq_chip *irq_chip_extn; int irq; spinlock_t lock; @@ -69,6 +71,8 @@ void __iomem *regs; }; +static struct msm_pinctrl *msm_pinctrl_data; + static inline struct msm_pinctrl *to_msm_pinctrl(struct gpio_chip *gc) { return container_of(gc, struct msm_pinctrl, chip); @@ -421,7 +425,6 @@ writel(val, pctrl->regs + g->ctl_reg); spin_unlock_irqrestore(&pctrl->lock, flags); - return 0; } @@ -583,6 +586,8 @@ clear_bit(d->hwirq, pctrl->enabled_irqs); spin_unlock_irqrestore(&pctrl->lock, flags); + if (pctrl->irq_chip_extn->irq_mask) + pctrl->irq_chip_extn->irq_mask(d); } static void msm_gpio_irq_unmask(struct irq_data *d) @@ -597,6 +602,10 @@ spin_lock_irqsave(&pctrl->lock, flags); + val = readl(pctrl->regs + g->intr_status_reg); + val &= ~BIT(g->intr_status_bit); + writel(val, pctrl->regs + g->intr_status_reg); + val = readl(pctrl->regs + g->intr_cfg_reg); val |= BIT(g->intr_enable_bit); writel(val, pctrl->regs + g->intr_cfg_reg); @@ -604,6 +613,8 @@ set_bit(d->hwirq, pctrl->enabled_irqs); spin_unlock_irqrestore(&pctrl->lock, flags); + if (pctrl->irq_chip_extn->irq_unmask) + pctrl->irq_chip_extn->irq_unmask(d); } static void msm_gpio_irq_ack(struct irq_data *d) @@ -722,6 +733,9 @@ else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) irq_set_handler_locked(d, handle_edge_irq); + if (pctrl->irq_chip_extn->irq_set_type) + pctrl->irq_chip_extn->irq_set_type(d, type); + return 0; } @@ -737,6 +751,9 @@ spin_unlock_irqrestore(&pctrl->lock, flags); + if (pctrl->irq_chip_extn->irq_set_wake) + pctrl->irq_chip_extn->irq_set_wake(d, on); + return 0; } @@ -783,6 +800,22 @@ chained_irq_exit(chip, desc); } +/* + * Add MPM extensions for the irqchip. + * Enable the MPM driver to enable/disable + * suspend/resume based on gpio interrupts + */ + +struct irq_chip mpm_pinctrl_extn = { + .irq_eoi = NULL, + .irq_mask = NULL, + .irq_unmask = NULL, + .irq_retrigger = NULL, + .irq_set_type = NULL, + .irq_set_wake = NULL, + .irq_disable = NULL, +}; + static int msm_gpio_init(struct msm_pinctrl *pctrl) { struct gpio_chip *chip; @@ -826,6 +859,7 @@ gpiochip_set_chained_irqchip(chip, &msm_gpio_irq_chip, pctrl->irq, msm_gpio_irq_handler); + of_mpm_init(); return 0; } @@ -865,6 +899,52 @@ } } +#ifdef CONFIG_PM +static int msm_pinctrl_suspend(void) +{ + return 0; +} + +static void msm_pinctrl_resume(void) +{ + int i, irq; + u32 val; + unsigned long flags; + struct irq_desc *desc; + const struct msm_pingroup *g; + const char *name = "null"; + struct msm_pinctrl *pctrl = msm_pinctrl_data; + + if (!msm_show_resume_irq_mask) + return; + + spin_lock_irqsave(&pctrl->lock, flags); + for_each_set_bit(i, pctrl->enabled_irqs, pctrl->chip.ngpio) { + g = &pctrl->soc->groups[i]; + val = readl_relaxed(pctrl->regs + g->intr_status_reg); + if (val & BIT(g->intr_status_bit)) { + irq = irq_find_mapping(pctrl->chip.irqdomain, i); + desc = irq_to_desc(irq); + if (desc == NULL) + name = "stray irq"; + else if (desc->action && desc->action->name) + name = desc->action->name; + + pr_warn("%s: %d triggered %s\n", __func__, irq, name); + } + } + spin_unlock_irqrestore(&pctrl->lock, flags); +} +#else +#define msm_pinctrl_suspend NULL +#define msm_pinctrl_resume NULL +#endif + +static struct syscore_ops msm_pinctrl_pm_ops = { + .suspend = msm_pinctrl_suspend, + .resume = msm_pinctrl_resume, +}; + int msm_pinctrl_probe(struct platform_device *pdev, const struct msm_pinctrl_soc_data *soc_data) { @@ -872,7 +952,8 @@ struct resource *res; int ret; - pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL); + msm_pinctrl_data = pctrl = devm_kzalloc(&pdev->dev, + sizeof(*pctrl), GFP_KERNEL); if (!pctrl) { dev_err(&pdev->dev, "Can't allocate msm_pinctrl\n"); return -ENOMEM; @@ -910,9 +991,10 @@ pinctrl_unregister(pctrl->pctrl); return ret; } - + pctrl->irq_chip_extn = &mpm_pinctrl_extn; platform_set_drvdata(pdev, pctrl); + register_syscore_ops(&msm_pinctrl_pm_ops); dev_dbg(&pdev->dev, "Probed Qualcomm pinctrl driver\n"); return 0; @@ -927,6 +1009,7 @@ pinctrl_unregister(pctrl->pctrl); unregister_restart_handler(&pctrl->restart_nb); + unregister_syscore_ops(&msm_pinctrl_pm_ops); return 0; } diff -ruw linux-4.4.115/drivers/pinctrl/qcom/pinctrl-msm.h linux-4.4.115-fbx/drivers/pinctrl/qcom/pinctrl-msm.h --- linux-4.4.115/drivers/pinctrl/qcom/pinctrl-msm.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/pinctrl/qcom/pinctrl-msm.h 2019-01-22 16:16:26.111270024 +0100 @@ -121,4 +121,5 @@ const struct msm_pinctrl_soc_data *soc_data); int msm_pinctrl_remove(struct platform_device *pdev); +extern int msm_show_resume_irq_mask; #endif diff -ruw linux-4.4.115/drivers/platform/goldfish/Kconfig linux-4.4.115-fbx/drivers/platform/goldfish/Kconfig --- linux-4.4.115/drivers/platform/goldfish/Kconfig 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/platform/goldfish/Kconfig 2019-01-22 16:16:26.143270313 +0100 @@ -1,5 +1,23 @@ +menuconfig GOLDFISH + bool "Platform support for Goldfish virtual devices" + depends on X86_32 || X86_64 || ARM || ARM64 || MIPS + ---help--- + Say Y here to get to see options for the Goldfish virtual platform. + This option alone does not add any kernel code. + + Unless you are building for the Android Goldfish emulator say N here. + +if GOLDFISH + +config GOLDFISH_BUS + bool "Goldfish platform bus" + ---help--- + This is a virtual bus to host Goldfish Android Virtual Devices. + config GOLDFISH_PIPE tristate "Goldfish virtual device for QEMU pipes" ---help--- This is a virtual device to drive the QEMU pipe interface used by the Goldfish Android Virtual Device. + +endif # GOLDFISH diff -ruw linux-4.4.115/drivers/platform/goldfish/Makefile linux-4.4.115-fbx/drivers/platform/goldfish/Makefile --- linux-4.4.115/drivers/platform/goldfish/Makefile 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/platform/goldfish/Makefile 2019-01-22 16:16:26.143270313 +0100 @@ -1,5 +1,6 @@ # # Makefile for Goldfish platform specific drivers # -obj-$(CONFIG_GOLDFISH) += pdev_bus.o -obj-$(CONFIG_GOLDFISH_PIPE) += goldfish_pipe.o +obj-$(CONFIG_GOLDFISH_BUS) += pdev_bus.o +obj-$(CONFIG_GOLDFISH_PIPE) += goldfish_pipe_all.o +goldfish_pipe_all-objs := goldfish_pipe.o goldfish_pipe_v2.o diff -ruw linux-4.4.115/drivers/platform/Kconfig linux-4.4.115-fbx/drivers/platform/Kconfig --- linux-4.4.115/drivers/platform/Kconfig 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/platform/Kconfig 2019-01-22 16:16:26.143270313 +0100 @@ -4,8 +4,8 @@ if MIPS source "drivers/platform/mips/Kconfig" endif -if GOLDFISH source "drivers/platform/goldfish/Kconfig" -endif source "drivers/platform/chrome/Kconfig" + +source "drivers/platform/msm/Kconfig" diff -ruw linux-4.4.115/drivers/platform/Makefile linux-4.4.115-fbx/drivers/platform/Makefile --- linux-4.4.115/drivers/platform/Makefile 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/platform/Makefile 2019-01-22 16:16:26.143270313 +0100 @@ -7,3 +7,5 @@ obj-$(CONFIG_OLPC) += olpc/ obj-$(CONFIG_GOLDFISH) += goldfish/ obj-$(CONFIG_CHROME_PLATFORMS) += chrome/ +obj-$(CONFIG_ARCH_QCOM) += msm/ + diff -ruw linux-4.4.115/drivers/power/Kconfig linux-4.4.115-fbx/drivers/power/Kconfig --- linux-4.4.115/drivers/power/Kconfig 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/power/Kconfig 2019-10-29 09:26:24.625212788 +0100 @@ -449,6 +449,18 @@ Say Y to include support for Summit Microelectronics SMB347 Battery Charger. +config BATTERY_BQ28400 + tristate "BQ28400 battery driver" + depends on I2C + default n + help + Say Y here to enable support for batteries with BQ28400 (I2C) chips. + The bq28400 Texas Instruments Inc device monitors the battery + charging/discharging status via Rsens resistor, typically 10 mohm. + It monitors the battery temperature via Thermistor. + The device monitors the battery level (Relative-State-Of-Charge). + The device is SBS compliant, providing battery info over I2C. + config CHARGER_TPS65090 tristate "TPS65090 battery charger driver" depends on MFD_TPS65090 @@ -509,7 +521,9 @@ AXP20x PMIC. source "drivers/power/reset/Kconfig" +source "drivers/power/supply/Kconfig" endif # POWER_SUPPLY source "drivers/power/avs/Kconfig" +source "drivers/power/qcom/Kconfig" diff -ruw linux-4.4.115/drivers/power/Makefile linux-4.4.115-fbx/drivers/power/Makefile --- linux-4.4.115/drivers/power/Makefile 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/power/Makefile 2019-01-22 16:16:26.211270929 +0100 @@ -72,3 +72,5 @@ obj-$(CONFIG_POWER_RESET) += reset/ obj-$(CONFIG_AXP288_FUEL_GAUGE) += axp288_fuel_gauge.o obj-$(CONFIG_AXP288_CHARGER) += axp288_charger.o +obj-$(CONFIG_ARCH_QCOM) += qcom/ +obj-$(CONFIG_POWER_SUPPLY) += supply/ diff -ruw linux-4.4.115/drivers/power/power_supply_sysfs.c linux-4.4.115-fbx/drivers/power/power_supply_sysfs.c --- linux-4.4.115/drivers/power/power_supply_sysfs.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/power/power_supply_sysfs.c 2019-10-29 09:26:24.629212827 +0100 @@ -44,19 +44,23 @@ struct device_attribute *attr, char *buf) { static char *type_text[] = { - "Unknown", "Battery", "UPS", "Mains", "USB", - "USB_DCP", "USB_CDP", "USB_ACA" + "Unknown", "Battery", "UPS", "Mains", "USB", "USB_DCP", + "USB_CDP", "USB_ACA", "USB_HVDCP", "USB_HVDCP_3", "USB_PD", + "Wireless", "USB_FLOAT", "BMS", "Parallel", "Main", "Wipower", + "TYPEC", "TYPEC_UFP", "TYPEC_DFP" }; static char *status_text[] = { "Unknown", "Charging", "Discharging", "Not charging", "Full" }; static char *charge_type[] = { - "Unknown", "N/A", "Trickle", "Fast" + "Unknown", "N/A", "Trickle", "Fast", + "Taper" }; static char *health_text[] = { "Unknown", "Good", "Overheat", "Dead", "Over voltage", "Unspecified failure", "Cold", "Watchdog timer expire", - "Safety timer expire" + "Safety timer expire", + "Warm", "Cool", "Hot" }; static char *technology_text[] = { "Unknown", "NiMH", "Li-ion", "Li-poly", "LiFe", "NiCd", @@ -68,6 +72,17 @@ static char *scope_text[] = { "Unknown", "System", "Device" }; + static char *typec_text[] = { + "Nothing attached", "Sink attached", "Powered cable w/ sink", + "Debug Accessory", "Audio Adapter", "Powered cable w/o sink", + "Source attached (default current)", + "Source attached (medium current)", + "Source attached (high current)", + "Non compliant", + }; + static char *typec_pr_text[] = { + "none", "dual power role", "sink", "source" + }; ssize_t ret = 0; struct power_supply *psy = dev_get_drvdata(dev); const ptrdiff_t off = attr - power_supply_attrs; @@ -99,13 +114,25 @@ return sprintf(buf, "%s\n", technology_text[value.intval]); else if (off == POWER_SUPPLY_PROP_CAPACITY_LEVEL) return sprintf(buf, "%s\n", capacity_level_text[value.intval]); - else if (off == POWER_SUPPLY_PROP_TYPE) + else if (off == POWER_SUPPLY_PROP_TYPE || + off == POWER_SUPPLY_PROP_REAL_TYPE) return sprintf(buf, "%s\n", type_text[value.intval]); else if (off == POWER_SUPPLY_PROP_SCOPE) return sprintf(buf, "%s\n", scope_text[value.intval]); + else if (off == POWER_SUPPLY_PROP_TYPEC_MODE) + return sprintf(buf, "%s\n", typec_text[value.intval]); + else if (off == POWER_SUPPLY_PROP_TYPEC_POWER_ROLE) + return sprintf(buf, "%s\n", typec_pr_text[value.intval]); + else if (off == POWER_SUPPLY_PROP_DIE_HEALTH) + return sprintf(buf, "%s\n", health_text[value.intval]); + else if (off == POWER_SUPPLY_PROP_CONNECTOR_HEALTH) + return sprintf(buf, "%s\n", health_text[value.intval]); else if (off >= POWER_SUPPLY_PROP_MODEL_NAME) return sprintf(buf, "%s\n", value.strval); + if (off == POWER_SUPPLY_PROP_CHARGE_COUNTER_EXT) + return sprintf(buf, "%lld\n", value.int64val); + else return sprintf(buf, "%d\n", value.intval); } @@ -162,6 +189,8 @@ POWER_SUPPLY_ATTR(charge_full), POWER_SUPPLY_ATTR(charge_empty), POWER_SUPPLY_ATTR(charge_now), + POWER_SUPPLY_ATTR(charge_now_raw), + POWER_SUPPLY_ATTR(charge_now_error), POWER_SUPPLY_ATTR(charge_avg), POWER_SUPPLY_ATTR(charge_counter), POWER_SUPPLY_ATTR(constant_charge_current), @@ -181,6 +210,7 @@ POWER_SUPPLY_ATTR(capacity_alert_min), POWER_SUPPLY_ATTR(capacity_alert_max), POWER_SUPPLY_ATTR(capacity_level), + POWER_SUPPLY_ATTR(capacity_raw), POWER_SUPPLY_ATTR(temp), POWER_SUPPLY_ATTR(temp_max), POWER_SUPPLY_ATTR(temp_min), @@ -197,10 +227,91 @@ POWER_SUPPLY_ATTR(scope), POWER_SUPPLY_ATTR(charge_term_current), POWER_SUPPLY_ATTR(calibrate), + /* Local extensions */ + POWER_SUPPLY_ATTR(usb_hc), + POWER_SUPPLY_ATTR(usb_otg), + POWER_SUPPLY_ATTR(battery_charging_enabled), + POWER_SUPPLY_ATTR(charging_enabled), + POWER_SUPPLY_ATTR(step_charging_enabled), + POWER_SUPPLY_ATTR(step_charging_step), + POWER_SUPPLY_ATTR(pin_enabled), + POWER_SUPPLY_ATTR(input_suspend), + POWER_SUPPLY_ATTR(input_voltage_regulation), + POWER_SUPPLY_ATTR(input_current_max), + POWER_SUPPLY_ATTR(input_current_trim), + POWER_SUPPLY_ATTR(input_current_settled), + POWER_SUPPLY_ATTR(input_voltage_settled), + POWER_SUPPLY_ATTR(bypass_vchg_loop_debouncer), + POWER_SUPPLY_ATTR(charge_counter_shadow), + POWER_SUPPLY_ATTR(hi_power), + POWER_SUPPLY_ATTR(low_power), + POWER_SUPPLY_ATTR(temp_cool), + POWER_SUPPLY_ATTR(temp_warm), + POWER_SUPPLY_ATTR(temp_cold), + POWER_SUPPLY_ATTR(temp_hot), + POWER_SUPPLY_ATTR(system_temp_level), + POWER_SUPPLY_ATTR(resistance), + POWER_SUPPLY_ATTR(resistance_capacitive), + POWER_SUPPLY_ATTR(resistance_id), + POWER_SUPPLY_ATTR(resistance_now), + POWER_SUPPLY_ATTR(flash_current_max), + POWER_SUPPLY_ATTR(update_now), + POWER_SUPPLY_ATTR(esr_count), + POWER_SUPPLY_ATTR(buck_freq), + POWER_SUPPLY_ATTR(boost_current), + POWER_SUPPLY_ATTR(safety_timer_enabled), + POWER_SUPPLY_ATTR(charge_done), + POWER_SUPPLY_ATTR(flash_active), + POWER_SUPPLY_ATTR(flash_trigger), + POWER_SUPPLY_ATTR(force_tlim), + POWER_SUPPLY_ATTR(dp_dm), + POWER_SUPPLY_ATTR(input_current_limited), + POWER_SUPPLY_ATTR(input_current_now), + POWER_SUPPLY_ATTR(charge_qnovo_enable), + POWER_SUPPLY_ATTR(current_qnovo), + POWER_SUPPLY_ATTR(voltage_qnovo), + POWER_SUPPLY_ATTR(rerun_aicl), + POWER_SUPPLY_ATTR(cycle_count_id), + POWER_SUPPLY_ATTR(safety_timer_expired), + POWER_SUPPLY_ATTR(restricted_charging), + POWER_SUPPLY_ATTR(current_capability), + POWER_SUPPLY_ATTR(typec_mode), + POWER_SUPPLY_ATTR(typec_cc_orientation), + POWER_SUPPLY_ATTR(typec_power_role), + POWER_SUPPLY_ATTR(pd_allowed), + POWER_SUPPLY_ATTR(pd_active), + POWER_SUPPLY_ATTR(pd_in_hard_reset), + POWER_SUPPLY_ATTR(pd_current_max), + POWER_SUPPLY_ATTR(pd_usb_suspend_supported), + POWER_SUPPLY_ATTR(charger_temp), + POWER_SUPPLY_ATTR(charger_temp_max), + POWER_SUPPLY_ATTR(parallel_disable), + POWER_SUPPLY_ATTR(pe_start), + POWER_SUPPLY_ATTR(set_ship_mode), + POWER_SUPPLY_ATTR(soc_reporting_ready), + POWER_SUPPLY_ATTR(debug_battery), + POWER_SUPPLY_ATTR(fcc_delta), + POWER_SUPPLY_ATTR(icl_reduction), + POWER_SUPPLY_ATTR(parallel_mode), + POWER_SUPPLY_ATTR(die_health), + POWER_SUPPLY_ATTR(connector_health), + POWER_SUPPLY_ATTR(ctm_current_max), + POWER_SUPPLY_ATTR(hw_current_max), + POWER_SUPPLY_ATTR(real_type), + POWER_SUPPLY_ATTR(pr_swap), + POWER_SUPPLY_ATTR(cc_step), + POWER_SUPPLY_ATTR(cc_step_sel), + POWER_SUPPLY_ATTR(sw_jeita_enabled), + POWER_SUPPLY_ATTR(pd_voltage_max), + POWER_SUPPLY_ATTR(pd_voltage_min), + POWER_SUPPLY_ATTR(sdp_current_max), + /* Local extensions of type int64_t */ + POWER_SUPPLY_ATTR(charge_counter_ext), /* Properties of type `const char *' */ POWER_SUPPLY_ATTR(model_name), POWER_SUPPLY_ATTR(manufacturer), POWER_SUPPLY_ATTR(serial_number), + POWER_SUPPLY_ATTR(battery_type), }; static struct attribute * diff -ruw linux-4.4.115/drivers/power/reset/Kconfig linux-4.4.115-fbx/drivers/power/reset/Kconfig --- linux-4.4.115/drivers/power/reset/Kconfig 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/power/reset/Kconfig 2019-01-22 16:16:26.223271038 +0100 @@ -80,12 +80,6 @@ say N here or disable in dts to make sure pm_power_off never be overwrote wrongly by this driver. -config POWER_RESET_MSM - bool "Qualcomm MSM power-off driver" - depends on ARCH_QCOM - help - Power off and restart support for Qualcomm boards. - config POWER_RESET_LTC2952 bool "LTC2952 PowerPath power-off driver" depends on OF_GPIO @@ -93,6 +87,22 @@ This driver supports an external powerdown trigger and board power down via the LTC2952. Bindings are made in the device tree. +config POWER_RESET_QCOM + bool "Qualcomm MSM power-off driver" + depends on ARCH_MSM || ARCH_QCOM + depends on POWER_RESET + help + Power off and restart support for Qualcomm boards. + +config QCOM_DLOAD_MODE + bool "Qualcomm download mode" + depends on POWER_RESET_QCOM + help + This makes the SoC enter download mode when it resets + due to a kernel panic. Note that this doesn't by itself + make the kernel reboot on a kernel panic - that must be + enabled via another mechanism. + config POWER_RESET_QNAP bool "QNAP power-off driver" depends on OF_GPIO && PLAT_ORION @@ -173,5 +183,19 @@ help Reboot support for ZTE SoCs. +config REBOOT_MODE + tristate + +config SYSCON_REBOOT_MODE + tristate "Generic SYSCON regmap reboot mode driver" + depends on OF + select REBOOT_MODE + select MFD_SYSCON + help + Say y here will enable reboot mode driver. This will + get reboot mode arguments and store it in SYSCON mapped + register, then the bootloader can read it to take different + action according to the mode. + endif diff -ruw linux-4.4.115/drivers/power/reset/Makefile linux-4.4.115-fbx/drivers/power/reset/Makefile --- linux-4.4.115/drivers/power/reset/Makefile 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/power/reset/Makefile 2019-01-22 16:16:26.223271038 +0100 @@ -7,7 +7,7 @@ obj-$(CONFIG_POWER_RESET_GPIO_RESTART) += gpio-restart.o obj-$(CONFIG_POWER_RESET_HISI) += hisi-reboot.o obj-$(CONFIG_POWER_RESET_IMX) += imx-snvs-poweroff.o -obj-$(CONFIG_POWER_RESET_MSM) += msm-poweroff.o +obj-$(CONFIG_POWER_RESET_QCOM) += msm-poweroff.o obj-$(CONFIG_POWER_RESET_LTC2952) += ltc2952-poweroff.o obj-$(CONFIG_POWER_RESET_QNAP) += qnap-poweroff.o obj-$(CONFIG_POWER_RESET_RESTART) += restart-poweroff.o @@ -20,3 +20,5 @@ obj-$(CONFIG_POWER_RESET_SYSCON_POWEROFF) += syscon-poweroff.o obj-$(CONFIG_POWER_RESET_RMOBILE) += rmobile-reset.o obj-$(CONFIG_POWER_RESET_ZX) += zx-reboot.o +obj-$(CONFIG_REBOOT_MODE) += reboot-mode.o +obj-$(CONFIG_SYSCON_REBOOT_MODE) += syscon-reboot-mode.o diff -ruw linux-4.4.115/drivers/power/reset/msm-poweroff.c linux-4.4.115-fbx/drivers/power/reset/msm-poweroff.c --- linux-4.4.115/drivers/power/reset/msm-poweroff.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/power/reset/msm-poweroff.c 2019-07-17 21:24:56.793296145 +0200 @@ -1,4 +1,4 @@ -/* Copyright (c) 2013, The Linux Foundation. All rights reserved. +/* Copyright (c) 2013-2017, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -15,49 +15,686 @@ #include #include #include + #include #include #include #include #include #include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#define EMERGENCY_DLOAD_MAGIC1 0x322A4F99 +#define EMERGENCY_DLOAD_MAGIC2 0xC67E4350 +#define EMERGENCY_DLOAD_MAGIC3 0x77777777 +#define EMMC_DLOAD_TYPE 0x2 + +#define SCM_IO_DISABLE_PMIC_ARBITER 1 +#define SCM_IO_DEASSERT_PS_HOLD 2 +#define SCM_WDOG_DEBUG_BOOT_PART 0x9 +#define SCM_DLOAD_FULLDUMP 0X10 +#define SCM_EDLOAD_MODE 0X01 +#define SCM_DLOAD_CMD 0x10 +#define SCM_DLOAD_MINIDUMP 0X20 +#define SCM_DLOAD_BOTHDUMPS (SCM_DLOAD_MINIDUMP | SCM_DLOAD_FULLDUMP) + +static int restart_mode; +static void *restart_reason; +static bool scm_pmic_arbiter_disable_supported; +static bool scm_deassert_ps_hold_supported; +/* Download mode master kill-switch */ static void __iomem *msm_ps_hold; -static int do_msm_restart(struct notifier_block *nb, unsigned long action, - void *data) +static phys_addr_t tcsr_boot_misc_detect; +static void scm_disable_sdi(void); + +/* Runtime could be only changed value once. + * There is no API from TZ to re-enable the registers. + * So the SDI cannot be re-enabled when it already by-passed. +*/ + +#ifdef CONFIG_QCOM_DLOAD_MODE +#define EDL_MODE_PROP "qcom,msm-imem-emergency_download_mode" +#define DL_MODE_PROP "qcom,msm-imem-download_mode" +#ifdef CONFIG_RANDOMIZE_BASE +#define KASLR_OFFSET_PROP "qcom,msm-imem-kaslr_offset" +#endif + +static int dload_type = SCM_DLOAD_FULLDUMP; +static int download_mode = 1; +static struct kobject dload_kobj; +static void *dload_mode_addr, *dload_type_addr; +static bool dload_mode_enabled; +static void *emergency_dload_mode_addr; +#ifdef CONFIG_RANDOMIZE_BASE +static void *kaslr_imem_addr; +#endif +static bool scm_dload_supported; + +static int dload_set(const char *val, struct kernel_param *kp); +/* interface for exporting attributes */ +struct reset_attribute { + struct attribute attr; + ssize_t (*show)(struct kobject *kobj, struct attribute *attr, + char *buf); + size_t (*store)(struct kobject *kobj, struct attribute *attr, + const char *buf, size_t count); +}; +#define to_reset_attr(_attr) \ + container_of(_attr, struct reset_attribute, attr) +#define RESET_ATTR(_name, _mode, _show, _store) \ + static struct reset_attribute reset_attr_##_name = \ + __ATTR(_name, _mode, _show, _store) + +module_param_call(download_mode, dload_set, param_get_int, + &download_mode, 0644); + + +int scm_set_dload_mode(int arg1, int arg2) { - writel(0, msm_ps_hold); - mdelay(10000); + struct scm_desc desc = { + .args[0] = arg1, + .args[1] = arg2, + .arginfo = SCM_ARGS(2), + }; + + if (!scm_dload_supported) { + if (tcsr_boot_misc_detect) + return scm_io_write(tcsr_boot_misc_detect, arg1); + + return 0; + } + + if (!is_scm_armv8()) + return scm_call_atomic2(SCM_SVC_BOOT, SCM_DLOAD_CMD, arg1, + arg2); + + return scm_call2_atomic(SCM_SIP_FNID(SCM_SVC_BOOT, SCM_DLOAD_CMD), + &desc); +} + +static void set_dload_mode(int on) +{ + int ret; + + if (dload_mode_addr) { + __raw_writel(on ? 0xE47B337D : 0, dload_mode_addr); + __raw_writel(on ? 0xCE14091A : 0, + dload_mode_addr + sizeof(unsigned int)); + mb(); + } + + ret = scm_set_dload_mode(on ? dload_type : 0, 0); + if (ret) + pr_err("Failed to set secure DLOAD mode: %d\n", ret); + + dload_mode_enabled = on; +} + +static bool get_dload_mode(void) +{ + return dload_mode_enabled; +} + +static void enable_emergency_dload_mode(void) +{ + int ret; + + if (emergency_dload_mode_addr) { + __raw_writel(EMERGENCY_DLOAD_MAGIC1, + emergency_dload_mode_addr); + __raw_writel(EMERGENCY_DLOAD_MAGIC2, + emergency_dload_mode_addr + + sizeof(unsigned int)); + __raw_writel(EMERGENCY_DLOAD_MAGIC3, + emergency_dload_mode_addr + + (2 * sizeof(unsigned int))); + + /* Need disable the pmic wdt, then the emergency dload mode + * will not auto reset. */ + qpnp_pon_wd_config(0); + mb(); + } + + ret = scm_set_dload_mode(SCM_EDLOAD_MODE, 0); + if (ret) + pr_err("Failed to set secure EDLOAD mode: %d\n", ret); +} + +static int dload_set(const char *val, struct kernel_param *kp) +{ + int ret; + int old_val = download_mode; + + ret = param_set_int(val, kp); + if (ret) + return ret; + + /* If download_mode is not zero or one, ignore. */ + if (download_mode >> 1) { + download_mode = old_val; + return -EINVAL; + } + + set_dload_mode(download_mode); + + return 0; +} +#else +static void set_dload_mode(int on) +{ + return; +} + +static void enable_emergency_dload_mode(void) +{ + pr_err("dload mode is not enabled on target\n"); +} +static bool get_dload_mode(void) +{ + return false; +} +#endif + +static int in_panic; + +static int panic_prep_restart(struct notifier_block *this, + unsigned long event, void *ptr) +{ + in_panic = 1; return NOTIFY_DONE; } -static struct notifier_block restart_nb = { - .notifier_call = do_msm_restart, - .priority = 128, +static struct notifier_block panic_blk = { + .notifier_call = panic_prep_restart, +}; + +static void scm_disable_sdi(void) +{ + int ret; + struct scm_desc desc = { + .args[0] = 1, + .args[1] = 0, + .arginfo = SCM_ARGS(2), + }; + + /* Needed to bypass debug image on some chips */ + if (!is_scm_armv8()) + ret = scm_call_atomic2(SCM_SVC_BOOT, + SCM_WDOG_DEBUG_BOOT_PART, 1, 0); + else + ret = scm_call2_atomic(SCM_SIP_FNID(SCM_SVC_BOOT, + SCM_WDOG_DEBUG_BOOT_PART), &desc); + if (ret) + pr_err("Failed to disable secure wdog debug: %d\n", ret); +} + +void msm_set_restart_mode(int mode) +{ + restart_mode = mode; +} +EXPORT_SYMBOL(msm_set_restart_mode); + +/* + * Force the SPMI PMIC arbiter to shutdown so that no more SPMI transactions + * are sent from the MSM to the PMIC. This is required in order to avoid an + * SPMI lockup on certain PMIC chips if PS_HOLD is lowered in the middle of + * an SPMI transaction. + */ +static void halt_spmi_pmic_arbiter(void) +{ + struct scm_desc desc = { + .args[0] = 0, + .arginfo = SCM_ARGS(1), + }; + + if (scm_pmic_arbiter_disable_supported) { + pr_crit("Calling SCM to disable SPMI PMIC arbiter\n"); + if (!is_scm_armv8()) + scm_call_atomic1(SCM_SVC_PWR, + SCM_IO_DISABLE_PMIC_ARBITER, 0); + else + scm_call2_atomic(SCM_SIP_FNID(SCM_SVC_PWR, + SCM_IO_DISABLE_PMIC_ARBITER), &desc); + } +} + +static void msm_restart_prepare(const char *cmd) +{ + bool need_warm_reset = false; + +#ifdef CONFIG_QCOM_DLOAD_MODE + + /* Write download mode flags if we're panic'ing + * Write download mode flags if restart_mode says so + * Kill download mode if master-kill switch is set + */ + + set_dload_mode(download_mode && + (in_panic || restart_mode == RESTART_DLOAD)); +#endif + + if (qpnp_pon_check_hard_reset_stored()) { + /* Set warm reset as true when device is in dload mode */ + if (get_dload_mode() || + ((cmd != NULL && cmd[0] != '\0') && + !strcmp(cmd, "edl"))) + need_warm_reset = true; + } else { + need_warm_reset = (get_dload_mode() || + (cmd != NULL && cmd[0] != '\0')); + } + +#ifdef CONFIG_PSTORE + if (in_panic) { + pr_warn("disable SDI due to in_panic && CONFIG_PSTORE\n"); + mdelay(200); + need_warm_reset = true; + scm_disable_sdi(); + } +#endif + + /* Hard reset the PMIC unless memory contents must be maintained. */ + if (need_warm_reset) { + qpnp_pon_system_pwr_off(PON_POWER_OFF_WARM_RESET); + } else { + qpnp_pon_system_pwr_off(PON_POWER_OFF_HARD_RESET); + } + + if (cmd != NULL) { + if (!strncmp(cmd, "bootloader", 10)) { + qpnp_pon_set_restart_reason( + PON_RESTART_REASON_BOOTLOADER); + __raw_writel(0x77665500, restart_reason); + } else if (!strncmp(cmd, "recovery", 8)) { + qpnp_pon_set_restart_reason( + PON_RESTART_REASON_RECOVERY); + __raw_writel(0x77665502, restart_reason); + } else if (!strcmp(cmd, "rtc")) { + qpnp_pon_set_restart_reason( + PON_RESTART_REASON_RTC); + __raw_writel(0x77665503, restart_reason); + } else if (!strcmp(cmd, "dm-verity device corrupted")) { + qpnp_pon_set_restart_reason( + PON_RESTART_REASON_DMVERITY_CORRUPTED); + __raw_writel(0x77665508, restart_reason); + } else if (!strcmp(cmd, "dm-verity enforcing")) { + qpnp_pon_set_restart_reason( + PON_RESTART_REASON_DMVERITY_ENFORCE); + __raw_writel(0x77665509, restart_reason); + } else if (!strcmp(cmd, "keys clear")) { + qpnp_pon_set_restart_reason( + PON_RESTART_REASON_KEYS_CLEAR); + __raw_writel(0x7766550a, restart_reason); + } else if (!strncmp(cmd, "oem-", 4)) { + unsigned long code; + unsigned long reset_reason; + int ret; + ret = kstrtoul(cmd + 4, 16, &code); + if (!ret) { + /* Bit-2 to bit-7 of SOFT_RB_SPARE for hard + * reset reason: + * Value 0 to 31 for common defined features + * Value 32 to 63 for oem specific features + */ + reset_reason = code + + PON_RESTART_REASON_OEM_MIN; + if (reset_reason > PON_RESTART_REASON_OEM_MAX || + reset_reason < PON_RESTART_REASON_OEM_MIN) { + pr_err("Invalid oem reset reason: %lx\n", + reset_reason); + } else { + qpnp_pon_set_restart_reason( + reset_reason); + } + __raw_writel(0x6f656d00 | (code & 0xff), + restart_reason); + } + } else if (!strncmp(cmd, "edl", 3)) { + enable_emergency_dload_mode(); + } else { + __raw_writel(0x77665501, restart_reason); + } + } + + flush_cache_all(); + + /*outer_flush_all is not supported by 64bit kernel*/ +#ifndef CONFIG_ARM64 + outer_flush_all(); +#endif + +} + +/* + * Deassert PS_HOLD to signal the PMIC that we are ready to power down or reset. + * Do this by calling into the secure environment, if available, or by directly + * writing to a hardware register. + * + * This function should never return. + */ +static void deassert_ps_hold(void) +{ + struct scm_desc desc = { + .args[0] = 0, + .arginfo = SCM_ARGS(1), }; + if (scm_deassert_ps_hold_supported) { + /* This call will be available on ARMv8 only */ + scm_call2_atomic(SCM_SIP_FNID(SCM_SVC_PWR, + SCM_IO_DEASSERT_PS_HOLD), &desc); + } + + /* Fall-through to the direct write in case the scm_call "returns" */ + __raw_writel(0, msm_ps_hold); +} + +static void do_msm_restart(enum reboot_mode reboot_mode, const char *cmd) +{ + pr_notice("Going down for restart now\n"); + + msm_restart_prepare(cmd); + +#ifdef CONFIG_QCOM_DLOAD_MODE + /* + * Trigger a watchdog bite here and if this fails, + * device will take the usual restart path. + */ + + if (WDOG_BITE_ON_PANIC && in_panic) + msm_trigger_wdog_bite(); +#endif + + scm_disable_sdi(); + halt_spmi_pmic_arbiter(); + deassert_ps_hold(); + + mdelay(10000); +} + static void do_msm_poweroff(void) { - /* TODO: Add poweroff capability */ - do_msm_restart(&restart_nb, 0, NULL); + pr_notice("Powering off the SoC\n"); + + set_dload_mode(0); + scm_disable_sdi(); + qpnp_pon_system_pwr_off(PON_POWER_OFF_SHUTDOWN); + + halt_spmi_pmic_arbiter(); + deassert_ps_hold(); + + mdelay(10000); + pr_err("Powering off has failed\n"); + return; +} + +#ifdef CONFIG_QCOM_DLOAD_MODE +static ssize_t attr_show(struct kobject *kobj, struct attribute *attr, + char *buf) +{ + struct reset_attribute *reset_attr = to_reset_attr(attr); + ssize_t ret = -EIO; + + if (reset_attr->show) + ret = reset_attr->show(kobj, attr, buf); + + return ret; +} + +static ssize_t attr_store(struct kobject *kobj, struct attribute *attr, + const char *buf, size_t count) +{ + struct reset_attribute *reset_attr = to_reset_attr(attr); + ssize_t ret = -EIO; + + if (reset_attr->store) + ret = reset_attr->store(kobj, attr, buf, count); + + return ret; +} + +static const struct sysfs_ops reset_sysfs_ops = { + .show = attr_show, + .store = attr_store, +}; + +static struct kobj_type reset_ktype = { + .sysfs_ops = &reset_sysfs_ops, +}; + +static ssize_t show_emmc_dload(struct kobject *kobj, struct attribute *attr, + char *buf) +{ + uint32_t read_val, show_val; + + read_val = __raw_readl(dload_type_addr); + if (read_val == EMMC_DLOAD_TYPE) + show_val = 1; + else + show_val = 0; + + return scnprintf(buf, sizeof(show_val), "%u\n", show_val); +} + +static size_t store_emmc_dload(struct kobject *kobj, struct attribute *attr, + const char *buf, size_t count) +{ + uint32_t enabled; + int ret; + + ret = kstrtouint(buf, 0, &enabled); + if (ret < 0) + return ret; + + if (!((enabled == 0) || (enabled == 1))) + return -EINVAL; + + if (enabled == 1) + __raw_writel(EMMC_DLOAD_TYPE, dload_type_addr); + else + __raw_writel(0, dload_type_addr); + + return count; +} + +#ifdef CONFIG_QCOM_MINIDUMP + +static DEFINE_MUTEX(tcsr_lock); + +static ssize_t show_dload_mode(struct kobject *kobj, struct attribute *attr, + char *buf) +{ + return scnprintf(buf, PAGE_SIZE, "DLOAD dump type: %s\n", + (dload_type == SCM_DLOAD_BOTHDUMPS) ? "both" : + ((dload_type == SCM_DLOAD_MINIDUMP) ? "mini" : "full")); +} + +static size_t store_dload_mode(struct kobject *kobj, struct attribute *attr, + const char *buf, size_t count) +{ + if (sysfs_streq(buf, "full")) { + dload_type = SCM_DLOAD_FULLDUMP; + } else if (sysfs_streq(buf, "mini")) { + if (!minidump_enabled) { + pr_err("Minidump is not enabled\n"); + return -ENODEV; + } + dload_type = SCM_DLOAD_MINIDUMP; + } else if (sysfs_streq(buf, "both")) { + if (!minidump_enabled) { + pr_err("Minidump not enabled, setting fulldump only\n"); + dload_type = SCM_DLOAD_FULLDUMP; + return count; + } + dload_type = SCM_DLOAD_BOTHDUMPS; + } else{ + pr_err("Invalid Dump setup request..\n"); + pr_err("Supported dumps:'full', 'mini', or 'both'\n"); + return -EINVAL; + } + + mutex_lock(&tcsr_lock); + /*Overwrite TCSR reg*/ + set_dload_mode(dload_type); + mutex_unlock(&tcsr_lock); + return count; } +RESET_ATTR(dload_mode, 0644, show_dload_mode, store_dload_mode); +#endif + +RESET_ATTR(emmc_dload, 0644, show_emmc_dload, store_emmc_dload); + +static struct attribute *reset_attrs[] = { + &reset_attr_emmc_dload.attr, +#ifdef CONFIG_QCOM_MINIDUMP + &reset_attr_dload_mode.attr, +#endif + NULL +}; + +static struct attribute_group reset_attr_group = { + .attrs = reset_attrs, +}; +#endif static int msm_restart_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; struct resource *mem; + struct device_node *np; + int ret = 0; - mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); + atomic_notifier_chain_register(&panic_notifier_list, &panic_blk); + +#ifdef CONFIG_QCOM_DLOAD_MODE + if (scm_is_call_available(SCM_SVC_BOOT, SCM_DLOAD_CMD) > 0) + scm_dload_supported = true; + + np = of_find_compatible_node(NULL, NULL, DL_MODE_PROP); + if (!np) { + pr_err("unable to find DT imem DLOAD mode node\n"); + } else { + dload_mode_addr = of_iomap(np, 0); + if (!dload_mode_addr) + pr_err("unable to map imem DLOAD offset\n"); + } + + np = of_find_compatible_node(NULL, NULL, EDL_MODE_PROP); + if (!np) { + pr_err("unable to find DT imem EDLOAD mode node\n"); + } else { + emergency_dload_mode_addr = of_iomap(np, 0); + if (!emergency_dload_mode_addr) + pr_err("unable to map imem EDLOAD mode offset\n"); + } + +#ifdef CONFIG_RANDOMIZE_BASE +#define KASLR_OFFSET_BIT_MASK 0x00000000FFFFFFFF + np = of_find_compatible_node(NULL, NULL, KASLR_OFFSET_PROP); + if (!np) { + pr_err("unable to find DT imem KASLR_OFFSET node\n"); + } else { + kaslr_imem_addr = of_iomap(np, 0); + if (!kaslr_imem_addr) + pr_err("unable to map imem KASLR offset\n"); + } + + if (kaslr_imem_addr) { + __raw_writel(0xdead4ead, kaslr_imem_addr); + __raw_writel(KASLR_OFFSET_BIT_MASK & + (kimage_vaddr - KIMAGE_VADDR), kaslr_imem_addr + 4); + __raw_writel(KASLR_OFFSET_BIT_MASK & + ((kimage_vaddr - KIMAGE_VADDR) >> 32), + kaslr_imem_addr + 8); + iounmap(kaslr_imem_addr); + } +#endif + + np = of_find_compatible_node(NULL, NULL, + "qcom,msm-imem-dload-type"); + if (!np) { + pr_err("unable to find DT imem dload-type node\n"); + goto skip_sysfs_create; + } else { + dload_type_addr = of_iomap(np, 0); + if (!dload_type_addr) { + pr_err("unable to map imem dload-type offset\n"); + goto skip_sysfs_create; + } + } + + ret = kobject_init_and_add(&dload_kobj, &reset_ktype, + kernel_kobj, "%s", "dload"); + if (ret) { + pr_err("%s:Error in creation kobject_add\n", __func__); + kobject_put(&dload_kobj); + goto skip_sysfs_create; + } + + ret = sysfs_create_group(&dload_kobj, &reset_attr_group); + if (ret) { + pr_err("%s:Error in creation sysfs_create_group\n", __func__); + kobject_del(&dload_kobj); + } +skip_sysfs_create: +#endif + np = of_find_compatible_node(NULL, NULL, + "qcom,msm-imem-restart_reason"); + if (!np) { + pr_err("unable to find DT imem restart reason node\n"); + } else { + restart_reason = of_iomap(np, 0); + if (!restart_reason) { + pr_err("unable to map imem restart reason offset\n"); + ret = -ENOMEM; + goto err_restart_reason; + } + } + + mem = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pshold-base"); msm_ps_hold = devm_ioremap_resource(dev, mem); if (IS_ERR(msm_ps_hold)) return PTR_ERR(msm_ps_hold); - register_restart_handler(&restart_nb); + mem = platform_get_resource_byname(pdev, IORESOURCE_MEM, + "tcsr-boot-misc-detect"); + if (mem) + tcsr_boot_misc_detect = mem->start; pm_power_off = do_msm_poweroff; + arm_pm_restart = do_msm_restart; + + if (scm_is_call_available(SCM_SVC_PWR, SCM_IO_DISABLE_PMIC_ARBITER) > 0) + scm_pmic_arbiter_disable_supported = true; + if (scm_is_call_available(SCM_SVC_PWR, SCM_IO_DEASSERT_PS_HOLD) > 0) + scm_deassert_ps_hold_supported = true; + +#ifdef CONFIG_QCOM_DLOAD_MODE + set_dload_mode(download_mode); + if (!download_mode) + scm_disable_sdi(); +#endif return 0; + +err_restart_reason: +#ifdef CONFIG_QCOM_DLOAD_MODE + iounmap(emergency_dload_mode_addr); + iounmap(dload_mode_addr); +#endif + return ret; } static const struct of_device_id of_msm_restart_match[] = { @@ -78,4 +715,4 @@ { return platform_driver_register(&msm_restart_driver); } -device_initcall(msm_restart_init); +pure_initcall(msm_restart_init); diff -ruw linux-4.4.115/drivers/pwm/Kconfig linux-4.4.115-fbx/drivers/pwm/Kconfig --- linux-4.4.115/drivers/pwm/Kconfig 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/pwm/Kconfig 2019-01-22 16:16:26.243271219 +0100 @@ -309,6 +309,16 @@ To compile this driver as a module, choose M here: the module will be called pwm-rcar. +config PWM_QPNP + tristate "Qualcomm Technologies, Inc. QPNP LPG/PWM support" + depends on SPMI + help + This driver supports PWM/LPG devices in Qualcomm Technologies, Inc. + PMIC chips which comply with QPNP. QPNP is an SPMI based PMIC + implementation. These devices support Pulse Width Modulation output + with user generated patterns. They share a lookup table with size of + 64 entries. + config PWM_RENESAS_TPU tristate "Renesas TPU PWM support" depends on ARCH_SHMOBILE || COMPILE_TEST diff -ruw linux-4.4.115/drivers/pwm/Makefile linux-4.4.115-fbx/drivers/pwm/Makefile --- linux-4.4.115/drivers/pwm/Makefile 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/pwm/Makefile 2019-01-22 16:16:26.243271219 +0100 @@ -28,6 +28,7 @@ obj-$(CONFIG_PWM_PUV3) += pwm-puv3.o obj-$(CONFIG_PWM_PXA) += pwm-pxa.o obj-$(CONFIG_PWM_RCAR) += pwm-rcar.o +obj-$(CONFIG_PWM_QPNP) += pwm-qpnp.o obj-$(CONFIG_PWM_RENESAS_TPU) += pwm-renesas-tpu.o obj-$(CONFIG_PWM_ROCKCHIP) += pwm-rockchip.o obj-$(CONFIG_PWM_SAMSUNG) += pwm-samsung.o @@ -41,3 +42,4 @@ obj-$(CONFIG_PWM_TWL) += pwm-twl.o obj-$(CONFIG_PWM_TWL_LED) += pwm-twl-led.o obj-$(CONFIG_PWM_VT8500) += pwm-vt8500.o + diff -ruw linux-4.4.115/drivers/regulator/core.c linux-4.4.115-fbx/drivers/regulator/core.c --- linux-4.4.115/drivers/regulator/core.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/regulator/core.c 2019-01-22 16:16:26.259271364 +0100 @@ -27,6 +27,8 @@ #include #include #include +#include +#include #include #include #include @@ -224,6 +226,15 @@ return -EPERM; } + /* check if requested voltage range actually overlaps the constraints */ + if (*max_uV < rdev->constraints->min_uV || + *min_uV > rdev->constraints->max_uV) { + rdev_err(rdev, "requested voltage range [%d, %d] does not fit " + "within constraints: [%d, %d]\n", *min_uV, *max_uV, + rdev->constraints->min_uV, rdev->constraints->max_uV); + return -EINVAL; + } + if (*max_uV > rdev->constraints->max_uV) *max_uV = rdev->constraints->max_uV; if (*min_uV < rdev->constraints->min_uV) @@ -245,6 +256,8 @@ int *min_uV, int *max_uV) { struct regulator *regulator; + int init_min_uV = *min_uV; + int init_max_uV = *max_uV; list_for_each_entry(regulator, &rdev->consumer_list, list) { /* @@ -254,6 +267,13 @@ if (!regulator->min_uV && !regulator->max_uV) continue; + if (init_max_uV < regulator->min_uV + || init_min_uV > regulator->max_uV) + rdev_err(rdev, "requested voltage range [%d, %d] does " + "not fit within previously voted range: " + "[%d, %d]\n", init_min_uV, init_max_uV, + regulator->min_uV, regulator->max_uV); + if (*max_uV > regulator->max_uV) *max_uV = regulator->max_uV; if (*min_uV < regulator->min_uV) @@ -337,7 +357,7 @@ static int regulator_check_drms(struct regulator_dev *rdev) { if (!rdev->constraints) { - rdev_err(rdev, "no constraints\n"); + rdev_dbg(rdev, "no constraints\n"); return -ENODEV; } if (!(rdev->constraints->valid_ops_mask & REGULATOR_CHANGE_DRMS)) { @@ -684,7 +704,7 @@ { struct regulator *sibling; int current_uA = 0, output_uV, input_uV, err; - unsigned int mode; + unsigned int regulator_curr_mode, mode; lockdep_assert_held_once(&rdev->mutex); @@ -745,6 +765,14 @@ current_uA, input_uV, output_uV); return err; } + /* return if the same mode is requested */ + if (rdev->desc->ops->get_mode) { + regulator_curr_mode = rdev->desc->ops->get_mode(rdev); + if (regulator_curr_mode == mode) + return 0; + } else { + return 0; + } err = rdev->desc->ops->set_mode(rdev, mode); if (err < 0) @@ -1514,16 +1542,6 @@ return ret; } - /* Cascade always-on state to supply */ - if (_regulator_is_enabled(rdev) && rdev->supply) { - ret = regulator_enable(rdev->supply); - if (ret < 0) { - _regulator_put(rdev->supply); - rdev->supply = NULL; - return ret; - } - } - return 0; } @@ -2110,6 +2128,8 @@ if (ret < 0) return ret; + _notifier_call_chain(rdev, REGULATOR_EVENT_ENABLE, + NULL); } else if (ret < 0) { rdev_err(rdev, "is_enabled() failed: %d\n", ret); return ret; @@ -2148,7 +2168,11 @@ } mutex_lock(&rdev->mutex); + ret = _regulator_enable(rdev); + if (ret == 0) + regulator->enabled++; + mutex_unlock(&rdev->mutex); if (ret != 0 && rdev->supply) @@ -2260,6 +2284,8 @@ mutex_lock(&rdev->mutex); ret = _regulator_disable(rdev); + if (ret == 0) + regulator->enabled--; mutex_unlock(&rdev->mutex); if (ret == 0 && rdev->supply) @@ -2335,6 +2361,14 @@ count = rdev->deferred_disables; rdev->deferred_disables = 0; + /* + * Workqueue functions queue the new work instance while the previous + * work instance is being processed. Cancel the queued work instance + * as the work instance under processing does the job of the queued + * work instance. + */ + cancel_delayed_work(&rdev->disable_work); + for (i = 0; i < count; i++) { ret = _regulator_disable(rdev); if (ret != 0) @@ -2369,7 +2403,6 @@ int regulator_disable_deferred(struct regulator *regulator, int ms) { struct regulator_dev *rdev = regulator->rdev; - int ret; if (regulator->always_on) return 0; @@ -2379,14 +2412,10 @@ mutex_lock(&rdev->mutex); rdev->deferred_disables++; + mod_delayed_work(system_power_efficient_wq, &rdev->disable_work, + msecs_to_jiffies(ms)); mutex_unlock(&rdev->mutex); - ret = queue_delayed_work(system_power_efficient_wq, - &rdev->disable_work, - msecs_to_jiffies(ms)); - if (ret < 0) - return ret; - else return 0; } EXPORT_SYMBOL_GPL(regulator_disable_deferred); @@ -2603,6 +2632,40 @@ EXPORT_SYMBOL_GPL(regulator_list_hardware_vsel); /** + * regulator_list_corner_voltage - return the maximum voltage in microvolts that + * can be physically configured for the regulator when operating at the + * specified voltage corner + * @regulator: regulator source + * @corner: voltage corner value + * Context: can sleep + * + * This function can be used for regulators which allow scaling between + * different voltage corners as opposed to be different absolute voltages. The + * absolute voltage for a given corner may vary part-to-part or for a given part + * at runtime based upon various factors. + * + * Returns a voltage corresponding to the specified voltage corner or a negative + * errno if the corner value can't be used on this system. + */ +int regulator_list_corner_voltage(struct regulator *regulator, int corner) +{ + struct regulator_dev *rdev = regulator->rdev; + int ret; + + if (corner < rdev->constraints->min_uV || + corner > rdev->constraints->max_uV || + !rdev->desc->ops->list_corner_voltage) + return -EINVAL; + + mutex_lock(&rdev->mutex); + ret = rdev->desc->ops->list_corner_voltage(rdev, corner); + mutex_unlock(&rdev->mutex); + + return ret; +} +EXPORT_SYMBOL(regulator_list_corner_voltage); + +/** * regulator_get_linear_step - return the voltage step size between VSEL values * @regulator: regulator source * @@ -2871,7 +2934,8 @@ goto out2; if (rdev->supply && (rdev->desc->min_dropout_uV || - !rdev->desc->ops->get_voltage)) { + !(rdev->desc->ops->get_voltage || + rdev->desc->ops->get_voltage_sel))) { int current_supply_uV; int selector; @@ -3363,7 +3427,8 @@ if (enable && !regulator->bypass) { rdev->bypass_count++; - if (rdev->bypass_count == rdev->open_count) { + if (rdev->bypass_count == rdev->open_count - + rdev->open_offset) { ret = rdev->desc->ops->set_bypass(rdev, enable); if (ret != 0) rdev->bypass_count--; @@ -3372,7 +3437,8 @@ } else if (!enable && regulator->bypass) { rdev->bypass_count--; - if (rdev->bypass_count != rdev->open_count) { + if (rdev->bypass_count != rdev->open_count - + rdev->open_offset) { ret = rdev->desc->ops->set_bypass(rdev, enable); if (ret != 0) rdev->bypass_count++; @@ -3533,6 +3599,42 @@ EXPORT_SYMBOL_GPL(regulator_bulk_enable); /** + * regulator_bulk_set_voltage - set voltage for multiple regulator consumers + * + * @num_consumers: Number of consumers + * @consumers: Consumer data; clients are stored here. + * @return 0 on success, an errno on failure + * + * This convenience API allows the voted voltage ranges of multiple regulator + * clients to be set in a single API call. If any consumers cannot have their + * voltages set, this function returns WITHOUT withdrawing votes for any + * consumers that have already been set. + */ +int regulator_bulk_set_voltage(int num_consumers, + struct regulator_bulk_data *consumers) +{ + int i; + int rc; + + for (i = 0; i < num_consumers; i++) { + if (!consumers[i].min_uV && !consumers[i].max_uV) + continue; + rc = regulator_set_voltage(consumers[i].consumer, + consumers[i].min_uV, + consumers[i].max_uV); + if (rc) + goto err; + } + + return 0; + +err: + pr_err("Failed to set voltage for %s: %d\n", consumers[i].supply, rc); + return rc; +} +EXPORT_SYMBOL_GPL(regulator_bulk_set_voltage); + +/** * regulator_bulk_disable - disable multiple regulator consumers * * @num_consumers: Number of consumers @@ -3800,11 +3902,269 @@ .dev_groups = regulator_dev_groups, }; +#ifdef CONFIG_DEBUG_FS + +static int reg_debug_enable_set(void *data, u64 val) +{ + struct regulator *regulator = data; + int ret; + + if (val) { + ret = regulator_enable(regulator); + if (ret) + rdev_err(regulator->rdev, "enable failed, ret=%d\n", + ret); + } else { + ret = regulator_disable(regulator); + if (ret) + rdev_err(regulator->rdev, "disable failed, ret=%d\n", + ret); + } + + return ret; +} + +static int reg_debug_enable_get(void *data, u64 *val) +{ + struct regulator *regulator = data; + + *val = regulator_is_enabled(regulator); + + return 0; +} +DEFINE_SIMPLE_ATTRIBUTE(reg_enable_fops, reg_debug_enable_get, + reg_debug_enable_set, "%llu\n"); + +static int reg_debug_bypass_enable_get(void *data, u64 *val) +{ + struct regulator *regulator = data; + struct regulator_dev *rdev = regulator->rdev; + bool enable = false; + int ret = 0; + + mutex_lock(&rdev->mutex); + if (rdev->desc->ops->get_bypass) { + ret = rdev->desc->ops->get_bypass(rdev, &enable); + if (ret) + rdev_err(rdev, "get_bypass() failed, ret=%d\n", ret); + } else { + enable = (rdev->bypass_count == rdev->open_count + - rdev->open_offset); + } + mutex_unlock(&rdev->mutex); + + *val = enable; + + return ret; +} + +static int reg_debug_bypass_enable_set(void *data, u64 val) +{ + struct regulator *regulator = data; + struct regulator_dev *rdev = regulator->rdev; + int ret = 0; + + mutex_lock(&rdev->mutex); + rdev->open_offset = 0; + mutex_unlock(&rdev->mutex); + + ret = regulator_allow_bypass(data, val); + + return ret; +} +DEFINE_SIMPLE_ATTRIBUTE(reg_bypass_enable_fops, reg_debug_bypass_enable_get, + reg_debug_bypass_enable_set, "%llu\n"); + +static int reg_debug_force_disable_set(void *data, u64 val) +{ + struct regulator *regulator = data; + int ret = 0; + + if (val > 0) { + ret = regulator_force_disable(regulator); + if (ret) + rdev_err(regulator->rdev, "force_disable failed, ret=%d\n", + ret); + } + + return ret; +} +DEFINE_SIMPLE_ATTRIBUTE(reg_force_disable_fops, reg_debug_enable_get, + reg_debug_force_disable_set, "%llu\n"); + +#define MAX_DEBUG_BUF_LEN 50 + +static ssize_t reg_debug_voltage_write(struct file *file, + const char __user *ubuf, size_t count, loff_t *ppos) +{ + struct regulator *regulator = file->private_data; + char buf[MAX_DEBUG_BUF_LEN]; + int ret, filled; + int min_uV, max_uV = -1; + + if (count < MAX_DEBUG_BUF_LEN) { + if (copy_from_user(buf, ubuf, count)) + return -EFAULT; + + buf[count] = '\0'; + filled = sscanf(buf, "%d %d", &min_uV, &max_uV); + + /* Check that both min and max voltage were specified. */ + if (filled < 2 || min_uV < 0 || max_uV < min_uV) { + rdev_err(regulator->rdev, "incorrect values specified: \"%s\"; should be: \"min_uV max_uV\"\n", + buf); + return -EINVAL; + } + + ret = regulator_set_voltage(regulator, min_uV, max_uV); + if (ret) { + rdev_err(regulator->rdev, "set voltage(%d, %d) failed, ret=%d\n", + min_uV, max_uV, ret); + return ret; + } + } else { + rdev_err(regulator->rdev, "voltage request string exceeds maximum buffer size\n"); + return -EINVAL; + } + + return count; +} + +static ssize_t reg_debug_voltage_read(struct file *file, char __user *ubuf, + size_t count, loff_t *ppos) +{ + struct regulator *regulator = file->private_data; + char buf[MAX_DEBUG_BUF_LEN]; + int voltage, ret; + + voltage = regulator_get_voltage(regulator); + + ret = snprintf(buf, MAX_DEBUG_BUF_LEN - 1, "%d\n", voltage); + + return simple_read_from_buffer(ubuf, count, ppos, buf, ret); +} + +static int reg_debug_voltage_open(struct inode *inode, struct file *file) +{ + file->private_data = inode->i_private; + + return 0; +} + +static const struct file_operations reg_voltage_fops = { + .write = reg_debug_voltage_write, + .open = reg_debug_voltage_open, + .read = reg_debug_voltage_read, +}; + +static int reg_debug_mode_set(void *data, u64 val) +{ + struct regulator *regulator = data; + unsigned int mode = val; + int ret; + + ret = regulator_set_mode(regulator, mode); + if (ret) + rdev_err(regulator->rdev, "set mode=%u failed, ret=%d\n", + mode, ret); + + return ret; +} + +static int reg_debug_mode_get(void *data, u64 *val) +{ + struct regulator *regulator = data; + int mode; + + mode = regulator_get_mode(regulator); + if (mode < 0) { + rdev_err(regulator->rdev, "get mode failed, ret=%d\n", mode); + return mode; + } + + *val = mode; + + return 0; +} +DEFINE_SIMPLE_ATTRIBUTE(reg_mode_fops, reg_debug_mode_get, reg_debug_mode_set, + "%llu\n"); + +static int reg_debug_set_load(void *data, u64 val) +{ + struct regulator *regulator = data; + int load = val; + int ret; + + ret = regulator_set_load(regulator, load); + if (ret) + rdev_err(regulator->rdev, "set load=%d failed, ret=%d\n", + load, ret); + + return ret; +} +DEFINE_SIMPLE_ATTRIBUTE(reg_set_load_fops, reg_debug_mode_get, + reg_debug_set_load, "%llu\n"); + +static int reg_debug_consumers_show(struct seq_file *m, void *v) +{ + struct regulator_dev *rdev = m->private; + struct regulator *reg; + char *supply_name; + + mutex_lock(&rdev->mutex); + + /* Print a header if there are consumers. */ + if (rdev->open_count) + seq_printf(m, "%-32s EN Min_uV Max_uV load_uA\n", + "Device-Supply"); + + list_for_each_entry(reg, &rdev->consumer_list, list) { + if (reg->supply_name) + supply_name = reg->supply_name; + else + supply_name = "(null)-(null)"; + + seq_printf(m, "%-32s %c %8d %8d %8d\n", supply_name, + (reg->enabled ? 'Y' : 'N'), reg->min_uV, reg->max_uV, + reg->uA_load); + } + + mutex_unlock(&rdev->mutex); + + return 0; +} + +static int reg_debug_consumers_open(struct inode *inode, struct file *file) +{ + return single_open(file, reg_debug_consumers_show, inode->i_private); +} + +static const struct file_operations reg_consumers_fops = { + .owner = THIS_MODULE, + .open = reg_debug_consumers_open, + .read = seq_read, + .llseek = seq_lseek, + .release = single_release, +}; + +static void rdev_deinit_debugfs(struct regulator_dev *rdev) +{ + if (!IS_ERR_OR_NULL(rdev)) { + debugfs_remove_recursive(rdev->debugfs); + if (rdev->debug_consumer) + rdev->debug_consumer->debugfs = NULL; + regulator_put(rdev->debug_consumer); + } +} + static void rdev_init_debugfs(struct regulator_dev *rdev) { struct device *parent = rdev->dev.parent; const char *rname = rdev_get_name(rdev); char name[NAME_MAX]; + struct regulator *regulator; + const struct regulator_ops *ops; + mode_t mode; /* Avoid duplicate debugfs directory names */ if (parent && rname == rdev->desc->name) { @@ -3825,8 +4185,75 @@ &rdev->open_count); debugfs_create_u32("bypass_count", 0444, rdev->debugfs, &rdev->bypass_count); + debugfs_create_file("consumers", 0444, rdev->debugfs, rdev, + ®_consumers_fops); + + regulator = regulator_get(NULL, rdev_get_name(rdev)); + if (IS_ERR(regulator)) { + rdev_err(rdev, "regulator get failed, ret=%ld\n", + PTR_ERR(regulator)); + return; + } + rdev->debug_consumer = regulator; + + rdev->open_offset = 1; + ops = rdev->desc->ops; + + debugfs_create_file("enable", 0644, rdev->debugfs, regulator, + ®_enable_fops); + if (ops->set_bypass) + debugfs_create_file("bypass", 0644, rdev->debugfs, regulator, + ®_bypass_enable_fops); + + mode = 0; + if (ops->is_enabled) + mode |= 0444; + if (ops->disable) + mode |= 0200; + if (mode) + debugfs_create_file("force_disable", mode, rdev->debugfs, + regulator, ®_force_disable_fops); + + mode = 0; + if (ops->get_voltage || ops->get_voltage_sel) + mode |= 0444; + if (ops->set_voltage || ops->set_voltage_sel) + mode |= 0200; + if (mode) + debugfs_create_file("voltage", mode, rdev->debugfs, regulator, + ®_voltage_fops); + + mode = 0; + if (ops->get_mode) + mode |= 0444; + if (ops->set_mode) + mode |= 0200; + if (mode) + debugfs_create_file("mode", mode, rdev->debugfs, regulator, + ®_mode_fops); + + mode = 0; + if (ops->get_mode) + mode |= 0444; + if (ops->set_load || (ops->get_optimum_mode && ops->set_mode)) + mode |= 0200; + if (mode) + debugfs_create_file("load", mode, rdev->debugfs, regulator, + ®_set_load_fops); +} + +#else + +static inline void rdev_deinit_debugfs(struct regulator_dev *rdev) +{ +} + +static inline void rdev_init_debugfs(struct regulator_dev *rdev) +{ } +#endif + /** * regulator_register - register regulator * @regulator_desc: regulator to register @@ -3972,7 +4399,13 @@ } } + mutex_unlock(®ulator_list_mutex); rdev_init_debugfs(rdev); + rdev->proxy_consumer = regulator_proxy_consumer_register(dev, + config->of_node); + kfree(config); + return rdev; + out: mutex_unlock(®ulator_list_mutex); kfree(config); @@ -4013,8 +4446,9 @@ regulator_disable(rdev->supply); regulator_put(rdev->supply); } + regulator_proxy_consumer_unregister(rdev->proxy_consumer); + rdev_deinit_debugfs(rdev); mutex_lock(®ulator_list_mutex); - debugfs_remove_recursive(rdev->debugfs); flush_work(&rdev->disable_work.work); WARN_ON(rdev->open_count); unset_regulator_supplies(rdev); diff -ruw linux-4.4.115/drivers/regulator/internal.h linux-4.4.115-fbx/drivers/regulator/internal.h --- linux-4.4.115/drivers/regulator/internal.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/regulator/internal.h 2019-01-22 16:16:26.267271436 +0100 @@ -29,6 +29,7 @@ int uA_load; int min_uV; int max_uV; + int enabled; char *supply_name; struct device_attribute dev_attr; struct regulator_dev *rdev; diff -ruw linux-4.4.115/drivers/regulator/Kconfig linux-4.4.115-fbx/drivers/regulator/Kconfig --- linux-4.4.115/drivers/regulator/Kconfig 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/regulator/Kconfig 2019-01-22 16:16:26.255271328 +0100 @@ -241,6 +241,16 @@ input voltage supply of 2.5V to 5.5V. The output voltage is programmed through an I2C interface. +config REGULATOR_MSM_GFX_LDO + tristate "MSM GFX LDO Regulator" + depends on OF + help + This driver supports the MSM GFX (Graphics) LDO regulator. The + GFU core is either powered by an internal MSM LDO or by BHS. + Typically the lower voltage corners are powered by LDO and + the higher ones by BHS. This driver allows for configuration of + the rail between the LDO/BHS as well as the LDO voltage. + config REGULATOR_GPIO tristate "GPIO regulator support" depends on GPIOLIB || COMPILE_TEST @@ -334,6 +344,15 @@ regulator via I2C bus. The provided regulator is suitable for PXA27x chips to control VCC_CORE and VCC_USIM voltages. +config REGULATOR_MAX20010 + tristate "Maxim MAX20010 regulator support" + depends on I2C + help + This driver supports the Maxim MAX20010 switching voltage regulator + (buck converter). The regulator is controlled using an I2C interface + and supports 2 programmable voltage ranges from 0.5V to 1.27V in 10mV + steps and 0.625V to 1.5875V in 12.5mV steps. + config REGULATOR_MAX8649 tristate "Maxim 8649 voltage regulator" depends on I2C @@ -462,6 +481,15 @@ This driver supports the control of different power rails of device through regulator interface. +config REGULATOR_ONSEMI_NCP6335D + tristate "OnSemi NCP6335D regulator support" + depends on I2C + help + This driver supports the OnSemi NCP6335D switching voltage regulator + (buck converter). The regulator is controlled using an I2C interface + and supports a programmable voltage range from 0.6V to 1.4V in steps + of 6.25mV. + config REGULATOR_PALMAS tristate "TI Palmas PMIC Regulators" depends on MFD_PALMAS @@ -785,5 +813,195 @@ This driver provides support for the voltage regulators on the WM8994 CODEC. +config REGULATOR_RPM_SMD + bool "RPM SMD regulator driver" + depends on OF + depends on MSM_RPM_SMD + help + Compile in support for the RPM SMD regulator driver which is used for + setting voltages and other parameters of the various power rails + supplied by some Qualcomm PMICs. The RPM SMD regulator driver should + be used on systems which contain an RPM which communicates with the + application processor over SMD. + +config REGULATOR_QPNP + tristate "Qualcomm Technologies, Inc. QPNP regulator support" + depends on SPMI + help + This driver supports voltage regulators in Qualcomm Technologies, Inc. + PMIC chips which comply with QPNP. QPNP is a SPMI based PMIC + implementation. These chips provide several different varieties of + LDO and switching regulators. They also provide voltage switches and + boost regulators. + +config REGULATOR_QPNP_LABIBB + tristate "Qualcomm Technologies, Inc. QPNP LAB/IBB regulator support" + depends on SPMI + help + This driver supports voltage regulators in Qualcomm Technologies, Inc. + PMIC chips which comply with QPNP LAB/IBB regulators. QPNP LAB and IBB + are SPMI based PMIC implementations. LAB regulator can be used as a + regular positive boost regulator. IBB can be used as a regular + negative boost regulator. LAB/IBB regulators can also be used + together for LCD or AMOLED. + +config REGULATOR_QPNP_LCDB + tristate "Qualcomm Technologies, Inc. QPNP LCDB support" + depends on SPMI + help + Supports the LCDB module in the Qualcomm Technologies, Inc. + QPNP PMICs. Exposes regulators to control the positive and + negative voltage bias for the LCD display panel. It also + allows configurability for the various bias-voltage parameters. + +config REGULATOR_QPNP_OLEDB + tristate "Qualcomm Technologies, Inc. QPNP OLEDB regulator support" + depends on SPMI + help + This driver supports the OLEDB (AVDD bias) signal for AMOLED panel in + Qualcomm Technologies, Inc. QPNP PMICs. It exposes the OLED voltage + configuration via the regulator framework. The configurable range of + this bias is 5 V to 8.1 V. + +config REGULATOR_SPM + bool "SPM regulator driver" + depends on SPMI + help + Enable support for the SPM regulator driver which is used for + setting voltages of processor supply regulators via the SPM module + found inside of Qualcomm Technologies (QTI) chips. The SPM regulator + driver can be used on QTI SoCs where the APSS processor cores are + supplied by their own PMIC regulator. + +config REGULATOR_CPR + bool "RBCPR regulator driver for APC" + depends on OF + help + Compile in RBCPR (RapidBridge Core Power Reduction) driver to support + corner vote for APC power rail. The driver takes PTE process voltage + suggestions in efuse as initial settings. It converts corner vote + to voltage value before writing to a voltage regulator API, such as + that provided by spm-regulator driver. + +config REGULATOR_CPR2_GFX + bool "RBCPR regulator driver for GFX" + depends on OF + help + This driver supports the CPR (core power reduction) controller for the + graphics (GFX) rail. The GFX CPR2 controller monitors the graphics voltage + requirements. This driver reads initial voltage values out of hardware + fuses and CPR target quotient values out of device tree. + +config REGULATOR_CPR3 + bool "CPR3 regulator core support" + help + This driver supports Core Power Reduction (CPR) version 3 controllers + which are used by some Qualcomm Technologies, Inc. (QTI) SoCs to + manage important voltage regulators. CPR3 controllers are capable of + monitoring several ring oscillator sensing loops simultaneously. The + CPR3 controller informs software when the silicon conditions require + the supply voltage to be increased or decreased. On certain supply + rails, the CPR3 controller is able to propagate the voltage increase + or decrease requests all the way to the PMIC without software + involvement. + +config REGULATOR_CPR3_HMSS + bool "CPR3 regulator for HMSS" + depends on OF + select REGULATOR_CPR3 + help + This driver supports Qualcomm Technologies, Inc. HMSS application + processor specific features including memory array power mux (APM) + switching, two CPR3 threads which monitor the two HMSS clusters that + are both powered by a shared supply, and hardware closed-loop auto + voltage stepping. This driver reads both initial voltage and CPR + target quotient values out of hardware fuses. + +config REGULATOR_CPR3_MMSS + bool "RBCPR3 regulator for MMSS" + depends on OF + select REGULATOR_CPR3 + help + This driver supports Qualcomm Technologies, Inc. MMSS graphics + processor specific features. The MMSS CPR3 controller only uses one + thread to monitor the MMSS voltage requirements. This driver reads + initial voltage values out of hardware fuses and CPR target quotient + values out of device tree. + +config REGULATOR_CPR4_APSS + bool "CPR4 regulator for APSS" + depends on OF + select REGULATOR_CPR3 + help + This driver supports Qualcomm Technologies, Inc. APSS application + processor specific features including memory array power mux (APM) + switching, one CPR4 thread which monitor the two APSS clusters that + are both powered by a shared supply, hardware closed-loop auto + voltage stepping, voltage adjustments based on online core count, + voltage adjustments based on temperature readings, and voltage + adjustments for performance boost mode. This driver reads both initial + voltage and CPR target quotient values out of hardware fuses. + +config REGULATOR_CPRH_KBSS + bool "CPRH regulator for KBSS" + depends on OF + select REGULATOR_CPR3 + help + This driver supports Qualcomm Technologies, Inc. KBSS application + processor specific features including CPR hardening (CPRh) and two + CPRh controllers which monitor the two KBSS clusters each powered by + independent voltage supplies. This driver reads both initial voltage + and CPR target quotient values out of hardware fuses. + +config REGULATOR_CPR4_MMSS_LDO + bool "RBCPR3 regulator for MMSS LDO" + depends on OF + select REGULATOR_CPR3 + help + This driver supports Qualcomm Technologies, Inc. MMSS graphics + processor specific features. The MMSS CPR3 controller only uses one + thread to monitor the MMSS LDO voltage requirements. This driver reads + initial voltage values out of hardware fuses and CPR target quotient + values out of device tree. + +config REGULATOR_KRYO + bool "Kryo regulator driver" + depends on OF + help + Some MSM designs have CPUs that can be directly powered from a common + voltage rail via a Block Head Switch (BHS) or an LDO whose output + voltage can be configured for use when certain power constraints are + met. Say yes to support management of LDO and BHS modes for the + clusters in the CPU subsystem. + +config REGULATOR_MEM_ACC + tristate "QTI Memory accelerator regulator driver" + help + Say y here to enable the memory accelerator driver for Qualcomm + Technologies, Inc. (QTI) chips. The accelerator controls delays + applied for memory accesses. This driver configures the power-mode + (corner) for the memory accelerator. + +config REGULATOR_PROXY_CONSUMER + bool "Boot time regulator proxy consumer support" + help + This driver provides support for boot time regulator proxy requests. + It can enforce a specified voltage range, set a minimum current, + and/or keep a regulator enabled. It is needed in circumstances where + reducing one or more of these three quantities will cause hardware to + stop working if performed before the driver managing the hardware has + probed. + +config REGULATOR_STUB + tristate "Stub Regulator" + help + This driver adds stub regulator support. The driver is absent of any + real hardware based implementation. It allows for clients to register + their regulator device constraints and use all of the standard + regulator interfaces. This is useful for bringing up new platforms + when the real hardware based implementation may not be yet available. + Clients can use the real regulator device names with proper + constraint checking while the real driver is being developed. + endif diff -ruw linux-4.4.115/drivers/regulator/Makefile linux-4.4.115-fbx/drivers/regulator/Makefile --- linux-4.4.115/drivers/regulator/Makefile 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/regulator/Makefile 2019-01-22 16:16:26.255271328 +0100 @@ -33,6 +33,7 @@ obj-$(CONFIG_REGULATOR_DB8500_PRCMU) += db8500-prcmu.o obj-$(CONFIG_REGULATOR_FAN53555) += fan53555.o obj-$(CONFIG_REGULATOR_GPIO) += gpio-regulator.o +obj-$(CONFIG_REGULATOR_MSM_GFX_LDO) += msm_gfx_ldo.o obj-$(CONFIG_REGULATOR_HI6421) += hi6421-regulator.o obj-$(CONFIG_REGULATOR_ISL6271A) += isl6271a-regulator.o obj-$(CONFIG_REGULATOR_ISL9305) += isl9305.o @@ -45,6 +46,7 @@ obj-$(CONFIG_REGULATOR_LTC3589) += ltc3589.o obj-$(CONFIG_REGULATOR_MAX14577) += max14577.o obj-$(CONFIG_REGULATOR_MAX1586) += max1586.o +obj-$(CONFIG_REGULATOR_MAX20010) += max20010-regulator.o obj-$(CONFIG_REGULATOR_MAX8649) += max8649.o obj-$(CONFIG_REGULATOR_MAX8660) += max8660.o obj-$(CONFIG_REGULATOR_MAX8907) += max8907-regulator.o @@ -64,6 +66,7 @@ obj-$(CONFIG_REGULATOR_QCOM_RPM) += qcom_rpm-regulator.o obj-$(CONFIG_REGULATOR_QCOM_SMD_RPM) += qcom_smd-regulator.o obj-$(CONFIG_REGULATOR_QCOM_SPMI) += qcom_spmi-regulator.o +obj-$(CONFIG_REGULATOR_ONSEMI_NCP6335D) += onsemi-ncp6335d.o obj-$(CONFIG_REGULATOR_PALMAS) += palmas-regulator.o obj-$(CONFIG_REGULATOR_PFUZE100) += pfuze100-regulator.o obj-$(CONFIG_REGULATOR_PWM) += pwm-regulator.o @@ -102,5 +105,23 @@ obj-$(CONFIG_REGULATOR_WM8400) += wm8400-regulator.o obj-$(CONFIG_REGULATOR_WM8994) += wm8994-regulator.o +obj-$(CONFIG_REGULATOR_PROXY_CONSUMER) += proxy-consumer.o +obj-$(CONFIG_REGULATOR_MEM_ACC) += mem-acc-regulator.o +obj-$(CONFIG_REGULATOR_RPM_SMD) += rpm-smd-regulator.o +obj-$(CONFIG_REGULATOR_QPNP) += qpnp-regulator.o +obj-$(CONFIG_REGULATOR_SPM) += spm-regulator.o +obj-$(CONFIG_REGULATOR_CPR) += cpr-regulator.o +obj-$(CONFIG_REGULATOR_CPR3) += cpr3-regulator.o cpr3-util.o +obj-$(CONFIG_REGULATOR_CPR3_HMSS) += cpr3-hmss-regulator.o +obj-$(CONFIG_REGULATOR_CPR3_MMSS) += cpr3-mmss-regulator.o +obj-$(CONFIG_REGULATOR_CPR4_APSS) += cpr4-apss-regulator.o +obj-$(CONFIG_REGULATOR_CPRH_KBSS) += cprh-kbss-regulator.o +obj-$(CONFIG_REGULATOR_CPR4_MMSS_LDO) += cpr4-mmss-ldo-regulator.o +obj-$(CONFIG_REGULATOR_QPNP_LABIBB) += qpnp-labibb-regulator.o +obj-$(CONFIG_REGULATOR_QPNP_LCDB) += qpnp-lcdb-regulator.o +obj-$(CONFIG_REGULATOR_QPNP_OLEDB) += qpnp-oledb-regulator.o +obj-$(CONFIG_REGULATOR_STUB) += stub-regulator.o +obj-$(CONFIG_REGULATOR_KRYO) += kryo-regulator.o +obj-$(CONFIG_REGULATOR_CPR2_GFX) += cpr2-gfx-regulator.o ccflags-$(CONFIG_REGULATOR_DEBUG) += -DDEBUG diff -ruw linux-4.4.115/drivers/rtc/interface.c linux-4.4.115-fbx/drivers/rtc/interface.c --- linux-4.4.115/drivers/rtc/interface.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/rtc/interface.c 2019-10-29 09:26:24.653213062 +0100 @@ -362,6 +362,14 @@ } EXPORT_SYMBOL_GPL(rtc_set_alarm); +static void rtc_alarm_disable(struct rtc_device *rtc) +{ + if (!rtc->ops || !rtc->ops->alarm_irq_enable) + return; + + rtc->ops->alarm_irq_enable(rtc->dev.parent, false); +} + /* Called once per device from rtc_device_register */ int rtc_initialize_alarm(struct rtc_device *rtc, struct rtc_wkalrm *alarm) { @@ -389,7 +397,11 @@ rtc->aie_timer.enabled = 1; timerqueue_add(&rtc->timerqueue, &rtc->aie_timer.node); + } else if (alarm->enabled && (rtc_tm_to_ktime(now).tv64 >= + rtc->aie_timer.node.expires.tv64)){ + rtc_alarm_disable(rtc); } + mutex_unlock(&rtc->ops_lock); return err; } @@ -782,14 +794,6 @@ return 0; } -static void rtc_alarm_disable(struct rtc_device *rtc) -{ - if (!rtc->ops || !rtc->ops->alarm_irq_enable) - return; - - rtc->ops->alarm_irq_enable(rtc->dev.parent, false); -} - /** * rtc_timer_remove - Removes a rtc_timer from the rtc_device timerqueue * @rtc rtc device diff -ruw linux-4.4.115/drivers/rtc/Kconfig linux-4.4.115-fbx/drivers/rtc/Kconfig --- linux-4.4.115/drivers/rtc/Kconfig 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/rtc/Kconfig 2019-10-29 09:26:24.653213062 +0100 @@ -1591,6 +1591,15 @@ This driver can also be built as a module. If so, the module will be called rtc-moxart +config RTC_DRV_QPNP + tristate "Qualcomm Technologies, Inc. QPNP PMIC RTC" + depends on SPMI + help + This enables support for the RTC found on Qualcomm Technologies, Inc. + QPNP PMIC chips. This driver supports using the PMIC RTC peripheral + to wake a mobile device up from suspend or to wake it up from power- + off. + config RTC_DRV_MT6397 tristate "Mediatek Real Time Clock driver" depends on MFD_MT6397 || COMPILE_TEST diff -ruw linux-4.4.115/drivers/rtc/Makefile linux-4.4.115-fbx/drivers/rtc/Makefile --- linux-4.4.115/drivers/rtc/Makefile 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/rtc/Makefile 2019-10-29 09:26:24.653213062 +0100 @@ -118,6 +118,7 @@ obj-$(CONFIG_RTC_DRV_PS3) += rtc-ps3.o obj-$(CONFIG_RTC_DRV_PUV3) += rtc-puv3.o obj-$(CONFIG_RTC_DRV_PXA) += rtc-pxa.o +obj-$(CONFIG_RTC_DRV_QPNP) += qpnp-rtc.o obj-$(CONFIG_RTC_DRV_R9701) += rtc-r9701.o obj-$(CONFIG_RTC_DRV_RC5T583) += rtc-rc5t583.o obj-$(CONFIG_RTC_DRV_RK808) += rtc-rk808.o diff -ruw linux-4.4.115/drivers/scsi/scsi_pm.c linux-4.4.115-fbx/drivers/scsi/scsi_pm.c --- linux-4.4.115/drivers/scsi/scsi_pm.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/scsi/scsi_pm.c 2019-01-22 16:16:26.607274515 +0100 @@ -16,6 +16,9 @@ #include "scsi_priv.h" +static int do_scsi_runtime_resume(struct device *dev, + const struct dev_pm_ops *pm); + #ifdef CONFIG_PM_SLEEP static int do_scsi_suspend(struct device *dev, const struct dev_pm_ops *pm) @@ -77,10 +80,22 @@ scsi_device_resume(to_scsi_device(dev)); dev_dbg(dev, "scsi resume: %d\n", err); - if (err == 0) { + if (err == 0 && (cb != do_scsi_runtime_resume)) { pm_runtime_disable(dev); - pm_runtime_set_active(dev); + err = pm_runtime_set_active(dev); pm_runtime_enable(dev); + + if (!err && scsi_is_sdev_device(dev)) { + struct scsi_device *sdev = to_scsi_device(dev); + + /* + * If scsi device runtime PM is managed by block layer + * then we should update request queue's runtime status + * as well. + */ + if (sdev->request_queue->dev) + blk_post_runtime_resume(sdev->request_queue, 0); + } } return err; @@ -213,12 +228,32 @@ #endif /* CONFIG_PM_SLEEP */ +static int do_scsi_runtime_suspend(struct device *dev, + const struct dev_pm_ops *pm) +{ + return pm && pm->runtime_suspend ? pm->runtime_suspend(dev) : 0; +} + +static int do_scsi_runtime_resume(struct device *dev, + const struct dev_pm_ops *pm) +{ + return pm && pm->runtime_resume ? pm->runtime_resume(dev) : 0; +} + static int sdev_runtime_suspend(struct device *dev) { const struct dev_pm_ops *pm = dev->driver ? dev->driver->pm : NULL; struct scsi_device *sdev = to_scsi_device(dev); int err = 0; + if (!sdev->request_queue->dev) { + err = scsi_dev_type_suspend(dev, do_scsi_runtime_suspend); + if (err == -EAGAIN) + pm_schedule_suspend(dev, jiffies_to_msecs( + round_jiffies_up_relative(HZ/10))); + return err; + } + err = blk_pre_runtime_suspend(sdev->request_queue); if (err) return err; @@ -248,6 +283,9 @@ const struct dev_pm_ops *pm = dev->driver ? dev->driver->pm : NULL; int err = 0; + if (!sdev->request_queue->dev) + return scsi_dev_type_resume(dev, do_scsi_runtime_resume); + blk_pre_runtime_resume(sdev->request_queue); if (pm && pm->runtime_resume) err = pm->runtime_resume(dev); diff -ruw linux-4.4.115/drivers/scsi/scsi_scan.c linux-4.4.115-fbx/drivers/scsi/scsi_scan.c --- linux-4.4.115/drivers/scsi/scsi_scan.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/scsi/scsi_scan.c 2019-10-29 09:26:24.785214354 +0100 @@ -820,15 +820,10 @@ * well-known logical units. Force well-known type * to enumerate them correctly. */ - if (scsi_is_wlun(sdev->lun) && sdev->type != TYPE_WLUN) { - sdev_printk(KERN_WARNING, sdev, - "%s: correcting incorrect peripheral device type 0x%x for W-LUN 0x%16xhN\n", - __func__, sdev->type, (unsigned int)sdev->lun); + if (scsi_is_wlun(sdev->lun) && sdev->type != TYPE_WLUN) sdev->type = TYPE_WLUN; } - } - if (sdev->type == TYPE_RBC || sdev->type == TYPE_ROM) { /* RBC and MMC devices can return SCSI-3 compliance and yet * still not support REPORT LUNS, so make them act as @@ -971,6 +966,10 @@ transport_configure_device(&sdev->sdev_gendev); + /* The LLD can override auto suspend tunables in ->slave_configure() */ + sdev->use_rpm_auto = 0; + sdev->autosuspend_delay = SCSI_DEFAULT_AUTOSUSPEND_DELAY; + if (sdev->host->hostt->slave_configure) { ret = sdev->host->hostt->slave_configure(sdev); if (ret) { diff -ruw linux-4.4.115/drivers/scsi/scsi_sysfs.c linux-4.4.115-fbx/drivers/scsi/scsi_sysfs.c --- linux-4.4.115/drivers/scsi/scsi_sysfs.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/scsi/scsi_sysfs.c 2019-10-29 09:26:24.785214354 +0100 @@ -1040,6 +1040,7 @@ device_enable_async_suspend(&sdev->sdev_gendev); scsi_autopm_get_target(starget); pm_runtime_set_active(&sdev->sdev_gendev); + if (!sdev->use_rpm_auto) pm_runtime_forbid(&sdev->sdev_gendev); pm_runtime_enable(&sdev->sdev_gendev); scsi_autopm_put_target(starget); diff -ruw linux-4.4.115/drivers/scsi/sd.c linux-4.4.115-fbx/drivers/scsi/sd.c --- linux-4.4.115/drivers/scsi/sd.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/scsi/sd.c 2019-10-29 09:26:24.789214393 +0100 @@ -601,6 +601,31 @@ mutex_unlock(&sd_ref_mutex); } +struct gendisk *scsi_gendisk_get_from_dev(struct device *dev) +{ + struct scsi_disk *sdkp; + + mutex_lock(&sd_ref_mutex); + sdkp = dev_get_drvdata(dev); + if (sdkp) + sdkp = scsi_disk_get(sdkp->disk); + mutex_unlock(&sd_ref_mutex); + return !sdkp ? NULL : sdkp->disk; +} +EXPORT_SYMBOL(scsi_gendisk_get_from_dev); + +void scsi_gendisk_put(struct device *dev) +{ + struct scsi_disk *sdkp = dev_get_drvdata(dev); + struct scsi_device *sdev = sdkp->device; + + mutex_lock(&sd_ref_mutex); + put_device(&sdkp->dev); + scsi_device_put(sdev); + mutex_unlock(&sd_ref_mutex); +} +EXPORT_SYMBOL(scsi_gendisk_put); + static unsigned char sd_setup_protect_cmnd(struct scsi_cmnd *scmd, unsigned int dix, unsigned int dif) { @@ -1395,86 +1420,6 @@ return 0; } -/** - * sd_check_events - check media events - * @disk: kernel device descriptor - * @clearing: disk events currently being cleared - * - * Returns mask of DISK_EVENT_*. - * - * Note: this function is invoked from the block subsystem. - **/ -static unsigned int sd_check_events(struct gendisk *disk, unsigned int clearing) -{ - struct scsi_disk *sdkp = scsi_disk_get(disk); - struct scsi_device *sdp; - struct scsi_sense_hdr *sshdr = NULL; - int retval; - - if (!sdkp) - return 0; - - sdp = sdkp->device; - SCSI_LOG_HLQUEUE(3, sd_printk(KERN_INFO, sdkp, "sd_check_events\n")); - - /* - * If the device is offline, don't send any commands - just pretend as - * if the command failed. If the device ever comes back online, we - * can deal with it then. It is only because of unrecoverable errors - * that we would ever take a device offline in the first place. - */ - if (!scsi_device_online(sdp)) { - set_media_not_present(sdkp); - goto out; - } - - /* - * Using TEST_UNIT_READY enables differentiation between drive with - * no cartridge loaded - NOT READY, drive with changed cartridge - - * UNIT ATTENTION, or with same cartridge - GOOD STATUS. - * - * Drives that auto spin down. eg iomega jaz 1G, will be started - * by sd_spinup_disk() from sd_revalidate_disk(), which happens whenever - * sd_revalidate() is called. - */ - retval = -ENODEV; - - if (scsi_block_when_processing_errors(sdp)) { - sshdr = kzalloc(sizeof(*sshdr), GFP_KERNEL); - retval = scsi_test_unit_ready(sdp, SD_TIMEOUT, SD_MAX_RETRIES, - sshdr); - } - - /* failed to execute TUR, assume media not present */ - if (host_byte(retval)) { - set_media_not_present(sdkp); - goto out; - } - - if (media_not_present(sdkp, sshdr)) - goto out; - - /* - * For removable scsi disk we have to recognise the presence - * of a disk in the drive. - */ - if (!sdkp->media_present) - sdp->changed = 1; - sdkp->media_present = 1; -out: - /* - * sdp->changed is set under the following conditions: - * - * Medium present state has changed in either direction. - * Device has indicated UNIT_ATTENTION. - */ - kfree(sshdr); - retval = sdp->changed ? DISK_EVENT_MEDIA_CHANGE : 0; - sdp->changed = 0; - scsi_disk_put(sdkp); - return retval; -} - static int sd_sync_cache(struct scsi_disk *sdkp) { int retries, res; @@ -1667,7 +1612,6 @@ #ifdef CONFIG_COMPAT .compat_ioctl = sd_compat_ioctl, #endif - .check_events = sd_check_events, .revalidate_disk = sd_revalidate_disk, .unlock_native_capacity = sd_unlock_native_capacity, .pr_ops = &sd_pr_ops, @@ -2352,11 +2296,6 @@ sizeof(cap_str_10)); if (sdkp->first_scan || old_capacity != sdkp->capacity) { - sd_printk(KERN_NOTICE, sdkp, - "%llu %d-byte logical blocks: (%s/%s)\n", - (unsigned long long)sdkp->capacity, - sector_size, cap_str_10, cap_str_2); - if (sdkp->physical_block_size != sector_size) sd_printk(KERN_NOTICE, sdkp, "%u-byte physical blocks\n", @@ -2393,7 +2332,6 @@ int res; struct scsi_device *sdp = sdkp->device; struct scsi_mode_data data; - int old_wp = sdkp->write_prot; set_disk_ro(sdkp->disk, 0); if (sdp->skip_ms_page_3f) { @@ -2434,13 +2372,6 @@ } else { sdkp->write_prot = ((data.device_specific & 0x80) != 0); set_disk_ro(sdkp->disk, sdkp->write_prot); - if (sdkp->first_scan || old_wp != sdkp->write_prot) { - sd_printk(KERN_NOTICE, sdkp, "Write Protect is %s\n", - sdkp->write_prot ? "on" : "off"); - sd_printk(KERN_DEBUG, sdkp, - "Mode Sense: %02x %02x %02x %02x\n", - buffer[0], buffer[1], buffer[2], buffer[3]); - } } } @@ -2453,16 +2384,13 @@ { int len = 0, res; struct scsi_device *sdp = sdkp->device; + struct Scsi_Host *host = sdp->host; int dbd; int modepage; int first_len; struct scsi_mode_data data; struct scsi_sense_hdr sshdr; - int old_wce = sdkp->WCE; - int old_rcd = sdkp->RCD; - int old_dpofua = sdkp->DPOFUA; - if (sdkp->cache_override) return; @@ -2484,6 +2412,9 @@ dbd = 8; } else { modepage = 8; + if (host->set_dbd_for_caching) + dbd = 8; + else dbd = 0; } @@ -2585,15 +2516,6 @@ if (sdkp->WCE && sdkp->write_prot) sdkp->WCE = 0; - if (sdkp->first_scan || old_wce != sdkp->WCE || - old_rcd != sdkp->RCD || old_dpofua != sdkp->DPOFUA) - sd_printk(KERN_NOTICE, sdkp, - "Write cache: %s, read cache: %s, %s\n", - sdkp->WCE ? "enabled" : "disabled", - sdkp->RCD ? "disabled" : "enabled", - sdkp->DPOFUA ? "supports DPO and FUA" - : "doesn't support DPO or FUA"); - return; } @@ -2907,10 +2829,10 @@ if (sdkp->opt_xfer_blocks && sdkp->opt_xfer_blocks <= dev_max && sdkp->opt_xfer_blocks <= SD_DEF_XFER_BLOCKS && - logical_to_bytes(sdp, sdkp->opt_xfer_blocks) >= PAGE_CACHE_SIZE) { - q->limits.io_opt = logical_to_bytes(sdp, sdkp->opt_xfer_blocks); - rw_max = logical_to_sectors(sdp, sdkp->opt_xfer_blocks); - } else + sdkp->opt_xfer_blocks * sdp->sector_size >= PAGE_CACHE_SIZE) + rw_max = q->limits.io_opt = + sdkp->opt_xfer_blocks * sdp->sector_size; + else rw_max = min_not_zero(logical_to_sectors(sdp, dev_max), (sector_t)BLK_DEF_MAX_SECTORS); @@ -3048,14 +2970,15 @@ } blk_pm_runtime_init(sdp->request_queue, dev); + if (sdp->autosuspend_delay >= 0) + pm_runtime_set_autosuspend_delay(dev, sdp->autosuspend_delay); + add_disk(gd); if (sdkp->capacity) sd_dif_config_host(sdkp); sd_revalidate_disk(gd); - sd_printk(KERN_NOTICE, sdkp, "Attached SCSI %sdisk\n", - sdp->removable ? "removable " : ""); scsi_autopm_put_device(sdp); put_device(&sdkp->dev); } @@ -3300,7 +3223,6 @@ return 0; if (sdkp->WCE && sdkp->media_present) { - sd_printk(KERN_NOTICE, sdkp, "Synchronizing SCSI cache\n"); ret = sd_sync_cache(sdkp); if (ret) { /* ignore OFFLINE device */ @@ -3311,7 +3233,7 @@ } if (sdkp->device->manage_start_stop) { - sd_printk(KERN_NOTICE, sdkp, "Stopping disk\n"); + sd_printk(KERN_DEBUG, sdkp, "Stopping disk\n"); /* an error is not worth aborting a system sleep */ ret = sd_start_stop_device(sdkp, 0); if (ignore_stop_errors) @@ -3342,7 +3264,7 @@ if (!sdkp->device->manage_start_stop) return 0; - sd_printk(KERN_NOTICE, sdkp, "Starting disk\n"); + sd_printk(KERN_DEBUG, sdkp, "Starting disk\n"); return sd_start_stop_device(sdkp, 1); } diff -ruw linux-4.4.115/drivers/scsi/sd.h linux-4.4.115-fbx/drivers/scsi/sd.h --- linux-4.4.115/drivers/scsi/sd.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/scsi/sd.h 2019-01-22 16:16:26.611274551 +0100 @@ -151,11 +151,6 @@ return blocks << (ilog2(sdev->sector_size) - 9); } -static inline unsigned int logical_to_bytes(struct scsi_device *sdev, sector_t blocks) -{ - return blocks * sdev->sector_size; -} - /* * A DIF-capable target device can be formatted with different * protection schemes. Currently 0 through 3 are defined: diff -ruw linux-4.4.115/drivers/scsi/sg.c linux-4.4.115-fbx/drivers/scsi/sg.c --- linux-4.4.115/drivers/scsi/sg.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/scsi/sg.c 2019-10-29 09:26:24.793214432 +0100 @@ -897,8 +897,10 @@ return -ENXIO; if (!access_ok(VERIFY_WRITE, p, SZ_SG_IO_HDR)) return -EFAULT; + mutex_lock(&sfp->parentdp->open_rel_lock); result = sg_new_write(sfp, filp, p, SZ_SG_IO_HDR, 1, read_only, 1, &srp); + mutex_unlock(&sfp->parentdp->open_rel_lock); if (result < 0) return result; result = wait_event_interruptible(sfp->read_wait, @@ -1009,9 +1011,10 @@ mutex_unlock(&sfp->f_mutex); return -EBUSY; } - + mutex_lock(&sfp->parentdp->open_rel_lock); sg_remove_scat(sfp, &sfp->reserve); sg_build_reserve(sfp, val); + mutex_unlock(&sfp->parentdp->open_rel_lock); } mutex_unlock(&sfp->f_mutex); return 0; @@ -1531,9 +1534,6 @@ } else pr_warn("%s: sg_sys Invalid\n", __func__); - sdev_printk(KERN_NOTICE, scsidp, "Attached scsi generic sg%d " - "type %d\n", sdp->index, scsidp->type); - dev_set_drvdata(cl_dev, sdp); return 0; @@ -2072,11 +2072,12 @@ if ((1 == resp->done) && (!resp->sg_io_owned) && ((-1 == pack_id) || (resp->header.pack_id == pack_id))) { resp->done = 2; /* guard against other readers */ - break; + write_unlock_irqrestore(&sfp->rq_list_lock, iflags); + return resp; } } write_unlock_irqrestore(&sfp->rq_list_lock, iflags); - return resp; + return NULL; } /* always adds to end of list */ @@ -2631,6 +2632,9 @@ seq_puts(s, srp->done ? ((1 == srp->done) ? "rcv:" : "fin:") : "act:"); + seq_printf(s, srp->done ? + ((1 == srp->done) ? "rcv:" : "fin:") + : "act:"); seq_printf(s, " id=%d blen=%d", srp->header.pack_id, blen); if (srp->done) diff -ruw linux-4.4.115/drivers/scsi/ufs/Kconfig linux-4.4.115-fbx/drivers/scsi/ufs/Kconfig --- linux-4.4.115/drivers/scsi/ufs/Kconfig 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/scsi/ufs/Kconfig 2019-01-22 16:16:26.627274696 +0100 @@ -83,3 +83,38 @@ Select this if you have UFS controller on QCOM chipset. If unsure, say N. + +config SCSI_UFS_QCOM_ICE + bool "QCOM specific hooks to Inline Crypto Engine for UFS driver" + depends on SCSI_UFS_QCOM && CRYPTO_DEV_QCOM_ICE + help + This selects the QCOM specific additions to support Inline Crypto + Engine (ICE). + ICE accelerates the crypto operations and maintains the high UFS + performance. + + Select this if you have ICE supported for UFS on QCOM chipset. + If unsure, say N. + + +config SCSI_UFS_TEST + tristate "Universal Flash Storage host controller driver unit-tests" + depends on SCSI_UFSHCD && IOSCHED_TEST + default m + ---help--- + This adds UFS Host controller unit-test framework. + The UFS unit-tests register as a block device test utility to + the test-iosched and will be initiated when the test-iosched will + be chosen to be the active I/O scheduler. + +config SCSI_UFSHCD_CMD_LOGGING + bool "Universal Flash Storage host controller driver layer command logging support" + depends on SCSI_UFSHCD + help + This selects the UFS host controller driver layer command logging. + UFS host controller driver layer command logging records all the + command information sent from UFS host controller for debugging + purpose. + + Select this if you want above mentioned debug information captured. + If unsure, say N. diff -ruw linux-4.4.115/drivers/scsi/ufs/Makefile linux-4.4.115-fbx/drivers/scsi/ufs/Makefile --- linux-4.4.115/drivers/scsi/ufs/Makefile 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/scsi/ufs/Makefile 2019-01-22 16:16:26.627274696 +0100 @@ -1,5 +1,8 @@ # UFSHCD makefile obj-$(CONFIG_SCSI_UFS_QCOM) += ufs-qcom.o -obj-$(CONFIG_SCSI_UFSHCD) += ufshcd.o +obj-$(CONFIG_SCSI_UFS_QCOM_ICE) += ufs-qcom-ice.o +obj-$(CONFIG_SCSI_UFSHCD) += ufshcd.o ufs_quirks.o obj-$(CONFIG_SCSI_UFSHCD_PCI) += ufshcd-pci.o obj-$(CONFIG_SCSI_UFSHCD_PLATFORM) += ufshcd-pltfrm.o +obj-$(CONFIG_SCSI_UFS_TEST) += ufs_test.o +obj-$(CONFIG_DEBUG_FS) += ufs-debugfs.o ufs-qcom-debugfs.o diff -ruw linux-4.4.115/drivers/scsi/ufs/ufs.h linux-4.4.115-fbx/drivers/scsi/ufs/ufs.h --- linux-4.4.115/drivers/scsi/ufs/ufs.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/scsi/ufs/ufs.h 2019-10-29 09:26:24.797214471 +0100 @@ -38,13 +38,16 @@ #include #include +#include #define MAX_CDB_SIZE 16 #define GENERAL_UPIU_REQUEST_SIZE 32 #define QUERY_DESC_MAX_SIZE 255 #define QUERY_DESC_MIN_SIZE 2 +#define QUERY_DESC_HDR_SIZE 2 #define QUERY_OSF_SIZE (GENERAL_UPIU_REQUEST_SIZE - \ (sizeof(struct utp_upiu_header))) +#define RESPONSE_UPIU_SENSE_DATA_LENGTH 18 #define UPIU_HEADER_DWORD(byte3, byte2, byte1, byte0)\ cpu_to_be32((byte3 << 24) | (byte2 << 16) |\ @@ -71,6 +74,16 @@ UFS_UPIU_RPMB_WLUN = 0xC4, }; +/** + * ufs_is_valid_unit_desc_lun - checks if the given LUN has a unit descriptor + * @lun: LU number to check + * @return: true if the lun has a matching unit descriptor, false otherwise + */ +static inline bool ufs_is_valid_unit_desc_lun(u8 lun) +{ + return lun == UFS_UPIU_RPMB_WLUN || (lun < UFS_UPIU_MAX_GENERAL_LUN); +} + /* * UFS Protocol Information Unit related definitions */ @@ -126,42 +139,13 @@ UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST = 0x81, }; -/* Flag idn for Query Requests*/ -enum flag_idn { - QUERY_FLAG_IDN_FDEVICEINIT = 0x01, - QUERY_FLAG_IDN_PWR_ON_WPE = 0x03, - QUERY_FLAG_IDN_BKOPS_EN = 0x04, -}; - -/* Attribute idn for Query requests */ -enum attr_idn { - QUERY_ATTR_IDN_ACTIVE_ICC_LVL = 0x03, - QUERY_ATTR_IDN_BKOPS_STATUS = 0x05, - QUERY_ATTR_IDN_EE_CONTROL = 0x0D, - QUERY_ATTR_IDN_EE_STATUS = 0x0E, -}; - -/* Descriptor idn for Query requests */ -enum desc_idn { - QUERY_DESC_IDN_DEVICE = 0x0, - QUERY_DESC_IDN_CONFIGURAION = 0x1, - QUERY_DESC_IDN_UNIT = 0x2, - QUERY_DESC_IDN_RFU_0 = 0x3, - QUERY_DESC_IDN_INTERCONNECT = 0x4, - QUERY_DESC_IDN_STRING = 0x5, - QUERY_DESC_IDN_RFU_1 = 0x6, - QUERY_DESC_IDN_GEOMETRY = 0x7, - QUERY_DESC_IDN_POWER = 0x8, - QUERY_DESC_IDN_MAX, -}; - enum desc_header_offset { QUERY_DESC_LENGTH_OFFSET = 0x00, QUERY_DESC_DESC_TYPE_OFFSET = 0x01, }; enum ufs_desc_max_size { - QUERY_DESC_DEVICE_MAX_SIZE = 0x1F, + QUERY_DESC_DEVICE_MAX_SIZE = 0x40, QUERY_DESC_CONFIGURAION_MAX_SIZE = 0x90, QUERY_DESC_UNIT_MAX_SIZE = 0x23, QUERY_DESC_INTERCONNECT_MAX_SIZE = 0x06, @@ -195,6 +179,36 @@ UNIT_DESC_PARAM_LARGE_UNIT_SIZE_M1 = 0x22, }; +/* Device descriptor parameters offsets in bytes*/ +enum device_desc_param { + DEVICE_DESC_PARAM_LEN = 0x0, + DEVICE_DESC_PARAM_TYPE = 0x1, + DEVICE_DESC_PARAM_DEVICE_TYPE = 0x2, + DEVICE_DESC_PARAM_DEVICE_CLASS = 0x3, + DEVICE_DESC_PARAM_DEVICE_SUB_CLASS = 0x4, + DEVICE_DESC_PARAM_PRTCL = 0x5, + DEVICE_DESC_PARAM_NUM_LU = 0x6, + DEVICE_DESC_PARAM_NUM_WLU = 0x7, + DEVICE_DESC_PARAM_BOOT_ENBL = 0x8, + DEVICE_DESC_PARAM_DESC_ACCSS_ENBL = 0x9, + DEVICE_DESC_PARAM_INIT_PWR_MODE = 0xA, + DEVICE_DESC_PARAM_HIGH_PR_LUN = 0xB, + DEVICE_DESC_PARAM_SEC_RMV_TYPE = 0xC, + DEVICE_DESC_PARAM_SEC_LU = 0xD, + DEVICE_DESC_PARAM_BKOP_TERM_LT = 0xE, + DEVICE_DESC_PARAM_ACTVE_ICC_LVL = 0xF, + DEVICE_DESC_PARAM_SPEC_VER = 0x10, + DEVICE_DESC_PARAM_MANF_DATE = 0x12, + DEVICE_DESC_PARAM_MANF_NAME = 0x14, + DEVICE_DESC_PARAM_PRDCT_NAME = 0x15, + DEVICE_DESC_PARAM_SN = 0x16, + DEVICE_DESC_PARAM_OEM_ID = 0x17, + DEVICE_DESC_PARAM_MANF_ID = 0x18, + DEVICE_DESC_PARAM_UD_OFFSET = 0x1A, + DEVICE_DESC_PARAM_UD_LEN = 0x1B, + DEVICE_DESC_PARAM_RTT_CAP = 0x1C, + DEVICE_DESC_PARAM_FRQ_RTC = 0x1D, +}; /* * Logical Unit Write Protect * 00h: LU not write protected @@ -247,19 +261,6 @@ BKOPS_STATUS_MAX = BKOPS_STATUS_CRITICAL, }; -/* UTP QUERY Transaction Specific Fields OpCode */ -enum query_opcode { - UPIU_QUERY_OPCODE_NOP = 0x0, - UPIU_QUERY_OPCODE_READ_DESC = 0x1, - UPIU_QUERY_OPCODE_WRITE_DESC = 0x2, - UPIU_QUERY_OPCODE_READ_ATTR = 0x3, - UPIU_QUERY_OPCODE_WRITE_ATTR = 0x4, - UPIU_QUERY_OPCODE_READ_FLAG = 0x5, - UPIU_QUERY_OPCODE_SET_FLAG = 0x6, - UPIU_QUERY_OPCODE_CLEAR_FLAG = 0x7, - UPIU_QUERY_OPCODE_TOGGLE_FLAG = 0x8, -}; - /* Query response result code */ enum { QUERY_RESULT_SUCCESS = 0x00, @@ -383,7 +384,7 @@ __be32 residual_transfer_count; __be32 reserved[4]; __be16 sense_data_len; - u8 sense_data[18]; + u8 sense_data[RESPONSE_UPIU_SENSE_DATA_LENGTH]; }; /** @@ -469,6 +470,7 @@ struct regulator *reg; const char *name; bool enabled; + bool unused; int min_uV; int max_uV; int min_uA; diff -ruw linux-4.4.115/drivers/scsi/ufs/ufshcd.c linux-4.4.115-fbx/drivers/scsi/ufs/ufshcd.c --- linux-4.4.115/drivers/scsi/ufs/ufshcd.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/scsi/ufs/ufshcd.c 2019-10-29 09:26:24.801214510 +0100 @@ -3,7 +3,7 @@ * * This code is based on drivers/scsi/ufs/ufshcd.c * Copyright (C) 2011-2013 Samsung India Software Operations - * Copyright (c) 2013-2014, The Linux Foundation. All rights reserved. + * Copyright (c) 2013-2017, The Linux Foundation. All rights reserved. * * Authors: * Santosh Yaraganavi @@ -38,10 +38,145 @@ */ #include +#include #include +#include +#include +#include #include "ufshcd.h" -#include "unipro.h" +#include "ufshci.h" +#include "ufs_quirks.h" +#include "ufs-debugfs.h" +#include "ufs-qcom.h" + +#define CREATE_TRACE_POINTS +#include + +#ifdef CONFIG_DEBUG_FS + +static int ufshcd_tag_req_type(struct request *rq) +{ + int rq_type = TS_WRITE; + + if (!rq || !(rq->cmd_type & REQ_TYPE_FS)) + rq_type = TS_NOT_SUPPORTED; + else if (rq->cmd_flags & REQ_FLUSH) + rq_type = TS_FLUSH; + else if (rq_data_dir(rq) == READ) + rq_type = (rq->cmd_flags & REQ_URGENT) ? + TS_URGENT_READ : TS_READ; + else if (rq->cmd_flags & REQ_URGENT) + rq_type = TS_URGENT_WRITE; + + return rq_type; +} + +static void ufshcd_update_error_stats(struct ufs_hba *hba, int type) +{ + ufsdbg_set_err_state(hba); + if (type < UFS_ERR_MAX) + hba->ufs_stats.err_stats[type]++; +} + +static void ufshcd_update_tag_stats(struct ufs_hba *hba, int tag) +{ + struct request *rq = + hba->lrb[tag].cmd ? hba->lrb[tag].cmd->request : NULL; + u64 **tag_stats = hba->ufs_stats.tag_stats; + int rq_type; + + if (!hba->ufs_stats.enabled) + return; + + tag_stats[tag][TS_TAG]++; + if (!rq || !(rq->cmd_type & REQ_TYPE_FS)) + return; + + WARN_ON(hba->ufs_stats.q_depth > hba->nutrs); + rq_type = ufshcd_tag_req_type(rq); + if (!(rq_type < 0 || rq_type > TS_NUM_STATS)) + tag_stats[hba->ufs_stats.q_depth++][rq_type]++; +} + +static void ufshcd_update_tag_stats_completion(struct ufs_hba *hba, + struct scsi_cmnd *cmd) +{ + struct request *rq = cmd ? cmd->request : NULL; + + if (rq && rq->cmd_type & REQ_TYPE_FS) + hba->ufs_stats.q_depth--; +} + +static void update_req_stats(struct ufs_hba *hba, struct ufshcd_lrb *lrbp) +{ + int rq_type; + struct request *rq = lrbp->cmd ? lrbp->cmd->request : NULL; + s64 delta = ktime_us_delta(lrbp->complete_time_stamp, + lrbp->issue_time_stamp); + + /* update general request statistics */ + if (hba->ufs_stats.req_stats[TS_TAG].count == 0) + hba->ufs_stats.req_stats[TS_TAG].min = delta; + hba->ufs_stats.req_stats[TS_TAG].count++; + hba->ufs_stats.req_stats[TS_TAG].sum += delta; + if (delta > hba->ufs_stats.req_stats[TS_TAG].max) + hba->ufs_stats.req_stats[TS_TAG].max = delta; + if (delta < hba->ufs_stats.req_stats[TS_TAG].min) + hba->ufs_stats.req_stats[TS_TAG].min = delta; + + rq_type = ufshcd_tag_req_type(rq); + if (rq_type == TS_NOT_SUPPORTED) + return; + + /* update request type specific statistics */ + if (hba->ufs_stats.req_stats[rq_type].count == 0) + hba->ufs_stats.req_stats[rq_type].min = delta; + hba->ufs_stats.req_stats[rq_type].count++; + hba->ufs_stats.req_stats[rq_type].sum += delta; + if (delta > hba->ufs_stats.req_stats[rq_type].max) + hba->ufs_stats.req_stats[rq_type].max = delta; + if (delta < hba->ufs_stats.req_stats[rq_type].min) + hba->ufs_stats.req_stats[rq_type].min = delta; +} + +static void +ufshcd_update_query_stats(struct ufs_hba *hba, enum query_opcode opcode, u8 idn) +{ + if (opcode < UPIU_QUERY_OPCODE_MAX && idn < MAX_QUERY_IDN) + hba->ufs_stats.query_stats_arr[opcode][idn]++; +} + +#else +static inline void ufshcd_update_tag_stats(struct ufs_hba *hba, int tag) +{ +} + +static inline void ufshcd_update_tag_stats_completion(struct ufs_hba *hba, + struct scsi_cmnd *cmd) +{ +} + +static inline void ufshcd_update_error_stats(struct ufs_hba *hba, int type) +{ +} + +static inline +void update_req_stats(struct ufs_hba *hba, struct ufshcd_lrb *lrbp) +{ +} + +static inline +void ufshcd_update_query_stats(struct ufs_hba *hba, + enum query_opcode opcode, u8 idn) +{ +} +#endif + +#define PWR_INFO_MASK 0xF +#define PWR_RX_OFFSET 4 + +#define UFSHCD_REQ_SENSE_SIZE 18 #define UFSHCD_ENABLE_INTRS (UTP_TRANSFER_REQ_COMPL |\ UTP_TASK_REQ_COMPL |\ @@ -55,16 +190,22 @@ #define NOP_OUT_TIMEOUT 30 /* msecs */ /* Query request retries */ -#define QUERY_REQ_RETRIES 10 +#define QUERY_REQ_RETRIES 3 /* Query request timeout */ -#define QUERY_REQ_TIMEOUT 30 /* msec */ +#define QUERY_REQ_TIMEOUT 1500 /* 1.5 seconds */ /* Task management command timeout */ #define TM_CMD_TIMEOUT 100 /* msecs */ +/* maximum number of retries for a general UIC command */ +#define UFS_UIC_COMMAND_RETRIES 3 + /* maximum number of link-startup retries */ #define DME_LINKSTARTUP_RETRIES 3 +/* Maximum retries for Hibern8 enter */ +#define UIC_HIBERN8_ENTER_RETRIES 3 + /* maximum number of reset retries before giving up */ #define MAX_HOST_RESET_RETRIES 5 @@ -74,6 +215,17 @@ /* Interrupt aggregation default timeout, unit: 40us */ #define INT_AGGR_DEF_TO 0x02 +/* default value of auto suspend is 3 seconds */ +#define UFSHCD_AUTO_SUSPEND_DELAY_MS 3000 /* millisecs */ + +#define UFSHCD_CLK_GATING_DELAY_MS_PWR_SAVE 10 +#define UFSHCD_CLK_GATING_DELAY_MS_PERF 50 + +/* IOCTL opcode for command - ufs set device read only */ +#define UFS_IOCTL_BLKROSET BLKROSET + +#define UFSHCD_DEFAULT_LANES_PER_DIRECTION 2 + #define ufshcd_toggle_vreg(_dev, _vreg, _on) \ ({ \ int _ret; \ @@ -84,6 +236,9 @@ _ret; \ }) +#define ufshcd_hex_dump(prefix_str, buf, len) \ +print_hex_dump(KERN_ERR, prefix_str, DUMP_PREFIX_OFFSET, 16, 4, buf, len, false) + static u32 ufs_query_desc_max_size[] = { QUERY_DESC_DEVICE_MAX_SIZE, QUERY_DESC_CONFIGURAION_MAX_SIZE, @@ -119,9 +274,11 @@ /* UFSHCD UIC layer error flags */ enum { UFSHCD_UIC_DL_PA_INIT_ERROR = (1 << 0), /* Data link layer error */ - UFSHCD_UIC_NL_ERROR = (1 << 1), /* Network layer error */ - UFSHCD_UIC_TL_ERROR = (1 << 2), /* Transport Layer error */ - UFSHCD_UIC_DME_ERROR = (1 << 3), /* DME error */ + UFSHCD_UIC_DL_NAC_RECEIVED_ERROR = (1 << 1), /* Data link layer error */ + UFSHCD_UIC_DL_TCx_REPLAY_ERROR = (1 << 2), /* Data link layer error */ + UFSHCD_UIC_NL_ERROR = (1 << 3), /* Network layer error */ + UFSHCD_UIC_TL_ERROR = (1 << 4), /* Transport Layer error */ + UFSHCD_UIC_DME_ERROR = (1 << 5), /* DME error */ }; /* Interrupt configuration options */ @@ -131,6 +288,8 @@ UFSHCD_INT_CLEAR, }; +#define DEFAULT_UFSHCD_DBG_PRINT_EN UFSHCD_DBG_PRINT_ALL + #define ufshcd_set_eh_in_progress(h) \ (h->eh_flags |= UFSHCD_EH_IN_PROGRESS) #define ufshcd_eh_in_progress(h) \ @@ -172,49 +331,590 @@ return ufs_pm_lvl_states[lvl].link_state; } -static void ufshcd_tmc_handler(struct ufs_hba *hba); +static inline enum ufs_pm_level +ufs_get_desired_pm_lvl_for_dev_link_state(enum ufs_dev_pwr_mode dev_state, + enum uic_link_state link_state) +{ + enum ufs_pm_level lvl; + + for (lvl = UFS_PM_LVL_0; lvl < UFS_PM_LVL_MAX; lvl++) { + if ((ufs_pm_lvl_states[lvl].dev_state == dev_state) && + (ufs_pm_lvl_states[lvl].link_state == link_state)) + return lvl; + } + + /* if no match found, return the level 0 */ + return UFS_PM_LVL_0; +} + +static inline bool ufshcd_is_valid_pm_lvl(int lvl) +{ + if (lvl >= 0 && lvl < ARRAY_SIZE(ufs_pm_lvl_states)) + return true; + else + return false; +} + +static irqreturn_t ufshcd_intr(int irq, void *__hba); +static irqreturn_t ufshcd_tmc_handler(struct ufs_hba *hba); static void ufshcd_async_scan(void *data, async_cookie_t cookie); static int ufshcd_reset_and_restore(struct ufs_hba *hba); +static int ufshcd_eh_host_reset_handler(struct scsi_cmnd *cmd); static int ufshcd_clear_tm_cmd(struct ufs_hba *hba, int tag); static void ufshcd_hba_exit(struct ufs_hba *hba); static int ufshcd_probe_hba(struct ufs_hba *hba); -static int __ufshcd_setup_clocks(struct ufs_hba *hba, bool on, - bool skip_ref_clk); -static int ufshcd_setup_clocks(struct ufs_hba *hba, bool on); -static int ufshcd_uic_hibern8_exit(struct ufs_hba *hba); -static int ufshcd_uic_hibern8_enter(struct ufs_hba *hba); +static int ufshcd_enable_clocks(struct ufs_hba *hba); +static int ufshcd_disable_clocks(struct ufs_hba *hba, + bool is_gating_context); +static int ufshcd_disable_clocks_skip_ref_clk(struct ufs_hba *hba, + bool is_gating_context); +static void ufshcd_hold_all(struct ufs_hba *hba); +static void ufshcd_release_all(struct ufs_hba *hba); +static int ufshcd_set_vccq_rail_unused(struct ufs_hba *hba, bool unused); static inline void ufshcd_add_delay_before_dme_cmd(struct ufs_hba *hba); +static inline void ufshcd_save_tstamp_of_last_dme_cmd(struct ufs_hba *hba); static int ufshcd_host_reset_and_restore(struct ufs_hba *hba); -static irqreturn_t ufshcd_intr(int irq, void *__hba); -static int ufshcd_config_pwr_mode(struct ufs_hba *hba, - struct ufs_pa_layer_attr *desired_pwr_mode); -static int ufshcd_change_power_mode(struct ufs_hba *hba, - struct ufs_pa_layer_attr *pwr_mode); +static void ufshcd_resume_clkscaling(struct ufs_hba *hba); +static void ufshcd_suspend_clkscaling(struct ufs_hba *hba); +static void __ufshcd_suspend_clkscaling(struct ufs_hba *hba); +static void ufshcd_release_all(struct ufs_hba *hba); +static void ufshcd_hba_vreg_set_lpm(struct ufs_hba *hba); +static void ufshcd_hba_vreg_set_hpm(struct ufs_hba *hba); +static int ufshcd_devfreq_target(struct device *dev, + unsigned long *freq, u32 flags); +static int ufshcd_devfreq_get_dev_status(struct device *dev, + struct devfreq_dev_status *stat); + +#if IS_ENABLED(CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND) +static struct devfreq_simple_ondemand_data ufshcd_ondemand_data = { + .upthreshold = 35, + .downdifferential = 30, + .simple_scaling = 1, +}; + +static void *gov_data = &ufshcd_ondemand_data; +#else +static void *gov_data; +#endif + +static struct devfreq_dev_profile ufs_devfreq_profile = { + .polling_ms = 40, + .target = ufshcd_devfreq_target, + .get_dev_status = ufshcd_devfreq_get_dev_status, +}; -static inline int ufshcd_enable_irq(struct ufs_hba *hba) +static inline bool ufshcd_valid_tag(struct ufs_hba *hba, int tag) { - int ret = 0; + return tag >= 0 && tag < hba->nutrs; +} +static inline void ufshcd_enable_irq(struct ufs_hba *hba) +{ if (!hba->is_irq_enabled) { - ret = request_irq(hba->irq, ufshcd_intr, IRQF_SHARED, UFSHCD, - hba); - if (ret) - dev_err(hba->dev, "%s: request_irq failed, ret=%d\n", - __func__, ret); + enable_irq(hba->irq); hba->is_irq_enabled = true; } - - return ret; } static inline void ufshcd_disable_irq(struct ufs_hba *hba) { if (hba->is_irq_enabled) { - free_irq(hba->irq, hba); + disable_irq(hba->irq); hba->is_irq_enabled = false; } } +void ufshcd_scsi_unblock_requests(struct ufs_hba *hba) +{ + unsigned long flags; + bool unblock = false; + + spin_lock_irqsave(hba->host->host_lock, flags); + hba->scsi_block_reqs_cnt--; + unblock = !hba->scsi_block_reqs_cnt; + spin_unlock_irqrestore(hba->host->host_lock, flags); + if (unblock) + scsi_unblock_requests(hba->host); +} +EXPORT_SYMBOL(ufshcd_scsi_unblock_requests); + +static inline void __ufshcd_scsi_block_requests(struct ufs_hba *hba) +{ + if (!hba->scsi_block_reqs_cnt++) + scsi_block_requests(hba->host); +} + +void ufshcd_scsi_block_requests(struct ufs_hba *hba) +{ + unsigned long flags; + + spin_lock_irqsave(hba->host->host_lock, flags); + __ufshcd_scsi_block_requests(hba); + spin_unlock_irqrestore(hba->host->host_lock, flags); +} +EXPORT_SYMBOL(ufshcd_scsi_block_requests); + +static int ufshcd_device_reset_ctrl(struct ufs_hba *hba, bool ctrl) +{ + int ret = 0; + + if (!hba->pctrl) + return 0; + + /* Assert reset if ctrl == true */ + if (ctrl) + ret = pinctrl_select_state(hba->pctrl, + pinctrl_lookup_state(hba->pctrl, "dev-reset-assert")); + else + ret = pinctrl_select_state(hba->pctrl, + pinctrl_lookup_state(hba->pctrl, "dev-reset-deassert")); + + if (ret < 0) + dev_err(hba->dev, "%s: %s failed with err %d\n", + __func__, ctrl ? "Assert" : "Deassert", ret); + + return ret; +} + +static inline int ufshcd_assert_device_reset(struct ufs_hba *hba) +{ + return ufshcd_device_reset_ctrl(hba, true); +} + +static inline int ufshcd_deassert_device_reset(struct ufs_hba *hba) +{ + return ufshcd_device_reset_ctrl(hba, false); +} + +static int ufshcd_reset_device(struct ufs_hba *hba) +{ + int ret; + + /* reset the connected UFS device */ + ret = ufshcd_assert_device_reset(hba); + if (ret) + goto out; + /* + * The reset signal is active low. + * The UFS device shall detect more than or equal to 1us of positive + * or negative RST_n pulse width. + * To be on safe side, keep the reset low for atleast 10us. + */ + usleep_range(10, 15); + + ret = ufshcd_deassert_device_reset(hba); + if (ret) + goto out; + /* same as assert, wait for atleast 10us after deassert */ + usleep_range(10, 15); +out: + return ret; +} + +/* replace non-printable or non-ASCII characters with spaces */ +static inline void ufshcd_remove_non_printable(char *val) +{ + if (!val || !*val) + return; + + if (*val < 0x20 || *val > 0x7e) + *val = ' '; +} + +#define UFSHCD_MAX_CMD_LOGGING 200 + +#ifdef CONFIG_TRACEPOINTS +static inline void ufshcd_add_command_trace(struct ufs_hba *hba, + struct ufshcd_cmd_log_entry *entry, u8 opcode) +{ + if (trace_ufshcd_command_enabled()) { + u32 intr = ufshcd_readl(hba, REG_INTERRUPT_STATUS); + + trace_ufshcd_command(dev_name(hba->dev), entry->str, entry->tag, + entry->doorbell, entry->transfer_len, intr, + entry->lba, opcode); + } +} +#else +static inline void ufshcd_add_command_trace(struct ufs_hba *hba, + struct ufshcd_cmd_log_entry *entry, u8 opcode) +{ +} +#endif + +#ifdef CONFIG_SCSI_UFSHCD_CMD_LOGGING +static void ufshcd_cmd_log_init(struct ufs_hba *hba) +{ + /* Allocate log entries */ + if (!hba->cmd_log.entries) { + hba->cmd_log.entries = kzalloc(UFSHCD_MAX_CMD_LOGGING * + sizeof(struct ufshcd_cmd_log_entry), GFP_KERNEL); + if (!hba->cmd_log.entries) + return; + dev_dbg(hba->dev, "%s: cmd_log.entries initialized\n", + __func__); + } +} + +static void __ufshcd_cmd_log(struct ufs_hba *hba, char *str, char *cmd_type, + unsigned int tag, u8 cmd_id, u8 idn, u8 lun, + sector_t lba, int transfer_len, u8 opcode) +{ + struct ufshcd_cmd_log_entry *entry; + + if (!hba->cmd_log.entries) + return; + + entry = &hba->cmd_log.entries[hba->cmd_log.pos]; + entry->lun = lun; + entry->str = str; + entry->cmd_type = cmd_type; + entry->cmd_id = cmd_id; + entry->lba = lba; + entry->transfer_len = transfer_len; + entry->idn = idn; + entry->doorbell = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL); + entry->tag = tag; + entry->tstamp = ktime_get(); + entry->outstanding_reqs = hba->outstanding_reqs; + entry->seq_num = hba->cmd_log.seq_num; + hba->cmd_log.seq_num++; + hba->cmd_log.pos = + (hba->cmd_log.pos + 1) % UFSHCD_MAX_CMD_LOGGING; + + ufshcd_add_command_trace(hba, entry, opcode); +} + +static void ufshcd_cmd_log(struct ufs_hba *hba, char *str, char *cmd_type, + unsigned int tag, u8 cmd_id, u8 idn) +{ + __ufshcd_cmd_log(hba, str, cmd_type, tag, cmd_id, idn, + 0xff, (sector_t)-1, -1, -1); +} + +static void ufshcd_dme_cmd_log(struct ufs_hba *hba, char *str, u8 cmd_id) +{ + ufshcd_cmd_log(hba, str, "dme", 0xff, cmd_id, 0xff); +} + +static void ufshcd_print_cmd_log(struct ufs_hba *hba) +{ + int i; + int pos; + struct ufshcd_cmd_log_entry *p; + + if (!hba->cmd_log.entries) + return; + + pos = hba->cmd_log.pos; + for (i = 0; i < UFSHCD_MAX_CMD_LOGGING; i++) { + p = &hba->cmd_log.entries[pos]; + pos = (pos + 1) % UFSHCD_MAX_CMD_LOGGING; + + if (ktime_to_us(p->tstamp)) { + pr_err("%s: %s: seq_no=%u lun=0x%x cmd_id=0x%02x lba=0x%llx txfer_len=%d tag=%u, doorbell=0x%x outstanding=0x%x idn=%d time=%lld us\n", + p->cmd_type, p->str, p->seq_num, + p->lun, p->cmd_id, (unsigned long long)p->lba, + p->transfer_len, p->tag, p->doorbell, + p->outstanding_reqs, p->idn, + ktime_to_us(p->tstamp)); + usleep_range(1000, 1100); + } + } +} +#else +static void ufshcd_cmd_log_init(struct ufs_hba *hba) +{ +} + +static void __ufshcd_cmd_log(struct ufs_hba *hba, char *str, char *cmd_type, + unsigned int tag, u8 cmd_id, u8 idn, u8 lun, + sector_t lba, int transfer_len, u8 opcode) +{ + struct ufshcd_cmd_log_entry entry; + + entry.str = str; + entry.lba = lba; + entry.transfer_len = transfer_len; + entry.doorbell = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL); + entry.tag = tag; + + ufshcd_add_command_trace(hba, &entry, opcode); +} + +static void ufshcd_dme_cmd_log(struct ufs_hba *hba, char *str, u8 cmd_id) +{ +} + +static void ufshcd_print_cmd_log(struct ufs_hba *hba) +{ +} +#endif + +#ifdef CONFIG_TRACEPOINTS +static inline void ufshcd_cond_add_cmd_trace(struct ufs_hba *hba, + unsigned int tag, const char *str) +{ + struct ufshcd_lrb *lrbp; + char *cmd_type = NULL; + u8 opcode = 0; + u8 cmd_id = 0, idn = 0; + sector_t lba = -1; + int transfer_len = -1; + + lrbp = &hba->lrb[tag]; + + if (lrbp->cmd) { /* data phase exists */ + opcode = (u8)(*lrbp->cmd->cmnd); + if ((opcode == READ_10) || (opcode == WRITE_10)) { + /* + * Currently we only fully trace read(10) and write(10) + * commands + */ + if (lrbp->cmd->request && lrbp->cmd->request->bio) + lba = + lrbp->cmd->request->bio->bi_iter.bi_sector; + transfer_len = be32_to_cpu( + lrbp->ucd_req_ptr->sc.exp_data_transfer_len); + } + } + + if (lrbp->cmd && (lrbp->command_type == UTP_CMD_TYPE_SCSI)) { + cmd_type = "scsi"; + cmd_id = (u8)(*lrbp->cmd->cmnd); + } else if (lrbp->command_type == UTP_CMD_TYPE_DEV_MANAGE) { + if (hba->dev_cmd.type == DEV_CMD_TYPE_NOP) { + cmd_type = "nop"; + cmd_id = 0; + } else if (hba->dev_cmd.type == DEV_CMD_TYPE_QUERY) { + cmd_type = "query"; + cmd_id = hba->dev_cmd.query.request.upiu_req.opcode; + idn = hba->dev_cmd.query.request.upiu_req.idn; + } + } + + __ufshcd_cmd_log(hba, (char *) str, cmd_type, tag, cmd_id, idn, + lrbp->lun, lba, transfer_len, opcode); +} +#else +static inline void ufshcd_cond_add_cmd_trace(struct ufs_hba *hba, + unsigned int tag, const char *str) +{ +} +#endif + +static void ufshcd_print_clk_freqs(struct ufs_hba *hba) +{ + struct ufs_clk_info *clki; + struct list_head *head = &hba->clk_list_head; + + if (!(hba->ufshcd_dbg_print & UFSHCD_DBG_PRINT_CLK_FREQ_EN)) + return; + + if (!head || list_empty(head)) + return; + + list_for_each_entry(clki, head, list) { + if (!IS_ERR_OR_NULL(clki->clk) && clki->min_freq && + clki->max_freq) + dev_err(hba->dev, "clk: %s, rate: %u\n", + clki->name, clki->curr_freq); + } +} + +static void ufshcd_print_uic_err_hist(struct ufs_hba *hba, + struct ufs_uic_err_reg_hist *err_hist, char *err_name) +{ + int i; + + if (!(hba->ufshcd_dbg_print & UFSHCD_DBG_PRINT_UIC_ERR_HIST_EN)) + return; + + for (i = 0; i < UIC_ERR_REG_HIST_LENGTH; i++) { + int p = (i + err_hist->pos - 1) % UIC_ERR_REG_HIST_LENGTH; + + if (err_hist->reg[p] == 0) + continue; + dev_err(hba->dev, "%s[%d] = 0x%x at %lld us", err_name, i, + err_hist->reg[p], ktime_to_us(err_hist->tstamp[p])); + } +} + +static inline void __ufshcd_print_host_regs(struct ufs_hba *hba, bool no_sleep) +{ + if (!(hba->ufshcd_dbg_print & UFSHCD_DBG_PRINT_HOST_REGS_EN)) + return; + + /* + * hex_dump reads its data without the readl macro. This might + * cause inconsistency issues on some platform, as the printed + * values may be from cache and not the most recent value. + * To know whether you are looking at an un-cached version verify + * that IORESOURCE_MEM flag is on when xxx_get_resource() is invoked + * during platform/pci probe function. + */ + ufshcd_hex_dump("host regs: ", hba->mmio_base, UFSHCI_REG_SPACE_SIZE); + dev_err(hba->dev, "hba->ufs_version = 0x%x, hba->capabilities = 0x%x", + hba->ufs_version, hba->capabilities); + dev_err(hba->dev, + "hba->outstanding_reqs = 0x%x, hba->outstanding_tasks = 0x%x", + (u32)hba->outstanding_reqs, (u32)hba->outstanding_tasks); + dev_err(hba->dev, + "last_hibern8_exit_tstamp at %lld us, hibern8_exit_cnt = %d", + ktime_to_us(hba->ufs_stats.last_hibern8_exit_tstamp), + hba->ufs_stats.hibern8_exit_cnt); + + ufshcd_print_uic_err_hist(hba, &hba->ufs_stats.pa_err, "pa_err"); + ufshcd_print_uic_err_hist(hba, &hba->ufs_stats.dl_err, "dl_err"); + ufshcd_print_uic_err_hist(hba, &hba->ufs_stats.nl_err, "nl_err"); + ufshcd_print_uic_err_hist(hba, &hba->ufs_stats.tl_err, "tl_err"); + ufshcd_print_uic_err_hist(hba, &hba->ufs_stats.dme_err, "dme_err"); + + ufshcd_print_clk_freqs(hba); + + ufshcd_vops_dbg_register_dump(hba, no_sleep); +} + +static void ufshcd_print_host_regs(struct ufs_hba *hba) +{ + __ufshcd_print_host_regs(hba, false); +} + +static +void ufshcd_print_trs(struct ufs_hba *hba, unsigned long bitmap, bool pr_prdt) +{ + struct ufshcd_lrb *lrbp; + int prdt_length; + int tag; + + if (!(hba->ufshcd_dbg_print & UFSHCD_DBG_PRINT_TRS_EN)) + return; + + for_each_set_bit(tag, &bitmap, hba->nutrs) { + lrbp = &hba->lrb[tag]; + + dev_err(hba->dev, "UPIU[%d] - issue time %lld us", + tag, ktime_to_us(lrbp->issue_time_stamp)); + dev_err(hba->dev, + "UPIU[%d] - Transfer Request Descriptor phys@0x%llx", + tag, (u64)lrbp->utrd_dma_addr); + ufshcd_hex_dump("UPIU TRD: ", lrbp->utr_descriptor_ptr, + sizeof(struct utp_transfer_req_desc)); + dev_err(hba->dev, "UPIU[%d] - Request UPIU phys@0x%llx", tag, + (u64)lrbp->ucd_req_dma_addr); + ufshcd_hex_dump("UPIU REQ: ", lrbp->ucd_req_ptr, + sizeof(struct utp_upiu_req)); + dev_err(hba->dev, "UPIU[%d] - Response UPIU phys@0x%llx", tag, + (u64)lrbp->ucd_rsp_dma_addr); + ufshcd_hex_dump("UPIU RSP: ", lrbp->ucd_rsp_ptr, + sizeof(struct utp_upiu_rsp)); + prdt_length = + le16_to_cpu(lrbp->utr_descriptor_ptr->prd_table_length); + dev_err(hba->dev, "UPIU[%d] - PRDT - %d entries phys@0x%llx", + tag, prdt_length, (u64)lrbp->ucd_prdt_dma_addr); + if (pr_prdt) + ufshcd_hex_dump("UPIU PRDT: ", lrbp->ucd_prdt_ptr, + sizeof(struct ufshcd_sg_entry) * prdt_length); + } +} + +static void ufshcd_print_tmrs(struct ufs_hba *hba, unsigned long bitmap) +{ + struct utp_task_req_desc *tmrdp; + int tag; + + if (!(hba->ufshcd_dbg_print & UFSHCD_DBG_PRINT_TMRS_EN)) + return; + + for_each_set_bit(tag, &bitmap, hba->nutmrs) { + tmrdp = &hba->utmrdl_base_addr[tag]; + dev_err(hba->dev, "TM[%d] - Task Management Header", tag); + ufshcd_hex_dump("TM TRD: ", &tmrdp->header, + sizeof(struct request_desc_header)); + dev_err(hba->dev, "TM[%d] - Task Management Request UPIU", + tag); + ufshcd_hex_dump("TM REQ: ", tmrdp->task_req_upiu, + sizeof(struct utp_upiu_req)); + dev_err(hba->dev, "TM[%d] - Task Management Response UPIU", + tag); + ufshcd_hex_dump("TM RSP: ", tmrdp->task_rsp_upiu, + sizeof(struct utp_task_req_desc)); + } +} + +static void ufshcd_print_fsm_state(struct ufs_hba *hba) +{ + int err = 0, tx_fsm_val = 0, rx_fsm_val = 0; + + err = ufshcd_dme_get(hba, + UIC_ARG_MIB_SEL(MPHY_TX_FSM_STATE, + UIC_ARG_MPHY_TX_GEN_SEL_INDEX(0)), + &tx_fsm_val); + dev_err(hba->dev, "%s: TX_FSM_STATE = %u, err = %d\n", __func__, + tx_fsm_val, err); + err = ufshcd_dme_get(hba, + UIC_ARG_MIB_SEL(MPHY_RX_FSM_STATE, + UIC_ARG_MPHY_RX_GEN_SEL_INDEX(0)), + &rx_fsm_val); + dev_err(hba->dev, "%s: RX_FSM_STATE = %u, err = %d\n", __func__, + rx_fsm_val, err); +} + +static void ufshcd_print_host_state(struct ufs_hba *hba) +{ + if (!(hba->ufshcd_dbg_print & UFSHCD_DBG_PRINT_HOST_STATE_EN)) + return; + + dev_err(hba->dev, "UFS Host state=%d\n", hba->ufshcd_state); + dev_err(hba->dev, "lrb in use=0x%lx, outstanding reqs=0x%lx tasks=0x%lx\n", + hba->lrb_in_use, hba->outstanding_tasks, hba->outstanding_reqs); + dev_err(hba->dev, "saved_err=0x%x, saved_uic_err=0x%x, saved_ce_err=0x%x\n", + hba->saved_err, hba->saved_uic_err, hba->saved_ce_err); + dev_err(hba->dev, "Device power mode=%d, UIC link state=%d\n", + hba->curr_dev_pwr_mode, hba->uic_link_state); + dev_err(hba->dev, "PM in progress=%d, sys. suspended=%d\n", + hba->pm_op_in_progress, hba->is_sys_suspended); + dev_err(hba->dev, "Auto BKOPS=%d, Host self-block=%d\n", + hba->auto_bkops_enabled, hba->host->host_self_blocked); + dev_err(hba->dev, "Clk gate=%d, hibern8 on idle=%d\n", + hba->clk_gating.state, hba->hibern8_on_idle.state); + dev_err(hba->dev, "error handling flags=0x%x, req. abort count=%d\n", + hba->eh_flags, hba->req_abort_count); + dev_err(hba->dev, "Host capabilities=0x%x, caps=0x%x\n", + hba->capabilities, hba->caps); + dev_err(hba->dev, "quirks=0x%x, dev. quirks=0x%x\n", hba->quirks, + hba->dev_quirks); +} + +/** + * ufshcd_print_pwr_info - print power params as saved in hba + * power info + * @hba: per-adapter instance + */ +static void ufshcd_print_pwr_info(struct ufs_hba *hba) +{ + char *names[] = { + "INVALID MODE", + "FAST MODE", + "SLOW_MODE", + "INVALID MODE", + "FASTAUTO_MODE", + "SLOWAUTO_MODE", + "INVALID MODE", + }; + + if (!(hba->ufshcd_dbg_print & UFSHCD_DBG_PRINT_PWR_EN)) + return; + + dev_err(hba->dev, "%s:[RX, TX]: gear=[%d, %d], lane[%d, %d], pwr[%s, %s], rate = %d\n", + __func__, + hba->pwr_info.gear_rx, hba->pwr_info.gear_tx, + hba->pwr_info.lane_rx, hba->pwr_info.lane_tx, + names[hba->pwr_info.pwr_rx], + names[hba->pwr_info.pwr_tx], + hba->pwr_info.hs_rate); +} + /* * ufshcd_wait_for_register - wait for register value to change * @hba - per-adapter interface @@ -223,11 +923,12 @@ * @val - wait condition * @interval_us - polling interval in microsecs * @timeout_ms - timeout in millisecs - * + * @can_sleep - perform sleep or just spin * Returns -ETIMEDOUT on error, zero on success */ -static int ufshcd_wait_for_register(struct ufs_hba *hba, u32 reg, u32 mask, - u32 val, unsigned long interval_us, unsigned long timeout_ms) +int ufshcd_wait_for_register(struct ufs_hba *hba, u32 reg, u32 mask, + u32 val, unsigned long interval_us, + unsigned long timeout_ms, bool can_sleep) { int err = 0; unsigned long timeout = jiffies + msecs_to_jiffies(timeout_ms); @@ -236,9 +937,10 @@ val = val & mask; while ((ufshcd_readl(hba, reg) & mask) != val) { - /* wakeup within 50us of expiry */ + if (can_sleep) usleep_range(interval_us, interval_us + 50); - + else + udelay(interval_us); if (time_after(jiffies, timeout)) { if ((ufshcd_readl(hba, reg) & mask) != val) err = -ETIMEDOUT; @@ -257,10 +959,27 @@ */ static inline u32 ufshcd_get_intr_mask(struct ufs_hba *hba) { - if (hba->ufs_version == UFSHCI_VERSION_10) - return INTERRUPT_MASK_ALL_VER_10; - else - return INTERRUPT_MASK_ALL_VER_11; + u32 intr_mask = 0; + + switch (hba->ufs_version) { + case UFSHCI_VERSION_10: + intr_mask = INTERRUPT_MASK_ALL_VER_10; + break; + /* allow fall through */ + case UFSHCI_VERSION_11: + case UFSHCI_VERSION_20: + intr_mask = INTERRUPT_MASK_ALL_VER_11; + break; + /* allow fall through */ + case UFSHCI_VERSION_21: + default: + intr_mask = INTERRUPT_MASK_ALL_VER_21; + } + + if (!ufshcd_is_crypto_supported(hba)) + intr_mask &= ~CRYPTO_ENGINE_FATAL_ERROR; + + return intr_mask; } /** @@ -360,6 +1079,16 @@ } /** + * ufshcd_outstanding_req_clear - Clear a bit in outstanding request field + * @hba: per adapter instance + * @tag: position of the bit to be cleared + */ +static inline void ufshcd_outstanding_req_clear(struct ufs_hba *hba, int tag) +{ + __clear_bit(tag, &hba->outstanding_reqs); +} + +/** * ufshcd_get_lists_status - Check UCRDY, UTRLRDY and UTMRLRDY * @reg: Register value of host controller status * @@ -374,11 +1103,9 @@ * 1 UTRLRDY * 2 UTMRLRDY * 3 UCRDY - * 4 HEI - * 5 DEI - * 6-7 reserved + * 4-7 reserved */ - return (((reg) & (0xFF)) >> 1) ^ (0x07); + return ((reg & 0xFF) >> 1) ^ 0x07; } /** @@ -514,7 +1241,11 @@ */ static inline void ufshcd_hba_start(struct ufs_hba *hba) { - ufshcd_writel(hba, CONTROLLER_ENABLE, REG_CONTROLLER_ENABLE); + u32 val = CONTROLLER_ENABLE; + + if (ufshcd_is_crypto_supported(hba)) + val |= CRYPTO_GENERAL_ENABLE; + ufshcd_writel(hba, val, REG_CONTROLLER_ENABLE); } /** @@ -528,6 +1259,153 @@ return (ufshcd_readl(hba, REG_CONTROLLER_ENABLE) & 0x1) ? 0 : 1; } +static const char *ufschd_uic_link_state_to_string( + enum uic_link_state state) +{ + switch (state) { + case UIC_LINK_OFF_STATE: return "OFF"; + case UIC_LINK_ACTIVE_STATE: return "ACTIVE"; + case UIC_LINK_HIBERN8_STATE: return "HIBERN8"; + default: return "UNKNOWN"; + } +} + +static const char *ufschd_ufs_dev_pwr_mode_to_string( + enum ufs_dev_pwr_mode state) +{ + switch (state) { + case UFS_ACTIVE_PWR_MODE: return "ACTIVE"; + case UFS_SLEEP_PWR_MODE: return "SLEEP"; + case UFS_POWERDOWN_PWR_MODE: return "POWERDOWN"; + default: return "UNKNOWN"; + } +} + +u32 ufshcd_get_local_unipro_ver(struct ufs_hba *hba) +{ + /* HCI version 1.0 and 1.1 supports UniPro 1.41 */ + if ((hba->ufs_version == UFSHCI_VERSION_10) || + (hba->ufs_version == UFSHCI_VERSION_11)) + return UFS_UNIPRO_VER_1_41; + else + return UFS_UNIPRO_VER_1_6; +} +EXPORT_SYMBOL(ufshcd_get_local_unipro_ver); + +static bool ufshcd_is_unipro_pa_params_tuning_req(struct ufs_hba *hba) +{ + /* + * If both host and device support UniPro ver1.6 or later, PA layer + * parameters tuning happens during link startup itself. + * + * We can manually tune PA layer parameters if either host or device + * doesn't support UniPro ver 1.6 or later. But to keep manual tuning + * logic simple, we will only do manual tuning if local unipro version + * doesn't support ver1.6 or later. + */ + if (ufshcd_get_local_unipro_ver(hba) < UFS_UNIPRO_VER_1_6) + return true; + else + return false; +} + +/** + * ufshcd_set_clk_freq - set UFS controller clock frequencies + * @hba: per adapter instance + * @scale_up: If True, set max possible frequency othewise set low frequency + * + * Returns 0 if successful + * Returns < 0 for any other errors + */ +static int ufshcd_set_clk_freq(struct ufs_hba *hba, bool scale_up) +{ + int ret = 0; + struct ufs_clk_info *clki; + struct list_head *head = &hba->clk_list_head; + + if (!head || list_empty(head)) + goto out; + + list_for_each_entry(clki, head, list) { + if (!IS_ERR_OR_NULL(clki->clk)) { + if (scale_up && clki->max_freq) { + if (clki->curr_freq == clki->max_freq) + continue; + + ret = clk_set_rate(clki->clk, clki->max_freq); + if (ret) { + dev_err(hba->dev, "%s: %s clk set rate(%dHz) failed, %d\n", + __func__, clki->name, + clki->max_freq, ret); + break; + } + trace_ufshcd_clk_scaling(dev_name(hba->dev), + "scaled up", clki->name, + clki->curr_freq, + clki->max_freq); + clki->curr_freq = clki->max_freq; + + } else if (!scale_up && clki->min_freq) { + if (clki->curr_freq == clki->min_freq) + continue; + + ret = clk_set_rate(clki->clk, clki->min_freq); + if (ret) { + dev_err(hba->dev, "%s: %s clk set rate(%dHz) failed, %d\n", + __func__, clki->name, + clki->min_freq, ret); + break; + } + trace_ufshcd_clk_scaling(dev_name(hba->dev), + "scaled down", clki->name, + clki->curr_freq, + clki->min_freq); + clki->curr_freq = clki->min_freq; + } + } + dev_dbg(hba->dev, "%s: clk: %s, rate: %lu\n", __func__, + clki->name, clk_get_rate(clki->clk)); + } + +out: + return ret; +} + +/** + * ufshcd_scale_clks - scale up or scale down UFS controller clocks + * @hba: per adapter instance + * @scale_up: True if scaling up and false if scaling down + * + * Returns 0 if successful + * Returns < 0 for any other errors + */ +static int ufshcd_scale_clks(struct ufs_hba *hba, bool scale_up) +{ + int ret = 0; + + ret = ufshcd_vops_clk_scale_notify(hba, scale_up, PRE_CHANGE); + if (ret) + return ret; + + ret = ufshcd_set_clk_freq(hba, scale_up); + if (ret) + return ret; + + ret = ufshcd_vops_clk_scale_notify(hba, scale_up, POST_CHANGE); + if (ret) { + ufshcd_set_clk_freq(hba, !scale_up); + return ret; + } + + return ret; +} + +static inline void ufshcd_cancel_gate_work(struct ufs_hba *hba) +{ + hrtimer_cancel(&hba->clk_gating.gate_hrtimer); + cancel_work_sync(&hba->clk_gating.gate_work); +} + static void ufshcd_ungate_work(struct work_struct *work) { int ret; @@ -535,7 +1413,7 @@ struct ufs_hba *hba = container_of(work, struct ufs_hba, clk_gating.ungate_work); - cancel_delayed_work_sync(&hba->clk_gating.gate_work); + ufshcd_cancel_gate_work(hba); spin_lock_irqsave(hba->host->host_lock, flags); if (hba->clk_gating.state == CLKS_ON) { @@ -544,7 +1422,8 @@ } spin_unlock_irqrestore(hba->host->host_lock, flags); - ufshcd_setup_clocks(hba, true); + ufshcd_hba_vreg_set_hpm(hba); + ufshcd_enable_clocks(hba); /* Exit from hibern8 */ if (ufshcd_can_hibern8_during_gating(hba)) { @@ -561,9 +1440,7 @@ hba->clk_gating.is_suspended = false; } unblock_reqs: - if (ufshcd_is_clkscaling_enabled(hba)) - devfreq_resume_device(hba->devfreq); - scsi_unblock_requests(hba->host); + ufshcd_scsi_unblock_requests(hba); } /** @@ -582,24 +1459,53 @@ spin_lock_irqsave(hba->host->host_lock, flags); hba->clk_gating.active_reqs++; + if (ufshcd_eh_in_progress(hba)) { + spin_unlock_irqrestore(hba->host->host_lock, flags); + return 0; + } + start: switch (hba->clk_gating.state) { case CLKS_ON: + /* + * Wait for the ungate work to complete if in progress. + * Though the clocks may be in ON state, the link could + * still be in hibner8 state if hibern8 is allowed + * during clock gating. + * Make sure we exit hibern8 state also in addition to + * clocks being ON. + */ + if (ufshcd_can_hibern8_during_gating(hba) && + ufshcd_is_link_hibern8(hba)) { + spin_unlock_irqrestore(hba->host->host_lock, flags); + flush_work(&hba->clk_gating.ungate_work); + spin_lock_irqsave(hba->host->host_lock, flags); + goto start; + } break; case REQ_CLKS_OFF: - if (cancel_delayed_work(&hba->clk_gating.gate_work)) { + /* + * If the timer was active but the callback was not running + * we have nothing to do, just change state and return. + */ + if (hrtimer_try_to_cancel(&hba->clk_gating.gate_hrtimer) == 1) { hba->clk_gating.state = CLKS_ON; + trace_ufshcd_clk_gating(dev_name(hba->dev), + hba->clk_gating.state); break; } /* - * If we here, it means gating work is either done or + * If we are here, it means gating work is either done or * currently running. Hence, fall through to cancel gating * work and to enable clocks. */ case CLKS_OFF: - scsi_block_requests(hba->host); + __ufshcd_scsi_block_requests(hba); hba->clk_gating.state = REQ_CLKS_ON; - schedule_work(&hba->clk_gating.ungate_work); + trace_ufshcd_clk_gating(dev_name(hba->dev), + hba->clk_gating.state); + queue_work(hba->clk_gating.clk_gating_workq, + &hba->clk_gating.ungate_work); /* * fall through to check if we should wait for this * work to be done or not. @@ -623,6 +1529,7 @@ } spin_unlock_irqrestore(hba->host->host_lock, flags); out: + hba->ufs_stats.clk_hold.ts = ktime_get(); return rc; } EXPORT_SYMBOL_GPL(ufshcd_hold); @@ -630,12 +1537,21 @@ static void ufshcd_gate_work(struct work_struct *work) { struct ufs_hba *hba = container_of(work, struct ufs_hba, - clk_gating.gate_work.work); + clk_gating.gate_work); unsigned long flags; spin_lock_irqsave(hba->host->host_lock, flags); - if (hba->clk_gating.is_suspended) { + /* + * In case you are here to cancel this work the gating state + * would be marked as REQ_CLKS_ON. In this case save time by + * skipping the gating work and exit after changing the clock + * state to CLKS_ON. + */ + if (hba->clk_gating.is_suspended || + (hba->clk_gating.state != REQ_CLKS_OFF)) { hba->clk_gating.state = CLKS_ON; + trace_ufshcd_clk_gating(dev_name(hba->dev), + hba->clk_gating.state); goto rel_lock; } @@ -647,25 +1563,38 @@ spin_unlock_irqrestore(hba->host->host_lock, flags); + if (ufshcd_is_hibern8_on_idle_allowed(hba) && + hba->hibern8_on_idle.is_enabled) + /* + * Hibern8 enter work (on Idle) needs clocks to be ON hence + * make sure that it is flushed before turning off the clocks. + */ + flush_delayed_work(&hba->hibern8_on_idle.enter_work); + /* put the link into hibern8 mode before turning off clocks */ if (ufshcd_can_hibern8_during_gating(hba)) { if (ufshcd_uic_hibern8_enter(hba)) { hba->clk_gating.state = CLKS_ON; + trace_ufshcd_clk_gating(dev_name(hba->dev), + hba->clk_gating.state); goto out; } ufshcd_set_link_hibern8(hba); } - if (ufshcd_is_clkscaling_enabled(hba)) { - devfreq_suspend_device(hba->devfreq); - hba->clk_scaling.window_start_t = 0; - } - - if (!ufshcd_is_link_active(hba)) - ufshcd_setup_clocks(hba, false); + /* + * If auto hibern8 is supported then the link will already + * be in hibern8 state and the ref clock can be gated. + */ + if ((ufshcd_is_auto_hibern8_supported(hba) || + !ufshcd_is_link_active(hba)) && !hba->no_ref_clk_gating) + ufshcd_disable_clocks(hba, true); else /* If link is active, device ref_clk can't be switched off */ - __ufshcd_setup_clocks(hba, false, true); + ufshcd_disable_clocks_skip_ref_clk(hba, true); + + /* Put the host controller in low power mode if possible */ + ufshcd_hba_vreg_set_lpm(hba); /* * In case you are here to cancel this work the gating state @@ -677,9 +1606,11 @@ * new requests arriving before the current cancel work is done. */ spin_lock_irqsave(hba->host->host_lock, flags); - if (hba->clk_gating.state == REQ_CLKS_OFF) + if (hba->clk_gating.state == REQ_CLKS_OFF) { hba->clk_gating.state = CLKS_OFF; - + trace_ufshcd_clk_gating(dev_name(hba->dev), + hba->clk_gating.state); + } rel_lock: spin_unlock_irqrestore(hba->host->host_lock, flags); out: @@ -687,7 +1618,7 @@ } /* host lock must be held before calling this variant */ -static void __ufshcd_release(struct ufs_hba *hba) +static void __ufshcd_release(struct ufs_hba *hba, bool no_sched) { if (!ufshcd_is_clkgating_allowed(hba)) return; @@ -697,20 +1628,25 @@ if (hba->clk_gating.active_reqs || hba->clk_gating.is_suspended || hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL || hba->lrb_in_use || hba->outstanding_tasks - || hba->active_uic_cmd || hba->uic_async_done) + || hba->active_uic_cmd || hba->uic_async_done + || ufshcd_eh_in_progress(hba) || no_sched) return; hba->clk_gating.state = REQ_CLKS_OFF; - schedule_delayed_work(&hba->clk_gating.gate_work, - msecs_to_jiffies(hba->clk_gating.delay_ms)); + trace_ufshcd_clk_gating(dev_name(hba->dev), hba->clk_gating.state); + hba->ufs_stats.clk_rel.ts = ktime_get(); + + hrtimer_start(&hba->clk_gating.gate_hrtimer, + ms_to_ktime(hba->clk_gating.delay_ms), + HRTIMER_MODE_REL); } -void ufshcd_release(struct ufs_hba *hba) +void ufshcd_release(struct ufs_hba *hba, bool no_sched) { unsigned long flags; spin_lock_irqsave(hba->host->host_lock, flags); - __ufshcd_release(hba); + __ufshcd_release(hba, no_sched); spin_unlock_irqrestore(hba->host->host_lock, flags); } EXPORT_SYMBOL_GPL(ufshcd_release); @@ -738,15 +1674,177 @@ return count; } +static ssize_t ufshcd_clkgate_delay_pwr_save_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct ufs_hba *hba = dev_get_drvdata(dev); + + return snprintf(buf, PAGE_SIZE, "%lu\n", + hba->clk_gating.delay_ms_pwr_save); +} + +static ssize_t ufshcd_clkgate_delay_pwr_save_store(struct device *dev, + struct device_attribute *attr, const char *buf, size_t count) +{ + struct ufs_hba *hba = dev_get_drvdata(dev); + unsigned long flags, value; + + if (kstrtoul(buf, 0, &value)) + return -EINVAL; + + spin_lock_irqsave(hba->host->host_lock, flags); + + hba->clk_gating.delay_ms_pwr_save = value; + if (ufshcd_is_clkscaling_supported(hba) && + !hba->clk_scaling.is_scaled_up) + hba->clk_gating.delay_ms = hba->clk_gating.delay_ms_pwr_save; + + spin_unlock_irqrestore(hba->host->host_lock, flags); + return count; +} + +static ssize_t ufshcd_clkgate_delay_perf_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct ufs_hba *hba = dev_get_drvdata(dev); + + return snprintf(buf, PAGE_SIZE, "%lu\n", hba->clk_gating.delay_ms_perf); +} + +static ssize_t ufshcd_clkgate_delay_perf_store(struct device *dev, + struct device_attribute *attr, const char *buf, size_t count) +{ + struct ufs_hba *hba = dev_get_drvdata(dev); + unsigned long flags, value; + + if (kstrtoul(buf, 0, &value)) + return -EINVAL; + + spin_lock_irqsave(hba->host->host_lock, flags); + + hba->clk_gating.delay_ms_perf = value; + if (ufshcd_is_clkscaling_supported(hba) && + hba->clk_scaling.is_scaled_up) + hba->clk_gating.delay_ms = hba->clk_gating.delay_ms_perf; + + spin_unlock_irqrestore(hba->host->host_lock, flags); + return count; +} + +static ssize_t ufshcd_clkgate_enable_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct ufs_hba *hba = dev_get_drvdata(dev); + + return snprintf(buf, PAGE_SIZE, "%d\n", hba->clk_gating.is_enabled); +} + +static ssize_t ufshcd_clkgate_enable_store(struct device *dev, + struct device_attribute *attr, const char *buf, size_t count) +{ + struct ufs_hba *hba = dev_get_drvdata(dev); + unsigned long flags; + u32 value; + + if (kstrtou32(buf, 0, &value)) + return -EINVAL; + + value = !!value; + if (value == hba->clk_gating.is_enabled) + goto out; + + if (value) { + ufshcd_release(hba, false); + } else { + spin_lock_irqsave(hba->host->host_lock, flags); + hba->clk_gating.active_reqs++; + spin_unlock_irqrestore(hba->host->host_lock, flags); + } + + hba->clk_gating.is_enabled = value; +out: + return count; +} + +static enum hrtimer_restart ufshcd_clkgate_hrtimer_handler( + struct hrtimer *timer) +{ + struct ufs_hba *hba = container_of(timer, struct ufs_hba, + clk_gating.gate_hrtimer); + + queue_work(hba->clk_gating.clk_gating_workq, + &hba->clk_gating.gate_work); + + return HRTIMER_NORESTART; +} + static void ufshcd_init_clk_gating(struct ufs_hba *hba) { + struct ufs_clk_gating *gating = &hba->clk_gating; + char wq_name[sizeof("ufs_clk_gating_00")]; + + hba->clk_gating.state = CLKS_ON; + if (!ufshcd_is_clkgating_allowed(hba)) return; - hba->clk_gating.delay_ms = 150; - INIT_DELAYED_WORK(&hba->clk_gating.gate_work, ufshcd_gate_work); - INIT_WORK(&hba->clk_gating.ungate_work, ufshcd_ungate_work); + /* + * Disable hibern8 during clk gating if + * auto hibern8 is supported + */ + if (ufshcd_is_auto_hibern8_supported(hba)) + hba->caps &= ~UFSHCD_CAP_HIBERN8_WITH_CLK_GATING; + + INIT_WORK(&gating->gate_work, ufshcd_gate_work); + INIT_WORK(&gating->ungate_work, ufshcd_ungate_work); + /* + * Clock gating work must be executed only after auto hibern8 + * timeout has expired in the hardware or after aggressive + * hibern8 on idle software timeout. Using jiffy based low + * resolution delayed work is not reliable to guarantee this, + * hence use a high resolution timer to make sure we schedule + * the gate work precisely more than hibern8 timeout. + * + * Always make sure gating->delay_ms > hibern8_on_idle->delay_ms + */ + hrtimer_init(&gating->gate_hrtimer, CLOCK_MONOTONIC, HRTIMER_MODE_REL); + gating->gate_hrtimer.function = ufshcd_clkgate_hrtimer_handler; + + snprintf(wq_name, ARRAY_SIZE(wq_name), "ufs_clk_gating_%d", + hba->host->host_no); + hba->clk_gating.clk_gating_workq = + create_singlethread_workqueue(wq_name); + + gating->is_enabled = true; + + gating->delay_ms_pwr_save = UFSHCD_CLK_GATING_DELAY_MS_PWR_SAVE; + gating->delay_ms_perf = UFSHCD_CLK_GATING_DELAY_MS_PERF; + + /* start with performance mode */ + gating->delay_ms = gating->delay_ms_perf; + + if (!ufshcd_is_clkscaling_supported(hba)) + goto scaling_not_supported; + + gating->delay_pwr_save_attr.show = ufshcd_clkgate_delay_pwr_save_show; + gating->delay_pwr_save_attr.store = ufshcd_clkgate_delay_pwr_save_store; + sysfs_attr_init(&gating->delay_pwr_save_attr.attr); + gating->delay_pwr_save_attr.attr.name = "clkgate_delay_ms_pwr_save"; + gating->delay_pwr_save_attr.attr.mode = S_IRUGO | S_IWUSR; + if (device_create_file(hba->dev, &gating->delay_pwr_save_attr)) + dev_err(hba->dev, "Failed to create sysfs for clkgate_delay_ms_pwr_save\n"); + + gating->delay_perf_attr.show = ufshcd_clkgate_delay_perf_show; + gating->delay_perf_attr.store = ufshcd_clkgate_delay_perf_store; + sysfs_attr_init(&gating->delay_perf_attr.attr); + gating->delay_perf_attr.attr.name = "clkgate_delay_ms_perf"; + gating->delay_perf_attr.attr.mode = S_IRUGO | S_IWUSR; + if (device_create_file(hba->dev, &gating->delay_perf_attr)) + dev_err(hba->dev, "Failed to create sysfs for clkgate_delay_ms_perf\n"); + goto add_clkgate_enable; + +scaling_not_supported: hba->clk_gating.delay_attr.show = ufshcd_clkgate_delay_show; hba->clk_gating.delay_attr.store = ufshcd_clkgate_delay_store; sysfs_attr_init(&hba->clk_gating.delay_attr.attr); @@ -754,23 +1852,456 @@ hba->clk_gating.delay_attr.attr.mode = S_IRUGO | S_IWUSR; if (device_create_file(hba->dev, &hba->clk_gating.delay_attr)) dev_err(hba->dev, "Failed to create sysfs for clkgate_delay\n"); + +add_clkgate_enable: + gating->enable_attr.show = ufshcd_clkgate_enable_show; + gating->enable_attr.store = ufshcd_clkgate_enable_store; + sysfs_attr_init(&gating->enable_attr.attr); + gating->enable_attr.attr.name = "clkgate_enable"; + gating->enable_attr.attr.mode = S_IRUGO | S_IWUSR; + if (device_create_file(hba->dev, &gating->enable_attr)) + dev_err(hba->dev, "Failed to create sysfs for clkgate_enable\n"); } static void ufshcd_exit_clk_gating(struct ufs_hba *hba) { if (!ufshcd_is_clkgating_allowed(hba)) return; + if (ufshcd_is_clkscaling_supported(hba)) { + device_remove_file(hba->dev, + &hba->clk_gating.delay_pwr_save_attr); + device_remove_file(hba->dev, &hba->clk_gating.delay_perf_attr); + } else { device_remove_file(hba->dev, &hba->clk_gating.delay_attr); + } + device_remove_file(hba->dev, &hba->clk_gating.enable_attr); + ufshcd_cancel_gate_work(hba); cancel_work_sync(&hba->clk_gating.ungate_work); - cancel_delayed_work_sync(&hba->clk_gating.gate_work); + destroy_workqueue(hba->clk_gating.clk_gating_workq); +} + +static void ufshcd_set_auto_hibern8_timer(struct ufs_hba *hba, u32 delay) +{ + ufshcd_rmwl(hba, AUTO_HIBERN8_TIMER_SCALE_MASK | + AUTO_HIBERN8_IDLE_TIMER_MASK, + AUTO_HIBERN8_TIMER_SCALE_1_MS | delay, + REG_AUTO_HIBERN8_IDLE_TIMER); + /* Make sure the timer gets applied before further operations */ + mb(); +} + +/** + * ufshcd_hibern8_hold - Make sure that link is not in hibern8. + * + * @hba: per adapter instance + * @async: This indicates whether caller wants to exit hibern8 asynchronously. + * + * Exit from hibern8 mode and set the link as active. + * + * Return 0 on success, non-zero on failure. + */ +static int ufshcd_hibern8_hold(struct ufs_hba *hba, bool async) +{ + int rc = 0; + unsigned long flags; + + if (!ufshcd_is_hibern8_on_idle_allowed(hba)) + goto out; + + spin_lock_irqsave(hba->host->host_lock, flags); + hba->hibern8_on_idle.active_reqs++; + + if (ufshcd_eh_in_progress(hba)) { + spin_unlock_irqrestore(hba->host->host_lock, flags); + return 0; + } + +start: + switch (hba->hibern8_on_idle.state) { + case HIBERN8_EXITED: + break; + case REQ_HIBERN8_ENTER: + if (cancel_delayed_work(&hba->hibern8_on_idle.enter_work)) { + hba->hibern8_on_idle.state = HIBERN8_EXITED; + trace_ufshcd_hibern8_on_idle(dev_name(hba->dev), + hba->hibern8_on_idle.state); + break; + } + /* + * If we here, it means Hibern8 enter work is either done or + * currently running. Hence, fall through to cancel hibern8 + * work and exit hibern8. + */ + case HIBERN8_ENTERED: + __ufshcd_scsi_block_requests(hba); + hba->hibern8_on_idle.state = REQ_HIBERN8_EXIT; + trace_ufshcd_hibern8_on_idle(dev_name(hba->dev), + hba->hibern8_on_idle.state); + schedule_work(&hba->hibern8_on_idle.exit_work); + /* + * fall through to check if we should wait for this + * work to be done or not. + */ + case REQ_HIBERN8_EXIT: + if (async) { + rc = -EAGAIN; + hba->hibern8_on_idle.active_reqs--; + break; + } else { + spin_unlock_irqrestore(hba->host->host_lock, flags); + flush_work(&hba->hibern8_on_idle.exit_work); + /* Make sure state is HIBERN8_EXITED before returning */ + spin_lock_irqsave(hba->host->host_lock, flags); + goto start; + } + default: + dev_err(hba->dev, "%s: H8 is in invalid state %d\n", + __func__, hba->hibern8_on_idle.state); + break; + } + spin_unlock_irqrestore(hba->host->host_lock, flags); +out: + return rc; +} + +/* host lock must be held before calling this variant */ +static void __ufshcd_hibern8_release(struct ufs_hba *hba, bool no_sched) +{ + unsigned long delay_in_jiffies; + + if (!ufshcd_is_hibern8_on_idle_allowed(hba)) + return; + + hba->hibern8_on_idle.active_reqs--; + BUG_ON(hba->hibern8_on_idle.active_reqs < 0); + + if (hba->hibern8_on_idle.active_reqs + || hba->hibern8_on_idle.is_suspended + || hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL + || hba->lrb_in_use || hba->outstanding_tasks + || hba->active_uic_cmd || hba->uic_async_done + || ufshcd_eh_in_progress(hba) || no_sched) + return; + + hba->hibern8_on_idle.state = REQ_HIBERN8_ENTER; + trace_ufshcd_hibern8_on_idle(dev_name(hba->dev), + hba->hibern8_on_idle.state); + /* + * Scheduling the delayed work after 1 jiffies will make the work to + * get schedule any time from 0ms to 1000/HZ ms which is not desirable + * for hibern8 enter work as it may impact the performance if it gets + * scheduled almost immediately. Hence make sure that hibern8 enter + * work gets scheduled atleast after 2 jiffies (any time between + * 1000/HZ ms to 2000/HZ ms). + */ + delay_in_jiffies = msecs_to_jiffies(hba->hibern8_on_idle.delay_ms); + if (delay_in_jiffies == 1) + delay_in_jiffies++; + + schedule_delayed_work(&hba->hibern8_on_idle.enter_work, + delay_in_jiffies); +} + +static void ufshcd_hibern8_release(struct ufs_hba *hba, bool no_sched) +{ + unsigned long flags; + + spin_lock_irqsave(hba->host->host_lock, flags); + __ufshcd_hibern8_release(hba, no_sched); + spin_unlock_irqrestore(hba->host->host_lock, flags); +} + +static void ufshcd_hibern8_enter_work(struct work_struct *work) +{ + struct ufs_hba *hba = container_of(work, struct ufs_hba, + hibern8_on_idle.enter_work.work); + unsigned long flags; + + spin_lock_irqsave(hba->host->host_lock, flags); + if (hba->hibern8_on_idle.is_suspended) { + hba->hibern8_on_idle.state = HIBERN8_EXITED; + trace_ufshcd_hibern8_on_idle(dev_name(hba->dev), + hba->hibern8_on_idle.state); + goto rel_lock; + } + + if (hba->hibern8_on_idle.active_reqs + || hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL + || hba->lrb_in_use || hba->outstanding_tasks + || hba->active_uic_cmd || hba->uic_async_done) + goto rel_lock; + + spin_unlock_irqrestore(hba->host->host_lock, flags); + + if (ufshcd_is_link_active(hba) && ufshcd_uic_hibern8_enter(hba)) { + /* Enter failed */ + hba->hibern8_on_idle.state = HIBERN8_EXITED; + trace_ufshcd_hibern8_on_idle(dev_name(hba->dev), + hba->hibern8_on_idle.state); + goto out; + } + ufshcd_set_link_hibern8(hba); + + /* + * In case you are here to cancel this work the hibern8_on_idle.state + * would be marked as REQ_HIBERN8_EXIT. In this case keep the state + * as REQ_HIBERN8_EXIT which would anyway imply that we are in hibern8 + * and a request to exit from it is pending. By doing this way, + * we keep the state machine in tact and this would ultimately + * prevent from doing cancel work multiple times when there are + * new requests arriving before the current cancel work is done. + */ + spin_lock_irqsave(hba->host->host_lock, flags); + if (hba->hibern8_on_idle.state == REQ_HIBERN8_ENTER) { + hba->hibern8_on_idle.state = HIBERN8_ENTERED; + trace_ufshcd_hibern8_on_idle(dev_name(hba->dev), + hba->hibern8_on_idle.state); + } +rel_lock: + spin_unlock_irqrestore(hba->host->host_lock, flags); +out: + return; +} + +static void __ufshcd_set_auto_hibern8_timer(struct ufs_hba *hba, + unsigned long delay_ms) +{ + pm_runtime_get_sync(hba->dev); + ufshcd_hold_all(hba); + ufshcd_scsi_block_requests(hba); + down_write(&hba->lock); + /* wait for all the outstanding requests to finish */ + ufshcd_wait_for_doorbell_clr(hba, U64_MAX); + ufshcd_set_auto_hibern8_timer(hba, delay_ms); + up_write(&hba->lock); + ufshcd_scsi_unblock_requests(hba); + ufshcd_release_all(hba); + pm_runtime_put_sync(hba->dev); +} + +static void ufshcd_hibern8_exit_work(struct work_struct *work) +{ + int ret; + unsigned long flags; + struct ufs_hba *hba = container_of(work, struct ufs_hba, + hibern8_on_idle.exit_work); + + cancel_delayed_work_sync(&hba->hibern8_on_idle.enter_work); + + spin_lock_irqsave(hba->host->host_lock, flags); + if ((hba->hibern8_on_idle.state == HIBERN8_EXITED) + || ufshcd_is_link_active(hba)) { + hba->hibern8_on_idle.state = HIBERN8_EXITED; + spin_unlock_irqrestore(hba->host->host_lock, flags); + goto unblock_reqs; + } + spin_unlock_irqrestore(hba->host->host_lock, flags); + + /* Exit from hibern8 */ + if (ufshcd_is_link_hibern8(hba)) { + hba->ufs_stats.clk_hold.ctx = H8_EXIT_WORK; + ufshcd_hold(hba, false); + ret = ufshcd_uic_hibern8_exit(hba); + hba->ufs_stats.clk_rel.ctx = H8_EXIT_WORK; + ufshcd_release(hba, false); + if (!ret) { + spin_lock_irqsave(hba->host->host_lock, flags); + ufshcd_set_link_active(hba); + hba->hibern8_on_idle.state = HIBERN8_EXITED; + trace_ufshcd_hibern8_on_idle(dev_name(hba->dev), + hba->hibern8_on_idle.state); + spin_unlock_irqrestore(hba->host->host_lock, flags); + } + } +unblock_reqs: + ufshcd_scsi_unblock_requests(hba); +} + +static ssize_t ufshcd_hibern8_on_idle_delay_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct ufs_hba *hba = dev_get_drvdata(dev); + + return snprintf(buf, PAGE_SIZE, "%lu\n", hba->hibern8_on_idle.delay_ms); +} + +static ssize_t ufshcd_hibern8_on_idle_delay_store(struct device *dev, + struct device_attribute *attr, const char *buf, size_t count) +{ + struct ufs_hba *hba = dev_get_drvdata(dev); + unsigned long flags, value; + bool change = true; + + if (kstrtoul(buf, 0, &value)) + return -EINVAL; + + spin_lock_irqsave(hba->host->host_lock, flags); + if (hba->hibern8_on_idle.delay_ms == value) + change = false; + + if (value >= hba->clk_gating.delay_ms_pwr_save || + value >= hba->clk_gating.delay_ms_perf) { + dev_err(hba->dev, "hibern8_on_idle_delay (%lu) can not be >= to clkgate_delay_ms_pwr_save (%lu) and clkgate_delay_ms_perf (%lu)\n", + value, hba->clk_gating.delay_ms_pwr_save, + hba->clk_gating.delay_ms_perf); + spin_unlock_irqrestore(hba->host->host_lock, flags); + return -EINVAL; + } + + hba->hibern8_on_idle.delay_ms = value; + spin_unlock_irqrestore(hba->host->host_lock, flags); + + /* Update auto hibern8 timer value if supported */ + if (change && ufshcd_is_auto_hibern8_supported(hba) && + hba->hibern8_on_idle.is_enabled) + __ufshcd_set_auto_hibern8_timer(hba, + hba->hibern8_on_idle.delay_ms); + + return count; +} + +static ssize_t ufshcd_hibern8_on_idle_enable_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct ufs_hba *hba = dev_get_drvdata(dev); + + return snprintf(buf, PAGE_SIZE, "%d\n", + hba->hibern8_on_idle.is_enabled); +} + +static ssize_t ufshcd_hibern8_on_idle_enable_store(struct device *dev, + struct device_attribute *attr, const char *buf, size_t count) +{ + struct ufs_hba *hba = dev_get_drvdata(dev); + unsigned long flags; + u32 value; + + if (kstrtou32(buf, 0, &value)) + return -EINVAL; + + value = !!value; + if (value == hba->hibern8_on_idle.is_enabled) + goto out; + + /* Update auto hibern8 timer value if supported */ + if (ufshcd_is_auto_hibern8_supported(hba)) { + __ufshcd_set_auto_hibern8_timer(hba, + value ? hba->hibern8_on_idle.delay_ms : value); + goto update; + } + + if (value) { + /* + * As clock gating work would wait for the hibern8 enter work + * to finish, clocks would remain on during hibern8 enter work. + */ + ufshcd_hold(hba, false); + ufshcd_release_all(hba); + } else { + spin_lock_irqsave(hba->host->host_lock, flags); + hba->hibern8_on_idle.active_reqs++; + spin_unlock_irqrestore(hba->host->host_lock, flags); + } + +update: + hba->hibern8_on_idle.is_enabled = value; +out: + return count; +} + +static void ufshcd_init_hibern8_on_idle(struct ufs_hba *hba) +{ + /* initialize the state variable here */ + hba->hibern8_on_idle.state = HIBERN8_EXITED; + + if (!ufshcd_is_hibern8_on_idle_allowed(hba) && + !ufshcd_is_auto_hibern8_supported(hba)) + return; + + if (ufshcd_is_auto_hibern8_supported(hba)) { + hba->hibern8_on_idle.delay_ms = 1; + hba->hibern8_on_idle.state = AUTO_HIBERN8; + /* + * Disable SW hibern8 enter on idle in case + * auto hibern8 is supported + */ + hba->caps &= ~UFSHCD_CAP_HIBERN8_ENTER_ON_IDLE; + } else { + hba->hibern8_on_idle.delay_ms = 10; + INIT_DELAYED_WORK(&hba->hibern8_on_idle.enter_work, + ufshcd_hibern8_enter_work); + INIT_WORK(&hba->hibern8_on_idle.exit_work, + ufshcd_hibern8_exit_work); + } + + hba->hibern8_on_idle.is_enabled = true; + + hba->hibern8_on_idle.delay_attr.show = + ufshcd_hibern8_on_idle_delay_show; + hba->hibern8_on_idle.delay_attr.store = + ufshcd_hibern8_on_idle_delay_store; + sysfs_attr_init(&hba->hibern8_on_idle.delay_attr.attr); + hba->hibern8_on_idle.delay_attr.attr.name = "hibern8_on_idle_delay_ms"; + hba->hibern8_on_idle.delay_attr.attr.mode = S_IRUGO | S_IWUSR; + if (device_create_file(hba->dev, &hba->hibern8_on_idle.delay_attr)) + dev_err(hba->dev, "Failed to create sysfs for hibern8_on_idle_delay\n"); + + hba->hibern8_on_idle.enable_attr.show = + ufshcd_hibern8_on_idle_enable_show; + hba->hibern8_on_idle.enable_attr.store = + ufshcd_hibern8_on_idle_enable_store; + sysfs_attr_init(&hba->hibern8_on_idle.enable_attr.attr); + hba->hibern8_on_idle.enable_attr.attr.name = "hibern8_on_idle_enable"; + hba->hibern8_on_idle.enable_attr.attr.mode = S_IRUGO | S_IWUSR; + if (device_create_file(hba->dev, &hba->hibern8_on_idle.enable_attr)) + dev_err(hba->dev, "Failed to create sysfs for hibern8_on_idle_enable\n"); +} + +static void ufshcd_exit_hibern8_on_idle(struct ufs_hba *hba) +{ + if (!ufshcd_is_hibern8_on_idle_allowed(hba) && + !ufshcd_is_auto_hibern8_supported(hba)) + return; + device_remove_file(hba->dev, &hba->hibern8_on_idle.delay_attr); + device_remove_file(hba->dev, &hba->hibern8_on_idle.enable_attr); +} + +static void ufshcd_hold_all(struct ufs_hba *hba) +{ + ufshcd_hold(hba, false); + ufshcd_hibern8_hold(hba, false); +} + +static void ufshcd_release_all(struct ufs_hba *hba) +{ + ufshcd_hibern8_release(hba, false); + ufshcd_release(hba, false); } /* Must be called with host lock acquired */ static void ufshcd_clk_scaling_start_busy(struct ufs_hba *hba) { - if (!ufshcd_is_clkscaling_enabled(hba)) + bool queue_resume_work = false; + + if (!ufshcd_is_clkscaling_supported(hba)) + return; + + if (!hba->clk_scaling.active_reqs++) + queue_resume_work = true; + + if (!hba->clk_scaling.is_allowed || hba->pm_op_in_progress) return; + if (queue_resume_work) + queue_work(hba->clk_scaling.workq, + &hba->clk_scaling.resume_work); + + if (!hba->clk_scaling.window_start_t) { + hba->clk_scaling.window_start_t = jiffies; + hba->clk_scaling.tot_busy_t = 0; + hba->clk_scaling.is_busy_started = false; + } + if (!hba->clk_scaling.is_busy_started) { hba->clk_scaling.busy_start_t = ktime_get(); hba->clk_scaling.is_busy_started = true; @@ -781,7 +2312,7 @@ { struct ufs_clk_scaling *scaling = &hba->clk_scaling; - if (!ufshcd_is_clkscaling_enabled(hba)) + if (!ufshcd_is_clkscaling_supported(hba)) return; if (!hba->outstanding_reqs && scaling->is_busy_started) { @@ -791,17 +2322,27 @@ scaling->is_busy_started = false; } } + /** * ufshcd_send_command - Send SCSI or device management commands * @hba: per adapter instance * @task_tag: Task tag of the command */ static inline -void ufshcd_send_command(struct ufs_hba *hba, unsigned int task_tag) +int ufshcd_send_command(struct ufs_hba *hba, unsigned int task_tag) { + int ret = 0; + + hba->lrb[task_tag].issue_time_stamp = ktime_get(); + hba->lrb[task_tag].complete_time_stamp = ktime_set(0, 0); ufshcd_clk_scaling_start_busy(hba); __set_bit(task_tag, &hba->outstanding_reqs); ufshcd_writel(hba, 1 << task_tag, REG_UTP_TRANSFER_REQ_DOOR_BELL); + /* Make sure that doorbell is committed immediately */ + wmb(); + ufshcd_cond_add_cmd_trace(hba, task_tag, "send"); + ufshcd_update_tag_stats(hba, task_tag); + return ret; } /** @@ -813,10 +2354,14 @@ int len; if (lrbp->sense_buffer && ufshcd_get_rsp_upiu_data_seg_len(lrbp->ucd_rsp_ptr)) { + int len_to_copy; + len = be16_to_cpu(lrbp->ucd_rsp_ptr->sr.sense_data_len); + len_to_copy = min_t(int, RESPONSE_UPIU_SENSE_DATA_LENGTH, len); + memcpy(lrbp->sense_buffer, lrbp->ucd_rsp_ptr->sr.sense_data, - min_t(int, len, SCSI_SENSE_BUFFERSIZE)); + min_t(int, len_to_copy, UFSHCD_REQ_SENSE_SIZE)); } } @@ -912,6 +2457,7 @@ hba->active_uic_cmd = uic_cmd; + ufshcd_dme_cmd_log(hba, "send", hba->active_uic_cmd->command); /* Write Args */ ufshcd_writel(hba, uic_cmd->argument1, REG_UIC_COMMAND_ARG_1); ufshcd_writel(hba, uic_cmd->argument2, REG_UIC_COMMAND_ARG_2); @@ -942,6 +2488,11 @@ else ret = -ETIMEDOUT; + if (ret) + ufsdbg_set_err_state(hba); + + ufshcd_dme_cmd_log(hba, "cmp1", hba->active_uic_cmd->command); + spin_lock_irqsave(hba->host->host_lock, flags); hba->active_uic_cmd = NULL; spin_unlock_irqrestore(hba->host->host_lock, flags); @@ -953,13 +2504,15 @@ * __ufshcd_send_uic_cmd - Send UIC commands and retrieve the result * @hba: per adapter instance * @uic_cmd: UIC command + * @completion: initialize the completion only if this is set to true * * Identical to ufshcd_send_uic_cmd() expect mutex. Must be called * with mutex held and host_lock locked. * Returns 0 only if success. */ static int -__ufshcd_send_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd) +__ufshcd_send_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd, + bool completion) { if (!ufshcd_ready_for_uic_cmd(hba)) { dev_err(hba->dev, @@ -967,6 +2520,7 @@ return -EIO; } + if (completion) init_completion(&uic_cmd->done); ufshcd_dispatch_uic_cmd(hba, uic_cmd); @@ -987,19 +2541,25 @@ int ret; unsigned long flags; - ufshcd_hold(hba, false); + hba->ufs_stats.clk_hold.ctx = UIC_CMD_SEND; + ufshcd_hold_all(hba); mutex_lock(&hba->uic_cmd_mutex); ufshcd_add_delay_before_dme_cmd(hba); spin_lock_irqsave(hba->host->host_lock, flags); - ret = __ufshcd_send_uic_cmd(hba, uic_cmd); + ret = __ufshcd_send_uic_cmd(hba, uic_cmd, true); spin_unlock_irqrestore(hba->host->host_lock, flags); if (!ret) ret = ufshcd_wait_for_uic_cmd(hba, uic_cmd); + ufshcd_save_tstamp_of_last_dme_cmd(hba); mutex_unlock(&hba->uic_cmd_mutex); + ufshcd_release_all(hba); + hba->ufs_stats.clk_rel.ctx = UIC_CMD_SEND; + + ufsdbg_error_inject_dispatcher(hba, + ERR_INJECT_UIC, 0, &ret); - ufshcd_release(hba); return ret; } @@ -1035,6 +2595,7 @@ cpu_to_le32(lower_32_bits(sg->dma_address)); prd_table[i].upper_addr = cpu_to_le32(upper_32_bits(sg->dma_address)); + prd_table[i].reserved = 0; } } else { lrbp->utr_descriptor_ptr->prd_table_length = 0; @@ -1085,15 +2646,52 @@ ufshcd_writel(hba, set, REG_INTERRUPT_ENABLE); } +static int ufshcd_prepare_crypto_utrd(struct ufs_hba *hba, + struct ufshcd_lrb *lrbp) +{ + struct utp_transfer_req_desc *req_desc = lrbp->utr_descriptor_ptr; + u8 cc_index = 0; + bool enable = false; + u64 dun = 0; + int ret; + + /* + * Call vendor specific code to get crypto info for this request: + * enable, crypto config. index, DUN. + * If bypass is set, don't bother setting the other fields. + */ + ret = ufshcd_vops_crypto_req_setup(hba, lrbp, &cc_index, &enable, &dun); + if (ret) { + if (ret != -EAGAIN) { + dev_err(hba->dev, + "%s: failed to setup crypto request (%d)\n", + __func__, ret); + } + + return ret; + } + + if (!enable) + goto out; + + req_desc->header.dword_0 |= cc_index | UTRD_CRYPTO_ENABLE; + req_desc->header.dword_1 = (u32)(dun & 0xFFFFFFFF); + req_desc->header.dword_3 = (u32)((dun >> 32) & 0xFFFFFFFF); +out: + return 0; +} + /** * ufshcd_prepare_req_desc_hdr() - Fills the requests header * descriptor according to request + * @hba: per adapter instance * @lrbp: pointer to local reference block * @upiu_flags: flags required in the header * @cmd_dir: requests data direction */ -static void ufshcd_prepare_req_desc_hdr(struct ufshcd_lrb *lrbp, - u32 *upiu_flags, enum dma_data_direction cmd_dir) +static int ufshcd_prepare_req_desc_hdr(struct ufs_hba *hba, + struct ufshcd_lrb *lrbp, u32 *upiu_flags, + enum dma_data_direction cmd_dir) { struct utp_transfer_req_desc *req_desc = lrbp->utr_descriptor_ptr; u32 data_direction; @@ -1117,7 +2715,8 @@ /* Transfer request descriptor header fields */ req_desc->header.dword_0 = cpu_to_le32(dword_0); - + /* dword_1 is reserved, hence it is set to 0 */ + req_desc->header.dword_1 = 0; /* * assigning invalid value for command status. Controller * updates OCS on command completion, with the command @@ -1125,6 +2724,15 @@ */ req_desc->header.dword_2 = cpu_to_le32(OCS_INVALID_COMMAND_STATUS); + /* dword_3 is reserved, hence it is set to 0 */ + req_desc->header.dword_3 = 0; + + req_desc->prd_table_length = 0; + + if (ufshcd_is_crypto_supported(hba)) + return ufshcd_prepare_crypto_utrd(hba, lrbp); + + return 0; } /** @@ -1137,6 +2745,7 @@ void ufshcd_prepare_utp_scsi_cmd_upiu(struct ufshcd_lrb *lrbp, u32 upiu_flags) { struct utp_upiu_req *ucd_req_ptr = lrbp->ucd_req_ptr; + unsigned short cdb_len; /* command descriptor fields */ ucd_req_ptr->header.dword_0 = UPIU_HEADER_DWORD( @@ -1151,8 +2760,12 @@ ucd_req_ptr->sc.exp_data_transfer_len = cpu_to_be32(lrbp->cmd->sdb.length); - memcpy(ucd_req_ptr->sc.cdb, lrbp->cmd->cmnd, - (min_t(unsigned short, lrbp->cmd->cmd_len, MAX_CDB_SIZE))); + cdb_len = min_t(unsigned short, lrbp->cmd->cmd_len, MAX_CDB_SIZE); + memcpy(ucd_req_ptr->sc.cdb, lrbp->cmd->cmnd, cdb_len); + if (cdb_len < MAX_CDB_SIZE) + memset(ucd_req_ptr->sc.cdb + cdb_len, 0, + (MAX_CDB_SIZE - cdb_len)); + memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp)); } /** @@ -1189,6 +2802,7 @@ if (query->request.upiu_req.opcode == UPIU_QUERY_OPCODE_WRITE_DESC) memcpy(descp, query->descriptor, len); + memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp)); } static inline void ufshcd_prepare_utp_nop_upiu(struct ufshcd_lrb *lrbp) @@ -1201,6 +2815,11 @@ ucd_req_ptr->header.dword_0 = UPIU_HEADER_DWORD( UPIU_TRANSACTION_NOP_OUT, 0, 0, lrbp->task_tag); + /* clear rest of the fields of basic header */ + ucd_req_ptr->header.dword_1 = 0; + ucd_req_ptr->header.dword_2 = 0; + + memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp)); } /** @@ -1216,15 +2835,16 @@ switch (lrbp->command_type) { case UTP_CMD_TYPE_SCSI: if (likely(lrbp->cmd)) { - ufshcd_prepare_req_desc_hdr(lrbp, &upiu_flags, - lrbp->cmd->sc_data_direction); + ret = ufshcd_prepare_req_desc_hdr(hba, lrbp, + &upiu_flags, lrbp->cmd->sc_data_direction); ufshcd_prepare_utp_scsi_cmd_upiu(lrbp, upiu_flags); } else { ret = -EINVAL; } break; case UTP_CMD_TYPE_DEV_MANAGE: - ufshcd_prepare_req_desc_hdr(lrbp, &upiu_flags, DMA_NONE); + ret = ufshcd_prepare_req_desc_hdr(hba, lrbp, &upiu_flags, + DMA_NONE); if (hba->dev_cmd.type == DEV_CMD_TYPE_QUERY) ufshcd_prepare_utp_query_req_upiu( hba, lrbp, upiu_flags); @@ -1276,6 +2896,61 @@ } /** + * ufshcd_get_write_lock - synchronize between shutdown, scaling & + * arrival of requests + * @hba: ufs host + * + * Lock is predominantly held by shutdown context thus, ensuring + * that no requests from any other context may sneak through. + */ +static inline void ufshcd_get_write_lock(struct ufs_hba *hba) +{ + down_write(&hba->lock); +} + +/** + * ufshcd_get_read_lock - synchronize between shutdown, scaling & + * arrival of requests + * @hba: ufs host + * + * Returns 1 if acquired, < 0 on contention + * + * After shutdown's initiated, allow requests only directed to the + * well known device lun. The sync between scaling & issue is maintained + * as is and this restructuring syncs shutdown with these too. + */ +static int ufshcd_get_read_lock(struct ufs_hba *hba, u64 lun) +{ + int err = 0; + + err = down_read_trylock(&hba->lock); + if (err > 0) + goto out; + /* let requests for well known device lun to go through */ + if (ufshcd_scsi_to_upiu_lun(lun) == UFS_UPIU_UFS_DEVICE_WLUN) + return 0; + else if (!ufshcd_is_shutdown_ongoing(hba)) + return -EAGAIN; + else + return -EPERM; + +out: + return err; +} + +/** + * ufshcd_put_read_lock - synchronize between shutdown, scaling & + * arrival of requests + * @hba: ufs host + * + * Returns none + */ +static inline void ufshcd_put_read_lock(struct ufs_hba *hba) +{ + up_read(&hba->lock); +} + +/** * ufshcd_queuecommand - main entry point for SCSI requests * @cmd: command from SCSI Midlayer * @done: call back function @@ -1289,12 +2964,42 @@ unsigned long flags; int tag; int err = 0; + bool has_read_lock = false; hba = shost_priv(host); + if (!cmd || !cmd->request || !hba) + return -EINVAL; + tag = cmd->request->tag; + if (!ufshcd_valid_tag(hba, tag)) { + dev_err(hba->dev, + "%s: invalid command tag %d: cmd=0x%p, cmd->request=0x%p", + __func__, tag, cmd, cmd->request); + BUG(); + } + + err = ufshcd_get_read_lock(hba, cmd->device->lun); + if (unlikely(err < 0)) { + if (err == -EPERM) { + set_host_byte(cmd, DID_ERROR); + cmd->scsi_done(cmd); + return 0; + } + if (err == -EAGAIN) + return SCSI_MLQUEUE_HOST_BUSY; + } else if (err == 1) { + has_read_lock = true; + } spin_lock_irqsave(hba->host->host_lock, flags); + + /* if error handling is in progress, return host busy */ + if (ufshcd_eh_in_progress(hba)) { + err = SCSI_MLQUEUE_HOST_BUSY; + goto out_unlock; + } + switch (hba->ufshcd_state) { case UFSHCD_STATE_OPERATIONAL: break; @@ -1314,6 +3019,8 @@ } spin_unlock_irqrestore(hba->host->host_lock, flags); + hba->req_abort_count = 0; + /* acquire the tag to make sure device cmds don't use it */ if (test_and_set_bit_lock(tag, &hba->lrb_in_use)) { /* @@ -1326,40 +3033,118 @@ goto out; } + hba->ufs_stats.clk_hold.ctx = QUEUE_CMD; err = ufshcd_hold(hba, true); if (err) { err = SCSI_MLQUEUE_HOST_BUSY; clear_bit_unlock(tag, &hba->lrb_in_use); goto out; } + if (ufshcd_is_clkgating_allowed(hba)) + WARN_ON(hba->clk_gating.state != CLKS_ON); + + err = ufshcd_hibern8_hold(hba, true); + if (err) { + clear_bit_unlock(tag, &hba->lrb_in_use); + err = SCSI_MLQUEUE_HOST_BUSY; + hba->ufs_stats.clk_rel.ctx = QUEUE_CMD; + ufshcd_release(hba, true); + goto out; + } + if (ufshcd_is_hibern8_on_idle_allowed(hba)) + WARN_ON(hba->hibern8_on_idle.state != HIBERN8_EXITED); + + /* Vote PM QoS for the request */ + ufshcd_vops_pm_qos_req_start(hba, cmd->request); + + /* IO svc time latency histogram */ + if (hba->latency_hist_enabled && + (cmd->request->cmd_type == REQ_TYPE_FS)) { + cmd->request->lat_hist_io_start = ktime_get(); + cmd->request->lat_hist_enabled = 1; + } else { + cmd->request->lat_hist_enabled = 0; + } + WARN_ON(hba->clk_gating.state != CLKS_ON); lrbp = &hba->lrb[tag]; WARN_ON(lrbp->cmd); lrbp->cmd = cmd; - lrbp->sense_bufflen = SCSI_SENSE_BUFFERSIZE; + lrbp->sense_bufflen = UFSHCD_REQ_SENSE_SIZE; lrbp->sense_buffer = cmd->sense_buffer; lrbp->task_tag = tag; lrbp->lun = ufshcd_scsi_to_upiu_lun(cmd->device->lun); lrbp->intr_cmd = !ufshcd_is_intr_aggr_allowed(hba) ? true : false; lrbp->command_type = UTP_CMD_TYPE_SCSI; + lrbp->req_abort_skip = false; /* form UPIU before issuing the command */ - ufshcd_compose_upiu(hba, lrbp); + err = ufshcd_compose_upiu(hba, lrbp); + if (err) { + if (err != -EAGAIN) + dev_err(hba->dev, + "%s: failed to compose upiu %d\n", + __func__, err); + + lrbp->cmd = NULL; + clear_bit_unlock(tag, &hba->lrb_in_use); + ufshcd_release_all(hba); + ufshcd_vops_pm_qos_req_end(hba, cmd->request, true); + goto out; + } + err = ufshcd_map_sg(lrbp); if (err) { lrbp->cmd = NULL; clear_bit_unlock(tag, &hba->lrb_in_use); + ufshcd_release_all(hba); + ufshcd_vops_pm_qos_req_end(hba, cmd->request, true); + goto out; + } + + err = ufshcd_vops_crypto_engine_cfg_start(hba, tag); + if (err) { + if (err != -EAGAIN) + dev_err(hba->dev, + "%s: failed to configure crypto engine %d\n", + __func__, err); + + scsi_dma_unmap(lrbp->cmd); + lrbp->cmd = NULL; + clear_bit_unlock(tag, &hba->lrb_in_use); + ufshcd_release_all(hba); + ufshcd_vops_pm_qos_req_end(hba, cmd->request, true); + goto out; } + /* Make sure descriptors are ready before ringing the doorbell */ + wmb(); /* issue command to the controller */ spin_lock_irqsave(hba->host->host_lock, flags); - ufshcd_send_command(hba, tag); + + err = ufshcd_send_command(hba, tag); + if (err) { + spin_unlock_irqrestore(hba->host->host_lock, flags); + scsi_dma_unmap(lrbp->cmd); + lrbp->cmd = NULL; + clear_bit_unlock(tag, &hba->lrb_in_use); + ufshcd_release_all(hba); + ufshcd_vops_pm_qos_req_end(hba, cmd->request, true); + ufshcd_vops_crypto_engine_cfg_end(hba, lrbp, cmd->request); + dev_err(hba->dev, "%s: failed sending command, %d\n", + __func__, err); + err = DID_ERROR; + goto out; + } + out_unlock: spin_unlock_irqrestore(hba->host->host_lock, flags); out: + if (has_read_lock) + ufshcd_put_read_lock(hba); return err; } @@ -1396,7 +3181,7 @@ */ err = ufshcd_wait_for_register(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL, - mask, ~mask, 1000, 1000); + mask, ~mask, 1000, 1000, true); return err; } @@ -1423,6 +3208,7 @@ int resp; int err = 0; + hba->ufs_stats.last_hibern8_exit_tstamp = ktime_set(0, 0); resp = ufshcd_get_req_rsp(lrbp->ucd_rsp_ptr); switch (resp) { @@ -1475,11 +3261,22 @@ if (!time_left) { err = -ETIMEDOUT; + dev_dbg(hba->dev, "%s: dev_cmd request timedout, tag %d\n", + __func__, lrbp->task_tag); if (!ufshcd_clear_cmd(hba, lrbp->task_tag)) - /* sucessfully cleared the command, retry if needed */ + /* successfully cleared the command, retry if needed */ err = -EAGAIN; + /* + * in case of an error, after clearing the doorbell, + * we also need to clear the outstanding_request + * field in hba + */ + ufshcd_outstanding_req_clear(hba, lrbp->task_tag); } + if (err) + ufsdbg_set_err_state(hba); + return err; } @@ -1540,6 +3337,15 @@ unsigned long flags; /* + * May get invoked from shutdown and IOCTL contexts. + * In shutdown context, it comes in with lock acquired. + * In error recovery context, it may come with lock acquired. + */ + + if (!ufshcd_is_shutdown_ongoing(hba) && !ufshcd_eh_in_progress(hba)) + down_read(&hba->lock); + + /* * Get free slot, sleep if slots are unavailable. * Even though we use wait_event() which sleeps indefinitely, * the maximum wait time is bounded by SCSI request timeout. @@ -1555,15 +3361,23 @@ hba->dev_cmd.complete = &wait; + /* Make sure descriptors are ready before ringing the doorbell */ + wmb(); spin_lock_irqsave(hba->host->host_lock, flags); - ufshcd_send_command(hba, tag); + err = ufshcd_send_command(hba, tag); spin_unlock_irqrestore(hba->host->host_lock, flags); - + if (err) { + dev_err(hba->dev, "%s: failed sending command, %d\n", + __func__, err); + goto out_put_tag; + } err = ufshcd_wait_for_dev_cmd(hba, lrbp, timeout); out_put_tag: ufshcd_put_dev_cmd_tag(hba, tag); wake_up(&hba->dev_cmd.tag_wq); + if (!ufshcd_is_shutdown_ongoing(hba) && !ufshcd_eh_in_progress(hba)) + up_read(&hba->lock); return err; } @@ -1581,6 +3395,12 @@ struct ufs_query_req **request, struct ufs_query_res **response, enum query_opcode opcode, u8 idn, u8 index, u8 selector) { + int idn_t = (int)idn; + + ufsdbg_error_inject_dispatcher(hba, + ERR_INJECT_QUERY, idn_t, (int *)&idn_t); + idn = idn_t; + *request = &hba->dev_cmd.query.request; *response = &hba->dev_cmd.query.response; memset(*request, 0, sizeof(struct ufs_query_req)); @@ -1589,6 +3409,31 @@ (*request)->upiu_req.idn = idn; (*request)->upiu_req.index = index; (*request)->upiu_req.selector = selector; + + ufshcd_update_query_stats(hba, opcode, idn); +} + +static int ufshcd_query_flag_retry(struct ufs_hba *hba, + enum query_opcode opcode, enum flag_idn idn, bool *flag_res) +{ + int ret; + int retries; + + for (retries = 0; retries < QUERY_REQ_RETRIES; retries++) { + ret = ufshcd_query_flag(hba, opcode, idn, flag_res); + if (ret) + dev_dbg(hba->dev, + "%s: failed with error %d, retries %d\n", + __func__, ret, retries); + else + break; + } + + if (ret) + dev_err(hba->dev, + "%s: query attribute, opcode %d, idn %d, failed with error %d after %d retires\n", + __func__, opcode, idn, ret, retries); + return ret; } /** @@ -1600,16 +3445,17 @@ * * Returns 0 for success, non-zero in case of failure */ -static int ufshcd_query_flag(struct ufs_hba *hba, enum query_opcode opcode, +int ufshcd_query_flag(struct ufs_hba *hba, enum query_opcode opcode, enum flag_idn idn, bool *flag_res) { struct ufs_query_req *request = NULL; struct ufs_query_res *response = NULL; int err, index = 0, selector = 0; + int timeout = QUERY_REQ_TIMEOUT; BUG_ON(!hba); - ufshcd_hold(hba, false); + ufshcd_hold_all(hba); mutex_lock(&hba->dev_cmd.lock); ufshcd_init_query(hba, &request, &response, opcode, idn, index, selector); @@ -1638,12 +3484,12 @@ goto out_unlock; } - err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, QUERY_REQ_TIMEOUT); + err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, timeout); if (err) { dev_err(hba->dev, "%s: Sending flag query for idn %d failed, err = %d\n", - __func__, idn, err); + __func__, request->upiu_req.idn, err); goto out_unlock; } @@ -1653,9 +3499,10 @@ out_unlock: mutex_unlock(&hba->dev_cmd.lock); - ufshcd_release(hba); + ufshcd_release_all(hba); return err; } +EXPORT_SYMBOL(ufshcd_query_flag); /** * ufshcd_query_attr - API function for sending attribute requests @@ -1668,7 +3515,7 @@ * * Returns 0 for success, non-zero in case of failure */ -static int ufshcd_query_attr(struct ufs_hba *hba, enum query_opcode opcode, +int ufshcd_query_attr(struct ufs_hba *hba, enum query_opcode opcode, enum attr_idn idn, u8 index, u8 selector, u32 *attr_val) { struct ufs_query_req *request = NULL; @@ -1677,7 +3524,7 @@ BUG_ON(!hba); - ufshcd_hold(hba, false); + ufshcd_hold_all(hba); if (!attr_val) { dev_err(hba->dev, "%s: attribute value required for opcode 0x%x\n", __func__, opcode); @@ -1707,8 +3554,9 @@ err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, QUERY_REQ_TIMEOUT); if (err) { - dev_err(hba->dev, "%s: opcode 0x%.2x for idn %d failed, err = %d\n", - __func__, opcode, idn, err); + dev_err(hba->dev, "%s: opcode 0x%.2x for idn %d failed, index %d, err = %d\n", + __func__, opcode, + request->upiu_req.idn, index, err); goto out_unlock; } @@ -1717,25 +3565,49 @@ out_unlock: mutex_unlock(&hba->dev_cmd.lock); out: - ufshcd_release(hba); + ufshcd_release_all(hba); return err; } +EXPORT_SYMBOL(ufshcd_query_attr); /** - * ufshcd_query_descriptor - API function for sending descriptor requests - * hba: per-adapter instance - * opcode: attribute opcode - * idn: attribute idn to access - * index: index field - * selector: selector field - * desc_buf: the buffer that contains the descriptor - * buf_len: length parameter passed to the device + * ufshcd_query_attr_retry() - API function for sending query + * attribute with retries + * @hba: per-adapter instance + * @opcode: attribute opcode + * @idn: attribute idn to access + * @index: index field + * @selector: selector field + * @attr_val: the attribute value after the query request + * completes * - * Returns 0 for success, non-zero in case of failure. - * The buf_len parameter will contain, on return, the length parameter - * received on the response. + * Returns 0 for success, non-zero in case of failure */ -static int ufshcd_query_descriptor(struct ufs_hba *hba, +static int ufshcd_query_attr_retry(struct ufs_hba *hba, + enum query_opcode opcode, enum attr_idn idn, u8 index, u8 selector, + u32 *attr_val) +{ + int ret = 0; + u32 retries; + + for (retries = QUERY_REQ_RETRIES; retries > 0; retries--) { + ret = ufshcd_query_attr(hba, opcode, idn, index, + selector, attr_val); + if (ret) + dev_dbg(hba->dev, "%s: failed with error %d, retries %d\n", + __func__, ret, retries); + else + break; + } + + if (ret) + dev_err(hba->dev, + "%s: query attribute, idn %d, failed with error %d after %d retires\n", + __func__, idn, ret, retries); + return ret; +} + +static int __ufshcd_query_descriptor(struct ufs_hba *hba, enum query_opcode opcode, enum desc_idn idn, u8 index, u8 selector, u8 *desc_buf, int *buf_len) { @@ -1745,7 +3617,7 @@ BUG_ON(!hba); - ufshcd_hold(hba, false); + ufshcd_hold_all(hba); if (!desc_buf) { dev_err(hba->dev, "%s: descriptor buffer required for opcode 0x%x\n", __func__, opcode); @@ -1784,8 +3656,9 @@ err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, QUERY_REQ_TIMEOUT); if (err) { - dev_err(hba->dev, "%s: opcode 0x%.2x for idn %d failed, err = %d\n", - __func__, opcode, idn, err); + dev_err(hba->dev, "%s: opcode 0x%.2x for idn %d failed, index %d, err = %d\n", + __func__, opcode, + request->upiu_req.idn, index, err); goto out_unlock; } @@ -1795,9 +3668,41 @@ out_unlock: mutex_unlock(&hba->dev_cmd.lock); out: - ufshcd_release(hba); + ufshcd_release_all(hba); + return err; +} + +/** + * ufshcd_query_descriptor - API function for sending descriptor requests + * hba: per-adapter instance + * opcode: attribute opcode + * idn: attribute idn to access + * index: index field + * selector: selector field + * desc_buf: the buffer that contains the descriptor + * buf_len: length parameter passed to the device + * + * Returns 0 for success, non-zero in case of failure. + * The buf_len parameter will contain, on return, the length parameter + * received on the response. + */ +int ufshcd_query_descriptor(struct ufs_hba *hba, + enum query_opcode opcode, enum desc_idn idn, u8 index, + u8 selector, u8 *desc_buf, int *buf_len) +{ + int err; + int retries; + + for (retries = QUERY_REQ_RETRIES; retries > 0; retries--) { + err = __ufshcd_query_descriptor(hba, opcode, idn, index, + selector, desc_buf, buf_len); + if (!err || err == -EINVAL) + break; + } + return err; } +EXPORT_SYMBOL(ufshcd_query_descriptor); /** * ufshcd_read_desc_param - read the specified descriptor parameter @@ -1845,15 +3750,38 @@ desc_id, desc_index, 0, desc_buf, &buff_len); - if (ret || (buff_len < ufs_query_desc_max_size[desc_id]) || - (desc_buf[QUERY_DESC_LENGTH_OFFSET] != - ufs_query_desc_max_size[desc_id]) - || (desc_buf[QUERY_DESC_DESC_TYPE_OFFSET] != desc_id)) { - dev_err(hba->dev, "%s: Failed reading descriptor. desc_id %d param_offset %d buff_len %d ret %d", - __func__, desc_id, param_offset, buff_len, ret); - if (!ret) + if (ret) { + dev_err(hba->dev, "%s: Failed reading descriptor. desc_id %d, desc_index %d, param_offset %d, ret %d", + __func__, desc_id, desc_index, param_offset, ret); + + goto out; + } + + /* Sanity check */ + if (desc_buf[QUERY_DESC_DESC_TYPE_OFFSET] != desc_id) { + dev_err(hba->dev, "%s: invalid desc_id %d in descriptor header", + __func__, desc_buf[QUERY_DESC_DESC_TYPE_OFFSET]); ret = -EINVAL; + goto out; + } + /* + * While reading variable size descriptors (like string descriptor), + * some UFS devices may report the "LENGTH" (field in "Transaction + * Specific fields" of Query Response UPIU) same as what was requested + * in Query Request UPIU instead of reporting the actual size of the + * variable size descriptor. + * Although it's safe to ignore the "LENGTH" field for variable size + * descriptors as we can always derive the length of the descriptor from + * the descriptor header fields. Hence this change impose the length + * match check only for fixed size descriptors (for which we always + * request the correct size as part of Query Request UPIU). + */ + if ((desc_id != QUERY_DESC_IDN_STRING) && + (buff_len != desc_buf[QUERY_DESC_LENGTH_OFFSET])) { + dev_err(hba->dev, "%s: desc_buf length mismatch: buff_len %d, buff_len(desc_header) %d", + __func__, buff_len, desc_buf[QUERY_DESC_LENGTH_OFFSET]); + ret = -EINVAL; goto out; } @@ -1881,6 +3809,82 @@ return ufshcd_read_desc(hba, QUERY_DESC_IDN_POWER, 0, buf, size); } +int ufshcd_read_device_desc(struct ufs_hba *hba, u8 *buf, u32 size) +{ + return ufshcd_read_desc(hba, QUERY_DESC_IDN_DEVICE, 0, buf, size); +} + +/** + * ufshcd_read_string_desc - read string descriptor + * @hba: pointer to adapter instance + * @desc_index: descriptor index + * @buf: pointer to buffer where descriptor would be read + * @size: size of buf + * @ascii: if true convert from unicode to ascii characters + * + * Return 0 in case of success, non-zero otherwise + */ +int ufshcd_read_string_desc(struct ufs_hba *hba, int desc_index, u8 *buf, + u32 size, bool ascii) +{ + int err = 0; + + err = ufshcd_read_desc(hba, + QUERY_DESC_IDN_STRING, desc_index, buf, size); + + if (err) { + dev_err(hba->dev, "%s: reading String Desc failed after %d retries. err = %d\n", + __func__, QUERY_REQ_RETRIES, err); + goto out; + } + + if (ascii) { + int desc_len; + int ascii_len; + int i; + char *buff_ascii; + + desc_len = buf[0]; + /* remove header and divide by 2 to move from UTF16 to UTF8 */ + ascii_len = (desc_len - QUERY_DESC_HDR_SIZE) / 2 + 1; + if (size < ascii_len + QUERY_DESC_HDR_SIZE) { + dev_err(hba->dev, "%s: buffer allocated size is too small\n", + __func__); + err = -ENOMEM; + goto out; + } + + buff_ascii = kzalloc(ascii_len, GFP_KERNEL); + if (!buff_ascii) { + dev_err(hba->dev, "%s: Failed allocating %d bytes\n", + __func__, ascii_len); + err = -ENOMEM; + goto out_free_buff; + } + + /* + * the descriptor contains string in UTF16 format + * we need to convert to utf-8 so it can be displayed + */ + utf16s_to_utf8s((wchar_t *)&buf[QUERY_DESC_HDR_SIZE], + desc_len - QUERY_DESC_HDR_SIZE, + UTF16_BIG_ENDIAN, buff_ascii, ascii_len); + + /* replace non-printable or non-ASCII characters with spaces */ + for (i = 0; i < ascii_len; i++) + ufshcd_remove_non_printable(&buff_ascii[i]); + + memset(buf + QUERY_DESC_HDR_SIZE, 0, + size - QUERY_DESC_HDR_SIZE); + memcpy(buf + QUERY_DESC_HDR_SIZE, buff_ascii, ascii_len); + buf[QUERY_DESC_LENGTH_OFFSET] = ascii_len + QUERY_DESC_HDR_SIZE; +out_free_buff: + kfree(buff_ascii); + } +out: + return err; +} + /** * ufshcd_read_unit_desc_param - read the specified unit descriptor parameter * @hba: Pointer to adapter instance @@ -1901,7 +3905,7 @@ * Unit descriptors are only available for general purpose LUs (LUN id * from 0 to 7) and RPMB Well known LU. */ - if (lun != UFS_UPIU_RPMB_WLUN && (lun >= UFS_UPIU_MAX_GENERAL_LUN)) + if (!ufs_is_valid_unit_desc_lun(lun)) return -EOPNOTSUPP; return ufshcd_read_desc_param(hba, QUERY_DESC_IDN_UNIT, lun, @@ -2043,12 +4047,19 @@ cpu_to_le16(ALIGNED_UPIU_SIZE >> 2); hba->lrb[i].utr_descriptor_ptr = (utrdlp + i); + hba->lrb[i].utrd_dma_addr = hba->utrdl_dma_addr + + (i * sizeof(struct utp_transfer_req_desc)); hba->lrb[i].ucd_req_ptr = (struct utp_upiu_req *)(cmd_descp + i); + hba->lrb[i].ucd_req_dma_addr = cmd_desc_element_addr; hba->lrb[i].ucd_rsp_ptr = (struct utp_upiu_rsp *)cmd_descp[i].response_upiu; + hba->lrb[i].ucd_rsp_dma_addr = cmd_desc_element_addr + + response_offset; hba->lrb[i].ucd_prdt_ptr = (struct ufshcd_sg_entry *)cmd_descp[i].prd_table; + hba->lrb[i].ucd_prdt_dma_addr = cmd_desc_element_addr + + prdt_offset; } } @@ -2072,7 +4083,7 @@ ret = ufshcd_send_uic_cmd(hba, &uic_cmd); if (ret) - dev_err(hba->dev, + dev_dbg(hba->dev, "dme-link-startup: error code %d\n", ret); return ret; } @@ -2108,6 +4119,13 @@ usleep_range(min_sleep_time_us, min_sleep_time_us + 50); } +static inline void ufshcd_save_tstamp_of_last_dme_cmd( + struct ufs_hba *hba) +{ + if (hba->quirks & UFSHCD_QUIRK_DELAY_BEFORE_DME_CMDS) + hba->last_dme_cmd_tstamp = ktime_get(); +} + /** * ufshcd_dme_set_attr - UIC command for DME_SET, DME_PEER_SET * @hba: per adapter instance @@ -2128,6 +4146,10 @@ }; const char *set = action[!!peer]; int ret; + int retries = UFS_UIC_COMMAND_RETRIES; + + ufsdbg_error_inject_dispatcher(hba, + ERR_INJECT_DME_ATTR, attr_sel, &attr_sel); uic_cmd.command = peer ? UIC_CMD_DME_PEER_SET : UIC_CMD_DME_SET; @@ -2135,10 +4157,18 @@ uic_cmd.argument2 = UIC_ARG_ATTR_TYPE(attr_set); uic_cmd.argument3 = mib_val; + do { + /* for peer attributes we retry upon failure */ ret = ufshcd_send_uic_cmd(hba, &uic_cmd); if (ret) - dev_err(hba->dev, "%s: attr-id 0x%x val 0x%x error code %d\n", + dev_dbg(hba->dev, "%s: attr-id 0x%x val 0x%x error code %d\n", set, UIC_GET_ATTR_ID(attr_sel), mib_val, ret); + } while (ret && peer && --retries); + + if (ret) + dev_err(hba->dev, "%s: attr-id 0x%x val 0x%x failed %d retries\n", + set, UIC_GET_ATTR_ID(attr_sel), mib_val, + UFS_UIC_COMMAND_RETRIES - retries); return ret; } @@ -2163,6 +4193,7 @@ }; const char *get = action[!!peer]; int ret; + int retries = UFS_UIC_COMMAND_RETRIES; struct ufs_pa_layer_attr orig_pwr_info; struct ufs_pa_layer_attr temp_pwr_info; bool pwr_mode_change = false; @@ -2191,16 +4222,26 @@ uic_cmd.command = peer ? UIC_CMD_DME_PEER_GET : UIC_CMD_DME_GET; + + ufsdbg_error_inject_dispatcher(hba, + ERR_INJECT_DME_ATTR, attr_sel, &attr_sel); + uic_cmd.argument1 = attr_sel; + do { + /* for peer attributes we retry upon failure */ ret = ufshcd_send_uic_cmd(hba, &uic_cmd); - if (ret) { - dev_err(hba->dev, "%s: attr-id 0x%x error code %d\n", + if (ret) + dev_dbg(hba->dev, "%s: attr-id 0x%x error code %d\n", get, UIC_GET_ATTR_ID(attr_sel), ret); - goto out; - } + } while (ret && peer && --retries); + + if (ret) + dev_err(hba->dev, "%s: attr-id 0x%x failed %d retries\n", + get, UIC_GET_ATTR_ID(attr_sel), + UFS_UIC_COMMAND_RETRIES - retries); - if (mib_val) + if (mib_val && !ret) *mib_val = uic_cmd.argument3; if (peer && (hba->quirks & UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE) @@ -2233,6 +4274,7 @@ unsigned long flags; u8 status; int ret; + bool reenable_intr = false; mutex_lock(&hba->uic_cmd_mutex); init_completion(&uic_async_done); @@ -2240,15 +4282,17 @@ spin_lock_irqsave(hba->host->host_lock, flags); hba->uic_async_done = &uic_async_done; - ret = __ufshcd_send_uic_cmd(hba, cmd); - spin_unlock_irqrestore(hba->host->host_lock, flags); - if (ret) { - dev_err(hba->dev, - "pwr ctrl cmd 0x%x with mode 0x%x uic error %d\n", - cmd->command, cmd->argument3, ret); - goto out; + if (ufshcd_readl(hba, REG_INTERRUPT_ENABLE) & UIC_COMMAND_COMPL) { + ufshcd_disable_intr(hba, UIC_COMMAND_COMPL); + /* + * Make sure UIC command completion interrupt is disabled before + * issuing UIC command. + */ + wmb(); + reenable_intr = true; } - ret = ufshcd_wait_for_uic_cmd(hba, cmd); + ret = __ufshcd_send_uic_cmd(hba, cmd, false); + spin_unlock_irqrestore(hba->host->host_lock, flags); if (ret) { dev_err(hba->dev, "pwr ctrl cmd 0x%x with mode 0x%x uic error %d\n", @@ -2272,12 +4316,83 @@ cmd->command, status); ret = (status != PWR_OK) ? status : -1; } + ufshcd_dme_cmd_log(hba, "cmp2", hba->active_uic_cmd->command); + out: + if (ret) { + ufsdbg_set_err_state(hba); + ufshcd_print_host_state(hba); + ufshcd_print_pwr_info(hba); + ufshcd_print_host_regs(hba); + ufshcd_print_cmd_log(hba); + } + + ufshcd_save_tstamp_of_last_dme_cmd(hba); spin_lock_irqsave(hba->host->host_lock, flags); + hba->active_uic_cmd = NULL; hba->uic_async_done = NULL; + if (reenable_intr) + ufshcd_enable_intr(hba, UIC_COMMAND_COMPL); spin_unlock_irqrestore(hba->host->host_lock, flags); mutex_unlock(&hba->uic_cmd_mutex); + return ret; +} +int ufshcd_wait_for_doorbell_clr(struct ufs_hba *hba, u64 wait_timeout_us) +{ + unsigned long flags; + int ret = 0; + u32 tm_doorbell; + u32 tr_doorbell; + bool timeout = false, do_last_check = false; + ktime_t start; + + ufshcd_hold_all(hba); + spin_lock_irqsave(hba->host->host_lock, flags); + /* + * Wait for all the outstanding tasks/transfer requests. + * Verify by checking the doorbell registers are clear. + */ + start = ktime_get(); + do { + if (hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL) { + ret = -EBUSY; + goto out; + } + + tm_doorbell = ufshcd_readl(hba, REG_UTP_TASK_REQ_DOOR_BELL); + tr_doorbell = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL); + if (!tm_doorbell && !tr_doorbell) { + timeout = false; + break; + } else if (do_last_check) { + break; + } + + spin_unlock_irqrestore(hba->host->host_lock, flags); + schedule(); + if (ktime_to_us(ktime_sub(ktime_get(), start)) > + wait_timeout_us) { + timeout = true; + /* + * We might have scheduled out for long time so make + * sure to check if doorbells are cleared by this time + * or not. + */ + do_last_check = true; + } + spin_lock_irqsave(hba->host->host_lock, flags); + } while (tm_doorbell || tr_doorbell); + + if (timeout) { + dev_err(hba->dev, + "%s: timedout waiting for doorbell to clear (tm=0x%x, tr=0x%x)\n", + __func__, tm_doorbell, tr_doorbell); + ret = -EBUSY; + } +out: + spin_unlock_irqrestore(hba->host->host_lock, flags); + ufshcd_release_all(hba); return ret; } @@ -2307,33 +4422,149 @@ uic_cmd.command = UIC_CMD_DME_SET; uic_cmd.argument1 = UIC_ARG_MIB(PA_PWRMODE); uic_cmd.argument3 = mode; - ufshcd_hold(hba, false); + hba->ufs_stats.clk_hold.ctx = PWRCTL_CMD_SEND; + ufshcd_hold_all(hba); ret = ufshcd_uic_pwr_ctrl(hba, &uic_cmd); - ufshcd_release(hba); - + hba->ufs_stats.clk_rel.ctx = PWRCTL_CMD_SEND; + ufshcd_release_all(hba); out: return ret; } -static int ufshcd_uic_hibern8_enter(struct ufs_hba *hba) +static int ufshcd_link_recovery(struct ufs_hba *hba) { + int ret = 0; + unsigned long flags; + + /* + * Check if there is any race with fatal error handling. + * If so, wait for it to complete. Even though fatal error + * handling does reset and restore in some cases, don't assume + * anything out of it. We are just avoiding race here. + */ + do { + spin_lock_irqsave(hba->host->host_lock, flags); + if (!(work_pending(&hba->eh_work) || + hba->ufshcd_state == UFSHCD_STATE_RESET)) + break; + spin_unlock_irqrestore(hba->host->host_lock, flags); + dev_dbg(hba->dev, "%s: reset in progress\n", __func__); + flush_work(&hba->eh_work); + } while (1); + + + /* + * we don't know if previous reset had really reset the host controller + * or not. So let's force reset here to be sure. + */ + hba->ufshcd_state = UFSHCD_STATE_ERROR; + hba->force_host_reset = true; + schedule_work(&hba->eh_work); + + /* wait for the reset work to finish */ + do { + if (!(work_pending(&hba->eh_work) || + hba->ufshcd_state == UFSHCD_STATE_RESET)) + break; + spin_unlock_irqrestore(hba->host->host_lock, flags); + dev_dbg(hba->dev, "%s: reset in progress\n", __func__); + flush_work(&hba->eh_work); + spin_lock_irqsave(hba->host->host_lock, flags); + } while (1); + + if (!((hba->ufshcd_state == UFSHCD_STATE_OPERATIONAL) && + ufshcd_is_link_active(hba))) + ret = -ENOLINK; + spin_unlock_irqrestore(hba->host->host_lock, flags); + + return ret; +} + +static int __ufshcd_uic_hibern8_enter(struct ufs_hba *hba) +{ + int ret; struct uic_command uic_cmd = {0}; + ktime_t start = ktime_get(); uic_cmd.command = UIC_CMD_DME_HIBER_ENTER; + ret = ufshcd_uic_pwr_ctrl(hba, &uic_cmd); + trace_ufshcd_profile_hibern8(dev_name(hba->dev), "enter", + ktime_to_us(ktime_sub(ktime_get(), start)), ret); + + /* + * Do full reinit if enter failed or if LINERESET was detected during + * Hibern8 operation. After LINERESET, link moves to default PWM-G1 + * mode hence full reinit is required to move link to HS speeds. + */ + if (ret || hba->full_init_linereset) { + int err; + + hba->full_init_linereset = false; + ufshcd_update_error_stats(hba, UFS_ERR_HIBERN8_ENTER); + dev_err(hba->dev, "%s: hibern8 enter failed. ret = %d", + __func__, ret); + /* + * If link recovery fails then return error code (-ENOLINK) + * returned ufshcd_link_recovery(). + * If link recovery succeeds then return -EAGAIN to attempt + * hibern8 enter retry again. + */ + err = ufshcd_link_recovery(hba); + if (err) { + dev_err(hba->dev, "%s: link recovery failed", __func__); + ret = err; + } else { + ret = -EAGAIN; + } + } else { + dev_dbg(hba->dev, "%s: Hibern8 Enter at %lld us", __func__, + ktime_to_us(ktime_get())); + } + + return ret; +} - return ufshcd_uic_pwr_ctrl(hba, &uic_cmd); +int ufshcd_uic_hibern8_enter(struct ufs_hba *hba) +{ + int ret = 0, retries; + + for (retries = UIC_HIBERN8_ENTER_RETRIES; retries > 0; retries--) { + ret = __ufshcd_uic_hibern8_enter(hba); + if (!ret) + goto out; + else if (ret != -EAGAIN) + /* Unable to recover the link, so no point proceeding */ + BUG(); + } +out: + return ret; } -static int ufshcd_uic_hibern8_exit(struct ufs_hba *hba) +int ufshcd_uic_hibern8_exit(struct ufs_hba *hba) { struct uic_command uic_cmd = {0}; int ret; + ktime_t start = ktime_get(); uic_cmd.command = UIC_CMD_DME_HIBER_EXIT; ret = ufshcd_uic_pwr_ctrl(hba, &uic_cmd); + trace_ufshcd_profile_hibern8(dev_name(hba->dev), "exit", + ktime_to_us(ktime_sub(ktime_get(), start)), ret); + + /* Do full reinit if exit failed */ if (ret) { - ufshcd_set_link_off(hba); - ret = ufshcd_host_reset_and_restore(hba); + ufshcd_update_error_stats(hba, UFS_ERR_HIBERN8_EXIT); + dev_err(hba->dev, "%s: hibern8 exit failed. ret = %d", + __func__, ret); + ret = ufshcd_link_recovery(hba); + /* Unable to recover the link, so no point proceeding */ + if (ret) + BUG(); + } else { + dev_dbg(hba->dev, "%s: Hibern8 Exit at %lld us", __func__, + ktime_to_us(ktime_get())); + hba->ufs_stats.last_hibern8_exit_tstamp = ktime_get(); + hba->ufs_stats.hibern8_exit_cnt++; } return ret; @@ -2366,8 +4597,8 @@ if (hba->max_pwr_info.is_valid) return 0; - pwr_info->pwr_tx = FASTAUTO_MODE; - pwr_info->pwr_rx = FASTAUTO_MODE; + pwr_info->pwr_tx = FAST_MODE; + pwr_info->pwr_rx = FAST_MODE; pwr_info->hs_rate = PA_HS_MODE_B; /* Get the connected lane count */ @@ -2398,7 +4629,7 @@ __func__, pwr_info->gear_rx); return -EINVAL; } - pwr_info->pwr_rx = SLOWAUTO_MODE; + pwr_info->pwr_rx = SLOW_MODE; } ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_MAXRXHSGEAR), @@ -2411,20 +4642,21 @@ __func__, pwr_info->gear_tx); return -EINVAL; } - pwr_info->pwr_tx = SLOWAUTO_MODE; + pwr_info->pwr_tx = SLOW_MODE; } hba->max_pwr_info.is_valid = true; return 0; } -static int ufshcd_change_power_mode(struct ufs_hba *hba, +int ufshcd_change_power_mode(struct ufs_hba *hba, struct ufs_pa_layer_attr *pwr_mode) { - int ret; + int ret = 0; /* if already configured to the requested pwr_mode */ - if (pwr_mode->gear_rx == hba->pwr_info.gear_rx && + if (!hba->restore_needed && + pwr_mode->gear_rx == hba->pwr_info.gear_rx && pwr_mode->gear_tx == hba->pwr_info.gear_tx && pwr_mode->lane_rx == hba->pwr_info.lane_rx && pwr_mode->lane_tx == hba->pwr_info.lane_tx && @@ -2435,6 +4667,10 @@ return 0; } + ufsdbg_error_inject_dispatcher(hba, ERR_INJECT_PWR_CHANGE, 0, &ret); + if (ret) + return ret; + /* * Configure attributes for power mode change with below. * - PA_RXGEAR, PA_ACTIVERXDATALANES, PA_RXTERMINATION, @@ -2466,10 +4702,25 @@ ufshcd_dme_set(hba, UIC_ARG_MIB(PA_HSSERIES), pwr_mode->hs_rate); + ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA0), + DL_FC0ProtectionTimeOutVal_Default); + ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA1), + DL_TC0ReplayTimeOutVal_Default); + ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA2), + DL_AFC0ReqTimeOutVal_Default); + + ufshcd_dme_set(hba, UIC_ARG_MIB(DME_LocalFC0ProtectionTimeOutVal), + DL_FC0ProtectionTimeOutVal_Default); + ufshcd_dme_set(hba, UIC_ARG_MIB(DME_LocalTC0ReplayTimeOutVal), + DL_TC0ReplayTimeOutVal_Default); + ufshcd_dme_set(hba, UIC_ARG_MIB(DME_LocalAFC0ReqTimeOutVal), + DL_AFC0ReqTimeOutVal_Default); + ret = ufshcd_uic_change_pwr_mode(hba, pwr_mode->pwr_rx << 4 | pwr_mode->pwr_tx); if (ret) { + ufshcd_update_error_stats(hba, UFS_ERR_POWER_MODE_CHANGE); dev_err(hba->dev, "%s: power mode change failed %d\n", __func__, ret); } else { @@ -2478,6 +4729,7 @@ memcpy(&hba->pwr_info, pwr_mode, sizeof(struct ufs_pa_layer_attr)); + hba->ufs_stats.power_mode_change_cnt++; } return ret; @@ -2501,6 +4753,8 @@ memcpy(&final_params, desired_pwr_mode, sizeof(final_params)); ret = ufshcd_change_power_mode(hba, &final_params); + if (!ret) + ufshcd_print_pwr_info(hba); return ret; } @@ -2513,17 +4767,12 @@ */ static int ufshcd_complete_dev_init(struct ufs_hba *hba) { - int i, retries, err = 0; + int i; + int err; bool flag_res = 1; - for (retries = QUERY_REQ_RETRIES; retries > 0; retries--) { - /* Set the fDeviceInit flag */ - err = ufshcd_query_flag(hba, UPIU_QUERY_OPCODE_SET_FLAG, + err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_SET_FLAG, QUERY_FLAG_IDN_FDEVICEINIT, NULL); - if (!err || err == -ETIMEDOUT) - break; - dev_dbg(hba->dev, "%s: error %d retrying\n", __func__, err); - } if (err) { dev_err(hba->dev, "%s setting fDeviceInit flag failed with error %d\n", @@ -2531,18 +4780,11 @@ goto out; } - /* poll for max. 100 iterations for fDeviceInit flag to clear */ - for (i = 0; i < 100 && !err && flag_res; i++) { - for (retries = QUERY_REQ_RETRIES; retries > 0; retries--) { - err = ufshcd_query_flag(hba, - UPIU_QUERY_OPCODE_READ_FLAG, + /* poll for max. 1000 iterations for fDeviceInit flag to clear */ + for (i = 0; i < 1000 && !err && flag_res; i++) + err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_READ_FLAG, QUERY_FLAG_IDN_FDEVICEINIT, &flag_res); - if (!err || err == -ETIMEDOUT) - break; - dev_dbg(hba->dev, "%s: error %d retrying\n", __func__, - err); - } - } + if (err) dev_err(hba->dev, "%s reading fDeviceInit flag failed with error %d\n", @@ -2563,7 +4805,7 @@ * To bring UFS host controller to operational state, * 1. Enable required interrupts * 2. Configure interrupt aggregation - * 3. Program UTRL and UTMRL base addres + * 3. Program UTRL and UTMRL base address * 4. Configure run-stop-registers * * Returns 0 on success, non-zero value on failure @@ -2593,8 +4835,13 @@ REG_UTP_TASK_REQ_LIST_BASE_H); /* + * Make sure base address and interrupt setup are updated before + * enabling the run/stop registers below. + */ + wmb(); + + /* * UCRDY, UTMRLDY and UTRLRDY bits must be 1 - * DEI, HEI bits must be 0 */ reg = ufshcd_readl(hba, REG_CONTROLLER_STATUS); if (!(ufshcd_get_lists_status(reg))) { @@ -2611,6 +4858,23 @@ } /** + * ufshcd_hba_stop - Send controller to reset state + * @hba: per adapter instance + * @can_sleep: perform sleep or just spin + */ +static inline void ufshcd_hba_stop(struct ufs_hba *hba, bool can_sleep) +{ + int err; + + ufshcd_writel(hba, CONTROLLER_DISABLE, REG_CONTROLLER_ENABLE); + err = ufshcd_wait_for_register(hba, REG_CONTROLLER_ENABLE, + CONTROLLER_ENABLE, CONTROLLER_DISABLE, + 10, 1, can_sleep); + if (err) + dev_err(hba->dev, "%s: Controller disable failed\n", __func__); +} + +/** * ufshcd_hba_enable - initialize the controller * @hba: per adapter instance * @@ -2630,18 +4894,9 @@ * development and testing of this driver. msleep can be changed to * mdelay and retry count can be reduced based on the controller. */ - if (!ufshcd_is_hba_active(hba)) { - + if (!ufshcd_is_hba_active(hba)) /* change controller state to "reset state" */ - ufshcd_hba_stop(hba); - - /* - * This delay is based on the testing done with UFS host - * controller FPGA. The delay can be changed based on the - * host controller used. - */ - msleep(5); - } + ufshcd_hba_stop(hba, true); /* UniPro link is disabled at this point */ ufshcd_set_link_off(hba); @@ -2715,6 +4970,11 @@ return err; } +static inline int ufshcd_disable_host_tx_lcc(struct ufs_hba *hba) +{ + return ufshcd_disable_tx_lcc(hba, false); +} + static inline int ufshcd_disable_device_tx_lcc(struct ufs_hba *hba) { return ufshcd_disable_tx_lcc(hba, true); @@ -2730,14 +4990,26 @@ { int ret; int retries = DME_LINKSTARTUP_RETRIES; + bool link_startup_again = false; + + /* + * If UFS device isn't active then we will have to issue link startup + * 2 times to make sure the device state move to active. + */ + if (!ufshcd_is_ufs_dev_active(hba)) + link_startup_again = true; +link_startup: do { ufshcd_vops_link_startup_notify(hba, PRE_CHANGE); ret = ufshcd_dme_link_startup(hba); + if (ret) + ufshcd_update_error_stats(hba, UFS_ERR_LINKSTARTUP); /* check if device is detected by inter-connect layer */ if (!ret && !ufshcd_is_device_present(hba)) { + ufshcd_update_error_stats(hba, UFS_ERR_LINKSTARTUP); dev_err(hba->dev, "%s: Device not present\n", __func__); ret = -ENXIO; goto out; @@ -2756,12 +5028,28 @@ /* failed to get the link up... retire */ goto out; + if (link_startup_again) { + link_startup_again = false; + retries = DME_LINKSTARTUP_RETRIES; + goto link_startup; + } + + /* Mark that link is up in PWM-G1, 1-lane, SLOW-AUTO mode */ + ufshcd_init_pwr_info(hba); + ufshcd_print_pwr_info(hba); + if (hba->quirks & UFSHCD_QUIRK_BROKEN_LCC) { ret = ufshcd_disable_device_tx_lcc(hba); if (ret) goto out; } + if (hba->dev_quirks & UFS_DEVICE_QUIRK_BROKEN_LCC) { + ret = ufshcd_disable_host_tx_lcc(hba); + if (ret) + goto out; + } + /* Include any host controller configuration via UIC commands */ ret = ufshcd_vops_link_startup_notify(hba, POST_CHANGE); if (ret) @@ -2769,8 +5057,12 @@ ret = ufshcd_make_hba_operational(hba); out: - if (ret) + if (ret) { dev_err(hba->dev, "link startup failed %d\n", ret); + ufshcd_print_host_state(hba); + ufshcd_print_pwr_info(hba); + ufshcd_print_host_regs(hba); + } return ret; } @@ -2789,7 +5081,7 @@ int err = 0; int retries; - ufshcd_hold(hba, false); + ufshcd_hold_all(hba); mutex_lock(&hba->dev_cmd.lock); for (retries = NOP_OUT_RETRIES; retries > 0; retries--) { err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_NOP, @@ -2801,7 +5093,7 @@ dev_dbg(hba->dev, "%s: error %d retrying\n", __func__, err); } mutex_unlock(&hba->dev_cmd.lock); - ufshcd_release(hba); + ufshcd_release_all(hba); if (err) dev_err(hba->dev, "%s: NOP OUT failed %d\n", __func__, err); @@ -2923,6 +5215,8 @@ /* REPORT SUPPORTED OPERATION CODES is not supported */ sdev->no_report_opcodes = 1; + /* WRITE_SAME command is not supported*/ + sdev->no_write_same = 1; ufshcd_set_queue_depth(sdev); @@ -2958,6 +5252,9 @@ blk_queue_update_dma_pad(q, PRDT_DATA_BYTE_COUNT_PAD - 1); blk_queue_max_segment_size(q, PRDT_DATA_BYTE_COUNT_MAX); + sdev->autosuspend_delay = UFSHCD_AUTO_SUSPEND_DELAY_MS; + sdev->use_rpm_auto = 1; + return 0; } @@ -3067,6 +5364,7 @@ int result = 0; int scsi_status; int ocs; + bool print_prdt; /* overall command status of utrd */ ocs = ufshcd_get_tr_ocs(lrbp); @@ -3074,7 +5372,7 @@ switch (ocs) { case OCS_SUCCESS: result = ufshcd_get_req_rsp(lrbp->ucd_rsp_ptr); - + hba->ufs_stats.last_hibern8_exit_tstamp = ktime_set(0, 0); switch (result) { case UPIU_TRANSACTION_RESPONSE: /* @@ -3090,7 +5388,20 @@ scsi_status = result & MASK_SCSI_STATUS; result = ufshcd_scsi_cmd_status(lrbp, scsi_status); - if (ufshcd_is_exception_event(lrbp->ucd_rsp_ptr)) + /* + * Currently we are only supporting BKOPs exception + * events hence we can ignore BKOPs exception event + * during power management callbacks. BKOPs exception + * event is not expected to be raised in runtime suspend + * callback as it allows the urgent bkops. + * During system suspend, we are anyway forcefully + * disabling the bkops and if urgent bkops is needed + * it will be enabled on system resume. Long term + * solution could be to abort the system suspend if + * UFS device needs urgent BKOPs. + */ + if (!hba->pm_op_in_progress && + ufshcd_is_exception_event(lrbp->ucd_rsp_ptr)) schedule_work(&hba->eeh_work); break; case UPIU_TRANSACTION_REJECT_UPIU: @@ -3119,13 +5430,34 @@ case OCS_MISMATCH_RESP_UPIU_SIZE: case OCS_PEER_COMM_FAILURE: case OCS_FATAL_ERROR: + case OCS_DEVICE_FATAL_ERROR: + case OCS_INVALID_CRYPTO_CONFIG: + case OCS_GENERAL_CRYPTO_ERROR: default: result |= DID_ERROR << 16; dev_err(hba->dev, - "OCS error from controller = %x\n", ocs); + "OCS error from controller = %x for tag %d\n", + ocs, lrbp->task_tag); + /* + * This is called in interrupt context, hence avoid sleep + * while printing debug registers. Also print only the minimum + * debug registers needed to debug OCS failure. + */ + __ufshcd_print_host_regs(hba, true); + ufshcd_print_host_state(hba); break; } /* end of switch */ + if ((host_byte(result) != DID_OK) && !hba->silence_err_logs) { + print_prdt = (ocs == OCS_INVALID_PRDT_ATTR || + ocs == OCS_MISMATCH_DATA_BUF_SIZE); + ufshcd_print_trs(hba, 1 << lrbp->task_tag, print_prdt); + } + + if ((host_byte(result) == DID_ERROR) || + (host_byte(result) == DID_ABORT)) + ufsdbg_set_err_state(hba); + return result; } @@ -3133,65 +5465,180 @@ * ufshcd_uic_cmd_compl - handle completion of uic command * @hba: per adapter instance * @intr_status: interrupt status generated by the controller + * + * Returns + * IRQ_HANDLED - If interrupt is valid + * IRQ_NONE - If invalid interrupt */ -static void ufshcd_uic_cmd_compl(struct ufs_hba *hba, u32 intr_status) +static irqreturn_t ufshcd_uic_cmd_compl(struct ufs_hba *hba, u32 intr_status) { + irqreturn_t retval = IRQ_NONE; + if ((intr_status & UIC_COMMAND_COMPL) && hba->active_uic_cmd) { hba->active_uic_cmd->argument2 |= ufshcd_get_uic_cmd_result(hba); hba->active_uic_cmd->argument3 = ufshcd_get_dme_attr_val(hba); complete(&hba->active_uic_cmd->done); + retval = IRQ_HANDLED; } - if ((intr_status & UFSHCD_UIC_PWR_MASK) && hba->uic_async_done) + if (intr_status & UFSHCD_UIC_PWR_MASK) { + if (hba->uic_async_done) { complete(hba->uic_async_done); + retval = IRQ_HANDLED; + } else if (ufshcd_is_auto_hibern8_supported(hba)) { + /* + * If uic_async_done flag is not set then this + * is an Auto hibern8 err interrupt. + * Perform a host reset followed by a full + * link recovery. + */ + hba->ufshcd_state = UFSHCD_STATE_ERROR; + hba->force_host_reset = true; + dev_err(hba->dev, "%s: Auto Hibern8 %s failed - status: 0x%08x, upmcrs: 0x%08x\n", + __func__, (intr_status & UIC_HIBERNATE_ENTER) ? + "Enter" : "Exit", + intr_status, ufshcd_get_upmcrs(hba)); + __ufshcd_print_host_regs(hba, true); + ufshcd_print_host_state(hba); + schedule_work(&hba->eh_work); + retval = IRQ_HANDLED; + } + } + return retval; } /** - * ufshcd_transfer_req_compl - handle SCSI and query command completion + * ufshcd_abort_outstanding_requests - abort all outstanding transfer requests. * @hba: per adapter instance + * @result: error result to inform scsi layer about */ -static void ufshcd_transfer_req_compl(struct ufs_hba *hba) +void ufshcd_abort_outstanding_transfer_requests(struct ufs_hba *hba, int result) { + u8 index; struct ufshcd_lrb *lrbp; struct scsi_cmnd *cmd; - unsigned long completed_reqs; - u32 tr_doorbell; - int result; - int index; - /* Resetting interrupt aggregation counters first and reading the - * DOOR_BELL afterward allows us to handle all the completed requests. - * In order to prevent other interrupts starvation the DB is read once - * after reset. The down side of this solution is the possibility of - * false interrupt if device completes another request after resetting - * aggregation and before reading the DB. - */ - if (ufshcd_is_intr_aggr_allowed(hba)) - ufshcd_reset_intr_aggr(hba); + if (!hba->outstanding_reqs) + return; - tr_doorbell = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL); - completed_reqs = tr_doorbell ^ hba->outstanding_reqs; + for_each_set_bit(index, &hba->outstanding_reqs, hba->nutrs) { + lrbp = &hba->lrb[index]; + cmd = lrbp->cmd; + if (cmd) { + ufshcd_cond_add_cmd_trace(hba, index, "failed"); + ufshcd_update_error_stats(hba, + UFS_ERR_INT_FATAL_ERRORS); + scsi_dma_unmap(cmd); + cmd->result = result; + /* Clear pending transfer requests */ + ufshcd_clear_cmd(hba, index); + ufshcd_outstanding_req_clear(hba, index); + clear_bit_unlock(index, &hba->lrb_in_use); + lrbp->complete_time_stamp = ktime_get(); + update_req_stats(hba, lrbp); + /* Mark completed command as NULL in LRB */ + lrbp->cmd = NULL; + ufshcd_release_all(hba); + if (cmd->request) { + /* + * As we are accessing the "request" structure, + * this must be called before calling + * ->scsi_done() callback. + */ + ufshcd_vops_pm_qos_req_end(hba, cmd->request, + true); + ufshcd_vops_crypto_engine_cfg_end(hba, + lrbp, cmd->request); + } + /* Do not touch lrbp after scsi done */ + cmd->scsi_done(cmd); + } else if (lrbp->command_type == UTP_CMD_TYPE_DEV_MANAGE) { + if (hba->dev_cmd.complete) { + ufshcd_cond_add_cmd_trace(hba, index, + "dev_failed"); + ufshcd_outstanding_req_clear(hba, index); + complete(hba->dev_cmd.complete); + } + } + if (ufshcd_is_clkscaling_supported(hba)) + hba->clk_scaling.active_reqs--; + } +} + +/** + * __ufshcd_transfer_req_compl - handle SCSI and query command completion + * @hba: per adapter instance + * @completed_reqs: requests to complete + */ +static void __ufshcd_transfer_req_compl(struct ufs_hba *hba, + unsigned long completed_reqs) +{ + struct ufshcd_lrb *lrbp; + struct scsi_cmnd *cmd; + int result; + int index; + struct request *req; for_each_set_bit(index, &completed_reqs, hba->nutrs) { lrbp = &hba->lrb[index]; cmd = lrbp->cmd; if (cmd) { + ufshcd_cond_add_cmd_trace(hba, index, "complete"); + ufshcd_update_tag_stats_completion(hba, cmd); result = ufshcd_transfer_rsp_status(hba, lrbp); scsi_dma_unmap(cmd); cmd->result = result; + clear_bit_unlock(index, &hba->lrb_in_use); + lrbp->complete_time_stamp = ktime_get(); + update_req_stats(hba, lrbp); /* Mark completed command as NULL in LRB */ lrbp->cmd = NULL; + hba->ufs_stats.clk_rel.ctx = XFR_REQ_COMPL; + __ufshcd_release(hba, false); + __ufshcd_hibern8_release(hba, false); + if (cmd->request) { + /* + * As we are accessing the "request" structure, + * this must be called before calling + * ->scsi_done() callback. + */ + ufshcd_vops_pm_qos_req_end(hba, cmd->request, + false); + ufshcd_vops_crypto_engine_cfg_end(hba, + lrbp, cmd->request); + } + clear_bit_unlock(index, &hba->lrb_in_use); + req = cmd->request; + if (req) { + /* Update IO svc time latency histogram */ + if (req->lat_hist_enabled) { + ktime_t completion; + u_int64_t delta_us; + + completion = ktime_get(); + delta_us = ktime_us_delta(completion, + req->lat_hist_io_start); + blk_update_latency_hist( + (rq_data_dir(req) == READ) ? + &hba->io_lat_read : + &hba->io_lat_write, delta_us); + } + } /* Do not touch lrbp after scsi done */ cmd->scsi_done(cmd); - __ufshcd_release(hba); } else if (lrbp->command_type == UTP_CMD_TYPE_DEV_MANAGE) { - if (hba->dev_cmd.complete) + if (hba->dev_cmd.complete) { + ufshcd_cond_add_cmd_trace(hba, index, + "dcmp"); complete(hba->dev_cmd.complete); } } + if (ufshcd_is_clkscaling_supported(hba)) + hba->clk_scaling.active_reqs--; + } /* clear corresponding bits of completed commands */ hba->outstanding_reqs ^= completed_reqs; @@ -3203,6 +5650,40 @@ } /** + * ufshcd_transfer_req_compl - handle SCSI and query command completion + * @hba: per adapter instance + * + * Returns + * IRQ_HANDLED - If interrupt is valid + * IRQ_NONE - If invalid interrupt + */ +static irqreturn_t ufshcd_transfer_req_compl(struct ufs_hba *hba) +{ + unsigned long completed_reqs; + u32 tr_doorbell; + + /* Resetting interrupt aggregation counters first and reading the + * DOOR_BELL afterward allows us to handle all the completed requests. + * In order to prevent other interrupts starvation the DB is read once + * after reset. The down side of this solution is the possibility of + * false interrupt if device completes another request after resetting + * aggregation and before reading the DB. + */ + if (ufshcd_is_intr_aggr_allowed(hba)) + ufshcd_reset_intr_aggr(hba); + + tr_doorbell = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL); + completed_reqs = tr_doorbell ^ hba->outstanding_reqs; + + if (completed_reqs) { + __ufshcd_transfer_req_compl(hba, completed_reqs); + return IRQ_HANDLED; + } else { + return IRQ_NONE; + } +} + +/** * ufshcd_disable_ee - disable exception event * @hba: per-adapter instance * @mask: exception event to disable @@ -3222,7 +5703,7 @@ val = hba->ee_ctrl_mask & ~mask; val &= 0xFFFF; /* 2 bytes */ - err = ufshcd_query_attr(hba, UPIU_QUERY_OPCODE_WRITE_ATTR, + err = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_WRITE_ATTR, QUERY_ATTR_IDN_EE_CONTROL, 0, 0, &val); if (!err) hba->ee_ctrl_mask &= ~mask; @@ -3250,7 +5731,7 @@ val = hba->ee_ctrl_mask | mask; val &= 0xFFFF; /* 2 bytes */ - err = ufshcd_query_attr(hba, UPIU_QUERY_OPCODE_WRITE_ATTR, + err = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_WRITE_ATTR, QUERY_ATTR_IDN_EE_CONTROL, 0, 0, &val); if (!err) hba->ee_ctrl_mask |= mask; @@ -3276,7 +5757,7 @@ if (hba->auto_bkops_enabled) goto out; - err = ufshcd_query_flag(hba, UPIU_QUERY_OPCODE_SET_FLAG, + err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_SET_FLAG, QUERY_FLAG_IDN_BKOPS_EN, NULL); if (err) { dev_err(hba->dev, "%s: failed to enable bkops %d\n", @@ -3285,6 +5766,7 @@ } hba->auto_bkops_enabled = true; + trace_ufshcd_auto_bkops_state(dev_name(hba->dev), 1); /* No need of URGENT_BKOPS exception from the device */ err = ufshcd_disable_ee(hba, MASK_EE_URGENT_BKOPS); @@ -3325,7 +5807,7 @@ goto out; } - err = ufshcd_query_flag(hba, UPIU_QUERY_OPCODE_CLEAR_FLAG, + err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_CLEAR_FLAG, QUERY_FLAG_IDN_BKOPS_EN, NULL); if (err) { dev_err(hba->dev, "%s: failed to disable bkops %d\n", @@ -3335,6 +5817,7 @@ } hba->auto_bkops_enabled = false; + trace_ufshcd_auto_bkops_state(dev_name(hba->dev), 0); out: return err; } @@ -3363,7 +5846,7 @@ static inline int ufshcd_get_bkops_status(struct ufs_hba *hba, u32 *status) { - return ufshcd_query_attr(hba, UPIU_QUERY_OPCODE_READ_ATTR, + return ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR, QUERY_ATTR_IDN_BKOPS_STATUS, 0, 0, status); } @@ -3421,15 +5904,52 @@ */ static int ufshcd_urgent_bkops(struct ufs_hba *hba) { - return ufshcd_bkops_ctrl(hba, BKOPS_STATUS_PERF_IMPACT); + return ufshcd_bkops_ctrl(hba, hba->urgent_bkops_lvl); } static inline int ufshcd_get_ee_status(struct ufs_hba *hba, u32 *status) { - return ufshcd_query_attr(hba, UPIU_QUERY_OPCODE_READ_ATTR, + return ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR, QUERY_ATTR_IDN_EE_STATUS, 0, 0, status); } +static void ufshcd_bkops_exception_event_handler(struct ufs_hba *hba) +{ + int err; + u32 curr_status = 0; + + if (hba->is_urgent_bkops_lvl_checked) + goto enable_auto_bkops; + + err = ufshcd_get_bkops_status(hba, &curr_status); + if (err) { + dev_err(hba->dev, "%s: failed to get BKOPS status %d\n", + __func__, err); + goto out; + } + + /* + * We are seeing that some devices are raising the urgent bkops + * exception events even when BKOPS status doesn't indicate performace + * impacted or critical. Handle these device by determining their urgent + * bkops status at runtime. + */ + if (curr_status < BKOPS_STATUS_PERF_IMPACT) { + dev_err(hba->dev, "%s: device raised urgent BKOPS exception for bkops status %d\n", + __func__, curr_status); + /* update the current status as the urgent bkops level */ + hba->urgent_bkops_lvl = curr_status; + hba->is_urgent_bkops_lvl_checked = true; + } + +enable_auto_bkops: + err = ufshcd_enable_auto_bkops(hba); +out: + if (err < 0) + dev_err(hba->dev, "%s: failed to handle urgent bkops %d\n", + __func__, err); +} + /** * ufshcd_exception_event_handler - handle exceptions raised by device * @work: pointer to work data @@ -3445,6 +5965,7 @@ hba = container_of(work, struct ufs_hba, eeh_work); pm_runtime_get_sync(hba->dev); + ufshcd_scsi_block_requests(hba); err = ufshcd_get_ee_status(hba, &status); if (err) { dev_err(hba->dev, "%s: failed to get exception status %d\n", @@ -3453,17 +5974,117 @@ } status &= hba->ee_ctrl_mask; - if (status & MASK_EE_URGENT_BKOPS) { - err = ufshcd_urgent_bkops(hba); - if (err < 0) - dev_err(hba->dev, "%s: failed to handle urgent bkops %d\n", - __func__, err); - } + + if (status & MASK_EE_URGENT_BKOPS) + ufshcd_bkops_exception_event_handler(hba); + out: - pm_runtime_put_sync(hba->dev); + ufshcd_scsi_unblock_requests(hba); + pm_runtime_put(hba->dev); return; } +/* Complete requests that have door-bell cleared */ +static void ufshcd_complete_requests(struct ufs_hba *hba) +{ + ufshcd_transfer_req_compl(hba); + ufshcd_tmc_handler(hba); +} + +/** + * ufshcd_quirk_dl_nac_errors - This function checks if error handling is + * to recover from the DL NAC errors or not. + * @hba: per-adapter instance + * + * Returns true if error handling is required, false otherwise + */ +static bool ufshcd_quirk_dl_nac_errors(struct ufs_hba *hba) +{ + unsigned long flags; + bool err_handling = true; + + spin_lock_irqsave(hba->host->host_lock, flags); + /* + * UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS only workaround the + * device fatal error and/or DL NAC & REPLAY timeout errors. + */ + if (hba->saved_err & (CONTROLLER_FATAL_ERROR | SYSTEM_BUS_FATAL_ERROR)) + goto out; + + if ((hba->saved_err & DEVICE_FATAL_ERROR) || + ((hba->saved_err & UIC_ERROR) && + (hba->saved_uic_err & UFSHCD_UIC_DL_TCx_REPLAY_ERROR))) { + /* + * we have to do error recovery but atleast silence the error + * logs. + */ + hba->silence_err_logs = true; + goto out; + } + + if ((hba->saved_err & UIC_ERROR) && + (hba->saved_uic_err & UFSHCD_UIC_DL_NAC_RECEIVED_ERROR)) { + int err; + /* + * wait for 50ms to see if we can get any other errors or not. + */ + spin_unlock_irqrestore(hba->host->host_lock, flags); + msleep(50); + spin_lock_irqsave(hba->host->host_lock, flags); + + /* + * now check if we have got any other severe errors other than + * DL NAC error? + */ + if ((hba->saved_err & INT_FATAL_ERRORS) || + ((hba->saved_err & UIC_ERROR) && + (hba->saved_uic_err & ~UFSHCD_UIC_DL_NAC_RECEIVED_ERROR))) { + if (((hba->saved_err & INT_FATAL_ERRORS) == + DEVICE_FATAL_ERROR) || (hba->saved_uic_err & + ~UFSHCD_UIC_DL_NAC_RECEIVED_ERROR)) + hba->silence_err_logs = true; + goto out; + } + + /* + * As DL NAC is the only error received so far, send out NOP + * command to confirm if link is still active or not. + * - If we don't get any response then do error recovery. + * - If we get response then clear the DL NAC error bit. + */ + + /* silence the error logs from NOP command */ + hba->silence_err_logs = true; + spin_unlock_irqrestore(hba->host->host_lock, flags); + err = ufshcd_verify_dev_init(hba); + spin_lock_irqsave(hba->host->host_lock, flags); + hba->silence_err_logs = false; + + if (err) { + hba->silence_err_logs = true; + goto out; + } + + /* Link seems to be alive hence ignore the DL NAC errors */ + if (hba->saved_uic_err == UFSHCD_UIC_DL_NAC_RECEIVED_ERROR) + hba->saved_err &= ~UIC_ERROR; + /* clear NAC error */ + hba->saved_uic_err &= ~UFSHCD_UIC_DL_NAC_RECEIVED_ERROR; + if (!hba->saved_uic_err) { + err_handling = false; + goto out; + } + /* + * there seems to be some errors other than NAC, so do error + * recovery + */ + hba->silence_err_logs = true; + } +out: + spin_unlock_irqrestore(hba->host->host_lock, flags); + return err_handling; +} + /** * ufshcd_err_handler - handle UFS errors that require s/w attention * @work: pointer to work structure @@ -3472,51 +6093,149 @@ { struct ufs_hba *hba; unsigned long flags; - u32 err_xfer = 0; - u32 err_tm = 0; + bool err_xfer = false, err_tm = false; int err = 0; int tag; + bool needs_reset = false; + bool clks_enabled = false; hba = container_of(work, struct ufs_hba, eh_work); - pm_runtime_get_sync(hba->dev); - ufshcd_hold(hba, false); - spin_lock_irqsave(hba->host->host_lock, flags); - if (hba->ufshcd_state == UFSHCD_STATE_RESET) { - spin_unlock_irqrestore(hba->host->host_lock, flags); + ufsdbg_set_err_state(hba); + + if (hba->ufshcd_state == UFSHCD_STATE_RESET) goto out; + + /* + * Make sure the clocks are ON before we proceed with err + * handling. For the majority of cases err handler would be + * run with clocks ON. There is a possibility that the err + * handler was scheduled due to auto hibern8 error interrupt, + * in which case the clocks could be gated or be in the + * process of gating when the err handler runs. + */ + if (unlikely((hba->clk_gating.state != CLKS_ON) && + ufshcd_is_auto_hibern8_supported(hba))) { + spin_unlock_irqrestore(hba->host->host_lock, flags); + hba->ufs_stats.clk_hold.ctx = ERR_HNDLR_WORK; + ufshcd_hold(hba, false); + spin_lock_irqsave(hba->host->host_lock, flags); + clks_enabled = true; } hba->ufshcd_state = UFSHCD_STATE_RESET; ufshcd_set_eh_in_progress(hba); /* Complete requests that have door-bell cleared by h/w */ - ufshcd_transfer_req_compl(hba); - ufshcd_tmc_handler(hba); + ufshcd_complete_requests(hba); + + if (hba->dev_quirks & UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS) { + bool ret; + + spin_unlock_irqrestore(hba->host->host_lock, flags); + /* release the lock as ufshcd_quirk_dl_nac_errors() may sleep */ + ret = ufshcd_quirk_dl_nac_errors(hba); + spin_lock_irqsave(hba->host->host_lock, flags); + if (!ret) + goto skip_err_handling; + } + + /* + * Dump controller state before resetting. Transfer requests state + * will be dump as part of the request completion. + */ + if (hba->saved_err & (INT_FATAL_ERRORS | UIC_ERROR)) { + dev_err(hba->dev, "%s: saved_err 0x%x saved_uic_err 0x%x", + __func__, hba->saved_err, hba->saved_uic_err); + if (!hba->silence_err_logs) { + /* release lock as print host regs sleeps */ spin_unlock_irqrestore(hba->host->host_lock, flags); + ufshcd_print_host_regs(hba); + ufshcd_print_host_state(hba); + ufshcd_print_pwr_info(hba); + ufshcd_print_tmrs(hba, hba->outstanding_tasks); + ufshcd_print_cmd_log(hba); + spin_lock_irqsave(hba->host->host_lock, flags); + } + } + + if ((hba->saved_err & INT_FATAL_ERRORS) + || hba->saved_ce_err || hba->force_host_reset || + ((hba->saved_err & UIC_ERROR) && + (hba->saved_uic_err & (UFSHCD_UIC_DL_PA_INIT_ERROR | + UFSHCD_UIC_DL_NAC_RECEIVED_ERROR | + UFSHCD_UIC_DL_TCx_REPLAY_ERROR)))) + needs_reset = true; + + /* + * if host reset is required then skip clearing the pending + * transfers forcefully because they will automatically get + * cleared after link startup. + */ + if (needs_reset) + goto skip_pending_xfer_clear; + /* release lock as clear command might sleep */ + spin_unlock_irqrestore(hba->host->host_lock, flags); /* Clear pending transfer requests */ - for_each_set_bit(tag, &hba->outstanding_reqs, hba->nutrs) - if (ufshcd_clear_cmd(hba, tag)) - err_xfer |= 1 << tag; + for_each_set_bit(tag, &hba->outstanding_reqs, hba->nutrs) { + if (ufshcd_clear_cmd(hba, tag)) { + err_xfer = true; + goto lock_skip_pending_xfer_clear; + } + } /* Clear pending task management requests */ - for_each_set_bit(tag, &hba->outstanding_tasks, hba->nutmrs) - if (ufshcd_clear_tm_cmd(hba, tag)) - err_tm |= 1 << tag; + for_each_set_bit(tag, &hba->outstanding_tasks, hba->nutmrs) { + if (ufshcd_clear_tm_cmd(hba, tag)) { + err_tm = true; + goto lock_skip_pending_xfer_clear; + } + } - /* Complete the requests that are cleared by s/w */ +lock_skip_pending_xfer_clear: spin_lock_irqsave(hba->host->host_lock, flags); - ufshcd_transfer_req_compl(hba); - ufshcd_tmc_handler(hba); - spin_unlock_irqrestore(hba->host->host_lock, flags); + /* Complete the requests that are cleared by s/w */ + ufshcd_complete_requests(hba); + + if (err_xfer || err_tm) + needs_reset = true; + +skip_pending_xfer_clear: /* Fatal errors need reset */ - if (err_xfer || err_tm || (hba->saved_err & INT_FATAL_ERRORS) || - ((hba->saved_err & UIC_ERROR) && - (hba->saved_uic_err & UFSHCD_UIC_DL_PA_INIT_ERROR))) { + if (needs_reset) { + unsigned long max_doorbells = (1UL << hba->nutrs) - 1; + + if (hba->saved_err & INT_FATAL_ERRORS) + ufshcd_update_error_stats(hba, + UFS_ERR_INT_FATAL_ERRORS); + if (hba->saved_ce_err) + ufshcd_update_error_stats(hba, UFS_ERR_CRYPTO_ENGINE); + + if (hba->saved_err & UIC_ERROR) + ufshcd_update_error_stats(hba, + UFS_ERR_INT_UIC_ERROR); + + if (err_xfer || err_tm) + ufshcd_update_error_stats(hba, + UFS_ERR_CLEAR_PEND_XFER_TM); + + /* + * ufshcd_reset_and_restore() does the link reinitialization + * which will need atleast one empty doorbell slot to send the + * device management commands (NOP and query commands). + * If there is no slot empty at this moment then free up last + * slot forcefully. + */ + if (hba->outstanding_reqs == max_doorbells) + __ufshcd_transfer_req_compl(hba, + (1UL << (hba->nutrs - 1))); + + spin_unlock_irqrestore(hba->host->host_lock, flags); err = ufshcd_reset_and_restore(hba); + spin_lock_irqsave(hba->host->host_lock, flags); if (err) { dev_err(hba->dev, "%s: reset and restore failed\n", __func__); @@ -3529,76 +6248,223 @@ scsi_report_bus_reset(hba->host, 0); hba->saved_err = 0; hba->saved_uic_err = 0; + hba->saved_ce_err = 0; + hba->force_host_reset = false; + } + +skip_err_handling: + if (!needs_reset) { + hba->ufshcd_state = UFSHCD_STATE_OPERATIONAL; + if (hba->saved_err || hba->saved_uic_err) + dev_err_ratelimited(hba->dev, "%s: exit: saved_err 0x%x saved_uic_err 0x%x", + __func__, hba->saved_err, hba->saved_uic_err); + } + + hba->silence_err_logs = false; + + if (clks_enabled) { + __ufshcd_release(hba, false); + hba->ufs_stats.clk_rel.ctx = ERR_HNDLR_WORK; } +out: ufshcd_clear_eh_in_progress(hba); + spin_unlock_irqrestore(hba->host->host_lock, flags); +} + +static void ufshcd_update_uic_reg_hist(struct ufs_uic_err_reg_hist *reg_hist, + u32 reg) +{ + reg_hist->reg[reg_hist->pos] = reg; + reg_hist->tstamp[reg_hist->pos] = ktime_get(); + reg_hist->pos = (reg_hist->pos + 1) % UIC_ERR_REG_HIST_LENGTH; +} + +static void ufshcd_rls_handler(struct work_struct *work) +{ + struct ufs_hba *hba; + int ret = 0; + u32 mode; + + hba = container_of(work, struct ufs_hba, rls_work); + ufshcd_scsi_block_requests(hba); + pm_runtime_get_sync(hba->dev); + ret = ufshcd_wait_for_doorbell_clr(hba, U64_MAX); + if (ret) { + dev_err(hba->dev, + "Timed out (%d) waiting for DB to clear\n", + ret); + goto out; + } + + ufshcd_dme_get(hba, UIC_ARG_MIB(PA_PWRMODE), &mode); + if (hba->pwr_info.pwr_rx != ((mode >> PWR_RX_OFFSET) & PWR_INFO_MASK)) + hba->restore_needed = true; + + if (hba->pwr_info.pwr_tx != (mode & PWR_INFO_MASK)) + hba->restore_needed = true; + + ufshcd_dme_get(hba, UIC_ARG_MIB(PA_RXGEAR), &mode); + if (hba->pwr_info.gear_rx != mode) + hba->restore_needed = true; + + ufshcd_dme_get(hba, UIC_ARG_MIB(PA_TXGEAR), &mode); + if (hba->pwr_info.gear_tx != mode) + hba->restore_needed = true; + + if (hba->restore_needed) + ret = ufshcd_config_pwr_mode(hba, &(hba->pwr_info)); + + if (ret) + dev_err(hba->dev, "%s: Failed setting power mode, err = %d\n", + __func__, ret); + else + hba->restore_needed = false; out: - scsi_unblock_requests(hba->host); - ufshcd_release(hba); + ufshcd_scsi_unblock_requests(hba); pm_runtime_put_sync(hba->dev); } /** * ufshcd_update_uic_error - check and set fatal UIC error flags. * @hba: per-adapter instance + * + * Returns + * IRQ_HANDLED - If interrupt is valid + * IRQ_NONE - If invalid interrupt */ -static void ufshcd_update_uic_error(struct ufs_hba *hba) +static irqreturn_t ufshcd_update_uic_error(struct ufs_hba *hba) { u32 reg; + irqreturn_t retval = IRQ_NONE; + + /* PHY layer lane error */ + reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_PHY_ADAPTER_LAYER); + if ((reg & UIC_PHY_ADAPTER_LAYER_ERROR) && + (reg & UIC_PHY_ADAPTER_LAYER_ERROR_CODE_MASK)) { + /* + * To know whether this error is fatal or not, DB timeout + * must be checked but this error is handled separately. + */ + dev_dbg(hba->dev, "%s: UIC Lane error reported, reg 0x%x\n", + __func__, reg); + ufshcd_update_uic_reg_hist(&hba->ufs_stats.pa_err, reg); + + /* + * Don't ignore LINERESET indication during hibern8 + * enter operation. + */ + if (reg & UIC_PHY_ADAPTER_LAYER_GENERIC_ERROR) { + struct uic_command *cmd = hba->active_uic_cmd; + + if (cmd) { + if (cmd->command == UIC_CMD_DME_HIBER_ENTER) { + dev_err(hba->dev, "%s: LINERESET during hibern8 enter, reg 0x%x\n", + __func__, reg); + hba->full_init_linereset = true; + } + } + if (!hba->full_init_linereset) + schedule_work(&hba->rls_work); + } + retval |= IRQ_HANDLED; + } /* PA_INIT_ERROR is fatal and needs UIC reset */ reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_DATA_LINK_LAYER); - if (reg & UIC_DATA_LINK_LAYER_ERROR_PA_INIT) + if ((reg & UIC_DATA_LINK_LAYER_ERROR) && + (reg & UIC_DATA_LINK_LAYER_ERROR_CODE_MASK)) { + ufshcd_update_uic_reg_hist(&hba->ufs_stats.dl_err, reg); + + if (reg & UIC_DATA_LINK_LAYER_ERROR_PA_INIT) { hba->uic_error |= UFSHCD_UIC_DL_PA_INIT_ERROR; + } else if (hba->dev_quirks & + UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS) { + if (reg & UIC_DATA_LINK_LAYER_ERROR_NAC_RECEIVED) + hba->uic_error |= + UFSHCD_UIC_DL_NAC_RECEIVED_ERROR; + else if (reg & + UIC_DATA_LINK_LAYER_ERROR_TCx_REPLAY_TIMEOUT) + hba->uic_error |= + UFSHCD_UIC_DL_TCx_REPLAY_ERROR; + } + retval |= IRQ_HANDLED; + } /* UIC NL/TL/DME errors needs software retry */ reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_NETWORK_LAYER); - if (reg) + if ((reg & UIC_NETWORK_LAYER_ERROR) && + (reg & UIC_NETWORK_LAYER_ERROR_CODE_MASK)) { + ufshcd_update_uic_reg_hist(&hba->ufs_stats.nl_err, reg); hba->uic_error |= UFSHCD_UIC_NL_ERROR; + retval |= IRQ_HANDLED; + } reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_TRANSPORT_LAYER); - if (reg) + if ((reg & UIC_TRANSPORT_LAYER_ERROR) && + (reg & UIC_TRANSPORT_LAYER_ERROR_CODE_MASK)) { + ufshcd_update_uic_reg_hist(&hba->ufs_stats.tl_err, reg); hba->uic_error |= UFSHCD_UIC_TL_ERROR; + retval |= IRQ_HANDLED; + } reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_DME); - if (reg) + if ((reg & UIC_DME_ERROR) && + (reg & UIC_DME_ERROR_CODE_MASK)) { + ufshcd_update_uic_reg_hist(&hba->ufs_stats.dme_err, reg); hba->uic_error |= UFSHCD_UIC_DME_ERROR; + retval |= IRQ_HANDLED; + } dev_dbg(hba->dev, "%s: UIC error flags = 0x%08x\n", __func__, hba->uic_error); + return retval; } /** * ufshcd_check_errors - Check for errors that need s/w attention * @hba: per-adapter instance + * + * Returns + * IRQ_HANDLED - If interrupt is valid + * IRQ_NONE - If invalid interrupt */ -static void ufshcd_check_errors(struct ufs_hba *hba) +static irqreturn_t ufshcd_check_errors(struct ufs_hba *hba) { bool queue_eh_work = false; + irqreturn_t retval = IRQ_NONE; - if (hba->errors & INT_FATAL_ERRORS) + if (hba->errors & INT_FATAL_ERRORS || hba->ce_error) queue_eh_work = true; if (hba->errors & UIC_ERROR) { hba->uic_error = 0; - ufshcd_update_uic_error(hba); + retval = ufshcd_update_uic_error(hba); if (hba->uic_error) queue_eh_work = true; } if (queue_eh_work) { - /* handle fatal errors only when link is functional */ - if (hba->ufshcd_state == UFSHCD_STATE_OPERATIONAL) { - /* block commands from scsi mid-layer */ - scsi_block_requests(hba->host); - - /* transfer error masks to sticky bits */ + /* + * update the transfer error masks to sticky bits, let's do this + * irrespective of current ufshcd_state. + */ hba->saved_err |= hba->errors; hba->saved_uic_err |= hba->uic_error; + hba->saved_ce_err |= hba->ce_error; + + /* handle fatal errors only when link is functional */ + if (hba->ufshcd_state == UFSHCD_STATE_OPERATIONAL) { + /* + * Set error handling in progress flag early so that we + * don't issue new requests any more. + */ + ufshcd_set_eh_in_progress(hba); hba->ufshcd_state = UFSHCD_STATE_ERROR; schedule_work(&hba->eh_work); } + retval |= IRQ_HANDLED; } /* * if (!queue_eh_work) - @@ -3606,40 +6472,63 @@ * itself without s/w intervention or errors that will be * handled by the SCSI core layer. */ + return retval; } /** * ufshcd_tmc_handler - handle task management function completion * @hba: per adapter instance + * + * Returns + * IRQ_HANDLED - If interrupt is valid + * IRQ_NONE - If invalid interrupt */ -static void ufshcd_tmc_handler(struct ufs_hba *hba) +static irqreturn_t ufshcd_tmc_handler(struct ufs_hba *hba) { u32 tm_doorbell; tm_doorbell = ufshcd_readl(hba, REG_UTP_TASK_REQ_DOOR_BELL); hba->tm_condition = tm_doorbell ^ hba->outstanding_tasks; + if (hba->tm_condition) { wake_up(&hba->tm_wq); + return IRQ_HANDLED; + } else { + return IRQ_NONE; + } } /** * ufshcd_sl_intr - Interrupt service routine * @hba: per adapter instance * @intr_status: contains interrupts generated by the controller + * + * Returns + * IRQ_HANDLED - If interrupt is valid + * IRQ_NONE - If invalid interrupt */ -static void ufshcd_sl_intr(struct ufs_hba *hba, u32 intr_status) +static irqreturn_t ufshcd_sl_intr(struct ufs_hba *hba, u32 intr_status) { + irqreturn_t retval = IRQ_NONE; + + ufsdbg_error_inject_dispatcher(hba, + ERR_INJECT_INTR, intr_status, &intr_status); + + ufshcd_vops_crypto_engine_get_status(hba, &hba->ce_error); + hba->errors = UFSHCD_ERROR_MASK & intr_status; - if (hba->errors) - ufshcd_check_errors(hba); + if (hba->errors || hba->ce_error) + retval |= ufshcd_check_errors(hba); if (intr_status & UFSHCD_UIC_MASK) - ufshcd_uic_cmd_compl(hba, intr_status); + retval |= ufshcd_uic_cmd_compl(hba, intr_status); if (intr_status & UTP_TASK_REQ_COMPL) - ufshcd_tmc_handler(hba); + retval |= ufshcd_tmc_handler(hba); if (intr_status & UTP_TRANSFER_REQ_COMPL) - ufshcd_transfer_req_compl(hba); + retval |= ufshcd_transfer_req_compl(hba); + + return retval; } /** @@ -3647,23 +6536,45 @@ * @irq: irq number * @__hba: pointer to adapter instance * - * Returns IRQ_HANDLED - If interrupt is valid + * Returns + * IRQ_HANDLED - If interrupt is valid * IRQ_NONE - If invalid interrupt */ static irqreturn_t ufshcd_intr(int irq, void *__hba) { - u32 intr_status; + u32 intr_status, enabled_intr_status; irqreturn_t retval = IRQ_NONE; struct ufs_hba *hba = __hba; + int retries = hba->nutrs; spin_lock(hba->host->host_lock); intr_status = ufshcd_readl(hba, REG_INTERRUPT_STATUS); - - if (intr_status) { + hba->ufs_stats.last_intr_status = intr_status; + hba->ufs_stats.last_intr_ts = ktime_get(); + /* + * There could be max of hba->nutrs reqs in flight and in worst case + * if the reqs get finished 1 by 1 after the interrupt status is + * read, make sure we handle them by checking the interrupt status + * again in a loop until we process all of the reqs before returning. + */ + do { + enabled_intr_status = + intr_status & ufshcd_readl(hba, REG_INTERRUPT_ENABLE); + if (intr_status) ufshcd_writel(hba, intr_status, REG_INTERRUPT_STATUS); - ufshcd_sl_intr(hba, intr_status); - retval = IRQ_HANDLED; + if (enabled_intr_status) + retval |= ufshcd_sl_intr(hba, enabled_intr_status); + + intr_status = ufshcd_readl(hba, REG_INTERRUPT_STATUS); + } while (intr_status && --retries); + + if (retval == IRQ_NONE) { + dev_err(hba->dev, "%s: Unhandled interrupt 0x%08x\n", + __func__, intr_status); + ufshcd_hex_dump("host regs: ", hba->mmio_base, + UFSHCI_REG_SPACE_SIZE); } + spin_unlock(hba->host->host_lock); return retval; } @@ -3684,7 +6595,7 @@ /* poll for max. 1 sec to clear door bell register by h/w */ err = ufshcd_wait_for_register(hba, REG_UTP_TASK_REQ_DOOR_BELL, - mask, 0, 1000, 1000); + mask, 0, 1000, 1000, true); out: return err; } @@ -3718,7 +6629,8 @@ * the maximum wait time is bounded by %TM_CMD_TIMEOUT. */ wait_event(hba->tm_tag_wq, ufshcd_get_tm_free_slot(hba, &free_slot)); - ufshcd_hold(hba, false); + hba->ufs_stats.clk_hold.ctx = TM_CMD_SEND; + ufshcd_hold_all(hba); spin_lock_irqsave(host->host_lock, flags); task_req_descp = hba->utmrdl_base_addr; @@ -3747,7 +6659,13 @@ /* send command to the controller */ __set_bit(free_slot, &hba->outstanding_tasks); + + /* Make sure descriptors are ready before ringing the task doorbell */ + wmb(); + ufshcd_writel(hba, 1 << free_slot, REG_UTP_TASK_REQ_DOOR_BELL); + /* Make sure that doorbell is committed immediately */ + wmb(); spin_unlock_irqrestore(host->host_lock, flags); @@ -3769,8 +6687,9 @@ clear_bit(free_slot, &hba->tm_condition); ufshcd_put_tm_slot(hba, free_slot); wake_up(&hba->tm_tag_wq); + hba->ufs_stats.clk_rel.ctx = TM_CMD_SEND; - ufshcd_release(hba); + ufshcd_release_all(hba); return err; } @@ -3796,6 +6715,7 @@ hba = shost_priv(host); tag = cmd->request->tag; + ufshcd_print_cmd_log(hba); lrbp = &hba->lrb[tag]; err = ufshcd_issue_tm_cmd(hba, lrbp->lun, 0, UFS_LOGICAL_RESET, &resp); if (err || resp != UPIU_TASK_MANAGEMENT_FUNC_COMPL) { @@ -3815,7 +6735,9 @@ spin_lock_irqsave(host->host_lock, flags); ufshcd_transfer_req_compl(hba); spin_unlock_irqrestore(host->host_lock, flags); + out: + hba->req_abort_count = 0; if (!err) { err = SUCCESS; } else { @@ -3825,6 +6747,17 @@ return err; } +static void ufshcd_set_req_abort_skip(struct ufs_hba *hba, unsigned long bitmap) +{ + struct ufshcd_lrb *lrbp; + int tag; + + for_each_set_bit(tag, &bitmap, hba->nutrs) { + lrbp = &hba->lrb[tag]; + lrbp->req_abort_skip = true; + } +} + /** * ufshcd_abort - abort a specific command * @cmd: SCSI command pointer @@ -3852,31 +6785,87 @@ host = cmd->device->host; hba = shost_priv(host); tag = cmd->request->tag; + if (!ufshcd_valid_tag(hba, tag)) { + dev_err(hba->dev, + "%s: invalid command tag %d: cmd=0x%p, cmd->request=0x%p", + __func__, tag, cmd, cmd->request); + BUG(); + } - ufshcd_hold(hba, false); + lrbp = &hba->lrb[tag]; + + ufshcd_update_error_stats(hba, UFS_ERR_TASK_ABORT); + + /* + * Task abort to the device W-LUN is illegal. When this command + * will fail, due to spec violation, scsi err handling next step + * will be to send LU reset which, again, is a spec violation. + * To avoid these unnecessary/illegal step we skip to the last error + * handling stage: reset and restore. + */ + if (lrbp->lun == UFS_UPIU_UFS_DEVICE_WLUN) + return ufshcd_eh_host_reset_handler(cmd); + + ufshcd_hold_all(hba); + reg = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL); /* If command is already aborted/completed, return SUCCESS */ - if (!(test_bit(tag, &hba->outstanding_reqs))) + if (!(test_bit(tag, &hba->outstanding_reqs))) { + dev_err(hba->dev, + "%s: cmd at tag %d already completed, outstanding=0x%lx, doorbell=0x%x\n", + __func__, tag, hba->outstanding_reqs, reg); goto out; + } - reg = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL); if (!(reg & (1 << tag))) { dev_err(hba->dev, "%s: cmd was completed, but without a notifying intr, tag = %d", __func__, tag); } - lrbp = &hba->lrb[tag]; + /* Print Transfer Request of aborted task */ + dev_err(hba->dev, "%s: Device abort task at tag %d", __func__, tag); + + /* + * Print detailed info about aborted request. + * As more than one request might get aborted at the same time, + * print full information only for the first aborted request in order + * to reduce repeated printouts. For other aborted requests only print + * basic details. + */ + scsi_print_command(cmd); + if (!hba->req_abort_count) { + ufshcd_print_fsm_state(hba); + ufshcd_print_host_regs(hba); + ufshcd_print_host_state(hba); + ufshcd_print_pwr_info(hba); + ufshcd_print_trs(hba, 1 << tag, true); + } else { + ufshcd_print_trs(hba, 1 << tag, false); + } + hba->req_abort_count++; + + + /* Skip task abort in case previous aborts failed and report failure */ + if (lrbp->req_abort_skip) { + err = -EIO; + goto out; + } + for (poll_cnt = 100; poll_cnt; poll_cnt--) { err = ufshcd_issue_tm_cmd(hba, lrbp->lun, lrbp->task_tag, UFS_QUERY_TASK, &resp); if (!err && resp == UPIU_TASK_MANAGEMENT_FUNC_SUCCEEDED) { /* cmd pending in the device */ + dev_err(hba->dev, "%s: cmd pending in the device. tag = %d", + __func__, tag); break; } else if (!err && resp == UPIU_TASK_MANAGEMENT_FUNC_COMPL) { /* * cmd not pending in the device, check if it is * in transition. */ + dev_err(hba->dev, "%s: cmd at tag %d not pending in the device.", + __func__, tag); reg = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL); if (reg & (1 << tag)) { /* sleep for max. 200us to stabilize */ @@ -3884,8 +6873,13 @@ continue; } /* command completed already */ + dev_err(hba->dev, "%s: cmd at tag %d successfully cleared from DB.", + __func__, tag); goto out; } else { + dev_err(hba->dev, + "%s: no response from device. tag = %d, err %d", + __func__, tag, err); if (!err) err = resp; /* service response error */ goto out; @@ -3900,19 +6894,25 @@ err = ufshcd_issue_tm_cmd(hba, lrbp->lun, lrbp->task_tag, UFS_ABORT_TASK, &resp); if (err || resp != UPIU_TASK_MANAGEMENT_FUNC_COMPL) { - if (!err) + if (!err) { err = resp; /* service response error */ + dev_err(hba->dev, "%s: issued. tag = %d, err %d", + __func__, tag, err); + } goto out; } err = ufshcd_clear_cmd(hba, tag); - if (err) + if (err) { + dev_err(hba->dev, "%s: Failed clearing cmd at tag %d, err %d", + __func__, tag, err); goto out; + } scsi_dma_unmap(cmd); spin_lock_irqsave(host->host_lock, flags); - __clear_bit(tag, &hba->outstanding_reqs); + ufshcd_outstanding_req_clear(hba, tag); hba->lrb[tag].cmd = NULL; spin_unlock_irqrestore(host->host_lock, flags); @@ -3924,14 +6924,15 @@ err = SUCCESS; } else { dev_err(hba->dev, "%s: failed with err %d\n", __func__, err); + ufshcd_set_req_abort_skip(hba, hba->outstanding_reqs); err = FAILED; } /* - * This ufshcd_release() corresponds to the original scsi cmd that got - * aborted here (as we won't get any IRQ for it). + * This ufshcd_release_all() corresponds to the original scsi cmd that + * got aborted here (as we won't get any IRQ for it). */ - ufshcd_release(hba); + ufshcd_release_all(hba); return err; } @@ -3952,9 +6953,12 @@ /* Reset the host controller */ spin_lock_irqsave(hba->host->host_lock, flags); - ufshcd_hba_stop(hba); + ufshcd_hba_stop(hba, false); spin_unlock_irqrestore(hba->host->host_lock, flags); + /* scale up clocks to max frequency before full reinitialization */ + ufshcd_set_clk_freq(hba, true); + err = ufshcd_hba_enable(hba); if (err) goto out; @@ -3962,8 +6966,21 @@ /* Establish the link again and restore the device */ err = ufshcd_probe_hba(hba); - if (!err && (hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL)) + if (!err && (hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL)) { err = -EIO; + goto out; + } + + if (!err) { + err = ufshcd_vops_crypto_engine_reset(hba); + if (err) { + dev_err(hba->dev, + "%s: failed to reset crypto engine %d\n", + __func__, err); + goto out; + } + } + out: if (err) dev_err(hba->dev, "%s: Host init failed %d\n", __func__, err); @@ -3987,10 +7004,26 @@ int retries = MAX_HOST_RESET_RETRIES; do { + err = ufshcd_vops_full_reset(hba); + if (err) + dev_warn(hba->dev, "%s: full reset returned %d\n", + __func__, err); + + err = ufshcd_reset_device(hba); + if (err) + dev_warn(hba->dev, "%s: device reset failed. err %d\n", + __func__, err); + err = ufshcd_host_reset_and_restore(hba); } while (err && --retries); /* + * There is no point proceeding even after failing + * to recover after multiple retries. + */ + if (err) + BUG(); + /* * After reset the door-bell might be cleared, complete * outstanding requests in s/w here. */ @@ -4010,13 +7043,12 @@ */ static int ufshcd_eh_host_reset_handler(struct scsi_cmnd *cmd) { - int err; + int err = SUCCESS; unsigned long flags; struct ufs_hba *hba; hba = shost_priv(cmd->device->host); - ufshcd_hold(hba, false); /* * Check if there is any race with fatal error handling. * If so, wait for it to complete. Even though fatal error @@ -4029,28 +7061,37 @@ hba->ufshcd_state == UFSHCD_STATE_RESET)) break; spin_unlock_irqrestore(hba->host->host_lock, flags); - dev_dbg(hba->dev, "%s: reset in progress\n", __func__); + dev_err(hba->dev, "%s: reset in progress - 1\n", __func__); flush_work(&hba->eh_work); } while (1); - hba->ufshcd_state = UFSHCD_STATE_RESET; - ufshcd_set_eh_in_progress(hba); - spin_unlock_irqrestore(hba->host->host_lock, flags); - - err = ufshcd_reset_and_restore(hba); + /* + * we don't know if previous reset had really reset the host controller + * or not. So let's force reset here to be sure. + */ + hba->ufshcd_state = UFSHCD_STATE_ERROR; + hba->force_host_reset = true; + schedule_work(&hba->eh_work); + /* wait for the reset work to finish */ + do { + if (!(work_pending(&hba->eh_work) || + hba->ufshcd_state == UFSHCD_STATE_RESET)) + break; + spin_unlock_irqrestore(hba->host->host_lock, flags); + dev_err(hba->dev, "%s: reset in progress - 2\n", __func__); + flush_work(&hba->eh_work); spin_lock_irqsave(hba->host->host_lock, flags); - if (!err) { - err = SUCCESS; - hba->ufshcd_state = UFSHCD_STATE_OPERATIONAL; - } else { + } while (1); + + if (!((hba->ufshcd_state == UFSHCD_STATE_OPERATIONAL) && + ufshcd_is_link_active(hba))) { err = FAILED; hba->ufshcd_state = UFSHCD_STATE_ERROR; } - ufshcd_clear_eh_in_progress(hba); + spin_unlock_irqrestore(hba->host->host_lock, flags); - ufshcd_release(hba); return err; } @@ -4162,7 +7203,7 @@ dev_dbg(hba->dev, "%s: setting icc_level 0x%x", __func__, hba->init_prefetch_data.icc_level); - ret = ufshcd_query_attr(hba, UPIU_QUERY_OPCODE_WRITE_ATTR, + ret = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_WRITE_ATTR, QUERY_ATTR_IDN_ACTIVE_ICC_LVL, 0, 0, &hba->init_prefetch_data.icc_level); @@ -4240,6 +7281,210 @@ } /** + * ufshcd_tune_pa_tactivate - Tunes PA_TActivate of local UniPro + * @hba: per-adapter instance + * + * PA_TActivate parameter can be tuned manually if UniPro version is less than + * 1.61. PA_TActivate needs to be greater than or equal to peerM-PHY's + * RX_MIN_ACTIVATETIME_CAPABILITY attribute. This optimal value can help reduce + * the hibern8 exit latency. + * + * Returns zero on success, non-zero error value on failure. + */ +static int ufshcd_tune_pa_tactivate(struct ufs_hba *hba) +{ + int ret = 0; + u32 peer_rx_min_activatetime = 0, tuned_pa_tactivate; + + if (!ufshcd_is_unipro_pa_params_tuning_req(hba)) + return 0; + + ret = ufshcd_dme_peer_get(hba, + UIC_ARG_MIB_SEL( + RX_MIN_ACTIVATETIME_CAPABILITY, + UIC_ARG_MPHY_RX_GEN_SEL_INDEX(0)), + &peer_rx_min_activatetime); + if (ret) + goto out; + + /* make sure proper unit conversion is applied */ + tuned_pa_tactivate = + ((peer_rx_min_activatetime * RX_MIN_ACTIVATETIME_UNIT_US) + / PA_TACTIVATE_TIME_UNIT_US); + ret = ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TACTIVATE), + tuned_pa_tactivate); + +out: + return ret; +} + +/** + * ufshcd_tune_pa_hibern8time - Tunes PA_Hibern8Time of local UniPro + * @hba: per-adapter instance + * + * PA_Hibern8Time parameter can be tuned manually if UniPro version is less than + * 1.61. PA_Hibern8Time needs to be maximum of local M-PHY's + * TX_HIBERN8TIME_CAPABILITY & peer M-PHY's RX_HIBERN8TIME_CAPABILITY. + * This optimal value can help reduce the hibern8 exit latency. + * + * Returns zero on success, non-zero error value on failure. + */ +static int ufshcd_tune_pa_hibern8time(struct ufs_hba *hba) +{ + int ret = 0; + u32 local_tx_hibern8_time_cap = 0, peer_rx_hibern8_time_cap = 0; + u32 max_hibern8_time, tuned_pa_hibern8time; + + ret = ufshcd_dme_get(hba, + UIC_ARG_MIB_SEL(TX_HIBERN8TIME_CAPABILITY, + UIC_ARG_MPHY_TX_GEN_SEL_INDEX(0)), + &local_tx_hibern8_time_cap); + if (ret) + goto out; + + ret = ufshcd_dme_peer_get(hba, + UIC_ARG_MIB_SEL(RX_HIBERN8TIME_CAPABILITY, + UIC_ARG_MPHY_RX_GEN_SEL_INDEX(0)), + &peer_rx_hibern8_time_cap); + if (ret) + goto out; + + max_hibern8_time = max(local_tx_hibern8_time_cap, + peer_rx_hibern8_time_cap); + /* make sure proper unit conversion is applied */ + tuned_pa_hibern8time = ((max_hibern8_time * HIBERN8TIME_UNIT_US) + / PA_HIBERN8_TIME_UNIT_US); + ret = ufshcd_dme_set(hba, UIC_ARG_MIB(PA_HIBERN8TIME), + tuned_pa_hibern8time); +out: + return ret; +} + +/** + * ufshcd_quirk_tune_host_pa_tactivate - Ensures that host PA_TACTIVATE is + * less than device PA_TACTIVATE time. + * @hba: per-adapter instance + * + * Some UFS devices require host PA_TACTIVATE to be lower than device + * PA_TACTIVATE, we need to enable UFS_DEVICE_QUIRK_HOST_PA_TACTIVATE quirk + * for such devices. + * + * Returns zero on success, non-zero error value on failure. + */ +static int ufshcd_quirk_tune_host_pa_tactivate(struct ufs_hba *hba) +{ + int ret = 0; + u32 granularity, peer_granularity; + u32 pa_tactivate, peer_pa_tactivate; + u32 pa_tactivate_us, peer_pa_tactivate_us; + u8 gran_to_us_table[] = {1, 4, 8, 16, 32, 100}; + + ret = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_GRANULARITY), + &granularity); + if (ret) + goto out; + + ret = ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_GRANULARITY), + &peer_granularity); + if (ret) + goto out; + + if ((granularity < PA_GRANULARITY_MIN_VAL) || + (granularity > PA_GRANULARITY_MAX_VAL)) { + dev_err(hba->dev, "%s: invalid host PA_GRANULARITY %d", + __func__, granularity); + return -EINVAL; + } + + if ((peer_granularity < PA_GRANULARITY_MIN_VAL) || + (peer_granularity > PA_GRANULARITY_MAX_VAL)) { + dev_err(hba->dev, "%s: invalid device PA_GRANULARITY %d", + __func__, peer_granularity); + return -EINVAL; + } + + ret = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_TACTIVATE), &pa_tactivate); + if (ret) + goto out; + + ret = ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_TACTIVATE), + &peer_pa_tactivate); + if (ret) + goto out; + + pa_tactivate_us = pa_tactivate * gran_to_us_table[granularity - 1]; + peer_pa_tactivate_us = peer_pa_tactivate * + gran_to_us_table[peer_granularity - 1]; + + if (pa_tactivate_us > peer_pa_tactivate_us) { + u32 new_peer_pa_tactivate; + + new_peer_pa_tactivate = pa_tactivate_us / + gran_to_us_table[peer_granularity - 1]; + new_peer_pa_tactivate++; + ret = ufshcd_dme_peer_set(hba, UIC_ARG_MIB(PA_TACTIVATE), + new_peer_pa_tactivate); + } + +out: + return ret; +} + +static void ufshcd_tune_unipro_params(struct ufs_hba *hba) +{ + if (ufshcd_is_unipro_pa_params_tuning_req(hba)) { + ufshcd_tune_pa_tactivate(hba); + ufshcd_tune_pa_hibern8time(hba); + } + + if (hba->dev_quirks & UFS_DEVICE_QUIRK_PA_TACTIVATE) + /* set 1ms timeout for PA_TACTIVATE */ + ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TACTIVATE), 10); + + if (hba->dev_quirks & UFS_DEVICE_QUIRK_HOST_PA_TACTIVATE) + ufshcd_quirk_tune_host_pa_tactivate(hba); + + ufshcd_vops_apply_dev_quirks(hba); +} + +static void ufshcd_clear_dbg_ufs_stats(struct ufs_hba *hba) +{ + int err_reg_hist_size = sizeof(struct ufs_uic_err_reg_hist); + + memset(&hba->ufs_stats.pa_err, 0, err_reg_hist_size); + memset(&hba->ufs_stats.dl_err, 0, err_reg_hist_size); + memset(&hba->ufs_stats.nl_err, 0, err_reg_hist_size); + memset(&hba->ufs_stats.tl_err, 0, err_reg_hist_size); + memset(&hba->ufs_stats.dme_err, 0, err_reg_hist_size); + + hba->req_abort_count = 0; +} + +static void ufshcd_apply_pm_quirks(struct ufs_hba *hba) +{ + if (hba->dev_quirks & UFS_DEVICE_QUIRK_NO_LINK_OFF) { + if (ufs_get_pm_lvl_to_link_pwr_state(hba->rpm_lvl) == + UIC_LINK_OFF_STATE) { + hba->rpm_lvl = + ufs_get_desired_pm_lvl_for_dev_link_state( + UFS_SLEEP_PWR_MODE, + UIC_LINK_HIBERN8_STATE); + dev_info(hba->dev, "UFS_DEVICE_QUIRK_NO_LINK_OFF enabled, changed rpm_lvl to %d\n", + hba->rpm_lvl); + } + if (ufs_get_pm_lvl_to_link_pwr_state(hba->spm_lvl) == + UIC_LINK_OFF_STATE) { + hba->spm_lvl = + ufs_get_desired_pm_lvl_for_dev_link_state( + UFS_SLEEP_PWR_MODE, + UIC_LINK_HIBERN8_STATE); + dev_info(hba->dev, "UFS_DEVICE_QUIRK_NO_LINK_OFF enabled, changed spm_lvl to %d\n", + hba->spm_lvl); + } + } +} + +/** * ufshcd_probe_hba - probe hba to detect device and initialize * @hba: per-adapter instance * @@ -4248,12 +7493,17 @@ static int ufshcd_probe_hba(struct ufs_hba *hba) { int ret; + ktime_t start = ktime_get(); ret = ufshcd_link_startup(hba); if (ret) goto out; - ufshcd_init_pwr_info(hba); + /* Debug counters initialization */ + ufshcd_clear_dbg_ufs_stats(hba); + /* set the default level for urgent bkops */ + hba->urgent_bkops_lvl = BKOPS_STATUS_PERF_IMPACT; + hba->is_urgent_bkops_lvl_checked = false; /* UniPro link is active now */ ufshcd_set_link_active(hba); @@ -4266,10 +7516,18 @@ if (ret) goto out; + ufs_advertise_fixup_device(hba); + ufshcd_tune_unipro_params(hba); + + ufshcd_apply_pm_quirks(hba); + ret = ufshcd_set_vccq_rail_unused(hba, + (hba->dev_quirks & UFS_DEVICE_NO_VCCQ) ? true : false); + if (ret) + goto out; + /* UFS device is also active now */ ufshcd_set_ufs_dev_active(hba); ufshcd_force_reset_auto_bkops(hba); - hba->ufshcd_state = UFSHCD_STATE_OPERATIONAL; hba->wlun_dev_clr_ua = true; if (ufshcd_get_max_pwr_mode(hba)) { @@ -4278,11 +7536,15 @@ __func__); } else { ret = ufshcd_config_pwr_mode(hba, &hba->max_pwr_info.info); - if (ret) + if (ret) { dev_err(hba->dev, "%s: Failed setting power mode, err = %d\n", __func__, ret); + goto out; + } } + /* set the state as operational after switching to desired gear */ + hba->ufshcd_state = UFSHCD_STATE_OPERATIONAL; /* * If we are in error handling context or in power management callbacks * context, no need to scan the host @@ -4292,7 +7554,7 @@ /* clear any previous UFS device information */ memset(&hba->dev_info, 0, sizeof(hba->dev_info)); - if (!ufshcd_query_flag(hba, UPIU_QUERY_OPCODE_READ_FLAG, + if (!ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_READ_FLAG, QUERY_FLAG_IDN_PWR_ON_WPE, &flag)) hba->dev_info.f_power_on_wp_en = flag; @@ -4303,6 +7565,27 @@ if (ufshcd_scsi_add_wlus(hba)) goto out; + /* Initialize devfreq after UFS device is detected */ + if (ufshcd_is_clkscaling_supported(hba)) { + memcpy(&hba->clk_scaling.saved_pwr_info.info, + &hba->pwr_info, sizeof(struct ufs_pa_layer_attr)); + hba->clk_scaling.saved_pwr_info.is_valid = true; + hba->clk_scaling.is_scaled_up = true; + if (!hba->devfreq) { + hba->devfreq = devfreq_add_device(hba->dev, + &ufs_devfreq_profile, + "simple_ondemand", + gov_data); + if (IS_ERR(hba->devfreq)) { + ret = PTR_ERR(hba->devfreq); + dev_err(hba->dev, "Unable to register with devfreq %d\n", + ret); + goto out; + } + } + hba->clk_scaling.is_allowed = true; + } + scsi_scan_host(hba->host); pm_runtime_put_sync(hba->dev); } @@ -4310,10 +7593,13 @@ if (!hba->is_init_prefetch) hba->is_init_prefetch = true; - /* Resume devfreq after UFS device is detected */ - if (ufshcd_is_clkscaling_enabled(hba)) - devfreq_resume_device(hba->devfreq); - + /* + * Enable auto hibern8 if supported, after full host and + * device initialization. + */ + if (ufshcd_is_auto_hibern8_supported(hba)) + ufshcd_set_auto_hibern8_timer(hba, + hba->hibern8_on_idle.delay_ms); out: /* * If we failed to initialize the device or the device is not @@ -4324,6 +7610,9 @@ ufshcd_hba_exit(hba); } + trace_ufshcd_init(dev_name(hba->dev), ret, + ktime_to_us(ktime_sub(ktime_get(), start)), + hba->curr_dev_pwr_mode, hba->uic_link_state); return ret; } @@ -4336,7 +7625,296 @@ { struct ufs_hba *hba = (struct ufs_hba *)data; + /* + * Don't allow clock gating and hibern8 enter for faster device + * detection. + */ + ufshcd_hold_all(hba); ufshcd_probe_hba(hba); + ufshcd_release_all(hba); +} + +/** + * ufshcd_query_ioctl - perform user read queries + * @hba: per-adapter instance + * @lun: used for lun specific queries + * @buffer: user space buffer for reading and submitting query data and params + * @return: 0 for success negative error code otherwise + * + * Expected/Submitted buffer structure is struct ufs_ioctl_query_data. + * It will read the opcode, idn and buf_length parameters, and, put the + * response in the buffer field while updating the used size in buf_length. + */ +static int ufshcd_query_ioctl(struct ufs_hba *hba, u8 lun, void __user *buffer) +{ + struct ufs_ioctl_query_data *ioctl_data; + int err = 0; + int length = 0; + void *data_ptr; + bool flag; + u32 att; + u8 index; + u8 *desc = NULL; + + ioctl_data = kzalloc(sizeof(struct ufs_ioctl_query_data), GFP_KERNEL); + if (!ioctl_data) { + dev_err(hba->dev, "%s: Failed allocating %zu bytes\n", __func__, + sizeof(struct ufs_ioctl_query_data)); + err = -ENOMEM; + goto out; + } + + /* extract params from user buffer */ + err = copy_from_user(ioctl_data, buffer, + sizeof(struct ufs_ioctl_query_data)); + if (err) { + dev_err(hba->dev, + "%s: Failed copying buffer from user, err %d\n", + __func__, err); + goto out_release_mem; + } + + /* verify legal parameters & send query */ + switch (ioctl_data->opcode) { + case UPIU_QUERY_OPCODE_READ_DESC: + switch (ioctl_data->idn) { + case QUERY_DESC_IDN_DEVICE: + case QUERY_DESC_IDN_CONFIGURAION: + case QUERY_DESC_IDN_INTERCONNECT: + case QUERY_DESC_IDN_GEOMETRY: + case QUERY_DESC_IDN_POWER: + index = 0; + break; + case QUERY_DESC_IDN_UNIT: + if (!ufs_is_valid_unit_desc_lun(lun)) { + dev_err(hba->dev, + "%s: No unit descriptor for lun 0x%x\n", + __func__, lun); + err = -EINVAL; + goto out_release_mem; + } + index = lun; + break; + default: + goto out_einval; + } + length = min_t(int, QUERY_DESC_MAX_SIZE, + ioctl_data->buf_size); + desc = kzalloc(length, GFP_KERNEL); + if (!desc) { + dev_err(hba->dev, "%s: Failed allocating %d bytes\n", + __func__, length); + err = -ENOMEM; + goto out_release_mem; + } + err = ufshcd_query_descriptor(hba, ioctl_data->opcode, + ioctl_data->idn, index, 0, desc, &length); + break; + case UPIU_QUERY_OPCODE_READ_ATTR: + switch (ioctl_data->idn) { + case QUERY_ATTR_IDN_BOOT_LU_EN: + case QUERY_ATTR_IDN_POWER_MODE: + case QUERY_ATTR_IDN_ACTIVE_ICC_LVL: + case QUERY_ATTR_IDN_OOO_DATA_EN: + case QUERY_ATTR_IDN_BKOPS_STATUS: + case QUERY_ATTR_IDN_PURGE_STATUS: + case QUERY_ATTR_IDN_MAX_DATA_IN: + case QUERY_ATTR_IDN_MAX_DATA_OUT: + case QUERY_ATTR_IDN_REF_CLK_FREQ: + case QUERY_ATTR_IDN_CONF_DESC_LOCK: + case QUERY_ATTR_IDN_MAX_NUM_OF_RTT: + case QUERY_ATTR_IDN_EE_CONTROL: + case QUERY_ATTR_IDN_EE_STATUS: + case QUERY_ATTR_IDN_SECONDS_PASSED: + index = 0; + break; + case QUERY_ATTR_IDN_DYN_CAP_NEEDED: + case QUERY_ATTR_IDN_CORR_PRG_BLK_NUM: + index = lun; + break; + default: + goto out_einval; + } + err = ufshcd_query_attr(hba, ioctl_data->opcode, ioctl_data->idn, + index, 0, &att); + break; + + case UPIU_QUERY_OPCODE_WRITE_ATTR: + err = copy_from_user(&att, + buffer + sizeof(struct ufs_ioctl_query_data), + sizeof(u32)); + if (err) { + dev_err(hba->dev, + "%s: Failed copying buffer from user, err %d\n", + __func__, err); + goto out_release_mem; + } + + switch (ioctl_data->idn) { + case QUERY_ATTR_IDN_BOOT_LU_EN: + index = 0; + if (att > QUERY_ATTR_IDN_BOOT_LU_EN_MAX) { + dev_err(hba->dev, + "%s: Illegal ufs query ioctl data, opcode 0x%x, idn 0x%x, att 0x%x\n", + __func__, ioctl_data->opcode, + (unsigned int)ioctl_data->idn, att); + err = -EINVAL; + goto out_release_mem; + } + break; + default: + goto out_einval; + } + err = ufshcd_query_attr(hba, ioctl_data->opcode, + ioctl_data->idn, index, 0, &att); + break; + + case UPIU_QUERY_OPCODE_READ_FLAG: + switch (ioctl_data->idn) { + case QUERY_FLAG_IDN_FDEVICEINIT: + case QUERY_FLAG_IDN_PERMANENT_WPE: + case QUERY_FLAG_IDN_PWR_ON_WPE: + case QUERY_FLAG_IDN_BKOPS_EN: + case QUERY_FLAG_IDN_PURGE_ENABLE: + case QUERY_FLAG_IDN_FPHYRESOURCEREMOVAL: + case QUERY_FLAG_IDN_BUSY_RTC: + break; + default: + goto out_einval; + } + err = ufshcd_query_flag_retry(hba, ioctl_data->opcode, + ioctl_data->idn, &flag); + break; + default: + goto out_einval; + } + + if (err) { + dev_err(hba->dev, "%s: Query for idn %d failed\n", __func__, + ioctl_data->idn); + goto out_release_mem; + } + + /* + * copy response data + * As we might end up reading less data then what is specified in + * "ioctl_data->buf_size". So we are updating "ioctl_data-> + * buf_size" to what exactly we have read. + */ + switch (ioctl_data->opcode) { + case UPIU_QUERY_OPCODE_READ_DESC: + ioctl_data->buf_size = min_t(int, ioctl_data->buf_size, length); + data_ptr = desc; + break; + case UPIU_QUERY_OPCODE_READ_ATTR: + ioctl_data->buf_size = sizeof(u32); + data_ptr = &att; + break; + case UPIU_QUERY_OPCODE_READ_FLAG: + ioctl_data->buf_size = 1; + data_ptr = &flag; + break; + case UPIU_QUERY_OPCODE_WRITE_ATTR: + goto out_release_mem; + default: + goto out_einval; + } + + /* copy to user */ + err = copy_to_user(buffer, ioctl_data, + sizeof(struct ufs_ioctl_query_data)); + if (err) + dev_err(hba->dev, "%s: Failed copying back to user.\n", + __func__); + err = copy_to_user(buffer + sizeof(struct ufs_ioctl_query_data), + data_ptr, ioctl_data->buf_size); + if (err) + dev_err(hba->dev, "%s: err %d copying back to user.\n", + __func__, err); + goto out_release_mem; + +out_einval: + dev_err(hba->dev, + "%s: illegal ufs query ioctl data, opcode 0x%x, idn 0x%x\n", + __func__, ioctl_data->opcode, (unsigned int)ioctl_data->idn); + err = -EINVAL; +out_release_mem: + kfree(ioctl_data); + kfree(desc); +out: + return err; +} + +/** + * ufshcd_ioctl - ufs ioctl callback registered in scsi_host + * @dev: scsi device required for per LUN queries + * @cmd: command opcode + * @buffer: user space buffer for transferring data + * + * Supported commands: + * UFS_IOCTL_QUERY + */ +static int ufshcd_ioctl(struct scsi_device *dev, int cmd, void __user *buffer) +{ + struct ufs_hba *hba = shost_priv(dev->host); + int err = 0; + + BUG_ON(!hba); + if (!buffer) { + dev_err(hba->dev, "%s: User buffer is NULL!\n", __func__); + return -EINVAL; + } + + switch (cmd) { + case UFS_IOCTL_QUERY: + pm_runtime_get_sync(hba->dev); + err = ufshcd_query_ioctl(hba, ufshcd_scsi_to_upiu_lun(dev->lun), + buffer); + pm_runtime_put_sync(hba->dev); + break; + default: + err = -ENOIOCTLCMD; + dev_dbg(hba->dev, "%s: Unsupported ioctl cmd %d\n", __func__, + cmd); + break; + } + + return err; +} + +static enum blk_eh_timer_return ufshcd_eh_timed_out(struct scsi_cmnd *scmd) +{ + unsigned long flags; + struct Scsi_Host *host; + struct ufs_hba *hba; + int index; + bool found = false; + + if (!scmd || !scmd->device || !scmd->device->host) + return BLK_EH_NOT_HANDLED; + + host = scmd->device->host; + hba = shost_priv(host); + if (!hba) + return BLK_EH_NOT_HANDLED; + + spin_lock_irqsave(host->host_lock, flags); + + for_each_set_bit(index, &hba->outstanding_reqs, hba->nutrs) { + if (hba->lrb[index].cmd == scmd) { + found = true; + break; + } + } + + spin_unlock_irqrestore(host->host_lock, flags); + + /* + * Bypass SCSI error handling and reset the block layer timer if this + * SCSI command was not actually dispatched to UFS driver, otherwise + * let SCSI layer handle the error as usual. + */ + return found ? BLK_EH_NOT_HANDLED : BLK_EH_RESET_TIMER; } static struct scsi_host_template ufshcd_driver_template = { @@ -4351,6 +7929,11 @@ .eh_abort_handler = ufshcd_abort, .eh_device_reset_handler = ufshcd_eh_device_reset_handler, .eh_host_reset_handler = ufshcd_eh_host_reset_handler, + .eh_timed_out = ufshcd_eh_timed_out, + .ioctl = ufshcd_ioctl, +#ifdef CONFIG_COMPAT + .compat_ioctl = ufshcd_ioctl, +#endif .this_id = -1, .sg_tablesize = SG_ALL, .cmd_per_lun = UFSHCD_CMD_PER_LUN, @@ -4379,12 +7962,23 @@ static inline int ufshcd_config_vreg_lpm(struct ufs_hba *hba, struct ufs_vreg *vreg) { - return ufshcd_config_vreg_load(hba->dev, vreg, UFS_VREG_LPM_LOAD_UA); + if (!vreg) + return 0; + else if (vreg->unused) + return 0; + else + return ufshcd_config_vreg_load(hba->dev, vreg, + UFS_VREG_LPM_LOAD_UA); } static inline int ufshcd_config_vreg_hpm(struct ufs_hba *hba, struct ufs_vreg *vreg) { + if (!vreg) + return 0; + else if (vreg->unused) + return 0; + else return ufshcd_config_vreg_load(hba->dev, vreg, vreg->max_uA); } @@ -4423,7 +8017,9 @@ { int ret = 0; - if (!vreg || vreg->enabled) + if (!vreg) + goto out; + else if (vreg->enabled || vreg->unused) goto out; ret = ufshcd_config_vreg(dev, vreg, true); @@ -4443,7 +8039,9 @@ { int ret = 0; - if (!vreg || !vreg->enabled) + if (!vreg) + goto out; + else if (!vreg->enabled || vreg->unused) goto out; ret = regulator_disable(vreg->reg); @@ -4493,11 +8091,16 @@ static int ufshcd_setup_hba_vreg(struct ufs_hba *hba, bool on) { struct ufs_vreg_info *info = &hba->vreg_info; + int ret = 0; - if (info) - return ufshcd_toggle_vreg(hba->dev, info->vdd_hba, on); + if (info->vdd_hba) { + ret = ufshcd_toggle_vreg(hba->dev, info->vdd_hba, on); - return 0; + if (!ret) + ufshcd_vops_update_sec_cfg(hba, on); + } + + return ret; } static int ufshcd_get_vreg(struct device *dev, struct ufs_vreg *vreg) @@ -4549,22 +8152,73 @@ return 0; } -static int __ufshcd_setup_clocks(struct ufs_hba *hba, bool on, - bool skip_ref_clk) +static int ufshcd_set_vccq_rail_unused(struct ufs_hba *hba, bool unused) +{ + int ret = 0; + struct ufs_vreg_info *info = &hba->vreg_info; + + if (!info) + goto out; + else if (!info->vccq) + goto out; + + if (unused) { + /* shut off the rail here */ + ret = ufshcd_toggle_vreg(hba->dev, info->vccq, false); + /* + * Mark this rail as no longer used, so it doesn't get enabled + * later by mistake + */ + if (!ret) + info->vccq->unused = true; + } else { + /* + * rail should have been already enabled hence just make sure + * that unused flag is cleared. + */ + info->vccq->unused = false; + } +out: + return ret; +} + +static int ufshcd_setup_clocks(struct ufs_hba *hba, bool on, + bool skip_ref_clk, bool is_gating_context) { int ret = 0; struct ufs_clk_info *clki; struct list_head *head = &hba->clk_list_head; unsigned long flags; + ktime_t start = ktime_get(); + bool clk_state_changed = false; if (!head || list_empty(head)) goto out; + /* call vendor specific bus vote before enabling the clocks */ + if (on) { + ret = ufshcd_vops_set_bus_vote(hba, on); + if (ret) + return ret; + } + + /* + * vendor specific setup_clocks ops may depend on clocks managed by + * this standard driver hence call the vendor specific setup_clocks + * before disabling the clocks managed here. + */ + if (!on) { + ret = ufshcd_vops_setup_clocks(hba, on, is_gating_context); + if (ret) + return ret; + } + list_for_each_entry(clki, head, list) { if (!IS_ERR_OR_NULL(clki->clk)) { if (skip_ref_clk && !strcmp(clki->name, "ref_clk")) continue; + clk_state_changed = on ^ clki->enabled; if (on && !clki->enabled) { ret = clk_prepare_enable(clki->clk); if (ret) { @@ -4581,24 +8235,65 @@ } } - ret = ufshcd_vops_setup_clocks(hba, on); + /* + * vendor specific setup_clocks ops may depend on clocks managed by + * this standard driver hence call the vendor specific setup_clocks + * after enabling the clocks managed here. + */ + if (on) { + ret = ufshcd_vops_setup_clocks(hba, on, is_gating_context); + if (ret) + goto out; + } + + /* + * call vendor specific bus vote to remove the vote after + * disabling the clocks. + */ + if (!on) + ret = ufshcd_vops_set_bus_vote(hba, on); + out: if (ret) { + if (on) + /* Can't do much if this fails */ + (void) ufshcd_vops_set_bus_vote(hba, false); list_for_each_entry(clki, head, list) { if (!IS_ERR_OR_NULL(clki->clk) && clki->enabled) clk_disable_unprepare(clki->clk); } - } else if (on) { + } else if (!ret && on) { spin_lock_irqsave(hba->host->host_lock, flags); hba->clk_gating.state = CLKS_ON; + trace_ufshcd_clk_gating(dev_name(hba->dev), + hba->clk_gating.state); spin_unlock_irqrestore(hba->host->host_lock, flags); + /* restore the secure configuration as clocks are enabled */ + ufshcd_vops_update_sec_cfg(hba, true); } + + if (clk_state_changed) + trace_ufshcd_profile_clk_gating(dev_name(hba->dev), + (on ? "on" : "off"), + ktime_to_us(ktime_sub(ktime_get(), start)), ret); return ret; } -static int ufshcd_setup_clocks(struct ufs_hba *hba, bool on) +static int ufshcd_enable_clocks(struct ufs_hba *hba) { - return __ufshcd_setup_clocks(hba, on, false); + return ufshcd_setup_clocks(hba, true, false, false); +} + +static int ufshcd_disable_clocks(struct ufs_hba *hba, + bool is_gating_context) +{ + return ufshcd_setup_clocks(hba, false, false, is_gating_context); +} + +static int ufshcd_disable_clocks_skip_ref_clk(struct ufs_hba *hba, + bool is_gating_context) +{ + return ufshcd_setup_clocks(hba, false, true, is_gating_context); } static int ufshcd_init_clocks(struct ufs_hba *hba) @@ -4644,7 +8339,7 @@ { int err = 0; - if (!hba->vops) + if (!hba->var || !hba->var->vops) goto out; err = ufshcd_vops_init(hba); @@ -4668,11 +8363,9 @@ static void ufshcd_variant_hba_exit(struct ufs_hba *hba) { - if (!hba->vops) + if (!hba->var || !hba->var->vops) return; - ufshcd_vops_setup_clocks(hba, false); - ufshcd_vops_setup_regulators(hba, false); ufshcd_vops_exit(hba); @@ -4701,7 +8394,7 @@ if (err) goto out_disable_hba_vreg; - err = ufshcd_setup_clocks(hba, true); + err = ufshcd_enable_clocks(hba); if (err) goto out_disable_hba_vreg; @@ -4723,7 +8416,7 @@ out_disable_vreg: ufshcd_setup_vreg(hba, false); out_disable_clks: - ufshcd_setup_clocks(hba, false); + ufshcd_disable_clocks(hba, false); out_disable_hba_vreg: ufshcd_setup_hba_vreg(hba, false); out: @@ -4735,7 +8428,12 @@ if (hba->is_powered) { ufshcd_variant_hba_exit(hba); ufshcd_setup_vreg(hba, false); - ufshcd_setup_clocks(hba, false); + if (ufshcd_is_clkscaling_supported(hba)) { + if (hba->devfreq) + ufshcd_suspend_clkscaling(hba); + destroy_workqueue(hba->clk_scaling.workq); + } + ufshcd_disable_clocks(hba, false); ufshcd_setup_hba_vreg(hba, false); hba->is_powered = false; } @@ -4748,19 +8446,19 @@ 0, 0, 0, - SCSI_SENSE_BUFFERSIZE, + UFSHCD_REQ_SENSE_SIZE, 0}; char *buffer; int ret; - buffer = kzalloc(SCSI_SENSE_BUFFERSIZE, GFP_KERNEL); + buffer = kzalloc(UFSHCD_REQ_SENSE_SIZE, GFP_KERNEL); if (!buffer) { ret = -ENOMEM; goto out; } ret = scsi_execute_req_flags(sdp, cmd, DMA_FROM_DEVICE, buffer, - SCSI_SENSE_BUFFERSIZE, NULL, + UFSHCD_REQ_SENSE_SIZE, NULL, msecs_to_jiffies(1000), 3, NULL, REQ_PM); if (ret) pr_err("%s: failed with err %d\n", __func__, ret); @@ -4868,10 +8566,20 @@ (!check_for_bkops || (check_for_bkops && !hba->auto_bkops_enabled))) { /* + * Let's make sure that link is in low power mode, we are doing + * this currently by putting the link in Hibern8. Otherway to + * put the link in low power mode is to send the DME end point + * to device and then send the DME reset command to local + * unipro. But putting the link in hibern8 is much faster. + */ + ret = ufshcd_uic_hibern8_enter(hba); + if (ret) + goto out; + /* * Change controller state to "reset state" which * should also put the link in off/reset state */ - ufshcd_hba_stop(hba); + ufshcd_hba_stop(hba, true); /* * TODO: Check if we need any delay to make sure that * controller is reset @@ -4886,6 +8594,15 @@ static void ufshcd_vreg_set_lpm(struct ufs_hba *hba) { /* + * It seems some UFS devices may keep drawing more than sleep current + * (atleast for 500us) from UFS rails (especially from VCCQ rail). + * To avoid this situation, add 2ms delay before putting these UFS + * rails in LPM mode. + */ + if (!ufshcd_is_link_active(hba)) + usleep_range(2000, 2100); + + /* * If UFS device is either in UFS_Sleep turn off VCC rail to save some * power. * @@ -4917,7 +8634,6 @@ !hba->dev_info.is_lu_power_on_wp) { ret = ufshcd_setup_vreg(hba, true); } else if (!ufshcd_is_ufs_dev_active(hba)) { - ret = ufshcd_toggle_vreg(hba->dev, hba->vreg_info.vcc, true); if (!ret && !ufshcd_is_link_active(hba)) { ret = ufshcd_config_vreg_hpm(hba, hba->vreg_info.vccq); if (ret) @@ -4926,6 +8642,7 @@ if (ret) goto vccq_lpm; } + ret = ufshcd_toggle_vreg(hba->dev, hba->vreg_info.vcc, true); } goto out; @@ -4939,13 +8656,17 @@ static void ufshcd_hba_vreg_set_lpm(struct ufs_hba *hba) { - if (ufshcd_is_link_off(hba)) + if (ufshcd_is_link_off(hba) || + (ufshcd_is_link_hibern8(hba) + && ufshcd_is_power_collapse_during_hibern8_allowed(hba))) ufshcd_setup_hba_vreg(hba, false); } static void ufshcd_hba_vreg_set_hpm(struct ufs_hba *hba) { - if (ufshcd_is_link_off(hba)) + if (ufshcd_is_link_off(hba) || + (ufshcd_is_link_hibern8(hba) + && ufshcd_is_power_collapse_during_hibern8_allowed(hba))) ufshcd_setup_hba_vreg(hba, true); } @@ -4987,8 +8708,17 @@ * If we can't transition into any of the low power modes * just gate the clocks. */ - ufshcd_hold(hba, false); + WARN_ON(hba->hibern8_on_idle.is_enabled && + hba->hibern8_on_idle.active_reqs); + ufshcd_hold_all(hba); hba->clk_gating.is_suspended = true; + hba->hibern8_on_idle.is_suspended = true; + + if (hba->clk_scaling.is_allowed) { + cancel_work_sync(&hba->clk_scaling.suspend_work); + cancel_work_sync(&hba->clk_scaling.resume_work); + ufshcd_suspend_clkscaling(hba); + } if (req_dev_pwr_mode == UFS_ACTIVE_PWR_MODE && req_link_state == UIC_LINK_ACTIVE_STATE) { @@ -4997,12 +8727,12 @@ if ((req_dev_pwr_mode == hba->curr_dev_pwr_mode) && (req_link_state == hba->uic_link_state)) - goto out; + goto enable_gating; /* UFS device & link must be active before we enter in this function */ if (!ufshcd_is_ufs_dev_active(hba) || !ufshcd_is_link_active(hba)) { ret = -EINVAL; - goto out; + goto enable_gating; } if (ufshcd_is_runtime_pm(pm_op)) { @@ -5035,19 +8765,14 @@ if (ret) goto set_dev_active; + if (ufshcd_is_link_hibern8(hba) && + ufshcd_is_hibern8_on_idle_allowed(hba)) + hba->hibern8_on_idle.state = HIBERN8_ENTERED; + ufshcd_vreg_set_lpm(hba); disable_clks: /* - * The clock scaling needs access to controller registers. Hence, Wait - * for pending clock scaling work to be done before clocks are - * turned off. - */ - if (ufshcd_is_clkscaling_enabled(hba)) { - devfreq_suspend_device(hba->devfreq); - hba->clk_scaling.window_start_t = 0; - } - /* * Call vendor specific suspend callback. As these callbacks may access * vendor specific host controller register space call them before the * host clocks are ON. @@ -5056,17 +8781,19 @@ if (ret) goto set_link_active; - ret = ufshcd_vops_setup_clocks(hba, false); - if (ret) - goto vops_resume; - if (!ufshcd_is_link_active(hba)) - ufshcd_setup_clocks(hba, false); + ret = ufshcd_disable_clocks(hba, false); else /* If link is active, device ref_clk can't be switched off */ - __ufshcd_setup_clocks(hba, false, true); + ret = ufshcd_disable_clocks_skip_ref_clk(hba, false); + if (ret) + goto set_link_active; + if (ufshcd_is_clkgating_allowed(hba)) { hba->clk_gating.state = CLKS_OFF; + trace_ufshcd_clk_gating(dev_name(hba->dev), + hba->clk_gating.state); + } /* * Disable the host irq as host controller as there won't be any * host controller transaction expected till resume. @@ -5076,22 +8803,31 @@ ufshcd_hba_vreg_set_lpm(hba); goto out; -vops_resume: - ufshcd_vops_resume(hba, pm_op); set_link_active: + if (hba->clk_scaling.is_allowed) + ufshcd_resume_clkscaling(hba); ufshcd_vreg_set_hpm(hba); - if (ufshcd_is_link_hibern8(hba) && !ufshcd_uic_hibern8_exit(hba)) + if (ufshcd_is_link_hibern8(hba) && !ufshcd_uic_hibern8_exit(hba)) { ufshcd_set_link_active(hba); - else if (ufshcd_is_link_off(hba)) + } else if (ufshcd_is_link_off(hba)) { + ufshcd_update_error_stats(hba, UFS_ERR_VOPS_SUSPEND); ufshcd_host_reset_and_restore(hba); + } set_dev_active: if (!ufshcd_set_dev_pwr_mode(hba, UFS_ACTIVE_PWR_MODE)) ufshcd_disable_auto_bkops(hba); enable_gating: + if (hba->clk_scaling.is_allowed) + ufshcd_resume_clkscaling(hba); + hba->hibern8_on_idle.is_suspended = false; hba->clk_gating.is_suspended = false; - ufshcd_release(hba); + ufshcd_release_all(hba); out: hba->pm_op_in_progress = 0; + + if (ret) + ufshcd_update_error_stats(hba, UFS_ERR_SUSPEND); + return ret; } @@ -5115,14 +8851,12 @@ ufshcd_hba_vreg_set_hpm(hba); /* Make sure clocks are enabled before accessing controller */ - ret = ufshcd_setup_clocks(hba, true); + ret = ufshcd_enable_clocks(hba); if (ret) goto out; /* enable the host irq as host controller would be active soon */ - ret = ufshcd_enable_irq(hba); - if (ret) - goto disable_irq_and_vops_clks; + ufshcd_enable_irq(hba); ret = ufshcd_vreg_set_hpm(hba); if (ret) @@ -5139,18 +8873,28 @@ if (ufshcd_is_link_hibern8(hba)) { ret = ufshcd_uic_hibern8_exit(hba); - if (!ret) + if (!ret) { ufshcd_set_link_active(hba); - else + if (ufshcd_is_hibern8_on_idle_allowed(hba)) + hba->hibern8_on_idle.state = HIBERN8_EXITED; + } else { goto vendor_suspend; + } } else if (ufshcd_is_link_off(hba)) { - ret = ufshcd_host_reset_and_restore(hba); /* - * ufshcd_host_reset_and_restore() should have already + * A full initialization of the host and the device is required + * since the link was put to off during suspend. + */ + ret = ufshcd_reset_and_restore(hba); + /* + * ufshcd_reset_and_restore() should have already * set the link state as active */ if (ret || !ufshcd_is_link_active(hba)) goto vendor_suspend; + /* mark link state as hibern8 exited */ + if (ufshcd_is_hibern8_on_idle_allowed(hba)) + hba->hibern8_on_idle.state = HIBERN8_EXITED; } if (!ufshcd_is_ufs_dev_active(hba)) { @@ -5169,25 +8913,37 @@ ufshcd_urgent_bkops(hba); hba->clk_gating.is_suspended = false; + hba->hibern8_on_idle.is_suspended = false; - if (ufshcd_is_clkscaling_enabled(hba)) - devfreq_resume_device(hba->devfreq); + if (hba->clk_scaling.is_allowed) + ufshcd_resume_clkscaling(hba); /* Schedule clock gating in case of no access to UFS device yet */ - ufshcd_release(hba); + ufshcd_release_all(hba); goto out; set_old_link_state: ufshcd_link_state_transition(hba, old_link_state, 0); + if (ufshcd_is_link_hibern8(hba) && + ufshcd_is_hibern8_on_idle_allowed(hba)) + hba->hibern8_on_idle.state = HIBERN8_ENTERED; vendor_suspend: ufshcd_vops_suspend(hba, pm_op); disable_vreg: ufshcd_vreg_set_lpm(hba); disable_irq_and_vops_clks: ufshcd_disable_irq(hba); - ufshcd_setup_clocks(hba, false); + if (hba->clk_scaling.is_allowed) + ufshcd_suspend_clkscaling(hba); + ufshcd_disable_clocks(hba, false); + if (ufshcd_is_clkgating_allowed(hba)) + hba->clk_gating.state = CLKS_OFF; out: hba->pm_op_in_progress = 0; + + if (ret) + ufshcd_update_error_stats(hba, UFS_ERR_RESUME); + return ret; } @@ -5203,20 +8959,18 @@ int ufshcd_system_suspend(struct ufs_hba *hba) { int ret = 0; + ktime_t start = ktime_get(); if (!hba || !hba->is_powered) return 0; - if (pm_runtime_suspended(hba->dev)) { - if (hba->rpm_lvl == hba->spm_lvl) - /* - * There is possibility that device may still be in - * active state during the runtime suspend. - */ if ((ufs_get_pm_lvl_to_dev_pwr_mode(hba->spm_lvl) == - hba->curr_dev_pwr_mode) && !hba->auto_bkops_enabled) + hba->curr_dev_pwr_mode) && + (ufs_get_pm_lvl_to_link_pwr_state(hba->spm_lvl) == + hba->uic_link_state)) goto out; + if (pm_runtime_suspended(hba->dev)) { /* * UFS device and/or UFS link low power states during runtime * suspend seems to be different than what is expected during @@ -5232,6 +8986,9 @@ ret = ufshcd_suspend(hba, UFS_SYSTEM_PM); out: + trace_ufshcd_system_suspend(dev_name(hba->dev), ret, + ktime_to_us(ktime_sub(ktime_get(), start)), + hba->curr_dev_pwr_mode, hba->uic_link_state); if (!ret) hba->is_sys_suspended = true; return ret; @@ -5247,14 +9004,25 @@ int ufshcd_system_resume(struct ufs_hba *hba) { - if (!hba || !hba->is_powered || pm_runtime_suspended(hba->dev)) + int ret = 0; + ktime_t start = ktime_get(); + + if (!hba) + return -EINVAL; + + if (!hba->is_powered || pm_runtime_suspended(hba->dev)) /* * Let the runtime resume take care of resuming * if runtime suspended. */ - return 0; - - return ufshcd_resume(hba, UFS_SYSTEM_PM); + goto out; + else + ret = ufshcd_resume(hba, UFS_SYSTEM_PM); +out: + trace_ufshcd_system_resume(dev_name(hba->dev), ret, + ktime_to_us(ktime_sub(ktime_get(), start)), + hba->curr_dev_pwr_mode, hba->uic_link_state); + return ret; } EXPORT_SYMBOL(ufshcd_system_resume); @@ -5268,10 +9036,23 @@ */ int ufshcd_runtime_suspend(struct ufs_hba *hba) { - if (!hba || !hba->is_powered) - return 0; + int ret = 0; + ktime_t start = ktime_get(); + + if (!hba) + return -EINVAL; + + if (!hba->is_powered) + goto out; + else + ret = ufshcd_suspend(hba, UFS_RUNTIME_PM); +out: + trace_ufshcd_runtime_suspend(dev_name(hba->dev), ret, + ktime_to_us(ktime_sub(ktime_get(), start)), + hba->curr_dev_pwr_mode, + hba->uic_link_state); + return ret; - return ufshcd_suspend(hba, UFS_RUNTIME_PM); } EXPORT_SYMBOL(ufshcd_runtime_suspend); @@ -5298,10 +9079,22 @@ */ int ufshcd_runtime_resume(struct ufs_hba *hba) { - if (!hba || !hba->is_powered) - return 0; + int ret = 0; + ktime_t start = ktime_get(); + + if (!hba) + return -EINVAL; + + if (!hba->is_powered) + goto out; else - return ufshcd_resume(hba, UFS_RUNTIME_PM); + ret = ufshcd_resume(hba, UFS_RUNTIME_PM); +out: + trace_ufshcd_runtime_resume(dev_name(hba->dev), ret, + ktime_to_us(ktime_sub(ktime_get(), start)), + hba->curr_dev_pwr_mode, + hba->uic_link_state); + return ret; } EXPORT_SYMBOL(ufshcd_runtime_resume); @@ -5311,6 +9104,157 @@ } EXPORT_SYMBOL(ufshcd_runtime_idle); +static inline ssize_t ufshcd_pm_lvl_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count, + bool rpm) +{ + struct ufs_hba *hba = dev_get_drvdata(dev); + unsigned long flags, value; + + if (kstrtoul(buf, 0, &value)) + return -EINVAL; + + if (value >= UFS_PM_LVL_MAX) + return -EINVAL; + + spin_lock_irqsave(hba->host->host_lock, flags); + if (rpm) + hba->rpm_lvl = value; + else + hba->spm_lvl = value; + ufshcd_apply_pm_quirks(hba); + spin_unlock_irqrestore(hba->host->host_lock, flags); + return count; +} + +static ssize_t ufshcd_rpm_lvl_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct ufs_hba *hba = dev_get_drvdata(dev); + int curr_len; + u8 lvl; + + curr_len = snprintf(buf, PAGE_SIZE, + "\nCurrent Runtime PM level [%d] => dev_state [%s] link_state [%s]\n", + hba->rpm_lvl, + ufschd_ufs_dev_pwr_mode_to_string( + ufs_pm_lvl_states[hba->rpm_lvl].dev_state), + ufschd_uic_link_state_to_string( + ufs_pm_lvl_states[hba->rpm_lvl].link_state)); + + curr_len += snprintf((buf + curr_len), (PAGE_SIZE - curr_len), + "\nAll available Runtime PM levels info:\n"); + for (lvl = UFS_PM_LVL_0; lvl < UFS_PM_LVL_MAX; lvl++) + curr_len += snprintf((buf + curr_len), (PAGE_SIZE - curr_len), + "\tRuntime PM level [%d] => dev_state [%s] link_state [%s]\n", + lvl, + ufschd_ufs_dev_pwr_mode_to_string( + ufs_pm_lvl_states[lvl].dev_state), + ufschd_uic_link_state_to_string( + ufs_pm_lvl_states[lvl].link_state)); + + return curr_len; +} + +static ssize_t ufshcd_rpm_lvl_store(struct device *dev, + struct device_attribute *attr, const char *buf, size_t count) +{ + return ufshcd_pm_lvl_store(dev, attr, buf, count, true); +} + +static void ufshcd_add_rpm_lvl_sysfs_nodes(struct ufs_hba *hba) +{ + hba->rpm_lvl_attr.show = ufshcd_rpm_lvl_show; + hba->rpm_lvl_attr.store = ufshcd_rpm_lvl_store; + sysfs_attr_init(&hba->rpm_lvl_attr.attr); + hba->rpm_lvl_attr.attr.name = "rpm_lvl"; + hba->rpm_lvl_attr.attr.mode = S_IRUGO | S_IWUSR; + if (device_create_file(hba->dev, &hba->rpm_lvl_attr)) + dev_err(hba->dev, "Failed to create sysfs for rpm_lvl\n"); +} + +static ssize_t ufshcd_spm_lvl_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct ufs_hba *hba = dev_get_drvdata(dev); + int curr_len; + u8 lvl; + + curr_len = snprintf(buf, PAGE_SIZE, + "\nCurrent System PM level [%d] => dev_state [%s] link_state [%s]\n", + hba->spm_lvl, + ufschd_ufs_dev_pwr_mode_to_string( + ufs_pm_lvl_states[hba->spm_lvl].dev_state), + ufschd_uic_link_state_to_string( + ufs_pm_lvl_states[hba->spm_lvl].link_state)); + + curr_len += snprintf((buf + curr_len), (PAGE_SIZE - curr_len), + "\nAll available System PM levels info:\n"); + for (lvl = UFS_PM_LVL_0; lvl < UFS_PM_LVL_MAX; lvl++) + curr_len += snprintf((buf + curr_len), (PAGE_SIZE - curr_len), + "\tSystem PM level [%d] => dev_state [%s] link_state [%s]\n", + lvl, + ufschd_ufs_dev_pwr_mode_to_string( + ufs_pm_lvl_states[lvl].dev_state), + ufschd_uic_link_state_to_string( + ufs_pm_lvl_states[lvl].link_state)); + + return curr_len; +} + +static ssize_t ufshcd_spm_lvl_store(struct device *dev, + struct device_attribute *attr, const char *buf, size_t count) +{ + return ufshcd_pm_lvl_store(dev, attr, buf, count, false); +} + +static void ufshcd_add_spm_lvl_sysfs_nodes(struct ufs_hba *hba) +{ + hba->spm_lvl_attr.show = ufshcd_spm_lvl_show; + hba->spm_lvl_attr.store = ufshcd_spm_lvl_store; + sysfs_attr_init(&hba->spm_lvl_attr.attr); + hba->spm_lvl_attr.attr.name = "spm_lvl"; + hba->spm_lvl_attr.attr.mode = S_IRUGO | S_IWUSR; + if (device_create_file(hba->dev, &hba->spm_lvl_attr)) + dev_err(hba->dev, "Failed to create sysfs for spm_lvl\n"); +} + +static inline void ufshcd_add_sysfs_nodes(struct ufs_hba *hba) +{ + ufshcd_add_rpm_lvl_sysfs_nodes(hba); + ufshcd_add_spm_lvl_sysfs_nodes(hba); +} + +static void ufshcd_shutdown_clkscaling(struct ufs_hba *hba) +{ + bool suspend = false; + unsigned long flags; + + spin_lock_irqsave(hba->host->host_lock, flags); + if (hba->clk_scaling.is_allowed) { + hba->clk_scaling.is_allowed = false; + suspend = true; + } + spin_unlock_irqrestore(hba->host->host_lock, flags); + + /** + * Scaling may be scheduled before, hence make sure it + * doesn't race with shutdown + */ + if (ufshcd_is_clkscaling_supported(hba)) { + device_remove_file(hba->dev, &hba->clk_scaling.enable_attr); + cancel_work_sync(&hba->clk_scaling.suspend_work); + cancel_work_sync(&hba->clk_scaling.resume_work); + if (suspend) + ufshcd_suspend_clkscaling(hba); + } + + /* Unregister so that devfreq_monitor can't race with shutdown */ + if (hba->devfreq) + devfreq_remove_device(hba->devfreq); +} + /** * ufshcd_shutdown - shutdown routine * @hba: per adapter instance @@ -5326,12 +9270,25 @@ if (ufshcd_is_ufs_dev_poweroff(hba) && ufshcd_is_link_off(hba)) goto out; - if (pm_runtime_suspended(hba->dev)) { - ret = ufshcd_runtime_resume(hba); + pm_runtime_get_sync(hba->dev); + ufshcd_hold_all(hba); + ufshcd_mark_shutdown_ongoing(hba); + ufshcd_shutdown_clkscaling(hba); + /** + * (1) Acquire the lock to stop any more requests + * (2) Wait for all issued requests to complete + */ + ufshcd_get_write_lock(hba); + ufshcd_scsi_block_requests(hba); + ret = ufshcd_wait_for_doorbell_clr(hba, U64_MAX); if (ret) - goto out; - } - + dev_err(hba->dev, "%s: waiting for DB clear: failed: %d\n", + __func__, ret); + /* Requests may have errored out above, let it be handled */ + flush_work(&hba->eh_work); + /* reqs issued from contexts other than shutdown will fail from now */ + ufshcd_scsi_unblock_requests(hba); + ufshcd_release_all(hba); ret = ufshcd_suspend(hba, UFS_SHUTDOWN_PM); out: if (ret) @@ -5341,6 +9298,61 @@ } EXPORT_SYMBOL(ufshcd_shutdown); +/* + * Values permitted 0, 1, 2. + * 0 -> Disable IO latency histograms (default) + * 1 -> Enable IO latency histograms + * 2 -> Zero out IO latency histograms + */ +static ssize_t +latency_hist_store(struct device *dev, struct device_attribute *attr, + const char *buf, size_t count) +{ + struct ufs_hba *hba = dev_get_drvdata(dev); + long value; + + if (kstrtol(buf, 0, &value)) + return -EINVAL; + if (value == BLK_IO_LAT_HIST_ZERO) { + memset(&hba->io_lat_read, 0, sizeof(hba->io_lat_read)); + memset(&hba->io_lat_write, 0, sizeof(hba->io_lat_write)); + } else if (value == BLK_IO_LAT_HIST_ENABLE || + value == BLK_IO_LAT_HIST_DISABLE) + hba->latency_hist_enabled = value; + return count; +} + +ssize_t +latency_hist_show(struct device *dev, struct device_attribute *attr, + char *buf) +{ + struct ufs_hba *hba = dev_get_drvdata(dev); + size_t written_bytes; + + written_bytes = blk_latency_hist_show("Read", &hba->io_lat_read, + buf, PAGE_SIZE); + written_bytes += blk_latency_hist_show("Write", &hba->io_lat_write, + buf + written_bytes, PAGE_SIZE - written_bytes); + + return written_bytes; +} + +static DEVICE_ATTR(latency_hist, S_IRUGO | S_IWUSR, + latency_hist_show, latency_hist_store); + +static void +ufshcd_init_latency_hist(struct ufs_hba *hba) +{ + if (device_create_file(hba->dev, &dev_attr_latency_hist)) + dev_err(hba->dev, "Failed to create latency_hist sysfs entry\n"); +} + +static void +ufshcd_exit_latency_hist(struct ufs_hba *hba) +{ + device_create_file(hba->dev, &dev_attr_latency_hist); +} + /** * ufshcd_remove - de-allocate SCSI host and host memory space * data structure memory @@ -5351,14 +9363,17 @@ scsi_remove_host(hba->host); /* disable interrupts */ ufshcd_disable_intr(hba, hba->intr_mask); - ufshcd_hba_stop(hba); - - scsi_host_put(hba->host); + ufshcd_hba_stop(hba, true); ufshcd_exit_clk_gating(hba); - if (ufshcd_is_clkscaling_enabled(hba)) + ufshcd_exit_hibern8_on_idle(hba); + if (ufshcd_is_clkscaling_supported(hba)) { + device_remove_file(hba->dev, &hba->clk_scaling.enable_attr); + ufshcd_exit_latency_hist(hba); devfreq_remove_device(hba->devfreq); + } ufshcd_hba_exit(hba); + ufsdbg_remove_debugfs(hba); } EXPORT_SYMBOL_GPL(ufshcd_remove); @@ -5424,71 +9439,400 @@ } EXPORT_SYMBOL(ufshcd_alloc_host); -static int ufshcd_scale_clks(struct ufs_hba *hba, bool scale_up) +/** + * ufshcd_is_devfreq_scaling_required - check if scaling is required or not + * @hba: per adapter instance + * @scale_up: True if scaling up and false if scaling down + * + * Returns true if scaling is required, false otherwise. + */ +static bool ufshcd_is_devfreq_scaling_required(struct ufs_hba *hba, + bool scale_up) { - int ret = 0; struct ufs_clk_info *clki; struct list_head *head = &hba->clk_list_head; if (!head || list_empty(head)) - goto out; - - ret = ufshcd_vops_clk_scale_notify(hba, scale_up, PRE_CHANGE); - if (ret) - return ret; + return false; list_for_each_entry(clki, head, list) { if (!IS_ERR_OR_NULL(clki->clk)) { if (scale_up && clki->max_freq) { if (clki->curr_freq == clki->max_freq) continue; - ret = clk_set_rate(clki->clk, clki->max_freq); - if (ret) { - dev_err(hba->dev, "%s: %s clk set rate(%dHz) failed, %d\n", - __func__, clki->name, - clki->max_freq, ret); - break; - } - clki->curr_freq = clki->max_freq; - + return true; } else if (!scale_up && clki->min_freq) { if (clki->curr_freq == clki->min_freq) continue; - ret = clk_set_rate(clki->clk, clki->min_freq); - if (ret) { - dev_err(hba->dev, "%s: %s clk set rate(%dHz) failed, %d\n", - __func__, clki->name, - clki->min_freq, ret); - break; + return true; } - clki->curr_freq = clki->min_freq; } } - dev_dbg(hba->dev, "%s: clk: %s, rate: %lu\n", __func__, - clki->name, clk_get_rate(clki->clk)); + + return false; } - ret = ufshcd_vops_clk_scale_notify(hba, scale_up, POST_CHANGE); +/** + * ufshcd_scale_gear - scale up/down UFS gear + * @hba: per adapter instance + * @scale_up: True for scaling up gear and false for scaling down + * + * Returns 0 for success, + * Returns -EBUSY if scaling can't happen at this time + * Returns non-zero for any other errors + */ +static int ufshcd_scale_gear(struct ufs_hba *hba, bool scale_up) +{ + int ret = 0; + struct ufs_pa_layer_attr new_pwr_info; + u32 scale_down_gear = ufshcd_vops_get_scale_down_gear(hba); + + BUG_ON(!hba->clk_scaling.saved_pwr_info.is_valid); + + if (scale_up) { + memcpy(&new_pwr_info, &hba->clk_scaling.saved_pwr_info.info, + sizeof(struct ufs_pa_layer_attr)); + /* + * Some UFS devices may stop responding after switching from + * HS-G1 to HS-G3. Also, it is found that these devices work + * fine if we do 2 steps switch: HS-G1 to HS-G2 followed by + * HS-G2 to HS-G3. If UFS_DEVICE_QUIRK_HS_G1_TO_HS_G3_SWITCH + * quirk is enabled for such devices, this 2 steps gear switch + * workaround will be applied. + */ + if ((hba->dev_quirks & UFS_DEVICE_QUIRK_HS_G1_TO_HS_G3_SWITCH) + && (hba->pwr_info.gear_tx == UFS_HS_G1) + && (new_pwr_info.gear_tx == UFS_HS_G3)) { + /* scale up to G2 first */ + new_pwr_info.gear_tx = UFS_HS_G2; + new_pwr_info.gear_rx = UFS_HS_G2; + ret = ufshcd_change_power_mode(hba, &new_pwr_info); + if (ret) + goto out; + + /* scale up to G3 now */ + new_pwr_info.gear_tx = UFS_HS_G3; + new_pwr_info.gear_rx = UFS_HS_G3; + /* now, fall through to set the HS-G3 */ + } + ret = ufshcd_change_power_mode(hba, &new_pwr_info); + if (ret) + goto out; + } else { + memcpy(&new_pwr_info, &hba->pwr_info, + sizeof(struct ufs_pa_layer_attr)); + + if (hba->pwr_info.gear_tx > scale_down_gear + || hba->pwr_info.gear_rx > scale_down_gear) { + /* save the current power mode */ + memcpy(&hba->clk_scaling.saved_pwr_info.info, + &hba->pwr_info, + sizeof(struct ufs_pa_layer_attr)); + + /* scale down gear */ + new_pwr_info.gear_tx = scale_down_gear; + new_pwr_info.gear_rx = scale_down_gear; + if (!(hba->dev_quirks & UFS_DEVICE_NO_FASTAUTO)) { + new_pwr_info.pwr_tx = FASTAUTO_MODE; + new_pwr_info.pwr_rx = FASTAUTO_MODE; + } + } + ret = ufshcd_change_power_mode(hba, &new_pwr_info); + } + +out: + if (ret) + dev_err(hba->dev, "%s: failed err %d, old gear: (tx %d rx %d), new gear: (tx %d rx %d), scale_up = %d", + __func__, ret, + hba->pwr_info.gear_tx, hba->pwr_info.gear_rx, + new_pwr_info.gear_tx, new_pwr_info.gear_rx, + scale_up); + + return ret; +} + +static int ufshcd_clock_scaling_prepare(struct ufs_hba *hba) +{ + #define DOORBELL_CLR_TOUT_US (1000 * 1000) /* 1 sec */ + int ret = 0; + /* + * make sure that there are no outstanding requests when + * clock scaling is in progress + */ + ufshcd_scsi_block_requests(hba); + down_write(&hba->lock); + if (ufshcd_wait_for_doorbell_clr(hba, DOORBELL_CLR_TOUT_US)) { + ret = -EBUSY; + up_write(&hba->lock); + ufshcd_scsi_unblock_requests(hba); + } + + return ret; +} + +static void ufshcd_clock_scaling_unprepare(struct ufs_hba *hba) +{ + up_write(&hba->lock); + ufshcd_scsi_unblock_requests(hba); +} + +/** + * ufshcd_devfreq_scale - scale up/down UFS clocks and gear + * @hba: per adapter instance + * @scale_up: True for scaling up and false for scalin down + * + * Returns 0 for success, + * Returns -EBUSY if scaling can't happen at this time + * Returns non-zero for any other errors + */ +static int ufshcd_devfreq_scale(struct ufs_hba *hba, bool scale_up) +{ + int ret = 0; + + /* let's not get into low power until clock scaling is completed */ + hba->ufs_stats.clk_hold.ctx = CLK_SCALE_WORK; + ufshcd_hold_all(hba); + + ret = ufshcd_clock_scaling_prepare(hba); + if (ret) + goto out; + + /* scale down the gear before scaling down clocks */ + if (!scale_up) { + ret = ufshcd_scale_gear(hba, false); + if (ret) + goto clk_scaling_unprepare; + } + + /* + * If auto hibern8 is supported then put the link in + * hibern8 manually, this is to avoid auto hibern8 + * racing during clock frequency scaling sequence. + */ + if (ufshcd_is_auto_hibern8_supported(hba)) { + ret = ufshcd_uic_hibern8_enter(hba); + if (ret) + /* link will be bad state so no need to scale_up_gear */ + return ret; + } + + ret = ufshcd_scale_clks(hba, scale_up); + if (ret) + goto scale_up_gear; + if (ufshcd_is_auto_hibern8_supported(hba)) { + ret = ufshcd_uic_hibern8_exit(hba); + if (ret) + /* link will be bad state so no need to scale_up_gear */ + return ret; + } + + /* scale up the gear after scaling up clocks */ + if (scale_up) { + ret = ufshcd_scale_gear(hba, true); + if (ret) { + ufshcd_scale_clks(hba, false); + goto clk_scaling_unprepare; + } + } + + if (!ret) { + hba->clk_scaling.is_scaled_up = scale_up; + if (scale_up) + hba->clk_gating.delay_ms = + hba->clk_gating.delay_ms_perf; + else + hba->clk_gating.delay_ms = + hba->clk_gating.delay_ms_pwr_save; + } + + goto clk_scaling_unprepare; + +scale_up_gear: + if (!scale_up) + ufshcd_scale_gear(hba, true); +clk_scaling_unprepare: + ufshcd_clock_scaling_unprepare(hba); out: + hba->ufs_stats.clk_rel.ctx = CLK_SCALE_WORK; + ufshcd_release_all(hba); return ret; } +static void __ufshcd_suspend_clkscaling(struct ufs_hba *hba) +{ + unsigned long flags; + + devfreq_suspend_device(hba->devfreq); + spin_lock_irqsave(hba->host->host_lock, flags); + hba->clk_scaling.window_start_t = 0; + spin_unlock_irqrestore(hba->host->host_lock, flags); +} + +static void ufshcd_suspend_clkscaling(struct ufs_hba *hba) +{ + unsigned long flags; + bool suspend = false; + + if (!ufshcd_is_clkscaling_supported(hba)) + return; + + spin_lock_irqsave(hba->host->host_lock, flags); + if (!hba->clk_scaling.is_suspended) { + suspend = true; + hba->clk_scaling.is_suspended = true; + } + spin_unlock_irqrestore(hba->host->host_lock, flags); + + if (suspend) + __ufshcd_suspend_clkscaling(hba); +} + +static void ufshcd_resume_clkscaling(struct ufs_hba *hba) +{ + unsigned long flags; + bool resume = false; + + if (!ufshcd_is_clkscaling_supported(hba)) + return; + + spin_lock_irqsave(hba->host->host_lock, flags); + if (hba->clk_scaling.is_suspended) { + resume = true; + hba->clk_scaling.is_suspended = false; + } + spin_unlock_irqrestore(hba->host->host_lock, flags); + + if (resume) + devfreq_resume_device(hba->devfreq); +} + +static ssize_t ufshcd_clkscale_enable_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct ufs_hba *hba = dev_get_drvdata(dev); + + return snprintf(buf, PAGE_SIZE, "%d\n", hba->clk_scaling.is_allowed); +} + +static ssize_t ufshcd_clkscale_enable_store(struct device *dev, + struct device_attribute *attr, const char *buf, size_t count) +{ + struct ufs_hba *hba = dev_get_drvdata(dev); + u32 value; + int err; + + if (kstrtou32(buf, 0, &value)) + return -EINVAL; + + value = !!value; + if (value == hba->clk_scaling.is_allowed) + goto out; + + pm_runtime_get_sync(hba->dev); + ufshcd_hold(hba, false); + + cancel_work_sync(&hba->clk_scaling.suspend_work); + cancel_work_sync(&hba->clk_scaling.resume_work); + + hba->clk_scaling.is_allowed = value; + + if (value) { + ufshcd_resume_clkscaling(hba); + } else { + ufshcd_suspend_clkscaling(hba); + err = ufshcd_devfreq_scale(hba, true); + if (err) + dev_err(hba->dev, "%s: failed to scale clocks up %d\n", + __func__, err); + } + + ufshcd_release(hba, false); + pm_runtime_put_sync(hba->dev); +out: + return count; +} + +static void ufshcd_clk_scaling_suspend_work(struct work_struct *work) +{ + struct ufs_hba *hba = container_of(work, struct ufs_hba, + clk_scaling.suspend_work); + unsigned long irq_flags; + + spin_lock_irqsave(hba->host->host_lock, irq_flags); + if (hba->clk_scaling.active_reqs || hba->clk_scaling.is_suspended) { + spin_unlock_irqrestore(hba->host->host_lock, irq_flags); + return; + } + hba->clk_scaling.is_suspended = true; + spin_unlock_irqrestore(hba->host->host_lock, irq_flags); + + __ufshcd_suspend_clkscaling(hba); +} + +static void ufshcd_clk_scaling_resume_work(struct work_struct *work) +{ + struct ufs_hba *hba = container_of(work, struct ufs_hba, + clk_scaling.resume_work); + unsigned long irq_flags; + + spin_lock_irqsave(hba->host->host_lock, irq_flags); + if (!hba->clk_scaling.is_suspended) { + spin_unlock_irqrestore(hba->host->host_lock, irq_flags); + return; + } + hba->clk_scaling.is_suspended = false; + spin_unlock_irqrestore(hba->host->host_lock, irq_flags); + + devfreq_resume_device(hba->devfreq); +} + static int ufshcd_devfreq_target(struct device *dev, unsigned long *freq, u32 flags) { - int err = 0; + int ret = 0; struct ufs_hba *hba = dev_get_drvdata(dev); + unsigned long irq_flags; + ktime_t start; + bool scale_up, sched_clk_scaling_suspend_work = false; - if (!ufshcd_is_clkscaling_enabled(hba)) + if (!ufshcd_is_clkscaling_supported(hba)) return -EINVAL; - if (*freq == UINT_MAX) - err = ufshcd_scale_clks(hba, true); - else if (*freq == 0) - err = ufshcd_scale_clks(hba, false); + if ((*freq > 0) && (*freq < UINT_MAX)) { + dev_err(hba->dev, "%s: invalid freq = %lu\n", __func__, *freq); + return -EINVAL; + } - return err; + spin_lock_irqsave(hba->host->host_lock, irq_flags); + if (ufshcd_eh_in_progress(hba)) { + spin_unlock_irqrestore(hba->host->host_lock, irq_flags); + return 0; + } + + if (!hba->clk_scaling.active_reqs) + sched_clk_scaling_suspend_work = true; + + scale_up = (*freq == UINT_MAX) ? true : false; + if (!ufshcd_is_devfreq_scaling_required(hba, scale_up)) { + spin_unlock_irqrestore(hba->host->host_lock, irq_flags); + ret = 0; + goto out; /* no state change required */ + } + spin_unlock_irqrestore(hba->host->host_lock, irq_flags); + + start = ktime_get(); + ret = ufshcd_devfreq_scale(hba, scale_up); + trace_ufshcd_profile_clk_scaling(dev_name(hba->dev), + (scale_up ? "up" : "down"), + ktime_to_us(ktime_sub(ktime_get(), start)), ret); + +out: + if (sched_clk_scaling_suspend_work) + queue_work(hba->clk_scaling.workq, + &hba->clk_scaling.suspend_work); + + return ret; } static int ufshcd_devfreq_get_dev_status(struct device *dev, @@ -5498,7 +9842,7 @@ struct ufs_clk_scaling *scaling = &hba->clk_scaling; unsigned long flags; - if (!ufshcd_is_clkscaling_enabled(hba)) + if (!ufshcd_is_clkscaling_supported(hba)) return -EINVAL; memset(stat, 0, sizeof(*stat)); @@ -5529,12 +9873,31 @@ return 0; } -static struct devfreq_dev_profile ufs_devfreq_profile = { - .polling_ms = 100, - .target = ufshcd_devfreq_target, - .get_dev_status = ufshcd_devfreq_get_dev_status, -}; +static void ufshcd_clkscaling_init_sysfs(struct ufs_hba *hba) +{ + hba->clk_scaling.enable_attr.show = ufshcd_clkscale_enable_show; + hba->clk_scaling.enable_attr.store = ufshcd_clkscale_enable_store; + sysfs_attr_init(&hba->clk_scaling.enable_attr.attr); + hba->clk_scaling.enable_attr.attr.name = "clkscale_enable"; + hba->clk_scaling.enable_attr.attr.mode = S_IRUGO | S_IWUSR; + if (device_create_file(hba->dev, &hba->clk_scaling.enable_attr)) + dev_err(hba->dev, "Failed to create sysfs for clkscale_enable\n"); +} + +static void ufshcd_init_lanes_per_dir(struct ufs_hba *hba) +{ + struct device *dev = hba->dev; + int ret; + ret = of_property_read_u32(dev->of_node, "lanes-per-direction", + &hba->lanes_per_direction); + if (ret) { + dev_dbg(hba->dev, + "%s: failed to read lanes-per-direction, ret=%d\n", + __func__, ret); + hba->lanes_per_direction = UFSHCD_DEFAULT_LANES_PER_DIRECTION; + } +} /** * ufshcd_init - Driver initialization routine * @hba: per-adapter instance @@ -5558,6 +9921,8 @@ hba->mmio_base = mmio_base; hba->irq = irq; + ufshcd_init_lanes_per_dir(hba); + err = ufshcd_hba_init(hba); if (err) goto out_error; @@ -5568,9 +9933,20 @@ /* Get UFS version supported by the controller */ hba->ufs_version = ufshcd_get_ufs_version(hba); + /* print error message if ufs_version is not valid */ + if ((hba->ufs_version != UFSHCI_VERSION_10) && + (hba->ufs_version != UFSHCI_VERSION_11) && + (hba->ufs_version != UFSHCI_VERSION_20) && + (hba->ufs_version != UFSHCI_VERSION_21)) + dev_err(hba->dev, "invalid UFS version 0x%x\n", + hba->ufs_version); + /* Get Interrupt bit mask per version */ hba->intr_mask = ufshcd_get_intr_mask(hba); + /* Enable debug prints */ + hba->ufshcd_dbg_print = DEFAULT_UFSHCD_DBG_PRINT_EN; + err = ufshcd_set_dma_mask(hba); if (err) { dev_err(hba->dev, "set dma mask failed\n"); @@ -5594,6 +9970,7 @@ host->max_channel = UFSHCD_MAX_CHANNEL; host->unique_id = host->host_no; host->max_cmd_len = MAX_CDB_SIZE; + host->set_dbd_for_caching = 1; hba->max_pwr_info.is_valid = false; @@ -5604,6 +9981,7 @@ /* Initialize work queues */ INIT_WORK(&hba->eh_work, ufshcd_err_handler); INIT_WORK(&hba->eeh_work, ufshcd_exception_event_handler); + INIT_WORK(&hba->rls_work, ufshcd_rls_handler); /* Initialize UIC command mutex */ mutex_init(&hba->uic_cmd_mutex); @@ -5611,10 +9989,28 @@ /* Initialize mutex for device management commands */ mutex_init(&hba->dev_cmd.lock); + init_rwsem(&hba->lock); + /* Initialize device management tag acquire wait queue */ init_waitqueue_head(&hba->dev_cmd.tag_wq); ufshcd_init_clk_gating(hba); + ufshcd_init_hibern8_on_idle(hba); + + /* + * In order to avoid any spurious interrupt immediately after + * registering UFS controller interrupt handler, clear any pending UFS + * interrupt status and disable all the UFS interrupts. + */ + ufshcd_writel(hba, ufshcd_readl(hba, REG_INTERRUPT_STATUS), + REG_INTERRUPT_STATUS); + ufshcd_writel(hba, 0, REG_INTERRUPT_ENABLE); + /* + * Make sure that UFS interrupts are disabled and any pending interrupt + * status is cleared before registering UFS interrupt handler. + */ + mb(); + /* IRQ registration */ err = devm_request_irq(dev, irq, ufshcd_intr, IRQF_SHARED, UFSHCD, hba); if (err) { @@ -5630,46 +10026,84 @@ goto exit_gating; } + /* Reset controller to power on reset (POR) state */ + ufshcd_vops_full_reset(hba); + + /* reset connected UFS device */ + err = ufshcd_reset_device(hba); + if (err) + dev_warn(hba->dev, "%s: device reset failed. err %d\n", + __func__, err); + /* Host controller enable */ err = ufshcd_hba_enable(hba); if (err) { dev_err(hba->dev, "Host controller enable failed\n"); + ufshcd_print_host_regs(hba); + ufshcd_print_host_state(hba); goto out_remove_scsi_host; } - if (ufshcd_is_clkscaling_enabled(hba)) { - hba->devfreq = devfreq_add_device(dev, &ufs_devfreq_profile, - "simple_ondemand", NULL); - if (IS_ERR(hba->devfreq)) { - dev_err(hba->dev, "Unable to register with devfreq %ld\n", - PTR_ERR(hba->devfreq)); - goto out_remove_scsi_host; - } - /* Suspend devfreq until the UFS device is detected */ - devfreq_suspend_device(hba->devfreq); - hba->clk_scaling.window_start_t = 0; + if (ufshcd_is_clkscaling_supported(hba)) { + char wq_name[sizeof("ufs_clkscaling_00")]; + + INIT_WORK(&hba->clk_scaling.suspend_work, + ufshcd_clk_scaling_suspend_work); + INIT_WORK(&hba->clk_scaling.resume_work, + ufshcd_clk_scaling_resume_work); + + snprintf(wq_name, ARRAY_SIZE(wq_name), "ufs_clkscaling_%d", + host->host_no); + hba->clk_scaling.workq = create_singlethread_workqueue(wq_name); + + ufshcd_clkscaling_init_sysfs(hba); } + /* + * If rpm_lvl and and spm_lvl are not already set to valid levels, + * set the default power management level for UFS runtime and system + * suspend. Default power saving mode selected is keeping UFS link in + * Hibern8 state and UFS device in sleep. + */ + if (!ufshcd_is_valid_pm_lvl(hba->rpm_lvl)) + hba->rpm_lvl = ufs_get_desired_pm_lvl_for_dev_link_state( + UFS_SLEEP_PWR_MODE, + UIC_LINK_HIBERN8_STATE); + if (!ufshcd_is_valid_pm_lvl(hba->spm_lvl)) + hba->spm_lvl = ufs_get_desired_pm_lvl_for_dev_link_state( + UFS_SLEEP_PWR_MODE, + UIC_LINK_HIBERN8_STATE); + /* Hold auto suspend until async scan completes */ pm_runtime_get_sync(dev); + ufshcd_init_latency_hist(hba); + /* - * The device-initialize-sequence hasn't been invoked yet. - * Set the device to power-off state + * We are assuming that device wasn't put in sleep/power-down + * state exclusively during the boot stage before kernel. + * This assumption helps avoid doing link startup twice during + * ufshcd_probe_hba(). */ - ufshcd_set_ufs_dev_poweroff(hba); + ufshcd_set_ufs_dev_active(hba); + + ufshcd_cmd_log_init(hba); async_schedule(ufshcd_async_scan, hba); + ufsdbg_add_debugfs(hba); + + ufshcd_add_sysfs_nodes(hba); + return 0; out_remove_scsi_host: scsi_remove_host(hba->host); exit_gating: ufshcd_exit_clk_gating(hba); + ufshcd_exit_latency_hist(hba); out_disable: hba->is_irq_enabled = false; - scsi_host_put(host); ufshcd_hba_exit(hba); out_error: return err; diff -ruw linux-4.4.115/drivers/scsi/ufs/ufshcd.h linux-4.4.115-fbx/drivers/scsi/ufs/ufshcd.h --- linux-4.4.115/drivers/scsi/ufs/ufshcd.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/scsi/ufs/ufshcd.h 2019-01-22 16:16:26.635274769 +0100 @@ -3,6 +3,7 @@ * * This code is based on drivers/scsi/ufs/ufshcd.h * Copyright (C) 2011-2013 Samsung India Software Operations + * Copyright (c) 2013-2017, The Linux Foundation. All rights reserved. * * Authors: * Santosh Yaraganavi @@ -38,12 +39,14 @@ #include #include +#include #include #include #include #include #include #include +#include #include #include #include @@ -53,6 +56,8 @@ #include #include #include +#include +#include "unipro.h" #include #include @@ -63,11 +68,15 @@ #include #include +#include #include "ufs.h" #include "ufshci.h" #define UFSHCD "ufshcd" -#define UFSHCD_DRIVER_VERSION "0.2" +#define UFSHCD_DRIVER_VERSION "0.3" + +#define UFS_BIT(x) BIT(x) +#define UFS_MASK(x, y) (x << ((y) % BITS_PER_LONG)) struct ufs_hba; @@ -125,6 +134,26 @@ #define ufshcd_set_link_hibern8(hba) ((hba)->uic_link_state = \ UIC_LINK_HIBERN8_STATE) +enum { + /* errors which require the host controller reset for recovery */ + UFS_ERR_HIBERN8_EXIT, + UFS_ERR_VOPS_SUSPEND, + UFS_ERR_EH, + UFS_ERR_CLEAR_PEND_XFER_TM, + UFS_ERR_INT_FATAL_ERRORS, + UFS_ERR_INT_UIC_ERROR, + UFS_ERR_CRYPTO_ENGINE, + + /* other errors */ + UFS_ERR_HIBERN8_ENTER, + UFS_ERR_RESUME, + UFS_ERR_SUSPEND, + UFS_ERR_LINKSTARTUP, + UFS_ERR_POWER_MODE_CHANGE, + UFS_ERR_TASK_ABORT, + UFS_ERR_MAX, +}; + /* * UFS Power management levels. * Each level is in increasing order of power savings. @@ -150,6 +179,10 @@ * @ucd_req_ptr: UCD address of the command * @ucd_rsp_ptr: Response UPIU address for this command * @ucd_prdt_ptr: PRDT address of the command + * @utrd_dma_addr: UTRD dma address for debug + * @ucd_prdt_dma_addr: PRDT dma address for debug + * @ucd_rsp_dma_addr: UPIU response dma address for debug + * @ucd_req_dma_addr: UPIU request dma address for debug * @cmd: pointer to SCSI command * @sense_buffer: pointer to sense buffer address of the SCSI command * @sense_bufflen: Length of the sense buffer @@ -158,6 +191,9 @@ * @task_tag: Task tag of the command * @lun: LUN of the command * @intr_cmd: Interrupt command (doesn't participate in interrupt aggregation) + * @issue_time_stamp: time stamp for debug purposes + * @complete_time_stamp: time stamp for statistics + * @req_abort_skip: skip request abort task flag */ struct ufshcd_lrb { struct utp_transfer_req_desc *utr_descriptor_ptr; @@ -165,6 +201,11 @@ struct utp_upiu_rsp *ucd_rsp_ptr; struct ufshcd_sg_entry *ucd_prdt_ptr; + dma_addr_t utrd_dma_addr; + dma_addr_t ucd_req_dma_addr; + dma_addr_t ucd_rsp_dma_addr; + dma_addr_t ucd_prdt_dma_addr; + struct scsi_cmnd *cmd; u8 *sense_buffer; unsigned int sense_bufflen; @@ -174,6 +215,10 @@ int task_tag; u8 lun; /* UPIU LUN id field is only 8-bit wide */ bool intr_cmd; + ktime_t issue_time_stamp; + ktime_t complete_time_stamp; + + bool req_abort_skip; }; /** @@ -245,7 +290,6 @@ /** * struct ufs_hba_variant_ops - variant specific callbacks - * @name: variant name * @init: called when the driver is initialized * @exit: called to cleanup everything done in init * @get_ufs_hci_version: called to get UFS HCI version @@ -261,16 +305,23 @@ * to be set. * @suspend: called during host controller PM callback * @resume: called during host controller PM callback + * @full_reset: called during link recovery for handling variant specific + * implementations of resetting the hci * @dbg_register_dump: used to dump controller debug information + * @update_sec_cfg: called to restore host controller secure configuration + * @get_scale_down_gear: called to get the minimum supported gear to + * scale down + * @set_bus_vote: called to vote for the required bus bandwidth + * @add_debugfs: used to add debugfs entries + * @remove_debugfs: used to remove debugfs entries */ struct ufs_hba_variant_ops { - const char *name; int (*init)(struct ufs_hba *); void (*exit)(struct ufs_hba *); u32 (*get_ufs_hci_version)(struct ufs_hba *); int (*clk_scale_notify)(struct ufs_hba *, bool, enum ufs_notify_change_status); - int (*setup_clocks)(struct ufs_hba *, bool); + int (*setup_clocks)(struct ufs_hba *, bool, bool); int (*setup_regulators)(struct ufs_hba *, bool); int (*hce_enable_notify)(struct ufs_hba *, enum ufs_notify_change_status); @@ -280,9 +331,60 @@ enum ufs_notify_change_status status, struct ufs_pa_layer_attr *, struct ufs_pa_layer_attr *); + int (*apply_dev_quirks)(struct ufs_hba *); int (*suspend)(struct ufs_hba *, enum ufs_pm_op); int (*resume)(struct ufs_hba *, enum ufs_pm_op); - void (*dbg_register_dump)(struct ufs_hba *hba); + int (*full_reset)(struct ufs_hba *); + void (*dbg_register_dump)(struct ufs_hba *hba, bool no_sleep); + int (*update_sec_cfg)(struct ufs_hba *hba, bool restore_sec_cfg); + u32 (*get_scale_down_gear)(struct ufs_hba *); + int (*set_bus_vote)(struct ufs_hba *, bool); +#ifdef CONFIG_DEBUG_FS + void (*add_debugfs)(struct ufs_hba *hba, struct dentry *root); + void (*remove_debugfs)(struct ufs_hba *hba); +#endif +}; + +/** + * struct ufs_hba_crypto_variant_ops - variant specific crypto callbacks + * @crypto_req_setup: retreieve the necessary cryptographic arguments to setup + a requests's transfer descriptor. + * @crypto_engine_cfg_start: start configuring cryptographic engine + * according to tag + * parameter + * @crypto_engine_cfg_end: end configuring cryptographic engine + * according to tag parameter + * @crypto_engine_reset: perform reset to the cryptographic engine + * @crypto_engine_get_status: get errors status of the cryptographic engine + */ +struct ufs_hba_crypto_variant_ops { + int (*crypto_req_setup)(struct ufs_hba *, struct ufshcd_lrb *lrbp, + u8 *cc_index, bool *enable, u64 *dun); + int (*crypto_engine_cfg_start)(struct ufs_hba *, unsigned int); + int (*crypto_engine_cfg_end)(struct ufs_hba *, struct ufshcd_lrb *, + struct request *); + int (*crypto_engine_reset)(struct ufs_hba *); + int (*crypto_engine_get_status)(struct ufs_hba *, u32 *); +}; + +/** +* struct ufs_hba_pm_qos_variant_ops - variant specific PM QoS callbacks +*/ +struct ufs_hba_pm_qos_variant_ops { + void (*req_start)(struct ufs_hba *, struct request *); + void (*req_end)(struct ufs_hba *, struct request *, bool); +}; + +/** + * struct ufs_hba_variant - variant specific parameters + * @name: variant name + */ +struct ufs_hba_variant { + struct device *dev; + const char *name; + struct ufs_hba_variant_ops *vops; + struct ufs_hba_crypto_variant_ops *crypto_vops; + struct ufs_hba_pm_qos_variant_ops *pm_qos_vops; }; /* clock gating state */ @@ -295,33 +397,117 @@ /** * struct ufs_clk_gating - UFS clock gating related info - * @gate_work: worker to turn off clocks after some delay as specified in - * delay_ms + * @gate_hrtimer: hrtimer to invoke @gate_work after some delay as + * specified in @delay_ms + * @gate_work: worker to turn off clocks * @ungate_work: worker to turn on clocks that will be used in case of * interrupt context * @state: the current clocks state - * @delay_ms: gating delay in ms + * @delay_ms: current gating delay in ms + * @delay_ms_pwr_save: gating delay (in ms) in power save mode + * @delay_ms_perf: gating delay (in ms) in performance mode * @is_suspended: clk gating is suspended when set to 1 which can be used * during suspend/resume - * @delay_attr: sysfs attribute to control delay_attr + * @delay_attr: sysfs attribute to control delay_ms if clock scaling is disabled + * @delay_pwr_save_attr: sysfs attribute to control delay_ms_pwr_save + * @delay_perf_attr: sysfs attribute to control delay_ms_perf + * @enable_attr: sysfs attribute to enable/disable clock gating + * @is_enabled: Indicates the current status of clock gating * @active_reqs: number of requests that are pending and should be waited for * completion before gating clocks. */ struct ufs_clk_gating { - struct delayed_work gate_work; + struct hrtimer gate_hrtimer; + struct work_struct gate_work; struct work_struct ungate_work; enum clk_gating_state state; unsigned long delay_ms; + unsigned long delay_ms_pwr_save; + unsigned long delay_ms_perf; bool is_suspended; struct device_attribute delay_attr; + struct device_attribute delay_pwr_save_attr; + struct device_attribute delay_perf_attr; + struct device_attribute enable_attr; + bool is_enabled; + int active_reqs; + struct workqueue_struct *clk_gating_workq; +}; + +/* Hibern8 state */ +enum ufshcd_hibern8_on_idle_state { + HIBERN8_ENTERED, + HIBERN8_EXITED, + REQ_HIBERN8_ENTER, + REQ_HIBERN8_EXIT, + AUTO_HIBERN8, +}; + +/** + * struct ufs_hibern8_on_idle - UFS Hibern8 on idle related data + * @enter_work: worker to put UFS link in hibern8 after some delay as + * specified in delay_ms + * @exit_work: worker to bring UFS link out of hibern8 + * @state: the current hibern8 state + * @delay_ms: hibern8 enter delay in ms + * @is_suspended: hibern8 enter is suspended when set to 1 which can be used + * during suspend/resume + * @active_reqs: number of requests that are pending and should be waited for + * completion before scheduling delayed "enter_work". + * @delay_attr: sysfs attribute to control delay_attr + * @enable_attr: sysfs attribute to enable/disable hibern8 on idle + * @is_enabled: Indicates the current status of hibern8 + */ +struct ufs_hibern8_on_idle { + struct delayed_work enter_work; + struct work_struct exit_work; + enum ufshcd_hibern8_on_idle_state state; + unsigned long delay_ms; + bool is_suspended; int active_reqs; + struct device_attribute delay_attr; + struct device_attribute enable_attr; + bool is_enabled; +}; + +struct ufs_saved_pwr_info { + struct ufs_pa_layer_attr info; + bool is_valid; }; +/** + * struct ufs_clk_scaling - UFS clock scaling related data + * @active_reqs: number of requests that are pending. If this is zero when + * devfreq ->target() function is called then schedule "suspend_work" to + * suspend devfreq. + * @tot_busy_t: Total busy time in current polling window + * @window_start_t: Start time (in jiffies) of the current polling window + * @busy_start_t: Start time of current busy period + * @enable_attr: sysfs attribute to enable/disable clock scaling + * @saved_pwr_info: UFS power mode may also be changed during scaling and this + * one keeps track of previous power mode. + * @workq: workqueue to schedule devfreq suspend/resume work + * @suspend_work: worker to suspend devfreq + * @resume_work: worker to resume devfreq + * @is_allowed: tracks if scaling is currently allowed or not + * @is_busy_started: tracks if busy period has started or not + * @is_suspended: tracks if devfreq is suspended or not + * @is_scaled_up: tracks if we are currently scaled up or scaled down + */ struct ufs_clk_scaling { - ktime_t busy_start_t; - bool is_busy_started; + int active_reqs; unsigned long tot_busy_t; unsigned long window_start_t; + ktime_t busy_start_t; + struct device_attribute enable_attr; + struct ufs_saved_pwr_info saved_pwr_info; + struct workqueue_struct *workq; + struct work_struct suspend_work; + struct work_struct resume_work; + bool is_allowed; + bool is_busy_started; + bool is_suspended; + bool is_scaled_up; }; /** @@ -333,6 +519,170 @@ u32 icc_level; }; +#define UIC_ERR_REG_HIST_LENGTH 20 +/** + * struct ufs_uic_err_reg_hist - keeps history of uic errors + * @pos: index to indicate cyclic buffer position + * @reg: cyclic buffer for registers value + * @tstamp: cyclic buffer for time stamp + */ +struct ufs_uic_err_reg_hist { + int pos; + u32 reg[UIC_ERR_REG_HIST_LENGTH]; + ktime_t tstamp[UIC_ERR_REG_HIST_LENGTH]; +}; + +#ifdef CONFIG_DEBUG_FS +struct debugfs_files { + struct dentry *debugfs_root; + struct dentry *stats_folder; + struct dentry *tag_stats; + struct dentry *err_stats; + struct dentry *show_hba; + struct dentry *host_regs; + struct dentry *dump_dev_desc; + struct dentry *power_mode; + struct dentry *dme_local_read; + struct dentry *dme_peer_read; + struct dentry *dbg_print_en; + struct dentry *req_stats; + struct dentry *query_stats; + u32 dme_local_attr_id; + u32 dme_peer_attr_id; + struct dentry *reset_controller; + struct dentry *err_state; + bool err_occurred; +#ifdef CONFIG_UFS_FAULT_INJECTION + struct dentry *err_inj_scenario; + struct dentry *err_inj_stats; + u32 err_inj_scenario_mask; + struct fault_attr fail_attr; +#endif + bool is_sys_suspended; +}; + +/* tag stats statistics types */ +enum ts_types { + TS_NOT_SUPPORTED = -1, + TS_TAG = 0, + TS_READ = 1, + TS_WRITE = 2, + TS_URGENT_READ = 3, + TS_URGENT_WRITE = 4, + TS_FLUSH = 5, + TS_NUM_STATS = 6, +}; + +/** + * struct ufshcd_req_stat - statistics for request handling times (in usec) + * @min: shortest time measured + * @max: longest time measured + * @sum: sum of all the handling times measured (used for average calculation) + * @count: number of measurements taken + */ +struct ufshcd_req_stat { + u64 min; + u64 max; + u64 sum; + u64 count; +}; +#endif + +enum ufshcd_ctx { + QUEUE_CMD, + ERR_HNDLR_WORK, + H8_EXIT_WORK, + UIC_CMD_SEND, + PWRCTL_CMD_SEND, + TM_CMD_SEND, + XFR_REQ_COMPL, + CLK_SCALE_WORK, +}; + +struct ufshcd_clk_ctx { + ktime_t ts; + enum ufshcd_ctx ctx; +}; + +/** + * struct ufs_stats - keeps usage/err statistics + * @enabled: enable tag stats for debugfs + * @tag_stats: pointer to tag statistic counters + * @q_depth: current amount of busy slots + * @err_stats: counters to keep track of various errors + * @req_stats: request handling time statistics per request type + * @query_stats_arr: array that holds query statistics + * @hibern8_exit_cnt: Counter to keep track of number of exits, + * reset this after link-startup. + * @last_hibern8_exit_tstamp: Set time after the hibern8 exit. + * Clear after the first successful command completion. + * @pa_err: tracks pa-uic errors + * @dl_err: tracks dl-uic errors + * @nl_err: tracks nl-uic errors + * @tl_err: tracks tl-uic errors + * @dme_err: tracks dme errors + */ +struct ufs_stats { +#ifdef CONFIG_DEBUG_FS + bool enabled; + u64 **tag_stats; + int q_depth; + int err_stats[UFS_ERR_MAX]; + struct ufshcd_req_stat req_stats[TS_NUM_STATS]; + int query_stats_arr[UPIU_QUERY_OPCODE_MAX][MAX_QUERY_IDN]; + +#endif + u32 last_intr_status; + ktime_t last_intr_ts; + struct ufshcd_clk_ctx clk_hold; + struct ufshcd_clk_ctx clk_rel; + u32 hibern8_exit_cnt; + ktime_t last_hibern8_exit_tstamp; + u32 power_mode_change_cnt; + struct ufs_uic_err_reg_hist pa_err; + struct ufs_uic_err_reg_hist dl_err; + struct ufs_uic_err_reg_hist nl_err; + struct ufs_uic_err_reg_hist tl_err; + struct ufs_uic_err_reg_hist dme_err; +}; + +/* UFS Host Controller debug print bitmask */ +#define UFSHCD_DBG_PRINT_CLK_FREQ_EN UFS_BIT(0) +#define UFSHCD_DBG_PRINT_UIC_ERR_HIST_EN UFS_BIT(1) +#define UFSHCD_DBG_PRINT_HOST_REGS_EN UFS_BIT(2) +#define UFSHCD_DBG_PRINT_TRS_EN UFS_BIT(3) +#define UFSHCD_DBG_PRINT_TMRS_EN UFS_BIT(4) +#define UFSHCD_DBG_PRINT_PWR_EN UFS_BIT(5) +#define UFSHCD_DBG_PRINT_HOST_STATE_EN UFS_BIT(6) + +#define UFSHCD_DBG_PRINT_ALL \ + (UFSHCD_DBG_PRINT_CLK_FREQ_EN | \ + UFSHCD_DBG_PRINT_UIC_ERR_HIST_EN | \ + UFSHCD_DBG_PRINT_HOST_REGS_EN | UFSHCD_DBG_PRINT_TRS_EN | \ + UFSHCD_DBG_PRINT_TMRS_EN | UFSHCD_DBG_PRINT_PWR_EN | \ + UFSHCD_DBG_PRINT_HOST_STATE_EN) + +struct ufshcd_cmd_log_entry { + char *str; /* context like "send", "complete" */ + char *cmd_type; /* "scsi", "query", "nop", "dme" */ + u8 lun; + u8 cmd_id; + sector_t lba; + int transfer_len; + u8 idn; /* used only for query idn */ + u32 doorbell; + u32 outstanding_reqs; + u32 seq_num; + unsigned int tag; + ktime_t tstamp; +}; + +struct ufshcd_cmd_log { + struct ufshcd_cmd_log_entry *entries; + int pos; + u32 seq_num; +}; + /** * struct ufs_hba - per adapter private structure * @mmio_base: UFSHCI base register address @@ -352,7 +702,7 @@ * @nutrs: Transfer Request Queue depth supported by controller * @nutmrs: Task Management Queue depth supported by controller * @ufs_version: UFS Version to which controller complies - * @vops: pointer to variant specific operations + * @var: pointer to variant specific data * @priv: pointer to variant specific private data * @irq: Irq number of the controller * @active_uic_cmd: handle of active UIC command @@ -378,10 +728,18 @@ * @dev_cmd: ufs device management command information * @last_dme_cmd_tstamp: time stamp of the last completed DME command * @auto_bkops_enabled: to track whether bkops is enabled in device + * @ufs_stats: ufshcd statistics to be used via debugfs + * @debugfs_files: debugfs files associated with the ufs stats + * @ufshcd_dbg_print: Bitmask for enabling debug prints * @vreg_info: UFS device voltage regulator information * @clk_list_head: UFS host controller clocks list node head * @pwr_info: holds current power mode * @max_pwr_info: keeps the device max valid pwm + * @hibern8_on_idle: UFS Hibern8 on idle related data + * @urgent_bkops_lvl: keeps track of urgent bkops level for device + * @is_urgent_bkops_lvl_checked: keeps track if the urgent bkops level for + * device is known or not. + * @scsi_block_reqs_cnt: reference counting for scsi block requests */ struct ufs_hba { void __iomem *mmio_base; @@ -407,9 +765,11 @@ enum ufs_dev_pwr_mode curr_dev_pwr_mode; enum uic_link_state uic_link_state; /* Desired UFS power management level during runtime PM */ - enum ufs_pm_level rpm_lvl; + int rpm_lvl; /* Desired UFS power management level during system PM */ - enum ufs_pm_level spm_lvl; + int spm_lvl; + struct device_attribute rpm_lvl_attr; + struct device_attribute spm_lvl_attr; int pm_op_in_progress; struct ufshcd_lrb *lrb; @@ -422,7 +782,7 @@ int nutrs; int nutmrs; u32 ufs_version; - struct ufs_hba_variant_ops *vops; + struct ufs_hba_variant *var; void *priv; unsigned int irq; bool is_irq_enabled; @@ -467,8 +827,14 @@ */ #define UFSHCD_QUIRK_BROKEN_UFS_HCI_VERSION UFS_BIT(5) + /* Auto hibern8 support is broken */ + #define UFSHCD_QUIRK_BROKEN_AUTO_HIBERN8 UFS_BIT(6) + unsigned int quirks; /* Deviations from standard UFSHCI spec. */ + /* Device deviations from standard UFS device spec. */ + unsigned int dev_quirks; + wait_queue_head_t tm_wq; wait_queue_head_t tm_tag_wq; unsigned long tm_condition; @@ -489,12 +855,17 @@ /* Work Queues */ struct work_struct eh_work; struct work_struct eeh_work; + struct work_struct rls_work; /* HBA Errors */ u32 errors; u32 uic_error; + u32 ce_error; /* crypto engine errors */ u32 saved_err; u32 saved_uic_err; + u32 saved_ce_err; + bool silence_err_logs; + bool force_host_reset; /* Device management request data */ struct ufs_dev_cmd dev_cmd; @@ -503,15 +874,33 @@ /* Keeps information of the UFS device connected to this host */ struct ufs_dev_info dev_info; bool auto_bkops_enabled; + + struct ufs_stats ufs_stats; +#ifdef CONFIG_DEBUG_FS + struct debugfs_files debugfs_files; +#endif + struct ufs_vreg_info vreg_info; struct list_head clk_list_head; bool wlun_dev_clr_ua; + /* Number of requests aborts */ + int req_abort_count; + + /* Number of lanes available (1 or 2) for Rx/Tx */ + u32 lanes_per_direction; + + /* Bitmask for enabling debug prints */ + u32 ufshcd_dbg_print; + struct ufs_pa_layer_attr pwr_info; struct ufs_pwr_mode_info max_pwr_info; struct ufs_clk_gating clk_gating; + struct ufs_hibern8_on_idle hibern8_on_idle; + struct ufshcd_cmd_log cmd_log; + /* Control to enable/disable host capabilities */ u32 caps; /* Allow dynamic clk gating */ @@ -528,6 +917,8 @@ * CAUTION: Enabling this might reduce overall UFS throughput. */ #define UFSHCD_CAP_INTR_AGGR (1 << 4) + /* Allow standalone Hibern8 enter on idle */ +#define UFSHCD_CAP_HIBERN8_ENTER_ON_IDLE (1 << 5) /* * This capability allows the device auto-bkops to be always enabled * except during suspend (both runtime and suspend). @@ -535,13 +926,49 @@ * to do background operation when it's active but it might degrade * the performance of ongoing read/write operations. */ -#define UFSHCD_CAP_KEEP_AUTO_BKOPS_ENABLED_EXCEPT_SUSPEND (1 << 5) +#define UFSHCD_CAP_KEEP_AUTO_BKOPS_ENABLED_EXCEPT_SUSPEND (1 << 6) + /* + * If host controller hardware can be power collapsed when UFS link is + * in hibern8 then enable this cap. + */ +#define UFSHCD_CAP_POWER_COLLAPSE_DURING_HIBERN8 (1 << 7) struct devfreq *devfreq; struct ufs_clk_scaling clk_scaling; bool is_sys_suspended; + + enum bkops_status urgent_bkops_lvl; + bool is_urgent_bkops_lvl_checked; + + /* sync b/w diff contexts */ + struct rw_semaphore lock; + unsigned long shutdown_in_prog; + + struct reset_control *core_reset; + /* If set, don't gate device ref_clk during clock gating */ + bool no_ref_clk_gating; + + int scsi_block_reqs_cnt; + + bool full_init_linereset; + struct pinctrl *pctrl; + + int latency_hist_enabled; + struct io_latency_state io_lat_read; + struct io_latency_state io_lat_write; + bool restore_needed; }; +static inline void ufshcd_mark_shutdown_ongoing(struct ufs_hba *hba) +{ + set_bit(0, &hba->shutdown_in_prog); +} + +static inline bool ufshcd_is_shutdown_ongoing(struct ufs_hba *hba) +{ + return !!(test_bit(0, &hba->shutdown_in_prog)); +} + /* Returns true if clocks can be gated. Otherwise false */ static inline bool ufshcd_is_clkgating_allowed(struct ufs_hba *hba) { @@ -551,7 +978,7 @@ { return hba->caps & UFSHCD_CAP_HIBERN8_WITH_CLK_GATING; } -static inline int ufshcd_is_clkscaling_enabled(struct ufs_hba *hba) +static inline int ufshcd_is_clkscaling_supported(struct ufs_hba *hba) { return hba->caps & UFSHCD_CAP_CLK_SCALING; } @@ -559,6 +986,22 @@ { return hba->caps & UFSHCD_CAP_AUTO_BKOPS_SUSPEND; } +static inline bool ufshcd_is_hibern8_on_idle_allowed(struct ufs_hba *hba) +{ + return hba->caps & UFSHCD_CAP_HIBERN8_ENTER_ON_IDLE; +} + +static inline bool ufshcd_is_power_collapse_during_hibern8_allowed( + struct ufs_hba *hba) +{ + return !!(hba->caps & UFSHCD_CAP_POWER_COLLAPSE_DURING_HIBERN8); +} + +static inline bool ufshcd_keep_autobkops_enabled_except_suspend( + struct ufs_hba *hba) +{ + return hba->caps & UFSHCD_CAP_KEEP_AUTO_BKOPS_ENABLED_EXCEPT_SUSPEND; +} static inline bool ufshcd_is_intr_aggr_allowed(struct ufs_hba *hba) { @@ -569,10 +1012,21 @@ return false; } +static inline bool ufshcd_is_auto_hibern8_supported(struct ufs_hba *hba) +{ + return !!((hba->capabilities & MASK_AUTO_HIBERN8_SUPPORT) && + !(hba->quirks & UFSHCD_QUIRK_BROKEN_AUTO_HIBERN8)); +} + +static inline bool ufshcd_is_crypto_supported(struct ufs_hba *hba) +{ + return !!(hba->capabilities & MASK_CRYPTO_SUPPORT); +} + #define ufshcd_writel(hba, val, reg) \ - writel((val), (hba)->mmio_base + (reg)) + writel_relaxed((val), (hba)->mmio_base + (reg)) #define ufshcd_readl(hba, reg) \ - readl((hba)->mmio_base + (reg)) + readl_relaxed((hba)->mmio_base + (reg)) /** * ufshcd_rmwl - read modify write into a register @@ -595,21 +1049,11 @@ void ufshcd_dealloc_host(struct ufs_hba *); int ufshcd_init(struct ufs_hba * , void __iomem * , unsigned int); void ufshcd_remove(struct ufs_hba *); - -/** - * ufshcd_hba_stop - Send controller to reset state - * @hba: per adapter instance - */ -static inline void ufshcd_hba_stop(struct ufs_hba *hba) -{ - ufshcd_writel(hba, CONTROLLER_DISABLE, REG_CONTROLLER_ENABLE); -} - -static inline void check_upiu_size(void) -{ - BUILD_BUG_ON(ALIGNED_UPIU_SIZE < - GENERAL_UPIU_REQUEST_SIZE + QUERY_DESC_MAX_SIZE); -} +int ufshcd_wait_for_register(struct ufs_hba *hba, u32 reg, u32 mask, + u32 val, unsigned long interval_us, + unsigned long timeout_ms, bool can_sleep); +int ufshcd_uic_hibern8_enter(struct ufs_hba *hba); +int ufshcd_uic_hibern8_exit(struct ufs_hba *hba); /** * ufshcd_set_variant - set variant specific data to the hba @@ -631,12 +1075,6 @@ BUG_ON(!hba); return hba->priv; } -static inline bool ufshcd_keep_autobkops_enabled_except_suspend( - struct ufs_hba *hba) -{ - return hba->caps & UFSHCD_CAP_KEEP_AUTO_BKOPS_ENABLED_EXCEPT_SUSPEND; -} - extern int ufshcd_runtime_suspend(struct ufs_hba *hba); extern int ufshcd_runtime_resume(struct ufs_hba *hba); extern int ufshcd_runtime_idle(struct ufs_hba *hba); @@ -694,76 +1132,139 @@ return ufshcd_dme_get_attr(hba, attr_sel, mib_val, DME_PEER); } +/** + * ufshcd_dme_rmw - get modify set a dme attribute + * @hba - per adapter instance + * @mask - mask to apply on read value + * @val - actual value to write + * @attr - dme attribute + */ +static inline int ufshcd_dme_rmw(struct ufs_hba *hba, u32 mask, + u32 val, u32 attr) +{ + u32 cfg = 0; + int err = 0; + + err = ufshcd_dme_get(hba, UIC_ARG_MIB(attr), &cfg); + if (err) + goto out; + + cfg &= ~mask; + cfg |= (val & mask); + + err = ufshcd_dme_set(hba, UIC_ARG_MIB(attr), cfg); + +out: + return err; +} + +int ufshcd_read_device_desc(struct ufs_hba *hba, u8 *buf, u32 size); + +static inline bool ufshcd_is_hs_mode(struct ufs_pa_layer_attr *pwr_info) +{ + return (pwr_info->pwr_rx == FAST_MODE || + pwr_info->pwr_rx == FASTAUTO_MODE) && + (pwr_info->pwr_tx == FAST_MODE || + pwr_info->pwr_tx == FASTAUTO_MODE); +} + +#ifdef CONFIG_DEBUG_FS +static inline void ufshcd_init_req_stats(struct ufs_hba *hba) +{ + memset(hba->ufs_stats.req_stats, 0, sizeof(hba->ufs_stats.req_stats)); +} +#else +static inline void ufshcd_init_req_stats(struct ufs_hba *hba) {} +#endif + +#define ASCII_STD true +#define UTF16_STD false +int ufshcd_read_string_desc(struct ufs_hba *hba, int desc_index, u8 *buf, + u32 size, bool ascii); + +/* Expose Query-Request API */ +int ufshcd_query_flag(struct ufs_hba *hba, enum query_opcode opcode, + enum flag_idn idn, bool *flag_res); +int ufshcd_query_attr(struct ufs_hba *hba, enum query_opcode opcode, + enum attr_idn idn, u8 index, u8 selector, u32 *attr_val); +int ufshcd_query_descriptor(struct ufs_hba *hba, enum query_opcode opcode, + enum desc_idn idn, u8 index, u8 selector, u8 *desc_buf, int *buf_len); + int ufshcd_hold(struct ufs_hba *hba, bool async); -void ufshcd_release(struct ufs_hba *hba); +void ufshcd_release(struct ufs_hba *hba, bool no_sched); +int ufshcd_wait_for_doorbell_clr(struct ufs_hba *hba, u64 wait_timeout_us); +int ufshcd_change_power_mode(struct ufs_hba *hba, + struct ufs_pa_layer_attr *pwr_mode); +void ufshcd_abort_outstanding_transfer_requests(struct ufs_hba *hba, + int result); +u32 ufshcd_get_local_unipro_ver(struct ufs_hba *hba); + +void ufshcd_scsi_block_requests(struct ufs_hba *hba); +void ufshcd_scsi_unblock_requests(struct ufs_hba *hba); /* Wrapper functions for safely calling variant operations */ static inline const char *ufshcd_get_var_name(struct ufs_hba *hba) { - if (hba->vops) - return hba->vops->name; + if (hba->var && hba->var->name) + return hba->var->name; return ""; } static inline int ufshcd_vops_init(struct ufs_hba *hba) { - if (hba->vops && hba->vops->init) - return hba->vops->init(hba); - + if (hba->var && hba->var->vops && hba->var->vops->init) + return hba->var->vops->init(hba); return 0; } static inline void ufshcd_vops_exit(struct ufs_hba *hba) { - if (hba->vops && hba->vops->exit) - return hba->vops->exit(hba); + if (hba->var && hba->var->vops && hba->var->vops->exit) + hba->var->vops->exit(hba); } static inline u32 ufshcd_vops_get_ufs_hci_version(struct ufs_hba *hba) { - if (hba->vops && hba->vops->get_ufs_hci_version) - return hba->vops->get_ufs_hci_version(hba); - + if (hba->var && hba->var->vops && hba->var->vops->get_ufs_hci_version) + return hba->var->vops->get_ufs_hci_version(hba); return ufshcd_readl(hba, REG_UFS_VERSION); } static inline int ufshcd_vops_clk_scale_notify(struct ufs_hba *hba, bool up, enum ufs_notify_change_status status) { - if (hba->vops && hba->vops->clk_scale_notify) - return hba->vops->clk_scale_notify(hba, up, status); + if (hba->var && hba->var->vops && hba->var->vops->clk_scale_notify) + return hba->var->vops->clk_scale_notify(hba, up, status); return 0; } -static inline int ufshcd_vops_setup_clocks(struct ufs_hba *hba, bool on) +static inline int ufshcd_vops_setup_clocks(struct ufs_hba *hba, bool on, + bool is_gating_context) { - if (hba->vops && hba->vops->setup_clocks) - return hba->vops->setup_clocks(hba, on); + if (hba->var && hba->var->vops && hba->var->vops->setup_clocks) + return hba->var->vops->setup_clocks(hba, on, is_gating_context); return 0; } static inline int ufshcd_vops_setup_regulators(struct ufs_hba *hba, bool status) { - if (hba->vops && hba->vops->setup_regulators) - return hba->vops->setup_regulators(hba, status); - + if (hba->var && hba->var->vops && hba->var->vops->setup_regulators) + return hba->var->vops->setup_regulators(hba, status); return 0; } static inline int ufshcd_vops_hce_enable_notify(struct ufs_hba *hba, bool status) { - if (hba->vops && hba->vops->hce_enable_notify) - return hba->vops->hce_enable_notify(hba, status); - + if (hba->var && hba->var->vops && hba->var->vops->hce_enable_notify) + hba->var->vops->hce_enable_notify(hba, status); return 0; } static inline int ufshcd_vops_link_startup_notify(struct ufs_hba *hba, bool status) { - if (hba->vops && hba->vops->link_startup_notify) - return hba->vops->link_startup_notify(hba, status); - + if (hba->var && hba->var->vops && hba->var->vops->link_startup_notify) + return hba->var->vops->link_startup_notify(hba, status); return 0; } @@ -772,33 +1273,156 @@ struct ufs_pa_layer_attr *dev_max_params, struct ufs_pa_layer_attr *dev_req_params) { - if (hba->vops && hba->vops->pwr_change_notify) - return hba->vops->pwr_change_notify(hba, status, + if (hba->var && hba->var->vops && hba->var->vops->pwr_change_notify) + return hba->var->vops->pwr_change_notify(hba, status, dev_max_params, dev_req_params); - return -ENOTSUPP; } -static inline int ufshcd_vops_suspend(struct ufs_hba *hba, enum ufs_pm_op op) +static inline int ufshcd_vops_apply_dev_quirks(struct ufs_hba *hba) { - if (hba->vops && hba->vops->suspend) - return hba->vops->suspend(hba, op); + if (hba->var && hba->var->vops && hba->var->vops->apply_dev_quirks) + return hba->var->vops->apply_dev_quirks(hba); + return 0; +} +static inline int ufshcd_vops_suspend(struct ufs_hba *hba, enum ufs_pm_op op) +{ + if (hba->var && hba->var->vops && hba->var->vops->suspend) + return hba->var->vops->suspend(hba, op); return 0; } static inline int ufshcd_vops_resume(struct ufs_hba *hba, enum ufs_pm_op op) { - if (hba->vops && hba->vops->resume) - return hba->vops->resume(hba, op); + if (hba->var && hba->var->vops && hba->var->vops->resume) + return hba->var->vops->resume(hba, op); + return 0; +} + +static inline int ufshcd_vops_full_reset(struct ufs_hba *hba) +{ + if (hba->var && hba->var->vops && hba->var->vops->full_reset) + return hba->var->vops->full_reset(hba); + return 0; +} + + +static inline void ufshcd_vops_dbg_register_dump(struct ufs_hba *hba, + bool no_sleep) +{ + if (hba->var && hba->var->vops && hba->var->vops->dbg_register_dump) + hba->var->vops->dbg_register_dump(hba, no_sleep); +} + +static inline int ufshcd_vops_update_sec_cfg(struct ufs_hba *hba, + bool restore_sec_cfg) +{ + if (hba->var && hba->var->vops && hba->var->vops->update_sec_cfg) + return hba->var->vops->update_sec_cfg(hba, restore_sec_cfg); + return 0; +} + +static inline u32 ufshcd_vops_get_scale_down_gear(struct ufs_hba *hba) +{ + if (hba->var && hba->var->vops && hba->var->vops->get_scale_down_gear) + return hba->var->vops->get_scale_down_gear(hba); + /* Default to lowest high speed gear */ + return UFS_HS_G1; +} +static inline int ufshcd_vops_set_bus_vote(struct ufs_hba *hba, bool on) +{ + if (hba->var && hba->var->vops && hba->var->vops->set_bus_vote) + return hba->var->vops->set_bus_vote(hba, on); return 0; } -static inline void ufshcd_vops_dbg_register_dump(struct ufs_hba *hba) +#ifdef CONFIG_DEBUG_FS +static inline void ufshcd_vops_add_debugfs(struct ufs_hba *hba, + struct dentry *root) +{ + if (hba->var && hba->var->vops && hba->var->vops->add_debugfs) + hba->var->vops->add_debugfs(hba, root); +} + +static inline void ufshcd_vops_remove_debugfs(struct ufs_hba *hba) +{ + if (hba->var && hba->var->vops && hba->var->vops->remove_debugfs) + hba->var->vops->remove_debugfs(hba); +} +#else +static inline void ufshcd_vops_add_debugfs(struct ufs_hba *hba, struct dentry *) +{ +} + +static inline void ufshcd_vops_remove_debugfs(struct ufs_hba *hba) +{ +} +#endif + +static inline int ufshcd_vops_crypto_req_setup(struct ufs_hba *hba, + struct ufshcd_lrb *lrbp, u8 *cc_index, bool *enable, u64 *dun) +{ + if (hba->var && hba->var->crypto_vops && + hba->var->crypto_vops->crypto_req_setup) + return hba->var->crypto_vops->crypto_req_setup(hba, lrbp, + cc_index, enable, dun); + return 0; +} + +static inline int ufshcd_vops_crypto_engine_cfg_start(struct ufs_hba *hba, + unsigned int task_tag) +{ + if (hba->var && hba->var->crypto_vops && + hba->var->crypto_vops->crypto_engine_cfg_start) + return hba->var->crypto_vops->crypto_engine_cfg_start + (hba, task_tag); + return 0; +} + +static inline int ufshcd_vops_crypto_engine_cfg_end(struct ufs_hba *hba, + struct ufshcd_lrb *lrbp, + struct request *req) +{ + if (hba->var && hba->var->crypto_vops && + hba->var->crypto_vops->crypto_engine_cfg_end) + return hba->var->crypto_vops->crypto_engine_cfg_end + (hba, lrbp, req); + return 0; +} + +static inline int ufshcd_vops_crypto_engine_reset(struct ufs_hba *hba) +{ + if (hba->var && hba->var->crypto_vops && + hba->var->crypto_vops->crypto_engine_reset) + return hba->var->crypto_vops->crypto_engine_reset(hba); + return 0; +} + +static inline int ufshcd_vops_crypto_engine_get_status(struct ufs_hba *hba, + u32 *status) +{ + if (hba->var && hba->var->crypto_vops && + hba->var->crypto_vops->crypto_engine_get_status) + return hba->var->crypto_vops->crypto_engine_get_status(hba, + status); + return 0; +} + +static inline void ufshcd_vops_pm_qos_req_start(struct ufs_hba *hba, + struct request *req) +{ + if (hba->var && hba->var->pm_qos_vops && + hba->var->pm_qos_vops->req_start) + hba->var->pm_qos_vops->req_start(hba, req); +} + +static inline void ufshcd_vops_pm_qos_req_end(struct ufs_hba *hba, + struct request *req, bool lock) { - if (hba->vops && hba->vops->dbg_register_dump) - hba->vops->dbg_register_dump(hba); + if (hba->var && hba->var->pm_qos_vops && hba->var->pm_qos_vops->req_end) + hba->var->pm_qos_vops->req_end(hba, req, lock); } #endif /* End of Header */ diff -ruw linux-4.4.115/drivers/scsi/ufs/ufshcd-pltfrm.c linux-4.4.115-fbx/drivers/scsi/ufs/ufshcd-pltfrm.c --- linux-4.4.115/drivers/scsi/ufs/ufshcd-pltfrm.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/scsi/ufs/ufshcd-pltfrm.c 2019-01-22 16:16:26.631274732 +0100 @@ -40,6 +40,22 @@ #include "ufshcd.h" #include "ufshcd-pltfrm.h" +static int ufshcd_parse_reset_info(struct ufs_hba *hba) +{ + int ret = 0; + + hba->core_reset = devm_reset_control_get(hba->dev, + "core_reset"); + if (IS_ERR(hba->core_reset)) { + ret = PTR_ERR(hba->core_reset); + dev_err(hba->dev, "core_reset unavailable,err = %d\n", + ret); + hba->core_reset = NULL; + } + + return ret; +} + static int ufshcd_parse_clock_info(struct ufs_hba *hba) { int ret = 0; @@ -161,7 +177,7 @@ if (ret) { dev_err(dev, "%s: unable to find %s err %d\n", __func__, prop_name, ret); - goto out_free; + goto out; } vreg->min_uA = 0; @@ -183,9 +199,6 @@ goto out; -out_free: - devm_kfree(dev, vreg); - vreg = NULL; out: if (!ret) *out_vreg = vreg; @@ -224,7 +237,34 @@ return err; } -#ifdef CONFIG_PM +static void ufshcd_parse_pm_levels(struct ufs_hba *hba) +{ + struct device *dev = hba->dev; + struct device_node *np = dev->of_node; + + if (np) { + if (of_property_read_u32(np, "rpm-level", &hba->rpm_lvl)) + hba->rpm_lvl = -1; + if (of_property_read_u32(np, "spm-level", &hba->spm_lvl)) + hba->spm_lvl = -1; + } +} + +static int ufshcd_parse_pinctrl_info(struct ufs_hba *hba) +{ + int ret = 0; + + /* Try to obtain pinctrl handle */ + hba->pctrl = devm_pinctrl_get(hba->dev); + if (IS_ERR(hba->pctrl)) { + ret = PTR_ERR(hba->pctrl); + hba->pctrl = NULL; + } + + return ret; +} + +#ifdef CONFIG_SMP /** * ufshcd_pltfrm_suspend - suspend power management function * @dev: pointer to device handle @@ -280,12 +320,12 @@ /** * ufshcd_pltfrm_init - probe routine of the driver * @pdev: pointer to Platform device handle - * @vops: pointer to variant ops + * @var: pointer to variant specific data * * Returns 0 on success, non-zero value on failure */ int ufshcd_pltfrm_init(struct platform_device *pdev, - struct ufs_hba_variant_ops *vops) + struct ufs_hba_variant *var) { struct ufs_hba *hba; void __iomem *mmio_base; @@ -313,7 +353,7 @@ goto out; } - hba->vops = vops; + hba->var = var; err = ufshcd_parse_clock_info(hba); if (err) { @@ -328,22 +368,37 @@ goto dealloc_host; } - pm_runtime_set_active(&pdev->dev); - pm_runtime_enable(&pdev->dev); + err = ufshcd_parse_reset_info(hba); + if (err) { + dev_err(&pdev->dev, "%s: reset parse failed %d\n", + __func__, err); + goto dealloc_host; + } + + err = ufshcd_parse_pinctrl_info(hba); + if (err) { + dev_dbg(&pdev->dev, "%s: unable to parse pinctrl data %d\n", + __func__, err); + /* let's not fail the probe */ + } + + ufshcd_parse_pm_levels(hba); + + if (!dev->dma_mask) + dev->dma_mask = &dev->coherent_dma_mask; err = ufshcd_init(hba, mmio_base, irq); if (err) { dev_err(dev, "Intialization failed\n"); - goto out_disable_rpm; + goto dealloc_host; } platform_set_drvdata(pdev, hba); - return 0; + pm_runtime_set_active(&pdev->dev); + pm_runtime_enable(&pdev->dev); -out_disable_rpm: - pm_runtime_disable(&pdev->dev); - pm_runtime_set_suspended(&pdev->dev); + return 0; dealloc_host: ufshcd_dealloc_host(hba); out: diff -ruw linux-4.4.115/drivers/scsi/ufs/ufshcd-pltfrm.h linux-4.4.115-fbx/drivers/scsi/ufs/ufshcd-pltfrm.h --- linux-4.4.115/drivers/scsi/ufs/ufshcd-pltfrm.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/scsi/ufs/ufshcd-pltfrm.h 2019-01-22 16:16:26.631274732 +0100 @@ -17,7 +17,7 @@ #include "ufshcd.h" int ufshcd_pltfrm_init(struct platform_device *pdev, - struct ufs_hba_variant_ops *vops); + struct ufs_hba_variant *var); void ufshcd_pltfrm_shutdown(struct platform_device *pdev); #ifdef CONFIG_PM diff -ruw linux-4.4.115/drivers/scsi/ufs/ufshci.h linux-4.4.115-fbx/drivers/scsi/ufs/ufshci.h --- linux-4.4.115/drivers/scsi/ufs/ufshci.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/scsi/ufs/ufshci.h 2019-01-22 16:16:26.635274769 +0100 @@ -48,6 +48,7 @@ REG_UFS_VERSION = 0x08, REG_CONTROLLER_DEV_ID = 0x10, REG_CONTROLLER_PROD_ID = 0x14, + REG_AUTO_HIBERN8_IDLE_TIMER = 0x18, REG_INTERRUPT_STATUS = 0x20, REG_INTERRUPT_ENABLE = 0x24, REG_CONTROLLER_STATUS = 0x30, @@ -72,15 +73,24 @@ REG_UIC_COMMAND_ARG_1 = 0x94, REG_UIC_COMMAND_ARG_2 = 0x98, REG_UIC_COMMAND_ARG_3 = 0x9C, + + UFSHCI_REG_SPACE_SIZE = 0xA0, + + REG_UFS_CCAP = 0x100, + REG_UFS_CRYPTOCAP = 0x104, + + UFSHCI_CRYPTO_REG_SPACE_SIZE = 0x400, }; /* Controller capability masks */ enum { MASK_TRANSFER_REQUESTS_SLOTS = 0x0000001F, MASK_TASK_MANAGEMENT_REQUEST_SLOTS = 0x00070000, + MASK_AUTO_HIBERN8_SUPPORT = 0x00800000, MASK_64_ADDRESSING_SUPPORT = 0x01000000, MASK_OUT_OF_ORDER_DATA_DELIVERY_SUPPORT = 0x02000000, MASK_UIC_DME_TEST_MODE_SUPPORT = 0x04000000, + MASK_CRYPTO_SUPPORT = 0x10000000, }; /* UFS Version 08h */ @@ -92,6 +102,7 @@ UFSHCI_VERSION_10 = 0x00010000, /* 1.0 */ UFSHCI_VERSION_11 = 0x00010100, /* 1.1 */ UFSHCI_VERSION_20 = 0x00000200, /* 2.0 */ + UFSHCI_VERSION_21 = 0x00000210, /* 2.1 */ }; /* @@ -108,8 +119,19 @@ #define MANUFACTURE_ID_MASK UFS_MASK(0xFFFF, 0) #define PRODUCT_ID_MASK UFS_MASK(0xFFFF, 16) -#define UFS_BIT(x) (1L << (x)) +/* + * AHIT - Auto-Hibernate Idle Timer 18h + */ +#define AUTO_HIBERN8_IDLE_TIMER_MASK UFS_MASK(0x3FF, 0) +#define AUTO_HIBERN8_TIMER_SCALE_MASK UFS_MASK(0x7, 10) +#define AUTO_HIBERN8_TIMER_SCALE_1_US UFS_MASK(0x0, 10) +#define AUTO_HIBERN8_TIMER_SCALE_10_US UFS_MASK(0x1, 10) +#define AUTO_HIBERN8_TIMER_SCALE_100_US UFS_MASK(0x2, 10) +#define AUTO_HIBERN8_TIMER_SCALE_1_MS UFS_MASK(0x3, 10) +#define AUTO_HIBERN8_TIMER_SCALE_10_MS UFS_MASK(0x4, 10) +#define AUTO_HIBERN8_TIMER_SCALE_100_MS UFS_MASK(0x5, 10) +/* IS - Interrupt status (20h) / IE - Interrupt enable (24h) */ #define UTP_TRANSFER_REQ_COMPL UFS_BIT(0) #define UIC_DME_END_PT_RESET UFS_BIT(1) #define UIC_ERROR UFS_BIT(2) @@ -124,6 +146,7 @@ #define DEVICE_FATAL_ERROR UFS_BIT(11) #define CONTROLLER_FATAL_ERROR UFS_BIT(16) #define SYSTEM_BUS_FATAL_ERROR UFS_BIT(17) +#define CRYPTO_ENGINE_FATAL_ERROR UFS_BIT(18) #define UFSHCD_UIC_PWR_MASK (UIC_HIBERNATE_ENTER |\ UIC_HIBERNATE_EXIT |\ @@ -134,11 +157,13 @@ #define UFSHCD_ERROR_MASK (UIC_ERROR |\ DEVICE_FATAL_ERROR |\ CONTROLLER_FATAL_ERROR |\ - SYSTEM_BUS_FATAL_ERROR) + SYSTEM_BUS_FATAL_ERROR |\ + CRYPTO_ENGINE_FATAL_ERROR) #define INT_FATAL_ERRORS (DEVICE_FATAL_ERROR |\ CONTROLLER_FATAL_ERROR |\ - SYSTEM_BUS_FATAL_ERROR) + SYSTEM_BUS_FATAL_ERROR |\ + CRYPTO_ENGINE_FATAL_ERROR) /* HCS - Host Controller Status 30h */ #define DEVICE_PRESENT UFS_BIT(0) @@ -160,16 +185,21 @@ /* HCE - Host Controller Enable 34h */ #define CONTROLLER_ENABLE UFS_BIT(0) +#define CRYPTO_GENERAL_ENABLE UFS_BIT(1) #define CONTROLLER_DISABLE 0x0 /* UECPA - Host UIC Error Code PHY Adapter Layer 38h */ #define UIC_PHY_ADAPTER_LAYER_ERROR UFS_BIT(31) +#define UIC_PHY_ADAPTER_LAYER_GENERIC_ERROR UFS_BIT(4) #define UIC_PHY_ADAPTER_LAYER_ERROR_CODE_MASK 0x1F +#define UIC_PHY_ADAPTER_LAYER_LANE_ERR_MASK 0xF /* UECDL - Host UIC Error Code Data Link Layer 3Ch */ #define UIC_DATA_LINK_LAYER_ERROR UFS_BIT(31) #define UIC_DATA_LINK_LAYER_ERROR_CODE_MASK 0x7FFF #define UIC_DATA_LINK_LAYER_ERROR_PA_INIT 0x2000 +#define UIC_DATA_LINK_LAYER_ERROR_NAC_RECEIVED 0x0001 +#define UIC_DATA_LINK_LAYER_ERROR_TCx_REPLAY_TIMEOUT 0x0002 /* UECN - Host UIC Error Code Network Layer 40h */ #define UIC_NETWORK_LAYER_ERROR UFS_BIT(31) @@ -209,6 +239,7 @@ /* GenSelectorIndex calculation macros for M-PHY attributes */ #define UIC_ARG_MPHY_TX_GEN_SEL_INDEX(lane) (lane) +#define UIC_ARG_MPHY_RX_GEN_SEL_INDEX(lane) (PA_MAXDATALANES + (lane)) #define UIC_ARG_MIB_SEL(attr, sel) ((((attr) & 0xFFFF) << 16) |\ ((sel) & 0xFFFF)) @@ -262,6 +293,9 @@ /* Interrupt disable mask for UFSHCI v1.1 */ INTERRUPT_MASK_ALL_VER_11 = 0x31FFF, + + /* Interrupt disable mask for UFSHCI v2.1 */ + INTERRUPT_MASK_ALL_VER_21 = 0x71FFF, }; /* @@ -299,6 +333,9 @@ OCS_PEER_COMM_FAILURE = 0x5, OCS_ABORTED = 0x6, OCS_FATAL_ERROR = 0x7, + OCS_DEVICE_FATAL_ERROR = 0x8, + OCS_INVALID_CRYPTO_CONFIG = 0x9, + OCS_GENERAL_CRYPTO_ERROR = 0xA, OCS_INVALID_COMMAND_STATUS = 0x0F, MASK_OCS = 0x0F, }; @@ -334,6 +371,8 @@ struct ufshcd_sg_entry prd_table[SG_ALL]; }; +#define UTRD_CRYPTO_ENABLE UFS_BIT(23) + /** * struct request_desc_header - Descriptor Header common to both UTRD and UTMRD * @dword0: Descriptor Header DW0 diff -ruw linux-4.4.115/drivers/scsi/ufs/ufs-qcom.c linux-4.4.115-fbx/drivers/scsi/ufs/ufs-qcom.c --- linux-4.4.115/drivers/scsi/ufs/ufs-qcom.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/scsi/ufs/ufs-qcom.c 2019-10-29 09:26:24.797214471 +0100 @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2015, Linux Foundation. All rights reserved. + * Copyright (c) 2013-2017, Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -14,15 +14,33 @@ #include #include +#include #include -#include +#ifdef CONFIG_QCOM_BUS_SCALING +#include +#endif + +#include +#include #include + #include "ufshcd.h" #include "ufshcd-pltfrm.h" #include "unipro.h" #include "ufs-qcom.h" #include "ufshci.h" +#include "ufs_quirks.h" +#include "ufs-qcom-ice.h" +#include "ufs-qcom-debugfs.h" +#include + +#define MAX_PROP_SIZE 32 +#define VDDP_REF_CLK_MIN_UV 1200000 +#define VDDP_REF_CLK_MAX_UV 1200000 +/* TODO: further tuning for this parameter may be required */ +#define UFS_QCOM_PM_QOS_UNVOTE_TIMEOUT_US (10000) /* microseconds */ + #define UFS_QCOM_DEFAULT_DBG_PRINT_EN \ (UFS_QCOM_DBG_PRINT_REGS_EN | UFS_QCOM_DBG_PRINT_TEST_BUS_EN) @@ -44,18 +62,24 @@ static struct ufs_qcom_host *ufs_qcom_hosts[MAX_UFS_QCOM_HOSTS]; -static int ufs_qcom_set_bus_vote(struct ufs_qcom_host *host, int vote); +static int ufs_qcom_update_sec_cfg(struct ufs_hba *hba, bool restore_sec_cfg); static void ufs_qcom_get_default_testbus_cfg(struct ufs_qcom_host *host); static int ufs_qcom_set_dme_vs_core_clk_ctrl_clear_div(struct ufs_hba *hba, u32 clk_cycles); +static void ufs_qcom_pm_qos_suspend(struct ufs_qcom_host *host); static void ufs_qcom_dump_regs(struct ufs_hba *hba, int offset, int len, char *prefix) { print_hex_dump(KERN_ERR, prefix, len > 4 ? DUMP_PREFIX_OFFSET : DUMP_PREFIX_NONE, - 16, 4, (void __force *)hba->mmio_base + offset, - len * 4, false); + 16, 4, hba->mmio_base + offset, len * 4, false); +} + +static void ufs_qcom_dump_regs_wrapper(struct ufs_hba *hba, int offset, int len, + char *prefix, void *priv) +{ + ufs_qcom_dump_regs(hba, offset, len, prefix); } static int ufs_qcom_get_connected_tx_lanes(struct ufs_hba *hba, u32 *tx_lanes) @@ -78,13 +102,10 @@ int err = 0; clk = devm_clk_get(dev, name); - if (IS_ERR(clk)) { + if (IS_ERR(clk)) err = PTR_ERR(clk); - dev_err(dev, "%s: failed to get %s err %d", - __func__, name, err); - } else { + else *clk_out = clk; - } return err; } @@ -106,8 +127,10 @@ if (!host->is_lane_clks_enabled) return; + if (host->tx_l1_sync_clk) clk_disable_unprepare(host->tx_l1_sync_clk); clk_disable_unprepare(host->tx_l0_sync_clk); + if (host->rx_l1_sync_clk) clk_disable_unprepare(host->rx_l1_sync_clk); clk_disable_unprepare(host->rx_l0_sync_clk); @@ -132,21 +155,20 @@ if (err) goto disable_rx_l0; + if (host->hba->lanes_per_direction > 1) { err = ufs_qcom_host_clk_enable(dev, "rx_lane1_sync_clk", host->rx_l1_sync_clk); if (err) goto disable_tx_l0; - err = ufs_qcom_host_clk_enable(dev, "tx_lane1_sync_clk", + /* The tx lane1 clk could be muxed, hence keep this optional */ + if (host->tx_l1_sync_clk) + ufs_qcom_host_clk_enable(dev, "tx_lane1_sync_clk", host->tx_l1_sync_clk); - if (err) - goto disable_rx_l1; - + } host->is_lane_clks_enabled = true; goto out; -disable_rx_l1: - clk_disable_unprepare(host->rx_l1_sync_clk); disable_tx_l0: clk_disable_unprepare(host->tx_l0_sync_clk); disable_rx_l0: @@ -162,42 +184,34 @@ err = ufs_qcom_host_clk_get(dev, "rx_lane0_sync_clk", &host->rx_l0_sync_clk); - if (err) + if (err) { + dev_err(dev, "%s: failed to get rx_lane0_sync_clk, err %d", + __func__, err); goto out; + } err = ufs_qcom_host_clk_get(dev, "tx_lane0_sync_clk", &host->tx_l0_sync_clk); - if (err) + if (err) { + dev_err(dev, "%s: failed to get tx_lane0_sync_clk, err %d", + __func__, err); goto out; + } + /* In case of single lane per direction, don't read lane1 clocks */ + if (host->hba->lanes_per_direction > 1) { err = ufs_qcom_host_clk_get(dev, "rx_lane1_sync_clk", &host->rx_l1_sync_clk); - if (err) + if (err) { + dev_err(dev, "%s: failed to get rx_lane1_sync_clk, err %d", + __func__, err); goto out; + } - err = ufs_qcom_host_clk_get(dev, "tx_lane1_sync_clk", + /* The tx lane1 clk could be muxed, hence keep this optional */ + ufs_qcom_host_clk_get(dev, "tx_lane1_sync_clk", &host->tx_l1_sync_clk); - -out: - return err; } - -static int ufs_qcom_link_startup_post_change(struct ufs_hba *hba) -{ - struct ufs_qcom_host *host = ufshcd_get_variant(hba); - struct phy *phy = host->generic_phy; - u32 tx_lanes; - int err = 0; - - err = ufs_qcom_get_connected_tx_lanes(hba, &tx_lanes); - if (err) - goto out; - - err = ufs_qcom_phy_set_tx_lane_enable(phy, tx_lanes); - if (err) - dev_err(hba->dev, "%s: ufs_qcom_phy_set_tx_lane_enable failed\n", - __func__); - out: return err; } @@ -267,8 +281,7 @@ ret = ufs_qcom_phy_calibrate_phy(phy, is_rate_B); if (ret) { - dev_err(hba->dev, - "%s: ufs_qcom_phy_calibrate_phy()failed, ret = %d\n", + dev_err(hba->dev, "%s: ufs_qcom_phy_calibrate_phy() failed, ret = %d\n", __func__, ret); goto out; } @@ -290,8 +303,7 @@ ret = ufs_qcom_phy_is_pcs_ready(phy); if (ret) - dev_err(hba->dev, - "%s: is_physical_coding_sublayer_ready() failed, ret = %d\n", + dev_err(hba->dev, "%s: is_physical_coding_sublayer_ready() failed, ret = %d\n", __func__, ret); ufs_qcom_select_unipro_mode(host); @@ -307,15 +319,65 @@ * in a specific operation, UTP controller CGCs are by default disabled and * this function enables them (after every UFS link startup) to save some power * leakage. + * + * UFS host controller v3.0.0 onwards has internal clock gating mechanism + * in Qunipro, enable them to save additional power. */ -static void ufs_qcom_enable_hw_clk_gating(struct ufs_hba *hba) +static int ufs_qcom_enable_hw_clk_gating(struct ufs_hba *hba) { + struct ufs_qcom_host *host = ufshcd_get_variant(hba); + int err = 0; + + /* Enable UTP internal clock gating */ ufshcd_writel(hba, ufshcd_readl(hba, REG_UFS_CFG2) | REG_UFS_CFG2_CGC_EN_ALL, REG_UFS_CFG2); /* Ensure that HW clock gating is enabled before next operations */ mb(); + + /* Enable Qunipro internal clock gating if supported */ + if (!ufs_qcom_cap_qunipro_clk_gating(host)) + goto out; + + /* Enable all the mask bits */ + err = ufshcd_dme_rmw(hba, DL_VS_CLK_CFG_MASK, + DL_VS_CLK_CFG_MASK, DL_VS_CLK_CFG); + if (err) + goto out; + + err = ufshcd_dme_rmw(hba, PA_VS_CLK_CFG_REG_MASK, + PA_VS_CLK_CFG_REG_MASK, PA_VS_CLK_CFG_REG); + if (err) + goto out; + + err = ufshcd_dme_rmw(hba, DME_VS_CORE_CLK_CTRL_DME_HW_CGC_EN, + DME_VS_CORE_CLK_CTRL_DME_HW_CGC_EN, + DME_VS_CORE_CLK_CTRL); +out: + return err; +} + +static void ufs_qcom_force_mem_config(struct ufs_hba *hba) +{ + struct ufs_clk_info *clki; + + /* + * Configure the behavior of ufs clocks core and peripheral + * memory state when they are turned off. + * This configuration is required to allow retaining + * ICE crypto configuration (including keys) when + * core_clk_ice is turned off, and powering down + * non-ICE RAMs of host controller. + */ + list_for_each_entry(clki, &hba->clk_list_head, list) { + if (!strcmp(clki->name, "core_clk_ice")) + clk_set_flags(clki->clk, CLKFLAG_RETAIN_MEM); + else + clk_set_flags(clki->clk, CLKFLAG_NORETAIN_MEM); + clk_set_flags(clki->clk, CLKFLAG_NORETAIN_PERIPH); + clk_set_flags(clki->clk, CLKFLAG_PERIPH_OFF_CLEAR); + } } static int ufs_qcom_hce_enable_notify(struct ufs_hba *hba, @@ -326,6 +388,7 @@ switch (status) { case PRE_CHANGE: + ufs_qcom_force_mem_config(hba); ufs_qcom_power_up_sequence(hba); /* * The PHY PLL output is the source of tx/rx lane symbol @@ -333,12 +396,19 @@ * is initialized. */ err = ufs_qcom_enable_lane_clks(host); + if (!err && host->ice.pdev) { + err = ufs_qcom_ice_init(host); + if (err) { + dev_err(hba->dev, "%s: ICE init failed (%d)\n", + __func__, err); + err = -EINVAL; + } + } + break; case POST_CHANGE: /* check if UFS PHY moved from DISABLED to HIBERN8 */ err = ufs_qcom_check_hibern8(hba); - ufs_qcom_enable_hw_clk_gating(hba); - break; default: dev_err(hba->dev, "%s: invalid status %d\n", __func__, status); @@ -351,8 +421,9 @@ /** * Returns zero for success and non-zero in case of a failure */ -static int ufs_qcom_cfg_timers(struct ufs_hba *hba, u32 gear, - u32 hs, u32 rate, bool update_link_startup_timer) +static int __ufs_qcom_cfg_timers(struct ufs_hba *hba, u32 gear, + u32 hs, u32 rate, bool update_link_startup_timer, + bool is_pre_scale_up) { int ret = 0; struct ufs_qcom_host *host = ufshcd_get_variant(hba); @@ -386,9 +457,11 @@ * SYS1CLK_1US_REG, TX_SYMBOL_CLK_1US_REG, CLK_NS_REG & * UFS_REG_PA_LINK_STARTUP_TIMER * But UTP controller uses SYS1CLK_1US_REG register for Interrupt - * Aggregation logic. + * Aggregation / Auto hibern8 logic. */ - if (ufs_qcom_cap_qunipro(host) && !ufshcd_is_intr_aggr_allowed(hba)) + if (ufs_qcom_cap_qunipro(host) && + (!(ufshcd_is_intr_aggr_allowed(hba) || + ufshcd_is_auto_hibern8_supported(hba)))) goto out; if (gear == 0) { @@ -397,9 +470,13 @@ } list_for_each_entry(clki, &hba->clk_list_head, list) { - if (!strcmp(clki->name, "core_clk")) + if (!strcmp(clki->name, "core_clk")) { + if (is_pre_scale_up) + core_clk_rate = clki->max_freq; + else core_clk_rate = clk_get_rate(clki->clk); } + } /* If frequency is smaller than 1MHz, set to 1MHz */ if (core_clk_rate < DEFAULT_CLK_RATE_HZ) @@ -495,70 +572,247 @@ return ret; } -static int ufs_qcom_link_startup_notify(struct ufs_hba *hba, - enum ufs_notify_change_status status) +static int ufs_qcom_cfg_timers(struct ufs_hba *hba, u32 gear, + u32 hs, u32 rate, bool update_link_startup_timer) +{ + return __ufs_qcom_cfg_timers(hba, gear, hs, rate, + update_link_startup_timer, false); +} + +static int ufs_qcom_link_startup_pre_change(struct ufs_hba *hba) { - int err = 0; struct ufs_qcom_host *host = ufshcd_get_variant(hba); + struct phy *phy = host->generic_phy; + u32 unipro_ver; + int err = 0; - switch (status) { - case PRE_CHANGE: - if (ufs_qcom_cfg_timers(hba, UFS_PWM_G1, SLOWAUTO_MODE, - 0, true)) { + if (ufs_qcom_cfg_timers(hba, UFS_PWM_G1, SLOWAUTO_MODE, 0, true)) { dev_err(hba->dev, "%s: ufs_qcom_cfg_timers() failed\n", __func__); err = -EINVAL; goto out; } - if (ufs_qcom_cap_qunipro(host)) + /* make sure RX LineCfg is enabled before link startup */ + err = ufs_qcom_phy_ctrl_rx_linecfg(phy, true); + if (err) + goto out; + + if (ufs_qcom_cap_qunipro(host)) { /* - * set unipro core clock cycles to 150 & clear clock - * divider + * set unipro core clock cycles to 150 & clear clock divider */ - err = ufs_qcom_set_dme_vs_core_clk_ctrl_clear_div(hba, - 150); + err = ufs_qcom_set_dme_vs_core_clk_ctrl_clear_div(hba, 150); + if (err) + goto out; + } + + err = ufs_qcom_enable_hw_clk_gating(hba); + if (err) + goto out; + + /* + * Some UFS devices (and may be host) have issues if LCC is + * enabled. So we are setting PA_Local_TX_LCC_Enable to 0 + * before link startup which will make sure that both host + * and device TX LCC are disabled once link startup is + * completed. + */ + unipro_ver = ufshcd_get_local_unipro_ver(hba); + if (unipro_ver != UFS_UNIPRO_VER_1_41) + err = ufshcd_dme_set(hba, + UIC_ARG_MIB(PA_LOCAL_TX_LCC_ENABLE), + 0); + if (err) + goto out; + + if (!ufs_qcom_cap_qunipro_clk_gating(host)) + goto out; + + /* Enable all the mask bits */ + err = ufshcd_dme_rmw(hba, SAVECONFIGTIME_MODE_MASK, + SAVECONFIGTIME_MODE_MASK, + PA_VS_CONFIG_REG1); +out: + return err; +} + +static int ufs_qcom_link_startup_post_change(struct ufs_hba *hba) +{ + struct ufs_qcom_host *host = ufshcd_get_variant(hba); + struct phy *phy = host->generic_phy; + u32 tx_lanes; + int err = 0; + + err = ufs_qcom_get_connected_tx_lanes(hba, &tx_lanes); + if (err) + goto out; + + err = ufs_qcom_phy_set_tx_lane_enable(phy, tx_lanes); + if (err) { + dev_err(hba->dev, "%s: ufs_qcom_phy_set_tx_lane_enable failed\n", + __func__); + goto out; + } + /* + * Some UFS devices send incorrect LineCfg data as part of power mode + * change sequence which may cause host PHY to go into bad state. + * Disabling Rx LineCfg of host PHY should help avoid this. + */ + if (ufshcd_get_local_unipro_ver(hba) == UFS_UNIPRO_VER_1_41) + err = ufs_qcom_phy_ctrl_rx_linecfg(phy, false); + if (err) { + dev_err(hba->dev, "%s: ufs_qcom_phy_ctrl_rx_linecfg failed\n", + __func__); + goto out; + } + + /* + * UFS controller has *clk_req output to GCC, for each one if the clocks + * entering it. When *clk_req for a specific clock is de-asserted, + * a corresponding clock from GCC is stopped. UFS controller de-asserts + * *clk_req outputs when it is in Auto Hibernate state only if the + * Clock request feature is enabled. + * Enable the Clock request feature: + * - Enable HW clock control for UFS clocks in GCC (handled by the + * clock driver as part of clk_prepare_enable). + * - Set the AH8_CFG.*CLK_REQ register bits to 1. + */ + if (ufshcd_is_auto_hibern8_supported(hba)) + ufshcd_writel(hba, ufshcd_readl(hba, UFS_AH8_CFG) | + UFS_HW_CLK_CTRL_EN, + UFS_AH8_CFG); + /* + * Make sure clock request feature gets enabled for HW clk gating + * before further operations. + */ + mb(); + +out: + return err; +} + +static int ufs_qcom_link_startup_notify(struct ufs_hba *hba, + enum ufs_notify_change_status status) +{ + int err = 0; + + switch (status) { + case PRE_CHANGE: + err = ufs_qcom_link_startup_pre_change(hba); break; case POST_CHANGE: - ufs_qcom_link_startup_post_change(hba); + err = ufs_qcom_link_startup_post_change(hba); break; default: break; } -out: return err; } + +static int ufs_qcom_config_vreg(struct device *dev, + struct ufs_vreg *vreg, bool on) +{ + int ret = 0; + struct regulator *reg; + int min_uV, uA_load; + + if (!vreg) { + WARN_ON(1); + ret = -EINVAL; + goto out; + } + + reg = vreg->reg; + if (regulator_count_voltages(reg) > 0) { + min_uV = on ? vreg->min_uV : 0; + ret = regulator_set_voltage(reg, min_uV, vreg->max_uV); + if (ret) { + dev_err(dev, "%s: %s set voltage failed, err=%d\n", + __func__, vreg->name, ret); + goto out; + } + + uA_load = on ? vreg->max_uA : 0; + ret = regulator_set_load(vreg->reg, uA_load); + if (ret) + goto out; + } +out: + return ret; +} + +static int ufs_qcom_enable_vreg(struct device *dev, struct ufs_vreg *vreg) +{ + int ret = 0; + + if (vreg->enabled) + return ret; + + ret = ufs_qcom_config_vreg(dev, vreg, true); + if (ret) + goto out; + + ret = regulator_enable(vreg->reg); + if (ret) + goto out; + + vreg->enabled = true; +out: + return ret; +} + +static int ufs_qcom_disable_vreg(struct device *dev, struct ufs_vreg *vreg) +{ + int ret = 0; + + if (!vreg->enabled) + return ret; + + ret = regulator_disable(vreg->reg); + if (ret) + goto out; + + ret = ufs_qcom_config_vreg(dev, vreg, false); + if (ret) + goto out; + + vreg->enabled = false; +out: + return ret; +} + static int ufs_qcom_suspend(struct ufs_hba *hba, enum ufs_pm_op pm_op) { struct ufs_qcom_host *host = ufshcd_get_variant(hba); struct phy *phy = host->generic_phy; int ret = 0; - if (ufs_qcom_is_link_off(hba)) { /* - * Disable the tx/rx lane symbol clocks before PHY is - * powered down as the PLL source should be disabled - * after downstream clocks are disabled. + * If UniPro link is not active or OFF, PHY ref_clk, main PHY analog + * power rail and low noise analog power rail for PLL can be + * switched off. */ + if (!ufs_qcom_is_link_active(hba)) { ufs_qcom_disable_lane_clks(host); phy_power_off(phy); + if (host->vddp_ref_clk && ufs_qcom_is_link_off(hba)) + ret = ufs_qcom_disable_vreg(hba->dev, + host->vddp_ref_clk); + ufs_qcom_ice_suspend(host); + + if (ufs_qcom_is_link_off(hba)) { /* Assert PHY soft reset */ ufs_qcom_assert_reset(hba); goto out; } - - /* - * If UniPro link is not active, PHY ref_clk, main PHY analog power - * rail and low noise analog power rail for PLL can be switched off. - */ - if (!ufs_qcom_is_link_active(hba)) { - ufs_qcom_disable_lane_clks(host); - phy_power_off(phy); } + /* Unvote PM QoS */ + ufs_qcom_pm_qos_suspend(host); out: return ret; @@ -577,16 +831,146 @@ goto out; } + if (host->vddp_ref_clk && (hba->rpm_lvl > UFS_PM_LVL_3 || + hba->spm_lvl > UFS_PM_LVL_3)) + ufs_qcom_enable_vreg(hba->dev, + host->vddp_ref_clk); + err = ufs_qcom_enable_lane_clks(host); if (err) goto out; + err = ufs_qcom_ice_resume(host); + if (err) { + dev_err(hba->dev, "%s: ufs_qcom_ice_resume failed, err = %d\n", + __func__, err); + goto out; + } + hba->is_sys_suspended = false; out: return err; } +static int ufs_qcom_full_reset(struct ufs_hba *hba) +{ + int ret = -ENOTSUPP; + + if (!hba->core_reset) { + dev_err(hba->dev, "%s: failed, err = %d\n", __func__, + ret); + goto out; + } + + ret = reset_control_assert(hba->core_reset); + if (ret) { + dev_err(hba->dev, "%s: core_reset assert failed, err = %d\n", + __func__, ret); + goto out; + } + + /* + * The hardware requirement for delay between assert/deassert + * is at least 3-4 sleep clock (32.7KHz) cycles, which comes to + * ~125us (4/32768). To be on the safe side add 200us delay. + */ + usleep_range(200, 210); + + ret = reset_control_deassert(hba->core_reset); + if (ret) + dev_err(hba->dev, "%s: core_reset deassert failed, err = %d\n", + __func__, ret); + +out: + return ret; +} + +#ifdef CONFIG_SCSI_UFS_QCOM_ICE +static int ufs_qcom_crypto_req_setup(struct ufs_hba *hba, + struct ufshcd_lrb *lrbp, u8 *cc_index, bool *enable, u64 *dun) +{ + struct ufs_qcom_host *host = ufshcd_get_variant(hba); + struct request *req; + int ret; + + if (lrbp->cmd && lrbp->cmd->request) + req = lrbp->cmd->request; + else + return 0; + + /* Use request LBA as the DUN value */ + if (req->bio) + *dun = (req->bio->bi_iter.bi_sector) >> + UFS_QCOM_ICE_TR_DATA_UNIT_4_KB; + + ret = ufs_qcom_ice_req_setup(host, lrbp->cmd, cc_index, enable); + + return ret; +} + +static +int ufs_qcom_crytpo_engine_cfg_start(struct ufs_hba *hba, unsigned int task_tag) +{ + struct ufs_qcom_host *host = ufshcd_get_variant(hba); + struct ufshcd_lrb *lrbp = &hba->lrb[task_tag]; + int err = 0; + + if (!host->ice.pdev || + !lrbp->cmd || lrbp->command_type != UTP_CMD_TYPE_SCSI) + goto out; + + err = ufs_qcom_ice_cfg_start(host, lrbp->cmd); +out: + return err; +} + +static +int ufs_qcom_crytpo_engine_cfg_end(struct ufs_hba *hba, + struct ufshcd_lrb *lrbp, struct request *req) +{ + struct ufs_qcom_host *host = ufshcd_get_variant(hba); + int err = 0; + + if (!host->ice.pdev || lrbp->command_type != UTP_CMD_TYPE_SCSI) + goto out; + + err = ufs_qcom_ice_cfg_end(host, req); +out: + return err; +} + +static +int ufs_qcom_crytpo_engine_reset(struct ufs_hba *hba) +{ + struct ufs_qcom_host *host = ufshcd_get_variant(hba); + int err = 0; + + if (!host->ice.pdev) + goto out; + + err = ufs_qcom_ice_reset(host); +out: + return err; +} + +static int ufs_qcom_crypto_engine_get_status(struct ufs_hba *hba, u32 *status) +{ + struct ufs_qcom_host *host = ufshcd_get_variant(hba); + + if (!status) + return -EINVAL; + + return ufs_qcom_ice_get_status(host, status); +} +#else /* !CONFIG_SCSI_UFS_QCOM_ICE */ +#define ufs_qcom_crypto_req_setup NULL +#define ufs_qcom_crytpo_engine_cfg_start NULL +#define ufs_qcom_crytpo_engine_cfg_end NULL +#define ufs_qcom_crytpo_engine_reset NULL +#define ufs_qcom_crypto_engine_get_status NULL +#endif /* CONFIG_SCSI_UFS_QCOM_ICE */ + struct ufs_qcom_dev_params { u32 pwm_rx_gear; /* pwm rx gear to work in */ u32 pwm_tx_gear; /* pwm tx gear to work in */ @@ -685,7 +1069,7 @@ return 0; } -#ifdef CONFIG_MSM_BUS_SCALING +#ifdef CONFIG_QCOM_BUS_SCALING static int ufs_qcom_get_bus_vote(struct ufs_qcom_host *host, const char *speed_mode) { @@ -739,7 +1123,7 @@ } } -static int ufs_qcom_set_bus_vote(struct ufs_qcom_host *host, int vote) +static int __ufs_qcom_set_bus_vote(struct ufs_qcom_host *host, int vote) { int err = 0; @@ -770,7 +1154,7 @@ vote = ufs_qcom_get_bus_vote(host, mode); if (vote >= 0) - err = ufs_qcom_set_bus_vote(host, vote); + err = __ufs_qcom_set_bus_vote(host, vote); else err = vote; @@ -781,6 +1165,35 @@ return err; } +static int ufs_qcom_set_bus_vote(struct ufs_hba *hba, bool on) +{ + struct ufs_qcom_host *host = ufshcd_get_variant(hba); + int vote, err; + + /* + * In case ufs_qcom_init() is not yet done, simply ignore. + * This ufs_qcom_set_bus_vote() shall be called from + * ufs_qcom_init() after init is done. + */ + if (!host) + return 0; + + if (on) { + vote = host->bus_vote.saved_vote; + if (vote == host->bus_vote.min_bw_vote) + ufs_qcom_update_bus_bw_vote(host); + } else { + vote = host->bus_vote.min_bw_vote; + } + + err = __ufs_qcom_set_bus_vote(host, vote); + if (err) + dev_err(hba->dev, "%s: set bus vote failed %d\n", + __func__, err); + + return err; +} + static ssize_t show_ufs_to_mem_max_bus_bw(struct device *dev, struct device_attribute *attr, char *buf) @@ -851,13 +1264,13 @@ out: return err; } -#else /* CONFIG_MSM_BUS_SCALING */ +#else /* CONFIG_QCOM_BUS_SCALING */ static int ufs_qcom_update_bus_bw_vote(struct ufs_qcom_host *host) { return 0; } -static int ufs_qcom_set_bus_vote(struct ufs_qcom_host *host, int vote) +static int ufs_qcom_set_bus_vote(struct ufs_hba *hba, bool on) { return 0; } @@ -866,7 +1279,10 @@ { return 0; } -#endif /* CONFIG_MSM_BUS_SCALING */ +static inline void msm_bus_scale_unregister_client(uint32_t cl) +{ +} +#endif /* CONFIG_QCOM_BUS_SCALING */ static void ufs_qcom_dev_ref_clk_ctrl(struct ufs_qcom_host *host, bool enable) { @@ -953,6 +1369,18 @@ ufs_qcom_cap.hs_rx_gear = UFS_HS_G2; } + /* + * Platforms using QRBTCv2 phy must limit link to PWM Gear-1 + * and SLOW mode to successfully bring up the link. + */ + if (!strcmp(ufs_qcom_phy_name(phy), "ufs_phy_qrbtc_v2")) { + ufs_qcom_cap.tx_lanes = 1; + ufs_qcom_cap.rx_lanes = 1; + ufs_qcom_cap.pwm_rx_gear = UFS_PWM_G1; + ufs_qcom_cap.pwm_tx_gear = UFS_PWM_G1; + ufs_qcom_cap.desired_working_mode = SLOW; + } + ret = ufs_qcom_get_pwr_dev_param(&ufs_qcom_cap, dev_max_params, dev_req_params); @@ -962,6 +1390,10 @@ goto out; } + /* enable the device ref clock before changing to HS mode */ + if (!ufshcd_is_hs_mode(&hba->pwr_info) && + ufshcd_is_hs_mode(dev_req_params)) + ufs_qcom_dev_ref_clk_ctrl(host, true); break; case POST_CHANGE: if (ufs_qcom_cfg_timers(hba, dev_req_params->gear_rx, @@ -989,6 +1421,11 @@ memcpy(&host->dev_req_params, dev_req_params, sizeof(*dev_req_params)); ufs_qcom_update_bus_bw_vote(host); + + /* disable the device ref clock if entered PWM mode */ + if (ufshcd_is_hs_mode(&hba->pwr_info) && + !ufshcd_is_hs_mode(dev_req_params)) + ufs_qcom_dev_ref_clk_ctrl(host, false); break; default: ret = -EINVAL; @@ -998,6 +1435,34 @@ return ret; } +static int ufs_qcom_quirk_host_pa_saveconfigtime(struct ufs_hba *hba) +{ + int err; + u32 pa_vs_config_reg1; + + err = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_VS_CONFIG_REG1), + &pa_vs_config_reg1); + if (err) + goto out; + + /* Allow extension of MSB bits of PA_SaveConfigTime attribute */ + err = ufshcd_dme_set(hba, UIC_ARG_MIB(PA_VS_CONFIG_REG1), + (pa_vs_config_reg1 | (1 << 12))); + +out: + return err; +} + +static int ufs_qcom_apply_dev_quirks(struct ufs_hba *hba) +{ + int err = 0; + + if (hba->dev_quirks & UFS_DEVICE_QUIRK_HOST_PA_SAVECONFIGTIME) + err = ufs_qcom_quirk_host_pa_saveconfigtime(hba); + + return err; +} + static u32 ufs_qcom_get_ufs_hci_version(struct ufs_hba *hba) { struct ufs_qcom_host *host = ufshcd_get_variant(hba); @@ -1021,18 +1486,18 @@ { struct ufs_qcom_host *host = ufshcd_get_variant(hba); - if (host->hw_ver.major == 0x01) { - hba->quirks |= UFSHCD_QUIRK_DELAY_BEFORE_DME_CMDS + if (host->hw_ver.major == 0x1) { + hba->quirks |= (UFSHCD_QUIRK_DELAY_BEFORE_DME_CMDS | UFSHCD_QUIRK_BROKEN_PA_RXHSUNTERMCAP - | UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE; + | UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE); - if (host->hw_ver.minor == 0x0001 && host->hw_ver.step == 0x0001) + if (host->hw_ver.minor == 0x001 && host->hw_ver.step == 0x0001) hba->quirks |= UFSHCD_QUIRK_BROKEN_INTR_AGGR; hba->quirks |= UFSHCD_QUIRK_BROKEN_LCC; } - if (host->hw_ver.major >= 0x2) { + if (host->hw_ver.major == 0x2) { hba->quirks |= UFSHCD_QUIRK_BROKEN_UFS_HCI_VERSION; if (!ufs_qcom_cap_qunipro(host)) @@ -1041,34 +1506,59 @@ | UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE | UFSHCD_QUIRK_BROKEN_PA_RXHSUNTERMCAP); } + + if (host->disable_lpm) + hba->quirks |= UFSHCD_QUIRK_BROKEN_AUTO_HIBERN8; } static void ufs_qcom_set_caps(struct ufs_hba *hba) { struct ufs_qcom_host *host = ufshcd_get_variant(hba); - hba->caps |= UFSHCD_CAP_CLK_GATING | UFSHCD_CAP_HIBERN8_WITH_CLK_GATING; + if (!host->disable_lpm) { + hba->caps |= UFSHCD_CAP_CLK_GATING; + hba->caps |= UFSHCD_CAP_HIBERN8_WITH_CLK_GATING; hba->caps |= UFSHCD_CAP_CLK_SCALING; + } hba->caps |= UFSHCD_CAP_AUTO_BKOPS_SUSPEND; if (host->hw_ver.major >= 0x2) { + if (!host->disable_lpm) + hba->caps |= UFSHCD_CAP_POWER_COLLAPSE_DURING_HIBERN8; host->caps = UFS_QCOM_CAP_QUNIPRO | UFS_QCOM_CAP_RETAIN_SEC_CFG_AFTER_PWR_COLLAPSE; } + if (host->hw_ver.major >= 0x3) { + host->caps |= UFS_QCOM_CAP_QUNIPRO_CLK_GATING; + /* + * The UFS PHY attached to v3.0.0 controller supports entering + * deeper low power state of SVS2. This lets the controller + * run at much lower clock frequencies for saving power. + * Assuming this and any future revisions of the controller + * support this capability. Need to revist this assumption if + * any future platform with this core doesn't support the + * capability, as there will be no benefit running at lower + * frequencies then. + */ + host->caps |= UFS_QCOM_CAP_SVS2; + } } /** * ufs_qcom_setup_clocks - enables/disable clocks * @hba: host controller instance * @on: If true, enable clocks else disable them. + * @is_gating_context: If true then it means this function is called from + * aggressive clock gating context and we may only need to gate off important + * clocks. If false then make sure to gate off all clocks. * * Returns 0 on success, non-zero on failure. */ -static int ufs_qcom_setup_clocks(struct ufs_hba *hba, bool on) +static int ufs_qcom_setup_clocks(struct ufs_hba *hba, bool on, + bool is_gating_context) { struct ufs_qcom_host *host = ufshcd_get_variant(hba); int err; - int vote = 0; /* * In case ufs_qcom_init() is not yet done, simply ignore. @@ -1090,30 +1580,426 @@ ufs_qcom_phy_disable_iface_clk(host->generic_phy); goto out; } - vote = host->bus_vote.saved_vote; - if (vote == host->bus_vote.min_bw_vote) - ufs_qcom_update_bus_bw_vote(host); + /* enable the device ref clock for HS mode*/ + if (ufshcd_is_hs_mode(&hba->pwr_info)) + ufs_qcom_dev_ref_clk_ctrl(host, true); + err = ufs_qcom_ice_resume(host); + if (err) + goto out; } else { + err = ufs_qcom_ice_suspend(host); + if (err) + goto out; /* M-PHY RMMI interface clocks can be turned off */ ufs_qcom_phy_disable_iface_clk(host->generic_phy); - if (!ufs_qcom_is_link_active(hba)) + /* + * If auto hibern8 is supported then the link will already + * be in hibern8 state and the ref clock can be gated. + */ + if (ufshcd_is_auto_hibern8_supported(hba) || + !ufs_qcom_is_link_active(hba)) { + /* turn off UFS local PHY ref_clk */ + ufs_qcom_phy_disable_ref_clk(host->generic_phy); /* disable device ref_clk */ ufs_qcom_dev_ref_clk_ctrl(host, false); + } + } - vote = host->bus_vote.min_bw_vote; +out: + return err; } - err = ufs_qcom_set_bus_vote(host, vote); - if (err) - dev_err(hba->dev, "%s: set bus vote failed %d\n", - __func__, err); +#ifdef CONFIG_SMP /* CONFIG_SMP */ +static int ufs_qcom_cpu_to_group(struct ufs_qcom_host *host, int cpu) +{ + int i; + + if (cpu >= 0 && cpu < num_possible_cpus()) + for (i = 0; i < host->pm_qos.num_groups; i++) + if (cpumask_test_cpu(cpu, &host->pm_qos.groups[i].mask)) + return i; + + return host->pm_qos.default_cpu; +} + +static void ufs_qcom_pm_qos_req_start(struct ufs_hba *hba, struct request *req) +{ + unsigned long flags; + struct ufs_qcom_host *host; + struct ufs_qcom_pm_qos_cpu_group *group; + if (!hba || !req) + return; + + host = ufshcd_get_variant(hba); + if (!host->pm_qos.groups) + return; + + group = &host->pm_qos.groups[ufs_qcom_cpu_to_group(host, req->cpu)]; + + spin_lock_irqsave(hba->host->host_lock, flags); + if (!host->pm_qos.is_enabled) + goto out; + + group->active_reqs++; + if (group->state != PM_QOS_REQ_VOTE && + group->state != PM_QOS_VOTED) { + group->state = PM_QOS_REQ_VOTE; + queue_work(host->pm_qos.workq, &group->vote_work); + } out: - return err; + spin_unlock_irqrestore(hba->host->host_lock, flags); +} + +/* hba->host->host_lock is assumed to be held by caller */ +static void __ufs_qcom_pm_qos_req_end(struct ufs_qcom_host *host, int req_cpu) +{ + struct ufs_qcom_pm_qos_cpu_group *group; + + if (!host->pm_qos.groups || !host->pm_qos.is_enabled) + return; + + group = &host->pm_qos.groups[ufs_qcom_cpu_to_group(host, req_cpu)]; + + if (--group->active_reqs) + return; + group->state = PM_QOS_REQ_UNVOTE; + queue_work(host->pm_qos.workq, &group->unvote_work); +} + +static void ufs_qcom_pm_qos_req_end(struct ufs_hba *hba, struct request *req, + bool should_lock) +{ + unsigned long flags = 0; + + if (!hba || !req) + return; + + if (should_lock) + spin_lock_irqsave(hba->host->host_lock, flags); + __ufs_qcom_pm_qos_req_end(ufshcd_get_variant(hba), req->cpu); + if (should_lock) + spin_unlock_irqrestore(hba->host->host_lock, flags); +} + +static void ufs_qcom_pm_qos_vote_work(struct work_struct *work) +{ + struct ufs_qcom_pm_qos_cpu_group *group = + container_of(work, struct ufs_qcom_pm_qos_cpu_group, vote_work); + struct ufs_qcom_host *host = group->host; + unsigned long flags; + + spin_lock_irqsave(host->hba->host->host_lock, flags); + + if (!host->pm_qos.is_enabled || !group->active_reqs) { + spin_unlock_irqrestore(host->hba->host->host_lock, flags); + return; + } + + group->state = PM_QOS_VOTED; + spin_unlock_irqrestore(host->hba->host->host_lock, flags); + + pm_qos_update_request(&group->req, group->latency_us); +} + +static void ufs_qcom_pm_qos_unvote_work(struct work_struct *work) +{ + struct ufs_qcom_pm_qos_cpu_group *group = container_of(work, + struct ufs_qcom_pm_qos_cpu_group, unvote_work); + struct ufs_qcom_host *host = group->host; + unsigned long flags; + + /* + * Check if new requests were submitted in the meantime and do not + * unvote if so. + */ + spin_lock_irqsave(host->hba->host->host_lock, flags); + + if (!host->pm_qos.is_enabled || group->active_reqs) { + spin_unlock_irqrestore(host->hba->host->host_lock, flags); + return; + } + + group->state = PM_QOS_UNVOTED; + spin_unlock_irqrestore(host->hba->host->host_lock, flags); + + pm_qos_update_request_timeout(&group->req, + group->latency_us, UFS_QCOM_PM_QOS_UNVOTE_TIMEOUT_US); +} + +static ssize_t ufs_qcom_pm_qos_enable_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct ufs_hba *hba = dev_get_drvdata(dev->parent); + struct ufs_qcom_host *host = ufshcd_get_variant(hba); + + return snprintf(buf, PAGE_SIZE, "%d\n", host->pm_qos.is_enabled); +} + +static ssize_t ufs_qcom_pm_qos_enable_store(struct device *dev, + struct device_attribute *attr, const char *buf, size_t count) +{ + struct ufs_hba *hba = dev_get_drvdata(dev->parent); + struct ufs_qcom_host *host = ufshcd_get_variant(hba); + unsigned long value; + unsigned long flags; + bool enable; + int i; + + if (kstrtoul(buf, 0, &value)) + return -EINVAL; + + enable = !!value; + + /* + * Must take the spinlock and save irqs before changing the enabled + * flag in order to keep correctness of PM QoS release. + */ + spin_lock_irqsave(hba->host->host_lock, flags); + if (enable == host->pm_qos.is_enabled) { + spin_unlock_irqrestore(hba->host->host_lock, flags); + return count; + } + host->pm_qos.is_enabled = enable; + spin_unlock_irqrestore(hba->host->host_lock, flags); + + if (!enable) + for (i = 0; i < host->pm_qos.num_groups; i++) { + cancel_work_sync(&host->pm_qos.groups[i].vote_work); + cancel_work_sync(&host->pm_qos.groups[i].unvote_work); + spin_lock_irqsave(hba->host->host_lock, flags); + host->pm_qos.groups[i].state = PM_QOS_UNVOTED; + host->pm_qos.groups[i].active_reqs = 0; + spin_unlock_irqrestore(hba->host->host_lock, flags); + pm_qos_update_request(&host->pm_qos.groups[i].req, + PM_QOS_DEFAULT_VALUE); + } + + return count; } +static ssize_t ufs_qcom_pm_qos_latency_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct ufs_hba *hba = dev_get_drvdata(dev->parent); + struct ufs_qcom_host *host = ufshcd_get_variant(hba); + int ret; + int i; + int offset = 0; + + for (i = 0; i < host->pm_qos.num_groups; i++) { + ret = snprintf(&buf[offset], PAGE_SIZE, + "cpu group #%d(mask=0x%lx): %d\n", i, + host->pm_qos.groups[i].mask.bits[0], + host->pm_qos.groups[i].latency_us); + if (ret > 0) + offset += ret; + else + break; + } + + return offset; +} + +static ssize_t ufs_qcom_pm_qos_latency_store(struct device *dev, + struct device_attribute *attr, const char *buf, size_t count) +{ + struct ufs_hba *hba = dev_get_drvdata(dev->parent); + struct ufs_qcom_host *host = ufshcd_get_variant(hba); + unsigned long value; + unsigned long flags; + char *strbuf; + char *strbuf_copy; + char *token; + int i; + int ret; + + /* reserve one byte for null termination */ + strbuf = kmalloc(count + 1, GFP_KERNEL); + if (!strbuf) + return -ENOMEM; + strbuf_copy = strbuf; + strlcpy(strbuf, buf, count + 1); + + for (i = 0; i < host->pm_qos.num_groups; i++) { + token = strsep(&strbuf, ","); + if (!token) + break; + + ret = kstrtoul(token, 0, &value); + if (ret) + break; + + spin_lock_irqsave(hba->host->host_lock, flags); + host->pm_qos.groups[i].latency_us = value; + spin_unlock_irqrestore(hba->host->host_lock, flags); + } + + kfree(strbuf_copy); + return count; +} + +static int ufs_qcom_pm_qos_init(struct ufs_qcom_host *host) +{ + struct device_node *node = host->hba->dev->of_node; + struct device_attribute *attr; + int ret = 0; + int num_groups; + int num_values; + char wq_name[sizeof("ufs_pm_qos_00")]; + int i; + + num_groups = of_property_count_u32_elems(node, + "qcom,pm-qos-cpu-groups"); + if (num_groups <= 0) + goto no_pm_qos; + + num_values = of_property_count_u32_elems(node, + "qcom,pm-qos-cpu-group-latency-us"); + if (num_values <= 0) + goto no_pm_qos; + + if (num_values != num_groups || num_groups > num_possible_cpus()) { + dev_err(host->hba->dev, "%s: invalid count: num_groups=%d, num_values=%d, num_possible_cpus=%d\n", + __func__, num_groups, num_values, num_possible_cpus()); + goto no_pm_qos; + } + + host->pm_qos.num_groups = num_groups; + host->pm_qos.groups = kcalloc(host->pm_qos.num_groups, + sizeof(struct ufs_qcom_pm_qos_cpu_group), GFP_KERNEL); + if (!host->pm_qos.groups) + return -ENOMEM; + + for (i = 0; i < host->pm_qos.num_groups; i++) { + u32 mask; + + ret = of_property_read_u32_index(node, "qcom,pm-qos-cpu-groups", + i, &mask); + if (ret) + goto free_groups; + host->pm_qos.groups[i].mask.bits[0] = mask; + if (!cpumask_subset(&host->pm_qos.groups[i].mask, + cpu_possible_mask)) { + dev_err(host->hba->dev, "%s: invalid mask 0x%x for cpu group\n", + __func__, mask); + goto free_groups; + } + + ret = of_property_read_u32_index(node, + "qcom,pm-qos-cpu-group-latency-us", i, + &host->pm_qos.groups[i].latency_us); + if (ret) + goto free_groups; + + host->pm_qos.groups[i].req.type = PM_QOS_REQ_AFFINE_CORES; + host->pm_qos.groups[i].req.cpus_affine = + host->pm_qos.groups[i].mask; + host->pm_qos.groups[i].state = PM_QOS_UNVOTED; + host->pm_qos.groups[i].active_reqs = 0; + host->pm_qos.groups[i].host = host; + + INIT_WORK(&host->pm_qos.groups[i].vote_work, + ufs_qcom_pm_qos_vote_work); + INIT_WORK(&host->pm_qos.groups[i].unvote_work, + ufs_qcom_pm_qos_unvote_work); + } + + ret = of_property_read_u32(node, "qcom,pm-qos-default-cpu", + &host->pm_qos.default_cpu); + if (ret || host->pm_qos.default_cpu > num_possible_cpus()) + host->pm_qos.default_cpu = 0; + + /* + * Use a single-threaded workqueue to assure work submitted to the queue + * is performed in order. Consider the following 2 possible cases: + * + * 1. A new request arrives and voting work is scheduled for it. Before + * the voting work is performed the request is finished and unvote + * work is also scheduled. + * 2. A request is finished and unvote work is scheduled. Before the + * work is performed a new request arrives and voting work is also + * scheduled. + * + * In both cases a vote work and unvote work wait to be performed. + * If ordering is not guaranteed, then the end state might be the + * opposite of the desired state. + */ + snprintf(wq_name, ARRAY_SIZE(wq_name), "%s_%d", "ufs_pm_qos", + host->hba->host->host_no); + host->pm_qos.workq = create_singlethread_workqueue(wq_name); + if (!host->pm_qos.workq) { + dev_err(host->hba->dev, "%s: failed to create the workqueue\n", + __func__); + ret = -ENOMEM; + goto free_groups; + } + + /* Initialization was ok, add all PM QoS requests */ + for (i = 0; i < host->pm_qos.num_groups; i++) + pm_qos_add_request(&host->pm_qos.groups[i].req, + PM_QOS_CPU_DMA_LATENCY, PM_QOS_DEFAULT_VALUE); + + /* PM QoS latency sys-fs attribute */ + attr = &host->pm_qos.latency_attr; + attr->show = ufs_qcom_pm_qos_latency_show; + attr->store = ufs_qcom_pm_qos_latency_store; + sysfs_attr_init(&attr->attr); + attr->attr.name = "pm_qos_latency_us"; + attr->attr.mode = S_IRUGO | S_IWUSR; + if (device_create_file(host->hba->var->dev, attr)) + dev_dbg(host->hba->dev, "Failed to create sysfs for pm_qos_latency_us\n"); + + /* PM QoS enable sys-fs attribute */ + attr = &host->pm_qos.enable_attr; + attr->show = ufs_qcom_pm_qos_enable_show; + attr->store = ufs_qcom_pm_qos_enable_store; + sysfs_attr_init(&attr->attr); + attr->attr.name = "pm_qos_enable"; + attr->attr.mode = S_IRUGO | S_IWUSR; + if (device_create_file(host->hba->var->dev, attr)) + dev_dbg(host->hba->dev, "Failed to create sysfs for pm_qos enable\n"); + + host->pm_qos.is_enabled = true; + + return 0; + +free_groups: + kfree(host->pm_qos.groups); +no_pm_qos: + host->pm_qos.groups = NULL; + return ret ? ret : -ENOTSUPP; +} + +static void ufs_qcom_pm_qos_suspend(struct ufs_qcom_host *host) +{ + int i; + + if (!host->pm_qos.groups) + return; + + for (i = 0; i < host->pm_qos.num_groups; i++) + flush_work(&host->pm_qos.groups[i].unvote_work); +} + +static void ufs_qcom_pm_qos_remove(struct ufs_qcom_host *host) +{ + int i; + + if (!host->pm_qos.groups) + return; + + for (i = 0; i < host->pm_qos.num_groups; i++) + pm_qos_remove_request(&host->pm_qos.groups[i].req); + destroy_workqueue(host->pm_qos.workq); + + kfree(host->pm_qos.groups); + host->pm_qos.groups = NULL; +} +#endif /* CONFIG_SMP */ + #define ANDROID_BOOT_DEV_MAX 30 static char android_boot_dev[ANDROID_BOOT_DEV_MAX]; @@ -1126,6 +2012,69 @@ __setup("androidboot.bootdevice=", get_android_boot_dev); #endif +/* + * ufs_qcom_parse_lpm - read from DTS whether LPM modes should be disabled. + */ +static void ufs_qcom_parse_lpm(struct ufs_qcom_host *host) +{ + struct device_node *node = host->hba->dev->of_node; + + host->disable_lpm = of_property_read_bool(node, "qcom,disable-lpm"); + if (host->disable_lpm) + pr_info("%s: will disable all LPM modes\n", __func__); +} + +static int ufs_qcom_parse_reg_info(struct ufs_qcom_host *host, char *name, + struct ufs_vreg **out_vreg) +{ + int ret = 0; + char prop_name[MAX_PROP_SIZE]; + struct ufs_vreg *vreg = NULL; + struct device *dev = host->hba->dev; + struct device_node *np = dev->of_node; + + if (!np) { + dev_err(dev, "%s: non DT initialization\n", __func__); + goto out; + } + + snprintf(prop_name, MAX_PROP_SIZE, "%s-supply", name); + if (!of_parse_phandle(np, prop_name, 0)) { + dev_info(dev, "%s: Unable to find %s regulator, assuming enabled\n", + __func__, prop_name); + ret = -ENODEV; + goto out; + } + + vreg = devm_kzalloc(dev, sizeof(*vreg), GFP_KERNEL); + if (!vreg) + return -ENOMEM; + + vreg->name = name; + + snprintf(prop_name, MAX_PROP_SIZE, "%s-max-microamp", name); + ret = of_property_read_u32(np, prop_name, &vreg->max_uA); + if (ret) { + dev_err(dev, "%s: unable to find %s err %d\n", + __func__, prop_name, ret); + goto out; + } + + vreg->reg = devm_regulator_get(dev, vreg->name); + if (IS_ERR(vreg->reg)) { + ret = PTR_ERR(vreg->reg); + dev_err(dev, "%s: %s get failed, err=%d\n", + __func__, vreg->name, ret); + } + vreg->min_uV = VDDP_REF_CLK_MIN_UV; + vreg->max_uV = VDDP_REF_CLK_MAX_UV; + +out: + if (!ret) + *out_vreg = vreg; + return ret; +} + /** * ufs_qcom_init - bind phy with controller * @hba: host controller instance @@ -1144,9 +2093,6 @@ struct ufs_qcom_host *host; struct resource *res; - if (strlen(android_boot_dev) && strcmp(android_boot_dev, dev_name(dev))) - return -ENODEV; - host = devm_kzalloc(dev, sizeof(*host), GFP_KERNEL); if (!host) { err = -ENOMEM; @@ -1156,21 +2102,58 @@ /* Make a two way bind between the qcom host and the hba */ host->hba = hba; + spin_lock_init(&host->ice_work_lock); + ufshcd_set_variant(hba, host); + err = ufs_qcom_ice_get_dev(host); + if (err == -EPROBE_DEFER) { + /* + * UFS driver might be probed before ICE driver does. + * In that case we would like to return EPROBE_DEFER code + * in order to delay its probing. + */ + dev_err(dev, "%s: required ICE device not probed yet err = %d\n", + __func__, err); + goto out_host_free; + + } else if (err == -ENODEV) { /* - * voting/devoting device ref_clk source is time consuming hence - * skip devoting it during aggressive clock gating. This clock - * will still be gated off during runtime suspend. + * ICE device is not enabled in DTS file. No need for further + * initialization of ICE driver. */ + dev_warn(dev, "%s: ICE device is not enabled", + __func__); + } else if (err) { + dev_err(dev, "%s: ufs_qcom_ice_get_dev failed %d\n", + __func__, err); + goto out_host_free; + } + host->generic_phy = devm_phy_get(dev, "ufsphy"); - if (IS_ERR(host->generic_phy)) { + if (host->generic_phy == ERR_PTR(-EPROBE_DEFER)) { + /* + * UFS driver might be probed before the phy driver does. + * In that case we would like to return EPROBE_DEFER code. + */ + err = -EPROBE_DEFER; + dev_warn(dev, "%s: required phy device. hasn't probed yet. err = %d\n", + __func__, err); + goto out_host_free; + } else if (IS_ERR(host->generic_phy)) { err = PTR_ERR(host->generic_phy); dev_err(dev, "%s: PHY get failed %d\n", __func__, err); goto out; } + err = ufs_qcom_pm_qos_init(host); + if (err) + dev_info(dev, "%s: PM QoS will be disabled\n", __func__); + + /* restore the secure configuration */ + ufs_qcom_update_sec_cfg(hba, true); + err = ufs_qcom_bus_register(host); if (err) goto out_host_free; @@ -1206,19 +2189,33 @@ ufs_qcom_phy_save_controller_version(host->generic_phy, host->hw_ver.major, host->hw_ver.minor, host->hw_ver.step); + err = ufs_qcom_parse_reg_info(host, "qcom,vddp-ref-clk", + &host->vddp_ref_clk); phy_init(host->generic_phy); err = phy_power_on(host->generic_phy); if (err) goto out_unregister_bus; + if (host->vddp_ref_clk) { + err = ufs_qcom_enable_vreg(dev, host->vddp_ref_clk); + if (err) { + dev_err(dev, "%s: failed enabling ref clk supply: %d\n", + __func__, err); + goto out_disable_phy; + } + } err = ufs_qcom_init_lane_clks(host); if (err) - goto out_disable_phy; + goto out_disable_vddp; + ufs_qcom_parse_lpm(host); + if (host->disable_lpm) + pm_runtime_forbid(host->hba->dev); ufs_qcom_set_caps(hba); ufs_qcom_advertise_quirks(hba); - ufs_qcom_setup_clocks(hba, true); + ufs_qcom_set_bus_vote(hba, true); + ufs_qcom_setup_clocks(hba, true, false); if (hba->dev->id < MAX_UFS_QCOM_HOSTS) ufs_qcom_hosts[hba->dev->id] = host; @@ -1234,10 +2231,14 @@ goto out; +out_disable_vddp: + if (host->vddp_ref_clk) + ufs_qcom_disable_vreg(dev, host->vddp_ref_clk); out_disable_phy: phy_power_off(host->generic_phy); out_unregister_bus: phy_exit(host->generic_phy); + msm_bus_scale_unregister_client(host->bus_vote.client_handle); out_host_free: devm_kfree(dev, host); ufshcd_set_variant(hba, NULL); @@ -1249,8 +2250,10 @@ { struct ufs_qcom_host *host = ufshcd_get_variant(hba); + msm_bus_scale_unregister_client(host->bus_vote.client_handle); ufs_qcom_disable_lane_clks(host); phy_power_off(host->generic_phy); + ufs_qcom_pm_qos_remove(host); } static int ufs_qcom_set_dme_vs_core_clk_ctrl_clear_div(struct ufs_hba *hba, @@ -1281,105 +2284,292 @@ return err; } -static int ufs_qcom_clk_scale_up_pre_change(struct ufs_hba *hba) +static inline int ufs_qcom_configure_lpm(struct ufs_hba *hba, bool enable) { - /* nothing to do as of now */ - return 0; + struct ufs_qcom_host *host = ufshcd_get_variant(hba); + struct phy *phy = host->generic_phy; + int err = 0; + + /* The default low power mode configuration is SVS2 */ + if (!ufs_qcom_cap_svs2(host)) + goto out; + + if (!((host->hw_ver.major == 0x3) && + (host->hw_ver.minor == 0x0) && + (host->hw_ver.step == 0x0))) + goto out; + + /* + * The link should be put in hibern8 state before + * configuring the PHY to enter/exit SVS2 mode. + */ + err = ufshcd_uic_hibern8_enter(hba); + if (err) + goto out; + + err = ufs_qcom_phy_configure_lpm(phy, enable); + if (err) + goto out; + + err = ufshcd_uic_hibern8_exit(hba); +out: + return err; } -static int ufs_qcom_clk_scale_up_post_change(struct ufs_hba *hba) +static int ufs_qcom_clk_scale_up_pre_change(struct ufs_hba *hba) { struct ufs_qcom_host *host = ufshcd_get_variant(hba); + struct ufs_pa_layer_attr *attr = &host->dev_req_params; + int err = 0; if (!ufs_qcom_cap_qunipro(host)) - return 0; + goto out; + + err = ufs_qcom_configure_lpm(hba, false); + if (err) + goto out; + + if (attr) + __ufs_qcom_cfg_timers(hba, attr->gear_rx, attr->pwr_rx, + attr->hs_rate, false, true); /* set unipro core clock cycles to 150 and clear clock divider */ - return ufs_qcom_set_dme_vs_core_clk_ctrl_clear_div(hba, 150); + err = ufs_qcom_set_dme_vs_core_clk_ctrl_clear_div(hba, 150); +out: + return err; } static int ufs_qcom_clk_scale_down_pre_change(struct ufs_hba *hba) { struct ufs_qcom_host *host = ufshcd_get_variant(hba); - int err; - u32 core_clk_ctrl_reg; if (!ufs_qcom_cap_qunipro(host)) return 0; - err = ufshcd_dme_get(hba, - UIC_ARG_MIB(DME_VS_CORE_CLK_CTRL), - &core_clk_ctrl_reg); - - /* make sure CORE_CLK_DIV_EN is cleared */ - if (!err && - (core_clk_ctrl_reg & DME_VS_CORE_CLK_CTRL_CORE_CLK_DIV_EN_BIT)) { - core_clk_ctrl_reg &= ~DME_VS_CORE_CLK_CTRL_CORE_CLK_DIV_EN_BIT; - err = ufshcd_dme_set(hba, - UIC_ARG_MIB(DME_VS_CORE_CLK_CTRL), - core_clk_ctrl_reg); - } - - return err; + return ufs_qcom_configure_lpm(hba, true); } static int ufs_qcom_clk_scale_down_post_change(struct ufs_hba *hba) { struct ufs_qcom_host *host = ufshcd_get_variant(hba); + struct ufs_pa_layer_attr *attr = &host->dev_req_params; + int err = 0; if (!ufs_qcom_cap_qunipro(host)) return 0; - /* set unipro core clock cycles to 75 and clear clock divider */ - return ufs_qcom_set_dme_vs_core_clk_ctrl_clear_div(hba, 75); + if (attr) + ufs_qcom_cfg_timers(hba, attr->gear_rx, attr->pwr_rx, + attr->hs_rate, false); + + if (ufs_qcom_cap_svs2(host)) + /* + * For SVS2 set unipro core clock cycles to 37 and + * clear clock divider + */ + err = ufs_qcom_set_dme_vs_core_clk_ctrl_clear_div(hba, 37); + else + /* + * For SVS set unipro core clock cycles to 75 and + * clear clock divider + */ + err = ufs_qcom_set_dme_vs_core_clk_ctrl_clear_div(hba, 75); + + return err; } static int ufs_qcom_clk_scale_notify(struct ufs_hba *hba, bool scale_up, enum ufs_notify_change_status status) { struct ufs_qcom_host *host = ufshcd_get_variant(hba); - struct ufs_pa_layer_attr *dev_req_params = &host->dev_req_params; int err = 0; - if (status == PRE_CHANGE) { + switch (status) { + case PRE_CHANGE: if (scale_up) err = ufs_qcom_clk_scale_up_pre_change(hba); else err = ufs_qcom_clk_scale_down_pre_change(hba); - } else { - if (scale_up) - err = ufs_qcom_clk_scale_up_post_change(hba); - else + break; + case POST_CHANGE: + if (!scale_up) err = ufs_qcom_clk_scale_down_post_change(hba); - if (err || !dev_req_params) + ufs_qcom_update_bus_bw_vote(host); + break; + default: + dev_err(hba->dev, "%s: invalid status %d\n", __func__, status); + err = -EINVAL; + break; + } + + return err; +} + +/* + * This function should be called to restore the security configuration of UFS + * register space after coming out of UFS host core power collapse. + * + * @hba: host controller instance + * @restore_sec_cfg: Set "true" if secure configuration needs to be restored + * and set "false" when secure configuration is lost. + */ +static int ufs_qcom_update_sec_cfg(struct ufs_hba *hba, bool restore_sec_cfg) +{ + int ret = 0; + u64 scm_ret = 0; + struct ufs_qcom_host *host = ufshcd_get_variant(hba); + + /* scm command buffer structrue */ + struct msm_scm_cmd_buf { + unsigned int device_id; + unsigned int spare; + } cbuf = {0}; + #define RESTORE_SEC_CFG_CMD 0x2 + #define UFS_TZ_DEV_ID 19 + + if (!host || !hba->vreg_info.vdd_hba || + !(host->sec_cfg_updated ^ restore_sec_cfg)) { + return 0; + } else if (host->caps & + UFS_QCOM_CAP_RETAIN_SEC_CFG_AFTER_PWR_COLLAPSE) { + return 0; + } else if (!restore_sec_cfg) { + /* + * Clear the flag so next time when this function is called + * with restore_sec_cfg set to true, we can restore the secure + * configuration. + */ + host->sec_cfg_updated = false; + goto out; + } else if (hba->clk_gating.state != CLKS_ON) { + /* + * Clocks should be ON to restore the host controller secure + * configuration. + */ goto out; + } - ufs_qcom_cfg_timers(hba, - dev_req_params->gear_rx, - dev_req_params->pwr_rx, - dev_req_params->hs_rate, - false); - ufs_qcom_update_bus_bw_vote(host); + /* + * If we are here, Host controller clocks are running, Host controller + * power collapse feature is supported and Host controller has just came + * out of power collapse. + */ + cbuf.device_id = UFS_TZ_DEV_ID; + ret = scm_restore_sec_cfg(cbuf.device_id, cbuf.spare, &scm_ret); + if (ret || scm_ret) { + dev_dbg(hba->dev, "%s: failed, ret %d scm_ret %llu\n", + __func__, ret, scm_ret); + if (!ret) + ret = scm_ret; + } else { + host->sec_cfg_updated = true; } out: - return err; + dev_dbg(hba->dev, "%s: ip: restore_sec_cfg %d, op: restore_sec_cfg %d, ret %d scm_ret %llu\n", + __func__, restore_sec_cfg, host->sec_cfg_updated, ret, scm_ret); + return ret; +} + + +static inline u32 ufs_qcom_get_scale_down_gear(struct ufs_hba *hba) +{ + struct ufs_qcom_host *host = ufshcd_get_variant(hba); + + if (ufs_qcom_cap_svs2(host)) + return UFS_HS_G1; + /* Default SVS support @ HS G2 frequencies*/ + return UFS_HS_G2; +} + +void ufs_qcom_print_hw_debug_reg_all(struct ufs_hba *hba, void *priv, + void (*print_fn)(struct ufs_hba *hba, int offset, int num_regs, + char *str, void *priv)) +{ + u32 reg; + struct ufs_qcom_host *host; + + if (unlikely(!hba)) { + pr_err("%s: hba is NULL\n", __func__); + return; + } + if (unlikely(!print_fn)) { + dev_err(hba->dev, "%s: print_fn is NULL\n", __func__); + return; + } + + host = ufshcd_get_variant(hba); + if (!(host->dbg_print_en & UFS_QCOM_DBG_PRINT_REGS_EN)) + return; + + reg = ufs_qcom_get_debug_reg_offset(host, UFS_UFS_DBG_RD_REG_OCSC); + print_fn(hba, reg, 44, "UFS_UFS_DBG_RD_REG_OCSC ", priv); + + reg = ufshcd_readl(hba, REG_UFS_CFG1); + reg |= UFS_BIT(17); + ufshcd_writel(hba, reg, REG_UFS_CFG1); + + reg = ufs_qcom_get_debug_reg_offset(host, UFS_UFS_DBG_RD_EDTL_RAM); + print_fn(hba, reg, 32, "UFS_UFS_DBG_RD_EDTL_RAM ", priv); + + reg = ufs_qcom_get_debug_reg_offset(host, UFS_UFS_DBG_RD_DESC_RAM); + print_fn(hba, reg, 128, "UFS_UFS_DBG_RD_DESC_RAM ", priv); + + reg = ufs_qcom_get_debug_reg_offset(host, UFS_UFS_DBG_RD_PRDT_RAM); + print_fn(hba, reg, 64, "UFS_UFS_DBG_RD_PRDT_RAM ", priv); + + /* clear bit 17 - UTP_DBG_RAMS_EN */ + ufshcd_rmwl(hba, UFS_BIT(17), 0, REG_UFS_CFG1); + + reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_UAWM); + print_fn(hba, reg, 4, "UFS_DBG_RD_REG_UAWM ", priv); + + reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_UARM); + print_fn(hba, reg, 4, "UFS_DBG_RD_REG_UARM ", priv); + + reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_TXUC); + print_fn(hba, reg, 48, "UFS_DBG_RD_REG_TXUC ", priv); + + reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_RXUC); + print_fn(hba, reg, 27, "UFS_DBG_RD_REG_RXUC ", priv); + + reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_DFC); + print_fn(hba, reg, 19, "UFS_DBG_RD_REG_DFC ", priv); + + reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_TRLUT); + print_fn(hba, reg, 34, "UFS_DBG_RD_REG_TRLUT ", priv); + + reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_TMRLUT); + print_fn(hba, reg, 9, "UFS_DBG_RD_REG_TMRLUT ", priv); +} + +static void ufs_qcom_enable_test_bus(struct ufs_qcom_host *host) +{ + if (host->dbg_print_en & UFS_QCOM_DBG_PRINT_TEST_BUS_EN) { + ufshcd_rmwl(host->hba, UFS_REG_TEST_BUS_EN, + UFS_REG_TEST_BUS_EN, REG_UFS_CFG1); + ufshcd_rmwl(host->hba, TEST_BUS_EN, TEST_BUS_EN, REG_UFS_CFG1); + } else { + ufshcd_rmwl(host->hba, UFS_REG_TEST_BUS_EN, 0, REG_UFS_CFG1); + ufshcd_rmwl(host->hba, TEST_BUS_EN, 0, REG_UFS_CFG1); + } } static void ufs_qcom_get_default_testbus_cfg(struct ufs_qcom_host *host) { /* provide a legal default configuration */ - host->testbus.select_major = TSTBUS_UAWM; - host->testbus.select_minor = 1; + host->testbus.select_major = TSTBUS_UNIPRO; + host->testbus.select_minor = 37; } -static bool ufs_qcom_testbus_cfg_is_ok(struct ufs_qcom_host *host) +bool ufs_qcom_testbus_cfg_is_ok(struct ufs_qcom_host *host, + u8 select_major, u8 select_minor) { - if (host->testbus.select_major >= TSTBUS_MAX) { + if (select_major >= TSTBUS_MAX) { dev_err(host->hba->dev, "%s: UFS_CFG1[TEST_BUS_SEL} may not equal 0x%05X\n", - __func__, host->testbus.select_major); + __func__, select_major); return false; } @@ -1388,28 +2578,33 @@ * mappings of select_minor, since there is no harm in * configuring a non-existent select_minor */ - if (host->testbus.select_minor > 0x1F) { + if (select_minor > 0xFF) { dev_err(host->hba->dev, "%s: 0x%05X is not a legal testbus option\n", - __func__, host->testbus.select_minor); + __func__, select_minor); return false; } return true; } +/* + * The caller of this function must make sure that the controller + * is out of runtime suspend and appropriate clocks are enabled + * before accessing. + */ int ufs_qcom_testbus_config(struct ufs_qcom_host *host) { - int reg; - int offset; + int reg = 0; + int offset, ret = 0, testbus_sel_offset = 19; u32 mask = TEST_BUS_SUB_SEL_MASK; + unsigned long flags; + struct ufs_hba *hba; if (!host) return -EINVAL; - - if (!ufs_qcom_testbus_cfg_is_ok(host)) - return -EPERM; - + hba = host->hba; + spin_lock_irqsave(hba->host->host_lock, flags); switch (host->testbus.select_major) { case TSTBUS_UAWM: reg = UFS_TEST_BUS_CTRL_0; @@ -1457,7 +2652,8 @@ break; case TSTBUS_UNIPRO: reg = UFS_UNIPRO_CFG; - offset = 1; + offset = 20; + mask = 0xFFF; break; /* * No need for a default case, since @@ -1466,19 +2662,27 @@ */ } mask <<= offset; - - pm_runtime_get_sync(host->hba->dev); - ufshcd_hold(host->hba, false); + spin_unlock_irqrestore(hba->host->host_lock, flags); + if (reg) { ufshcd_rmwl(host->hba, TEST_BUS_SEL, - (u32)host->testbus.select_major << 19, + (u32)host->testbus.select_major << testbus_sel_offset, REG_UFS_CFG1); ufshcd_rmwl(host->hba, mask, (u32)host->testbus.select_minor << offset, reg); - ufshcd_release(host->hba); - pm_runtime_put_sync(host->hba->dev); - - return 0; + } else { + dev_err(hba->dev, "%s: Problem setting minor\n", __func__); + ret = -EINVAL; + goto out; + } + ufs_qcom_enable_test_bus(host); + /* + * Make sure the test bus configuration is + * committed before returning. + */ + mb(); +out: + return ret; } static void ufs_qcom_testbus_read(struct ufs_hba *hba) @@ -1486,13 +2690,50 @@ ufs_qcom_dump_regs(hba, UFS_TEST_BUS, 1, "UFS_TEST_BUS "); } -static void ufs_qcom_dump_dbg_regs(struct ufs_hba *hba) +static void ufs_qcom_print_unipro_testbus(struct ufs_hba *hba) { + struct ufs_qcom_host *host = ufshcd_get_variant(hba); + u32 *testbus = NULL; + int i, nminor = 256, testbus_len = nminor * sizeof(u32); + + testbus = kmalloc(testbus_len, GFP_KERNEL); + if (!testbus) + return; + + host->testbus.select_major = TSTBUS_UNIPRO; + for (i = 0; i < nminor; i++) { + host->testbus.select_minor = i; + ufs_qcom_testbus_config(host); + testbus[i] = ufshcd_readl(hba, UFS_TEST_BUS); + } + print_hex_dump(KERN_ERR, "UNIPRO_TEST_BUS ", DUMP_PREFIX_OFFSET, + 16, 4, testbus, testbus_len, false); + kfree(testbus); +} + +static void ufs_qcom_dump_dbg_regs(struct ufs_hba *hba, bool no_sleep) +{ + struct ufs_qcom_host *host = ufshcd_get_variant(hba); + struct phy *phy = host->generic_phy; + ufs_qcom_dump_regs(hba, REG_UFS_SYS1CLK_1US, 16, "HCI Vendor Specific Registers "); + ufs_qcom_print_hw_debug_reg_all(hba, NULL, ufs_qcom_dump_regs_wrapper); + + if (no_sleep) + return; + /* sleep a bit intermittently as we are dumping too much data */ + usleep_range(1000, 1100); ufs_qcom_testbus_read(hba); + usleep_range(1000, 1100); + ufs_qcom_print_unipro_testbus(hba); + usleep_range(1000, 1100); + ufs_qcom_phy_dbg_register_dump(phy); + usleep_range(1000, 1100); + ufs_qcom_ice_print_regs(host); } + /** * struct ufs_hba_qcom_vops - UFS QCOM specific variant operations * @@ -1500,7 +2741,6 @@ * handshake during initialization. */ static struct ufs_hba_variant_ops ufs_hba_qcom_vops = { - .name = "qcom", .init = ufs_qcom_init, .exit = ufs_qcom_exit, .get_ufs_hci_version = ufs_qcom_get_ufs_hci_version, @@ -1509,9 +2749,37 @@ .hce_enable_notify = ufs_qcom_hce_enable_notify, .link_startup_notify = ufs_qcom_link_startup_notify, .pwr_change_notify = ufs_qcom_pwr_change_notify, + .apply_dev_quirks = ufs_qcom_apply_dev_quirks, .suspend = ufs_qcom_suspend, .resume = ufs_qcom_resume, + .full_reset = ufs_qcom_full_reset, + .update_sec_cfg = ufs_qcom_update_sec_cfg, + .get_scale_down_gear = ufs_qcom_get_scale_down_gear, + .set_bus_vote = ufs_qcom_set_bus_vote, .dbg_register_dump = ufs_qcom_dump_dbg_regs, +#ifdef CONFIG_DEBUG_FS + .add_debugfs = ufs_qcom_dbg_add_debugfs, +#endif +}; + +static struct ufs_hba_crypto_variant_ops ufs_hba_crypto_variant_ops = { + .crypto_req_setup = ufs_qcom_crypto_req_setup, + .crypto_engine_cfg_start = ufs_qcom_crytpo_engine_cfg_start, + .crypto_engine_cfg_end = ufs_qcom_crytpo_engine_cfg_end, + .crypto_engine_reset = ufs_qcom_crytpo_engine_reset, + .crypto_engine_get_status = ufs_qcom_crypto_engine_get_status, +}; + +static struct ufs_hba_pm_qos_variant_ops ufs_hba_pm_qos_variant_ops = { + .req_start = ufs_qcom_pm_qos_req_start, + .req_end = ufs_qcom_pm_qos_req_end, +}; + +static struct ufs_hba_variant ufs_hba_qcom_variant = { + .name = "qcom", + .vops = &ufs_hba_qcom_vops, + .crypto_vops = &ufs_hba_crypto_variant_ops, + .pm_qos_vops = &ufs_hba_pm_qos_variant_ops, }; /** @@ -1524,9 +2792,27 @@ { int err; struct device *dev = &pdev->dev; + struct device_node *np = dev->of_node; + + /* + * On qcom platforms, bootdevice is the primary storage + * device. This device can either be eMMC or UFS. + * The type of device connected is detected at runtime. + * So, if an eMMC device is connected, and this function + * is invoked, it would turn-off the regulator if it detects + * that the storage device is not ufs. + * These regulators are turned ON by the bootloaders & turning + * them off without sending PON may damage the connected device. + * Hence, check for the connected device early-on & don't turn-off + * the regulators. + */ + if (of_property_read_bool(np, "non-removable") && + strlen(android_boot_dev) && + strcmp(android_boot_dev, dev_name(dev))) + return -ENODEV; /* Perform generic probe */ - err = ufshcd_pltfrm_init(pdev, &ufs_hba_qcom_vops); + err = ufshcd_pltfrm_init(pdev, &ufs_hba_qcom_variant); if (err) dev_err(dev, "ufshcd_pltfrm_init() failed %d\n", err); diff -ruw linux-4.4.115/drivers/scsi/ufs/ufs-qcom.h linux-4.4.115-fbx/drivers/scsi/ufs/ufs-qcom.h --- linux-4.4.115/drivers/scsi/ufs/ufs-qcom.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/scsi/ufs/ufs-qcom.h 2019-01-22 16:16:26.631274732 +0100 @@ -1,4 +1,4 @@ -/* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved. +/* Copyright (c) 2013-2017, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -14,9 +14,14 @@ #ifndef UFS_QCOM_H_ #define UFS_QCOM_H_ +#include +#include +#include "ufshcd.h" + #define MAX_UFS_QCOM_HOSTS 1 #define MAX_U32 (~(u32)0) #define MPHY_TX_FSM_STATE 0x41 +#define MPHY_RX_FSM_STATE 0xC1 #define TX_FSM_HIBERN8 0x1 #define HBRN8_POLL_TOUT_MS 100 #define DEFAULT_CLK_RATE_HZ 1000000 @@ -71,6 +76,7 @@ UFS_AH8_CFG = 0xFC, }; + /* QCOM UFS host controller vendor specific debug registers */ enum { UFS_DBG_RD_REG_UAWM = 0x100, @@ -94,7 +100,8 @@ /* bit definitions for REG_UFS_CFG1 register */ #define QUNIPRO_SEL UFS_BIT(0) #define TEST_BUS_EN BIT(18) -#define TEST_BUS_SEL GENMASK(22, 19) +#define TEST_BUS_SEL 0x780000 +#define UFS_REG_TEST_BUS_EN BIT(30) /* bit definitions for REG_UFS_CFG2 register */ #define UAWM_HW_CGC_EN (1 << 0) @@ -114,6 +121,17 @@ DFC_HW_CGC_EN | TRLUT_HW_CGC_EN |\ TMRLUT_HW_CGC_EN | OCSC_HW_CGC_EN) +/* bit definitions for UFS_AH8_CFG register */ +#define CC_UFS_HCLK_REQ_EN BIT(1) +#define CC_UFS_SYS_CLK_REQ_EN BIT(2) +#define CC_UFS_ICE_CORE_CLK_REQ_EN BIT(3) +#define CC_UFS_UNIPRO_CORE_CLK_REQ_EN BIT(4) +#define CC_UFS_AUXCLK_REQ_EN BIT(5) + +#define UFS_HW_CLK_CTRL_EN (CC_UFS_SYS_CLK_REQ_EN |\ + CC_UFS_ICE_CORE_CLK_REQ_EN |\ + CC_UFS_UNIPRO_CORE_CLK_REQ_EN |\ + CC_UFS_AUXCLK_REQ_EN) /* bit offset */ enum { OFFSET_UFS_PHY_SOFT_RESET = 1, @@ -142,10 +160,20 @@ UFS_QCOM_DBG_PRINT_TEST_BUS_EN) /* QUniPro Vendor specific attributes */ +#define PA_VS_CONFIG_REG1 0x9000 +#define SAVECONFIGTIME_MODE_MASK 0x6000 + +#define PA_VS_CLK_CFG_REG 0x9004 +#define PA_VS_CLK_CFG_REG_MASK 0x1FF + +#define DL_VS_CLK_CFG 0xA00B +#define DL_VS_CLK_CFG_MASK 0x3FF + #define DME_VS_CORE_CLK_CTRL 0xD002 /* bit and mask definitions for DME_VS_CORE_CLK_CTRL attribute */ -#define DME_VS_CORE_CLK_CTRL_CORE_CLK_DIV_EN_BIT BIT(8) #define DME_VS_CORE_CLK_CTRL_MAX_CORE_CLK_1US_CYCLES_MASK 0xFF +#define DME_VS_CORE_CLK_CTRL_CORE_CLK_DIV_EN_BIT BIT(8) +#define DME_VS_CORE_CLK_CTRL_DME_HW_CGC_EN BIT(9) static inline void ufs_qcom_get_controller_revision(struct ufs_hba *hba, @@ -192,6 +220,26 @@ struct device_attribute max_bus_bw; }; +/** + * struct ufs_qcom_ice_data - ICE related information + * @vops: pointer to variant operations of ICE + * @async_done: completion for supporting ICE's driver asynchronous nature + * @pdev: pointer to the proper ICE platform device + * @state: UFS-ICE interface's internal state (see + * ufs-qcom-ice.h for possible internal states) + * @quirks: UFS-ICE interface related quirks + * @crypto_engine_err: crypto engine errors + */ +struct ufs_qcom_ice_data { + struct qcom_ice_variant_ops *vops; + struct platform_device *pdev; + int state; + + u16 quirks; + + bool crypto_engine_err; +}; + /* Host controller hardware version: major.minor.step */ struct ufs_hw_version { u16 step; @@ -199,11 +247,76 @@ u8 major; }; +#ifdef CONFIG_DEBUG_FS +struct qcom_debugfs_files { + struct dentry *debugfs_root; + struct dentry *dbg_print_en; + struct dentry *testbus; + struct dentry *testbus_en; + struct dentry *testbus_cfg; + struct dentry *testbus_bus; + struct dentry *dbg_regs; + struct dentry *pm_qos; +}; +#endif + struct ufs_qcom_testbus { u8 select_major; u8 select_minor; }; +/* PM QoS voting state */ +enum ufs_qcom_pm_qos_state { + PM_QOS_UNVOTED, + PM_QOS_VOTED, + PM_QOS_REQ_VOTE, + PM_QOS_REQ_UNVOTE, +}; + +/** + * struct ufs_qcom_pm_qos_cpu_group - data related to cluster PM QoS voting + * logic + * @req: request object for PM QoS + * @vote_work: work object for voting procedure + * @unvote_work: work object for un-voting procedure + * @host: back pointer to the main structure + * @state: voting state machine current state + * @latency_us: requested latency value used for cluster voting, in + * microseconds + * @mask: cpu mask defined for this cluster + * @active_reqs: number of active requests on this cluster + */ +struct ufs_qcom_pm_qos_cpu_group { + struct pm_qos_request req; + struct work_struct vote_work; + struct work_struct unvote_work; + struct ufs_qcom_host *host; + enum ufs_qcom_pm_qos_state state; + s32 latency_us; + cpumask_t mask; + int active_reqs; +}; + +/** + * struct ufs_qcom_pm_qos - data related to PM QoS voting logic + * @groups: PM QoS cpu group state array + * @enable_attr: sysfs attribute to enable/disable PM QoS voting logic + * @latency_attr: sysfs attribute to set latency value + * @workq: single threaded workqueue to run PM QoS voting/unvoting + * @num_clusters: number of clusters defined + * @default_cpu: cpu to use for voting for request not specifying a cpu + * @is_enabled: flag specifying whether voting logic is enabled + */ +struct ufs_qcom_pm_qos { + struct ufs_qcom_pm_qos_cpu_group *groups; + struct device_attribute enable_attr; + struct device_attribute latency_attr; + struct workqueue_struct *workq; + int num_groups; + int default_cpu; + bool is_enabled; +}; + struct ufs_qcom_host { /* * Set this capability if host controller supports the QUniPro mode @@ -218,6 +331,17 @@ * configuration even after UFS controller core power collapse. */ #define UFS_QCOM_CAP_RETAIN_SEC_CFG_AFTER_PWR_COLLAPSE UFS_BIT(1) + + /* + * Set this capability if host controller supports Qunipro internal + * clock gating. + */ + #define UFS_QCOM_CAP_QUNIPRO_CLK_GATING UFS_BIT(2) + + /* + * Set this capability if host controller supports SVS2 frequencies. + */ + #define UFS_QCOM_CAP_SVS2 UFS_BIT(3) u32 caps; struct phy *generic_phy; @@ -228,24 +352,51 @@ struct clk *tx_l0_sync_clk; struct clk *rx_l1_sync_clk; struct clk *tx_l1_sync_clk; - bool is_lane_clks_enabled; + /* PM Quality-of-Service (QoS) data */ + struct ufs_qcom_pm_qos pm_qos; + + bool disable_lpm; + bool is_lane_clks_enabled; + bool sec_cfg_updated; + struct ufs_qcom_ice_data ice; void __iomem *dev_ref_clk_ctrl_mmio; bool is_dev_ref_clk_enabled; struct ufs_hw_version hw_ver; - u32 dev_ref_clk_en_mask; - +#ifdef CONFIG_DEBUG_FS + struct qcom_debugfs_files debugfs_files; +#endif /* Bitmask for enabling debug prints */ u32 dbg_print_en; struct ufs_qcom_testbus testbus; + + spinlock_t ice_work_lock; + struct work_struct ice_cfg_work; + struct request *req_pending; + struct ufs_vreg *vddp_ref_clk; + bool work_pending; +}; + +static inline u32 +ufs_qcom_get_debug_reg_offset(struct ufs_qcom_host *host, u32 reg) +{ + if (host->hw_ver.major <= 0x02) + return UFS_CNTLR_2_x_x_VEN_REGS_OFFSET(reg); + + return UFS_CNTLR_3_x_x_VEN_REGS_OFFSET(reg); }; #define ufs_qcom_is_link_off(hba) ufshcd_is_link_off(hba) #define ufs_qcom_is_link_active(hba) ufshcd_is_link_active(hba) #define ufs_qcom_is_link_hibern8(hba) ufshcd_is_link_hibern8(hba) +bool ufs_qcom_testbus_cfg_is_ok(struct ufs_qcom_host *host, u8 select_major, + u8 select_minor); int ufs_qcom_testbus_config(struct ufs_qcom_host *host); +void ufs_qcom_print_hw_debug_reg_all(struct ufs_hba *hba, void *priv, + void (*print_fn)(struct ufs_hba *hba, int offset, int num_regs, + char *str, void *priv)); static inline bool ufs_qcom_cap_qunipro(struct ufs_qcom_host *host) { @@ -255,4 +406,14 @@ return false; } +static inline bool ufs_qcom_cap_qunipro_clk_gating(struct ufs_qcom_host *host) +{ + return !!(host->caps & UFS_QCOM_CAP_QUNIPRO_CLK_GATING); +} + +static inline bool ufs_qcom_cap_svs2(struct ufs_qcom_host *host) +{ + return !!(host->caps & UFS_QCOM_CAP_SVS2); +} + #endif /* UFS_QCOM_H_ */ diff -ruw linux-4.4.115/drivers/scsi/ufs/unipro.h linux-4.4.115-fbx/drivers/scsi/ufs/unipro.h --- linux-4.4.115/drivers/scsi/ufs/unipro.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/scsi/ufs/unipro.h 2019-01-22 16:16:26.635274769 +0100 @@ -1,6 +1,4 @@ /* - * drivers/scsi/ufs/unipro.h - * * Copyright (C) 2013 Samsung Electronics Co., Ltd. * * This program is free software; you can redistribute it and/or modify @@ -15,6 +13,7 @@ /* * M-TX Configuration Attributes */ +#define TX_HIBERN8TIME_CAPABILITY 0x000F #define TX_MODE 0x0021 #define TX_HSRATE_SERIES 0x0022 #define TX_HSGEAR 0x0023 @@ -48,8 +47,16 @@ #define RX_ENTER_HIBERN8 0x00A7 #define RX_BYPASS_8B10B_ENABLE 0x00A8 #define RX_TERMINATION_FORCE_ENABLE 0x0089 +#define RX_MIN_ACTIVATETIME_CAPABILITY 0x008F +#define RX_HIBERN8TIME_CAPABILITY 0x0092 + +#define MPHY_RX_ATTR_ADDR_START 0x81 +#define MPHY_RX_ATTR_ADDR_END 0xC1 #define is_mphy_tx_attr(attr) (attr < RX_MODE) +#define RX_MIN_ACTIVATETIME_UNIT_US 100 +#define HIBERN8TIME_UNIT_US 100 + /* * PHY Adpater attributes */ @@ -70,6 +77,7 @@ #define PA_MAXRXSPEEDFAST 0x1541 #define PA_MAXRXSPEEDSLOW 0x1542 #define PA_TXLINKSTARTUPHS 0x1544 +#define PA_LOCAL_TX_LCC_ENABLE 0x155E #define PA_TXSPEEDFAST 0x1565 #define PA_TXSPEEDSLOW 0x1566 #define PA_REMOTEVERINFO 0x15A0 @@ -83,6 +91,7 @@ #define PA_MAXRXHSGEAR 0x1587 #define PA_RXHSUNTERMCAP 0x15A5 #define PA_RXLSTERMCAP 0x15A6 +#define PA_GRANULARITY 0x15AA #define PA_PACPREQTIMEOUT 0x1590 #define PA_PACPREQEOBTIMEOUT 0x1591 #define PA_HIBERN8TIME 0x15A7 @@ -110,6 +119,23 @@ #define PA_STALLNOCONFIGTIME 0x15A3 #define PA_SAVECONFIGTIME 0x15A4 +#define PA_TACTIVATE_TIME_UNIT_US 10 +#define PA_HIBERN8_TIME_UNIT_US 100 + +#define PA_GRANULARITY_MIN_VAL 1 +#define PA_GRANULARITY_MAX_VAL 6 + +/* PHY Adapter Protocol Constants */ +#define PA_MAXDATALANES 4 + +#define DL_FC0ProtectionTimeOutVal_Default 8191 +#define DL_TC0ReplayTimeOutVal_Default 65535 +#define DL_AFC0ReqTimeOutVal_Default 32767 + +#define DME_LocalFC0ProtectionTimeOutVal 0xD041 +#define DME_LocalTC0ReplayTimeOutVal 0xD042 +#define DME_LocalAFC0ReqTimeOutVal 0xD043 + /* PA power modes */ enum { FAST_MODE = 1, @@ -143,6 +169,16 @@ UFS_HS_G3, /* HS Gear 3 */ }; +enum ufs_unipro_ver { + UFS_UNIPRO_VER_RESERVED = 0, + UFS_UNIPRO_VER_1_40 = 1, /* UniPro version 1.40 */ + UFS_UNIPRO_VER_1_41 = 2, /* UniPro version 1.41 */ + UFS_UNIPRO_VER_1_6 = 3, /* UniPro version 1.6 */ + UFS_UNIPRO_VER_MAX = 4, /* UniPro unsupported version */ + /* UniPro version field mask in PA_LOCALVERINFO */ + UFS_UNIPRO_VER_MASK = 0xF, +}; + /* * Data Link Layer Attributes */ diff -ruw linux-4.4.115/drivers/soc/Makefile linux-4.4.115-fbx/drivers/soc/Makefile --- linux-4.4.115/drivers/soc/Makefile 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/soc/Makefile 2019-01-22 16:16:26.643274841 +0100 @@ -7,7 +7,9 @@ obj-$(CONFIG_ARCH_MEDIATEK) += mediatek/ obj-$(CONFIG_ARCH_QCOM) += qcom/ obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/ +obj-$(CONFIG_QCOM_SCM_QCPE) += qcom/ obj-$(CONFIG_ARCH_SUNXI) += sunxi/ obj-$(CONFIG_ARCH_TEGRA) += tegra/ obj-$(CONFIG_SOC_TI) += ti/ obj-$(CONFIG_PLAT_VERSATILE) += versatile/ +obj-$(CONFIG_ARCH_QCOM) += qcom/ diff -ruw linux-4.4.115/drivers/soc/qcom/Kconfig linux-4.4.115-fbx/drivers/soc/qcom/Kconfig --- linux-4.4.115/drivers/soc/qcom/Kconfig 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/soc/qcom/Kconfig 2019-10-29 09:26:24.805214550 +0100 @@ -1,6 +1,223 @@ # # QCOM Soc drivers # +source "drivers/soc/qcom/hab/Kconfig" + +config MSM_INRUSH_CURRENT_MITIGATION + bool "Inrush-current mitigation Driver" + help + This driver helps in mitigating in-rush current on MSM + chipsets which has voltage droop issues due to sudden + huge load on a rail. This driver introduces an intermediate + load to mitigate the in-rush current. + +config MSM_PFE_WA + depends on HW_PERF_EVENTS + bool "Enable a H/W PFE WA" + help + Sometimes the PFTLB entries get stuck in the invalid state and new + prefetches get dropped. For a workaround, count L1 prefeches dropped + due to PFTLB miss and reset H/W PFE when a overflow happens. + + If unsure, say N. + +config QCOM_COMMON_LOG + bool "QCOM Common Log Support" + help + Use this to export symbols of some log address and variables + that need to parse crash dump files to a memory dump table. This + table can be used by post analysis tools to extract information + from memory when device crashes. + +config MSM_SMEM + depends on ARCH_QCOM + depends on REMOTE_SPINLOCK_MSM + bool "MSM Shared Memory (SMEM)" + help + Support for the shared memory interface between the various + processors in the System on a Chip (SoC) which allows basic + inter-processor communication. + +config QPNP_HAPTIC + tristate "Haptic support for QPNP PMIC" + depends on ARCH_QCOM + help + This option enables device driver support for the haptic peripheral + found on Qualcomm Technologies, Inc. QPNP PMICs. The haptic + peripheral is capable of driving both LRA and ERM vibrators. This + module provides haptic feedback for user actions such as a long press + on the touch screen. It uses the Android timed-output framework. + +config QPNP_PBS + tristate "PBS trigger support for QPNP PMIC" + depends on SPMI + help + This driver supports configuring software PBS trigger event through PBS + RAM on Qualcomm Technologies, Inc. QPNP PMICs. This module provides + the APIs to the client drivers that wants to send the PBS trigger + event to the PBS RAM. + +config MSM_SMD + depends on MSM_SMEM + bool "MSM Shared Memory Driver (SMD)" + help + Support for the shared memory interprocessor communication protocol + which provides virual point to point serial channels between processes + on the apps processor and processes on other processors in the SoC. + Also includes support for the Shared Memory State Machine (SMSM) + protocol which provides a mechanism to publish single bit state + information to one or more processors in the SoC. + +config MSM_SMD_DEBUG + depends on MSM_SMD + bool "MSM SMD debug support" + help + Support for debugging SMD and SMSM communication between apps and + other processors in the SoC. Debug support primarily consists of + logs consisting of information such as what interrupts were processed, + what channels caused interrupt activity, and when internal state + change events occur. + +config MSM_GLINK + bool "Generic Link (G-Link)" + help + G-Link is a generic link transport that replaces SMD. It is used + within a System-on-Chip (SoC) for communication between both internal + processors and external peripherals. The actual physical transport + is handled by transport plug-ins that can be individually enabled and + configured separately. + +config MSM_GLINK_LOOPBACK_SERVER + bool "Generic Link (G-Link) Loopback Server" + help + G-Link Loopback Server that enable loopback test framework to test + and validate the G-Link protocol stack. It support both local and + remote clients to configure the loopback server and echo back the + data received from the clients. + +config MSM_GLINK_SMD_XPRT + depends on MSM_SMD + depends on MSM_GLINK + bool "Generic Link (G-Link) SMD Transport" + help + G-Link SMD Transport is a G-Link Transport plug-in. It allows G-Link + communication to remote entities through a SMD physical transport + channel. The remote side is assumed to be pure SMD. The nature of + SMD limits this G-Link transport to only connecting with entities + internal to the System-on-Chip. + +config MSM_GLINK_SMEM_NATIVE_XPRT + depends on MSM_SMEM + depends on MSM_GLINK + bool "Generic Link (G-Link) SMEM Native Transport" + help + G-Link SMEM Native Transport is a G-Link Transport plug-in. It allows + G-Link communication to remote entities through a shared memory + physical transport. The nature of shared memory limits this G-Link + transport to only connecting with entities internal to the + System-on-Chip. + +config MSM_GLINK_SPI_XPRT + depends on MSM_GLINK + tristate "Generic Link (G-Link) SPI Transport" + help + G-Link SPI Transport is a Transport plug-in developed over SPI + bus. This transport plug-in performs marshaling of G-Link + commands & data to the appropriate SPI bus wire format and + allows for G-Link communication with remote subsystems that are + external to the System-on-Chip. + +config MSM_SPCOM + depends on MSM_GLINK + bool "Secure Processor Communication over GLINK" + help + spcom driver allows loading Secure Processor Applications and + sending messages to Secure Processor Applications. + spcom provides interface to both user space app and kernel driver. + It is using glink as the transport layer, which provides multiple + logical channels over signle physical channel. + The physical layer is based on shared memory and interrupts. + spcom provides clients/server API, although currently only one client + or server is allowed per logical channel. + +config MSM_SPSS_UTILS + depends on MSM_PIL + bool "Secure Processor Utilities" + help + spss-utils driver selects Secure Processor firmware file name. + The firmware file name for test or production is selected based + on a test fuse. + Different file name is used for differnt SPSS HW versions, + because the SPSS firmware size is too small to support multiple + HW versions. + +config MSM_SMEM_LOGGING + depends on MSM_SMEM + bool "MSM Shared Memory Logger" + help + Enable the shared memory logging to log the events between + the various processors in the system. This option exposes + the shared memory logger at /dev/smem_log and a debugfs node + named smem_log. + +config MSM_SMP2P + bool "SMSM Point-to-Point (SMP2P)" + depends on MSM_SMEM + help + Provide point-to-point remote signaling support. + SMP2P enables transferring 32-bit values between + the local and a remote system using shared + memory and interrupts. A client can open multiple + 32-bit values by specifying a unique string and + remote processor ID. + +config MSM_SMP2P_TEST + bool "SMSM Point-to-Point Test" + depends on MSM_SMP2P + help + Enables loopback and unit testing support for + SMP2P. Loopback support is used by other + processors to do unit testing. Unit tests + are used to verify the local and remote + implementations. + +config MSM_QMI_INTERFACE + depends on IPC_ROUTER + depends on QMI_ENCDEC + bool "MSM QMI Interface Library" + help + Library to send and receive QMI messages over IPC Router. + This library provides interface functions to the kernel drivers + to perform QMI message marshaling and transport them over IPC + Router. + +config MSM_L2_IA_DEBUG + bool "Enable MSM L2 Indirect Access Debug" + depends on DEBUG_FS + default n + help + This option enables L2 indirect access debug + capability. It exposes L2 indirect access + debugfs interface to get/set data, address, + and target cpus. + +config MSM_RPM_SMD + bool "RPM driver using SMD protocol" + help + RPM is the dedicated hardware engine for managing shared SoC + resources. This config adds driver support for using SMD as a + transport layer communication with RPM hardware. It also selects + the MSM_MPM config that programs the MPM module to monitor interrupts + during sleep modes. + +config QCOM_BUS_SCALING + bool "Bus scaling driver" + help + This option enables bus scaling on MSM devices. Bus scaling + allows devices to request the clocks be set to rates sufficient + for the active devices needs without keeping the clocks at max + frequency when a slower speed is sufficient. + config QCOM_GSBI tristate "QCOM General Serial Bus Interface" depends on ARCH_QCOM @@ -28,6 +245,100 @@ The driver provides an interface to items in a heap shared among all processors in a Qualcomm platform. +config MSM_SERVICE_LOCATOR + bool "Service Locator" + depends on MSM_QMI_INTERFACE + help + The Service Locator provides a library to retrieve location + information given a service identifier. Location here translates + to what process domain exports the service, and which subsystem + that process domain will execute in. + +config MSM_HVC + bool "MSM Hypervisor Call Support" + help + This enables the Hypervisor Call module. It provides apis to call + into the hypervisor thereby allowing access to services exposed by + the hypervisor. It is primarily intended to be used for Silicon + Partner/Manufacturer function identifier subrange but supports other + service call subranges as well. + +config QCOM_DCC + bool "QCOM Data Capture and Compare enigne support" + help + This option enables driver for Data Capture and Compare engine. DCC + driver provides interface to configure DCC block and read back + captured data from DCC's internal SRAM. + +config MSM_IPC_ROUTER_SMD_XPRT + depends on MSM_SMD + depends on IPC_ROUTER + bool "MSM SMD XPRT Layer" + help + SMD Transport Layer that enables IPC Router communication within + a System-on-Chip(SoC). When the SMD channels become available, + this layer registers a transport with IPC Router and enable + message exchange. + +config MSM_SYSMON_GLINK_COMM + bool "MSM System Monitor communication support using GLINK transport" + depends on MSM_GLINK && MSM_SUBSYSTEM_RESTART + help + This option adds support for MSM System Monitor APIs using the GLINK + transport layer. The APIs provided may be used for notifying + subsystems within the SoC about other subsystems' power-up/down + state-changes. + +config MSM_IPC_ROUTER_HSIC_XPRT + depends on USB_QCOM_IPC_BRIDGE + depends on IPC_ROUTER + bool "MSM HSIC XPRT Layer" + help + HSIC Transport Layer that enables off-chip communication of + IPC Router. When the HSIC endpoint becomes available, this layer + registers the transport with IPC Router and enable message + exchange. + +config MSM_IPC_ROUTER_MHI_XPRT + depends on MSM_MHI + depends on IPC_ROUTER + bool "MSM MHI XPRT Layer" + help + MHI Transport Layer that enables off-chip communication of + IPC Router. When the MHI endpoint becomes available, this layer + registers the transport with IPC Router and enable message + exchange. + +config MSM_IPC_ROUTER_GLINK_XPRT + depends on MSM_GLINK + depends on IPC_ROUTER + bool "MSM GLINK XPRT Layer" + help + GLINK Transport Layer that enables IPC Router communication within + a System-on-Chip(SoC). When the GLINK channels become available, + this layer registers a transport with IPC Router and enable + message exchange. + +config MSM_SYSTEM_HEALTH_MONITOR + bool "System Health Monitor" + depends on MSM_QMI_INTERFACE && MSM_SUBSYSTEM_RESTART + help + System Health Monitor (SHM) passively monitors the health of the + peripherals connected to the application processor. Software + components in the application processor that experience + communication failure can request the SHM to perform a system-wide + health check. If any failures are detected during the health-check, + then a subsystem restart will be triggered for the failed subsystem. + +config MSM_GLINK_PKT + bool "Enable device interface for GLINK packet channels" + depends on MSM_GLINK + help + G-link packet driver provides the interface for the userspace + clients to communicate over G-Link via deivce nodes. + This enable the usersapce clients to read and write to + some glink packets channel. + config QCOM_SMD tristate "Qualcomm Shared Memory Driver (SMD)" depends on QCOM_SMEM @@ -49,3 +360,611 @@ Say M here if you want to include support for the Qualcomm RPM as a module. This will build a module called "qcom-smd-rpm". + +config MSM_SPM + bool "Driver support for SPM and AVS wrapper hardware" + help + Enables the support SAW and AVS wrapper hardware on MSMs SPM + hardware is used to manage the processor power during sleep. The + driver allows configuring SPM to allow different low power modes for + both core and L2. + +config MSM_L2_SPM + bool "SPM support for L2 cache" + help + Enable SPM driver support for L2 cache. Some MSM chipsets allow + control of L2 cache low power mode with a Subsystem Power manager. + Enabling this driver allows configuring L2 SPM for low power modes + on supported chipsets + +config QCOM_SCM + bool "Secure Channel Manager (SCM) support" + default n + +config QCOM_SCM_QCPE + bool "Para-Virtualized Secure Channel Manager (SCM) support over QCPE" + default n + +menuconfig QCOM_SCM_XPU + bool "Qualcomm XPU configuration driver" + depends on QCOM_SCM + +if QCOM_SCM_XPU + +choice + prompt "XPU Violation Behavior" + default QCOM_XPU_ERR_FATAL + +config QCOM_XPU_ERR_FATAL + bool "Configure XPU violations as fatal errors" + help + Select if XPU violations have to be configured as fatal errors. + +config QCOM_XPU_ERR_NONFATAL + bool "Configure XPU violations as non-fatal errors" + help + Select if XPU violations have to be configured as non-fatal errors. + +endchoice + +endif + +config QCOM_SCM_ERRATA + depends on DEBUG_FS + depends on QCOM_SCM + bool "Support for enabling/disabling errata workarounds via debugfs" + help + Exposes a debugfs interface intended for advanced system debugging + where it may be desirable to enable or disable certain hardware + errata workarounds at runtime. + + If unsure, say N. + +if ARCH_QCOM + +config QCOM_WATCHDOG_V2 + bool "Qualcomm Watchdog Support" + help + This enables the watchdog module. It causes kernel panic if the + watchdog times out. It allows for detection of cpu hangs and + deadlocks. It does not run during the bootup process, so it will + not catch any early lockups. + +config QCOM_IRQ_HELPER + bool "QCOM Irq Helper" + help + This enables the irq helper module. It exposes two APIs + int irq_blacklist_on(void) and int irq_blacklist_off(void) + to other kernel module. + These two apis will be used to control the black list used + by the irq balancer. + +config QCOM_MEMORY_DUMP + bool "Qualcomm Memory Dump Support" + help + This enables memory dump feature. It allows various client + subsystems to register respective dump regions. At the time + of deadlocks or cpu hangs these dump regions are captured to + give a snapshot of the system at the time of the crash. + +config QCOM_MEMORY_DUMP_V2 + bool "QCOM Memory Dump V2 Support" + help + This enables memory dump feature. It allows various client + subsystems to register respective dump regions. At the time + of deadlocks or cpu hangs these dump regions are captured to + give a snapshot of the system at the time of the crash. + +config QCOM_MINIDUMP + bool "QCOM Minidump Support" + depends on MSM_SMEM && QCOM_DLOAD_MODE + help + This enables minidump feature. It allows various clients to + register to dump their state at system bad state (panic/WDT,etc.,). + This uses SMEM to store all registered client information. + This will dump all registered entries, only when DLOAD mode is enabled. + +config MINIDUMP_MAX_ENTRIES + int "Minidump Maximum num of entries" + default 200 + depends on QCOM_MINIDUMP + help + This defines maximum number of entries to be allocated for application + subsytem in Minidump SMEM table. + +config ICNSS + tristate "Platform driver for Q6 integrated connectivity" + select CNSS_UTILS + ---help--- + This module adds support for Q6 integrated WLAN connectivity + subsystem. This module is responsible for communicating WLAN on/off + control messages to FW over QMI channel. It is also responsible for + handling WLAN PD restart notifications. + +config ICNSS_DEBUG + bool "ICNSS debug support" + depends on ICNSS + ---help--- + Say 'Y' here to enable ICNSS driver debug support. Debug support + primarily consists of logs consisting of information related to + hardware register access and enabling BUG_ON for certain cases to aid + the debugging. + +config MSM_SECURE_BUFFER + bool "Helper functions for securing buffers through TZ" + help + Say 'Y' here for targets that need to call into TZ to secure + memory buffers. This ensures that only the correct clients can + use this memory and no unauthorized access is made to the + buffer + +config MSM_TZ_SMMU + bool "Helper functions for SMMU configuration through TZ" + depends on ARCH_MSMTHULIUM + help + Say 'Y' here for targets that need to call into TZ to configure + SMMUs for any reason (for example, for errata workarounds or + configuration of SMMU virtualization). + + If unsure, say N. + +config MSM_GLADIATOR_ERP + tristate "GLADIATOR coherency interconnect error reporting driver" + help + Support dumping debug information for the GLADIATOR + cache interconnect in the error interrupt handler. + Meant to be used for debug scenarios only. + + If unsure, say N. + +config MSM_GLADIATOR_ERP_V2 + tristate "GLADIATOR coherency interconnect error reporting driver v2" + help + Support dumping debug information for the GLADIATOR + cache interconnect in the error interrupt handler. + Meant to be used for debug scenarios only. + + If unsure, say N. + +config PANIC_ON_GLADIATOR_ERROR_V2 + depends on MSM_GLADIATOR_ERP_V2 + bool "Panic on GLADIATOR error report v2" + help + Panic upon detection of an Gladiator coherency interconnect error + in order to support dumping debug information. + Meant to be used for debug scenarios only. + + If unsure, say N. + +config MSM_GLADIATOR_ERROR_V2_MAIN_LOGGER_ONLY + depends on MSM_GLADIATOR_ERP_V2 + bool "QCOM Gladiator error v2 main logger support only" + help + Gladiator has two error loggers to report error captured. + By default, two error loggers will both be enabled. + This option enables only the main error logger. + If unsure, say no + +config MSM_GLADIATOR_HANG_DETECT + tristate "MSM Gladiator Hang Detection Support" + help + This enables the gladiator hang detection module. + If the configured threshold is reached, it causes SoC reset on + gladiator hang detection and collects the context for the + gladiator hang. + +config MSM_CORE_HANG_DETECT + tristate "MSM Core Hang Detection Support" + help + This enables the core hang detection module. It causes SoC + reset on core hang detection and collects the core context + for hang. + +config MSM_RUN_QUEUE_STATS + bool "Enable collection and exporting of MSM Run Queue stats to userspace" + help + This option enables the driver to periodically collecting the statistics + of kernel run queue information and calculate the load of the system. + This information is exported to usespace via sysfs entries and userspace + algorithms uses info and decide when to turn on/off the cpu cores. + +config MSM_JTAGV8 + bool "Debug and ETM trace support across power collapse for ARMv8" + default y if CORESIGHT_SOURCE_ETM4X + help + Enables support for debugging (specifically breakpoints) and ETM + processor tracing across power collapse both for JTag and OS hosted + software running on ARMv8 target. Enabling this will ensure debug + and ETM registers are saved and restored across power collapse. + + If unsure, say 'N' here to avoid potential power, performance and + memory penalty. + +config MSM_BOOT_STATS + bool "Use MSM boot stats reporting" + help + Use this to report msm boot stats such as bootloader throughput, + display init, total boot time. + This figures are reported in mpm sleep clock cycles and have a + resolution of 31 bits as 1 bit is used as an overflow check. + +config MSM_BOOT_TIME_MARKER + bool "Use MSM boot time marker reporting" + depends on MSM_BOOT_STATS + help + Use this to mark msm boot kpi for measurement. + An instrumentation for boot time measurement. + To create an entry, call "place_marker" function. + At userspace, write marker name to "/sys/kernel/debug/bootkpi/kpi_values" + If unsure, say N + +config QCOM_CPUSS_DUMP + bool "CPU Subsystem Dumping support" + help + Add support to dump various hardware entities such as the instruction + and data tlb's as well as the unified tlb, which are a part of the + cpu subsystem to an allocated buffer. This allows for analysis of the + the entities if corruption is suspected. + If unsure, say N + +config MSM_QDSP6_APRV2 + bool "Audio QDSP6 APRv2 support" + depends on MSM_SMD + help + Enable APRv2 IPC protocol support between + application processor and QDSP6. APR is + used by audio driver to configure QDSP6's + ASM, ADM and AFE. + +config MSM_QDSP6_APRV2_VM + bool "Audio QDSP6 APRv2 virtualization support" + depends on MSM_HAB + help + Enable APRv2 IPC protocol support over + HAB between application processor and + QDSP6. APR is used by audio driver to + configure QDSP6's ASM, ADM and AFE. + +config MSM_QDSP6_APRV3 + bool "Audio QDSP6 APRv3 support" + depends on MSM_SMD + help + Enable APRv3 IPC protocol support between + application processor and QDSP6. APR is + used by audio driver to configure QDSP6v2's + ASM, ADM and AFE. + +config MSM_QDSP6_APRV2_GLINK + bool "Audio QDSP6 APRv2 over Glink support" + depends on MSM_GLINK + help + Enable APRv2 IPC protocol support over + Glink between application processor and + QDSP6. APR is used by audio driver to + configure QDSP6's ASM, ADM and AFE. + +config MSM_QDSP6_APRV3_GLINK + bool "Audio QDSP6 APRv3 over Glink support" + depends on MSM_GLINK + help + Enable APRv3 IPC protocol support over + Glink between application processor and + QDSP6. APR is used by audio driver to + configure QDSP6v2's ASM, ADM and AFE. + +config MSM_QDSP6_SSR + bool "Audio QDSP6 SSR support" + depends on MSM_QDSP6_APRV2 || MSM_QDSP6_APRV3 || \ + MSM_QDSP6_APRV2_GLINK || MSM_QDSP6_APRV3_GLINK + help + Enable Subsystem Restart. Reset audio + clients when the ADSP subsystem is + restarted. Subsystem Restart for audio + is only used for processes on the ADSP + and signals audio drivers through APR. + + +config MSM_QDSP6_PDR + bool "Audio QDSP6 PDR support" + depends on MSM_QDSP6_APRV2 || MSM_QDSP6_APRV3 || \ + MSM_QDSP6_APRV2_GLINK || MSM_QDSP6_APRV3_GLINK + help + Enable Protection Domain Restart. Reset + audio clients when a process on the ADSP + is restarted. PDR for audio is only used + for processes on the ADSP and signals + audio drivers through APR. + +config MSM_QDSP6_NOTIFIER + bool "Audio QDSP6 PDR support" + depends on MSM_QDSP6_SSR || MSM_QDSP6_PDR + help + Enable notifier which decides whether + to use SSR or PDR and notifies all + audio clients of the event. Both SSR + and PDR are recovery methods when + there is a crash on ADSP. Audio drivers + are contacted by ADSP through APR. + +config MSM_ADSP_LOADER + tristate "ADSP loader support" + select SND_SOC_MSM_APRV2_INTF + depends on MSM_QDSP6_APRV2 || MSM_QDSP6_APRV3 || \ + MSM_QDSP6_APRV2_GLINK || MSM_QDSP6_APRV3_GLINK + help + Enable ADSP image loader. + The ADSP loader brings ADSP out of reset + for the platforms that use APRv2. + Say M if you want to enable this module. + +config MSM_CDSP_LOADER + tristate "CDSP loader support" + help + Enable CDSP image loader. + The CDSP loader brings CDSP out of reset + during boot. + Say M if you want to enable this module. + +config MSM_PERFORMANCE + tristate "msm_performance driver to support perflock request" + help + This driver is used to set minfreq/maxfreq for CPUs from userspace via + perflock. It also add CPU hotplug support to userspace. It ensures + that no more than a user specified number of CPUs stay online at any + given point in time. It also provides CPU/IO intensive workload + detection for userspace. + +config MSM_PERFORMANCE_HOTPLUG_ON + bool "Hotplug functionality through msm_performance turned on" + depends on MSM_PERFORMANCE + help + Setting this flag to true will enable the nodes needed for core-control + functionality of hot plugging cores through msm_performance if there is + no default core-control driver available. + +endif # ARCH_QCOM + +config MSM_SUBSYSTEM_RESTART + bool "MSM Subsystem Restart" + help + This option enables the MSM subsystem restart framework. + + The MSM subsystem restart framework provides support to boot, + shutdown, and restart subsystems with a reference counted API. + It also notifies userspace of transitions between these states via + sysfs. + +config MSM_SYSMON_COMM + bool "MSM System Monitor communication support" + depends on MSM_SMD && MSM_SUBSYSTEM_RESTART + help + This option adds support for MSM System Monitor library, which + provides an API that may be used for notifying subsystems within + the SoC about other subsystems' power-up/down state-changes. + +config MSM_PIL + bool "Peripheral image loading" + select FW_LOADER + default n + help + Some peripherals need to be loaded into memory before they can be + brought out of reset. + + Say yes to support these devices. + +config MSM_PIL_SSR_GENERIC + tristate "MSM Subsystem Boot Support" + depends on MSM_PIL && MSM_SUBSYSTEM_RESTART + help + Support for booting and shutting down MSM Subsystem processors. + This driver also monitors the SMSM status bits and the watchdog + interrupt for the subsystem and restarts it on a watchdog bite + or a fatal error. Subsystems include LPASS, Venus, VPU, WCNSS and + BCSS. + +config MSM_PIL_MSS_QDSP6V5 + tristate "MSS QDSP6v5 (Hexagon) Boot Support" + depends on MSM_PIL && MSM_SUBSYSTEM_RESTART + help + Support for booting and shutting down QDSP6v5 (Hexagon) processors + in modem subsystems. If you would like to make or receive phone + calls then say Y here. + + If unsure, say N. + +config TRACER_PKT + bool "Tracer Packet" + help + Tracer Packet helps in profiling the performance of inter- + processor communication protocols. The profiling information + can be logged into the tracer packet itself. + +config QCOM_FORCE_WDOG_BITE_ON_PANIC + bool "QCOM force watchdog bite" + depends on QCOM_WATCHDOG_V2 + help + This forces a watchdog bite when the device restarts due to a + kernel panic. On certain MSM SoCs, this provides us + additional debugging information. + +config MSM_MPM_OF + bool "Modem Power Manager" + depends on OF + help + MPM is a dedicated hardware resource responsible for entering and + waking up from a system wide low power mode. The MPM driver tracks + the wakeup interrupts and configures the MPM to monitor the wakeup + interrupts when going to a system wide sleep mode. This config option + enables the MPM driver that supports initialization from a device + tree + + +config MSM_EVENT_TIMER + bool "Event timer" + help + This option enables a modules that manages a list of event timers that + need to be monitored by the PM. The enables the PM code to monitor + events that require the core to be awake and ready to handle the + event. + +config MSM_AVTIMER + tristate "Avtimer Driver" + depends on MSM_QDSP6_APRV2 || MSM_QDSP6_APRV3 || MSM_QDSP6_APRV2_GLINK || \ + MSM_QDSP6_APRV2_VM + help + This driver gets the Q6 out of power collapsed state and + exposes ioctl control to read avtimer tick. + +config MSM_KERNEL_PROTECT + bool "Protect kernel text by removing write permissions in stage-2" + depends on !FUNCTION_TRACER + help + On hypervisor-enabled targets, this option will make a call into + the hypervisor to request that the kernel text be remapped + without write permissions. This protects against malicious + devices rewriting kernel code. + + Note that this will BREAK any runtime patching of the kernel text + (i.e. anything that uses apply_alternatives, + aarch64_insn_patch_text_nosync, etc. including the various CPU + errata workarounds in arch/arm64/kernel/cpu_errata.c). + +config MSM_KERNEL_PROTECT_TEST + bool "Bootup test of kernel protection (INTENTIONAL CRASH)" + depends on MSM_KERNEL_PROTECT + help + Attempts to write to the kernel text after making the kernel text + read-only. This test is FATAL whether it passes or fails! + Success is signaled by a stage-2 fault. + +config QCOM_REMOTEQDSS + bool "Allow debug tools to enable events on other processors" + depends on QCOM_SCM && DEBUG_FS + help + Other onchip processors/execution environments may support debug + events. Provide a sysfs interface for debug tools to dynamically + enable/disable these events. Interface located in + /sys/class/remoteqdss. + +config MSM_SERVICE_NOTIFIER + bool "Service Notifier" + depends on MSM_SERVICE_LOCATOR && MSM_SUBSYSTEM_RESTART + help + The Service Notifier provides a library for a kernel client to + register for state change notifications regarding a remote service. + A remote service here refers to a process providing certain services + like audio, the identifier for which is provided by the service + locator. + +config MSM_QBT1000 + bool "QBT1000 Ultrasonic Fingerprint Sensor" + help + This driver provides services for configuring the fingerprint + sensor hardware and for communicating with the trusted app which + uses it. It enables clocks and provides commands for loading + trusted apps, unloading them and marshalling buffers to the + trusted fingerprint app. + +config MSM_RPM_RBCPR_STATS_V2_LOG + tristate "MSM Resource Power Manager RPBCPR Stat Driver" + depends on DEBUG_FS + help + This option enables v2 of the rpmrbcpr_stats driver which reads RPM + memory for statistics pertaining to RPM's RBCPR(Rapid Bridge Core + Power Reduction) driver. The drivers outputs the message via a + debugfs node. + +config MSM_RPM_LOG + tristate "MSM Resource Power Manager Log Driver" + depends on DEBUG_FS + depends on MSM_RPM_SMD + default n + help + This option enables a driver which can read from a circular buffer + of messages produced by the RPM. These messages provide diagnostic + information about RPM operation. The driver outputs the messages + via a debugfs node. + +config MSM_RPM_STATS_LOG + tristate "MSM Resource Power Manager Stat Driver" + depends on DEBUG_FS + depends on MSM_RPM_SMD + default n + help + This option enables a driver which reads RPM messages from a shared + memory location. These messages provide statistical information about + the low power modes that RPM enters. The drivers outputs the message + via a debugfs node. + +config QSEE_IPC_IRQ_BRIDGE + tristate "QSEE IPC Interrupt Bridge" + help + This module enables bridging an Inter-Processor Communication(IPC) + interrupt from a remote subsystem directed towards Qualcomm + Technologies, Inc. Secure Execution Environment(QSEE). + +config WCD_DSP_GLINK + tristate "WCD DSP GLINK Driver" + depends on MSM_GLINK + default y if SND_SOC_WCD934X=y + help + This option enables driver which provides communication interface + between MSM and WCD DSP over glink transport protocol. This driver + provides read and write interface via char device. + +config QCOM_SMCINVOKE + bool "Secure QSEE Support" + help + Enable SMCInvoke driver which supports capability based secure + communication between QSEE and HLOS. + +config QCOM_EARLY_RANDOM + bool "Initialize random pool very early" + help + The standard random pool may not initialize until late in the boot + process which means that any calls to get random numbers before then + may not be truly random. Select this option to make an early call + to get some random data to put in the pool. If unsure, say N. + +config QCOM_CX_IPEAK + bool "Common driver to handle Cx iPeak limitation" + help + Cx ipeak HW module is used to limit the current drawn by various subsystem + blocks on Cx power rail. Each client needs to set their + bit in tcsr register if it is going to cross its own threshold. If all + clients are going to cross their thresholds then Cx ipeak hw module will raise + an interrupt to cDSP block to throttle cDSP fmax. + +config MSM_CACHE_M4M_ERP64 + bool "Cache and M4M error report" + depends on ARCH_MSM8996 + help + Say 'Y' here to enable reporting of cache and M4M errors to the kernel + log. The kernel log contains collected error syndrome and address + registers. These register dumps can be used as useful information + to find out possible hardware problems. + +config MSM_CACHE_M4M_ERP64_PANIC_ON_CE + bool "Panic on correctable cache/M4M errors" + help + Say 'Y' here to cause kernel panic when correctable cache/M4M errors + are detected. Enabling this is useful when you want to dump memory + and system state close to the time when the error occured. + + If unsure, say N. + +config MSM_CACHE_M4M_ERP64_PANIC_ON_UE + bool "Panic on uncorrectable cache/M4M errors" + help + Say 'Y' here to cause kernel panic when uncorrectable cache/M4M errors + are detected. + +config QCOM_QDSS_BRIDGE + bool "Configure bridge driver for QTI/Qualcomm Technologies, Inc. MDM" + depends on MSM_MHI + help + The driver will help route diag traffic from modem side over the QDSS + sub-system to USB on APSS side. The driver acts as a bridge between the + MHI and USB interface. If unsure, say N. + +source "drivers/soc/qcom/memshare/Kconfig" diff -ruw linux-4.4.115/drivers/soc/qcom/Makefile linux-4.4.115-fbx/drivers/soc/qcom/Makefile --- linux-4.4.115/drivers/soc/qcom/Makefile 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/soc/qcom/Makefile 2019-10-29 09:26:24.805214550 +0100 @@ -1,5 +1,111 @@ +KASAN_SANITIZE_scm.o := n + +CFLAGS_scm.o :=$(call as-instr,.arch_extension sec,-DREQUIRES_SEC=1) +CFLAGS_tracer_pkt.o = -I$(src) + +ccflags-$(CONFIG_MSM_QBT1000) += -Idrivers/misc/ + +obj-$(CONFIG_MSM_INRUSH_CURRENT_MITIGATION) += inrush-current-mitigation.o +obj-$(CONFIG_MSM_SMEM) += msm_smem.o smem_debug.o +obj-$(CONFIG_MSM_SMD) += msm_smd.o smd_debug.o smd_private.o smd_init_dt.o smsm_debug.o +obj-$(CONFIG_MSM_GLINK) += glink.o glink_debugfs.o glink_ssr.o +obj-$(CONFIG_MSM_GLINK_LOOPBACK_SERVER) += glink_loopback_server.o +obj-$(CONFIG_MSM_GLINK_SMD_XPRT) += glink_smd_xprt.o +obj-$(CONFIG_MSM_GLINK_SMEM_NATIVE_XPRT)+= glink_smem_native_xprt.o +obj-$(CONFIG_MSM_GLINK_SPI_XPRT) += glink_spi_xprt.o +obj-$(CONFIG_MSM_SMEM_LOGGING) += smem_log.o +obj-$(CONFIG_MSM_SYSMON_GLINK_COMM) += sysmon-glink.o sysmon-qmi.o +obj-$(CONFIG_ARCH_MSM8996) += kryo-l2-accessors.o +obj-$(CONFIG_MSM_SMP2P) += smp2p.o smp2p_loopback.o smp2p_debug.o smp2p_sleepstate.o +obj-$(CONFIG_MSM_QMI_INTERFACE) += qmi_interface.o +obj-$(CONFIG_MSM_RPM_SMD) += rpm-smd.o +obj-$(CONFIG_MSM_HVC) += hvc.o +ifdef CONFIG_DEBUG_FS +obj-$(CONFIG_MSM_RPM_SMD) += rpm-smd-debug.o +endif +obj-$(CONFIG_MSM_IPC_ROUTER_SMD_XPRT) += ipc_router_smd_xprt.o +obj-$(CONFIG_MSM_IPC_ROUTER_HSIC_XPRT) += ipc_router_hsic_xprt.o +obj-$(CONFIG_MSM_IPC_ROUTER_MHI_XPRT) += ipc_router_mhi_xprt.o +obj-$(CONFIG_MSM_IPC_ROUTER_GLINK_XPRT) += ipc_router_glink_xprt.o +obj-$(CONFIG_MSM_SPCOM) += spcom.o +obj-$(CONFIG_MSM_SPSS_UTILS) += spss_utils.o +obj-y += qdsp6v2/ +obj-$(CONFIG_MSM_SYSTEM_HEALTH_MONITOR) += system_health_monitor_v01.o +obj-$(CONFIG_MSM_SYSTEM_HEALTH_MONITOR) += system_health_monitor.o +obj-$(CONFIG_MSM_GLINK_PKT) += msm_glink_pkt.o + +obj-$(CONFIG_MEM_SHARE_QMI_SERVICE) += memshare/ +obj-$(CONFIG_MSM_PIL_SSR_GENERIC) += subsys-pil-tz.o +obj-$(CONFIG_MSM_PIL_MSS_QDSP6V5) += pil-q6v5.o pil-msa.o pil-q6v5-mss.o +obj-$(CONFIG_MSM_PIL) += peripheral-loader.o +obj-$(CONFIG_MSM_PFE_WA) += pfe-wa.o +obj-$(CONFIG_ARCH_MSM8996) += msm_cpu_voltage.o + +obj-$(CONFIG_MSM_PERFORMANCE) += msm_performance.o + +ifdef CONFIG_MSM_SUBSYSTEM_RESTART + obj-y += subsystem_notif.o + obj-y += subsystem_restart.o + obj-y += ramdump.o +endif + +obj-$(CONFIG_QPNP_HAPTIC) += qpnp-haptic.o obj-$(CONFIG_QCOM_GSBI) += qcom_gsbi.o +obj-$(CONFIG_QCOM_CPUSS_DUMP) += cpuss_dump.o +obj-$(CONFIG_QPNP_PBS) += qpnp-pbs.o obj-$(CONFIG_QCOM_PM) += spm.o obj-$(CONFIG_QCOM_SMD) += smd.o obj-$(CONFIG_QCOM_SMD_RPM) += smd-rpm.o obj-$(CONFIG_QCOM_SMEM) += smem.o +obj-$(CONFIG_MSM_SPM) += msm-spm.o spm_devices.o +CFLAGS_scm.o :=$(call as-instr,.arch_extension sec,-DREQUIRES_SEC=1) + +obj-$(CONFIG_QCOM_SCM_ERRATA) += scm-errata.o +obj-$(CONFIG_QCOM_SCM) += scm.o scm-boot.o +obj-$(CONFIG_QCOM_SCM_QCPE) += scm_qcpe.o +obj-$(CONFIG_QCOM_SCM_XPU) += scm-xpu.o +obj-$(CONFIG_QCOM_WATCHDOG_V2) += watchdog_v2.o +obj-$(CONFIG_QCOM_MEMORY_DUMP) += memory_dump.o +obj-$(CONFIG_QCOM_MEMORY_DUMP_V2) += memory_dump_v2.o +obj-$(CONFIG_QCOM_MINIDUMP) += msm_minidump.o +obj-$(CONFIG_QCOM_DCC) += dcc.o +obj-$(CONFIG_QCOM_WATCHDOG_V2) += watchdog_v2.o +obj-$(CONFIG_QCOM_COMMON_LOG) += common_log.o +obj-$(CONFIG_QCOM_IRQ_HELPER) += irq-helper.o +obj-$(CONFIG_TRACER_PKT) += tracer_pkt.o +obj-$(CONFIG_ICNSS) += icnss.o wlan_firmware_service_v01.o icnss_utils.o +obj-$(CONFIG_SOC_BUS) += socinfo.o +obj-$(CONFIG_QCOM_BUS_SCALING) += msm_bus/ +obj-$(CONFIG_MSM_SERVICE_NOTIFIER) += service-notifier.o +obj-$(CONFIG_MSM_SECURE_BUFFER) += secure_buffer.o +obj-$(CONFIG_MSM_MPM_OF) += mpm-of.o +obj-$(CONFIG_MSM_EVENT_TIMER) += event_timer.o +obj-$(CONFIG_MSM_TZ_SMMU) += msm_tz_smmu.o +obj-$(CONFIG_MSM_GLADIATOR_ERP) += gladiator_erp.o +obj-$(CONFIG_MSM_GLADIATOR_ERP_V2) += gladiator_erp_v2.o +obj-$(CONFIG_MSM_CORE_HANG_DETECT) += core_hang_detect.o +obj-$(CONFIG_MSM_GLADIATOR_HANG_DETECT) += gladiator_hang_detect.o +obj-$(CONFIG_MSM_RUN_QUEUE_STATS) += msm_rq_stats.o +obj-$(CONFIG_MSM_BOOT_STATS) += boot_stats.o +obj-$(CONFIG_MSM_BOOT_TIME_MARKER) += boot_marker.o +obj-$(CONFIG_MSM_AVTIMER) += avtimer.o +ifdef CONFIG_ARCH_MSM8996 +obj-$(CONFIG_HW_PERF_EVENTS) += perf_event_kryo.o +endif +obj-$(CONFIG_MSM_JTAGV8) += jtag-fuse.o jtagv8.o jtagv8-etm.o +obj-$(CONFIG_MSM_KERNEL_PROTECT) += kernel_protect.o +obj-$(CONFIG_MSM_RTB) += msm_rtb-hotplug.o +obj-$(CONFIG_QCOM_REMOTEQDSS) += remoteqdss.o +obj-$(CONFIG_MSM_SERVICE_LOCATOR) += service-locator.o +obj-$(CONFIG_MSM_QBT1000) += qbt1000.o +obj-$(CONFIG_MSM_RPM_RBCPR_STATS_V2_LOG) += rpm_rbcpr_stats_v2.o +obj-$(CONFIG_MSM_RPM_STATS_LOG) += rpm_stats.o rpm_master_stat.o rpm_rail_stats.o system_stats.o +obj-$(CONFIG_MSM_RPM_LOG) += rpm_log.o +obj-$(CONFIG_QSEE_IPC_IRQ_BRIDGE) += qsee_ipc_irq_bridge.o +obj-$(CONFIG_WCD_DSP_GLINK) += wcd-dsp-glink.o +obj-$(CONFIG_QCOM_SMCINVOKE) += smcinvoke.o +obj-$(CONFIG_QCOM_EARLY_RANDOM) += early_random.o +obj-$(CONFIG_QCOM_CX_IPEAK) += cx_ipeak.o +obj-$(CONFIG_MSM_CACHE_M4M_ERP64) += cache_m4m_erp64.o +obj-$(CONFIG_MSM_HAB) += hab/ +obj-$(CONFIG_QCOM_QDSS_BRIDGE) += qdss_bridge.o diff -ruw linux-4.4.115/drivers/spi/Kconfig linux-4.4.115-fbx/drivers/spi/Kconfig --- linux-4.4.115/drivers/spi/Kconfig 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/spi/Kconfig 2019-01-22 16:16:26.687275240 +0100 @@ -704,6 +704,18 @@ endif # SPI_MASTER -# (slave support would go here) +# +# SLAVE side ... listening to other SPI masters +# + +config SPI_SLAVE + bool "SPI slave protocol handlers" + help + If your system has a slave-capable SPI controller, you can enable + slave protocol handlers. + +if SPI_SLAVE + +endif # SPI_SLAVE endif # SPI diff -ruw linux-4.4.115/drivers/spi/Makefile linux-4.4.115-fbx/drivers/spi/Makefile --- linux-4.4.115/drivers/spi/Makefile 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/spi/Makefile 2019-01-22 16:16:26.687275240 +0100 @@ -93,3 +93,7 @@ obj-$(CONFIG_SPI_XLP) += spi-xlp.o obj-$(CONFIG_SPI_XTENSA_XTFPGA) += spi-xtensa-xtfpga.o obj-$(CONFIG_SPI_ZYNQMP_GQSPI) += spi-zynqmp-gqspi.o +obj-$(CONFIG_SPI_QSD) += spi_qsd.o +obj-$(CONFIG_SPI_QUP) += spi_qsd.o + +# SPI slave protocol handlers diff -ruw linux-4.4.115/drivers/spi/spi.c linux-4.4.115-fbx/drivers/spi/spi.c --- linux-4.4.115/drivers/spi/spi.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/spi/spi.c 2019-10-29 09:26:24.841214902 +0100 @@ -1421,39 +1421,11 @@ /*-------------------------------------------------------------------------*/ #if defined(CONFIG_OF) -static struct spi_device * -of_register_spi_device(struct spi_master *master, struct device_node *nc) +static int of_spi_parse_dt(struct spi_master *master, struct spi_device *spi, + struct device_node *nc) { - struct spi_device *spi; - int rc; u32 value; - - /* Alloc an spi_device */ - spi = spi_alloc_device(master); - if (!spi) { - dev_err(&master->dev, "spi_device alloc error for %s\n", - nc->full_name); - rc = -ENOMEM; - goto err_out; - } - - /* Select device driver */ - rc = of_modalias_node(nc, spi->modalias, - sizeof(spi->modalias)); - if (rc < 0) { - dev_err(&master->dev, "cannot find modalias for %s\n", - nc->full_name); - goto err_out; - } - - /* Device address */ - rc = of_property_read_u32(nc, "reg", &value); - if (rc) { - dev_err(&master->dev, "%s has no valid 'reg' property (%d)\n", - nc->full_name, rc); - goto err_out; - } - spi->chip_select = value; + int rc; /* Mode (clock phase/polarity/etc.) */ if (of_find_property(nc, "spi-cpha", NULL)) @@ -1504,15 +1476,64 @@ } } + if (spi_controller_is_slave(master)) { + if (strcmp(nc->name, "slave")) { + dev_err(&master->dev, "%s is not called 'slave'\n", + nc->full_name); + return -EINVAL; + } + return 0; + } + + /* Device address */ + rc = of_property_read_u32(nc, "reg", &value); + if (rc) { + dev_err(&master->dev, "%s has no valid 'reg' property (%d)\n", + nc->full_name, rc); + return rc; + } + spi->chip_select = value; + /* Device speed */ rc = of_property_read_u32(nc, "spi-max-frequency", &value); if (rc) { dev_err(&master->dev, "%s has no valid 'spi-max-frequency' property (%d)\n", nc->full_name, rc); - goto err_out; + return rc; } spi->max_speed_hz = value; + return 0; +} + +static struct spi_device * +of_register_spi_device(struct spi_master *master, struct device_node *nc) +{ + struct spi_device *spi; + int rc; + + /* Alloc an spi_device */ + spi = spi_alloc_device(master); + if (!spi) { + dev_err(&master->dev, "spi_device alloc error for %s\n", + nc->full_name); + rc = -ENOMEM; + goto err_out; + } + + /* Select device driver */ + rc = of_modalias_node(nc, spi->modalias, + sizeof(spi->modalias)); + if (rc < 0) { + dev_err(&master->dev, "cannot find modalias for %s\n", + nc->full_name); + goto err_out; + } + + rc = of_spi_parse_dt(master, spi, nc); + if (rc) + goto err_out; + /* Store a pointer to the node in the device structure */ of_node_get(nc); spi->dev.of_node = nc; @@ -1536,8 +1557,8 @@ * of_register_spi_devices() - Register child devices onto the SPI bus * @master: Pointer to spi_master device * - * Registers an spi_device for each child node of master node which has a 'reg' - * property. + * Registers an spi_device for each child node of controller node which + * represents a valid SPI slave. */ static void of_register_spi_devices(struct spi_master *master) { @@ -1669,28 +1690,129 @@ .dev_groups = spi_master_groups, }; +#ifdef CONFIG_SPI_SLAVE +/** + * spi_slave_abort - abort the ongoing transfer request on an SPI slave + * controller + * @spi: device used for the current transfer + */ +int spi_slave_abort(struct spi_device *spi) +{ + struct spi_master *master = spi->master; + + if (spi_controller_is_slave(master) && master->slave_abort) + return master->slave_abort(master); + + return -ENOTSUPP; +} +EXPORT_SYMBOL_GPL(spi_slave_abort); + +static int match_true(struct device *dev, void *data) +{ + return 1; +} + +static ssize_t spi_slave_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct spi_master *ctlr = container_of(dev, struct spi_master, dev); + struct device *child; + + child = device_find_child(&ctlr->dev, NULL, match_true); + return sprintf(buf, "%s\n", + child ? to_spi_device(child)->modalias : NULL); +} + +static ssize_t spi_slave_store(struct device *dev, + struct device_attribute *attr, const char *buf, + size_t count) +{ + struct spi_master *ctlr = container_of(dev, struct spi_master, dev); + struct spi_device *spi; + struct device *child; + char name[32]; + int rc; + + rc = sscanf(buf, "%31s", name); + if (rc != 1 || !name[0]) + return -EINVAL; + + child = device_find_child(&ctlr->dev, NULL, match_true); + if (child) { + /* Remove registered slave */ + device_unregister(child); + put_device(child); + } + + if (strcmp(name, "(null)")) { + /* Register new slave */ + spi = spi_alloc_device(ctlr); + if (!spi) + return -ENOMEM; + + strlcpy(spi->modalias, name, sizeof(spi->modalias)); + + rc = spi_add_device(spi); + if (rc) { + spi_dev_put(spi); + return rc; + } + } + + return count; +} + +static DEVICE_ATTR(slave, 0644, spi_slave_show, spi_slave_store); + +static struct attribute *spi_slave_attrs[] = { + &dev_attr_slave.attr, + NULL, +}; + +static const struct attribute_group spi_slave_group = { + .attrs = spi_slave_attrs, +}; + +static const struct attribute_group *spi_slave_groups[] = { + &spi_master_statistics_group, + &spi_slave_group, + NULL, +}; + +static struct class spi_slave_class = { + .name = "spi_slave", + .owner = THIS_MODULE, + .dev_release = spi_master_release, + .dev_groups = spi_slave_groups, +}; +#else +extern struct class spi_slave_class; /* dummy */ +#endif /** - * spi_alloc_master - allocate SPI master controller + * __spi_alloc_controller - allocate an SPI master or slave controller * @dev: the controller, possibly using the platform_bus * @size: how much zeroed driver-private data to allocate; the pointer to this * memory is in the driver_data field of the returned device, * accessible with spi_master_get_devdata(). + * @slave: flag indicating whether to allocate an SPI master (false) or SPI + * slave (true) controller * Context: can sleep * - * This call is used only by SPI master controller drivers, which are the + * This call is used only by SPI controller drivers, which are the * only ones directly touching chip registers. It's how they allocate * an spi_master structure, prior to calling spi_register_master(). * * This must be called from context that can sleep. * - * The caller is responsible for assigning the bus number and initializing - * the master's methods before calling spi_register_master(); and (after errors + * The caller is responsible for assigning the bus number and initializing the + * controller's methods before calling spi_register_master(); and (after errors * adding the device) calling spi_master_put() to prevent a memory leak. * - * Return: the SPI master structure on success, else NULL. + * Return: the SPI controller structure on success, else NULL. */ -struct spi_master *spi_alloc_master(struct device *dev, unsigned size) +struct spi_master *__spi_alloc_controller(struct device *dev, + unsigned int size, bool slave) { struct spi_master *master; @@ -1704,13 +1826,17 @@ device_initialize(&master->dev); master->bus_num = -1; master->num_chipselect = 1; + master->slave = slave; + if (IS_ENABLED(CONFIG_SPI_SLAVE) && slave) + master->dev.class = &spi_slave_class; + else master->dev.class = &spi_master_class; master->dev.parent = dev; spi_master_set_devdata(master, &master[1]); return master; } -EXPORT_SYMBOL_GPL(spi_alloc_master); +EXPORT_SYMBOL_GPL(__spi_alloc_controller); #ifdef CONFIG_OF static int of_spi_register_master(struct spi_master *master) @@ -1786,9 +1912,11 @@ if (!dev) return -ENODEV; + if (!spi_controller_is_slave(master)) { status = of_spi_register_master(master); if (status) return status; + } /* even if it's just one always-selected device, there must * be at least one chipselect @@ -1824,8 +1952,9 @@ status = device_add(&master->dev); if (status < 0) goto done; - dev_dbg(dev, "registered master %s%s\n", dev_name(&master->dev), - dynamic ? " (dynamic)" : ""); + dev_dbg(dev, "registered %s %s%s\n", + spi_controller_is_slave(master) ? "slave" : "master", + dev_name(&master->dev), dynamic ? " (dynamic)" : ""); /* If we're using a queued driver, start the queue */ if (master->transfer) @@ -2613,6 +2742,9 @@ dev = class_find_device(&spi_master_class, NULL, node, __spi_of_master_match); + if (!dev && IS_ENABLED(CONFIG_SPI_SLAVE)) + dev = class_find_device(&spi_slave_class, NULL, node, + __spi_of_master_match); if (!dev) return NULL; @@ -2685,11 +2817,19 @@ if (status < 0) goto err2; + if (IS_ENABLED(CONFIG_SPI_SLAVE)) { + status = class_register(&spi_slave_class); + if (status < 0) + goto err3; + } + if (IS_ENABLED(CONFIG_OF_DYNAMIC)) WARN_ON(of_reconfig_notifier_register(&spi_of_notifier)); return 0; +err3: + class_unregister(&spi_master_class); err2: bus_unregister(&spi_bus_type); err1: diff -ruw linux-4.4.115/drivers/spi/spidev.c linux-4.4.115-fbx/drivers/spi/spidev.c --- linux-4.4.115/drivers/spi/spidev.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/spi/spidev.c 2019-01-22 16:16:26.707275421 +0100 @@ -695,6 +695,9 @@ static const struct of_device_id spidev_dt_ids[] = { { .compatible = "rohm,dh2228fv" }, { .compatible = "lineartechnology,ltc2488" }, + { .compatible = "qcom,spi-msm-codec-slave", }, + { .compatible = "nxp,mpc57xx", }, + { .compatible = "infineon,sli97", }, {}, }; MODULE_DEVICE_TABLE(of, spidev_dt_ids); @@ -715,8 +718,10 @@ */ if (spi->dev.of_node && !of_match_device(spidev_dt_ids, &spi->dev)) { dev_err(&spi->dev, "buggy DT: spidev listed directly in DT\n"); +#if 0 WARN_ON(spi->dev.of_node && !of_match_device(spidev_dt_ids, &spi->dev)); +#endif } /* Allocate driver data */ diff -ruw linux-4.4.115/drivers/spmi/spmi.c linux-4.4.115-fbx/drivers/spmi/spmi.c --- linux-4.4.115/drivers/spmi/spmi.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/spmi/spmi.c 2019-01-22 16:16:26.707275421 +0100 @@ -69,7 +69,7 @@ struct spmi_controller *ctrl = sdev->ctrl; int err; - dev_set_name(&sdev->dev, "%d-%02x", ctrl->nr, sdev->usid); + dev_set_name(&sdev->dev, "spmi%d-%02x", ctrl->nr, sdev->usid); err = device_add(&sdev->dev); if (err < 0) { diff -ruw linux-4.4.115/drivers/spmi/spmi-pmic-arb.c linux-4.4.115-fbx/drivers/spmi/spmi-pmic-arb.c --- linux-4.4.115/drivers/spmi/spmi-pmic-arb.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/spmi/spmi-pmic-arb.c 2019-10-29 09:26:24.841214902 +0100 @@ -1,5 +1,5 @@ /* - * Copyright (c) 2012-2015, The Linux Foundation. All rights reserved. + * Copyright (c) 2012-2017, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -10,6 +10,7 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ +#include #include #include #include @@ -23,10 +24,13 @@ #include #include #include +#include /* PMIC Arbiter configuration registers */ #define PMIC_ARB_VERSION 0x0000 #define PMIC_ARB_VERSION_V2_MIN 0x20010000 +#define PMIC_ARB_VERSION_V3_MIN 0x30000000 +#define PMIC_ARB_VERSION_V5_MIN 0x50000000 #define PMIC_ARB_INT_EN 0x0004 /* PMIC Arbiter channel registers offsets */ @@ -37,7 +41,6 @@ #define PMIC_ARB_WDATA1 0x14 #define PMIC_ARB_RDATA0 0x18 #define PMIC_ARB_RDATA1 0x1C -#define PMIC_ARB_REG_CHNL(N) (0x800 + 0x4 * (N)) /* Mapping Table */ #define SPMI_MAPPING_TABLE_REG(N) (0x0B00 + (4 * (N))) @@ -47,9 +50,11 @@ #define SPMI_MAPPING_BIT_IS_1_FLAG(X) (((X) >> 8) & 0x1) #define SPMI_MAPPING_BIT_IS_1_RESULT(X) (((X) >> 0) & 0xFF) -#define SPMI_MAPPING_TABLE_LEN 255 #define SPMI_MAPPING_TABLE_TREE_DEPTH 16 /* Maximum of 16-bits */ -#define PPID_TO_CHAN_TABLE_SZ BIT(12) /* PPID is 12bit chan is 1byte*/ +#define PMIC_ARB_MAX_PPID BIT(12) /* PPID is 12bit */ +#define PMIC_ARB_CHAN_VALID BIT(15) +#define PMIC_ARB_CHAN_IS_IRQ_OWNER(reg) ((reg) & BIT(24)) +#define INVALID_EE (-1) /* Ownership Table */ #define SPMI_OWNERSHIP_TABLE_REG(N) (0x0700 + (4 * (N))) @@ -57,10 +62,10 @@ /* Channel Status fields */ enum pmic_arb_chnl_status { - PMIC_ARB_STATUS_DONE = (1 << 0), - PMIC_ARB_STATUS_FAILURE = (1 << 1), - PMIC_ARB_STATUS_DENIED = (1 << 2), - PMIC_ARB_STATUS_DROPPED = (1 << 3), + PMIC_ARB_STATUS_DONE = BIT(0), + PMIC_ARB_STATUS_FAILURE = BIT(1), + PMIC_ARB_STATUS_DENIED = BIT(2), + PMIC_ARB_STATUS_DROPPED = BIT(3), }; /* Command register fields */ @@ -84,10 +89,17 @@ PMIC_ARB_OP_ZERO_WRITE = 16, }; +/* + * PMIC arbiter version 5 uses different register offsets for read/write vs + * observer channels. + */ +enum pmic_arb_channel { + PMIC_ARB_CHANNEL_RW, + PMIC_ARB_CHANNEL_OBS, +}; + /* Maximum number of support PMIC peripherals */ -#define PMIC_ARB_MAX_PERIPHS 256 -#define PMIC_ARB_MAX_CHNL 128 -#define PMIC_ARB_PERIPH_ID_VALID (1 << 15) +#define PMIC_ARB_MAX_PERIPHS 512 #define PMIC_ARB_TIMEOUT_US 100 #define PMIC_ARB_MAX_TRANS_BYTES (8) @@ -97,14 +109,32 @@ /* interrupt enable bit */ #define SPMI_PIC_ACC_ENABLE_BIT BIT(0) +#define HWIRQ(slave_id, periph_id, irq_id, apid) \ + ((((slave_id) & 0xF) << 28) | \ + (((periph_id) & 0xFF) << 20) | \ + (((irq_id) & 0x7) << 16) | \ + (((apid) & 0x1FF) << 0)) + +#define HWIRQ_SID(hwirq) (((hwirq) >> 28) & 0xF) +#define HWIRQ_PER(hwirq) (((hwirq) >> 20) & 0xFF) +#define HWIRQ_IRQ(hwirq) (((hwirq) >> 16) & 0x7) +#define HWIRQ_APID(hwirq) (((hwirq) >> 0) & 0x1FF) + struct pmic_arb_ver_ops; +struct apid_data { + u16 ppid; + u8 write_owner; + u8 irq_owner; +}; + /** - * spmi_pmic_arb_dev - SPMI PMIC Arbiter object + * spmi_pmic_arb - SPMI PMIC Arbiter object * * @rd_base: on v1 "core", on v2 "observer" register base off DT. * @wr_base: on v1 "core", on v2 "chnls" register base off DT. * @intr: address of the SPMI interrupt control registers. + * @acc_status: address of SPMI ACC interrupt status registers. * @cnfg: address of the PMIC Arbiter configuration registers. * @lock: lock to synchronize accesses. * @channel: execution environment channel to use for accesses. @@ -112,36 +142,47 @@ * @ee: the current Execution Environment * @min_apid: minimum APID (used for bounding IRQ search) * @max_apid: maximum APID + * @max_periph: maximum number of PMIC peripherals supported by HW. * @mapping_table: in-memory copy of PPID -> APID mapping table. * @domain: irq domain object for PMIC IRQ domain * @spmic: SPMI controller object - * @apid_to_ppid: in-memory copy of APID -> PPID mapping table. * @ver_ops: version dependent operations. - * @ppid_to_chan in-memory copy of PPID -> channel (APID) mapping table. + * @ppid_to_apid in-memory copy of PPID -> channel (APID) mapping table. * v2 only. */ -struct spmi_pmic_arb_dev { +struct spmi_pmic_arb { void __iomem *rd_base; void __iomem *wr_base; void __iomem *intr; + void __iomem *acc_status; void __iomem *cnfg; + void __iomem *core; + resource_size_t core_size; raw_spinlock_t lock; u8 channel; int irq; u8 ee; - u8 min_apid; - u8 max_apid; - u32 mapping_table[SPMI_MAPPING_TABLE_LEN]; + u16 min_apid; + u16 max_apid; + u16 max_periph; + u32 *mapping_table; + int reserved_chan; + DECLARE_BITMAP(mapping_table_valid, PMIC_ARB_MAX_PERIPHS); struct irq_domain *domain; struct spmi_controller *spmic; - u16 apid_to_ppid[256]; const struct pmic_arb_ver_ops *ver_ops; - u8 *ppid_to_chan; + u16 *ppid_to_apid; + u16 last_apid; + struct apid_data apid_data[PMIC_ARB_MAX_PERIPHS]; }; +static struct spmi_pmic_arb *the_pa; /** * pmic_arb_ver: version dependent functionality. * + * @ver_str: version string. + * @ppid_to_apid: finds the apid for a given ppid. + * @mode: access rights to specified pmic peripheral. * @non_data_cmd: on v1 issues an spmi non-data command. * on v2 no HW support, returns -EOPNOTSUPP. * @offset: on v1 offset of per-ee channel. @@ -155,29 +196,37 @@ * on v2 offset of SPMI_PIC_IRQ_STATUSn. * @irq_clear: on v1 offset of PMIC_ARB_SPMI_PIC_IRQ_CLEARn * on v2 offset of SPMI_PIC_IRQ_CLEARn. + * @channel_map_offset: offset of PMIC_ARB_REG_CHNLn */ struct pmic_arb_ver_ops { + const char *ver_str; + int (*ppid_to_apid)(struct spmi_pmic_arb *pa, u8 sid, u16 addr, + u16 *apid); + int (*mode)(struct spmi_pmic_arb *dev, u8 sid, u16 addr, + mode_t *mode); /* spmi commands (read_cmd, write_cmd, cmd) functionality */ - u32 (*offset)(struct spmi_pmic_arb_dev *dev, u8 sid, u16 addr); + int (*offset)(struct spmi_pmic_arb *dev, u8 sid, u16 addr, + enum pmic_arb_channel ch_type, u32 *offset); u32 (*fmt_cmd)(u8 opc, u8 sid, u16 addr, u8 bc); int (*non_data_cmd)(struct spmi_controller *ctrl, u8 opc, u8 sid); /* Interrupts controller functionality (offset of PIC registers) */ - u32 (*owner_acc_status)(u8 m, u8 n); - u32 (*acc_enable)(u8 n); - u32 (*irq_status)(u8 n); - u32 (*irq_clear)(u8 n); + u32 (*owner_acc_status)(u8 m, u16 n); + u32 (*acc_enable)(u16 n); + u32 (*irq_status)(u16 n); + u32 (*irq_clear)(u16 n); + u32 (*channel_map_offset)(u16 n); }; -static inline void pmic_arb_base_write(struct spmi_pmic_arb_dev *dev, +static inline void pmic_arb_base_write(struct spmi_pmic_arb *pa, u32 offset, u32 val) { - writel_relaxed(val, dev->wr_base + offset); + writel_relaxed(val, pa->wr_base + offset); } -static inline void pmic_arb_set_rd_cmd(struct spmi_pmic_arb_dev *dev, +static inline void pmic_arb_set_rd_cmd(struct spmi_pmic_arb *pa, u32 offset, u32 val) { - writel_relaxed(val, dev->rd_base + offset); + writel_relaxed(val, pa->rd_base + offset); } /** @@ -186,9 +235,10 @@ * @reg: register's address * @buf: output parameter, length must be bc + 1 */ -static void pa_read_data(struct spmi_pmic_arb_dev *dev, u8 *buf, u32 reg, u8 bc) +static void pa_read_data(struct spmi_pmic_arb *pa, u8 *buf, u32 reg, u8 bc) { - u32 data = __raw_readl(dev->rd_base + reg); + u32 data = __raw_readl(pa->rd_base + reg); + memcpy(buf, &data, (bc & 3) + 1); } @@ -199,20 +249,29 @@ * @buf: buffer to write. length must be bc + 1. */ static void -pa_write_data(struct spmi_pmic_arb_dev *dev, const u8 *buf, u32 reg, u8 bc) +pa_write_data(struct spmi_pmic_arb *pa, const u8 *buf, u32 reg, u8 bc) { u32 data = 0; + memcpy(&data, buf, (bc & 3) + 1); - __raw_writel(data, dev->wr_base + reg); + pmic_arb_base_write(pa, reg, data); } static int pmic_arb_wait_for_done(struct spmi_controller *ctrl, - void __iomem *base, u8 sid, u16 addr) + void __iomem *base, u8 sid, u16 addr, + enum pmic_arb_channel ch_type) { - struct spmi_pmic_arb_dev *dev = spmi_controller_get_drvdata(ctrl); + struct spmi_pmic_arb *pa = spmi_controller_get_drvdata(ctrl); u32 status = 0; u32 timeout = PMIC_ARB_TIMEOUT_US; - u32 offset = dev->ver_ops->offset(dev, sid, addr) + PMIC_ARB_STATUS; + u32 offset; + int rc; + + rc = pa->ver_ops->offset(pa, sid, addr, ch_type, &offset); + if (rc) + return rc; + + offset += PMIC_ARB_STATUS; while (timeout--) { status = readl_relaxed(base + offset); @@ -253,18 +312,23 @@ static int pmic_arb_non_data_cmd_v1(struct spmi_controller *ctrl, u8 opc, u8 sid) { - struct spmi_pmic_arb_dev *pmic_arb = spmi_controller_get_drvdata(ctrl); + struct spmi_pmic_arb *pa = spmi_controller_get_drvdata(ctrl); unsigned long flags; u32 cmd; int rc; - u32 offset = pmic_arb->ver_ops->offset(pmic_arb, sid, 0); + u32 offset; + + rc = pa->ver_ops->offset(pa, sid, 0, PMIC_ARB_CHANNEL_RW, &offset); + if (rc) + return rc; cmd = ((opc | 0x40) << 27) | ((sid & 0xf) << 20); - raw_spin_lock_irqsave(&pmic_arb->lock, flags); - pmic_arb_base_write(pmic_arb, offset + PMIC_ARB_CMD, cmd); - rc = pmic_arb_wait_for_done(ctrl, pmic_arb->wr_base, sid, 0); - raw_spin_unlock_irqrestore(&pmic_arb->lock, flags); + raw_spin_lock_irqsave(&pa->lock, flags); + pmic_arb_base_write(pa, offset + PMIC_ARB_CMD, cmd); + rc = pmic_arb_wait_for_done(ctrl, pa->wr_base, sid, 0, + PMIC_ARB_CHANNEL_RW); + raw_spin_unlock_irqrestore(&pa->lock, flags); return rc; } @@ -278,7 +342,7 @@ /* Non-data command */ static int pmic_arb_cmd(struct spmi_controller *ctrl, u8 opc, u8 sid) { - struct spmi_pmic_arb_dev *pmic_arb = spmi_controller_get_drvdata(ctrl); + struct spmi_pmic_arb *pa = spmi_controller_get_drvdata(ctrl); dev_dbg(&ctrl->dev, "cmd op:0x%x sid:%d\n", opc, sid); @@ -286,18 +350,34 @@ if (opc < SPMI_CMD_RESET || opc > SPMI_CMD_WAKEUP) return -EINVAL; - return pmic_arb->ver_ops->non_data_cmd(ctrl, opc, sid); + return pa->ver_ops->non_data_cmd(ctrl, opc, sid); } static int pmic_arb_read_cmd(struct spmi_controller *ctrl, u8 opc, u8 sid, u16 addr, u8 *buf, size_t len) { - struct spmi_pmic_arb_dev *pmic_arb = spmi_controller_get_drvdata(ctrl); + struct spmi_pmic_arb *pa = spmi_controller_get_drvdata(ctrl); unsigned long flags; u8 bc = len - 1; u32 cmd; int rc; - u32 offset = pmic_arb->ver_ops->offset(pmic_arb, sid, addr); + u32 offset; + mode_t mode; + + rc = pa->ver_ops->offset(pa, sid, addr, PMIC_ARB_CHANNEL_OBS, &offset); + if (rc) + return rc; + + rc = pa->ver_ops->mode(pa, sid, addr, &mode); + if (rc) + return rc; + + if (!(mode & 0400)) { + dev_err(&pa->spmic->dev, + "error: impermissible read from peripheral sid:%d addr:0x%x\n", + sid, addr); + return -ENODEV; + } if (bc >= PMIC_ARB_MAX_TRANS_BYTES) { dev_err(&ctrl->dev, @@ -316,35 +396,51 @@ else return -EINVAL; - cmd = pmic_arb->ver_ops->fmt_cmd(opc, sid, addr, bc); + cmd = pa->ver_ops->fmt_cmd(opc, sid, addr, bc); - raw_spin_lock_irqsave(&pmic_arb->lock, flags); - pmic_arb_set_rd_cmd(pmic_arb, offset + PMIC_ARB_CMD, cmd); - rc = pmic_arb_wait_for_done(ctrl, pmic_arb->rd_base, sid, addr); + raw_spin_lock_irqsave(&pa->lock, flags); + pmic_arb_set_rd_cmd(pa, offset + PMIC_ARB_CMD, cmd); + rc = pmic_arb_wait_for_done(ctrl, pa->rd_base, sid, addr, + PMIC_ARB_CHANNEL_OBS); if (rc) goto done; - pa_read_data(pmic_arb, buf, offset + PMIC_ARB_RDATA0, + pa_read_data(pa, buf, offset + PMIC_ARB_RDATA0, min_t(u8, bc, 3)); if (bc > 3) - pa_read_data(pmic_arb, buf + 4, - offset + PMIC_ARB_RDATA1, bc - 4); + pa_read_data(pa, buf + 4, offset + PMIC_ARB_RDATA1, bc - 4); done: - raw_spin_unlock_irqrestore(&pmic_arb->lock, flags); + raw_spin_unlock_irqrestore(&pa->lock, flags); return rc; } static int pmic_arb_write_cmd(struct spmi_controller *ctrl, u8 opc, u8 sid, u16 addr, const u8 *buf, size_t len) { - struct spmi_pmic_arb_dev *pmic_arb = spmi_controller_get_drvdata(ctrl); + struct spmi_pmic_arb *pa = spmi_controller_get_drvdata(ctrl); unsigned long flags; u8 bc = len - 1; u32 cmd; int rc; - u32 offset = pmic_arb->ver_ops->offset(pmic_arb, sid, addr); + u32 offset; + mode_t mode; + + rc = pa->ver_ops->offset(pa, sid, addr, PMIC_ARB_CHANNEL_RW, &offset); + if (rc) + return rc; + + rc = pa->ver_ops->mode(pa, sid, addr, &mode); + if (rc) + return rc; + + if (!(mode & 0200)) { + dev_err(&pa->spmic->dev, + "error: impermissible write to peripheral sid:%d addr:0x%x\n", + sid, addr); + return -ENODEV; + } if (bc >= PMIC_ARB_MAX_TRANS_BYTES) { dev_err(&ctrl->dev, @@ -365,20 +461,19 @@ else return -EINVAL; - cmd = pmic_arb->ver_ops->fmt_cmd(opc, sid, addr, bc); + cmd = pa->ver_ops->fmt_cmd(opc, sid, addr, bc); /* Write data to FIFOs */ - raw_spin_lock_irqsave(&pmic_arb->lock, flags); - pa_write_data(pmic_arb, buf, offset + PMIC_ARB_WDATA0, - min_t(u8, bc, 3)); + raw_spin_lock_irqsave(&pa->lock, flags); + pa_write_data(pa, buf, offset + PMIC_ARB_WDATA0, min_t(u8, bc, 3)); if (bc > 3) - pa_write_data(pmic_arb, buf + 4, - offset + PMIC_ARB_WDATA1, bc - 4); + pa_write_data(pa, buf + 4, offset + PMIC_ARB_WDATA1, bc - 4); /* Start the transaction */ - pmic_arb_base_write(pmic_arb, offset + PMIC_ARB_CMD, cmd); - rc = pmic_arb_wait_for_done(ctrl, pmic_arb->wr_base, sid, addr); - raw_spin_unlock_irqrestore(&pmic_arb->lock, flags); + pmic_arb_base_write(pa, offset + PMIC_ARB_CMD, cmd); + rc = pmic_arb_wait_for_done(ctrl, pa->wr_base, sid, addr, + PMIC_ARB_CHANNEL_RW); + raw_spin_unlock_irqrestore(&pa->lock, flags); return rc; } @@ -404,9 +499,9 @@ static void qpnpint_spmi_write(struct irq_data *d, u8 reg, void *buf, size_t len) { - struct spmi_pmic_arb_dev *pa = irq_data_get_irq_chip_data(d); - u8 sid = d->hwirq >> 24; - u8 per = d->hwirq >> 16; + struct spmi_pmic_arb *pa = irq_data_get_irq_chip_data(d); + u8 sid = HWIRQ_SID(d->hwirq); + u8 per = HWIRQ_PER(d->hwirq); if (pmic_arb_write_cmd(pa->spmic, SPMI_CMD_EXT_WRITEL, sid, (per << 8) + reg, buf, len)) @@ -417,9 +512,9 @@ static void qpnpint_spmi_read(struct irq_data *d, u8 reg, void *buf, size_t len) { - struct spmi_pmic_arb_dev *pa = irq_data_get_irq_chip_data(d); - u8 sid = d->hwirq >> 24; - u8 per = d->hwirq >> 16; + struct spmi_pmic_arb *pa = irq_data_get_irq_chip_data(d); + u8 sid = HWIRQ_SID(d->hwirq); + u8 per = HWIRQ_PER(d->hwirq); if (pmic_arb_read_cmd(pa->spmic, SPMI_CMD_EXT_READL, sid, (per << 8) + reg, buf, len)) @@ -428,145 +523,196 @@ d->irq); } -static void periph_interrupt(struct spmi_pmic_arb_dev *pa, u8 apid) +static void cleanup_irq(struct spmi_pmic_arb *pa, u16 apid, int id) +{ + u16 ppid = pa->apid_data[apid].ppid; + u8 sid = ppid >> 8; + u8 per = ppid & 0xFF; + u8 irq_mask = BIT(id); + + dev_err_ratelimited(&pa->spmic->dev, + "cleanup_irq apid=%d sid=0x%x per=0x%x irq=%d\n", + apid, sid, per, id); + writel_relaxed(irq_mask, pa->intr + pa->ver_ops->irq_clear(apid)); +} + +static void periph_interrupt(struct spmi_pmic_arb *pa, u16 apid, bool show) { unsigned int irq; u32 status; int id; + u8 sid = (pa->apid_data[apid].ppid >> 8) & 0xF; + u8 per = pa->apid_data[apid].ppid & 0xFF; status = readl_relaxed(pa->intr + pa->ver_ops->irq_status(apid)); while (status) { id = ffs(status) - 1; - status &= ~(1 << id); - irq = irq_find_mapping(pa->domain, - pa->apid_to_ppid[apid] << 16 - | id << 8 - | apid); + status &= ~BIT(id); + irq = irq_find_mapping(pa->domain, HWIRQ(sid, per, id, apid)); + if (irq == 0) { + cleanup_irq(pa, apid, id); + continue; + } + if (show) { + struct irq_desc *desc; + const char *name = "null"; + + desc = irq_to_desc(irq); + if (desc == NULL) + name = "stray irq"; + else if (desc->action && desc->action->name) + name = desc->action->name; + + pr_warn("spmi_show_resume_irq: %d triggered [0x%01x, 0x%02x, 0x%01x] %s\n", + irq, sid, per, id, name); + } else { generic_handle_irq(irq); } } +} -static void pmic_arb_chained_irq(struct irq_desc *desc) +static void __pmic_arb_chained_irq(struct spmi_pmic_arb *pa, bool show) { - struct spmi_pmic_arb_dev *pa = irq_desc_get_handler_data(desc); - struct irq_chip *chip = irq_desc_get_chip(desc); - void __iomem *intr = pa->intr; int first = pa->min_apid >> 5; int last = pa->max_apid >> 5; - u32 status; - int i, id; - - chained_irq_enter(chip, desc); + u32 status, enable; + int i, id, apid; + /* status based dispatch */ + bool acc_valid = false; + u32 irq_status = 0; for (i = first; i <= last; ++i) { - status = readl_relaxed(intr + + status = readl_relaxed(pa->acc_status + pa->ver_ops->owner_acc_status(pa->ee, i)); + if (status) + acc_valid = true; + while (status) { id = ffs(status) - 1; - status &= ~(1 << id); - periph_interrupt(pa, id + i * 32); + status &= ~BIT(id); + apid = id + i * 32; + if (apid < pa->min_apid || apid > pa->max_apid) { + WARN_ONCE(true, "spurious spmi irq received for apid=%d\n", + apid); + continue; + } + enable = readl_relaxed(pa->intr + + pa->ver_ops->acc_enable(apid)); + if (enable & SPMI_PIC_ACC_ENABLE_BIT) + periph_interrupt(pa, apid, show); } } + /* ACC_STATUS is empty but IRQ fired check IRQ_STATUS */ + if (!acc_valid) { + for (i = pa->min_apid; i <= pa->max_apid; i++) { + /* skip if APPS is not irq owner */ + if (pa->apid_data[i].irq_owner != pa->ee) + continue; + + irq_status = readl_relaxed(pa->intr + + pa->ver_ops->irq_status(i)); + if (irq_status) { + enable = readl_relaxed(pa->intr + + pa->ver_ops->acc_enable(i)); + if (enable & SPMI_PIC_ACC_ENABLE_BIT) { + dev_dbg(&pa->spmic->dev, + "Dispatching IRQ for apid=%d status=%x\n", + i, irq_status); + periph_interrupt(pa, i, show); + } + } + } + } +} + +static void pmic_arb_chained_irq(struct irq_desc *desc) +{ + struct spmi_pmic_arb *pa = irq_desc_get_handler_data(desc); + struct irq_chip *chip = irq_desc_get_chip(desc); + + chained_irq_enter(chip, desc); + __pmic_arb_chained_irq(pa, false); chained_irq_exit(chip, desc); } static void qpnpint_irq_ack(struct irq_data *d) { - struct spmi_pmic_arb_dev *pa = irq_data_get_irq_chip_data(d); - u8 irq = d->hwirq >> 8; - u8 apid = d->hwirq; - unsigned long flags; + struct spmi_pmic_arb *pa = irq_data_get_irq_chip_data(d); + u8 irq = HWIRQ_IRQ(d->hwirq); + u16 apid = HWIRQ_APID(d->hwirq); u8 data; - raw_spin_lock_irqsave(&pa->lock, flags); - writel_relaxed(1 << irq, pa->intr + pa->ver_ops->irq_clear(apid)); - raw_spin_unlock_irqrestore(&pa->lock, flags); + writel_relaxed(BIT(irq), pa->intr + pa->ver_ops->irq_clear(apid)); - data = 1 << irq; + data = BIT(irq); qpnpint_spmi_write(d, QPNPINT_REG_LATCHED_CLR, &data, 1); } static void qpnpint_irq_mask(struct irq_data *d) { - struct spmi_pmic_arb_dev *pa = irq_data_get_irq_chip_data(d); - u8 irq = d->hwirq >> 8; - u8 apid = d->hwirq; - unsigned long flags; - u32 status; - u8 data; + u8 irq = HWIRQ_IRQ(d->hwirq); + u8 data = BIT(irq); - raw_spin_lock_irqsave(&pa->lock, flags); - status = readl_relaxed(pa->intr + pa->ver_ops->acc_enable(apid)); - if (status & SPMI_PIC_ACC_ENABLE_BIT) { - status = status & ~SPMI_PIC_ACC_ENABLE_BIT; - writel_relaxed(status, pa->intr + - pa->ver_ops->acc_enable(apid)); - } - raw_spin_unlock_irqrestore(&pa->lock, flags); - - data = 1 << irq; qpnpint_spmi_write(d, QPNPINT_REG_EN_CLR, &data, 1); } static void qpnpint_irq_unmask(struct irq_data *d) { - struct spmi_pmic_arb_dev *pa = irq_data_get_irq_chip_data(d); - u8 irq = d->hwirq >> 8; - u8 apid = d->hwirq; - unsigned long flags; - u32 status; - u8 data; + struct spmi_pmic_arb *pa = irq_data_get_irq_chip_data(d); + u8 irq = HWIRQ_IRQ(d->hwirq); + u16 apid = HWIRQ_APID(d->hwirq); + u8 buf[2]; - raw_spin_lock_irqsave(&pa->lock, flags); - status = readl_relaxed(pa->intr + pa->ver_ops->acc_enable(apid)); - if (!(status & SPMI_PIC_ACC_ENABLE_BIT)) { - writel_relaxed(status | SPMI_PIC_ACC_ENABLE_BIT, + writel_relaxed(SPMI_PIC_ACC_ENABLE_BIT, pa->intr + pa->ver_ops->acc_enable(apid)); - } - raw_spin_unlock_irqrestore(&pa->lock, flags); - data = 1 << irq; - qpnpint_spmi_write(d, QPNPINT_REG_EN_SET, &data, 1); + qpnpint_spmi_read(d, QPNPINT_REG_EN_SET, &buf[0], 1); + if (!(buf[0] & BIT(irq))) { + /* + * Since the interrupt is currently disabled, write to both the + * LATCHED_CLR and EN_SET registers so that a spurious interrupt + * cannot be triggered when the interrupt is enabled + */ + buf[0] = BIT(irq); + buf[1] = BIT(irq); + qpnpint_spmi_write(d, QPNPINT_REG_LATCHED_CLR, &buf, 2); } - -static void qpnpint_irq_enable(struct irq_data *d) -{ - u8 irq = d->hwirq >> 8; - u8 data; - - qpnpint_irq_unmask(d); - - data = 1 << irq; - qpnpint_spmi_write(d, QPNPINT_REG_LATCHED_CLR, &data, 1); } static int qpnpint_irq_set_type(struct irq_data *d, unsigned int flow_type) { struct spmi_pmic_arb_qpnpint_type type; - u8 irq = d->hwirq >> 8; + u8 irq = HWIRQ_IRQ(d->hwirq); + u8 bit_mask_irq = BIT(irq); qpnpint_spmi_read(d, QPNPINT_REG_SET_TYPE, &type, sizeof(type)); if (flow_type & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING)) { - type.type |= 1 << irq; + type.type |= bit_mask_irq; if (flow_type & IRQF_TRIGGER_RISING) - type.polarity_high |= 1 << irq; + type.polarity_high |= bit_mask_irq; if (flow_type & IRQF_TRIGGER_FALLING) - type.polarity_low |= 1 << irq; + type.polarity_low |= bit_mask_irq; } else { if ((flow_type & (IRQF_TRIGGER_HIGH)) && (flow_type & (IRQF_TRIGGER_LOW))) return -EINVAL; - type.type &= ~(1 << irq); /* level trig */ + type.type &= ~bit_mask_irq; /* level trig */ if (flow_type & IRQF_TRIGGER_HIGH) - type.polarity_high |= 1 << irq; + type.polarity_high |= bit_mask_irq; else - type.polarity_low |= 1 << irq; + type.polarity_low |= bit_mask_irq; } qpnpint_spmi_write(d, QPNPINT_REG_SET_TYPE, &type, sizeof(type)); + + if (flow_type & IRQ_TYPE_EDGE_BOTH) + irq_set_handler_locked(d, handle_edge_irq); + else + irq_set_handler_locked(d, handle_level_irq); + return 0; } @@ -574,7 +720,7 @@ enum irqchip_irq_state which, bool *state) { - u8 irq = d->hwirq >> 8; + u8 irq = HWIRQ_IRQ(d->hwirq); u8 status = 0; if (which != IRQCHIP_STATE_LINE_LEVEL) @@ -588,7 +734,6 @@ static struct irq_chip pmic_arb_irqchip = { .name = "pmic_arb", - .irq_enable = qpnpint_irq_enable, .irq_ack = qpnpint_irq_ack, .irq_mask = qpnpint_irq_mask, .irq_unmask = qpnpint_irq_unmask, @@ -598,42 +743,15 @@ | IRQCHIP_SKIP_SET_WAKE, }; -struct spmi_pmic_arb_irq_spec { - unsigned slave:4; - unsigned per:8; - unsigned irq:3; -}; - -static int search_mapping_table(struct spmi_pmic_arb_dev *pa, - struct spmi_pmic_arb_irq_spec *spec, - u8 *apid) +static void qpnpint_irq_domain_activate(struct irq_domain *domain, + struct irq_data *d) { - u16 ppid = spec->slave << 8 | spec->per; - u32 *mapping_table = pa->mapping_table; - int index = 0, i; - u32 data; + u8 irq = HWIRQ_IRQ(d->hwirq); + u8 buf; - for (i = 0; i < SPMI_MAPPING_TABLE_TREE_DEPTH; ++i) { - data = mapping_table[index]; - - if (ppid & (1 << SPMI_MAPPING_BIT_INDEX(data))) { - if (SPMI_MAPPING_BIT_IS_1_FLAG(data)) { - index = SPMI_MAPPING_BIT_IS_1_RESULT(data); - } else { - *apid = SPMI_MAPPING_BIT_IS_1_RESULT(data); - return 0; - } - } else { - if (SPMI_MAPPING_BIT_IS_0_FLAG(data)) { - index = SPMI_MAPPING_BIT_IS_0_RESULT(data); - } else { - *apid = SPMI_MAPPING_BIT_IS_0_RESULT(data); - return 0; - } - } - } - - return -ENODEV; + buf = BIT(irq); + qpnpint_spmi_write(d, QPNPINT_REG_EN_CLR, &buf, 1); + qpnpint_spmi_write(d, QPNPINT_REG_LATCHED_CLR, &buf, 1); } static int qpnpint_irq_domain_dt_translate(struct irq_domain *d, @@ -643,10 +761,9 @@ unsigned long *out_hwirq, unsigned int *out_type) { - struct spmi_pmic_arb_dev *pa = d->host_data; - struct spmi_pmic_arb_irq_spec spec; - int err; - u8 apid; + struct spmi_pmic_arb *pa = d->host_data; + int rc; + u16 apid; dev_dbg(&pa->spmic->dev, "intspec[0] 0x%1x intspec[1] 0x%02x intspec[2] 0x%02x\n", @@ -659,15 +776,21 @@ if (intspec[0] > 0xF || intspec[1] > 0xFF || intspec[2] > 0x7) return -EINVAL; - spec.slave = intspec[0]; - spec.per = intspec[1]; - spec.irq = intspec[2]; - - err = search_mapping_table(pa, &spec, &apid); - if (err) - return err; + rc = pa->ver_ops->ppid_to_apid(pa, intspec[0], + (intspec[1] << 8), &apid); + if (rc < 0) { + dev_err(&pa->spmic->dev, + "failed to xlate sid = 0x%x, periph = 0x%x, irq = %u rc = %d\n", + intspec[0], intspec[1], intspec[2], rc); + return rc; + } - pa->apid_to_ppid[apid] = spec.slave << 8 | spec.per; + if (pa->apid_data[apid].irq_owner != pa->ee) { + dev_err(&pa->spmic->dev, "failed to xlate sid = 0x%x, periph = 0x%x, irq = %u: ee=%u but owner=%u\n", + intspec[0], intspec[1], intspec[2], pa->ee, + pa->apid_data[apid].irq_owner); + return -ENODEV; + } /* Keep track of {max,min}_apid for bounding search during interrupt */ if (apid > pa->max_apid) @@ -675,10 +798,7 @@ if (apid < pa->min_apid) pa->min_apid = apid; - *out_hwirq = spec.slave << 24 - | spec.per << 16 - | spec.irq << 8 - | apid; + *out_hwirq = HWIRQ(intspec[0], intspec[1], intspec[2], apid); *out_type = intspec[3] & IRQ_TYPE_SENSE_MASK; dev_dbg(&pa->spmic->dev, "out_hwirq = %lu\n", *out_hwirq); @@ -690,7 +810,7 @@ unsigned int virq, irq_hw_number_t hwirq) { - struct spmi_pmic_arb_dev *pa = d->host_data; + struct spmi_pmic_arb *pa = d->host_data; dev_dbg(&pa->spmic->dev, "virq = %u, hwirq = %lu\n", virq, hwirq); @@ -700,19 +820,267 @@ return 0; } +static int +pmic_arb_ppid_to_apid_v1(struct spmi_pmic_arb *pa, u8 sid, u16 addr, u16 *apid) +{ + u16 ppid = sid << 8 | ((addr >> 8) & 0xFF); + u32 *mapping_table = pa->mapping_table; + int index = 0, i; + u16 apid_valid; + u32 data; + + apid_valid = pa->ppid_to_apid[ppid]; + if (apid_valid & PMIC_ARB_CHAN_VALID) { + *apid = (apid_valid & ~PMIC_ARB_CHAN_VALID); + return 0; + } + + for (i = 0; i < SPMI_MAPPING_TABLE_TREE_DEPTH; ++i) { + if (!test_and_set_bit(index, pa->mapping_table_valid)) + mapping_table[index] = readl_relaxed(pa->cnfg + + SPMI_MAPPING_TABLE_REG(index)); + + data = mapping_table[index]; + + if (ppid & BIT(SPMI_MAPPING_BIT_INDEX(data))) { + if (SPMI_MAPPING_BIT_IS_1_FLAG(data)) { + index = SPMI_MAPPING_BIT_IS_1_RESULT(data); + } else { + *apid = SPMI_MAPPING_BIT_IS_1_RESULT(data); + pa->ppid_to_apid[ppid] + = *apid | PMIC_ARB_CHAN_VALID; + pa->apid_data[*apid].ppid = ppid; + return 0; + } + } else { + if (SPMI_MAPPING_BIT_IS_0_FLAG(data)) { + index = SPMI_MAPPING_BIT_IS_0_RESULT(data); + } else { + *apid = SPMI_MAPPING_BIT_IS_0_RESULT(data); + pa->ppid_to_apid[ppid] + = *apid | PMIC_ARB_CHAN_VALID; + pa->apid_data[*apid].ppid = ppid; + return 0; + } + } + } + + return -ENODEV; +} + +static int +pmic_arb_mode_v1_v3(struct spmi_pmic_arb *pa, u8 sid, u16 addr, mode_t *mode) +{ + *mode = 0600; + return 0; +} + /* v1 offset per ee */ -static u32 pmic_arb_offset_v1(struct spmi_pmic_arb_dev *pa, u8 sid, u16 addr) +static int +pmic_arb_offset_v1(struct spmi_pmic_arb *pa, u8 sid, u16 addr, + enum pmic_arb_channel ch_type, u32 *offset) { - return 0x800 + 0x80 * pa->channel; + *offset = 0x800 + 0x80 * pa->channel; + return 0; +} + +static u16 pmic_arb_find_apid(struct spmi_pmic_arb *pa, u16 ppid) +{ + u32 regval, offset; + u16 apid; + u16 id; + + /* + * PMIC_ARB_REG_CHNL is a table in HW mapping channel to ppid. + * ppid_to_apid is an in-memory invert of that table. + */ + for (apid = pa->last_apid; apid < pa->max_periph; apid++) { + /* Do not keep the reserved channel in the mapping table */ + if (pa->reserved_chan >= 0 && apid == pa->reserved_chan) + continue; + + regval = readl_relaxed(pa->cnfg + + SPMI_OWNERSHIP_TABLE_REG(apid)); + pa->apid_data[apid].irq_owner + = SPMI_OWNERSHIP_PERIPH2OWNER(regval); + pa->apid_data[apid].write_owner = pa->apid_data[apid].irq_owner; + + offset = pa->ver_ops->channel_map_offset(apid); + if (offset >= pa->core_size) + break; + + regval = readl_relaxed(pa->core + offset); + if (!regval) + continue; + + id = (regval >> 8) & PMIC_ARB_PPID_MASK; + pa->ppid_to_apid[id] = apid | PMIC_ARB_CHAN_VALID; + pa->apid_data[apid].ppid = id; + if (id == ppid) { + apid |= PMIC_ARB_CHAN_VALID; + break; + } + } + pa->last_apid = apid & ~PMIC_ARB_CHAN_VALID; + + return apid; } -/* v2 offset per ppid (chan) and per ee */ -static u32 pmic_arb_offset_v2(struct spmi_pmic_arb_dev *pa, u8 sid, u16 addr) +static int +pmic_arb_ppid_to_apid_v2(struct spmi_pmic_arb *pa, u8 sid, u16 addr, u16 *apid) { u16 ppid = (sid << 8) | (addr >> 8); - u8 chan = pa->ppid_to_chan[ppid]; + u16 apid_valid; + + apid_valid = pa->ppid_to_apid[ppid]; + if (!(apid_valid & PMIC_ARB_CHAN_VALID)) + apid_valid = pmic_arb_find_apid(pa, ppid); + if (!(apid_valid & PMIC_ARB_CHAN_VALID)) + return -ENODEV; + + *apid = (apid_valid & ~PMIC_ARB_CHAN_VALID); + return 0; +} + +static int pmic_arb_read_apid_map_v5(struct spmi_pmic_arb *pa) +{ + u32 regval, offset; + u16 apid, prev_apid, ppid; + bool valid, is_irq_owner; + + /* + * PMIC_ARB_REG_CHNL is a table in HW mapping APID (channel) to PPID. + * ppid_to_apid is an in-memory invert of that table. In order to allow + * multiple EE's to write to a single PPID in arbiter version 5, there + * is more than one APID mapped to each PPID. The owner field for each + * of these mappings specifies the EE which is allowed to write to the + * APID. The owner of the last (highest) APID for a given PPID will + * receive interrupts from the PPID. + */ + for (apid = 0; apid < pa->max_periph; apid++) { + /* Do not keep the reserved channel in the mapping table */ + if (pa->reserved_chan >= 0 && apid == pa->reserved_chan) + continue; + + offset = pa->ver_ops->channel_map_offset(apid); + if (offset >= pa->core_size) + break; + + regval = readl_relaxed(pa->core + offset); + if (!regval) + continue; + ppid = (regval >> 8) & PMIC_ARB_PPID_MASK; + is_irq_owner = PMIC_ARB_CHAN_IS_IRQ_OWNER(regval); + + regval = readl_relaxed(pa->cnfg + + SPMI_OWNERSHIP_TABLE_REG(apid)); + pa->apid_data[apid].write_owner + = SPMI_OWNERSHIP_PERIPH2OWNER(regval); + + pa->apid_data[apid].irq_owner = is_irq_owner ? + pa->apid_data[apid].write_owner : INVALID_EE; + + valid = pa->ppid_to_apid[ppid] & PMIC_ARB_CHAN_VALID; + prev_apid = pa->ppid_to_apid[ppid] & ~PMIC_ARB_CHAN_VALID; + + if (valid && is_irq_owner && + pa->apid_data[prev_apid].write_owner == pa->ee) { + /* + * Duplicate PPID mapping after the one for this EE; + * override the irq owner + */ + pa->apid_data[prev_apid].irq_owner + = pa->apid_data[apid].irq_owner; + } else if (!valid || is_irq_owner) { + /* First PPID mapping or duplicate for another EE */ + pa->ppid_to_apid[ppid] = apid | PMIC_ARB_CHAN_VALID; + } + + pa->apid_data[apid].ppid = ppid; + pa->last_apid = apid; + } + + /* Dump the mapping table for debug purposes. */ + dev_dbg(&pa->spmic->dev, "PPID APID Write-EE IRQ-EE\n"); + for (ppid = 0; ppid < PMIC_ARB_MAX_PPID; ppid++) { + valid = pa->ppid_to_apid[ppid] & PMIC_ARB_CHAN_VALID; + apid = pa->ppid_to_apid[ppid] & ~PMIC_ARB_CHAN_VALID; + + if (valid) + dev_dbg(&pa->spmic->dev, "0x%03X %3u %2u %2u\n", + ppid, apid, pa->apid_data[apid].write_owner, + pa->apid_data[apid].irq_owner); + } + + return 0; +} + +static int +pmic_arb_ppid_to_apid_v5(struct spmi_pmic_arb *pa, u8 sid, u16 addr, u16 *apid) +{ + u16 ppid = (sid << 8) | (addr >> 8); + + if (!(pa->ppid_to_apid[ppid] & PMIC_ARB_CHAN_VALID)) + return -ENODEV; + + *apid = pa->ppid_to_apid[ppid] & ~PMIC_ARB_CHAN_VALID; + + return 0; +} + +static int +pmic_arb_mode_v2(struct spmi_pmic_arb *pa, u8 sid, u16 addr, mode_t *mode) +{ + u16 apid; + int rc; + + rc = pa->ver_ops->ppid_to_apid(pa, sid, addr, &apid); + if (rc < 0) + return rc; + + *mode = 0; + *mode |= 0400; + + if (pa->ee == pa->apid_data[apid].write_owner) + *mode |= 0200; + return 0; +} + +/* v2 offset per ppid and per ee */ +static int +pmic_arb_offset_v2(struct spmi_pmic_arb *pa, u8 sid, u16 addr, + enum pmic_arb_channel ch_type, u32 *offset) +{ + u16 apid; + int rc; + + rc = pmic_arb_ppid_to_apid_v2(pa, sid, addr, &apid); + if (rc < 0) + return rc; + + *offset = 0x1000 * pa->ee + 0x8000 * apid; + return 0; +} + +/* + * v5 offset per ee and per apid for observer channels and per apid for + * read/write channels. + */ +static int +pmic_arb_offset_v5(struct spmi_pmic_arb *pa, u8 sid, u16 addr, + enum pmic_arb_channel ch_type, u32 *offset) +{ + u16 apid; + int rc; - return 0x1000 * pa->ee + 0x8000 * chan; + rc = pmic_arb_ppid_to_apid_v5(pa, sid, addr, &apid); + if (rc < 0) + return rc; + + *offset = (ch_type == PMIC_ARB_CHANNEL_OBS) + ? 0x10000 * pa->ee + 0x80 * apid + : 0x10000 * apid; + return 0; } static u32 pmic_arb_fmt_cmd_v1(u8 opc, u8 sid, u16 addr, u8 bc) @@ -725,47 +1093,85 @@ return (opc << 27) | ((addr & 0xff) << 4) | (bc & 0x7); } -static u32 pmic_arb_owner_acc_status_v1(u8 m, u8 n) +static u32 pmic_arb_owner_acc_status_v1(u8 m, u16 n) { return 0x20 * m + 0x4 * n; } -static u32 pmic_arb_owner_acc_status_v2(u8 m, u8 n) +static u32 pmic_arb_owner_acc_status_v2(u8 m, u16 n) { return 0x100000 + 0x1000 * m + 0x4 * n; } -static u32 pmic_arb_acc_enable_v1(u8 n) +static u32 pmic_arb_owner_acc_status_v3(u8 m, u16 n) +{ + return 0x200000 + 0x1000 * m + 0x4 * n; +} + +static u32 pmic_arb_owner_acc_status_v5(u8 m, u16 n) +{ + return 0x10000 * m + 0x4 * n; +} + +static u32 pmic_arb_acc_enable_v1(u16 n) { return 0x200 + 0x4 * n; } -static u32 pmic_arb_acc_enable_v2(u8 n) +static u32 pmic_arb_acc_enable_v2(u16 n) { return 0x1000 * n; } -static u32 pmic_arb_irq_status_v1(u8 n) +static u32 pmic_arb_acc_enable_v5(u16 n) +{ + return 0x100 + 0x10000 * n; +} + +static u32 pmic_arb_irq_status_v1(u16 n) { return 0x600 + 0x4 * n; } -static u32 pmic_arb_irq_status_v2(u8 n) +static u32 pmic_arb_irq_status_v2(u16 n) { return 0x4 + 0x1000 * n; } -static u32 pmic_arb_irq_clear_v1(u8 n) +static u32 pmic_arb_irq_status_v5(u16 n) +{ + return 0x104 + 0x10000 * n; +} + +static u32 pmic_arb_irq_clear_v1(u16 n) { return 0xA00 + 0x4 * n; } -static u32 pmic_arb_irq_clear_v2(u8 n) +static u32 pmic_arb_irq_clear_v2(u16 n) { return 0x8 + 0x1000 * n; } +static u32 pmic_arb_irq_clear_v5(u16 n) +{ + return 0x108 + 0x10000 * n; +} + +static u32 pmic_arb_channel_map_offset_v2(u16 n) +{ + return 0x800 + 0x4 * n; +} + +static u32 pmic_arb_channel_map_offset_v5(u16 n) +{ + return 0x900 + 0x4 * n; +} + static const struct pmic_arb_ver_ops pmic_arb_v1 = { + .ver_str = "v1", + .ppid_to_apid = pmic_arb_ppid_to_apid_v1, + .mode = pmic_arb_mode_v1_v3, .non_data_cmd = pmic_arb_non_data_cmd_v1, .offset = pmic_arb_offset_v1, .fmt_cmd = pmic_arb_fmt_cmd_v1, @@ -773,9 +1179,13 @@ .acc_enable = pmic_arb_acc_enable_v1, .irq_status = pmic_arb_irq_status_v1, .irq_clear = pmic_arb_irq_clear_v1, + .channel_map_offset = pmic_arb_channel_map_offset_v2, }; static const struct pmic_arb_ver_ops pmic_arb_v2 = { + .ver_str = "v2", + .ppid_to_apid = pmic_arb_ppid_to_apid_v2, + .mode = pmic_arb_mode_v2, .non_data_cmd = pmic_arb_non_data_cmd_v2, .offset = pmic_arb_offset_v2, .fmt_cmd = pmic_arb_fmt_cmd_v2, @@ -783,22 +1193,61 @@ .acc_enable = pmic_arb_acc_enable_v2, .irq_status = pmic_arb_irq_status_v2, .irq_clear = pmic_arb_irq_clear_v2, + .channel_map_offset = pmic_arb_channel_map_offset_v2, +}; + +static const struct pmic_arb_ver_ops pmic_arb_v3 = { + .ver_str = "v3", + .ppid_to_apid = pmic_arb_ppid_to_apid_v2, + .mode = pmic_arb_mode_v1_v3, + .non_data_cmd = pmic_arb_non_data_cmd_v2, + .offset = pmic_arb_offset_v2, + .fmt_cmd = pmic_arb_fmt_cmd_v2, + .owner_acc_status = pmic_arb_owner_acc_status_v3, + .acc_enable = pmic_arb_acc_enable_v2, + .irq_status = pmic_arb_irq_status_v2, + .irq_clear = pmic_arb_irq_clear_v2, + .channel_map_offset = pmic_arb_channel_map_offset_v2, +}; + +static const struct pmic_arb_ver_ops pmic_arb_v5 = { + .ver_str = "v5", + .ppid_to_apid = pmic_arb_ppid_to_apid_v5, + .mode = pmic_arb_mode_v2, + .non_data_cmd = pmic_arb_non_data_cmd_v2, + .offset = pmic_arb_offset_v5, + .fmt_cmd = pmic_arb_fmt_cmd_v2, + .owner_acc_status = pmic_arb_owner_acc_status_v5, + .acc_enable = pmic_arb_acc_enable_v5, + .irq_status = pmic_arb_irq_status_v5, + .irq_clear = pmic_arb_irq_clear_v5, + .channel_map_offset = pmic_arb_channel_map_offset_v5, }; static const struct irq_domain_ops pmic_arb_irq_domain_ops = { .map = qpnpint_irq_domain_map, .xlate = qpnpint_irq_domain_dt_translate, + .activate = qpnpint_irq_domain_activate, +}; + +static void spmi_pmic_arb_resume(void) +{ + if (spmi_show_resume_irq()) + __pmic_arb_chained_irq(the_pa, true); +} + +static struct syscore_ops spmi_pmic_arb_syscore_ops = { + .resume = spmi_pmic_arb_resume, }; static int spmi_pmic_arb_probe(struct platform_device *pdev) { - struct spmi_pmic_arb_dev *pa; + struct spmi_pmic_arb *pa; struct spmi_controller *ctrl; struct resource *res; void __iomem *core; u32 channel, ee, hw_ver; - int err, i; - bool is_v1; + int err; ctrl = spmi_controller_alloc(&pdev->dev, sizeof(*pa)); if (!ctrl) @@ -808,6 +1257,19 @@ pa->spmic = ctrl; res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "core"); + if (!res) { + dev_err(&pdev->dev, "core resource not specified\n"); + err = -EINVAL; + goto err_put_ctrl; + } + + pa->core_size = resource_size(res); + if (pa->core_size <= 0x800) { + dev_err(&pdev->dev, "core_size is smaller than 0x800. Failing Probe\n"); + err = -EINVAL; + goto err_put_ctrl; + } + core = devm_ioremap_resource(&ctrl->dev, res); if (IS_ERR(core)) { err = PTR_ERR(core); @@ -815,21 +1277,24 @@ } hw_ver = readl_relaxed(core + PMIC_ARB_VERSION); - is_v1 = (hw_ver < PMIC_ARB_VERSION_V2_MIN); - - dev_info(&ctrl->dev, "PMIC Arb Version-%d (0x%x)\n", (is_v1 ? 1 : 2), - hw_ver); - if (is_v1) { + if (hw_ver < PMIC_ARB_VERSION_V2_MIN) { pa->ver_ops = &pmic_arb_v1; pa->wr_base = core; pa->rd_base = core; } else { - u8 chan; - u16 ppid; - u32 regval; + pa->core = core; + if (hw_ver < PMIC_ARB_VERSION_V3_MIN) pa->ver_ops = &pmic_arb_v2; + else if (hw_ver < PMIC_ARB_VERSION_V5_MIN) + pa->ver_ops = &pmic_arb_v3; + else + pa->ver_ops = &pmic_arb_v5; + + /* the apid to ppid table starts at PMIC_ARB_REG_CHNL0 */ + pa->max_periph + = (pa->core_size - pa->ver_ops->channel_map_offset(0)) / 4; res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "obsrvr"); @@ -847,32 +1312,33 @@ goto err_put_ctrl; } - pa->ppid_to_chan = devm_kzalloc(&ctrl->dev, - PPID_TO_CHAN_TABLE_SZ, GFP_KERNEL); - if (!pa->ppid_to_chan) { + pa->ppid_to_apid = devm_kcalloc(&ctrl->dev, + PMIC_ARB_MAX_PPID, + sizeof(*pa->ppid_to_apid), + GFP_KERNEL); + if (!pa->ppid_to_apid) { err = -ENOMEM; goto err_put_ctrl; } - /* - * PMIC_ARB_REG_CHNL is a table in HW mapping channel to ppid. - * ppid_to_chan is an in-memory invert of that table. - */ - for (chan = 0; chan < PMIC_ARB_MAX_CHNL; ++chan) { - regval = readl_relaxed(core + PMIC_ARB_REG_CHNL(chan)); - if (!regval) - continue; - - ppid = (regval >> 8) & 0xFFF; - pa->ppid_to_chan[ppid] = chan; - } } + dev_info(&ctrl->dev, "PMIC arbiter version %s (0x%x)\n", + pa->ver_ops->ver_str, hw_ver); + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "intr"); pa->intr = devm_ioremap_resource(&ctrl->dev, res); if (IS_ERR(pa->intr)) { err = PTR_ERR(pa->intr); goto err_put_ctrl; } + pa->acc_status = pa->intr; + + /* + * PMIC arbiter v5 groups the IRQ control registers in the same hardware + * module as the read/write channels. + */ + if (hw_ver >= PMIC_ARB_VERSION_V5_MIN) + pa->intr = pa->wr_base; res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cnfg"); pa->cnfg = devm_ioremap_resource(&ctrl->dev, res); @@ -896,6 +1362,7 @@ if (channel > 5) { dev_err(&pdev->dev, "invalid channel (%u) specified.\n", channel); + err = -EINVAL; goto err_put_ctrl; } @@ -915,9 +1382,16 @@ pa->ee = ee; - for (i = 0; i < ARRAY_SIZE(pa->mapping_table); ++i) - pa->mapping_table[i] = readl_relaxed( - pa->cnfg + SPMI_MAPPING_TABLE_REG(i)); + pa->reserved_chan = -EINVAL; + of_property_read_u32(pdev->dev.of_node, "qcom,reserved-chan", + &pa->reserved_chan); + + pa->mapping_table = devm_kcalloc(&ctrl->dev, PMIC_ARB_MAX_PERIPHS - 1, + sizeof(*pa->mapping_table), GFP_KERNEL); + if (!pa->mapping_table) { + err = -ENOMEM; + goto err_put_ctrl; + } /* Initialize max_apid/min_apid to the opposite bounds, during * the irq domain translation, we are sure to update these */ @@ -931,6 +1405,15 @@ ctrl->read_cmd = pmic_arb_read_cmd; ctrl->write_cmd = pmic_arb_write_cmd; + if (hw_ver >= PMIC_ARB_VERSION_V5_MIN) { + err = pmic_arb_read_apid_map_v5(pa); + if (err) { + dev_err(&pdev->dev, "could not read APID->PPID mapping table, rc= %d\n", + err); + goto err_put_ctrl; + } + } + dev_dbg(&pdev->dev, "adding irq domain\n"); pa->domain = irq_domain_add_tree(pdev->dev.of_node, &pmic_arb_irq_domain_ops, pa); @@ -941,11 +1424,14 @@ } irq_set_chained_handler_and_data(pa->irq, pmic_arb_chained_irq, pa); + enable_irq_wake(pa->irq); err = spmi_controller_add(ctrl); if (err) goto err_domain_remove; + the_pa = pa; + register_syscore_ops(&spmi_pmic_arb_syscore_ops); return 0; err_domain_remove: @@ -959,9 +1445,12 @@ static int spmi_pmic_arb_remove(struct platform_device *pdev) { struct spmi_controller *ctrl = platform_get_drvdata(pdev); - struct spmi_pmic_arb_dev *pa = spmi_controller_get_drvdata(ctrl); + struct spmi_pmic_arb *pa = spmi_controller_get_drvdata(ctrl); + spmi_controller_remove(ctrl); irq_set_chained_handler_and_data(pa->irq, NULL, NULL); + unregister_syscore_ops(&spmi_pmic_arb_syscore_ops); + the_pa = NULL; irq_domain_remove(pa->domain); spmi_controller_put(ctrl); return 0; @@ -981,7 +1470,12 @@ .of_match_table = spmi_pmic_arb_match_table, }, }; -module_platform_driver(spmi_pmic_arb_driver); + +int __init spmi_pmic_arb_init(void) +{ + return platform_driver_register(&spmi_pmic_arb_driver); +} +arch_initcall(spmi_pmic_arb_init); MODULE_LICENSE("GPL v2"); MODULE_ALIAS("platform:spmi_pmic_arb"); diff -ruw linux-4.4.115/drivers/staging/android/ashmem.c linux-4.4.115-fbx/drivers/staging/android/ashmem.c --- linux-4.4.115/drivers/staging/android/ashmem.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/staging/android/ashmem.c 2019-10-29 09:26:24.841214902 +0100 @@ -397,21 +397,13 @@ } get_file(asma->file); - /* - * XXX - Reworked to use shmem_zero_setup() instead of - * shmem_set_file while we're in staging. -jstultz - */ - if (vma->vm_flags & VM_SHARED) { - ret = shmem_zero_setup(vma); - if (ret) { - fput(asma->file); - goto out; - } - } - + if (vma->vm_flags & VM_SHARED) + shmem_set_file(vma, asma->file); + else { if (vma->vm_file) fput(vma->vm_file); vma->vm_file = asma->file; + } out: mutex_unlock(&ashmem_mutex); @@ -442,12 +434,14 @@ if (!(sc->gfp_mask & __GFP_FS)) return SHRINK_STOP; - mutex_lock(&ashmem_mutex); + if (!mutex_trylock(&ashmem_mutex)) + return -1; + list_for_each_entry_safe(range, next, &ashmem_lru_list, lru) { loff_t start = range->pgstart * PAGE_SIZE; loff_t end = (range->pgend + 1) * PAGE_SIZE; - vfs_fallocate(range->asma->file, + range->asma->file->f_op->fallocate(range->asma->file, FALLOC_FL_PUNCH_HOLE | FALLOC_FL_KEEP_SIZE, start, end - start); range->purged = ASHMEM_WAS_PURGED; diff -ruw linux-4.4.115/drivers/staging/android/ion/compat_ion.h linux-4.4.115-fbx/drivers/staging/android/ion/compat_ion.h --- linux-4.4.115/drivers/staging/android/ion/compat_ion.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/staging/android/ion/compat_ion.h 2019-01-22 16:16:26.711275457 +0100 @@ -21,6 +21,8 @@ long compat_ion_ioctl(struct file *filp, unsigned int cmd, unsigned long arg); +#define compat_ion_user_handle_t compat_int_t + #else #define compat_ion_ioctl NULL diff -ruw linux-4.4.115/drivers/staging/android/ion/ion.c linux-4.4.115-fbx/drivers/staging/android/ion/ion.c --- linux-4.4.115/drivers/staging/android/ion/ion.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/staging/android/ion/ion.c 2019-10-29 09:26:24.845214941 +0100 @@ -3,6 +3,7 @@ * drivers/staging/android/ion/ion.c * * Copyright (C) 2011 Google, Inc. + * Copyright (c) 2011-2017, The Linux Foundation. All rights reserved. * * This software is licensed under the terms of the GNU General Public * License version 2, as published by the Free Software Foundation, and @@ -15,7 +16,7 @@ * */ -#include +#include #include #include #include @@ -23,6 +24,7 @@ #include #include #include +#include #include #include #include @@ -36,6 +38,10 @@ #include #include #include +#include +#include +#include + #include "ion.h" #include "ion_priv.h" @@ -86,7 +92,7 @@ struct rb_root handles; struct idr idr; struct mutex lock; - const char *name; + char *name; char *display_name; int display_serial; struct task_struct *task; @@ -108,6 +114,7 @@ */ struct ion_handle { struct kref ref; + unsigned int user_ref_count; struct ion_client *client; struct ion_buffer *buffer; struct rb_node node; @@ -207,6 +214,8 @@ buffer->dev = dev; buffer->size = len; + buffer->flags = flags; + INIT_LIST_HEAD(&buffer->vmas); table = heap->ops->map_dma(heap, buffer); if (WARN_ONCE(table == NULL, @@ -237,9 +246,6 @@ } } - buffer->dev = dev; - buffer->size = len; - INIT_LIST_HEAD(&buffer->vmas); mutex_init(&buffer->lock); /* * this will set up dma addresses for the sglist -- it is not @@ -258,6 +264,7 @@ mutex_lock(&dev->buffer_lock); ion_buffer_add(dev, buffer); mutex_unlock(&dev->buffer_lock); + atomic_long_add(len, &heap->total_allocated); return buffer; err: @@ -274,6 +281,8 @@ if (WARN_ON(buffer->kmap_cnt > 0)) buffer->heap->ops->unmap_kernel(buffer->heap, buffer); buffer->heap->ops->unmap_dma(buffer->heap, buffer); + + atomic_long_sub(buffer->size, &buffer->heap->total_allocated); buffer->heap->ops->free(buffer); vfree(buffer->pages); kfree(buffer); @@ -285,6 +294,8 @@ struct ion_heap *heap = buffer->heap; struct ion_device *dev = buffer->dev; + msm_dma_buf_freed(buffer); + mutex_lock(&dev->buffer_lock); rb_erase(&buffer->node, &dev->buffers); mutex_unlock(&dev->buffer_lock); @@ -308,6 +319,9 @@ static void ion_buffer_add_to_handle(struct ion_buffer *buffer) { mutex_lock(&buffer->lock); + if (buffer->handle_count == 0) + atomic_long_add(buffer->size, &buffer->heap->total_handles); + buffer->handle_count++; mutex_unlock(&buffer->lock); } @@ -332,6 +346,7 @@ task = current->group_leader; get_task_comm(buffer->task_comm, task); buffer->pid = task_pid_nr(task); + atomic_long_sub(buffer->size, &buffer->heap->total_handles); } mutex_unlock(&buffer->lock); } @@ -387,6 +402,15 @@ kref_get(&handle->ref); } +/* Must hold the client lock */ +static struct ion_handle* ion_handle_get_check_overflow(struct ion_handle *handle) +{ + if (atomic_read(&handle->ref.refcount) + 1 == 0) + return ERR_PTR(-EOVERFLOW); + ion_handle_get(handle); + return handle; +} + static int ion_handle_put_nolock(struct ion_handle *handle) { int ret; @@ -408,6 +432,50 @@ return ret; } +/* Must hold the client lock */ +static void user_ion_handle_get(struct ion_handle *handle) +{ + if (handle->user_ref_count++ == 0) + kref_get(&handle->ref); +} + +/* Must hold the client lock */ +static struct ion_handle *user_ion_handle_get_check_overflow( + struct ion_handle *handle) +{ + if (handle->user_ref_count + 1 == 0) + return ERR_PTR(-EOVERFLOW); + user_ion_handle_get(handle); + return handle; +} + +/* passes a kref to the user ref count. + * We know we're holding a kref to the object before and + * after this call, so no need to reverify handle. + */ +static struct ion_handle *pass_to_user(struct ion_handle *handle) +{ + struct ion_client *client = handle->client; + struct ion_handle *ret; + + mutex_lock(&client->lock); + ret = user_ion_handle_get_check_overflow(handle); + ion_handle_put_nolock(handle); + mutex_unlock(&client->lock); + return ret; +} + +/* Must hold the client lock */ +static int user_ion_handle_put_nolock(struct ion_handle *handle) +{ + int ret = 0; + + if (--handle->user_ref_count == 0) + ret = ion_handle_put_nolock(handle); + + return ret; +} + static struct ion_handle *ion_handle_lookup(struct ion_client *client, struct ion_buffer *buffer) { @@ -433,9 +501,9 @@ handle = idr_find(&client->idr, id); if (handle) - ion_handle_get(handle); + return ion_handle_get_check_overflow(handle); - return handle ? handle : ERR_PTR(-EINVAL); + return ERR_PTR(-EINVAL); } struct ion_handle *ion_handle_get_by_id(struct ion_client *client, @@ -488,15 +556,28 @@ return 0; } -struct ion_handle *ion_alloc(struct ion_client *client, size_t len, +static struct ion_handle *__ion_alloc(struct ion_client *client, size_t len, size_t align, unsigned int heap_id_mask, - unsigned int flags) + unsigned int flags, bool grab_handle) { struct ion_handle *handle; struct ion_device *dev = client->dev; struct ion_buffer *buffer = NULL; struct ion_heap *heap; int ret; + const unsigned int MAX_DBG_STR_LEN = 64; + char dbg_str[MAX_DBG_STR_LEN]; + unsigned int dbg_str_idx = 0; + + dbg_str[0] = '\0'; + + /* + * For now, we don't want to fault in pages individually since + * clients are already doing manual cache maintenance. In + * other words, the implicit caching infrastructure is in + * place (in code) but should not be used. + */ + flags |= ION_FLAG_CACHED_NEEDS_SYNC; pr_debug("%s: len %zu align %zu heap_id_mask %u flags %x\n", __func__, len, align, heap_id_mask, flags); @@ -516,17 +597,49 @@ /* if the caller didn't specify this heap id */ if (!((1 << heap->id) & heap_id_mask)) continue; + trace_ion_alloc_buffer_start(client->name, heap->name, len, + heap_id_mask, flags); buffer = ion_buffer_create(heap, dev, len, align, flags); + trace_ion_alloc_buffer_end(client->name, heap->name, len, + heap_id_mask, flags); if (!IS_ERR(buffer)) break; + + trace_ion_alloc_buffer_fallback(client->name, heap->name, len, + heap_id_mask, flags, + PTR_ERR(buffer)); + if (dbg_str_idx < MAX_DBG_STR_LEN) { + unsigned int len_left = MAX_DBG_STR_LEN-dbg_str_idx-1; + int ret_value = snprintf(&dbg_str[dbg_str_idx], + len_left, "%s ", heap->name); + if (ret_value >= len_left) { + /* overflow */ + dbg_str[MAX_DBG_STR_LEN-1] = '\0'; + dbg_str_idx = MAX_DBG_STR_LEN; + } else if (ret_value >= 0) { + dbg_str_idx += ret_value; + } else { + /* error */ + dbg_str[MAX_DBG_STR_LEN-1] = '\0'; + } + } } up_read(&dev->lock); - if (buffer == NULL) + if (buffer == NULL) { + trace_ion_alloc_buffer_fail(client->name, dbg_str, len, + heap_id_mask, flags, -ENODEV); return ERR_PTR(-ENODEV); + } - if (IS_ERR(buffer)) + if (IS_ERR(buffer)) { + trace_ion_alloc_buffer_fail(client->name, dbg_str, len, + heap_id_mask, flags, + PTR_ERR(buffer)); + pr_debug("ION is unable to allocate 0x%zx bytes (alignment: 0x%zx) from heap(s) %sfor client %s\n", + len, align, dbg_str, client->name); return ERR_CAST(buffer); + } handle = ion_handle_create(client, buffer); @@ -540,6 +653,8 @@ return handle; mutex_lock(&client->lock); + if (grab_handle) + ion_handle_get(handle); ret = ion_handle_add(client, handle); mutex_unlock(&client->lock); if (ret) { @@ -549,6 +664,13 @@ return handle; } + +struct ion_handle *ion_alloc(struct ion_client *client, size_t len, + size_t align, unsigned int heap_id_mask, + unsigned int flags) +{ + return __ion_alloc(client, len, align, heap_id_mask, flags, false); +} EXPORT_SYMBOL(ion_alloc); static void ion_free_nolock(struct ion_client *client, struct ion_handle *handle) @@ -558,7 +680,6 @@ BUG_ON(client != handle->client); valid_handle = ion_handle_validate(client, handle); - if (!valid_handle) { WARN(1, "%s: invalid handle passed to free.\n", __func__); return; @@ -566,6 +687,25 @@ ion_handle_put_nolock(handle); } +static void user_ion_free_nolock(struct ion_client *client, + struct ion_handle *handle) +{ + bool valid_handle; + + WARN_ON(client != handle->client); + + valid_handle = ion_handle_validate(client, handle); + if (!valid_handle) { + WARN(1, "%s: invalid handle passed to free.\n", __func__); + return; + } + if (handle->user_ref_count == 0) { + WARN(1, "%s: User does not have access!\n", __func__); + return; + } + user_ion_handle_put_nolock(handle); +} + void ion_free(struct ion_client *client, struct ion_handle *handle) { BUG_ON(client != handle->client); @@ -702,32 +842,66 @@ } EXPORT_SYMBOL(ion_unmap_kernel); +static struct mutex debugfs_mutex; +static struct rb_root *ion_root_client; +static int is_client_alive(struct ion_client *client) +{ + struct rb_node *node; + struct ion_client *tmp; + struct ion_device *dev; + + node = ion_root_client->rb_node; + dev = container_of(ion_root_client, struct ion_device, clients); + + down_read(&dev->lock); + while (node) { + tmp = rb_entry(node, struct ion_client, node); + if (client < tmp) { + node = node->rb_left; + } else if (client > tmp) { + node = node->rb_right; + } else { + up_read(&dev->lock); + return 1; + } + } + + up_read(&dev->lock); + return 0; +} + static int ion_debug_client_show(struct seq_file *s, void *unused) { struct ion_client *client = s->private; struct rb_node *n; - size_t sizes[ION_NUM_HEAP_IDS] = {0}; - const char *names[ION_NUM_HEAP_IDS] = {NULL}; - int i; + + mutex_lock(&debugfs_mutex); + if (!is_client_alive(client)) { + seq_printf(s, "ion_client 0x%pK dead, can't dump its buffers\n", + client); + mutex_unlock(&debugfs_mutex); + return 0; + } + + seq_printf(s, "%16.16s: %16.16s : %16.16s : %12.12s\n", + "heap_name", "size_in_bytes", "handle refcount", + "buffer"); mutex_lock(&client->lock); for (n = rb_first(&client->handles); n; n = rb_next(n)) { struct ion_handle *handle = rb_entry(n, struct ion_handle, node); - unsigned int id = handle->buffer->heap->id; - if (!names[id]) - names[id] = handle->buffer->heap->name; - sizes[id] += handle->buffer->size; - } - mutex_unlock(&client->lock); + seq_printf(s, "%16.16s: %16zx : %16d : %12pK", + handle->buffer->heap->name, + handle->buffer->size, + atomic_read(&handle->ref.refcount), + handle->buffer); - seq_printf(s, "%16.16s: %16.16s\n", "heap_name", "size_in_bytes"); - for (i = 0; i < ION_NUM_HEAP_IDS; i++) { - if (!names[i]) - continue; - seq_printf(s, "%16.16s: %16zu\n", names[i], sizes[i]); + seq_printf(s, "\n"); } + mutex_unlock(&client->lock); + mutex_unlock(&debugfs_mutex); return 0; } @@ -798,6 +972,7 @@ client->handles = RB_ROOT; idr_init(&client->idr); mutex_init(&client->lock); + client->task = task; client->pid = pid; client->name = kstrdup(name, GFP_KERNEL); @@ -857,6 +1032,7 @@ struct rb_node *n; pr_debug("%s: %d\n", __func__, __LINE__); + mutex_lock(&debugfs_mutex); while ((n = rb_first(&client->handles))) { struct ion_handle *handle = rb_entry(n, struct ion_handle, node); @@ -870,14 +1046,67 @@ put_task_struct(client->task); rb_erase(&client->node, &dev->clients); debugfs_remove_recursive(client->debug_root); + up_write(&dev->lock); kfree(client->display_name); kfree(client->name); kfree(client); + mutex_unlock(&debugfs_mutex); } EXPORT_SYMBOL(ion_client_destroy); +int ion_handle_get_flags(struct ion_client *client, struct ion_handle *handle, + unsigned long *flags) +{ + struct ion_buffer *buffer; + + mutex_lock(&client->lock); + if (!ion_handle_validate(client, handle)) { + pr_err("%s: invalid handle passed to %s.\n", + __func__, __func__); + mutex_unlock(&client->lock); + return -EINVAL; + } + buffer = handle->buffer; + mutex_lock(&buffer->lock); + *flags = buffer->flags; + mutex_unlock(&buffer->lock); + mutex_unlock(&client->lock); + + return 0; +} +EXPORT_SYMBOL(ion_handle_get_flags); + +int ion_handle_get_size(struct ion_client *client, struct ion_handle *handle, + size_t *size) +{ + struct ion_buffer *buffer; + + mutex_lock(&client->lock); + if (!ion_handle_validate(client, handle)) { + pr_err("%s: invalid handle passed to %s.\n", + __func__, __func__); + mutex_unlock(&client->lock); + return -EINVAL; + } + buffer = handle->buffer; + mutex_lock(&buffer->lock); + *size = buffer->size; + mutex_unlock(&buffer->lock); + mutex_unlock(&client->lock); + + return 0; +} +EXPORT_SYMBOL(ion_handle_get_size); + +/** + * ion_sg_table - get an sg_table for the buffer + * + * NOTE: most likely you should NOT being using this API. + * You should be using Ion as a DMA Buf exporter and using + * the sg_table returned by dma_buf_map_attachment. + */ struct sg_table *ion_sg_table(struct ion_client *client, struct ion_handle *handle) { @@ -898,6 +1127,60 @@ } EXPORT_SYMBOL(ion_sg_table); +struct sg_table *ion_create_chunked_sg_table(phys_addr_t buffer_base, + size_t chunk_size, size_t total_size) +{ + struct sg_table *table; + int i, n_chunks, ret; + struct scatterlist *sg; + + table = kzalloc(sizeof(struct sg_table), GFP_KERNEL); + if (!table) + return ERR_PTR(-ENOMEM); + + n_chunks = DIV_ROUND_UP(total_size, chunk_size); + pr_debug("creating sg_table with %d chunks\n", n_chunks); + + ret = sg_alloc_table(table, n_chunks, GFP_KERNEL); + if (ret) + goto err0; + + for_each_sg(table->sgl, sg, table->nents, i) { + dma_addr_t addr = buffer_base + i * chunk_size; + sg_dma_address(sg) = addr; + sg->length = chunk_size; + } + + return table; +err0: + kfree(table); + return ERR_PTR(ret); +} + +static struct sg_table *ion_dupe_sg_table(struct sg_table *orig_table) +{ + int ret, i; + struct scatterlist *sg, *sg_orig; + struct sg_table *table; + + table = kzalloc(sizeof(struct sg_table), GFP_KERNEL); + if (!table) + return NULL; + + ret = sg_alloc_table(table, orig_table->nents, GFP_KERNEL); + if (ret) { + kfree(table); + return NULL; + } + + sg_orig = orig_table->sgl; + for_each_sg(table->sgl, sg, table->nents, i) { + memcpy(sg, sg_orig, sizeof(*sg)); + sg_orig = sg_next(sg_orig); + } + return table; +} + static void ion_buffer_sync_for_device(struct ion_buffer *buffer, struct device *dev, enum dma_data_direction direction); @@ -907,15 +1190,22 @@ { struct dma_buf *dmabuf = attachment->dmabuf; struct ion_buffer *buffer = dmabuf->priv; + struct sg_table *table; + + table = ion_dupe_sg_table(buffer->sg_table); + if (!table) + return NULL; ion_buffer_sync_for_device(buffer, attachment->dev, direction); - return buffer->sg_table; + return table; } static void ion_unmap_dma_buf(struct dma_buf_attachment *attachment, struct sg_table *table, enum dma_data_direction direction) { + sg_free_table(table); + kfree(table); } void ion_pages_sync_for_device(struct device *dev, struct page *page, @@ -923,6 +1213,8 @@ { struct scatterlist sg; + WARN_ONCE(!dev, "A device is required for dma_sync\n"); + sg_init_table(&sg, 1); sg_set_page(&sg, page, size, 0); /* @@ -1003,7 +1295,7 @@ mutex_lock(&buffer->lock); list_add(&vma_list->list, &buffer->vmas); mutex_unlock(&buffer->lock); - pr_debug("%s: adding %p\n", __func__, vma); + pr_debug("%s: adding %pK\n", __func__, vma); } static void ion_vm_close(struct vm_area_struct *vma) @@ -1018,10 +1310,13 @@ continue; list_del(&vma_list->list); kfree(vma_list); - pr_debug("%s: deleting %p\n", __func__, vma); + pr_debug("%s: deleting %pK\n", __func__, vma); break; } mutex_unlock(&buffer->lock); + + if (buffer->heap->ops->unmap_user) + buffer->heap->ops->unmap_user(buffer->heap, buffer); } static const struct vm_operations_struct ion_vma_ops = { @@ -1046,6 +1341,7 @@ VM_DONTDUMP; vma->vm_private_data = buffer; vma->vm_ops = &ion_vma_ops; + vma->vm_flags |= VM_MIXEDMAP; ion_vm_open(vma); return 0; } @@ -1173,11 +1469,32 @@ fd = dma_buf_fd(dmabuf, O_CLOEXEC); if (fd < 0) dma_buf_put(dmabuf); - return fd; } EXPORT_SYMBOL(ion_share_dma_buf_fd); +bool ion_dma_buf_is_secure(struct dma_buf *dmabuf) +{ + struct ion_buffer *buffer; + enum ion_heap_type type; + + /* Return false if we didn't create the buffer */ + if (!dmabuf || dmabuf->ops != &dma_buf_ops) + return false; + + buffer = dmabuf->priv; + + if (!buffer || !buffer->heap) + return false; + + type = buffer->heap->type; + + return (type == (enum ion_heap_type)ION_HEAP_TYPE_SECURE_DMA || + type == (enum ion_heap_type)ION_HEAP_TYPE_SYSTEM_SECURE) ? + true : false; +} +EXPORT_SYMBOL(ion_dma_buf_is_secure); + struct ion_handle *ion_import_dma_buf(struct ion_client *client, int fd) { struct dma_buf *dmabuf; @@ -1202,7 +1519,7 @@ /* if a handle exists for this buffer just take a reference to it */ handle = ion_handle_lookup(client, buffer); if (!IS_ERR(handle)) { - ion_handle_get(handle); + handle = ion_handle_get_check_overflow(handle); mutex_unlock(&client->lock); goto end; } @@ -1244,6 +1561,11 @@ } buffer = dmabuf->priv; + if (get_secure_vmid(buffer->flags) > 0) { + pr_err("%s: cannot sync a secure dmabuf\n", __func__); + dma_buf_put(dmabuf); + return -EINVAL; + } dma_sync_sg_for_device(NULL, buffer->sg_table->sgl, buffer->sg_table->nents, DMA_BIDIRECTIONAL); dma_buf_put(dmabuf); @@ -1292,13 +1614,13 @@ { struct ion_handle *handle; - handle = ion_alloc(client, data.allocation.len, + handle = __ion_alloc(client, data.allocation.len, data.allocation.align, data.allocation.heap_id_mask, - data.allocation.flags); + data.allocation.flags, true); if (IS_ERR(handle)) return PTR_ERR(handle); - + pass_to_user(handle); data.allocation.handle = handle->id; cleanup_handle = handle; @@ -1314,7 +1636,7 @@ mutex_unlock(&client->lock); return PTR_ERR(handle); } - ion_free_nolock(client, handle); + user_ion_free_nolock(client, handle); ion_handle_put_nolock(handle); mutex_unlock(&client->lock); break; @@ -1338,10 +1660,15 @@ struct ion_handle *handle; handle = ion_import_dma_buf(client, data.fd.fd); + if (IS_ERR(handle)) { + ret = PTR_ERR(handle); + } else { + handle = pass_to_user(handle); if (IS_ERR(handle)) ret = PTR_ERR(handle); else data.handle.handle = handle->id; + } break; } case ION_IOC_SYNC: @@ -1357,17 +1684,32 @@ data.custom.arg); break; } + case ION_IOC_CLEAN_CACHES: + return client->dev->custom_ioctl(client, + ION_IOC_CLEAN_CACHES, arg); + case ION_IOC_INV_CACHES: + return client->dev->custom_ioctl(client, + ION_IOC_INV_CACHES, arg); + case ION_IOC_CLEAN_INV_CACHES: + return client->dev->custom_ioctl(client, + ION_IOC_CLEAN_INV_CACHES, arg); default: return -ENOTTY; } if (dir & _IOC_READ) { if (copy_to_user((void __user *)arg, &data, _IOC_SIZE(cmd))) { - if (cleanup_handle) - ion_free(client, cleanup_handle); + if (cleanup_handle) { + mutex_lock(&client->lock); + user_ion_free_nolock(client, cleanup_handle); + ion_handle_put_nolock(cleanup_handle); + mutex_unlock(&client->lock); + } return -EFAULT; } } + if (cleanup_handle) + ion_handle_put(cleanup_handle); return ret; } @@ -1423,6 +1765,106 @@ return size; } +/** + * Create a mem_map of the heap. + * @param s seq_file to log error message to. + * @param heap The heap to create mem_map for. + * @param mem_map The mem map to be created. + */ +void ion_debug_mem_map_create(struct seq_file *s, struct ion_heap *heap, + struct list_head *mem_map) +{ + struct ion_device *dev = heap->dev; + struct rb_node *cnode; + size_t size; + struct ion_client *client; + + if (!heap->ops->phys) + return; + + down_read(&dev->lock); + for (cnode = rb_first(&dev->clients); cnode; cnode = rb_next(cnode)) { + struct rb_node *hnode; + client = rb_entry(cnode, struct ion_client, node); + + mutex_lock(&client->lock); + for (hnode = rb_first(&client->handles); + hnode; + hnode = rb_next(hnode)) { + struct ion_handle *handle = rb_entry( + hnode, struct ion_handle, node); + if (handle->buffer->heap == heap) { + struct mem_map_data *data = + kzalloc(sizeof(*data), GFP_KERNEL); + if (!data) + goto inner_error; + heap->ops->phys(heap, handle->buffer, + &(data->addr), &size); + data->size = (unsigned long) size; + data->addr_end = data->addr + data->size - 1; + data->client_name = kstrdup(client->name, + GFP_KERNEL); + if (!data->client_name) { + kfree(data); + goto inner_error; + } + list_add(&data->node, mem_map); + } + } + mutex_unlock(&client->lock); + } + up_read(&dev->lock); + return; + +inner_error: + seq_puts(s, + "ERROR: out of memory. Part of memory map will not be logged\n"); + mutex_unlock(&client->lock); + up_read(&dev->lock); +} + +/** + * Free the memory allocated by ion_debug_mem_map_create + * @param mem_map The mem map to free. + */ +static void ion_debug_mem_map_destroy(struct list_head *mem_map) +{ + if (mem_map) { + struct mem_map_data *data, *tmp; + list_for_each_entry_safe(data, tmp, mem_map, node) { + list_del(&data->node); + kfree(data->client_name); + kfree(data); + } + } +} + +static int mem_map_cmp(void *priv, struct list_head *a, struct list_head *b) +{ + struct mem_map_data *d1, *d2; + d1 = list_entry(a, struct mem_map_data, node); + d2 = list_entry(b, struct mem_map_data, node); + if (d1->addr == d2->addr) + return d1->size - d2->size; + return d1->addr - d2->addr; +} + +/** + * Print heap debug information. + * @param s seq_file to log message to. + * @param heap pointer to heap that we will print debug information for. + */ +static void ion_heap_print_debug(struct seq_file *s, struct ion_heap *heap) +{ + if (heap->ops->print_debug) { + struct list_head mem_map = LIST_HEAD_INIT(mem_map); + ion_debug_mem_map_create(s, heap, &mem_map); + list_sort(NULL, &mem_map, mem_map_cmp); + heap->ops->print_debug(heap, s, &mem_map); + ion_debug_mem_map_destroy(&mem_map); + } +} + static int ion_debug_heap_show(struct seq_file *s, void *unused) { struct ion_heap *heap = s->private; @@ -1434,6 +1876,7 @@ seq_printf(s, "%16s %16s %16s\n", "client", "pid", "size"); seq_puts(s, "----------------------------------------------------\n"); + mutex_lock(&debugfs_mutex); for (n = rb_first(&dev->clients); n; n = rb_next(n)) { struct ion_client *client = rb_entry(n, struct ion_client, node); @@ -1452,6 +1895,8 @@ client->pid, size); } } + mutex_unlock(&debugfs_mutex); + seq_puts(s, "----------------------------------------------------\n"); seq_puts(s, "orphaned allocations (info is from last known client):\n"); mutex_lock(&dev->buffer_lock); @@ -1482,6 +1927,7 @@ if (heap->debug_show) heap->debug_show(heap, s, unused); + ion_heap_print_debug(s, heap); return 0; } @@ -1497,6 +1943,31 @@ .release = single_release, }; +void show_ion_usage(struct ion_device *dev) +{ + struct ion_heap *heap; + + if (!down_read_trylock(&dev->lock)) { + pr_err("Ion output would deadlock, can't print debug information\n"); + return; + } + + pr_info("%16.s %16.s %16.s\n", "Heap name", "Total heap size", + "Total orphaned size"); + pr_info("---------------------------------\n"); + plist_for_each_entry(heap, &dev->heaps, node) { + pr_info("%16.s 0x%16.lx 0x%16.lx\n", + heap->name, atomic_long_read(&heap->total_allocated), + atomic_long_read(&heap->total_allocated) - + atomic_long_read(&heap->total_handles)); + if (heap->debug_show) + heap->debug_show(heap, NULL, 0); + + } + up_read(&dev->lock); +} + +#ifdef DEBUG_HEAP_SHRINKER static int debug_shrink_set(void *data, u64 val) { struct ion_heap *heap = data; @@ -1531,6 +2002,7 @@ DEFINE_SIMPLE_ATTRIBUTE(debug_shrink_fops, debug_shrink_get, debug_shrink_set, "%llu\n"); +#endif void ion_device_add_heap(struct ion_device *dev, struct ion_heap *heap) { @@ -1570,6 +2042,7 @@ path, heap->name); } +#ifdef DEBUG_HEAP_SHRINKER if (heap->shrinker.count_objects && heap->shrinker.scan_objects) { char debug_name[64]; @@ -1585,11 +2058,36 @@ path, debug_name); } } +#endif up_write(&dev->lock); } EXPORT_SYMBOL(ion_device_add_heap); +int ion_walk_heaps(struct ion_client *client, int heap_id, + enum ion_heap_type type, void *data, + int (*f)(struct ion_heap *heap, void *data)) +{ + int ret_val = 0; + struct ion_heap *heap; + struct ion_device *dev = client->dev; + /* + * traverse the list of heaps available in this system + * and find the heap that is specified. + */ + down_write(&dev->lock); + plist_for_each_entry(heap, &dev->heaps, node) { + if (ION_HEAP(heap->id) != heap_id || + type != heap->type) + continue; + ret_val = f(heap, data); + break; + } + up_write(&dev->lock); + return ret_val; +} +EXPORT_SYMBOL(ion_walk_heaps); + struct ion_device *ion_device_create(long (*custom_ioctl) (struct ion_client *client, unsigned int cmd, @@ -1636,6 +2134,8 @@ init_rwsem(&idev->lock); plist_head_init(&idev->heaps); idev->clients = RB_ROOT; + ion_root_client = &idev->clients; + mutex_init(&debugfs_mutex); return idev; } EXPORT_SYMBOL(ion_device_create); @@ -1673,13 +2173,13 @@ int ret = memblock_reserve(data->heaps[i].base, data->heaps[i].size); if (ret) - pr_err("memblock reserve of %zx@%lx failed\n", + pr_err("memblock reserve of %zx@%pa failed\n", data->heaps[i].size, - data->heaps[i].base); + &data->heaps[i].base); } - pr_info("%s: %s reserved base %lx size %zu\n", __func__, + pr_info("%s: %s reserved base %pa size %zu\n", __func__, data->heaps[i].name, - data->heaps[i].base, + &data->heaps[i].base, data->heaps[i].size); } } diff -ruw linux-4.4.115/drivers/staging/android/ion/ion_carveout_heap.c linux-4.4.115-fbx/drivers/staging/android/ion/ion_carveout_heap.c --- linux-4.4.115/drivers/staging/android/ion/ion_carveout_heap.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/staging/android/ion/ion_carveout_heap.c 2019-01-22 16:16:26.711275457 +0100 @@ -111,12 +111,14 @@ struct ion_heap *heap = buffer->heap; struct sg_table *table = buffer->priv_virt; struct page *page = sg_page(table->sgl); + struct device *dev = heap->priv; + ion_phys_addr_t paddr = PFN_PHYS(page_to_pfn(page)); ion_heap_buffer_zero(buffer); if (ion_buffer_cached(buffer)) - dma_sync_sg_for_device(NULL, table->sgl, table->nents, + dma_sync_sg_for_device(dev, table->sgl, table->nents, DMA_BIDIRECTIONAL); ion_carveout_free(heap, paddr, buffer->size); @@ -153,11 +155,12 @@ struct page *page; size_t size; + struct device *dev = heap_data->priv; page = pfn_to_page(PFN_DOWN(heap_data->base)); size = heap_data->size; - ion_pages_sync_for_device(NULL, page, size, DMA_BIDIRECTIONAL); + ion_pages_sync_for_device(dev, page, size, DMA_BIDIRECTIONAL); ret = ion_heap_pages_zero(page, size, pgprot_writecombine(PAGE_KERNEL)); if (ret) @@ -167,7 +170,7 @@ if (!carveout_heap) return ERR_PTR(-ENOMEM); - carveout_heap->pool = gen_pool_create(12, -1); + carveout_heap->pool = gen_pool_create(PAGE_SHIFT, -1); if (!carveout_heap->pool) { kfree(carveout_heap); return ERR_PTR(-ENOMEM); diff -ruw linux-4.4.115/drivers/staging/android/ion/ion_chunk_heap.c linux-4.4.115-fbx/drivers/staging/android/ion/ion_chunk_heap.c --- linux-4.4.115/drivers/staging/android/ion/ion_chunk_heap.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/staging/android/ion/ion_chunk_heap.c 2019-01-22 16:16:26.711275457 +0100 @@ -99,13 +99,14 @@ struct scatterlist *sg; int i; unsigned long allocated_size; + struct device *dev = heap->priv; allocated_size = ALIGN(buffer->size, chunk_heap->chunk_size); ion_heap_buffer_zero(buffer); if (ion_buffer_cached(buffer)) - dma_sync_sg_for_device(NULL, table->sgl, table->nents, + dma_sync_sg_for_device(dev, table->sgl, table->nents, DMA_BIDIRECTIONAL); for_each_sg(table->sgl, sg, table->nents, i) { @@ -144,11 +145,12 @@ int ret; struct page *page; size_t size; + struct device *dev = heap_data->priv; page = pfn_to_page(PFN_DOWN(heap_data->base)); size = heap_data->size; - ion_pages_sync_for_device(NULL, page, size, DMA_BIDIRECTIONAL); + ion_pages_sync_for_device(dev, page, size, DMA_BIDIRECTIONAL); ret = ion_heap_pages_zero(page, size, pgprot_writecombine(PAGE_KERNEL)); if (ret) @@ -173,8 +175,8 @@ chunk_heap->heap.ops = &chunk_heap_ops; chunk_heap->heap.type = ION_HEAP_TYPE_CHUNK; chunk_heap->heap.flags = ION_HEAP_FLAG_DEFER_FREE; - pr_debug("%s: base %lu size %zu align %ld\n", __func__, - chunk_heap->base, heap_data->size, heap_data->align); + pr_debug("%s: base %pad size %zu align %pad\n", __func__, + &chunk_heap->base, heap_data->size, &heap_data->align); return &chunk_heap->heap; diff -ruw linux-4.4.115/drivers/staging/android/ion/ion_cma_heap.c linux-4.4.115-fbx/drivers/staging/android/ion/ion_cma_heap.c --- linux-4.4.115/drivers/staging/android/ion/ion_cma_heap.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/staging/android/ion/ion_cma_heap.c 2019-10-29 09:26:24.845214941 +0100 @@ -20,49 +20,63 @@ #include #include #include +#include + +#include +#include #include "ion.h" #include "ion_priv.h" #define ION_CMA_ALLOCATE_FAILED -1 -struct ion_cma_heap { - struct ion_heap heap; - struct device *dev; -}; - -#define to_cma_heap(x) container_of(x, struct ion_cma_heap, heap) - struct ion_cma_buffer_info { void *cpu_addr; dma_addr_t handle; struct sg_table *table; + bool is_cached; }; +static int cma_heap_has_outer_cache; +/* + * Create scatter-list for the already allocated DMA buffer. + * This function could be replace by dma_common_get_sgtable + * as soon as it will avalaible. + */ +static int ion_cma_get_sgtable(struct device *dev, struct sg_table *sgt, + void *cpu_addr, dma_addr_t handle, size_t size) +{ + struct page *page = pfn_to_page(PFN_DOWN(handle)); + int ret; + + ret = sg_alloc_table(sgt, 1, GFP_KERNEL); + if (unlikely(ret)) + return ret; + + sg_set_page(sgt->sgl, page, PAGE_ALIGN(size), 0); + return 0; +} /* ION CMA heap operations functions */ static int ion_cma_allocate(struct ion_heap *heap, struct ion_buffer *buffer, unsigned long len, unsigned long align, unsigned long flags) { - struct ion_cma_heap *cma_heap = to_cma_heap(heap); - struct device *dev = cma_heap->dev; + struct device *dev = heap->priv; struct ion_cma_buffer_info *info; dev_dbg(dev, "Request buffer allocation len %ld\n", len); - if (buffer->flags & ION_FLAG_CACHED) - return -EINVAL; - - if (align > PAGE_SIZE) - return -EINVAL; - info = kzalloc(sizeof(struct ion_cma_buffer_info), GFP_KERNEL); if (!info) return ION_CMA_ALLOCATE_FAILED; - info->cpu_addr = dma_alloc_coherent(dev, len, &(info->handle), - GFP_HIGHUSER | __GFP_ZERO); + if (!ION_IS_CACHED(flags)) + info->cpu_addr = dma_alloc_writecombine(dev, len, + &(info->handle), GFP_KERNEL); + else + info->cpu_addr = dma_alloc_nonconsistent(dev, len, + &(info->handle), GFP_KERNEL); if (!info->cpu_addr) { dev_err(dev, "Fail to allocate buffer\n"); @@ -71,20 +85,18 @@ info->table = kmalloc(sizeof(struct sg_table), GFP_KERNEL); if (!info->table) - goto free_mem; + goto err; + + info->is_cached = ION_IS_CACHED(flags); + + ion_cma_get_sgtable(dev, + info->table, info->cpu_addr, info->handle, len); - if (dma_get_sgtable(dev, info->table, info->cpu_addr, info->handle, - len)) - goto free_table; /* keep this for memory release */ buffer->priv_virt = info; - dev_dbg(dev, "Allocate buffer %p\n", buffer); + dev_dbg(dev, "Allocate buffer %pK\n", buffer); return 0; -free_table: - kfree(info->table); -free_mem: - dma_free_coherent(dev, len, info->cpu_addr, info->handle); err: kfree(info); return ION_CMA_ALLOCATE_FAILED; @@ -92,15 +104,14 @@ static void ion_cma_free(struct ion_buffer *buffer) { - struct ion_cma_heap *cma_heap = to_cma_heap(buffer->heap); - struct device *dev = cma_heap->dev; + struct device *dev = buffer->heap->priv; struct ion_cma_buffer_info *info = buffer->priv_virt; - dev_dbg(dev, "Release buffer %p\n", buffer); + dev_dbg(dev, "Release buffer %pK\n", buffer); /* release memory */ dma_free_coherent(dev, buffer->size, info->cpu_addr, info->handle); - /* release sg table */ sg_free_table(info->table); + /* release sg table */ kfree(info->table); kfree(info); } @@ -109,11 +120,10 @@ static int ion_cma_phys(struct ion_heap *heap, struct ion_buffer *buffer, ion_phys_addr_t *addr, size_t *len) { - struct ion_cma_heap *cma_heap = to_cma_heap(buffer->heap); - struct device *dev = cma_heap->dev; + struct device *dev = heap->priv; struct ion_cma_buffer_info *info = buffer->priv_virt; - dev_dbg(dev, "Return buffer %p physical address %pa\n", buffer, + dev_dbg(dev, "Return buffer %pK physical address %pa\n", buffer, &info->handle); *addr = info->handle; @@ -138,25 +148,56 @@ static int ion_cma_mmap(struct ion_heap *mapper, struct ion_buffer *buffer, struct vm_area_struct *vma) { - struct ion_cma_heap *cma_heap = to_cma_heap(buffer->heap); - struct device *dev = cma_heap->dev; + struct device *dev = buffer->heap->priv; struct ion_cma_buffer_info *info = buffer->priv_virt; - return dma_mmap_coherent(dev, vma, info->cpu_addr, info->handle, - buffer->size); + if (info->is_cached) + return dma_mmap_nonconsistent(dev, vma, info->cpu_addr, + info->handle, buffer->size); + else + return dma_mmap_writecombine(dev, vma, info->cpu_addr, + info->handle, buffer->size); } static void *ion_cma_map_kernel(struct ion_heap *heap, struct ion_buffer *buffer) { struct ion_cma_buffer_info *info = buffer->priv_virt; - /* kernel memory mapping has been done at allocation time */ + return info->cpu_addr; } static void ion_cma_unmap_kernel(struct ion_heap *heap, struct ion_buffer *buffer) { + return; +} + +static int ion_cma_print_debug(struct ion_heap *heap, struct seq_file *s, + const struct list_head *mem_map) +{ + if (mem_map) { + struct mem_map_data *data; + + seq_printf(s, "\nMemory Map\n"); + seq_printf(s, "%16.s %14.s %14.s %14.s\n", + "client", "start address", "end address", + "size"); + + list_for_each_entry(data, mem_map, node) { + const char *client_name = "(null)"; + + + if (data->client_name) + client_name = data->client_name; + + seq_printf(s, "%16.s 0x%14pa 0x%14pa %14lu (0x%lx)\n", + client_name, &data->addr, + &data->addr_end, + data->size, data->size); + } + } + return 0; } static struct ion_heap_ops ion_cma_ops = { @@ -168,30 +209,147 @@ .map_user = ion_cma_mmap, .map_kernel = ion_cma_map_kernel, .unmap_kernel = ion_cma_unmap_kernel, + .print_debug = ion_cma_print_debug, }; struct ion_heap *ion_cma_heap_create(struct ion_platform_heap *data) { - struct ion_cma_heap *cma_heap; + struct ion_heap *heap; - cma_heap = kzalloc(sizeof(struct ion_cma_heap), GFP_KERNEL); + heap = kzalloc(sizeof(struct ion_heap), GFP_KERNEL); - if (!cma_heap) + if (!heap) return ERR_PTR(-ENOMEM); - cma_heap->heap.ops = &ion_cma_ops; + heap->ops = &ion_cma_ops; + /* set device as private heaps data, later it will be + * used to make the link with reserved CMA memory */ + heap->priv = data->priv; + heap->type = ION_HEAP_TYPE_DMA; + cma_heap_has_outer_cache = data->has_outer_cache; + return heap; +} + +void ion_cma_heap_destroy(struct ion_heap *heap) +{ + kfree(heap); +} + +static void ion_secure_cma_free(struct ion_buffer *buffer) +{ + int i, ret = 0; + int source_vm; + int dest_vmid; + int dest_perms; + struct sg_table *sgt; + struct scatterlist *sg; + struct ion_cma_buffer_info *info = buffer->priv_virt; + + source_vm = get_secure_vmid(buffer->flags); + if (source_vm < 0) { + pr_err("%s: Failed to get secure vmid\n", __func__); + return; + } + dest_vmid = VMID_HLOS; + dest_perms = PERM_READ | PERM_WRITE | PERM_EXEC; + + sgt = info->table; + ret = hyp_assign_table(sgt, &source_vm, 1, &dest_vmid, &dest_perms, 1); + if (ret) { + pr_err("%s: Not freeing memory since assign failed\n", + __func__); + return; + } + + for_each_sg(sgt->sgl, sg, sgt->nents, i) + ClearPagePrivate(sg_page(sg)); + + ion_cma_free(buffer); +} + +static int ion_secure_cma_allocate(struct ion_heap *heap, + struct ion_buffer *buffer, unsigned long len, + unsigned long align, unsigned long flags) +{ + int i, ret = 0; + int source_vm; + int dest_vm; + int dest_perms; + struct ion_cma_buffer_info *info; + struct sg_table *sgt; + struct scatterlist *sg; + + source_vm = VMID_HLOS; + dest_vm = get_secure_vmid(flags); + + if (dest_vm < 0) { + pr_err("%s: Failed to get secure vmid\n", __func__); + return -EINVAL; + } + + if (dest_vm == VMID_CP_SEC_DISPLAY) + dest_perms = PERM_READ; + else + dest_perms = PERM_READ | PERM_WRITE; + + ret = ion_cma_allocate(heap, buffer, len, align, flags); + if (ret) { + dev_err(heap->priv, "Unable to allocate cma buffer"); + return ret; + } + + info = buffer->priv_virt; + sgt = info->table; + ret = hyp_assign_table(sgt, &source_vm, 1, &dest_vm, &dest_perms, 1); + if (ret) { + pr_err("%s: Assign call failed\n", __func__); + goto err; + } + + /* Set the private bit to indicate that we've secured this */ + for_each_sg(sgt->sgl, sg, sgt->nents, i) + SetPagePrivate(sg_page(sg)); + + return ret; + +err: + ion_secure_cma_free(buffer); + return ret; +} + +static struct ion_heap_ops ion_secure_cma_ops = { + .allocate = ion_secure_cma_allocate, + .free = ion_secure_cma_free, + .map_dma = ion_cma_heap_map_dma, + .unmap_dma = ion_cma_heap_unmap_dma, + .phys = ion_cma_phys, + .map_user = ion_cma_mmap, + .map_kernel = ion_cma_map_kernel, + .unmap_kernel = ion_cma_unmap_kernel, + .print_debug = ion_cma_print_debug, +}; + +struct ion_heap *ion_cma_secure_heap_create(struct ion_platform_heap *data) +{ + struct ion_heap *heap; + + heap = kzalloc(sizeof(struct ion_heap), GFP_KERNEL); + + if (!heap) + return ERR_PTR(-ENOMEM); + + heap->ops = &ion_secure_cma_ops; /* - * get device from private heaps data, later it will be + * set device as private heaps data, later it will be * used to make the link with reserved CMA memory */ - cma_heap->dev = data->priv; - cma_heap->heap.type = ION_HEAP_TYPE_DMA; - return &cma_heap->heap; + heap->priv = data->priv; + heap->type = ION_HEAP_TYPE_HYP_CMA; + cma_heap_has_outer_cache = data->has_outer_cache; + return heap; } -void ion_cma_heap_destroy(struct ion_heap *heap) +void ion_cma_secure_heap_destroy(struct ion_heap *heap) { - struct ion_cma_heap *cma_heap = to_cma_heap(heap); - - kfree(cma_heap); + kfree(heap); } diff -ruw linux-4.4.115/drivers/staging/android/ion/ion.h linux-4.4.115-fbx/drivers/staging/android/ion/ion.h --- linux-4.4.115/drivers/staging/android/ion/ion.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/staging/android/ion/ion.h 2019-01-22 16:16:26.711275457 +0100 @@ -2,6 +2,7 @@ * drivers/staging/android/ion/ion.h * * Copyright (C) 2011 Google, Inc. + * Copyright (c) 2011-2014,2017 The Linux Foundation. All rights reserved. * * This software is licensed under the terms of the GNU General Public * License version 2, as published by the Free Software Foundation, and @@ -17,8 +18,7 @@ #ifndef _LINUX_ION_H #define _LINUX_ION_H -#include - +#include #include "../uapi/ion.h" struct ion_handle; @@ -28,13 +28,11 @@ struct ion_client; struct ion_buffer; -/* - * This should be removed some day when phys_addr_t's are fully - * plumbed in the kernel, and all instances of ion_phys_addr_t should - * be converted to phys_addr_t. For the time being many kernel interfaces - * do not accept phys_addr_t's that would have to - */ -#define ion_phys_addr_t unsigned long +/* This should be removed some day when phys_addr_t's are fully + plumbed in the kernel, and all instances of ion_phys_addr_t should + be converted to phys_addr_t. For the time being many kernel interfaces + do not accept phys_addr_t's that would have to */ +#define ion_phys_addr_t dma_addr_t /** * struct ion_platform_heap - defines a heap in the given platform @@ -45,6 +43,9 @@ * @name: used for debug purposes * @base: base address of heap in physical memory if applicable * @size: size of the heap in bytes if applicable + * @has_outer_cache: set to 1 if outer cache is used, 0 otherwise. + * @extra_data: Extra data specific to each heap type + * @priv: heap private data * @align: required alignment in physical memory if applicable * @priv: private info passed from the board file * @@ -56,22 +57,28 @@ const char *name; ion_phys_addr_t base; size_t size; + unsigned int has_outer_cache; + void *extra_data; ion_phys_addr_t align; void *priv; }; /** * struct ion_platform_data - array of platform heaps passed from board file + * @has_outer_cache: set to 1 if outer cache is used, 0 otherwise. * @nr: number of structures in the array * @heaps: array of platform_heap structions * * Provided by the board file in the form of platform data to a platform device. */ struct ion_platform_data { + unsigned int has_outer_cache; int nr; struct ion_platform_heap *heaps; }; +#ifdef CONFIG_ION + /** * ion_reserve() - reserve memory for ion heaps if applicable * @data: platform data specifying starting physical address and @@ -202,4 +209,83 @@ */ struct ion_handle *ion_import_dma_buf(struct ion_client *client, int fd); +/** + * ion_dma_buf_is_secure() - Returns true if the dma buf is secure + * dmabuf + * @dmabuf: pointer to a dma-buf + * + * Given a dma-buf pointer, return true if ion created it and it is from + * a secure heap. + */ +bool ion_dma_buf_is_secure(struct dma_buf *dmabuf); + +#else +static inline void ion_reserve(struct ion_platform_data *data) +{ + +} + +static inline struct ion_client *ion_client_create( + struct ion_device *dev, unsigned int heap_id_mask, const char *name) +{ + return ERR_PTR(-ENODEV); +} + +static inline void ion_client_destroy(struct ion_client *client) { } + +static inline struct ion_handle *ion_alloc(struct ion_client *client, + size_t len, size_t align, + unsigned int heap_id_mask, + unsigned int flags) +{ + return ERR_PTR(-ENODEV); +} + +static inline void ion_free(struct ion_client *client, + struct ion_handle *handle) { } + + +static inline int ion_phys(struct ion_client *client, + struct ion_handle *handle, ion_phys_addr_t *addr, size_t *len) +{ + return -ENODEV; +} + +static inline struct sg_table *ion_sg_table(struct ion_client *client, + struct ion_handle *handle) +{ + return ERR_PTR(-ENODEV); +} + +static inline void *ion_map_kernel(struct ion_client *client, + struct ion_handle *handle) +{ + return ERR_PTR(-ENODEV); +} + +static inline void ion_unmap_kernel(struct ion_client *client, + struct ion_handle *handle) { } + +static inline int ion_share_dma_buf(struct ion_client *client, struct ion_handle *handle) +{ + return -ENODEV; +} + +static inline struct ion_handle *ion_import_dma_buf(struct ion_client *client, int fd) +{ + return ERR_PTR(-ENODEV); +} + +static inline int ion_handle_get_flags(struct ion_client *client, + struct ion_handle *handle, unsigned long *flags) +{ + return -ENODEV; +} + +bool ion_dma_buf_is_secure(struct dma_buf *dmabuf) +{ + return false; +} + +#endif /* CONFIG_ION */ #endif /* _LINUX_ION_H */ diff -ruw linux-4.4.115/drivers/staging/android/ion/ion_heap.c linux-4.4.115-fbx/drivers/staging/android/ion/ion_heap.c --- linux-4.4.115/drivers/staging/android/ion/ion_heap.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/staging/android/ion/ion_heap.c 2019-01-22 16:16:26.715275493 +0100 @@ -2,6 +2,7 @@ * drivers/staging/android/ion/ion_heap.c * * Copyright (C) 2011 Google, Inc. + * Copyright (c) 2011-2016, The Linux Foundation. All rights reserved. * * This software is licensed under the terms of the GNU General Public * License version 2, as published by the Free Software Foundation, and @@ -22,6 +23,9 @@ #include #include #include +#include +#include +#include #include "ion.h" #include "ion_priv.h" @@ -38,7 +42,7 @@ struct page **tmp = pages; if (!pages) - return NULL; + return ERR_PTR(-ENOMEM); if (buffer->flags & ION_FLAG_CACHED) pgprot = PAGE_KERNEL; @@ -321,8 +325,9 @@ switch (heap_data->type) { case ION_HEAP_TYPE_SYSTEM_CONTIG: - heap = ion_system_contig_heap_create(heap_data); - break; + pr_err("%s: Heap type is disabled: %d\n", __func__, + heap_data->type); + return ERR_PTR(-EINVAL); case ION_HEAP_TYPE_SYSTEM: heap = ion_system_heap_create(heap_data); break; @@ -342,14 +347,15 @@ } if (IS_ERR_OR_NULL(heap)) { - pr_err("%s: error creating heap %s type %d base %lu size %zu\n", + pr_err("%s: error creating heap %s type %d base %pa size %zu\n", __func__, heap_data->name, heap_data->type, - heap_data->base, heap_data->size); + &heap_data->base, heap_data->size); return ERR_PTR(-EINVAL); } heap->name = heap_data->name; heap->id = heap_data->id; + heap->priv = heap_data->priv; return heap; } EXPORT_SYMBOL(ion_heap_create); @@ -361,7 +367,8 @@ switch (heap->type) { case ION_HEAP_TYPE_SYSTEM_CONTIG: - ion_system_contig_heap_destroy(heap); + pr_err("%s: Heap type is disabled: %d\n", __func__, + heap->type); break; case ION_HEAP_TYPE_SYSTEM: ion_system_heap_destroy(heap); diff -ruw linux-4.4.115/drivers/staging/android/ion/ion_page_pool.c linux-4.4.115-fbx/drivers/staging/android/ion/ion_page_pool.c --- linux-4.4.115/drivers/staging/android/ion/ion_page_pool.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/staging/android/ion/ion_page_pool.c 2019-01-22 16:16:26.715275493 +0100 @@ -1,5 +1,5 @@ /* - * drivers/staging/android/ion/ion_mem_pool.c + * drivers/staging/android/ion/ion_page_pool.c * * Copyright (C) 2011 Google, Inc. * @@ -22,22 +22,35 @@ #include #include #include +#include #include "ion_priv.h" static void *ion_page_pool_alloc_pages(struct ion_page_pool *pool) { - struct page *page = alloc_pages(pool->gfp_mask, pool->order); + struct page *page; + + page = alloc_pages(pool->gfp_mask & ~__GFP_ZERO, pool->order); if (!page) return NULL; - ion_pages_sync_for_device(NULL, page, PAGE_SIZE << pool->order, - DMA_BIDIRECTIONAL); + + if (pool->gfp_mask & __GFP_ZERO) + if (msm_ion_heap_high_order_page_zero(pool->dev, page, + pool->order)) + goto error_free_pages; + + ion_page_pool_alloc_set_cache_policy(pool, page); + return page; +error_free_pages: + __free_pages(page, pool->order); + return NULL; } static void ion_page_pool_free_pages(struct ion_page_pool *pool, struct page *page) { + ion_page_pool_free_set_cache_policy(pool, page); __free_pages(page, pool->order); } @@ -51,6 +64,9 @@ list_add_tail(&page->lru, &pool->low_items); pool->low_count++; } + + mod_zone_page_state(page_zone(page), NR_INDIRECTLY_RECLAIMABLE_BYTES, + (1 << (PAGE_SHIFT + pool->order))); mutex_unlock(&pool->mutex); return 0; } @@ -70,24 +86,49 @@ } list_del(&page->lru); + mod_zone_page_state(page_zone(page), NR_INDIRECTLY_RECLAIMABLE_BYTES, + -(1 << (PAGE_SHIFT + pool->order))); return page; } -struct page *ion_page_pool_alloc(struct ion_page_pool *pool) +void *ion_page_pool_alloc(struct ion_page_pool *pool, bool *from_pool) { struct page *page = NULL; BUG_ON(!pool); - mutex_lock(&pool->mutex); + *from_pool = true; + + if (mutex_trylock(&pool->mutex)) { if (pool->high_count) page = ion_page_pool_remove(pool, true); else if (pool->low_count) page = ion_page_pool_remove(pool, false); mutex_unlock(&pool->mutex); - - if (!page) + } + if (!page) { page = ion_page_pool_alloc_pages(pool); + *from_pool = false; + } + return page; +} + +/* + * Tries to allocate from only the specified Pool and returns NULL otherwise + */ +void *ion_page_pool_alloc_pool_only(struct ion_page_pool *pool) +{ + struct page *page = NULL; + + BUG_ON(!pool); + + if (mutex_trylock(&pool->mutex)) { + if (pool->high_count) + page = ion_page_pool_remove(pool, true); + else if (pool->low_count) + page = ion_page_pool_remove(pool, false); + mutex_unlock(&pool->mutex); + } return page; } @@ -96,14 +137,17 @@ { int ret; - BUG_ON(pool->order != compound_order(page)); - ret = ion_page_pool_add(pool, page); if (ret) ion_page_pool_free_pages(pool, page); } -static int ion_page_pool_total(struct ion_page_pool *pool, bool high) +void ion_page_pool_free_immediate(struct ion_page_pool *pool, struct page *page) +{ + ion_page_pool_free_pages(pool, page); +} + +int ion_page_pool_total(struct ion_page_pool *pool, bool high) { int count = pool->low_count; @@ -147,17 +191,19 @@ return freed; } -struct ion_page_pool *ion_page_pool_create(gfp_t gfp_mask, unsigned int order) +struct ion_page_pool *ion_page_pool_create(struct device *dev, gfp_t gfp_mask, + unsigned int order) { struct ion_page_pool *pool = kmalloc(sizeof(struct ion_page_pool), GFP_KERNEL); if (!pool) return NULL; + pool->dev = dev; pool->high_count = 0; pool->low_count = 0; INIT_LIST_HEAD(&pool->low_items); INIT_LIST_HEAD(&pool->high_items); - pool->gfp_mask = gfp_mask | __GFP_COMP; + pool->gfp_mask = gfp_mask; pool->order = order; mutex_init(&pool->mutex); plist_node_init(&pool->list, order); diff -ruw linux-4.4.115/drivers/staging/android/ion/ion_priv.h linux-4.4.115-fbx/drivers/staging/android/ion/ion_priv.h --- linux-4.4.115/drivers/staging/android/ion/ion_priv.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/staging/android/ion/ion_priv.h 2019-10-29 09:26:24.845214941 +0100 @@ -2,6 +2,7 @@ * drivers/staging/android/ion/ion_priv.h * * Copyright (C) 2011 Google, Inc. + * Copyright (c) 2011-2017, The Linux Foundation. All rights reserved. * * This software is licensed under the terms of the GNU General Public * License version 2, as published by the Free Software Foundation, and @@ -23,9 +24,16 @@ #include #include #include +#include + +#include "msm_ion_priv.h" #include #include #include +#ifdef CONFIG_ION_POOL_CACHE_POLICY +#include +#endif +#include #include "ion.h" @@ -46,9 +54,12 @@ * an ion_phys_addr_t (and someday a phys_addr_t) * @lock: protects the buffers cnt fields * @kmap_cnt: number of times the buffer is mapped to the kernel - * @vaddr: the kernel mapping if kmap_cnt is not zero - * @dmap_cnt: number of times the buffer is mapped for dma - * @sg_table: the sg table for the buffer if dmap_cnt is not zero + * @vaddr: the kenrel mapping if kmap_cnt is not zero + * @sg_table: the sg table for the buffer. Note that if you need + * an sg_table for this buffer, you should likely be + * using Ion as a DMA Buf exporter and using + * dma_buf_map_attachment rather than trying to use this + * field directly. * @pages: flat array of pages in the buffer -- used by fault * handler and only valid for buffers that are faulted in * @vmas: list of vma's mapping this buffer @@ -76,7 +87,6 @@ struct mutex lock; int kmap_cnt; void *vaddr; - int dmap_cnt; struct sg_table *sg_table; struct page **pages; struct list_head vmas; @@ -90,7 +100,11 @@ /** * struct ion_heap_ops - ops to operate on a given heap * @allocate: allocate memory - * @free: free memory + * @free: free memory. Will be called with + * ION_PRIV_FLAG_SHRINKER_FREE set in buffer flags when + * called from a shrinker. In that case, the pages being + * free'd must be truly free'd back to the system, not put + * in a page pool or otherwise cached. * @phys get physical address of a buffer (only define on * physically contiguous heaps) * @map_dma map the memory for dma to a scatterlist @@ -98,6 +112,7 @@ * @map_kernel map memory to the kernel * @unmap_kernel unmap memory to the kernel * @map_user map memory to userspace + * @unmap_user unmap memory to userspace * * allocate, phys, and map_user return 0 on success, -errno on error. * map_dma and map_kernel return pointer on success, ERR_PTR on @@ -121,6 +136,9 @@ int (*map_user)(struct ion_heap *mapper, struct ion_buffer *buffer, struct vm_area_struct *vma); int (*shrink)(struct ion_heap *heap, gfp_t gfp_mask, int nr_to_scan); + void (*unmap_user) (struct ion_heap *mapper, struct ion_buffer *buffer); + int (*print_debug)(struct ion_heap *heap, struct seq_file *s, + const struct list_head *mem_map); }; /** @@ -151,6 +169,7 @@ * MUST be unique * @name: used for debugging * @shrinker: a shrinker for the heap + * @priv: private heap data * @free_list: free list head if deferred free is used * @free_list_size size of the deferred free list in bytes * @lock: protects the free list @@ -173,6 +192,7 @@ unsigned int id; const char *name; struct shrinker shrinker; + void *priv; struct list_head free_list; size_t free_list_size; spinlock_t free_lock; @@ -180,6 +200,8 @@ struct task_struct *task; int (*debug_show)(struct ion_heap *heap, struct seq_file *, void *); + atomic_long_t total_allocated; + atomic_long_t total_handles; }; /** @@ -223,6 +245,12 @@ */ void ion_device_add_heap(struct ion_device *dev, struct ion_heap *heap); +struct pages_mem { + struct page **pages; + u32 size; + void (*free_fn) (const void *); +}; + /** * some helpers for common operations on buffers using the sg_table * and vaddr fields @@ -234,6 +262,32 @@ int ion_heap_buffer_zero(struct ion_buffer *buffer); int ion_heap_pages_zero(struct page *page, size_t size, pgprot_t pgprot); +int msm_ion_heap_high_order_page_zero(struct device *dev, struct page *page, + int order); +struct ion_heap *get_ion_heap(int heap_id); +int msm_ion_heap_sg_table_zero(struct device *dev, struct sg_table *, + size_t size); +int msm_ion_heap_pages_zero(struct page **pages, int num_pages); +int msm_ion_heap_alloc_pages_mem(struct pages_mem *pages_mem); +void msm_ion_heap_free_pages_mem(struct pages_mem *pages_mem); + +/** + * Functions to help assign/unassign sg_table for System Secure Heap + */ + +int ion_system_secure_heap_unassign_sg(struct sg_table *sgt, int source_vmid); +int ion_system_secure_heap_assign_sg(struct sg_table *sgt, int dest_vmid); + +/** + * ion_heap_init_shrinker + * @heap: the heap + * + * If a heap sets the ION_HEAP_FLAG_DEFER_FREE flag or defines the shrink op + * this function will be called to setup a shrinker to shrink the freelists + * and call the heap's shrink op. + */ +void ion_heap_init_shrinker(struct ion_heap *heap); + /** * ion_heap_init_shrinker * @heap: the heap @@ -276,7 +330,7 @@ size_t ion_heap_freelist_drain(struct ion_heap *heap, size_t size); /** - * ion_heap_freelist_shrink - drain the deferred free + * ion_heap_freelist_drain_from_shrinker - drain the deferred free * list, skipping any heap-specific * pooling or caching mechanisms * @@ -292,10 +346,10 @@ * page pools or otherwise cache the pages. Everything must be * genuinely free'd back to the system. If you're free'ing from a * shrinker you probably want to use this. Note that this relies on - * the heap.ops.free callback honoring the ION_PRIV_FLAG_SHRINKER_FREE - * flag. + * the heap.ops.free callback honoring the + * ION_PRIV_FLAG_SHRINKER_FREE flag. */ -size_t ion_heap_freelist_shrink(struct ion_heap *heap, +size_t ion_heap_freelist_drain_from_shrinker(struct ion_heap *heap, size_t size); /** @@ -324,8 +378,16 @@ struct ion_heap *ion_chunk_heap_create(struct ion_platform_heap *); void ion_chunk_heap_destroy(struct ion_heap *); +#ifdef CONFIG_CMA struct ion_heap *ion_cma_heap_create(struct ion_platform_heap *); void ion_cma_heap_destroy(struct ion_heap *); +#else +static inline struct ion_heap *ion_cma_heap_create(struct ion_platform_heap *h) +{ + return NULL; +} +static inline void ion_cma_heap_destroy(struct ion_heap *h) {} +#endif /** * kernel api to allocate/free from carveout -- used when carveout is @@ -372,15 +434,51 @@ struct list_head high_items; struct list_head low_items; struct mutex mutex; + struct device *dev; gfp_t gfp_mask; unsigned int order; struct plist_node list; }; -struct ion_page_pool *ion_page_pool_create(gfp_t gfp_mask, unsigned int order); +struct ion_page_pool *ion_page_pool_create(struct device *dev, gfp_t gfp_mask, + unsigned int order); void ion_page_pool_destroy(struct ion_page_pool *); -struct page *ion_page_pool_alloc(struct ion_page_pool *); +void *ion_page_pool_alloc(struct ion_page_pool *, bool *from_pool); +void *ion_page_pool_alloc_pool_only(struct ion_page_pool *); void ion_page_pool_free(struct ion_page_pool *, struct page *); +void ion_page_pool_free_immediate(struct ion_page_pool *, struct page *); +int ion_page_pool_total(struct ion_page_pool *pool, bool high); +size_t ion_system_heap_secure_page_pool_total(struct ion_heap *heap, int vmid); + +#ifdef CONFIG_ION_POOL_CACHE_POLICY +static inline void ion_page_pool_alloc_set_cache_policy + (struct ion_page_pool *pool, + struct page *page){ + void *va = page_address(page); + + if (va) + set_memory_wc((unsigned long)va, 1 << pool->order); +} + +static inline void ion_page_pool_free_set_cache_policy + (struct ion_page_pool *pool, + struct page *page){ + void *va = page_address(page); + + if (va) + set_memory_wb((unsigned long)va, 1 << pool->order); + +} +#else +static inline void ion_page_pool_alloc_set_cache_policy + (struct ion_page_pool *pool, + struct page *page){ } + +static inline void ion_page_pool_free_set_cache_policy + (struct ion_page_pool *pool, + struct page *page){ } +#endif + /** ion_page_pool_shrink - shrinks the size of the memory cached in the pool * @pool: the pool @@ -403,4 +501,13 @@ void ion_pages_sync_for_device(struct device *dev, struct page *page, size_t size, enum dma_data_direction dir); +int ion_walk_heaps(struct ion_client *client, int heap_id, + enum ion_heap_type type, void *data, + int (*f)(struct ion_heap *heap, void *data)); + +struct ion_handle *ion_handle_get_by_id(struct ion_client *client, + int id); + +int ion_handle_put(struct ion_handle *handle); + #endif /* _ION_PRIV_H */ diff -ruw linux-4.4.115/drivers/staging/android/ion/ion_system_heap.c linux-4.4.115-fbx/drivers/staging/android/ion/ion_system_heap.c --- linux-4.4.115/drivers/staging/android/ion/ion_system_heap.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/staging/android/ion/ion_system_heap.c 2019-10-29 09:26:24.845214941 +0100 @@ -2,6 +2,7 @@ * drivers/staging/android/ion/ion_system_heap.c * * Copyright (C) 2011 Google, Inc. + * Copyright (c) 2011-2019, The Linux Foundation. All rights reserved. * * This software is licensed under the terms of the GNU General Public * License version 2, as published by the Free Software Foundation, and @@ -19,22 +20,32 @@ #include #include #include +#include #include #include #include #include #include "ion.h" #include "ion_priv.h" +#include +#include +#include + +static gfp_t high_order_gfp_flags = (GFP_HIGHUSER | __GFP_NOWARN | + __GFP_NORETRY) + & ~__GFP_RECLAIM; +static gfp_t low_order_gfp_flags = (GFP_HIGHUSER | __GFP_NOWARN); + +#ifndef CONFIG_ALLOC_BUFFERS_IN_4K_CHUNKS +static const unsigned int orders[] = {9, 8, 4, 0}; +#else +static const unsigned int orders[] = {0}; +#endif -static gfp_t high_order_gfp_flags = (GFP_HIGHUSER | __GFP_ZERO | __GFP_NOWARN | - __GFP_NORETRY) & ~__GFP_DIRECT_RECLAIM; -static gfp_t low_order_gfp_flags = (GFP_HIGHUSER | __GFP_ZERO | __GFP_NOWARN); -static const unsigned int orders[] = {8, 4, 0}; static const int num_orders = ARRAY_SIZE(orders); static int order_to_index(unsigned int order) { int i; - for (i = 0; i < num_orders; i++) if (order == orders[i]) return i; @@ -42,81 +53,284 @@ return -1; } -static inline unsigned int order_to_size(int order) +static unsigned int order_to_size(int order) { return PAGE_SIZE << order; } struct ion_system_heap { struct ion_heap heap; - struct ion_page_pool *pools[0]; + struct ion_page_pool **uncached_pools; + struct ion_page_pool **cached_pools; + struct ion_page_pool **secure_pools[VMID_LAST]; + /* Prevents unnecessary page splitting */ + struct mutex split_page_mutex; +}; + +struct page_info { + struct page *page; + bool from_pool; + unsigned int order; + struct list_head list; }; +/* + * Used by ion_system_secure_heap only + * Since no lock is held, results are approximate. + */ +size_t ion_system_heap_secure_page_pool_total(struct ion_heap *heap, + int vmid_flags) +{ + struct ion_system_heap *sys_heap; + struct ion_page_pool *pool; + size_t total = 0; + int vmid, i; + + sys_heap = container_of(heap, struct ion_system_heap, heap); + vmid = get_secure_vmid(vmid_flags); + if (!is_secure_vmid_valid(vmid)) + return 0; + + for (i = 0; i < num_orders; i++) { + pool = sys_heap->secure_pools[vmid][i]; + total += ion_page_pool_total(pool, true); + } + + return total << PAGE_SHIFT; +} + static struct page *alloc_buffer_page(struct ion_system_heap *heap, struct ion_buffer *buffer, - unsigned long order) + unsigned long order, + bool *from_pool) { bool cached = ion_buffer_cached(buffer); - struct ion_page_pool *pool = heap->pools[order_to_index(order)]; struct page *page; + struct ion_page_pool *pool; + int vmid = get_secure_vmid(buffer->flags); + struct device *dev = heap->heap.priv; - if (!cached) { - page = ion_page_pool_alloc(pool); - } else { - gfp_t gfp_flags = low_order_gfp_flags; + if (*from_pool) { + if (vmid > 0) + pool = heap->secure_pools[vmid][order_to_index(order)]; + else if (!cached) + pool = heap->uncached_pools[order_to_index(order)]; + else + pool = heap->cached_pools[order_to_index(order)]; - if (order > 4) - gfp_flags = high_order_gfp_flags; - page = alloc_pages(gfp_flags | __GFP_COMP, order); - if (!page) - return NULL; - ion_pages_sync_for_device(NULL, page, PAGE_SIZE << order, + page = ion_page_pool_alloc(pool, from_pool); + } else { + gfp_t gfp_mask = low_order_gfp_flags; + if (order) + gfp_mask = high_order_gfp_flags; + + page = alloc_pages(gfp_mask, order); + if (page) + ion_pages_sync_for_device(dev, page, PAGE_SIZE << order, DMA_BIDIRECTIONAL); } + if (!page) + return 0; return page; } +/* + * For secure pages that need to be freed and not added back to the pool; the + * hyp_unassign should be called before calling this function + */ static void free_buffer_page(struct ion_system_heap *heap, - struct ion_buffer *buffer, struct page *page) + struct ion_buffer *buffer, struct page *page, + unsigned int order) { - unsigned int order = compound_order(page); bool cached = ion_buffer_cached(buffer); + int vmid = get_secure_vmid(buffer->flags); - if (!cached && !(buffer->private_flags & ION_PRIV_FLAG_SHRINKER_FREE)) { - struct ion_page_pool *pool = heap->pools[order_to_index(order)]; - + if (!(buffer->flags & ION_FLAG_POOL_FORCE_ALLOC)) { + struct ion_page_pool *pool; + if (vmid > 0) + pool = heap->secure_pools[vmid][order_to_index(order)]; + else if (cached) + pool = heap->cached_pools[order_to_index(order)]; + else + pool = heap->uncached_pools[order_to_index(order)]; + + if (buffer->private_flags & ION_PRIV_FLAG_SHRINKER_FREE) + ion_page_pool_free_immediate(pool, page); + else ion_page_pool_free(pool, page); } else { __free_pages(page, order); } } +static struct page *alloc_from_secure_pool_order(struct ion_system_heap *heap, + struct ion_buffer *buffer, + unsigned long order) +{ + int vmid = get_secure_vmid(buffer->flags); + struct ion_page_pool *pool; -static struct page *alloc_largest_available(struct ion_system_heap *heap, + if (!is_secure_vmid_valid(vmid)) + return NULL; + + pool = heap->secure_pools[vmid][order_to_index(order)]; + return ion_page_pool_alloc_pool_only(pool); +} + +static struct page *split_page_from_secure_pool(struct ion_system_heap *heap, + struct ion_buffer *buffer) +{ + int i, j; + struct page *page; + unsigned int order; + + mutex_lock(&heap->split_page_mutex); + + /* + * Someone may have just split a page and returned the unused portion + * back to the pool, so try allocating from the pool one more time + * before splitting. We want to maintain large pages sizes when + * possible. + */ + page = alloc_from_secure_pool_order(heap, buffer, 0); + if (page) + goto got_page; + + for (i = num_orders - 2; i >= 0; i--) { + order = orders[i]; + page = alloc_from_secure_pool_order(heap, buffer, order); + if (!page) + continue; + + split_page(page, order); + break; + } + /* + * Return the remaining order-0 pages to the pool. + * SetPagePrivate flag to mark memory as secure. + */ + if (page) { + for (j = 1; j < (1 << order); j++) { + SetPagePrivate(page + j); + free_buffer_page(heap, buffer, page + j, 0); + } + } +got_page: + mutex_unlock(&heap->split_page_mutex); + + return page; +} + +static struct page_info *alloc_largest_available(struct ion_system_heap *heap, struct ion_buffer *buffer, unsigned long size, unsigned int max_order) { struct page *page; + struct page_info *info; int i; + bool from_pool; + + info = kmalloc(sizeof(struct page_info), GFP_KERNEL); + if (!info) + return NULL; for (i = 0; i < num_orders; i++) { if (size < order_to_size(orders[i])) continue; if (max_order < orders[i]) continue; - - page = alloc_buffer_page(heap, buffer, orders[i]); + from_pool = !(buffer->flags & ION_FLAG_POOL_FORCE_ALLOC); + page = alloc_buffer_page(heap, buffer, orders[i], &from_pool); if (!page) continue; - return page; + info->page = page; + info->order = orders[i]; + info->from_pool = from_pool; + INIT_LIST_HEAD(&info->list); + return info; } + kfree(info); return NULL; } +static struct page_info *alloc_from_pool_preferred( + struct ion_system_heap *heap, struct ion_buffer *buffer, + unsigned long size, unsigned int max_order) +{ + struct page *page; + struct page_info *info; + int i; + + if (buffer->flags & ION_FLAG_POOL_FORCE_ALLOC) + goto force_alloc; + + info = kmalloc(sizeof(*info), GFP_KERNEL); + if (!info) + return NULL; + + for (i = 0; i < num_orders; i++) { + if (size < order_to_size(orders[i])) + continue; + if (max_order < orders[i]) + continue; + + page = alloc_from_secure_pool_order(heap, buffer, orders[i]); + if (!page) + continue; + + info->page = page; + info->order = orders[i]; + info->from_pool = true; + INIT_LIST_HEAD(&info->list); + return info; + } + + page = split_page_from_secure_pool(heap, buffer); + if (page) { + info->page = page; + info->order = 0; + info->from_pool = true; + INIT_LIST_HEAD(&info->list); + return info; + } + + kfree(info); +force_alloc: + return alloc_largest_available(heap, buffer, size, max_order); +} + +static unsigned int process_info(struct page_info *info, + struct scatterlist *sg, + struct scatterlist *sg_sync, + struct pages_mem *data, unsigned int i) +{ + struct page *page = info->page; + unsigned int j; + + if (sg_sync) { + sg_set_page(sg_sync, page, (1 << info->order) * PAGE_SIZE, 0); + sg_dma_address(sg_sync) = page_to_phys(page); + } + sg_set_page(sg, page, (1 << info->order) * PAGE_SIZE, 0); + /* + * This is not correct - sg_dma_address needs a dma_addr_t + * that is valid for the the targeted device, but this works + * on the currently targeted hardware. + */ + sg_dma_address(sg) = page_to_phys(page); + if (data) { + for (j = 0; j < (1 << info->order); ++j) + data->pages[i++] = nth_page(page, j); + } + list_del(&info->list); + kfree(info); + return i; +} + static int ion_system_heap_allocate(struct ion_heap *heap, struct ion_buffer *buffer, unsigned long size, unsigned long align, @@ -126,12 +340,21 @@ struct ion_system_heap, heap); struct sg_table *table; + struct sg_table table_sync; struct scatterlist *sg; + struct scatterlist *sg_sync; + int ret; struct list_head pages; - struct page *page, *tmp_page; + struct list_head pages_from_pool; + struct page_info *info, *tmp_info; int i = 0; + unsigned int nents_sync = 0; unsigned long size_remaining = PAGE_ALIGN(size); unsigned int max_order = orders[0]; + struct pages_mem data; + unsigned int sz; + int vmid = get_secure_vmid(buffer->flags); + struct device *dev = heap->priv; if (align > PAGE_SIZE) return -EINVAL; @@ -139,84 +362,253 @@ if (size / PAGE_SIZE > totalram_pages / 2) return -ENOMEM; + data.size = 0; INIT_LIST_HEAD(&pages); + INIT_LIST_HEAD(&pages_from_pool); + while (size_remaining > 0) { - page = alloc_largest_available(sys_heap, buffer, size_remaining, + if (is_secure_vmid_valid(vmid)) + info = alloc_from_pool_preferred( + sys_heap, buffer, size_remaining, max_order); - if (!page) - goto free_pages; - list_add_tail(&page->lru, &pages); - size_remaining -= PAGE_SIZE << compound_order(page); - max_order = compound_order(page); + else + info = alloc_largest_available( + sys_heap, buffer, size_remaining, + max_order); + + if (!info) + goto err; + + sz = (1 << info->order) * PAGE_SIZE; + + if (info->from_pool) { + list_add_tail(&info->list, &pages_from_pool); + } else { + list_add_tail(&info->list, &pages); + data.size += sz; + ++nents_sync; + } + size_remaining -= sz; + max_order = info->order; i++; } - table = kmalloc(sizeof(struct sg_table), GFP_KERNEL); + + ret = msm_ion_heap_alloc_pages_mem(&data); + + if (ret) + goto err; + + table = kzalloc(sizeof(struct sg_table), GFP_KERNEL); if (!table) - goto free_pages; + goto err_free_data_pages; - if (sg_alloc_table(table, i, GFP_KERNEL)) - goto free_table; + ret = sg_alloc_table(table, i, GFP_KERNEL); + if (ret) + goto err1; + if (nents_sync) { + ret = sg_alloc_table(&table_sync, nents_sync, GFP_KERNEL); + if (ret) + goto err_free_sg; + } + + i = 0; sg = table->sgl; - list_for_each_entry_safe(page, tmp_page, &pages, lru) { - sg_set_page(sg, page, PAGE_SIZE << compound_order(page), 0); + sg_sync = table_sync.sgl; + + /* + * We now have two separate lists. One list contains pages from the + * pool and the other pages from buddy. We want to merge these + * together while preserving the ordering of the pages (higher order + * first). + */ + do { + info = list_first_entry_or_null(&pages, struct page_info, list); + tmp_info = list_first_entry_or_null(&pages_from_pool, + struct page_info, list); + if (info && tmp_info) { + if (info->order >= tmp_info->order) { + i = process_info(info, sg, sg_sync, &data, i); + sg_sync = sg_next(sg_sync); + } else { + i = process_info(tmp_info, sg, 0, 0, i); + } + } else if (info) { + i = process_info(info, sg, sg_sync, &data, i); + sg_sync = sg_next(sg_sync); + } else if (tmp_info) { + i = process_info(tmp_info, sg, 0, 0, i); + } else { + BUG(); + } sg = sg_next(sg); - list_del(&page->lru); + + } while (sg); + + ret = msm_ion_heap_pages_zero(data.pages, data.size >> PAGE_SHIFT); + if (ret) { + pr_err("Unable to zero pages\n"); + goto err_free_sg2; + } + + if (nents_sync) { + dma_sync_sg_for_device(dev, table_sync.sgl, table_sync.nents, + DMA_BIDIRECTIONAL); + if (vmid > 0) { + ret = ion_system_secure_heap_assign_sg(&table_sync, + vmid); + if (ret) + goto err_free_sg2; + } } buffer->priv_virt = table; + if (nents_sync) + sg_free_table(&table_sync); + msm_ion_heap_free_pages_mem(&data); return 0; -free_table: +err_free_sg2: + /* We failed to zero buffers. Bypass pool */ + buffer->private_flags |= ION_PRIV_FLAG_SHRINKER_FREE; + + if (vmid > 0) + ion_system_secure_heap_unassign_sg(table, vmid); + + for_each_sg(table->sgl, sg, table->nents, i) + free_buffer_page(sys_heap, buffer, sg_page(sg), + get_order(sg->length)); + if (nents_sync) + sg_free_table(&table_sync); +err_free_sg: + sg_free_table(table); +err1: kfree(table); -free_pages: - list_for_each_entry_safe(page, tmp_page, &pages, lru) - free_buffer_page(sys_heap, buffer, page); +err_free_data_pages: + msm_ion_heap_free_pages_mem(&data); +err: + list_for_each_entry_safe(info, tmp_info, &pages, list) { + free_buffer_page(sys_heap, buffer, info->page, info->order); + kfree(info); + } + list_for_each_entry_safe(info, tmp_info, &pages_from_pool, list) { + free_buffer_page(sys_heap, buffer, info->page, info->order); + kfree(info); + } return -ENOMEM; } -static void ion_system_heap_free(struct ion_buffer *buffer) +void ion_system_heap_free(struct ion_buffer *buffer) { - struct ion_system_heap *sys_heap = container_of(buffer->heap, + struct ion_heap *heap = buffer->heap; + struct ion_system_heap *sys_heap = container_of(heap, struct ion_system_heap, heap); - struct sg_table *table = buffer->sg_table; - bool cached = ion_buffer_cached(buffer); + struct sg_table *table = buffer->priv_virt; struct scatterlist *sg; + LIST_HEAD(pages); int i; + int vmid = get_secure_vmid(buffer->flags); + struct device *dev = heap->priv; - /* - * uncached pages come from the page pools, zero them before returning - * for security purposes (other allocations are zerod at - * alloc time - */ - if (!cached && !(buffer->private_flags & ION_PRIV_FLAG_SHRINKER_FREE)) - ion_heap_buffer_zero(buffer); + if (!(buffer->private_flags & ION_PRIV_FLAG_SHRINKER_FREE) && + !(buffer->flags & ION_FLAG_POOL_FORCE_ALLOC)) { + if (vmid < 0) + msm_ion_heap_sg_table_zero(dev, table, buffer->size); + } else if (vmid > 0) { + if (ion_system_secure_heap_unassign_sg(table, vmid)) + return; + } for_each_sg(table->sgl, sg, table->nents, i) - free_buffer_page(sys_heap, buffer, sg_page(sg)); + free_buffer_page(sys_heap, buffer, sg_page(sg), + get_order(sg->length)); sg_free_table(table); kfree(table); } -static struct sg_table *ion_system_heap_map_dma(struct ion_heap *heap, +struct sg_table *ion_system_heap_map_dma(struct ion_heap *heap, struct ion_buffer *buffer) { return buffer->priv_virt; } -static void ion_system_heap_unmap_dma(struct ion_heap *heap, +void ion_system_heap_unmap_dma(struct ion_heap *heap, struct ion_buffer *buffer) { } +static int ion_secure_page_pool_shrink( + struct ion_system_heap *sys_heap, + int vmid, int order_idx, int nr_to_scan) +{ + int ret, freed = 0; + int order = orders[order_idx]; + struct page *page, *tmp; + struct sg_table sgt; + struct scatterlist *sg; + struct ion_page_pool *pool = sys_heap->secure_pools[vmid][order_idx]; + LIST_HEAD(pages); + + if (nr_to_scan == 0) + return ion_page_pool_total(pool, true); + + while (freed < nr_to_scan) { + page = ion_page_pool_alloc_pool_only(pool); + if (!page) + break; + list_add(&page->lru, &pages); + freed += (1 << order); + } + + if (!freed) + return freed; + + ret = sg_alloc_table(&sgt, (freed >> order), GFP_KERNEL); + if (ret) + goto out1; + sg = sgt.sgl; + list_for_each_entry(page, &pages, lru) { + sg_set_page(sg, page, (1 << order) * PAGE_SIZE, 0); + sg_dma_address(sg) = page_to_phys(page); + sg = sg_next(sg); + } + + if (ion_system_secure_heap_unassign_sg(&sgt, vmid)) + goto out2; + + list_for_each_entry_safe(page, tmp, &pages, lru) { + list_del(&page->lru); + ion_page_pool_free_immediate(pool, page); + } + + sg_free_table(&sgt); + return freed; + +out1: + /* Restore pages to secure pool */ + list_for_each_entry_safe(page, tmp, &pages, lru) { + list_del(&page->lru); + ion_page_pool_free(pool, page); + } + return 0; +out2: + /* + * The security state of the pages is unknown after a failure; + * They can neither be added back to the secure pool nor buddy system. + */ + sg_free_table(&sgt); + return 0; +} + static int ion_system_heap_shrink(struct ion_heap *heap, gfp_t gfp_mask, int nr_to_scan) { struct ion_system_heap *sys_heap; int nr_total = 0; - int i, nr_freed; + int i, j, nr_freed = 0; int only_scan = 0; + struct ion_page_pool *pool; sys_heap = container_of(heap, struct ion_system_heap, heap); @@ -224,9 +616,19 @@ only_scan = 1; for (i = 0; i < num_orders; i++) { - struct ion_page_pool *pool = sys_heap->pools[i]; + nr_freed = 0; + + for (j = 0; j < VMID_LAST; j++) { + if (is_secure_vmid_valid(j)) + nr_freed += ion_secure_page_pool_shrink( + sys_heap, j, i, nr_to_scan); + } + + pool = sys_heap->uncached_pools[i]; + nr_freed += ion_page_pool_shrink(pool, gfp_mask, nr_to_scan); - nr_freed = ion_page_pool_shrink(pool, gfp_mask, nr_to_scan); + pool = sys_heap->cached_pools[i]; + nr_freed += ion_page_pool_shrink(pool, gfp_mask, nr_to_scan); nr_total += nr_freed; if (!only_scan) { @@ -258,53 +660,196 @@ struct ion_system_heap *sys_heap = container_of(heap, struct ion_system_heap, heap); - int i; + bool use_seq = s != NULL; + unsigned long uncached_total = 0; + unsigned long cached_total = 0; + unsigned long secure_total = 0; + struct ion_page_pool *pool; + int i, j; for (i = 0; i < num_orders; i++) { - struct ion_page_pool *pool = sys_heap->pools[i]; + pool = sys_heap->uncached_pools[i]; + if (use_seq) { + seq_printf(s, + "%d order %u highmem pages in uncached pool = %lu total\n", + pool->high_count, pool->order, + (1 << pool->order) * PAGE_SIZE * + pool->high_count); + seq_printf(s, + "%d order %u lowmem pages in uncached pool = %lu total\n", + pool->low_count, pool->order, + (1 << pool->order) * PAGE_SIZE * + pool->low_count); + } + + uncached_total += (1 << pool->order) * PAGE_SIZE * + pool->high_count; + uncached_total += (1 << pool->order) * PAGE_SIZE * + pool->low_count; + } - seq_printf(s, "%d order %u highmem pages in pool = %lu total\n", + for (i = 0; i < num_orders; i++) { + pool = sys_heap->cached_pools[i]; + if (use_seq) { + seq_printf(s, + "%d order %u highmem pages in cached pool = %lu total\n", pool->high_count, pool->order, - (PAGE_SIZE << pool->order) * pool->high_count); - seq_printf(s, "%d order %u lowmem pages in pool = %lu total\n", + (1 << pool->order) * PAGE_SIZE * pool->high_count); + seq_printf(s, + "%d order %u lowmem pages in cached pool = %lu total\n", pool->low_count, pool->order, - (PAGE_SIZE << pool->order) * pool->low_count); + (1 << pool->order) * PAGE_SIZE * + pool->low_count); + } + + cached_total += (1 << pool->order) * PAGE_SIZE * + pool->high_count; + cached_total += (1 << pool->order) * PAGE_SIZE * + pool->low_count; + } + + for (i = 0; i < num_orders; i++) { + for (j = 0; j < VMID_LAST; j++) { + if (!is_secure_vmid_valid(j)) + continue; + pool = sys_heap->secure_pools[j][i]; + + if (use_seq) { + seq_printf(s, + "VMID %d: %d order %u highmem pages in secure pool = %lu total\n", + j, pool->high_count, pool->order, + (1 << pool->order) * PAGE_SIZE * + pool->high_count); + seq_printf(s, + "VMID %d: %d order %u lowmem pages in secure pool = %lu total\n", + j, pool->low_count, pool->order, + (1 << pool->order) * PAGE_SIZE * + pool->low_count); + } + + secure_total += (1 << pool->order) * PAGE_SIZE * + pool->high_count; + secure_total += (1 << pool->order) * PAGE_SIZE * + pool->low_count; + } + } + + if (use_seq) { + seq_puts(s, "--------------------------------------------\n"); + seq_printf(s, "uncached pool = %lu cached pool = %lu secure pool = %lu\n", + uncached_total, cached_total, secure_total); + seq_printf(s, "pool total (uncached + cached + secure) = %lu\n", + uncached_total + cached_total + secure_total); + seq_puts(s, "--------------------------------------------\n"); + } else { + pr_info("-------------------------------------------------\n"); + pr_info("uncached pool = %lu cached pool = %lu secure pool = %lu\n", + uncached_total, cached_total, secure_total); + pr_info("pool total (uncached + cached + secure) = %lu\n", + uncached_total + cached_total + secure_total); + pr_info("-------------------------------------------------\n"); + } + + return 0; +} + + +static void ion_system_heap_destroy_pools(struct ion_page_pool **pools) +{ + int i; + for (i = 0; i < num_orders; i++) + if (pools[i]) { + ion_page_pool_destroy(pools[i]); + pools[i] = NULL; + } +} + +/** + * ion_system_heap_create_pools - Creates pools for all orders + * + * If this fails you don't need to destroy any pools. It's all or + * nothing. If it succeeds you'll eventually need to use + * ion_system_heap_destroy_pools to destroy the pools. + */ +static int ion_system_heap_create_pools(struct device *dev, + struct ion_page_pool **pools) +{ + int i; + for (i = 0; i < num_orders; i++) { + struct ion_page_pool *pool; + gfp_t gfp_flags = low_order_gfp_flags; + + if (orders[i]) + gfp_flags = high_order_gfp_flags; + pool = ion_page_pool_create(dev, gfp_flags, orders[i]); + if (!pool) + goto err_create_pool; + pools[i] = pool; } return 0; +err_create_pool: + ion_system_heap_destroy_pools(pools); + return 1; } -struct ion_heap *ion_system_heap_create(struct ion_platform_heap *unused) +struct ion_heap *ion_system_heap_create(struct ion_platform_heap *data) { struct ion_system_heap *heap; int i; + int pools_size = sizeof(struct ion_page_pool *) * num_orders; + struct device *dev = data->priv; - heap = kzalloc(sizeof(struct ion_system_heap) + - sizeof(struct ion_page_pool *) * num_orders, - GFP_KERNEL); + heap = kzalloc(sizeof(struct ion_system_heap), GFP_KERNEL); if (!heap) return ERR_PTR(-ENOMEM); heap->heap.ops = &system_heap_ops; heap->heap.type = ION_HEAP_TYPE_SYSTEM; heap->heap.flags = ION_HEAP_FLAG_DEFER_FREE; - for (i = 0; i < num_orders; i++) { - struct ion_page_pool *pool; - gfp_t gfp_flags = low_order_gfp_flags; + heap->uncached_pools = kzalloc(pools_size, GFP_KERNEL); + if (!heap->uncached_pools) + goto err_alloc_uncached_pools; - if (orders[i] > 4) - gfp_flags = high_order_gfp_flags; - pool = ion_page_pool_create(gfp_flags, orders[i]); - if (!pool) - goto destroy_pools; - heap->pools[i] = pool; + heap->cached_pools = kzalloc(pools_size, GFP_KERNEL); + if (!heap->cached_pools) + goto err_alloc_cached_pools; + + for (i = 0; i < VMID_LAST; i++) { + if (is_secure_vmid_valid(i)) { + heap->secure_pools[i] = kzalloc(pools_size, GFP_KERNEL); + if (!heap->secure_pools[i]) + goto err_create_secure_pools; + if (ion_system_heap_create_pools( + dev, heap->secure_pools[i])) + goto err_create_secure_pools; } + } + + if (ion_system_heap_create_pools(dev, heap->uncached_pools)) + goto err_create_uncached_pools; + + if (ion_system_heap_create_pools(dev, heap->cached_pools)) + goto err_create_cached_pools; + + mutex_init(&heap->split_page_mutex); heap->heap.debug_show = ion_system_heap_debug_show; return &heap->heap; -destroy_pools: - while (i--) - ion_page_pool_destroy(heap->pools[i]); +err_create_cached_pools: + ion_system_heap_destroy_pools(heap->uncached_pools); +err_create_uncached_pools: + kfree(heap->cached_pools); +err_create_secure_pools: + for (i = 0; i < VMID_LAST; i++) { + if (heap->secure_pools[i]) { + ion_system_heap_destroy_pools(heap->secure_pools[i]); + kfree(heap->secure_pools[i]); + } + } +err_alloc_cached_pools: + kfree(heap->uncached_pools); +err_alloc_uncached_pools: kfree(heap); return ERR_PTR(-ENOMEM); } @@ -314,10 +859,20 @@ struct ion_system_heap *sys_heap = container_of(heap, struct ion_system_heap, heap); - int i; + int i, j; - for (i = 0; i < num_orders; i++) - ion_page_pool_destroy(sys_heap->pools[i]); + for (i = 0; i < VMID_LAST; i++) { + if (!is_secure_vmid_valid(i)) + continue; + for (j = 0; j < num_orders; j++) + ion_secure_page_pool_shrink(sys_heap, i, j, UINT_MAX); + + ion_system_heap_destroy_pools(sys_heap->secure_pools[i]); + } + ion_system_heap_destroy_pools(sys_heap->uncached_pools); + ion_system_heap_destroy_pools(sys_heap->cached_pools); + kfree(sys_heap->uncached_pools); + kfree(sys_heap->cached_pools); kfree(sys_heap); } @@ -332,11 +887,12 @@ struct sg_table *table; unsigned long i; int ret; + struct device *dev = heap->priv; if (align > (PAGE_SIZE << order)) return -EINVAL; - page = alloc_pages(low_order_gfp_flags, order); + page = alloc_pages(low_order_gfp_flags | __GFP_ZERO, order); if (!page) return -ENOMEM; @@ -346,34 +902,32 @@ for (i = len >> PAGE_SHIFT; i < (1 << order); i++) __free_page(page + i); - table = kmalloc(sizeof(struct sg_table), GFP_KERNEL); + table = kzalloc(sizeof(struct sg_table), GFP_KERNEL); if (!table) { ret = -ENOMEM; - goto free_pages; + goto out; } ret = sg_alloc_table(table, 1, GFP_KERNEL); if (ret) - goto free_table; + goto out; sg_set_page(table->sgl, page, len, 0); buffer->priv_virt = table; - ion_pages_sync_for_device(NULL, page, len, DMA_BIDIRECTIONAL); + ion_pages_sync_for_device(dev, page, len, DMA_BIDIRECTIONAL); return 0; -free_table: - kfree(table); -free_pages: +out: for (i = 0; i < len >> PAGE_SHIFT; i++) __free_page(page + i); - + kfree(table); return ret; } -static void ion_system_contig_heap_free(struct ion_buffer *buffer) +void ion_system_contig_heap_free(struct ion_buffer *buffer) { struct sg_table *table = buffer->priv_virt; struct page *page = sg_page(table->sgl); @@ -397,13 +951,13 @@ return 0; } -static struct sg_table *ion_system_contig_heap_map_dma(struct ion_heap *heap, +struct sg_table *ion_system_contig_heap_map_dma(struct ion_heap *heap, struct ion_buffer *buffer) { return buffer->priv_virt; } -static void ion_system_contig_heap_unmap_dma(struct ion_heap *heap, +void ion_system_contig_heap_unmap_dma(struct ion_heap *heap, struct ion_buffer *buffer) { } diff -ruw linux-4.4.115/drivers/staging/android/ion/Kconfig linux-4.4.115-fbx/drivers/staging/android/ion/Kconfig --- linux-4.4.115/drivers/staging/android/ion/Kconfig 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/staging/android/ion/Kconfig 2019-01-22 16:16:26.711275457 +0100 @@ -33,3 +33,24 @@ help Choose this option if you wish to use ion on an nVidia Tegra. +config ION_POOL_CACHE_POLICY + bool "Ion set page pool cache policy" + depends on ION && X86 + default y if X86 + help + Choose this option if need to explicity set cache policy of the + pages in the page pool. + +config ION_MSM + tristate "Ion for MSM" + depends on ARCH_QCOM && ION + select MSM_SECURE_BUFFER + help + Choose this option if you wish to use ion on an MSM target. + +config ALLOC_BUFFERS_IN_4K_CHUNKS + bool "Turns off allocation optimization and allocate only 4K pages" + depends on ARCH_QCOM && ION + help + Choose this option if you want ION to allocate buffers in + only 4KB chunks. diff -ruw linux-4.4.115/drivers/staging/android/ion/Makefile linux-4.4.115-fbx/drivers/staging/android/ion/Makefile --- linux-4.4.115/drivers/staging/android/ion/Makefile 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/staging/android/ion/Makefile 2019-01-22 16:16:26.711275457 +0100 @@ -1,10 +1,13 @@ obj-$(CONFIG_ION) += ion.o ion_heap.o ion_page_pool.o ion_system_heap.o \ - ion_carveout_heap.o ion_chunk_heap.o ion_cma_heap.o + ion_carveout_heap.o ion_chunk_heap.o +ifdef CONFIG_ION_MSM +obj-$(CONFIG_CMA) += ion_cma_heap.o ion_cma_secure_heap.o +endif obj-$(CONFIG_ION_TEST) += ion_test.o ifdef CONFIG_COMPAT obj-$(CONFIG_ION) += compat_ion.o endif - obj-$(CONFIG_ION_DUMMY) += ion_dummy_driver.o obj-$(CONFIG_ION_TEGRA) += tegra/ - +obj-$(CONFIG_ION_MSM) += msm/ +obj-$(CONFIG_ION_MSM) += ion_system_secure_heap.o diff -ruw linux-4.4.115/drivers/staging/android/Kconfig linux-4.4.115-fbx/drivers/staging/android/Kconfig --- linux-4.4.115/drivers/staging/android/Kconfig 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/staging/android/Kconfig 2019-10-29 09:26:24.841214902 +0100 @@ -38,6 +38,15 @@ scripts (/init.rc), and it defines priority values with minimum free memory size for each priority. +config ANDROID_LOW_MEMORY_KILLER_AUTODETECT_OOM_ADJ_VALUES + bool "Android Low Memory Killer: detect oom_adj values" + depends on ANDROID_LOW_MEMORY_KILLER + default y + ---help--- + Detect oom_adj values written to + /sys/module/lowmemorykiller/parameters/adj and convert them + to oom_score_adj values. + config SYNC bool "Synchronization framework" default n @@ -66,8 +75,25 @@ *WARNING* improper use of this can result in deadlocking kernel drivers from userspace. +config ONESHOT_SYNC + bool "One shot sync objects" + depends on SYNC + help + This sync driver provides a way to create sync objects that may + be signaled by userspace. Unlike other sync objects, the + sync objects created by this driver may be signaled in any order + without changing the state of other sync objects on the timeline. + +config ONESHOT_SYNC_USER + bool "Userspace API for ONESHOT_SYNC" + depends on SYNC + help + Provide a userspace API for creating oneshot sync objects. + source "drivers/staging/android/ion/Kconfig" +source "drivers/staging/android/fiq_debugger/Kconfig" + endif # if ANDROID endmenu diff -ruw linux-4.4.115/drivers/staging/android/lowmemorykiller.c linux-4.4.115-fbx/drivers/staging/android/lowmemorykiller.c --- linux-4.4.115/drivers/staging/android/lowmemorykiller.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/staging/android/lowmemorykiller.c 2019-10-29 09:26:24.849214980 +0100 @@ -42,6 +42,25 @@ #include #include #include +#include +#include +#include +#include +#include +#include +#include + +#define CREATE_TRACE_POINTS +#include + +#ifdef CONFIG_HIGHMEM +#define _ZONE ZONE_HIGHMEM +#else +#define _ZONE ZONE_NORMAL +#endif + +#define CREATE_TRACE_POINTS +#include "trace/lowmemorykiller.h" static uint32_t lowmem_debug_level = 1; static short lowmem_adj[6] = { @@ -58,6 +77,7 @@ 16 * 1024, /* 64MB */ }; static int lowmem_minfree_size = 4; +static int lmk_fast_run = 1; static unsigned long lowmem_deathpending_timeout; @@ -76,6 +96,314 @@ global_page_state(NR_INACTIVE_FILE); } +static atomic_t shift_adj = ATOMIC_INIT(0); +static short adj_max_shift = 353; +module_param_named(adj_max_shift, adj_max_shift, short, + S_IRUGO | S_IWUSR); + +/* User knob to enable/disable adaptive lmk feature */ +static int enable_adaptive_lmk; +module_param_named(enable_adaptive_lmk, enable_adaptive_lmk, int, + S_IRUGO | S_IWUSR); + +/* + * This parameter controls the behaviour of LMK when vmpressure is in + * the range of 90-94. Adaptive lmk triggers based on number of file + * pages wrt vmpressure_file_min, when vmpressure is in the range of + * 90-94. Usually this is a pseudo minfree value, higher than the + * highest configured value in minfree array. + */ +static int vmpressure_file_min; +module_param_named(vmpressure_file_min, vmpressure_file_min, int, + S_IRUGO | S_IWUSR); + +enum { + VMPRESSURE_NO_ADJUST = 0, + VMPRESSURE_ADJUST_ENCROACH, + VMPRESSURE_ADJUST_NORMAL, +}; + +int adjust_minadj(short *min_score_adj) +{ + int ret = VMPRESSURE_NO_ADJUST; + + if (!enable_adaptive_lmk) + return 0; + + if (atomic_read(&shift_adj) && + (*min_score_adj > adj_max_shift)) { + if (*min_score_adj == OOM_SCORE_ADJ_MAX + 1) + ret = VMPRESSURE_ADJUST_ENCROACH; + else + ret = VMPRESSURE_ADJUST_NORMAL; + *min_score_adj = adj_max_shift; + } + atomic_set(&shift_adj, 0); + + return ret; +} + +static int lmk_vmpressure_notifier(struct notifier_block *nb, + unsigned long action, void *data) +{ + int other_free = 0, other_file = 0; + unsigned long pressure = action; + int array_size = ARRAY_SIZE(lowmem_adj); + + if (!enable_adaptive_lmk) + return 0; + + if (pressure >= 95) { + other_file = global_page_state(NR_FILE_PAGES) + zcache_pages() - + global_page_state(NR_SHMEM) - + total_swapcache_pages(); + other_free = global_page_state(NR_FREE_PAGES); + + atomic_set(&shift_adj, 1); + trace_almk_vmpressure(pressure, other_free, other_file); + } else if (pressure >= 90) { + if (lowmem_adj_size < array_size) + array_size = lowmem_adj_size; + if (lowmem_minfree_size < array_size) + array_size = lowmem_minfree_size; + + other_file = global_page_state(NR_FILE_PAGES) + zcache_pages() - + global_page_state(NR_SHMEM) - + total_swapcache_pages(); + + other_free = global_page_state(NR_FREE_PAGES); + + if ((other_free < lowmem_minfree[array_size - 1]) && + (other_file < vmpressure_file_min)) { + atomic_set(&shift_adj, 1); + trace_almk_vmpressure(pressure, other_free, other_file); + } + } else if (atomic_read(&shift_adj)) { + other_file = global_page_state(NR_FILE_PAGES) + zcache_pages() - + global_page_state(NR_SHMEM) - + total_swapcache_pages(); + other_free = global_page_state(NR_FREE_PAGES); + + /* + * shift_adj would have been set by a previous invocation + * of notifier, which is not followed by a lowmem_shrink yet. + * Since vmpressure has improved, reset shift_adj to avoid + * false adaptive LMK trigger. + */ + trace_almk_vmpressure(pressure, other_free, other_file); + atomic_set(&shift_adj, 0); + } + + return 0; +} + +static struct notifier_block lmk_vmpr_nb = { + .notifier_call = lmk_vmpressure_notifier, +}; + +static int test_task_flag(struct task_struct *p, int flag) +{ + struct task_struct *t; + + for_each_thread(p, t) { + task_lock(t); + if (test_tsk_thread_flag(t, flag)) { + task_unlock(t); + return 1; + } + task_unlock(t); + } + + return 0; +} + +static int test_task_state(struct task_struct *p, int state) +{ + struct task_struct *t; + + for_each_thread(p, t) { + task_lock(t); + if (t->state & state) { + task_unlock(t); + return 1; + } + task_unlock(t); + } + + return 0; +} + +static DEFINE_MUTEX(scan_mutex); + +int can_use_cma_pages(gfp_t gfp_mask) +{ + int can_use = 0; + int mtype = gfpflags_to_migratetype(gfp_mask); + int i = 0; + int *mtype_fallbacks = get_migratetype_fallbacks(mtype); + + if (is_migrate_cma(mtype)) { + can_use = 1; + } else { + for (i = 0;; i++) { + int fallbacktype = mtype_fallbacks[i]; + + if (is_migrate_cma(fallbacktype)) { + can_use = 1; + break; + } + + if (fallbacktype == MIGRATE_TYPES) + break; + } + } + return can_use; +} + +void tune_lmk_zone_param(struct zonelist *zonelist, int classzone_idx, + int *other_free, int *other_file, + int use_cma_pages) +{ + struct zone *zone; + struct zoneref *zoneref; + int zone_idx; + + for_each_zone_zonelist(zone, zoneref, zonelist, MAX_NR_ZONES) { + zone_idx = zonelist_zone_idx(zoneref); + if (zone_idx == ZONE_MOVABLE) { + if (!use_cma_pages && other_free) + *other_free -= + zone_page_state(zone, NR_FREE_CMA_PAGES); + continue; + } + + if (zone_idx > classzone_idx) { + if (other_free != NULL) + *other_free -= zone_page_state(zone, + NR_FREE_PAGES); + if (other_file != NULL) + *other_file -= zone_page_state(zone, + NR_FILE_PAGES) + - zone_page_state(zone, NR_SHMEM) + - zone_page_state(zone, NR_SWAPCACHE); + } else if (zone_idx < classzone_idx) { + if (zone_watermark_ok(zone, 0, 0, classzone_idx, 0) && + other_free) { + if (!use_cma_pages) { + *other_free -= min( + zone->lowmem_reserve[classzone_idx] + + zone_page_state( + zone, NR_FREE_CMA_PAGES), + zone_page_state( + zone, NR_FREE_PAGES)); + } else { + *other_free -= + zone->lowmem_reserve[classzone_idx]; + } + } else { + if (other_free) + *other_free -= + zone_page_state(zone, NR_FREE_PAGES); + } + } + } +} + +#ifdef CONFIG_HIGHMEM +void adjust_gfp_mask(gfp_t *gfp_mask) +{ + struct zone *preferred_zone; + struct zonelist *zonelist; + enum zone_type high_zoneidx; + + if (current_is_kswapd()) { + zonelist = node_zonelist(0, *gfp_mask); + high_zoneidx = gfp_zone(*gfp_mask); + first_zones_zonelist(zonelist, high_zoneidx, NULL, + &preferred_zone); + + if (high_zoneidx == ZONE_NORMAL) { + if (zone_watermark_ok_safe( + preferred_zone, 0, + high_wmark_pages(preferred_zone), 0)) + *gfp_mask |= __GFP_HIGHMEM; + } else if (high_zoneidx == ZONE_HIGHMEM) { + *gfp_mask |= __GFP_HIGHMEM; + } + } +} +#else +void adjust_gfp_mask(gfp_t *unused) +{ +} +#endif + +void tune_lmk_param(int *other_free, int *other_file, struct shrink_control *sc) +{ + gfp_t gfp_mask; + struct zone *preferred_zone; + struct zonelist *zonelist; + enum zone_type high_zoneidx, classzone_idx; + unsigned long balance_gap; + int use_cma_pages; + + gfp_mask = sc->gfp_mask; + adjust_gfp_mask(&gfp_mask); + + zonelist = node_zonelist(0, gfp_mask); + high_zoneidx = gfp_zone(gfp_mask); + first_zones_zonelist(zonelist, high_zoneidx, NULL, &preferred_zone); + classzone_idx = zone_idx(preferred_zone); + use_cma_pages = can_use_cma_pages(gfp_mask); + + balance_gap = min(low_wmark_pages(preferred_zone), + (preferred_zone->present_pages + + KSWAPD_ZONE_BALANCE_GAP_RATIO-1) / + KSWAPD_ZONE_BALANCE_GAP_RATIO); + + if (likely(current_is_kswapd() && zone_watermark_ok(preferred_zone, 0, + high_wmark_pages(preferred_zone) + SWAP_CLUSTER_MAX + + balance_gap, 0, 0))) { + if (lmk_fast_run) + tune_lmk_zone_param(zonelist, classzone_idx, other_free, + other_file, use_cma_pages); + else + tune_lmk_zone_param(zonelist, classzone_idx, other_free, + NULL, use_cma_pages); + + if (zone_watermark_ok(preferred_zone, 0, 0, _ZONE, 0)) { + if (!use_cma_pages) { + *other_free -= min( + preferred_zone->lowmem_reserve[_ZONE] + + zone_page_state( + preferred_zone, NR_FREE_CMA_PAGES), + zone_page_state( + preferred_zone, NR_FREE_PAGES)); + } else { + *other_free -= + preferred_zone->lowmem_reserve[_ZONE]; + } + } else { + *other_free -= zone_page_state(preferred_zone, + NR_FREE_PAGES); + } + + lowmem_print(4, "lowmem_shrink of kswapd tunning for highmem " + "ofree %d, %d\n", *other_free, *other_file); + } else { + tune_lmk_zone_param(zonelist, classzone_idx, other_free, + other_file, use_cma_pages); + + if (!use_cma_pages) { + *other_free -= + zone_page_state(preferred_zone, NR_FREE_CMA_PAGES); + } + + lowmem_print(4, "lowmem_shrink tunning for others ofree %d, " + "%d\n", *other_free, *other_file); + } +} + static unsigned long lowmem_scan(struct shrinker *s, struct shrink_control *sc) { struct task_struct *tsk; @@ -83,34 +411,54 @@ unsigned long rem = 0; int tasksize; int i; + int ret = 0; short min_score_adj = OOM_SCORE_ADJ_MAX + 1; + int minfree = 0; int selected_tasksize = 0; short selected_oom_score_adj; int array_size = ARRAY_SIZE(lowmem_adj); - int other_free = global_page_state(NR_FREE_PAGES) - totalreserve_pages; - int other_file = global_page_state(NR_FILE_PAGES) - + int other_free; + int other_file; + + if (!mutex_trylock(&scan_mutex)) + return 0; + + other_free = global_page_state(NR_FREE_PAGES); + + if (global_page_state(NR_SHMEM) + total_swapcache_pages() < + global_page_state(NR_FILE_PAGES) + zcache_pages()) + other_file = global_page_state(NR_FILE_PAGES) + zcache_pages() - global_page_state(NR_SHMEM) - + global_page_state(NR_UNEVICTABLE) - total_swapcache_pages(); + else + other_file = 0; + + tune_lmk_param(&other_free, &other_file, sc); if (lowmem_adj_size < array_size) array_size = lowmem_adj_size; if (lowmem_minfree_size < array_size) array_size = lowmem_minfree_size; for (i = 0; i < array_size; i++) { - if (other_free < lowmem_minfree[i] && - other_file < lowmem_minfree[i]) { + minfree = lowmem_minfree[i]; + if (other_free < minfree && other_file < minfree) { min_score_adj = lowmem_adj[i]; break; } } + ret = adjust_minadj(&min_score_adj); + lowmem_print(3, "lowmem_scan %lu, %x, ofree %d %d, ma %hd\n", sc->nr_to_scan, sc->gfp_mask, other_free, other_file, min_score_adj); if (min_score_adj == OOM_SCORE_ADJ_MAX + 1) { + trace_almk_shrink(0, ret, other_free, other_file, 0); lowmem_print(5, "lowmem_scan %lu, %x, return 0\n", sc->nr_to_scan, sc->gfp_mask); + mutex_unlock(&scan_mutex); return 0; } @@ -124,16 +472,22 @@ if (tsk->flags & PF_KTHREAD) continue; - p = find_lock_task_mm(tsk); - if (!p) + /* if task no longer has any memory ignore it */ + if (test_task_flag(tsk, TIF_MM_RELEASED)) continue; - if (test_tsk_thread_flag(p, TIF_MEMDIE) && - time_before_eq(jiffies, lowmem_deathpending_timeout)) { - task_unlock(p); + if (time_before_eq(jiffies, lowmem_deathpending_timeout)) { + if (test_task_flag(tsk, TIF_MEMDIE)) { rcu_read_unlock(); + mutex_unlock(&scan_mutex); return 0; } + } + + p = find_lock_task_mm(tsk); + if (!p) + continue; + oom_score_adj = p->signal->oom_score_adj; if (oom_score_adj < min_score_adj) { task_unlock(p); @@ -153,10 +507,22 @@ selected = p; selected_tasksize = tasksize; selected_oom_score_adj = oom_score_adj; - lowmem_print(2, "select %d (%s), adj %hd, size %d, to kill\n", - p->pid, p->comm, oom_score_adj, tasksize); + lowmem_print(3, "select '%s' (%d), adj %hd, size %d, to kill\n", + p->comm, p->pid, oom_score_adj, tasksize); } if (selected) { + long cache_size, cache_limit, free; + + if (test_task_flag(selected, TIF_MEMDIE) && + (test_task_state(selected, TASK_UNINTERRUPTIBLE))) { + lowmem_print(2, "'%s' (%d) is already killed\n", + selected->comm, + selected->pid); + rcu_read_unlock(); + mutex_unlock(&scan_mutex); + return 0; + } + task_lock(selected); send_sig(SIGKILL, selected, 0); /* @@ -167,40 +533,169 @@ if (selected->mm) mark_oom_victim(selected); task_unlock(selected); - lowmem_print(1, "send sigkill to %d (%s), adj %hd, size %d\n", - selected->pid, selected->comm, - selected_oom_score_adj, selected_tasksize); + cache_size = other_file * (long)(PAGE_SIZE / 1024); + cache_limit = minfree * (long)(PAGE_SIZE / 1024); + free = other_free * (long)(PAGE_SIZE / 1024); + trace_lowmemory_kill(selected, cache_size, cache_limit, free); + lowmem_print(1, "Killing '%s' (%d) (tgid %d), adj %hd,\n" \ + " to free %ldkB on behalf of '%s' (%d) because\n" \ + " cache %ldkB is below limit %ldkB for oom_score_adj %hd\n" \ + " Free memory is %ldkB above reserved.\n" \ + " Free CMA is %ldkB\n" \ + " Total reserve is %ldkB\n" \ + " Total free pages is %ldkB\n" \ + " Total file cache is %ldkB\n" \ + " Total zcache is %ldkB\n" \ + " GFP mask is 0x%x\n", + selected->comm, selected->pid, selected->tgid, + selected_oom_score_adj, + selected_tasksize * (long)(PAGE_SIZE / 1024), + current->comm, current->pid, + cache_size, cache_limit, + min_score_adj, + free, + global_page_state(NR_FREE_CMA_PAGES) * + (long)(PAGE_SIZE / 1024), + totalreserve_pages * (long)(PAGE_SIZE / 1024), + global_page_state(NR_FREE_PAGES) * + (long)(PAGE_SIZE / 1024), + global_page_state(NR_FILE_PAGES) * + (long)(PAGE_SIZE / 1024), + (long)zcache_pages() * (long)(PAGE_SIZE / 1024), + sc->gfp_mask); + + if (lowmem_debug_level >= 2 && selected_oom_score_adj == 0) { + show_mem(SHOW_MEM_FILTER_NODES); + dump_tasks(NULL, NULL); + } + lowmem_deathpending_timeout = jiffies + HZ; rem += selected_tasksize; + rcu_read_unlock(); + /* give the system time to free up the memory */ + msleep_interruptible(20); + trace_almk_shrink(selected_tasksize, ret, + other_free, other_file, + selected_oom_score_adj); + } else { + trace_almk_shrink(1, ret, other_free, other_file, 0); + rcu_read_unlock(); } lowmem_print(4, "lowmem_scan %lu, %x, return %lu\n", sc->nr_to_scan, sc->gfp_mask, rem); - rcu_read_unlock(); + mutex_unlock(&scan_mutex); return rem; } static struct shrinker lowmem_shrinker = { .scan_objects = lowmem_scan, .count_objects = lowmem_count, - .seeks = DEFAULT_SEEKS * 16 + .seeks = DEFAULT_SEEKS * 16, + .flags = SHRINKER_LMK }; static int __init lowmem_init(void) { register_shrinker(&lowmem_shrinker); + vmpressure_notifier_register(&lmk_vmpr_nb); return 0; } device_initcall(lowmem_init); +#ifdef CONFIG_ANDROID_LOW_MEMORY_KILLER_AUTODETECT_OOM_ADJ_VALUES +static short lowmem_oom_adj_to_oom_score_adj(short oom_adj) +{ + if (oom_adj == OOM_ADJUST_MAX) + return OOM_SCORE_ADJ_MAX; + else + return (oom_adj * OOM_SCORE_ADJ_MAX) / -OOM_DISABLE; +} + +static void lowmem_autodetect_oom_adj_values(void) +{ + int i; + short oom_adj; + short oom_score_adj; + int array_size = ARRAY_SIZE(lowmem_adj); + + if (lowmem_adj_size < array_size) + array_size = lowmem_adj_size; + + if (array_size <= 0) + return; + + oom_adj = lowmem_adj[array_size - 1]; + if (oom_adj > OOM_ADJUST_MAX) + return; + + oom_score_adj = lowmem_oom_adj_to_oom_score_adj(oom_adj); + if (oom_score_adj <= OOM_ADJUST_MAX) + return; + + lowmem_print(1, "lowmem_shrink: convert oom_adj to oom_score_adj:\n"); + for (i = 0; i < array_size; i++) { + oom_adj = lowmem_adj[i]; + oom_score_adj = lowmem_oom_adj_to_oom_score_adj(oom_adj); + lowmem_adj[i] = oom_score_adj; + lowmem_print(1, "oom_adj %d => oom_score_adj %d\n", + oom_adj, oom_score_adj); + } +} + +static int lowmem_adj_array_set(const char *val, const struct kernel_param *kp) +{ + int ret; + + ret = param_array_ops.set(val, kp); + + /* HACK: Autodetect oom_adj values in lowmem_adj array */ + lowmem_autodetect_oom_adj_values(); + + return ret; +} + +static int lowmem_adj_array_get(char *buffer, const struct kernel_param *kp) +{ + return param_array_ops.get(buffer, kp); +} + +static void lowmem_adj_array_free(void *arg) +{ + param_array_ops.free(arg); +} + +static struct kernel_param_ops lowmem_adj_array_ops = { + .set = lowmem_adj_array_set, + .get = lowmem_adj_array_get, + .free = lowmem_adj_array_free, +}; + +static const struct kparam_array __param_arr_adj = { + .max = ARRAY_SIZE(lowmem_adj), + .num = &lowmem_adj_size, + .ops = ¶m_ops_short, + .elemsize = sizeof(lowmem_adj[0]), + .elem = lowmem_adj, +}; +#endif + /* * not really modular, but the easiest way to keep compat with existing * bootargs behaviour is to continue using module_param here. */ module_param_named(cost, lowmem_shrinker.seeks, int, S_IRUGO | S_IWUSR); +#ifdef CONFIG_ANDROID_LOW_MEMORY_KILLER_AUTODETECT_OOM_ADJ_VALUES +module_param_cb(adj, &lowmem_adj_array_ops, + .arr = &__param_arr_adj, + S_IRUGO | S_IWUSR); +__MODULE_PARM_TYPE(adj, "array of short"); +#else module_param_array_named(adj, lowmem_adj, short, &lowmem_adj_size, S_IRUGO | S_IWUSR); +#endif module_param_array_named(minfree, lowmem_minfree, uint, &lowmem_minfree_size, S_IRUGO | S_IWUSR); module_param_named(debug_level, lowmem_debug_level, uint, S_IRUGO | S_IWUSR); +module_param_named(lmk_fast_run, lmk_fast_run, int, S_IRUGO | S_IWUSR); diff -ruw linux-4.4.115/drivers/staging/android/Makefile linux-4.4.115-fbx/drivers/staging/android/Makefile --- linux-4.4.115/drivers/staging/android/Makefile 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/staging/android/Makefile 2019-10-29 09:26:24.841214902 +0100 @@ -1,6 +1,7 @@ ccflags-y += -I$(src) # needed for trace events obj-y += ion/ +obj-$(CONFIG_FIQ_DEBUGGER) += fiq_debugger/ obj-$(CONFIG_ASHMEM) += ashmem.o obj-$(CONFIG_ANDROID_TIMED_OUTPUT) += timed_output.o @@ -8,3 +9,4 @@ obj-$(CONFIG_ANDROID_LOW_MEMORY_KILLER) += lowmemorykiller.o obj-$(CONFIG_SYNC) += sync.o sync_debug.o obj-$(CONFIG_SW_SYNC) += sw_sync.o +obj-$(CONFIG_ONESHOT_SYNC) += oneshot_sync.o diff -ruw linux-4.4.115/drivers/staging/android/sync.c linux-4.4.115-fbx/drivers/staging/android/sync.c --- linux-4.4.115/drivers/staging/android/sync.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/staging/android/sync.c 2019-10-29 09:26:24.849214980 +0100 @@ -29,6 +29,7 @@ #include "sync.h" #define CREATE_TRACE_POINTS +#define SYNC_DUMP_TIME_LIMIT 7000 #include "trace/sync.h" static const struct fence_ops android_fence_ops; @@ -390,8 +391,10 @@ return ret; } else if (ret == 0) { if (timeout) { - pr_info("fence timeout on [%p] after %dms\n", fence, + pr_info("fence timeout on [%pK] after %dms\n", fence, jiffies_to_msecs(timeout)); + if (jiffies_to_msecs(timeout) >= + SYNC_DUMP_TIME_LIMIT) sync_dump(); } return -ETIME; @@ -399,7 +402,7 @@ ret = atomic_read(&fence->status); if (ret) { - pr_info("fence error %ld on [%p]\n", ret, fence); + pr_info("fence error %ld on [%pK]\n", ret, fence); sync_dump(); } return ret; @@ -465,6 +468,13 @@ return true; } +static void android_fence_disable_signaling(struct fence *fence) +{ + struct sync_pt *pt = container_of(fence, struct sync_pt, base); + + list_del_init(&pt->active_list); +} + static int android_fence_fill_driver_data(struct fence *fence, void *data, int size) { @@ -508,6 +518,7 @@ .get_driver_name = android_fence_get_driver_name, .get_timeline_name = android_fence_get_timeline_name, .enable_signaling = android_fence_enable_signaling, + .disable_signaling = android_fence_disable_signaling, .signaled = android_fence_signaled, .wait = fence_default_wait, .release = android_fence_release, @@ -519,12 +530,10 @@ static void sync_fence_free(struct kref *kref) { struct sync_fence *fence = container_of(kref, struct sync_fence, kref); - int i, status = atomic_read(&fence->status); + int i; for (i = 0; i < fence->num_fences; ++i) { - if (status) - fence_remove_callback(fence->cbs[i].sync_pt, - &fence->cbs[i].cb); + fence_remove_callback(fence->cbs[i].sync_pt, &fence->cbs[i].cb); fence_put(fence->cbs[i].sync_pt); } diff -ruw linux-4.4.115/drivers/staging/android/sync_debug.c linux-4.4.115-fbx/drivers/staging/android/sync_debug.c --- linux-4.4.115/drivers/staging/android/sync_debug.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/staging/android/sync_debug.c 2019-01-22 16:16:26.719275529 +0100 @@ -87,7 +87,7 @@ int status = 1; struct sync_timeline *parent = sync_pt_parent(pt); - if (fence_is_signaled_locked(&pt->base)) + if (test_bit(FENCE_FLAG_SIGNALED_BIT, &pt->base.flags)) status = pt->base.status; seq_printf(s, " %s%spt %s", @@ -149,7 +149,7 @@ unsigned long flags; int i; - seq_printf(s, "[%p] %s: %s\n", fence, fence->name, + seq_printf(s, "[%pK] %s: %s\n", fence, fence->name, sync_status_str(atomic_read(&fence->status))); for (i = 0; i < fence->num_fences; ++i) { diff -ruw linux-4.4.115/drivers/staging/android/sync.h linux-4.4.115-fbx/drivers/staging/android/sync.h --- linux-4.4.115/drivers/staging/android/sync.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/staging/android/sync.h 2019-01-22 16:16:26.719275529 +0100 @@ -92,7 +92,7 @@ struct sync_timeline { struct kref kref; const struct sync_timeline_ops *ops; - char name[32]; + char name[64]; /* protected by child_list_lock */ bool destroyed; @@ -154,7 +154,7 @@ struct sync_fence { struct file *file; struct kref kref; - char name[32]; + char name[64]; #ifdef CONFIG_DEBUG_FS struct list_head sync_fence_list; #endif diff -ruw linux-4.4.115/drivers/staging/android/uapi/ashmem.h linux-4.4.115-fbx/drivers/staging/android/uapi/ashmem.h --- linux-4.4.115/drivers/staging/android/uapi/ashmem.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/staging/android/uapi/ashmem.h 2019-01-22 16:16:26.719275529 +0100 @@ -13,6 +13,7 @@ #define _UAPI_LINUX_ASHMEM_H #include +#include #define ASHMEM_NAME_LEN 256 diff -ruw linux-4.4.115/drivers/staging/goldfish/Kconfig linux-4.4.115-fbx/drivers/staging/goldfish/Kconfig --- linux-4.4.115/drivers/staging/goldfish/Kconfig 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/staging/goldfish/Kconfig 2019-10-29 09:26:24.861215098 +0100 @@ -4,6 +4,12 @@ ---help--- Emulated audio channel for the Goldfish Android Virtual Device +config GOLDFISH_SYNC + tristate "Goldfish AVD Sync Driver" + depends on GOLDFISH + ---help--- + Emulated sync fences for the Goldfish Android Virtual Device + config MTD_GOLDFISH_NAND tristate "Goldfish NAND device" depends on GOLDFISH diff -ruw linux-4.4.115/drivers/staging/goldfish/Makefile linux-4.4.115-fbx/drivers/staging/goldfish/Makefile --- linux-4.4.115/drivers/staging/goldfish/Makefile 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/staging/goldfish/Makefile 2019-10-29 09:26:24.861215098 +0100 @@ -4,3 +4,8 @@ obj-$(CONFIG_GOLDFISH_AUDIO) += goldfish_audio.o obj-$(CONFIG_MTD_GOLDFISH_NAND) += goldfish_nand.o + +# and sync + +ccflags-y := -Idrivers/staging/android +obj-$(CONFIG_GOLDFISH_SYNC) += goldfish_sync.o diff -ruw linux-4.4.115/drivers/staging/Makefile linux-4.4.115-fbx/drivers/staging/Makefile --- linux-4.4.115/drivers/staging/Makefile 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/staging/Makefile 2019-01-22 16:16:26.711275457 +0100 @@ -26,7 +26,6 @@ obj-$(CONFIG_FB_XGI) += xgifb/ obj-$(CONFIG_USB_EMXX) += emxx_udc/ obj-$(CONFIG_SPEAKUP) += speakup/ -obj-$(CONFIG_TOUCHSCREEN_SYNAPTICS_I2C_RMI4) += ste_rmi4/ obj-$(CONFIG_MFD_NVEC) += nvec/ obj-$(CONFIG_STAGING_RDMA) += rdma/ obj-$(CONFIG_ANDROID) += android/ diff -ruw linux-4.4.115/drivers/thermal/cpu_cooling.c linux-4.4.115-fbx/drivers/thermal/cpu_cooling.c --- linux-4.4.115/drivers/thermal/cpu_cooling.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/thermal/cpu_cooling.c 2019-01-22 16:16:27.151279441 +0100 @@ -103,6 +103,7 @@ int dyn_power_table_entries; struct device *cpu_dev; get_static_t plat_get_static_power; + struct cpu_cooling_ops *plat_ops; }; static DEFINE_IDR(cpufreq_idr); static DEFINE_MUTEX(cooling_cpufreq_lock); @@ -506,7 +507,12 @@ unsigned long *state) { struct cpufreq_cooling_device *cpufreq_device = cdev->devdata; + unsigned int cpu = cpumask_any(&cpufreq_device->allowed_cpus); + if (cpufreq_device->plat_ops + && cpufreq_device->plat_ops->get_cur_state) + cpufreq_device->plat_ops->get_cur_state(cpu, state); + else *state = cpufreq_device->cpufreq_state; return 0; @@ -541,7 +547,17 @@ cpufreq_device->cpufreq_state = state; cpufreq_device->clipped_freq = clip_freq; + /* Check if the device has a platform mitigation function that + * can handle the CPU freq mitigation, if not, notify cpufreq + * framework. + */ + if (cpufreq_device->plat_ops) { + if (cpufreq_device->plat_ops->ceil_limit) + cpufreq_device->plat_ops->ceil_limit(cpu, + clip_freq); + } else { cpufreq_update_policy(cpu); + } return 0; } @@ -775,6 +791,9 @@ * @capacitance: dynamic power coefficient for these cpus * @plat_static_func: function to calculate the static power consumed by these * cpus (optional) + * @plat_mitig_func: function that does the mitigation by changing the + * frequencies (Optional). By default, cpufreq framweork will + * be notified of the new limits. * * This interface function registers the cpufreq cooling device with the name * "thermal-cpufreq-%x". This api can support multiple instances of cpufreq @@ -787,7 +806,8 @@ static struct thermal_cooling_device * __cpufreq_cooling_register(struct device_node *np, const struct cpumask *clip_cpus, u32 capacitance, - get_static_t plat_static_func) + get_static_t plat_static_func, + struct cpu_cooling_ops *plat_ops) { struct thermal_cooling_device *cool_dev; struct cpufreq_cooling_device *cpufreq_dev; @@ -853,6 +873,8 @@ } } + cpufreq_dev->plat_ops = plat_ops; + ret = get_idr(&cpufreq_idr, &cpufreq_dev->id); if (ret) { cool_dev = ERR_PTR(ret); @@ -926,7 +948,7 @@ struct thermal_cooling_device * cpufreq_cooling_register(const struct cpumask *clip_cpus) { - return __cpufreq_cooling_register(NULL, clip_cpus, 0, NULL); + return __cpufreq_cooling_register(NULL, clip_cpus, 0, NULL, NULL); } EXPORT_SYMBOL_GPL(cpufreq_cooling_register); @@ -950,7 +972,7 @@ if (!np) return ERR_PTR(-EINVAL); - return __cpufreq_cooling_register(np, clip_cpus, 0, NULL); + return __cpufreq_cooling_register(np, clip_cpus, 0, NULL, NULL); } EXPORT_SYMBOL_GPL(of_cpufreq_cooling_register); @@ -980,11 +1002,31 @@ get_static_t plat_static_func) { return __cpufreq_cooling_register(NULL, clip_cpus, capacitance, - plat_static_func); + plat_static_func, NULL); } EXPORT_SYMBOL(cpufreq_power_cooling_register); /** + * cpufreq_platform_cooling_register() - create cpufreq cooling device with + * additional platform specific mitigation function. + * + * @clip_cpus: cpumask of cpus where the frequency constraints will happen + * @plat_ops: the platform mitigation functions that will be called insted of + * cpufreq, if provided. + * + * Return: a valid struct thermal_cooling_device pointer on success, + * on failure, it returns a corresponding ERR_PTR(). + */ +struct thermal_cooling_device * +cpufreq_platform_cooling_register(const struct cpumask *clip_cpus, + struct cpu_cooling_ops *plat_ops) +{ + return __cpufreq_cooling_register(NULL, clip_cpus, 0, NULL, + plat_ops); +} +EXPORT_SYMBOL(cpufreq_platform_cooling_register); + +/** * of_cpufreq_power_cooling_register() - create cpufreq cooling device with power extensions * @np: a valid struct device_node to the cooling device device tree node * @clip_cpus: cpumask of cpus where the frequency constraints will happen @@ -1017,7 +1059,7 @@ return ERR_PTR(-EINVAL); return __cpufreq_cooling_register(np, clip_cpus, capacitance, - plat_static_func); + plat_static_func, NULL); } EXPORT_SYMBOL(of_cpufreq_power_cooling_register); diff -ruw linux-4.4.115/drivers/thermal/Kconfig linux-4.4.115-fbx/drivers/thermal/Kconfig --- linux-4.4.115/drivers/thermal/Kconfig 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/thermal/Kconfig 2019-10-29 09:26:24.913215606 +0100 @@ -175,6 +175,36 @@ because userland can easily disable the thermal policy by simply flooding this sysfs node with low temperature values. +config LIMITS_MONITOR + bool "LMH monitor driver" + depends on THERMAL + help + Enable this to manage the limits hardware for interrupts, throttling + intensities, and LMH device profiles. This driver also registers the + Limits hardware's monitoring entities as sensors with the thermal + framework. + +config LIMITS_LITE_HW + bool "LMH Lite hardware driver" + depends on LIMITS_MONITOR + help + Enable this option for interacting with LMH Lite hardware. This + implements the APIs required for getting the details about sensors + supported by LMH Lite, their throttling intensity and the operating + profiles. + +config THERMAL_MONITOR + bool "Monitor thermal state and limit CPU Frequency" + depends on THERMAL_TSENS8974 + depends on CPU_FREQ || CPU_FREQ_MSM + depends on PM_OPP + default n + help + This enables thermal monitoring capability in the kernel in the + absence of a system wide thermal monitoring entity or until such an + entity starts running in the userspace. Monitors TSENS temperature + and limits the max frequency of the cores. + config HISI_THERMAL tristate "Hisilicon thermal driver" depends on (ARCH_HISI && CPU_THERMAL && OF) || COMPILE_TEST @@ -183,6 +213,16 @@ thermal framework. cpufreq is used as the cooling device to throttle CPUs when the passive trip is crossed. +config THERMAL_TSENS8974 + tristate "Qualcomm 8974 TSENS Temperature driver" + depends on THERMAL + help + This enables the thermal sysfs driver for the TSENS device. It shows + up in Sysfs as a thermal zone with multiple trip points. Also able + to set threshold temperature for both warm and cool and update + thermal userspace client when a threshold is reached. Warm/Cool + temperature thresholds can be set independently for each sensor. + config IMX_THERMAL tristate "Temperature sensor driver for Freescale i.MX SoCs" depends on CPU_THERMAL @@ -365,6 +405,42 @@ Thermal reporting device will provide temperature reading, programmable trip points and other information. +config THERMAL_QPNP + tristate "Qualcomm Technologies, Inc. QPNP PMIC Temperature Alarm" + depends on OF && SPMI + help + This enables a thermal Sysfs driver for Qualcomm Technologies, Inc. + QPNP PMIC devices. It shows up in Sysfs as a thermal zone with + multiple trip points. The temperature reported by the thermal zone + reflects the real time die temperature if an ADC is present or an + estimate of the temperature based upon the over temperature stage + value if no ADC is available. If allowed via compile time + configuration; enabling the thermal zone device via the mode file + results in shifting PMIC over temperature shutdown control from + hardware to software. + +config THERMAL_QPNP_ADC_TM + tristate "Qualcomm 8974 Thermal Monitor ADC Driver" + depends on THERMAL + depends on SPMI + help + This enables the thermal Sysfs driver for the ADC thermal monitoring + device. It shows up in Sysfs as a thermal zone with multiple trip points. + Disabling the thermal zone device via the mode file results in disabling + the sensor. Also able to set threshold temperature for both hot and cold + and update when a threshold is reached. + +config QCOM_THERMAL_LIMITS_DCVS + bool "QTI LMH DCVS Driver" + depends on THERMAL && ARCH_QCOM + depends on OF + help + This enables the driver for Limits Management Hardware - DCVS block + for the application processors. The h/w block that is available for + each cluster can be used to peform quick thermal mitigations by + tracking temperatures of the CPUs and taking thermal action in the + hardware without s/w intervention. + menu "Texas Instruments thermal drivers" depends on ARCH_HAS_BANDGAP || COMPILE_TEST source "drivers/thermal/ti-soc-thermal/Kconfig" diff -ruw linux-4.4.115/drivers/thermal/Makefile linux-4.4.115-fbx/drivers/thermal/Makefile --- linux-4.4.115/drivers/thermal/Makefile 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/thermal/Makefile 2019-01-22 16:16:27.147279405 +0100 @@ -48,3 +48,10 @@ obj-$(CONFIG_ST_THERMAL) += st/ obj-$(CONFIG_TEGRA_SOCTHERM) += tegra_soctherm.o obj-$(CONFIG_HISI_THERMAL) += hisi_thermal.o +obj-$(CONFIG_THERMAL_QPNP) += qpnp-temp-alarm.o +obj-$(CONFIG_THERMAL_QPNP_ADC_TM) += qpnp-adc-tm.o +obj-$(CONFIG_THERMAL_TSENS8974) += msm-tsens.o +obj-$(CONFIG_THERMAL_MONITOR) += msm_thermal.o msm_thermal-dev.o +obj-$(CONFIG_LIMITS_MONITOR) += lmh_interface.o +obj-$(CONFIG_LIMITS_LITE_HW) += lmh_lite.o +obj-$(CONFIG_QCOM_THERMAL_LIMITS_DCVS) += msm_lmh_dcvs.o diff -ruw linux-4.4.115/drivers/thermal/thermal_core.c linux-4.4.115-fbx/drivers/thermal/thermal_core.c --- linux-4.4.115/drivers/thermal/thermal_core.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/thermal/thermal_core.c 2019-01-22 16:16:27.159279514 +0100 @@ -4,6 +4,7 @@ * Copyright (C) 2008 Intel Corp * Copyright (C) 2008 Zhang Rui * Copyright (C) 2008 Sujith Thomas + * Copyright (c) 2013-2017, The Linux Foundation. All rights reserved. * * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ * @@ -35,9 +36,9 @@ #include #include #include +#include #include #include -#include #define CREATE_TRACE_POINTS #include @@ -45,6 +46,8 @@ #include "thermal_core.h" #include "thermal_hwmon.h" +#define THERMAL_UEVENT_DATA "type" + MODULE_AUTHOR("Zhang Rui"); MODULE_DESCRIPTION("Generic thermal management sysfs support"); MODULE_LICENSE("GPL v2"); @@ -60,8 +63,6 @@ static DEFINE_MUTEX(thermal_list_lock); static DEFINE_MUTEX(thermal_governor_lock); -static atomic_t in_suspend; - static struct thermal_governor *def_governor; static struct thermal_governor *__find_governor(const char *name) @@ -206,6 +207,407 @@ return; } +static LIST_HEAD(sensor_info_list); +static DEFINE_MUTEX(sensor_list_lock); + +static struct sensor_info *get_sensor(uint32_t sensor_id) +{ + struct sensor_info *pos = NULL, *matching_sensor = NULL; + + rcu_read_lock(); + list_for_each_entry_rcu(pos, &sensor_info_list, sensor_list) { + if (pos->sensor_id == sensor_id) { + matching_sensor = pos; + break; + } + } + rcu_read_unlock(); + + return matching_sensor; +} + +int sensor_get_id(char *name) +{ + struct sensor_info *pos = NULL; + int matching_id = -ENODEV; + + if (!name) + return matching_id; + + rcu_read_lock(); + list_for_each_entry_rcu(pos, &sensor_info_list, sensor_list) { + if (!strcmp(pos->tz->type, name)) { + matching_id = pos->sensor_id; + break; + } + } + rcu_read_unlock(); + + return matching_id; +} +EXPORT_SYMBOL(sensor_get_id); + +static void init_sensor_trip(struct sensor_info *sensor) +{ + int ret = 0, i = 0; + enum thermal_trip_type type; + + for (i = 0; ((sensor->max_idx == -1) || + (sensor->min_idx == -1)) && + (sensor->tz->ops->get_trip_type) && + (i < sensor->tz->trips); i++) { + + sensor->tz->ops->get_trip_type(sensor->tz, i, &type); + if (type == THERMAL_TRIP_CONFIGURABLE_HI) + sensor->max_idx = i; + if (type == THERMAL_TRIP_CONFIGURABLE_LOW) + sensor->min_idx = i; + type = 0; + } + + ret = sensor->tz->ops->get_trip_temp(sensor->tz, + sensor->min_idx, &sensor->threshold_min); + if (ret) + pr_err("Unable to get MIN trip temp. sensor:%d err:%d\n", + sensor->sensor_id, ret); + + ret = sensor->tz->ops->get_trip_temp(sensor->tz, + sensor->max_idx, &sensor->threshold_max); + if (ret) + pr_err("Unable to get MAX trip temp. sensor:%d err:%d\n", + sensor->sensor_id, ret); +} + +static int __update_sensor_thresholds(struct sensor_info *sensor) +{ + long max_of_low_thresh = LONG_MIN; + long min_of_high_thresh = LONG_MAX; + struct sensor_threshold *pos = NULL; + int ret = 0; + + if (!sensor->tz->ops->set_trip_temp || + !sensor->tz->ops->activate_trip_type || + !sensor->tz->ops->get_trip_type || + !sensor->tz->ops->get_trip_temp) { + ret = -ENODEV; + goto update_done; + } + + if ((sensor->max_idx == -1) || (sensor->min_idx == -1)) + init_sensor_trip(sensor); + + list_for_each_entry(pos, &sensor->threshold_list, list) { + if (!pos->active) + continue; + if (pos->trip == THERMAL_TRIP_CONFIGURABLE_LOW) { + if (pos->temp > max_of_low_thresh) + max_of_low_thresh = pos->temp; + } + if (pos->trip == THERMAL_TRIP_CONFIGURABLE_HI) { + if (pos->temp < min_of_high_thresh) + min_of_high_thresh = pos->temp; + } + } + + pr_debug("sensor %d: Thresholds: max of low: %ld min of high: %ld\n", + sensor->sensor_id, max_of_low_thresh, + min_of_high_thresh); + + if (min_of_high_thresh != LONG_MAX) { + ret = sensor->tz->ops->set_trip_temp(sensor->tz, + sensor->max_idx, min_of_high_thresh); + if (ret) { + pr_err("sensor %d: Unable to set high threshold %d", + sensor->sensor_id, ret); + goto update_done; + } + sensor->threshold_max = min_of_high_thresh; + } + ret = sensor->tz->ops->activate_trip_type(sensor->tz, + sensor->max_idx, + (min_of_high_thresh == LONG_MAX) ? + THERMAL_TRIP_ACTIVATION_DISABLED : + THERMAL_TRIP_ACTIVATION_ENABLED); + if (ret) { + pr_err("sensor %d: Unable to activate high threshold %d", + sensor->sensor_id, ret); + goto update_done; + } + + if (max_of_low_thresh != LONG_MIN) { + ret = sensor->tz->ops->set_trip_temp(sensor->tz, + sensor->min_idx, max_of_low_thresh); + if (ret) { + pr_err("sensor %d: Unable to set low threshold %d", + sensor->sensor_id, ret); + goto update_done; + } + sensor->threshold_min = max_of_low_thresh; + } + ret = sensor->tz->ops->activate_trip_type(sensor->tz, + sensor->min_idx, + (max_of_low_thresh == LONG_MIN) ? + THERMAL_TRIP_ACTIVATION_DISABLED : + THERMAL_TRIP_ACTIVATION_ENABLED); + if (ret) { + pr_err("sensor %d: Unable to activate low threshold %d", + sensor->sensor_id, ret); + goto update_done; + } + + pr_debug("sensor %d: low: %d high: %d\n", + sensor->sensor_id, + sensor->threshold_min, sensor->threshold_max); + +update_done: + return ret; +} + +static void sensor_update_work(struct work_struct *work) +{ + struct sensor_info *sensor = container_of(work, struct sensor_info, + work); + int ret = 0; + mutex_lock(&sensor->lock); + ret = __update_sensor_thresholds(sensor); + if (ret) + pr_err("sensor %d: Error %d setting threshold\n", + sensor->sensor_id, ret); + mutex_unlock(&sensor->lock); +} + +static __ref int sensor_sysfs_notify(void *data) +{ + int ret = 0; + struct sensor_info *sensor = (struct sensor_info *)data; + + while (!kthread_should_stop()) { + if (wait_for_completion_interruptible( + &sensor->sysfs_notify_complete) != 0) + continue; + if (sensor->deregister_active) + return ret; + reinit_completion(&sensor->sysfs_notify_complete); + sysfs_notify(&sensor->tz->device.kobj, NULL, + THERMAL_UEVENT_DATA); + } + return ret; +} + +/* May be called in an interrupt context. + * Do NOT call sensor_set_trip from this function + */ +int thermal_sensor_trip(struct thermal_zone_device *tz, + enum thermal_trip_type trip, long temp) +{ + struct sensor_threshold *pos = NULL; + int ret = -ENODEV; + + if (trip != THERMAL_TRIP_CONFIGURABLE_HI && + trip != THERMAL_TRIP_CONFIGURABLE_LOW) + return 0; + + if (list_empty(&tz->sensor.threshold_list)) + return 0; + + rcu_read_lock(); + list_for_each_entry_rcu(pos, &tz->sensor.threshold_list, list) { + if ((pos->trip != trip) || (!pos->active)) + continue; + if (((trip == THERMAL_TRIP_CONFIGURABLE_LOW) && + (pos->temp <= tz->sensor.threshold_min) && + (pos->temp >= temp)) || + ((trip == THERMAL_TRIP_CONFIGURABLE_HI) && + (pos->temp >= tz->sensor.threshold_max) && + (pos->temp <= temp))) { + if ((pos == &tz->tz_threshold[0]) + || (pos == &tz->tz_threshold[1])) + complete(&tz->sensor.sysfs_notify_complete); + pos->active = 0; + pos->notify(trip, temp, pos->data); + } + } + rcu_read_unlock(); + + schedule_work(&tz->sensor.work); + + return ret; +} +EXPORT_SYMBOL(thermal_sensor_trip); + +int sensor_get_temp(uint32_t sensor_id, int *temp) +{ + struct sensor_info *sensor = get_sensor(sensor_id); + int ret = 0; + + if (!sensor) + return -ENODEV; + + ret = sensor->tz->ops->get_temp(sensor->tz, temp); + + return ret; +} +EXPORT_SYMBOL(sensor_get_temp); + +int sensor_activate_trip(uint32_t sensor_id, + struct sensor_threshold *threshold, bool enable) +{ + struct sensor_info *sensor = get_sensor(sensor_id); + int ret = 0; + + if (!sensor || !threshold) { + pr_err("%s: uninitialized data\n", + KBUILD_MODNAME); + ret = -ENODEV; + goto activate_trip_exit; + } + + mutex_lock(&sensor->lock); + threshold->active = (enable) ? 1 : 0; + ret = __update_sensor_thresholds(sensor); + mutex_unlock(&sensor->lock); + +activate_trip_exit: + return ret; +} +EXPORT_SYMBOL(sensor_activate_trip); + +int sensor_set_trip(uint32_t sensor_id, struct sensor_threshold *threshold) +{ + struct sensor_threshold *pos = NULL; + struct sensor_info *sensor = get_sensor(sensor_id); + + if (!sensor) + return -ENODEV; + + if (!threshold || !threshold->notify) + return -EFAULT; + + mutex_lock(&sensor->lock); + list_for_each_entry(pos, &sensor->threshold_list, list) { + if (pos == threshold) + break; + } + + if (pos != threshold) { + INIT_LIST_HEAD(&threshold->list); + list_add_rcu(&threshold->list, &sensor->threshold_list); + } + threshold->active = 0; /* Do not allow active threshold right away */ + + mutex_unlock(&sensor->lock); + + return 0; + +} +EXPORT_SYMBOL(sensor_set_trip); + +int sensor_cancel_trip(uint32_t sensor_id, struct sensor_threshold *threshold) +{ + struct sensor_threshold *pos = NULL, *var = NULL; + struct sensor_info *sensor = get_sensor(sensor_id); + int ret = 0; + + if (!sensor) + return -ENODEV; + + mutex_lock(&sensor->lock); + list_for_each_entry_safe(pos, var, &sensor->threshold_list, list) { + if (pos == threshold) { + pos->active = 0; + list_del_rcu(&pos->list); + break; + } + } + + ret = __update_sensor_thresholds(sensor); + mutex_unlock(&sensor->lock); + + return ret; +} +EXPORT_SYMBOL(sensor_cancel_trip); + +static int tz_notify_trip(enum thermal_trip_type type, int temp, void *data) +{ + struct thermal_zone_device *tz = (struct thermal_zone_device *)data; + + pr_debug("sensor %d tripped: type %d temp %d\n", + tz->sensor.sensor_id, type, temp); + + return 0; +} + +static void get_trip_threshold(struct thermal_zone_device *tz, int trip, + struct sensor_threshold **threshold) +{ + enum thermal_trip_type type; + + tz->ops->get_trip_type(tz, trip, &type); + + if (type == THERMAL_TRIP_CONFIGURABLE_HI) + *threshold = &tz->tz_threshold[0]; + else if (type == THERMAL_TRIP_CONFIGURABLE_LOW) + *threshold = &tz->tz_threshold[1]; + else + *threshold = NULL; +} + +int sensor_set_trip_temp(struct thermal_zone_device *tz, + int trip, long temp) +{ + int ret = 0; + struct sensor_threshold *threshold = NULL; + + if (!tz->ops->get_trip_type) + return -EPERM; + + get_trip_threshold(tz, trip, &threshold); + if (threshold) { + threshold->temp = temp; + ret = sensor_set_trip(tz->sensor.sensor_id, threshold); + } else { + ret = tz->ops->set_trip_temp(tz, trip, temp); + } + + return ret; +} + +int sensor_init(struct thermal_zone_device *tz) +{ + struct sensor_info *sensor = &tz->sensor; + + sensor->sensor_id = tz->id; + sensor->tz = tz; + sensor->threshold_min = INT_MIN; + sensor->threshold_max = INT_MAX; + sensor->max_idx = -1; + sensor->min_idx = -1; + sensor->deregister_active = false; + mutex_init(&sensor->lock); + INIT_LIST_HEAD_RCU(&sensor->sensor_list); + INIT_LIST_HEAD_RCU(&sensor->threshold_list); + INIT_LIST_HEAD(&tz->tz_threshold[0].list); + INIT_LIST_HEAD(&tz->tz_threshold[1].list); + tz->tz_threshold[0].notify = tz_notify_trip; + tz->tz_threshold[0].data = tz; + tz->tz_threshold[0].trip = THERMAL_TRIP_CONFIGURABLE_HI; + tz->tz_threshold[1].notify = tz_notify_trip; + tz->tz_threshold[1].data = tz; + tz->tz_threshold[1].trip = THERMAL_TRIP_CONFIGURABLE_LOW; + list_add_rcu(&sensor->sensor_list, &sensor_info_list); + INIT_WORK(&sensor->work, sensor_update_work); + init_completion(&sensor->sysfs_notify_complete); + sensor->sysfs_notify_thread = kthread_run(sensor_sysfs_notify, + &tz->sensor, + "therm_core:notify%d", + tz->id); + if (IS_ERR(sensor->sysfs_notify_thread)) + pr_err("Failed to create notify thread %d", tz->id); + + + return 0; +} + static int get_idr(struct idr *idr, struct mutex *lock, int *id) { int ret; @@ -434,15 +836,19 @@ tz->ops->get_trip_temp(tz, trip, &trip_temp); /* If we have not crossed the trip_temp, we do not care. */ - if (trip_temp <= 0 || tz->temperature < trip_temp) + if (trip_type != THERMAL_TRIP_CRITICAL_LOW && + trip_type != THERMAL_TRIP_CONFIGURABLE_LOW) { + if (tz->temperature < trip_temp) + return; + } else + if (tz->temperature >= trip_temp) return; - - trace_thermal_zone_trip(tz, trip, trip_type); if (tz->ops->notify) tz->ops->notify(tz, trip, trip_type); - if (trip_type == THERMAL_TRIP_CRITICAL) { + if (trip_type == THERMAL_TRIP_CRITICAL || + trip_type == THERMAL_TRIP_CRITICAL_LOW) { dev_emerg(&tz->device, "critical temperature reached(%d C),shutting down\n", tz->temperature / 1000); @@ -460,7 +866,10 @@ tz->ops->get_trip_type(tz, trip, &type); - if (type == THERMAL_TRIP_CRITICAL || type == THERMAL_TRIP_HOT) + if (type == THERMAL_TRIP_CRITICAL || type == THERMAL_TRIP_HOT || + type == THERMAL_TRIP_CONFIGURABLE_HI || + type == THERMAL_TRIP_CONFIGURABLE_LOW || + type == THERMAL_TRIP_CRITICAL_LOW) handle_critical_trips(tz, trip, type); else handle_non_critical_trips(tz, trip, type); @@ -561,9 +970,6 @@ { int count; - if (atomic_read(&in_suspend)) - return; - if (!tz->ops->get_temp) return; @@ -673,6 +1079,12 @@ return sprintf(buf, "critical\n"); case THERMAL_TRIP_HOT: return sprintf(buf, "hot\n"); + case THERMAL_TRIP_CONFIGURABLE_HI: + return sprintf(buf, "configurable_hi\n"); + case THERMAL_TRIP_CONFIGURABLE_LOW: + return sprintf(buf, "configurable_low\n"); + case THERMAL_TRIP_CRITICAL_LOW: + return sprintf(buf, "critical_low\n"); case THERMAL_TRIP_PASSIVE: return sprintf(buf, "passive\n"); case THERMAL_TRIP_ACTIVE: @@ -683,12 +1095,57 @@ } static ssize_t +trip_point_type_activate(struct device *dev, struct device_attribute *attr, + const char *buf, size_t count) +{ + struct thermal_zone_device *tz = to_thermal_zone(dev); + int trip, result = 0; + bool activate; + struct sensor_threshold *threshold = NULL; + + if (!tz->ops->get_trip_type || + !tz->ops->activate_trip_type) { + result = -EPERM; + goto trip_activate_exit; + } + + if (!sscanf(attr->attr.name, "trip_point_%d_type", &trip)) { + result = -EINVAL; + goto trip_activate_exit; + } + + if (!strcmp(buf, "enabled")) { + activate = true; + } else if (!strcmp(buf, "disabled")) { + activate = false; + } else { + result = -EINVAL; + goto trip_activate_exit; + } + + get_trip_threshold(tz, trip, &threshold); + if (threshold) + result = sensor_activate_trip(tz->sensor.sensor_id, + threshold, activate); + else + result = tz->ops->activate_trip_type(tz, trip, + activate ? THERMAL_TRIP_ACTIVATION_ENABLED : + THERMAL_TRIP_ACTIVATION_DISABLED); + +trip_activate_exit: + if (result) + return result; + + return count; +} + +static ssize_t trip_point_temp_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t count) { struct thermal_zone_device *tz = to_thermal_zone(dev); int trip, ret; - unsigned long temperature; + long temperature; if (!tz->ops->set_trip_temp) return -EPERM; @@ -696,10 +1153,10 @@ if (!sscanf(attr->attr.name, "trip_point_%d_temp", &trip)) return -EINVAL; - if (kstrtoul(buf, 10, &temperature)) + if (kstrtol(buf, 10, &temperature)) return -EINVAL; - ret = tz->ops->set_trip_temp(tz, trip, temperature); + ret = sensor_set_trip_temp(tz, trip, temperature); return ret ? ret : count; } @@ -719,7 +1176,6 @@ return -EINVAL; ret = tz->ops->get_trip_temp(tz, trip, &temperature); - if (ret) return ret; @@ -1702,8 +2158,9 @@ sysfs_attr_init(&tz->trip_type_attrs[indx].attr.attr); tz->trip_type_attrs[indx].attr.attr.name = tz->trip_type_attrs[indx].name; - tz->trip_type_attrs[indx].attr.attr.mode = S_IRUGO; + tz->trip_type_attrs[indx].attr.attr.mode = S_IRUGO | S_IWUSR; tz->trip_type_attrs[indx].attr.show = trip_point_type_show; + tz->trip_type_attrs[indx].attr.store = trip_point_type_activate; device_create_file(&tz->device, &tz->trip_type_attrs[indx].attr); @@ -1933,7 +2390,8 @@ } mutex_lock(&thermal_list_lock); - list_add_tail(&tz->node, &thermal_tz_list); + list_add_tail_rcu(&tz->node, &thermal_tz_list); + sensor_init(tz); mutex_unlock(&thermal_list_lock); /* Bind cooling devices for this zone */ @@ -1980,7 +2438,7 @@ mutex_unlock(&thermal_list_lock); return; } - list_del(&tz->node); + list_del_rcu(&tz->node); /* Unbind all cdevs associated with 'this' thermal zone */ list_for_each_entry(cdev, &thermal_cdev_list, node) { @@ -2015,6 +2473,13 @@ thermal_set_governor(tz, NULL); thermal_remove_hwmon_sysfs(tz); + flush_work(&tz->sensor.work); + tz->sensor.deregister_active = true; + complete(&tz->sensor.sysfs_notify_complete); + kthread_stop(tz->sensor.sysfs_notify_thread); + mutex_lock(&thermal_list_lock); + list_del_rcu(&tz->sensor.sensor_list); + mutex_unlock(&thermal_list_lock); release_idr(&thermal_tz_idr, &thermal_idr_lock, tz->id); idr_destroy(&tz->idr); mutex_destroy(&tz->lock); @@ -2041,13 +2506,13 @@ if (!name) goto exit; - mutex_lock(&thermal_list_lock); - list_for_each_entry(pos, &thermal_tz_list, node) + rcu_read_lock(); + list_for_each_entry_rcu(pos, &thermal_tz_list, node) if (!strncasecmp(name, pos->type, THERMAL_NAME_LENGTH)) { found++; ref = pos; } - mutex_unlock(&thermal_list_lock); + rcu_read_unlock(); /* nothing has been found, thus an error code for it */ if (found == 0) @@ -2184,36 +2649,6 @@ thermal_gov_power_allocator_unregister(); } -static int thermal_pm_notify(struct notifier_block *nb, - unsigned long mode, void *_unused) -{ - struct thermal_zone_device *tz; - - switch (mode) { - case PM_HIBERNATION_PREPARE: - case PM_RESTORE_PREPARE: - case PM_SUSPEND_PREPARE: - atomic_set(&in_suspend, 1); - break; - case PM_POST_HIBERNATION: - case PM_POST_RESTORE: - case PM_POST_SUSPEND: - atomic_set(&in_suspend, 0); - list_for_each_entry(tz, &thermal_tz_list, node) { - thermal_zone_device_reset(tz); - thermal_zone_device_update(tz); - } - break; - default: - break; - } - return 0; -} - -static struct notifier_block thermal_pm_nb = { - .notifier_call = thermal_pm_notify, -}; - static int __init thermal_init(void) { int result; @@ -2234,11 +2669,6 @@ if (result) goto exit_netlink; - result = register_pm_notifier(&thermal_pm_nb); - if (result) - pr_warn("Thermal: Can not register suspend notifier, return %d\n", - result); - return 0; exit_netlink: @@ -2258,7 +2688,6 @@ static void __exit thermal_exit(void) { - unregister_pm_notifier(&thermal_pm_nb); of_thermal_destroy_zones(); genetlink_exit(); class_unregister(&thermal_class); diff -ruw linux-4.4.115/drivers/tty/serial/earlycon.c linux-4.4.115-fbx/drivers/tty/serial/earlycon.c --- linux-4.4.115/drivers/tty/serial/earlycon.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/tty/serial/earlycon.c 2019-01-22 16:16:27.191279804 +0100 @@ -19,7 +19,6 @@ #include #include #include -#include #ifdef CONFIG_FIX_EARLYCON_MEM #include @@ -37,13 +36,6 @@ .con = &early_con, }; -extern struct earlycon_id __earlycon_table[]; -static const struct earlycon_id __earlycon_table_sentinel - __used __section(__earlycon_table_end); - -static const struct of_device_id __earlycon_of_table_sentinel - __used __section(__earlycon_of_table_end); - static void __iomem * __init earlycon_map(unsigned long paddr, size_t size) { void __iomem *base; @@ -159,7 +151,7 @@ if (early_con.flags & CON_ENABLED) return -EALREADY; - for (match = __earlycon_table; match->name[0]; match++) { + for (match = __earlycon_table; match < __earlycon_table_end; match++) { size_t len = strlen(match->name); if (strncmp(buf, match->name, len)) diff -ruw linux-4.4.115/drivers/tty/serial/Kconfig linux-4.4.115-fbx/drivers/tty/serial/Kconfig --- linux-4.4.115/drivers/tty/serial/Kconfig 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/tty/serial/Kconfig 2019-01-22 16:16:27.183279731 +0100 @@ -1054,6 +1054,18 @@ select SERIAL_CORE_CONSOLE select SERIAL_EARLYCON +config SERIAL_MSM_HS + tristate "MSM UART High Speed: Serial Driver" + depends on ARCH_QCOM + select SERIAL_CORE + help + If you have a machine based on MSM family of SoCs, you + can enable its onboard high speed serial port by enabling + this option. + + Choose M here to compile it as a module. The module will be + called msm_serial_hs. + config SERIAL_VT8500 bool "VIA VT8500 on-chip serial port support" depends on ARCH_VT8500 @@ -1408,6 +1420,14 @@ (the system console is the device which receives all kernel messages and warnings and which allows logins in single user mode). +config SERIAL_MSM_SMD + bool "Enable tty device interface for some SMD ports" + default n + depends on MSM_SMD + help + Enables userspace clients to read and write to some streaming SMD + ports via tty device interface for MSM chipset. + config SERIAL_MXS_AUART depends on ARCH_MXS || COMPILE_TEST tristate "MXS AUART support" diff -ruw linux-4.4.115/drivers/tty/serial/Makefile linux-4.4.115-fbx/drivers/tty/serial/Makefile --- linux-4.4.115/drivers/tty/serial/Makefile 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/tty/serial/Makefile 2019-01-22 16:16:27.183279731 +0100 @@ -62,6 +62,7 @@ obj-$(CONFIG_SERIAL_ATMEL) += atmel_serial.o obj-$(CONFIG_SERIAL_UARTLITE) += uartlite.o obj-$(CONFIG_SERIAL_MSM) += msm_serial.o +obj-$(CONFIG_SERIAL_MSM_HS) += msm_serial_hs.o obj-$(CONFIG_SERIAL_NETX) += netx-serial.o obj-$(CONFIG_SERIAL_OF_PLATFORM) += of_serial.o obj-$(CONFIG_SERIAL_OF_PLATFORM_NWPSERIAL) += nwpserial.o @@ -79,6 +80,7 @@ obj-$(CONFIG_SERIAL_VT8500) += vt8500_serial.o obj-$(CONFIG_SERIAL_IFX6X60) += ifx6x60.o obj-$(CONFIG_SERIAL_PCH_UART) += pch_uart.o +obj-$(CONFIG_SERIAL_MSM_SMD) += msm_smd_tty.o obj-$(CONFIG_SERIAL_MXS_AUART) += mxs-auart.o obj-$(CONFIG_SERIAL_LANTIQ) += lantiq.o obj-$(CONFIG_SERIAL_XILINX_PS_UART) += xilinx_uartps.o diff -ruw linux-4.4.115/drivers/tty/serial/msm_serial.c linux-4.4.115-fbx/drivers/tty/serial/msm_serial.c --- linux-4.4.115/drivers/tty/serial/msm_serial.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/tty/serial/msm_serial.c 2019-10-29 09:26:24.941215880 +0100 @@ -19,28 +19,142 @@ # define SUPPORT_SYSRQ #endif +#include #include #include #include -#include #include #include #include -#include +#include #include #include #include #include #include -#include #include #include #include #include #include #include +#include -#include "msm_serial.h" +#define UART_MR1 0x0000 + +#define UART_MR1_AUTO_RFR_LEVEL0 0x3F +#define UART_MR1_AUTO_RFR_LEVEL1 0x3FF00 +#define UART_DM_MR1_AUTO_RFR_LEVEL1 0xFFFFFF00 +#define UART_MR1_RX_RDY_CTL BIT(7) +#define UART_MR1_CTS_CTL BIT(6) + +#define UART_MR2 0x0004 +#define UART_MR2_ERROR_MODE BIT(6) +#define UART_MR2_BITS_PER_CHAR 0x30 +#define UART_MR2_BITS_PER_CHAR_5 (0x0 << 4) +#define UART_MR2_BITS_PER_CHAR_6 (0x1 << 4) +#define UART_MR2_BITS_PER_CHAR_7 (0x2 << 4) +#define UART_MR2_BITS_PER_CHAR_8 (0x3 << 4) +#define UART_MR2_STOP_BIT_LEN_ONE (0x1 << 2) +#define UART_MR2_STOP_BIT_LEN_TWO (0x3 << 2) +#define UART_MR2_PARITY_MODE_NONE 0x0 +#define UART_MR2_PARITY_MODE_ODD 0x1 +#define UART_MR2_PARITY_MODE_EVEN 0x2 +#define UART_MR2_PARITY_MODE_SPACE 0x3 +#define UART_MR2_PARITY_MODE 0x3 + +#define UART_CSR 0x0008 + +#define UART_TF 0x000C +#define UARTDM_TF 0x0070 + +#define UART_CR 0x0010 +#define UART_CR_CMD_NULL (0 << 4) +#define UART_CR_CMD_RESET_RX (1 << 4) +#define UART_CR_CMD_RESET_TX (2 << 4) +#define UART_CR_CMD_RESET_ERR (3 << 4) +#define UART_CR_CMD_RESET_BREAK_INT (4 << 4) +#define UART_CR_CMD_START_BREAK (5 << 4) +#define UART_CR_CMD_STOP_BREAK (6 << 4) +#define UART_CR_CMD_RESET_CTS (7 << 4) +#define UART_CR_CMD_RESET_STALE_INT (8 << 4) +#define UART_CR_CMD_PACKET_MODE (9 << 4) +#define UART_CR_CMD_MODE_RESET (12 << 4) +#define UART_CR_CMD_SET_RFR (13 << 4) +#define UART_CR_CMD_RESET_RFR (14 << 4) +#define UART_CR_CMD_PROTECTION_EN (16 << 4) +#define UART_CR_CMD_STALE_EVENT_DISABLE (6 << 8) +#define UART_CR_CMD_STALE_EVENT_ENABLE (80 << 4) +#define UART_CR_CMD_FORCE_STALE (4 << 8) +#define UART_CR_CMD_RESET_TX_READY (3 << 8) +#define UART_CR_TX_DISABLE BIT(3) +#define UART_CR_TX_ENABLE BIT(2) +#define UART_CR_RX_DISABLE BIT(1) +#define UART_CR_RX_ENABLE BIT(0) +#define UART_CR_CMD_RESET_RXBREAK_START ((1 << 11) | (2 << 4)) + +#define UART_IMR 0x0014 +#define UART_IMR_TXLEV BIT(0) +#define UART_IMR_RXSTALE BIT(3) +#define UART_IMR_RXLEV BIT(4) +#define UART_IMR_DELTA_CTS BIT(5) +#define UART_IMR_CURRENT_CTS BIT(6) +#define UART_IMR_RXBREAK_START BIT(10) + +#define UART_IPR_RXSTALE_LAST 0x20 +#define UART_IPR_STALE_LSB 0x1F +#define UART_IPR_STALE_TIMEOUT_MSB 0x3FF80 +#define UART_DM_IPR_STALE_TIMEOUT_MSB 0xFFFFFF80 + +#define UART_IPR 0x0018 +#define UART_TFWR 0x001C +#define UART_RFWR 0x0020 +#define UART_HCR 0x0024 + +#define UART_MREG 0x0028 +#define UART_NREG 0x002C +#define UART_DREG 0x0030 +#define UART_MNDREG 0x0034 +#define UART_IRDA 0x0038 +#define UART_MISR_MODE 0x0040 +#define UART_MISR_RESET 0x0044 +#define UART_MISR_EXPORT 0x0048 +#define UART_MISR_VAL 0x004C +#define UART_TEST_CTRL 0x0050 + +#define UART_SR 0x0008 +#define UART_SR_HUNT_CHAR BIT(7) +#define UART_SR_RX_BREAK BIT(6) +#define UART_SR_PAR_FRAME_ERR BIT(5) +#define UART_SR_OVERRUN BIT(4) +#define UART_SR_TX_EMPTY BIT(3) +#define UART_SR_TX_READY BIT(2) +#define UART_SR_RX_FULL BIT(1) +#define UART_SR_RX_READY BIT(0) + +#define UART_RF 0x000C +#define UARTDM_RF 0x0070 +#define UART_MISR 0x0010 +#define UART_ISR 0x0014 +#define UART_ISR_TX_READY BIT(7) + +#define UARTDM_RXFS 0x50 +#define UARTDM_RXFS_BUF_SHIFT 0x7 +#define UARTDM_RXFS_BUF_MASK 0x7 + +#define UARTDM_DMEN 0x3C +#define UARTDM_DMEN_RX_SC_ENABLE BIT(5) +#define UARTDM_DMEN_TX_SC_ENABLE BIT(4) + +#define UARTDM_DMEN_TX_BAM_ENABLE BIT(2) /* UARTDM_1P4 */ +#define UARTDM_DMEN_TX_DM_ENABLE BIT(0) /* < UARTDM_1P4 */ + +#define UARTDM_DMEN_RX_BAM_ENABLE BIT(3) /* UARTDM_1P4 */ +#define UARTDM_DMEN_RX_DM_ENABLE BIT(1) /* < UARTDM_1P4 */ + +#define UARTDM_DMRX 0x34 +#define UARTDM_NCF_TX 0x40 +#define UARTDM_RX_TOTAL_SNAP 0x38 #define UARTDM_BURST_SIZE 16 /* in bytes */ #define UARTDM_TX_AIGN(x) ((x) & ~0x3) /* valid for > 1p3 */ @@ -78,10 +192,65 @@ struct msm_dma rx_dma; }; +#define UART_TO_MSM(uart_port) container_of(uart_port, struct msm_port, uart) + +static +void msm_write(struct uart_port *port, unsigned int val, unsigned int off) +{ + writel_relaxed_no_log(val, port->membase + off); +} + +static +unsigned int msm_read(struct uart_port *port, unsigned int off) +{ + return readl_relaxed_no_log(port->membase + off); +} + +/* + * Setup the MND registers to use the TCXO clock. + */ +static void msm_serial_set_mnd_regs_tcxo(struct uart_port *port) +{ + msm_write(port, 0x06, UART_MREG); + msm_write(port, 0xF1, UART_NREG); + msm_write(port, 0x0F, UART_DREG); + msm_write(port, 0x1A, UART_MNDREG); + port->uartclk = 1843200; +} + +/* + * Setup the MND registers to use the TCXO clock divided by 4. + */ +static void msm_serial_set_mnd_regs_tcxoby4(struct uart_port *port) +{ + msm_write(port, 0x18, UART_MREG); + msm_write(port, 0xF6, UART_NREG); + msm_write(port, 0x0F, UART_DREG); + msm_write(port, 0x0A, UART_MNDREG); + port->uartclk = 1843200; +} + +static void msm_serial_set_mnd_regs(struct uart_port *port) +{ + struct msm_port *msm_port = UART_TO_MSM(port); + + /* + * These registers don't exist so we change the clk input rate + * on uartdm hardware instead + */ + if (msm_port->is_uartdm) + return; + + if (port->uartclk == 19200000) + msm_serial_set_mnd_regs_tcxo(port); + else if (port->uartclk == 4800000) + msm_serial_set_mnd_regs_tcxoby4(port); +} + static void msm_handle_tx(struct uart_port *port); static void msm_start_rx_dma(struct msm_port *msm_port); -void msm_stop_dma(struct uart_port *port, struct msm_dma *dma) +static void msm_stop_dma(struct uart_port *port, struct msm_dma *dma) { struct device *dev = port->dev; unsigned int mapped; @@ -134,15 +303,17 @@ struct device *dev = msm_port->uart.dev; struct dma_slave_config conf; struct msm_dma *dma; + struct dma_chan *dma_chan; u32 crci = 0; int ret; dma = &msm_port->tx_dma; /* allocate DMA resources, if available */ - dma->chan = dma_request_slave_channel_reason(dev, "tx"); - if (IS_ERR(dma->chan)) + dma_chan = dma_request_slave_channel_reason(dev, "tx"); + if (IS_ERR(dma_chan)) goto no_tx; + dma->chan = dma_chan; of_property_read_u32(dev->of_node, "qcom,tx-crci", &crci); @@ -177,15 +348,17 @@ struct device *dev = msm_port->uart.dev; struct dma_slave_config conf; struct msm_dma *dma; + struct dma_chan *dma_chan; u32 crci = 0; int ret; dma = &msm_port->rx_dma; /* allocate DMA resources, if available */ - dma->chan = dma_request_slave_channel_reason(dev, "rx"); - if (IS_ERR(dma->chan)) + dma_chan = dma_request_slave_channel_reason(dev, "rx"); + if (IS_ERR(dma_chan)) goto no_rx; + dma->chan = dma_chan; of_property_read_u32(dev->of_node, "qcom,rx-crci", &crci); @@ -388,10 +561,6 @@ val &= ~dma->enable_bit; msm_write(port, val, UARTDM_DMEN); - /* Restore interrupts */ - msm_port->imr |= UART_IMR_RXLEV | UART_IMR_RXSTALE; - msm_write(port, msm_port->imr, UART_IMR); - if (msm_read(port, UART_SR) & UART_SR_OVERRUN) { port->icount.overrun++; tty_insert_flip_char(tport, 0, TTY_OVERRUN); @@ -861,37 +1030,72 @@ }; static const struct msm_baud_map * -msm_find_best_baud(struct uart_port *port, unsigned int baud) +msm_find_best_baud(struct uart_port *port, unsigned int baud, + unsigned long *rate) { - unsigned int i, divisor; - const struct msm_baud_map *entry; + struct msm_port *msm_port = UART_TO_MSM(port); + unsigned int divisor, result; + unsigned long target, old, best_rate = 0, diff, best_diff = ULONG_MAX; + const struct msm_baud_map *entry, *end, *best; static const struct msm_baud_map table[] = { - { 1536, 0x00, 1 }, - { 768, 0x11, 1 }, - { 384, 0x22, 1 }, - { 192, 0x33, 1 }, - { 96, 0x44, 1 }, - { 48, 0x55, 1 }, - { 32, 0x66, 1 }, - { 24, 0x77, 1 }, - { 16, 0x88, 1 }, - { 12, 0x99, 6 }, - { 8, 0xaa, 6 }, - { 6, 0xbb, 6 }, - { 4, 0xcc, 6 }, - { 3, 0xdd, 8 }, - { 2, 0xee, 16 }, { 1, 0xff, 31 }, - { 0, 0xff, 31 }, + { 2, 0xee, 16 }, + { 3, 0xdd, 8 }, + { 4, 0xcc, 6 }, + { 6, 0xbb, 6 }, + { 8, 0xaa, 6 }, + { 12, 0x99, 6 }, + { 16, 0x88, 1 }, + { 24, 0x77, 1 }, + { 32, 0x66, 1 }, + { 48, 0x55, 1 }, + { 96, 0x44, 1 }, + { 192, 0x33, 1 }, + { 384, 0x22, 1 }, + { 768, 0x11, 1 }, + { 1536, 0x00, 1 }, }; - divisor = uart_get_divisor(port, baud); + best = table; /* Default to smallest divider */ + target = clk_round_rate(msm_port->clk, 16 * baud); + divisor = DIV_ROUND_CLOSEST(target, 16 * baud); + + end = table + ARRAY_SIZE(table); + entry = table; + while (entry < end) { + if (entry->divisor <= divisor) { + result = target / entry->divisor / 16; + diff = abs(result - baud); + + /* Keep track of best entry */ + if (diff < best_diff) { + best_diff = diff; + best = entry; + best_rate = target; + } - for (i = 0, entry = table; i < ARRAY_SIZE(table); i++, entry++) - if (entry->divisor <= divisor) + if (result == baud) + break; + } else if (entry->divisor > divisor) { + old = target; + target = clk_round_rate(msm_port->clk, old + 1); + /* + * The rate didn't get any faster so we can't do + * better at dividing it down + */ + if (target == old) break; - return entry; /* Default to smallest divider */ + /* Start the divisor search over at this new rate */ + entry = table; + divisor = DIV_ROUND_CLOSEST(target, 16 * baud); + continue; + } + entry++; + } + + *rate = best_rate; + return best; } static int msm_set_baud_rate(struct uart_port *port, unsigned int baud, @@ -900,22 +1104,20 @@ unsigned int rxstale, watermark, mask; struct msm_port *msm_port = UART_TO_MSM(port); const struct msm_baud_map *entry; - unsigned long flags; - - entry = msm_find_best_baud(port, baud); - - msm_write(port, entry->code, UART_CSR); - - if (baud > 460800) - port->uartclk = baud * 16; + unsigned long flags, rate; flags = *saved_flags; spin_unlock_irqrestore(&port->lock, flags); - clk_set_rate(msm_port->clk, port->uartclk); + entry = msm_find_best_baud(port, baud, &rate); + clk_set_rate(msm_port->clk, rate); + baud = rate / 16 / entry->divisor; spin_lock_irqsave(&port->lock, flags); *saved_flags = flags; + port->uartclk = rate; + + msm_write(port, entry->code, UART_CSR); /* RX stale watermark */ rxstale = entry->rxstale; @@ -959,15 +1161,6 @@ return baud; } -static void msm_init_clock(struct uart_port *port) -{ - struct msm_port *msm_port = UART_TO_MSM(port); - - clk_prepare_enable(msm_port->clk); - clk_prepare_enable(msm_port->pclk); - msm_serial_set_mnd_regs(port); -} - static int msm_startup(struct uart_port *port) { struct msm_port *msm_port = UART_TO_MSM(port); @@ -977,12 +1170,19 @@ snprintf(msm_port->name, sizeof(msm_port->name), "msm_serial%d", port->line); - ret = request_irq(port->irq, msm_uart_irq, IRQF_TRIGGER_HIGH, - msm_port->name, port); - if (unlikely(ret)) + /* + * UART clk must be kept enabled to + * avoid losing received character + */ + ret = clk_prepare_enable(msm_port->clk); + if (ret) return ret; - msm_init_clock(port); + ret = clk_prepare_enable(msm_port->pclk); + if (ret) + goto err_pclk; + + msm_serial_set_mnd_regs(port); if (likely(port->fifosize > 12)) rfr_level = port->fifosize - 12; @@ -1008,7 +1208,23 @@ msm_request_rx_dma(msm_port, msm_port->uart.mapbase); } + ret = request_irq(port->irq, msm_uart_irq, IRQF_TRIGGER_HIGH, + msm_port->name, port); + if (unlikely(ret)) + goto err_irq; + return 0; + +err_irq: + if (msm_port->is_uartdm) + msm_release_dma(msm_port); + + clk_disable_unprepare(msm_port->pclk); + +err_pclk: + clk_disable_unprepare(msm_port->clk); + + return ret; } static void msm_shutdown(struct uart_port *port) @@ -1021,6 +1237,7 @@ if (msm_port->is_uartdm) msm_release_dma(msm_port); + clk_disable_unprepare(msm_port->pclk); clk_disable_unprepare(msm_port->clk); free_irq(port->irq, port); @@ -1187,8 +1404,16 @@ switch (state) { case 0: - clk_prepare_enable(msm_port->clk); - clk_prepare_enable(msm_port->pclk); + /* + * UART clk must be kept enabled to + * avoid losing received character + */ + if (clk_prepare_enable(msm_port->clk)) + return; + if (clk_prepare_enable(msm_port->pclk)) { + clk_disable_unprepare(msm_port->clk); + return; + } break; case 3: clk_disable_unprepare(msm_port->clk); @@ -1391,6 +1616,7 @@ int j; unsigned int num_chars; char buf[4] = { 0 }; + const u32 *buffer; if (is_uartdm) num_chars = min(count - i, (unsigned int)sizeof(buf)); @@ -1415,7 +1641,8 @@ while (!(msm_read(port, UART_SR) & UART_SR_TX_READY)) cpu_relax(); - iowrite32_rep(tf, buf, 1); + buffer = (const u32 *)buf; + writel_relaxed_no_log(*buffer, tf); i += num_chars; } spin_unlock(&port->lock); @@ -1451,7 +1678,7 @@ if (unlikely(!port->membase)) return -ENXIO; - msm_init_clock(port); + msm_serial_set_mnd_regs(port); if (options) uart_parse_options(options, &baud, &parity, &bits, &flow); @@ -1478,7 +1705,6 @@ device->con->write = msm_serial_early_write; return 0; } -EARLYCON_DECLARE(msm_serial, msm_serial_early_console_setup); OF_EARLYCON_DECLARE(msm_serial, "qcom,msm-uart", msm_serial_early_console_setup); @@ -1500,7 +1726,6 @@ device->con->write = msm_serial_early_write_dm; return 0; } -EARLYCON_DECLARE(msm_serial_dm, msm_serial_early_console_setup_dm); OF_EARLYCON_DECLARE(msm_serial_dm, "qcom,msm-uartdm", msm_serial_early_console_setup_dm); @@ -1579,8 +1804,6 @@ msm_port->pclk = devm_clk_get(&pdev->dev, "iface"); if (IS_ERR(msm_port->pclk)) return PTR_ERR(msm_port->pclk); - - clk_set_rate(msm_port->clk, 1843200); } port->uartclk = clk_get_rate(msm_port->clk); @@ -1617,12 +1840,37 @@ }; MODULE_DEVICE_TABLE(of, msm_match_table); +#ifdef CONFIG_PM_SLEEP +static int msm_serial_suspend(struct device *dev) +{ + struct uart_port *port = dev_get_drvdata(dev); + + uart_suspend_port(&msm_uart_driver, port); + + return 0; +} + +static int msm_serial_resume(struct device *dev) +{ + struct uart_port *port = dev_get_drvdata(dev); + + uart_resume_port(&msm_uart_driver, port); + + return 0; +} +#endif + +static const struct dev_pm_ops msm_serial_pm_ops = { + SET_SYSTEM_SLEEP_PM_OPS(msm_serial_suspend, msm_serial_resume) +}; + static struct platform_driver msm_platform_driver = { .remove = msm_serial_remove, .probe = msm_serial_probe, .driver = { .name = "msm_serial", .of_match_table = msm_match_table, + .pm = &msm_serial_pm_ops, }, }; diff -ruw linux-4.4.115/drivers/tty/serial/serial_core.c linux-4.4.115-fbx/drivers/tty/serial/serial_core.c --- linux-4.4.115/drivers/tty/serial/serial_core.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/tty/serial/serial_core.c 2019-01-22 16:16:27.207279948 +0100 @@ -95,6 +95,9 @@ struct uart_state *state = tty->driver_data; struct uart_port *port = state->uart_port; + if (port->ops->wake_peer) + port->ops->wake_peer(port); + if (!uart_tx_stopped(port)) port->ops->start_tx(port); } diff -ruw linux-4.4.115/drivers/tty/sysrq.c linux-4.4.115-fbx/drivers/tty/sysrq.c --- linux-4.4.115/drivers/tty/sysrq.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/tty/sysrq.c 2019-01-22 16:16:27.219280057 +0100 @@ -55,10 +55,11 @@ static int __read_mostly sysrq_enabled = CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE; static bool __read_mostly sysrq_always_enabled; -static bool sysrq_on(void) +bool sysrq_on(void) { return sysrq_enabled || sysrq_always_enabled; } +EXPORT_SYMBOL(sysrq_on); /* * A value of 1 means 'all', other nonzero values are an op mask: diff -ruw linux-4.4.115/drivers/uio/Kconfig linux-4.4.115-fbx/drivers/uio/Kconfig --- linux-4.4.115/drivers/uio/Kconfig 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/uio/Kconfig 2019-01-22 16:16:27.223280093 +0100 @@ -155,4 +155,11 @@ If you compile this as a module, it will be called uio_mf624. +config UIO_MSM_SHAREDMEM + bool "MSM shared memory driver" + default n + help + Provides the clients with their respective alloted shared memory + addresses which are used as transport buffer. + endif diff -ruw linux-4.4.115/drivers/uio/Makefile linux-4.4.115-fbx/drivers/uio/Makefile --- linux-4.4.115/drivers/uio/Makefile 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/uio/Makefile 2019-01-22 16:16:27.223280093 +0100 @@ -9,3 +9,4 @@ obj-$(CONFIG_UIO_PRUSS) += uio_pruss.o obj-$(CONFIG_UIO_MF624) += uio_mf624.o obj-$(CONFIG_UIO_FSL_ELBC_GPCM) += uio_fsl_elbc_gpcm.o +obj-$(CONFIG_UIO_MSM_SHAREDMEM) += msm_sharedmem/ diff -ruw linux-4.4.115/drivers/usb/common/common.c linux-4.4.115-fbx/drivers/usb/common/common.c --- linux-4.4.115/drivers/usb/common/common.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/usb/common/common.c 2019-01-22 16:16:27.235280202 +0100 @@ -34,6 +34,7 @@ [OTG_STATE_B_PERIPHERAL] = "b_peripheral", [OTG_STATE_B_WAIT_ACON] = "b_wait_acon", [OTG_STATE_B_HOST] = "b_host", + [OTG_STATE_B_SUSPEND] = "b_suspend", }; if (state < 0 || state >= ARRAY_SIZE(names)) diff -ruw linux-4.4.115/drivers/usb/core/config.c linux-4.4.115-fbx/drivers/usb/core/config.c --- linux-4.4.115/drivers/usb/core/config.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/usb/core/config.c 2019-10-29 09:26:24.965216115 +0100 @@ -732,18 +732,21 @@ return; if (dev->rawdescriptors) { - for (i = 0; i < dev->descriptor.bNumConfigurations; i++) + for (i = 0; i < dev->descriptor.bNumConfigurations && + i < USB_MAXCONFIG; i++) kfree(dev->rawdescriptors[i]); kfree(dev->rawdescriptors); dev->rawdescriptors = NULL; } - for (c = 0; c < dev->descriptor.bNumConfigurations; c++) { + for (c = 0; c < dev->descriptor.bNumConfigurations && + c < USB_MAXCONFIG; c++) { struct usb_host_config *cf = &dev->config[c]; kfree(cf->string); - for (i = 0; i < cf->desc.bNumInterfaces; i++) { + for (i = 0; i < cf->desc.bNumInterfaces && + i < USB_MAXINTERFACES; i++) { if (cf->intf_cache[i]) kref_put(&cf->intf_cache[i]->ref, usb_release_interface_cache); @@ -984,6 +987,15 @@ case USB_PTM_CAP_TYPE: dev->bos->ptm_cap = (struct usb_ptm_cap_descriptor *)buffer; + break; + case USB_CAP_TYPE_CONFIG_SUMMARY: + /* one such desc per configuration */ + if (!dev->bos->num_config_summary_desc) + dev->bos->config_summary = + (struct usb_config_summary_descriptor *)buffer; + + dev->bos->num_config_summary_desc++; + break; default: break; } diff -ruw linux-4.4.115/drivers/usb/core/driver.c linux-4.4.115-fbx/drivers/usb/core/driver.c --- linux-4.4.115/drivers/usb/core/driver.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/usb/core/driver.c 2019-10-29 09:26:24.965216115 +0100 @@ -1459,6 +1459,9 @@ { struct usb_device *udev = to_usb_device(dev); + if (udev->bus->skip_resume && udev->state == USB_STATE_SUSPENDED) + return 0; + unbind_no_pm_drivers_interfaces(udev); /* From now on we are sure all drivers support suspend/resume @@ -1488,6 +1491,15 @@ struct usb_device *udev = to_usb_device(dev); int status; + /* + * Some buses would like to keep their devices in suspend + * state after system resume. Their resume happen when + * a remote wakeup is detected or interface driver start + * I/O. + */ + if (udev->bus->skip_resume) + return 0; + /* For all calls, take the device back to full power and * tell the PM core in case it was autosuspended previously. * Unbind the interfaces that will need rebinding later, diff -ruw linux-4.4.115/drivers/usb/core/generic.c linux-4.4.115-fbx/drivers/usb/core/generic.c --- linux-4.4.115/drivers/usb/core/generic.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/usb/core/generic.c 2019-10-29 09:26:24.969216154 +0100 @@ -19,6 +19,8 @@ #include #include +#include +#include #include "usb.h" static inline const char *plural(int n) @@ -40,6 +42,36 @@ && desc->bInterfaceProtocol == 1; } +static int usb_audio_max_rev_config(struct usb_host_bos *bos) +{ + int desc_cnt, func_cnt, numfunc; + int num_cfg_desc; + struct usb_config_summary_descriptor *conf_summary; + + if (!bos || !bos->config_summary) + goto done; + + conf_summary = bos->config_summary; + num_cfg_desc = bos->num_config_summary_desc; + + for (desc_cnt = 0; desc_cnt < num_cfg_desc; desc_cnt++) { + numfunc = conf_summary->bNumFunctions; + for (func_cnt = 0; func_cnt < numfunc; func_cnt++) { + /* look for BADD 3.0 */ + if (conf_summary->cs_info[func_cnt].bClass == + USB_CLASS_AUDIO && + conf_summary->cs_info[func_cnt].bProtocol == + UAC_VERSION_3 && + conf_summary->cs_info[func_cnt].bSubClass != + FULL_ADC_PROFILE) + return conf_summary->bConfigurationValue; + } + } + +done: + return -EINVAL; +} + int usb_choose_configuration(struct usb_device *udev) { int i; @@ -130,7 +162,6 @@ best = c; break; } - /* If all the remaining configs are vendor-specific, * choose the first one. */ else if (!best) @@ -143,6 +174,9 @@ insufficient_power, plural(insufficient_power)); if (best) { + /* choose usb audio class preferred config if available */ + i = usb_audio_max_rev_config(udev->bos); + if (i < 0) i = best->desc.bConfigurationValue; dev_dbg(&udev->dev, "configuration #%d chosen from %d choice%s\n", diff -ruw linux-4.4.115/drivers/usb/core/hcd.c linux-4.4.115-fbx/drivers/usb/core/hcd.c --- linux-4.4.115/drivers/usb/core/hcd.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/usb/core/hcd.c 2019-10-29 09:26:24.969216154 +0100 @@ -2205,8 +2205,64 @@ return hcd->driver->get_frame_number (hcd); } +int usb_hcd_sec_event_ring_setup(struct usb_device *udev, + unsigned intr_num) +{ + struct usb_hcd *hcd = bus_to_hcd(udev->bus); + + if (!HCD_RH_RUNNING(hcd)) + return 0; + + return hcd->driver->sec_event_ring_setup(hcd, intr_num); +} + +int usb_hcd_sec_event_ring_cleanup(struct usb_device *udev, + unsigned intr_num) +{ + struct usb_hcd *hcd = bus_to_hcd(udev->bus); + + if (!HCD_RH_RUNNING(hcd)) + return 0; + + return hcd->driver->sec_event_ring_cleanup(hcd, intr_num); +} + /*-------------------------------------------------------------------------*/ +dma_addr_t +usb_hcd_get_sec_event_ring_dma_addr(struct usb_device *udev, + unsigned intr_num) +{ + struct usb_hcd *hcd = bus_to_hcd(udev->bus); + + if (!HCD_RH_RUNNING(hcd)) + return 0; + + return hcd->driver->get_sec_event_ring_dma_addr(hcd, intr_num); +} + +dma_addr_t +usb_hcd_get_xfer_ring_dma_addr(struct usb_device *udev, + struct usb_host_endpoint *ep) +{ + struct usb_hcd *hcd = bus_to_hcd(udev->bus); + + if (!HCD_RH_RUNNING(hcd)) + return 0; + + return hcd->driver->get_xfer_ring_dma_addr(hcd, udev, ep); +} + +int usb_hcd_get_controller_id(struct usb_device *udev) +{ + struct usb_hcd *hcd = bus_to_hcd(udev->bus); + + if (!HCD_RH_RUNNING(hcd)) + return -EINVAL; + + return hcd->driver->get_core_id(hcd); +} + #ifdef CONFIG_PM int hcd_bus_suspend(struct usb_device *rhdev, pm_message_t msg) @@ -2461,6 +2517,7 @@ } spin_unlock_irqrestore (&hcd_root_hub_lock, flags); /* Make sure that the other roothub is also deallocated. */ + usb_atomic_notify_dead_bus(&hcd->self); } EXPORT_SYMBOL_GPL (usb_hc_died); @@ -2946,6 +3003,9 @@ cancel_work_sync(&hcd->wakeup_work); #endif + /* handle any pending hub events before XHCI stops */ + usb_flush_hub_wq(); + mutex_lock(&usb_bus_list_lock); usb_disconnect(&rhdev); /* Sets rhdev to NULL */ mutex_unlock(&usb_bus_list_lock); diff -ruw linux-4.4.115/drivers/usb/core/hub.c linux-4.4.115-fbx/drivers/usb/core/hub.c --- linux-4.4.115/drivers/usb/core/hub.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/usb/core/hub.c 2019-10-29 09:26:24.969216154 +0100 @@ -48,6 +48,11 @@ /* synchronize hub-port add/remove and peering operations */ DEFINE_MUTEX(usb_port_peer_mutex); +static bool skip_extended_resume_delay = 1; +module_param(skip_extended_resume_delay, bool, S_IRUGO | S_IWUSR); +MODULE_PARM_DESC(skip_extended_resume_delay, + "removes extra delay added to finish bus resume"); + /* cycle leds on hubs that aren't blinking for attention */ static bool blinkenlights = 0; module_param(blinkenlights, bool, S_IRUGO); @@ -620,6 +625,12 @@ kick_hub_wq(hub); } +void usb_flush_hub_wq(void) +{ + flush_workqueue(hub_wq); +} +EXPORT_SYMBOL(usb_flush_hub_wq); + /* * Let the USB core know that a USB 3.0 device has sent a Function Wake Device * Notification, which indicates it had initiated remote wakeup. @@ -3376,7 +3387,9 @@ /* drive resume for USB_RESUME_TIMEOUT msec */ dev_dbg(&udev->dev, "usb %sresume\n", (PMSG_IS_AUTO(msg) ? "auto-" : "")); - msleep(USB_RESUME_TIMEOUT); + if (!skip_extended_resume_delay) + usleep_range(USB_RESUME_TIMEOUT * 1000, + (USB_RESUME_TIMEOUT + 1) * 1000); /* Virtual root hubs can trigger on GET_PORT_STATUS to * stop resume signaling. Then finish the resume @@ -3385,7 +3398,7 @@ status = hub_port_status(hub, port1, &portstatus, &portchange); /* TRSMRCY = 10 msec */ - msleep(10); + usleep_range(10000, 10500); } SuspendCleared: @@ -4281,6 +4294,8 @@ enum usb_device_speed oldspeed = udev->speed; const char *speed; int devnum = udev->devnum; + char *error_event[] = { + "USB_DEVICE_ERROR=Device_No_Response", NULL }; /* root hub ports have a slightly longer reset period * (from USB 2.0 spec, section 7.1.7.5) @@ -4454,6 +4469,8 @@ if (r != -ENODEV) dev_err(&udev->dev, "device descriptor read/64, error %d\n", r); + kobject_uevent_env(&udev->parent->dev.kobj, + KOBJ_CHANGE, error_event); retval = -EMSGSIZE; continue; } @@ -4506,6 +4523,8 @@ dev_err(&udev->dev, "device descriptor read/8, error %d\n", retval); + kobject_uevent_env(&udev->parent->dev.kobj, + KOBJ_CHANGE, error_event); if (retval >= 0) retval = -EMSGSIZE; } else { diff -ruw linux-4.4.115/drivers/usb/core/message.c linux-4.4.115-fbx/drivers/usb/core/message.c --- linux-4.4.115/drivers/usb/core/message.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/usb/core/message.c 2019-10-29 09:26:24.973216194 +0100 @@ -12,6 +12,7 @@ #include #include #include +#include #include #include /* for usbcore internals */ #include @@ -2027,3 +2028,159 @@ return 0; } EXPORT_SYMBOL_GPL(usb_driver_set_configuration); + +/** + * cdc_parse_cdc_header - parse the extra headers present in CDC devices + * @hdr: the place to put the results of the parsing + * @intf: the interface for which parsing is requested + * @buffer: pointer to the extra headers to be parsed + * @buflen: length of the extra headers + * + * This evaluates the extra headers present in CDC devices which + * bind the interfaces for data and control and provide details + * about the capabilities of the device. + * + * Return: number of descriptors parsed or -EINVAL + * if the header is contradictory beyond salvage + */ + +int cdc_parse_cdc_header(struct usb_cdc_parsed_header *hdr, + struct usb_interface *intf, + u8 *buffer, + int buflen) +{ + /* duplicates are ignored */ + struct usb_cdc_union_desc *union_header = NULL; + + /* duplicates are not tolerated */ + struct usb_cdc_header_desc *header = NULL; + struct usb_cdc_ether_desc *ether = NULL; + struct usb_cdc_mdlm_detail_desc *detail = NULL; + struct usb_cdc_mdlm_desc *desc = NULL; + + unsigned int elength; + int cnt = 0; + + memset(hdr, 0x00, sizeof(struct usb_cdc_parsed_header)); + hdr->phonet_magic_present = false; + while (buflen > 0) { + elength = buffer[0]; + if (!elength) { + dev_err(&intf->dev, "skipping garbage byte\n"); + elength = 1; + goto next_desc; + } + if ((buflen < elength) || (elength < 3)) { + dev_err(&intf->dev, "invalid descriptor buffer length\n"); + break; + } + if (buffer[1] != USB_DT_CS_INTERFACE) { + dev_err(&intf->dev, "skipping garbage\n"); + goto next_desc; + } + + switch (buffer[2]) { + case USB_CDC_UNION_TYPE: /* we've found it */ + if (elength < sizeof(struct usb_cdc_union_desc)) + goto next_desc; + if (union_header) { + dev_err(&intf->dev, "More than one union descriptor, skipping ...\n"); + goto next_desc; + } + union_header = (struct usb_cdc_union_desc *)buffer; + break; + case USB_CDC_COUNTRY_TYPE: + if (elength < sizeof(struct usb_cdc_country_functional_desc)) + goto next_desc; + hdr->usb_cdc_country_functional_desc = + (struct usb_cdc_country_functional_desc *)buffer; + break; + case USB_CDC_HEADER_TYPE: + if (elength != sizeof(struct usb_cdc_header_desc)) + goto next_desc; + if (header) + return -EINVAL; + header = (struct usb_cdc_header_desc *)buffer; + break; + case USB_CDC_ACM_TYPE: + if (elength < sizeof(struct usb_cdc_acm_descriptor)) + goto next_desc; + hdr->usb_cdc_acm_descriptor = + (struct usb_cdc_acm_descriptor *)buffer; + break; + case USB_CDC_ETHERNET_TYPE: + if (elength != sizeof(struct usb_cdc_ether_desc)) + goto next_desc; + if (ether) + return -EINVAL; + ether = (struct usb_cdc_ether_desc *)buffer; + break; + case USB_CDC_CALL_MANAGEMENT_TYPE: + if (elength < sizeof(struct usb_cdc_call_mgmt_descriptor)) + goto next_desc; + hdr->usb_cdc_call_mgmt_descriptor = + (struct usb_cdc_call_mgmt_descriptor *)buffer; + break; + case USB_CDC_DMM_TYPE: + if (elength < sizeof(struct usb_cdc_dmm_desc)) + goto next_desc; + hdr->usb_cdc_dmm_desc = + (struct usb_cdc_dmm_desc *)buffer; + break; + case USB_CDC_MDLM_TYPE: + if (elength < sizeof(struct usb_cdc_mdlm_desc *)) + goto next_desc; + if (desc) + return -EINVAL; + desc = (struct usb_cdc_mdlm_desc *)buffer; + break; + case USB_CDC_MDLM_DETAIL_TYPE: + if (elength < sizeof(struct usb_cdc_mdlm_detail_desc *)) + goto next_desc; + if (detail) + return -EINVAL; + detail = (struct usb_cdc_mdlm_detail_desc *)buffer; + break; + case USB_CDC_NCM_TYPE: + if (elength < sizeof(struct usb_cdc_ncm_desc)) + goto next_desc; + hdr->usb_cdc_ncm_desc = (struct usb_cdc_ncm_desc *)buffer; + break; + case USB_CDC_MBIM_TYPE: + if (elength < sizeof(struct usb_cdc_mbim_desc)) + goto next_desc; + + hdr->usb_cdc_mbim_desc = (struct usb_cdc_mbim_desc *)buffer; + break; + case USB_CDC_MBIM_EXTENDED_TYPE: + if (elength < sizeof(struct usb_cdc_mbim_extended_desc)) + break; + hdr->usb_cdc_mbim_extended_desc = + (struct usb_cdc_mbim_extended_desc *)buffer; + break; + case CDC_PHONET_MAGIC_NUMBER: + hdr->phonet_magic_present = true; + break; + default: + /* + * there are LOTS more CDC descriptors that + * could legitimately be found here. + */ + dev_dbg(&intf->dev, "Ignoring descriptor: type %02x, length %ud\n", + buffer[2], elength); + goto next_desc; + } + cnt++; +next_desc: + buflen -= elength; + buffer += elength; + } + hdr->usb_cdc_union_desc = union_header; + hdr->usb_cdc_header_desc = header; + hdr->usb_cdc_mdlm_detail_desc = detail; + hdr->usb_cdc_mdlm_desc = desc; + hdr->usb_cdc_ether_desc = ether; + return cnt; +} + +EXPORT_SYMBOL(cdc_parse_cdc_header); diff -ruw linux-4.4.115/drivers/usb/core/notify.c linux-4.4.115-fbx/drivers/usb/core/notify.c --- linux-4.4.115/drivers/usb/core/notify.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/usb/core/notify.c 2019-01-22 16:16:27.243280274 +0100 @@ -17,6 +17,7 @@ #include "usb.h" static BLOCKING_NOTIFIER_HEAD(usb_notifier_list); +static ATOMIC_NOTIFIER_HEAD(usb_atomic_notifier_list); /** * usb_register_notify - register a notifier callback whenever a usb change happens @@ -67,3 +68,33 @@ { blocking_notifier_call_chain(&usb_notifier_list, USB_BUS_REMOVE, ubus); } + +/** + * usb_register_atomic_notify - register a atomic notifier callback whenever a + * HC dies + * @nb: pointer to the atomic notifier block for the callback events. + * + */ +void usb_register_atomic_notify(struct notifier_block *nb) +{ + atomic_notifier_chain_register(&usb_atomic_notifier_list, nb); +} +EXPORT_SYMBOL_GPL(usb_register_atomic_notify); + +/** + * usb_unregister_atomic_notify - unregister a atomic notifier callback + * @nb: pointer to the notifier block for the callback events. + * + */ +void usb_unregister_atomic_notify(struct notifier_block *nb) +{ + atomic_notifier_chain_unregister(&usb_atomic_notifier_list, nb); +} +EXPORT_SYMBOL_GPL(usb_unregister_atomic_notify); + + +void usb_atomic_notify_dead_bus(struct usb_bus *ubus) +{ + atomic_notifier_call_chain(&usb_atomic_notifier_list, USB_BUS_DIED, + ubus); +} diff -ruw linux-4.4.115/drivers/usb/core/usb.c linux-4.4.115-fbx/drivers/usb/core/usb.c --- linux-4.4.115/drivers/usb/core/usb.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/usb/core/usb.c 2019-10-29 09:26:24.973216194 +0100 @@ -669,6 +669,53 @@ } EXPORT_SYMBOL_GPL(usb_get_current_frame_number); +int usb_sec_event_ring_setup(struct usb_device *dev, + unsigned intr_num) +{ + if (dev->state == USB_STATE_NOTATTACHED) + return 0; + + return usb_hcd_sec_event_ring_setup(dev, intr_num); +} +EXPORT_SYMBOL(usb_sec_event_ring_setup); + +int usb_sec_event_ring_cleanup(struct usb_device *dev, + unsigned intr_num) +{ + return usb_hcd_sec_event_ring_cleanup(dev, intr_num); +} +EXPORT_SYMBOL(usb_sec_event_ring_cleanup); + +dma_addr_t +usb_get_sec_event_ring_dma_addr(struct usb_device *dev, + unsigned intr_num) +{ + if (dev->state == USB_STATE_NOTATTACHED) + return 0; + + return usb_hcd_get_sec_event_ring_dma_addr(dev, intr_num); +} +EXPORT_SYMBOL(usb_get_sec_event_ring_dma_addr); + +dma_addr_t usb_get_xfer_ring_dma_addr(struct usb_device *dev, + struct usb_host_endpoint *ep) +{ + if (dev->state == USB_STATE_NOTATTACHED) + return 0; + + return usb_hcd_get_xfer_ring_dma_addr(dev, ep); +} +EXPORT_SYMBOL(usb_get_xfer_ring_dma_addr); + +int usb_get_controller_id(struct usb_device *dev) +{ + if (dev->state == USB_STATE_NOTATTACHED) + return -EINVAL; + + return usb_hcd_get_controller_id(dev); +} +EXPORT_SYMBOL(usb_get_controller_id); + /*-------------------------------------------------------------------*/ /* * __usb_get_extra_descriptor() finds a descriptor of specific type in the diff -ruw linux-4.4.115/drivers/usb/core/usb.h linux-4.4.115-fbx/drivers/usb/core/usb.h --- linux-4.4.115/drivers/usb/core/usb.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/usb/core/usb.h 2019-10-29 09:26:24.973216194 +0100 @@ -175,6 +175,7 @@ extern void usb_notify_remove_device(struct usb_device *udev); extern void usb_notify_add_bus(struct usb_bus *ubus); extern void usb_notify_remove_bus(struct usb_bus *ubus); +extern void usb_atomic_notify_dead_bus(struct usb_bus *ubus); extern void usb_hub_adjust_deviceremovable(struct usb_device *hdev, struct usb_hub_descriptor *desc); diff -ruw linux-4.4.115/drivers/usb/dwc3/core.c linux-4.4.115-fbx/drivers/usb/dwc3/core.c --- linux-4.4.115/drivers/usb/dwc3/core.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/usb/dwc3/core.c 2019-10-29 09:26:24.981216272 +0100 @@ -35,6 +35,7 @@ #include #include #include +#include #include #include @@ -50,6 +51,20 @@ /* -------------------------------------------------------------------------- */ +void dwc3_usb3_phy_suspend(struct dwc3 *dwc, int suspend) +{ + u32 reg; + + reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0)); + + if (suspend) + reg |= DWC3_GUSB3PIPECTL_SUSPHY; + else + reg &= ~DWC3_GUSB3PIPECTL_SUSPHY; + + dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg); +} + void dwc3_set_mode(struct dwc3 *dwc, u32 mode) { u32 reg; @@ -57,35 +72,74 @@ reg = dwc3_readl(dwc->regs, DWC3_GCTL); reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG)); reg |= DWC3_GCTL_PRTCAPDIR(mode); + /* + * Set this bit so that device attempts three more times at SS, even + * if it failed previously to operate in SS mode. + */ + reg |= DWC3_GCTL_U2RSTECN; + reg &= ~(DWC3_GCTL_SOFITPSYNC); + reg &= ~(DWC3_GCTL_PWRDNSCALEMASK); + reg |= DWC3_GCTL_PWRDNSCALE(2); + reg |= DWC3_GCTL_U2EXIT_LFPS; dwc3_writel(dwc->regs, DWC3_GCTL, reg); + + if (mode == DWC3_GCTL_PRTCAP_OTG || mode == DWC3_GCTL_PRTCAP_HOST) { + /* + * Allow ITP generated off of ref clk based counter instead + * of UTMI/ULPI clk based counter, when superspeed only is + * active so that UTMI/ULPI PHY can be suspened. + * + * Starting with revision 2.50A, GFLADJ_REFCLK_LPM_SEL is used + * instead. + */ + if (dwc->revision < DWC3_REVISION_250A) { + reg = dwc3_readl(dwc->regs, DWC3_GCTL); + reg |= DWC3_GCTL_SOFITPSYNC; + dwc3_writel(dwc->regs, DWC3_GCTL, reg); + } else { + reg = dwc3_readl(dwc->regs, DWC3_GFLADJ); + reg |= DWC3_GFLADJ_REFCLK_LPM_SEL; + dwc3_writel(dwc->regs, DWC3_GFLADJ, reg); + } + } } /** - * dwc3_core_soft_reset - Issues core soft reset and PHY reset + * Peforms initialization of HS and SS PHYs. + * If used as a part of POR or init sequence it is recommended + * that we should perform hard reset of the PHYs prior to invoking + * this function. * @dwc: pointer to our context structure */ -static int dwc3_core_soft_reset(struct dwc3 *dwc) +static int dwc3_init_usb_phys(struct dwc3 *dwc) { - u32 reg; int ret; - /* Before Resetting PHY, put Core in Reset */ - reg = dwc3_readl(dwc->regs, DWC3_GCTL); - reg |= DWC3_GCTL_CORESOFTRESET; - dwc3_writel(dwc->regs, DWC3_GCTL, reg); + /* Bring up PHYs */ + ret = usb_phy_init(dwc->usb2_phy); + if (ret) { + pr_err("%s: usb_phy_init(dwc->usb2_phy) returned %d\n", + __func__, ret); + return ret; + } - /* Assert USB3 PHY reset */ - reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0)); - reg |= DWC3_GUSB3PIPECTL_PHYSOFTRST; - dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg); + if (dwc->maximum_speed == USB_SPEED_HIGH) + goto generic_phy_init; - /* Assert USB2 PHY reset */ - reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); - reg |= DWC3_GUSB2PHYCFG_PHYSOFTRST; - dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); + ret = usb_phy_init(dwc->usb3_phy); + if (ret == -EBUSY) { + /* + * Setting Max speed as high when USB3 PHY initialiation + * is failing and USB superspeed can't be supported. + */ + dwc->maximum_speed = USB_SPEED_HIGH; + } else if (ret) { + pr_err("%s: usb_phy_init(dwc->usb3_phy) returned %d\n", + __func__, ret); + return ret; + } - usb_phy_init(dwc->usb2_phy); - usb_phy_init(dwc->usb3_phy); +generic_phy_init: ret = phy_init(dwc->usb2_generic_phy); if (ret < 0) return ret; @@ -95,24 +149,45 @@ phy_exit(dwc->usb2_generic_phy); return ret; } - mdelay(100); - /* Clear USB3 PHY reset */ + return 0; +} + +/** + * dwc3_core_reset - Issues core soft reset and PHY reset + * @dwc: pointer to our context structure + */ +static int dwc3_core_reset(struct dwc3 *dwc) +{ + int ret; + u32 reg; + + /* Reset PHYs */ + usb_phy_reset(dwc->usb2_phy); + + if (dwc->maximum_speed == USB_SPEED_SUPER) + usb_phy_reset(dwc->usb3_phy); + + /* Initialize PHYs */ + ret = dwc3_init_usb_phys(dwc); + if (ret) { + pr_err("%s: dwc3_init_phys returned %d\n", + __func__, ret); + return ret; + } + reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0)); - reg &= ~DWC3_GUSB3PIPECTL_PHYSOFTRST; - dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg); + reg &= ~DWC3_GUSB3PIPECTL_DELAYP1TRANS; - /* Clear USB2 PHY reset */ - reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); - reg &= ~DWC3_GUSB2PHYCFG_PHYSOFTRST; - dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); + /* core exits U1/U2/U3 only in PHY power state P1/P2/P3 respectively */ + if (dwc->revision <= DWC3_REVISION_310A) + reg |= DWC3_GUSB3PIPECTL_UX_EXIT_IN_PX; - mdelay(100); + dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg); - /* After PHYs are stable we can take Core out of reset state */ - reg = dwc3_readl(dwc->regs, DWC3_GCTL); - reg &= ~DWC3_GCTL_CORESOFTRESET; - dwc3_writel(dwc->regs, DWC3_GCTL, reg); + dwc3_notify_event(dwc, DWC3_CONTROLLER_RESET_EVENT, 0); + + dwc3_notify_event(dwc, DWC3_CONTROLLER_POST_RESET_EVENT, 0); return 0; } @@ -190,7 +265,7 @@ * otherwise ERR_PTR(errno). */ static struct dwc3_event_buffer *dwc3_alloc_one_event_buffer(struct dwc3 *dwc, - unsigned length) + unsigned length, enum event_buf_type type) { struct dwc3_event_buffer *evt; @@ -200,6 +275,7 @@ evt->dwc = dwc; evt->length = length; + evt->type = type; evt->buf = dma_alloc_coherent(dwc->dev, length, &evt->dma, GFP_KERNEL); if (!evt->buf) @@ -234,26 +310,40 @@ */ static int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned length) { - int num; int i; + int j = 0; - num = DWC3_NUM_INT(dwc->hwparams.hwparams1); - dwc->num_event_buffers = num; + dwc->num_event_buffers = dwc->num_normal_event_buffers + + dwc->num_gsi_event_buffers; - dwc->ev_buffs = devm_kzalloc(dwc->dev, sizeof(*dwc->ev_buffs) * num, + dwc->ev_buffs = devm_kzalloc(dwc->dev, + sizeof(*dwc->ev_buffs) * dwc->num_event_buffers, GFP_KERNEL); if (!dwc->ev_buffs) return -ENOMEM; - for (i = 0; i < num; i++) { + for (i = 0; i < dwc->num_normal_event_buffers; i++) { struct dwc3_event_buffer *evt; - evt = dwc3_alloc_one_event_buffer(dwc, length); + evt = dwc3_alloc_one_event_buffer(dwc, length, + EVT_BUF_TYPE_NORMAL); if (IS_ERR(evt)) { dev_err(dwc->dev, "can't allocate event buffer\n"); return PTR_ERR(evt); } - dwc->ev_buffs[i] = evt; + dwc->ev_buffs[j++] = evt; + } + + for (i = 0; i < dwc->num_gsi_event_buffers; i++) { + struct dwc3_event_buffer *evt; + + evt = dwc3_alloc_one_event_buffer(dwc, length, + EVT_BUF_TYPE_GSI); + if (IS_ERR(evt)) { + dev_err(dwc->dev, "can't allocate event buffer\n"); + return PTR_ERR(evt); + } + dwc->ev_buffs[j++] = evt; } return 0; @@ -265,25 +355,40 @@ * * Returns 0 on success otherwise negative errno. */ -static int dwc3_event_buffers_setup(struct dwc3 *dwc) +int dwc3_event_buffers_setup(struct dwc3 *dwc) { struct dwc3_event_buffer *evt; int n; for (n = 0; n < dwc->num_event_buffers; n++) { evt = dwc->ev_buffs[n]; - dev_dbg(dwc->dev, "Event buf %p dma %08llx length %d\n", + dev_dbg(dwc->dev, "Event buf %pK dma %08llx length %d\n", evt->buf, (unsigned long long) evt->dma, evt->length); + memset(evt->buf, 0, evt->length); + evt->lpos = 0; dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(n), lower_32_bits(evt->dma)); + + if (evt->type == EVT_BUF_TYPE_NORMAL) { dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n), upper_32_bits(evt->dma)); dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n), DWC3_GEVNTSIZ_SIZE(evt->length)); + } else { + dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n), + DWC3_GEVNTADRHI_EVNTADRHI_GSI_EN( + DWC3_GEVENT_TYPE_GSI) | + DWC3_GEVNTADRHI_EVNTADRHI_GSI_IDX(n)); + + dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n), + DWC3_GEVNTCOUNT_EVNTINTRPTMASK | + ((evt->length) & 0xffff)); + } + dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(n), 0); } @@ -529,7 +634,7 @@ * * Returns 0 on success otherwise negative errno. */ -static int dwc3_core_init(struct dwc3 *dwc) +int dwc3_core_init(struct dwc3 *dwc) { u32 hwparams4 = dwc->hwparams.hwparams4; u32 reg; @@ -559,16 +664,28 @@ /* Handle USB2.0-only core configuration */ if (DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3) == DWC3_GHWPARAMS3_SSPHY_IFC_DIS) { - if (dwc->maximum_speed == USB_SPEED_SUPER) - dwc->maximum_speed = USB_SPEED_HIGH; + if (dwc->max_hw_supp_speed == USB_SPEED_SUPER) { + dwc->max_hw_supp_speed = USB_SPEED_HIGH; + dwc->maximum_speed = dwc->max_hw_supp_speed; + } } - /* issue device SoftReset too */ - ret = dwc3_soft_reset(dwc); + /* + * Workaround for STAR 9000961433 which affects only version + * 3.00a of the DWC_usb3 core. This prevents the controller + * interrupt from being masked while handling events. IMOD + * allows us to work around this issue. Enable it for the + * affected version. + */ + if (!dwc->imod_interval && (dwc->revision == DWC3_REVISION_300A)) + dwc->imod_interval = 1; + + ret = dwc3_core_reset(dwc); if (ret) goto err0; - ret = dwc3_core_soft_reset(dwc); + /* issue device SoftReset too */ + ret = dwc3_soft_reset(dwc); if (ret) goto err0; @@ -639,6 +756,15 @@ dwc3_core_num_eps(dwc); + /* + * Disable clock gating to work around a known HW bug that causes the + * internal RAM clock to get stuck when entering low power modes. + */ + if (dwc->disable_clk_gating) { + dev_dbg(dwc->dev, "Disabling controller clock gating.\n"); + reg |= DWC3_GCTL_DSBLCLKGTNG; + } + dwc3_writel(dwc->regs, DWC3_GCTL, reg); ret = dwc3_alloc_scratch_buffers(dwc); @@ -649,6 +775,17 @@ if (ret) goto err2; + /* + * clear Elastic buffer mode in GUSBPIPE_CTRL(0) register, otherwise + * it results in high link errors and could cause SS mode transfer + * failure. + */ + if (!dwc->nominal_elastic_buffer) { + reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0)); + reg &= ~DWC3_GUSB3PIPECTL_ELASTIC_BUF_MODE; + dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg); + } + return 0; err2: @@ -743,38 +880,16 @@ static int dwc3_core_init_mode(struct dwc3 *dwc) { struct device *dev = dwc->dev; - int ret; switch (dwc->dr_mode) { case USB_DR_MODE_PERIPHERAL: dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_DEVICE); - ret = dwc3_gadget_init(dwc); - if (ret) { - dev_err(dev, "failed to initialize gadget\n"); - return ret; - } break; case USB_DR_MODE_HOST: dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_HOST); - ret = dwc3_host_init(dwc); - if (ret) { - dev_err(dev, "failed to initialize host\n"); - return ret; - } break; case USB_DR_MODE_OTG: dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_OTG); - ret = dwc3_host_init(dwc); - if (ret) { - dev_err(dev, "failed to initialize host\n"); - return ret; - } - - ret = dwc3_gadget_init(dwc); - if (ret) { - dev_err(dev, "failed to initialize gadget\n"); - return ret; - } break; default: dev_err(dev, "Unsupported mode of operation %d\n", dwc->dr_mode); @@ -803,8 +918,310 @@ } } +/* XHCI reset, resets other CORE registers as well, re-init those */ +void dwc3_post_host_reset_core_init(struct dwc3 *dwc) +{ + dwc3_core_init(dwc); + dwc3_gadget_restart(dwc); +} + +static void (*notify_event)(struct dwc3 *, unsigned, unsigned); +void dwc3_set_notifier(void (*notify)(struct dwc3 *, unsigned, unsigned)) +{ + notify_event = notify; +} +EXPORT_SYMBOL(dwc3_set_notifier); + +int dwc3_notify_event(struct dwc3 *dwc, unsigned event, unsigned value) +{ + int ret = 0; + + if (dwc->notify_event) + dwc->notify_event(dwc, event, value); + else + ret = -ENODEV; + + return ret; +} +EXPORT_SYMBOL(dwc3_notify_event); + +int dwc3_core_pre_init(struct dwc3 *dwc) +{ + int ret; + + dwc3_cache_hwparams(dwc); + + ret = dwc3_phy_setup(dwc); + if (ret) + goto err0; + + if (!dwc->ev_buffs) { + ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE); + if (ret) { + dev_err(dwc->dev, "failed to allocate event buffers\n"); + ret = -ENOMEM; + goto err1; + } + } + + ret = dwc3_core_init(dwc); + if (ret) { + dev_err(dwc->dev, "failed to initialize core\n"); + goto err2; + } + + ret = phy_power_on(dwc->usb2_generic_phy); + if (ret < 0) + goto err3; + + ret = phy_power_on(dwc->usb3_generic_phy); + if (ret < 0) + goto err4; + + ret = dwc3_event_buffers_setup(dwc); + if (ret) { + dev_err(dwc->dev, "failed to setup event buffers\n"); + goto err5; + } + + ret = dwc3_core_init_mode(dwc); + if (ret) { + dev_err(dwc->dev, "failed to set mode with dwc3 core\n"); + goto err6; + } + + return ret; + +err6: + dwc3_event_buffers_cleanup(dwc); +err5: + phy_power_off(dwc->usb3_generic_phy); +err4: + phy_power_off(dwc->usb2_generic_phy); +err3: + dwc3_core_exit(dwc); +err2: + dwc3_free_event_buffers(dwc); +err1: + dwc3_ulpi_exit(dwc); +err0: + return ret; +} + +static void dwc3_process_event_entry(struct dwc3 *dwc, + const union dwc3_event *event) +{ + trace_dwc3_event(event->raw); + + /* skip event processing in absence of vbus */ + if (!dwc->vbus_active) { + dbg_print_reg("SKIP EVT", event->raw); + return; + } + + /* If run/stop is cleared don't process any more events */ + if (!dwc->pullups_connected) { + dbg_print_reg("SKIP_EVT_PULLUP", event->raw); + return; + } + + /* Endpoint IRQ, handle it and return early */ + if (event->type.is_devspec == 0) { + /* depevt */ + return dwc3_endpoint_interrupt(dwc, &event->depevt); + } + + switch (event->type.type) { + case DWC3_EVENT_TYPE_DEV: + dwc3_gadget_interrupt(dwc, &event->devt); + break; + /* REVISIT what to do with Carkit and I2C events ? */ + default: + dev_err(dwc->dev, "UNKNOWN IRQ type %d\n", event->raw); + } +} + +static irqreturn_t dwc3_process_event_buf(struct dwc3 *dwc, u32 buf) +{ + struct dwc3_event_buffer *evt; + irqreturn_t ret = IRQ_NONE; + int left; + u32 reg; + + evt = dwc->ev_buffs[buf]; + left = evt->count; + + if (!(evt->flags & DWC3_EVENT_PENDING)) + return IRQ_NONE; + + while (left > 0) { + union dwc3_event event; + + event.raw = *(u32 *) (evt->buf + evt->lpos); + + dwc3_process_event_entry(dwc, &event); + + if (dwc->err_evt_seen) { + /* + * if erratic error, skip remaining events + * while controller undergoes reset + */ + evt->lpos = (evt->lpos + left) % + DWC3_EVENT_BUFFERS_SIZE; + dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(buf), left); + if (dwc3_notify_event(dwc, + DWC3_CONTROLLER_ERROR_EVENT, 0)) + dwc->err_evt_seen = 0; + break; + } + + /* + * FIXME we wrap around correctly to the next entry as + * almost all entries are 4 bytes in size. There is one + * entry which has 12 bytes which is a regular entry + * followed by 8 bytes data. ATM I don't know how + * things are organized if we get next to the a + * boundary so I worry about that once we try to handle + * that. + */ + evt->lpos = (evt->lpos + 4) % DWC3_EVENT_BUFFERS_SIZE; + left -= 4; + } + + dwc->bh_handled_evt_cnt[dwc->bh_dbg_index] += (evt->count / 4); + + evt->count = 0; + evt->flags &= ~DWC3_EVENT_PENDING; + ret = IRQ_HANDLED; + + /* Unmask interrupt */ + reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(buf)); + reg &= ~DWC3_GEVNTSIZ_INTMASK; + dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(buf), reg); + + if (dwc->imod_interval) + dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(buf), + DWC3_GEVNTCOUNT_EHB); + + return ret; +} + +static irqreturn_t dwc3_thread_interrupt(int irq, void *_dwc) +{ + struct dwc3 *dwc = _dwc; + unsigned long flags; + irqreturn_t ret = IRQ_NONE; + int i; + unsigned temp_time; + ktime_t start_time; + + start_time = ktime_get(); + + spin_lock_irqsave(&dwc->lock, flags); + dwc->bh_handled_evt_cnt[dwc->bh_dbg_index] = 0; + + for (i = 0; i < dwc->num_normal_event_buffers; i++) + ret |= dwc3_process_event_buf(dwc, i); + + spin_unlock_irqrestore(&dwc->lock, flags); + + temp_time = ktime_to_us(ktime_sub(ktime_get(), start_time)); + dwc->bh_completion_time[dwc->bh_dbg_index] = temp_time; + dwc->bh_dbg_index = (dwc->bh_dbg_index + 1) % 10; + + return ret; +} + +void dwc3_bh_work(struct work_struct *w) +{ + struct dwc3 *dwc = container_of(w, struct dwc3, bh_work); + + pm_runtime_get_sync(dwc->dev); + dwc3_thread_interrupt(dwc->irq, dwc); + pm_runtime_put(dwc->dev); +} + +static irqreturn_t dwc3_check_event_buf(struct dwc3 *dwc, u32 buf) +{ + struct dwc3_event_buffer *evt; + u32 count; + u32 reg; + + evt = dwc->ev_buffs[buf]; + + count = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(buf)); + count &= DWC3_GEVNTCOUNT_MASK; + if (!count) + return IRQ_NONE; + + if (count > evt->length) { + dbg_event(0xFF, "HUGE_EVCNT", count); + evt->lpos = (evt->lpos + count) % DWC3_EVENT_BUFFERS_SIZE; + dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(buf), count); + return IRQ_HANDLED; + } + + evt->count = count; + evt->flags |= DWC3_EVENT_PENDING; + + /* Mask interrupt */ + reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(buf)); + reg |= DWC3_GEVNTSIZ_INTMASK; + dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(buf), reg); + + dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(buf), count); + + return IRQ_WAKE_THREAD; +} + +static irqreturn_t dwc3_interrupt(int irq, void *_dwc) +{ + struct dwc3 *dwc = _dwc; + int i; + irqreturn_t ret = IRQ_NONE; + unsigned temp_cnt = 0; + ktime_t start_time; + + start_time = ktime_get(); + dwc->irq_cnt++; + + /* controller reset is still pending */ + if (dwc->err_evt_seen) + return IRQ_HANDLED; + + for (i = 0; i < dwc->num_normal_event_buffers; i++) { + irqreturn_t status; + + status = dwc3_check_event_buf(dwc, i); + if (status == IRQ_WAKE_THREAD) + ret = status; + + temp_cnt += dwc->ev_buffs[i]->count; + } + + dwc->irq_start_time[dwc->irq_dbg_index] = start_time; + dwc->irq_completion_time[dwc->irq_dbg_index] = + ktime_us_delta(ktime_get(), start_time); + dwc->irq_event_count[dwc->irq_dbg_index] = temp_cnt / 4; + dwc->irq_dbg_index = (dwc->irq_dbg_index + 1) % MAX_INTR_STATS; + + if (ret == IRQ_WAKE_THREAD) + queue_work(dwc->dwc_wq, &dwc->bh_work); + + return IRQ_HANDLED; +} + #define DWC3_ALIGN_MASK (16 - 1) +/* check whether the core supports IMOD */ +bool dwc3_has_imod(struct dwc3 *dwc) +{ + return ((dwc3_is_usb3(dwc) && + dwc->revision >= DWC3_REVISION_300A) || + (dwc3_is_usb31(dwc) && + dwc->revision >= DWC3_USB31_REVISION_120A)); +} + static int dwc3_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; @@ -815,7 +1232,8 @@ u8 tx_de_emphasis; u8 hird_threshold; u32 fladj = 0; - + u32 num_evt_buffs; + int irq; int ret; void __iomem *regs; @@ -829,6 +1247,7 @@ dwc->mem = mem; dwc->dev = dev; + dwc->notify_event = notify_event; res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); if (!res) { dev_err(dev, "missing IRQ\n"); @@ -839,12 +1258,27 @@ dwc->xhci_resources[1].flags = res->flags; dwc->xhci_resources[1].name = res->name; + irq = platform_get_irq(to_platform_device(dwc->dev), 0); + + /* will be enabled in dwc3_msm_resume() */ + irq_set_status_flags(irq, IRQ_NOAUTOEN); + ret = devm_request_irq(dev, irq, dwc3_interrupt, IRQF_SHARED, "dwc3", + dwc); + if (ret) { + dev_err(dwc->dev, "failed to request irq #%d --> %d\n", + irq, ret); + return -ENODEV; + } + + dwc->irq = irq; + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); if (!res) { dev_err(dev, "missing memory resource\n"); return -ENODEV; } + dwc->reg_phys = res->start; dwc->xhci_resources[0].start = res->start; dwc->xhci_resources[0].end = dwc->xhci_resources[0].start + DWC3_XHCI_REGS_END; @@ -867,7 +1301,7 @@ dwc->regs_size = resource_size(res); /* default to highest possible threshold */ - lpm_nyet_threshold = 0xff; + lpm_nyet_threshold = 0xf; /* default to -3.5dB de-emphasis */ tx_de_emphasis = 1; @@ -879,6 +1313,7 @@ hird_threshold = 12; dwc->maximum_speed = usb_get_maximum_speed(dev); + dwc->max_hw_supp_speed = dwc->maximum_speed; dwc->dr_mode = usb_get_dr_mode(dev); dwc->has_lpm_erratum = device_property_read_bool(dev, @@ -927,8 +1362,32 @@ device_property_read_u32(dev, "snps,quirk-frame-length-adjustment", &fladj); + dwc->nominal_elastic_buffer = device_property_read_bool(dev, + "snps,nominal-elastic-buffer"); + dwc->usb3_u1u2_disable = device_property_read_bool(dev, + "snps,usb3-u1u2-disable"); + dwc->disable_clk_gating = device_property_read_bool(dev, + "snps,disable-clk-gating"); + dwc->enable_bus_suspend = device_property_read_bool(dev, + "snps,bus-suspend-enable"); + + dwc->num_normal_event_buffers = 1; + ret = device_property_read_u32(dev, + "snps,num-normal-evt-buffs", &num_evt_buffs); + if (!ret) + dwc->num_normal_event_buffers = num_evt_buffs; + + ret = device_property_read_u32(dev, + "snps,num-gsi-evt-buffs", &dwc->num_gsi_event_buffers); + + if (dwc->enable_bus_suspend) { + pm_runtime_set_autosuspend_delay(dev, 500); + pm_runtime_use_autosuspend(dev); + } + if (pdata) { dwc->maximum_speed = pdata->maximum_speed; + dwc->max_hw_supp_speed = dwc->maximum_speed; dwc->has_lpm_erratum = pdata->has_lpm_erratum; if (pdata->lpm_nyet_threshold) lpm_nyet_threshold = pdata->lpm_nyet_threshold; @@ -962,7 +1421,7 @@ /* default to superspeed if no maximum_speed passed */ if (dwc->maximum_speed == USB_SPEED_UNKNOWN) - dwc->maximum_speed = USB_SPEED_SUPER; + dwc->max_hw_supp_speed = dwc->maximum_speed = USB_SPEED_SUPER; dwc->lpm_nyet_threshold = lpm_nyet_threshold; dwc->tx_de_emphasis = tx_de_emphasis; @@ -970,104 +1429,84 @@ dwc->hird_threshold = hird_threshold | (dwc->is_utmi_l1_suspend << 4); + init_waitqueue_head(&dwc->wait_linkstate); platform_set_drvdata(pdev, dwc); - dwc3_cache_hwparams(dwc); - - ret = dwc3_phy_setup(dwc); - if (ret) - goto err0; - ret = dwc3_core_get_phy(dwc); if (ret) goto err0; spin_lock_init(&dwc->lock); - if (!dev->dma_mask) { dev->dma_mask = dev->parent->dma_mask; dev->dma_parms = dev->parent->dma_parms; dma_set_coherent_mask(dev, dev->parent->coherent_dma_mask); + + dwc->dwc_wq = alloc_ordered_workqueue("dwc_wq", WQ_HIGHPRI); + if (!dwc->dwc_wq) { + pr_err("%s: Unable to create workqueue dwc_wq\n", __func__); + return -ENOMEM; } + INIT_WORK(&dwc->bh_work, dwc3_bh_work); + + pm_runtime_no_callbacks(dev); + pm_runtime_set_active(dev); pm_runtime_enable(dev); - pm_runtime_get_sync(dev); pm_runtime_forbid(dev); - ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE); - if (ret) { - dev_err(dwc->dev, "failed to allocate event buffers\n"); - ret = -ENOMEM; - goto err1; - } - if (IS_ENABLED(CONFIG_USB_DWC3_HOST)) dwc->dr_mode = USB_DR_MODE_HOST; else if (IS_ENABLED(CONFIG_USB_DWC3_GADGET)) dwc->dr_mode = USB_DR_MODE_PERIPHERAL; - if (dwc->dr_mode == USB_DR_MODE_UNKNOWN) + if (dwc->dr_mode == USB_DR_MODE_UNKNOWN) { dwc->dr_mode = USB_DR_MODE_OTG; - - ret = dwc3_core_init(dwc); - if (ret) { - dev_err(dev, "failed to initialize core\n"); - goto err1; + dwc->is_drd = true; } /* Adjust Frame Length */ dwc3_frame_length_adjustment(dwc, fladj); - usb_phy_set_suspend(dwc->usb2_phy, 0); - usb_phy_set_suspend(dwc->usb3_phy, 0); - ret = phy_power_on(dwc->usb2_generic_phy); - if (ret < 0) - goto err2; - - ret = phy_power_on(dwc->usb3_generic_phy); - if (ret < 0) - goto err3; + /* Hardcode number of eps */ + dwc->num_in_eps = 16; + dwc->num_out_eps = 16; - ret = dwc3_event_buffers_setup(dwc); + if (dwc->dr_mode == USB_DR_MODE_OTG || + dwc->dr_mode == USB_DR_MODE_PERIPHERAL) { + ret = dwc3_gadget_init(dwc); if (ret) { - dev_err(dwc->dev, "failed to setup event buffers\n"); - goto err4; + dev_err(dev, "failed to initialize gadget\n"); + goto err0; + } } - ret = dwc3_core_init_mode(dwc); - if (ret) - goto err5; + if (dwc->dr_mode == USB_DR_MODE_OTG || + dwc->dr_mode == USB_DR_MODE_HOST) { + ret = dwc3_host_init(dwc); + if (ret) { + dev_err(dev, "failed to initialize host\n"); + goto err_gadget; + } + } ret = dwc3_debugfs_init(dwc); if (ret) { dev_err(dev, "failed to initialize debugfs\n"); - goto err6; + goto err_host; } pm_runtime_allow(dev); return 0; -err6: - dwc3_core_exit_mode(dwc); - -err5: - dwc3_event_buffers_cleanup(dwc); - -err4: - phy_power_off(dwc->usb3_generic_phy); - -err3: - phy_power_off(dwc->usb2_generic_phy); - -err2: - usb_phy_set_suspend(dwc->usb2_phy, 1); - usb_phy_set_suspend(dwc->usb3_phy, 1); - dwc3_core_exit(dwc); - -err1: - dwc3_free_event_buffers(dwc); - dwc3_ulpi_exit(dwc); - +err_host: + if (dwc->dr_mode == USB_DR_MODE_OTG || + dwc->dr_mode == USB_DR_MODE_HOST) + dwc3_host_exit(dwc); +err_gadget: + if (dwc->dr_mode == USB_DR_MODE_OTG || + dwc->dr_mode == USB_DR_MODE_PERIPHERAL) + dwc3_gadget_exit(dwc); err0: /* * restore res->start back to its original value so that, in case the @@ -1075,6 +1514,7 @@ * memory region the next time probe is called. */ res->start -= DWC3_GLOBALS_REGS_START; + destroy_workqueue(dwc->dwc_wq); return ret; } @@ -1096,14 +1536,14 @@ dwc3_event_buffers_cleanup(dwc); dwc3_free_event_buffers(dwc); - usb_phy_set_suspend(dwc->usb2_phy, 1); - usb_phy_set_suspend(dwc->usb3_phy, 1); phy_power_off(dwc->usb2_generic_phy); phy_power_off(dwc->usb3_generic_phy); dwc3_core_exit(dwc); dwc3_ulpi_exit(dwc); + destroy_workqueue(dwc->dwc_wq); + pm_runtime_put_sync(&pdev->dev); pm_runtime_disable(&pdev->dev); @@ -1116,6 +1556,10 @@ struct dwc3 *dwc = dev_get_drvdata(dev); unsigned long flags; + /* Check if platform glue driver handling PM, if not then handle here */ + if (!dwc3_notify_event(dwc, DWC3_CORE_PM_SUSPEND_EVENT, 0)) + return 0; + spin_lock_irqsave(&dwc->lock, flags); switch (dwc->dr_mode) { @@ -1148,6 +1592,10 @@ unsigned long flags; int ret; + /* Check if platform glue driver handling PM, if not then handle here */ + if (!dwc3_notify_event(dwc, DWC3_CORE_PM_RESUME_EVENT, 0)) + return 0; + pinctrl_pm_select_default_state(dev); usb_phy_init(dwc->usb3_phy); diff -ruw linux-4.4.115/drivers/usb/dwc3/core.h linux-4.4.115-fbx/drivers/usb/dwc3/core.h --- linux-4.4.115/drivers/usb/dwc3/core.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/usb/dwc3/core.h 2019-10-29 09:26:24.981216272 +0100 @@ -26,6 +26,8 @@ #include #include #include +#include +#include #include #include @@ -37,6 +39,7 @@ #define DWC3_MSG_MAX 500 /* Global constants */ +#define DWC3_ZLP_BUF_SIZE 1024 /* size of a superspeed bulk */ #define DWC3_EP0_BOUNCE_SIZE 512 #define DWC3_ENDPOINTS_NUM 32 #define DWC3_XHCI_RESOURCES_NUM 2 @@ -56,12 +59,15 @@ #define DWC3_DEVICE_EVENT_WAKEUP 4 #define DWC3_DEVICE_EVENT_HIBER_REQ 5 #define DWC3_DEVICE_EVENT_EOPF 6 +/* For version 2.30a and above */ +#define DWC3_DEVICE_EVENT_SUSPEND 6 #define DWC3_DEVICE_EVENT_SOF 7 #define DWC3_DEVICE_EVENT_ERRATIC_ERROR 9 #define DWC3_DEVICE_EVENT_CMD_CMPL 10 #define DWC3_DEVICE_EVENT_OVERFLOW 11 #define DWC3_GEVNTCOUNT_MASK 0xfffc +#define DWC3_GEVNTCOUNT_EHB (1 << 31) #define DWC3_GSNPSID_MASK 0xffff0000 #define DWC3_GSNPSREV_MASK 0xffff @@ -124,6 +130,11 @@ #define DWC3_GEVNTSIZ(n) (0xc408 + (n * 0x10)) #define DWC3_GEVNTCOUNT(n) (0xc40c + (n * 0x10)) +#define DWC3_GEVNTCOUNT_EVNTINTRPTMASK (1 << 31) +#define DWC3_GEVNTADRHI_EVNTADRHI_GSI_EN(n) (n << 22) +#define DWC3_GEVNTADRHI_EVNTADRHI_GSI_IDX(n) (n << 16) +#define DWC3_GEVENT_TYPE_GSI 0x3 + #define DWC3_GHWPARAMS8 0xc600 #define DWC3_GFLADJ 0xc630 @@ -140,6 +151,8 @@ #define DWC3_DEPCMDPAR0(n) (0xc808 + (n * 0x10)) #define DWC3_DEPCMD(n) (0xc80c + (n * 0x10)) +#define DWC3_DEV_IMOD(n) (0xca00 + (n * 0x4)) + /* OTG Registers */ #define DWC3_OCFG 0xcc00 #define DWC3_OCTL 0xcc04 @@ -149,9 +162,16 @@ /* Bit fields */ +/* Global SoC Bus Configuration Register 1 */ +#define DWC3_GSBUSCFG1_PIPETRANSLIMIT_MASK (0x0f << 8) +#define DWC3_GSBUSCFG1_PIPETRANSLIMIT(n) ((n) << 8) + /* Global Configuration Register */ #define DWC3_GCTL_PWRDNSCALE(n) ((n) << 19) +#define DWC3_GCTL_PWRDNSCALEMASK (0xFFF80000) #define DWC3_GCTL_U2RSTECN (1 << 16) +#define DWC3_GCTL_SOFITPSYNC (1 << 10) +#define DWC3_GCTL_U2EXIT_LFPS (1 << 2) #define DWC3_GCTL_RAMCLKSEL(x) (((x) & DWC3_GCTL_CLK_MASK) << 6) #define DWC3_GCTL_CLK_BUS (0) #define DWC3_GCTL_CLK_PIPE (1) @@ -173,8 +193,15 @@ #define DWC3_GCTL_GBLHIBERNATIONEN (1 << 1) #define DWC3_GCTL_DSBLCLKGTNG (1 << 0) +/* Global User Control Register */ +#define DWC3_GUCTL_REFCLKPER (0x3FF << 22) + +/* Global Debug LTSSM Register */ +#define DWC3_GDBGLTSSM_LINKSTATE_MASK (0xF << 22) + /* Global USB2 PHY Configuration Register */ #define DWC3_GUSB2PHYCFG_PHYSOFTRST (1 << 31) +#define DWC3_GUSB2PHYCFG_ENBLSLPM (1 << 8) #define DWC3_GUSB2PHYCFG_SUSPHY (1 << 6) #define DWC3_GUSB2PHYCFG_ULPI_UTMI (1 << 4) #define DWC3_GUSB2PHYCFG_ENBLSLPM (1 << 8) @@ -190,6 +217,7 @@ /* Global USB3 PIPE Control Register */ #define DWC3_GUSB3PIPECTL_PHYSOFTRST (1 << 31) #define DWC3_GUSB3PIPECTL_U2SSINP3OK (1 << 29) +#define DWC3_GUSB3PIPECTL_UX_EXIT_IN_PX (1 << 27) #define DWC3_GUSB3PIPECTL_REQP1P2P3 (1 << 24) #define DWC3_GUSB3PIPECTL_DEP1P2P3(n) ((n) << 19) #define DWC3_GUSB3PIPECTL_DEP1P2P3_MASK DWC3_GUSB3PIPECTL_DEP1P2P3(7) @@ -200,6 +228,8 @@ #define DWC3_GUSB3PIPECTL_RX_DETOPOLL (1 << 8) #define DWC3_GUSB3PIPECTL_TX_DEEPH_MASK DWC3_GUSB3PIPECTL_TX_DEEPH(3) #define DWC3_GUSB3PIPECTL_TX_DEEPH(n) ((n) << 1) +#define DWC3_GUSB3PIPECTL_DELAYP1TRANS (1 << 18) +#define DWC3_GUSB3PIPECTL_ELASTIC_BUF_MODE (1 << 0) /* Global TX Fifo Size Register */ #define DWC3_GTXFIFOSIZ_TXFDEF(n) ((n) & 0xffff) @@ -241,6 +271,12 @@ #define DWC3_GFLADJ_30MHZ_SDBND_SEL (1 << 7) #define DWC3_GFLADJ_30MHZ_MASK 0x3f +/* Global Frame Length Adjustment Register */ +#define DWC3_GFLADJ_REFCLK_240MHZDECR_PLS1 (1 << 31) +#define DWC3_GFLADJ_REFCLK_240MHZ_DECR (0x7F << 24) +#define DWC3_GFLADJ_REFCLK_LPM_SEL (1 << 23) +#define DWC3_GFLADJ_REFCLK_FLADJ (0x3FFF << 8) + /* Device Configuration Register */ #define DWC3_DCFG_DEVADDR(addr) ((addr) << 3) #define DWC3_DCFG_DEVADDR_MASK DWC3_DCFG_DEVADDR(0x7f) @@ -306,6 +342,8 @@ #define DWC3_DEVTEN_ERRTICERREN (1 << 9) #define DWC3_DEVTEN_SOFEN (1 << 7) #define DWC3_DEVTEN_EOPFEN (1 << 6) +/* For version 2.30a and above*/ +#define DWC3_DEVTEN_SUSPEND (1 << 6) #define DWC3_DEVTEN_HIBERNATIONREQEVTEN (1 << 5) #define DWC3_DEVTEN_WKUPEVTEN (1 << 4) #define DWC3_DEVTEN_ULSTCNGEN (1 << 3) @@ -346,6 +384,7 @@ #define DWC3_DGCMD_SET_LMP 0x01 #define DWC3_DGCMD_SET_PERIODIC_PAR 0x02 #define DWC3_DGCMD_XMIT_FUNCTION 0x03 +#define DWC3_DGCMD_XMIT_DEV 0x07 /* These apply for core versions 1.94a and later */ #define DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO 0x04 @@ -398,10 +437,20 @@ #define DWC3_DEPCMD_TYPE_BULK 2 #define DWC3_DEPCMD_TYPE_INTR 3 +#define DWC3_DEV_IMOD_COUNT_SHIFT 16 +#define DWC3_DEV_IMOD_COUNT_MASK (0xffff << 16) +#define DWC3_DEV_IMOD_INTERVAL_SHIFT 0 +#define DWC3_DEV_IMOD_INTERVAL_MASK (0xffff << 0) + /* Structures */ struct dwc3_trb; +enum event_buf_type { + EVT_BUF_TYPE_NORMAL, + EVT_BUF_TYPE_GSI +}; + /** * struct dwc3_event_buffer - Software event buffer representation * @buf: _THE_ buffer @@ -415,6 +464,7 @@ struct dwc3_event_buffer { void *buf; unsigned length; + enum event_buf_type type; unsigned int lpos; unsigned int count; unsigned int flags; @@ -426,6 +476,36 @@ struct dwc3 *dwc; }; +struct dwc3_gadget_events { + unsigned int disconnect; + unsigned int reset; + unsigned int connect; + unsigned int wakeup; + unsigned int link_status_change; + unsigned int eopf; + unsigned int suspend; + unsigned int sof; + unsigned int erratic_error; + unsigned int overflow; + unsigned int vendor_dev_test_lmp; + unsigned int cmdcmplt; + unsigned int unknown_event; +}; + +struct dwc3_ep_events { + unsigned int xfercomplete; + unsigned int xfernotready; + unsigned int control_data; + unsigned int control_status; + unsigned int xferinprogress; + unsigned int rxtxfifoevent; + unsigned int streamevent; + unsigned int epcmdcomplete; + unsigned int cmdcmplt; + unsigned int unknown_event; + unsigned int total; +}; + #define DWC3_EP_FLAG_STALLED (1 << 0) #define DWC3_EP_FLAG_WEDGED (1 << 1) @@ -440,8 +520,10 @@ * @endpoint: usb endpoint * @request_list: list of requests for this endpoint * @req_queued: list of requests on this ep which have TRBs setup + * @trb_dma_pool: dma pool used to get aligned trb memory pool * @trb_pool: array of transaction buffers * @trb_pool_dma: dma address of @trb_pool + * @num_trbs: num of trbs in the trb dma pool * @free_slot: next slot which is going to be used * @busy_slot: first slot which is owned by HW * @desc: usb_endpoint_descriptor pointer @@ -451,18 +533,24 @@ * @number: endpoint number (1 - 15) * @type: set to bmAttributes & USB_ENDPOINT_XFERTYPE_MASK * @resource_index: Resource transfer index + * @current_uf: Current uf received through last event parameter * @interval: the interval on which the ISOC transfer is started * @name: a human readable name e.g. ep1out-bulk * @direction: true for TX, false for RX * @stream_capable: true when streams are enabled + * @dbg_ep_events: different events counter for endpoint + * @dbg_ep_events_diff: differential events counter for endpoint + * @dbg_ep_events_ts: timestamp for previous event counters */ struct dwc3_ep { struct usb_ep endpoint; struct list_head request_list; struct list_head req_queued; + struct dma_pool *trb_dma_pool; struct dwc3_trb *trb_pool; dma_addr_t trb_pool_dma; + u32 num_trbs; u32 free_slot; u32 busy_slot; const struct usb_ss_ep_comp_descriptor *comp_desc; @@ -483,12 +571,16 @@ u8 number; u8 type; u8 resource_index; + u16 current_uf; u32 interval; char name[20]; unsigned direction:1; unsigned stream_capable:1; + struct dwc3_ep_events dbg_ep_events; + struct dwc3_ep_events dbg_ep_events_diff; + struct timespec dbg_ep_events_ts; }; enum dwc3_phy { @@ -640,11 +732,24 @@ __le64 dma_adr[DWC3_MAX_HIBER_SCRATCHBUFS]; }; +#define DWC3_CONTROLLER_ERROR_EVENT 0 +#define DWC3_CONTROLLER_RESET_EVENT 1 +#define DWC3_CONTROLLER_POST_RESET_EVENT 2 +#define DWC3_CORE_PM_SUSPEND_EVENT 3 +#define DWC3_CORE_PM_RESUME_EVENT 4 +#define DWC3_CONTROLLER_CONNDONE_EVENT 5 +#define DWC3_CONTROLLER_NOTIFY_OTG_EVENT 6 +#define DWC3_CONTROLLER_SET_CURRENT_DRAW_EVENT 7 +#define DWC3_CONTROLLER_RESTART_USB_SESSION 8 +#define DWC3_CONTROLLER_NOTIFY_DISABLE_UPDXFER 9 + +#define MAX_INTR_STATS 10 /** * struct dwc3 - representation of our controller * @ctrl_req: usb control request which is used for ep0 * @ep0_trb: trb which is used for the ctrl_req * @ep0_bounce: bounce buffer for ep0 + * @zlp_buf: used when request->zero is set * @setup_buf: used while precessing STD USB requests * @ctrl_req_addr: dma address of ctrl_req * @ep0_trb: dma address of ep0_trb @@ -659,10 +764,12 @@ * @gadget_driver: pointer to the gadget driver * @regs: base address for our registers * @regs_size: address space size + * @reg_phys: physical base address of dwc3 core register address space * @nr_scratch: number of scratch buffers * @num_event_buffers: calculated number of event buffers * @u1u2: only used on revisions <1.83a for workaround - * @maximum_speed: maximum speed requested (mainly for testing purposes) + * @maximum_speed: maximum speed to operate as requested by sw + * @max_hw_supp_speed: maximum speed supported by hw design * @revision: revision register contents * @dr_mode: requested mode of operation * @usb2_phy: pointer to USB2 PHY @@ -727,11 +834,29 @@ * 1 - -3.5dB de-emphasis * 2 - No de-emphasis * 3 - Reserved + * @is_drd: device supports dual-role or not + * @err_evt_seen: previous event in queue was erratic error + * @usb3_u1u2_disable: if true, disable U1U2 low power modes in Superspeed mode. + * @in_lpm: indicates if controller is in low power mode (no clocks) + * @tx_fifo_size: Available RAM size for TX fifo allocation + * @irq: irq number + * @bh: tasklet which handles the interrupt + * @irq_cnt: total irq count + * @last_irq_cnt: last irq count + * @bh_completion_time: time taken for taklet completion + * @bh_handled_evt_cnt: no. of events handled by tasklet per interrupt + * @bh_dbg_index: index for capturing bh_completion_time and bh_handled_evt_cnt + * @wait_linkstate: waitqueue for waiting LINK to move into required state + * @vbus_draw: current to be drawn from USB + * @imod_interval: set the interrupt moderation interval in 250ns + * increments or 0 to disable. + * @create_reg_debugfs: create debugfs entry to allow dwc3 register dump */ struct dwc3 { struct usb_ctrlrequest *ctrl_req; struct dwc3_trb *ep0_trb; void *ep0_bounce; + void *zlp_buf; void *scratchbuf; u8 *setup_buf; dma_addr_t ctrl_req_addr; @@ -764,6 +889,7 @@ void __iomem *regs; size_t regs_size; + phys_addr_t reg_phys; enum usb_dr_mode dr_mode; @@ -773,8 +899,13 @@ u32 nr_scratch; u32 num_event_buffers; + u32 num_normal_event_buffers; + u32 num_gsi_event_buffers; + + u32 u1; u32 u1u2; u32 maximum_speed; + u32 max_hw_supp_speed; /* * All 3.1 IP version constants are greater than the 3.0 IP @@ -804,6 +935,8 @@ #define DWC3_REVISION_260A 0x5533260a #define DWC3_REVISION_270A 0x5533270a #define DWC3_REVISION_280A 0x5533280a +#define DWC3_REVISION_300A 0x5533300a +#define DWC3_REVISION_310A 0x5533310a /* * NOTICE: we're using bit 31 as a "is usb 3.1" flag. This is really @@ -811,6 +944,7 @@ */ #define DWC3_REVISION_IS_DWC31 0x80000000 #define DWC3_USB31_REVISION_110A (0x3131302a | DWC3_REVISION_IS_USB31) +#define DWC3_USB31_REVISION_120A (0x3132302a | DWC3_REVISION_IS_DWC31) enum dwc3_ep0_next ep0_next_event; enum dwc3_ep0_state ep0state; @@ -840,6 +974,9 @@ const char *hsphy_interface; + void (*notify_event)(struct dwc3 *, unsigned, unsigned); + struct work_struct wakeup_work; + unsigned delayed_status:1; unsigned ep0_bounced:1; unsigned ep0_expect_in:1; @@ -868,6 +1005,49 @@ unsigned tx_de_emphasis_quirk:1; unsigned tx_de_emphasis:2; + + unsigned is_drd:1; + /* Indicate if the gadget was powered by the otg driver */ + unsigned vbus_active:1; + /* Indicate if software connect was issued by the usb_gadget_driver */ + unsigned softconnect:1; + unsigned nominal_elastic_buffer:1; + unsigned err_evt_seen:1; + unsigned usb3_u1u2_disable:1; + /* Indicate if need to disable controller internal clkgating */ + unsigned disable_clk_gating:1; + unsigned enable_bus_suspend:1; + + struct dwc3_gadget_events dbg_gadget_events; + + atomic_t in_lpm; + int tx_fifo_size; + bool b_suspend; + unsigned vbus_draw; + + u16 imod_interval; + + struct workqueue_struct *dwc_wq; + struct work_struct bh_work; + + /* IRQ timing statistics */ + int irq; + unsigned long irq_cnt; + unsigned long last_irq_cnt; + unsigned long ep_cmd_timeout_cnt; + unsigned bh_completion_time[MAX_INTR_STATS]; + unsigned bh_handled_evt_cnt[MAX_INTR_STATS]; + unsigned bh_dbg_index; + ktime_t irq_start_time[MAX_INTR_STATS]; + ktime_t t_pwr_evt_irq; + unsigned irq_completion_time[MAX_INTR_STATS]; + unsigned irq_event_count[MAX_INTR_STATS]; + unsigned irq_dbg_index; + + unsigned long l1_remote_wakeup_cnt; + + wait_queue_head_t wait_linkstate; + bool create_reg_debugfs; }; /* -------------------------------------------------------------------------- */ @@ -1019,6 +1199,20 @@ void dwc3_set_mode(struct dwc3 *dwc, u32 mode); int dwc3_gadget_resize_tx_fifos(struct dwc3 *dwc); +/* check whether we are on the DWC_usb3 core */ +static inline bool dwc3_is_usb3(struct dwc3 *dwc) +{ + return !(dwc->revision & DWC3_REVISION_IS_DWC31); +} + +/* check whether we are on the DWC_usb31 core */ +static inline bool dwc3_is_usb31(struct dwc3 *dwc) +{ + return !!(dwc->revision & DWC3_REVISION_IS_DWC31); +} + +bool dwc3_has_imod(struct dwc3 *dwc); + #if IS_ENABLED(CONFIG_USB_DWC3_HOST) || IS_ENABLED(CONFIG_USB_DWC3_DUAL_ROLE) int dwc3_host_init(struct dwc3 *dwc); void dwc3_host_exit(struct dwc3 *dwc); @@ -1032,17 +1226,22 @@ #if IS_ENABLED(CONFIG_USB_DWC3_GADGET) || IS_ENABLED(CONFIG_USB_DWC3_DUAL_ROLE) int dwc3_gadget_init(struct dwc3 *dwc); void dwc3_gadget_exit(struct dwc3 *dwc); +void dwc3_gadget_restart(struct dwc3 *dwc); int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode); int dwc3_gadget_get_link_state(struct dwc3 *dwc); int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state); int dwc3_send_gadget_ep_cmd(struct dwc3 *dwc, unsigned ep, unsigned cmd, struct dwc3_gadget_ep_cmd_params *params); int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned cmd, u32 param); +void dwc3_gadget_enable_irq(struct dwc3 *dwc); +void dwc3_gadget_disable_irq(struct dwc3 *dwc); #else static inline int dwc3_gadget_init(struct dwc3 *dwc) { return 0; } static inline void dwc3_gadget_exit(struct dwc3 *dwc) { } +static inline void dwc3_gadget_restart(struct dwc3 *dwc) +{ } static inline int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode) { return 0; } static inline int dwc3_gadget_get_link_state(struct dwc3 *dwc) @@ -1057,6 +1256,10 @@ static inline int dwc3_send_gadget_generic_command(struct dwc3 *dwc, int cmd, u32 param) { return 0; } +static inline void dwc3_gadget_enable_irq(struct dwc3 *dwc) +{ } +static inline void dwc3_gadget_disable_irq(struct dwc3 *dwc) +{ } #endif /* power management interface */ @@ -1075,6 +1278,7 @@ } #endif /* !IS_ENABLED(CONFIG_USB_DWC3_HOST) */ + #if IS_ENABLED(CONFIG_USB_DWC3_ULPI) int dwc3_ulpi_init(struct dwc3 *dwc); void dwc3_ulpi_exit(struct dwc3 *dwc); @@ -1085,4 +1289,15 @@ { } #endif + +int dwc3_core_init(struct dwc3 *dwc); +int dwc3_core_pre_init(struct dwc3 *dwc); +void dwc3_post_host_reset_core_init(struct dwc3 *dwc); +int dwc3_event_buffers_setup(struct dwc3 *dwc); +void dwc3_usb3_phy_suspend(struct dwc3 *dwc, int suspend); + +extern void dwc3_set_notifier( + void (*notify)(struct dwc3 *dwc3, unsigned event, unsigned value)); +extern int dwc3_notify_event(struct dwc3 *dwc3, unsigned event, unsigned value); + #endif /* __DRIVERS_USB_DWC3_CORE_H */ diff -ruw linux-4.4.115/drivers/usb/dwc3/debugfs.c linux-4.4.115-fbx/drivers/usb/dwc3/debugfs.c --- linux-4.4.115/drivers/usb/dwc3/debugfs.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/usb/dwc3/debugfs.c 2019-01-22 16:16:27.255280383 +0100 @@ -16,6 +16,7 @@ * GNU General Public License for more details. */ +#include #include #include #include @@ -39,6 +40,9 @@ .offset = DWC3_ ##nm - DWC3_GLOBALS_REGS_START, \ } +#define ep_event_rate(ev, c, p, dt) \ + ((dt) ? ((c.ev - p.ev) * (MSEC_PER_SEC)) / (dt) : 0) + static const struct debugfs_reg32 dwc3_regs[] = { dump_register(GSBUSCFG0), dump_register(GSBUSCFG1), @@ -210,6 +214,7 @@ dump_register(GEVNTCOUNT(0)), dump_register(GHWPARAMS8), + dump_register(GFLADJ), dump_register(DCFG), dump_register(DCTL), dump_register(DEVTEN), @@ -363,6 +368,11 @@ unsigned long flags; u32 reg; + if (atomic_read(&dwc->in_lpm)) { + seq_puts(s, "USB device is powered off\n"); + return 0; + } + spin_lock_irqsave(&dwc->lock, flags); reg = dwc3_readl(dwc->regs, DWC3_GCTL); spin_unlock_irqrestore(&dwc->lock, flags); @@ -396,7 +406,12 @@ struct dwc3 *dwc = s->private; unsigned long flags; u32 mode = 0; - char buf[32]; + char buf[32] = {}; + + if (atomic_read(&dwc->in_lpm)) { + dev_err(dwc->dev, "USB device is powered off\n"); + return count; + } if (copy_from_user(&buf, ubuf, min_t(size_t, sizeof(buf) - 1, count))) return -EFAULT; @@ -432,6 +447,12 @@ unsigned long flags; u32 reg; + + if (atomic_read(&dwc->in_lpm)) { + seq_puts(s, "USB device is powered off\n"); + return 0; + } + spin_lock_irqsave(&dwc->lock, flags); reg = dwc3_readl(dwc->regs, DWC3_DCTL); reg &= DWC3_DCTL_TSTCTRL_MASK; @@ -476,7 +497,12 @@ struct dwc3 *dwc = s->private; unsigned long flags; u32 testmode = 0; - char buf[32]; + char buf[32] = {}; + + if (atomic_read(&dwc->in_lpm)) { + seq_puts(s, "USB device is powered off\n"); + return count; + } if (copy_from_user(&buf, ubuf, min_t(size_t, sizeof(buf) - 1, count))) return -EFAULT; @@ -516,6 +542,11 @@ enum dwc3_link_state state; u32 reg; + if (atomic_read(&dwc->in_lpm)) { + seq_puts(s, "USB device is powered off\n"); + return 0; + } + spin_lock_irqsave(&dwc->lock, flags); reg = dwc3_readl(dwc->regs, DWC3_DSTS); state = DWC3_DSTS_USBLNKST(reg); @@ -583,7 +614,12 @@ struct dwc3 *dwc = s->private; unsigned long flags; enum dwc3_link_state state = 0; - char buf[32]; + char buf[32] = {}; + + if (atomic_read(&dwc->in_lpm)) { + seq_puts(s, "USB device is powered off\n"); + return count; + } if (copy_from_user(&buf, ubuf, min_t(size_t, sizeof(buf) - 1, count))) return -EFAULT; @@ -618,6 +654,600 @@ .release = single_release, }; +static int ep_num; +static ssize_t dwc3_store_ep_num(struct file *file, const char __user *ubuf, + size_t count, loff_t *ppos) +{ + struct seq_file *s = file->private_data; + struct dwc3 *dwc = s->private; + char kbuf[10] = {}; + unsigned int num, dir, temp; + unsigned long flags; + + if (copy_from_user(kbuf, ubuf, min_t(size_t, sizeof(kbuf) - 1, count))) + return -EFAULT; + + if (sscanf(kbuf, "%u %u", &num, &dir) != 2) + return -EINVAL; + + if (dir != 0 && dir != 1) + return -EINVAL; + + temp = (num << 1) + dir; + if (temp >= (dwc->num_in_eps + dwc->num_out_eps) || + temp >= DWC3_ENDPOINTS_NUM) + return -EINVAL; + + spin_lock_irqsave(&dwc->lock, flags); + ep_num = temp; + spin_unlock_irqrestore(&dwc->lock, flags); + + return count; +} + +static int dwc3_ep_req_list_show(struct seq_file *s, void *unused) +{ + struct dwc3 *dwc = s->private; + struct dwc3_ep *dep; + struct dwc3_request *req = NULL; + struct list_head *ptr = NULL; + unsigned long flags; + + spin_lock_irqsave(&dwc->lock, flags); + dep = dwc->eps[ep_num]; + + seq_printf(s, "%s request list: flags: 0x%x\n", dep->name, dep->flags); + list_for_each(ptr, &dep->request_list) { + req = list_entry(ptr, struct dwc3_request, list); + + seq_printf(s, + "req:0x%pK len: %d sts: %d dma:0x%pa num_sgs: %d\n", + req, req->request.length, req->request.status, + &req->request.dma, req->request.num_sgs); + } + spin_unlock_irqrestore(&dwc->lock, flags); + + return 0; +} + +static int dwc3_ep_req_list_open(struct inode *inode, struct file *file) +{ + return single_open(file, dwc3_ep_req_list_show, inode->i_private); +} + +static const struct file_operations dwc3_ep_req_list_fops = { + .open = dwc3_ep_req_list_open, + .write = dwc3_store_ep_num, + .read = seq_read, + .llseek = seq_lseek, + .release = single_release, +}; + +static int dwc3_ep_queued_req_show(struct seq_file *s, void *unused) +{ + struct dwc3 *dwc = s->private; + struct dwc3_ep *dep; + struct dwc3_request *req = NULL; + struct list_head *ptr = NULL; + unsigned long flags; + + spin_lock_irqsave(&dwc->lock, flags); + dep = dwc->eps[ep_num]; + + seq_printf(s, "%s queued reqs to HW: flags:0x%x\n", dep->name, + dep->flags); + list_for_each(ptr, &dep->req_queued) { + req = list_entry(ptr, struct dwc3_request, list); + + seq_printf(s, + "req:0x%pK len:%d sts:%d dma:%pa nsg:%d trb:0x%pK\n", + req, req->request.length, req->request.status, + &req->request.dma, req->request.num_sgs, req->trb); + } + spin_unlock_irqrestore(&dwc->lock, flags); + + return 0; +} + +static int dwc3_ep_queued_req_open(struct inode *inode, struct file *file) +{ + return single_open(file, dwc3_ep_queued_req_show, inode->i_private); +} + +const struct file_operations dwc3_ep_req_queued_fops = { + .open = dwc3_ep_queued_req_open, + .write = dwc3_store_ep_num, + .read = seq_read, + .llseek = seq_lseek, + .release = single_release, +}; + +static int dwc3_ep_trbs_show(struct seq_file *s, void *unused) +{ + struct dwc3 *dwc = s->private; + struct dwc3_ep *dep; + struct dwc3_trb *trb; + unsigned long flags; + int j; + + if (!ep_num) + return 0; + + spin_lock_irqsave(&dwc->lock, flags); + dep = dwc->eps[ep_num]; + + seq_printf(s, "%s trb pool: flags:0x%x freeslot:%d busyslot:%d\n", + dep->name, dep->flags, dep->free_slot, dep->busy_slot); + for (j = 0; j < DWC3_TRB_NUM; j++) { + trb = &dep->trb_pool[j]; + seq_printf(s, "trb:0x%pK bph:0x%x bpl:0x%x size:0x%x ctrl: %x\n", + trb, trb->bph, trb->bpl, trb->size, trb->ctrl); + } + spin_unlock_irqrestore(&dwc->lock, flags); + + return 0; +} + +static int dwc3_ep_trbs_list_open(struct inode *inode, struct file *file) +{ + return single_open(file, dwc3_ep_trbs_show, inode->i_private); +} + +const struct file_operations dwc3_ep_trb_list_fops = { + .open = dwc3_ep_trbs_list_open, + .write = dwc3_store_ep_num, + .read = seq_read, + .llseek = seq_lseek, + .release = single_release, +}; + +static unsigned int ep_addr_rxdbg_mask = 1; +module_param(ep_addr_rxdbg_mask, uint, S_IRUGO | S_IWUSR); +static unsigned int ep_addr_txdbg_mask = 1; +module_param(ep_addr_txdbg_mask, uint, S_IRUGO | S_IWUSR); + +/* Maximum debug message length */ +#define DBG_DATA_MSG 64UL + +/* Maximum number of messages */ +#define DBG_DATA_MAX 2048UL + +static struct { + char (buf[DBG_DATA_MAX])[DBG_DATA_MSG]; /* buffer */ + unsigned idx; /* index */ + unsigned tty; /* print to console? */ + rwlock_t lck; /* lock */ +} dbg_dwc3_data = { + .idx = 0, + .tty = 0, + .lck = __RW_LOCK_UNLOCKED(lck) +}; + +/** + * dbg_dec: decrements debug event index + * @idx: buffer index + */ +static inline void __maybe_unused dbg_dec(unsigned *idx) +{ + *idx = (*idx - 1) % DBG_DATA_MAX; +} + +/** + * dbg_inc: increments debug event index + * @idx: buffer index + */ +static inline void dbg_inc(unsigned *idx) +{ + *idx = (*idx + 1) % DBG_DATA_MAX; +} + +#define TIME_BUF_LEN 20 +/*get_timestamp - returns time of day in us */ +static char *get_timestamp(char *tbuf) +{ + unsigned long long t; + unsigned long nanosec_rem; + + t = cpu_clock(smp_processor_id()); + nanosec_rem = do_div(t, 1000000000)/1000; + scnprintf(tbuf, TIME_BUF_LEN, "[%5lu.%06lu] ", (unsigned long)t, + nanosec_rem); + return tbuf; +} + +static int allow_dbg_print(u8 ep_num) +{ + int dir, num; + + /* allow bus wide events */ + if (ep_num == 0xff) + return 1; + + dir = ep_num & 0x1; + num = ep_num >> 1; + num = 1 << num; + + if (dir && (num & ep_addr_txdbg_mask)) + return 1; + if (!dir && (num & ep_addr_rxdbg_mask)) + return 1; + + return 0; +} + +/** + * dbg_print: prints the common part of the event + * @addr: endpoint address + * @name: event name + * @status: status + * @extra: extra information + */ +void dbg_print(u8 ep_num, const char *name, int status, const char *extra) +{ + unsigned long flags; + char tbuf[TIME_BUF_LEN]; + + if (!allow_dbg_print(ep_num)) + return; + + write_lock_irqsave(&dbg_dwc3_data.lck, flags); + + scnprintf(dbg_dwc3_data.buf[dbg_dwc3_data.idx], DBG_DATA_MSG, + "%s\t? %02X %-12.12s %4i ?\t%s\n", + get_timestamp(tbuf), ep_num, name, status, extra); + + dbg_inc(&dbg_dwc3_data.idx); + + write_unlock_irqrestore(&dbg_dwc3_data.lck, flags); + + if (dbg_dwc3_data.tty != 0) + pr_notice("%s\t? %02X %-7.7s %4i ?\t%s\n", + get_timestamp(tbuf), ep_num, name, status, extra); +} + +/** + * dbg_done: prints a DONE event + * @addr: endpoint address + * @td: transfer descriptor + * @status: status + */ +void dbg_done(u8 ep_num, const u32 count, int status) +{ + char msg[DBG_DATA_MSG]; + + if (!allow_dbg_print(ep_num)) + return; + + scnprintf(msg, sizeof(msg), "%d", count); + dbg_print(ep_num, "DONE", status, msg); +} + +/** + * dbg_event: prints a generic event + * @addr: endpoint address + * @name: event name + * @status: status + */ +void dbg_event(u8 ep_num, const char *name, int status) +{ + if (!allow_dbg_print(ep_num)) + return; + + if (name != NULL) + dbg_print(ep_num, name, status, ""); +} + +/* + * dbg_queue: prints a QUEUE event + * @addr: endpoint address + * @req: USB request + * @status: status + */ +void dbg_queue(u8 ep_num, const struct usb_request *req, int status) +{ + char msg[DBG_DATA_MSG]; + + if (!allow_dbg_print(ep_num)) + return; + + if (req != NULL) { + scnprintf(msg, sizeof(msg), + "%d %d", !req->no_interrupt, req->length); + dbg_print(ep_num, "QUEUE", status, msg); + } +} + +/** + * dbg_setup: prints a SETUP event + * @addr: endpoint address + * @req: setup request + */ +void dbg_setup(u8 ep_num, const struct usb_ctrlrequest *req) +{ + char msg[DBG_DATA_MSG]; + + if (!allow_dbg_print(ep_num)) + return; + + if (req != NULL) { + scnprintf(msg, sizeof(msg), + "%02X %02X %04X %04X %d", req->bRequestType, + req->bRequest, le16_to_cpu(req->wValue), + le16_to_cpu(req->wIndex), le16_to_cpu(req->wLength)); + dbg_print(ep_num, "SETUP", 0, msg); + } +} + +/** + * dbg_print_reg: prints a reg value + * @name: reg name + * @reg: reg value to be printed + */ +void dbg_print_reg(const char *name, int reg) +{ + unsigned long flags; + + write_lock_irqsave(&dbg_dwc3_data.lck, flags); + + scnprintf(dbg_dwc3_data.buf[dbg_dwc3_data.idx], DBG_DATA_MSG, + "%s = 0x%08x\n", name, reg); + + dbg_inc(&dbg_dwc3_data.idx); + + write_unlock_irqrestore(&dbg_dwc3_data.lck, flags); + + if (dbg_dwc3_data.tty != 0) + pr_notice("%s = 0x%08x\n", name, reg); +} + +/** + * store_events: configure if events are going to be also printed to console + * + */ +static ssize_t dwc3_store_events(struct file *file, + const char __user *buf, size_t count, loff_t *ppos) +{ + int ret; + u8 tty; + + if (buf == NULL) { + pr_err("[%s] EINVAL\n", __func__); + ret = -EINVAL; + return ret; + } + + ret = kstrtou8_from_user(buf, count, 0, &tty); + if (ret < 0) { + pr_err("can't get enter value.\n"); + return ret; + } + + if (tty > 1) { + pr_err("<1|0>: enable|disable console log\n"); + ret = -EINVAL; + return ret; + } + + dbg_dwc3_data.tty = tty; + pr_info("tty = %u", dbg_dwc3_data.tty); + + return count; +} + +static int dwc3_gadget_data_events_show(struct seq_file *s, void *unused) +{ + unsigned long flags; + unsigned i; + + read_lock_irqsave(&dbg_dwc3_data.lck, flags); + + i = dbg_dwc3_data.idx; + if (strnlen(dbg_dwc3_data.buf[i], DBG_DATA_MSG)) + seq_printf(s, "%s\n", dbg_dwc3_data.buf[i]); + for (dbg_inc(&i); i != dbg_dwc3_data.idx; dbg_inc(&i)) { + if (!strnlen(dbg_dwc3_data.buf[i], DBG_DATA_MSG)) + continue; + seq_printf(s, "%s\n", dbg_dwc3_data.buf[i]); + } + + read_unlock_irqrestore(&dbg_dwc3_data.lck, flags); + + return 0; +} + +static int dwc3_gadget_data_events_open(struct inode *inode, struct file *f) +{ + return single_open(f, dwc3_gadget_data_events_show, inode->i_private); +} + +const struct file_operations dwc3_gadget_dbg_data_fops = { + .open = dwc3_gadget_data_events_open, + .read = seq_read, + .write = dwc3_store_events, + .llseek = seq_lseek, + .release = single_release, +}; + +static ssize_t dwc3_store_int_events(struct file *file, + const char __user *ubuf, size_t count, loff_t *ppos) +{ + int i, ret; + unsigned long flags; + struct seq_file *s = file->private_data; + struct dwc3 *dwc = s->private; + struct dwc3_ep *dep; + struct timespec ts; + u8 clear_stats; + + if (ubuf == NULL) { + pr_err("[%s] EINVAL\n", __func__); + ret = -EINVAL; + return ret; + } + + ret = kstrtou8_from_user(ubuf, count, 0, &clear_stats); + if (ret < 0) { + pr_err("can't get enter value.\n"); + return ret; + } + + if (clear_stats != 0) { + pr_err("Wrong value. To clear stats, enter value as 0.\n"); + ret = -EINVAL; + return ret; + } + + spin_lock_irqsave(&dwc->lock, flags); + + pr_debug("%s(): clearing debug interrupt buffers\n", __func__); + ts = current_kernel_time(); + for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) { + dep = dwc->eps[i]; + memset(&dep->dbg_ep_events, 0, sizeof(dep->dbg_ep_events)); + memset(&dep->dbg_ep_events_diff, 0, sizeof(dep->dbg_ep_events)); + dep->dbg_ep_events_ts = ts; + } + memset(&dwc->dbg_gadget_events, 0, sizeof(dwc->dbg_gadget_events)); + + spin_unlock_irqrestore(&dwc->lock, flags); + + return count; +} + +static int dwc3_gadget_int_events_show(struct seq_file *s, void *unused) +{ + unsigned long flags; + struct dwc3 *dwc = s->private; + struct dwc3_gadget_events *dbg_gadget_events; + struct dwc3_ep *dep; + int i; + struct timespec ts_delta; + struct timespec ts_current; + u32 ts_delta_ms; + + spin_lock_irqsave(&dwc->lock, flags); + dbg_gadget_events = &dwc->dbg_gadget_events; + + for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) { + dep = dwc->eps[i]; + + if (dep == NULL || !(dep->flags & DWC3_EP_ENABLED)) + continue; + + ts_current = current_kernel_time(); + ts_delta = timespec_sub(ts_current, dep->dbg_ep_events_ts); + ts_delta_ms = ts_delta.tv_nsec / NSEC_PER_MSEC + + ts_delta.tv_sec * MSEC_PER_SEC; + + seq_printf(s, "\n\n===== dbg_ep_events for EP(%d) %s =====\n", + i, dep->name); + seq_printf(s, "xfercomplete:%u @ %luHz\n", + dep->dbg_ep_events.xfercomplete, + ep_event_rate(xfercomplete, dep->dbg_ep_events, + dep->dbg_ep_events_diff, ts_delta_ms)); + seq_printf(s, "xfernotready:%u @ %luHz\n", + dep->dbg_ep_events.xfernotready, + ep_event_rate(xfernotready, dep->dbg_ep_events, + dep->dbg_ep_events_diff, ts_delta_ms)); + seq_printf(s, "control_data:%u @ %luHz\n", + dep->dbg_ep_events.control_data, + ep_event_rate(control_data, dep->dbg_ep_events, + dep->dbg_ep_events_diff, ts_delta_ms)); + seq_printf(s, "control_status:%u @ %luHz\n", + dep->dbg_ep_events.control_status, + ep_event_rate(control_status, dep->dbg_ep_events, + dep->dbg_ep_events_diff, ts_delta_ms)); + seq_printf(s, "xferinprogress:%u @ %luHz\n", + dep->dbg_ep_events.xferinprogress, + ep_event_rate(xferinprogress, dep->dbg_ep_events, + dep->dbg_ep_events_diff, ts_delta_ms)); + seq_printf(s, "rxtxfifoevent:%u @ %luHz\n", + dep->dbg_ep_events.rxtxfifoevent, + ep_event_rate(rxtxfifoevent, dep->dbg_ep_events, + dep->dbg_ep_events_diff, ts_delta_ms)); + seq_printf(s, "streamevent:%u @ %luHz\n", + dep->dbg_ep_events.streamevent, + ep_event_rate(streamevent, dep->dbg_ep_events, + dep->dbg_ep_events_diff, ts_delta_ms)); + seq_printf(s, "epcmdcomplt:%u @ %luHz\n", + dep->dbg_ep_events.epcmdcomplete, + ep_event_rate(epcmdcomplete, dep->dbg_ep_events, + dep->dbg_ep_events_diff, ts_delta_ms)); + seq_printf(s, "cmdcmplt:%u @ %luHz\n", + dep->dbg_ep_events.cmdcmplt, + ep_event_rate(cmdcmplt, dep->dbg_ep_events, + dep->dbg_ep_events_diff, ts_delta_ms)); + seq_printf(s, "unknown:%u @ %luHz\n", + dep->dbg_ep_events.unknown_event, + ep_event_rate(unknown_event, dep->dbg_ep_events, + dep->dbg_ep_events_diff, ts_delta_ms)); + seq_printf(s, "total:%u @ %luHz\n", + dep->dbg_ep_events.total, + ep_event_rate(total, dep->dbg_ep_events, + dep->dbg_ep_events_diff, ts_delta_ms)); + + dep->dbg_ep_events_ts = ts_current; + dep->dbg_ep_events_diff = dep->dbg_ep_events; + } + + seq_puts(s, "\n=== dbg_gadget events ==\n"); + seq_printf(s, "disconnect:%u\n reset:%u\n", + dbg_gadget_events->disconnect, dbg_gadget_events->reset); + seq_printf(s, "connect:%u\n wakeup:%u\n", + dbg_gadget_events->connect, dbg_gadget_events->wakeup); + seq_printf(s, "link_status_change:%u\n eopf:%u\n", + dbg_gadget_events->link_status_change, dbg_gadget_events->eopf); + seq_printf(s, "sof:%u\n suspend:%u\n", + dbg_gadget_events->sof, dbg_gadget_events->suspend); + seq_printf(s, "erratic_error:%u\n overflow:%u\n", + dbg_gadget_events->erratic_error, + dbg_gadget_events->overflow); + seq_printf(s, "vendor_dev_test_lmp:%u\n cmdcmplt:%u\n", + dbg_gadget_events->vendor_dev_test_lmp, + dbg_gadget_events->cmdcmplt); + seq_printf(s, "unknown_event:%u\n", dbg_gadget_events->unknown_event); + + seq_printf(s, "\n\t== Last %d interrupts stats ==\t\n", MAX_INTR_STATS); + seq_puts(s, "@ time (us):\t"); + for (i = 0; i < MAX_INTR_STATS; i++) + seq_printf(s, "%lld\t", ktime_to_us(dwc->irq_start_time[i])); + seq_puts(s, "\nhard irq time (us):\t"); + for (i = 0; i < MAX_INTR_STATS; i++) + seq_printf(s, "%d\t", dwc->irq_completion_time[i]); + seq_puts(s, "\nevents count:\t\t"); + for (i = 0; i < MAX_INTR_STATS; i++) + seq_printf(s, "%d\t", dwc->irq_event_count[i]); + seq_puts(s, "\nbh handled count:\t"); + for (i = 0; i < MAX_INTR_STATS; i++) + seq_printf(s, "%d\t", dwc->bh_handled_evt_cnt[i]); + seq_puts(s, "\nirq thread time (us):\t"); + for (i = 0; i < MAX_INTR_STATS; i++) + seq_printf(s, "%d\t", dwc->bh_completion_time[i]); + seq_putc(s, '\n'); + + seq_printf(s, "t_pwr evt irq : %lld\n", + ktime_to_us(dwc->t_pwr_evt_irq)); + + seq_printf(s, "l1_remote_wakeup_cnt : %lu\n", + dwc->l1_remote_wakeup_cnt); + + spin_unlock_irqrestore(&dwc->lock, flags); + return 0; +} + +static int dwc3_gadget_events_open(struct inode *inode, struct file *f) +{ + return single_open(f, dwc3_gadget_int_events_show, inode->i_private); +} + +const struct file_operations dwc3_gadget_dbg_events_fops = { + .open = dwc3_gadget_events_open, + .read = seq_read, + .write = dwc3_store_int_events, + .llseek = seq_lseek, + .release = single_release, +}; + int dwc3_debugfs_init(struct dwc3 *dwc) { struct dentry *root; @@ -642,11 +1272,15 @@ dwc->regset->nregs = ARRAY_SIZE(dwc3_regs); dwc->regset->base = dwc->regs; - file = debugfs_create_regset32("regdump", S_IRUGO, root, dwc->regset); + if (dwc->create_reg_debugfs) { + file = debugfs_create_regset32("regdump", 0444, + root, dwc->regset); if (!file) { + dev_dbg(dwc->dev, "Can't create debugfs regdump\n"); ret = -ENOMEM; goto err1; } + } if (IS_ENABLED(CONFIG_USB_DWC3_DUAL_ROLE)) { file = debugfs_create_file("mode", S_IRUGO | S_IWUSR, root, @@ -674,6 +1308,41 @@ } } + file = debugfs_create_file("trbs", S_IRUGO | S_IWUSR, root, + dwc, &dwc3_ep_trb_list_fops); + if (!file) { + ret = -ENOMEM; + goto err1; + } + + file = debugfs_create_file("requests", S_IRUGO | S_IWUSR, root, + dwc, &dwc3_ep_req_list_fops); + if (!file) { + ret = -ENOMEM; + goto err1; + } + + file = debugfs_create_file("queued_reqs", S_IRUGO | S_IWUSR, root, + dwc, &dwc3_ep_req_queued_fops); + if (!file) { + ret = -ENOMEM; + goto err1; + } + + file = debugfs_create_file("events", S_IRUGO | S_IWUSR, root, + dwc, &dwc3_gadget_dbg_data_fops); + if (!file) { + ret = -ENOMEM; + goto err1; + } + + file = debugfs_create_file("int_events", S_IRUGO | S_IWUSR, root, + dwc, &dwc3_gadget_dbg_events_fops); + if (!file) { + ret = -ENOMEM; + goto err1; + } + return 0; err1: diff -ruw linux-4.4.115/drivers/usb/dwc3/debug.h linux-4.4.115-fbx/drivers/usb/dwc3/debug.h --- linux-4.4.115/drivers/usb/dwc3/debug.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/usb/dwc3/debug.h 2019-01-22 16:16:27.255280383 +0100 @@ -217,9 +217,29 @@ void dwc3_trace(void (*trace)(struct va_format *), const char *fmt, ...); #ifdef CONFIG_DEBUG_FS +extern void dbg_event(u8, const char*, int); +extern void dbg_print(u8, const char*, int, const char*); +extern void dbg_done(u8, const u32, int); +extern void dbg_queue(u8, const struct usb_request*, int); +extern void dbg_setup(u8, const struct usb_ctrlrequest*); extern int dwc3_debugfs_init(struct dwc3 *); extern void dwc3_debugfs_exit(struct dwc3 *); +extern void dbg_print_reg(const char *name, int reg); #else +static inline void dbg_event(u8 ep_num, const char *name, int status) +{ } +static inline void dbg_print(u8 ep_num, const char *name, int status, + const char *extra) +{ } +static inline void dbg_done(u8 ep_num, const u32 count, int status) +{ } +static inline void dbg_queue(u8 ep_num, const struct usb_request *req, + int status) +{ } +static inline void dbg_setup(u8 ep_num, const struct usb_ctrlrequest *req) +{ } +static inline void dbg_print_reg(const char *name, int reg) +{ } static inline int dwc3_debugfs_init(struct dwc3 *d) { return 0; } static inline void dwc3_debugfs_exit(struct dwc3 *d) diff -ruw linux-4.4.115/drivers/usb/dwc3/gadget.h linux-4.4.115-fbx/drivers/usb/dwc3/gadget.h --- linux-4.4.115/drivers/usb/dwc3/gadget.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/usb/dwc3/gadget.h 2019-01-22 16:16:27.263280456 +0100 @@ -68,6 +68,14 @@ return list_first_entry(list, struct dwc3_request, list); } +static inline void dwc3_gadget_move_request_list_front(struct dwc3_request *req) +{ + struct dwc3_ep *dep = req->dep; + + req->queued = false; + list_move(&req->list, &dep->request_list); +} + static inline void dwc3_gadget_move_request_queued(struct dwc3_request *req) { struct dwc3_ep *dep = req->dep; @@ -76,17 +84,49 @@ list_move_tail(&req->list, &dep->req_queued); } +static inline enum dwc3_link_state dwc3_get_link_state(struct dwc3 *dwc) +{ + u32 reg; + + reg = dwc3_readl(dwc->regs, DWC3_DSTS); + return DWC3_DSTS_USBLNKST(reg); +} + void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req, int status); void dwc3_ep0_interrupt(struct dwc3 *dwc, const struct dwc3_event_depevt *event); void dwc3_ep0_out_start(struct dwc3 *dwc); +void dwc3_ep0_stall_and_restart(struct dwc3 *dwc); int __dwc3_gadget_ep0_set_halt(struct usb_ep *ep, int value); int dwc3_gadget_ep0_set_halt(struct usb_ep *ep, int value); int dwc3_gadget_ep0_queue(struct usb_ep *ep, struct usb_request *request, gfp_t gfp_flags); int __dwc3_gadget_ep_set_halt(struct dwc3_ep *dep, int value, int protocol); +void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum, bool force); + +#if IS_ENABLED(CONFIG_USB_DWC3_GADGET) || IS_ENABLED(CONFIG_USB_DWC3_DUAL_ROLE) +void dwc3_gadget_interrupt(struct dwc3 *dwc, + const struct dwc3_event_devt *event); +void dwc3_endpoint_interrupt(struct dwc3 *dwc, + const struct dwc3_event_depevt *event); +#else +static inline void dwc3_gadget_interrupt(struct dwc3 *dwc, + const struct dwc3_event_devt *event) +{ } +static inline void dwc3_endpoint_interrupt(struct dwc3 *dwc, + const struct dwc3_event_depevt *event) +{ } +#endif + +static inline dma_addr_t dwc3_trb_dma_offset(struct dwc3_ep *dep, + struct dwc3_trb *trb) +{ + u32 offset = (char *) trb - (char *) dep->trb_pool; + + return dep->trb_pool_dma + offset; +} /** * dwc3_gadget_ep_get_transfer_index - Gets transfer index from HW diff -ruw linux-4.4.115/drivers/usb/dwc3/host.c linux-4.4.115-fbx/drivers/usb/dwc3/host.c --- linux-4.4.115/drivers/usb/dwc3/host.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/usb/dwc3/host.c 2019-01-22 16:16:27.263280456 +0100 @@ -25,6 +25,7 @@ struct platform_device *xhci; struct usb_xhci_pdata pdata; int ret; + struct device_node *node = dwc->dev->of_node; xhci = platform_device_alloc("xhci-hcd", PLATFORM_DEVID_AUTO); if (!xhci) { @@ -32,6 +33,7 @@ return -ENOMEM; } + arch_setup_dma_ops(&xhci->dev, 0, 0, NULL, 0); dma_set_coherent_mask(&xhci->dev, dwc->dev->coherent_dma_mask); xhci->dev.parent = dwc->dev; @@ -51,6 +53,11 @@ pdata.usb3_lpm_capable = dwc->usb3_lpm_capable; + ret = of_property_read_u32(node, "xhci-imod-value", + &pdata.imod_interval); + if (ret) + pdata.imod_interval = 0; /* use default xhci.c value */ + ret = platform_device_add_data(xhci, &pdata, sizeof(pdata)); if (ret) { dev_err(dwc->dev, "couldn't add platform data to xHCI device\n"); @@ -62,18 +69,9 @@ phy_create_lookup(dwc->usb3_generic_phy, "usb3-phy", dev_name(&xhci->dev)); - ret = platform_device_add(xhci); - if (ret) { - dev_err(dwc->dev, "failed to register xHCI device\n"); - goto err2; - } - + /* Platform device gets added as part of state machine */ return 0; -err2: - phy_remove_lookup(dwc->usb2_generic_phy, "usb2-phy", - dev_name(&xhci->dev)); - phy_remove_lookup(dwc->usb3_generic_phy, "usb3-phy", - dev_name(&xhci->dev)); + err1: platform_device_put(xhci); return ret; @@ -85,5 +83,6 @@ dev_name(&dwc->xhci->dev)); phy_remove_lookup(dwc->usb3_generic_phy, "usb3-phy", dev_name(&dwc->xhci->dev)); + if (!dwc->is_drd) platform_device_unregister(dwc->xhci); } diff -ruw linux-4.4.115/drivers/usb/dwc3/io.h linux-4.4.115-fbx/drivers/usb/dwc3/io.h --- linux-4.4.115/drivers/usb/dwc3/io.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/usb/dwc3/io.h 2019-01-22 16:16:27.263280456 +0100 @@ -41,7 +41,7 @@ * documentation, so we revert it back to the proper addresses, the * same way they are described on SNPS documentation */ - dwc3_trace(trace_dwc3_readl, "addr %p value %08x", + dwc3_trace(trace_dwc3_readl, "addr %pK value %08x", base - DWC3_GLOBALS_REGS_START + offset, value); return value; @@ -63,7 +63,7 @@ * documentation, so we revert it back to the proper addresses, the * same way they are described on SNPS documentation */ - dwc3_trace(trace_dwc3_writel, "addr %p value %08x", + dwc3_trace(trace_dwc3_writel, "addr %pK value %08x", base - DWC3_GLOBALS_REGS_START + offset, value); } diff -ruw linux-4.4.115/drivers/usb/dwc3/Makefile linux-4.4.115-fbx/drivers/usb/dwc3/Makefile --- linux-4.4.115/drivers/usb/dwc3/Makefile 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/usb/dwc3/Makefile 2019-01-22 16:16:27.255280383 +0100 @@ -1,5 +1,6 @@ # define_trace.h needs to know how to find our header CFLAGS_trace.o := -I$(src) +CFLAGS_dwc3-msm.o := -Idrivers/usb/host -Idrivers/base/power obj-$(CONFIG_USB_DWC3) += dwc3.o @@ -37,5 +38,5 @@ obj-$(CONFIG_USB_DWC3_EXYNOS) += dwc3-exynos.o obj-$(CONFIG_USB_DWC3_PCI) += dwc3-pci.o obj-$(CONFIG_USB_DWC3_KEYSTONE) += dwc3-keystone.o -obj-$(CONFIG_USB_DWC3_QCOM) += dwc3-qcom.o +obj-$(CONFIG_USB_DWC3_QCOM) += dwc3-qcom.o dwc3-msm.o dbm.o obj-$(CONFIG_USB_DWC3_ST) += dwc3-st.o diff -ruw linux-4.4.115/drivers/usb/dwc3/trace.h linux-4.4.115-fbx/drivers/usb/dwc3/trace.h --- linux-4.4.115/drivers/usb/dwc3/trace.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/usb/dwc3/trace.h 2019-01-22 16:16:27.263280456 +0100 @@ -125,7 +125,7 @@ __entry->length = req->request.length; __entry->status = req->request.status; ), - TP_printk("%s: req %p length %u/%u ==> %d", + TP_printk("%s: req %pK length %u/%u ==> %d", __get_str(name), __entry->req, __entry->actual, __entry->length, __entry->status ) @@ -228,7 +228,7 @@ __entry->size = trb->size; __entry->ctrl = trb->ctrl; ), - TP_printk("%s: trb %p bph %08x bpl %08x size %08x ctrl %08x", + TP_printk("%s: trb %pK bph %08x bpl %08x size %08x ctrl %08x", __get_str(name), __entry->trb, __entry->bph, __entry->bpl, __entry->size, __entry->ctrl ) diff -ruw linux-4.4.115/drivers/usb/gadget/function/Makefile linux-4.4.115-fbx/drivers/usb/gadget/function/Makefile --- linux-4.4.115/drivers/usb/gadget/function/Makefile 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/usb/gadget/function/Makefile 2019-10-29 09:26:24.993216389 +0100 @@ -44,3 +44,25 @@ obj-$(CONFIG_USB_F_HID) += usb_f_hid.o usb_f_printer-y := f_printer.o obj-$(CONFIG_USB_F_PRINTER) += usb_f_printer.o +usb_f_mtp-y := f_mtp.o +obj-$(CONFIG_USB_F_MTP) += usb_f_mtp.o +usb_f_ptp-y := f_ptp.o +obj-$(CONFIG_USB_F_PTP) += usb_f_ptp.o +usb_f_audio_source-y := f_audio_source.o +obj-$(CONFIG_USB_F_AUDIO_SRC) += usb_f_audio_source.o +usb_f_accessory-y := f_accessory.o +obj-$(CONFIG_USB_F_ACC) += usb_f_accessory.o +usb_f_diag-y := f_diag.o +obj-$(CONFIG_USB_F_DIAG) += usb_f_diag.o +usb_f_gsi-y := f_gsi.o rndis.o +obj-$(CONFIG_USB_F_GSI) += usb_f_gsi.o +usb_f_cdev-y := f_cdev.o +obj-$(CONFIG_USB_F_CDEV) += usb_f_cdev.o +usb_f_qdss-y := f_qdss.o u_qdss.o +obj-$(CONFIG_USB_F_QDSS) += usb_f_qdss.o +usb_f_qcrndis-y := f_qc_rndis.o rndis.o u_data_ipa.o +obj-$(CONFIG_USB_F_QCRNDIS) += usb_f_qcrndis.o +usb_f_rmnet_bam-y := f_rmnet.o u_ctrl_qti.o +obj-$(CONFIG_USB_F_RMNET_BAM) += usb_f_rmnet_bam.o +usb_f_ccid-y := f_ccid.o +obj-$(CONFIG_USB_F_CCID) += usb_f_ccid.o diff -ruw linux-4.4.115/drivers/usb/gadget/Kconfig linux-4.4.115-fbx/drivers/usb/gadget/Kconfig --- linux-4.4.115/drivers/usb/gadget/Kconfig 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/usb/gadget/Kconfig 2019-10-29 09:26:24.989216350 +0100 @@ -175,6 +175,12 @@ config USB_F_RNDIS tristate +config USB_F_QCRNDIS + tristate + +config USB_F_RMNET_BAM + tristate + config USB_F_MASS_STORAGE tristate @@ -199,6 +205,33 @@ config USB_F_PRINTER tristate +config USB_F_MTP + tristate + +config USB_F_PTP + tristate + +config USB_F_AUDIO_SRC + tristate + +config USB_F_ACC + tristate + +config USB_F_DIAG + tristate + +config USB_F_GSI + tristate + +config USB_F_CDEV + tristate + +config USB_F_QDSS + tristate + +config USB_F_CCID + tristate + choice tristate "USB Gadget Drivers" default USB_ETH @@ -294,6 +327,14 @@ On hardware that can't implement the full protocol, a simple CDC subset is used, placing fewer demands on USB. +config USB_CONFIGFS_QCRNDIS + bool "QCRNDIS" + depends on USB_CONFIGFS + depends on RNDIS_IPA + depends on NET + select USB_U_ETHER + select USB_F_QCRNDIS + config USB_CONFIGFS_RNDIS bool "RNDIS" depends on USB_CONFIGFS @@ -310,6 +351,12 @@ XP, you'll need to download drivers from Microsoft's website; a URL is given in comments found in that info file. +config USB_CONFIGFS_RMNET_BAM + bool "RMNET" + depends on USB_CONFIGFS + depends on IPA + select USB_F_RMNET_BAM + config USB_CONFIGFS_EEM bool "Ethernet Emulation Model (EEM)" depends on USB_CONFIGFS @@ -371,6 +418,44 @@ implemented in kernel space (for instance Ethernet, serial or mass storage) and other are implemented in user space. +config USB_CONFIGFS_F_MTP + boolean "MTP gadget" + depends on USB_CONFIGFS + select USB_F_MTP + help + USB gadget MTP support + +config USB_CONFIGFS_F_PTP + boolean "PTP gadget" + depends on USB_CONFIGFS && USB_CONFIGFS_F_MTP + select USB_F_PTP + help + USB gadget PTP support + +config USB_CONFIGFS_F_ACC + boolean "Accessory gadget" + depends on USB_CONFIGFS + select USB_F_ACC + help + USB gadget Accessory support + +config USB_CONFIGFS_F_AUDIO_SRC + boolean "Audio Source gadget" + depends on USB_CONFIGFS && USB_CONFIGFS_F_ACC + depends on SND + select SND_PCM + select USB_F_AUDIO_SRC + help + USB gadget Audio Source support + +config USB_CONFIGFS_UEVENT + boolean "Uevent notification of Gadget state" + depends on USB_CONFIGFS + help + Enable uevent notifications to userspace when the gadget + state changes. The gadget can be in any of the following + three states: "CONNECTED/DISCONNECTED/CONFIGURED" + config USB_CONFIGFS_F_UAC1 bool "Audio Class 1.0" depends on USB_CONFIGFS @@ -451,6 +536,43 @@ For more information, see Documentation/usb/gadget_printer.txt which includes sample code for accessing the device file. +config USB_CONFIGFS_F_DIAG + bool "USB Diag function" + select USB_F_DIAG + depends on USB_CONFIGFS + help + Diag function driver enables support for Qualcomm diagnostics + port over USB. + +config USB_CONFIGFS_F_GSI + bool "USB GSI function" + select USB_F_GSI + depends on USB_CONFIGFS + help + Generic function driver to support h/w acceleration to IPA over GSI. + +config USB_CONFIGFS_F_CDEV + bool "USB Serial Character function" + select USB_F_CDEV + depends on USB_CONFIGFS + help + Generic USB serial character function driver to support DUN/NMEA. + +config USB_CONFIGFS_F_QDSS + bool "USB QDSS function" + select USB_F_QDSS + depends on USB_CONFIGFS + help + USB QDSS function driver to get hwtracing related data over USB. + +config USB_CONFIGFS_F_CCID + bool "USB CCID function" + select USB_F_CCID + depends on USB_CONFIGFS + help + USB CCID function driver creats transport layer between the + userspace CCID component and the Windows Host. + source "drivers/usb/gadget/legacy/Kconfig" endchoice diff -ruw linux-4.4.115/drivers/usb/gadget/Makefile linux-4.4.115-fbx/drivers/usb/gadget/Makefile --- linux-4.4.115/drivers/usb/gadget/Makefile 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/usb/gadget/Makefile 2019-01-22 16:16:27.263280456 +0100 @@ -10,3 +10,4 @@ libcomposite-y += composite.o functions.o configfs.o u_f.o obj-$(CONFIG_USB_GADGET) += udc/ function/ legacy/ +obj-y += debug.o diff -ruw linux-4.4.115/drivers/usb/host/xhci.c linux-4.4.115-fbx/drivers/usb/host/xhci.c --- linux-4.4.115/drivers/usb/host/xhci.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/usb/host/xhci.c 2019-10-29 09:26:25.033216781 +0100 @@ -114,10 +114,20 @@ STS_HALT, STS_HALT, XHCI_MAX_HALT_USEC); if (!ret) { xhci->xhc_state |= XHCI_STATE_HALTED; - xhci->cmd_ring_state = CMD_RING_STATE_STOPPED; - } else + } else { xhci_warn(xhci, "Host not halted after %u microseconds.\n", XHCI_MAX_HALT_USEC); + } + + xhci->cmd_ring_state = CMD_RING_STATE_STOPPED; + + if (delayed_work_pending(&xhci->cmd_timer)) { + xhci_dbg_trace(xhci, trace_xhci_dbg_init, + "Cleanup command queue"); + cancel_delayed_work(&xhci->cmd_timer); + xhci_cleanup_command_queue(xhci); + } + return ret; } @@ -128,7 +138,13 @@ { u32 temp; int ret; + struct usb_hcd *hcd = xhci_to_hcd(xhci); + /* + * disable irq to avoid xhci_irq flooding due to unhandeled port + * change event in halt state, as soon as xhci_start clears halt bit + */ + disable_irq(hcd->irq); temp = readl(&xhci->op_regs->command); temp |= (CMD_RUN); xhci_dbg_trace(xhci, trace_xhci_dbg_init, "// Turn on HC, cmd = 0x%x.", @@ -149,6 +165,8 @@ /* clear state flags. Including dying, halted or removing */ xhci->xhc_state = 0; + enable_irq(hcd->irq); + return ret; } @@ -647,7 +665,7 @@ temp = readl(&xhci->ir_set->irq_pending); xhci_dbg_trace(xhci, trace_xhci_dbg_init, - "// Enabling event ring interrupter %p by writing 0x%x to irq_pending", + "// Enabling event ring interrupter %pK by writing 0x%x to irq_pending", xhci->ir_set, (unsigned int) ER_IRQ_ENABLE(temp)); writel(ER_IRQ_ENABLE(temp), &xhci->ir_set->irq_pending); xhci_print_ir_set(xhci, 0); @@ -745,6 +763,10 @@ usb_disable_xhci_ports(to_pci_dev(hcd->self.controller)); spin_lock_irq(&xhci->lock); + if (!HCD_HW_ACCESSIBLE(hcd)) { + spin_unlock_irq(&xhci->lock); + return; + } xhci_halt(xhci); /* Workaround for spurious wakeups at shutdown with HSW */ if (xhci->quirks & XHCI_SPURIOUS_WAKEUP) @@ -900,7 +922,7 @@ struct usb_hcd *hcd = xhci_to_hcd(xhci); u32 command; - if (!hcd->state) + if (!hcd->state || xhci->suspended) return 0; if (hcd->state != HC_STATE_SUSPENDED || @@ -970,6 +992,7 @@ /* step 5: remove core well power */ /* synchronize irq when using MSI-X */ xhci_msix_sync_irqs(xhci); + xhci->suspended = true; return rc; } @@ -989,7 +1012,7 @@ int retval = 0; bool comp_timer_running = false; - if (!hcd->state) + if (!hcd->state || !xhci->suspended) return 0; /* Wait a bit if either of the roothubs need to settle from the @@ -1123,6 +1146,7 @@ /* Re-enable port polling. */ xhci_dbg(xhci, "%s: starting port polling.\n", __func__); + xhci->suspended = false; set_bit(HCD_FLAG_POLL_RH, &xhci->shared_hcd->flags); usb_hcd_poll_rh_status(xhci->shared_hcd); set_bit(HCD_FLAG_POLL_RH, &hcd->flags); @@ -1446,7 +1470,7 @@ exit: return ret; dying: - xhci_dbg(xhci, "Ep 0x%x: URB %p submitted for " + xhci_dbg(xhci, "Ep 0x%x: URB %pK submitted for " "non-responsive xHCI host.\n", urb->ep->desc.bEndpointAddress, urb); ret = -ESHUTDOWN; @@ -1582,7 +1606,7 @@ i = urb_priv->td_cnt; if (i < urb_priv->length) xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, - "Cancel URB %p, dev %s, ep 0x%x, " + "Cancel URB %pK, dev %s, ep 0x%x, " "starting at offset 0x%llx", urb, urb->dev->devpath, urb->ep->desc.bEndpointAddress, @@ -1650,7 +1674,7 @@ if (xhci->xhc_state & XHCI_STATE_DYING) return -ENODEV; - xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev); + xhci_dbg(xhci, "%s called for udev %pK\n", __func__, udev); drop_flag = xhci_get_endpoint_flag(&ep->desc); if (drop_flag == SLOT_FLAG || drop_flag == EP0_FLAG) { xhci_dbg(xhci, "xHCI %s - can't drop slot or ep 0 %#x\n", @@ -1678,7 +1702,7 @@ xhci_get_endpoint_flag(&ep->desc)) { /* Do not warn when called after a usb_device_reset */ if (xhci->devs[udev->slot_id]->eps[ep_index].ring != NULL) - xhci_warn(xhci, "xHCI %s called with disabled ep %p\n", + xhci_warn(xhci, "xHCI %s called with disabled ep %pK\n", __func__, ep); return 0; } @@ -1770,7 +1794,7 @@ * ignore this request. */ if (le32_to_cpu(ctrl_ctx->add_flags) & added_ctxs) { - xhci_warn(xhci, "xHCI %s called with enabled ep %p\n", + xhci_warn(xhci, "xHCI %s called with enabled ep %pK\n", __func__, ep); return 0; } @@ -2751,7 +2775,7 @@ (xhci->xhc_state & XHCI_STATE_REMOVING)) return -ENODEV; - xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev); + xhci_dbg(xhci, "%s called for udev %pK\n", __func__, udev); virt_dev = xhci->devs[udev->slot_id]; command = xhci_alloc_command(xhci, false, true, GFP_KERNEL); @@ -2848,7 +2872,7 @@ return; xhci = hcd_to_xhci(hcd); - xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev); + xhci_dbg(xhci, "%s called for udev %pK\n", __func__, udev); virt_dev = xhci->devs[udev->slot_id]; /* Free any rings allocated for added endpoints */ for (i = 0; i < 31; ++i) { @@ -2901,7 +2925,7 @@ if (addr == 0) { xhci_warn(xhci, "WARN Cannot submit config ep after " "reset ep command\n"); - xhci_warn(xhci, "WARN deq seg = %p, deq ptr = %p\n", + xhci_warn(xhci, "WARN deq seg = %pK, deq ptr = %pK\n", deq_state->new_deq_seg, deq_state->new_deq_ptr); return; @@ -3925,7 +3949,7 @@ xhci_dbg_trace(xhci, trace_xhci_dbg_address, "Op regs DCBAA ptr = %#016llx", temp_64); xhci_dbg_trace(xhci, trace_xhci_dbg_address, - "Slot ID %d dcbaa entry @%p = %#016llx", + "Slot ID %d dcbaa entry @%pK = %#016llx", udev->slot_id, &xhci->dcbaa->dev_context_ptrs[udev->slot_id], (unsigned long long) @@ -4956,6 +4980,57 @@ } EXPORT_SYMBOL_GPL(xhci_gen_setup); +dma_addr_t xhci_get_sec_event_ring_dma_addr(struct usb_hcd *hcd, + unsigned intr_num) +{ + struct xhci_hcd *xhci = hcd_to_xhci(hcd); + + if (intr_num >= xhci->max_interrupters) { + xhci_err(xhci, "intr num %d >= max intrs %d\n", intr_num, + xhci->max_interrupters); + return 0; + } + + if (!(xhci->xhc_state & XHCI_STATE_HALTED) && + xhci->sec_event_ring && xhci->sec_event_ring[intr_num] + && xhci->sec_event_ring[intr_num]->first_seg) + return xhci->sec_event_ring[intr_num]->first_seg->dma; + + return 0; +} + +dma_addr_t xhci_get_xfer_ring_dma_addr(struct usb_hcd *hcd, + struct usb_device *udev, struct usb_host_endpoint *ep) +{ + int ret; + unsigned int ep_index; + struct xhci_virt_device *virt_dev; + + struct xhci_hcd *xhci = hcd_to_xhci(hcd); + + ret = xhci_check_args(hcd, udev, ep, 1, true, __func__); + if (ret <= 0) { + xhci_err(xhci, "%s: invalid args\n", __func__); + return 0; + } + + virt_dev = xhci->devs[udev->slot_id]; + ep_index = xhci_get_endpoint_index(&ep->desc); + + if (virt_dev->eps[ep_index].ring && + virt_dev->eps[ep_index].ring->first_seg) + return virt_dev->eps[ep_index].ring->first_seg->dma; + + return 0; +} + +int xhci_get_core_id(struct usb_hcd *hcd) +{ + struct xhci_hcd *xhci = hcd_to_xhci(hcd); + + return xhci->core_id; +} + static const struct hc_driver xhci_hc_driver = { .description = "xhci-hcd", .product_desc = "xHCI Host Controller", @@ -5015,6 +5090,11 @@ .enable_usb3_lpm_timeout = xhci_enable_usb3_lpm_timeout, .disable_usb3_lpm_timeout = xhci_disable_usb3_lpm_timeout, .find_raw_port_number = xhci_find_raw_port_number, + .sec_event_ring_setup = xhci_sec_event_ring_setup, + .sec_event_ring_cleanup = xhci_sec_event_ring_cleanup, + .get_sec_event_ring_dma_addr = xhci_get_sec_event_ring_dma_addr, + .get_xfer_ring_dma_addr = xhci_get_xfer_ring_dma_addr, + .get_core_id = xhci_get_core_id, }; void xhci_init_driver(struct hc_driver *drv, diff -ruw linux-4.4.115/drivers/usb/host/xhci-dbg.c linux-4.4.115-fbx/drivers/usb/host/xhci-dbg.c --- linux-4.4.115/drivers/usb/host/xhci-dbg.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/usb/host/xhci-dbg.c 2019-01-22 16:16:27.343281180 +0100 @@ -30,10 +30,10 @@ { u32 temp; - xhci_dbg(xhci, "// xHCI capability registers at %p:\n", + xhci_dbg(xhci, "// xHCI capability registers at %pK:\n", xhci->cap_regs); temp = readl(&xhci->cap_regs->hc_capbase); - xhci_dbg(xhci, "// @%p = 0x%x (CAPLENGTH AND HCIVERSION)\n", + xhci_dbg(xhci, "// @%pK = 0x%x (CAPLENGTH AND HCIVERSION)\n", &xhci->cap_regs->hc_capbase, temp); xhci_dbg(xhci, "// CAPLENGTH: 0x%x\n", (unsigned int) HC_LENGTH(temp)); @@ -42,17 +42,17 @@ (unsigned int) HC_VERSION(temp)); #endif - xhci_dbg(xhci, "// xHCI operational registers at %p:\n", xhci->op_regs); + xhci_dbg(xhci, "// xHCI operational registers at %pK:\n", xhci->op_regs); temp = readl(&xhci->cap_regs->run_regs_off); - xhci_dbg(xhci, "// @%p = 0x%x RTSOFF\n", + xhci_dbg(xhci, "// @%pK = 0x%x RTSOFF\n", &xhci->cap_regs->run_regs_off, (unsigned int) temp & RTSOFF_MASK); - xhci_dbg(xhci, "// xHCI runtime registers at %p:\n", xhci->run_regs); + xhci_dbg(xhci, "// xHCI runtime registers at %pK:\n", xhci->run_regs); temp = readl(&xhci->cap_regs->db_off); - xhci_dbg(xhci, "// @%p = 0x%x DBOFF\n", &xhci->cap_regs->db_off, temp); - xhci_dbg(xhci, "// Doorbell array at %p:\n", xhci->dba); + xhci_dbg(xhci, "// @%pK = 0x%x DBOFF\n", &xhci->cap_regs->db_off, temp); + xhci_dbg(xhci, "// Doorbell array at %pK:\n", xhci->dba); } static void xhci_print_cap_regs(struct xhci_hcd *xhci) @@ -60,7 +60,7 @@ u32 temp; u32 hci_version; - xhci_dbg(xhci, "xHCI capability registers at %p:\n", xhci->cap_regs); + xhci_dbg(xhci, "xHCI capability registers at %pK:\n", xhci->cap_regs); temp = readl(&xhci->cap_regs->hc_capbase); hci_version = HC_VERSION(temp); @@ -157,7 +157,7 @@ static void xhci_print_op_regs(struct xhci_hcd *xhci) { - xhci_dbg(xhci, "xHCI operational registers at %p:\n", xhci->op_regs); + xhci_dbg(xhci, "xHCI operational registers at %pK:\n", xhci->op_regs); xhci_print_command_reg(xhci); xhci_print_status(xhci); } @@ -178,7 +178,7 @@ addr = &xhci->op_regs->port_status_base; for (i = 0; i < ports; i++) { for (j = 0; j < NUM_PORT_REGS; ++j) { - xhci_dbg(xhci, "%p port %s reg = 0x%x\n", + xhci_dbg(xhci, "%pK port %s reg = 0x%x\n", addr, names[j], (unsigned int) readl(addr)); addr++; @@ -198,35 +198,35 @@ if (temp == XHCI_INIT_VALUE) return; - xhci_dbg(xhci, " %p: ir_set[%i]\n", ir_set, set_num); + xhci_dbg(xhci, " %pK: ir_set[%i]\n", ir_set, set_num); - xhci_dbg(xhci, " %p: ir_set.pending = 0x%x\n", addr, + xhci_dbg(xhci, " %pK: ir_set.pending = 0x%x\n", addr, (unsigned int)temp); addr = &ir_set->irq_control; temp = readl(addr); - xhci_dbg(xhci, " %p: ir_set.control = 0x%x\n", addr, + xhci_dbg(xhci, " %pK: ir_set.control = 0x%x\n", addr, (unsigned int)temp); addr = &ir_set->erst_size; temp = readl(addr); - xhci_dbg(xhci, " %p: ir_set.erst_size = 0x%x\n", addr, + xhci_dbg(xhci, " %pK: ir_set.erst_size = 0x%x\n", addr, (unsigned int)temp); addr = &ir_set->rsvd; temp = readl(addr); if (temp != XHCI_INIT_VALUE) - xhci_dbg(xhci, " WARN: %p: ir_set.rsvd = 0x%x\n", + xhci_dbg(xhci, " WARN: %pK: ir_set.rsvd = 0x%x\n", addr, (unsigned int)temp); addr = &ir_set->erst_base; temp_64 = xhci_read_64(xhci, addr); - xhci_dbg(xhci, " %p: ir_set.erst_base = @%08llx\n", + xhci_dbg(xhci, " %pK: ir_set.erst_base = @%08llx\n", addr, temp_64); addr = &ir_set->erst_dequeue; temp_64 = xhci_read_64(xhci, addr); - xhci_dbg(xhci, " %p: ir_set.erst_dequeue = @%08llx\n", + xhci_dbg(xhci, " %pK: ir_set.erst_dequeue = @%08llx\n", addr, temp_64); } @@ -235,15 +235,15 @@ u32 temp; int i; - xhci_dbg(xhci, "xHCI runtime registers at %p:\n", xhci->run_regs); + xhci_dbg(xhci, "xHCI runtime registers at %pK:\n", xhci->run_regs); temp = readl(&xhci->run_regs->microframe_index); - xhci_dbg(xhci, " %p: Microframe index = 0x%x\n", + xhci_dbg(xhci, " %pK: Microframe index = 0x%x\n", &xhci->run_regs->microframe_index, (unsigned int) temp); for (i = 0; i < 7; ++i) { temp = readl(&xhci->run_regs->rsvd[i]); if (temp != XHCI_INIT_VALUE) - xhci_dbg(xhci, " WARN: %p: Rsvd[%i] = 0x%x\n", + xhci_dbg(xhci, " WARN: %pK: Rsvd[%i] = 0x%x\n", &xhci->run_regs->rsvd[i], i, (unsigned int) temp); } @@ -345,13 +345,13 @@ void xhci_dbg_ring_ptrs(struct xhci_hcd *xhci, struct xhci_ring *ring) { - xhci_dbg(xhci, "Ring deq = %p (virt), 0x%llx (dma)\n", + xhci_dbg(xhci, "Ring deq = %pK (virt), 0x%llx (dma)\n", ring->dequeue, (unsigned long long)xhci_trb_virt_to_dma(ring->deq_seg, ring->dequeue)); xhci_dbg(xhci, "Ring deq updated %u times\n", ring->deq_updates); - xhci_dbg(xhci, "Ring enq = %p (virt), 0x%llx (dma)\n", + xhci_dbg(xhci, "Ring enq = %pK (virt), 0x%llx (dma)\n", ring->enqueue, (unsigned long long)xhci_trb_virt_to_dma(ring->enq_seg, ring->enqueue)); @@ -441,7 +441,7 @@ { int i; for (i = 0; i < 4; ++i) { - xhci_dbg(xhci, "@%p (virt) @%08llx " + xhci_dbg(xhci, "@%pK (virt) @%08llx " "(dma) %#08llx - rsvd64[%d]\n", &ctx[4 + i], (unsigned long long)dma, ctx[4 + i], i); @@ -480,24 +480,24 @@ int csz = HCC_64BYTE_CONTEXT(xhci->hcc_params); xhci_dbg(xhci, "Slot Context:\n"); - xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08x - dev_info\n", + xhci_dbg(xhci, "@%pK (virt) @%08llx (dma) %#08x - dev_info\n", &slot_ctx->dev_info, (unsigned long long)dma, slot_ctx->dev_info); dma += field_size; - xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08x - dev_info2\n", + xhci_dbg(xhci, "@%pK (virt) @%08llx (dma) %#08x - dev_info2\n", &slot_ctx->dev_info2, (unsigned long long)dma, slot_ctx->dev_info2); dma += field_size; - xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08x - tt_info\n", + xhci_dbg(xhci, "@%pK (virt) @%08llx (dma) %#08x - tt_info\n", &slot_ctx->tt_info, (unsigned long long)dma, slot_ctx->tt_info); dma += field_size; - xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08x - dev_state\n", + xhci_dbg(xhci, "@%pK (virt) @%08llx (dma) %#08x - dev_state\n", &slot_ctx->dev_state, (unsigned long long)dma, slot_ctx->dev_state); dma += field_size; for (i = 0; i < 4; ++i) { - xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08x - rsvd[%d]\n", + xhci_dbg(xhci, "@%pK (virt) @%08llx (dma) %#08x - rsvd[%d]\n", &slot_ctx->reserved[i], (unsigned long long)dma, slot_ctx->reserved[i], i); dma += field_size; @@ -528,24 +528,24 @@ xhci_dbg(xhci, "%s Endpoint %02d Context (ep_index %02d):\n", usb_endpoint_out(epaddr) ? "OUT" : "IN", epaddr & USB_ENDPOINT_NUMBER_MASK, i); - xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08x - ep_info\n", + xhci_dbg(xhci, "@%pK (virt) @%08llx (dma) %#08x - ep_info\n", &ep_ctx->ep_info, (unsigned long long)dma, ep_ctx->ep_info); dma += field_size; - xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08x - ep_info2\n", + xhci_dbg(xhci, "@%pK (virt) @%08llx (dma) %#08x - ep_info2\n", &ep_ctx->ep_info2, (unsigned long long)dma, ep_ctx->ep_info2); dma += field_size; - xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08llx - deq\n", + xhci_dbg(xhci, "@%pK (virt) @%08llx (dma) %#08llx - deq\n", &ep_ctx->deq, (unsigned long long)dma, ep_ctx->deq); dma += 2*field_size; - xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08x - tx_info\n", + xhci_dbg(xhci, "@%pK (virt) @%08llx (dma) %#08x - tx_info\n", &ep_ctx->tx_info, (unsigned long long)dma, ep_ctx->tx_info); dma += field_size; for (j = 0; j < 3; ++j) { - xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08x - rsvd[%d]\n", + xhci_dbg(xhci, "@%pK (virt) @%08llx (dma) %#08x - rsvd[%d]\n", &ep_ctx->reserved[j], (unsigned long long)dma, ep_ctx->reserved[j], j); @@ -575,16 +575,16 @@ return; } - xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08x - drop flags\n", + xhci_dbg(xhci, "@%pK (virt) @%08llx (dma) %#08x - drop flags\n", &ctrl_ctx->drop_flags, (unsigned long long)dma, ctrl_ctx->drop_flags); dma += field_size; - xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08x - add flags\n", + xhci_dbg(xhci, "@%pK (virt) @%08llx (dma) %#08x - add flags\n", &ctrl_ctx->add_flags, (unsigned long long)dma, ctrl_ctx->add_flags); dma += field_size; for (i = 0; i < 6; ++i) { - xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08x - rsvd2[%d]\n", + xhci_dbg(xhci, "@%pK (virt) @%08llx (dma) %#08x - rsvd2[%d]\n", &ctrl_ctx->rsvd2[i], (unsigned long long)dma, ctrl_ctx->rsvd2[i], i); dma += field_size; diff -ruw linux-4.4.115/drivers/usb/host/xhci.h linux-4.4.115-fbx/drivers/usb/host/xhci.h --- linux-4.4.115/drivers/usb/host/xhci.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/usb/host/xhci.h 2019-10-29 09:26:25.033216781 +0100 @@ -1516,6 +1516,11 @@ /* Our HCD's current interrupter register set */ struct xhci_intr_reg __iomem *ir_set; + /* secondary interrupter */ + struct xhci_intr_reg __iomem **sec_ir_set; + + int core_id; + /* Cached register copies of read-only HC data */ __u32 hcs_params1; __u32 hcs_params2; @@ -1557,6 +1562,11 @@ struct xhci_command *current_cmd; struct xhci_ring *event_ring; struct xhci_erst erst; + + /* secondary event ring and erst */ + struct xhci_ring **sec_event_ring; + struct xhci_erst *sec_erst; + /* Scratchpad */ struct xhci_scratchpad *scratchpad; /* Store LPM test failed devices' information */ @@ -1659,6 +1669,7 @@ /* Compliance Mode Recovery Data */ struct timer_list comp_mode_recovery_timer; u32 port_status_u0; + bool suspended; /* Compliance Mode Timer Triggered every 2 seconds */ #define COMP_MODE_RCVRY_MSECS 2000 }; @@ -1816,6 +1827,8 @@ void xhci_urb_free_priv(struct urb_priv *urb_priv); void xhci_free_command(struct xhci_hcd *xhci, struct xhci_command *command); +int xhci_sec_event_ring_setup(struct usb_hcd *hcd, unsigned intr_num); +int xhci_sec_event_ring_cleanup(struct usb_hcd *hcd, unsigned intr_num); /* xHCI host controller glue */ typedef void (*xhci_get_quirks_t)(struct device *, struct xhci_hcd *); @@ -1935,6 +1948,7 @@ char *buf, u16 wLength); int xhci_hub_status_data(struct usb_hcd *hcd, char *buf); int xhci_find_raw_port_number(struct usb_hcd *hcd, int port1); +int xhci_get_core_id(struct usb_hcd *hcd); #ifdef CONFIG_PM int xhci_bus_suspend(struct usb_hcd *hcd); @@ -1954,4 +1968,8 @@ struct xhci_slot_ctx *xhci_get_slot_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx); struct xhci_ep_ctx *xhci_get_ep_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx, unsigned int ep_index); +/* EHSET */ +int xhci_submit_single_step_set_feature(struct usb_hcd *hcd, struct urb *urb, + int is_setup); + #endif /* __LINUX_XHCI_HCD_H */ diff -ruw linux-4.4.115/drivers/usb/host/xhci-hub.c linux-4.4.115-fbx/drivers/usb/host/xhci-hub.c --- linux-4.4.115/drivers/usb/host/xhci-hub.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/usb/host/xhci-hub.c 2019-10-29 09:26:25.025216703 +0100 @@ -20,7 +20,7 @@ * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */ - +#include #include #include @@ -376,10 +376,6 @@ int i; ret = 0; - virt_dev = xhci->devs[slot_id]; - if (!virt_dev) - return -ENODEV; - cmd = xhci_alloc_command(xhci, false, true, GFP_NOIO); if (!cmd) { xhci_dbg(xhci, "Couldn't allocate command structure.\n"); @@ -387,6 +383,13 @@ } spin_lock_irqsave(&xhci->lock, flags); + virt_dev = xhci->devs[slot_id]; + if (!virt_dev) { + spin_unlock_irqrestore(&xhci->lock, flags); + xhci_free_command(xhci, cmd); + return -ENODEV; + } + for (i = LAST_EP_INDEX; i > 0; i--) { if (virt_dev->eps[i].ring && virt_dev->eps[i].ring->dequeue) { struct xhci_command *command; @@ -878,6 +881,151 @@ return status; } +static void xhci_single_step_completion(struct urb *urb) +{ + struct completion *done = urb->context; + + complete(done); +} + +/* + * Allocate a URB and initialize the various fields of it. + * This API is used by the single_step_set_feature test of + * EHSET where IN packet of the GetDescriptor request is + * sent 15secs after the SETUP packet. + * Return NULL if failed. + */ +static struct urb *xhci_request_single_step_set_feature_urb( + struct usb_device *udev, + void *dr, + void *buf, + struct completion *done) +{ + struct urb *urb; + struct usb_hcd *hcd = bus_to_hcd(udev->bus); + struct usb_host_endpoint *ep; + + urb = usb_alloc_urb(0, GFP_KERNEL); + if (!urb) + return NULL; + + urb->pipe = usb_rcvctrlpipe(udev, 0); + ep = udev->ep_in[usb_pipeendpoint(urb->pipe)]; + if (!ep) { + usb_free_urb(urb); + return NULL; + } + + /* + * Initialize the various URB fields as these are used by the HCD + * driver to queue it and as well as when completion happens. + */ + urb->ep = ep; + urb->dev = udev; + urb->setup_packet = dr; + urb->transfer_buffer = buf; + urb->transfer_buffer_length = USB_DT_DEVICE_SIZE; + urb->complete = xhci_single_step_completion; + urb->status = -EINPROGRESS; + urb->actual_length = 0; + urb->transfer_flags = URB_DIR_IN; + usb_get_urb(urb); + atomic_inc(&urb->use_count); + atomic_inc(&urb->dev->urbnum); + usb_hcd_map_urb_for_dma(hcd, urb, GFP_KERNEL); + urb->context = done; + return urb; +} + +/* + * This function implements the USB_PORT_FEAT_TEST handling of the + * SINGLE_STEP_SET_FEATURE test mode as defined in the Embedded + * High-Speed Electrical Test (EHSET) specification. This simply + * issues a GetDescriptor control transfer, with an inserted 15-second + * delay after the end of the SETUP stage and before the IN token of + * the DATA stage is set. The idea is that this gives the test operator + * enough time to configure the oscilloscope to perform a measurement + * of the response time between the DATA and ACK packets that follow. + */ +static int xhci_ehset_single_step_set_feature(struct usb_hcd *hcd, int port) +{ + int retval; + struct usb_ctrlrequest *dr; + struct urb *urb; + struct usb_device *udev; + struct xhci_hcd *xhci = hcd_to_xhci(hcd); + struct usb_device_descriptor *buf; + unsigned long flags; + DECLARE_COMPLETION_ONSTACK(done); + + /* Obtain udev of the rhub's child port */ + udev = usb_hub_find_child(hcd->self.root_hub, port); + if (!udev) { + xhci_err(xhci, "No device attached to the RootHub\n"); + return -ENODEV; + } + buf = kmalloc(USB_DT_DEVICE_SIZE, GFP_KERNEL); + if (!buf) + return -ENOMEM; + + dr = kmalloc(sizeof(struct usb_ctrlrequest), GFP_KERNEL); + if (!dr) { + kfree(buf); + return -ENOMEM; + } + + /* Fill Setup packet for GetDescriptor */ + dr->bRequestType = USB_DIR_IN; + dr->bRequest = USB_REQ_GET_DESCRIPTOR; + dr->wValue = cpu_to_le16(USB_DT_DEVICE << 8); + dr->wIndex = 0; + dr->wLength = cpu_to_le16(USB_DT_DEVICE_SIZE); + urb = xhci_request_single_step_set_feature_urb(udev, dr, buf, &done); + if (!urb) { + retval = -ENOMEM; + goto cleanup; + } + + /* Now complete just the SETUP stage */ + spin_lock_irqsave(&xhci->lock, flags); + retval = xhci_submit_single_step_set_feature(hcd, urb, 1); + spin_unlock_irqrestore(&xhci->lock, flags); + if (retval) + goto out1; + + if (!wait_for_completion_timeout(&done, msecs_to_jiffies(2000))) { + usb_kill_urb(urb); + retval = -ETIMEDOUT; + xhci_err(xhci, "%s SETUP stage timed out on ep0\n", __func__); + goto out1; + } + + /* Sleep for 15 seconds; HC will send SOFs during this period */ + msleep(15 * 1000); + + /* Complete remaining DATA and status stages. Re-use same URB */ + urb->status = -EINPROGRESS; + usb_get_urb(urb); + atomic_inc(&urb->use_count); + atomic_inc(&urb->dev->urbnum); + + spin_lock_irqsave(&xhci->lock, flags); + retval = xhci_submit_single_step_set_feature(hcd, urb, 0); + spin_unlock_irqrestore(&xhci->lock, flags); + if (!retval && !wait_for_completion_timeout(&done, + msecs_to_jiffies(2000))) { + usb_kill_urb(urb); + retval = -ETIMEDOUT; + xhci_err(xhci, "%s IN stage timed out on ep0\n", __func__); + } +out1: + usb_free_urb(urb); +cleanup: + kfree(dr); + kfree(buf); + return retval; +} + int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue, u16 wIndex, char *buf, u16 wLength) { @@ -892,6 +1040,7 @@ u16 link_state = 0; u16 wake_mask = 0; u16 timeout = 0; + u16 test_mode = 0; max_ports = xhci_get_ports(hcd, &port_array); bus_state = &xhci->bus_state[hcd_index(hcd)]; @@ -965,8 +1114,8 @@ link_state = (wIndex & 0xff00) >> 3; if (wValue == USB_PORT_FEAT_REMOTE_WAKE_MASK) wake_mask = wIndex & 0xff00; - /* The MSB of wIndex is the U1/U2 timeout */ - timeout = (wIndex & 0xff00) >> 8; + /* The MSB of wIndex is the U1/U2 timeout OR TEST mode*/ + test_mode = timeout = (wIndex & 0xff00) >> 8; wIndex &= 0xff; if (!wIndex || wIndex > max_ports) goto error; @@ -1140,6 +1289,32 @@ temp |= PORT_U2_TIMEOUT(timeout); writel(temp, port_array[wIndex] + PORTPMSC); break; + case USB_PORT_FEAT_TEST: + slot_id = xhci_find_slot_id_by_port(hcd, xhci, + wIndex + 1); + if (test_mode && test_mode <= 5) { + /* unlock to execute stop endpoint commands */ + spin_unlock_irqrestore(&xhci->lock, flags); + xhci_stop_device(xhci, slot_id, 1); + spin_lock_irqsave(&xhci->lock, flags); + xhci_halt(xhci); + + temp = readl_relaxed(port_array[wIndex] + + PORTPMSC); + temp |= test_mode << 28; + writel_relaxed(temp, port_array[wIndex] + + PORTPMSC); + /* to make sure above write goes through */ + mb(); + } else if (test_mode == 6) { + spin_unlock_irqrestore(&xhci->lock, flags); + retval = xhci_ehset_single_step_set_feature(hcd, + wIndex); + spin_lock_irqsave(&xhci->lock, flags); + } else { + goto error; + } + break; default: goto error; } @@ -1172,7 +1347,7 @@ xhci_set_link_state(xhci, port_array, wIndex, XDEV_RESUME); spin_unlock_irqrestore(&xhci->lock, flags); - msleep(USB_RESUME_TIMEOUT); + usleep_range(21000, 21500); spin_lock_irqsave(&xhci->lock, flags); xhci_set_link_state(xhci, port_array, wIndex, XDEV_U0); @@ -1453,7 +1628,7 @@ if (need_usb2_u3_exit) { spin_unlock_irqrestore(&xhci->lock, flags); - msleep(USB_RESUME_TIMEOUT); + usleep_range(21000, 21500); spin_lock_irqsave(&xhci->lock, flags); } diff -ruw linux-4.4.115/drivers/usb/host/xhci-mem.c linux-4.4.115-fbx/drivers/usb/host/xhci-mem.c --- linux-4.4.115/drivers/usb/host/xhci-mem.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/usb/host/xhci-mem.c 2019-10-29 09:26:25.029216742 +0100 @@ -1062,7 +1062,7 @@ /* Point to output device context in dcbaa. */ xhci->dcbaa->dev_context_ptrs[slot_id] = cpu_to_le64(dev->out_ctx->dma); - xhci_dbg(xhci, "Set slot id %d dcbaa entry %p to 0x%llx\n", + xhci_dbg(xhci, "Set slot id %d dcbaa entry %pK to 0x%llx\n", slot_id, &xhci->dcbaa->dev_context_ptrs[slot_id], le64_to_cpu(xhci->dcbaa->dev_context_ptrs[slot_id])); @@ -1233,7 +1233,7 @@ if (udev->tt->multi) slot_ctx->dev_info |= cpu_to_le32(DEV_MTT); } - xhci_dbg(xhci, "udev->tt = %p\n", udev->tt); + xhci_dbg(xhci, "udev->tt = %pK\n", udev->tt); xhci_dbg(xhci, "udev->ttport = 0x%x\n", udev->ttport); /* Step 4 - ring already allocated */ @@ -1525,6 +1525,8 @@ } break; case USB_SPEED_FULL: + if (usb_endpoint_xfer_bulk(&ep->desc) && max_packet < 8) + max_packet = 8; case USB_SPEED_LOW: break; default: @@ -1838,25 +1840,151 @@ kfree(command); } -void xhci_mem_cleanup(struct xhci_hcd *xhci) +void xhci_handle_sec_intr_events(struct xhci_hcd *xhci, int intr_num) +{ + union xhci_trb *erdp_trb, *current_trb; + struct xhci_segment *seg; + u64 erdp_reg; + u32 iman_reg; + dma_addr_t deq; + unsigned long segment_offset; + + /* disable irq, ack pending interrupt and ack all pending events */ + + iman_reg = + readl_relaxed(&xhci->sec_ir_set[intr_num]->irq_pending); + iman_reg &= ~IMAN_IE; + writel_relaxed(iman_reg, + &xhci->sec_ir_set[intr_num]->irq_pending); + iman_reg = + readl_relaxed(&xhci->sec_ir_set[intr_num]->irq_pending); + if (iman_reg & IMAN_IP) + writel_relaxed(iman_reg, + &xhci->sec_ir_set[intr_num]->irq_pending); + + /* last acked event trb is in erdp reg */ + erdp_reg = + xhci_read_64(xhci, &xhci->sec_ir_set[intr_num]->erst_dequeue); + deq = (dma_addr_t)(erdp_reg & ~ERST_PTR_MASK); + if (!deq) { + pr_debug("%s: event ring handling not required\n", __func__); + return; + } + + seg = xhci->sec_event_ring[intr_num]->first_seg; + segment_offset = deq - seg->dma; + + /* find out virtual address of the last acked event trb */ + erdp_trb = current_trb = &seg->trbs[0] + + (segment_offset/sizeof(*current_trb)); + + /* read cycle state of the last acked trb to find out CCS */ + xhci->sec_event_ring[intr_num]->cycle_state = + (current_trb->event_cmd.flags & TRB_CYCLE); + + while (1) { + /* last trb of the event ring: toggle cycle state */ + if (current_trb == &seg->trbs[TRBS_PER_SEGMENT - 1]) { + xhci->sec_event_ring[intr_num]->cycle_state ^= 1; + current_trb = &seg->trbs[0]; + } else { + current_trb++; + } + + /* cycle state transition */ + if ((le32_to_cpu(current_trb->event_cmd.flags) & TRB_CYCLE) != + xhci->sec_event_ring[intr_num]->cycle_state) + break; + } + + if (erdp_trb != current_trb) { + deq = + xhci_trb_virt_to_dma(xhci->sec_event_ring[intr_num]->deq_seg, + current_trb); + if (deq == 0) + xhci_warn(xhci, + "WARN ivalid SW event ring dequeue ptr.\n"); + /* Update HC event ring dequeue pointer */ + erdp_reg &= ERST_PTR_MASK; + erdp_reg |= ((u64) deq & (u64) ~ERST_PTR_MASK); + } + + /* Clear the event handler busy flag (RW1C); event ring is empty. */ + erdp_reg |= ERST_EHB; + xhci_write_64(xhci, erdp_reg, + &xhci->sec_ir_set[intr_num]->erst_dequeue); +} + +int xhci_sec_event_ring_cleanup(struct usb_hcd *hcd, unsigned intr_num) { + int size; + struct xhci_hcd *xhci = hcd_to_xhci(hcd); struct device *dev = xhci_to_hcd(xhci)->self.controller; + + if (intr_num >= xhci->max_interrupters) { + xhci_err(xhci, "invalid secondary interrupter num %d\n", + intr_num); + return -EINVAL; + } + + size = + sizeof(struct xhci_erst_entry)*(xhci->sec_erst[intr_num].num_entries); + if (xhci->sec_erst[intr_num].entries) { + xhci_handle_sec_intr_events(xhci, intr_num); + dma_free_coherent(dev, size, xhci->sec_erst[intr_num].entries, + xhci->sec_erst[intr_num].erst_dma_addr); + xhci->sec_erst[intr_num].entries = NULL; + } + xhci_dbg_trace(xhci, trace_xhci_dbg_init, "Freed SEC ERST#%d", + intr_num); + if (xhci->sec_event_ring[intr_num]) + xhci_ring_free(xhci, xhci->sec_event_ring[intr_num]); + + xhci->sec_event_ring[intr_num] = NULL; + xhci_dbg_trace(xhci, trace_xhci_dbg_init, + "Freed sec event ring"); + + return 0; +} + +void xhci_event_ring_cleanup(struct xhci_hcd *xhci) +{ int size; - int i, j, num_ports; + unsigned int i; + struct device *dev = xhci_to_hcd(xhci)->self.controller; - cancel_delayed_work_sync(&xhci->cmd_timer); + /* sec event ring clean up */ + for (i = 1; i < xhci->max_interrupters; i++) + xhci_sec_event_ring_cleanup(xhci_to_hcd(xhci), i); + + kfree(xhci->sec_ir_set); + xhci->sec_ir_set = NULL; + kfree(xhci->sec_erst); + xhci->sec_erst = NULL; + kfree(xhci->sec_event_ring); + xhci->sec_event_ring = NULL; - /* Free the Event Ring Segment Table and the actual Event Ring */ + /* primary event ring clean up */ size = sizeof(struct xhci_erst_entry)*(xhci->erst.num_entries); if (xhci->erst.entries) dma_free_coherent(dev, size, xhci->erst.entries, xhci->erst.erst_dma_addr); xhci->erst.entries = NULL; - xhci_dbg_trace(xhci, trace_xhci_dbg_init, "Freed ERST"); + xhci_dbg_trace(xhci, trace_xhci_dbg_init, "Freed primary ERST"); if (xhci->event_ring) xhci_ring_free(xhci, xhci->event_ring); xhci->event_ring = NULL; - xhci_dbg_trace(xhci, trace_xhci_dbg_init, "Freed event ring"); + xhci_dbg_trace(xhci, trace_xhci_dbg_init, "Freed priamry event ring"); +} + +void xhci_mem_cleanup(struct xhci_hcd *xhci) +{ + struct device *dev = xhci_to_hcd(xhci)->self.controller; + int i, j, num_ports; + + cancel_delayed_work_sync(&xhci->cmd_timer); + + xhci_event_ring_cleanup(xhci); if (xhci->lpm_command) xhci_free_command(xhci, xhci->lpm_command); @@ -1958,15 +2086,15 @@ if (seg != result_seg) { xhci_warn(xhci, "WARN: %s TRB math test %d failed!\n", test_name, test_number); - xhci_warn(xhci, "Tested TRB math w/ seg %p and " + xhci_warn(xhci, "Tested TRB math w/ seg %pK and " "input DMA 0x%llx\n", input_seg, (unsigned long long) input_dma); - xhci_warn(xhci, "starting TRB %p (0x%llx DMA), " - "ending TRB %p (0x%llx DMA)\n", + xhci_warn(xhci, "starting TRB %pK (0x%llx DMA), " + "ending TRB %pK (0x%llx DMA)\n", start_trb, start_dma, end_trb, end_dma); - xhci_warn(xhci, "Expected seg %p, got seg %p\n", + xhci_warn(xhci, "Expected seg %pK, got seg %pK\n", result_seg, seg); trb_in_td(xhci, input_seg, start_trb, end_trb, input_dma, true); @@ -2097,30 +2225,6 @@ return 0; } -static void xhci_set_hc_event_deq(struct xhci_hcd *xhci) -{ - u64 temp; - dma_addr_t deq; - - deq = xhci_trb_virt_to_dma(xhci->event_ring->deq_seg, - xhci->event_ring->dequeue); - if (deq == 0 && !in_interrupt()) - xhci_warn(xhci, "WARN something wrong with SW event ring " - "dequeue ptr.\n"); - /* Update HC event ring dequeue pointer */ - temp = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue); - temp &= ERST_PTR_MASK; - /* Don't clear the EHB bit (which is RW1C) because - * there might be more events to service. - */ - temp &= ~ERST_EHB; - xhci_dbg_trace(xhci, trace_xhci_dbg_init, - "// Write event ring dequeue pointer, " - "preserving EHB bit"); - xhci_write_64(xhci, ((u64) deq & (u64) ~ERST_PTR_MASK) | temp, - &xhci->ir_set->erst_dequeue); -} - static void xhci_add_in_port(struct xhci_hcd *xhci, unsigned int num_ports, __le32 __iomem *addr, u8 major_revision, int max_caps) { @@ -2136,7 +2240,7 @@ rhub = &xhci->usb2_rhub; } else { xhci_warn(xhci, "Ignoring unknown port speed, " - "Ext Cap %p, revision = 0x%x\n", + "Ext Cap %pK, revision = 0x%x\n", addr, major_revision); /* Ignoring port protocol we can't understand. FIXME */ return; @@ -2149,7 +2253,7 @@ port_offset = XHCI_EXT_PORT_OFF(temp); port_count = XHCI_EXT_PORT_COUNT(temp); xhci_dbg_trace(xhci, trace_xhci_dbg_init, - "Ext Cap %p, port offset = %u, " + "Ext Cap %pK, port offset = %u, " "count = %u, revision = 0x%x", addr, port_offset, port_count, major_revision); /* Port count includes the current port offset */ @@ -2211,7 +2315,7 @@ for (i = port_offset; i < (port_offset + port_count); i++) { /* Duplicate entry. Ignore the port if the revisions differ. */ if (xhci->port_array[i] != 0) { - xhci_warn(xhci, "Duplicate port entry, Ext Cap %p," + xhci_warn(xhci, "Duplicate port entry, Ext Cap %pK," " port %u\n", addr, i); xhci_warn(xhci, "Port was marked as USB %u, " "duplicated as USB %u\n", @@ -2367,7 +2471,7 @@ NUM_PORT_REGS*i; xhci_dbg_trace(xhci, trace_xhci_dbg_init, "USB 2.0 port at index %u, " - "addr = %p", i, + "addr = %pK", i, xhci->usb2_ports[port_index]); port_index++; if (port_index == xhci->num_usb2_ports) @@ -2388,7 +2492,7 @@ NUM_PORT_REGS*i; xhci_dbg_trace(xhci, trace_xhci_dbg_init, "USB 3.0 port at index %u, " - "addr = %p", i, + "addr = %pK", i, xhci->usb3_ports[port_index]); port_index++; if (port_index == xhci->num_usb3_ports) @@ -2398,13 +2502,184 @@ return 0; } +int xhci_event_ring_setup(struct xhci_hcd *xhci, struct xhci_ring **er, + struct xhci_intr_reg __iomem *ir_set, struct xhci_erst *erst, + unsigned int intr_num, gfp_t flags) +{ + dma_addr_t dma, deq; + u64 val_64; + unsigned int val; + struct xhci_segment *seg; + struct device *dev = xhci_to_hcd(xhci)->self.controller; + + *er = xhci_ring_alloc(xhci, ERST_NUM_SEGS, 1, + TYPE_EVENT, flags); + if (!*er) + return -ENOMEM; + + erst->entries = dma_alloc_coherent(dev, + sizeof(struct xhci_erst_entry) * ERST_NUM_SEGS, &dma, + flags); + if (!erst->entries) { + xhci_ring_free(xhci, *er); + return -ENOMEM; + } + + xhci_dbg_trace(xhci, trace_xhci_dbg_init, + "intr# %d: Allocated event ring segment table at 0x%llx", + intr_num, (unsigned long long)dma); + + memset(erst->entries, 0, sizeof(struct xhci_erst_entry)*ERST_NUM_SEGS); + erst->num_entries = ERST_NUM_SEGS; + erst->erst_dma_addr = dma; + xhci_dbg_trace(xhci, trace_xhci_dbg_init, + "intr# %d: num segs = %i, virt addr = %pK, dma addr = 0x%llx", + intr_num, + erst->num_entries, + erst->entries, + (unsigned long long)erst->erst_dma_addr); + + /* set ring base address and size for each segment table entry */ + for (val = 0, seg = (*er)->first_seg; val < ERST_NUM_SEGS; val++) { + struct xhci_erst_entry *entry = &erst->entries[val]; + + entry->seg_addr = cpu_to_le64(seg->dma); + entry->seg_size = cpu_to_le32(TRBS_PER_SEGMENT); + entry->rsvd = 0; + seg = seg->next; + } + + /* set ERST count with the number of entries in the segment table */ + val = readl_relaxed(&ir_set->erst_size); + val &= ERST_SIZE_MASK; + val |= ERST_NUM_SEGS; + xhci_dbg_trace(xhci, trace_xhci_dbg_init, + "Write ERST size = %i to ir_set %d (some bits preserved)", val, + intr_num); + writel_relaxed(val, &ir_set->erst_size); + + xhci_dbg_trace(xhci, trace_xhci_dbg_init, + "intr# %d: Set ERST entries to point to event ring.", + intr_num); + /* set the segment table base address */ + xhci_dbg_trace(xhci, trace_xhci_dbg_init, + "Set ERST base address for ir_set %d = 0x%llx", + intr_num, + (unsigned long long)erst->erst_dma_addr); + val_64 = xhci_read_64(xhci, &ir_set->erst_base); + val_64 &= ERST_PTR_MASK; + val_64 |= (erst->erst_dma_addr & (u64) ~ERST_PTR_MASK); + xhci_write_64(xhci, val_64, &ir_set->erst_base); + + /* Set the event ring dequeue address */ + deq = xhci_trb_virt_to_dma((*er)->deq_seg, (*er)->dequeue); + if (deq == 0 && !in_interrupt()) + xhci_warn(xhci, + "intr# %d:WARN something wrong with SW event ring deq ptr.\n", + intr_num); + /* Update HC event ring dequeue pointer */ + val_64 = xhci_read_64(xhci, &ir_set->erst_dequeue); + val_64 &= ERST_PTR_MASK; + /* Don't clear the EHB bit (which is RW1C) because + * there might be more events to service. + */ + val_64 &= ~ERST_EHB; + xhci_dbg_trace(xhci, trace_xhci_dbg_init, + "intr# %d:Write event ring dequeue pointer, preserving EHB bit", + intr_num); + xhci_write_64(xhci, ((u64) deq & (u64) ~ERST_PTR_MASK) | val_64, + &ir_set->erst_dequeue); + xhci_dbg_trace(xhci, trace_xhci_dbg_init, + "Wrote ERST address to ir_set %d.", intr_num); + xhci_print_ir_set(xhci, intr_num); + + return 0; +} + +int xhci_sec_event_ring_setup(struct usb_hcd *hcd, unsigned intr_num) +{ + int ret; + struct xhci_hcd *xhci = hcd_to_xhci(hcd); + + if ((xhci->xhc_state & XHCI_STATE_HALTED) || !xhci->sec_ir_set + || !xhci->sec_event_ring || !xhci->sec_erst || + intr_num >= xhci->max_interrupters) { + xhci_err(xhci, + "%s:state %x ir_set %pK evt_ring %pK erst %pK intr# %d\n", + __func__, xhci->xhc_state, xhci->sec_ir_set, + xhci->sec_event_ring, xhci->sec_erst, intr_num); + return -EINVAL; + } + + if (xhci->sec_event_ring && xhci->sec_event_ring[intr_num] + && xhci->sec_event_ring[intr_num]->first_seg) + goto done; + + xhci->sec_ir_set[intr_num] = &xhci->run_regs->ir_set[intr_num]; + ret = xhci_event_ring_setup(xhci, + &xhci->sec_event_ring[intr_num], + xhci->sec_ir_set[intr_num], + &xhci->sec_erst[intr_num], + intr_num, GFP_KERNEL); + if (ret) { + xhci_err(xhci, "sec event ring setup failed inter#%d\n", + intr_num); + return ret; + } +done: + return 0; +} + +int xhci_event_ring_init(struct xhci_hcd *xhci, gfp_t flags) +{ + int ret = 0; + + /* primary + secondary */ + xhci->max_interrupters = HCS_MAX_INTRS(xhci->hcs_params1); + + xhci_dbg_trace(xhci, trace_xhci_dbg_init, + "// Allocating primary event ring"); + + /* Set ir_set to interrupt register set 0 */ + xhci->ir_set = &xhci->run_regs->ir_set[0]; + ret = xhci_event_ring_setup(xhci, &xhci->event_ring, xhci->ir_set, + &xhci->erst, 0, flags); + if (ret) { + xhci_err(xhci, "failed to setup primary event ring\n"); + goto fail; + } + + xhci_dbg_trace(xhci, trace_xhci_dbg_init, + "// Allocating sec event ring related pointers"); + + xhci->sec_ir_set = kcalloc(xhci->max_interrupters, + sizeof(*xhci->sec_ir_set), flags); + if (!xhci->sec_ir_set) { + ret = -ENOMEM; + goto fail; + } + + xhci->sec_event_ring = kcalloc(xhci->max_interrupters, + sizeof(*xhci->sec_event_ring), flags); + if (!xhci->sec_event_ring) { + ret = -ENOMEM; + goto fail; + } + + xhci->sec_erst = kcalloc(xhci->max_interrupters, + sizeof(*xhci->sec_erst), flags); + if (!xhci->sec_erst) + ret = -ENOMEM; +fail: + return ret; +} + int xhci_mem_init(struct xhci_hcd *xhci, gfp_t flags) { dma_addr_t dma; struct device *dev = xhci_to_hcd(xhci)->self.controller; unsigned int val, val2; u64 val_64; - struct xhci_segment *seg; u32 page_size, temp; int i; @@ -2457,7 +2732,7 @@ memset(xhci->dcbaa, 0, sizeof *(xhci->dcbaa)); xhci->dcbaa->dma = dma; xhci_dbg_trace(xhci, trace_xhci_dbg_init, - "// Device context base array address = 0x%llx (DMA), %p (virt)", + "// Device context base array address = 0x%llx (DMA), %pK (virt)", (unsigned long long)xhci->dcbaa->dma, xhci->dcbaa); xhci_write_64(xhci, dma, &xhci->op_regs->dcbaa_ptr); @@ -2498,7 +2773,7 @@ if (!xhci->cmd_ring) goto fail; xhci_dbg_trace(xhci, trace_xhci_dbg_init, - "Allocated command ring at %p", xhci->cmd_ring); + "Allocated command ring at %pK", xhci->cmd_ring); xhci_dbg_trace(xhci, trace_xhci_dbg_init, "First segment DMA is 0x%llx", (unsigned long long)xhci->cmd_ring->first_seg->dma); @@ -2530,73 +2805,16 @@ xhci->dba = (void __iomem *) xhci->cap_regs + val; xhci_dbg_regs(xhci); xhci_print_run_regs(xhci); - /* Set ir_set to interrupt register set 0 */ - xhci->ir_set = &xhci->run_regs->ir_set[0]; /* * Event ring setup: Allocate a normal ring, but also setup * the event ring segment table (ERST). Section 4.9.3. */ - xhci_dbg_trace(xhci, trace_xhci_dbg_init, "// Allocating event ring"); - xhci->event_ring = xhci_ring_alloc(xhci, ERST_NUM_SEGS, 1, TYPE_EVENT, - flags); - if (!xhci->event_ring) - goto fail; - if (xhci_check_trb_in_td_math(xhci) < 0) + if (xhci_event_ring_init(xhci, GFP_KERNEL)) goto fail; - xhci->erst.entries = dma_alloc_coherent(dev, - sizeof(struct xhci_erst_entry) * ERST_NUM_SEGS, &dma, - flags); - if (!xhci->erst.entries) + if (xhci_check_trb_in_td_math(xhci) < 0) goto fail; - xhci_dbg_trace(xhci, trace_xhci_dbg_init, - "// Allocated event ring segment table at 0x%llx", - (unsigned long long)dma); - - memset(xhci->erst.entries, 0, sizeof(struct xhci_erst_entry)*ERST_NUM_SEGS); - xhci->erst.num_entries = ERST_NUM_SEGS; - xhci->erst.erst_dma_addr = dma; - xhci_dbg_trace(xhci, trace_xhci_dbg_init, - "Set ERST to 0; private num segs = %i, virt addr = %p, dma addr = 0x%llx", - xhci->erst.num_entries, - xhci->erst.entries, - (unsigned long long)xhci->erst.erst_dma_addr); - - /* set ring base address and size for each segment table entry */ - for (val = 0, seg = xhci->event_ring->first_seg; val < ERST_NUM_SEGS; val++) { - struct xhci_erst_entry *entry = &xhci->erst.entries[val]; - entry->seg_addr = cpu_to_le64(seg->dma); - entry->seg_size = cpu_to_le32(TRBS_PER_SEGMENT); - entry->rsvd = 0; - seg = seg->next; - } - - /* set ERST count with the number of entries in the segment table */ - val = readl(&xhci->ir_set->erst_size); - val &= ERST_SIZE_MASK; - val |= ERST_NUM_SEGS; - xhci_dbg_trace(xhci, trace_xhci_dbg_init, - "// Write ERST size = %i to ir_set 0 (some bits preserved)", - val); - writel(val, &xhci->ir_set->erst_size); - - xhci_dbg_trace(xhci, trace_xhci_dbg_init, - "// Set ERST entries to point to event ring."); - /* set the segment table base address */ - xhci_dbg_trace(xhci, trace_xhci_dbg_init, - "// Set ERST base address for ir_set 0 = 0x%llx", - (unsigned long long)xhci->erst.erst_dma_addr); - val_64 = xhci_read_64(xhci, &xhci->ir_set->erst_base); - val_64 &= ERST_PTR_MASK; - val_64 |= (xhci->erst.erst_dma_addr & (u64) ~ERST_PTR_MASK); - xhci_write_64(xhci, val_64, &xhci->ir_set->erst_base); - - /* Set the event ring dequeue address */ - xhci_set_hc_event_deq(xhci); - xhci_dbg_trace(xhci, trace_xhci_dbg_init, - "Wrote ERST address to ir_set 0."); - xhci_print_ir_set(xhci, 0); /* * XXX: Might need to set the Interrupter Moderation Register to diff -ruw linux-4.4.115/drivers/usb/host/xhci-plat.c linux-4.4.115-fbx/drivers/usb/host/xhci-plat.c --- linux-4.4.115/drivers/usb/host/xhci-plat.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/usb/host/xhci-plat.c 2019-10-29 09:26:25.029216742 +0100 @@ -38,12 +38,19 @@ static void xhci_plat_quirks(struct device *dev, struct xhci_hcd *xhci) { + struct device_node *node = dev->of_node; + struct usb_xhci_pdata *pdata = dev_get_platdata(dev); + /* * As of now platform drivers don't provide MSI support so we ensure * here that the generic code does not try to make a pci_dev from our * dev struct in order to setup MSI */ xhci->quirks |= XHCI_PLAT; + + if ((node && of_property_read_bool(node, "usb3-lpm-capable")) || + (pdata && pdata->usb3_lpm_capable)) + xhci->quirks |= XHCI_LPM_SUPPORT; } /* called during probe() after chip reset completes */ @@ -73,9 +80,62 @@ return xhci_run(hcd); } +static ssize_t config_imod_store(struct device *pdev, + struct device_attribute *attr, const char *buff, size_t size) +{ + struct usb_hcd *hcd = dev_get_drvdata(pdev); + struct xhci_hcd *xhci; + u32 temp; + u32 imod; + unsigned long flags; + + if (kstrtouint(buff, 10, &imod) != 1) + return 0; + + imod &= ER_IRQ_INTERVAL_MASK; + xhci = hcd_to_xhci(hcd); + + if (xhci->shared_hcd->state == HC_STATE_SUSPENDED + && hcd->state == HC_STATE_SUSPENDED) + return -EACCES; + + spin_lock_irqsave(&xhci->lock, flags); + temp = readl_relaxed(&xhci->ir_set->irq_control); + temp &= ~ER_IRQ_INTERVAL_MASK; + temp |= imod; + writel_relaxed(temp, &xhci->ir_set->irq_control); + spin_unlock_irqrestore(&xhci->lock, flags); + + return size; +} + +static ssize_t config_imod_show(struct device *pdev, + struct device_attribute *attr, char *buff) +{ + struct usb_hcd *hcd = dev_get_drvdata(pdev); + struct xhci_hcd *xhci; + u32 temp; + unsigned long flags; + + xhci = hcd_to_xhci(hcd); + + if (xhci->shared_hcd->state == HC_STATE_SUSPENDED + && hcd->state == HC_STATE_SUSPENDED) + return -EACCES; + + spin_lock_irqsave(&xhci->lock, flags); + temp = readl_relaxed(&xhci->ir_set->irq_control) & + ER_IRQ_INTERVAL_MASK; + spin_unlock_irqrestore(&xhci->lock, flags); + + return snprintf(buff, PAGE_SIZE, "%08u\n", temp); +} + +static DEVICE_ATTR(config_imod, S_IRUGO | S_IWUSR, + config_imod_show, config_imod_store); + static int xhci_plat_probe(struct platform_device *pdev) { - struct device_node *node = pdev->dev.of_node; struct usb_xhci_pdata *pdata = dev_get_platdata(&pdev->dev); const struct hc_driver *driver; struct xhci_hcd *xhci; @@ -84,6 +144,8 @@ struct clk *clk; int ret; int irq; + u32 temp, imod; + unsigned long flags; if (usb_disabled()) return -ENODEV; @@ -113,6 +175,8 @@ if (!hcd) return -ENOMEM; + hcd_to_bus(hcd)->skip_resume = true; + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); hcd->regs = devm_ioremap_resource(&pdev->dev, res); if (IS_ERR(hcd->regs)) { @@ -137,6 +201,15 @@ goto put_hcd; } + if (pdev->dev.parent) + pm_runtime_resume(pdev->dev.parent); + + pm_runtime_use_autosuspend(&pdev->dev); + pm_runtime_set_autosuspend_delay(&pdev->dev, 1000); + pm_runtime_set_active(&pdev->dev); + pm_runtime_enable(&pdev->dev); + pm_runtime_get_sync(&pdev->dev); + if (of_device_is_compatible(pdev->dev.of_node, "marvell,armada-375-xhci") || of_device_is_compatible(pdev->dev.of_node, @@ -158,9 +231,11 @@ goto disable_clk; } - if ((node && of_property_read_bool(node, "usb3-lpm-capable")) || - (pdata && pdata->usb3_lpm_capable)) - xhci->quirks |= XHCI_LPM_SUPPORT; + hcd_to_bus(xhci->shared_hcd)->skip_resume = true; + + if (device_property_read_u32(pdev->dev.parent, "usb-core-id", + &xhci->core_id)) + xhci->core_id = -EINVAL; hcd->usb_phy = devm_usb_get_phy_by_phandle(&pdev->dev, "usb-phy", 0); if (IS_ERR(hcd->usb_phy)) { @@ -178,6 +253,8 @@ if (ret) goto disable_usb_phy; + device_wakeup_enable(&hcd->self.root_hub->dev); + if (HCC_MAX_PSA(xhci->hcc_params) >= 4) xhci->shared_hcd->can_do_streams = 1; @@ -185,6 +262,28 @@ if (ret) goto dealloc_usb2_hcd; + device_wakeup_enable(&xhci->shared_hcd->self.root_hub->dev); + + /* override imod interval if specified */ + if (pdata && pdata->imod_interval) { + imod = pdata->imod_interval & ER_IRQ_INTERVAL_MASK; + spin_lock_irqsave(&xhci->lock, flags); + temp = readl_relaxed(&xhci->ir_set->irq_control); + temp &= ~ER_IRQ_INTERVAL_MASK; + temp |= imod; + writel_relaxed(temp, &xhci->ir_set->irq_control); + spin_unlock_irqrestore(&xhci->lock, flags); + dev_dbg(&pdev->dev, "%s: imod set to %u\n", __func__, imod); + } + + ret = device_create_file(&pdev->dev, &dev_attr_config_imod); + if (ret) + dev_err(&pdev->dev, "%s: unable to create imod sysfs entry\n", + __func__); + + pm_runtime_mark_last_busy(&pdev->dev); + pm_runtime_put_autosuspend(&pdev->dev); + return 0; @@ -213,8 +312,10 @@ struct xhci_hcd *xhci = hcd_to_xhci(hcd); struct clk *clk = xhci->clk; - xhci->xhc_state |= XHCI_STATE_REMOVING; + pm_runtime_disable(&dev->dev); + device_remove_file(&dev->dev, &dev_attr_config_imod); + xhci->xhc_state |= XHCI_STATE_REMOVING; usb_remove_hcd(xhci->shared_hcd); usb_phy_shutdown(hcd->usb_phy); @@ -234,27 +335,79 @@ struct usb_hcd *hcd = dev_get_drvdata(dev); struct xhci_hcd *xhci = hcd_to_xhci(hcd); + if (!xhci) + return 0; + + dev_dbg(dev, "xhci-plat PM suspend\n"); + + return xhci_suspend(xhci, true); +} + +static int xhci_plat_resume(struct device *dev) +{ + struct usb_hcd *hcd = dev_get_drvdata(dev); + struct xhci_hcd *xhci = hcd_to_xhci(hcd); + + if (!xhci) + return 0; + + dev_dbg(dev, "xhci-plat PM resume\n"); + + return xhci_resume(xhci, false); +} +#endif + +#ifdef CONFIG_PM +static int xhci_plat_runtime_idle(struct device *dev) +{ /* - * xhci_suspend() needs `do_wakeup` to know whether host is allowed - * to do wakeup during suspend. Since xhci_plat_suspend is currently - * only designed for system suspend, device_may_wakeup() is enough - * to dertermine whether host is allowed to do wakeup. Need to - * reconsider this when xhci_plat_suspend enlarges its scope, e.g., - * also applies to runtime suspend. + * When pm_runtime_put_autosuspend() is called on this device, + * after this idle callback returns the PM core will schedule the + * autosuspend if there is any remaining time until expiry. However, + * when reaching this point because the child_count becomes 0, the + * core does not honor autosuspend in that case and results in + * idle/suspend happening immediately. In order to have a delay + * before suspend we have to call pm_runtime_autosuspend() manually. */ - return xhci_suspend(xhci, device_may_wakeup(dev)); + pm_runtime_mark_last_busy(dev); + pm_runtime_autosuspend(dev); + return -EBUSY; } -static int xhci_plat_resume(struct device *dev) +static int xhci_plat_runtime_suspend(struct device *dev) +{ + struct usb_hcd *hcd = dev_get_drvdata(dev); + struct xhci_hcd *xhci = hcd_to_xhci(hcd); + + if (!xhci) + return 0; + + dev_dbg(dev, "xhci-plat runtime suspend\n"); + + return xhci_suspend(xhci, true); +} + +static int xhci_plat_runtime_resume(struct device *dev) { struct usb_hcd *hcd = dev_get_drvdata(dev); struct xhci_hcd *xhci = hcd_to_xhci(hcd); + int ret; - return xhci_resume(xhci, 0); + if (!xhci) + return 0; + + dev_dbg(dev, "xhci-plat runtime resume\n"); + + ret = xhci_resume(xhci, false); + pm_runtime_mark_last_busy(dev); + + return ret; } static const struct dev_pm_ops xhci_plat_pm_ops = { SET_SYSTEM_SLEEP_PM_OPS(xhci_plat_suspend, xhci_plat_resume) + SET_RUNTIME_PM_OPS(xhci_plat_runtime_suspend, xhci_plat_runtime_resume, + xhci_plat_runtime_idle) }; #define DEV_PM_OPS (&xhci_plat_pm_ops) #else diff -ruw linux-4.4.115/drivers/usb/host/xhci-ring.c linux-4.4.115-fbx/drivers/usb/host/xhci-ring.c --- linux-4.4.115/drivers/usb/host/xhci-ring.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/usb/host/xhci-ring.c 2019-10-29 09:26:25.029216742 +0100 @@ -310,7 +310,7 @@ i_cmd->status = COMP_CMD_STOP; - xhci_dbg(xhci, "Turn aborted command %p to no-op\n", + xhci_dbg(xhci, "Turn aborted command %pK to no-op\n", i_cmd->command_trb); /* get cycle state from the original cmd trb */ cycle_state = le32_to_cpu( @@ -592,7 +592,7 @@ "Cycle state = 0x%x", state->new_cycle_state); xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, - "New dequeue segment = %p (virtual)", + "New dequeue segment = %pK (virtual)", state->new_deq_seg); addr = xhci_trb_virt_to_dma(state->new_deq_seg, state->new_deq_ptr); xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, @@ -627,8 +627,8 @@ xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, "Cancel (unchain) link TRB"); xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, - "Address = %p (0x%llx dma); " - "in seg %p (0x%llx dma)", + "Address = %pK (0x%llx dma); " + "in seg %pK (0x%llx dma)", cur_trb, (unsigned long long)xhci_trb_virt_to_dma(cur_seg, cur_trb), cur_seg, @@ -764,7 +764,7 @@ * short, don't muck with the stream ID after * submission. */ - xhci_warn(xhci, "WARN Cancelled URB %p " + xhci_warn(xhci, "WARN Cancelled URB %pK " "has invalid stream ID %u.\n", cur_td->urb, cur_td->urb->stream_id); @@ -1103,7 +1103,7 @@ ep_ring, ep_index); } else { xhci_warn(xhci, "Mismatch between completed Set TR Deq Ptr command & xHCI internal state.\n"); - xhci_warn(xhci, "ep deq seg = %p, deq ptr = %p\n", + xhci_warn(xhci, "ep deq seg = %pK, deq ptr = %pK\n", ep->queued_deq_seg, ep->queued_deq_ptr); } } @@ -2624,7 +2624,7 @@ URB_SHORT_NOT_OK)) || (status != 0 && !usb_endpoint_xfer_isoc(&urb->ep->desc))) - xhci_dbg(xhci, "Giveback URB %p, len = %d, " + xhci_dbg(xhci, "Giveback URB %pK, len = %d, " "expected = %d, status = %d\n", urb, urb->actual_length, urb->transfer_buffer_length, @@ -3574,6 +3574,156 @@ return 0; } +/* + * Variant of xhci_queue_ctrl_tx() used to implement EHSET + * SINGLE_STEP_SET_FEATURE test mode. It differs in that the control + * transfer is broken up so that the SETUP stage can happen and call + * the URB's completion handler before the DATA/STATUS stages are + * executed by the xHC hardware. This assumes the control transfer is a + * GetDescriptor, with a DATA stage in the IN direction, and an OUT + * STATUS stage. + * + * This function is called twice, usually with a 15-second delay in between. + * - with is_setup==true, the SETUP stage for the control request + * (GetDescriptor) is queued in the TRB ring and sent to HW immediately + * - with is_setup==false, the DATA and STATUS TRBs are queued and exceuted + * + * Caller must have locked xhci->lock + */ +int xhci_submit_single_step_set_feature(struct usb_hcd *hcd, struct urb *urb, + int is_setup) +{ + struct xhci_hcd *xhci = hcd_to_xhci(hcd); + struct xhci_ring *ep_ring; + int num_trbs; + int ret; + unsigned int slot_id, ep_index; + struct usb_ctrlrequest *setup; + struct xhci_generic_trb *start_trb; + int start_cycle; + u32 field, length_field, remainder; + struct urb_priv *urb_priv; + struct xhci_td *td; + + ep_ring = xhci_urb_to_transfer_ring(xhci, urb); + if (!ep_ring) + return -EINVAL; + + /* Need buffer for data stage */ + if (urb->transfer_buffer_length <= 0) + return -EINVAL; + + /* + * Need to copy setup packet into setup TRB, so we can't use the setup + * DMA address. + */ + if (!urb->setup_packet) + return -EINVAL; + setup = (struct usb_ctrlrequest *) urb->setup_packet; + + slot_id = urb->dev->slot_id; + ep_index = xhci_get_endpoint_index(&urb->ep->desc); + + urb_priv = kzalloc(sizeof(struct urb_priv) + + sizeof(struct xhci_td *), GFP_ATOMIC); + if (!urb_priv) + return -ENOMEM; + + td = urb_priv->td[0] = kzalloc(sizeof(struct xhci_td), GFP_ATOMIC); + if (!td) { + kfree(urb_priv); + return -ENOMEM; + } + + urb_priv->length = 1; + urb_priv->td_cnt = 0; + urb->hcpriv = urb_priv; + + num_trbs = is_setup ? 1 : 2; + + ret = prepare_transfer(xhci, xhci->devs[slot_id], + ep_index, urb->stream_id, + num_trbs, urb, 0, GFP_ATOMIC); + if (ret < 0) { + kfree(td); + kfree(urb_priv); + return ret; + } + + /* + * Don't give the first TRB to the hardware (by toggling the cycle bit) + * until we've finished creating all the other TRBs. The ring's cycle + * state may change as we enqueue the other TRBs, so save it too. + */ + start_trb = &ep_ring->enqueue->generic; + start_cycle = ep_ring->cycle_state; + + if (is_setup) { + /* Queue only the setup TRB */ + field = TRB_IDT | TRB_IOC | TRB_TYPE(TRB_SETUP); + if (start_cycle == 0) + field |= 0x1; + + /* xHCI 1.0 6.4.1.2.1: Transfer Type field */ + if (xhci->hci_version == 0x100) { + if (setup->bRequestType & USB_DIR_IN) + field |= TRB_TX_TYPE(TRB_DATA_IN); + else + field |= TRB_TX_TYPE(TRB_DATA_OUT); + } + + /* Save the DMA address of the last TRB in the TD */ + td->last_trb = ep_ring->enqueue; + + queue_trb(xhci, ep_ring, false, + setup->bRequestType | setup->bRequest << 8 | + le16_to_cpu(setup->wValue) << 16, + le16_to_cpu(setup->wIndex) | + le16_to_cpu(setup->wLength) << 16, + TRB_LEN(8) | TRB_INTR_TARGET(0), + field); + } else { + /* Queue data TRB */ + field = TRB_ISP | TRB_TYPE(TRB_DATA); + if (start_cycle == 0) + field |= 0x1; + if (setup->bRequestType & USB_DIR_IN) + field |= TRB_DIR_IN; + + remainder = xhci_td_remainder(xhci, 0, + urb->transfer_buffer_length, + urb->transfer_buffer_length, + urb, 1); + + length_field = TRB_LEN(urb->transfer_buffer_length) | + TRB_TD_SIZE(remainder) | + TRB_INTR_TARGET(0); + + queue_trb(xhci, ep_ring, true, + lower_32_bits(urb->transfer_dma), + upper_32_bits(urb->transfer_dma), + length_field, + field); + + /* Save the DMA address of the last TRB in the TD */ + td->last_trb = ep_ring->enqueue; + + /* Queue status TRB */ + field = TRB_IOC | TRB_TYPE(TRB_STATUS); + if (!(setup->bRequestType & USB_DIR_IN)) + field |= TRB_DIR_IN; + + queue_trb(xhci, ep_ring, false, + 0, + 0, + TRB_INTR_TARGET(0), + field | ep_ring->cycle_state); + } + + giveback_first_trb(xhci, slot_id, ep_index, 0, start_cycle, start_trb); + return 0; +} + static int count_isoc_trbs_needed(struct xhci_hcd *xhci, struct urb *urb, int i) { @@ -4178,7 +4328,7 @@ int ret; xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, - "Set TR Deq Ptr cmd, new deq seg = %p (0x%llx dma), new deq ptr = %p (0x%llx dma), new cycle = %u", + "Set TR Deq Ptr cmd, new deq seg = %pK (0x%llx dma), new deq ptr = %pK (0x%llx dma), new cycle = %u", deq_state->new_deq_seg, (unsigned long long)deq_state->new_deq_seg->dma, deq_state->new_deq_ptr, @@ -4190,7 +4340,7 @@ deq_state->new_deq_ptr); if (addr == 0) { xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr\n"); - xhci_warn(xhci, "WARN deq seg = %p, deq pt = %p\n", + xhci_warn(xhci, "WARN deq seg = %pK, deq pt = %pK\n", deq_state->new_deq_seg, deq_state->new_deq_ptr); return; } diff -ruw linux-4.4.115/drivers/usb/host/xhci-trace.h linux-4.4.115-fbx/drivers/usb/host/xhci-trace.h --- linux-4.4.115/drivers/usb/host/xhci-trace.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/usb/host/xhci-trace.h 2019-01-22 16:16:27.347281216 +0100 @@ -103,7 +103,7 @@ ((HCC_64BYTE_CONTEXT(xhci->hcc_params) + 1) * 32) * ((ctx->type == XHCI_CTX_TYPE_INPUT) + ep_num + 1)); ), - TP_printk("\nctx_64=%d, ctx_type=%u, ctx_dma=@%llx, ctx_va=@%p", + TP_printk("\nctx_64=%d, ctx_type=%u, ctx_dma=@%llx, ctx_va=@%pK", __entry->ctx_64, __entry->ctx_type, (unsigned long long) __entry->ctx_dma, __entry->ctx_va ) @@ -134,7 +134,7 @@ memcpy(__get_dynamic_array(trb), trb_va, sizeof(struct xhci_generic_trb)); ), - TP_printk("\ntrb_dma=@%llx, trb_va=@%p, status=%08x, flags=%08x", + TP_printk("\ntrb_dma=@%llx, trb_va=@%pK, status=%08x, flags=%08x", (unsigned long long) __entry->dma, __entry->va, __entry->status, __entry->flags ) diff -ruw linux-4.4.115/drivers/usb/Kconfig linux-4.4.115-fbx/drivers/usb/Kconfig --- linux-4.4.115/drivers/usb/Kconfig 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/usb/Kconfig 2019-01-22 16:16:27.227280130 +0100 @@ -106,6 +106,8 @@ source "drivers/usb/isp1760/Kconfig" +source "drivers/usb/pd/Kconfig" + comment "USB port drivers" if USB diff -ruw linux-4.4.115/drivers/usb/Makefile linux-4.4.115-fbx/drivers/usb/Makefile --- linux-4.4.115/drivers/usb/Makefile 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/usb/Makefile 2019-01-22 16:16:27.227280130 +0100 @@ -61,3 +61,5 @@ obj-$(CONFIG_USB_COMMON) += common/ obj-$(CONFIG_USBIP_CORE) += usbip/ + +obj-$(CONFIG_USB_PD) += pd/ diff -ruw linux-4.4.115/drivers/usb/misc/Kconfig linux-4.4.115-fbx/drivers/usb/misc/Kconfig --- linux-4.4.115/drivers/usb/misc/Kconfig 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/usb/misc/Kconfig 2019-10-29 09:26:25.037216820 +0100 @@ -268,3 +268,13 @@ To compile this driver as a module, choose M here: the module will be called chaoskey. + +config USB_QTI_KS_BRIDGE + tristate "USB QTI kick start bridge" + depends on USB + help + Say Y here if you have a QTI modem device connected via USB that + will be bridged in kernel space. This driver works as a bridge to pass + boot images, ram-dumps and efs sync. + To compile this driver as a module, choose M here: the module + will be called ks_bridge. If unsure, choose N. diff -ruw linux-4.4.115/drivers/usb/misc/Makefile linux-4.4.115-fbx/drivers/usb/misc/Makefile --- linux-4.4.115/drivers/usb/misc/Makefile 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/usb/misc/Makefile 2019-10-29 09:26:25.037216820 +0100 @@ -29,3 +29,5 @@ obj-$(CONFIG_USB_SISUSBVGA) += sisusbvga/ obj-$(CONFIG_USB_LINK_LAYER_TEST) += lvstest.o + +obj-$(CONFIG_USB_QTI_KS_BRIDGE) += ks_bridge.o diff -ruw linux-4.4.115/drivers/usb/phy/Kconfig linux-4.4.115-fbx/drivers/usb/phy/Kconfig --- linux-4.4.115/drivers/usb/phy/Kconfig 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/usb/phy/Kconfig 2019-10-29 09:26:25.045216898 +0100 @@ -6,6 +6,14 @@ config USB_PHY def_bool n +config USB_OTG_WAKELOCK + bool "Hold a wakelock when USB connected" + depends on WAKELOCK + select USB_OTG_UTILS + help + Select this to automatically hold a wakelock when USB is + connected, preventing suspend. + # # USB Transceiver Drivers # @@ -165,6 +173,46 @@ To compile this driver as a module, choose M here: the module will be called phy-qcom-8x16-usb. +config USB_MSM_HSPHY + tristate "MSM HSUSB PHY Driver" + depends on ARCH_QCOM + select USB_PHY + help + Enable this to support the High-speed USB transceiver on MSM chips. + This driver supports the PHY which uses the QSCRATCH-based register + set for its control sequences, normally paired with newer DWC3-based + SuperSpeed controllers. + +config USB_MSM_SSPHY + tristate "MSM SSUSB PHY Driver" + depends on ARCH_QCOM + select USB_PHY + help + Enable this to support the SuperSpeed USB transceiver on MSM chips. + This driver supports the PHY which uses the QSCRATCH-based register + set for its control sequences, normally paired with newer DWC3-based + SuperSpeed controllers. + +config USB_MSM_SSPHY_QMP + tristate "MSM SSUSB QMP PHY Driver" + depends on ARCH_QCOM + select USB_PHY + help + Enable this to support the SuperSpeed USB transceiver on MSM chips. + This driver supports the PHY which uses the QSCRATCH-based register + set for its control sequences, normally paired with newer DWC3-based + SuperSpeed controllers. + +config MSM_QUSB_PHY + tristate "MSM QUSB2 PHY Driver" + depends on ARCH_QCOM + select USB_PHY + help + Enable this to support the QUSB2 PHY on MSM chips. This driver supports + the high-speed PHY which is usually paired with either the ChipIdea or + Synopsys DWC3 USB IPs on MSM SOCs. This driver expects to configure the + PHY with a dedicated register I/O memory region. + config USB_MV_OTG tristate "Marvell USB OTG support" depends on USB_EHCI_MV && USB_MV_UDC && PM && USB_OTG @@ -213,4 +261,13 @@ Provides read/write operations to the ULPI phy register set for controllers with a viewport register (e.g. Chipidea/ARC controllers). +config DUAL_ROLE_USB_INTF + bool "Generic DUAL ROLE sysfs interface" + depends on SYSFS && USB_PHY + help + A generic sysfs interface to track and change the state of + dual role usb phys. The usb phy drivers can register to + this interface to expose it capabilities to the userspace + and thereby allowing userspace to change the port mode. + endmenu diff -ruw linux-4.4.115/drivers/usb/phy/Makefile linux-4.4.115-fbx/drivers/usb/phy/Makefile --- linux-4.4.115/drivers/usb/phy/Makefile 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/usb/phy/Makefile 2019-01-22 16:16:27.371281434 +0100 @@ -3,6 +3,8 @@ # obj-$(CONFIG_USB_PHY) += phy.o obj-$(CONFIG_OF) += of.o +obj-$(CONFIG_USB_OTG_WAKELOCK) += otg-wakelock.o +obj-$(CONFIG_DUAL_ROLE_USB_INTF) += class-dual-role.o # transceiver drivers, keep the list sorted @@ -21,6 +23,10 @@ obj-$(CONFIG_USB_ISP1301) += phy-isp1301.o obj-$(CONFIG_USB_MSM_OTG) += phy-msm-usb.o obj-$(CONFIG_USB_QCOM_8X16_PHY) += phy-qcom-8x16-usb.o +obj-$(CONFIG_USB_MSM_HSPHY) += phy-msm-hsusb.o +obj-$(CONFIG_USB_MSM_SSPHY) += phy-msm-ssusb.o +obj-$(CONFIG_USB_MSM_SSPHY_QMP) += phy-msm-ssusb-qmp.o +obj-$(CONFIG_MSM_QUSB_PHY) += phy-msm-qusb.o phy-msm-qusb-v2.o obj-$(CONFIG_USB_MV_OTG) += phy-mv-usb.o obj-$(CONFIG_USB_MXS_PHY) += phy-mxs-usb.o obj-$(CONFIG_USB_RCAR_PHY) += phy-rcar-usb.o diff -ruw linux-4.4.115/drivers/video/fbdev/core/fbcmap.c linux-4.4.115-fbx/drivers/video/fbdev/core/fbcmap.c --- linux-4.4.115/drivers/video/fbdev/core/fbcmap.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/video/fbdev/core/fbcmap.c 2019-10-29 09:26:25.085217290 +0100 @@ -203,6 +203,8 @@ return -EINVAL; size *= sizeof(u16); + + if (copy_to_user(to->red+tooff, from->red+fromoff, size)) return -EFAULT; if (copy_to_user(to->green+tooff, from->green+fromoff, size)) diff -ruw linux-4.4.115/drivers/video/fbdev/core/fbmem.c linux-4.4.115-fbx/drivers/video/fbdev/core/fbmem.c --- linux-4.4.115/drivers/video/fbdev/core/fbmem.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/video/fbdev/core/fbmem.c 2019-10-29 09:26:25.085217290 +0100 @@ -1085,7 +1085,7 @@ EXPORT_SYMBOL(fb_blank); static long do_fb_ioctl(struct fb_info *info, unsigned int cmd, - unsigned long arg) + unsigned long arg, struct file *file) { struct fb_ops *fb; struct fb_var_screeninfo var; @@ -1097,6 +1097,13 @@ void __user *argp = (void __user *)arg; long ret = 0; + memset(&var, 0, sizeof(var)); + memset(&fix, 0, sizeof(fix)); + memset(&con2fb, 0, sizeof(con2fb)); + memset(&cmap_from, 0, sizeof(cmap_from)); + memset(&cmap, 0, sizeof(cmap)); + memset(&event, 0, sizeof(event)); + switch (cmd) { case FBIOGET_VSCREENINFO: if (!lock_fb_info(info)) @@ -1212,14 +1219,13 @@ console_unlock(); break; default: - if (!lock_fb_info(info)) - return -ENODEV; fb = info->fbops; - if (fb->fb_ioctl) + if (fb->fb_ioctl_v2) + ret = fb->fb_ioctl_v2(info, cmd, arg, file); + else if (fb->fb_ioctl) ret = fb->fb_ioctl(info, cmd, arg); else ret = -ENOTTY; - unlock_fb_info(info); } return ret; } @@ -1230,7 +1236,7 @@ if (!info) return -ENODEV; - return do_fb_ioctl(info, cmd, arg); + return do_fb_ioctl(info, cmd, arg, file); } #ifdef CONFIG_COMPAT @@ -1261,7 +1267,7 @@ }; static int fb_getput_cmap(struct fb_info *info, unsigned int cmd, - unsigned long arg) + unsigned long arg, struct file *file) { struct fb_cmap_user __user *cmap; struct fb_cmap32 __user *cmap32; @@ -1284,7 +1290,7 @@ put_user(compat_ptr(data), &cmap->transp)) return -EFAULT; - err = do_fb_ioctl(info, cmd, (unsigned long) cmap); + err = do_fb_ioctl(info, cmd, (unsigned long) cmap, file); if (!err) { if (copy_in_user(&cmap32->start, @@ -1329,7 +1335,7 @@ } static int fb_get_fscreeninfo(struct fb_info *info, unsigned int cmd, - unsigned long arg) + unsigned long arg, struct file *file) { mm_segment_t old_fs; struct fb_fix_screeninfo fix; @@ -1340,7 +1346,7 @@ old_fs = get_fs(); set_fs(KERNEL_DS); - err = do_fb_ioctl(info, cmd, (unsigned long) &fix); + err = do_fb_ioctl(info, cmd, (unsigned long) &fix, file); set_fs(old_fs); if (!err) @@ -1367,20 +1373,22 @@ case FBIOPUT_CON2FBMAP: arg = (unsigned long) compat_ptr(arg); case FBIOBLANK: - ret = do_fb_ioctl(info, cmd, arg); + ret = do_fb_ioctl(info, cmd, arg, file); break; case FBIOGET_FSCREENINFO: - ret = fb_get_fscreeninfo(info, cmd, arg); + ret = fb_get_fscreeninfo(info, cmd, arg, file); break; case FBIOGETCMAP: case FBIOPUTCMAP: - ret = fb_getput_cmap(info, cmd, arg); + ret = fb_getput_cmap(info, cmd, arg, file); break; default: - if (fb->fb_compat_ioctl) + if (fb->fb_compat_ioctl_v2) + ret = fb->fb_compat_ioctl_v2(info, cmd, arg, file); + else if (fb->fb_compat_ioctl) ret = fb->fb_compat_ioctl(info, cmd, arg); break; } @@ -1460,6 +1468,7 @@ goto out; } file->private_data = info; + info->file = file; if (info->fbops->fb_open) { res = info->fbops->fb_open(info,1); if (res) @@ -1484,6 +1493,7 @@ struct fb_info * const info = file->private_data; mutex_lock(&info->lock); + info->file = file; if (info->fbops->fb_release) info->fbops->fb_release(info,1); module_put(info->fbops->owner); diff -ruw linux-4.4.115/drivers/video/fbdev/Kconfig linux-4.4.115-fbx/drivers/video/fbdev/Kconfig --- linux-4.4.115/drivers/video/fbdev/Kconfig 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/video/fbdev/Kconfig 2019-10-29 09:26:25.081217251 +0100 @@ -2328,6 +2328,19 @@ Select this option if display contents should be inherited as set by the bootloader. +config FB_MSM + tristate "MSM Framebuffer support" + depends on FB && ARCH_QCOM + select FB_CFB_FILLRECT + select FB_CFB_COPYAREA + select FB_CFB_IMAGEBLIT + select SYNC + select SW_SYNC + ---help--- + The MSM driver implements a frame buffer interface to provide access to + the display hardware and provide a way for users to display graphics + on connected display panels. + config FB_MX3 tristate "MX3 Framebuffer support" depends on FB && MX3_IPU @@ -2449,6 +2462,7 @@ source "drivers/video/fbdev/omap2/Kconfig" source "drivers/video/fbdev/exynos/Kconfig" source "drivers/video/fbdev/mmp/Kconfig" +source "drivers/video/fbdev/msm/Kconfig" config FB_SH_MOBILE_MERAM tristate "SuperH Mobile MERAM read ahead support" diff -ruw linux-4.4.115/drivers/video/fbdev/Makefile linux-4.4.115-fbx/drivers/video/fbdev/Makefile --- linux-4.4.115/drivers/video/fbdev/Makefile 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/video/fbdev/Makefile 2019-01-22 16:16:27.443282086 +0100 @@ -126,6 +126,11 @@ obj-$(CONFIG_XEN_FBDEV_FRONTEND) += xen-fbfront.o obj-$(CONFIG_FB_CARMINE) += carminefb.o obj-$(CONFIG_FB_MB862XX) += mb862xx/ +ifeq ($(CONFIG_FB_MSM),y) +obj-y += msm/ +else +obj-$(CONFIG_MSM_DBA) += msm/msm_dba/ +endif obj-$(CONFIG_FB_NUC900) += nuc900fb.o obj-$(CONFIG_FB_JZ4740) += jz4740_fb.o obj-$(CONFIG_FB_PUV3_UNIGFX) += fb-puv3.o diff -ruw linux-4.4.115/drivers/video/hdmi.c linux-4.4.115-fbx/drivers/video/hdmi.c --- linux-4.4.115/drivers/video/hdmi.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/video/hdmi.c 2019-10-29 09:26:25.129217720 +0100 @@ -533,6 +533,10 @@ return "4:3"; case HDMI_PICTURE_ASPECT_16_9: return "16:9"; + case HDMI_PICTURE_ASPECT_64_27: + return "64:27"; + case HDMI_PICTURE_ASPECT_256_135: + return "256:135"; case HDMI_PICTURE_ASPECT_RESERVED: return "Reserved"; } diff -ruw linux-4.4.115/drivers/video/Kconfig linux-4.4.115-fbx/drivers/video/Kconfig --- linux-4.4.115/drivers/video/Kconfig 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/video/Kconfig 2019-01-22 16:16:27.431281977 +0100 @@ -21,14 +21,17 @@ source "drivers/gpu/host1x/Kconfig" source "drivers/gpu/ipu-v3/Kconfig" +source "drivers/gpu/msm/Kconfig" source "drivers/gpu/drm/Kconfig" +source "drivers/video/msm/ba/Kconfig" menu "Frame buffer Devices" source "drivers/video/fbdev/Kconfig" endmenu source "drivers/video/backlight/Kconfig" +source "drivers/video/adf/Kconfig" config VGASTATE tristate diff -ruw linux-4.4.115/drivers/video/Makefile linux-4.4.115-fbx/drivers/video/Makefile --- linux-4.4.115/drivers/video/Makefile 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/drivers/video/Makefile 2019-01-22 16:16:27.431281977 +0100 @@ -1,6 +1,8 @@ +obj-$(CONFIG_MSM_BA_V4L2) += msm/ba/ obj-$(CONFIG_VGASTATE) += vgastate.o obj-$(CONFIG_HDMI) += hdmi.o +obj-$(CONFIG_ADF) += adf/ obj-$(CONFIG_VT) += console/ obj-$(CONFIG_LOGO) += logo/ obj-y += backlight/ diff -ruw linux-4.4.115/fs/attr.c linux-4.4.115-fbx/fs/attr.c --- linux-4.4.115/fs/attr.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/fs/attr.c 2019-01-22 16:16:27.695284368 +0100 @@ -187,7 +187,7 @@ * the file open for write, as there can be no conflicting delegation in * that case. */ -int notify_change(struct dentry * dentry, struct iattr * attr, struct inode **delegated_inode) +int notify_change2(struct vfsmount *mnt, struct dentry * dentry, struct iattr * attr, struct inode **delegated_inode) { struct inode *inode = dentry->d_inode; umode_t mode = inode->i_mode; @@ -211,7 +211,7 @@ return -EPERM; if (!inode_owner_or_capable(inode)) { - error = inode_permission(inode, MAY_WRITE); + error = inode_permission2(mnt, inode, MAY_WRITE); if (error) return error; } @@ -277,7 +277,9 @@ if (error) return error; - if (inode->i_op->setattr) + if (mnt && inode->i_op->setattr2) + error = inode->i_op->setattr2(mnt, dentry, attr); + else if (inode->i_op->setattr) error = inode->i_op->setattr(dentry, attr); else error = simple_setattr(dentry, attr); @@ -290,4 +292,10 @@ return error; } +EXPORT_SYMBOL(notify_change2); + +int notify_change(struct dentry * dentry, struct iattr * attr, struct inode **delegated_inode) +{ + return notify_change2(NULL, dentry, attr, delegated_inode); +} EXPORT_SYMBOL(notify_change); diff -ruw linux-4.4.115/fs/binfmt_elf.c linux-4.4.115-fbx/fs/binfmt_elf.c --- linux-4.4.115/fs/binfmt_elf.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/fs/binfmt_elf.c 2019-10-29 09:26:25.149217916 +0100 @@ -651,7 +651,7 @@ if ((current->flags & PF_RANDOMIZE) && !(current->personality & ADDR_NO_RANDOMIZE)) { - random_variable = (unsigned long) get_random_int(); + random_variable = get_random_long(); random_variable &= STACK_RND_MASK; random_variable <<= PAGE_SHIFT; } diff -ruw linux-4.4.115/fs/block_dev.c linux-4.4.115-fbx/fs/block_dev.c --- linux-4.4.115/fs/block_dev.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/fs/block_dev.c 2019-01-22 16:16:27.703284440 +0100 @@ -532,6 +532,7 @@ #ifdef CONFIG_SYSFS INIT_LIST_HEAD(&bdev->bd_holder_disks); #endif + bdev->bd_bdi = &noop_backing_dev_info; inode_init_once(&ei->vfs_inode); /* Initialize mutex for freeze. */ mutex_init(&bdev->bd_fsfreeze_mutex); @@ -557,6 +558,12 @@ } list_del_init(&bdev->bd_list); spin_unlock(&bdev_lock); + /* Detach inode from wb early as bdi_put() may free bdi->wb */ + inode_detach_wb(inode); + if (bdev->bd_bdi != &noop_backing_dev_info) { + bdi_put(bdev->bd_bdi); + bdev->bd_bdi = &noop_backing_dev_info; + } } static const struct super_operations bdev_sops = { @@ -623,6 +630,21 @@ static LIST_HEAD(all_bdevs); +/* + * If there is a bdev inode for this device, unhash it so that it gets evicted + * as soon as last inode reference is dropped. + */ +void bdev_unhash_inode(dev_t dev) +{ + struct inode *inode; + + inode = ilookup5(blockdev_superblock, hash(dev), bdev_test, &dev); + if (inode) { + remove_inode_hash(inode); + iput(inode); + } +} + struct block_device *bdget(dev_t dev) { struct block_device *bdev; @@ -1201,6 +1223,7 @@ bdev->bd_disk = disk; bdev->bd_queue = disk->queue; bdev->bd_contains = bdev; + bdev->bd_inode->i_flags = disk->fops->direct_access ? S_DAX : 0; if (!partno) { ret = -ENXIO; @@ -1271,6 +1294,9 @@ (bdev->bd_part->nr_sects % (PAGE_SIZE / 512))) bdev->bd_inode->i_flags &= ~S_DAX; } + + if (bdev->bd_bdi == &noop_backing_dev_info) + bdev->bd_bdi = bdi_get(disk->queue->backing_dev_info); } else { if (bdev->bd_contains == bdev) { ret = 0; @@ -1523,12 +1549,6 @@ kill_bdev(bdev); bdev_write_inode(bdev); - /* - * Detaching bdev inode from its wb in __destroy_inode() - * is too late: the queue which embeds its bdi (along with - * root wb) can be gone as soon as we put_disk() below. - */ - inode_detach_wb(bdev->bd_inode); } if (bdev->bd_contains == bdev) { if (disk->fops->release) diff -ruw linux-4.4.115/fs/buffer.c linux-4.4.115-fbx/fs/buffer.c --- linux-4.4.115/fs/buffer.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/fs/buffer.c 2019-10-29 09:26:25.193218347 +0100 @@ -621,6 +621,18 @@ } EXPORT_SYMBOL(mark_buffer_dirty_inode); +#ifdef CONFIG_BLK_DEV_IO_TRACE +static inline void save_dirty_task(struct page *page) +{ + /* Save the task that is dirtying this page */ + page->tsk_dirty = current; +} +#else +static inline void save_dirty_task(struct page *page) +{ +} +#endif + /* * Mark the page dirty, and set it dirty in the radix tree, and mark the inode * dirty. @@ -641,6 +653,7 @@ account_page_dirtied(page, mapping, memcg); radix_tree_tag_set(&mapping->page_tree, page_index(page), PAGECACHE_TAG_DIRTY); + save_dirty_task(page); } spin_unlock_irqrestore(&mapping->tree_lock, flags); } @@ -1466,12 +1479,48 @@ return 0; } +static void __evict_bh_lru(void *arg) +{ + struct bh_lru *b = &get_cpu_var(bh_lrus); + struct buffer_head *bh = arg; + int i; + + for (i = 0; i < BH_LRU_SIZE; i++) { + if (b->bhs[i] == bh) { + brelse(b->bhs[i]); + b->bhs[i] = NULL; + goto out; + } + } +out: + put_cpu_var(bh_lrus); +} + +static bool bh_exists_in_lru(int cpu, void *arg) +{ + struct bh_lru *b = per_cpu_ptr(&bh_lrus, cpu); + struct buffer_head *bh = arg; + int i; + + for (i = 0; i < BH_LRU_SIZE; i++) { + if (b->bhs[i] == bh) + return 1; + } + + return 0; + +} void invalidate_bh_lrus(void) { on_each_cpu_cond(has_bh_in_lru, invalidate_bh_lru, NULL, 1, GFP_KERNEL); } EXPORT_SYMBOL_GPL(invalidate_bh_lrus); +static void evict_bh_lrus(struct buffer_head *bh) +{ + on_each_cpu_cond(bh_exists_in_lru, __evict_bh_lru, bh, 1, GFP_ATOMIC); +} + void set_bh_page(struct buffer_head *bh, struct page *page, unsigned long offset) { @@ -3192,8 +3241,15 @@ do { if (buffer_write_io_error(bh) && page->mapping) set_bit(AS_EIO, &page->mapping->flags); + if (buffer_busy(bh)) { + /* + * Check if the busy failure was due to an + * outstanding LRU reference + */ + evict_bh_lrus(bh); if (buffer_busy(bh)) goto failed; + } bh = bh->b_this_page; } while (bh != head); diff -ruw linux-4.4.115/fs/compat_ioctl.c linux-4.4.115-fbx/fs/compat_ioctl.c --- linux-4.4.115/fs/compat_ioctl.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/fs/compat_ioctl.c 2019-10-29 09:26:25.225218660 +0100 @@ -871,6 +871,9 @@ COMPATIBLE_IOCTL(TIOCSPTLCK) COMPATIBLE_IOCTL(TIOCSERGETLSR) COMPATIBLE_IOCTL(TIOCSIG) +COMPATIBLE_IOCTL(TIOCPMGET) +COMPATIBLE_IOCTL(TIOCPMPUT) +COMPATIBLE_IOCTL(TIOCPMACT) #ifdef TIOCSRS485 COMPATIBLE_IOCTL(TIOCSRS485) #endif diff -ruw linux-4.4.115/fs/coredump.c linux-4.4.115-fbx/fs/coredump.c --- linux-4.4.115/fs/coredump.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/fs/coredump.c 2019-01-22 16:16:27.779285128 +0100 @@ -720,7 +720,7 @@ goto close_fail; if (!(cprm.file->f_mode & FMODE_CAN_WRITE)) goto close_fail; - if (do_truncate(cprm.file->f_path.dentry, 0, 0, cprm.file)) + if (do_truncate2(cprm.file->f_path.mnt, cprm.file->f_path.dentry, 0, 0, cprm.file)) goto close_fail; } diff -ruw linux-4.4.115/fs/dcache.c linux-4.4.115-fbx/fs/dcache.c --- linux-4.4.115/fs/dcache.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/fs/dcache.c 2019-10-29 09:26:25.233218738 +0100 @@ -1392,7 +1392,7 @@ goto out; if (dentry->d_flags & DCACHE_SHRINK_LIST) { - data->found++; + goto out; } else { if (dentry->d_flags & DCACHE_LRU_LIST) d_lru_del(dentry); @@ -3054,6 +3054,7 @@ return ERR_PTR(error); return res; } +EXPORT_SYMBOL(d_absolute_path); /* * same as __d_path but appends "(deleted)" for unlinked files. diff -ruw linux-4.4.115/fs/direct-io.c linux-4.4.115-fbx/fs/direct-io.c --- linux-4.4.115/fs/direct-io.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/fs/direct-io.c 2019-01-22 16:16:27.787285201 +0100 @@ -399,6 +399,7 @@ if (dio->is_async && dio->rw == READ && dio->should_dirty) bio_set_pages_dirty(bio); + bio->bi_dio_inode = dio->inode; dio->bio_bdev = bio->bi_bdev; if (sdio->submit_io) { @@ -413,6 +414,19 @@ sdio->logical_offset_in_bio = 0; } +struct inode *dio_bio_get_inode(struct bio *bio) +{ + struct inode *inode = NULL; + + if (bio == NULL) + return NULL; + + inode = bio->bi_dio_inode; + + return inode; +} +EXPORT_SYMBOL(dio_bio_get_inode); + /* * Release any resources in case of a failure */ diff -ruw linux-4.4.115/fs/drop_caches.c linux-4.4.115-fbx/fs/drop_caches.c --- linux-4.4.115/fs/drop_caches.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/fs/drop_caches.c 2019-10-29 09:26:25.233218738 +0100 @@ -13,7 +13,7 @@ /* A global variable is a bit ugly, but it keeps the code simple */ int sysctl_drop_caches; -static void drop_pagecache_sb(struct super_block *sb, void *unused) +void drop_pagecache_sb(struct super_block *sb, void *unused) { struct inode *inode, *toput_inode = NULL; diff -ruw linux-4.4.115/fs/ecryptfs/Makefile linux-4.4.115-fbx/fs/ecryptfs/Makefile --- linux-4.4.115/fs/ecryptfs/Makefile 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/fs/ecryptfs/Makefile 2019-01-22 16:16:27.791285237 +0100 @@ -4,7 +4,7 @@ obj-$(CONFIG_ECRYPT_FS) += ecryptfs.o -ecryptfs-y := dentry.o file.o inode.o main.o super.o mmap.o read_write.o \ +ecryptfs-y := dentry.o file.o inode.o main.o super.o mmap.o read_write.o events.o \ crypto.o keystore.o kthread.o debug.o ecryptfs-$(CONFIG_ECRYPT_FS_MESSAGING) += messaging.o miscdev.o diff -ruw linux-4.4.115/fs/eventpoll.c linux-4.4.115-fbx/fs/eventpoll.c --- linux-4.4.115/fs/eventpoll.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/fs/eventpoll.c 2019-10-29 09:26:25.237218777 +0100 @@ -34,6 +34,7 @@ #include #include #include +#include #include #include #include @@ -1598,7 +1599,7 @@ { int res = 0, eavail, timed_out = 0; unsigned long flags; - long slack = 0; + u64 slack = 0; wait_queue_t wait; ktime_t expires, *to = NULL; @@ -1645,7 +1646,8 @@ } spin_unlock_irqrestore(&ep->lock, flags); - if (!schedule_hrtimeout_range(to, slack, HRTIMER_MODE_ABS)) + if (!freezable_schedule_hrtimeout_range(to, slack, + HRTIMER_MODE_ABS)) timed_out = 1; spin_lock_irqsave(&ep->lock, flags); diff -ruw linux-4.4.115/fs/exec.c linux-4.4.115-fbx/fs/exec.c --- linux-4.4.115/fs/exec.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/fs/exec.c 2019-10-29 09:26:25.237218777 +0100 @@ -1153,8 +1153,10 @@ void would_dump(struct linux_binprm *bprm, struct file *file) { struct inode *inode = file_inode(file); - if (inode_permission(inode, MAY_READ) < 0) { + + if (inode_permission2(file->f_path.mnt, inode, MAY_READ) < 0) { struct user_namespace *old, *user_ns; + bprm->interp_flags |= BINPRM_FLAGS_ENFORCE_NONDUMP; /* Ensure mm->user_ns contains the executable */ @@ -1537,6 +1539,23 @@ return PTR_ERR(filename); /* + * handle current->exec_mode: + * - if unlimited, then nothing to do. + * - if once, then set it to denied and continue (next execve + * after this one will fail). + * - if denied, then effectively fail the execve call with EPERM. + */ + switch (current->exec_mode) { + case EXEC_MODE_UNLIMITED: + break; + case EXEC_MODE_ONCE: + current->exec_mode = EXEC_MODE_DENIED; + break; + case EXEC_MODE_DENIED: + return -EPERM; + } + + /* * We move the actual failure in case of RLIMIT_NPROC excess from * set*uid() to execve() because too many poorly written programs * don't check setuid() return code. Here we additionally recheck diff -ruw linux-4.4.115/fs/ext4/dir.c linux-4.4.115-fbx/fs/ext4/dir.c --- linux-4.4.115/fs/ext4/dir.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/fs/ext4/dir.c 2019-10-29 09:26:25.253218934 +0100 @@ -163,8 +163,11 @@ index, 1); file->f_ra.prev_pos = (loff_t)index << PAGE_CACHE_SHIFT; bh = ext4_bread(NULL, inode, map.m_lblk, 0); - if (IS_ERR(bh)) - return PTR_ERR(bh); + if (IS_ERR(bh)) { + err = PTR_ERR(bh); + bh = NULL; + goto errout; + } } if (!bh) { diff -ruw linux-4.4.115/fs/ext4/ext4_crypto.h linux-4.4.115-fbx/fs/ext4/ext4_crypto.h --- linux-4.4.115/fs/ext4/ext4_crypto.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/fs/ext4/ext4_crypto.h 2019-01-22 16:16:27.819285490 +0100 @@ -12,6 +12,7 @@ #define _EXT4_CRYPTO_H #include +#include #define EXT4_KEY_DESCRIPTOR_SIZE 8 @@ -58,9 +59,12 @@ #define EXT4_XTS_TWEAK_SIZE 16 #define EXT4_AES_128_ECB_KEY_SIZE 16 #define EXT4_AES_256_GCM_KEY_SIZE 32 +#define EXT4_AES_256_ECB_KEY_SIZE 32 #define EXT4_AES_256_CBC_KEY_SIZE 32 #define EXT4_AES_256_CTS_KEY_SIZE 32 +#define EXT4_AES_256_HEH_KEY_SIZE 32 #define EXT4_AES_256_XTS_KEY_SIZE 64 +#define EXT4_PRIVATE_KEY_SIZE 64 #define EXT4_MAX_KEY_SIZE 64 #define EXT4_KEY_DESC_PREFIX "ext4:" @@ -78,9 +82,13 @@ char ci_filename_mode; char ci_flags; struct crypto_ablkcipher *ci_ctfm; + struct key *ci_keyring_key; char ci_master_key[EXT4_KEY_DESCRIPTOR_SIZE]; + char ci_raw_key[EXT4_MAX_KEY_SIZE]; }; + + #define EXT4_CTX_REQUIRES_FREE_ENCRYPT_FL 0x00000001 #define EXT4_WRITE_PATH_FL 0x00000002 @@ -113,6 +121,7 @@ { switch (mode) { case EXT4_ENCRYPTION_MODE_AES_256_XTS: + case EXT4_ENCRYPTION_MODE_PRIVATE: return EXT4_AES_256_XTS_KEY_SIZE; case EXT4_ENCRYPTION_MODE_AES_256_GCM: return EXT4_AES_256_GCM_KEY_SIZE; @@ -120,6 +129,8 @@ return EXT4_AES_256_CBC_KEY_SIZE; case EXT4_ENCRYPTION_MODE_AES_256_CTS: return EXT4_AES_256_CTS_KEY_SIZE; + case EXT4_ENCRYPTION_MODE_AES_256_HEH: + return EXT4_AES_256_HEH_KEY_SIZE; default: BUG(); } diff -ruw linux-4.4.115/fs/ext4/ext4.h linux-4.4.115-fbx/fs/ext4/ext4.h --- linux-4.4.115/fs/ext4/ext4.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/fs/ext4/ext4.h 2019-10-29 09:26:25.253218934 +0100 @@ -589,6 +589,8 @@ #define EXT4_ENCRYPTION_MODE_AES_256_GCM 2 #define EXT4_ENCRYPTION_MODE_AES_256_CBC 3 #define EXT4_ENCRYPTION_MODE_AES_256_CTS 4 +#define EXT4_ENCRYPTION_MODE_PRIVATE 127 +#define EXT4_ENCRYPTION_MODE_AES_256_HEH 126 #include "ext4_crypto.h" @@ -1441,7 +1443,7 @@ struct list_head s_es_list; /* List of inodes with reclaimable extents */ long s_es_nr_inode; struct ext4_es_stats s_es_stats; - struct mb_cache *s_mb_cache; + struct mb2_cache *s_mb_cache; spinlock_t s_es_lock ____cacheline_aligned_in_smp; /* Ratelimit ext4 messages. */ @@ -2269,7 +2271,8 @@ struct page *plaintext_page, gfp_t gfp_flags); int ext4_decrypt(struct page *page); -int ext4_encrypted_zeroout(struct inode *inode, struct ext4_extent *ex); +int ext4_encrypted_zeroout(struct inode *inode, ext4_lblk_t lblk, + ext4_fsblk_t pblk, ext4_lblk_t len); extern const struct dentry_operations ext4_encrypted_d_ops; #ifdef CONFIG_EXT4_FS_ENCRYPTION @@ -2333,17 +2336,37 @@ /* crypto_key.c */ void ext4_free_crypt_info(struct ext4_crypt_info *ci); void ext4_free_encryption_info(struct inode *inode, struct ext4_crypt_info *ci); +int _ext4_get_encryption_info(struct inode *inode); #ifdef CONFIG_EXT4_FS_ENCRYPTION int ext4_has_encryption_key(struct inode *inode); -int ext4_get_encryption_info(struct inode *inode); +static inline int ext4_get_encryption_info(struct inode *inode) +{ + struct ext4_crypt_info *ci = EXT4_I(inode)->i_crypt_info; + + if (!ci || + (ci->ci_keyring_key && + (ci->ci_keyring_key->flags & ((1 << KEY_FLAG_INVALIDATED) | + (1 << KEY_FLAG_REVOKED) | + (1 << KEY_FLAG_DEAD))))) + return _ext4_get_encryption_info(inode); + return 0; +} static inline struct ext4_crypt_info *ext4_encryption_info(struct inode *inode) { return EXT4_I(inode)->i_crypt_info; } +static inline int ext4_using_hardware_encryption(struct inode *inode) +{ + struct ext4_crypt_info *ci = ext4_encryption_info(inode); + + return S_ISREG(inode->i_mode) && ci && + ci->ci_data_mode == EXT4_ENCRYPTION_MODE_PRIVATE; +} + #else static inline int ext4_has_encryption_key(struct inode *inode) { @@ -2357,6 +2380,10 @@ { return NULL; } +static inline int ext4_using_hardware_encryption(struct inode *inode) +{ + return 0; +} #endif @@ -2456,7 +2483,8 @@ ext4_group_t i, struct ext4_group_desc *desc); extern int ext4_group_add_blocks(handle_t *handle, struct super_block *sb, ext4_fsblk_t block, unsigned long count); -extern int ext4_trim_fs(struct super_block *, struct fstrim_range *); +extern int ext4_trim_fs(struct super_block *, struct fstrim_range *, + unsigned long blkdev_flags); /* inode.c */ int ext4_inode_is_fast_symlink(struct inode *inode); @@ -2512,6 +2540,8 @@ extern qsize_t *ext4_get_reserved_space(struct inode *inode); extern void ext4_da_update_reserve_space(struct inode *inode, int used, int quota_claim); +extern int ext4_issue_zeroout(struct inode *inode, ext4_lblk_t lblk, + ext4_fsblk_t pblk, ext4_lblk_t len); /* indirect.c */ extern int ext4_ind_map_blocks(handle_t *handle, struct inode *inode, @@ -3014,8 +3044,7 @@ struct page *page); extern int ext4_try_add_inline_entry(handle_t *handle, struct ext4_filename *fname, - struct dentry *dentry, - struct inode *inode); + struct inode *dir, struct inode *inode); extern int ext4_try_create_inline_dir(handle_t *handle, struct inode *parent, struct inode *inode); diff -ruw linux-4.4.115/fs/ext4/extents.c linux-4.4.115-fbx/fs/ext4/extents.c --- linux-4.4.115/fs/ext4/extents.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/fs/ext4/extents.c 2019-10-29 09:26:25.257218973 +0100 @@ -3127,19 +3127,11 @@ { ext4_fsblk_t ee_pblock; unsigned int ee_len; - int ret; ee_len = ext4_ext_get_actual_len(ex); ee_pblock = ext4_ext_pblock(ex); - - if (ext4_encrypted_inode(inode)) - return ext4_encrypted_zeroout(inode, ex); - - ret = sb_issue_zeroout(inode->i_sb, ee_pblock, ee_len, GFP_NOFS); - if (ret > 0) - ret = 0; - - return ret; + return ext4_issue_zeroout(inode, le32_to_cpu(ex->ee_block), ee_pblock, + ee_len); } /* diff -ruw linux-4.4.115/fs/ext4/inline.c linux-4.4.115-fbx/fs/ext4/inline.c --- linux-4.4.115/fs/ext4/inline.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/fs/ext4/inline.c 2019-10-29 09:26:25.257218973 +0100 @@ -18,6 +18,7 @@ #include "ext4.h" #include "xattr.h" #include "truncate.h" +#include #define EXT4_XATTR_SYSTEM_DATA "data" #define EXT4_MIN_INLINE_DATA_SIZE ((sizeof(__le32) * EXT4_N_BLOCKS)) @@ -502,6 +503,17 @@ return -EAGAIN; } + if (trace_android_fs_dataread_start_enabled()) { + char *path, pathbuf[MAX_TRACE_PATHBUF_LEN]; + + path = android_fstrace_get_pathname(pathbuf, + MAX_TRACE_PATHBUF_LEN, + inode); + trace_android_fs_dataread_start(inode, page_offset(page), + PAGE_SIZE, current->pid, + path, current->comm); + } + /* * Current inline data can only exist in the 1st page, * So for all the other pages, just set them uptodate. @@ -513,6 +525,8 @@ SetPageUptodate(page); } + trace_android_fs_dataread_end(inode, page_offset(page), PAGE_SIZE); + up_read(&EXT4_I(inode)->xattr_sem); unlock_page(page); @@ -1004,12 +1018,11 @@ */ static int ext4_add_dirent_to_inline(handle_t *handle, struct ext4_filename *fname, - struct dentry *dentry, + struct inode *dir, struct inode *inode, struct ext4_iloc *iloc, void *inline_start, int inline_size) { - struct inode *dir = d_inode(dentry->d_parent); int err; struct ext4_dir_entry_2 *de; @@ -1253,12 +1266,11 @@ * the new created block. */ int ext4_try_add_inline_entry(handle_t *handle, struct ext4_filename *fname, - struct dentry *dentry, struct inode *inode) + struct inode *dir, struct inode *inode) { int ret, inline_size; void *inline_start; struct ext4_iloc iloc; - struct inode *dir = d_inode(dentry->d_parent); ret = ext4_get_inode_loc(dir, &iloc); if (ret) @@ -1272,7 +1284,7 @@ EXT4_INLINE_DOTDOT_SIZE; inline_size = EXT4_MIN_INLINE_DATA_SIZE - EXT4_INLINE_DOTDOT_SIZE; - ret = ext4_add_dirent_to_inline(handle, fname, dentry, inode, &iloc, + ret = ext4_add_dirent_to_inline(handle, fname, dir, inode, &iloc, inline_start, inline_size); if (ret != -ENOSPC) goto out; @@ -1293,7 +1305,7 @@ if (inline_size) { inline_start = ext4_get_inline_xattr_pos(dir, &iloc); - ret = ext4_add_dirent_to_inline(handle, fname, dentry, + ret = ext4_add_dirent_to_inline(handle, fname, dir, inode, &iloc, inline_start, inline_size); diff -ruw linux-4.4.115/fs/ext4/inode.c linux-4.4.115-fbx/fs/ext4/inode.c --- linux-4.4.115/fs/ext4/inode.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/fs/ext4/inode.c 2019-10-29 09:26:25.261219012 +0100 @@ -42,8 +42,10 @@ #include "xattr.h" #include "acl.h" #include "truncate.h" +#include "ext4_ice.h" #include +#include #define MPAGE_DA_EXTENT_TAIL 0x01 @@ -388,6 +390,21 @@ return 0; } +int ext4_issue_zeroout(struct inode *inode, ext4_lblk_t lblk, ext4_fsblk_t pblk, + ext4_lblk_t len) +{ + int ret; + + if (ext4_encrypted_inode(inode)) + return ext4_encrypted_zeroout(inode, lblk, pblk, len); + + ret = sb_issue_zeroout(inode->i_sb, pblk, len, GFP_NOFS); + if (ret > 0) + ret = 0; + + return ret; +} + #define check_block_validity(inode, map) \ __check_block_validity((inode), __func__, __LINE__, (map)) @@ -998,7 +1015,8 @@ ll_rw_block(READ, 1, &bh); *wait_bh++ = bh; decrypt = ext4_encrypted_inode(inode) && - S_ISREG(inode->i_mode); + S_ISREG(inode->i_mode) && + !ext4_is_ice_enabled(); } } /* @@ -1029,6 +1047,16 @@ pgoff_t index; unsigned from, to; + if (trace_android_fs_datawrite_start_enabled()) { + char *path, pathbuf[MAX_TRACE_PATHBUF_LEN]; + + path = android_fstrace_get_pathname(pathbuf, + MAX_TRACE_PATHBUF_LEN, + inode); + trace_android_fs_datawrite_start(inode, pos, len, + current->pid, path, + current->comm); + } trace_ext4_write_begin(inode, pos, len, flags); /* * Reserve one block more for addition to orphan list in case @@ -1165,6 +1193,7 @@ int ret = 0, ret2; int i_size_changed = 0; + trace_android_fs_datawrite_end(inode, pos, len); trace_ext4_write_end(inode, pos, len, copied); if (ext4_has_inline_data(inode)) { ret = ext4_write_inline_data_end(inode, pos, len, @@ -1269,6 +1298,7 @@ unsigned from, to; int size_changed = 0; + trace_android_fs_datawrite_end(inode, pos, len); trace_ext4_journalled_write_end(inode, pos, len, copied); from = pos & (PAGE_CACHE_SIZE - 1); to = from + len; @@ -2758,6 +2788,16 @@ len, flags, pagep, fsdata); } *fsdata = (void *)0; + if (trace_android_fs_datawrite_start_enabled()) { + char *path, pathbuf[MAX_TRACE_PATHBUF_LEN]; + + path = android_fstrace_get_pathname(pathbuf, + MAX_TRACE_PATHBUF_LEN, + inode); + trace_android_fs_datawrite_start(inode, pos, len, + current->pid, + path, current->comm); + } trace_ext4_da_write_begin(inode, pos, len, flags); if (ext4_test_inode_state(inode, EXT4_STATE_MAY_INLINE_DATA)) { @@ -2876,6 +2916,7 @@ return ext4_write_end(file, mapping, pos, len, copied, page, fsdata); + trace_android_fs_datawrite_end(inode, pos, len); trace_ext4_da_write_end(inode, pos, len, copied); start = pos & (PAGE_CACHE_SIZE - 1); end = start + copied - 1; @@ -3282,7 +3323,9 @@ get_block_func = ext4_get_block_write; dio_flags = DIO_LOCKING; } -#ifdef CONFIG_EXT4_FS_ENCRYPTION +#if defined(CONFIG_EXT4_FS_ENCRYPTION) && \ +!defined(CONFIG_EXT4_FS_ICE_ENCRYPTION) + BUG_ON(ext4_encrypted_inode(inode) && S_ISREG(inode->i_mode)); #endif if (IS_DAX(inode)) @@ -3349,7 +3392,9 @@ size_t count = iov_iter_count(iter); ssize_t ret; -#ifdef CONFIG_EXT4_FS_ENCRYPTION +#if defined(CONFIG_EXT4_FS_ENCRYPTION) && \ +!defined(CONFIG_EXT4_FS_ICE_ENCRYPTION) + if (ext4_encrypted_inode(inode) && S_ISREG(inode->i_mode)) return 0; #endif @@ -3364,12 +3409,42 @@ if (ext4_has_inline_data(inode)) return 0; + if (trace_android_fs_dataread_start_enabled() && + (iov_iter_rw(iter) == READ)) { + char *path, pathbuf[MAX_TRACE_PATHBUF_LEN]; + + path = android_fstrace_get_pathname(pathbuf, + MAX_TRACE_PATHBUF_LEN, + inode); + trace_android_fs_dataread_start(inode, offset, count, + current->pid, path, + current->comm); + } + if (trace_android_fs_datawrite_start_enabled() && + (iov_iter_rw(iter) == WRITE)) { + char *path, pathbuf[MAX_TRACE_PATHBUF_LEN]; + + path = android_fstrace_get_pathname(pathbuf, + MAX_TRACE_PATHBUF_LEN, + inode); + trace_android_fs_datawrite_start(inode, offset, count, + current->pid, path, + current->comm); + } trace_ext4_direct_IO_enter(inode, offset, count, iov_iter_rw(iter)); if (ext4_test_inode_flag(inode, EXT4_INODE_EXTENTS)) ret = ext4_ext_direct_IO(iocb, iter, offset); else ret = ext4_ind_direct_IO(iocb, iter, offset); trace_ext4_direct_IO_exit(inode, offset, count, iov_iter_rw(iter), ret); + + if (trace_android_fs_dataread_start_enabled() && + (iov_iter_rw(iter) == READ)) + trace_android_fs_dataread_end(inode, offset, count); + if (trace_android_fs_datawrite_start_enabled() && + (iov_iter_rw(iter) == WRITE)) + trace_android_fs_datawrite_end(inode, offset, count); + return ret; } @@ -3519,7 +3594,8 @@ if (!buffer_uptodate(bh)) goto unlock; if (S_ISREG(inode->i_mode) && - ext4_encrypted_inode(inode)) { + ext4_encrypted_inode(inode) && + !ext4_using_hardware_encryption(inode)) { /* We expect the key to be set. */ BUG_ON(!ext4_has_encryption_key(inode)); BUG_ON(blocksize != PAGE_CACHE_SIZE); @@ -3692,6 +3768,7 @@ int ext4_punch_hole(struct inode *inode, loff_t offset, loff_t length) { +#if 0 struct super_block *sb = inode->i_sb; ext4_lblk_t first_block, stop_block; struct address_space *mapping = inode->i_mapping; @@ -3822,6 +3899,12 @@ out_mutex: mutex_unlock(&inode->i_mutex); return ret; +#else + /* + * Disabled as per b/28760453 + */ + return -EOPNOTSUPP; +#endif } int ext4_inode_attach_jinode(struct inode *inode) @@ -4140,8 +4223,11 @@ new_fl |= S_DIRSYNC; if (test_opt(inode->i_sb, DAX)) new_fl |= S_DAX; + if (flags & EXT4_ENCRYPT_FL) + new_fl |= S_ENCRYPTED; inode_set_flags(inode, new_fl, - S_SYNC|S_APPEND|S_IMMUTABLE|S_NOATIME|S_DIRSYNC|S_DAX); + S_SYNC|S_APPEND|S_IMMUTABLE|S_NOATIME|S_DIRSYNC|S_DAX| + S_ENCRYPTED); } /* Propagate flags from i_flags to EXT4_I(inode)->i_flags */ diff -ruw linux-4.4.115/fs/ext4/ioctl.c linux-4.4.115-fbx/fs/ext4/ioctl.c --- linux-4.4.115/fs/ext4/ioctl.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/fs/ext4/ioctl.c 2019-10-29 09:26:25.261219012 +0100 @@ -587,11 +587,13 @@ return err; } + case FIDTRIM: case FITRIM: { struct request_queue *q = bdev_get_queue(sb->s_bdev); struct fstrim_range range; int ret = 0; + int flags = cmd == FIDTRIM ? BLKDEV_DISCARD_SECURE : 0; if (!capable(CAP_SYS_ADMIN)) return -EPERM; @@ -599,13 +601,15 @@ if (!blk_queue_discard(q)) return -EOPNOTSUPP; + if ((flags & BLKDEV_DISCARD_SECURE) && !blk_queue_secdiscard(q)) + return -EOPNOTSUPP; if (copy_from_user(&range, (struct fstrim_range __user *)arg, sizeof(range))) return -EFAULT; range.minlen = max((unsigned int)range.minlen, q->limits.discard_granularity); - ret = ext4_trim_fs(sb, &range); + ret = ext4_trim_fs(sb, &range, flags); if (ret < 0) return ret; @@ -622,9 +626,6 @@ struct ext4_encryption_policy policy; int err = 0; - if (!ext4_has_feature_encrypt(sb)) - return -EOPNOTSUPP; - if (copy_from_user(&policy, (struct ext4_encryption_policy __user *)arg, sizeof(policy))) { diff -ruw linux-4.4.115/fs/ext4/Kconfig linux-4.4.115-fbx/fs/ext4/Kconfig --- linux-4.4.115/fs/ext4/Kconfig 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/fs/ext4/Kconfig 2019-01-22 16:16:27.815285454 +0100 @@ -106,6 +106,7 @@ select CRYPTO_ECB select CRYPTO_XTS select CRYPTO_CTS + select CRYPTO_HEH select CRYPTO_CTR select CRYPTO_SHA256 select KEYS @@ -117,10 +118,16 @@ decrypted pages in the page cache. config EXT4_FS_ENCRYPTION - bool - default y + bool "Ext4 FS Encryption" + default n depends on EXT4_ENCRYPTION +config EXT4_FS_ICE_ENCRYPTION + bool "Ext4 Encryption with ICE support" + default n + depends on EXT4_FS_ENCRYPTION + depends on PFK + config EXT4_DEBUG bool "EXT4 debugging support" depends on EXT4_FS diff -ruw linux-4.4.115/fs/ext4/Makefile linux-4.4.115-fbx/fs/ext4/Makefile --- linux-4.4.115/fs/ext4/Makefile 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/fs/ext4/Makefile 2019-01-22 16:16:27.815285454 +0100 @@ -14,3 +14,5 @@ ext4-$(CONFIG_EXT4_FS_SECURITY) += xattr_security.o ext4-$(CONFIG_EXT4_FS_ENCRYPTION) += crypto_policy.o crypto.o \ crypto_key.o crypto_fname.o + +ext4-$(CONFIG_EXT4_FS_ICE_ENCRYPTION) += ext4_ice.o diff -ruw linux-4.4.115/fs/ext4/mballoc.c linux-4.4.115-fbx/fs/ext4/mballoc.c --- linux-4.4.115/fs/ext4/mballoc.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/fs/ext4/mballoc.c 2019-10-29 09:26:25.261219012 +0100 @@ -2772,7 +2772,8 @@ } static inline int ext4_issue_discard(struct super_block *sb, - ext4_group_t block_group, ext4_grpblk_t cluster, int count) + ext4_group_t block_group, ext4_grpblk_t cluster, int count, + unsigned long flags) { ext4_fsblk_t discard_block; @@ -2781,7 +2782,7 @@ count = EXT4_C2B(EXT4_SB(sb), count); trace_ext4_discard_blocks(sb, (unsigned long long) discard_block, count); - return sb_issue_discard(sb, discard_block, count, GFP_NOFS, 0); + return sb_issue_discard(sb, discard_block, count, GFP_NOFS, flags); } /* @@ -2803,7 +2804,7 @@ if (test_opt(sb, DISCARD)) { err = ext4_issue_discard(sb, entry->efd_group, entry->efd_start_cluster, - entry->efd_count); + entry->efd_count, 0); if (err && err != -EOPNOTSUPP) ext4_msg(sb, KERN_WARNING, "discard request in" " group:%d block:%d count:%d failed" @@ -4855,7 +4856,8 @@ * them with group lock_held */ if (test_opt(sb, DISCARD)) { - err = ext4_issue_discard(sb, block_group, bit, count); + err = ext4_issue_discard(sb, block_group, bit, count, + 0); if (err && err != -EOPNOTSUPP) ext4_msg(sb, KERN_WARNING, "discard request in" " group:%d block:%d count:%lu failed" @@ -5051,13 +5053,15 @@ * @count: number of blocks to TRIM * @group: alloc. group we are working with * @e4b: ext4 buddy for the group + * @blkdev_flags: flags for the block device * * Trim "count" blocks starting at "start" in the "group". To assure that no * one will allocate those blocks, mark it as used in buddy bitmap. This must * be called with under the group lock. */ static int ext4_trim_extent(struct super_block *sb, int start, int count, - ext4_group_t group, struct ext4_buddy *e4b) + ext4_group_t group, struct ext4_buddy *e4b, + unsigned long blkdev_flags) __releases(bitlock) __acquires(bitlock) { @@ -5078,7 +5082,7 @@ */ mb_mark_used(e4b, &ex); ext4_unlock_group(sb, group); - ret = ext4_issue_discard(sb, group, start, count); + ret = ext4_issue_discard(sb, group, start, count, blkdev_flags); ext4_lock_group(sb, group); mb_free_blocks(NULL, e4b, start, ex.fe_len); return ret; @@ -5091,6 +5095,7 @@ * @start: first group block to examine * @max: last group block to examine * @minblocks: minimum extent block count + * @blkdev_flags: flags for the block device * * ext4_trim_all_free walks through group's buddy bitmap searching for free * extents. When the free block is found, ext4_trim_extent is called to TRIM @@ -5105,7 +5110,7 @@ static ext4_grpblk_t ext4_trim_all_free(struct super_block *sb, ext4_group_t group, ext4_grpblk_t start, ext4_grpblk_t max, - ext4_grpblk_t minblocks) + ext4_grpblk_t minblocks, unsigned long blkdev_flags) { void *bitmap; ext4_grpblk_t next, count = 0, free_count = 0; @@ -5138,7 +5143,8 @@ if ((next - start) >= minblocks) { ret = ext4_trim_extent(sb, start, - next - start, group, &e4b); + next - start, group, &e4b, + blkdev_flags); if (ret && ret != -EOPNOTSUPP) break; ret = 0; @@ -5180,6 +5186,7 @@ * ext4_trim_fs() -- trim ioctl handle function * @sb: superblock for filesystem * @range: fstrim_range structure + * @blkdev_flags: flags for the block device * * start: First Byte to trim * len: number of Bytes to trim from start @@ -5188,7 +5195,8 @@ * start to start+len. For each such a group ext4_trim_all_free function * is invoked to trim all free space. */ -int ext4_trim_fs(struct super_block *sb, struct fstrim_range *range) +int ext4_trim_fs(struct super_block *sb, struct fstrim_range *range, + unsigned long blkdev_flags) { struct ext4_group_info *grp; ext4_group_t group, first_group, last_group; @@ -5244,7 +5252,7 @@ if (grp->bb_free >= minlen) { cnt = ext4_trim_all_free(sb, group, first_cluster, - end, minlen); + end, minlen, blkdev_flags); if (cnt < 0) { ret = cnt; break; diff -ruw linux-4.4.115/fs/ext4/namei.c linux-4.4.115-fbx/fs/ext4/namei.c --- linux-4.4.115/fs/ext4/namei.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/fs/ext4/namei.c 2019-10-29 09:26:25.265219051 +0100 @@ -273,7 +273,7 @@ struct ext4_filename *fname, struct ext4_dir_entry_2 **res_dir); static int ext4_dx_add_entry(handle_t *handle, struct ext4_filename *fname, - struct dentry *dentry, struct inode *inode); + struct inode *dir, struct inode *inode); /* checksumming functions */ void initialize_dirent_tail(struct ext4_dir_entry_tail *t, @@ -1949,10 +1949,9 @@ * directory, and adds the dentry to the indexed directory. */ static int make_indexed_dir(handle_t *handle, struct ext4_filename *fname, - struct dentry *dentry, + struct inode *dir, struct inode *inode, struct buffer_head *bh) { - struct inode *dir = d_inode(dentry->d_parent); struct buffer_head *bh2; struct dx_root *root; struct dx_frame frames[2], *frame; @@ -2105,8 +2104,7 @@ return retval; if (ext4_has_inline_data(dir)) { - retval = ext4_try_add_inline_entry(handle, &fname, - dentry, inode); + retval = ext4_try_add_inline_entry(handle, &fname, dir, inode); if (retval < 0) goto out; if (retval == 1) { @@ -2116,7 +2114,7 @@ } if (is_dx(dir)) { - retval = ext4_dx_add_entry(handle, &fname, dentry, inode); + retval = ext4_dx_add_entry(handle, &fname, dir, inode); if (!retval || (retval != ERR_BAD_DX_DIR)) goto out; ext4_clear_inode_flag(dir, EXT4_INODE_INDEX); @@ -2138,7 +2136,7 @@ if (blocks == 1 && !dx_fallback && ext4_has_feature_dir_index(sb)) { - retval = make_indexed_dir(handle, &fname, dentry, + retval = make_indexed_dir(handle, &fname, dir, inode, bh); bh = NULL; /* make_indexed_dir releases bh */ goto out; @@ -2173,12 +2171,11 @@ * Returns 0 for success, or a negative error value */ static int ext4_dx_add_entry(handle_t *handle, struct ext4_filename *fname, - struct dentry *dentry, struct inode *inode) + struct inode *dir, struct inode *inode) { struct dx_frame frames[2], *frame; struct dx_entry *entries, *at; struct buffer_head *bh; - struct inode *dir = d_inode(dentry->d_parent); struct super_block *sb = dir->i_sb; struct ext4_dir_entry_2 *de; int err; diff -ruw linux-4.4.115/fs/ext4/page-io.c linux-4.4.115-fbx/fs/ext4/page-io.c --- linux-4.4.115/fs/ext4/page-io.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/fs/ext4/page-io.c 2019-01-22 16:16:27.831285599 +0100 @@ -28,6 +28,7 @@ #include "ext4_jbd2.h" #include "xattr.h" #include "acl.h" +#include "ext4_ice.h" static struct kmem_cache *io_end_cachep; @@ -489,7 +490,11 @@ gfp_t gfp_flags = GFP_NOFS; retry_encrypt: + + if (!ext4_using_hardware_encryption(inode)) data_page = ext4_encrypt(inode, page, gfp_flags); + + if (IS_ERR(data_page)) { ret = PTR_ERR(data_page); if (ret == -ENOMEM && wbc->sync_mode == WB_SYNC_ALL) { diff -ruw linux-4.4.115/fs/ext4/readpage.c linux-4.4.115-fbx/fs/ext4/readpage.c --- linux-4.4.115/fs/ext4/readpage.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/fs/ext4/readpage.c 2019-01-22 16:16:27.831285599 +0100 @@ -45,6 +45,8 @@ #include #include "ext4.h" +#include "ext4_ice.h" +#include /* * Call ext4_decrypt on every single page, reusing the encryption @@ -62,12 +64,17 @@ bio_for_each_segment_all(bv, bio, i) { struct page *page = bv->bv_page; + if (ext4_is_ice_enabled()) { + SetPageUptodate(page); + } else { int ret = ext4_decrypt(page); + if (ret) { WARN_ON_ONCE(1); SetPageError(page); } else SetPageUptodate(page); + } unlock_page(page); } ext4_release_crypto_ctx(ctx); @@ -86,6 +93,17 @@ #endif } +static void +ext4_trace_read_completion(struct bio *bio) +{ + struct page *first_page = bio->bi_io_vec[0].bv_page; + + if (first_page != NULL) + trace_android_fs_dataread_end(first_page->mapping->host, + page_offset(first_page), + bio->bi_iter.bi_size); +} + /* * I/O completion handler for multipage BIOs. * @@ -103,6 +121,9 @@ struct bio_vec *bv; int i; + if (trace_android_fs_dataread_start_enabled()) + ext4_trace_read_completion(bio); + if (ext4_bio_encrypted(bio)) { struct ext4_crypto_ctx *ctx = bio->bi_private; @@ -130,6 +151,30 @@ bio_put(bio); } +static void +ext4_submit_bio_read(struct bio *bio) +{ + if (trace_android_fs_dataread_start_enabled()) { + struct page *first_page = bio->bi_io_vec[0].bv_page; + + if (first_page != NULL) { + char *path, pathbuf[MAX_TRACE_PATHBUF_LEN]; + + path = android_fstrace_get_pathname(pathbuf, + MAX_TRACE_PATHBUF_LEN, + first_page->mapping->host); + trace_android_fs_dataread_start( + first_page->mapping->host, + page_offset(first_page), + bio->bi_iter.bi_size, + current->pid, + path, + current->comm); + } + } + submit_bio(READ, bio); +} + int ext4_mpage_readpages(struct address_space *mapping, struct list_head *pages, struct page *page, unsigned nr_pages) @@ -271,7 +316,7 @@ */ if (bio && (last_block_in_bio != blocks[0] - 1)) { submit_and_realloc: - submit_bio(READ, bio); + ext4_submit_bio_read(bio); bio = NULL; } if (bio == NULL) { @@ -303,14 +348,14 @@ if (((map.m_flags & EXT4_MAP_BOUNDARY) && (relative_block == map.m_len)) || (first_hole != blocks_per_page)) { - submit_bio(READ, bio); + ext4_submit_bio_read(bio); bio = NULL; } else last_block_in_bio = blocks[blocks_per_page - 1]; goto next_page; confused: if (bio) { - submit_bio(READ, bio); + ext4_submit_bio_read(bio); bio = NULL; } if (!PageUptodate(page)) @@ -323,6 +368,6 @@ } BUG_ON(pages && !list_empty(pages)); if (bio) - submit_bio(READ, bio); + ext4_submit_bio_read(bio); return 0; } diff -ruw linux-4.4.115/fs/ext4/super.c linux-4.4.115-fbx/fs/ext4/super.c --- linux-4.4.115/fs/ext4/super.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/fs/ext4/super.c 2019-10-29 09:26:25.265219051 +0100 @@ -816,7 +816,6 @@ ext4_release_system_zone(sb); ext4_mb_release(sb); ext4_ext_release(sb); - ext4_xattr_put_super(sb); if (!(sb->s_flags & MS_RDONLY) && !aborted) { ext4_clear_feature_journal_needs_recovery(sb); @@ -3854,7 +3853,7 @@ no_journal: if (ext4_mballoc_ready) { - sbi->s_mb_cache = ext4_xattr_create_cache(sb->s_id); + sbi->s_mb_cache = ext4_xattr_create_cache(); if (!sbi->s_mb_cache) { ext4_msg(sb, KERN_ERR, "Failed to create an mb_cache"); goto failed_mount_wq; @@ -4086,6 +4085,10 @@ if (EXT4_SB(sb)->rsv_conversion_wq) destroy_workqueue(EXT4_SB(sb)->rsv_conversion_wq); failed_mount_wq: + if (sbi->s_mb_cache) { + ext4_xattr_destroy_cache(sbi->s_mb_cache); + sbi->s_mb_cache = NULL; + } if (sbi->s_journal) { jbd2_journal_destroy(sbi->s_journal); sbi->s_journal = NULL; diff -ruw linux-4.4.115/fs/ext4/xattr.c linux-4.4.115-fbx/fs/ext4/xattr.c --- linux-4.4.115/fs/ext4/xattr.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/fs/ext4/xattr.c 2019-10-29 09:26:25.269219090 +0100 @@ -53,7 +53,7 @@ #include #include #include -#include +#include #include #include "ext4_jbd2.h" #include "ext4.h" @@ -80,10 +80,10 @@ # define ea_bdebug(bh, fmt, ...) no_printk(fmt, ##__VA_ARGS__) #endif -static void ext4_xattr_cache_insert(struct mb_cache *, struct buffer_head *); +static void ext4_xattr_cache_insert(struct mb2_cache *, struct buffer_head *); static struct buffer_head *ext4_xattr_cache_find(struct inode *, struct ext4_xattr_header *, - struct mb_cache_entry **); + struct mb2_cache_entry **); static void ext4_xattr_rehash(struct ext4_xattr_header *, struct ext4_xattr_entry *); static int ext4_xattr_list(struct dentry *dentry, char *buffer, @@ -300,7 +300,7 @@ struct ext4_xattr_entry *entry; size_t size; int error; - struct mb_cache *ext4_mb_cache = EXT4_GET_MB_CACHE(inode); + struct mb2_cache *ext4_mb_cache = EXT4_GET_MB_CACHE(inode); ea_idebug(inode, "name=%d.%s, buffer=%p, buffer_size=%ld", name_index, name, buffer, (long)buffer_size); @@ -447,7 +447,7 @@ struct inode *inode = d_inode(dentry); struct buffer_head *bh = NULL; int error; - struct mb_cache *ext4_mb_cache = EXT4_GET_MB_CACHE(inode); + struct mb2_cache *ext4_mb_cache = EXT4_GET_MB_CACHE(inode); ea_idebug(inode, "buffer=%p, buffer_size=%ld", buffer, (long)buffer_size); @@ -564,11 +564,8 @@ ext4_xattr_release_block(handle_t *handle, struct inode *inode, struct buffer_head *bh) { - struct mb_cache_entry *ce = NULL; int error = 0; - struct mb_cache *ext4_mb_cache = EXT4_GET_MB_CACHE(inode); - ce = mb_cache_entry_get(ext4_mb_cache, bh->b_bdev, bh->b_blocknr); BUFFER_TRACE(bh, "get_write_access"); error = ext4_journal_get_write_access(handle, bh); if (error) @@ -576,9 +573,15 @@ lock_buffer(bh); if (BHDR(bh)->h_refcount == cpu_to_le32(1)) { + __u32 hash = le32_to_cpu(BHDR(bh)->h_hash); + ea_bdebug(bh, "refcount now=0; freeing"); - if (ce) - mb_cache_entry_free(ce); + /* + * This must happen under buffer lock for + * ext4_xattr_block_set() to reliably detect freed block + */ + mb2_cache_entry_delete_block(EXT4_GET_MB_CACHE(inode), hash, + bh->b_blocknr); get_bh(bh); unlock_buffer(bh); ext4_free_blocks(handle, inode, bh, 0, 1, @@ -586,8 +589,6 @@ EXT4_FREE_BLOCKS_FORGET); } else { le32_add_cpu(&BHDR(bh)->h_refcount, -1); - if (ce) - mb_cache_entry_release(ce); /* * Beware of this ugliness: Releasing of xattr block references * from different inodes can race and so we have to protect @@ -800,17 +801,15 @@ struct super_block *sb = inode->i_sb; struct buffer_head *new_bh = NULL; struct ext4_xattr_search *s = &bs->s; - struct mb_cache_entry *ce = NULL; + struct mb2_cache_entry *ce = NULL; int error = 0; - struct mb_cache *ext4_mb_cache = EXT4_GET_MB_CACHE(inode); + struct mb2_cache *ext4_mb_cache = EXT4_GET_MB_CACHE(inode); #define header(x) ((struct ext4_xattr_header *)(x)) if (i->value && i->value_len > sb->s_blocksize) return -ENOSPC; if (s->base) { - ce = mb_cache_entry_get(ext4_mb_cache, bs->bh->b_bdev, - bs->bh->b_blocknr); BUFFER_TRACE(bs->bh, "get_write_access"); error = ext4_journal_get_write_access(handle, bs->bh); if (error) @@ -818,10 +817,15 @@ lock_buffer(bs->bh); if (header(s->base)->h_refcount == cpu_to_le32(1)) { - if (ce) { - mb_cache_entry_free(ce); - ce = NULL; - } + __u32 hash = le32_to_cpu(BHDR(bs->bh)->h_hash); + + /* + * This must happen under buffer lock for + * ext4_xattr_block_set() to reliably detect modified + * block + */ + mb2_cache_entry_delete_block(ext4_mb_cache, hash, + bs->bh->b_blocknr); ea_bdebug(bs->bh, "modifying in-place"); error = ext4_xattr_set_entry(i, s); if (!error) { @@ -845,10 +849,6 @@ int offset = (char *)s->here - bs->bh->b_data; unlock_buffer(bs->bh); - if (ce) { - mb_cache_entry_release(ce); - ce = NULL; - } ea_bdebug(bs->bh, "cloning"); s->base = kmalloc(bs->bh->b_size, GFP_NOFS); error = -ENOMEM; @@ -903,6 +903,31 @@ if (error) goto cleanup_dquot; lock_buffer(new_bh); + /* + * We have to be careful about races with + * freeing or rehashing of xattr block. Once we + * hold buffer lock xattr block's state is + * stable so we can check whether the block got + * freed / rehashed or not. Since we unhash + * mbcache entry under buffer lock when freeing + * / rehashing xattr block, checking whether + * entry is still hashed is reliable. + */ + if (hlist_bl_unhashed(&ce->e_hash_list)) { + /* + * Undo everything and check mbcache + * again. + */ + unlock_buffer(new_bh); + dquot_free_block(inode, + EXT4_C2B(EXT4_SB(sb), + 1)); + brelse(new_bh); + mb2_cache_entry_put(ext4_mb_cache, ce); + ce = NULL; + new_bh = NULL; + goto inserted; + } le32_add_cpu(&BHDR(new_bh)->h_refcount, 1); ea_bdebug(new_bh, "reusing; refcount now=%d", le32_to_cpu(BHDR(new_bh)->h_refcount)); @@ -913,7 +938,8 @@ if (error) goto cleanup_dquot; } - mb_cache_entry_release(ce); + mb2_cache_entry_touch(ext4_mb_cache, ce); + mb2_cache_entry_put(ext4_mb_cache, ce); ce = NULL; } else if (bs->bh && s->base == bs->bh->b_data) { /* We were modifying this block in-place. */ @@ -978,7 +1004,7 @@ cleanup: if (ce) - mb_cache_entry_release(ce); + mb2_cache_entry_put(ext4_mb_cache, ce); brelse(new_bh); if (!(bs->bh && s->base == bs->bh->b_data)) kfree(s->base); @@ -1543,17 +1569,6 @@ } /* - * ext4_xattr_put_super() - * - * This is called when a file system is unmounted. - */ -void -ext4_xattr_put_super(struct super_block *sb) -{ - mb_cache_shrink(sb->s_bdev); -} - -/* * ext4_xattr_cache_insert() * * Create a new entry in the extended attribute cache, and insert @@ -1562,28 +1577,18 @@ * Returns 0, or a negative error number on failure. */ static void -ext4_xattr_cache_insert(struct mb_cache *ext4_mb_cache, struct buffer_head *bh) +ext4_xattr_cache_insert(struct mb2_cache *ext4_mb_cache, struct buffer_head *bh) { __u32 hash = le32_to_cpu(BHDR(bh)->h_hash); - struct mb_cache_entry *ce; int error; - ce = mb_cache_entry_alloc(ext4_mb_cache, GFP_NOFS); - if (!ce) { - ea_bdebug(bh, "out of memory"); - return; - } - error = mb_cache_entry_insert(ce, bh->b_bdev, bh->b_blocknr, hash); + error = mb2_cache_entry_create(ext4_mb_cache, GFP_NOFS, hash, + bh->b_blocknr); if (error) { - mb_cache_entry_free(ce); - if (error == -EBUSY) { + if (error == -EBUSY) ea_bdebug(bh, "already in cache"); - error = 0; - } - } else { + } else ea_bdebug(bh, "inserting [%x]", (int)hash); - mb_cache_entry_release(ce); - } } /* @@ -1636,26 +1641,19 @@ */ static struct buffer_head * ext4_xattr_cache_find(struct inode *inode, struct ext4_xattr_header *header, - struct mb_cache_entry **pce) + struct mb2_cache_entry **pce) { __u32 hash = le32_to_cpu(header->h_hash); - struct mb_cache_entry *ce; - struct mb_cache *ext4_mb_cache = EXT4_GET_MB_CACHE(inode); + struct mb2_cache_entry *ce; + struct mb2_cache *ext4_mb_cache = EXT4_GET_MB_CACHE(inode); if (!header->h_hash) return NULL; /* never share */ ea_idebug(inode, "looking for cached blocks [%x]", (int)hash); -again: - ce = mb_cache_entry_find_first(ext4_mb_cache, inode->i_sb->s_bdev, - hash); + ce = mb2_cache_entry_find_first(ext4_mb_cache, hash); while (ce) { struct buffer_head *bh; - if (IS_ERR(ce)) { - if (PTR_ERR(ce) == -EAGAIN) - goto again; - break; - } bh = sb_bread(inode->i_sb, ce->e_block); if (!bh) { EXT4_ERROR_INODE(inode, "block %lu read error", @@ -1671,7 +1669,7 @@ return bh; } brelse(bh); - ce = mb_cache_entry_find_next(ce, inode->i_sb->s_bdev, hash); + ce = mb2_cache_entry_find_next(ext4_mb_cache, ce); } return NULL; } @@ -1746,15 +1744,15 @@ #define HASH_BUCKET_BITS 10 -struct mb_cache * -ext4_xattr_create_cache(char *name) +struct mb2_cache * +ext4_xattr_create_cache(void) { - return mb_cache_create(name, HASH_BUCKET_BITS); + return mb2_cache_create(HASH_BUCKET_BITS); } -void ext4_xattr_destroy_cache(struct mb_cache *cache) +void ext4_xattr_destroy_cache(struct mb2_cache *cache) { if (cache) - mb_cache_destroy(cache); + mb2_cache_destroy(cache); } diff -ruw linux-4.4.115/fs/ext4/xattr.h linux-4.4.115-fbx/fs/ext4/xattr.h --- linux-4.4.115/fs/ext4/xattr.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/fs/ext4/xattr.h 2019-10-29 09:26:25.269219090 +0100 @@ -108,7 +108,6 @@ extern int ext4_xattr_set_handle(handle_t *, struct inode *, int, const char *, const void *, size_t, int); extern void ext4_xattr_delete_inode(handle_t *, struct inode *); -extern void ext4_xattr_put_super(struct super_block *); extern int ext4_expand_extra_isize_ea(struct inode *inode, int new_extra_isize, struct ext4_inode *raw_inode, handle_t *handle); @@ -124,8 +123,8 @@ struct ext4_xattr_info *i, struct ext4_xattr_ibody_find *is); -extern struct mb_cache *ext4_xattr_create_cache(char *name); -extern void ext4_xattr_destroy_cache(struct mb_cache *); +extern struct mb2_cache *ext4_xattr_create_cache(void); +extern void ext4_xattr_destroy_cache(struct mb2_cache *); #ifdef CONFIG_EXT4_FS_SECURITY extern int ext4_init_security(handle_t *handle, struct inode *inode, diff -ruw linux-4.4.115/fs/f2fs/Kconfig linux-4.4.115-fbx/fs/f2fs/Kconfig --- linux-4.4.115/fs/f2fs/Kconfig 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/fs/f2fs/Kconfig 2019-01-22 16:16:27.835285635 +0100 @@ -1,6 +1,8 @@ config F2FS_FS tristate "F2FS filesystem support" depends on BLOCK + select CRYPTO + select CRYPTO_CRC32 help F2FS is based on Log-structured File System (LFS), which supports versatile "flash-friendly" features. The design has been focused on @@ -76,15 +78,7 @@ bool "F2FS Encryption" depends on F2FS_FS depends on F2FS_FS_XATTR - select CRYPTO_AES - select CRYPTO_CBC - select CRYPTO_ECB - select CRYPTO_XTS - select CRYPTO_CTS - select CRYPTO_CTR - select CRYPTO_SHA256 - select KEYS - select ENCRYPTED_KEYS + select FS_ENCRYPTION help Enable encryption of f2fs files and directories. This feature is similar to ecryptfs, but it is more memory @@ -100,3 +94,11 @@ information and block IO patterns in the filesystem level. If unsure, say N. + +config F2FS_FAULT_INJECTION + bool "F2FS fault injection facility" + depends on F2FS_FS + help + Test F2FS to inject faults such as ENOMEM, ENOSPC, and so on. + + If unsure, say N. diff -ruw linux-4.4.115/fs/f2fs/Makefile linux-4.4.115-fbx/fs/f2fs/Makefile --- linux-4.4.115/fs/f2fs/Makefile 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/fs/f2fs/Makefile 2019-01-22 16:16:27.835285635 +0100 @@ -2,10 +2,8 @@ f2fs-y := dir.o file.o inode.o namei.o hash.o super.o inline.o f2fs-y += checkpoint.o gc.o data.o node.o segment.o recovery.o -f2fs-y += shrinker.o extent_cache.o +f2fs-y += shrinker.o extent_cache.o sysfs.o f2fs-$(CONFIG_F2FS_STAT_FS) += debug.o f2fs-$(CONFIG_F2FS_FS_XATTR) += xattr.o f2fs-$(CONFIG_F2FS_FS_POSIX_ACL) += acl.o f2fs-$(CONFIG_F2FS_IO_TRACE) += trace.o -f2fs-$(CONFIG_F2FS_FS_ENCRYPTION) += crypto_policy.o crypto.o \ - crypto_key.o crypto_fname.o diff -ruw linux-4.4.115/fs/fat/fatent.c linux-4.4.115-fbx/fs/fat/fatent.c --- linux-4.4.115/fs/fat/fatent.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/fs/fat/fatent.c 2019-10-29 09:26:25.285219247 +0100 @@ -92,7 +92,8 @@ err_brelse: brelse(bhs[0]); err: - fat_msg(sb, KERN_ERR, "FAT read failed (blocknr %llu)", (llu)blocknr); + fat_msg_ratelimit(sb, KERN_ERR, + "FAT read failed (blocknr %llu)", (llu)blocknr); return -EIO; } @@ -105,8 +106,8 @@ fatent->fat_inode = MSDOS_SB(sb)->fat_inode; fatent->bhs[0] = sb_bread(sb, blocknr); if (!fatent->bhs[0]) { - fat_msg(sb, KERN_ERR, "FAT read failed (blocknr %llu)", - (llu)blocknr); + fat_msg_ratelimit(sb, KERN_ERR, + "FAT read failed (blocknr %llu)", (llu)blocknr); return -EIO; } fatent->nr_bhs = 1; diff -ruw linux-4.4.115/fs/fat/inode.c linux-4.4.115-fbx/fs/fat/inode.c --- linux-4.4.115/fs/fat/inode.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/fs/fat/inode.c 2019-10-29 09:26:25.289219286 +0100 @@ -760,8 +760,9 @@ fat_get_blknr_offset(sbi, i_pos, &blocknr, &offset); bh = sb_bread(sb, blocknr); if (!bh) { - fat_msg(sb, KERN_ERR, "unable to read inode block " - "for updating (i_pos %lld)", i_pos); + fat_msg_ratelimit(sb, KERN_ERR, + "unable to read inode block for updating (i_pos %lld)", + i_pos); return -EIO; } spin_lock(&sbi->inode_hash_lock); diff -ruw linux-4.4.115/fs/file_table.c linux-4.4.115-fbx/fs/file_table.c --- linux-4.4.115/fs/file_table.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/fs/file_table.c 2019-01-22 16:16:27.851285780 +0100 @@ -41,6 +41,141 @@ static struct percpu_counter nr_files __cacheline_aligned_in_smp; +#ifdef CONFIG_FILE_TABLE_DEBUG +#include +#include +static DEFINE_MUTEX(global_files_lock); +static DEFINE_HASHTABLE(global_files_hashtable, 10); + +struct global_filetable_lookup_key { + struct work_struct work; + uintptr_t value; +}; + +void global_filetable_print_warning_once(void) +{ + pr_err_once("\n**********************************************************\n"); + pr_err_once("** NOTICE NOTICE NOTICE NOTICE NOTICE NOTICE NOTICE **\n"); + pr_err_once("** **\n"); + pr_err_once("** VFS FILE TABLE DEBUG is enabled . **\n"); + pr_err_once("** Allocating extra memory and slowing access to files **\n"); + pr_err_once("** **\n"); + pr_err_once("** This means that this is a DEBUG kernel and it is **\n"); + pr_err_once("** unsafe for production use. **\n"); + pr_err_once("** **\n"); + pr_err_once("** If you see this message and you are not debugging **\n"); + pr_err_once("** the kernel, report this immediately to your vendor! **\n"); + pr_err_once("** **\n"); + pr_err_once("** NOTICE NOTICE NOTICE NOTICE NOTICE NOTICE NOTICE **\n"); + pr_err_once("**********************************************************\n"); +} + +void global_filetable_add(struct file *filp) +{ + struct mount *mnt; + + if (filp->f_path.dentry->d_iname == NULL || + strlen(filp->f_path.dentry->d_iname) == 0) + return; + + mnt = real_mount(filp->f_path.mnt); + + mutex_lock(&global_files_lock); + hash_add(global_files_hashtable, &filp->f_hash, (uintptr_t)mnt); + mutex_unlock(&global_files_lock); +} + +void global_filetable_del(struct file *filp) +{ + mutex_lock(&global_files_lock); + hash_del(&filp->f_hash); + mutex_unlock(&global_files_lock); +} + +static void global_print_file(struct file *filp, char *path_buffer, int *count) +{ + char *pathname; + + pathname = d_path(&filp->f_path, path_buffer, PAGE_SIZE); + if (IS_ERR(pathname)) + pr_err("VFS: File %d Address : %pa partial filename: %s ref_count=%ld\n", + ++(*count), &filp, filp->f_path.dentry->d_iname, + atomic_long_read(&filp->f_count)); + else + pr_err("VFS: File %d Address : %pa full filepath: %s ref_count=%ld\n", + ++(*count), &filp, pathname, + atomic_long_read(&filp->f_count)); +} + +static void global_filetable_print(uintptr_t lookup_mnt) +{ + struct hlist_node *tmp; + struct file *filp; + struct mount *mnt; + int index; + int count = 0; + char *path_buffer = (char *)__get_free_page(GFP_TEMPORARY); + + mutex_lock(&global_files_lock); + pr_err("\n**********************************************************\n"); + pr_err("** NOTICE NOTICE NOTICE NOTICE NOTICE NOTICE NOTICE **\n"); + + pr_err("\n"); + pr_err("VFS: The following files hold a reference to the mount\n"); + pr_err("\n"); + hash_for_each_possible_safe(global_files_hashtable, filp, tmp, f_hash, + lookup_mnt) { + mnt = real_mount(filp->f_path.mnt); + if ((uintptr_t)mnt == lookup_mnt) + global_print_file(filp, path_buffer, &count); + } + pr_err("\n"); + pr_err("VFS: Found total of %d open files\n", count); + pr_err("\n"); + + count = 0; + pr_err("\n"); + pr_err("VFS: The following files need to cleaned up\n"); + pr_err("\n"); + hash_for_each_safe(global_files_hashtable, index, tmp, filp, f_hash) { + if (atomic_long_read(&filp->f_count) == 0) + global_print_file(filp, path_buffer, &count); + } + + pr_err("\n"); + pr_err("VFS: Found total of %d files awaiting clean-up\n", count); + pr_err("\n"); + pr_err("** NOTICE NOTICE NOTICE NOTICE NOTICE NOTICE NOTICE **\n"); + pr_err("\n**********************************************************\n"); + + mutex_unlock(&global_files_lock); + free_page((unsigned long)path_buffer); +} + +static void global_filetable_print_work_fn(struct work_struct *work) +{ + struct global_filetable_lookup_key *key; + uintptr_t lookup_mnt; + + key = container_of(work, struct global_filetable_lookup_key, work); + lookup_mnt = key->value; + kfree(key); + global_filetable_print(lookup_mnt); +} + +void global_filetable_delayed_print(struct mount *mnt) +{ + struct global_filetable_lookup_key *key; + + key = kzalloc(sizeof(*key), GFP_KERNEL); + if (key == NULL) + return; + key->value = (uintptr_t)mnt; + INIT_WORK(&key->work, global_filetable_print_work_fn); + schedule_work(&key->work); +} +#endif /* CONFIG_FILE_TABLE_DEBUG */ + static void file_free_rcu(struct rcu_head *head) { struct file *f = container_of(head, struct file, f_u.fu_rcuhead); @@ -219,6 +354,7 @@ put_write_access(inode); __mnt_drop_write(mnt); } + global_filetable_del(file); file->f_path.dentry = NULL; file->f_path.mnt = NULL; file->f_inode = NULL; @@ -314,6 +450,7 @@ filp_cachep = kmem_cache_create("filp", sizeof(struct file), 0, SLAB_HWCACHE_ALIGN | SLAB_PANIC, NULL); percpu_counter_init(&nr_files, 0, GFP_KERNEL); + global_filetable_print_warning_once(); } /* diff -ruw linux-4.4.115/fs/fs_struct.c linux-4.4.115-fbx/fs/fs_struct.c --- linux-4.4.115/fs/fs_struct.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/fs/fs_struct.c 2019-01-22 16:16:27.855285816 +0100 @@ -44,6 +44,7 @@ if (old_pwd.dentry) path_put(&old_pwd); } +EXPORT_SYMBOL(set_fs_pwd); static inline int replace_path(struct path *p, const struct path *old, const struct path *new) { @@ -89,6 +90,7 @@ path_put(&fs->pwd); kmem_cache_free(fs_cachep, fs); } +EXPORT_SYMBOL(free_fs_struct); void exit_fs(struct task_struct *tsk) { @@ -127,6 +129,7 @@ } return fs; } +EXPORT_SYMBOL_GPL(copy_fs_struct); int unshare_fs_struct(void) { diff -ruw linux-4.4.115/fs/fs-writeback.c linux-4.4.115-fbx/fs/fs-writeback.c --- linux-4.4.115/fs/fs-writeback.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/fs/fs-writeback.c 2019-10-29 09:26:25.289219286 +0100 @@ -2069,7 +2069,7 @@ (dirtytime && (inode->i_state & I_DIRTY_INODE))) return; - if (unlikely(block_dump)) + if (unlikely(block_dump > 1)) block_dump___mark_inode_dirty(inode); spin_lock(&inode->i_lock); diff -ruw linux-4.4.115/fs/fuse/dev.c linux-4.4.115-fbx/fs/fuse/dev.c --- linux-4.4.115/fs/fuse/dev.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/fs/fuse/dev.c 2019-10-29 09:26:25.293219325 +0100 @@ -7,18 +7,21 @@ */ #include "fuse_i.h" +#include "fuse_passthrough.h" #include #include #include #include #include +#include #include #include #include #include #include #include +#include MODULE_ALIAS_MISCDEV(FUSE_MINOR); MODULE_ALIAS("devname:fuse"); @@ -477,7 +480,9 @@ * Either request is already in userspace, or it was forced. * Wait it out. */ - wait_event(req->waitq, test_bit(FR_FINISHED, &req->flags)); + while (!test_bit(FR_FINISHED, &req->flags)) + wait_event_freezable(req->waitq, + test_bit(FR_FINISHED, &req->flags)); } static void __fuse_request_send(struct fuse_conn *fc, struct fuse_req *req) @@ -570,10 +575,15 @@ args->out.numargs * sizeof(struct fuse_arg)); fuse_request_send(fc, req); ret = req->out.h.error; - if (!ret && args->out.argvar) { + if (!ret) { + if (args->out.argvar) { BUG_ON(args->out.numargs != 1); ret = req->out.args[0].size; } + + if (req->passthrough_filp != NULL) + args->out.passthrough_filp = req->passthrough_filp; + } fuse_put_request(fc, req); return ret; @@ -1936,8 +1946,15 @@ cs->move_pages = 0; err = copy_out_args(cs, &req->out, nbytes); + if (req->in.h.opcode == FUSE_CANONICAL_PATH) { + char *path = (char *)req->out.args[0].value; + + path[req->out.args[0].size - 1] = 0; + req->out.h.error = kern_path(path, 0, req->canonical_path); + } fuse_copy_finish(cs); + fuse_setup_passthrough(fc, req); spin_lock(&fpq->lock); clear_bit(FR_LOCKED, &req->flags); if (!fpq->connected) diff -ruw linux-4.4.115/fs/fuse/dir.c linux-4.4.115-fbx/fs/fuse/dir.c --- linux-4.4.115/fs/fuse/dir.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/fs/fuse/dir.c 2019-10-29 09:26:25.293219325 +0100 @@ -267,6 +267,50 @@ goto out; } +/* + * Get the canonical path. Since we must translate to a path, this must be done + * in the context of the userspace daemon, however, the userspace daemon cannot + * look up paths on its own. Instead, we handle the lookup as a special case + * inside of the write request. + */ +static void fuse_dentry_canonical_path(const struct path *path, struct path *canonical_path) { + struct inode *inode = path->dentry->d_inode; + struct fuse_conn *fc = get_fuse_conn(inode); + struct fuse_req *req; + int err; + char *path_name; + + req = fuse_get_req(fc, 1); + err = PTR_ERR(req); + if (IS_ERR(req)) + goto default_path; + + path_name = (char*)__get_free_page(GFP_KERNEL); + if (!path_name) { + fuse_put_request(fc, req); + goto default_path; + } + + req->in.h.opcode = FUSE_CANONICAL_PATH; + req->in.h.nodeid = get_node_id(inode); + req->in.numargs = 0; + req->out.numargs = 1; + req->out.args[0].size = PATH_MAX; + req->out.args[0].value = path_name; + req->canonical_path = canonical_path; + req->out.argvar = 1; + fuse_request_send(fc, req); + err = req->out.h.error; + fuse_put_request(fc, req); + free_page((unsigned long)path_name); + if (!err) + return; +default_path: + canonical_path->dentry = path->dentry; + canonical_path->mnt = path->mnt; + path_get(canonical_path); +} + static int invalid_nodeid(u64 nodeid) { return !nodeid || nodeid == FUSE_ROOT_ID; @@ -274,6 +318,7 @@ const struct dentry_operations fuse_dentry_operations = { .d_revalidate = fuse_dentry_revalidate, + .d_canonical_path = fuse_dentry_canonical_path, }; int fuse_valid_type(int m) @@ -428,6 +473,7 @@ args.out.args[0].value = &outentry; args.out.args[1].size = sizeof(outopen); args.out.args[1].value = &outopen; + args.out.passthrough_filp = NULL; err = fuse_simple_request(fc, &args); if (err) goto out_free_ff; @@ -439,6 +485,8 @@ ff->fh = outopen.fh; ff->nodeid = outentry.nodeid; ff->open_flags = outopen.open_flags; + if (args.out.passthrough_filp != NULL) + ff->passthrough_filp = args.out.passthrough_filp; inode = fuse_iget(dir->i_sb, outentry.nodeid, outentry.generation, &outentry.attr, entry_attr_timeout(&outentry), 0); if (!inode) { diff -ruw linux-4.4.115/fs/fuse/file.c linux-4.4.115-fbx/fs/fuse/file.c --- linux-4.4.115/fs/fuse/file.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/fs/fuse/file.c 2019-10-29 09:26:25.293219325 +0100 @@ -7,6 +7,7 @@ */ #include "fuse_i.h" +#include "fuse_passthrough.h" #include #include @@ -21,8 +22,10 @@ static const struct file_operations fuse_direct_io_file_operations; static int fuse_send_open(struct fuse_conn *fc, u64 nodeid, struct file *file, - int opcode, struct fuse_open_out *outargp) + int opcode, struct fuse_open_out *outargp, + struct file **passthrough_filpp) { + int ret_val; struct fuse_open_in inarg; FUSE_ARGS(args); @@ -38,8 +41,14 @@ args.out.numargs = 1; args.out.args[0].size = sizeof(*outargp); args.out.args[0].value = outargp; + args.out.passthrough_filp = NULL; - return fuse_simple_request(fc, &args); + ret_val = fuse_simple_request(fc, &args); + + if (args.out.passthrough_filp != NULL) + *passthrough_filpp = args.out.passthrough_filp; + + return ret_val; } struct fuse_file *fuse_file_alloc(struct fuse_conn *fc) @@ -50,6 +59,10 @@ if (unlikely(!ff)) return NULL; + ff->passthrough_filp = NULL; + ff->passthrough_enabled = 0; + if (fc->passthrough) + ff->passthrough_enabled = 1; ff->fc = fc; ff->reserved_req = fuse_request_alloc(0); if (unlikely(!ff->reserved_req)) { @@ -118,6 +131,7 @@ bool isdir) { struct fuse_file *ff; + struct file *passthrough_filp = NULL; int opcode = isdir ? FUSE_OPENDIR : FUSE_OPEN; ff = fuse_file_alloc(fc); @@ -130,10 +144,12 @@ struct fuse_open_out outarg; int err; - err = fuse_send_open(fc, nodeid, file, opcode, &outarg); + err = fuse_send_open(fc, nodeid, file, opcode, &outarg, + &(passthrough_filp)); if (!err) { ff->fh = outarg.fh; ff->open_flags = outarg.open_flags; + ff->passthrough_filp = passthrough_filp; } else if (err != -ENOSYS || isdir) { fuse_file_free(ff); @@ -253,6 +269,8 @@ if (unlikely(!ff)) return; + fuse_passthrough_release(ff); + req = ff->reserved_req; fuse_prepare_release(ff, file->f_flags, opcode); @@ -883,6 +901,43 @@ return -EIO; } +#ifdef CONFIG_CMA + if (is_cma_pageblock(page)) { + struct page *oldpage = page, *newpage; + int err; + + /* make sure that old page is not free in-between the calls */ + page_cache_get(oldpage); + + newpage = alloc_page(GFP_HIGHUSER); + if (!newpage) { + page_cache_release(oldpage); + return -ENOMEM; + } + + err = replace_page_cache_page(oldpage, newpage, GFP_KERNEL); + if (err) { + __free_page(newpage); + page_cache_release(oldpage); + return err; + } + + /* + * Decrement the count on new page to make page cache the only + * owner of it + */ + lock_page(newpage); + put_page(newpage); + + lru_cache_add_file(newpage); + + /* finally release the old page and swap pointers */ + unlock_page(oldpage); + page_cache_release(oldpage); + page = newpage; + } +#endif + page_cache_get(page); req->pages[req->num_pages] = page; req->page_descs[req->num_pages].length = PAGE_SIZE; @@ -928,8 +983,10 @@ static ssize_t fuse_file_read_iter(struct kiocb *iocb, struct iov_iter *to) { + ssize_t ret_val; struct inode *inode = iocb->ki_filp->f_mapping->host; struct fuse_conn *fc = get_fuse_conn(inode); + struct fuse_file *ff = iocb->ki_filp->private_data; /* * In auto invalidate mode, always update attributes on read. @@ -944,7 +1001,12 @@ return err; } - return generic_file_read_iter(iocb, to); + if (ff && ff->passthrough_enabled && ff->passthrough_filp) + ret_val = fuse_passthrough_read_iter(iocb, to); + else + ret_val = generic_file_read_iter(iocb, to); + + return ret_val; } static void fuse_write_fill(struct fuse_req *req, struct fuse_file *ff, @@ -1176,6 +1238,7 @@ static ssize_t fuse_file_write_iter(struct kiocb *iocb, struct iov_iter *from) { struct file *file = iocb->ki_filp; + struct fuse_file *ff = file->private_data; struct address_space *mapping = file->f_mapping; ssize_t written = 0; ssize_t written_buffered = 0; @@ -1209,8 +1272,14 @@ if (err) goto out; + if (ff && ff->passthrough_enabled && ff->passthrough_filp) { + written = fuse_passthrough_write_iter(iocb, from); + goto out; + } + if (iocb->ki_flags & IOCB_DIRECT) { loff_t pos = iocb->ki_pos; + written = generic_file_direct_write(iocb, from, pos); if (written < 0 || !iov_iter_count(from)) goto out; @@ -2081,6 +2150,9 @@ static int fuse_file_mmap(struct file *file, struct vm_area_struct *vma) { + struct fuse_file *ff = file->private_data; + + ff->passthrough_enabled = 0; if ((vma->vm_flags & VM_SHARED) && (vma->vm_flags & VM_MAYWRITE)) fuse_link_write_file(file); @@ -2091,6 +2163,9 @@ static int fuse_direct_mmap(struct file *file, struct vm_area_struct *vma) { + struct fuse_file *ff = file->private_data; + + ff->passthrough_enabled = 0; /* Can't provide the coherency needed for MAP_SHARED */ if (vma->vm_flags & VM_MAYSHARE) return -ENODEV; diff -ruw linux-4.4.115/fs/fuse/fuse_i.h linux-4.4.115-fbx/fs/fuse/fuse_i.h --- linux-4.4.115/fs/fuse/fuse_i.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/fs/fuse/fuse_i.h 2019-10-29 09:26:25.293219325 +0100 @@ -158,6 +158,10 @@ /** Has flock been performed on this file? */ bool flock:1; + + /* the read write file */ + struct file *passthrough_filp; + bool passthrough_enabled; }; /** One input argument of a request */ @@ -237,6 +241,7 @@ unsigned argvar:1; unsigned numargs; struct fuse_arg args[2]; + struct file *passthrough_filp; } out; }; @@ -372,6 +377,9 @@ /** Inode used in the request or NULL */ struct inode *inode; + /** Path used for completing d_canonical_path */ + struct path *canonical_path; + /** AIO control block */ struct fuse_io_priv *io; @@ -383,6 +391,9 @@ /** Request is stolen from fuse_file->reserved_req */ struct file *stolen_file; + + /** fuse passthrough file */ + struct file *passthrough_filp; }; struct fuse_iqueue { @@ -540,6 +551,9 @@ /** write-back cache policy (default is write-through) */ unsigned writeback_cache:1; + /** passthrough IO. */ + unsigned passthrough:1; + /* * The following bitfields are only for optimization purposes * and hence races in setting them will not cause malfunction diff -ruw linux-4.4.115/fs/fuse/inode.c linux-4.4.115-fbx/fs/fuse/inode.c --- linux-4.4.115/fs/fuse/inode.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/fs/fuse/inode.c 2019-10-29 09:26:25.293219325 +0100 @@ -860,6 +860,7 @@ fc->conn_error = 1; else { unsigned long ra_pages; + struct super_block *sb = fc->sb; process_init_limits(fc, arg); @@ -898,6 +899,13 @@ fc->async_dio = 1; if (arg->flags & FUSE_WRITEBACK_CACHE) fc->writeback_cache = 1; + if (arg->flags & FUSE_PASSTHROUGH) { + fc->passthrough = 1; + /* Prevent further stacking */ + sb->s_stack_depth = FILESYSTEM_MAX_STACK_DEPTH; + pr_info("FUSE: Pass through is enabled [%s : %d]!\n", + current->comm, current->pid); + } if (arg->time_gran && arg->time_gran <= 1000000000) fc->sb->s_time_gran = arg->time_gran; } else { diff -ruw linux-4.4.115/fs/fuse/Makefile linux-4.4.115-fbx/fs/fuse/Makefile --- linux-4.4.115/fs/fuse/Makefile 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/fs/fuse/Makefile 2019-01-22 16:16:27.855285816 +0100 @@ -5,4 +5,4 @@ obj-$(CONFIG_FUSE_FS) += fuse.o obj-$(CONFIG_CUSE) += cuse.o -fuse-objs := dev.o dir.o file.o inode.o control.o +fuse-objs := dev.o dir.o file.o inode.o control.o passthrough.o diff -ruw linux-4.4.115/fs/inode.c linux-4.4.115-fbx/fs/inode.c --- linux-4.4.115/fs/inode.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/fs/inode.c 2019-10-29 09:26:25.305219443 +0100 @@ -154,6 +154,12 @@ inode->i_rdev = 0; inode->dirtied_when = 0; +#ifdef CONFIG_CGROUP_WRITEBACK + inode->i_wb_frn_winner = 0; + inode->i_wb_frn_avg_time = 0; + inode->i_wb_frn_history = 0; +#endif + if (security_inode_alloc(inode)) goto out; spin_lock_init(&inode->i_lock); @@ -1715,7 +1721,7 @@ } EXPORT_SYMBOL(dentry_needs_remove_privs); -static int __remove_privs(struct dentry *dentry, int kill) +static int __remove_privs(struct vfsmount *mnt, struct dentry *dentry, int kill) { struct iattr newattrs; @@ -1724,7 +1730,7 @@ * Note we call this on write, so notify_change will not * encounter any conflicting delegations: */ - return notify_change(dentry, &newattrs, NULL); + return notify_change2(mnt, dentry, &newattrs, NULL); } /* @@ -1746,7 +1752,7 @@ if (kill < 0) return kill; if (kill) - error = __remove_privs(dentry, kill); + error = __remove_privs(file->f_path.mnt, dentry, kill); if (!error) inode_has_no_xattr(inode); diff -ruw linux-4.4.115/fs/internal.h linux-4.4.115-fbx/fs/internal.h --- linux-4.4.115/fs/internal.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/fs/internal.h 2019-10-29 09:26:25.305219443 +0100 @@ -84,9 +84,11 @@ * super.c */ extern int do_remount_sb(struct super_block *, int, void *, int); +extern int do_remount_sb2(struct vfsmount *, struct super_block *, int, + void *, int); extern bool trylock_super(struct super_block *sb); extern struct dentry *mount_fs(struct file_system_type *, - int, const char *, void *); + int, const char *, struct vfsmount *, void *); extern struct super_block *user_get_super(dev_t); /* @@ -151,3 +153,29 @@ * fs/nsfs.c */ extern struct dentry_operations ns_dentry_operations; + +#ifdef CONFIG_FILE_TABLE_DEBUG +void global_filetable_print_warning_once(void); +void global_filetable_add(struct file *filp); +void global_filetable_del(struct file *filp); +void global_filetable_delayed_print(struct mount *mnt); + +#else /* i.e NOT CONFIG_FILE_TABLE_DEBUG */ + +static inline void global_filetable_print_warning_once(void) +{ +} + +static inline void global_filetable_add(struct file *filp) +{ +} + +static inline void global_filetable_del(struct file *filp) +{ +} + +static inline void global_filetable_delayed_print(struct mount *mnt) +{ +} + +#endif /* CONFIG_FILE_TABLE_DEBUG */ diff -ruw linux-4.4.115/fs/jbd2/journal.c linux-4.4.115-fbx/fs/jbd2/journal.c --- linux-4.4.115/fs/jbd2/journal.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/fs/jbd2/journal.c 2019-10-29 09:26:25.309219482 +0100 @@ -275,11 +275,11 @@ goto loop; end_loop: - write_unlock(&journal->j_state_lock); del_timer_sync(&journal->j_commit_timer); journal->j_task = NULL; wake_up(&journal->j_wait_done_commit); jbd_debug(1, "Journal thread exiting.\n"); + write_unlock(&journal->j_state_lock); return 0; } diff -ruw linux-4.4.115/fs/Kconfig linux-4.4.115-fbx/fs/Kconfig --- linux-4.4.115/fs/Kconfig 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/fs/Kconfig 2019-01-25 20:32:47.247752405 +0100 @@ -73,6 +73,8 @@ for filesystems like NFS and for the flock() system call. Disabling this option saves about 11k. +source "fs/crypto/Kconfig" + source "fs/notify/Kconfig" source "fs/quota/Kconfig" @@ -102,6 +104,7 @@ source "fs/fat/Kconfig" source "fs/ntfs/Kconfig" +source "fs/exfat/Kconfig" endmenu endif # BLOCK @@ -199,6 +202,7 @@ source "fs/adfs/Kconfig" source "fs/affs/Kconfig" source "fs/ecryptfs/Kconfig" +source "fs/sdcardfs/Kconfig" source "fs/hfs/Kconfig" source "fs/hfsplus/Kconfig" source "fs/befs/Kconfig" @@ -281,4 +285,9 @@ source "fs/nls/Kconfig" source "fs/dlm/Kconfig" +config FILE_TABLE_DEBUG + bool "Enable FILE_TABLE_DEBUG" + help + This option enables debug of the open files using a global filetable + endmenu diff -ruw linux-4.4.115/fs/Makefile linux-4.4.115-fbx/fs/Makefile --- linux-4.4.115/fs/Makefile 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/fs/Makefile 2019-01-25 20:32:47.247752405 +0100 @@ -30,6 +30,7 @@ obj-$(CONFIG_USERFAULTFD) += userfaultfd.o obj-$(CONFIG_AIO) += aio.o obj-$(CONFIG_FS_DAX) += dax.o +obj-$(CONFIG_FS_ENCRYPTION) += crypto/ obj-$(CONFIG_FILE_LOCKING) += locks.o obj-$(CONFIG_COMPAT) += compat.o compat_ioctl.o obj-$(CONFIG_BINFMT_AOUT) += binfmt_aout.o @@ -41,7 +42,7 @@ obj-$(CONFIG_BINFMT_ELF_FDPIC) += binfmt_elf_fdpic.o obj-$(CONFIG_BINFMT_FLAT) += binfmt_flat.o -obj-$(CONFIG_FS_MBCACHE) += mbcache.o +obj-$(CONFIG_FS_MBCACHE) += mbcache.o mbcache2.o obj-$(CONFIG_FS_POSIX_ACL) += posix_acl.o obj-$(CONFIG_NFS_COMMON) += nfs_common/ obj-$(CONFIG_COREDUMP) += coredump.o @@ -81,6 +82,7 @@ obj-$(CONFIG_HFSPLUS_FS) += hfsplus/ # Before hfs to find wrapped HFS+ obj-$(CONFIG_HFS_FS) += hfs/ obj-$(CONFIG_ECRYPT_FS) += ecryptfs/ +obj-$(CONFIG_SDCARD_FS) += sdcardfs/ obj-$(CONFIG_VXFS_FS) += freevxfs/ obj-$(CONFIG_NFS_FS) += nfs/ obj-$(CONFIG_EXPORTFS) += exportfs/ @@ -126,3 +128,4 @@ obj-$(CONFIG_CEPH_FS) += ceph/ obj-$(CONFIG_PSTORE) += pstore/ obj-$(CONFIG_EFIVAR_FS) += efivarfs/ +obj-$(CONFIG_EXFAT_FS) += exfat/ diff -ruw linux-4.4.115/fs/mbcache.c linux-4.4.115-fbx/fs/mbcache.c --- linux-4.4.115/fs/mbcache.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/fs/mbcache.c 2019-01-22 16:16:27.911286324 +0100 @@ -222,8 +222,19 @@ * then reacquire the lock in the proper order. */ spin_lock(&mb_cache_spinlock); + /* + * Evaluate the conditions under global lock mb_cache_spinlock, + * to check if mb_cache_entry_get() is running now + * and has already deleted the entry from mb_cache_lru_list + * and incremented ce->e_refcnt to prevent further additions + * to mb_cache_lru_list. + */ + if (!(ce->e_used || ce->e_queued || + atomic_read(&ce->e_refcnt))) { if (list_empty(&ce->e_lru_list)) - list_add_tail(&ce->e_lru_list, &mb_cache_lru_list); + list_add_tail(&ce->e_lru_list, + &mb_cache_lru_list); + } spin_unlock(&mb_cache_spinlock); } __spin_unlock_mb_cache_entry(ce); @@ -262,7 +273,6 @@ list_del_init(&ce->e_lru_list); if (ce->e_used || ce->e_queued || atomic_read(&ce->e_refcnt)) continue; - spin_unlock(&mb_cache_spinlock); /* Prevent any find or get operation on the entry */ hlist_bl_lock(ce->e_block_hash_p); hlist_bl_lock(ce->e_index_hash_p); @@ -271,10 +281,10 @@ !list_empty(&ce->e_lru_list)) { hlist_bl_unlock(ce->e_index_hash_p); hlist_bl_unlock(ce->e_block_hash_p); - spin_lock(&mb_cache_spinlock); continue; } __mb_cache_entry_unhash_unlock(ce); + spin_unlock(&mb_cache_spinlock); list_add_tail(&ce->e_lru_list, &free_list); spin_lock(&mb_cache_spinlock); } @@ -516,7 +526,6 @@ if (ce->e_used || ce->e_queued || atomic_read(&ce->e_refcnt)) continue; - spin_unlock(&mb_cache_spinlock); /* * Prevent any find or get operation on the * entry. @@ -530,13 +539,13 @@ hlist_bl_unlock(ce->e_index_hash_p); hlist_bl_unlock(ce->e_block_hash_p); l = &mb_cache_lru_list; - spin_lock(&mb_cache_spinlock); continue; } mb_assert(list_empty(&ce->e_lru_list)); mb_assert(!(ce->e_used || ce->e_queued || atomic_read(&ce->e_refcnt))); __mb_cache_entry_unhash_unlock(ce); + spin_unlock(&mb_cache_spinlock); goto found; } } @@ -670,6 +679,7 @@ cache->c_bucket_bits); block_hash_p = &cache->c_block_hash[bucket]; /* First serialize access to the block corresponding hash chain. */ + spin_lock(&mb_cache_spinlock); hlist_bl_lock(block_hash_p); hlist_bl_for_each_entry(ce, l, block_hash_p, e_block_list) { mb_assert(ce->e_block_hash_p == block_hash_p); @@ -678,9 +688,11 @@ * Prevent a free from removing the entry. */ atomic_inc(&ce->e_refcnt); + if (!list_empty(&ce->e_lru_list)) + list_del_init(&ce->e_lru_list); hlist_bl_unlock(block_hash_p); + spin_unlock(&mb_cache_spinlock); __spin_lock_mb_cache_entry(ce); - atomic_dec(&ce->e_refcnt); if (ce->e_used > 0) { DEFINE_WAIT(wait); while (ce->e_used > 0) { @@ -695,13 +707,9 @@ finish_wait(&mb_cache_queue, &wait); } ce->e_used += 1 + MB_CACHE_WRITER; + atomic_dec(&ce->e_refcnt); __spin_unlock_mb_cache_entry(ce); - if (!list_empty(&ce->e_lru_list)) { - spin_lock(&mb_cache_spinlock); - list_del_init(&ce->e_lru_list); - spin_unlock(&mb_cache_spinlock); - } if (!__mb_cache_entry_is_block_hashed(ce)) { __mb_cache_entry_release(ce); return NULL; @@ -710,6 +718,7 @@ } } hlist_bl_unlock(block_hash_p); + spin_unlock(&mb_cache_spinlock); return NULL; } diff -ruw linux-4.4.115/fs/mpage.c linux-4.4.115-fbx/fs/mpage.c --- linux-4.4.115/fs/mpage.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/fs/mpage.c 2019-01-22 16:16:27.911286324 +0100 @@ -30,6 +30,14 @@ #include #include "internal.h" +#define CREATE_TRACE_POINTS +#include + +EXPORT_TRACEPOINT_SYMBOL(android_fs_datawrite_start); +EXPORT_TRACEPOINT_SYMBOL(android_fs_datawrite_end); +EXPORT_TRACEPOINT_SYMBOL(android_fs_dataread_start); +EXPORT_TRACEPOINT_SYMBOL(android_fs_dataread_end); + /* * I/O completion handler for multipage BIOs. * @@ -47,6 +55,16 @@ struct bio_vec *bv; int i; + if (trace_android_fs_dataread_end_enabled() && + (bio_data_dir(bio) == READ)) { + struct page *first_page = bio->bi_io_vec[0].bv_page; + + if (first_page != NULL) + trace_android_fs_dataread_end(first_page->mapping->host, + page_offset(first_page), + bio->bi_iter.bi_size); + } + bio_for_each_segment_all(bv, bio, i) { struct page *page = bv->bv_page; page_endio(page, bio_data_dir(bio), bio->bi_error); @@ -57,6 +75,24 @@ static struct bio *mpage_bio_submit(int rw, struct bio *bio) { + if (trace_android_fs_dataread_start_enabled() && (rw == READ)) { + struct page *first_page = bio->bi_io_vec[0].bv_page; + + if (first_page != NULL) { + char *path, pathbuf[MAX_TRACE_PATHBUF_LEN]; + + path = android_fstrace_get_pathname(pathbuf, + MAX_TRACE_PATHBUF_LEN, + first_page->mapping->host); + trace_android_fs_dataread_start( + first_page->mapping->host, + page_offset(first_page), + bio->bi_iter.bi_size, + current->pid, + path, + current->comm); + } + } bio->bi_end_io = mpage_end_io; guard_bio_eod(rw, bio); submit_bio(rw, bio); diff -ruw linux-4.4.115/fs/namei.c linux-4.4.115-fbx/fs/namei.c --- linux-4.4.115/fs/namei.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/fs/namei.c 2019-10-29 09:26:25.317219560 +0100 @@ -373,9 +373,11 @@ * flag in inode->i_opflags, that says "this has not special * permission function, use the fast case". */ -static inline int do_inode_permission(struct inode *inode, int mask) +static inline int do_inode_permission(struct vfsmount *mnt, struct inode *inode, int mask) { if (unlikely(!(inode->i_opflags & IOP_FASTPERM))) { + if (likely(mnt && inode->i_op->permission2)) + return inode->i_op->permission2(mnt, inode, mask); if (likely(inode->i_op->permission)) return inode->i_op->permission(inode, mask); @@ -399,7 +401,7 @@ * This does not check for a read-only file system. You probably want * inode_permission(). */ -int __inode_permission(struct inode *inode, int mask) +int __inode_permission2(struct vfsmount *mnt, struct inode *inode, int mask) { int retval; @@ -411,7 +413,7 @@ return -EACCES; } - retval = do_inode_permission(inode, mask); + retval = do_inode_permission(mnt, inode, mask); if (retval) return retval; @@ -419,7 +421,14 @@ if (retval) return retval; - return security_inode_permission(inode, mask); + retval = security_inode_permission(inode, mask); + return retval; +} +EXPORT_SYMBOL(__inode_permission2); + +int __inode_permission(struct inode *inode, int mask) +{ + return __inode_permission2(NULL, inode, mask); } EXPORT_SYMBOL(__inode_permission); @@ -455,14 +464,20 @@ * * When checking for MAY_APPEND, MAY_WRITE must also be set in @mask. */ -int inode_permission(struct inode *inode, int mask) +int inode_permission2(struct vfsmount *mnt, struct inode *inode, int mask) { int retval; retval = sb_permission(inode->i_sb, inode, mask); if (retval) return retval; - return __inode_permission(inode, mask); + return __inode_permission2(mnt, inode, mask); +} +EXPORT_SYMBOL(inode_permission2); + +int inode_permission(struct inode *inode, int mask) +{ + return inode_permission2(NULL, inode, mask); } EXPORT_SYMBOL(inode_permission); @@ -1645,13 +1660,13 @@ static inline int may_lookup(struct nameidata *nd) { if (nd->flags & LOOKUP_RCU) { - int err = inode_permission(nd->inode, MAY_EXEC|MAY_NOT_BLOCK); + int err = inode_permission2(nd->path.mnt, nd->inode, MAY_EXEC|MAY_NOT_BLOCK); if (err != -ECHILD) return err; if (unlazy_walk(nd, NULL, 0)) return -ECHILD; } - return inode_permission(nd->inode, MAY_EXEC); + return inode_permission2(nd->path.mnt, nd->inode, MAY_EXEC); } static inline int handle_dots(struct nameidata *nd, int type) @@ -2005,11 +2020,12 @@ nd->depth = 0; if (flags & LOOKUP_ROOT) { struct dentry *root = nd->root.dentry; + struct vfsmount *mnt = nd->root.mnt; struct inode *inode = root->d_inode; if (*s) { if (!d_can_lookup(root)) return ERR_PTR(-ENOTDIR); - retval = inode_permission(inode, MAY_EXEC); + retval = inode_permission2(mnt, inode, MAY_EXEC); if (retval) return ERR_PTR(retval); } @@ -2280,13 +2296,14 @@ /** * lookup_one_len - filesystem helper to lookup single pathname component * @name: pathname component to lookup + * @mnt: mount we are looking up on * @base: base directory to lookup from * @len: maximum length @len should be interpreted to * * Note that this routine is purely a helper for filesystem usage and should * not be called by generic code. */ -struct dentry *lookup_one_len(const char *name, struct dentry *base, int len) +struct dentry *lookup_one_len2(const char *name, struct vfsmount *mnt, struct dentry *base, int len) { struct qstr this; unsigned int c; @@ -2320,12 +2337,18 @@ return ERR_PTR(err); } - err = inode_permission(base->d_inode, MAY_EXEC); + err = inode_permission2(mnt, base->d_inode, MAY_EXEC); if (err) return ERR_PTR(err); return __lookup_hash(&this, base, 0); } +EXPORT_SYMBOL(lookup_one_len2); + +struct dentry *lookup_one_len(const char *name, struct dentry *base, int len) +{ + return lookup_one_len2(name, NULL, base, len); +} EXPORT_SYMBOL(lookup_one_len); int user_path_at_empty(int dfd, const char __user *name, unsigned flags, @@ -2552,7 +2575,7 @@ * 10. We don't allow removal of NFS sillyrenamed files; it's handled by * nfs_async_unlink(). */ -static int may_delete(struct inode *dir, struct dentry *victim, bool isdir) +static int may_delete(struct vfsmount *mnt, struct inode *dir, struct dentry *victim, bool isdir) { struct inode *inode = d_backing_inode(victim); int error; @@ -2564,7 +2587,7 @@ BUG_ON(victim->d_parent->d_inode != dir); audit_inode_child(dir, victim, AUDIT_TYPE_CHILD_DELETE); - error = inode_permission(dir, MAY_WRITE | MAY_EXEC); + error = inode_permission2(mnt, dir, MAY_WRITE | MAY_EXEC); if (error) return error; if (IS_APPEND(dir)) @@ -2595,14 +2618,14 @@ * 3. We should have write and exec permissions on dir * 4. We can't do it if dir is immutable (done in permission()) */ -static inline int may_create(struct inode *dir, struct dentry *child) +static inline int may_create(struct vfsmount *mnt, struct inode *dir, struct dentry *child) { audit_inode_child(dir, child, AUDIT_TYPE_CHILD_CREATE); if (child->d_inode) return -EEXIST; if (IS_DEADDIR(dir)) return -ENOENT; - return inode_permission(dir, MAY_WRITE | MAY_EXEC); + return inode_permission2(mnt, dir, MAY_WRITE | MAY_EXEC); } /* @@ -2649,10 +2672,10 @@ } EXPORT_SYMBOL(unlock_rename); -int vfs_create(struct inode *dir, struct dentry *dentry, umode_t mode, - bool want_excl) +int vfs_create2(struct vfsmount *mnt, struct inode *dir, struct dentry *dentry, + umode_t mode, bool want_excl) { - int error = may_create(dir, dentry); + int error = may_create(mnt, dir, dentry); if (error) return error; @@ -2664,15 +2687,29 @@ if (error) return error; error = dir->i_op->create(dir, dentry, mode, want_excl); + if (error) + return error; + error = security_inode_post_create(dir, dentry, mode); + if (error) + return error; if (!error) fsnotify_create(dir, dentry); + return error; } +EXPORT_SYMBOL(vfs_create2); + +int vfs_create(struct inode *dir, struct dentry *dentry, umode_t mode, + bool want_excl) +{ + return vfs_create2(NULL, dir, dentry, mode, want_excl); +} EXPORT_SYMBOL(vfs_create); static int may_open(struct path *path, int acc_mode, int flag) { struct dentry *dentry = path->dentry; + struct vfsmount *mnt = path->mnt; struct inode *inode = dentry->d_inode; int error; @@ -2701,7 +2738,7 @@ break; } - error = inode_permission(inode, acc_mode); + error = inode_permission2(mnt, inode, acc_mode); if (error) return error; @@ -2736,7 +2773,7 @@ if (!error) error = security_path_truncate(path); if (!error) { - error = do_truncate(path->dentry, 0, + error = do_truncate2(path->mnt, path->dentry, 0, ATTR_MTIME|ATTR_CTIME|ATTR_OPEN, filp); } @@ -2757,7 +2794,7 @@ if (error) return error; - error = inode_permission(dir->dentry->d_inode, MAY_WRITE | MAY_EXEC); + error = inode_permission2(dir->mnt, dir->dentry->d_inode, MAY_WRITE | MAY_EXEC); if (error) return error; @@ -2943,6 +2980,7 @@ bool got_write, int *opened) { struct dentry *dir = nd->path.dentry; + struct vfsmount *mnt = nd->path.mnt; struct inode *dir_inode = dir->d_inode; struct dentry *dentry; int error; @@ -2990,7 +3028,7 @@ error = security_path_mknod(&nd->path, dentry, mode, 0); if (error) goto out_dput; - error = vfs_create(dir->d_inode, dentry, mode, + error = vfs_create2(mnt, dir->d_inode, dentry, mode, nd->flags & LOOKUP_EXCL); if (error) goto out_dput; @@ -3252,7 +3290,7 @@ goto out; dir = path.dentry->d_inode; /* we want directory to be writable */ - error = inode_permission(dir, MAY_WRITE | MAY_EXEC); + error = inode_permission2(path.mnt, dir, MAY_WRITE | MAY_EXEC); if (error) goto out2; if (!dir->i_op->tmpfile) { @@ -3341,6 +3379,8 @@ error = -ESTALE; } file = ERR_PTR(error); + } else { + global_filetable_add(file); } return file; } @@ -3486,9 +3526,9 @@ } EXPORT_SYMBOL(user_path_create); -int vfs_mknod(struct inode *dir, struct dentry *dentry, umode_t mode, dev_t dev) +int vfs_mknod2(struct vfsmount *mnt, struct inode *dir, struct dentry *dentry, umode_t mode, dev_t dev) { - int error = may_create(dir, dentry); + int error = may_create(mnt, dir, dentry); if (error) return error; @@ -3508,10 +3548,24 @@ return error; error = dir->i_op->mknod(dir, dentry, mode, dev); + if (error) + return error; + + error = security_inode_post_create(dir, dentry, mode); + if (error) + return error; + if (!error) fsnotify_create(dir, dentry); + return error; } +EXPORT_SYMBOL(vfs_mknod2); + +int vfs_mknod(struct inode *dir, struct dentry *dentry, umode_t mode, dev_t dev) +{ + return vfs_mknod2(NULL, dir, dentry, mode, dev); +} EXPORT_SYMBOL(vfs_mknod); static int may_mknod(umode_t mode) @@ -3554,10 +3608,10 @@ goto out; switch (mode & S_IFMT) { case 0: case S_IFREG: - error = vfs_create(path.dentry->d_inode,dentry,mode,true); + error = vfs_create2(path.mnt, path.dentry->d_inode,dentry,mode,true); break; case S_IFCHR: case S_IFBLK: - error = vfs_mknod(path.dentry->d_inode,dentry,mode, + error = vfs_mknod2(path.mnt, path.dentry->d_inode,dentry,mode, new_decode_dev(dev)); break; case S_IFIFO: case S_IFSOCK: @@ -3578,9 +3632,9 @@ return sys_mknodat(AT_FDCWD, filename, mode, dev); } -int vfs_mkdir(struct inode *dir, struct dentry *dentry, umode_t mode) +int vfs_mkdir2(struct vfsmount *mnt, struct inode *dir, struct dentry *dentry, umode_t mode) { - int error = may_create(dir, dentry); + int error = may_create(mnt, dir, dentry); unsigned max_links = dir->i_sb->s_max_links; if (error) @@ -3602,6 +3656,12 @@ fsnotify_mkdir(dir, dentry); return error; } +EXPORT_SYMBOL(vfs_mkdir2); + +int vfs_mkdir(struct inode *dir, struct dentry *dentry, umode_t mode) +{ + return vfs_mkdir2(NULL, dir, dentry, mode); +} EXPORT_SYMBOL(vfs_mkdir); SYSCALL_DEFINE3(mkdirat, int, dfd, const char __user *, pathname, umode_t, mode) @@ -3620,7 +3680,7 @@ mode &= ~current_umask(); error = security_path_mkdir(&path, dentry, mode); if (!error) - error = vfs_mkdir(path.dentry->d_inode, dentry, mode); + error = vfs_mkdir2(path.mnt, path.dentry->d_inode, dentry, mode); done_path_create(&path, dentry); if (retry_estale(error, lookup_flags)) { lookup_flags |= LOOKUP_REVAL; @@ -3659,9 +3719,9 @@ } EXPORT_SYMBOL(dentry_unhash); -int vfs_rmdir(struct inode *dir, struct dentry *dentry) +int vfs_rmdir2(struct vfsmount *mnt, struct inode *dir, struct dentry *dentry) { - int error = may_delete(dir, dentry, 1); + int error = may_delete(mnt, dir, dentry, 1); if (error) return error; @@ -3696,6 +3756,12 @@ d_delete(dentry); return error; } +EXPORT_SYMBOL(vfs_rmdir2); + +int vfs_rmdir(struct inode *dir, struct dentry *dentry) +{ + return vfs_rmdir2(NULL, dir, dentry); +} EXPORT_SYMBOL(vfs_rmdir); static long do_rmdir(int dfd, const char __user *pathname) @@ -3741,7 +3807,7 @@ error = security_path_rmdir(&path, dentry); if (error) goto exit3; - error = vfs_rmdir(path.dentry->d_inode, dentry); + error = vfs_rmdir2(path.mnt, path.dentry->d_inode, dentry); exit3: dput(dentry); exit2: @@ -3780,10 +3846,10 @@ * be appropriate for callers that expect the underlying filesystem not * to be NFS exported. */ -int vfs_unlink(struct inode *dir, struct dentry *dentry, struct inode **delegated_inode) +int vfs_unlink2(struct vfsmount *mnt, struct inode *dir, struct dentry *dentry, struct inode **delegated_inode) { struct inode *target = dentry->d_inode; - int error = may_delete(dir, dentry, 0); + int error = may_delete(mnt, dir, dentry, 0); if (error) return error; @@ -3818,6 +3884,12 @@ return error; } +EXPORT_SYMBOL(vfs_unlink2); + +int vfs_unlink(struct inode *dir, struct dentry *dentry, struct inode **delegated_inode) +{ + return vfs_unlink2(NULL, dir, dentry, delegated_inode); +} EXPORT_SYMBOL(vfs_unlink); /* @@ -3865,7 +3937,7 @@ error = security_path_unlink(&path, dentry); if (error) goto exit2; - error = vfs_unlink(path.dentry->d_inode, dentry, &delegated_inode); + error = vfs_unlink2(path.mnt, path.dentry->d_inode, dentry, &delegated_inode); exit2: dput(dentry); } @@ -3915,9 +3987,9 @@ return do_unlinkat(AT_FDCWD, pathname); } -int vfs_symlink(struct inode *dir, struct dentry *dentry, const char *oldname) +int vfs_symlink2(struct vfsmount *mnt, struct inode *dir, struct dentry *dentry, const char *oldname) { - int error = may_create(dir, dentry); + int error = may_create(mnt, dir, dentry); if (error) return error; @@ -3934,6 +4006,12 @@ fsnotify_create(dir, dentry); return error; } +EXPORT_SYMBOL(vfs_symlink2); + +int vfs_symlink(struct inode *dir, struct dentry *dentry, const char *oldname) +{ + return vfs_symlink2(NULL, dir, dentry, oldname); +} EXPORT_SYMBOL(vfs_symlink); SYSCALL_DEFINE3(symlinkat, const char __user *, oldname, @@ -3956,7 +4034,7 @@ error = security_path_symlink(&path, dentry, from->name); if (!error) - error = vfs_symlink(path.dentry->d_inode, dentry, from->name); + error = vfs_symlink2(path.mnt, path.dentry->d_inode, dentry, from->name); done_path_create(&path, dentry); if (retry_estale(error, lookup_flags)) { lookup_flags |= LOOKUP_REVAL; @@ -3991,7 +4069,7 @@ * be appropriate for callers that expect the underlying filesystem not * to be NFS exported. */ -int vfs_link(struct dentry *old_dentry, struct inode *dir, struct dentry *new_dentry, struct inode **delegated_inode) +int vfs_link2(struct vfsmount *mnt, struct dentry *old_dentry, struct inode *dir, struct dentry *new_dentry, struct inode **delegated_inode) { struct inode *inode = old_dentry->d_inode; unsigned max_links = dir->i_sb->s_max_links; @@ -4000,7 +4078,7 @@ if (!inode) return -ENOENT; - error = may_create(dir, new_dentry); + error = may_create(mnt, dir, new_dentry); if (error) return error; @@ -4043,6 +4121,12 @@ fsnotify_link(dir, inode, new_dentry); return error; } +EXPORT_SYMBOL(vfs_link2); + +int vfs_link(struct dentry *old_dentry, struct inode *dir, struct dentry *new_dentry, struct inode **delegated_inode) +{ + return vfs_link2(NULL, old_dentry, dir, new_dentry, delegated_inode); +} EXPORT_SYMBOL(vfs_link); /* @@ -4098,7 +4182,7 @@ error = security_path_link(old_path.dentry, &new_path, new_dentry); if (error) goto out_dput; - error = vfs_link(old_path.dentry, new_path.dentry->d_inode, new_dentry, &delegated_inode); + error = vfs_link2(old_path.mnt, old_path.dentry, new_path.dentry->d_inode, new_dentry, &delegated_inode); out_dput: done_path_create(&new_path, new_dentry); if (delegated_inode) { @@ -4173,7 +4257,8 @@ * ->i_mutex on parents, which works but leads to some truly excessive * locking]. */ -int vfs_rename(struct inode *old_dir, struct dentry *old_dentry, +int vfs_rename2(struct vfsmount *mnt, + struct inode *old_dir, struct dentry *old_dentry, struct inode *new_dir, struct dentry *new_dentry, struct inode **delegated_inode, unsigned int flags) { @@ -4192,19 +4277,19 @@ if (vfs_select_inode(old_dentry, 0) == vfs_select_inode(new_dentry, 0)) return 0; - error = may_delete(old_dir, old_dentry, is_dir); + error = may_delete(mnt, old_dir, old_dentry, is_dir); if (error) return error; if (!target) { - error = may_create(new_dir, new_dentry); + error = may_create(mnt, new_dir, new_dentry); } else { new_is_dir = d_is_dir(new_dentry); if (!(flags & RENAME_EXCHANGE)) - error = may_delete(new_dir, new_dentry, is_dir); + error = may_delete(mnt, new_dir, new_dentry, is_dir); else - error = may_delete(new_dir, new_dentry, new_is_dir); + error = may_delete(mnt, new_dir, new_dentry, new_is_dir); } if (error) return error; @@ -4221,12 +4306,12 @@ */ if (new_dir != old_dir) { if (is_dir) { - error = inode_permission(source, MAY_WRITE); + error = inode_permission2(mnt, source, MAY_WRITE); if (error) return error; } if ((flags & RENAME_EXCHANGE) && new_is_dir) { - error = inode_permission(target, MAY_WRITE); + error = inode_permission2(mnt, target, MAY_WRITE); if (error) return error; } @@ -4309,6 +4394,14 @@ return error; } +EXPORT_SYMBOL(vfs_rename2); + +int vfs_rename(struct inode *old_dir, struct dentry *old_dentry, + struct inode *new_dir, struct dentry *new_dentry, + struct inode **delegated_inode, unsigned int flags) +{ + return vfs_rename2(NULL, old_dir, old_dentry, new_dir, new_dentry, delegated_inode, flags); +} EXPORT_SYMBOL(vfs_rename); SYSCALL_DEFINE5(renameat2, int, olddfd, const char __user *, oldname, @@ -4422,7 +4515,7 @@ &new_path, new_dentry, flags); if (error) goto exit5; - error = vfs_rename(old_path.dentry->d_inode, old_dentry, + error = vfs_rename2(old_path.mnt, old_path.dentry->d_inode, old_dentry, new_path.dentry->d_inode, new_dentry, &delegated_inode, flags); exit5: @@ -4467,7 +4560,7 @@ int vfs_whiteout(struct inode *dir, struct dentry *dentry) { - int error = may_create(dir, dentry); + int error = may_create(NULL, dir, dentry); if (error) return error; diff -ruw linux-4.4.115/fs/namespace.c linux-4.4.115-fbx/fs/namespace.c --- linux-4.4.115/fs/namespace.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/fs/namespace.c 2019-10-29 09:26:25.317219560 +0100 @@ -227,6 +227,7 @@ mnt->mnt_count = 1; mnt->mnt_writers = 0; #endif + mnt->mnt.data = NULL; INIT_HLIST_NODE(&mnt->mnt_hash); INIT_LIST_HEAD(&mnt->mnt_child); @@ -581,6 +582,7 @@ static void free_vfsmnt(struct mount *mnt) { + kfree(mnt->mnt.data); kfree_const(mnt->mnt_devname); #ifdef CONFIG_SMP free_percpu(mnt->mnt_pcp); @@ -975,10 +977,18 @@ if (!mnt) return ERR_PTR(-ENOMEM); + if (type->alloc_mnt_data) { + mnt->mnt.data = type->alloc_mnt_data(); + if (!mnt->mnt.data) { + mnt_free_id(mnt); + free_vfsmnt(mnt); + return ERR_PTR(-ENOMEM); + } + } if (flags & MS_KERNMOUNT) mnt->mnt.mnt_flags = MNT_INTERNAL; - root = mount_fs(type, flags, name, data); + root = mount_fs(type, flags, name, &mnt->mnt, data); if (IS_ERR(root)) { mnt_free_id(mnt); free_vfsmnt(mnt); @@ -1007,6 +1017,14 @@ if (!mnt) return ERR_PTR(-ENOMEM); + if (sb->s_op->clone_mnt_data) { + mnt->mnt.data = sb->s_op->clone_mnt_data(old->mnt.data); + if (!mnt->mnt.data) { + err = -ENOMEM; + goto out_free; + } + } + if (flag & (CL_SLAVE | CL_PRIVATE | CL_SHARED_TO_SLAVE)) mnt->mnt_group_id = 0; /* not a peer of original */ else @@ -1576,6 +1594,8 @@ } unlock_mount_hash(); namespace_unlock(); + if (retval == -EBUSY) + global_filetable_delayed_print(mnt); return retval; } @@ -2288,8 +2308,14 @@ err = change_mount_flags(path->mnt, flags); else if (!capable(CAP_SYS_ADMIN)) err = -EPERM; - else - err = do_remount_sb(sb, flags, data, 0); + else { + err = do_remount_sb2(path->mnt, sb, flags, data, 0); + namespace_lock(); + lock_mount_hash(); + propagate_remount(mnt); + unlock_mount_hash(); + namespace_unlock(); + } if (!err) { lock_mount_hash(); mnt_flags |= mnt->mnt.mnt_flags & ~MNT_USER_SETTABLE_MASK; diff -ruw linux-4.4.115/fs/notify/fanotify/fanotify_user.c linux-4.4.115-fbx/fs/notify/fanotify/fanotify_user.c --- linux-4.4.115/fs/notify/fanotify/fanotify_user.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/fs/notify/fanotify/fanotify_user.c 2019-01-22 16:16:27.991287048 +0100 @@ -488,7 +488,7 @@ } /* you can only watch an inode if you have read permissions on it */ - ret = inode_permission(path->dentry->d_inode, MAY_READ); + ret = inode_permission2(path->mnt, path->dentry->d_inode, MAY_READ); if (ret) path_put(path); out: diff -ruw linux-4.4.115/fs/notify/inotify/inotify_user.c linux-4.4.115-fbx/fs/notify/inotify/inotify_user.c --- linux-4.4.115/fs/notify/inotify/inotify_user.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/fs/notify/inotify/inotify_user.c 2019-01-22 16:16:27.991287048 +0100 @@ -337,7 +337,7 @@ if (error) return error; /* you can only watch an inode if you have read permissions on it */ - error = inode_permission(path->dentry->d_inode, MAY_READ); + error = inode_permission2(path->mnt, path->dentry->d_inode, MAY_READ); if (error) path_put(path); return error; @@ -702,6 +702,8 @@ struct fsnotify_group *group; struct inode *inode; struct path path; + struct path alteredpath; + struct path *canonical_path = &path; struct fd f; int ret; unsigned flags = 0; @@ -741,13 +743,22 @@ if (ret) goto fput_and_out; + /* support stacked filesystems */ + if(path.dentry && path.dentry->d_op) { + if (path.dentry->d_op->d_canonical_path) { + path.dentry->d_op->d_canonical_path(&path, &alteredpath); + canonical_path = &alteredpath; + path_put(&path); + } + } + /* inode held in place by reference to path; group by fget on fd */ - inode = path.dentry->d_inode; + inode = canonical_path->dentry->d_inode; group = f.file->private_data; /* create/update an inode mark */ ret = inotify_update_watch(group, inode, mask); - path_put(&path); + path_put(canonical_path); fput_and_out: fdput(f); return ret; diff -ruw linux-4.4.115/fs/nsfs.c linux-4.4.115-fbx/fs/nsfs.c --- linux-4.4.115/fs/nsfs.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/fs/nsfs.c 2019-10-29 09:26:25.353219912 +0100 @@ -95,7 +95,8 @@ return ERR_PTR(-ENOMEM); } d_instantiate(dentry, inode); - dentry->d_fsdata = (void *)ns_ops; + dentry->d_flags |= DCACHE_RCUACCESS; + dentry->d_fsdata = (void *)ns->ops; d = atomic_long_cmpxchg(&ns->stashed, 0, (unsigned long)dentry); if (d) { d_delete(dentry); /* make sure ->d_prune() does nothing */ diff -ruw linux-4.4.115/fs/open.c linux-4.4.115-fbx/fs/open.c --- linux-4.4.115/fs/open.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/fs/open.c 2019-10-29 09:26:25.365220030 +0100 @@ -34,8 +34,8 @@ #include "internal.h" -int do_truncate(struct dentry *dentry, loff_t length, unsigned int time_attrs, - struct file *filp) +int do_truncate2(struct vfsmount *mnt, struct dentry *dentry, loff_t length, + unsigned int time_attrs, struct file *filp) { int ret; struct iattr newattrs; @@ -60,17 +60,24 @@ mutex_lock(&dentry->d_inode->i_mutex); /* Note any delegations or leases have already been broken: */ - ret = notify_change(dentry, &newattrs, NULL); + ret = notify_change2(mnt, dentry, &newattrs, NULL); mutex_unlock(&dentry->d_inode->i_mutex); return ret; } +int do_truncate(struct dentry *dentry, loff_t length, unsigned int time_attrs, + struct file *filp) +{ + return do_truncate2(NULL, dentry, length, time_attrs, filp); +} long vfs_truncate(struct path *path, loff_t length) { struct inode *inode; + struct vfsmount *mnt; long error; inode = path->dentry->d_inode; + mnt = path->mnt; /* For directories it's -EISDIR, for other non-regulars - -EINVAL */ if (S_ISDIR(inode->i_mode)) @@ -82,7 +89,7 @@ if (error) goto out; - error = inode_permission(inode, MAY_WRITE); + error = inode_permission2(mnt, inode, MAY_WRITE); if (error) goto mnt_drop_write_and_out; @@ -106,7 +113,7 @@ if (!error) error = security_path_truncate(path); if (!error) - error = do_truncate(path->dentry, length, 0, NULL); + error = do_truncate2(mnt, path->dentry, length, 0, NULL); put_write_and_out: put_write_access(inode); @@ -155,6 +162,7 @@ { struct inode *inode; struct dentry *dentry; + struct vfsmount *mnt; struct fd f; int error; @@ -171,6 +179,7 @@ small = 0; dentry = f.file->f_path.dentry; + mnt = f.file->f_path.mnt; inode = dentry->d_inode; error = -EINVAL; if (!S_ISREG(inode->i_mode) || !(f.file->f_mode & FMODE_WRITE)) @@ -190,7 +199,7 @@ if (!error) error = security_path_truncate(&f.file->f_path); if (!error) - error = do_truncate(dentry, length, ATTR_MTIME|ATTR_CTIME, f.file); + error = do_truncate2(mnt, dentry, length, ATTR_MTIME|ATTR_CTIME, f.file); sb_end_write(inode->i_sb); out_putf: fdput(f); @@ -340,6 +349,7 @@ struct cred *override_cred; struct path path; struct inode *inode; + struct vfsmount *mnt; int res; unsigned int lookup_flags = LOOKUP_FOLLOW; @@ -370,6 +380,7 @@ goto out; inode = d_backing_inode(path.dentry); + mnt = path.mnt; if ((mode & MAY_EXEC) && S_ISREG(inode->i_mode)) { /* @@ -381,7 +392,7 @@ goto out_path_release; } - res = inode_permission(inode, mode | MAY_ACCESS); + res = inode_permission2(mnt, inode, mode | MAY_ACCESS); /* SuS v2 requires we report a read only fs too */ if (res || !(mode & S_IWOTH) || special_file(inode->i_mode)) goto out_path_release; @@ -425,7 +436,7 @@ if (error) goto out; - error = inode_permission(path.dentry->d_inode, MAY_EXEC | MAY_CHDIR); + error = inode_permission2(path.mnt, path.dentry->d_inode, MAY_EXEC | MAY_CHDIR); if (error) goto dput_and_out; @@ -445,6 +456,7 @@ { struct fd f = fdget_raw(fd); struct inode *inode; + struct vfsmount *mnt; int error = -EBADF; error = -EBADF; @@ -452,12 +464,13 @@ goto out; inode = file_inode(f.file); + mnt = f.file->f_path.mnt; error = -ENOTDIR; if (!S_ISDIR(inode->i_mode)) goto out_putf; - error = inode_permission(inode, MAY_EXEC | MAY_CHDIR); + error = inode_permission2(mnt, inode, MAY_EXEC | MAY_CHDIR); if (!error) set_fs_pwd(current->fs, &f.file->f_path); out_putf: @@ -476,7 +489,7 @@ if (error) goto out; - error = inode_permission(path.dentry->d_inode, MAY_EXEC | MAY_CHDIR); + error = inode_permission2(path.mnt, path.dentry->d_inode, MAY_EXEC | MAY_CHDIR); if (error) goto dput_and_out; @@ -516,7 +529,7 @@ goto out_unlock; newattrs.ia_mode = (mode & S_IALLUGO) | (inode->i_mode & ~S_IALLUGO); newattrs.ia_valid = ATTR_MODE | ATTR_CTIME; - error = notify_change(path->dentry, &newattrs, &delegated_inode); + error = notify_change2(path->mnt, path->dentry, &newattrs, &delegated_inode); out_unlock: mutex_unlock(&inode->i_mutex); if (delegated_inode) { @@ -596,7 +609,7 @@ mutex_lock(&inode->i_mutex); error = security_path_chown(path, uid, gid); if (!error) - error = notify_change(path->dentry, &newattrs, &delegated_inode); + error = notify_change2(path->mnt, path->dentry, &newattrs, &delegated_inode); mutex_unlock(&inode->i_mutex); if (delegated_inode) { error = break_deleg_wait(&delegated_inode); diff -ruw linux-4.4.115/fs/pnode.c linux-4.4.115-fbx/fs/pnode.c --- linux-4.4.115/fs/pnode.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/fs/pnode.c 2019-10-29 09:26:25.369220069 +0100 @@ -609,3 +609,37 @@ return 0; } + +/* + * Iterates over all slaves, and slaves of slaves. + */ +static struct mount *next_descendent(struct mount *root, struct mount *cur) +{ + if (!IS_MNT_NEW(cur) && !list_empty(&cur->mnt_slave_list)) + return first_slave(cur); + do { + struct mount *master = cur->mnt_master; + + if (!master || cur->mnt_slave.next != &master->mnt_slave_list) { + struct mount *next = next_slave(cur); + + return (next == root) ? NULL : next; + } + cur = master; + } while (cur != root); + return NULL; +} + +void propagate_remount(struct mount *mnt) +{ + struct mount *m = mnt; + struct super_block *sb = mnt->mnt.mnt_sb; + + if (sb->s_op->copy_mnt_data) { + m = next_descendent(mnt, m); + while (m) { + sb->s_op->copy_mnt_data(m->mnt.data, mnt->mnt.data); + m = next_descendent(mnt, m); + } + } +} diff -ruw linux-4.4.115/fs/pnode.h linux-4.4.115-fbx/fs/pnode.h --- linux-4.4.115/fs/pnode.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/fs/pnode.h 2019-01-22 16:16:28.031287410 +0100 @@ -44,6 +44,7 @@ int propagate_umount(struct list_head *); int propagate_mount_busy(struct mount *, int); void propagate_mount_unlock(struct mount *); +void propagate_remount(struct mount *); void mnt_release_group_id(struct mount *); int get_dominating_id(struct mount *mnt, const struct path *root); unsigned int mnt_get_count(struct mount *mnt); diff -ruw linux-4.4.115/fs/proc/array.c linux-4.4.115-fbx/fs/proc/array.c --- linux-4.4.115/fs/proc/array.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/fs/proc/array.c 2019-10-29 09:26:25.369220069 +0100 @@ -139,6 +139,21 @@ return task_state_array[fls(state)]; } +static const char *const task_exec_mode_array[] = { + "0 (Denied)", + "1 (Once)", + "2 (Unlimited)", +}; + +static inline const char *get_task_exec_mode(struct task_struct *tsk) +{ + unsigned int exec_mode = tsk->exec_mode; + + if (exec_mode > EXEC_MODE_UNLIMITED) + return "? (Invalid)"; + return task_exec_mode_array[exec_mode]; +} + static inline void task_state(struct seq_file *m, struct pid_namespace *ns, struct pid *pid, struct task_struct *p) { @@ -171,15 +186,15 @@ seq_printf(m, "State:\t%s\n" "Tgid:\t%d\n" - "Ngid:\t%d\n" "Pid:\t%d\n" "PPid:\t%d\n" "TracerPid:\t%d\n" "Uid:\t%d\t%d\t%d\t%d\n" "Gid:\t%d\t%d\t%d\t%d\n" + "Ngid:\t%d\n" "FDSize:\t%d\nGroups:\t", get_task_state(p), - tgid, ngid, pid_nr_ns(pid, ns), ppid, tpid, + tgid, pid_nr_ns(pid, ns), ppid, tpid, from_kuid_munged(user_ns, cred->uid), from_kuid_munged(user_ns, cred->euid), from_kuid_munged(user_ns, cred->suid), @@ -188,7 +203,7 @@ from_kgid_munged(user_ns, cred->egid), from_kgid_munged(user_ns, cred->sgid), from_kgid_munged(user_ns, cred->fsgid), - max_fds); + ngid, max_fds); group_info = cred->group_info; for (g = 0; g < group_info->ngroups; g++) @@ -343,6 +358,12 @@ p->nivcsw); } +static inline void task_exec_mode(struct seq_file *m, + struct task_struct *p) +{ + seq_printf(m, "Exec mode: %s\n", get_task_exec_mode(p)); +} + static void task_cpus_allowed(struct seq_file *m, struct task_struct *task) { seq_printf(m, "Cpus_allowed:\t%*pb\n", @@ -369,6 +390,7 @@ task_cpus_allowed(m, task); cpuset_task_status_allowed(m, task); task_context_switch_counts(m, task); + task_exec_mode(m, task); return 0; } diff -ruw linux-4.4.115/fs/proc/base.c linux-4.4.115-fbx/fs/proc/base.c --- linux-4.4.115/fs/proc/base.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/fs/proc/base.c 2019-10-29 09:26:25.373220108 +0100 @@ -1018,15 +1018,20 @@ int oom_adj = OOM_ADJUST_MIN; size_t len; unsigned long flags; + int mult = 1; if (!task) return -ESRCH; if (lock_task_sighand(task, &flags)) { - if (task->signal->oom_score_adj == OOM_SCORE_ADJ_MAX) + if (task->signal->oom_score_adj == OOM_SCORE_ADJ_MAX) { oom_adj = OOM_ADJUST_MAX; - else - oom_adj = (task->signal->oom_score_adj * -OOM_DISABLE) / - OOM_SCORE_ADJ_MAX; + } else { + if (task->signal->oom_score_adj < 0) + mult = -1; + oom_adj = roundup(mult * task->signal->oom_score_adj * + -OOM_DISABLE, OOM_SCORE_ADJ_MAX) / + OOM_SCORE_ADJ_MAX * mult; + } unlock_task_sighand(task, &flags); } put_task_struct(task); @@ -1410,6 +1415,204 @@ #endif +/* + * Print out various scheduling related per-task fields: + */ + +#ifdef CONFIG_SMP + +static int sched_wake_up_idle_show(struct seq_file *m, void *v) +{ + struct inode *inode = m->private; + struct task_struct *p; + + p = get_proc_task(inode); + if (!p) + return -ESRCH; + + seq_printf(m, "%d\n", sched_get_wake_up_idle(p)); + + put_task_struct(p); + + return 0; +} + +static ssize_t +sched_wake_up_idle_write(struct file *file, const char __user *buf, + size_t count, loff_t *offset) +{ + struct inode *inode = file_inode(file); + struct task_struct *p; + char buffer[PROC_NUMBUF]; + int wake_up_idle, err; + + memset(buffer, 0, sizeof(buffer)); + if (count > sizeof(buffer) - 1) + count = sizeof(buffer) - 1; + if (copy_from_user(buffer, buf, count)) { + err = -EFAULT; + goto out; + } + + err = kstrtoint(strstrip(buffer), 0, &wake_up_idle); + if (err) + goto out; + + p = get_proc_task(inode); + if (!p) + return -ESRCH; + + err = sched_set_wake_up_idle(p, wake_up_idle); + + put_task_struct(p); + +out: + return err < 0 ? err : count; +} + +static int sched_wake_up_idle_open(struct inode *inode, struct file *filp) +{ + return single_open(filp, sched_wake_up_idle_show, inode); +} + +static const struct file_operations proc_pid_sched_wake_up_idle_operations = { + .open = sched_wake_up_idle_open, + .read = seq_read, + .write = sched_wake_up_idle_write, + .llseek = seq_lseek, + .release = single_release, +}; + +#endif /* CONFIG_SMP */ + +#ifdef CONFIG_SCHED_HMP + +static int sched_init_task_load_show(struct seq_file *m, void *v) +{ + struct inode *inode = m->private; + struct task_struct *p; + + p = get_proc_task(inode); + if (!p) + return -ESRCH; + + seq_printf(m, "%d\n", sched_get_init_task_load(p)); + + put_task_struct(p); + + return 0; +} + +static ssize_t +sched_init_task_load_write(struct file *file, const char __user *buf, + size_t count, loff_t *offset) +{ + struct inode *inode = file_inode(file); + struct task_struct *p; + char buffer[PROC_NUMBUF]; + int init_task_load, err; + + memset(buffer, 0, sizeof(buffer)); + if (count > sizeof(buffer) - 1) + count = sizeof(buffer) - 1; + if (copy_from_user(buffer, buf, count)) { + err = -EFAULT; + goto out; + } + + err = kstrtoint(strstrip(buffer), 0, &init_task_load); + if (err) + goto out; + + p = get_proc_task(inode); + if (!p) + return -ESRCH; + + err = sched_set_init_task_load(p, init_task_load); + + put_task_struct(p); + +out: + return err < 0 ? err : count; +} + +static int sched_init_task_load_open(struct inode *inode, struct file *filp) +{ + return single_open(filp, sched_init_task_load_show, inode); +} + +static const struct file_operations proc_pid_sched_init_task_load_operations = { + .open = sched_init_task_load_open, + .read = seq_read, + .write = sched_init_task_load_write, + .llseek = seq_lseek, + .release = single_release, +}; + +static int sched_group_id_show(struct seq_file *m, void *v) +{ + struct inode *inode = m->private; + struct task_struct *p; + + p = get_proc_task(inode); + if (!p) + return -ESRCH; + + seq_printf(m, "%d\n", sched_get_group_id(p)); + + put_task_struct(p); + + return 0; +} + +static ssize_t +sched_group_id_write(struct file *file, const char __user *buf, + size_t count, loff_t *offset) +{ + struct inode *inode = file_inode(file); + struct task_struct *p; + char buffer[PROC_NUMBUF]; + int group_id, err; + + memset(buffer, 0, sizeof(buffer)); + if (count > sizeof(buffer) - 1) + count = sizeof(buffer) - 1; + if (copy_from_user(buffer, buf, count)) { + err = -EFAULT; + goto out; + } + + err = kstrtoint(strstrip(buffer), 0, &group_id); + if (err) + goto out; + + p = get_proc_task(inode); + if (!p) + return -ESRCH; + + err = sched_set_group_id(p, group_id); + + put_task_struct(p); + +out: + return err < 0 ? err : count; +} + +static int sched_group_id_open(struct inode *inode, struct file *filp) +{ + return single_open(filp, sched_group_id_show, inode); +} + +static const struct file_operations proc_pid_sched_group_id_operations = { + .open = sched_group_id_open, + .read = seq_read, + .write = sched_group_id_write, + .llseek = seq_lseek, + .release = single_release, +}; + +#endif /* CONFIG_SCHED_HMP */ + #ifdef CONFIG_SCHED_AUTOGROUP /* * Print out autogroup related information: @@ -2240,6 +2443,92 @@ .release = seq_release_private, }; +static ssize_t timerslack_ns_write(struct file *file, const char __user *buf, + size_t count, loff_t *offset) +{ + struct inode *inode = file_inode(file); + struct task_struct *p; + u64 slack_ns; + int err; + + err = kstrtoull_from_user(buf, count, 10, &slack_ns); + if (err < 0) + return err; + + p = get_proc_task(inode); + if (!p) + return -ESRCH; + + if (p != current) { + if (!capable(CAP_SYS_NICE)) { + count = -EPERM; + goto out; + } + + err = security_task_setscheduler(p); + if (err) { + count = err; + goto out; + } + } + + task_lock(p); + if (slack_ns == 0) + p->timer_slack_ns = p->default_timer_slack_ns; + else + p->timer_slack_ns = slack_ns; + task_unlock(p); + +out: + put_task_struct(p); + + return count; +} + +static int timerslack_ns_show(struct seq_file *m, void *v) +{ + struct inode *inode = m->private; + struct task_struct *p; + int err = 0; + + p = get_proc_task(inode); + if (!p) + return -ESRCH; + + if (p != current) { + + if (!capable(CAP_SYS_NICE)) { + err = -EPERM; + goto out; + } + err = security_task_getscheduler(p); + if (err) + goto out; + } + + task_lock(p); + seq_printf(m, "%llu\n", p->timer_slack_ns); + task_unlock(p); + +out: + put_task_struct(p); + + return err; +} + +static int timerslack_ns_open(struct inode *inode, struct file *filp) +{ + return single_open(filp, timerslack_ns_show, inode); +} + +static const struct file_operations proc_pid_set_timerslack_ns_operations = { + .open = timerslack_ns_open, + .read = seq_read, + .write = timerslack_ns_write, + .llseek = seq_lseek, + .release = single_release, +}; + static int proc_pident_instantiate(struct inode *dir, struct dentry *dentry, struct task_struct *task, const void *ptr) { @@ -2739,6 +3028,13 @@ ONE("status", S_IRUGO, proc_pid_status), ONE("personality", S_IRUSR, proc_pid_personality), ONE("limits", S_IRUGO, proc_pid_limits), +#ifdef CONFIG_SMP + REG("sched_wake_up_idle", S_IRUGO|S_IWUSR, proc_pid_sched_wake_up_idle_operations), +#endif +#ifdef CONFIG_SCHED_HMP + REG("sched_init_task_load", S_IRUGO|S_IWUSR, proc_pid_sched_init_task_load_operations), + REG("sched_group_id", S_IRUGO|S_IWUGO, proc_pid_sched_group_id_operations), +#endif #ifdef CONFIG_SCHED_DEBUG REG("sched", S_IRUGO|S_IWUSR, proc_pid_sched_operations), #endif @@ -2763,6 +3059,9 @@ REG("mounts", S_IRUGO, proc_mounts_operations), REG("mountinfo", S_IRUGO, proc_mountinfo_operations), REG("mountstats", S_IRUSR, proc_mountstats_operations), +#ifdef CONFIG_PROCESS_RECLAIM + REG("reclaim", S_IWUSR, proc_reclaim_operations), +#endif #ifdef CONFIG_PROC_PAGE_MONITOR REG("clear_refs", S_IWUSR, proc_clear_refs_operations), REG("smaps", S_IRUGO, proc_pid_smaps_operations), @@ -2790,8 +3089,8 @@ ONE("cgroup", S_IRUGO, proc_cgroup_show), #endif ONE("oom_score", S_IRUGO, proc_oom_score), - REG("oom_adj", S_IRUGO|S_IWUSR, proc_oom_adj_operations), - REG("oom_score_adj", S_IRUGO|S_IWUSR, proc_oom_score_adj_operations), + REG("oom_adj", S_IRUSR, proc_oom_adj_operations), + REG("oom_score_adj", S_IRUSR, proc_oom_score_adj_operations), #ifdef CONFIG_AUDITSYSCALL REG("loginuid", S_IWUSR|S_IRUGO, proc_loginuid_operations), REG("sessionid", S_IRUGO, proc_sessionid_operations), @@ -2817,6 +3116,7 @@ #ifdef CONFIG_CHECKPOINT_RESTORE REG("timers", S_IRUGO, proc_timers_operations), #endif + REG("timerslack_ns", S_IRUGO|S_IWUGO, proc_pid_set_timerslack_ns_operations), }; static int proc_tgid_base_readdir(struct file *file, struct dir_context *ctx) @@ -3076,6 +3376,44 @@ } /* + * proc_tid_comm_permission is a special permission function exclusively + * used for the node /proc//task//comm. + * It bypasses generic permission checks in the case where a task of the same + * task group attempts to access the node. + * The rational behind this is that glibc and bionic access this node for + * cross thread naming (pthread_set/getname_np(!self)). However, if + * PR_SET_DUMPABLE gets set to 0 this node among others becomes uid=0 gid=0, + * which locks out the cross thread naming implementation. + * This function makes sure that the node is always accessible for members of + * same thread group. + */ +static int proc_tid_comm_permission(struct inode *inode, int mask) +{ + bool is_same_tgroup; + struct task_struct *task; + + task = get_proc_task(inode); + if (!task) + return -ESRCH; + is_same_tgroup = same_thread_group(current, task); + put_task_struct(task); + + if (likely(is_same_tgroup && !(mask & MAY_EXEC))) { + /* This file (/proc//task//comm) can always be + * read or written by the members of the corresponding + * thread group. + */ + return 0; + } + + return generic_permission(inode, mask); +} + +static const struct inode_operations proc_tid_comm_inode_operations = { + .permission = proc_tid_comm_permission, +}; + +/* * Tasks */ static const struct pid_entry tid_base_stuff[] = { @@ -3093,7 +3431,9 @@ #ifdef CONFIG_SCHED_DEBUG REG("sched", S_IRUGO|S_IWUSR, proc_pid_sched_operations), #endif - REG("comm", S_IRUGO|S_IWUSR, proc_pid_set_comm_operations), + NOD("comm", S_IFREG|S_IRUGO|S_IWUSR, + &proc_tid_comm_inode_operations, + &proc_pid_set_comm_operations, {}), #ifdef CONFIG_HAVE_ARCH_TRACEHOOK ONE("syscall", S_IRUSR, proc_pid_syscall), #endif @@ -3140,8 +3480,8 @@ ONE("cgroup", S_IRUGO, proc_cgroup_show), #endif ONE("oom_score", S_IRUGO, proc_oom_score), - REG("oom_adj", S_IRUGO|S_IWUSR, proc_oom_adj_operations), - REG("oom_score_adj", S_IRUGO|S_IWUSR, proc_oom_score_adj_operations), + REG("oom_adj", S_IRUSR, proc_oom_adj_operations), + REG("oom_score_adj", S_IRUSR, proc_oom_score_adj_operations), #ifdef CONFIG_AUDITSYSCALL REG("loginuid", S_IWUSR|S_IRUGO, proc_loginuid_operations), REG("sessionid", S_IRUGO, proc_sessionid_operations), diff -ruw linux-4.4.115/fs/proc/internal.h linux-4.4.115-fbx/fs/proc/internal.h --- linux-4.4.115/fs/proc/internal.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/fs/proc/internal.h 2019-10-29 09:26:25.373220108 +0100 @@ -209,6 +209,7 @@ extern const struct inode_operations proc_link_inode_operations; extern const struct inode_operations proc_pid_link_inode_operations; +extern const struct file_operations proc_reclaim_operations; extern void proc_init_inodecache(void); extern struct inode *proc_get_inode(struct super_block *, struct proc_dir_entry *); diff -ruw linux-4.4.115/fs/proc/meminfo.c linux-4.4.115-fbx/fs/proc/meminfo.c --- linux-4.4.115/fs/proc/meminfo.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/fs/proc/meminfo.c 2019-10-29 09:26:25.373220108 +0100 @@ -79,6 +79,13 @@ available += global_page_state(NR_SLAB_RECLAIMABLE) - min(global_page_state(NR_SLAB_RECLAIMABLE) / 2, wmark_low); + /* + * Part of the kernel memory, which can be released under memory + * pressure. + */ + available += global_page_state(NR_INDIRECTLY_RECLAIMABLE_BYTES) >> + PAGE_SHIFT; + if (available < 0) available = 0; diff -ruw linux-4.4.115/fs/proc/task_mmu.c linux-4.4.115-fbx/fs/proc/task_mmu.c --- linux-4.4.115/fs/proc/task_mmu.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/fs/proc/task_mmu.c 2019-10-29 09:26:25.373220108 +0100 @@ -14,6 +14,8 @@ #include #include #include +#include +#include #include #include @@ -116,6 +118,56 @@ } #endif +static void seq_print_vma_name(struct seq_file *m, struct vm_area_struct *vma) +{ + const char __user *name = vma_get_anon_name(vma); + struct mm_struct *mm = vma->vm_mm; + + unsigned long page_start_vaddr; + unsigned long page_offset; + unsigned long num_pages; + unsigned long max_len = NAME_MAX; + int i; + + page_start_vaddr = (unsigned long)name & PAGE_MASK; + page_offset = (unsigned long)name - page_start_vaddr; + num_pages = DIV_ROUND_UP(page_offset + max_len, PAGE_SIZE); + + seq_puts(m, "[anon:"); + + for (i = 0; i < num_pages; i++) { + int len; + int write_len; + const char *kaddr; + long pages_pinned; + struct page *page; + + pages_pinned = get_user_pages(current, mm, page_start_vaddr, + 1, 0, 0, &page, NULL); + if (pages_pinned < 1) { + seq_puts(m, "]"); + return; + } + + kaddr = (const char *)kmap(page); + len = min(max_len, PAGE_SIZE - page_offset); + write_len = strnlen(kaddr + page_offset, len); + seq_write(m, kaddr + page_offset, write_len); + kunmap(page); + put_page(page); + + /* if strnlen hit a null terminator then we're done */ + if (write_len != len) + break; + + max_len -= len; + page_offset = 0; + page_start_vaddr += PAGE_SIZE; + } + + seq_putc(m, ']'); +} + static void vma_stop(struct proc_maps_private *priv) { struct mm_struct *mm = priv->mm; @@ -337,8 +389,14 @@ goto done; } - if (is_stack(priv, vma, is_pid)) + if (is_stack(priv, vma, is_pid)) { name = "[stack]"; + goto done; + } + if (vma_get_anon_name(vma)) { + seq_pad(m, ' '); + seq_print_vma_name(m, vma); + } } done: @@ -663,6 +721,12 @@ show_map_vma(m, vma, is_pid); + if (vma_get_anon_name(vma)) { + seq_puts(m, "Name: "); + seq_print_vma_name(m, vma); + seq_putc(m, '\n'); + } + seq_printf(m, "Size: %8lu kB\n" "Rss: %8lu kB\n" @@ -1361,6 +1425,241 @@ }; #endif /* CONFIG_PROC_PAGE_MONITOR */ +#ifdef CONFIG_PROCESS_RECLAIM +static int reclaim_pte_range(pmd_t *pmd, unsigned long addr, + unsigned long end, struct mm_walk *walk) +{ + struct reclaim_param *rp = walk->private; + struct vm_area_struct *vma = rp->vma; + pte_t *pte, ptent; + spinlock_t *ptl; + struct page *page; + LIST_HEAD(page_list); + int isolated; + int reclaimed; + + split_huge_page_pmd(vma, addr, pmd); + if (pmd_trans_unstable(pmd) || !rp->nr_to_reclaim) + return 0; +cont: + isolated = 0; + pte = pte_offset_map_lock(vma->vm_mm, pmd, addr, &ptl); + for (; addr != end; pte++, addr += PAGE_SIZE) { + ptent = *pte; + if (!pte_present(ptent)) + continue; + + page = vm_normal_page(vma, addr, ptent); + if (!page) + continue; + + if (isolate_lru_page(page)) + continue; + + list_add(&page->lru, &page_list); + inc_zone_page_state(page, NR_ISOLATED_ANON + + page_is_file_cache(page)); + isolated++; + rp->nr_scanned++; + if ((isolated >= SWAP_CLUSTER_MAX) || !rp->nr_to_reclaim) + break; + } + pte_unmap_unlock(pte - 1, ptl); + reclaimed = reclaim_pages_from_list(&page_list, vma); + rp->nr_reclaimed += reclaimed; + rp->nr_to_reclaim -= reclaimed; + if (rp->nr_to_reclaim < 0) + rp->nr_to_reclaim = 0; + + if (rp->nr_to_reclaim && (addr != end)) + goto cont; + + cond_resched(); + return 0; +} + +enum reclaim_type { + RECLAIM_FILE, + RECLAIM_ANON, + RECLAIM_ALL, + RECLAIM_RANGE, +}; + +struct reclaim_param reclaim_task_anon(struct task_struct *task, + int nr_to_reclaim) +{ + struct mm_struct *mm; + struct vm_area_struct *vma; + struct mm_walk reclaim_walk = {}; + struct reclaim_param rp; + + rp.nr_reclaimed = 0; + rp.nr_scanned = 0; + get_task_struct(task); + mm = get_task_mm(task); + if (!mm) + goto out; + + reclaim_walk.mm = mm; + reclaim_walk.pmd_entry = reclaim_pte_range; + + rp.nr_to_reclaim = nr_to_reclaim; + reclaim_walk.private = &rp; + + down_read(&mm->mmap_sem); + for (vma = mm->mmap; vma; vma = vma->vm_next) { + if (is_vm_hugetlb_page(vma)) + continue; + + if (vma->vm_file) + continue; + + if (vma->vm_flags & VM_LOCKED) + continue; + + if (!rp.nr_to_reclaim) + break; + + rp.vma = vma; + walk_page_range(vma->vm_start, vma->vm_end, + &reclaim_walk); + } + + flush_tlb_mm(mm); + up_read(&mm->mmap_sem); + mmput(mm); +out: + put_task_struct(task); + return rp; +} + +static ssize_t reclaim_write(struct file *file, const char __user *buf, + size_t count, loff_t *ppos) +{ + struct task_struct *task; + char buffer[200]; + struct mm_struct *mm; + struct vm_area_struct *vma; + enum reclaim_type type; + char *type_buf; + struct mm_walk reclaim_walk = {}; + unsigned long start = 0; + unsigned long end = 0; + struct reclaim_param rp; + + memset(buffer, 0, sizeof(buffer)); + if (count > sizeof(buffer) - 1) + count = sizeof(buffer) - 1; + + if (copy_from_user(buffer, buf, count)) + return -EFAULT; + + type_buf = strstrip(buffer); + if (!strcmp(type_buf, "file")) + type = RECLAIM_FILE; + else if (!strcmp(type_buf, "anon")) + type = RECLAIM_ANON; + else if (!strcmp(type_buf, "all")) + type = RECLAIM_ALL; + else if (isdigit(*type_buf)) + type = RECLAIM_RANGE; + else + goto out_err; + + if (type == RECLAIM_RANGE) { + char *token; + unsigned long long len, len_in, tmp; + token = strsep(&type_buf, " "); + if (!token) + goto out_err; + tmp = memparse(token, &token); + if (tmp & ~PAGE_MASK || tmp > ULONG_MAX) + goto out_err; + start = tmp; + + token = strsep(&type_buf, " "); + if (!token) + goto out_err; + len_in = memparse(token, &token); + len = (len_in + ~PAGE_MASK) & PAGE_MASK; + if (len > ULONG_MAX) + goto out_err; + /* + * Check to see whether len was rounded up from small -ve + * to zero. + */ + if (len_in && !len) + goto out_err; + + end = start + len; + if (end < start) + goto out_err; + } + + task = get_proc_task(file->f_path.dentry->d_inode); + if (!task) + return -ESRCH; + + mm = get_task_mm(task); + if (!mm) + goto out; + + reclaim_walk.mm = mm; + reclaim_walk.pmd_entry = reclaim_pte_range; + + rp.nr_to_reclaim = ~0; + rp.nr_reclaimed = 0; + reclaim_walk.private = &rp; + + down_read(&mm->mmap_sem); + if (type == RECLAIM_RANGE) { + vma = find_vma(mm, start); + while (vma) { + if (vma->vm_start > end) + break; + if (is_vm_hugetlb_page(vma)) + continue; + + rp.vma = vma; + walk_page_range(max(vma->vm_start, start), + min(vma->vm_end, end), + &reclaim_walk); + vma = vma->vm_next; + } + } else { + for (vma = mm->mmap; vma; vma = vma->vm_next) { + if (is_vm_hugetlb_page(vma)) + continue; + + if (type == RECLAIM_ANON && vma->vm_file) + continue; + + if (type == RECLAIM_FILE && !vma->vm_file) + continue; + + rp.vma = vma; + walk_page_range(vma->vm_start, vma->vm_end, + &reclaim_walk); + } + } + + flush_tlb_mm(mm); + up_read(&mm->mmap_sem); + mmput(mm); +out: + put_task_struct(task); + return count; + +out_err: + return -EINVAL; +} + +const struct file_operations proc_reclaim_operations = { + .write = reclaim_write, + .llseek = noop_llseek, +}; +#endif + #ifdef CONFIG_NUMA struct numa_maps { diff -ruw linux-4.4.115/fs/proc_namespace.c linux-4.4.115-fbx/fs/proc_namespace.c --- linux-4.4.115/fs/proc_namespace.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/fs/proc_namespace.c 2019-01-22 16:16:28.039287483 +0100 @@ -118,7 +118,9 @@ if (err) goto out; show_mnt_opts(m, mnt); - if (sb->s_op->show_options) + if (sb->s_op->show_options2) + err = sb->s_op->show_options2(mnt, m, mnt_path.dentry); + else if (sb->s_op->show_options) err = sb->s_op->show_options(m, mnt_path.dentry); seq_puts(m, " 0 0\n"); out: @@ -178,7 +180,9 @@ err = show_sb_opts(m, sb); if (err) goto out; - if (sb->s_op->show_options) + if (sb->s_op->show_options2) { + err = sb->s_op->show_options2(mnt, m, mnt->mnt_root); + } else if (sb->s_op->show_options) err = sb->s_op->show_options(m, mnt->mnt_root); seq_putc(m, '\n'); out: diff -ruw linux-4.4.115/fs/pstore/platform.c linux-4.4.115-fbx/fs/pstore/platform.c --- linux-4.4.115/fs/pstore/platform.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/fs/pstore/platform.c 2019-10-29 09:26:25.377220147 +0100 @@ -431,6 +431,40 @@ size, psi); } +static int pstore_write_buf_user_compat(enum pstore_type_id type, + enum kmsg_dump_reason reason, + u64 *id, unsigned int part, + const char __user *buf, + bool compressed, size_t size, + struct pstore_info *psi) +{ + unsigned long flags = 0; + size_t i, bufsize = size; + long ret = 0; + + if (unlikely(!access_ok(VERIFY_READ, buf, size))) + return -EFAULT; + if (bufsize > psinfo->bufsize) + bufsize = psinfo->bufsize; + spin_lock_irqsave(&psinfo->buf_lock, flags); + for (i = 0; i < size; ) { + size_t c = min(size - i, bufsize); + + ret = __copy_from_user(psinfo->buf, buf + i, c); + if (unlikely(ret != 0)) { + ret = -EFAULT; + break; + } + ret = psi->write_buf(type, reason, id, part, psinfo->buf, + compressed, c, psi); + if (unlikely(ret < 0)) + break; + i += c; + } + spin_unlock_irqrestore(&psinfo->buf_lock, flags); + return unlikely(ret < 0) ? ret : size; +} + /* * platform specific persistent storage driver registers with * us here. If pstore is already mounted, call the platform @@ -453,6 +487,8 @@ if (!psi->write) psi->write = pstore_write_compat; + if (!psi->write_buf_user) + psi->write_buf_user = pstore_write_buf_user_compat; psinfo = psi; mutex_init(&psinfo->read_mutex); spin_unlock(&pstore_lock); diff -ruw linux-4.4.115/fs/pstore/ram.c linux-4.4.115-fbx/fs/pstore/ram.c --- linux-4.4.115/fs/pstore/ram.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/fs/pstore/ram.c 2019-01-22 16:16:28.043287519 +0100 @@ -34,6 +34,8 @@ #include #include #include +#include +#include #define RAMOOPS_KERNMSG_HDR "====" #define MIN_MEM_SIZE 4096UL @@ -329,6 +331,24 @@ return 0; } +static int notrace ramoops_pstore_write_buf_user(enum pstore_type_id type, + enum kmsg_dump_reason reason, + u64 *id, unsigned int part, + const char __user *buf, + bool compressed, size_t size, + struct pstore_info *psi) +{ + if (type == PSTORE_TYPE_PMSG) { + struct ramoops_context *cxt = psi->data; + + if (!cxt->mprz) + return -ENOMEM; + return persistent_ram_write_user(cxt->mprz, buf, size); + } + + return -EINVAL; +} + static int ramoops_pstore_erase(enum pstore_type_id type, u64 id, int count, struct timespec time, struct pstore_info *psi) { @@ -367,6 +387,7 @@ .open = ramoops_pstore_open, .read = ramoops_pstore_read, .write_buf = ramoops_pstore_write_buf, + .write_buf_user = ramoops_pstore_write_buf_user, .erase = ramoops_pstore_erase, }, }; @@ -467,6 +488,97 @@ return 0; } +void notrace ramoops_console_write_buf(const char *buf, size_t size) +{ + struct ramoops_context *cxt = &oops_cxt; + persistent_ram_write(cxt->cprz, buf, size); +} + +static int ramoops_parse_dt_size(struct platform_device *pdev, + const char *propname, unsigned long *val) +{ + u32 val64; + int ret; + + ret = of_property_read_u32(pdev->dev.of_node, propname, &val64); + if (ret == -EINVAL) { + *val = 0; + return 0; + } else if (ret != 0) { + dev_err(&pdev->dev, "failed to parse property %s: %d\n", + propname, ret); + return ret; + } + + if (val64 > ULONG_MAX) { + dev_err(&pdev->dev, "invalid %s %u\n", propname, val64); + return -EOVERFLOW; + } + + *val = val64; + return 0; +} + +static int ramoops_parse_dt(struct platform_device *pdev, + struct ramoops_platform_data *pdata) +{ + struct device_node *of_node = pdev->dev.of_node; + struct device_node *mem_region; + struct resource res; + u32 ecc_size; + int ret; + + dev_dbg(&pdev->dev, "using Device Tree\n"); + + mem_region = of_parse_phandle(of_node, "memory-region", 0); + if (!mem_region) { + dev_err(&pdev->dev, "no memory-region phandle\n"); + return -ENODEV; + } + + ret = of_address_to_resource(mem_region, 0, &res); + of_node_put(mem_region); + if (ret) { + dev_err(&pdev->dev, "failed to translate memory-region to resource: %d\n", + ret); + return ret; + } + + pdata->mem_size = resource_size(&res); + pdata->mem_address = res.start; + pdata->mem_type = of_property_read_bool(of_node, "unbuffered"); + pdata->dump_oops = !of_property_read_bool(of_node, "no-dump-oops"); + + ret = ramoops_parse_dt_size(pdev, "record-size", &pdata->record_size); + if (ret < 0) + return ret; + + ret = ramoops_parse_dt_size(pdev, "console-size", &pdata->console_size); + if (ret < 0) + return ret; + + ret = ramoops_parse_dt_size(pdev, "ftrace-size", &pdata->ftrace_size); + if (ret < 0) + return ret; + + ret = ramoops_parse_dt_size(pdev, "pmsg-size", &pdata->pmsg_size); + if (ret < 0) + return ret; + + ret = of_property_read_u32(of_node, "ecc-size", &ecc_size); + if (ret == 0) { + if (ecc_size > INT_MAX) { + dev_err(&pdev->dev, "invalid ecc-size %u\n", ecc_size); + return -EOVERFLOW; + } + pdata->ecc_info.ecc_size = ecc_size; + } else if (ret != -EINVAL) { + return ret; + } + + return 0; +} + static int ramoops_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; @@ -476,6 +588,18 @@ phys_addr_t paddr; int err = -EINVAL; + if (dev->of_node && !pdata) { + pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL); + if (!pdata) { + err = -ENOMEM; + goto fail_out; + } + + err = ramoops_parse_dt(pdev, pdata); + if (err < 0) + goto fail_out; + } + /* Only a single ramoops area allowed at a time, so fail extra * probes. */ @@ -604,11 +728,17 @@ return 0; } +static const struct of_device_id dt_match[] = { + { .compatible = "ramoops" }, + {} +}; + static struct platform_driver ramoops_driver = { .probe = ramoops_probe, .remove = ramoops_remove, .driver = { .name = "ramoops", + .of_match_table = dt_match, }, }; diff -ruw linux-4.4.115/fs/pstore/ram_core.c linux-4.4.115-fbx/fs/pstore/ram_core.c --- linux-4.4.115/fs/pstore/ram_core.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/fs/pstore/ram_core.c 2019-10-29 09:26:25.377220147 +0100 @@ -17,15 +17,16 @@ #include #include #include -#include #include #include +#include #include #include +#include #include #include +#include #include -#include #include struct persistent_ram_buffer { @@ -269,6 +270,16 @@ persistent_ram_update_ecc(prz, start, count); } +static int notrace persistent_ram_update_user(struct persistent_ram_zone *prz, + const void __user *s, unsigned int start, unsigned int count) +{ + struct persistent_ram_buffer *buffer = prz->buffer; + int ret = unlikely(__copy_from_user(buffer->data + start, s, count)) ? + -EFAULT : 0; + persistent_ram_update_ecc(prz, start, count); + return ret; +} + void persistent_ram_save_old(struct persistent_ram_zone *prz) { struct persistent_ram_buffer *buffer = prz->buffer; @@ -322,6 +333,38 @@ return count; } +int notrace persistent_ram_write_user(struct persistent_ram_zone *prz, + const void __user *s, unsigned int count) +{ + int rem, ret = 0, c = count; + size_t start; + + if (unlikely(!access_ok(VERIFY_READ, s, count))) + return -EFAULT; + if (unlikely(c > prz->buffer_size)) { + s += c - prz->buffer_size; + c = prz->buffer_size; + } + + buffer_size_add(prz, c); + + start = buffer_start_add(prz, c); + + rem = prz->buffer_size - start; + if (unlikely(rem < c)) { + ret = persistent_ram_update_user(prz, s, start, rem); + s += rem; + c -= rem; + start = 0; + } + if (likely(!ret)) + ret = persistent_ram_update_user(prz, s, start, c); + + persistent_ram_update_header_ecc(prz); + + return unlikely(ret) ? ret : count; +} + size_t persistent_ram_old_size(struct persistent_ram_zone *prz) { return prz->old_log_size; diff -ruw linux-4.4.115/fs/select.c linux-4.4.115-fbx/fs/select.c --- linux-4.4.115/fs/select.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/fs/select.c 2019-01-22 16:16:28.063287700 +0100 @@ -71,9 +71,9 @@ return slack; } -long select_estimate_accuracy(struct timespec *tv) +u64 select_estimate_accuracy(struct timespec *tv) { - unsigned long ret; + u64 ret; struct timespec now; /* @@ -403,7 +403,7 @@ struct poll_wqueues table; poll_table *wait; int retval, i, timed_out = 0; - unsigned long slack = 0; + u64 slack = 0; unsigned int busy_flag = net_busy_loop_on() ? POLL_BUSY_LOOP : 0; unsigned long busy_end = 0; @@ -792,7 +792,7 @@ poll_table* pt = &wait->pt; ktime_t expire, *to = NULL; int timed_out = 0, count = 0; - unsigned long slack = 0; + u64 slack = 0; unsigned int busy_flag = net_busy_loop_on() ? POLL_BUSY_LOOP : 0; unsigned long busy_end = 0; diff -ruw linux-4.4.115/fs/squashfs/block.c linux-4.4.115-fbx/fs/squashfs/block.c --- linux-4.4.115/fs/squashfs/block.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/fs/squashfs/block.c 2019-10-29 09:26:25.385220225 +0100 @@ -28,9 +28,12 @@ #include #include +#include #include #include +#include #include +#include #include "squashfs_fs.h" #include "squashfs_fs_sb.h" @@ -38,177 +41,435 @@ #include "decompressor.h" #include "page_actor.h" +static struct workqueue_struct *squashfs_read_wq; + +struct squashfs_read_request { + struct super_block *sb; + u64 index; + int length; + int compressed; + int offset; + u64 read_end; + struct squashfs_page_actor *output; + enum { + SQUASHFS_COPY, + SQUASHFS_DECOMPRESS, + SQUASHFS_METADATA, + } data_processing; + bool synchronous; + /* - * Read the metadata block length, this is stored in the first two - * bytes of the metadata block. + * If the read is synchronous, it is possible to retrieve information + * about the request by setting these pointers. */ -static struct buffer_head *get_block_length(struct super_block *sb, - u64 *cur_index, int *offset, int *length) + int *res; + int *bytes_read; + int *bytes_uncompressed; + + int nr_buffers; + struct buffer_head **bh; + struct work_struct offload; +}; + +struct squashfs_bio_request { + struct buffer_head **bh; + int nr_buffers; +}; + +static int squashfs_bio_submit(struct squashfs_read_request *req); + +int squashfs_init_read_wq(void) { - struct squashfs_sb_info *msblk = sb->s_fs_info; - struct buffer_head *bh; + squashfs_read_wq = create_workqueue("SquashFS read wq"); + return !!squashfs_read_wq; +} - bh = sb_bread(sb, *cur_index); - if (bh == NULL) - return NULL; - - if (msblk->devblksize - *offset == 1) { - *length = (unsigned char) bh->b_data[*offset]; - put_bh(bh); - bh = sb_bread(sb, ++(*cur_index)); - if (bh == NULL) - return NULL; - *length |= (unsigned char) bh->b_data[0] << 8; - *offset = 1; - } else { - *length = (unsigned char) bh->b_data[*offset] | - (unsigned char) bh->b_data[*offset + 1] << 8; - *offset += 2; +void squashfs_destroy_read_wq(void) +{ + flush_workqueue(squashfs_read_wq); + destroy_workqueue(squashfs_read_wq); +} - if (*offset == msblk->devblksize) { - put_bh(bh); - bh = sb_bread(sb, ++(*cur_index)); - if (bh == NULL) - return NULL; - *offset = 0; +static void free_read_request(struct squashfs_read_request *req, int error) +{ + if (!req->synchronous) + squashfs_page_actor_free(req->output, error); + if (req->res) + *(req->res) = error; + kfree(req->bh); + kfree(req); } + +static void squashfs_process_blocks(struct squashfs_read_request *req) +{ + int error = 0; + int bytes, i, length; + struct squashfs_sb_info *msblk = req->sb->s_fs_info; + struct squashfs_page_actor *actor = req->output; + struct buffer_head **bh = req->bh; + int nr_buffers = req->nr_buffers; + + for (i = 0; i < nr_buffers; ++i) { + if (!bh[i]) + continue; + wait_on_buffer(bh[i]); + if (!buffer_uptodate(bh[i])) + error = -EIO; } + if (error) + goto cleanup; - return bh; + if (req->data_processing == SQUASHFS_METADATA) { + /* Extract the length of the metadata block */ + if (req->offset != msblk->devblksize - 1) { + length = le16_to_cpup((__le16 *) + (bh[0]->b_data + req->offset)); + } else { + length = (unsigned char)bh[0]->b_data[req->offset]; + length |= (unsigned char)bh[1]->b_data[0] << 8; + } + req->compressed = SQUASHFS_COMPRESSED(length); + req->data_processing = req->compressed ? SQUASHFS_DECOMPRESS + : SQUASHFS_COPY; + length = SQUASHFS_COMPRESSED_SIZE(length); + if (req->index + length + 2 > req->read_end) { + for (i = 0; i < nr_buffers; ++i) + put_bh(bh[i]); + kfree(bh); + req->length = length; + req->index += 2; + squashfs_bio_submit(req); + return; + } + req->length = length; + req->offset = (req->offset + 2) % PAGE_SIZE; + if (req->offset < 2) { + put_bh(bh[0]); + ++bh; + --nr_buffers; + } + } + if (req->bytes_read) + *(req->bytes_read) = req->length; + + if (req->data_processing == SQUASHFS_COPY) { + squashfs_bh_to_actor(bh, nr_buffers, req->output, req->offset, + req->length, msblk->devblksize); + } else if (req->data_processing == SQUASHFS_DECOMPRESS) { + req->length = squashfs_decompress(msblk, bh, nr_buffers, + req->offset, req->length, actor); + if (req->length < 0) { + error = -EIO; + goto cleanup; + } } + /* Last page may have trailing bytes not filled */ + bytes = req->length % PAGE_SIZE; + if (bytes && actor->page[actor->pages - 1]) + zero_user_segment(actor->page[actor->pages - 1], bytes, + PAGE_SIZE); + +cleanup: + if (req->bytes_uncompressed) + *(req->bytes_uncompressed) = req->length; + if (error) { + for (i = 0; i < nr_buffers; ++i) + if (bh[i]) + put_bh(bh[i]); + } + free_read_request(req, error); +} -/* - * Read and decompress a metadata block or datablock. Length is non-zero - * if a datablock is being read (the size is stored elsewhere in the - * filesystem), otherwise the length is obtained from the first two bytes of - * the metadata block. A bit in the length field indicates if the block - * is stored uncompressed in the filesystem (usually because compression - * generated a larger block - this does occasionally happen with compression - * algorithms). - */ -int squashfs_read_data(struct super_block *sb, u64 index, int length, - u64 *next_index, struct squashfs_page_actor *output) +static void read_wq_handler(struct work_struct *work) { - struct squashfs_sb_info *msblk = sb->s_fs_info; - struct buffer_head **bh; - int offset = index & ((1 << msblk->devblksize_log2) - 1); - u64 cur_index = index >> msblk->devblksize_log2; - int bytes, compressed, b = 0, k = 0, avail, i; - - bh = kcalloc(((output->length + msblk->devblksize - 1) - >> msblk->devblksize_log2) + 1, sizeof(*bh), GFP_KERNEL); - if (bh == NULL) - return -ENOMEM; + squashfs_process_blocks(container_of(work, + struct squashfs_read_request, offload)); +} - if (length) { - /* - * Datablock. - */ - bytes = -offset; - compressed = SQUASHFS_COMPRESSED_BLOCK(length); - length = SQUASHFS_COMPRESSED_SIZE_BLOCK(length); - if (next_index) - *next_index = index + length; +static void squashfs_bio_end_io(struct bio *bio) +{ + int i; + int error = bio->bi_error; + struct squashfs_bio_request *bio_req = bio->bi_private; - TRACE("Block @ 0x%llx, %scompressed size %d, src size %d\n", - index, compressed ? "" : "un", length, output->length); + bio_put(bio); - if (length < 0 || length > output->length || - (index + length) > msblk->bytes_used) - goto read_failure; - - for (b = 0; bytes < length; b++, cur_index++) { - bh[b] = sb_getblk(sb, cur_index); - if (bh[b] == NULL) - goto block_release; - bytes += msblk->devblksize; + for (i = 0; i < bio_req->nr_buffers; ++i) { + if (!bio_req->bh[i]) + continue; + if (!error) + set_buffer_uptodate(bio_req->bh[i]); + else + clear_buffer_uptodate(bio_req->bh[i]); + unlock_buffer(bio_req->bh[i]); + } + kfree(bio_req); } - ll_rw_block(READ, b, bh); - } else { - /* - * Metadata block. - */ - if ((index + 2) > msblk->bytes_used) - goto read_failure; - bh[0] = get_block_length(sb, &cur_index, &offset, &length); - if (bh[0] == NULL) - goto read_failure; - b = 1; +static int bh_is_optional(struct squashfs_read_request *req, int idx) +{ + int start_idx, end_idx; + struct squashfs_sb_info *msblk = req->sb->s_fs_info; - bytes = msblk->devblksize - offset; - compressed = SQUASHFS_COMPRESSED(length); - length = SQUASHFS_COMPRESSED_SIZE(length); - if (next_index) - *next_index = index + length + 2; + start_idx = (idx * msblk->devblksize - req->offset) >> PAGE_SHIFT; + end_idx = ((idx + 1) * msblk->devblksize - req->offset + 1) >> PAGE_SHIFT; + if (start_idx >= req->output->pages) + return 1; + if (start_idx < 0) + start_idx = end_idx; + if (end_idx >= req->output->pages) + end_idx = start_idx; + return !req->output->page[start_idx] && !req->output->page[end_idx]; +} - TRACE("Block @ 0x%llx, %scompressed size %d\n", index, - compressed ? "" : "un", length); +static int actor_getblks(struct squashfs_read_request *req, u64 block) +{ + int i; - if (length < 0 || length > output->length || - (index + length) > msblk->bytes_used) - goto block_release; + req->bh = kmalloc_array(req->nr_buffers, sizeof(*(req->bh)), GFP_NOIO); + if (!req->bh) + return -ENOMEM; - for (; bytes < length; b++) { - bh[b] = sb_getblk(sb, ++cur_index); - if (bh[b] == NULL) - goto block_release; - bytes += msblk->devblksize; + for (i = 0; i < req->nr_buffers; ++i) { + /* + * When dealing with an uncompressed block, the actor may + * contains NULL pages. There's no need to read the buffers + * associated with these pages. + */ + if (!req->compressed && bh_is_optional(req, i)) { + req->bh[i] = NULL; + continue; + } + req->bh[i] = sb_getblk(req->sb, block + i); + if (!req->bh[i]) { + while (--i) { + if (req->bh[i]) + put_bh(req->bh[i]); } - ll_rw_block(READ, b - 1, bh + 1); + return -1; + } + } + return 0; } - for (i = 0; i < b; i++) { - wait_on_buffer(bh[i]); - if (!buffer_uptodate(bh[i])) - goto block_release; +static int squashfs_bio_submit(struct squashfs_read_request *req) +{ + struct bio *bio = NULL; + struct buffer_head *bh; + struct squashfs_bio_request *bio_req = NULL; + int b = 0, prev_block = 0; + struct squashfs_sb_info *msblk = req->sb->s_fs_info; + + u64 read_start = round_down(req->index, msblk->devblksize); + u64 read_end = round_up(req->index + req->length, msblk->devblksize); + sector_t block = read_start >> msblk->devblksize_log2; + sector_t block_end = read_end >> msblk->devblksize_log2; + int offset = read_start - round_down(req->index, PAGE_SIZE); + int nr_buffers = block_end - block; + int blksz = msblk->devblksize; + int bio_max_pages = nr_buffers > BIO_MAX_PAGES ? BIO_MAX_PAGES + : nr_buffers; + + /* Setup the request */ + req->read_end = read_end; + req->offset = req->index - read_start; + req->nr_buffers = nr_buffers; + if (actor_getblks(req, block) < 0) + goto getblk_failed; + + /* Create and submit the BIOs */ + for (b = 0; b < nr_buffers; ++b, offset += blksz) { + bh = req->bh[b]; + if (!bh || !trylock_buffer(bh)) + continue; + if (buffer_uptodate(bh)) { + unlock_buffer(bh); + continue; + } + offset %= PAGE_SIZE; + + /* Append the buffer to the current BIO if it is contiguous */ + if (bio && bio_req && prev_block + 1 == b) { + if (bio_add_page(bio, bh->b_page, blksz, offset)) { + bio_req->nr_buffers += 1; + prev_block = b; + continue; + } + } + + /* Otherwise, submit the current BIO and create a new one */ + if (bio) + submit_bio(READ, bio); + bio_req = kcalloc(1, sizeof(struct squashfs_bio_request), + GFP_NOIO); + if (!bio_req) + goto req_alloc_failed; + bio_req->bh = &req->bh[b]; + bio = bio_alloc(GFP_NOIO, bio_max_pages); + if (!bio) + goto bio_alloc_failed; + bio->bi_bdev = req->sb->s_bdev; + bio->bi_iter.bi_sector = (block + b) + << (msblk->devblksize_log2 - 9); + bio->bi_private = bio_req; + bio->bi_end_io = squashfs_bio_end_io; + + bio_add_page(bio, bh->b_page, blksz, offset); + bio_req->nr_buffers += 1; + prev_block = b; + } + if (bio) + submit_bio(READ, bio); + + if (req->synchronous) + squashfs_process_blocks(req); + else { + INIT_WORK(&req->offload, read_wq_handler); + schedule_work(&req->offload); + } + return 0; + +bio_alloc_failed: + kfree(bio_req); +req_alloc_failed: + unlock_buffer(bh); + while (--nr_buffers >= b) + if (req->bh[nr_buffers]) + put_bh(req->bh[nr_buffers]); + while (--b >= 0) + if (req->bh[b]) + wait_on_buffer(req->bh[b]); +getblk_failed: + free_read_request(req, -ENOMEM); + return -ENOMEM; } - if (compressed) { - length = squashfs_decompress(msblk, bh, b, offset, length, - output); - if (length < 0) - goto read_failure; - } else { +static int read_metadata_block(struct squashfs_read_request *req, + u64 *next_index) +{ + int ret, error, bytes_read = 0, bytes_uncompressed = 0; + struct squashfs_sb_info *msblk = req->sb->s_fs_info; + + if (req->index + 2 > msblk->bytes_used) { + free_read_request(req, -EINVAL); + return -EINVAL; + } + req->length = 2; + + /* Do not read beyond the end of the device */ + if (req->index + req->length > msblk->bytes_used) + req->length = msblk->bytes_used - req->index; + req->data_processing = SQUASHFS_METADATA; + /* - * Block is uncompressed. + * Reading metadata is always synchronous because we don't know the + * length in advance and the function is expected to update + * 'next_index' and return the length. */ - int in, pg_offset = 0; - void *data = squashfs_first_page(output); - - for (bytes = length; k < b; k++) { - in = min(bytes, msblk->devblksize - offset); - bytes -= in; - while (in) { - if (pg_offset == PAGE_CACHE_SIZE) { - data = squashfs_next_page(output); - pg_offset = 0; - } - avail = min_t(int, in, PAGE_CACHE_SIZE - - pg_offset); - memcpy(data + pg_offset, bh[k]->b_data + offset, - avail); - in -= avail; - pg_offset += avail; - offset += avail; + req->synchronous = true; + req->res = &error; + req->bytes_read = &bytes_read; + req->bytes_uncompressed = &bytes_uncompressed; + + TRACE("Metadata block @ 0x%llx, %scompressed size %d, src size %d\n", + req->index, req->compressed ? "" : "un", bytes_read, + req->output->length); + + ret = squashfs_bio_submit(req); + if (ret) + return ret; + if (error) + return error; + if (next_index) + *next_index += 2 + bytes_read; + return bytes_uncompressed; } - offset = 0; - put_bh(bh[k]); + +static int read_data_block(struct squashfs_read_request *req, int length, + u64 *next_index, bool synchronous) +{ + int ret, error = 0, bytes_uncompressed = 0, bytes_read = 0; + + req->compressed = SQUASHFS_COMPRESSED_BLOCK(length); + req->length = length = SQUASHFS_COMPRESSED_SIZE_BLOCK(length); + req->data_processing = req->compressed ? SQUASHFS_DECOMPRESS + : SQUASHFS_COPY; + + req->synchronous = synchronous; + if (synchronous) { + req->res = &error; + req->bytes_read = &bytes_read; + req->bytes_uncompressed = &bytes_uncompressed; + } + + TRACE("Data block @ 0x%llx, %scompressed size %d, src size %d\n", + req->index, req->compressed ? "" : "un", req->length, + req->output->length); + + ret = squashfs_bio_submit(req); + if (ret) + return ret; + if (synchronous) + ret = error ? error : bytes_uncompressed; + if (next_index) + *next_index += length; + return ret; } - squashfs_finish_page(output); + +/* + * Read and decompress a metadata block or datablock. Length is non-zero + * if a datablock is being read (the size is stored elsewhere in the + * filesystem), otherwise the length is obtained from the first two bytes of + * the metadata block. A bit in the length field indicates if the block + * is stored uncompressed in the filesystem (usually because compression + * generated a larger block - this does occasionally happen with compression + * algorithms). + */ +static int __squashfs_read_data(struct super_block *sb, u64 index, int length, + u64 *next_index, struct squashfs_page_actor *output, bool sync) +{ + struct squashfs_read_request *req; + + req = kcalloc(1, sizeof(struct squashfs_read_request), GFP_KERNEL); + if (!req) { + if (!sync) + squashfs_page_actor_free(output, -ENOMEM); + return -ENOMEM; } - kfree(bh); - return length; + req->sb = sb; + req->index = index; + req->output = output; -block_release: - for (; k < b; k++) - put_bh(bh[k]); + if (next_index) + *next_index = index; + + if (length) + length = read_data_block(req, length, next_index, sync); + else + length = read_metadata_block(req, next_index); -read_failure: + if (length < 0) { ERROR("squashfs_read_data failed to read block 0x%llx\n", (unsigned long long) index); - kfree(bh); return -EIO; } + + return length; +} + +int squashfs_read_data(struct super_block *sb, u64 index, int length, + u64 *next_index, struct squashfs_page_actor *output) +{ + return __squashfs_read_data(sb, index, length, next_index, output, + true); +} + +int squashfs_read_data_async(struct super_block *sb, u64 index, int length, + u64 *next_index, struct squashfs_page_actor *output) +{ + + return __squashfs_read_data(sb, index, length, next_index, output, + false); +} diff -ruw linux-4.4.115/fs/squashfs/cache.c linux-4.4.115-fbx/fs/squashfs/cache.c --- linux-4.4.115/fs/squashfs/cache.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/fs/squashfs/cache.c 2019-10-29 09:26:25.385220225 +0100 @@ -209,17 +209,14 @@ */ void squashfs_cache_delete(struct squashfs_cache *cache) { - int i, j; + int i; if (cache == NULL) return; for (i = 0; i < cache->entries; i++) { - if (cache->entry[i].data) { - for (j = 0; j < cache->pages; j++) - kfree(cache->entry[i].data[j]); - kfree(cache->entry[i].data); - } + if (cache->entry[i].page) + free_page_array(cache->entry[i].page, cache->pages); kfree(cache->entry[i].actor); } @@ -236,7 +233,7 @@ struct squashfs_cache *squashfs_cache_init(char *name, int entries, int block_size) { - int i, j; + int i; struct squashfs_cache *cache = kzalloc(sizeof(*cache), GFP_KERNEL); if (cache == NULL) { @@ -268,22 +265,13 @@ init_waitqueue_head(&cache->entry[i].wait_queue); entry->cache = cache; entry->block = SQUASHFS_INVALID_BLK; - entry->data = kcalloc(cache->pages, sizeof(void *), GFP_KERNEL); - if (entry->data == NULL) { + entry->page = alloc_page_array(cache->pages, GFP_KERNEL); + if (!entry->page) { ERROR("Failed to allocate %s cache entry\n", name); goto cleanup; } - - for (j = 0; j < cache->pages; j++) { - entry->data[j] = kmalloc(PAGE_CACHE_SIZE, GFP_KERNEL); - if (entry->data[j] == NULL) { - ERROR("Failed to allocate %s buffer\n", name); - goto cleanup; - } - } - - entry->actor = squashfs_page_actor_init(entry->data, - cache->pages, 0); + entry->actor = squashfs_page_actor_init(entry->page, + cache->pages, 0, NULL); if (entry->actor == NULL) { ERROR("Failed to allocate %s cache entry\n", name); goto cleanup; @@ -314,18 +302,20 @@ return min(length, entry->length - offset); while (offset < entry->length) { - void *buff = entry->data[offset / PAGE_CACHE_SIZE] + void *buff = kmap_atomic(entry->page[offset / PAGE_CACHE_SIZE]) + (offset % PAGE_CACHE_SIZE); int bytes = min_t(int, entry->length - offset, PAGE_CACHE_SIZE - (offset % PAGE_CACHE_SIZE)); if (bytes >= remaining) { memcpy(buffer, buff, remaining); + kunmap_atomic(buff); remaining = 0; break; } memcpy(buffer, buff, bytes); + kunmap_atomic(buff); buffer += bytes; remaining -= bytes; offset += bytes; @@ -416,43 +406,38 @@ void *squashfs_read_table(struct super_block *sb, u64 block, int length) { int pages = (length + PAGE_CACHE_SIZE - 1) >> PAGE_CACHE_SHIFT; - int i, res; - void *table, *buffer, **data; + struct page **page; + void *buff; + int res; struct squashfs_page_actor *actor; - table = buffer = kmalloc(length, GFP_KERNEL); - if (table == NULL) + page = alloc_page_array(pages, GFP_KERNEL); + if (!page) return ERR_PTR(-ENOMEM); - data = kcalloc(pages, sizeof(void *), GFP_KERNEL); - if (data == NULL) { - res = -ENOMEM; - goto failed; - } - - actor = squashfs_page_actor_init(data, pages, length); + actor = squashfs_page_actor_init(page, pages, length, NULL); if (actor == NULL) { res = -ENOMEM; - goto failed2; + goto failed; } - for (i = 0; i < pages; i++, buffer += PAGE_CACHE_SIZE) - data[i] = buffer; - res = squashfs_read_data(sb, block, length | SQUASHFS_COMPRESSED_BIT_BLOCK, NULL, actor); - kfree(data); - kfree(actor); - if (res < 0) - goto failed; + goto failed2; - return table; + buff = kmalloc(length, GFP_KERNEL); + if (!buff) + goto failed2; + squashfs_actor_to_buf(actor, buff, length); + squashfs_page_actor_free(actor, 0); + free_page_array(page, pages); + return buff; failed2: - kfree(data); + squashfs_page_actor_free(actor, 0); failed: - kfree(table); + free_page_array(page, pages); return ERR_PTR(res); } diff -ruw linux-4.4.115/fs/squashfs/decompressor.c linux-4.4.115-fbx/fs/squashfs/decompressor.c --- linux-4.4.115/fs/squashfs/decompressor.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/fs/squashfs/decompressor.c 2019-10-29 09:26:25.385220225 +0100 @@ -24,7 +24,8 @@ #include #include #include -#include +#include +#include #include "squashfs_fs.h" #include "squashfs_fs_sb.h" @@ -65,6 +66,12 @@ }; #endif +#ifndef CONFIG_SQUASHFS_ZSTD +static const struct squashfs_decompressor squashfs_zstd_comp_ops = { + NULL, NULL, NULL, NULL, ZSTD_COMPRESSION, "zstd", 0 +}; +#endif + static const struct squashfs_decompressor squashfs_unknown_comp_ops = { NULL, NULL, NULL, NULL, 0, "unknown", 0 }; @@ -75,6 +82,7 @@ &squashfs_lzo_comp_ops, &squashfs_xz_comp_ops, &squashfs_lzma_unsupported_comp_ops, + &squashfs_zstd_comp_ops, &squashfs_unknown_comp_ops }; @@ -94,24 +102,26 @@ static void *get_comp_opts(struct super_block *sb, unsigned short flags) { struct squashfs_sb_info *msblk = sb->s_fs_info; - void *buffer = NULL, *comp_opts; + void *comp_opts, *buffer = NULL; + struct page *page; struct squashfs_page_actor *actor = NULL; int length = 0; + if (!SQUASHFS_COMP_OPTS(flags)) + return squashfs_comp_opts(msblk, buffer, length); + /* * Read decompressor specific options from file system if present */ - if (SQUASHFS_COMP_OPTS(flags)) { - buffer = kmalloc(PAGE_CACHE_SIZE, GFP_KERNEL); - if (buffer == NULL) { - comp_opts = ERR_PTR(-ENOMEM); - goto out; - } - actor = squashfs_page_actor_init(&buffer, 1, 0); + page = alloc_page(GFP_KERNEL); + if (!page) + return ERR_PTR(-ENOMEM); + + actor = squashfs_page_actor_init(&page, 1, 0, NULL); if (actor == NULL) { comp_opts = ERR_PTR(-ENOMEM); - goto out; + goto actor_error; } length = squashfs_read_data(sb, @@ -119,15 +129,17 @@ if (length < 0) { comp_opts = ERR_PTR(length); - goto out; - } + goto read_error; } + buffer = kmap_atomic(page); comp_opts = squashfs_comp_opts(msblk, buffer, length); + kunmap_atomic(buffer); -out: - kfree(actor); - kfree(buffer); +read_error: + squashfs_page_actor_free(actor, 0); +actor_error: + __free_page(page); return comp_opts; } diff -ruw linux-4.4.115/fs/squashfs/decompressor.h linux-4.4.115-fbx/fs/squashfs/decompressor.h --- linux-4.4.115/fs/squashfs/decompressor.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/fs/squashfs/decompressor.h 2019-10-29 09:26:25.385220225 +0100 @@ -58,4 +58,8 @@ extern const struct squashfs_decompressor squashfs_zlib_comp_ops; #endif +#ifdef CONFIG_SQUASHFS_ZSTD +extern const struct squashfs_decompressor squashfs_zstd_comp_ops; +#endif + #endif diff -ruw linux-4.4.115/fs/squashfs/file.c linux-4.4.115-fbx/fs/squashfs/file.c --- linux-4.4.115/fs/squashfs/file.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/fs/squashfs/file.c 2019-10-29 09:26:25.385220225 +0100 @@ -47,12 +47,16 @@ #include #include #include +#include #include "squashfs_fs.h" #include "squashfs_fs_sb.h" #include "squashfs_fs_i.h" #include "squashfs.h" +// Backported from 4.5 +#define lru_to_page(head) (list_entry((head)->prev, struct page, lru)) + /* * Locate cache slot in range [offset, index] for specified inode. If * there's more than one return the slot closest to index. @@ -438,6 +442,21 @@ return res; } +static int squashfs_readpages_fragment(struct page *page, + struct list_head *readahead_pages, struct address_space *mapping) +{ + if (!page) { + page = lru_to_page(readahead_pages); + list_del(&page->lru); + if (add_to_page_cache_lru(page, mapping, page->index, + mapping_gfp_constraint(mapping, GFP_KERNEL))) { + put_page(page); + return 0; + } + } + return squashfs_readpage_fragment(page); +} + static int squashfs_readpage_sparse(struct page *page, int index, int file_end) { struct inode *inode = page->mapping->host; @@ -450,54 +469,105 @@ return 0; } -static int squashfs_readpage(struct file *file, struct page *page) +static int squashfs_readpages_sparse(struct page *page, + struct list_head *readahead_pages, int index, int file_end, + struct address_space *mapping) +{ + if (!page) { + page = lru_to_page(readahead_pages); + list_del(&page->lru); + if (add_to_page_cache_lru(page, mapping, page->index, + mapping_gfp_constraint(mapping, GFP_KERNEL))) { + put_page(page); + return 0; + } + } + return squashfs_readpage_sparse(page, index, file_end); +} + +static int __squashfs_readpages(struct file *file, struct page *page, + struct list_head *readahead_pages, unsigned int nr_pages, + struct address_space *mapping) { - struct inode *inode = page->mapping->host; + struct inode *inode = mapping->host; struct squashfs_sb_info *msblk = inode->i_sb->s_fs_info; - int index = page->index >> (msblk->block_log - PAGE_CACHE_SHIFT); int file_end = i_size_read(inode) >> msblk->block_log; int res; - void *pageaddr; - TRACE("Entered squashfs_readpage, page index %lx, start block %llx\n", - page->index, squashfs_i(inode)->start); + do { + struct page *cur_page = page ? page + : lru_to_page(readahead_pages); + int page_index = cur_page->index; + int index = page_index >> (msblk->block_log - PAGE_CACHE_SHIFT); - if (page->index >= ((i_size_read(inode) + PAGE_CACHE_SIZE - 1) >> + if (page_index >= ((i_size_read(inode) + PAGE_CACHE_SIZE - 1) >> PAGE_CACHE_SHIFT)) - goto out; + return 1; if (index < file_end || squashfs_i(inode)->fragment_block == SQUASHFS_INVALID_BLK) { u64 block = 0; int bsize = read_blocklist(inode, index, &block); + if (bsize < 0) - goto error_out; + return -1; - if (bsize == 0) - res = squashfs_readpage_sparse(page, index, file_end); - else - res = squashfs_readpage_block(page, block, bsize); - } else - res = squashfs_readpage_fragment(page); + if (bsize == 0) { + res = squashfs_readpages_sparse(page, + readahead_pages, index, file_end, + mapping); + } else { + res = squashfs_readpages_block(page, + readahead_pages, &nr_pages, mapping, + page_index, block, bsize); + } + } else { + res = squashfs_readpages_fragment(page, + readahead_pages, mapping); + } + if (res) + return 0; + page = NULL; + } while (readahead_pages && !list_empty(readahead_pages)); - if (!res) return 0; +} -error_out: - SetPageError(page); -out: - pageaddr = kmap_atomic(page); - memset(pageaddr, 0, PAGE_CACHE_SIZE); - kunmap_atomic(pageaddr); +static int squashfs_readpage(struct file *file, struct page *page) +{ + int ret; + + TRACE("Entered squashfs_readpage, page index %lx, start block %llx\n", + page->index, squashfs_i(page->mapping->host)->start); + + get_page(page); + + ret = __squashfs_readpages(file, page, NULL, 1, page->mapping); + if (ret) { flush_dcache_page(page); - if (!PageError(page)) + if (ret < 0) + SetPageError(page); + else SetPageUptodate(page); + zero_user_segment(page, 0, PAGE_CACHE_SIZE); unlock_page(page); + put_page(page); + } return 0; } +static int squashfs_readpages(struct file *file, struct address_space *mapping, + struct list_head *pages, unsigned int nr_pages) +{ + TRACE("Entered squashfs_readpages, %u pages, first page index %lx\n", + nr_pages, lru_to_page(pages)->index); + __squashfs_readpages(file, NULL, pages, nr_pages, mapping); + return 0; +} + const struct address_space_operations squashfs_aops = { - .readpage = squashfs_readpage + .readpage = squashfs_readpage, + .readpages = squashfs_readpages, }; diff -ruw linux-4.4.115/fs/squashfs/file_direct.c linux-4.4.115-fbx/fs/squashfs/file_direct.c --- linux-4.4.115/fs/squashfs/file_direct.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/fs/squashfs/file_direct.c 2019-10-29 09:26:25.385220225 +0100 @@ -13,6 +13,7 @@ #include #include #include +#include #include "squashfs_fs.h" #include "squashfs_fs_sb.h" @@ -20,157 +21,139 @@ #include "squashfs.h" #include "page_actor.h" -static int squashfs_read_cache(struct page *target_page, u64 block, int bsize, - int pages, struct page **page); - -/* Read separately compressed datablock directly into page cache */ -int squashfs_readpage_block(struct page *target_page, u64 block, int bsize) +// Backported from 4.5 +#define lru_to_page(head) (list_entry((head)->prev, struct page, lru)) +static void release_actor_pages(struct page **page, int pages, int error) { - struct inode *inode = target_page->mapping->host; - struct squashfs_sb_info *msblk = inode->i_sb->s_fs_info; - - int file_end = (i_size_read(inode) - 1) >> PAGE_CACHE_SHIFT; - int mask = (1 << (msblk->block_log - PAGE_CACHE_SHIFT)) - 1; - int start_index = target_page->index & ~mask; - int end_index = start_index | mask; - int i, n, pages, missing_pages, bytes, res = -ENOMEM; - struct page **page; - struct squashfs_page_actor *actor; - void *pageaddr; - - if (end_index > file_end) - end_index = file_end; + int i; - pages = end_index - start_index + 1; - - page = kmalloc_array(pages, sizeof(void *), GFP_KERNEL); - if (page == NULL) - return res; + for (i = 0; i < pages; i++) { + if (!page[i]) + continue; + flush_dcache_page(page[i]); + if (!error) + SetPageUptodate(page[i]); + else { + SetPageError(page[i]); + zero_user_segment(page[i], 0, PAGE_CACHE_SIZE); + } + unlock_page(page[i]); + put_page(page[i]); + } + kfree(page); +} /* * Create a "page actor" which will kmap and kunmap the * page cache pages appropriately within the decompressor */ - actor = squashfs_page_actor_init_special(page, pages, 0); - if (actor == NULL) - goto out; - - /* Try to grab all the pages covered by the Squashfs block */ - for (missing_pages = 0, i = 0, n = start_index; i < pages; i++, n++) { - page[i] = (n == target_page->index) ? target_page : - grab_cache_page_nowait(target_page->mapping, n); +static struct squashfs_page_actor *actor_from_page_cache( + unsigned int actor_pages, struct page *target_page, + struct list_head *rpages, unsigned int *nr_pages, int start_index, + struct address_space *mapping) +{ + struct page **page; + struct squashfs_page_actor *actor; + int i, n; + gfp_t gfp = mapping_gfp_constraint(mapping, GFP_KERNEL); - if (page[i] == NULL) { - missing_pages++; + page = kmalloc_array(actor_pages, sizeof(void *), GFP_KERNEL); + if (!page) + return NULL; + + for (i = 0, n = start_index; i < actor_pages; i++, n++) { + if (target_page == NULL && rpages && !list_empty(rpages)) { + struct page *cur_page = lru_to_page(rpages); + + if (cur_page->index < start_index + actor_pages) { + list_del(&cur_page->lru); + --(*nr_pages); + if (add_to_page_cache_lru(cur_page, mapping, + cur_page->index, gfp)) + put_page(cur_page); + else + target_page = cur_page; + } else + rpages = NULL; + } + + if (target_page && target_page->index == n) { + page[i] = target_page; + target_page = NULL; + } else { + page[i] = grab_cache_page_nowait(mapping, n); + if (page[i] == NULL) continue; } if (PageUptodate(page[i])) { unlock_page(page[i]); - page_cache_release(page[i]); + put_page(page[i]); page[i] = NULL; - missing_pages++; } } - if (missing_pages) { - /* - * Couldn't get one or more pages, this page has either - * been VM reclaimed, but others are still in the page cache - * and uptodate, or we're racing with another thread in - * squashfs_readpage also trying to grab them. Fall back to - * using an intermediate buffer. - */ - res = squashfs_read_cache(target_page, block, bsize, pages, - page); - if (res < 0) - goto mark_errored; - - goto out; - } - - /* Decompress directly into the page cache buffers */ - res = squashfs_read_data(inode->i_sb, block, bsize, NULL, actor); - if (res < 0) - goto mark_errored; - - /* Last page may have trailing bytes not filled */ - bytes = res % PAGE_CACHE_SIZE; - if (bytes) { - pageaddr = kmap_atomic(page[pages - 1]); - memset(pageaddr + bytes, 0, PAGE_CACHE_SIZE - bytes); - kunmap_atomic(pageaddr); - } - - /* Mark pages as uptodate, unlock and release */ - for (i = 0; i < pages; i++) { - flush_dcache_page(page[i]); - SetPageUptodate(page[i]); - unlock_page(page[i]); - if (page[i] != target_page) - page_cache_release(page[i]); - } - - kfree(actor); + actor = squashfs_page_actor_init(page, actor_pages, 0, + release_actor_pages); + if (!actor) { + release_actor_pages(page, actor_pages, -ENOMEM); kfree(page); - - return 0; - -mark_errored: - /* Decompression failed, mark pages as errored. Target_page is - * dealt with by the caller - */ - for (i = 0; i < pages; i++) { - if (page[i] == NULL || page[i] == target_page) - continue; - flush_dcache_page(page[i]); - SetPageError(page[i]); - unlock_page(page[i]); - page_cache_release(page[i]); + return NULL; } - -out: - kfree(actor); - kfree(page); - return res; + return actor; } +int squashfs_readpages_block(struct page *target_page, + struct list_head *readahead_pages, + unsigned int *nr_pages, + struct address_space *mapping, + int page_index, u64 block, int bsize) -static int squashfs_read_cache(struct page *target_page, u64 block, int bsize, - int pages, struct page **page) { - struct inode *i = target_page->mapping->host; - struct squashfs_cache_entry *buffer = squashfs_get_datablock(i->i_sb, - block, bsize); - int bytes = buffer->length, res = buffer->error, n, offset = 0; - void *pageaddr; - - if (res) { - ERROR("Unable to read page, block %llx, size %x\n", block, - bsize); - goto out; - } - - for (n = 0; n < pages && bytes > 0; n++, - bytes -= PAGE_CACHE_SIZE, offset += PAGE_CACHE_SIZE) { - int avail = min_t(int, bytes, PAGE_CACHE_SIZE); + struct squashfs_page_actor *actor; + struct inode *inode = mapping->host; + struct squashfs_sb_info *msblk = inode->i_sb->s_fs_info; + int start_index, end_index, file_end, actor_pages, res; + int mask = (1 << (msblk->block_log - PAGE_CACHE_SHIFT)) - 1; - if (page[n] == NULL) - continue; + /* + * If readpage() is called on an uncompressed datablock, we can just + * read the pages instead of fetching the whole block. + * This greatly improves the performance when a process keep doing + * random reads because we only fetch the necessary data. + * The readahead algorithm will take care of doing speculative reads + * if necessary. + * We can't read more than 1 block even if readahead provides use more + * pages because we don't know yet if the next block is compressed or + * not. + */ + if (bsize && !SQUASHFS_COMPRESSED_BLOCK(bsize)) { + u64 block_end = block + msblk->block_size; - pageaddr = kmap_atomic(page[n]); - squashfs_copy_data(pageaddr, buffer, offset, avail); - memset(pageaddr + avail, 0, PAGE_CACHE_SIZE - avail); - kunmap_atomic(pageaddr); - flush_dcache_page(page[n]); - SetPageUptodate(page[n]); - unlock_page(page[n]); - if (page[n] != target_page) - page_cache_release(page[n]); + block += (page_index & mask) * PAGE_CACHE_SIZE; + actor_pages = (block_end - block) / PAGE_CACHE_SIZE; + if (*nr_pages < actor_pages) + actor_pages = *nr_pages; + start_index = page_index; + bsize = min_t(int, bsize, (PAGE_CACHE_SIZE * actor_pages) + | SQUASHFS_COMPRESSED_BIT_BLOCK); + } else { + file_end = (i_size_read(inode) - 1) >> PAGE_CACHE_SHIFT; + start_index = page_index & ~mask; + end_index = start_index | mask; + if (end_index > file_end) + end_index = file_end; + actor_pages = end_index - start_index + 1; } -out: - squashfs_cache_put(buffer); - return res; + actor = actor_from_page_cache(actor_pages, target_page, + readahead_pages, nr_pages, start_index, + mapping); + if (!actor) + return -ENOMEM; + + res = squashfs_read_data_async(inode->i_sb, block, bsize, NULL, + actor); + return res < 0 ? res : 0; } diff -ruw linux-4.4.115/fs/squashfs/Kconfig linux-4.4.115-fbx/fs/squashfs/Kconfig --- linux-4.4.115/fs/squashfs/Kconfig 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/fs/squashfs/Kconfig 2019-10-29 09:26:25.385220225 +0100 @@ -26,34 +26,6 @@ If unsure, say N. choice - prompt "File decompression options" - depends on SQUASHFS - help - Squashfs now supports two options for decompressing file - data. Traditionally Squashfs has decompressed into an - intermediate buffer and then memcopied it into the page cache. - Squashfs now supports the ability to decompress directly into - the page cache. - - If unsure, select "Decompress file data into an intermediate buffer" - -config SQUASHFS_FILE_CACHE - bool "Decompress file data into an intermediate buffer" - help - Decompress file data into an intermediate buffer and then - memcopy it into the page cache. - -config SQUASHFS_FILE_DIRECT - bool "Decompress files directly into the page cache" - help - Directly decompress file data into the page cache. - Doing so can significantly improve performance because - it eliminates a memcpy and it also removes the lock contention - on the single buffer. - -endchoice - -choice prompt "Decompressor parallelisation options" depends on SQUASHFS help @@ -164,6 +136,20 @@ file systems will be readable without selecting this option. If unsure, say N. + +config SQUASHFS_ZSTD + bool "Include support for ZSTD compressed file systems" + depends on SQUASHFS + select ZSTD_DECOMPRESS + help + Saying Y here includes support for reading Squashfs file systems + compressed with ZSTD compression. ZSTD gives better compression than + the default ZLIB compression, while using less CPU. + + ZSTD is not the standard compression used in Squashfs and so most + file systems will be readable without selecting this option. + + If unsure, say N. config SQUASHFS_4K_DEVBLK_SIZE bool "Use 4K device block size?" diff -ruw linux-4.4.115/fs/squashfs/Makefile linux-4.4.115-fbx/fs/squashfs/Makefile --- linux-4.4.115/fs/squashfs/Makefile 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/fs/squashfs/Makefile 2019-10-29 09:26:25.385220225 +0100 @@ -5,8 +5,7 @@ obj-$(CONFIG_SQUASHFS) += squashfs.o squashfs-y += block.o cache.o dir.o export.o file.o fragment.o id.o inode.o squashfs-y += namei.o super.o symlink.o decompressor.o -squashfs-$(CONFIG_SQUASHFS_FILE_CACHE) += file_cache.o -squashfs-$(CONFIG_SQUASHFS_FILE_DIRECT) += file_direct.o page_actor.o +squashfs-y += file_direct.o page_actor.o squashfs-$(CONFIG_SQUASHFS_DECOMP_SINGLE) += decompressor_single.o squashfs-$(CONFIG_SQUASHFS_DECOMP_MULTI) += decompressor_multi.o squashfs-$(CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU) += decompressor_multi_percpu.o @@ -15,3 +14,4 @@ squashfs-$(CONFIG_SQUASHFS_LZO) += lzo_wrapper.o squashfs-$(CONFIG_SQUASHFS_XZ) += xz_wrapper.o squashfs-$(CONFIG_SQUASHFS_ZLIB) += zlib_wrapper.o +squashfs-$(CONFIG_SQUASHFS_ZSTD) += zstd_wrapper.o diff -ruw linux-4.4.115/fs/squashfs/page_actor.c linux-4.4.115-fbx/fs/squashfs/page_actor.c --- linux-4.4.115/fs/squashfs/page_actor.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/fs/squashfs/page_actor.c 2019-10-29 09:26:25.385220225 +0100 @@ -9,92 +9,145 @@ #include #include #include +#include #include "page_actor.h" -/* - * This file contains implementations of page_actor for decompressing into - * an intermediate buffer, and for decompressing directly into the - * page cache. - * - * Calling code should avoid sleeping between calls to squashfs_first_page() - * and squashfs_finish_page(). - */ - -/* Implementation of page_actor for decompressing into intermediate buffer */ -static void *cache_first_page(struct squashfs_page_actor *actor) +struct squashfs_page_actor *squashfs_page_actor_init(struct page **page, + int pages, int length, void (*release_pages)(struct page **, int, int)) { - actor->next_page = 1; - return actor->buffer[0]; -} + struct squashfs_page_actor *actor = kmalloc(sizeof(*actor), GFP_KERNEL); -static void *cache_next_page(struct squashfs_page_actor *actor) -{ - if (actor->next_page == actor->pages) + if (actor == NULL) return NULL; - return actor->buffer[actor->next_page++]; + actor->length = length ? : pages * PAGE_CACHE_SIZE; + actor->page = page; + actor->pages = pages; + actor->next_page = 0; + actor->pageaddr = NULL; + actor->release_pages = release_pages; + return actor; } -static void cache_finish_page(struct squashfs_page_actor *actor) +void squashfs_page_actor_free(struct squashfs_page_actor *actor, int error) { - /* empty */ + if (!actor) + return; + + if (actor->release_pages) + actor->release_pages(actor->page, actor->pages, error); + kfree(actor); } -struct squashfs_page_actor *squashfs_page_actor_init(void **buffer, - int pages, int length) +void squashfs_actor_to_buf(struct squashfs_page_actor *actor, void *buf, + int length) { - struct squashfs_page_actor *actor = kmalloc(sizeof(*actor), GFP_KERNEL); + void *pageaddr; + int pos = 0, avail, i; - if (actor == NULL) - return NULL; + for (i = 0; i < actor->pages && pos < length; ++i) { + avail = min_t(int, length - pos, PAGE_CACHE_SIZE); + if (actor->page[i]) { + pageaddr = kmap_atomic(actor->page[i]); + memcpy(buf + pos, pageaddr, avail); + kunmap_atomic(pageaddr); + } + pos += avail; + } +} - actor->length = length ? : pages * PAGE_CACHE_SIZE; - actor->buffer = buffer; - actor->pages = pages; - actor->next_page = 0; - actor->squashfs_first_page = cache_first_page; - actor->squashfs_next_page = cache_next_page; - actor->squashfs_finish_page = cache_finish_page; - return actor; +void squashfs_buf_to_actor(void *buf, struct squashfs_page_actor *actor, + int length) +{ + void *pageaddr; + int pos = 0, avail, i; + + for (i = 0; i < actor->pages && pos < length; ++i) { + avail = min_t(int, length - pos, PAGE_CACHE_SIZE); + if (actor->page[i]) { + pageaddr = kmap_atomic(actor->page[i]); + memcpy(pageaddr, buf + pos, avail); + kunmap_atomic(pageaddr); + } + pos += avail; + } } -/* Implementation of page_actor for decompressing directly into page cache. */ -static void *direct_first_page(struct squashfs_page_actor *actor) +void squashfs_bh_to_actor(struct buffer_head **bh, int nr_buffers, + struct squashfs_page_actor *actor, int offset, int length, int blksz) { - actor->next_page = 1; - return actor->pageaddr = kmap_atomic(actor->page[0]); + void *kaddr = NULL; + int bytes = 0, pgoff = 0, b = 0, p = 0, avail, i; + + while (bytes < length) { + if (actor->page[p]) { + kaddr = kmap_atomic(actor->page[p]); + while (pgoff < PAGE_CACHE_SIZE && bytes < length) { + avail = min_t(int, blksz - offset, + PAGE_CACHE_SIZE - pgoff); + memcpy(kaddr + pgoff, bh[b]->b_data + offset, + avail); + pgoff += avail; + bytes += avail; + offset = (offset + avail) % blksz; + if (!offset) { + put_bh(bh[b]); + ++b; + } + } + kunmap_atomic(kaddr); + pgoff = 0; + } else { + for (i = 0; i < PAGE_CACHE_SIZE / blksz; ++i) { + if (bh[b]) + put_bh(bh[b]); + ++b; + } + bytes += PAGE_CACHE_SIZE; + } + ++p; + } } -static void *direct_next_page(struct squashfs_page_actor *actor) +void squashfs_bh_to_buf(struct buffer_head **bh, int nr_buffers, void *buf, + int offset, int length, int blksz) { - if (actor->pageaddr) - kunmap_atomic(actor->pageaddr); + int i, avail, bytes = 0; - return actor->pageaddr = actor->next_page == actor->pages ? NULL : - kmap_atomic(actor->page[actor->next_page++]); + for (i = 0; i < nr_buffers && bytes < length; ++i) { + avail = min_t(int, length - bytes, blksz - offset); + if (bh[i]) { + memcpy(buf + bytes, bh[i]->b_data + offset, avail); + put_bh(bh[i]); + } + bytes += avail; + offset = 0; + } } -static void direct_finish_page(struct squashfs_page_actor *actor) +void free_page_array(struct page **page, int nr_pages) { - if (actor->pageaddr) - kunmap_atomic(actor->pageaddr); + int i; + + for (i = 0; i < nr_pages; ++i) + __free_page(page[i]); + kfree(page); } -struct squashfs_page_actor *squashfs_page_actor_init_special(struct page **page, - int pages, int length) +struct page **alloc_page_array(int nr_pages, int gfp_mask) { - struct squashfs_page_actor *actor = kmalloc(sizeof(*actor), GFP_KERNEL); + int i; + struct page **page; - if (actor == NULL) + page = kcalloc(nr_pages, sizeof(struct page *), gfp_mask); + if (!page) return NULL; - - actor->length = length ? : pages * PAGE_CACHE_SIZE; - actor->page = page; - actor->pages = pages; - actor->next_page = 0; - actor->pageaddr = NULL; - actor->squashfs_first_page = direct_first_page; - actor->squashfs_next_page = direct_next_page; - actor->squashfs_finish_page = direct_finish_page; - return actor; + for (i = 0; i < nr_pages; ++i) { + page[i] = alloc_page(gfp_mask); + if (!page[i]) { + free_page_array(page, i); + return NULL; + } + } + return page; } diff -ruw linux-4.4.115/fs/squashfs/page_actor.h linux-4.4.115-fbx/fs/squashfs/page_actor.h --- linux-4.4.115/fs/squashfs/page_actor.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/fs/squashfs/page_actor.h 2019-10-29 09:26:25.385220225 +0100 @@ -5,77 +5,61 @@ * Phillip Lougher * * This work is licensed under the terms of the GNU GPL, version 2. See - * the COPYING file in the top-level directory. + * the COPYING file in the top-level squashfsory. */ -#ifndef CONFIG_SQUASHFS_FILE_DIRECT struct squashfs_page_actor { - void **page; + struct page **page; + void *pageaddr; int pages; int length; int next_page; + void (*release_pages)(struct page **, int, int); }; -static inline struct squashfs_page_actor *squashfs_page_actor_init(void **page, - int pages, int length) -{ - struct squashfs_page_actor *actor = kmalloc(sizeof(*actor), GFP_KERNEL); - - if (actor == NULL) - return NULL; - - actor->length = length ? : pages * PAGE_CACHE_SIZE; - actor->page = page; - actor->pages = pages; - actor->next_page = 0; - return actor; -} - +extern struct squashfs_page_actor *squashfs_page_actor_init(struct page **, + int, int, void (*)(struct page **, int, int)); +extern void squashfs_page_actor_free(struct squashfs_page_actor *, int); + +extern void squashfs_actor_to_buf(struct squashfs_page_actor *, void *, int); +extern void squashfs_buf_to_actor(void *, struct squashfs_page_actor *, int); +extern void squashfs_bh_to_actor(struct buffer_head **, int, + struct squashfs_page_actor *, int, int, int); +extern void squashfs_bh_to_buf(struct buffer_head **, int, void *, int, int, + int); + +/* + * Calling code should avoid sleeping between calls to squashfs_first_page() + * and squashfs_finish_page(). + */ static inline void *squashfs_first_page(struct squashfs_page_actor *actor) { actor->next_page = 1; - return actor->page[0]; + return actor->pageaddr = actor->page[0] ? kmap_atomic(actor->page[0]) + : NULL; } static inline void *squashfs_next_page(struct squashfs_page_actor *actor) { - return actor->next_page == actor->pages ? NULL : - actor->page[actor->next_page++]; -} + if (!IS_ERR_OR_NULL(actor->pageaddr)) + kunmap_atomic(actor->pageaddr); -static inline void squashfs_finish_page(struct squashfs_page_actor *actor) -{ - /* empty */ -} -#else -struct squashfs_page_actor { - union { - void **buffer; - struct page **page; - }; - void *pageaddr; - void *(*squashfs_first_page)(struct squashfs_page_actor *); - void *(*squashfs_next_page)(struct squashfs_page_actor *); - void (*squashfs_finish_page)(struct squashfs_page_actor *); - int pages; - int length; - int next_page; -}; + if (actor->next_page == actor->pages) + return actor->pageaddr = ERR_PTR(-ENODATA); -extern struct squashfs_page_actor *squashfs_page_actor_init(void **, int, int); -extern struct squashfs_page_actor *squashfs_page_actor_init_special(struct page - **, int, int); -static inline void *squashfs_first_page(struct squashfs_page_actor *actor) -{ - return actor->squashfs_first_page(actor); -} -static inline void *squashfs_next_page(struct squashfs_page_actor *actor) -{ - return actor->squashfs_next_page(actor); + actor->pageaddr = actor->page[actor->next_page] ? + kmap_atomic(actor->page[actor->next_page]) : NULL; + ++actor->next_page; + return actor->pageaddr; } + static inline void squashfs_finish_page(struct squashfs_page_actor *actor) { - actor->squashfs_finish_page(actor); + if (!IS_ERR_OR_NULL(actor->pageaddr)) + kunmap_atomic(actor->pageaddr); } -#endif + +extern struct page **alloc_page_array(int, int); +extern void free_page_array(struct page **, int); + #endif diff -ruw linux-4.4.115/fs/squashfs/squashfs_fs.h linux-4.4.115-fbx/fs/squashfs/squashfs_fs.h --- linux-4.4.115/fs/squashfs/squashfs_fs.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/fs/squashfs/squashfs_fs.h 2019-10-29 09:26:25.385220225 +0100 @@ -241,6 +241,7 @@ #define LZO_COMPRESSION 3 #define XZ_COMPRESSION 4 #define LZ4_COMPRESSION 5 +#define ZSTD_COMPRESSION 6 struct squashfs_super_block { __le32 s_magic; diff -ruw linux-4.4.115/fs/squashfs/squashfs_fs_sb.h linux-4.4.115-fbx/fs/squashfs/squashfs_fs_sb.h --- linux-4.4.115/fs/squashfs/squashfs_fs_sb.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/fs/squashfs/squashfs_fs_sb.h 2019-10-29 09:26:25.389220265 +0100 @@ -49,7 +49,7 @@ int num_waiters; wait_queue_head_t wait_queue; struct squashfs_cache *cache; - void **data; + struct page **page; struct squashfs_page_actor *actor; }; diff -ruw linux-4.4.115/fs/squashfs/squashfs.h linux-4.4.115-fbx/fs/squashfs/squashfs.h --- linux-4.4.115/fs/squashfs/squashfs.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/fs/squashfs/squashfs.h 2019-10-29 09:26:25.385220225 +0100 @@ -28,8 +28,14 @@ #define WARNING(s, args...) pr_warn("SQUASHFS: "s, ## args) /* block.c */ +extern int squashfs_init_read_wq(void); +extern void squashfs_destroy_read_wq(void); extern int squashfs_read_data(struct super_block *, u64, int, u64 *, struct squashfs_page_actor *); +extern int squashfs_read_data(struct super_block *, u64, int, u64 *, + struct squashfs_page_actor *); +extern int squashfs_read_data_async(struct super_block *, u64, int, u64 *, + struct squashfs_page_actor *); /* cache.c */ extern struct squashfs_cache *squashfs_cache_init(char *, int, int); @@ -70,8 +76,9 @@ void squashfs_copy_cache(struct page *, struct squashfs_cache_entry *, int, int); -/* file_xxx.c */ -extern int squashfs_readpage_block(struct page *, u64, int); +/* file_direct.c */ +extern int squashfs_readpages_block(struct page *, struct list_head *, + unsigned int *, struct address_space *, int, u64, int); /* id.c */ extern int squashfs_get_id(struct super_block *, unsigned int, unsigned int *); diff -ruw linux-4.4.115/fs/squashfs/super.c linux-4.4.115-fbx/fs/squashfs/super.c --- linux-4.4.115/fs/squashfs/super.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/fs/squashfs/super.c 2019-10-29 09:26:25.389220265 +0100 @@ -444,9 +444,15 @@ if (err) return err; + if (!squashfs_init_read_wq()) { + destroy_inodecache(); + return -ENOMEM; + } + err = register_filesystem(&squashfs_fs_type); if (err) { destroy_inodecache(); + squashfs_destroy_read_wq(); return err; } @@ -460,6 +466,7 @@ { unregister_filesystem(&squashfs_fs_type); destroy_inodecache(); + squashfs_destroy_read_wq(); } diff -ruw linux-4.4.115/fs/squashfs/xz_wrapper.c linux-4.4.115-fbx/fs/squashfs/xz_wrapper.c --- linux-4.4.115/fs/squashfs/xz_wrapper.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/fs/squashfs/xz_wrapper.c 2019-10-29 09:26:25.389220265 +0100 @@ -55,7 +55,7 @@ struct comp_opts *opts; int err = 0, n; - opts = kmalloc(sizeof(*opts), GFP_KERNEL); + opts = kmalloc(sizeof(*opts), GFP_ATOMIC); if (opts == NULL) { err = -ENOMEM; goto out2; @@ -136,6 +136,7 @@ enum xz_ret xz_err; int avail, total = 0, k = 0; struct squashfs_xz *stream = strm; + void *buf = NULL; xz_dec_reset(stream->state); stream->buf.in_pos = 0; @@ -156,12 +157,20 @@ if (stream->buf.out_pos == stream->buf.out_size) { stream->buf.out = squashfs_next_page(output); - if (stream->buf.out != NULL) { + if (!IS_ERR(stream->buf.out)) { stream->buf.out_pos = 0; total += PAGE_CACHE_SIZE; } } + if (!stream->buf.out) { + if (!buf) { + buf = kmalloc(PAGE_CACHE_SIZE, GFP_ATOMIC); + if (!buf) + goto out; + } + stream->buf.out = buf; + } xz_err = xz_dec_run(stream->state, &stream->buf); if (stream->buf.in_pos == stream->buf.in_size && k < b) @@ -173,11 +182,13 @@ if (xz_err != XZ_STREAM_END || k < b) goto out; + kfree(buf); return total + stream->buf.out_pos; out: for (; k < b; k++) put_bh(bh[k]); + kfree(buf); return -EIO; } diff -ruw linux-4.4.115/fs/super.c linux-4.4.115-fbx/fs/super.c --- linux-4.4.115/fs/super.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/fs/super.c 2019-10-29 09:26:25.389220265 +0100 @@ -703,7 +703,8 @@ } /** - * do_remount_sb - asks filesystem to change mount options. + * do_remount_sb2 - asks filesystem to change mount options. + * @mnt: mount we are looking at * @sb: superblock in question * @flags: numeric part of options * @data: the rest of options @@ -711,7 +712,7 @@ * * Alters the mount options of a mounted file system. */ -int do_remount_sb(struct super_block *sb, int flags, void *data, int force) +int do_remount_sb2(struct vfsmount *mnt, struct super_block *sb, int flags, void *data, int force) { int retval; int remount_ro; @@ -753,7 +754,16 @@ } } - if (sb->s_op->remount_fs) { + if (mnt && sb->s_op->remount_fs2) { + retval = sb->s_op->remount_fs2(mnt, sb, &flags, data); + if (retval) { + if (!force) + goto cancel_readonly; + /* If forced remount, go ahead despite any errors */ + WARN(1, "forced remount of a %s fs returned %i\n", + sb->s_type->name, retval); + } + } else if (sb->s_op->remount_fs) { retval = sb->s_op->remount_fs(sb, &flags, data); if (retval) { if (!force) @@ -785,12 +795,17 @@ return retval; } +int do_remount_sb(struct super_block *sb, int flags, void *data, int force) +{ + return do_remount_sb2(NULL, sb, flags, data, force); +} + static void do_emergency_remount(struct work_struct *work) { struct super_block *sb, *p = NULL; spin_lock(&sb_lock); - list_for_each_entry(sb, &super_blocks, s_list) { + list_for_each_entry_reverse(sb, &super_blocks, s_list) { if (hlist_unhashed(&sb->s_instances)) continue; sb->s_count++; @@ -953,7 +968,7 @@ * We set the bdi here to the queue backing, file systems can * overwrite this in ->fill_super() */ - s->s_bdi = &bdev_get_queue(s->s_bdev)->backing_dev_info; + s->s_bdi = bdev_get_queue(s->s_bdev)->backing_dev_info; return 0; } @@ -1104,7 +1119,7 @@ EXPORT_SYMBOL(mount_single); struct dentry * -mount_fs(struct file_system_type *type, int flags, const char *name, void *data) +mount_fs(struct file_system_type *type, int flags, const char *name, struct vfsmount *mnt, void *data) { struct dentry *root; struct super_block *sb; @@ -1121,6 +1136,9 @@ goto out_free_secdata; } + if (type->mount2) + root = type->mount2(mnt, type, flags, name, data); + else root = type->mount(type, flags, name, data); if (IS_ERR(root)) { error = PTR_ERR(root); diff -ruw linux-4.4.115/fs/sync.c linux-4.4.115-fbx/fs/sync.c --- linux-4.4.115/fs/sync.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/fs/sync.c 2019-01-22 16:16:28.067287736 +0100 @@ -218,6 +218,7 @@ if (f.file) { ret = vfs_fsync(f.file, datasync); fdput(f); + inc_syscfs(current); } return ret; } diff -ruw linux-4.4.115/fs/timerfd.c linux-4.4.115-fbx/fs/timerfd.c --- linux-4.4.115/fs/timerfd.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/fs/timerfd.c 2019-10-29 09:26:25.389220265 +0100 @@ -50,7 +50,8 @@ static inline bool isalarm(struct timerfd_ctx *ctx) { return ctx->clockid == CLOCK_REALTIME_ALARM || - ctx->clockid == CLOCK_BOOTTIME_ALARM; + ctx->clockid == CLOCK_BOOTTIME_ALARM || + ctx->clockid == CLOCK_POWEROFF_ALARM; } /* @@ -142,7 +143,8 @@ { spin_lock(&ctx->cancel_lock); if ((ctx->clockid == CLOCK_REALTIME || - ctx->clockid == CLOCK_REALTIME_ALARM) && + ctx->clockid == CLOCK_REALTIME_ALARM || + ctx->clockid == CLOCK_POWEROFF_ALARM) && (flags & TFD_TIMER_ABSTIME) && (flags & TFD_TIMER_CANCEL_ON_SET)) { if (!ctx->might_cancel) { ctx->might_cancel = true; @@ -174,6 +176,7 @@ enum hrtimer_mode htmode; ktime_t texp; int clockid = ctx->clockid; + enum alarmtimer_type type; htmode = (flags & TFD_TIMER_ABSTIME) ? HRTIMER_MODE_ABS: HRTIMER_MODE_REL; @@ -184,10 +187,8 @@ ctx->tintv = timespec_to_ktime(ktmr->it_interval); if (isalarm(ctx)) { - alarm_init(&ctx->t.alarm, - ctx->clockid == CLOCK_REALTIME_ALARM ? - ALARM_REALTIME : ALARM_BOOTTIME, - timerfd_alarmproc); + type = clock2alarm(ctx->clockid); + alarm_init(&ctx->t.alarm, type, timerfd_alarmproc); } else { hrtimer_init(&ctx->t.tmr, clockid, htmode); hrtimer_set_expires(&ctx->t.tmr, texp); @@ -387,6 +388,7 @@ { int ufd; struct timerfd_ctx *ctx; + enum alarmtimer_type type; /* Check the TFD_* constants for consistency. */ BUILD_BUG_ON(TFD_CLOEXEC != O_CLOEXEC); @@ -397,7 +399,8 @@ clockid != CLOCK_REALTIME && clockid != CLOCK_REALTIME_ALARM && clockid != CLOCK_BOOTTIME && - clockid != CLOCK_BOOTTIME_ALARM)) + clockid != CLOCK_BOOTTIME_ALARM && + clockid != CLOCK_POWEROFF_ALARM)) return -EINVAL; ctx = kzalloc(sizeof(*ctx), GFP_KERNEL); @@ -408,13 +411,12 @@ spin_lock_init(&ctx->cancel_lock); ctx->clockid = clockid; - if (isalarm(ctx)) - alarm_init(&ctx->t.alarm, - ctx->clockid == CLOCK_REALTIME_ALARM ? - ALARM_REALTIME : ALARM_BOOTTIME, - timerfd_alarmproc); - else + if (isalarm(ctx)) { + type = clock2alarm(ctx->clockid); + alarm_init(&ctx->t.alarm, type, timerfd_alarmproc); + } else { hrtimer_init(&ctx->t.tmr, clockid, HRTIMER_MODE_ABS); + } ctx->moffs = ktime_mono_to_real((ktime_t){ .tv64 = 0 }); @@ -486,6 +488,10 @@ ret = timerfd_setup(ctx, flags, new); spin_unlock_irq(&ctx->wqh.lock); + + if (ctx->clockid == CLOCK_POWEROFF_ALARM) + set_power_on_alarm(); + fdput(f); return ret; } diff -ruw linux-4.4.115/fs/utimes.c linux-4.4.115-fbx/fs/utimes.c --- linux-4.4.115/fs/utimes.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/fs/utimes.c 2019-01-22 16:16:28.091287954 +0100 @@ -91,7 +91,7 @@ } retry_deleg: mutex_lock(&inode->i_mutex); - error = notify_change(path->dentry, &newattrs, &delegated_inode); + error = notify_change2(path->mnt, path->dentry, &newattrs, &delegated_inode); mutex_unlock(&inode->i_mutex); if (delegated_inode) { error = break_deleg_wait(&delegated_inode); diff -ruw linux-4.4.115/fs/xattr.c linux-4.4.115-fbx/fs/xattr.c --- linux-4.4.115/fs/xattr.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/fs/xattr.c 2019-10-29 09:26:25.397220343 +0100 @@ -70,7 +70,7 @@ return -EPERM; } - return inode_permission(inode, mask); + return inode_permission2(ERR_PTR(-EOPNOTSUPP), inode, mask); } /** diff -ruw linux-4.4.115/include/asm-generic/dma-mapping-common.h linux-4.4.115-fbx/include/asm-generic/dma-mapping-common.h --- linux-4.4.115/include/asm-generic/dma-mapping-common.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/asm-generic/dma-mapping-common.h 2019-01-22 16:16:28.147288461 +0100 @@ -13,7 +13,7 @@ enum dma_data_direction dir, struct dma_attrs *attrs) { - struct dma_map_ops *ops = get_dma_ops(dev); + const struct dma_map_ops *ops = get_dma_ops(dev); dma_addr_t addr; kmemcheck_mark_initialized(ptr, size); @@ -32,7 +32,7 @@ enum dma_data_direction dir, struct dma_attrs *attrs) { - struct dma_map_ops *ops = get_dma_ops(dev); + const struct dma_map_ops *ops = get_dma_ops(dev); BUG_ON(!valid_dma_direction(dir)); if (ops->unmap_page) @@ -48,7 +48,7 @@ int nents, enum dma_data_direction dir, struct dma_attrs *attrs) { - struct dma_map_ops *ops = get_dma_ops(dev); + const struct dma_map_ops *ops = get_dma_ops(dev); int i, ents; struct scatterlist *s; @@ -66,7 +66,7 @@ int nents, enum dma_data_direction dir, struct dma_attrs *attrs) { - struct dma_map_ops *ops = get_dma_ops(dev); + const struct dma_map_ops *ops = get_dma_ops(dev); BUG_ON(!valid_dma_direction(dir)); debug_dma_unmap_sg(dev, sg, nents, dir); @@ -78,7 +78,7 @@ size_t offset, size_t size, enum dma_data_direction dir) { - struct dma_map_ops *ops = get_dma_ops(dev); + const struct dma_map_ops *ops = get_dma_ops(dev); dma_addr_t addr; kmemcheck_mark_initialized(page_address(page) + offset, size); @@ -92,7 +92,7 @@ static inline void dma_unmap_page(struct device *dev, dma_addr_t addr, size_t size, enum dma_data_direction dir) { - struct dma_map_ops *ops = get_dma_ops(dev); + const struct dma_map_ops *ops = get_dma_ops(dev); BUG_ON(!valid_dma_direction(dir)); if (ops->unmap_page) @@ -104,7 +104,7 @@ size_t size, enum dma_data_direction dir) { - struct dma_map_ops *ops = get_dma_ops(dev); + const struct dma_map_ops *ops = get_dma_ops(dev); BUG_ON(!valid_dma_direction(dir)); if (ops->sync_single_for_cpu) @@ -116,7 +116,7 @@ dma_addr_t addr, size_t size, enum dma_data_direction dir) { - struct dma_map_ops *ops = get_dma_ops(dev); + const struct dma_map_ops *ops = get_dma_ops(dev); BUG_ON(!valid_dma_direction(dir)); if (ops->sync_single_for_device) @@ -156,7 +156,7 @@ dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg, int nelems, enum dma_data_direction dir) { - struct dma_map_ops *ops = get_dma_ops(dev); + const struct dma_map_ops *ops = get_dma_ops(dev); BUG_ON(!valid_dma_direction(dir)); if (ops->sync_sg_for_cpu) @@ -168,7 +168,7 @@ dma_sync_sg_for_device(struct device *dev, struct scatterlist *sg, int nelems, enum dma_data_direction dir) { - struct dma_map_ops *ops = get_dma_ops(dev); + const struct dma_map_ops *ops = get_dma_ops(dev); BUG_ON(!valid_dma_direction(dir)); if (ops->sync_sg_for_device) @@ -192,7 +192,8 @@ void *dma_common_pages_remap(struct page **pages, size_t size, unsigned long vm_flags, pgprot_t prot, const void *caller); -void dma_common_free_remap(void *cpu_addr, size_t size, unsigned long vm_flags); +void dma_common_free_remap(void *cpu_addr, size_t size, unsigned long vm_flags, + bool no_warn); /** * dma_mmap_attrs - map a coherent DMA allocation into user space @@ -211,7 +212,7 @@ dma_mmap_attrs(struct device *dev, struct vm_area_struct *vma, void *cpu_addr, dma_addr_t dma_addr, size_t size, struct dma_attrs *attrs) { - struct dma_map_ops *ops = get_dma_ops(dev); + const struct dma_map_ops *ops = get_dma_ops(dev); BUG_ON(!ops); if (ops->mmap) return ops->mmap(dev, vma, cpu_addr, dma_addr, size, attrs); @@ -228,7 +229,7 @@ dma_get_sgtable_attrs(struct device *dev, struct sg_table *sgt, void *cpu_addr, dma_addr_t dma_addr, size_t size, struct dma_attrs *attrs) { - struct dma_map_ops *ops = get_dma_ops(dev); + const struct dma_map_ops *ops = get_dma_ops(dev); BUG_ON(!ops); if (ops->get_sgtable) return ops->get_sgtable(dev, sgt, cpu_addr, dma_addr, size, @@ -246,7 +247,7 @@ dma_addr_t *dma_handle, gfp_t flag, struct dma_attrs *attrs) { - struct dma_map_ops *ops = get_dma_ops(dev); + const struct dma_map_ops *ops = get_dma_ops(dev); void *cpu_addr; BUG_ON(!ops); @@ -268,7 +269,7 @@ void *cpu_addr, dma_addr_t dma_handle, struct dma_attrs *attrs) { - struct dma_map_ops *ops = get_dma_ops(dev); + const struct dma_map_ops *ops = get_dma_ops(dev); BUG_ON(!ops); WARN_ON(irqs_disabled()); @@ -327,10 +328,35 @@ #endif } +static inline void *dma_alloc_nonconsistent(struct device *dev, size_t size, + dma_addr_t *dma_handle, gfp_t flag) +{ + DEFINE_DMA_ATTRS(attrs); + dma_set_attr(DMA_ATTR_NON_CONSISTENT, &attrs); + return dma_alloc_attrs(dev, size, dma_handle, flag, &attrs); +} + +static inline void dma_free_nonconsistent(struct device *dev, size_t size, + void *cpu_addr, dma_addr_t dma_handle) +{ + DEFINE_DMA_ATTRS(attrs); + dma_set_attr(DMA_ATTR_NON_CONSISTENT, &attrs); + return dma_free_attrs(dev, size, cpu_addr, dma_handle, &attrs); +} + +static inline int dma_mmap_nonconsistent(struct device *dev, + struct vm_area_struct *vma, void *cpu_addr, + dma_addr_t dma_addr, size_t size) +{ + DEFINE_DMA_ATTRS(attrs); + dma_set_attr(DMA_ATTR_NON_CONSISTENT, &attrs); + return dma_mmap_attrs(dev, vma, cpu_addr, dma_addr, size, &attrs); +} + #ifndef HAVE_ARCH_DMA_SUPPORTED static inline int dma_supported(struct device *dev, u64 mask) { - struct dma_map_ops *ops = get_dma_ops(dev); + const struct dma_map_ops *ops = get_dma_ops(dev); if (!ops) return 0; @@ -343,7 +369,7 @@ #ifndef HAVE_ARCH_DMA_SET_MASK static inline int dma_set_mask(struct device *dev, u64 mask) { - struct dma_map_ops *ops = get_dma_ops(dev); + const struct dma_map_ops *ops = get_dma_ops(dev); if (ops->set_dma_mask) return ops->set_dma_mask(dev, mask); diff -ruw linux-4.4.115/include/asm-generic/fixmap.h linux-4.4.115-fbx/include/asm-generic/fixmap.h --- linux-4.4.115/include/asm-generic/fixmap.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/asm-generic/fixmap.h 2019-01-22 16:16:28.151288497 +0100 @@ -72,10 +72,10 @@ /* Return a pointer with offset calculated */ #define __set_fixmap_offset(idx, phys, flags) \ ({ \ - unsigned long addr; \ + unsigned long ________addr; \ __set_fixmap(idx, phys, flags); \ - addr = fix_to_virt(idx) + ((phys) & (PAGE_SIZE - 1)); \ - addr; \ + ________addr = fix_to_virt(idx) + ((phys) & (PAGE_SIZE - 1)); \ + ________addr; \ }) #define set_fixmap_offset(idx, phys) \ diff -ruw linux-4.4.115/include/asm-generic/preempt.h linux-4.4.115-fbx/include/asm-generic/preempt.h --- linux-4.4.115/include/asm-generic/preempt.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/asm-generic/preempt.h 2019-01-22 16:16:28.151288497 +0100 @@ -7,10 +7,10 @@ static __always_inline int preempt_count(void) { - return current_thread_info()->preempt_count; + return READ_ONCE(current_thread_info()->preempt_count); } -static __always_inline int *preempt_count_ptr(void) +static __always_inline volatile int *preempt_count_ptr(void) { return ¤t_thread_info()->preempt_count; } diff -ruw linux-4.4.115/include/asm-generic/sections.h linux-4.4.115-fbx/include/asm-generic/sections.h --- linux-4.4.115/include/asm-generic/sections.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/asm-generic/sections.h 2019-01-22 16:16:28.155288533 +0100 @@ -24,6 +24,8 @@ * __kprobes_text_start, __kprobes_text_end * __entry_text_start, __entry_text_end * __ctors_start, __ctors_end + * __irqentry_text_start, __irqentry_text_end + * __softirqentry_text_start, __softirqentry_text_end */ extern char _text[], _stext[], _etext[]; extern char _data[], _sdata[], _edata[]; @@ -35,6 +37,8 @@ extern char __kprobes_text_start[], __kprobes_text_end[]; extern char __entry_text_start[], __entry_text_end[]; extern char __start_rodata[], __end_rodata[]; +extern char __irqentry_text_start[], __irqentry_text_end[]; +extern char __softirqentry_text_start[], __softirqentry_text_end[]; /* Start and end of .ctors section - used for constructor calls. */ extern char __ctors_start[], __ctors_end[]; diff -ruw linux-4.4.115/include/asm-generic/vmlinux.lds.h linux-4.4.115-fbx/include/asm-generic/vmlinux.lds.h --- linux-4.4.115/include/asm-generic/vmlinux.lds.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/asm-generic/vmlinux.lds.h 2019-01-22 16:16:28.155288533 +0100 @@ -157,7 +157,7 @@ #define EARLYCON_TABLE() STRUCT_ALIGN(); \ VMLINUX_SYMBOL(__earlycon_table) = .; \ *(__earlycon_table) \ - *(__earlycon_table_end) + VMLINUX_SYMBOL(__earlycon_table_end) = .; #else #define EARLYCON_TABLE() #endif @@ -179,7 +179,6 @@ #define RESERVEDMEM_OF_TABLES() OF_TABLE(CONFIG_OF_RESERVED_MEM, reservedmem) #define CPU_METHOD_OF_TABLES() OF_TABLE(CONFIG_SMP, cpu_method) #define CPUIDLE_METHOD_OF_TABLES() OF_TABLE(CONFIG_CPU_IDLE, cpuidle_method) -#define EARLYCON_OF_TABLES() OF_TABLE(CONFIG_SERIAL_EARLYCON, earlycon) #ifdef CONFIG_ACPI #define ACPI_PROBE_TABLE(name) \ @@ -249,6 +248,14 @@ *(.data..init_task) /* + * Allow architectures to handle ro_after_init data on their + * own by defining an empty RO_AFTER_INIT_DATA. + */ +#ifndef RO_AFTER_INIT_DATA +#define RO_AFTER_INIT_DATA *(.data..ro_after_init) +#endif + +/* * Read only Data */ #define RO_DATA_SECTION(align) \ @@ -256,6 +263,7 @@ .rodata : AT(ADDR(.rodata) - LOAD_OFFSET) { \ VMLINUX_SYMBOL(__start_rodata) = .; \ *(.rodata) *(.rodata.*) \ + RO_AFTER_INIT_DATA /* Read only after init */ \ *(__vermagic) /* Kernel version magic */ \ . = ALIGN(8); \ VMLINUX_SYMBOL(__start___tracepoints_ptrs) = .; \ @@ -456,15 +464,17 @@ *(.entry.text) \ VMLINUX_SYMBOL(__entry_text_end) = .; -#ifdef CONFIG_FUNCTION_GRAPH_TRACER #define IRQENTRY_TEXT \ ALIGN_FUNCTION(); \ VMLINUX_SYMBOL(__irqentry_text_start) = .; \ *(.irqentry.text) \ VMLINUX_SYMBOL(__irqentry_text_end) = .; -#else -#define IRQENTRY_TEXT -#endif + +#define SOFTIRQENTRY_TEXT \ + ALIGN_FUNCTION(); \ + VMLINUX_SYMBOL(__softirqentry_text_start) = .; \ + *(.softirqentry.text) \ + VMLINUX_SYMBOL(__softirqentry_text_end) = .; /* Section used for early init (in .S files) */ #define HEAD_TEXT *(.head.text) @@ -526,8 +536,7 @@ IRQCHIP_OF_MATCH_TABLE() \ ACPI_PROBE_TABLE(irqchip) \ ACPI_PROBE_TABLE(clksrc) \ - EARLYCON_TABLE() \ - EARLYCON_OF_TABLES() + EARLYCON_TABLE() #define INIT_TEXT \ *(.init.text) \ diff -ruw linux-4.4.115/include/clocksource/arm_arch_timer.h linux-4.4.115-fbx/include/clocksource/arm_arch_timer.h --- linux-4.4.115/include/clocksource/arm_arch_timer.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/clocksource/arm_arch_timer.h 2019-01-22 16:16:28.155288533 +0100 @@ -23,6 +23,12 @@ #define ARCH_TIMER_CTRL_IT_MASK (1 << 1) #define ARCH_TIMER_CTRL_IT_STAT (1 << 2) +#define CNTHCTL_EL1PCTEN (1 << 0) +#define CNTHCTL_EL1PCEN (1 << 1) +#define CNTHCTL_EVNTEN (1 << 2) +#define CNTHCTL_EVNTDIR (1 << 3) +#define CNTHCTL_EVNTI (0xF << 4) + enum arch_timer_reg { ARCH_TIMER_REG_CTRL, ARCH_TIMER_REG_TVAL, diff -ruw linux-4.4.115/include/crypto/algapi.h linux-4.4.115-fbx/include/crypto/algapi.h --- linux-4.4.115/include/crypto/algapi.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/crypto/algapi.h 2019-01-22 16:16:28.155288533 +0100 @@ -202,6 +202,9 @@ struct blkcipher_walk *walk, struct crypto_aead *tfm, unsigned int blocksize); +int blkcipher_ablkcipher_walk_virt(struct blkcipher_desc *desc, + struct blkcipher_walk *walk, + struct crypto_ablkcipher *tfm); int ablkcipher_walk_done(struct ablkcipher_request *req, struct ablkcipher_walk *walk, int err); diff -ruw linux-4.4.115/include/crypto/gf128mul.h linux-4.4.115-fbx/include/crypto/gf128mul.h --- linux-4.4.115/include/crypto/gf128mul.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/crypto/gf128mul.h 2019-01-22 16:16:28.159288569 +0100 @@ -43,7 +43,7 @@ --------------------------------------------------------------------------- Issue Date: 31/01/2006 - An implementation of field multiplication in Galois Field GF(128) + An implementation of field multiplication in Galois Field GF(2^128) */ #ifndef _CRYPTO_GF128MUL_H @@ -65,7 +65,7 @@ * are left and the lsb's are right. char b[16] is an array and b[0] is * the first octet. * - * 80000000 00000000 00000000 00000000 .... 00000000 00000000 00000000 + * 10000000 00000000 00000000 00000000 .... 00000000 00000000 00000000 * b[0] b[1] b[2] b[3] b[13] b[14] b[15] * * Every bit is a coefficient of some power of X. We can store the bits @@ -155,42 +155,45 @@ 64...71 72...79 80...87 88...95 96..103 104.111 112.119 120.127 */ -/* A slow generic version of gf_mul, implemented for lle and bbe - * It multiplies a and b and puts the result in a */ +/* A slow generic version of gf_mul, implemented for lle, bbe, and ble. + * It multiplies a and b and puts the result in a + */ void gf128mul_lle(be128 *a, const be128 *b); - void gf128mul_bbe(be128 *a, const be128 *b); +void gf128mul_ble(be128 *a, const be128 *b); -/* multiply by x in ble format, needed by XTS */ +/* multiply by x in ble format, needed by XTS and HEH */ void gf128mul_x_ble(be128 *a, const be128 *b); /* 4k table optimization */ - struct gf128mul_4k { be128 t[256]; }; struct gf128mul_4k *gf128mul_init_4k_lle(const be128 *g); struct gf128mul_4k *gf128mul_init_4k_bbe(const be128 *g); +struct gf128mul_4k *gf128mul_init_4k_ble(const be128 *g); void gf128mul_4k_lle(be128 *a, struct gf128mul_4k *t); void gf128mul_4k_bbe(be128 *a, struct gf128mul_4k *t); +void gf128mul_4k_ble(be128 *a, struct gf128mul_4k *t); static inline void gf128mul_free_4k(struct gf128mul_4k *t) { - kfree(t); + kzfree(t); } -/* 64k table optimization, implemented for lle and bbe */ +/* 64k table optimization, implemented for lle, ble, and bbe */ struct gf128mul_64k { struct gf128mul_4k *t[16]; }; -/* first initialize with the constant factor with which you - * want to multiply and then call gf128_64k_lle with the other - * factor in the first argument, the table in the second and a - * scratch register in the third. Afterwards *a = *r. */ +/* First initialize with the constant factor with which you + * want to multiply and then call gf128mul_64k_bbe with the other + * factor in the first argument, and the table in the second. + * Afterwards, the result is stored in *a. + */ struct gf128mul_64k *gf128mul_init_64k_lle(const be128 *g); struct gf128mul_64k *gf128mul_init_64k_bbe(const be128 *g); void gf128mul_free_64k(struct gf128mul_64k *t); diff -ruw linux-4.4.115/include/crypto/internal/hash.h linux-4.4.115-fbx/include/crypto/internal/hash.h --- linux-4.4.115/include/crypto/internal/hash.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/crypto/internal/hash.h 2019-10-29 09:26:25.409220460 +0100 @@ -110,6 +110,8 @@ struct shash_instance *inst); void shash_free_instance(struct crypto_instance *inst); +int crypto_grab_shash(struct crypto_shash_spawn *spawn, + const char *name, u32 type, u32 mask); int crypto_init_shash_spawn(struct crypto_shash_spawn *spawn, struct shash_alg *alg, struct crypto_instance *inst); @@ -119,6 +121,12 @@ crypto_drop_spawn(&spawn->base); } +static inline struct shash_alg *crypto_spawn_shash_alg( + struct crypto_shash_spawn *spawn) +{ + return container_of(spawn->base.alg, struct shash_alg, base); +} + struct shash_alg *shash_attr_alg(struct rtattr *rta, u32 type, u32 mask); int shash_ahash_update(struct ahash_request *req, struct shash_desc *desc); diff -ruw linux-4.4.115/include/drm/drm_crtc.h linux-4.4.115-fbx/include/drm/drm_crtc.h --- linux-4.4.115/include/drm/drm_crtc.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/drm/drm_crtc.h 2019-01-22 16:16:28.163288606 +0100 @@ -61,7 +61,7 @@ struct drm_object_properties *properties; }; -#define DRM_OBJECT_MAX_PROPERTY 24 +#define DRM_OBJECT_MAX_PROPERTY 64 struct drm_object_properties { int count, atomic_count; /* NOTE: if we ever start dynamically destroying properties (ie. @@ -644,6 +644,23 @@ * @audio_latency: audio latency info from ELD, if found * @null_edid_counter: track sinks that give us all zeros for the EDID * @bad_edid_counter: track sinks that give us an EDID with invalid checksum + * @max_tmds_char: indicates the maximum TMDS Character Rate supported + * @scdc_present: when set the sink supports SCDC functionality + * @rr_capable: when set the sink is capable of initiating an SCDC read request + * @supports_scramble: when set the sink supports less than 340Mcsc scrambling + * @flags_3d: 3D view(s) supported by the sink, see drm_edid.h (DRM_EDID_3D_*) + * @pt_scan_info: PT scan info obtained from the VCDB of EDID + * @it_scan_info: IT scan info obtained from the VCDB of EDID + * @ce_scan_info: CE scan info obtained from the VCDB of EDID + * @color_enc_fmt: Colorimetry encoding formats of sink + * @hdr_eotf: Electro optical transfer function obtained from HDR block + * @hdr_metadata_type_one: Metadata type one obtained from HDR block + * @hdr_max_luminance: desired max luminance obtained from HDR block + * @hdr_avg_luminance: desired avg luminance obtained from HDR block + * @hdr_min_luminance: desired min luminance obtained from HDR block + * @hdr_supported: does the sink support HDR content + * @rgb_qs: does the sink declare RGB selectable quantization range + * @yuv_qs: does the sink declare YCC selectable quantization range * @edid_corrupt: indicates whether the last read EDID was corrupt * @debugfs_entry: debugfs directory for this connector * @state: current atomic state for this connector @@ -717,6 +734,24 @@ int null_edid_counter; /* needed to workaround some HW bugs where we get all 0s */ unsigned bad_edid_counter; + /* EDID bits HDMI 2.0 */ + int max_tmds_char; /* in Mcsc */ + bool scdc_present; + bool rr_capable; + bool supports_scramble; + int flags_3d; + u8 pt_scan_info; + u8 it_scan_info; + u8 ce_scan_info; + u8 color_enc_fmt; + u32 hdr_eotf; + bool hdr_metadata_type_one; + u32 hdr_max_luminance; + u32 hdr_avg_luminance; + u32 hdr_min_luminance; + bool hdr_supported; + bool rgb_qs; + bool yuv_qs; /* Flag for raw EDID header corruption - used in Displayport * compliance testing - * Displayport Link CTS Core 1.2 rev1.1 4.2.2.6 */ diff -ruw linux-4.4.115/include/drm/drm_displayid.h linux-4.4.115-fbx/include/drm/drm_displayid.h --- linux-4.4.115/include/drm/drm_displayid.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/drm/drm_displayid.h 2019-01-22 16:16:28.163288606 +0100 @@ -73,4 +73,21 @@ u8 topology_id[8]; } __packed; +struct displayid_detailed_timings_1 { + u8 pixel_clock[3]; + u8 flags; + u8 hactive[2]; + u8 hblank[2]; + u8 hsync[2]; + u8 hsw[2]; + u8 vactive[2]; + u8 vblank[2]; + u8 vsync[2]; + u8 vsw[2]; +} __packed; + +struct displayid_detailed_timing_block { + struct displayid_block base; + struct displayid_detailed_timings_1 timings[0]; +}; #endif diff -ruw linux-4.4.115/include/drm/drm_edid.h linux-4.4.115-fbx/include/drm/drm_edid.h --- linux-4.4.115/include/drm/drm_edid.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/drm/drm_edid.h 2019-10-29 09:26:25.413220499 +0100 @@ -209,6 +209,20 @@ #define DRM_EDID_HDMI_DC_30 (1 << 4) #define DRM_EDID_HDMI_DC_Y444 (1 << 3) +/* YCBCR 420 deep color modes */ +#define DRM_EDID_YCBCR420_DC_48 (1 << 2) +#define DRM_EDID_YCBCR420_DC_36 (1 << 1) +#define DRM_EDID_YCBCR420_DC_30 (1 << 0) + +#define DRM_EDID_COLORIMETRY_xvYCC_601 (1 << 0) +#define DRM_EDID_COLORIMETRY_xvYCC_709 (1 << 1) +#define DRM_EDID_COLORIMETRY_sYCC_601 (1 << 2) +#define DRM_EDID_COLORIMETRY_ADBYCC_601 (1 << 3) +#define DRM_EDID_COLORIMETRY_ADB_RGB (1 << 4) +#define DRM_EDID_COLORIMETRY_BT2020_CYCC (1 << 5) +#define DRM_EDID_COLORIMETRY_BT2020_YCC (1 << 6) +#define DRM_EDID_COLORIMETRY_BT2020_RGB (1 << 7) + /* ELD Header Block */ #define DRM_ELD_HEADER_BLOCK_SIZE 4 @@ -266,6 +280,11 @@ #define DRM_ELD_CEA_SAD(mnl, sad) (20 + (mnl) + 3 * (sad)) +/* HDMI 2.0 */ +#define DRM_EDID_3D_INDEPENDENT_VIEW (1 << 2) +#define DRM_EDID_3D_DUAL_VIEW (1 << 1) +#define DRM_EDID_3D_OSD_DISPARITY (1 << 0) + struct edid { u8 header[8]; /* Vendor & product info */ diff -ruw linux-4.4.115/include/drm/drm_mm.h linux-4.4.115-fbx/include/drm/drm_mm.h --- linux-4.4.115/include/drm/drm_mm.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/drm/drm_mm.h 2019-01-22 16:16:28.163288606 +0100 @@ -37,6 +37,7 @@ * Generic range manager structs */ #include +#include #include #include #include @@ -48,6 +49,7 @@ DRM_MM_SEARCH_DEFAULT = 0, DRM_MM_SEARCH_BEST = 1 << 0, DRM_MM_SEARCH_BELOW = 1 << 1, + DRM_MM_SEARCH_BOTTOM_UP = 1 << 2, }; enum drm_mm_allocator_flags { @@ -61,6 +63,8 @@ struct drm_mm_node { struct list_head node_list; struct list_head hole_stack; + struct rb_node rb; + struct rb_node hole_node; unsigned hole_follows : 1; unsigned scanned_block : 1; unsigned scanned_prev_free : 1; @@ -70,6 +74,7 @@ unsigned long color; u64 start; u64 size; + u64 __subtree_last; struct drm_mm *mm; }; @@ -79,6 +84,10 @@ /* head_node.node_list is the list of all memory nodes, ordered * according to the (increasing) start address of the memory node. */ struct drm_mm_node head_node; + /* Keep an interval_tree for fast lookup of drm_mm_nodes by address. */ + struct rb_root interval_tree; + struct rb_root holes_tree; + unsigned int scan_check_range : 1; unsigned scan_alignment; unsigned long scan_color; @@ -301,6 +310,12 @@ void drm_mm_takedown(struct drm_mm *mm); bool drm_mm_clean(struct drm_mm *mm); +struct drm_mm_node * +drm_mm_interval_first(struct drm_mm *mm, u64 start, u64 last); + +struct drm_mm_node * +drm_mm_interval_next(struct drm_mm_node *node, u64 start, u64 last); + void drm_mm_init_scan(struct drm_mm *mm, u64 size, unsigned alignment, diff -ruw linux-4.4.115/include/dt-bindings/input/linux-event-codes.h linux-4.4.115-fbx/include/dt-bindings/input/linux-event-codes.h --- linux-4.4.115/include/dt-bindings/input/linux-event-codes.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/dt-bindings/input/linux-event-codes.h 2019-10-29 09:26:25.545221791 +0100 @@ -611,6 +611,37 @@ #define KEY_KBDINPUTASSIST_ACCEPT 0x264 #define KEY_KBDINPUTASSIST_CANCEL 0x265 +/* Diagonal movement keys */ +#define KEY_RIGHT_UP 0x266 +#define KEY_RIGHT_DOWN 0x267 +#define KEY_LEFT_UP 0x268 +#define KEY_LEFT_DOWN 0x269 + +#define KEY_ROOT_MENU 0x26a /* Show Device's Root Menu */ +/* Show Top Menu of the Media (e.g. DVD) */ +#define KEY_MEDIA_TOP_MENU 0x26b +#define KEY_NUMERIC_11 0x26c +#define KEY_NUMERIC_12 0x26d +/* + * Toggle Audio Description: refers to an audio service that helps blind and + * visually impaired consumers understand the action in a program. Note: in + * some countries this is referred to as "Video Description". + */ +#define KEY_AUDIO_DESC 0x26e +#define KEY_3D_MODE 0x26f +#define KEY_NEXT_FAVORITE 0x270 +#define KEY_STOP_RECORD 0x271 +#define KEY_PAUSE_RECORD 0x272 +#define KEY_VOD 0x273 /* Video on Demand */ +#define KEY_UNMUTE 0x274 +#define KEY_FASTREVERSE 0x275 +#define KEY_SLOWREVERSE 0x276 +/* + * Control a data application associated with the currently viewed channel, + * e.g. teletext or data broadcast application (MHEG, MHP, HbbTV, etc.) + */ +#define KEY_DATA 0x275 + #define BTN_TRIGGER_HAPPY 0x2c0 #define BTN_TRIGGER_HAPPY1 0x2c0 #define BTN_TRIGGER_HAPPY2 0x2c1 @@ -653,6 +684,18 @@ #define BTN_TRIGGER_HAPPY39 0x2e6 #define BTN_TRIGGER_HAPPY40 0x2e7 +#define KEY_APP_TV 0x2f1 +#define KEY_APP_REPLAY 0x2f2 +#define KEY_APP_VIDEOCLUB 0x2f3 +#define KEY_APP_WHATSON 0x2f4 +#define KEY_APP_RECORDS 0x2f5 +#define KEY_APP_MEDIA 0x2f6 +#define KEY_APP_YOUTUBE 0x2f7 +#define KEY_APP_RADIOS 0x2f8 +#define KEY_APP_CANALVOD 0x2f9 +#define KEY_APP_PIP 0x2fa +#define KEY_APP_NETFLIX 0x2fb + /* We avoid low common keys in module aliases so they don't get huge. */ #define KEY_MIN_INTERESTING KEY_MUTE #define KEY_MAX 0x2ff @@ -749,7 +792,11 @@ #define SW_ROTATE_LOCK 0x0c /* set = rotate locked/disabled */ #define SW_LINEIN_INSERT 0x0d /* set = inserted */ #define SW_MUTE_DEVICE 0x0e /* set = device disabled */ -#define SW_MAX 0x0f +#define SW_HPHL_OVERCURRENT 0x0f /* set = over current on left hph */ +#define SW_HPHR_OVERCURRENT 0x10 /* set = over current on right hph */ +#define SW_MICROPHONE2_INSERT 0x11 /* set = inserted */ +#define SW_UNSUPPORT_INSERT 0x12 /* set = unsupported device inserted */ +#define SW_MAX 0x20 #define SW_CNT (SW_MAX+1) /* diff -ruw linux-4.4.115/include/kvm/arm_vgic.h linux-4.4.115-fbx/include/kvm/arm_vgic.h --- linux-4.4.115/include/kvm/arm_vgic.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/kvm/arm_vgic.h 2019-01-22 16:16:28.187288823 +0100 @@ -279,6 +279,12 @@ u32 vgic_lr[VGIC_V2_MAX_LRS]; }; +/* + * LRs are stored in reverse order in memory. make sure we index them + * correctly. + */ +#define VGIC_V3_LR_INDEX(lr) (VGIC_V3_MAX_LRS - 1 - lr) + struct vgic_v3_cpu_if { #ifdef CONFIG_KVM_ARM_VGIC_V3 u32 vgic_hcr; diff -ruw linux-4.4.115/include/linux/alarmtimer.h linux-4.4.115-fbx/include/linux/alarmtimer.h --- linux-4.4.115/include/linux/alarmtimer.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/linux/alarmtimer.h 2019-10-29 09:26:25.413220499 +0100 @@ -5,10 +5,12 @@ #include #include #include +#include enum alarmtimer_type { ALARM_REALTIME, ALARM_BOOTTIME, + ALARM_POWEROFF_REALTIME, ALARM_NUMTYPE, }; @@ -48,6 +50,9 @@ void alarm_restart(struct alarm *alarm); int alarm_try_to_cancel(struct alarm *alarm); int alarm_cancel(struct alarm *alarm); +void set_power_on_alarm(void); +void power_on_alarm_init(void); +enum alarmtimer_type clock2alarm(clockid_t clockid); u64 alarm_forward(struct alarm *alarm, ktime_t now, ktime_t interval); u64 alarm_forward_now(struct alarm *alarm, ktime_t interval); @@ -55,5 +60,8 @@ /* Provide way to access the rtc device being used by alarmtimers */ struct rtc_device *alarmtimer_get_rtcdev(void); +#ifdef CONFIG_RTC_DRV_QPNP +extern bool poweron_alarm; +#endif #endif diff -ruw linux-4.4.115/include/linux/amba/bus.h linux-4.4.115-fbx/include/linux/amba/bus.h --- linux-4.4.115/include/linux/amba/bus.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/linux/amba/bus.h 2019-01-22 16:16:28.187288823 +0100 @@ -163,4 +163,13 @@ #define module_amba_driver(__amba_drv) \ module_driver(__amba_drv, amba_driver_register, amba_driver_unregister) +/* + * builtin_amba_driver() - Helper macro for drivers that don't do anything + * special in driver initcall. This eliminates a lot of boilerplate. Each + * driver may only use this macro once, and calling it replaces the instance + * device_initcall(). + */ +#define builtin_amba_driver(__amba_drv) \ + builtin_driver(__amba_drv, amba_driver_register) + #endif diff -ruw linux-4.4.115/include/linux/backing-dev-defs.h linux-4.4.115-fbx/include/linux/backing-dev-defs.h --- linux-4.4.115/include/linux/backing-dev-defs.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/linux/backing-dev-defs.h 2019-10-29 09:26:25.413220499 +0100 @@ -10,6 +10,7 @@ #include #include #include +#include struct page; struct device; @@ -141,6 +142,7 @@ void *congested_data; /* Pointer to aux data for congested func */ char *name; + struct kref refcnt; /* Reference counter for the structure */ unsigned int min_ratio; unsigned int max_ratio, max_prop_frac; diff -ruw linux-4.4.115/include/linux/backing-dev.h linux-4.4.115-fbx/include/linux/backing-dev.h --- linux-4.4.115/include/linux/backing-dev.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/linux/backing-dev.h 2019-10-29 09:26:25.413220499 +0100 @@ -18,7 +18,14 @@ #include int __must_check bdi_init(struct backing_dev_info *bdi); -void bdi_exit(struct backing_dev_info *bdi); + +static inline struct backing_dev_info *bdi_get(struct backing_dev_info *bdi) +{ + kref_get(&bdi->refcnt); + return bdi; +} + +void bdi_put(struct backing_dev_info *bdi); __printf(3, 4) int bdi_register(struct backing_dev_info *bdi, struct device *parent, @@ -29,6 +36,7 @@ int __must_check bdi_setup_and_register(struct backing_dev_info *, char *); void bdi_destroy(struct backing_dev_info *bdi); +struct backing_dev_info *bdi_alloc_node(gfp_t gfp_mask, int node_id); void wb_start_writeback(struct bdi_writeback *wb, long nr_pages, bool range_cyclic, enum wb_reason reason); diff -ruw linux-4.4.115/include/linux/balloon_compaction.h linux-4.4.115-fbx/include/linux/balloon_compaction.h --- linux-4.4.115/include/linux/balloon_compaction.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/linux/balloon_compaction.h 2019-01-22 16:16:28.191288859 +0100 @@ -48,6 +48,7 @@ #include #include #include +#include /* * Balloon device information descriptor. @@ -62,6 +63,7 @@ struct list_head pages; /* Pages enqueued & handled to Host */ int (*migratepage)(struct balloon_dev_info *, struct page *newpage, struct page *page, enum migrate_mode mode); + struct inode *inode; }; extern struct page *balloon_page_enqueue(struct balloon_dev_info *b_dev_info); @@ -73,45 +75,19 @@ spin_lock_init(&balloon->pages_lock); INIT_LIST_HEAD(&balloon->pages); balloon->migratepage = NULL; + balloon->inode = NULL; } #ifdef CONFIG_BALLOON_COMPACTION -extern bool balloon_page_isolate(struct page *page); +extern const struct address_space_operations balloon_aops; +extern bool balloon_page_isolate(struct page *page, + isolate_mode_t mode); extern void balloon_page_putback(struct page *page); -extern int balloon_page_migrate(struct page *newpage, +extern int balloon_page_migrate(struct address_space *mapping, + struct page *newpage, struct page *page, enum migrate_mode mode); /* - * __is_movable_balloon_page - helper to perform @page PageBalloon tests - */ -static inline bool __is_movable_balloon_page(struct page *page) -{ - return PageBalloon(page); -} - -/* - * balloon_page_movable - test PageBalloon to identify balloon pages - * and PagePrivate to check that the page is not - * isolated and can be moved by compaction/migration. - * - * As we might return false positives in the case of a balloon page being just - * released under us, this need to be re-tested later, under the page lock. - */ -static inline bool balloon_page_movable(struct page *page) -{ - return PageBalloon(page) && PagePrivate(page); -} - -/* - * isolated_balloon_page - identify an isolated balloon page on private - * compaction/migration page lists. - */ -static inline bool isolated_balloon_page(struct page *page) -{ - return PageBalloon(page); -} - -/* * balloon_page_insert - insert a page into the balloon's page list and make * the page->private assignment accordingly. * @balloon : pointer to balloon device @@ -124,7 +100,7 @@ struct page *page) { __SetPageBalloon(page); - SetPagePrivate(page); + __SetPageMovable(page, balloon->inode->i_mapping); set_page_private(page, (unsigned long)balloon); list_add(&page->lru, &balloon->pages); } @@ -140,12 +116,15 @@ static inline void balloon_page_delete(struct page *page) { __ClearPageBalloon(page); + __ClearPageMovable(page); set_page_private(page, 0); - if (PagePrivate(page)) { - ClearPagePrivate(page); + /* + * No touch page.lru field once @page has been isolated + * because VM is using the field. + */ + if (!PageIsolated(page)) list_del(&page->lru); } -} /* * balloon_page_device - get the b_dev_info descriptor for the balloon device diff -ruw linux-4.4.115/include/linux/blkdev.h linux-4.4.115-fbx/include/linux/blkdev.h --- linux-4.4.115/include/linux/blkdev.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/linux/blkdev.h 2019-10-29 09:26:25.417220539 +0100 @@ -197,6 +197,9 @@ /* for bidi */ struct request *next_rq; + + ktime_t lat_hist_io_start; + int lat_hist_enabled; }; static inline unsigned short req_get_ioprio(struct request *req) @@ -329,7 +332,7 @@ */ struct delayed_work delay_work; - struct backing_dev_info backing_dev_info; + struct backing_dev_info *backing_dev_info; /* * The queue owner gets to use this for whatever they like. @@ -489,6 +492,7 @@ #define QUEUE_FLAG_INIT_DONE 20 /* queue is initialized */ #define QUEUE_FLAG_NO_SG_MERGE 21 /* don't attempt to merge SG segments*/ #define QUEUE_FLAG_POLL 22 /* IO polling enabled if set */ +#define QUEUE_FLAG_FAST 23 /* fast block device (e.g. ram based) */ #define QUEUE_FLAG_DEFAULT ((1 << QUEUE_FLAG_IO_STAT) | \ (1 << QUEUE_FLAG_STACKABLE) | \ @@ -577,6 +581,7 @@ #define blk_queue_discard(q) test_bit(QUEUE_FLAG_DISCARD, &(q)->queue_flags) #define blk_queue_secdiscard(q) (blk_queue_discard(q) && \ test_bit(QUEUE_FLAG_SECDISCARD, &(q)->queue_flags)) +#define blk_queue_fast(q) test_bit(QUEUE_FLAG_FAST, &(q)->queue_flags) #define blk_noretry_request(rq) \ ((rq)->cmd_flags & (REQ_FAILFAST_DEV|REQ_FAILFAST_TRANSPORT| \ @@ -794,6 +799,7 @@ extern int sg_scsi_ioctl(struct request_queue *, struct gendisk *, fmode_t, struct scsi_ioctl_command __user *); +extern void blk_recalc_rq_segments(struct request *rq); extern int blk_queue_enter(struct request_queue *q, gfp_t gfp); extern void blk_queue_exit(struct request_queue *q); extern void blk_start_queue(struct request_queue *q); @@ -1006,6 +1012,8 @@ extern struct backing_dev_info *blk_get_backing_dev_info(struct block_device *bdev); extern int blk_rq_map_sg(struct request_queue *, struct request *, struct scatterlist *); +extern int blk_rq_map_sg_no_cluster + (struct request_queue *, struct request *, struct scatterlist *); extern void blk_dump_rq_flags(struct request *, char *); extern long nr_blockdev_pages(void); @@ -1118,6 +1126,7 @@ #define BLKDEV_DISCARD_SECURE 0x01 /* secure discard */ extern int blkdev_issue_flush(struct block_device *, gfp_t, sector_t *); +extern int blkdev_issue_barrier(struct block_device *, gfp_t, sector_t *); extern int blkdev_issue_discard(struct block_device *bdev, sector_t sector, sector_t nr_sects, gfp_t gfp_mask, unsigned long flags); extern int blkdev_issue_write_same(struct block_device *bdev, sector_t sector, @@ -1656,6 +1665,62 @@ struct writeback_control *); extern long bdev_direct_access(struct block_device *, sector_t, void __pmem **addr, unsigned long *pfn, long size); + +/* + * X-axis for IO latency histogram support. + */ +static const u_int64_t latency_x_axis_us[] = { + 100, + 200, + 300, + 400, + 500, + 600, + 700, + 800, + 900, + 1000, + 1200, + 1400, + 1600, + 1800, + 2000, + 2500, + 3000, + 4000, + 5000, + 6000, + 7000, + 9000, + 10000 +}; + +#define BLK_IO_LAT_HIST_DISABLE 0 +#define BLK_IO_LAT_HIST_ENABLE 1 +#define BLK_IO_LAT_HIST_ZERO 2 + +struct io_latency_state { + u_int64_t latency_y_axis[ARRAY_SIZE(latency_x_axis_us) + 1]; + u_int64_t latency_elems; + u_int64_t latency_sum; +}; + +static inline void +blk_update_latency_hist(struct io_latency_state *s, u_int64_t delta_us) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(latency_x_axis_us); i++) + if (delta_us < (u_int64_t)latency_x_axis_us[i]) + break; + s->latency_y_axis[i]++; + s->latency_elems++; + s->latency_sum += delta_us; +} + +ssize_t blk_latency_hist_show(char* name, struct io_latency_state *s, + char *buf, int buf_size); + #else /* CONFIG_BLOCK */ struct block_device; diff -ruw linux-4.4.115/include/linux/blk_types.h linux-4.4.115-fbx/include/linux/blk_types.h --- linux-4.4.115/include/linux/blk_types.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/linux/blk_types.h 2019-10-29 09:26:25.417220539 +0100 @@ -39,6 +39,15 @@ current bvec */ }; +#ifdef CONFIG_BLOCK_PERF_FRAMEWORK +/* Double declaration from ktime.h so as to not break the include dependency + * chain. Should be kept up to date. + */ +union blk_ktime { + s64 tv64; +}; +#endif + /* * main unit of I/O for the block layer and lower layers (ie drivers and * stacking drivers) @@ -54,6 +63,10 @@ struct bvec_iter bi_iter; +#ifdef CONFIG_BLOCK_PERF_FRAMEWORK + union blk_ktime submit_time; + unsigned int blk_sector_count; +#endif /* Number of segments in this BIO after * physical address coalescing is performed. */ @@ -88,6 +101,13 @@ unsigned short bi_vcnt; /* how many bio_vec's */ /* + * When using dircet-io (O_DIRECT), we can't get the inode from a bio + * by walking bio->bi_io_vec->bv_page->mapping->host + * since the page is anon. + */ + struct inode *bi_dio_inode; + + /* * Everything starting with bi_max_vecs will be preserved by bio_reset() */ @@ -127,6 +147,13 @@ */ #define BIO_RESET_BITS 13 #define BIO_OWNS_VEC 13 /* bio_free() should free bvec */ +/* + * Added for Req based dm which need to perform post processing. This flag + * ensures blk_update_request does not free the bios or request, this is done + * at the dm level + */ +#define BIO_DONTFREE 14 +#define BIO_INLINECRYPT 15 /* * top 4 bits of bio flags indicate the pool this bio came from @@ -161,6 +188,8 @@ __REQ_INTEGRITY, /* I/O includes block integrity payload */ __REQ_FUA, /* forced unit access */ __REQ_FLUSH, /* request for cache flush */ + __REQ_POST_FLUSH_BARRIER,/* cache barrier after a data req */ + __REQ_BARRIER, /* marks flush req as barrier */ /* bio only flags */ __REQ_RAHEAD, /* read ahead, can fail anytime */ @@ -168,7 +197,7 @@ * throttling rules. Don't do it again. */ /* request only flags */ - __REQ_SORTED, /* elevator knows about this request */ + __REQ_SORTED = __REQ_RAHEAD, /* elevator knows about this request */ __REQ_SOFTBARRIER, /* may not be passed by ioscheduler */ __REQ_NOMERGE, /* don't touch this for merging */ __REQ_STARTED, /* drive already may have started this one */ @@ -189,6 +218,7 @@ __REQ_HASHED, /* on IO scheduler merge hash */ __REQ_MQ_INFLIGHT, /* track inflight for MQ */ __REQ_NO_TIMEOUT, /* requests may never expire */ + __REQ_URGENT, /* urgent request */ __REQ_NR_BITS, /* stops here */ }; @@ -201,6 +231,7 @@ #define REQ_PRIO (1ULL << __REQ_PRIO) #define REQ_DISCARD (1ULL << __REQ_DISCARD) #define REQ_WRITE_SAME (1ULL << __REQ_WRITE_SAME) +#define REQ_URGENT (1ULL << __REQ_URGENT) #define REQ_NOIDLE (1ULL << __REQ_NOIDLE) #define REQ_INTEGRITY (1ULL << __REQ_INTEGRITY) @@ -209,7 +240,7 @@ #define REQ_COMMON_MASK \ (REQ_WRITE | REQ_FAILFAST_MASK | REQ_SYNC | REQ_META | REQ_PRIO | \ REQ_DISCARD | REQ_WRITE_SAME | REQ_NOIDLE | REQ_FLUSH | REQ_FUA | \ - REQ_SECURE | REQ_INTEGRITY) + REQ_SECURE | REQ_INTEGRITY | REQ_BARRIER) #define REQ_CLONE_MASK REQ_COMMON_MASK #define BIO_NO_ADVANCE_ITER_MASK (REQ_DISCARD|REQ_WRITE_SAME) @@ -224,6 +255,7 @@ #define REQ_SORTED (1ULL << __REQ_SORTED) #define REQ_SOFTBARRIER (1ULL << __REQ_SOFTBARRIER) #define REQ_FUA (1ULL << __REQ_FUA) +#define REQ_BARRIER (1ULL << __REQ_BARRIER) #define REQ_NOMERGE (1ULL << __REQ_NOMERGE) #define REQ_STARTED (1ULL << __REQ_STARTED) #define REQ_DONTPREP (1ULL << __REQ_DONTPREP) @@ -235,6 +267,7 @@ #define REQ_ALLOCED (1ULL << __REQ_ALLOCED) #define REQ_COPY_USER (1ULL << __REQ_COPY_USER) #define REQ_FLUSH (1ULL << __REQ_FLUSH) +#define REQ_POST_FLUSH_BARRIER (1ULL << __REQ_POST_FLUSH_BARRIER) #define REQ_FLUSH_SEQ (1ULL << __REQ_FLUSH_SEQ) #define REQ_IO_STAT (1ULL << __REQ_IO_STAT) #define REQ_MIXED_MERGE (1ULL << __REQ_MIXED_MERGE) diff -ruw linux-4.4.115/include/linux/bug.h linux-4.4.115-fbx/include/linux/bug.h --- linux-4.4.115/include/linux/bug.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/linux/bug.h 2019-10-29 09:26:25.417220539 +0100 @@ -109,4 +109,10 @@ } #endif /* CONFIG_GENERIC_BUG */ + +#ifdef CONFIG_PANIC_ON_DATA_CORRUPTION +#define PANIC_CORRUPTION 1 +#else +#define PANIC_CORRUPTION 0 +#endif /* CONFIG_PANIC_ON_DATA_CORRUPTION */ #endif /* _LINUX_BUG_H */ diff -ruw linux-4.4.115/include/linux/cache.h linux-4.4.115-fbx/include/linux/cache.h --- linux-4.4.115/include/linux/cache.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/linux/cache.h 2019-01-22 16:16:28.199288932 +0100 @@ -12,10 +12,24 @@ #define SMP_CACHE_BYTES L1_CACHE_BYTES #endif +/* + * __read_mostly is used to keep rarely changing variables out of frequently + * updated cachelines. If an architecture doesn't support it, ignore the + * hint. + */ #ifndef __read_mostly #define __read_mostly #endif +/* + * __ro_after_init is used to mark things that are read-only after init (i.e. + * after mark_rodata_ro() has been called). These are effectively read-only, + * but may get written to during init, so can't live in .rodata (via "const"). + */ +#ifndef __ro_after_init +#define __ro_after_init __attribute__((__section__(".data..ro_after_init"))) +#endif + #ifndef ____cacheline_aligned #define ____cacheline_aligned __attribute__((__aligned__(SMP_CACHE_BYTES))) #endif diff -ruw linux-4.4.115/include/linux/cgroup-defs.h linux-4.4.115-fbx/include/linux/cgroup-defs.h --- linux-4.4.115/include/linux/cgroup-defs.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/linux/cgroup-defs.h 2019-01-22 16:16:28.203288968 +0100 @@ -66,7 +66,6 @@ /* cgroup_root->flags */ enum { - CGRP_ROOT_SANE_BEHAVIOR = (1 << 0), /* __DEVEL__sane_behavior specified */ CGRP_ROOT_NOPREFIX = (1 << 1), /* mounted subsystems have no named prefix */ CGRP_ROOT_XATTR = (1 << 2), /* supports extended attributes */ }; diff -ruw linux-4.4.115/include/linux/cgroup_subsys.h linux-4.4.115-fbx/include/linux/cgroup_subsys.h --- linux-4.4.115/include/linux/cgroup_subsys.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/linux/cgroup_subsys.h 2019-01-22 16:16:28.203288968 +0100 @@ -26,6 +26,10 @@ SUBSYS(cpuacct) #endif +#if IS_ENABLED(CONFIG_CGROUP_SCHEDTUNE) +SUBSYS(schedtune) +#endif + #if IS_ENABLED(CONFIG_BLK_CGROUP) SUBSYS(io) #endif diff -ruw linux-4.4.115/include/linux/clkdev.h linux-4.4.115-fbx/include/linux/clkdev.h --- linux-4.4.115/include/linux/clkdev.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/linux/clkdev.h 2019-01-22 16:16:28.203288968 +0100 @@ -21,6 +21,7 @@ struct list_head node; const char *dev_id; const char *con_id; + int of_idx; struct clk *clk; struct clk_hw *clk_hw; }; diff -ruw linux-4.4.115/include/linux/clk.h linux-4.4.115-fbx/include/linux/clk.h --- linux-4.4.115/include/linux/clk.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/linux/clk.h 2019-01-22 16:16:28.203288968 +0100 @@ -408,6 +408,16 @@ */ struct clk *clk_get_sys(const char *dev_id, const char *con_id); +/** + * clk_set_flags - set the custom specific flags for this clock + * @clk: clock source + * @flags: custom flags which would be hardware specific, defined for specific + * hardware. + * + * Returns success 0 or negative errno. + */ +int clk_set_flags(struct clk *clk, unsigned long flags); + #else /* !CONFIG_HAVE_CLK */ static inline struct clk *clk_get(struct device *dev, const char *id) @@ -488,7 +498,7 @@ struct device_node; struct of_phandle_args; -#if defined(CONFIG_OF) && defined(CONFIG_COMMON_CLK) +#if defined(CONFIG_OF) struct clk *of_clk_get(struct device_node *np, int index); struct clk *of_clk_get_by_name(struct device_node *np, const char *name); struct clk *of_clk_get_from_provider(struct of_phandle_args *clkspec); diff -ruw linux-4.4.115/include/linux/clk-provider.h linux-4.4.115-fbx/include/linux/clk-provider.h --- linux-4.4.115/include/linux/clk-provider.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/linux/clk-provider.h 2019-01-22 16:16:28.203288968 +0100 @@ -13,6 +13,7 @@ #include #include +#include #ifdef CONFIG_COMMON_CLK @@ -31,6 +32,11 @@ #define CLK_SET_RATE_NO_REPARENT BIT(7) /* don't re-parent on rate change */ #define CLK_GET_ACCURACY_NOCACHE BIT(8) /* do not use the cached clk accuracy */ #define CLK_RECALC_NEW_RATES BIT(9) /* recalc rates after notifications */ +#define CLK_IS_CRITICAL BIT(11) /* do not gate, ever */ +#define CLK_ENABLE_HAND_OFF BIT(12) /* enable clock when registered. + hand-off enable_count & prepare_count + to first consumer that enables clk */ +#define CLK_IS_MEASURE BIT(14) /* measure clock */ struct clk; struct clk_hw; @@ -173,6 +179,16 @@ * directory is provided as an argument. Called with * prepare_lock held. Returns 0 on success, -EERROR otherwise. * + * @set_flags: Set custom flags which deals with hardware specifics. Returns 0 + * on success, -EEROR otherwise. + * + * @list_registers: Queries the hardware to get the current register contents. + * This callback is optional and required clocks could + * add this callback. + * + * @list_rate: Return the nth supported frequency for a given clock which is + * below rate_max on success and -ENXIO in case of no frequency + * table. * * The clk_enable/clk_disable and clk_prepare/clk_unprepare pairs allow * implementations to split any work between atomic (enable) and sleepable @@ -213,6 +229,11 @@ int (*set_phase)(struct clk_hw *hw, int degrees); void (*init)(struct clk_hw *hw); int (*debug_init)(struct clk_hw *hw, struct dentry *dentry); + int (*set_flags)(struct clk_hw *hw, unsigned flags); + void (*list_registers)(struct seq_file *f, + struct clk_hw *hw); + long (*list_rate)(struct clk_hw *hw, unsigned n, + unsigned long rate_max); }; /** @@ -224,6 +245,9 @@ * @parent_names: array of string names for all possible parents * @num_parents: number of possible parents * @flags: framework-level hints and quirks + * @vdd_class: voltage scaling requirement class + * @rate_max: maximum clock rate in Hz supported at each voltage level + * @num_rate_max: number of maximum voltage level supported */ struct clk_init_data { const char *name; @@ -231,7 +255,72 @@ const char * const *parent_names; u8 num_parents; unsigned long flags; -}; + struct clk_vdd_class *vdd_class; + unsigned long *rate_max; + int num_rate_max; +}; + +struct regulator; + +/** + * struct clk_vdd_class - Voltage scaling class + * @class_name: name of the class + * @regulator: array of regulators + * @num_regulators: size of regulator array. Standard regulator APIs will be + used if this field > 0 + * @set_vdd: function to call when applying a new voltage setting + * @vdd_uv: sorted 2D array of legal voltage settings. Indexed by level, then + regulator + * @level_votes: array of votes for each level + * @num_levels: specifies the size of level_votes array + * @skip_handoff: do not vote for the max possible voltage during init + * @use_max_uV: use INT_MAX for max_uV when calling regulator_set_voltage + * @cur_level: the currently set voltage level + * @lock: lock to protect this struct + */ +struct clk_vdd_class { + const char *class_name; + struct regulator **regulator; + int num_regulators; + int (*set_vdd)(struct clk_vdd_class *v_class, int level); + int *vdd_uv; + int *level_votes; + int num_levels; + bool skip_handoff; + bool use_max_uV; + unsigned long cur_level; + struct mutex lock; +}; + +#define DEFINE_VDD_CLASS(_name, _set_vdd, _num_levels) \ + struct clk_vdd_class _name = { \ + .class_name = #_name, \ + .set_vdd = _set_vdd, \ + .level_votes = (int [_num_levels]) {}, \ + .num_levels = _num_levels, \ + .cur_level = _num_levels, \ + .lock = __MUTEX_INITIALIZER(_name.lock) \ + } + +#define DEFINE_VDD_REGULATORS(_name, _num_levels, _num_regulators, _vdd_uv) \ + struct clk_vdd_class _name = { \ + .class_name = #_name, \ + .vdd_uv = _vdd_uv, \ + .regulator = (struct regulator * [_num_regulators]) {}, \ + .num_regulators = _num_regulators, \ + .level_votes = (int [_num_levels]) {}, \ + .num_levels = _num_levels, \ + .cur_level = _num_levels, \ + .lock = __MUTEX_INITIALIZER(_name.lock) \ + } + +#define DEFINE_VDD_REGS_INIT(_name, _num_regulators) \ + struct clk_vdd_class _name = { \ + .class_name = #_name, \ + .regulator = (struct regulator * [_num_regulators]) {}, \ + .num_regulators = _num_regulators, \ + .lock = __MUTEX_INITIALIZER(_name.lock) \ + } /** * struct clk_hw - handle for traversing from a struct clk to its corresponding @@ -667,6 +756,9 @@ void clk_hw_set_rate_range(struct clk_hw *hw, unsigned long min_rate, unsigned long max_rate); +unsigned long clk_aggregate_rate(struct clk_hw *hw, + const struct clk_core *parent); + static inline void __clk_hw_set_clk(struct clk_hw *dst, struct clk_hw *src) { dst->clk = src->clk; @@ -704,7 +796,8 @@ int of_clk_parent_fill(struct device_node *np, const char **parents, unsigned int size); const char *of_clk_get_parent_name(struct device_node *np, int index); - +int of_clk_detect_critical(struct device_node *np, int index, + unsigned long *flags); void of_clk_init(const struct of_device_id *matches); #else /* !CONFIG_OF */ @@ -742,6 +835,13 @@ { return NULL; } + +static inline int of_clk_detect_critical(struct device_node *np, int index, + unsigned long *flags) +{ + return 0; +} + #define of_clk_init(matches) \ { while (0); } #endif /* CONFIG_OF */ @@ -781,6 +881,13 @@ struct dentry *clk_debugfs_add_file(struct clk_hw *hw, char *name, umode_t mode, void *data, const struct file_operations *fops); #endif +#else +struct of_device_id; + +static inline void __init of_clk_init(const struct of_device_id *matches) +{ + return; +} #endif /* CONFIG_COMMON_CLK */ #endif /* CLK_PROVIDER_H */ diff -ruw linux-4.4.115/include/linux/clocksource.h linux-4.4.115-fbx/include/linux/clocksource.h --- linux-4.4.115/include/linux/clocksource.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/linux/clocksource.h 2019-10-29 09:26:25.421220578 +0100 @@ -186,6 +186,7 @@ extern void clocksource_resume(void); extern struct clocksource * __init clocksource_default_clock(void); extern void clocksource_mark_unstable(struct clocksource *cs); +extern void clocksource_select_force(void); extern u64 clocks_calc_max_nsecs(u32 mult, u32 shift, u32 maxadj, u64 mask, u64 *max_cycles); diff -ruw linux-4.4.115/include/linux/compaction.h linux-4.4.115-fbx/include/linux/compaction.h --- linux-4.4.115/include/linux/compaction.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/linux/compaction.h 2019-01-22 16:16:28.207289004 +0100 @@ -52,6 +52,10 @@ bool alloc_success); extern bool compaction_restarting(struct zone *zone, int order); +extern int kcompactd_run(int nid); +extern void kcompactd_stop(int nid); +extern void wakeup_kcompactd(pg_data_t *pgdat, int order, int classzone_idx); + #else static inline unsigned long try_to_compact_pages(gfp_t gfp_mask, unsigned int order, int alloc_flags, @@ -84,9 +88,22 @@ return true; } +static inline int kcompactd_run(int nid) +{ + return 0; +} +static inline void kcompactd_stop(int nid) +{ +} + +static inline void wakeup_kcompactd(pg_data_t *pgdat, int order, int classzone_idx) +{ +} + #endif /* CONFIG_COMPACTION */ #if defined(CONFIG_COMPACTION) && defined(CONFIG_SYSFS) && defined(CONFIG_NUMA) +struct node; extern int compaction_register_node(struct node *node); extern void compaction_unregister_node(struct node *node); diff -ruw linux-4.4.115/include/linux/compiler-gcc.h linux-4.4.115-fbx/include/linux/compiler-gcc.h --- linux-4.4.115/include/linux/compiler-gcc.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/linux/compiler-gcc.h 2019-10-29 09:26:25.421220578 +0100 @@ -66,18 +66,22 @@ /* * Force always-inline if the user requests it so via the .config, - * or if gcc is too old: + * or if gcc is too old. + * GCC does not warn about unused static inline functions for + * -Wunused-function. This turns out to avoid the need for complex #ifdef + * directives. Suppress the warning in clang as well by using "unused" + * function attribute, which is redundant but not harmful for gcc. */ #if !defined(CONFIG_ARCH_SUPPORTS_OPTIMIZED_INLINING) || \ !defined(CONFIG_OPTIMIZE_INLINING) || (__GNUC__ < 4) -#define inline inline __attribute__((always_inline)) notrace -#define __inline__ __inline__ __attribute__((always_inline)) notrace -#define __inline __inline __attribute__((always_inline)) notrace +#define inline inline __attribute__((always_inline,unused)) notrace +#define __inline__ __inline__ __attribute__((always_inline,unused)) notrace +#define __inline __inline __attribute__((always_inline,unused)) notrace #else /* A lot of inline functions can cause havoc with function tracing */ -#define inline inline notrace -#define __inline__ __inline__ notrace -#define __inline __inline notrace +#define inline inline __attribute__((unused)) notrace +#define __inline__ __inline__ __attribute__((unused)) notrace +#define __inline __inline __attribute__((unused)) notrace #endif #define __always_inline inline __attribute__((always_inline)) diff -ruw linux-4.4.115/include/linux/coresight.h linux-4.4.115-fbx/include/linux/coresight.h --- linux-4.4.115/include/linux/coresight.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/linux/coresight.h 2019-01-22 16:16:28.207289004 +0100 @@ -1,4 +1,4 @@ -/* Copyright (c) 2012, The Linux Foundation. All rights reserved. +/* Copyright (c) 2012, 2016 The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -40,6 +40,13 @@ extern struct bus_type coresight_bustype; +enum coresight_clk_rate { + CORESIGHT_CLK_RATE_OFF, + CORESIGHT_CLK_RATE_TRACE = 1000, + CORESIGHT_CLK_RATE_HSTRACE = 2000, + CORESIGHT_CLK_RATE_FIXED = 3000, +}; + enum coresight_dev_type { CORESIGHT_DEV_TYPE_NONE, CORESIGHT_DEV_TYPE_SINK, @@ -94,6 +101,7 @@ connected to. * @nr_outport: number of output ports for this component. * @clk: The clock this component is associated to. + * @default_sink: Flag to set default sink */ struct coresight_platform_data { int cpu; @@ -104,6 +112,7 @@ int *child_ports; int nr_outport; struct clk *clk; + bool default_sink; }; /** @@ -185,10 +194,12 @@ * Operations available for sinks * @enable: enables the sink. * @disable: disables the sink. + * @abort: captures sink trace on abort */ struct coresight_ops_sink { int (*enable)(struct coresight_device *csdev); void (*disable)(struct coresight_device *csdev); + void (*abort)(struct coresight_device *csdev); }; /** @@ -230,6 +241,7 @@ extern void coresight_disable(struct coresight_device *csdev); extern int coresight_timeout(void __iomem *addr, u32 offset, int position, int value); +extern void coresight_abort(void); #else static inline struct coresight_device * coresight_register(struct coresight_desc *desc) { return NULL; } @@ -239,14 +251,19 @@ static inline void coresight_disable(struct coresight_device *csdev) {} static inline int coresight_timeout(void __iomem *addr, u32 offset, int position, int value) { return 1; } +static inline void coresight_abort(void) {} #endif -#ifdef CONFIG_OF +#if defined(CONFIG_OF) && defined(CONFIG_CORESIGHT) extern struct coresight_platform_data *of_get_coresight_platform_data( struct device *dev, struct device_node *node); +extern struct coresight_cti_data *of_get_coresight_cti_data( + struct device *dev, struct device_node *node); #else static inline struct coresight_platform_data *of_get_coresight_platform_data( struct device *dev, struct device_node *node) { return NULL; } +static inline struct coresight_cti_data *of_get_coresight_cti_data( + struct device *dev, struct device_node *node) { return NULL; } #endif #ifdef CONFIG_PID_NS diff -ruw linux-4.4.115/include/linux/cpu_cooling.h linux-4.4.115-fbx/include/linux/cpu_cooling.h --- linux-4.4.115/include/linux/cpu_cooling.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/linux/cpu_cooling.h 2019-01-22 16:16:28.207289004 +0100 @@ -31,6 +31,11 @@ typedef int (*get_static_t)(cpumask_t *cpumask, int interval, unsigned long voltage, u32 *power); +struct cpu_cooling_ops { + int (*ceil_limit)(int, u32); + int (*get_cur_state)(int, unsigned long *); +}; + #ifdef CONFIG_CPU_THERMAL /** * cpufreq_cooling_register - function to create cpufreq cooling device. @@ -43,6 +48,10 @@ cpufreq_power_cooling_register(const struct cpumask *clip_cpus, u32 capacitance, get_static_t plat_static_func); +struct thermal_cooling_device * +cpufreq_platform_cooling_register(const struct cpumask *clip_cpus, + struct cpu_cooling_ops *ops); + /** * of_cpufreq_cooling_register - create cpufreq cooling device based on DT. * @np: a valid struct device_node to the cooling device device tree node. @@ -111,6 +120,13 @@ { return NULL; } + +static inline struct thermal_cooling_device * +cpufreq_platform_cooling_register(const struct cpumask *clip_cpus, + struct cpu_cooling_ops *ops) +{ + return NULL; +} static inline void cpufreq_cooling_unregister(struct thermal_cooling_device *cdev) diff -ruw linux-4.4.115/include/linux/cpufreq.h linux-4.4.115-fbx/include/linux/cpufreq.h --- linux-4.4.115/include/linux/cpufreq.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/linux/cpufreq.h 2019-10-29 09:26:25.425220617 +0100 @@ -107,6 +107,30 @@ */ struct rw_semaphore rwsem; + + /* + * Fast switch flags: + * - fast_switch_possible should be set by the driver if it can + * guarantee that frequency can be changed on any CPU sharing the + * policy and that the change will affect all of the policy CPUs then. + * - fast_switch_enabled is to be set by governors that support fast + * freqnency switching with the help of cpufreq_enable_fast_switch(). + */ + bool fast_switch_possible; + bool fast_switch_enabled; + + /* + * Preferred average time interval between consecutive invocations of + * the driver to set the frequency for this policy. To be set by the + * scaling driver (0, which is the default, means no preference). + */ + unsigned int up_transition_delay_us; + unsigned int down_transition_delay_us; + + /* Cached frequency lookup from cpufreq_driver_resolve_freq. */ + unsigned int cached_target_freq; + int cached_resolved_idx; + /* Synchronization for frequency transitions */ bool transition_ongoing; /* Tracks transition status */ spinlock_t transition_lock; @@ -160,6 +184,7 @@ int cpufreq_get_policy(struct cpufreq_policy *policy, unsigned int cpu); int cpufreq_update_policy(unsigned int cpu); bool have_governor_per_policy(void); +bool cpufreq_driver_is_slow(void); struct kobject *get_governor_parent_kobj(struct cpufreq_policy *policy); #else static inline unsigned int cpufreq_get(unsigned int cpu) @@ -317,6 +342,14 @@ */ #define CPUFREQ_NEED_INITIAL_FREQ_CHECK (1 << 5) +/* + * Indicates that it is safe to call cpufreq_driver_target from + * non-interruptable context in scheduler hot paths. Drivers must + * opt-in to this flag, as the safe default is that they might sleep + * or be too slow for hot path use. + */ +#define CPUFREQ_DRIVER_FAST (1 << 6) + int cpufreq_register_driver(struct cpufreq_driver *driver_data); int cpufreq_unregister_driver(struct cpufreq_driver *driver_data); @@ -361,6 +394,7 @@ #define CPUFREQ_TRANSITION_NOTIFIER (0) #define CPUFREQ_POLICY_NOTIFIER (1) +#define CPUFREQ_GOVINFO_NOTIFIER (2) /* Transition notifiers */ #define CPUFREQ_PRECHANGE (0) @@ -373,6 +407,9 @@ #define CPUFREQ_CREATE_POLICY (3) #define CPUFREQ_REMOVE_POLICY (4) +/* Govinfo Notifiers */ +#define CPUFREQ_LOAD_CHANGE (0) + #ifdef CONFIG_CPU_FREQ int cpufreq_register_notifier(struct notifier_block *nb, unsigned int list); int cpufreq_unregister_notifier(struct notifier_block *nb, unsigned int list); @@ -381,6 +418,16 @@ struct cpufreq_freqs *freqs); void cpufreq_freq_transition_end(struct cpufreq_policy *policy, struct cpufreq_freqs *freqs, int transition_failed); +/* + * Governor specific info that can be passed to modules that subscribe + * to CPUFREQ_GOVINFO_NOTIFIER + */ +struct cpufreq_govinfo { + unsigned int cpu; + unsigned int load; + unsigned int sampling_rate_us; +}; +extern struct atomic_notifier_head cpufreq_govinfo_notifier_list; #else /* CONFIG_CPU_FREQ */ static inline int cpufreq_register_notifier(struct notifier_block *nb, @@ -462,6 +509,8 @@ int __cpufreq_driver_target(struct cpufreq_policy *policy, unsigned int target_freq, unsigned int relation); +unsigned int cpufreq_driver_resolve_freq(struct cpufreq_policy *policy, + unsigned int target_freq); int cpufreq_register_governor(struct cpufreq_governor *governor); void cpufreq_unregister_governor(struct cpufreq_governor *governor); @@ -487,8 +536,48 @@ #elif defined(CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE) extern struct cpufreq_governor cpufreq_gov_conservative; #define CPUFREQ_DEFAULT_GOVERNOR (&cpufreq_gov_conservative) +#elif defined(CONFIG_CPU_FREQ_DEFAULT_GOV_INTERACTIVE) +extern struct cpufreq_governor cpufreq_gov_interactive; +#define CPUFREQ_DEFAULT_GOVERNOR (&cpufreq_gov_interactive) +#elif defined(CONFIG_CPU_FREQ_DEFAULT_GOV_SCHED) +extern struct cpufreq_governor cpufreq_gov_sched; +#define CPUFREQ_DEFAULT_GOVERNOR (&cpufreq_gov_sched) +#elif defined(CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL) +extern struct cpufreq_governor cpufreq_gov_schedutil; +#define CPUFREQ_DEFAULT_GOVERNOR (&cpufreq_gov_schedutil) #endif +static inline void cpufreq_policy_apply_limits(struct cpufreq_policy *policy) +{ + if (policy->max < policy->cur) + __cpufreq_driver_target(policy, policy->max, CPUFREQ_RELATION_H); + else if (policy->min > policy->cur) + __cpufreq_driver_target(policy, policy->min, CPUFREQ_RELATION_L); +} + +/* Governor attribute set */ +struct gov_attr_set { + struct kobject kobj; + struct list_head policy_list; + struct mutex update_lock; + int usage_count; +}; + +/* sysfs ops for cpufreq governors */ +extern const struct sysfs_ops governor_sysfs_ops; + +void gov_attr_set_init(struct gov_attr_set *attr_set, struct list_head *list_node); +void gov_attr_set_get(struct gov_attr_set *attr_set, struct list_head *list_node); +unsigned int gov_attr_set_put(struct gov_attr_set *attr_set, struct list_head *list_node); + +/* Governor sysfs attribute */ +struct governor_attr { + struct attribute attr; + ssize_t (*show)(struct gov_attr_set *attr_set, char *buf); + ssize_t (*store)(struct gov_attr_set *attr_set, const char *buf, + size_t count); +}; + /********************************************************************* * FREQUENCY TABLE HELPERS * *********************************************************************/ @@ -616,4 +705,8 @@ int cpufreq_generic_init(struct cpufreq_policy *policy, struct cpufreq_frequency_table *table, unsigned int transition_latency); + +struct sched_domain; +unsigned long cpufreq_scale_freq_capacity(struct sched_domain *sd, int cpu); +unsigned long cpufreq_scale_max_freq_capacity(int cpu); #endif /* _LINUX_CPUFREQ_H */ diff -ruw linux-4.4.115/include/linux/cpu.h linux-4.4.115-fbx/include/linux/cpu.h --- linux-4.4.115/include/linux/cpu.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/linux/cpu.h 2019-10-29 09:26:25.425220617 +0100 @@ -27,6 +27,19 @@ struct device dev; }; +struct cpu_pstate_pwr { + unsigned int freq; + uint32_t power; +}; + +struct cpu_pwr_stats { + int cpu; + long temp; + struct cpu_pstate_pwr *ptable; + bool throttling; + int len; +}; + extern int register_cpu(struct cpu *cpu, int num); extern struct device *get_cpu_device(unsigned cpu); extern bool cpu_is_hotpluggable(unsigned cpu); @@ -228,6 +241,7 @@ extern void cpu_hotplug_begin(void); extern void cpu_hotplug_done(void); extern void get_online_cpus(void); +extern void cpu_hotplug_mutex_held(void); extern void put_online_cpus(void); extern void cpu_hotplug_disable(void); extern void cpu_hotplug_enable(void); @@ -250,6 +264,7 @@ #define cpu_hotplug_enable() do { } while (0) #define hotcpu_notifier(fn, pri) do { (void)(fn); } while (0) #define __hotcpu_notifier(fn, pri) do { (void)(fn); } while (0) +#define cpu_hotplug_mutex_held() do { } while (0) /* These aren't inline functions due to a GCC bug. */ #define register_hotcpu_notifier(nb) ({ (void)(nb); 0; }) #define __register_hotcpu_notifier(nb) ({ (void)(nb); 0; }) @@ -265,6 +280,9 @@ static inline void enable_nonboot_cpus(void) {} #endif /* !CONFIG_PM_SLEEP_SMP */ +struct cpu_pwr_stats *get_cpu_pwr_stats(void); +void trigger_cpu_pwr_stats_calc(void); + enum cpuhp_state { CPUHP_OFFLINE, CPUHP_ONLINE, @@ -290,4 +308,11 @@ bool cpu_report_death(void); #endif /* #ifdef CONFIG_HOTPLUG_CPU */ +#define IDLE_START 1 +#define IDLE_END 2 + +void idle_notifier_register(struct notifier_block *n); +void idle_notifier_unregister(struct notifier_block *n); +void idle_notifier_call_chain(unsigned long val); + #endif /* _LINUX_CPU_H_ */ diff -ruw linux-4.4.115/include/linux/cpuidle.h linux-4.4.115-fbx/include/linux/cpuidle.h --- linux-4.4.115/include/linux/cpuidle.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/linux/cpuidle.h 2019-10-29 09:26:25.425220617 +0100 @@ -204,7 +204,7 @@ #endif /* kernel/sched/idle.c */ -extern void sched_idle_set_state(struct cpuidle_state *idle_state); +extern void sched_idle_set_state(struct cpuidle_state *idle_state, int index); extern void default_idle_call(void); #ifdef CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED diff -ruw linux-4.4.115/include/linux/cpumask.h linux-4.4.115-fbx/include/linux/cpumask.h --- linux-4.4.115/include/linux/cpumask.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/linux/cpumask.h 2019-10-29 09:26:25.425220617 +0100 @@ -53,6 +53,7 @@ * cpu_present_mask - has bit 'cpu' set iff cpu is populated * cpu_online_mask - has bit 'cpu' set iff cpu available to scheduler * cpu_active_mask - has bit 'cpu' set iff cpu available to migration + * cpu_isolated_mask- has bit 'cpu' set iff cpu isolated * * If !CONFIG_HOTPLUG_CPU, present == possible, and active == online. * @@ -89,25 +90,38 @@ extern const struct cpumask *const cpu_online_mask; extern const struct cpumask *const cpu_present_mask; extern const struct cpumask *const cpu_active_mask; +extern const struct cpumask *const cpu_isolated_mask; #if NR_CPUS > 1 #define num_online_cpus() cpumask_weight(cpu_online_mask) #define num_possible_cpus() cpumask_weight(cpu_possible_mask) #define num_present_cpus() cpumask_weight(cpu_present_mask) #define num_active_cpus() cpumask_weight(cpu_active_mask) +#define num_isolated_cpus() cpumask_weight(cpu_isolated_mask) +#define num_online_uniso_cpus() \ +({ \ + cpumask_t mask; \ + \ + cpumask_andnot(&mask, cpu_online_mask, cpu_isolated_mask); \ + cpumask_weight(&mask); \ +}) #define cpu_online(cpu) cpumask_test_cpu((cpu), cpu_online_mask) #define cpu_possible(cpu) cpumask_test_cpu((cpu), cpu_possible_mask) #define cpu_present(cpu) cpumask_test_cpu((cpu), cpu_present_mask) #define cpu_active(cpu) cpumask_test_cpu((cpu), cpu_active_mask) +#define cpu_isolated(cpu) cpumask_test_cpu((cpu), cpu_isolated_mask) #else #define num_online_cpus() 1U #define num_possible_cpus() 1U #define num_present_cpus() 1U #define num_active_cpus() 1U +#define num_isolated_cpus() 0U +#define num_online_uniso_cpus() 1U #define cpu_online(cpu) ((cpu) == 0) #define cpu_possible(cpu) ((cpu) == 0) #define cpu_present(cpu) ((cpu) == 0) #define cpu_active(cpu) ((cpu) == 0) +#define cpu_isolated(cpu) ((cpu) != 0) #endif /* verify cpu argument to cpumask_* operators */ @@ -714,12 +728,14 @@ #define for_each_possible_cpu(cpu) for_each_cpu((cpu), cpu_possible_mask) #define for_each_online_cpu(cpu) for_each_cpu((cpu), cpu_online_mask) #define for_each_present_cpu(cpu) for_each_cpu((cpu), cpu_present_mask) +#define for_each_isolated_cpu(cpu) for_each_cpu((cpu), cpu_isolated_mask) /* Wrappers for arch boot code to manipulate normally-constant masks */ void set_cpu_possible(unsigned int cpu, bool possible); void set_cpu_present(unsigned int cpu, bool present); void set_cpu_online(unsigned int cpu, bool online); void set_cpu_active(unsigned int cpu, bool active); +void set_cpu_isolated(unsigned int cpu, bool isolated); void init_cpu_present(const struct cpumask *src); void init_cpu_possible(const struct cpumask *src); void init_cpu_online(const struct cpumask *src); diff -ruw linux-4.4.115/include/linux/cpu_pm.h linux-4.4.115-fbx/include/linux/cpu_pm.h --- linux-4.4.115/include/linux/cpu_pm.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/linux/cpu_pm.h 2019-01-22 16:16:28.207289004 +0100 @@ -71,8 +71,8 @@ int cpu_pm_unregister_notifier(struct notifier_block *nb); int cpu_pm_enter(void); int cpu_pm_exit(void); -int cpu_cluster_pm_enter(void); -int cpu_cluster_pm_exit(void); +int cpu_cluster_pm_enter(unsigned long aff_level); +int cpu_cluster_pm_exit(unsigned long aff_level); #else @@ -96,12 +96,12 @@ return 0; } -static inline int cpu_cluster_pm_enter(void) +static inline int cpu_cluster_pm_enter(unsigned long aff_level) { return 0; } -static inline int cpu_cluster_pm_exit(void) +static inline int cpu_cluster_pm_exit(unsigned long aff_level) { return 0; } diff -ruw linux-4.4.115/include/linux/crypto.h linux-4.4.115-fbx/include/linux/crypto.h --- linux-4.4.115/include/linux/crypto.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/linux/crypto.h 2019-10-29 09:26:25.425220617 +0100 @@ -24,6 +24,7 @@ #include #include #include +#include /* * Autoloaded crypto modules should only use a prefixed name to avoid allowing @@ -470,6 +471,45 @@ } CRYPTO_MINALIGN_ATTR; /* + * A helper struct for waiting for completion of async crypto ops + */ +struct crypto_wait { + struct completion completion; + int err; +}; + +/* + * Macro for declaring a crypto op async wait object on stack + */ +#define DECLARE_CRYPTO_WAIT(_wait) \ + struct crypto_wait _wait = { \ + COMPLETION_INITIALIZER_ONSTACK((_wait).completion), 0 } + +/* + * Async ops completion helper functioons + */ +void crypto_req_done(struct crypto_async_request *req, int err); + +static inline int crypto_wait_req(int err, struct crypto_wait *wait) +{ + switch (err) { + case -EINPROGRESS: + case -EBUSY: + wait_for_completion(&wait->completion); + reinit_completion(&wait->completion); + err = wait->err; + break; + }; + + return err; +} + +static inline void crypto_init_wait(struct crypto_wait *wait) +{ + init_completion(&wait->completion); +} + +/* * Algorithm registration interface. */ int crypto_register_alg(struct crypto_alg *alg); diff -ruw linux-4.4.115/include/linux/dcache.h linux-4.4.115-fbx/include/linux/dcache.h --- linux-4.4.115/include/linux/dcache.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/linux/dcache.h 2019-01-22 16:16:28.215289076 +0100 @@ -162,6 +162,7 @@ int (*d_manage)(struct dentry *, bool); struct inode *(*d_select_inode)(struct dentry *, unsigned); struct dentry *(*d_real)(struct dentry *, struct inode *); + void (*d_canonical_path)(const struct path *, struct path *); } ____cacheline_aligned; /* @@ -228,6 +229,7 @@ #define DCACHE_MAY_FREE 0x00800000 #define DCACHE_FALLTHRU 0x01000000 /* Fall through to lower layer */ #define DCACHE_OP_SELECT_INODE 0x02000000 /* Unioned entry: dcache op selects inode */ +#define DCACHE_ENCRYPTED_WITH_KEY 0x04000000 /* dir is encrypted with a valid key */ #define DCACHE_OP_REAL 0x08000000 extern seqlock_t rename_lock; diff -ruw linux-4.4.115/include/linux/devfreq_cooling.h linux-4.4.115-fbx/include/linux/devfreq_cooling.h --- linux-4.4.115/include/linux/devfreq_cooling.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/linux/devfreq_cooling.h 2019-01-22 16:16:28.215289076 +0100 @@ -4,6 +4,8 @@ * * Copyright (C) 2014-2015 ARM Limited * + * Copyright (c) 2018 The Linux Foundation. All rights reserved. + * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. @@ -20,7 +22,6 @@ #include #include -#ifdef CONFIG_DEVFREQ_THERMAL /** * struct devfreq_cooling_power - Devfreq cooling power ops @@ -43,6 +44,8 @@ unsigned long dyn_power_coeff; }; +#ifdef CONFIG_DEVFREQ_THERMAL + struct thermal_cooling_device * of_devfreq_cooling_register_power(struct device_node *np, struct devfreq *df, struct devfreq_cooling_power *dfc_power); diff -ruw linux-4.4.115/include/linux/devfreq.h linux-4.4.115-fbx/include/linux/devfreq.h --- linux-4.4.115/include/linux/devfreq.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/linux/devfreq.h 2019-01-22 16:16:28.215289076 +0100 @@ -5,6 +5,8 @@ * Copyright (C) 2011 Samsung Electronics * MyungJoo Ham * + * Copyright (c) 2018 The Linux Foundation. All rights reserved. + * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. @@ -52,6 +54,10 @@ */ #define DEVFREQ_FLAG_LEAST_UPPER_BOUND 0x1 +#define DEVFREQ_FLAG_WAKEUP_MAXFREQ 0x2 +#define DEVFREQ_FLAG_FAST_HINT 0x4 +#define DEVFREQ_FLAG_SLOW_HINT 0x8 + /** * struct devfreq_dev_profile - Devfreq's user device profile * @initial_freq: The operating frequency when devfreq_add_device() is @@ -114,7 +120,8 @@ struct list_head node; const char name[DEVFREQ_NAME_LEN]; - int (*get_target_freq)(struct devfreq *this, unsigned long *freq); + int (*get_target_freq)(struct devfreq *this, unsigned long *freq, + u32 *flag); int (*event_handler)(struct devfreq *devfreq, unsigned int event, void *data); }; @@ -196,6 +203,14 @@ extern int devfreq_suspend_device(struct devfreq *devfreq); extern int devfreq_resume_device(struct devfreq *devfreq); +/** + * update_devfreq() - Reevaluate the device and configure frequency + * @devfreq: the devfreq device + * + * Note: devfreq->lock must be held + */ +extern int update_devfreq(struct devfreq *devfreq); + /* Helper functions for devfreq user device driver with OPP. */ extern struct dev_pm_opp *devfreq_recommended_opp(struct device *dev, unsigned long *freq, u32 flags); @@ -231,6 +246,9 @@ * the governor may consider slowing the frequency down. * Specify 0 to use the default. Valid value = 0 to 100. * downdifferential < upthreshold must hold. + * @simple_scaling: Setting this flag will scale the clocks up only if the + * load is above @upthreshold and will scale the clocks + * down only if the load is below @downdifferential. * * If the fed devfreq_simple_ondemand_data pointer is NULL to the governor, * the governor uses the default values. @@ -238,6 +256,7 @@ struct devfreq_simple_ondemand_data { unsigned int upthreshold; unsigned int downdifferential; + unsigned int simple_scaling; }; #endif diff -ruw linux-4.4.115/include/linux/device.h linux-4.4.115-fbx/include/linux/device.h --- linux-4.4.115/include/linux/device.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/linux/device.h 2019-10-29 09:26:25.429220656 +0100 @@ -683,6 +683,18 @@ int devm_add_action(struct device *dev, void (*action)(void *), void *data); void devm_remove_action(struct device *dev, void (*action)(void *), void *data); +static inline int devm_add_action_or_reset(struct device *dev, + void (*action)(void *), void *data) +{ + int ret; + + ret = devm_add_action(dev, action, data); + if (ret) + action(data); + + return ret; +} + struct device_dma_parameters { /* * a low level driver may set these to teach IOMMU code about @@ -817,6 +829,7 @@ struct cma *cma_area; /* contiguous memory area for dma allocations */ #endif + struct removed_region *removed_mem; /* arch specific additions */ struct dev_archdata archdata; @@ -1012,6 +1025,7 @@ extern void lock_device_hotplug(void); extern void unlock_device_hotplug(void); extern int lock_device_hotplug_sysfs(void); +extern void lock_device_hotplug_assert(void); extern int device_offline(struct device *dev); extern int device_online(struct device *dev); extern void set_primary_fwnode(struct device *dev, struct fwnode_handle *fwnode); diff -ruw linux-4.4.115/include/linux/device-mapper.h linux-4.4.115-fbx/include/linux/device-mapper.h --- linux-4.4.115/include/linux/device-mapper.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/linux/device-mapper.h 2019-10-29 09:26:25.425220617 +0100 @@ -383,6 +383,12 @@ void *dm_get_mdptr(struct mapped_device *md); /* + * Export the device via the ioctl interface (uses mdptr). + */ +int dm_ioctl_export(struct mapped_device *md, const char *name, + const char *uuid); + +/* * A device can still be used while suspended, but I/O is deferred. */ int dm_suspend(struct mapped_device *md, unsigned suspend_flags); @@ -409,6 +415,13 @@ struct queue_limits *dm_get_queue_limits(struct mapped_device *md); +void dm_lock_md_type(struct mapped_device *md); +void dm_unlock_md_type(struct mapped_device *md); +void dm_set_md_type(struct mapped_device *md, unsigned type); +unsigned dm_get_md_type(struct mapped_device *md); +int dm_setup_md_queue(struct mapped_device *md); +unsigned dm_table_get_type(struct dm_table *t); + /* * Geometry functions. */ @@ -603,4 +616,11 @@ return (n << SECTOR_SHIFT); } +/*----------------------------------------------------------------- + * Helper for block layer and dm core operations + *----------------------------------------------------------------- + */ +void dm_dispatch_request(struct request *rq); +void dm_kill_unmapped_request(struct request *rq, int error); +void dm_end_request(struct request *clone, int error); #endif /* _LINUX_DEVICE_MAPPER_H */ diff -ruw linux-4.4.115/include/linux/dma-attrs.h linux-4.4.115-fbx/include/linux/dma-attrs.h --- linux-4.4.115/include/linux/dma-attrs.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/linux/dma-attrs.h 2019-01-22 16:16:28.219289113 +0100 @@ -18,6 +18,12 @@ DMA_ATTR_NO_KERNEL_MAPPING, DMA_ATTR_SKIP_CPU_SYNC, DMA_ATTR_FORCE_CONTIGUOUS, + DMA_ATTR_STRONGLY_ORDERED, + DMA_ATTR_SKIP_ZEROING, + DMA_ATTR_NO_DELAYED_UNMAP, + DMA_ATTR_EXEC_MAPPING, + DMA_ATTR_FORCE_COHERENT, + DMA_ATTR_FORCE_NON_COHERENT, DMA_ATTR_MAX, }; diff -ruw linux-4.4.115/include/linux/dma-mapping.h linux-4.4.115-fbx/include/linux/dma-mapping.h --- linux-4.4.115/include/linux/dma-mapping.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/linux/dma-mapping.h 2019-01-22 16:16:28.219289113 +0100 @@ -61,6 +61,10 @@ int (*mapping_error)(struct device *dev, dma_addr_t dma_addr); int (*dma_supported)(struct device *dev, u64 mask); int (*set_dma_mask)(struct device *dev, u64 mask); + void *(*remap)(struct device *dev, void *cpu_addr, dma_addr_t handle, + size_t size, struct dma_attrs *attrs); + void (*unremap)(struct device *dev, void *remapped_address, + size_t size); #ifdef ARCH_HAS_DMA_GET_REQUIRED_MASK u64 (*get_required_mask)(struct device *dev); #endif @@ -89,6 +93,40 @@ #include #endif +#ifndef CONFIG_NO_DMA +static inline void *dma_remap(struct device *dev, void *cpu_addr, + dma_addr_t dma_handle, size_t size, struct dma_attrs *attrs) +{ + const struct dma_map_ops *ops = get_dma_ops(dev); + BUG_ON(!ops); + + if (!ops->remap) { + WARN_ONCE(1, "Remap function not implemented for %pS\n", + ops->remap); + return NULL; + } + + return ops->remap(dev, cpu_addr, dma_handle, size, attrs); +} + + +static inline void dma_unremap(struct device *dev, void *remapped_addr, + size_t size) +{ + const struct dma_map_ops *ops = get_dma_ops(dev); + BUG_ON(!ops); + + if (!ops->unremap) { + WARN_ONCE(1, "unremap function not implemented for %pS\n", + ops->unremap); + return; + } + + return ops->unremap(dev, remapped_addr, size); +} +#endif + + static inline u64 dma_get_mask(struct device *dev) { if (dev && dev->dma_mask && *dev->dma_mask) diff -ruw linux-4.4.115/include/linux/efi.h linux-4.4.115-fbx/include/linux/efi.h --- linux-4.4.115/include/linux/efi.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/linux/efi.h 2019-10-29 09:26:25.429220656 +0100 @@ -299,7 +299,7 @@ void *open_protocol_information; void *protocols_per_handle; void *locate_handle_buffer; - void *locate_protocol; + efi_status_t (*locate_protocol)(efi_guid_t *, void *, void **); void *install_multiple_protocol_interfaces; void *uninstall_multiple_protocol_interfaces; void *calculate_crc32; @@ -599,6 +599,10 @@ #define EFI_PROPERTIES_TABLE_GUID \ EFI_GUID( 0x880aaca3, 0x4adc, 0x4a04, 0x90, 0x79, 0xb7, 0x47, 0x34, 0x08, 0x25, 0xe5 ) +#define EFI_RNG_PROTOCOL_GUID \ + EFI_GUID(0x3152bca5, 0xeade, 0x433d, \ + 0x86, 0x2e, 0xc0, 0x1c, 0xdc, 0x29, 0x1f, 0x44) + typedef struct { efi_guid_t guid; u64 table; @@ -1288,7 +1292,7 @@ unsigned long *load_addr, unsigned long *load_size); -efi_status_t efi_parse_options(char *cmdline); +efi_status_t efi_parse_options(char const *cmdline); bool efi_runtime_disabled(void); #endif /* _LINUX_EFI_H */ diff -ruw linux-4.4.115/include/linux/extcon.h linux-4.4.115-fbx/include/linux/extcon.h --- linux-4.4.115/include/linux/extcon.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/linux/extcon.h 2019-10-29 09:26:25.429220656 +0100 @@ -55,6 +55,12 @@ #define EXTCON_JACK_SPDIF_IN 26 /* Sony Philips Digital InterFace */ #define EXTCON_JACK_SPDIF_OUT 27 +/* connector orientation 0 - CC1, 1 - CC2 */ +#define EXTCON_USB_CC 28 + +/* connector speed 0 - High Speed, 1 - super speed */ +#define EXTCON_USB_SPEED 29 + /* Display external connector */ #define EXTCON_DISP_HDMI 40 /* High-Definition Multimedia Interface */ #define EXTCON_DISP_MHL 41 /* Mobile High-Definition Link */ diff -ruw linux-4.4.115/include/linux/fb.h linux-4.4.115-fbx/include/linux/fb.h --- linux-4.4.115/include/linux/fb.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/linux/fb.h 2019-01-22 16:16:28.227289185 +0100 @@ -288,10 +288,18 @@ int (*fb_ioctl)(struct fb_info *info, unsigned int cmd, unsigned long arg); + /* perform fb specific ioctl v2 (optional) - provides file param */ + int (*fb_ioctl_v2)(struct fb_info *info, unsigned int cmd, + unsigned long arg, struct file *file); + /* Handle 32bit compat ioctl (optional) */ int (*fb_compat_ioctl)(struct fb_info *info, unsigned cmd, unsigned long arg); + /* Handle 32bit compat ioctl (optional) */ + int (*fb_compat_ioctl_v2)(struct fb_info *info, unsigned cmd, + unsigned long arg, struct file *file); + /* perform fb specific mmap */ int (*fb_mmap)(struct fb_info *info, struct vm_area_struct *vma); @@ -460,17 +468,8 @@ struct fb_cmap cmap; /* Current cmap */ struct list_head modelist; /* mode list */ struct fb_videomode *mode; /* current mode */ + struct file *file; /* current file node */ -#ifdef CONFIG_FB_BACKLIGHT - /* assigned backlight device */ - /* set before framebuffer registration, - remove after unregister */ - struct backlight_device *bl_dev; - - /* Backlight level curve */ - struct mutex bl_curve_mutex; - u8 bl_curve[FB_BACKLIGHT_LEVELS]; -#endif #ifdef CONFIG_FB_DEFERRED_IO struct delayed_work deferred_work; struct fb_deferred_io *fbdefio; diff -ruw linux-4.4.115/include/linux/fence.h linux-4.4.115-fbx/include/linux/fence.h --- linux-4.4.115/include/linux/fence.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/linux/fence.h 2019-01-22 16:16:28.227289185 +0100 @@ -107,6 +107,7 @@ * @get_driver_name: returns the driver name. * @get_timeline_name: return the name of the context this fence belongs to. * @enable_signaling: enable software signaling of fence. + * @disable_signaling: disable software signaling of fence (optional). * @signaled: [optional] peek whether the fence is signaled, can be null. * @wait: custom wait implementation, or fence_default_wait. * @release: [optional] called on destruction of fence, can be null @@ -166,6 +167,7 @@ const char * (*get_driver_name)(struct fence *fence); const char * (*get_timeline_name)(struct fence *fence); bool (*enable_signaling)(struct fence *fence); + void (*disable_signaling)(struct fence *fence); bool (*signaled)(struct fence *fence); signed long (*wait)(struct fence *fence, bool intr, signed long timeout); void (*release)(struct fence *fence); diff -ruw linux-4.4.115/include/linux/firmware.h linux-4.4.115-fbx/include/linux/firmware.h --- linux-4.4.115/include/linux/firmware.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/linux/firmware.h 2019-01-22 16:16:28.227289185 +0100 @@ -48,6 +48,20 @@ int request_firmware_direct(const struct firmware **fw, const char *name, struct device *device); +int request_firmware_into_buf(const char *name, struct device *device, + phys_addr_t dest_addr, size_t dest_size, + void * (*map_fw_mem)(phys_addr_t phys, + size_t size, void *data), + void (*unmap_fw_mem)(void *virt, size_t size, + void *data), + void *data); +int request_firmware_nowait_into_buf( + struct module *module, bool uevent, + const char *name, struct device *device, gfp_t gfp, void *context, + void (*cont)(const struct firmware *fw, void *context), + phys_addr_t dest_addr, size_t dest_size, + void * (*map_fw_mem)(phys_addr_t phys, size_t size, void *data), + void (*unmap_fw_mem)(void *virt, size_t size, void *data), void *data); void release_firmware(const struct firmware *fw); #else static inline int request_firmware(const struct firmware **fw, @@ -56,6 +70,19 @@ { return -EINVAL; } +static inline int request_firmware_into_buf(const char *name, + struct device *device, + phys_addr_t dest_addr, + size_t dest_size, + void * (*map_fw_mem)(phys_addr_t phys, + size_t size, void *data), + void (*unmap_fw_mem)(void *virt, + size_t size, + void *data), + void *data) +{ + return -EINVAL; +} static inline int request_firmware_nowait( struct module *module, bool uevent, const char *name, struct device *device, gfp_t gfp, void *context, @@ -63,7 +90,16 @@ { return -EINVAL; } - +static inline int request_firmware_nowait_into_buf( + struct module *module, bool uevent, + const char *name, struct device *device, gfp_t gfp, void *context, + void (*cont)(const struct firmware *fw, void *context), + phys_addr_t dest_addr, size_t dest_size, + void * (*map_fw_mem)(phys_addr_t phys, size_t size, void *data), + void (*unmap_fw_mem)(void *virt, size_t size, void *data), void *data) +{ + return -EINVAL; +} static inline void release_firmware(const struct firmware *fw) { } diff -ruw linux-4.4.115/include/linux/freezer.h linux-4.4.115-fbx/include/linux/freezer.h --- linux-4.4.115/include/linux/freezer.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/linux/freezer.h 2019-01-22 16:16:28.227289185 +0100 @@ -231,7 +231,7 @@ * call this with locks held. */ static inline int freezable_schedule_hrtimeout_range(ktime_t *expires, - unsigned long delta, const enum hrtimer_mode mode) + u64 delta, const enum hrtimer_mode mode) { int __retval; freezer_do_not_count(); diff -ruw linux-4.4.115/include/linux/fs.h linux-4.4.115-fbx/include/linux/fs.h --- linux-4.4.115/include/linux/fs.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/linux/fs.h 2019-10-29 09:26:25.433220695 +0100 @@ -52,6 +52,8 @@ struct seq_file; struct workqueue_struct; struct iov_iter; +struct fscrypt_info; +struct fscrypt_operations; extern void __init inode_init(void); extern void __init inode_init_early(void); @@ -202,8 +204,15 @@ #define WRITE_SYNC (WRITE | REQ_SYNC | REQ_NOIDLE) #define WRITE_ODIRECT (WRITE | REQ_SYNC) #define WRITE_FLUSH (WRITE | REQ_SYNC | REQ_NOIDLE | REQ_FLUSH) +#define WRITE_FLUSH_BARRIER (WRITE | REQ_SYNC | REQ_NOIDLE | REQ_FLUSH | \ + REQ_BARRIER) #define WRITE_FUA (WRITE | REQ_SYNC | REQ_NOIDLE | REQ_FUA) #define WRITE_FLUSH_FUA (WRITE | REQ_SYNC | REQ_NOIDLE | REQ_FLUSH | REQ_FUA) +#define WRITE_POST_FLUSH_BARRIER (WRITE | REQ_SYNC | REQ_NOIDLE | \ + REQ_POST_FLUSH_BARRIER | REQ_BARRIER) +#define WRITE_ORDERED_FLUSH_BARRIER (WRITE | REQ_SYNC | REQ_NOIDLE | \ + REQ_FLUSH | REQ_POST_FLUSH_BARRIER | \ + REQ_BARRIER) /* * Attribute flags. These should be or-ed together to figure out what @@ -398,6 +407,8 @@ */ int (*migratepage) (struct address_space *, struct page *, struct page *, enum migrate_mode); + bool (*isolate_page)(struct page *, isolate_mode_t); + void (*putback_page)(struct page *); int (*launder_page) (struct page *); int (*is_partially_uptodate) (struct page *, unsigned long, unsigned long); @@ -470,6 +481,7 @@ int bd_invalidated; struct gendisk * bd_disk; struct request_queue * bd_queue; + struct backing_dev_info *bd_bdi; struct list_head bd_list; /* * Private data. You must have bd_claim'ed the block_device @@ -677,6 +689,9 @@ struct hlist_head i_fsnotify_marks; #endif +#if IS_ENABLED(CONFIG_FS_ENCRYPTION) + struct fscrypt_info *i_crypt_info; +#endif void *i_private; /* fs or device private pointer */ }; @@ -903,6 +918,10 @@ struct list_head f_tfile_llink; #endif /* #ifdef CONFIG_EPOLL */ struct address_space *f_mapping; + +#ifdef CONFIG_FILE_TABLE_DEBUG + struct hlist_node f_hash; +#endif /* #ifdef CONFIG_FILE_TABLE_DEBUG */ } __attribute__((aligned(4))); /* lest something weird decides that 2 is OK */ struct file_handle { @@ -1337,6 +1356,8 @@ #endif const struct xattr_handler **s_xattr; + const struct fscrypt_operations *s_cop; + struct hlist_bl_head s_anon; /* anonymous dentries for (nfs) exporting */ struct list_head s_mounts; /* list of mounts; _not_ for fs use */ struct block_device *s_bdev; @@ -1544,13 +1565,21 @@ * VFS helper functions.. */ extern int vfs_create(struct inode *, struct dentry *, umode_t, bool); +extern int vfs_create2(struct vfsmount *, struct inode *, struct dentry *, umode_t, bool); extern int vfs_mkdir(struct inode *, struct dentry *, umode_t); +extern int vfs_mkdir2(struct vfsmount *, struct inode *, struct dentry *, umode_t); extern int vfs_mknod(struct inode *, struct dentry *, umode_t, dev_t); +extern int vfs_mknod2(struct vfsmount *, struct inode *, struct dentry *, umode_t, dev_t); extern int vfs_symlink(struct inode *, struct dentry *, const char *); +extern int vfs_symlink2(struct vfsmount *, struct inode *, struct dentry *, const char *); extern int vfs_link(struct dentry *, struct inode *, struct dentry *, struct inode **); +extern int vfs_link2(struct vfsmount *, struct dentry *, struct inode *, struct dentry *, struct inode **); extern int vfs_rmdir(struct inode *, struct dentry *); +extern int vfs_rmdir2(struct vfsmount *, struct inode *, struct dentry *); extern int vfs_unlink(struct inode *, struct dentry *, struct inode **); +extern int vfs_unlink2(struct vfsmount *, struct inode *, struct dentry *, struct inode **); extern int vfs_rename(struct inode *, struct dentry *, struct inode *, struct dentry *, struct inode **, unsigned int); +extern int vfs_rename2(struct vfsmount *, struct inode *, struct dentry *, struct inode *, struct dentry *, struct inode **, unsigned int); extern int vfs_whiteout(struct inode *, struct dentry *); /* @@ -1676,6 +1705,7 @@ struct dentry * (*lookup) (struct inode *,struct dentry *, unsigned int); const char * (*follow_link) (struct dentry *, void **); int (*permission) (struct inode *, int); + int (*permission2) (struct vfsmount *, struct inode *, int); struct posix_acl * (*get_acl)(struct inode *, int); int (*readlink) (struct dentry *, char __user *,int); @@ -1693,6 +1723,7 @@ int (*rename2) (struct inode *, struct dentry *, struct inode *, struct dentry *, unsigned int); int (*setattr) (struct dentry *, struct iattr *); + int (*setattr2) (struct vfsmount *, struct dentry *, struct iattr *); int (*getattr) (struct vfsmount *mnt, struct dentry *, struct kstat *); int (*setxattr) (struct dentry *, const char *,const void *,size_t,int); ssize_t (*getxattr) (struct dentry *, const char *, void *, size_t); @@ -1738,9 +1769,13 @@ int (*unfreeze_fs) (struct super_block *); int (*statfs) (struct dentry *, struct kstatfs *); int (*remount_fs) (struct super_block *, int *, char *); + int (*remount_fs2) (struct vfsmount *, struct super_block *, int *, char *); + void *(*clone_mnt_data) (void *); + void (*copy_mnt_data) (void *, void *); void (*umount_begin) (struct super_block *); int (*show_options)(struct seq_file *, struct dentry *); + int (*show_options2)(struct vfsmount *,struct seq_file *, struct dentry *); int (*show_devname)(struct seq_file *, struct dentry *); int (*show_path)(struct seq_file *, struct dentry *); int (*show_stats)(struct seq_file *, struct dentry *); @@ -1777,6 +1812,7 @@ #else #define S_DAX 0 /* Make all the DAX code disappear */ #endif +#define S_ENCRYPTED 16384 /* Encrypted file (using fs/crypto/) */ /* * Note that nosuid etc flags are inode-specific: setting some file-system @@ -1815,6 +1851,7 @@ #define IS_AUTOMOUNT(inode) ((inode)->i_flags & S_AUTOMOUNT) #define IS_NOSEC(inode) ((inode)->i_flags & S_NOSEC) #define IS_DAX(inode) ((inode)->i_flags & S_DAX) +#define IS_ENCRYPTED(inode) ((inode)->i_flags & S_ENCRYPTED) #define IS_WHITEOUT(inode) (S_ISCHR(inode->i_mode) && \ (inode)->i_rdev == WHITEOUT_DEV) @@ -1972,6 +2009,9 @@ #define FS_RENAME_DOES_D_MOVE 32768 /* FS will handle d_move() during rename() internally. */ struct dentry *(*mount) (struct file_system_type *, int, const char *, void *); + struct dentry *(*mount2) (struct vfsmount *, struct file_system_type *, int, + const char *, void *); + void *(*alloc_mnt_data) (void); void (*kill_sb) (struct super_block *); struct module *owner; struct file_system_type * next; @@ -2251,6 +2291,8 @@ extern long vfs_truncate(struct path *, loff_t); extern int do_truncate(struct dentry *, loff_t start, unsigned int time_attrs, struct file *filp); +extern int do_truncate2(struct vfsmount *, struct dentry *, loff_t start, + unsigned int time_attrs, struct file *filp); extern int vfs_fallocate(struct file *file, int mode, loff_t offset, loff_t len); extern long do_sys_open(int dfd, const char __user *filename, int flags, @@ -2292,6 +2334,7 @@ #ifdef CONFIG_BLOCK extern int register_blkdev(unsigned int, const char *); extern void unregister_blkdev(unsigned int, const char *); +extern void bdev_unhash_inode(dev_t dev); extern struct block_device *bdget(dev_t); extern struct block_device *bdgrab(struct block_device *bdev); extern void bd_set_size(struct block_device *, loff_t size); @@ -2475,8 +2518,11 @@ extern sector_t bmap(struct inode *, sector_t); #endif extern int notify_change(struct dentry *, struct iattr *, struct inode **); +extern int notify_change2(struct vfsmount *, struct dentry *, struct iattr *, struct inode **); extern int inode_permission(struct inode *, int); +extern int inode_permission2(struct vfsmount *, struct inode *, int); extern int __inode_permission(struct inode *, int); +extern int __inode_permission2(struct vfsmount *, struct inode *, int); extern int generic_permission(struct inode *, int); extern int __check_sticky(struct inode *dir, struct inode *inode); @@ -2768,6 +2814,8 @@ wake_up_bit(&inode->i_state, __I_DIO_WAKEUP); } +struct inode *dio_bio_get_inode(struct bio *bio); + extern void inode_set_flags(struct inode *inode, unsigned int flags, unsigned int mask); diff -ruw linux-4.4.115/include/linux/fsnotify.h linux-4.4.115-fbx/include/linux/fsnotify.h --- linux-4.4.115/include/linux/fsnotify.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/linux/fsnotify.h 2019-01-22 16:16:28.231289221 +0100 @@ -230,12 +230,19 @@ static inline void fsnotify_open(struct file *file) { struct path *path = &file->f_path; + struct path lower_path; struct inode *inode = file_inode(file); __u32 mask = FS_OPEN; if (S_ISDIR(inode->i_mode)) mask |= FS_ISDIR; + if (path->dentry->d_op && path->dentry->d_op->d_canonical_path) { + path->dentry->d_op->d_canonical_path(path, &lower_path); + fsnotify_parent(&lower_path, NULL, mask); + fsnotify(lower_path.dentry->d_inode, mask, &lower_path, FSNOTIFY_EVENT_PATH, NULL, 0); + path_put(&lower_path); + } fsnotify_parent(path, NULL, mask); fsnotify(inode, mask, path, FSNOTIFY_EVENT_PATH, NULL, 0); } diff -ruw linux-4.4.115/include/linux/ftrace.h linux-4.4.115-fbx/include/linux/ftrace.h --- linux-4.4.115/include/linux/ftrace.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/linux/ftrace.h 2019-01-22 16:16:28.231289221 +0100 @@ -702,7 +702,8 @@ static inline void time_hardirqs_off(unsigned long a0, unsigned long a1) { } #endif -#ifdef CONFIG_PREEMPT_TRACER +#if defined(CONFIG_PREEMPT_TRACER) || \ + (defined(CONFIG_DEBUG_PREEMPT) && defined(CONFIG_PREEMPTIRQ_EVENTS)) extern void trace_preempt_on(unsigned long a0, unsigned long a1); extern void trace_preempt_off(unsigned long a0, unsigned long a1); #else @@ -780,16 +781,6 @@ */ #define __notrace_funcgraph notrace -/* - * We want to which function is an entrypoint of a hardirq. - * That will help us to put a signal on output. - */ -#define __irq_entry __attribute__((__section__(".irqentry.text"))) - -/* Limits of hardirq entrypoints */ -extern char __irqentry_text_start[]; -extern char __irqentry_text_end[]; - #define FTRACE_NOTRACE_DEPTH 65536 #define FTRACE_RETFUNC_DEPTH 50 #define FTRACE_RETSTACK_ALLOC_SIZE 32 @@ -826,7 +817,6 @@ #else /* !CONFIG_FUNCTION_GRAPH_TRACER */ #define __notrace_funcgraph -#define __irq_entry #define INIT_FTRACE_GRAPH static inline void ftrace_graph_init_task(struct task_struct *t) { } diff -ruw linux-4.4.115/include/linux/gfp.h linux-4.4.115-fbx/include/linux/gfp.h --- linux-4.4.115/include/linux/gfp.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/linux/gfp.h 2019-01-22 16:16:28.235289258 +0100 @@ -36,6 +36,7 @@ #define ___GFP_OTHER_NODE 0x800000u #define ___GFP_WRITE 0x1000000u #define ___GFP_KSWAPD_RECLAIM 0x2000000u +#define ___GFP_CMA 0x4000000u /* If the above are modified, __GFP_BITS_SHIFT may need updating */ /* @@ -50,8 +51,9 @@ #define __GFP_DMA32 ((__force gfp_t)___GFP_DMA32) #define __GFP_MOVABLE ((__force gfp_t)___GFP_MOVABLE) /* Page is movable */ #define __GFP_MOVABLE ((__force gfp_t)___GFP_MOVABLE) /* ZONE_MOVABLE allowed */ -#define GFP_ZONEMASK (__GFP_DMA|__GFP_HIGHMEM|__GFP_DMA32|__GFP_MOVABLE) - +#define __GFP_CMA ((__force gfp_t)___GFP_CMA) +#define GFP_ZONEMASK (__GFP_DMA|__GFP_HIGHMEM|__GFP_DMA32|__GFP_MOVABLE| \ + __GFP_CMA) /* * Page mobility and placement hints * @@ -183,7 +185,7 @@ #define __GFP_OTHER_NODE ((__force gfp_t)___GFP_OTHER_NODE) /* Room for N __GFP_FOO bits */ -#define __GFP_BITS_SHIFT 26 +#define __GFP_BITS_SHIFT 27 #define __GFP_BITS_MASK ((__force gfp_t)((1 << __GFP_BITS_SHIFT) - 1)) /* @@ -264,7 +266,12 @@ return MIGRATE_UNMOVABLE; /* Group based on mobility */ +#ifndef CONFIG_CMA return (gfp_flags & GFP_MOVABLE_MASK) >> GFP_MOVABLE_SHIFT; +#else + return ((gfp_flags & GFP_MOVABLE_MASK) >> GFP_MOVABLE_SHIFT) | + ((gfp_flags & __GFP_CMA) != 0); +#endif } #undef GFP_MOVABLE_MASK #undef GFP_MOVABLE_SHIFT diff -ruw linux-4.4.115/include/linux/hash.h linux-4.4.115-fbx/include/linux/hash.h --- linux-4.4.115/include/linux/hash.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/linux/hash.h 2019-01-22 16:16:28.235289258 +0100 @@ -15,6 +15,7 @@ */ #include +#include #include /* 2^31 + 2^29 - 2^25 + 2^22 - 2^19 - 2^16 + 1 */ @@ -99,4 +100,38 @@ return (u32)val; } +struct fast_hash_ops { + u32 (*hash)(const void *data, u32 len, u32 seed); + u32 (*hash2)(const u32 *data, u32 len, u32 seed); +}; + +/** + * arch_fast_hash - Caclulates a hash over a given buffer that can have + * arbitrary size. This function will eventually use an + * architecture-optimized hashing implementation if + * available, and trades off distribution for speed. + * + * @data: buffer to hash + * @len: length of buffer in bytes + * @seed: start seed + * + * Returns 32bit hash. + */ +extern u32 arch_fast_hash(const void *data, u32 len, u32 seed); + +/** + * arch_fast_hash2 - Caclulates a hash over a given buffer that has a + * size that is of a multiple of 32bit words. This + * function will eventually use an architecture- + * optimized hashing implementation if available, + * and trades off distribution for speed. + * + * @data: buffer to hash (must be 32bit padded) + * @len: number of 32bit words + * @seed: start seed + * + * Returns 32bit hash. + */ +extern u32 arch_fast_hash2(const u32 *data, u32 len, u32 seed); + #endif /* _LINUX_HASH_H */ diff -ruw linux-4.4.115/include/linux/hdmi.h linux-4.4.115-fbx/include/linux/hdmi.h --- linux-4.4.115/include/linux/hdmi.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/linux/hdmi.h 2019-01-22 16:16:28.235289258 +0100 @@ -35,6 +35,7 @@ }; #define HDMI_IEEE_OUI 0x000c03 +#define HDMI_IEEE_OUI_HF 0xc45dd8 #define HDMI_INFOFRAME_HEADER_SIZE 4 #define HDMI_AVI_INFOFRAME_SIZE 13 #define HDMI_SPD_INFOFRAME_SIZE 25 @@ -78,6 +79,8 @@ HDMI_PICTURE_ASPECT_NONE, HDMI_PICTURE_ASPECT_4_3, HDMI_PICTURE_ASPECT_16_9, + HDMI_PICTURE_ASPECT_64_27, + HDMI_PICTURE_ASPECT_256_135, HDMI_PICTURE_ASPECT_RESERVED, }; diff -ruw linux-4.4.115/include/linux/highmem.h linux-4.4.115-fbx/include/linux/highmem.h --- linux-4.4.115/include/linux/highmem.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/linux/highmem.h 2019-01-22 16:16:28.239289294 +0100 @@ -39,6 +39,12 @@ void kmap_flush_unused(void); +#ifdef CONFIG_ARCH_WANT_KMAP_ATOMIC_FLUSH +void kmap_atomic_flush_unused(void); +#else +static inline void kmap_atomic_flush_unused(void) { } +#endif + struct page *kmap_to_page(void *addr); #else /* CONFIG_HIGHMEM */ @@ -80,6 +86,7 @@ #define kmap_atomic_pfn(pfn) kmap_atomic(pfn_to_page(pfn)) #define kmap_flush_unused() do {} while(0) +#define kmap_atomic_flush_unused() do {} while (0) #endif #endif /* CONFIG_HIGHMEM */ @@ -180,9 +187,24 @@ alloc_zeroed_user_highpage_movable(struct vm_area_struct *vma, unsigned long vaddr) { +#ifndef CONFIG_CMA return __alloc_zeroed_user_highpage(__GFP_MOVABLE, vma, vaddr); +#else + return __alloc_zeroed_user_highpage(__GFP_MOVABLE|__GFP_CMA, vma, + vaddr); +#endif } +#ifdef CONFIG_CMA +static inline struct page * +alloc_zeroed_user_highpage_movable_cma(struct vm_area_struct *vma, + unsigned long vaddr) +{ + return __alloc_zeroed_user_highpage(__GFP_MOVABLE|__GFP_CMA, vma, + vaddr); +} +#endif + static inline void clear_highpage(struct page *page) { void *kaddr = kmap_atomic(page); diff -ruw linux-4.4.115/include/linux/hrtimer.h linux-4.4.115-fbx/include/linux/hrtimer.h --- linux-4.4.115/include/linux/hrtimer.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/linux/hrtimer.h 2019-01-22 16:16:28.239289294 +0100 @@ -53,6 +53,7 @@ * * 0x00 inactive * 0x01 enqueued into rbtree + * 0x02 timer is pinned to a cpu * * The callback state is not part of the timer->state because clearing it would * mean touching the timer after the callback, this makes it impossible to free @@ -72,6 +73,8 @@ */ #define HRTIMER_STATE_INACTIVE 0x00 #define HRTIMER_STATE_ENQUEUED 0x01 +#define HRTIMER_PINNED_SHIFT 1 +#define HRTIMER_STATE_PINNED (1 << HRTIMER_PINNED_SHIFT) /** * struct hrtimer - the basic hrtimer structure @@ -88,12 +91,6 @@ * @base: pointer to the timer base (per cpu and per clock) * @state: state information (See bit values above) * @is_rel: Set if the timer was armed relative - * @start_pid: timer statistics field to store the pid of the task which - * started the timer - * @start_site: timer statistics field to store the site where the timer - * was started - * @start_comm: timer statistics field to store the name of the process which - * started the timer * * The hrtimer structure must be initialized by hrtimer_init() */ @@ -104,11 +101,6 @@ struct hrtimer_clock_base *base; u8 state; u8 is_rel; -#ifdef CONFIG_TIMER_STATS - int start_pid; - void *start_site; - char start_comm[16]; -#endif }; /** @@ -220,7 +212,7 @@ timer->node.expires = ktime_add_safe(time, delta); } -static inline void hrtimer_set_expires_range_ns(struct hrtimer *timer, ktime_t time, unsigned long delta) +static inline void hrtimer_set_expires_range_ns(struct hrtimer *timer, ktime_t time, u64 delta) { timer->_softexpires = time; timer->node.expires = ktime_add_safe(time, ns_to_ktime(delta)); @@ -357,6 +349,9 @@ /* Exported timer functions: */ +/* To be used from cpusets, only */ +extern void hrtimer_quiesce_cpu(void *cpup); + /* Initialize timers: */ extern void hrtimer_init(struct hrtimer *timer, clockid_t which_clock, enum hrtimer_mode mode); @@ -378,7 +373,7 @@ /* Basic timer operations: */ extern void hrtimer_start_range_ns(struct hrtimer *timer, ktime_t tim, - unsigned long range_ns, const enum hrtimer_mode mode); + u64 range_ns, const enum hrtimer_mode mode); /** * hrtimer_start - (re)start an hrtimer on the current CPU @@ -399,7 +394,7 @@ static inline void hrtimer_start_expires(struct hrtimer *timer, enum hrtimer_mode mode) { - unsigned long delta; + u64 delta; ktime_t soft, hard; soft = hrtimer_get_softexpires(timer); hard = hrtimer_get_expires(timer); @@ -477,10 +472,12 @@ extern void hrtimer_init_sleeper(struct hrtimer_sleeper *sl, struct task_struct *tsk); -extern int schedule_hrtimeout_range(ktime_t *expires, unsigned long delta, +extern int schedule_hrtimeout_range(ktime_t *expires, u64 delta, const enum hrtimer_mode mode); extern int schedule_hrtimeout_range_clock(ktime_t *expires, - unsigned long delta, const enum hrtimer_mode mode, int clock); + u64 delta, + const enum hrtimer_mode mode, + int clock); extern int schedule_hrtimeout(ktime_t *expires, const enum hrtimer_mode mode); /* Soft interrupt function to run the hrtimer queues: */ diff -ruw linux-4.4.115/include/linux/hugetlb.h linux-4.4.115-fbx/include/linux/hugetlb.h --- linux-4.4.115/include/linux/hugetlb.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/linux/hugetlb.h 2019-10-29 09:26:25.437220734 +0100 @@ -96,9 +96,7 @@ struct address_space *mapping, pgoff_t idx, unsigned long address); -#ifdef CONFIG_ARCH_WANT_HUGE_PMD_SHARE pte_t *huge_pmd_share(struct mm_struct *mm, unsigned long addr, pud_t *pud); -#endif extern int hugepages_treat_as_movable; extern int sysctl_hugetlb_shm_group; diff -ruw linux-4.4.115/include/linux/ieee80211.h linux-4.4.115-fbx/include/linux/ieee80211.h --- linux-4.4.115/include/linux/ieee80211.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/linux/ieee80211.h 2019-01-22 16:16:28.247289366 +0100 @@ -1535,6 +1535,9 @@ #define WLAN_AUTH_SHARED_KEY 1 #define WLAN_AUTH_FT 2 #define WLAN_AUTH_SAE 3 +#define WLAN_AUTH_FILS_SK 4 +#define WLAN_AUTH_FILS_SK_PFS 5 +#define WLAN_AUTH_FILS_PK 6 #define WLAN_AUTH_LEAP 128 #define WLAN_AUTH_CHALLENGE_LEN 128 @@ -1674,6 +1677,9 @@ WLAN_STATUS_REJECT_DSE_BAND = 96, WLAN_STATUS_DENIED_WITH_SUGGESTED_BAND_AND_CHANNEL = 99, WLAN_STATUS_DENIED_DUE_TO_SPECTRUM_MANAGEMENT = 103, + /* 802.11ai */ + WLAN_STATUS_FILS_AUTHENTICATION_FAILURE = 108, + WLAN_STATUS_UNKNOWN_AUTHENTICATION_SERVER = 109, }; @@ -2032,6 +2038,15 @@ #define IEEE80211_GCMP_MIC_LEN 16 #define IEEE80211_GCMP_PN_LEN 6 +#define FILS_NONCE_LEN 16 +#define FILS_MAX_KEK_LEN 64 + +#define FILS_ERP_MAX_USERNAME_LEN 16 +#define FILS_ERP_MAX_REALM_LEN 253 +#define FILS_ERP_MAX_RRK_LEN 64 + +#define PMK_MAX_LEN 48 + /* Public action codes */ enum ieee80211_pub_actioncode { WLAN_PUB_ACTION_EXT_CHANSW_ANN = 4, @@ -2245,31 +2260,37 @@ }; +#define SUITE(oui, id) (((oui) << 8) | (id)) + /* cipher suite selectors */ -#define WLAN_CIPHER_SUITE_USE_GROUP 0x000FAC00 -#define WLAN_CIPHER_SUITE_WEP40 0x000FAC01 -#define WLAN_CIPHER_SUITE_TKIP 0x000FAC02 -/* reserved: 0x000FAC03 */ -#define WLAN_CIPHER_SUITE_CCMP 0x000FAC04 -#define WLAN_CIPHER_SUITE_WEP104 0x000FAC05 -#define WLAN_CIPHER_SUITE_AES_CMAC 0x000FAC06 -#define WLAN_CIPHER_SUITE_GCMP 0x000FAC08 -#define WLAN_CIPHER_SUITE_GCMP_256 0x000FAC09 -#define WLAN_CIPHER_SUITE_CCMP_256 0x000FAC0A -#define WLAN_CIPHER_SUITE_BIP_GMAC_128 0x000FAC0B -#define WLAN_CIPHER_SUITE_BIP_GMAC_256 0x000FAC0C -#define WLAN_CIPHER_SUITE_BIP_CMAC_256 0x000FAC0D +#define WLAN_CIPHER_SUITE_USE_GROUP SUITE(0x000FAC, 0) +#define WLAN_CIPHER_SUITE_WEP40 SUITE(0x000FAC, 1) +#define WLAN_CIPHER_SUITE_TKIP SUITE(0x000FAC, 2) +/* reserved: SUITE(0x000FAC, 3) */ +#define WLAN_CIPHER_SUITE_CCMP SUITE(0x000FAC, 4) +#define WLAN_CIPHER_SUITE_WEP104 SUITE(0x000FAC, 5) +#define WLAN_CIPHER_SUITE_AES_CMAC SUITE(0x000FAC, 6) +#define WLAN_CIPHER_SUITE_GCMP SUITE(0x000FAC, 8) +#define WLAN_CIPHER_SUITE_GCMP_256 SUITE(0x000FAC, 9) +#define WLAN_CIPHER_SUITE_CCMP_256 SUITE(0x000FAC, 10) +#define WLAN_CIPHER_SUITE_BIP_GMAC_128 SUITE(0x000FAC, 11) +#define WLAN_CIPHER_SUITE_BIP_GMAC_256 SUITE(0x000FAC, 12) +#define WLAN_CIPHER_SUITE_BIP_CMAC_256 SUITE(0x000FAC, 13) -#define WLAN_CIPHER_SUITE_SMS4 0x00147201 +#define WLAN_CIPHER_SUITE_SMS4 SUITE(0x001472, 1) /* AKM suite selectors */ -#define WLAN_AKM_SUITE_8021X 0x000FAC01 -#define WLAN_AKM_SUITE_PSK 0x000FAC02 -#define WLAN_AKM_SUITE_8021X_SHA256 0x000FAC05 -#define WLAN_AKM_SUITE_PSK_SHA256 0x000FAC06 -#define WLAN_AKM_SUITE_TDLS 0x000FAC07 -#define WLAN_AKM_SUITE_SAE 0x000FAC08 -#define WLAN_AKM_SUITE_FT_OVER_SAE 0x000FAC09 +#define WLAN_AKM_SUITE_8021X SUITE(0x000FAC, 1) +#define WLAN_AKM_SUITE_PSK SUITE(0x000FAC, 2) +#define WLAN_AKM_SUITE_8021X_SHA256 SUITE(0x000FAC, 5) +#define WLAN_AKM_SUITE_PSK_SHA256 SUITE(0x000FAC, 6) +#define WLAN_AKM_SUITE_TDLS SUITE(0x000FAC, 7) +#define WLAN_AKM_SUITE_SAE SUITE(0x000FAC, 8) +#define WLAN_AKM_SUITE_FT_OVER_SAE SUITE(0x000FAC, 9) +#define WLAN_AKM_SUITE_FILS_SHA256 SUITE(0x000FAC, 14) +#define WLAN_AKM_SUITE_FILS_SHA384 SUITE(0x000FAC, 15) +#define WLAN_AKM_SUITE_FT_FILS_SHA256 SUITE(0x000FAC, 16) +#define WLAN_AKM_SUITE_FT_FILS_SHA384 SUITE(0x000FAC, 17) #define WLAN_MAX_KEY_LEN 32 diff -ruw linux-4.4.115/include/linux/if_pppox.h linux-4.4.115-fbx/include/linux/if_pppox.h --- linux-4.4.115/include/linux/if_pppox.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/linux/if_pppox.h 2019-10-29 09:26:25.441220774 +0100 @@ -43,6 +43,25 @@ u32 seq_sent, seq_recv; int ppp_flags; }; + +struct pppolac_opt { + __u32 local; + __u32 remote; + __u32 recv_sequence; + __u32 xmit_sequence; + atomic_t sequencing; + int (*backlog_rcv)(struct sock *sk_udp, struct sk_buff *skb); +}; + +struct pppopns_opt { + __u16 local; + __u16 remote; + __u32 recv_sequence; + __u32 xmit_sequence; + void (*data_ready)(struct sock *sk_raw); + int (*backlog_rcv)(struct sock *sk_raw, struct sk_buff *skb); +}; + #include struct pppox_sock { @@ -53,6 +72,8 @@ union { struct pppoe_opt pppoe; struct pptp_opt pptp; + struct pppolac_opt lac; + struct pppopns_opt pns; } proto; __be16 num; }; diff -ruw linux-4.4.115/include/linux/iio/consumer.h linux-4.4.115-fbx/include/linux/iio/consumer.h --- linux-4.4.115/include/linux/iio/consumer.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/linux/iio/consumer.h 2019-01-22 16:16:28.251289402 +0100 @@ -161,6 +161,16 @@ int iio_write_channel_raw(struct iio_channel *chan, int val); /** + * iio_write_channel_processed() - write to a given channel + * @chan: The channel being queried. + * @val: Value being written. + * + * Note processed writes to iio channels are converted to raw + * values before being written. + */ +int iio_write_channel_processed(struct iio_channel *chan, int val); + +/** * iio_get_channel_type() - get the type of a channel * @channel: The channel being queried. * @type: The type of the channel. diff -ruw linux-4.4.115/include/linux/inetdevice.h linux-4.4.115-fbx/include/linux/inetdevice.h --- linux-4.4.115/include/linux/inetdevice.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/linux/inetdevice.h 2019-01-22 16:16:28.251289402 +0100 @@ -128,6 +128,8 @@ #define IN_DEV_ARP_ANNOUNCE(in_dev) IN_DEV_MAXCONF((in_dev), ARP_ANNOUNCE) #define IN_DEV_ARP_IGNORE(in_dev) IN_DEV_MAXCONF((in_dev), ARP_IGNORE) #define IN_DEV_ARP_NOTIFY(in_dev) IN_DEV_MAXCONF((in_dev), ARP_NOTIFY) +#define IN_DEV_NF_IPV4_DEFRAG_SKIP(in_dev) \ + IN_DEV_ORCONF((in_dev), NF_IPV4_DEFRAG_SKIP) struct in_ifaddr { struct hlist_node hash; diff -ruw linux-4.4.115/include/linux/inet_diag.h linux-4.4.115-fbx/include/linux/inet_diag.h --- linux-4.4.115/include/linux/inet_diag.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/linux/inet_diag.h 2019-01-22 16:16:28.251289402 +0100 @@ -3,6 +3,7 @@ #include +struct net; struct sock; struct inet_hashinfo; struct nlattr; @@ -23,6 +24,10 @@ void (*idiag_get_info)(struct sock *sk, struct inet_diag_msg *r, void *info); + + int (*destroy)(struct sk_buff *in_skb, + const struct inet_diag_req_v2 *req); + __u16 idiag_type; __u16 idiag_info_size; }; @@ -32,7 +37,7 @@ struct sk_buff *skb, const struct inet_diag_req_v2 *req, struct user_namespace *user_ns, u32 pid, u32 seq, u16 nlmsg_flags, - const struct nlmsghdr *unlh); + const struct nlmsghdr *unlh, bool net_admin); void inet_diag_dump_icsk(struct inet_hashinfo *h, struct sk_buff *skb, struct netlink_callback *cb, const struct inet_diag_req_v2 *r, @@ -41,6 +46,10 @@ struct sk_buff *in_skb, const struct nlmsghdr *nlh, const struct inet_diag_req_v2 *req); +struct sock *inet_diag_find_one_icsk(struct net *net, + struct inet_hashinfo *hashinfo, + const struct inet_diag_req_v2 *req); + int inet_diag_bc_sk(const struct nlattr *_bc, struct sock *sk); extern int inet_diag_register(const struct inet_diag_handler *handler); diff -ruw linux-4.4.115/include/linux/inet_lro.h linux-4.4.115-fbx/include/linux/inet_lro.h --- linux-4.4.115/include/linux/inet_lro.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/linux/inet_lro.h 2019-01-22 16:16:28.251289402 +0100 @@ -81,6 +81,7 @@ #define LRO_F_EXTRACT_VLAN_ID 2 /* Set flag if VLAN IDs are extracted from received packets and eth protocol is still ETH_P_8021Q */ +#define LRO_F_NI 4 /* If not NAPI, Pass packets to stack via NI */ /* * Set for generated SKBs that are not added to @@ -122,6 +123,50 @@ }; /* + * Large Receive Offload (LRO) information provided by the driver + * + * Fields must be set by driver when using the lro_receive_skb_ext() + */ +struct net_lro_info { + /* bitmask indicating the supported fields */ + unsigned long valid_fields; + /* + * Driver has checked the LRO eligibilty of the skb + */ + #define LRO_ELIGIBILITY_CHECKED (1 << 0) + /* + * Driver has provided the TCP payload checksum + */ + #define LRO_TCP_DATA_CSUM (1 << 1) + /* + * Driver has extracted the TCP window from the skb + * The value is in network format + */ + #define LRO_TCP_WIN (1 << 2) + /* + * Driver has extracted the TCP sequence number from skb + * The value is in network format + */ + #define LRO_TCP_SEQ_NUM (1 << 3) + /* + * Driver has extracted the TCP ack number from the skb + * The value is in network format + */ + #define LRO_TCP_ACK_NUM (1 << 4) + /* + * Driver has provided the LRO descriptor + */ + #define LRO_DESC (1 << 5) + + bool lro_eligible; + __wsum tcp_data_csum; + __be16 tcp_win; + __be32 tcp_seq_num; + __be32 tcp_ack_num; + struct net_lro_desc *lro_desc; +}; + +/* * Processes a SKB * * @lro_mgr: LRO manager to use @@ -133,10 +178,54 @@ void lro_receive_skb(struct net_lro_mgr *lro_mgr, struct sk_buff *skb, void *priv); + +/* + * Processes an SKB + * + * This API provides means to pass any LRO information that has already + * been extracted by the driver + * + * @lro_mgr: LRO manager to use + * @skb: SKB to aggregate + * @priv: Private data that may be used by driver functions + * (for example get_tcp_ip_hdr) + * @lro_info: LRO information extracted by the driver + */ + +void lro_receive_skb_ext(struct net_lro_mgr *lro_mgr, + struct sk_buff *skb, + void *priv, + struct net_lro_info *lro_info); + +/* + * Processes a fragment list + * + * This functions aggregate fragments and generate SKBs do pass + * the packets to the stack. + * + * @lro_mgr: LRO manager to use + * @frags: Fragment to be processed. Must contain entire header in first + * element. + * @len: Length of received data + * @true_size: Actual size of memory the fragment is consuming + * @priv: Private data that may be used by driver functions + * (for example get_tcp_ip_hdr) + */ + +void lro_receive_frags(struct net_lro_mgr *lro_mgr, + struct skb_frag_struct *frags, + int len, int true_size, void *priv, __wsum sum); + /* * Forward all aggregated SKBs held by lro_mgr to network stack */ void lro_flush_all(struct net_lro_mgr *lro_mgr); +void lro_flush_pkt(struct net_lro_mgr *lro_mgr, + struct iphdr *iph, struct tcphdr *tcph); + +void lro_flush_desc(struct net_lro_mgr *lro_mgr, + struct net_lro_desc *lro_desc); + #endif diff -ruw linux-4.4.115/include/linux/init.h linux-4.4.115-fbx/include/linux/init.h --- linux-4.4.115/include/linux/init.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/linux/init.h 2019-10-29 09:26:25.441220774 +0100 @@ -142,6 +142,10 @@ void __init load_default_modules(void); int __init init_rootfs(void); +#ifdef CONFIG_DEBUG_RODATA +void mark_rodata_ro(void); +#endif + extern void (*late_time_init)(void); extern bool initcall_debug; diff -ruw linux-4.4.115/include/linux/init_task.h linux-4.4.115-fbx/include/linux/init_task.h --- linux-4.4.115/include/linux/init_task.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/linux/init_task.h 2019-01-22 16:16:28.251289402 +0100 @@ -15,6 +15,8 @@ #include #include +#include + #ifdef CONFIG_SMP # define INIT_PUSHABLE_TASKS(tsk) \ .pushable_tasks = PLIST_NODE_INIT(tsk.pushable_tasks, MAX_PRIO), @@ -183,16 +185,24 @@ # define INIT_KASAN(tsk) #endif +#ifdef CONFIG_THREAD_INFO_IN_TASK +# define INIT_TASK_TI(tsk) .thread_info = INIT_THREAD_INFO(tsk), +#else +# define INIT_TASK_TI(tsk) +#endif + /* * INIT_TASK is used to set up the first task table, touch at * your own risk!. Base=0, limit=0x1fffff (=2MB) */ #define INIT_TASK(tsk) \ { \ + INIT_TASK_TI(tsk) \ .state = 0, \ - .stack = &init_thread_info, \ + .stack = init_stack, \ .usage = ATOMIC_INIT(2), \ .flags = PF_KTHREAD, \ + .exec_mode = EXEC_MODE_UNLIMITED, \ .prio = MAX_PRIO-20, \ .static_prio = MAX_PRIO-20, \ .normal_prio = MAX_PRIO-20, \ diff -ruw linux-4.4.115/include/linux/interrupt.h linux-4.4.115-fbx/include/linux/interrupt.h --- linux-4.4.115/include/linux/interrupt.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/linux/interrupt.h 2019-01-22 16:16:28.255289439 +0100 @@ -18,6 +18,7 @@ #include #include #include +#include /* * These correspond to the IORESOURCE_IRQ_* defines in @@ -423,6 +424,12 @@ }; #define SOFTIRQ_STOP_IDLE_MASK (~(1 << RCU_SOFTIRQ)) +/* Softirq's where the handling might be long: */ +#define LONG_SOFTIRQ_MASK ((1 << NET_TX_SOFTIRQ) | \ + (1 << NET_RX_SOFTIRQ) | \ + (1 << BLOCK_SOFTIRQ) | \ + (1 << BLOCK_IOPOLL_SOFTIRQ) | \ + (1 << TASKLET_SOFTIRQ)) /* map softirq index to softirq name. update 'softirq_to_name' in * kernel/softirq.c when adding a new softirq. @@ -458,6 +465,7 @@ extern void raise_softirq(unsigned int nr); DECLARE_PER_CPU(struct task_struct *, ksoftirqd); +DECLARE_PER_CPU(__u32, active_softirqs); static inline struct task_struct *this_cpu_ksoftirqd(void) { @@ -672,4 +680,11 @@ extern int arch_probe_nr_irqs(void); extern int arch_early_irq_init(void); +/* + * We want to know which function is an entrypoint of a hardirq or a softirq. + */ +#define __irq_entry __attribute__((__section__(".irqentry.text"))) +#define __softirq_entry \ + __attribute__((__section__(".softirqentry.text"))) + #endif diff -ruw linux-4.4.115/include/linux/iommu.h linux-4.4.115-fbx/include/linux/iommu.h --- linux-4.4.115/include/linux/iommu.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/linux/iommu.h 2019-01-22 16:16:28.255289439 +0100 @@ -23,13 +23,14 @@ #include #include #include -#include #include #define IOMMU_READ (1 << 0) #define IOMMU_WRITE (1 << 1) #define IOMMU_CACHE (1 << 2) /* DMA cache coherency */ #define IOMMU_NOEXEC (1 << 3) +#define IOMMU_PRIV (1 << 4) +#define IOMMU_DEVICE (1 << 5) /* Indicates access to device memory */ struct iommu_ops; struct iommu_group; @@ -39,8 +40,12 @@ struct notifier_block; /* iommu fault flags */ -#define IOMMU_FAULT_READ 0x0 -#define IOMMU_FAULT_WRITE 0x1 +#define IOMMU_FAULT_READ (1 << 0) +#define IOMMU_FAULT_WRITE (1 << 1) +#define IOMMU_FAULT_TRANSLATION (1 << 2) +#define IOMMU_FAULT_PERMISSION (1 << 3) +#define IOMMU_FAULT_EXTERNAL (1 << 4) +#define IOMMU_FAULT_TRANSACTION_STALLED (1 << 5) typedef int (*iommu_fault_handler_t)(struct iommu_domain *, struct device *, unsigned long, int, void *); @@ -51,6 +56,10 @@ bool force_aperture; /* DMA only allowed in mappable range? */ }; +struct iommu_pgtbl_info { + void *pmds; +}; + /* Domain feature flags */ #define __IOMMU_DOMAIN_PAGING (1U << 0) /* Support for iommu_map/unmap */ #define __IOMMU_DOMAIN_DMA_API (1U << 1) /* Domain for use in DMA-API @@ -112,9 +121,28 @@ DOMAIN_ATTR_FSL_PAMU_ENABLE, DOMAIN_ATTR_FSL_PAMUV1, DOMAIN_ATTR_NESTING, /* two stages of translation */ + DOMAIN_ATTR_PT_BASE_ADDR, + DOMAIN_ATTR_SECURE_VMID, + DOMAIN_ATTR_ATOMIC, + DOMAIN_ATTR_CONTEXT_BANK, + DOMAIN_ATTR_TTBR0, + DOMAIN_ATTR_CONTEXTIDR, + DOMAIN_ATTR_PROCID, + DOMAIN_ATTR_DYNAMIC, + DOMAIN_ATTR_NON_FATAL_FAULTS, + DOMAIN_ATTR_S1_BYPASS, + DOMAIN_ATTR_FAST, + DOMAIN_ATTR_PGTBL_INFO, + DOMAIN_ATTR_EARLY_MAP, + DOMAIN_ATTR_PAGE_TABLE_IS_COHERENT, + DOMAIN_ATTR_PAGE_TABLE_FORCE_COHERENT, + DOMAIN_ATTR_ENABLE_TTBR1, + DOMAIN_ATTR_CB_STALL_DISABLE, DOMAIN_ATTR_MAX, }; +extern struct dentry *iommu_debugfs_top; + /** * struct iommu_dm_region - descriptor for a direct mapped memory region * @list: Linked list pointers @@ -142,12 +170,21 @@ * @map_sg: map a scatter-gather list of physically contiguous memory chunks * to an iommu domain * @iova_to_phys: translate iova to physical address + * @iova_to_phys_hard: translate iova to physical address using IOMMU hardware * @add_device: add device to iommu grouping * @remove_device: remove device from iommu grouping * @domain_get_attr: Query domain attributes * @domain_set_attr: Change domain attributes * @of_xlate: add OF master IDs to iommu grouping * @pgsize_bitmap: bitmap of supported page sizes + * @get_pgsize_bitmap: gets a bitmap of supported page sizes for a domain + * This takes precedence over @pgsize_bitmap. + * @trigger_fault: trigger a fault on the device attached to an iommu domain + * @reg_read: read an IOMMU register + * @reg_write: write an IOMMU register + * @tlbi_domain: Invalidate all TLBs covering an iommu domain + * @enable_config_clocks: Enable all config clocks for this domain's IOMMU + * @disable_config_clocks: Disable all config clocks for this domain's IOMMU * @priv: per-instance data private to the iommu driver */ struct iommu_ops { @@ -166,6 +203,8 @@ size_t (*map_sg)(struct iommu_domain *domain, unsigned long iova, struct scatterlist *sg, unsigned int nents, int prot); phys_addr_t (*iova_to_phys)(struct iommu_domain *domain, dma_addr_t iova); + phys_addr_t (*iova_to_phys_hard)(struct iommu_domain *domain, + dma_addr_t iova); int (*add_device)(struct device *dev); void (*remove_device)(struct device *dev); struct iommu_group *(*device_group)(struct device *dev); @@ -186,11 +225,25 @@ int (*domain_set_windows)(struct iommu_domain *domain, u32 w_count); /* Get the numer of window per domain */ u32 (*domain_get_windows)(struct iommu_domain *domain); + int (*dma_supported)(struct iommu_domain *domain, struct device *dev, + u64 mask); + void (*trigger_fault)(struct iommu_domain *domain, unsigned long flags); + unsigned long (*reg_read)(struct iommu_domain *domain, + unsigned long offset); + void (*reg_write)(struct iommu_domain *domain, unsigned long val, + unsigned long offset); + void (*tlbi_domain)(struct iommu_domain *domain); + int (*enable_config_clocks)(struct iommu_domain *domain); + void (*disable_config_clocks)(struct iommu_domain *domain); + uint64_t (*iova_to_pte)(struct iommu_domain *domain, + dma_addr_t iova); #ifdef CONFIG_OF_IOMMU int (*of_xlate)(struct device *dev, struct of_phandle_args *args); #endif + unsigned long (*get_pgsize_bitmap)(struct iommu_domain *domain); + bool (*is_iova_coherent)(struct iommu_domain *domain, dma_addr_t iova); unsigned long pgsize_bitmap; void *priv; }; @@ -212,17 +265,31 @@ struct device *dev); extern void iommu_detach_device(struct iommu_domain *domain, struct device *dev); +extern size_t iommu_pgsize(unsigned long pgsize_bitmap, + unsigned long addr_merge, size_t size); extern struct iommu_domain *iommu_get_domain_for_dev(struct device *dev); extern int iommu_map(struct iommu_domain *domain, unsigned long iova, phys_addr_t paddr, size_t size, int prot); extern size_t iommu_unmap(struct iommu_domain *domain, unsigned long iova, size_t size); +extern int iommu_unmap_range(struct iommu_domain *domain, unsigned int iova, + unsigned int len); extern size_t default_iommu_map_sg(struct iommu_domain *domain, unsigned long iova, struct scatterlist *sg,unsigned int nents, int prot); extern phys_addr_t iommu_iova_to_phys(struct iommu_domain *domain, dma_addr_t iova); +extern phys_addr_t iommu_iova_to_phys_hard(struct iommu_domain *domain, + dma_addr_t iova); +extern bool iommu_is_iova_coherent(struct iommu_domain *domain, + dma_addr_t iova); extern void iommu_set_fault_handler(struct iommu_domain *domain, iommu_fault_handler_t handler, void *token); +extern void iommu_trigger_fault(struct iommu_domain *domain, + unsigned long flags); +extern unsigned long iommu_reg_read(struct iommu_domain *domain, + unsigned long offset); +extern void iommu_reg_write(struct iommu_domain *domain, unsigned long offset, + unsigned long val); extern void iommu_get_dm_regions(struct device *dev, struct list_head *list); extern void iommu_put_dm_regions(struct device *dev, struct list_head *list); @@ -269,6 +336,9 @@ phys_addr_t offset, u64 size, int prot); extern void iommu_domain_window_disable(struct iommu_domain *domain, u32 wnd_nr); + +extern uint64_t iommu_iova_to_pte(struct iommu_domain *domain, + dma_addr_t iova); /** * report_iommu_fault() - report about an IOMMU fault to the IOMMU framework * @domain: the iommu domain where the fault has happened @@ -292,6 +362,11 @@ * Specifically, -ENOSYS is returned if a fault handler isn't installed * (though fault handlers can also return -ENOSYS, in case they want to * elicit the default behavior of the IOMMU drivers). + + * Client fault handler returns -EBUSY to signal to the IOMMU driver + * that the client will take responsibility for any further fault + * handling, including clearing fault status registers or retrying + * the faulting transaction. */ static inline int report_iommu_fault(struct iommu_domain *domain, struct device *dev, unsigned long iova, int flags) @@ -314,14 +389,41 @@ unsigned long iova, struct scatterlist *sg, unsigned int nents, int prot) { - return domain->ops->map_sg(domain, iova, sg, nents, prot); + size_t ret; + + trace_map_sg_start(iova, nents); + ret = domain->ops->map_sg(domain, iova, sg, nents, prot); + trace_map_sg_end(iova, nents); + return ret; } +extern int iommu_dma_supported(struct iommu_domain *domain, struct device *dev, + u64 mask); + /* PCI device grouping function */ extern struct iommu_group *pci_device_group(struct device *dev); /* Generic device grouping function */ extern struct iommu_group *generic_device_group(struct device *dev); +static inline void iommu_tlbiall(struct iommu_domain *domain) +{ + if (domain->ops->tlbi_domain) + domain->ops->tlbi_domain(domain); +} + +static inline int iommu_enable_config_clocks(struct iommu_domain *domain) +{ + if (domain->ops->enable_config_clocks) + return domain->ops->enable_config_clocks(domain); + return 0; +} + +static inline void iommu_disable_config_clocks(struct iommu_domain *domain) +{ + if (domain->ops->disable_config_clocks) + domain->ops->disable_config_clocks(domain); +} + #else /* CONFIG_IOMMU_API */ struct iommu_ops {}; @@ -379,6 +481,12 @@ return -ENODEV; } +static inline int iommu_unmap_range(struct iommu_domain *domain, + unsigned int iova, unsigned int len) +{ + return -ENODEV; +} + static inline size_t iommu_map_sg(struct iommu_domain *domain, unsigned long iova, struct scatterlist *sg, unsigned int nents, int prot) @@ -403,11 +511,39 @@ return 0; } +static inline phys_addr_t iommu_iova_to_phys_hard(struct iommu_domain *domain, + dma_addr_t iova) +{ + return 0; +} + +static inline bool iommu_is_iova_coherent(struct iommu_domain *domain, + dma_addr_t iova) +{ + return 0; +} + static inline void iommu_set_fault_handler(struct iommu_domain *domain, iommu_fault_handler_t handler, void *token) { } +static inline void iommu_trigger_fault(struct iommu_domain *domain, + unsigned long flags) +{ +} + +static inline unsigned long iommu_reg_read(struct iommu_domain *domain, + unsigned long offset) +{ + return 0; +} + +static inline void iommu_reg_write(struct iommu_domain *domain, + unsigned long val, unsigned long offset) +{ +} + static inline void iommu_get_dm_regions(struct device *dev, struct list_head *list) { @@ -532,6 +668,25 @@ { } +static inline int iommu_dma_supported(struct iommu_domain *domain, + struct device *dev, u64 mask) +{ + return -EINVAL; +} + +static inline void iommu_tlbiall(struct iommu_domain *domain) +{ +} + +static inline int iommu_enable_config_clocks(struct iommu_domain *domain) +{ + return 0; +} + +static inline void iommu_disable_config_clocks(struct iommu_domain *domain) +{ +} + #endif /* CONFIG_IOMMU_API */ #endif /* __LINUX_IOMMU_H */ diff -ruw linux-4.4.115/include/linux/ipv6.h linux-4.4.115-fbx/include/linux/ipv6.h --- linux-4.4.115/include/linux/ipv6.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/linux/ipv6.h 2019-01-22 16:16:28.259289475 +0100 @@ -18,6 +18,7 @@ __s32 dad_transmits; __s32 rtr_solicits; __s32 rtr_solicit_interval; + __s32 rtr_solicit_max_interval; __s32 rtr_solicit_delay; __s32 force_mld_version; __s32 mldv1_unsolicited_report_interval; @@ -36,9 +37,11 @@ __s32 accept_ra_rtr_pref; __s32 rtr_probe_interval; #ifdef CONFIG_IPV6_ROUTE_INFO + __s32 accept_ra_rt_info_min_plen; __s32 accept_ra_rt_info_max_plen; #endif #endif + __s32 accept_ra_rt_table; __s32 proxy_ndp; __s32 accept_source_route; __s32 accept_ra_from_local; @@ -60,6 +63,7 @@ struct in6_addr secret; } stable_secret; __s32 use_oif_addrs_only; + __s32 accept_ra_prefix_route; void *sysctl; }; diff -ruw linux-4.4.115/include/linux/irqchip/arm-gic.h linux-4.4.115-fbx/include/linux/irqchip/arm-gic.h --- linux-4.4.115/include/linux/irqchip/arm-gic.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/linux/irqchip/arm-gic.h 2019-01-22 16:16:28.259289475 +0100 @@ -100,6 +100,11 @@ struct device_node; +extern struct irq_chip gic_arch_extn; + +void gic_set_irqchip_flags(unsigned long flags); +void gic_init_bases(unsigned int, int, void __iomem *, void __iomem *, + u32 offset, struct device_node *); void gic_cascade_irq(unsigned int gic_nr, unsigned int irq); int gic_cpu_if_down(unsigned int gic_nr); diff -ruw linux-4.4.115/include/linux/irq.h linux-4.4.115-fbx/include/linux/irq.h --- linux-4.4.115/include/linux/irq.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/linux/irq.h 2019-01-22 16:16:28.259289475 +0100 @@ -73,6 +73,7 @@ * it from the spurious interrupt detection * mechanism and from core side polling. * IRQ_DISABLE_UNLAZY - Disable lazy irq disable + * IRQ_AFFINITY_MANAGED - Affinity is auto-managed by the kernel */ enum { IRQ_TYPE_NONE = 0x00000000, @@ -99,13 +100,14 @@ IRQ_PER_CPU_DEVID = (1 << 17), IRQ_IS_POLLED = (1 << 18), IRQ_DISABLE_UNLAZY = (1 << 19), + IRQ_AFFINITY_MANAGED = (1 << 21), }; #define IRQF_MODIFY_MASK \ (IRQ_TYPE_SENSE_MASK | IRQ_NOPROBE | IRQ_NOREQUEST | \ IRQ_NOAUTOEN | IRQ_MOVE_PCNTXT | IRQ_LEVEL | IRQ_NO_BALANCING | \ IRQ_PER_CPU | IRQ_NESTED_THREAD | IRQ_NOTHREAD | IRQ_PER_CPU_DEVID | \ - IRQ_IS_POLLED | IRQ_DISABLE_UNLAZY) + IRQ_IS_POLLED | IRQ_DISABLE_UNLAZY | IRQ_AFFINITY_MANAGED) #define IRQ_NO_BALANCING_MASK (IRQ_PER_CPU | IRQ_NO_BALANCING) @@ -191,6 +193,7 @@ * IRQD_IRQ_INPROGRESS - In progress state of the interrupt * IRQD_WAKEUP_ARMED - Wakeup mode armed * IRQD_FORWARDED_TO_VCPU - The interrupt is forwarded to a VCPU + * IRQD_AFFINITY_MANAGED - Affinity is auto-managed by the kernel */ enum { IRQD_TRIGGER_MASK = 0xf, @@ -206,6 +209,7 @@ IRQD_IRQ_INPROGRESS = (1 << 18), IRQD_WAKEUP_ARMED = (1 << 19), IRQD_FORWARDED_TO_VCPU = (1 << 20), + IRQD_AFFINITY_MANAGED = (1 << 21), }; #define __irqd_to_state(d) ((d)->common->state_use_accessors) @@ -299,6 +303,11 @@ __irqd_to_state(d) &= ~IRQD_FORWARDED_TO_VCPU; } +static inline bool irqd_affinity_is_managed(struct irq_data *d) +{ + return __irqd_to_state(d) & IRQD_AFFINITY_MANAGED; +} + static inline irq_hw_number_t irqd_to_hwirq(struct irq_data *d) { return d->hwirq; diff -ruw linux-4.4.115/include/linux/kasan.h linux-4.4.115-fbx/include/linux/kasan.h --- linux-4.4.115/include/linux/kasan.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/linux/kasan.h 2019-01-22 16:16:28.263289511 +0100 @@ -1,6 +1,7 @@ #ifndef _LINUX_KASAN_H #define _LINUX_KASAN_H +#include #include struct kmem_cache; @@ -13,7 +14,6 @@ #include #include -#include extern unsigned char kasan_zero_page[PAGE_SIZE]; extern pte_t kasan_zero_pte[PTRS_PER_PTE]; @@ -30,67 +30,102 @@ } /* Enable reporting bugs after kasan_disable_current() */ -static inline void kasan_enable_current(void) -{ - current->kasan_depth++; -} +extern void kasan_enable_current(void); /* Disable reporting bugs for current task */ -static inline void kasan_disable_current(void) -{ - current->kasan_depth--; -} +extern void kasan_disable_current(void); void kasan_unpoison_shadow(const void *address, size_t size); +void kasan_unpoison_task_stack(struct task_struct *task); +void kasan_unpoison_stack_above_sp_to(const void *watermark); + void kasan_alloc_pages(struct page *page, unsigned int order); void kasan_free_pages(struct page *page, unsigned int order); +void kasan_cache_create(struct kmem_cache *cache, size_t *size, + unsigned long *flags); +void kasan_cache_shrink(struct kmem_cache *cache); +void kasan_cache_shutdown(struct kmem_cache *cache); + void kasan_poison_slab(struct page *page); void kasan_unpoison_object_data(struct kmem_cache *cache, void *object); void kasan_poison_object_data(struct kmem_cache *cache, void *object); +void kasan_init_slab_obj(struct kmem_cache *cache, const void *object); -void kasan_kmalloc_large(const void *ptr, size_t size); +void kasan_kmalloc_large(const void *ptr, size_t size, gfp_t flags); void kasan_kfree_large(const void *ptr); -void kasan_kfree(void *ptr); -void kasan_kmalloc(struct kmem_cache *s, const void *object, size_t size); -void kasan_krealloc(const void *object, size_t new_size); - -void kasan_slab_alloc(struct kmem_cache *s, void *object); -void kasan_slab_free(struct kmem_cache *s, void *object); +void kasan_poison_kfree(void *ptr); +void kasan_kmalloc(struct kmem_cache *s, const void *object, size_t size, + gfp_t flags); +void kasan_krealloc(const void *object, size_t new_size, gfp_t flags); + +void kasan_slab_alloc(struct kmem_cache *s, void *object, gfp_t flags); +bool kasan_slab_free(struct kmem_cache *s, void *object); + +struct kasan_cache { + int alloc_meta_offset; + int free_meta_offset; +}; int kasan_module_alloc(void *addr, size_t size); void kasan_free_shadow(const struct vm_struct *vm); +size_t ksize(const void *); +static inline void kasan_unpoison_slab(const void *ptr) { ksize(ptr); } +size_t kasan_metadata_size(struct kmem_cache *cache); + +bool kasan_save_enable_multi_shot(void); +void kasan_restore_multi_shot(bool enabled); + #else /* CONFIG_KASAN */ static inline void kasan_unpoison_shadow(const void *address, size_t size) {} +static inline void kasan_unpoison_task_stack(struct task_struct *task) {} +static inline void kasan_unpoison_stack_above_sp_to(const void *watermark) {} + static inline void kasan_enable_current(void) {} static inline void kasan_disable_current(void) {} static inline void kasan_alloc_pages(struct page *page, unsigned int order) {} static inline void kasan_free_pages(struct page *page, unsigned int order) {} +static inline void kasan_cache_create(struct kmem_cache *cache, + size_t *size, + unsigned long *flags) {} +static inline void kasan_cache_shrink(struct kmem_cache *cache) {} +static inline void kasan_cache_shutdown(struct kmem_cache *cache) {} + static inline void kasan_poison_slab(struct page *page) {} static inline void kasan_unpoison_object_data(struct kmem_cache *cache, void *object) {} static inline void kasan_poison_object_data(struct kmem_cache *cache, void *object) {} +static inline void kasan_init_slab_obj(struct kmem_cache *cache, + const void *object) {} -static inline void kasan_kmalloc_large(void *ptr, size_t size) {} +static inline void kasan_kmalloc_large(void *ptr, size_t size, gfp_t flags) {} static inline void kasan_kfree_large(const void *ptr) {} -static inline void kasan_kfree(void *ptr) {} +static inline void kasan_poison_kfree(void *ptr) {} static inline void kasan_kmalloc(struct kmem_cache *s, const void *object, - size_t size) {} -static inline void kasan_krealloc(const void *object, size_t new_size) {} - -static inline void kasan_slab_alloc(struct kmem_cache *s, void *object) {} -static inline void kasan_slab_free(struct kmem_cache *s, void *object) {} + size_t size, gfp_t flags) {} +static inline void kasan_krealloc(const void *object, size_t new_size, + gfp_t flags) {} + +static inline void kasan_slab_alloc(struct kmem_cache *s, void *object, + gfp_t flags) {} +static inline bool kasan_slab_free(struct kmem_cache *s, void *object) +{ + return false; +} static inline int kasan_module_alloc(void *addr, size_t size) { return 0; } static inline void kasan_free_shadow(const struct vm_struct *vm) {} +static inline void kasan_unpoison_slab(const void *ptr) { } +static inline size_t kasan_metadata_size(struct kmem_cache *cache) { return 0; } + #endif /* CONFIG_KASAN */ #endif /* LINUX_KASAN_H */ diff -ruw linux-4.4.115/include/linux/kbuild.h linux-4.4.115-fbx/include/linux/kbuild.h --- linux-4.4.115/include/linux/kbuild.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/linux/kbuild.h 2019-01-22 16:16:28.263289511 +0100 @@ -2,14 +2,14 @@ #define __LINUX_KBUILD_H #define DEFINE(sym, val) \ - asm volatile("\n->" #sym " %0 " #val : : "i" (val)) + asm volatile("\n.ascii \"->" #sym " %0 " #val "\"" : : "i" (val)) -#define BLANK() asm volatile("\n->" : : ) +#define BLANK() asm volatile("\n.ascii \"->\"" : : ) #define OFFSET(sym, str, mem) \ DEFINE(sym, offsetof(struct str, mem)) #define COMMENT(x) \ - asm volatile("\n->#" x) + asm volatile("\n.ascii \"->#" x "\"") #endif diff -ruw linux-4.4.115/include/linux/kdb.h linux-4.4.115-fbx/include/linux/kdb.h --- linux-4.4.115/include/linux/kdb.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/linux/kdb.h 2019-01-22 16:16:28.267289547 +0100 @@ -177,7 +177,7 @@ static inline int kdb_process_cpu(const struct task_struct *p) { - unsigned int cpu = task_thread_info(p)->cpu; + unsigned int cpu = task_cpu(p); if (cpu > num_possible_cpus()) cpu = 0; return cpu; diff -ruw linux-4.4.115/include/linux/kernel.h linux-4.4.115-fbx/include/linux/kernel.h --- linux-4.4.115/include/linux/kernel.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/linux/kernel.h 2019-01-22 16:16:28.267289547 +0100 @@ -53,6 +53,13 @@ #define ARRAY_SIZE(arr) (sizeof(arr) / sizeof((arr)[0]) + __must_be_array(arr)) +#define u64_to_user_ptr(x) ( \ +{ \ + typecheck(u64, x); \ + (void __user *)(uintptr_t)x; \ +} \ +) + /* * This looks more complex than it should be. But we need to * get the type for the ~ right in round_down (it needs to be diff -ruw linux-4.4.115/include/linux/kobject.h linux-4.4.115-fbx/include/linux/kobject.h --- linux-4.4.115/include/linux/kobject.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/linux/kobject.h 2019-10-29 09:26:25.445220813 +0100 @@ -29,7 +29,7 @@ #include #define UEVENT_HELPER_PATH_LEN 256 -#define UEVENT_NUM_ENVP 32 /* number of env pointers */ +#define UEVENT_NUM_ENVP 64 /* number of env pointers */ #define UEVENT_BUFFER_SIZE 2048 /* buffer for the variables */ #ifdef CONFIG_UEVENT_HELPER diff -ruw linux-4.4.115/include/linux/kref.h linux-4.4.115-fbx/include/linux/kref.h --- linux-4.4.115/include/linux/kref.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/linux/kref.h 2019-01-22 16:16:28.267289547 +0100 @@ -19,6 +19,7 @@ #include #include #include +#include struct kref { atomic_t refcount; @@ -98,6 +99,38 @@ return kref_sub(kref, 1, release); } +/** + * kref_put_spinlock_irqsave - decrement refcount for object. + * @kref: object. + * @release: pointer to the function that will clean up the object when the + * last reference to the object is released. + * This pointer is required, and it is not acceptable to pass kfree + * in as this function. + * @lock: lock to take in release case + * + * Behaves identical to kref_put with one exception. If the reference count + * drops to zero, the lock will be taken atomically wrt dropping the reference + * count. The release function has to call spin_unlock() without _irqrestore. + */ +static inline int kref_put_spinlock_irqsave(struct kref *kref, + void (*release)(struct kref *kref), + spinlock_t *lock) +{ + unsigned long flags; + + WARN_ON(release == NULL); + if (atomic_add_unless(&kref->refcount, -1, 1)) + return 0; + spin_lock_irqsave(lock, flags); + if (atomic_dec_and_test(&kref->refcount)) { + release(kref); + local_irq_restore(flags); + return 1; + } + spin_unlock_irqrestore(lock, flags); + return 0; +} + static inline int kref_put_mutex(struct kref *kref, void (*release)(struct kref *kref), struct mutex *lock) diff -ruw linux-4.4.115/include/linux/ksm.h linux-4.4.115-fbx/include/linux/ksm.h --- linux-4.4.115/include/linux/ksm.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/linux/ksm.h 2019-01-22 16:16:28.267289547 +0100 @@ -43,8 +43,7 @@ static inline void set_page_stable_node(struct page *page, struct stable_node *stable_node) { - page->mapping = (void *)stable_node + - (PAGE_MAPPING_ANON | PAGE_MAPPING_KSM); + page->mapping = (void *)((unsigned long)stable_node | PAGE_MAPPING_KSM); } /* diff -ruw linux-4.4.115/include/linux/kthread.h linux-4.4.115-fbx/include/linux/kthread.h --- linux-4.4.115/include/linux/kthread.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/linux/kthread.h 2019-01-22 16:16:28.267289547 +0100 @@ -75,6 +75,8 @@ struct list_head node; kthread_work_func_t func; struct kthread_worker *worker; + /* Number of canceling calls that are running at the moment. */ + int canceling; }; #define KTHREAD_WORKER_INIT(worker) { \ @@ -129,4 +131,6 @@ void flush_kthread_work(struct kthread_work *work); void flush_kthread_worker(struct kthread_worker *worker); +bool kthread_cancel_work_sync(struct kthread_work *work); + #endif /* _LINUX_KTHREAD_H */ diff -ruw linux-4.4.115/include/linux/leds.h linux-4.4.115-fbx/include/linux/leds.h --- linux-4.4.115/include/linux/leds.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/linux/leds.h 2019-01-22 16:16:28.271289584 +0100 @@ -35,6 +35,7 @@ const char *name; enum led_brightness brightness; enum led_brightness max_brightness; + enum led_brightness usr_brightness_req; int flags; /* Lower 16 bits reflect status */ @@ -48,6 +49,7 @@ #define SET_BRIGHTNESS_ASYNC (1 << 21) #define SET_BRIGHTNESS_SYNC (1 << 22) #define LED_DEV_CAP_FLASH (1 << 23) +#define LED_KEEP_TRIGGER (1 << 24) /* Set LED brightness level */ /* Must not sleep, use a workqueue if needed */ diff -ruw linux-4.4.115/include/linux/libfdt_env.h linux-4.4.115-fbx/include/linux/libfdt_env.h --- linux-4.4.115/include/linux/libfdt_env.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/linux/libfdt_env.h 2019-01-22 16:16:28.271289584 +0100 @@ -1,6 +1,7 @@ #ifndef _LIBFDT_ENV_H #define _LIBFDT_ENV_H +#include #include #include diff -ruw linux-4.4.115/include/linux/lsm_hooks.h linux-4.4.115-fbx/include/linux/lsm_hooks.h --- linux-4.4.115/include/linux/lsm_hooks.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/linux/lsm_hooks.h 2019-01-22 16:16:28.275289620 +0100 @@ -1384,6 +1384,8 @@ size_t *len); int (*inode_create)(struct inode *dir, struct dentry *dentry, umode_t mode); + int (*inode_post_create)(struct inode *dir, struct dentry *dentry, + umode_t mode); int (*inode_link)(struct dentry *old_dentry, struct inode *dir, struct dentry *new_dentry); int (*inode_unlink)(struct inode *dir, struct dentry *dentry); @@ -1440,6 +1442,7 @@ struct fown_struct *fown, int sig); int (*file_receive)(struct file *file); int (*file_open)(struct file *file, const struct cred *cred); + int (*file_close)(struct file *file); int (*task_create)(unsigned long clone_flags); void (*task_free)(struct task_struct *task); @@ -1666,6 +1669,7 @@ struct list_head inode_free_security; struct list_head inode_init_security; struct list_head inode_create; + struct list_head inode_post_create; struct list_head inode_link; struct list_head inode_unlink; struct list_head inode_symlink; @@ -1702,6 +1706,7 @@ struct list_head file_send_sigiotask; struct list_head file_receive; struct list_head file_open; + struct list_head file_close; struct list_head task_create; struct list_head task_free; struct list_head cred_alloc_blank; diff -ruw linux-4.4.115/include/linux/memblock.h linux-4.4.115-fbx/include/linux/memblock.h --- linux-4.4.115/include/linux/memblock.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/linux/memblock.h 2019-01-22 16:16:28.279289656 +0100 @@ -25,6 +25,7 @@ MEMBLOCK_NONE = 0x0, /* No special request */ MEMBLOCK_HOTPLUG = 0x1, /* hotpluggable region */ MEMBLOCK_MIRROR = 0x2, /* mirrored region */ + MEMBLOCK_NOMAP = 0x4, /* don't add to kernel direct mapping */ }; struct memblock_region { @@ -82,7 +83,11 @@ int memblock_mark_hotplug(phys_addr_t base, phys_addr_t size); int memblock_clear_hotplug(phys_addr_t base, phys_addr_t size); int memblock_mark_mirror(phys_addr_t base, phys_addr_t size); +int memblock_mark_nomap(phys_addr_t base, phys_addr_t size); +int memblock_clear_nomap(phys_addr_t base, phys_addr_t size); ulong choose_memblock_flags(void); +unsigned long memblock_region_resize_late_begin(void); +void memblock_region_resize_late_end(unsigned long); /* Low level functions */ int memblock_add_range(struct memblock_type *type, @@ -184,6 +189,11 @@ return m->flags & MEMBLOCK_MIRROR; } +static inline bool memblock_is_nomap(struct memblock_region *m) +{ + return m->flags & MEMBLOCK_NOMAP; +} + #ifdef CONFIG_HAVE_MEMBLOCK_NODE_MAP int memblock_search_pfn_nid(unsigned long pfn, unsigned long *start_pfn, unsigned long *end_pfn); @@ -319,7 +329,9 @@ phys_addr_t memblock_end_of_DRAM(void); void memblock_enforce_memory_limit(phys_addr_t memory_limit); int memblock_is_memory(phys_addr_t addr); +int memblock_is_map_memory(phys_addr_t addr); int memblock_is_region_memory(phys_addr_t base, phys_addr_t size); +bool memblock_overlaps_memory(phys_addr_t base, phys_addr_t size); int memblock_is_reserved(phys_addr_t addr); bool memblock_is_region_reserved(phys_addr_t base, phys_addr_t size); @@ -391,6 +403,11 @@ region < (memblock.memblock_type.regions + memblock.memblock_type.cnt); \ region++) +#define for_each_memblock_rev(memblock_type, region) \ + for (region = memblock.memblock_type.regions + \ + memblock.memblock_type.cnt - 1; \ + region >= memblock.memblock_type.regions; \ + region--) #ifdef CONFIG_ARCH_DISCARD_MEMBLOCK #define __init_memblock __meminit diff -ruw linux-4.4.115/include/linux/memory_hotplug.h linux-4.4.115-fbx/include/linux/memory_hotplug.h --- linux-4.4.115/include/linux/memory_hotplug.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/linux/memory_hotplug.h 2019-01-22 16:16:28.279289656 +0100 @@ -89,7 +89,7 @@ unsigned long *valid_start, unsigned long *valid_end); extern void __offline_isolated_pages(unsigned long, unsigned long); -typedef void (*online_page_callback_t)(struct page *page); +typedef int (*online_page_callback_t)(struct page *page); extern int set_online_page_callback(online_page_callback_t callback); extern int restore_online_page_callback(online_page_callback_t callback); diff -ruw linux-4.4.115/include/linux/migrate.h linux-4.4.115-fbx/include/linux/migrate.h --- linux-4.4.115/include/linux/migrate.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/linux/migrate.h 2019-10-29 09:26:25.453220891 +0100 @@ -23,9 +23,13 @@ MR_SYSCALL, /* also applies to cpusets */ MR_MEMPOLICY_MBIND, MR_NUMA_MISPLACED, - MR_CMA + MR_CMA, + MR_TYPES }; +/* In mm/debug.c; also keep sync with include/trace/events/migrate.h */ +extern char *migrate_reason_names[MR_TYPES]; + #ifdef CONFIG_MIGRATION extern void putback_movable_pages(struct list_head *l); @@ -33,6 +37,8 @@ struct page *, struct page *, enum migrate_mode); extern int migrate_pages(struct list_head *l, new_page_t new, free_page_t free, unsigned long private, enum migrate_mode mode, int reason); +extern bool isolate_movable_page(struct page *page, isolate_mode_t mode); +extern void putback_movable_page(struct page *page); extern int migrate_prep(void); extern int migrate_prep_local(void); @@ -65,6 +71,21 @@ #endif /* CONFIG_MIGRATION */ +#ifdef CONFIG_COMPACTION +extern int PageMovable(struct page *page); +extern void __SetPageMovable(struct page *page, struct address_space *mapping); +extern void __ClearPageMovable(struct page *page); +#else +static inline int PageMovable(struct page *page) { return 0; }; +static inline void __SetPageMovable(struct page *page, + struct address_space *mapping) +{ +} +static inline void __ClearPageMovable(struct page *page) +{ +} +#endif + #ifdef CONFIG_NUMA_BALANCING extern bool pmd_trans_migrating(pmd_t pmd); extern int migrate_misplaced_page(struct page *page, diff -ruw linux-4.4.115/include/linux/mmc/card.h linux-4.4.115-fbx/include/linux/mmc/card.h --- linux-4.4.115/include/linux/mmc/card.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/linux/mmc/card.h 2019-01-22 16:16:28.307289910 +0100 @@ -12,7 +12,11 @@ #include #include +#include #include +#include + +#define MMC_CARD_CMDQ_BLK_SIZE 512 struct mmc_cid { unsigned int manfid; @@ -52,6 +56,7 @@ u8 sec_feature_support; u8 rel_sectors; u8 rel_param; + bool enhanced_rpmb_supported; u8 part_config; u8 cache_ctrl; u8 rst_n_function; @@ -83,11 +88,13 @@ bool hpi; /* HPI support bit */ unsigned int hpi_cmd; /* cmd used as HPI */ bool bkops; /* background support bit */ - bool man_bkops_en; /* manual bkops enable bit */ + u8 bkops_en; /* bkops enable */ unsigned int data_sector_size; /* 512 bytes or 4KB */ unsigned int data_tag_unit_size; /* DATA TAG UNIT size */ unsigned int boot_ro_lock; /* ro lock support */ bool boot_ro_lockable; + u8 raw_ext_csd_cmdq; /* 15 */ + u8 raw_ext_csd_cache_ctrl; /* 33 */ bool ffu_capable; /* Firmware upgrade support */ #define MMC_FIRMWARE_LEN 8 u8 fwrev[MMC_FIRMWARE_LEN]; /* FW version */ @@ -95,6 +102,10 @@ u8 raw_partition_support; /* 160 */ u8 raw_rpmb_size_mult; /* 168 */ u8 raw_erased_mem_count; /* 181 */ + u8 raw_ext_csd_bus_width; /* 183 */ + u8 strobe_support; /* 184 */ +#define MMC_STROBE_SUPPORT (1 << 0) + u8 raw_ext_csd_hs_timing; /* 185 */ u8 raw_ext_csd_structure; /* 194 */ u8 raw_card_type; /* 196 */ u8 raw_driver_strength; /* 197 */ @@ -116,9 +127,19 @@ u8 raw_pwr_cl_ddr_52_195; /* 238 */ u8 raw_pwr_cl_ddr_52_360; /* 239 */ u8 raw_pwr_cl_ddr_200_360; /* 253 */ + u8 cache_flush_policy; /* 240 */ +#define MMC_BKOPS_URGENCY_MASK 0x3 u8 raw_bkops_status; /* 246 */ u8 raw_sectors[4]; /* 212 - 4 bytes */ + u8 pre_eol_info; /* 267 */ + u8 device_life_time_est_typ_a; /* 268 */ + u8 device_life_time_est_typ_b; /* 269 */ + u8 cmdq_depth; /* 307 */ + u8 cmdq_support; /* 308 */ + u8 barrier_support; /* 486 */ + u8 barrier_en; + u8 fw_version; /* 254 */ unsigned int feature_support; #define MMC_DISCARD_FEATURE BIT(0) /* CMD38 feature */ }; @@ -189,7 +210,8 @@ wide_bus:1, high_power:1, high_speed:1, - disable_cd:1; + disable_cd:1, + async_intr_sup:1; }; struct sdio_cis { @@ -218,6 +240,28 @@ MMC_BLK_NEW_REQUEST, }; +enum mmc_packed_stop_reasons { + EXCEEDS_SEGMENTS = 0, + EXCEEDS_SECTORS, + WRONG_DATA_DIR, + FLUSH_OR_DISCARD, + EMPTY_QUEUE, + REL_WRITE, + THRESHOLD, + LARGE_SEC_ALIGN, + RANDOM, + FUA, + MAX_REASONS, +}; + +struct mmc_wr_pack_stats { + u32 *packing_events; + u32 pack_stop_reason[MAX_REASONS]; + spinlock_t lock; + bool enabled; + bool print_in_read; +}; + /* The number of MMC physical partitions. These consist of: * boot partitions (2), general purpose partitions (4) and * RPMB partition (1) in MMC v4.4. @@ -242,6 +286,62 @@ #define MMC_BLK_DATA_AREA_RPMB (1<<3) }; +enum { + MMC_BKOPS_NO_OP, + MMC_BKOPS_NOT_CRITICAL, + MMC_BKOPS_PERF_IMPACT, + MMC_BKOPS_CRITICAL, + MMC_BKOPS_NUM_SEVERITY_LEVELS, +}; + +/** + * struct mmc_bkops_stats - BKOPS statistics + * @lock: spinlock used for synchronizing the debugfs and the runtime accesses + * to this structure. No need to call with spin_lock_irq api + * @manual_start: number of times START_BKOPS was sent to the device + * @hpi: number of times HPI was sent to the device + * @auto_start: number of times AUTO_EN was set to 1 + * @auto_stop: number of times AUTO_EN was set to 0 + * @level: number of times the device reported the need for each level of + * bkops handling + * @enabled: control over whether statistics should be gathered + * + * This structure is used to collect statistics regarding the bkops + * configuration and use-patterns. It is collected during runtime and can be + * shown to the user via a debugfs entry. + */ +struct mmc_bkops_stats { + spinlock_t lock; + unsigned int manual_start; + unsigned int hpi; + unsigned int auto_start; + unsigned int auto_stop; + unsigned int level[MMC_BKOPS_NUM_SEVERITY_LEVELS]; + bool enabled; +}; + +/** + * struct mmc_bkops_info - BKOPS data + * @stats: statistic information regarding bkops + * @needs_check: indication whether need to check with the device + * whether it requires handling of BKOPS (CMD8) + * @needs_manual: indication whether have to send START_BKOPS + * to the device + */ +struct mmc_bkops_info { + struct mmc_bkops_stats stats; + bool needs_check; + bool needs_bkops; + u32 retry_counter; +}; + +enum mmc_pon_type { + MMC_LONG_PON = 1, + MMC_SHRT_PON, +}; + +#define MMC_QUIRK_CMDQ_DELAY_BEFORE_DCMD 6 /* microseconds */ + /* * MMC device */ @@ -249,6 +349,10 @@ struct mmc_host *host; /* the host this device belongs to */ struct device dev; /* the device */ u32 ocr; /* the current OCR setting */ + unsigned long clk_scaling_lowest; /* lowest scaleable + * frequency */ + unsigned long clk_scaling_highest; /* highest scaleable + * frequency */ unsigned int rca; /* relative card address of device */ unsigned int type; /* card type */ #define MMC_TYPE_MMC 0 /* MMC card */ @@ -261,14 +365,17 @@ #define MMC_STATE_BLOCKADDR (1<<2) /* card uses block-addressing */ #define MMC_CARD_SDXC (1<<3) /* card is SDXC */ #define MMC_CARD_REMOVED (1<<4) /* card has been removed */ -#define MMC_STATE_DOING_BKOPS (1<<5) /* card is doing BKOPS */ +#define MMC_STATE_DOING_BKOPS (1<<5) /* card is doing manual BKOPS */ #define MMC_STATE_SUSPENDED (1<<6) /* card is suspended */ +#define MMC_STATE_CMDQ (1<<12) /* card is in cmd queue mode */ +#define MMC_STATE_AUTO_BKOPS (1<<13) /* card is doing auto BKOPS */ unsigned int quirks; /* card quirks */ #define MMC_QUIRK_LENIENT_FN0 (1<<0) /* allow SDIO FN0 writes outside of the VS CCCR range */ #define MMC_QUIRK_BLKSZ_FOR_BYTE_MODE (1<<1) /* use func->cur_blksize */ /* for byte mode */ #define MMC_QUIRK_NONSTD_SDIO (1<<2) /* non-standard SDIO card attached */ /* (missing CIA registers) */ +#define MMC_QUIRK_BROKEN_CLK_GATING (1<<3) /* clock gating the sdio bus will make card fail */ #define MMC_QUIRK_NONSTD_FUNC_IF (1<<4) /* SDIO card has nonstd function interfaces */ #define MMC_QUIRK_DISABLE_CD (1<<5) /* disconnect CD/DAT[3] resistor */ #define MMC_QUIRK_INAND_CMD38 (1<<6) /* iNAND devices have broken CMD38 */ @@ -279,7 +386,17 @@ #define MMC_QUIRK_SEC_ERASE_TRIM_BROKEN (1<<10) /* Skip secure for erase/trim */ #define MMC_QUIRK_BROKEN_IRQ_POLLING (1<<11) /* Polling SDIO_CCCR_INTx could create a fake interrupt */ #define MMC_QUIRK_TRIM_BROKEN (1<<12) /* Skip trim */ + /* byte mode */ +#define MMC_QUIRK_INAND_DATA_TIMEOUT (1<<13) /* For incorrect data timeout */ +#define MMC_QUIRK_BROKEN_HPI (1 << 14) /* For devices which gets */ + /* broken due to HPI feature */ +#define MMC_QUIRK_CACHE_DISABLE (1 << 15) /* prevent cache enable */ +#define MMC_QUIRK_QCA6574_SETTINGS (1 << 16) /* QCA6574 card settings*/ +#define MMC_QUIRK_QCA9377_SETTINGS (1 << 17) /* QCA9377 card settings*/ + +/* Make sure CMDQ is empty before queuing DCMD */ +#define MMC_QUIRK_CMDQ_EMPTY_BEFORE_DCMD (1 << 17) unsigned int erase_size; /* erase size in sectors */ unsigned int erase_shift; /* if erase unit is power 2 */ @@ -313,6 +430,15 @@ struct dentry *debugfs_root; struct mmc_part part[MMC_NUM_PHY_PARTITION]; /* physical partitions */ unsigned int nr_parts; + unsigned int part_curr; + + struct mmc_wr_pack_stats wr_pack_stats; /* packed commands stats*/ + struct notifier_block reboot_notify; + enum mmc_pon_type pon_type; + bool cmdq_init; + struct mmc_bkops_info bkops; + bool err_in_sdr104; + bool sdr104_blocked; }; /* @@ -353,19 +479,43 @@ /* SDIO-specfic fields. You can use SDIO_ANY_ID here of course */ u16 cis_vendor, cis_device; + /* MMC-specific field, You can use EXT_CSD_REV_ANY here of course */ + unsigned int ext_csd_rev; + void (*vendor_fixup)(struct mmc_card *card, int data); int data; }; +#define CID_MANFID_SANDISK 0x2 +#define CID_MANFID_TOSHIBA 0x11 +#define CID_MANFID_MICRON 0x13 +#define CID_MANFID_SAMSUNG 0x15 +#define CID_MANFID_KINGSTON 0x70 +#define CID_MANFID_HYNIX 0x90 + #define CID_MANFID_ANY (-1u) #define CID_OEMID_ANY ((unsigned short) -1) #define CID_NAME_ANY (NULL) +#define EXT_CSD_REV_ANY (-1u) #define END_FIXUP { NULL } +/* extended CSD mapping to mmc version */ +enum mmc_version_ext_csd_rev { + MMC_V4_0, + MMC_V4_1, + MMC_V4_2, + MMC_V4_41 = 5, + MMC_V4_5, + MMC_V4_51 = MMC_V4_5, + MMC_V5_0, + MMC_V5_01 = MMC_V5_0, + MMC_V5_1 +}; + #define _FIXUP_EXT(_name, _manfid, _oemid, _rev_start, _rev_end, \ _cis_vendor, _cis_device, \ - _fixup, _data) \ + _fixup, _data, _ext_csd_rev) \ { \ .name = (_name), \ .manfid = (_manfid), \ @@ -376,23 +526,30 @@ .cis_device = (_cis_device), \ .vendor_fixup = (_fixup), \ .data = (_data), \ + .ext_csd_rev = (_ext_csd_rev), \ } #define MMC_FIXUP_REV(_name, _manfid, _oemid, _rev_start, _rev_end, \ - _fixup, _data) \ + _fixup, _data, _ext_csd_rev) \ _FIXUP_EXT(_name, _manfid, \ _oemid, _rev_start, _rev_end, \ SDIO_ANY_ID, SDIO_ANY_ID, \ - _fixup, _data) \ + _fixup, _data, _ext_csd_rev) \ #define MMC_FIXUP(_name, _manfid, _oemid, _fixup, _data) \ - MMC_FIXUP_REV(_name, _manfid, _oemid, 0, -1ull, _fixup, _data) + MMC_FIXUP_REV(_name, _manfid, _oemid, 0, -1ull, _fixup, _data, \ + EXT_CSD_REV_ANY) + +#define MMC_FIXUP_EXT_CSD_REV(_name, _manfid, _oemid, _fixup, _data, \ + _ext_csd_rev) \ + MMC_FIXUP_REV(_name, _manfid, _oemid, 0, -1ull, _fixup, _data, \ + _ext_csd_rev) #define SDIO_FIXUP(_vendor, _device, _fixup, _data) \ _FIXUP_EXT(CID_NAME_ANY, CID_MANFID_ANY, \ CID_OEMID_ANY, 0, -1ull, \ _vendor, _device, \ - _fixup, _data) \ + _fixup, _data, EXT_CSD_REV_ANY) \ #define cid_rev(hwrev, fwrev, year, month) \ (((u64) hwrev) << 40 | \ @@ -431,6 +588,8 @@ #define mmc_card_removed(c) ((c) && ((c)->state & MMC_CARD_REMOVED)) #define mmc_card_doing_bkops(c) ((c)->state & MMC_STATE_DOING_BKOPS) #define mmc_card_suspended(c) ((c)->state & MMC_STATE_SUSPENDED) +#define mmc_card_cmdq(c) ((c)->state & MMC_STATE_CMDQ) +#define mmc_card_doing_auto_bkops(c) ((c)->state & MMC_STATE_AUTO_BKOPS) #define mmc_card_set_present(c) ((c)->state |= MMC_STATE_PRESENT) #define mmc_card_set_readonly(c) ((c)->state |= MMC_STATE_READONLY) @@ -441,6 +600,12 @@ #define mmc_card_clr_doing_bkops(c) ((c)->state &= ~MMC_STATE_DOING_BKOPS) #define mmc_card_set_suspended(c) ((c)->state |= MMC_STATE_SUSPENDED) #define mmc_card_clr_suspended(c) ((c)->state &= ~MMC_STATE_SUSPENDED) +#define mmc_card_set_cmdq(c) ((c)->state |= MMC_STATE_CMDQ) +#define mmc_card_clr_cmdq(c) ((c)->state &= ~MMC_STATE_CMDQ) +#define mmc_card_set_auto_bkops(c) ((c)->state |= MMC_STATE_AUTO_BKOPS) +#define mmc_card_clr_auto_bkops(c) ((c)->state &= ~MMC_STATE_AUTO_BKOPS) + +#define mmc_card_strobe(c) (((c)->ext_csd).strobe_support & MMC_STROBE_SUPPORT) /* * Quirk add/remove for MMC products. @@ -511,10 +676,37 @@ return c->quirks & MMC_QUIRK_BROKEN_IRQ_POLLING; } +static inline bool mmc_card_support_auto_bkops(const struct mmc_card *c) +{ + return c->ext_csd.rev >= MMC_V5_1; +} + +static inline bool mmc_card_configured_manual_bkops(const struct mmc_card *c) +{ + return c->ext_csd.bkops_en & EXT_CSD_BKOPS_MANUAL_EN; +} + +static inline bool mmc_card_configured_auto_bkops(const struct mmc_card *c) +{ + return c->ext_csd.bkops_en & EXT_CSD_BKOPS_AUTO_EN; +} + +static inline bool mmc_enable_qca6574_settings(const struct mmc_card *c) +{ + return c->quirks & MMC_QUIRK_QCA6574_SETTINGS; +} + +static inline bool mmc_enable_qca9377_settings(const struct mmc_card *c) +{ + return c->quirks & MMC_QUIRK_QCA9377_SETTINGS; +} + #define mmc_card_name(c) ((c)->cid.prod_name) #define mmc_card_id(c) (dev_name(&(c)->dev)) #define mmc_dev_to_card(d) container_of(d, struct mmc_card, dev) +#define mmc_get_drvdata(c) dev_get_drvdata(&(c)->dev) +#define mmc_set_drvdata(c,d) dev_set_drvdata(&(c)->dev, d) /* * MMC device driver (e.g., Flash card, I/O card...) @@ -531,5 +723,9 @@ extern void mmc_fixup_device(struct mmc_card *card, const struct mmc_fixup *table); - +extern struct mmc_wr_pack_stats *mmc_blk_get_packed_statistics( + struct mmc_card *card); +extern void mmc_blk_init_packed_statistics(struct mmc_card *card); +extern int mmc_send_pon(struct mmc_card *card); +extern void mmc_blk_cmdq_req_done(struct mmc_request *mrq); #endif /* LINUX_MMC_CARD_H */ diff -ruw linux-4.4.115/include/linux/mmc/core.h linux-4.4.115-fbx/include/linux/mmc/core.h --- linux-4.4.115/include/linux/mmc/core.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/linux/mmc/core.h 2019-10-29 09:26:25.457220930 +0100 @@ -8,6 +8,7 @@ #ifndef LINUX_MMC_CORE_H #define LINUX_MMC_CORE_H +#include #include #include @@ -23,38 +24,6 @@ #define MMC_CMD23_ARG_TAG_REQ (1 << 29) u32 resp[4]; unsigned int flags; /* expected response type */ -#define MMC_RSP_PRESENT (1 << 0) -#define MMC_RSP_136 (1 << 1) /* 136 bit response */ -#define MMC_RSP_CRC (1 << 2) /* expect valid crc */ -#define MMC_RSP_BUSY (1 << 3) /* card may send busy */ -#define MMC_RSP_OPCODE (1 << 4) /* response contains opcode */ - -#define MMC_CMD_MASK (3 << 5) /* non-SPI command type */ -#define MMC_CMD_AC (0 << 5) -#define MMC_CMD_ADTC (1 << 5) -#define MMC_CMD_BC (2 << 5) -#define MMC_CMD_BCR (3 << 5) - -#define MMC_RSP_SPI_S1 (1 << 7) /* one status byte */ -#define MMC_RSP_SPI_S2 (1 << 8) /* second byte */ -#define MMC_RSP_SPI_B4 (1 << 9) /* four data bytes */ -#define MMC_RSP_SPI_BUSY (1 << 10) /* card may send busy */ - -/* - * These are the native response types, and correspond to valid bit - * patterns of the above flags. One additional valid pattern - * is all zeros, which means we don't expect a response. - */ -#define MMC_RSP_NONE (0) -#define MMC_RSP_R1 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE) -#define MMC_RSP_R1B (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE|MMC_RSP_BUSY) -#define MMC_RSP_R2 (MMC_RSP_PRESENT|MMC_RSP_136|MMC_RSP_CRC) -#define MMC_RSP_R3 (MMC_RSP_PRESENT) -#define MMC_RSP_R4 (MMC_RSP_PRESENT) -#define MMC_RSP_R5 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE) -#define MMC_RSP_R6 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE) -#define MMC_RSP_R7 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE) - #define mmc_resp_type(cmd) ((cmd)->flags & (MMC_RSP_PRESENT|MMC_RSP_136|MMC_RSP_CRC|MMC_RSP_BUSY|MMC_RSP_OPCODE)) /* @@ -98,6 +67,8 @@ unsigned int busy_timeout; /* busy detect timeout in ms */ /* Set this flag only for blocking sanitize request */ bool sanitize_busy; + /* Set this flag only for blocking bkops request */ + bool bkops_busy; struct mmc_data *data; /* data segment associated with cmd */ struct mmc_request *mrq; /* associated request */ @@ -124,6 +95,7 @@ int sg_count; /* mapped sg entries */ struct scatterlist *sg; /* I/O scatter list */ s32 host_cookie; /* host private data */ + bool fault_injected; /* fault injected */ }; struct mmc_host; @@ -136,10 +108,47 @@ struct completion completion; void (*done)(struct mmc_request *);/* completion function */ struct mmc_host *host; + struct mmc_cmdq_req *cmdq_req; + struct request *req; + ktime_t io_start; +#ifdef CONFIG_BLOCK + int lat_hist_enabled; +#endif +}; + +struct mmc_bus_ops { + void (*remove)(struct mmc_host *); + void (*detect)(struct mmc_host *); + int (*pre_suspend)(struct mmc_host *); + int (*suspend)(struct mmc_host *); + int (*resume)(struct mmc_host *); + int (*runtime_suspend)(struct mmc_host *); + int (*runtime_resume)(struct mmc_host *); + int (*runtime_idle)(struct mmc_host *); + int (*power_save)(struct mmc_host *); + int (*power_restore)(struct mmc_host *); + int (*alive)(struct mmc_host *); + int (*shutdown)(struct mmc_host *); + int (*reset)(struct mmc_host *); + int (*change_bus_speed)(struct mmc_host *, unsigned long *); }; struct mmc_card; struct mmc_async_req; +struct mmc_cmdq_req; + +extern int mmc_cmdq_discard_queue(struct mmc_host *host, u32 tasks); +extern int mmc_cmdq_halt(struct mmc_host *host, bool enable); +extern int mmc_cmdq_halt_on_empty_queue(struct mmc_host *host); +extern void mmc_cmdq_post_req(struct mmc_host *host, int tag, int err); +extern int mmc_cmdq_start_req(struct mmc_host *host, + struct mmc_cmdq_req *cmdq_req); +extern int mmc_cmdq_prepare_flush(struct mmc_command *cmd); +extern int mmc_cmdq_wait_for_dcmd(struct mmc_host *host, + struct mmc_cmdq_req *cmdq_req); +extern int mmc_cmdq_erase(struct mmc_cmdq_req *cmdq_req, + struct mmc_card *card, unsigned int from, unsigned int nr, + unsigned int arg); extern int mmc_stop_bkops(struct mmc_card *); extern int mmc_read_bkops_status(struct mmc_card *); @@ -151,10 +160,17 @@ extern int mmc_app_cmd(struct mmc_host *, struct mmc_card *); extern int mmc_wait_for_app_cmd(struct mmc_host *, struct mmc_card *, struct mmc_command *, int); -extern void mmc_start_bkops(struct mmc_card *card, bool from_exception); +extern void mmc_check_bkops(struct mmc_card *card); +extern void mmc_start_manual_bkops(struct mmc_card *card); extern int mmc_switch(struct mmc_card *, u8, u8, u8, unsigned int); +extern int __mmc_switch_cmdq_mode(struct mmc_command *cmd, u8 set, u8 index, + u8 value, unsigned int timeout_ms, + bool use_busy_signal, bool ignore_timeout); extern int mmc_send_tuning(struct mmc_host *host, u32 opcode, int *cmd_error); extern int mmc_get_ext_csd(struct mmc_card *card, u8 **new_ext_csd); +extern int mmc_set_auto_bkops(struct mmc_card *card, bool enable); +extern int mmc_suspend_clk_scaling(struct mmc_host *host); +extern void mmc_flush_detect_work(struct mmc_host *); #define MMC_ERASE_ARG 0x00000000 #define MMC_SECURE_ERASE_ARG 0x80000000 @@ -181,6 +197,7 @@ extern int mmc_set_blockcount(struct mmc_card *card, unsigned int blockcount, bool is_rel_write); extern int mmc_hw_reset(struct mmc_host *host); +extern int mmc_cmdq_hw_reset(struct mmc_host *host); extern int mmc_can_reset(struct mmc_card *card); extern void mmc_set_data_timeout(struct mmc_data *, const struct mmc_card *); @@ -188,14 +205,27 @@ extern int __mmc_claim_host(struct mmc_host *host, atomic_t *abort); extern void mmc_release_host(struct mmc_host *host); +extern int mmc_try_claim_host(struct mmc_host *host, unsigned int delay); extern void mmc_get_card(struct mmc_card *card); extern void mmc_put_card(struct mmc_card *card); +extern void __mmc_put_card(struct mmc_card *card); +extern void mmc_set_ios(struct mmc_host *host); extern int mmc_flush_cache(struct mmc_card *); +extern int mmc_cache_barrier(struct mmc_card *); extern int mmc_detect_card_removed(struct mmc_host *host); +extern void mmc_blk_init_bkops_statistics(struct mmc_card *card); + +extern void mmc_deferred_scaling(struct mmc_host *host); +extern void mmc_cmdq_clk_scaling_start_busy(struct mmc_host *host, + bool lock_needed); +extern void mmc_cmdq_clk_scaling_stop_busy(struct mmc_host *host, + bool lock_needed, bool is_cmdq_dcmd); +extern int mmc_recovery_fallback_lower_speed(struct mmc_host *host); + /** * mmc_claim_host - exclusively claim a host * @host: mmc host to claim diff -ruw linux-4.4.115/include/linux/mmc/host.h linux-4.4.115-fbx/include/linux/mmc/host.h --- linux-4.4.115/include/linux/mmc/host.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/linux/mmc/host.h 2019-10-29 09:26:25.457220930 +0100 @@ -15,14 +15,21 @@ #include #include #include +#include #include +#include #include #include #include +#include + +#define MMC_AUTOSUSPEND_DELAY_MS 3000 struct mmc_ios { unsigned int clock; /* clock rate */ + unsigned int old_rate; /* saved clock rate */ + unsigned long clk_ts; /* time stamp of last updated clock */ unsigned short vdd; /* vdd stores the bit number of the selected voltage range from below. */ @@ -79,7 +86,31 @@ #define MMC_SET_DRIVER_TYPE_D 3 }; +/* states to represent load on the host */ +enum mmc_load { + MMC_LOAD_HIGH, + MMC_LOAD_LOW, +}; + +struct mmc_cmdq_host_ops { + int (*init)(struct mmc_host *host); + int (*enable)(struct mmc_host *host); + void (*disable)(struct mmc_host *host, bool soft); + int (*request)(struct mmc_host *host, struct mmc_request *mrq); + void (*post_req)(struct mmc_host *host, int tag, int err); + int (*halt)(struct mmc_host *host, bool halt); + void (*reset)(struct mmc_host *host, bool soft); + void (*dumpstate)(struct mmc_host *host); +}; + struct mmc_host_ops { + int (*init)(struct mmc_host *host); + /* + * 'enable' is called when the host is claimed and 'disable' is called + * when the host is released. 'enable' and 'disable' are deprecated. + */ + int (*enable)(struct mmc_host *host); + int (*disable)(struct mmc_host *host); /* * It is optional for the host to implement pre_req and post_req in * order to support double buffering of requests (prepare one @@ -132,6 +163,7 @@ /* Prepare HS400 target operating frequency depending host driver */ int (*prepare_hs400_tuning)(struct mmc_host *host, struct mmc_ios *ios); + int (*enhanced_strobe)(struct mmc_host *host); int (*select_drive_strength)(struct mmc_card *card, unsigned int max_dtr, int host_drv, int card_drv, int *drv_type); @@ -144,11 +176,43 @@ */ int (*multi_io_quirk)(struct mmc_card *card, unsigned int direction, int blk_size); + + unsigned long (*get_max_frequency)(struct mmc_host *host); + unsigned long (*get_min_frequency)(struct mmc_host *host); + + int (*notify_load)(struct mmc_host *, enum mmc_load); + void (*notify_halt)(struct mmc_host *mmc, bool halt); + void (*force_err_irq)(struct mmc_host *host, u64 errmask); }; struct mmc_card; struct device; +struct mmc_cmdq_req { + unsigned int cmd_flags; + u32 blk_addr; + /* active mmc request */ + struct mmc_request mrq; + struct mmc_data data; + struct mmc_command cmd; +#define DCMD (1 << 0) +#define QBR (1 << 1) +#define DIR (1 << 2) +#define PRIO (1 << 3) +#define REL_WR (1 << 4) +#define DAT_TAG (1 << 5) +#define FORCED_PRG (1 << 6) + unsigned int cmdq_req_flags; + + unsigned int resp_idx; + unsigned int resp_arg; + unsigned int dev_pend_tasks; + bool resp_err; + bool skip_err_handling; + int tag; /* used for command queuing */ + u8 ctx_id; +}; + struct mmc_async_req { /* active mmc request */ struct mmc_request *mrq; @@ -175,6 +239,33 @@ void *handler_priv; }; + +/** + * mmc_cmdq_context_info - describes the contexts of cmdq + * @active_reqs requests being processed + * @data_active_reqs data requests being processed + * @curr_state state of cmdq engine + * @cmdq_ctx_lock acquire this before accessing this structure + * @queue_empty_wq workqueue for waiting for all + * the outstanding requests to be completed + * @wait waiting for all conditions described in + * mmc_cmdq_ready_wait to be satisified before + * issuing the new request to LLD. + */ +struct mmc_cmdq_context_info { + unsigned long active_reqs; /* in-flight requests */ + unsigned long data_active_reqs; /* in-flight data requests */ + unsigned long curr_state; +#define CMDQ_STATE_ERR 0 +#define CMDQ_STATE_DCMD_ACTIVE 1 +#define CMDQ_STATE_HALT 2 +#define CMDQ_STATE_CQ_DISABLE 3 +#define CMDQ_STATE_REQ_TIMED_OUT 4 + wait_queue_head_t queue_empty_wq; + wait_queue_head_t wait; + int active_small_sector_read_reqs; +}; + /** * mmc_context_info - synchronization details for mmc context * @is_done_rcv wake up reason was done request @@ -199,11 +290,70 @@ struct regulator *vqmmc; /* Optional Vccq supply */ }; +enum dev_state { + DEV_SUSPENDING = 1, + DEV_SUSPENDED, + DEV_RESUMED, +}; + +/** + * struct mmc_devfeq_clk_scaling - main context for MMC clock scaling logic + * + * @lock: spinlock to protect statistics + * @devfreq: struct that represent mmc-host as a client for devfreq + * @devfreq_profile: MMC device profile, mostly polling interval and callbacks + * @ondemand_gov_data: struct supplied to ondemmand governor (thresholds) + * @state: load state, can be HIGH or LOW. used to notify mmc_host_ops callback + * @start_busy: timestamped armed once a data request is started + * @measure_interval_start: timestamped armed once a measure interval started + * @devfreq_abort: flag to sync between different contexts relevant to devfreq + * @skip_clk_scale_freq_update: flag that enable/disable frequency change + * @freq_table_sz: table size of frequencies supplied to devfreq + * @freq_table: frequencies table supplied to devfreq + * @curr_freq: current frequency + * @polling_delay_ms: polling interval for status collection used by devfreq + * @upthreshold: up-threshold supplied to ondemand governor + * @downthreshold: down-threshold supplied to ondemand governor + * @need_freq_change: flag indicating if a frequency change is required + * @clk_scaling_in_progress: flag indicating if there's ongoing frequency change + * @is_busy_started: flag indicating if a request is handled by the HW + * @enable: flag indicating if the clock scaling logic is enabled for this host + */ +struct mmc_devfeq_clk_scaling { + spinlock_t lock; + struct devfreq *devfreq; + struct devfreq_dev_profile devfreq_profile; + struct devfreq_simple_ondemand_data ondemand_gov_data; + enum mmc_load state; + ktime_t start_busy; + ktime_t measure_interval_start; + atomic_t devfreq_abort; + bool skip_clk_scale_freq_update; + int freq_table_sz; + int pltfm_freq_table_sz; + u32 *freq_table; + u32 *pltfm_freq_table; + unsigned long total_busy_time_us; + unsigned long target_freq; + unsigned long curr_freq; + unsigned long polling_delay_ms; + unsigned int upthreshold; + unsigned int downthreshold; + unsigned int lower_bus_speed_mode; +#define MMC_SCALING_LOWER_DDR52_MODE 1 + bool need_freq_change; + bool clk_scaling_in_progress; + bool is_busy_started; + bool enable; +}; + struct mmc_host { struct device *parent; struct device class_dev; + struct mmc_devfeq_clk_scaling clk_scaling; int index; const struct mmc_host_ops *ops; + const struct mmc_cmdq_host_ops *cmdq_ops; struct mmc_pwrseq *pwrseq; unsigned int f_min; unsigned int f_max; @@ -289,9 +439,33 @@ #define MMC_CAP2_HSX00_1_2V (MMC_CAP2_HS200_1_2V_SDR | MMC_CAP2_HS400_1_2V) #define MMC_CAP2_SDIO_IRQ_NOTHREAD (1 << 17) #define MMC_CAP2_NO_WRITE_PROTECT (1 << 18) /* No physical write protect pin, assume that card is always read-write */ +#define MMC_CAP2_PACKED_WR_CONTROL (1 << 19) /* Allow write packing control */ +#define MMC_CAP2_CLK_SCALE (1 << 20) /* Allow dynamic clk scaling */ +/* Allows Asynchronous SDIO irq while card is in 4-bit mode */ +#define MMC_CAP2_ASYNC_SDIO_IRQ_4BIT_MODE (1 << 21) +/* Some hosts need additional tuning */ +#define MMC_CAP2_HS400_POST_TUNING (1 << 22) +#define MMC_CAP2_NONHOTPLUG (1 << 25) /*Don't support hotplug*/ +#define MMC_CAP2_CMD_QUEUE (1 << 26) /* support eMMC command queue */ +#define MMC_CAP2_SANITIZE (1 << 27) /* Support Sanitize */ +#define MMC_CAP2_SLEEP_AWAKE (1 << 28) /* Use Sleep/Awake (CMD5) */ +/* use max discard ignoring max_busy_timeout parameter */ +#define MMC_CAP2_MAX_DISCARD_SIZE (1 << 29) mmc_pm_flag_t pm_caps; /* supported pm features */ +#ifdef CONFIG_MMC_CLKGATE + int clk_requests; /* internal reference counter */ + unsigned int clk_delay; /* number of MCI clk hold cycles */ + bool clk_gated; /* clock gated */ + struct delayed_work clk_gate_work; /* delayed clock gate */ + unsigned int clk_old; /* old clock value cache */ + spinlock_t clk_lock; /* lock for clk fields */ + struct mutex clk_gate_mutex; /* mutex for clock gating */ + struct device_attribute clkgate_delay_attr; + unsigned long clkgate_delay; +#endif + /* host specific block data */ unsigned int max_seg_size; /* see blk_queue_max_segment_size */ unsigned short max_segs; /* see blk_queue_max_segments */ @@ -305,6 +479,7 @@ spinlock_t lock; /* lock for claim and bus ops */ struct mmc_ios ios; /* current io bus settings */ + struct mmc_ios cached_ios; /* group bitfields together to minimize padding */ unsigned int use_spi_crc:1; @@ -331,6 +506,7 @@ wait_queue_head_t wq; struct task_struct *claimer; /* task that has host claimed */ + struct task_struct *suspend_task; int claim_cnt; /* "claim" nesting count */ struct delayed_work detect; @@ -340,6 +516,11 @@ const struct mmc_bus_ops *bus_ops; /* current bus driver */ unsigned int bus_refs; /* reference counter */ + unsigned int bus_resume_flags; +#define MMC_BUSRESUME_MANUAL_RESUME (1 << 0) +#define MMC_BUSRESUME_NEEDS_RESUME (1 << 1) + bool ignore_bus_resume_flags; + unsigned int sdio_irqs; struct task_struct *sdio_irq_thread; bool sdio_irq_pending; @@ -356,6 +537,8 @@ struct dentry *debugfs_root; + bool err_occurred; + struct mmc_async_req *areq; /* active async req */ struct mmc_context_info context_info; /* async synchronization info */ @@ -370,25 +553,100 @@ int dsr_req; /* DSR value is valid */ u32 dsr; /* optional driver stage (DSR) value */ +#ifdef CONFIG_MMC_EMBEDDED_SDIO + struct { + struct sdio_cis *cis; + struct sdio_cccr *cccr; + struct sdio_embedded_func *funcs; + int num_funcs; + } embedded_sdio_data; +#endif + /* + * Set to 1 to just stop the SDCLK to the card without + * actually disabling the clock from it's source. + */ + bool card_clock_off; + +#ifdef CONFIG_MMC_PERF_PROFILING + struct { + + unsigned long rbytes_drv; /* Rd bytes MMC Host */ + unsigned long wbytes_drv; /* Wr bytes MMC Host */ + ktime_t rtime_drv; /* Rd time MMC Host */ + ktime_t wtime_drv; /* Wr time MMC Host */ + ktime_t start; + } perf; + bool perf_enable; +#endif + struct mmc_trace_buffer trace_buf; + enum dev_state dev_status; + bool wakeup_on_idle; + struct mmc_cmdq_context_info cmdq_ctx; + int num_cq_slots; + int dcmd_cq_slot; + bool cmdq_thist_enabled; + /* + * several cmdq supporting host controllers are extensions + * of legacy controllers. This variable can be used to store + * a reference to the cmdq extension of the existing host + * controller. + */ + void *cmdq_private; + struct mmc_request *err_mrq; +#ifdef CONFIG_BLOCK + int latency_hist_enabled; + struct io_latency_state io_lat_read; + struct io_latency_state io_lat_write; +#endif + + bool sdr104_wa; unsigned long private[0] ____cacheline_aligned; }; struct mmc_host *mmc_alloc_host(int extra, struct device *); +extern bool mmc_host_may_gate_card(struct mmc_card *); int mmc_add_host(struct mmc_host *); void mmc_remove_host(struct mmc_host *); void mmc_free_host(struct mmc_host *); int mmc_of_parse(struct mmc_host *host); +#ifdef CONFIG_MMC_EMBEDDED_SDIO +extern void mmc_set_embedded_sdio_data(struct mmc_host *host, + struct sdio_cis *cis, + struct sdio_cccr *cccr, + struct sdio_embedded_func *funcs, + int num_funcs); +#endif + static inline void *mmc_priv(struct mmc_host *host) { return (void *)host->private; } +static inline void *mmc_cmdq_private(struct mmc_host *host) +{ + return host->cmdq_private; +} + #define mmc_host_is_spi(host) ((host)->caps & MMC_CAP_SPI) #define mmc_dev(x) ((x)->parent) #define mmc_classdev(x) (&(x)->class_dev) #define mmc_hostname(x) (dev_name(&(x)->class_dev)) +#define mmc_bus_needs_resume(host) ((host)->bus_resume_flags & \ + MMC_BUSRESUME_NEEDS_RESUME) +#define mmc_bus_manual_resume(host) ((host)->bus_resume_flags & \ + MMC_BUSRESUME_MANUAL_RESUME) + +static inline void mmc_set_bus_resume_policy(struct mmc_host *host, int manual) +{ + if (manual) + host->bus_resume_flags |= MMC_BUSRESUME_MANUAL_RESUME; + else + host->bus_resume_flags &= ~MMC_BUSRESUME_MANUAL_RESUME; +} + +extern int mmc_resume_bus(struct mmc_host *host); int mmc_power_save_host(struct mmc_host *host); int mmc_power_restore_host(struct mmc_host *host); @@ -461,6 +719,12 @@ return !(host->caps2 & MMC_CAP2_BOOTPART_NOACC); } +static inline bool mmc_card_and_host_support_async_int(struct mmc_host *host) +{ + return ((host->caps2 & MMC_CAP2_ASYNC_SDIO_IRQ_4BIT_MODE) && + (host->card->cccr.async_intr_sup)); +} + static inline int mmc_host_uhs(struct mmc_host *host) { return host->caps & @@ -469,11 +733,71 @@ MMC_CAP_UHS_DDR50); } +static inline void mmc_host_clear_sdr104(struct mmc_host *host) +{ + host->caps &= ~MMC_CAP_UHS_SDR104; +} + +static inline void mmc_host_set_sdr104(struct mmc_host *host) +{ + host->caps |= MMC_CAP_UHS_SDR104; +} + static inline int mmc_host_packed_wr(struct mmc_host *host) { return host->caps2 & MMC_CAP2_PACKED_WR; } +static inline void mmc_host_set_halt(struct mmc_host *host) +{ + set_bit(CMDQ_STATE_HALT, &host->cmdq_ctx.curr_state); +} + +static inline void mmc_host_clr_halt(struct mmc_host *host) +{ + clear_bit(CMDQ_STATE_HALT, &host->cmdq_ctx.curr_state); +} + +static inline int mmc_host_halt(struct mmc_host *host) +{ + return test_bit(CMDQ_STATE_HALT, &host->cmdq_ctx.curr_state); +} + +static inline void mmc_host_set_cq_disable(struct mmc_host *host) +{ + set_bit(CMDQ_STATE_CQ_DISABLE, &host->cmdq_ctx.curr_state); +} + +static inline void mmc_host_clr_cq_disable(struct mmc_host *host) +{ + clear_bit(CMDQ_STATE_CQ_DISABLE, &host->cmdq_ctx.curr_state); +} + +static inline int mmc_host_cq_disable(struct mmc_host *host) +{ + return test_bit(CMDQ_STATE_CQ_DISABLE, &host->cmdq_ctx.curr_state); +} + +#ifdef CONFIG_MMC_CLKGATE +void mmc_host_clk_hold(struct mmc_host *host); +void mmc_host_clk_release(struct mmc_host *host); +unsigned int mmc_host_clk_rate(struct mmc_host *host); + +#else +static inline void mmc_host_clk_hold(struct mmc_host *host) +{ +} + +static inline void mmc_host_clk_release(struct mmc_host *host) +{ +} + +static inline unsigned int mmc_host_clk_rate(struct mmc_host *host) +{ + return host->ios.clock; +} +#endif + static inline int mmc_card_hs(struct mmc_card *card) { return card->host->ios.timing == MMC_TIMING_SD_HS || @@ -501,6 +825,8 @@ return card->host->ios.timing == MMC_TIMING_MMC_HS400; } +void mmc_retune_enable(struct mmc_host *host); +void mmc_retune_disable(struct mmc_host *host); void mmc_retune_timer_stop(struct mmc_host *host); static inline void mmc_retune_needed(struct mmc_host *host) diff -ruw linux-4.4.115/include/linux/mmc/mmc.h linux-4.4.115-fbx/include/linux/mmc/mmc.h --- linux-4.4.115/include/linux/mmc/mmc.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/linux/mmc/mmc.h 2019-01-22 16:16:28.311289946 +0100 @@ -24,65 +24,12 @@ #ifndef LINUX_MMC_MMC_H #define LINUX_MMC_MMC_H -/* Standard MMC commands (4.1) type argument response */ - /* class 1 */ -#define MMC_GO_IDLE_STATE 0 /* bc */ -#define MMC_SEND_OP_COND 1 /* bcr [31:0] OCR R3 */ -#define MMC_ALL_SEND_CID 2 /* bcr R2 */ -#define MMC_SET_RELATIVE_ADDR 3 /* ac [31:16] RCA R1 */ -#define MMC_SET_DSR 4 /* bc [31:16] RCA */ -#define MMC_SLEEP_AWAKE 5 /* ac [31:16] RCA 15:flg R1b */ -#define MMC_SWITCH 6 /* ac [31:0] See below R1b */ -#define MMC_SELECT_CARD 7 /* ac [31:16] RCA R1 */ -#define MMC_SEND_EXT_CSD 8 /* adtc R1 */ -#define MMC_SEND_CSD 9 /* ac [31:16] RCA R2 */ -#define MMC_SEND_CID 10 /* ac [31:16] RCA R2 */ -#define MMC_READ_DAT_UNTIL_STOP 11 /* adtc [31:0] dadr R1 */ -#define MMC_STOP_TRANSMISSION 12 /* ac R1b */ -#define MMC_SEND_STATUS 13 /* ac [31:16] RCA R1 */ -#define MMC_BUS_TEST_R 14 /* adtc R1 */ -#define MMC_GO_INACTIVE_STATE 15 /* ac [31:16] RCA */ -#define MMC_BUS_TEST_W 19 /* adtc R1 */ -#define MMC_SPI_READ_OCR 58 /* spi spi_R3 */ -#define MMC_SPI_CRC_ON_OFF 59 /* spi [0:0] flag spi_R1 */ - - /* class 2 */ -#define MMC_SET_BLOCKLEN 16 /* ac [31:0] block len R1 */ -#define MMC_READ_SINGLE_BLOCK 17 /* adtc [31:0] data addr R1 */ -#define MMC_READ_MULTIPLE_BLOCK 18 /* adtc [31:0] data addr R1 */ -#define MMC_SEND_TUNING_BLOCK 19 /* adtc R1 */ -#define MMC_SEND_TUNING_BLOCK_HS200 21 /* adtc R1 */ - - /* class 3 */ -#define MMC_WRITE_DAT_UNTIL_STOP 20 /* adtc [31:0] data addr R1 */ - - /* class 4 */ -#define MMC_SET_BLOCK_COUNT 23 /* adtc [31:0] data addr R1 */ -#define MMC_WRITE_BLOCK 24 /* adtc [31:0] data addr R1 */ -#define MMC_WRITE_MULTIPLE_BLOCK 25 /* adtc R1 */ -#define MMC_PROGRAM_CID 26 /* adtc R1 */ -#define MMC_PROGRAM_CSD 27 /* adtc R1 */ - - /* class 6 */ -#define MMC_SET_WRITE_PROT 28 /* ac [31:0] data addr R1b */ -#define MMC_CLR_WRITE_PROT 29 /* ac [31:0] data addr R1b */ -#define MMC_SEND_WRITE_PROT 30 /* adtc [31:0] wpdata addr R1 */ - - /* class 5 */ -#define MMC_ERASE_GROUP_START 35 /* ac [31:0] data addr R1 */ -#define MMC_ERASE_GROUP_END 36 /* ac [31:0] data addr R1 */ -#define MMC_ERASE 38 /* ac R1b */ - - /* class 9 */ -#define MMC_FAST_IO 39 /* ac R4 */ -#define MMC_GO_IRQ_STATE 40 /* bcr R5 */ - - /* class 7 */ -#define MMC_LOCK_UNLOCK 42 /* adtc R1b */ - - /* class 8 */ -#define MMC_APP_CMD 55 /* ac [31:16] RCA R1 */ -#define MMC_GEN_CMD 56 /* adtc [0] RD/WR R1 */ +#include + +/* class 11 */ +#define MMC_CMDQ_TASK_MGMT 48 /* ac [31:0] task ID R1b */ +#define DISCARD_QUEUE 0x1 +#define DISCARD_TASK 0x2 static inline bool mmc_op_multi(u32 opcode) { @@ -223,6 +170,7 @@ * OCR bits are mostly in host.h */ #define MMC_CARD_BUSY 0x80000000 /* Card Power up status bit */ +#define MMC_CARD_SECTOR_ADDR 0x40000000 /* Card supports sectors */ /* * Card Command Classes (CCC) @@ -272,6 +220,8 @@ * EXT_CSD fields */ +#define EXT_CSD_CMDQ 15 /* R/W */ +#define EXT_CSD_BARRIER_CTRL 31 /* R/W */ #define EXT_CSD_FLUSH_CACHE 32 /* W */ #define EXT_CSD_CACHE_CTRL 33 /* R/W */ #define EXT_CSD_POWER_OFF_NOTIFICATION 34 /* R/W */ @@ -297,6 +247,7 @@ #define EXT_CSD_PART_CONFIG 179 /* R/W */ #define EXT_CSD_ERASED_MEM_CONT 181 /* RO */ #define EXT_CSD_BUS_WIDTH 183 /* R/W */ +#define EXT_CSD_STROBE_SUPPORT 184 /* RO */ #define EXT_CSD_HS_TIMING 185 /* R/W */ #define EXT_CSD_POWER_CLASS 187 /* R/W */ #define EXT_CSD_REV 192 /* RO */ @@ -324,12 +275,20 @@ #define EXT_CSD_PWR_CL_200_360 237 /* RO */ #define EXT_CSD_PWR_CL_DDR_52_195 238 /* RO */ #define EXT_CSD_PWR_CL_DDR_52_360 239 /* RO */ +#define EXT_CSD_CACHE_FLUSH_POLICY 240 /* RO */ #define EXT_CSD_BKOPS_STATUS 246 /* RO */ #define EXT_CSD_POWER_OFF_LONG_TIME 247 /* RO */ #define EXT_CSD_GENERIC_CMD6_TIME 248 /* RO */ #define EXT_CSD_CACHE_SIZE 249 /* RO, 4 bytes */ #define EXT_CSD_PWR_CL_DDR_200_360 253 /* RO */ #define EXT_CSD_FIRMWARE_VERSION 254 /* RO, 8 bytes */ +#define EXT_CSD_PRE_EOL_INFO 267 /* RO */ +#define EXT_CSD_DEVICE_LIFE_TIME_EST_TYP_A 268 /* RO */ +#define EXT_CSD_DEVICE_LIFE_TIME_EST_TYP_B 269 /* RO */ +#define EXT_CSD_CMDQ_DEPTH 307 /* RO */ +#define EXT_CSD_CMDQ_SUPPORT 308 /* RO */ +#define EXT_CSD_BARRIER_SUPPORT 486 /* RO */ + #define EXT_CSD_TAG_UNIT_SIZE 498 /* RO */ #define EXT_CSD_SUPPORTED_MODE 493 /* RO */ #define EXT_CSD_TAG_UNIT_SIZE 498 /* RO */ #define EXT_CSD_DATA_TAG_SUPPORT 499 /* RO */ @@ -343,6 +302,7 @@ */ #define EXT_CSD_WR_REL_PARAM_EN (1<<2) +#define EXT_CSD_WR_REL_PARAM_EN_RPMB_REL_WR (1<<4) #define EXT_CSD_BOOT_WP_B_PWR_WP_DIS (0x40) #define EXT_CSD_BOOT_WP_B_PERM_WP_DIS (0x10) @@ -386,6 +346,7 @@ #define EXT_CSD_BUS_WIDTH_8 2 /* Card is in 8 bit mode */ #define EXT_CSD_DDR_BUS_WIDTH_4 5 /* Card is in 4 bit DDR mode */ #define EXT_CSD_DDR_BUS_WIDTH_8 6 /* Card is in 8 bit DDR mode */ +#define EXT_CSD_BUS_WIDTH_STROBE 0x80 /* Card is in 8 bit DDR mode */ #define EXT_CSD_TIMING_BC 0 /* Backwards compatility */ #define EXT_CSD_TIMING_HS 1 /* High speed */ @@ -413,6 +374,9 @@ #define EXT_CSD_PACKED_EVENT_EN BIT(3) +#define EXT_CSD_BKOPS_MANUAL_EN BIT(0) +#define EXT_CSD_BKOPS_AUTO_EN BIT(1) + /* * EXCEPTION_EVENT_STATUS field */ diff -ruw linux-4.4.115/include/linux/mmc/pm.h linux-4.4.115-fbx/include/linux/mmc/pm.h --- linux-4.4.115/include/linux/mmc/pm.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/linux/mmc/pm.h 2019-01-22 16:16:28.311289946 +0100 @@ -26,5 +26,6 @@ #define MMC_PM_KEEP_POWER (1 << 0) /* preserve card power during suspend */ #define MMC_PM_WAKE_SDIO_IRQ (1 << 1) /* wake up host system on SDIO IRQ assertion */ +#define MMC_PM_IGNORE_PM_NOTIFY (1 << 2) /* ignore mmc pm notify */ #endif /* LINUX_MMC_PM_H */ diff -ruw linux-4.4.115/include/linux/mmc/sdio_func.h linux-4.4.115-fbx/include/linux/mmc/sdio_func.h --- linux-4.4.115/include/linux/mmc/sdio_func.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/linux/mmc/sdio_func.h 2019-01-22 16:16:28.311289946 +0100 @@ -23,6 +23,14 @@ typedef void (sdio_irq_handler_t)(struct sdio_func *); /* + * Structure used to hold embedded SDIO device data from platform layer + */ +struct sdio_embedded_func { + uint8_t f_class; + uint32_t f_maxblksize; +}; + +/* * SDIO function CIS tuple (unknown to the core) */ struct sdio_func_tuple { @@ -128,6 +136,8 @@ extern unsigned int sdio_align_size(struct sdio_func *func, unsigned int sz); extern u8 sdio_readb(struct sdio_func *func, unsigned int addr, int *err_ret); +extern u8 sdio_readb_ext(struct sdio_func *func, unsigned int addr, int *err_ret, + unsigned in); extern u16 sdio_readw(struct sdio_func *func, unsigned int addr, int *err_ret); extern u32 sdio_readl(struct sdio_func *func, unsigned int addr, int *err_ret); diff -ruw linux-4.4.115/include/linux/mmc/sdio.h linux-4.4.115-fbx/include/linux/mmc/sdio.h --- linux-4.4.115/include/linux/mmc/sdio.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/linux/mmc/sdio.h 2019-01-22 16:16:28.311289946 +0100 @@ -102,6 +102,7 @@ #define SDIO_BUS_WIDTH_1BIT 0x00 #define SDIO_BUS_WIDTH_RESERVED 0x01 #define SDIO_BUS_WIDTH_4BIT 0x02 +#define SDIO_BUS_WIDTH_8BIT 0x03 #define SDIO_BUS_ECSI 0x20 /* Enable continuous SPI interrupt */ #define SDIO_BUS_SCSI 0x40 /* Support continuous SPI interrupt */ @@ -163,6 +164,10 @@ #define SDIO_DTSx_SET_TYPE_A (1 << SDIO_DRIVE_DTSx_SHIFT) #define SDIO_DTSx_SET_TYPE_C (2 << SDIO_DRIVE_DTSx_SHIFT) #define SDIO_DTSx_SET_TYPE_D (3 << SDIO_DRIVE_DTSx_SHIFT) + +#define SDIO_CCCR_INTERRUPT_EXTENSION 0x16 +#define SDIO_SUPPORT_ASYNC_INTR (1<<0) +#define SDIO_ENABLE_ASYNC_INTR (1<<1) /* * Function Basic Registers (FBR) */ diff -ruw linux-4.4.115/include/linux/mm.h linux-4.4.115-fbx/include/linux/mm.h --- linux-4.4.115/include/linux/mm.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/linux/mm.h 2019-10-29 09:26:25.457220930 +0100 @@ -29,6 +29,7 @@ struct user_struct; struct writeback_control; struct bdi_writeback; +struct super_block; #ifndef CONFIG_NEED_MULTIPLE_NODES /* Don't use mapnrs, do it properly */ extern unsigned long max_mapnr; @@ -51,6 +52,17 @@ #define sysctl_legacy_va_layout 0 #endif +#ifdef CONFIG_HAVE_ARCH_MMAP_RND_BITS +extern const int mmap_rnd_bits_min; +extern const int mmap_rnd_bits_max; +extern int mmap_rnd_bits __read_mostly; +#endif +#ifdef CONFIG_HAVE_ARCH_MMAP_RND_COMPAT_BITS +extern const int mmap_rnd_compat_bits_min; +extern const int mmap_rnd_compat_bits_max; +extern int mmap_rnd_compat_bits __read_mostly; +#endif + #include #include #include @@ -59,6 +71,10 @@ #define __pa_symbol(x) __pa(RELOC_HIDE((unsigned long)(x), 0)) #endif +#ifndef lm_alias +#define lm_alias(x) __va(__pa_symbol(x)) +#endif + /* * To prevent common memory management code establishing * a zero page mapping on a read fault. @@ -374,16 +390,16 @@ * On nommu, vmalloc/vfree wrap through kmalloc/kfree directly, so there * is no special casing required. */ -static inline int is_vmalloc_addr(const void *x) -{ -#ifdef CONFIG_MMU - unsigned long addr = (unsigned long)x; - return addr >= VMALLOC_START && addr < VMALLOC_END; +#ifdef CONFIG_MMU +extern int is_vmalloc_addr(const void *x); #else +static inline int is_vmalloc_addr(const void *x) +{ return 0; -#endif } +#endif + #ifdef CONFIG_MMU extern int is_vmalloc_or_module_addr(const void *x); #else @@ -517,7 +533,6 @@ void put_pages_list(struct list_head *pages); void split_page(struct page *page, unsigned int order); -int split_free_page(struct page *page); /* * Compound pages have a destructor function. Provide a @@ -983,6 +998,7 @@ { return atomic_read(&(page)->_mapcount) >= 0; } +struct address_space *page_mapping(struct page *page); /* * Return true only if the page has been allocated with @@ -1059,6 +1075,7 @@ extern void show_free_areas(unsigned int flags); extern bool skip_free_areas_node(unsigned int flags, int nid); +void shmem_set_file(struct vm_area_struct *vma, struct file *file); int shmem_zero_setup(struct vm_area_struct *); #ifdef CONFIG_SHMEM bool shmem_mapping(struct address_space *mapping); @@ -1838,7 +1855,7 @@ extern struct vm_area_struct *vma_merge(struct mm_struct *, struct vm_area_struct *prev, unsigned long addr, unsigned long end, unsigned long vm_flags, struct anon_vma *, struct file *, pgoff_t, - struct mempolicy *, struct vm_userfaultfd_ctx); + struct mempolicy *, struct vm_userfaultfd_ctx, const char __user *); extern struct anon_vma *find_mergeable_anon_vma(struct vm_area_struct *); extern int split_vma(struct mm_struct *, struct vm_area_struct *, unsigned long addr, int new_below); @@ -1951,8 +1968,11 @@ /* truncate.c */ extern void truncate_inode_pages(struct address_space *, loff_t); +extern void truncate_inode_pages_fill_zero(struct address_space *, loff_t); extern void truncate_inode_pages_range(struct address_space *, loff_t lstart, loff_t lend); +extern void truncate_inode_pages_range_fill_zero(struct address_space *, + loff_t lstart, loff_t lend); extern void truncate_inode_pages_final(struct address_space *); /* generic vm_area_ops exported for stackable file systems */ @@ -1965,7 +1985,7 @@ void task_dirty_inc(struct task_struct *tsk); /* readahead.c */ -#define VM_MAX_READAHEAD 128 /* kbytes */ +#define VM_MAX_READAHEAD 512 /* kbytes */ #define VM_MIN_READAHEAD 16 /* kbytes (includes current page) */ int force_page_cache_readahead(struct address_space *mapping, struct file *filp, @@ -2126,6 +2146,17 @@ } #endif /* CONFIG_PROC_FS */ +#ifdef CONFIG_PAGE_POISONING +extern bool page_poisoning_enabled(void); +extern void kernel_poison_pages(struct page *page, int numpages, int enable); +extern bool page_is_poisoned(struct page *page); +#else +static inline bool page_poisoning_enabled(void) { return false; } +static inline void kernel_poison_pages(struct page *page, int numpages, + int enable) { } +static inline bool page_is_poisoned(struct page *page) { return false; } +#endif + #ifdef CONFIG_DEBUG_PAGEALLOC extern bool _debug_pagealloc_enabled; extern void __kernel_map_pages(struct page *page, int numpages, int enable); @@ -2146,13 +2177,17 @@ #ifdef CONFIG_HIBERNATION extern bool kernel_page_present(struct page *page); #endif /* CONFIG_HIBERNATION */ -#else +#else /* CONFIG_DEBUG_PAGEALLOC */ static inline void kernel_map_pages(struct page *page, int numpages, int enable) {} #ifdef CONFIG_HIBERNATION static inline bool kernel_page_present(struct page *page) { return true; } #endif /* CONFIG_HIBERNATION */ -#endif +static inline bool debug_pagealloc_enabled(void) +{ + return false; +} +#endif /* CONFIG_DEBUG_PAGEALLOC */ #ifdef __HAVE_ARCH_GATE_AREA extern struct vm_area_struct *get_gate_vma(struct mm_struct *mm); @@ -2179,6 +2214,8 @@ void drop_slab(void); void drop_slab_node(int nid); +void drop_pagecache_sb(struct super_block *sb, void *unused); + #ifndef CONFIG_MMU #define randomize_va_space 0 #else @@ -2273,7 +2310,6 @@ #endif /* CONFIG_TRANSPARENT_HUGEPAGE || CONFIG_HUGETLBFS */ extern struct page_ext_operations debug_guardpage_ops; -extern struct page_ext_operations page_poisoning_ops; #ifdef CONFIG_DEBUG_PAGEALLOC extern unsigned int _debug_guardpage_minorder; @@ -2311,5 +2347,19 @@ static inline void setup_nr_node_ids(void) {} #endif +#ifdef CONFIG_PROCESS_RECLAIM +struct reclaim_param { + struct vm_area_struct *vma; + /* Number of pages scanned */ + int nr_scanned; + /* max pages to reclaim */ + int nr_to_reclaim; + /* pages reclaimed */ + int nr_reclaimed; +}; +extern struct reclaim_param reclaim_task_anon(struct task_struct *task, + int nr_to_reclaim); +#endif + #endif /* __KERNEL__ */ #endif /* _LINUX_MM_H */ diff -ruw linux-4.4.115/include/linux/mm_types.h linux-4.4.115-fbx/include/linux/mm_types.h --- linux-4.4.115/include/linux/mm_types.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/linux/mm_types.h 2019-10-29 09:26:25.457220930 +0100 @@ -12,6 +12,7 @@ #include #include #include +#include #include #include @@ -207,6 +208,10 @@ not kmapped, ie. highmem) */ #endif /* WANT_PAGE_VIRTUAL */ +#ifdef CONFIG_BLK_DEV_IO_TRACE + struct task_struct *tsk_dirty; /* task that sets this page dirty */ +#endif + #ifdef CONFIG_KMEMCHECK /* * kmemcheck wants to track the status of each byte in a page; this @@ -323,11 +328,18 @@ /* * For areas with an address space and backing store, * linkage into the address_space->i_mmap interval tree. + * + * For private anonymous mappings, a pointer to a null terminated string + * in the user process containing the name given to the vma, or NULL + * if unnamed. */ + union { struct { struct rb_node rb; unsigned long rb_subtree_last; } shared; + const char __user *anon_name; + }; /* * A file's MAP_PRIVATE vma can be in both i_mmap tree and anon_vma @@ -516,6 +528,11 @@ #ifdef CONFIG_HUGETLB_PAGE atomic_long_t hugetlb_usage; #endif +#ifdef CONFIG_MSM_APP_SETTINGS + int app_setting; +#endif + + struct work_struct async_put_work; }; static inline void mm_init_cpumask(struct mm_struct *mm) @@ -596,4 +613,13 @@ unsigned long val; } swp_entry_t; +/* Return the name for an anonymous mapping or NULL for a file-backed mapping */ +static inline const char __user *vma_get_anon_name(struct vm_area_struct *vma) +{ + if (vma->vm_file) + return NULL; + + return vma->anon_name; +} + #endif /* _LINUX_MM_TYPES_H */ diff -ruw linux-4.4.115/include/linux/mmzone.h linux-4.4.115-fbx/include/linux/mmzone.h --- linux-4.4.115/include/linux/mmzone.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/linux/mmzone.h 2019-01-22 16:16:28.311289946 +0100 @@ -39,8 +39,6 @@ MIGRATE_UNMOVABLE, MIGRATE_MOVABLE, MIGRATE_RECLAIMABLE, - MIGRATE_PCPTYPES, /* the number of types on the pcp lists */ - MIGRATE_HIGHATOMIC = MIGRATE_PCPTYPES, #ifdef CONFIG_CMA /* * MIGRATE_CMA migration type is designed to mimic the way @@ -57,16 +55,35 @@ */ MIGRATE_CMA, #endif + MIGRATE_PCPTYPES, /* the number of types on the pcp lists */ + MIGRATE_HIGHATOMIC = MIGRATE_PCPTYPES, #ifdef CONFIG_MEMORY_ISOLATION MIGRATE_ISOLATE, /* can't allocate from here */ #endif MIGRATE_TYPES }; +/* + * Returns a list which contains the migrate types on to which + * an allocation falls back when the free list for the migrate + * type mtype is depleted. + * The end of the list is delimited by the type MIGRATE_TYPES. + */ +extern int *get_migratetype_fallbacks(int mtype); + +/* In mm/page_alloc.c; keep in sync also with show_migration_types() there */ +extern char * const migratetype_names[MIGRATE_TYPES]; + #ifdef CONFIG_CMA +bool is_cma_pageblock(struct page *page); # define is_migrate_cma(migratetype) unlikely((migratetype) == MIGRATE_CMA) +# define get_cma_migrate_type() MIGRATE_CMA +# define is_migrate_cma_page(_page) (get_pageblock_migratetype(_page) == MIGRATE_CMA) #else +# define is_cma_pageblock(page) false # define is_migrate_cma(migratetype) false +# define get_cma_migrate_type() MIGRATE_MOVABLE +# define is_migrate_cma_page(_page) false #endif #define for_each_migratetype_order(order, type) \ @@ -158,6 +175,8 @@ WORKINGSET_NODERECLAIM, NR_ANON_TRANSPARENT_HUGEPAGES, NR_FREE_CMA_PAGES, + NR_SWAPCACHE, + NR_INDIRECTLY_RECLAIMABLE_BYTES, /* measured in bytes */ NR_VM_ZONE_STAT_ITEMS }; /* @@ -362,10 +381,13 @@ struct per_cpu_pageset __percpu *pageset; /* - * This is a per-zone reserve of pages that should not be - * considered dirtyable memory. + * This is a per-zone reserve of pages that are not available + * to userspace allocations. */ - unsigned long dirty_balance_reserve; + unsigned long totalreserve_pages; +#ifdef CONFIG_CMA + bool cma_alloc; +#endif #ifndef CONFIG_SPARSEMEM /* @@ -672,6 +694,12 @@ mem_hotplug_begin/end() */ int kswapd_max_order; enum zone_type classzone_idx; +#ifdef CONFIG_COMPACTION + int kcompactd_max_order; + enum zone_type kcompactd_classzone_idx; + wait_queue_head_t kcompactd_wait; + struct task_struct *kcompactd; +#endif #ifdef CONFIG_NUMA_BALANCING /* Lock serializing the migrate rate limiting window */ spinlock_t numabalancing_migrate_lock; diff -ruw linux-4.4.115/include/linux/mod_devicetable.h linux-4.4.115-fbx/include/linux/mod_devicetable.h --- linux-4.4.115/include/linux/mod_devicetable.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/linux/mod_devicetable.h 2019-10-29 09:26:25.461220969 +0100 @@ -291,7 +291,7 @@ #define INPUT_DEVICE_ID_LED_MAX 0x0f #define INPUT_DEVICE_ID_SND_MAX 0x07 #define INPUT_DEVICE_ID_FF_MAX 0x7f -#define INPUT_DEVICE_ID_SW_MAX 0x0f +#define INPUT_DEVICE_ID_SW_MAX 0x20 #define INPUT_DEVICE_ID_MATCH_BUS 1 #define INPUT_DEVICE_ID_MATCH_VENDOR 2 @@ -445,6 +445,16 @@ kernel_ulong_t driver_data; /* Data private to the driver */ }; +/* soundwire */ + +#define SOUNDWIRE_NAME_SIZE 32 +#define SOUNDWIRE_MODULE_PREFIX "swr:" + +struct swr_device_id { + char name[SOUNDWIRE_NAME_SIZE]; + kernel_ulong_t driver_data; /* Data private to the driver */ +}; + /* dmi */ enum dmi_field { DMI_NONE, @@ -481,6 +491,16 @@ struct dmi_strmatch matches[4]; void *driver_data; }; + +#define SLIMBUS_NAME_SIZE 32 +#define SLIMBUS_MODULE_PREFIX "slim:" + +struct slim_device_id { + char name[SLIMBUS_NAME_SIZE]; + kernel_ulong_t driver_data /* Data private to the driver */ + __attribute__((aligned(sizeof(kernel_ulong_t)))); +}; + /* * struct dmi_device_id appears during expansion of * "MODULE_DEVICE_TABLE(dmi, x)". Compiler doesn't look inside it diff -ruw linux-4.4.115/include/linux/module.h linux-4.4.115-fbx/include/linux/module.h --- linux-4.4.115/include/linux/module.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/linux/module.h 2019-10-29 09:26:25.461220969 +0100 @@ -125,13 +125,13 @@ /* Each module must use one module_init(). */ #define module_init(initfn) \ - static inline initcall_t __inittest(void) \ + static inline initcall_t __maybe_unused __inittest(void) \ { return initfn; } \ int init_module(void) __attribute__((alias(#initfn))); /* This is only required if you want to be unloadable. */ #define module_exit(exitfn) \ - static inline exitcall_t __exittest(void) \ + static inline exitcall_t __maybe_unused __exittest(void) \ { return exitfn; } \ void cleanup_module(void) __attribute__((alias(#exitfn))); diff -ruw linux-4.4.115/include/linux/mount.h linux-4.4.115-fbx/include/linux/mount.h --- linux-4.4.115/include/linux/mount.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/linux/mount.h 2019-01-22 16:16:28.311289946 +0100 @@ -67,6 +67,7 @@ struct dentry *mnt_root; /* root of the mounted tree */ struct super_block *mnt_sb; /* pointer to superblock */ int mnt_flags; + void *data; }; struct file; /* forward dec */ diff -ruw linux-4.4.115/include/linux/namei.h linux-4.4.115-fbx/include/linux/namei.h --- linux-4.4.115/include/linux/namei.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/linux/namei.h 2019-01-22 16:16:28.319290018 +0100 @@ -75,8 +75,11 @@ extern void done_path_create(struct path *, struct dentry *); extern struct dentry *kern_path_locked(const char *, struct path *); extern int kern_path_mountpoint(int, const char *, struct path *, unsigned int); +extern int vfs_path_lookup(struct dentry *, struct vfsmount *, + const char *, unsigned int, struct path *); extern struct dentry *lookup_one_len(const char *, struct dentry *, int); +extern struct dentry *lookup_one_len2(const char *, struct vfsmount *mnt, struct dentry *, int); extern int follow_down_one(struct path *); extern int follow_down(struct path *); diff -ruw linux-4.4.115/include/linux/netdevice.h linux-4.4.115-fbx/include/linux/netdevice.h --- linux-4.4.115/include/linux/netdevice.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/linux/netdevice.h 2019-10-29 09:26:25.465221008 +0100 @@ -2582,6 +2582,7 @@ */ struct softnet_data { struct list_head poll_list; + struct napi_struct *current_napi; struct sk_buff_head process_queue; /* stats */ @@ -2589,6 +2590,8 @@ unsigned int time_squeeze; unsigned int cpu_collision; unsigned int received_rps; + unsigned int gro_coalesced; + #ifdef CONFIG_RPS struct softnet_data *rps_ipi_list; #endif @@ -3076,6 +3079,7 @@ gro_result_t napi_gro_frags(struct napi_struct *napi); struct packet_offload *gro_find_receive_by_type(__be16 type); struct packet_offload *gro_find_complete_by_type(__be16 type); +extern struct napi_struct *get_current_napi_context(void); static inline void napi_free_frags(struct napi_struct *napi) { diff -ruw linux-4.4.115/include/linux/nmi.h linux-4.4.115-fbx/include/linux/nmi.h --- linux-4.4.115/include/linux/nmi.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/linux/nmi.h 2019-01-22 16:16:28.327290091 +0100 @@ -14,8 +14,11 @@ * may be used to reset the timeout - for code which intentionally * disables interrupts for a long time. This call is stateless. */ -#if defined(CONFIG_HAVE_NMI_WATCHDOG) || defined(CONFIG_HARDLOCKUP_DETECTOR) +#if defined(CONFIG_HAVE_NMI_WATCHDOG) || defined(CONFIG_HARDLOCKUP_DETECTOR_NMI) #include +#endif + +#if defined(CONFIG_HAVE_NMI_WATCHDOG) || defined(CONFIG_HARDLOCKUP_DETECTOR) extern void touch_nmi_watchdog(void); #else static inline void touch_nmi_watchdog(void) @@ -38,13 +41,22 @@ #ifdef arch_trigger_all_cpu_backtrace static inline bool trigger_all_cpu_backtrace(void) { + #if defined(CONFIG_ARM64) + arch_trigger_all_cpu_backtrace(); + #else arch_trigger_all_cpu_backtrace(true); + #endif return true; } static inline bool trigger_allbutself_cpu_backtrace(void) { + #if defined(CONFIG_ARM64) + arch_trigger_all_cpu_backtrace(); + #else arch_trigger_all_cpu_backtrace(false); + #endif + return true; } diff -ruw linux-4.4.115/include/linux/of_address.h linux-4.4.115-fbx/include/linux/of_address.h --- linux-4.4.115/include/linux/of_address.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/linux/of_address.h 2019-01-22 16:16:28.331290127 +0100 @@ -36,6 +36,8 @@ const struct of_device_id *matches, u64 base_address); extern void __iomem *of_iomap(struct device_node *device, int index); +extern void __iomem *of_iomap_by_name(struct device_node *device, + const char *name); /* Extract an address from a device, returns the region size and * the address space flags too. The PCI version uses a BAR number @@ -43,6 +45,8 @@ */ extern const __be32 *of_get_address(struct device_node *dev, int index, u64 *size, unsigned int *flags); +extern const __be32 *of_get_address_by_name(struct device_node *dev, + const char *name, u64 *size, unsigned int *flags); extern int pci_register_io_range(phys_addr_t addr, resource_size_t size); extern unsigned long pci_address_to_pio(phys_addr_t addr); diff -ruw linux-4.4.115/include/linux/of_fdt.h linux-4.4.115-fbx/include/linux/of_fdt.h --- linux-4.4.115/include/linux/of_fdt.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/linux/of_fdt.h 2019-01-22 16:16:28.331290127 +0100 @@ -59,6 +59,27 @@ extern unsigned long of_get_flat_dt_root(void); extern int of_get_flat_dt_size(void); +/* + * early_init_dt_scan_chosen - scan the device tree for ramdisk and bootargs + * + * The boot arguments will be placed into the memory pointed to by @data. + * That memory should be COMMAND_LINE_SIZE big and initialized to be a valid + * (possibly empty) string. Logic for what will be in @data after this + * function finishes: + * + * - CONFIG_CMDLINE_FORCE=true + * CONFIG_CMDLINE + * - CONFIG_CMDLINE_EXTEND=true, @data is non-empty string + * @data + dt bootargs (even if dt bootargs are empty) + * - CONFIG_CMDLINE_EXTEND=true, @data is empty string + * CONFIG_CMDLINE + dt bootargs (even if dt bootargs are empty) + * - CMDLINE_FROM_BOOTLOADER=true, dt bootargs=non-empty: + * dt bootargs + * - CMDLINE_FROM_BOOTLOADER=true, dt bootargs=empty, @data is non-empty string + * @data is left unchanged + * - CMDLINE_FROM_BOOTLOADER=true, dt bootargs=empty, @data is empty string + * CONFIG_CMDLINE (or "" if that's not defined) + */ extern int early_init_dt_scan_chosen(unsigned long node, const char *uname, int depth, void *data); extern int early_init_dt_scan_memory(unsigned long node, const char *uname, diff -ruw linux-4.4.115/include/linux/of_reserved_mem.h linux-4.4.115-fbx/include/linux/of_reserved_mem.h --- linux-4.4.115/include/linux/of_reserved_mem.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/linux/of_reserved_mem.h 2019-01-22 16:16:28.331290127 +0100 @@ -13,6 +13,7 @@ phys_addr_t base; phys_addr_t size; void *priv; + int fixup; }; struct reserved_mem_ops { diff -ruw linux-4.4.115/include/linux/oom.h linux-4.4.115-fbx/include/linux/oom.h --- linux-4.4.115/include/linux/oom.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/linux/oom.h 2019-01-22 16:16:28.331290127 +0100 @@ -113,6 +113,9 @@ !(task->signal->flags & SIGNAL_GROUP_COREDUMP); } +extern void dump_tasks(struct mem_cgroup *memcg, + const nodemask_t *nodemask); + /* sysctls */ extern int sysctl_oom_dump_tasks; extern int sysctl_oom_kill_allocating_task; diff -ruw linux-4.4.115/include/linux/page_ext.h linux-4.4.115-fbx/include/linux/page_ext.h --- linux-4.4.115/include/linux/page_ext.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/linux/page_ext.h 2019-01-22 16:16:28.335290163 +0100 @@ -3,6 +3,7 @@ #include #include +#include struct pglist_data; struct page_ext_operations { @@ -44,8 +45,8 @@ #ifdef CONFIG_PAGE_OWNER unsigned int order; gfp_t gfp_mask; - unsigned int nr_entries; - unsigned long trace_entries[8]; + int last_migrate_reason; + depot_stack_handle_t handle; #endif }; diff -ruw linux-4.4.115/include/linux/page-flags.h linux-4.4.115-fbx/include/linux/page-flags.h --- linux-4.4.115/include/linux/page-flags.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/linux/page-flags.h 2019-10-29 09:26:25.469221048 +0100 @@ -108,6 +108,9 @@ PG_young, PG_idle, #endif +#ifdef CONFIG_ZCACHE + PG_was_active, +#endif __NR_PAGEFLAGS, /* Filesystems */ @@ -129,6 +132,9 @@ /* SLOB */ PG_slob_free = PG_private, + + /* non-lru isolated movable page */ + PG_isolated = PG_reclaim, }; #ifndef __GENERATING_BOUNDS_H @@ -224,6 +230,11 @@ __SETPAGEFLAG(SwapBacked, swapbacked) __PAGEFLAG(SlobFree, slob_free) +#ifdef CONFIG_ZCACHE +PAGEFLAG(WasActive, was_active) +#else +PAGEFLAG_FALSE(WasActive) +#endif /* * Private page markings that may be used by the filesystem that owns the page @@ -301,25 +312,38 @@ * with the PAGE_MAPPING_ANON bit set to distinguish it. See rmap.h. * * On an anonymous page in a VM_MERGEABLE area, if CONFIG_KSM is enabled, - * the PAGE_MAPPING_KSM bit may be set along with the PAGE_MAPPING_ANON bit; - * and then page->mapping points, not to an anon_vma, but to a private + * the PAGE_MAPPING_MOVABLE bit may be set along with the PAGE_MAPPING_ANON + * bit; and then page->mapping points, not to an anon_vma, but to a private * structure which KSM associates with that merged page. See ksm.h. * - * PAGE_MAPPING_KSM without PAGE_MAPPING_ANON is currently never used. + * PAGE_MAPPING_KSM without PAGE_MAPPING_ANON is used for non-lru movable + * page and then page->mapping points a struct address_space. * * Please note that, confusingly, "page_mapping" refers to the inode * address_space which maps the page from disk; whereas "page_mapped" * refers to user virtual address space into which the page is mapped. */ -#define PAGE_MAPPING_ANON 1 -#define PAGE_MAPPING_KSM 2 -#define PAGE_MAPPING_FLAGS (PAGE_MAPPING_ANON | PAGE_MAPPING_KSM) +#define PAGE_MAPPING_ANON 0x1 +#define PAGE_MAPPING_MOVABLE 0x2 +#define PAGE_MAPPING_KSM (PAGE_MAPPING_ANON | PAGE_MAPPING_MOVABLE) +#define PAGE_MAPPING_FLAGS (PAGE_MAPPING_ANON | PAGE_MAPPING_MOVABLE) + +static __always_inline int PageMappingFlags(struct page *page) +{ + return ((unsigned long)page->mapping & PAGE_MAPPING_FLAGS) != 0; +} static inline int PageAnon(struct page *page) { return ((unsigned long)page->mapping & PAGE_MAPPING_ANON) != 0; } +static __always_inline int __PageMovable(struct page *page) +{ + return ((unsigned long)page->mapping & PAGE_MAPPING_FLAGS) == + PAGE_MAPPING_MOVABLE; +} + #ifdef CONFIG_KSM /* * A KSM page is one of those write-protected "shared pages" or "merged pages" @@ -330,7 +354,7 @@ static inline int PageKsm(struct page *page) { return ((unsigned long)page->mapping & PAGE_MAPPING_FLAGS) == - (PAGE_MAPPING_ANON | PAGE_MAPPING_KSM); + PAGE_MAPPING_KSM; } #else TESTPAGEFLAG_FALSE(Ksm) @@ -549,6 +573,8 @@ atomic_set(&page->_mapcount, -1); } +__PAGEFLAG(Isolated, isolated); + /* * If network-based swap is enabled, sl*b must keep track of whether pages * were allocated from pfmemalloc reserves. diff -ruw linux-4.4.115/include/linux/page_owner.h linux-4.4.115-fbx/include/linux/page_owner.h --- linux-4.4.115/include/linux/page_owner.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/linux/page_owner.h 2019-01-22 16:16:28.335290163 +0100 @@ -1,38 +1,52 @@ #ifndef __LINUX_PAGE_OWNER_H #define __LINUX_PAGE_OWNER_H +#include + #ifdef CONFIG_PAGE_OWNER -extern bool page_owner_inited; +extern struct static_key_false page_owner_inited; extern struct page_ext_operations page_owner_ops; extern void __reset_page_owner(struct page *page, unsigned int order); extern void __set_page_owner(struct page *page, unsigned int order, gfp_t gfp_mask); -extern gfp_t __get_page_owner_gfp(struct page *page); +extern void __split_page_owner(struct page *page, unsigned int order); +extern void __copy_page_owner(struct page *oldpage, struct page *newpage); +extern void __set_page_owner_migrate_reason(struct page *page, int reason); +extern void __dump_page_owner(struct page *page); static inline void reset_page_owner(struct page *page, unsigned int order) { - if (likely(!page_owner_inited)) - return; - + if (static_branch_unlikely(&page_owner_inited)) __reset_page_owner(page, order); } static inline void set_page_owner(struct page *page, unsigned int order, gfp_t gfp_mask) { - if (likely(!page_owner_inited)) - return; - + if (static_branch_unlikely(&page_owner_inited)) __set_page_owner(page, order, gfp_mask); } -static inline gfp_t get_page_owner_gfp(struct page *page) +static inline void split_page_owner(struct page *page, unsigned int order) { - if (likely(!page_owner_inited)) - return 0; - - return __get_page_owner_gfp(page); + if (static_branch_unlikely(&page_owner_inited)) + __split_page_owner(page, order); +} +static inline void copy_page_owner(struct page *oldpage, struct page *newpage) +{ + if (static_branch_unlikely(&page_owner_inited)) + __copy_page_owner(oldpage, newpage); +} +static inline void set_page_owner_migrate_reason(struct page *page, int reason) +{ + if (static_branch_unlikely(&page_owner_inited)) + __set_page_owner_migrate_reason(page, reason); +} +static inline void dump_page_owner(struct page *page) +{ + if (static_branch_unlikely(&page_owner_inited)) + __dump_page_owner(page); } #else static inline void reset_page_owner(struct page *page, unsigned int order) @@ -42,10 +56,18 @@ unsigned int order, gfp_t gfp_mask) { } -static inline gfp_t get_page_owner_gfp(struct page *page) +static inline void split_page_owner(struct page *page, + unsigned int order) +{ +} +static inline void copy_page_owner(struct page *oldpage, struct page *newpage) +{ +} +static inline void set_page_owner_migrate_reason(struct page *page, int reason) +{ +} +static inline void dump_page_owner(struct page *page) { - return 0; } - #endif /* CONFIG_PAGE_OWNER */ #endif /* __LINUX_PAGE_OWNER_H */ diff -ruw linux-4.4.115/include/linux/percpu-rwsem.h linux-4.4.115-fbx/include/linux/percpu-rwsem.h --- linux-4.4.115/include/linux/percpu-rwsem.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/linux/percpu-rwsem.h 2019-01-22 16:16:28.339290199 +0100 @@ -10,30 +10,96 @@ struct percpu_rw_semaphore { struct rcu_sync rss; - unsigned int __percpu *fast_read_ctr; + unsigned int __percpu *read_count; struct rw_semaphore rw_sem; - atomic_t slow_read_ctr; - wait_queue_head_t write_waitq; + wait_queue_head_t writer; + int readers_block; }; -extern void percpu_down_read(struct percpu_rw_semaphore *); -extern int percpu_down_read_trylock(struct percpu_rw_semaphore *); -extern void percpu_up_read(struct percpu_rw_semaphore *); +extern int __percpu_down_read(struct percpu_rw_semaphore *, int); +extern void __percpu_up_read(struct percpu_rw_semaphore *); + +static inline void percpu_down_read(struct percpu_rw_semaphore *sem) +{ + might_sleep(); + + rwsem_acquire_read(&sem->rw_sem.dep_map, 0, 0, _RET_IP_); + + preempt_disable(); + /* + * We are in an RCU-sched read-side critical section, so the writer + * cannot both change sem->state from readers_fast and start checking + * counters while we are here. So if we see !sem->state, we know that + * the writer won't be checking until we're past the preempt_enable() + * and that one the synchronize_sched() is done, the writer will see + * anything we did within this RCU-sched read-size critical section. + */ + __this_cpu_inc(*sem->read_count); + if (unlikely(!rcu_sync_is_idle(&sem->rss))) + __percpu_down_read(sem, false); /* Unconditional memory barrier */ + preempt_enable(); + /* + * The barrier() from preempt_enable() prevents the compiler from + * bleeding the critical section out. + */ +} + +static inline int percpu_down_read_trylock(struct percpu_rw_semaphore *sem) +{ + int ret = 1; + + preempt_disable(); + /* + * Same as in percpu_down_read(). + */ + __this_cpu_inc(*sem->read_count); + if (unlikely(!rcu_sync_is_idle(&sem->rss))) + ret = __percpu_down_read(sem, true); /* Unconditional memory barrier */ + preempt_enable(); + /* + * The barrier() from preempt_enable() prevents the compiler from + * bleeding the critical section out. + */ + + if (ret) + rwsem_acquire_read(&sem->rw_sem.dep_map, 0, 1, _RET_IP_); + + return ret; +} + +static inline void percpu_up_read(struct percpu_rw_semaphore *sem) +{ + /* + * The barrier() in preempt_disable() prevents the compiler from + * bleeding the critical section out. + */ + preempt_disable(); + /* + * Same as in percpu_down_read(). + */ + if (likely(rcu_sync_is_idle(&sem->rss))) + __this_cpu_dec(*sem->read_count); + else + __percpu_up_read(sem); /* Unconditional memory barrier */ + preempt_enable(); + + rwsem_release(&sem->rw_sem.dep_map, 1, _RET_IP_); +} extern void percpu_down_write(struct percpu_rw_semaphore *); extern void percpu_up_write(struct percpu_rw_semaphore *); extern int __percpu_init_rwsem(struct percpu_rw_semaphore *, const char *, struct lock_class_key *); + extern void percpu_free_rwsem(struct percpu_rw_semaphore *); -#define percpu_init_rwsem(brw) \ +#define percpu_init_rwsem(sem) \ ({ \ static struct lock_class_key rwsem_key; \ - __percpu_init_rwsem(brw, #brw, &rwsem_key); \ + __percpu_init_rwsem(sem, #sem, &rwsem_key); \ }) - #define percpu_rwsem_is_held(sem) lockdep_is_held(&(sem)->rw_sem) static inline void percpu_rwsem_release(struct percpu_rw_semaphore *sem, diff -ruw linux-4.4.115/include/linux/perf/arm_pmu.h linux-4.4.115-fbx/include/linux/perf/arm_pmu.h --- linux-4.4.115/include/linux/perf/arm_pmu.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/linux/perf/arm_pmu.h 2019-01-22 16:16:28.339290199 +0100 @@ -77,6 +77,12 @@ struct arm_pmu *percpu_pmu; }; +enum armpmu_pmu_states { + ARM_PMU_STATE_OFF, + ARM_PMU_STATE_RUNNING, + ARM_PMU_STATE_GOING_DOWN, +}; + struct arm_pmu { struct pmu pmu; cpumask_t active_irqs; @@ -101,17 +107,24 @@ void (*free_irq)(struct arm_pmu *); int (*map_event)(struct perf_event *event); int num_events; + int pmu_state; + int percpu_irq; atomic_t active_events; struct mutex reserve_mutex; u64 max_period; + bool secure_access; /* 32-bit ARM only */ struct platform_device *plat_device; struct pmu_hw_events __percpu *hw_events; struct notifier_block hotplug_nb; + struct notifier_block cpu_pm_nb; }; #define to_arm_pmu(p) (container_of(p, struct arm_pmu, pmu)) -int armpmu_register(struct arm_pmu *armpmu, int type); +extern const unsigned armv8_pmuv3_perf_map[PERF_COUNT_HW_MAX]; +extern const unsigned armv8_pmuv3_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] + [PERF_COUNT_HW_CACHE_OP_MAX] + [PERF_COUNT_HW_CACHE_RESULT_MAX]; u64 armpmu_event_update(struct perf_event *event); @@ -149,6 +162,18 @@ const struct of_device_id *of_table, const struct pmu_probe_info *probe_table); +void armv8_pmu_init(struct arm_pmu *cpu_pmu); +int armv8pmu_enable_intens(int idx); +int armv8pmu_disable_intens(int idx); +int armv8pmu_enable_counter(int idx); +int armv8pmu_disable_counter(int idx); +u32 armv8pmu_getreset_flags(void); +void armv8pmu_pmcr_write(u32 val); +void armv8pmu_write_evtype(int idx, u32 val); +int armv8pmu_probe_num_events(struct arm_pmu *arm_pmu); + +int kryo_pmu_init(struct arm_pmu *cpu_pmu); + #endif /* CONFIG_ARM_PMU */ #endif /* __ARM_PMU_H__ */ diff -ruw linux-4.4.115/include/linux/perf_event.h linux-4.4.115-fbx/include/linux/perf_event.h --- linux-4.4.115/include/linux/perf_event.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/linux/perf_event.h 2019-10-29 09:26:25.469221048 +0100 @@ -235,6 +235,8 @@ atomic_t exclusive_cnt; /* < 0: cpu; > 0: tsk */ int task_ctx_nr; int hrtimer_interval_ms; + u32 events_across_hotplug:1, + reserved:31; /* * Fully disable/enable this PMU, can be used to protect from the PMI @@ -379,7 +381,7 @@ /* * Set up pmu-private data structures for an AUX area */ - void *(*setup_aux) (int cpu, void **pages, + void *(*setup_aux) (struct perf_event *event, void **pages, int nr_pages, bool overwrite); /* optional */ @@ -392,6 +394,14 @@ * Filter events for PMU-specific reasons. */ int (*filter_match) (struct perf_event *event); /* optional */ + + /* + * Initial, PMU driver specific configuration. + */ + int (*get_drv_configs) (struct perf_event *event, + void __user *arg); /* optional */ + void (*free_drv_configs) (struct perf_event *event); + /* optional */ }; /** @@ -467,6 +477,12 @@ int nr_siblings; int group_flags; struct perf_event *group_leader; + + /* + * Protect the pmu, attributes and context of a group leader. + * Note: does not protect the pointer to the group_leader. + */ + struct mutex group_leader_mutex; struct pmu *pmu; enum perf_event_active_state state; @@ -559,6 +575,7 @@ struct irq_work pending; atomic_t event_limit; + struct list_head drv_configs; void (*destroy)(struct perf_event *); struct rcu_head rcu_head; @@ -754,6 +771,7 @@ extern u64 perf_event_read_value(struct perf_event *event, u64 *enabled, u64 *running); +extern struct dentry *perf_create_debug_dir(void); struct perf_sample_data { /* @@ -990,6 +1008,11 @@ loff_t *ppos); +static inline bool perf_paranoid_any(void) +{ + return sysctl_perf_event_paranoid > 2; +} + static inline bool perf_paranoid_tracepoint_raw(void) { return sysctl_perf_event_paranoid > -1; diff -ruw linux-4.4.115/include/linux/phy/phy-qcom-ufs.h linux-4.4.115-fbx/include/linux/phy/phy-qcom-ufs.h --- linux-4.4.115/include/linux/phy/phy-qcom-ufs.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/linux/phy/phy-qcom-ufs.h 2019-01-22 16:16:28.339290199 +0100 @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2015, Linux Foundation. All rights reserved. + * Copyright (c) 2013-2016, Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -51,9 +51,13 @@ void ufs_qcom_phy_disable_iface_clk(struct phy *phy); int ufs_qcom_phy_start_serdes(struct phy *phy); int ufs_qcom_phy_set_tx_lane_enable(struct phy *phy, u32 tx_lanes); +int ufs_qcom_phy_ctrl_rx_linecfg(struct phy *generic_phy, bool ctrl); int ufs_qcom_phy_calibrate_phy(struct phy *phy, bool is_rate_B); int ufs_qcom_phy_is_pcs_ready(struct phy *phy); void ufs_qcom_phy_save_controller_version(struct phy *phy, u8 major, u16 minor, u16 step); +const char *ufs_qcom_phy_name(struct phy *phy); +int ufs_qcom_phy_configure_lpm(struct phy *generic_phy, bool enable); +void ufs_qcom_phy_dbg_register_dump(struct phy *generic_phy); #endif /* PHY_QCOM_UFS_H_ */ diff -ruw linux-4.4.115/include/linux/platform_device.h linux-4.4.115-fbx/include/linux/platform_device.h --- linux-4.4.115/include/linux/platform_device.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/linux/platform_device.h 2019-01-22 16:16:28.355290344 +0100 @@ -51,6 +51,7 @@ extern struct resource *platform_get_resource(struct platform_device *, unsigned int, unsigned int); extern int platform_get_irq(struct platform_device *, unsigned int); +extern int platform_irq_count(struct platform_device *); extern struct resource *platform_get_resource_byname(struct platform_device *, unsigned int, const char *); diff -ruw linux-4.4.115/include/linux/plist.h linux-4.4.115-fbx/include/linux/plist.h --- linux-4.4.115/include/linux/plist.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/linux/plist.h 2019-01-22 16:16:28.355290344 +0100 @@ -266,6 +266,9 @@ #define plist_next(pos) \ list_next_entry(pos, node_list) +#define plist_next_entry(pos, type, member) \ + container_of(plist_next(pos), type, member) + /** * plist_prev - get the prev entry in list * @pos: the type * to cursor diff -ruw linux-4.4.115/include/linux/pm.h linux-4.4.115-fbx/include/linux/pm.h --- linux-4.4.115/include/linux/pm.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/linux/pm.h 2019-01-22 16:16:28.355290344 +0100 @@ -573,6 +573,7 @@ struct wakeup_source *wakeup; bool wakeup_path:1; bool syscore:1; + bool no_pm_callbacks:1; /* Owned by the PM core */ #else unsigned int should_wakeup:1; #endif diff -ruw linux-4.4.115/include/linux/pm_opp.h linux-4.4.115-fbx/include/linux/pm_opp.h --- linux-4.4.115/include/linux/pm_opp.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/linux/pm_opp.h 2019-01-22 16:16:28.355290344 +0100 @@ -34,6 +34,8 @@ int dev_pm_opp_get_opp_count(struct device *dev); unsigned long dev_pm_opp_get_max_clock_latency(struct device *dev); +unsigned long dev_pm_opp_get_max_volt_latency(struct device *dev); +unsigned long dev_pm_opp_get_max_transition_latency(struct device *dev); struct dev_pm_opp *dev_pm_opp_get_suspend_opp(struct device *dev); struct dev_pm_opp *dev_pm_opp_find_freq_exact(struct device *dev, @@ -55,6 +57,14 @@ int dev_pm_opp_disable(struct device *dev, unsigned long freq); struct srcu_notifier_head *dev_pm_opp_get_notifier(struct device *dev); +int dev_pm_opp_set_supported_hw(struct device *dev, const u32 *versions, + unsigned int count); +void dev_pm_opp_put_supported_hw(struct device *dev); +int dev_pm_opp_set_prop_name(struct device *dev, const char *name); +void dev_pm_opp_put_prop_name(struct device *dev); +int dev_pm_opp_set_regulator(struct device *dev, const char *name); +void dev_pm_opp_put_regulator(struct device *dev); +int dev_pm_opp_set_rate(struct device *dev, unsigned long target_freq); #else static inline unsigned long dev_pm_opp_get_voltage(struct dev_pm_opp *opp) { @@ -81,6 +91,16 @@ return 0; } +static inline unsigned long dev_pm_opp_get_max_volt_latency(struct device *dev) +{ + return 0; +} + +static inline unsigned long dev_pm_opp_get_max_transition_latency(struct device *dev) +{ + return 0; +} + static inline struct dev_pm_opp *dev_pm_opp_get_suspend_opp(struct device *dev) { return NULL; @@ -129,6 +149,35 @@ { return ERR_PTR(-EINVAL); } + +static inline int dev_pm_opp_set_supported_hw(struct device *dev, + const u32 *versions, + unsigned int count) +{ + return -EINVAL; +} + +static inline void dev_pm_opp_put_supported_hw(struct device *dev) {} + +static inline int dev_pm_opp_set_prop_name(struct device *dev, const char *name) +{ + return -EINVAL; +} + +static inline void dev_pm_opp_put_prop_name(struct device *dev) {} + +static inline int dev_pm_opp_set_regulator(struct device *dev, const char *name) +{ + return -EINVAL; +} + +static inline void dev_pm_opp_put_regulator(struct device *dev) {} + +static inline int dev_pm_opp_set_rate(struct device *dev, unsigned long target_freq) +{ + return -EINVAL; +} + #endif /* CONFIG_PM_OPP */ #if defined(CONFIG_PM_OPP) && defined(CONFIG_OF) diff -ruw linux-4.4.115/include/linux/pm_qos.h linux-4.4.115-fbx/include/linux/pm_qos.h --- linux-4.4.115/include/linux/pm_qos.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/linux/pm_qos.h 2019-01-22 16:16:28.355290344 +0100 @@ -9,6 +9,8 @@ #include #include #include +#include +#include enum { PM_QOS_RESERVED = 0, @@ -42,7 +44,22 @@ #define PM_QOS_FLAG_NO_POWER_OFF (1 << 0) #define PM_QOS_FLAG_REMOTE_WAKEUP (1 << 1) +enum pm_qos_req_type { + PM_QOS_REQ_ALL_CORES = 0, + PM_QOS_REQ_AFFINE_CORES, +#ifdef CONFIG_SMP + PM_QOS_REQ_AFFINE_IRQ, +#endif +}; + struct pm_qos_request { + enum pm_qos_req_type type; + struct cpumask cpus_affine; +#ifdef CONFIG_SMP + uint32_t irq; + /* Internal structure members */ + struct irq_affinity_notify irq_notify; +#endif struct plist_node node; int pm_qos_class; struct delayed_work work; /* for pm_qos_update_request_timeout */ @@ -62,7 +79,7 @@ struct dev_pm_qos_request { enum dev_pm_qos_req_type type; union { - struct plist_node pnode; + struct pm_qos_request lat; struct pm_qos_flags_request flr; } data; struct device *dev; @@ -83,6 +100,7 @@ struct pm_qos_constraints { struct plist_head list; s32 target_value; /* Do not change to 64 bit */ + s32 target_per_cpu[NR_CPUS]; s32 default_value; s32 no_constraint_value; enum pm_qos_type type; @@ -115,7 +133,8 @@ return req->dev != NULL; } -int pm_qos_update_target(struct pm_qos_constraints *c, struct plist_node *node, +int pm_qos_update_target(struct pm_qos_constraints *c, + struct pm_qos_request *req, enum pm_qos_req_action action, int value); bool pm_qos_update_flags(struct pm_qos_flags *pqf, struct pm_qos_flags_request *req, @@ -129,6 +148,8 @@ void pm_qos_remove_request(struct pm_qos_request *req); int pm_qos_request(int pm_qos_class); +int pm_qos_request_for_cpu(int pm_qos_class, int cpu); +int pm_qos_request_for_cpumask(int pm_qos_class, struct cpumask *mask); int pm_qos_add_notifier(int pm_qos_class, struct notifier_block *notifier); int pm_qos_remove_notifier(int pm_qos_class, struct notifier_block *notifier); int pm_qos_request_active(struct pm_qos_request *req); @@ -166,7 +187,7 @@ static inline s32 dev_pm_qos_requested_resume_latency(struct device *dev) { - return dev->power.qos->resume_latency_req->data.pnode.prio; + return dev->power.qos->resume_latency_req->data.lat.node.prio; } static inline s32 dev_pm_qos_requested_flags(struct device *dev) diff -ruw linux-4.4.115/include/linux/poison.h linux-4.4.115-fbx/include/linux/poison.h --- linux-4.4.115/include/linux/poison.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/linux/poison.h 2019-01-22 16:16:28.355290344 +0100 @@ -30,7 +30,11 @@ #define TIMER_ENTRY_STATIC ((void *) 0x74737461) /********** mm/debug-pagealloc.c **********/ +#ifdef CONFIG_PAGE_POISONING_ZERO +#define PAGE_POISON 0x00 +#else #define PAGE_POISON 0xaa +#endif /********** mm/slab.c **********/ /* diff -ruw linux-4.4.115/include/linux/poll.h linux-4.4.115-fbx/include/linux/poll.h --- linux-4.4.115/include/linux/poll.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/linux/poll.h 2019-01-22 16:16:28.355290344 +0100 @@ -96,7 +96,7 @@ extern void poll_freewait(struct poll_wqueues *pwq); extern int poll_schedule_timeout(struct poll_wqueues *pwq, int state, ktime_t *expires, unsigned long slack); -extern long select_estimate_accuracy(struct timespec *tv); +extern u64 select_estimate_accuracy(struct timespec *tv); static inline int poll_schedule(struct poll_wqueues *pwq, int state) diff -ruw linux-4.4.115/include/linux/power_supply.h linux-4.4.115-fbx/include/linux/power_supply.h --- linux-4.4.115/include/linux/power_supply.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/linux/power_supply.h 2019-10-29 09:26:25.473221087 +0100 @@ -18,6 +18,7 @@ #include #include #include +#include /* * All voltages, currents, charges, energies, time and temperatures in uV, @@ -45,6 +46,7 @@ POWER_SUPPLY_CHARGE_TYPE_NONE, POWER_SUPPLY_CHARGE_TYPE_TRICKLE, POWER_SUPPLY_CHARGE_TYPE_FAST, + POWER_SUPPLY_CHARGE_TYPE_TAPER, }; enum { @@ -57,6 +59,9 @@ POWER_SUPPLY_HEALTH_COLD, POWER_SUPPLY_HEALTH_WATCHDOG_TIMER_EXPIRE, POWER_SUPPLY_HEALTH_SAFETY_TIMER_EXPIRE, + POWER_SUPPLY_HEALTH_WARM, + POWER_SUPPLY_HEALTH_COOL, + POWER_SUPPLY_HEALTH_HOT, }; enum { @@ -84,6 +89,32 @@ POWER_SUPPLY_SCOPE_DEVICE, }; +enum { + POWER_SUPPLY_DP_DM_UNKNOWN = 0, + POWER_SUPPLY_DP_DM_PREPARE = 1, + POWER_SUPPLY_DP_DM_UNPREPARE = 2, + POWER_SUPPLY_DP_DM_CONFIRMED_HVDCP3 = 3, + POWER_SUPPLY_DP_DM_DP_PULSE = 4, + POWER_SUPPLY_DP_DM_DM_PULSE = 5, + POWER_SUPPLY_DP_DM_DP0P6_DMF = 6, + POWER_SUPPLY_DP_DM_DP0P6_DM3P3 = 7, + POWER_SUPPLY_DP_DM_DPF_DMF = 8, + POWER_SUPPLY_DP_DM_DPR_DMR = 9, + POWER_SUPPLY_DP_DM_HVDCP3_SUPPORTED = 10, + POWER_SUPPLY_DP_DM_ICL_DOWN = 11, + POWER_SUPPLY_DP_DM_ICL_UP = 12, + POWER_SUPPLY_DP_DM_FORCE_5V = 13, + POWER_SUPPLY_DP_DM_FORCE_9V = 14, + POWER_SUPPLY_DP_DM_FORCE_12V = 15, +}; + +enum { + POWER_SUPPLY_PL_NONE, + POWER_SUPPLY_PL_USBIN_USBIN, + POWER_SUPPLY_PL_USBIN_USBIN_EXT, + POWER_SUPPLY_PL_USBMID_USBMID, +}; + enum power_supply_property { /* Properties of type `int' */ POWER_SUPPLY_PROP_STATUS = 0, @@ -113,6 +144,8 @@ POWER_SUPPLY_PROP_CHARGE_FULL, POWER_SUPPLY_PROP_CHARGE_EMPTY, POWER_SUPPLY_PROP_CHARGE_NOW, + POWER_SUPPLY_PROP_CHARGE_NOW_RAW, + POWER_SUPPLY_PROP_CHARGE_NOW_ERROR, POWER_SUPPLY_PROP_CHARGE_AVG, POWER_SUPPLY_PROP_CHARGE_COUNTER, POWER_SUPPLY_PROP_CONSTANT_CHARGE_CURRENT, @@ -132,6 +165,7 @@ POWER_SUPPLY_PROP_CAPACITY_ALERT_MIN, /* in percents! */ POWER_SUPPLY_PROP_CAPACITY_ALERT_MAX, /* in percents! */ POWER_SUPPLY_PROP_CAPACITY_LEVEL, + POWER_SUPPLY_PROP_CAPACITY_RAW, POWER_SUPPLY_PROP_TEMP, POWER_SUPPLY_PROP_TEMP_MAX, POWER_SUPPLY_PROP_TEMP_MIN, @@ -148,10 +182,91 @@ POWER_SUPPLY_PROP_SCOPE, POWER_SUPPLY_PROP_CHARGE_TERM_CURRENT, POWER_SUPPLY_PROP_CALIBRATE, + /* Local extensions */ + POWER_SUPPLY_PROP_USB_HC, + POWER_SUPPLY_PROP_USB_OTG, + POWER_SUPPLY_PROP_BATTERY_CHARGING_ENABLED, + POWER_SUPPLY_PROP_CHARGING_ENABLED, + POWER_SUPPLY_PROP_STEP_CHARGING_ENABLED, + POWER_SUPPLY_PROP_STEP_CHARGING_STEP, + POWER_SUPPLY_PROP_PIN_ENABLED, + POWER_SUPPLY_PROP_INPUT_SUSPEND, + POWER_SUPPLY_PROP_INPUT_VOLTAGE_REGULATION, + POWER_SUPPLY_PROP_INPUT_CURRENT_MAX, + POWER_SUPPLY_PROP_INPUT_CURRENT_TRIM, + POWER_SUPPLY_PROP_INPUT_CURRENT_SETTLED, + POWER_SUPPLY_PROP_INPUT_VOLTAGE_SETTLED, + POWER_SUPPLY_PROP_VCHG_LOOP_DBC_BYPASS, + POWER_SUPPLY_PROP_CHARGE_COUNTER_SHADOW, + POWER_SUPPLY_PROP_HI_POWER, + POWER_SUPPLY_PROP_LOW_POWER, + POWER_SUPPLY_PROP_COOL_TEMP, + POWER_SUPPLY_PROP_WARM_TEMP, + POWER_SUPPLY_PROP_COLD_TEMP, + POWER_SUPPLY_PROP_HOT_TEMP, + POWER_SUPPLY_PROP_SYSTEM_TEMP_LEVEL, + POWER_SUPPLY_PROP_RESISTANCE, + POWER_SUPPLY_PROP_RESISTANCE_CAPACITIVE, + POWER_SUPPLY_PROP_RESISTANCE_ID, /* in Ohms */ + POWER_SUPPLY_PROP_RESISTANCE_NOW, + POWER_SUPPLY_PROP_FLASH_CURRENT_MAX, + POWER_SUPPLY_PROP_UPDATE_NOW, + POWER_SUPPLY_PROP_ESR_COUNT, + POWER_SUPPLY_PROP_BUCK_FREQ, + POWER_SUPPLY_PROP_BOOST_CURRENT, + POWER_SUPPLY_PROP_SAFETY_TIMER_ENABLE, + POWER_SUPPLY_PROP_CHARGE_DONE, + POWER_SUPPLY_PROP_FLASH_ACTIVE, + POWER_SUPPLY_PROP_FLASH_TRIGGER, + POWER_SUPPLY_PROP_FORCE_TLIM, + POWER_SUPPLY_PROP_DP_DM, + POWER_SUPPLY_PROP_INPUT_CURRENT_LIMITED, + POWER_SUPPLY_PROP_INPUT_CURRENT_NOW, + POWER_SUPPLY_PROP_CHARGE_QNOVO_ENABLE, + POWER_SUPPLY_PROP_CURRENT_QNOVO, + POWER_SUPPLY_PROP_VOLTAGE_QNOVO, + POWER_SUPPLY_PROP_RERUN_AICL, + POWER_SUPPLY_PROP_CYCLE_COUNT_ID, + POWER_SUPPLY_PROP_SAFETY_TIMER_EXPIRED, + POWER_SUPPLY_PROP_RESTRICTED_CHARGING, + POWER_SUPPLY_PROP_CURRENT_CAPABILITY, + POWER_SUPPLY_PROP_TYPEC_MODE, + POWER_SUPPLY_PROP_TYPEC_CC_ORIENTATION, /* 0: N/C, 1: CC1, 2: CC2 */ + POWER_SUPPLY_PROP_TYPEC_POWER_ROLE, + POWER_SUPPLY_PROP_PD_ALLOWED, + POWER_SUPPLY_PROP_PD_ACTIVE, + POWER_SUPPLY_PROP_PD_IN_HARD_RESET, + POWER_SUPPLY_PROP_PD_CURRENT_MAX, + POWER_SUPPLY_PROP_PD_USB_SUSPEND_SUPPORTED, + POWER_SUPPLY_PROP_CHARGER_TEMP, + POWER_SUPPLY_PROP_CHARGER_TEMP_MAX, + POWER_SUPPLY_PROP_PARALLEL_DISABLE, + POWER_SUPPLY_PROP_PE_START, + POWER_SUPPLY_PROP_SET_SHIP_MODE, + POWER_SUPPLY_PROP_SOC_REPORTING_READY, + POWER_SUPPLY_PROP_DEBUG_BATTERY, + POWER_SUPPLY_PROP_FCC_DELTA, + POWER_SUPPLY_PROP_ICL_REDUCTION, + POWER_SUPPLY_PROP_PARALLEL_MODE, + POWER_SUPPLY_PROP_DIE_HEALTH, + POWER_SUPPLY_PROP_CONNECTOR_HEALTH, + POWER_SUPPLY_PROP_CTM_CURRENT_MAX, + POWER_SUPPLY_PROP_HW_CURRENT_MAX, + POWER_SUPPLY_PROP_REAL_TYPE, + POWER_SUPPLY_PROP_PR_SWAP, + POWER_SUPPLY_PROP_CC_STEP, + POWER_SUPPLY_PROP_CC_STEP_SEL, + POWER_SUPPLY_PROP_SW_JEITA_ENABLED, + POWER_SUPPLY_PROP_PD_VOLTAGE_MAX, + POWER_SUPPLY_PROP_PD_VOLTAGE_MIN, + POWER_SUPPLY_PROP_SDP_CURRENT_MAX, + /* Local extensions of type int64_t */ + POWER_SUPPLY_PROP_CHARGE_COUNTER_EXT, /* Properties of type `const char *' */ POWER_SUPPLY_PROP_MODEL_NAME, POWER_SUPPLY_PROP_MANUFACTURER, POWER_SUPPLY_PROP_SERIAL_NUMBER, + POWER_SUPPLY_PROP_BATTERY_TYPE, }; enum power_supply_type { @@ -163,15 +278,59 @@ POWER_SUPPLY_TYPE_USB_DCP, /* Dedicated Charging Port */ POWER_SUPPLY_TYPE_USB_CDP, /* Charging Downstream Port */ POWER_SUPPLY_TYPE_USB_ACA, /* Accessory Charger Adapters */ + POWER_SUPPLY_TYPE_USB_HVDCP, /* High Voltage DCP */ + POWER_SUPPLY_TYPE_USB_HVDCP_3, /* Efficient High Voltage DCP */ + POWER_SUPPLY_TYPE_USB_PD, /* Power Delivery */ + POWER_SUPPLY_TYPE_WIRELESS, /* Accessory Charger Adapters */ + POWER_SUPPLY_TYPE_USB_FLOAT, /* Floating charger */ + POWER_SUPPLY_TYPE_BMS, /* Battery Monitor System */ + POWER_SUPPLY_TYPE_PARALLEL, /* Parallel Path */ + POWER_SUPPLY_TYPE_MAIN, /* Main Path */ + POWER_SUPPLY_TYPE_WIPOWER, /* Wipower */ + POWER_SUPPLY_TYPE_TYPEC, /* Type-C */ + POWER_SUPPLY_TYPE_UFP, /* Type-C UFP */ + POWER_SUPPLY_TYPE_DFP, /* TYpe-C DFP */ +}; + +/* Indicates USB Type-C CC connection status */ +enum power_supply_typec_mode { + POWER_SUPPLY_TYPEC_NONE, + + /* Acting as source */ + POWER_SUPPLY_TYPEC_SINK, /* Rd only */ + POWER_SUPPLY_TYPEC_SINK_POWERED_CABLE, /* Rd/Ra */ + POWER_SUPPLY_TYPEC_SINK_DEBUG_ACCESSORY, /* Rd/Rd */ + POWER_SUPPLY_TYPEC_SINK_AUDIO_ADAPTER, /* Ra/Ra */ + POWER_SUPPLY_TYPEC_POWERED_CABLE_ONLY, /* Ra only */ + + /* Acting as sink */ + POWER_SUPPLY_TYPEC_SOURCE_DEFAULT, /* Rp default */ + POWER_SUPPLY_TYPEC_SOURCE_MEDIUM, /* Rp 1.5A */ + POWER_SUPPLY_TYPEC_SOURCE_HIGH, /* Rp 3A */ + POWER_SUPPLY_TYPEC_NON_COMPLIANT, +}; + +enum power_supply_typec_power_role { + POWER_SUPPLY_TYPEC_PR_NONE, /* CC lines in high-Z */ + POWER_SUPPLY_TYPEC_PR_DUAL, + POWER_SUPPLY_TYPEC_PR_SINK, + POWER_SUPPLY_TYPEC_PR_SOURCE, }; enum power_supply_notifier_events { PSY_EVENT_PROP_CHANGED, }; +enum vmbms_power_usecase { + VMBMS_IGNORE_ALL_BIT = 1, + VMBMS_VOICE_CALL_BIT = (1 << 4), + VMBMS_STATIC_DISPLAY_BIT = (1 << 5), +}; + union power_supply_propval { int intval; const char *strval; + int64_t int64val; }; struct device_node; @@ -361,6 +520,9 @@ case POWER_SUPPLY_PROP_CURRENT_NOW: case POWER_SUPPLY_PROP_CURRENT_AVG: case POWER_SUPPLY_PROP_CURRENT_BOOT: + case POWER_SUPPLY_PROP_CHARGE_COUNTER_SHADOW: + case POWER_SUPPLY_PROP_INPUT_CURRENT_MAX: + case POWER_SUPPLY_PROP_FLASH_CURRENT_MAX: return 1; default: break; diff -ruw linux-4.4.115/include/linux/psci.h linux-4.4.115-fbx/include/linux/psci.h --- linux-4.4.115/include/linux/psci.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/linux/psci.h 2019-01-22 16:16:28.359290380 +0100 @@ -24,7 +24,11 @@ bool psci_power_state_loses_context(u32 state); bool psci_power_state_is_valid(u32 state); +int psci_cpu_init_idle(unsigned int cpu); +int psci_cpu_suspend_enter(unsigned long index); + struct psci_operations { + u32 (*get_version)(void); int (*cpu_suspend)(u32 state, unsigned long entry_point); int (*cpu_off)(u32 state); int (*cpu_on)(unsigned long cpuid, unsigned long entry_point); diff -ruw linux-4.4.115/include/linux/pstore.h linux-4.4.115-fbx/include/linux/pstore.h --- linux-4.4.115/include/linux/pstore.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/linux/pstore.h 2019-01-22 16:16:28.359290380 +0100 @@ -22,12 +22,13 @@ #ifndef _LINUX_PSTORE_H #define _LINUX_PSTORE_H -#include +#include +#include #include #include -#include #include -#include +#include +#include /* types */ enum pstore_type_id { @@ -67,6 +68,10 @@ enum kmsg_dump_reason reason, u64 *id, unsigned int part, const char *buf, bool compressed, size_t size, struct pstore_info *psi); + int (*write_buf_user)(enum pstore_type_id type, + enum kmsg_dump_reason reason, u64 *id, + unsigned int part, const char __user *buf, + bool compressed, size_t size, struct pstore_info *psi); int (*erase)(enum pstore_type_id type, u64 id, int count, struct timespec time, struct pstore_info *psi); diff -ruw linux-4.4.115/include/linux/pstore_ram.h linux-4.4.115-fbx/include/linux/pstore_ram.h --- linux-4.4.115/include/linux/pstore_ram.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/linux/pstore_ram.h 2019-01-22 16:16:28.359290380 +0100 @@ -17,11 +17,12 @@ #ifndef __LINUX_PSTORE_RAM_H__ #define __LINUX_PSTORE_RAM_H__ +#include #include +#include #include #include #include -#include /* * Choose whether access to the RAM zone requires locking or not. If a zone @@ -69,6 +70,8 @@ int persistent_ram_write(struct persistent_ram_zone *prz, const void *s, unsigned int count); +int persistent_ram_write_user(struct persistent_ram_zone *prz, + const void __user *s, unsigned int count); void persistent_ram_save_old(struct persistent_ram_zone *prz); size_t persistent_ram_old_size(struct persistent_ram_zone *prz); @@ -77,6 +80,8 @@ ssize_t persistent_ram_ecc_string(struct persistent_ram_zone *prz, char *str, size_t len); +void ramoops_console_write_buf(const char *buf, size_t size); + /* * Ramoops platform data * @mem_size memory size for ramoops diff -ruw linux-4.4.115/include/linux/radix-tree.h linux-4.4.115-fbx/include/linux/radix-tree.h --- linux-4.4.115/include/linux/radix-tree.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/linux/radix-tree.h 2019-10-29 09:26:25.473221087 +0100 @@ -274,6 +274,10 @@ unsigned int radix_tree_gang_lookup(struct radix_tree_root *root, void **results, unsigned long first_index, unsigned int max_items); +unsigned int +radix_tree_gang_lookup_index(struct radix_tree_root *root, void **results, + unsigned long *indices, unsigned long first_index, + unsigned int max_items); unsigned int radix_tree_gang_lookup_slot(struct radix_tree_root *root, void ***results, unsigned long *indices, unsigned long first_index, unsigned int max_items); diff -ruw linux-4.4.115/include/linux/rcu_sync.h linux-4.4.115-fbx/include/linux/rcu_sync.h --- linux-4.4.115/include/linux/rcu_sync.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/linux/rcu_sync.h 2019-01-22 16:16:28.367290453 +0100 @@ -59,6 +59,7 @@ } extern void rcu_sync_init(struct rcu_sync *, enum rcu_sync_type); +extern void rcu_sync_enter_start(struct rcu_sync *); extern void rcu_sync_enter(struct rcu_sync *); extern void rcu_sync_exit(struct rcu_sync *); extern void rcu_sync_dtor(struct rcu_sync *); diff -ruw linux-4.4.115/include/linux/rcutree.h linux-4.4.115-fbx/include/linux/rcutree.h --- linux-4.4.115/include/linux/rcutree.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/linux/rcutree.h 2019-01-22 16:16:28.367290453 +0100 @@ -37,7 +37,7 @@ /* * Note a virtualization-based context switch. This is simply a * wrapper around rcu_note_context_switch(), which allows TINY_RCU - * to save a few bytes. + * to save a few bytes. The caller must have disabled interrupts. */ static inline void rcu_virt_note_context_switch(int cpu) { diff -ruw linux-4.4.115/include/linux/regmap.h linux-4.4.115-fbx/include/linux/regmap.h --- linux-4.4.115/include/linux/regmap.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/linux/regmap.h 2019-01-22 16:16:28.371290489 +0100 @@ -29,6 +29,7 @@ struct regmap_range_cfg; struct regmap_field; struct snd_ac97; +struct swr_device; /* An enum of all the supported cache types */ enum regcache_type { @@ -387,7 +388,10 @@ const struct regmap_config *config, struct lock_class_key *lock_key, const char *lock_name); - +struct regmap *__regmap_init_swr(struct swr_device *dev, + const struct regmap_config *config, + struct lock_class_key *lock_key, + const char *lock_name); struct regmap *__devm_regmap_init(struct device *dev, const struct regmap_bus *bus, void *bus_context, @@ -420,6 +424,10 @@ const struct regmap_config *config, struct lock_class_key *lock_key, const char *lock_name); +struct regmap *__devm_regmap_init_swr(struct swr_device *dev, + const struct regmap_config *config, + struct lock_class_key *lock_key, + const char *lock_name); /* * Wrapper for regmap_init macros to include a unique lockdep key and name @@ -554,6 +562,18 @@ bool regmap_ac97_default_volatile(struct device *dev, unsigned int reg); /** + * regmap_init_swr(): Initialise register map + * + * @swr: Device that will be interacted with + * @config: Configuration for register map + * + * The return value will be an ERR_PTR() on error or a valid pointer to + * a struct regmap. + */ +#define regmap_init_swr(swr, config) \ + __regmap_lockdep_wrapper(__regmap_init_swr, #config, \ + swr, config) +/** * devm_regmap_init(): Initialise managed register map * * @dev: Device that will be interacted with @@ -668,6 +688,20 @@ __regmap_lockdep_wrapper(__devm_regmap_init_ac97, #config, \ ac97, config) +/** + * devm_regmap_init_swr(): Initialise managed register map + * + * @swr: Device that will be interacted with + * @config: Configuration for register map + * + * The return value will be an ERR_PTR() on error or a valid pointer + * to a struct regmap. The regmap will be automatically freed by the + * device management code. + */ +#define devm_regmap_init_swr(swr, config) \ + __regmap_lockdep_wrapper(__devm_regmap_init_swr, #config, \ + swr, config) + void regmap_exit(struct regmap *map); int regmap_reinit_cache(struct regmap *map, const struct regmap_config *config); diff -ruw linux-4.4.115/include/linux/regulator/consumer.h linux-4.4.115-fbx/include/linux/regulator/consumer.h --- linux-4.4.115/include/linux/regulator/consumer.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/linux/regulator/consumer.h 2019-01-22 16:16:28.371290489 +0100 @@ -103,6 +103,7 @@ * Data passed is old voltage cast to (void *). * PRE_DISABLE Regulator is about to be disabled * ABORT_DISABLE Regulator disable failed for some reason + * ENABLE Regulator was enabled. * * NOTE: These events can be OR'ed together when passed into handler. */ @@ -119,6 +120,7 @@ #define REGULATOR_EVENT_ABORT_VOLTAGE_CHANGE 0x200 #define REGULATOR_EVENT_PRE_DISABLE 0x400 #define REGULATOR_EVENT_ABORT_DISABLE 0x800 +#define REGULATOR_EVENT_ENABLE 0x1000 /** * struct pre_voltage_change_data - Data sent with PRE_VOLTAGE_CHANGE event @@ -142,6 +144,10 @@ * using the bulk regulator APIs. * @consumer: The regulator consumer for the supply. This will be managed * by the bulk API. + * @min_uV: The minimum requested voltage for the regulator (in microvolts), + * or 0 to not set a voltage. + * @max_uV: The maximum requested voltage for the regulator (in microvolts), + * or 0 to use @min_uV. * * The regulator APIs provide a series of regulator_bulk_() API calls as * a convenience to consumers which require multiple supplies. This @@ -150,6 +156,8 @@ struct regulator_bulk_data { const char *supply; struct regulator *consumer; + int min_uV; + int max_uV; /* private: Internal use */ int ret; @@ -214,6 +222,8 @@ struct regulator_bulk_data *consumers); int __must_check regulator_bulk_enable(int num_consumers, struct regulator_bulk_data *consumers); +int regulator_bulk_set_voltage(int num_consumers, + struct regulator_bulk_data *consumers); int regulator_bulk_disable(int num_consumers, struct regulator_bulk_data *consumers); int regulator_bulk_force_disable(int num_consumers, @@ -224,6 +234,7 @@ int regulator_can_change_voltage(struct regulator *regulator); int regulator_count_voltages(struct regulator *regulator); int regulator_list_voltage(struct regulator *regulator, unsigned selector); +int regulator_list_corner_voltage(struct regulator *regulator, int corner); int regulator_is_supported_voltage(struct regulator *regulator, int min_uV, int max_uV); unsigned int regulator_get_linear_step(struct regulator *regulator); @@ -556,6 +567,11 @@ return -EINVAL; } +static inline int regulator_list_corner_voltage(struct regulator *regulator, + int corner) +{ + return -EINVAL; +} #endif static inline int regulator_set_voltage_triplet(struct regulator *regulator, diff -ruw linux-4.4.115/include/linux/regulator/driver.h linux-4.4.115-fbx/include/linux/regulator/driver.h --- linux-4.4.115/include/linux/regulator/driver.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/linux/regulator/driver.h 2019-01-22 16:16:28.371290489 +0100 @@ -18,6 +18,7 @@ #include #include #include +#include struct regmap; struct regulator_dev; @@ -87,6 +88,10 @@ * if the selector indicates a voltage that is unusable on this system; * or negative errno. Selectors range from zero to one less than * regulator_desc.n_voltages. Voltages may be reported in any order. + * @list_corner_voltage: Return the maximum voltage in microvolts that + * that can be physically configured for the regulator when operating at + * the specified voltage corner or a negative errno if the corner value + * can't be used on this system. * * @set_current_limit: Configure a limit for a current-limited regulator. * The driver should select the current closest to max_uA. @@ -133,6 +138,7 @@ /* enumerate supported voltages */ int (*list_voltage) (struct regulator_dev *, unsigned selector); + int (*list_corner_voltage)(struct regulator_dev *, int corner); /* get/set regulator voltage */ int (*set_voltage) (struct regulator_dev *, int min_uV, int max_uV, @@ -370,6 +376,7 @@ int exclusive; u32 use_count; u32 open_count; + u32 open_offset; u32 bypass_count; /* lists we belong to */ @@ -399,6 +406,8 @@ /* time when this regulator was disabled last time */ unsigned long last_off_jiffy; + struct proxy_consumer *proxy_consumer; + struct regulator *debug_consumer; }; struct regulator_dev * diff -ruw linux-4.4.115/include/linux/rmap.h linux-4.4.115-fbx/include/linux/rmap.h --- linux-4.4.115/include/linux/rmap.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/linux/rmap.h 2019-01-22 16:16:28.375290525 +0100 @@ -10,6 +10,11 @@ #include #include +extern int isolate_lru_page(struct page *page); +extern void putback_lru_page(struct page *page); +extern unsigned long reclaim_pages_from_list(struct list_head *page_list, + struct vm_area_struct *vma); + /* * The anon_vma heads a list of private "related" vmas, to scan if * an anonymous page pointing to this anon_vma needs to be unmapped: @@ -176,7 +181,8 @@ #define TTU_ACTION(x) ((x) & TTU_ACTION_MASK) -int try_to_unmap(struct page *, enum ttu_flags flags); +int try_to_unmap(struct page *, enum ttu_flags flags, + struct vm_area_struct *vma); /* * Used by uprobes to replace a userspace page safely @@ -232,6 +238,7 @@ */ struct rmap_walk_control { void *arg; + struct vm_area_struct *target_vma; int (*rmap_one)(struct page *page, struct vm_area_struct *vma, unsigned long addr, void *arg); int (*done)(struct page *page); @@ -255,7 +262,7 @@ return 0; } -#define try_to_unmap(page, refs) SWAP_FAIL +#define try_to_unmap(page, refs, vma) SWAP_FAIL static inline int page_mkclean(struct page *page) { diff -ruw linux-4.4.115/include/linux/sched/sysctl.h linux-4.4.115-fbx/include/linux/sched/sysctl.h --- linux-4.4.115/include/linux/sched/sysctl.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/linux/sched/sysctl.h 2019-10-29 09:26:25.481221165 +0100 @@ -39,6 +39,51 @@ extern unsigned int sysctl_sched_min_granularity; extern unsigned int sysctl_sched_wakeup_granularity; extern unsigned int sysctl_sched_child_runs_first; +extern unsigned int sysctl_sched_sync_hint_enable; +extern unsigned int sysctl_sched_cstate_aware; + +#ifdef CONFIG_SCHED_HMP + +enum freq_reporting_policy { + FREQ_REPORT_MAX_CPU_LOAD_TOP_TASK, + FREQ_REPORT_CPU_LOAD, + FREQ_REPORT_TOP_TASK, + FREQ_REPORT_INVALID_POLICY +}; + +extern int sysctl_sched_freq_inc_notify; +extern int sysctl_sched_freq_dec_notify; +extern unsigned int sysctl_sched_freq_reporting_policy; +extern unsigned int sysctl_sched_window_stats_policy; +extern unsigned int sysctl_sched_ravg_hist_size; +extern unsigned int sysctl_sched_cpu_high_irqload; +extern unsigned int sysctl_sched_init_task_load_pct; +extern unsigned int sysctl_sched_spill_nr_run; +extern unsigned int sysctl_sched_spill_load_pct; +extern unsigned int sysctl_sched_upmigrate_pct; +extern unsigned int sysctl_sched_downmigrate_pct; +extern unsigned int sysctl_sched_group_upmigrate_pct; +extern unsigned int sysctl_sched_group_downmigrate_pct; +extern unsigned int sysctl_early_detection_duration; +extern unsigned int sysctl_sched_boost; +extern unsigned int sysctl_sched_small_wakee_task_load_pct; +extern unsigned int sysctl_sched_big_waker_task_load_pct; +extern unsigned int sysctl_sched_select_prev_cpu_us; +extern unsigned int sysctl_sched_restrict_cluster_spill; +extern unsigned int sysctl_sched_new_task_windows; +extern unsigned int sysctl_sched_pred_alert_freq; +extern unsigned int sysctl_sched_freq_aggregate; +extern unsigned int sysctl_sched_enable_thread_grouping; +extern unsigned int sysctl_sched_freq_aggregate_threshold_pct; +extern unsigned int sysctl_sched_prefer_sync_wakee_to_waker; +extern unsigned int sysctl_sched_short_burst; +extern unsigned int sysctl_sched_short_sleep; + +#else /* CONFIG_SCHED_HMP */ + +#define sysctl_sched_enable_hmp_task_placement 0 + +#endif /* CONFIG_SCHED_HMP */ enum sched_tunable_scaling { SCHED_TUNABLESCALING_NONE, @@ -64,6 +109,18 @@ loff_t *ppos); #endif +extern int sched_migrate_notify_proc_handler(struct ctl_table *table, + int write, void __user *buffer, size_t *lenp, loff_t *ppos); + +extern int sched_hmp_proc_update_handler(struct ctl_table *table, + int write, void __user *buffer, size_t *lenp, loff_t *ppos); + +extern int sched_boost_handler(struct ctl_table *table, int write, + void __user *buffer, size_t *lenp, loff_t *ppos); + +extern int sched_window_update_handler(struct ctl_table *table, + int write, void __user *buffer, size_t *lenp, loff_t *ppos); + /* * control realtime throttling: * @@ -77,6 +134,22 @@ extern unsigned int sysctl_sched_cfs_bandwidth_slice; #endif +#ifdef CONFIG_SCHED_TUNE +extern unsigned int sysctl_sched_cfs_boost; +int sysctl_sched_cfs_boost_handler(struct ctl_table *table, int write, + void __user *buffer, size_t *length, + loff_t *ppos); +static inline unsigned int get_sysctl_sched_cfs_boost(void) +{ + return sysctl_sched_cfs_boost; +} +#else +static inline unsigned int get_sysctl_sched_cfs_boost(void) +{ + return 0; +} +#endif + #ifdef CONFIG_SCHED_AUTOGROUP extern unsigned int sysctl_sched_autogroup_enabled; #endif diff -ruw linux-4.4.115/include/linux/sched.h linux-4.4.115-fbx/include/linux/sched.h --- linux-4.4.115/include/linux/sched.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/linux/sched.h 2019-10-29 09:26:25.481221165 +0100 @@ -51,6 +51,7 @@ #include #include #include +#include #include #include #include @@ -173,6 +174,14 @@ extern unsigned long nr_iowait(void); extern unsigned long nr_iowait_cpu(int cpu); extern void get_iowait_load(unsigned long *nr_waiters, unsigned long *load); +#ifdef CONFIG_CPU_QUIET +extern u64 nr_running_integral(unsigned int cpu); +#endif + +extern void sched_update_nr_prod(int cpu, long delta, bool inc); +extern void sched_get_nr_running_avg(int *avg, int *iowait_avg, int *big_avg, + unsigned int *max_nr, + unsigned int *big_max_nr); extern void calc_global_load(unsigned long ticks); @@ -219,9 +228,10 @@ #define TASK_WAKING 256 #define TASK_PARKED 512 #define TASK_NOLOAD 1024 -#define TASK_STATE_MAX 2048 +#define TASK_NEW 2048 +#define TASK_STATE_MAX 4096 -#define TASK_STATE_TO_CHAR_STR "RSDTtXZxKWPN" +#define TASK_STATE_TO_CHAR_STR "RSDTtXZxKWPNn" extern char ___assert_task_state[1 - 2*!!( sizeof(TASK_STATE_TO_CHAR_STR)-1 != ilog2(TASK_STATE_MAX)+1)]; @@ -314,6 +324,23 @@ /* Task command name length */ #define TASK_COMM_LEN 16 +extern const char *sched_window_reset_reasons[]; + +enum task_event { + PUT_PREV_TASK = 0, + PICK_NEXT_TASK = 1, + TASK_WAKE = 2, + TASK_MIGRATE = 3, + TASK_UPDATE = 4, + IRQ_UPDATE = 5, +}; + +/* Note: this need to be in sync with migrate_type_names array */ +enum migrate_types { + GROUP_TO_RQ, + RQ_TO_GROUP, +}; + #include /* @@ -334,13 +361,48 @@ extern void sched_init(void); extern void sched_init_smp(void); extern asmlinkage void schedule_tail(struct task_struct *prev); -extern void init_idle(struct task_struct *idle, int cpu); +extern void init_idle(struct task_struct *idle, int cpu, bool hotplug); extern void init_idle_bootup_task(struct task_struct *idle); extern cpumask_var_t cpu_isolated_map; extern int runqueue_is_locked(int cpu); +#ifdef CONFIG_HOTPLUG_CPU +extern int sched_isolate_count(const cpumask_t *mask, bool include_offline); +extern int sched_isolate_cpu(int cpu); +extern int sched_unisolate_cpu(int cpu); +extern int sched_unisolate_cpu_unlocked(int cpu); +#else +static inline int sched_isolate_count(const cpumask_t *mask, + bool include_offline) +{ + cpumask_t count_mask; + + if (include_offline) + cpumask_andnot(&count_mask, mask, cpu_online_mask); + else + return 0; + + return cpumask_weight(&count_mask); +} + +static inline int sched_isolate_cpu(int cpu) +{ + return 0; +} + +static inline int sched_unisolate_cpu(int cpu) +{ + return 0; +} + +static inline int sched_unisolate_cpu_unlocked(int cpu) +{ + return 0; +} +#endif + #if defined(CONFIG_SMP) && defined(CONFIG_NO_HZ_COMMON) extern void nohz_balance_enter_idle(int cpu); extern void set_cpu_sd_state_idle(void); @@ -377,6 +439,7 @@ extern void sched_show_task(struct task_struct *p); #ifdef CONFIG_LOCKUP_DETECTOR +extern void touch_softlockup_watchdog_sched(void); extern void touch_softlockup_watchdog(void); extern void touch_softlockup_watchdog_sync(void); extern void touch_all_softlockup_watchdogs(void); @@ -386,7 +449,13 @@ extern unsigned int softlockup_panic; extern unsigned int hardlockup_panic; void lockup_detector_init(void); +extern void watchdog_enable(unsigned int cpu); +extern void watchdog_disable(unsigned int cpu); +extern bool watchdog_configured(unsigned int cpu); #else +static inline void touch_softlockup_watchdog_sched(void) +{ +} static inline void touch_softlockup_watchdog(void) { } @@ -399,6 +468,20 @@ static inline void lockup_detector_init(void) { } +static inline void watchdog_enable(unsigned int cpu) +{ +} +static inline void watchdog_disable(unsigned int cpu) +{ +} +static inline bool watchdog_configured(unsigned int cpu) +{ + /* + * Predend the watchdog is always configured. + * We will be waiting for the watchdog to be enabled in core isolation + */ + return true; +} #endif #ifdef CONFIG_DETECT_HUNG_TASK @@ -939,6 +1022,14 @@ #define SCHED_CAPACITY_SHIFT 10 #define SCHED_CAPACITY_SCALE (1L << SCHED_CAPACITY_SHIFT) +struct sched_capacity_reqs { + unsigned long cfs; + unsigned long rt; + unsigned long dl; + + unsigned long total; +}; + /* * Wake-queues are lists of tasks with a pending wakeup, whose * callers have already marked the task as woken internally, @@ -972,12 +1063,13 @@ struct wake_q_head { struct wake_q_node *first; struct wake_q_node **lastp; + int count; }; #define WAKE_Q_TAIL ((struct wake_q_node *) 0x01) #define WAKE_Q(name) \ - struct wake_q_head name = { WAKE_Q_TAIL, &name.first } + struct wake_q_head name = { WAKE_Q_TAIL, &name.first, 0 } extern void wake_q_add(struct wake_q_head *head, struct task_struct *task); @@ -993,7 +1085,8 @@ #define SD_BALANCE_FORK 0x0008 /* Balance on fork, clone */ #define SD_BALANCE_WAKE 0x0010 /* Balance on wakeup */ #define SD_WAKE_AFFINE 0x0020 /* Wake task to waking CPU */ -#define SD_SHARE_CPUCAPACITY 0x0080 /* Domain members share cpu power */ +#define SD_ASYM_CPUCAPACITY 0x0040 /* Groups have different max cpu capacities */ +#define SD_SHARE_CPUCAPACITY 0x0080 /* Domain members share cpu capacity */ #define SD_SHARE_POWERDOMAIN 0x0100 /* Domain members share power domain */ #define SD_SHARE_PKG_RESOURCES 0x0200 /* Domain members share cpu pkg resources */ #define SD_SERIALIZE 0x0400 /* Only a single load balancing instance */ @@ -1001,6 +1094,7 @@ #define SD_PREFER_SIBLING 0x1000 /* Prefer to place tasks in a sibling domain */ #define SD_OVERLAP 0x2000 /* sched_domains of this level overlap */ #define SD_NUMA 0x4000 /* cross-node balancing */ +#define SD_SHARE_CAP_STATES 0x8000 /* Domain members share capacity state */ #ifdef CONFIG_SCHED_SMT static inline int cpu_smt_flags(void) @@ -1033,8 +1127,57 @@ extern int sched_domain_level_max; +struct capacity_state { + unsigned long cap; /* compute capacity */ + unsigned long power; /* power consumption at this compute capacity */ +}; + +struct idle_state { + unsigned long power; /* power consumption in this idle state */ +}; + +struct sched_group_energy { + unsigned int nr_idle_states; /* number of idle states */ + struct idle_state *idle_states; /* ptr to idle state array */ + unsigned int nr_cap_states; /* number of capacity states */ + struct capacity_state *cap_states; /* ptr to capacity state array */ +}; + +unsigned long capacity_curr_of(int cpu); + struct sched_group; +struct eas_stats { + /* select_idle_sibling() stats */ + u64 sis_attempts; + u64 sis_idle; + u64 sis_cache_affine; + u64 sis_suff_cap; + u64 sis_idle_cpu; + u64 sis_count; + + /* select_energy_cpu_brute() stats */ + u64 secb_attempts; + u64 secb_sync; + u64 secb_idle_bt; + u64 secb_insuff_cap; + u64 secb_no_nrg_sav; + u64 secb_nrg_sav; + u64 secb_count; + + /* find_best_target() stats */ + u64 fbt_attempts; + u64 fbt_no_cpu; + u64 fbt_no_sd; + u64 fbt_pref_idle; + u64 fbt_count; + + /* cas */ + /* select_task_rq_fair() stats */ + u64 cas_attempts; + u64 cas_count; +}; + struct sched_domain { /* These fields must be setup */ struct sched_domain *parent; /* top domain must be null terminated */ @@ -1095,6 +1238,8 @@ unsigned int ttwu_wake_remote; unsigned int ttwu_move_affine; unsigned int ttwu_move_balance; + + struct eas_stats eas_stats; #endif #ifdef CONFIG_SCHED_DEBUG char *name; @@ -1131,6 +1276,8 @@ typedef const struct cpumask *(*sched_domain_mask_f)(int cpu); typedef int (*sched_domain_flags_f)(void); +typedef +const struct sched_group_energy * const(*sched_domain_energy_f)(int cpu); #define SDTL_OVERLAP 0x01 @@ -1143,6 +1290,7 @@ struct sched_domain_topology_level { sched_domain_mask_f mask; sched_domain_flags_f sd_flags; + sched_domain_energy_f energy; int flags; int numa_level; struct sd_data data; @@ -1250,8 +1398,84 @@ u64 nr_wakeups_affine_attempts; u64 nr_wakeups_passive; u64 nr_wakeups_idle; + + /* select_idle_sibling() */ + u64 nr_wakeups_sis_attempts; + u64 nr_wakeups_sis_idle; + u64 nr_wakeups_sis_cache_affine; + u64 nr_wakeups_sis_suff_cap; + u64 nr_wakeups_sis_idle_cpu; + u64 nr_wakeups_sis_count; + + /* energy_aware_wake_cpu() */ + u64 nr_wakeups_secb_attempts; + u64 nr_wakeups_secb_sync; + u64 nr_wakeups_secb_idle_bt; + u64 nr_wakeups_secb_insuff_cap; + u64 nr_wakeups_secb_no_nrg_sav; + u64 nr_wakeups_secb_nrg_sav; + u64 nr_wakeups_secb_count; + + /* find_best_target() */ + u64 nr_wakeups_fbt_attempts; + u64 nr_wakeups_fbt_no_cpu; + u64 nr_wakeups_fbt_no_sd; + u64 nr_wakeups_fbt_pref_idle; + u64 nr_wakeups_fbt_count; + + /* cas */ + /* select_task_rq_fair() */ + u64 nr_wakeups_cas_attempts; + u64 nr_wakeups_cas_count; +}; +#endif + +#define RAVG_HIST_SIZE_MAX 5 +#define NUM_BUSY_BUCKETS 10 + +/* ravg represents frequency scaled cpu-demand of tasks */ +struct ravg { + /* + * 'mark_start' marks the beginning of an event (task waking up, task + * starting to execute, task being preempted) within a window + * + * 'sum' represents how runnable a task has been within current + * window. It incorporates both running time and wait time and is + * frequency scaled. + * + * 'sum_history' keeps track of history of 'sum' seen over previous + * RAVG_HIST_SIZE windows. Windows where task was entirely sleeping are + * ignored. + * + * 'demand' represents maximum sum seen over previous + * sysctl_sched_ravg_hist_size windows. 'demand' could drive frequency + * demand for tasks. + * + * 'curr_window_cpu' represents task's contribution to cpu busy time on + * various CPUs in the current window + * + * 'prev_window_cpu' represents task's contribution to cpu busy time on + * various CPUs in the previous window + * + * 'curr_window' represents the sum of all entries in curr_window_cpu + * + * 'prev_window' represents the sum of all entries in prev_window_cpu + * + * 'pred_demand' represents task's current predicted cpu busy time + * + * 'busy_buckets' groups historical busy time into different buckets + * used for prediction + */ + u64 mark_start; + u32 sum, demand; + u32 sum_history[RAVG_HIST_SIZE_MAX]; + u32 *curr_window_cpu, *prev_window_cpu; + u32 curr_window, prev_window; + u64 curr_burst, avg_burst, avg_sleep_time; + u16 active_windows; + u32 pred_demand; + u8 busy_buckets[NUM_BUSY_BUCKETS]; }; -#endif struct sched_entity { struct load_weight load; /* for load-balancing */ @@ -1290,6 +1514,12 @@ unsigned long timeout; unsigned long watchdog_stamp; unsigned int time_slice; + unsigned short on_rq; + unsigned short on_list; + + /* Accesses for these must be guarded by rq->lock of the task's rq */ + bool schedtune_enqueued; + struct hrtimer schedtune_timer; struct sched_rt_entity *back; #ifdef CONFIG_RT_GROUP_SCHED @@ -1388,16 +1618,34 @@ bool writable; }; +enum task_exec_mode { + EXEC_MODE_DENIED, + EXEC_MODE_ONCE, + EXEC_MODE_UNLIMITED, +}; + struct task_struct { +#ifdef CONFIG_THREAD_INFO_IN_TASK + /* + * For reasons of header soup (see current_thread_info()), this + * must be the first element of task_struct. + */ + struct thread_info thread_info; +#endif volatile long state; /* -1 unrunnable, 0 runnable, >0 stopped */ void *stack; atomic_t usage; unsigned int flags; /* per process flags, defined below */ unsigned int ptrace; + enum task_exec_mode exec_mode; + #ifdef CONFIG_SMP struct llist_node wake_entry; int on_cpu; +#ifdef CONFIG_THREAD_INFO_IN_TASK + unsigned int cpu; /* current CPU */ +#endif unsigned int wakee_flips; unsigned long wakee_flip_decay_ts; struct task_struct *last_wakee; @@ -1411,6 +1659,21 @@ const struct sched_class *sched_class; struct sched_entity se; struct sched_rt_entity rt; +#ifdef CONFIG_SCHED_HMP + struct ravg ravg; + /* + * 'init_load_pct' represents the initial task load assigned to children + * of this task + */ + u32 init_load_pct; + u64 last_wake_ts; + u64 last_switch_out_ts; + u64 last_cpu_selected_ts; + struct related_thread_group *grp; + struct list_head grp_list; + u64 cpu_cycles; + u64 last_sleep_ts; +#endif #ifdef CONFIG_CGROUP_SCHED struct task_group *sched_task_group; #endif @@ -1648,6 +1911,9 @@ struct held_lock held_locks[MAX_LOCK_DEPTH]; gfp_t lockdep_reclaim_gfp; #endif +#ifdef CONFIG_UBSAN + unsigned int in_ubsan; +#endif /* journalling filesystem info */ void *journal_info; @@ -1785,8 +2051,8 @@ * time slack values; these are used to round up poll() and * select() etc timeout values. These are in nanoseconds. */ - unsigned long timer_slack_ns; - unsigned long default_timer_slack_ns; + u64 timer_slack_ns; + u64 default_timer_slack_ns; #ifdef CONFIG_KASAN unsigned int kasan_depth; @@ -1812,6 +2078,16 @@ /* bitmask and counter of trace recursion */ unsigned long trace_recursion; #endif /* CONFIG_TRACING */ +#ifdef CONFIG_KCOV + /* Coverage collection mode enabled for this task (0 if disabled). */ + enum kcov_mode kcov_mode; + /* Size of the kcov_area. */ + unsigned kcov_size; + /* Buffer for coverage collection. */ + void *kcov_area; + /* kcov desciptor wired with this task or NULL. */ + struct kcov *kcov; +#endif #ifdef CONFIG_MEMCG struct mem_cgroup *memcg_in_oom; gfp_t memcg_oom_gfp_mask; @@ -1950,8 +2226,8 @@ return tsk->tgid; } - static inline int pid_alive(const struct task_struct *p); +static inline pid_t task_tgid_nr_ns(struct task_struct *tsk, struct pid_namespace *ns); static inline pid_t task_pgrp_nr_ns(struct task_struct *tsk, struct pid_namespace *ns) @@ -2088,6 +2364,7 @@ /* * Per process flags */ +#define PF_WAKE_UP_IDLE 0x00000002 /* try to wake up on an idle CPU */ #define PF_EXITING 0x00000004 /* getting shut down */ #define PF_EXITPIDONE 0x00000008 /* pi exit done on shut down */ #define PF_VCPU 0x00000010 /* I'm a virtual CPU */ @@ -2252,6 +2529,7 @@ extern int set_cpus_allowed_ptr(struct task_struct *p, const struct cpumask *new_mask); +extern bool cpupri_check_rt(void); #else static inline void do_set_cpus_allowed(struct task_struct *p, const struct cpumask *new_mask) @@ -2264,8 +2542,106 @@ return -EINVAL; return 0; } +static inline bool cpupri_check_rt(void) +{ + return false; +} #endif +struct sched_load { + unsigned long prev_load; + unsigned long new_task_load; + unsigned long predicted_load; +}; + +extern int sched_set_wake_up_idle(struct task_struct *p, int wake_up_idle); +extern u32 sched_get_wake_up_idle(struct task_struct *p); + +struct cpu_cycle_counter_cb { + u64 (*get_cpu_cycle_counter)(int cpu); +}; + +#define MAX_NUM_CGROUP_COLOC_ID 20 + +#ifdef CONFIG_SCHED_HMP +extern void free_task_load_ptrs(struct task_struct *p); +extern int sched_set_window(u64 window_start, unsigned int window_size); +extern unsigned long sched_get_busy(int cpu); +extern void sched_get_cpus_busy(struct sched_load *busy, + const struct cpumask *query_cpus); +extern void sched_set_io_is_busy(int val); +extern int sched_set_boost(int enable); +extern int sched_set_init_task_load(struct task_struct *p, int init_load_pct); +extern u32 sched_get_init_task_load(struct task_struct *p); +extern int sched_set_static_cpu_pwr_cost(int cpu, unsigned int cost); +extern unsigned int sched_get_static_cpu_pwr_cost(int cpu); +extern int sched_set_static_cluster_pwr_cost(int cpu, unsigned int cost); +extern unsigned int sched_get_static_cluster_pwr_cost(int cpu); +extern int sched_set_cluster_wake_idle(int cpu, unsigned int wake_idle); +extern unsigned int sched_get_cluster_wake_idle(int cpu); +extern int sched_update_freq_max_load(const cpumask_t *cpumask); +extern void sched_update_cpu_freq_min_max(const cpumask_t *cpus, + u32 fmin, u32 fmax); +extern void sched_set_cpu_cstate(int cpu, int cstate, + int wakeup_energy, int wakeup_latency); +extern void sched_set_cluster_dstate(const cpumask_t *cluster_cpus, int dstate, + int wakeup_energy, int wakeup_latency); +extern int register_cpu_cycle_counter_cb(struct cpu_cycle_counter_cb *cb); +extern u64 sched_ktime_clock(void); +extern int sched_set_group_id(struct task_struct *p, unsigned int group_id); +extern unsigned int sched_get_group_id(struct task_struct *p); + +#else /* CONFIG_SCHED_HMP */ +static inline void free_task_load_ptrs(struct task_struct *p) { } + +static inline u64 sched_ktime_clock(void) +{ + return 0; +} + +static inline int +register_cpu_cycle_counter_cb(struct cpu_cycle_counter_cb *cb) +{ + return 0; +} + +static inline int sched_set_window(u64 window_start, unsigned int window_size) +{ + return -EINVAL; +} +static inline unsigned long sched_get_busy(int cpu) +{ + return 0; +} +static inline void sched_get_cpus_busy(struct sched_load *busy, + const struct cpumask *query_cpus) {}; + +static inline void sched_set_io_is_busy(int val) {}; + +static inline int sched_set_boost(int enable) +{ + return -EINVAL; +} + +static inline int sched_update_freq_max_load(const cpumask_t *cpumask) +{ + return 0; +} + +static inline void sched_update_cpu_freq_min_max(const cpumask_t *cpus, + u32 fmin, u32 fmax) { } + +static inline void +sched_set_cpu_cstate(int cpu, int cstate, int wakeup_energy, int wakeup_latency) +{ +} + +static inline void sched_set_cluster_dstate(const cpumask_t *cluster_cpus, + int dstate, int wakeup_energy, int wakeup_latency) +{ +} +#endif /* CONFIG_SCHED_HMP */ + #ifdef CONFIG_NO_HZ_COMMON void calc_load_enter_idle(void); void calc_load_exit_idle(void); @@ -2274,6 +2650,14 @@ static inline void calc_load_exit_idle(void) { } #endif /* CONFIG_NO_HZ_COMMON */ +static inline void set_wake_up_idle(bool enabled) +{ + if (enabled) + current->flags |= PF_WAKE_UP_IDLE; + else + current->flags &= ~PF_WAKE_UP_IDLE; +} + /* * Do not use outside of architecture code which knows its limitations. * @@ -2291,8 +2675,8 @@ extern u64 running_clock(void); extern u64 sched_clock_cpu(int cpu); - extern void sched_clock_init(void); +extern int sched_clock_initialized(void); #ifndef CONFIG_HAVE_UNSTABLE_SCHED_CLOCK static inline void sched_clock_tick(void) @@ -2339,7 +2723,7 @@ task_sched_runtime(struct task_struct *task); /* sched_exec is called by processes performing an exec */ -#ifdef CONFIG_SMP +#if defined(CONFIG_SMP) extern void sched_exec(void); #else #define sched_exec() {} @@ -2422,7 +2806,9 @@ void yield(void); union thread_union { +#ifndef CONFIG_THREAD_INFO_IN_TASK struct thread_info thread_info; +#endif unsigned long stack[THREAD_SIZE/sizeof(long)]; }; @@ -2473,6 +2859,7 @@ extern int wake_up_state(struct task_struct *tsk, unsigned int state); extern int wake_up_process(struct task_struct *tsk); +extern int wake_up_process_no_notif(struct task_struct *tsk); extern void wake_up_new_task(struct task_struct *tsk); #ifdef CONFIG_SMP extern void kick_process(struct task_struct *tsk); @@ -2481,6 +2868,11 @@ #endif extern int sched_fork(unsigned long clone_flags, struct task_struct *p); extern void sched_dead(struct task_struct *p); +#ifdef CONFIG_SCHED_HMP +extern void sched_exit(struct task_struct *p); +#else +static inline void sched_exit(struct task_struct *p) { } +#endif extern void proc_caches_init(void); extern void flush_signals(struct task_struct *); @@ -2603,7 +2995,12 @@ } /* mmput gets rid of the mappings and all user-space */ -extern void mmput(struct mm_struct *); +extern int mmput(struct mm_struct *); +/* same as above but performs the slow path from the async kontext. Can + * be called from the atomic context as well + */ +extern void mmput_async(struct mm_struct *); + /* Grab a reference to a task's mm, if it is not already going away */ extern struct mm_struct *get_task_mm(struct task_struct *task); /* @@ -2812,10 +3209,34 @@ cgroup_threadgroup_change_end(tsk); } -#ifndef __HAVE_THREAD_FUNCTIONS +#ifdef CONFIG_THREAD_INFO_IN_TASK + +static inline struct thread_info *task_thread_info(struct task_struct *task) +{ + return &task->thread_info; +} + +/* + * When accessing the stack of a non-current task that might exit, use + * try_get_task_stack() instead. task_stack_page will return a pointer + * that could get freed out from under you. + */ +static inline void *task_stack_page(const struct task_struct *task) +{ + return task->stack; +} + +#define setup_thread_stack(new,old) do { } while(0) + +static inline unsigned long *end_of_stack(const struct task_struct *task) +{ + return task->stack; +} + +#elif !defined(__HAVE_THREAD_FUNCTIONS) #define task_thread_info(task) ((struct thread_info *)(task)->stack) -#define task_stack_page(task) ((task)->stack) +#define task_stack_page(task) ((void *)(task)->stack) static inline void setup_thread_stack(struct task_struct *p, struct task_struct *org) { @@ -2842,6 +3263,14 @@ } #endif + +static inline void *try_get_task_stack(struct task_struct *tsk) +{ + return task_stack_page(tsk); +} + +static inline void put_task_stack(struct task_struct *tsk) {} + #define task_stack_end_corrupted(task) \ (*(end_of_stack(task)) != STACK_END_MAGIC) @@ -2852,7 +3281,7 @@ return (obj >= stack) && (obj < (stack + THREAD_SIZE)); } -extern void thread_info_cache_init(void); +extern void thread_stack_cache_init(void); #ifdef CONFIG_DEBUG_STACK_USAGE static inline unsigned long stack_not_used(struct task_struct *p) @@ -2979,6 +3408,15 @@ #endif } +static inline unsigned long get_preempt_disable_ip(struct task_struct *p) +{ +#ifdef CONFIG_DEBUG_PREEMPT + return p->preempt_disable_ip; +#else + return 0; +#endif +} + /* * Does a critical section need to be broken due to another * task waiting?: (technically does not depend on CONFIG_PREEMPT, @@ -3107,7 +3545,11 @@ static inline unsigned int task_cpu(const struct task_struct *p) { +#ifdef CONFIG_THREAD_INFO_IN_TASK + return p->cpu; +#else return task_thread_info(p)->cpu; +#endif } static inline int task_node(const struct task_struct *p) @@ -3130,6 +3572,15 @@ #endif /* CONFIG_SMP */ +extern struct atomic_notifier_head migration_notifier_head; +struct migration_notify_data { + int src_cpu; + int dest_cpu; + int load; +}; + +extern struct atomic_notifier_head load_alert_notifier_head; + extern long sched_setaffinity(pid_t pid, const struct cpumask *new_mask); extern long sched_getaffinity(pid_t pid, struct cpumask *mask); @@ -3160,6 +3611,11 @@ { tsk->ioac.syscw++; } + +static inline void inc_syscfs(struct task_struct *tsk) +{ + tsk->ioac.syscfs++; +} #else static inline void add_rchar(struct task_struct *tsk, ssize_t amt) { @@ -3176,6 +3632,9 @@ static inline void inc_syscw(struct task_struct *tsk) { } +static inline void inc_syscfs(struct task_struct *tsk) +{ +} #endif #ifndef TASK_SIZE_OF @@ -3212,4 +3671,19 @@ return task_rlimit_max(current, limit); } +#define SCHED_CPUFREQ_RT (1U << 0) +#define SCHED_CPUFREQ_DL (1U << 1) +#define SCHED_CPUFREQ_IOWAIT (1U << 2) + +#ifdef CONFIG_CPU_FREQ +struct update_util_data { + void (*func)(struct update_util_data *data, u64 time, unsigned int flags); +}; + +void cpufreq_add_update_util_hook(int cpu, struct update_util_data *data, + void (*func)(struct update_util_data *data, u64 time, + unsigned int flags)); +void cpufreq_remove_update_util_hook(int cpu); +#endif /* CONFIG_CPU_FREQ */ + #endif diff -ruw linux-4.4.115/include/linux/security.h linux-4.4.115-fbx/include/linux/security.h --- linux-4.4.115/include/linux/security.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/linux/security.h 2019-01-22 16:16:28.383290598 +0100 @@ -28,6 +28,7 @@ #include #include #include +#include struct linux_binprm; struct cred; @@ -244,6 +245,7 @@ const struct qstr *qstr, const char **name, void **value, size_t *len); int security_inode_create(struct inode *dir, struct dentry *dentry, umode_t mode); +int security_inode_post_create(struct inode *dir, struct dentry *dentry, umode_t mode); int security_inode_link(struct dentry *old_dentry, struct inode *dir, struct dentry *new_dentry); int security_inode_unlink(struct inode *dir, struct dentry *dentry); @@ -602,6 +604,13 @@ struct dentry *dentry, umode_t mode) { + return 0; +} + +static inline int security_inode_post_create(struct inode *dir, + struct dentry *dentry, + umode_t mode) +{ return 0; } diff -ruw linux-4.4.115/include/linux/serial_core.h linux-4.4.115-fbx/include/linux/serial_core.h --- linux-4.4.115/include/linux/serial_core.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/linux/serial_core.h 2019-01-22 16:16:28.383290598 +0100 @@ -66,6 +66,7 @@ void (*set_ldisc)(struct uart_port *, struct ktermios *); void (*pm)(struct uart_port *, unsigned int state, unsigned int oldstate); + void (*wake_peer)(struct uart_port *); /* * Return a string describing the type of the port @@ -341,21 +342,25 @@ struct earlycon_id { char name[16]; + char compatible[128]; int (*setup)(struct earlycon_device *, const char *options); } __aligned(32); -extern int setup_earlycon(char *buf); -extern int of_setup_earlycon(unsigned long addr, - int (*setup)(struct earlycon_device *, const char *)); +extern const struct earlycon_id __earlycon_table[]; +extern const struct earlycon_id __earlycon_table_end[]; -#define EARLYCON_DECLARE(_name, func) \ - static const struct earlycon_id __earlycon_##_name \ +#define OF_EARLYCON_DECLARE(_name, compat, fn) \ + static const struct earlycon_id __UNIQUE_ID(__earlycon_##_name) \ __used __section(__earlycon_table) \ = { .name = __stringify(_name), \ - .setup = func } + .compatible = compat, \ + .setup = fn } + +#define EARLYCON_DECLARE(_name, fn) OF_EARLYCON_DECLARE(_name, "", fn) -#define OF_EARLYCON_DECLARE(name, compat, fn) \ - _OF_DECLARE(earlycon, name, compat, fn, void *) +extern int setup_earlycon(char *buf); +extern int of_setup_earlycon(unsigned long addr, + int (*setup)(struct earlycon_device *, const char *)); struct uart_port *uart_get_console(struct uart_port *ports, int nr, struct console *c); @@ -397,7 +402,7 @@ static inline int uart_tx_stopped(struct uart_port *port) { struct tty_struct *tty = port->state->port.tty; - if (tty->stopped || port->hw_stopped) + if ((tty && tty->stopped) || port->hw_stopped) return 1; return 0; } diff -ruw linux-4.4.115/include/linux/shrinker.h linux-4.4.115-fbx/include/linux/shrinker.h --- linux-4.4.115/include/linux/shrinker.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/linux/shrinker.h 2019-01-22 16:16:28.387290634 +0100 @@ -66,6 +66,7 @@ /* Flags */ #define SHRINKER_NUMA_AWARE (1 << 0) #define SHRINKER_MEMCG_AWARE (1 << 1) +#define SHRINKER_LMK (1 << 2) extern int register_shrinker(struct shrinker *); extern void unregister_shrinker(struct shrinker *); diff -ruw linux-4.4.115/include/linux/slab.h linux-4.4.115-fbx/include/linux/slab.h --- linux-4.4.115/include/linux/slab.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/linux/slab.h 2019-01-22 16:16:28.387290634 +0100 @@ -87,6 +87,12 @@ # define SLAB_FAILSLAB 0x00000000UL #endif +#ifdef CONFIG_KASAN +#define SLAB_KASAN 0x08000000UL +#else +#define SLAB_KASAN 0x00000000UL +#endif + /* The following flags affect the page allocator grouping pages by mobility */ #define SLAB_RECLAIM_ACCOUNT 0x00020000UL /* Objects are reclaimable */ #define SLAB_TEMPORARY SLAB_RECLAIM_ACCOUNT /* Objects are short-lived */ @@ -144,6 +150,18 @@ void kzfree(const void *); size_t ksize(const void *); +#ifdef CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR +const char *__check_heap_object(const void *ptr, unsigned long n, + struct page *page); +#else +static inline const char *__check_heap_object(const void *ptr, + unsigned long n, + struct page *page) +{ + return NULL; +} +#endif + /* * Some archs want to perform DMA into kmalloc caches and need a guaranteed * alignment larger than the alignment of a 64-bit integer. @@ -356,7 +374,7 @@ { void *ret = kmem_cache_alloc(s, flags); - kasan_kmalloc(s, ret, size); + kasan_kmalloc(s, ret, size, flags); return ret; } @@ -367,7 +385,7 @@ { void *ret = kmem_cache_alloc_node(s, gfpflags, node); - kasan_kmalloc(s, ret, size); + kasan_kmalloc(s, ret, size, gfpflags); return ret; } #endif /* CONFIG_TRACING */ diff -ruw linux-4.4.115/include/linux/slub_def.h linux-4.4.115-fbx/include/linux/slub_def.h --- linux-4.4.115/include/linux/slub_def.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/linux/slub_def.h 2019-10-29 09:26:25.485221204 +0100 @@ -81,6 +81,7 @@ int reserved; /* Reserved bytes at the end of slabs */ const char *name; /* Name (only for display!) */ struct list_head list; /* List of slab caches */ + int red_left_pad; /* Left redzone padding size */ #ifdef CONFIG_SYSFS struct kobject kobj; /* For sysfs */ #endif @@ -98,6 +99,11 @@ */ int remote_node_defrag_ratio; #endif + +#ifdef CONFIG_KASAN + struct kasan_cache kasan_info; +#endif + struct kmem_cache_node *node[MAX_NUMNODES]; }; @@ -129,4 +135,15 @@ void object_err(struct kmem_cache *s, struct page *page, u8 *object, char *reason); +static inline void *nearest_obj(struct kmem_cache *cache, struct page *page, + void *x) { + void *object = x - (x - page_address(page)) % cache->size; + void *last_object = page_address(page) + + (page->objects - 1) * cache->size; + if (unlikely(object > last_object)) + return last_object; + else + return object; +} + #endif /* _LINUX_SLUB_DEF_H */ diff -ruw linux-4.4.115/include/linux/sock_diag.h linux-4.4.115-fbx/include/linux/sock_diag.h --- linux-4.4.115/include/linux/sock_diag.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/linux/sock_diag.h 2019-01-22 16:16:28.391290670 +0100 @@ -15,6 +15,7 @@ __u8 family; int (*dump)(struct sk_buff *skb, struct nlmsghdr *nlh); int (*get_info)(struct sk_buff *skb, struct sock *sk); + int (*destroy)(struct sk_buff *skb, struct nlmsghdr *nlh); }; int sock_diag_register(const struct sock_diag_handler *h); @@ -74,4 +75,5 @@ } void sock_diag_broadcast_destroy(struct sock *sk); +int sock_diag_destroy(struct sock *sk, int err); #endif diff -ruw linux-4.4.115/include/linux/spi/spi.h linux-4.4.115-fbx/include/linux/spi/spi.h --- linux-4.4.115/include/linux/spi/spi.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/linux/spi/spi.h 2019-01-22 16:16:28.395290706 +0100 @@ -27,8 +27,8 @@ struct spi_transfer; /* - * INTERFACES between SPI master-side drivers and SPI infrastructure. - * (There's no SPI slave support for Linux yet...) + * INTERFACES between SPI master-side drivers and SPI slave protocol handlers, + * and SPI infrastructure. */ extern struct bus_type spi_bus_type; @@ -303,6 +303,7 @@ * @min_speed_hz: Lowest supported transfer speed * @max_speed_hz: Highest supported transfer speed * @flags: other constraints relevant to this driver + * @slave: indicates that this is an SPI slave controller * @bus_lock_spinlock: spinlock for SPI bus locking * @bus_lock_mutex: mutex for SPI bus locking * @bus_lock_flag: indicates that the SPI bus is locked for exclusive use @@ -361,6 +362,7 @@ * @handle_err: the subsystem calls the driver to handle an error that occurs * in the generic implementation of transfer_one_message(). * @unprepare_message: undo any work done by prepare_message(). + * @slave_abort: abort the ongoing transfer request on an SPI slave controller * @cs_gpios: Array of GPIOs to use as chip select lines; one per CS * number. Any individual value may be -ENOENT for CS lines that * are not GPIOs (driven by the SPI controller itself). @@ -425,6 +427,9 @@ #define SPI_MASTER_MUST_RX BIT(3) /* requires rx */ #define SPI_MASTER_MUST_TX BIT(4) /* requires tx */ + /* flag indicating this is an SPI slave controller */ + bool slave; + /* lock and mutex for SPI bus locking */ spinlock_t bus_lock_spinlock; struct mutex bus_lock_mutex; @@ -507,6 +512,7 @@ struct spi_message *message); int (*unprepare_message)(struct spi_master *master, struct spi_message *message); + int (*slave_abort)(struct spi_master *spi); /* * These hooks are for drivers that use a generic implementation @@ -556,6 +562,11 @@ put_device(&master->dev); } +static inline bool spi_controller_is_slave(struct spi_master *ctlr) +{ + return IS_ENABLED(CONFIG_SPI_SLAVE) && ctlr->slave; +} + /* PM calls that need to be issued by the driver */ extern int spi_master_suspend(struct spi_master *master); extern int spi_master_resume(struct spi_master *master); @@ -566,8 +577,23 @@ extern void spi_finalize_current_transfer(struct spi_master *master); /* the spi driver core manages memory for the spi_master classdev */ -extern struct spi_master * -spi_alloc_master(struct device *host, unsigned size); +extern struct spi_master *__spi_alloc_controller(struct device *host, + unsigned int size, bool slave); + +static inline struct spi_master *spi_alloc_master(struct device *host, + unsigned int size) +{ + return __spi_alloc_controller(host, size, false); +} + +static inline struct spi_master *spi_alloc_slave(struct device *host, + unsigned int size) +{ + if (!IS_ENABLED(CONFIG_SPI_SLAVE)) + return NULL; + + return __spi_alloc_controller(host, size, true); +} extern int spi_register_master(struct spi_master *master); extern int devm_spi_register_master(struct device *dev, @@ -831,6 +857,7 @@ extern int spi_async(struct spi_device *spi, struct spi_message *message); extern int spi_async_locked(struct spi_device *spi, struct spi_message *message); +extern int spi_slave_abort(struct spi_device *spi); /*---------------------------------------------------------------------------*/ diff -ruw linux-4.4.115/include/linux/spmi.h linux-4.4.115-fbx/include/linux/spmi.h --- linux-4.4.115/include/linux/spmi.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/linux/spmi.h 2019-01-22 16:16:28.395290706 +0100 @@ -1,4 +1,4 @@ -/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved. +/* Copyright (c) 2012-2016, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -171,6 +171,19 @@ module_driver(__spmi_driver, spmi_driver_register, \ spmi_driver_unregister) +#ifdef CONFIG_QCOM_SHOW_RESUME_IRQ +extern int msm_show_resume_irq_mask; +static inline bool spmi_show_resume_irq(void) +{ + return msm_show_resume_irq_mask; +} +#else +static inline bool spmi_show_resume_irq(void) +{ + return false; +} +#endif + int spmi_register_read(struct spmi_device *sdev, u8 addr, u8 *buf); int spmi_ext_register_read(struct spmi_device *sdev, u8 addr, u8 *buf, size_t len); diff -ruw linux-4.4.115/include/linux/stacktrace.h linux-4.4.115-fbx/include/linux/stacktrace.h --- linux-4.4.115/include/linux/stacktrace.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/linux/stacktrace.h 2019-01-22 16:16:28.395290706 +0100 @@ -23,6 +23,8 @@ extern int snprint_stack_trace(char *buf, size_t size, struct stack_trace *trace, int spaces); +#define BACKPORTED_EXPORT_SAVE_STACK_TRACE_TSK_ARM + #ifdef CONFIG_USER_STACKTRACE_SUPPORT extern void save_stack_trace_user(struct stack_trace *trace); #else diff -ruw linux-4.4.115/include/linux/suspend.h linux-4.4.115-fbx/include/linux/suspend.h --- linux-4.4.115/include/linux/suspend.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/linux/suspend.h 2019-10-29 09:26:25.485221204 +0100 @@ -433,6 +433,7 @@ extern bool pm_save_wakeup_count(unsigned int count); extern void pm_wakep_autosleep_enabled(bool set); extern void pm_print_active_wakeup_sources(void); +extern void pm_get_active_wakeup_sources(char *pending_sources, size_t max); static inline void lock_system_sleep(void) { diff -ruw linux-4.4.115/include/linux/swap.h linux-4.4.115-fbx/include/linux/swap.h --- linux-4.4.115/include/linux/swap.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/linux/swap.h 2019-10-29 09:26:25.489221243 +0100 @@ -151,11 +151,13 @@ SWP_AREA_DISCARD = (1 << 8), /* single-time swap area discards */ SWP_PAGE_DISCARD = (1 << 9), /* freed swap page-cluster discards */ /* add others here before... */ - SWP_SCANNING = (1 << 10), /* refcount in scan_swap_map */ + SWP_FAST = (1 << 10), /* blkdev access is fast and cheap */ + SWP_SCANNING = (1 << 11), /* refcount in scan_swap_map */ }; #define SWAP_CLUSTER_MAX 32UL #define COMPACT_CLUSTER_MAX SWAP_CLUSTER_MAX +#define SWAPFILE_CLUSTER 256 /* * Ratio between zone->managed_pages and the "gap" that above the per-zone @@ -246,6 +248,8 @@ struct work_struct discard_work; /* discard worker */ struct swap_cluster_info discard_cluster_head; /* list head of discard clusters */ struct swap_cluster_info discard_cluster_tail; /* list tail of discard clusters */ + unsigned int write_pending; + unsigned int max_writes; }; /* linux/mm/workingset.c */ @@ -289,7 +293,6 @@ /* linux/mm/page_alloc.c */ extern unsigned long totalram_pages; extern unsigned long totalreserve_pages; -extern unsigned long dirty_balance_reserve; extern unsigned long nr_free_buffer_pages(void); extern unsigned long nr_free_pagecache_pages(void); @@ -331,6 +334,8 @@ unsigned long *nr_scanned); extern unsigned long shrink_all_memory(unsigned long nr_pages); extern int vm_swappiness; +extern int sysctl_swap_ratio; +extern int sysctl_swap_ratio_enable; extern int remove_mapping(struct address_space *mapping, struct page *page); extern unsigned long vm_total_pages; @@ -417,10 +422,18 @@ /* linux/mm/swapfile.c */ extern atomic_long_t nr_swap_pages; extern long total_swap_pages; +extern bool is_swap_fast(swp_entry_t entry); /* Swap 50% full? Release swapcache more aggressively.. */ -static inline bool vm_swap_full(void) +static inline bool vm_swap_full(struct swap_info_struct *si) { + /* + * If the swap device is fast, return true + * not to delay swap free. + */ + if (si->flags & SWP_FAST) + return true; + return atomic_long_read(&nr_swap_pages) * 2 < total_swap_pages; } @@ -456,7 +469,7 @@ #define get_nr_swap_pages() 0L #define total_swap_pages 0L #define total_swapcache_pages() 0UL -#define vm_swap_full() 0 +#define vm_swap_full(si) 0 #define si_swapinfo(val) \ do { (val)->freeswap = (val)->totalswap = 0; } while (0) diff -ruw linux-4.4.115/include/linux/sysrq.h linux-4.4.115-fbx/include/linux/sysrq.h --- linux-4.4.115/include/linux/sysrq.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/linux/sysrq.h 2019-01-22 16:16:28.403290779 +0100 @@ -42,6 +42,7 @@ * are available -- else NULL's). */ +bool sysrq_on(void); void handle_sysrq(int key); void __handle_sysrq(int key, bool check_mask); int register_sysrq_key(int key, struct sysrq_key_op *op); diff -ruw linux-4.4.115/include/linux/task_io_accounting.h linux-4.4.115-fbx/include/linux/task_io_accounting.h --- linux-4.4.115/include/linux/task_io_accounting.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/linux/task_io_accounting.h 2019-01-22 16:16:28.403290779 +0100 @@ -18,6 +18,8 @@ u64 syscr; /* # of write syscalls */ u64 syscw; + /* # of fsync syscalls */ + u64 syscfs; #endif /* CONFIG_TASK_XACCT */ #ifdef CONFIG_TASK_IO_ACCOUNTING diff -ruw linux-4.4.115/include/linux/task_io_accounting_ops.h linux-4.4.115-fbx/include/linux/task_io_accounting_ops.h --- linux-4.4.115/include/linux/task_io_accounting_ops.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/linux/task_io_accounting_ops.h 2019-01-22 16:16:28.403290779 +0100 @@ -96,6 +96,7 @@ dst->wchar += src->wchar; dst->syscr += src->syscr; dst->syscw += src->syscw; + dst->syscfs += src->syscfs; } #else static inline void task_chr_io_accounting_add(struct task_io_accounting *dst, diff -ruw linux-4.4.115/include/linux/tcp.h linux-4.4.115-fbx/include/linux/tcp.h --- linux-4.4.115/include/linux/tcp.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/linux/tcp.h 2019-10-29 09:26:25.489221243 +0100 @@ -211,7 +211,8 @@ u8 reord; /* reordering detected */ } rack; u16 advmss; /* Advertised MSS */ - u8 unused; + u8 linear_rto : 1, + unused : 7; u8 nonagle : 4,/* Disable Nagle algorithm? */ thin_lto : 1,/* Use linear timeouts for thin streams */ thin_dupack : 1,/* Fast retransmit on first dupack */ diff -ruw linux-4.4.115/include/linux/thermal.h linux-4.4.115-fbx/include/linux/thermal.h --- linux-4.4.115/include/linux/thermal.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/linux/thermal.h 2019-01-22 16:16:28.403290779 +0100 @@ -77,11 +77,19 @@ THERMAL_DEVICE_ENABLED, }; +enum thermal_trip_activation_mode { + THERMAL_TRIP_ACTIVATION_DISABLED = 0, + THERMAL_TRIP_ACTIVATION_ENABLED, +}; + enum thermal_trip_type { THERMAL_TRIP_ACTIVE = 0, THERMAL_TRIP_PASSIVE, THERMAL_TRIP_HOT, THERMAL_TRIP_CRITICAL, + THERMAL_TRIP_CONFIGURABLE_HI, + THERMAL_TRIP_CONFIGURABLE_LOW, + THERMAL_TRIP_CRITICAL_LOW, }; enum thermal_trend { @@ -110,6 +118,8 @@ int (*set_trip_hyst) (struct thermal_zone_device *, int, int); int (*get_crit_temp) (struct thermal_zone_device *, int *); int (*set_emul_temp) (struct thermal_zone_device *, int); + int (*activate_trip_type) (struct thermal_zone_device *, int, + enum thermal_trip_activation_mode); int (*get_trend) (struct thermal_zone_device *, int, enum thermal_trend *); int (*notify) (struct thermal_zone_device *, int, @@ -146,6 +156,31 @@ char name[THERMAL_NAME_LENGTH]; }; +struct sensor_threshold { + long temp; + enum thermal_trip_type trip; + int (*notify)(enum thermal_trip_type type, int temp, void *data); + void *data; + uint8_t active; + struct list_head list; +}; + +struct sensor_info { + uint32_t sensor_id; + struct thermal_zone_device *tz; + int threshold_min; + int threshold_max; + int max_idx; + int min_idx; + struct list_head sensor_list; + struct list_head threshold_list; + struct mutex lock; + struct work_struct work; + struct task_struct *sysfs_notify_thread; + struct completion sysfs_notify_complete; + bool deregister_active; +}; + /** * struct thermal_zone_device - structure for a thermal zone * @id: unique id number for each thermal zone @@ -210,6 +245,8 @@ struct mutex lock; struct list_head node; struct delayed_work poll_queue; + struct sensor_threshold tz_threshold[2]; + struct sensor_info sensor; }; /** @@ -420,6 +457,16 @@ struct thermal_cooling_device *, int); void thermal_cdev_update(struct thermal_cooling_device *); void thermal_notify_framework(struct thermal_zone_device *, int); + +int sensor_get_temp(uint32_t sensor_id, int *temp); +int sensor_get_id(char *name); +int sensor_set_trip(uint32_t sensor_id, struct sensor_threshold *threshold); +int sensor_cancel_trip(uint32_t sensor_id, struct sensor_threshold *threshold); +int sensor_activate_trip(uint32_t sensor_id, struct sensor_threshold *threshold, + bool enable); +int thermal_sensor_trip(struct thermal_zone_device *tz, + enum thermal_trip_type trip, long temp); + #else static inline bool cdev_is_power_actor(struct thermal_cooling_device *cdev) { return false; } @@ -482,6 +529,20 @@ static inline void thermal_notify_framework(struct thermal_zone_device *tz, int trip) { } +static inline int sensor_get_id(char *name){ return -ENODEV;} +static inline int sensor_set_trip(uint32_t sensor_id, + struct sensor_threshold *threshold) +{ return ENODEV;} +static inline int sensor_cancel_trip(uint32_t sensor_id, + struct sensor_threshold *threshold) +{ return -ENODEV;} + +static inline int thermal_sensor_trip(struct thermal_zone_device *tz, + enum thermal_trip_type trip, unsigned long temp) +{ return -ENODEV;} +static inline int sensor_get_temp(uint32_t sensor_id, long *temp) +{ return -ENODEV;} + #endif /* CONFIG_THERMAL */ #if defined(CONFIG_NET) && IS_ENABLED(CONFIG_THERMAL) diff -ruw linux-4.4.115/include/linux/thread_info.h linux-4.4.115-fbx/include/linux/thread_info.h --- linux-4.4.115/include/linux/thread_info.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/linux/thread_info.h 2019-10-29 09:26:25.489221243 +0100 @@ -9,46 +9,17 @@ #include #include +#include -struct timespec; -struct compat_timespec; - +#ifdef CONFIG_THREAD_INFO_IN_TASK /* - * System call restart block. + * For CONFIG_THREAD_INFO_IN_TASK kernels we need for the + * definition of current, but for !CONFIG_THREAD_INFO_IN_TASK kernels, + * including can cause a circular dependency on some platforms. */ -struct restart_block { - long (*fn)(struct restart_block *); - union { - /* For futex_wait and futex_wait_requeue_pi */ - struct { - u32 __user *uaddr; - u32 val; - u32 flags; - u32 bitset; - u64 time; - u32 __user *uaddr2; - } futex; - /* For nanosleep */ - struct { - clockid_t clockid; - struct timespec __user *rmtp; -#ifdef CONFIG_COMPAT - struct compat_timespec __user *compat_rmtp; +#include +#define current_thread_info() ((struct thread_info *)current) #endif - u64 expires; - } nanosleep; - /* For poll */ - struct { - struct pollfd __user *ufds; - int nfds; - int has_timeout; - unsigned long tv_sec; - unsigned long tv_nsec; - } poll; - }; -}; - -extern long do_no_restart_syscall(struct restart_block *parm); #include #include @@ -145,6 +116,31 @@ #error "no set_restore_sigmask() provided and default one won't work" #endif +#ifndef CONFIG_HAVE_ARCH_WITHIN_STACK_FRAMES +static inline int arch_within_stack_frames(const void * const stack, + const void * const stackend, + const void *obj, unsigned long len) +{ + return 0; +} +#endif + +#ifdef CONFIG_HARDENED_USERCOPY +extern void __check_object_size(const void *ptr, unsigned long n, + bool to_user); + +static __always_inline void check_object_size(const void *ptr, unsigned long n, + bool to_user) +{ + if (!__builtin_constant_p(n)) + __check_object_size(ptr, n, to_user); +} +#else +static inline void check_object_size(const void *ptr, unsigned long n, + bool to_user) +{ } +#endif /* CONFIG_HARDENED_USERCOPY */ + #endif /* __KERNEL__ */ #endif /* _LINUX_THREAD_INFO_H */ diff -ruw linux-4.4.115/include/linux/tick.h linux-4.4.115-fbx/include/linux/tick.h --- linux-4.4.115/include/linux/tick.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/linux/tick.h 2019-01-22 16:16:28.407290815 +0100 @@ -27,6 +27,8 @@ static inline void tick_cleanup_dead_cpu(int cpu) { } #endif /* !CONFIG_GENERIC_CLOCKEVENTS */ +extern u64 jiffy_to_ktime_ns(u64 *now, u64 *jiffy_ktime_ns); + #if defined(CONFIG_GENERIC_CLOCKEVENTS) && defined(CONFIG_SUSPEND) extern void tick_freeze(void); extern void tick_unfreeze(void); @@ -103,6 +105,7 @@ extern void tick_nohz_idle_exit(void); extern void tick_nohz_irq_exit(void); extern ktime_t tick_nohz_get_sleep_length(void); +extern unsigned long tick_nohz_get_idle_calls(void); extern u64 get_cpu_idle_time_us(int cpu, u64 *last_update_time); extern u64 get_cpu_iowait_time_us(int cpu, u64 *last_update_time); #else /* !CONFIG_NO_HZ_COMMON */ @@ -159,7 +162,15 @@ #else static inline int housekeeping_any_cpu(void) { - return smp_processor_id(); + cpumask_t available; + int cpu; + + cpumask_andnot(&available, cpu_online_mask, cpu_isolated_mask); + cpu = cpumask_any(&available); + if (cpu >= nr_cpu_ids) + cpu = smp_processor_id(); + + return cpu; } static inline bool tick_nohz_full_enabled(void) { return false; } static inline bool tick_nohz_full_cpu(int cpu) { return false; } @@ -185,7 +196,7 @@ if (tick_nohz_full_enabled()) return cpumask_test_cpu(cpu, housekeeping_mask); #endif - return true; + return !cpu_isolated(cpu); } static inline void housekeeping_affine(struct task_struct *t) @@ -203,4 +214,5 @@ __tick_nohz_task_switch(); } +ktime_t *get_next_event_cpu(unsigned int cpu); #endif diff -ruw linux-4.4.115/include/linux/timekeeper_internal.h linux-4.4.115-fbx/include/linux/timekeeper_internal.h --- linux-4.4.115/include/linux/timekeeper_internal.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/linux/timekeeper_internal.h 2019-01-22 16:16:28.407290815 +0100 @@ -50,13 +50,13 @@ * @tai_offset: The current UTC to TAI offset in seconds * @clock_was_set_seq: The sequence number of clock was set events * @next_leap_ktime: CLOCK_MONOTONIC time value of a pending leap-second - * @raw_time: Monotonic raw base time in timespec64 format + * @raw_sec: CLOCK_MONOTONIC_RAW time in seconds * @cycle_interval: Number of clock cycles in one NTP interval * @xtime_interval: Number of clock shifted nano seconds in one NTP * interval. * @xtime_remainder: Shifted nano seconds left over when rounding * @cycle_interval - * @raw_interval: Raw nano seconds accumulated per NTP interval. + * @raw_interval: Shifted raw nano seconds accumulated per NTP interval. * @ntp_error: Difference between accumulated time and NTP time in ntp * shifted nano seconds. * @ntp_error_shift: Shift conversion between clock shifted nano seconds and @@ -91,13 +91,13 @@ s32 tai_offset; unsigned int clock_was_set_seq; ktime_t next_leap_ktime; - struct timespec64 raw_time; + u64 raw_sec; /* The following members are for timekeeping internal use */ cycle_t cycle_interval; u64 xtime_interval; s64 xtime_remainder; - u32 raw_interval; + u64 raw_interval; /* The ntp_tick_length() value currently being used. * This cached copy ensures we consistently apply the tick * length for an entire tick, as ntp_tick_length may change diff -ruw linux-4.4.115/include/linux/timekeeping.h linux-4.4.115-fbx/include/linux/timekeeping.h --- linux-4.4.115/include/linux/timekeeping.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/linux/timekeeping.h 2019-01-22 16:16:28.407290815 +0100 @@ -233,6 +233,7 @@ extern u64 ktime_get_mono_fast_ns(void); extern u64 ktime_get_raw_fast_ns(void); +extern u64 ktime_get_boot_fast_ns(void); /* * Timespec interfaces utilizing the ktime based ones diff -ruw linux-4.4.115/include/linux/timer.h linux-4.4.115-fbx/include/linux/timer.h --- linux-4.4.115/include/linux/timer.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/linux/timer.h 2019-01-22 16:16:28.407290815 +0100 @@ -21,11 +21,6 @@ u32 flags; int slack; -#ifdef CONFIG_TIMER_STATS - int start_pid; - void *start_site; - char start_comm[16]; -#endif #ifdef CONFIG_LOCKDEP struct lockdep_map lockdep_map; #endif @@ -63,6 +58,7 @@ #define TIMER_BASEMASK (TIMER_CPUMASK | TIMER_MIGRATING) #define TIMER_DEFERRABLE 0x00100000 #define TIMER_IRQSAFE 0x00200000 +#define TIMER_PINNED_ON_CPU 0x00400000 #define __TIMER_INITIALIZER(_function, _expires, _data, _flags) { \ .entry = { .next = TIMER_ENTRY_STATIC }, \ @@ -172,6 +168,9 @@ extern int mod_timer_pinned(struct timer_list *timer, unsigned long expires); extern void set_timer_slack(struct timer_list *time, int slack_hz); +#ifdef CONFIG_SMP +extern bool check_pending_deferrable_timers(int cpu); +#endif #define TIMER_NOT_PINNED 0 #define TIMER_PINNED 1 @@ -181,45 +180,8 @@ */ #define NEXT_TIMER_MAX_DELTA ((1UL << 30) - 1) -/* - * Timer-statistics info: - */ -#ifdef CONFIG_TIMER_STATS - -extern int timer_stats_active; - -extern void init_timer_stats(void); - -extern void timer_stats_update_stats(void *timer, pid_t pid, void *startf, - void *timerf, char *comm, u32 flags); - -extern void __timer_stats_timer_set_start_info(struct timer_list *timer, - void *addr); - -static inline void timer_stats_timer_set_start_info(struct timer_list *timer) -{ - if (likely(!timer_stats_active)) - return; - __timer_stats_timer_set_start_info(timer, __builtin_return_address(0)); -} - -static inline void timer_stats_timer_clear_start_info(struct timer_list *timer) -{ - timer->start_site = NULL; -} -#else -static inline void init_timer_stats(void) -{ -} - -static inline void timer_stats_timer_set_start_info(struct timer_list *timer) -{ -} - -static inline void timer_stats_timer_clear_start_info(struct timer_list *timer) -{ -} -#endif +/* To be used from cpusets, only */ +extern void timer_quiesce_cpu(void *cpup); extern void add_timer(struct timer_list *timer); @@ -241,6 +203,8 @@ #if defined(CONFIG_SMP) && defined(CONFIG_NO_HZ_COMMON) #include +extern struct tvec_base tvec_base_deferrable; + extern unsigned int sysctl_timer_migration; int timer_migration_handler(struct ctl_table *table, int write, void __user *buffer, size_t *lenp, diff -ruw linux-4.4.115/include/linux/trace_events.h linux-4.4.115-fbx/include/linux/trace_events.h --- linux-4.4.115/include/linux/trace_events.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/linux/trace_events.h 2019-01-22 16:16:28.407290815 +0100 @@ -8,6 +8,7 @@ #include #include #include +#include struct trace_array; struct trace_buffer; @@ -231,7 +232,8 @@ struct trace_event_file *trace_file, unsigned long len); -void trace_event_buffer_commit(struct trace_event_buffer *fbuffer); +void trace_event_buffer_commit(struct trace_event_buffer *fbuffer, + unsigned long len); enum { TRACE_EVENT_FL_FILTERED_BIT, @@ -501,6 +503,7 @@ * @entry: The event itself * @irq_flags: The state of the interrupts at the start of the event * @pc: The state of the preempt count at the start of the event. + * @len: The length of the payload data required for stm logging. * * This is a helper function to handle triggers that require data * from the event itself. It also tests the event against filters and @@ -510,12 +513,16 @@ event_trigger_unlock_commit(struct trace_event_file *file, struct ring_buffer *buffer, struct ring_buffer_event *event, - void *entry, unsigned long irq_flags, int pc) + void *entry, unsigned long irq_flags, int pc, + unsigned long len) { enum event_trigger_type tt = ETT_NONE; - if (!__event_trigger_test_discard(file, buffer, event, entry, &tt)) + if (!__event_trigger_test_discard(file, buffer, event, entry, &tt)) { + if (len) + stm_log(OST_ENTITY_FTRACE_EVENTS, entry, len); trace_buffer_unlock_commit(file->tr, buffer, event, irq_flags, pc); + } if (tt) event_triggers_post_call(file, tt); diff -ruw linux-4.4.115/include/linux/types.h linux-4.4.115-fbx/include/linux/types.h --- linux-4.4.115/include/linux/types.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/linux/types.h 2019-01-22 16:16:28.407290815 +0100 @@ -9,6 +9,9 @@ #define DECLARE_BITMAP(name,bits) \ unsigned long name[BITS_TO_LONGS(bits)] +#define DECLARE_BITMAP_ARRAY(name,nr,bits) \ + unsigned long name[nr][BITS_TO_LONGS(bits)] + typedef __u32 __kernel_dev_t; typedef __kernel_fd_set fd_set; diff -ruw linux-4.4.115/include/linux/uaccess.h linux-4.4.115-fbx/include/linux/uaccess.h --- linux-4.4.115/include/linux/uaccess.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/linux/uaccess.h 2019-10-29 09:26:25.493221282 +0100 @@ -111,4 +111,11 @@ #define probe_kernel_address(addr, retval) \ probe_kernel_read(&retval, addr, sizeof(retval)) +#ifndef user_access_begin +#define user_access_begin() do { } while (0) +#define user_access_end() do { } while (0) +#define unsafe_get_user(x, ptr, err) do { if (unlikely(__get_user(x, ptr))) goto err; } while (0) +#define unsafe_put_user(x, ptr, err) do { if (unlikely(__put_user(x, ptr))) goto err; } while (0) +#endif + #endif /* __LINUX_UACCESS_H__ */ diff -ruw linux-4.4.115/include/linux/usb/gadget.h linux-4.4.115-fbx/include/linux/usb/gadget.h --- linux-4.4.115/include/linux/usb/gadget.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/linux/usb/gadget.h 2019-10-29 09:26:25.493221282 +0100 @@ -24,9 +24,82 @@ #include #include #include +#include struct usb_ep; +enum ep_type { + EP_TYPE_NORMAL = 0, + EP_TYPE_GSI, +}; + +/* Operations codes for GSI enabled EPs */ +enum gsi_ep_op { + GSI_EP_OP_CONFIG = 0, + GSI_EP_OP_STARTXFER, + GSI_EP_OP_STORE_DBL_INFO, + GSI_EP_OP_ENABLE_GSI, + GSI_EP_OP_UPDATEXFER, + GSI_EP_OP_RING_IN_DB, + GSI_EP_OP_ENDXFER, + GSI_EP_OP_GET_CH_INFO, + GSI_EP_OP_GET_XFER_IDX, + GSI_EP_OP_PREPARE_TRBS, + GSI_EP_OP_FREE_TRBS, + GSI_EP_OP_SET_CLR_BLOCK_DBL, + GSI_EP_OP_CHECK_FOR_SUSPEND, + GSI_EP_OP_DISABLE, +}; + +/* + * @buf_base_addr: Base pointer to buffer allocated for each GSI enabled EP. + * TRBs point to buffers that are split from this pool. The size of the + * buffer is num_bufs times buf_len. num_bufs and buf_len are determined + based on desired performance and aggregation size. + * @dma: DMA address corresponding to buf_base_addr. + * @num_bufs: Number of buffers associated with the GSI enabled EP. This + * corresponds to the number of non-zlp TRBs allocated for the EP. + * The value is determined based on desired performance for the EP. + * @buf_len: Size of each individual buffer is determined based on aggregation + * negotiated as per the protocol. In case of no aggregation supported by + * the protocol, we use default values. + */ +struct usb_gsi_request { + void *buf_base_addr; + dma_addr_t dma; + size_t num_bufs; + size_t buf_len; +}; + +/* + * @last_trb_addr: Address (LSB - based on alignment restrictions) of + * last TRB in queue. Used to identify rollover case. + * @const_buffer_size: TRB buffer size in KB (similar to IPA aggregation + * configuration). Must be aligned to Max USB Packet Size. + * Should be 1 <= const_buffer_size <= 31. + * @depcmd_low_addr: Used by GSI hardware to write "Update Transfer" cmd + * @depcmd_hi_addr: Used to write "Update Transfer" command. + * @gevntcount_low_addr: GEVNCOUNT low address for GSI hardware to read and + * clear processed events. + * @gevntcount_hi_addr: GEVNCOUNT high address. + * @xfer_ring_len: length of transfer ring in bytes (must be integral + * multiple of TRB size - 16B for xDCI). + * @xfer_ring_base_addr: physical base address of transfer ring. Address must + * be aligned to xfer_ring_len rounded to power of two. + * @ch_req: Used to pass request specific info for certain operations on GSI EP + */ +struct gsi_channel_info { + u16 last_trb_addr; + u8 const_buffer_size; + u32 depcmd_low_addr; + u8 depcmd_hi_addr; + u32 gevntcount_low_addr; + u8 gevntcount_hi_addr; + u16 xfer_ring_len; + u64 xfer_ring_base_addr; + struct usb_gsi_request *ch_req; +}; + /** * struct usb_request - describes one i/o request * @buf: Buffer used for data. Always provide this; some controllers @@ -46,6 +119,11 @@ * by adding a zero length packet as needed; * @short_not_ok: When reading data, makes short packets be * treated as errors (queue stops advancing till cleanup). + * @dma_pre_mapped: Tells the USB core driver whether this request should be + * DMA-mapped before it is queued to the USB HW. When set to true, it means + * that the request has already been mapped in advance and therefore the + * USB core driver does NOT need to do DMA-mapping when the request is + * queued to the USB HW. * @complete: Function called when request completes, so this request and * its buffer may be re-used. The function will always be called with * interrupts disabled, and it must not sleep. @@ -69,6 +147,7 @@ * Note that for writes (IN transfers) some data bytes may still * reside in a device-side FIFO when the request is reported as * complete. + * @udc_priv: Vendor private data in usage by the UDC. * * These are allocated/freed through the endpoint they're used with. The * hardware's driver can add extra per-request data to the memory it returns, @@ -101,6 +180,7 @@ unsigned no_interrupt:1; unsigned zero:1; unsigned short_not_ok:1; + unsigned dma_pre_mapped:1; void (*complete)(struct usb_ep *ep, struct usb_request *req); @@ -109,6 +189,7 @@ int status; unsigned actual; + unsigned udc_priv; }; /*-------------------------------------------------------------------------*/ @@ -138,6 +219,8 @@ int (*fifo_status) (struct usb_ep *ep); void (*fifo_flush) (struct usb_ep *ep); + int (*gsi_ep_op)(struct usb_ep *ep, void *op_data, + enum gsi_ep_op op); }; /** @@ -201,6 +284,10 @@ * enabled and remains valid until the endpoint is disabled. * @comp_desc: In case of SuperSpeed support, this is the endpoint companion * descriptor that is used to configure the endpoint + * @ep_type: Used to specify type of EP eg. normal vs h/w accelerated. + * @ep_intr_num: Interrupter number for EP. + * @endless: In case where endless transfer is being initiated, this is set + * to disable usb event interrupt for few events. * * the bus controller driver lists all the general purpose endpoints in * gadget->ep_list. the control endpoint (gadget->ep0) is not in that list, @@ -224,6 +311,10 @@ u8 address; const struct usb_endpoint_descriptor *desc; const struct usb_ss_ep_comp_descriptor *comp_desc; + enum ep_type ep_type; + u8 ep_num; + u8 ep_intr_num; + bool endless; }; /*-------------------------------------------------------------------------*/ @@ -526,7 +617,20 @@ ep->ops->fifo_flush(ep); } +/** + * usb_gsi_ep_op - performs operation on GSI accelerated EP based on EP op code + * + * Operations such as EP configuration, TRB allocation, StartXfer etc. + * See gsi_ep_op for more details. + */ +static inline int usb_gsi_ep_op(struct usb_ep *ep, + struct usb_gsi_request *req, enum gsi_ep_op op) +{ + if (ep->ops->gsi_ep_op) + return ep->ops->gsi_ep_op(ep, req, op); + return -EOPNOTSUPP; +} /*-------------------------------------------------------------------------*/ struct usb_dcd_config_params { @@ -547,10 +651,12 @@ struct usb_gadget_ops { int (*get_frame)(struct usb_gadget *); int (*wakeup)(struct usb_gadget *); + int (*func_wakeup)(struct usb_gadget *, int interface_id); int (*set_selfpowered) (struct usb_gadget *, int is_selfpowered); int (*vbus_session) (struct usb_gadget *, int is_active); int (*vbus_draw) (struct usb_gadget *, unsigned mA); int (*pullup) (struct usb_gadget *, int is_on); + int (*restart)(struct usb_gadget *); int (*ioctl)(struct usb_gadget *, unsigned code, unsigned long param); void (*get_config_params)(struct usb_dcd_config_params *); @@ -646,6 +752,7 @@ unsigned is_selfpowered:1; unsigned deactivated:1; unsigned connected:1; + bool remote_wakeup; }; #define work_to_gadget(w) (container_of((w), struct usb_gadget, work)) @@ -774,6 +881,26 @@ } /** + * usb_gadget_func_wakeup - send a function remote wakeup up notification + * to the host connected to this gadget + * @gadget: controller used to wake up the host + * @interface_id: the interface which triggered the remote wakeup event + * + * Returns zero on success. Otherwise, negative error code is returned. + */ +static inline int usb_gadget_func_wakeup(struct usb_gadget *gadget, + int interface_id) +{ + if (gadget->speed != USB_SPEED_SUPER) + return -EOPNOTSUPP; + + if (!gadget->ops->func_wakeup) + return -EOPNOTSUPP; + + return gadget->ops->func_wakeup(gadget, interface_id); +} + +/** * usb_gadget_set_selfpowered - sets the device selfpowered feature. * @gadget:the device being declared as self-powered * @@ -929,6 +1056,20 @@ } /** + * usb_gadget_restart - software-controlled reset of USB peripheral connection + * @gadget:the peripheral being reset + * + * Informs controller driver for Vbus LOW followed by Vbus HIGH notification. + * This performs full hardware reset and re-initialization. + */ +static inline int usb_gadget_restart(struct usb_gadget *gadget) +{ + if (!gadget->ops->restart) + return -EOPNOTSUPP; + return gadget->ops->restart(gadget); +} + +/** * usb_gadget_deactivate - deactivate function which is not ready to work * @gadget: the peripheral being deactivated * @@ -987,6 +1128,129 @@ return 0; } +/** + * usb_gadget_autopm_get - increment PM-usage counter of usb gadget's parent + * device. + * @gadget: usb gadget whose parent device counter is incremented + * + * This routine should be called by function driver when it wants to use + * gadget's parent device and needs to guarantee that it is not suspended. In + * addition, the routine prevents subsequent autosuspends of gadget's parent + * device. However if the autoresume fails then the counter is re-decremented. + * + * This routine can run only in process context. + */ +static inline int usb_gadget_autopm_get(struct usb_gadget *gadget) +{ + int status = -ENODEV; + + if (!gadget || !gadget->dev.parent) + return status; + + status = pm_runtime_get_sync(gadget->dev.parent); + if (status < 0) + pm_runtime_put_sync(gadget->dev.parent); + + if (status > 0) + status = 0; + return status; +} + +/** + * usb_gadget_autopm_get_async - increment PM-usage counter of usb gadget's + * parent device. + * @gadget: usb gadget whose parent device counter is incremented + * + * This routine increments @gadget parent device PM usage counter and queue an + * autoresume request if the device is suspended. It does not autoresume device + * directly (it only queues a request). After a successful call, the device may + * not yet be resumed. + * + * This routine can run in atomic context. + */ +static inline int usb_gadget_autopm_get_async(struct usb_gadget *gadget) +{ + int status = -ENODEV; + + if (!gadget || !gadget->dev.parent) + return status; + + status = pm_runtime_get(gadget->dev.parent); + if (status < 0 && status != -EINPROGRESS) + pm_runtime_put_noidle(gadget->dev.parent); + + if (status > 0 || status == -EINPROGRESS) + status = 0; + return status; +} + +/** + * usb_gadget_autopm_get_noresume - increment PM-usage counter of usb gadget's + * parent device. + * @gadget: usb gadget whose parent device counter is incremented + * + * This routine increments PM-usage count of @gadget parent device but does not + * carry out an autoresume. + * + * This routine can run in atomic context. + */ +static inline void usb_gadget_autopm_get_noresume(struct usb_gadget *gadget) +{ + if (gadget && gadget->dev.parent) + pm_runtime_get_noresume(gadget->dev.parent); +} + +/** + * usb_gadget_autopm_put - decrement PM-usage counter of usb gadget's parent + * device. + * @gadget: usb gadget whose parent device counter is decremented. + * + * This routine should be called by function driver when it is finished using + * @gadget parent device and wants to allow it to autosuspend. It decrements + * PM-usage counter of @gadget parent device, when the counter reaches 0, a + * delayed autosuspend request is attempted. + * + * This routine can run only in process context. + */ +static inline void usb_gadget_autopm_put(struct usb_gadget *gadget) +{ + if (gadget && gadget->dev.parent) + pm_runtime_put_sync(gadget->dev.parent); +} + +/** + * usb_gadget_autopm_put_async - decrement PM-usage counter of usb gadget's + * parent device. + * @gadget: usb gadget whose parent device counter is decremented. + * + * This routine decrements PM-usage counter of @gadget parent device and + * schedules a delayed autosuspend request if the counter is <= 0. + * + * This routine can run in atomic context. + */ +static inline void usb_gadget_autopm_put_async(struct usb_gadget *gadget) +{ + if (gadget && gadget->dev.parent) + pm_runtime_put(gadget->dev.parent); +} + +/** + * usb_gadget_autopm_put_no_suspend - decrement PM-usage counter of usb gadget +'s + * parent device. + * @gadget: usb gadget whose parent device counter is decremented. + * + * This routine decrements PM-usage counter of @gadget parent device but does + * not carry out an autosuspend. + * + * This routine can run in atomic context. + */ +static inline void usb_gadget_autopm_put_no_suspend(struct usb_gadget *gadget) +{ + if (gadget && gadget->dev.parent) + pm_runtime_put_noidle(gadget->dev.parent); +} + /*-------------------------------------------------------------------------*/ /** @@ -1196,6 +1460,24 @@ struct usb_descriptor_header *otg_desc); /*-------------------------------------------------------------------------*/ +/** + * usb_func_ep_queue - queues (submits) an I/O request to a function endpoint. + * This function is similar to the usb_ep_queue function, but in addition it + * also checks whether the function is in Super Speed USB Function Suspend + * state, and if so a Function Wake notification is sent to the host + * (USB 3.0 spec, section 9.2.5.2). + * @func: the function which issues the USB I/O request. + * @ep:the endpoint associated with the request + * @req:the request being submitted + * @gfp_flags: GFP_* flags to use in case the lower level driver couldn't + * pre-allocate all necessary memory with the request. + * + */ +int usb_func_ep_queue(struct usb_function *func, struct usb_ep *ep, + struct usb_request *req, gfp_t gfp_flags); + +/*-------------------------------------------------------------------------*/ + /* utility to simplify map/unmap of usb_requests to/from DMA */ extern int usb_gadget_map_request(struct usb_gadget *gadget, @@ -1259,5 +1541,8 @@ extern void usb_ep_autoconfig_release(struct usb_ep *); extern void usb_ep_autoconfig_reset(struct usb_gadget *); +extern struct usb_ep *usb_ep_autoconfig_by_name(struct usb_gadget *, + struct usb_endpoint_descriptor *, + const char *ep_name); #endif /* __LINUX_USB_GADGET_H */ diff -ruw linux-4.4.115/include/linux/usb/hcd.h linux-4.4.115-fbx/include/linux/usb/hcd.h --- linux-4.4.115/include/linux/usb/hcd.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/linux/usb/hcd.h 2019-10-29 09:26:25.493221282 +0100 @@ -397,6 +397,13 @@ /* Call for power on/off the port if necessary */ int (*port_power)(struct usb_hcd *hcd, int portnum, bool enable); + int (*sec_event_ring_setup)(struct usb_hcd *hcd, unsigned intr_num); + int (*sec_event_ring_cleanup)(struct usb_hcd *hcd, unsigned intr_num); + dma_addr_t (*get_sec_event_ring_dma_addr)(struct usb_hcd *hcd, + unsigned intr_num); + dma_addr_t (*get_xfer_ring_dma_addr)(struct usb_hcd *hcd, + struct usb_device *udev, struct usb_host_endpoint *ep); + int (*get_core_id)(struct usb_hcd *hcd); }; static inline int hcd_giveback_urb_in_bh(struct usb_hcd *hcd) @@ -435,6 +442,17 @@ struct usb_host_interface *old_alt, struct usb_host_interface *new_alt); extern int usb_hcd_get_frame_number(struct usb_device *udev); +extern int usb_hcd_sec_event_ring_setup(struct usb_device *udev, + unsigned intr_num); +extern int usb_hcd_sec_event_ring_cleanup(struct usb_device *udev, + unsigned intr_num); +extern dma_addr_t +usb_hcd_get_sec_event_ring_dma_addr(struct usb_device *udev, + unsigned intr_num); +extern dma_addr_t +usb_hcd_get_xfer_ring_dma_addr(struct usb_device *udev, + struct usb_host_endpoint *ep); +extern int usb_hcd_get_controller_id(struct usb_device *udev); extern struct usb_hcd *usb_create_hcd(const struct hc_driver *driver, struct device *dev, const char *bus_name); @@ -484,7 +502,7 @@ extern void usb_hcd_poll_rh_status(struct usb_hcd *hcd); extern void usb_wakeup_notification(struct usb_device *hdev, unsigned int portnum); - +extern void usb_flush_hub_wq(void); extern void usb_hcd_start_port_resume(struct usb_bus *bus, int portnum); extern void usb_hcd_end_port_resume(struct usb_bus *bus, int portnum); diff -ruw linux-4.4.115/include/linux/usb/msm_hsusb.h linux-4.4.115-fbx/include/linux/usb/msm_hsusb.h --- linux-4.4.115/include/linux/usb/msm_hsusb.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/linux/usb/msm_hsusb.h 2019-01-22 16:16:28.415290888 +0100 @@ -1,8 +1,8 @@ -/* linux/include/asm-arm/arch-msm/hsusb.h +/* include/linux/usb/msm_hsusb.h * * Copyright (C) 2008 Google, Inc. * Author: Brian Swetland - * Copyright (c) 2009-2011, Code Aurora Forum. All rights reserved. + * Copyright (c) 2009-2016, The Linux Foundation. All rights reserved. * * This software is licensed under the terms of the GNU General Public * License version 2, as published by the Free Software Foundation, and @@ -20,8 +20,24 @@ #include #include +#include +#include #include -#include +/* + * The following are bit fields describing the usb_request.udc_priv word. + * These bit fields are set by function drivers that wish to queue + * usb_requests with sps/bam parameters. + */ +#define MSM_PIPE_ID_MASK (0x1F) +#define MSM_TX_PIPE_ID_OFS (16) +#define MSM_SPS_MODE BIT(5) +#define MSM_IS_FINITE_TRANSFER BIT(6) +#define MSM_PRODUCER BIT(7) +#define MSM_DISABLE_WB BIT(8) +#define MSM_ETD_IOC BIT(9) +#define MSM_INTERNAL_MEM BIT(10) +#define MSM_VENDOR_ID BIT(16) + /** * OTG control @@ -99,6 +115,25 @@ }; /** + * Supported USB controllers + */ +enum usb_ctrl { + DWC3_CTRL = 0, /* DWC3 controller */ + CI_CTRL, /* ChipIdea controller */ + HSIC_CTRL, /* HSIC controller */ + NUM_CTRL, +}; + + +/** + * USB ID state + */ +enum usb_id_state { + USB_ID_GROUND = 0, + USB_ID_FLOAT, +}; + +/** * struct msm_otg_platform_data - platform device data * for msm_otg driver. * @phy_init_seq: PHY configuration sequence values. Value of -1 is reserved as @@ -131,6 +166,21 @@ struct extcon_dev *extcon; }; + +/* phy related flags */ +#define ENABLE_DP_MANUAL_PULLUP BIT(0) +#define ENABLE_SECONDARY_PHY BIT(1) +#define PHY_HOST_MODE BIT(2) +#define PHY_CHARGER_CONNECTED BIT(3) +#define PHY_VBUS_VALID_OVERRIDE BIT(4) +#define DEVICE_IN_SS_MODE BIT(5) +#define PHY_LANE_A BIT(6) +#define PHY_LANE_B BIT(7) +#define PHY_HSFS_MODE BIT(8) +#define PHY_LS_MODE BIT(9) + +#define USB_NUM_BUS_CLOCKS 3 + /** * struct msm_otg: OTG driver data. Shared by HCD and DCD. * @otg: USB OTG Transceiver structure. @@ -197,4 +247,94 @@ struct notifier_block reboot; }; +#ifdef CONFIG_USB_BAM +void msm_bam_set_usb_host_dev(struct device *dev); +void msm_bam_set_hsic_host_dev(struct device *dev); +void msm_bam_wait_for_usb_host_prod_granted(void); +void msm_bam_wait_for_hsic_host_prod_granted(void); +bool msm_bam_hsic_lpm_ok(void); +void msm_bam_usb_host_notify_on_resume(void); +void msm_bam_hsic_host_notify_on_resume(void); +bool msm_bam_hsic_host_pipe_empty(void); +bool msm_usb_bam_enable(enum usb_ctrl ctrl, bool bam_enable); +#else +static inline void msm_bam_set_usb_host_dev(struct device *dev) {} +static inline void msm_bam_set_hsic_host_dev(struct device *dev) {} +static inline void msm_bam_wait_for_usb_host_prod_granted(void) {} +static inline void msm_bam_wait_for_hsic_host_prod_granted(void) {} +static inline bool msm_bam_hsic_lpm_ok(void) { return true; } +static inline void msm_bam_hsic_host_notify_on_resume(void) {} +static inline void msm_bam_usb_host_notify_on_resume(void) {} +static inline bool msm_bam_hsic_host_pipe_empty(void) { return true; } +static inline bool msm_usb_bam_enable(enum usb_ctrl ctrl, bool bam_enable) +{ + return true; +} +#endif + +/* CONFIG_PM */ +#ifdef CONFIG_PM +static inline int get_pm_runtime_counter(struct device *dev) +{ + return atomic_read(&dev->power.usage_count); +} +#else /* !CONFIG_PM */ +static inline int get_pm_runtime_counter(struct device *dev) { return -ENOSYS; } +#endif + +#ifdef CONFIG_USB_CI13XXX_MSM +void msm_hw_bam_disable(bool bam_disable); +void msm_usb_irq_disable(bool disable); +#else +static inline void msm_hw_bam_disable(bool bam_disable) +{ +} + +static inline void msm_usb_irq_disable(bool disable) +{ +} +#endif + +#ifdef CONFIG_USB_DWC3_QCOM +int msm_ep_config(struct usb_ep *ep, struct usb_request *request); +int msm_ep_unconfig(struct usb_ep *ep); +void dwc3_tx_fifo_resize_request(struct usb_ep *ep, bool qdss_enable); +int msm_data_fifo_config(struct usb_ep *ep, phys_addr_t addr, u32 size, + u8 dst_pipe_idx); +bool msm_dwc3_reset_ep_after_lpm(struct usb_gadget *gadget); +int msm_dwc3_reset_dbm_ep(struct usb_ep *ep); + +#else +static inline int msm_data_fifo_config(struct usb_ep *ep, phys_addr_t addr, + u32 size, u8 dst_pipe_idx) +{ + return -ENODEV; +} + +static inline int msm_ep_config(struct usb_ep *ep, struct usb_request *request) +{ + return -ENODEV; +} + +static inline int msm_ep_unconfig(struct usb_ep *ep) +{ + return -ENODEV; +} + +static inline void dwc3_tx_fifo_resize_request( + struct usb_ep *ep, bool qdss_enable) +{ +} + +static inline bool msm_dwc3_reset_ep_after_lpm(struct usb_gadget *gadget) +{ + return false; +} + +static inline int msm_dwc3_reset_dbm_ep(struct usb_ep *ep) +{ + return -ENODEV; +} + +#endif #endif diff -ruw linux-4.4.115/include/linux/usb/phy.h linux-4.4.115-fbx/include/linux/usb/phy.h --- linux-4.4.115/include/linux/usb/phy.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/linux/usb/phy.h 2019-10-29 09:26:25.493221282 +0100 @@ -44,6 +44,7 @@ OTG_STATE_B_IDLE, OTG_STATE_B_SRP_INIT, OTG_STATE_B_PERIPHERAL, + OTG_STATE_B_SUSPEND, /* extra dual-role default-b states */ OTG_STATE_B_WAIT_ACON, @@ -122,6 +123,9 @@ enum usb_device_speed speed); int (*notify_disconnect)(struct usb_phy *x, enum usb_device_speed speed); + + /* reset the PHY clocks */ + int (*reset)(struct usb_phy *x); }; /** @@ -196,6 +200,15 @@ return x->set_vbus(x, false); } +static inline int +usb_phy_reset(struct usb_phy *x) +{ + if (x && x->reset) + return x->reset(x); + + return 0; +} + /* for usb host and peripheral controller drivers */ #if IS_ENABLED(CONFIG_USB_PHY) extern struct usb_phy *usb_get_phy(enum usb_phy_type type); diff -ruw linux-4.4.115/include/linux/usb/xhci_pdriver.h linux-4.4.115-fbx/include/linux/usb/xhci_pdriver.h --- linux-4.4.115/include/linux/usb/xhci_pdriver.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/linux/usb/xhci_pdriver.h 2019-01-22 16:16:28.419290924 +0100 @@ -19,9 +19,13 @@ * @usb3_lpm_capable: determines if this xhci platform supports USB3 * LPM capability * + * @imod_interval: minimum inter-interrupt interval. Specified in + * 250nsec increments. + * */ struct usb_xhci_pdata { unsigned usb3_lpm_capable:1; + unsigned imod_interval; }; #endif /* __USB_CORE_XHCI_PDRIVER_H */ diff -ruw linux-4.4.115/include/linux/usb.h linux-4.4.115-fbx/include/linux/usb.h --- linux-4.4.115/include/linux/usb.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/linux/usb.h 2019-10-29 09:26:25.493221282 +0100 @@ -331,6 +331,8 @@ struct usb_ssp_cap_descriptor *ssp_cap; struct usb_ss_container_id_descriptor *ss_id; struct usb_ptm_cap_descriptor *ptm_cap; + struct usb_config_summary_descriptor *config_summary; + unsigned int num_config_summary_desc; }; int __usb_get_extra_descriptor(char *buffer, unsigned size, @@ -395,6 +397,15 @@ struct mon_bus *mon_bus; /* non-null when associated */ int monitored; /* non-zero when monitored */ #endif + unsigned skip_resume:1; /* All USB devices are brought into full + * power state after system resume. It + * is desirable for some buses to keep + * their devices in suspend state even + * after system resume. The devices + * are resumed later when a remote + * wakeup is detected or an interface + * driver starts I/O. + */ }; struct usb_dev_state; @@ -734,6 +745,17 @@ /* for drivers using iso endpoints */ extern int usb_get_current_frame_number(struct usb_device *usb_dev); +extern int usb_sec_event_ring_setup(struct usb_device *dev, + unsigned intr_num); +extern int usb_sec_event_ring_cleanup(struct usb_device *dev, + unsigned intr_num); + +extern dma_addr_t +usb_get_sec_event_ring_dma_addr(struct usb_device *dev, + unsigned intr_num); +extern dma_addr_t usb_get_xfer_ring_dma_addr(struct usb_device *dev, + struct usb_host_endpoint *ep); +extern int usb_get_controller_id(struct usb_device *dev); /* Sets up a group of bulk endpoints to support multiple stream IDs. */ extern int usb_alloc_streams(struct usb_interface *interface, @@ -1885,8 +1907,11 @@ #define USB_DEVICE_REMOVE 0x0002 #define USB_BUS_ADD 0x0003 #define USB_BUS_REMOVE 0x0004 +#define USB_BUS_DIED 0x0005 extern void usb_register_notify(struct notifier_block *nb); extern void usb_unregister_notify(struct notifier_block *nb); +extern void usb_register_atomic_notify(struct notifier_block *nb); +extern void usb_unregister_atomic_notify(struct notifier_block *nb); /* debugfs stuff */ extern struct dentry *usb_debug_root; diff -ruw linux-4.4.115/include/linux/vmalloc.h linux-4.4.115-fbx/include/linux/vmalloc.h --- linux-4.4.115/include/linux/vmalloc.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/linux/vmalloc.h 2019-01-22 16:16:28.423290960 +0100 @@ -4,6 +4,7 @@ #include #include #include +#include #include /* pgprot_t */ #include @@ -18,6 +19,8 @@ #define VM_UNINITIALIZED 0x00000020 /* vm_struct is not fully initialized */ #define VM_NO_GUARD 0x00000040 /* don't add guard page */ #define VM_KASAN 0x00000080 /* has allocated kasan shadow memory */ +#define VM_LOWMEM 0x00000100 /* Tracking of direct mapped lowmem */ + /* bits [20..32] reserved for arch specific ioremap internals */ /* @@ -45,7 +48,7 @@ unsigned long flags; struct rb_node rb_node; /* address sorted rbtree */ struct list_head list; /* address sorted list */ - struct list_head purge_list; /* "lazy purge" list */ + struct llist_node purge_list; /* "lazy purge" list */ struct vm_struct *vm; struct rcu_head rcu_head; }; @@ -81,6 +84,7 @@ const void *caller); extern void vfree(const void *addr); +extern void vfree_atomic(const void *addr); extern void *vmap(struct page **pages, unsigned int count, unsigned long flags, pgprot_t prot); @@ -158,6 +162,13 @@ extern struct list_head vmap_area_list; extern __init void vm_area_add_early(struct vm_struct *vm); extern __init void vm_area_register_early(struct vm_struct *vm, size_t align); +extern __init int vm_area_check_early(struct vm_struct *vm); +#ifdef CONFIG_ENABLE_VMALLOC_SAVING +extern void mark_vmalloc_reserved_area(void *addr, unsigned long size); +#else +static inline void mark_vmalloc_reserved_area(void *addr, unsigned long size) +{ }; +#endif #ifdef CONFIG_SMP # ifdef CONFIG_MMU @@ -183,7 +194,12 @@ #endif #ifdef CONFIG_MMU +#ifdef CONFIG_ENABLE_VMALLOC_SAVING +extern unsigned long total_vmalloc_size; +#define VMALLOC_TOTAL total_vmalloc_size +#else #define VMALLOC_TOTAL (VMALLOC_END - VMALLOC_START) +#endif #else #define VMALLOC_TOTAL 0UL #endif diff -ruw linux-4.4.115/include/linux/vm_event_item.h linux-4.4.115-fbx/include/linux/vm_event_item.h --- linux-4.4.115/include/linux/vm_event_item.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/linux/vm_event_item.h 2019-10-29 09:26:25.497221322 +0100 @@ -21,7 +21,7 @@ #define FOR_ALL_ZONES(xx) DMA_ZONE(xx) DMA32_ZONE(xx) xx##_NORMAL, HIGHMEM_ZONE(xx) xx##_MOVABLE -enum vm_event_item { PGPGIN, PGPGOUT, PSWPIN, PSWPOUT, +enum vm_event_item { PGPGIN, PGPGOUT, PGPGOUTCLEAN, PSWPIN, PSWPOUT, FOR_ALL_ZONES(PGALLOC), PGFREE, PGACTIVATE, PGDEACTIVATE, PGFAULT, PGMAJFAULT, @@ -52,6 +52,7 @@ COMPACTMIGRATE_SCANNED, COMPACTFREE_SCANNED, COMPACTISOLATED, COMPACTSTALL, COMPACTFAIL, COMPACTSUCCESS, + KCOMPACTD_WAKE, #endif #ifdef CONFIG_HUGETLB_PAGE HTLB_BUDDY_PGALLOC, HTLB_BUDDY_PGALLOC_FAIL, diff -ruw linux-4.4.115/include/linux/vmpressure.h linux-4.4.115-fbx/include/linux/vmpressure.h --- linux-4.4.115/include/linux/vmpressure.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/linux/vmpressure.h 2019-01-22 16:16:28.423290960 +0100 @@ -12,6 +12,7 @@ struct vmpressure { unsigned long scanned; unsigned long reclaimed; + unsigned long stall; /* The lock is used to keep the scanned/reclaimed above in sync. */ struct spinlock sr_lock; @@ -25,11 +26,13 @@ struct mem_cgroup; -#ifdef CONFIG_MEMCG +extern int vmpressure_notifier_register(struct notifier_block *nb); +extern int vmpressure_notifier_unregister(struct notifier_block *nb); extern void vmpressure(gfp_t gfp, struct mem_cgroup *memcg, unsigned long scanned, unsigned long reclaimed); extern void vmpressure_prio(gfp_t gfp, struct mem_cgroup *memcg, int prio); +#ifdef CONFIG_MEMCG extern void vmpressure_init(struct vmpressure *vmpr); extern void vmpressure_cleanup(struct vmpressure *vmpr); extern struct vmpressure *memcg_to_vmpressure(struct mem_cgroup *memcg); @@ -40,9 +43,9 @@ extern void vmpressure_unregister_event(struct mem_cgroup *memcg, struct eventfd_ctx *eventfd); #else -static inline void vmpressure(gfp_t gfp, struct mem_cgroup *memcg, - unsigned long scanned, unsigned long reclaimed) {} -static inline void vmpressure_prio(gfp_t gfp, struct mem_cgroup *memcg, - int prio) {} +static inline struct vmpressure *memcg_to_vmpressure(struct mem_cgroup *memcg) +{ + return NULL; +} #endif /* CONFIG_MEMCG */ #endif /* __LINUX_VMPRESSURE_H */ diff -ruw linux-4.4.115/include/linux/vmstat.h linux-4.4.115-fbx/include/linux/vmstat.h --- linux-4.4.115/include/linux/vmstat.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/linux/vmstat.h 2019-01-22 16:16:28.423290960 +0100 @@ -160,6 +160,26 @@ return x; } +static inline unsigned long global_page_state_snapshot(enum zone_stat_item item) +{ + long x = atomic_long_read(&vm_stat[item]); + +#ifdef CONFIG_SMP + struct zone *zone; + int cpu; + + for_each_online_cpu(cpu) { + for_each_populated_zone(zone) + x += per_cpu_ptr(zone->pageset, + cpu)->vm_stat_diff[item]; + } + + if (x < 0) + x = 0; +#endif + return x; +} + #ifdef CONFIG_NUMA extern unsigned long node_page_state(int node, enum zone_stat_item item); @@ -189,6 +209,7 @@ extern void dec_zone_state(struct zone *, enum zone_stat_item); extern void __dec_zone_state(struct zone *, enum zone_stat_item); +void quiet_vmstat(void); void cpu_vm_stats_fold(int cpu); void refresh_zone_stat_thresholds(void); @@ -249,6 +270,7 @@ static inline void refresh_zone_stat_thresholds(void) { } static inline void cpu_vm_stats_fold(int cpu) { } +static inline void quiet_vmstat(void) { } static inline void drain_zonestat(struct zone *zone, struct per_cpu_pageset *pset) { } diff -ruw linux-4.4.115/include/linux/workqueue.h linux-4.4.115-fbx/include/linux/workqueue.h --- linux-4.4.115/include/linux/workqueue.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/linux/workqueue.h 2019-10-29 09:26:25.497221322 +0100 @@ -620,4 +620,10 @@ { return 0; } #endif /* CONFIG_SYSFS */ +#ifdef CONFIG_WQ_WATCHDOG +void wq_watchdog_touch(int cpu); +#else /* CONFIG_WQ_WATCHDOG */ +static inline void wq_watchdog_touch(int cpu) { } +#endif /* CONFIG_WQ_WATCHDOG */ + #endif diff -ruw linux-4.4.115/include/linux/writeback.h linux-4.4.115-fbx/include/linux/writeback.h --- linux-4.4.115/include/linux/writeback.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/linux/writeback.h 2019-01-22 16:16:28.427290996 +0100 @@ -224,6 +224,7 @@ static inline void inode_detach_wb(struct inode *inode) { if (inode->i_wb) { + WARN_ON_ONCE(!(inode->i_state & I_CLEAR)); wb_put(inode->i_wb); inode->i_wb = NULL; } diff -ruw linux-4.4.115/include/linux/zsmalloc.h linux-4.4.115-fbx/include/linux/zsmalloc.h --- linux-4.4.115/include/linux/zsmalloc.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/linux/zsmalloc.h 2019-10-29 09:26:25.497221322 +0100 @@ -41,10 +41,10 @@ struct zs_pool; -struct zs_pool *zs_create_pool(const char *name, gfp_t flags); +struct zs_pool *zs_create_pool(const char *name); void zs_destroy_pool(struct zs_pool *pool); -unsigned long zs_malloc(struct zs_pool *pool, size_t size); +unsigned long zs_malloc(struct zs_pool *pool, size_t size, gfp_t flags); void zs_free(struct zs_pool *pool, unsigned long obj); void *zs_map_object(struct zs_pool *pool, unsigned long handle, diff -ruw linux-4.4.115/include/media/rc-map.h linux-4.4.115-fbx/include/media/rc-map.h --- linux-4.4.115/include/media/rc-map.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/media/rc-map.h 2019-10-29 09:26:25.501221361 +0100 @@ -31,6 +31,7 @@ RC_TYPE_RC6_MCE = 16, /* MCE (Philips RC6-6A-32 subtype) protocol */ RC_TYPE_SHARP = 17, /* Sharp protocol */ RC_TYPE_XMP = 18, /* XMP protocol */ + RC_TYPE_CEC = 19, /* CEC protocol */ }; #define RC_BIT_NONE 0 @@ -53,6 +54,7 @@ #define RC_BIT_RC6_MCE (1 << RC_TYPE_RC6_MCE) #define RC_BIT_SHARP (1 << RC_TYPE_SHARP) #define RC_BIT_XMP (1 << RC_TYPE_XMP) +#define RC_BIT_CEC (1 << RC_TYPE_CEC) #define RC_BIT_ALL (RC_BIT_UNKNOWN | RC_BIT_OTHER | \ RC_BIT_RC5 | RC_BIT_RC5X | RC_BIT_RC5_SZ | \ @@ -61,7 +63,7 @@ RC_BIT_NEC | RC_BIT_SANYO | RC_BIT_MCE_KBD | \ RC_BIT_RC6_0 | RC_BIT_RC6_6A_20 | RC_BIT_RC6_6A_24 | \ RC_BIT_RC6_6A_32 | RC_BIT_RC6_MCE | RC_BIT_SHARP | \ - RC_BIT_XMP) + RC_BIT_XMP | RC_BIT_CEC) #define RC_SCANCODE_UNKNOWN(x) (x) @@ -123,6 +125,7 @@ #define RC_MAP_BEHOLD_COLUMBUS "rc-behold-columbus" #define RC_MAP_BEHOLD "rc-behold" #define RC_MAP_BUDGET_CI_OLD "rc-budget-ci-old" +#define RC_MAP_CEC "rc-cec" #define RC_MAP_CINERGY_1400 "rc-cinergy-1400" #define RC_MAP_CINERGY "rc-cinergy" #define RC_MAP_DELOCK_61959 "rc-delock-61959" diff -ruw linux-4.4.115/include/media/videobuf2-core.h linux-4.4.115-fbx/include/media/videobuf2-core.h --- linux-4.4.115/include/media/videobuf2-core.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/media/videobuf2-core.h 2019-01-22 16:16:28.443291141 +0100 @@ -17,7 +17,7 @@ #include #include -#define VB2_MAX_FRAME (32) +#define VB2_MAX_FRAME (64) #define VB2_MAX_PLANES (8) enum vb2_memory { diff -ruw linux-4.4.115/include/net/addrconf.h linux-4.4.115-fbx/include/net/addrconf.h --- linux-4.4.115/include/net/addrconf.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/net/addrconf.h 2019-10-29 09:26:25.501221361 +0100 @@ -1,8 +1,9 @@ #ifndef _ADDRCONF_H #define _ADDRCONF_H -#define MAX_RTR_SOLICITATIONS 3 +#define MAX_RTR_SOLICITATIONS -1 /* unlimited */ #define RTR_SOLICITATION_INTERVAL (4*HZ) +#define RTR_SOLICITATION_MAX_INTERVAL (3600*HZ) /* 1 hour */ #define MIN_VALID_LIFETIME (2*3600) /* 2 hours */ @@ -229,6 +230,8 @@ void addrconf_prefix_rcv(struct net_device *dev, u8 *opt, int len, bool sllao); +u32 addrconf_rt_table(const struct net_device *dev, u32 default_table); + /* * anycast prototypes (anycast.c) */ diff -ruw linux-4.4.115/include/net/cfg80211.h linux-4.4.115-fbx/include/net/cfg80211.h --- linux-4.4.115/include/net/cfg80211.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/net/cfg80211.h 2019-10-29 09:26:25.505221400 +0100 @@ -63,6 +63,25 @@ struct wiphy; +#define CFG80211_SCAN_BSSID 1 +#define CFG80211_CONNECT_PREV_BSSID 1 +#define CFG80211_CONNECT_BSS 1 +#define CFG80211_ABORT_SCAN 1 +#define CFG80211_UPDATE_CONNECT_PARAMS 1 +#define CFG80211_BEACON_TX_RATE_CUSTOM_BACKPORT 1 +#define CFG80211_RAND_TA_FOR_PUBLIC_ACTION_FRAME 1 +#define CFG80211_REPORT_BETTER_BSS_IN_SCHED_SCAN 1 +#define CFG80211_CONNECT_TIMEOUT 1 +#define CFG80211_CONNECT_TIMEOUT_REASON_CODE 1 + +/* Indicate backport support for the new connect done api */ +#define CFG80211_CONNECT_DONE 1 +/* Indicate backport support for FILS SK offload in cfg80211 */ +#define CFG80211_FILS_SK_OFFLOAD_SUPPORT 1 + +/* Indicate support for including KEK length in rekey data */ +#define CFG80211_REKEY_DATA_KEK_LEN 1 + /* * wireless hardware capability structures */ @@ -690,6 +709,18 @@ struct mac_address mac_addrs[]; }; +/* + * cfg80211_bitrate_mask - masks for bitrate control + */ +struct cfg80211_bitrate_mask { + struct { + u32 legacy; + u8 ht_mcs[IEEE80211_HT_MCS_MASK_LEN]; + u16 vht_mcs[NL80211_VHT_NSS_MAX]; + enum nl80211_txrate_gi gi; + } control[IEEE80211_NUM_BANDS]; +}; + /** * struct cfg80211_ap_settings - AP configuration * @@ -712,6 +743,9 @@ * @p2p_opp_ps: P2P opportunistic PS * @acl: ACL configuration used by the drivers which has support for * MAC address based access control + * @pbss: If set, start as a PCP instead of AP. Relevant for DMG + * networks. + * @beacon_rate: bitrate to be used for beacons */ struct cfg80211_ap_settings { struct cfg80211_chan_def chandef; @@ -730,6 +764,8 @@ u8 p2p_ctwindow; bool p2p_opp_ps; const struct cfg80211_acl_data *acl; + bool pbss; + struct cfg80211_bitrate_mask beacon_rate; }; /** @@ -762,6 +798,30 @@ }; /** + * struct iface_combination_params - input parameters for interface combinations + * + * Used to pass interface combination parameters + * + * @num_different_channels: the number of different channels we want + * to use for verification + * @radar_detect: a bitmap where each bit corresponds to a channel + * width where radar detection is needed, as in the definition of + * &struct ieee80211_iface_combination.@radar_detect_widths + * @iftype_num: array with the number of interfaces of each interface + * type. The index is the interface type as specified in &enum + * nl80211_iftype. + * @new_beacon_int: set this to the beacon interval of a new interface + * that's not operating yet, if such is to be checked as part of + * the verification + */ +struct iface_combination_params { + int num_different_channels; + u8 radar_detect; + int iftype_num[NUM_NL80211_IFTYPES]; + u32 new_beacon_int; +}; + +/** * enum station_parameters_apply_mask - station parameter values to apply * @STATION_PARAM_APPLY_UAPSD: apply new uAPSD parameters (uapsd_queues, max_sp) * @STATION_PARAM_APPLY_CAPABILITY: apply new capability @@ -1347,6 +1407,7 @@ * @beacon_interval: beacon interval to use * @mcast_rate: multicat rate for Mesh Node [6Mbps is the default for 802.11a] * @basic_rates: basic rates to use when creating the mesh + * @beacon_rate: bitrate to be used for beacons * * These parameters are fixed when the mesh is created. */ @@ -1367,6 +1428,7 @@ u16 beacon_interval; int mcast_rate[IEEE80211_NUM_BANDS]; u32 basic_rates; + struct cfg80211_bitrate_mask beacon_rate; }; /** @@ -1452,6 +1514,7 @@ * @mac_addr_mask: MAC address mask used with randomisation, bits that * are 0 in the mask should be randomised, bits that are 1 should * be taken from the @mac_addr + * @bssid: BSSID to scan for (most commonly, the wildcard BSSID) */ struct cfg80211_scan_request { struct cfg80211_ssid *ssids; @@ -1468,6 +1531,7 @@ u8 mac_addr[ETH_ALEN] __aligned(2); u8 mac_addr_mask[ETH_ALEN] __aligned(2); + u8 bssid[ETH_ALEN] __aligned(2); /* internal */ struct wiphy *wiphy; @@ -1516,6 +1580,17 @@ }; /** + * struct cfg80211_bss_select_adjust - BSS selection with RSSI adjustment. + * + * @band: band of BSS which should match for RSSI level adjustment. + * @delta: value of RSSI level adjustment. + */ +struct cfg80211_bss_select_adjust { + enum nl80211_band band; + s8 delta; +}; + +/** * struct cfg80211_sched_scan_request - scheduled scan request description * * @ssids: SSIDs to scan for (passed in the probe_reqs in active scans) @@ -1550,6 +1625,16 @@ * cycle. The driver may ignore this parameter and start * immediately (or at any other time), if this feature is not * supported. + * @relative_rssi_set: Indicates whether @relative_rssi is set or not. + * @relative_rssi: Relative RSSI threshold in dB to restrict scan result + * reporting in connected state to cases where a matching BSS is determined + * to have better or slightly worse RSSI than the current connected BSS. + * The relative RSSI threshold values are ignored in disconnected state. + * @rssi_adjust: delta dB of RSSI preference to be given to the BSSs that belong + * to the specified band while deciding whether a better BSS is reported + * using @relative_rssi. If delta is a negative number, the BSSs that + * belong to the specified band will be penalized by delta dB in relative + * comparisions. */ struct cfg80211_sched_scan_request { struct cfg80211_ssid *ssids; @@ -1569,6 +1654,10 @@ u8 mac_addr[ETH_ALEN] __aligned(2); u8 mac_addr_mask[ETH_ALEN] __aligned(2); + bool relative_rssi_set; + s8 relative_rssi; + struct cfg80211_bss_select_adjust rssi_adjust; + /* internal */ struct wiphy *wiphy; struct net_device *dev; @@ -1702,9 +1791,11 @@ * @key_len: length of WEP key for shared key authentication * @key_idx: index of WEP key for shared key authentication * @key: WEP key for shared key authentication - * @sae_data: Non-IE data to use with SAE or %NULL. This starts with - * Authentication transaction sequence number field. - * @sae_data_len: Length of sae_data buffer in octets + * @auth_data: Fields and elements in Authentication frames. This contains + * the authentication frame body (non-IE and IE data), excluding the + * Authentication algorithm number, i.e., starting at the Authentication + * transaction sequence number field. + * @auth_data_len: Length of auth_data buffer in octets */ struct cfg80211_auth_request { struct cfg80211_bss *bss; @@ -1713,8 +1804,8 @@ enum nl80211_auth_type auth_type; const u8 *key; u8 key_len, key_idx; - const u8 *sae_data; - size_t sae_data_len; + const u8 *auth_data; + size_t auth_data_len; }; /** @@ -1750,6 +1841,12 @@ * @ht_capa_mask: The bits of ht_capa which are to be used. * @vht_capa: VHT capability override * @vht_capa_mask: VHT capability mask indicating which fields to use + * @fils_kek: FILS KEK for protecting (Re)Association Request/Response frame or + * %NULL if FILS is not used. + * @fils_kek_len: Length of fils_kek in octets + * @fils_nonces: FILS nonces (part of AAD) for protecting (Re)Association + * Request/Response frame or %NULL if FILS is not used. This field starts + * with 16 octets of STA Nonce followed by 16 octets of AP Nonce. */ struct cfg80211_assoc_request { struct cfg80211_bss *bss; @@ -1761,6 +1858,9 @@ struct ieee80211_ht_cap ht_capa; struct ieee80211_ht_cap ht_capa_mask; struct ieee80211_vht_cap vht_capa, vht_capa_mask; + const u8 *fils_kek; + size_t fils_kek_len; + const u8 *fils_nonces; }; /** @@ -1854,6 +1954,22 @@ }; /** + * struct cfg80211_bss_selection - connection parameters for BSS selection. + * + * @behaviour: requested BSS selection behaviour. + * @param: parameters for requestion behaviour. + * @band_pref: preferred band for %NL80211_BSS_SELECT_ATTR_BAND_PREF. + * @adjust: parameters for %NL80211_BSS_SELECT_ATTR_RSSI_ADJUST. + */ +struct cfg80211_bss_selection { + enum nl80211_bss_select_attr behaviour; + union { + enum ieee80211_band band_pref; + struct cfg80211_bss_select_adjust adjust; + } param; +}; + +/** * struct cfg80211_connect_params - Connection parameters * * This structure provides information needed to complete IEEE 802.11 @@ -1888,6 +2004,23 @@ * @ht_capa_mask: The bits of ht_capa which are to be used. * @vht_capa: VHT Capability overrides * @vht_capa_mask: The bits of vht_capa which are to be used. + * @pbss: if set, connect to a PCP instead of AP. Valid for DMG + * networks. + * @bss_select: criteria to be used for BSS selection. + * @prev_bssid: previous BSSID, if not %NULL use reassociate frame + * @fils_erp_username: EAP re-authentication protocol (ERP) username part of the + * NAI or %NULL if not specified. This is used to construct FILS wrapped + * data IE. + * @fils_erp_username_len: Length of @fils_erp_username in octets. + * @fils_erp_realm: EAP re-authentication protocol (ERP) realm part of NAI or + * %NULL if not specified. This specifies the domain name of ER server and + * is used to construct FILS wrapped data IE. + * @fils_erp_realm_len: Length of @fils_erp_realm in octets. + * @fils_erp_next_seq_num: The next sequence number to use in the FILS ERP + * messages. This is also used to construct FILS wrapped data IE. + * @fils_erp_rrk: ERP re-authentication Root Key (rRK) used to derive additional + * keys in FILS or %NULL if not specified. + * @fils_erp_rrk_len: Length of @fils_erp_rrk in octets. */ struct cfg80211_connect_params { struct ieee80211_channel *channel; @@ -1910,6 +2043,33 @@ struct ieee80211_ht_cap ht_capa_mask; struct ieee80211_vht_cap vht_capa; struct ieee80211_vht_cap vht_capa_mask; + bool pbss; + struct cfg80211_bss_selection bss_select; + const u8 *prev_bssid; + const u8 *fils_erp_username; + size_t fils_erp_username_len; + const u8 *fils_erp_realm; + size_t fils_erp_realm_len; + u16 fils_erp_next_seq_num; + const u8 *fils_erp_rrk; + size_t fils_erp_rrk_len; +}; + +/** + * enum cfg80211_connect_params_changed - Connection parameters being updated + * + * This enum provides information of all connect parameters that + * have to be updated as part of update_connect_params() call. + * + * @UPDATE_ASSOC_IES: Indicates whether association request IEs are updated + * @UPDATE_FILS_ERP_INFO: Indicates that FILS connection parameters (realm, + * username, erp sequence number and rrk) are updated + * @UPDATE_AUTH_TYPE: Indicates that Authentication type is updated + */ +enum cfg80211_connect_params_changed { + UPDATE_ASSOC_IES = BIT(0), + UPDATE_FILS_ERP_INFO = BIT(1), + UPDATE_AUTH_TYPE = BIT(2), }; /** @@ -1930,29 +2090,33 @@ WIPHY_PARAM_DYN_ACK = 1 << 5, }; -/* - * cfg80211_bitrate_mask - masks for bitrate control - */ -struct cfg80211_bitrate_mask { - struct { - u32 legacy; - u8 ht_mcs[IEEE80211_HT_MCS_MASK_LEN]; - u16 vht_mcs[NL80211_VHT_NSS_MAX]; - enum nl80211_txrate_gi gi; - } control[IEEE80211_NUM_BANDS]; -}; /** * struct cfg80211_pmksa - PMK Security Association * * This structure is passed to the set/del_pmksa() method for PMKSA * caching. * - * @bssid: The AP's BSSID. - * @pmkid: The PMK material itself. + * @bssid: The AP's BSSID (may be %NULL). + * @pmkid: The identifier to refer a PMKSA. + * @pmk: The PMK for the PMKSA identified by @pmkid. This is used for key + * derivation by a FILS STA. Otherwise, %NULL. + * @pmk_len: Length of the @pmk. The length of @pmk can differ depending on + * the hash algorithm used to generate this. + * @ssid: SSID to specify the ESS within which a PMKSA is valid when using FILS + * cache identifier (may be %NULL). + * @ssid_len: Length of the @ssid in octets. + * @cache_id: 2-octet cache identifier advertized by a FILS AP identifying the + * scope of PMKSA. This is valid only if @ssid_len is non-zero (may be + * %NULL). */ struct cfg80211_pmksa { const u8 *bssid; const u8 *pmkid; + const u8 *pmk; + size_t pmk_len; + const u8 *ssid; + size_t ssid_len; + const u8 *cache_id; }; /** @@ -2127,12 +2291,14 @@ /** * struct cfg80211_gtk_rekey_data - rekey data - * @kek: key encryption key (NL80211_KEK_LEN bytes) + * @kek: key encryption key * @kck: key confirmation key (NL80211_KCK_LEN bytes) * @replay_ctr: replay counter (NL80211_REPLAY_CTR_LEN bytes) + * @kek_len: Length of @kek in octets */ struct cfg80211_gtk_rekey_data { const u8 *kek, *kck, *replay_ctr; + size_t kek_len; }; /** @@ -2321,6 +2487,8 @@ * the driver, and will be valid until passed to cfg80211_scan_done(). * For scan results, call cfg80211_inform_bss(); you can call this outside * the scan/scan_done bracket too. + * @abort_scan: Tell the driver to abort an ongoing scan. The driver shall + * indicate the status of the scan through cfg80211_scan_done(). * * @auth: Request to authenticate with the specified peer * (invoked with the wireless_dev mutex held) @@ -2332,9 +2500,31 @@ * (invoked with the wireless_dev mutex held) * * @connect: Connect to the ESS with the specified parameters. When connected, - * call cfg80211_connect_result() with status code %WLAN_STATUS_SUCCESS. - * If the connection fails for some reason, call cfg80211_connect_result() - * with the status from the AP. + * call cfg80211_connect_result()/cfg80211_connect_bss() with status code + * %WLAN_STATUS_SUCCESS. If the connection fails for some reason, call + * cfg80211_connect_result()/cfg80211_connect_bss() with the status code + * from the AP or cfg80211_connect_timeout() if no frame with status code + * was received. + * The driver is allowed to roam to other BSSes within the ESS when the + * other BSS matches the connect parameters. When such roaming is initiated + * by the driver, the driver is expected to verify that the target matches + * the configured security parameters and to use Reassociation Request + * frame instead of Association Request frame. + * The connect function can also be used to request the driver to perform a + * specific roam when connected to an ESS. In that case, the prev_bssid + * parameter is set to the BSSID of the currently associated BSS as an + * indication of requesting reassociation. + * In both the driver-initiated and new connect() call initiated roaming + * cases, the result of roaming is indicated with a call to + * cfg80211_roamed() or cfg80211_roamed_bss(). + * (invoked with the wireless_dev mutex held) + * @update_connect_params: Update the connect parameters while connected to a + * BSS. The updated parameters can be used by driver/firmware for + * subsequent BSS selection (roaming) decisions and to form the + * Authentication/(Re)Association Request frames. This call does not + * request an immediate disassociation or reassociation with the current + * BSS, i.e., this impacts only subsequent (re)associations. The bits in + * changed are defined in &enum cfg80211_connect_params_changed. * (invoked with the wireless_dev mutex held) * @disconnect: Disconnect from the BSS/ESS. * (invoked with the wireless_dev mutex held) @@ -2593,6 +2783,7 @@ int (*scan)(struct wiphy *wiphy, struct cfg80211_scan_request *request); + void (*abort_scan)(struct wiphy *wiphy, struct wireless_dev *wdev); int (*auth)(struct wiphy *wiphy, struct net_device *dev, struct cfg80211_auth_request *req); @@ -2605,6 +2796,10 @@ int (*connect)(struct wiphy *wiphy, struct net_device *dev, struct cfg80211_connect_params *sme); + int (*update_connect_params)(struct wiphy *wiphy, + struct net_device *dev, + struct cfg80211_connect_params *sme, + u32 changed); int (*disconnect)(struct wiphy *wiphy, struct net_device *dev, u16 reason_code); @@ -2799,6 +2994,7 @@ * responds to probe-requests in hardware. * @WIPHY_FLAG_OFFCHAN_TX: Device supports direct off-channel TX. * @WIPHY_FLAG_HAS_REMAIN_ON_CHANNEL: Device supports remain-on-channel call. + * @WIPHY_FLAG_DFS_OFFLOAD: The driver handles all the DFS related operations. * @WIPHY_FLAG_SUPPORTS_5_10_MHZ: Device supports 5 MHz and 10 MHz channels. * @WIPHY_FLAG_HAS_CHANNEL_SWITCH: Device supports channel switch in * beaconing mode (AP, IBSS, Mesh, ...). @@ -2827,6 +3023,7 @@ WIPHY_FLAG_HAS_REMAIN_ON_CHANNEL = BIT(21), WIPHY_FLAG_SUPPORTS_5_10_MHZ = BIT(22), WIPHY_FLAG_HAS_CHANNEL_SWITCH = BIT(23), + WIPHY_FLAG_DFS_OFFLOAD = BIT(24), }; /** @@ -2851,6 +3048,12 @@ * only in special cases. * @radar_detect_widths: bitmap of channel widths supported for radar detection * @radar_detect_regions: bitmap of regions supported for radar detection + * @beacon_int_min_gcd: This interface combination supports different + * beacon intervals. + * = 0 - all beacon intervals for different interface must be same. + * > 0 - any beacon interval for the interface part of this combination AND + * *GCD* of all beacon intervals from beaconing interfaces of this + * combination must be greater or equal to this value. * * With this structure the driver can describe which interface * combinations it supports concurrently. @@ -2909,6 +3112,7 @@ bool beacon_int_infra_match; u8 radar_detect_widths; u8 radar_detect_regions; + u32 beacon_int_min_gcd; }; struct ieee80211_txrx_stypes { @@ -3034,6 +3238,24 @@ }; /** + * struct wiphy_iftype_ext_capab - extended capabilities per interface type + * @iftype: interface type + * @extended_capabilities: extended capabilities supported by the driver, + * additional capabilities might be supported by userspace; these are the + * 802.11 extended capabilities ("Extended Capabilities element") and are + * in the same format as in the information element. See IEEE Std + * 802.11-2012 8.4.2.29 for the defined fields. + * @extended_capabilities_mask: mask of the valid values + * @extended_capabilities_len: length of the extended capabilities + */ +struct wiphy_iftype_ext_capab { + enum nl80211_iftype iftype; + const u8 *extended_capabilities; + const u8 *extended_capabilities_mask; + u8 extended_capabilities_len; +}; + +/** * struct wiphy - wireless hardware description * @reg_notifier: the driver's regulatory notification callback, * note that if your driver uses wiphy_apply_custom_regulatory() @@ -3143,6 +3365,9 @@ * @vht_capa_mod_mask: Specify what VHT capabilities can be over-ridden. * If null, then none can be over-ridden. * + * @wdev_list: the list of associated (virtual) interfaces; this list must + * not be modified by the driver, but can be read with RTNL/RCU protection. + * * @max_acl_mac_addrs: Maximum number of MAC addresses that the device * supports for ACL. * @@ -3150,9 +3375,14 @@ * additional capabilities might be supported by userspace; these are * the 802.11 extended capabilities ("Extended Capabilities element") * and are in the same format as in the information element. See - * 802.11-2012 8.4.2.29 for the defined fields. + * 802.11-2012 8.4.2.29 for the defined fields. These are the default + * extended capabilities to be used if the capabilities are not specified + * for a specific interface type in iftype_ext_capab. * @extended_capabilities_mask: mask of the valid values * @extended_capabilities_len: length of the extended capabilities + * @iftype_ext_capab: array of extended capabilities per interface type + * @num_iftype_ext_capab: number of interface types for which extended + * capabilities are specified separately. * @coalesce: packet coalescing support information * * @vendor_commands: array of vendor commands supported by the hardware @@ -3175,6 +3405,9 @@ * low rssi when a frame is heard on different channel, then it should set * this variable to the maximal offset for which it can compensate. * This value should be set in MHz. + * @bss_select_support: bitmask indicating the BSS selection criteria supported + * by the driver in the .connect() callback. The bit position maps to the + * attribute indices defined in &enum nl80211_bss_select_attr. */ struct wiphy { /* assign these fields before you register the wiphy */ @@ -3249,6 +3482,9 @@ const u8 *extended_capabilities, *extended_capabilities_mask; u8 extended_capabilities_len; + const struct wiphy_iftype_ext_capab *iftype_ext_capab; + unsigned int num_iftype_ext_capab; + /* If multiple wiphys are registered and you're handed e.g. * a regular netdev with assigned ieee80211_ptr, you won't * know whether it points to a wiphy your driver has registered @@ -3279,6 +3515,8 @@ const struct ieee80211_ht_cap *ht_capa_mod_mask; const struct ieee80211_vht_cap *vht_capa_mod_mask; + struct list_head wdev_list; + /* the network namespace this phy lives in currently */ possible_net_t _net; @@ -3297,6 +3535,8 @@ u8 max_num_csa_counters; u8 max_adj_channel_rssi_comp; + u32 bss_select_support; + char priv[0] __aligned(NETDEV_ALIGN); }; @@ -3486,6 +3726,7 @@ * registered for unexpected class 3 frames (AP mode) * @conn: (private) cfg80211 software SME connection state machine data * @connect_keys: (private) keys to set after connection is established + * @conn_bss_type: connecting/connected BSS type * @ibss_fixed: (private) IBSS is using fixed BSSID * @ibss_dfs_possible: (private) IBSS may change to a DFS channel * @event_list: (private) list for internal event processing @@ -3516,6 +3757,7 @@ u8 ssid_len, mesh_id_len, mesh_id_up_len; struct cfg80211_conn *conn; struct cfg80211_cached_keys *connect_keys; + enum ieee80211_bss_type conn_bss_type; struct list_head event_list; spinlock_t event_lock; @@ -3889,6 +4131,32 @@ int regulatory_hint(struct wiphy *wiphy, const char *alpha2); /** + * regulatory_hint_user - hint to the wireless core a regulatory domain + * which the driver has received from an application + * @alpha2: the ISO/IEC 3166 alpha2 the driver claims its regulatory domain + * should be in. If @rd is set this should be NULL. Note that if you + * set this to NULL you should still set rd->alpha2 to some accepted + * alpha2. + * @user_reg_hint_type: the type of user regulatory hint. + * + * Wireless drivers can use this function to hint to the wireless core + * the current regulatory domain as specified by trusted applications, + * it is the driver's responsibilty to estbalish which applications it + * trusts. + * + * The wiphy should be registered to cfg80211 prior to this call. + * For cfg80211 drivers this means you must first use wiphy_register(), + * for mac80211 drivers you must first use ieee80211_register_hw(). + * + * Drivers should check the return value, its possible you can get + * an -ENOMEM or an -EINVAL. + * + * Return: 0 on success. -ENOMEM, -EINVAL. + */ +int regulatory_hint_user(const char *alpha2, + enum nl80211_user_reg_hint_type user_reg_hint_type); + +/** * regulatory_set_wiphy_regd - set regdom info for self managed drivers * @wiphy: the wireless device we want to process the regulatory domain on * @rd: the regulatory domain informatoin to use for this wiphy @@ -4610,6 +4878,134 @@ #endif /** + * struct cfg80211_connect_resp_params - Connection response params + * @status: Status code, %WLAN_STATUS_SUCCESS for successful connection, use + * %WLAN_STATUS_UNSPECIFIED_FAILURE if your device cannot give you + * the real status code for failures. If this call is used to report a + * failure due to a timeout (e.g., not receiving an Authentication frame + * from the AP) instead of an explicit rejection by the AP, -1 is used to + * indicate that this is a failure, but without a status code. + * @timeout_reason is used to report the reason for the timeout in that + * case. + * @bssid: The BSSID of the AP (may be %NULL) + * @bss: Entry of bss to which STA got connected to, can be obtained through + * cfg80211_get_bss() (may be %NULL). Only one parameter among @bssid and + * @bss needs to be specified. + * @req_ie: Association request IEs (may be %NULL) + * @req_ie_len: Association request IEs length + * @resp_ie: Association response IEs (may be %NULL) + * @resp_ie_len: Association response IEs length + * @fils_kek: KEK derived from a successful FILS connection (may be %NULL) + * @fils_kek_len: Length of @fils_kek in octets + * @update_erp_next_seq_num: Boolean value to specify whether the value in + * @fils_erp_next_seq_num is valid. + * @fils_erp_next_seq_num: The next sequence number to use in ERP message in + * FILS Authentication. This value should be specified irrespective of the + * status for a FILS connection. + * @pmk: A new PMK if derived from a successful FILS connection (may be %NULL). + * @pmk_len: Length of @pmk in octets + * @pmkid: A new PMKID if derived from a successful FILS connection or the PMKID + * used for this FILS connection (may be %NULL). + * @timeout_reason: Reason for connection timeout. This is used when the + * connection fails due to a timeout instead of an explicit rejection from + * the AP. %NL80211_TIMEOUT_UNSPECIFIED is used when the timeout reason is + * not known. This value is used only if @status < 0 to indicate that the + * failure is due to a timeout and not due to explicit rejection by the AP. + * This value is ignored in other cases (@status >= 0). + */ +struct cfg80211_connect_resp_params { + int status; + const u8 *bssid; + struct cfg80211_bss *bss; + const u8 *req_ie; + size_t req_ie_len; + const u8 *resp_ie; + size_t resp_ie_len; + const u8 *fils_kek; + size_t fils_kek_len; + bool update_erp_next_seq_num; + u16 fils_erp_next_seq_num; + const u8 *pmk; + size_t pmk_len; + const u8 *pmkid; + enum nl80211_timeout_reason timeout_reason; +}; + +/** + * cfg80211_connect_done - notify cfg80211 of connection result + * + * @dev: network device + * @params: connection response parameters + * @gfp: allocation flags + * + * It should be called by the underlying driver once execution of the connection + * request from connect() has been completed. This is similar to + * cfg80211_connect_bss(), but takes a structure pointer for connection response + * parameters. Only one of the functions among cfg80211_connect_bss(), + * cfg80211_connect_result(), cfg80211_connect_timeout(), + * and cfg80211_connect_done() should be called. + */ +void cfg80211_connect_done(struct net_device *dev, + struct cfg80211_connect_resp_params *params, + gfp_t gfp); + +/** + * cfg80211_connect_bss - notify cfg80211 of connection result + * + * @dev: network device + * @bssid: the BSSID of the AP + * @bss: entry of bss to which STA got connected to, can be obtained + * through cfg80211_get_bss (may be %NULL) + * @req_ie: association request IEs (maybe be %NULL) + * @req_ie_len: association request IEs length + * @resp_ie: association response IEs (may be %NULL) + * @resp_ie_len: assoc response IEs length + * @status: status code, %WLAN_STATUS_SUCCESS for successful connection, use + * %WLAN_STATUS_UNSPECIFIED_FAILURE if your device cannot give you + * the real status code for failures. If this call is used to report a + * failure due to a timeout (e.g., not receiving an Authentication frame + * from the AP) instead of an explicit rejection by the AP, -1 is used to + * indicate that this is a failure, but without a status code. + * @timeout_reason is used to report the reason for the timeout in that + * case. + * @gfp: allocation flags + * @timeout_reason: reason for connection timeout. This is used when the + * connection fails due to a timeout instead of an explicit rejection from + * the AP. %NL80211_TIMEOUT_UNSPECIFIED is used when the timeout reason is + * not known. This value is used only if @status < 0 to indicate that the + * failure is due to a timeout and not due to explicit rejection by the AP. + * This value is ignored in other cases (@status >= 0). + * + * It should be called by the underlying driver once execution of the connection + * request from connect() has been completed. This is similar to + * cfg80211_connect_result(), but with the option of identifying the exact bss + * entry for the connection. Only one of the functions among + * cfg80211_connect_bss(), cfg80211_connect_result(), + * cfg80211_connect_timeout(), and cfg80211_connect_done() should be called. + */ +static inline void +cfg80211_connect_bss(struct net_device *dev, const u8 *bssid, + struct cfg80211_bss *bss, const u8 *req_ie, + size_t req_ie_len, const u8 *resp_ie, + size_t resp_ie_len, int status, gfp_t gfp, + enum nl80211_timeout_reason timeout_reason) +{ + struct cfg80211_connect_resp_params params; + + memset(¶ms, 0, sizeof(params)); + params.status = status; + params.bssid = bssid; + params.bss = bss; + params.req_ie = req_ie; + params.req_ie_len = req_ie_len; + params.resp_ie = resp_ie; + params.resp_ie_len = resp_ie_len; + params.timeout_reason = timeout_reason; + + cfg80211_connect_done(dev, ¶ms, gfp); +} + +/** * cfg80211_connect_result - notify cfg80211 of connection result * * @dev: network device @@ -4618,18 +5014,54 @@ * @req_ie_len: association request IEs length * @resp_ie: association response IEs (may be %NULL) * @resp_ie_len: assoc response IEs length - * @status: status code, 0 for successful connection, use + * @status: status code, %WLAN_STATUS_SUCCESS for successful connection, use * %WLAN_STATUS_UNSPECIFIED_FAILURE if your device cannot give you * the real status code for failures. * @gfp: allocation flags * - * It should be called by the underlying driver whenever connect() has - * succeeded. + * It should be called by the underlying driver once execution of the connection + * request from connect() has been completed. This is similar to + * cfg80211_connect_bss() which allows the exact bss entry to be specified. Only + * one of the functions among cfg80211_connect_bss(), cfg80211_connect_result(), + * cfg80211_connect_timeout(), and cfg80211_connect_done() should be called. */ -void cfg80211_connect_result(struct net_device *dev, const u8 *bssid, +static inline void +cfg80211_connect_result(struct net_device *dev, const u8 *bssid, const u8 *req_ie, size_t req_ie_len, const u8 *resp_ie, size_t resp_ie_len, - u16 status, gfp_t gfp); + u16 status, gfp_t gfp) +{ + cfg80211_connect_bss(dev, bssid, NULL, req_ie, req_ie_len, resp_ie, + resp_ie_len, status, gfp, + NL80211_TIMEOUT_UNSPECIFIED); +} + +/** + * cfg80211_connect_timeout - notify cfg80211 of connection timeout + * + * @dev: network device + * @bssid: the BSSID of the AP + * @req_ie: association request IEs (maybe be %NULL) + * @req_ie_len: association request IEs length + * @gfp: allocation flags + * @timeout_reason: reason for connection timeout. + * + * It should be called by the underlying driver whenever connect() has failed + * in a sequence where no explicit authentication/association rejection was + * received from the AP. This could happen, e.g., due to not being able to send + * out the Authentication or Association Request frame or timing out while + * waiting for the response. Only one of the functions among + * cfg80211_connect_bss(), cfg80211_connect_result(), + * cfg80211_connect_timeout(), and cfg80211_connect_done() should be called. + */ +static inline void +cfg80211_connect_timeout(struct net_device *dev, const u8 *bssid, + const u8 *req_ie, size_t req_ie_len, gfp_t gfp, + enum nl80211_timeout_reason timeout_reason) +{ + cfg80211_connect_bss(dev, bssid, NULL, req_ie, req_ie_len, NULL, 0, -1, + gfp, timeout_reason); +} /** * cfg80211_roamed - notify cfg80211 of roaming @@ -5215,6 +5647,16 @@ void cfg80211_crit_proto_stopped(struct wireless_dev *wdev, gfp_t gfp); /** + * cfg80211_is_gratuitous_arp_unsolicited_na - packet is grat. ARP/unsol. NA + * @skb: the input packet, must be an ethernet frame already + * + * Return: %true if the packet is a gratuitous ARP or unsolicited NA packet. + * This is used to drop packets that shouldn't occur because the AP implements + * a proxy service. + */ +bool cfg80211_is_gratuitous_arp_unsolicited_na(struct sk_buff *skb); + +/** * ieee80211_get_num_supported_channels - get number of channels device has * @wiphy: the wiphy * @@ -5226,36 +5668,20 @@ * cfg80211_check_combinations - check interface combinations * * @wiphy: the wiphy - * @num_different_channels: the number of different channels we want - * to use for verification - * @radar_detect: a bitmap where each bit corresponds to a channel - * width where radar detection is needed, as in the definition of - * &struct ieee80211_iface_combination.@radar_detect_widths - * @iftype_num: array with the numbers of interfaces of each interface - * type. The index is the interface type as specified in &enum - * nl80211_iftype. + * @params: the interface combinations parameter * * This function can be called by the driver to check whether a * combination of interfaces and their types are allowed according to * the interface combinations. */ int cfg80211_check_combinations(struct wiphy *wiphy, - const int num_different_channels, - const u8 radar_detect, - const int iftype_num[NUM_NL80211_IFTYPES]); + struct iface_combination_params *params); /** * cfg80211_iter_combinations - iterate over matching combinations * * @wiphy: the wiphy - * @num_different_channels: the number of different channels we want - * to use for verification - * @radar_detect: a bitmap where each bit corresponds to a channel - * width where radar detection is needed, as in the definition of - * &struct ieee80211_iface_combination.@radar_detect_widths - * @iftype_num: array with the numbers of interfaces of each interface - * type. The index is the interface type as specified in &enum - * nl80211_iftype. + * @params: the interface combinations parameter * @iter: function to call for each matching combination * @data: pointer to pass to iter function * @@ -5264,9 +5690,7 @@ * purposes. */ int cfg80211_iter_combinations(struct wiphy *wiphy, - const int num_different_channels, - const u8 radar_detect, - const int iftype_num[NUM_NL80211_IFTYPES], + struct iface_combination_params *params, void (*iter)(const struct ieee80211_iface_combination *c, void *data), void *data); @@ -5340,6 +5764,13 @@ /* ethtool helper */ void cfg80211_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info); +/** + * cfg80211_ap_stopped - notify userspace that AP mode stopped + * @netdev: network device + * @gfp: context flags + */ +void cfg80211_ap_stopped(struct net_device *netdev, gfp_t gfp); + /* Logging, debugging and troubleshooting/diagnostic helpers. */ /* wiphy_printk helpers, similar to dev_printk */ diff -ruw linux-4.4.115/include/net/fib_rules.h linux-4.4.115-fbx/include/net/fib_rules.h --- linux-4.4.115/include/net/fib_rules.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/net/fib_rules.h 2019-01-22 16:16:28.451291214 +0100 @@ -8,6 +8,11 @@ #include #include +struct fib_kuid_range { + kuid_t start; + kuid_t end; +}; + struct fib_rule { struct list_head list; int iifindex; @@ -29,6 +34,7 @@ int suppress_prefixlen; char iifname[IFNAMSIZ]; char oifname[IFNAMSIZ]; + struct fib_kuid_range uid_range; struct rcu_head rcu; }; @@ -89,7 +95,8 @@ [FRA_TABLE] = { .type = NLA_U32 }, \ [FRA_SUPPRESS_PREFIXLEN] = { .type = NLA_U32 }, \ [FRA_SUPPRESS_IFGROUP] = { .type = NLA_U32 }, \ - [FRA_GOTO] = { .type = NLA_U32 } + [FRA_GOTO] = { .type = NLA_U32 }, \ + [FRA_UID_RANGE] = { .len = sizeof(struct fib_rule_uid_range) } static inline void fib_rule_get(struct fib_rule *rule) { diff -ruw linux-4.4.115/include/net/flow.h linux-4.4.115-fbx/include/net/flow.h --- linux-4.4.115/include/net/flow.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/net/flow.h 2019-01-22 16:16:28.451291214 +0100 @@ -11,6 +11,7 @@ #include #include #include +#include /* * ifindex generation is per-net namespace, and loopback is @@ -38,6 +39,7 @@ #define FLOWI_FLAG_SKIP_NH_OIF 0x08 __u32 flowic_secid; struct flowi_tunnel flowic_tun_key; + kuid_t flowic_uid; }; union flowi_uli { @@ -75,6 +77,7 @@ #define flowi4_flags __fl_common.flowic_flags #define flowi4_secid __fl_common.flowic_secid #define flowi4_tun_key __fl_common.flowic_tun_key +#define flowi4_uid __fl_common.flowic_uid /* (saddr,daddr) must be grouped, same order as in IP header */ __be32 saddr; @@ -94,7 +97,8 @@ __u32 mark, __u8 tos, __u8 scope, __u8 proto, __u8 flags, __be32 daddr, __be32 saddr, - __be16 dport, __be16 sport) + __be16 dport, __be16 sport, + kuid_t uid) { fl4->flowi4_oif = oif; fl4->flowi4_iif = LOOPBACK_IFINDEX; @@ -105,6 +109,7 @@ fl4->flowi4_flags = flags; fl4->flowi4_secid = 0; fl4->flowi4_tun_key.tun_id = 0; + fl4->flowi4_uid = uid; fl4->daddr = daddr; fl4->saddr = saddr; fl4->fl4_dport = dport; @@ -133,6 +138,7 @@ #define flowi6_flags __fl_common.flowic_flags #define flowi6_secid __fl_common.flowic_secid #define flowi6_tun_key __fl_common.flowic_tun_key +#define flowi6_uid __fl_common.flowic_uid struct in6_addr daddr; struct in6_addr saddr; __be32 flowlabel; @@ -177,6 +183,7 @@ #define flowi_flags u.__fl_common.flowic_flags #define flowi_secid u.__fl_common.flowic_secid #define flowi_tun_key u.__fl_common.flowic_tun_key +#define flowi_uid u.__fl_common.flowic_uid } __attribute__((__aligned__(BITS_PER_LONG/8))); static inline struct flowi *flowi4_to_flowi(struct flowi4 *fl4) diff -ruw linux-4.4.115/include/net/if_inet6.h linux-4.4.115-fbx/include/net/if_inet6.h --- linux-4.4.115/include/net/if_inet6.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/net/if_inet6.h 2019-01-22 16:16:28.455291250 +0100 @@ -201,6 +201,7 @@ struct ipv6_devstat stats; struct timer_list rs_timer; + __s32 rs_interval; /* in jiffies */ __u8 rs_probes; __u8 addr_gen_mode; diff -ruw linux-4.4.115/include/net/ip6_route.h linux-4.4.115-fbx/include/net/ip6_route.h --- linux-4.4.115/include/net/ip6_route.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/net/ip6_route.h 2019-01-22 16:16:28.455291250 +0100 @@ -118,9 +118,10 @@ const struct in6_addr *gwaddr); void ip6_update_pmtu(struct sk_buff *skb, struct net *net, __be32 mtu, int oif, - u32 mark); + u32 mark, kuid_t uid); void ip6_sk_update_pmtu(struct sk_buff *skb, struct sock *sk, __be32 mtu); -void ip6_redirect(struct sk_buff *skb, struct net *net, int oif, u32 mark); +void ip6_redirect(struct sk_buff *skb, struct net *net, int oif, u32 mark, + kuid_t uid); void ip6_redirect_no_header(struct sk_buff *skb, struct net *net, int oif, u32 mark); void ip6_sk_redirect(struct sk_buff *skb, struct sock *sk); diff -ruw linux-4.4.115/include/net/ip.h linux-4.4.115-fbx/include/net/ip.h --- linux-4.4.115/include/net/ip.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/net/ip.h 2019-10-29 09:26:25.509221439 +0100 @@ -172,6 +172,7 @@ /* -1 if not needed */ int bound_dev_if; u8 tos; + kuid_t uid; }; #define IP_REPLY_ARG_NOSRCCHECK 1 @@ -242,6 +243,8 @@ } #endif +extern int sysctl_reserved_port_bind; + /* From inetpeer.c */ extern int inet_peer_threshold; extern int inet_peer_minttl; diff -ruw linux-4.4.115/include/net/l3mdev.h linux-4.4.115-fbx/include/net/l3mdev.h --- linux-4.4.115/include/net/l3mdev.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/net/l3mdev.h 2019-01-22 16:16:28.459291286 +0100 @@ -51,6 +51,24 @@ return ifindex; } +static inline int l3mdev_master_ifindex_by_index(struct net *net, int ifindex) +{ + struct net_device *dev; + int rc = 0; + + if (likely(ifindex)) { + rcu_read_lock(); + + dev = dev_get_by_index_rcu(net, ifindex); + if (dev) + rc = l3mdev_master_ifindex_rcu(dev); + + rcu_read_unlock(); + } + + return rc; +} + /* get index of an interface to use for FIB lookups. For devices * enslaved to an L3 master device FIB lookups are based on the * master index @@ -169,6 +187,11 @@ { return 0; } + +static inline int l3mdev_master_ifindex_by_index(struct net *net, int ifindex) +{ + return 0; +} static inline int l3mdev_fib_oif_rcu(struct net_device *dev) { diff -ruw linux-4.4.115/include/net/mac80211.h linux-4.4.115-fbx/include/net/mac80211.h --- linux-4.4.115/include/net/mac80211.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/net/mac80211.h 2019-10-29 09:26:25.513221478 +0100 @@ -1014,6 +1014,14 @@ * @RX_FLAG_AMPDU_DELIM_CRC_KNOWN: The delimiter CRC field is known (the CRC * is stored in the @ampdu_delimiter_crc field) * @RX_FLAG_LDPC: LDPC was used + * @RX_FLAG_ONLY_MONITOR: Report frame only to monitor interfaces without + * processing it in any regular way. + * This is useful if drivers offload some frames but still want to report + * them for sniffing purposes. + * @RX_FLAG_SKIP_MONITOR: Process and report frame to all interfaces except + * monitor interfaces. + * This is useful if drivers offload some frames but still want to report + * them for sniffing purposes. * @RX_FLAG_STBC_MASK: STBC 2 bit bitmask. 1 - Nss=1, 2 - Nss=2, 3 - Nss=3 * @RX_FLAG_10MHZ: 10 MHz (half channel) was used * @RX_FLAG_5MHZ: 5 MHz (quarter channel) was used @@ -1054,6 +1062,8 @@ RX_FLAG_MACTIME_END = BIT(21), RX_FLAG_VHT = BIT(22), RX_FLAG_LDPC = BIT(23), + RX_FLAG_ONLY_MONITOR = BIT(24), + RX_FLAG_SKIP_MONITOR = BIT(25), RX_FLAG_STBC_MASK = BIT(26) | BIT(27), RX_FLAG_10MHZ = BIT(28), RX_FLAG_5MHZ = BIT(29), @@ -1072,6 +1082,7 @@ * @RX_VHT_FLAG_160MHZ: 160 MHz was used * @RX_VHT_FLAG_BF: packet was beamformed */ + enum mac80211_rx_vht_flags { RX_VHT_FLAG_80MHZ = BIT(0), RX_VHT_FLAG_160MHZ = BIT(1), @@ -3773,11 +3784,12 @@ * This function must be called with BHs disabled. * * @hw: the hardware this frame came in on + * @sta: the station the frame was received from, or %NULL * @skb: the buffer to receive, owned by mac80211 after this call * @napi: the NAPI context */ -void ieee80211_rx_napi(struct ieee80211_hw *hw, struct sk_buff *skb, - struct napi_struct *napi); +void ieee80211_rx_napi(struct ieee80211_hw *hw, struct ieee80211_sta *sta, + struct sk_buff *skb, struct napi_struct *napi); /** * ieee80211_rx - receive frame @@ -3801,7 +3813,7 @@ */ static inline void ieee80211_rx(struct ieee80211_hw *hw, struct sk_buff *skb) { - ieee80211_rx_napi(hw, skb, NULL); + ieee80211_rx_napi(hw, NULL, skb, NULL); } /** @@ -5489,4 +5501,19 @@ */ struct sk_buff *ieee80211_tx_dequeue(struct ieee80211_hw *hw, struct ieee80211_txq *txq); + +/** + * ieee80211_txq_get_depth - get pending frame/byte count of given txq + * + * The values are not guaranteed to be coherent with regard to each other, i.e. + * txq state can change half-way of this function and the caller may end up + * with "new" frame_cnt and "old" byte_cnt or vice-versa. + * + * @txq: pointer obtained from station or virtual interface + * @frame_cnt: pointer to store frame count + * @byte_cnt: pointer to store byte count + */ +void ieee80211_txq_get_depth(struct ieee80211_txq *txq, + unsigned long *frame_cnt, + unsigned long *byte_cnt); #endif /* MAC80211_H */ diff -ruw linux-4.4.115/include/net/pkt_sched.h linux-4.4.115-fbx/include/net/pkt_sched.h --- linux-4.4.115/include/net/pkt_sched.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/net/pkt_sched.h 2019-01-22 16:16:28.471291395 +0100 @@ -124,6 +124,8 @@ return skb->protocol; } +extern int tc_qdisc_flow_control(struct net_device *dev, u32 tcm_handle, + int flow_enable); /* Calculate maximal size of packet seen by hard_start_xmit routine of this device. */ diff -ruw linux-4.4.115/include/net/route.h linux-4.4.115-fbx/include/net/route.h --- linux-4.4.115/include/net/route.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/net/route.h 2019-10-29 09:26:25.517221517 +0100 @@ -154,7 +154,7 @@ flowi4_init_output(fl4, oif, sk ? sk->sk_mark : 0, tos, RT_SCOPE_UNIVERSE, proto, sk ? inet_sk_flowi_flags(sk) : 0, - daddr, saddr, dport, sport); + daddr, saddr, dport, sport, sock_net_uid(net, sk)); if (sk) security_sk_classify_flow(sk, flowi4_to_flowi(fl4)); return ip_route_output_flow(net, fl4, sk); @@ -267,7 +267,8 @@ flow_flags |= FLOWI_FLAG_ANYSRC; flowi4_init_output(fl4, oif, sk->sk_mark, tos, RT_SCOPE_UNIVERSE, - protocol, flow_flags, dst, src, dport, sport); + protocol, flow_flags, dst, src, dport, sport, + sk->sk_uid); } static inline struct rtable *ip_route_connect(struct flowi4 *fl4, diff -ruw linux-4.4.115/include/net/sock.h linux-4.4.115-fbx/include/net/sock.h --- linux-4.4.115/include/net/sock.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/net/sock.h 2019-10-29 09:26:25.521221556 +0100 @@ -446,6 +446,7 @@ void *sk_security; #endif __u32 sk_mark; + kuid_t sk_uid; #ifdef CONFIG_CGROUP_NET_CLASSID u32 sk_classid; #endif @@ -457,6 +458,7 @@ int (*sk_backlog_rcv)(struct sock *sk, struct sk_buff *skb); void (*sk_destruct)(struct sock *sk); + struct rcu_head sk_rcu; }; #define __sk_user_data(sk) ((*((void __rcu **)&(sk)->sk_user_data))) @@ -739,6 +741,7 @@ */ SOCK_FILTER_LOCKED, /* Filter cannot be changed anymore */ SOCK_SELECT_ERR_QUEUE, /* Wake select on error queue */ + SOCK_RCU_FREE, /* wait rcu grace period in sk_destruct() */ }; #define SK_FLAGS_TIMESTAMP ((1UL << SOCK_TIMESTAMP) | (1UL << SOCK_TIMESTAMPING_RX_SOFTWARE)) @@ -1067,6 +1070,7 @@ void (*destroy_cgroup)(struct mem_cgroup *memcg); struct cg_proto *(*proto_cgroup)(struct mem_cgroup *memcg); #endif + int (*diag_destroy)(struct sock *sk, int err); }; int proto_register(struct proto *prot, int alloc_slab); @@ -1691,6 +1695,7 @@ sk->sk_wq = parent->wq; parent->sk = sk; sk_set_socket(sk, parent); + sk->sk_uid = SOCK_INODE(parent)->i_uid; security_sock_graft(sk, parent); write_unlock_bh(&sk->sk_callback_lock); } @@ -1698,6 +1703,11 @@ kuid_t sock_i_uid(struct sock *sk); unsigned long sock_i_ino(struct sock *sk); +static inline kuid_t sock_net_uid(const struct net *net, const struct sock *sk) +{ + return sk ? sk->sk_uid : make_kuid(net->user_ns, 0); +} + static inline u32 net_tx_rndhash(void) { u32 v = prandom_u32(); @@ -2302,4 +2312,15 @@ extern __u32 sysctl_wmem_default; extern __u32 sysctl_rmem_default; +/* SOCKEV Notifier Events */ +#define SOCKEV_SOCKET 0x00 +#define SOCKEV_BIND 0x01 +#define SOCKEV_LISTEN 0x02 +#define SOCKEV_ACCEPT 0x03 +#define SOCKEV_CONNECT 0x04 +#define SOCKEV_SHUTDOWN 0x05 + +int sockev_register_notify(struct notifier_block *nb); +int sockev_unregister_notify(struct notifier_block *nb); + #endif /* _SOCK_H */ diff -ruw linux-4.4.115/include/net/tcp.h linux-4.4.115-fbx/include/net/tcp.h --- linux-4.4.115/include/net/tcp.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/net/tcp.h 2019-10-29 09:26:25.521221556 +0100 @@ -141,6 +141,9 @@ * most likely due to retrans in 3WHS. */ +/* Number of full MSS to receive before Acking RFC2581 */ +#define TCP_DELACK_SEG 1 + #define TCP_RESOURCE_PROBE_INTERVAL ((unsigned)(HZ/2U)) /* Maximal interval between probes * for local resources. */ @@ -284,8 +287,14 @@ extern int sysctl_tcp_invalid_ratelimit; extern int sysctl_tcp_pacing_ss_ratio; extern int sysctl_tcp_pacing_ca_ratio; +extern int sysctl_tcp_default_init_rwnd; extern atomic_long_t tcp_memory_allocated; + +/* sysctl variables for controlling various tcp parameters */ +extern int sysctl_tcp_delack_seg; +extern int sysctl_tcp_use_userconfig; + extern struct percpu_counter tcp_sockets_allocated; extern int tcp_memory_pressure; @@ -376,6 +385,12 @@ struct pipe_inode_info *pipe, size_t len, unsigned int flags); +/* sysctl master controller */ +extern int tcp_use_userconfig_sysctl_handler(struct ctl_table *, int, + void __user *, size_t *, loff_t *); +extern int tcp_proc_delayed_ack_control(struct ctl_table *, int, + void __user *, size_t *, loff_t *); + static inline void tcp_dec_quickack_mode(struct sock *sk, const unsigned int pkts) { @@ -1171,6 +1186,8 @@ void tcp_done(struct sock *sk); +int tcp_abort(struct sock *sk, int err); + static inline void tcp_sack_reset(struct tcp_options_received *rx_opt) { rx_opt->dsack = 0; diff -ruw linux-4.4.115/include/net/udp.h linux-4.4.115-fbx/include/net/udp.h --- linux-4.4.115/include/net/udp.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/net/udp.h 2019-01-22 16:16:28.479291467 +0100 @@ -238,6 +238,7 @@ int (*saddr_cmp)(const struct sock *, const struct sock *)); void udp_err(struct sk_buff *, u32); +int udp_abort(struct sock *sk, int err); int udp_sendmsg(struct sock *sk, struct msghdr *msg, size_t len); int udp_push_pending_frames(struct sock *sk); void udp_flush_pending_frames(struct sock *sk); diff -ruw linux-4.4.115/include/net/xfrm.h linux-4.4.115-fbx/include/net/xfrm.h --- linux-4.4.115/include/net/xfrm.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/net/xfrm.h 2019-10-29 09:26:25.525221596 +0100 @@ -159,6 +159,7 @@ int header_len; int trailer_len; u32 extra_flags; + u32 output_mark; } props; struct xfrm_lifetime_cfg lft; @@ -288,10 +289,12 @@ struct dst_entry *(*dst_lookup)(struct net *net, int tos, int oif, const xfrm_address_t *saddr, - const xfrm_address_t *daddr); + const xfrm_address_t *daddr, + u32 mark); int (*get_saddr)(struct net *net, int oif, xfrm_address_t *saddr, - xfrm_address_t *daddr); + xfrm_address_t *daddr, + u32 mark); void (*decode_session)(struct sk_buff *skb, struct flowi *fl, int reverse); diff -ruw linux-4.4.115/include/scsi/scsi_device.h linux-4.4.115-fbx/include/scsi/scsi_device.h --- linux-4.4.115/include/scsi/scsi_device.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/scsi/scsi_device.h 2019-10-29 09:26:25.525221596 +0100 @@ -175,6 +175,10 @@ unsigned no_dif:1; /* T10 PI (DIF) should be disabled */ unsigned broken_fua:1; /* Don't set FUA bit */ unsigned lun_in_cdb:1; /* Store LUN bits in CDB[1] */ + unsigned use_rpm_auto:1; /* Enable runtime PM auto suspend */ + +#define SCSI_DEFAULT_AUTOSUSPEND_DELAY -1 + int autosuspend_delay; atomic_t disk_events_disable_depth; /* disable depth for disk events */ diff -ruw linux-4.4.115/include/scsi/scsi.h linux-4.4.115-fbx/include/scsi/scsi.h --- linux-4.4.115/include/scsi/scsi.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/scsi/scsi.h 2019-01-22 16:16:28.491291576 +0100 @@ -8,6 +8,7 @@ #include #include #include +#include #include #include @@ -306,4 +307,9 @@ return (ptr[0]<<24) + (ptr[1]<<16) + (ptr[2]<<8) + ptr[3]; } +struct scsi_disk *scsi_disk_get_from_dev(struct device *dev); + +struct gendisk *scsi_gendisk_get_from_dev(struct device *dev); +void scsi_gendisk_put(struct device *dev); + #endif /* _SCSI_SCSI_H */ diff -ruw linux-4.4.115/include/scsi/scsi_host.h linux-4.4.115-fbx/include/scsi/scsi_host.h --- linux-4.4.115/include/scsi/scsi_host.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/scsi/scsi_host.h 2019-01-22 16:16:28.491291576 +0100 @@ -672,6 +672,12 @@ unsigned short_inquiry:1; /* + * Set "DBD" field in mode_sense caching mode page in case it is + * mandatory by LLD standard. + */ + unsigned set_dbd_for_caching:1; + + /* * Optional work queue to be utilized by the transport */ char work_q_name[20]; diff -ruw linux-4.4.115/include/sound/compress_driver.h linux-4.4.115-fbx/include/sound/compress_driver.h --- linux-4.4.115/include/sound/compress_driver.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/sound/compress_driver.h 2019-10-29 09:26:25.533221674 +0100 @@ -82,6 +82,7 @@ bool metadata_set; bool next_track; void *private_data; + struct snd_soc_pcm_runtime *be; }; /** @@ -96,6 +97,8 @@ * @get_params: retrieve the codec parameters, mandatory * @set_metadata: Set the metadata values for a stream * @get_metadata: retrieves the requested metadata values from stream + * @set_next_track_param: send codec specific data of subsequent track + * in gapless * @trigger: Trigger operations like start, pause, resume, drain, stop. * This callback is mandatory * @pointer: Retrieve current h/w pointer information. Mandatory @@ -118,6 +121,8 @@ struct snd_compr_metadata *metadata); int (*get_metadata)(struct snd_compr_stream *stream, struct snd_compr_metadata *metadata); + int (*set_next_track_param)(struct snd_compr_stream *stream, + union snd_codec_options *codec_options); int (*trigger)(struct snd_compr_stream *stream, int cmd); int (*pointer)(struct snd_compr_stream *stream, struct snd_compr_tstamp *tstamp); @@ -159,6 +164,7 @@ int snd_compress_deregister(struct snd_compr *device); int snd_compress_new(struct snd_card *card, int device, int type, struct snd_compr *compr); +void snd_compress_free(struct snd_card *card, struct snd_compr *compr); /* dsp driver callback apis * For playback: driver should call snd_compress_fragment_elapsed() to let the diff -ruw linux-4.4.115/include/sound/core.h linux-4.4.115-fbx/include/sound/core.h --- linux-4.4.115/include/sound/core.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/sound/core.h 2019-01-22 16:16:28.503291684 +0100 @@ -134,6 +134,9 @@ struct device card_dev; /* cardX object for sysfs */ const struct attribute_group *dev_groups[4]; /* assigned sysfs attr */ bool registered; /* card_dev is registered? */ + int offline; /* if this sound card is offline */ + unsigned long offline_change; + wait_queue_head_t offline_poll_wait; #ifdef CONFIG_PM unsigned int power_state; /* power state */ @@ -265,6 +268,8 @@ int snd_card_file_add(struct snd_card *card, struct file *file); int snd_card_file_remove(struct snd_card *card, struct file *file); #define snd_card_unref(card) put_device(&(card)->card_dev) +void snd_card_change_online_state(struct snd_card *card, int online); +bool snd_card_is_online_state(struct snd_card *card); #define snd_card_set_dev(card, devptr) ((card)->dev = (devptr)) diff -ruw linux-4.4.115/include/sound/info.h linux-4.4.115-fbx/include/sound/info.h --- linux-4.4.115/include/sound/info.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/sound/info.h 2019-01-22 16:16:28.507291721 +0100 @@ -161,7 +161,9 @@ } int snd_info_check_reserved_words(const char *str); - +struct snd_info_entry *snd_register_module_info(struct module *module, + const char *name, + struct snd_info_entry *parent); #else #define snd_seq_root NULL @@ -190,7 +192,9 @@ void *private_data, void (*read)(struct snd_info_entry *, struct snd_info_buffer *)) {} static inline int snd_info_check_reserved_words(const char *str) { return 1; } - +static inline struct snd_info_entry *snd_register_module_info( + struct module *module, const char *name, + struct snd_info_entry *parent) { return NULL; } #endif /* diff -ruw linux-4.4.115/include/sound/jack.h linux-4.4.115-fbx/include/sound/jack.h --- linux-4.4.115/include/sound/jack.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/sound/jack.h 2019-01-22 16:16:28.507291721 +0100 @@ -58,14 +58,20 @@ SND_JACK_VIDEOOUT = 0x0010, SND_JACK_AVOUT = SND_JACK_LINEOUT | SND_JACK_VIDEOOUT, SND_JACK_LINEIN = 0x0020, + SND_JACK_OC_HPHL = 0x0040, + SND_JACK_OC_HPHR = 0x0080, + SND_JACK_UNSUPPORTED = 0x0100, + SND_JACK_MICROPHONE2 = 0x0200, + SND_JACK_ANC_HEADPHONE = SND_JACK_HEADPHONE | SND_JACK_MICROPHONE | + SND_JACK_MICROPHONE2, /* Kept separate from switches to facilitate implementation */ - SND_JACK_BTN_0 = 0x4000, - SND_JACK_BTN_1 = 0x2000, - SND_JACK_BTN_2 = 0x1000, - SND_JACK_BTN_3 = 0x0800, - SND_JACK_BTN_4 = 0x0400, - SND_JACK_BTN_5 = 0x0200, + SND_JACK_BTN_0 = 0x8000, + SND_JACK_BTN_1 = 0x4000, + SND_JACK_BTN_2 = 0x2000, + SND_JACK_BTN_3 = 0x1000, + SND_JACK_BTN_4 = 0x0800, + SND_JACK_BTN_5 = 0x0400, }; /* Keep in sync with definitions above */ diff -ruw linux-4.4.115/include/sound/pcm.h linux-4.4.115-fbx/include/sound/pcm.h --- linux-4.4.115/include/sound/pcm.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/sound/pcm.h 2019-01-22 16:16:28.507291721 +0100 @@ -68,6 +68,8 @@ int (*close)(struct snd_pcm_substream *substream); int (*ioctl)(struct snd_pcm_substream * substream, unsigned int cmd, void *arg); + int (*compat_ioctl)(struct snd_pcm_substream *substream, + unsigned int cmd, void *arg); int (*hw_params)(struct snd_pcm_substream *substream, struct snd_pcm_hw_params *params); int (*hw_free)(struct snd_pcm_substream *substream); @@ -78,6 +80,9 @@ struct timespec *system_ts, struct timespec *audio_ts, struct snd_pcm_audio_tstamp_config *audio_tstamp_config, struct snd_pcm_audio_tstamp_report *audio_tstamp_report); + int (*delay_blk)(struct snd_pcm_substream *substream); + int (*wall_clock)(struct snd_pcm_substream *substream, + struct timespec *audio_ts); int (*copy)(struct snd_pcm_substream *substream, int channel, snd_pcm_uframes_t pos, void __user *buf, snd_pcm_uframes_t count); @@ -87,6 +92,7 @@ unsigned long offset); int (*mmap)(struct snd_pcm_substream *substream, struct vm_area_struct *vma); int (*ack)(struct snd_pcm_substream *substream); + int (*restart)(struct snd_pcm_substream *substream); }; /* @@ -100,7 +106,7 @@ #endif #define SNDRV_PCM_IOCTL1_RESET 0 -#define SNDRV_PCM_IOCTL1_INFO 1 +/* 1 is absent slot. */ #define SNDRV_PCM_IOCTL1_CHANNEL_INFO 2 #define SNDRV_PCM_IOCTL1_GSTATE 3 #define SNDRV_PCM_IOCTL1_FIFO_SIZE 4 @@ -115,6 +121,12 @@ #define SNDRV_PCM_POS_XRUN ((snd_pcm_uframes_t)-1) +#define SNDRV_DMA_MODE (0) +#define SNDRV_NON_DMA_MODE (1 << 0) +#define SNDRV_RENDER_STOPPED (1 << 1) +#define SNDRV_RENDER_RUNNING (1 << 2) + + /* If you change this don't forget to change rates[] table in pcm_native.c */ #define SNDRV_PCM_RATE_5512 (1<<0) /* 5512Hz */ #define SNDRV_PCM_RATE_8000 (1<<1) /* 8000Hz */ @@ -129,6 +141,8 @@ #define SNDRV_PCM_RATE_96000 (1<<10) /* 96000Hz */ #define SNDRV_PCM_RATE_176400 (1<<11) /* 176400Hz */ #define SNDRV_PCM_RATE_192000 (1<<12) /* 192000Hz */ +#define SNDRV_PCM_RATE_352800 (1<<13) /* 352800Hz */ +#define SNDRV_PCM_RATE_384000 (1<<14) /* 384000Hz */ #define SNDRV_PCM_RATE_CONTINUOUS (1<<30) /* continuous range */ #define SNDRV_PCM_RATE_KNOT (1<<31) /* supports more non-continuos rates */ @@ -141,6 +155,9 @@ SNDRV_PCM_RATE_88200|SNDRV_PCM_RATE_96000) #define SNDRV_PCM_RATE_8000_192000 (SNDRV_PCM_RATE_8000_96000|SNDRV_PCM_RATE_176400|\ SNDRV_PCM_RATE_192000) +#define SNDRV_PCM_RATE_8000_384000 (SNDRV_PCM_RATE_8000_192000|\ + SNDRV_PCM_RATE_352800|\ + SNDRV_PCM_RATE_384000) #define _SNDRV_PCM_FMTBIT(fmt) (1ULL << (__force int)SNDRV_PCM_FORMAT_##fmt) #define SNDRV_PCM_FMTBIT_S8 _SNDRV_PCM_FMTBIT(S8) #define SNDRV_PCM_FMTBIT_U8 _SNDRV_PCM_FMTBIT(U8) @@ -368,6 +385,7 @@ unsigned int rate_num; unsigned int rate_den; unsigned int no_period_wakeup: 1; + unsigned int render_flag; /* -- SW params -- */ int tstamp_mode; /* mmap timestamp is updated */ @@ -448,6 +466,7 @@ const struct snd_pcm_ops *ops; /* -- runtime information -- */ struct snd_pcm_runtime *runtime; + spinlock_t runtime_lock; /* -- timer section -- */ struct snd_timer *timer; /* timer */ unsigned timer_running: 1; /* time is running */ @@ -482,6 +501,7 @@ #endif /* CONFIG_SND_VERBOSE_PROCFS */ /* misc flags */ unsigned int hw_opened: 1; + unsigned int hw_no_buffer: 1; /* substream may not have a buffer */ }; #define SUBSTREAM_BUSY(substream) ((substream)->ref_count > 0) @@ -507,6 +527,8 @@ #endif #endif struct snd_kcontrol *chmap_kctl; /* channel-mapping controls */ + struct snd_kcontrol *vol_kctl; /* volume controls */ + struct snd_kcontrol *usr_kctl; /* user controls */ struct device dev; }; @@ -1399,6 +1421,54 @@ return 1ULL << (__force int) pcm_format; } +/* + * PCM Volume control API + */ +/* array element of volume */ +struct snd_pcm_volume_elem { + int volume; +}; + +/* pp information; retrieved via snd_kcontrol_chip() */ +struct snd_pcm_volume { + struct snd_pcm *pcm; /* assigned PCM instance */ + int stream; /* PLAYBACK or CAPTURE */ + struct snd_kcontrol *kctl; + const struct snd_pcm_volume_elem *volume; + int max_length; + void *private_data; /* optional: private data pointer */ +}; + +int snd_pcm_add_volume_ctls(struct snd_pcm *pcm, int stream, + const struct snd_pcm_volume_elem *volume, + int max_length, + unsigned long private_value, + struct snd_pcm_volume **info_ret); + +/* + * PCM User control API + */ +/* array element of usr elem */ +struct snd_pcm_usr_elem { + int val[128]; +}; + +/* pp information; retrieved via snd_kcontrol_chip() */ +struct snd_pcm_usr { + struct snd_pcm *pcm; /* assigned PCM instance */ + int stream; /* PLAYBACK or CAPTURE */ + struct snd_kcontrol *kctl; + const struct snd_pcm_usr_elem *usr; + int max_length; + void *private_data; /* optional: private data pointer */ +}; + +int snd_pcm_add_usr_ctls(struct snd_pcm *pcm, int stream, + const struct snd_pcm_usr_elem *usr, + int max_length, int max_control_str_len, + unsigned long private_value, + struct snd_pcm_usr **info_ret); + /* printk helpers */ #define pcm_err(pcm, fmt, args...) \ dev_err((pcm)->card->dev, fmt, ##args) diff -ruw linux-4.4.115/include/sound/pcm_params.h linux-4.4.115-fbx/include/sound/pcm_params.h --- linux-4.4.115/include/sound/pcm_params.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/sound/pcm_params.h 2019-10-29 09:26:25.533221674 +0100 @@ -110,10 +110,14 @@ static inline void snd_mask_leave(struct snd_mask *mask, unsigned int val) { - unsigned int v; - v = mask->bits[MASK_OFS(val)] & MASK_BIT(val); + unsigned int v, bits_index; + + bits_index = MASK_OFS(val); + if (bits_index < ((SNDRV_MASK_MAX+31)/32)) { + v = mask->bits[bits_index] & MASK_BIT(val); snd_mask_none(mask); - mask->bits[MASK_OFS(val)] = v; + mask->bits[bits_index] = v; + } } static inline void snd_mask_intersect(struct snd_mask *mask, diff -ruw linux-4.4.115/include/sound/rawmidi.h linux-4.4.115-fbx/include/sound/rawmidi.h --- linux-4.4.115/include/sound/rawmidi.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/sound/rawmidi.h 2019-01-22 16:16:28.511291757 +0100 @@ -78,6 +78,7 @@ size_t xruns; /* over/underruns counter */ /* misc */ spinlock_t lock; + struct mutex realloc_mutex; wait_queue_head_t sleep; /* event handler (new bytes, input only) */ void (*event)(struct snd_rawmidi_substream *substream); diff -ruw linux-4.4.115/include/sound/soc-dai.h linux-4.4.115-fbx/include/sound/soc-dai.h --- linux-4.4.115/include/sound/soc-dai.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/sound/soc-dai.h 2019-01-22 16:16:28.511291757 +0100 @@ -138,6 +138,10 @@ int snd_soc_dai_digital_mute(struct snd_soc_dai *dai, int mute, int direction); +int snd_soc_dai_get_channel_map(struct snd_soc_dai *dai, + unsigned int *tx_num, unsigned int *tx_slot, + unsigned int *rx_num, unsigned int *rx_slot); + int snd_soc_dai_is_dummy(struct snd_soc_dai *dai); struct snd_soc_dai_ops { @@ -166,6 +170,9 @@ unsigned int tx_num, unsigned int *tx_slot, unsigned int rx_num, unsigned int *rx_slot); int (*set_tristate)(struct snd_soc_dai *dai, int tristate); + int (*get_channel_map)(struct snd_soc_dai *dai, + unsigned int *tx_num, unsigned int *tx_slot, + unsigned int *rx_num, unsigned int *rx_slot); /* * DAI digital mute - optional. @@ -262,8 +269,8 @@ struct snd_soc_dai_driver *driver; /* DAI runtime info */ - unsigned int capture_active:1; /* stream is in use */ - unsigned int playback_active:1; /* stream is in use */ + unsigned int capture_active; /* stream is in use */ + unsigned int playback_active; /* stream is in use */ unsigned int symmetric_rates:1; unsigned int symmetric_channels:1; unsigned int symmetric_samplebits:1; diff -ruw linux-4.4.115/include/sound/soc-dapm.h linux-4.4.115-fbx/include/sound/soc-dapm.h --- linux-4.4.115/include/sound/soc-dapm.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/sound/soc-dapm.h 2019-01-22 16:16:28.511291757 +0100 @@ -314,6 +314,11 @@ .get = snd_soc_dapm_get_pin_switch, \ .put = snd_soc_dapm_put_pin_switch, \ .private_value = (unsigned long)xname } +#define SND_SOC_DAPM_MICBIAS_E(wname, wreg, wshift, winvert, wevent, wflags) \ +{ .id = snd_soc_dapm_micbias, .name = wname, \ + SND_SOC_DAPM_INIT_REG_VAL(wreg, wshift, winvert), \ + .kcontrol_news = NULL, .num_kcontrols = 0, \ + .event = wevent, .event_flags = wflags} /* dapm stream operations */ #define SND_SOC_DAPM_STREAM_NOP 0x0 @@ -451,6 +456,8 @@ struct snd_soc_dapm_context *snd_soc_dapm_kcontrol_dapm( struct snd_kcontrol *kcontrol); +struct snd_soc_dapm_widget_list *dapm_kcontrol_get_wlist( + const struct snd_kcontrol *kcontrol); struct snd_soc_dapm_widget *snd_soc_dapm_kcontrol_widget( struct snd_kcontrol *kcontrol); diff -ruw linux-4.4.115/include/sound/soc-dpcm.h linux-4.4.115-fbx/include/sound/soc-dpcm.h --- linux-4.4.115/include/sound/soc-dpcm.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/sound/soc-dpcm.h 2019-01-22 16:16:28.511291757 +0100 @@ -17,6 +17,7 @@ struct snd_soc_pcm_runtime; +#define DPCM_MAX_BE_USERS 8 /* * Types of runtime_update to perform. e.g. originated from FE PCM ops * or audio route changes triggered by muxes/mixers. @@ -86,6 +87,7 @@ #ifdef CONFIG_DEBUG_FS struct dentry *debugfs_state; #endif + int stream; }; /* @@ -148,8 +150,13 @@ void dpcm_clear_pending_state(struct snd_soc_pcm_runtime *fe, int stream); int dpcm_be_dai_hw_free(struct snd_soc_pcm_runtime *fe, int stream); int dpcm_be_dai_hw_params(struct snd_soc_pcm_runtime *fe, int tream); +int dpcm_fe_dai_hw_params_be(struct snd_soc_pcm_runtime *fe, + struct snd_soc_pcm_runtime *be, struct snd_pcm_hw_params *hw_params, + int stream); int dpcm_be_dai_trigger(struct snd_soc_pcm_runtime *fe, int stream, int cmd); int dpcm_be_dai_prepare(struct snd_soc_pcm_runtime *fe, int stream); +int dpcm_fe_dai_prepare_be(struct snd_soc_pcm_runtime *fe, + struct snd_soc_pcm_runtime *be, int stream); int dpcm_dapm_stream_event(struct snd_soc_pcm_runtime *fe, int dir, int event); diff -ruw linux-4.4.115/include/sound/soc.h linux-4.4.115-fbx/include/sound/soc.h --- linux-4.4.115/include/sound/soc.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/sound/soc.h 2019-01-22 16:16:28.511291757 +0100 @@ -22,6 +22,7 @@ #include #include #include +#include #include #include #include @@ -224,6 +225,14 @@ .get = xhandler_get, .put = xhandler_put, \ .private_value = SOC_DOUBLE_R_VALUE(reg_left, reg_right, xshift, \ xmax, xinvert) } +#define SOC_SINGLE_MULTI_EXT(xname, xreg, xshift, xmax, xinvert, xcount,\ + xhandler_get, xhandler_put) \ +{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ + .info = snd_soc_info_multi_ext, \ + .get = xhandler_get, .put = xhandler_put, \ + .private_value = (unsigned long)&(struct soc_multi_mixer_control) \ + {.reg = xreg, .shift = xshift, .rshift = xshift, .max = xmax, \ + .count = xcount, .platform_max = xmax, .invert = xinvert} } #define SOC_SINGLE_EXT_TLV(xname, xreg, xshift, xmax, xinvert,\ xhandler_get, xhandler_put, tlv_array) \ { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ @@ -354,6 +363,10 @@ #define SND_SOC_COMP_ORDER_LATE 1 #define SND_SOC_COMP_ORDER_LAST 2 +/* DAI Link Host Mode Support */ +#define SND_SOC_DAI_LINK_NO_HOST 0x1 +#define SND_SOC_DAI_LINK_OPT_HOST 0x2 + /* * Bias levels * @@ -545,12 +558,13 @@ int snd_soc_test_bits(struct snd_soc_codec *codec, unsigned int reg, unsigned int mask, unsigned int value); +void snd_soc_card_change_online_state(struct snd_soc_card *soc_card, + int online); #ifdef CONFIG_SND_SOC_AC97_BUS struct snd_ac97 *snd_soc_alloc_ac97_codec(struct snd_soc_codec *codec); struct snd_ac97 *snd_soc_new_ac97_codec(struct snd_soc_codec *codec, unsigned int id, unsigned int id_mask); void snd_soc_free_ac97_codec(struct snd_ac97 *ac97); - int snd_soc_set_ac97_ops(struct snd_ac97_bus_ops *ops); int snd_soc_set_ac97_ops_of_reset(struct snd_ac97_bus_ops *ops, struct platform_device *pdev); @@ -636,6 +650,8 @@ struct snd_ctl_elem_value *ucontrol); int snd_soc_put_strobe(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol); +int snd_soc_info_multi_ext(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_info *uinfo); /** * struct snd_soc_jack_pin - Describes a pin to update based on jack detection @@ -727,6 +743,7 @@ unsigned int channels_min; /* min channels */ unsigned int channels_max; /* max channels */ unsigned int sig_bits; /* number of bits of content */ + const char *aif_name; /* DAPM AIF widget name */ }; /* SoC audio ops */ @@ -925,6 +942,16 @@ snd_pcm_sframes_t (*delay)(struct snd_pcm_substream *, struct snd_soc_dai *); + /* + * For platform-caused delay reporting, where the thread blocks waiting + * for the delay amount to be determined. Defining this will cause the + * ASoC core to skip calling the delay callbacks for all components in + * the runtime. + * Optional. + */ + snd_pcm_sframes_t (*delay_blk)(struct snd_pcm_substream *, + struct snd_soc_dai *); + /* platform stream pcm ops */ const struct snd_pcm_ops *ops; @@ -949,6 +976,14 @@ struct snd_soc_component component; }; +enum snd_soc_async_ops { + ASYNC_DPCM_SND_SOC_OPEN = 1 << 0, + ASYNC_DPCM_SND_SOC_CLOSE = 1 << 1, + ASYNC_DPCM_SND_SOC_PREPARE = 1 << 2, + ASYNC_DPCM_SND_SOC_HW_PARAMS = 1 << 3, + ASYNC_DPCM_SND_SOC_FREE = 1 << 4, +}; + struct snd_soc_dai_link { /* config - must be set by machine driver */ const char *name; /* Codec name */ @@ -1028,6 +1063,9 @@ /* This DAI link can route to other DAI links at runtime (Frontend)*/ unsigned int dynamic:1; + /* This DAI can support no host IO (no pcm data is copied to from host) */ + unsigned int no_host_mode:2; + /* DPCM capture and Playback support */ unsigned int dpcm_capture:1; unsigned int dpcm_playback:1; @@ -1037,6 +1075,9 @@ /* pmdown_time is ignored at stop */ unsigned int ignore_pmdown_time:1; + + /* this value determines what all ops can be started asynchronously */ + enum snd_soc_async_ops async_ops; }; struct snd_soc_codec_conf { @@ -1079,6 +1120,7 @@ struct mutex mutex; struct mutex dapm_mutex; + struct mutex dapm_power_mutex; bool instantiated; @@ -1184,6 +1226,8 @@ long pmdown_time; unsigned char pop_wait:1; + /* err in case of ops failed */ + int err_ops; /* runtime devices */ struct snd_pcm *pcm; struct snd_compr *compr; @@ -1225,8 +1269,10 @@ struct snd_soc_dobj dobj; /* used for TLV byte control */ - int (*get)(unsigned int __user *bytes, unsigned int size); - int (*put)(const unsigned int __user *bytes, unsigned int size); + int (*get)(struct snd_kcontrol *kcontrol, unsigned int __user *bytes, + unsigned int size); + int (*put)(struct snd_kcontrol *kcontrol, const unsigned int __user *bytes, + unsigned int size); }; /* multi register control */ @@ -1235,6 +1281,11 @@ unsigned int regbase, regcount, nbits, invert; }; +struct soc_multi_mixer_control { + int min, max, platform_max, count; + unsigned int reg, rreg, shift, rshift, invert; +}; + /* enumerated kcontrol */ struct soc_enum { int reg; @@ -1420,6 +1471,8 @@ void snd_soc_component_async_complete(struct snd_soc_component *component); int snd_soc_component_test_bits(struct snd_soc_component *component, unsigned int reg, unsigned int mask, unsigned int value); +struct snd_soc_component *soc_find_component( + const struct device_node *of_node, const char *name); #ifdef CONFIG_REGMAP diff -ruw linux-4.4.115/include/sound/soc-topology.h linux-4.4.115-fbx/include/sound/soc-topology.h --- linux-4.4.115/include/sound/soc-topology.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/sound/soc-topology.h 2019-01-22 16:16:28.511291757 +0100 @@ -92,8 +92,10 @@ /* Bytes ext operations, for TLV byte controls */ struct snd_soc_tplg_bytes_ext_ops { u32 id; - int (*get)(unsigned int __user *bytes, unsigned int size); - int (*put)(const unsigned int __user *bytes, unsigned int size); + int (*get)(struct snd_kcontrol *kcontrol, unsigned int __user *bytes, + unsigned int size); + int (*put)(struct snd_kcontrol *kcontrol, + const unsigned int __user *bytes, unsigned int size); }; /* diff -ruw linux-4.4.115/include/trace/events/cma.h linux-4.4.115-fbx/include/trace/events/cma.h --- linux-4.4.115/include/trace/events/cma.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/trace/events/cma.h 2019-01-22 16:16:28.519291829 +0100 @@ -7,7 +7,7 @@ #include #include -TRACE_EVENT(cma_alloc, +DECLARE_EVENT_CLASS(cma_alloc_class, TP_PROTO(unsigned long pfn, const struct page *page, unsigned int count, unsigned int align), @@ -60,6 +60,44 @@ __entry->count) ); +TRACE_EVENT(cma_alloc_start, + + TP_PROTO(unsigned int count, unsigned int align), + + TP_ARGS(count, align), + + TP_STRUCT__entry( + __field(unsigned int, count) + __field(unsigned int, align) + ), + + TP_fast_assign( + __entry->count = count; + __entry->align = align; + ), + + TP_printk("count=%u align=%u", + __entry->count, + __entry->align) +); + +DEFINE_EVENT(cma_alloc_class, cma_alloc, + + TP_PROTO(unsigned long pfn, const struct page *page, + unsigned int count, unsigned int align), + + TP_ARGS(pfn, page, count, align) +); + +DEFINE_EVENT(cma_alloc_class, cma_alloc_busy_retry, + + TP_PROTO(unsigned long pfn, const struct page *page, + unsigned int count, unsigned int align), + + TP_ARGS(pfn, page, count, align) +); + + #endif /* _TRACE_CMA_H */ /* This part must be outside protection */ diff -ruw linux-4.4.115/include/trace/events/compaction.h linux-4.4.115-fbx/include/trace/events/compaction.h --- linux-4.4.115/include/trace/events/compaction.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/trace/events/compaction.h 2019-01-22 16:16:28.519291829 +0100 @@ -350,6 +350,61 @@ ); #endif +TRACE_EVENT(mm_compaction_kcompactd_sleep, + + TP_PROTO(int nid), + + TP_ARGS(nid), + + TP_STRUCT__entry( + __field(int, nid) + ), + + TP_fast_assign( + __entry->nid = nid; + ), + + TP_printk("nid=%d", __entry->nid) +); + +DECLARE_EVENT_CLASS(kcompactd_wake_template, + + TP_PROTO(int nid, int order, enum zone_type classzone_idx), + + TP_ARGS(nid, order, classzone_idx), + + TP_STRUCT__entry( + __field(int, nid) + __field(int, order) + __field(enum zone_type, classzone_idx) + ), + + TP_fast_assign( + __entry->nid = nid; + __entry->order = order; + __entry->classzone_idx = classzone_idx; + ), + + TP_printk("nid=%d order=%d classzone_idx=%-8s", + __entry->nid, + __entry->order, + __print_symbolic(__entry->classzone_idx, ZONE_TYPE)) +); + +DEFINE_EVENT(kcompactd_wake_template, mm_compaction_wakeup_kcompactd, + + TP_PROTO(int nid, int order, enum zone_type classzone_idx), + + TP_ARGS(nid, order, classzone_idx) +); + +DEFINE_EVENT(kcompactd_wake_template, mm_compaction_kcompactd_wake, + + TP_PROTO(int nid, int order, enum zone_type classzone_idx), + + TP_ARGS(nid, order, classzone_idx) +); + #endif /* _TRACE_COMPACTION_H */ /* This part must be outside protection */ diff -ruw linux-4.4.115/include/trace/events/iommu.h linux-4.4.115-fbx/include/trace/events/iommu.h --- linux-4.4.115/include/trace/events/iommu.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/trace/events/iommu.h 2019-01-22 16:16:28.519291829 +0100 @@ -83,6 +83,29 @@ TP_ARGS(dev) ); +DECLARE_EVENT_CLASS(iommu_map_unmap, + + TP_PROTO(unsigned long iova, phys_addr_t paddr, size_t size), + + TP_ARGS(iova, paddr, size), + + TP_STRUCT__entry( + __field(u64, iova) + __field(u64, paddr) + __field(size_t, size) + ), + + TP_fast_assign( + __entry->iova = iova; + __entry->paddr = paddr; + __entry->size = size; + ), + + TP_printk("IOMMU: iova=0x%016llx paddr=0x%016llx size=0x%zx", + __entry->iova, __entry->paddr, __entry->size + ) +); + TRACE_EVENT(map, TP_PROTO(unsigned long iova, phys_addr_t paddr, size_t size), @@ -129,6 +152,77 @@ ) ); +DEFINE_EVENT(iommu_map_unmap, map_start, + + TP_PROTO(unsigned long iova, phys_addr_t paddr, size_t size), + + TP_ARGS(iova, paddr, size) +); + +DEFINE_EVENT(iommu_map_unmap, map_end, + + TP_PROTO(unsigned long iova, phys_addr_t paddr, size_t size), + + TP_ARGS(iova, paddr, size) +); + +DEFINE_EVENT_PRINT(iommu_map_unmap, unmap_start, + + TP_PROTO(unsigned long iova, phys_addr_t paddr, size_t size), + + TP_ARGS(iova, paddr, size), + + TP_printk("IOMMU: iova=0x%016llx size=0x%x", + __entry->iova, __entry->size + ) +); + +DEFINE_EVENT_PRINT(iommu_map_unmap, unmap_end, + + TP_PROTO(unsigned long iova, phys_addr_t paddr, size_t size), + + TP_ARGS(iova, paddr, size), + + TP_printk("IOMMU: iova=0x%016llx size=0x%x", + __entry->iova, __entry->size + ) +); + +DECLARE_EVENT_CLASS(iommu_map_sg, + + TP_PROTO(unsigned long iova, unsigned int nents), + + TP_ARGS(iova, nents), + + TP_STRUCT__entry( + __field(u64, iova) + __field(int, nents) + ), + + TP_fast_assign( + __entry->iova = iova; + __entry->nents = nents; + ), + + TP_printk("IOMMU: iova=0x%016llx nents=%u", + __entry->iova, __entry->nents + ) +); + +DEFINE_EVENT(iommu_map_sg, map_sg_start, + + TP_PROTO(unsigned long iova, unsigned int nents), + + TP_ARGS(iova, nents) +); + +DEFINE_EVENT(iommu_map_sg, map_sg_end, + + TP_PROTO(unsigned long iova, unsigned int nents), + + TP_ARGS(iova, nents) +); + DECLARE_EVENT_CLASS(iommu_error, TP_PROTO(struct device *dev, unsigned long iova, int flags), diff -ruw linux-4.4.115/include/trace/events/kmem.h linux-4.4.115-fbx/include/trace/events/kmem.h --- linux-4.4.115/include/trace/events/kmem.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/trace/events/kmem.h 2019-01-22 16:16:28.523291866 +0100 @@ -351,6 +351,550 @@ __entry->change_ownership) ); + +DECLARE_EVENT_CLASS(ion_alloc, + + TP_PROTO(const char *client_name, + const char *heap_name, + size_t len, + unsigned int mask, + unsigned int flags), + + TP_ARGS(client_name, heap_name, len, mask, flags), + + TP_STRUCT__entry( + __array(char, client_name, 64) + __field(const char *, heap_name) + __field(size_t, len) + __field(unsigned int, mask) + __field(unsigned int, flags) + ), + + TP_fast_assign( + strlcpy(__entry->client_name, client_name, 64); + __entry->heap_name = heap_name; + __entry->len = len; + __entry->mask = mask; + __entry->flags = flags; + ), + + TP_printk("client_name=%s heap_name=%s len=%zu mask=0x%x flags=0x%x", + __entry->client_name, + __entry->heap_name, + __entry->len, + __entry->mask, + __entry->flags) +); + +DEFINE_EVENT(ion_alloc, ion_alloc_buffer_start, + + TP_PROTO(const char *client_name, + const char *heap_name, + size_t len, + unsigned int mask, + unsigned int flags), + + TP_ARGS(client_name, heap_name, len, mask, flags) +); + +DEFINE_EVENT(ion_alloc, ion_alloc_buffer_end, + + TP_PROTO(const char *client_name, + const char *heap_name, + size_t len, + unsigned int mask, + unsigned int flags), + + TP_ARGS(client_name, heap_name, len, mask, flags) +); + +DECLARE_EVENT_CLASS(ion_alloc_error, + + TP_PROTO(const char *client_name, + const char *heap_name, + size_t len, + unsigned int mask, + unsigned int flags, + long error), + + TP_ARGS(client_name, heap_name, len, mask, flags, error), + + TP_STRUCT__entry( + __field(const char *, client_name) + __field(const char *, heap_name) + __field(size_t, len) + __field(unsigned int, mask) + __field(unsigned int, flags) + __field(long, error) + ), + + TP_fast_assign( + __entry->client_name = client_name; + __entry->heap_name = heap_name; + __entry->len = len; + __entry->mask = mask; + __entry->flags = flags; + __entry->error = error; + ), + + TP_printk( + "client_name=%s heap_name=%s len=%zu mask=0x%x flags=0x%x error=%ld", + __entry->client_name, + __entry->heap_name, + __entry->len, + __entry->mask, + __entry->flags, + __entry->error) +); + + +DEFINE_EVENT(ion_alloc_error, ion_alloc_buffer_fallback, + + TP_PROTO(const char *client_name, + const char *heap_name, + size_t len, + unsigned int mask, + unsigned int flags, + long error), + + TP_ARGS(client_name, heap_name, len, mask, flags, error) +); + +DEFINE_EVENT(ion_alloc_error, ion_alloc_buffer_fail, + + TP_PROTO(const char *client_name, + const char *heap_name, + size_t len, + unsigned int mask, + unsigned int flags, + long error), + + TP_ARGS(client_name, heap_name, len, mask, flags, error) +); + + +DECLARE_EVENT_CLASS(alloc_retry, + + TP_PROTO(int tries), + + TP_ARGS(tries), + + TP_STRUCT__entry( + __field(int, tries) + ), + + TP_fast_assign( + __entry->tries = tries; + ), + + TP_printk("tries=%d", + __entry->tries) +); + +DEFINE_EVENT(alloc_retry, ion_cp_alloc_retry, + + TP_PROTO(int tries), + + TP_ARGS(tries) +); + +DEFINE_EVENT(alloc_retry, migrate_retry, + + TP_PROTO(int tries), + + TP_ARGS(tries) +); + +DEFINE_EVENT(alloc_retry, dma_alloc_contiguous_retry, + + TP_PROTO(int tries), + + TP_ARGS(tries) +); + +DECLARE_EVENT_CLASS(migrate_pages, + + TP_PROTO(int mode), + + TP_ARGS(mode), + + TP_STRUCT__entry( + __field(int, mode) + ), + + TP_fast_assign( + __entry->mode = mode; + ), + + TP_printk("mode=%d", + __entry->mode) +); + +DEFINE_EVENT(migrate_pages, migrate_pages_start, + + TP_PROTO(int mode), + + TP_ARGS(mode) +); + +DEFINE_EVENT(migrate_pages, migrate_pages_end, + + TP_PROTO(int mode), + + TP_ARGS(mode) +); + +DECLARE_EVENT_CLASS(ion_alloc_pages, + + TP_PROTO(gfp_t gfp_flags, + unsigned int order), + + TP_ARGS(gfp_flags, order), + + TP_STRUCT__entry( + __field(gfp_t, gfp_flags) + __field(unsigned int, order) + ), + + TP_fast_assign( + __entry->gfp_flags = gfp_flags; + __entry->order = order; + ), + + TP_printk("gfp_flags=%s order=%d", + show_gfp_flags(__entry->gfp_flags), + __entry->order) + ); + +DEFINE_EVENT(ion_alloc_pages, alloc_pages_iommu_start, + TP_PROTO(gfp_t gfp_flags, + unsigned int order), + + TP_ARGS(gfp_flags, order) + ); + +DEFINE_EVENT(ion_alloc_pages, alloc_pages_iommu_end, + TP_PROTO(gfp_t gfp_flags, + unsigned int order), + + TP_ARGS(gfp_flags, order) + ); + +DEFINE_EVENT(ion_alloc_pages, alloc_pages_iommu_fail, + TP_PROTO(gfp_t gfp_flags, + unsigned int order), + + TP_ARGS(gfp_flags, order) + ); + +DEFINE_EVENT(ion_alloc_pages, alloc_pages_sys_start, + TP_PROTO(gfp_t gfp_flags, + unsigned int order), + + TP_ARGS(gfp_flags, order) + ); + +DEFINE_EVENT(ion_alloc_pages, alloc_pages_sys_end, + TP_PROTO(gfp_t gfp_flags, + unsigned int order), + + TP_ARGS(gfp_flags, order) + ); + +DEFINE_EVENT(ion_alloc_pages, alloc_pages_sys_fail, + TP_PROTO(gfp_t gfp_flags, + unsigned int order), + + TP_ARGS(gfp_flags, order) + + ); + +DECLARE_EVENT_CLASS(smmu_map, + + TP_PROTO(unsigned long va, + phys_addr_t pa, + unsigned long chunk_size, + size_t len), + + TP_ARGS(va, pa, chunk_size, len), + + TP_STRUCT__entry( + __field(unsigned long, va) + __field(phys_addr_t, pa) + __field(unsigned long, chunk_size) + __field(size_t, len) + ), + + TP_fast_assign( + __entry->va = va; + __entry->pa = pa; + __entry->chunk_size = chunk_size; + __entry->len = len; + ), + + TP_printk("v_addr=%p p_addr=%pa chunk_size=0x%lu len=%zu", + (void *)__entry->va, + &__entry->pa, + __entry->chunk_size, + __entry->len) + ); + +DEFINE_EVENT(smmu_map, iommu_map_range, + TP_PROTO(unsigned long va, + phys_addr_t pa, + unsigned long chunk_size, + size_t len), + + TP_ARGS(va, pa, chunk_size, len) + ); + +DECLARE_EVENT_CLASS(ion_secure_cma_add_to_pool, + + TP_PROTO(unsigned long len, + int pool_total, + bool is_prefetch), + + TP_ARGS(len, pool_total, is_prefetch), + + TP_STRUCT__entry( + __field(unsigned long, len) + __field(int, pool_total) + __field(bool, is_prefetch) + ), + + TP_fast_assign( + __entry->len = len; + __entry->pool_total = pool_total; + __entry->is_prefetch = is_prefetch; + ), + + TP_printk("len %lx, pool total %x is_prefetch %d", + __entry->len, + __entry->pool_total, + __entry->is_prefetch) + ); + +DEFINE_EVENT(ion_secure_cma_add_to_pool, ion_secure_cma_add_to_pool_start, + TP_PROTO(unsigned long len, + int pool_total, + bool is_prefetch), + + TP_ARGS(len, pool_total, is_prefetch) + ); + +DEFINE_EVENT(ion_secure_cma_add_to_pool, ion_secure_cma_add_to_pool_end, + TP_PROTO(unsigned long len, + int pool_total, + bool is_prefetch), + + TP_ARGS(len, pool_total, is_prefetch) + ); + +DECLARE_EVENT_CLASS(ion_secure_cma_shrink_pool, + + TP_PROTO(unsigned long drained_size, + unsigned long skipped_size), + + TP_ARGS(drained_size, skipped_size), + + TP_STRUCT__entry( + __field(unsigned long, drained_size) + __field(unsigned long, skipped_size) + ), + + TP_fast_assign( + __entry->drained_size = drained_size; + __entry->skipped_size = skipped_size; + ), + + TP_printk("drained size %lx, skipped size %lx", + __entry->drained_size, + __entry->skipped_size) + ); + +DEFINE_EVENT(ion_secure_cma_shrink_pool, ion_secure_cma_shrink_pool_start, + TP_PROTO(unsigned long drained_size, + unsigned long skipped_size), + + TP_ARGS(drained_size, skipped_size) + ); + +DEFINE_EVENT(ion_secure_cma_shrink_pool, ion_secure_cma_shrink_pool_end, + TP_PROTO(unsigned long drained_size, + unsigned long skipped_size), + + TP_ARGS(drained_size, skipped_size) + ); + +TRACE_EVENT(ion_prefetching, + + TP_PROTO(unsigned long len), + + TP_ARGS(len), + + TP_STRUCT__entry( + __field(unsigned long, len) + ), + + TP_fast_assign( + __entry->len = len; + ), + + TP_printk("prefetch size %lx", + __entry->len) + ); + +DECLARE_EVENT_CLASS(ion_secure_cma_allocate, + + TP_PROTO(const char *heap_name, + unsigned long len, + unsigned long align, + unsigned long flags), + + TP_ARGS(heap_name, len, align, flags), + + TP_STRUCT__entry( + __field(const char *, heap_name) + __field(unsigned long, len) + __field(unsigned long, align) + __field(unsigned long, flags) + ), + + TP_fast_assign( + __entry->heap_name = heap_name; + __entry->len = len; + __entry->align = align; + __entry->flags = flags; + ), + + TP_printk("heap_name=%s len=%lx align=%lx flags=%lx", + __entry->heap_name, + __entry->len, + __entry->align, + __entry->flags) + ); + +DEFINE_EVENT(ion_secure_cma_allocate, ion_secure_cma_allocate_start, + TP_PROTO(const char *heap_name, + unsigned long len, + unsigned long align, + unsigned long flags), + + TP_ARGS(heap_name, len, align, flags) + ); + +DEFINE_EVENT(ion_secure_cma_allocate, ion_secure_cma_allocate_end, + TP_PROTO(const char *heap_name, + unsigned long len, + unsigned long align, + unsigned long flags), + + TP_ARGS(heap_name, len, align, flags) + ); + +DECLARE_EVENT_CLASS(ion_cp_secure_buffer, + + TP_PROTO(const char *heap_name, + unsigned long len, + unsigned long align, + unsigned long flags), + + TP_ARGS(heap_name, len, align, flags), + + TP_STRUCT__entry( + __field(const char *, heap_name) + __field(unsigned long, len) + __field(unsigned long, align) + __field(unsigned long, flags) + ), + + TP_fast_assign( + __entry->heap_name = heap_name; + __entry->len = len; + __entry->align = align; + __entry->flags = flags; + ), + + TP_printk("heap_name=%s len=%lx align=%lx flags=%lx", + __entry->heap_name, + __entry->len, + __entry->align, + __entry->flags) + ); + +DEFINE_EVENT(ion_cp_secure_buffer, ion_cp_secure_buffer_start, + TP_PROTO(const char *heap_name, + unsigned long len, + unsigned long align, + unsigned long flags), + + TP_ARGS(heap_name, len, align, flags) + ); + +DEFINE_EVENT(ion_cp_secure_buffer, ion_cp_secure_buffer_end, + TP_PROTO(const char *heap_name, + unsigned long len, + unsigned long align, + unsigned long flags), + + TP_ARGS(heap_name, len, align, flags) + ); + +DECLARE_EVENT_CLASS(iommu_sec_ptbl_map_range, + + TP_PROTO(int sec_id, + int num, + unsigned long va, + unsigned int pa, + size_t len), + + TP_ARGS(sec_id, num, va, pa, len), + + TP_STRUCT__entry( + __field(int, sec_id) + __field(int, num) + __field(unsigned long, va) + __field(unsigned int, pa) + __field(size_t, len) + ), + + TP_fast_assign( + __entry->sec_id = sec_id; + __entry->num = num; + __entry->va = va; + __entry->pa = pa; + __entry->len = len; + ), + + TP_printk("sec_id=%d num=%d va=%lx pa=%u len=%zu", + __entry->sec_id, + __entry->num, + __entry->va, + __entry->pa, + __entry->len) + ); + +DEFINE_EVENT(iommu_sec_ptbl_map_range, iommu_sec_ptbl_map_range_start, + + TP_PROTO(int sec_id, + int num, + unsigned long va, + unsigned int pa, + size_t len), + + TP_ARGS(sec_id, num, va, pa, len) + ); + +DEFINE_EVENT(iommu_sec_ptbl_map_range, iommu_sec_ptbl_map_range_end, + + TP_PROTO(int sec_id, + int num, + unsigned long va, + unsigned int pa, + size_t len), + + TP_ARGS(sec_id, num, va, pa, len) + ); #endif /* _TRACE_KMEM_H */ /* This part must be outside protection */ diff -ruw linux-4.4.115/include/trace/events/migrate.h linux-4.4.115-fbx/include/trace/events/migrate.h --- linux-4.4.115/include/trace/events/migrate.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/trace/events/migrate.h 2019-01-22 16:16:28.523291866 +0100 @@ -96,6 +96,27 @@ __entry->dst_nid, __entry->nr_pages) ); + +TRACE_EVENT(mm_migrate_pages_start, + + TP_PROTO(enum migrate_mode mode, int reason), + + TP_ARGS(mode, reason), + + TP_STRUCT__entry( + __field(enum migrate_mode, mode) + __field(int, reason) + ), + + TP_fast_assign( + __entry->mode = mode; + __entry->reason = reason; + ), + + TP_printk("mode=%s reason=%s", + __print_symbolic(__entry->mode, MIGRATE_MODE), + __print_symbolic(__entry->reason, MIGRATE_REASON)) +); #endif /* _TRACE_MIGRATE_H */ /* This part must be outside protection */ diff -ruw linux-4.4.115/include/trace/events/net.h linux-4.4.115-fbx/include/trace/events/net.h --- linux-4.4.115/include/trace/events/net.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/trace/events/net.h 2019-01-22 16:16:28.523291866 +0100 @@ -57,7 +57,7 @@ __entry->gso_type = skb_shinfo(skb)->gso_type; ), - TP_printk("dev=%s queue_mapping=%u skbaddr=%p vlan_tagged=%d vlan_proto=0x%04x vlan_tci=0x%04x protocol=0x%04x ip_summed=%d len=%u data_len=%u network_offset=%d transport_offset_valid=%d transport_offset=%d tx_flags=%d gso_size=%d gso_segs=%d gso_type=%#x", + TP_printk("dev=%s queue_mapping=%u skbaddr=%pK vlan_tagged=%d vlan_proto=0x%04x vlan_tci=0x%04x protocol=0x%04x ip_summed=%d len=%u data_len=%u network_offset=%d transport_offset_valid=%d transport_offset=%d tx_flags=%d gso_size=%d gso_segs=%d gso_type=%#x", __get_str(name), __entry->queue_mapping, __entry->skbaddr, __entry->vlan_tagged, __entry->vlan_proto, __entry->vlan_tci, __entry->protocol, __entry->ip_summed, __entry->len, @@ -90,7 +90,7 @@ __assign_str(name, dev->name); ), - TP_printk("dev=%s skbaddr=%p len=%u rc=%d", + TP_printk("dev=%s skbaddr=%pK len=%u rc=%d", __get_str(name), __entry->skbaddr, __entry->len, __entry->rc) ); @@ -112,7 +112,7 @@ __assign_str(name, skb->dev->name); ), - TP_printk("dev=%s skbaddr=%p len=%u", + TP_printk("dev=%s skbaddr=%pK len=%u", __get_str(name), __entry->skbaddr, __entry->len) ) @@ -191,7 +191,7 @@ __entry->gso_type = skb_shinfo(skb)->gso_type; ), - TP_printk("dev=%s napi_id=%#x queue_mapping=%u skbaddr=%p vlan_tagged=%d vlan_proto=0x%04x vlan_tci=0x%04x protocol=0x%04x ip_summed=%d hash=0x%08x l4_hash=%d len=%u data_len=%u truesize=%u mac_header_valid=%d mac_header=%d nr_frags=%d gso_size=%d gso_type=%#x", + TP_printk("dev=%s napi_id=%#x queue_mapping=%u skbaddr=%pK vlan_tagged=%d vlan_proto=0x%04x vlan_tci=0x%04x protocol=0x%04x ip_summed=%d hash=0x%08x l4_hash=%d len=%u data_len=%u truesize=%u mac_header_valid=%d mac_header=%d nr_frags=%d gso_size=%d gso_type=%#x", __get_str(name), __entry->napi_id, __entry->queue_mapping, __entry->skbaddr, __entry->vlan_tagged, __entry->vlan_proto, __entry->vlan_tci, __entry->protocol, __entry->ip_summed, diff -ruw linux-4.4.115/include/trace/events/power.h linux-4.4.115-fbx/include/trace/events/power.h --- linux-4.4.115/include/trace/events/power.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/trace/events/power.h 2019-01-22 16:16:28.523291866 +0100 @@ -120,6 +120,80 @@ TP_ARGS(frequency, cpu_id) ); +TRACE_EVENT(cpu_frequency_limits, + + TP_PROTO(unsigned int max_freq, unsigned int min_freq, + unsigned int cpu_id), + + TP_ARGS(max_freq, min_freq, cpu_id), + + TP_STRUCT__entry( + __field( u32, min_freq ) + __field( u32, max_freq ) + __field( u32, cpu_id ) + ), + + TP_fast_assign( + __entry->min_freq = min_freq; + __entry->max_freq = max_freq; + __entry->cpu_id = cpu_id; + ), + + TP_printk("min=%lu max=%lu cpu_id=%lu", + (unsigned long)__entry->min_freq, + (unsigned long)__entry->max_freq, + (unsigned long)__entry->cpu_id) +); + +TRACE_EVENT(cpu_frequency_switch_start, + + TP_PROTO(unsigned int start_freq, unsigned int end_freq, + unsigned int cpu_id), + + TP_ARGS(start_freq, end_freq, cpu_id), + + TP_STRUCT__entry( + __field( u32, start_freq ) + __field( u32, end_freq ) + __field( u32, cpu_id ) + ), + + TP_fast_assign( + __entry->start_freq = start_freq; + __entry->end_freq = end_freq; + __entry->cpu_id = cpu_id; + ), + + TP_printk("start=%lu end=%lu cpu_id=%lu", + (unsigned long)__entry->start_freq, + (unsigned long)__entry->end_freq, + (unsigned long)__entry->cpu_id) +); + +TRACE_EVENT(cpu_frequency_switch_end, + + TP_PROTO(unsigned int cpu_id), + + TP_ARGS(cpu_id), + + TP_STRUCT__entry( + __field( u32, cpu_id ) + ), + + TP_fast_assign( + __entry->cpu_id = cpu_id; + ), + + TP_printk("cpu_id=%lu", (unsigned long)__entry->cpu_id) +); + +DEFINE_EVENT(cpu, cpu_capacity, + + TP_PROTO(unsigned int capacity, unsigned int cpu_id), + + TP_ARGS(capacity, cpu_id) +); + TRACE_EVENT(device_pm_callback_start, TP_PROTO(struct device *dev, const char *pm_ops, int event), @@ -230,6 +304,7 @@ * The clock events are used for clock enable/disable and for * clock rate change */ +#if defined(CONFIG_COMMON_CLK_MSM) DECLARE_EVENT_CLASS(clock, TP_PROTO(const char *name, unsigned int state, unsigned int cpu_id), @@ -273,6 +348,62 @@ TP_ARGS(name, state, cpu_id) ); +DEFINE_EVENT(clock, clock_set_rate_complete, + + TP_PROTO(const char *name, unsigned int state, unsigned int cpu_id), + + TP_ARGS(name, state, cpu_id) +); + +TRACE_EVENT(clock_set_parent, + + TP_PROTO(const char *name, const char *parent_name), + + TP_ARGS(name, parent_name), + + TP_STRUCT__entry( + __string( name, name ) + __string( parent_name, parent_name ) + ), + + TP_fast_assign( + __assign_str(name, name); + __assign_str(parent_name, parent_name); + ), + + TP_printk("%s parent=%s", __get_str(name), __get_str(parent_name)) +); + +TRACE_EVENT(clock_state, + + TP_PROTO(const char *name, unsigned long prepare_count, + unsigned long count, unsigned long rate, + unsigned int vdd_level), + + TP_ARGS(name, prepare_count, count, rate, vdd_level), + + TP_STRUCT__entry( + __string(name, name) + __field(unsigned long, prepare_count) + __field(unsigned long, count) + __field(unsigned long, rate) + __field(unsigned int, vdd_level) + ), + + TP_fast_assign( + __assign_str(name, name); + __entry->prepare_count = prepare_count; + __entry->count = count; + __entry->rate = rate; + __entry->vdd_level = vdd_level; + ), + + TP_printk("%s\tprepare:enable cnt [%lu:%lu]\trate: vdd level [%lu:%u]", + __get_str(name), __entry->prepare_count, + __entry->count, __entry->rate, __entry->vdd_level) +); +#endif /* CONFIG_COMMON_CLK_MSM */ + /* * The power domain events are used for power domains transitions */ @@ -476,6 +607,494 @@ TP_ARGS(name, type, new_value) ); + +TRACE_EVENT(bw_hwmon_meas, + + TP_PROTO(const char *name, unsigned long mbps, + unsigned long us, int wake), + + TP_ARGS(name, mbps, us, wake), + + TP_STRUCT__entry( + __string( name, name ) + __field( unsigned long, mbps ) + __field( unsigned long, us ) + __field( int, wake ) + ), + + TP_fast_assign( + __assign_str(name, name); + __entry->mbps = mbps; + __entry->us = us; + __entry->wake = wake; + ), + + TP_printk("dev: %s, mbps = %lu, us = %lu, wake = %d", + __get_str(name), + __entry->mbps, + __entry->us, + __entry->wake) +); + +TRACE_EVENT(bw_hwmon_update, + + TP_PROTO(const char *name, unsigned long mbps, unsigned long freq, + unsigned long up_thres, unsigned long down_thres), + + TP_ARGS(name, mbps, freq, up_thres, down_thres), + + TP_STRUCT__entry( + __string( name, name ) + __field( unsigned long, mbps ) + __field( unsigned long, freq ) + __field( unsigned long, up_thres ) + __field( unsigned long, down_thres ) + ), + + TP_fast_assign( + __assign_str(name, name); + __entry->mbps = mbps; + __entry->freq = freq; + __entry->up_thres = up_thres; + __entry->down_thres = down_thres; + ), + + TP_printk("dev: %s, mbps = %lu, freq = %lu, up = %lu, down = %lu", + __get_str(name), + __entry->mbps, + __entry->freq, + __entry->up_thres, + __entry->down_thres) +); + +TRACE_EVENT(cache_hwmon_meas, + TP_PROTO(const char *name, unsigned long high_mrps, + unsigned long med_mrps, unsigned long low_mrps, + unsigned int busy_percent, unsigned int us), + TP_ARGS(name, high_mrps, med_mrps, low_mrps, busy_percent, us), + TP_STRUCT__entry( + __string(name, name) + __field(unsigned long, high_mrps) + __field(unsigned long, med_mrps) + __field(unsigned long, low_mrps) + __field(unsigned long, total_mrps) + __field(unsigned int, busy_percent) + __field(unsigned int, us) + ), + TP_fast_assign( + __assign_str(name, name); + __entry->high_mrps = high_mrps; + __entry->med_mrps = med_mrps; + __entry->low_mrps = low_mrps; + __entry->total_mrps = high_mrps + med_mrps + low_mrps; + __entry->busy_percent = busy_percent; + __entry->us = us; + ), + TP_printk("dev=%s H=%lu M=%lu L=%lu T=%lu busy_pct=%u period=%u", + __get_str(name), __entry->high_mrps, __entry->med_mrps, + __entry->low_mrps, __entry->total_mrps, + __entry->busy_percent, __entry->us) +); + +TRACE_EVENT(cache_hwmon_update, + TP_PROTO(const char *name, unsigned long freq_mhz), + TP_ARGS(name, freq_mhz), + TP_STRUCT__entry( + __string(name, name) + __field(unsigned long, freq) + ), + TP_fast_assign( + __assign_str(name, name); + __entry->freq = freq_mhz; + ), + TP_printk("dev=%s freq=%lu", __get_str(name), __entry->freq) +); + +TRACE_EVENT(memlat_dev_meas, + + TP_PROTO(const char *name, unsigned int dev_id, unsigned long inst, + unsigned long mem, unsigned long freq, unsigned int ratio), + + TP_ARGS(name, dev_id, inst, mem, freq, ratio), + + TP_STRUCT__entry( + __string(name, name) + __field(unsigned int, dev_id) + __field(unsigned long, inst) + __field(unsigned long, mem) + __field(unsigned long, freq) + __field(unsigned int, ratio) + ), + + TP_fast_assign( + __assign_str(name, name); + __entry->dev_id = dev_id; + __entry->inst = inst; + __entry->mem = mem; + __entry->freq = freq; + __entry->ratio = ratio; + ), + + TP_printk("dev: %s, id=%u, inst=%lu, mem=%lu, freq=%lu, ratio=%u", + __get_str(name), + __entry->dev_id, + __entry->inst, + __entry->mem, + __entry->freq, + __entry->ratio) +); + +TRACE_EVENT(memlat_dev_update, + + TP_PROTO(const char *name, unsigned int dev_id, unsigned long inst, + unsigned long mem, unsigned long freq, unsigned long vote), + + TP_ARGS(name, dev_id, inst, mem, freq, vote), + + TP_STRUCT__entry( + __string(name, name) + __field(unsigned int, dev_id) + __field(unsigned long, inst) + __field(unsigned long, mem) + __field(unsigned long, freq) + __field(unsigned long, vote) + ), + + TP_fast_assign( + __assign_str(name, name); + __entry->dev_id = dev_id; + __entry->inst = inst; + __entry->mem = mem; + __entry->freq = freq; + __entry->vote = vote; + ), + + TP_printk("dev: %s, id=%u, inst=%lu, mem=%lu, freq=%lu, vote=%lu", + __get_str(name), + __entry->dev_id, + __entry->inst, + __entry->mem, + __entry->freq, + __entry->vote) +); + +DECLARE_EVENT_CLASS(kpm_module, + + TP_PROTO(unsigned int managed_cpus, unsigned int max_cpus), + + TP_ARGS(managed_cpus, max_cpus), + + TP_STRUCT__entry( + __field(u32, managed_cpus) + __field(u32, max_cpus) + ), + + TP_fast_assign( + __entry->managed_cpus = managed_cpus; + __entry->max_cpus = max_cpus; + ), + + TP_printk("managed:%x max_cpus=%u", (unsigned int)__entry->managed_cpus, + (unsigned int)__entry->max_cpus) +); + +DEFINE_EVENT(kpm_module, set_max_cpus, + TP_PROTO(unsigned int managed_cpus, unsigned int max_cpus), + TP_ARGS(managed_cpus, max_cpus) +); + +DEFINE_EVENT(kpm_module, reevaluate_hotplug, + TP_PROTO(unsigned int managed_cpus, unsigned int max_cpus), + TP_ARGS(managed_cpus, max_cpus) +); + +DECLARE_EVENT_CLASS(kpm_module2, + + TP_PROTO(unsigned int cpu, unsigned int enter_cycle_cnt, + unsigned int exit_cycle_cnt, + unsigned int io_busy, u64 iowait), + + TP_ARGS(cpu, enter_cycle_cnt, exit_cycle_cnt, io_busy, iowait), + + TP_STRUCT__entry( + __field(u32, cpu) + __field(u32, enter_cycle_cnt) + __field(u32, exit_cycle_cnt) + __field(u32, io_busy) + __field(u64, iowait) + ), + + TP_fast_assign( + __entry->cpu = cpu; + __entry->enter_cycle_cnt = enter_cycle_cnt; + __entry->exit_cycle_cnt = exit_cycle_cnt; + __entry->io_busy = io_busy; + __entry->iowait = iowait; + ), + + TP_printk("CPU:%u enter_cycles=%u exit_cycles=%u io_busy=%u iowait=%lu", + (unsigned int)__entry->cpu, + (unsigned int)__entry->enter_cycle_cnt, + (unsigned int)__entry->exit_cycle_cnt, + (unsigned int)__entry->io_busy, + (unsigned long)__entry->iowait) +); + +DEFINE_EVENT(kpm_module2, track_iowait, + TP_PROTO(unsigned int cpu, unsigned int enter_cycle_cnt, + unsigned int exit_cycle_cnt, unsigned int io_busy, u64 iowait), + TP_ARGS(cpu, enter_cycle_cnt, exit_cycle_cnt, io_busy, iowait) +); + +DECLARE_EVENT_CLASS(cpu_modes, + + TP_PROTO(unsigned int cpu, unsigned int max_load, + unsigned int single_enter_cycle_cnt, + unsigned int single_exit_cycle_cnt, + unsigned int total_load, unsigned int multi_enter_cycle_cnt, + unsigned int multi_exit_cycle_cnt, + unsigned int perf_cl_peak_enter_cycle_cnt, + unsigned int perf_cl_peak_exit_cycle_cnt, + unsigned int mode, + unsigned int cpu_cnt), + + TP_ARGS(cpu, max_load, single_enter_cycle_cnt, single_exit_cycle_cnt, + total_load, multi_enter_cycle_cnt, multi_exit_cycle_cnt, + perf_cl_peak_enter_cycle_cnt, perf_cl_peak_exit_cycle_cnt, mode, + cpu_cnt), + + TP_STRUCT__entry( + __field(u32, cpu) + __field(u32, max_load) + __field(u32, single_enter_cycle_cnt) + __field(u32, single_exit_cycle_cnt) + __field(u32, total_load) + __field(u32, multi_enter_cycle_cnt) + __field(u32, multi_exit_cycle_cnt) + __field(u32, perf_cl_peak_enter_cycle_cnt) + __field(u32, perf_cl_peak_exit_cycle_cnt) + __field(u32, mode) + __field(u32, cpu_cnt) + ), + + TP_fast_assign( + __entry->cpu = cpu; + __entry->max_load = max_load; + __entry->single_enter_cycle_cnt = single_enter_cycle_cnt; + __entry->single_exit_cycle_cnt = single_exit_cycle_cnt; + __entry->total_load = total_load; + __entry->multi_enter_cycle_cnt = multi_enter_cycle_cnt; + __entry->multi_exit_cycle_cnt = multi_exit_cycle_cnt; + __entry->perf_cl_peak_enter_cycle_cnt = + perf_cl_peak_enter_cycle_cnt; + __entry->perf_cl_peak_exit_cycle_cnt = + perf_cl_peak_exit_cycle_cnt; + __entry->mode = mode; + __entry->cpu_cnt = cpu_cnt; + ), + + TP_printk("%u:%4u:%4u:%4u:%4u:%4u:%4u:%4u:%4u:%4u:%u", + (unsigned int)__entry->cpu, (unsigned int)__entry->max_load, + (unsigned int)__entry->single_enter_cycle_cnt, + (unsigned int)__entry->single_exit_cycle_cnt, + (unsigned int)__entry->total_load, + (unsigned int)__entry->multi_enter_cycle_cnt, + (unsigned int)__entry->multi_exit_cycle_cnt, + (unsigned int)__entry->perf_cl_peak_enter_cycle_cnt, + (unsigned int)__entry->perf_cl_peak_exit_cycle_cnt, + (unsigned int)__entry->mode, + (unsigned int)__entry->cpu_cnt) +); + +DEFINE_EVENT(cpu_modes, cpu_mode_detect, + TP_PROTO(unsigned int cpu, unsigned int max_load, + unsigned int single_enter_cycle_cnt, + unsigned int single_exit_cycle_cnt, + unsigned int total_load, unsigned int multi_enter_cycle_cnt, + unsigned int multi_exit_cycle_cnt, + unsigned int perf_cl_peak_enter_cycle_cnt, + unsigned int perf_cl_peak_exit_cycle_cnt, + unsigned int mode, + unsigned int cpu_cnt), + TP_ARGS(cpu, max_load, single_enter_cycle_cnt, single_exit_cycle_cnt, + total_load, multi_enter_cycle_cnt, multi_exit_cycle_cnt, + perf_cl_peak_enter_cycle_cnt, perf_cl_peak_exit_cycle_cnt, + mode, cpu_cnt) +); + +DECLARE_EVENT_CLASS(timer_status, + TP_PROTO(unsigned int cpu, unsigned int single_enter_cycles, + unsigned int single_enter_cycle_cnt, + unsigned int single_exit_cycles, + unsigned int single_exit_cycle_cnt, + unsigned int multi_enter_cycles, + unsigned int multi_enter_cycle_cnt, + unsigned int multi_exit_cycles, + unsigned int multi_exit_cycle_cnt, unsigned int timer_rate, + unsigned int mode), + TP_ARGS(cpu, single_enter_cycles, single_enter_cycle_cnt, + single_exit_cycles, single_exit_cycle_cnt, multi_enter_cycles, + multi_enter_cycle_cnt, multi_exit_cycles, + multi_exit_cycle_cnt, timer_rate, mode), + + TP_STRUCT__entry( + __field(unsigned int, cpu) + __field(unsigned int, single_enter_cycles) + __field(unsigned int, single_enter_cycle_cnt) + __field(unsigned int, single_exit_cycles) + __field(unsigned int, single_exit_cycle_cnt) + __field(unsigned int, multi_enter_cycles) + __field(unsigned int, multi_enter_cycle_cnt) + __field(unsigned int, multi_exit_cycles) + __field(unsigned int, multi_exit_cycle_cnt) + __field(unsigned int, timer_rate) + __field(unsigned int, mode) + ), + + TP_fast_assign( + __entry->cpu = cpu; + __entry->single_enter_cycles = single_enter_cycles; + __entry->single_enter_cycle_cnt = single_enter_cycle_cnt; + __entry->single_exit_cycles = single_exit_cycles; + __entry->single_exit_cycle_cnt = single_exit_cycle_cnt; + __entry->multi_enter_cycles = multi_enter_cycles; + __entry->multi_enter_cycle_cnt = multi_enter_cycle_cnt; + __entry->multi_exit_cycles = multi_exit_cycles; + __entry->multi_exit_cycle_cnt = multi_exit_cycle_cnt; + __entry->timer_rate = timer_rate; + __entry->mode = mode; + ), + + TP_printk("%u:%4u:%4u:%4u:%4u:%4u:%4u:%4u:%4u:%4u:%4u", + (unsigned int) __entry->cpu, + (unsigned int) __entry->single_enter_cycles, + (unsigned int) __entry->single_enter_cycle_cnt, + (unsigned int) __entry->single_exit_cycles, + (unsigned int) __entry->single_exit_cycle_cnt, + (unsigned int) __entry->multi_enter_cycles, + (unsigned int) __entry->multi_enter_cycle_cnt, + (unsigned int) __entry->multi_exit_cycles, + (unsigned int) __entry->multi_exit_cycle_cnt, + (unsigned int) __entry->timer_rate, + (unsigned int) __entry->mode) +); + +DEFINE_EVENT(timer_status, single_mode_timeout, + TP_PROTO(unsigned int cpu, unsigned int single_enter_cycles, + unsigned int single_enter_cycle_cnt, + unsigned int single_exit_cycles, + unsigned int single_exit_cycle_cnt, + unsigned int multi_enter_cycles, + unsigned int multi_enter_cycle_cnt, + unsigned int multi_exit_cycles, + unsigned int multi_exit_cycle_cnt, unsigned int timer_rate, + unsigned int mode), + TP_ARGS(cpu, single_enter_cycles, single_enter_cycle_cnt, + single_exit_cycles, single_exit_cycle_cnt, multi_enter_cycles, + multi_enter_cycle_cnt, multi_exit_cycles, multi_exit_cycle_cnt, + timer_rate, mode) +); + +DEFINE_EVENT(timer_status, single_cycle_exit_timer_start, + TP_PROTO(unsigned int cpu, unsigned int single_enter_cycles, + unsigned int single_enter_cycle_cnt, + unsigned int single_exit_cycles, + unsigned int single_exit_cycle_cnt, + unsigned int multi_enter_cycles, + unsigned int multi_enter_cycle_cnt, + unsigned int multi_exit_cycles, + unsigned int multi_exit_cycle_cnt, unsigned int timer_rate, + unsigned int mode), + TP_ARGS(cpu, single_enter_cycles, single_enter_cycle_cnt, + single_exit_cycles, single_exit_cycle_cnt, multi_enter_cycles, + multi_enter_cycle_cnt, multi_exit_cycles, multi_exit_cycle_cnt, + timer_rate, mode) +); + +DEFINE_EVENT(timer_status, single_cycle_exit_timer_stop, + TP_PROTO(unsigned int cpu, unsigned int single_enter_cycles, + unsigned int single_enter_cycle_cnt, + unsigned int single_exit_cycles, + unsigned int single_exit_cycle_cnt, + unsigned int multi_enter_cycles, + unsigned int multi_enter_cycle_cnt, + unsigned int multi_exit_cycles, + unsigned int multi_exit_cycle_cnt, unsigned int timer_rate, + unsigned int mode), + TP_ARGS(cpu, single_enter_cycles, single_enter_cycle_cnt, + single_exit_cycles, single_exit_cycle_cnt, multi_enter_cycles, + multi_enter_cycle_cnt, multi_exit_cycles, multi_exit_cycle_cnt, + timer_rate, mode) +); + +DECLARE_EVENT_CLASS(perf_cl_peak_timer_status, + TP_PROTO(unsigned int cpu, unsigned int perf_cl_peak_enter_cycles, + unsigned int perf_cl_peak_enter_cycle_cnt, + unsigned int perf_cl_peak_exit_cycles, + unsigned int perf_cl_peak_exit_cycle_cnt, + unsigned int timer_rate, + unsigned int mode), + TP_ARGS(cpu, perf_cl_peak_enter_cycles, perf_cl_peak_enter_cycle_cnt, + perf_cl_peak_exit_cycles, perf_cl_peak_exit_cycle_cnt, + timer_rate, mode), + + TP_STRUCT__entry( + __field(unsigned int, cpu) + __field(unsigned int, perf_cl_peak_enter_cycles) + __field(unsigned int, perf_cl_peak_enter_cycle_cnt) + __field(unsigned int, perf_cl_peak_exit_cycles) + __field(unsigned int, perf_cl_peak_exit_cycle_cnt) + __field(unsigned int, timer_rate) + __field(unsigned int, mode) + ), + + TP_fast_assign( + __entry->cpu = cpu; + __entry->perf_cl_peak_enter_cycles = perf_cl_peak_enter_cycles; + __entry->perf_cl_peak_enter_cycle_cnt = + perf_cl_peak_enter_cycle_cnt; + __entry->perf_cl_peak_exit_cycles = perf_cl_peak_exit_cycles; + __entry->perf_cl_peak_exit_cycle_cnt = + perf_cl_peak_exit_cycle_cnt; + __entry->timer_rate = timer_rate; + __entry->mode = mode; + ), + + TP_printk("%u:%4u:%4u:%4u:%4u:%4u:%4u", + (unsigned int) __entry->cpu, + (unsigned int) __entry->perf_cl_peak_enter_cycles, + (unsigned int) __entry->perf_cl_peak_enter_cycle_cnt, + (unsigned int) __entry->perf_cl_peak_exit_cycles, + (unsigned int) __entry->perf_cl_peak_exit_cycle_cnt, + (unsigned int) __entry->timer_rate, + (unsigned int) __entry->mode) +); + +DEFINE_EVENT(perf_cl_peak_timer_status, perf_cl_peak_exit_timer_start, + TP_PROTO(unsigned int cpu, unsigned int perf_cl_peak_enter_cycles, + unsigned int perf_cl_peak_enter_cycle_cnt, + unsigned int perf_cl_peak_exit_cycles, + unsigned int perf_cl_peak_exit_cycle_cnt, + unsigned int timer_rate, + unsigned int mode), + TP_ARGS(cpu, perf_cl_peak_enter_cycles, perf_cl_peak_enter_cycle_cnt, + perf_cl_peak_exit_cycles, perf_cl_peak_exit_cycle_cnt, + timer_rate, mode) +); + + +DEFINE_EVENT(perf_cl_peak_timer_status, perf_cl_peak_exit_timer_stop, + TP_PROTO(unsigned int cpu, unsigned int perf_cl_peak_enter_cycles, + unsigned int perf_cl_peak_enter_cycle_cnt, + unsigned int perf_cl_peak_exit_cycles, + unsigned int perf_cl_peak_exit_cycle_cnt, + unsigned int timer_rate, + unsigned int mode), + TP_ARGS(cpu, perf_cl_peak_enter_cycles, perf_cl_peak_enter_cycle_cnt, + perf_cl_peak_exit_cycles, perf_cl_peak_exit_cycle_cnt, + timer_rate, mode) +); + #endif /* _TRACE_POWER_H */ /* This part must be outside protection */ diff -ruw linux-4.4.115/include/trace/events/sched.h linux-4.4.115-fbx/include/trace/events/sched.h --- linux-4.4.115/include/trace/events/sched.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/trace/events/sched.h 2019-10-29 09:26:25.537221713 +0100 @@ -8,6 +8,8 @@ #include #include +struct rq; + /* * Tracepoint for calling kthread_stop, performed to end a kthread: */ @@ -51,6 +53,653 @@ ); /* + * Tracepoint for task enqueue/dequeue: + */ +TRACE_EVENT(sched_enq_deq_task, + + TP_PROTO(struct task_struct *p, bool enqueue, unsigned int cpus_allowed), + + TP_ARGS(p, enqueue, cpus_allowed), + + TP_STRUCT__entry( + __array( char, comm, TASK_COMM_LEN ) + __field( pid_t, pid ) + __field( int, prio ) + __field( int, cpu ) + __field( bool, enqueue ) + __field(unsigned int, nr_running ) + __field(unsigned long, cpu_load ) + __field(unsigned int, rt_nr_running ) + __field(unsigned int, cpus_allowed ) +#ifdef CONFIG_SCHED_HMP + __field(unsigned int, demand ) + __field(unsigned int, pred_demand ) +#endif + ), + + TP_fast_assign( + memcpy(__entry->comm, p->comm, TASK_COMM_LEN); + __entry->pid = p->pid; + __entry->prio = p->prio; + __entry->cpu = task_cpu(p); + __entry->enqueue = enqueue; + __entry->nr_running = task_rq(p)->nr_running; + __entry->cpu_load = task_rq(p)->cpu_load[0]; + __entry->rt_nr_running = task_rq(p)->rt.rt_nr_running; + __entry->cpus_allowed = cpus_allowed; +#ifdef CONFIG_SCHED_HMP + __entry->demand = p->ravg.demand; + __entry->pred_demand = p->ravg.pred_demand; +#endif + ), + + TP_printk("cpu=%d %s comm=%s pid=%d prio=%d nr_running=%u cpu_load=%lu rt_nr_running=%u affine=%x" +#ifdef CONFIG_SCHED_HMP + " demand=%u pred_demand=%u" +#endif + , __entry->cpu, + __entry->enqueue ? "enqueue" : "dequeue", + __entry->comm, __entry->pid, + __entry->prio, __entry->nr_running, + __entry->cpu_load, __entry->rt_nr_running, __entry->cpus_allowed +#ifdef CONFIG_SCHED_HMP + , __entry->demand, __entry->pred_demand +#endif + ) +); + +#ifdef CONFIG_SCHED_HMP + +struct group_cpu_time; +struct migration_sum_data; +extern const char *task_event_names[]; +extern const char *migrate_type_names[]; + +TRACE_EVENT(sched_task_load, + + TP_PROTO(struct task_struct *p, bool boost, int reason, + bool sync, bool need_idle, u32 flags, int best_cpu), + + TP_ARGS(p, boost, reason, sync, need_idle, flags, best_cpu), + + TP_STRUCT__entry( + __array( char, comm, TASK_COMM_LEN ) + __field( pid_t, pid ) + __field(unsigned int, demand ) + __field( bool, boost ) + __field( int, reason ) + __field( bool, sync ) + __field( bool, need_idle ) + __field( u32, flags ) + __field( int, best_cpu ) + __field( u64, latency ) + __field( int, grp_id ) + __field( u64, avg_burst ) + __field( u64, avg_sleep ) + ), + + TP_fast_assign( + memcpy(__entry->comm, p->comm, TASK_COMM_LEN); + __entry->pid = p->pid; + __entry->demand = p->ravg.demand; + __entry->boost = boost; + __entry->reason = reason; + __entry->sync = sync; + __entry->need_idle = need_idle; + __entry->flags = flags; + __entry->best_cpu = best_cpu; + __entry->latency = p->state == TASK_WAKING ? + sched_ktime_clock() - + p->ravg.mark_start : 0; + __entry->grp_id = p->grp ? p->grp->id : 0; + __entry->avg_burst = p->ravg.avg_burst; + __entry->avg_sleep = p->ravg.avg_sleep_time; + ), + + TP_printk("%d (%s): demand=%u boost=%d reason=%d sync=%d need_idle=%d flags=%x grp=%d best_cpu=%d latency=%llu avg_burst=%llu avg_sleep=%llu", + __entry->pid, __entry->comm, __entry->demand, + __entry->boost, __entry->reason, __entry->sync, + __entry->need_idle, __entry->flags, __entry->grp_id, + __entry->best_cpu, __entry->latency, __entry->avg_burst, + __entry->avg_sleep) +); + +TRACE_EVENT(sched_set_preferred_cluster, + + TP_PROTO(struct related_thread_group *grp, u64 total_demand), + + TP_ARGS(grp, total_demand), + + TP_STRUCT__entry( + __field( int, id ) + __field( u64, demand ) + __field( int, cluster_first_cpu ) + __array( char, comm, TASK_COMM_LEN ) + __field( pid_t, pid ) + __field(unsigned int, task_demand ) + ), + + TP_fast_assign( + __entry->id = grp->id; + __entry->demand = total_demand; + __entry->cluster_first_cpu = grp->preferred_cluster ? + cluster_first_cpu(grp->preferred_cluster) + : -1; + ), + + TP_printk("group_id %d total_demand %llu preferred_cluster_first_cpu %d", + __entry->id, __entry->demand, + __entry->cluster_first_cpu) +); + +DECLARE_EVENT_CLASS(sched_cpu_load, + + TP_PROTO(struct rq *rq, int idle, u64 irqload, unsigned int power_cost, int temp), + + TP_ARGS(rq, idle, irqload, power_cost, temp), + + TP_STRUCT__entry( + __field(unsigned int, cpu ) + __field(unsigned int, idle ) + __field(unsigned int, nr_running ) + __field(unsigned int, nr_big_tasks ) + __field(unsigned int, load_scale_factor ) + __field(unsigned int, capacity ) + __field( u64, cumulative_runnable_avg ) + __field( u64, irqload ) + __field(unsigned int, max_freq ) + __field(unsigned int, power_cost ) + __field( int, cstate ) + __field( int, dstate ) + __field( int, temp ) + ), + + TP_fast_assign( + __entry->cpu = rq->cpu; + __entry->idle = idle; + __entry->nr_running = rq->nr_running; + __entry->nr_big_tasks = rq->hmp_stats.nr_big_tasks; + __entry->load_scale_factor = cpu_load_scale_factor(rq->cpu); + __entry->capacity = cpu_capacity(rq->cpu); + __entry->cumulative_runnable_avg = rq->hmp_stats.cumulative_runnable_avg; + __entry->irqload = irqload; + __entry->max_freq = cpu_max_freq(rq->cpu); + __entry->power_cost = power_cost; + __entry->cstate = rq->cstate; + __entry->dstate = rq->cluster->dstate; + __entry->temp = temp; + ), + + TP_printk("cpu %u idle %d nr_run %u nr_big %u lsf %u capacity %u cr_avg %llu irqload %llu fmax %u power_cost %u cstate %d dstate %d temp %d", + __entry->cpu, __entry->idle, __entry->nr_running, __entry->nr_big_tasks, + __entry->load_scale_factor, __entry->capacity, + __entry->cumulative_runnable_avg, __entry->irqload, + __entry->max_freq, __entry->power_cost, __entry->cstate, + __entry->dstate, __entry->temp) +); + +DEFINE_EVENT(sched_cpu_load, sched_cpu_load_wakeup, + TP_PROTO(struct rq *rq, int idle, u64 irqload, unsigned int power_cost, int temp), + TP_ARGS(rq, idle, irqload, power_cost, temp) +); + +DEFINE_EVENT(sched_cpu_load, sched_cpu_load_lb, + TP_PROTO(struct rq *rq, int idle, u64 irqload, unsigned int power_cost, int temp), + TP_ARGS(rq, idle, irqload, power_cost, temp) +); + +DEFINE_EVENT(sched_cpu_load, sched_cpu_load_cgroup, + TP_PROTO(struct rq *rq, int idle, u64 irqload, unsigned int power_cost, int temp), + TP_ARGS(rq, idle, irqload, power_cost, temp) +); + +TRACE_EVENT(sched_set_boost, + + TP_PROTO(int type), + + TP_ARGS(type), + + TP_STRUCT__entry( + __field(int, type ) + ), + + TP_fast_assign( + __entry->type = type; + ), + + TP_printk("type %d", __entry->type) +); + +#if defined(CREATE_TRACE_POINTS) && defined(CONFIG_SCHED_HMP) +static inline void __window_data(u32 *dst, u32 *src) +{ + if (src) + memcpy(dst, src, nr_cpu_ids * sizeof(u32)); + else + memset(dst, 0, nr_cpu_ids * sizeof(u32)); +} + +struct trace_seq; +const char *__window_print(struct trace_seq *p, const u32 *buf, int buf_len) +{ + int i; + const char *ret = p->buffer + seq_buf_used(&p->seq); + + for (i = 0; i < buf_len; i++) + trace_seq_printf(p, "%u ", buf[i]); + + trace_seq_putc(p, 0); + + return ret; +} + +static inline s64 __rq_update_sum(struct rq *rq, bool curr, bool new) +{ + if (curr) + if (new) + return rq->nt_curr_runnable_sum; + else + return rq->curr_runnable_sum; + else + if (new) + return rq->nt_prev_runnable_sum; + else + return rq->prev_runnable_sum; +} + +static inline s64 __grp_update_sum(struct rq *rq, bool curr, bool new) +{ + if (curr) + if (new) + return rq->grp_time.nt_curr_runnable_sum; + else + return rq->grp_time.curr_runnable_sum; + else + if (new) + return rq->grp_time.nt_prev_runnable_sum; + else + return rq->grp_time.prev_runnable_sum; +} + +static inline s64 +__get_update_sum(struct rq *rq, enum migrate_types migrate_type, + bool src, bool new, bool curr) +{ + switch (migrate_type) { + case RQ_TO_GROUP: + if (src) + return __rq_update_sum(rq, curr, new); + else + return __grp_update_sum(rq, curr, new); + case GROUP_TO_RQ: + if (src) + return __grp_update_sum(rq, curr, new); + else + return __rq_update_sum(rq, curr, new); + default: + WARN_ON_ONCE(1); + return -1; + } +} +#endif + +TRACE_EVENT(sched_update_task_ravg, + + TP_PROTO(struct task_struct *p, struct rq *rq, enum task_event evt, + u64 wallclock, u64 irqtime, u64 cycles, u64 exec_time, + struct group_cpu_time *cpu_time), + + TP_ARGS(p, rq, evt, wallclock, irqtime, cycles, exec_time, cpu_time), + + TP_STRUCT__entry( + __array( char, comm, TASK_COMM_LEN ) + __field( pid_t, pid ) + __field( pid_t, cur_pid ) + __field(unsigned int, cur_freq ) + __field( u64, wallclock ) + __field( u64, mark_start ) + __field( u64, delta_m ) + __field( u64, win_start ) + __field( u64, delta ) + __field( u64, irqtime ) + __field(enum task_event, evt ) + __field(unsigned int, demand ) + __field(unsigned int, sum ) + __field( int, cpu ) + __field(unsigned int, pred_demand ) + __field( u64, rq_cs ) + __field( u64, rq_ps ) + __field( u64, grp_cs ) + __field( u64, grp_ps ) + __field( u64, grp_nt_cs ) + __field( u64, grp_nt_ps ) + __field( u32, curr_window ) + __field( u32, prev_window ) + __dynamic_array(u32, curr_sum, nr_cpu_ids ) + __dynamic_array(u32, prev_sum, nr_cpu_ids ) + __field( u64, nt_cs ) + __field( u64, nt_ps ) + __field( u32, active_windows ) + __field( u8, curr_top ) + __field( u8, prev_top ) + ), + + TP_fast_assign( + __entry->wallclock = wallclock; + __entry->win_start = rq->window_start; + __entry->delta = (wallclock - rq->window_start); + __entry->evt = evt; + __entry->cpu = rq->cpu; + __entry->cur_pid = rq->curr->pid; + __entry->cur_freq = cpu_cycles_to_freq(cycles, exec_time); + memcpy(__entry->comm, p->comm, TASK_COMM_LEN); + __entry->pid = p->pid; + __entry->mark_start = p->ravg.mark_start; + __entry->delta_m = (wallclock - p->ravg.mark_start); + __entry->demand = p->ravg.demand; + __entry->sum = p->ravg.sum; + __entry->irqtime = irqtime; + __entry->pred_demand = p->ravg.pred_demand; + __entry->rq_cs = rq->curr_runnable_sum; + __entry->rq_ps = rq->prev_runnable_sum; + __entry->grp_cs = cpu_time ? cpu_time->curr_runnable_sum : 0; + __entry->grp_ps = cpu_time ? cpu_time->prev_runnable_sum : 0; + __entry->grp_nt_cs = cpu_time ? cpu_time->nt_curr_runnable_sum : 0; + __entry->grp_nt_ps = cpu_time ? cpu_time->nt_prev_runnable_sum : 0; + __entry->curr_window = p->ravg.curr_window; + __entry->prev_window = p->ravg.prev_window; + __window_data(__get_dynamic_array(curr_sum), p->ravg.curr_window_cpu); + __window_data(__get_dynamic_array(prev_sum), p->ravg.prev_window_cpu); + __entry->nt_cs = rq->nt_curr_runnable_sum; + __entry->nt_ps = rq->nt_prev_runnable_sum; + __entry->active_windows = p->ravg.active_windows; + __entry->curr_top = rq->curr_top; + __entry->prev_top = rq->prev_top; + ), + + TP_printk("wc %llu ws %llu delta %llu event %s cpu %d cur_freq %u cur_pid %d task %d (%s) ms %llu delta %llu demand %u sum %u irqtime %llu pred_demand %u rq_cs %llu rq_ps %llu cur_window %u (%s) prev_window %u (%s) nt_cs %llu nt_ps %llu active_wins %u grp_cs %lld grp_ps %lld, grp_nt_cs %llu, grp_nt_ps: %llu curr_top %u prev_top %u", + __entry->wallclock, __entry->win_start, __entry->delta, + task_event_names[__entry->evt], __entry->cpu, + __entry->cur_freq, __entry->cur_pid, + __entry->pid, __entry->comm, __entry->mark_start, + __entry->delta_m, __entry->demand, + __entry->sum, __entry->irqtime, __entry->pred_demand, + __entry->rq_cs, __entry->rq_ps, __entry->curr_window, + __window_print(p, __get_dynamic_array(curr_sum), nr_cpu_ids), + __entry->prev_window, + __window_print(p, __get_dynamic_array(prev_sum), nr_cpu_ids), + __entry->nt_cs, __entry->nt_ps, + __entry->active_windows, __entry->grp_cs, + __entry->grp_ps, __entry->grp_nt_cs, __entry->grp_nt_ps, + __entry->curr_top, __entry->prev_top) +); + +TRACE_EVENT(sched_get_task_cpu_cycles, + + TP_PROTO(int cpu, int event, u64 cycles, u64 exec_time, struct task_struct *p), + + TP_ARGS(cpu, event, cycles, exec_time, p), + + TP_STRUCT__entry( + __field(int, cpu ) + __field(int, event ) + __field(u64, cycles ) + __field(u64, exec_time ) + __field(u32, freq ) + __field(u32, legacy_freq ) + __field(u32, max_freq) + __field(pid_t, pid ) + __array(char, comm, TASK_COMM_LEN ) + ), + + TP_fast_assign( + __entry->cpu = cpu; + __entry->event = event; + __entry->cycles = cycles; + __entry->exec_time = exec_time; + __entry->freq = cpu_cycles_to_freq(cycles, exec_time); + __entry->legacy_freq = cpu_cur_freq(cpu); + __entry->max_freq = cpu_max_freq(cpu); + __entry->pid = p->pid; + memcpy(__entry->comm, p->comm, TASK_COMM_LEN); + ), + + TP_printk("cpu=%d event=%d cycles=%llu exec_time=%llu freq=%u legacy_freq=%u max_freq=%u task=%d (%s)", + __entry->cpu, __entry->event, __entry->cycles, + __entry->exec_time, __entry->freq, __entry->legacy_freq, + __entry->max_freq, __entry->pid, __entry->comm) +); + +TRACE_EVENT(sched_update_history, + + TP_PROTO(struct rq *rq, struct task_struct *p, u32 runtime, int samples, + enum task_event evt), + + TP_ARGS(rq, p, runtime, samples, evt), + + TP_STRUCT__entry( + __array( char, comm, TASK_COMM_LEN ) + __field( pid_t, pid ) + __field(unsigned int, runtime ) + __field( int, samples ) + __field(enum task_event, evt ) + __field(unsigned int, demand ) + __field(unsigned int, pred_demand ) + __array( u32, hist, RAVG_HIST_SIZE_MAX) + __field(unsigned int, nr_big_tasks ) + __field( int, cpu ) + ), + + TP_fast_assign( + memcpy(__entry->comm, p->comm, TASK_COMM_LEN); + __entry->pid = p->pid; + __entry->runtime = runtime; + __entry->samples = samples; + __entry->evt = evt; + __entry->demand = p->ravg.demand; + __entry->pred_demand = p->ravg.pred_demand; + memcpy(__entry->hist, p->ravg.sum_history, + RAVG_HIST_SIZE_MAX * sizeof(u32)); + __entry->nr_big_tasks = rq->hmp_stats.nr_big_tasks; + __entry->cpu = rq->cpu; + ), + + TP_printk("%d (%s): runtime %u samples %d event %s demand %u pred_demand %u" + " (hist: %u %u %u %u %u) cpu %d nr_big %u", + __entry->pid, __entry->comm, + __entry->runtime, __entry->samples, + task_event_names[__entry->evt], + __entry->demand, __entry->pred_demand, + __entry->hist[0], __entry->hist[1], + __entry->hist[2], __entry->hist[3], + __entry->hist[4], __entry->cpu, __entry->nr_big_tasks) +); + +TRACE_EVENT(sched_reset_all_window_stats, + + TP_PROTO(u64 window_start, u64 window_size, u64 time_taken, + int reason, unsigned int old_val, unsigned int new_val), + + TP_ARGS(window_start, window_size, time_taken, + reason, old_val, new_val), + + TP_STRUCT__entry( + __field( u64, window_start ) + __field( u64, window_size ) + __field( u64, time_taken ) + __field( int, reason ) + __field(unsigned int, old_val ) + __field(unsigned int, new_val ) + ), + + TP_fast_assign( + __entry->window_start = window_start; + __entry->window_size = window_size; + __entry->time_taken = time_taken; + __entry->reason = reason; + __entry->old_val = old_val; + __entry->new_val = new_val; + ), + + TP_printk("time_taken %llu window_start %llu window_size %llu reason %s old_val %u new_val %u", + __entry->time_taken, __entry->window_start, + __entry->window_size, + sched_window_reset_reasons[__entry->reason], + __entry->old_val, __entry->new_val) +); + +TRACE_EVENT(sched_update_pred_demand, + + TP_PROTO(struct rq *rq, struct task_struct *p, u32 runtime, int pct, + unsigned int pred_demand), + + TP_ARGS(rq, p, runtime, pct, pred_demand), + + TP_STRUCT__entry( + __array( char, comm, TASK_COMM_LEN ) + __field( pid_t, pid ) + __field(unsigned int, runtime ) + __field( int, pct ) + __field(unsigned int, pred_demand ) + __array( u8, bucket, NUM_BUSY_BUCKETS) + __field( int, cpu ) + ), + + TP_fast_assign( + memcpy(__entry->comm, p->comm, TASK_COMM_LEN); + __entry->pid = p->pid; + __entry->runtime = runtime; + __entry->pct = pct; + __entry->pred_demand = pred_demand; + memcpy(__entry->bucket, p->ravg.busy_buckets, + NUM_BUSY_BUCKETS * sizeof(u8)); + __entry->cpu = rq->cpu; + ), + + TP_printk("%d (%s): runtime %u pct %d cpu %d pred_demand %u (buckets: %u %u %u %u %u %u %u %u %u %u)", + __entry->pid, __entry->comm, + __entry->runtime, __entry->pct, __entry->cpu, + __entry->pred_demand, __entry->bucket[0], __entry->bucket[1], + __entry->bucket[2], __entry->bucket[3],__entry->bucket[4], + __entry->bucket[5], __entry->bucket[6], __entry->bucket[7], + __entry->bucket[8], __entry->bucket[9]) +); + +TRACE_EVENT(sched_migration_update_sum, + + TP_PROTO(struct task_struct *p, enum migrate_types migrate_type, struct rq *rq), + + TP_ARGS(p, migrate_type, rq), + + TP_STRUCT__entry( + __field(int, tcpu ) + __field(int, pid ) + __field(enum migrate_types, migrate_type ) + __field( s64, src_cs ) + __field( s64, src_ps ) + __field( s64, dst_cs ) + __field( s64, dst_ps ) + __field( s64, src_nt_cs ) + __field( s64, src_nt_ps ) + __field( s64, dst_nt_cs ) + __field( s64, dst_nt_ps ) + ), + + TP_fast_assign( + __entry->tcpu = task_cpu(p); + __entry->pid = p->pid; + __entry->migrate_type = migrate_type; + __entry->src_cs = __get_update_sum(rq, migrate_type, + true, false, true); + __entry->src_ps = __get_update_sum(rq, migrate_type, + true, false, false); + __entry->dst_cs = __get_update_sum(rq, migrate_type, + false, false, true); + __entry->dst_ps = __get_update_sum(rq, migrate_type, + false, false, false); + __entry->src_nt_cs = __get_update_sum(rq, migrate_type, + true, true, true); + __entry->src_nt_ps = __get_update_sum(rq, migrate_type, + true, true, false); + __entry->dst_nt_cs = __get_update_sum(rq, migrate_type, + false, true, true); + __entry->dst_nt_ps = __get_update_sum(rq, migrate_type, + false, true, false); + ), + + TP_printk("pid %d task_cpu %d migrate_type %s src_cs %llu src_ps %llu dst_cs %lld dst_ps %lld src_nt_cs %llu src_nt_ps %llu dst_nt_cs %lld dst_nt_ps %lld", + __entry->pid, __entry->tcpu, migrate_type_names[__entry->migrate_type], + __entry->src_cs, __entry->src_ps, __entry->dst_cs, __entry->dst_ps, + __entry->src_nt_cs, __entry->src_nt_ps, __entry->dst_nt_cs, __entry->dst_nt_ps) +); + +TRACE_EVENT(sched_get_busy, + + TP_PROTO(int cpu, u64 load, u64 nload, u64 pload, int early, bool aggregated), + + TP_ARGS(cpu, load, nload, pload, early, aggregated), + + TP_STRUCT__entry( + __field( int, cpu ) + __field( u64, load ) + __field( u64, nload ) + __field( u64, pload ) + __field( int, early ) + __field( bool, aggregated ) + ), + + TP_fast_assign( + __entry->cpu = cpu; + __entry->load = load; + __entry->nload = nload; + __entry->pload = pload; + __entry->early = early; + __entry->aggregated = aggregated; + ), + + TP_printk("cpu %d load %lld new_task_load %lld predicted_load %lld early %d aggregated %d", + __entry->cpu, __entry->load, __entry->nload, + __entry->pload, __entry->early, __entry->aggregated) +); + +TRACE_EVENT(sched_freq_alert, + + TP_PROTO(int cpu, int pd_notif, int check_groups, struct rq *rq, + u64 new_load), + + TP_ARGS(cpu, pd_notif, check_groups, rq, new_load), + + TP_STRUCT__entry( + __field( int, cpu ) + __field( int, pd_notif ) + __field( int, check_groups ) + __field( u64, old_busy_time ) + __field( u64, ps ) + __field( u64, new_load ) + __field( u64, old_pred ) + __field( u64, new_pred ) + ), + + TP_fast_assign( + __entry->cpu = cpu; + __entry->pd_notif = pd_notif; + __entry->check_groups = check_groups; + __entry->old_busy_time = rq->old_busy_time; + __entry->ps = rq->prev_runnable_sum; + __entry->new_load = new_load; + __entry->old_pred = rq->old_estimated_time; + __entry->new_pred = rq->hmp_stats.pred_demands_sum; + ), + + TP_printk("cpu %d pd_notif=%d check_groups %d old_busy_time=%llu prev_sum=%lld new_load=%llu old_pred=%llu new_pred=%llu", + __entry->cpu, __entry->pd_notif, __entry->check_groups, + __entry->old_busy_time, __entry->ps, __entry->new_load, + __entry->old_pred, __entry->new_pred) +); + +#endif /* CONFIG_SCHED_HMP */ + +/* * Tracepoint for waking up a task: */ DECLARE_EVENT_CLASS(sched_wakeup_template, @@ -166,14 +815,16 @@ */ TRACE_EVENT(sched_migrate_task, - TP_PROTO(struct task_struct *p, int dest_cpu), + TP_PROTO(struct task_struct *p, int dest_cpu, + unsigned int load), - TP_ARGS(p, dest_cpu), + TP_ARGS(p, dest_cpu, load), TP_STRUCT__entry( __array( char, comm, TASK_COMM_LEN ) __field( pid_t, pid ) __field( int, prio ) + __field(unsigned int, load ) __field( int, orig_cpu ) __field( int, dest_cpu ) ), @@ -182,15 +833,91 @@ memcpy(__entry->comm, p->comm, TASK_COMM_LEN); __entry->pid = p->pid; __entry->prio = p->prio; + __entry->load = load; __entry->orig_cpu = task_cpu(p); __entry->dest_cpu = dest_cpu; ), - TP_printk("comm=%s pid=%d prio=%d orig_cpu=%d dest_cpu=%d", - __entry->comm, __entry->pid, __entry->prio, + TP_printk("comm=%s pid=%d prio=%d load=%d orig_cpu=%d dest_cpu=%d", + __entry->comm, __entry->pid, __entry->prio, __entry->load, __entry->orig_cpu, __entry->dest_cpu) ); +/* + * Tracepoint for a CPU going offline/online: + */ +TRACE_EVENT(sched_cpu_hotplug, + + TP_PROTO(int affected_cpu, int error, int status), + + TP_ARGS(affected_cpu, error, status), + + TP_STRUCT__entry( + __field( int, affected_cpu ) + __field( int, error ) + __field( int, status ) + ), + + TP_fast_assign( + __entry->affected_cpu = affected_cpu; + __entry->error = error; + __entry->status = status; + ), + + TP_printk("cpu %d %s error=%d", __entry->affected_cpu, + __entry->status ? "online" : "offline", __entry->error) +); + +/* + * Tracepoint for load balancing: + */ +#if NR_CPUS > 32 +#error "Unsupported NR_CPUS for lb tracepoint." +#endif +TRACE_EVENT(sched_load_balance, + + TP_PROTO(int cpu, enum cpu_idle_type idle, int balance, + unsigned long group_mask, int busiest_nr_running, + unsigned long imbalance, unsigned int env_flags, int ld_moved, + unsigned int balance_interval), + + TP_ARGS(cpu, idle, balance, group_mask, busiest_nr_running, + imbalance, env_flags, ld_moved, balance_interval), + + TP_STRUCT__entry( + __field( int, cpu) + __field( enum cpu_idle_type, idle) + __field( int, balance) + __field( unsigned long, group_mask) + __field( int, busiest_nr_running) + __field( unsigned long, imbalance) + __field( unsigned int, env_flags) + __field( int, ld_moved) + __field( unsigned int, balance_interval) + ), + + TP_fast_assign( + __entry->cpu = cpu; + __entry->idle = idle; + __entry->balance = balance; + __entry->group_mask = group_mask; + __entry->busiest_nr_running = busiest_nr_running; + __entry->imbalance = imbalance; + __entry->env_flags = env_flags; + __entry->ld_moved = ld_moved; + __entry->balance_interval = balance_interval; + ), + + TP_printk("cpu=%d state=%s balance=%d group=%#lx busy_nr=%d imbalance=%ld flags=%#x ld_moved=%d bal_int=%d", + __entry->cpu, + __entry->idle == CPU_IDLE ? "idle" : + (__entry->idle == CPU_NEWLY_IDLE ? "newly_idle" : "busy"), + __entry->balance, + __entry->group_mask, __entry->busiest_nr_running, + __entry->imbalance, __entry->env_flags, __entry->ld_moved, + __entry->balance_interval) +); + DECLARE_EVENT_CLASS(sched_process_template, TP_PROTO(struct task_struct *p), @@ -374,6 +1101,30 @@ TP_ARGS(tsk, delay)); /* + * Tracepoint for recording the cause of uninterruptible sleep. + */ +TRACE_EVENT(sched_blocked_reason, + + TP_PROTO(struct task_struct *tsk), + + TP_ARGS(tsk), + + TP_STRUCT__entry( + __field( pid_t, pid ) + __field( void*, caller ) + __field( bool, io_wait ) + ), + + TP_fast_assign( + __entry->pid = tsk->pid; + __entry->caller = (void*)get_wchan(tsk); + __entry->io_wait = tsk->in_iowait; + ), + + TP_printk("pid=%d iowait=%d caller=%pS", __entry->pid, __entry->io_wait, __entry->caller) +); + +/* * Tracepoint for accounting runtime (time the task is executing * on a CPU). */ @@ -562,6 +1313,698 @@ TP_printk("cpu=%d", __entry->cpu) ); + +TRACE_EVENT(sched_get_nr_running_avg, + + TP_PROTO(int avg, int big_avg, int iowait_avg, + unsigned int max_nr, unsigned int big_max_nr), + + TP_ARGS(avg, big_avg, iowait_avg, max_nr, big_max_nr), + + TP_STRUCT__entry( + __field( int, avg ) + __field( int, big_avg ) + __field( int, iowait_avg ) + __field( unsigned int, max_nr ) + __field( unsigned int, big_max_nr ) + ), + + TP_fast_assign( + __entry->avg = avg; + __entry->big_avg = big_avg; + __entry->iowait_avg = iowait_avg; + __entry->max_nr = max_nr; + __entry->big_max_nr = big_max_nr; + ), + + TP_printk("avg=%d big_avg=%d iowait_avg=%d max_nr=%u big_max_nr=%u", + __entry->avg, __entry->big_avg, __entry->iowait_avg, + __entry->max_nr, __entry->big_max_nr) +); + +TRACE_EVENT(core_ctl_eval_need, + + TP_PROTO(unsigned int cpu, unsigned int old_need, + unsigned int new_need, unsigned int updated), + TP_ARGS(cpu, old_need, new_need, updated), + TP_STRUCT__entry( + __field(u32, cpu) + __field(u32, old_need) + __field(u32, new_need) + __field(u32, updated) + ), + TP_fast_assign( + __entry->cpu = cpu; + __entry->old_need = old_need; + __entry->new_need = new_need; + __entry->updated = updated; + ), + TP_printk("cpu=%u, old_need=%u, new_need=%u, updated=%u", __entry->cpu, + __entry->old_need, __entry->new_need, __entry->updated) +); + +TRACE_EVENT(core_ctl_set_busy, + + TP_PROTO(unsigned int cpu, unsigned int busy, + unsigned int old_is_busy, unsigned int is_busy), + TP_ARGS(cpu, busy, old_is_busy, is_busy), + TP_STRUCT__entry( + __field(u32, cpu) + __field(u32, busy) + __field(u32, old_is_busy) + __field(u32, is_busy) + ), + TP_fast_assign( + __entry->cpu = cpu; + __entry->busy = busy; + __entry->old_is_busy = old_is_busy; + __entry->is_busy = is_busy; + ), + TP_printk("cpu=%u, busy=%u, old_is_busy=%u, new_is_busy=%u", + __entry->cpu, __entry->busy, __entry->old_is_busy, + __entry->is_busy) +); + +TRACE_EVENT(core_ctl_set_boost, + + TP_PROTO(u32 refcount, s32 ret), + TP_ARGS(refcount, ret), + TP_STRUCT__entry( + __field(u32, refcount) + __field(s32, ret) + ), + TP_fast_assign( + __entry->refcount = refcount; + __entry->ret = ret; + ), + TP_printk("refcount=%u, ret=%d", __entry->refcount, __entry->ret) +); + +/** + * sched_isolate - called when cores are isolated/unisolated + * + * @acutal_mask: mask of cores actually isolated/unisolated + * @req_mask: mask of cores requested isolated/unisolated + * @online_mask: cpu online mask + * @time: amount of time in us it took to isolate/unisolate + * @isolate: 1 if isolating, 0 if unisolating + * + */ +TRACE_EVENT(sched_isolate, + + TP_PROTO(unsigned int requested_cpu, unsigned int isolated_cpus, + u64 start_time, unsigned char isolate), + + TP_ARGS(requested_cpu, isolated_cpus, start_time, isolate), + + TP_STRUCT__entry( + __field(u32, requested_cpu) + __field(u32, isolated_cpus) + __field(u32, time) + __field(unsigned char, isolate) + ), + + TP_fast_assign( + __entry->requested_cpu = requested_cpu; + __entry->isolated_cpus = isolated_cpus; + __entry->time = div64_u64(sched_clock() - start_time, 1000); + __entry->isolate = isolate; + ), + + TP_printk("iso cpu=%u cpus=0x%x time=%u us isolated=%d", + __entry->requested_cpu, __entry->isolated_cpus, + __entry->time, __entry->isolate) +); + +TRACE_EVENT(sched_contrib_scale_f, + + TP_PROTO(int cpu, unsigned long freq_scale_factor, + unsigned long cpu_scale_factor), + + TP_ARGS(cpu, freq_scale_factor, cpu_scale_factor), + + TP_STRUCT__entry( + __field(int, cpu) + __field(unsigned long, freq_scale_factor) + __field(unsigned long, cpu_scale_factor) + ), + + TP_fast_assign( + __entry->cpu = cpu; + __entry->freq_scale_factor = freq_scale_factor; + __entry->cpu_scale_factor = cpu_scale_factor; + ), + + TP_printk("cpu=%d freq_scale_factor=%lu cpu_scale_factor=%lu", + __entry->cpu, __entry->freq_scale_factor, + __entry->cpu_scale_factor) +); + +#ifdef CONFIG_SMP + +#ifdef CONFIG_SCHED_WALT +extern unsigned int sysctl_sched_use_walt_cpu_util; +extern unsigned int sysctl_sched_use_walt_task_util; +extern unsigned int walt_ravg_window; +extern bool walt_disabled; +#endif + +/* + * Tracepoint for accounting sched averages for tasks. + */ +TRACE_EVENT(sched_load_avg_task, + + TP_PROTO(struct task_struct *tsk, struct sched_avg *avg, void *_ravg), + + TP_ARGS(tsk, avg, _ravg), + + TP_STRUCT__entry( + __array( char, comm, TASK_COMM_LEN ) + __field( pid_t, pid ) + __field( int, cpu ) + __field( unsigned long, load_avg ) + __field( unsigned long, util_avg ) + __field( unsigned long, util_avg_pelt ) + __field( unsigned long, util_avg_walt ) + __field( u64, load_sum ) + __field( u32, util_sum ) + __field( u32, period_contrib ) + ), + + TP_fast_assign( + memcpy(__entry->comm, tsk->comm, TASK_COMM_LEN); + __entry->pid = tsk->pid; + __entry->cpu = task_cpu(tsk); + __entry->load_avg = avg->load_avg; + __entry->util_avg = avg->util_avg; + __entry->load_sum = avg->load_sum; + __entry->util_sum = avg->util_sum; + __entry->period_contrib = avg->period_contrib; + __entry->util_avg_pelt = avg->util_avg; + __entry->util_avg_walt = 0; +#ifdef CONFIG_SCHED_WALT + __entry->util_avg_walt = (((unsigned long)((struct ravg*)_ravg)->demand) << SCHED_LOAD_SHIFT); + do_div(__entry->util_avg_walt, walt_ravg_window); + if (!walt_disabled && sysctl_sched_use_walt_task_util) + __entry->util_avg = __entry->util_avg_walt; +#endif + ), + TP_printk("comm=%s pid=%d cpu=%d load_avg=%lu util_avg=%lu " + "util_avg_pelt=%lu util_avg_walt=%lu load_sum=%llu" + " util_sum=%u period_contrib=%u", + __entry->comm, + __entry->pid, + __entry->cpu, + __entry->load_avg, + __entry->util_avg, + __entry->util_avg_pelt, + __entry->util_avg_walt, + (u64)__entry->load_sum, + (u32)__entry->util_sum, + (u32)__entry->period_contrib) +); + +/* + * Tracepoint for accounting sched averages for cpus. + */ +TRACE_EVENT(sched_load_avg_cpu, + + TP_PROTO(int cpu, struct cfs_rq *cfs_rq), + + TP_ARGS(cpu, cfs_rq), + + TP_STRUCT__entry( + __field( int, cpu ) + __field( unsigned long, load_avg ) + __field( unsigned long, util_avg ) + __field( unsigned long, util_avg_pelt ) + __field( unsigned long, util_avg_walt ) + ), + + TP_fast_assign( + __entry->cpu = cpu; + __entry->load_avg = cfs_rq->avg.load_avg; + __entry->util_avg = cfs_rq->avg.util_avg; + __entry->util_avg_pelt = cfs_rq->avg.util_avg; + __entry->util_avg_walt = 0; +#ifdef CONFIG_SCHED_WALT + __entry->util_avg_walt = + div64_u64(cpu_rq(cpu)->cumulative_runnable_avg, + walt_ravg_window >> SCHED_LOAD_SHIFT); + if (!walt_disabled && sysctl_sched_use_walt_cpu_util) + __entry->util_avg = __entry->util_avg_walt; +#endif + ), + + TP_printk("cpu=%d load_avg=%lu util_avg=%lu " + "util_avg_pelt=%lu util_avg_walt=%lu", + __entry->cpu, __entry->load_avg, __entry->util_avg, + __entry->util_avg_pelt, __entry->util_avg_walt) +); + +/* + * Tracepoint for sched_tune_config settings + */ +TRACE_EVENT(sched_tune_config, + + TP_PROTO(int boost), + + TP_ARGS(boost), + + TP_STRUCT__entry( + __field( int, boost ) + ), + + TP_fast_assign( + __entry->boost = boost; + ), + + TP_printk("boost=%d ", __entry->boost) +); + +/* + * Tracepoint for accounting CPU boosted utilization + */ +TRACE_EVENT(sched_boost_cpu, + + TP_PROTO(int cpu, unsigned long util, long margin), + + TP_ARGS(cpu, util, margin), + + TP_STRUCT__entry( + __field( int, cpu ) + __field( unsigned long, util ) + __field(long, margin ) + ), + + TP_fast_assign( + __entry->cpu = cpu; + __entry->util = util; + __entry->margin = margin; + ), + + TP_printk("cpu=%d util=%lu margin=%ld", + __entry->cpu, + __entry->util, + __entry->margin) +); + +/* + * Tracepoint for schedtune_tasks_update + */ +TRACE_EVENT(sched_tune_tasks_update, + + TP_PROTO(struct task_struct *tsk, int cpu, int tasks, int idx, + int boost, int max_boost), + + TP_ARGS(tsk, cpu, tasks, idx, boost, max_boost), + + TP_STRUCT__entry( + __array( char, comm, TASK_COMM_LEN ) + __field( pid_t, pid ) + __field( int, cpu ) + __field( int, tasks ) + __field( int, idx ) + __field( int, boost ) + __field( int, max_boost ) + ), + + TP_fast_assign( + memcpy(__entry->comm, tsk->comm, TASK_COMM_LEN); + __entry->pid = tsk->pid; + __entry->cpu = cpu; + __entry->tasks = tasks; + __entry->idx = idx; + __entry->boost = boost; + __entry->max_boost = max_boost; + ), + + TP_printk("pid=%d comm=%s " + "cpu=%d tasks=%d idx=%d boost=%d max_boost=%d", + __entry->pid, __entry->comm, + __entry->cpu, __entry->tasks, __entry->idx, + __entry->boost, __entry->max_boost) +); + +/* + * Tracepoint for schedtune_boostgroup_update + */ +TRACE_EVENT(sched_tune_boostgroup_update, + + TP_PROTO(int cpu, int variation, int max_boost), + + TP_ARGS(cpu, variation, max_boost), + + TP_STRUCT__entry( + __field( int, cpu ) + __field( int, variation ) + __field( int, max_boost ) + ), + + TP_fast_assign( + __entry->cpu = cpu; + __entry->variation = variation; + __entry->max_boost = max_boost; + ), + + TP_printk("cpu=%d variation=%d max_boost=%d", + __entry->cpu, __entry->variation, __entry->max_boost) +); + +/* + * Tracepoint for accounting task boosted utilization + */ +TRACE_EVENT(sched_boost_task, + + TP_PROTO(struct task_struct *tsk, unsigned long util, long margin), + + TP_ARGS(tsk, util, margin), + + TP_STRUCT__entry( + __array( char, comm, TASK_COMM_LEN ) + __field( pid_t, pid ) + __field( unsigned long, util ) + __field( long, margin ) + + ), + + TP_fast_assign( + memcpy(__entry->comm, tsk->comm, TASK_COMM_LEN); + __entry->pid = tsk->pid; + __entry->util = util; + __entry->margin = margin; + ), + + TP_printk("comm=%s pid=%d util=%lu margin=%ld", + __entry->comm, __entry->pid, + __entry->util, + __entry->margin) +); + +/* + * Tracepoint for find_best_target + */ +TRACE_EVENT(sched_find_best_target, + + TP_PROTO(struct task_struct *tsk, bool prefer_idle, + unsigned long min_util, int start_cpu, + int best_idle, int best_active, int target), + + TP_ARGS(tsk, prefer_idle, min_util, start_cpu, + best_idle, best_active, target), + + TP_STRUCT__entry( + __array( char, comm, TASK_COMM_LEN ) + __field( pid_t, pid ) + __field( unsigned long, min_util ) + __field( bool, prefer_idle ) + __field( int, start_cpu ) + __field( int, best_idle ) + __field( int, best_active ) + __field( int, target ) + ), + + TP_fast_assign( + memcpy(__entry->comm, tsk->comm, TASK_COMM_LEN); + __entry->pid = tsk->pid; + __entry->min_util = min_util; + __entry->prefer_idle = prefer_idle; + __entry->start_cpu = start_cpu; + __entry->best_idle = best_idle; + __entry->best_active = best_active; + __entry->target = target; + ), + + TP_printk("pid=%d comm=%s prefer_idle=%d start_cpu=%d " + "best_idle=%d best_active=%d target=%d", + __entry->pid, __entry->comm, + __entry->prefer_idle, __entry->start_cpu, + __entry->best_idle, __entry->best_active, + __entry->target) +); + +/* + * Tracepoint for accounting sched group energy + */ +TRACE_EVENT(sched_energy_diff, + + TP_PROTO(struct task_struct *tsk, int scpu, int dcpu, int udelta, + int nrgb, int nrga, int nrgd, int capb, int capa, int capd, + int nrgn, int nrgp), + + TP_ARGS(tsk, scpu, dcpu, udelta, + nrgb, nrga, nrgd, capb, capa, capd, + nrgn, nrgp), + + TP_STRUCT__entry( + __array( char, comm, TASK_COMM_LEN ) + __field( pid_t, pid ) + __field( int, scpu ) + __field( int, dcpu ) + __field( int, udelta ) + __field( int, nrgb ) + __field( int, nrga ) + __field( int, nrgd ) + __field( int, capb ) + __field( int, capa ) + __field( int, capd ) + __field( int, nrgn ) + __field( int, nrgp ) + ), + + TP_fast_assign( + memcpy(__entry->comm, tsk->comm, TASK_COMM_LEN); + __entry->pid = tsk->pid; + __entry->scpu = scpu; + __entry->dcpu = dcpu; + __entry->udelta = udelta; + __entry->nrgb = nrgb; + __entry->nrga = nrga; + __entry->nrgd = nrgd; + __entry->capb = capb; + __entry->capa = capa; + __entry->capd = capd; + __entry->nrgn = nrgn; + __entry->nrgp = nrgp; + ), + + TP_printk("pid=%d comm=%s " + "src_cpu=%d dst_cpu=%d usage_delta=%d " + "nrg_before=%d nrg_after=%d nrg_diff=%d " + "cap_before=%d cap_after=%d cap_delta=%d " + "nrg_delta=%d nrg_payoff=%d", + __entry->pid, __entry->comm, + __entry->scpu, __entry->dcpu, __entry->udelta, + __entry->nrgb, __entry->nrga, __entry->nrgd, + __entry->capb, __entry->capa, __entry->capd, + __entry->nrgn, __entry->nrgp) +); + +/* + * Tracepoint for schedtune_tasks_update + */ +TRACE_EVENT(sched_tune_filter, + + TP_PROTO(int nrg_delta, int cap_delta, + int nrg_gain, int cap_gain, + int payoff, int region), + + TP_ARGS(nrg_delta, cap_delta, nrg_gain, cap_gain, payoff, region), + + TP_STRUCT__entry( + __field( int, nrg_delta ) + __field( int, cap_delta ) + __field( int, nrg_gain ) + __field( int, cap_gain ) + __field( int, payoff ) + __field( int, region ) + ), + + TP_fast_assign( + __entry->nrg_delta = nrg_delta; + __entry->cap_delta = cap_delta; + __entry->nrg_gain = nrg_gain; + __entry->cap_gain = cap_gain; + __entry->payoff = payoff; + __entry->region = region; + ), + + TP_printk("nrg_delta=%d cap_delta=%d nrg_gain=%d cap_gain=%d payoff=%d region=%d", + __entry->nrg_delta, __entry->cap_delta, + __entry->nrg_gain, __entry->cap_gain, + __entry->payoff, __entry->region) +); + +/* + * Tracepoint for system overutilized flag + */ +TRACE_EVENT(sched_overutilized, + + TP_PROTO(bool overutilized), + + TP_ARGS(overutilized), + + TP_STRUCT__entry( + __field( bool, overutilized ) + ), + + TP_fast_assign( + __entry->overutilized = overutilized; + ), + + TP_printk("overutilized=%d", + __entry->overutilized ? 1 : 0) +); +#ifdef CONFIG_SCHED_WALT +struct rq; + +TRACE_EVENT(walt_update_task_ravg, + + TP_PROTO(struct task_struct *p, struct rq *rq, int evt, + u64 wallclock, u64 irqtime), + + TP_ARGS(p, rq, evt, wallclock, irqtime), + + TP_STRUCT__entry( + __array( char, comm, TASK_COMM_LEN ) + __field( pid_t, pid ) + __field( pid_t, cur_pid ) + __field( u64, wallclock ) + __field( u64, mark_start ) + __field( u64, delta_m ) + __field( u64, win_start ) + __field( u64, delta ) + __field( u64, irqtime ) + __field( int, evt ) + __field(unsigned int, demand ) + __field(unsigned int, sum ) + __field( int, cpu ) + __field( u64, cs ) + __field( u64, ps ) + __field(unsigned long, util ) + __field( u32, curr_window ) + __field( u32, prev_window ) + __field( u64, nt_cs ) + __field( u64, nt_ps ) + __field( u32, active_windows ) + ), + + TP_fast_assign( + __entry->wallclock = wallclock; + __entry->win_start = rq->window_start; + __entry->delta = (wallclock - rq->window_start); + __entry->evt = evt; + __entry->cpu = rq->cpu; + __entry->cur_pid = rq->curr->pid; + memcpy(__entry->comm, p->comm, TASK_COMM_LEN); + __entry->pid = p->pid; + __entry->mark_start = p->ravg.mark_start; + __entry->delta_m = (wallclock - p->ravg.mark_start); + __entry->demand = p->ravg.demand; + __entry->sum = p->ravg.sum; + __entry->irqtime = irqtime; + __entry->cs = rq->curr_runnable_sum; + __entry->ps = rq->prev_runnable_sum; + __entry->util = rq->prev_runnable_sum << SCHED_LOAD_SHIFT; + do_div(__entry->util, walt_ravg_window); + __entry->curr_window = p->ravg.curr_window; + __entry->prev_window = p->ravg.prev_window; + __entry->nt_cs = rq->nt_curr_runnable_sum; + __entry->nt_ps = rq->nt_prev_runnable_sum; + __entry->active_windows = p->ravg.active_windows; + ), + + TP_printk("wc %llu ws %llu delta %llu event %d cpu %d cur_pid %d task %d (%s) ms %llu delta %llu demand %u sum %u irqtime %llu" + " cs %llu ps %llu util %lu cur_window %u prev_window %u active_wins %u" + , __entry->wallclock, __entry->win_start, __entry->delta, + __entry->evt, __entry->cpu, __entry->cur_pid, + __entry->pid, __entry->comm, __entry->mark_start, + __entry->delta_m, __entry->demand, + __entry->sum, __entry->irqtime, + __entry->cs, __entry->ps, __entry->util, + __entry->curr_window, __entry->prev_window, + __entry->active_windows + ) +); + +TRACE_EVENT(walt_update_history, + + TP_PROTO(struct rq *rq, struct task_struct *p, u32 runtime, int samples, + int evt), + + TP_ARGS(rq, p, runtime, samples, evt), + + TP_STRUCT__entry( + __array( char, comm, TASK_COMM_LEN ) + __field( pid_t, pid ) + __field(unsigned int, runtime ) + __field( int, samples ) + __field( int, evt ) + __field( u64, demand ) + __field( u64, walt_avg ) + __field(unsigned int, pelt_avg ) + __array( u32, hist, RAVG_HIST_SIZE_MAX) + __field( int, cpu ) + ), + + TP_fast_assign( + memcpy(__entry->comm, p->comm, TASK_COMM_LEN); + __entry->pid = p->pid; + __entry->runtime = runtime; + __entry->samples = samples; + __entry->evt = evt; + __entry->demand = p->ravg.demand; + __entry->walt_avg = (__entry->demand << 10) / walt_ravg_window, + __entry->pelt_avg = p->se.avg.util_avg; + memcpy(__entry->hist, p->ravg.sum_history, + RAVG_HIST_SIZE_MAX * sizeof(u32)); + __entry->cpu = rq->cpu; + ), + + TP_printk("%d (%s): runtime %u samples %d event %d demand %llu" + " walt %llu pelt %u (hist: %u %u %u %u %u) cpu %d", + __entry->pid, __entry->comm, + __entry->runtime, __entry->samples, __entry->evt, + __entry->demand, + __entry->walt_avg, + __entry->pelt_avg, + __entry->hist[0], __entry->hist[1], + __entry->hist[2], __entry->hist[3], + __entry->hist[4], __entry->cpu) +); + +TRACE_EVENT(walt_migration_update_sum, + + TP_PROTO(struct rq *rq, struct task_struct *p), + + TP_ARGS(rq, p), + + TP_STRUCT__entry( + __field(int, cpu ) + __field(int, pid ) + __field( u64, cs ) + __field( u64, ps ) + __field( s64, nt_cs ) + __field( s64, nt_ps ) + ), + + TP_fast_assign( + __entry->cpu = cpu_of(rq); + __entry->cs = rq->curr_runnable_sum; + __entry->ps = rq->prev_runnable_sum; + __entry->nt_cs = (s64)rq->nt_curr_runnable_sum; + __entry->nt_ps = (s64)rq->nt_prev_runnable_sum; + __entry->pid = p->pid; + ), + + TP_printk("cpu %d: cs %llu ps %llu nt_cs %lld nt_ps %lld pid %d", + __entry->cpu, __entry->cs, __entry->ps, + __entry->nt_cs, __entry->nt_ps, __entry->pid) +); +#endif /* CONFIG_SCHED_WALT */ + +#endif /* CONFIG_SMP */ + #endif /* _TRACE_SCHED_H */ /* This part must be outside protection */ diff -ruw linux-4.4.115/include/trace/events/skb.h linux-4.4.115-fbx/include/trace/events/skb.h --- linux-4.4.115/include/trace/events/skb.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/trace/events/skb.h 2019-01-22 16:16:28.523291866 +0100 @@ -50,6 +50,33 @@ TP_printk("skbaddr=%p", __entry->skbaddr) ); +TRACE_EVENT(print_skb_gso, + + TP_PROTO(struct sk_buff *skb, __be16 src, __be16 dest), + + TP_ARGS(skb, src, dest), + + TP_STRUCT__entry( + __field(void *, skbaddr) + __field(int , len) + __field(int , data_len) + __field(__be16, src) + __field(__be16, dest) + ), + + TP_fast_assign( + __entry->skbaddr = skb; + __entry->len = skb->len; + __entry->data_len = skb->data_len; + __entry->src = src; + __entry->dest = dest; + ), + + TP_printk("GSO: skbaddr=%pK, len=%d, data_len=%d, src=%u, dest=%u", + __entry->skbaddr, __entry->len, __entry->data_len, + be16_to_cpu(__entry->src), be16_to_cpu(__entry->dest)) +); + TRACE_EVENT(skb_copy_datagram_iovec, TP_PROTO(const struct sk_buff *skb, int len), diff -ruw linux-4.4.115/include/trace/trace_events.h linux-4.4.115-fbx/include/trace/trace_events.h --- linux-4.4.115/include/trace/trace_events.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/trace/trace_events.h 2019-01-22 16:16:28.527291902 +0100 @@ -682,7 +682,8 @@ \ { assign; } \ \ - trace_event_buffer_commit(&fbuffer); \ + trace_event_buffer_commit(&fbuffer, \ + sizeof(*entry) + __data_size); \ } /* * The ftrace_test_probe is compiled out, it is only here as a build time check diff -ruw linux-4.4.115/include/uapi/asm-generic/ioctls.h linux-4.4.115-fbx/include/uapi/asm-generic/ioctls.h --- linux-4.4.115/include/uapi/asm-generic/ioctls.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/uapi/asm-generic/ioctls.h 2019-01-22 16:16:28.527291902 +0100 @@ -77,6 +77,9 @@ #define TIOCGPKT _IOR('T', 0x38, int) /* Get packet mode state */ #define TIOCGPTLCK _IOR('T', 0x39, int) /* Get Pty lock state */ #define TIOCGEXCL _IOR('T', 0x40, int) /* Get exclusive mode state */ +#define TIOCPMGET 0x5441 /* PM get */ +#define TIOCPMPUT 0x5442 /* PM put */ +#define TIOCPMACT 0x5443 /* PM is active */ #define FIONCLEX 0x5450 #define FIOCLEX 0x5451 diff -ruw linux-4.4.115/include/uapi/drm/drm_fourcc.h linux-4.4.115-fbx/include/uapi/drm/drm_fourcc.h --- linux-4.4.115/include/uapi/drm/drm_fourcc.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/uapi/drm/drm_fourcc.h 2019-01-22 16:16:28.531291938 +0100 @@ -26,6 +26,10 @@ #include +#if defined(__cplusplus) +extern "C" { +#endif + #define fourcc_code(a, b, c, d) ((__u32)(a) | ((__u32)(b) << 8) | \ ((__u32)(c) << 16) | ((__u32)(d) << 24)) @@ -230,4 +234,39 @@ */ #define DRM_FORMAT_MOD_SAMSUNG_64_32_TILE fourcc_mod_code(SAMSUNG, 1) +/* + * Qualcomm Compressed Format + * + * Refers to a compressed variant of the base format that is compressed. + * Implementation may be platform and base-format specific. + */ +#define DRM_FORMAT_MOD_QCOM_COMPRESSED fourcc_mod_code(QCOM, 1) + +/* + * QTI DX Format + * + * Refers to a DX variant of the base format. + * Implementation may be platform and base-format specific. + */ +#define DRM_FORMAT_MOD_QCOM_DX fourcc_mod_code(QCOM, 0x2) + +/* + * QTI Tight Format + * + * Refers to a tightly packed variant of the base format. + * Implementation may be platform and base-format specific. + */ +#define DRM_FORMAT_MOD_QCOM_TIGHT fourcc_mod_code(QCOM, 0x4) + +/* + * QTI Tile Format + * + * Refers to a tile variant of the base format. + * Implementation may be platform and base-format specific. + */ +#define DRM_FORMAT_MOD_QCOM_TILE fourcc_mod_code(QCOM, 0x8) + +#if defined(__cplusplus) +} +#endif #endif /* DRM_FOURCC_H */ diff -ruw linux-4.4.115/include/uapi/drm/drm.h linux-4.4.115-fbx/include/uapi/drm/drm.h --- linux-4.4.115/include/uapi/drm/drm.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/uapi/drm/drm.h 2019-01-22 16:16:28.531291938 +0100 @@ -58,6 +58,10 @@ #endif +#if defined(__cplusplus) +extern "C" { +#endif + #define DRM_NAME "drm" /**< Name in kernel, /dev, and /proc */ #define DRM_MIN_ORDER 5 /**< At least 2^5 bytes = 32 bytes */ #define DRM_MAX_ORDER 22 /**< Up to 2^22 bytes = 4MB */ @@ -372,7 +376,11 @@ */ struct drm_buf_map { int count; /**< Length of the buffer list */ +#ifdef __cplusplus + void __user *virt; +#else void __user *virtual; /**< Mmap'd area in user-virtual */ +#endif struct drm_buf_pub __user *list; /**< Buffer information */ }; @@ -631,6 +639,7 @@ #define DRM_CAP_CURSOR_WIDTH 0x8 #define DRM_CAP_CURSOR_HEIGHT 0x9 #define DRM_CAP_ADDFB2_MODIFIERS 0x10 +#define DRM_CAP_CRTC_IN_VBLANK_EVENT 0x12 /** DRM_IOCTL_GET_CAP ioctl argument type */ struct drm_get_cap { @@ -679,7 +688,15 @@ __s32 fd; }; -#include +#if defined(__cplusplus) +} +#endif + +#include "drm_mode.h" + +#if defined(__cplusplus) +extern "C" { +#endif #define DRM_IOCTL_BASE 'd' #define DRM_IO(nr) _IO(DRM_IOCTL_BASE,nr) @@ -826,7 +843,7 @@ __u32 tv_sec; __u32 tv_usec; __u32 sequence; - __u32 reserved; + __u32 crtc_id; /* 0 on older kernels that do not support this */ }; /* typedef area */ @@ -874,4 +891,8 @@ typedef struct drm_set_version drm_set_version_t; #endif +#if defined(__cplusplus) +} +#endif + #endif diff -ruw linux-4.4.115/include/uapi/drm/drm_mode.h linux-4.4.115-fbx/include/uapi/drm/drm_mode.h --- linux-4.4.115/include/uapi/drm/drm_mode.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/uapi/drm/drm_mode.h 2019-10-29 09:26:25.537221713 +0100 @@ -29,6 +29,10 @@ #include +#if defined(__cplusplus) +extern "C" { +#endif + #define DRM_DISPLAY_INFO_LEN 32 #define DRM_CONNECTOR_NAME_LEN 32 #define DRM_DISPLAY_MODE_LEN 32 @@ -72,7 +76,9 @@ #define DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH (6<<14) #define DRM_MODE_FLAG_3D_TOP_AND_BOTTOM (7<<14) #define DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF (8<<14) - +#define DRM_MODE_FLAG_SEAMLESS (1<<19) +#define DRM_MODE_FLAG_SUPPORTS_RGB (1<<20) +#define DRM_MODE_FLAG_SUPPORTS_YUV (1<<21) /* DPMS flags */ /* bit compatible with the xorg definitions. */ @@ -354,6 +360,7 @@ #define DRM_MODE_FB_INTERLACED (1<<0) /* for interlaced framebuffers */ #define DRM_MODE_FB_MODIFIERS (1<<1) /* enables ->modifer[] */ +#define DRM_MODE_FB_SECURE (1<<2) /* for secure framebuffers */ struct drm_mode_fb_cmd2 { __u32 fb_id; @@ -596,4 +603,8 @@ __u32 blob_id; }; +#if defined(__cplusplus) +} +#endif + #endif diff -ruw linux-4.4.115/include/uapi/drm/drm_sarea.h linux-4.4.115-fbx/include/uapi/drm/drm_sarea.h --- linux-4.4.115/include/uapi/drm/drm_sarea.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/uapi/drm/drm_sarea.h 2019-01-22 16:16:28.531291938 +0100 @@ -34,6 +34,10 @@ #include +#if defined(__cplusplus) +extern "C" { +#endif + /* SAREA area needs to be at least a page */ #if defined(__alpha__) #define SAREA_MAX 0x2000U @@ -83,4 +87,8 @@ typedef struct drm_sarea drm_sarea_t; #endif +#if defined(__cplusplus) +} +#endif + #endif /* _DRM_SAREA_H_ */ diff -ruw linux-4.4.115/include/uapi/drm/Kbuild linux-4.4.115-fbx/include/uapi/drm/Kbuild --- linux-4.4.115/include/uapi/drm/Kbuild 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/uapi/drm/Kbuild 2019-01-22 16:16:28.527291902 +0100 @@ -18,3 +18,5 @@ header-y += vmwgfx_drm.h header-y += msm_drm.h header-y += virtgpu_drm.h +header-y += sde_drm.h +header-y += msm_drm_pp.h diff -ruw linux-4.4.115/include/uapi/drm/msm_drm.h linux-4.4.115-fbx/include/uapi/drm/msm_drm.h --- linux-4.4.115/include/uapi/drm/msm_drm.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/uapi/drm/msm_drm.h 2019-01-22 16:16:28.531291938 +0100 @@ -20,6 +20,11 @@ #include #include +#include + +#if defined(__cplusplus) +extern "C" { +#endif /* Please note that modifications to all structs defined here are * subject to backwards-compatibility constraints: @@ -39,6 +44,15 @@ #define MSM_PIPE_2D1 0x02 #define MSM_PIPE_3D0 0x10 +/* The pipe-id just uses the lower bits, so can be OR'd with flags in + * the upper 16 bits (which could be extended further, if needed, maybe + * we extend/overload the pipe-id some day to deal with multiple rings, + * but even then I don't think we need the full lower 16 bits). + */ +#define MSM_PIPE_ID_MASK 0xffff +#define MSM_PIPE_ID(x) ((x) & MSM_PIPE_ID_MASK) +#define MSM_PIPE_FLAGS(x) ((x) & ~MSM_PIPE_ID_MASK) + /* timeouts are specified in clock-monotonic absolute times (to simplify * restarting interrupted ioctls). The following struct is logically the * same as 'struct timespec' but 32/64b ABI safe. @@ -48,9 +62,73 @@ __s64 tv_nsec; /* nanoseconds */ }; +/* From CEA.861.3 */ +#define HDR_EOTF_SMTPE_ST2084 0x2 +#define HDR_EOTF_HLG 0x3 + +/* hdr hdmi state takes possible values of 0, 1 and 2 respectively */ +#define DRM_MSM_HDR_DISABLE 0 +#define DRM_MSM_HDR_ENABLE 1 +#define DRM_MSM_HDR_RESET 2 + +/* + * HDR Metadata + * These are defined as per EDID spec and shall be used by the sink + * to set the HDR metadata for playback from userspace. + */ + +#define HDR_PRIMARIES_COUNT 3 + +struct drm_msm_ext_panel_hdr_metadata { + __u32 eotf; /* electro optical transfer function */ + __u32 hdr_supported; /* HDR supported */ + __u32 display_primaries_x[HDR_PRIMARIES_COUNT]; /* Primaries x */ + __u32 display_primaries_y[HDR_PRIMARIES_COUNT]; /* Primaries y */ + __u32 white_point_x; /* white_point_x */ + __u32 white_point_y; /* white_point_y */ + __u32 max_luminance; /* Max luminance */ + __u32 min_luminance; /* Min Luminance */ + __u32 max_content_light_level; /* max content light level */ + __u32 max_average_light_level; /* max average light level */ +}; + +/** + * HDR Control + * This encapsulates the HDR metadata as well as a state control + * for the HDR metadata as required by the HDMI spec to send the + * relevant metadata depending on the state of the HDR playback. + * hdr_state: Controls HDR state, takes values ENABLE(1)/DISABLE(0) + * hdr_meta: Metadata sent by the userspace for the HDR clip + */ + +#define DRM_MSM_EXT_PANEL_HDR_CTRL +struct drm_msm_ext_panel_hdr_ctrl { + __u8 hdr_state; /* HDR state */ + struct drm_msm_ext_panel_hdr_metadata hdr_meta; /* HDR metadata */ +}; + +/** + * HDR sink properties + * These are defined as per EDID spec and shall be used by the userspace + * to determine the HDR properties to be set to the sink. + */ +struct drm_msm_ext_panel_hdr_properties { + __u8 hdr_metadata_type_one; /* static metadata type one */ + __u32 hdr_supported; /* HDR supported */ + __u32 hdr_eotf; /* electro optical transfer function */ + __u32 hdr_max_luminance; /* Max luminance */ + __u32 hdr_avg_luminance; /* Avg luminance */ + __u32 hdr_min_luminance; /* Min Luminance */ +}; + #define MSM_PARAM_GPU_ID 0x01 #define MSM_PARAM_GMEM_SIZE 0x02 #define MSM_PARAM_CHIP_ID 0x03 +#define MSM_PARAM_MAX_FREQ 0x04 +#define MSM_PARAM_TIMESTAMP 0x05 +#define MSM_PARAM_GMEM_BASE 0x06 +#define MSM_PARAM_NR_RINGS 0x07 +#define MSM_PARAM_GPU_HANG_TIMEOUT 0xa0 /* timeout in ms */ struct drm_msm_param { __u32 pipe; /* in, MSM_PIPE_x */ @@ -64,6 +142,8 @@ #define MSM_BO_SCANOUT 0x00000001 /* scanout capable */ #define MSM_BO_GPU_READONLY 0x00000002 +#define MSM_BO_PRIVILEGED 0x00000004 +#define MSM_BO_SECURE 0x00000008 /* Allocate and map as secure */ #define MSM_BO_CACHE_MASK 0x000f0000 /* cache modes */ #define MSM_BO_CACHED 0x00010000 @@ -72,6 +152,7 @@ #define MSM_BO_FLAGS (MSM_BO_SCANOUT | \ MSM_BO_GPU_READONLY | \ + MSM_BO_SECURE | \ MSM_BO_CACHED | \ MSM_BO_WC | \ MSM_BO_UNCACHED) @@ -82,10 +163,21 @@ __u32 handle; /* out */ }; +struct drm_msm_gem_svm_new { + __u64 hostptr; /* in, must be page-aligned */ + __u64 size; /* in, must be page-aligned */ + __u32 flags; /* in, mask of MSM_BO_x */ + __u32 handle; /* out */ +}; + +#define MSM_INFO_IOVA 0x01 + +#define MSM_INFO_FLAGS (MSM_INFO_IOVA) + struct drm_msm_gem_info { __u32 handle; /* in */ - __u32 pad; - __u64 offset; /* out, offset to pass to mmap() */ + __u32 flags; /* in - combination of MSM_INFO_* flags */ + __u64 offset; /* out, mmap() offset or iova */ }; #define MSM_PREP_READ 0x01 @@ -121,7 +213,11 @@ */ struct drm_msm_gem_submit_reloc { __u32 submit_offset; /* in, offset from submit_bo */ +#ifdef __cplusplus + __u32 or_val; +#else __u32 or; /* in, value OR'd with result */ +#endif __s32 shift; /* in, amount of left shift (can be negative) */ __u32 reloc_idx; /* in, index of reloc_bo buffer */ __u64 reloc_offset; /* in, offset from start of reloc_bo */ @@ -134,10 +230,13 @@ * this buffer in the first-level ringbuffer * CTX_RESTORE_BUF - only executed if there has been a GPU context * switch since the last SUBMIT ioctl + * PROFILE_BUF - A profiling buffer written to by both GPU and CPU. */ #define MSM_SUBMIT_CMD_BUF 0x0001 #define MSM_SUBMIT_CMD_IB_TARGET_BUF 0x0002 #define MSM_SUBMIT_CMD_CTX_RESTORE_BUF 0x0003 +#define MSM_SUBMIT_CMD_PROFILE_BUF 0x0004 + struct drm_msm_gem_submit_cmd { __u32 type; /* in, one of MSM_SUBMIT_CMD_x */ __u32 submit_idx; /* in, index of submit_bo cmdstream buffer */ @@ -145,7 +244,7 @@ __u32 size; /* in, cmdstream size */ __u32 pad; __u32 nr_relocs; /* in, number of submit_reloc's */ - __u64 __user relocs; /* in, ptr to array of submit_reloc's */ + __u64 relocs; /* in, ptr to array of submit_reloc's */ }; /* Each buffer referenced elsewhere in the cmdstream submit (ie. the @@ -170,17 +269,39 @@ __u64 presumed; /* in/out, presumed buffer address */ }; +/* Valid submit ioctl flags: */ +#define MSM_SUBMIT_RING_MASK 0x000F0000 +#define MSM_SUBMIT_RING_SHIFT 16 + +#define MSM_SUBMIT_FLAGS (MSM_SUBMIT_RING_MASK) + /* Each cmdstream submit consists of a table of buffers involved, and * one or more cmdstream buffers. This allows for conditional execution * (context-restore), and IB buffers needed for per tile/bin draw cmds. */ struct drm_msm_gem_submit { - __u32 pipe; /* in, MSM_PIPE_x */ + __u32 flags; /* MSM_PIPE_x | MSM_SUBMIT_x */ __u32 fence; /* out */ __u32 nr_bos; /* in, number of submit_bo's */ __u32 nr_cmds; /* in, number of submit_cmd's */ - __u64 __user bos; /* in, ptr to array of submit_bo's */ - __u64 __user cmds; /* in, ptr to array of submit_cmd's */ + __u64 bos; /* in, ptr to array of submit_bo's */ + __u64 cmds; /* in, ptr to array of submit_cmd's */ + __s32 fence_fd; /* gap for the fence_fd which is upstream */ + __u32 queueid; /* in, submitqueue id */ +}; + +/* + * Define a preprocessor variable to let the userspace know that + * drm_msm_gem_submit_profile_buffer switched to only support a kernel timestamp + * for submit time + */ +#define MSM_PROFILE_BUFFER_SUBMIT_TIME 1 + +struct drm_msm_gem_submit_profile_buffer { + struct drm_msm_timespec time; /* out, submission time */ + __u64 ticks_queued; /* out, GPU ticks at ringbuffer submission */ + __u64 ticks_submitted; /* out, GPU ticks before cmdstream execution*/ + __u64 ticks_retired; /* out, GPU ticks after cmdstream execution */ }; /* The normal way to synchronize with the GPU is just to CPU_PREP on @@ -196,6 +317,141 @@ struct drm_msm_timespec timeout; /* in */ }; +/** + * struct drm_msm_event_req - Payload to event enable/disable ioctls. + * @object_id: DRM object id. Ex: for crtc pass crtc id. + * @object_type: DRM object type. Ex: for crtc set it to DRM_MODE_OBJECT_CRTC. + * @event: Event for which notification is being enabled/disabled. + * Ex: for Histogram set - DRM_EVENT_HISTOGRAM. + * @client_context: Opaque pointer that will be returned during event response + * notification. + * @index: Object index(ex: crtc index), optional for user-space to set. + * Driver will override value based on object_id and object_type. + */ +struct drm_msm_event_req { + __u32 object_id; + __u32 object_type; + __u32 event; + __u64 client_context; + __u32 index; +}; + +/** + * struct drm_msm_event_resp - payload returned when read is called for + * custom notifications. + * @base: Event type and length of complete notification payload. + * @info: Contains information about DRM that which raised this event. + * @data: Custom payload that driver returns for event type. + * size of data = base.length - (sizeof(base) + sizeof(info)) + */ +struct drm_msm_event_resp { + struct drm_event base; + struct drm_msm_event_req info; + __u8 data[]; +}; + +#define MSM_COUNTER_GROUP_CP 0 +#define MSM_COUNTER_GROUP_RBBM 1 +#define MSM_COUNTER_GROUP_PC 2 +#define MSM_COUNTER_GROUP_VFD 3 +#define MSM_COUNTER_GROUP_HLSQ 4 +#define MSM_COUNTER_GROUP_VPC 5 +#define MSM_COUNTER_GROUP_TSE 6 +#define MSM_COUNTER_GROUP_RAS 7 +#define MSM_COUNTER_GROUP_UCHE 8 +#define MSM_COUNTER_GROUP_TP 9 +#define MSM_COUNTER_GROUP_SP 10 +#define MSM_COUNTER_GROUP_RB 11 +#define MSM_COUNTER_GROUP_VBIF 12 +#define MSM_COUNTER_GROUP_VBIF_PWR 13 +#define MSM_COUNTER_GROUP_VSC 23 +#define MSM_COUNTER_GROUP_CCU 24 +#define MSM_COUNTER_GROUP_LRZ 25 +#define MSM_COUNTER_GROUP_CMP 26 +#define MSM_COUNTER_GROUP_ALWAYSON 27 +#define MSM_COUNTER_GROUP_SP_PWR 28 +#define MSM_COUNTER_GROUP_TP_PWR 29 +#define MSM_COUNTER_GROUP_RB_PWR 30 +#define MSM_COUNTER_GROUP_CCU_PWR 31 +#define MSM_COUNTER_GROUP_UCHE_PWR 32 +#define MSM_COUNTER_GROUP_CP_PWR 33 +#define MSM_COUNTER_GROUP_GPMU_PWR 34 +#define MSM_COUNTER_GROUP_ALWAYSON_PWR 35 + +/** + * struct drm_msm_counter - allocate or release a GPU performance counter + * @groupid: The group ID of the counter to get/put + * @counterid: For GET returns the counterid that was assigned. For PUT + * release the counter identified by groupid/counterid + * @countable: For GET the countable for the counter + */ +struct drm_msm_counter { + __u32 groupid; + int counterid; + __u32 countable; + __u32 counter_lo; + __u32 counter_hi; +}; + +struct drm_msm_counter_read_op { + __u64 value; + __u32 groupid; + int counterid; +}; + +/** + * struct drm_msm_counter_read - Read a number of GPU performance counters + * ops: Pointer to the list of struct drm_msm_counter_read_op operations + * nr_ops: Number of operations in the list + */ +struct drm_msm_counter_read { + __u64 __user ops; + __u32 nr_ops; +}; + +#define MSM_GEM_SYNC_TO_DEV 0 +#define MSM_GEM_SYNC_TO_CPU 1 + +struct drm_msm_gem_syncop { + __u32 handle; + __u32 op; +}; + +struct drm_msm_gem_sync { + __u32 nr_ops; + __u64 __user ops; +}; + +/* + * Draw queues allow the user to set specific submission parameter. Command + * submissions will specify a specific submit queue id to use. id '0' is + * reserved as a "default" drawqueue with medium priority. The user can safely + * use and query 0 but cannot destroy it. + */ + +/* + * Allows a process to bypass the 2 second quality of service timeout. + * Only CAP_SYS_ADMIN capable processes can set this flag. + */ +#define MSM_SUBMITQUEUE_BYPASS_QOS_TIMEOUT 0x00000001 + +#define MSM_SUBMITQUEUE_FLAGS (MSM_SUBMITQUEUE_BYPASS_QOS_TIMEOUT) + +struct drm_msm_submitqueue { + __u32 flags; /* in, MSM_SUBMITQUEUE_x */ + __u32 prio; /* in, Priority level */ + __u32 id; /* out, identifier */ +}; + +#define MSM_SUBMITQUEUE_PARAM_FAULTS 0 + +struct drm_msm_submitqueue_query { + __u64 data; + __u32 id; + __u32 param; + __u32 len; +}; + #define DRM_MSM_GET_PARAM 0x00 /* placeholder: #define DRM_MSM_SET_PARAM 0x01 @@ -206,7 +462,27 @@ #define DRM_MSM_GEM_CPU_FINI 0x05 #define DRM_MSM_GEM_SUBMIT 0x06 #define DRM_MSM_WAIT_FENCE 0x07 -#define DRM_MSM_NUM_IOCTLS 0x08 +/* Gap for upstream DRM_MSM_GEM_MADVISE */ +#define DRM_MSM_GEM_SVM_NEW 0x09 +#define DRM_MSM_SUBMITQUEUE_NEW 0x0A +#define DRM_MSM_SUBMITQUEUE_CLOSE 0x0B +#define DRM_MSM_SUBMITQUEUE_QUERY 0x0C + +#define DRM_SDE_WB_CONFIG 0x40 +#define DRM_MSM_REGISTER_EVENT 0x41 +#define DRM_MSM_DEREGISTER_EVENT 0x42 +#define DRM_MSM_COUNTER_GET 0x43 +#define DRM_MSM_COUNTER_PUT 0x44 +#define DRM_MSM_COUNTER_READ 0x45 +#define DRM_MSM_GEM_SYNC 0x46 + +/** + * Currently DRM framework supports only VSYNC event. + * Starting the custom events at 0xff to provide space for DRM + * framework to add new events. + */ +#define DRM_EVENT_HISTOGRAM 0xff +#define DRM_EVENT_AD 0x100 #define DRM_IOCTL_MSM_GET_PARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GET_PARAM, struct drm_msm_param) #define DRM_IOCTL_MSM_GEM_NEW DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_NEW, struct drm_msm_gem_new) @@ -215,5 +491,36 @@ #define DRM_IOCTL_MSM_GEM_CPU_FINI DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_GEM_CPU_FINI, struct drm_msm_gem_cpu_fini) #define DRM_IOCTL_MSM_GEM_SUBMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_SUBMIT, struct drm_msm_gem_submit) #define DRM_IOCTL_MSM_WAIT_FENCE DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_WAIT_FENCE, struct drm_msm_wait_fence) +#define DRM_IOCTL_SDE_WB_CONFIG \ + DRM_IOW((DRM_COMMAND_BASE + DRM_SDE_WB_CONFIG), struct sde_drm_wb_cfg) +#define DRM_IOCTL_MSM_REGISTER_EVENT DRM_IOW((DRM_COMMAND_BASE + \ + DRM_MSM_REGISTER_EVENT), struct drm_msm_event_req) +#define DRM_IOCTL_MSM_DEREGISTER_EVENT DRM_IOW((DRM_COMMAND_BASE + \ + DRM_MSM_DEREGISTER_EVENT), struct drm_msm_event_req) +#define DRM_IOCTL_MSM_COUNTER_GET \ + DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_COUNTER_GET, struct drm_msm_counter) +#define DRM_IOCTL_MSM_COUNTER_PUT \ + DRM_IOW(DRM_COMMAND_BASE + DRM_MSM_COUNTER_PUT, struct drm_msm_counter) +#define DRM_IOCTL_MSM_COUNTER_READ \ + DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_COUNTER_READ, \ + struct drm_msm_counter_read) +#define DRM_IOCTL_MSM_GEM_SYNC DRM_IOW(DRM_COMMAND_BASE + DRM_MSM_GEM_SYNC,\ + struct drm_msm_gem_sync) +#define DRM_IOCTL_MSM_GEM_SVM_NEW \ + DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_SVM_NEW, \ + struct drm_msm_gem_svm_new) +#define DRM_IOCTL_MSM_SUBMITQUEUE_NEW \ + DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_SUBMITQUEUE_NEW, \ + struct drm_msm_submitqueue) +#define DRM_IOCTL_MSM_SUBMITQUEUE_CLOSE \ + DRM_IOW(DRM_COMMAND_BASE + DRM_MSM_SUBMITQUEUE_CLOSE, \ + struct drm_msm_submitqueue) +#define DRM_IOCTL_MSM_SUBMITQUEUE_QUERY \ + DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_SUBMITQUEUE_QUERY, \ + struct drm_msm_submitqueue_query) + +#if defined(__cplusplus) +} +#endif #endif /* __MSM_DRM_H__ */ diff -ruw linux-4.4.115/include/uapi/Kbuild linux-4.4.115-fbx/include/uapi/Kbuild --- linux-4.4.115/include/uapi/Kbuild 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/uapi/Kbuild 2019-01-22 16:16:28.527291902 +0100 @@ -13,3 +13,4 @@ header-y += xen/ header-y += scsi/ header-y += misc/ +header-y += media/ diff -ruw linux-4.4.115/include/uapi/linux/android/binder.h linux-4.4.115-fbx/include/uapi/linux/android/binder.h --- linux-4.4.115/include/uapi/linux/android/binder.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/uapi/linux/android/binder.h 2019-10-29 09:26:25.541221752 +0100 @@ -33,11 +33,60 @@ BINDER_TYPE_HANDLE = B_PACK_CHARS('s', 'h', '*', B_TYPE_LARGE), BINDER_TYPE_WEAK_HANDLE = B_PACK_CHARS('w', 'h', '*', B_TYPE_LARGE), BINDER_TYPE_FD = B_PACK_CHARS('f', 'd', '*', B_TYPE_LARGE), + BINDER_TYPE_FDA = B_PACK_CHARS('f', 'd', 'a', B_TYPE_LARGE), + BINDER_TYPE_PTR = B_PACK_CHARS('p', 't', '*', B_TYPE_LARGE), }; -enum { +/** + * enum flat_binder_object_shifts: shift values for flat_binder_object_flags + * @FLAT_BINDER_FLAG_SCHED_POLICY_SHIFT: shift for getting scheduler policy. + * + */ +enum flat_binder_object_shifts { + FLAT_BINDER_FLAG_SCHED_POLICY_SHIFT = 9, +}; + +/** + * enum flat_binder_object_flags - flags for use in flat_binder_object.flags + */ +enum flat_binder_object_flags { + /** + * @FLAT_BINDER_FLAG_PRIORITY_MASK: bit-mask for min scheduler priority + * + * These bits can be used to set the minimum scheduler priority + * at which transactions into this node should run. Valid values + * in these bits depend on the scheduler policy encoded in + * @FLAT_BINDER_FLAG_SCHED_POLICY_MASK. + * + * For SCHED_NORMAL/SCHED_BATCH, the valid range is between [-20..19] + * For SCHED_FIFO/SCHED_RR, the value can run between [1..99] + */ FLAT_BINDER_FLAG_PRIORITY_MASK = 0xff, + /** + * @FLAT_BINDER_FLAG_ACCEPTS_FDS: whether the node accepts fds. + */ FLAT_BINDER_FLAG_ACCEPTS_FDS = 0x100, + /** + * @FLAT_BINDER_FLAG_SCHED_POLICY_MASK: bit-mask for scheduling policy + * + * These two bits can be used to set the min scheduling policy at which + * transactions on this node should run. These match the UAPI + * scheduler policy values, eg: + * 00b: SCHED_NORMAL + * 01b: SCHED_FIFO + * 10b: SCHED_RR + * 11b: SCHED_BATCH + */ + FLAT_BINDER_FLAG_SCHED_POLICY_MASK = + 3U << FLAT_BINDER_FLAG_SCHED_POLICY_SHIFT, + + /** + * @FLAT_BINDER_FLAG_INHERIT_RT: whether the node inherits RT policy + * + * Only when set, calls into this node will inherit a real-time + * scheduling policy from the caller (for synchronous transactions). + */ + FLAT_BINDER_FLAG_INHERIT_RT = 0x800, }; #ifdef BINDER_IPC_32BIT @@ -48,6 +97,14 @@ typedef __u64 binder_uintptr_t; #endif +/** + * struct binder_object_header - header shared by all binder metadata objects. + * @type: type of the object + */ +struct binder_object_header { + __u32 type; +}; + /* * This is the flattened representation of a Binder object for transfer * between processes. The 'offsets' supplied as part of a binder transaction @@ -56,8 +113,7 @@ * between processes. */ struct flat_binder_object { - /* 8 bytes for large_flat_header. */ - __u32 type; + struct binder_object_header hdr; __u32 flags; /* 8 bytes of data. */ @@ -70,6 +126,86 @@ binder_uintptr_t cookie; }; +/** + * struct binder_fd_object - describes a filedescriptor to be fixed up. + * @hdr: common header structure + * @pad_flags: padding to remain compatible with old userspace code + * @pad_binder: padding to remain compatible with old userspace code + * @fd: file descriptor + * @cookie: opaque data, used by user-space + */ +struct binder_fd_object { + struct binder_object_header hdr; + __u32 pad_flags; + union { + binder_uintptr_t pad_binder; + __u32 fd; + }; + + binder_uintptr_t cookie; +}; + +/* struct binder_buffer_object - object describing a userspace buffer + * @hdr: common header structure + * @flags: one or more BINDER_BUFFER_* flags + * @buffer: address of the buffer + * @length: length of the buffer + * @parent: index in offset array pointing to parent buffer + * @parent_offset: offset in @parent pointing to this buffer + * + * A binder_buffer object represents an object that the + * binder kernel driver can copy verbatim to the target + * address space. A buffer itself may be pointed to from + * within another buffer, meaning that the pointer inside + * that other buffer needs to be fixed up as well. This + * can be done by setting the BINDER_BUFFER_FLAG_HAS_PARENT + * flag in @flags, by setting @parent buffer to the index + * in the offset array pointing to the parent binder_buffer_object, + * and by setting @parent_offset to the offset in the parent buffer + * at which the pointer to this buffer is located. + */ +struct binder_buffer_object { + struct binder_object_header hdr; + __u32 flags; + binder_uintptr_t buffer; + binder_size_t length; + binder_size_t parent; + binder_size_t parent_offset; +}; + +enum { + BINDER_BUFFER_FLAG_HAS_PARENT = 0x01, +}; + +/* struct binder_fd_array_object - object describing an array of fds in a buffer + * @hdr: common header structure + * @pad: padding to ensure correct alignment + * @num_fds: number of file descriptors in the buffer + * @parent: index in offset array to buffer holding the fd array + * @parent_offset: start offset of fd array in the buffer + * + * A binder_fd_array object represents an array of file + * descriptors embedded in a binder_buffer_object. It is + * different from a regular binder_buffer_object because it + * describes a list of file descriptors to fix up, not an opaque + * blob of memory, and hence the kernel needs to treat it differently. + * + * An example of how this would be used is with Android's + * native_handle_t object, which is a struct with a list of integers + * and a list of file descriptors. The native_handle_t struct itself + * will be represented by a struct binder_buffer_objct, whereas the + * embedded list of file descriptors is represented by a + * struct binder_fd_array_object with that binder_buffer_object as + * a parent. + */ +struct binder_fd_array_object { + struct binder_object_header hdr; + __u32 pad; + binder_size_t num_fds; + binder_size_t parent; + binder_size_t parent_offset; +}; + /* * On 64-bit platforms where user code may run in 32-bits the driver must * translate the buffer (and local binder) addresses appropriately. @@ -97,6 +233,19 @@ #define BINDER_CURRENT_PROTOCOL_VERSION 8 #endif +/* + * Use with BINDER_GET_NODE_DEBUG_INFO, driver reads ptr, writes to all fields. + * Set ptr to NULL for the first call to get the info for the first node, and + * then repeat the call passing the previously returned value to get the next + * nodes. ptr will be 0 when there are no more nodes. + */ +struct binder_node_debug_info { + binder_uintptr_t ptr; + binder_uintptr_t cookie; + __u32 has_strong_ref; + __u32 has_weak_ref; +}; + #define BINDER_WRITE_READ _IOWR('b', 1, struct binder_write_read) #define BINDER_SET_IDLE_TIMEOUT _IOW('b', 3, __s64) #define BINDER_SET_MAX_THREADS _IOW('b', 5, __u32) @@ -104,6 +253,7 @@ #define BINDER_SET_CONTEXT_MGR _IOW('b', 7, __s32) #define BINDER_THREAD_EXIT _IOW('b', 8, __s32) #define BINDER_VERSION _IOWR('b', 9, struct binder_version) +#define BINDER_GET_NODE_DEBUG_INFO _IOWR('b', 11, struct binder_node_debug_info) /* * NOTE: Two special error codes you should check for when calling @@ -162,6 +312,11 @@ } data; }; +struct binder_transaction_data_sg { + struct binder_transaction_data transaction_data; + binder_size_t buffers_size; +}; + struct binder_ptr_cookie { binder_uintptr_t ptr; binder_uintptr_t cookie; @@ -346,6 +501,12 @@ /* * void *: cookie */ + + BC_TRANSACTION_SG = _IOW('c', 17, struct binder_transaction_data_sg), + BC_REPLY_SG = _IOW('c', 18, struct binder_transaction_data_sg), + /* + * binder_transaction_data_sg: the sent command. + */ }; #endif /* _UAPI_LINUX_BINDER_H */ diff -ruw linux-4.4.115/include/uapi/linux/eventpoll.h linux-4.4.115-fbx/include/uapi/linux/eventpoll.h --- linux-4.4.115/include/uapi/linux/eventpoll.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/uapi/linux/eventpoll.h 2019-01-22 16:16:28.547292083 +0100 @@ -39,6 +39,9 @@ #define EPOLLMSG 0x00000400 #define EPOLLRDHUP 0x00002000 +/* Set exclusive wakeup mode for the target file descriptor */ +#define EPOLLEXCLUSIVE (1U << 28) + /* * Request the handling of system wakeup events so as to prevent system suspends * from happening while those events are being processed. @@ -49,13 +52,13 @@ * * Requires CAP_BLOCK_SUSPEND */ -#define EPOLLWAKEUP (1 << 29) +#define EPOLLWAKEUP (1U << 29) /* Set the One Shot behaviour for the target file descriptor */ -#define EPOLLONESHOT (1 << 30) +#define EPOLLONESHOT (1U << 30) /* Set the Edge Triggered behaviour for the target file descriptor */ -#define EPOLLET (1 << 31) +#define EPOLLET (1U << 31) /* * On x86-64 make the 64bit structure have the same alignment as the @@ -69,6 +72,7 @@ #define EPOLL_PACKED #endif +#ifdef __KERNEL__ struct epoll_event { __u32 events; __u64 data; @@ -86,4 +90,5 @@ epev->events &= ~EPOLLWAKEUP; } #endif +#endif /* __KERNEL__ */ #endif /* _UAPI_LINUX_EVENTPOLL_H */ diff -ruw linux-4.4.115/include/uapi/linux/fib_rules.h linux-4.4.115-fbx/include/uapi/linux/fib_rules.h --- linux-4.4.115/include/uapi/linux/fib_rules.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/uapi/linux/fib_rules.h 2019-01-22 16:16:28.547292083 +0100 @@ -29,6 +29,11 @@ __u32 flags; }; +struct fib_rule_uid_range { + __u32 start; + __u32 end; +}; + enum { FRA_UNSPEC, FRA_DST, /* destination address */ @@ -49,6 +54,9 @@ FRA_TABLE, /* Extended table id */ FRA_FWMASK, /* mask for netfilter mark */ FRA_OIFNAME, + FRA_PAD, + FRA_L3MDEV, /* iif or oif is l3mdev goto its table */ + FRA_UID_RANGE, /* UID range */ __FRA_MAX }; diff -ruw linux-4.4.115/include/uapi/linux/fs.h linux-4.4.115-fbx/include/uapi/linux/fs.h --- linux-4.4.115/include/uapi/linux/fs.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/uapi/linux/fs.h 2019-10-29 09:26:25.545221791 +0100 @@ -160,6 +160,8 @@ #define FITHAW _IOWR('X', 120, int) /* Thaw */ #define FITRIM _IOWR('X', 121, struct fstrim_range) /* Trim */ +#define FIDTRIM _IOWR('f', 128, struct fstrim_range) /* Deep discard trim */ + #define FS_IOC_GETFLAGS _IOR('f', 1, long) #define FS_IOC_SETFLAGS _IOW('f', 2, long) #define FS_IOC_GETVERSION _IOR('v', 1, long) @@ -171,6 +173,54 @@ #define FS_IOC32_SETVERSION _IOW('v', 2, int) /* + * File system encryption support + */ +/* Policy provided via an ioctl on the topmost directory */ +#define FS_KEY_DESCRIPTOR_SIZE 8 + +#define FS_POLICY_FLAGS_PAD_4 0x00 +#define FS_POLICY_FLAGS_PAD_8 0x01 +#define FS_POLICY_FLAGS_PAD_16 0x02 +#define FS_POLICY_FLAGS_PAD_32 0x03 +#define FS_POLICY_FLAGS_PAD_MASK 0x03 +#define FS_POLICY_FLAGS_VALID 0x03 + +/* Encryption algorithms */ +#define FS_ENCRYPTION_MODE_INVALID 0 +#define FS_ENCRYPTION_MODE_AES_256_XTS 1 +#define FS_ENCRYPTION_MODE_AES_256_GCM 2 +#define FS_ENCRYPTION_MODE_AES_256_CBC 3 +#define FS_ENCRYPTION_MODE_AES_256_CTS 4 +#define FS_ENCRYPTION_MODE_AES_128_CBC 5 +#define FS_ENCRYPTION_MODE_AES_128_CTS 6 + + +struct fscrypt_policy { + __u8 version; + __u8 contents_encryption_mode; + __u8 filenames_encryption_mode; + __u8 flags; + __u8 master_key_descriptor[FS_KEY_DESCRIPTOR_SIZE]; +} __packed; + +#define FS_IOC_SET_ENCRYPTION_POLICY _IOR('f', 19, struct fscrypt_policy) +#define FS_IOC_GET_ENCRYPTION_PWSALT _IOW('f', 20, __u8[16]) +#define FS_IOC_GET_ENCRYPTION_POLICY _IOW('f', 21, struct fscrypt_policy) + +/* Parameters for passing an encryption key into the kernel keyring */ +#define FS_KEY_DESC_PREFIX "fscrypt:" +#define FS_KEY_DESC_PREFIX_SIZE 8 + +/* Structure that userspace passes to the kernel keyring */ +#define FS_MAX_KEY_SIZE 64 + +struct fscrypt_key { + __u32 mode; + __u8 raw[FS_MAX_KEY_SIZE]; + __u32 size; +}; + +/* * Inode flags (FS_IOC_GETFLAGS / FS_IOC_SETFLAGS) */ #define FS_SECRM_FL 0x00000001 /* Secure deletion */ diff -ruw linux-4.4.115/include/uapi/linux/fuse.h linux-4.4.115-fbx/include/uapi/linux/fuse.h --- linux-4.4.115/include/uapi/linux/fuse.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/uapi/linux/fuse.h 2019-10-29 09:26:25.545221791 +0100 @@ -250,6 +250,7 @@ #define FUSE_ASYNC_DIO (1 << 15) #define FUSE_WRITEBACK_CACHE (1 << 16) #define FUSE_NO_OPEN_SUPPORT (1 << 17) +#define FUSE_PASSTHROUGH (1 << 18) /** * CUSE INIT request/reply flags @@ -358,6 +359,7 @@ FUSE_FALLOCATE = 43, FUSE_READDIRPLUS = 44, FUSE_RENAME2 = 45, + FUSE_CANONICAL_PATH= 2016, /* CUSE specific operations */ CUSE_INIT = 4096, @@ -480,7 +482,7 @@ struct fuse_open_out { uint64_t fh; uint32_t open_flags; - uint32_t padding; + int32_t passthrough_fd; }; struct fuse_release_in { diff -ruw linux-4.4.115/include/uapi/linux/hw_breakpoint.h linux-4.4.115-fbx/include/uapi/linux/hw_breakpoint.h --- linux-4.4.115/include/uapi/linux/hw_breakpoint.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/uapi/linux/hw_breakpoint.h 2019-01-22 16:16:28.551292119 +0100 @@ -4,7 +4,11 @@ enum { HW_BREAKPOINT_LEN_1 = 1, HW_BREAKPOINT_LEN_2 = 2, + HW_BREAKPOINT_LEN_3 = 3, HW_BREAKPOINT_LEN_4 = 4, + HW_BREAKPOINT_LEN_5 = 5, + HW_BREAKPOINT_LEN_6 = 6, + HW_BREAKPOINT_LEN_7 = 7, HW_BREAKPOINT_LEN_8 = 8, }; diff -ruw linux-4.4.115/include/uapi/linux/if_arp.h linux-4.4.115-fbx/include/uapi/linux/if_arp.h --- linux-4.4.115/include/uapi/linux/if_arp.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/uapi/linux/if_arp.h 2019-01-22 16:16:28.551292119 +0100 @@ -59,6 +59,7 @@ #define ARPHRD_LAPB 516 /* LAPB */ #define ARPHRD_DDCMP 517 /* Digital's DDCMP protocol */ #define ARPHRD_RAWHDLC 518 /* Raw HDLC */ +#define ARPHRD_RAWIP 519 /* Raw IP */ #define ARPHRD_TUNNEL 768 /* IPIP tunnel */ #define ARPHRD_TUNNEL6 769 /* IP6IP6 tunnel */ diff -ruw linux-4.4.115/include/uapi/linux/if_ether.h linux-4.4.115-fbx/include/uapi/linux/if_ether.h --- linux-4.4.115/include/uapi/linux/if_ether.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/uapi/linux/if_ether.h 2019-10-29 09:26:25.545221791 +0100 @@ -130,6 +130,9 @@ #define ETH_P_IEEE802154 0x00F6 /* IEEE802.15.4 frame */ #define ETH_P_CAIF 0x00F7 /* ST-Ericsson CAIF protocol */ #define ETH_P_XDSA 0x00F8 /* Multiplexed DSA protocol */ +#define ETH_P_MAP 0x00F9 /* Qualcomm multiplexing and + * aggregation protocol + */ /* * This is an Ethernet frame header. diff -ruw linux-4.4.115/include/uapi/linux/if.h linux-4.4.115-fbx/include/uapi/linux/if.h --- linux-4.4.115/include/uapi/linux/if.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/uapi/linux/if.h 2019-04-24 19:28:47.292498169 +0200 @@ -24,6 +24,10 @@ #include /* for "struct sockaddr" et al */ #include /* for "__user" et al */ +#ifndef __KERNEL__ +#include /* for struct sockaddr. */ +#endif + #if __UAPI_DEF_IF_IFNAMSIZ #define IFNAMSIZ 16 #endif /* __UAPI_DEF_IF_IFNAMSIZ */ diff -ruw linux-4.4.115/include/uapi/linux/if_pppox.h linux-4.4.115-fbx/include/uapi/linux/if_pppox.h --- linux-4.4.115/include/uapi/linux/if_pppox.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/uapi/linux/if_pppox.h 2019-01-22 16:16:28.551292119 +0100 @@ -23,6 +23,8 @@ #include #include #include +#include +#include /* For user-space programs to pick up these definitions * which they wouldn't get otherwise without defining __KERNEL__ @@ -56,7 +58,9 @@ #define PX_PROTO_OE 0 /* Currently just PPPoE */ #define PX_PROTO_OL2TP 1 /* Now L2TP also */ #define PX_PROTO_PPTP 2 -#define PX_MAX_PROTO 3 +#define PX_PROTO_OLAC 3 +#define PX_PROTO_OPNS 4 +#define PX_MAX_PROTO 5 struct sockaddr_pppox { __kernel_sa_family_t sa_family; /* address family, AF_PPPOX */ diff -ruw linux-4.4.115/include/uapi/linux/if_tun.h linux-4.4.115-fbx/include/uapi/linux/if_tun.h --- linux-4.4.115/include/uapi/linux/if_tun.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/uapi/linux/if_tun.h 2019-01-22 16:16:28.555292155 +0100 @@ -57,6 +57,32 @@ #define TUNSETVNETBE _IOW('T', 222, int) #define TUNGETVNETBE _IOR('T', 223, int) + +struct smalltun_rule { + __u8 proto; + __be16 src_port_start; + __be16 src_port_end; + __be16 dst_port_start; + __be16 dst_port_end; +}; + +struct smalltun_fp { + __be32 inner_src; + __be32 inner_dst; + + __u32 af; + __u8 outer_src[16]; + __u8 outer_dst[16]; + __be16 outer_src_port; + __be16 outer_dst_port; + + struct smalltun_rule rules[8]; + __u32 rule_count; +}; + +#define TUNSMALLTUNSETFP _IOW('T', 224, struct smalltun_fp) +#define TUNSMALLTUNDELFP _IOW('T', 225, struct smalltun_fp) + /* TUNSETIFF ifr flags */ #define IFF_TUN 0x0001 #define IFF_TAP 0x0002 diff -ruw linux-4.4.115/include/uapi/linux/inet_diag.h linux-4.4.115-fbx/include/uapi/linux/inet_diag.h --- linux-4.4.115/include/uapi/linux/inet_diag.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/uapi/linux/inet_diag.h 2019-01-22 16:16:28.555292155 +0100 @@ -72,6 +72,8 @@ INET_DIAG_BC_AUTO, INET_DIAG_BC_S_COND, INET_DIAG_BC_D_COND, + INET_DIAG_BC_DEV_COND, /* u32 ifindex */ + INET_DIAG_BC_MARK_COND, }; struct inet_diag_hostcond { @@ -81,6 +83,11 @@ __be32 addr[0]; }; +struct inet_diag_markcond { + __u32 mark; + __u32 mask; +}; + /* Base info structure. It contains socket identity (addrs/ports/cookie) * and, alas, the information shown by netstat. */ struct inet_diag_msg { @@ -113,9 +120,13 @@ INET_DIAG_DCTCPINFO, INET_DIAG_PROTOCOL, /* response attribute only */ INET_DIAG_SKV6ONLY, + INET_DIAG_LOCALS, + INET_DIAG_PEERS, + INET_DIAG_PAD, + INET_DIAG_MARK, }; -#define INET_DIAG_MAX INET_DIAG_SKV6ONLY +#define INET_DIAG_MAX INET_DIAG_MARK /* INET_DIAG_MEM */ diff -ruw linux-4.4.115/include/uapi/linux/input-event-codes.h linux-4.4.115-fbx/include/uapi/linux/input-event-codes.h --- linux-4.4.115/include/uapi/linux/input-event-codes.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/uapi/linux/input-event-codes.h 2019-10-29 09:26:25.545221791 +0100 @@ -611,6 +611,37 @@ #define KEY_KBDINPUTASSIST_ACCEPT 0x264 #define KEY_KBDINPUTASSIST_CANCEL 0x265 +/* Diagonal movement keys */ +#define KEY_RIGHT_UP 0x266 +#define KEY_RIGHT_DOWN 0x267 +#define KEY_LEFT_UP 0x268 +#define KEY_LEFT_DOWN 0x269 + +#define KEY_ROOT_MENU 0x26a /* Show Device's Root Menu */ +/* Show Top Menu of the Media (e.g. DVD) */ +#define KEY_MEDIA_TOP_MENU 0x26b +#define KEY_NUMERIC_11 0x26c +#define KEY_NUMERIC_12 0x26d +/* + * Toggle Audio Description: refers to an audio service that helps blind and + * visually impaired consumers understand the action in a program. Note: in + * some countries this is referred to as "Video Description". + */ +#define KEY_AUDIO_DESC 0x26e +#define KEY_3D_MODE 0x26f +#define KEY_NEXT_FAVORITE 0x270 +#define KEY_STOP_RECORD 0x271 +#define KEY_PAUSE_RECORD 0x272 +#define KEY_VOD 0x273 /* Video on Demand */ +#define KEY_UNMUTE 0x274 +#define KEY_FASTREVERSE 0x275 +#define KEY_SLOWREVERSE 0x276 +/* + * Control a data application associated with the currently viewed channel, + * e.g. teletext or data broadcast application (MHEG, MHP, HbbTV, etc.) + */ +#define KEY_DATA 0x275 + #define BTN_TRIGGER_HAPPY 0x2c0 #define BTN_TRIGGER_HAPPY1 0x2c0 #define BTN_TRIGGER_HAPPY2 0x2c1 @@ -653,6 +684,18 @@ #define BTN_TRIGGER_HAPPY39 0x2e6 #define BTN_TRIGGER_HAPPY40 0x2e7 +#define KEY_APP_TV 0x2f1 +#define KEY_APP_REPLAY 0x2f2 +#define KEY_APP_VIDEOCLUB 0x2f3 +#define KEY_APP_WHATSON 0x2f4 +#define KEY_APP_RECORDS 0x2f5 +#define KEY_APP_MEDIA 0x2f6 +#define KEY_APP_YOUTUBE 0x2f7 +#define KEY_APP_RADIOS 0x2f8 +#define KEY_APP_CANALVOD 0x2f9 +#define KEY_APP_PIP 0x2fa +#define KEY_APP_NETFLIX 0x2fb + /* We avoid low common keys in module aliases so they don't get huge. */ #define KEY_MIN_INTERESTING KEY_MUTE #define KEY_MAX 0x2ff @@ -749,7 +792,11 @@ #define SW_ROTATE_LOCK 0x0c /* set = rotate locked/disabled */ #define SW_LINEIN_INSERT 0x0d /* set = inserted */ #define SW_MUTE_DEVICE 0x0e /* set = device disabled */ -#define SW_MAX 0x0f +#define SW_HPHL_OVERCURRENT 0x0f /* set = over current on left hph */ +#define SW_HPHR_OVERCURRENT 0x10 /* set = over current on right hph */ +#define SW_MICROPHONE2_INSERT 0x11 /* set = inserted */ +#define SW_UNSUPPORT_INSERT 0x12 /* set = unsupported device inserted */ +#define SW_MAX 0x20 #define SW_CNT (SW_MAX+1) /* diff -ruw linux-4.4.115/include/uapi/linux/input.h linux-4.4.115-fbx/include/uapi/linux/input.h --- linux-4.4.115/include/uapi/linux/input.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/uapi/linux/input.h 2019-01-22 16:16:28.555292155 +0100 @@ -161,6 +161,50 @@ #define EVIOCGRAB _IOW('E', 0x90, int) /* Grab/Release device */ #define EVIOCREVOKE _IOW('E', 0x91, int) /* Revoke device access */ +#define EVIOCSCLOCKID _IOW('E', 0xa0, int) /* Set clockid to be used for timestamps */ + +/* + * Device properties and quirks + */ + +/* HACK: disable conflicting EVIOCREVOKE until Android userspace stops using EVIOCSSUSPENDBLOCK */ +/*#define EVIOCREVOKE _IOW('E', 0x91, int)*/ /* Revoke device access */ + +#define INPUT_PROP_POINTER 0x00 /* needs a pointer */ +#define INPUT_PROP_DIRECT 0x01 /* direct input devices */ +#define INPUT_PROP_BUTTONPAD 0x02 /* has button(s) under pad */ +#define INPUT_PROP_SEMI_MT 0x03 /* touch rectangle only */ +#define INPUT_PROP_TOPBUTTONPAD 0x04 /* softbuttons at top of pad */ +#define INPUT_PROP_POINTING_STICK 0x05 /* is a pointing stick */ +#define INPUT_PROP_NO_DUMMY_RELEASE 0x06 /* no dummy event */ + +#define INPUT_PROP_MAX 0x1f +#define INPUT_PROP_CNT (INPUT_PROP_MAX + 1) + +/* + * Event types + */ + +#define EV_SYN 0x00 +#define EV_KEY 0x01 +#define EV_REL 0x02 +#define EV_ABS 0x03 +#define EV_MSC 0x04 +#define EV_SW 0x05 +#define EV_LED 0x11 +#define EV_SND 0x12 +#define EV_REP 0x14 +#define EV_FF 0x15 +#define EV_PWR 0x16 +#define EV_FF_STATUS 0x17 +#define EV_MAX 0x1f +#define EV_CNT (EV_MAX+1) + +/* + * Synchronization events. + */ + + /** * EVIOCGMASK - Retrieve current event mask * @@ -246,6 +290,7 @@ #define BUS_GSC 0x1A #define BUS_ATARI 0x1B #define BUS_SPI 0x1C +#define BUS_CEC 0x1E /* * MT_TOOL types diff -ruw linux-4.4.115/include/uapi/linux/ip.h linux-4.4.115-fbx/include/uapi/linux/ip.h --- linux-4.4.115/include/uapi/linux/ip.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/uapi/linux/ip.h 2019-01-22 16:16:28.555292155 +0100 @@ -165,6 +165,7 @@ IPV4_DEVCONF_IGMPV2_UNSOLICITED_REPORT_INTERVAL, IPV4_DEVCONF_IGMPV3_UNSOLICITED_REPORT_INTERVAL, IPV4_DEVCONF_IGNORE_ROUTES_WITH_LINKDOWN, + IPV4_DEVCONF_NF_IPV4_DEFRAG_SKIP, __IPV4_DEVCONF_MAX }; diff -ruw linux-4.4.115/include/uapi/linux/ipv6.h linux-4.4.115-fbx/include/uapi/linux/ipv6.h --- linux-4.4.115/include/uapi/linux/ipv6.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/uapi/linux/ipv6.h 2019-01-22 16:16:28.555292155 +0100 @@ -164,6 +164,7 @@ DEVCONF_ACCEPT_DAD, DEVCONF_FORCE_TLLAO, DEVCONF_NDISC_NOTIFY, + DEVCONF_ACCEPT_RA_RT_TABLE, DEVCONF_MLDV1_UNSOLICITED_REPORT_INTERVAL, DEVCONF_MLDV2_UNSOLICITED_REPORT_INTERVAL, DEVCONF_SUPPRESS_FRAG_NDISC, @@ -174,6 +175,17 @@ DEVCONF_USE_OIF_ADDRS_ONLY, DEVCONF_ACCEPT_RA_MIN_HOP_LIMIT, DEVCONF_IGNORE_ROUTES_WITH_LINKDOWN, + DEVCONF_ACCEPT_RA_PREFIX_ROUTE, + DEVCONF_DROP_UNICAST_IN_L2_MULTICAST, + DEVCONF_DROP_UNSOLICITED_NA, + DEVCONF_KEEP_ADDR_ON_DOWN, + DEVCONF_RTR_SOLICIT_MAX_INTERVAL, + DEVCONF_SEG6_ENABLED, + DEVCONF_SEG6_REQUIRE_HMAC, + DEVCONF_ENHANCED_DAD, + DEVCONF_ADDR_GEN_MODE, + DEVCONF_DISABLE_POLICY, + DEVCONF_ACCEPT_RA_RT_INFO_MIN_PLEN, DEVCONF_MAX }; diff -ruw linux-4.4.115/include/uapi/linux/Kbuild linux-4.4.115-fbx/include/uapi/linux/Kbuild --- linux-4.4.115/include/uapi/linux/Kbuild 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/uapi/linux/Kbuild 2019-10-29 09:26:25.541221752 +0100 @@ -22,6 +22,8 @@ header-y += netfilter_ipv6/ header-y += usb/ header-y += wimax/ +header-y += mfd/ +header-y += nfc/ genhdr-y += version.h @@ -30,6 +32,7 @@ header-y += a.out.h endif +header-y += ashmem.h header-y += acct.h header-y += adb.h header-y += adfs_fs.h @@ -62,8 +65,10 @@ header-y += auto_fs4.h header-y += auto_fs.h header-y += auxvec.h +header-y += avtimer.h header-y += ax25.h header-y += b1lli.h +header-y += batterydata-interface.h header-y += baycom.h header-y += bcm933xx_hcs.h header-y += bfs_fs.h @@ -81,6 +86,8 @@ header-y += cciss_defs.h header-y += cciss_ioctl.h header-y += cdrom.h +header-y += cec.h +header-y += cec-funcs.h header-y += cgroupstats.h header-y += chio.h header-y += cm4000_cs.h @@ -111,10 +118,13 @@ header-y += elf-em.h header-y += elf-fdpic.h header-y += elf.h +header-y += epm_adc.h header-y += errno.h header-y += errqueue.h +header-y += esoc_ctrl.h header-y += ethtool.h header-y += eventpoll.h +header-y += exfat_user.h header-y += fadvise.h header-y += falloc.h header-y += fanotify.h @@ -125,6 +135,7 @@ header-y += fib_rules.h header-y += fiemap.h header-y += filter.h +header-y += fips_status.h header-y += firewire-cdev.h header-y += firewire-constants.h header-y += flat.h @@ -139,6 +150,8 @@ header-y += gfs2_ondisk.h header-y += gigaset_dev.h header-y += gsmmux.h +header-y += hbtp_input.h +header-y += hbtp_vm.h header-y += hdlcdrv.h header-y += hdlc.h header-y += hdreg.h @@ -195,6 +208,8 @@ header-y += input-event-codes.h header-y += in_route.h header-y += ioctl.h +header-y += ion.h +header-y += ion_test.h header-y += ip6_tunnel.h header-y += ipc.h header-y += ip.h @@ -250,7 +265,9 @@ header-y += major.h header-y += map_to_7segment.h header-y += matroxfb.h +header-y += maxim_sti.h header-y += mdio.h +header-y += mdss_rotator.h header-y += media.h header-y += media-bus-format.h header-y += mei.h @@ -258,6 +275,7 @@ header-y += memfd.h header-y += mempolicy.h header-y += meye.h +header-y += mhi.h header-y += mic_common.h header-y += mic_ioctl.h header-y += mii.h @@ -271,6 +289,34 @@ header-y += mroute.h header-y += msdos_fs.h header-y += msg.h +header-y += msm_adsp.h +header-y += msm_audio.h +header-y += msm_audio_aac.h +header-y += msm_audio_ac3.h +header-y += msm_audio_amrnb.h +header-y += msm_audio_amrwb.h +header-y += msm_audio_amrwbplus.h +header-y += msm_audio_calibration.h +header-y += msm_audio_mvs.h +header-y += msm_audio_qcp.h +header-y += msm_audio_sbc.h +header-y += msm_audio_voicememo.h +header-y += msm_audio_wma.h +header-y += msm_audio_wmapro.h +header-y += msm_audio_alac.h +header-y += msm_audio_ape.h +header-y += msm_audio_g711.h +header-y += msm_audio_g711_dec.h +header-y += msm_ion.h +header-y += msm_ipc.h +header-y += msm_kgsl.h +header-y += msm_pft.h +header-y += msm_mdp.h +header-y += msm_mdp_ext.h +header-y += msm_rmnet.h +header-y += msm_rotator.h +header-y += msm_vidc_dec.h +header-y += msm_vidc_enc.h header-y += mtio.h header-y += nbd.h header-y += ncp_fs.h @@ -282,6 +328,7 @@ header-y += netconf.h header-y += netdevice.h header-y += net_dropmon.h +header-y += net_map.h header-y += netfilter_arp.h header-y += netfilter_bridge.h header-y += netfilter_decnet.h @@ -311,6 +358,7 @@ header-y += nvram.h header-y += omap3isp.h header-y += omapfb.h +header-y += oneshot_sync.h header-y += oom.h header-y += openvswitch.h header-y += packet_diag.h @@ -337,11 +385,17 @@ header-y += ppp-ioctl.h header-y += pps.h header-y += prctl.h +header-y += prctl-private.h header-y += psci.h header-y += ptp_clock.h header-y += ptrace.h +header-y += qbt1000.h +header-y += qcedev.h +header-y += qcota.h header-y += qnx4_fs.h header-y += qnxtypes.h +header-y += qseecom.h +header-y += qrng.h header-y += quota.h header-y += radeonfb.h header-y += random.h @@ -352,6 +406,8 @@ header-y += reiserfs_xattr.h header-y += resource.h header-y += rfkill.h +header-y += rmnet_data.h +header-y += rmnet.h header-y += romfs_fs.h header-y += rose.h header-y += route.h @@ -365,6 +421,8 @@ header-y += sdla.h header-y += seccomp.h header-y += securebits.h +header-y += seemp_api.h +header-y += seemp_param_id.h header-y += selinux_netlink.h header-y += sem.h header-y += serial_core.h @@ -378,16 +436,20 @@ header-y += snmp.h header-y += sock_diag.h header-y += socket.h +header-y += sockev.h header-y += sockios.h header-y += sonet.h header-y += sonypi.h header-y += soundcard.h header-y += sound.h +header-y += spcom.h header-y += stat.h header-y += stddef.h header-y += string.h header-y += suspend_ioctls.h +header-y += sw_sync.h header-y += swab.h +header-y += sync.h header-y += synclink.h header-y += sysctl.h header-y += sysinfo.h @@ -461,3 +523,16 @@ header-y += zorro.h header-y += zorro_ids.h header-y += userfaultfd.h +header-y += msm_dsps.h +header-y += msm-core-interface.h +header-y += msm_thermal_ioctl.h +header-y += android_pmem.h +header-y += ipa_qmi_service_v01.h +header-y += rmnet_ipa_fd_ioctl.h +header-y += msm_ipa.h +header-y += smcinvoke.h +header-y += habmm.h + +header-y += fbxatm.h +header-y += rtl8367c_ioctl.h +header-y += hdmi-cec/ diff -ruw linux-4.4.115/include/uapi/linux/magic.h linux-4.4.115-fbx/include/uapi/linux/magic.h --- linux-4.4.115/include/uapi/linux/magic.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/uapi/linux/magic.h 2019-01-22 16:16:28.559292192 +0100 @@ -52,8 +52,11 @@ #define REISER2FS_SUPER_MAGIC_STRING "ReIsEr2Fs" #define REISER2FS_JR_SUPER_MAGIC_STRING "ReIsEr3Fs" +#define SDCARDFS_SUPER_MAGIC 0x5dca2df5 + #define SMB_SUPER_MAGIC 0x517B #define CGROUP_SUPER_MAGIC 0x27e0eb +#define CGROUP2_SUPER_MAGIC 0x63677270 #define STACK_END_MAGIC 0x57AC6E9D @@ -76,5 +79,7 @@ #define BTRFS_TEST_MAGIC 0x73727279 #define NSFS_MAGIC 0x6e736673 #define BPF_FS_MAGIC 0xcafe4a11 +#define BALLOON_KVM_MAGIC 0x13661366 +#define ZSMALLOC_MAGIC 0x58295829 #endif /* __LINUX_MAGIC_H__ */ diff -ruw linux-4.4.115/include/uapi/linux/mmc/ioctl.h linux-4.4.115-fbx/include/uapi/linux/mmc/ioctl.h --- linux-4.4.115/include/uapi/linux/mmc/ioctl.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/uapi/linux/mmc/ioctl.h 2019-01-22 16:16:28.563292228 +0100 @@ -63,6 +63,61 @@ * commands in array in sequence to card. */ #define MMC_IOC_MULTI_CMD _IOWR(MMC_BLOCK_MAJOR, 1, struct mmc_ioc_multi_cmd) + +/** + * There are four request types that are applicable for rpmb accesses- two + * under read category and two under write. They are + * + * Reads + * ------- + * 1. Read Write Counter + * 2. Authenticated data read + * + * + * Writes + * ------- + * 1. Provision RPMB key (though it might be done in a secure environment) + * 2. Authenticated data write + * + * While its given that the rpmb data frames are going to have that + * information encoded in it and the frames should be generated by a secure + * piece of code, the request types can be classified as above. + * + * So here are the set of commands that should be executed atomically in the + * ioctl for rpmb read operation + * 1. Switch partition + * 2. Set block count + * 3. Write data frame - CMD25 to write the rpmb data frame + * 4. Set block count + * 5. Read the data - CMD18 to do the actual read + * + * Similarly for rpmb write operation, these are the commands that should be + * executed atomically in the ioctl for rpmb write operation + * 1. Switch partition + * 2. Set block count + * 3. Write data frame - CMD25 to write the rpmb data frame with data + * 4. Set block count + * 5. Read the data - CMD25 to write rpmb data frame indicating that rpmb + * result register is about to be read + * 6. Set block count + * 7. Read rpmb result - CMD18 to read the rpmb result register + * + * Each of the above commands should be sent individually via struct mmc_ioc_cmd + * and fields like is_acmd that are not needed for rpmb operations will be + * ignored. + */ +#define MMC_IOC_MAX_RPMB_CMD 3 +struct mmc_ioc_rpmb { + struct mmc_ioc_cmd cmds[MMC_IOC_MAX_RPMB_CMD]; +}; + +/* + * This ioctl is meant for use with rpmb partitions. This is needed since the + * access procedure for this particular partition is different from regular + * or normal partitions. + */ +#define MMC_IOC_RPMB_CMD _IOWR(MMC_BLOCK_MAJOR, 0, struct mmc_ioc_rpmb) + /* * Since this ioctl is only meant to enhance (and not replace) normal access * to the mmc bus device, an upper data transfer limit of MMC_IOC_MAX_BYTES diff -ruw linux-4.4.115/include/uapi/linux/mmc/Kbuild linux-4.4.115-fbx/include/uapi/linux/mmc/Kbuild --- linux-4.4.115/include/uapi/linux/mmc/Kbuild 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/uapi/linux/mmc/Kbuild 2019-01-22 16:16:28.563292228 +0100 @@ -1,2 +1,6 @@ # UAPI Header export list +header-y += core.h +header-y += core.h header-y += ioctl.h +header-y += mmc.h +header-y += mmc.h diff -ruw linux-4.4.115/include/uapi/linux/netfilter/xt_IDLETIMER.h linux-4.4.115-fbx/include/uapi/linux/netfilter/xt_IDLETIMER.h --- linux-4.4.115/include/uapi/linux/netfilter/xt_IDLETIMER.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/uapi/linux/netfilter/xt_IDLETIMER.h 2019-01-22 16:16:28.571292300 +0100 @@ -4,6 +4,7 @@ * Header file for Xtables timer target module. * * Copyright (C) 2004, 2010 Nokia Corporation + * * Written by Timo Teras * * Converted to x_tables and forward-ported to 2.6.34 @@ -32,12 +33,19 @@ #include #define MAX_IDLETIMER_LABEL_SIZE 28 +#define NLMSG_MAX_SIZE 64 + +#define NL_EVENT_TYPE_INACTIVE 0 +#define NL_EVENT_TYPE_ACTIVE 1 struct idletimer_tg_info { __u32 timeout; char label[MAX_IDLETIMER_LABEL_SIZE]; + /* Use netlink messages for notification in addition to sysfs */ + __u8 send_nl_msg; + /* for kernel module internal use only */ struct idletimer_tg *timer __attribute__((aligned(8))); }; diff -ruw linux-4.4.115/include/uapi/linux/netfilter/xt_socket.h linux-4.4.115-fbx/include/uapi/linux/netfilter/xt_socket.h --- linux-4.4.115/include/uapi/linux/netfilter/xt_socket.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/uapi/linux/netfilter/xt_socket.h 2019-01-22 16:16:28.575292336 +0100 @@ -26,4 +26,11 @@ | XT_SOCKET_NOWILDCARD \ | XT_SOCKET_RESTORESKMARK) +struct sock *xt_socket_lookup_slow_v4(struct net *net, + const struct sk_buff *skb, + const struct net_device *indev); +struct sock *xt_socket_lookup_slow_v6(struct net *net, + const struct sk_buff *skb, + const struct net_device *indev); + #endif /* _XT_SOCKET_H */ diff -ruw linux-4.4.115/include/uapi/linux/netlink.h linux-4.4.115-fbx/include/uapi/linux/netlink.h --- linux-4.4.115/include/uapi/linux/netlink.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/uapi/linux/netlink.h 2019-01-22 16:16:28.579292373 +0100 @@ -27,7 +27,7 @@ #define NETLINK_ECRYPTFS 19 #define NETLINK_RDMA 20 #define NETLINK_CRYPTO 21 /* Crypto layer */ - +#define NETLINK_SOCKEV 22 /* Socket Administrative Events */ #define NETLINK_INET_DIAG NETLINK_SOCK_DIAG #define MAX_LINKS 32 diff -ruw linux-4.4.115/include/uapi/linux/nl80211.h linux-4.4.115-fbx/include/uapi/linux/nl80211.h --- linux-4.4.115/include/uapi/linux/nl80211.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/uapi/linux/nl80211.h 2019-10-29 09:26:25.549221830 +0100 @@ -172,6 +172,42 @@ */ /** + * DOC: FILS shared key authentication offload + * + * FILS shared key authentication offload can be advertized by drivers by + * setting @NL80211_EXT_FEATURE_FILS_SK_OFFLOAD flag. The drivers that support + * FILS shared key authentication offload should be able to construct the + * authentication and association frames for FILS shared key authentication and + * eventually do a key derivation as per IEEE 802.11ai. The below additional + * parameters should be given to driver in %NL80211_CMD_CONNECT. + * %NL80211_ATTR_FILS_ERP_USERNAME - used to construct keyname_nai + * %NL80211_ATTR_FILS_ERP_REALM - used to construct keyname_nai + * %NL80211_ATTR_FILS_ERP_NEXT_SEQ_NUM - used to construct erp message + * %NL80211_ATTR_FILS_ERP_RRK - used to generate the rIK and rMSK + * rIK should be used to generate an authentication tag on the ERP message and + * rMSK should be used to derive a PMKSA. + * rIK, rMSK should be generated and keyname_nai, sequence number should be used + * as specified in IETF RFC 6696. + * + * When FILS shared key authentication is completed, driver needs to provide the + * below additional parameters to userspace. + * %NL80211_ATTR_FILS_KEK - used for key renewal + * %NL80211_ATTR_FILS_ERP_NEXT_SEQ_NUM - used in further EAP-RP exchanges + * %NL80211_ATTR_PMKID - used to identify the PMKSA used/generated + * %Nl80211_ATTR_PMK - used to update PMKSA cache in userspace + * The PMKSA can be maintained in userspace persistently so that it can be used + * later after reboots or wifi turn off/on also. + * + * %NL80211_ATTR_FILS_CACHE_ID is the cache identifier advertized by a FILS + * capable AP supporting PMK caching. It specifies the scope within which the + * PMKSAs are cached in an ESS. %NL80211_CMD_SET_PMKSA and + * %NL80211_CMD_DEL_PMKSA are enhanced to allow support for PMKSA caching based + * on FILS cache identifier. Additionally %NL80211_ATTR_PMK is used with + * %NL80211_SET_PMKSA to specify the PMK corresponding to a PMKSA for driver to + * use in a FILS shared key connection with PMKSA caching. + */ + +/** * enum nl80211_commands - supported nl80211 commands * * @NL80211_CMD_UNSPEC: unspecified command to catch errors @@ -322,7 +358,9 @@ * @NL80211_CMD_GET_SCAN: get scan results * @NL80211_CMD_TRIGGER_SCAN: trigger a new scan with the given parameters * %NL80211_ATTR_TX_NO_CCK_RATE is used to decide whether to send the - * probe requests at CCK rate or not. + * probe requests at CCK rate or not. %NL80211_ATTR_BSSID can be used to + * specify a BSSID to scan for; if not included, the wildcard BSSID will + * be used. * @NL80211_CMD_NEW_SCAN_RESULTS: scan notification (as a reply to * NL80211_CMD_GET_SCAN and on the "scan" multicast group) * @NL80211_CMD_SCAN_ABORTED: scan was aborted, for unspecified reasons, @@ -367,10 +405,18 @@ * @NL80211_CMD_NEW_SURVEY_RESULTS: survey data notification (as a reply to * NL80211_CMD_GET_SURVEY and on the "scan" multicast group) * - * @NL80211_CMD_SET_PMKSA: Add a PMKSA cache entry, using %NL80211_ATTR_MAC - * (for the BSSID) and %NL80211_ATTR_PMKID. + * @NL80211_CMD_SET_PMKSA: Add a PMKSA cache entry using %NL80211_ATTR_MAC + * (for the BSSID), %NL80211_ATTR_PMKID, and optionally %NL80211_ATTR_PMK + * (PMK is used for PTKSA derivation in case of FILS shared key offload) or + * using %NL80211_ATTR_SSID, %NL80211_ATTR_FILS_CACHE_ID, + * %NL80211_ATTR_PMKID, and %NL80211_ATTR_PMK in case of FILS + * authentication where %NL80211_ATTR_FILS_CACHE_ID is the identifier + * advertized by a FILS capable AP identifying the scope of PMKSA in an + * ESS. * @NL80211_CMD_DEL_PMKSA: Delete a PMKSA cache entry, using %NL80211_ATTR_MAC - * (for the BSSID) and %NL80211_ATTR_PMKID. + * (for the BSSID) and %NL80211_ATTR_PMKID or using %NL80211_ATTR_SSID, + * %NL80211_ATTR_FILS_CACHE_ID, and %NL80211_ATTR_PMKID in case of FILS + * authentication. * @NL80211_CMD_FLUSH_PMKSA: Flush all PMKSA cache entries. * * @NL80211_CMD_REG_CHANGE: indicates to userspace the regulatory domain @@ -484,7 +530,12 @@ * This attribute is ignored if driver does not support roam scan. * It is also sent as an event, with the BSSID and response IEs when the * connection is established or failed to be established. This can be - * determined by the STATUS_CODE attribute. + * determined by the %NL80211_ATTR_STATUS_CODE attribute (0 = success, + * non-zero = failure). If %NL80211_ATTR_TIMED_OUT is included in the + * event, the connection attempt failed due to not being able to initiate + * authentication/association or not receiving a response from the AP. + * Non-zero %NL80211_ATTR_STATUS_CODE value is indicated in that case as + * well to remain backwards compatible. * @NL80211_CMD_ROAM: request that the card roam (currently not implemented), * sent as an event when the card/driver roamed by itself. * @NL80211_CMD_DISCONNECT: drop a given connection; also used to notify @@ -820,6 +871,51 @@ * as an event to indicate changes for devices with wiphy-specific regdom * management. * + * @NL80211_CMD_ABORT_SCAN: Stop an ongoing scan. Returns -ENOENT if a scan is + * not running. The driver indicates the status of the scan through + * cfg80211_scan_done(). + * + * @NL80211_CMD_START_NAN: Start NAN operation, identified by its + * %NL80211_ATTR_WDEV interface. This interface must have been previously + * created with %NL80211_CMD_NEW_INTERFACE. After it has been started, the + * NAN interface will create or join a cluster. This command must have a + * valid %NL80211_ATTR_NAN_MASTER_PREF attribute and optional + * %NL80211_ATTR_NAN_DUAL attributes. + * After this command NAN functions can be added. + * @NL80211_CMD_STOP_NAN: Stop the NAN operation, identified by + * its %NL80211_ATTR_WDEV interface. + * @NL80211_CMD_ADD_NAN_FUNCTION: Add a NAN function. The function is defined + * with %NL80211_ATTR_NAN_FUNC nested attribute. When called, this + * operation returns the strictly positive and unique instance id + * (%NL80211_ATTR_NAN_FUNC_INST_ID) and a cookie (%NL80211_ATTR_COOKIE) + * of the function upon success. + * Since instance ID's can be re-used, this cookie is the right + * way to identify the function. This will avoid races when a termination + * event is handled by the user space after it has already added a new + * function that got the same instance id from the kernel as the one + * which just terminated. + * This cookie may be used in NAN events even before the command + * returns, so userspace shouldn't process NAN events until it processes + * the response to this command. + * Look at %NL80211_ATTR_SOCKET_OWNER as well. + * @NL80211_CMD_DEL_NAN_FUNCTION: Delete a NAN function by cookie. + * This command is also used as a notification sent when a NAN function is + * terminated. This will contain a %NL80211_ATTR_NAN_FUNC_INST_ID + * and %NL80211_ATTR_COOKIE attributes. + * @NL80211_CMD_CHANGE_NAN_CONFIG: Change current NAN configuration. NAN + * must be operational (%NL80211_CMD_START_NAN was executed). + * It must contain at least one of the following attributes: + * %NL80211_ATTR_NAN_MASTER_PREF, %NL80211_ATTR_NAN_DUAL. + * @NL80211_CMD_NAN_FUNC_MATCH: Notification sent when a match is reported. + * This will contain a %NL80211_ATTR_NAN_MATCH nested attribute and + * %NL80211_ATTR_COOKIE. + * + * @NL80211_CMD_UPDATE_CONNECT_PARAMS: Update one or more connect parameters + * for subsequent roaming cases if the driver or firmware uses internal + * BSS selection. This command can be issued only while connected and it + * does not result in a change for the current association. Currently, + * only the %NL80211_ATTR_IE data is used and updated with this command. + * * @NL80211_CMD_MAX: highest used command number * @__NL80211_CMD_AFTER_LAST: internal use */ @@ -1006,6 +1102,19 @@ NL80211_CMD_WIPHY_REG_CHANGE, + NL80211_CMD_ABORT_SCAN, + + NL80211_CMD_START_NAN, + NL80211_CMD_STOP_NAN, + NL80211_CMD_ADD_NAN_FUNCTION, + NL80211_CMD_DEL_NAN_FUNCTION, + NL80211_CMD_CHANGE_NAN_CONFIG, + NL80211_CMD_NAN_MATCH, + + NL80211_CMD_SET_MULTICAST_TO_UNICAST, + + NL80211_CMD_UPDATE_CONNECT_PARAMS, + /* add new commands above here */ /* used to define NL80211_CMD_MAX below */ @@ -1320,7 +1429,13 @@ * enum nl80211_band value is used as the index (nla_type() of the nested * data. If a band is not included, it will be configured to allow all * rates based on negotiated supported rates information. This attribute - * is used with %NL80211_CMD_SET_TX_BITRATE_MASK. + * is used with %NL80211_CMD_SET_TX_BITRATE_MASK and with starting AP, + * and joining mesh networks (not IBSS yet). In the later case, it must + * specify just a single bitrate, which is to be used for the beacon. + * The driver must also specify support for this with the extended + * features NL80211_EXT_FEATURE_BEACON_RATE_LEGACY, + * NL80211_EXT_FEATURE_BEACON_RATE_HT and + * NL80211_EXT_FEATURE_BEACON_RATE_VHT. * * @NL80211_ATTR_FRAME_MATCH: A binary attribute which typically must contain * at least one byte, currently used with @NL80211_CMD_REGISTER_FRAME. @@ -1566,8 +1681,16 @@ * the connection request from a station. nl80211_connect_failed_reason * enum has different reasons of connection failure. * - * @NL80211_ATTR_SAE_DATA: SAE elements in Authentication frames. This starts - * with the Authentication transaction sequence number field. + * @NL80211_ATTR_AUTH_DATA: Fields and elements in Authentication frames. + * This contains the authentication frame body (non-IE and IE data), + * excluding the Authentication algorithm number, i.e., starting at the + * Authentication transaction sequence number field. It is used with + * authentication algorithms that need special fields to be added into + * the frames (SAE and FILS). Currently, only the SAE cases use the + * initial two fields (Authentication transaction sequence number and + * Status code). However, those fields are included in the attribute data + * for all authentication algorithms to keep the attribute definition + * consistent. * * @NL80211_ATTR_VHT_CAPABILITY: VHT Capability information element (from * association request when used with NL80211_CMD_NEW_STATION) @@ -1764,8 +1887,9 @@ * over all channels. * * @NL80211_ATTR_SCHED_SCAN_DELAY: delay before the first cycle of a - * scheduled scan (or a WoWLAN net-detect scan) is started, u32 - * in seconds. + * scheduled scan is started. Or the delay before a WoWLAN + * net-detect scan is started, counting from the moment the + * system is suspended. This value is a u32, in seconds. * @NL80211_ATTR_REG_INDOOR: flag attribute, if set indicates that the device * is operating in an indoor environment. @@ -1782,6 +1906,133 @@ * thus it must not specify the number of iterations, only the interval * between scans. The scan plans are executed sequentially. * Each scan plan is a nested attribute of &enum nl80211_sched_scan_plan. + * @NL80211_ATTR_PBSS: flag attribute. If set it means operate + * in a PBSS. Specified in %NL80211_CMD_CONNECT to request + * connecting to a PCP, and in %NL80211_CMD_START_AP to start + * a PCP instead of AP. Relevant for DMG networks only. + * @NL80211_ATTR_BSS_SELECT: nested attribute for driver supporting the + * BSS selection feature. When used with %NL80211_CMD_GET_WIPHY it contains + * attributes according &enum nl80211_bss_select_attr to indicate what + * BSS selection behaviours are supported. When used with %NL80211_CMD_CONNECT + * it contains the behaviour-specific attribute containing the parameters for + * BSS selection to be done by driver and/or firmware. + * + * @NL80211_ATTR_STA_SUPPORT_P2P_PS: whether P2P PS mechanism supported + * or not. u8, one of the values of &enum nl80211_sta_p2p_ps_status + * + * @NL80211_ATTR_PAD: attribute used for padding for 64-bit alignment + * + * @NL80211_ATTR_IFTYPE_EXT_CAPA: Nested attribute of the following attributes: + * %NL80211_ATTR_IFTYPE, %NL80211_ATTR_EXT_CAPA, + * %NL80211_ATTR_EXT_CAPA_MASK, to specify the extended capabilities per + * interface type. + * + * @NL80211_ATTR_MU_MIMO_GROUP_DATA: array of 24 bytes that defines a MU-MIMO + * groupID for monitor mode. + * The first 8 bytes are a mask that defines the membership in each + * group (there are 64 groups, group 0 and 63 are reserved), + * each bit represents a group and set to 1 for being a member in + * that group and 0 for not being a member. + * The remaining 16 bytes define the position in each group: 2 bits for + * each group. + * (smaller group numbers represented on most significant bits and bigger + * group numbers on least significant bits.) + * This attribute is used only if all interfaces are in monitor mode. + * Set this attribute in order to monitor packets using the given MU-MIMO + * groupID data. + * to turn off that feature set all the bits of the groupID to zero. + * @NL80211_ATTR_MU_MIMO_FOLLOW_MAC_ADDR: mac address for the sniffer to follow + * when using MU-MIMO air sniffer. + * to turn that feature off set an invalid mac address + * (e.g. FF:FF:FF:FF:FF:FF) + * + * @NL80211_ATTR_SCAN_START_TIME_TSF: The time at which the scan was actually + * started (u64). The time is the TSF of the BSS the interface that + * requested the scan is connected to (if available, otherwise this + * attribute must not be included). + * @NL80211_ATTR_SCAN_START_TIME_TSF_BSSID: The BSS according to which + * %NL80211_ATTR_SCAN_START_TIME_TSF is set. + * @NL80211_ATTR_MEASUREMENT_DURATION: measurement duration in TUs (u16). If + * %NL80211_ATTR_MEASUREMENT_DURATION_MANDATORY is not set, this is the + * maximum measurement duration allowed. This attribute is used with + * measurement requests. It can also be used with %NL80211_CMD_TRIGGER_SCAN + * if the scan is used for beacon report radio measurement. + * @NL80211_ATTR_MEASUREMENT_DURATION_MANDATORY: flag attribute that indicates + * that the duration specified with %NL80211_ATTR_MEASUREMENT_DURATION is + * mandatory. If this flag is not set, the duration is the maximum duration + * and the actual measurement duration may be shorter. + * + * @NL80211_ATTR_MESH_PEER_AID: Association ID for the mesh peer (u16). This is + * used to pull the stored data for mesh peer in power save state. + * + * @NL80211_ATTR_NAN_MASTER_PREF: the master preference to be used by + * %NL80211_CMD_START_NAN and optionally with + * %NL80211_CMD_CHANGE_NAN_CONFIG. Its type is u8 and it can't be 0. + * Also, values 1 and 255 are reserved for certification purposes and + * should not be used during a normal device operation. + * @NL80211_ATTR_NAN_DUAL: NAN dual band operation config (see + * &enum nl80211_nan_dual_band_conf). This attribute is used with + * %NL80211_CMD_START_NAN and optionally with + * %NL80211_CMD_CHANGE_NAN_CONFIG. + * @NL80211_ATTR_NAN_FUNC: a function that can be added to NAN. See + * &enum nl80211_nan_func_attributes for description of this nested + * attribute. + * @NL80211_ATTR_NAN_MATCH: used to report a match. This is a nested attribute. + * See &enum nl80211_nan_match_attributes. + * @NL80211_ATTR_FILS_KEK: KEK for FILS (Re)Association Request/Response frame + * protection. + * @NL80211_ATTR_FILS_NONCES: Nonces (part of AAD) for FILS (Re)Association + * Request/Response frame protection. This attribute contains the 16 octet + * STA Nonce followed by 16 octets of AP Nonce. + * + * @NL80211_ATTR_MULTICAST_TO_UNICAST_ENABLED: Indicates whether or not multicast + * packets should be send out as unicast to all stations (flag attribute). + * + * @NL80211_ATTR_BSSID: The BSSID of the AP. Note that %NL80211_ATTR_MAC is also + * used in various commands/events for specifying the BSSID. + * + * @NL80211_ATTR_SCHED_SCAN_RELATIVE_RSSI: Relative RSSI threshold by which + * other BSSs has to be better or slightly worse than the current + * connected BSS so that they get reported to user space. + * This will give an opportunity to userspace to consider connecting to + * other matching BSSs which have better or slightly worse RSSI than + * the current connected BSS by using an offloaded operation to avoid + * unnecessary wakeups. + * + * @NL80211_ATTR_SCHED_SCAN_RSSI_ADJUST: When present the RSSI level for BSSs in + * the specified band is to be adjusted before doing + * %NL80211_ATTR_SCHED_SCAN_RELATIVE_RSSI based comparision to figure out + * better BSSs. The attribute value is a packed structure + * value as specified by &struct nl80211_bss_select_rssi_adjust. + * + * @NL80211_ATTR_TIMEOUT_REASON: The reason for which an operation timed out. + * u32 attribute with an &enum nl80211_timeout_reason value. This is used, + * e.g., with %NL80211_CMD_CONNECT event. + * + * @NL80211_ATTR_FILS_ERP_USERNAME: EAP Re-authentication Protocol (ERP) + * username part of NAI used to refer keys rRK and rIK. This is used with + * %NL80211_CMD_CONNECT. + * + * @NL80211_ATTR_FILS_ERP_REALM: EAP Re-authentication Protocol (ERP) realm part + * of NAI specifying the domain name of the ER server. This is used with + * %NL80211_CMD_CONNECT. + * + * @NL80211_ATTR_FILS_ERP_NEXT_SEQ_NUM: Unsigned 16-bit ERP next sequence number + * to use in ERP messages. This is used in generating the FILS wrapped data + * for FILS authentication and is used with %NL80211_CMD_CONNECT. + * + * @NL80211_ATTR_FILS_ERP_RRK: ERP re-authentication Root Key (rRK) for the + * NAI specified by %NL80211_ATTR_FILS_ERP_USERNAME and + * %NL80211_ATTR_FILS_ERP_REALM. This is used for generating rIK and rMSK + * from successful FILS authentication and is used with + * %NL80211_CMD_CONNECT. + * + * @NL80211_ATTR_FILS_CACHE_ID: A 2-octet identifier advertized by a FILS AP + * identifying the scope of PMKSAs. This is used with + * @NL80211_CMD_SET_PMKSA and @NL80211_CMD_DEL_PMKSA. + * + * @NL80211_ATTR_PMK: PMK for the PMKSA identified by %NL80211_ATTR_PMKID. + * This is used with @NL80211_CMD_SET_PMKSA. * * @NUM_NL80211_ATTR: total number of nl80211_attrs available * @NL80211_ATTR_MAX: highest attribute number currently defined @@ -2041,7 +2292,7 @@ NL80211_ATTR_CONN_FAILED_REASON, - NL80211_ATTR_SAE_DATA, + NL80211_ATTR_AUTH_DATA, NL80211_ATTR_VHT_CAPABILITY, @@ -2157,6 +2408,51 @@ NL80211_ATTR_MAX_SCAN_PLAN_ITERATIONS, NL80211_ATTR_SCHED_SCAN_PLANS, + NL80211_ATTR_PBSS, + + NL80211_ATTR_BSS_SELECT, + + NL80211_ATTR_STA_SUPPORT_P2P_PS, + + NL80211_ATTR_PAD, + + NL80211_ATTR_IFTYPE_EXT_CAPA, + + NL80211_ATTR_MU_MIMO_GROUP_DATA, + NL80211_ATTR_MU_MIMO_FOLLOW_MAC_ADDR, + + NL80211_ATTR_SCAN_START_TIME_TSF, + NL80211_ATTR_SCAN_START_TIME_TSF_BSSID, + NL80211_ATTR_MEASUREMENT_DURATION, + NL80211_ATTR_MEASUREMENT_DURATION_MANDATORY, + + NL80211_ATTR_MESH_PEER_AID, + + NL80211_ATTR_NAN_MASTER_PREF, + NL80211_ATTR_NAN_DUAL, + NL80211_ATTR_NAN_FUNC, + NL80211_ATTR_NAN_MATCH, + + NL80211_ATTR_FILS_KEK, + NL80211_ATTR_FILS_NONCES, + + NL80211_ATTR_MULTICAST_TO_UNICAST_ENABLED, + + NL80211_ATTR_BSSID, + + NL80211_ATTR_SCHED_SCAN_RELATIVE_RSSI, + NL80211_ATTR_SCHED_SCAN_RSSI_ADJUST, + + NL80211_ATTR_TIMEOUT_REASON, + + NL80211_ATTR_FILS_ERP_USERNAME, + NL80211_ATTR_FILS_ERP_REALM, + NL80211_ATTR_FILS_ERP_NEXT_SEQ_NUM, + NL80211_ATTR_FILS_ERP_RRK, + NL80211_ATTR_FILS_CACHE_ID, + + NL80211_ATTR_PMK, + /* add attributes here, update the policy in nl80211.c */ __NL80211_ATTR_AFTER_LAST, @@ -2168,6 +2464,7 @@ #define NL80211_ATTR_SCAN_GENERATION NL80211_ATTR_GENERATION #define NL80211_ATTR_MESH_PARAMS NL80211_ATTR_MESH_CONFIG #define NL80211_ATTR_IFACE_SOCKET_OWNER NL80211_ATTR_SOCKET_OWNER +#define NL80211_ATTR_SAE_DATA NL80211_ATTR_AUTH_DATA /* * Allow user space programs to use #ifdef on new attributes by defining them @@ -2825,6 +3122,13 @@ * how this API was implemented in the past. Also, due to the same problem, * the only way to create a matchset with only an RSSI filter (with this * attribute) is if there's only a single matchset with the RSSI attribute. + * @NL80211_SCHED_SCAN_MATCH_ATTR_RELATIVE_RSSI: Flag indicating whether + * %NL80211_SCHED_SCAN_MATCH_ATTR_RSSI to be used as absolute RSSI or + * relative to current bss's RSSI. + * @NL80211_SCHED_SCAN_MATCH_ATTR_RSSI_ADJUST: When present the RSSI level for + * BSS-es in the specified band is to be adjusted before doing + * RSSI-based BSS selection. The attribute value is a packed structure + * value as specified by &struct nl80211_bss_select_rssi_adjust. * @NL80211_SCHED_SCAN_MATCH_ATTR_MAX: highest scheduled scan filter * attribute number currently defined * @__NL80211_SCHED_SCAN_MATCH_ATTR_AFTER_LAST: internal use @@ -2834,6 +3138,8 @@ NL80211_SCHED_SCAN_MATCH_ATTR_SSID, NL80211_SCHED_SCAN_MATCH_ATTR_RSSI, + NL80211_SCHED_SCAN_MATCH_ATTR_RELATIVE_RSSI, + NL80211_SCHED_SCAN_MATCH_ATTR_RSSI_ADJUST, /* keep last */ __NL80211_SCHED_SCAN_MATCH_ATTR_AFTER_LAST, @@ -3446,6 +3752,9 @@ * @NL80211_AUTHTYPE_FT: Fast BSS Transition (IEEE 802.11r) * @NL80211_AUTHTYPE_NETWORK_EAP: Network EAP (some Cisco APs and mainly LEAP) * @NL80211_AUTHTYPE_SAE: Simultaneous authentication of equals + * @NL80211_AUTHTYPE_FILS_SK: Fast Initial Link Setup shared key + * @NL80211_AUTHTYPE_FILS_SK_PFS: Fast Initial Link Setup shared key with PFS + * @NL80211_AUTHTYPE_FILS_PK: Fast Initial Link Setup public key * @__NL80211_AUTHTYPE_NUM: internal * @NL80211_AUTHTYPE_MAX: maximum valid auth algorithm * @NL80211_AUTHTYPE_AUTOMATIC: determine automatically (if necessary by @@ -3458,6 +3767,9 @@ NL80211_AUTHTYPE_FT, NL80211_AUTHTYPE_NETWORK_EAP, NL80211_AUTHTYPE_SAE, + NL80211_AUTHTYPE_FILS_SK, + NL80211_AUTHTYPE_FILS_SK_PFS, + NL80211_AUTHTYPE_FILS_PK, /* keep last */ __NL80211_AUTHTYPE_NUM, @@ -3621,7 +3933,10 @@ * @__NL80211_ATTR_CQM_INVALID: invalid * @NL80211_ATTR_CQM_RSSI_THOLD: RSSI threshold in dBm. This value specifies * the threshold for the RSSI level at which an event will be sent. Zero - * to disable. + * to disable. Alternatively, if %NL80211_EXT_FEATURE_CQM_RSSI_LIST is + * set, multiple values can be supplied as a low-to-high sorted array of + * threshold values in dBm. Events will be sent when the RSSI value + * crosses any of the thresholds. * @NL80211_ATTR_CQM_RSSI_HYST: RSSI hysteresis in dBm. This value specifies * the minimum amount the RSSI level must change after an event before a * new event may be issued (to reduce effects of RSSI oscillation). @@ -4062,6 +4377,9 @@ * of supported channel widths for radar detection. * @NL80211_IFACE_COMB_RADAR_DETECT_REGIONS: u32 attribute containing the bitmap * of supported regulatory regions for radar detection. + * @NL80211_IFACE_COMB_BI_MIN_GCD: u32 attribute specifying the minimum GCD of + * different beacon intervals supported by all the interface combinations + * in this group (if not present, all beacon intervals be identical). * @NUM_NL80211_IFACE_COMB: number of attributes * @MAX_NL80211_IFACE_COMB: highest attribute number * @@ -4069,8 +4387,8 @@ * limits = [ #{STA} <= 1, #{AP} <= 1 ], matching BI, channels = 1, max = 2 * => allows an AP and a STA that must match BIs * - * numbers = [ #{AP, P2P-GO} <= 8 ], channels = 1, max = 8 - * => allows 8 of AP/GO + * numbers = [ #{AP, P2P-GO} <= 8 ], BI min gcd, channels = 1, max = 8, + * => allows 8 of AP/GO that can have BI gcd >= min gcd * * numbers = [ #{STA} <= 2 ], channels = 2, max = 2 * => allows two STAs on different channels @@ -4096,6 +4414,7 @@ NL80211_IFACE_COMB_NUM_CHANNELS, NL80211_IFACE_COMB_RADAR_DETECT_WIDTHS, NL80211_IFACE_COMB_RADAR_DETECT_REGIONS, + NL80211_IFACE_COMB_BI_MIN_GCD, /* keep last */ NUM_NL80211_IFACE_COMB, @@ -4389,12 +4708,67 @@ /** * enum nl80211_ext_feature_index - bit index of extended features. * @NL80211_EXT_FEATURE_VHT_IBSS: This driver supports IBSS with VHT datarates. + * @NL80211_EXT_FEATURE_RRM: This driver supports RRM. When featured, user can + * can request to use RRM (see %NL80211_ATTR_USE_RRM) with + * %NL80211_CMD_ASSOCIATE and %NL80211_CMD_CONNECT requests, which will set + * the ASSOC_REQ_USE_RRM flag in the association request even if + * NL80211_FEATURE_QUIET is not advertized. + * @NL80211_EXT_FEATURE_MU_MIMO_AIR_SNIFFER: This device supports MU-MIMO air + * sniffer which means that it can be configured to hear packets from + * certain groups which can be configured by the + * %NL80211_ATTR_MU_MIMO_GROUP_DATA attribute, + * or can be configured to follow a station by configuring the + * %NL80211_ATTR_MU_MIMO_FOLLOW_MAC_ADDR attribute. + * @NL80211_EXT_FEATURE_SCAN_START_TIME: This driver includes the actual + * time the scan started in scan results event. The time is the TSF of + * the BSS that the interface that requested the scan is connected to + * (if available). + * @NL80211_EXT_FEATURE_BSS_PARENT_TSF: Per BSS, this driver reports the + * time the last beacon/probe was received. The time is the TSF of the + * BSS that the interface that requested the scan is connected to + * (if available). + * @NL80211_EXT_FEATURE_SET_SCAN_DWELL: This driver supports configuration of + * channel dwell time. + * @NL80211_EXT_FEATURE_BEACON_RATE_LEGACY: Driver supports beacon rate + * configuration (AP/mesh), supporting a legacy (non HT/VHT) rate. + * @NL80211_EXT_FEATURE_BEACON_RATE_HT: Driver supports beacon rate + * configuration (AP/mesh) with HT rates. + * @NL80211_EXT_FEATURE_BEACON_RATE_VHT: Driver supports beacon rate + * configuration (AP/mesh) with VHT rates. + * @NL80211_EXT_FEATURE_FILS_STA: This driver supports Fast Initial Link Setup + * with user space SME (NL80211_CMD_AUTHENTICATE) in station mode. + * @NL80211_EXT_FEATURE_MGMT_TX_RANDOM_TA: This driver supports randomized TA + * in @NL80211_CMD_FRAME while not associated. + * @NL80211_EXT_FEATURE_MGMT_TX_RANDOM_TA_CONNECTED: This driver supports + * randomized TA in @NL80211_CMD_FRAME while associated. + * @NL80211_EXT_FEATURE_SCHED_SCAN_RELATIVE_RSSI: The driver supports sched_scan + * for reporting BSSs with better RSSI than the current connected BSS + * (%NL80211_ATTR_SCHED_SCAN_RELATIVE_RSSI). + * @NL80211_EXT_FEATURE_CQM_RSSI_LIST: With this driver the + * %NL80211_ATTR_CQM_RSSI_THOLD attribute accepts a list of zero or more + * RSSI threshold values to monitor rather than exactly one threshold. + * @NL80211_EXT_FEATURE_FILS_SK_OFFLOAD: Driver SME supports FILS shared key + * authentication with %NL80211_CMD_CONNECT. * * @NUM_NL80211_EXT_FEATURES: number of extended features. * @MAX_NL80211_EXT_FEATURES: highest extended feature index. */ enum nl80211_ext_feature_index { NL80211_EXT_FEATURE_VHT_IBSS, + NL80211_EXT_FEATURE_RRM, + NL80211_EXT_FEATURE_MU_MIMO_AIR_SNIFFER, + NL80211_EXT_FEATURE_SCAN_START_TIME, + NL80211_EXT_FEATURE_BSS_PARENT_TSF, + NL80211_EXT_FEATURE_SET_SCAN_DWELL, + NL80211_EXT_FEATURE_BEACON_RATE_LEGACY, + NL80211_EXT_FEATURE_BEACON_RATE_HT, + NL80211_EXT_FEATURE_BEACON_RATE_VHT, + NL80211_EXT_FEATURE_FILS_STA, + NL80211_EXT_FEATURE_MGMT_TX_RANDOM_TA, + NL80211_EXT_FEATURE_MGMT_TX_RANDOM_TA_CONNECTED, + NL80211_EXT_FEATURE_SCHED_SCAN_RELATIVE_RSSI, + NL80211_EXT_FEATURE_CQM_RSSI_LIST, + NL80211_EXT_FEATURE_FILS_SK_OFFLOAD, /* add new features before the definition below */ NUM_NL80211_EXT_FEATURES, @@ -4434,6 +4808,21 @@ }; /** + * enum nl80211_timeout_reason - timeout reasons + * + * @NL80211_TIMEOUT_UNSPECIFIED: Timeout reason unspecified. + * @NL80211_TIMEOUT_SCAN: Scan (AP discovery) timed out. + * @NL80211_TIMEOUT_AUTH: Authentication timed out. + * @NL80211_TIMEOUT_ASSOC: Association timed out. + */ +enum nl80211_timeout_reason { + NL80211_TIMEOUT_UNSPECIFIED, + NL80211_TIMEOUT_SCAN, + NL80211_TIMEOUT_AUTH, + NL80211_TIMEOUT_ASSOC, +}; + +/** * enum nl80211_scan_flags - scan request control flags * * Scan request control flags are used to control the handling @@ -4515,12 +4904,17 @@ * change to the channel status. * @NL80211_RADAR_NOP_FINISHED: The Non-Occupancy Period for this channel is * over, channel becomes usable. + * @NL80211_RADAR_PRE_CAC_EXPIRED: Channel Availability Check done on this + * non-operating channel is expired and no longer valid. New CAC must + * be done on this channel before starting the operation. This is not + * applicable for ETSI dfs domain where pre-CAC is valid for ever. */ enum nl80211_radar_event { NL80211_RADAR_DETECTED, NL80211_RADAR_CAC_FINISHED, NL80211_RADAR_CAC_ABORTED, NL80211_RADAR_NOP_FINISHED, + NL80211_RADAR_PRE_CAC_EXPIRED, }; /** @@ -4644,4 +5038,48 @@ __NL80211_SCHED_SCAN_PLAN_AFTER_LAST - 1 }; +/** + * struct nl80211_bss_select_rssi_adjust - RSSI adjustment parameters. + * + * @band: band of BSS that must match for RSSI value adjustment. + * @delta: value used to adjust the RSSI value of matching BSS. + */ +struct nl80211_bss_select_rssi_adjust { + __u8 band; + __s8 delta; +} __attribute__((packed)); + +/** + * enum nl80211_bss_select_attr - attributes for bss selection. + * + * @__NL80211_BSS_SELECT_ATTR_INVALID: reserved. + * @NL80211_BSS_SELECT_ATTR_RSSI: Flag indicating only RSSI-based BSS selection + * is requested. + * @NL80211_BSS_SELECT_ATTR_BAND_PREF: attribute indicating BSS + * selection should be done such that the specified band is preferred. + * When there are multiple BSS-es in the preferred band, the driver + * shall use RSSI-based BSS selection as a second step. The value of + * this attribute is according to &enum nl80211_band (u32). + * @NL80211_BSS_SELECT_ATTR_RSSI_ADJUST: When present the RSSI level for + * BSS-es in the specified band is to be adjusted before doing + * RSSI-based BSS selection. The attribute value is a packed structure + * value as specified by &struct nl80211_bss_select_rssi_adjust. + * @NL80211_BSS_SELECT_ATTR_MAX: highest bss select attribute number. + * @__NL80211_BSS_SELECT_ATTR_AFTER_LAST: internal use. + * + * One and only one of these attributes are found within %NL80211_ATTR_BSS_SELECT + * for %NL80211_CMD_CONNECT. It specifies the required BSS selection behaviour + * which the driver shall use. + */ +enum nl80211_bss_select_attr { + __NL80211_BSS_SELECT_ATTR_INVALID, + NL80211_BSS_SELECT_ATTR_RSSI, + NL80211_BSS_SELECT_ATTR_BAND_PREF, + NL80211_BSS_SELECT_ATTR_RSSI_ADJUST, + + /* keep last */ + __NL80211_BSS_SELECT_ATTR_AFTER_LAST, + NL80211_BSS_SELECT_ATTR_MAX = __NL80211_BSS_SELECT_ATTR_AFTER_LAST - 1 +}; + #endif /* __LINUX_NL80211_H */ diff -ruw linux-4.4.115/include/uapi/linux/perf_event.h linux-4.4.115-fbx/include/uapi/linux/perf_event.h --- linux-4.4.115/include/uapi/linux/perf_event.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/uapi/linux/perf_event.h 2019-01-22 16:16:28.583292409 +0100 @@ -334,7 +334,9 @@ comm_exec : 1, /* flag comm events that are due to an exec */ use_clockid : 1, /* use @clockid for time fields */ context_switch : 1, /* context switch data */ - __reserved_1 : 37; + constraint_duplicate : 1, + + __reserved_1 : 36; union { __u32 wakeup_events; /* wakeup every n events */ @@ -395,6 +397,7 @@ #define PERF_EVENT_IOC_SET_FILTER _IOW('$', 6, char *) #define PERF_EVENT_IOC_ID _IOR('$', 7, __u64 *) #define PERF_EVENT_IOC_SET_BPF _IOW('$', 8, __u32) +#define PERF_EVENT_IOC_SET_DRV_CONFIGS _IOW('$', 10, char *) enum perf_event_ioc_flags { PERF_IOC_FLAG_GROUP = 1U << 0, diff -ruw linux-4.4.115/include/uapi/linux/pkt_sched.h linux-4.4.115-fbx/include/uapi/linux/pkt_sched.h --- linux-4.4.115/include/uapi/linux/pkt_sched.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/uapi/linux/pkt_sched.h 2019-01-22 16:16:28.583292409 +0100 @@ -126,6 +126,7 @@ struct tc_prio_qopt { int bands; /* Number of bands */ __u8 priomap[TC_PRIO_MAX+1]; /* Map: logical priority -> PRIO band */ + __u8 enable_flow; /* Enable dequeue */ }; /* MULTIQ section */ diff -ruw linux-4.4.115/include/uapi/linux/prctl.h linux-4.4.115-fbx/include/uapi/linux/prctl.h --- linux-4.4.115/include/uapi/linux/prctl.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/uapi/linux/prctl.h 2019-10-29 09:26:25.553221870 +0100 @@ -197,4 +197,13 @@ # define PR_CAP_AMBIENT_LOWER 3 # define PR_CAP_AMBIENT_CLEAR_ALL 4 +/* Sets the timerslack for arbitrary threads + * arg2 slack value, 0 means "use default" + * arg3 pid of the thread whose timer slack needs to be set + */ +#define PR_SET_TIMERSLACK_PID 127 + +#define PR_SET_VMA 0x53564d41 +# define PR_SET_VMA_ANON_NAME 0 + #endif /* _LINUX_PRCTL_H */ diff -ruw linux-4.4.115/include/uapi/linux/rtnetlink.h linux-4.4.115-fbx/include/uapi/linux/rtnetlink.h --- linux-4.4.115/include/uapi/linux/rtnetlink.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/uapi/linux/rtnetlink.h 2019-01-22 16:16:28.587292445 +0100 @@ -311,6 +311,9 @@ RTA_PREF, RTA_ENCAP_TYPE, RTA_ENCAP, + RTA_EXPIRES, + RTA_PAD, + RTA_UID, __RTA_MAX }; diff -ruw linux-4.4.115/include/uapi/linux/sock_diag.h linux-4.4.115-fbx/include/uapi/linux/sock_diag.h --- linux-4.4.115/include/uapi/linux/sock_diag.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/uapi/linux/sock_diag.h 2019-01-22 16:16:28.587292445 +0100 @@ -4,6 +4,7 @@ #include #define SOCK_DIAG_BY_FAMILY 20 +#define SOCK_DESTROY_BACKPORT 21 struct sock_diag_req { __u8 sdiag_family; diff -ruw linux-4.4.115/include/uapi/linux/sockios.h linux-4.4.115-fbx/include/uapi/linux/sockios.h --- linux-4.4.115/include/uapi/linux/sockios.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/uapi/linux/sockios.h 2019-01-22 16:16:28.587292445 +0100 @@ -65,6 +65,7 @@ #define SIOCDIFADDR 0x8936 /* delete PA address */ #define SIOCSIFHWBROADCAST 0x8937 /* set hardware broadcast addr */ #define SIOCGIFCOUNT 0x8938 /* get number of devices */ +#define SIOCKILLADDR 0x8939 /* kill sockets with this local addr */ #define SIOCGIFBR 0x8940 /* Bridging support */ #define SIOCSIFBR 0x8941 /* Set bridging options */ diff -ruw linux-4.4.115/include/uapi/linux/sysctl.h linux-4.4.115-fbx/include/uapi/linux/sysctl.h --- linux-4.4.115/include/uapi/linux/sysctl.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/uapi/linux/sysctl.h 2019-01-22 16:16:28.591292481 +0100 @@ -154,6 +154,7 @@ KERN_NMI_WATCHDOG=75, /* int: enable/disable nmi watchdog */ KERN_PANIC_ON_NMI=76, /* int: whether we will panic on an unrecovered */ KERN_PANIC_ON_WARN=77, /* int: call panic() in WARN() functions */ + KERN_COLD_BOOT = 78, /* int: identify if system cold booted */ }; @@ -482,6 +483,7 @@ NET_IPV4_CONF_PROMOTE_SECONDARIES=20, NET_IPV4_CONF_ARP_ACCEPT=21, NET_IPV4_CONF_ARP_NOTIFY=22, + NET_IPV4_CONF_NF_IPV4_DEFRAG_SKIP = 23, }; /* /proc/sys/net/ipv4/netfilter */ @@ -570,6 +572,7 @@ NET_IPV6_PROXY_NDP=23, NET_IPV6_ACCEPT_SOURCE_ROUTE=25, NET_IPV6_ACCEPT_RA_FROM_LOCAL=26, + NET_IPV6_ACCEPT_RA_RT_INFO_MIN_PLEN=27, __NET_IPV6_MAX }; diff -ruw linux-4.4.115/include/uapi/linux/tcp.h linux-4.4.115-fbx/include/uapi/linux/tcp.h --- linux-4.4.115/include/uapi/linux/tcp.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/uapi/linux/tcp.h 2019-01-22 16:16:28.591292481 +0100 @@ -116,6 +116,8 @@ #define TCP_SAVE_SYN 27 /* Record SYN headers for new connections */ #define TCP_SAVED_SYN 28 /* Get SYN headers recorded for connection */ +#define TCP_LINEAR_RTO 128 /* force use of linear timeouts */ + struct tcp_repair_opt { __u32 opt_code; __u32 opt_val; @@ -157,6 +159,7 @@ __u8 tcpi_backoff; __u8 tcpi_options; __u8 tcpi_snd_wscale : 4, tcpi_rcv_wscale : 4; + __u8 tcpi_count; __u32 tcpi_rto; __u32 tcpi_ato; diff -ruw linux-4.4.115/include/uapi/linux/time.h linux-4.4.115-fbx/include/uapi/linux/time.h --- linux-4.4.115/include/uapi/linux/time.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/uapi/linux/time.h 2019-10-29 09:26:25.553221870 +0100 @@ -56,6 +56,7 @@ #define CLOCK_BOOTTIME_ALARM 9 #define CLOCK_SGI_CYCLE 10 /* Hardware specific */ #define CLOCK_TAI 11 +#define CLOCK_POWEROFF_ALARM 12 #define MAX_CLOCKS 16 #define CLOCKS_MASK (CLOCK_REALTIME | CLOCK_MONOTONIC) diff -ruw linux-4.4.115/include/uapi/linux/usb/audio.h linux-4.4.115-fbx/include/uapi/linux/usb/audio.h --- linux-4.4.115/include/uapi/linux/usb/audio.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/uapi/linux/usb/audio.h 2019-10-29 09:26:25.553221870 +0100 @@ -26,6 +26,7 @@ /* bInterfaceProtocol values to denote the version of the standard used */ #define UAC_VERSION_1 0x00 #define UAC_VERSION_2 0x20 +#define UAC_VERSION_3 0x30 /* A.2 Audio Interface Subclass Codes */ #define USB_SUBCLASS_AUDIOCONTROL 0x01 diff -ruw linux-4.4.115/include/uapi/linux/usb/cdc.h linux-4.4.115-fbx/include/uapi/linux/usb/cdc.h --- linux-4.4.115/include/uapi/linux/usb/cdc.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/uapi/linux/usb/cdc.h 2019-01-22 16:16:28.595292518 +0100 @@ -231,6 +231,7 @@ #define USB_CDC_SEND_ENCAPSULATED_COMMAND 0x00 #define USB_CDC_GET_ENCAPSULATED_RESPONSE 0x01 +#define USB_CDC_RESET_FUNCTION 0x05 #define USB_CDC_REQ_SET_LINE_CODING 0x20 #define USB_CDC_REQ_GET_LINE_CODING 0x21 #define USB_CDC_REQ_SET_CONTROL_LINE_STATE 0x22 diff -ruw linux-4.4.115/include/uapi/linux/usb/ch9.h linux-4.4.115-fbx/include/uapi/linux/usb/ch9.h --- linux-4.4.115/include/uapi/linux/usb/ch9.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/uapi/linux/usb/ch9.h 2019-01-22 16:16:28.595292518 +0100 @@ -909,6 +909,30 @@ } __attribute__((packed)); /* + * Configuration Summary descriptors: Defines a list of functions in the + * configuration. This descriptor may be used by Host software to decide + * which Configuration to use to obtain the desired functionality. + */ +#define USB_CAP_TYPE_CONFIG_SUMMARY 0x10 + +struct function_class_info { + __u8 bClass; + __u8 bSubClass; + __u8 bProtocol; +}; + +struct usb_config_summary_descriptor { + __u8 bLength; + __u8 bDescriptorType; + __u8 bDevCapabilityType; + __u16 bcdVersion; + __u8 bConfigurationValue; + __u8 bMaxPower; + __u8 bNumFunctions; + struct function_class_info cs_info[]; +} __attribute__((packed)); + +/* * The size of the descriptor for the Sublink Speed Attribute Count * (SSAC) specified in bmAttributes[4:0]. */ diff -ruw linux-4.4.115/include/uapi/linux/usb/Kbuild linux-4.4.115-fbx/include/uapi/linux/usb/Kbuild --- linux-4.4.115/include/uapi/linux/usb/Kbuild 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/uapi/linux/usb/Kbuild 2019-01-22 16:16:28.595292518 +0100 @@ -9,4 +9,5 @@ header-y += gadgetfs.h header-y += midi.h header-y += tmc.h +header-y += usb_ctrl_qti.h header-y += video.h diff -ruw linux-4.4.115/include/uapi/linux/v4l2-controls.h linux-4.4.115-fbx/include/uapi/linux/v4l2-controls.h --- linux-4.4.115/include/uapi/linux/v4l2-controls.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/uapi/linux/v4l2-controls.h 2019-01-22 16:16:28.595292518 +0100 @@ -369,6 +369,7 @@ enum v4l2_mpeg_video_header_mode { V4L2_MPEG_VIDEO_HEADER_MODE_SEPARATE = 0, V4L2_MPEG_VIDEO_HEADER_MODE_JOINED_WITH_1ST_FRAME = 1, + V4L2_MPEG_VIDEO_HEADER_MODE_JOINED_WITH_I_FRAME = 2, }; #define V4L2_CID_MPEG_VIDEO_MAX_REF_PIC (V4L2_CID_MPEG_BASE+217) @@ -380,6 +381,7 @@ V4L2_MPEG_VIDEO_MULTI_SLICE_MODE_SINGLE = 0, V4L2_MPEG_VIDEO_MULTI_SICE_MODE_MAX_MB = 1, V4L2_MPEG_VIDEO_MULTI_SICE_MODE_MAX_BYTES = 2, + V4L2_MPEG_VIDEO_MULTI_SLICE_GOB = 3, }; #define V4L2_CID_MPEG_VIDEO_VBV_SIZE (V4L2_CID_MPEG_BASE+222) #define V4L2_CID_MPEG_VIDEO_DEC_PTS (V4L2_CID_MPEG_BASE+223) @@ -425,6 +427,7 @@ V4L2_MPEG_VIDEO_H264_LEVEL_4_2 = 13, V4L2_MPEG_VIDEO_H264_LEVEL_5_0 = 14, V4L2_MPEG_VIDEO_H264_LEVEL_5_1 = 15, + V4L2_MPEG_VIDEO_H264_LEVEL_5_2 = 16, }; #define V4L2_CID_MPEG_VIDEO_H264_LOOP_FILTER_ALPHA (V4L2_CID_MPEG_BASE+360) #define V4L2_CID_MPEG_VIDEO_H264_LOOP_FILTER_BETA (V4L2_CID_MPEG_BASE+361) @@ -453,6 +456,7 @@ V4L2_MPEG_VIDEO_H264_PROFILE_SCALABLE_HIGH_INTRA = 14, V4L2_MPEG_VIDEO_H264_PROFILE_STEREO_HIGH = 15, V4L2_MPEG_VIDEO_H264_PROFILE_MULTIVIEW_HIGH = 16, + V4L2_MPEG_VIDEO_H264_PROFILE_CONSTRAINED_HIGH = 17, }; #define V4L2_CID_MPEG_VIDEO_H264_VUI_EXT_SAR_HEIGHT (V4L2_CID_MPEG_BASE+364) #define V4L2_CID_MPEG_VIDEO_H264_VUI_EXT_SAR_WIDTH (V4L2_CID_MPEG_BASE+365) @@ -644,6 +648,590 @@ #define V4L2_CID_MPEG_MFC51_VIDEO_H264_ADAPTIVE_RC_STATIC (V4L2_CID_MPEG_MFC51_BASE+53) #define V4L2_CID_MPEG_MFC51_VIDEO_H264_NUM_REF_PIC_FOR_P (V4L2_CID_MPEG_MFC51_BASE+54) +/* MPEG-class control IDs specific to the msm_vidc driver */ +#define V4L2_CID_MPEG_MSM_VIDC_BASE (V4L2_CTRL_CLASS_MPEG | 0x2000) + +#define V4L2_CID_MPEG_VIDC_VIDEO_PICTYPE_DEC_MODE \ + (V4L2_CID_MPEG_MSM_VIDC_BASE+0) +enum v4l2_mpeg_vidc_video_pictype_dec_mode { + V4L2_MPEG_VIDC_VIDEO_PICTYPE_DECODE_OFF = 0, + V4L2_MPEG_VIDC_VIDEO_PICTYPE_DECODE_ON = 1, +}; + +#define V4L2_CID_MPEG_VIDC_VIDEO_KEEP_ASPECT_RATIO \ + (V4L2_CID_MPEG_MSM_VIDC_BASE+1) +#define V4L2_CID_MPEG_VIDC_VIDEO_POST_LOOP_DEBLOCKER_MODE \ + (V4L2_CID_MPEG_MSM_VIDC_BASE+2) +#define V4L2_CID_MPEG_VIDC_VIDEO_DIVX_FORMAT \ + (V4L2_CID_MPEG_MSM_VIDC_BASE+3) +enum v4l2_mpeg_vidc_video_divx_format_type { + V4L2_MPEG_VIDC_VIDEO_DIVX_FORMAT_4 = 0, + V4L2_MPEG_VIDC_VIDEO_DIVX_FORMAT_5 = 1, + V4L2_MPEG_VIDC_VIDEO_DIVX_FORMAT_6 = 2, +}; +#define V4L2_CID_MPEG_VIDC_VIDEO_MB_ERROR_MAP_REPORTING \ + (V4L2_CID_MPEG_MSM_VIDC_BASE+4) +#define V4L2_CID_MPEG_VIDC_VIDEO_CONTINUE_DATA_TRANSFER \ + (V4L2_CID_MPEG_MSM_VIDC_BASE+5) + +#define V4L2_CID_MPEG_VIDC_VIDEO_STREAM_FORMAT (V4L2_CID_MPEG_MSM_VIDC_BASE+6) +enum v4l2_mpeg_vidc_video_stream_format { + V4L2_MPEG_VIDC_VIDEO_NAL_FORMAT_STARTCODES = 0, + V4L2_MPEG_VIDC_VIDEO_NAL_FORMAT_ONE_NAL_PER_BUFFER = 1, + V4L2_MPEG_VIDC_VIDEO_NAL_FORMAT_ONE_BYTE_LENGTH = 2, + V4L2_MPEG_VIDC_VIDEO_NAL_FORMAT_TWO_BYTE_LENGTH = 3, + V4L2_MPEG_VIDC_VIDEO_NAL_FORMAT_FOUR_BYTE_LENGTH = 4, +}; + +#define V4L2_CID_MPEG_VIDC_VIDEO_OUTPUT_ORDER (V4L2_CID_MPEG_MSM_VIDC_BASE+7) +enum v4l2_mpeg_vidc_video_output_order { + V4L2_MPEG_VIDC_VIDEO_OUTPUT_ORDER_DISPLAY = 0, + V4L2_MPEG_VIDC_VIDEO_OUTPUT_ORDER_DECODE = 1, +}; + +#define V4L2_CID_MPEG_VIDC_VIDEO_FRAME_RATE (V4L2_CID_MPEG_MSM_VIDC_BASE+8) +#define V4L2_CID_MPEG_VIDC_VIDEO_IDR_PERIOD (V4L2_CID_MPEG_MSM_VIDC_BASE+9) +#define V4L2_CID_MPEG_VIDC_VIDEO_NUM_P_FRAMES (V4L2_CID_MPEG_MSM_VIDC_BASE+10) +#define V4L2_CID_MPEG_VIDC_VIDEO_NUM_B_FRAMES (V4L2_CID_MPEG_MSM_VIDC_BASE+11) +#define V4L2_CID_MPEG_VIDC_VIDEO_REQUEST_IFRAME (V4L2_CID_MPEG_MSM_VIDC_BASE+12) + +#define V4L2_CID_MPEG_VIDC_VIDEO_RATE_CONTROL (V4L2_CID_MPEG_MSM_VIDC_BASE+13) +enum v4l2_mpeg_vidc_video_rate_control { + V4L2_CID_MPEG_VIDC_VIDEO_RATE_CONTROL_OFF = 0, + V4L2_CID_MPEG_VIDC_VIDEO_RATE_CONTROL_VBR_VFR = 1, + V4L2_CID_MPEG_VIDC_VIDEO_RATE_CONTROL_VBR_CFR = 2, + V4L2_CID_MPEG_VIDC_VIDEO_RATE_CONTROL_CBR_VFR = 3, + V4L2_CID_MPEG_VIDC_VIDEO_RATE_CONTROL_CBR_CFR = 4, + V4L2_CID_MPEG_VIDC_VIDEO_RATE_CONTROL_MBR_CFR = 5, + V4L2_CID_MPEG_VIDC_VIDEO_RATE_CONTROL_MBR_VFR = 6, +}; +#define V4L2_CID_MPEG_VIDC_VIDEO_RATE_CONTROL_MBR_CFR \ + V4L2_CID_MPEG_VIDC_VIDEO_RATE_CONTROL_MBR_CFR +#define V4L2_CID_MPEG_VIDC_VIDEO_RATE_CONTROL_MBR_VFR \ + V4L2_CID_MPEG_VIDC_VIDEO_RATE_CONTROL_MBR_VFR + +#define V4L2_CID_MPEG_VIDC_VIDEO_ROTATION (V4L2_CID_MPEG_MSM_VIDC_BASE+14) +enum v4l2_mpeg_vidc_video_rotation { + V4L2_CID_MPEG_VIDC_VIDEO_ROTATION_NONE = 0, + V4L2_CID_MPEG_VIDC_VIDEO_ROTATION_90 = 1, + V4L2_CID_MPEG_VIDC_VIDEO_ROTATION_180 = 2, + V4L2_CID_MPEG_VIDC_VIDEO_ROTATION_270 = 3, +}; +#define MSM_VIDC_BASE V4L2_CID_MPEG_MSM_VIDC_BASE +#define V4L2_CID_MPEG_VIDC_VIDEO_H264_CABAC_MODEL (MSM_VIDC_BASE+15) +enum v4l2_mpeg_vidc_h264_cabac_model { + V4L2_CID_MPEG_VIDC_VIDEO_H264_CABAC_MODEL_0 = 0, + V4L2_CID_MPEG_VIDC_VIDEO_H264_CABAC_MODEL_1 = 1, + V4L2_CID_MPEG_VIDC_VIDEO_H264_CABAC_MODEL_2 = 2, +}; + +#define V4L2_CID_MPEG_VIDC_VIDEO_INTRA_REFRESH_MODE (MSM_VIDC_BASE+16) +enum v4l2_mpeg_vidc_video_intra_refresh_mode { + V4L2_CID_MPEG_VIDC_VIDEO_INTRA_REFRESH_NONE = 0, + V4L2_CID_MPEG_VIDC_VIDEO_INTRA_REFRESH_CYCLIC = 1, + V4L2_CID_MPEG_VIDC_VIDEO_INTRA_REFRESH_ADAPTIVE = 2, + V4L2_CID_MPEG_VIDC_VIDEO_INTRA_REFRESH_CYCLIC_ADAPTIVE = 3, + V4L2_CID_MPEG_VIDC_VIDEO_INTRA_REFRESH_RANDOM = 4, +}; +#define V4L2_CID_MPEG_VIDC_VIDEO_AIR_MBS (V4L2_CID_MPEG_MSM_VIDC_BASE+17) +#define V4L2_CID_MPEG_VIDC_VIDEO_AIR_REF (V4L2_CID_MPEG_MSM_VIDC_BASE+18) +#define V4L2_CID_MPEG_VIDC_VIDEO_CIR_MBS (V4L2_CID_MPEG_MSM_VIDC_BASE+19) + +#define V4L2_CID_MPEG_VIDC_VIDEO_H263_PROFILE (V4L2_CID_MPEG_MSM_VIDC_BASE+20) +enum v4l2_mpeg_vidc_video_h263_profile { + V4L2_MPEG_VIDC_VIDEO_H263_PROFILE_BASELINE = 0, + V4L2_MPEG_VIDC_VIDEO_H263_PROFILE_H320CODING = 1, + V4L2_MPEG_VIDC_VIDEO_H263_PROFILE_BACKWARDCOMPATIBLE = 2, + V4L2_MPEG_VIDC_VIDEO_H263_PROFILE_ISWV2 = 3, + V4L2_MPEG_VIDC_VIDEO_H263_PROFILE_ISWV3 = 4, + V4L2_MPEG_VIDC_VIDEO_H263_PROFILE_HIGHCOMPRESSION = 5, + V4L2_MPEG_VIDC_VIDEO_H263_PROFILE_INTERNET = 6, + V4L2_MPEG_VIDC_VIDEO_H263_PROFILE_INTERLACE = 7, + V4L2_MPEG_VIDC_VIDEO_H263_PROFILE_HIGHLATENCY = 8, +}; + +#define V4L2_CID_MPEG_VIDC_VIDEO_H263_LEVEL (V4L2_CID_MPEG_MSM_VIDC_BASE+21) +enum v4l2_mpeg_vidc_video_h263_level { + V4L2_MPEG_VIDC_VIDEO_H263_LEVEL_1_0 = 0, + V4L2_MPEG_VIDC_VIDEO_H263_LEVEL_2_0 = 1, + V4L2_MPEG_VIDC_VIDEO_H263_LEVEL_3_0 = 2, + V4L2_MPEG_VIDC_VIDEO_H263_LEVEL_4_0 = 3, + V4L2_MPEG_VIDC_VIDEO_H263_LEVEL_4_5 = 4, + V4L2_MPEG_VIDC_VIDEO_H263_LEVEL_5_0 = 5, + V4L2_MPEG_VIDC_VIDEO_H263_LEVEL_6_0 = 6, + V4L2_MPEG_VIDC_VIDEO_H263_LEVEL_7_0 = 7, +}; + +#define V4L2_CID_MPEG_VIDC_VIDEO_H264_AU_DELIMITER \ + (V4L2_CID_MPEG_MSM_VIDC_BASE + 22) +enum v4l2_mpeg_vidc_video_h264_au_delimiter { + V4L2_MPEG_VIDC_VIDEO_H264_AU_DELIMITER_DISABLED = 0, + V4L2_MPEG_VIDC_VIDEO_H264_AU_DELIMITER_ENABLED = 1 +}; +#define V4L2_CID_MPEG_VIDC_VIDEO_SYNC_FRAME_DECODE \ + (V4L2_CID_MPEG_MSM_VIDC_BASE + 23) +enum v4l2_mpeg_vidc_video_sync_frame_decode { + V4L2_MPEG_VIDC_VIDEO_SYNC_FRAME_DECODE_DISABLE = 0, + V4L2_MPEG_VIDC_VIDEO_SYNC_FRAME_DECODE_ENABLE = 1 +}; +#define V4L2_CID_MPEG_VIDC_VIDEO_SECURE (V4L2_CID_MPEG_MSM_VIDC_BASE+24) +#define V4L2_CID_MPEG_VIDC_VIDEO_EXTRADATA \ + (V4L2_CID_MPEG_MSM_VIDC_BASE + 25) +enum v4l2_mpeg_vidc_extradata { + V4L2_MPEG_VIDC_EXTRADATA_NONE = 0, + V4L2_MPEG_VIDC_EXTRADATA_MB_QUANTIZATION = 1, + V4L2_MPEG_VIDC_EXTRADATA_INTERLACE_VIDEO = 2, + V4L2_MPEG_VIDC_EXTRADATA_VC1_FRAMEDISP = 3, + V4L2_MPEG_VIDC_EXTRADATA_VC1_SEQDISP = 4, + V4L2_MPEG_VIDC_EXTRADATA_TIMESTAMP = 5, + V4L2_MPEG_VIDC_EXTRADATA_S3D_FRAME_PACKING = 6, + V4L2_MPEG_VIDC_EXTRADATA_FRAME_RATE = 7, + V4L2_MPEG_VIDC_EXTRADATA_PANSCAN_WINDOW = 8, + V4L2_MPEG_VIDC_EXTRADATA_RECOVERY_POINT_SEI = 9, + V4L2_MPEG_VIDC_EXTRADATA_MULTISLICE_INFO = 10, + V4L2_MPEG_VIDC_EXTRADATA_NUM_CONCEALED_MB = 11, + V4L2_MPEG_VIDC_EXTRADATA_METADATA_FILLER = 12, + V4L2_MPEG_VIDC_EXTRADATA_INPUT_CROP = 13, + V4L2_MPEG_VIDC_EXTRADATA_DIGITAL_ZOOM = 14, + V4L2_MPEG_VIDC_EXTRADATA_ASPECT_RATIO = 15, + V4L2_MPEG_VIDC_EXTRADATA_MPEG2_SEQDISP = 16, + V4L2_MPEG_VIDC_EXTRADATA_STREAM_USERDATA = 17, + V4L2_MPEG_VIDC_EXTRADATA_FRAME_QP = 18, + V4L2_MPEG_VIDC_EXTRADATA_FRAME_BITS_INFO = 19, + V4L2_MPEG_VIDC_EXTRADATA_LTR = 20, + V4L2_MPEG_VIDC_EXTRADATA_METADATA_MBI = 21, + V4L2_MPEG_VIDC_EXTRADATA_VQZIP_SEI = 22, + V4L2_MPEG_VIDC_EXTRADATA_YUV_STATS = 23, + V4L2_MPEG_VIDC_EXTRADATA_ROI_QP = 24, +#define V4L2_MPEG_VIDC_EXTRADATA_OUTPUT_CROP \ + V4L2_MPEG_VIDC_EXTRADATA_OUTPUT_CROP + V4L2_MPEG_VIDC_EXTRADATA_OUTPUT_CROP = 25, +#define V4L2_MPEG_VIDC_EXTRADATA_DISPLAY_COLOUR_SEI \ + V4L2_MPEG_VIDC_EXTRADATA_DISPLAY_COLOUR_SEI + V4L2_MPEG_VIDC_EXTRADATA_DISPLAY_COLOUR_SEI = 26, +#define V4L2_MPEG_VIDC_EXTRADATA_CONTENT_LIGHT_LEVEL_SEI \ + V4L2_MPEG_VIDC_EXTRADATA_CONTENT_LIGHT_LEVEL_SEI + V4L2_MPEG_VIDC_EXTRADATA_CONTENT_LIGHT_LEVEL_SEI = 27, +#define V4L2_MPEG_VIDC_EXTRADATA_PQ_INFO \ + V4L2_MPEG_VIDC_EXTRADATA_PQ_INFO + V4L2_MPEG_VIDC_EXTRADATA_PQ_INFO = 28, +#define V4L2_MPEG_VIDC_EXTRADATA_VUI_DISPLAY \ + V4L2_MPEG_VIDC_EXTRADATA_VUI_DISPLAY + V4L2_MPEG_VIDC_EXTRADATA_VUI_DISPLAY = 29, +#define V4L2_MPEG_VIDC_EXTRADATA_VPX_COLORSPACE \ + V4L2_MPEG_VIDC_EXTRADATA_VPX_COLORSPACE + V4L2_MPEG_VIDC_EXTRADATA_VPX_COLORSPACE = 30, +}; + +#define V4L2_CID_MPEG_VIDC_SET_PERF_LEVEL (V4L2_CID_MPEG_MSM_VIDC_BASE + 26) +enum v4l2_mpeg_vidc_perf_level { + V4L2_CID_MPEG_VIDC_PERF_LEVEL_NOMINAL = 0, + V4L2_CID_MPEG_VIDC_PERF_LEVEL_PERFORMANCE = 1, + V4L2_CID_MPEG_VIDC_PERF_LEVEL_TURBO = 2, +}; +#define V4L2_CID_MPEG_VIDEO_MULTI_SLICE_GOB \ + (V4L2_CID_MPEG_MSM_VIDC_BASE + 27) + +#define V4L2_CID_MPEG_VIDEO_MULTI_SLICE_DELIVERY_MODE \ + (V4L2_CID_MPEG_MSM_VIDC_BASE + 28) + +#define V4L2_CID_MPEG_VIDC_VIDEO_H264_VUI_TIMING_INFO \ + (V4L2_CID_MPEG_MSM_VIDC_BASE + 29) +enum v4l2_mpeg_vidc_video_h264_vui_timing_info { + V4L2_MPEG_VIDC_VIDEO_H264_VUI_TIMING_INFO_DISABLED = 0, + V4L2_MPEG_VIDC_VIDEO_H264_VUI_TIMING_INFO_ENABLED = 1 +}; + +#define V4L2_CID_MPEG_VIDC_VIDEO_ALLOC_MODE_INPUT \ + (V4L2_CID_MPEG_MSM_VIDC_BASE + 30) +#define V4L2_CID_MPEG_VIDC_VIDEO_ALLOC_MODE_OUTPUT \ + (V4L2_CID_MPEG_MSM_VIDC_BASE + 31) +enum v4l2_mpeg_vidc_video_alloc_mode_type { + V4L2_MPEG_VIDC_VIDEO_STATIC = 0, + V4L2_MPEG_VIDC_VIDEO_RING = 1, + V4L2_MPEG_VIDC_VIDEO_DYNAMIC = 2, +}; + +#define V4L2_CID_MPEG_VIDC_VIDEO_FRAME_ASSEMBLY \ + (V4L2_CID_MPEG_MSM_VIDC_BASE + 32) +enum v4l2_mpeg_vidc_video_assembly { + V4L2_MPEG_VIDC_FRAME_ASSEMBLY_DISABLE = 0, + V4L2_MPEG_VIDC_FRAME_ASSEMBLY_ENABLE = 1, +}; + +#define V4L2_CID_MPEG_VIDC_VIDEO_VP8_PROFILE_LEVEL \ + (V4L2_CID_MPEG_MSM_VIDC_BASE + 33) +enum v4l2_mpeg_vidc_video_vp8_profile_level { + V4L2_MPEG_VIDC_VIDEO_VP8_UNUSED, + V4L2_MPEG_VIDC_VIDEO_VP8_VERSION_0, + V4L2_MPEG_VIDC_VIDEO_VP8_VERSION_1, + V4L2_MPEG_VIDC_VIDEO_VP8_VERSION_2, + V4L2_MPEG_VIDC_VIDEO_VP8_VERSION_3, +}; + +#define V4L2_CID_MPEG_VIDC_VIDEO_H264_VUI_BITSTREAM_RESTRICT \ + (V4L2_CID_MPEG_MSM_VIDC_BASE + 34) +enum v4l2_mpeg_vidc_video_h264_vui_bitstream_restrict { + V4L2_MPEG_VIDC_VIDEO_H264_VUI_BITSTREAM_RESTRICT_DISABLED = 0, + V4L2_MPEG_VIDC_VIDEO_H264_VUI_BITSTREAM_RESTRICT_ENABLED = 1 +}; + +#define V4L2_CID_MPEG_VIDC_VIDEO_PRESERVE_TEXT_QUALITY \ + (V4L2_CID_MPEG_MSM_VIDC_BASE + 35) +enum v4l2_mpeg_vidc_video_preserve_text_quality { + V4L2_MPEG_VIDC_VIDEO_PRESERVE_TEXT_QUALITY_DISABLED = 0, + V4L2_MPEG_VIDC_VIDEO_PRESERVE_TEXT_QUALITY_ENABLED = 1 +}; + +#define V4L2_CID_MPEG_VIDC_VIDEO_DEINTERLACE \ + (V4L2_CID_MPEG_MSM_VIDC_BASE + 36) +enum v4l2_mpeg_vidc_video_deinterlace { + V4L2_CID_MPEG_VIDC_VIDEO_DEINTERLACE_DISABLED = 0, + V4L2_CID_MPEG_VIDC_VIDEO_DEINTERLACE_ENABLED = 1 +}; + +#define V4L2_CID_MPEG_VIDC_VIDEO_MPEG4_TIME_RESOLUTION \ + (V4L2_CID_MPEG_MSM_VIDC_BASE + 37) + +#define V4L2_CID_MPEG_VIDC_VIDEO_STREAM_OUTPUT_MODE \ + (V4L2_CID_MPEG_MSM_VIDC_BASE + 38) +enum v4l2_mpeg_vidc_video_decoder_multi_stream { + V4L2_CID_MPEG_VIDC_VIDEO_STREAM_OUTPUT_PRIMARY = 0, + V4L2_CID_MPEG_VIDC_VIDEO_STREAM_OUTPUT_SECONDARY = 1, +}; +#define V4L2_CID_MPEG_VIDC_VIDEO_SCS_THRESHOLD \ + (V4L2_CID_MPEG_MSM_VIDC_BASE + 39) + +#define V4L2_CID_MPEG_VIDC_VIDEO_MPEG2_LEVEL (V4L2_CID_MPEG_MSM_VIDC_BASE+40) +enum v4l2_mpeg_vidc_video_mpeg2_level { + V4L2_MPEG_VIDC_VIDEO_MPEG2_LEVEL_0 = 0, + V4L2_MPEG_VIDC_VIDEO_MPEG2_LEVEL_1 = 1, + V4L2_MPEG_VIDC_VIDEO_MPEG2_LEVEL_2 = 2, + V4L2_MPEG_VIDC_VIDEO_MPEG2_LEVEL_3 = 3, +}; +#define V4L2_CID_MPEG_VIDC_VIDEO_MPEG2_PROFILE (V4L2_CID_MPEG_MSM_VIDC_BASE+41) +enum v4l2_mpeg_vidc_video_mpeg2_profile { + V4L2_MPEG_VIDC_VIDEO_MPEG2_PROFILE_SIMPLE = 0, + V4L2_MPEG_VIDC_VIDEO_MPEG2_PROFILE_MAIN = 1, + V4L2_MPEG_VIDC_VIDEO_MPEG2_PROFILE_422 = 2, + V4L2_MPEG_VIDC_VIDEO_MPEG2_PROFILE_SNR_SCALABLE = 3, + V4L2_MPEG_VIDC_VIDEO_MPEG2_PROFILE_SPATIAL_SCALABLE = 4, + V4L2_MPEG_VIDC_VIDEO_MPEG2_PROFILE_HIGH = 5, +}; +#define V4L2_CID_MPEG_VIDC_VIDEO_REQUEST_SEQ_HEADER \ + (V4L2_CID_MPEG_MSM_VIDC_BASE + 42) + +#define V4L2_CID_MPEG_VIDC_VIDEO_MVC_BUFFER_LAYOUT \ + (V4L2_CID_MPEG_MSM_VIDC_BASE + 43) +enum v4l2_mpeg_vidc_video_mvc_layout { + V4L2_MPEG_VIDC_VIDEO_MVC_SEQUENTIAL = 0, + V4L2_MPEG_VIDC_VIDEO_MVC_TOP_BOTTOM = 1 +}; +#define V4L2_CID_MPEG_VIDC_VIDEO_VP8_MIN_QP (V4L2_CID_MPEG_MSM_VIDC_BASE + 44) +#define V4L2_CID_MPEG_VIDC_VIDEO_VP8_MAX_QP (V4L2_CID_MPEG_MSM_VIDC_BASE + 45) + +#define V4L2_CID_MPEG_VIDC_VIDEO_CONCEAL_COLOR \ + (V4L2_CID_MPEG_MSM_VIDC_BASE + 46) + +#define V4L2_CID_MPEG_VIDC_VIDEO_LTRMODE \ + (V4L2_CID_MPEG_MSM_VIDC_BASE + 47) + +enum v4l2_mpeg_vidc_video_ltrmode { + V4L2_MPEG_VIDC_VIDEO_LTR_MODE_DISABLE = 0, + V4L2_MPEG_VIDC_VIDEO_LTR_MODE_MANUAL = 1, + V4L2_MPEG_VIDC_VIDEO_LTR_MODE_PERIODIC = 2 +}; + +#define V4L2_CID_MPEG_VIDC_VIDEO_LTRCOUNT \ + (V4L2_CID_MPEG_MSM_VIDC_BASE + 48) + +#define V4L2_CID_MPEG_VIDC_VIDEO_USELTRFRAME \ + (V4L2_CID_MPEG_MSM_VIDC_BASE + 49) + +#define V4L2_CID_MPEG_VIDC_VIDEO_MARKLTRFRAME \ + (V4L2_CID_MPEG_MSM_VIDC_BASE + 50) + +#define V4L2_CID_MPEG_VIDC_VIDEO_HIER_P_NUM_LAYERS \ + (V4L2_CID_MPEG_MSM_VIDC_BASE + 51) + +#define V4L2_CID_MPEG_VIDC_VIDEO_RATE_CONTROL_TIMESTAMP_MODE \ + (V4L2_CID_MPEG_MSM_VIDC_BASE + 52) +enum v4l2_mpeg_vidc_video_rate_control_timestamp_mode { + V4L2_MPEG_VIDC_VIDEO_RATE_CONTROL_TIMESTAMP_MODE_HONOR = 0, + V4L2_MPEG_VIDC_VIDEO_RATE_CONTROL_TIMESTAMP_MODE_IGNORE = 1, +}; + +#define V4L2_CID_MPEG_VIDC_VIDEO_ENABLE_INITIAL_QP \ + (V4L2_CID_MPEG_MSM_VIDC_BASE + 53) +enum vl42_mpeg_vidc_video_enable_initial_qp { + V4L2_CID_MPEG_VIDC_VIDEO_ENABLE_INITIAL_QP_IFRAME = 0x1, + V4L2_CID_MPEG_VIDC_VIDEO_ENABLE_INITIAL_QP_PFRAME = 0x2, + V4L2_CID_MPEG_VIDC_VIDEO_ENABLE_INITIAL_QP_BFRAME = 0x4, +}; + +#define V4L2_CID_MPEG_VIDC_VIDEO_INITIAL_I_FRAME_QP \ + (V4L2_CID_MPEG_MSM_VIDC_BASE + 54) + +#define V4L2_CID_MPEG_VIDC_VIDEO_INITIAL_P_FRAME_QP \ + (V4L2_CID_MPEG_MSM_VIDC_BASE + 55) + +#define V4L2_CID_MPEG_VIDC_VIDEO_INITIAL_B_FRAME_QP \ + (V4L2_CID_MPEG_MSM_VIDC_BASE + 56) + +#define V4L2_CID_MPEG_VIDC_VIDEO_IFRAME_X_RANGE \ + (V4L2_CID_MPEG_MSM_VIDC_BASE + 57) + +#define V4L2_CID_MPEG_VIDC_VIDEO_PFRAME_X_RANGE \ + (V4L2_CID_MPEG_MSM_VIDC_BASE + 58) + +#define V4L2_CID_MPEG_VIDC_VIDEO_BFRAME_X_RANGE \ + (V4L2_CID_MPEG_MSM_VIDC_BASE + 59) + +#define V4L2_CID_MPEG_VIDC_VIDEO_IFRAME_Y_RANGE \ + (V4L2_CID_MPEG_MSM_VIDC_BASE + 60) + +#define V4L2_CID_MPEG_VIDC_VIDEO_PFRAME_Y_RANGE \ + (V4L2_CID_MPEG_MSM_VIDC_BASE + 61) + +#define V4L2_CID_MPEG_VIDC_VIDEO_BFRAME_Y_RANGE \ + (V4L2_CID_MPEG_MSM_VIDC_BASE + 62) + +#define V4L2_CID_MPEG_VIDC_VIDEO_VPX_ERROR_RESILIENCE \ + (V4L2_CID_MPEG_MSM_VIDC_BASE + 63) + +#define V4L2_CID_MPEG_VIDC_VIDEO_BUFFER_SIZE_LIMIT \ + (V4L2_CID_MPEG_MSM_VIDC_BASE + 64) + +enum vl42_mpeg_vidc_video_vpx_error_resilience { + V4L2_MPEG_VIDC_VIDEO_VPX_ERROR_RESILIENCE_DISABLED = 0, + V4L2_MPEG_VIDC_VIDEO_VPX_ERROR_RESILIENCE_ENABLED = 1, +}; + +#define V4L2_CID_MPEG_VIDC_VIDEO_HEVC_PROFILE \ + (V4L2_CID_MPEG_MSM_VIDC_BASE + 65) +enum v4l2_mpeg_video_hevc_profile { + V4L2_MPEG_VIDC_VIDEO_HEVC_PROFILE_MAIN = 0, + V4L2_MPEG_VIDC_VIDEO_HEVC_PROFILE_MAIN10 = 1, + V4L2_MPEG_VIDC_VIDEO_HEVC_PROFILE_MAIN_STILL_PIC = 2, +}; + +#define V4L2_CID_MPEG_VIDC_VIDEO_HEVC_TIER_LEVEL \ + (V4L2_CID_MPEG_MSM_VIDC_BASE + 66) +enum v4l2_mpeg_video_hevc_level { + V4L2_MPEG_VIDC_VIDEO_HEVC_LEVEL_MAIN_TIER_LEVEL_1 = 0, + V4L2_MPEG_VIDC_VIDEO_HEVC_LEVEL_HIGH_TIER_LEVEL_1 = 1, + V4L2_MPEG_VIDC_VIDEO_HEVC_LEVEL_MAIN_TIER_LEVEL_2 = 2, + V4L2_MPEG_VIDC_VIDEO_HEVC_LEVEL_HIGH_TIER_LEVEL_2 = 3, + V4L2_MPEG_VIDC_VIDEO_HEVC_LEVEL_MAIN_TIER_LEVEL_2_1 = 4, + V4L2_MPEG_VIDC_VIDEO_HEVC_LEVEL_HIGH_TIER_LEVEL_2_1 = 5, + V4L2_MPEG_VIDC_VIDEO_HEVC_LEVEL_MAIN_TIER_LEVEL_3 = 6, + V4L2_MPEG_VIDC_VIDEO_HEVC_LEVEL_HIGH_TIER_LEVEL_3 = 7, + V4L2_MPEG_VIDC_VIDEO_HEVC_LEVEL_MAIN_TIER_LEVEL_3_1 = 8, + V4L2_MPEG_VIDC_VIDEO_HEVC_LEVEL_HIGH_TIER_LEVEL_3_1 = 9, + V4L2_MPEG_VIDC_VIDEO_HEVC_LEVEL_MAIN_TIER_LEVEL_4 = 10, + V4L2_MPEG_VIDC_VIDEO_HEVC_LEVEL_HIGH_TIER_LEVEL_4 = 11, + V4L2_MPEG_VIDC_VIDEO_HEVC_LEVEL_MAIN_TIER_LEVEL_4_1 = 12, + V4L2_MPEG_VIDC_VIDEO_HEVC_LEVEL_HIGH_TIER_LEVEL_4_1 = 13, + V4L2_MPEG_VIDC_VIDEO_HEVC_LEVEL_MAIN_TIER_LEVEL_5 = 14, + V4L2_MPEG_VIDC_VIDEO_HEVC_LEVEL_HIGH_TIER_LEVEL_5 = 15, + V4L2_MPEG_VIDC_VIDEO_HEVC_LEVEL_MAIN_TIER_LEVEL_5_1 = 16, + V4L2_MPEG_VIDC_VIDEO_HEVC_LEVEL_HIGH_TIER_LEVEL_5_1 = 17, + V4L2_MPEG_VIDC_VIDEO_HEVC_LEVEL_MAIN_TIER_LEVEL_5_2 = 18, + V4L2_MPEG_VIDC_VIDEO_HEVC_LEVEL_HIGH_TIER_LEVEL_5_2 = 19, + V4L2_MPEG_VIDC_VIDEO_HEVC_LEVEL_MAIN_TIER_LEVEL_6 = 20, + V4L2_MPEG_VIDC_VIDEO_HEVC_LEVEL_HIGH_TIER_LEVEL_6 = 21, + V4L2_MPEG_VIDC_VIDEO_HEVC_LEVEL_MAIN_TIER_LEVEL_6_1 = 22, + V4L2_MPEG_VIDC_VIDEO_HEVC_LEVEL_HIGH_TIER_LEVEL_6_1 = 23, + V4L2_MPEG_VIDC_VIDEO_HEVC_LEVEL_MAIN_TIER_LEVEL_6_2 = 24, + V4L2_MPEG_VIDC_VIDEO_HEVC_LEVEL_HIGH_TIER_LEVEL_6_2 = 25, +}; + +#define V4L2_CID_MPEG_VIDC_VIDEO_H264_NAL_SVC \ + (V4L2_CID_MPEG_MSM_VIDC_BASE + 67) + +enum vl42_mpeg_vidc_video_h264_svc_nal { + V4L2_CID_MPEG_VIDC_VIDEO_H264_NAL_SVC_DISABLED = 0, + V4L2_CID_MPEG_VIDC_VIDEO_H264_NAL_SVC_ENABLED = 1, +}; + +#define V4L2_CID_MPEG_VIDC_VIDEO_PERF_MODE \ + (V4L2_CID_MPEG_MSM_VIDC_BASE + 68) + +enum v4l2_mpeg_vidc_video_perf_mode { +#define V4L2_MPEG_VIDC_VIDEO_PERF_UNINIT \ + V4L2_MPEG_VIDC_VIDEO_PERF_UNINIT + V4L2_MPEG_VIDC_VIDEO_PERF_UNINIT = 0, + V4L2_MPEG_VIDC_VIDEO_PERF_MAX_QUALITY = 1, + V4L2_MPEG_VIDC_VIDEO_PERF_POWER_SAVE = 2 +}; + +#define V4L2_CID_MPEG_VIDC_VIDEO_HIER_B_NUM_LAYERS \ + (V4L2_CID_MPEG_MSM_VIDC_BASE + 69) + +#define V4L2_CID_MPEG_VIDC_VIDEO_SECURE_SCALING_THRESHOLD \ + (V4L2_CID_MPEG_MSM_VIDC_BASE + 70) + +#define V4L2_CID_MPEG_VIDC_VIDEO_NON_SECURE_OUTPUT2 \ + (V4L2_CID_MPEG_MSM_VIDC_BASE + 71) + +#define V4L2_CID_MPEG_VIDC_VIDEO_HYBRID_HIERP_MODE \ + (V4L2_CID_MPEG_MSM_VIDC_BASE + 72) + +#define V4L2_CID_MPEG_VIDC_VIDEO_DPB_COLOR_FORMAT \ + (V4L2_CID_MPEG_MSM_VIDC_BASE + 73) + +enum v4l2_mpeg_vidc_video_dpb_color_format { + V4L2_MPEG_VIDC_VIDEO_DPB_COLOR_FMT_NONE = 0, + V4L2_MPEG_VIDC_VIDEO_DPB_COLOR_FMT_UBWC = 1, + V4L2_MPEG_VIDC_VIDEO_DPB_COLOR_FMT_TP10_UBWC = 2 +}; + +#define V4L2_CID_MPEG_VIDC_VIDEO_MBI_STATISTICS_MODE \ + (V4L2_CID_MPEG_MSM_VIDC_BASE + 74) + +enum v4l2_mpeg_vidc_video_mbi_statistics_mode { + V4L2_CID_MPEG_VIDC_VIDEO_MBI_MODE_DEFAULT = 0, + V4L2_CID_MPEG_VIDC_VIDEO_MBI_MODE_1 = 1, + V4L2_CID_MPEG_VIDC_VIDEO_MBI_MODE_2 = 2, + V4L2_CID_MPEG_VIDC_VIDEO_MBI_MODE_3 = 3, +}; + +#define V4L2_CID_VIDC_QBUF_MODE \ + (V4L2_CID_MPEG_MSM_VIDC_BASE + 75) +enum v4l2_vidc_qbuf_mode { + V4L2_VIDC_QBUF_STANDARD = 0, + V4L2_VIDC_QBUF_BATCHED = 1, +}; + +#define V4L2_CID_MPEG_VIDC_VIDEO_MAX_HIERP_LAYERS \ + (V4L2_CID_MPEG_MSM_VIDC_BASE + 76) + +#define V4L2_CID_MPEG_VIDC_VIDEO_BASELAYER_ID \ + (V4L2_CID_MPEG_MSM_VIDC_BASE + 77) + +#define V4L2_CID_MPEG_VIDC_VIDEO_CONFIG_QP \ + (V4L2_CID_MPEG_MSM_VIDC_BASE + 78) + +#define V4L2_CID_MPEG_VIDC_VENC_PARAM_SAR_WIDTH \ + (V4L2_CID_MPEG_MSM_VIDC_BASE + 79) + +#define V4L2_CID_MPEG_VIDC_VENC_PARAM_SAR_HEIGHT \ + (V4L2_CID_MPEG_MSM_VIDC_BASE + 80) + +#define V4L2_CID_MPEG_VIDC_VIDEO_VQZIP_SEI \ + (V4L2_CID_MPEG_MSM_VIDC_BASE + 81) + +enum v4l2_mpeg_vidc_video_vqzip_sei_enable { + V4L2_CID_MPEG_VIDC_VIDEO_VQZIP_SEI_DISABLE = 0, + V4L2_CID_MPEG_VIDC_VIDEO_VQZIP_SEI_ENABLE = 1 +}; + +#define V4L2_CID_MPEG_VIDC_VENC_PARAM_LAYER_BITRATE \ + (V4L2_CID_MPEG_MSM_VIDC_BASE + 82) + +#define V4L2_CID_MPEG_VIDC_VIDEO_PRIORITY \ + (V4L2_CID_MPEG_MSM_VIDC_BASE + 83) + +enum v4l2_mpeg_vidc_video_priority { + V4L2_MPEG_VIDC_VIDEO_PRIORITY_REALTIME_ENABLE = 0, + V4L2_MPEG_VIDC_VIDEO_PRIORITY_REALTIME_DISABLE = 1, +}; + +#define V4L2_CID_MPEG_VIDC_VIDEO_OPERATING_RATE \ + (V4L2_CID_MPEG_MSM_VIDC_BASE + 84) + +#define V4L2_CID_MPEG_VIDC_VIDEO_VENC_BITRATE_TYPE \ + (V4L2_CID_MPEG_MSM_VIDC_BASE + 85) + +enum v4l2_mpeg_vidc_video_venc_bitrate_type_enable { + V4L2_CID_MPEG_VIDC_VIDEO_VENC_BITRATE_DISABLE = 0, + V4L2_CID_MPEG_VIDC_VIDEO_VENC_BITRATE_ENABLE = 1 +}; + +#define V4L2_CID_MPEG_VIDC_VIDEO_H264_PIC_ORDER_CNT \ + (V4L2_CID_MPEG_MSM_VIDC_BASE + 86) + +#define V4L2_CID_MPEG_VIDC_VIDEO_VPE_CSC \ + (V4L2_CID_MPEG_MSM_VIDC_BASE + 87) + +enum v4l2_cid_mpeg_vidc_video_vpe_csc_type_enable { + V4L2_CID_MPEG_VIDC_VIDEO_VPE_CSC_DISABLE = 0, + V4L2_CID_MPEG_VIDC_VIDEO_VPE_CSC_ENABLE = 1 +}; + +#define V4L2_CID_MPEG_VIDC_VIDEO_LOWLATENCY_MODE \ + (V4L2_CID_MPEG_MSM_VIDC_BASE + 88) + +enum v4l2_mpeg_vidc_video_lowlatency_mode { + V4L2_CID_MPEG_VIDC_VIDEO_LOWLATENCY_DISABLE = 0, + V4L2_CID_MPEG_VIDC_VIDEO_LOWLATENCY_ENABLE = 1, +}; + +#define V4L2_CID_MPEG_VIDC_VIDEO_BLUR_WIDTH \ + (V4L2_CID_MPEG_MSM_VIDC_BASE + 89) + +#define V4L2_CID_MPEG_VIDC_VIDEO_BLUR_HEIGHT \ + (V4L2_CID_MPEG_MSM_VIDC_BASE + 90) + +#define V4L2_CID_MPEG_VIDEO_MIN_QP_PACKED \ + (V4L2_CID_MPEG_MSM_VIDC_BASE + 91) +#define V4L2_CID_MPEG_VIDEO_MAX_QP_PACKED \ + (V4L2_CID_MPEG_MSM_VIDC_BASE + 92) + +#define V4L2_CID_MPEG_VIDC_VIDEO_H264_TRANSFORM_8x8 \ + (V4L2_CID_MPEG_MSM_VIDC_BASE + 93) +enum v4l2_mpeg_vidc_video_h264_transform_8x8 { + V4L2_MPEG_VIDC_VIDEO_H264_TRANSFORM_8x8_DISABLE = 0, + V4L2_MPEG_VIDC_VIDEO_H264_TRANSFORM_8x8_ENABLE = 1, +}; + +#define V4L2_CID_MPEG_VIDC_VIDEO_COLOR_SPACE \ + (V4L2_CID_MPEG_MSM_VIDC_BASE + 94) + +#define V4L2_CID_MPEG_VIDC_VIDEO_FULL_RANGE \ + (V4L2_CID_MPEG_MSM_VIDC_BASE + 95) + +enum v4l2_cid_mpeg_vidc_video_full_range { + V4L2_CID_MPEG_VIDC_VIDEO_FULL_RANGE_DISABLE = 0, + V4L2_CID_MPEG_VIDC_VIDEO_FULL_RANGE_ENABLE = 1, +}; + +#define V4L2_CID_MPEG_VIDC_VIDEO_TRANSFER_CHARS \ + (V4L2_CID_MPEG_MSM_VIDC_BASE + 96) + +#define V4L2_CID_MPEG_VIDC_VIDEO_MATRIX_COEFFS \ + (V4L2_CID_MPEG_MSM_VIDC_BASE + 97) + +#define V4L2_CID_MPEG_VIDC_VIDEO_IFRAME_SIZE_TYPE \ + (V4L2_CID_MPEG_MSM_VIDC_BASE + 98) +enum v4l2_mpeg_vidc_video_venc_iframesize_type { + V4L2_CID_MPEG_VIDC_VIDEO_IFRAME_SIZE_DEFAULT, + V4L2_CID_MPEG_VIDC_VIDEO_IFRAME_SIZE_MEDIUM, + V4L2_CID_MPEG_VIDC_VIDEO_IFRAME_SIZE_HUGE, + V4L2_CID_MPEG_VIDC_VIDEO_IFRAME_SIZE_UNLIMITED, +}; + +#define V4L2_CID_MPEG_VIDC_VIDEO_I_FRAME_QP \ + (V4L2_CID_MPEG_MSM_VIDC_BASE + 99) +#define V4L2_CID_MPEG_VIDC_VIDEO_P_FRAME_QP \ + (V4L2_CID_MPEG_MSM_VIDC_BASE + 100) +#define V4L2_CID_MPEG_VIDC_VIDEO_B_FRAME_QP \ + (V4L2_CID_MPEG_MSM_VIDC_BASE + 101) + +#define V4L2_CID_MPEG_VIDC_VIDEO_AU_DELIMITER \ + (V4L2_CID_MPEG_MSM_VIDC_BASE + 102) +enum v4l2_mpeg_vidc_video_au_delimiter { + V4L2_MPEG_VIDC_VIDEO_AU_DELIMITER_DISABLED = 0, + V4L2_MPEG_VIDC_VIDEO_AU_DELIMITER_ENABLED = 1 +}; + +#define V4L2_CID_MPEG_VIDC_VIDEO_SEND_SKIPPED_FRAME \ + (V4L2_CID_MPEG_MSM_VIDC_BASE + 103) +enum v4l2_mpeg_vidc_video_venc_send_skipped_frame { + V4L2_MPEG_VIDC_VIDEO_SEND_SKIPPED_FRAME_DISABLE = 0, + V4L2_MPEG_VIDC_VIDEO_SEND_SKIPPED_FRAME_ENABLE = 1 +}; + /* Camera class control IDs */ @@ -757,6 +1345,12 @@ #define V4L2_CID_PAN_SPEED (V4L2_CID_CAMERA_CLASS_BASE+32) #define V4L2_CID_TILT_SPEED (V4L2_CID_CAMERA_CLASS_BASE+33) +/* User-class control IDs specific to the msm_ba driver */ + +#define MSM_BA_PRIV_BASE_START (V4L2_CID_USER_BASE | 0x7000) +#define MSM_BA_PRIV_SD_NODE_ADDR (MSM_BA_PRIV_BASE_START + 1) +#define MSM_BA_PRIV_FPS (MSM_BA_PRIV_BASE_START + 2) + /* FM Modulator class control IDs */ #define V4L2_CID_FM_TX_CLASS_BASE (V4L2_CTRL_CLASS_FM_TX | 0x900) diff -ruw linux-4.4.115/include/uapi/linux/videodev2.h linux-4.4.115-fbx/include/uapi/linux/videodev2.h --- linux-4.4.115/include/uapi/linux/videodev2.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/uapi/linux/videodev2.h 2019-01-22 16:16:28.595292518 +0100 @@ -2,6 +2,7 @@ * Video for Linux Two header file * * Copyright (C) 1999-2012 the contributors + * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -69,7 +70,7 @@ * Common stuff for both V4L1 and V4L2 * Moved from videodev.h */ -#define VIDEO_MAX_FRAME 32 +#define VIDEO_MAX_FRAME 64 #define VIDEO_MAX_PLANES 8 /* @@ -488,6 +489,9 @@ #define V4L2_PIX_FMT_ARGB32 v4l2_fourcc('B', 'A', '2', '4') /* 32 ARGB-8-8-8-8 */ #define V4L2_PIX_FMT_XRGB32 v4l2_fourcc('B', 'X', '2', '4') /* 32 XRGB-8-8-8-8 */ +/* UBWC 32-bit RGBA8888 */ +#define V4L2_PIX_FMT_RGBA8888_UBWC v4l2_fourcc('Q', 'R', 'G', 'B') + /* Grey formats */ #define V4L2_PIX_FMT_GREY v4l2_fourcc('G', 'R', 'E', 'Y') /* 8 Greyscale */ #define V4L2_PIX_FMT_Y4 v4l2_fourcc('Y', '0', '4', ' ') /* 4 Greyscale */ @@ -535,6 +539,11 @@ #define V4L2_PIX_FMT_NV24 v4l2_fourcc('N', 'V', '2', '4') /* 24 Y/CbCr 4:4:4 */ #define V4L2_PIX_FMT_NV42 v4l2_fourcc('N', 'V', '4', '2') /* 24 Y/CrCb 4:4:4 */ +/* UBWC 8-bit Y/CbCr 4:2:0 */ +#define V4L2_PIX_FMT_NV12_UBWC v4l2_fourcc('Q', '1', '2', '8') +/* UBWC 10-bit Y/CbCr 4:2:0 */ +#define V4L2_PIX_FMT_NV12_TP10_UBWC v4l2_fourcc('Q', '1', '2', 'A') + /* two non contiguous planes - one Y, one Cr + Cb interleaved */ #define V4L2_PIX_FMT_NV12M v4l2_fourcc('N', 'M', '1', '2') /* 12 Y/CbCr 4:2:0 */ #define V4L2_PIX_FMT_NV21M v4l2_fourcc('N', 'M', '2', '1') /* 21 Y/CrCb 4:2:0 */ @@ -576,6 +585,16 @@ #define V4L2_PIX_FMT_SGRBG12 v4l2_fourcc('B', 'A', '1', '2') /* 12 GRGR.. BGBG.. */ #define V4L2_PIX_FMT_SRGGB12 v4l2_fourcc('R', 'G', '1', '2') /* 12 RGRG.. GBGB.. */ #define V4L2_PIX_FMT_SBGGR16 v4l2_fourcc('B', 'Y', 'R', '2') /* 16 BGBG.. GRGR.. */ + /* 10bit raw bayer DPCM compressed to 6 bits */ +#define V4L2_PIX_FMT_SBGGR10DPCM6 v4l2_fourcc('b', 'B', 'A', '6') +#define V4L2_PIX_FMT_SGBRG10DPCM6 v4l2_fourcc('b', 'G', 'A', '6') +#define V4L2_PIX_FMT_SGRBG10DPCM6 v4l2_fourcc('B', 'D', '1', '6') +#define V4L2_PIX_FMT_SRGGB10DPCM6 v4l2_fourcc('b', 'R', 'A', '6') + /* 10bit raw bayer, plain16 packed */ +#define V4L2_PIX_FMT_SBGGRPLAIN16 v4l2_fourcc('B', 'G', '1', '6') +#define V4L2_PIX_FMT_SGBRGPLAIN16 v4l2_fourcc('G', 'B', '1', '6') +#define V4L2_PIX_FMT_SGRBGPLAIN16 v4l2_fourcc('G', 'R', '1', '6') +#define V4L2_PIX_FMT_SRGGBPLAIN16 v4l2_fourcc('R', 'G', '1', '6') /* compressed formats */ #define V4L2_PIX_FMT_MJPEG v4l2_fourcc('M', 'J', 'P', 'G') /* Motion-JPEG */ @@ -593,6 +612,11 @@ #define V4L2_PIX_FMT_VC1_ANNEX_G v4l2_fourcc('V', 'C', '1', 'G') /* SMPTE 421M Annex G compliant stream */ #define V4L2_PIX_FMT_VC1_ANNEX_L v4l2_fourcc('V', 'C', '1', 'L') /* SMPTE 421M Annex L compliant stream */ #define V4L2_PIX_FMT_VP8 v4l2_fourcc('V', 'P', '8', '0') /* VP8 */ +#define V4L2_PIX_FMT_VP9 v4l2_fourcc('V', 'P', '9', '0') /* VP9 */ +#define V4L2_PIX_FMT_DIVX_311 v4l2_fourcc('D', 'I', 'V', '3') /* DIVX311 */ +#define V4L2_PIX_FMT_DIVX v4l2_fourcc('D', 'I', 'V', 'X') /* DIVX */ +#define V4L2_PIX_FMT_HEVC v4l2_fourcc('H', 'E', 'V', 'C') /* for HEVC stream */ +#define V4L2_PIX_FMT_HEVC_HYBRID v4l2_fourcc('H', 'V', 'C', 'H') /* Vendor-specific formats */ #define V4L2_PIX_FMT_CPIA1 v4l2_fourcc('C', 'P', 'I', 'A') /* cpia1 YUV */ @@ -625,6 +649,79 @@ #define V4L2_PIX_FMT_Y12I v4l2_fourcc('Y', '1', '2', 'I') /* Greyscale 12-bit L/R interleaved */ #define V4L2_PIX_FMT_Z16 v4l2_fourcc('Z', '1', '6', ' ') /* Depth data 16-bit */ +#define V4L2_PIX_FMT_SDE_ABGR_8888 \ + v4l2_fourcc('R', 'A', '2', '4') /* 32-bit ABGR 8:8:8:8 */ +#define V4L2_PIX_FMT_SDE_RGBA_8888 \ + v4l2_fourcc('A', 'B', '2', '4') /* 32-bit RGBA 8:8:8:8 */ +#define V4L2_PIX_FMT_SDE_RGBX_8888 \ + v4l2_fourcc('X', 'B', '2', '4') /* 32-bit RGBX 8:8:8:8 */ +#define V4L2_PIX_FMT_SDE_XBGR_8888 \ + v4l2_fourcc('R', 'X', '2', '4') /* 32-bit XBGR 8:8:8:8 */ +#define V4L2_PIX_FMT_SDE_RGBA_5551 \ + v4l2_fourcc('R', 'A', '1', '5') /* 16-bit RGBA 5:5:5:1 */ +#define V4L2_PIX_FMT_SDE_ABGR_1555 \ + v4l2_fourcc('A', 'B', '1', '5') /* 16-bit ABGR 1:5:5:5 */ +#define V4L2_PIX_FMT_SDE_BGRA_5551 \ + v4l2_fourcc('B', 'A', '1', '5') /* 16-bit BGRA 5:5:5:1 */ +#define V4L2_PIX_FMT_SDE_BGRX_5551 \ + v4l2_fourcc('B', 'X', '1', '5') /* 16-bit BGRX 5:5:5:1 */ +#define V4L2_PIX_FMT_SDE_RGBX_5551 \ + v4l2_fourcc('R', 'X', '1', '5') /* 16-bit RGBX 5:5:5:1 */ +#define V4L2_PIX_FMT_SDE_XBGR_1555 \ + v4l2_fourcc('X', 'B', '1', '5') /* 16-bit XBGR 1:5:5:5 */ +#define V4L2_PIX_FMT_SDE_RGBA_4444 \ + v4l2_fourcc('R', 'A', '1', '2') /* 16-bit RGBA 4:4:4:4 */ +#define V4L2_PIX_FMT_SDE_BGRA_4444 \ + v4l2_fourcc('b', 'A', '1', '2') /* 16-bit BGRA 4:4:4:4 */ +#define V4L2_PIX_FMT_SDE_ABGR_4444 \ + v4l2_fourcc('A', 'B', '1', '2') /* 16-bit ABGR 4:4:4:4 */ +#define V4L2_PIX_FMT_SDE_RGBX_4444 \ + v4l2_fourcc('R', 'X', '1', '2') /* 16-bit RGBX 4:4:4:4 */ +#define V4L2_PIX_FMT_SDE_BGRX_4444 \ + v4l2_fourcc('B', 'X', '1', '2') /* 16-bit BGRX 4:4:4:4 */ +#define V4L2_PIX_FMT_SDE_XBGR_4444 \ + v4l2_fourcc('X', 'B', '1', '2') /* 16-bit XBGR 4:4:4:4 */ +#define V4L2_PIX_FMT_SDE_BGR_565 \ + v4l2_fourcc('B', 'G', '1', '6') /* 16-bit BGR 5:6:5 */ +#define V4L2_PIX_FMT_SDE_Y_CR_CB_GH2V2 \ + v4l2_fourcc('Y', 'U', '4', '2') /* Planar YVU 4:2:0 A16 */ +#define V4L2_PIX_FMT_SDE_Y_CBCR_H1V2 \ + v4l2_fourcc('N', 'H', '1', '6') /* Y/CbCr 4:2:2 */ +#define V4L2_PIX_FMT_SDE_Y_CRCB_H1V2 \ + v4l2_fourcc('N', 'H', '6', '1') /* Y/CrCb 4:2:2 */ +#define V4L2_PIX_FMT_SDE_Y_CBCR_H2V2_VENUS \ + v4l2_fourcc('Q', 'N', 'V', '2') /* Y/CbCr 4:2:0 Venus */ +#define V4L2_PIX_FMT_SDE_Y_CRCB_H2V2_VENUS \ + v4l2_fourcc('Q', 'N', 'V', '1') /* Y/CrCb 4:2:0 Venus */ +#define V4L2_PIX_FMT_SDE_RGBX_8888_UBWC \ + v4l2_fourcc('Q', 'X', 'B', '4') /* RGBX 8:8:8:8 UBWC */ +#define V4L2_PIX_FMT_SDE_RGB_565_UBWC \ + v4l2_fourcc('Q', 'R', 'G', '6') /* RGB 5:6:5 UBWC */ +#define V4L2_PIX_FMT_SDE_RGBA_1010102 \ + v4l2_fourcc('A', 'B', '3', '0') /* RGBA 10:10:10:2 */ +#define V4L2_PIX_FMT_SDE_RGBX_1010102 \ + v4l2_fourcc('X', 'B', '3', '0') /* RGBX 10:10:10:2 */ +#define V4L2_PIX_FMT_SDE_ARGB_2101010 \ + v4l2_fourcc('A', 'R', '3', '0') /* ARGB 2:10:10:10 */ +#define V4L2_PIX_FMT_SDE_XRGB_2101010 \ + v4l2_fourcc('X', 'R', '3', '0') /* XRGB 2:10:10:10 */ +#define V4L2_PIX_FMT_SDE_BGRA_1010102 \ + v4l2_fourcc('B', 'A', '3', '0') /* BGRA 10:10:10:2 */ +#define V4L2_PIX_FMT_SDE_BGRX_1010102 \ + v4l2_fourcc('B', 'X', '3', '0') /* BGRX 10:10:10:2 */ +#define V4L2_PIX_FMT_SDE_ABGR_2101010 \ + v4l2_fourcc('R', 'A', '3', '0') /* ABGR 2:10:10:10 */ +#define V4L2_PIX_FMT_SDE_XBGR_2101010 \ + v4l2_fourcc('R', 'X', '3', '0') /* XBGR 2:10:10:10 */ +#define V4L2_PIX_FMT_SDE_RGBA_1010102_UBWC \ + v4l2_fourcc('Q', 'R', 'B', 'A') /* RGBA 10:10:10:2 UBWC */ +#define V4L2_PIX_FMT_SDE_RGBX_1010102_UBWC \ + v4l2_fourcc('Q', 'X', 'B', 'A') /* RGBX 10:10:10:2 UBWC */ +#define V4L2_PIX_FMT_SDE_Y_CBCR_H2V2_TP10 \ + v4l2_fourcc('T', 'P', '1', '0') /* Y/CbCr 4:2:0 TP10 */ +#define V4L2_PIX_FMT_SDE_Y_CBCR_H2V2_P010 \ + v4l2_fourcc('P', '0', '1', '0') /* Y/CbCr 4:2:0 P10 */ + /* SDR formats - used only for Software Defined Radio devices */ #define V4L2_SDR_FMT_CU8 v4l2_fourcc('C', 'U', '0', '8') /* IQ u8 */ #define V4L2_SDR_FMT_CU16LE v4l2_fourcc('C', 'U', '1', '6') /* IQ u16le */ @@ -907,6 +1004,21 @@ #define V4L2_BUF_FLAG_TSTAMP_SRC_SOE 0x00010000 /* mem2mem encoder/decoder */ #define V4L2_BUF_FLAG_LAST 0x00100000 +/* Vendor extensions */ +#define V4L2_QCOM_BUF_FLAG_CODECCONFIG 0x00020000 +#define V4L2_QCOM_BUF_FLAG_EOSEQ 0x00040000 +#define V4L2_QCOM_BUF_TIMESTAMP_INVALID 0x00080000 +#define V4L2_QCOM_BUF_FLAG_DECODEONLY 0x00200000 +#define V4L2_QCOM_BUF_DATA_CORRUPT 0x00400000 +#define V4L2_QCOM_BUF_DROP_FRAME 0x00800000 +#define V4L2_QCOM_BUF_INPUT_UNSUPPORTED 0x01000000 +#define V4L2_QCOM_BUF_FLAG_EOS 0x02000000 +#define V4L2_QCOM_BUF_FLAG_READONLY 0x04000000 +#define V4L2_MSM_VIDC_BUF_START_CODE_NOT_FOUND 0x08000000 +#define V4L2_MSM_BUF_FLAG_YUV_601_709_CLAMP 0x10000000 +#define V4L2_MSM_BUF_FLAG_MBAFF 0x20000000 +#define V4L2_MSM_BUF_FLAG_DEFER 0x40000000 +#define V4L2_QCOM_BUF_FLAG_IDRFRAME 0x80000000 /** * struct v4l2_exportbuffer - export of video buffer as DMABUF file descriptor @@ -1003,6 +1115,12 @@ /* Flags for 'capability' and 'capturemode' fields */ #define V4L2_MODE_HIGHQUALITY 0x0001 /* High quality imaging mode */ #define V4L2_CAP_TIMEPERFRAME 0x1000 /* timeperframe field is supported */ +#define V4L2_CAP_QCOM_FRAMESKIP 0x2000 /* frame skipping is supported */ + +struct v4l2_qcom_frameskip { + __u64 maxframeinterval; + __u8 fpsvariance; +}; struct v4l2_outputparm { __u32 capability; /* Supported modes */ @@ -1561,6 +1679,7 @@ #define V4L2_CTRL_FLAG_VOLATILE 0x0080 #define V4L2_CTRL_FLAG_HAS_PAYLOAD 0x0100 #define V4L2_CTRL_FLAG_EXECUTE_ON_WRITE 0x0200 +#define V4L2_CTRL_FLAG_MODIFY_LAYOUT 0X0400 /* Query flags, to be ORed with the control ID */ #define V4L2_CTRL_FLAG_NEXT_CTRL 0x80000000 @@ -1744,6 +1863,7 @@ #define V4L2_ENC_CMD_STOP (1) #define V4L2_ENC_CMD_PAUSE (2) #define V4L2_ENC_CMD_RESUME (3) +#define V4L2_ENC_QCOM_CMD_FLUSH (4) /* Flags for V4L2_ENC_CMD_STOP */ #define V4L2_ENC_CMD_STOP_AT_GOP_END (1 << 0) @@ -1763,6 +1883,8 @@ #define V4L2_DEC_CMD_STOP (1) #define V4L2_DEC_CMD_PAUSE (2) #define V4L2_DEC_CMD_RESUME (3) +#define V4L2_DEC_QCOM_CMD_FLUSH (4) +#define V4L2_DEC_QCOM_CMD_RECONFIG_HINT (5) /* Flags for V4L2_DEC_CMD_START */ #define V4L2_DEC_CMD_START_MUTE_AUDIO (1 << 0) @@ -1774,6 +1896,13 @@ #define V4L2_DEC_CMD_STOP_TO_BLACK (1 << 0) #define V4L2_DEC_CMD_STOP_IMMEDIATELY (1 << 1) +/* Flags for V4L2_DEC_QCOM_CMD_FLUSH */ +#define V4L2_DEC_QCOM_CMD_FLUSH_OUTPUT (1 << 0) +#define V4L2_DEC_QCOM_CMD_FLUSH_CAPTURE (1 << 1) + +#define V4L2_QCOM_CMD_FLUSH_OUTPUT (1 << 0) +#define V4L2_QCOM_CMD_FLUSH_CAPTURE (1 << 1) + /* Play format requirements (returned by the driver): */ /* The decoder has no special format requirements */ @@ -2039,6 +2168,56 @@ #define V4L2_EVENT_MOTION_DET 6 #define V4L2_EVENT_PRIVATE_START 0x08000000 +#define V4L2_EVENT_BITDEPTH_FLAG 0x1 +#define V4L2_EVENT_PICSTRUCT_FLAG 0x2 +#define V4L2_EVENT_COLOUR_SPACE_FLAG 0x4 + +#define V4L2_EVENT_MSM_VIDC_START (V4L2_EVENT_PRIVATE_START + 0x00001000) +#define V4L2_EVENT_MSM_VIDC_FLUSH_DONE (V4L2_EVENT_MSM_VIDC_START + 1) +#define V4L2_EVENT_MSM_VIDC_PORT_SETTINGS_CHANGED_SUFFICIENT \ + (V4L2_EVENT_MSM_VIDC_START + 2) +#define V4L2_EVENT_MSM_VIDC_PORT_SETTINGS_CHANGED_INSUFFICIENT \ + (V4L2_EVENT_MSM_VIDC_START + 3) +/* + * Bitdepth changed insufficient is deprecated now, however retaining + * to prevent changing the values of the other macros after bitdepth + */ +#define V4L2_EVENT_MSM_VIDC_PORT_SETTINGS_BITDEPTH_CHANGED_INSUFFICIENT \ + (V4L2_EVENT_MSM_VIDC_START + 4) +#define V4L2_EVENT_MSM_VIDC_SYS_ERROR (V4L2_EVENT_MSM_VIDC_START + 5) +#define V4L2_EVENT_MSM_VIDC_RELEASE_BUFFER_REFERENCE \ + (V4L2_EVENT_MSM_VIDC_START + 6) +#define V4L2_EVENT_MSM_VIDC_RELEASE_UNQUEUED_BUFFER \ + (V4L2_EVENT_MSM_VIDC_START + 7) +#define V4L2_EVENT_MSM_VIDC_HW_OVERLOAD (V4L2_EVENT_MSM_VIDC_START + 8) +#define V4L2_EVENT_MSM_VIDC_MAX_CLIENTS (V4L2_EVENT_MSM_VIDC_START + 9) +#define V4L2_EVENT_MSM_VIDC_HW_UNSUPPORTED (V4L2_EVENT_MSM_VIDC_START + 10) + +#define V4L2_EVENT_MSM_BA_PRIVATE_EVENT_BASE \ + (V4L2_EVENT_PRIVATE_START + 0x00005000) +#define V4L2_EVENT_MSM_BA_START V4L2_EVENT_MSM_BA_PRIVATE_EVENT_BASE +#define V4L2_EVENT_MSM_BA_DEVICE_AVAILABLE (V4L2_EVENT_MSM_BA_START + 1) +#define V4L2_EVENT_MSM_BA_DEVICE_UNAVAILABLE \ + (V4L2_EVENT_MSM_BA_START + 2) +#define V4L2_EVENT_MSM_BA_PORT_SETTINGS_CHANGED \ + (V4L2_EVENT_MSM_BA_START + 3) +#define V4L2_EVENT_MSM_BA_SIGNAL_IN_LOCK \ + (V4L2_EVENT_MSM_BA_START + 4) +#define V4L2_EVENT_MSM_BA_SIGNAL_LOST_LOCK \ + (V4L2_EVENT_MSM_BA_START + 5) +#define V4L2_EVENT_MSM_BA_SOURCE_CHANGE \ + (V4L2_EVENT_MSM_BA_START + 6) +#define V4L2_EVENT_MSM_BA_HDMI_HPD \ + (V4L2_EVENT_MSM_BA_START + 7) +#define V4L2_EVENT_MSM_BA_HDMI_CEC_MESSAGE \ + (V4L2_EVENT_MSM_BA_START + 8) +#define V4L2_EVENT_MSM_BA_CP \ + (V4L2_EVENT_MSM_BA_START + 9) +#define V4L2_EVENT_MSM_BA_CABLE_DETECT \ + (V4L2_EVENT_MSM_BA_START + 10) +#define V4L2_EVENT_MSM_BA_ERROR \ + (V4L2_EVENT_MSM_BA_START + 11) + /* Payload for V4L2_EVENT_VSYNC */ struct v4l2_event_vsync { /* Can be V4L2_FIELD_ANY, _NONE, _TOP or _BOTTOM */ @@ -2294,4 +2473,11 @@ #define BASE_VIDIOC_PRIVATE 192 /* 192-255 are private */ +/* HDMI rx provide ioctls */ +#define VIDIOC_HDMI_RX_CEC_S_LOGICAL _IOW('V', BASE_VIDIOC_PRIVATE + 0, int) +#define VIDIOC_HDMI_RX_CEC_CLEAR_LOGICAL _IO('V', BASE_VIDIOC_PRIVATE + 1) +#define VIDIOC_HDMI_RX_CEC_G_PHYSICAL _IOR('V', BASE_VIDIOC_PRIVATE + 2, int) +#define VIDIOC_HDMI_RX_CEC_G_CONNECTED _IOR('V', BASE_VIDIOC_PRIVATE + 3, int) +#define VIDIOC_HDMI_RX_CEC_S_ENABLE _IOR('V', BASE_VIDIOC_PRIVATE + 4, int) + #endif /* _UAPI__LINUX_VIDEODEV2_H */ diff -ruw linux-4.4.115/include/uapi/linux/xfrm.h linux-4.4.115-fbx/include/uapi/linux/xfrm.h --- linux-4.4.115/include/uapi/linux/xfrm.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/uapi/linux/xfrm.h 2019-01-22 16:16:28.599292554 +0100 @@ -302,6 +302,9 @@ XFRMA_SA_EXTRA_FLAGS, /* __u32 */ XFRMA_PROTO, /* __u8 */ XFRMA_ADDRESS_FILTER, /* struct xfrm_address_filter */ + XFRMA_PAD, + XFRMA_OFFLOAD_DEV, /* struct xfrm_state_offload */ + XFRMA_OUTPUT_MARK, /* __u32 */ __XFRMA_MAX #define XFRMA_MAX (__XFRMA_MAX - 1) diff -ruw linux-4.4.115/include/uapi/scsi/Kbuild linux-4.4.115-fbx/include/uapi/scsi/Kbuild --- linux-4.4.115/include/uapi/scsi/Kbuild 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/uapi/scsi/Kbuild 2019-01-22 16:16:28.603292590 +0100 @@ -1,5 +1,6 @@ # UAPI Header export list header-y += fc/ +header-y += ufs/ header-y += scsi_bsg_fc.h header-y += scsi_netlink.h header-y += scsi_netlink_fc.h diff -ruw linux-4.4.115/include/uapi/sound/asound.h linux-4.4.115-fbx/include/uapi/sound/asound.h --- linux-4.4.115/include/uapi/sound/asound.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/uapi/sound/asound.h 2019-01-22 16:16:28.607292626 +0100 @@ -102,9 +102,11 @@ SNDRV_HWDEP_IFACE_FW_OXFW, /* Oxford OXFW970/971 based device */ SNDRV_HWDEP_IFACE_FW_DIGI00X, /* Digidesign Digi 002/003 family */ SNDRV_HWDEP_IFACE_FW_TASCAM, /* TASCAM FireWire series */ + SNDRV_HWDEP_IFACE_AUDIO_BE, /* Backend Audio Control */ + SNDRV_HWDEP_IFACE_AUDIO_CODEC, /* codec Audio Control */ /* Don't forget to change the following: */ - SNDRV_HWDEP_IFACE_LAST = SNDRV_HWDEP_IFACE_FW_TASCAM + SNDRV_HWDEP_IFACE_LAST = SNDRV_HWDEP_IFACE_AUDIO_CODEC }; struct snd_hwdep_info { diff -ruw linux-4.4.115/include/uapi/sound/compress_offload.h linux-4.4.115-fbx/include/uapi/sound/compress_offload.h --- linux-4.4.115/include/uapi/sound/compress_offload.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/uapi/sound/compress_offload.h 2019-01-22 16:16:28.607292626 +0100 @@ -66,10 +66,11 @@ */ struct snd_compr_tstamp { __u32 byte_offset; - __u32 copied_total; + __u64 copied_total; __u32 pcm_frames; __u32 pcm_io_frames; __u32 sampling_rate; + __u64 timestamp; } __attribute__((packed, aligned(4))); /** @@ -122,17 +123,65 @@ } __attribute__((packed, aligned(4))); /** + * struct snd_compr_audio_info: compressed input audio information + * @frame_size: legth of the encoded frame with valid data + * @reserved: reserved for furture use + */ +struct snd_compr_audio_info { + __u32 frame_size; + __u32 reserved[15]; +} __attribute__((packed, aligned(4))); + +#define SNDRV_COMPRESS_RENDER_MODE_AUDIO_MASTER 0 +#define SNDRV_COMPRESS_RENDER_MODE_STC_MASTER 1 + +#define SNDRV_COMPRESS_CLK_REC_MODE_NONE 0 +#define SNDRV_COMPRESS_CLK_REC_MODE_AUTO 1 + +enum sndrv_compress_latency_mode { + SNDRV_COMPRESS_LEGACY_LATENCY_MODE = 0, + SNDRV_COMPRESS_LOW_LATENCY_MODE = 1, +}; + +/** * enum sndrv_compress_encoder * @SNDRV_COMPRESS_ENCODER_PADDING: no of samples appended by the encoder at the * end of the track * @SNDRV_COMPRESS_ENCODER_DELAY: no of samples inserted by the encoder at the * beginning of the track + * @SNDRV_COMPRESS_PATH_DELAY: dsp path delay in microseconds + * @SNDRV_COMPRESS_RENDER_MODE: dsp render mode (audio master or stc) + * @SNDRV_COMPRESS_CLK_REC_MODE: clock recovery mode ( none or auto) + * @SNDRV_COMPRESS_RENDER_WINDOW: render window + * @SNDRV_COMPRESS_START_DELAY: start delay + * @SNDRV_COMPRESS_ENABLE_ADJUST_SESSION_CLOCK: enable dsp drift correction + * @SNDRV_COMPRESS_ADJUST_SESSION_CLOCK: set drift correction value */ enum sndrv_compress_encoder { SNDRV_COMPRESS_ENCODER_PADDING = 1, SNDRV_COMPRESS_ENCODER_DELAY = 2, + SNDRV_COMPRESS_MIN_BLK_SIZE = 3, + SNDRV_COMPRESS_MAX_BLK_SIZE = 4, + SNDRV_COMPRESS_PATH_DELAY = 5, + SNDRV_COMPRESS_RENDER_MODE = 6, + SNDRV_COMPRESS_CLK_REC_MODE = 7, + SNDRV_COMPRESS_RENDER_WINDOW = 8, + SNDRV_COMPRESS_START_DELAY = 9, + SNDRV_COMPRESS_ENABLE_ADJUST_SESSION_CLOCK = 10, + SNDRV_COMPRESS_ADJUST_SESSION_CLOCK = 11, + SNDRV_COMPRESS_LATENCY_MODE = 12, }; +#define SNDRV_COMPRESS_PATH_DELAY SNDRV_COMPRESS_PATH_DELAY +#define SNDRV_COMPRESS_RENDER_MODE SNDRV_COMPRESS_RENDER_MODE +#define SNDRV_COMPRESS_CLK_REC_MODE SNDRV_COMPRESS_CLK_REC_MODE +#define SNDRV_COMPRESS_RENDER_WINDOW SNDRV_COMPRESS_RENDER_WINDOW +#define SNDRV_COMPRESS_START_DELAY SNDRV_COMPRESS_START_DELAY +#define SNDRV_COMPRESS_ENABLE_ADJUST_SESSION_CLOCK \ + SNDRV_COMPRESS_ENABLE_ADJUST_SESSION_CLOCK +#define SNDRV_COMPRESS_ADJUST_SESSION_CLOCK SNDRV_COMPRESS_ADJUST_SESSION_CLOCK +#define SNDRV_COMPRESS_LATENCY_MODE SNDRV_COMPRESS_LATENCY_MODE + /** * struct snd_compr_metadata - compressed stream metadata * @key: key id @@ -159,6 +208,8 @@ * SNDRV_COMPRESS_STOP: stop a running stream, discarding ring buffer content * and the buffers currently with DSP * SNDRV_COMPRESS_DRAIN: Play till end of buffers and stop after that + * SNDRV_COMPRESS_SET_NEXT_TRACK_PARAM: send codec specific data for the next + * track in gapless * SNDRV_COMPRESS_IOCTL_VERSION: Query the API version */ #define SNDRV_COMPRESS_IOCTL_VERSION _IOR('C', 0x00, int) @@ -180,6 +231,8 @@ #define SNDRV_COMPRESS_DRAIN _IO('C', 0x34) #define SNDRV_COMPRESS_NEXT_TRACK _IO('C', 0x35) #define SNDRV_COMPRESS_PARTIAL_DRAIN _IO('C', 0x36) +#define SNDRV_COMPRESS_SET_NEXT_TRACK_PARAM\ + _IOW('C', 0x80, union snd_codec_options) /* * TODO * 1. add mmap support diff -ruw linux-4.4.115/include/uapi/sound/compress_params.h linux-4.4.115-fbx/include/uapi/sound/compress_params.h --- linux-4.4.115/include/uapi/sound/compress_params.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/uapi/sound/compress_params.h 2019-01-22 16:16:28.607292626 +0100 @@ -53,12 +53,28 @@ #include +#define SND_DEC_DDP_MAX_PARAMS 18 + /* AUDIO CODECS SUPPORTED */ #define MAX_NUM_CODECS 32 #define MAX_NUM_CODEC_DESCRIPTORS 32 #define MAX_NUM_BITRATES 32 #define MAX_NUM_SAMPLE_RATES 32 +/* compressed TX */ +#define MAX_NUM_FRAMES_PER_BUFFER 1 +#define COMPRESSED_META_DATA_MODE 0x10 +#define META_DATA_LEN_BYTES 36 +#define Q6_AC3_DECODER 0x00010BF6 +#define Q6_EAC3_DECODER 0x00010C3C +#define Q6_DTS 0x00010D88 +#define Q6_DTS_LBR 0x00010DBB + +/* Timestamp flsg */ +/* Bit-0 - 1 : Enable Timestamp mode */ +/* Bit-0 - 0 : Disable Timestamp mode */ +#define COMPRESSED_TIMESTAMP_FLAG 0x0001 + /* Codecs are listed linearly to allow for extensibility */ #define SND_AUDIOCODEC_PCM ((__u32) 0x00000001) #define SND_AUDIOCODEC_MP3 ((__u32) 0x00000002) @@ -73,8 +89,23 @@ #define SND_AUDIOCODEC_IEC61937 ((__u32) 0x0000000B) #define SND_AUDIOCODEC_G723_1 ((__u32) 0x0000000C) #define SND_AUDIOCODEC_G729 ((__u32) 0x0000000D) -#define SND_AUDIOCODEC_MAX SND_AUDIOCODEC_G729 - +#define SND_AUDIOCODEC_DTS_PASS_THROUGH ((__u32) 0x0000000E) +#define SND_AUDIOCODEC_DTS_LBR ((__u32) 0x0000000F) +#define SND_AUDIOCODEC_DTS_TRANSCODE_LOOPBACK ((__u32) 0x00000010) +#define SND_AUDIOCODEC_PASS_THROUGH ((__u32) 0x00000011) +#define SND_AUDIOCODEC_MP2 ((__u32) 0x00000012) +#define SND_AUDIOCODEC_DTS_LBR_PASS_THROUGH ((__u32) 0x00000013) +#define SND_AUDIOCODEC_AC3 ((__u32) 0x00000014) +#define SND_AUDIOCODEC_AC3_PASS_THROUGH ((__u32) 0x00000015) +#define SND_AUDIOCODEC_WMA_PRO ((__u32) 0x00000016) +#define SND_AUDIOCODEC_DTS ((__u32) 0x00000017) +#define SND_AUDIOCODEC_EAC3 ((__u32) 0x00000018) +#define SND_AUDIOCODEC_ALAC ((__u32) 0x00000019) +#define SND_AUDIOCODEC_APE ((__u32) 0x00000020) +#define SND_AUDIOCODEC_DSD ((__u32) 0x00000021) +#define SND_AUDIOCODEC_APTX ((__u32) 0x00000022) +#define SND_AUDIOCODEC_TRUEHD ((__u32) 0x00000023) +#define SND_AUDIOCODEC_MAX SND_AUDIOCODEC_TRUEHD /* * Profile and modes are listed with bit masks. This allows for a * more compact representation of fields that will not evolve @@ -239,6 +270,12 @@ struct snd_enc_wma { __u32 super_block_align; /* WMA Type-specific data */ + __u32 bits_per_sample; + __u32 channelmask; + __u32 encodeopt; + __u32 encodeopt1; + __u32 encodeopt2; + __u32 avg_bit_rate; }; @@ -315,13 +352,71 @@ __s32 reserved[15]; } __attribute__((packed, aligned(4))); +struct snd_dec_ddp { + __u32 params_length; + __u32 params_id[SND_DEC_DDP_MAX_PARAMS]; + __u32 params_value[SND_DEC_DDP_MAX_PARAMS]; +} __attribute__((packed, aligned(4))); + +struct snd_dec_flac { + __u16 sample_size; + __u16 min_blk_size; + __u16 max_blk_size; + __u16 min_frame_size; + __u16 max_frame_size; +} __attribute__((packed, aligned(4))); + +struct snd_dec_vorbis { + __u32 bit_stream_fmt; +}; + +struct snd_dec_alac { + __u32 frame_length; + __u8 compatible_version; + __u8 bit_depth; + __u8 pb; + __u8 mb; + __u8 kb; + __u8 num_channels; + __u16 max_run; + __u32 max_frame_bytes; + __u32 avg_bit_rate; + __u32 sample_rate; + __u32 channel_layout_tag; +}; + +struct snd_dec_ape { + __u16 compatible_version; + __u16 compression_level; + __u32 format_flags; + __u32 blocks_per_frame; + __u32 final_frame_blocks; + __u32 total_frames; + __u16 bits_per_sample; + __u16 num_channels; + __u32 sample_rate; + __u32 seek_table_present; +}; + +struct snd_dec_aptx { + __u32 lap; + __u32 uap; + __u32 nap; +}; + union snd_codec_options { struct snd_enc_wma wma; struct snd_enc_vorbis vorbis; struct snd_enc_real real; struct snd_enc_flac flac; struct snd_enc_generic generic; -} __attribute__((packed, aligned(4))); + struct snd_dec_ddp ddp; + struct snd_dec_flac flac_dec; + struct snd_dec_vorbis vorbis_dec; + struct snd_dec_alac alac; + struct snd_dec_ape ape; + struct snd_dec_aptx aptx_dec; +}; /** struct snd_codec_desc - description of codec capabilities * @max_ch: Maximum number of audio channels @@ -397,8 +492,26 @@ __u32 ch_mode; __u32 format; __u32 align; + __u32 compr_passthr; union snd_codec_options options; - __u32 reserved[3]; + __u32 flags; + __u32 reserved[2]; } __attribute__((packed, aligned(4))); + +/** struct snd_codec_metadata + * @length: Length of the encoded buffer. + * @offset: Offset from the buffer address to the first byte of the first + * encoded frame. All encoded frames are consecutive starting + * from this offset. + * @timestamp: Session time in microseconds of the first sample in the buffer. + * @reserved: Reserved for future use. + */ +struct snd_codec_metadata { + __u32 length; + __u32 offset; + __u64 timestamp; + __u32 reserved[4]; +}; + #endif diff -ruw linux-4.4.115/include/uapi/sound/Kbuild linux-4.4.115-fbx/include/uapi/sound/Kbuild --- linux-4.4.115/include/uapi/sound/Kbuild 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/uapi/sound/Kbuild 2019-01-22 16:16:28.607292626 +0100 @@ -10,3 +10,12 @@ header-y += hdspm.h header-y += sb16_csp.h header-y += sfnt_info.h +header-y += tlv.h +header-y += lsm_params.h +header-y += audio_slimslave.h +header-y += voice_params.h +header-y += audio_effects.h +header-y += voice_svc.h +header-y += devdep_params.h +header-y += msmcal-hwdep.h +header-y += wcd-dsp-glink.h diff -ruw linux-4.4.115/include/uapi/video/Kbuild linux-4.4.115-fbx/include/uapi/video/Kbuild --- linux-4.4.115/include/uapi/video/Kbuild 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/include/uapi/video/Kbuild 2019-01-22 16:16:28.607292626 +0100 @@ -2,3 +2,5 @@ header-y += edid.h header-y += sisfb.h header-y += uvesafb.h +header-y += msm_hdmi_modes.h +header-y += msm_hdmi_hdcp_mgr.h diff -ruw linux-4.4.115/init/do_mounts.c linux-4.4.115-fbx/init/do_mounts.c --- linux-4.4.115/init/do_mounts.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/init/do_mounts.c 2019-01-22 16:16:28.623292771 +0100 @@ -566,6 +566,7 @@ wait_for_device_probe(); md_run_setup(); + dm_run_setup(); if (saved_root_name[0]) { root_device_name = saved_root_name; diff -ruw linux-4.4.115/init/do_mounts.h linux-4.4.115-fbx/init/do_mounts.h --- linux-4.4.115/init/do_mounts.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/init/do_mounts.h 2019-01-22 16:16:28.623292771 +0100 @@ -74,3 +74,13 @@ static inline void md_run_setup(void) {} #endif + +#ifdef CONFIG_BLK_DEV_DM + +void dm_run_setup(void); + +#else + +static inline void dm_run_setup(void) {} + +#endif diff -ruw linux-4.4.115/init/initramfs.c linux-4.4.115-fbx/init/initramfs.c --- linux-4.4.115/init/initramfs.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/init/initramfs.c 2019-01-22 16:16:28.623292771 +0100 @@ -18,6 +18,7 @@ #include #include #include +#include static ssize_t __init xwrite(int fd, const char *p, size_t count) { @@ -605,9 +606,28 @@ } #endif +static int __initdata do_skip_initramfs; + +static int __init skip_initramfs_param(char *str) +{ + if (*str) + return 0; + do_skip_initramfs = 1; + return 1; +} +__setup("skip_initramfs", skip_initramfs_param); + static int __init populate_rootfs(void) { - char *err = unpack_to_rootfs(__initramfs_start, __initramfs_size); + char *err; + + if (do_skip_initramfs) { + if (initrd_start) + free_initrd(); + return default_rootfs(); + } + + err = unpack_to_rootfs(__initramfs_start, __initramfs_size); if (err) panic("%s", err); /* Failed to decompress INTERNAL initramfs */ if (initrd_start) { @@ -628,7 +648,18 @@ fd = sys_open("/initrd.image", O_WRONLY|O_CREAT, 0700); if (fd >= 0) { - ssize_t written = xwrite(fd, (char *)initrd_start, + ssize_t written; +#ifdef CONFIG_FBX_DECRYPT_INITRD + int err; + extern int fbx_decrypt_initrd(char *start, + u32 size); + + err = fbx_decrypt_initrd((char*)initrd_start, + initrd_end - initrd_start); + if (err) + printk(KERN_ERR "Decrypt failed: %i\n", err); +#endif + written = xwrite(fd, (char *)initrd_start, initrd_end - initrd_start); if (written != initrd_end - initrd_start) diff -ruw linux-4.4.115/init/init_task.c linux-4.4.115-fbx/init/init_task.c --- linux-4.4.115/init/init_task.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/init/init_task.c 2019-01-22 16:16:28.623292771 +0100 @@ -22,5 +22,8 @@ * Initial thread structure. Alignment of this is handled by a special * linker map entry. */ -union thread_union init_thread_union __init_task_data = - { INIT_THREAD_INFO(init_task) }; +union thread_union init_thread_union __init_task_data = { +#ifndef CONFIG_THREAD_INFO_IN_TASK + INIT_THREAD_INFO(init_task) +#endif +}; diff -ruw linux-4.4.115/init/Kconfig linux-4.4.115-fbx/init/Kconfig --- linux-4.4.115/init/Kconfig 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/init/Kconfig 2019-10-29 09:26:25.557221909 +0100 @@ -26,6 +26,16 @@ config BUILDTIME_EXTABLE_SORT bool +config THREAD_INFO_IN_TASK + bool + help + Select this to move thread_info off the stack into task_struct. To + make this work, an arch will need to remove all thread_info fields + except flags and fix any runtime bugs. + + One subtle change that will be needed is to use try_get_task_stack() + and put_task_stack() in save_thread_stack_tsk() and get_wchan(). + menu "General setup" config BROKEN @@ -392,6 +402,16 @@ endchoice +config SCHED_WALT + bool "Support window based load tracking" + depends on SMP + depends on FAIR_GROUP_SCHED + help + This feature will allow the scheduler to maintain a tunable window + based set of metrics for tasks and runqueues. These metrics can be + used to guide task placement as well as task frequency requirements + for cpufreq governors. + config BSD_PROCESS_ACCT bool "BSD Process Accounting" depends on MULTIUSER @@ -866,6 +886,15 @@ 13 => 8 KB for each CPU 12 => 4 KB for each CPU +config FBX_DECRYPT_INITRD + bool "Decrypt initrd at boot" + depends on BLK_DEV_RAM + default n + +config FBX_DECRYPT_INITRD_KEY + string "Decryption key" + depends on FBX_DECRYPT_INITRD + # # Architectures with an unreliable sched_clock() should select this: # @@ -999,9 +1028,43 @@ Provides a simple Resource Controller for monitoring the total CPU consumed by the tasks in a cgroup. +config CGROUP_SCHEDTUNE + bool "CFS tasks boosting cgroup subsystem (EXPERIMENTAL)" + depends on SCHED_TUNE + help + This option provides the "schedtune" controller which improves the + flexibility of the task boosting mechanism by introducing the support + to define "per task" boost values. + + This new controller: + 1. allows only a two layers hierarchy, where the root defines the + system-wide boost value and its direct childrens define each one a + different "class of tasks" to be boosted with a different value + 2. supports up to 16 different task classes, each one which could be + configured with a different boost value + + Say N if unsure. + config PAGE_COUNTER bool +config CGROUP_SCHEDTUNE + bool "CFS tasks boosting cgroup subsystem (EXPERIMENTAL)" + depends on SCHED_TUNE + help + This option provides the "schedtune" controller which improves the + flexibility of the task boosting mechanism by introducing the support + to define "per task" boost values. + + This new controller: + 1. allows only a two layers hierarchy, where the root defines the + system-wide boost value and its direct childrens define each one a + different "class of tasks" to be boosted with a different value + 2. supports up to 16 different task classes, each one which could be + configured with a different boost value + + Say N if unsure. + config MEMCG bool "Memory Resource Controller for Control Groups" select PAGE_COUNTER @@ -1153,6 +1216,33 @@ endif # CGROUPS +config SCHED_HMP + bool "Scheduler support for heterogenous multi-processor systems" + depends on SMP && FAIR_GROUP_SCHED + help + This feature will let the scheduler optimize task placement on + systems made of heterogeneous cpus i.e cpus that differ either + in their instructions per-cycle capability or the maximum + frequency they can attain. + +config SCHED_HMP_CSTATE_AWARE + bool "CPU C-state aware scheduler" + depends on SCHED_HMP + help + This feature will let the HMP scheduler optimize task placement + with CPUs C-state. If this is enabled, scheduler places tasks + onto the shallowest C-state CPU among the most power efficient CPUs. + +config SCHED_CORE_CTL + bool "QTI Core Control" + depends on SMP + help + This options enables the core control functionality in + the scheduler. Core control automatically offline and + online cores based on cpu load and utilization. + + If unsure, say N here. + config CHECKPOINT_RESTORE bool "Checkpoint/restore support" if EXPERT select PROC_CHILDREN @@ -1237,6 +1327,43 @@ desktop applications. Task group autogeneration is currently based upon task session. +config SCHED_TUNE + bool "Boosting for CFS tasks (EXPERIMENTAL)" + depends on SMP + help + This option enables the system-wide support for task boosting. + When this support is enabled a new sysctl interface is exposed to + userspace via: + /proc/sys/kernel/sched_cfs_boost + which allows to set a system-wide boost value in range [0..100]. + + The currently boosting strategy is implemented in such a way that: + - a 0% boost value requires to operate in "standard" mode by + scheduling all tasks at the minimum capacities required by their + workload demand + - a 100% boost value requires to push at maximum the task + performances, "regardless" of the incurred energy consumption + + A boost value in between these two boundaries is used to bias the + power/performance trade-off, the higher the boost value the more the + scheduler is biased toward performance boosting instead of energy + efficiency. + + Since this support exposes a single system-wide knob, the specified + boost value is applied to all (CFS) tasks in the system. + + If unsure, say N. + +config DEFAULT_USE_ENERGY_AWARE + bool "Default to enabling the Energy Aware Scheduler feature" + default n + help + This option defaults the ENERGY_AWARE scheduling feature to true, + as without SCHED_DEBUG set this feature can't be enabled or disabled + via sysctl. + + Say N if unsure. + config SYSFS_DEPRECATED bool "Enable deprecated sysfs features to support old userspace tools" depends on SYSFS @@ -1355,7 +1482,6 @@ menuconfig EXPERT bool "Configure standard kernel features (expert users)" # Unhide debug options, to make the on-by-default options visible - select DEBUG_KERNEL help This option allows certain base kernel options and settings to be disabled or tweaked. This is for specialized @@ -1726,6 +1852,7 @@ config SLAB bool "SLAB" + select HAVE_HARDENED_USERCOPY_ALLOCATOR help The regular slab allocator that is established and known to work well in all environments. It organizes cache hot objects in @@ -1733,6 +1860,7 @@ config SLUB bool "SLUB (Unqueued Allocator)" + select HAVE_HARDENED_USERCOPY_ALLOCATOR help SLUB is a slab allocator that minimizes cache line usage instead of managing queues of cached objects (SLAB approach). diff -ruw linux-4.4.115/init/main.c linux-4.4.115-fbx/init/main.c --- linux-4.4.115/init/main.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/init/main.c 2019-10-29 09:26:25.561221948 +0100 @@ -94,9 +94,6 @@ extern void init_IRQ(void); extern void fork_init(void); extern void radix_tree_init(void); -#ifndef CONFIG_DEBUG_RODATA -static inline void mark_rodata_ro(void) { } -#endif /* * Debug helper: via this flag we know that we are in 'early bootup code' @@ -472,7 +469,7 @@ } # if THREAD_SIZE >= PAGE_SIZE -void __init __weak thread_info_cache_init(void) +void __init __weak thread_stack_cache_init(void) { } #endif @@ -510,11 +507,6 @@ smp_setup_processor_id(); debug_objects_early_init(); - /* - * Set up the the initial canary ASAP: - */ - boot_init_stack_canary(); - cgroup_init_early(); local_irq_disable(); @@ -528,6 +520,10 @@ page_address_init(); pr_notice("%s", linux_banner); setup_arch(&command_line); + /* + * Set up the the initial canary ASAP: + */ + boot_init_stack_canary(); mm_init_cpumask(&init_mm); setup_command_line(command_line); setup_nr_cpu_ids(); @@ -650,7 +646,7 @@ /* Should be run before the first non-init thread is created */ init_espfix_bsp(); #endif - thread_info_cache_init(); + thread_stack_cache_init(); cred_init(); fork_init(); proc_caches_init(); @@ -931,6 +927,28 @@ static noinline void __init kernel_init_freeable(void); +#ifdef CONFIG_DEBUG_RODATA +static bool rodata_enabled = true; +static int __init set_debug_rodata(char *str) +{ + return strtobool(str, &rodata_enabled); +} +__setup("rodata=", set_debug_rodata); + +static void mark_readonly(void) +{ + if (rodata_enabled) + mark_rodata_ro(); + else + pr_info("Kernel memory protection disabled.\n"); +} +#else +static inline void mark_readonly(void) +{ + pr_warn("This architecture does not have kernel memory protection.\n"); +} +#endif + static int __ref kernel_init(void *unused) { int ret; @@ -939,7 +957,7 @@ /* need to finish all async __init code before freeing the memory */ async_synchronize_full(); free_initmem(); - mark_rodata_ro(); + mark_readonly(); system_state = SYSTEM_RUNNING; numa_default_policy(); diff -ruw linux-4.4.115/init/Makefile linux-4.4.115-fbx/init/Makefile --- linux-4.4.115/init/Makefile 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/init/Makefile 2019-01-22 16:16:28.619292735 +0100 @@ -3,21 +3,20 @@ # obj-y := main.o version.o mounts.o -ifneq ($(CONFIG_BLK_DEV_INITRD),y) obj-y += noinitramfs.o -else obj-$(CONFIG_BLK_DEV_INITRD) += initramfs.o -endif obj-$(CONFIG_GENERIC_CALIBRATE_DELAY) += calibrate.o ifneq ($(CONFIG_ARCH_INIT_TASK),y) obj-y += init_task.o endif +obj-$(CONFIG_FBX_DECRYPT_INITRD)+= fbx_decrypt_initrd.o rc4.o mounts-y := do_mounts.o mounts-$(CONFIG_BLK_DEV_RAM) += do_mounts_rd.o mounts-$(CONFIG_BLK_DEV_INITRD) += do_mounts_initrd.o mounts-$(CONFIG_BLK_DEV_MD) += do_mounts_md.o +mounts-$(CONFIG_BLK_DEV_DM) += do_mounts_dm.o # dependencies on generated files need to be listed explicitly $(obj)/version.o: include/generated/compile.h diff -ruw linux-4.4.115/init/noinitramfs.c linux-4.4.115-fbx/init/noinitramfs.c --- linux-4.4.115/init/noinitramfs.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/init/noinitramfs.c 2019-01-22 16:16:28.623292771 +0100 @@ -21,11 +21,16 @@ #include #include #include +#include +#include /* * Create a simple rootfs that is similar to the default initramfs */ -static int __init default_rootfs(void) +#if !IS_BUILTIN(CONFIG_BLK_DEV_INITRD) +static +#endif +int __init default_rootfs(void) { int err; @@ -49,4 +54,6 @@ printk(KERN_WARNING "Failed to create a rootfs\n"); return err; } +#if !IS_BUILTIN(CONFIG_BLK_DEV_INITRD) rootfs_initcall(default_rootfs); +#endif diff -ruw linux-4.4.115/ipc/mqueue.c linux-4.4.115-fbx/ipc/mqueue.c --- linux-4.4.115/ipc/mqueue.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/ipc/mqueue.c 2019-10-29 09:26:25.561221948 +0100 @@ -747,7 +747,7 @@ } mode &= ~current_umask(); - ret = vfs_create(dir, path->dentry, mode, true); + ret = vfs_create2(path->mnt, dir, path->dentry, mode, true); path->dentry->d_fsdata = NULL; if (ret) return ERR_PTR(ret); @@ -763,7 +763,7 @@ if ((oflag & O_ACCMODE) == (O_RDWR | O_WRONLY)) return ERR_PTR(-EINVAL); acc = oflag2acc[oflag & O_ACCMODE]; - if (inode_permission(d_inode(path->dentry), acc)) + if (inode_permission2(path->mnt, d_inode(path->dentry), acc)) return ERR_PTR(-EACCES); return dentry_open(path, oflag, current_cred()); } @@ -796,7 +796,7 @@ ro = mnt_want_write(mnt); /* we'll drop it in any case */ error = 0; mutex_lock(&d_inode(root)->i_mutex); - path.dentry = lookup_one_len(name->name, root, strlen(name->name)); + path.dentry = lookup_one_len2(name->name, mnt, root, strlen(name->name)); if (IS_ERR(path.dentry)) { error = PTR_ERR(path.dentry); goto out_putfd; @@ -867,7 +867,7 @@ if (err) goto out_name; mutex_lock_nested(&d_inode(mnt->mnt_root)->i_mutex, I_MUTEX_PARENT); - dentry = lookup_one_len(name->name, mnt->mnt_root, + dentry = lookup_one_len2(name->name, mnt, mnt->mnt_root, strlen(name->name)); if (IS_ERR(dentry)) { err = PTR_ERR(dentry); @@ -879,7 +879,7 @@ err = -ENOENT; } else { ihold(inode); - err = vfs_unlink(d_inode(dentry->d_parent), dentry, NULL); + err = vfs_unlink2(mnt, d_inode(dentry->d_parent), dentry, NULL); } dput(dentry); diff -ruw linux-4.4.115/ipc/shm.c linux-4.4.115-fbx/ipc/shm.c --- linux-4.4.115/ipc/shm.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/ipc/shm.c 2019-10-29 09:26:25.561221948 +0100 @@ -1269,7 +1269,7 @@ int retval = -EINVAL; #ifdef CONFIG_MMU loff_t size = 0; - struct file *file; + struct file *file = NULL; struct vm_area_struct *next; #endif diff -ruw linux-4.4.115/Kbuild linux-4.4.115-fbx/Kbuild --- linux-4.4.115/Kbuild 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/Kbuild 2019-01-22 16:16:21.027223985 +0100 @@ -6,31 +6,6 @@ # 3) Generate asm-offsets.h (may need bounds.h and timeconst.h) # 4) Check for missing system calls -# Default sed regexp - multiline due to syntax constraints -define sed-y - "/^->/{s:->#\(.*\):/* \1 */:; \ - s:^->\([^ ]*\) [\$$#]*\([-0-9]*\) \(.*\):#define \1 \2 /* \3 */:; \ - s:^->\([^ ]*\) [\$$#]*\([^ ]*\) \(.*\):#define \1 \2 /* \3 */:; \ - s:->::; p;}" -endef - -# Use filechk to avoid rebuilds when a header changes, but the resulting file -# does not -define filechk_offsets - (set -e; \ - echo "#ifndef $2"; \ - echo "#define $2"; \ - echo "/*"; \ - echo " * DO NOT MODIFY."; \ - echo " *"; \ - echo " * This file was generated by Kbuild"; \ - echo " */"; \ - echo ""; \ - sed -ne $(sed-y); \ - echo ""; \ - echo "#endif" ) -endef - ##### # 1) Generate bounds.h diff -ruw linux-4.4.115/kernel/audit.c linux-4.4.115-fbx/kernel/audit.c --- linux-4.4.115/kernel/audit.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/kernel/audit.c 2019-10-29 09:26:25.565221987 +0100 @@ -870,6 +870,12 @@ return err; } if (s.mask & AUDIT_STATUS_PID) { + /* NOTE: we are using task_tgid_vnr() below because + * the s.pid value is relative to the namespace + * of the caller; at present this doesn't matter + * much since you can really only run auditd + * from the initial pid namespace, but something + * to keep in mind if this changes */ int new_pid = s.pid; if ((!new_pid) && (task_tgid_vnr(current) != audit_pid)) @@ -1896,7 +1902,7 @@ " euid=%u suid=%u fsuid=%u" " egid=%u sgid=%u fsgid=%u tty=%s ses=%u", task_ppid_nr(tsk), - task_pid_nr(tsk), + task_tgid_nr(tsk), from_kuid(&init_user_ns, audit_get_loginuid(tsk)), from_kuid(&init_user_ns, cred->uid), from_kgid(&init_user_ns, cred->gid), diff -ruw linux-4.4.115/kernel/auditsc.c linux-4.4.115-fbx/kernel/auditsc.c --- linux-4.4.115/kernel/auditsc.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/kernel/auditsc.c 2019-10-29 09:26:25.569222026 +0100 @@ -458,7 +458,7 @@ switch (f->type) { case AUDIT_PID: - pid = task_pid_nr(tsk); + pid = task_tgid_nr(tsk); result = audit_comparator(pid, f->op, f->val); break; case AUDIT_PPID: @@ -1987,7 +1987,7 @@ ab = audit_log_start(NULL, GFP_KERNEL, AUDIT_LOGIN); if (!ab) return; - audit_log_format(ab, "pid=%d uid=%u", task_pid_nr(current), uid); + audit_log_format(ab, "pid=%d uid=%u", task_tgid_nr(current), uid); audit_log_task_context(ab); audit_log_format(ab, " old-auid=%u auid=%u old-ses=%u ses=%u res=%d", oldloginuid, loginuid, oldsessionid, sessionid, !rc); @@ -2212,7 +2212,7 @@ { struct audit_context *context = current->audit_context; - context->target_pid = task_pid_nr(t); + context->target_pid = task_tgid_nr(t); context->target_auid = audit_get_loginuid(t); context->target_uid = task_uid(t); context->target_sessionid = audit_get_sessionid(t); @@ -2237,7 +2237,7 @@ if (audit_pid && t->tgid == audit_pid) { if (sig == SIGTERM || sig == SIGHUP || sig == SIGUSR1 || sig == SIGUSR2) { - audit_sig_pid = task_pid_nr(tsk); + audit_sig_pid = task_tgid_nr(tsk); if (uid_valid(tsk->loginuid)) audit_sig_uid = tsk->loginuid; else @@ -2337,7 +2337,7 @@ void __audit_log_capset(const struct cred *new, const struct cred *old) { struct audit_context *context = current->audit_context; - context->capset.pid = task_pid_nr(current); + context->capset.pid = task_tgid_nr(current); context->capset.cap.effective = new->cap_effective; context->capset.cap.inheritable = new->cap_effective; context->capset.cap.permitted = new->cap_permitted; @@ -2369,7 +2369,7 @@ from_kgid(&init_user_ns, gid), sessionid); audit_log_task_context(ab); - audit_log_format(ab, " pid=%d comm=", task_pid_nr(current)); + audit_log_format(ab, " pid=%d comm=", task_tgid_nr(current)); audit_log_untrustedstring(ab, get_task_comm(comm, current)); audit_log_d_path_exe(ab, current->mm); } diff -ruw linux-4.4.115/kernel/cgroup.c linux-4.4.115-fbx/kernel/cgroup.c --- linux-4.4.115/kernel/cgroup.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/kernel/cgroup.c 2019-01-22 16:16:28.639292916 +0100 @@ -211,6 +211,7 @@ /* Ditto for the can_fork callback. */ static unsigned long have_canfork_callback __read_mostly; +static struct file_system_type cgroup2_fs_type; static struct cftype cgroup_dfl_base_files[]; static struct cftype cgroup_legacy_base_files[]; @@ -716,10 +717,10 @@ if (to_cset) { /* - * We are synchronized through cgroup_threadgroup_rwsem - * against PF_EXITING setting such that we can't race - * against cgroup_exit() changing the css_set to - * init_css_set and dropping the old one. + * We are synchronized through css_set_lock against + * PF_EXITING setting such that we can't race against + * cgroup_exit() disassociating the task from the + * css_set. */ WARN_ON_ONCE(task->flags & PF_EXITING); @@ -784,6 +785,8 @@ static void put_css_set(struct css_set *cset) { + unsigned long flags; + /* * Ensure that the refcount doesn't hit zero while any readers * can see it. Similar to atomic_dec_and_lock(), but for an @@ -792,9 +795,9 @@ if (atomic_add_unless(&cset->refcount, -1, 1)) return; - spin_lock_bh(&css_set_lock); + spin_lock_irqsave(&css_set_lock, flags); put_css_set_locked(cset); - spin_unlock_bh(&css_set_lock); + spin_unlock_irqrestore(&css_set_lock, flags); } /* @@ -1017,11 +1020,11 @@ /* First see if we already have a cgroup group that matches * the desired set */ - spin_lock_bh(&css_set_lock); + spin_lock_irq(&css_set_lock); cset = find_existing_css_set(old_cset, cgrp, template); if (cset) get_css_set(cset); - spin_unlock_bh(&css_set_lock); + spin_unlock_irq(&css_set_lock); if (cset) return cset; @@ -1049,7 +1052,7 @@ * find_existing_css_set() */ memcpy(cset->subsys, template, sizeof(cset->subsys)); - spin_lock_bh(&css_set_lock); + spin_lock_irq(&css_set_lock); /* Add reference counts and links from the new css_set. */ list_for_each_entry(link, &old_cset->cgrp_links, cgrp_link) { struct cgroup *c = link->cgrp; @@ -1075,7 +1078,7 @@ css_get(css); } - spin_unlock_bh(&css_set_lock); + spin_unlock_irq(&css_set_lock); return cset; } @@ -1139,7 +1142,7 @@ * Release all the links from cset_links to this hierarchy's * root cgroup */ - spin_lock_bh(&css_set_lock); + spin_lock_irq(&css_set_lock); list_for_each_entry_safe(link, tmp_link, &cgrp->cset_links, cset_link) { list_del(&link->cset_link); @@ -1147,7 +1150,7 @@ kfree(link); } - spin_unlock_bh(&css_set_lock); + spin_unlock_irq(&css_set_lock); if (!list_empty(&root->root_list)) { list_del(&root->root_list); @@ -1551,11 +1554,11 @@ ss->root = dst_root; css->cgroup = dcgrp; - spin_lock_bh(&css_set_lock); + spin_lock_irq(&css_set_lock); hash_for_each(css_set_table, i, cset, hlist) list_move_tail(&cset->e_cset_node[ss->id], &dcgrp->e_csets[ss->id]); - spin_unlock_bh(&css_set_lock); + spin_unlock_irq(&css_set_lock); src_root->subsys_mask &= ~(1 << ssid); scgrp->subtree_control &= ~(1 << ssid); @@ -1650,10 +1653,6 @@ all_ss = true; continue; } - if (!strcmp(token, "__DEVEL__sane_behavior")) { - opts->flags |= CGRP_ROOT_SANE_BEHAVIOR; - continue; - } if (!strcmp(token, "noprefix")) { opts->flags |= CGRP_ROOT_NOPREFIX; continue; @@ -1720,15 +1719,6 @@ return -ENOENT; } - if (opts->flags & CGRP_ROOT_SANE_BEHAVIOR) { - pr_warn("sane_behavior: this is still under development and its behaviors will change, proceed at your own risk\n"); - if (nr_opts != 1) { - pr_err("sane_behavior: no other mount options allowed\n"); - return -EINVAL; - } - return 0; - } - /* * If the 'all' option was specified select all the subsystems, * otherwise if 'none', 'name=' and a subsystem name options were @@ -1832,7 +1822,7 @@ { struct task_struct *p, *g; - spin_lock_bh(&css_set_lock); + spin_lock_irq(&css_set_lock); if (use_task_css_set_links) goto out_unlock; @@ -1857,8 +1847,12 @@ * entry won't be deleted though the process has exited. * Do it while holding siglock so that we don't end up * racing against cgroup_exit(). + * + * Interrupts were already disabled while acquiring + * the css_set_lock, so we do not need to disable it + * again when acquiring the sighand->siglock here. */ - spin_lock_irq(&p->sighand->siglock); + spin_lock(&p->sighand->siglock); if (!(p->flags & PF_EXITING)) { struct css_set *cset = task_css_set(p); @@ -1867,11 +1861,11 @@ list_add_tail(&p->cg_list, &cset->tasks); get_css_set(cset); } - spin_unlock_irq(&p->sighand->siglock); + spin_unlock(&p->sighand->siglock); } while_each_thread(g, p); read_unlock(&tasklist_lock); out_unlock: - spin_unlock_bh(&css_set_lock); + spin_unlock_irq(&css_set_lock); } static void init_cgroup_housekeeping(struct cgroup *cgrp) @@ -1976,13 +1970,13 @@ * Link the root cgroup in this hierarchy into all the css_set * objects. */ - spin_lock_bh(&css_set_lock); + spin_lock_irq(&css_set_lock); hash_for_each(css_set_table, i, cset, hlist) { link_css_set(&tmp_links, cset, root_cgrp); if (css_set_populated(cset)) cgroup_update_populated(root_cgrp, true); } - spin_unlock_bh(&css_set_lock); + spin_unlock_irq(&css_set_lock); BUG_ON(!list_empty(&root_cgrp->self.children)); BUG_ON(atomic_read(&root->nr_cgrps) != 1); @@ -2007,9 +2001,10 @@ int flags, const char *unused_dev_name, void *data) { + bool is_v2 = fs_type == &cgroup2_fs_type; struct super_block *pinned_sb = NULL; struct cgroup_subsys *ss; - struct cgroup_root *root; + struct cgroup_root *root = NULL; struct cgroup_sb_opts opts; struct dentry *dentry; int ret; @@ -2023,6 +2018,17 @@ if (!use_task_css_set_links) cgroup_enable_task_cg_lists(); + if (is_v2) { + if (data) { + pr_err("cgroup2: unknown option \"%s\"\n", (char *)data); + return ERR_PTR(-EINVAL); + } + cgrp_dfl_root_visible = true; + root = &cgrp_dfl_root; + cgroup_get(&root->cgrp); + goto out_mount; + } + mutex_lock(&cgroup_mutex); /* First find the desired set of subsystems */ @@ -2030,15 +2036,6 @@ if (ret) goto out_unlock; - /* look for a matching existing root */ - if (opts.flags & CGRP_ROOT_SANE_BEHAVIOR) { - cgrp_dfl_root_visible = true; - root = &cgrp_dfl_root; - cgroup_get(&root->cgrp); - ret = 0; - goto out_unlock; - } - /* * Destruction of cgroup root is asynchronous, so subsystems may * still be dying after the previous unmount. Let's drain the @@ -2149,9 +2146,10 @@ if (ret) return ERR_PTR(ret); - +out_mount: dentry = kernfs_mount(fs_type, flags, root->kf_root, - CGROUP_SUPER_MAGIC, &new_sb); + is_v2 ? CGROUP2_SUPER_MAGIC : CGROUP_SUPER_MAGIC, + &new_sb); if (IS_ERR(dentry) || !new_sb) cgroup_put(&root->cgrp); @@ -2194,6 +2192,12 @@ .kill_sb = cgroup_kill_sb, }; +static struct file_system_type cgroup2_fs_type = { + .name = "cgroup2", + .mount = cgroup_mount, + .kill_sb = cgroup_kill_sb, +}; + /** * task_cgroup_path - cgroup path of a task in the first cgroup hierarchy * @task: target task @@ -2215,7 +2219,7 @@ char *path = NULL; mutex_lock(&cgroup_mutex); - spin_lock_bh(&css_set_lock); + spin_lock_irq(&css_set_lock); root = idr_get_next(&cgroup_hierarchy_idr, &hierarchy_id); @@ -2228,7 +2232,7 @@ path = buf; } - spin_unlock_bh(&css_set_lock); + spin_unlock_irq(&css_set_lock); mutex_unlock(&cgroup_mutex); return path; } @@ -2403,7 +2407,7 @@ * the new cgroup. There are no failure cases after here, so this * is the commit point. */ - spin_lock_bh(&css_set_lock); + spin_lock_irq(&css_set_lock); list_for_each_entry(cset, &tset->src_csets, mg_node) { list_for_each_entry_safe(task, tmp_task, &cset->mg_tasks, cg_list) { struct css_set *from_cset = task_css_set(task); @@ -2414,7 +2418,7 @@ put_css_set_locked(from_cset); } } - spin_unlock_bh(&css_set_lock); + spin_unlock_irq(&css_set_lock); /* * Migration is committed, all target tasks are now on dst_csets. @@ -2443,13 +2447,13 @@ } } out_release_tset: - spin_lock_bh(&css_set_lock); + spin_lock_irq(&css_set_lock); list_splice_init(&tset->dst_csets, &tset->src_csets); list_for_each_entry_safe(cset, tmp_cset, &tset->src_csets, mg_node) { list_splice_tail_init(&cset->mg_tasks, &cset->tasks); list_del_init(&cset->mg_node); } - spin_unlock_bh(&css_set_lock); + spin_unlock_irq(&css_set_lock); return ret; } @@ -2466,14 +2470,14 @@ lockdep_assert_held(&cgroup_mutex); - spin_lock_bh(&css_set_lock); + spin_lock_irq(&css_set_lock); list_for_each_entry_safe(cset, tmp_cset, preloaded_csets, mg_preload_node) { cset->mg_src_cgrp = NULL; cset->mg_dst_cset = NULL; list_del_init(&cset->mg_preload_node); put_css_set_locked(cset); } - spin_unlock_bh(&css_set_lock); + spin_unlock_irq(&css_set_lock); } /** @@ -2623,7 +2627,7 @@ * already PF_EXITING could be freed from underneath us unless we * take an rcu_read_lock. */ - spin_lock_bh(&css_set_lock); + spin_lock_irq(&css_set_lock); rcu_read_lock(); task = leader; do { @@ -2632,7 +2636,7 @@ break; } while_each_thread(leader, task); rcu_read_unlock(); - spin_unlock_bh(&css_set_lock); + spin_unlock_irq(&css_set_lock); return cgroup_taskset_migrate(&tset, cgrp); } @@ -2653,7 +2657,7 @@ int ret; /* look up all src csets */ - spin_lock_bh(&css_set_lock); + spin_lock_irq(&css_set_lock); rcu_read_lock(); task = leader; do { @@ -2663,7 +2667,7 @@ break; } while_each_thread(leader, task); rcu_read_unlock(); - spin_unlock_bh(&css_set_lock); + spin_unlock_irq(&css_set_lock); /* prepare dst csets and commit */ ret = cgroup_migrate_prepare_dst(dst_cgrp, &preloaded_csets); @@ -2688,7 +2692,8 @@ */ if (!uid_eq(cred->euid, GLOBAL_ROOT_UID) && !uid_eq(cred->euid, tcred->uid) && - !uid_eq(cred->euid, tcred->suid)) + !uid_eq(cred->euid, tcred->suid) && + !ns_capable(tcred->user_ns, CAP_SYS_NICE)) ret = -EACCES; if (!ret && cgroup_on_dfl(dst_cgrp)) { @@ -2696,9 +2701,9 @@ struct cgroup *cgrp; struct inode *inode; - spin_lock_bh(&css_set_lock); + spin_lock_irq(&css_set_lock); cgrp = task_cgroup_from_root(task, &cgrp_dfl_root); - spin_unlock_bh(&css_set_lock); + spin_unlock_irq(&css_set_lock); while (!cgroup_is_descendant(dst_cgrp, cgrp)) cgrp = cgroup_parent(cgrp); @@ -2794,20 +2799,22 @@ int retval = 0; mutex_lock(&cgroup_mutex); + percpu_down_write(&cgroup_threadgroup_rwsem); for_each_root(root) { struct cgroup *from_cgrp; if (root == &cgrp_dfl_root) continue; - spin_lock_bh(&css_set_lock); + spin_lock_irq(&css_set_lock); from_cgrp = task_cgroup_from_root(from, root); - spin_unlock_bh(&css_set_lock); + spin_unlock_irq(&css_set_lock); retval = cgroup_attach_task(from_cgrp, tsk, false); if (retval) break; } + percpu_up_write(&cgroup_threadgroup_rwsem); mutex_unlock(&cgroup_mutex); return retval; @@ -2927,7 +2934,7 @@ percpu_down_write(&cgroup_threadgroup_rwsem); /* look up all csses currently attached to @cgrp's subtree */ - spin_lock_bh(&css_set_lock); + spin_lock_irq(&css_set_lock); css_for_each_descendant_pre(css, cgroup_css(cgrp, NULL)) { struct cgrp_cset_link *link; @@ -2939,14 +2946,14 @@ cgroup_migrate_add_src(link->cset, cgrp, &preloaded_csets); } - spin_unlock_bh(&css_set_lock); + spin_unlock_irq(&css_set_lock); /* NULL dst indicates self on default hierarchy */ ret = cgroup_migrate_prepare_dst(NULL, &preloaded_csets); if (ret) goto out_finish; - spin_lock_bh(&css_set_lock); + spin_lock_irq(&css_set_lock); list_for_each_entry(src_cset, &preloaded_csets, mg_preload_node) { struct task_struct *task, *ntask; @@ -2958,7 +2965,7 @@ list_for_each_entry_safe(task, ntask, &src_cset->tasks, cg_list) cgroup_taskset_add(task, &tset); } - spin_unlock_bh(&css_set_lock); + spin_unlock_irq(&css_set_lock); ret = cgroup_taskset_migrate(&tset, cgrp); out_finish: @@ -3641,10 +3648,10 @@ int count = 0; struct cgrp_cset_link *link; - spin_lock_bh(&css_set_lock); + spin_lock_irq(&css_set_lock); list_for_each_entry(link, &cgrp->cset_links, cset_link) count += atomic_read(&link->cset->refcount); - spin_unlock_bh(&css_set_lock); + spin_unlock_irq(&css_set_lock); return count; } @@ -3982,7 +3989,7 @@ memset(it, 0, sizeof(*it)); - spin_lock_bh(&css_set_lock); + spin_lock_irq(&css_set_lock); it->ss = css->ss; @@ -3995,7 +4002,7 @@ css_task_iter_advance_css_set(it); - spin_unlock_bh(&css_set_lock); + spin_unlock_irq(&css_set_lock); } /** @@ -4013,7 +4020,7 @@ it->cur_task = NULL; } - spin_lock_bh(&css_set_lock); + spin_lock_irq(&css_set_lock); if (it->task_pos) { it->cur_task = list_entry(it->task_pos, struct task_struct, @@ -4022,7 +4029,7 @@ css_task_iter_advance(it); } - spin_unlock_bh(&css_set_lock); + spin_unlock_irq(&css_set_lock); return it->cur_task; } @@ -4036,10 +4043,10 @@ void css_task_iter_end(struct css_task_iter *it) { if (it->cur_cset) { - spin_lock_bh(&css_set_lock); + spin_lock_irq(&css_set_lock); list_del(&it->iters_node); put_css_set_locked(it->cur_cset); - spin_unlock_bh(&css_set_lock); + spin_unlock_irq(&css_set_lock); } if (it->cur_task) @@ -4067,11 +4074,13 @@ mutex_lock(&cgroup_mutex); + percpu_down_write(&cgroup_threadgroup_rwsem); + /* all tasks in @from are being moved, all csets are source */ - spin_lock_bh(&css_set_lock); + spin_lock_irq(&css_set_lock); list_for_each_entry(link, &from->cset_links, cset_link) cgroup_migrate_add_src(link->cset, to, &preloaded_csets); - spin_unlock_bh(&css_set_lock); + spin_unlock_irq(&css_set_lock); ret = cgroup_migrate_prepare_dst(to, &preloaded_csets); if (ret) @@ -4083,7 +4092,11 @@ */ do { css_task_iter_start(&from->self, &it); + + do { task = css_task_iter_next(&it); + } while (task && (task->flags & PF_EXITING)); + if (task) get_task_struct(task); css_task_iter_end(&it); @@ -4095,6 +4108,7 @@ } while (task && !ret); out_err: cgroup_migrate_finish(&preloaded_csets); + percpu_up_write(&cgroup_threadgroup_rwsem); mutex_unlock(&cgroup_mutex); return ret; } @@ -5176,10 +5190,10 @@ */ cgrp->self.flags &= ~CSS_ONLINE; - spin_lock_bh(&css_set_lock); + spin_lock_irq(&css_set_lock); list_for_each_entry(link, &cgrp->cset_links, cset_link) link->cset->dead = true; - spin_unlock_bh(&css_set_lock); + spin_unlock_irq(&css_set_lock); /* initiate massacre of all css's */ for_each_css(css, ssid, cgrp) @@ -5329,6 +5343,12 @@ BUG_ON(cgroup_init_cftypes(NULL, cgroup_dfl_base_files)); BUG_ON(cgroup_init_cftypes(NULL, cgroup_legacy_base_files)); + /* + * The latency of the synchronize_sched() is too high for cgroups, + * avoid it at the cost of forcing all readers into the slow path. + */ + rcu_sync_enter_start(&cgroup_threadgroup_rwsem.rss); + mutex_lock(&cgroup_mutex); /* Add init_css_set to the hash table */ @@ -5384,6 +5404,7 @@ WARN_ON(sysfs_create_mount_point(fs_kobj, "cgroup")); WARN_ON(register_filesystem(&cgroup_fs_type)); + WARN_ON(register_filesystem(&cgroup2_fs_type)); WARN_ON(!proc_create("cgroups", 0, NULL, &proc_cgroupstats_operations)); return 0; @@ -5432,7 +5453,7 @@ goto out; mutex_lock(&cgroup_mutex); - spin_lock_bh(&css_set_lock); + spin_lock_irq(&css_set_lock); for_each_root(root) { struct cgroup_subsys *ss; @@ -5484,7 +5505,7 @@ retval = 0; out_unlock: - spin_unlock_bh(&css_set_lock); + spin_unlock_irq(&css_set_lock); mutex_unlock(&cgroup_mutex); kfree(buf); out: @@ -5645,13 +5666,13 @@ if (use_task_css_set_links) { struct css_set *cset; - spin_lock_bh(&css_set_lock); + spin_lock_irq(&css_set_lock); cset = task_css_set(current); if (list_empty(&child->cg_list)) { get_css_set(cset); css_set_move_task(child, NULL, cset, false); } - spin_unlock_bh(&css_set_lock); + spin_unlock_irq(&css_set_lock); } /* @@ -5689,19 +5710,22 @@ int i; /* - * Unlink from @tsk from its css_set. As migration path can't race - * with us, we can check css_set and cg_list without synchronization. + * Avoid potential race with the migrate path. + */ + spin_lock_irq(&css_set_lock); + /* + * Unlink from @tsk from its css_set. */ cset = task_css_set(tsk); if (!list_empty(&tsk->cg_list)) { - spin_lock_bh(&css_set_lock); css_set_move_task(tsk, cset, NULL, false); - spin_unlock_bh(&css_set_lock); } else { get_css_set(cset); } + spin_unlock_irq(&css_set_lock); + /* see cgroup_post_fork() for details */ for_each_subsys_which(ss, i, &have_exit_callback) ss->exit(tsk); @@ -5763,7 +5787,9 @@ if (!pathbuf || !agentbuf) goto out; + spin_lock_irq(&css_set_lock); path = cgroup_path(cgrp, pathbuf, PATH_MAX); + spin_unlock_irq(&css_set_lock); if (!path) goto out; @@ -5910,7 +5936,7 @@ if (!name_buf) return -ENOMEM; - spin_lock_bh(&css_set_lock); + spin_lock_irq(&css_set_lock); rcu_read_lock(); cset = rcu_dereference(current->cgroups); list_for_each_entry(link, &cset->cgrp_links, cgrp_link) { @@ -5921,7 +5947,7 @@ c->root->hierarchy_id, name_buf); } rcu_read_unlock(); - spin_unlock_bh(&css_set_lock); + spin_unlock_irq(&css_set_lock); kfree(name_buf); return 0; } @@ -5932,13 +5958,13 @@ struct cgroup_subsys_state *css = seq_css(seq); struct cgrp_cset_link *link; - spin_lock_bh(&css_set_lock); + spin_lock_irq(&css_set_lock); list_for_each_entry(link, &css->cgroup->cset_links, cset_link) { struct css_set *cset = link->cset; struct task_struct *task; int count = 0; - seq_printf(seq, "css_set %p\n", cset); + seq_printf(seq, "css_set %pK\n", cset); list_for_each_entry(task, &cset->tasks, cg_list) { if (count++ > MAX_TASKS_SHOWN_PER_CSS) @@ -5955,7 +5981,7 @@ overflow: seq_puts(seq, " ...\n"); } - spin_unlock_bh(&css_set_lock); + spin_unlock_irq(&css_set_lock); return 0; } diff -ruw linux-4.4.115/kernel/cpu.c linux-4.4.115-fbx/kernel/cpu.c --- linux-4.4.115/kernel/cpu.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/kernel/cpu.c 2019-10-29 09:26:25.573222065 +0100 @@ -24,6 +24,8 @@ #include #include +#include + #include "smpboot.h" #ifdef CONFIG_SMP @@ -89,6 +91,11 @@ #define cpuhp_lock_acquire() lock_map_acquire(&cpu_hotplug.dep_map) #define cpuhp_lock_release() lock_map_release(&cpu_hotplug.dep_map) +void cpu_hotplug_mutex_held(void) +{ + lockdep_assert_held(&cpu_hotplug.lock); +} +EXPORT_SYMBOL(cpu_hotplug_mutex_held); void get_online_cpus(void) { @@ -183,10 +190,17 @@ } EXPORT_SYMBOL_GPL(cpu_hotplug_disable); +static void __cpu_hotplug_enable(void) +{ + if (WARN_ONCE(!cpu_hotplug_disabled, "Unbalanced cpu hotplug enable\n")) + return; + cpu_hotplug_disabled--; +} + void cpu_hotplug_enable(void) { cpu_maps_update_begin(); - WARN_ON(--cpu_hotplug_disabled < 0); + __cpu_hotplug_enable(); cpu_maps_update_done(); } EXPORT_SYMBOL_GPL(cpu_hotplug_enable); @@ -352,6 +366,9 @@ if (!cpu_online(cpu)) return -EINVAL; + if (!tasks_frozen && !cpu_isolated(cpu) && num_online_uniso_cpus() == 1) + return -EBUSY; + cpu_hotplug_begin(); err = __cpu_notify(CPU_DOWN_PREPARE | mod, hcpu, -1, &nr_calls); @@ -425,6 +442,7 @@ out_release: cpu_hotplug_done(); + trace_sched_cpu_hotplug(cpu, err, 0); if (!err) cpu_notify_nofail(CPU_POST_DEAD | mod, hcpu); return err; @@ -510,7 +528,7 @@ ret = __cpu_notify(CPU_UP_PREPARE | mod, hcpu, -1, &nr_calls); if (ret) { nr_calls--; - pr_warn("%s: attempt to bring up CPU %u failed\n", + pr_warn_ratelimited("%s: attempt to bring up CPU %u failed\n", __func__, cpu); goto out_notify; } @@ -530,13 +548,46 @@ __cpu_notify(CPU_UP_CANCELED | mod, hcpu, nr_calls, NULL); out: cpu_hotplug_done(); + trace_sched_cpu_hotplug(cpu, ret, 1); return ret; } +static int switch_to_rt_policy(void) +{ + struct sched_param param = { .sched_priority = MAX_RT_PRIO - 1 }; + unsigned int policy = current->policy; + int err; + + /* Nobody should be attempting hotplug from these policy contexts. */ + if (policy == SCHED_BATCH || policy == SCHED_IDLE || + policy == SCHED_DEADLINE) + return -EPERM; + + if (policy == SCHED_FIFO || policy == SCHED_RR) + return 1; + + /* Only SCHED_NORMAL left. */ + err = sched_setscheduler_nocheck(current, SCHED_FIFO, ¶m); + return err; + +} + +static int switch_to_fair_policy(void) +{ + struct sched_param param = { .sched_priority = 0 }; + + return sched_setscheduler_nocheck(current, SCHED_NORMAL, ¶m); +} + int cpu_up(unsigned int cpu) { int err = 0; + int switch_err = 0; + + switch_err = switch_to_rt_policy(); + if (switch_err < 0) + return switch_err; if (!cpu_possible(cpu)) { pr_err("can't online cpu %d because it is not configured as may-hotadd at boot time\n", @@ -562,6 +613,14 @@ out: cpu_maps_update_done(); + + if (!switch_err) { + switch_err = switch_to_fair_policy(); + if (switch_err) + pr_err("Hotplug policy switch err=%d Task %s pid=%d\n", + switch_err, current->comm, current->pid); + } + return err; } EXPORT_SYMBOL_GPL(cpu_up); @@ -623,10 +682,11 @@ void enable_nonboot_cpus(void) { int cpu, error; + struct device *cpu_device; /* Allow everyone to use the CPU hotplug again */ cpu_maps_update_begin(); - WARN_ON(--cpu_hotplug_disabled < 0); + __cpu_hotplug_enable(); if (cpumask_empty(frozen_cpus)) goto out; @@ -640,6 +700,12 @@ trace_suspend_resume(TPS("CPU_ON"), cpu, false); if (!error) { pr_info("CPU%d is up\n", cpu); + cpu_device = get_cpu_device(cpu); + if (!cpu_device) + pr_err("%s: failed to get cpu%d device\n", + __func__, cpu); + else + kobject_uevent(&cpu_device->kobj, KOBJ_ONLINE); continue; } pr_warn("Error taking CPU%d up: %d\n", cpu, error); @@ -779,6 +845,10 @@ const struct cpumask *const cpu_active_mask = to_cpumask(cpu_active_bits); EXPORT_SYMBOL(cpu_active_mask); +static DECLARE_BITMAP(cpu_isolated_bits, CONFIG_NR_CPUS) __read_mostly; +const struct cpumask *const cpu_isolated_mask = to_cpumask(cpu_isolated_bits); +EXPORT_SYMBOL(cpu_isolated_mask); + void set_cpu_possible(unsigned int cpu, bool possible) { if (possible) @@ -813,6 +883,14 @@ cpumask_clear_cpu(cpu, to_cpumask(cpu_active_bits)); } +void set_cpu_isolated(unsigned int cpu, bool isolated) +{ + if (isolated) + cpumask_set_cpu(cpu, to_cpumask(cpu_isolated_bits)); + else + cpumask_clear_cpu(cpu, to_cpumask(cpu_isolated_bits)); +} + void init_cpu_present(const struct cpumask *src) { cpumask_copy(to_cpumask(cpu_present_bits), src); @@ -827,3 +905,28 @@ { cpumask_copy(to_cpumask(cpu_online_bits), src); } + +void init_cpu_isolated(const struct cpumask *src) +{ + cpumask_copy(to_cpumask(cpu_isolated_bits), src); +} + +static ATOMIC_NOTIFIER_HEAD(idle_notifier); + +void idle_notifier_register(struct notifier_block *n) +{ + atomic_notifier_chain_register(&idle_notifier, n); +} +EXPORT_SYMBOL_GPL(idle_notifier_register); + +void idle_notifier_unregister(struct notifier_block *n) +{ + atomic_notifier_chain_unregister(&idle_notifier, n); +} +EXPORT_SYMBOL_GPL(idle_notifier_unregister); + +void idle_notifier_call_chain(unsigned long val) +{ + atomic_notifier_call_chain(&idle_notifier, val, NULL); +} +EXPORT_SYMBOL_GPL(idle_notifier_call_chain); diff -ruw linux-4.4.115/kernel/cpu_pm.c linux-4.4.115-fbx/kernel/cpu_pm.c --- linux-4.4.115/kernel/cpu_pm.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/kernel/cpu_pm.c 2019-01-22 16:16:28.639292916 +0100 @@ -22,14 +22,17 @@ #include #include +bool from_suspend = false; + static DEFINE_RWLOCK(cpu_pm_notifier_lock); static RAW_NOTIFIER_HEAD(cpu_pm_notifier_chain); -static int cpu_pm_notify(enum cpu_pm_event event, int nr_to_call, int *nr_calls) +static int cpu_pm_notify(enum cpu_pm_event event, int nr_to_call, int *nr_calls, + void *data) { int ret; - ret = __raw_notifier_call_chain(&cpu_pm_notifier_chain, event, NULL, + ret = __raw_notifier_call_chain(&cpu_pm_notifier_chain, event, data, nr_to_call, nr_calls); return notifier_to_errno(ret); @@ -101,13 +104,13 @@ int ret = 0; read_lock(&cpu_pm_notifier_lock); - ret = cpu_pm_notify(CPU_PM_ENTER, -1, &nr_calls); + ret = cpu_pm_notify(CPU_PM_ENTER, -1, &nr_calls, NULL); if (ret) /* * Inform listeners (nr_calls - 1) about failure of CPU PM * PM entry who are notified earlier to prepare for it. */ - cpu_pm_notify(CPU_PM_ENTER_FAILED, nr_calls - 1, NULL); + cpu_pm_notify(CPU_PM_ENTER_FAILED, nr_calls - 1, NULL, NULL); read_unlock(&cpu_pm_notifier_lock); return ret; @@ -131,7 +134,7 @@ int ret; read_lock(&cpu_pm_notifier_lock); - ret = cpu_pm_notify(CPU_PM_EXIT, -1, NULL); + ret = cpu_pm_notify(CPU_PM_EXIT, -1, NULL, NULL); read_unlock(&cpu_pm_notifier_lock); return ret; @@ -154,19 +157,21 @@ * * Return conditions are same as __raw_notifier_call_chain. */ -int cpu_cluster_pm_enter(void) +int cpu_cluster_pm_enter(unsigned long aff_level) { int nr_calls; int ret = 0; read_lock(&cpu_pm_notifier_lock); - ret = cpu_pm_notify(CPU_CLUSTER_PM_ENTER, -1, &nr_calls); + ret = cpu_pm_notify(CPU_CLUSTER_PM_ENTER, -1, &nr_calls, + (void *) aff_level); if (ret) /* * Inform listeners (nr_calls - 1) about failure of CPU cluster * PM entry who are notified earlier to prepare for it. */ - cpu_pm_notify(CPU_CLUSTER_PM_ENTER_FAILED, nr_calls - 1, NULL); + cpu_pm_notify(CPU_CLUSTER_PM_ENTER_FAILED, nr_calls - 1, NULL, + (void *) aff_level); read_unlock(&cpu_pm_notifier_lock); return ret; @@ -188,12 +193,12 @@ * * Return conditions are same as __raw_notifier_call_chain. */ -int cpu_cluster_pm_exit(void) +int cpu_cluster_pm_exit(unsigned long aff_level) { int ret; read_lock(&cpu_pm_notifier_lock); - ret = cpu_pm_notify(CPU_CLUSTER_PM_EXIT, -1, NULL); + ret = cpu_pm_notify(CPU_CLUSTER_PM_EXIT, -1, NULL, (void *) aff_level); read_unlock(&cpu_pm_notifier_lock); return ret; @@ -205,17 +210,19 @@ { int ret; + from_suspend = true; ret = cpu_pm_enter(); if (ret) return ret; - ret = cpu_cluster_pm_enter(); + ret = cpu_cluster_pm_enter(0); return ret; } static void cpu_pm_resume(void) { - cpu_cluster_pm_exit(); + from_suspend = false; + cpu_cluster_pm_exit(0); cpu_pm_exit(); } diff -ruw linux-4.4.115/kernel/cpuset.c linux-4.4.115-fbx/kernel/cpuset.c --- linux-4.4.115/kernel/cpuset.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/kernel/cpuset.c 2019-10-29 09:26:25.577222104 +0100 @@ -99,6 +99,7 @@ /* user-configured CPUs and Memory Nodes allow to tasks */ cpumask_var_t cpus_allowed; + cpumask_var_t cpus_requested; /* CPUS requested, but not used because of hotplug */ nodemask_t mems_allowed; /* effective CPUs and Memory Nodes allow to tasks */ @@ -398,7 +399,7 @@ static int is_cpuset_subset(const struct cpuset *p, const struct cpuset *q) { - return cpumask_subset(p->cpus_allowed, q->cpus_allowed) && + return cpumask_subset(p->cpus_requested, q->cpus_requested) && nodes_subset(p->mems_allowed, q->mems_allowed) && is_cpu_exclusive(p) <= is_cpu_exclusive(q) && is_mem_exclusive(p) <= is_mem_exclusive(q); @@ -498,7 +499,7 @@ cpuset_for_each_child(c, css, par) { if ((is_cpu_exclusive(trial) || is_cpu_exclusive(c)) && c != cur && - cpumask_intersects(trial->cpus_allowed, c->cpus_allowed)) + cpumask_intersects(trial->cpus_requested, c->cpus_requested)) goto out; if ((is_mem_exclusive(trial) || is_mem_exclusive(c)) && c != cur && @@ -806,16 +807,15 @@ * 'cpus' is removed, then call this routine to rebuild the * scheduler's dynamic sched domains. * - * Call with cpuset_mutex held. Takes get_online_cpus(). */ -static void rebuild_sched_domains_locked(void) +static void rebuild_sched_domains_unlocked(void) { struct sched_domain_attr *attr; cpumask_var_t *doms; int ndoms; + cpu_hotplug_mutex_held(); lockdep_assert_held(&cpuset_mutex); - get_online_cpus(); /* * We have raced with CPU hotplug. Don't do anything to avoid @@ -823,27 +823,27 @@ * Anyways, hotplug work item will rebuild sched domains. */ if (!cpumask_equal(top_cpuset.effective_cpus, cpu_active_mask)) - goto out; + return; /* Generate domain masks and attrs */ ndoms = generate_sched_domains(&doms, &attr); /* Have scheduler rebuild the domains */ partition_sched_domains(ndoms, doms, attr); -out: - put_online_cpus(); } #else /* !CONFIG_SMP */ -static void rebuild_sched_domains_locked(void) +static void rebuild_sched_domains_unlocked(void) { } #endif /* CONFIG_SMP */ void rebuild_sched_domains(void) { + get_online_cpus(); mutex_lock(&cpuset_mutex); - rebuild_sched_domains_locked(); + rebuild_sched_domains_unlocked(); mutex_unlock(&cpuset_mutex); + put_online_cpus(); } /** @@ -875,7 +875,6 @@ * * On legacy hierachy, effective_cpus will be the same with cpu_allowed. * - * Called with cpuset_mutex held */ static void update_cpumasks_hier(struct cpuset *cs, struct cpumask *new_cpus) { @@ -930,7 +929,7 @@ rcu_read_unlock(); if (need_rebuild_sched_domains) - rebuild_sched_domains_locked(); + rebuild_sched_domains_unlocked(); } /** @@ -957,17 +956,18 @@ if (!*buf) { cpumask_clear(trialcs->cpus_allowed); } else { - retval = cpulist_parse(buf, trialcs->cpus_allowed); + retval = cpulist_parse(buf, trialcs->cpus_requested); if (retval < 0) return retval; - if (!cpumask_subset(trialcs->cpus_allowed, - top_cpuset.cpus_allowed)) + if (!cpumask_subset(trialcs->cpus_requested, cpu_present_mask)) return -EINVAL; + + cpumask_and(trialcs->cpus_allowed, trialcs->cpus_requested, cpu_active_mask); } /* Nothing to do if the cpus didn't change */ - if (cpumask_equal(cs->cpus_allowed, trialcs->cpus_allowed)) + if (cpumask_equal(cs->cpus_requested, trialcs->cpus_requested)) return 0; retval = validate_change(cs, trialcs); @@ -976,6 +976,7 @@ spin_lock_irq(&callback_lock); cpumask_copy(cs->cpus_allowed, trialcs->cpus_allowed); + cpumask_copy(cs->cpus_requested, trialcs->cpus_requested); spin_unlock_irq(&callback_lock); /* use trialcs->cpus_allowed as a temp variable */ @@ -1287,7 +1288,7 @@ cs->relax_domain_level = val; if (!cpumask_empty(cs->cpus_allowed) && is_sched_load_balance(cs)) - rebuild_sched_domains_locked(); + rebuild_sched_domains_unlocked(); } return 0; @@ -1318,7 +1319,6 @@ * cs: the cpuset to update * turning_on: whether the flag is being set or cleared * - * Call with cpuset_mutex held. */ static int update_flag(cpuset_flagbits_t bit, struct cpuset *cs, @@ -1353,7 +1353,7 @@ spin_unlock_irq(&callback_lock); if (!cpumask_empty(trialcs->cpus_allowed) && balance_flag_changed) - rebuild_sched_domains_locked(); + rebuild_sched_domains_unlocked(); if (spread_flag_changed) update_tasks_flags(cs); @@ -1618,6 +1618,7 @@ cpuset_filetype_t type = cft->private; int retval = 0; + get_online_cpus(); mutex_lock(&cpuset_mutex); if (!is_cpuset_online(cs)) { retval = -ENODEV; @@ -1655,6 +1656,7 @@ } out_unlock: mutex_unlock(&cpuset_mutex); + put_online_cpus(); return retval; } @@ -1665,6 +1667,7 @@ cpuset_filetype_t type = cft->private; int retval = -ENODEV; + get_online_cpus(); mutex_lock(&cpuset_mutex); if (!is_cpuset_online(cs)) goto out_unlock; @@ -1679,6 +1682,7 @@ } out_unlock: mutex_unlock(&cpuset_mutex); + put_online_cpus(); return retval; } @@ -1717,6 +1721,7 @@ kernfs_break_active_protection(of->kn); flush_work(&cpuset_hotplug_work); + get_online_cpus(); mutex_lock(&cpuset_mutex); if (!is_cpuset_online(cs)) goto out_unlock; @@ -1742,6 +1747,7 @@ free_trial_cpuset(trialcs); out_unlock: mutex_unlock(&cpuset_mutex); + put_online_cpus(); kernfs_unbreak_active_protection(of->kn); css_put(&cs->css); flush_workqueue(cpuset_migrate_mm_wq); @@ -1766,7 +1772,7 @@ switch (type) { case FILE_CPULIST: - seq_printf(sf, "%*pbl\n", cpumask_pr_args(cs->cpus_allowed)); + seq_printf(sf, "%*pbl\n", cpumask_pr_args(cs->cpus_requested)); break; case FILE_MEMLIST: seq_printf(sf, "%*pbl\n", nodemask_pr_args(&cs->mems_allowed)); @@ -1955,12 +1961,15 @@ if (!cs) return ERR_PTR(-ENOMEM); if (!alloc_cpumask_var(&cs->cpus_allowed, GFP_KERNEL)) - goto free_cs; + goto error_allowed; if (!alloc_cpumask_var(&cs->effective_cpus, GFP_KERNEL)) - goto free_cpus; + goto error_effective; + if (!alloc_cpumask_var(&cs->cpus_requested, GFP_KERNEL)) + goto error_requested; set_bit(CS_SCHED_LOAD_BALANCE, &cs->flags); cpumask_clear(cs->cpus_allowed); + cpumask_clear(cs->cpus_requested); nodes_clear(cs->mems_allowed); cpumask_clear(cs->effective_cpus); nodes_clear(cs->effective_mems); @@ -1969,9 +1978,11 @@ return &cs->css; -free_cpus: +error_requested: + free_cpumask_var(cs->effective_cpus); +error_effective: free_cpumask_var(cs->cpus_allowed); -free_cs: +error_allowed: kfree(cs); return ERR_PTR(-ENOMEM); } @@ -2032,6 +2043,7 @@ cs->mems_allowed = parent->mems_allowed; cs->effective_mems = parent->mems_allowed; cpumask_copy(cs->cpus_allowed, parent->cpus_allowed); + cpumask_copy(cs->cpus_requested, parent->cpus_requested); cpumask_copy(cs->effective_cpus, parent->cpus_allowed); spin_unlock_irq(&callback_lock); out_unlock: @@ -2042,13 +2054,14 @@ /* * If the cpuset being removed has its flag 'sched_load_balance' * enabled, then simulate turning sched_load_balance off, which - * will call rebuild_sched_domains_locked(). + * will call rebuild_sched_domains_unlocked(). */ static void cpuset_css_offline(struct cgroup_subsys_state *css) { struct cpuset *cs = css_cs(css); + get_online_cpus(); mutex_lock(&cpuset_mutex); if (is_sched_load_balance(cs)) @@ -2058,6 +2071,7 @@ clear_bit(CS_ONLINE, &cs->flags); mutex_unlock(&cpuset_mutex); + put_online_cpus(); } static void cpuset_css_free(struct cgroup_subsys_state *css) @@ -2066,6 +2080,7 @@ free_cpumask_var(cs->effective_cpus); free_cpumask_var(cs->cpus_allowed); + free_cpumask_var(cs->cpus_requested); kfree(cs); } @@ -2130,8 +2145,11 @@ BUG(); if (!alloc_cpumask_var(&top_cpuset.effective_cpus, GFP_KERNEL)) BUG(); + if (!alloc_cpumask_var(&top_cpuset.cpus_requested, GFP_KERNEL)) + BUG(); cpumask_setall(top_cpuset.cpus_allowed); + cpumask_setall(top_cpuset.cpus_requested); nodes_setall(top_cpuset.mems_allowed); cpumask_setall(top_cpuset.effective_cpus); nodes_setall(top_cpuset.effective_mems); @@ -2265,7 +2283,8 @@ goto retry; } - cpumask_and(&new_cpus, cs->cpus_allowed, parent_cs(cs)->effective_cpus); + cpumask_and(&new_cpus, cs->cpus_requested, + parent_cs(cs)->effective_cpus); nodes_and(new_mems, cs->mems_allowed, parent_cs(cs)->effective_mems); cpus_updated = !cpumask_equal(&new_cpus, cs->effective_cpus); diff -ruw linux-4.4.115/kernel/events/core.c linux-4.4.115-fbx/kernel/events/core.c --- linux-4.4.115/kernel/events/core.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/kernel/events/core.c 2019-10-29 09:26:25.585222183 +0100 @@ -158,6 +158,7 @@ struct static_key_deferred perf_sched_events __read_mostly; static DEFINE_PER_CPU(atomic_t, perf_cgroup_events); static DEFINE_PER_CPU(int, perf_sched_cb_usages); +static DEFINE_PER_CPU(bool, is_idle); static atomic_t nr_mmap_events __read_mostly; static atomic_t nr_comm_events __read_mostly; @@ -175,8 +176,15 @@ * 0 - disallow raw tracepoint access for unpriv * 1 - disallow cpu events for unpriv * 2 - disallow kernel profiling for unpriv + * 3 - disallow all unpriv perf event use */ +#ifdef CONFIG_PERF_EVENTS_USERMODE +int sysctl_perf_event_paranoid __read_mostly = -1; +#elif defined CONFIG_SECURITY_PERF_EVENTS_RESTRICT +int sysctl_perf_event_paranoid __read_mostly = 3; +#else int sysctl_perf_event_paranoid __read_mostly = 1; +#endif /* Minimum for 512 kiB + 1 user control page */ int sysctl_perf_event_mlock __read_mostly = 512 + (PAGE_SIZE / 1024); /* 'free' kiB per user */ @@ -1481,10 +1489,17 @@ * If this was a group event with sibling events then * upgrade the siblings to singleton events by adding them * to whatever list we are on. + * If this isn't on a list, make sure we still remove the sibling's + * group_entry from this sibling_list; otherwise, when that sibling + * is later deallocated, it will try to remove itself from this + * sibling_list, which may well have been deallocated already, + * resulting in a use-after-free. */ list_for_each_entry_safe(sibling, tmp, &event->sibling_list, group_entry) { if (list) list_move_tail(&sibling->group_entry, list); + else + list_del_init(&sibling->group_entry); sibling->group_leader = sibling; /* Inherit group flags from the previous leader */ @@ -1679,6 +1694,31 @@ } +#ifdef CONFIG_SMP +static void perf_retry_remove(struct perf_event *event, + struct remove_event *rep) +{ + int up_ret; + /* + * CPU was offline. Bring it online so we can + * gracefully exit a perf context. + */ + up_ret = cpu_up(event->cpu); + if (!up_ret) + /* Try the remove call once again. */ + cpu_function_call(event->cpu, __perf_remove_from_context, + rep); + else + pr_err("Failed to bring up CPU: %d, ret: %d\n", + event->cpu, up_ret); +} +#else +static void perf_retry_remove(struct perf_event *event, + struct remove_event *rep) +{ +} +#endif + /* * Remove the event from a task's (or a CPU's) list of events. * @@ -1692,7 +1732,8 @@ * When called from perf_event_exit_task, it's OK because the * context has been detached from its task. */ -static void perf_remove_from_context(struct perf_event *event, bool detach_group) +static void __ref perf_remove_from_context(struct perf_event *event, + bool detach_group) { struct perf_event_context *ctx = event->ctx; struct task_struct *task = ctx->task; @@ -1700,6 +1741,7 @@ .event = event, .detach_group = detach_group, }; + int ret; lockdep_assert_held(&ctx->mutex); @@ -1710,7 +1752,11 @@ * already called __perf_remove_from_context from * perf_event_exit_cpu. */ - cpu_function_call(event->cpu, __perf_remove_from_context, &re); + ret = cpu_function_call(event->cpu, __perf_remove_from_context, + &re); + if (ret == -ENXIO) + perf_retry_remove(event, &re); + return; } @@ -1906,8 +1952,13 @@ if (event->state <= PERF_EVENT_STATE_OFF) return 0; - event->state = PERF_EVENT_STATE_ACTIVE; - event->oncpu = smp_processor_id(); + WRITE_ONCE(event->oncpu, smp_processor_id()); + /* + * Order event::oncpu write to happen before the ACTIVE state + * is visible. + */ + smp_wmb(); + WRITE_ONCE(event->state, PERF_EVENT_STATE_ACTIVE); /* * Unthrottle events, since we scheduled we might have missed several @@ -2388,6 +2439,29 @@ } EXPORT_SYMBOL_GPL(perf_event_enable); +static int __perf_event_stop(void *info) +{ + struct perf_event *event = info; + + /* for AUX events, our job is done if the event is already inactive */ + if (READ_ONCE(event->state) != PERF_EVENT_STATE_ACTIVE) + return 0; + + /* matches smp_wmb() in event_sched_in() */ + smp_rmb(); + + /* + * There is a window with interrupts enabled before we get here, + * so we need to check again lest we try to stop another CPU's event. + */ + if (READ_ONCE(event->oncpu) != smp_processor_id()) + return -EAGAIN; + + event->pmu->stop(event, PERF_EF_UPDATE); + + return 0; +} + static int _perf_event_refresh(struct perf_event *event, int refresh) { /* @@ -3363,21 +3437,30 @@ static int perf_event_read(struct perf_event *event, bool group) { - int ret = 0; + int event_cpu, ret = 0; /* * If event is enabled and currently active on a CPU, update the * value in the event structure: */ - if (event->state == PERF_EVENT_STATE_ACTIVE) { + event_cpu = READ_ONCE(event->oncpu); + + if (event->state == PERF_EVENT_STATE_ACTIVE && + !cpu_isolated(event_cpu)) { struct perf_read_data data = { .event = event, .group = group, .ret = 0, }; - smp_call_function_single(event->oncpu, + + if ((unsigned int)event_cpu >= nr_cpu_ids) + return 0; + if (!event->attr.exclude_idle || + !per_cpu(is_idle, event_cpu)) { + smp_call_function_single(event_cpu, __perf_event_read, &data, 1); ret = data.ret; + } } else if (event->state == PERF_EVENT_STATE_INACTIVE) { struct perf_event_context *ctx = event->ctx; unsigned long flags; @@ -3472,7 +3555,8 @@ if (!task) { /* Must be root to operate on a CPU event: */ - if (perf_paranoid_cpu() && !capable(CAP_SYS_ADMIN)) + if (event->owner != EVENT_OWNER_KERNEL && perf_paranoid_cpu() && + !capable(CAP_SYS_ADMIN)) return ERR_PTR(-EACCES); /* @@ -3713,6 +3797,9 @@ if (event->destroy) event->destroy(event); + if (event->pmu->free_drv_configs) + event->pmu->free_drv_configs(event); + if (event->ctx) put_ctx(event->ctx); @@ -3856,6 +3943,15 @@ */ static int perf_release(struct inode *inode, struct file *file) { + struct perf_event *event = file->private_data; + + /* + * Event can be in state OFF because of a constraint check. + * Change to ACTIVE so that it gets cleaned up correctly. + */ + if ((event->state == PERF_EVENT_STATE_OFF) && + event->attr.constraint_duplicate) + event->state = PERF_EVENT_STATE_ACTIVE; put_event(file->private_data); return 0; } @@ -4265,6 +4361,8 @@ struct perf_event *output_event); static int perf_event_set_filter(struct perf_event *event, void __user *arg); static int perf_event_set_bpf_prog(struct perf_event *event, u32 prog_fd); +static int perf_event_drv_configs(struct perf_event *event, + void __user *arg); static long _perf_ioctl(struct perf_event *event, unsigned int cmd, unsigned long arg) { @@ -4321,6 +4419,9 @@ case PERF_EVENT_IOC_SET_BPF: return perf_event_set_bpf_prog(event, arg); + case PERF_EVENT_IOC_SET_DRV_CONFIGS: + return perf_event_drv_configs(event, (void __user *)arg); + default: return -ENOTTY; } @@ -4353,6 +4454,7 @@ switch (_IOC_NR(cmd)) { case _IOC_NR(PERF_EVENT_IOC_SET_FILTER): case _IOC_NR(PERF_EVENT_IOC_ID): + case _IOC_NR(PERF_EVENT_IOC_SET_DRV_CONFIGS): /* Fix up pointer size (usually 4 -> 8 in 32-on-64-bit case */ if (_IOC_SIZE(cmd) == sizeof(compat_uptr_t)) { cmd &= ~IOCSIZE_MASK; @@ -4637,6 +4739,8 @@ event->pmu->event_mapped(event); } +static void perf_pmu_output_stop(struct perf_event *event); + /* * A buffer can be mmap()ed multiple times; either directly through the same * event, or through other events by use of perf_event_set_output(). @@ -4664,10 +4768,22 @@ */ if (rb_has_aux(rb) && vma->vm_pgoff == rb->aux_pgoff && atomic_dec_and_mutex_lock(&rb->aux_mmap_count, &event->mmap_mutex)) { + /* + * Stop all AUX events that are writing to this buffer, + * so that we can free its AUX pages and corresponding PMU + * data. Note that after rb::aux_mmap_count dropped to zero, + * they won't start any more (see perf_aux_output_begin()). + */ + perf_pmu_output_stop(event); + + /* now it's safe to free the pages */ atomic_long_sub(rb->aux_nr_pages, &mmap_user->locked_vm); vma->vm_mm->pinned_vm -= rb->aux_mmap_locked; + /* this has to be the last one */ rb_free_aux(rb); + WARN_ON_ONCE(atomic_read(&rb->aux_refcount)); + mutex_unlock(&event->mmap_mutex); } @@ -5738,6 +5854,80 @@ rcu_read_unlock(); } +struct remote_output { + struct ring_buffer *rb; + int err; +}; + +static void __perf_event_output_stop(struct perf_event *event, void *data) +{ + struct perf_event *parent = event->parent; + struct remote_output *ro = data; + struct ring_buffer *rb = ro->rb; + + if (!has_aux(event)) + return; + + if (!parent) + parent = event; + + /* + * In case of inheritance, it will be the parent that links to the + * ring-buffer, but it will be the child that's actually using it: + */ + if (rcu_dereference(parent->rb) == rb) + ro->err = __perf_event_stop(event); +} + +static int __perf_pmu_output_stop(void *info) +{ + struct perf_event *event = info; + struct pmu *pmu = event->pmu; + struct perf_cpu_context *cpuctx = get_cpu_ptr(pmu->pmu_cpu_context); + struct remote_output ro = { + .rb = event->rb, + }; + + rcu_read_lock(); + perf_event_aux_ctx(&cpuctx->ctx, __perf_event_output_stop, &ro); + if (cpuctx->task_ctx) + perf_event_aux_ctx(cpuctx->task_ctx, __perf_event_output_stop, + &ro); + rcu_read_unlock(); + + return ro.err; +} + +static void perf_pmu_output_stop(struct perf_event *event) +{ + struct perf_event *iter; + int err, cpu; + +restart: + rcu_read_lock(); + list_for_each_entry_rcu(iter, &event->rb->event_list, rb_entry) { + /* + * For per-CPU events, we need to make sure that neither they + * nor their children are running; for cpu==-1 events it's + * sufficient to stop the event itself if it's active, since + * it can't have children. + */ + cpu = iter->cpu; + if (cpu == -1) + cpu = READ_ONCE(iter->oncpu); + + if (cpu == -1) + continue; + + err = cpu_function_call(cpu, __perf_pmu_output_stop, event); + if (err == -EAGAIN) { + rcu_read_unlock(); + goto restart; + } + } + rcu_read_unlock(); +} + /* * task tracking -- fork/exit * @@ -6932,6 +7122,8 @@ .start = perf_swevent_start, .stop = perf_swevent_stop, .read = perf_swevent_read, + + .events_across_hotplug = 1, }; #ifdef CONFIG_EVENT_TRACING @@ -7053,6 +7245,8 @@ .start = perf_swevent_start, .stop = perf_swevent_stop, .read = perf_swevent_read, + + .events_across_hotplug = 1, }; static inline void perf_tp_register(void) @@ -7165,6 +7359,15 @@ } #endif +static int perf_event_drv_configs(struct perf_event *event, + void __user *arg) +{ + if (!event->pmu->get_drv_configs) + return -EINVAL; + + return event->pmu->get_drv_configs(event, arg); +} + /* * hrtimer based swevent callback */ @@ -7332,6 +7535,8 @@ .start = cpu_clock_event_start, .stop = cpu_clock_event_stop, .read = cpu_clock_event_read, + + .events_across_hotplug = 1, }; /* @@ -7413,6 +7618,8 @@ .start = task_clock_event_start, .stop = task_clock_event_stop, .read = task_clock_event_read, + + .events_across_hotplug = 1, }; static void perf_pmu_nop_void(struct pmu *pmu) @@ -7893,6 +8100,7 @@ if (!group_leader) group_leader = event; + mutex_init(&event->group_leader_mutex); mutex_init(&event->child_mutex); INIT_LIST_HEAD(&event->child_list); @@ -7901,6 +8109,7 @@ INIT_LIST_HEAD(&event->sibling_list); INIT_LIST_HEAD(&event->rb_entry); INIT_LIST_HEAD(&event->active_entry); + INIT_LIST_HEAD(&event->drv_configs); INIT_HLIST_NODE(&event->hlist_entry); @@ -8312,10 +8521,16 @@ if (flags & ~PERF_FLAG_ALL) return -EINVAL; + if (perf_paranoid_any() && !capable(CAP_SYS_ADMIN)) + return -EACCES; + err = perf_copy_attr(attr_uptr, &attr); if (err) return err; + if (attr.constraint_duplicate || attr.__reserved_1) + return -EINVAL; + if (!attr.exclude_kernel) { if (perf_paranoid_kernel() && !capable(CAP_SYS_ADMIN)) return -EACCES; @@ -8356,6 +8571,16 @@ group_leader = NULL; } + /* + * Take the group_leader's group_leader_mutex before observing + * anything in the group leader that leads to changes in ctx, + * many of which may be changing on another thread. + * In particular, we want to take this lock before deciding + * whether we need to move_group. + */ + if (group_leader) + mutex_lock(&group_leader->group_leader_mutex); + if (pid != -1 && !(flags & PERF_FLAG_PID_CGROUP)) { task = find_lively_task_by_vpid(pid); if (IS_ERR(task)) { @@ -8513,6 +8738,7 @@ f_flags); if (IS_ERR(event_file)) { err = PTR_ERR(event_file); + event_file = NULL; goto err_context; } @@ -8633,6 +8859,8 @@ if (move_group) perf_event_ctx_unlock(group_leader, gctx); mutex_unlock(&ctx->mutex); + if (group_leader) + mutex_unlock(&group_leader->group_leader_mutex); if (task) { mutex_unlock(&task->signal->cred_guard_mutex); @@ -8682,6 +8910,8 @@ if (task) put_task_struct(task); err_group_fd: + if (group_leader) + mutex_unlock(&group_leader->group_leader_mutex); fdput(group); err_fd: put_unused_fd(event_fd); @@ -9393,6 +9623,18 @@ rcu_read_unlock(); } +static void __perf_event_stop_swclock(void *__info) +{ + struct perf_event_context *ctx = __info; + struct perf_event *event, *tmp; + + list_for_each_entry_safe(event, tmp, &ctx->event_list, event_entry) { + if (event->attr.config == PERF_COUNT_SW_CPU_CLOCK && + event->attr.type == PERF_TYPE_SOFTWARE) + cpu_clock_event_stop(event, 0); + } +} + static void perf_event_exit_cpu_context(int cpu) { struct perf_event_context *ctx; @@ -9402,20 +9644,56 @@ idx = srcu_read_lock(&pmus_srcu); list_for_each_entry_rcu(pmu, &pmus, entry) { ctx = &per_cpu_ptr(pmu->pmu_cpu_context, cpu)->ctx; - mutex_lock(&ctx->mutex); - smp_call_function_single(cpu, __perf_event_exit_context, ctx, 1); + /* + * If keeping events across hotplugging is supported, do not + * remove the event list, but keep it alive across CPU hotplug. + * The context is exited via an fd close path when userspace + * is done and the target CPU is online. If software clock + * event is active, then stop hrtimer associated with it. + * Start the timer when the CPU comes back online. + */ + if (!pmu->events_across_hotplug) + smp_call_function_single(cpu, __perf_event_exit_context, + ctx, 1); + else + smp_call_function_single(cpu, __perf_event_stop_swclock, + ctx, 1); mutex_unlock(&ctx->mutex); } srcu_read_unlock(&pmus_srcu, idx); } +static void perf_event_start_swclock(int cpu) +{ + struct perf_event_context *ctx; + struct pmu *pmu; + int idx; + struct perf_event *event, *tmp; + + idx = srcu_read_lock(&pmus_srcu); + list_for_each_entry_rcu(pmu, &pmus, entry) { + if (pmu->events_across_hotplug) { + ctx = &per_cpu_ptr(pmu->pmu_cpu_context, cpu)->ctx; + list_for_each_entry_safe(event, tmp, &ctx->event_list, + event_entry) { + if (event->attr.config == + PERF_COUNT_SW_CPU_CLOCK && + event->attr.type == PERF_TYPE_SOFTWARE) + cpu_clock_event_start(event, 0); + } + } + } + srcu_read_unlock(&pmus_srcu, idx); +} + static void perf_event_exit_cpu(int cpu) { perf_event_exit_cpu_context(cpu); } #else static inline void perf_event_exit_cpu(int cpu) { } +static inline void perf_event_start_swclock(int cpu) { } #endif static int @@ -9454,6 +9732,11 @@ case CPU_DOWN_PREPARE: perf_event_exit_cpu(cpu); break; + + case CPU_STARTING: + perf_event_start_swclock(cpu); + break; + default: break; } @@ -9461,6 +9744,25 @@ return NOTIFY_OK; } +static int event_idle_notif(struct notifier_block *nb, unsigned long action, + void *data) +{ + switch (action) { + case IDLE_START: + __this_cpu_write(is_idle, true); + break; + case IDLE_END: + __this_cpu_write(is_idle, false); + break; + } + + return NOTIFY_OK; +} + +static struct notifier_block perf_event_idle_nb = { + .notifier_call = event_idle_notif, +}; + void __init perf_event_init(void) { int ret; @@ -9474,6 +9776,7 @@ perf_pmu_register(&perf_task_clock, NULL, -1); perf_tp_register(); perf_cpu_notifier(perf_cpu_notify); + idle_notifier_register(&perf_event_idle_nb); register_reboot_notifier(&perf_reboot_notifier); ret = init_hw_breakpoint(); diff -ruw linux-4.4.115/kernel/events/internal.h linux-4.4.115-fbx/kernel/events/internal.h --- linux-4.4.115/kernel/events/internal.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/kernel/events/internal.h 2019-01-22 16:16:28.651293025 +0100 @@ -11,7 +11,6 @@ struct ring_buffer { atomic_t refcount; struct rcu_head rcu_head; - struct irq_work irq_work; #ifdef CONFIG_PERF_USE_VMALLOC struct work_struct work; int page_order; /* allocation order */ diff -ruw linux-4.4.115/kernel/events/ring_buffer.c linux-4.4.115-fbx/kernel/events/ring_buffer.c --- linux-4.4.115/kernel/events/ring_buffer.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/kernel/events/ring_buffer.c 2019-10-29 09:26:25.585222183 +0100 @@ -221,8 +221,6 @@ rcu_read_unlock(); } -static void rb_irq_work(struct irq_work *work); - static void ring_buffer_init(struct ring_buffer *rb, long watermark, int flags) { @@ -243,16 +241,6 @@ INIT_LIST_HEAD(&rb->event_list); spin_lock_init(&rb->event_lock); - init_irq_work(&rb->irq_work, rb_irq_work); -} - -static void ring_buffer_put_async(struct ring_buffer *rb) -{ - if (!atomic_dec_and_test(&rb->refcount)) - return; - - rb->rcu_head.next = (void *)rb; - irq_work_queue(&rb->irq_work); } /* @@ -264,6 +252,10 @@ * The ordering is similar to that of perf_output_{begin,end}, with * the exception of (B), which should be taken care of by the pmu * driver, since ordering rules will differ depending on hardware. + * + * Call this from pmu::start(); see the comment in perf_aux_output_end() + * about its use in pmu callbacks. Both can also be called from the PMI + * handler if needed. */ void *perf_aux_output_begin(struct perf_output_handle *handle, struct perf_event *event) @@ -288,6 +280,13 @@ goto err; /* + * If rb::aux_mmap_count is zero (and rb_has_aux() above went through), + * the aux buffer is in perf_mmap_close(), about to get freed. + */ + if (!atomic_read(&rb->aux_mmap_count)) + goto err_put; + + /* * Nesting is not supported for AUX area, make sure nested * writers are caught early */ @@ -328,10 +327,11 @@ return handle->rb->aux_priv; err_put: + /* can't be last */ rb_free_aux(rb); err: - ring_buffer_put_async(rb); + ring_buffer_put(rb); handle->event = NULL; return NULL; @@ -342,6 +342,10 @@ * aux_head and posting a PERF_RECORD_AUX into the perf buffer. It is the * pmu driver's responsibility to observe ordering rules of the hardware, * so that all the data is externally visible before this is called. + * + * Note: this has to be called from pmu::stop() callback, as the assumption + * of the AUX buffer management code is that after pmu::stop(), the AUX + * transaction must be stopped and therefore drop the AUX reference count. */ void perf_aux_output_end(struct perf_output_handle *handle, unsigned long size, bool truncated) @@ -389,8 +393,9 @@ handle->event = NULL; local_set(&rb->aux_nest, 0); + /* can't be last */ rb_free_aux(rb); - ring_buffer_put_async(rb); + ring_buffer_put(rb); } /* @@ -467,6 +472,33 @@ __free_page(page); } +static void __rb_free_aux(struct ring_buffer *rb) +{ + int pg; + + /* + * Should never happen, the last reference should be dropped from + * perf_mmap_close() path, which first stops aux transactions (which + * in turn are the atomic holders of aux_refcount) and then does the + * last rb_free_aux(). + */ + WARN_ON_ONCE(in_atomic()); + + if (rb->aux_priv) { + rb->free_aux(rb->aux_priv); + rb->free_aux = NULL; + rb->aux_priv = NULL; + } + + if (rb->aux_nr_pages) { + for (pg = 0; pg < rb->aux_nr_pages; pg++) + rb_free_aux_page(rb, pg); + + kfree(rb->aux_pages); + rb->aux_nr_pages = 0; + } +} + int rb_alloc_aux(struct ring_buffer *rb, struct perf_event *event, pgoff_t pgoff, int nr_pages, long watermark, int flags) { @@ -530,7 +562,7 @@ goto out; } - rb->aux_priv = event->pmu->setup_aux(event->cpu, rb->aux_pages, nr_pages, + rb->aux_priv = event->pmu->setup_aux(event, rb->aux_pages, nr_pages, overwrite); if (!rb->aux_priv) goto out; @@ -555,45 +587,15 @@ if (!ret) rb->aux_pgoff = pgoff; else - rb_free_aux(rb); + __rb_free_aux(rb); return ret; } -static void __rb_free_aux(struct ring_buffer *rb) -{ - int pg; - - if (rb->aux_priv) { - rb->free_aux(rb->aux_priv); - rb->free_aux = NULL; - rb->aux_priv = NULL; - } - - if (rb->aux_nr_pages) { - for (pg = 0; pg < rb->aux_nr_pages; pg++) - rb_free_aux_page(rb, pg); - - kfree(rb->aux_pages); - rb->aux_nr_pages = 0; - } -} - void rb_free_aux(struct ring_buffer *rb) { if (atomic_dec_and_test(&rb->aux_refcount)) - irq_work_queue(&rb->irq_work); -} - -static void rb_irq_work(struct irq_work *work) -{ - struct ring_buffer *rb = container_of(work, struct ring_buffer, irq_work); - - if (!atomic_read(&rb->aux_refcount)) __rb_free_aux(rb); - - if (rb->rcu_head.next == (void *)rb) - call_rcu(&rb->rcu_head, rb_free_rcu); } #ifndef CONFIG_PERF_USE_VMALLOC diff -ruw linux-4.4.115/kernel/exit.c linux-4.4.115-fbx/kernel/exit.c --- linux-4.4.115/kernel/exit.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/kernel/exit.c 2019-10-29 09:26:25.589222222 +0100 @@ -53,6 +53,9 @@ #include #include #include +#include + +#include "sched/tune.h" #include #include @@ -388,6 +391,7 @@ { struct mm_struct *mm = tsk->mm; struct core_state *core_state; + int mm_released; mm_release(tsk, mm); if (!mm) @@ -434,9 +438,12 @@ enter_lazy_tlb(mm, current); task_unlock(tsk); mm_update_next_owner(mm); - mmput(mm); + + mm_released = mmput(mm); if (test_thread_flag(TIF_MEMDIE)) exit_oom_victim(); + if (mm_released) + set_tsk_thread_flag(tsk, TIF_MM_RELEASED); } static struct task_struct *find_alive_thread(struct task_struct *p) @@ -632,6 +639,7 @@ static DEFINE_SPINLOCK(low_water_lock); static int lowest_to_date = THREAD_SIZE; unsigned long free; + int islower = false; free = stack_not_used(current); @@ -640,11 +648,16 @@ spin_lock(&low_water_lock); if (free < lowest_to_date) { - pr_warn("%s (%d) used greatest stack depth: %lu bytes left\n", - current->comm, task_pid_nr(current), free); lowest_to_date = free; + islower = true; } spin_unlock(&low_water_lock); + + if (islower) { + printk(KERN_WARNING "%s (%d) used greatest stack depth: " + "%lu bytes left\n", + current->comm, task_pid_nr(current), free); + } } #else static inline void check_stack_usage(void) {} @@ -657,6 +670,7 @@ TASKS_RCU(int tasks_rcu_i); profile_task_exit(tsk); + kcov_task_exit(tsk); WARN_ON(blk_needs_flush_plug(tsk)); @@ -699,6 +713,10 @@ } exit_signals(tsk); /* sets PF_EXITING */ + + sched_exit(tsk); + schedtune_exit_task(tsk); + /* * tsk->flags are checked in the futex code to protect against * an exiting task cleaning up the robust pi futexes. diff -ruw linux-4.4.115/kernel/fork.c linux-4.4.115-fbx/kernel/fork.c --- linux-4.4.115/kernel/fork.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/kernel/fork.c 2019-10-29 09:26:25.589222222 +0100 @@ -23,6 +23,7 @@ #include #include #include +#include #include #include #include @@ -76,6 +77,7 @@ #include #include #include +#include #include #include @@ -148,18 +150,18 @@ } #endif -void __weak arch_release_thread_info(struct thread_info *ti) +void __weak arch_release_thread_stack(unsigned long *stack) { } -#ifndef CONFIG_ARCH_THREAD_INFO_ALLOCATOR +#ifndef CONFIG_ARCH_THREAD_STACK_ALLOCATOR /* * Allocate pages if THREAD_SIZE is >= PAGE_SIZE, otherwise use a * kmemcache based allocator. */ # if THREAD_SIZE >= PAGE_SIZE -static struct thread_info *alloc_thread_info_node(struct task_struct *tsk, +static unsigned long *alloc_thread_stack_node(struct task_struct *tsk, int node) { struct page *page = alloc_kmem_pages_node(node, THREADINFO_GFP, @@ -168,30 +170,33 @@ return page ? page_address(page) : NULL; } -static inline void free_thread_info(struct thread_info *ti) +static inline void free_thread_stack(unsigned long *stack) { - kaiser_unmap_thread_stack(ti); - free_kmem_pages((unsigned long)ti, THREAD_SIZE_ORDER); + struct page *page = virt_to_page(stack); + + kasan_alloc_pages(page, THREAD_SIZE_ORDER); + kaiser_unmap_thread_stack(stack); + __free_kmem_pages(page, THREAD_SIZE_ORDER); } # else -static struct kmem_cache *thread_info_cache; +static struct kmem_cache *thread_stack_cache; -static struct thread_info *alloc_thread_info_node(struct task_struct *tsk, +static unsigned long *alloc_thread_stack_node(struct task_struct *tsk, int node) { - return kmem_cache_alloc_node(thread_info_cache, THREADINFO_GFP, node); + return kmem_cache_alloc_node(thread_stack_cache, THREADINFO_GFP, node); } -static void free_thread_info(struct thread_info *ti) +static void free_thread_stack(unsigned long *stack) { - kmem_cache_free(thread_info_cache, ti); + kmem_cache_free(thread_stack_cache, stack); } -void thread_info_cache_init(void) +void thread_stack_cache_init(void) { - thread_info_cache = kmem_cache_create("thread_info", THREAD_SIZE, + thread_stack_cache = kmem_cache_create("thread_stack", THREAD_SIZE, THREAD_SIZE, 0, NULL); - BUG_ON(thread_info_cache == NULL); + BUG_ON(thread_stack_cache == NULL); } # endif #endif @@ -214,9 +219,9 @@ /* SLAB cache for mm_struct structures (tsk->mm) */ static struct kmem_cache *mm_cachep; -static void account_kernel_stack(struct thread_info *ti, int account) +static void account_kernel_stack(unsigned long *stack, int account) { - struct zone *zone = page_zone(virt_to_page(ti)); + struct zone *zone = page_zone(virt_to_page(stack)); mod_zone_page_state(zone, NR_KERNEL_STACK, account); } @@ -224,8 +229,8 @@ void free_task(struct task_struct *tsk) { account_kernel_stack(tsk->stack, -1); - arch_release_thread_info(tsk->stack); - free_thread_info(tsk->stack); + arch_release_thread_stack(tsk->stack); + free_thread_stack(tsk->stack); rt_mutex_debug_task_free(tsk); ftrace_graph_exit_task(tsk); put_seccomp_filter(tsk); @@ -336,7 +341,7 @@ static struct task_struct *dup_task_struct(struct task_struct *orig, int node) { struct task_struct *tsk; - struct thread_info *ti; + unsigned long *stack; int err; if (node == NUMA_NO_NODE) @@ -345,19 +350,19 @@ if (!tsk) return NULL; - ti = alloc_thread_info_node(tsk, node); - if (!ti) + stack = alloc_thread_stack_node(tsk, node); + if (!stack) goto free_tsk; err = arch_dup_task_struct(tsk, orig); if (err) - goto free_ti; + goto free_stack; - tsk->stack = ti; + tsk->stack = stack; err = kaiser_map_thread_stack(tsk->stack); if (err) - goto free_ti; + goto free_stack; #ifdef CONFIG_SECCOMP /* * We must handle setting up seccomp filters once we're under @@ -389,12 +394,19 @@ tsk->task_frag.page = NULL; tsk->wake_q.next = NULL; - account_kernel_stack(ti, 1); + /* + * inherit parent exec_mode. + */ + tsk->exec_mode = orig->exec_mode; + + account_kernel_stack(stack, 1); + + kcov_task_init(tsk); return tsk; -free_ti: - free_thread_info(ti); +free_stack: + free_thread_stack(stack); free_tsk: free_task_struct(tsk); return NULL; @@ -699,14 +711,10 @@ } EXPORT_SYMBOL_GPL(__mmdrop); -/* - * Decrement the use count and release all resources for an mm. - */ -void mmput(struct mm_struct *mm) +static inline void __mmput(struct mm_struct *mm) { - might_sleep(); + VM_BUG_ON(atomic_read(&mm->mm_users)); - if (atomic_dec_and_test(&mm->mm_users)) { uprobe_clear_state(mm); exit_aio(mm); ksm_exit(mm); @@ -722,9 +730,37 @@ module_put(mm->binfmt->module); mmdrop(mm); } + +/* + * Decrement the use count and release all resources for an mm. + */ +int mmput(struct mm_struct *mm) +{ + int mm_freed = 0; + might_sleep(); + + if (atomic_dec_and_test(&mm->mm_users)) { + __mmput(mm); + mm_freed = 1; + } + return mm_freed; } EXPORT_SYMBOL_GPL(mmput); +static void mmput_async_fn(struct work_struct *work) +{ + struct mm_struct *mm = container_of(work, struct mm_struct, async_put_work); + __mmput(mm); +} + +void mmput_async(struct mm_struct *mm) +{ + if (atomic_dec_and_test(&mm->mm_users)) { + INIT_WORK(&mm->async_put_work, mmput_async_fn); + schedule_work(&mm->async_put_work); + } +} + /** * set_mm_exe_file - change a reference to the mm's executable file * @@ -1684,6 +1720,7 @@ bad_fork_cleanup_perf: perf_event_free_task(p); bad_fork_cleanup_policy: + free_task_load_ptrs(p); #ifdef CONFIG_NUMA mpol_put(p->mempolicy); bad_fork_cleanup_threadgroup_lock: @@ -1715,7 +1752,7 @@ cpu_to_node(cpu)); if (!IS_ERR(task)) { init_idle_pids(task->pids); - init_idle(task, cpu); + init_idle(task, cpu, false); } return task; diff -ruw linux-4.4.115/kernel/futex.c linux-4.4.115-fbx/kernel/futex.c --- linux-4.4.115/kernel/futex.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/kernel/futex.c 2019-10-29 09:26:25.593222261 +0100 @@ -470,6 +470,7 @@ unsigned long address = (unsigned long)uaddr; struct mm_struct *mm = current->mm; struct page *page, *page_head; + struct address_space *mapping; int err, ro = 0; /* @@ -555,7 +556,19 @@ } #endif - lock_page(page_head); + /* + * The treatment of mapping from this point on is critical. The page + * lock protects many things but in this context the page lock + * stabilizes mapping, prevents inode freeing in the shared + * file-backed region case and guards against movement to swap cache. + * + * Strictly speaking the page lock is not needed in all cases being + * considered here and page lock forces unnecessarily serialization + * From this point on, mapping will be re-verified if necessary and + * page lock will be acquired only if it is unavoidable + */ + + mapping = READ_ONCE(page_head->mapping); /* * If page_head->mapping is NULL, then it cannot be a PageAnon @@ -572,18 +585,31 @@ * shmem_writepage move it from filecache to swapcache beneath us: * an unlikely race, but we do need to retry for page_head->mapping. */ - if (!page_head->mapping) { - int shmem_swizzled = PageSwapCache(page_head); + if (unlikely(!mapping)) { + int shmem_swizzled; + + /* + * Page lock is required to identify which special case above + * applies. If this is really a shmem page then the page lock + * will prevent unexpected transitions. + */ + lock_page(page); + shmem_swizzled = PageSwapCache(page) || page->mapping; unlock_page(page_head); put_page(page_head); + if (shmem_swizzled) goto again; + return -EFAULT; } /* * Private mappings are handled in a simple way. * + * If the futex key is stored on an anonymous page, then the associated + * object is the mm which is implicitly pinned by the calling process. + * * NOTE: When userspace waits on a MAP_SHARED mapping, even if * it's a read-only handle, it's expected that futexes attach to * the object not the particular process. @@ -601,16 +627,74 @@ key->both.offset |= FUT_OFF_MMSHARED; /* ref taken on mm */ key->private.mm = mm; key->private.address = address; + + get_futex_key_refs(key); /* implies smp_mb(); (B) */ + } else { + struct inode *inode; + + /* + * The associated futex object in this case is the inode and + * the page->mapping must be traversed. Ordinarily this should + * be stabilised under page lock but it's not strictly + * necessary in this case as we just want to pin the inode, not + * update the radix tree or anything like that. + * + * The RCU read lock is taken as the inode is finally freed + * under RCU. If the mapping still matches expectations then the + * mapping->host can be safely accessed as being a valid inode. + */ + rcu_read_lock(); + + if (READ_ONCE(page_head->mapping) != mapping) { + rcu_read_unlock(); + put_page(page_head); + + goto again; + } + + inode = READ_ONCE(mapping->host); + if (!inode) { + rcu_read_unlock(); + put_page(page_head); + + goto again; + } + + /* + * Take a reference unless it is about to be freed. Previously + * this reference was taken by ihold under the page lock + * pinning the inode in place so i_lock was unnecessary. The + * only way for this check to fail is if the inode was + * truncated in parallel so warn for now if this happens. + * + * We are not calling into get_futex_key_refs() in file-backed + * cases, therefore a successful atomic_inc return below will + * guarantee that get_futex_key() will still imply smp_mb(); (B). + */ + if (WARN_ON_ONCE(!atomic_inc_not_zero(&inode->i_count))) { + rcu_read_unlock(); + put_page(page_head); + + goto again; + } + + /* Should be impossible but lets be paranoid for now */ + if (WARN_ON_ONCE(inode->i_mapping != mapping)) { + err = -EFAULT; + rcu_read_unlock(); + iput(inode); + + goto out; + } + key->both.offset |= FUT_OFF_INODE; /* inode-based key */ - key->shared.inode = page_head->mapping->host; + key->shared.inode = inode; key->shared.pgoff = basepage_index(page); + rcu_read_unlock(); } - get_futex_key_refs(key); /* implies MB (B) */ - out: - unlock_page(page_head); put_page(page_head); return err; } @@ -681,7 +765,7 @@ int ret; pagefault_disable(); - ret = __copy_from_user_inatomic(dest, from, sizeof(u32)); + ret = __get_user(*dest, from); pagefault_enable(); return ret ? -EFAULT : 0; diff -ruw linux-4.4.115/kernel/irq/chip.c linux-4.4.115-fbx/kernel/irq/chip.c --- linux-4.4.115/kernel/irq/chip.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/kernel/irq/chip.c 2019-10-29 09:26:25.593222261 +0100 @@ -836,7 +836,8 @@ irq_settings_clr_and_set(desc, clr, set); irqd_clear(&desc->irq_data, IRQD_NO_BALANCING | IRQD_PER_CPU | - IRQD_TRIGGER_MASK | IRQD_LEVEL | IRQD_MOVE_PCNTXT); + IRQD_TRIGGER_MASK | IRQD_LEVEL | IRQD_MOVE_PCNTXT | + IRQD_AFFINITY_MANAGED); if (irq_settings_has_no_balance_set(desc)) irqd_set(&desc->irq_data, IRQD_NO_BALANCING); if (irq_settings_is_per_cpu(desc)) @@ -845,6 +846,8 @@ irqd_set(&desc->irq_data, IRQD_MOVE_PCNTXT); if (irq_settings_is_level(desc)) irqd_set(&desc->irq_data, IRQD_LEVEL); + if (irq_settings_has_affinity_managed_set(desc)) + irqd_set(&desc->irq_data, IRQD_AFFINITY_MANAGED); irqd_set(&desc->irq_data, irq_settings_get_trigger_mask(desc)); diff -ruw linux-4.4.115/kernel/irq/cpuhotplug.c linux-4.4.115-fbx/kernel/irq/cpuhotplug.c --- linux-4.4.115/kernel/irq/cpuhotplug.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/kernel/irq/cpuhotplug.c 2019-01-22 16:16:28.659293097 +0100 @@ -11,6 +11,7 @@ #include #include #include +#include #include "internals.h" @@ -20,6 +21,7 @@ const struct cpumask *affinity = d->common->affinity; struct irq_chip *c; bool ret = false; + struct cpumask available_cpus; /* * If this is a per-CPU interrupt, or the affinity does not @@ -29,8 +31,37 @@ !cpumask_test_cpu(smp_processor_id(), affinity)) return false; + cpumask_copy(&available_cpus, affinity); + cpumask_andnot(&available_cpus, &available_cpus, cpu_isolated_mask); + affinity = &available_cpus; + if (cpumask_any_and(affinity, cpu_online_mask) >= nr_cpu_ids) { + /* + * The order of preference for selecting a fallback CPU is + * + * (1) online and un-isolated CPU from default affinity + * (2) online and un-isolated CPU + * (3) online CPU + */ + cpumask_andnot(&available_cpus, cpu_online_mask, + cpu_isolated_mask); + if (cpumask_intersects(&available_cpus, irq_default_affinity)) + cpumask_and(&available_cpus, &available_cpus, + irq_default_affinity); + else if (cpumask_empty(&available_cpus)) affinity = cpu_online_mask; + + /* + * We are overriding the affinity with all online and + * un-isolated cpus. irq_set_affinity_locked() call + * below notify this mask to PM QOS affinity listener. + * That results in applying the CPU_DMA_LATENCY QOS + * to all the CPUs specified in the mask. But the low + * level irqchip driver sets the affinity of an irq + * to only one CPU. So pick only one CPU from the + * prepared mask while overriding the user affinity. + */ + affinity = cpumask_of(cpumask_any(affinity)); ret = true; } @@ -38,7 +69,7 @@ if (!c->irq_set_affinity) { pr_debug("IRQ%u: unable to set affinity\n", d->irq); } else { - int r = irq_do_set_affinity(d, affinity, false); + int r = irq_set_affinity_locked(d, affinity, false); if (r) pr_warn_ratelimited("IRQ%u: set affinity failed(%d).\n", d->irq, r); @@ -69,6 +100,9 @@ bool affinity_broken; desc = irq_to_desc(irq); + if (!desc) + continue; + raw_spin_lock(&desc->lock); affinity_broken = migrate_one_irq(desc); raw_spin_unlock(&desc->lock); diff -ruw linux-4.4.115/kernel/irq/internals.h linux-4.4.115-fbx/kernel/irq/internals.h --- linux-4.4.115/kernel/irq/internals.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/kernel/irq/internals.h 2019-01-22 16:16:28.659293097 +0100 @@ -105,6 +105,8 @@ struct irqaction *action) { } #endif +extern bool irq_can_set_affinity_usr(unsigned int irq); + extern int irq_select_affinity_usr(unsigned int irq, struct cpumask *mask); extern void irq_set_thread_affinity(struct irq_desc *desc); diff -ruw linux-4.4.115/kernel/irq/manage.c linux-4.4.115-fbx/kernel/irq/manage.c --- linux-4.4.115/kernel/irq/manage.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/kernel/irq/manage.c 2019-10-29 09:26:25.593222261 +0100 @@ -115,12 +115,12 @@ #ifdef CONFIG_SMP cpumask_var_t irq_default_affinity; -static int __irq_can_set_affinity(struct irq_desc *desc) +static bool __irq_can_set_affinity(struct irq_desc *desc) { if (!desc || !irqd_can_balance(&desc->irq_data) || !desc->irq_data.chip || !desc->irq_data.chip->irq_set_affinity) - return 0; - return 1; + return false; + return true; } /** @@ -134,6 +134,21 @@ } /** + * irq_can_set_affinity_usr - Check if affinity of a irq can be set from user space + * @irq: Interrupt to check + * + * Like irq_can_set_affinity() above, but additionally checks for the + * AFFINITY_MANAGED flag. + */ +bool irq_can_set_affinity_usr(unsigned int irq) +{ + struct irq_desc *desc = irq_to_desc(irq); + + return __irq_can_set_affinity(desc) && + !irqd_affinity_is_managed(&desc->irq_data); +} + +/** * irq_set_thread_affinity - Notify irq threads to adjust affinity * @desc: irq descriptor which has affitnity changed * @@ -319,6 +334,9 @@ desc->affinity_notify = notify; raw_spin_unlock_irqrestore(&desc->lock, flags); + if (!notify && old_notify) + cancel_work_sync(&old_notify->work); + if (old_notify) kref_put(&old_notify->kref, old_notify->release); diff -ruw linux-4.4.115/kernel/irq/msi.c linux-4.4.115-fbx/kernel/irq/msi.c --- linux-4.4.115/kernel/irq/msi.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/kernel/irq/msi.c 2019-01-22 16:16:28.659293097 +0100 @@ -268,7 +268,7 @@ struct msi_domain_ops *ops = info->ops; msi_alloc_info_t arg; struct msi_desc *desc; - int i, ret, virq; + int i, ret, virq = 0; ret = ops->msi_check(domain, info, dev); if (ret == 0) diff -ruw linux-4.4.115/kernel/irq/proc.c linux-4.4.115-fbx/kernel/irq/proc.c --- linux-4.4.115/kernel/irq/proc.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/kernel/irq/proc.c 2019-01-22 16:16:28.663293133 +0100 @@ -96,7 +96,7 @@ cpumask_var_t new_value; int err; - if (!irq_can_set_affinity(irq) || no_irq_affinity) + if (!irq_can_set_affinity_usr(irq) || no_irq_affinity) return -EIO; if (!alloc_cpumask_var(&new_value, GFP_KERNEL)) @@ -113,6 +113,11 @@ err = -EINVAL; goto free_cpumask; } + + if (cpumask_subset(new_value, cpu_isolated_mask)) { + err = -EINVAL; + goto free_cpumask; + } /* * Do not allow disabling IRQs completely - it's a too easy diff -ruw linux-4.4.115/kernel/irq/settings.h linux-4.4.115-fbx/kernel/irq/settings.h --- linux-4.4.115/kernel/irq/settings.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/kernel/irq/settings.h 2019-01-22 16:16:28.663293133 +0100 @@ -17,6 +17,7 @@ _IRQ_IS_POLLED = IRQ_IS_POLLED, _IRQ_DISABLE_UNLAZY = IRQ_DISABLE_UNLAZY, _IRQF_MODIFY_MASK = IRQF_MODIFY_MASK, + _IRQ_AFFINITY_MANAGED = IRQ_AFFINITY_MANAGED, }; #define IRQ_PER_CPU GOT_YOU_MORON @@ -32,6 +33,7 @@ #define IRQ_DISABLE_UNLAZY GOT_YOU_MORON #undef IRQF_MODIFY_MASK #define IRQF_MODIFY_MASK GOT_YOU_MORON +#define IRQ_AFFINITY_MANAGED GOT_YOU_MORON static inline void irq_settings_clr_and_set(struct irq_desc *desc, u32 clr, u32 set) @@ -65,6 +67,16 @@ return desc->status_use_accessors & _IRQ_NO_BALANCING; } +static inline void irq_settings_set_affinity_managed(struct irq_desc *desc) +{ + desc->status_use_accessors |= _IRQ_AFFINITY_MANAGED; +} + +static inline bool irq_settings_has_affinity_managed_set(struct irq_desc *desc) +{ + return desc->status_use_accessors & _IRQ_AFFINITY_MANAGED; +} + static inline u32 irq_settings_get_trigger_mask(struct irq_desc *desc) { return desc->status_use_accessors & IRQ_TYPE_SENSE_MASK; diff -ruw linux-4.4.115/kernel/kthread.c linux-4.4.115-fbx/kernel/kthread.c --- linux-4.4.115/kernel/kthread.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/kernel/kthread.c 2019-10-29 09:26:25.597222300 +0100 @@ -65,7 +65,7 @@ static struct kthread *to_live_kthread(struct task_struct *k) { struct completion *vfork = ACCESS_ONCE(k->vfork_done); - if (likely(vfork)) + if (likely(vfork) && try_get_task_stack(k)) return __to_kthread(vfork); return NULL; } @@ -427,8 +427,10 @@ { struct kthread *kthread = to_live_kthread(k); - if (kthread) + if (kthread) { __kthread_unpark(k, kthread); + put_task_stack(k); + } } EXPORT_SYMBOL_GPL(kthread_unpark); @@ -457,6 +459,7 @@ wait_for_completion(&kthread->parked); } } + put_task_stack(k); ret = 0; } return ret; @@ -492,6 +495,7 @@ __kthread_unpark(k, kthread); wake_up_process(k); wait_for_completion(&kthread->exited); + put_task_stack(k); } ret = k->exit_code; put_task_struct(k); @@ -604,6 +608,19 @@ } EXPORT_SYMBOL_GPL(kthread_worker_fn); +/* + * Returns true when the work could not be queued at the moment. + * It happens when it is already pending in a worker list + * or when it is being cancelled. + */ +static inline bool queuing_blocked(struct kthread_worker *worker, + struct kthread_work *work) +{ + lockdep_assert_held(&worker->lock); + + return !list_empty(&work->node) || work->canceling; +} + /* insert @work before @pos in @worker */ static void insert_kthread_work(struct kthread_worker *worker, struct kthread_work *work, @@ -633,7 +650,7 @@ unsigned long flags; spin_lock_irqsave(&worker->lock, flags); - if (list_empty(&work->node)) { + if (!queuing_blocked(worker, work)) { insert_kthread_work(worker, work, &worker->work_list); ret = true; } @@ -694,6 +711,87 @@ } EXPORT_SYMBOL_GPL(flush_kthread_work); +/* + * This function removes the work from the worker queue. Also it makes sure + * that it won't get queued later via the delayed work's timer. + * + * The work might still be in use when this function finishes. See the + * current_work proceed by the worker. + * + * Return: %true if @work was pending and successfully canceled, + * %false if @work was not pending + */ +static bool __kthread_cancel_work(struct kthread_work *work, + unsigned long *flags) +{ + /* + * Try to remove the work from a worker list. It might either + * be from worker->work_list or from worker->delayed_work_list. + */ + if (!list_empty(&work->node)) { + list_del_init(&work->node); + return true; + } + + return false; +} + +static bool __kthread_cancel_work_sync(struct kthread_work *work) +{ + struct kthread_worker *worker = work->worker; + unsigned long flags; + int ret = false; + + if (!worker) + goto out; + + spin_lock_irqsave(&worker->lock, flags); + /* Work must not be used with >1 worker, see kthread_queue_work(). */ + WARN_ON_ONCE(work->worker != worker); + + ret = __kthread_cancel_work(work, &flags); + + if (worker->current_work != work) + goto out_fast; + + /* + * The work is in progress and we need to wait with the lock released. + * In the meantime, block any queuing by setting the canceling counter. + */ + work->canceling++; + spin_unlock_irqrestore(&worker->lock, flags); + flush_kthread_work(work); + spin_lock_irqsave(&worker->lock, flags); + work->canceling--; + +out_fast: + spin_unlock_irqrestore(&worker->lock, flags); +out: + return ret; +} + +/** + * kthread_cancel_work_sync - cancel a kthread work and wait for it to finish + * @work: the kthread work to cancel + * + * Cancel @work and wait for its execution to finish. This function + * can be used even if the work re-queues itself. On return from this + * function, @work is guaranteed to be not pending or executing on any CPU. + * + * kthread_cancel_work_sync(&delayed_work->work) must not be used for + * delayed_work's. Use kthread_cancel_delayed_work_sync() instead. + * + * The caller must ensure that the worker on which @work was last + * queued can't be destroyed before this function returns. + * + * Return: %true if @work was pending, %false otherwise. + */ +bool kthread_cancel_work_sync(struct kthread_work *work) +{ + return __kthread_cancel_work_sync(work); +} +EXPORT_SYMBOL_GPL(kthread_cancel_work_sync); + /** * flush_kthread_worker - flush all current works on a kthread_worker * @worker: worker to flush diff -ruw linux-4.4.115/kernel/locking/Makefile linux-4.4.115-fbx/kernel/locking/Makefile --- linux-4.4.115/kernel/locking/Makefile 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/kernel/locking/Makefile 2019-01-22 16:16:28.667293170 +0100 @@ -1,3 +1,6 @@ +# Any varying coverage in these files is non-deterministic +# and is generally not a function of system call inputs. +KCOV_INSTRUMENT := n obj-y += mutex.o semaphore.o rwsem.o percpu-rwsem.o diff -ruw linux-4.4.115/kernel/locking/mutex.c linux-4.4.115-fbx/kernel/locking/mutex.c --- linux-4.4.115/kernel/locking/mutex.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/kernel/locking/mutex.c 2019-01-22 16:16:28.671293206 +0100 @@ -26,6 +26,7 @@ #include #include #include +#include /* * In the DEBUG case we are using the "NULL fastpath" for mutexes, @@ -378,6 +379,17 @@ * values at the cost of a few extra spins. */ cpu_relax_lowlatency(); + + /* + * On arm systems, we must slow down the waiter's repeated + * aquisition of spin_mlock and atomics on the lock count, or + * we risk starving out a thread attempting to release the + * mutex. The mutex slowpath release must take spin lock + * wait_lock. This spin lock can share a monitor with the + * other waiter atomics in the mutex data structure, so must + * take care to rate limit the waiters. + */ + udelay(1); } osq_unlock(&lock->osq); @@ -537,7 +549,7 @@ goto skip_wait; debug_mutex_lock_common(lock, &waiter); - debug_mutex_add_waiter(lock, &waiter, task_thread_info(task)); + debug_mutex_add_waiter(lock, &waiter, task); /* add waiting tasks to the end of the waitqueue (FIFO): */ list_add_tail(&waiter.list, &lock->wait_list); @@ -584,7 +596,7 @@ } __set_task_state(task, TASK_RUNNING); - mutex_remove_waiter(lock, &waiter, current_thread_info()); + mutex_remove_waiter(lock, &waiter, task); /* set it to 0 if there are no waiters left: */ if (likely(list_empty(&lock->wait_list))) atomic_set(&lock->count, 0); @@ -605,7 +617,7 @@ return 0; err: - mutex_remove_waiter(lock, &waiter, task_thread_info(task)); + mutex_remove_waiter(lock, &waiter, task); spin_unlock_mutex(&lock->wait_lock, flags); debug_mutex_free_waiter(&waiter); mutex_release(&lock->dep_map, 1, ip); diff -ruw linux-4.4.115/kernel/locking/mutex.h linux-4.4.115-fbx/kernel/locking/mutex.h --- linux-4.4.115/kernel/locking/mutex.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/kernel/locking/mutex.h 2019-01-22 16:16:28.671293206 +0100 @@ -13,7 +13,7 @@ do { spin_lock(lock); (void)(flags); } while (0) #define spin_unlock_mutex(lock, flags) \ do { spin_unlock(lock); (void)(flags); } while (0) -#define mutex_remove_waiter(lock, waiter, ti) \ +#define mutex_remove_waiter(lock, waiter, task) \ __list_del((waiter)->list.prev, (waiter)->list.next) #ifdef CONFIG_MUTEX_SPIN_ON_OWNER diff -ruw linux-4.4.115/kernel/locking/osq_lock.c linux-4.4.115-fbx/kernel/locking/osq_lock.c --- linux-4.4.115/kernel/locking/osq_lock.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/kernel/locking/osq_lock.c 2019-01-22 16:16:28.671293206 +0100 @@ -1,6 +1,7 @@ #include #include #include +#include /* * An MCS like lock especially tailored for optimistic spinning for sleeping @@ -85,6 +86,7 @@ { struct optimistic_spin_node *node = this_cpu_ptr(&osq_node); struct optimistic_spin_node *prev, *next; + struct task_struct *task = current; int curr = encode_cpu(smp_processor_id()); int old; @@ -104,6 +106,19 @@ prev = decode_cpu(old); node->prev = prev; + + /* + * osq_lock() unqueue + * + * node->prev = prev osq_wait_next() + * WMB MB + * prev->next = node next->prev = prev // unqueue-C + * + * Here 'node->prev' and 'next->prev' are the same variable and we need + * to ensure these stores happen in-order to avoid corrupting the list. + */ + smp_wmb(); + WRITE_ONCE(prev->next, node); /* @@ -118,8 +133,13 @@ while (!READ_ONCE(node->locked)) { /* * If we need to reschedule bail... so we can block. + * If a task spins on owner on a CPU after acquiring + * osq_lock while a RT task spins on another CPU to + * acquire osq_lock, it will starve the owner from + * completing if owner is to be scheduled on the same CPU. + * It will be a live lock. */ - if (need_resched()) + if (need_resched() || rt_task(task)) goto unqueue; cpu_relax_lowlatency(); diff -ruw linux-4.4.115/kernel/locking/percpu-rwsem.c linux-4.4.115-fbx/kernel/locking/percpu-rwsem.c --- linux-4.4.115/kernel/locking/percpu-rwsem.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/kernel/locking/percpu-rwsem.c 2019-01-22 16:16:28.671293206 +0100 @@ -8,151 +8,186 @@ #include #include -int __percpu_init_rwsem(struct percpu_rw_semaphore *brw, +int __percpu_init_rwsem(struct percpu_rw_semaphore *sem, const char *name, struct lock_class_key *rwsem_key) { - brw->fast_read_ctr = alloc_percpu(int); - if (unlikely(!brw->fast_read_ctr)) + sem->read_count = alloc_percpu(int); + if (unlikely(!sem->read_count)) return -ENOMEM; /* ->rw_sem represents the whole percpu_rw_semaphore for lockdep */ - __init_rwsem(&brw->rw_sem, name, rwsem_key); - rcu_sync_init(&brw->rss, RCU_SCHED_SYNC); - atomic_set(&brw->slow_read_ctr, 0); - init_waitqueue_head(&brw->write_waitq); + rcu_sync_init(&sem->rss, RCU_SCHED_SYNC); + __init_rwsem(&sem->rw_sem, name, rwsem_key); + init_waitqueue_head(&sem->writer); + sem->readers_block = 0; return 0; } EXPORT_SYMBOL_GPL(__percpu_init_rwsem); -void percpu_free_rwsem(struct percpu_rw_semaphore *brw) +void percpu_free_rwsem(struct percpu_rw_semaphore *sem) { /* * XXX: temporary kludge. The error path in alloc_super() * assumes that percpu_free_rwsem() is safe after kzalloc(). */ - if (!brw->fast_read_ctr) + if (!sem->read_count) return; - rcu_sync_dtor(&brw->rss); - free_percpu(brw->fast_read_ctr); - brw->fast_read_ctr = NULL; /* catch use after free bugs */ + rcu_sync_dtor(&sem->rss); + free_percpu(sem->read_count); + sem->read_count = NULL; /* catch use after free bugs */ } +EXPORT_SYMBOL_GPL(percpu_free_rwsem); +int __percpu_down_read(struct percpu_rw_semaphore *sem, int try) +{ /* - * This is the fast-path for down_read/up_read. If it succeeds we rely - * on the barriers provided by rcu_sync_enter/exit; see the comments in - * percpu_down_write() and percpu_up_write(). + * Due to having preemption disabled the decrement happens on + * the same CPU as the increment, avoiding the + * increment-on-one-CPU-and-decrement-on-another problem. + * + * If the reader misses the writer's assignment of readers_block, then + * the writer is guaranteed to see the reader's increment. * - * If this helper fails the callers rely on the normal rw_semaphore and - * atomic_dec_and_test(), so in this case we have the necessary barriers. + * Conversely, any readers that increment their sem->read_count after + * the writer looks are guaranteed to see the readers_block value, + * which in turn means that they are guaranteed to immediately + * decrement their sem->read_count, so that it doesn't matter that the + * writer missed them. */ -static bool update_fast_ctr(struct percpu_rw_semaphore *brw, unsigned int val) -{ - bool success; - preempt_disable(); - success = rcu_sync_is_idle(&brw->rss); - if (likely(success)) - __this_cpu_add(*brw->fast_read_ctr, val); - preempt_enable(); + smp_mb(); /* A matches D */ - return success; -} + /* + * If !readers_block the critical section starts here, matched by the + * release in percpu_up_write(). + */ + if (likely(!smp_load_acquire(&sem->readers_block))) + return 1; /* - * Like the normal down_read() this is not recursive, the writer can - * come after the first percpu_down_read() and create the deadlock. - * - * Note: returns with lock_is_held(brw->rw_sem) == T for lockdep, - * percpu_up_read() does rwsem_release(). This pairs with the usage - * of ->rw_sem in percpu_down/up_write(). + * Per the above comment; we still have preemption disabled and + * will thus decrement on the same CPU as we incremented. */ -void percpu_down_read(struct percpu_rw_semaphore *brw) -{ - might_sleep(); - rwsem_acquire_read(&brw->rw_sem.dep_map, 0, 0, _RET_IP_); + __percpu_up_read(sem); - if (likely(update_fast_ctr(brw, +1))) - return; + if (try) + return 0; - /* Avoid rwsem_acquire_read() and rwsem_release() */ - __down_read(&brw->rw_sem); - atomic_inc(&brw->slow_read_ctr); - __up_read(&brw->rw_sem); -} -EXPORT_SYMBOL_GPL(percpu_down_read); + /* + * We either call schedule() in the wait, or we'll fall through + * and reschedule on the preempt_enable() in percpu_down_read(). + */ + preempt_enable_no_resched(); -int percpu_down_read_trylock(struct percpu_rw_semaphore *brw) -{ - if (unlikely(!update_fast_ctr(brw, +1))) { - if (!__down_read_trylock(&brw->rw_sem)) - return 0; - atomic_inc(&brw->slow_read_ctr); - __up_read(&brw->rw_sem); - } + /* + * Avoid lockdep for the down/up_read() we already have them. + */ + __down_read(&sem->rw_sem); + this_cpu_inc(*sem->read_count); + __up_read(&sem->rw_sem); - rwsem_acquire_read(&brw->rw_sem.dep_map, 0, 1, _RET_IP_); + preempt_disable(); return 1; } +EXPORT_SYMBOL_GPL(__percpu_down_read); -void percpu_up_read(struct percpu_rw_semaphore *brw) +void __percpu_up_read(struct percpu_rw_semaphore *sem) { - rwsem_release(&brw->rw_sem.dep_map, 1, _RET_IP_); - - if (likely(update_fast_ctr(brw, -1))) - return; + smp_mb(); /* B matches C */ + /* + * In other words, if they see our decrement (presumably to aggregate + * zero, as that is the only time it matters) they will also see our + * critical section. + */ + __this_cpu_dec(*sem->read_count); - /* false-positive is possible but harmless */ - if (atomic_dec_and_test(&brw->slow_read_ctr)) - wake_up_all(&brw->write_waitq); + /* Prod writer to recheck readers_active */ + wake_up(&sem->writer); } -EXPORT_SYMBOL_GPL(percpu_up_read); +EXPORT_SYMBOL_GPL(__percpu_up_read); + +#define per_cpu_sum(var) \ +({ \ + typeof(var) __sum = 0; \ + int cpu; \ + compiletime_assert_atomic_type(__sum); \ + for_each_possible_cpu(cpu) \ + __sum += per_cpu(var, cpu); \ + __sum; \ +}) -static int clear_fast_ctr(struct percpu_rw_semaphore *brw) +/* + * Return true if the modular sum of the sem->read_count per-CPU variable is + * zero. If this sum is zero, then it is stable due to the fact that if any + * newly arriving readers increment a given counter, they will immediately + * decrement that same counter. + */ +static bool readers_active_check(struct percpu_rw_semaphore *sem) { - unsigned int sum = 0; - int cpu; + if (per_cpu_sum(*sem->read_count) != 0) + return false; - for_each_possible_cpu(cpu) { - sum += per_cpu(*brw->fast_read_ctr, cpu); - per_cpu(*brw->fast_read_ctr, cpu) = 0; - } + /* + * If we observed the decrement; ensure we see the entire critical + * section. + */ + + smp_mb(); /* C matches B */ - return sum; + return true; } -void percpu_down_write(struct percpu_rw_semaphore *brw) +void percpu_down_write(struct percpu_rw_semaphore *sem) { + /* Notify readers to take the slow path. */ + rcu_sync_enter(&sem->rss); + + down_write(&sem->rw_sem); + /* - * Make rcu_sync_is_idle() == F and thus disable the fast-path in - * percpu_down_read() and percpu_up_read(), and wait for gp pass. - * - * The latter synchronises us with the preceding readers which used - * the fast-past, so we can not miss the result of __this_cpu_add() - * or anything else inside their criticial sections. + * Notify new readers to block; up until now, and thus throughout the + * longish rcu_sync_enter() above, new readers could still come in. */ - rcu_sync_enter(&brw->rss); + WRITE_ONCE(sem->readers_block, 1); - /* exclude other writers, and block the new readers completely */ - down_write(&brw->rw_sem); + smp_mb(); /* D matches A */ - /* nobody can use fast_read_ctr, move its sum into slow_read_ctr */ - atomic_add(clear_fast_ctr(brw), &brw->slow_read_ctr); + /* + * If they don't see our writer of readers_block, then we are + * guaranteed to see their sem->read_count increment, and therefore + * will wait for them. + */ - /* wait for all readers to complete their percpu_up_read() */ - wait_event(brw->write_waitq, !atomic_read(&brw->slow_read_ctr)); + /* Wait for all now active readers to complete. */ + wait_event(sem->writer, readers_active_check(sem)); } EXPORT_SYMBOL_GPL(percpu_down_write); -void percpu_up_write(struct percpu_rw_semaphore *brw) +void percpu_up_write(struct percpu_rw_semaphore *sem) { - /* release the lock, but the readers can't use the fast-path */ - up_write(&brw->rw_sem); /* - * Enable the fast-path in percpu_down_read() and percpu_up_read() - * but only after another gp pass; this adds the necessary barrier - * to ensure the reader can't miss the changes done by us. + * Signal the writer is done, no fast path yet. + * + * One reason that we cannot just immediately flip to readers_fast is + * that new readers might fail to see the results of this writer's + * critical section. + * + * Therefore we force it through the slow path which guarantees an + * acquire and thereby guarantees the critical section's consistency. + */ + smp_store_release(&sem->readers_block, 0); + + /* + * Release the write lock, this will allow readers back in the game. + */ + up_write(&sem->rw_sem); + + /* + * Once this completes (at least one RCU-sched grace period hence) the + * reader fast path will be available again. Safe to use outside the + * exclusive write lock because its counting. */ - rcu_sync_exit(&brw->rss); + rcu_sync_exit(&sem->rss); } EXPORT_SYMBOL_GPL(percpu_up_write); diff -ruw linux-4.4.115/kernel/locking/rwsem-xadd.c linux-4.4.115-fbx/kernel/locking/rwsem-xadd.c --- linux-4.4.115/kernel/locking/rwsem-xadd.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/kernel/locking/rwsem-xadd.c 2019-10-29 09:26:25.601222339 +0100 @@ -511,6 +511,41 @@ unsigned long flags; /* + * If a spinner is present, there is a chance that the load of + * rwsem_has_spinner() in rwsem_wake() can be reordered with + * respect to decrement of rwsem count in __up_write() leading + * to wakeup being missed. + * + * spinning writer up_write caller + * --------------- ----------------------- + * [S] osq_unlock() [L] osq + * spin_lock(wait_lock) + * sem->count=0xFFFFFFFF00000001 + * +0xFFFFFFFF00000000 + * count=sem->count + * MB + * sem->count=0xFFFFFFFE00000001 + * -0xFFFFFFFF00000001 + * RMB + * spin_trylock(wait_lock) + * return + * rwsem_try_write_lock(count) + * spin_unlock(wait_lock) + * schedule() + * + * Reordering of atomic_long_sub_return_release() in __up_write() + * and rwsem_has_spinner() in rwsem_wake() can cause missing of + * wakeup in up_write() context. In spinning writer, sem->count + * and local variable count is 0XFFFFFFFE00000001. It would result + * in rwsem_try_write_lock() failing to acquire rwsem and spinning + * writer going to sleep in rwsem_down_write_failed(). + * + * The smp_rmb() here is to make sure that the spinner state is + * consulted after sem->count is updated in up_write context. + */ + smp_rmb(); + + /* * If a spinner is present, it is not necessary to do the wakeup. * Try to do wakeup only if the trylock succeeds to minimize * spinlock contention which may introduce too much delay in the diff -ruw linux-4.4.115/kernel/Makefile linux-4.4.115-fbx/kernel/Makefile --- linux-4.4.115/kernel/Makefile 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/kernel/Makefile 2019-01-22 16:16:28.627292807 +0100 @@ -19,6 +19,17 @@ CFLAGS_REMOVE_irq_work.o = $(CC_FLAGS_FTRACE) endif +# Prevents flicker of uninteresting __do_softirq()/__local_bh_disable_ip() +# in coverage traces. +KCOV_INSTRUMENT_softirq.o := n +# These are called from save_stack_trace() on slub debug path, +# and produce insane amounts of uninteresting coverage. +KCOV_INSTRUMENT_module.o := n +KCOV_INSTRUMENT_extable.o := n +# Don't self-instrument. +KCOV_INSTRUMENT_kcov.o := n +KASAN_SANITIZE_kcov.o := n + # cond_syscall is currently not LTO compatible CFLAGS_sys_ni.o = $(DISABLE_LTO) @@ -69,6 +80,7 @@ obj-$(CONFIG_AUDIT_WATCH) += audit_watch.o audit_fsnotify.o obj-$(CONFIG_AUDIT_TREE) += audit_tree.o obj-$(CONFIG_GCOV_KERNEL) += gcov/ +obj-$(CONFIG_KCOV) += kcov.o obj-$(CONFIG_KPROBES) += kprobes.o obj-$(CONFIG_KGDB) += debug/ obj-$(CONFIG_DETECT_HUNG_TASK) += hung_task.o diff -ruw linux-4.4.115/kernel/module.c linux-4.4.115-fbx/kernel/module.c --- linux-4.4.115/kernel/module.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/kernel/module.c 2019-10-29 09:26:25.601222339 +0100 @@ -2585,7 +2585,13 @@ return vmalloc_exec(size); } -#ifdef CONFIG_DEBUG_KMEMLEAK +#if defined(CONFIG_DEBUG_KMEMLEAK) && defined(CONFIG_DEBUG_MODULE_SCAN_OFF) +static void kmemleak_load_module(const struct module *mod, + const struct load_info *info) +{ + kmemleak_no_scan(mod->module_core); +} +#elif defined(CONFIG_DEBUG_KMEMLEAK) static void kmemleak_load_module(const struct module *mod, const struct load_info *info) { diff -ruw linux-4.4.115/kernel/panic.c linux-4.4.115-fbx/kernel/panic.c --- linux-4.4.115/kernel/panic.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/kernel/panic.c 2019-01-22 16:16:28.675293242 +0100 @@ -24,6 +24,10 @@ #include #include #include +#include + +#define CREATE_TRACE_POINTS +#include #define PANIC_TIMER_STEP 100 #define PANIC_BLINK_SPD 18 @@ -77,6 +81,8 @@ long i, i_next = 0; int state = 0; + trace_kernel_panic(0); + /* * Disable local interrupts. This will prevent panic_smp_self_stop * from deadlocking the first cpu that invokes the panic, since @@ -103,6 +109,7 @@ va_start(args, fmt); vsnprintf(buf, sizeof(buf), fmt, args); va_end(args); + dump_stack_minidump(0); pr_emerg("Kernel panic - not syncing: %s\n", buf); #ifdef CONFIG_DEBUG_BUGVERBOSE /* @@ -178,6 +185,9 @@ mdelay(PANIC_TIMER_STEP); } } + + trace_kernel_panic_late(0); + if (panic_timeout != 0) { /* * This will not be a clean reboot, with everything diff -ruw linux-4.4.115/kernel/power/Kconfig linux-4.4.115-fbx/kernel/power/Kconfig --- linux-4.4.115/kernel/power/Kconfig 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/kernel/power/Kconfig 2019-10-29 09:26:25.605222378 +0100 @@ -1,6 +1,7 @@ config SUSPEND bool "Suspend to RAM and standby" depends on ARCH_SUSPEND_POSSIBLE + select RTC_LIB default y ---help--- Allow the system to enter sleep states in which main memory is @@ -28,6 +29,15 @@ of suspend, or they are content with invoking sync() from user-space before invoking suspend. Say Y if that's your case. +config WAKELOCK + bool "Android's method of preventing suspend" + default y + ---help--- + This allows applications to prevent the CPU from suspending while + they need it. + + Say Y if you are running an android userspace. + config HIBERNATE_CALLBACKS bool diff -ruw linux-4.4.115/kernel/power/main.c linux-4.4.115-fbx/kernel/power/main.c --- linux-4.4.115/kernel/power/main.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/kernel/power/main.c 2019-01-22 16:16:28.679293278 +0100 @@ -38,12 +38,19 @@ } EXPORT_SYMBOL_GPL(unregister_pm_notifier); -int pm_notifier_call_chain(unsigned long val) +int __pm_notifier_call_chain(unsigned long val, int nr_to_call, int *nr_calls) { - int ret = blocking_notifier_call_chain(&pm_chain_head, val, NULL); + int ret; + + ret = __blocking_notifier_call_chain(&pm_chain_head, val, NULL, + nr_to_call, nr_calls); return notifier_to_errno(ret); } +int pm_notifier_call_chain(unsigned long val) +{ + return __pm_notifier_call_chain(val, -1, NULL); +} /* If set, devices may be suspended and resumed asynchronously. */ int pm_async_enabled = 1; @@ -280,13 +287,7 @@ return pm_wakeup_irq ? sprintf(buf, "%u\n", pm_wakeup_irq) : -ENODATA; } -static ssize_t pm_wakeup_irq_store(struct kobject *kobj, - struct kobj_attribute *attr, - const char *buf, size_t n) -{ - return -EINVAL; -} -power_attr(pm_wakeup_irq); +power_attr_ro(pm_wakeup_irq); #else /* !CONFIG_PM_SLEEP_DEBUG */ static inline void pm_print_times_init(void) {} @@ -564,14 +565,7 @@ return show_trace_dev_match(buf, PAGE_SIZE); } -static ssize_t -pm_trace_dev_match_store(struct kobject *kobj, struct kobj_attribute *attr, - const char *buf, size_t n) -{ - return -EINVAL; -} - -power_attr(pm_trace_dev_match); +power_attr_ro(pm_trace_dev_match); #endif /* CONFIG_PM_TRACE */ diff -ruw linux-4.4.115/kernel/power/Makefile linux-4.4.115-fbx/kernel/power/Makefile --- linux-4.4.115/kernel/power/Makefile 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/kernel/power/Makefile 2019-01-22 16:16:28.675293242 +0100 @@ -12,3 +12,5 @@ obj-$(CONFIG_PM_WAKELOCKS) += wakelock.o obj-$(CONFIG_MAGIC_SYSRQ) += poweroff.o + +obj-$(CONFIG_SUSPEND) += wakeup_reason.o diff -ruw linux-4.4.115/kernel/power/power.h linux-4.4.115-fbx/kernel/power/power.h --- linux-4.4.115/kernel/power/power.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/kernel/power/power.h 2019-10-29 09:26:25.605222378 +0100 @@ -77,6 +77,15 @@ .store = _name##_store, \ } +#define power_attr_ro(_name) \ +static struct kobj_attribute _name##_attr = { \ + .attr = { \ + .name = __stringify(_name), \ + .mode = S_IRUGO, \ + }, \ + .show = _name##_show, \ +} + /* Preferred image size in bytes (default 500 MB) */ extern unsigned long image_size; /* Size of memory reserved for drivers (default SPARE_PAGES x PAGE_SIZE) */ @@ -191,6 +200,8 @@ #ifdef CONFIG_PM_SLEEP /* kernel/power/main.c */ +extern int __pm_notifier_call_chain(unsigned long val, int nr_to_call, + int *nr_calls); extern int pm_notifier_call_chain(unsigned long val); #endif diff -ruw linux-4.4.115/kernel/power/process.c linux-4.4.115-fbx/kernel/power/process.c --- linux-4.4.115/kernel/power/process.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/kernel/power/process.c 2019-01-22 16:16:28.679293278 +0100 @@ -18,6 +18,7 @@ #include #include #include +#include #include /* @@ -36,6 +37,9 @@ unsigned int elapsed_msecs; bool wakeup = false; int sleep_usecs = USEC_PER_MSEC; +#ifdef CONFIG_PM_SLEEP + char suspend_abort[MAX_SUSPEND_ABORT_LEN]; +#endif do_gettimeofday(&start); @@ -65,6 +69,11 @@ break; if (pm_wakeup_pending()) { +#ifdef CONFIG_PM_SLEEP + pm_get_active_wakeup_sources(suspend_abort, + MAX_SUSPEND_ABORT_LEN); + log_suspend_abort_reason(suspend_abort); +#endif wakeup = true; break; } @@ -84,15 +93,17 @@ do_div(elapsed_msecs64, NSEC_PER_MSEC); elapsed_msecs = elapsed_msecs64; - if (todo) { + if (wakeup) { pr_cont("\n"); - pr_err("Freezing of tasks %s after %d.%03d seconds " + pr_err("Freezing of tasks aborted after %d.%03d seconds", + elapsed_msecs / 1000, elapsed_msecs % 1000); + } else if (todo) { + pr_cont("\n"); + pr_err("Freezing of tasks failed after %d.%03d seconds" "(%d tasks refusing to freeze, wq_busy=%d):\n", - wakeup ? "aborted" : "failed", elapsed_msecs / 1000, elapsed_msecs % 1000, todo - wq_busy, wq_busy); - if (!wakeup) { read_lock(&tasklist_lock); for_each_process_thread(g, p) { if (p != current && !freezer_should_skip(p) @@ -100,7 +111,6 @@ sched_show_task(p); } read_unlock(&tasklist_lock); - } } else { pr_cont("(elapsed %d.%03d seconds) ", elapsed_msecs / 1000, elapsed_msecs % 1000); diff -ruw linux-4.4.115/kernel/power/qos.c linux-4.4.115-fbx/kernel/power/qos.c --- linux-4.4.115/kernel/power/qos.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/kernel/power/qos.c 2019-01-22 16:16:28.679293278 +0100 @@ -43,6 +43,9 @@ #include #include #include +#include +#include +#include #include #include @@ -67,6 +70,8 @@ static struct pm_qos_constraints cpu_dma_constraints = { .list = PLIST_HEAD_INIT(cpu_dma_constraints.list), .target_value = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE, + .target_per_cpu = { [0 ... (NR_CPUS - 1)] = + PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE }, .default_value = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE, .no_constraint_value = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE, .type = PM_QOS_MIN, @@ -81,6 +86,8 @@ static struct pm_qos_constraints network_lat_constraints = { .list = PLIST_HEAD_INIT(network_lat_constraints.list), .target_value = PM_QOS_NETWORK_LAT_DEFAULT_VALUE, + .target_per_cpu = { [0 ... (NR_CPUS - 1)] = + PM_QOS_NETWORK_LAT_DEFAULT_VALUE }, .default_value = PM_QOS_NETWORK_LAT_DEFAULT_VALUE, .no_constraint_value = PM_QOS_NETWORK_LAT_DEFAULT_VALUE, .type = PM_QOS_MIN, @@ -91,11 +98,12 @@ .name = "network_latency", }; - static BLOCKING_NOTIFIER_HEAD(network_throughput_notifier); static struct pm_qos_constraints network_tput_constraints = { .list = PLIST_HEAD_INIT(network_tput_constraints.list), .target_value = PM_QOS_NETWORK_THROUGHPUT_DEFAULT_VALUE, + .target_per_cpu = { [0 ... (NR_CPUS - 1)] = + PM_QOS_NETWORK_THROUGHPUT_DEFAULT_VALUE }, .default_value = PM_QOS_NETWORK_THROUGHPUT_DEFAULT_VALUE, .no_constraint_value = PM_QOS_NETWORK_THROUGHPUT_DEFAULT_VALUE, .type = PM_QOS_MAX, @@ -259,22 +267,60 @@ .release = single_release, }; +static inline void pm_qos_set_value_for_cpus(struct pm_qos_constraints *c, + struct cpumask *cpus) +{ + struct pm_qos_request *req = NULL; + int cpu; + s32 qos_val[NR_CPUS] = { [0 ... (NR_CPUS - 1)] = c->default_value }; + + plist_for_each_entry(req, &c->list, node) { + for_each_cpu(cpu, &req->cpus_affine) { + switch (c->type) { + case PM_QOS_MIN: + if (qos_val[cpu] > req->node.prio) + qos_val[cpu] = req->node.prio; + break; + case PM_QOS_MAX: + if (req->node.prio > qos_val[cpu]) + qos_val[cpu] = req->node.prio; + break; + case PM_QOS_SUM: + qos_val[cpu] += req->node.prio; + break; + default: + BUG(); + break; + } + } + } + + for_each_possible_cpu(cpu) { + if (c->target_per_cpu[cpu] != qos_val[cpu]) + cpumask_set_cpu(cpu, cpus); + c->target_per_cpu[cpu] = qos_val[cpu]; + } +} + /** * pm_qos_update_target - manages the constraints list and calls the notifiers * if needed * @c: constraints data struct - * @node: request to add to the list, to update or to remove + * @req: request to add to the list, to update or to remove * @action: action to take on the constraints list * @value: value of the request to add or update * * This function returns 1 if the aggregated constraint value has changed, 0 * otherwise. */ -int pm_qos_update_target(struct pm_qos_constraints *c, struct plist_node *node, +int pm_qos_update_target(struct pm_qos_constraints *c, + struct pm_qos_request *req, enum pm_qos_req_action action, int value) { unsigned long flags; int prev_value, curr_value, new_value; + struct plist_node *node = &req->node; + struct cpumask cpus; int ret; spin_lock_irqsave(&pm_qos_lock, flags); @@ -305,17 +351,23 @@ } curr_value = pm_qos_get_value(c); + cpumask_clear(&cpus); pm_qos_set_value(c, curr_value); + pm_qos_set_value_for_cpus(c, &cpus); spin_unlock_irqrestore(&pm_qos_lock, flags); trace_pm_qos_update_target(action, prev_value, curr_value); - if (prev_value != curr_value) { + /* + * if cpu mask bits are set, call the notifier call chain + * to update the new qos restriction for the cores + */ + if (!cpumask_empty(&cpus)) { ret = 1; if (c->notifiers) blocking_notifier_call_chain(c->notifiers, (unsigned long)curr_value, - NULL); + &cpus); } else { ret = 0; } @@ -398,12 +450,56 @@ } EXPORT_SYMBOL_GPL(pm_qos_request); +int pm_qos_request_for_cpu(int pm_qos_class, int cpu) +{ + if (cpu_isolated(cpu)) + return INT_MAX; + + return pm_qos_array[pm_qos_class]->constraints->target_per_cpu[cpu]; +} +EXPORT_SYMBOL(pm_qos_request_for_cpu); + int pm_qos_request_active(struct pm_qos_request *req) { return req->pm_qos_class != 0; } EXPORT_SYMBOL_GPL(pm_qos_request_active); +int pm_qos_request_for_cpumask(int pm_qos_class, struct cpumask *mask) +{ + unsigned long irqflags; + int cpu; + struct pm_qos_constraints *c = NULL; + int val; + + spin_lock_irqsave(&pm_qos_lock, irqflags); + c = pm_qos_array[pm_qos_class]->constraints; + val = c->default_value; + + for_each_cpu(cpu, mask) { + if (cpu_isolated(cpu)) + continue; + + switch (c->type) { + case PM_QOS_MIN: + if (c->target_per_cpu[cpu] < val) + val = c->target_per_cpu[cpu]; + break; + case PM_QOS_MAX: + if (c->target_per_cpu[cpu] > val) + val = c->target_per_cpu[cpu]; + break; + default: + BUG(); + break; + } + } + spin_unlock_irqrestore(&pm_qos_lock, irqflags); + + return val; +} +EXPORT_SYMBOL(pm_qos_request_for_cpumask); + static void __pm_qos_update_request(struct pm_qos_request *req, s32 new_value) { @@ -412,7 +508,7 @@ if (new_value != req->node.prio) pm_qos_update_target( pm_qos_array[req->pm_qos_class]->constraints, - &req->node, PM_QOS_UPDATE_REQ, new_value); + req, PM_QOS_UPDATE_REQ, new_value); } /** @@ -430,6 +526,41 @@ __pm_qos_update_request(req, PM_QOS_DEFAULT_VALUE); } +#ifdef CONFIG_SMP +static void pm_qos_irq_release(struct kref *ref) +{ + unsigned long flags; + struct irq_affinity_notify *notify = container_of(ref, + struct irq_affinity_notify, kref); + struct pm_qos_request *req = container_of(notify, + struct pm_qos_request, irq_notify); + struct pm_qos_constraints *c = + pm_qos_array[req->pm_qos_class]->constraints; + + spin_lock_irqsave(&pm_qos_lock, flags); + cpumask_setall(&req->cpus_affine); + spin_unlock_irqrestore(&pm_qos_lock, flags); + + pm_qos_update_target(c, req, PM_QOS_UPDATE_REQ, c->default_value); +} + +static void pm_qos_irq_notify(struct irq_affinity_notify *notify, + const cpumask_t *mask) +{ + unsigned long flags; + struct pm_qos_request *req = container_of(notify, + struct pm_qos_request, irq_notify); + struct pm_qos_constraints *c = + pm_qos_array[req->pm_qos_class]->constraints; + + spin_lock_irqsave(&pm_qos_lock, flags); + cpumask_copy(&req->cpus_affine, mask); + spin_unlock_irqrestore(&pm_qos_lock, flags); + + pm_qos_update_target(c, req, PM_QOS_UPDATE_REQ, req->node.prio); +} +#endif + /** * pm_qos_add_request - inserts new qos request into the list * @req: pointer to a preallocated handle @@ -453,11 +584,70 @@ WARN(1, KERN_ERR "pm_qos_add_request() called for already added request\n"); return; } + + switch (req->type) { + case PM_QOS_REQ_AFFINE_CORES: + if (cpumask_empty(&req->cpus_affine)) { + req->type = PM_QOS_REQ_ALL_CORES; + cpumask_setall(&req->cpus_affine); + WARN(1, KERN_ERR "Affine cores not set for request with affinity flag\n"); + } + break; +#ifdef CONFIG_SMP + case PM_QOS_REQ_AFFINE_IRQ: + if (irq_can_set_affinity(req->irq)) { + struct irq_desc *desc = irq_to_desc(req->irq); + struct cpumask *mask; + + if (!desc) + return; + mask = desc->irq_data.common->affinity; + + /* Get the current affinity */ + cpumask_copy(&req->cpus_affine, mask); + req->irq_notify.irq = req->irq; + req->irq_notify.notify = pm_qos_irq_notify; + req->irq_notify.release = pm_qos_irq_release; + + } else { + req->type = PM_QOS_REQ_ALL_CORES; + cpumask_setall(&req->cpus_affine); + WARN(1, KERN_ERR "IRQ-%d not set for request with affinity flag\n", + req->irq); + } + break; +#endif + default: + WARN(1, KERN_ERR "Unknown request type %d\n", req->type); + /* fall through */ + case PM_QOS_REQ_ALL_CORES: + cpumask_setall(&req->cpus_affine); + break; + } + req->pm_qos_class = pm_qos_class; INIT_DELAYED_WORK(&req->work, pm_qos_work_fn); trace_pm_qos_add_request(pm_qos_class, value); pm_qos_update_target(pm_qos_array[pm_qos_class]->constraints, - &req->node, PM_QOS_ADD_REQ, value); + req, PM_QOS_ADD_REQ, value); + +#ifdef CONFIG_SMP + if (req->type == PM_QOS_REQ_AFFINE_IRQ && + irq_can_set_affinity(req->irq)) { + int ret = 0; + + ret = irq_set_affinity_notifier(req->irq, + &req->irq_notify); + if (ret) { + WARN(1, "IRQ affinity notify set failed\n"); + req->type = PM_QOS_REQ_ALL_CORES; + cpumask_setall(&req->cpus_affine); + pm_qos_update_target( + pm_qos_array[pm_qos_class]->constraints, + req, PM_QOS_UPDATE_REQ, value); + } + } +#endif } EXPORT_SYMBOL_GPL(pm_qos_add_request); @@ -511,7 +701,7 @@ if (new_value != req->node.prio) pm_qos_update_target( pm_qos_array[req->pm_qos_class]->constraints, - &req->node, PM_QOS_UPDATE_REQ, new_value); + req, PM_QOS_UPDATE_REQ, new_value); schedule_delayed_work(&req->work, usecs_to_jiffies(timeout_us)); } @@ -531,15 +721,25 @@ /* silent return to keep pcm code cleaner */ if (!pm_qos_request_active(req)) { - WARN(1, KERN_ERR "pm_qos_remove_request() called for unknown object\n"); + WARN(1, "pm_qos_remove_request() called for unknown object\n"); return; } cancel_delayed_work_sync(&req->work); +#ifdef CONFIG_SMP + if (req->type == PM_QOS_REQ_AFFINE_IRQ) { + int ret = 0; + /* Get the current affinity */ + ret = irq_set_affinity_notifier(req->irq, NULL); + if (ret) + WARN(1, "IRQ affinity notify set failed\n"); + } +#endif + trace_pm_qos_remove_request(req->pm_qos_class, PM_QOS_DEFAULT_VALUE); pm_qos_update_target(pm_qos_array[req->pm_qos_class]->constraints, - &req->node, PM_QOS_REMOVE_REQ, + req, PM_QOS_REMOVE_REQ, PM_QOS_DEFAULT_VALUE); memset(req, 0, sizeof(*req)); } diff -ruw linux-4.4.115/kernel/power/suspend.c linux-4.4.115-fbx/kernel/power/suspend.c --- linux-4.4.115/kernel/power/suspend.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/kernel/power/suspend.c 2019-01-22 16:16:28.679293278 +0100 @@ -26,9 +26,11 @@ #include #include #include +#include #include #include #include +#include #include "power.h" @@ -266,16 +268,18 @@ */ static int suspend_prepare(suspend_state_t state) { - int error; + int error, nr_calls = 0; if (!sleep_state_supported(state)) return -EPERM; pm_prepare_console(); - error = pm_notifier_call_chain(PM_SUSPEND_PREPARE); - if (error) + error = __pm_notifier_call_chain(PM_SUSPEND_PREPARE, -1, &nr_calls); + if (error) { + nr_calls--; goto Finish; + } trace_suspend_resume(TPS("freeze_processes"), 0, true); error = suspend_freeze_processes(); @@ -286,7 +290,7 @@ suspend_stats.failed_freeze++; dpm_save_failed_step(SUSPEND_FREEZE); Finish: - pm_notifier_call_chain(PM_POST_SUSPEND); + __pm_notifier_call_chain(PM_POST_SUSPEND, nr_calls, NULL); pm_restore_console(); return error; } @@ -312,7 +316,8 @@ */ static int suspend_enter(suspend_state_t state, bool *wakeup) { - int error; + char suspend_abort[MAX_SUSPEND_ABORT_LEN]; + int error, last_dev; error = platform_suspend_prepare(state); if (error) @@ -320,7 +325,11 @@ error = dpm_suspend_late(PMSG_SUSPEND); if (error) { + last_dev = suspend_stats.last_failed_dev + REC_FAILED_NUM - 1; + last_dev %= REC_FAILED_NUM; printk(KERN_ERR "PM: late suspend of devices failed\n"); + log_suspend_abort_reason("%s device failed to power down", + suspend_stats.failed_devs[last_dev]); goto Platform_finish; } error = platform_suspend_prepare_late(state); @@ -329,7 +338,11 @@ error = dpm_suspend_noirq(PMSG_SUSPEND); if (error) { + last_dev = suspend_stats.last_failed_dev + REC_FAILED_NUM - 1; + last_dev %= REC_FAILED_NUM; printk(KERN_ERR "PM: noirq suspend of devices failed\n"); + log_suspend_abort_reason("noirq suspend of %s device failed", + suspend_stats.failed_devs[last_dev]); goto Platform_early_resume; } error = platform_suspend_prepare_noirq(state); @@ -353,8 +366,10 @@ } error = disable_nonboot_cpus(); - if (error || suspend_test(TEST_CPUS)) + if (error || suspend_test(TEST_CPUS)) { + log_suspend_abort_reason("Disabling non-boot cpus failed"); goto Enable_cpus; + } arch_suspend_disable_irqs(); BUG_ON(!irqs_disabled()); @@ -370,6 +385,9 @@ state, false); events_check_enabled = false; } else if (*wakeup) { + pm_get_active_wakeup_sources(suspend_abort, + MAX_SUSPEND_ABORT_LEN); + log_suspend_abort_reason(suspend_abort); error = -EBUSY; } syscore_resume(); @@ -417,6 +435,7 @@ error = dpm_suspend_start(PMSG_SUSPEND); if (error) { pr_err("PM: Some devices failed to suspend, or early wake event detected\n"); + log_suspend_abort_reason("Some devices failed to suspend, or early wake event detected"); goto Recover_platform; } suspend_test_finish("suspend devices"); @@ -518,6 +537,18 @@ return error; } +static void pm_suspend_marker(char *annotation) +{ + struct timespec ts; + struct rtc_time tm; + + getnstimeofday(&ts); + rtc_time_to_tm(ts.tv_sec, &tm); + pr_info("PM: suspend %s %d-%02d-%02d %02d:%02d:%02d.%09lu UTC\n", + annotation, tm.tm_year + 1900, tm.tm_mon + 1, tm.tm_mday, + tm.tm_hour, tm.tm_min, tm.tm_sec, ts.tv_nsec); +} + /** * pm_suspend - Externally visible function for suspending the system. * @state: System sleep state to enter. @@ -532,6 +563,7 @@ if (state <= PM_SUSPEND_ON || state >= PM_SUSPEND_MAX) return -EINVAL; + pm_suspend_marker("entry"); error = enter_state(state); if (error) { suspend_stats.fail++; @@ -539,6 +571,7 @@ } else { suspend_stats.success++; } + pm_suspend_marker("exit"); return error; } EXPORT_SYMBOL(pm_suspend); diff -ruw linux-4.4.115/kernel/printk/printk.c linux-4.4.115-fbx/kernel/printk/printk.c --- linux-4.4.115/kernel/printk/printk.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/kernel/printk/printk.c 2019-10-29 09:26:25.609222418 +0100 @@ -55,6 +55,10 @@ #include "console_cmdline.h" #include "braille.h" +#ifdef CONFIG_EARLY_PRINTK_DIRECT +extern void printascii(char *); +#endif + int console_printk[4] = { CONSOLE_LOGLEVEL_DEFAULT, /* console_loglevel */ MESSAGE_LOGLEVEL_DEFAULT, /* default_message_loglevel */ @@ -232,7 +236,11 @@ u8 facility; /* syslog facility */ u8 flags:5; /* internal record flags */ u8 level:3; /* syslog level */ -}; +} +#ifdef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS +__packed __aligned(4) +#endif +; /* * The logbuf_lock protects kmsg buffer, indices, counters. This can be taken @@ -273,11 +281,7 @@ #define LOG_FACILITY(v) ((v) >> 3 & 0xff) /* record buffer */ -#if defined(CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS) -#define LOG_ALIGN 4 -#else #define LOG_ALIGN __alignof__(struct printk_log) -#endif #define __LOG_BUF_LEN (1 << CONFIG_LOG_BUF_SHIFT) static char __log_buf[__LOG_BUF_LEN] __aligned(LOG_ALIGN); static char *log_buf = __log_buf; @@ -1754,6 +1758,10 @@ } } +#ifdef CONFIG_EARLY_PRINTK_DIRECT + printascii(text); +#endif + if (level == LOGLEVEL_DEFAULT) level = default_message_loglevel; @@ -2130,8 +2138,12 @@ case CPU_DEAD: case CPU_DOWN_FAILED: case CPU_UP_CANCELED: + case CPU_DYING: +#ifdef CONFIG_CONSOLE_FLUSH_ON_HOTPLUG console_lock(); console_unlock(); +#endif + break; } return NOTIFY_OK; } @@ -3168,9 +3180,8 @@ { dump_stack_print_info(log_lvl); - printk("%stask: %p ti: %p task.ti: %p\n", - log_lvl, current, current_thread_info(), - task_thread_info(current)); + printk("%stask: %p task.stack: %p\n", + log_lvl, current, task_stack_page(current)); } #endif diff -ruw linux-4.4.115/kernel/rcu/Makefile linux-4.4.115-fbx/kernel/rcu/Makefile --- linux-4.4.115/kernel/rcu/Makefile 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/kernel/rcu/Makefile 2019-01-22 16:16:28.683293314 +0100 @@ -1,3 +1,7 @@ +# Any varying coverage in these files is non-deterministic +# and is generally not a function of system call inputs. +KCOV_INSTRUMENT := n + obj-y += update.o sync.o obj-$(CONFIG_SRCU) += srcu.o obj-$(CONFIG_RCU_TORTURE_TEST) += rcutorture.o diff -ruw linux-4.4.115/kernel/rcu/sync.c linux-4.4.115-fbx/kernel/rcu/sync.c --- linux-4.4.115/kernel/rcu/sync.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/kernel/rcu/sync.c 2019-01-22 16:16:28.683293314 +0100 @@ -68,6 +68,7 @@ RCU_LOCKDEP_WARN(!gp_ops[rsp->gp_type].held(), "suspicious rcu_sync_is_idle() usage"); } +EXPORT_SYMBOL_GPL(rcu_sync_lockdep_assert); #endif /** @@ -83,6 +84,18 @@ } /** + * Must be called after rcu_sync_init() and before first use. + * + * Ensures rcu_sync_is_idle() returns false and rcu_sync_{enter,exit}() + * pairs turn into NO-OPs. + */ +void rcu_sync_enter_start(struct rcu_sync *rsp) +{ + rsp->gp_count++; + rsp->gp_state = GP_PASSED; +} + +/** * rcu_sync_enter() - Force readers onto slowpath * @rsp: Pointer to rcu_sync structure to use for synchronization * diff -ruw linux-4.4.115/kernel/rcu/tree.c linux-4.4.115-fbx/kernel/rcu/tree.c --- linux-4.4.115/kernel/rcu/tree.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/kernel/rcu/tree.c 2019-10-29 09:26:25.613222457 +0100 @@ -57,6 +57,8 @@ #include #include +#include + #include "tree.h" #include "rcu.h" @@ -246,24 +248,17 @@ */ void rcu_sched_qs(void) { - unsigned long flags; - - if (__this_cpu_read(rcu_sched_data.cpu_no_qs.s)) { + if (!__this_cpu_read(rcu_sched_data.cpu_no_qs.s)) + return; trace_rcu_grace_period(TPS("rcu_sched"), __this_cpu_read(rcu_sched_data.gpnum), TPS("cpuqs")); __this_cpu_write(rcu_sched_data.cpu_no_qs.b.norm, false); if (!__this_cpu_read(rcu_sched_data.cpu_no_qs.b.exp)) return; - local_irq_save(flags); - if (__this_cpu_read(rcu_sched_data.cpu_no_qs.b.exp)) { __this_cpu_write(rcu_sched_data.cpu_no_qs.b.exp, false); rcu_report_exp_rdp(&rcu_sched_state, - this_cpu_ptr(&rcu_sched_data), - true); - } - local_irq_restore(flags); - } + this_cpu_ptr(&rcu_sched_data), true); } void rcu_bh_qs(void) @@ -300,17 +295,16 @@ * We inform the RCU core by emulating a zero-duration dyntick-idle * period, which we in turn do by incrementing the ->dynticks counter * by two. + * + * The caller must have disabled interrupts. */ static void rcu_momentary_dyntick_idle(void) { - unsigned long flags; struct rcu_data *rdp; struct rcu_dynticks *rdtp; int resched_mask; struct rcu_state *rsp; - local_irq_save(flags); - /* * Yes, we can lose flag-setting operations. This is OK, because * the flag will be set again after some delay. @@ -340,13 +334,12 @@ smp_mb__after_atomic(); /* Later stuff after QS. */ break; } - local_irq_restore(flags); } /* * Note a context switch. This is a quiescent state for RCU-sched, * and requires special handling for preemptible RCU. - * The caller must have disabled preemption. + * The caller must have disabled interrupts. */ void rcu_note_context_switch(void) { @@ -376,9 +369,14 @@ */ void rcu_all_qs(void) { + unsigned long flags; + barrier(); /* Avoid RCU read-side critical sections leaking down. */ - if (unlikely(raw_cpu_read(rcu_sched_qs_mask))) + if (unlikely(raw_cpu_read(rcu_sched_qs_mask))) { + local_irq_save(flags); rcu_momentary_dyntick_idle(); + local_irq_restore(flags); + } this_cpu_inc(rcu_qs_ctr); barrier(); /* Avoid RCU read-side critical sections leaking up. */ } @@ -1310,6 +1308,11 @@ rcu_check_gp_kthread_starvation(rsp); +#ifdef CONFIG_RCU_STALL_WATCHDOG_BITE + /* Induce watchdog bite */ + msm_trigger_wdog_bite(); +#endif + force_quiescent_state(rsp); /* Kick them all. */ } @@ -1345,6 +1348,11 @@ jiffies + 3 * rcu_jiffies_till_stall_check() + 3); raw_spin_unlock_irqrestore(&rnp->lock, flags); +#ifdef CONFIG_RCU_STALL_WATCHDOG_BITE + /* Induce non secure watchdog bite to collect context */ + msm_trigger_wdog_bite(); +#endif + /* * Attempt to revive the RCU machinery by forcing a context switch. * diff -ruw linux-4.4.115/kernel/rcu/tree_plugin.h linux-4.4.115-fbx/kernel/rcu/tree_plugin.h --- linux-4.4.115/kernel/rcu/tree_plugin.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/kernel/rcu/tree_plugin.h 2019-01-22 16:16:28.687293351 +0100 @@ -147,8 +147,8 @@ * the corresponding expedited grace period will also be the end of the * normal grace period. */ -static void rcu_preempt_ctxt_queue(struct rcu_node *rnp, struct rcu_data *rdp, - unsigned long flags) __releases(rnp->lock) +static void rcu_preempt_ctxt_queue(struct rcu_node *rnp, struct rcu_data *rdp) + __releases(rnp->lock) /* But leaves rrupts disabled. */ { int blkd_state = (rnp->gp_tasks ? RCU_GP_TASKS : 0) + (rnp->exp_tasks ? RCU_EXP_TASKS : 0) + @@ -236,7 +236,7 @@ rnp->gp_tasks = &t->rcu_node_entry; if (!rnp->exp_tasks && (blkd_state & RCU_EXP_BLKD)) rnp->exp_tasks = &t->rcu_node_entry; - raw_spin_unlock(&rnp->lock); + raw_spin_unlock(&rnp->lock); /* rrupts remain disabled. */ /* * Report the quiescent state for the expedited GP. This expedited @@ -251,7 +251,6 @@ } else { WARN_ON_ONCE(t->rcu_read_unlock_special.b.exp_need_qs); } - local_irq_restore(flags); } /* @@ -286,12 +285,11 @@ * predating the current grace period drain, in other words, until * rnp->gp_tasks becomes NULL. * - * Caller must disable preemption. + * Caller must disable interrupts. */ static void rcu_preempt_note_context_switch(void) { struct task_struct *t = current; - unsigned long flags; struct rcu_data *rdp; struct rcu_node *rnp; @@ -301,7 +299,7 @@ /* Possibly blocking in an RCU read-side critical section. */ rdp = this_cpu_ptr(rcu_state_p->rda); rnp = rdp->mynode; - raw_spin_lock_irqsave(&rnp->lock, flags); + raw_spin_lock(&rnp->lock); smp_mb__after_unlock_lock(); t->rcu_read_unlock_special.b.blocked = true; t->rcu_blocked_node = rnp; @@ -318,7 +316,7 @@ (rnp->qsmask & rdp->grpmask) ? rnp->gpnum : rnp->gpnum + 1); - rcu_preempt_ctxt_queue(rnp, rdp, flags); + rcu_preempt_ctxt_queue(rnp, rdp); } else if (t->rcu_read_lock_nesting < 0 && t->rcu_read_unlock_special.s) { diff -ruw linux-4.4.115/kernel/resource.c linux-4.4.115-fbx/kernel/resource.c --- linux-4.4.115/kernel/resource.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/kernel/resource.c 2019-10-29 09:26:25.613222457 +0100 @@ -172,7 +172,7 @@ static int __init ioresources_init(void) { proc_create("ioports", 0, NULL, &proc_ioports_operations); - proc_create("iomem", 0, NULL, &proc_iomem_operations); + proc_create("iomem", S_IRUSR, NULL, &proc_iomem_operations); return 0; } __initcall(ioresources_init); @@ -367,15 +367,14 @@ read_lock(&resource_lock); for (p = iomem_resource.child; p; p = next_resource(p, sibling_only)) { - if (p->flags != res->flags) - continue; - if (name && strcmp(p->name, name)) - continue; if (p->start > end) { p = NULL; break; } - if ((p->end >= start) && (p->start < end)) + if (p->flags != res->flags) + continue; + if ((p->end >= start) && (p->start < end) && + (name == NULL || !strcmp(p->name, name))) break; } diff -ruw linux-4.4.115/kernel/sched/clock.c linux-4.4.115-fbx/kernel/sched/clock.c --- linux-4.4.115/kernel/sched/clock.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/kernel/sched/clock.c 2019-01-22 16:16:28.691293387 +0100 @@ -354,7 +354,7 @@ return; sched_clock_tick(); - touch_softlockup_watchdog(); + touch_softlockup_watchdog_sched(); } EXPORT_SYMBOL_GPL(sched_clock_idle_wakeup_event); diff -ruw linux-4.4.115/kernel/sched/core.c linux-4.4.115-fbx/kernel/sched/core.c --- linux-4.4.115/kernel/sched/core.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/kernel/sched/core.c 2019-10-29 09:26:25.617222496 +0100 @@ -26,6 +26,7 @@ * Thomas Gleixner, Mike Kravetz */ +#include #include #include #include @@ -74,6 +75,8 @@ #include #include #include +#include +#include #include #include @@ -82,14 +85,20 @@ #ifdef CONFIG_PARAVIRT #include #endif +#ifdef CONFIG_MSM_APP_SETTINGS +#include +#endif #include "sched.h" #include "../workqueue_internal.h" #include "../smpboot.h" +#include "../time/tick-internal.h" #define CREATE_TRACE_POINTS #include +ATOMIC_NOTIFIER_HEAD(load_alert_notifier_head); + DEFINE_MUTEX(sched_domains_mutex); DEFINE_PER_CPU_SHARED_ALIGNED(struct rq, runqueues); @@ -287,6 +296,18 @@ /* cpus with isolated domains */ cpumask_var_t cpu_isolated_map; +struct rq * +lock_rq_of(struct task_struct *p, unsigned long *flags) +{ + return task_rq_lock(p, flags); +} + +void +unlock_rq_of(struct rq *rq, struct task_struct *p, unsigned long *flags) +{ + task_rq_unlock(rq, p, flags); +} + /* * this_rq_lock - lock this runqueue and disable interrupts. */ @@ -533,6 +554,8 @@ if (cmpxchg(&node->next, NULL, WAKE_Q_TAIL)) return; + head->count++; + get_task_struct(task); /* @@ -542,6 +565,10 @@ head->lastp = &node->next; } +static int +try_to_wake_up(struct task_struct *p, unsigned int state, int wake_flags, + int sibling_count_hint); + void wake_up_q(struct wake_q_head *head) { struct wake_q_node *node = head->first; @@ -556,10 +583,10 @@ task->wake_q.next = NULL; /* - * wake_up_process() implies a wmb() to pair with the queueing + * try_to_wake_up() implies a wmb() to pair with the queueing * in wake_q_add() so as not to miss wakeups. */ - wake_up_process(task); + try_to_wake_up(task, TASK_NORMAL, 0, head->count); put_task_struct(task); } } @@ -835,6 +862,7 @@ if (!(flags & ENQUEUE_RESTORE)) sched_info_queued(rq, p); p->sched_class->enqueue_task(rq, p, flags); + trace_sched_enq_deq_task(p, 1, cpumask_bits(&p->cpus_allowed)[0]); } static inline void dequeue_task(struct rq *rq, struct task_struct *p, int flags) @@ -843,6 +871,7 @@ if (!(flags & DEQUEUE_SAVE)) sched_info_dequeued(rq, p); p->sched_class->dequeue_task(rq, p, flags); + trace_sched_enq_deq_task(p, 0, cpumask_bits(&p->cpus_allowed)[0]); } void activate_task(struct rq *rq, struct task_struct *p, int flags) @@ -858,6 +887,9 @@ if (task_contributes_to_load(p)) rq->nr_uninterruptible++; + if (flags & DEQUEUE_SLEEP) + clear_ed_task(p, rq); + dequeue_task(rq, p, flags); } @@ -1073,17 +1105,19 @@ { lockdep_assert_held(&rq->lock); - dequeue_task(rq, p, 0); p->on_rq = TASK_ON_RQ_MIGRATING; + dequeue_task(rq, p, 0); + double_lock_balance(rq, cpu_rq(new_cpu)); set_task_cpu(p, new_cpu); + double_unlock_balance(rq, cpu_rq(new_cpu)); raw_spin_unlock(&rq->lock); rq = cpu_rq(new_cpu); raw_spin_lock(&rq->lock); BUG_ON(task_cpu(p) != new_cpu); - p->on_rq = TASK_ON_RQ_QUEUED; enqueue_task(rq, p, 0); + p->on_rq = TASK_ON_RQ_QUEUED; check_preempt_curr(rq, p, 0); return rq; @@ -1105,6 +1139,8 @@ */ static struct rq *__migrate_task(struct rq *rq, struct task_struct *p, int dest_cpu) { + int src_cpu; + if (unlikely(!cpu_active(dest_cpu))) return rq; @@ -1112,6 +1148,7 @@ if (!cpumask_test_cpu(dest_cpu, tsk_cpus_allowed(p))) return rq; + src_cpu = cpu_of(rq); rq = move_queued_task(rq, p, dest_cpu); return rq; @@ -1127,6 +1164,8 @@ struct migration_arg *arg = data; struct task_struct *p = arg->task; struct rq *rq = this_rq(); + int src_cpu = cpu_of(rq); + bool moved = false; /* * The original target cpu might have gone down and we might @@ -1147,12 +1186,18 @@ * holding rq->lock, if p->on_rq == 0 it cannot get enqueued because * we're holding p->pi_lock. */ - if (task_rq(p) == rq && task_on_rq_queued(p)) + if (task_rq(p) == rq && task_on_rq_queued(p)) { rq = __migrate_task(rq, p, arg->dest_cpu); + moved = true; + } raw_spin_unlock(&rq->lock); raw_spin_unlock(&p->pi_lock); local_irq_enable(); + + if (moved) + notify_migration(src_cpu, arg->dest_cpu, false, p); + return 0; } @@ -1211,6 +1256,7 @@ struct rq *rq; unsigned int dest_cpu; int ret = 0; + cpumask_t allowed_mask; rq = task_rq_lock(p, &flags); @@ -1226,18 +1272,25 @@ if (cpumask_equal(&p->cpus_allowed, new_mask)) goto out; - if (!cpumask_intersects(new_mask, cpu_active_mask)) { + cpumask_andnot(&allowed_mask, new_mask, cpu_isolated_mask); + cpumask_and(&allowed_mask, &allowed_mask, cpu_active_mask); + + dest_cpu = cpumask_any(&allowed_mask); + if (dest_cpu >= nr_cpu_ids) { + cpumask_and(&allowed_mask, cpu_active_mask, new_mask); + dest_cpu = cpumask_any(&allowed_mask); + if (dest_cpu >= nr_cpu_ids) { ret = -EINVAL; goto out; } + } do_set_cpus_allowed(p, new_mask); /* Can the task run on the task's current CPU? If so, we're done */ - if (cpumask_test_cpu(task_cpu(p), new_mask)) + if (cpumask_test_cpu(task_cpu(p), &allowed_mask)) goto out; - dest_cpu = cpumask_any_and(cpu_active_mask, new_mask); if (task_running(rq, p) || p->state == TASK_WAKING) { struct migration_arg arg = { p, dest_cpu }; /* Need help from migration thread: drop lock and wait. */ @@ -1276,6 +1329,15 @@ WARN_ON_ONCE(p->state != TASK_RUNNING && p->state != TASK_WAKING && !p->on_rq); + /* + * Migrating fair class task must have p->on_rq = TASK_ON_RQ_MIGRATING, + * because schedstat_wait_{start,end} rebase migrating task's wait_start + * time relying on p->on_rq. + */ + WARN_ON_ONCE(p->state == TASK_RUNNING && + p->sched_class == &fair_sched_class && + (p->on_rq && !task_on_rq_migrating(p))); + #ifdef CONFIG_LOCKDEP /* * The caller should hold either p->pi_lock or rq->lock, when changing @@ -1292,13 +1354,15 @@ #endif #endif - trace_sched_migrate_task(p, new_cpu); + trace_sched_migrate_task(p, new_cpu, pct_task_load(p)); if (task_cpu(p) != new_cpu) { if (p->sched_class->migrate_task_rq) p->sched_class->migrate_task_rq(p); p->se.nr_migrations++; perf_event_task_migrate(p); + + fixup_busy_time(p, new_cpu); } __set_task_cpu(p, new_cpu); @@ -1312,9 +1376,13 @@ src_rq = task_rq(p); dst_rq = cpu_rq(cpu); + p->on_rq = TASK_ON_RQ_MIGRATING; deactivate_task(src_rq, p, 0); + p->on_rq = TASK_ON_RQ_MIGRATING; set_task_cpu(p, cpu); + p->on_rq = TASK_ON_RQ_QUEUED; activate_task(dst_rq, p, 0); + p->on_rq = TASK_ON_RQ_QUEUED; check_preempt_curr(dst_rq, p, 0); } else { /* @@ -1500,7 +1568,7 @@ * yield - it could be a while. */ if (unlikely(queued)) { - ktime_t to = ktime_set(0, NSEC_PER_SEC/HZ); + ktime_t to = ktime_set(0, NSEC_PER_MSEC); set_current_state(TASK_UNINTERRUPTIBLE); schedule_hrtimeout(&to, HRTIMER_MODE_REL); @@ -1546,12 +1614,13 @@ /* * ->cpus_allowed is protected by both rq->lock and p->pi_lock */ -static int select_fallback_rq(int cpu, struct task_struct *p) +static int select_fallback_rq(int cpu, struct task_struct *p, bool allow_iso) { int nid = cpu_to_node(cpu); const struct cpumask *nodemask = NULL; - enum { cpuset, possible, fail } state = cpuset; + enum { cpuset, possible, fail, bug } state = cpuset; int dest_cpu; + int isolated_candidate = -1; /* * If the node that the cpu is on has been offlined, cpu_to_node() @@ -1567,6 +1636,8 @@ continue; if (!cpu_active(dest_cpu)) continue; + if (cpu_isolated(dest_cpu)) + continue; if (cpumask_test_cpu(dest_cpu, tsk_cpus_allowed(p))) return dest_cpu; } @@ -1579,6 +1650,16 @@ continue; if (!cpu_active(dest_cpu)) continue; + if (cpu_isolated(dest_cpu)) { + if (allow_iso) + isolated_candidate = dest_cpu; + continue; + } + goto out; + } + + if (isolated_candidate != -1) { + dest_cpu = isolated_candidate; goto out; } @@ -1597,6 +1678,11 @@ break; case fail: + allow_iso = true; + state = bug; + break; + + case bug: BUG(); break; } @@ -1622,12 +1708,16 @@ * The caller (fork, wakeup) owns p->pi_lock, ->cpus_allowed is stable. */ static inline -int select_task_rq(struct task_struct *p, int cpu, int sd_flags, int wake_flags) +int select_task_rq(struct task_struct *p, int cpu, int sd_flags, int wake_flags, + int sibling_count_hint) { + bool allow_isolated = (p->flags & PF_KTHREAD); + lockdep_assert_held(&p->pi_lock); if (p->nr_cpus_allowed > 1) - cpu = p->sched_class->select_task_rq(p, cpu, sd_flags, wake_flags); + cpu = p->sched_class->select_task_rq(p, cpu, sd_flags, wake_flags, + sibling_count_hint); /* * In order not to call set_task_cpu() on a blocking task we need @@ -1640,13 +1730,14 @@ * not worry about this generic constraint ] */ if (unlikely(!cpumask_test_cpu(cpu, tsk_cpus_allowed(p)) || - !cpu_online(cpu))) - cpu = select_fallback_rq(task_cpu(p), p); + !cpu_online(cpu)) || + (cpu_isolated(cpu) && !allow_isolated)) + cpu = select_fallback_rq(task_cpu(p), p, allow_isolated); return cpu; } -static void update_avg(u64 *avg, u64 sample) +void update_avg(u64 *avg, u64 sample) { s64 diff = sample - *avg; *avg += diff >> 3; @@ -1719,6 +1810,7 @@ ttwu_do_wakeup(struct rq *rq, struct task_struct *p, int wake_flags) { check_preempt_curr(rq, p, wake_flags); + p->state = TASK_RUNNING; trace_sched_wakeup(p); @@ -1810,6 +1902,8 @@ void scheduler_ipi(void) { + int cpu = smp_processor_id(); + /* * Fold TIF_NEED_RESCHED into the preempt_count; anybody setting * TIF_NEED_RESCHED remotely (for the first time) will also send @@ -1817,9 +1911,18 @@ */ preempt_fold_need_resched(); - if (llist_empty(&this_rq()->wake_list) && !got_nohz_idle_kick()) + if (llist_empty(&this_rq()->wake_list) && !got_nohz_idle_kick() && + !got_boost_kick()) return; + if (got_boost_kick()) { + struct rq *rq = cpu_rq(cpu); + + if (rq->curr->sched_class == &fair_sched_class) + check_for_migration(rq, rq->curr); + clear_boost_kick(cpu); + } + /* * Not all reschedule IPI handlers call irq_enter/irq_exit, since * traditionally all their work was done from the interrupt return @@ -1839,7 +1942,7 @@ /* * Check if someone kicked us for doing the nohz idle load balance. */ - if (unlikely(got_nohz_idle_kick())) { + if (unlikely(got_nohz_idle_kick()) && !cpu_isolated(cpu)) { this_rq()->idle_balance = 1; raise_softirq_irqoff(SCHED_SOFTIRQ); } @@ -1912,6 +2015,8 @@ * @p: the thread to be awakened * @state: the mask of task states that can be woken * @wake_flags: wake modifier flags (WF_*) + * @sibling_count_hint: A hint at the number of threads that are being woken up + * in this event. * * Put it on the run-queue if it's not already there. The "current" * thread is always on the run-queue (except when the actual @@ -1923,10 +2028,21 @@ * or @state didn't match @p's state. */ static int -try_to_wake_up(struct task_struct *p, unsigned int state, int wake_flags) +try_to_wake_up(struct task_struct *p, unsigned int state, int wake_flags, + int sibling_count_hint) { unsigned long flags; - int cpu, success = 0; + int cpu, src_cpu, success = 0; +#ifdef CONFIG_SMP + unsigned int old_load; + struct rq *rq; + u64 wallclock; + struct related_thread_group *grp = NULL; +#endif + bool freq_notif_allowed = !(wake_flags & WF_NO_NOTIFIER); + bool check_group = false; + + wake_flags &= ~WF_NO_NOTIFIER; /* * If we are going to wake up a thread waiting for CONDITION we @@ -1936,13 +2052,14 @@ */ smp_mb__before_spinlock(); raw_spin_lock_irqsave(&p->pi_lock, flags); + src_cpu = cpu = task_cpu(p); + if (!(p->state & state)) goto out; trace_sched_waking(p); success = 1; /* we're going to change ->state */ - cpu = task_cpu(p); /* * Ensure we load p->on_rq _after_ p->state, otherwise it would @@ -2006,25 +2123,57 @@ */ smp_rmb(); + rq = cpu_rq(task_cpu(p)); + + raw_spin_lock(&rq->lock); + old_load = task_load(p); + wallclock = sched_ktime_clock(); + update_task_ravg(rq->curr, rq, TASK_UPDATE, wallclock, 0); + update_task_ravg(p, rq, TASK_WAKE, wallclock, 0); + raw_spin_unlock(&rq->lock); + + rcu_read_lock(); + grp = task_related_thread_group(p); + if (update_preferred_cluster(grp, p, old_load)) + set_preferred_cluster(grp); + rcu_read_unlock(); + check_group = grp != NULL; + p->sched_contributes_to_load = !!task_contributes_to_load(p); p->state = TASK_WAKING; if (p->sched_class->task_waking) p->sched_class->task_waking(p); - cpu = select_task_rq(p, p->wake_cpu, SD_BALANCE_WAKE, wake_flags); - if (task_cpu(p) != cpu) { + cpu = select_task_rq(p, p->wake_cpu, SD_BALANCE_WAKE, wake_flags, + sibling_count_hint); + + /* Refresh src_cpu as it could have changed since we last read it */ + src_cpu = task_cpu(p); + if (src_cpu != cpu) { wake_flags |= WF_MIGRATED; set_task_cpu(p, cpu); } -#endif /* CONFIG_SMP */ + note_task_waking(p, wallclock); +#endif /* CONFIG_SMP */ ttwu_queue(p, cpu); stat: ttwu_stat(p, cpu, wake_flags); out: raw_spin_unlock_irqrestore(&p->pi_lock, flags); + if (freq_notif_allowed) { + if (!same_freq_domain(src_cpu, cpu)) { + check_for_freq_change(cpu_rq(cpu), + false, check_group); + check_for_freq_change(cpu_rq(src_cpu), + false, check_group); + } else if (success) { + check_for_freq_change(cpu_rq(cpu), true, false); + } + } + return success; } @@ -2040,9 +2189,13 @@ { struct rq *rq = task_rq(p); - if (WARN_ON_ONCE(rq != this_rq()) || - WARN_ON_ONCE(p == current)) + if (rq != this_rq() || p == current) { + printk_deferred("%s: Failed to wakeup task %d (%s), rq = %p," + " this_rq = %p, p = %p, current = %p\n", + __func__, task_pid_nr(p), p->comm, rq, + this_rq(), p, current); return; + } lockdep_assert_held(&rq->lock); @@ -2065,13 +2218,20 @@ trace_sched_waking(p); - if (!task_on_rq_queued(p)) + if (!task_on_rq_queued(p)) { + u64 wallclock = sched_ktime_clock(); + + update_task_ravg(rq->curr, rq, TASK_UPDATE, wallclock, 0); + update_task_ravg(p, rq, TASK_WAKE, wallclock, 0); ttwu_activate(rq, p, ENQUEUE_WAKEUP); + note_task_waking(p, wallclock); + } ttwu_do_wakeup(rq, p, 0); ttwu_stat(p, smp_processor_id(), 0); out: raw_spin_unlock(&p->pi_lock); + /* Todo : Send cpufreq notifier */ } /** @@ -2088,13 +2248,33 @@ */ int wake_up_process(struct task_struct *p) { - return try_to_wake_up(p, TASK_NORMAL, 0); + return try_to_wake_up(p, TASK_NORMAL, 0, 1); } EXPORT_SYMBOL(wake_up_process); +/** + * wake_up_process_no_notif - Wake up a specific process without notifying + * governor + * @p: The process to be woken up. + * + * Attempt to wake up the nominated process and move it to the set of runnable + * processes. + * + * Return: 1 if the process was woken up, 0 if it was already running. + * + * It may be assumed that this function implies a write memory barrier before + * changing the task state if and only if any tasks are woken up. + */ +int wake_up_process_no_notif(struct task_struct *p) +{ + WARN_ON(task_is_stopped_or_traced(p)); + return try_to_wake_up(p, TASK_NORMAL, WF_NO_NOTIFIER, 1); +} +EXPORT_SYMBOL(wake_up_process_no_notif); + int wake_up_state(struct task_struct *p, unsigned int state) { - return try_to_wake_up(p, state, 0); + return try_to_wake_up(p, state, 0, 1); } /* @@ -2116,6 +2296,44 @@ dl_se->dl_yielded = 0; } +#ifdef CONFIG_SCHED_HMP +/* + * sched_exit() - Set EXITING_TASK_MARKER in task's ravg.demand field + * + * Stop accounting (exiting) task's future cpu usage + * + * We need this so that reset_all_windows_stats() can function correctly. + * reset_all_window_stats() depends on do_each_thread/for_each_thread task + * iterators to reset *all* task's statistics. Exiting tasks however become + * invisible to those iterators. sched_exit() is called on a exiting task prior + * to being removed from task_list, which will let reset_all_window_stats() + * function correctly. + */ +void sched_exit(struct task_struct *p) +{ + unsigned long flags; + struct rq *rq; + u64 wallclock; + + sched_set_group_id(p, 0); + + rq = task_rq_lock(p, &flags); + + /* rq->curr == p */ + wallclock = sched_ktime_clock(); + update_task_ravg(rq->curr, rq, TASK_UPDATE, wallclock, 0); + dequeue_task(rq, p, 0); + reset_task_stats(p); + p->ravg.mark_start = wallclock; + p->ravg.sum_history[0] = EXITING_TASK_MARKER; + + enqueue_task(rq, p, 0); + clear_ed_task(p, rq); + task_rq_unlock(rq, p, &flags); + free_task_load_ptrs(p); +} +#endif /* CONFIG_SCHED_HMP */ + /* * Perform scheduler related setup for a newly forked process p. * p is forked by current. @@ -2132,8 +2350,16 @@ p->se.prev_sum_exec_runtime = 0; p->se.nr_migrations = 0; p->se.vruntime = 0; +#ifdef CONFIG_SCHED_WALT + p->last_sleep_ts = 0; +#endif + INIT_LIST_HEAD(&p->se.group_node); +#ifdef CONFIG_FAIR_GROUP_SCHED + p->se.cfs_rq = NULL; +#endif + #ifdef CONFIG_SCHEDSTATS memset(&p->se.statistics, 0, sizeof(p->se.statistics)); #endif @@ -2142,7 +2368,12 @@ init_dl_task_timer(&p->dl); __dl_clear_params(p); + init_rt_schedtune_timer(&p->rt); INIT_LIST_HEAD(&p->rt.run_list); + p->rt.timeout = 0; + p->rt.time_slice = sched_rr_timeslice; + p->rt.on_rq = 0; + p->rt.on_list = 0; #ifdef CONFIG_PREEMPT_NOTIFIERS INIT_HLIST_HEAD(&p->preempt_notifiers); @@ -2212,15 +2443,18 @@ int sched_fork(unsigned long clone_flags, struct task_struct *p) { unsigned long flags; - int cpu = get_cpu(); + int cpu; + + init_new_task_load(p, false); + cpu = get_cpu(); __sched_fork(clone_flags, p); /* - * We mark the process as running here. This guarantees that + * We mark the process as NEW here. This guarantees that * nobody will actually run it, and a signal or other external * event cannot wake it up and insert it on the runqueue either. */ - p->state = TASK_RUNNING; + p->state = TASK_NEW; /* * Make sure we do not leak PI boosting priority to the child. @@ -2257,8 +2491,7 @@ p->sched_class = &fair_sched_class; } - if (p->sched_class->task_fork) - p->sched_class->task_fork(p); + init_entity_runnable_average(&p->se); /* * The child is not yet in the pid-hash so no cgroup attach races, @@ -2268,7 +2501,13 @@ * Silence PROVE_RCU. */ raw_spin_lock_irqsave(&p->pi_lock, flags); - set_task_cpu(p, cpu); + /* + * We're setting the cpu for the first time, we don't migrate, + * so use __set_task_cpu(). + */ + __set_task_cpu(p, cpu); + if (p->sched_class->task_fork) + p->sched_class->task_fork(p); raw_spin_unlock_irqrestore(&p->pi_lock, flags); #ifdef CONFIG_SCHED_INFO @@ -2399,7 +2638,10 @@ unsigned long flags; struct rq *rq; + add_new_task_to_grp(p); raw_spin_lock_irqsave(&p->pi_lock, flags); + p->state = TASK_RUNNING; + /* Initialize new task's runnable average */ init_entity_runnable_average(&p->se); #ifdef CONFIG_SMP @@ -2407,12 +2649,17 @@ * Fork balancing, do it here and not earlier because: * - cpus_allowed can change in the fork path * - any previously selected cpu might disappear through hotplug + * + * Use __set_task_cpu() to avoid calling sched_class::migrate_task_rq, + * as we're not fully set-up yet. */ - set_task_cpu(p, select_task_rq(p, task_cpu(p), SD_BALANCE_FORK, 0)); + __set_task_cpu(p, select_task_rq(p, task_cpu(p), SD_BALANCE_FORK, 0, 1)); #endif - rq = __task_rq_lock(p); - activate_task(rq, p, 0); + mark_task_starting(p); + update_rq_clock(rq); + post_init_entity_util_avg(&p->se); + activate_task(rq, p, ENQUEUE_WAKEUP_NEW); p->on_rq = TASK_ON_RQ_QUEUED; trace_sched_wakeup_new(p); check_preempt_curr(rq, p, WF_FORK); @@ -2539,6 +2786,14 @@ fire_sched_out_preempt_notifiers(prev, next); prepare_lock_switch(rq, next); prepare_arch_switch(next); + +#ifdef CONFIG_MSM_APP_SETTINGS + if (use_app_setting) + switch_app_setting_bit(prev, next); + + if (use_32bit_app_setting || use_32bit_app_setting_pro) + switch_32bit_app_setting_bit(prev, next); +#endif } /** @@ -2793,6 +3048,36 @@ return atomic_read(&this->nr_iowait); } +#ifdef CONFIG_CPU_QUIET +u64 nr_running_integral(unsigned int cpu) +{ + unsigned int seqcnt; + u64 integral; + struct rq *q; + + if (cpu >= nr_cpu_ids) + return 0; + + q = cpu_rq(cpu); + + /* + * Update average to avoid reading stalled value if there were + * no run-queue changes for a long time. On the other hand if + * the changes are happening right now, just read current value + * directly. + */ + + seqcnt = read_seqcount_begin(&q->ave_seqcnt); + integral = do_nr_running_integral(q); + if (read_seqcount_retry(&q->ave_seqcnt, seqcnt)) { + read_seqcount_begin(&q->ave_seqcnt); + integral = q->nr_running_integral; + } + + return integral; +} +#endif + void get_iowait_load(unsigned long *nr_waiters, unsigned long *load) { struct rq *rq = this_rq(); @@ -2800,7 +3085,7 @@ *load = rq->load.weight; } -#ifdef CONFIG_SMP +#if defined(CONFIG_SMP) /* * sched_exec - execve() is a valuable balancing opportunity, because at @@ -2810,18 +3095,23 @@ { struct task_struct *p = current; unsigned long flags; - int dest_cpu; + int dest_cpu, curr_cpu; + +#ifdef CONFIG_SCHED_HMP + return; +#endif raw_spin_lock_irqsave(&p->pi_lock, flags); - dest_cpu = p->sched_class->select_task_rq(p, task_cpu(p), SD_BALANCE_EXEC, 0); + curr_cpu = task_cpu(p); + dest_cpu = p->sched_class->select_task_rq(p, task_cpu(p), SD_BALANCE_EXEC, 0, 1); if (dest_cpu == smp_processor_id()) goto unlock; - if (likely(cpu_active(dest_cpu))) { + if (likely(cpu_active(dest_cpu) && likely(!cpu_isolated(dest_cpu)))) { struct migration_arg arg = { p, dest_cpu }; raw_spin_unlock_irqrestore(&p->pi_lock, flags); - stop_one_cpu(task_cpu(p), migration_cpu_stop, &arg); + stop_one_cpu(curr_cpu, migration_cpu_stop, &arg); return; } unlock: @@ -2888,16 +3178,29 @@ int cpu = smp_processor_id(); struct rq *rq = cpu_rq(cpu); struct task_struct *curr = rq->curr; + u64 wallclock; + bool early_notif; + u32 old_load; + struct related_thread_group *grp; sched_clock_tick(); raw_spin_lock(&rq->lock); + old_load = task_load(curr); + set_window_start(rq); update_rq_clock(rq); curr->sched_class->task_tick(rq, curr, 0); update_cpu_load_active(rq); calc_global_load_tick(rq); + wallclock = sched_ktime_clock(); + update_task_ravg(rq->curr, rq, TASK_UPDATE, wallclock, 0); + early_notif = early_detection_notify(rq, wallclock); raw_spin_unlock(&rq->lock); + if (early_notif) + atomic_notifier_call_chain(&load_alert_notifier_head, + 0, (void *)(long)cpu); + perf_event_task_tick(); #ifdef CONFIG_SMP @@ -2905,6 +3208,18 @@ trigger_load_balance(rq); #endif rq_last_tick_reset(rq); + + rcu_read_lock(); + grp = task_related_thread_group(curr); + if (update_preferred_cluster(grp, curr, old_load)) + set_preferred_cluster(grp); + rcu_read_unlock(); + + if (curr->sched_class == &fair_sched_class) + check_for_migration(rq, curr); + + if (cpu == tick_do_timer_cpu) + core_ctl_check(wallclock); } #ifdef CONFIG_NO_HZ_FULL @@ -3006,6 +3321,9 @@ */ static noinline void __schedule_bug(struct task_struct *prev) { + /* Save this before calling printk(), since that will clobber it */ + unsigned long preempt_disable_ip = get_preempt_disable_ip(current); + if (oops_in_progress) return; @@ -3016,12 +3334,14 @@ print_modules(); if (irqs_disabled()) print_irqtrace_events(prev); -#ifdef CONFIG_DEBUG_PREEMPT - if (in_atomic_preempt_off()) { + if (IS_ENABLED(CONFIG_DEBUG_PREEMPT) + && in_atomic_preempt_off()) { pr_err("Preemption disabled at:"); - print_ip_sym(current->preempt_disable_ip); + print_ip_sym(preempt_disable_ip); pr_cont("\n"); } +#ifdef CONFIG_PANIC_ON_SCHED_BUG + BUG(); #endif dump_stack(); add_taint(TAINT_WARN, LOCKDEP_STILL_OK); @@ -3132,10 +3452,10 @@ unsigned long *switch_count; struct rq *rq; int cpu; + u64 wallclock; cpu = smp_processor_id(); rq = cpu_rq(cpu); - rcu_note_context_switch(); prev = rq->curr; /* @@ -3154,13 +3474,16 @@ if (sched_feat(HRTICK)) hrtick_clear(rq); + local_irq_disable(); + rcu_note_context_switch(); + /* * Make sure that signal_pending_state()->signal_pending() below * can't be reordered with __set_current_state(TASK_INTERRUPTIBLE) * done by the caller to avoid the race with signal_wake_up(). */ smp_mb__before_spinlock(); - raw_spin_lock_irq(&rq->lock); + raw_spin_lock(&rq->lock); lockdep_pin_lock(&rq->lock); rq->clock_skip_update <<= 1; /* promote REQ to ACT */ @@ -3197,15 +3520,30 @@ clear_preempt_need_resched(); rq->clock_skip_update = 0; + BUG_ON(task_cpu(next) != cpu_of(rq)); + + wallclock = sched_ktime_clock(); if (likely(prev != next)) { + update_task_ravg(prev, rq, PUT_PREV_TASK, wallclock, 0); + update_task_ravg(next, rq, PICK_NEXT_TASK, wallclock, 0); + if (!is_idle_task(prev) && !prev->on_rq) + update_avg_burst(prev); + +#ifdef CONFIG_SCHED_WALT + if (!prev->on_rq) + prev->last_sleep_ts = wallclock; +#endif rq->nr_switches++; rq->curr = next; ++*switch_count; + set_task_last_switch_out(prev, wallclock); + trace_sched_switch(preempt, prev, next); rq = context_switch(rq, prev, next); /* unlocks the rq */ cpu = cpu_of(rq); } else { + update_task_ravg(prev, rq, TASK_UPDATE, wallclock, 0); lockdep_unpin_lock(&rq->lock); raw_spin_unlock_irq(&rq->lock); } @@ -3371,7 +3709,7 @@ int default_wake_function(wait_queue_t *curr, unsigned mode, int wake_flags, void *key) { - return try_to_wake_up(curr->private, mode, wake_flags); + return try_to_wake_up(curr->private, mode, wake_flags, 1); } EXPORT_SYMBOL(default_wake_function); @@ -3390,13 +3728,14 @@ */ void rt_mutex_setprio(struct task_struct *p, int prio) { - int oldprio, queued, running, enqueue_flag = ENQUEUE_RESTORE; + int oldprio, queued, running, queue_flag = DEQUEUE_SAVE | DEQUEUE_MOVE; struct rq *rq; const struct sched_class *prev_class; BUG_ON(prio > MAX_PRIO); rq = __task_rq_lock(p); + update_rq_clock(rq); /* * Idle task boosting is a nono in general. There is one @@ -3418,11 +3757,15 @@ trace_sched_pi_setprio(p, prio); oldprio = p->prio; + + if (oldprio == prio) + queue_flag &= ~DEQUEUE_MOVE; + prev_class = p->sched_class; queued = task_on_rq_queued(p); running = task_current(rq, p); if (queued) - dequeue_task(rq, p, DEQUEUE_SAVE); + dequeue_task(rq, p, queue_flag); if (running) put_prev_task(rq, p); @@ -3440,7 +3783,7 @@ if (!dl_prio(p->normal_prio) || (pi_task && dl_entity_preempt(&pi_task->dl, &p->dl))) { p->dl.dl_boosted = 1; - enqueue_flag |= ENQUEUE_REPLENISH; + queue_flag |= ENQUEUE_REPLENISH; } else p->dl.dl_boosted = 0; p->sched_class = &dl_sched_class; @@ -3448,7 +3791,7 @@ if (dl_prio(oldprio)) p->dl.dl_boosted = 0; if (oldprio < prio) - enqueue_flag |= ENQUEUE_HEAD; + queue_flag |= ENQUEUE_HEAD; p->sched_class = &rt_sched_class; } else { if (dl_prio(oldprio)) @@ -3463,7 +3806,7 @@ if (running) p->sched_class->set_curr_task(rq); if (queued) - enqueue_task(rq, p, enqueue_flag); + enqueue_task(rq, p, queue_flag); check_class_changed(rq, p, prev_class, oldprio); out_unlock: @@ -3488,6 +3831,8 @@ * the task might be in the middle of scheduling on another CPU. */ rq = task_rq_lock(p, &flags); + update_rq_clock(rq); + /* * The RT priorities are set via sched_setscheduler(), but we still * allow the 'normal' nice value to be set - but as expected @@ -3820,6 +4165,7 @@ const struct sched_class *prev_class; struct rq *rq; int reset_on_fork; + int queue_flags = DEQUEUE_SAVE | DEQUEUE_MOVE; /* may grab non-irq protected spin_locks */ BUG_ON(in_interrupt()); @@ -3915,6 +4261,7 @@ * runqueue lock must be held. */ rq = task_rq_lock(p, &flags); + update_rq_clock(rq); /* * Changing the policy of the stop threads its a very bad idea @@ -4002,17 +4349,14 @@ * itself. */ new_effective_prio = rt_mutex_get_effective_prio(p, newprio); - if (new_effective_prio == oldprio) { - __setscheduler_params(p, attr); - task_rq_unlock(rq, p, &flags); - return 0; - } + if (new_effective_prio == oldprio) + queue_flags &= ~DEQUEUE_MOVE; } queued = task_on_rq_queued(p); running = task_current(rq, p); if (queued) - dequeue_task(rq, p, DEQUEUE_SAVE); + dequeue_task(rq, p, queue_flags); if (running) put_prev_task(rq, p); @@ -4022,15 +4366,14 @@ if (running) p->sched_class->set_curr_task(rq); if (queued) { - int enqueue_flags = ENQUEUE_RESTORE; /* * We enqueue to tail when the priority of a task is * increased (user space view). */ - if (oldprio <= p->prio) - enqueue_flags |= ENQUEUE_HEAD; + if (oldprio < p->prio) + queue_flags |= ENQUEUE_HEAD; - enqueue_task(rq, p, enqueue_flags); + enqueue_task(rq, p, queue_flags); } check_class_changed(rq, p, prev_class, oldprio); @@ -4108,7 +4451,7 @@ { return _sched_setscheduler(p, policy, param, false); } -EXPORT_SYMBOL_GPL(sched_setscheduler_nocheck); +EXPORT_SYMBOL(sched_setscheduler_nocheck); static int do_sched_setscheduler(pid_t pid, int policy, struct sched_param __user *param) @@ -4428,6 +4771,8 @@ cpumask_var_t cpus_allowed, new_mask; struct task_struct *p; int retval; + int dest_cpu; + cpumask_t allowed_mask; rcu_read_lock(); @@ -4489,8 +4834,10 @@ } #endif again: + cpumask_andnot(&allowed_mask, new_mask, cpu_isolated_mask); + dest_cpu = cpumask_any_and(cpu_active_mask, &allowed_mask); + if (dest_cpu < nr_cpu_ids) { retval = __set_cpus_allowed_ptr(p, new_mask, true); - if (!retval) { cpuset_cpus_allowed(p, cpus_allowed); if (!cpumask_subset(new_mask, cpus_allowed)) { @@ -4503,6 +4850,10 @@ goto again; } } + } else { + retval = -EINVAL; + } + out_free_new_mask: free_cpumask_var(new_mask); out_free_cpus_allowed: @@ -4566,6 +4917,15 @@ raw_spin_lock_irqsave(&p->pi_lock, flags); cpumask_and(mask, &p->cpus_allowed, cpu_active_mask); + + /* + * The userspace tasks are forbidden to run on + * isolated CPUs. So exclude isolated CPUs from + * the getaffinity. + */ + if (!(p->flags & PF_KTHREAD)) + cpumask_andnot(mask, mask, cpu_isolated_mask); + raw_spin_unlock_irqrestore(&p->pi_lock, flags); out_unlock: @@ -4987,6 +5347,8 @@ sched_show_task(p); } + touch_all_softlockup_watchdogs(); + #ifdef CONFIG_SCHED_DEBUG sysrq_sched_debug_show(); #endif @@ -5007,22 +5369,29 @@ * init_idle - set up an idle thread for a given CPU * @idle: task in question * @cpu: cpu the idle task belongs to + * @cpu_up: differentiate between initial boot vs hotplug * * NOTE: this function does not set the idle thread's NEED_RESCHED * flag, to make booting more robust. */ -void init_idle(struct task_struct *idle, int cpu) +void init_idle(struct task_struct *idle, int cpu, bool cpu_up) { struct rq *rq = cpu_rq(cpu); unsigned long flags; + if (!cpu_up) + init_new_task_load(idle, true); + raw_spin_lock_irqsave(&idle->pi_lock, flags); raw_spin_lock(&rq->lock); __sched_fork(0, idle); + idle->state = TASK_RUNNING; idle->se.exec_start = sched_clock(); + kasan_unpoison_task_stack(idle); + #ifdef CONFIG_SMP /* * Its possible that init_idle() gets called multiple times on a task, @@ -5245,18 +5614,54 @@ }; /* - * Migrate all tasks from the rq, sleeping tasks will be migrated by - * try_to_wake_up()->select_task_rq(). + * Remove a task from the runqueue and pretend that it's migrating. This + * should prevent migrations for the detached task and disallow further + * changes to tsk_cpus_allowed. + */ +static void +detach_one_task(struct task_struct *p, struct rq *rq, struct list_head *tasks) +{ + lockdep_assert_held(&rq->lock); + + p->on_rq = TASK_ON_RQ_MIGRATING; + deactivate_task(rq, p, 0); + list_add(&p->se.group_node, tasks); +} + +static void attach_tasks(struct list_head *tasks, struct rq *rq) +{ + struct task_struct *p; + + lockdep_assert_held(&rq->lock); + + while (!list_empty(tasks)) { + p = list_first_entry(tasks, struct task_struct, se.group_node); + list_del_init(&p->se.group_node); + + BUG_ON(task_rq(p) != rq); + activate_task(rq, p, 0); + p->on_rq = TASK_ON_RQ_QUEUED; + } +} + +/* + * Migrate all tasks (not pinned if pinned argument say so) from the rq, + * sleeping tasks will be migrated by try_to_wake_up()->select_task_rq(). * * Called with rq->lock held even though we'er in stop_machine() and * there's no concurrency possible, we hold the required locks anyway * because of lock validation efforts. */ -static void migrate_tasks(struct rq *dead_rq) +static void migrate_tasks(struct rq *dead_rq, bool migrate_pinned_tasks) { struct rq *rq = dead_rq; struct task_struct *next, *stop = rq->stop; int dest_cpu; + unsigned int num_pinned_kthreads = 1; /* this thread */ + LIST_HEAD(tasks); + cpumask_t avail_cpus; + + cpumask_andnot(&avail_cpus, cpu_online_mask, cpu_isolated_mask); /* * Fudge the rq selection such that the below task selection loop @@ -5292,6 +5697,14 @@ BUG_ON(!next); next->sched_class->put_prev_task(rq, next); + if (!migrate_pinned_tasks && next->flags & PF_KTHREAD && + !cpumask_intersects(&avail_cpus, &next->cpus_allowed)) { + detach_one_task(next, rq, &tasks); + num_pinned_kthreads += 1; + lockdep_unpin_lock(&rq->lock); + continue; + } + /* * Rules for changing task_struct::cpus_allowed are holding * both pi_lock and rq->lock, such that holding either @@ -5310,26 +5723,271 @@ * Since we're inside stop-machine, _nothing_ should have * changed the task, WARN if weird stuff happened, because in * that case the above rq->lock drop is a fail too. + * However, during cpu isolation the load balancer might have + * interferred since we don't stop all CPUs. Ignore warning for + * this case. */ - if (WARN_ON(task_rq(next) != rq || !task_on_rq_queued(next))) { + if (task_rq(next) != rq || !task_on_rq_queued(next)) { + WARN_ON(migrate_pinned_tasks); raw_spin_unlock(&next->pi_lock); continue; } /* Find suitable destination for @next, with force if needed. */ - dest_cpu = select_fallback_rq(dead_rq->cpu, next); + dest_cpu = select_fallback_rq(dead_rq->cpu, next, false); rq = __migrate_task(rq, next, dest_cpu); if (rq != dead_rq) { + raw_spin_unlock(&next->pi_lock); raw_spin_unlock(&rq->lock); + notify_migration(dead_rq->cpu, dest_cpu, true, next); rq = dead_rq; + raw_spin_lock(&next->pi_lock); raw_spin_lock(&rq->lock); } raw_spin_unlock(&next->pi_lock); } rq->stop = stop; + + if (num_pinned_kthreads > 1) + attach_tasks(&tasks, rq); } + +static void set_rq_online(struct rq *rq); +static void set_rq_offline(struct rq *rq); + +int do_isolation_work_cpu_stop(void *data) +{ + unsigned int cpu = smp_processor_id(); + struct rq *rq = cpu_rq(cpu); + + watchdog_disable(cpu); + + irq_migrate_all_off_this_cpu(); + + local_irq_disable(); + + sched_ttwu_pending(); + + raw_spin_lock(&rq->lock); + + /* + * Temporarily mark the rq as offline. This will allow us to + * move tasks off the CPU. + */ + if (rq->rd) { + BUG_ON(!cpumask_test_cpu(cpu, rq->rd->span)); + set_rq_offline(rq); + } + + migrate_tasks(rq, false); + + if (rq->rd) + set_rq_online(rq); + raw_spin_unlock(&rq->lock); + + /* + * We might have been in tickless state. Clear NOHZ flags to avoid + * us being kicked for helping out with balancing + */ + nohz_balance_clear_nohz_mask(cpu); + + clear_hmp_request(cpu); + local_irq_enable(); + return 0; +} + +int do_unisolation_work_cpu_stop(void *data) +{ + watchdog_enable(smp_processor_id()); + return 0; +} + +static void init_sched_groups_capacity(int cpu, struct sched_domain *sd); + +static void sched_update_group_capacities(int cpu) +{ + struct sched_domain *sd; + + mutex_lock(&sched_domains_mutex); + rcu_read_lock(); + + for_each_domain(cpu, sd) { + int balance_cpu = group_balance_cpu(sd->groups); + + init_sched_groups_capacity(cpu, sd); + /* + * Need to ensure this is also called with balancing + * cpu. + */ + if (cpu != balance_cpu) + init_sched_groups_capacity(balance_cpu, sd); + } + + rcu_read_unlock(); + mutex_unlock(&sched_domains_mutex); +} + +static unsigned int cpu_isolation_vote[NR_CPUS]; + +int sched_isolate_count(const cpumask_t *mask, bool include_offline) +{ + cpumask_t count_mask = CPU_MASK_NONE; + + if (include_offline) { + cpumask_complement(&count_mask, cpu_online_mask); + cpumask_or(&count_mask, &count_mask, cpu_isolated_mask); + cpumask_and(&count_mask, &count_mask, mask); + } else { + cpumask_and(&count_mask, mask, cpu_isolated_mask); + } + + return cpumask_weight(&count_mask); +} + +/* + * 1) CPU is isolated and cpu is offlined: + * Unisolate the core. + * 2) CPU is not isolated and CPU is offlined: + * No action taken. + * 3) CPU is offline and request to isolate + * Request ignored. + * 4) CPU is offline and isolated: + * Not a possible state. + * 5) CPU is online and request to isolate + * Normal case: Isolate the CPU + * 6) CPU is not isolated and comes back online + * Nothing to do + * + * Note: The client calling sched_isolate_cpu() is repsonsible for ONLY + * calling sched_unisolate_cpu() on a CPU that the client previously isolated. + * Client is also responsible for unisolating when a core goes offline + * (after CPU is marked offline). + */ +int sched_isolate_cpu(int cpu) +{ + struct rq *rq = cpu_rq(cpu); + cpumask_t avail_cpus; + int ret_code = 0; + u64 start_time = 0; + + if (trace_sched_isolate_enabled()) + start_time = sched_clock(); + + cpu_maps_update_begin(); + + cpumask_andnot(&avail_cpus, cpu_online_mask, cpu_isolated_mask); + + /* We cannot isolate ALL cpus in the system */ + if (cpumask_weight(&avail_cpus) == 1) { + ret_code = -EINVAL; + goto out; + } + + if (!cpu_online(cpu)) { + ret_code = -EINVAL; + goto out; + } + + if (++cpu_isolation_vote[cpu] > 1) + goto out; + + /* + * There is a race between watchdog being enabled by hotplug and + * core isolation disabling the watchdog. When a CPU is hotplugged in + * and the hotplug lock has been released the watchdog thread might + * not have run yet to enable the watchdog. + * We have to wait for the watchdog to be enabled before proceeding. + */ + if (!watchdog_configured(cpu)) { + msleep(20); + if (!watchdog_configured(cpu)) { + --cpu_isolation_vote[cpu]; + ret_code = -EBUSY; + goto out; + } + } + + set_cpu_isolated(cpu, true); + cpumask_clear_cpu(cpu, &avail_cpus); + + /* Migrate timers */ + smp_call_function_any(&avail_cpus, hrtimer_quiesce_cpu, &cpu, 1); + smp_call_function_any(&avail_cpus, timer_quiesce_cpu, &cpu, 1); + + stop_cpus(cpumask_of(cpu), do_isolation_work_cpu_stop, 0); + + calc_load_migrate(rq); + update_max_interval(); + sched_update_group_capacities(cpu); + +out: + cpu_maps_update_done(); + trace_sched_isolate(cpu, cpumask_bits(cpu_isolated_mask)[0], + start_time, 1); + return ret_code; +} + +/* + * Note: The client calling sched_isolate_cpu() is repsonsible for ONLY + * calling sched_unisolate_cpu() on a CPU that the client previously isolated. + * Client is also responsible for unisolating when a core goes offline + * (after CPU is marked offline). + */ +int sched_unisolate_cpu_unlocked(int cpu) +{ + int ret_code = 0; + struct rq *rq = cpu_rq(cpu); + u64 start_time = 0; + + if (trace_sched_isolate_enabled()) + start_time = sched_clock(); + + if (!cpu_isolation_vote[cpu]) { + ret_code = -EINVAL; + goto out; + } + + if (--cpu_isolation_vote[cpu]) + goto out; + + if (cpu_online(cpu)) { + unsigned long flags; + + raw_spin_lock_irqsave(&rq->lock, flags); + rq->age_stamp = sched_clock_cpu(cpu); + raw_spin_unlock_irqrestore(&rq->lock, flags); + } + + set_cpu_isolated(cpu, false); + update_max_interval(); + sched_update_group_capacities(cpu); + + if (cpu_online(cpu)) { + stop_cpus(cpumask_of(cpu), do_unisolation_work_cpu_stop, 0); + + /* Kick CPU to immediately do load balancing */ + if (!test_and_set_bit(NOHZ_BALANCE_KICK, nohz_flags(cpu))) + smp_send_reschedule(cpu); + } + +out: + trace_sched_isolate(cpu, cpumask_bits(cpu_isolated_mask)[0], + start_time, 0); + return ret_code; +} + +int sched_unisolate_cpu(int cpu) +{ + int ret_code; + + cpu_maps_update_begin(); + ret_code = sched_unisolate_cpu_unlocked(cpu); + cpu_maps_update_done(); + return ret_code; +} + #endif /* CONFIG_HOTPLUG_CPU */ #if defined(CONFIG_SCHED_DEBUG) && defined(CONFIG_SYSCTL) @@ -5402,9 +6060,60 @@ } static struct ctl_table * +sd_alloc_ctl_energy_table(struct sched_group_energy *sge) +{ + struct ctl_table *table = sd_alloc_ctl_entry(5); + + if (table == NULL) + return NULL; + + set_table_entry(&table[0], "nr_idle_states", &sge->nr_idle_states, + sizeof(int), 0644, proc_dointvec_minmax, false); + set_table_entry(&table[1], "idle_states", &sge->idle_states[0].power, + sge->nr_idle_states*sizeof(struct idle_state), 0644, + proc_doulongvec_minmax, false); + set_table_entry(&table[2], "nr_cap_states", &sge->nr_cap_states, + sizeof(int), 0644, proc_dointvec_minmax, false); + set_table_entry(&table[3], "cap_states", &sge->cap_states[0].cap, + sge->nr_cap_states*sizeof(struct capacity_state), 0644, + proc_doulongvec_minmax, false); + + return table; +} + +static struct ctl_table * +sd_alloc_ctl_group_table(struct sched_group *sg) +{ + struct ctl_table *table = sd_alloc_ctl_entry(2); + + if (table == NULL) + return NULL; + + table->procname = kstrdup("energy", GFP_KERNEL); + table->mode = 0555; + table->child = sd_alloc_ctl_energy_table((struct sched_group_energy *)sg->sge); + + return table; +} + +static struct ctl_table * sd_alloc_ctl_domain_table(struct sched_domain *sd) { - struct ctl_table *table = sd_alloc_ctl_entry(14); + struct ctl_table *table; + unsigned int nr_entries = 14; + + int i = 0; + struct sched_group *sg = sd->groups; + + if (sg->sge) { + int nr_sgs = 0; + + do {} while (nr_sgs++, sg = sg->next, sg != sd->groups); + + nr_entries += nr_sgs; + } + + table = sd_alloc_ctl_entry(nr_entries); if (table == NULL) return NULL; @@ -5437,7 +6146,19 @@ sizeof(long), 0644, proc_doulongvec_minmax, false); set_table_entry(&table[12], "name", sd->name, CORENAME_MAX_SIZE, 0444, proc_dostring, false); - /* &table[13] is terminator */ + sg = sd->groups; + if (sg->sge) { + char buf[32]; + struct ctl_table *entry = &table[13]; + + do { + snprintf(buf, 32, "group%d", i); + entry->procname = kstrdup(buf, GFP_KERNEL); + entry->mode = 0555; + entry->child = sd_alloc_ctl_group_table(sg); + } while (entry++, i++, sg = sg->next, sg != sd->groups); + } + /* &table[nr_entries-1] is terminator */ return table; } @@ -5553,6 +6274,9 @@ switch (action & ~CPU_TASKS_FROZEN) { case CPU_UP_PREPARE: + raw_spin_lock_irqsave(&rq->lock, flags); + set_window_start(rq); + raw_spin_unlock_irqrestore(&rq->lock, flags); rq->calc_load_update = calc_load_update; break; @@ -5572,16 +6296,18 @@ sched_ttwu_pending(); /* Update our root-domain */ raw_spin_lock_irqsave(&rq->lock, flags); + if (rq->rd) { BUG_ON(!cpumask_test_cpu(cpu, rq->rd->span)); set_rq_offline(rq); } - migrate_tasks(rq); + migrate_tasks(rq, true); BUG_ON(rq->nr_running != 1); /* the migration thread */ raw_spin_unlock_irqrestore(&rq->lock, flags); break; case CPU_DEAD: + clear_hmp_request(cpu); calc_load_migrate(rq); break; #endif @@ -5699,9 +6425,6 @@ if (!(sd->flags & SD_LOAD_BALANCE)) { printk("does not load-balance\n"); - if (sd->parent) - printk(KERN_ERR "ERROR: !SD_LOAD_BALANCE domain" - " has parent"); return -1; } @@ -5743,7 +6466,7 @@ printk(KERN_CONT " %*pbl", cpumask_pr_args(sched_group_cpus(group))); if (group->sgc->capacity != SCHED_CAPACITY_SCALE) { - printk(KERN_CONT " (cpu_capacity = %d)", + printk(KERN_CONT " (cpu_capacity = %lu)", group->sgc->capacity); } @@ -5794,8 +6517,12 @@ static int sd_degenerate(struct sched_domain *sd) { - if (cpumask_weight(sched_domain_span(sd)) == 1) + if (cpumask_weight(sched_domain_span(sd)) == 1) { + if (sd->groups->sge) + sd->flags &= ~SD_LOAD_BALANCE; + else return 1; + } /* Following flags need at least 2 groups */ if (sd->flags & (SD_LOAD_BALANCE | @@ -5803,8 +6530,10 @@ SD_BALANCE_FORK | SD_BALANCE_EXEC | SD_SHARE_CPUCAPACITY | + SD_ASYM_CPUCAPACITY | SD_SHARE_PKG_RESOURCES | - SD_SHARE_POWERDOMAIN)) { + SD_SHARE_POWERDOMAIN | + SD_SHARE_CAP_STATES)) { if (sd->groups != sd->groups->next) return 0; } @@ -5833,10 +6562,16 @@ SD_BALANCE_NEWIDLE | SD_BALANCE_FORK | SD_BALANCE_EXEC | + SD_ASYM_CPUCAPACITY | SD_SHARE_CPUCAPACITY | SD_SHARE_PKG_RESOURCES | SD_PREFER_SIBLING | - SD_SHARE_POWERDOMAIN); + SD_SHARE_POWERDOMAIN | + SD_SHARE_CAP_STATES); + if (parent->groups->sge) { + parent->flags &= ~SD_LOAD_BALANCE; + return 0; + } if (nr_node_ids == 1) pflags &= ~SD_SERIALIZE; } @@ -5921,6 +6656,11 @@ if (cpupri_init(&rd->cpupri) != 0) goto free_rto_mask; + + init_max_cpu_capacity(&rd->max_cpu_capacity); + + rd->max_cap_orig_cpu = rd->min_cap_orig_cpu = -1; + return 0; free_rto_mask: @@ -6026,11 +6766,13 @@ DEFINE_PER_CPU(struct sched_domain *, sd_numa); DEFINE_PER_CPU(struct sched_domain *, sd_busy); DEFINE_PER_CPU(struct sched_domain *, sd_asym); +DEFINE_PER_CPU(struct sched_domain *, sd_ea); +DEFINE_PER_CPU(struct sched_domain *, sd_scs); static void update_top_cache_domain(int cpu) { struct sched_domain *sd; - struct sched_domain *busy_sd = NULL; + struct sched_domain *busy_sd = NULL, *ea_sd = NULL; int id = cpu; int size = 1; @@ -6051,6 +6793,17 @@ sd = highest_flag_domain(cpu, SD_ASYM_PACKING); rcu_assign_pointer(per_cpu(sd_asym, cpu), sd); + + for_each_domain(cpu, sd) { + if (sd->groups->sge) + ea_sd = sd; + else + break; + } + rcu_assign_pointer(per_cpu(sd_ea, cpu), ea_sd); + + sd = highest_flag_domain(cpu, SD_SHARE_CAP_STATES); + rcu_assign_pointer(per_cpu(sd_scs, cpu), sd); } /* @@ -6062,6 +6815,7 @@ { struct rq *rq = cpu_rq(cpu); struct sched_domain *tmp; + unsigned long next_balance = rq->next_balance; /* Remove the sched domains which do not contribute to scheduling. */ for (tmp = sd; tmp; ) { @@ -6093,6 +6847,17 @@ sd->child = NULL; } + for (tmp = sd; tmp; ) { + unsigned long interval; + + interval = msecs_to_jiffies(tmp->balance_interval); + if (time_after(next_balance, tmp->last_balance + interval)) + next_balance = tmp->last_balance + interval; + + tmp = tmp->parent; + } + rq->next_balance = next_balance; + sched_domain_debug(sd, cpu); rq_attach_root(rq, rd); @@ -6227,6 +6992,8 @@ * die on a /0 trap. */ sg->sgc->capacity = SCHED_CAPACITY_SCALE * cpumask_weight(sg_span); + sg->sgc->max_capacity = SCHED_CAPACITY_SCALE; + sg->sgc->min_capacity = SCHED_CAPACITY_SCALE; /* * Make sure the first group of this domain contains the @@ -6340,11 +7107,14 @@ static void init_sched_groups_capacity(int cpu, struct sched_domain *sd) { struct sched_group *sg = sd->groups; + cpumask_t avail_mask; WARN_ON(!sg); do { - sg->group_weight = cpumask_weight(sched_group_cpus(sg)); + cpumask_andnot(&avail_mask, sched_group_cpus(sg), + cpu_isolated_mask); + sg->group_weight = cpumask_weight(&avail_mask); sg = sg->next; } while (sg != sd->groups); @@ -6356,6 +7126,66 @@ } /* + * Check that the per-cpu provided sd energy data is consistent for all cpus + * within the mask. + */ +static inline void check_sched_energy_data(int cpu, sched_domain_energy_f fn, + const struct cpumask *cpumask) +{ + const struct sched_group_energy * const sge = fn(cpu); + struct cpumask mask; + int i; + + if (cpumask_weight(cpumask) <= 1) + return; + + cpumask_xor(&mask, cpumask, get_cpu_mask(cpu)); + + for_each_cpu(i, &mask) { + const struct sched_group_energy * const e = fn(i); + int y; + + BUG_ON(e->nr_idle_states != sge->nr_idle_states); + + for (y = 0; y < (e->nr_idle_states); y++) { + BUG_ON(e->idle_states[y].power != + sge->idle_states[y].power); + } + + BUG_ON(e->nr_cap_states != sge->nr_cap_states); + + for (y = 0; y < (e->nr_cap_states); y++) { + BUG_ON(e->cap_states[y].cap != sge->cap_states[y].cap); + BUG_ON(e->cap_states[y].power != + sge->cap_states[y].power); + } + } +} + +static void init_sched_energy(int cpu, struct sched_domain *sd, + sched_domain_energy_f fn) +{ + if (!(fn && fn(cpu))) + return; + + if (cpu != group_balance_cpu(sd->groups)) + return; + + if (sd->child && !sd->child->groups->sge) { + pr_err("BUG: EAS setup broken for CPU%d\n", cpu); +#ifdef CONFIG_SCHED_DEBUG + pr_err(" energy data on %s but not on %s domain\n", + sd->name, sd->child->name); +#endif + return; + } + + check_sched_energy_data(cpu, fn, sched_group_cpus(sd->groups)); + + sd->groups->sge = fn(cpu); +} + +/* * Initializers for schedule domains * Non-inlined to reduce accumulated stack pressure in build_sched_domains() */ @@ -6459,10 +7289,19 @@ /* * SD_flags allowed in topology descriptions. * + * These flags are purely descriptive of the topology and do not prescribe + * behaviour. Behaviour is artificial and mapped in the below sd_init() + * function: + * * SD_SHARE_CPUCAPACITY - describes SMT topologies * SD_SHARE_PKG_RESOURCES - describes shared caches * SD_NUMA - describes NUMA topologies * SD_SHARE_POWERDOMAIN - describes shared power domain + * SD_ASYM_CPUCAPACITY - describes mixed capacity topologies + * SD_SHARE_CAP_STATES - describes shared capacity states + * + * Odd one out, which beside describing the topology has a quirk also + * prescribes the desired behaviour that goes along with it: * * Odd one out: * SD_ASYM_PACKING - describes SMT quirks @@ -6472,10 +7311,13 @@ SD_SHARE_PKG_RESOURCES | \ SD_NUMA | \ SD_ASYM_PACKING | \ - SD_SHARE_POWERDOMAIN) + SD_ASYM_CPUCAPACITY | \ + SD_SHARE_POWERDOMAIN | \ + SD_SHARE_CAP_STATES) static struct sched_domain * -sd_init(struct sched_domain_topology_level *tl, int cpu) +sd_init(struct sched_domain_topology_level *tl, + struct sched_domain *child, int cpu) { struct sched_domain *sd = *per_cpu_ptr(tl->data.sd, cpu); int sd_weight, sd_flags = 0; @@ -6527,6 +7369,7 @@ .smt_gain = 0, .max_newidle_lb_cost = 0, .next_decay_max_lb_cost = jiffies, + .child = child, #ifdef CONFIG_SCHED_DEBUG .name = tl->name, #endif @@ -6536,6 +7379,13 @@ * Convert topological properties into behaviour. */ + if (sd->flags & SD_ASYM_CPUCAPACITY) { + struct sched_domain *t = sd; + + for_each_lower_domain(t) + t->flags |= SD_BALANCE_WAKE; + } + if (sd->flags & SD_SHARE_CPUCAPACITY) { sd->flags |= SD_PREFER_SIBLING; sd->imbalance_pct = 110; @@ -6982,16 +7832,13 @@ const struct cpumask *cpu_map, struct sched_domain_attr *attr, struct sched_domain *child, int cpu) { - struct sched_domain *sd = sd_init(tl, cpu); - if (!sd) - return child; + struct sched_domain *sd = sd_init(tl, child, cpu); cpumask_and(sched_domain_span(sd), cpu_map, tl->mask(cpu)); if (child) { sd->level = child->level + 1; sched_domain_level_max = max(sched_domain_level_max, sd->level); child->parent = sd; - sd->child = child; if (!cpumask_subset(sched_domain_span(child), sched_domain_span(sd))) { @@ -7000,6 +7847,9 @@ pr_err(" the %s domain not a subset of the %s domain\n", child->name, sd->name); #endif +#ifdef CONFIG_PANIC_ON_SCHED_BUG + BUG(); +#endif /* Fixup, ensure @sd has at least @child cpus. */ cpumask_or(sched_domain_span(sd), sched_domain_span(sd), @@ -7039,8 +7889,6 @@ *per_cpu_ptr(d.sd, i) = sd; if (tl->flags & SDTL_OVERLAP || sched_feat(FORCE_SD_OVERLAP)) sd->flags |= SD_OVERLAP; - if (cpumask_equal(cpu_map, sched_domain_span(sd))) - break; } } @@ -7060,10 +7908,14 @@ /* Calculate CPU capacity for physical packages and nodes */ for (i = nr_cpumask_bits-1; i >= 0; i--) { + struct sched_domain_topology_level *tl = sched_domain_topology; + if (!cpumask_test_cpu(i, cpu_map)) continue; - for (sd = *per_cpu_ptr(d.sd, i); sd; sd = sd->parent) { + for (sd = *per_cpu_ptr(d.sd, i); sd; sd = sd->parent, tl++) { + if (energy_aware()) + init_sched_energy(i, sd, tl->energy); claim_allocations(i, sd); init_sched_groups_capacity(i, sd); } @@ -7072,7 +7924,19 @@ /* Attach the domains */ rcu_read_lock(); for_each_cpu(i, cpu_map) { + int max_cpu = READ_ONCE(d.rd->max_cap_orig_cpu); + int min_cpu = READ_ONCE(d.rd->min_cap_orig_cpu); + + if ((max_cpu < 0) || (cpu_rq(i)->cpu_capacity_orig > + cpu_rq(max_cpu)->cpu_capacity_orig)) + WRITE_ONCE(d.rd->max_cap_orig_cpu, i); + + if ((min_cpu < 0) || (cpu_rq(i)->cpu_capacity_orig < + cpu_rq(min_cpu)->cpu_capacity_orig)) + WRITE_ONCE(d.rd->min_cap_orig_cpu, i); + sd = *per_cpu_ptr(d.sd, i); + cpu_attach_domain(sd, d.rd, i); } rcu_read_unlock(); @@ -7373,6 +8237,8 @@ hotcpu_notifier(cpuset_cpu_active, CPU_PRI_CPUSET_ACTIVE); hotcpu_notifier(cpuset_cpu_inactive, CPU_PRI_CPUSET_INACTIVE); + update_cluster_topology(); + init_hrtick(); /* Move init over to a non-isolated CPU */ @@ -7391,6 +8257,7 @@ } #endif /* CONFIG_SMP */ + int in_sched_functions(unsigned long addr) { return in_lock_functions(addr) || @@ -7414,6 +8281,15 @@ int i, j; unsigned long alloc_size = 0, ptr; +#ifdef CONFIG_SCHED_HMP + pr_info("HMP scheduling enabled.\n"); +#endif + + BUG_ON(num_possible_cpus() > BITS_PER_LONG); + + sched_boost_parse_dt(); + init_clusters(); + #ifdef CONFIG_FAIR_GROUP_SCHED alloc_size += 2 * nr_cpu_ids * sizeof(void **); #endif @@ -7483,6 +8359,7 @@ #ifdef CONFIG_FAIR_GROUP_SCHED root_task_group.shares = ROOT_TASK_GROUP_LOAD; INIT_LIST_HEAD(&rq->leaf_cfs_rq_list); + rq->tmp_alone_branch = &rq->leaf_cfs_rq_list; /* * How much cpu bandwidth does root_task_group get? * @@ -7524,10 +8401,57 @@ rq->active_balance = 0; rq->next_balance = jiffies; rq->push_cpu = 0; + rq->push_task = NULL; rq->cpu = i; rq->online = 0; rq->idle_stamp = 0; rq->avg_idle = 2*sysctl_sched_migration_cost; +#ifdef CONFIG_SCHED_HMP + cpumask_set_cpu(i, &rq->freq_domain_cpumask); + rq->hmp_stats.cumulative_runnable_avg = 0; + rq->window_start = 0; + rq->hmp_stats.nr_big_tasks = 0; + rq->hmp_flags = 0; + rq->cur_irqload = 0; + rq->avg_irqload = 0; + rq->irqload_ts = 0; + rq->static_cpu_pwr_cost = 0; + rq->cc.cycles = 1; + rq->cc.time = 1; + rq->cstate = 0; + rq->wakeup_latency = 0; + rq->wakeup_energy = 0; + + /* + * All cpus part of same cluster by default. This avoids the + * need to check for rq->cluster being non-NULL in hot-paths + * like select_best_cpu() + */ + rq->cluster = &init_cluster; + rq->curr_runnable_sum = rq->prev_runnable_sum = 0; + rq->nt_curr_runnable_sum = rq->nt_prev_runnable_sum = 0; + memset(&rq->grp_time, 0, sizeof(struct group_cpu_time)); + rq->old_busy_time = 0; + rq->old_estimated_time = 0; + rq->old_busy_time_group = 0; + rq->hmp_stats.pred_demands_sum = 0; + rq->curr_table = 0; + rq->prev_top = 0; + rq->curr_top = 0; + + for (j = 0; j < NUM_TRACKED_WINDOWS; j++) { + memset(&rq->load_subs[j], 0, + sizeof(struct load_subtractions)); + + rq->top_tasks[j] = kcalloc(NUM_LOAD_INDICES, + sizeof(u8), GFP_NOWAIT); + + /* No other choice */ + BUG_ON(!rq->top_tasks[j]); + + clear_top_tasks_bitmap(rq->top_tasks_bitmap[j]); + } +#endif rq->max_idle_balance_cost = sysctl_sched_migration_cost; INIT_LIST_HEAD(&rq->cfs_tasks); @@ -7544,6 +8468,11 @@ atomic_set(&rq->nr_iowait, 0); } + i = alloc_related_thread_groups(); + BUG_ON(i); + + set_hmp_defaults(); + set_load_weight(&init_task); #ifdef CONFIG_PREEMPT_NOTIFIERS @@ -7567,7 +8496,7 @@ * but because we are the idle thread, we just pick up running again * when this runqueue becomes "idle". */ - init_idle(current, smp_processor_id()); + init_idle(current, smp_processor_id(), false); calc_load_update = jiffies + LOAD_FREQ; @@ -7592,6 +8521,14 @@ return (nested == preempt_offset); } +static int __might_sleep_init_called; +int __init __might_sleep_init(void) +{ + __might_sleep_init_called = 1; + return 0; +} +early_initcall(__might_sleep_init); + void __might_sleep(const char *file, int line, int preempt_offset) { /* @@ -7613,16 +8550,22 @@ void ___might_sleep(const char *file, int line, int preempt_offset) { static unsigned long prev_jiffy; /* ratelimiting */ + unsigned long preempt_disable_ip; rcu_sleep_check(); /* WARN_ON_ONCE() by default, no rate limit reqd. */ if ((preempt_count_equals(preempt_offset) && !irqs_disabled() && - !is_idle_task(current)) || - system_state != SYSTEM_RUNNING || oops_in_progress) + !is_idle_task(current)) || oops_in_progress) + return; + if (system_state != SYSTEM_RUNNING && + (!__might_sleep_init_called || system_state != SYSTEM_BOOTING)) return; if (time_before(jiffies, prev_jiffy + HZ) && prev_jiffy) return; prev_jiffy = jiffies; + /* Save this before calling printk(), since that will clobber it */ + preempt_disable_ip = get_preempt_disable_ip(current); + printk(KERN_ERR "BUG: sleeping function called from invalid context at %s:%d\n", file, line); @@ -7637,12 +8580,14 @@ debug_show_held_locks(current); if (irqs_disabled()) print_irqtrace_events(current); -#ifdef CONFIG_DEBUG_PREEMPT - if (!preempt_count_equals(preempt_offset)) { + if (IS_ENABLED(CONFIG_DEBUG_PREEMPT) + && !preempt_count_equals(preempt_offset)) { pr_err("Preemption disabled at:"); - print_ip_sym(current->preempt_disable_ip); + print_ip_sym(preempt_disable_ip); pr_cont("\n"); } +#ifdef CONFIG_PANIC_ON_SCHED_BUG + BUG(); #endif dump_stack(); } @@ -7803,11 +8748,9 @@ void sched_offline_group(struct task_group *tg) { unsigned long flags; - int i; /* end participation in shares distribution */ - for_each_possible_cpu(i) - unregister_fair_sched_group(tg, i); + unregister_fair_sched_group(tg); spin_lock_irqsave(&task_group_lock, flags); list_del_rcu(&tg->list); @@ -7815,27 +8758,9 @@ spin_unlock_irqrestore(&task_group_lock, flags); } -/* change task's runqueue when it moves between groups. - * The caller of this function should have put the task in its new group - * by now. This function just updates tsk->se.cfs_rq and tsk->se.parent to - * reflect its new group. - */ -void sched_move_task(struct task_struct *tsk) +static void sched_change_group(struct task_struct *tsk, int type) { struct task_group *tg; - int queued, running; - unsigned long flags; - struct rq *rq; - - rq = task_rq_lock(tsk, &flags); - - running = task_current(rq, tsk); - queued = task_on_rq_queued(tsk); - - if (queued) - dequeue_task(rq, tsk, DEQUEUE_SAVE); - if (unlikely(running)) - put_prev_task(rq, tsk); /* * All callers are synchronized by task_rq_lock(); we do not use RCU @@ -7848,16 +8773,42 @@ tsk->sched_task_group = tg; #ifdef CONFIG_FAIR_GROUP_SCHED - if (tsk->sched_class->task_move_group) - tsk->sched_class->task_move_group(tsk); + if (tsk->sched_class->task_change_group) + tsk->sched_class->task_change_group(tsk, type); else #endif set_task_rq(tsk, task_cpu(tsk)); +} + +/* + * Change task's runqueue when it moves between groups. + * + * The caller of this function should have put the task in its new group by + * now. This function just updates tsk->se.cfs_rq and tsk->se.parent to reflect + * its new group. + */ +void sched_move_task(struct task_struct *tsk) +{ + int queued, running; + unsigned long flags; + struct rq *rq; + + rq = task_rq_lock(tsk, &flags); + + running = task_current(rq, tsk); + queued = task_on_rq_queued(tsk); + + if (queued) + dequeue_task(rq, tsk, DEQUEUE_SAVE | DEQUEUE_MOVE); + if (unlikely(running)) + put_prev_task(rq, tsk); + + sched_change_group(tsk, TASK_MOVE_GROUP); if (unlikely(running)) tsk->sched_class->set_curr_task(rq); if (queued) - enqueue_task(rq, tsk, ENQUEUE_RESTORE); + enqueue_task(rq, tsk, ENQUEUE_RESTORE | ENQUEUE_MOVE); task_rq_unlock(rq, tsk, &flags); } @@ -8238,7 +9189,7 @@ #ifdef CONFIG_CGROUP_SCHED -static inline struct task_group *css_tg(struct cgroup_subsys_state *css) +inline struct task_group *css_tg(struct cgroup_subsys_state *css) { return css ? container_of(css, struct task_group, css) : NULL; } @@ -8289,15 +9240,28 @@ sched_free_group(tg); } +/* + * This is called before wake_up_new_task(), therefore we really only + * have to set its group bits, all the other stuff does not apply. + */ static void cpu_cgroup_fork(struct task_struct *task, void *private) { - sched_move_task(task); + unsigned long flags; + struct rq *rq; + + rq = task_rq_lock(task, &flags); + + update_rq_clock(rq); + sched_change_group(task, TASK_SET_GROUP); + + task_rq_unlock(rq, task, &flags); } static int cpu_cgroup_can_attach(struct cgroup_taskset *tset) { struct task_struct *task; struct cgroup_subsys_state *css; + int ret = 0; cgroup_taskset_for_each(task, css, tset) { #ifdef CONFIG_RT_GROUP_SCHED @@ -8308,8 +9272,24 @@ if (task->sched_class != &fair_sched_class) return -EINVAL; #endif + /* + * Serialize against wake_up_new_task() such that if its + * running, we're sure to observe its full state. + */ + raw_spin_lock_irq(&task->pi_lock); + /* + * Avoid calling sched_move_task() before wake_up_new_task() + * has happened. This would lead to problems with PELT, due to + * move wanting to detach+attach while we're not attached yet. + */ + if (task->state == TASK_NEW) + ret = -EINVAL; + raw_spin_unlock_irq(&task->pi_lock); + + if (ret) + break; } - return 0; + return ret; } static void cpu_cgroup_attach(struct cgroup_taskset *tset) @@ -8606,6 +9586,13 @@ #endif /* CONFIG_RT_GROUP_SCHED */ static struct cftype cpu_files[] = { +#ifdef CONFIG_SCHED_HMP + { + .name = "upmigrate_discourage", + .read_u64 = cpu_upmigrate_discourage_read_u64, + .write_u64 = cpu_upmigrate_discourage_write_u64, + }, +#endif #ifdef CONFIG_FAIR_GROUP_SCHED { .name = "shares", diff -ruw linux-4.4.115/kernel/sched/cpupri.c linux-4.4.115-fbx/kernel/sched/cpupri.c --- linux-4.4.115/kernel/sched/cpupri.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/kernel/sched/cpupri.c 2019-01-22 16:16:28.695293423 +0100 @@ -27,6 +27,8 @@ * of the License. */ +#include "sched.h" + #include #include #include @@ -51,6 +53,27 @@ } /** + * drop_nopreempt_cpus - remove a cpu from the mask if it is likely + * non-preemptible + * @lowest_mask: mask with selected CPUs (non-NULL) + */ +static void +drop_nopreempt_cpus(struct cpumask *lowest_mask) +{ + unsigned int cpu = cpumask_first(lowest_mask); + + while (cpu < nr_cpu_ids) { + /* unlocked access */ + struct task_struct *task = READ_ONCE(cpu_rq(cpu)->curr); + + if (task_may_not_preempt(task, cpu)) + cpumask_clear_cpu(cpu, lowest_mask); + + cpu = cpumask_next(cpu, lowest_mask); + } +} + +/** * cpupri_find - find the best (lowest-pri) CPU in the system * @cp: The cpupri context * @p: The task @@ -70,9 +93,11 @@ { int idx = 0; int task_pri = convert_prio(p->prio); + bool drop_nopreempts = task_pri <= MAX_RT_PRIO; BUG_ON(task_pri >= CPUPRI_NR_PRIORITIES); +retry: for (idx = 0; idx < task_pri; idx++) { struct cpupri_vec *vec = &cp->pri_to_cpu[idx]; int skip = 0; @@ -108,7 +133,8 @@ if (lowest_mask) { cpumask_and(lowest_mask, &p->cpus_allowed, vec->mask); - + if (drop_nopreempts) + drop_nopreempt_cpus(lowest_mask); /* * We have to ensure that we have at least one bit * still set in the array, since the map could have @@ -123,7 +149,14 @@ return 1; } - + /* + * If we can't find any non-preemptible cpu's, retry so we can + * find the lowest priority target and avoid priority inversion. + */ + if (drop_nopreempts) { + drop_nopreempts = false; + goto retry; + } return 0; } @@ -246,3 +279,14 @@ for (i = 0; i < CPUPRI_NR_PRIORITIES; i++) free_cpumask_var(cp->pri_to_cpu[i].mask); } + +/* + * cpupri_check_rt - check if CPU has a RT task + * should be called from rcu-sched read section. + */ +bool cpupri_check_rt(void) +{ + int cpu = raw_smp_processor_id(); + + return cpu_rq(cpu)->rd->cpupri.cpu_to_pri[cpu] > CPUPRI_NORMAL; +} diff -ruw linux-4.4.115/kernel/sched/cputime.c linux-4.4.115-fbx/kernel/sched/cputime.c --- linux-4.4.115/kernel/sched/cputime.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/kernel/sched/cputime.c 2019-10-29 09:26:25.617222496 +0100 @@ -49,6 +49,8 @@ unsigned long flags; s64 delta; int cpu; + u64 wallclock; + bool account = true; if (!sched_clock_irqtime) return; @@ -56,7 +58,8 @@ local_irq_save(flags); cpu = smp_processor_id(); - delta = sched_clock_cpu(cpu) - __this_cpu_read(irq_start_time); + wallclock = sched_clock_cpu(cpu); + delta = wallclock - __this_cpu_read(irq_start_time); __this_cpu_add(irq_start_time, delta); irq_time_write_begin(); @@ -70,8 +73,16 @@ __this_cpu_add(cpu_hardirq_time, delta); else if (in_serving_softirq() && curr != this_cpu_ksoftirqd()) __this_cpu_add(cpu_softirq_time, delta); + else + account = false; irq_time_write_end(); + + if (account) + sched_account_irqtime(cpu, curr, delta, wallclock); + else if (curr != this_cpu_ksoftirqd()) + sched_account_irqstart(cpu, curr, wallclock); + local_irq_restore(flags); } EXPORT_SYMBOL_GPL(irqtime_account_irq); diff -ruw linux-4.4.115/kernel/sched/deadline.c linux-4.4.115-fbx/kernel/sched/deadline.c --- linux-4.4.115/kernel/sched/deadline.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/kernel/sched/deadline.c 2019-01-22 16:16:28.695293423 +0100 @@ -18,6 +18,8 @@ #include +#include "walt.h" + struct dl_bandwidth def_dl_bandwidth; static inline struct task_struct *dl_task_of(struct sched_dl_entity *dl_se) @@ -43,6 +45,24 @@ return !RB_EMPTY_NODE(&dl_se->rb_node); } +static void add_average_bw(struct sched_dl_entity *dl_se, struct dl_rq *dl_rq) +{ + u64 se_bw = dl_se->dl_bw; + + dl_rq->avg_bw += se_bw; +} + +static void clear_average_bw(struct sched_dl_entity *dl_se, struct dl_rq *dl_rq) +{ + u64 se_bw = dl_se->dl_bw; + + dl_rq->avg_bw -= se_bw; + if (dl_rq->avg_bw < 0) { + WARN_ON(1); + dl_rq->avg_bw = 0; + } +} + static inline int is_leftmost(struct task_struct *p, struct dl_rq *dl_rq) { struct sched_dl_entity *dl_se = &p->dl; @@ -271,9 +291,11 @@ /* * By now the task is replenished and enqueued; migrate it. */ + p->on_rq = TASK_ON_RQ_MIGRATING; deactivate_task(rq, p, 0); set_task_cpu(p, later_rq->cpu); activate_task(later_rq, p, 0); + p->on_rq = TASK_ON_RQ_QUEUED; if (!fallback) resched_curr(later_rq); @@ -565,6 +587,9 @@ struct dl_rq *dl_rq = dl_rq_of_se(dl_se); struct rq *rq = rq_of_dl_rq(dl_rq); + if (dl_se->dl_new) + add_average_bw(dl_se, dl_rq); + /* * The arrival of a new instance needs special treatment, i.e., * the actual scheduling parameters have to be "renewed". @@ -849,6 +874,9 @@ if (unlikely((s64)delta_exec <= 0)) return; + /* kick cpufreq (see the comment in kernel/sched/sched.h). */ + cpufreq_update_this_cpu(rq, SCHED_CPUFREQ_DL); + schedstat_set(curr->se.statistics.exec_max, max(curr->se.statistics.exec_max, delta_exec)); @@ -858,8 +886,6 @@ curr->se.exec_start = rq_clock_task(rq); cpuacct_charge(curr, delta_exec); - sched_rt_avg_update(rq, delta_exec); - dl_se->runtime -= dl_se->dl_yielded ? 0 : delta_exec; if (dl_runtime_exceeded(dl_se)) { dl_se->dl_throttled = 1; @@ -968,6 +994,41 @@ #endif /* CONFIG_SMP */ +#ifdef CONFIG_SCHED_HMP + +static void +inc_hmp_sched_stats_dl(struct rq *rq, struct task_struct *p) +{ + inc_cumulative_runnable_avg(&rq->hmp_stats, p); +} + +static void +dec_hmp_sched_stats_dl(struct rq *rq, struct task_struct *p) +{ + dec_cumulative_runnable_avg(&rq->hmp_stats, p); +} + +static void +fixup_hmp_sched_stats_dl(struct rq *rq, struct task_struct *p, + u32 new_task_load, u32 new_pred_demand) +{ + s64 task_load_delta = (s64)new_task_load - task_load(p); + s64 pred_demand_delta = PRED_DEMAND_DELTA; + + fixup_cumulative_runnable_avg(&rq->hmp_stats, p, task_load_delta, + pred_demand_delta); +} + +#else /* CONFIG_SCHED_HMP */ + +static inline void +inc_hmp_sched_stats_dl(struct rq *rq, struct task_struct *p) { } + +static inline void +dec_hmp_sched_stats_dl(struct rq *rq, struct task_struct *p) { } + +#endif /* CONFIG_SCHED_HMP */ + static inline void inc_dl_tasks(struct sched_dl_entity *dl_se, struct dl_rq *dl_rq) { @@ -977,6 +1038,7 @@ WARN_ON(!dl_prio(prio)); dl_rq->dl_nr_running++; add_nr_running(rq_of_dl_rq(dl_rq), 1); + inc_hmp_sched_stats_dl(rq_of_dl_rq(dl_rq), dl_task_of(dl_se)); inc_dl_deadline(dl_rq, deadline); inc_dl_migration(dl_se, dl_rq); @@ -991,6 +1053,7 @@ WARN_ON(!dl_rq->dl_nr_running); dl_rq->dl_nr_running--; sub_nr_running(rq_of_dl_rq(dl_rq), 1); + dec_hmp_sched_stats_dl(rq_of_dl_rq(dl_rq), dl_task_of(dl_se)); dec_dl_deadline(dl_rq, dl_se->deadline); dec_dl_migration(dl_se, dl_rq); @@ -1170,7 +1233,8 @@ static int find_later_rq(struct task_struct *task); static int -select_task_rq_dl(struct task_struct *p, int cpu, int sd_flag, int flags) +select_task_rq_dl(struct task_struct *p, int cpu, int sd_flag, int flags, + int sibling_count_hint) { struct task_struct *curr; struct rq *rq; @@ -1367,6 +1431,8 @@ static void task_dead_dl(struct task_struct *p) { struct dl_bw *dl_b = dl_bw_of(task_cpu(p)); + struct dl_rq *dl_rq = dl_rq_of_se(&p->dl); + struct rq *rq = rq_of_dl_rq(dl_rq); /* * Since we are TASK_DEAD we won't slip out of the domain! @@ -1375,6 +1441,8 @@ /* XXX we should retain the bw until 0-lag */ dl_b->total_bw -= p->dl.dl_bw; raw_spin_unlock_irq(&dl_b->lock); + + clear_average_bw(&p->dl, &rq->dl); } static void set_curr_task_dl(struct rq *rq) @@ -1681,9 +1749,15 @@ goto retry; } + next_task->on_rq = TASK_ON_RQ_MIGRATING; deactivate_task(rq, next_task, 0); + clear_average_bw(&next_task->dl, &rq->dl); + next_task->on_rq = TASK_ON_RQ_MIGRATING; set_task_cpu(next_task, later_rq->cpu); + next_task->on_rq = TASK_ON_RQ_QUEUED; + add_average_bw(&next_task->dl, &later_rq->dl); activate_task(later_rq, next_task, 0); + next_task->on_rq = TASK_ON_RQ_QUEUED; ret = 1; resched_curr(later_rq); @@ -1769,9 +1843,15 @@ resched = true; + p->on_rq = TASK_ON_RQ_MIGRATING; deactivate_task(src_rq, p, 0); + clear_average_bw(&p->dl, &src_rq->dl); + p->on_rq = TASK_ON_RQ_MIGRATING; set_task_cpu(p, this_cpu); + p->on_rq = TASK_ON_RQ_QUEUED; + add_average_bw(&p->dl, &this_rq->dl); activate_task(this_rq, p, 0); + p->on_rq = TASK_ON_RQ_QUEUED; dmin = p->dl.deadline; /* Is there any other task even earlier? */ @@ -1876,6 +1956,8 @@ if (!start_dl_timer(p)) __dl_clear_params(p); + clear_average_bw(&p->dl, &rq->dl); + /* * Since this might be the only -deadline task on the rq, * this is the right place to try to pull some other one @@ -1971,6 +2053,11 @@ .switched_to = switched_to_dl, .update_curr = update_curr_dl, +#ifdef CONFIG_SCHED_HMP + .inc_hmp_sched_stats = inc_hmp_sched_stats_dl, + .dec_hmp_sched_stats = dec_hmp_sched_stats_dl, + .fixup_hmp_sched_stats = fixup_hmp_sched_stats_dl, +#endif }; #ifdef CONFIG_SCHED_DEBUG diff -ruw linux-4.4.115/kernel/sched/debug.c linux-4.4.115-fbx/kernel/sched/debug.c --- linux-4.4.115/kernel/sched/debug.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/kernel/sched/debug.c 2019-01-22 16:16:28.695293423 +0100 @@ -227,6 +227,14 @@ cfs_rq->throttled); SEQ_printf(m, " .%-30s: %d\n", "throttle_count", cfs_rq->throttle_count); + SEQ_printf(m, " .%-30s: %d\n", "runtime_enabled", + cfs_rq->runtime_enabled); +#ifdef CONFIG_SCHED_HMP + SEQ_printf(m, " .%-30s: %d\n", "nr_big_tasks", + cfs_rq->hmp_stats.nr_big_tasks); + SEQ_printf(m, " .%-30s: %llu\n", "cumulative_runnable_avg", + cfs_rq->hmp_stats.cumulative_runnable_avg); +#endif #endif #ifdef CONFIG_FAIR_GROUP_SCHED @@ -306,6 +314,23 @@ P(cpu_load[2]); P(cpu_load[3]); P(cpu_load[4]); +#ifdef CONFIG_SMP + P(cpu_capacity); +#endif +#ifdef CONFIG_SCHED_HMP + P(static_cpu_pwr_cost); + P(cluster->static_cluster_pwr_cost); + P(cluster->load_scale_factor); + P(cluster->capacity); + P(cluster->max_possible_capacity); + P(cluster->efficiency); + P(cluster->cur_freq); + P(cluster->max_freq); + P(cluster->exec_scale_factor); + P(hmp_stats.nr_big_tasks); + SEQ_printf(m, " .%-30s: %llu\n", "hmp_stats.cumulative_runnable_avg", + rq->hmp_stats.cumulative_runnable_avg); +#endif #undef P #undef PN @@ -386,6 +411,15 @@ PN(sysctl_sched_wakeup_granularity); P(sysctl_sched_child_runs_first); P(sysctl_sched_features); +#ifdef CONFIG_SCHED_HMP + P(sched_upmigrate); + P(sched_downmigrate); + P(sched_init_task_load_windows); + P(min_capacity); + P(max_capacity); + P(sched_ravg_window); + P(sched_load_granule); +#endif #undef PN #undef P @@ -408,6 +442,7 @@ return 0; } +#ifdef CONFIG_SYSRQ_SCHED_DEBUG void sysrq_sched_debug_show(void) { int cpu; @@ -417,6 +452,7 @@ print_cpu(NULL, cpu); } +#endif /* * This itererator needs some explanation. @@ -547,6 +583,9 @@ void proc_sched_show_task(struct task_struct *p, struct seq_file *m) { unsigned long nr_switches; + unsigned int load_avg; + + load_avg = pct_task_load(p); SEQ_printf(m, "%s (%d, #threads: %d)\n", p->comm, task_pid_nr(p), get_nr_threads(p)); @@ -597,6 +636,39 @@ P(se.statistics.nr_wakeups_affine_attempts); P(se.statistics.nr_wakeups_passive); P(se.statistics.nr_wakeups_idle); + /* eas */ + /* select_idle_sibling() */ + P(se.statistics.nr_wakeups_sis_attempts); + P(se.statistics.nr_wakeups_sis_idle); + P(se.statistics.nr_wakeups_sis_cache_affine); + P(se.statistics.nr_wakeups_sis_suff_cap); + P(se.statistics.nr_wakeups_sis_idle_cpu); + P(se.statistics.nr_wakeups_sis_count); + /* select_energy_cpu_brute() */ + P(se.statistics.nr_wakeups_secb_attempts); + P(se.statistics.nr_wakeups_secb_sync); + P(se.statistics.nr_wakeups_secb_idle_bt); + P(se.statistics.nr_wakeups_secb_insuff_cap); + P(se.statistics.nr_wakeups_secb_no_nrg_sav); + P(se.statistics.nr_wakeups_secb_nrg_sav); + P(se.statistics.nr_wakeups_secb_count); + /* find_best_target() */ + P(se.statistics.nr_wakeups_fbt_attempts); + P(se.statistics.nr_wakeups_fbt_no_cpu); + P(se.statistics.nr_wakeups_fbt_no_sd); + P(se.statistics.nr_wakeups_fbt_pref_idle); + P(se.statistics.nr_wakeups_fbt_count); + /* cas */ + /* select_task_rq_fair() */ + P(se.statistics.nr_wakeups_cas_attempts); + P(se.statistics.nr_wakeups_cas_count); + +#if defined(CONFIG_SMP) && defined(CONFIG_FAIR_GROUP_SCHED) + __P(load_avg); +#ifdef CONFIG_SCHED_HMP + P(ravg.demand); +#endif +#endif { u64 avg_atom, avg_per_cpu; diff -ruw linux-4.4.115/kernel/sched/fair.c linux-4.4.115-fbx/kernel/sched/fair.c --- linux-4.4.115/kernel/sched/fair.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/kernel/sched/fair.c 2019-10-29 09:26:25.625222574 +0100 @@ -30,10 +30,12 @@ #include #include #include - -#include +#include #include "sched.h" +#include +#include "tune.h" +#include "walt.h" /* * Targeted preemption latency for CPU-bound tasks: @@ -50,6 +52,9 @@ unsigned int sysctl_sched_latency = 6000000ULL; unsigned int normalized_sysctl_sched_latency = 6000000ULL; +unsigned int sysctl_sched_sync_hint_enable = 1; +unsigned int sysctl_sched_cstate_aware = 1; + /* * The initial- and re-scaling of tunables is configurable * (default SCHED_TUNABLESCALING_LOG = *(1+ilog(ncpus)) @@ -114,6 +119,12 @@ unsigned int sysctl_sched_cfs_bandwidth_slice = 5000UL; #endif +/* + * The margin used when comparing utilization with CPU capacity: + * util * margin < capacity * 1024 + */ +unsigned int capacity_margin = 1280; /* ~20% */ + static inline void update_load_add(struct load_weight *lw, unsigned long inc) { lw->weight += inc; @@ -236,6 +247,9 @@ return mul_u64_u32_shr(delta_exec, fact, shift); } +#ifdef CONFIG_SMP +static int active_load_balance_cpu_stop(void *data); +#endif const struct sched_class fair_sched_class; @@ -286,19 +300,59 @@ static inline void list_add_leaf_cfs_rq(struct cfs_rq *cfs_rq) { if (!cfs_rq->on_list) { + struct rq *rq = rq_of(cfs_rq); + int cpu = cpu_of(rq); /* * Ensure we either appear before our parent (if already * enqueued) or force our parent to appear after us when it is * enqueued. The fact that we always enqueue bottom-up - * reduces this to two cases. + * reduces this to two cases and a special case for the root + * cfs_rq. Furthermore, it also means that we will always reset + * tmp_alone_branch either when the branch is connected + * to a tree or when we reach the beg of the tree */ if (cfs_rq->tg->parent && - cfs_rq->tg->parent->cfs_rq[cpu_of(rq_of(cfs_rq))]->on_list) { - list_add_rcu(&cfs_rq->leaf_cfs_rq_list, - &rq_of(cfs_rq)->leaf_cfs_rq_list); - } else { + cfs_rq->tg->parent->cfs_rq[cpu]->on_list) { + /* + * If parent is already on the list, we add the child + * just before. Thanks to circular linked property of + * the list, this means to put the child at the tail + * of the list that starts by parent. + */ list_add_tail_rcu(&cfs_rq->leaf_cfs_rq_list, - &rq_of(cfs_rq)->leaf_cfs_rq_list); + &(cfs_rq->tg->parent->cfs_rq[cpu]->leaf_cfs_rq_list)); + /* + * The branch is now connected to its tree so we can + * reset tmp_alone_branch to the beginning of the + * list. + */ + rq->tmp_alone_branch = &rq->leaf_cfs_rq_list; + } else if (!cfs_rq->tg->parent) { + /* + * cfs rq without parent should be put + * at the tail of the list. + */ + list_add_tail_rcu(&cfs_rq->leaf_cfs_rq_list, + &rq->leaf_cfs_rq_list); + /* + * We have reach the beg of a tree so we can reset + * tmp_alone_branch to the beginning of the list. + */ + rq->tmp_alone_branch = &rq->leaf_cfs_rq_list; + } else { + /* + * The parent has not already been added so we want to + * make sure that it will be put after us. + * tmp_alone_branch points to the beg of the branch + * where we will add parent. + */ + list_add_rcu(&cfs_rq->leaf_cfs_rq_list, + rq->tmp_alone_branch); + /* + * update tmp_alone_branch to points to the new beg + * of the branch + */ + rq->tmp_alone_branch = &cfs_rq->leaf_cfs_rq_list; } cfs_rq->on_list = 1; @@ -656,7 +710,7 @@ } #ifdef CONFIG_SMP -static int select_idle_sibling(struct task_struct *p, int cpu); +static int select_idle_sibling(struct task_struct *p, int prev_cpu, int cpu); static unsigned long task_h_load(struct task_struct *p); /* @@ -680,18 +734,115 @@ * will definitely be update (after enqueue). */ sa->period_contrib = 1023; + /* + * Tasks are intialized with full load to be seen as heavy tasks until + * they get a chance to stabilize to their real load level. + * Group entities are intialized with zero load to reflect the fact that + * nothing has been attached to the task group yet. + */ + if (entity_is_task(se)) sa->load_avg = scale_load_down(se->load.weight); sa->load_sum = sa->load_avg * LOAD_AVG_MAX; - sa->util_avg = scale_load_down(SCHED_LOAD_SCALE); - sa->util_sum = sa->util_avg * LOAD_AVG_MAX; + /* + * In previous Android versions, we used to have: + * sa->util_avg = scale_load_down(SCHED_LOAD_SCALE); + * sa->util_sum = sa->util_avg * LOAD_AVG_MAX; + * However, that functionality has been moved to enqueue. + * It is unclear if we should restore this in enqueue. + */ + /* + * At this point, util_avg won't be used in select_task_rq_fair anyway + */ + sa->util_avg = 0; + sa->util_sum = 0; /* when this task enqueue'ed, it will contribute to its cfs_rq's load_avg */ } -#else +static inline u64 cfs_rq_clock_task(struct cfs_rq *cfs_rq); +static int update_cfs_rq_load_avg(u64 now, struct cfs_rq *cfs_rq, bool update_freq); +static void attach_entity_cfs_rq(struct sched_entity *se); +static void attach_entity_load_avg(struct cfs_rq *cfs_rq, struct sched_entity *se); + +/* + * With new tasks being created, their initial util_avgs are extrapolated + * based on the cfs_rq's current util_avg: + * + * util_avg = cfs_rq->util_avg / (cfs_rq->load_avg + 1) * se.load.weight + * + * However, in many cases, the above util_avg does not give a desired + * value. Moreover, the sum of the util_avgs may be divergent, such + * as when the series is a harmonic series. + * + * To solve this problem, we also cap the util_avg of successive tasks to + * only 1/2 of the left utilization budget: + * + * util_avg_cap = (1024 - cfs_rq->avg.util_avg) / 2^n + * + * where n denotes the nth task. + * + * For example, a simplest series from the beginning would be like: + * + * task util_avg: 512, 256, 128, 64, 32, 16, 8, ... + * cfs_rq util_avg: 512, 768, 896, 960, 992, 1008, 1016, ... + * + * Finally, that extrapolated util_avg is clamped to the cap (util_avg_cap) + * if util_avg > util_avg_cap. + */ +void post_init_entity_util_avg(struct sched_entity *se) +{ + struct cfs_rq *cfs_rq = cfs_rq_of(se); + struct sched_avg *sa = &se->avg; + long cap = (long)(SCHED_CAPACITY_SCALE - cfs_rq->avg.util_avg) / 2; + + if (cap > 0) { + if (cfs_rq->avg.util_avg != 0) { + sa->util_avg = cfs_rq->avg.util_avg * se->load.weight; + sa->util_avg /= (cfs_rq->avg.load_avg + 1); + + if (sa->util_avg > cap) + sa->util_avg = cap; + } else { + sa->util_avg = cap; + } + /* + * If we wish to restore tuning via setting initial util, + * this is where we should do it. + */ + sa->util_sum = sa->util_avg * LOAD_AVG_MAX; + } + + if (entity_is_task(se)) { + struct task_struct *p = task_of(se); + if (p->sched_class != &fair_sched_class) { + /* + * For !fair tasks do: + * + update_cfs_rq_load_avg(now, cfs_rq, false); + attach_entity_load_avg(cfs_rq, se); + switched_from_fair(rq, p); + * + * such that the next switched_to_fair() has the + * expected state. + */ + se->avg.last_update_time = cfs_rq_clock_task(cfs_rq); + return; + } + } + + attach_entity_cfs_rq(se); +} + +#else /* !CONFIG_SMP */ void init_entity_runnable_average(struct sched_entity *se) { } -#endif +void post_init_entity_util_avg(struct sched_entity *se) +{ +} +static void update_tg_load_avg(struct cfs_rq *cfs_rq, int force) +{ +} +#endif /* CONFIG_SMP */ /* * Update the current task's runtime statistics. @@ -736,12 +887,56 @@ update_curr(cfs_rq_of(&rq->curr->se)); } +#ifdef CONFIG_SCHEDSTATS +static inline void +update_stats_wait_start(struct cfs_rq *cfs_rq, struct sched_entity *se) +{ + u64 wait_start = rq_clock(rq_of(cfs_rq)); + + if (entity_is_task(se) && task_on_rq_migrating(task_of(se)) && + likely(wait_start > se->statistics.wait_start)) + wait_start -= se->statistics.wait_start; + + se->statistics.wait_start = wait_start; +} + +static void +update_stats_wait_end(struct cfs_rq *cfs_rq, struct sched_entity *se) +{ + struct task_struct *p; + u64 delta = rq_clock(rq_of(cfs_rq)) - se->statistics.wait_start; + + if (entity_is_task(se)) { + p = task_of(se); + if (task_on_rq_migrating(p)) { + /* + * Preserve migrating task's wait time so wait_start + * time stamp can be adjusted to accumulate wait time + * prior to migration. + */ + se->statistics.wait_start = delta; + return; + } + trace_sched_stat_wait(p, delta); + } + + se->statistics.wait_max = max(se->statistics.wait_max, delta); + se->statistics.wait_count++; + se->statistics.wait_sum += delta; + se->statistics.wait_start = 0; +} +#else static inline void update_stats_wait_start(struct cfs_rq *cfs_rq, struct sched_entity *se) { - schedstat_set(se->statistics.wait_start, rq_clock(rq_of(cfs_rq))); } +static inline void +update_stats_wait_end(struct cfs_rq *cfs_rq, struct sched_entity *se) +{ +} +#endif + /* * Task is being enqueued - update stats: */ @@ -755,23 +950,6 @@ update_stats_wait_start(cfs_rq, se); } -static void -update_stats_wait_end(struct cfs_rq *cfs_rq, struct sched_entity *se) -{ - schedstat_set(se->statistics.wait_max, max(se->statistics.wait_max, - rq_clock(rq_of(cfs_rq)) - se->statistics.wait_start)); - schedstat_set(se->statistics.wait_count, se->statistics.wait_count + 1); - schedstat_set(se->statistics.wait_sum, se->statistics.wait_sum + - rq_clock(rq_of(cfs_rq)) - se->statistics.wait_start); -#ifdef CONFIG_SCHEDSTATS - if (entity_is_task(se)) { - trace_sched_stat_wait(task_of(se), - rq_clock(rq_of(cfs_rq)) - se->statistics.wait_start); - } -#endif - schedstat_set(se->statistics.wait_start, 0); -} - static inline void update_stats_dequeue(struct cfs_rq *cfs_rq, struct sched_entity *se) { @@ -1388,7 +1566,8 @@ * Call select_idle_sibling to maybe find a better one. */ if (!cur) - env->dst_cpu = select_idle_sibling(env->p, env->dst_cpu); + env->dst_cpu = select_idle_sibling(env->p, env->src_cpu, + env->dst_cpu); assign: assigned = true; @@ -2373,28 +2552,22 @@ #ifdef CONFIG_FAIR_GROUP_SCHED # ifdef CONFIG_SMP -static inline long calc_tg_weight(struct task_group *tg, struct cfs_rq *cfs_rq) +static long calc_cfs_shares(struct cfs_rq *cfs_rq, struct task_group *tg) { - long tg_weight; + long tg_weight, load, shares; /* - * Use this CPU's real-time load instead of the last load contribution - * as the updating of the contribution is delayed, and we will use the - * the real-time load to calc the share. See update_tg_load_avg(). + * This really should be: cfs_rq->avg.load_avg, but instead we use + * cfs_rq->load.weight, which is its upper bound. This helps ramp up + * the shares for small weight interactive tasks. */ - tg_weight = atomic_long_read(&tg->load_avg); - tg_weight -= cfs_rq->tg_load_avg_contrib; - tg_weight += cfs_rq->load.weight; - - return tg_weight; -} + load = scale_load_down(cfs_rq->load.weight); -static long calc_cfs_shares(struct cfs_rq *cfs_rq, struct task_group *tg) -{ - long tg_weight, load, shares; + tg_weight = atomic_long_read(&tg->load_avg); - tg_weight = calc_tg_weight(tg, cfs_rq); - load = cfs_rq->load.weight; + /* Ensure tg_weight >= load */ + tg_weight -= cfs_rq->tg_load_avg_contrib; + tg_weight += load; shares = (tg->shares * load); if (tg_weight) @@ -2413,6 +2586,7 @@ return tg->shares; } # endif /* CONFIG_SMP */ + static void reweight_entity(struct cfs_rq *cfs_rq, struct sched_entity *se, unsigned long weight) { @@ -2431,16 +2605,20 @@ static inline int throttled_hierarchy(struct cfs_rq *cfs_rq); -static void update_cfs_shares(struct cfs_rq *cfs_rq) +static void update_cfs_shares(struct sched_entity *se) { + struct cfs_rq *cfs_rq = group_cfs_rq(se); struct task_group *tg; - struct sched_entity *se; long shares; - tg = cfs_rq->tg; - se = tg->se[cpu_of(rq_of(cfs_rq))]; - if (!se || throttled_hierarchy(cfs_rq)) + if (!cfs_rq) return; + + if (throttled_hierarchy(cfs_rq)) + return; + + tg = cfs_rq->tg; + #ifndef CONFIG_SMP if (likely(se->load.weight == tg->shares)) return; @@ -2449,14 +2627,33 @@ reweight_entity(cfs_rq_of(se), se, shares); } + #else /* CONFIG_FAIR_GROUP_SCHED */ -static inline void update_cfs_shares(struct cfs_rq *cfs_rq) +static inline void update_cfs_shares(struct sched_entity *se) { } #endif /* CONFIG_FAIR_GROUP_SCHED */ #ifdef CONFIG_SMP -/* Precomputed fixed inverse multiplies for multiplication by y^n */ +u32 sched_get_wake_up_idle(struct task_struct *p) +{ + u32 enabled = p->flags & PF_WAKE_UP_IDLE; + + return !!enabled; +} + +int sched_set_wake_up_idle(struct task_struct *p, int wake_up_idle) +{ + int enable = !!wake_up_idle; + + if (enable) + p->flags |= PF_WAKE_UP_IDLE; + else + p->flags &= ~PF_WAKE_UP_IDLE; + + return 0; +} + static const u32 runnable_avg_yN_inv[] = { 0xffffffff, 0xfa83b2da, 0xf5257d14, 0xefe4b99a, 0xeac0c6e6, 0xe5b906e6, 0xe0ccdeeb, 0xdbfbb796, 0xd744fcc9, 0xd2a81d91, 0xce248c14, 0xc9b9bd85, @@ -2536,6 +2733,1064 @@ return contrib + runnable_avg_yN_sum[n]; } +#ifdef CONFIG_SCHED_HMP + +/* CPU selection flag */ +#define SBC_FLAG_PREV_CPU 0x1 +#define SBC_FLAG_BEST_CAP_CPU 0x2 +#define SBC_FLAG_CPU_COST 0x4 +#define SBC_FLAG_MIN_COST 0x8 +#define SBC_FLAG_IDLE_LEAST_LOADED 0x10 +#define SBC_FLAG_IDLE_CSTATE 0x20 +#define SBC_FLAG_COST_CSTATE_TIE_BREAKER 0x40 +#define SBC_FLAG_COST_CSTATE_PREV_CPU_TIE_BREAKER 0x80 +#define SBC_FLAG_CSTATE_LOAD 0x100 +#define SBC_FLAG_BEST_SIBLING 0x200 +#define SBC_FLAG_WAKER_CPU 0x400 +#define SBC_FLAG_PACK_TASK 0x800 + +/* Cluster selection flag */ +#define SBC_FLAG_COLOC_CLUSTER 0x10000 +#define SBC_FLAG_WAKER_CLUSTER 0x20000 +#define SBC_FLAG_BACKUP_CLUSTER 0x40000 +#define SBC_FLAG_BOOST_CLUSTER 0x80000 + +struct cpu_select_env { + struct task_struct *p; + struct related_thread_group *rtg; + u8 reason; + u8 need_idle:1; + u8 need_waker_cluster:1; + u8 sync:1; + enum sched_boost_policy boost_policy; + u8 pack_task:1; + int prev_cpu; + DECLARE_BITMAP(candidate_list, NR_CPUS); + DECLARE_BITMAP(backup_list, NR_CPUS); + u64 task_load; + u64 cpu_load; + u32 sbc_best_flag; + u32 sbc_best_cluster_flag; + struct cpumask search_cpus; +}; + +struct cluster_cpu_stats { + int best_idle_cpu, least_loaded_cpu; + int best_capacity_cpu, best_cpu, best_sibling_cpu; + int min_cost, best_sibling_cpu_cost; + int best_cpu_wakeup_latency; + u64 min_load, best_load, best_sibling_cpu_load; + s64 highest_spare_capacity; +}; + +/* + * Should task be woken to any available idle cpu? + * + * Waking tasks to idle cpu has mixed implications on both performance and + * power. In many cases, scheduler can't estimate correctly impact of using idle + * cpus on either performance or power. PF_WAKE_UP_IDLE allows external kernel + * module to pass a strong hint to scheduler that the task in question should be + * woken to idle cpu, generally to improve performance. + */ +static inline int wake_to_idle(struct task_struct *p) +{ + return (current->flags & PF_WAKE_UP_IDLE) || + (p->flags & PF_WAKE_UP_IDLE); +} + +static int spill_threshold_crossed(struct cpu_select_env *env, struct rq *rq) +{ + u64 total_load; + + total_load = env->task_load + env->cpu_load; + + if (total_load > sched_spill_load || + (rq->nr_running + 1) > sysctl_sched_spill_nr_run) + return 1; + + return 0; +} + +static int skip_cpu(int cpu, struct cpu_select_env *env) +{ + int tcpu = task_cpu(env->p); + int skip = 0; + + if (!env->reason) + return 0; + + if (is_reserved(cpu)) + return 1; + + switch (env->reason) { + case UP_MIGRATION: + skip = !idle_cpu(cpu); + break; + case IRQLOAD_MIGRATION: + /* Purposely fall through */ + default: + skip = (cpu == tcpu); + break; + } + + return skip; +} + +static inline int +acceptable_capacity(struct sched_cluster *cluster, struct cpu_select_env *env) +{ + int tcpu; + + if (!env->reason) + return 1; + + tcpu = task_cpu(env->p); + switch (env->reason) { + case UP_MIGRATION: + return cluster->capacity > cpu_capacity(tcpu); + + case DOWN_MIGRATION: + return cluster->capacity < cpu_capacity(tcpu); + + default: + break; + } + + return 1; +} + +static int +skip_cluster(struct sched_cluster *cluster, struct cpu_select_env *env) +{ + if (!test_bit(cluster->id, env->candidate_list)) + return 1; + + if (!acceptable_capacity(cluster, env)) { + __clear_bit(cluster->id, env->candidate_list); + return 1; + } + + return 0; +} + +static struct sched_cluster * +select_least_power_cluster(struct cpu_select_env *env) +{ + struct sched_cluster *cluster; + + if (env->rtg) { + int cpu = cluster_first_cpu(env->rtg->preferred_cluster); + + env->task_load = scale_load_to_cpu(task_load(env->p), cpu); + + if (task_load_will_fit(env->p, env->task_load, + cpu, env->boost_policy)) { + env->sbc_best_cluster_flag |= SBC_FLAG_COLOC_CLUSTER; + + if (env->boost_policy == SCHED_BOOST_NONE) + return env->rtg->preferred_cluster; + + for_each_sched_cluster(cluster) { + if (cluster != env->rtg->preferred_cluster) { + __set_bit(cluster->id, + env->backup_list); + __clear_bit(cluster->id, + env->candidate_list); + } + } + + return env->rtg->preferred_cluster; + } + + /* + * Since the task load does not fit on the preferred + * cluster anymore, pretend that the task does not + * have any preferred cluster. This allows the waking + * task to get the appropriate CPU it needs as per the + * non co-location placement policy without having to + * wait until the preferred cluster is updated. + */ + env->rtg = NULL; + } + + for_each_sched_cluster(cluster) { + if (!skip_cluster(cluster, env)) { + int cpu = cluster_first_cpu(cluster); + + env->task_load = scale_load_to_cpu(task_load(env->p), + cpu); + if (task_load_will_fit(env->p, env->task_load, cpu, + env->boost_policy)) + return cluster; + + __set_bit(cluster->id, env->backup_list); + __clear_bit(cluster->id, env->candidate_list); + } + } + + return NULL; +} + +static struct sched_cluster * +next_candidate(const unsigned long *list, int start, int end) +{ + int cluster_id; + + cluster_id = find_next_bit(list, end, start - 1 + 1); + if (cluster_id >= end) + return NULL; + + return sched_cluster[cluster_id]; +} + +static void +update_spare_capacity(struct cluster_cpu_stats *stats, + struct cpu_select_env *env, int cpu, int capacity, + u64 cpu_load) +{ + s64 spare_capacity = sched_ravg_window - cpu_load; + + if (spare_capacity > 0 && + (spare_capacity > stats->highest_spare_capacity || + (spare_capacity == stats->highest_spare_capacity && + ((!env->need_waker_cluster && + capacity > cpu_capacity(stats->best_capacity_cpu)) || + (env->need_waker_cluster && + cpu_rq(cpu)->nr_running < + cpu_rq(stats->best_capacity_cpu)->nr_running))))) { + /* + * If sync waker is the only runnable of CPU, cr_avg of the + * CPU is 0 so we have high chance to place the wakee on the + * waker's CPU which likely causes preemtion of the waker. + * This can lead migration of preempted waker. Place the + * wakee on the real idle CPU when it's possible by checking + * nr_running to avoid such preemption. + */ + stats->highest_spare_capacity = spare_capacity; + stats->best_capacity_cpu = cpu; + } +} + +static inline void find_backup_cluster( +struct cpu_select_env *env, struct cluster_cpu_stats *stats) +{ + struct sched_cluster *next = NULL; + int i; + struct cpumask search_cpus; + + while (!bitmap_empty(env->backup_list, num_clusters)) { + next = next_candidate(env->backup_list, 0, num_clusters); + __clear_bit(next->id, env->backup_list); + + cpumask_and(&search_cpus, &env->search_cpus, &next->cpus); + for_each_cpu(i, &search_cpus) { + trace_sched_cpu_load_wakeup(cpu_rq(i), idle_cpu(i), + sched_irqload(i), power_cost(i, task_load(env->p) + + cpu_cravg_sync(i, env->sync)), 0); + + update_spare_capacity(stats, env, i, next->capacity, + cpu_load_sync(i, env->sync)); + } + env->sbc_best_cluster_flag = SBC_FLAG_BACKUP_CLUSTER; + } +} + +struct sched_cluster * +next_best_cluster(struct sched_cluster *cluster, struct cpu_select_env *env, + struct cluster_cpu_stats *stats) +{ + struct sched_cluster *next = NULL; + + __clear_bit(cluster->id, env->candidate_list); + + if (env->rtg && preferred_cluster(cluster, env->p)) + return NULL; + + do { + if (bitmap_empty(env->candidate_list, num_clusters)) + return NULL; + + next = next_candidate(env->candidate_list, 0, num_clusters); + if (next) { + if (next->min_power_cost > stats->min_cost) { + clear_bit(next->id, env->candidate_list); + next = NULL; + continue; + } + + if (skip_cluster(next, env)) + next = NULL; + } + } while (!next); + + env->task_load = scale_load_to_cpu(task_load(env->p), + cluster_first_cpu(next)); + return next; +} + +#ifdef CONFIG_SCHED_HMP_CSTATE_AWARE +static void __update_cluster_stats(int cpu, struct cluster_cpu_stats *stats, + struct cpu_select_env *env, int cpu_cost) +{ + int wakeup_latency; + int prev_cpu = env->prev_cpu; + + wakeup_latency = cpu_rq(cpu)->wakeup_latency; + + if (env->need_idle) { + stats->min_cost = cpu_cost; + if (idle_cpu(cpu)) { + if (wakeup_latency < stats->best_cpu_wakeup_latency || + (wakeup_latency == stats->best_cpu_wakeup_latency && + cpu == prev_cpu)) { + stats->best_idle_cpu = cpu; + stats->best_cpu_wakeup_latency = wakeup_latency; + } + } else { + if (env->cpu_load < stats->min_load || + (env->cpu_load == stats->min_load && + cpu == prev_cpu)) { + stats->least_loaded_cpu = cpu; + stats->min_load = env->cpu_load; + } + } + + return; + } + + if (cpu_cost < stats->min_cost) { + stats->min_cost = cpu_cost; + stats->best_cpu_wakeup_latency = wakeup_latency; + stats->best_load = env->cpu_load; + stats->best_cpu = cpu; + env->sbc_best_flag = SBC_FLAG_CPU_COST; + return; + } + + /* CPU cost is the same. Start breaking the tie by C-state */ + + if (wakeup_latency > stats->best_cpu_wakeup_latency) + return; + + if (wakeup_latency < stats->best_cpu_wakeup_latency) { + stats->best_cpu_wakeup_latency = wakeup_latency; + stats->best_load = env->cpu_load; + stats->best_cpu = cpu; + env->sbc_best_flag = SBC_FLAG_COST_CSTATE_TIE_BREAKER; + return; + } + + /* C-state is the same. Use prev CPU to break the tie */ + if (cpu == prev_cpu) { + stats->best_cpu = cpu; + env->sbc_best_flag = SBC_FLAG_COST_CSTATE_PREV_CPU_TIE_BREAKER; + return; + } + + if (stats->best_cpu != prev_cpu && + ((wakeup_latency == 0 && env->cpu_load < stats->best_load) || + (wakeup_latency > 0 && env->cpu_load > stats->best_load))) { + stats->best_load = env->cpu_load; + stats->best_cpu = cpu; + env->sbc_best_flag = SBC_FLAG_CSTATE_LOAD; + } +} +#else /* CONFIG_SCHED_HMP_CSTATE_AWARE */ +static void __update_cluster_stats(int cpu, struct cluster_cpu_stats *stats, + struct cpu_select_env *env, int cpu_cost) +{ + int prev_cpu = env->prev_cpu; + + if (cpu != prev_cpu && cpus_share_cache(prev_cpu, cpu)) { + if (stats->best_sibling_cpu_cost > cpu_cost || + (stats->best_sibling_cpu_cost == cpu_cost && + stats->best_sibling_cpu_load > env->cpu_load)) { + stats->best_sibling_cpu_cost = cpu_cost; + stats->best_sibling_cpu_load = env->cpu_load; + stats->best_sibling_cpu = cpu; + } + } + + if ((cpu_cost < stats->min_cost) || + ((stats->best_cpu != prev_cpu && + stats->min_load > env->cpu_load) || cpu == prev_cpu)) { + if (env->need_idle) { + if (idle_cpu(cpu)) { + stats->min_cost = cpu_cost; + stats->best_idle_cpu = cpu; + } + } else { + stats->min_cost = cpu_cost; + stats->min_load = env->cpu_load; + stats->best_cpu = cpu; + env->sbc_best_flag = SBC_FLAG_MIN_COST; + } + } +} +#endif /* CONFIG_SCHED_HMP_CSTATE_AWARE */ + +static void update_cluster_stats(int cpu, struct cluster_cpu_stats *stats, + struct cpu_select_env *env) +{ + int cpu_cost; + + /* + * We try to find the least loaded *busy* CPU irrespective + * of the power cost. + */ + if (env->pack_task) + cpu_cost = cpu_min_power_cost(cpu); + + else + cpu_cost = power_cost(cpu, task_load(env->p) + + cpu_cravg_sync(cpu, env->sync)); + + if (cpu_cost <= stats->min_cost) + __update_cluster_stats(cpu, stats, env, cpu_cost); +} + +static void find_best_cpu_in_cluster(struct sched_cluster *c, + struct cpu_select_env *env, struct cluster_cpu_stats *stats) +{ + int i; + struct cpumask search_cpus; + + cpumask_and(&search_cpus, &env->search_cpus, &c->cpus); + + env->need_idle = wake_to_idle(env->p) || c->wake_up_idle; + + for_each_cpu(i, &search_cpus) { + env->cpu_load = cpu_load_sync(i, env->sync); + + trace_sched_cpu_load_wakeup(cpu_rq(i), idle_cpu(i), + sched_irqload(i), + power_cost(i, task_load(env->p) + + cpu_cravg_sync(i, env->sync)), 0); + + if (skip_cpu(i, env)) + continue; + + update_spare_capacity(stats, env, i, c->capacity, + env->cpu_load); + + /* + * need_idle takes precedence over sched boost but when both + * are set, idlest CPU with in all the clusters is selected + * when boost_policy = BOOST_ON_ALL whereas idlest CPU in the + * big cluster is selected within boost_policy = BOOST_ON_BIG. + */ + if ((!env->need_idle && + env->boost_policy != SCHED_BOOST_NONE) || + env->need_waker_cluster || + sched_cpu_high_irqload(i) || + spill_threshold_crossed(env, cpu_rq(i))) + continue; + + update_cluster_stats(i, stats, env); + } +} + +static inline void init_cluster_cpu_stats(struct cluster_cpu_stats *stats) +{ + stats->best_cpu = stats->best_idle_cpu = -1; + stats->best_capacity_cpu = stats->best_sibling_cpu = -1; + stats->min_cost = stats->best_sibling_cpu_cost = INT_MAX; + stats->min_load = stats->best_sibling_cpu_load = ULLONG_MAX; + stats->highest_spare_capacity = 0; + stats->least_loaded_cpu = -1; + stats->best_cpu_wakeup_latency = INT_MAX; + /* No need to initialize stats->best_load */ +} + +static inline bool env_has_special_flags(struct cpu_select_env *env) +{ + if (env->need_idle || env->boost_policy != SCHED_BOOST_NONE || + env->reason) + return true; + + return false; +} + +static inline bool +bias_to_prev_cpu(struct cpu_select_env *env, struct cluster_cpu_stats *stats) +{ + int prev_cpu; + struct task_struct *task = env->p; + struct sched_cluster *cluster; + + if (!task->ravg.mark_start || !sched_short_sleep_task_threshold) + return false; + + prev_cpu = env->prev_cpu; + if (!cpumask_test_cpu(prev_cpu, &env->search_cpus)) + return false; + + if (task->ravg.mark_start - task->last_cpu_selected_ts >= + sched_long_cpu_selection_threshold) + return false; + + /* + * This function should be used by task wake up path only as it's + * assuming p->last_switch_out_ts as last sleep time. + * p->last_switch_out_ts can denote last preemption time as well as + * last sleep time. + */ + if (task->ravg.mark_start - task->last_switch_out_ts >= + sched_short_sleep_task_threshold) + return false; + + env->task_load = scale_load_to_cpu(task_load(task), prev_cpu); + cluster = cpu_rq(prev_cpu)->cluster; + + if (!task_load_will_fit(task, env->task_load, prev_cpu, + sched_boost_policy())) { + + __set_bit(cluster->id, env->backup_list); + __clear_bit(cluster->id, env->candidate_list); + return false; + } + + env->cpu_load = cpu_load_sync(prev_cpu, env->sync); + if (sched_cpu_high_irqload(prev_cpu) || + spill_threshold_crossed(env, cpu_rq(prev_cpu))) { + update_spare_capacity(stats, env, prev_cpu, + cluster->capacity, env->cpu_load); + cpumask_clear_cpu(prev_cpu, &env->search_cpus); + return false; + } + + return true; +} + +static inline bool +wake_to_waker_cluster(struct cpu_select_env *env) +{ + return env->sync && + task_load(current) > sched_big_waker_task_load && + task_load(env->p) < sched_small_wakee_task_load; +} + +static inline bool +bias_to_waker_cpu(struct cpu_select_env *env, int cpu) +{ + return sysctl_sched_prefer_sync_wakee_to_waker && + cpu_rq(cpu)->nr_running == 1 && + cpumask_test_cpu(cpu, &env->search_cpus); +} + +static inline int +cluster_allowed(struct cpu_select_env *env, struct sched_cluster *cluster) +{ + return cpumask_intersects(&env->search_cpus, &cluster->cpus); +} + +/* return cheapest cpu that can fit this task */ +static int select_best_cpu(struct task_struct *p, int target, int reason, + int sync) +{ + struct sched_cluster *cluster, *pref_cluster = NULL; + struct cluster_cpu_stats stats; + struct related_thread_group *grp; + unsigned int sbc_flag = 0; + int cpu = raw_smp_processor_id(); + bool special; + + struct cpu_select_env env = { + .p = p, + .reason = reason, + .need_idle = wake_to_idle(p), + .need_waker_cluster = 0, + .sync = sync, + .prev_cpu = target, + .rtg = NULL, + .sbc_best_flag = 0, + .sbc_best_cluster_flag = 0, + .pack_task = false, + }; + + env.boost_policy = task_sched_boost(p) ? + sched_boost_policy() : SCHED_BOOST_NONE; + + bitmap_copy(env.candidate_list, all_cluster_ids, NR_CPUS); + bitmap_zero(env.backup_list, NR_CPUS); + + cpumask_and(&env.search_cpus, tsk_cpus_allowed(p), cpu_active_mask); + cpumask_andnot(&env.search_cpus, &env.search_cpus, cpu_isolated_mask); + + init_cluster_cpu_stats(&stats); + special = env_has_special_flags(&env); + + rcu_read_lock(); + + grp = task_related_thread_group(p); + + if (grp && grp->preferred_cluster) { + pref_cluster = grp->preferred_cluster; + if (!cluster_allowed(&env, pref_cluster)) + clear_bit(pref_cluster->id, env.candidate_list); + else + env.rtg = grp; + } else if (!special) { + cluster = cpu_rq(cpu)->cluster; + if (wake_to_waker_cluster(&env)) { + if (bias_to_waker_cpu(&env, cpu)) { + target = cpu; + sbc_flag = SBC_FLAG_WAKER_CLUSTER | + SBC_FLAG_WAKER_CPU; + goto out; + } else if (cluster_allowed(&env, cluster)) { + env.need_waker_cluster = 1; + bitmap_zero(env.candidate_list, NR_CPUS); + __set_bit(cluster->id, env.candidate_list); + env.sbc_best_cluster_flag = + SBC_FLAG_WAKER_CLUSTER; + } + } else if (bias_to_prev_cpu(&env, &stats)) { + sbc_flag = SBC_FLAG_PREV_CPU; + goto out; + } + } + + if (!special && is_short_burst_task(p)) { + env.pack_task = true; + sbc_flag = SBC_FLAG_PACK_TASK; + } +retry: + cluster = select_least_power_cluster(&env); + + if (!cluster) + goto out; + + /* + * 'cluster' now points to the minimum power cluster which can satisfy + * task's perf goals. Walk down the cluster list starting with that + * cluster. For non-small tasks, skip clusters that don't have + * mostly_idle/idle cpus + */ + + do { + find_best_cpu_in_cluster(cluster, &env, &stats); + + } while ((cluster = next_best_cluster(cluster, &env, &stats))); + + if (env.need_idle) { + if (stats.best_idle_cpu >= 0) { + target = stats.best_idle_cpu; + sbc_flag |= SBC_FLAG_IDLE_CSTATE; + } else if (stats.least_loaded_cpu >= 0) { + target = stats.least_loaded_cpu; + sbc_flag |= SBC_FLAG_IDLE_LEAST_LOADED; + } + } else if (stats.best_cpu >= 0) { + if (stats.best_sibling_cpu >= 0 && + stats.best_cpu != task_cpu(p) && + stats.min_cost == stats.best_sibling_cpu_cost) { + stats.best_cpu = stats.best_sibling_cpu; + sbc_flag |= SBC_FLAG_BEST_SIBLING; + } + sbc_flag |= env.sbc_best_flag; + target = stats.best_cpu; + } else { + if (env.rtg && env.boost_policy == SCHED_BOOST_NONE) { + env.rtg = NULL; + goto retry; + } + + /* + * With boost_policy == SCHED_BOOST_ON_BIG, we reach here with + * backup_list = little cluster, candidate_list = none and + * stats->best_capacity_cpu points the best spare capacity + * CPU among the CPUs in the big cluster. + */ + if (env.boost_policy == SCHED_BOOST_ON_BIG && + stats.best_capacity_cpu >= 0) + sbc_flag |= SBC_FLAG_BOOST_CLUSTER; + else + find_backup_cluster(&env, &stats); + + if (stats.best_capacity_cpu >= 0) { + target = stats.best_capacity_cpu; + sbc_flag |= SBC_FLAG_BEST_CAP_CPU; + } + } + p->last_cpu_selected_ts = sched_ktime_clock(); +out: + sbc_flag |= env.sbc_best_cluster_flag; + rcu_read_unlock(); + trace_sched_task_load(p, sched_boost_policy() && task_sched_boost(p), + env.reason, env.sync, env.need_idle, sbc_flag, target); + return target; +} + +#ifdef CONFIG_CFS_BANDWIDTH + +static inline struct task_group *next_task_group(struct task_group *tg) +{ + tg = list_entry_rcu(tg->list.next, typeof(struct task_group), list); + + return (&tg->list == &task_groups) ? NULL : tg; +} + +/* Iterate over all cfs_rq in a cpu */ +#define for_each_cfs_rq(cfs_rq, tg, cpu) \ + for (tg = container_of(&task_groups, struct task_group, list); \ + ((tg = next_task_group(tg)) && (cfs_rq = tg->cfs_rq[cpu]));) + +void reset_cfs_rq_hmp_stats(int cpu, int reset_cra) +{ + struct task_group *tg; + struct cfs_rq *cfs_rq; + + rcu_read_lock(); + + for_each_cfs_rq(cfs_rq, tg, cpu) + reset_hmp_stats(&cfs_rq->hmp_stats, reset_cra); + + rcu_read_unlock(); +} + +static inline int cfs_rq_throttled(struct cfs_rq *cfs_rq); + +static void inc_cfs_rq_hmp_stats(struct cfs_rq *cfs_rq, + struct task_struct *p, int change_cra); +static void dec_cfs_rq_hmp_stats(struct cfs_rq *cfs_rq, + struct task_struct *p, int change_cra); + +/* Add task's contribution to a cpu' HMP statistics */ +void _inc_hmp_sched_stats_fair(struct rq *rq, + struct task_struct *p, int change_cra) +{ + struct cfs_rq *cfs_rq; + struct sched_entity *se = &p->se; + + /* + * Although below check is not strictly required (as + * inc/dec_nr_big_task and inc/dec_cumulative_runnable_avg called + * from inc_cfs_rq_hmp_stats() have similar checks), we gain a bit on + * efficiency by short-circuiting for_each_sched_entity() loop when + * sched_disable_window_stats + */ + if (sched_disable_window_stats) + return; + + for_each_sched_entity(se) { + cfs_rq = cfs_rq_of(se); + inc_cfs_rq_hmp_stats(cfs_rq, p, change_cra); + if (cfs_rq_throttled(cfs_rq)) + break; + } + + /* Update rq->hmp_stats only if we didn't find any throttled cfs_rq */ + if (!se) + inc_rq_hmp_stats(rq, p, change_cra); +} + +/* Remove task's contribution from a cpu' HMP statistics */ +static void +_dec_hmp_sched_stats_fair(struct rq *rq, struct task_struct *p, int change_cra) +{ + struct cfs_rq *cfs_rq; + struct sched_entity *se = &p->se; + + /* See comment on efficiency in _inc_hmp_sched_stats_fair */ + if (sched_disable_window_stats) + return; + + for_each_sched_entity(se) { + cfs_rq = cfs_rq_of(se); + dec_cfs_rq_hmp_stats(cfs_rq, p, change_cra); + if (cfs_rq_throttled(cfs_rq)) + break; + } + + /* Update rq->hmp_stats only if we didn't find any throttled cfs_rq */ + if (!se) + dec_rq_hmp_stats(rq, p, change_cra); +} + +static void inc_hmp_sched_stats_fair(struct rq *rq, struct task_struct *p) +{ + _inc_hmp_sched_stats_fair(rq, p, 1); +} + +static void dec_hmp_sched_stats_fair(struct rq *rq, struct task_struct *p) +{ + _dec_hmp_sched_stats_fair(rq, p, 1); +} + +static void fixup_hmp_sched_stats_fair(struct rq *rq, struct task_struct *p, + u32 new_task_load, u32 new_pred_demand) +{ + struct cfs_rq *cfs_rq; + struct sched_entity *se = &p->se; + s64 task_load_delta = (s64)new_task_load - task_load(p); + s64 pred_demand_delta = PRED_DEMAND_DELTA; + + for_each_sched_entity(se) { + cfs_rq = cfs_rq_of(se); + + fixup_cumulative_runnable_avg(&cfs_rq->hmp_stats, p, + task_load_delta, + pred_demand_delta); + fixup_nr_big_tasks(&cfs_rq->hmp_stats, p, task_load_delta); + if (cfs_rq_throttled(cfs_rq)) + break; + } + + /* Fix up rq->hmp_stats only if we didn't find any throttled cfs_rq */ + if (!se) { + fixup_cumulative_runnable_avg(&rq->hmp_stats, p, + task_load_delta, + pred_demand_delta); + fixup_nr_big_tasks(&rq->hmp_stats, p, task_load_delta); + } +} + +static int task_will_be_throttled(struct task_struct *p); + +#else /* CONFIG_CFS_BANDWIDTH */ + +inline void reset_cfs_rq_hmp_stats(int cpu, int reset_cra) { } + +static void +inc_hmp_sched_stats_fair(struct rq *rq, struct task_struct *p) +{ + inc_nr_big_task(&rq->hmp_stats, p); + inc_cumulative_runnable_avg(&rq->hmp_stats, p); +} + +static void +dec_hmp_sched_stats_fair(struct rq *rq, struct task_struct *p) +{ + dec_nr_big_task(&rq->hmp_stats, p); + dec_cumulative_runnable_avg(&rq->hmp_stats, p); +} +static void +fixup_hmp_sched_stats_fair(struct rq *rq, struct task_struct *p, + u32 new_task_load, u32 new_pred_demand) +{ + s64 task_load_delta = (s64)new_task_load - task_load(p); + s64 pred_demand_delta = PRED_DEMAND_DELTA; + + fixup_cumulative_runnable_avg(&rq->hmp_stats, p, task_load_delta, + pred_demand_delta); + fixup_nr_big_tasks(&rq->hmp_stats, p, task_load_delta); +} + +static inline int task_will_be_throttled(struct task_struct *p) +{ + return 0; +} + +void _inc_hmp_sched_stats_fair(struct rq *rq, + struct task_struct *p, int change_cra) +{ + inc_nr_big_task(&rq->hmp_stats, p); +} + +#endif /* CONFIG_CFS_BANDWIDTH */ + +/* + * Reset balance_interval at all sched_domain levels of given cpu, so that it + * honors kick. + */ +static inline void reset_balance_interval(int cpu) +{ + struct sched_domain *sd; + + if (cpu >= nr_cpu_ids) + return; + + rcu_read_lock(); + for_each_domain(cpu, sd) + sd->balance_interval = 0; + rcu_read_unlock(); +} + +/* + * Check if a task is on the "wrong" cpu (i.e its current cpu is not the ideal + * cpu as per its demand or priority) + * + * Returns reason why task needs to be migrated + */ +static inline int migration_needed(struct task_struct *p, int cpu) +{ + int nice; + struct related_thread_group *grp; + + if (p->state != TASK_RUNNING || p->nr_cpus_allowed == 1) + return 0; + + /* No need to migrate task that is about to be throttled */ + if (task_will_be_throttled(p)) + return 0; + + if (sched_boost_policy() == SCHED_BOOST_ON_BIG && + cpu_capacity(cpu) != max_capacity && task_sched_boost(p)) + return UP_MIGRATION; + + if (sched_cpu_high_irqload(cpu)) + return IRQLOAD_MIGRATION; + + nice = task_nice(p); + rcu_read_lock(); + grp = task_related_thread_group(p); + /* + * Don't assume higher capacity means higher power. If the task + * is running on the power efficient CPU, avoid migrating it + * to a lower capacity cluster. + */ + if (!grp && (nice > SCHED_UPMIGRATE_MIN_NICE || + upmigrate_discouraged(p)) && + cpu_capacity(cpu) > min_capacity && + cpu_max_power_cost(cpu) == max_power_cost) { + rcu_read_unlock(); + return DOWN_MIGRATION; + } + + if (!task_will_fit(p, cpu)) { + rcu_read_unlock(); + return UP_MIGRATION; + } + rcu_read_unlock(); + + return 0; +} + +static inline int +kick_active_balance(struct rq *rq, struct task_struct *p, int new_cpu) +{ + unsigned long flags; + int rc = 0; + + /* Invoke active balance to force migrate currently running task */ + raw_spin_lock_irqsave(&rq->lock, flags); + if (!rq->active_balance) { + rq->active_balance = 1; + rq->push_cpu = new_cpu; + get_task_struct(p); + rq->push_task = p; + rc = 1; + } + raw_spin_unlock_irqrestore(&rq->lock, flags); + + return rc; +} + +static DEFINE_RAW_SPINLOCK(migration_lock); + +static bool do_migration(int reason, int new_cpu, int cpu) +{ + if ((reason == UP_MIGRATION || reason == DOWN_MIGRATION) + && same_cluster(new_cpu, cpu)) + return false; + + /* Inter cluster high irqload migrations are OK */ + return new_cpu != cpu; +} + +/* + * Check if currently running task should be migrated to a better cpu. + * + * Todo: Effect this via changes to nohz_balancer_kick() and load balance? + */ +void check_for_migration(struct rq *rq, struct task_struct *p) +{ + int cpu = cpu_of(rq), new_cpu; + int active_balance = 0, reason; + + reason = migration_needed(p, cpu); + if (!reason) + return; + + raw_spin_lock(&migration_lock); + new_cpu = select_best_cpu(p, cpu, reason, 0); + + if (do_migration(reason, new_cpu, cpu)) { + active_balance = kick_active_balance(rq, p, new_cpu); + if (active_balance) + mark_reserved(new_cpu); + } + + raw_spin_unlock(&migration_lock); + + if (active_balance) + stop_one_cpu_nowait(cpu, active_load_balance_cpu_stop, rq, + &rq->active_balance_work); +} + +#ifdef CONFIG_CFS_BANDWIDTH + +static void init_cfs_rq_hmp_stats(struct cfs_rq *cfs_rq) +{ + cfs_rq->hmp_stats.nr_big_tasks = 0; + cfs_rq->hmp_stats.cumulative_runnable_avg = 0; + cfs_rq->hmp_stats.pred_demands_sum = 0; +} + +static void inc_cfs_rq_hmp_stats(struct cfs_rq *cfs_rq, + struct task_struct *p, int change_cra) +{ + inc_nr_big_task(&cfs_rq->hmp_stats, p); + if (change_cra) + inc_cumulative_runnable_avg(&cfs_rq->hmp_stats, p); +} + +static void dec_cfs_rq_hmp_stats(struct cfs_rq *cfs_rq, + struct task_struct *p, int change_cra) +{ + dec_nr_big_task(&cfs_rq->hmp_stats, p); + if (change_cra) + dec_cumulative_runnable_avg(&cfs_rq->hmp_stats, p); +} + +static void inc_throttled_cfs_rq_hmp_stats(struct hmp_sched_stats *stats, + struct cfs_rq *cfs_rq) +{ + stats->nr_big_tasks += cfs_rq->hmp_stats.nr_big_tasks; + stats->cumulative_runnable_avg += + cfs_rq->hmp_stats.cumulative_runnable_avg; + stats->pred_demands_sum += cfs_rq->hmp_stats.pred_demands_sum; +} + +static void dec_throttled_cfs_rq_hmp_stats(struct hmp_sched_stats *stats, + struct cfs_rq *cfs_rq) +{ + stats->nr_big_tasks -= cfs_rq->hmp_stats.nr_big_tasks; + stats->cumulative_runnable_avg -= + cfs_rq->hmp_stats.cumulative_runnable_avg; + stats->pred_demands_sum -= cfs_rq->hmp_stats.pred_demands_sum; + + BUG_ON(stats->nr_big_tasks < 0 || + (s64)stats->cumulative_runnable_avg < 0); + BUG_ON((s64)stats->pred_demands_sum < 0); +} + +#else /* CONFIG_CFS_BANDWIDTH */ + +static inline void inc_cfs_rq_hmp_stats(struct cfs_rq *cfs_rq, + struct task_struct *p, int change_cra) { } + +static inline void dec_cfs_rq_hmp_stats(struct cfs_rq *cfs_rq, + struct task_struct *p, int change_cra) { } + +#endif /* CONFIG_CFS_BANDWIDTH */ + +#else /* CONFIG_SCHED_HMP */ + +static inline void init_cfs_rq_hmp_stats(struct cfs_rq *cfs_rq) { } + +static inline void inc_cfs_rq_hmp_stats(struct cfs_rq *cfs_rq, + struct task_struct *p, int change_cra) { } + +static inline void dec_cfs_rq_hmp_stats(struct cfs_rq *cfs_rq, + struct task_struct *p, int change_cra) { } + +#define dec_throttled_cfs_rq_hmp_stats(...) +#define inc_throttled_cfs_rq_hmp_stats(...) + +#endif /* CONFIG_SCHED_HMP */ + #if (SCHED_LOAD_SHIFT - SCHED_LOAD_RESOLUTION) != 10 || SCHED_CAPACITY_SHIFT != 10 #error "load tracking assumes 2^10 as unit" #endif @@ -2600,6 +3855,7 @@ scale_freq = arch_scale_freq_capacity(NULL, cpu); scale_cpu = arch_scale_cpu_capacity(NULL, cpu); + trace_sched_contrib_scale_f(cpu, scale_freq, scale_cpu); /* delta_w is the amount already accumulated against our next period */ delta_w = sa->period_contrib; @@ -2658,6 +3914,7 @@ if (cfs_rq) cfs_rq->runnable_load_sum += weight * scaled_delta; } + if (running) sa->util_sum += scaled_delta * scale_cpu; @@ -2675,25 +3932,262 @@ return decayed; } -#ifdef CONFIG_FAIR_GROUP_SCHED /* - * Updating tg's load_avg is necessary before update_cfs_share (which is done) - * and effective_load (which is not done because it is too costly). + * Signed add and clamp on underflow. + * + * Explicitly do a load-store to ensure the intermediate value never hits + * memory. This allows lockless observations without ever seeing the negative + * values. + */ +#define add_positive(_ptr, _val) do { \ + typeof(_ptr) ptr = (_ptr); \ + typeof(_val) val = (_val); \ + typeof(*ptr) res, var = READ_ONCE(*ptr); \ + \ + res = var + val; \ + \ + if (val < 0 && res > var) \ + res = 0; \ + \ + WRITE_ONCE(*ptr, res); \ +} while (0) + +#ifdef CONFIG_FAIR_GROUP_SCHED +/** + * update_tg_load_avg - update the tg's load avg + * @cfs_rq: the cfs_rq whose avg changed + * @force: update regardless of how small the difference + * + * This function 'ensures': tg->load_avg := \Sum tg->cfs_rq[]->avg.load. + * However, because tg->load_avg is a global value there are performance + * considerations. + * + * In order to avoid having to look at the other cfs_rq's, we use a + * differential update where we store the last value we propagated. This in + * turn allows skipping updates if the differential is 'small'. + * + * Updating tg's load_avg is necessary before update_cfs_share() (which is + * done) and effective_load() (which is not done because it is too costly). */ static inline void update_tg_load_avg(struct cfs_rq *cfs_rq, int force) { long delta = cfs_rq->avg.load_avg - cfs_rq->tg_load_avg_contrib; + /* + * No need to update load_avg for root_task_group as it is not used. + */ + if (cfs_rq->tg == &root_task_group) + return; + if (force || abs(delta) > cfs_rq->tg_load_avg_contrib / 64) { atomic_long_add(delta, &cfs_rq->tg->load_avg); cfs_rq->tg_load_avg_contrib = cfs_rq->avg.load_avg; } } +/* + * Called within set_task_rq() right before setting a task's cpu. The + * caller only guarantees p->pi_lock is held; no other assumptions, + * including the state of rq->lock, should be made. + */ +void set_task_rq_fair(struct sched_entity *se, + struct cfs_rq *prev, struct cfs_rq *next) +{ + if (!sched_feat(ATTACH_AGE_LOAD)) + return; + + /* + * We are supposed to update the task to "current" time, then its up to + * date and ready to go to new CPU/cfs_rq. But we have difficulty in + * getting what current time is, so simply throw away the out-of-date + * time. This will result in the wakee task is less decayed, but giving + * the wakee more load sounds not bad. + */ + if (se->avg.last_update_time && prev) { + u64 p_last_update_time; + u64 n_last_update_time; + +#ifndef CONFIG_64BIT + u64 p_last_update_time_copy; + u64 n_last_update_time_copy; + + do { + p_last_update_time_copy = prev->load_last_update_time_copy; + n_last_update_time_copy = next->load_last_update_time_copy; + + smp_rmb(); + + p_last_update_time = prev->avg.last_update_time; + n_last_update_time = next->avg.last_update_time; + + } while (p_last_update_time != p_last_update_time_copy || + n_last_update_time != n_last_update_time_copy); +#else + p_last_update_time = prev->avg.last_update_time; + n_last_update_time = next->avg.last_update_time; +#endif + __update_load_avg(p_last_update_time, cpu_of(rq_of(prev)), + &se->avg, 0, 0, NULL); + se->avg.last_update_time = n_last_update_time; + } +} + +/* Take into account change of utilization of a child task group */ +static inline void +update_tg_cfs_util(struct cfs_rq *cfs_rq, struct sched_entity *se) +{ + struct cfs_rq *gcfs_rq = group_cfs_rq(se); + long delta = gcfs_rq->avg.util_avg - se->avg.util_avg; + + /* Nothing to update */ + if (!delta) + return; + + /* Set new sched_entity's utilization */ + se->avg.util_avg = gcfs_rq->avg.util_avg; + se->avg.util_sum = se->avg.util_avg * LOAD_AVG_MAX; + + /* Update parent cfs_rq utilization */ + add_positive(&cfs_rq->avg.util_avg, delta); + cfs_rq->avg.util_sum = cfs_rq->avg.util_avg * LOAD_AVG_MAX; +} + +/* Take into account change of load of a child task group */ +static inline void +update_tg_cfs_load(struct cfs_rq *cfs_rq, struct sched_entity *se) +{ + struct cfs_rq *gcfs_rq = group_cfs_rq(se); + long delta, load = gcfs_rq->avg.load_avg; + + /* + * If the load of group cfs_rq is null, the load of the + * sched_entity will also be null so we can skip the formula + */ + if (load) { + long tg_load; + + /* Get tg's load and ensure tg_load > 0 */ + tg_load = atomic_long_read(&gcfs_rq->tg->load_avg) + 1; + + /* Ensure tg_load >= load and updated with current load*/ + tg_load -= gcfs_rq->tg_load_avg_contrib; + tg_load += load; + + /* + * We need to compute a correction term in the case that the + * task group is consuming more CPU than a task of equal + * weight. A task with a weight equals to tg->shares will have + * a load less or equal to scale_load_down(tg->shares). + * Similarly, the sched_entities that represent the task group + * at parent level, can't have a load higher than + * scale_load_down(tg->shares). And the Sum of sched_entities' + * load must be <= scale_load_down(tg->shares). + */ + if (tg_load > scale_load_down(gcfs_rq->tg->shares)) { + /* scale gcfs_rq's load into tg's shares*/ + load *= scale_load_down(gcfs_rq->tg->shares); + load /= tg_load; + } + } + + delta = load - se->avg.load_avg; + + /* Nothing to update */ + if (!delta) + return; + + /* Set new sched_entity's load */ + se->avg.load_avg = load; + se->avg.load_sum = se->avg.load_avg * LOAD_AVG_MAX; + + /* Update parent cfs_rq load */ + add_positive(&cfs_rq->avg.load_avg, delta); + cfs_rq->avg.load_sum = cfs_rq->avg.load_avg * LOAD_AVG_MAX; + + /* + * If the sched_entity is already enqueued, we also have to update the + * runnable load avg. + */ + if (se->on_rq) { + /* Update parent cfs_rq runnable_load_avg */ + add_positive(&cfs_rq->runnable_load_avg, delta); + cfs_rq->runnable_load_sum = cfs_rq->runnable_load_avg * LOAD_AVG_MAX; + } +} + +static inline void set_tg_cfs_propagate(struct cfs_rq *cfs_rq) +{ + cfs_rq->propagate_avg = 1; +} + +static inline int test_and_clear_tg_cfs_propagate(struct sched_entity *se) +{ + struct cfs_rq *cfs_rq = group_cfs_rq(se); + + if (!cfs_rq->propagate_avg) + return 0; + + cfs_rq->propagate_avg = 0; + return 1; +} + +/* Update task and its cfs_rq load average */ +static inline int propagate_entity_load_avg(struct sched_entity *se) +{ + struct cfs_rq *cfs_rq; + + if (entity_is_task(se)) + return 0; + + if (!test_and_clear_tg_cfs_propagate(se)) + return 0; + + cfs_rq = cfs_rq_of(se); + + set_tg_cfs_propagate(cfs_rq); + + update_tg_cfs_util(cfs_rq, se); + update_tg_cfs_load(cfs_rq, se); + + return 1; +} + #else /* CONFIG_FAIR_GROUP_SCHED */ + static inline void update_tg_load_avg(struct cfs_rq *cfs_rq, int force) {} + +static inline int propagate_entity_load_avg(struct sched_entity *se) +{ + return 0; +} + +static inline void set_tg_cfs_propagate(struct cfs_rq *cfs_rq) {} + #endif /* CONFIG_FAIR_GROUP_SCHED */ +static inline void cfs_rq_util_change(struct cfs_rq *cfs_rq) +{ + if (&this_rq()->cfs == cfs_rq) { + /* + * There are a few boundary cases this might miss but it should + * get called often enough that that should (hopefully) not be + * a real problem -- added to that it only calls on the local + * CPU, so if we enqueue remotely we'll miss an update, but + * the next tick/schedule should update. + * + * It will not get called when we go idle, because the idle + * thread is a different class (!fair), nor will the utilization + * number include things like RT tasks. + * + * As is, the util number is not freq-invariant (we'd have to + * implement arch_scale_freq_capacity() for that). + * + * See cpu_util(). + */ + cpufreq_update_util(rq_of(cfs_rq), 0); + } +} + static inline u64 cfs_rq_clock_task(struct cfs_rq *cfs_rq); /* @@ -2713,23 +4207,43 @@ WRITE_ONCE(*ptr, res); \ } while (0) -/* Group cfs_rq's load_avg is used for task_h_load and update_cfs_share */ -static inline int update_cfs_rq_load_avg(u64 now, struct cfs_rq *cfs_rq) +/** + * update_cfs_rq_load_avg - update the cfs_rq's load/util averages + * @now: current time, as per cfs_rq_clock_task() + * @cfs_rq: cfs_rq to update + * @update_freq: should we call cfs_rq_util_change() or will the call do so + * + * The cfs_rq avg is the direct sum of all its entities (blocked and runnable) + * avg. The immediate corollary is that all (fair) tasks must be attached, see + * post_init_entity_util_avg(). + * + * cfs_rq->avg is used for task_h_load() and update_cfs_share() for example. + * + * Returns true if the load decayed or we removed load. + * + * Since both these conditions indicate a changed cfs_rq->avg.load we should + * call update_tg_load_avg() when this function returns true. + */ +static inline int +update_cfs_rq_load_avg(u64 now, struct cfs_rq *cfs_rq, bool update_freq) { struct sched_avg *sa = &cfs_rq->avg; - int decayed, removed = 0; + int decayed, removed = 0, removed_util = 0; if (atomic_long_read(&cfs_rq->removed_load_avg)) { s64 r = atomic_long_xchg(&cfs_rq->removed_load_avg, 0); sub_positive(&sa->load_avg, r); sub_positive(&sa->load_sum, r * LOAD_AVG_MAX); removed = 1; + set_tg_cfs_propagate(cfs_rq); } if (atomic_long_read(&cfs_rq->removed_util_avg)) { long r = atomic_long_xchg(&cfs_rq->removed_util_avg, 0); sub_positive(&sa->util_avg, r); sub_positive(&sa->util_sum, r * LOAD_AVG_MAX); + removed_util = 1; + set_tg_cfs_propagate(cfs_rq); } decayed = __update_load_avg(now, cpu_of(rq_of(cfs_rq)), sa, @@ -2740,65 +4254,93 @@ cfs_rq->load_last_update_time_copy = sa->last_update_time; #endif + /* Trace CPU load, unless cfs_rq belongs to a non-root task_group */ + if (cfs_rq == &rq_of(cfs_rq)->cfs) + trace_sched_load_avg_cpu(cpu_of(rq_of(cfs_rq)), cfs_rq); + + if (update_freq && (decayed || removed_util)) + cfs_rq_util_change(cfs_rq); + return decayed || removed; } +/* + * Optional action to be done while updating the load average + */ +#define UPDATE_TG 0x1 +#define SKIP_AGE_LOAD 0x2 + /* Update task and its cfs_rq load average */ -static inline void update_load_avg(struct sched_entity *se, int update_tg) +static inline void update_load_avg(struct sched_entity *se, int flags) { struct cfs_rq *cfs_rq = cfs_rq_of(se); u64 now = cfs_rq_clock_task(cfs_rq); int cpu = cpu_of(rq_of(cfs_rq)); + int decayed; + void *ptr = NULL; /* * Track task load average for carrying it to new CPU after migrated, and * track group sched_entity load average for task_h_load calc in migration */ + if (se->avg.last_update_time && !(flags & SKIP_AGE_LOAD)) { __update_load_avg(now, cpu, &se->avg, se->on_rq * scale_load_down(se->load.weight), cfs_rq->curr == se, NULL); - - if (update_cfs_rq_load_avg(now, cfs_rq) && update_tg) - update_tg_load_avg(cfs_rq, 0); } -static void attach_entity_load_avg(struct cfs_rq *cfs_rq, struct sched_entity *se) -{ - if (!sched_feat(ATTACH_AGE_LOAD)) - goto skip_aging; + decayed = update_cfs_rq_load_avg(now, cfs_rq, true); + decayed |= propagate_entity_load_avg(se); - /* - * If we got migrated (either between CPUs or between cgroups) we'll - * have aged the average right before clearing @last_update_time. - */ - if (se->avg.last_update_time) { - __update_load_avg(cfs_rq->avg.last_update_time, cpu_of(rq_of(cfs_rq)), - &se->avg, 0, 0, NULL); + if (decayed && (flags & UPDATE_TG)) + update_tg_load_avg(cfs_rq, 0); - /* - * XXX: we could have just aged the entire load away if we've been - * absent from the fair class for too long. - */ + if (entity_is_task(se)) { +#ifdef CONFIG_SCHED_WALT + ptr = (void *)&(task_of(se)->ravg); +#endif + trace_sched_load_avg_task(task_of(se), &se->avg, ptr); + } } -skip_aging: +/** + * attach_entity_load_avg - attach this entity to its cfs_rq load avg + * @cfs_rq: cfs_rq to attach to + * @se: sched_entity to attach + * + * Must call update_cfs_rq_load_avg() before this, since we rely on + * cfs_rq->avg.last_update_time being current. + */ +static void attach_entity_load_avg(struct cfs_rq *cfs_rq, struct sched_entity *se) +{ se->avg.last_update_time = cfs_rq->avg.last_update_time; cfs_rq->avg.load_avg += se->avg.load_avg; cfs_rq->avg.load_sum += se->avg.load_sum; cfs_rq->avg.util_avg += se->avg.util_avg; cfs_rq->avg.util_sum += se->avg.util_sum; + set_tg_cfs_propagate(cfs_rq); + + cfs_rq_util_change(cfs_rq); } +/** + * detach_entity_load_avg - detach this entity from its cfs_rq load avg + * @cfs_rq: cfs_rq to detach from + * @se: sched_entity to detach + * + * Must call update_cfs_rq_load_avg() before this, since we rely on + * cfs_rq->avg.last_update_time being current. + */ static void detach_entity_load_avg(struct cfs_rq *cfs_rq, struct sched_entity *se) { - __update_load_avg(cfs_rq->avg.last_update_time, cpu_of(rq_of(cfs_rq)), - &se->avg, se->on_rq * scale_load_down(se->load.weight), - cfs_rq->curr == se, NULL); sub_positive(&cfs_rq->avg.load_avg, se->avg.load_avg); sub_positive(&cfs_rq->avg.load_sum, se->avg.load_sum); sub_positive(&cfs_rq->avg.util_avg, se->avg.util_avg); sub_positive(&cfs_rq->avg.util_sum, se->avg.util_sum); + set_tg_cfs_propagate(cfs_rq); + + cfs_rq_util_change(cfs_rq); } /* Add the load generated by se into cfs_rq's load average */ @@ -2806,62 +4348,79 @@ enqueue_entity_load_avg(struct cfs_rq *cfs_rq, struct sched_entity *se) { struct sched_avg *sa = &se->avg; - u64 now = cfs_rq_clock_task(cfs_rq); - int migrated, decayed; - - migrated = !sa->last_update_time; - if (!migrated) { - __update_load_avg(now, cpu_of(rq_of(cfs_rq)), sa, - se->on_rq * scale_load_down(se->load.weight), - cfs_rq->curr == se, NULL); - } - - decayed = update_cfs_rq_load_avg(now, cfs_rq); cfs_rq->runnable_load_avg += sa->load_avg; cfs_rq->runnable_load_sum += sa->load_sum; - if (migrated) + if (!sa->last_update_time) { attach_entity_load_avg(cfs_rq, se); - - if (decayed || migrated) update_tg_load_avg(cfs_rq, 0); } +} /* Remove the runnable load generated by se from cfs_rq's runnable load average */ static inline void dequeue_entity_load_avg(struct cfs_rq *cfs_rq, struct sched_entity *se) { - update_load_avg(se, 1); - cfs_rq->runnable_load_avg = max_t(long, cfs_rq->runnable_load_avg - se->avg.load_avg, 0); cfs_rq->runnable_load_sum = max_t(s64, cfs_rq->runnable_load_sum - se->avg.load_sum, 0); } -/* - * Task first catches up with cfs_rq, and then subtract - * itself from the cfs_rq (task must be off the queue now). - */ -void remove_entity_load_avg(struct sched_entity *se) -{ - struct cfs_rq *cfs_rq = cfs_rq_of(se); - u64 last_update_time; - #ifndef CONFIG_64BIT +static inline u64 cfs_rq_last_update_time(struct cfs_rq *cfs_rq) +{ u64 last_update_time_copy; + u64 last_update_time; do { last_update_time_copy = cfs_rq->load_last_update_time_copy; smp_rmb(); last_update_time = cfs_rq->avg.last_update_time; } while (last_update_time != last_update_time_copy); + + return last_update_time; +} #else - last_update_time = cfs_rq->avg.last_update_time; +static inline u64 cfs_rq_last_update_time(struct cfs_rq *cfs_rq) +{ + return cfs_rq->avg.last_update_time; +} #endif +/* + * Synchronize entity load avg of dequeued entity without locking + * the previous rq. + */ +void sync_entity_load_avg(struct sched_entity *se) +{ + struct cfs_rq *cfs_rq = cfs_rq_of(se); + u64 last_update_time; + + last_update_time = cfs_rq_last_update_time(cfs_rq); __update_load_avg(last_update_time, cpu_of(rq_of(cfs_rq)), &se->avg, 0, 0, NULL); +} + +/* + * Task first catches up with cfs_rq, and then subtract + * itself from the cfs_rq (task must be off the queue now). + */ +void remove_entity_load_avg(struct sched_entity *se) +{ + struct cfs_rq *cfs_rq = cfs_rq_of(se); + + /* + * tasks cannot exit without having gone through wake_up_new_task() -> + * post_init_entity_util_avg() which will have added things to the + * cfs_rq, so we can remove unconditionally. + * + * Similarly for groups, they will have passed through + * post_init_entity_util_avg() before unregister_sched_fair_group() + * calls this. + */ + + sync_entity_load_avg(se); atomic_long_add(se->avg.load_avg, &cfs_rq->removed_load_avg); atomic_long_add(se->avg.util_avg, &cfs_rq->removed_util_avg); } @@ -2898,7 +4457,16 @@ #else /* CONFIG_SMP */ -static inline void update_load_avg(struct sched_entity *se, int update_tg) {} +static inline int +update_cfs_rq_load_avg(u64 now, struct cfs_rq *cfs_rq, bool update_freq) +{ + return 0; +} + +#define UPDATE_TG 0x0 +#define SKIP_AGE_LOAD 0x0 + +static inline void update_load_avg(struct sched_entity *se, int not_used1){} static inline void enqueue_entity_load_avg(struct cfs_rq *cfs_rq, struct sched_entity *se) {} static inline void @@ -2915,6 +4483,12 @@ return 0; } +static inline void inc_cfs_rq_hmp_stats(struct cfs_rq *cfs_rq, + struct task_struct *p, int change_cra) { } + +static inline void dec_cfs_rq_hmp_stats(struct cfs_rq *cfs_rq, + struct task_struct *p, int change_cra) { } + #endif /* CONFIG_SMP */ static void enqueue_sleeper(struct cfs_rq *cfs_rq, struct sched_entity *se) @@ -2962,6 +4536,7 @@ } trace_sched_stat_blocked(tsk, delta); + trace_sched_blocked_reason(tsk); /* * Blocking time is in units of nanosecs, so shift by @@ -3040,9 +4615,10 @@ * Update run-time statistics of the 'current'. */ update_curr(cfs_rq); + update_load_avg(se, UPDATE_TG); enqueue_entity_load_avg(cfs_rq, se); + update_cfs_shares(se); account_entity_enqueue(cfs_rq, se); - update_cfs_shares(cfs_rq); if (flags & ENQUEUE_WAKEUP) { place_entity(cfs_rq, se, 0); @@ -3115,6 +4691,16 @@ * Update run-time statistics of the 'current'. */ update_curr(cfs_rq); + + /* + * When dequeuing a sched_entity, we must: + * - Update loads to have both entity and cfs_rq synced with now. + * - Substract its load from the cfs_rq->runnable_avg. + * - Substract its previous weight from cfs_rq->load.weight. + * - For group entity, update its weight to reflect the new share + * of its group cfs_rq. + */ + update_load_avg(se, UPDATE_TG); dequeue_entity_load_avg(cfs_rq, se); update_stats_dequeue(cfs_rq, se); @@ -3150,7 +4736,7 @@ return_cfs_rq_runtime(cfs_rq); update_min_vruntime(cfs_rq); - update_cfs_shares(cfs_rq); + update_cfs_shares(se); } /* @@ -3205,7 +4791,7 @@ */ update_stats_wait_end(cfs_rq, se); __dequeue_entity(cfs_rq, se); - update_load_avg(se, 1); + update_load_avg(se, UPDATE_TG); } update_stats_curr_start(cfs_rq, se); @@ -3321,8 +4907,8 @@ /* * Ensure that runnable average is periodically updated. */ - update_load_avg(curr, 1); - update_cfs_shares(cfs_rq); + update_load_avg(curr, UPDATE_TG); + update_cfs_shares(curr); #ifdef CONFIG_SCHED_HRTICK /* @@ -3529,6 +5115,35 @@ return cfs_bandwidth_used() && cfs_rq->throttled; } +#ifdef CONFIG_SCHED_HMP +/* + * Check if task is part of a hierarchy where some cfs_rq does not have any + * runtime left. + * + * We can't rely on throttled_hierarchy() to do this test, as + * cfs_rq->throttle_count will not be updated yet when this function is called + * from scheduler_tick() + */ +static int task_will_be_throttled(struct task_struct *p) +{ + struct sched_entity *se = &p->se; + struct cfs_rq *cfs_rq; + + if (!cfs_bandwidth_used()) + return 0; + + for_each_sched_entity(se) { + cfs_rq = cfs_rq_of(se); + if (!cfs_rq->runtime_enabled) + continue; + if (cfs_rq->runtime_remaining <= 0) + return 1; + } + + return 0; +} +#endif + /* check whether cfs_rq, or any parent, is throttled */ static inline int throttled_hierarchy(struct cfs_rq *cfs_rq) { @@ -3608,13 +5223,16 @@ if (dequeue) dequeue_entity(qcfs_rq, se, DEQUEUE_SLEEP); qcfs_rq->h_nr_running -= task_delta; + dec_throttled_cfs_rq_hmp_stats(&qcfs_rq->hmp_stats, cfs_rq); if (qcfs_rq->load.weight) dequeue = 0; } - if (!se) + if (!se) { sub_nr_running(rq, task_delta); + dec_throttled_cfs_rq_hmp_stats(&rq->hmp_stats, cfs_rq); + } cfs_rq->throttled = 1; cfs_rq->throttled_clock = rq_clock(rq); @@ -3635,6 +5253,12 @@ start_cfs_bandwidth(cfs_b); raw_spin_unlock(&cfs_b->lock); + + /* Log effect on hmp stats after throttling */ + trace_sched_cpu_load_cgroup(rq, idle_cpu(cpu_of(rq)), + sched_irqload(cpu_of(rq)), + power_cost(cpu_of(rq), 0), + cpu_temp(cpu_of(rq))); } void unthrottle_cfs_rq(struct cfs_rq *cfs_rq) @@ -3644,6 +5268,7 @@ struct sched_entity *se; int enqueue = 1; long task_delta; + struct cfs_rq *tcfs_rq __maybe_unused = cfs_rq; se = cfs_rq->tg->se[cpu_of(rq)]; @@ -3671,17 +5296,26 @@ if (enqueue) enqueue_entity(cfs_rq, se, ENQUEUE_WAKEUP); cfs_rq->h_nr_running += task_delta; + inc_throttled_cfs_rq_hmp_stats(&cfs_rq->hmp_stats, tcfs_rq); if (cfs_rq_throttled(cfs_rq)) break; } - if (!se) + if (!se) { add_nr_running(rq, task_delta); + inc_throttled_cfs_rq_hmp_stats(&rq->hmp_stats, tcfs_rq); + } /* determine whether we need to wake up potentially idle cpu */ if (rq->curr == rq->idle && rq->cfs.nr_running) resched_curr(rq); + + /* Log effect on hmp stats after un-throttling */ + trace_sched_cpu_load_cgroup(rq, idle_cpu(cpu_of(rq)), + sched_irqload(cpu_of(rq)), + power_cost(cpu_of(rq), 0), + cpu_temp(cpu_of(rq))); } static u64 distribute_cfs_runtime(struct cfs_bandwidth *cfs_b, @@ -4022,6 +5656,7 @@ { cfs_rq->runtime_enabled = 0; INIT_LIST_HEAD(&cfs_rq->throttled_list); + init_cfs_rq_hmp_stats(cfs_rq); } void start_cfs_bandwidth(struct cfs_bandwidth *cfs_b) @@ -4137,7 +5772,7 @@ WARN_ON(task_rq(p) != rq); - if (cfs_rq->nr_running > 1) { + if (rq->cfs.h_nr_running > 1) { u64 slice = sched_slice(cfs_rq, se); u64 ran = se->sum_exec_runtime - se->prev_sum_exec_runtime; s64 delta = slice - ran; @@ -4153,8 +5788,7 @@ /* * called from enqueue/dequeue and updates the hrtick when the - * current task is from our class and nr_running is low enough - * to matter. + * current task is from our class. */ static void hrtick_update(struct rq *rq) { @@ -4163,7 +5797,6 @@ if (!hrtick_enabled(rq) || curr->sched_class != &fair_sched_class) return; - if (cfs_rq_of(&curr->se)->nr_running < sched_nr_latency) hrtick_start_fair(rq, curr); } #else /* !CONFIG_SCHED_HRTICK */ @@ -4177,6 +5810,14 @@ } #endif +#ifdef CONFIG_SMP +static bool __cpu_overutilized(int cpu, int delta); +static bool cpu_overutilized(int cpu); +unsigned long boosted_cpu_util(int cpu); +#else +#define boosted_cpu_util(cpu) cpu_util_freq(cpu) +#endif + /* * The enqueue_task method is called before nr_running is * increased. Here we update the fair scheduling stats and @@ -4187,6 +5828,17 @@ { struct cfs_rq *cfs_rq; struct sched_entity *se = &p->se; +#ifdef CONFIG_SMP + int task_new = flags & ENQUEUE_WAKEUP_NEW; +#endif + + /* + * If in_iowait is set, the code below may not trigger any cpufreq + * utilization updates, so do it here explicitly with the IOWAIT flag + * passed. + */ + if (p->in_iowait) + cpufreq_update_this_cpu(rq, SCHED_CPUFREQ_IOWAIT); for_each_sched_entity(se) { if (se->on_rq) @@ -4203,6 +5855,7 @@ if (cfs_rq_throttled(cfs_rq)) break; cfs_rq->h_nr_running++; + inc_cfs_rq_hmp_stats(cfs_rq, p, 1); flags = ENQUEUE_WAKEUP; } @@ -4210,17 +5863,50 @@ for_each_sched_entity(se) { cfs_rq = cfs_rq_of(se); cfs_rq->h_nr_running++; + inc_cfs_rq_hmp_stats(cfs_rq, p, 1); if (cfs_rq_throttled(cfs_rq)) break; - update_load_avg(se, 1); - update_cfs_shares(cfs_rq); + update_load_avg(se, UPDATE_TG); + update_cfs_shares(se); } - if (!se) + if (!se) { add_nr_running(rq, 1); + inc_rq_hmp_stats(rq, p, 1); + } + +#ifdef CONFIG_SMP + /* + * Update SchedTune accounting. + * + * We do it before updating the CPU capacity to ensure the + * boost value of the current task is accounted for in the + * selection of the OPP. + * + * We do it also in the case where we enqueue a throttled task; + * we could argue that a throttled task should not boost a CPU, + * however: + * a) properly implementing CPU boosting considering throttled + * tasks will increase a lot the complexity of the solution + * b) it's not easy to quantify the benefits introduced by + * such a more complex solution. + * Thus, for the time being we go for the simple solution and boost + * also for throttled RQs. + */ + schedtune_enqueue_task(p, cpu_of(rq)); + + if (energy_aware() && !se) { + if (!task_new && !rq->rd->overutilized && + cpu_overutilized(rq->cpu)) { + rq->rd->overutilized = true; + trace_sched_overutilized(true); + } + } + +#endif /* CONFIG_SMP */ hrtick_update(rq); } @@ -4250,6 +5936,7 @@ if (cfs_rq_throttled(cfs_rq)) break; cfs_rq->h_nr_running--; + dec_cfs_rq_hmp_stats(cfs_rq, p, 1); /* Don't dequeue parent if it has other entities besides us */ if (cfs_rq->load.weight) { @@ -4269,16 +5956,32 @@ for_each_sched_entity(se) { cfs_rq = cfs_rq_of(se); cfs_rq->h_nr_running--; + dec_cfs_rq_hmp_stats(cfs_rq, p, 1); if (cfs_rq_throttled(cfs_rq)) break; - update_load_avg(se, 1); - update_cfs_shares(cfs_rq); + update_load_avg(se, UPDATE_TG); + update_cfs_shares(se); } - if (!se) + if (!se) { sub_nr_running(rq, 1); + dec_rq_hmp_stats(rq, p, 1); + } + +#ifdef CONFIG_SMP + + /* + * Update SchedTune accounting + * + * We do it before updating the CPU capacity to ensure the + * boost value of the current task is accounted for in the + * selection of the OPP. + */ + schedtune_dequeue_task(p, cpu_of(rq)); + +#endif /* CONFIG_SMP */ hrtick_update(rq); } @@ -4506,15 +6209,6 @@ return max(rq->cpu_load[type-1], total); } -static unsigned long capacity_of(int cpu) -{ - return cpu_rq(cpu)->cpu_capacity; -} - -static unsigned long capacity_orig_of(int cpu) -{ - return cpu_rq(cpu)->cpu_capacity_orig; -} static unsigned long cpu_avg_load_per_task(int cpu) { @@ -4689,6 +6383,487 @@ #endif /* + * Returns the current capacity of cpu after applying both + * cpu and freq scaling. + */ +unsigned long capacity_curr_of(int cpu) +{ + return cpu_rq(cpu)->cpu_capacity_orig * + arch_scale_freq_capacity(NULL, cpu) + >> SCHED_CAPACITY_SHIFT; +} + +struct energy_env { + struct sched_group *sg_top; + struct sched_group *sg_cap; + int cap_idx; + int util_delta; + int src_cpu; + int dst_cpu; + int trg_cpu; + int energy; + int payoff; + struct task_struct *task; + struct { + int before; + int after; + int delta; + int diff; + } nrg; + struct { + int before; + int after; + int delta; + } cap; +}; + +static int cpu_util_wake(int cpu, struct task_struct *p); + +/* + * __cpu_norm_util() returns the cpu util relative to a specific capacity, + * i.e. it's busy ratio, in the range [0..SCHED_LOAD_SCALE], which is useful for + * energy calculations. + * + * Since util is a scale-invariant utilization defined as: + * + * util ~ (curr_freq/max_freq)*1024 * capacity_orig/1024 * running_time/time + * + * the normalized util can be found using the specific capacity. + * + * capacity = capacity_orig * curr_freq/max_freq + * + * norm_util = running_time/time ~ util/capacity + */ +static unsigned long __cpu_norm_util(unsigned long util, unsigned long capacity) +{ + if (util >= capacity) + return SCHED_CAPACITY_SCALE; + + return (util << SCHED_CAPACITY_SHIFT)/capacity; +} + +static unsigned long group_max_util(struct energy_env *eenv) +{ + unsigned long max_util = 0; + unsigned long util; + int cpu; + + for_each_cpu(cpu, sched_group_cpus(eenv->sg_cap)) { + util = cpu_util_wake(cpu, eenv->task); + + /* + * If we are looking at the target CPU specified by the eenv, + * then we should add the (estimated) utilization of the task + * assuming we will wake it up on that CPU. + */ + if (unlikely(cpu == eenv->trg_cpu)) + util += eenv->util_delta; + + max_util = max(max_util, util); + } + + return max_util; +} + +/* + * group_norm_util() returns the approximated group util relative to it's + * current capacity (busy ratio), in the range [0..SCHED_LOAD_SCALE], for use + * in energy calculations. + * + * Since task executions may or may not overlap in time in the group the true + * normalized util is between MAX(cpu_norm_util(i)) and SUM(cpu_norm_util(i)) + * when iterating over all CPUs in the group. + * The latter estimate is used as it leads to a more pessimistic energy + * estimate (more busy). + */ +static unsigned +long group_norm_util(struct energy_env *eenv, struct sched_group *sg) +{ + unsigned long capacity = sg->sge->cap_states[eenv->cap_idx].cap; + unsigned long util, util_sum = 0; + int cpu; + + for_each_cpu(cpu, sched_group_cpus(sg)) { + util = cpu_util_wake(cpu, eenv->task); + + /* + * If we are looking at the target CPU specified by the eenv, + * then we should add the (estimated) utilization of the task + * assuming we will wake it up on that CPU. + */ + if (unlikely(cpu == eenv->trg_cpu)) + util += eenv->util_delta; + + util_sum += __cpu_norm_util(util, capacity); + } + + return min_t(unsigned long, util_sum, SCHED_CAPACITY_SCALE); +} + +static int find_new_capacity(struct energy_env *eenv, + const struct sched_group_energy * const sge) +{ + int idx, max_idx = sge->nr_cap_states - 1; + unsigned long util = group_max_util(eenv); + + /* default is max_cap if we don't find a match */ + eenv->cap_idx = max_idx; + + for (idx = 0; idx < sge->nr_cap_states; idx++) { + if (sge->cap_states[idx].cap >= util) { + eenv->cap_idx = idx; + break; + } + } + + return eenv->cap_idx; +} + +static int group_idle_state(struct energy_env *eenv, struct sched_group *sg) +{ + int i, state = INT_MAX; + int src_in_grp, dst_in_grp; + long grp_util = 0; + + /* Find the shallowest idle state in the sched group. */ + for_each_cpu(i, sched_group_cpus(sg)) + state = min(state, idle_get_state_idx(cpu_rq(i))); + + /* Take non-cpuidle idling into account (active idle/arch_cpu_idle()) */ + state++; + + src_in_grp = cpumask_test_cpu(eenv->src_cpu, sched_group_cpus(sg)); + dst_in_grp = cpumask_test_cpu(eenv->dst_cpu, sched_group_cpus(sg)); + if (src_in_grp == dst_in_grp) { + /* both CPUs under consideration are in the same group or not in + * either group, migration should leave idle state the same. + */ + goto end; + } + + /* + * Try to estimate if a deeper idle state is + * achievable when we move the task. + */ + for_each_cpu(i, sched_group_cpus(sg)) { + grp_util += cpu_util_wake(i, eenv->task); + if (unlikely(i == eenv->trg_cpu)) + grp_util += eenv->util_delta; + } + + if (grp_util <= + ((long)sg->sgc->max_capacity * (int)sg->group_weight)) { + /* after moving, this group is at most partly + * occupied, so it should have some idle time. + */ + int max_idle_state_idx = sg->sge->nr_idle_states - 2; + int new_state = grp_util * max_idle_state_idx; + if (grp_util <= 0) + /* group will have no util, use lowest state */ + new_state = max_idle_state_idx + 1; + else { + /* for partially idle, linearly map util to idle + * states, excluding the lowest one. This does not + * correspond to the state we expect to enter in + * reality, but an indication of what might happen. + */ + new_state = min(max_idle_state_idx, (int) + (new_state / sg->sgc->max_capacity)); + new_state = max_idle_state_idx - new_state; + } + state = new_state; + } else { + /* After moving, the group will be fully occupied + * so assume it will not be idle at all. + */ + state = 0; + } +end: + return state; +} + +/* + * sched_group_energy(): Computes the absolute energy consumption of cpus + * belonging to the sched_group including shared resources shared only by + * members of the group. Iterates over all cpus in the hierarchy below the + * sched_group starting from the bottom working it's way up before going to + * the next cpu until all cpus are covered at all levels. The current + * implementation is likely to gather the same util statistics multiple times. + * This can probably be done in a faster but more complex way. + * Note: sched_group_energy() may fail when racing with sched_domain updates. + */ +static int sched_group_energy(struct energy_env *eenv) +{ + struct cpumask visit_cpus; + u64 total_energy = 0; + + WARN_ON(!eenv->sg_top->sge); + + cpumask_copy(&visit_cpus, sched_group_cpus(eenv->sg_top)); + + while (!cpumask_empty(&visit_cpus)) { + struct sched_group *sg_shared_cap = NULL; + int cpu = cpumask_first(&visit_cpus); + struct sched_domain *sd; + + /* + * Is the group utilization affected by cpus outside this + * sched_group? + */ + sd = rcu_dereference(per_cpu(sd_scs, cpu)); + + if (sd && sd->parent) + sg_shared_cap = sd->parent->groups; + + for_each_domain(cpu, sd) { + struct sched_group *sg = sd->groups; + + /* Has this sched_domain already been visited? */ + if (sd->child && group_first_cpu(sg) != cpu) + break; + + do { + unsigned long group_util; + int sg_busy_energy, sg_idle_energy; + int cap_idx, idle_idx; + + if (sg_shared_cap && sg_shared_cap->group_weight >= sg->group_weight) + eenv->sg_cap = sg_shared_cap; + else + eenv->sg_cap = sg; + + cap_idx = find_new_capacity(eenv, sg->sge); + + if (sg->group_weight == 1) { + /* Remove capacity of src CPU (before task move) */ + if (eenv->trg_cpu == eenv->src_cpu && + cpumask_test_cpu(eenv->src_cpu, sched_group_cpus(sg))) { + eenv->cap.before = sg->sge->cap_states[cap_idx].cap; + eenv->cap.delta -= eenv->cap.before; + } + /* Add capacity of dst CPU (after task move) */ + if (eenv->trg_cpu == eenv->dst_cpu && + cpumask_test_cpu(eenv->dst_cpu, sched_group_cpus(sg))) { + eenv->cap.after = sg->sge->cap_states[cap_idx].cap; + eenv->cap.delta += eenv->cap.after; + } + } + + idle_idx = group_idle_state(eenv, sg); + group_util = group_norm_util(eenv, sg); + + sg_busy_energy = (group_util * sg->sge->cap_states[cap_idx].power); + sg_idle_energy = ((SCHED_LOAD_SCALE-group_util) + * sg->sge->idle_states[idle_idx].power); + + total_energy += sg_busy_energy + sg_idle_energy; + + if (!sd->child) + cpumask_xor(&visit_cpus, &visit_cpus, sched_group_cpus(sg)); + + if (cpumask_equal(sched_group_cpus(sg), sched_group_cpus(eenv->sg_top))) + goto next_cpu; + + } while (sg = sg->next, sg != sd->groups); + } + + /* + * If we raced with hotplug and got an sd NULL-pointer; + * returning a wrong energy estimation is better than + * entering an infinite loop. + */ + if (cpumask_test_cpu(cpu, &visit_cpus)) + return -EINVAL; +next_cpu: + cpumask_clear_cpu(cpu, &visit_cpus); + continue; + } + + eenv->energy = total_energy >> SCHED_CAPACITY_SHIFT; + return 0; +} + +static inline bool cpu_in_sg(struct sched_group *sg, int cpu) +{ + return cpu != -1 && cpumask_test_cpu(cpu, sched_group_cpus(sg)); +} + +static inline unsigned long task_util(struct task_struct *p); + +/* + * energy_diff(): Estimate the energy impact of changing the utilization + * distribution. eenv specifies the change: utilisation amount, source, and + * destination cpu. Source or destination cpu may be -1 in which case the + * utilization is removed from or added to the system (e.g. task wake-up). If + * both are specified, the utilization is migrated. + */ +static inline int __energy_diff(struct energy_env *eenv) +{ + struct sched_domain *sd; + struct sched_group *sg; + int sd_cpu = -1, energy_before = 0, energy_after = 0; + int diff, margin; + + struct energy_env eenv_before = { + .util_delta = task_util(eenv->task), + .src_cpu = eenv->src_cpu, + .dst_cpu = eenv->dst_cpu, + .trg_cpu = eenv->src_cpu, + .nrg = { 0, 0, 0, 0}, + .cap = { 0, 0, 0 }, + .task = eenv->task, + }; + + if (eenv->src_cpu == eenv->dst_cpu) + return 0; + + sd_cpu = (eenv->src_cpu != -1) ? eenv->src_cpu : eenv->dst_cpu; + sd = rcu_dereference(per_cpu(sd_ea, sd_cpu)); + + if (!sd) + return 0; /* Error */ + + sg = sd->groups; + + do { + if (cpu_in_sg(sg, eenv->src_cpu) || cpu_in_sg(sg, eenv->dst_cpu)) { + eenv_before.sg_top = eenv->sg_top = sg; + + if (sched_group_energy(&eenv_before)) + return 0; /* Invalid result abort */ + energy_before += eenv_before.energy; + + /* Keep track of SRC cpu (before) capacity */ + eenv->cap.before = eenv_before.cap.before; + eenv->cap.delta = eenv_before.cap.delta; + + if (sched_group_energy(eenv)) + return 0; /* Invalid result abort */ + energy_after += eenv->energy; + } + } while (sg = sg->next, sg != sd->groups); + + eenv->nrg.before = energy_before; + eenv->nrg.after = energy_after; + eenv->nrg.diff = eenv->nrg.after - eenv->nrg.before; + eenv->payoff = 0; +#ifndef CONFIG_SCHED_TUNE + trace_sched_energy_diff(eenv->task, + eenv->src_cpu, eenv->dst_cpu, eenv->util_delta, + eenv->nrg.before, eenv->nrg.after, eenv->nrg.diff, + eenv->cap.before, eenv->cap.after, eenv->cap.delta, + eenv->nrg.delta, eenv->payoff); +#endif + /* + * Dead-zone margin preventing too many migrations. + */ + + margin = eenv->nrg.before >> 6; /* ~1.56% */ + + diff = eenv->nrg.after - eenv->nrg.before; + + eenv->nrg.diff = (abs(diff) < margin) ? 0 : eenv->nrg.diff; + + return eenv->nrg.diff; +} + +#ifdef CONFIG_SCHED_TUNE + +struct target_nrg schedtune_target_nrg; + +#ifdef CONFIG_CGROUP_SCHEDTUNE +extern bool schedtune_initialized; +#endif /* CONFIG_CGROUP_SCHEDTUNE */ + +/* + * System energy normalization + * Returns the normalized value, in the range [0..SCHED_CAPACITY_SCALE], + * corresponding to the specified energy variation. + */ +static inline int +normalize_energy(int energy_diff) +{ + u32 normalized_nrg; + +#ifdef CONFIG_CGROUP_SCHEDTUNE + /* during early setup, we don't know the extents */ + if (unlikely(!schedtune_initialized)) + return energy_diff < 0 ? -1 : 1 ; +#endif /* CONFIG_CGROUP_SCHEDTUNE */ + +#ifdef CONFIG_SCHED_DEBUG + { + int max_delta; + + /* Check for boundaries */ + max_delta = schedtune_target_nrg.max_power; + max_delta -= schedtune_target_nrg.min_power; + WARN_ON(abs(energy_diff) >= max_delta); + } +#endif + + /* Do scaling using positive numbers to increase the range */ + normalized_nrg = (energy_diff < 0) ? -energy_diff : energy_diff; + + /* Scale by energy magnitude */ + normalized_nrg <<= SCHED_CAPACITY_SHIFT; + + /* Normalize on max energy for target platform */ + normalized_nrg = reciprocal_divide( + normalized_nrg, schedtune_target_nrg.rdiv); + + return (energy_diff < 0) ? -normalized_nrg : normalized_nrg; +} + +static inline int +energy_diff(struct energy_env *eenv) +{ + int boost = schedtune_task_boost(eenv->task); + int nrg_delta; + + /* Conpute "absolute" energy diff */ + __energy_diff(eenv); + + /* Return energy diff when boost margin is 0 */ + if (boost == 0) { + trace_sched_energy_diff(eenv->task, + eenv->src_cpu, eenv->dst_cpu, eenv->util_delta, + eenv->nrg.before, eenv->nrg.after, eenv->nrg.diff, + eenv->cap.before, eenv->cap.after, eenv->cap.delta, + 0, -eenv->nrg.diff); + return eenv->nrg.diff; + } + + /* Compute normalized energy diff */ + nrg_delta = normalize_energy(eenv->nrg.diff); + eenv->nrg.delta = nrg_delta; + + eenv->payoff = schedtune_accept_deltas( + eenv->nrg.delta, + eenv->cap.delta, + eenv->task); + + trace_sched_energy_diff(eenv->task, + eenv->src_cpu, eenv->dst_cpu, eenv->util_delta, + eenv->nrg.before, eenv->nrg.after, eenv->nrg.diff, + eenv->cap.before, eenv->cap.after, eenv->cap.delta, + eenv->nrg.delta, eenv->payoff); + + /* + * When SchedTune is enabled, the energy_diff() function will return + * the computed energy payoff value. Since the energy_diff() return + * value is expected to be negative by its callers, this evaluation + * function return a negative value each time the evaluation return a + * positive payoff, which is the condition for the acceptance of + * a scheduling decision + */ + return -eenv->payoff; +} +#else /* CONFIG_SCHED_TUNE */ +#define energy_diff(eenv) __energy_diff(eenv) +#endif + +/* * Detect M:N waker/wakee relationships via a switching-frequency heuristic. * A waker of many should wake a different task than the one last awakened * at a frequency roughly N times higher than one of its wakees. In order @@ -4700,31 +6875,34 @@ * being client/server, worker/dispatcher, interrupt source or whatever is * irrelevant, spread criteria is apparent partner count exceeds socket size. */ -static int wake_wide(struct task_struct *p) +static int wake_wide(struct task_struct *p, int sibling_count_hint) { unsigned int master = current->wakee_flips; unsigned int slave = p->wakee_flips; - int factor = this_cpu_read(sd_llc_size); + int llc_size = this_cpu_read(sd_llc_size); + + if (sibling_count_hint >= llc_size) + return 1; if (master < slave) swap(master, slave); - if (slave < factor || master < slave * factor) + if (slave < llc_size || master < slave * llc_size) return 0; return 1; } -static int wake_affine(struct sched_domain *sd, struct task_struct *p, int sync) +static int wake_affine(struct sched_domain *sd, struct task_struct *p, + int prev_cpu, int sync) { s64 this_load, load; s64 this_eff_load, prev_eff_load; - int idx, this_cpu, prev_cpu; + int idx, this_cpu; struct task_group *tg; unsigned long weight; int balanced; idx = sd->wake_idx; this_cpu = smp_processor_id(); - prev_cpu = task_cpu(p); load = source_load(prev_cpu, idx); this_load = target_load(this_cpu, idx); @@ -4779,16 +6957,160 @@ return 1; } +static inline unsigned long task_util(struct task_struct *p) +{ + return p->se.avg.util_avg; +} + +static inline unsigned long boosted_task_util(struct task_struct *task); + +static inline bool __task_fits(struct task_struct *p, int cpu, int util) +{ + unsigned long capacity = capacity_of(cpu); + + util += boosted_task_util(p); + + return (capacity * 1024) > (util * capacity_margin); +} + +static inline bool task_fits_max(struct task_struct *p, int cpu) +{ + unsigned long capacity = capacity_of(cpu); + unsigned long max_capacity = cpu_rq(cpu)->rd->max_cpu_capacity.val; + + if (capacity == max_capacity) + return true; + + if (capacity * capacity_margin > max_capacity * 1024) + return true; + + return __task_fits(p, cpu, 0); +} + +static bool __cpu_overutilized(int cpu, int delta) +{ + return (capacity_of(cpu) * 1024) < ((cpu_util(cpu) + delta) * capacity_margin); +} + +static bool cpu_overutilized(int cpu) +{ + return __cpu_overutilized(cpu, 0); +} + +#ifdef CONFIG_SCHED_TUNE + +struct reciprocal_value schedtune_spc_rdiv; + +static long +schedtune_margin(unsigned long signal, long boost) +{ + long long margin = 0; + + /* + * Signal proportional compensation (SPC) + * + * The Boost (B) value is used to compute a Margin (M) which is + * proportional to the complement of the original Signal (S): + * M = B * (SCHED_CAPACITY_SCALE - S) + * The obtained M could be used by the caller to "boost" S. + */ + if (boost >= 0) { + margin = SCHED_CAPACITY_SCALE - signal; + margin *= boost; + } else + margin = -signal * boost; + + margin = reciprocal_divide(margin, schedtune_spc_rdiv); + + if (boost < 0) + margin *= -1; + return margin; +} + +static inline int +schedtune_cpu_margin(unsigned long util, int cpu) +{ + int boost = schedtune_cpu_boost(cpu); + + if (boost == 0) + return 0; + + return schedtune_margin(util, boost); +} + +static inline long +schedtune_task_margin(struct task_struct *task) +{ + int boost = schedtune_task_boost(task); + unsigned long util; + long margin; + + if (boost == 0) + return 0; + + util = task_util(task); + margin = schedtune_margin(util, boost); + + return margin; +} + +#else /* CONFIG_SCHED_TUNE */ + +static inline int +schedtune_cpu_margin(unsigned long util, int cpu) +{ + return 0; +} + +static inline int +schedtune_task_margin(struct task_struct *task) +{ + return 0; +} + +#endif /* CONFIG_SCHED_TUNE */ + +unsigned long +boosted_cpu_util(int cpu) +{ + unsigned long util = cpu_util_freq(cpu); + long margin = schedtune_cpu_margin(util, cpu); + + trace_sched_boost_cpu(cpu, util, margin); + + return util + margin; +} + +static inline unsigned long +boosted_task_util(struct task_struct *task) +{ + unsigned long util = task_util(task); + long margin = schedtune_task_margin(task); + + trace_sched_boost_task(task, util, margin); + + return util + margin; +} + +static unsigned long capacity_spare_wake(int cpu, struct task_struct *p) +{ + return capacity_orig_of(cpu) - cpu_util_wake(cpu, p); +} + /* * find_idlest_group finds and returns the least busy CPU group within the * domain. + * + * Assumes p is allowed on at least one CPU in sd. */ static struct sched_group * find_idlest_group(struct sched_domain *sd, struct task_struct *p, int this_cpu, int sd_flag) { struct sched_group *idlest = NULL, *group = sd->groups; - unsigned long min_load = ULONG_MAX, this_load = 0; + struct sched_group *most_spare_sg = NULL; + unsigned long min_load = ULONG_MAX, this_load = ULONG_MAX; + unsigned long most_spare = 0, this_spare = 0; int load_idx = sd->forkexec_idx; int imbalance = 100 + (sd->imbalance_pct-100)/2; @@ -4796,7 +7118,7 @@ load_idx = sd->wake_idx; do { - unsigned long load, avg_load; + unsigned long load, avg_load, spare_cap, max_spare_cap; int local_group; int i; @@ -4808,8 +7130,12 @@ local_group = cpumask_test_cpu(this_cpu, sched_group_cpus(group)); - /* Tally up the load of all CPUs in the group */ + /* + * Tally up the load of all CPUs in the group and find + * the group containing the CPU with most spare capacity. + */ avg_load = 0; + max_spare_cap = 0; for_each_cpu(i, sched_group_cpus(group)) { /* Bias balancing toward cpus of our domain */ @@ -4819,6 +7145,11 @@ load = target_load(i, load_idx); avg_load += load; + + spare_cap = capacity_spare_wake(i, p); + + if (spare_cap > max_spare_cap) + max_spare_cap = spare_cap; } /* Adjust by relative CPU capacity of the group */ @@ -4826,22 +7157,51 @@ if (local_group) { this_load = avg_load; - } else if (avg_load < min_load) { + this_spare = max_spare_cap; + } else { + if (avg_load < min_load) { min_load = avg_load; idlest = group; } + + if (most_spare < max_spare_cap) { + most_spare = max_spare_cap; + most_spare_sg = group; + } + } } while (group = group->next, group != sd->groups); + /* + * The cross-over point between using spare capacity or least load + * is too conservative for high utilization tasks on partially + * utilized systems if we require spare_capacity > task_util(p), + * so we allow for some task stuffing by using + * spare_capacity > task_util(p)/2. + * + * Spare capacity can't be used for fork because the utilization has + * not been set yet, we must first select a rq to compute the initial + * utilization. + */ + if (sd_flag & SD_BALANCE_FORK) + goto skip_spare; + + if (this_spare > task_util(p) / 2 && + imbalance*this_spare > 100*most_spare) + return NULL; + else if (most_spare > task_util(p) / 2) + return most_spare_sg; + +skip_spare: if (!idlest || 100*this_load < imbalance*min_load) return NULL; return idlest; } /* - * find_idlest_cpu - find the idlest cpu among the cpus in group. + * find_idlest_group_cpu - find the idlest cpu among the cpus in group. */ static int -find_idlest_cpu(struct sched_group *group, struct task_struct *p, int this_cpu) +find_idlest_group_cpu(struct sched_group *group, struct task_struct *p, int this_cpu) { unsigned long load, min_load = ULONG_MAX; unsigned int min_exit_latency = UINT_MAX; @@ -4850,6 +7210,10 @@ int shallowest_idle_cpu = -1; int i; + /* Check if we have any choice: */ + if (group->group_weight == 1) + return cpumask_first(sched_group_cpus(group)); + /* Traverse only the allowed CPUs */ for_each_cpu_and(i, sched_group_cpus(group), tsk_cpus_allowed(p)) { if (idle_cpu(i)) { @@ -4886,23 +7250,102 @@ return shallowest_idle_cpu != -1 ? shallowest_idle_cpu : least_loaded_cpu; } +static inline int find_idlest_cpu(struct sched_domain *sd, struct task_struct *p, + int cpu, int prev_cpu, int sd_flag) +{ + int new_cpu = cpu; + int wu = sd_flag & SD_BALANCE_WAKE; + int cas_cpu = -1; + + if (wu) { + schedstat_inc(p, se.statistics.nr_wakeups_cas_attempts); + schedstat_inc(this_rq(), eas_stats.cas_attempts); + } + + if (!cpumask_intersects(sched_domain_span(sd), &p->cpus_allowed)) + return prev_cpu; + + while (sd) { + struct sched_group *group; + struct sched_domain *tmp; + int weight; + + if (wu) + schedstat_inc(sd, eas_stats.cas_attempts); + + if (!(sd->flags & sd_flag)) { + sd = sd->child; + continue; + } + + group = find_idlest_group(sd, p, cpu, sd_flag); + if (!group) { + sd = sd->child; + continue; + } + + new_cpu = find_idlest_group_cpu(group, p, cpu); + if (new_cpu == cpu) { + /* Now try balancing at a lower domain level of cpu */ + sd = sd->child; + continue; + } + + /* Now try balancing at a lower domain level of new_cpu */ + cpu = cas_cpu = new_cpu; + weight = sd->span_weight; + sd = NULL; + for_each_domain(cpu, tmp) { + if (weight <= tmp->span_weight) + break; + if (tmp->flags & sd_flag) + sd = tmp; + } + /* while loop will break here if sd == NULL */ + } + + if (wu && (cas_cpu >= 0)) { + schedstat_inc(p, se.statistics.nr_wakeups_cas_count); + schedstat_inc(this_rq(), eas_stats.cas_count); + } + + return new_cpu; +} + /* * Try and locate an idle CPU in the sched_domain. */ -static int select_idle_sibling(struct task_struct *p, int target) +static int select_idle_sibling(struct task_struct *p, int prev, int target) { struct sched_domain *sd; struct sched_group *sg; - int i = task_cpu(p); - - if (idle_cpu(target)) + int best_idle_cpu = -1; + int best_idle_cstate = INT_MAX; + unsigned long best_idle_capacity = ULONG_MAX; + + schedstat_inc(p, se.statistics.nr_wakeups_sis_attempts); + schedstat_inc(this_rq(), eas_stats.sis_attempts); + + if (!sysctl_sched_cstate_aware) { + if (idle_cpu(target)) { + schedstat_inc(p, se.statistics.nr_wakeups_sis_idle); + schedstat_inc(this_rq(), eas_stats.sis_idle); return target; + } /* * If the prevous cpu is cache affine and idle, don't be stupid. */ - if (i != target && cpus_share_cache(i, target) && idle_cpu(i)) - return i; + if (prev != target && cpus_share_cache(prev, target) && idle_cpu(prev)) { + schedstat_inc(p, se.statistics.nr_wakeups_sis_cache_affine); + schedstat_inc(this_rq(), eas_stats.sis_cache_affine); + return prev; + } + } + + if (!(current->flags & PF_WAKE_UP_IDLE) && + !(p->flags & PF_WAKE_UP_IDLE)) + return target; /* * Otherwise, iterate the domains and find an elegible idle cpu. @@ -4911,10 +7354,35 @@ for_each_lower_domain(sd) { sg = sd->groups; do { + int i; if (!cpumask_intersects(sched_group_cpus(sg), tsk_cpus_allowed(p))) goto next; + if (sysctl_sched_cstate_aware) { + for_each_cpu_and(i, tsk_cpus_allowed(p), sched_group_cpus(sg)) { + int idle_idx = idle_get_state_idx(cpu_rq(i)); + unsigned long new_usage = boosted_task_util(p); + unsigned long capacity_orig = capacity_orig_of(i); + + if (new_usage > capacity_orig || !idle_cpu(i)) + goto next; + + if (i == target && new_usage <= capacity_curr_of(target)) { + schedstat_inc(p, se.statistics.nr_wakeups_sis_suff_cap); + schedstat_inc(this_rq(), eas_stats.sis_suff_cap); + schedstat_inc(sd, eas_stats.sis_suff_cap); + return target; + } + + if (idle_idx < best_idle_cstate && + capacity_orig <= best_idle_capacity) { + best_idle_cpu = i; + best_idle_cstate = idle_idx; + best_idle_capacity = capacity_orig; + } + } + } else { for_each_cpu(i, sched_group_cpus(sg)) { if (i == target || !idle_cpu(i)) goto next; @@ -4922,49 +7390,465 @@ target = cpumask_first_and(sched_group_cpus(sg), tsk_cpus_allowed(p)); + schedstat_inc(p, se.statistics.nr_wakeups_sis_idle_cpu); + schedstat_inc(this_rq(), eas_stats.sis_idle_cpu); + schedstat_inc(sd, eas_stats.sis_idle_cpu); goto done; + } next: sg = sg->next; } while (sg != sd->groups); } + + if (best_idle_cpu >= 0) + target = best_idle_cpu; + done: + schedstat_inc(p, se.statistics.nr_wakeups_sis_count); + schedstat_inc(this_rq(), eas_stats.sis_count); + return target; } /* - * cpu_util returns the amount of capacity of a CPU that is used by CFS - * tasks. The unit of the return value must be the one of capacity so we can - * compare the utilization with the capacity of the CPU that is available for - * CFS task (ie cpu_capacity). - * - * cfs_rq.avg.util_avg is the sum of running time of runnable tasks plus the - * recent utilization of currently non-runnable tasks on a CPU. It represents - * the amount of utilization of a CPU in the range [0..capacity_orig] where - * capacity_orig is the cpu_capacity available at the highest frequency - * (arch_scale_freq_capacity()). - * The utilization of a CPU converges towards a sum equal to or less than the - * current capacity (capacity_curr <= capacity_orig) of the CPU because it is - * the running time on this CPU scaled by capacity_curr. - * - * Nevertheless, cfs_rq.avg.util_avg can be higher than capacity_curr or even - * higher than capacity_orig because of unfortunate rounding in - * cfs.avg.util_avg or just after migrating tasks and new task wakeups until - * the average stabilizes with the new running time. We need to check that the - * utilization stays within the range of [0..capacity_orig] and cap it if - * necessary. Without utilization capping, a group could be seen as overloaded - * (CPU0 utilization at 121% + CPU1 utilization at 80%) whereas CPU1 has 20% of - * available capacity. We allow utilization to overshoot capacity_curr (but not - * capacity_orig) as it useful for predicting the capacity required after task - * migrations (scheduler-driven DVFS). + * cpu_util_wake: Compute cpu utilization with any contributions from + * the waking task p removed. check_for_migration() looks for a better CPU of + * rq->curr. For that case we should return cpu util with contributions from + * currently running task p removed. */ -static int cpu_util(int cpu) +static int cpu_util_wake(int cpu, struct task_struct *p) { - unsigned long util = cpu_rq(cpu)->cfs.avg.util_avg; - unsigned long capacity = capacity_orig_of(cpu); + unsigned long util, capacity; + +#ifdef CONFIG_SCHED_WALT + /* + * WALT does not decay idle tasks in the same manner + * as PELT, so it makes little sense to subtract task + * utilization from cpu utilization. Instead just use + * cpu_util for this case. + */ + if (!walt_disabled && sysctl_sched_use_walt_cpu_util && + p->state == TASK_WAKING) + return cpu_util(cpu); +#endif + /* Task has no contribution or is new */ + if (cpu != task_cpu(p) || !p->se.avg.last_update_time) + return cpu_util(cpu); + + capacity = capacity_orig_of(cpu); + util = max_t(long, cpu_util(cpu) - task_util(p), 0); return (util >= capacity) ? capacity : util; } +static int start_cpu(bool boosted) +{ + struct root_domain *rd = cpu_rq(smp_processor_id())->rd; + + return boosted ? rd->max_cap_orig_cpu : rd->min_cap_orig_cpu; +} + +static inline int find_best_target(struct task_struct *p, int *backup_cpu, + bool boosted, bool prefer_idle) +{ + unsigned long best_idle_min_cap_orig = ULONG_MAX; + unsigned long min_util = boosted_task_util(p); + unsigned long target_capacity = ULONG_MAX; + unsigned long min_wake_util = ULONG_MAX; + unsigned long target_max_spare_cap = 0; + unsigned long best_active_util = ULONG_MAX; + int best_idle_cstate = INT_MAX; + struct sched_domain *sd; + struct sched_group *sg; + int best_active_cpu = -1; + int best_idle_cpu = -1; + int target_cpu = -1; + int cpu, i; + + *backup_cpu = -1; + + schedstat_inc(p, se.statistics.nr_wakeups_fbt_attempts); + schedstat_inc(this_rq(), eas_stats.fbt_attempts); + + /* Find start CPU based on boost value */ + cpu = start_cpu(boosted); + if (cpu < 0) { + schedstat_inc(p, se.statistics.nr_wakeups_fbt_no_cpu); + schedstat_inc(this_rq(), eas_stats.fbt_no_cpu); + return -1; + } + + /* Find SD for the start CPU */ + sd = rcu_dereference(per_cpu(sd_ea, cpu)); + if (!sd) { + schedstat_inc(p, se.statistics.nr_wakeups_fbt_no_sd); + schedstat_inc(this_rq(), eas_stats.fbt_no_sd); + return -1; + } + + /* Scan CPUs in all SDs */ + sg = sd->groups; + do { + for_each_cpu_and(i, tsk_cpus_allowed(p), sched_group_cpus(sg)) { + unsigned long capacity_curr = capacity_curr_of(i); + unsigned long capacity_orig = capacity_orig_of(i); + unsigned long wake_util, new_util; + + if (!cpu_online(i)) + continue; + + if (walt_cpu_high_irqload(i)) + continue; + + /* + * p's blocked utilization is still accounted for on prev_cpu + * so prev_cpu will receive a negative bias due to the double + * accounting. However, the blocked utilization may be zero. + */ + wake_util = cpu_util_wake(i, p); + new_util = wake_util + task_util(p); + + /* + * Ensure minimum capacity to grant the required boost. + * The target CPU can be already at a capacity level higher + * than the one required to boost the task. + */ + new_util = max(min_util, new_util); + if (new_util > capacity_orig) + continue; + + /* + * Case A) Latency sensitive tasks + * + * Unconditionally favoring tasks that prefer idle CPU to + * improve latency. + * + * Looking for: + * - an idle CPU, whatever its idle_state is, since + * the first CPUs we explore are more likely to be + * reserved for latency sensitive tasks. + * - a non idle CPU where the task fits in its current + * capacity and has the maximum spare capacity. + * - a non idle CPU with lower contention from other + * tasks and running at the lowest possible OPP. + * + * The last two goals tries to favor a non idle CPU + * where the task can run as if it is "almost alone". + * A maximum spare capacity CPU is favoured since + * the task already fits into that CPU's capacity + * without waiting for an OPP chance. + * + * The following code path is the only one in the CPUs + * exploration loop which is always used by + * prefer_idle tasks. It exits the loop with wither a + * best_active_cpu or a target_cpu which should + * represent an optimal choice for latency sensitive + * tasks. + */ + if (prefer_idle) { + + /* + * Case A.1: IDLE CPU + * Return the first IDLE CPU we find. + */ + if (idle_cpu(i)) { + schedstat_inc(p, se.statistics.nr_wakeups_fbt_pref_idle); + schedstat_inc(this_rq(), eas_stats.fbt_pref_idle); + + trace_sched_find_best_target(p, + prefer_idle, min_util, + cpu, best_idle_cpu, + best_active_cpu, i); + + return i; + } + + /* + * Case A.2: Target ACTIVE CPU + * Favor CPUs with max spare capacity. + */ + if ((capacity_curr > new_util) && + (capacity_orig - new_util > target_max_spare_cap)) { + target_max_spare_cap = capacity_orig - new_util; + target_cpu = i; + continue; + } + if (target_cpu != -1) + continue; + + + /* + * Case A.3: Backup ACTIVE CPU + * Favor CPUs with: + * - lower utilization due to other tasks + * - lower utilization with the task in + */ + if (wake_util > min_wake_util) + continue; + if (new_util > best_active_util) + continue; + min_wake_util = wake_util; + best_active_util = new_util; + best_active_cpu = i; + continue; + } + + /* + * Enforce EAS mode + * + * For non latency sensitive tasks, skip CPUs that + * will be overutilized by moving the task there. + * + * The goal here is to remain in EAS mode as long as + * possible at least for !prefer_idle tasks. + */ + if ((new_util * capacity_margin) > + (capacity_orig * SCHED_CAPACITY_SCALE)) + continue; + + /* + * Case B) Non latency sensitive tasks on IDLE CPUs. + * + * Find an optimal backup IDLE CPU for non latency + * sensitive tasks. + * + * Looking for: + * - minimizing the capacity_orig, + * i.e. preferring LITTLE CPUs + * - favoring shallowest idle states + * i.e. avoid to wakeup deep-idle CPUs + * + * The following code path is used by non latency + * sensitive tasks if IDLE CPUs are available. If at + * least one of such CPUs are available it sets the + * best_idle_cpu to the most suitable idle CPU to be + * selected. + * + * If idle CPUs are available, favour these CPUs to + * improve performances by spreading tasks. + * Indeed, the energy_diff() computed by the caller + * will take care to ensure the minimization of energy + * consumptions without affecting performance. + */ + if (idle_cpu(i)) { + int idle_idx = idle_get_state_idx(cpu_rq(i)); + + /* Select idle CPU with lower cap_orig */ + if (capacity_orig > best_idle_min_cap_orig) + continue; + + /* + * Skip CPUs in deeper idle state, but only + * if they are also less energy efficient. + * IOW, prefer a deep IDLE LITTLE CPU vs a + * shallow idle big CPU. + */ + if (sysctl_sched_cstate_aware && + best_idle_cstate <= idle_idx) + continue; + + /* Keep track of best idle CPU */ + best_idle_min_cap_orig = capacity_orig; + best_idle_cstate = idle_idx; + best_idle_cpu = i; + continue; + } + + /* + * Case C) Non latency sensitive tasks on ACTIVE CPUs. + * + * Pack tasks in the most energy efficient capacities. + * + * This task packing strategy prefers more energy + * efficient CPUs (i.e. pack on smaller maximum + * capacity CPUs) while also trying to spread tasks to + * run them all at the lower OPP. + * + * This assumes for example that it's more energy + * efficient to run two tasks on two CPUs at a lower + * OPP than packing both on a single CPU but running + * that CPU at an higher OPP. + * + * Thus, this case keep track of the CPU with the + * smallest maximum capacity and highest spare maximum + * capacity. + */ + + /* Favor CPUs with smaller capacity */ + if (capacity_orig > target_capacity) + continue; + + /* Favor CPUs with maximum spare capacity */ + if ((capacity_orig - new_util) < target_max_spare_cap) + continue; + + target_max_spare_cap = capacity_orig - new_util; + target_capacity = capacity_orig; + target_cpu = i; + } + + } while (sg = sg->next, sg != sd->groups); + + /* + * For non latency sensitive tasks, cases B and C in the previous loop, + * we pick the best IDLE CPU only if we was not able to find a target + * ACTIVE CPU. + * + * Policies priorities: + * + * - prefer_idle tasks: + * + * a) IDLE CPU available, we return immediately + * b) ACTIVE CPU where task fits and has the bigger maximum spare + * capacity (i.e. target_cpu) + * c) ACTIVE CPU with less contention due to other tasks + * (i.e. best_active_cpu) + * + * - NON prefer_idle tasks: + * + * a) ACTIVE CPU: target_cpu + * b) IDLE CPU: best_idle_cpu + */ + if (target_cpu == -1) + target_cpu = prefer_idle + ? best_active_cpu + : best_idle_cpu; + else + *backup_cpu = prefer_idle + ? best_active_cpu + : best_idle_cpu; + + trace_sched_find_best_target(p, prefer_idle, min_util, cpu, + best_idle_cpu, best_active_cpu, + target_cpu); + + schedstat_inc(p, se.statistics.nr_wakeups_fbt_count); + schedstat_inc(this_rq(), eas_stats.fbt_count); + + return target_cpu; +} + +/* + * Disable WAKE_AFFINE in the case where task @p doesn't fit in the + * capacity of either the waking CPU @cpu or the previous CPU @prev_cpu. + * + * In that case WAKE_AFFINE doesn't make sense and we'll let + * BALANCE_WAKE sort things out. + */ +static int wake_cap(struct task_struct *p, int cpu, int prev_cpu) +{ + long min_cap, max_cap; + + min_cap = min(capacity_orig_of(prev_cpu), capacity_orig_of(cpu)); + max_cap = cpu_rq(cpu)->rd->max_cpu_capacity.val; + + /* Minimum capacity is close to max, no need to abort wake_affine */ + if (max_cap - min_cap < max_cap >> 3) + return 0; + + /* Bring task utilization in sync with prev_cpu */ + sync_entity_load_avg(&p->se); + + return min_cap * 1024 < task_util(p) * capacity_margin; +} + +static int select_energy_cpu_brute(struct task_struct *p, int prev_cpu, int sync) +{ + struct sched_domain *sd; + int target_cpu = prev_cpu, tmp_target, tmp_backup; + bool boosted, prefer_idle; + + schedstat_inc(p, se.statistics.nr_wakeups_secb_attempts); + schedstat_inc(this_rq(), eas_stats.secb_attempts); + + if (sysctl_sched_sync_hint_enable && sync) { + int cpu = smp_processor_id(); + + if (cpumask_test_cpu(cpu, tsk_cpus_allowed(p))) { + schedstat_inc(p, se.statistics.nr_wakeups_secb_sync); + schedstat_inc(this_rq(), eas_stats.secb_sync); + return cpu; + } + } + + rcu_read_lock(); +#ifdef CONFIG_CGROUP_SCHEDTUNE + boosted = schedtune_task_boost(p) > 0; + prefer_idle = schedtune_prefer_idle(p) > 0; +#else + boosted = get_sysctl_sched_cfs_boost() > 0; + prefer_idle = 0; +#endif + + sync_entity_load_avg(&p->se); + + sd = rcu_dereference(per_cpu(sd_ea, prev_cpu)); + /* Find a cpu with sufficient capacity */ + tmp_target = find_best_target(p, &tmp_backup, boosted, prefer_idle); + + if (!sd) + goto unlock; + if (tmp_target >= 0) { + target_cpu = tmp_target; + if ((boosted || prefer_idle) && idle_cpu(target_cpu)) { + schedstat_inc(p, se.statistics.nr_wakeups_secb_idle_bt); + schedstat_inc(this_rq(), eas_stats.secb_idle_bt); + goto unlock; + } + } + + if (target_cpu != prev_cpu) { + int delta = 0; + struct energy_env eenv = { + .util_delta = task_util(p), + .src_cpu = prev_cpu, + .dst_cpu = target_cpu, + .task = p, + .trg_cpu = target_cpu, + }; + + +#ifdef CONFIG_SCHED_WALT + if (!walt_disabled && sysctl_sched_use_walt_cpu_util && + p->state == TASK_WAKING) + delta = task_util(p); +#endif + /* Not enough spare capacity on previous cpu */ + if (__cpu_overutilized(prev_cpu, delta)) { + schedstat_inc(p, se.statistics.nr_wakeups_secb_insuff_cap); + schedstat_inc(this_rq(), eas_stats.secb_insuff_cap); + goto unlock; + } + + if (energy_diff(&eenv) >= 0) { + /* No energy saving for target_cpu, try backup */ + target_cpu = tmp_backup; + eenv.dst_cpu = target_cpu; + eenv.trg_cpu = target_cpu; + if (tmp_backup < 0 || + tmp_backup == prev_cpu || + energy_diff(&eenv) >= 0) { + schedstat_inc(p, se.statistics.nr_wakeups_secb_no_nrg_sav); + schedstat_inc(this_rq(), eas_stats.secb_no_nrg_sav); + target_cpu = prev_cpu; + goto unlock; + } + } + + schedstat_inc(p, se.statistics.nr_wakeups_secb_nrg_sav); + schedstat_inc(this_rq(), eas_stats.secb_nrg_sav); + goto unlock; + } + + schedstat_inc(p, se.statistics.nr_wakeups_secb_count); + schedstat_inc(this_rq(), eas_stats.secb_count); + +unlock: + rcu_read_unlock(); + + return target_cpu; +} + /* * select_task_rq_fair: Select target runqueue for the waking task in domains * that have the 'sd_flag' flag set. In practice, this is SD_BALANCE_WAKE, @@ -4978,7 +7862,8 @@ * preempt must be disabled. */ static int -select_task_rq_fair(struct task_struct *p, int prev_cpu, int sd_flag, int wake_flags) +select_task_rq_fair(struct task_struct *p, int prev_cpu, int sd_flag, int wake_flags, + int sibling_count_hint) { struct sched_domain *tmp, *affine_sd = NULL, *sd = NULL; int cpu = smp_processor_id(); @@ -4986,8 +7871,19 @@ int want_affine = 0; int sync = wake_flags & WF_SYNC; - if (sd_flag & SD_BALANCE_WAKE) - want_affine = !wake_wide(p) && cpumask_test_cpu(cpu, tsk_cpus_allowed(p)); +#ifdef CONFIG_SCHED_HMP + return select_best_cpu(p, prev_cpu, 0, sync); +#endif + + if (sd_flag & SD_BALANCE_WAKE) { + record_wakee(p); + want_affine = !wake_wide(p, sibling_count_hint) && + !wake_cap(p, cpu, prev_cpu) && + cpumask_test_cpu(cpu, &p->cpus_allowed); + } + + if (energy_aware() && !(cpu_rq(prev_cpu)->rd->overutilized)) + return select_energy_cpu_brute(p, prev_cpu, sync); rcu_read_lock(); for_each_domain(cpu, tmp) { @@ -5012,47 +7908,25 @@ if (affine_sd) { sd = NULL; /* Prefer wake_affine over balance flags */ - if (cpu != prev_cpu && wake_affine(affine_sd, p, sync)) + if (cpu != prev_cpu && wake_affine(affine_sd, p, prev_cpu, sync)) new_cpu = cpu; } - if (!sd) { - if (sd_flag & SD_BALANCE_WAKE) /* XXX always ? */ - new_cpu = select_idle_sibling(p, new_cpu); - - } else while (sd) { - struct sched_group *group; - int weight; - - if (!(sd->flags & sd_flag)) { - sd = sd->child; - continue; - } - - group = find_idlest_group(sd, p, cpu, sd_flag); - if (!group) { - sd = sd->child; - continue; + if (sd && !(sd_flag & SD_BALANCE_FORK)) { + /* + * We're going to need the task's util for capacity_spare_wake + * in find_idlest_group. Sync it up to prev_cpu's + * last_update_time. + */ + sync_entity_load_avg(&p->se); } - new_cpu = find_idlest_cpu(group, p, cpu); - if (new_cpu == -1 || new_cpu == cpu) { - /* Now try balancing at a lower domain level of cpu */ - sd = sd->child; - continue; - } + if (!sd) { + if (sd_flag & SD_BALANCE_WAKE) /* XXX always ? */ + new_cpu = select_idle_sibling(p, prev_cpu, new_cpu); - /* Now try balancing at a lower domain level of new_cpu */ - cpu = new_cpu; - weight = sd->span_weight; - sd = NULL; - for_each_domain(cpu, tmp) { - if (weight <= tmp->span_weight) - break; - if (tmp->flags & sd_flag) - sd = tmp; - } - /* while loop will break here if sd == NULL */ + } else { + new_cpu = find_idlest_cpu(sd, p, cpu, prev_cpu, sd_flag); } rcu_read_unlock(); @@ -5087,6 +7961,8 @@ { remove_entity_load_avg(&p->se); } +#else +#define task_fits_max(p, cpu) true #endif /* CONFIG_SMP */ static unsigned long @@ -5333,6 +8209,8 @@ if (hrtick_enabled(rq)) hrtick_start_fair(rq, p); + rq->misfit_task = !task_fits_max(p, rq->cpu); + return p; simple: cfs_rq = &rq->cfs; @@ -5354,9 +8232,12 @@ if (hrtick_enabled(rq)) hrtick_start_fair(rq, p); + rq->misfit_task = !task_fits_max(p, rq->cpu); + return p; idle: + rq->misfit_task = 0; /* * This is OK, because current is on_cpu, which avoids it being picked * for load-balance and preemption/IRQs are still disabled avoiding @@ -5569,10 +8450,21 @@ enum fbq_type { regular, remote, all }; +enum group_type { + group_other = 0, + group_misfit_task, + group_imbalanced, + group_overloaded, +}; + #define LBF_ALL_PINNED 0x01 #define LBF_NEED_BREAK 0x02 #define LBF_DST_PINNED 0x04 #define LBF_SOME_PINNED 0x08 +#define LBF_BIG_TASK_ACTIVE_BALANCE 0x80 +#define LBF_IGNORE_BIG_TASKS 0x100 +#define LBF_IGNORE_PREFERRED_CLUSTER_TASKS 0x200 +#define LBF_MOVED_RELATED_THREAD_GROUP_TASK 0x400 struct lb_env { struct sched_domain *sd; @@ -5587,8 +8479,11 @@ int new_dst_cpu; enum cpu_idle_type idle; long imbalance; + unsigned int src_grp_nr_running; /* The set of CPUs under consideration for load-balancing */ struct cpumask *cpus; + unsigned int busiest_grp_capacity; + unsigned int busiest_nr_running; unsigned int flags; @@ -5597,7 +8492,9 @@ unsigned int loop_max; enum fbq_type fbq_type; + enum group_type busiest_group_type; struct list_head tasks; + enum sched_boost_policy boost_policy; }; /* @@ -5695,6 +8592,7 @@ int can_migrate_task(struct task_struct *p, struct lb_env *env) { int tsk_cache_hot; + int twf, group_cpus; lockdep_assert_held(&env->src_rq->lock); @@ -5741,6 +8639,39 @@ /* Record that we found atleast one task that could run on dst_cpu */ env->flags &= ~LBF_ALL_PINNED; + if (cpu_capacity(env->dst_cpu) > cpu_capacity(env->src_cpu)) { + if (nr_big_tasks(env->src_rq) && !is_big_task(p)) + return 0; + + if (env->boost_policy == SCHED_BOOST_ON_BIG && + !task_sched_boost(p)) + return 0; + } + + twf = task_will_fit(p, env->dst_cpu); + + /* + * Attempt to not pull tasks that don't fit. We may get lucky and find + * one that actually fits. + */ + if (env->flags & LBF_IGNORE_BIG_TASKS && !twf) + return 0; + + if (env->flags & LBF_IGNORE_PREFERRED_CLUSTER_TASKS && + !preferred_cluster(rq_cluster(cpu_rq(env->dst_cpu)), p)) + return 0; + + /* + * Group imbalance can sometimes cause work to be pulled across groups + * even though the group could have managed the imbalance on its own. + * Prevent inter-cluster migrations for big tasks when the number of + * tasks is lower than the capacity of the group. + */ + group_cpus = DIV_ROUND_UP(env->busiest_grp_capacity, + SCHED_CAPACITY_SCALE); + if (!twf && env->busiest_nr_running <= group_cpus) + return 0; + if (task_running(env->src_rq, p)) { schedstat_inc(p, se.statistics.nr_failed_migrations_running); return 0; @@ -5748,15 +8679,16 @@ /* * Aggressive migration if: - * 1) destination numa is preferred - * 2) task is cache cold, or - * 3) too many balance attempts have failed. + * 1) IDLE or NEWLY_IDLE balance. + * 2) destination numa is preferred + * 3) task is cache cold, or + * 4) too many balance attempts have failed. */ tsk_cache_hot = migrate_degrades_locality(p, env); if (tsk_cache_hot == -1) tsk_cache_hot = task_hot(p, env); - if (tsk_cache_hot <= 0 || + if (env->idle != CPU_NOT_IDLE || tsk_cache_hot <= 0 || env->sd->nr_balance_failed > env->sd->cache_nice_tries) { if (tsk_cache_hot == 1) { schedstat_inc(env->sd, lb_hot_gained[env->idle]); @@ -5776,9 +8708,13 @@ { lockdep_assert_held(&env->src_rq->lock); - deactivate_task(env->src_rq, p, 0); p->on_rq = TASK_ON_RQ_MIGRATING; + deactivate_task(env->src_rq, p, 0); + double_lock_balance(env->src_rq, env->dst_rq); set_task_cpu(p, env->dst_cpu); + if (task_in_related_thread_group(p)) + env->flags |= LBF_MOVED_RELATED_THREAD_GROUP_TASK; + double_unlock_balance(env->src_rq, env->dst_rq); } /* @@ -5806,6 +8742,7 @@ * inside detach_tasks(). */ schedstat_inc(env->sd, lb_gained[env->idle]); + return p; } return NULL; @@ -5825,12 +8762,20 @@ struct task_struct *p; unsigned long load; int detached = 0; + int orig_loop = env->loop; lockdep_assert_held(&env->src_rq->lock); if (env->imbalance <= 0) return 0; + if (!same_cluster(env->dst_cpu, env->src_cpu)) + env->flags |= LBF_IGNORE_PREFERRED_CLUSTER_TASKS; + + if (cpu_capacity(env->dst_cpu) < cpu_capacity(env->src_cpu)) + env->flags |= LBF_IGNORE_BIG_TASKS; + +redo: while (!list_empty(tasks)) { /* * We don't want to steal all, otherwise we may be treated likewise, @@ -5892,6 +8837,15 @@ list_move_tail(&p->se.group_node, tasks); } + if (env->flags & (LBF_IGNORE_BIG_TASKS | + LBF_IGNORE_PREFERRED_CLUSTER_TASKS) && !detached) { + tasks = &env->src_rq->cfs_tasks; + env->flags &= ~(LBF_IGNORE_BIG_TASKS | + LBF_IGNORE_PREFERRED_CLUSTER_TASKS); + env->loop = orig_loop; + goto redo; + } + /* * Right now, this is one of only two places we collect this stat * so we can safely collect detach_one_task() stats here rather @@ -5910,8 +8864,8 @@ lockdep_assert_held(&rq->lock); BUG_ON(task_rq(p) != rq); - p->on_rq = TASK_ON_RQ_QUEUED; activate_task(rq, p, 0); + p->on_rq = TASK_ON_RQ_QUEUED; check_preempt_curr(rq, p, 0); } @@ -5966,8 +8920,13 @@ if (throttled_hierarchy(cfs_rq)) continue; - if (update_cfs_rq_load_avg(cfs_rq_clock_task(cfs_rq), cfs_rq)) + if (update_cfs_rq_load_avg(cfs_rq_clock_task(cfs_rq), cfs_rq, + true)) update_tg_load_avg(cfs_rq, 0); + + /* Propagate pending load changes to the parent */ + if (cfs_rq->tg->se[cpu]) + update_load_avg(cfs_rq->tg->se[cpu], 0); } raw_spin_unlock_irqrestore(&rq->lock, flags); } @@ -6027,7 +8986,7 @@ raw_spin_lock_irqsave(&rq->lock, flags); update_rq_clock(rq); - update_cfs_rq_load_avg(cfs_rq_clock_task(cfs_rq), cfs_rq); + update_cfs_rq_load_avg(cfs_rq_clock_task(cfs_rq), cfs_rq, true); raw_spin_unlock_irqrestore(&rq->lock, flags); } @@ -6039,12 +8998,6 @@ /********** Helpers for find_busiest_group ************************/ -enum group_type { - group_other = 0, - group_imbalanced, - group_overloaded, -}; - /* * sg_lb_stats - stats of a sched_group required for load_balancing */ @@ -6056,10 +9009,15 @@ unsigned long group_capacity; unsigned long group_util; /* Total utilization of the group */ unsigned int sum_nr_running; /* Nr tasks running in the group */ +#ifdef CONFIG_SCHED_HMP + unsigned long sum_nr_big_tasks; + u64 group_cpu_load; /* Scaled load of all CPUs of the group */ +#endif unsigned int idle_cpus; unsigned int group_weight; enum group_type group_type; int group_no_capacity; + int group_misfit_task; /* A cpu has a task too big for its capacity */ #ifdef CONFIG_NUMA_BALANCING unsigned int nr_numa_running; unsigned int nr_preferred_running; @@ -6098,10 +9056,64 @@ .avg_load = 0UL, .sum_nr_running = 0, .group_type = group_other, +#ifdef CONFIG_SCHED_HMP + .sum_nr_big_tasks = 0UL, + .group_cpu_load = 0ULL, +#endif }, }; } +#ifdef CONFIG_SCHED_HMP + +static int +bail_inter_cluster_balance(struct lb_env *env, struct sd_lb_stats *sds) +{ + int local_cpu, busiest_cpu; + int local_capacity, busiest_capacity; + int local_pwr_cost, busiest_pwr_cost; + int nr_cpus; + int boost = sched_boost(); + + if (!sysctl_sched_restrict_cluster_spill || + boost == FULL_THROTTLE_BOOST || boost == CONSERVATIVE_BOOST) + return 0; + + local_cpu = group_first_cpu(sds->local); + busiest_cpu = group_first_cpu(sds->busiest); + + local_capacity = cpu_max_possible_capacity(local_cpu); + busiest_capacity = cpu_max_possible_capacity(busiest_cpu); + + local_pwr_cost = cpu_max_power_cost(local_cpu); + busiest_pwr_cost = cpu_max_power_cost(busiest_cpu); + + if (local_pwr_cost <= busiest_pwr_cost) + return 0; + + if (local_capacity > busiest_capacity && + sds->busiest_stat.sum_nr_big_tasks) + return 0; + + nr_cpus = cpumask_weight(sched_group_cpus(sds->busiest)); + if ((sds->busiest_stat.group_cpu_load < nr_cpus * sched_spill_load) && + (sds->busiest_stat.sum_nr_running < + nr_cpus * sysctl_sched_spill_nr_run)) + return 1; + + return 0; +} + +#else /* CONFIG_SCHED_HMP */ + +static inline int +bail_inter_cluster_balance(struct lb_env *env, struct sd_lb_stats *sds) +{ + return 0; +} + +#endif /* CONFIG_SCHED_HMP */ + /** * get_sd_load_idx - Obtain the load index for a given sched domain. * @sd: The sched_domain whose load_idx is to be obtained. @@ -6151,19 +9163,58 @@ used = div_u64(avg, total); + /* + * deadline bandwidth is defined at system level so we must + * weight this bandwidth with the max capacity of the system. + * As a reminder, avg_bw is 20bits width and + * scale_cpu_capacity is 10 bits width + */ + used += div_u64(rq->dl.avg_bw, arch_scale_cpu_capacity(NULL, cpu)); + if (likely(used < SCHED_CAPACITY_SCALE)) return SCHED_CAPACITY_SCALE - used; return 1; } +void init_max_cpu_capacity(struct max_cpu_capacity *mcc) +{ + raw_spin_lock_init(&mcc->lock); + mcc->val = 0; + mcc->cpu = -1; +} + static void update_cpu_capacity(struct sched_domain *sd, int cpu) { unsigned long capacity = arch_scale_cpu_capacity(sd, cpu); struct sched_group *sdg = sd->groups; + struct max_cpu_capacity *mcc; + unsigned long max_capacity; + int max_cap_cpu; + unsigned long flags; cpu_rq(cpu)->cpu_capacity_orig = capacity; + mcc = &cpu_rq(cpu)->rd->max_cpu_capacity; + + raw_spin_lock_irqsave(&mcc->lock, flags); + max_capacity = mcc->val; + max_cap_cpu = mcc->cpu; + + if ((max_capacity > capacity && max_cap_cpu == cpu) || + (max_capacity < capacity)) { + mcc->val = capacity; + mcc->cpu = cpu; +#ifdef CONFIG_SCHED_DEBUG + raw_spin_unlock_irqrestore(&mcc->lock, flags); + printk_deferred(KERN_INFO "CPU%d: update max cpu_capacity %lu\n", + cpu, capacity); + goto skip_unlock; +#endif + } + raw_spin_unlock_irqrestore(&mcc->lock, flags); + +skip_unlock: __attribute__ ((unused)); capacity *= scale_rt_capacity(cpu); capacity >>= SCHED_CAPACITY_SHIFT; @@ -6172,13 +9223,15 @@ cpu_rq(cpu)->cpu_capacity = capacity; sdg->sgc->capacity = capacity; + sdg->sgc->max_capacity = capacity; + sdg->sgc->min_capacity = capacity; } void update_group_capacity(struct sched_domain *sd, int cpu) { struct sched_domain *child = sd->child; struct sched_group *group, *sdg = sd->groups; - unsigned long capacity; + unsigned long capacity, max_capacity, min_capacity; unsigned long interval; interval = msecs_to_jiffies(sd->balance_interval); @@ -6191,6 +9244,8 @@ } capacity = 0; + max_capacity = 0; + min_capacity = ULONG_MAX; if (child->flags & SD_OVERLAP) { /* @@ -6202,6 +9257,8 @@ struct sched_group_capacity *sgc; struct rq *rq = cpu_rq(cpu); + if (cpumask_test_cpu(cpu, cpu_isolated_mask)) + continue; /* * build_sched_domains() -> init_sched_groups_capacity() * gets here before we've attached the domains to the @@ -6215,12 +9272,14 @@ */ if (unlikely(!rq->sd)) { capacity += capacity_of(cpu); - continue; - } - + } else { sgc = rq->sd->groups->sgc; capacity += sgc->capacity; } + + max_capacity = max(capacity, max_capacity); + min_capacity = min(capacity, min_capacity); + } } else { /* * !SD_OVERLAP domains can assume that child groups @@ -6229,12 +9288,23 @@ group = child->groups; do { - capacity += group->sgc->capacity; + struct sched_group_capacity *sgc = group->sgc; + + cpumask_t *cpus = sched_group_cpus(group); + + /* Revisit this later. This won't work for MT domain */ + if (!cpu_isolated(cpumask_first(cpus))) { + capacity += sgc->capacity; + max_capacity = max(sgc->max_capacity, max_capacity); + min_capacity = min(sgc->min_capacity, min_capacity); + } group = group->next; } while (group != child->groups); } sdg->sgc->capacity = capacity; + sdg->sgc->max_capacity = max_capacity; + sdg->sgc->min_capacity = min_capacity; } /* @@ -6329,9 +9399,21 @@ return false; } + +/* + * group_smaller_cpu_capacity: Returns true if sched_group sg has smaller + * per-cpu capacity than sched_group ref. + */ +static inline bool +group_smaller_cpu_capacity(struct sched_group *sg, struct sched_group *ref) +{ + return sg->sgc->max_capacity + capacity_margin - SCHED_LOAD_SCALE < + ref->sgc->max_capacity; +} + static inline enum group_type group_classify(struct sched_group *group, - struct sg_lb_stats *sgs) + struct sg_lb_stats *sgs, struct lb_env *env) { if (sgs->group_no_capacity) return group_overloaded; @@ -6339,9 +9421,44 @@ if (sg_imbalanced(group)) return group_imbalanced; + if (sgs->group_misfit_task) + return group_misfit_task; + return group_other; } +#ifdef CONFIG_NO_HZ_COMMON +/* + * idle load balancing data + * - used by the nohz balance, but we want it available here + * so that we can see which CPUs have no tick. + */ +static struct { + cpumask_var_t idle_cpus_mask; + atomic_t nr_cpus; + unsigned long next_balance; /* in jiffy units */ +} nohz ____cacheline_aligned; + +static inline void update_cpu_stats_if_tickless(struct rq *rq) +{ + /* only called from update_sg_lb_stats when irqs are disabled */ + if (cpumask_test_cpu(rq->cpu, nohz.idle_cpus_mask)) { + /* rate limit updates to once-per-jiffie at most */ + if (READ_ONCE(jiffies) <= rq->last_load_update_tick) + return; + + raw_spin_lock(&rq->lock); + update_rq_clock(rq); + update_idle_cpu_load(rq); + update_cfs_rq_load_avg(rq->clock_task, &rq->cfs, false); + raw_spin_unlock(&rq->lock); + } +} + +#else +static inline void update_cpu_stats_if_tickless(struct rq *rq) { } +#endif + /** * update_sg_lb_stats - Update sched_group's statistics for load balancing. * @env: The load balancing environment. @@ -6350,20 +9467,35 @@ * @local_group: Does group contain this_cpu. * @sgs: variable to hold the statistics for this group. * @overload: Indicate more than one runnable task for any CPU. + * @overutilized: Indicate overutilization for any CPU. */ static inline void update_sg_lb_stats(struct lb_env *env, struct sched_group *group, int load_idx, int local_group, struct sg_lb_stats *sgs, - bool *overload) + bool *overload, bool *overutilized) { unsigned long load; - int i; + int i, nr_running; memset(sgs, 0, sizeof(*sgs)); for_each_cpu_and(i, sched_group_cpus(group), env->cpus) { struct rq *rq = cpu_rq(i); + trace_sched_cpu_load_lb(cpu_rq(i), idle_cpu(i), + sched_irqload(i), + power_cost(i, 0), + cpu_temp(i)); + + if (cpu_isolated(i)) + continue; + + /* if we are entering idle and there are CPUs with + * their tick stopped, do an update for them + */ + if (env->idle == CPU_NEWLY_IDLE) + update_cpu_stats_if_tickless(rq); + /* Bias balancing toward cpus of our domain */ if (local_group) load = target_load(i, load_idx); @@ -6374,30 +9506,82 @@ sgs->group_util += cpu_util(i); sgs->sum_nr_running += rq->cfs.h_nr_running; - if (rq->nr_running > 1) + nr_running = rq->nr_running; + if (nr_running > 1) *overload = true; +#ifdef CONFIG_SCHED_HMP + sgs->sum_nr_big_tasks += rq->hmp_stats.nr_big_tasks; + sgs->group_cpu_load += cpu_load(i); +#endif + #ifdef CONFIG_NUMA_BALANCING sgs->nr_numa_running += rq->nr_numa_running; sgs->nr_preferred_running += rq->nr_preferred_running; #endif sgs->sum_weighted_load += weighted_cpuload(i); - if (idle_cpu(i)) + /* + * No need to call idle_cpu() if nr_running is not 0 + */ + if (!nr_running && idle_cpu(i)) sgs->idle_cpus++; + + if (energy_aware() && cpu_overutilized(i)) { + *overutilized = true; + if (!sgs->group_misfit_task && rq->misfit_task) + sgs->group_misfit_task = capacity_of(i); + } } + /* Isolated CPU has no weight */ + if (!group->group_weight) { + sgs->group_capacity = 0; + sgs->avg_load = 0; + sgs->group_no_capacity = 1; + sgs->group_type = group_other; + sgs->group_weight = group->group_weight; + } else { /* Adjust by relative CPU capacity of the group */ sgs->group_capacity = group->sgc->capacity; - sgs->avg_load = (sgs->group_load*SCHED_CAPACITY_SCALE) / sgs->group_capacity; + sgs->avg_load = (sgs->group_load*SCHED_CAPACITY_SCALE) / + sgs->group_capacity; + + sgs->group_weight = group->group_weight; + + sgs->group_no_capacity = group_is_overloaded(env, sgs); + sgs->group_type = group_classify(group, sgs, env); + } if (sgs->sum_nr_running) sgs->load_per_task = sgs->sum_weighted_load / sgs->sum_nr_running; +} - sgs->group_weight = group->group_weight; +#ifdef CONFIG_SCHED_HMP +static bool update_sd_pick_busiest_active_balance(struct lb_env *env, + struct sd_lb_stats *sds, + struct sched_group *sg, + struct sg_lb_stats *sgs) +{ + if (env->idle != CPU_NOT_IDLE && + cpu_capacity(env->dst_cpu) > group_rq_capacity(sg)) { + if (sgs->sum_nr_big_tasks > + sds->busiest_stat.sum_nr_big_tasks) { + env->flags |= LBF_BIG_TASK_ACTIVE_BALANCE; + return true; + } + } - sgs->group_no_capacity = group_is_overloaded(env, sgs); - sgs->group_type = group_classify(group, sgs); + return false; } +#else +static bool update_sd_pick_busiest_active_balance(struct lb_env *env, + struct sd_lb_stats *sds, + struct sched_group *sg, + struct sg_lb_stats *sgs) +{ + return false; +} +#endif /** * update_sd_pick_busiest - return 1 on busiest group @@ -6419,15 +9603,42 @@ { struct sg_lb_stats *busiest = &sds->busiest_stat; + if (update_sd_pick_busiest_active_balance(env, sds, sg, sgs)) + return true; + if (sgs->group_type > busiest->group_type) return true; if (sgs->group_type < busiest->group_type) return false; + if (energy_aware()) { + /* + * Candidate sg doesn't face any serious load-balance problems + * so don't pick it if the local sg is already filled up. + */ + if (sgs->group_type == group_other && + !group_has_capacity(env, &sds->local_stat)) + return false; + if (sgs->avg_load <= busiest->avg_load) return false; + if (!(env->sd->flags & SD_ASYM_CPUCAPACITY)) + goto asym_packing; + + /* + * Candidate sg has no more than one task per CPU and + * has higher per-CPU capacity. Migrating tasks to less + * capable CPUs may harm throughput. Maximize throughput, + * power/energy consequences are not considered. + */ + if (sgs->sum_nr_running <= sgs->group_weight && + group_smaller_cpu_capacity(sds->local, sg)) + return false; + } + +asym_packing: /* This is the busiest node in its class. */ if (!(env->sd->flags & SD_ASYM_PACKING)) return true; @@ -6478,6 +9689,9 @@ } #endif /* CONFIG_NUMA_BALANCING */ +#define lb_sd_parent(sd) \ + (sd->parent && sd->parent->groups != sd->parent->groups->next) + /** * update_sd_lb_stats - Update sched_domain's statistics for load balancing. * @env: The load balancing environment. @@ -6489,7 +9703,7 @@ struct sched_group *sg = env->sd->groups; struct sg_lb_stats tmp_sgs; int load_idx, prefer_sibling = 0; - bool overload = false; + bool overload = false, overutilized = false; if (child && child->flags & SD_PREFER_SIBLING) prefer_sibling = 1; @@ -6511,7 +9725,7 @@ } update_sg_lb_stats(env, sg, load_idx, local_group, sgs, - &overload); + &overload, &overutilized); if (local_group) goto next_group; @@ -6530,12 +9744,24 @@ group_has_capacity(env, &sds->local_stat) && (sgs->sum_nr_running > 1)) { sgs->group_no_capacity = 1; - sgs->group_type = group_classify(sg, sgs); + sgs->group_type = group_classify(sg, sgs, env); } + /* + * Ignore task groups with misfit tasks if local group has no + * capacity or if per-cpu capacity isn't higher. + */ + if (energy_aware() && + sgs->group_type == group_misfit_task && + (!group_has_capacity(env, &sds->local_stat) || + !group_smaller_cpu_capacity(sg, sds->local))) + sgs->group_type = group_other; + if (update_sd_pick_busiest(env, sds, sg, sgs)) { sds->busiest = sg; sds->busiest_stat = *sgs; + env->busiest_nr_running = sgs->sum_nr_running; + env->busiest_grp_capacity = sgs->group_capacity; } next_group: @@ -6549,10 +9775,23 @@ if (env->sd->flags & SD_NUMA) env->fbq_type = fbq_classify_group(&sds->busiest_stat); - if (!env->sd->parent) { + env->src_grp_nr_running = sds->busiest_stat.sum_nr_running; + + if (!lb_sd_parent(env->sd)) { /* update overload indicator if we are at root domain */ if (env->dst_rq->rd->overload != overload) env->dst_rq->rd->overload = overload; + + /* Update over-utilization (tipping point, U >= 0) indicator */ + if (energy_aware() && env->dst_rq->rd->overutilized != overutilized) { + env->dst_rq->rd->overutilized = overutilized; + trace_sched_overutilized(overutilized); + } + } else { + if (energy_aware() && !env->dst_rq->rd->overutilized && overutilized) { + env->dst_rq->rd->overutilized = true; + trace_sched_overutilized(true); + } } } @@ -6701,6 +9940,24 @@ */ if (busiest->avg_load <= sds->avg_load || local->avg_load >= sds->avg_load) { + if (energy_aware()) { + /* Misfitting tasks should be migrated in any case */ + if (busiest->group_type == group_misfit_task) { + env->imbalance = busiest->group_misfit_task; + return; + } + + /* + * Busiest group is overloaded, local is not, use the spare + * cycles to maximize throughput + */ + if (busiest->group_type == group_overloaded && + local->group_type <= group_misfit_task) { + env->imbalance = busiest->load_per_task; + return; + } + } + env->imbalance = 0; return fix_small_imbalance(env, sds); } @@ -6734,6 +9991,11 @@ (sds->avg_load - local->avg_load) * local->group_capacity ) / SCHED_CAPACITY_SCALE; + /* Boost imbalance to allow misfit task to be balanced. */ + if (energy_aware() && busiest->group_type == group_misfit_task) + env->imbalance = max_t(long, env->imbalance, + busiest->group_misfit_task); + /* * if *imbalance is less than the average load per runnable task * there is no guarantee that any tasks will be moved so we'll have @@ -6775,6 +10037,10 @@ * this level. */ update_sd_lb_stats(env, &sds); + + if (energy_aware() && !env->dst_rq->rd->overutilized) + goto out_balanced; + local = &sds.local_stat; busiest = &sds.busiest_stat; @@ -6787,6 +10053,12 @@ if (!sds.busiest || busiest->sum_nr_running == 0) goto out_balanced; + if (env->flags & LBF_BIG_TASK_ACTIVE_BALANCE) + goto force_balance; + + if (bail_inter_cluster_balance(env, &sds)) + goto out_balanced; + sds.avg_load = (SCHED_CAPACITY_SCALE * sds.total_load) / sds.total_capacity; @@ -6798,11 +10070,19 @@ if (busiest->group_type == group_imbalanced) goto force_balance; - /* SD_BALANCE_NEWIDLE trumps SMP nice when underutilized */ - if (env->idle == CPU_NEWLY_IDLE && group_has_capacity(env, local) && + /* + * When dst_cpu is idle, prevent SMP nice and/or asymmetric group + * capacities from resulting in underutilization due to avg_load. + */ + if (env->idle != CPU_NOT_IDLE && group_has_capacity(env, local) && busiest->group_no_capacity) goto force_balance; + /* Misfitting tasks should be dealt with regardless of the avg load */ + if (energy_aware() && busiest->group_type == group_misfit_task) { + goto force_balance; + } + /* * If the local group is busier than the selected busiest group * don't try and pull any tasks. @@ -6826,7 +10106,8 @@ * might end up to just move the imbalance on another group */ if ((busiest->group_type != group_overloaded) && - (local->idle_cpus <= (busiest->idle_cpus + 1))) + (local->idle_cpus <= (busiest->idle_cpus + 1)) && + !group_smaller_cpu_capacity(sds.busiest, sds.local)) goto out_balanced; } else { /* @@ -6839,6 +10120,7 @@ } force_balance: + env->busiest_group_type = busiest->group_type; /* Looks like there is an imbalance. Compute it */ calculate_imbalance(env, &sds); return sds.busiest; @@ -6848,6 +10130,60 @@ return NULL; } +#ifdef CONFIG_SCHED_HMP +static struct rq *find_busiest_queue_hmp(struct lb_env *env, + struct sched_group *group) +{ + struct rq *busiest = NULL, *busiest_big = NULL; + u64 max_runnable_avg = 0, max_runnable_avg_big = 0; + int max_nr_big = 0, nr_big; + bool find_big = !!(env->flags & LBF_BIG_TASK_ACTIVE_BALANCE); + int i; + cpumask_t cpus; + + cpumask_andnot(&cpus, sched_group_cpus(group), cpu_isolated_mask); + + for_each_cpu(i, &cpus) { + struct rq *rq = cpu_rq(i); + u64 cumulative_runnable_avg = + rq->hmp_stats.cumulative_runnable_avg; + + if (!cpumask_test_cpu(i, env->cpus)) + continue; + + + if (find_big) { + nr_big = nr_big_tasks(rq); + if (nr_big > max_nr_big || + (nr_big > 0 && nr_big == max_nr_big && + cumulative_runnable_avg > max_runnable_avg_big)) { + max_runnable_avg_big = cumulative_runnable_avg; + busiest_big = rq; + max_nr_big = nr_big; + continue; + } + } + + if (cumulative_runnable_avg > max_runnable_avg) { + max_runnable_avg = cumulative_runnable_avg; + busiest = rq; + } + } + + if (busiest_big) + return busiest_big; + + env->flags &= ~LBF_BIG_TASK_ACTIVE_BALANCE; + return busiest; +} +#else +static inline struct rq *find_busiest_queue_hmp(struct lb_env *env, + struct sched_group *group) +{ + return NULL; +} +#endif + /* * find_busiest_queue - find the busiest runqueue among the cpus in group. */ @@ -6858,6 +10194,10 @@ unsigned long busiest_load = 0, busiest_capacity = 1; int i; +#ifdef CONFIG_SCHED_HMP + return find_busiest_queue_hmp(env, group); +#endif + for_each_cpu_and(i, sched_group_cpus(group), env->cpus) { unsigned long capacity, wl; enum fbq_type rt; @@ -6897,7 +10237,8 @@ */ if (rq->nr_running == 1 && wl > env->imbalance && - !check_cpu_capacity(rq, env->sd)) + !check_cpu_capacity(rq, env->sd) && + env->busiest_group_type != group_misfit_task) continue; /* @@ -6925,15 +10266,20 @@ * Max backoff if we encounter pinned tasks. Pretty arbitrary value, but * so long as it is large enough. */ -#define MAX_PINNED_INTERVAL 512 +#define MAX_PINNED_INTERVAL 16 /* Working cpumask for load_balance and load_balance_newidle. */ DEFINE_PER_CPU(cpumask_var_t, load_balance_mask); +#define NEED_ACTIVE_BALANCE_THRESHOLD 10 + static int need_active_balance(struct lb_env *env) { struct sched_domain *sd = env->sd; + if (env->flags & LBF_BIG_TASK_ACTIVE_BALANCE) + return 1; + if (env->idle == CPU_NEWLY_IDLE) { /* @@ -6958,10 +10304,27 @@ return 1; } - return unlikely(sd->nr_balance_failed > sd->cache_nice_tries+2); + if (energy_aware() && + (capacity_of(env->src_cpu) < capacity_of(env->dst_cpu)) && + ((capacity_orig_of(env->src_cpu) < capacity_orig_of(env->dst_cpu))) && + env->src_rq->cfs.h_nr_running == 1 && + cpu_overutilized(env->src_cpu) && + !cpu_overutilized(env->dst_cpu)) { + return 1; + } + + return unlikely(sd->nr_balance_failed > + sd->cache_nice_tries + NEED_ACTIVE_BALANCE_THRESHOLD); } -static int active_load_balance_cpu_stop(void *data); +static int group_balance_cpu_not_isolated(struct sched_group *sg) +{ + cpumask_t cpus; + + cpumask_and(&cpus, sched_group_cpus(sg), sched_group_mask(sg)); + cpumask_andnot(&cpus, &cpus, cpu_isolated_mask); + return cpumask_first(&cpus); +} static int should_we_balance(struct lb_env *env) { @@ -6980,7 +10343,8 @@ sg_mask = sched_group_mask(sg); /* Try to find first idle cpu */ for_each_cpu_and(cpu, sg_cpus, env->cpus) { - if (!cpumask_test_cpu(cpu, sg_mask) || !idle_cpu(cpu)) + if (!cpumask_test_cpu(cpu, sg_mask) || !idle_cpu(cpu) || + cpu_isolated(cpu)) continue; balance_cpu = cpu; @@ -6988,7 +10352,7 @@ } if (balance_cpu == -1) - balance_cpu = group_balance_cpu(sg); + balance_cpu = group_balance_cpu_not_isolated(sg); /* * First idle cpu or the first cpu(busiest) in this sched group @@ -7005,10 +10369,10 @@ struct sched_domain *sd, enum cpu_idle_type idle, int *continue_balancing) { - int ld_moved, cur_ld_moved, active_balance = 0; - struct sched_domain *sd_parent = sd->parent; - struct sched_group *group; - struct rq *busiest; + int ld_moved = 0, cur_ld_moved, active_balance = 0; + struct sched_domain *sd_parent = lb_sd_parent(sd) ? sd->parent : NULL; + struct sched_group *group = NULL; + struct rq *busiest = NULL; unsigned long flags; struct cpumask *cpus = this_cpu_cpumask_var_ptr(load_balance_mask); @@ -7022,6 +10386,12 @@ .cpus = cpus, .fbq_type = all, .tasks = LIST_HEAD_INIT(env.tasks), + .imbalance = 0, + .flags = 0, + .loop = 0, + .busiest_nr_running = 0, + .busiest_grp_capacity = 0, + .boost_policy = sched_boost_policy(), }; /* @@ -7073,6 +10443,14 @@ more_balance: raw_spin_lock_irqsave(&busiest->lock, flags); + update_rq_clock(busiest); + + /* The world might have changed. Validate assumptions */ + if (busiest->nr_running <= 1) { + raw_spin_unlock_irqrestore(&busiest->lock, flags); + env.flags &= ~LBF_ALL_PINNED; + goto no_move; + } /* * cur_ld_moved - load moved in current iteration @@ -7161,16 +10539,22 @@ } } +no_move: if (!ld_moved) { + if (!(env.flags & LBF_BIG_TASK_ACTIVE_BALANCE)) schedstat_inc(sd, lb_failed[idle]); + /* * Increment the failure counter only on periodic balance. * We do not want newidle balance, which can be very * frequent, pollute the failure counter causing * excessive cache_hot migrations and active balances. */ - if (idle != CPU_NEWLY_IDLE) + if (idle != CPU_NEWLY_IDLE && + !(env.flags & LBF_BIG_TASK_ACTIVE_BALANCE)) { + if (env.src_grp_nr_running > 1) sd->nr_balance_failed++; + } if (need_active_balance(&env)) { raw_spin_lock_irqsave(&busiest->lock, flags); @@ -7192,7 +10576,8 @@ * ->active_balance_work. Once set, it's cleared * only after active load balance is finished. */ - if (!busiest->active_balance) { + if (!busiest->active_balance && + !cpu_isolated(cpu_of(busiest))) { busiest->active_balance = 1; busiest->push_cpu = this_cpu; active_balance = 1; @@ -7203,17 +10588,31 @@ stop_one_cpu_nowait(cpu_of(busiest), active_load_balance_cpu_stop, busiest, &busiest->active_balance_work); + *continue_balancing = 0; } /* * We've kicked active balancing, reset the failure * counter. */ - sd->nr_balance_failed = sd->cache_nice_tries+1; + sd->nr_balance_failed = + sd->cache_nice_tries + + NEED_ACTIVE_BALANCE_THRESHOLD - 1; } - } else + } else { sd->nr_balance_failed = 0; + /* Assumes one 'busiest' cpu that we pulled tasks from */ + if (!same_freq_domain(this_cpu, cpu_of(busiest))) { + int check_groups = !!(env.flags & + LBF_MOVED_RELATED_THREAD_GROUP_TASK); + + check_for_freq_change(this_rq, false, check_groups); + check_for_freq_change(busiest, false, check_groups); + } else { + check_for_freq_change(this_rq, true, false); + } + } if (likely(!active_balance)) { /* We were unbalanced, so reset the balancing interval */ sd->balance_interval = sd->min_interval; @@ -7261,6 +10660,11 @@ ld_moved = 0; out: + trace_sched_load_balance(this_cpu, idle, *continue_balancing, + group ? group->cpumask[0] : 0, + busiest ? busiest->nr_running : 0, + env.imbalance, env.flags, ld_moved, + sd->balance_interval); return ld_moved; } @@ -7303,6 +10707,9 @@ int pulled_task = 0; u64 curr_cost = 0; + if (cpu_isolated(this_cpu)) + return 0; + idle_enter_fair(this_rq); /* @@ -7311,8 +10718,9 @@ */ this_rq->idle_stamp = rq_clock(this_rq); - if (this_rq->avg_idle < sysctl_sched_migration_cost || - !this_rq->rd->overload) { + if (!energy_aware() && + (this_rq->avg_idle < sysctl_sched_migration_cost || + !this_rq->rd->overload)) { rcu_read_lock(); sd = rcu_dereference_check_sched_domain(this_rq->sd); if (sd) @@ -7356,9 +10764,12 @@ /* * Stop searching for tasks to pull if there are - * now runnable tasks on this rq. + * now runnable tasks on the balance rq or if + * continue_balancing has been unset (only possible + * due to active migration). */ - if (pulled_task || this_rq->nr_running > 0) + if (pulled_task || this_rq->nr_running > 0 || + !continue_balancing) break; } rcu_read_unlock(); @@ -7405,8 +10816,24 @@ int busiest_cpu = cpu_of(busiest_rq); int target_cpu = busiest_rq->push_cpu; struct rq *target_rq = cpu_rq(target_cpu); - struct sched_domain *sd; + struct sched_domain *sd = NULL; struct task_struct *p = NULL; + struct task_struct *push_task = NULL; + int push_task_detached = 0; + struct lb_env env = { + .sd = sd, + .dst_cpu = target_cpu, + .dst_rq = target_rq, + .src_cpu = busiest_rq->cpu, + .src_rq = busiest_rq, + .idle = CPU_IDLE, + .busiest_nr_running = 0, + .busiest_grp_capacity = 0, + .flags = 0, + .loop = 0, + .boost_policy = sched_boost_policy(), + }; + bool moved = false; raw_spin_lock_irq(&busiest_rq->lock); @@ -7426,6 +10853,20 @@ */ BUG_ON(busiest_rq == target_rq); + push_task = busiest_rq->push_task; + target_cpu = busiest_rq->push_cpu; + if (push_task) { + if (task_on_rq_queued(push_task) && + push_task->state == TASK_RUNNING && + task_cpu(push_task) == busiest_cpu && + cpu_online(target_cpu)) { + detach_task(push_task, &env); + push_task_detached = 1; + moved = true; + } + goto out_unlock; + } + /* Search for an sd spanning us and the target CPU. */ rcu_read_lock(); for_each_domain(target_cpu, sd) { @@ -7435,33 +10876,50 @@ } if (likely(sd)) { - struct lb_env env = { - .sd = sd, - .dst_cpu = target_cpu, - .dst_rq = target_rq, - .src_cpu = busiest_rq->cpu, - .src_rq = busiest_rq, - .idle = CPU_IDLE, - }; - + env.sd = sd; schedstat_inc(sd, alb_count); + update_rq_clock(busiest_rq); p = detach_one_task(&env); - if (p) + if (p) { schedstat_inc(sd, alb_pushed); - else + moved = true; + } else { schedstat_inc(sd, alb_failed); } + } rcu_read_unlock(); out_unlock: busiest_rq->active_balance = 0; + push_task = busiest_rq->push_task; + target_cpu = busiest_rq->push_cpu; + + if (push_task) + busiest_rq->push_task = NULL; + raw_spin_unlock(&busiest_rq->lock); + if (push_task) { + if (push_task_detached) + attach_one_task(target_rq, push_task); + put_task_struct(push_task); + clear_reserved(target_cpu); + } + if (p) attach_one_task(target_rq, p); local_irq_enable(); + if (moved && !same_freq_domain(busiest_cpu, target_cpu)) { + int check_groups = !!(env.flags & + LBF_MOVED_RELATED_THREAD_GROUP_TASK); + check_for_freq_change(busiest_rq, false, check_groups); + check_for_freq_change(target_rq, false, check_groups); + } else if (moved) { + check_for_freq_change(target_rq, true, false); + } + return 0; } @@ -7477,15 +10935,49 @@ * needed, they will kick the idle load balancer, which then does idle * load balancing for all the idle CPUs. */ -static struct { - cpumask_var_t idle_cpus_mask; - atomic_t nr_cpus; - unsigned long next_balance; /* in jiffy units */ -} nohz ____cacheline_aligned; -static inline int find_new_ilb(void) +#ifdef CONFIG_SCHED_HMP +static inline int find_new_hmp_ilb(int type) +{ + int call_cpu = raw_smp_processor_id(); + struct sched_domain *sd; + int ilb; + + rcu_read_lock(); + + /* Pick an idle cpu "closest" to call_cpu */ + for_each_domain(call_cpu, sd) { + for_each_cpu_and(ilb, nohz.idle_cpus_mask, + sched_domain_span(sd)) { + if (idle_cpu(ilb) && (type != NOHZ_KICK_RESTRICT || + cpu_max_power_cost(ilb) <= + cpu_max_power_cost(call_cpu))) { + rcu_read_unlock(); + reset_balance_interval(ilb); + return ilb; + } + } + } + + rcu_read_unlock(); + return nr_cpu_ids; +} +#else /* CONFIG_SCHED_HMP */ +static inline int find_new_hmp_ilb(int type) +{ + return 0; +} +#endif /* CONFIG_SCHED_HMP */ + +static inline int find_new_ilb(int type) { - int ilb = cpumask_first(nohz.idle_cpus_mask); + int ilb; + +#ifdef CONFIG_SCHED_HMP + return find_new_hmp_ilb(type); +#endif + + ilb = cpumask_first(nohz.idle_cpus_mask); if (ilb < nr_cpu_ids && idle_cpu(ilb)) return ilb; @@ -7498,13 +10990,13 @@ * nohz_load_balancer CPU (if there is one) otherwise fallback to any idle * CPU (if there is one). */ -static void nohz_balancer_kick(void) +static void nohz_balancer_kick(int type) { int ilb_cpu; nohz.next_balance++; - ilb_cpu = find_new_ilb(); + ilb_cpu = find_new_ilb(type); if (ilb_cpu >= nr_cpu_ids) return; @@ -7521,16 +11013,21 @@ return; } +void nohz_balance_clear_nohz_mask(int cpu) +{ + if (likely(cpumask_test_cpu(cpu, nohz.idle_cpus_mask))) { + cpumask_clear_cpu(cpu, nohz.idle_cpus_mask); + atomic_dec(&nohz.nr_cpus); + } +} + static inline void nohz_balance_exit_idle(int cpu) { if (unlikely(test_bit(NOHZ_TICK_STOPPED, nohz_flags(cpu)))) { /* * Completely isolated CPUs don't ever set, so we must test. */ - if (likely(cpumask_test_cpu(cpu, nohz.idle_cpus_mask))) { - cpumask_clear_cpu(cpu, nohz.idle_cpus_mask); - atomic_dec(&nohz.nr_cpus); - } + nohz_balance_clear_nohz_mask(cpu); clear_bit(NOHZ_TICK_STOPPED, nohz_flags(cpu)); } } @@ -7587,7 +11084,7 @@ /* * If we're a completely isolated CPU, we don't play. */ - if (on_null_domain(cpu_rq(cpu))) + if (on_null_domain(cpu_rq(cpu)) || cpu_isolated(cpu)) return; cpumask_set_cpu(cpu, nohz.idle_cpus_mask); @@ -7616,7 +11113,13 @@ */ void update_max_interval(void) { - max_load_balance_interval = HZ*num_online_cpus()/10; + cpumask_t avail_mask; + unsigned int available_cpus; + + cpumask_andnot(&avail_mask, cpu_online_mask, cpu_isolated_mask); + available_cpus = cpumask_weight(&avail_mask); + + max_load_balance_interval = HZ*available_cpus/10; } /* @@ -7741,12 +11244,15 @@ /* Earliest time when we have to do rebalance again */ unsigned long next_balance = jiffies + 60*HZ; int update_next_balance = 0; + cpumask_t cpus; if (idle != CPU_IDLE || !test_bit(NOHZ_BALANCE_KICK, nohz_flags(this_cpu))) goto end; - for_each_cpu(balance_cpu, nohz.idle_cpus_mask) { + cpumask_andnot(&cpus, nohz.idle_cpus_mask, cpu_isolated_mask); + + for_each_cpu(balance_cpu, &cpus) { if (balance_cpu == this_cpu || !idle_cpu(balance_cpu)) continue; @@ -7789,6 +11295,79 @@ clear_bit(NOHZ_BALANCE_KICK, nohz_flags(this_cpu)); } +#ifdef CONFIG_SCHED_HMP +static inline int _nohz_kick_needed_hmp(struct rq *rq, int cpu, int *type) +{ + struct sched_domain *sd; + int i; + + if (rq->nr_running < 2) + return 0; + + if (!sysctl_sched_restrict_cluster_spill || + sched_boost_policy() == SCHED_BOOST_ON_ALL) + return 1; + + if (cpu_max_power_cost(cpu) == max_power_cost) + return 1; + + rcu_read_lock(); + sd = rcu_dereference_check_sched_domain(rq->sd); + if (!sd) { + rcu_read_unlock(); + return 0; + } + + for_each_cpu(i, sched_domain_span(sd)) { + if (cpu_load(i) < sched_spill_load && + cpu_rq(i)->nr_running < + sysctl_sched_spill_nr_run) { + /* Change the kick type to limit to CPUs that + * are of equal or lower capacity. + */ + *type = NOHZ_KICK_RESTRICT; + break; + } + } + rcu_read_unlock(); + return 1; +} +#else +static inline int _nohz_kick_needed_hmp(struct rq *rq, int cpu, int *type) +{ + return 0; +} +#endif + +static inline int _nohz_kick_needed(struct rq *rq, int cpu, int *type) +{ + unsigned long now = jiffies; + + /* + * None are in tickless mode and hence no need for NOHZ idle load + * balancing. + */ + if (likely(!atomic_read(&nohz.nr_cpus))) + return 0; + +#ifdef CONFIG_SCHED_HMP + return _nohz_kick_needed_hmp(rq, cpu, type); +#endif + + if (time_before(now, nohz.next_balance)) + return 0; + + if (rq->nr_running >= 2 && + (!energy_aware() || cpu_overutilized(cpu))) + return true; + + /* Do idle load balance if there have misfit task */ + if (energy_aware()) + return rq->misfit_task; + + return (rq->nr_running >= 2); +} + /* * Current heuristic for kicking the idle load balancer in the presence * of an idle cpu in the system. @@ -7800,12 +11379,14 @@ * - For SD_ASYM_PACKING, if the lower numbered cpu's in the scheduler * domain span are idle. */ -static inline bool nohz_kick_needed(struct rq *rq) +static inline bool nohz_kick_needed(struct rq *rq, int *type) { - unsigned long now = jiffies; +#ifndef CONFIG_SCHED_HMP struct sched_domain *sd; struct sched_group_capacity *sgc; - int nr_busy, cpu = rq->cpu; + int nr_busy; +#endif + int cpu = rq->cpu; bool kick = false; if (unlikely(rq->idle_balance)) @@ -7818,19 +11399,10 @@ set_cpu_sd_state_busy(); nohz_balance_exit_idle(cpu); - /* - * None are in tickless mode and hence no need for NOHZ idle load - * balancing. - */ - if (likely(!atomic_read(&nohz.nr_cpus))) - return false; - - if (time_before(now, nohz.next_balance)) - return false; - - if (rq->nr_running >= 2) + if (_nohz_kick_needed(rq, cpu, type)) return true; +#ifndef CONFIG_SCHED_HMP rcu_read_lock(); sd = rcu_dereference(per_cpu(sd_busy, cpu)); if (sd) { @@ -7862,6 +11434,7 @@ unlock: rcu_read_unlock(); +#endif return kick; } #else @@ -7895,15 +11468,19 @@ */ void trigger_load_balance(struct rq *rq) { - /* Don't need to rebalance while attached to NULL domain */ - if (unlikely(on_null_domain(rq))) + int type = NOHZ_KICK_ANY; + + /* Don't need to rebalance while attached to NULL domain or + * cpu is isolated. + */ + if (unlikely(on_null_domain(rq)) || cpu_isolated(cpu_of(rq))) return; if (time_after_eq(jiffies, rq->next_balance)) raise_softirq(SCHED_SOFTIRQ); #ifdef CONFIG_NO_HZ_COMMON - if (nohz_kick_needed(rq)) - nohz_balancer_kick(); + if (nohz_kick_needed(rq, &type)) + nohz_balancer_kick(type); #endif } @@ -7939,6 +11516,17 @@ if (static_branch_unlikely(&sched_numa_balancing)) task_tick_numa(rq, curr); + +#ifdef CONFIG_SMP + if (energy_aware() && + !rq->rd->overutilized && cpu_overutilized(task_cpu(curr))) { + rq->rd->overutilized = true; + trace_sched_overutilized(true); + } + + rq->misfit_task = !task_fits_max(curr, rq->cpu); +#endif + } /* @@ -7950,31 +11538,17 @@ { struct cfs_rq *cfs_rq; struct sched_entity *se = &p->se, *curr; - int this_cpu = smp_processor_id(); struct rq *rq = this_rq(); - unsigned long flags; - - raw_spin_lock_irqsave(&rq->lock, flags); + raw_spin_lock(&rq->lock); update_rq_clock(rq); cfs_rq = task_cfs_rq(current); curr = cfs_rq->curr; - - /* - * Not only the cpu but also the task_group of the parent might have - * been changed after parent->se.parent,cfs_rq were copied to - * child->se.parent,cfs_rq. So call __set_task_cpu() to make those - * of child point to valid ones. - */ - rcu_read_lock(); - __set_task_cpu(p, this_cpu); - rcu_read_unlock(); - + if (curr) { update_curr(cfs_rq); - - if (curr) se->vruntime = curr->vruntime; + } place_entity(cfs_rq, se, 1); if (sysctl_sched_child_runs_first && curr && entity_before(curr, se)) { @@ -7987,8 +11561,7 @@ } se->vruntime -= cfs_rq->min_vruntime; - - raw_spin_unlock_irqrestore(&rq->lock, flags); + raw_spin_unlock(&rq->lock); } /* @@ -8040,6 +11613,61 @@ return false; } +#ifdef CONFIG_FAIR_GROUP_SCHED +/* + * Propagate the changes of the sched_entity across the tg tree to make it + * visible to the root + */ +static void propagate_entity_cfs_rq(struct sched_entity *se) +{ + struct cfs_rq *cfs_rq; + + /* Start to propagate at parent */ + se = se->parent; + + for_each_sched_entity(se) { + cfs_rq = cfs_rq_of(se); + + if (cfs_rq_throttled(cfs_rq)) + break; + + update_load_avg(se, UPDATE_TG); + } +} +#else +static void propagate_entity_cfs_rq(struct sched_entity *se) { } +#endif + +static void detach_entity_cfs_rq(struct sched_entity *se) +{ + struct cfs_rq *cfs_rq = cfs_rq_of(se); + + /* Catch up with the cfs_rq and remove our load when we leave */ + update_load_avg(se, 0); + detach_entity_load_avg(cfs_rq, se); + update_tg_load_avg(cfs_rq, false); + propagate_entity_cfs_rq(se); +} + +static void attach_entity_cfs_rq(struct sched_entity *se) +{ + struct cfs_rq *cfs_rq = cfs_rq_of(se); + +#ifdef CONFIG_FAIR_GROUP_SCHED + /* + * Since the real-depth could have been changed (only FAIR + * class maintain depth value), reset depth properly. + */ + se->depth = se->parent ? se->parent->depth + 1 : 0; +#endif + + /* Synchronize entity with its cfs_rq */ + update_load_avg(se, sched_feat(ATTACH_AGE_LOAD) ? 0 : SKIP_AGE_LOAD); + attach_entity_load_avg(cfs_rq, se); + update_tg_load_avg(cfs_rq, false); + propagate_entity_cfs_rq(se); +} + static void detach_task_cfs_rq(struct task_struct *p) { struct sched_entity *se = &p->se; @@ -8054,8 +11682,7 @@ se->vruntime -= cfs_rq->min_vruntime; } - /* Catch up with the cfs_rq and remove our load when we leave */ - detach_entity_load_avg(cfs_rq, se); + detach_entity_cfs_rq(se); } static void attach_task_cfs_rq(struct task_struct *p) @@ -8063,16 +11690,7 @@ struct sched_entity *se = &p->se; struct cfs_rq *cfs_rq = cfs_rq_of(se); -#ifdef CONFIG_FAIR_GROUP_SCHED - /* - * Since the real-depth could have been changed (only FAIR - * class maintain depth value), reset depth properly. - */ - se->depth = se->parent ? se->parent->depth + 1 : 0; -#endif - - /* Synchronize task with its cfs_rq */ - attach_entity_load_avg(cfs_rq, se); + attach_entity_cfs_rq(se); if (!vruntime_normalized(p)) se->vruntime += cfs_rq->min_vruntime; @@ -8126,12 +11744,23 @@ cfs_rq->min_vruntime_copy = cfs_rq->min_vruntime; #endif #ifdef CONFIG_SMP +#ifdef CONFIG_FAIR_GROUP_SCHED + cfs_rq->propagate_avg = 0; +#endif atomic_long_set(&cfs_rq->removed_load_avg, 0); atomic_long_set(&cfs_rq->removed_util_avg, 0); #endif } #ifdef CONFIG_FAIR_GROUP_SCHED +static void task_set_group_fair(struct task_struct *p) +{ + struct sched_entity *se = &p->se; + + set_task_rq(p, task_cpu(p)); + se->depth = se->parent ? se->parent->depth + 1 : 0; +} + static void task_move_group_fair(struct task_struct *p) { detach_task_cfs_rq(p); @@ -8144,6 +11773,19 @@ attach_task_cfs_rq(p); } +static void task_change_group_fair(struct task_struct *p, int type) +{ + switch (type) { + case TASK_SET_GROUP: + task_set_group_fair(p); + break; + + case TASK_MOVE_GROUP: + task_move_group_fair(p); + break; + } +} + void free_fair_sched_group(struct task_group *tg) { int i; @@ -8153,12 +11795,9 @@ for_each_possible_cpu(i) { if (tg->cfs_rq) kfree(tg->cfs_rq[i]); - if (tg->se) { - if (tg->se[i]) - remove_entity_load_avg(tg->se[i]); + if (tg->se) kfree(tg->se[i]); } - } kfree(tg->cfs_rq); kfree(tg->se); @@ -8166,8 +11805,9 @@ int alloc_fair_sched_group(struct task_group *tg, struct task_group *parent) { - struct cfs_rq *cfs_rq; struct sched_entity *se; + struct cfs_rq *cfs_rq; + struct rq *rq; int i; tg->cfs_rq = kzalloc(sizeof(cfs_rq) * nr_cpu_ids, GFP_KERNEL); @@ -8182,6 +11822,8 @@ init_cfs_bandwidth(tg_cfs_bandwidth(tg)); for_each_possible_cpu(i) { + rq = cpu_rq(i); + cfs_rq = kzalloc_node(sizeof(struct cfs_rq), GFP_KERNEL, cpu_to_node(i)); if (!cfs_rq) @@ -8195,6 +11837,10 @@ init_cfs_rq(cfs_rq); init_tg_cfs_entry(tg, cfs_rq, se, i, parent->se[i]); init_entity_runnable_average(se); + + raw_spin_lock_irq(&rq->lock); + post_init_entity_util_avg(se); + raw_spin_unlock_irq(&rq->lock); } return 1; @@ -8205,22 +11851,30 @@ return 0; } -void unregister_fair_sched_group(struct task_group *tg, int cpu) +void unregister_fair_sched_group(struct task_group *tg) { - struct rq *rq = cpu_rq(cpu); unsigned long flags; + struct rq *rq; + int cpu; + + for_each_possible_cpu(cpu) { + if (tg->se[cpu]) + remove_entity_load_avg(tg->se[cpu]); /* * Only empty task groups can be destroyed; so we can speculatively * check on_list without danger of it being re-added. */ if (!tg->cfs_rq[cpu]->on_list) - return; + continue; + + rq = cpu_rq(cpu); raw_spin_lock_irqsave(&rq->lock, flags); list_del_leaf_cfs_rq(tg->cfs_rq[cpu]); raw_spin_unlock_irqrestore(&rq->lock, flags); } +} void init_tg_cfs_entry(struct task_group *tg, struct cfs_rq *cfs_rq, struct sched_entity *se, int cpu, @@ -8283,8 +11937,10 @@ /* Possible calls to update_curr() need rq clock */ update_rq_clock(rq); - for_each_sched_entity(se) - update_cfs_shares(group_cfs_rq(se)); + for_each_sched_entity(se) { + update_load_avg(se, UPDATE_TG); + update_cfs_shares(se); + } raw_spin_unlock_irqrestore(&rq->lock, flags); } @@ -8301,7 +11957,7 @@ return 1; } -void unregister_fair_sched_group(struct task_group *tg, int cpu) { } +void unregister_fair_sched_group(struct task_group *tg) { } #endif /* CONFIG_FAIR_GROUP_SCHED */ @@ -8361,7 +12017,12 @@ .update_curr = update_curr_fair, #ifdef CONFIG_FAIR_GROUP_SCHED - .task_move_group = task_move_group_fair, + .task_change_group = task_change_group_fair, +#endif +#ifdef CONFIG_SCHED_HMP + .inc_hmp_sched_stats = inc_hmp_sched_stats_fair, + .dec_hmp_sched_stats = dec_hmp_sched_stats_fair, + .fixup_hmp_sched_stats = fixup_hmp_sched_stats_fair, #endif }; diff -ruw linux-4.4.115/kernel/sched/features.h linux-4.4.115-fbx/kernel/sched/features.h --- linux-4.4.115/kernel/sched/features.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/kernel/sched/features.h 2019-01-22 16:16:28.699293459 +0100 @@ -49,7 +49,7 @@ * Queue remote wakeups on the target CPU and process them * using the scheduler IPI. Reduces rq->lock contention/bounces. */ -SCHED_FEAT(TTWU_QUEUE, true) +SCHED_FEAT(TTWU_QUEUE, false) #ifdef HAVE_RT_PUSH_IPI /* @@ -69,3 +69,12 @@ SCHED_FEAT(LB_MIN, false) SCHED_FEAT(ATTACH_AGE_LOAD, true) +/* + * Energy aware scheduling. Use platform energy model to guide scheduling + * decisions optimizing for energy efficiency. + */ +#ifdef CONFIG_DEFAULT_USE_ENERGY_AWARE +SCHED_FEAT(ENERGY_AWARE, true) +#else +SCHED_FEAT(ENERGY_AWARE, false) +#endif diff -ruw linux-4.4.115/kernel/sched/idle.c linux-4.4.115-fbx/kernel/sched/idle.c --- linux-4.4.115/kernel/sched/idle.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/kernel/sched/idle.c 2019-10-29 09:26:25.625222574 +0100 @@ -19,9 +19,10 @@ * sched_idle_set_state - Record idle state for the current CPU. * @idle_state: State to record. */ -void sched_idle_set_state(struct cpuidle_state *idle_state) +void sched_idle_set_state(struct cpuidle_state *idle_state, int index) { idle_set_state(this_rq(), idle_state); + idle_set_state_idx(this_rq(), index); } static int __read_mostly cpu_idle_force_poll; @@ -219,6 +220,7 @@ */ __current_set_polling(); + quiet_vmstat(); tick_nohz_idle_enter(); while (!need_resched()) { diff -ruw linux-4.4.115/kernel/sched/idle_task.c linux-4.4.115-fbx/kernel/sched/idle_task.c --- linux-4.4.115/kernel/sched/idle_task.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/kernel/sched/idle_task.c 2019-01-22 16:16:28.703293496 +0100 @@ -9,7 +9,8 @@ #ifdef CONFIG_SMP static int -select_task_rq_idle(struct task_struct *p, int cpu, int sd_flag, int flags) +select_task_rq_idle(struct task_struct *p, int cpu, int sd_flag, int flags, + int sibling_count_hint) { return task_cpu(p); /* IDLE tasks as never migrated */ } @@ -79,6 +80,26 @@ { } +#ifdef CONFIG_SCHED_HMP + +static void +inc_hmp_sched_stats_idle(struct rq *rq, struct task_struct *p) +{ +} + +static void +dec_hmp_sched_stats_idle(struct rq *rq, struct task_struct *p) +{ +} + +static void +fixup_hmp_sched_stats_idle(struct rq *rq, struct task_struct *p, + u32 new_task_load, u32 new_pred_demand) +{ +} + +#endif + /* * Simple, special scheduling class for the per-CPU idle tasks: */ @@ -107,4 +128,9 @@ .prio_changed = prio_changed_idle, .switched_to = switched_to_idle, .update_curr = update_curr_idle, +#ifdef CONFIG_SCHED_HMP + .inc_hmp_sched_stats = inc_hmp_sched_stats_idle, + .dec_hmp_sched_stats = dec_hmp_sched_stats_idle, + .fixup_hmp_sched_stats = fixup_hmp_sched_stats_idle, +#endif }; diff -ruw linux-4.4.115/kernel/sched/Makefile linux-4.4.115-fbx/kernel/sched/Makefile --- linux-4.4.115/kernel/sched/Makefile 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/kernel/sched/Makefile 2019-01-22 16:16:28.691293387 +0100 @@ -2,6 +2,10 @@ CFLAGS_REMOVE_clock.o = $(CC_FLAGS_FTRACE) endif +# These files are disabled because they produce non-interesting flaky coverage +# that is not a function of syscall inputs. E.g. involuntary context switches. +KCOV_INSTRUMENT := n + ifneq ($(CONFIG_SCHED_OMIT_FRAME_POINTER),y) # According to Alan Modra , the -fno-omit-frame-pointer is # needed for x86 only. Why this used to be enabled for all architectures is beyond @@ -13,9 +17,14 @@ obj-y += core.o loadavg.o clock.o cputime.o obj-y += idle_task.o fair.o rt.o deadline.o stop_task.o -obj-y += wait.o completion.o idle.o -obj-$(CONFIG_SMP) += cpupri.o cpudeadline.o +obj-y += wait.o completion.o idle.o sched_avg.o +obj-$(CONFIG_SMP) += cpupri.o cpudeadline.o energy.o +obj-$(CONFIG_SCHED_HMP) += hmp.o boost.o obj-$(CONFIG_SCHED_AUTOGROUP) += auto_group.o obj-$(CONFIG_SCHEDSTATS) += stats.o obj-$(CONFIG_SCHED_DEBUG) += debug.o +obj-$(CONFIG_SCHED_TUNE) += tune.o obj-$(CONFIG_CGROUP_CPUACCT) += cpuacct.o +obj-$(CONFIG_SCHED_CORE_CTL) += core_ctl.o +obj-$(CONFIG_CPU_FREQ) += cpufreq.o +obj-$(CONFIG_CPU_FREQ_GOV_SCHEDUTIL) += cpufreq_schedutil.o diff -ruw linux-4.4.115/kernel/sched/rt.c linux-4.4.115-fbx/kernel/sched/rt.c --- linux-4.4.115/kernel/sched/rt.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/kernel/sched/rt.c 2019-10-29 09:26:25.625222574 +0100 @@ -5,8 +5,13 @@ #include "sched.h" +#include #include #include +#include +#include + +#include "tune.h" int sched_rr_timeslice = RR_TIMESLICE; @@ -253,8 +258,12 @@ static inline bool need_pull_rt_task(struct rq *rq, struct task_struct *prev) { - /* Try to pull RT tasks here if we lower this rq's prio */ - return rq->rt.highest_prio.curr > prev->prio; + /* + * Try to pull RT tasks here if we lower this rq's prio and cpu is not + * isolated + */ + return rq->rt.highest_prio.curr > prev->prio && + !cpu_isolated(cpu_of(rq)); } static inline int rt_overloaded(struct rq *rq) @@ -425,7 +434,7 @@ static inline int on_rt_rq(struct sched_rt_entity *rt_se) { - return !list_empty(&rt_se->run_list); + return rt_se->on_rq; } #ifdef CONFIG_RT_GROUP_SCHED @@ -471,8 +480,8 @@ return rt_se->my_q; } -static void enqueue_rt_entity(struct sched_rt_entity *rt_se, bool head); -static void dequeue_rt_entity(struct sched_rt_entity *rt_se); +static void enqueue_rt_entity(struct sched_rt_entity *rt_se, unsigned int flags); +static void dequeue_rt_entity(struct sched_rt_entity *rt_se, unsigned int flags); static void sched_rt_rq_enqueue(struct rt_rq *rt_rq) { @@ -488,7 +497,7 @@ if (!rt_se) enqueue_top_rt_rq(rt_rq); else if (!on_rt_rq(rt_se)) - enqueue_rt_entity(rt_se, false); + enqueue_rt_entity(rt_se, 0); if (rt_rq->highest_prio.curr < curr->prio) resched_curr(rq); @@ -505,7 +514,7 @@ if (!rt_se) dequeue_top_rt_rq(rt_rq); else if (on_rt_rq(rt_se)) - dequeue_rt_entity(rt_se); + dequeue_rt_entity(rt_se, 0); } static inline int rt_rq_throttled(struct rt_rq *rt_rq) @@ -878,6 +887,51 @@ return rt_task_of(rt_se)->prio; } +static void dump_throttled_rt_tasks(struct rt_rq *rt_rq) +{ + struct rt_prio_array *array = &rt_rq->active; + struct sched_rt_entity *rt_se; + char buf[500]; + char *pos = buf; + char *end = buf + sizeof(buf); + int idx; + + pos += snprintf(pos, sizeof(buf), + "sched: RT throttling activated for rt_rq %p (cpu %d)\n", + rt_rq, cpu_of(rq_of_rt_rq(rt_rq))); + + if (bitmap_empty(array->bitmap, MAX_RT_PRIO)) + goto out; + + pos += snprintf(pos, end - pos, "potential CPU hogs:\n"); + idx = sched_find_first_bit(array->bitmap); + while (idx < MAX_RT_PRIO) { + list_for_each_entry(rt_se, array->queue + idx, run_list) { + struct task_struct *p; + + if (!rt_entity_is_task(rt_se)) + continue; + + p = rt_task_of(rt_se); + if (pos < end) + pos += snprintf(pos, end - pos, "\t%s (%d)\n", + p->comm, p->pid); + } + idx = find_next_bit(array->bitmap, MAX_RT_PRIO, idx + 1); + } +out: +#ifdef CONFIG_PANIC_ON_RT_THROTTLING + /* + * Use pr_err() in the BUG() case since printk_sched() will + * not get flushed and deadlock is not a concern. + */ + pr_err("%s", buf); + BUG(); +#else + printk_deferred("%s", buf); +#endif +} + static int sched_rt_runtime_exceeded(struct rt_rq *rt_rq) { u64 runtime = sched_rt_runtime(rt_rq); @@ -901,8 +955,14 @@ * but accrue some time due to boosting. */ if (likely(rt_b->rt_runtime)) { + static bool once = false; + rt_rq->rt_throttled = 1; - printk_deferred_once("sched: RT throttling activated\n"); + + if (!once) { + once = true; + dump_throttled_rt_tasks(rt_rq); + } } else { /* * In case we did anyway, make it go away, @@ -921,6 +981,70 @@ return 0; } +#define RT_SCHEDTUNE_INTERVAL 50000000ULL + +static enum hrtimer_restart rt_schedtune_timer(struct hrtimer *timer) +{ + struct sched_rt_entity *rt_se = container_of(timer, + struct sched_rt_entity, + schedtune_timer); + struct task_struct *p = rt_task_of(rt_se); + struct rq *rq = task_rq(p); + + raw_spin_lock(&rq->lock); + + /* + * Nothing to do if: + * - task has switched runqueues + * - task isn't RT anymore + */ + if (rq != task_rq(p) || (p->sched_class != &rt_sched_class)) + goto out; + + /* + * If task got enqueued back during callback time, it means we raced + * with the enqueue on another cpu, that's Ok, just do nothing as + * enqueue path would have tried to cancel us and we shouldn't run + * Also check the schedtune_enqueued flag as class-switch on a + * sleeping task may have already canceled the timer and done dq + */ + if (p->on_rq || !rt_se->schedtune_enqueued) + goto out; + + /* + * RT task is no longer active, cancel boost + */ + rt_se->schedtune_enqueued = false; + schedtune_dequeue_task(p, cpu_of(rq)); + cpufreq_update_this_cpu(rq, SCHED_CPUFREQ_RT); +out: + raw_spin_unlock(&rq->lock); + + /* + * This can free the task_struct if no more references. + */ + put_task_struct(p); + + return HRTIMER_NORESTART; +} + +void init_rt_schedtune_timer(struct sched_rt_entity *rt_se) +{ + struct hrtimer *timer = &rt_se->schedtune_timer; + + hrtimer_init(timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL); + timer->function = rt_schedtune_timer; + rt_se->schedtune_enqueued = false; +} + +static void start_schedtune_timer(struct sched_rt_entity *rt_se) +{ + struct hrtimer *timer = &rt_se->schedtune_timer; + + hrtimer_start(timer, ns_to_ktime(RT_SCHEDTUNE_INTERVAL), + HRTIMER_MODE_REL_PINNED); +} + /* * Update the current task's runtime statistics. Skip current tasks that * are not in our scheduling class. @@ -938,6 +1062,9 @@ if (unlikely((s64)delta_exec <= 0)) return; + /* Kick cpufreq (see the comment in kernel/sched/sched.h). */ + cpufreq_update_this_cpu(rq, SCHED_CPUFREQ_RT); + schedstat_set(curr->se.statistics.exec_max, max(curr->se.statistics.exec_max, delta_exec)); @@ -1119,6 +1246,41 @@ #endif /* CONFIG_RT_GROUP_SCHED */ +#ifdef CONFIG_SCHED_HMP + +static void +inc_hmp_sched_stats_rt(struct rq *rq, struct task_struct *p) +{ + inc_cumulative_runnable_avg(&rq->hmp_stats, p); +} + +static void +dec_hmp_sched_stats_rt(struct rq *rq, struct task_struct *p) +{ + dec_cumulative_runnable_avg(&rq->hmp_stats, p); +} + +static void +fixup_hmp_sched_stats_rt(struct rq *rq, struct task_struct *p, + u32 new_task_load, u32 new_pred_demand) +{ + s64 task_load_delta = (s64)new_task_load - task_load(p); + s64 pred_demand_delta = PRED_DEMAND_DELTA; + + fixup_cumulative_runnable_avg(&rq->hmp_stats, p, task_load_delta, + pred_demand_delta); +} + +#else /* CONFIG_SCHED_HMP */ + +static inline void +inc_hmp_sched_stats_rt(struct rq *rq, struct task_struct *p) { } + +static inline void +dec_hmp_sched_stats_rt(struct rq *rq, struct task_struct *p) { } + +#endif /* CONFIG_SCHED_HMP */ + static inline unsigned int rt_se_nr_running(struct sched_rt_entity *rt_se) { @@ -1155,7 +1317,30 @@ dec_rt_group(rt_se, rt_rq); } -static void __enqueue_rt_entity(struct sched_rt_entity *rt_se, bool head) +/* + * Change rt_se->run_list location unless SAVE && !MOVE + * + * assumes ENQUEUE/DEQUEUE flags match + */ +static inline bool move_entity(unsigned int flags) +{ + if ((flags & (DEQUEUE_SAVE | DEQUEUE_MOVE)) == DEQUEUE_SAVE) + return false; + + return true; +} + +static void __delist_rt_entity(struct sched_rt_entity *rt_se, struct rt_prio_array *array) +{ + list_del_init(&rt_se->run_list); + + if (list_empty(array->queue + rt_se_prio(rt_se))) + __clear_bit(rt_se_prio(rt_se), array->bitmap); + + rt_se->on_list = 0; +} + +static void __enqueue_rt_entity(struct sched_rt_entity *rt_se, unsigned int flags) { struct rt_rq *rt_rq = rt_rq_of_se(rt_se); struct rt_prio_array *array = &rt_rq->active; @@ -1168,26 +1353,37 @@ * get throttled and the current group doesn't have any other * active members. */ - if (group_rq && (rt_rq_throttled(group_rq) || !group_rq->rt_nr_running)) + if (group_rq && (rt_rq_throttled(group_rq) || !group_rq->rt_nr_running)) { + if (rt_se->on_list) + __delist_rt_entity(rt_se, array); return; + } - if (head) + if (move_entity(flags)) { + WARN_ON_ONCE(rt_se->on_list); + if (flags & ENQUEUE_HEAD) list_add(&rt_se->run_list, queue); else list_add_tail(&rt_se->run_list, queue); + __set_bit(rt_se_prio(rt_se), array->bitmap); + rt_se->on_list = 1; + } + rt_se->on_rq = 1; inc_rt_tasks(rt_se, rt_rq); } -static void __dequeue_rt_entity(struct sched_rt_entity *rt_se) +static void __dequeue_rt_entity(struct sched_rt_entity *rt_se, unsigned int flags) { struct rt_rq *rt_rq = rt_rq_of_se(rt_se); struct rt_prio_array *array = &rt_rq->active; - list_del_init(&rt_se->run_list); - if (list_empty(array->queue + rt_se_prio(rt_se))) - __clear_bit(rt_se_prio(rt_se), array->bitmap); + if (move_entity(flags)) { + WARN_ON_ONCE(!rt_se->on_list); + __delist_rt_entity(rt_se, array); + } + rt_se->on_rq = 0; dec_rt_tasks(rt_se, rt_rq); } @@ -1196,7 +1392,7 @@ * Because the prio of an upper entry depends on the lower * entries, we must remove entries top - down. */ -static void dequeue_rt_stack(struct sched_rt_entity *rt_se) +static void dequeue_rt_stack(struct sched_rt_entity *rt_se, unsigned int flags) { struct sched_rt_entity *back = NULL; @@ -1209,31 +1405,31 @@ for (rt_se = back; rt_se; rt_se = rt_se->back) { if (on_rt_rq(rt_se)) - __dequeue_rt_entity(rt_se); + __dequeue_rt_entity(rt_se, flags); } } -static void enqueue_rt_entity(struct sched_rt_entity *rt_se, bool head) +static void enqueue_rt_entity(struct sched_rt_entity *rt_se, unsigned int flags) { struct rq *rq = rq_of_rt_se(rt_se); - dequeue_rt_stack(rt_se); + dequeue_rt_stack(rt_se, flags); for_each_sched_rt_entity(rt_se) - __enqueue_rt_entity(rt_se, head); + __enqueue_rt_entity(rt_se, flags); enqueue_top_rt_rq(&rq->rt); } -static void dequeue_rt_entity(struct sched_rt_entity *rt_se) +static void dequeue_rt_entity(struct sched_rt_entity *rt_se, unsigned int flags) { struct rq *rq = rq_of_rt_se(rt_se); - dequeue_rt_stack(rt_se); + dequeue_rt_stack(rt_se, flags); for_each_sched_rt_entity(rt_se) { struct rt_rq *rt_rq = group_rt_rq(rt_se); if (rt_rq && rt_rq->rt_nr_running) - __enqueue_rt_entity(rt_se, false); + __enqueue_rt_entity(rt_se, flags); } enqueue_top_rt_rq(&rq->rt); } @@ -1249,10 +1445,38 @@ if (flags & ENQUEUE_WAKEUP) rt_se->timeout = 0; - enqueue_rt_entity(rt_se, flags & ENQUEUE_HEAD); + enqueue_rt_entity(rt_se, flags); + inc_hmp_sched_stats_rt(rq, p); if (!task_current(rq, p) && p->nr_cpus_allowed > 1) enqueue_pushable_task(rq, p); + + if (!schedtune_task_boost(p)) + return; + + /* + * If schedtune timer is active, that means a boost was already + * done, just cancel the timer so that deboost doesn't happen. + * Otherwise, increase the boost. If an enqueued timer was + * cancelled, put the task reference. + */ + if (hrtimer_try_to_cancel(&rt_se->schedtune_timer) == 1) + put_task_struct(p); + + /* + * schedtune_enqueued can be true in the following situation: + * enqueue_task_rt grabs rq lock before timer fires + * or before its callback acquires rq lock + * schedtune_enqueued can be false if timer callback is running + * and timer just released rq lock, or if the timer finished + * running and canceling the boost + */ + if (rt_se->schedtune_enqueued) + return; + + rt_se->schedtune_enqueued = true; + schedtune_enqueue_task(p, cpu_of(rq)); + cpufreq_update_this_cpu(rq, SCHED_CPUFREQ_RT); } static void dequeue_task_rt(struct rq *rq, struct task_struct *p, int flags) @@ -1260,9 +1484,23 @@ struct sched_rt_entity *rt_se = &p->rt; update_curr_rt(rq); - dequeue_rt_entity(rt_se); + dequeue_rt_entity(rt_se, flags); + dec_hmp_sched_stats_rt(rq, p); dequeue_pushable_task(rq, p); + + if (!rt_se->schedtune_enqueued) + return; + + if (flags == DEQUEUE_SLEEP) { + get_task_struct(p); + start_schedtune_timer(rt_se); + return; + } + + rt_se->schedtune_enqueued = false; + schedtune_dequeue_task(p, cpu_of(rq)); + cpufreq_update_this_cpu(rq, SCHED_CPUFREQ_RT); } /* @@ -1302,11 +1540,77 @@ #ifdef CONFIG_SMP static int find_lowest_rq(struct task_struct *task); +#ifdef CONFIG_SCHED_HMP +static int +select_task_rq_rt_hmp(struct task_struct *p, int cpu, int sd_flag, int flags) +{ + int target; + + rcu_read_lock(); + target = find_lowest_rq(p); + if (target != -1) + cpu = target; + rcu_read_unlock(); + + return cpu; +} +#endif + +/* + * Return whether the task on the given cpu is currently non-preemptible + * while handling a potentially long softint, or if the task is likely + * to block preemptions soon because it is a ksoftirq thread that is + * handling slow softints. + */ +bool +task_may_not_preempt(struct task_struct *task, int cpu) +{ + __u32 softirqs = per_cpu(active_softirqs, cpu) | + __IRQ_STAT(cpu, __softirq_pending); + struct task_struct *cpu_ksoftirqd = per_cpu(ksoftirqd, cpu); + + return ((softirqs & LONG_SOFTIRQ_MASK) && + (task == cpu_ksoftirqd || + task_thread_info(task)->preempt_count & SOFTIRQ_MASK)); +} + +/* + * Perform a schedtune dequeue and cancelation of boost timers if needed. + * Should be called only with the rq->lock held. + */ +static void schedtune_dequeue_rt(struct rq *rq, struct task_struct *p) +{ + struct sched_rt_entity *rt_se = &p->rt; + + BUG_ON(!raw_spin_is_locked(&rq->lock)); + + if (!rt_se->schedtune_enqueued) + return; + + /* + * Incase of class change cancel any active timers. If an enqueued + * timer was cancelled, put the task ref. + */ + if (hrtimer_try_to_cancel(&rt_se->schedtune_timer) == 1) + put_task_struct(p); + + /* schedtune_enqueued is true, deboost it */ + rt_se->schedtune_enqueued = false; + schedtune_dequeue_task(p, task_cpu(p)); + cpufreq_update_this_cpu(rq, SCHED_CPUFREQ_RT); +} + static int -select_task_rq_rt(struct task_struct *p, int cpu, int sd_flag, int flags) +select_task_rq_rt(struct task_struct *p, int cpu, int sd_flag, int flags, + int sibling_count_hint) { struct task_struct *curr; struct rq *rq; + bool may_not_preempt; + +#ifdef CONFIG_SCHED_HMP + return select_task_rq_rt_hmp(p, cpu, sd_flag, flags); +#endif /* For anything but wake ups, just return the task_cpu */ if (sd_flag != SD_BALANCE_WAKE && sd_flag != SD_BALANCE_FORK) @@ -1318,7 +1622,17 @@ curr = READ_ONCE(rq->curr); /* unlocked access */ /* - * If the current task on @p's runqueue is an RT task, then + * If the current task on @p's runqueue is a softirq task, + * it may run without preemption for a time that is + * ill-suited for a waiting RT task. Therefore, try to + * wake this RT task on another runqueue. + * + * Also, if the current task on @p's runqueue is an RT task, then + * it may run without preemption for a time that is + * ill-suited for a waiting RT task. Therefore, try to + * wake this RT task on another runqueue. + * + * Also, if the current task on @p's runqueue is an RT task, then * try to see if we can wake this RT task up on another * runqueue. Otherwise simply start this RT task * on its current runqueue. @@ -1339,22 +1653,40 @@ * This test is optimistic, if we get it wrong the load-balancer * will have to sort it out. */ - if (curr && unlikely(rt_task(curr)) && + may_not_preempt = task_may_not_preempt(curr, cpu); + if (may_not_preempt || + (unlikely(rt_task(curr)) && (curr->nr_cpus_allowed < 2 || - curr->prio <= p->prio)) { + curr->prio <= p->prio))) { int target = find_lowest_rq(p); /* - * Don't bother moving it if the destination CPU is - * not running a lower priority task. + * If cpu is non-preemptible, prefer remote cpu + * even if it's running a higher-prio task. + * Otherwise: Don't bother moving it if the + * destination CPU is not running a lower priority task. */ if (target != -1 && - p->prio < cpu_rq(target)->rt.highest_prio.curr) + (may_not_preempt || + p->prio < cpu_rq(target)->rt.highest_prio.curr)) cpu = target; } rcu_read_unlock(); out: + /* + * If previous CPU was different, make sure to cancel any active + * schedtune timers and deboost. + */ + if (task_cpu(p) != cpu) { + unsigned long fl; + struct rq *prq = task_rq(p); + + raw_spin_lock_irqsave(&prq->lock, fl); + schedtune_dequeue_rt(prq, p); + raw_spin_unlock_irqrestore(&prq->lock, fl); + } + return cpu; } @@ -1545,6 +1877,109 @@ static DEFINE_PER_CPU(cpumask_var_t, local_cpu_mask); +#ifdef CONFIG_SCHED_HMP + +static int find_lowest_rq_hmp(struct task_struct *task) +{ + struct cpumask *lowest_mask = *this_cpu_ptr(&local_cpu_mask); + struct cpumask candidate_mask = CPU_MASK_NONE; + struct sched_cluster *cluster; + int best_cpu = -1; + int prev_cpu = task_cpu(task); + u64 cpu_load, min_load = ULLONG_MAX; + int i; + int restrict_cluster; + int boost_on_big; + int pack_task, wakeup_latency, least_wakeup_latency = INT_MAX; + + boost_on_big = sched_boost() == FULL_THROTTLE_BOOST && + sched_boost_policy() == SCHED_BOOST_ON_BIG; + + restrict_cluster = sysctl_sched_restrict_cluster_spill; + + /* Make sure the mask is initialized first */ + if (unlikely(!lowest_mask)) + return best_cpu; + + if (task->nr_cpus_allowed == 1) + return best_cpu; /* No other targets possible */ + + if (!cpupri_find(&task_rq(task)->rd->cpupri, task, lowest_mask)) + return best_cpu; /* No targets found */ + + pack_task = is_short_burst_task(task); + + /* + * At this point we have built a mask of cpus representing the + * lowest priority tasks in the system. Now we want to elect + * the best one based on our affinity and topology. + */ + +retry: + for_each_sched_cluster(cluster) { + if (boost_on_big && cluster->capacity != max_possible_capacity) + continue; + + cpumask_and(&candidate_mask, &cluster->cpus, lowest_mask); + cpumask_andnot(&candidate_mask, &candidate_mask, + cpu_isolated_mask); + /* + * When placement boost is active, if there is no eligible CPU + * in the highest capacity cluster, we fallback to the other + * clusters. So clear the CPUs of the traversed cluster from + * the lowest_mask. + */ + if (unlikely(boost_on_big)) + cpumask_andnot(lowest_mask, lowest_mask, + &cluster->cpus); + + if (cpumask_empty(&candidate_mask)) + continue; + + for_each_cpu(i, &candidate_mask) { + if (sched_cpu_high_irqload(i)) + continue; + + cpu_load = cpu_rq(i)->hmp_stats.cumulative_runnable_avg; + if (!restrict_cluster) + cpu_load = scale_load_to_cpu(cpu_load, i); + + if (pack_task) { + wakeup_latency = cpu_rq(i)->wakeup_latency; + + if (wakeup_latency > least_wakeup_latency) + continue; + + if (wakeup_latency < least_wakeup_latency) { + least_wakeup_latency = wakeup_latency; + min_load = cpu_load; + best_cpu = i; + continue; + } + } + + if (cpu_load < min_load || + (cpu_load == min_load && + (i == prev_cpu || (best_cpu != prev_cpu && + cpus_share_cache(prev_cpu, i))))) { + min_load = cpu_load; + best_cpu = i; + } + } + + if (restrict_cluster && best_cpu != -1) + break; + } + + if (unlikely(boost_on_big && best_cpu == -1)) { + boost_on_big = 0; + goto retry; + } + + return best_cpu; +} +#endif /* CONFIG_SCHED_HMP */ + static int find_lowest_rq(struct task_struct *task) { struct sched_domain *sd; @@ -1552,6 +1987,10 @@ int this_cpu = smp_processor_id(); int cpu = task_cpu(task); +#ifdef CONFIG_SCHED_HMP + return find_lowest_rq_hmp(task); +#endif + /* Make sure the mask is initialized first */ if (unlikely(!lowest_mask)) return -1; @@ -1768,9 +2207,13 @@ goto retry; } + next_task->on_rq = TASK_ON_RQ_MIGRATING; deactivate_task(rq, next_task, 0); + next_task->on_rq = TASK_ON_RQ_MIGRATING; set_task_cpu(next_task, lowest_rq->cpu); + next_task->on_rq = TASK_ON_RQ_QUEUED; activate_task(lowest_rq, next_task, 0); + next_task->on_rq = TASK_ON_RQ_QUEUED; ret = 1; resched_curr(lowest_rq); @@ -2034,9 +2477,13 @@ resched = true; + p->on_rq = TASK_ON_RQ_MIGRATING; deactivate_task(src_rq, p, 0); + p->on_rq = TASK_ON_RQ_MIGRATING; set_task_cpu(p, this_cpu); + p->on_rq = TASK_ON_RQ_QUEUED; activate_task(this_rq, p, 0); + p->on_rq = TASK_ON_RQ_QUEUED; /* * We continue with the search, just in * case there's an even higher prio task @@ -2096,13 +2543,21 @@ static void switched_from_rt(struct rq *rq, struct task_struct *p) { /* + * On class switch from rt, always cancel active schedtune timers, + * this handles the cases where we switch class for a task that is + * already rt-dequeued but has a running timer. + */ + schedtune_dequeue_rt(rq, p); + + /* * If there are other RT tasks then we will reschedule * and the scheduling of the other RT tasks will handle * the balancing. But if we are the last RT task * we may need to handle the pulling of RT tasks * now. */ - if (!task_on_rq_queued(p) || rq->rt.rt_nr_running) + if (!task_on_rq_queued(p) || rq->rt.rt_nr_running || + cpu_isolated(cpu_of(rq))) return; queue_pull_task(rq); @@ -2117,6 +2572,7 @@ GFP_KERNEL, cpu_to_node(i)); } } + #endif /* CONFIG_SMP */ /* @@ -2290,6 +2746,11 @@ .switched_to = switched_to_rt, .update_curr = update_curr_rt, +#ifdef CONFIG_SCHED_HMP + .inc_hmp_sched_stats = inc_hmp_sched_stats_rt, + .dec_hmp_sched_stats = dec_hmp_sched_stats_rt, + .fixup_hmp_sched_stats = fixup_hmp_sched_stats_rt, +#endif }; #ifdef CONFIG_SCHED_DEBUG diff -ruw linux-4.4.115/kernel/sched/sched.h linux-4.4.115-fbx/kernel/sched/sched.h --- linux-4.4.115/kernel/sched/sched.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/kernel/sched/sched.h 2019-10-29 09:26:25.625222574 +0100 @@ -27,6 +27,7 @@ extern atomic_long_t calc_load_tasks; extern void calc_global_load_tick(struct rq *this_rq); + extern long calc_load_fold_active(struct rq *this_rq); #ifdef CONFIG_SMP @@ -240,6 +241,10 @@ struct task_group { struct cgroup_subsys_state css; +#ifdef CONFIG_SCHED_HMP + bool upmigrate_discouraged; +#endif + #ifdef CONFIG_FAIR_GROUP_SCHED /* schedulable entities of this group on each cpu */ struct sched_entity **se; @@ -308,7 +313,7 @@ extern void free_fair_sched_group(struct task_group *tg); extern int alloc_fair_sched_group(struct task_group *tg, struct task_group *parent); -extern void unregister_fair_sched_group(struct task_group *tg, int cpu); +extern void unregister_fair_sched_group(struct task_group *tg); extern void init_tg_cfs_entry(struct task_group *tg, struct cfs_rq *cfs_rq, struct sched_entity *se, int cpu, struct sched_entity *parent); @@ -335,14 +340,106 @@ #ifdef CONFIG_FAIR_GROUP_SCHED extern int sched_group_set_shares(struct task_group *tg, unsigned long shares); -#endif +#ifdef CONFIG_SMP +extern void set_task_rq_fair(struct sched_entity *se, + struct cfs_rq *prev, struct cfs_rq *next); +#else /* !CONFIG_SMP */ +static inline void set_task_rq_fair(struct sched_entity *se, + struct cfs_rq *prev, struct cfs_rq *next) { } +#endif /* CONFIG_SMP */ +#endif /* CONFIG_FAIR_GROUP_SCHED */ + +extern struct task_group *css_tg(struct cgroup_subsys_state *css); #else /* CONFIG_CGROUP_SCHED */ struct cfs_bandwidth { }; #endif /* CONFIG_CGROUP_SCHED */ +#ifdef CONFIG_SCHED_HMP + +#define NUM_TRACKED_WINDOWS 2 +#define NUM_LOAD_INDICES 1000 + +struct hmp_sched_stats { + int nr_big_tasks; + u64 cumulative_runnable_avg; + u64 pred_demands_sum; +}; + +struct load_subtractions { + u64 window_start; + u64 subs; + u64 new_subs; +}; + +struct group_cpu_time { + u64 curr_runnable_sum; + u64 prev_runnable_sum; + u64 nt_curr_runnable_sum; + u64 nt_prev_runnable_sum; +}; + +struct sched_cluster { + raw_spinlock_t load_lock; + struct list_head list; + struct cpumask cpus; + int id; + int max_power_cost; + int min_power_cost; + int max_possible_capacity; + int capacity; + int efficiency; /* Differentiate cpus with different IPC capability */ + int load_scale_factor; + unsigned int exec_scale_factor; + /* + * max_freq = user maximum + * max_mitigated_freq = thermal defined maximum + * max_possible_freq = maximum supported by hardware + */ + unsigned int cur_freq, max_freq, max_mitigated_freq, min_freq; + unsigned int max_possible_freq; + bool freq_init_done; + int dstate, dstate_wakeup_latency, dstate_wakeup_energy; + unsigned int static_cluster_pwr_cost; + int notifier_sent; + bool wake_up_idle; + atomic64_t last_cc_update; + atomic64_t cycles; +}; + +extern unsigned long all_cluster_ids[]; + +static inline int cluster_first_cpu(struct sched_cluster *cluster) +{ + return cpumask_first(&cluster->cpus); +} + +struct related_thread_group { + int id; + raw_spinlock_t lock; + struct list_head tasks; + struct list_head list; + struct sched_cluster *preferred_cluster; + struct rcu_head rcu; + u64 last_update; +}; + +extern struct list_head cluster_head; +extern int num_clusters; +extern struct sched_cluster *sched_cluster[NR_CPUS]; + +struct cpu_cycle { + u64 cycles; + u64 time; +}; + +#define for_each_sched_cluster(cluster) \ + list_for_each_entry_rcu(cluster, &cluster_head, list) + +#endif /* CONFIG_SCHED_HMP */ + /* CFS-related fields in a runqueue */ struct cfs_rq { struct load_weight load; @@ -376,6 +473,7 @@ unsigned long runnable_load_avg; #ifdef CONFIG_FAIR_GROUP_SCHED unsigned long tg_load_avg_contrib; + unsigned long propagate_avg; #endif atomic_long_t removed_load_avg, removed_util_avg; #ifndef CONFIG_64BIT @@ -411,6 +509,11 @@ struct task_group *tg; /* group that "owns" this runqueue */ #ifdef CONFIG_CFS_BANDWIDTH + +#ifdef CONFIG_SCHED_HMP + struct hmp_sched_stats hmp_stats; +#endif + int runtime_enabled; u64 runtime_expires; s64 runtime_remaining; @@ -500,10 +603,18 @@ #else struct dl_bw dl_bw; #endif + /* This is the "average utilization" for this runqueue */ + s64 avg_bw; }; #ifdef CONFIG_SMP +struct max_cpu_capacity { + raw_spinlock_t lock; + unsigned long val; + int cpu; +}; + /* * We add the notion of a root-domain which will be used to define per-domain * variables. Each exclusive cpuset essentially defines an island domain by @@ -522,6 +633,9 @@ /* Indicate more than one runnable task for any CPU */ bool overload; + /* Indicate one or more cpus over-utilized (tipping point) */ + bool overutilized; + /* * The bit corresponding to a CPU gets set here if such CPU has more * than one runnable -deadline task (as it is below for RT tasks). @@ -550,6 +664,12 @@ */ cpumask_var_t rto_mask; struct cpupri cpupri; + + /* Maximum cpu capacity in the system. */ + struct max_cpu_capacity max_cpu_capacity; + + /* First cpu with maximum and minimum original capacity */ + int max_cap_orig_cpu, min_cap_orig_cpu; }; extern struct root_domain def_root_domain; @@ -582,6 +702,7 @@ #define CPU_LOAD_IDX_MAX 5 unsigned long cpu_load[CPU_LOAD_IDX_MAX]; unsigned long last_load_update_tick; + unsigned int misfit_task; #ifdef CONFIG_NO_HZ_COMMON u64 nohz_stamp; unsigned long nohz_flags; @@ -589,6 +710,14 @@ #ifdef CONFIG_NO_HZ_FULL unsigned long last_sched_tick; #endif + +#ifdef CONFIG_CPU_QUIET + /* time-based average load */ + u64 nr_last_stamp; + u64 nr_running_integral; + seqcount_t ave_seqcnt; +#endif + /* capture load from *all* tasks on this cpu: */ struct load_weight load; unsigned long nr_load_updates; @@ -601,6 +730,7 @@ #ifdef CONFIG_FAIR_GROUP_SCHED /* list of leaf cfs_rq on this cpu: */ struct list_head leaf_cfs_rq_list; + struct list_head *tmp_alone_branch; #endif /* CONFIG_FAIR_GROUP_SCHED */ /* @@ -634,6 +764,7 @@ /* For active balancing */ int active_balance; int push_cpu; + struct task_struct *push_task; struct cpu_stop_work active_balance_work; /* cpu of this runqueue: */ int cpu; @@ -650,6 +781,50 @@ u64 max_idle_balance_cost; #endif +#ifdef CONFIG_SCHED_HMP + struct sched_cluster *cluster; + struct cpumask freq_domain_cpumask; + struct hmp_sched_stats hmp_stats; + + int cstate, wakeup_latency, wakeup_energy; + u64 window_start; + unsigned long hmp_flags; + + u64 cur_irqload; + u64 avg_irqload; + u64 irqload_ts; + unsigned int static_cpu_pwr_cost; + struct task_struct *ed_task; + struct cpu_cycle cc; + u64 old_busy_time, old_busy_time_group; + u64 old_estimated_time; + u64 curr_runnable_sum; + u64 prev_runnable_sum; + u64 nt_curr_runnable_sum; + u64 nt_prev_runnable_sum; + struct group_cpu_time grp_time; + struct load_subtractions load_subs[NUM_TRACKED_WINDOWS]; + DECLARE_BITMAP_ARRAY(top_tasks_bitmap, + NUM_TRACKED_WINDOWS, NUM_LOAD_INDICES); + u8 *top_tasks[NUM_TRACKED_WINDOWS]; + u8 curr_table; + int prev_top; + int curr_top; +#endif + +#ifdef CONFIG_SCHED_WALT + u64 cumulative_runnable_avg; + u64 window_start; + u64 curr_runnable_sum; + u64 prev_runnable_sum; + u64 nt_curr_runnable_sum; + u64 nt_prev_runnable_sum; + u64 cur_irqload; + u64 avg_irqload; + u64 irqload_ts; + u64 cum_window_demand; +#endif /* CONFIG_SCHED_WALT */ + #ifdef CONFIG_IRQ_TIME_ACCOUNTING u64 prev_irq_time; #endif @@ -688,6 +863,9 @@ /* try_to_wake_up() stats */ unsigned int ttwu_count; unsigned int ttwu_local; +#ifdef CONFIG_SMP + struct eas_stats eas_stats; +#endif #endif #ifdef CONFIG_SMP @@ -697,6 +875,7 @@ #ifdef CONFIG_CPU_IDLE /* Must be inspected within a rcu lock section */ struct cpuidle_state *idle_state; + int idle_state_idx; #endif }; @@ -846,6 +1025,8 @@ DECLARE_PER_CPU(struct sched_domain *, sd_numa); DECLARE_PER_CPU(struct sched_domain *, sd_busy); DECLARE_PER_CPU(struct sched_domain *, sd_asym); +DECLARE_PER_CPU(struct sched_domain *, sd_ea); +DECLARE_PER_CPU(struct sched_domain *, sd_scs); struct sched_group_capacity { atomic_t ref; @@ -853,7 +1034,9 @@ * CPU capacity of this group, SCHED_LOAD_SCALE being max capacity * for a single CPU. */ - unsigned int capacity; + unsigned long capacity; + unsigned long max_capacity; /* Max per-cpu capacity in group */ + unsigned long min_capacity; /* Min per-CPU capacity in group */ unsigned long next_update; int imbalance; /* XXX unrelated to capacity but shared group state */ /* @@ -870,6 +1053,7 @@ unsigned int group_weight; struct sched_group_capacity *sgc; + const struct sched_group_energy *sge; /* * The CPUs this group covers. @@ -915,6 +1099,648 @@ #include "stats.h" #include "auto_group.h" +enum sched_boost_policy { + SCHED_BOOST_NONE, + SCHED_BOOST_ON_BIG, + SCHED_BOOST_ON_ALL, +}; + +#ifdef CONFIG_SCHED_HMP + +#define WINDOW_STATS_RECENT 0 +#define WINDOW_STATS_MAX 1 +#define WINDOW_STATS_MAX_RECENT_AVG 2 +#define WINDOW_STATS_AVG 3 +#define WINDOW_STATS_INVALID_POLICY 4 + +#define SCHED_UPMIGRATE_MIN_NICE 15 +#define EXITING_TASK_MARKER 0xdeaddead + +#define UP_MIGRATION 1 +#define DOWN_MIGRATION 2 +#define IRQLOAD_MIGRATION 3 + +extern struct mutex policy_mutex; +extern unsigned int sched_ravg_window; +extern unsigned int sched_disable_window_stats; +extern unsigned int max_possible_freq; +extern unsigned int min_max_freq; +extern unsigned int pct_task_load(struct task_struct *p); +extern unsigned int max_possible_efficiency; +extern unsigned int min_possible_efficiency; +extern unsigned int max_capacity; +extern unsigned int min_capacity; +extern unsigned int max_load_scale_factor; +extern unsigned int max_possible_capacity; +extern unsigned int min_max_possible_capacity; +extern unsigned int max_power_cost; +extern unsigned int sched_init_task_load_windows; +extern unsigned int up_down_migrate_scale_factor; +extern unsigned int sysctl_sched_restrict_cluster_spill; +extern unsigned int sched_pred_alert_load; +extern struct sched_cluster init_cluster; +extern unsigned int __read_mostly sched_short_sleep_task_threshold; +extern unsigned int __read_mostly sched_long_cpu_selection_threshold; +extern unsigned int __read_mostly sched_big_waker_task_load; +extern unsigned int __read_mostly sched_small_wakee_task_load; +extern unsigned int __read_mostly sched_spill_load; +extern unsigned int __read_mostly sched_upmigrate; +extern unsigned int __read_mostly sched_downmigrate; +extern unsigned int __read_mostly sysctl_sched_spill_nr_run; +extern unsigned int __read_mostly sched_load_granule; + +extern void init_new_task_load(struct task_struct *p, bool idle_task); +extern u64 sched_ktime_clock(void); +extern int got_boost_kick(void); +extern int register_cpu_cycle_counter_cb(struct cpu_cycle_counter_cb *cb); +extern void update_task_ravg(struct task_struct *p, struct rq *rq, int event, + u64 wallclock, u64 irqtime); +extern bool early_detection_notify(struct rq *rq, u64 wallclock); +extern void clear_ed_task(struct task_struct *p, struct rq *rq); +extern void fixup_busy_time(struct task_struct *p, int new_cpu); +extern void clear_boost_kick(int cpu); +extern void clear_hmp_request(int cpu); +extern void mark_task_starting(struct task_struct *p); +extern void set_window_start(struct rq *rq); +extern void update_cluster_topology(void); +extern void note_task_waking(struct task_struct *p, u64 wallclock); +extern void set_task_last_switch_out(struct task_struct *p, u64 wallclock); +extern void init_clusters(void); +extern void reset_cpu_hmp_stats(int cpu, int reset_cra); +extern unsigned int max_task_load(void); +extern void sched_account_irqtime(int cpu, struct task_struct *curr, + u64 delta, u64 wallclock); +extern void sched_account_irqstart(int cpu, struct task_struct *curr, + u64 wallclock); +extern unsigned int cpu_temp(int cpu); +extern unsigned int nr_eligible_big_tasks(int cpu); +extern int update_preferred_cluster(struct related_thread_group *grp, + struct task_struct *p, u32 old_load); +extern void set_preferred_cluster(struct related_thread_group *grp); +extern void add_new_task_to_grp(struct task_struct *new); +extern unsigned int update_freq_aggregate_threshold(unsigned int threshold); +extern void update_avg_burst(struct task_struct *p); +extern void update_avg(u64 *avg, u64 sample); + +#define NO_BOOST 0 +#define FULL_THROTTLE_BOOST 1 +#define CONSERVATIVE_BOOST 2 +#define RESTRAINED_BOOST 3 + +static inline struct sched_cluster *cpu_cluster(int cpu) +{ + return cpu_rq(cpu)->cluster; +} + +static inline int cpu_capacity(int cpu) +{ + return cpu_rq(cpu)->cluster->capacity; +} + +static inline int cpu_max_possible_capacity(int cpu) +{ + return cpu_rq(cpu)->cluster->max_possible_capacity; +} + +static inline int cpu_load_scale_factor(int cpu) +{ + return cpu_rq(cpu)->cluster->load_scale_factor; +} + +static inline int cpu_efficiency(int cpu) +{ + return cpu_rq(cpu)->cluster->efficiency; +} + +static inline unsigned int cpu_cur_freq(int cpu) +{ + return cpu_rq(cpu)->cluster->cur_freq; +} + +static inline unsigned int cpu_min_freq(int cpu) +{ + return cpu_rq(cpu)->cluster->min_freq; +} + +static inline unsigned int cluster_max_freq(struct sched_cluster *cluster) +{ + /* + * Governor and thermal driver don't know the other party's mitigation + * voting. So struct cluster saves both and return min() for current + * cluster fmax. + */ + return min(cluster->max_mitigated_freq, cluster->max_freq); +} + +static inline unsigned int cpu_max_freq(int cpu) +{ + return cluster_max_freq(cpu_rq(cpu)->cluster); +} + +static inline unsigned int cpu_max_possible_freq(int cpu) +{ + return cpu_rq(cpu)->cluster->max_possible_freq; +} + +static inline int same_cluster(int src_cpu, int dst_cpu) +{ + return cpu_rq(src_cpu)->cluster == cpu_rq(dst_cpu)->cluster; +} + +static inline int cpu_max_power_cost(int cpu) +{ + return cpu_rq(cpu)->cluster->max_power_cost; +} + +static inline int cpu_min_power_cost(int cpu) +{ + return cpu_rq(cpu)->cluster->min_power_cost; +} + +static inline u32 cpu_cycles_to_freq(u64 cycles, u64 period) +{ + return div64_u64(cycles, period); +} + +static inline bool hmp_capable(void) +{ + return max_possible_capacity != min_max_possible_capacity; +} + +static inline bool is_max_capacity_cpu(int cpu) +{ + return cpu_max_possible_capacity(cpu) == max_possible_capacity; +} + +/* + * 'load' is in reference to "best cpu" at its best frequency. + * Scale that in reference to a given cpu, accounting for how bad it is + * in reference to "best cpu". + */ +static inline u64 scale_load_to_cpu(u64 task_load, int cpu) +{ + u64 lsf = cpu_load_scale_factor(cpu); + + if (lsf != 1024) { + task_load *= lsf; + task_load /= 1024; + } + + return task_load; +} + +static inline unsigned int task_load(struct task_struct *p) +{ + return p->ravg.demand; +} + +static inline void +inc_cumulative_runnable_avg(struct hmp_sched_stats *stats, + struct task_struct *p) +{ + u32 task_load; + + if (sched_disable_window_stats) + return; + + task_load = sched_disable_window_stats ? 0 : p->ravg.demand; + + stats->cumulative_runnable_avg += task_load; + stats->pred_demands_sum += p->ravg.pred_demand; +} + +static inline void +dec_cumulative_runnable_avg(struct hmp_sched_stats *stats, + struct task_struct *p) +{ + u32 task_load; + + if (sched_disable_window_stats) + return; + + task_load = sched_disable_window_stats ? 0 : p->ravg.demand; + + stats->cumulative_runnable_avg -= task_load; + + BUG_ON((s64)stats->cumulative_runnable_avg < 0); + + stats->pred_demands_sum -= p->ravg.pred_demand; + BUG_ON((s64)stats->pred_demands_sum < 0); +} + +static inline void +fixup_cumulative_runnable_avg(struct hmp_sched_stats *stats, + struct task_struct *p, s64 task_load_delta, + s64 pred_demand_delta) +{ + if (sched_disable_window_stats) + return; + + stats->cumulative_runnable_avg += task_load_delta; + BUG_ON((s64)stats->cumulative_runnable_avg < 0); + + stats->pred_demands_sum += pred_demand_delta; + BUG_ON((s64)stats->pred_demands_sum < 0); +} + +#define pct_to_real(tunable) \ + (div64_u64((u64)tunable * (u64)max_task_load(), 100)) + +#define real_to_pct(tunable) \ + (div64_u64((u64)tunable * (u64)100, (u64)max_task_load())) + +#define SCHED_HIGH_IRQ_TIMEOUT 3 +static inline u64 sched_irqload(int cpu) +{ + struct rq *rq = cpu_rq(cpu); + s64 delta; + + delta = get_jiffies_64() - rq->irqload_ts; + /* + * Current context can be preempted by irq and rq->irqload_ts can be + * updated by irq context so that delta can be negative. + * But this is okay and we can safely return as this means there + * was recent irq occurrence. + */ + + if (delta < SCHED_HIGH_IRQ_TIMEOUT) + return rq->avg_irqload; + else + return 0; +} + +static inline int sched_cpu_high_irqload(int cpu) +{ + return sched_irqload(cpu) >= sysctl_sched_cpu_high_irqload; +} + +static inline bool task_in_related_thread_group(struct task_struct *p) +{ + return !!(rcu_access_pointer(p->grp) != NULL); +} + +static inline +struct related_thread_group *task_related_thread_group(struct task_struct *p) +{ + return rcu_dereference(p->grp); +} + +#define PRED_DEMAND_DELTA ((s64)new_pred_demand - p->ravg.pred_demand) + +extern void +check_for_freq_change(struct rq *rq, bool check_pred, bool check_groups); + +extern void notify_migration(int src_cpu, int dest_cpu, + bool src_cpu_dead, struct task_struct *p); + +/* Is frequency of two cpus synchronized with each other? */ +static inline int same_freq_domain(int src_cpu, int dst_cpu) +{ + struct rq *rq = cpu_rq(src_cpu); + + if (src_cpu == dst_cpu) + return 1; + + return cpumask_test_cpu(dst_cpu, &rq->freq_domain_cpumask); +} + +#define BOOST_KICK 0 +#define CPU_RESERVED 1 + +static inline int is_reserved(int cpu) +{ + struct rq *rq = cpu_rq(cpu); + + return test_bit(CPU_RESERVED, &rq->hmp_flags); +} + +static inline int mark_reserved(int cpu) +{ + struct rq *rq = cpu_rq(cpu); + + /* Name boost_flags as hmp_flags? */ + return test_and_set_bit(CPU_RESERVED, &rq->hmp_flags); +} + +static inline void clear_reserved(int cpu) +{ + struct rq *rq = cpu_rq(cpu); + + clear_bit(CPU_RESERVED, &rq->hmp_flags); +} + +static inline u64 cpu_cravg_sync(int cpu, int sync) +{ + struct rq *rq = cpu_rq(cpu); + u64 load; + + load = rq->hmp_stats.cumulative_runnable_avg; + + /* + * If load is being checked in a sync wakeup environment, + * we may want to discount the load of the currently running + * task. + */ + if (sync && cpu == smp_processor_id()) { + if (load > rq->curr->ravg.demand) + load -= rq->curr->ravg.demand; + else + load = 0; + } + + return load; +} + +static inline bool is_short_burst_task(struct task_struct *p) +{ + return p->ravg.avg_burst < sysctl_sched_short_burst && + p->ravg.avg_sleep_time > sysctl_sched_short_sleep; +} + +extern void check_for_migration(struct rq *rq, struct task_struct *p); +extern void pre_big_task_count_change(const struct cpumask *cpus); +extern void post_big_task_count_change(const struct cpumask *cpus); +extern void set_hmp_defaults(void); +extern int power_delta_exceeded(unsigned int cpu_cost, unsigned int base_cost); +extern unsigned int power_cost(int cpu, u64 demand); +extern void reset_all_window_stats(u64 window_start, unsigned int window_size); +extern int sched_boost(void); +extern int task_load_will_fit(struct task_struct *p, u64 task_load, int cpu, + enum sched_boost_policy boost_policy); +extern enum sched_boost_policy sched_boost_policy(void); +extern int task_will_fit(struct task_struct *p, int cpu); +extern u64 cpu_load(int cpu); +extern u64 cpu_load_sync(int cpu, int sync); +extern int preferred_cluster(struct sched_cluster *cluster, + struct task_struct *p); +extern void inc_nr_big_task(struct hmp_sched_stats *stats, + struct task_struct *p); +extern void dec_nr_big_task(struct hmp_sched_stats *stats, + struct task_struct *p); +extern void inc_rq_hmp_stats(struct rq *rq, + struct task_struct *p, int change_cra); +extern void dec_rq_hmp_stats(struct rq *rq, + struct task_struct *p, int change_cra); +extern void reset_hmp_stats(struct hmp_sched_stats *stats, int reset_cra); +extern int is_big_task(struct task_struct *p); +extern int upmigrate_discouraged(struct task_struct *p); +extern struct sched_cluster *rq_cluster(struct rq *rq); +extern int nr_big_tasks(struct rq *rq); +extern void fixup_nr_big_tasks(struct hmp_sched_stats *stats, + struct task_struct *p, s64 delta); +extern void reset_task_stats(struct task_struct *p); +extern void reset_cfs_rq_hmp_stats(int cpu, int reset_cra); +extern void _inc_hmp_sched_stats_fair(struct rq *rq, + struct task_struct *p, int change_cra); +extern u64 cpu_upmigrate_discourage_read_u64(struct cgroup_subsys_state *css, + struct cftype *cft); +extern int cpu_upmigrate_discourage_write_u64(struct cgroup_subsys_state *css, + struct cftype *cft, u64 upmigrate_discourage); +extern void sched_boost_parse_dt(void); +extern void clear_top_tasks_bitmap(unsigned long *bitmap); + +#if defined(CONFIG_SCHED_TUNE) && defined(CONFIG_CGROUP_SCHEDTUNE) +extern bool task_sched_boost(struct task_struct *p); +extern int sync_cgroup_colocation(struct task_struct *p, bool insert); +extern bool same_schedtune(struct task_struct *tsk1, struct task_struct *tsk2); +extern void update_cgroup_boost_settings(void); +extern void restore_cgroup_boost_settings(void); + +#else +static inline bool +same_schedtune(struct task_struct *tsk1, struct task_struct *tsk2) +{ + return true; +} + +static inline bool task_sched_boost(struct task_struct *p) +{ + return true; +} + +static inline void update_cgroup_boost_settings(void) { } +static inline void restore_cgroup_boost_settings(void) { } +#endif + +extern int alloc_related_thread_groups(void); + +#else /* CONFIG_SCHED_HMP */ + +struct hmp_sched_stats; +struct related_thread_group; +struct sched_cluster; + +static inline enum sched_boost_policy sched_boost_policy(void) +{ + return SCHED_BOOST_NONE; +} + +static inline bool task_sched_boost(struct task_struct *p) +{ + return true; +} + +static inline int got_boost_kick(void) +{ + return 0; +} + +static inline void update_task_ravg(struct task_struct *p, struct rq *rq, + int event, u64 wallclock, u64 irqtime) { } + +static inline bool early_detection_notify(struct rq *rq, u64 wallclock) +{ + return 0; +} + +static inline void clear_ed_task(struct task_struct *p, struct rq *rq) { } +static inline void fixup_busy_time(struct task_struct *p, int new_cpu) { } +static inline void clear_boost_kick(int cpu) { } +static inline void clear_hmp_request(int cpu) { } +static inline void mark_task_starting(struct task_struct *p) { } +static inline void set_window_start(struct rq *rq) { } +static inline void init_clusters(void) {} +static inline void update_cluster_topology(void) { } +static inline void note_task_waking(struct task_struct *p, u64 wallclock) { } +static inline void set_task_last_switch_out(struct task_struct *p, + u64 wallclock) { } + +static inline int task_will_fit(struct task_struct *p, int cpu) +{ + return 1; +} + +static inline int select_best_cpu(struct task_struct *p, int target, + int reason, int sync) +{ + return 0; +} + +static inline unsigned int power_cost(int cpu, u64 demand) +{ + return SCHED_CAPACITY_SCALE; +} + +static inline int sched_boost(void) +{ + return 0; +} + +static inline int is_big_task(struct task_struct *p) +{ + return 0; +} + +static inline int nr_big_tasks(struct rq *rq) +{ + return 0; +} + +static inline int is_cpu_throttling_imminent(int cpu) +{ + return 0; +} + +static inline int is_task_migration_throttled(struct task_struct *p) +{ + return 0; +} + +static inline unsigned int cpu_temp(int cpu) +{ + return 0; +} + +static inline void +inc_rq_hmp_stats(struct rq *rq, struct task_struct *p, int change_cra) { } + +static inline void +dec_rq_hmp_stats(struct rq *rq, struct task_struct *p, int change_cra) { } + +static inline void +inc_hmp_sched_stats_fair(struct rq *rq, struct task_struct *p) { } + +static inline void +dec_hmp_sched_stats_fair(struct rq *rq, struct task_struct *p) { } + +static inline int +preferred_cluster(struct sched_cluster *cluster, struct task_struct *p) +{ + return 1; +} + +static inline struct sched_cluster *rq_cluster(struct rq *rq) +{ + return NULL; +} + +static inline void init_new_task_load(struct task_struct *p, bool idle_task) +{ +} + +static inline u64 scale_load_to_cpu(u64 load, int cpu) +{ + return load; +} + +static inline unsigned int nr_eligible_big_tasks(int cpu) +{ + return 0; +} + +static inline bool is_max_capacity_cpu(int cpu) { return true; } + +static inline int pct_task_load(struct task_struct *p) { return 0; } + +static inline int cpu_capacity(int cpu) +{ + return SCHED_LOAD_SCALE; +} + +static inline int same_cluster(int src_cpu, int dst_cpu) { return 1; } + +static inline void inc_cumulative_runnable_avg(struct hmp_sched_stats *stats, + struct task_struct *p) +{ +} + +static inline void dec_cumulative_runnable_avg(struct hmp_sched_stats *stats, + struct task_struct *p) +{ +} + +static inline void sched_account_irqtime(int cpu, struct task_struct *curr, + u64 delta, u64 wallclock) +{ +} + +static inline void sched_account_irqstart(int cpu, struct task_struct *curr, + u64 wallclock) +{ +} + +static inline int sched_cpu_high_irqload(int cpu) { return 0; } + +static inline void set_preferred_cluster(struct related_thread_group *grp) { } + +static inline bool task_in_related_thread_group(struct task_struct *p) +{ + return false; +} + +static inline +struct related_thread_group *task_related_thread_group(struct task_struct *p) +{ + return NULL; +} + +static inline u32 task_load(struct task_struct *p) { return 0; } + +static inline int update_preferred_cluster(struct related_thread_group *grp, + struct task_struct *p, u32 old_load) +{ + return 0; +} + +static inline void add_new_task_to_grp(struct task_struct *new) {} + +#define PRED_DEMAND_DELTA (0) + +static inline void +check_for_freq_change(struct rq *rq, bool check_pred, bool check_groups) { } + +static inline void notify_migration(int src_cpu, int dest_cpu, + bool src_cpu_dead, struct task_struct *p) { } + +static inline int same_freq_domain(int src_cpu, int dst_cpu) +{ + return 1; +} + +static inline void check_for_migration(struct rq *rq, struct task_struct *p) { } +static inline void pre_big_task_count_change(void) { } +static inline void post_big_task_count_change(void) { } +static inline void set_hmp_defaults(void) { } + +static inline void clear_reserved(int cpu) { } +static inline void sched_boost_parse_dt(void) {} +static inline int alloc_related_thread_groups(void) { return 0; } + +#define trace_sched_cpu_load(...) +#define trace_sched_cpu_load_lb(...) +#define trace_sched_cpu_load_cgroup(...) +#define trace_sched_cpu_load_wakeup(...) + +static inline void update_avg_burst(struct task_struct *p) {} + +#endif /* CONFIG_SCHED_HMP */ + +/* + * Returns the rq capacity of any rq in a group. This does not play + * well with groups where rq capacity can change independently. + */ +#define group_rq_capacity(group) cpu_capacity(group_first_cpu(group)) + #ifdef CONFIG_CGROUP_SCHED /* @@ -943,6 +1769,7 @@ #endif #ifdef CONFIG_FAIR_GROUP_SCHED + set_task_rq_fair(&p->se, p->se.cfs_rq, tg->cfs_rq[cpu]); p->se.cfs_rq = tg->cfs_rq[cpu]; p->se.parent = tg->se[cpu]; #endif @@ -960,7 +1787,6 @@ { return NULL; } - #endif /* CONFIG_CGROUP_SCHED */ static inline void __set_task_cpu(struct task_struct *p, unsigned int cpu) @@ -973,7 +1799,11 @@ * per-task data have been completed by this moment. */ smp_wmb(); +#ifdef CONFIG_THREAD_INFO_IN_TASK + p->cpu = cpu; +#else task_thread_info(p)->cpu = cpu; +#endif p->wake_cpu = cpu; #endif } @@ -1110,6 +1940,7 @@ #define WF_SYNC 0x01 /* waker goes to sleep after wakeup */ #define WF_FORK 0x02 /* child wakeup after fork */ #define WF_MIGRATED 0x4 /* internal use, task got migrated */ +#define WF_NO_NOTIFIER 0x08 /* do not notify governor */ /* * To aid in avoiding the subversion of "niceness" due to uneven distribution @@ -1164,18 +1995,41 @@ /* 15 */ 119304647, 148102320, 186737708, 238609294, 286331153, }; +/* + * {de,en}queue flags: + * + * DEQUEUE_SLEEP - task is no longer runnable + * ENQUEUE_WAKEUP - task just became runnable + * + * SAVE/RESTORE - an otherwise spurious dequeue/enqueue, done to ensure tasks + * are in a known state which allows modification. Such pairs + * should preserve as much state as possible. + * + * MOVE - paired with SAVE/RESTORE, explicitly does not preserve the location + * in the runqueue. + * + * ENQUEUE_HEAD - place at front of runqueue (tail if not specified) + * ENQUEUE_REPLENISH - CBS (replenish runtime and postpone deadline) + * ENQUEUE_WAKING - sched_class::task_waking was called + * + */ + +#define DEQUEUE_SLEEP 0x01 +#define DEQUEUE_SAVE 0x02 /* matches ENQUEUE_RESTORE */ +#define DEQUEUE_MOVE 0x04 /* matches ENQUEUE_MOVE */ + #define ENQUEUE_WAKEUP 0x01 -#define ENQUEUE_HEAD 0x02 +#define ENQUEUE_RESTORE 0x02 +#define ENQUEUE_MOVE 0x04 + +#define ENQUEUE_HEAD 0x08 +#define ENQUEUE_REPLENISH 0x10 #ifdef CONFIG_SMP -#define ENQUEUE_WAKING 0x04 /* sched_class::task_waking was called */ +#define ENQUEUE_WAKING 0x20 #else #define ENQUEUE_WAKING 0x00 #endif -#define ENQUEUE_REPLENISH 0x08 -#define ENQUEUE_RESTORE 0x10 - -#define DEQUEUE_SLEEP 0x01 -#define DEQUEUE_SAVE 0x02 +#define ENQUEUE_WAKEUP_NEW 0x40 #define RETRY_TASK ((void *)-1UL) @@ -1202,7 +2056,8 @@ void (*put_prev_task) (struct rq *rq, struct task_struct *p); #ifdef CONFIG_SMP - int (*select_task_rq)(struct task_struct *p, int task_cpu, int sd_flag, int flags); + int (*select_task_rq)(struct task_struct *p, int task_cpu, int sd_flag, int flags, + int subling_count_hint); void (*migrate_task_rq)(struct task_struct *p); void (*task_waking) (struct task_struct *task); @@ -1235,8 +2090,17 @@ void (*update_curr) (struct rq *rq); +#define TASK_SET_GROUP 0 +#define TASK_MOVE_GROUP 1 + #ifdef CONFIG_FAIR_GROUP_SCHED - void (*task_move_group) (struct task_struct *p); + void (*task_change_group)(struct task_struct *p, int type); +#endif +#ifdef CONFIG_SCHED_HMP + void (*inc_hmp_sched_stats)(struct rq *rq, struct task_struct *p); + void (*dec_hmp_sched_stats)(struct rq *rq, struct task_struct *p); + void (*fixup_hmp_sched_stats)(struct rq *rq, struct task_struct *p, + u32 new_task_load, u32 new_pred_demand); #endif }; @@ -1258,9 +2122,11 @@ #ifdef CONFIG_SMP +extern void init_max_cpu_capacity(struct max_cpu_capacity *mcc); extern void update_group_capacity(struct sched_domain *sd, int cpu); extern void trigger_load_balance(struct rq *rq); +extern void nohz_balance_clear_nohz_mask(int cpu); extern void idle_enter_fair(struct rq *this_rq); extern void idle_exit_fair(struct rq *this_rq); @@ -1286,6 +2152,17 @@ WARN_ON(!rcu_read_lock_held()); return rq->idle_state; } + +static inline void idle_set_state_idx(struct rq *rq, int idle_state_idx) +{ + rq->idle_state_idx = idle_state_idx; +} + +static inline int idle_get_state_idx(struct rq *rq) +{ + WARN_ON(!rcu_read_lock_held()); + return rq->idle_state_idx; +} #else static inline void idle_set_state(struct rq *rq, struct cpuidle_state *idle_state) @@ -1296,9 +2173,20 @@ { return NULL; } + +static inline void idle_set_state_idx(struct rq *rq, int idle_state_idx) +{ +} + +static inline int idle_get_state_idx(struct rq *rq) +{ + return -1; +} #endif +#ifdef CONFIG_SYSRQ_SCHED_DEBUG extern void sysrq_sched_debug_show(void); +#endif extern void sched_init_granularity(void); extern void update_max_interval(void); @@ -1311,6 +2199,7 @@ extern struct rt_bandwidth def_rt_bandwidth; extern void init_rt_bandwidth(struct rt_bandwidth *rt_b, u64 period, u64 runtime); +extern void init_rt_schedtune_timer(struct sched_rt_entity *rt_se); extern struct dl_bandwidth def_dl_bandwidth; extern void init_dl_bandwidth(struct dl_bandwidth *dl_b, u64 period, u64 runtime); @@ -1319,11 +2208,13 @@ unsigned long to_ratio(u64 period, u64 runtime); extern void init_entity_runnable_average(struct sched_entity *se); +extern void post_init_entity_util_avg(struct sched_entity *se); -static inline void add_nr_running(struct rq *rq, unsigned count) +static inline void __add_nr_running(struct rq *rq, unsigned count) { unsigned prev_nr = rq->nr_running; + sched_update_nr_prod(cpu_of(rq), count, true); rq->nr_running = prev_nr + count; if (prev_nr < 2 && rq->nr_running >= 2) { @@ -1348,11 +2239,49 @@ } } -static inline void sub_nr_running(struct rq *rq, unsigned count) +static inline void __sub_nr_running(struct rq *rq, unsigned count) { + sched_update_nr_prod(cpu_of(rq), count, false); rq->nr_running -= count; } +#ifdef CONFIG_CPU_QUIET +#define NR_AVE_SCALE(x) ((x) << FSHIFT) +static inline u64 do_nr_running_integral(struct rq *rq) +{ + s64 nr, deltax; + u64 nr_running_integral = rq->nr_running_integral; + + deltax = rq->clock_task - rq->nr_last_stamp; + nr = NR_AVE_SCALE(rq->nr_running); + + nr_running_integral += nr * deltax; + + return nr_running_integral; +} + +static inline void add_nr_running(struct rq *rq, unsigned count) +{ + write_seqcount_begin(&rq->ave_seqcnt); + rq->nr_running_integral = do_nr_running_integral(rq); + rq->nr_last_stamp = rq->clock_task; + __add_nr_running(rq, count); + write_seqcount_end(&rq->ave_seqcnt); +} + +static inline void sub_nr_running(struct rq *rq, unsigned count) +{ + write_seqcount_begin(&rq->ave_seqcnt); + rq->nr_running_integral = do_nr_running_integral(rq); + rq->nr_last_stamp = rq->clock_task; + __sub_nr_running(rq, count); + write_seqcount_end(&rq->ave_seqcnt); +} +#else +#define add_nr_running __add_nr_running +#define sub_nr_running __sub_nr_running +#endif + static inline void rq_last_tick_reset(struct rq *rq) { #ifdef CONFIG_NO_HZ_FULL @@ -1425,10 +2354,102 @@ } #endif +#ifdef CONFIG_SMP +static inline unsigned long capacity_of(int cpu) +{ + return cpu_rq(cpu)->cpu_capacity; +} + +static inline unsigned long capacity_orig_of(int cpu) +{ + return cpu_rq(cpu)->cpu_capacity_orig; +} + +extern unsigned int sysctl_sched_use_walt_cpu_util; +extern unsigned int walt_ravg_window; +extern bool walt_disabled; + +/* + * cpu_util returns the amount of capacity of a CPU that is used by CFS + * tasks. The unit of the return value must be the one of capacity so we can + * compare the utilization with the capacity of the CPU that is available for + * CFS task (ie cpu_capacity). + * + * cfs_rq.avg.util_avg is the sum of running time of runnable tasks plus the + * recent utilization of currently non-runnable tasks on a CPU. It represents + * the amount of utilization of a CPU in the range [0..capacity_orig] where + * capacity_orig is the cpu_capacity available at the highest frequency + * (arch_scale_freq_capacity()). + * The utilization of a CPU converges towards a sum equal to or less than the + * current capacity (capacity_curr <= capacity_orig) of the CPU because it is + * the running time on this CPU scaled by capacity_curr. + * + * Nevertheless, cfs_rq.avg.util_avg can be higher than capacity_curr or even + * higher than capacity_orig because of unfortunate rounding in + * cfs.avg.util_avg or just after migrating tasks and new task wakeups until + * the average stabilizes with the new running time. We need to check that the + * utilization stays within the range of [0..capacity_orig] and cap it if + * necessary. Without utilization capping, a group could be seen as overloaded + * (CPU0 utilization at 121% + CPU1 utilization at 80%) whereas CPU1 has 20% of + * available capacity. We allow utilization to overshoot capacity_curr (but not + * capacity_orig) as it useful for predicting the capacity required after task + * migrations (scheduler-driven DVFS). + */ +static inline unsigned long __cpu_util(int cpu, int delta) +{ + unsigned long util = cpu_rq(cpu)->cfs.avg.util_avg; + unsigned long capacity = capacity_orig_of(cpu); + +#ifdef CONFIG_SCHED_WALT + if (!walt_disabled && sysctl_sched_use_walt_cpu_util) + util = div64_u64(cpu_rq(cpu)->cumulative_runnable_avg, + walt_ravg_window >> SCHED_LOAD_SHIFT); +#endif + + delta += util; + if (delta < 0) + return 0; + + return (delta >= capacity) ? capacity : delta; +} + +static inline unsigned long cpu_util(int cpu) +{ + return __cpu_util(cpu, 0); +} + +static inline unsigned long cpu_util_freq(int cpu) +{ + unsigned long util = cpu_rq(cpu)->cfs.avg.util_avg; + unsigned long capacity = capacity_orig_of(cpu); + +#ifdef CONFIG_SCHED_WALT + if (!walt_disabled && sysctl_sched_use_walt_cpu_util) + util = div64_u64(cpu_rq(cpu)->prev_runnable_sum, + walt_ravg_window >> SCHED_LOAD_SHIFT); +#endif + return (util >= capacity) ? capacity : util; +} + +#endif + +#ifdef CONFIG_SCHED_HMP +/* + * HMP and EAS are orthogonal. Hopefully the compiler just elides out all code + * with the energy_aware() check, so that we don't even pay the comparison + * penalty at runtime. + */ +#define energy_aware() false +#else +static inline bool energy_aware(void) +{ + return sched_feat(ENERGY_AWARE); +} +#endif + static inline void sched_rt_avg_update(struct rq *rq, u64 rt_delta) { rq->rt_avg += rt_delta * arch_scale_freq_capacity(NULL, cpu_of(rq)); - sched_avg_update(rq); } #else static inline void sched_rt_avg_update(struct rq *rq, u64 rt_delta) { } @@ -1517,6 +2538,9 @@ raw_spin_unlock_irqrestore(&p->pi_lock, *flags); } +extern struct rq *lock_rq_of(struct task_struct *p, unsigned long *flags); +extern void unlock_rq_of(struct rq *rq, struct task_struct *p, unsigned long *flags); + #ifdef CONFIG_SMP #ifdef CONFIG_PREEMPT @@ -1589,6 +2613,7 @@ static inline void double_unlock_balance(struct rq *this_rq, struct rq *busiest) __releases(busiest->lock) { + if (this_rq != busiest) raw_spin_unlock(&busiest->lock); lock_set_subclass(&this_rq->lock.dep_map, 0, _RET_IP_); } @@ -1662,6 +2687,11 @@ __release(rq2->lock); } +/* + * task_may_not_preempt - check whether a task may not be preemptible soon + */ +extern bool task_may_not_preempt(struct task_struct *task, int cpu); + #else /* CONFIG_SMP */ /* @@ -1729,6 +2759,9 @@ NOHZ_BALANCE_KICK, }; +#define NOHZ_KICK_ANY 0 +#define NOHZ_KICK_RESTRICT 1 + #define nohz_flags(cpu) (&cpu_rq(cpu)->nohz_flags) #endif @@ -1780,3 +2813,66 @@ } #endif /* CONFIG_64BIT */ #endif /* CONFIG_IRQ_TIME_ACCOUNTING */ + +#ifdef CONFIG_CPU_FREQ +DECLARE_PER_CPU(struct update_util_data *, cpufreq_update_util_data); + +/** + * cpufreq_update_util - Take a note about CPU utilization changes. + * @rq: Runqueue to carry out the update for. + * @flags: Update reason flags. + * + * This function is called by the scheduler on the CPU whose utilization is + * being updated. + * + * It can only be called from RCU-sched read-side critical sections. + * + * The way cpufreq is currently arranged requires it to evaluate the CPU + * performance state (frequency/voltage) on a regular basis to prevent it from + * being stuck in a completely inadequate performance level for too long. + * That is not guaranteed to happen if the updates are only triggered from CFS, + * though, because they may not be coming in if RT or deadline tasks are active + * all the time (or there are RT and DL tasks only). + * + * As a workaround for that issue, this function is called by the RT and DL + * sched classes to trigger extra cpufreq updates to prevent it from stalling, + * but that really is a band-aid. Going forward it should be replaced with + * solutions targeted more specifically at RT and DL tasks. + */ +static inline void cpufreq_update_util(struct rq *rq, unsigned int flags) +{ + struct update_util_data *data; + + data = rcu_dereference_sched(*this_cpu_ptr(&cpufreq_update_util_data)); + if (data) + data->func(data, rq_clock(rq), flags); +} + +static inline void cpufreq_update_this_cpu(struct rq *rq, unsigned int flags) +{ + if (cpu_of(rq) == smp_processor_id()) + cpufreq_update_util(rq, flags); +} +#else +static inline void cpufreq_update_util(struct rq *rq, unsigned int flags) {} +static inline void cpufreq_update_this_cpu(struct rq *rq, unsigned int flags) {} +#endif /* CONFIG_CPU_FREQ */ + +#ifdef CONFIG_SCHED_WALT + +static inline bool +walt_task_in_cum_window_demand(struct rq *rq, struct task_struct *p) +{ + return cpu_of(rq) == task_cpu(p) && + (p->on_rq || p->last_sleep_ts >= rq->window_start); +} + +#endif /* CONFIG_SCHED_WALT */ + +#ifdef arch_scale_freq_capacity +#ifndef arch_scale_freq_invariant +#define arch_scale_freq_invariant() (true) +#endif +#else /* arch_scale_freq_capacity */ +#define arch_scale_freq_invariant() (false) +#endif diff -ruw linux-4.4.115/kernel/sched/stats.c linux-4.4.115-fbx/kernel/sched/stats.c --- linux-4.4.115/kernel/sched/stats.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/kernel/sched/stats.c 2019-01-22 16:16:28.703293496 +0100 @@ -12,6 +12,28 @@ */ #define SCHEDSTAT_VERSION 15 +#ifdef CONFIG_SMP +static inline void show_easstat(struct seq_file *seq, struct eas_stats *stats) +{ + /* eas-specific runqueue stats */ + seq_printf(seq, "eas %llu %llu %llu %llu %llu %llu ", + stats->sis_attempts, stats->sis_idle, stats->sis_cache_affine, + stats->sis_suff_cap, stats->sis_idle_cpu, stats->sis_count); + + seq_printf(seq, "%llu %llu %llu %llu %llu %llu %llu ", + stats->secb_attempts, stats->secb_sync, stats->secb_idle_bt, + stats->secb_insuff_cap, stats->secb_no_nrg_sav, + stats->secb_nrg_sav, stats->secb_count); + + seq_printf(seq, "%llu %llu %llu %llu %llu ", + stats->fbt_attempts, stats->fbt_no_cpu, stats->fbt_no_sd, + stats->fbt_pref_idle, stats->fbt_count); + + seq_printf(seq, "%llu %llu\n", + stats->cas_attempts, stats->cas_count); +} +#endif + static int show_schedstat(struct seq_file *seq, void *v) { int cpu; @@ -40,6 +62,8 @@ seq_printf(seq, "\n"); #ifdef CONFIG_SMP + show_easstat(seq, &rq->eas_stats); + /* domain-specific stats */ rcu_read_lock(); for_each_domain(cpu, sd) { @@ -66,6 +90,8 @@ sd->sbf_count, sd->sbf_balanced, sd->sbf_pushed, sd->ttwu_wake_remote, sd->ttwu_move_affine, sd->ttwu_move_balance); + + show_easstat(seq, &sd->eas_stats); } rcu_read_unlock(); #endif diff -ruw linux-4.4.115/kernel/sched/stop_task.c linux-4.4.115-fbx/kernel/sched/stop_task.c --- linux-4.4.115/kernel/sched/stop_task.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/kernel/sched/stop_task.c 2019-01-22 16:16:28.707293532 +0100 @@ -11,12 +11,48 @@ #ifdef CONFIG_SMP static int -select_task_rq_stop(struct task_struct *p, int cpu, int sd_flag, int flags) +select_task_rq_stop(struct task_struct *p, int cpu, int sd_flag, int flags, + int sibling_count_hint) { return task_cpu(p); /* stop tasks as never migrate */ } #endif /* CONFIG_SMP */ +#ifdef CONFIG_SCHED_HMP + +static void +inc_hmp_sched_stats_stop(struct rq *rq, struct task_struct *p) +{ + inc_cumulative_runnable_avg(&rq->hmp_stats, p); +} + +static void +dec_hmp_sched_stats_stop(struct rq *rq, struct task_struct *p) +{ + dec_cumulative_runnable_avg(&rq->hmp_stats, p); +} + +static void +fixup_hmp_sched_stats_stop(struct rq *rq, struct task_struct *p, + u32 new_task_load, u32 new_pred_demand) +{ + s64 task_load_delta = (s64)new_task_load - task_load(p); + s64 pred_demand_delta = PRED_DEMAND_DELTA; + + fixup_cumulative_runnable_avg(&rq->hmp_stats, p, task_load_delta, + pred_demand_delta); +} + +#else /* CONFIG_SCHED_HMP */ + +static inline void +inc_hmp_sched_stats_stop(struct rq *rq, struct task_struct *p) { } + +static inline void +dec_hmp_sched_stats_stop(struct rq *rq, struct task_struct *p) { } + +#endif /* CONFIG_SCHED_HMP */ + static void check_preempt_curr_stop(struct rq *rq, struct task_struct *p, int flags) { @@ -42,12 +78,14 @@ enqueue_task_stop(struct rq *rq, struct task_struct *p, int flags) { add_nr_running(rq, 1); + inc_hmp_sched_stats_stop(rq, p); } static void dequeue_task_stop(struct rq *rq, struct task_struct *p, int flags) { sub_nr_running(rq, 1); + dec_hmp_sched_stats_stop(rq, p); } static void yield_task_stop(struct rq *rq) @@ -134,4 +172,9 @@ .prio_changed = prio_changed_stop, .switched_to = switched_to_stop, .update_curr = update_curr_stop, +#ifdef CONFIG_SCHED_HMP + .inc_hmp_sched_stats = inc_hmp_sched_stats_stop, + .dec_hmp_sched_stats = dec_hmp_sched_stats_stop, + .fixup_hmp_sched_stats = fixup_hmp_sched_stats_stop, +#endif }; diff -ruw linux-4.4.115/kernel/smpboot.c linux-4.4.115-fbx/kernel/smpboot.c --- linux-4.4.115/kernel/smpboot.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/kernel/smpboot.c 2019-10-29 09:26:25.633222652 +0100 @@ -13,6 +13,7 @@ #include #include #include +#include #include "smpboot.h" @@ -31,7 +32,7 @@ if (!tsk) return ERR_PTR(-ENOMEM); - init_idle(tsk, cpu); + init_idle(tsk, cpu, true); return tsk; } @@ -177,6 +178,8 @@ td = kzalloc_node(sizeof(*td), GFP_KERNEL, cpu_to_node(cpu)); if (!td) return -ENOMEM; + + kmemleak_not_leak(td); td->cpu = cpu; td->ht = ht; diff -ruw linux-4.4.115/kernel/smp.c linux-4.4.115-fbx/kernel/smp.c --- linux-4.4.115/kernel/smp.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/kernel/smp.c 2019-01-22 16:16:28.711293568 +0100 @@ -32,6 +32,9 @@ static DEFINE_PER_CPU_SHARED_ALIGNED(struct llist_head, call_single_queue); static void flush_smp_call_function_queue(bool warn_cpu_offline); +/* CPU mask indicating which CPUs to bring online during smp_init() */ +static bool have_boot_cpu_mask; +static cpumask_var_t boot_cpu_mask; static int hotplug_cfd(struct notifier_block *nfb, unsigned long action, void *hcpu) @@ -548,6 +551,19 @@ early_param("maxcpus", maxcpus); +static int __init boot_cpus(char *str) +{ + alloc_bootmem_cpumask_var(&boot_cpu_mask); + if (cpulist_parse(str, boot_cpu_mask) < 0) { + pr_warn("SMP: Incorrect boot_cpus cpumask\n"); + return -EINVAL; + } + have_boot_cpu_mask = true; + return 0; +} + +early_param("boot_cpus", boot_cpus); + /* Setup number of possible processor ids */ int nr_cpu_ids __read_mostly = NR_CPUS; EXPORT_SYMBOL(nr_cpu_ids); @@ -563,6 +579,21 @@ printk(KERN_INFO "Brought up %d CPUs\n", num_online_cpus()); } +/* Should the given CPU be booted during smp_init() ? */ +static inline bool boot_cpu(int cpu) +{ + if (!have_boot_cpu_mask) + return true; + + return cpumask_test_cpu(cpu, boot_cpu_mask); +} + +static inline void free_boot_cpu_mask(void) +{ + if (have_boot_cpu_mask) /* Allocated from boot_cpus() */ + free_bootmem_cpumask_var(boot_cpu_mask); +} + /* Called by boot processor to activate the rest. */ void __init smp_init(void) { @@ -574,10 +605,12 @@ for_each_present_cpu(cpu) { if (num_online_cpus() >= setup_max_cpus) break; - if (!cpu_online(cpu)) + if (!cpu_online(cpu) && boot_cpu(cpu)) cpu_up(cpu); } + free_boot_cpu_mask(); + /* Any cleanup work */ smp_announce(); smp_cpus_done(setup_max_cpus); @@ -733,7 +766,7 @@ for_each_online_cpu(cpu) { if (cpu == smp_processor_id()) continue; - + if (!cpu_isolated(cpu)) wake_up_if_idle(cpu); } preempt_enable(); diff -ruw linux-4.4.115/kernel/softirq.c linux-4.4.115-fbx/kernel/softirq.c --- linux-4.4.115/kernel/softirq.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/kernel/softirq.c 2019-10-29 09:26:25.633222652 +0100 @@ -57,6 +57,13 @@ DEFINE_PER_CPU(struct task_struct *, ksoftirqd); +/* + * active_softirqs -- per cpu, a mask of softirqs that are being handled, + * with the expectation that approximate answers are acceptable and therefore + * no synchronization. + */ +DEFINE_PER_CPU(__u32, active_softirqs); + const char * const softirq_to_name[NR_SOFTIRQS] = { "HI", "TIMER", "NET_TX", "NET_RX", "BLOCK", "BLOCK_IOPOLL", "TASKLET", "SCHED", "HRTIMER", "RCU" @@ -227,7 +234,9 @@ static inline void lockdep_softirq_end(bool in_hardirq) { } #endif -asmlinkage __visible void __do_softirq(void) +#define long_softirq_pending() (local_softirq_pending() & LONG_SOFTIRQ_MASK) +#define defer_for_rt() (long_softirq_pending() && cpupri_check_rt()) +asmlinkage __visible void __softirq_entry __do_softirq(void) { unsigned long end = jiffies + MAX_SOFTIRQ_TIME; unsigned long old_flags = current->flags; @@ -253,6 +262,7 @@ restart: /* Reset the pending bitmask before enabling irqs */ set_softirq_pending(0); + __this_cpu_write(active_softirqs, pending); local_irq_enable(); @@ -282,12 +292,14 @@ pending >>= softirq_bit; } + __this_cpu_write(active_softirqs, 0); rcu_bh_qs(); local_irq_disable(); pending = local_softirq_pending(); if (pending) { if (time_before(jiffies, end) && !need_resched() && + !defer_for_rt() && --max_restart) goto restart; @@ -340,7 +352,7 @@ static inline void invoke_softirq(void) { - if (!force_irqthreads) { + if (!force_irqthreads && !defer_for_rt()) { #ifdef CONFIG_HAVE_IRQ_EXIT_ON_IRQ_STACK /* * We can safely execute softirq on the current stack if diff -ruw linux-4.4.115/kernel/sys.c linux-4.4.115-fbx/kernel/sys.c --- linux-4.4.115/kernel/sys.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/kernel/sys.c 2019-10-29 09:26:25.633222652 +0100 @@ -10,6 +10,7 @@ #include #include #include +#include #include #include #include @@ -41,6 +42,8 @@ #include #include #include +#include +#include #include #include @@ -2072,10 +2075,158 @@ } #endif +#ifdef CONFIG_MMU +static int prctl_update_vma_anon_name(struct vm_area_struct *vma, + struct vm_area_struct **prev, + unsigned long start, unsigned long end, + const char __user *name_addr) +{ + struct mm_struct *mm = vma->vm_mm; + int error = 0; + pgoff_t pgoff; + + if (name_addr == vma_get_anon_name(vma)) { + *prev = vma; + goto out; + } + + pgoff = vma->vm_pgoff + ((start - vma->vm_start) >> PAGE_SHIFT); + *prev = vma_merge(mm, *prev, start, end, vma->vm_flags, vma->anon_vma, + vma->vm_file, pgoff, vma_policy(vma), + vma->vm_userfaultfd_ctx, name_addr); + if (*prev) { + vma = *prev; + goto success; + } + + *prev = vma; + + if (start != vma->vm_start) { + error = split_vma(mm, vma, start, 1); + if (error) + goto out; + } + + if (end != vma->vm_end) { + error = split_vma(mm, vma, end, 0); + if (error) + goto out; + } + +success: + if (!vma->vm_file) + vma->anon_name = name_addr; + +out: + if (error == -ENOMEM) + error = -EAGAIN; + return error; +} + +static int prctl_set_vma_anon_name(unsigned long start, unsigned long end, + unsigned long arg) +{ + unsigned long tmp; + struct vm_area_struct *vma, *prev; + int unmapped_error = 0; + int error = -EINVAL; + + /* + * If the interval [start,end) covers some unmapped address + * ranges, just ignore them, but return -ENOMEM at the end. + * - this matches the handling in madvise. + */ + vma = find_vma_prev(current->mm, start, &prev); + if (vma && start > vma->vm_start) + prev = vma; + + for (;;) { + /* Still start < end. */ + error = -ENOMEM; + if (!vma) + return error; + + /* Here start < (end|vma->vm_end). */ + if (start < vma->vm_start) { + unmapped_error = -ENOMEM; + start = vma->vm_start; + if (start >= end) + return error; + } + + /* Here vma->vm_start <= start < (end|vma->vm_end) */ + tmp = vma->vm_end; + if (end < tmp) + tmp = end; + + /* Here vma->vm_start <= start < tmp <= (end|vma->vm_end). */ + error = prctl_update_vma_anon_name(vma, &prev, start, tmp, + (const char __user *)arg); + if (error) + return error; + start = tmp; + if (prev && start < prev->vm_end) + start = prev->vm_end; + error = unmapped_error; + if (start >= end) + return error; + if (prev) + vma = prev->vm_next; + else /* madvise_remove dropped mmap_sem */ + vma = find_vma(current->mm, start); + } +} + +static int prctl_set_vma(unsigned long opt, unsigned long start, + unsigned long len_in, unsigned long arg) +{ + struct mm_struct *mm = current->mm; + int error; + unsigned long len; + unsigned long end; + + if (start & ~PAGE_MASK) + return -EINVAL; + len = (len_in + ~PAGE_MASK) & PAGE_MASK; + + /* Check to see whether len was rounded up from small -ve to zero */ + if (len_in && !len) + return -EINVAL; + + end = start + len; + if (end < start) + return -EINVAL; + + if (end == start) + return 0; + + down_write(&mm->mmap_sem); + + switch (opt) { + case PR_SET_VMA_ANON_NAME: + error = prctl_set_vma_anon_name(start, end, arg); + break; + default: + error = -EINVAL; + } + + up_write(&mm->mmap_sem); + + return error; +} +#else /* CONFIG_MMU */ +static int prctl_set_vma(unsigned long opt, unsigned long start, + unsigned long len_in, unsigned long arg) +{ + return -EINVAL; +} +#endif + SYSCALL_DEFINE5(prctl, int, option, unsigned long, arg2, unsigned long, arg3, unsigned long, arg4, unsigned long, arg5) { struct task_struct *me = current; + struct task_struct *tsk; unsigned char comm[sizeof(me->comm)]; long error; @@ -2169,6 +2320,9 @@ error = perf_event_task_enable(); break; case PR_GET_TIMERSLACK: + if (current->timer_slack_ns > ULONG_MAX) + error = ULONG_MAX; + else error = current->timer_slack_ns; break; case PR_SET_TIMERSLACK: @@ -2218,6 +2372,26 @@ case PR_GET_TID_ADDRESS: error = prctl_get_tid_address(me, (int __user **)arg2); break; + case PR_SET_TIMERSLACK_PID: + if (task_pid_vnr(current) != (pid_t)arg3 && + !capable(CAP_SYS_NICE)) + return -EPERM; + rcu_read_lock(); + tsk = find_task_by_vpid((pid_t)arg3); + if (tsk == NULL) { + rcu_read_unlock(); + return -EINVAL; + } + get_task_struct(tsk); + rcu_read_unlock(); + if (arg2 <= 0) + tsk->timer_slack_ns = + tsk->default_timer_slack_ns; + else + tsk->timer_slack_ns = arg2; + put_task_struct(tsk); + error = 0; + break; case PR_SET_CHILD_SUBREAPER: me->signal->is_child_subreaper = !!arg2; break; @@ -2266,6 +2440,21 @@ case PR_GET_FP_MODE: error = GET_FP_MODE(me); break; + case PR_SET_VMA: + error = prctl_set_vma(arg2, arg3, arg4, arg5); + break; + case PR_SET_EXEC_MODE: + if (arg2 != EXEC_MODE_UNLIMITED && + arg2 != EXEC_MODE_ONCE && + arg2 != EXEC_MODE_DENIED) + return -EINVAL; + + if (arg2 > current->exec_mode) + return -EPERM; + current->exec_mode = arg2; + return 0; + case PR_GET_EXEC_MODE: + return current->exec_mode; default: error = -EINVAL; break; diff -ruw linux-4.4.115/kernel/sysctl_binary.c linux-4.4.115-fbx/kernel/sysctl_binary.c --- linux-4.4.115/kernel/sysctl_binary.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/kernel/sysctl_binary.c 2019-01-22 16:16:28.715293604 +0100 @@ -138,6 +138,8 @@ { CTL_INT, KERN_MAX_LOCK_DEPTH, "max_lock_depth" }, { CTL_INT, KERN_PANIC_ON_NMI, "panic_on_unrecovered_nmi" }, { CTL_INT, KERN_PANIC_ON_WARN, "panic_on_warn" }, + { CTL_INT, KERN_BOOT_REASON, "boot_reason" }, + { CTL_INT, KERN_COLD_BOOT, "cold_boot" }, {} }; @@ -253,6 +255,7 @@ { CTL_INT, NET_IPV4_CONF_NOPOLICY, "disable_policy" }, { CTL_INT, NET_IPV4_CONF_FORCE_IGMP_VERSION, "force_igmp_version" }, { CTL_INT, NET_IPV4_CONF_PROMOTE_SECONDARIES, "promote_secondaries" }, + { CTL_INT, NET_IPV4_CONF_NF_IPV4_DEFRAG_SKIP, "nf_ipv4_defrag_skip" }, {} }; @@ -523,6 +526,7 @@ { CTL_INT, NET_IPV6_PROXY_NDP, "proxy_ndp" }, { CTL_INT, NET_IPV6_ACCEPT_SOURCE_ROUTE, "accept_source_route" }, { CTL_INT, NET_IPV6_ACCEPT_RA_FROM_LOCAL, "accept_ra_from_local" }, + { CTL_INT, NET_IPV6_ACCEPT_RA_PREFIX_ROUTE, "accept_ra_prefix_route" }, {} }; diff -ruw linux-4.4.115/kernel/sysctl.c linux-4.4.115-fbx/kernel/sysctl.c --- linux-4.4.115/kernel/sysctl.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/kernel/sysctl.c 2019-10-29 09:26:25.633222652 +0100 @@ -105,6 +105,7 @@ extern unsigned int core_pipe_limit; #endif extern int pid_max; +extern int extra_free_kbytes; extern int pid_max_min, pid_max_max; extern int percpu_pagelist_fraction; extern int compat_log; @@ -124,12 +125,17 @@ static int zero; static int __maybe_unused one = 1; static int __maybe_unused two = 2; +static int __maybe_unused three = 3; static int __maybe_unused four = 4; static unsigned long one_ul = 1; static int one_hundred = 100; #ifdef CONFIG_PRINTK static int ten_thousand = 10000; #endif +#ifdef CONFIG_SCHED_HMP +static int one_thousand = 1000; +static int max_freq_reporting_policy = FREQ_REPORT_INVALID_POLICY - 1; +#endif /* this is needed for the proc_doulongvec_minmax of vm_dirty_bytes */ static unsigned long dirty_bytes_min = 2 * PAGE_SIZE; @@ -285,6 +291,217 @@ .mode = 0644, .proc_handler = proc_dointvec, }, +#ifdef CONFIG_SCHED_HMP + { + .procname = "sched_freq_reporting_policy", + .data = &sysctl_sched_freq_reporting_policy, + .maxlen = sizeof(unsigned int), + .mode = 0644, + .proc_handler = proc_dointvec_minmax, + .extra1 = &zero, + .extra2 = &max_freq_reporting_policy, + }, + { + .procname = "sched_freq_inc_notify", + .data = &sysctl_sched_freq_inc_notify, + .maxlen = sizeof(unsigned int), + .mode = 0644, + .proc_handler = proc_dointvec_minmax, + .extra1 = &zero, + }, + { + .procname = "sched_freq_dec_notify", + .data = &sysctl_sched_freq_dec_notify, + .maxlen = sizeof(unsigned int), + .mode = 0644, + .proc_handler = proc_dointvec_minmax, + .extra1 = &zero, + }, + { + .procname = "sched_cpu_high_irqload", + .data = &sysctl_sched_cpu_high_irqload, + .maxlen = sizeof(unsigned int), + .mode = 0644, + .proc_handler = proc_dointvec, + }, + { + .procname = "sched_ravg_hist_size", + .data = &sysctl_sched_ravg_hist_size, + .maxlen = sizeof(unsigned int), + .mode = 0644, + .proc_handler = sched_window_update_handler, + }, + { + .procname = "sched_window_stats_policy", + .data = &sysctl_sched_window_stats_policy, + .maxlen = sizeof(unsigned int), + .mode = 0644, + .proc_handler = sched_window_update_handler, + }, + { + .procname = "sched_spill_load", + .data = &sysctl_sched_spill_load_pct, + .maxlen = sizeof(unsigned int), + .mode = 0644, + .proc_handler = sched_hmp_proc_update_handler, + .extra1 = &zero, + .extra2 = &one_hundred, + }, + { + .procname = "sched_spill_nr_run", + .data = &sysctl_sched_spill_nr_run, + .maxlen = sizeof(unsigned int), + .mode = 0644, + .proc_handler = proc_dointvec_minmax, + .extra1 = &zero, + }, + { + .procname = "sched_upmigrate", + .data = &sysctl_sched_upmigrate_pct, + .maxlen = sizeof(unsigned int), + .mode = 0644, + .proc_handler = sched_hmp_proc_update_handler, + .extra1 = &zero, + .extra2 = &one_hundred, + }, + { + .procname = "sched_downmigrate", + .data = &sysctl_sched_downmigrate_pct, + .maxlen = sizeof(unsigned int), + .mode = 0644, + .proc_handler = sched_hmp_proc_update_handler, + .extra1 = &zero, + .extra2 = &one_hundred, + }, + { + .procname = "sched_group_upmigrate", + .data = &sysctl_sched_group_upmigrate_pct, + .maxlen = sizeof(unsigned int), + .mode = 0644, + .proc_handler = sched_hmp_proc_update_handler, + .extra1 = &zero, + }, + { + .procname = "sched_group_downmigrate", + .data = &sysctl_sched_group_downmigrate_pct, + .maxlen = sizeof(unsigned int), + .mode = 0644, + .proc_handler = sched_hmp_proc_update_handler, + .extra1 = &zero, + }, + { + .procname = "sched_init_task_load", + .data = &sysctl_sched_init_task_load_pct, + .maxlen = sizeof(unsigned int), + .mode = 0644, + .proc_handler = sched_hmp_proc_update_handler, + .extra1 = &zero, + .extra2 = &one_hundred, + }, + { + .procname = "sched_select_prev_cpu_us", + .data = &sysctl_sched_select_prev_cpu_us, + .maxlen = sizeof(unsigned int), + .mode = 0644, + .proc_handler = sched_hmp_proc_update_handler, + .extra1 = &zero, + }, + { + .procname = "sched_restrict_cluster_spill", + .data = &sysctl_sched_restrict_cluster_spill, + .maxlen = sizeof(unsigned int), + .mode = 0644, + .proc_handler = proc_dointvec_minmax, + .extra1 = &zero, + .extra2 = &one, + }, + { + .procname = "sched_small_wakee_task_load", + .data = &sysctl_sched_small_wakee_task_load_pct, + .maxlen = sizeof(unsigned int), + .mode = 0644, + .proc_handler = sched_hmp_proc_update_handler, + .extra1 = &zero, + .extra2 = &one_hundred, + }, + { + .procname = "sched_big_waker_task_load", + .data = &sysctl_sched_big_waker_task_load_pct, + .maxlen = sizeof(unsigned int), + .mode = 0644, + .proc_handler = sched_hmp_proc_update_handler, + .extra1 = &zero, + .extra2 = &one_hundred, + }, + { + .procname = "sched_prefer_sync_wakee_to_waker", + .data = &sysctl_sched_prefer_sync_wakee_to_waker, + .maxlen = sizeof(unsigned int), + .mode = 0644, + .proc_handler = proc_dointvec_minmax, + .extra1 = &zero, + .extra2 = &one, + }, + { + .procname = "sched_enable_thread_grouping", + .data = &sysctl_sched_enable_thread_grouping, + .maxlen = sizeof(unsigned int), + .mode = 0644, + .proc_handler = proc_dointvec, + }, + { + .procname = "sched_pred_alert_freq", + .data = &sysctl_sched_pred_alert_freq, + .maxlen = sizeof(unsigned int), + .mode = 0644, + .proc_handler = proc_dointvec_minmax, + .extra1 = &zero, + }, + { + .procname = "sched_freq_aggregate", + .data = &sysctl_sched_freq_aggregate, + .maxlen = sizeof(unsigned int), + .mode = 0644, + .proc_handler = sched_window_update_handler, + }, + { + .procname = "sched_freq_aggregate_threshold", + .data = &sysctl_sched_freq_aggregate_threshold_pct, + .maxlen = sizeof(unsigned int), + .mode = 0644, + .proc_handler = sched_hmp_proc_update_handler, + .extra1 = &zero, + /* + * Special handling for sched_freq_aggregate_threshold_pct + * which can be greater than 100. Use 1000 as an upper bound + * value which works for all practical use cases. + */ + .extra2 = &one_thousand, + }, + { + .procname = "sched_boost", + .data = &sysctl_sched_boost, + .maxlen = sizeof(unsigned int), + .mode = 0644, + .proc_handler = sched_boost_handler, + .extra1 = &zero, + .extra2 = &three, + }, + { + .procname = "sched_short_burst_ns", + .data = &sysctl_sched_short_burst, + .maxlen = sizeof(unsigned int), + .mode = 0644, + .proc_handler = proc_dointvec, + }, + { + .procname = "sched_short_sleep_ns", + .data = &sysctl_sched_short_sleep, + .maxlen = sizeof(unsigned int), + .mode = 0644, + .proc_handler = proc_dointvec, + }, +#endif /* CONFIG_SCHED_HMP */ #ifdef CONFIG_SCHED_DEBUG { .procname = "sched_min_granularity_ns", @@ -305,6 +522,20 @@ .extra2 = &max_sched_granularity_ns, }, { + .procname = "sched_sync_hint_enable", + .data = &sysctl_sched_sync_hint_enable, + .maxlen = sizeof(unsigned int), + .mode = 0644, + .proc_handler = proc_dointvec, + }, + { + .procname = "sched_cstate_aware", + .data = &sysctl_sched_cstate_aware, + .maxlen = sizeof(unsigned int), + .mode = 0644, + .proc_handler = proc_dointvec, + }, + { .procname = "sched_wakeup_granularity_ns", .data = &sysctl_sched_wakeup_granularity, .maxlen = sizeof(unsigned int), @@ -342,7 +573,8 @@ .data = &sysctl_sched_time_avg, .maxlen = sizeof(unsigned int), .mode = 0644, - .proc_handler = proc_dointvec, + .proc_handler = proc_dointvec_minmax, + .extra1 = &one, }, { .procname = "sched_shares_window_ns", @@ -435,6 +667,21 @@ .extra1 = &one, }, #endif +#ifdef CONFIG_SCHED_TUNE + { + .procname = "sched_cfs_boost", + .data = &sysctl_sched_cfs_boost, + .maxlen = sizeof(sysctl_sched_cfs_boost), +#ifdef CONFIG_CGROUP_SCHEDTUNE + .mode = 0444, +#else + .mode = 0644, +#endif + .proc_handler = &sysctl_sched_cfs_boost_handler, + .extra1 = &zero, + .extra2 = &one_hundred, + }, +#endif #ifdef CONFIG_PROVE_LOCKING { .procname = "prove_locking", @@ -1175,6 +1422,27 @@ .extra2 = &one, }, #endif +#if defined(CONFIG_ARM) || defined(CONFIG_ARM64) + { + .procname = "boot_reason", + .data = &boot_reason, + .maxlen = sizeof(int), + .mode = 0444, + .proc_handler = proc_dointvec, + }, + + { + .procname = "cold_boot", + .data = &cold_boot, + .maxlen = sizeof(int), + .mode = 0444, + .proc_handler = proc_dointvec, + }, +#endif +/* + * NOTE: do not add new entries to this table unless you have read + * Documentation/sysctl/ctl_unnumbered.txt + */ { } }; @@ -1396,6 +1664,14 @@ .extra1 = &zero, }, { + .procname = "extra_free_kbytes", + .data = &extra_free_kbytes, + .maxlen = sizeof(extra_free_kbytes), + .mode = 0644, + .proc_handler = min_free_kbytes_sysctl_handler, + .extra1 = &zero, + }, + { .procname = "percpu_pagelist_fraction", .data = &percpu_pagelist_fraction, .maxlen = sizeof(percpu_pagelist_fraction), @@ -1571,6 +1847,44 @@ .mode = 0644, .proc_handler = proc_doulongvec_minmax, }, +#ifdef CONFIG_HAVE_ARCH_MMAP_RND_BITS + { + .procname = "mmap_rnd_bits", + .data = &mmap_rnd_bits, + .maxlen = sizeof(mmap_rnd_bits), + .mode = 0600, + .proc_handler = proc_dointvec_minmax, + .extra1 = (void *)&mmap_rnd_bits_min, + .extra2 = (void *)&mmap_rnd_bits_max, + }, +#endif +#ifdef CONFIG_HAVE_ARCH_MMAP_RND_COMPAT_BITS + { + .procname = "mmap_rnd_compat_bits", + .data = &mmap_rnd_compat_bits, + .maxlen = sizeof(mmap_rnd_compat_bits), + .mode = 0600, + .proc_handler = proc_dointvec_minmax, + .extra1 = (void *)&mmap_rnd_compat_bits_min, + .extra2 = (void *)&mmap_rnd_compat_bits_max, + }, +#endif +#ifdef CONFIG_SWAP + { + .procname = "swap_ratio", + .data = &sysctl_swap_ratio, + .maxlen = sizeof(sysctl_swap_ratio), + .mode = 0644, + .proc_handler = proc_dointvec_minmax, + }, + { + .procname = "swap_ratio_enable", + .data = &sysctl_swap_ratio_enable, + .maxlen = sizeof(sysctl_swap_ratio_enable), + .mode = 0644, + .proc_handler = proc_dointvec_minmax, + }, +#endif { } }; @@ -2040,15 +2354,7 @@ int write, void *data) { if (write) { - if (*negp) { - if (*lvalp > (unsigned long) INT_MAX + 1) - return -EINVAL; - *valp = -*lvalp; - } else { - if (*lvalp > (unsigned long) INT_MAX) - return -EINVAL; - *valp = *lvalp; - } + *valp = *negp ? -*lvalp : *lvalp; } else { int val = *valp; if (val < 0) { diff -ruw linux-4.4.115/kernel/taskstats.c linux-4.4.115-fbx/kernel/taskstats.c --- linux-4.4.115/kernel/taskstats.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/kernel/taskstats.c 2019-01-22 16:16:28.715293604 +0100 @@ -54,7 +54,11 @@ [TASKSTATS_CMD_ATTR_REGISTER_CPUMASK] = { .type = NLA_STRING }, [TASKSTATS_CMD_ATTR_DEREGISTER_CPUMASK] = { .type = NLA_STRING },}; -static const struct nla_policy cgroupstats_cmd_get_policy[CGROUPSTATS_CMD_ATTR_MAX+1] = { +/* + * We have to use TASKSTATS_CMD_ATTR_MAX here, it is the maxattr in the family. + * Make sure they are always aligned. + */ +static const struct nla_policy cgroupstats_cmd_get_policy[TASKSTATS_CMD_ATTR_MAX+1] = { [CGROUPSTATS_CMD_ATTR_FD] = { .type = NLA_U32 }, }; diff -ruw linux-4.4.115/kernel/time/alarmtimer.c linux-4.4.115-fbx/kernel/time/alarmtimer.c --- linux-4.4.115/kernel/time/alarmtimer.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/kernel/time/alarmtimer.c 2019-10-29 09:26:25.637222692 +0100 @@ -26,6 +26,11 @@ #include #include +#ifdef CONFIG_MSM_PM +#include "lpm-levels.h" +#endif +#include + /** * struct alarm_base - Alarm timer bases * @lock: Lock for syncrhonized access to the base @@ -46,14 +51,130 @@ static DEFINE_SPINLOCK(freezer_delta_lock); static struct wakeup_source *ws; +static struct delayed_work work; +static struct workqueue_struct *power_off_alarm_workqueue; #ifdef CONFIG_RTC_CLASS /* rtc timer and device for setting alarm wakeups at suspend */ static struct rtc_timer rtctimer; static struct rtc_device *rtcdev; static DEFINE_SPINLOCK(rtcdev_lock); +static struct mutex power_on_alarm_lock; +static struct alarm init_alarm; + +/** + * power_on_alarm_init - Init power on alarm value + * + * Read rtc alarm value after device booting up and add this alarm + * into alarm queue. + */ +void power_on_alarm_init(void) +{ + struct rtc_wkalrm rtc_alarm; + struct rtc_time rt; + unsigned long alarm_time; + struct rtc_device *rtc; + ktime_t alarm_ktime; + + rtc = alarmtimer_get_rtcdev(); + + if (!rtc) + return; + + rtc_read_alarm(rtc, &rtc_alarm); + rt = rtc_alarm.time; + + rtc_tm_to_time(&rt, &alarm_time); + + if (alarm_time) { + alarm_ktime = ktime_set(alarm_time, 0); + alarm_init(&init_alarm, ALARM_POWEROFF_REALTIME, NULL); + alarm_start(&init_alarm, alarm_ktime); + } +} /** + * set_power_on_alarm - set power on alarm value into rtc register + * + * Get the soonest power off alarm timer and set the alarm value into rtc + * register. + */ +void set_power_on_alarm(void) +{ + int rc; + struct timespec wall_time, alarm_ts; + long alarm_secs = 0l; + long rtc_secs, alarm_time, alarm_delta; + struct rtc_time rtc_time; + struct rtc_wkalrm alarm; + struct rtc_device *rtc; + struct timerqueue_node *next; + unsigned long flags; + struct alarm_base *base = &alarm_bases[ALARM_POWEROFF_REALTIME]; + + rc = mutex_lock_interruptible(&power_on_alarm_lock); + if (rc != 0) + return; + + spin_lock_irqsave(&base->lock, flags); + next = timerqueue_getnext(&base->timerqueue); + spin_unlock_irqrestore(&base->lock, flags); + + if (next) { + alarm_ts = ktime_to_timespec(next->expires); + alarm_secs = alarm_ts.tv_sec; + } + + if (!alarm_secs) + goto disable_alarm; + + getnstimeofday(&wall_time); + + /* + * alarm_secs have to be bigger than "wall_time +1". + * It is to make sure that alarm time will be always + * bigger than wall time. + */ + if (alarm_secs <= wall_time.tv_sec + 1) + goto disable_alarm; + + rtc = alarmtimer_get_rtcdev(); + if (!rtc) + goto exit; + + rtc_read_time(rtc, &rtc_time); + rtc_tm_to_time(&rtc_time, &rtc_secs); + alarm_delta = wall_time.tv_sec - rtc_secs; + alarm_time = alarm_secs - alarm_delta; + + rtc_time_to_tm(alarm_time, &alarm.time); + alarm.enabled = 1; + rc = rtc_set_alarm(rtcdev, &alarm); + if (rc) + goto disable_alarm; + + mutex_unlock(&power_on_alarm_lock); + return; + +disable_alarm: + rtc_alarm_irq_enable(rtcdev, 0); +exit: + mutex_unlock(&power_on_alarm_lock); +} + +static void alarmtimer_triggered_func(void *p) +{ + struct rtc_device *rtc = rtcdev; + + if (!(rtc->irq_data & RTC_AF)) + return; + __pm_wakeup_event(ws, 2 * MSEC_PER_SEC); +} + +static struct rtc_task alarmtimer_rtc_task = { + .func = alarmtimer_triggered_func +}; +/** * alarmtimer_get_rtcdev - Return selected rtcdevice * * This function returns the rtc device to use for wakealarms. @@ -63,7 +184,7 @@ struct rtc_device *alarmtimer_get_rtcdev(void) { unsigned long flags; - struct rtc_device *ret; + struct rtc_device *ret = NULL; spin_lock_irqsave(&rtcdev_lock, flags); ret = rtcdev; @@ -77,33 +198,48 @@ struct class_interface *class_intf) { unsigned long flags; + int err = 0; struct rtc_device *rtc = to_rtc_device(dev); - if (rtcdev) return -EBUSY; - if (!rtc->ops->set_alarm) return -1; - if (!device_may_wakeup(rtc->dev.parent)) - return -1; spin_lock_irqsave(&rtcdev_lock, flags); if (!rtcdev) { + err = rtc_irq_register(rtc, &alarmtimer_rtc_task); + if (err) + goto rtc_irq_reg_err; rtcdev = rtc; /* hold a reference so it doesn't go away */ get_device(dev); } + +rtc_irq_reg_err: spin_unlock_irqrestore(&rtcdev_lock, flags); - return 0; + return err; + +} + +static void alarmtimer_rtc_remove_device(struct device *dev, + struct class_interface *class_intf) +{ + if (rtcdev && dev == &rtcdev->dev) { + rtc_irq_unregister(rtcdev, &alarmtimer_rtc_task); + rtcdev = NULL; + } } static inline void alarmtimer_rtc_timer_init(void) { + mutex_init(&power_on_alarm_lock); + rtc_timer_init(&rtctimer, NULL, NULL); } static struct class_interface alarmtimer_rtc_interface = { .add_dev = &alarmtimer_rtc_add_device, + .remove_dev = &alarmtimer_rtc_remove_device, }; static int alarmtimer_rtc_interface_setup(void) @@ -124,8 +260,14 @@ static inline int alarmtimer_rtc_interface_setup(void) { return 0; } static inline void alarmtimer_rtc_interface_remove(void) { } static inline void alarmtimer_rtc_timer_init(void) { } +void set_power_on_alarm(void) { } #endif +static void alarm_work_func(struct work_struct *unused) +{ + set_power_on_alarm(); +} + /** * alarmtimer_enqueue - Adds an alarm timer to an alarm_base timerqueue * @base: pointer to the base where the timer is being run @@ -195,6 +337,10 @@ } spin_unlock_irqrestore(&base->lock, flags); + /* set next power off alarm */ + if (alarm->type == ALARM_POWEROFF_REALTIME) + queue_delayed_work(power_off_alarm_workqueue, &work, 0); + return ret; } @@ -217,6 +363,68 @@ * set an rtc timer to fire that far into the future, which * will wake us from suspend. */ +#if defined(CONFIG_RTC_DRV_QPNP) && defined(CONFIG_MSM_PM) +static int alarmtimer_suspend(struct device *dev) +{ + struct rtc_time tm; + ktime_t min, now; + unsigned long flags; + struct rtc_device *rtc; + int i; + int ret = 0; + + spin_lock_irqsave(&freezer_delta_lock, flags); + min = freezer_delta; + freezer_delta = ktime_set(0, 0); + spin_unlock_irqrestore(&freezer_delta_lock, flags); + + rtc = alarmtimer_get_rtcdev(); + /* If we have no rtcdev, just return */ + if (!rtc) + return 0; + + /* Find the soonest timer to expire*/ + for (i = 0; i < ALARM_NUMTYPE; i++) { + struct alarm_base *base = &alarm_bases[i]; + struct timerqueue_node *next; + ktime_t delta; + + spin_lock_irqsave(&base->lock, flags); + next = timerqueue_getnext(&base->timerqueue); + spin_unlock_irqrestore(&base->lock, flags); + if (!next) + continue; + delta = ktime_sub(next->expires, base->gettime()); + if (!min.tv64 || (delta.tv64 < min.tv64)) + min = delta; + } + if (min.tv64 == 0) + return 0; + + if (ktime_to_ns(min) < 2 * NSEC_PER_SEC) { + __pm_wakeup_event(ws, 2 * MSEC_PER_SEC); + return -EBUSY; + } + + /* Setup a timer to fire that far in the future */ + rtc_timer_cancel(rtc, &rtctimer); + rtc_read_time(rtc, &tm); + now = rtc_tm_to_ktime(tm); + now = ktime_add(now, min); + if (poweron_alarm) { + uint64_t msec = 0; + + msec = ktime_to_ms(min); + lpm_suspend_wake_time(msec); + } else { + /* Set alarm, if in the past reject suspend briefly to handle */ + ret = rtc_timer_start(rtc, &rtctimer, now, ktime_set(0, 0)); + if (ret < 0) + __pm_wakeup_event(ws, MSEC_PER_SEC); + } + return ret; +} +#else static int alarmtimer_suspend(struct device *dev) { struct rtc_time tm; @@ -226,6 +434,8 @@ int i; int ret; + cancel_delayed_work_sync(&work); + spin_lock_irqsave(&freezer_delta_lock, flags); min = freezer_delta; freezer_delta = ktime_set(0, 0); @@ -271,11 +481,31 @@ __pm_wakeup_event(ws, MSEC_PER_SEC); return ret; } +#endif +static int alarmtimer_resume(struct device *dev) +{ + struct rtc_device *rtc; + + rtc = alarmtimer_get_rtcdev(); + /* If we have no rtcdev, just return */ + if (!rtc) + return 0; + rtc_timer_cancel(rtc, &rtctimer); + + queue_delayed_work(power_off_alarm_workqueue, &work, 0); + return 0; +} + #else static int alarmtimer_suspend(struct device *dev) { return 0; } + +static int alarmtimer_resume(struct device *dev) +{ + return 0; +} #endif static void alarmtimer_freezerset(ktime_t absexp, enum alarmtimer_type type) @@ -443,12 +673,14 @@ * clock2alarm - helper that converts from clockid to alarmtypes * @clockid: clockid. */ -static enum alarmtimer_type clock2alarm(clockid_t clockid) +enum alarmtimer_type clock2alarm(clockid_t clockid) { if (clockid == CLOCK_REALTIME_ALARM) return ALARM_REALTIME; if (clockid == CLOCK_BOOTTIME_ALARM) return ALARM_BOOTTIME; + if (clockid == CLOCK_POWEROFF_ALARM) + return ALARM_POWEROFF_REALTIME; return -1; } @@ -809,6 +1041,7 @@ /* Suspend hook structures */ static const struct dev_pm_ops alarmtimer_pm_ops = { .suspend = alarmtimer_suspend, + .resume = alarmtimer_resume, }; static struct platform_driver alarmtimer_driver = { @@ -843,10 +1076,13 @@ posix_timers_register_clock(CLOCK_REALTIME_ALARM, &alarm_clock); posix_timers_register_clock(CLOCK_BOOTTIME_ALARM, &alarm_clock); + posix_timers_register_clock(CLOCK_POWEROFF_ALARM, &alarm_clock); /* Initialize alarm bases */ alarm_bases[ALARM_REALTIME].base_clockid = CLOCK_REALTIME; alarm_bases[ALARM_REALTIME].gettime = &ktime_get_real; + alarm_bases[ALARM_POWEROFF_REALTIME].base_clockid = CLOCK_REALTIME; + alarm_bases[ALARM_POWEROFF_REALTIME].gettime = &ktime_get_real; alarm_bases[ALARM_BOOTTIME].base_clockid = CLOCK_BOOTTIME; alarm_bases[ALARM_BOOTTIME].gettime = &ktime_get_boottime; for (i = 0; i < ALARM_NUMTYPE; i++) { @@ -868,8 +1104,24 @@ goto out_drv; } ws = wakeup_source_register("alarmtimer"); - return 0; + if (!ws) { + error = -ENOMEM; + goto out_ws; + } + + INIT_DELAYED_WORK(&work, alarm_work_func); + power_off_alarm_workqueue = + create_singlethread_workqueue("power_off_alarm"); + if (!power_off_alarm_workqueue) { + error = -ENOMEM; + goto out_wq; + } + return 0; +out_wq: + wakeup_source_unregister(ws); +out_ws: + platform_device_unregister(pdev); out_drv: platform_driver_unregister(&alarmtimer_driver); out_if: diff -ruw linux-4.4.115/kernel/time/clocksource.c linux-4.4.115-fbx/kernel/time/clocksource.c --- linux-4.4.115/kernel/time/clocksource.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/kernel/time/clocksource.c 2019-01-22 16:16:28.715293604 +0100 @@ -108,7 +108,7 @@ #ifdef CONFIG_CLOCKSOURCE_WATCHDOG static void clocksource_watchdog_work(struct work_struct *work); -static void clocksource_select(void); +static void clocksource_select(bool force); static LIST_HEAD(watchdog_list); static struct clocksource *watchdog; @@ -415,7 +415,7 @@ { mutex_lock(&clocksource_mutex); if (__clocksource_watchdog_kthread()) - clocksource_select(); + clocksource_select(false); mutex_unlock(&clocksource_mutex); return 0; } @@ -555,11 +555,12 @@ #ifndef CONFIG_ARCH_USES_GETTIMEOFFSET -static struct clocksource *clocksource_find_best(bool oneshot, bool skipcur) +static struct clocksource *clocksource_find_best(bool oneshot, bool skipcur, + bool force) { struct clocksource *cs; - if (!finished_booting || list_empty(&clocksource_list)) + if ((!finished_booting && !force) || list_empty(&clocksource_list)) return NULL; /* @@ -577,13 +578,13 @@ return NULL; } -static void __clocksource_select(bool skipcur) +static void __clocksource_select(bool skipcur, bool force) { bool oneshot = tick_oneshot_mode_active(); struct clocksource *best, *cs; /* Find the best suitable clocksource */ - best = clocksource_find_best(oneshot, skipcur); + best = clocksource_find_best(oneshot, skipcur, force); if (!best) return; @@ -623,22 +624,40 @@ * Select the clocksource with the best rating, or the clocksource, * which is selected by userspace override. */ -static void clocksource_select(void) +static void clocksource_select(bool force) { - __clocksource_select(false); + return __clocksource_select(false, force); } static void clocksource_select_fallback(void) { - __clocksource_select(true); + __clocksource_select(true, false); } #else /* !CONFIG_ARCH_USES_GETTIMEOFFSET */ -static inline void clocksource_select(void) { } + +static inline void clocksource_select(bool force) { } static inline void clocksource_select_fallback(void) { } #endif +/** + * clocksource_select_force - Force re-selection of the best clocksource + * among registered clocksources + * + * clocksource_select() can't select the best clocksource before + * calling clocksource_done_booting() and since clocksource_select() + * should be called with clocksource_mutex held, provide a new API + * can be called from other files to select best clockrouce irrespective + * of finished_booting flag. + */ +void clocksource_select_force(void) +{ + mutex_lock(&clocksource_mutex); + clocksource_select(true); + mutex_unlock(&clocksource_mutex); +} + /* * clocksource_done_booting - Called near the end of core bootup * @@ -655,7 +674,7 @@ * Run the watchdog first to eliminate unstable clock sources */ __clocksource_watchdog_kthread(); - clocksource_select(); + clocksource_select(false); mutex_unlock(&clocksource_mutex); return 0; } @@ -744,6 +763,7 @@ } EXPORT_SYMBOL_GPL(__clocksource_update_freq_scale); + /** * __clocksource_register_scale - Used to install new clocksources * @cs: clocksource to be registered @@ -765,7 +785,7 @@ mutex_lock(&clocksource_mutex); clocksource_enqueue(cs); clocksource_enqueue_watchdog(cs); - clocksource_select(); + clocksource_select(false); clocksource_select_watchdog(false); mutex_unlock(&clocksource_mutex); return 0; @@ -788,7 +808,7 @@ { mutex_lock(&clocksource_mutex); __clocksource_change_rating(cs, rating); - clocksource_select(); + clocksource_select(false); clocksource_select_watchdog(false); mutex_unlock(&clocksource_mutex); } @@ -892,7 +912,7 @@ ret = sysfs_get_uname(buf, override_name, count); if (ret >= 0) - clocksource_select(); + clocksource_select(false); mutex_unlock(&clocksource_mutex); diff -ruw linux-4.4.115/kernel/time/hrtimer.c linux-4.4.115-fbx/kernel/time/hrtimer.c --- linux-4.4.115/kernel/time/hrtimer.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/kernel/time/hrtimer.c 2019-10-29 09:26:25.637222692 +0100 @@ -783,34 +783,6 @@ clock_was_set_delayed(); } -static inline void timer_stats_hrtimer_set_start_info(struct hrtimer *timer) -{ -#ifdef CONFIG_TIMER_STATS - if (timer->start_site) - return; - timer->start_site = __builtin_return_address(0); - memcpy(timer->start_comm, current->comm, TASK_COMM_LEN); - timer->start_pid = current->pid; -#endif -} - -static inline void timer_stats_hrtimer_clear_start_info(struct hrtimer *timer) -{ -#ifdef CONFIG_TIMER_STATS - timer->start_site = NULL; -#endif -} - -static inline void timer_stats_account_hrtimer(struct hrtimer *timer) -{ -#ifdef CONFIG_TIMER_STATS - if (likely(!timer_stats_active)) - return; - timer_stats_update_stats(timer, timer->start_pid, timer->start_site, - timer->function, timer->start_comm, 0); -#endif -} - /* * Counterpart to lock_hrtimer_base above: */ @@ -887,7 +859,7 @@ base->cpu_base->active_bases |= 1 << base->index; - timer->state = HRTIMER_STATE_ENQUEUED; + timer->state |= HRTIMER_STATE_ENQUEUED; return timerqueue_add(&base->active, &timer->node); } @@ -907,11 +879,9 @@ u8 newstate, int reprogram) { struct hrtimer_cpu_base *cpu_base = base->cpu_base; - u8 state = timer->state; - timer->state = newstate; - if (!(state & HRTIMER_STATE_ENQUEUED)) - return; + if (!(timer->state & HRTIMER_STATE_ENQUEUED)) + goto out; if (!timerqueue_del(&base->active, &timer->node)) cpu_base->active_bases &= ~(1 << base->index); @@ -928,6 +898,13 @@ if (reprogram && timer == cpu_base->next_timer) hrtimer_force_reprogram(cpu_base, 1); #endif + +out: + /* + * We need to preserve PINNED state here, otherwise we may end up + * migrating pinned hrtimers as well. + */ + timer->state = newstate | (timer->state & HRTIMER_STATE_PINNED); } /* @@ -949,13 +926,13 @@ * rare case and less expensive than a smp call. */ debug_deactivate(timer); - timer_stats_hrtimer_clear_start_info(timer); reprogram = base->cpu_base == this_cpu_ptr(&hrtimer_bases); if (!restart) state = HRTIMER_STATE_INACTIVE; __remove_hrtimer(timer, base, state, reprogram); + timer->state &= ~HRTIMER_STATE_PINNED; return 1; } return 0; @@ -986,7 +963,7 @@ * relative (HRTIMER_MODE_REL) */ void hrtimer_start_range_ns(struct hrtimer *timer, ktime_t tim, - unsigned long delta_ns, const enum hrtimer_mode mode) + u64 delta_ns, const enum hrtimer_mode mode) { struct hrtimer_clock_base *base, *new_base; unsigned long flags; @@ -1007,7 +984,9 @@ /* Switch the timer base, if necessary: */ new_base = switch_hrtimer_base(timer, base, mode & HRTIMER_MODE_PINNED); - timer_stats_hrtimer_set_start_info(timer); + /* Update pinned state */ + timer->state &= ~HRTIMER_STATE_PINNED; + timer->state |= (!!(mode & HRTIMER_MODE_PINNED)) << HRTIMER_PINNED_SHIFT; leftmost = enqueue_hrtimer(timer, new_base); if (!leftmost) @@ -1145,12 +1124,6 @@ base = hrtimer_clockid_to_base(clock_id); timer->base = &cpu_base->clock_base[base]; timerqueue_init(&timer->node); - -#ifdef CONFIG_TIMER_STATS - timer->start_site = NULL; - timer->start_pid = -1; - memset(timer->start_comm, 0, TASK_COMM_LEN); -#endif } /** @@ -1183,8 +1156,8 @@ cpu_base = READ_ONCE(timer->base->cpu_base); seq = raw_read_seqcount_begin(&cpu_base->seq); - if (timer->state != HRTIMER_STATE_INACTIVE || - cpu_base->running == timer) + if (((timer->state & ~HRTIMER_STATE_PINNED) != + HRTIMER_STATE_INACTIVE) || cpu_base->running == timer) return true; } while (read_seqcount_retry(&cpu_base->seq, seq) || @@ -1234,7 +1207,6 @@ raw_write_seqcount_barrier(&cpu_base->seq); __remove_hrtimer(timer, base, HRTIMER_STATE_INACTIVE, 0); - timer_stats_account_hrtimer(timer); fn = timer->function; /* @@ -1555,7 +1527,7 @@ struct restart_block *restart; struct hrtimer_sleeper t; int ret = 0; - unsigned long slack; + u64 slack; slack = current->timer_slack_ns; if (dl_task(current) || rt_task(current)) @@ -1622,16 +1594,22 @@ hrtimer_init_hres(cpu_base); } -#ifdef CONFIG_HOTPLUG_CPU - +#if defined(CONFIG_HOTPLUG_CPU) static void migrate_hrtimer_list(struct hrtimer_clock_base *old_base, - struct hrtimer_clock_base *new_base) + struct hrtimer_clock_base *new_base, + bool remove_pinned) { struct hrtimer *timer; struct timerqueue_node *node; + struct timerqueue_head pinned; + int is_pinned; + bool is_hotplug = !cpu_online(old_base->cpu_base->cpu); + + timerqueue_init_head(&pinned); while ((node = timerqueue_getnext(&old_base->active))) { timer = container_of(node, struct hrtimer, node); + if (is_hotplug) BUG_ON(hrtimer_callback_running(timer)); debug_deactivate(timer); @@ -1641,6 +1619,13 @@ * under us on another CPU */ __remove_hrtimer(timer, old_base, HRTIMER_STATE_ENQUEUED, 0); + + is_pinned = timer->state & HRTIMER_STATE_PINNED; + if (!remove_pinned && is_pinned) { + timerqueue_add(&pinned, &timer->node); + continue; + } + timer->base = new_base; /* * Enqueue the timers on the new cpu. This does not @@ -1652,17 +1637,23 @@ */ enqueue_hrtimer(timer, new_base); } + + /* Re-queue pinned timers for non-hotplug usecase */ + while ((node = timerqueue_getnext(&pinned))) { + timer = container_of(node, struct hrtimer, node); + + timerqueue_del(&pinned, &timer->node); + enqueue_hrtimer(timer, old_base); + } } -static void migrate_hrtimers(int scpu) +static void __migrate_hrtimers(int scpu, bool remove_pinned) { struct hrtimer_cpu_base *old_base, *new_base; + unsigned long flags; int i; - BUG_ON(cpu_online(scpu)); - tick_cancel_sched_timer(scpu); - - local_irq_disable(); + local_irq_save(flags); old_base = &per_cpu(hrtimer_bases, scpu); new_base = this_cpu_ptr(&hrtimer_bases); /* @@ -1674,7 +1665,7 @@ for (i = 0; i < HRTIMER_MAX_CLOCK_BASES; i++) { migrate_hrtimer_list(&old_base->clock_base[i], - &new_base->clock_base[i]); + &new_base->clock_base[i], remove_pinned); } raw_spin_unlock(&old_base->lock); @@ -1682,7 +1673,20 @@ /* Check, if we got expired work to do */ __hrtimer_peek_ahead_timers(); - local_irq_enable(); + local_irq_restore(flags); +} + +static void migrate_hrtimers(int scpu) +{ + BUG_ON(cpu_online(scpu)); + tick_cancel_sched_timer(scpu); + + __migrate_hrtimers(scpu, true); +} + +void hrtimer_quiesce_cpu(void *cpup) +{ + __migrate_hrtimers(*(int *)cpup, false); } #endif /* CONFIG_HOTPLUG_CPU */ @@ -1732,7 +1736,7 @@ * @clock: timer clock, CLOCK_MONOTONIC or CLOCK_REALTIME */ int __sched -schedule_hrtimeout_range_clock(ktime_t *expires, unsigned long delta, +schedule_hrtimeout_range_clock(ktime_t *expires, u64 delta, const enum hrtimer_mode mode, int clock) { struct hrtimer_sleeper t; @@ -1790,17 +1794,21 @@ * You can set the task state as follows - * * %TASK_UNINTERRUPTIBLE - at least @timeout time is guaranteed to - * pass before the routine returns. + * pass before the routine returns unless the current task is explicitly + * woken up, (e.g. by wake_up_process()). * * %TASK_INTERRUPTIBLE - the routine may return early if a signal is - * delivered to the current task. + * delivered to the current task or the current task is explicitly woken + * up. * * The current task state is guaranteed to be TASK_RUNNING when this * routine returns. * - * Returns 0 when the timer has expired otherwise -EINTR + * Returns 0 when the timer has expired. If the task was woken before the + * timer expired by a signal (only possible in state TASK_INTERRUPTIBLE) or + * by an explicit wakeup, it returns -EINTR. */ -int __sched schedule_hrtimeout_range(ktime_t *expires, unsigned long delta, +int __sched schedule_hrtimeout_range(ktime_t *expires, u64 delta, const enum hrtimer_mode mode) { return schedule_hrtimeout_range_clock(expires, delta, mode, @@ -1820,15 +1828,19 @@ * You can set the task state as follows - * * %TASK_UNINTERRUPTIBLE - at least @timeout time is guaranteed to - * pass before the routine returns. + * pass before the routine returns unless the current task is explicitly + * woken up, (e.g. by wake_up_process()). * * %TASK_INTERRUPTIBLE - the routine may return early if a signal is - * delivered to the current task. + * delivered to the current task or the current task is explicitly woken + * up. * * The current task state is guaranteed to be TASK_RUNNING when this * routine returns. * - * Returns 0 when the timer has expired otherwise -EINTR + * Returns 0 when the timer has expired. If the task was woken before the + * timer expired by a signal (only possible in state TASK_INTERRUPTIBLE) or + * by an explicit wakeup, it returns -EINTR. */ int __sched schedule_hrtimeout(ktime_t *expires, const enum hrtimer_mode mode) diff -ruw linux-4.4.115/kernel/time/Makefile linux-4.4.115-fbx/kernel/time/Makefile --- linux-4.4.115/kernel/time/Makefile 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/kernel/time/Makefile 2019-01-22 16:16:28.715293604 +0100 @@ -9,6 +9,7 @@ endif obj-$(CONFIG_GENERIC_SCHED_CLOCK) += sched_clock.o obj-$(CONFIG_TICK_ONESHOT) += tick-oneshot.o tick-sched.o -obj-$(CONFIG_TIMER_STATS) += timer_stats.o obj-$(CONFIG_DEBUG_FS) += timekeeping_debug.o obj-$(CONFIG_TEST_UDELAY) += test_udelay.o + +ccflags-y += -Idrivers/cpuidle diff -ruw linux-4.4.115/kernel/time/posix-cpu-timers.c linux-4.4.115-fbx/kernel/time/posix-cpu-timers.c --- linux-4.4.115/kernel/time/posix-cpu-timers.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/kernel/time/posix-cpu-timers.c 2019-10-29 09:26:25.641222731 +0100 @@ -1250,7 +1250,7 @@ void set_process_cpu_timer(struct task_struct *tsk, unsigned int clock_idx, cputime_t *newval, cputime_t *oldval) { - unsigned long long now; + unsigned long long now = 0; WARN_ON_ONCE(clock_idx == CPUCLOCK_SCHED); cpu_timer_sample_group(clock_idx, tsk, &now); diff -ruw linux-4.4.115/kernel/time/sched_clock.c linux-4.4.115-fbx/kernel/time/sched_clock.c --- linux-4.4.115/kernel/time/sched_clock.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/kernel/time/sched_clock.c 2019-10-29 09:26:25.641222731 +0100 @@ -70,6 +70,11 @@ static struct hrtimer sched_clock_timer; static int irqtime = -1; +static int initialized; +static u64 suspend_ns; +static u64 suspend_cycles; +static u64 resume_cycles; + core_param(irqtime, irqtime, int, 0400); @@ -231,6 +236,11 @@ pr_debug("Registered %pF as sched_clock source\n", read); } +int sched_clock_initialized(void) +{ + return initialized; +} + void __init sched_clock_postinit(void) { /* @@ -249,6 +259,8 @@ hrtimer_init(&sched_clock_timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL); sched_clock_timer.function = sched_clock_poll; hrtimer_start(&sched_clock_timer, cd.wrap_kt, HRTIMER_MODE_REL); + + initialized = 1; } /* @@ -274,6 +286,11 @@ struct clock_read_data *rd = &cd.read_data[0]; update_sched_clock(); + + suspend_ns = rd->epoch_ns; + suspend_cycles = rd->epoch_cyc; + pr_info("suspend ns:%17llu suspend cycles:%17llu\n", + rd->epoch_ns, rd->epoch_cyc); hrtimer_cancel(&sched_clock_timer); rd->read_sched_clock = suspended_sched_clock_read; @@ -285,6 +302,8 @@ struct clock_read_data *rd = &cd.read_data[0]; rd->epoch_cyc = cd.actual_read_sched_clock(); + resume_cycles = rd->epoch_cyc; + pr_info("resume cycles:%17llu\n", rd->epoch_cyc); hrtimer_start(&sched_clock_timer, cd.wrap_kt, HRTIMER_MODE_REL); rd->read_sched_clock = cd.actual_read_sched_clock; } diff -ruw linux-4.4.115/kernel/time/tick-sched.c linux-4.4.115-fbx/kernel/time/tick-sched.c --- linux-4.4.115/kernel/time/tick-sched.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/kernel/time/tick-sched.c 2019-10-29 09:26:25.641222731 +0100 @@ -19,11 +19,13 @@ #include #include #include +#include #include #include #include #include #include +#include #include @@ -31,6 +33,10 @@ #include +struct rq_data rq_info; +struct workqueue_struct *rq_wq; +spinlock_t rq_lock; + /* * Per cpu nohz control structure */ @@ -41,6 +47,21 @@ */ static ktime_t last_jiffies_update; +u64 jiffy_to_ktime_ns(u64 *now, u64 *jiffy_ktime_ns) +{ + u64 cur_jiffies; + unsigned long seq; + + do { + seq = read_seqbegin(&jiffies_lock); + *now = ktime_get_ns(); + *jiffy_ktime_ns = ktime_to_ns(last_jiffies_update); + cur_jiffies = get_jiffies_64(); + } while (read_seqretry(&jiffies_lock, seq)); + + return cur_jiffies; +} + struct tick_sched *tick_get_tick_sched(int cpu) { return &per_cpu(tick_cpu_sched, cpu); @@ -143,7 +164,7 @@ * when we go busy again does not account too much ticks. */ if (ts->tick_stopped) { - touch_softlockup_watchdog(); + touch_softlockup_watchdog_sched(); if (is_idle_task(current)) ts->idle_jiffies++; } @@ -430,7 +451,7 @@ tick_do_update_jiffies64(now); local_irq_restore(flags); - touch_softlockup_watchdog(); + touch_softlockup_watchdog_sched(); } /* @@ -716,7 +737,7 @@ update_cpu_load_nohz(); calc_load_exit_idle(); - touch_softlockup_watchdog(); + touch_softlockup_watchdog_sched(); /* * Cancel the scheduled timer and restore the tick */ @@ -804,6 +825,11 @@ now = tick_nohz_start_idle(ts); +#ifdef CONFIG_SMP + if (check_pending_deferrable_timers(cpu)) + raise_softirq_irqoff(TIMER_SOFTIRQ); +#endif + if (can_stop_idle_tick(cpu, ts)) { int was_stopped = ts->tick_stopped; @@ -885,6 +911,18 @@ return ts->sleep_length; } +/** + * tick_nohz_get_idle_calls - return the current idle calls counter value + * + * Called from the schedutil frequency scaling governor in scheduler context. + */ +unsigned long tick_nohz_get_idle_calls(void) +{ + struct tick_sched *ts = this_cpu_ptr(&tick_cpu_sched); + + return ts->idle_calls; +} + static void tick_nohz_account_idle_ticks(struct tick_sched *ts) { #ifndef CONFIG_VIRT_CPU_ACCOUNTING_NATIVE @@ -1064,6 +1102,51 @@ * High resolution timer specific code */ #ifdef CONFIG_HIGH_RES_TIMERS +static void update_rq_stats(void) +{ + unsigned long jiffy_gap = 0; + unsigned int rq_avg = 0; + unsigned long flags = 0; + + jiffy_gap = jiffies - rq_info.rq_poll_last_jiffy; + + if (jiffy_gap >= rq_info.rq_poll_jiffies) { + + spin_lock_irqsave(&rq_lock, flags); + + if (!rq_info.rq_avg) + rq_info.rq_poll_total_jiffies = 0; + + rq_avg = nr_running() * 10; + + if (rq_info.rq_poll_total_jiffies) { + rq_avg = (rq_avg * jiffy_gap) + + (rq_info.rq_avg * + rq_info.rq_poll_total_jiffies); + do_div(rq_avg, + rq_info.rq_poll_total_jiffies + jiffy_gap); + } + + rq_info.rq_avg = rq_avg; + rq_info.rq_poll_total_jiffies += jiffy_gap; + rq_info.rq_poll_last_jiffy = jiffies; + + spin_unlock_irqrestore(&rq_lock, flags); + } +} + +static void wakeup_user(void) +{ + unsigned long jiffy_gap; + + jiffy_gap = jiffies - rq_info.def_timer_last_jiffy; + + if (jiffy_gap >= rq_info.def_timer_jiffies) { + rq_info.def_timer_last_jiffy = jiffies; + queue_work(rq_wq, &rq_info.def_timer_work); + } +} + /* * We rearm the timer until we get disabled by the idle code. * Called with interrupts disabled. @@ -1081,9 +1164,23 @@ * Do not call, when we are not in irq context and have * no valid regs pointer */ - if (regs) + if (regs) { tick_sched_handle(ts, regs); + if (rq_info.init == 1 && + tick_do_timer_cpu == smp_processor_id()) { + /* + * update run queue statistics + */ + update_rq_stats(); + + /* + * wakeup user if needed + */ + wakeup_user(); + } + } + /* No need to reprogram if we are in idle or full dynticks mode */ if (unlikely(ts->tick_stopped)) return HRTIMER_NORESTART; @@ -1196,3 +1293,8 @@ tick_nohz_switch_to_nohz(); return 0; } + +ktime_t * get_next_event_cpu(unsigned int cpu) +{ + return &(per_cpu(tick_cpu_device, cpu).evtdev->next_event); +} diff -ruw linux-4.4.115/kernel/time/timekeeping.c linux-4.4.115-fbx/kernel/time/timekeeping.c --- linux-4.4.115/kernel/time/timekeeping.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/kernel/time/timekeeping.c 2019-10-29 09:26:25.645222770 +0100 @@ -70,6 +70,10 @@ tk->tkr_mono.xtime_nsec -= (u64)NSEC_PER_SEC << tk->tkr_mono.shift; tk->xtime_sec++; } + while (tk->tkr_raw.xtime_nsec >= ((u64)NSEC_PER_SEC << tk->tkr_raw.shift)) { + tk->tkr_raw.xtime_nsec -= (u64)NSEC_PER_SEC << tk->tkr_raw.shift; + tk->raw_sec++; + } } static inline struct timespec64 tk_xtime(struct timekeeper *tk) @@ -277,18 +281,19 @@ /* Go back from cycles -> shifted ns */ tk->xtime_interval = (u64) interval * clock->mult; tk->xtime_remainder = ntpinterval - tk->xtime_interval; - tk->raw_interval = - ((u64) interval * clock->mult) >> clock->shift; + tk->raw_interval = interval * clock->mult; /* if changing clocks, convert xtime_nsec shift units */ if (old_clock) { int shift_change = clock->shift - old_clock->shift; - if (shift_change < 0) + if (shift_change < 0) { tk->tkr_mono.xtime_nsec >>= -shift_change; - else + tk->tkr_raw.xtime_nsec >>= -shift_change; + } else { tk->tkr_mono.xtime_nsec <<= shift_change; + tk->tkr_raw.xtime_nsec <<= shift_change; + } } - tk->tkr_raw.xtime_nsec = 0; tk->tkr_mono.shift = clock->shift; tk->tkr_raw.shift = clock->shift; @@ -442,6 +447,35 @@ } EXPORT_SYMBOL_GPL(ktime_get_raw_fast_ns); +/** + * ktime_get_boot_fast_ns - NMI safe and fast access to boot clock. + * + * To keep it NMI safe since we're accessing from tracing, we're not using a + * separate timekeeper with updates to monotonic clock and boot offset + * protected with seqlocks. This has the following minor side effects: + * + * (1) Its possible that a timestamp be taken after the boot offset is updated + * but before the timekeeper is updated. If this happens, the new boot offset + * is added to the old timekeeping making the clock appear to update slightly + * earlier: + * CPU 0 CPU 1 + * timekeeping_inject_sleeptime64() + * __timekeeping_inject_sleeptime(tk, delta); + * timestamp(); + * timekeeping_update(tk, TK_CLEAR_NTP...); + * + * (2) On 32-bit systems, the 64-bit boot offset (tk->offs_boot) may be + * partially updated. Since the tk->offs_boot update is a rare event, this + * should be a rare occurrence which postprocessing should be able to handle. + */ +u64 notrace ktime_get_boot_fast_ns(void) +{ + struct timekeeper *tk = &tk_core.timekeeper; + + return (ktime_get_mono_fast_ns() + ktime_to_ns(tk->offs_boot)); +} +EXPORT_SYMBOL_GPL(ktime_get_boot_fast_ns); + /* Suspend-time cycles value for halted fast timekeeper. */ static cycle_t cycles_at_suspend; @@ -588,9 +622,6 @@ nsec = (u32) tk->wall_to_monotonic.tv_nsec; tk->tkr_mono.base = ns_to_ktime(seconds * NSEC_PER_SEC + nsec); - /* Update the monotonic raw base */ - tk->tkr_raw.base = timespec64_to_ktime(tk->raw_time); - /* * The sum of the nanoseconds portions of xtime and * wall_to_monotonic can be greater/equal one second. Take @@ -600,6 +631,9 @@ if (nsec >= NSEC_PER_SEC) seconds++; tk->ktime_sec = seconds; + + /* Update the monotonic raw base */ + tk->tkr_raw.base = ns_to_ktime(tk->raw_sec * NSEC_PER_SEC); } /* must hold timekeeper_lock */ @@ -641,7 +675,6 @@ static void timekeeping_forward_now(struct timekeeper *tk) { cycle_t cycle_now, delta; - s64 nsec; cycle_now = tk_clock_read(&tk->tkr_mono); delta = clocksource_delta(cycle_now, tk->tkr_mono.cycle_last, tk->tkr_mono.mask); @@ -653,10 +686,13 @@ /* If arch requires, add in get_arch_timeoffset() */ tk->tkr_mono.xtime_nsec += (u64)arch_gettimeoffset() << tk->tkr_mono.shift; - tk_normalize_xtime(tk); - nsec = clocksource_cyc2ns(delta, tk->tkr_raw.mult, tk->tkr_raw.shift); - timespec64_add_ns(&tk->raw_time, nsec); + tk->tkr_raw.xtime_nsec += delta * tk->tkr_raw.mult; + + /* If arch requires, add in get_arch_timeoffset() */ + tk->tkr_raw.xtime_nsec += (u64)arch_gettimeoffset() << tk->tkr_raw.shift; + + tk_normalize_xtime(tk); } /** @@ -1150,19 +1186,18 @@ void getrawmonotonic64(struct timespec64 *ts) { struct timekeeper *tk = &tk_core.timekeeper; - struct timespec64 ts64; unsigned long seq; s64 nsecs; do { seq = read_seqcount_begin(&tk_core.seq); + ts->tv_sec = tk->raw_sec; nsecs = timekeeping_get_ns(&tk->tkr_raw); - ts64 = tk->raw_time; } while (read_seqcount_retry(&tk_core.seq, seq)); - timespec64_add_ns(&ts64, nsecs); - *ts = ts64; + ts->tv_nsec = 0; + timespec64_add_ns(ts, nsecs); } EXPORT_SYMBOL(getrawmonotonic64); @@ -1286,8 +1321,7 @@ tk_setup_internals(tk, clock); tk_set_xtime(tk, &now); - tk->raw_time.tv_sec = 0; - tk->raw_time.tv_nsec = 0; + tk->raw_sec = 0; if (boot.tv_sec == 0 && boot.tv_nsec == 0) boot = tk_xtime(tk); @@ -1767,7 +1801,7 @@ unsigned int *clock_set) { cycle_t interval = tk->cycle_interval << shift; - u64 raw_nsecs; + u64 snsec_per_sec; /* If the offset is smaller than a shifted interval, do nothing */ if (offset < interval) @@ -1782,14 +1816,12 @@ *clock_set |= accumulate_nsecs_to_secs(tk); /* Accumulate raw time */ - raw_nsecs = (u64)tk->raw_interval << shift; - raw_nsecs += tk->raw_time.tv_nsec; - if (raw_nsecs >= NSEC_PER_SEC) { - u64 raw_secs = raw_nsecs; - raw_nsecs = do_div(raw_secs, NSEC_PER_SEC); - tk->raw_time.tv_sec += raw_secs; + tk->tkr_raw.xtime_nsec += tk->raw_interval << shift; + snsec_per_sec = (u64)NSEC_PER_SEC << tk->tkr_raw.shift; + while (tk->tkr_raw.xtime_nsec >= snsec_per_sec) { + tk->tkr_raw.xtime_nsec -= snsec_per_sec; + tk->raw_sec++; } - tk->raw_time.tv_nsec = raw_nsecs; /* Accumulate error between NTP and clock interval */ tk->ntp_error += tk->ntp_tick << shift; diff -ruw linux-4.4.115/kernel/time/timer.c linux-4.4.115-fbx/kernel/time/timer.c --- linux-4.4.115/kernel/time/timer.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/kernel/time/timer.c 2019-01-22 16:16:28.723293677 +0100 @@ -94,12 +94,16 @@ struct tvec tv5; } ____cacheline_aligned; +static inline void __run_timers(struct tvec_base *base); static DEFINE_PER_CPU(struct tvec_base, tvec_bases); #if defined(CONFIG_SMP) && defined(CONFIG_NO_HZ_COMMON) unsigned int sysctl_timer_migration = 1; +struct tvec_base tvec_base_deferrable; +static atomic_t deferrable_pending; + void timers_update_migration(bool update_nohz) { bool on = sysctl_timer_migration && tick_nohz_active; @@ -135,18 +139,66 @@ } static inline struct tvec_base *get_target_base(struct tvec_base *base, - int pinned) + int pinned, u32 timer_flags) { + if (!pinned && !(timer_flags & TIMER_PINNED_ON_CPU) && + (timer_flags & TIMER_DEFERRABLE)) + return &tvec_base_deferrable; if (pinned || !base->migration_enabled) return this_cpu_ptr(&tvec_bases); return per_cpu_ptr(&tvec_bases, get_nohz_timer_target()); } + +static inline void __run_deferrable_timers(void) +{ + if ((atomic_cmpxchg(&deferrable_pending, 1, 0) && + tick_do_timer_cpu == TICK_DO_TIMER_NONE) || + tick_do_timer_cpu == smp_processor_id()) { + if (time_after_eq(jiffies, + tvec_base_deferrable.timer_jiffies)) + __run_timers(&tvec_base_deferrable); + } +} + +static inline void init_timer_deferrable_global(void) +{ + tvec_base_deferrable.cpu = nr_cpu_ids; + spin_lock_init(&tvec_base_deferrable.lock); + tvec_base_deferrable.timer_jiffies = jiffies; + tvec_base_deferrable.next_timer = tvec_base_deferrable.timer_jiffies; +} + +static inline struct tvec_base *get_timer_base(u32 timer_flags) +{ + if (!(timer_flags & TIMER_PINNED_ON_CPU) && + timer_flags & TIMER_DEFERRABLE) + return &tvec_base_deferrable; + else + return per_cpu_ptr(&tvec_bases, timer_flags & TIMER_CPUMASK); +} #else static inline struct tvec_base *get_target_base(struct tvec_base *base, - int pinned) + int pinned, u32 timer_flags) { return this_cpu_ptr(&tvec_bases); } + +static inline void __run_deferrable_timers(void) +{ +} + +static inline void init_timer_deferrable_global(void) +{ + /* + * initialize cpu unbound deferrable timer base only when CONFIG_SMP. + * UP kernel handles the timers with cpu 0 timer base. + */ +} + +static inline struct tvec_base *get_timer_base(u32 timer_flags) +{ + return per_cpu_ptr(&tvec_bases, timer_flags & TIMER_CPUMASK); +} #endif static unsigned long round_jiffies_common(unsigned long j, int cpu, @@ -448,38 +500,6 @@ } } -#ifdef CONFIG_TIMER_STATS -void __timer_stats_timer_set_start_info(struct timer_list *timer, void *addr) -{ - if (timer->start_site) - return; - - timer->start_site = addr; - memcpy(timer->start_comm, current->comm, TASK_COMM_LEN); - timer->start_pid = current->pid; -} - -static void timer_stats_account_timer(struct timer_list *timer) -{ - void *site; - - /* - * start_site can be concurrently reset by - * timer_stats_timer_clear_start_info() - */ - site = READ_ONCE(timer->start_site); - if (likely(!site)) - return; - - timer_stats_update_stats(timer, timer->start_pid, site, - timer->function, timer->start_comm, - timer->flags); -} - -#else -static void timer_stats_account_timer(struct timer_list *timer) {} -#endif - #ifdef CONFIG_DEBUG_OBJECTS_TIMERS static struct debug_obj_descr timer_debug_descr; @@ -682,11 +702,6 @@ timer->entry.pprev = NULL; timer->flags = flags | raw_smp_processor_id(); timer->slack = -1; -#ifdef CONFIG_TIMER_STATS - timer->start_site = NULL; - timer->start_pid = -1; - memset(timer->start_comm, 0, TASK_COMM_LEN); -#endif lockdep_init_map(&timer->lockdep_map, name, key, 0); } @@ -775,7 +790,7 @@ tf = READ_ONCE(timer->flags); if (!(tf & TIMER_MIGRATING)) { - base = per_cpu_ptr(&tvec_bases, tf & TIMER_CPUMASK); + base = get_timer_base(tf); spin_lock_irqsave(&base->lock, *flags); if (timer->flags == tf) return base; @@ -793,7 +808,6 @@ unsigned long flags; int ret = 0; - timer_stats_timer_set_start_info(timer); BUG_ON(!timer->function); base = lock_timer_base(timer, &flags); @@ -804,7 +818,7 @@ debug_activate(timer, expires); - new_base = get_target_base(base, pinned); + new_base = get_target_base(base, pinned, timer->flags); if (base != new_base) { /* @@ -826,6 +840,10 @@ } } + if (pinned == TIMER_PINNED) + timer->flags |= TIMER_PINNED_ON_CPU; + else + timer->flags &= ~TIMER_PINNED_ON_CPU; timer->expires = expires; internal_add_timer(base, timer); @@ -988,7 +1006,6 @@ struct tvec_base *base; unsigned long flags; - timer_stats_timer_set_start_info(timer); BUG_ON(timer_pending(timer) || !timer->function); /* @@ -1007,6 +1024,7 @@ (timer->flags & ~TIMER_BASEMASK) | cpu); } + timer->flags |= TIMER_PINNED_ON_CPU; debug_activate(timer, timer->expires); internal_add_timer(base, timer); spin_unlock_irqrestore(&base->lock, flags); @@ -1032,7 +1050,6 @@ debug_assert_init(timer); - timer_stats_timer_clear_start_info(timer); if (timer_pending(timer)) { base = lock_timer_base(timer, &flags); ret = detach_if_pending(timer, base, true); @@ -1060,10 +1077,9 @@ base = lock_timer_base(timer, &flags); - if (base->running_timer != timer) { - timer_stats_timer_clear_start_info(timer); + if (base->running_timer != timer) ret = detach_if_pending(timer, base, true); - } + spin_unlock_irqrestore(&base->lock, flags); return ret; @@ -1247,8 +1263,6 @@ data = timer->data; irqsafe = timer->flags & TIMER_IRQSAFE; - timer_stats_account_timer(timer); - base->running_timer = timer; detach_expired_timer(timer, base); @@ -1376,6 +1390,30 @@ return DIV_ROUND_UP_ULL(nextevt, TICK_NSEC) * TICK_NSEC; } +#ifdef CONFIG_SMP +/* + * check_pending_deferrable_timers - Check for unbound deferrable timer expiry. + * @cpu - Current CPU + * + * The function checks whether any global deferrable pending timers + * are exipired or not. This function does not check cpu bounded + * diferrable pending timers expiry. + * + * The function returns true when a cpu unbounded deferrable timer is expired. + */ +bool check_pending_deferrable_timers(int cpu) +{ + if (cpu == tick_do_timer_cpu || + tick_do_timer_cpu == TICK_DO_TIMER_NONE) { + if (time_after_eq(jiffies, tvec_base_deferrable.timer_jiffies) + && !atomic_cmpxchg(&deferrable_pending, 0, 1)) { + return true; + } + } + return false; +} +#endif + /** * get_next_timer_interrupt - return the time (clock mono) of the next timer * @basej: base time jiffies @@ -1440,6 +1478,8 @@ { struct tvec_base *base = this_cpu_ptr(&tvec_bases); + __run_deferrable_timers(); + if (time_after_eq(jiffies, base->timer_jiffies)) __run_timers(base); } @@ -1482,11 +1522,12 @@ * You can set the task state as follows - * * %TASK_UNINTERRUPTIBLE - at least @timeout jiffies are guaranteed to - * pass before the routine returns. The routine will return 0 + * pass before the routine returns unless the current task is explicitly + * woken up, (e.g. by wake_up_process())". * * %TASK_INTERRUPTIBLE - the routine may return early if a signal is - * delivered to the current task. In this case the remaining time - * in jiffies will be returned, or 0 if the timer expired in time + * delivered to the current task or the current task is explicitly woken + * up. * * The current task state is guaranteed to be TASK_RUNNING when this * routine returns. @@ -1495,7 +1536,9 @@ * the CPU away without a bound on the timeout. In this case the return * value will be %MAX_SCHEDULE_TIMEOUT. * - * In all cases the return value is guaranteed to be non-negative. + * Returns 0 when the timer has expired otherwise the remaining time in + * jiffies will be returned. In all cases the return value is guaranteed + * to be non-negative. */ signed long __sched schedule_timeout(signed long timeout) { @@ -1573,56 +1616,82 @@ } EXPORT_SYMBOL(schedule_timeout_uninterruptible); -#ifdef CONFIG_HOTPLUG_CPU -static void migrate_timer_list(struct tvec_base *new_base, struct hlist_head *head) +#if defined(CONFIG_HOTPLUG_CPU) +static void migrate_timer_list(struct tvec_base *new_base, + struct hlist_head *head, bool remove_pinned) { struct timer_list *timer; int cpu = new_base->cpu; + struct hlist_node *n; + int is_pinned; - while (!hlist_empty(head)) { - timer = hlist_entry(head->first, struct timer_list, entry); - /* We ignore the accounting on the dying cpu */ - detach_timer(timer, false); + hlist_for_each_entry_safe(timer, n, head, entry) { + is_pinned = timer->flags & TIMER_PINNED_ON_CPU; + if (!remove_pinned && is_pinned) + continue; + + detach_if_pending(timer, get_timer_base(timer->flags), false); timer->flags = (timer->flags & ~TIMER_BASEMASK) | cpu; internal_add_timer(new_base, timer); } } -static void migrate_timers(int cpu) +static void __migrate_timers(int cpu, bool remove_pinned) { struct tvec_base *old_base; struct tvec_base *new_base; + unsigned long flags; int i; - BUG_ON(cpu_online(cpu)); old_base = per_cpu_ptr(&tvec_bases, cpu); new_base = get_cpu_ptr(&tvec_bases); /* * The caller is globally serialized and nobody else * takes two locks at once, deadlock is not possible. */ - spin_lock_irq(&new_base->lock); + spin_lock_irqsave(&new_base->lock, flags); spin_lock_nested(&old_base->lock, SINGLE_DEPTH_NESTING); + /* + * If we're in the hotplug path, kill the system if there's a running + * timer. It's ok to have a running timer in the isolation case - the + * currently running or just expired timers are off of the timer wheel + * and so everything else can be migrated off. + */ + if (!cpu_online(cpu)) BUG_ON(old_base->running_timer); for (i = 0; i < TVR_SIZE; i++) - migrate_timer_list(new_base, old_base->tv1.vec + i); + migrate_timer_list(new_base, old_base->tv1.vec + i, + remove_pinned); for (i = 0; i < TVN_SIZE; i++) { - migrate_timer_list(new_base, old_base->tv2.vec + i); - migrate_timer_list(new_base, old_base->tv3.vec + i); - migrate_timer_list(new_base, old_base->tv4.vec + i); - migrate_timer_list(new_base, old_base->tv5.vec + i); + migrate_timer_list(new_base, old_base->tv2.vec + i, + remove_pinned); + migrate_timer_list(new_base, old_base->tv3.vec + i, + remove_pinned); + migrate_timer_list(new_base, old_base->tv4.vec + i, + remove_pinned); + migrate_timer_list(new_base, old_base->tv5.vec + i, + remove_pinned); } - old_base->active_timers = 0; - old_base->all_timers = 0; - spin_unlock(&old_base->lock); - spin_unlock_irq(&new_base->lock); + spin_unlock_irqrestore(&new_base->lock, flags); put_cpu_ptr(&tvec_bases); } +/* Migrate timers from 'cpu' to this_cpu */ +static void migrate_timers(int cpu) +{ + BUG_ON(cpu_online(cpu)); + __migrate_timers(cpu, true); +} + +void timer_quiesce_cpu(void *cpup) +{ + __migrate_timers(*(int *)cpup, false); +} + static int timer_cpu_notify(struct notifier_block *self, unsigned long action, void *hcpu) { @@ -1663,12 +1732,13 @@ for_each_possible_cpu(cpu) init_timer_cpu(cpu); + + init_timer_deferrable_global(); } void __init init_timers(void) { init_timer_cpus(); - init_timer_stats(); timer_register_cpu_notifier(); open_softirq(TIMER_SOFTIRQ, run_timer_softirq); } @@ -1702,16 +1772,6 @@ EXPORT_SYMBOL(msleep_interruptible); -static void __sched do_usleep_range(unsigned long min, unsigned long max) -{ - ktime_t kmin; - unsigned long delta; - - kmin = ktime_set(0, min * NSEC_PER_USEC); - delta = (max - min) * NSEC_PER_USEC; - schedule_hrtimeout_range(&kmin, delta, HRTIMER_MODE_REL); -} - /** * usleep_range - Drop in replacement for udelay where wakeup is flexible * @min: Minimum time in usecs to sleep @@ -1719,7 +1779,14 @@ */ void __sched usleep_range(unsigned long min, unsigned long max) { + ktime_t exp = ktime_add_us(ktime_get(), min); + u64 delta = (u64)(max - min) * NSEC_PER_USEC; + + for (;;) { __set_current_state(TASK_UNINTERRUPTIBLE); - do_usleep_range(min, max); + /* Do not return before the requested sleep time has elapsed */ + if (!schedule_hrtimeout_range(&exp, delta, HRTIMER_MODE_ABS)) + break; + } } EXPORT_SYMBOL(usleep_range); diff -ruw linux-4.4.115/kernel/time/timer_list.c linux-4.4.115-fbx/kernel/time/timer_list.c --- linux-4.4.115/kernel/time/timer_list.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/kernel/time/timer_list.c 2019-10-29 09:26:25.645222770 +0100 @@ -62,21 +62,11 @@ print_timer(struct seq_file *m, struct hrtimer *taddr, struct hrtimer *timer, int idx, u64 now) { -#ifdef CONFIG_TIMER_STATS - char tmp[TASK_COMM_LEN + 1]; -#endif SEQ_printf(m, " #%d: ", idx); print_name_offset(m, taddr); SEQ_printf(m, ", "); print_name_offset(m, timer->function); SEQ_printf(m, ", S:%02x", timer->state); -#ifdef CONFIG_TIMER_STATS - SEQ_printf(m, ", "); - print_name_offset(m, timer->start_site); - memcpy(tmp, timer->start_comm, TASK_COMM_LEN); - tmp[TASK_COMM_LEN] = 0; - SEQ_printf(m, ", %s/%d", tmp, timer->start_pid); -#endif SEQ_printf(m, "\n"); SEQ_printf(m, " # expires at %Lu-%Lu nsecs [in %Ld to %Ld nsecs]\n", (unsigned long long)ktime_to_ns(hrtimer_get_softexpires(timer)), diff -ruw linux-4.4.115/kernel/trace/blktrace.c linux-4.4.115-fbx/kernel/trace/blktrace.c --- linux-4.4.115/kernel/trace/blktrace.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/kernel/trace/blktrace.c 2019-10-29 09:26:25.645222770 +0100 @@ -199,9 +199,9 @@ * blk_io_trace structure and places it in a per-cpu subbuffer. */ static void __blk_add_trace(struct blk_trace *bt, sector_t sector, int bytes, - int rw, u32 what, int error, int pdu_len, void *pdu_data) + int rw, u32 what, int error, int pdu_len, + void *pdu_data, struct task_struct *tsk) { - struct task_struct *tsk = current; struct ring_buffer_event *event = NULL; struct ring_buffer *buffer = NULL; struct blk_io_trace *t; @@ -708,18 +708,33 @@ unsigned int nr_bytes, u32 what) { struct blk_trace *bt = q->blk_trace; + struct task_struct *tsk = current; if (likely(!bt)) return; + /* + * Use the bio context for all events except ISSUE and + * COMPLETE events. + * + * Not all the pages in the bio are dirtied by the same task but + * most likely it will be, since the sectors accessed on the device + * must be adjacent. + */ + if (!((what == BLK_TA_ISSUE) || (what == BLK_TA_COMPLETE)) && + bio_has_data(rq->bio) && rq->bio->bi_io_vec && + rq->bio->bi_io_vec->bv_page && + rq->bio->bi_io_vec->bv_page->tsk_dirty) + tsk = rq->bio->bi_io_vec->bv_page->tsk_dirty; + if (rq->cmd_type == REQ_TYPE_BLOCK_PC) { what |= BLK_TC_ACT(BLK_TC_PC); __blk_add_trace(bt, 0, nr_bytes, rq->cmd_flags, - what, rq->errors, rq->cmd_len, rq->cmd); + what, rq->errors, rq->cmd_len, rq->cmd, tsk); } else { what |= BLK_TC_ACT(BLK_TC_FS); __blk_add_trace(bt, blk_rq_pos(rq), nr_bytes, - rq->cmd_flags, what, rq->errors, 0, NULL); + rq->cmd_flags, what, rq->errors, 0, NULL, tsk); } } @@ -771,12 +786,22 @@ u32 what, int error) { struct blk_trace *bt = q->blk_trace; + struct task_struct *tsk = current; if (likely(!bt)) return; + /* + * Not all the pages in the bio are dirtied by the same task but + * most likely it will be, since the sectors accessed on the device + * must be adjacent. + */ + if (bio_has_data(bio) && bio->bi_io_vec && bio->bi_io_vec->bv_page && + bio->bi_io_vec->bv_page->tsk_dirty) + tsk = bio->bi_io_vec->bv_page->tsk_dirty; + __blk_add_trace(bt, bio->bi_iter.bi_sector, bio->bi_iter.bi_size, - bio->bi_rw, what, error, 0, NULL); + bio->bi_rw, what, error, 0, NULL, tsk); } static void blk_add_trace_bio_bounce(void *ignore, @@ -824,7 +849,8 @@ struct blk_trace *bt = q->blk_trace; if (bt) - __blk_add_trace(bt, 0, 0, rw, BLK_TA_GETRQ, 0, 0, NULL); + __blk_add_trace(bt, 0, 0, rw, BLK_TA_GETRQ, 0, 0, + NULL, current); } } @@ -840,7 +866,7 @@ if (bt) __blk_add_trace(bt, 0, 0, rw, BLK_TA_SLEEPRQ, - 0, 0, NULL); + 0, 0, NULL, current); } } @@ -849,7 +875,8 @@ struct blk_trace *bt = q->blk_trace; if (bt) - __blk_add_trace(bt, 0, 0, 0, BLK_TA_PLUG, 0, 0, NULL); + __blk_add_trace(bt, 0, 0, 0, BLK_TA_PLUG, 0, 0, NULL, + current); } static void blk_add_trace_unplug(void *ignore, struct request_queue *q, @@ -866,7 +893,8 @@ else what = BLK_TA_UNPLUG_TIMER; - __blk_add_trace(bt, 0, 0, 0, what, 0, sizeof(rpdu), &rpdu); + __blk_add_trace(bt, 0, 0, 0, what, 0, sizeof(rpdu), &rpdu, + current); } } @@ -875,13 +903,19 @@ unsigned int pdu) { struct blk_trace *bt = q->blk_trace; + struct task_struct *tsk = current; if (bt) { __be64 rpdu = cpu_to_be64(pdu); + if (bio_has_data(bio) && bio->bi_io_vec && + bio->bi_io_vec->bv_page && + bio->bi_io_vec->bv_page->tsk_dirty) + tsk = bio->bi_io_vec->bv_page->tsk_dirty; + __blk_add_trace(bt, bio->bi_iter.bi_sector, bio->bi_iter.bi_size, bio->bi_rw, BLK_TA_SPLIT, - bio->bi_error, sizeof(rpdu), &rpdu); + bio->bi_error, sizeof(rpdu), &rpdu, tsk); } } @@ -904,6 +938,7 @@ { struct blk_trace *bt = q->blk_trace; struct blk_io_trace_remap r; + struct task_struct *tsk = current; if (likely(!bt)) return; @@ -912,9 +947,14 @@ r.device_to = cpu_to_be32(bio->bi_bdev->bd_dev); r.sector_from = cpu_to_be64(from); + if (bio_has_data(bio) && bio->bi_io_vec && + bio->bi_io_vec->bv_page && + bio->bi_io_vec->bv_page->tsk_dirty) + tsk = bio->bi_io_vec->bv_page->tsk_dirty; + __blk_add_trace(bt, bio->bi_iter.bi_sector, bio->bi_iter.bi_size, bio->bi_rw, BLK_TA_REMAP, bio->bi_error, - sizeof(r), &r); + sizeof(r), &r, tsk); } /** @@ -937,6 +977,7 @@ { struct blk_trace *bt = q->blk_trace; struct blk_io_trace_remap r; + struct task_struct *tsk = current; if (likely(!bt)) return; @@ -945,9 +986,14 @@ r.device_to = cpu_to_be32(disk_devt(rq->rq_disk)); r.sector_from = cpu_to_be64(from); + if (bio_has_data(rq->bio) && rq->bio->bi_io_vec && + rq->bio->bi_io_vec->bv_page && + rq->bio->bi_io_vec->bv_page->tsk_dirty) + tsk = rq->bio->bi_io_vec->bv_page->tsk_dirty; + __blk_add_trace(bt, blk_rq_pos(rq), blk_rq_bytes(rq), rq_data_dir(rq), BLK_TA_REMAP, !!rq->errors, - sizeof(r), &r); + sizeof(r), &r, tsk); } /** @@ -966,16 +1012,22 @@ void *data, size_t len) { struct blk_trace *bt = q->blk_trace; + struct task_struct *tsk = current; if (likely(!bt)) return; + if (bio_has_data(rq->bio) && rq->bio->bi_io_vec && + rq->bio->bi_io_vec->bv_page && + rq->bio->bi_io_vec->bv_page->tsk_dirty) + tsk = rq->bio->bi_io_vec->bv_page->tsk_dirty; + if (rq->cmd_type == REQ_TYPE_BLOCK_PC) __blk_add_trace(bt, 0, blk_rq_bytes(rq), 0, - BLK_TA_DRV_DATA, rq->errors, len, data); + BLK_TA_DRV_DATA, rq->errors, len, data, tsk); else __blk_add_trace(bt, blk_rq_pos(rq), blk_rq_bytes(rq), 0, - BLK_TA_DRV_DATA, rq->errors, len, data); + BLK_TA_DRV_DATA, rq->errors, len, data, tsk); } EXPORT_SYMBOL_GPL(blk_add_driver_data); diff -ruw linux-4.4.115/kernel/trace/Kconfig linux-4.4.115-fbx/kernel/trace/Kconfig --- linux-4.4.115/kernel/trace/Kconfig 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/kernel/trace/Kconfig 2019-01-22 16:16:28.727293713 +0100 @@ -77,6 +77,9 @@ select CONTEXT_SWITCH_TRACER bool +config GPU_TRACEPOINTS + bool + config CONTEXT_SWITCH_TRACER bool @@ -86,6 +89,31 @@ Allow the use of ring_buffer_swap_cpu. Adds a very slight overhead to tracing when enabled. +config IPC_LOGGING + bool "Debug Logging for IPC Drivers" + select GENERIC_TRACER + help + This option allows the debug logging for IPC Drivers. + + If in doubt, say no. + +config QCOM_RTB + bool "Register tracing" + help + Add support for logging different events to a small uncached + region. This is designed to aid in debugging reset cases where the + caches may not be flushed before the target resets. + +config QCOM_RTB_SEPARATE_CPUS + bool "Separate entries for each cpu" + depends on QCOM_RTB + depends on SMP + help + Under some circumstances, it may be beneficial to give dedicated space + for each cpu to log accesses. Selecting this option will log each cpu + separately. This will guarantee that the last acesses for each cpu + will be logged but there will be fewer entries per cpu + # All tracer options should select GENERIC_TRACER. For those options that are # enabled by all tracers (context switch and event tracer) they select TRACING. # This allows those options to appear when no other tracer is selected. But the @@ -162,6 +190,17 @@ address on the current task structure into a stack of calls. +config PREEMPTIRQ_EVENTS + bool "Enable trace events for preempt and irq disable/enable" + select TRACE_IRQFLAGS + depends on DEBUG_PREEMPT || !PROVE_LOCKING + default n + help + Enable tracing of disable and enable events for preemption and irqs. + For tracing preempt disable/enable events, DEBUG_PREEMPT must be + enabled. For tracing irq disable/enable events, PROVE_LOCKING must + be disabled. + config IRQSOFF_TRACER bool "Interrupts-off Latency Tracer" default n @@ -485,6 +524,19 @@ If in doubt, say N. +config CPU_FREQ_SWITCH_PROFILER + bool "CPU frequency switch time profiler" + select GENERIC_TRACER + help + This option enables the CPU frequency switch profiler. A file is + created in debugfs called "cpu_freq_switch_profile_enabled", which + defaults to zero. When a 1 is echoed into this file, profiling begins. + When a zero is echoed, profiling stops. A "cpu_freq_switch" file is + also created in the trace_stats directory; this file shows the + switches that have occurred and duration statistics. + + If in doubt, say N. + config FTRACE_MCOUNT_RECORD def_bool y depends on DYNAMIC_FTRACE diff -ruw linux-4.4.115/kernel/trace/Makefile linux-4.4.115-fbx/kernel/trace/Makefile --- linux-4.4.115/kernel/trace/Makefile 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/kernel/trace/Makefile 2019-01-22 16:16:28.727293713 +0100 @@ -37,9 +37,11 @@ obj-$(CONFIG_TRACING) += trace_printk.o obj-$(CONFIG_CONTEXT_SWITCH_TRACER) += trace_sched_switch.o obj-$(CONFIG_FUNCTION_TRACER) += trace_functions.o +obj-$(CONFIG_PREEMPTIRQ_EVENTS) += trace_irqsoff.o obj-$(CONFIG_IRQSOFF_TRACER) += trace_irqsoff.o obj-$(CONFIG_PREEMPT_TRACER) += trace_irqsoff.o obj-$(CONFIG_SCHED_TRACER) += trace_sched_wakeup.o +obj-$(CONFIG_CPU_FREQ_SWITCH_PROFILER) += trace_cpu_freq_switch.o obj-$(CONFIG_NOP_TRACER) += trace_nop.o obj-$(CONFIG_STACK_TRACER) += trace_stack.o obj-$(CONFIG_MMIOTRACE) += trace_mmiotrace.o @@ -68,7 +70,13 @@ endif obj-$(CONFIG_PROBE_EVENTS) += trace_probe.o obj-$(CONFIG_UPROBE_EVENT) += trace_uprobe.o +obj-$(CONFIG_GPU_TRACEPOINTS) += gpu-traces.o +obj-$(CONFIG_QCOM_RTB) += msm_rtb.o obj-$(CONFIG_TRACEPOINT_BENCHMARK) += trace_benchmark.o +obj-$(CONFIG_IPC_LOGGING) += ipc_logging.o +ifdef CONFIG_DEBUG_FS +obj-$(CONFIG_IPC_LOGGING) += ipc_logging_debug.o +endif libftrace-y := ftrace.o diff -ruw linux-4.4.115/kernel/trace/power-traces.c linux-4.4.115-fbx/kernel/trace/power-traces.c --- linux-4.4.115/kernel/trace/power-traces.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/kernel/trace/power-traces.c 2019-01-22 16:16:28.731293749 +0100 @@ -15,4 +15,3 @@ EXPORT_TRACEPOINT_SYMBOL_GPL(suspend_resume); EXPORT_TRACEPOINT_SYMBOL_GPL(cpu_idle); - diff -ruw linux-4.4.115/kernel/trace/trace.c linux-4.4.115-fbx/kernel/trace/trace.c --- linux-4.4.115/kernel/trace/trace.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/kernel/trace/trace.c 2019-10-29 09:26:25.653222848 +0100 @@ -41,6 +41,7 @@ #include #include #include +#include #include "trace.h" #include "trace_output.h" @@ -573,8 +574,11 @@ if (entry->buf[size - 1] != '\n') { entry->buf[size] = '\n'; entry->buf[size + 1] = '\0'; - } else + stm_log(OST_ENTITY_TRACE_PRINTK, entry->buf, size + 2); + } else { entry->buf[size] = '\0'; + stm_log(OST_ENTITY_TRACE_PRINTK, entry->buf, size + 1); + } __buffer_unlock_commit(buffer, event); ftrace_trace_stack(&global_trace, buffer, irq_flags, 4, pc, NULL); @@ -615,6 +619,7 @@ entry = ring_buffer_event_data(event); entry->ip = ip; entry->str = str; + stm_log(OST_ENTITY_TRACE_PRINTK, entry->str, strlen(entry->str)+1); __buffer_unlock_commit(buffer, event); ftrace_trace_stack(&global_trace, buffer, irq_flags, 4, pc, NULL); @@ -890,6 +895,7 @@ { trace_clock, "perf", 1 }, { ktime_get_mono_fast_ns, "mono", 1 }, { ktime_get_raw_fast_ns, "mono_raw", 1 }, + { ktime_get_boot_fast_ns, "boot", 1 }, ARCH_TRACE_CLOCKS }; @@ -1356,6 +1362,7 @@ struct saved_cmdlines_buffer { unsigned map_pid_to_cmdline[PID_MAX_DEFAULT+1]; unsigned *map_cmdline_to_pid; + unsigned *map_cmdline_to_tgid; unsigned cmdline_num; int cmdline_idx; char *saved_cmdlines; @@ -1389,12 +1396,23 @@ return -ENOMEM; } + s->map_cmdline_to_tgid = kmalloc_array(val, + sizeof(*s->map_cmdline_to_tgid), + GFP_KERNEL); + if (!s->map_cmdline_to_tgid) { + kfree(s->map_cmdline_to_pid); + kfree(s->saved_cmdlines); + return -ENOMEM; + } + s->cmdline_idx = 0; s->cmdline_num = val; memset(&s->map_pid_to_cmdline, NO_CMDLINE_MAP, sizeof(s->map_pid_to_cmdline)); memset(s->map_cmdline_to_pid, NO_CMDLINE_MAP, val * sizeof(*s->map_cmdline_to_pid)); + memset(s->map_cmdline_to_tgid, NO_CMDLINE_MAP, + val * sizeof(*s->map_cmdline_to_tgid)); return 0; } @@ -1560,14 +1578,17 @@ if (!tsk->pid || unlikely(tsk->pid > PID_MAX_DEFAULT)) return 0; + preempt_disable(); /* * It's not the end of the world if we don't get * the lock, but we also don't want to spin * nor do we want to disable interrupts, * so if we miss here, then better luck next time. */ - if (!arch_spin_trylock(&trace_cmdline_lock)) + if (!arch_spin_trylock(&trace_cmdline_lock)) { + preempt_enable(); return 0; + } idx = savedcmd->map_pid_to_cmdline[tsk->pid]; if (idx == NO_CMDLINE_MAP) { @@ -1590,8 +1611,9 @@ } set_cmdline(idx, tsk->comm); - + savedcmd->map_cmdline_to_tgid[idx] = tsk->tgid; arch_spin_unlock(&trace_cmdline_lock); + preempt_enable(); return 1; } @@ -1617,7 +1639,7 @@ map = savedcmd->map_pid_to_cmdline[pid]; if (map != NO_CMDLINE_MAP) - strcpy(comm, get_saved_cmdlines(map)); + strlcpy(comm, get_saved_cmdlines(map), TASK_COMM_LEN - 1); else strcpy(comm, "<...>"); } @@ -1633,6 +1655,35 @@ preempt_enable(); } +static int __find_tgid_locked(int pid) +{ + unsigned map; + int tgid; + + map = savedcmd->map_pid_to_cmdline[pid]; + if (map != NO_CMDLINE_MAP) + tgid = savedcmd->map_cmdline_to_tgid[map]; + else + tgid = -1; + + return tgid; +} + +int trace_find_tgid(int pid) +{ + int tgid; + + preempt_disable(); + arch_spin_lock(&trace_cmdline_lock); + + tgid = __find_tgid_locked(pid); + + arch_spin_unlock(&trace_cmdline_lock); + preempt_enable(); + + return tgid; +} + void tracing_record_cmdline(struct task_struct *tsk) { if (atomic_read(&trace_record_cmdline_disabled) || !tracing_is_on()) @@ -2220,6 +2271,7 @@ memcpy(&entry->buf, tbuffer, len + 1); if (!call_filter_check_discard(call, entry, buffer, event)) { + stm_log(OST_ENTITY_TRACE_PRINTK, entry->buf, len + 1); __buffer_unlock_commit(buffer, event); ftrace_trace_stack(&global_trace, buffer, flags, 6, pc, NULL); } @@ -2583,6 +2635,13 @@ "# | | | | |\n"); } +static void print_func_help_header_tgid(struct trace_buffer *buf, struct seq_file *m) +{ + print_event_info(buf, m); + seq_puts(m, "# TASK-PID TGID CPU# TIMESTAMP FUNCTION\n"); + seq_puts(m, "# | | | | | |\n"); +} + static void print_func_help_header_irq(struct trace_buffer *buf, struct seq_file *m) { print_event_info(buf, m); @@ -2595,6 +2654,18 @@ "# | | | |||| | |\n"); } +static void print_func_help_header_irq_tgid(struct trace_buffer *buf, struct seq_file *m) +{ + print_event_info(buf, m); + seq_puts(m, "# _-----=> irqs-off\n"); + seq_puts(m, "# / _----=> need-resched\n"); + seq_puts(m, "# | / _---=> hardirq/softirq\n"); + seq_puts(m, "# || / _--=> preempt-depth\n"); + seq_puts(m, "# ||| / delay\n"); + seq_puts(m, "# TASK-PID TGID CPU# |||| TIMESTAMP FUNCTION\n"); + seq_puts(m, "# | | | | |||| | |\n"); +} + void print_trace_header(struct seq_file *m, struct trace_iterator *iter) { @@ -2907,8 +2978,14 @@ } else { if (!(trace_flags & TRACE_ITER_VERBOSE)) { if (trace_flags & TRACE_ITER_IRQ_INFO) + if (trace_flags & TRACE_ITER_TGID) + print_func_help_header_irq_tgid(iter->trace_buffer, m); + else print_func_help_header_irq(iter->trace_buffer, m); else + if (trace_flags & TRACE_ITER_TGID) + print_func_help_header_tgid(iter->trace_buffer, m); + else print_func_help_header(iter->trace_buffer, m); } } @@ -3912,10 +3989,15 @@ { char buf[64]; int r; + unsigned int n; + preempt_disable(); arch_spin_lock(&trace_cmdline_lock); - r = scnprintf(buf, sizeof(buf), "%u\n", savedcmd->cmdline_num); + n = savedcmd->cmdline_num; arch_spin_unlock(&trace_cmdline_lock); + preempt_enable(); + + r = scnprintf(buf, sizeof(buf), "%u\n", n); return simple_read_from_buffer(ubuf, cnt, ppos, buf, r); } @@ -3924,6 +4006,7 @@ { kfree(s->saved_cmdlines); kfree(s->map_cmdline_to_pid); + kfree(s->map_cmdline_to_tgid); kfree(s); } @@ -3940,10 +4023,12 @@ return -ENOMEM; } + preempt_disable(); arch_spin_lock(&trace_cmdline_lock); savedcmd_temp = savedcmd; savedcmd = s; arch_spin_unlock(&trace_cmdline_lock); + preempt_enable(); free_saved_cmdlines_buffer(savedcmd_temp); return 0; @@ -4156,6 +4241,78 @@ } static ssize_t +tracing_saved_tgids_read(struct file *file, char __user *ubuf, + size_t cnt, loff_t *ppos) +{ + char *file_buf; + char *buf; + int len = 0; + int i; + int *pids; + int n = 0; + + preempt_disable(); + arch_spin_lock(&trace_cmdline_lock); + + pids = kmalloc_array(savedcmd->cmdline_num, 2*sizeof(int), GFP_KERNEL); + if (!pids) { + arch_spin_unlock(&trace_cmdline_lock); + preempt_enable(); + return -ENOMEM; + } + + for (i = 0; i < savedcmd->cmdline_num; i++) { + int pid; + + pid = savedcmd->map_cmdline_to_pid[i]; + if (pid == -1 || pid == NO_CMDLINE_MAP) + continue; + + pids[n] = pid; + pids[n+1] = __find_tgid_locked(pid); + n += 2; + } + arch_spin_unlock(&trace_cmdline_lock); + preempt_enable(); + + if (n == 0) { + kfree(pids); + return 0; + } + + /* enough to hold max pair of pids + space, lr and nul */ + len = n * 12; + file_buf = kmalloc(len, GFP_KERNEL); + if (!file_buf) { + kfree(pids); + return -ENOMEM; + } + + buf = file_buf; + for (i = 0; i < n && len > 0; i += 2) { + int r; + + r = snprintf(buf, len, "%d %d\n", pids[i], pids[i+1]); + buf += r; + len -= r; + } + + len = simple_read_from_buffer(ubuf, cnt, ppos, + file_buf, buf - file_buf); + + kfree(file_buf); + kfree(pids); + + return len; +} + +static const struct file_operations tracing_saved_tgids_fops = { + .open = tracing_open_generic, + .read = tracing_saved_tgids_read, + .llseek = generic_file_llseek, +}; + +static ssize_t tracing_set_trace_read(struct file *filp, char __user *ubuf, size_t cnt, loff_t *ppos) { @@ -5175,8 +5332,11 @@ if (entry->buf[cnt - 1] != '\n') { entry->buf[cnt] = '\n'; entry->buf[cnt + 1] = '\0'; - } else + stm_log(OST_ENTITY_TRACE_MARKER, entry->buf, cnt + 2); + } else { entry->buf[cnt] = '\0'; + stm_log(OST_ENTITY_TRACE_MARKER, entry->buf, cnt + 1); + } __buffer_unlock_commit(buffer, event); @@ -6783,6 +6943,9 @@ trace_create_file("trace_marker", 0220, d_tracer, tr, &tracing_mark_fops); + trace_create_file("saved_tgids", 0444, d_tracer, + tr, &tracing_saved_tgids_fops); + trace_create_file("trace_clock", 0644, d_tracer, tr, &trace_clock_fops); diff -ruw linux-4.4.115/kernel/trace/trace_event_perf.c linux-4.4.115-fbx/kernel/trace/trace_event_perf.c --- linux-4.4.115/kernel/trace/trace_event_perf.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/kernel/trace/trace_event_perf.c 2019-01-22 16:16:28.735293785 +0100 @@ -256,6 +256,7 @@ void perf_trace_del(struct perf_event *p_event, int flags) { struct trace_event_call *tp_event = p_event->tp_event; + if (!hlist_unhashed(&p_event->hlist_entry)) hlist_del_rcu(&p_event->hlist_entry); tp_event->class->reg(tp_event, TRACE_REG_PERF_DEL, p_event); } diff -ruw linux-4.4.115/kernel/trace/trace_events.c linux-4.4.115-fbx/kernel/trace/trace_events.c --- linux-4.4.115/kernel/trace/trace_events.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/kernel/trace/trace_events.c 2019-10-29 09:26:25.657222887 +0100 @@ -287,14 +287,15 @@ spin_unlock_irqrestore(&tracepoint_iter_lock, flags); } -void trace_event_buffer_commit(struct trace_event_buffer *fbuffer) +void trace_event_buffer_commit(struct trace_event_buffer *fbuffer, + unsigned long len) { if (tracepoint_printk) output_printk(fbuffer); event_trigger_unlock_commit(fbuffer->trace_file, fbuffer->buffer, fbuffer->event, fbuffer->entry, - fbuffer->flags, fbuffer->pc); + fbuffer->flags, fbuffer->pc, len); } EXPORT_SYMBOL_GPL(trace_event_buffer_commit); diff -ruw linux-4.4.115/kernel/trace/trace.h linux-4.4.115-fbx/kernel/trace/trace.h --- linux-4.4.115/kernel/trace/trace.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/kernel/trace/trace.h 2019-10-29 09:26:25.653222848 +0100 @@ -656,6 +656,7 @@ extern cycle_t ftrace_now(int cpu); extern void trace_find_cmdline(int pid, char comm[]); +extern int trace_find_tgid(int pid); #ifdef CONFIG_DYNAMIC_FTRACE extern unsigned long ftrace_update_tot_cnt; @@ -970,7 +971,8 @@ FUNCTION_FLAGS \ FGRAPH_FLAGS \ STACK_FLAGS \ - BRANCH_FLAGS + BRANCH_FLAGS \ + C(TGID, "print-tgid"), /* * By defining C, we can make TRACE_FLAGS a list of bit names diff -ruw linux-4.4.115/kernel/trace/trace_output.c linux-4.4.115-fbx/kernel/trace/trace_output.c --- linux-4.4.115/kernel/trace/trace_output.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/kernel/trace/trace_output.c 2019-01-22 16:16:28.739293822 +0100 @@ -526,11 +526,21 @@ unsigned long long t; unsigned long secs, usec_rem; char comm[TASK_COMM_LEN]; + int tgid; trace_find_cmdline(entry->pid, comm); - trace_seq_printf(s, "%16s-%-5d [%03d] ", - comm, entry->pid, iter->cpu); + trace_seq_printf(s, "%16s-%-5d ", comm, entry->pid); + + if (tr->trace_flags & TRACE_ITER_TGID) { + tgid = trace_find_tgid(entry->pid); + if (tgid < 0) + trace_seq_puts(s, "(-----) "); + else + trace_seq_printf(s, "(%5d) ", tgid); + } + + trace_seq_printf(s, "[%03d] ", iter->cpu); if (tr->trace_flags & TRACE_ITER_IRQ_INFO) trace_print_lat_fmt(s, entry); @@ -845,6 +855,174 @@ .funcs = &trace_fn_funcs, }; +/* TRACE_GRAPH_ENT */ +static enum print_line_t trace_graph_ent_trace(struct trace_iterator *iter, int flags, + struct trace_event *event) +{ + struct trace_seq *s = &iter->seq; + struct ftrace_graph_ent_entry *field; + + trace_assign_type(field, iter->ent); + + trace_seq_puts(s, "graph_ent: func="); + if (trace_seq_has_overflowed(s)) + return TRACE_TYPE_PARTIAL_LINE; + + if (!seq_print_ip_sym(s, field->graph_ent.func, flags)) + return TRACE_TYPE_PARTIAL_LINE; + + trace_seq_puts(s, "\n"); + if (trace_seq_has_overflowed(s)) + return TRACE_TYPE_PARTIAL_LINE; + + return TRACE_TYPE_HANDLED; +} + +static enum print_line_t trace_graph_ent_raw(struct trace_iterator *iter, int flags, + struct trace_event *event) +{ + struct ftrace_graph_ent_entry *field; + + trace_assign_type(field, iter->ent); + + trace_seq_printf(&iter->seq, "%lx %d\n", + field->graph_ent.func, + field->graph_ent.depth); + if (trace_seq_has_overflowed(&iter->seq)) + return TRACE_TYPE_PARTIAL_LINE; + + return TRACE_TYPE_HANDLED; +} + +static enum print_line_t trace_graph_ent_hex(struct trace_iterator *iter, int flags, + struct trace_event *event) +{ + struct ftrace_graph_ent_entry *field; + struct trace_seq *s = &iter->seq; + + trace_assign_type(field, iter->ent); + + SEQ_PUT_HEX_FIELD(s, field->graph_ent.func); + SEQ_PUT_HEX_FIELD(s, field->graph_ent.depth); + + return TRACE_TYPE_HANDLED; +} + +static enum print_line_t trace_graph_ent_bin(struct trace_iterator *iter, int flags, + struct trace_event *event) +{ + struct ftrace_graph_ent_entry *field; + struct trace_seq *s = &iter->seq; + + trace_assign_type(field, iter->ent); + + SEQ_PUT_FIELD(s, field->graph_ent.func); + SEQ_PUT_FIELD(s, field->graph_ent.depth); + + return TRACE_TYPE_HANDLED; +} + +static struct trace_event_functions trace_graph_ent_funcs = { + .trace = trace_graph_ent_trace, + .raw = trace_graph_ent_raw, + .hex = trace_graph_ent_hex, + .binary = trace_graph_ent_bin, +}; + +static struct trace_event trace_graph_ent_event = { + .type = TRACE_GRAPH_ENT, + .funcs = &trace_graph_ent_funcs, +}; + +/* TRACE_GRAPH_RET */ +static enum print_line_t trace_graph_ret_trace(struct trace_iterator *iter, int flags, + struct trace_event *event) +{ + struct trace_seq *s = &iter->seq; + struct trace_entry *entry = iter->ent; + struct ftrace_graph_ret_entry *field; + + trace_assign_type(field, entry); + + trace_seq_puts(s, "graph_ret: func="); + if (trace_seq_has_overflowed(s)) + return TRACE_TYPE_PARTIAL_LINE; + + if (!seq_print_ip_sym(s, field->ret.func, flags)) + return TRACE_TYPE_PARTIAL_LINE; + + trace_seq_puts(s, "\n"); + if (trace_seq_has_overflowed(s)) + return TRACE_TYPE_PARTIAL_LINE; + + return TRACE_TYPE_HANDLED; +} + +static enum print_line_t trace_graph_ret_raw(struct trace_iterator *iter, int flags, + struct trace_event *event) +{ + struct ftrace_graph_ret_entry *field; + + trace_assign_type(field, iter->ent); + + trace_seq_printf(&iter->seq, "%lx %lld %lld %ld %d\n", + field->ret.func, + field->ret.calltime, + field->ret.rettime, + field->ret.overrun, + field->ret.depth); + if (trace_seq_has_overflowed(&iter->seq)) + return TRACE_TYPE_PARTIAL_LINE; + + return TRACE_TYPE_HANDLED; +} + +static enum print_line_t trace_graph_ret_hex(struct trace_iterator *iter, int flags, + struct trace_event *event) +{ + struct ftrace_graph_ret_entry *field; + struct trace_seq *s = &iter->seq; + + trace_assign_type(field, iter->ent); + + SEQ_PUT_HEX_FIELD(s, field->ret.func); + SEQ_PUT_HEX_FIELD(s, field->ret.calltime); + SEQ_PUT_HEX_FIELD(s, field->ret.rettime); + SEQ_PUT_HEX_FIELD(s, field->ret.overrun); + SEQ_PUT_HEX_FIELD(s, field->ret.depth); + + return TRACE_TYPE_HANDLED; +} + +static enum print_line_t trace_graph_ret_bin(struct trace_iterator *iter, int flags, + struct trace_event *event) +{ + struct ftrace_graph_ret_entry *field; + struct trace_seq *s = &iter->seq; + + trace_assign_type(field, iter->ent); + + SEQ_PUT_FIELD(s, field->ret.func); + SEQ_PUT_FIELD(s, field->ret.calltime); + SEQ_PUT_FIELD(s, field->ret.rettime); + SEQ_PUT_FIELD(s, field->ret.overrun); + SEQ_PUT_FIELD(s, field->ret.depth); + + return TRACE_TYPE_HANDLED; +} + +static struct trace_event_functions trace_graph_ret_funcs = { + .trace = trace_graph_ret_trace, + .raw = trace_graph_ret_raw, + .hex = trace_graph_ret_hex, + .binary = trace_graph_ret_bin, +}; + +static struct trace_event trace_graph_ret_event = { + .type = TRACE_GRAPH_RET, + .funcs = &trace_graph_ret_funcs, +}; + /* TRACE_CTX an TRACE_WAKE */ static enum print_line_t trace_ctxwake_print(struct trace_iterator *iter, char *delim) @@ -1222,6 +1400,8 @@ static struct trace_event *events[] __initdata = { &trace_fn_event, + &trace_graph_ent_event, + &trace_graph_ret_event, &trace_ctx_event, &trace_wake_event, &trace_stack_event, diff -ruw linux-4.4.115/kernel/trace/trace_printk.c linux-4.4.115-fbx/kernel/trace/trace_printk.c --- linux-4.4.115/kernel/trace/trace_printk.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/kernel/trace/trace_printk.c 2019-01-22 16:16:28.739293822 +0100 @@ -304,7 +304,7 @@ if (!*fmt) return 0; - seq_printf(m, "0x%lx : \"", *(unsigned long *)fmt); + seq_printf(m, "0x%lx : \"", 0L); /* * Tabs and new lines need to be converted. diff -ruw linux-4.4.115/kernel/watchdog.c linux-4.4.115-fbx/kernel/watchdog.c --- linux-4.4.115/kernel/watchdog.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/kernel/watchdog.c 2019-01-22 16:16:28.747293894 +0100 @@ -13,6 +13,7 @@ #include #include +#include #include #include #include @@ -20,6 +21,7 @@ #include #include #include +#include #include #include @@ -94,6 +96,7 @@ static DEFINE_PER_CPU(unsigned long, watchdog_touch_ts); static DEFINE_PER_CPU(struct task_struct *, softlockup_watchdog); static DEFINE_PER_CPU(struct hrtimer, watchdog_hrtimer); +static DEFINE_PER_CPU(unsigned int, watchdog_en); static DEFINE_PER_CPU(bool, softlockup_touch_sync); static DEFINE_PER_CPU(bool, soft_watchdog_warn); static DEFINE_PER_CPU(unsigned long, hrtimer_interrupts); @@ -103,6 +106,11 @@ static DEFINE_PER_CPU(bool, hard_watchdog_warn); static DEFINE_PER_CPU(bool, watchdog_nmi_touch); static DEFINE_PER_CPU(unsigned long, hrtimer_interrupts_saved); +#endif +#ifdef CONFIG_HARDLOCKUP_DETECTOR_OTHER_CPU +static cpumask_t __read_mostly watchdog_cpus; +#endif +#ifdef CONFIG_HARDLOCKUP_DETECTOR_NMI static DEFINE_PER_CPU(struct perf_event *, watchdog_ev); #endif static unsigned long soft_lockup_nmi_warn; @@ -114,7 +122,7 @@ #ifdef CONFIG_HARDLOCKUP_DETECTOR unsigned int __read_mostly hardlockup_panic = CONFIG_BOOTPARAM_HARDLOCKUP_PANIC_VALUE; -static unsigned long hardlockup_allcpu_dumped; +static unsigned long __maybe_unused hardlockup_allcpu_dumped; /* * We may not want to enable hard lockup detection by default in all cases, * for example when running the kernel as a guest on a hypervisor. In these @@ -225,7 +233,15 @@ __this_cpu_write(watchdog_touch_ts, get_timestamp()); } -void touch_softlockup_watchdog(void) +/** + * touch_softlockup_watchdog_sched - touch watchdog on scheduler stalls + * + * Call when the scheduler may have stalled for legitimate reasons + * preventing the watchdog task from executing - e.g. the scheduler + * entering idle state. This should only be used for scheduler events. + * Use touch_softlockup_watchdog() for everything else. + */ +void touch_softlockup_watchdog_sched(void) { /* * Preemption can be enabled. It doesn't matter which CPU's timestamp @@ -233,6 +249,12 @@ */ raw_cpu_write(watchdog_touch_ts, 0); } + +void touch_softlockup_watchdog(void) +{ + touch_softlockup_watchdog_sched(); + wq_watchdog_touch(raw_smp_processor_id()); +} EXPORT_SYMBOL(touch_softlockup_watchdog); void touch_all_softlockup_watchdogs(void) @@ -246,6 +268,7 @@ */ for_each_watchdog_cpu(cpu) per_cpu(watchdog_touch_ts, cpu) = 0; + wq_watchdog_touch(-1); } #ifdef CONFIG_HARDLOCKUP_DETECTOR @@ -271,7 +294,7 @@ __this_cpu_write(watchdog_touch_ts, 0); } -#ifdef CONFIG_HARDLOCKUP_DETECTOR +#ifdef CONFIG_HARDLOCKUP_DETECTOR_NMI /* watchdog detector functions */ static bool is_hardlockup(void) { @@ -285,6 +308,76 @@ } #endif +#ifdef CONFIG_HARDLOCKUP_DETECTOR_OTHER_CPU +static unsigned int watchdog_next_cpu(unsigned int cpu) +{ + cpumask_t cpus = watchdog_cpus; + unsigned int next_cpu; + + next_cpu = cpumask_next(cpu, &cpus); + if (next_cpu >= nr_cpu_ids) + next_cpu = cpumask_first(&cpus); + + if (next_cpu == cpu) + return nr_cpu_ids; + + return next_cpu; +} + +static int is_hardlockup_other_cpu(unsigned int cpu) +{ + unsigned long hrint = per_cpu(hrtimer_interrupts, cpu); + + if (per_cpu(hrtimer_interrupts_saved, cpu) == hrint) + return 1; + + per_cpu(hrtimer_interrupts_saved, cpu) = hrint; + return 0; +} + +static void watchdog_check_hardlockup_other_cpu(void) +{ + unsigned int next_cpu; + + /* + * Test for hardlockups every 3 samples. The sample period is + * watchdog_thresh * 2 / 5, so 3 samples gets us back to slightly over + * watchdog_thresh (over by 20%). + */ + if (__this_cpu_read(hrtimer_interrupts) % 3 != 0) + return; + + /* check for a hardlockup on the next cpu */ + next_cpu = watchdog_next_cpu(smp_processor_id()); + if (next_cpu >= nr_cpu_ids) + return; + + smp_rmb(); + + if (per_cpu(watchdog_nmi_touch, next_cpu) == true) { + per_cpu(watchdog_nmi_touch, next_cpu) = false; + return; + } + + if (is_hardlockup_other_cpu(next_cpu)) { + /* only warn once */ + if (per_cpu(hard_watchdog_warn, next_cpu) == true) + return; + + if (hardlockup_panic) + panic("Watchdog detected hard LOCKUP on cpu %u", next_cpu); + else + WARN(1, "Watchdog detected hard LOCKUP on cpu %u", next_cpu); + + per_cpu(hard_watchdog_warn, next_cpu) = true; + } else { + per_cpu(hard_watchdog_warn, next_cpu) = false; + } +} +#else +static inline void watchdog_check_hardlockup_other_cpu(void) { return; } +#endif + static int is_softlockup(unsigned long touch_ts) { unsigned long now = get_timestamp(); @@ -297,7 +390,7 @@ return 0; } -#ifdef CONFIG_HARDLOCKUP_DETECTOR +#ifdef CONFIG_HARDLOCKUP_DETECTOR_NMI static struct perf_event_attr wd_hw_attr = { .type = PERF_TYPE_HARDWARE, @@ -359,7 +452,7 @@ __this_cpu_write(hard_watchdog_warn, false); return; } -#endif /* CONFIG_HARDLOCKUP_DETECTOR */ +#endif /* CONFIG_HARDLOCKUP_DETECTOR_NMI */ static void watchdog_interrupt_count(void) { @@ -383,6 +476,9 @@ /* kick the hardlockup detector */ watchdog_interrupt_count(); + /* test for hardlockups on the next cpu */ + watchdog_check_hardlockup_other_cpu(); + /* kick the softlockup detector */ wake_up_process(__this_cpu_read(softlockup_watchdog)); @@ -489,9 +585,13 @@ sched_setscheduler(current, policy, ¶m); } -static void watchdog_enable(unsigned int cpu) +void watchdog_enable(unsigned int cpu) { struct hrtimer *hrtimer = raw_cpu_ptr(&watchdog_hrtimer); + unsigned int *enabled = raw_cpu_ptr(&watchdog_en); + + if (*enabled) + return; /* kick off the timer for the hardlockup detector */ hrtimer_init(hrtimer, CLOCK_MONOTONIC, HRTIMER_MODE_REL); @@ -507,16 +607,40 @@ /* initialize timestamp */ watchdog_set_prio(SCHED_FIFO, MAX_RT_PRIO - 1); __touch_watchdog(); + + /* + * Need to ensure above operations are observed by other CPUs before + * indicating that timer is enabled. This is to synchronize core + * isolation and hotplug. Core isolation will wait for this flag to be + * set. + */ + mb(); + *enabled = 1; } -static void watchdog_disable(unsigned int cpu) +void watchdog_disable(unsigned int cpu) { struct hrtimer *hrtimer = raw_cpu_ptr(&watchdog_hrtimer); + unsigned int *enabled = raw_cpu_ptr(&watchdog_en); + + if (!*enabled) + return; watchdog_set_prio(SCHED_NORMAL, 0); hrtimer_cancel(hrtimer); /* disable the perf event */ watchdog_nmi_disable(cpu); + + /* + * No need for barrier here since disabling the watchdog is + * synchronized with hotplug lock + */ + *enabled = 0; +} + +bool watchdog_configured(unsigned int cpu) +{ + return *per_cpu_ptr(&watchdog_en, cpu); } static void watchdog_cleanup(unsigned int cpu, bool online) @@ -560,7 +684,7 @@ watchdog_nmi_disable(cpu); } -#ifdef CONFIG_HARDLOCKUP_DETECTOR +#ifdef CONFIG_HARDLOCKUP_DETECTOR_NMI /* * People like the simple clean cpu node info on boot. * Reduce the watchdog noise by only printing messages @@ -659,9 +783,44 @@ } #else +#ifdef CONFIG_HARDLOCKUP_DETECTOR_OTHER_CPU +static int watchdog_nmi_enable(unsigned int cpu) +{ + /* + * The new cpu will be marked online before the first hrtimer interrupt + * runs on it. If another cpu tests for a hardlockup on the new cpu + * before it has run its first hrtimer, it will get a false positive. + * Touch the watchdog on the new cpu to delay the first check for at + * least 3 sampling periods to guarantee one hrtimer has run on the new + * cpu. + */ + per_cpu(watchdog_nmi_touch, cpu) = true; + smp_wmb(); + cpumask_set_cpu(cpu, &watchdog_cpus); + return 0; +} + +static void watchdog_nmi_disable(unsigned int cpu) +{ + unsigned int next_cpu = watchdog_next_cpu(cpu); + + /* + * Offlining this cpu will cause the cpu before this one to start + * checking the one after this one. If this cpu just finished checking + * the next cpu and updating hrtimer_interrupts_saved, and then the + * previous cpu checks it within one sample period, it will trigger a + * false positive. Touch the watchdog on the next cpu to prevent it. + */ + if (next_cpu < nr_cpu_ids) + per_cpu(watchdog_nmi_touch, next_cpu) = true; + smp_wmb(); + cpumask_clear_cpu(cpu, &watchdog_cpus); +} +#else static int watchdog_nmi_enable(unsigned int cpu) { return 0; } static void watchdog_nmi_disable(unsigned int cpu) { return; } -#endif /* CONFIG_HARDLOCKUP_DETECTOR */ +#endif /* CONFIG_HARDLOCKUP_DETECTOR_OTHER_CPU */ +#endif /* CONFIG_HARDLOCKUP_DETECTOR_NMI */ static struct smp_hotplug_thread watchdog_threads = { .store = &softlockup_watchdog, diff -ruw linux-4.4.115/kernel/workqueue.c linux-4.4.115-fbx/kernel/workqueue.c --- linux-4.4.115/kernel/workqueue.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/kernel/workqueue.c 2019-10-29 09:26:25.665222966 +0100 @@ -48,6 +48,8 @@ #include #include #include +#include +#include #include "workqueue_internal.h" @@ -149,6 +151,8 @@ int id; /* I: pool ID */ unsigned int flags; /* X: flags */ + unsigned long watchdog_ts; /* L: watchdog timestamp */ + struct list_head worklist; /* L: list of pending works */ int nr_workers; /* L: total number of workers */ @@ -1123,6 +1127,8 @@ struct pool_workqueue *pwq = get_work_pwq(work); trace_workqueue_activate_work(work); + if (list_empty(&pwq->pool->worklist)) + pwq->pool->watchdog_ts = jiffies; move_linked_works(work, &pwq->pool->worklist, NULL); __clear_bit(WORK_STRUCT_DELAYED_BIT, work_data_bits(work)); pwq->nr_active++; @@ -1281,6 +1287,12 @@ if (work_is_canceling(work)) return -ENOENT; cpu_relax(); + /* + * The queueing is in progress in another context. If we keep + * taking the pool->lock in a busy loop, the other context may + * never get the lock. Give 1 usec delay to avoid this contention. + */ + udelay(1); return -EAGAIN; } @@ -1425,6 +1437,8 @@ trace_workqueue_activate_work(work); pwq->nr_active++; worklist = &pwq->pool->worklist; + if (list_empty(worklist)) + pwq->pool->watchdog_ts = jiffies; } else { work_flags |= WORK_STRUCT_DELAYED; worklist = &pwq->delayed_works; @@ -1496,8 +1510,6 @@ return; } - timer_stats_timer_set_start_info(&dwork->timer); - dwork->wq = wq; dwork->cpu = cpu; timer->expires = jiffies + delay; @@ -2076,6 +2088,7 @@ current->comm, preempt_count(), task_pid_nr(current), worker->current_func); debug_show_held_locks(current); + BUG_ON(PANIC_CORRUPTION); dump_stack(); } @@ -2191,6 +2204,8 @@ list_first_entry(&pool->worklist, struct work_struct, entry); + pool->watchdog_ts = jiffies; + if (likely(!(*work_data_bits(work) & WORK_STRUCT_LINKED))) { /* optimization path, not strictly necessary */ process_one_work(worker, work); @@ -2274,6 +2289,7 @@ struct pool_workqueue, mayday_node); struct worker_pool *pool = pwq->pool; struct work_struct *work, *n; + bool first = true; __set_current_state(TASK_RUNNING); list_del_init(&pwq->mayday_node); @@ -2290,9 +2306,14 @@ * process'em. */ WARN_ON_ONCE(!list_empty(scheduled)); - list_for_each_entry_safe(work, n, &pool->worklist, entry) - if (get_work_pwq(work) == pwq) + list_for_each_entry_safe(work, n, &pool->worklist, entry) { + if (get_work_pwq(work) == pwq) { + if (first) + pool->watchdog_ts = jiffies; move_linked_works(work, scheduled, &n); + } + first = false; + } if (!list_empty(scheduled)) { process_scheduled_works(rescuer); @@ -3103,6 +3124,7 @@ pool->cpu = -1; pool->node = NUMA_NO_NODE; pool->flags |= POOL_DISASSOCIATED; + pool->watchdog_ts = jiffies; INIT_LIST_HEAD(&pool->worklist); INIT_LIST_HEAD(&pool->idle_list); hash_init(pool->busy_hash); @@ -4356,7 +4378,9 @@ pr_info("pool %d:", pool->id); pr_cont_pool_info(pool); - pr_cont(" workers=%d", pool->nr_workers); + pr_cont(" hung=%us workers=%d", + jiffies_to_msecs(jiffies - pool->watchdog_ts) / 1000, + pool->nr_workers); if (pool->manager) pr_cont(" manager: %d", task_pid_nr(pool->manager->task)); @@ -5226,6 +5250,154 @@ static void workqueue_sysfs_unregister(struct workqueue_struct *wq) { } #endif /* CONFIG_SYSFS */ +/* + * Workqueue watchdog. + * + * Stall may be caused by various bugs - missing WQ_MEM_RECLAIM, illegal + * flush dependency, a concurrency managed work item which stays RUNNING + * indefinitely. Workqueue stalls can be very difficult to debug as the + * usual warning mechanisms don't trigger and internal workqueue state is + * largely opaque. + * + * Workqueue watchdog monitors all worker pools periodically and dumps + * state if some pools failed to make forward progress for a while where + * forward progress is defined as the first item on ->worklist changing. + * + * This mechanism is controlled through the kernel parameter + * "workqueue.watchdog_thresh" which can be updated at runtime through the + * corresponding sysfs parameter file. + */ +#ifdef CONFIG_WQ_WATCHDOG + +static void wq_watchdog_timer_fn(unsigned long data); + +static unsigned long wq_watchdog_thresh = 30; +static struct timer_list wq_watchdog_timer = + TIMER_DEFERRED_INITIALIZER(wq_watchdog_timer_fn, 0, 0); + +static unsigned long wq_watchdog_touched = INITIAL_JIFFIES; +static DEFINE_PER_CPU(unsigned long, wq_watchdog_touched_cpu) = INITIAL_JIFFIES; + +static void wq_watchdog_reset_touched(void) +{ + int cpu; + + wq_watchdog_touched = jiffies; + for_each_possible_cpu(cpu) + per_cpu(wq_watchdog_touched_cpu, cpu) = jiffies; +} + +static void wq_watchdog_timer_fn(unsigned long data) +{ + unsigned long thresh = READ_ONCE(wq_watchdog_thresh) * HZ; + bool lockup_detected = false; + struct worker_pool *pool; + int pi; + + if (!thresh) + return; + + rcu_read_lock(); + + for_each_pool(pool, pi) { + unsigned long pool_ts, touched, ts; + + if (list_empty(&pool->worklist)) + continue; + + /* get the latest of pool and touched timestamps */ + pool_ts = READ_ONCE(pool->watchdog_ts); + touched = READ_ONCE(wq_watchdog_touched); + + if (time_after(pool_ts, touched)) + ts = pool_ts; + else + ts = touched; + + if (pool->cpu >= 0) { + unsigned long cpu_touched = + READ_ONCE(per_cpu(wq_watchdog_touched_cpu, + pool->cpu)); + if (time_after(cpu_touched, ts)) + ts = cpu_touched; + } + + /* did we stall? */ + if (time_after(jiffies, ts + thresh)) { + lockup_detected = true; + pr_emerg("BUG: workqueue lockup - pool"); + pr_cont_pool_info(pool); + pr_cont(" stuck for %us!\n", + jiffies_to_msecs(jiffies - pool_ts) / 1000); + } + } + + rcu_read_unlock(); + + if (lockup_detected) + show_workqueue_state(); + + wq_watchdog_reset_touched(); + mod_timer(&wq_watchdog_timer, jiffies + thresh); +} + +void wq_watchdog_touch(int cpu) +{ + if (cpu >= 0) + per_cpu(wq_watchdog_touched_cpu, cpu) = jiffies; + else + wq_watchdog_touched = jiffies; +} + +static void wq_watchdog_set_thresh(unsigned long thresh) +{ + wq_watchdog_thresh = 0; + del_timer_sync(&wq_watchdog_timer); + + if (thresh) { + wq_watchdog_thresh = thresh; + wq_watchdog_reset_touched(); + mod_timer(&wq_watchdog_timer, jiffies + thresh * HZ); + } +} + +static int wq_watchdog_param_set_thresh(const char *val, + const struct kernel_param *kp) +{ + unsigned long thresh; + int ret; + + ret = kstrtoul(val, 0, &thresh); + if (ret) + return ret; + + if (system_wq) + wq_watchdog_set_thresh(thresh); + else + wq_watchdog_thresh = thresh; + + return 0; +} + +static const struct kernel_param_ops wq_watchdog_thresh_ops = { + .set = wq_watchdog_param_set_thresh, + .get = param_get_ulong, +}; + +module_param_cb(watchdog_thresh, &wq_watchdog_thresh_ops, &wq_watchdog_thresh, + 0644); + +static void wq_watchdog_init(void) +{ + wq_watchdog_set_thresh(wq_watchdog_thresh); +} + +#else /* CONFIG_WQ_WATCHDOG */ + +static inline void wq_watchdog_init(void) { } + +#endif /* CONFIG_WQ_WATCHDOG */ + static void __init wq_numa_init(void) { cpumask_var_t *tbl; @@ -5349,6 +5521,9 @@ !system_unbound_wq || !system_freezable_wq || !system_power_efficient_wq || !system_freezable_power_efficient_wq); + + wq_watchdog_init(); + return 0; } early_initcall(init_workqueues); diff -ruw linux-4.4.115/lib/extable.c linux-4.4.115-fbx/lib/extable.c --- linux-4.4.115/lib/extable.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/lib/extable.c 2019-01-22 16:16:28.759294003 +0100 @@ -14,7 +14,37 @@ #include #include +#ifndef ARCH_HAS_RELATIVE_EXTABLE +#define ex_to_insn(x) ((x)->insn) +#else +static inline unsigned long ex_to_insn(const struct exception_table_entry *x) +{ + return (unsigned long)&x->insn + x->insn; +} +#endif + #ifndef ARCH_HAS_SORT_EXTABLE +#ifndef ARCH_HAS_RELATIVE_EXTABLE +#define swap_ex NULL +#else +static void swap_ex(void *a, void *b, int size) +{ + struct exception_table_entry *x = a, *y = b, tmp; + int delta = b - a; + + tmp = *x; + x->insn = y->insn + delta; + y->insn = tmp.insn - delta; + +#ifdef swap_ex_entry_fixup + swap_ex_entry_fixup(x, y, tmp, delta); +#else + x->fixup = y->fixup + delta; + y->fixup = tmp.fixup - delta; +#endif +} +#endif /* ARCH_HAS_RELATIVE_EXTABLE */ + /* * The exception table needs to be sorted so that the binary * search that we use to find entries in it works properly. @@ -26,9 +56,9 @@ const struct exception_table_entry *x = a, *y = b; /* avoid overflow */ - if (x->insn > y->insn) + if (ex_to_insn(x) > ex_to_insn(y)) return 1; - if (x->insn < y->insn) + if (ex_to_insn(x) < ex_to_insn(y)) return -1; return 0; } @@ -37,7 +67,7 @@ struct exception_table_entry *finish) { sort(start, finish - start, sizeof(struct exception_table_entry), - cmp_ex, NULL); + cmp_ex, swap_ex); } #ifdef CONFIG_MODULES @@ -48,13 +78,15 @@ void trim_init_extable(struct module *m) { /*trim the beginning*/ - while (m->num_exentries && within_module_init(m->extable[0].insn, m)) { + while (m->num_exentries && + within_module_init(ex_to_insn(&m->extable[0]), m)) { m->extable++; m->num_exentries--; } /*trim the end*/ while (m->num_exentries && - within_module_init(m->extable[m->num_exentries-1].insn, m)) + within_module_init(ex_to_insn(&m->extable[m->num_exentries - 1]), + m)) m->num_exentries--; } #endif /* CONFIG_MODULES */ @@ -81,9 +113,9 @@ * careful, the distance between value and insn * can be larger than MAX_LONG: */ - if (mid->insn < value) + if (ex_to_insn(mid) < value) first = mid + 1; - else if (mid->insn > value) + else if (ex_to_insn(mid) > value) last = mid - 1; else return mid; diff -ruw linux-4.4.115/lib/hweight.c linux-4.4.115-fbx/lib/hweight.c --- linux-4.4.115/lib/hweight.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/lib/hweight.c 2019-01-22 16:16:28.763294039 +0100 @@ -9,6 +9,7 @@ * The Hamming Weight of a number is the total number of bits set in it. */ +#ifndef __HAVE_ARCH_SW_HWEIGHT unsigned int __sw_hweight32(unsigned int w) { #ifdef CONFIG_ARCH_HAS_FAST_MULTIPLIER @@ -25,6 +26,7 @@ #endif } EXPORT_SYMBOL(__sw_hweight32); +#endif unsigned int __sw_hweight16(unsigned int w) { @@ -43,6 +45,7 @@ } EXPORT_SYMBOL(__sw_hweight8); +#ifndef __HAVE_ARCH_SW_HWEIGHT unsigned long __sw_hweight64(__u64 w) { #if BITS_PER_LONG == 32 @@ -65,3 +68,4 @@ #endif } EXPORT_SYMBOL(__sw_hweight64); +#endif diff -ruw linux-4.4.115/lib/Kconfig linux-4.4.115-fbx/lib/Kconfig --- linux-4.4.115/lib/Kconfig 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/lib/Kconfig 2019-01-22 16:16:28.751293930 +0100 @@ -185,6 +185,9 @@ when they need to do cyclic redundancy check according CRC8 algorithm. Module will be called crc8. +config XXHASH + tristate + config AUDIT_GENERIC bool depends on AUDIT && !AUDIT_ARCH @@ -239,6 +242,14 @@ config LZ4_DECOMPRESS tristate +config ZSTD_COMPRESS + select XXHASH + tristate + +config ZSTD_DECOMPRESS + select XXHASH + tristate + source "lib/xz/Kconfig" # @@ -531,4 +542,31 @@ config ARCH_HAS_MMIO_FLUSH bool +config QMI_ENCDEC + bool "QMI Encode/Decode Library" + help + Library to encode & decode QMI messages from within + the kernel. The kernel drivers encode the C structure into + QMI message wire format and then send it over a transport. + The kernel drivers receive the QMI message over a transport + and then decode it into a C structure. + +config QMI_ENCDEC_DEBUG + bool "QMI Encode/Decode Library Debug" + help + Kernel config option to enable debugging QMI Encode/Decode + library. This will log the information regarding the element + and message being encoded & decoded. + +config STACKDEPOT + bool + select STACKTRACE + +config ARCH_HAS_FBXSERIAL + bool + +config FBXSERIAL + bool "fbxserial" + select CRC32 + endmenu diff -ruw linux-4.4.115/lib/Kconfig.debug linux-4.4.115-fbx/lib/Kconfig.debug --- linux-4.4.115/lib/Kconfig.debug 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/lib/Kconfig.debug 2019-10-29 09:26:25.669223005 +0100 @@ -244,6 +244,7 @@ depends on DEBUG_KERNEL && STACKTRACE_SUPPORT select DEBUG_FS select STACKTRACE + select STACKDEPOT select PAGE_EXTENSION help This keeps track of what call chain is the owner of a page, may @@ -255,6 +256,13 @@ If unsure, say N. +config PAGE_OWNER_ENABLE_DEFAULT + bool "Enable Track page owner by default" + depends on PAGE_OWNER + ---help--- + Enable track page owner by default? This value + can be overridden by page_owner_disabled=off|on. + config DEBUG_FS bool "Debug Filesystem" help @@ -674,8 +682,42 @@ source "lib/Kconfig.kasan" +config DEBUG_REFCOUNT + bool "Verbose refcount checks" + help + Say Y here if you want reference counters (refcount_t and kref) to + generate WARNs on dubious usage. Without this refcount_t will still + be a saturating counter and avoid Use-After-Free by turning it into + a resource leak Denial-Of-Service. + + Use of this option will increase kernel text size but will alert the + admin of potential abuse. + + If in doubt, say "N". + endmenu # "Memory Debugging" +config ARCH_HAS_KCOV + bool + help + KCOV does not have any arch-specific code, but currently it is enabled + only for x86_64. KCOV requires testing on other archs, and most likely + disabling of instrumentation for some early boot code. + +config KCOV + bool "Code coverage for fuzzing" + depends on ARCH_HAS_KCOV + select DEBUG_FS + help + KCOV exposes kernel code coverage information in a form suitable + for coverage-guided fuzzing (randomized testing). + + If RANDOMIZE_BASE is enabled, PC values will not be stable across + different machines and across reboots. If you need stable PC values, + disable RANDOMIZE_BASE. + + For more details, see Documentation/kcov.txt. + config DEBUG_SHIRQ bool "Debug shared IRQ handlers" depends on DEBUG_KERNEL @@ -707,15 +749,27 @@ The overhead should be minimal. A periodic hrtimer runs to generate interrupts and kick the watchdog task every 4 seconds. An NMI is generated every 10 seconds or so to check for hardlockups. + If NMIs are not available on the platform, every 12 seconds the + hrtimer interrupt on one cpu will be used to check for hardlockups + on the next cpu. The frequency of hrtimer and NMI events and the soft and hard lockup thresholds can be controlled through the sysctl watchdog_thresh. -config HARDLOCKUP_DETECTOR +config HARDLOCKUP_DETECTOR_NMI def_bool y depends on LOCKUP_DETECTOR && !HAVE_NMI_WATCHDOG depends on PERF_EVENTS && HAVE_PERF_EVENTS_NMI +config HARDLOCKUP_DETECTOR_OTHER_CPU + def_bool y + depends on LOCKUP_DETECTOR && SMP + depends on !HARDLOCKUP_DETECTOR_NMI && !HAVE_NMI_WATCHDOG + +config HARDLOCKUP_DETECTOR + def_bool y + depends on HARDLOCKUP_DETECTOR_NMI || HARDLOCKUP_DETECTOR_OTHER_CPU + config BOOTPARAM_HARDLOCKUP_PANIC bool "Panic (Reboot) On Hard Lockups" depends on HARDLOCKUP_DETECTOR @@ -812,6 +866,17 @@ default 0 if !BOOTPARAM_HUNG_TASK_PANIC default 1 if BOOTPARAM_HUNG_TASK_PANIC +config WQ_WATCHDOG + bool "Detect Workqueue Stalls" + depends on DEBUG_KERNEL + help + Say Y here to enable stall detection on workqueues. If a + worker pool doesn't make forward progress on a pending work + item for over a given amount of time, 30s by default, a + warning message is printed along with dump of workqueue + state. This can be configured through kernel parameter + "workqueue.watchdog_thresh" and its sysfs counterpart. + endmenu # "Debug lockups and hangs" config PANIC_ON_OOPS @@ -855,6 +920,34 @@ bool default n +config PANIC_ON_SCHED_BUG + bool "Panic on all bugs encountered by the scheduler" + help + Say Y here to panic on all 'BUG:' conditions encountered by the + scheduler, even potentially-recoverable ones such as scheduling + while atomic, sleeping from invalid context, and detection of + broken arch topologies. + + Say N if unsure. + +config PANIC_ON_RT_THROTTLING + bool "Panic on RT throttling" + help + Say Y here to enable the kernel to panic when a realtime + runqueue is throttled. This may be useful for detecting + and debugging RT throttling issues. + + Say N if unsure. + +config SYSRQ_SCHED_DEBUG + bool "Print scheduling debugging info from sysrq-trigger" + depends on SCHED_DEBUG + default y + help + If you say Y here, the "show-task-states(T)" and + "show-blocked-tasks(W)" sysrq-triggers will print additional + scheduling statistics. + config SCHEDSTATS bool "Collect scheduler statistics" depends on DEBUG_KERNEL && PROC_FS @@ -893,19 +986,23 @@ If unsure, say N. -config TIMER_STATS - bool "Collect kernel timers statistics" - depends on DEBUG_KERNEL && PROC_FS +config DEBUG_TASK_STACK_SCAN_OFF + bool "Disable kmemleak task stack scan by default" + depends on DEBUG_KMEMLEAK help - If you say Y here, additional code will be inserted into the - timer routines to collect statistics about kernel timers being - reprogrammed. The statistics can be read from /proc/timer_stats. - The statistics collection is started by writing 1 to /proc/timer_stats, - writing 0 stops it. This feature is useful to collect information - about timer usage patterns in kernel and userspace. This feature - is lightweight if enabled in the kernel config but not activated - (it defaults to deactivated on bootup and will only be activated - if some application like powertop activates it explicitly). + Say Y here to disable kmemleak task stack scan by default + at compile time. It can be enabled later if required by + writing to the debugfs entry : + echo "stack=on" > /sys/kernel/debug/kmemleak. + +config DEBUG_MODULE_SCAN_OFF + bool "Disable module memory scan for leaks by default" + depends on DEBUG_KMEMLEAK + help + Say Y here to disable scanning kernel modules area list + by default for memory leaks. Module scan an potentially + run with irq/preemption disabled for considerable amount + of time. config DEBUG_PREEMPT bool "Debug preemptible kernel" @@ -936,6 +1033,28 @@ best used in conjunction with the NMI watchdog so that spinlock deadlocks are also debuggable. +choice + prompt "Perform Action on spinlock bug" + depends on DEBUG_SPINLOCK + + default DEBUG_SPINLOCK_BITE_ON_BUG + + config DEBUG_SPINLOCK_BITE_ON_BUG + bool "Cause a Watchdog Bite on Spinlock bug" + depends on QCOM_WATCHDOG_V2 + help + On a spinlock bug, cause a watchdog bite so that we can get the precise + state of the system captured at the time of spin dump. This is mutually + exclusive with the below DEBUG_SPINLOCK_PANIC_ON_BUG config. + + config DEBUG_SPINLOCK_PANIC_ON_BUG + bool "Cause a Kernel Panic on Spinlock bug" + help + On a spinlock bug, cause a kernel panic so that we can get the complete + information about the system at the time of spin dump in the dmesg. + This is mutually exclusive with the above DEBUG_SPINLOCK_BITE_ON_BUG. +endchoice + config DEBUG_MUTEXES bool "Mutex debugging: basic checks" depends on DEBUG_KERNEL @@ -1357,6 +1476,17 @@ RCU grace period persists, additional CPU stall warnings are printed at more widely spaced intervals. +config RCU_STALL_WATCHDOG_BITE + bool "RCU stall induce watchdog bite" + depends on RCU_STALL_COMMON && QCOM_WATCHDOG_V2 + help + Induce watchdog bite if RCU grace period extends more than + specified no of seconds instead of just warning messages. + This helps to collect ram dumps and cpu context for + postmortem analysis. Generally if a given RCU grace period + extends more than the specified number of seconds, + a CPU stall warning is printed. + config RCU_TRACE bool "Enable tracing for RCU" depends on DEBUG_KERNEL @@ -1532,6 +1662,20 @@ and to test how the mmc host driver handles retries from the block device. +config UFS_FAULT_INJECTION + bool "Fault-injection capability for UFS IO" + select DEBUG_FS + depends on FAULT_INJECTION && SCSI_UFSHCD + help + Provide fault-injection capability for UFS IO. + This will make the UFS host controller driver to randomly + abort ongoing commands in the host controller, update OCS + field according to the injected fatal error and can also + forcefully hang the command indefinitely till upper layer + timeout occurs. This is useful to test error handling in + the UFS contoller driver and test how the driver handles + the retries from block/SCSI mid layer. + config FAIL_FUTEX bool "Fault-injection capability for futexes" select DEBUG_FS @@ -1840,6 +1984,19 @@ memtest=17, mean do 17 test patterns. If you are unsure how to answer this question, answer N. +config MEMTEST_ENABLE_DEFAULT + int "Enable Memtest pattern test by default? (0-17)" + range 0 17 + default "0" + depends on MEMTEST + help + This option helps to select Memtest to be enabled through + kernel defconfig options. Alternatively it can be enabled + using memtest= kernel command line. + + Default value is kept as "0" so that it is kept as disabled. + To enable enter any value between 1-17 range. + config TEST_STATIC_KEYS tristate "Test static keys" default n @@ -1849,7 +2006,16 @@ If unsure, say N. +config PANIC_ON_DATA_CORRUPTION + bool "Cause a Kernel Panic When Data Corruption is detected" + help + Select this option to upgrade warnings for potentially + recoverable data corruption scenarios to system-halting panics, + for easier detection and debug. + source "samples/Kconfig" source "lib/Kconfig.kgdb" +source "lib/Kconfig.ubsan" + diff -ruw linux-4.4.115/lib/Kconfig.kasan linux-4.4.115-fbx/lib/Kconfig.kasan --- linux-4.4.115/lib/Kconfig.kasan 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/lib/Kconfig.kasan 2019-01-22 16:16:28.751293930 +0100 @@ -5,8 +5,9 @@ config KASAN bool "KASan: runtime memory debugger" - depends on SLUB_DEBUG + depends on SLUB || (SLAB && !DEBUG_SLAB) select CONSTRUCTORS + select STACKDEPOT help Enables kernel address sanitizer - runtime memory debugger, designed to find out-of-bounds accesses and use-after-free bugs. @@ -16,6 +17,10 @@ This feature consumes about 1/8 of available memory and brings about ~x3 performance slowdown. For better error detection enable CONFIG_STACKTRACE. + See KASAN_SANITIZE_ALL for selectively compiling files and directories + with this compiler feature enabled. + Currently CONFIG_KASAN doesn't work with CONFIG_DEBUG_SLAB + (the resulting kernel does not boot). choice prompt "Instrumentation type" @@ -42,6 +47,22 @@ endchoice +config KASAN_SANITIZE_ALL + bool "KASan: Enable Instrumentation for entire kernel" + depends on KASAN + default y + help + Enable compilation with $(CFLAGS_KASAN) by default. + KASAN_SANITIZE := n - exclude all files in a directory + KASAN_SANITIZE_file_name.o := n - exclude a single file + Setting KASAN_SANITIZE_ALL to 'n' allows enabling kasan in + only certain files or directories. + KASAN_SANITIZE := y - include all files in a directory + KASAN_SANITIZE_file_name.o := y - include single file + + KASAN_SANITIZE does not affect subdirectories. + KASAN_SANITIZE_file_name.o has priority over KASAN_SANITIZE. + config TEST_KASAN tristate "Module for testing kasan for bug detection" depends on m && KASAN diff -ruw linux-4.4.115/lib/libcrc32c.c linux-4.4.115-fbx/lib/libcrc32c.c --- linux-4.4.115/lib/libcrc32c.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/lib/libcrc32c.c 2019-01-22 16:16:28.767294075 +0100 @@ -42,7 +42,7 @@ u32 crc32c(u32 crc, const void *address, unsigned int length) { SHASH_DESC_ON_STACK(shash, tfm); - u32 *ctx = (u32 *)shash_desc_ctx(shash); + u32 ret, *ctx = (u32 *)shash_desc_ctx(shash); int err; shash->tfm = tfm; @@ -52,7 +52,9 @@ err = crypto_shash_update(shash, address, length); BUG_ON(err); - return *ctx; + ret = *ctx; + barrier_data(ctx); + return ret; } EXPORT_SYMBOL(crc32c); diff -ruw linux-4.4.115/lib/Makefile linux-4.4.115-fbx/lib/Makefile --- linux-4.4.115/lib/Makefile 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/lib/Makefile 2019-10-29 09:26:25.669223005 +0100 @@ -7,6 +7,18 @@ KBUILD_CFLAGS = $(subst $(CC_FLAGS_FTRACE),,$(ORIG_CFLAGS)) endif +# These files are disabled because they produce lots of non-interesting and/or +# flaky coverage that is not a function of syscall inputs. For example, +# rbtree can be global and individual rotations don't correlate with inputs. +KCOV_INSTRUMENT_string.o := n +KCOV_INSTRUMENT_rbtree.o := n +KCOV_INSTRUMENT_list_debug.o := n +KCOV_INSTRUMENT_debugobjects.o := n +KCOV_INSTRUMENT_dynamic_debug.o := n +# Kernel does not boot if we instrument this file as it uses custom calling +# convention (see CONFIG_ARCH_HWEIGHT_CFLAGS). +KCOV_INSTRUMENT_hweight.o := n + lib-y := ctype.o string.o vsprintf.o cmdline.o \ rbtree.o radix-tree.o dump_stack.o timerqueue.o\ idr.o int_sqrt.o extable.o \ @@ -22,12 +34,14 @@ lib-y += kobject.o klist.o obj-y += lockref.o +KASAN_SANITIZE_find_bit.o := n + obj-y += bcd.o div64.o sort.o parser.o halfmd4.o debug_locks.o random32.o \ bust_spinlocks.o kasprintf.o bitmap.o scatterlist.o \ gcd.o lcm.o list_sort.o uuid.o flex_array.o iov_iter.o clz_ctz.o \ bsearch.o find_bit.o llist.o memweight.o kfifo.o \ percpu-refcount.o percpu_ida.o rhashtable.o reciprocal_div.o \ - once.o + once.o hash.o obj-y += string_helpers.o obj-$(CONFIG_TEST_STRING_HELPERS) += test-string_helpers.o obj-y += hexdump.o @@ -58,8 +72,6 @@ obj-$(CONFIG_CHECK_SIGNATURE) += check_signature.o obj-$(CONFIG_DEBUG_LOCKING_API_SELFTESTS) += locking-selftest.o -GCOV_PROFILE_hweight.o := n -CFLAGS_hweight.o = $(subst $(quote),,$(CONFIG_ARCH_HWEIGHT_CFLAGS)) obj-$(CONFIG_GENERIC_HWEIGHT) += hweight.o obj-$(CONFIG_BTREE) += btree.o @@ -83,6 +95,7 @@ obj-$(CONFIG_CRC7) += crc7.o obj-$(CONFIG_LIBCRC32C) += libcrc32c.o obj-$(CONFIG_CRC8) += crc8.o +obj-$(CONFIG_XXHASH) += xxhash.o obj-$(CONFIG_GENERIC_ALLOCATOR) += genalloc.o obj-$(CONFIG_842_COMPRESS) += 842/ @@ -96,6 +109,8 @@ obj-$(CONFIG_LZ4_COMPRESS) += lz4/ obj-$(CONFIG_LZ4HC_COMPRESS) += lz4/ obj-$(CONFIG_LZ4_DECOMPRESS) += lz4/ +obj-$(CONFIG_ZSTD_COMPRESS) += zstd/ +obj-$(CONFIG_ZSTD_DECOMPRESS) += zstd/ obj-$(CONFIG_XZ_DEC) += xz/ obj-$(CONFIG_RAID6_PQ) += raid6/ @@ -165,6 +180,9 @@ obj-$(CONFIG_SG_SPLIT) += sg_split.o obj-$(CONFIG_STMP_DEVICE) += stmp_device.o +obj-$(CONFIG_STACKDEPOT) += stackdepot.o +KASAN_SANITIZE_stackdepot.o := n + libfdt_files = fdt.o fdt_ro.o fdt_wip.o fdt_rw.o fdt_sw.o fdt_strerror.o \ fdt_empty_tree.o $(foreach file, $(libfdt_files), \ @@ -208,3 +226,11 @@ clean-files += oid_registry_data.c obj-$(CONFIG_UCS2_STRING) += ucs2_string.o + +obj-$(CONFIG_QMI_ENCDEC) += qmi_encdec.o + +obj-$(CONFIG_UBSAN) += ubsan.o + +UBSAN_SANITIZE_ubsan.o := n + +obj-$(CONFIG_FBXSERIAL) += fbxserial.o diff -ruw linux-4.4.115/lib/radix-tree.c linux-4.4.115-fbx/lib/radix-tree.c --- linux-4.4.115/lib/radix-tree.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/lib/radix-tree.c 2019-01-22 16:16:28.771294111 +0100 @@ -1035,6 +1035,49 @@ EXPORT_SYMBOL(radix_tree_gang_lookup); /** + * radix_tree_gang_lookup_index - perform multiple lookup on a radix tree + * @root: radix tree root + * @results: where the results of the lookup are placed + * @indices: where their indices should be placed + * @first_index: start the lookup from this key + * @max_items: place up to this many items at *results + * + * Performs an index-ascending scan of the tree for present items. Places + * them at *@results and returns the number of items which were placed at + * *@results. The indices are placed in @indices. + * + * The implementation is naive. + * + * Just one difference from radix_tree_gang_lookup, the indices are also + * collected along with the results of lookup. + */ +unsigned int +radix_tree_gang_lookup_index(struct radix_tree_root *root, void **results, + unsigned long *indices, unsigned long first_index, + unsigned int max_items) +{ + struct radix_tree_iter iter; + void **slot; + unsigned int ret = 0; + + if (unlikely(!max_items)) + return 0; + + radix_tree_for_each_slot(slot, root, &iter, first_index) { + results[ret] = indirect_to_ptr(rcu_dereference_raw(*slot)); + if (!results[ret]) + continue; + if (indices) + indices[ret] = iter.index; + if (++ret == max_items) + break; + } + + return ret; +} +EXPORT_SYMBOL(radix_tree_gang_lookup_index); + +/** * radix_tree_gang_lookup_slot - perform multiple slot lookup on radix tree * @root: radix tree root * @results: where the results of the lookup are placed diff -ruw linux-4.4.115/lib/strncpy_from_user.c linux-4.4.115-fbx/lib/strncpy_from_user.c --- linux-4.4.115/lib/strncpy_from_user.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/lib/strncpy_from_user.c 2019-10-29 09:26:25.677223083 +0100 @@ -1,5 +1,6 @@ #include #include +#include #include #include #include @@ -14,6 +15,8 @@ (((long) dst | (long) src) & (sizeof(long) - 1)) #endif +#define CHECK_ALIGN(v, a) ((((unsigned long)(v)) & ((a) - 1)) == 0) + /* * Do a strncpy, return length of string without final '\0'. * 'count' is the user-supplied count (return 'count' if we @@ -35,12 +38,27 @@ if (IS_UNALIGNED(src, dst)) goto byte_at_a_time; + /* Copy a byte at a time until we align to 8 bytes */ + while (max && (!CHECK_ALIGN(src + res, 8))) { + char c; + int ret; + + ret = __get_user(c, src + res); + if (ret) + return -EFAULT; + dst[res] = c; + if (!c) + return res; + res++; + max--; + } + while (max >= sizeof(unsigned long)) { unsigned long c, data; /* Fall back to byte-at-a-time if we get a page fault */ - if (unlikely(__get_user(c,(unsigned long __user *)(src+res)))) - break; + unsafe_get_user(c, (unsigned long __user *)(src+res), byte_at_a_time); + *(unsigned long *)(dst+res) = c; if (has_zero(c, &data, &constants)) { data = prep_zero_mask(c, data, &constants); @@ -55,8 +73,7 @@ while (max) { char c; - if (unlikely(__get_user(c,src+res))) - return -EFAULT; + unsafe_get_user(c,src+res, efault); dst[res] = c; if (!c) return res; @@ -75,6 +92,7 @@ * Nope: we hit the address space limit, and we still had more * characters the caller would have wanted. That's an EFAULT. */ +efault: return -EFAULT; } @@ -107,7 +125,13 @@ src_addr = (unsigned long)src; if (likely(src_addr < max_addr)) { unsigned long max = max_addr - src_addr; - return do_strncpy_from_user(dst, src, count, max); + long retval; + + check_object_size(dst, count, false); + user_access_begin(); + retval = do_strncpy_from_user(dst, src, count, max); + user_access_end(); + return retval; } return -EFAULT; } diff -ruw linux-4.4.115/lib/strnlen_user.c linux-4.4.115-fbx/lib/strnlen_user.c --- linux-4.4.115/lib/strnlen_user.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/lib/strnlen_user.c 2019-10-29 09:26:25.677223083 +0100 @@ -45,8 +45,7 @@ src -= align; max += align; - if (unlikely(__get_user(c,(unsigned long __user *)src))) - return 0; + unsafe_get_user(c, (unsigned long __user *)src, efault); c |= aligned_byte_mask(align); for (;;) { @@ -61,8 +60,7 @@ if (unlikely(max <= sizeof(unsigned long))) break; max -= sizeof(unsigned long); - if (unlikely(__get_user(c,(unsigned long __user *)(src+res)))) - return 0; + unsafe_get_user(c, (unsigned long __user *)(src+res), efault); } res -= align; @@ -77,6 +75,7 @@ * Nope: we hit the address space limit, and we still had more * characters the caller would have wanted. That's 0. */ +efault: return 0; } @@ -112,7 +111,12 @@ src_addr = (unsigned long)str; if (likely(src_addr < max_addr)) { unsigned long max = max_addr - src_addr; - return do_strnlen_user(str, count, max); + long retval; + + user_access_begin(); + retval = do_strnlen_user(str, count, max); + user_access_end(); + return retval; } return 0; } @@ -141,7 +145,12 @@ src_addr = (unsigned long)str; if (likely(src_addr < max_addr)) { unsigned long max = max_addr - src_addr; - return do_strnlen_user(str, ~0ul, max); + long retval; + + user_access_begin(); + retval = do_strnlen_user(str, ~0ul, max); + user_access_end(); + return retval; } return 0; } diff -ruw linux-4.4.115/Makefile linux-4.4.115-fbx/Makefile --- linux-4.4.115/Makefile 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/Makefile 2019-10-29 09:32:37.124855595 +0100 @@ -146,7 +146,7 @@ $(filter-out _all sub-make $(CURDIR)/Makefile, $(MAKECMDGOALS)) _all: sub-make @: -sub-make: FORCE +sub-make: $(Q)$(MAKE) -C $(KBUILD_OUTPUT) KBUILD_SRC=$(CURDIR) \ -f $(CURDIR)/Makefile $(filter-out _all sub-make,$(MAKECMDGOALS)) @@ -301,7 +301,7 @@ HOSTCC = gcc HOSTCXX = g++ -HOSTCFLAGS = -Wall -Wmissing-prototypes -Wstrict-prototypes -O2 -fomit-frame-pointer -std=gnu89 +HOSTCFLAGS := -Wall -Wmissing-prototypes -Wstrict-prototypes -O2 -fomit-frame-pointer -std=gnu89 HOSTCXXFLAGS = -O2 ifeq ($(shell $(HOSTCC) -v 2>&1 | grep -c "clang version"), 1) @@ -369,6 +369,7 @@ CFLAGS_KERNEL = AFLAGS_KERNEL = CFLAGS_GCOV = -fprofile-arcs -ftest-coverage -fno-tree-loop-im +CFLAGS_KCOV = -fsanitize-coverage=trace-pc # Use USERINCLUDE when you must reference the UAPI directories only. @@ -416,7 +417,7 @@ export HOSTCXX HOSTCXXFLAGS LDFLAGS_MODULE CHECK CHECKFLAGS export KBUILD_CPPFLAGS NOSTDINC_FLAGS LINUXINCLUDE OBJCOPYFLAGS LDFLAGS -export KBUILD_CFLAGS CFLAGS_KERNEL CFLAGS_MODULE CFLAGS_GCOV CFLAGS_KASAN +export KBUILD_CFLAGS CFLAGS_KERNEL CFLAGS_MODULE CFLAGS_GCOV CFLAGS_KCOV CFLAGS_KASAN CFLAGS_UBSAN export KBUILD_AFLAGS AFLAGS_KERNEL AFLAGS_MODULE export KBUILD_AFLAGS_MODULE KBUILD_CFLAGS_MODULE KBUILD_LDFLAGS_MODULE export KBUILD_AFLAGS_KERNEL KBUILD_CFLAGS_KERNEL @@ -624,7 +625,7 @@ KBUILD_CFLAGS += $(call cc-disable-warning, int-in-bool-context) ifdef CONFIG_CC_OPTIMIZE_FOR_SIZE -KBUILD_CFLAGS += -Os +KBUILD_CFLAGS += $(call cc-option,-Oz,-Os) else ifdef CONFIG_PROFILE_ALL_BRANCHES KBUILD_CFLAGS += -O2 @@ -693,12 +694,31 @@ endif KBUILD_CFLAGS += $(stackp-flag) +ifdef CONFIG_KCOV + ifeq ($(call cc-option, $(CFLAGS_KCOV)),) + $(warning Cannot use CONFIG_KCOV: \ + -fsanitize-coverage=trace-pc is not supported by compiler) + CFLAGS_KCOV = + endif +endif + ifeq ($(cc-name),clang) +ifneq ($(CROSS_COMPILE),) +CLANG_TRIPLE ?= $(CROSS_COMPILE) +CLANG_TARGET := --target=$(notdir $(CLANG_TRIPLE:%-=%)) +GCC_TOOLCHAIN := $(realpath $(dir $(shell which $(LD)))/..) +endif +ifneq ($(GCC_TOOLCHAIN),) +CLANG_GCC_TC := --gcc-toolchain=$(GCC_TOOLCHAIN) +endif +KBUILD_CFLAGS += $(CLANG_TARGET) $(CLANG_GCC_TC) +KBUILD_AFLAGS += $(CLANG_TARGET) $(CLANG_GCC_TC) KBUILD_CPPFLAGS += $(call cc-option,-Qunused-arguments,) -KBUILD_CPPFLAGS += $(call cc-option,-Wno-unknown-warning-option,) KBUILD_CFLAGS += $(call cc-disable-warning, unused-variable) KBUILD_CFLAGS += $(call cc-disable-warning, format-invalid-specifier) KBUILD_CFLAGS += $(call cc-disable-warning, gnu) +KBUILD_CFLAGS += $(call cc-disable-warning, address-of-packed-member) +KBUILD_CFLAGS += $(call cc-disable-warning, duplicate-decl-specifier) # Quiet clang warning: comparison of unsigned expression < 0 is always false KBUILD_CFLAGS += $(call cc-disable-warning, tautological-compare) # CLANG uses a _MergedGlobals as optimization, but this breaks modpost, as the @@ -706,6 +726,8 @@ # See modpost pattern 2 KBUILD_CFLAGS += $(call cc-option, -mno-global-merge,) KBUILD_CFLAGS += $(call cc-option, -fcatch-undefined-behavior) +KBUILD_CFLAGS += $(call cc-option, -no-integrated-as) +KBUILD_AFLAGS += $(call cc-option, -no-integrated-as) else # These warnings generated too much noise in a regular build. @@ -802,6 +824,7 @@ include scripts/Makefile.kasan include scripts/Makefile.extrawarn +include scripts/Makefile.ubsan # Add any arch overrides and user supplied CPPFLAGS, AFLAGS and CFLAGS as the # last assignments @@ -1006,7 +1029,7 @@ archprepare: archheaders archscripts prepare1 scripts_basic -prepare0: archprepare FORCE +prepare0: archprepare $(Q)$(MAKE) $(build)=. # All the preparing.. @@ -1051,7 +1074,7 @@ export INSTALL_FW_PATH PHONY += firmware_install -firmware_install: FORCE +firmware_install: @mkdir -p $(objtree)/firmware $(Q)$(MAKE) -f $(srctree)/scripts/Makefile.fwinst obj=firmware __fw_install @@ -1071,7 +1094,7 @@ archscripts: PHONY += __headers -__headers: $(version_h) scripts_basic asm-generic archheaders archscripts FORCE +__headers: $(version_h) scripts_basic asm-generic archheaders archscripts $(Q)$(MAKE) $(build)=scripts build_unifdef PHONY += headers_install_all @@ -1284,6 +1307,8 @@ @echo ' (default: $$(INSTALL_MOD_PATH)/lib/firmware)' @echo ' dir/ - Build all files in dir and below' @echo ' dir/file.[ois] - Build specified target only' + @echo ' dir/file.ll - Build the LLVM assembly file' + @echo ' (requires compiler support for LLVM assembly generation)' @echo ' dir/file.lst - Build specified mixed source/assembly target only' @echo ' (requires a recent binutils and recent build (System.map))' @echo ' dir/file.ko - Build module including final link' @@ -1459,6 +1484,7 @@ -o -name '.*.d' -o -name '.*.tmp' -o -name '*.mod.c' \ -o -name '*.symtypes' -o -name 'modules.order' \ -o -name modules.builtin -o -name '.tmp_*.o.*' \ + -o -name '*.ll' \ -o -name '*.gcno' \) -type f -print | xargs rm -f # Generate tags for editors @@ -1562,6 +1588,8 @@ $(Q)$(MAKE) $(build)=$(build-dir) $(target-dir)$(notdir $@) %.symtypes: %.c prepare scripts FORCE $(Q)$(MAKE) $(build)=$(build-dir) $(target-dir)$(notdir $@) +%.ll: %.c prepare scripts FORCE + $(Q)$(MAKE) $(build)=$(build-dir) $(target-dir)$(notdir $@) # Modules /: prepare scripts FORCE diff -ruw linux-4.4.115/mm/backing-dev.c linux-4.4.115-fbx/mm/backing-dev.c --- linux-4.4.115/mm/backing-dev.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/mm/backing-dev.c 2019-10-29 09:26:25.681223122 +0100 @@ -237,6 +237,7 @@ bdi_class->dev_groups = bdi_dev_groups; bdi_debug_init(); + return 0; } postcore_initcall(bdi_class_init); @@ -780,6 +781,7 @@ bdi->dev = NULL; + kref_init(&bdi->refcnt); bdi->min_ratio = 0; bdi->max_ratio = 100; bdi->max_prop_frac = FPROP_FRAC_BASE; @@ -795,6 +797,22 @@ } EXPORT_SYMBOL(bdi_init); +struct backing_dev_info *bdi_alloc_node(gfp_t gfp_mask, int node_id) +{ + struct backing_dev_info *bdi; + + bdi = kmalloc_node(sizeof(struct backing_dev_info), + gfp_mask | __GFP_ZERO, node_id); + if (!bdi) + return NULL; + + if (bdi_init(bdi)) { + kfree(bdi); + return NULL; + } + return bdi; +} + int bdi_register(struct backing_dev_info *bdi, struct device *parent, const char *fmt, ...) { @@ -875,12 +893,26 @@ } } -void bdi_exit(struct backing_dev_info *bdi) +static void bdi_exit(struct backing_dev_info *bdi) { WARN_ON_ONCE(bdi->dev); wb_exit(&bdi->wb); } +static void release_bdi(struct kref *ref) +{ + struct backing_dev_info *bdi = + container_of(ref, struct backing_dev_info, refcnt); + + bdi_exit(bdi); + kfree(bdi); +} + +void bdi_put(struct backing_dev_info *bdi) +{ + kref_put(&bdi->refcnt, release_bdi); +} + void bdi_destroy(struct backing_dev_info *bdi) { bdi_unregister(bdi); diff -ruw linux-4.4.115/mm/cma.c linux-4.4.115-fbx/mm/cma.c --- linux-4.4.115/mm/cma.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/mm/cma.c 2019-10-29 09:26:25.685223161 +0100 @@ -35,6 +35,7 @@ #include #include #include +#include #include #include "cma.h" @@ -131,6 +132,10 @@ spin_lock_init(&cma->mem_head_lock); #endif + if (!PageHighMem(pfn_to_page(cma->base_pfn))) + kmemleak_free_part(__va(cma->base_pfn << PAGE_SHIFT), + cma->count << PAGE_SHIFT); + return 0; err: @@ -367,6 +372,7 @@ unsigned long bitmap_maxno, bitmap_no, bitmap_count; struct page *page = NULL; int ret; + int retry_after_sleep = 0; if (!cma || !cma->count) return NULL; @@ -377,20 +383,41 @@ if (!count) return NULL; + trace_cma_alloc_start(count, align); + mask = cma_bitmap_aligned_mask(cma, align); offset = cma_bitmap_aligned_offset(cma, align); bitmap_maxno = cma_bitmap_maxno(cma); bitmap_count = cma_bitmap_pages_to_bits(cma, count); + if (bitmap_count > bitmap_maxno) + return NULL; + for (;;) { mutex_lock(&cma->lock); bitmap_no = bitmap_find_next_zero_area_off(cma->bitmap, bitmap_maxno, start, bitmap_count, mask, offset); if (bitmap_no >= bitmap_maxno) { + if (retry_after_sleep < 2) { + start = 0; + /* + * Page may be momentarily pinned by some other + * process which has been scheduled out, eg. + * in exit path, during unmap call, or process + * fork and so cannot be freed there. Sleep + * for 100ms and retry twice to see if it has + * been freed later. + */ + mutex_unlock(&cma->lock); + msleep(100); + retry_after_sleep++; + continue; + } else { mutex_unlock(&cma->lock); break; } + } bitmap_set(cma->bitmap, bitmap_no, bitmap_count); /* * It's safe to drop the lock here. We've marked this region for @@ -414,6 +441,8 @@ pr_debug("%s(): memory range at %p is busy, retrying\n", __func__, pfn_to_page(pfn)); + + trace_cma_alloc_busy_retry(pfn, pfn_to_page(pfn), count, align); /* try again with a bit different memory target */ start = bitmap_no + mask + 1; } diff -ruw linux-4.4.115/mm/compaction.c linux-4.4.115-fbx/mm/compaction.c --- linux-4.4.115/mm/compaction.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/mm/compaction.c 2019-10-29 09:26:25.685223161 +0100 @@ -7,6 +7,7 @@ * * Copyright IBM Corp. 2007-2010 Mel Gorman */ +#include #include #include #include @@ -14,9 +15,11 @@ #include #include #include -#include #include #include +#include +#include +#include #include "internal.h" #ifdef CONFIG_COMPACTION @@ -57,13 +60,27 @@ static void map_pages(struct list_head *list) { - struct page *page; + unsigned int i, order, nr_pages; + struct page *page, *next; + LIST_HEAD(tmp_list); + + list_for_each_entry_safe(page, next, list, lru) { + list_del(&page->lru); + + order = page_private(page); + nr_pages = 1 << order; + + post_alloc_hook(page, order, __GFP_MOVABLE); + if (order) + split_page(page, order); - list_for_each_entry(page, list, lru) { - arch_alloc_page(page, 0); - kernel_map_pages(page, 1, 1); - kasan_alloc_pages(page, 0); + for (i = 0; i < nr_pages; i++) { + list_add(&page->lru, &tmp_list); + page++; + } } + + list_splice(&tmp_list, list); } static inline bool migrate_async_suitable(int migratetype) @@ -116,6 +133,44 @@ #ifdef CONFIG_COMPACTION +int PageMovable(struct page *page) +{ + struct address_space *mapping; + + VM_BUG_ON_PAGE(!PageLocked(page), page); + if (!__PageMovable(page)) + return 0; + + mapping = page_mapping(page); + if (mapping && mapping->a_ops && mapping->a_ops->isolate_page) + return 1; + + return 0; +} +EXPORT_SYMBOL(PageMovable); + +void __SetPageMovable(struct page *page, struct address_space *mapping) +{ + VM_BUG_ON_PAGE(!PageLocked(page), page); + VM_BUG_ON_PAGE((unsigned long)mapping & PAGE_MAPPING_MOVABLE, page); + page->mapping = (void *)((unsigned long)mapping | PAGE_MAPPING_MOVABLE); +} +EXPORT_SYMBOL(__SetPageMovable); + +void __ClearPageMovable(struct page *page) +{ + VM_BUG_ON_PAGE(!PageLocked(page), page); + VM_BUG_ON_PAGE(!PageMovable(page), page); + /* + * Clear registered address_space val with keeping PAGE_MAPPING_MOVABLE + * flag so that VM can catch up released page by driver after isolation. + * With it, VM migration doesn't try to put it back. + */ + page->mapping = (void *)((unsigned long)page->mapping & + PAGE_MAPPING_MOVABLE); +} +EXPORT_SYMBOL(__ClearPageMovable); + /* Do not skip compaction more than 64 times */ #define COMPACT_MAX_DEFER_SHIFT 6 @@ -403,12 +458,13 @@ unsigned long flags = 0; bool locked = false; unsigned long blockpfn = *start_pfn; + unsigned int order; cursor = pfn_to_page(blockpfn); /* Isolate free pages. */ for (; blockpfn < end_pfn; blockpfn++, cursor++) { - int isolated, i; + int isolated; struct page *page = cursor; /* @@ -474,17 +530,17 @@ goto isolate_fail; } - /* Found a free page, break it into order-0 pages */ - isolated = split_free_page(page); + /* Found a free page, will break it into order-0 pages */ + order = page_order(page); + isolated = __isolate_free_page(page, order); if (!isolated) break; + set_page_private(page, order); total_isolated += isolated; cc->nr_freepages += isolated; - for (i = 0; i < isolated; i++) { - list_add(&page->lru, freelist); - page++; - } + list_add_tail(&page->lru, freelist); + if (!strict && cc->nr_migratepages <= cc->nr_freepages) { blockpfn += isolated; break; @@ -603,7 +659,7 @@ */ } - /* split_free_page does not map the pages */ + /* __isolate_free_page() does not map the pages */ map_pages(&freelist); if (pfn < end_pfn) { @@ -632,21 +688,46 @@ mod_zone_page_state(zone, NR_ISOLATED_FILE, count[1]); } -/* Similar to reclaim, but different enough that they don't share logic */ -static bool too_many_isolated(struct zone *zone) +static bool __too_many_isolated(struct zone *zone, int safe) { unsigned long active, inactive, isolated; + if (safe) { + inactive = zone_page_state_snapshot(zone, NR_INACTIVE_FILE) + + zone_page_state_snapshot(zone, NR_INACTIVE_ANON); + active = zone_page_state_snapshot(zone, NR_ACTIVE_FILE) + + zone_page_state_snapshot(zone, NR_ACTIVE_ANON); + isolated = zone_page_state_snapshot(zone, NR_ISOLATED_FILE) + + zone_page_state_snapshot(zone, NR_ISOLATED_ANON); + } else { inactive = zone_page_state(zone, NR_INACTIVE_FILE) + zone_page_state(zone, NR_INACTIVE_ANON); active = zone_page_state(zone, NR_ACTIVE_FILE) + zone_page_state(zone, NR_ACTIVE_ANON); isolated = zone_page_state(zone, NR_ISOLATED_FILE) + zone_page_state(zone, NR_ISOLATED_ANON); + } return isolated > (inactive + active) / 2; } +/* Similar to reclaim, but different enough that they don't share logic */ +static bool too_many_isolated(struct compact_control *cc) +{ + /* + * __too_many_isolated(safe=0) is fast but inaccurate, because it + * doesn't account for the vm_stat_diff[] counters. So if it looks + * like too_many_isolated() is about to return true, fall back to the + * slower, more accurate zone_page_state_snapshot(). + */ + if (unlikely(__too_many_isolated(cc->zone, 0))) { + if (cc->mode != MIGRATE_ASYNC) + return __too_many_isolated(cc->zone, 1); + } + + return false; +} + /** * isolate_migratepages_block() - isolate all migrate-able pages within * a single pageblock @@ -683,7 +764,7 @@ * list by either parallel reclaimers or compaction. If there are, * delay for some time until fewer pages are isolated */ - while (unlikely(too_many_isolated(zone))) { + while (unlikely(too_many_isolated(cc))) { /* async migration should just abort */ if (cc->mode == MIGRATE_ASYNC) return 0; @@ -699,7 +780,6 @@ /* Time to isolate some pages for migration */ for (; low_pfn < end_pfn; low_pfn++) { - bool is_lru; /* * Periodically drop the lock (if held) regardless of its @@ -740,21 +820,6 @@ } /* - * Check may be lockless but that's ok as we recheck later. - * It's possible to migrate LRU pages and balloon pages - * Skip any other type of page - */ - is_lru = PageLRU(page); - if (!is_lru) { - if (unlikely(balloon_page_movable(page))) { - if (balloon_page_isolate(page)) { - /* Successfully isolated */ - goto isolate_success; - } - } - } - - /* * Regardless of being on LRU, compound pages such as THP and * hugetlbfs are not to be compacted. We can potentially save * a lot of iterations if we skip them at once. The check is @@ -770,8 +835,30 @@ continue; } - if (!is_lru) + /* + * Check may be lockless but that's ok as we recheck later. + * It's possible to migrate LRU and non-lru movable pages. + * Skip any other type of page + */ + if (!PageLRU(page)) { + /* + * __PageMovable can return false positive so we need + * to verify it under page_lock. + */ + if (unlikely(__PageMovable(page)) && + !PageIsolated(page)) { + if (locked) { + spin_unlock_irqrestore(&zone->lru_lock, + flags); + locked = false; + } + + if (isolate_movable_page(page, isolate_mode)) + goto isolate_success; + } + continue; + } /* * Migration will fail if an anonymous page is pinned in memory, @@ -1026,7 +1113,7 @@ } } - /* split_free_page does not map the pages */ + /* __isolate_free_page() does not map the pages */ map_pages(freelist); /* @@ -1218,11 +1305,11 @@ /* * Mark that the PG_migrate_skip information should be cleared - * by kswapd when it goes to sleep. kswapd does not set the + * by kswapd when it goes to sleep. kcompactd does not set the * flag itself as the decision to be clear should be directly * based on an allocation request. */ - if (!current_is_kswapd()) + if (cc->direct_compaction) zone->compact_blockskip_flush = true; return COMPACT_COMPLETE; @@ -1365,10 +1452,9 @@ /* * Clear pageblock skip if there were failures recently and compaction - * is about to be retried after being deferred. kswapd does not do - * this reset as it'll reset the cached information when going to sleep. + * is about to be retried after being deferred. */ - if (compaction_restarting(zone, cc->order) && !current_is_kswapd()) + if (compaction_restarting(zone, cc->order)) __reset_isolation_suitable(zone); /* @@ -1504,6 +1590,7 @@ .mode = mode, .alloc_flags = alloc_flags, .classzone_idx = classzone_idx, + .direct_compaction = true, }; INIT_LIST_HEAD(&cc.freepages); INIT_LIST_HEAD(&cc.migratepages); @@ -1762,4 +1849,225 @@ } #endif /* CONFIG_SYSFS && CONFIG_NUMA */ +static inline bool kcompactd_work_requested(pg_data_t *pgdat) +{ + return pgdat->kcompactd_max_order > 0 || kthread_should_stop(); +} + +static bool kcompactd_node_suitable(pg_data_t *pgdat) +{ + int zoneid; + struct zone *zone; + enum zone_type classzone_idx = pgdat->kcompactd_classzone_idx; + + for (zoneid = 0; zoneid <= classzone_idx; zoneid++) { + zone = &pgdat->node_zones[zoneid]; + + if (!populated_zone(zone)) + continue; + + if (compaction_suitable(zone, pgdat->kcompactd_max_order, 0, + classzone_idx) == COMPACT_CONTINUE) + return true; + } + + return false; +} + +static void kcompactd_do_work(pg_data_t *pgdat) +{ + /* + * With no special task, compact all zones so that a page of requested + * order is allocatable. + */ + int zoneid; + struct zone *zone; + struct compact_control cc = { + .order = pgdat->kcompactd_max_order, + .classzone_idx = pgdat->kcompactd_classzone_idx, + .mode = MIGRATE_SYNC_LIGHT, + .ignore_skip_hint = true, + + }; + bool success = false; + + trace_mm_compaction_kcompactd_wake(pgdat->node_id, cc.order, + cc.classzone_idx); + count_vm_event(KCOMPACTD_WAKE); + + for (zoneid = 0; zoneid <= cc.classzone_idx; zoneid++) { + int status; + + zone = &pgdat->node_zones[zoneid]; + if (!populated_zone(zone)) + continue; + + if (compaction_deferred(zone, cc.order)) + continue; + + if (compaction_suitable(zone, cc.order, 0, zoneid) != + COMPACT_CONTINUE) + continue; + + cc.nr_freepages = 0; + cc.nr_migratepages = 0; + cc.zone = zone; + INIT_LIST_HEAD(&cc.freepages); + INIT_LIST_HEAD(&cc.migratepages); + + if (kthread_should_stop()) + return; + status = compact_zone(zone, &cc); + + if (zone_watermark_ok(zone, cc.order, low_wmark_pages(zone), + cc.classzone_idx, 0)) { + success = true; + compaction_defer_reset(zone, cc.order, false); + } else if (status == COMPACT_COMPLETE) { + /* + * We use sync migration mode here, so we defer like + * sync direct compaction does. + */ + defer_compaction(zone, cc.order); + } + + VM_BUG_ON(!list_empty(&cc.freepages)); + VM_BUG_ON(!list_empty(&cc.migratepages)); + } + + /* + * Regardless of success, we are done until woken up next. But remember + * the requested order/classzone_idx in case it was higher/tighter than + * our current ones + */ + if (pgdat->kcompactd_max_order <= cc.order) + pgdat->kcompactd_max_order = 0; + if (pgdat->kcompactd_classzone_idx >= cc.classzone_idx) + pgdat->kcompactd_classzone_idx = pgdat->nr_zones - 1; +} + +void wakeup_kcompactd(pg_data_t *pgdat, int order, int classzone_idx) +{ + if (!order) + return; + + if (pgdat->kcompactd_max_order < order) + pgdat->kcompactd_max_order = order; + + if (pgdat->kcompactd_classzone_idx > classzone_idx) + pgdat->kcompactd_classzone_idx = classzone_idx; + + if (!waitqueue_active(&pgdat->kcompactd_wait)) + return; + + if (!kcompactd_node_suitable(pgdat)) + return; + + trace_mm_compaction_wakeup_kcompactd(pgdat->node_id, order, + classzone_idx); + wake_up_interruptible(&pgdat->kcompactd_wait); +} + +/* + * The background compaction daemon, started as a kernel thread + * from the init process. + */ +static int kcompactd(void *p) +{ + pg_data_t *pgdat = (pg_data_t*)p; + struct task_struct *tsk = current; + + const struct cpumask *cpumask = cpumask_of_node(pgdat->node_id); + + if (!cpumask_empty(cpumask)) + set_cpus_allowed_ptr(tsk, cpumask); + + set_freezable(); + + pgdat->kcompactd_max_order = 0; + pgdat->kcompactd_classzone_idx = pgdat->nr_zones - 1; + + while (!kthread_should_stop()) { + trace_mm_compaction_kcompactd_sleep(pgdat->node_id); + wait_event_freezable(pgdat->kcompactd_wait, + kcompactd_work_requested(pgdat)); + + kcompactd_do_work(pgdat); + } + + return 0; +} + +/* + * This kcompactd start function will be called by init and node-hot-add. + * On node-hot-add, kcompactd will moved to proper cpus if cpus are hot-added. + */ +int kcompactd_run(int nid) +{ + pg_data_t *pgdat = NODE_DATA(nid); + int ret = 0; + + if (pgdat->kcompactd) + return 0; + + pgdat->kcompactd = kthread_run(kcompactd, pgdat, "kcompactd%d", nid); + if (IS_ERR(pgdat->kcompactd)) { + pr_err("Failed to start kcompactd on node %d\n", nid); + ret = PTR_ERR(pgdat->kcompactd); + pgdat->kcompactd = NULL; + } + return ret; +} + +/* + * Called by memory hotplug when all memory in a node is offlined. Caller must + * hold mem_hotplug_begin/end(). + */ +void kcompactd_stop(int nid) +{ + struct task_struct *kcompactd = NODE_DATA(nid)->kcompactd; + + if (kcompactd) { + kthread_stop(kcompactd); + NODE_DATA(nid)->kcompactd = NULL; + } +} + +/* + * It's optimal to keep kcompactd on the same CPUs as their memory, but + * not required for correctness. So if the last cpu in a node goes + * away, we get changed to run anywhere: as the first one comes back, + * restore their cpu bindings. + */ +static int cpu_callback(struct notifier_block *nfb, unsigned long action, + void *hcpu) +{ + int nid; + + if (action == CPU_ONLINE || action == CPU_ONLINE_FROZEN) { + for_each_node_state(nid, N_MEMORY) { + pg_data_t *pgdat = NODE_DATA(nid); + const struct cpumask *mask; + + mask = cpumask_of_node(pgdat->node_id); + + if (cpumask_any_and(cpu_online_mask, mask) < nr_cpu_ids) + /* One of our CPUs online: restore mask */ + set_cpus_allowed_ptr(pgdat->kcompactd, mask); + } + } + return NOTIFY_OK; +} + +static int __init kcompactd_init(void) +{ + int nid; + + for_each_node_state(nid, N_MEMORY) + kcompactd_run(nid); + hotcpu_notifier(cpu_callback, 0); + return 0; +} +subsys_initcall(kcompactd_init) + #endif /* CONFIG_COMPACTION */ diff -ruw linux-4.4.115/mm/debug.c linux-4.4.115-fbx/mm/debug.c --- linux-4.4.115/mm/debug.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/mm/debug.c 2019-10-29 09:26:25.685223161 +0100 @@ -9,6 +9,18 @@ #include #include #include +#include +#include + +char *migrate_reason_names[MR_TYPES] = { + "compaction", + "memory_failure", + "memory_hotplug", + "syscall_or_cpuset", + "mempolicy_mbind", + "numa_misplaced", + "cma", +}; static const struct trace_print_flags pageflag_names[] = { {1UL << PG_locked, "locked" }, @@ -47,6 +59,9 @@ {1UL << PG_young, "young" }, {1UL << PG_idle, "idle" }, #endif +#ifdef CONFIG_ZCACHE + {1UL << PG_was_active, "was_active" }, +#endif }; static void dump_flags(unsigned long flags, @@ -103,6 +118,7 @@ void dump_page(struct page *page, const char *reason) { dump_page_badflags(page, reason, 0); + dump_page_owner(page); } EXPORT_SYMBOL(dump_page); diff -ruw linux-4.4.115/mm/dmapool.c linux-4.4.115-fbx/mm/dmapool.c --- linux-4.4.115/mm/dmapool.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/mm/dmapool.c 2019-01-22 16:16:28.791294292 +0100 @@ -452,13 +452,11 @@ } spin_unlock_irqrestore(&pool->lock, flags); if (pool->dev) - dev_err(pool->dev, "dma_pool_free %s, dma %Lx " - "already free\n", pool->name, - (unsigned long long)dma); + dev_err(pool->dev, "dma_pool_free %s, dma %Lx already free\n", + pool->name, (unsigned long long)dma); else - printk(KERN_ERR "dma_pool_free %s, dma %Lx " - "already free\n", pool->name, - (unsigned long long)dma); + printk(KERN_ERR "dma_pool_free %s, dma %Lx already free\n", + pool->name, (unsigned long long)dma); return; } } diff -ruw linux-4.4.115/mm/filemap.c linux-4.4.115-fbx/mm/filemap.c --- linux-4.4.115/mm/filemap.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/mm/filemap.c 2019-10-29 09:26:25.689223200 +0100 @@ -239,10 +239,12 @@ * invalidate any existing cleancache entries. We can't leave * stale data around in the cleancache once our page is gone */ - if (PageUptodate(page) && PageMappedToDisk(page)) + if (PageUptodate(page) && PageMappedToDisk(page)) { + count_vm_event(PGPGOUTCLEAN); cleancache_put_page(page); - else + } else { cleancache_invalidate_page(mapping, page); + } page_cache_tree_delete(mapping, page, shadow); diff -ruw linux-4.4.115/mm/internal.h linux-4.4.115-fbx/mm/internal.h --- linux-4.4.115/mm/internal.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/mm/internal.h 2019-01-22 16:16:28.795294329 +0100 @@ -182,6 +182,8 @@ #ifdef CONFIG_MEMORY_FAILURE extern bool is_free_buddy_page(struct page *page); #endif +extern void post_alloc_hook(struct page *page, unsigned int order, + gfp_t gfp_flags); extern int user_min_free_kbytes; #if defined CONFIG_COMPACTION || defined CONFIG_CMA @@ -206,6 +208,7 @@ unsigned long last_migrated_pfn;/* Not yet flushed page being freed */ enum migrate_mode mode; /* Async or sync migration mode */ bool ignore_skip_hint; /* Scan blocks even if marked skip */ + bool direct_compaction; /* False from kcompactd or /proc/... */ int order; /* order a direct compactor needs */ const gfp_t gfp_mask; /* gfp mask of a direct compactor */ const int alloc_flags; /* alloc flags of a direct compactor */ @@ -310,10 +313,8 @@ extern pmd_t maybe_pmd_mkwrite(pmd_t pmd, struct vm_area_struct *vma); -#ifdef CONFIG_TRANSPARENT_HUGEPAGE extern unsigned long vma_address(struct page *page, struct vm_area_struct *vma); -#endif #else /* !CONFIG_MMU */ static inline void clear_page_mlock(struct page *page) { } static inline void mlock_vma_page(struct page *page) { } diff -ruw linux-4.4.115/mm/kasan/Makefile linux-4.4.115-fbx/mm/kasan/Makefile --- linux-4.4.115/mm/kasan/Makefile 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/mm/kasan/Makefile 2019-01-22 16:16:28.795294329 +0100 @@ -1,8 +1,10 @@ KASAN_SANITIZE := n +UBSAN_SANITIZE_kasan.o := n +KCOV_INSTRUMENT := n CFLAGS_REMOVE_kasan.o = -pg # Function splitter causes unnecessary splits in __asan_load1/__asan_store1 # see: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=63533 CFLAGS_kasan.o := $(call cc-option, -fno-conserve-stack -fno-stack-protector) -obj-y := kasan.o report.o kasan_init.o +obj-y := kasan.o report.o kasan_init.o quarantine.o diff -ruw linux-4.4.115/mm/Kconfig linux-4.4.115-fbx/mm/Kconfig --- linux-4.4.115/mm/Kconfig 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/mm/Kconfig 2019-10-29 09:26:25.681223122 +0100 @@ -187,7 +187,7 @@ bool "Allow for memory hot-add" depends on SPARSEMEM || X86_64_ACPI_NUMA depends on ARCH_ENABLE_MEMORY_HOTPLUG - depends on (IA64 || X86 || PPC_BOOK3S_64 || SUPERH || S390) + depends on (IA64 || X86 || PPC_BOOK3S_64 || SUPERH || S390 || ARM64) config MEMORY_HOTPLUG_SPARSE def_bool y @@ -619,6 +619,44 @@ A sane initial value is 80 MB. +config ZCACHE + bool "Compressed cache for file pages (EXPERIMENTAL)" + depends on CRYPTO && CLEANCACHE + select CRYPTO_LZO + select ZBUD + default n + help + A compressed cache for file pages. + It takes active file pages that are in the process of being reclaimed + and attempts to compress them into a dynamically allocated RAM-based + memory pool. + + If this process is successful, when those file pages needed again, the + I/O reading operation was avoided. This results in a significant performance + gains under memory pressure for systems full with file pages. + +config BALANCE_ANON_FILE_RECLAIM + bool "During reclaim treat anon and file backed pages equally" + depends on SWAP + help + When performing memory reclaim treat anonymous and file backed pages + equally. + Swapping anonymous pages out to memory can be efficient enough to justify + treating anonymous and file backed pages equally. + +config KSWAPD_CPU_AFFINITY_MASK + string "kswapd cpu affinity mask" + depends on SMP + help + Set the cpu affinity for the kswapd task. + There can be power benefits on certain targets when limiting kswapd + to run only on certain cores. + The cpu affinity bitmask is represented by a hex string where commas + group hex digits into chunks. Each chunk defines exactly 32 bits of + the resultant bitmask. + For example to limit kswapd to the first 4 cores use the following: + CONFIG_KSWAPD_CPU_AFFINITY_MASK="f" + # For architectures that support deferred memory initialisation config ARCH_SUPPORTS_DEFERRED_STRUCT_PAGE_INIT bool @@ -668,3 +706,29 @@ config FRAME_VECTOR bool + +config FORCE_ALLOC_FROM_DMA_ZONE + bool "Force certain memory allocators to always return ZONE_DMA memory" + depends on ZONE_DMA + help + Ensure certain memory allocators always return memory from ZONE_DMA. + This option helps ensure that clients who require ZONE_DMA memory are + always using ZONE_DMA memory. + + If unsure, say "n". + +config PROCESS_RECLAIM + bool "Enable process reclaim" + depends on PROC_FS + default n + help + It allows to reclaim pages of the process by /proc/pid/reclaim. + + (echo file > /proc/PID/reclaim) reclaims file-backed pages only. + (echo anon > /proc/PID/reclaim) reclaims anonymous pages only. + (echo all > /proc/PID/reclaim) reclaims all pages. + + (echo addr size-byte > /proc/PID/reclaim) reclaims pages in + (addr, addr + size-bytes) of the process. + + Any other vaule is ignored. diff -ruw linux-4.4.115/mm/Kconfig.debug linux-4.4.115-fbx/mm/Kconfig.debug --- linux-4.4.115/mm/Kconfig.debug 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/mm/Kconfig.debug 2019-01-22 16:16:28.787294256 +0100 @@ -16,8 +16,8 @@ select PAGE_POISONING if !ARCH_SUPPORTS_DEBUG_PAGEALLOC ---help--- Unmap pages from the kernel linear mapping after free_pages(). - This results in a large slowdown, but helps to find certain types - of memory corruption. + Depending on runtime enablement, this results in a small or large + slowdown, but helps to find certain types of memory corruption. For architectures which don't enable ARCH_SUPPORTS_DEBUG_PAGEALLOC, fill the pages with poison patterns after free_pages() and verify @@ -26,5 +26,76 @@ that would result in incorrect warnings of memory corruption after a resume because free pages are not saved to the suspend image. + By default this option will have a small overhead, e.g. by not + allowing the kernel mapping to be backed by large pages on some + architectures. Even bigger overhead comes when the debugging is + enabled by DEBUG_PAGEALLOC_ENABLE_DEFAULT or the debug_pagealloc + command line parameter. + +config DEBUG_PAGEALLOC_ENABLE_DEFAULT + bool "Enable debug page memory allocations by default?" + default n + depends on DEBUG_PAGEALLOC + ---help--- + Enable debug page memory allocations by default? This value + can be overridden by debug_pagealloc=off|on. + +config SLUB_DEBUG_PANIC_ON + bool "Enable to Panic on SLUB corruption detection" + depends on SLUB_DEBUG + help + SLUB has a resiliency feature enabled which restores bytes in + order for production environments to continue to operate. IN + debug options this may not be desirable as it prevents from + investigating the root cause which may be rooted within cache + or memory. + config PAGE_POISONING - bool + bool "Poison pages after freeing" + select PAGE_EXTENSION + select PAGE_POISONING_NO_SANITY if HIBERNATION + ---help--- + Fill the pages with poison patterns after free_pages() and verify + the patterns before alloc_pages. The filling of the memory helps + reduce the risk of information leaks from freed data. This does + have a potential performance impact. + + Note that "poison" here is not the same thing as the "HWPoison" + for CONFIG_MEMORY_FAILURE. This is software poisoning only. + + If unsure, say N + +config PAGE_POISONING_ENABLE_DEFAULT + bool "Enable page poisoning by default?" + default n + depends on PAGE_POISONING + ---help--- + Enable page poisoning of free pages by default? This value + can be overridden by page_poison=off|on. This can be used + to avoid passing the kernel parameter and let page poisoning + feature enabled by default. + +config PAGE_POISONING_NO_SANITY + depends on PAGE_POISONING + bool "Only poison, don't sanity check" + ---help--- + Skip the sanity checking on alloc, only fill the pages with + poison on free. This reduces some of the overhead of the + poisoning feature. + + If you are only interested in sanitization, say Y. Otherwise + say N. + +config PAGE_POISONING_ZERO + bool "Use zero for poisoning instead of random data" + depends on PAGE_POISONING + ---help--- + Instead of using the existing poison value, fill the pages with + zeros. This makes it harder to detect when errors are occurring + due to sanitization but the zeroing at free means that it is + no longer necessary to write zeros when GFP_ZERO is used on + allocation. + + Enabling page poisoning with this option will disable hibernation + + If unsure, say N diff -ruw linux-4.4.115/mm/maccess.c linux-4.4.115-fbx/mm/maccess.c --- linux-4.4.115/mm/maccess.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/mm/maccess.c 2019-01-22 16:16:28.799294365 +0100 @@ -96,8 +96,7 @@ pagefault_disable(); do { - ret = __copy_from_user_inatomic(dst++, - (const void __user __force *)src++, 1); + ret = __get_user(*dst++, (const char __user __force *)src++); } while (dst[-1] && ret == 0 && src - unsafe_addr < count); dst[-1] = '\0'; diff -ruw linux-4.4.115/mm/madvise.c linux-4.4.115-fbx/mm/madvise.c --- linux-4.4.115/mm/madvise.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/mm/madvise.c 2019-10-29 09:26:25.697223279 +0100 @@ -104,7 +104,7 @@ pgoff = vma->vm_pgoff + ((start - vma->vm_start) >> PAGE_SHIFT); *prev = vma_merge(mm, *prev, start, end, new_flags, vma->anon_vma, vma->vm_file, pgoff, vma_policy(vma), - vma->vm_userfaultfd_ctx); + vma->vm_userfaultfd_ctx, vma_get_anon_name(vma)); if (*prev) { vma = *prev; goto success; diff -ruw linux-4.4.115/mm/Makefile linux-4.4.115-fbx/mm/Makefile --- linux-4.4.115/mm/Makefile 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/mm/Makefile 2019-01-22 16:16:28.787294256 +0100 @@ -3,8 +3,27 @@ # KASAN_SANITIZE_slab_common.o := n +KASAN_SANITIZE_slab.o := n KASAN_SANITIZE_slub.o := n +# Since __builtin_frame_address does work as used, disable the warning. +CFLAGS_usercopy.o += $(call cc-disable-warning, frame-address) + +# These files are disabled because they produce non-interesting and/or +# flaky coverage that is not a function of syscall inputs. E.g. slab is out of +# free pages, or a task is migrated between nodes. +KCOV_INSTRUMENT_slab_common.o := n +KCOV_INSTRUMENT_slob.o := n +KCOV_INSTRUMENT_slab.o := n +KCOV_INSTRUMENT_slub.o := n +KCOV_INSTRUMENT_page_alloc.o := n +KCOV_INSTRUMENT_debug-pagealloc.o := n +KCOV_INSTRUMENT_kmemleak.o := n +KCOV_INSTRUMENT_kmemcheck.o := n +KCOV_INSTRUMENT_memcontrol.o := n +KCOV_INSTRUMENT_mmzone.o := n +KCOV_INSTRUMENT_vmstat.o := n + mmu-y := nommu.o mmu-$(CONFIG_MMU) := gup.o highmem.o memory.o mincore.o \ mlock.o mmap.o mprotect.o mremap.o msync.o rmap.o \ @@ -21,7 +40,7 @@ mm_init.o mmu_context.o percpu.o slab_common.o \ compaction.o vmacache.o \ interval_tree.o list_lru.o workingset.o \ - debug.o $(mmu-y) + debug.o $(mmu-y) showmem.o vmpressure.o obj-y += init-mm.o @@ -37,9 +56,10 @@ endif obj-$(CONFIG_HAVE_MEMBLOCK) += memblock.o -obj-$(CONFIG_SWAP) += page_io.o swap_state.o swapfile.o +obj-$(CONFIG_SWAP) += page_io.o swap_state.o swapfile.o swap_ratio.o obj-$(CONFIG_FRONTSWAP) += frontswap.o obj-$(CONFIG_ZSWAP) += zswap.o +obj-$(CONFIG_ZCACHE) += zcache.o obj-$(CONFIG_HAS_DMA) += dmapool.o obj-$(CONFIG_HUGETLBFS) += hugetlb.o obj-$(CONFIG_NUMA) += mempolicy.o @@ -48,7 +68,7 @@ obj-$(CONFIG_SLOB) += slob.o obj-$(CONFIG_MMU_NOTIFIER) += mmu_notifier.o obj-$(CONFIG_KSM) += ksm.o -obj-$(CONFIG_PAGE_POISONING) += debug-pagealloc.o +obj-$(CONFIG_PAGE_POISONING) += page_poison.o obj-$(CONFIG_SLAB) += slab.o obj-$(CONFIG_SLUB) += slub.o obj-$(CONFIG_KMEMCHECK) += kmemcheck.o @@ -60,7 +80,7 @@ obj-$(CONFIG_QUICKLIST) += quicklist.o obj-$(CONFIG_TRANSPARENT_HUGEPAGE) += huge_memory.o obj-$(CONFIG_PAGE_COUNTER) += page_counter.o -obj-$(CONFIG_MEMCG) += memcontrol.o vmpressure.o +obj-$(CONFIG_MEMCG) += memcontrol.o obj-$(CONFIG_MEMCG_SWAP) += swap_cgroup.o obj-$(CONFIG_CGROUP_HUGETLB) += hugetlb_cgroup.o obj-$(CONFIG_MEMORY_FAILURE) += memory-failure.o @@ -81,3 +101,5 @@ obj-$(CONFIG_USERFAULTFD) += userfaultfd.o obj-$(CONFIG_IDLE_PAGE_TRACKING) += page_idle.o obj-$(CONFIG_FRAME_VECTOR) += frame_vector.o +obj-$(CONFIG_PROCESS_RECLAIM) += process_reclaim.o +obj-$(CONFIG_HARDENED_USERCOPY) += usercopy.o diff -ruw linux-4.4.115/mm/memblock.c linux-4.4.115-fbx/mm/memblock.c --- linux-4.4.115/mm/memblock.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/mm/memblock.c 2019-01-22 16:16:28.799294365 +0100 @@ -19,6 +19,9 @@ #include #include #include +#include +#include +#include #include #include @@ -31,6 +34,7 @@ static struct memblock_region memblock_physmem_init_regions[INIT_PHYSMEM_REGIONS] __initdata_memblock; #endif +static seqcount_t memblock_seq; struct memblock memblock __initdata_memblock = { .memory.regions = memblock_memory_init_regions, .memory.cnt = 1, /* empty dummy entry */ @@ -241,8 +245,7 @@ * so we use WARN_ONCE() here to see the stack trace if * fail happens. */ - WARN_ONCE(1, "memblock: bottom-up allocation failed, " - "memory hotunplug may be affected\n"); + WARN_ONCE(1, "memblock: bottom-up allocation failed, memory hotunplug may be affected\n"); } return __memblock_find_range_top_down(start, end, size, align, nid, @@ -734,6 +737,7 @@ (unsigned long long)base + size - 1, (void *)_RET_IP_); + if (base < memblock.current_limit) kmemleak_free_part(__va(base), size); return memblock_remove_range(&memblock.reserved, base, size); } @@ -822,6 +826,27 @@ return memblock_setclr_flag(base, size, 1, MEMBLOCK_MIRROR); } +/** + * memblock_mark_nomap - Mark a memory region with flag MEMBLOCK_NOMAP. + * @base: the base phys addr of the region + * @size: the size of the region + * + * Return 0 on success, -errno on failure. + */ +int __init_memblock memblock_mark_nomap(phys_addr_t base, phys_addr_t size) +{ + return memblock_setclr_flag(base, size, 1, MEMBLOCK_NOMAP); +} + +/** + * memblock_clear_nomap - Clear a flag of MEMBLOCK_NOMAP memory region + * @base: the base phys addr of the region + * @size: the size of the region + */ +int __init_memblock memblock_clear_nomap(phys_addr_t base, phys_addr_t size) +{ + return memblock_setclr_flag(base, size, 0, MEMBLOCK_NOMAP); +} /** * __next_reserved_mem_region - next function for for_each_reserved_region() @@ -913,6 +938,10 @@ if ((flags & MEMBLOCK_MIRROR) && !memblock_is_mirror(m)) continue; + /* skip nomap memory unless we were asked for it explicitly */ + if (!(flags & MEMBLOCK_NOMAP) && memblock_is_nomap(m)) + continue; + if (!type_b) { if (out_start) *out_start = m_start; @@ -1022,6 +1051,10 @@ if ((flags & MEMBLOCK_MIRROR) && !memblock_is_mirror(m)) continue; + /* skip nomap memory unless we were asked for it explicitly */ + if (!(flags & MEMBLOCK_NOMAP) && memblock_is_nomap(m)) + continue; + if (!type_b) { if (out_start) *out_start = m_start; @@ -1151,6 +1184,7 @@ * The min_count is set to 0 so that memblock allocations are * never reported as leaks. */ + if (found < memblock.current_limit) kmemleak_alloc(__va(found), size, 0, 0); return found; } @@ -1491,7 +1525,7 @@ (phys_addr_t)ULLONG_MAX); } -static int __init_memblock memblock_search(struct memblock_type *type, phys_addr_t addr) +static int __init_memblock __memblock_search(struct memblock_type *type, phys_addr_t addr) { unsigned int left = 0, right = type->cnt; @@ -1509,6 +1543,19 @@ return -1; } +static int __init_memblock memblock_search(struct memblock_type *type, phys_addr_t addr) +{ + int ret; + unsigned long seq; + + do { + seq = raw_read_seqcount_begin(&memblock_seq); + ret = __memblock_search(type, addr); + } while (unlikely(read_seqcount_retry(&memblock_seq, seq))); + + return ret; +} + int __init memblock_is_reserved(phys_addr_t addr) { return memblock_search(&memblock.reserved, addr) != -1; @@ -1519,6 +1566,15 @@ return memblock_search(&memblock.memory, addr) != -1; } +int __init_memblock memblock_is_map_memory(phys_addr_t addr) +{ + int i = memblock_search(&memblock.memory, addr); + + if (i == -1) + return false; + return !memblock_is_nomap(&memblock.memory.regions[i]); +} + #ifdef CONFIG_HAVE_MEMBLOCK_NODE_MAP int __init_memblock memblock_search_pfn_nid(unsigned long pfn, unsigned long *start_pfn, unsigned long *end_pfn) @@ -1558,6 +1614,14 @@ memblock.memory.regions[idx].size) >= end; } +bool __init_memblock memblock_overlaps_memory(phys_addr_t base, + phys_addr_t size) +{ + memblock_cap_size(base, &size); + + return memblock_overlaps_region(&memblock.memory, base, size); +} + /** * memblock_is_region_reserved - check if a region intersects reserved memory * @base: base of region to check @@ -1674,6 +1738,37 @@ memblock_can_resize = 1; } +static unsigned long __init_memblock +memblock_resize_late(int begin, unsigned long flags) +{ + static int memblock_can_resize_old; + + if (begin) { + preempt_disable(); + local_irq_save(flags); + memblock_can_resize_old = memblock_can_resize; + memblock_can_resize = 0; + raw_write_seqcount_begin(&memblock_seq); + } else { + raw_write_seqcount_end(&memblock_seq); + memblock_can_resize = memblock_can_resize_old; + local_irq_restore(flags); + preempt_enable(); + } + + return flags; +} + +unsigned long __init_memblock memblock_region_resize_late_begin(void) +{ + return memblock_resize_late(1, 0); +} + +void __init_memblock memblock_region_resize_late_end(unsigned long flags) +{ + memblock_resize_late(0, flags); +} + static int __init early_memblock(char *p) { if (p && strstr(p, "debug")) diff -ruw linux-4.4.115/mm/memory.c linux-4.4.115-fbx/mm/memory.c --- linux-4.4.115/mm/memory.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/mm/memory.c 2019-10-29 09:26:25.705223357 +0100 @@ -2619,7 +2619,8 @@ } swap_free(entry); - if (vm_swap_full() || (vma->vm_flags & VM_LOCKED) || PageMlocked(page)) + if ((PageSwapCache(page) && vm_swap_full(page_swap_info(page))) || + (vma->vm_flags & VM_LOCKED) || PageMlocked(page)) try_to_free_swap(page); unlock_page(page); if (page != swapcache) { @@ -2833,7 +2834,7 @@ } static unsigned long fault_around_bytes __read_mostly = - rounddown_pow_of_two(65536); + rounddown_pow_of_two(4096); #ifdef CONFIG_DEBUG_FS static int fault_around_bytes_get(void *data, u64 *val) diff -ruw linux-4.4.115/mm/mempool.c linux-4.4.115-fbx/mm/mempool.c --- linux-4.4.115/mm/mempool.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/mm/mempool.c 2019-01-22 16:16:28.811294474 +0100 @@ -104,20 +104,16 @@ static void kasan_poison_element(mempool_t *pool, void *element) { - if (pool->alloc == mempool_alloc_slab) - kasan_slab_free(pool->pool_data, element); - if (pool->alloc == mempool_kmalloc) - kasan_kfree(element); + if (pool->alloc == mempool_alloc_slab || pool->alloc == mempool_kmalloc) + kasan_poison_kfree(element); if (pool->alloc == mempool_alloc_pages) kasan_free_pages(element, (unsigned long)pool->pool_data); } -static void kasan_unpoison_element(mempool_t *pool, void *element) +static void kasan_unpoison_element(mempool_t *pool, void *element, gfp_t flags) { - if (pool->alloc == mempool_alloc_slab) - kasan_slab_alloc(pool->pool_data, element); - if (pool->alloc == mempool_kmalloc) - kasan_krealloc(element, (size_t)pool->pool_data); + if (pool->alloc == mempool_alloc_slab || pool->alloc == mempool_kmalloc) + kasan_unpoison_slab(element); if (pool->alloc == mempool_alloc_pages) kasan_alloc_pages(element, (unsigned long)pool->pool_data); } @@ -130,12 +126,12 @@ pool->elements[pool->curr_nr++] = element; } -static void *remove_element(mempool_t *pool) +static void *remove_element(mempool_t *pool, gfp_t flags) { void *element = pool->elements[--pool->curr_nr]; BUG_ON(pool->curr_nr < 0); - kasan_unpoison_element(pool, element); + kasan_unpoison_element(pool, element, flags); check_element(pool, element); return element; } @@ -154,7 +150,7 @@ return; while (pool->curr_nr) { - void *element = remove_element(pool); + void *element = remove_element(pool, GFP_KERNEL); pool->free(element, pool->pool_data); } kfree(pool->elements); @@ -250,7 +246,7 @@ spin_lock_irqsave(&pool->lock, flags); if (new_min_nr <= pool->min_nr) { while (new_min_nr < pool->curr_nr) { - element = remove_element(pool); + element = remove_element(pool, GFP_KERNEL); spin_unlock_irqrestore(&pool->lock, flags); pool->free(element, pool->pool_data); spin_lock_irqsave(&pool->lock, flags); @@ -336,7 +332,7 @@ spin_lock_irqsave(&pool->lock, flags); if (likely(pool->curr_nr)) { - element = remove_element(pool); + element = remove_element(pool, gfp_temp); spin_unlock_irqrestore(&pool->lock, flags); /* paired with rmb in mempool_free(), read comment there */ smp_wmb(); diff -ruw linux-4.4.115/mm/migrate.c linux-4.4.115-fbx/mm/migrate.c --- linux-4.4.115/mm/migrate.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/mm/migrate.c 2019-10-29 09:26:25.709223396 +0100 @@ -31,6 +31,7 @@ #include #include #include +#include #include #include #include @@ -38,6 +39,7 @@ #include #include #include +#include #include #include @@ -73,6 +75,81 @@ return 0; } +bool isolate_movable_page(struct page *page, isolate_mode_t mode) +{ + struct address_space *mapping; + + /* + * Avoid burning cycles with pages that are yet under __free_pages(), + * or just got freed under us. + * + * In case we 'win' a race for a movable page being freed under us and + * raise its refcount preventing __free_pages() from doing its job + * the put_page() at the end of this block will take care of + * release this page, thus avoiding a nasty leakage. + */ + if (unlikely(!get_page_unless_zero(page))) + goto out; + + /* + * Check PageMovable before holding a PG_lock because page's owner + * assumes anybody doesn't touch PG_lock of newly allocated page + * so unconditionally grapping the lock ruins page's owner side. + */ + if (unlikely(!__PageMovable(page))) + goto out_putpage; + /* + * As movable pages are not isolated from LRU lists, concurrent + * compaction threads can race against page migration functions + * as well as race against the releasing a page. + * + * In order to avoid having an already isolated movable page + * being (wrongly) re-isolated while it is under migration, + * or to avoid attempting to isolate pages being released, + * lets be sure we have the page lock + * before proceeding with the movable page isolation steps. + */ + if (unlikely(!trylock_page(page))) + goto out_putpage; + + if (!PageMovable(page) || PageIsolated(page)) + goto out_no_isolated; + + mapping = page_mapping(page); + VM_BUG_ON_PAGE(!mapping, page); + + if (!mapping->a_ops->isolate_page(page, mode)) + goto out_no_isolated; + + /* Driver shouldn't use PG_isolated bit of page->flags */ + WARN_ON_ONCE(PageIsolated(page)); + __SetPageIsolated(page); + unlock_page(page); + + return true; + +out_no_isolated: + unlock_page(page); +out_putpage: + put_page(page); +out: + return false; +} + +/* It should be called on page which is PG_movable */ +void putback_movable_page(struct page *page) +{ + struct address_space *mapping; + + VM_BUG_ON_PAGE(!PageLocked(page), page); + VM_BUG_ON_PAGE(!PageMovable(page), page); + VM_BUG_ON_PAGE(!PageIsolated(page), page); + + mapping = page_mapping(page); + mapping->a_ops->putback_page(page); + __ClearPageIsolated(page); +} + /* * Put previously isolated pages back onto the appropriate lists * from where they were once taken off for compaction/migration. @@ -94,12 +171,25 @@ list_del(&page->lru); dec_zone_page_state(page, NR_ISOLATED_ANON + page_is_file_cache(page)); - if (unlikely(isolated_balloon_page(page))) - balloon_page_putback(page); + /* + * We isolated non-lru movable page so here we can use + * __PageMovable because LRU page's mapping cannot have + * PAGE_MAPPING_MOVABLE. + */ + if (unlikely(__PageMovable(page))) { + VM_BUG_ON_PAGE(!PageIsolated(page), page); + lock_page(page); + if (PageMovable(page)) + putback_movable_page(page); else + __ClearPageIsolated(page); + unlock_page(page); + put_page(page); + } else { putback_lru_page(page); } } +} /* * Restore a potential migration pte to a working pte entry @@ -580,6 +670,8 @@ */ if (PageWriteback(newpage)) end_page_writeback(newpage); + + copy_page_owner(page, newpage); } EXPORT_SYMBOL(migrate_page_copy); @@ -588,7 +680,7 @@ ***********************************************************/ /* - * Common logic to directly migrate a single page suitable for + * Common logic to directly migrate a single LRU page suitable for * pages that do not use PagePrivate/PagePrivate2. * * Pages are locked upon entry and exit. @@ -751,24 +843,47 @@ enum migrate_mode mode) { struct address_space *mapping; - int rc; + int rc = -EAGAIN; + bool is_lru = !__PageMovable(page); VM_BUG_ON_PAGE(!PageLocked(page), page); VM_BUG_ON_PAGE(!PageLocked(newpage), newpage); mapping = page_mapping(page); + + if (likely(is_lru)) { if (!mapping) rc = migrate_page(mapping, newpage, page, mode); else if (mapping->a_ops->migratepage) /* - * Most pages have a mapping and most filesystems provide a - * migratepage callback. Anonymous pages are part of swap - * space which also has its own migratepage callback. This - * is the most common path for page migration. + * Most pages have a mapping and most filesystems + * provide a migratepage callback. Anonymous pages + * are part of swap space which also has its own + * migratepage callback. This is the most common path + * for page migration. */ - rc = mapping->a_ops->migratepage(mapping, newpage, page, mode); + rc = mapping->a_ops->migratepage(mapping, newpage, + page, mode); else - rc = fallback_migrate_page(mapping, newpage, page, mode); + rc = fallback_migrate_page(mapping, newpage, + page, mode); + } else { + /* + * In case of non-lru page, it could be released after + * isolation step. In that case, we shouldn't try migration. + */ + VM_BUG_ON_PAGE(!PageIsolated(page), page); + if (!PageMovable(page)) { + rc = MIGRATEPAGE_SUCCESS; + __ClearPageIsolated(page); + goto out; + } + + rc = mapping->a_ops->migratepage(mapping, newpage, + page, mode); + WARN_ON_ONCE(rc == MIGRATEPAGE_SUCCESS && + !PageIsolated(page)); + } /* * When successful, old pagecache page->mapping must be cleared before @@ -776,9 +891,25 @@ */ if (rc == MIGRATEPAGE_SUCCESS) { set_page_memcg(page, NULL); - if (!PageAnon(page)) + if (__PageMovable(page)) { + VM_BUG_ON_PAGE(!PageIsolated(page), page); + + /* + * We clear PG_movable under page_lock so any compactor + * cannot try to migrate this page. + */ + __ClearPageIsolated(page); + } + + /* + * Anonymous and movable page->mapping will be cleard by + * free_pages_prepare so don't reset it here for keeping + * the type to work PageAnon, for example. + */ + if (!PageMappingFlags(page)) page->mapping = NULL; } +out: return rc; } @@ -788,6 +919,7 @@ int rc = -EAGAIN; int page_was_mapped = 0; struct anon_vma *anon_vma = NULL; + bool is_lru = !__PageMovable(page); if (!trylock_page(page)) { if (!force || mode == MIGRATE_ASYNC) @@ -856,15 +988,8 @@ if (unlikely(!trylock_page(newpage))) goto out_unlock; - if (unlikely(isolated_balloon_page(page))) { - /* - * A ballooned page does not need any special attention from - * physical to virtual reverse mapping procedures. - * Skip any attempt to unmap PTEs or to remap swap cache, - * in order to avoid burning cycles at rmap level, and perform - * the page migration right away (proteced by page lock). - */ - rc = balloon_page_migrate(newpage, page, mode); + if (unlikely(!is_lru)) { + rc = move_to_new_page(newpage, page, mode); goto out_unlock_both; } @@ -891,7 +1016,7 @@ VM_BUG_ON_PAGE(PageAnon(page) && !PageKsm(page) && !anon_vma, page); try_to_unmap(page, - TTU_MIGRATION|TTU_IGNORE_MLOCK|TTU_IGNORE_ACCESS); + TTU_MIGRATION|TTU_IGNORE_MLOCK|TTU_IGNORE_ACCESS, NULL); page_was_mapped = 1; } @@ -910,6 +1035,19 @@ put_anon_vma(anon_vma); unlock_page(page); out: + /* + * If migration is successful, decrease refcount of the newpage + * which will not free the page because new page owner increased + * refcounter. As well, if it is LRU page, add the page to LRU + * list in here. + */ + if (rc == MIGRATEPAGE_SUCCESS) { + if (unlikely(__PageMovable(newpage))) + put_page(newpage); + else + putback_lru_page(newpage); + } + return rc; } @@ -943,6 +1081,18 @@ if (page_count(page) == 1) { /* page was freed from under us. So we are done. */ + ClearPageActive(page); + ClearPageUnevictable(page); + if (unlikely(__PageMovable(page))) { + lock_page(page); + if (!PageMovable(page)) + __ClearPageIsolated(page); + unlock_page(page); + } + if (put_new_page) + put_new_page(newpage, private); + else + put_page(newpage); goto out; } @@ -951,8 +1101,9 @@ goto out; rc = __unmap_and_move(page, newpage, force, mode); - if (rc == MIGRATEPAGE_SUCCESS) - put_new_page = NULL; + if (rc == MIGRATEPAGE_SUCCESS) { + set_page_owner_migrate_reason(newpage, reason); + } out: if (rc != -EAGAIN) { @@ -965,33 +1116,45 @@ list_del(&page->lru); dec_zone_page_state(page, NR_ISOLATED_ANON + page_is_file_cache(page)); - /* Soft-offlined page shouldn't go through lru cache list */ - if (reason == MR_MEMORY_FAILURE && rc == MIGRATEPAGE_SUCCESS) { + } + /* - * With this release, we free successfully migrated - * page and set PG_HWPoison on just freed page - * intentionally. Although it's rather weird, it's how - * HWPoison flag works at the moment. + * If migration is successful, releases reference grabbed during + * isolation. Otherwise, restore the page to right list unless + * we want to retry. */ + if (rc == MIGRATEPAGE_SUCCESS) { put_page(page); + if (reason == MR_MEMORY_FAILURE) { + /* + * Set PG_HWPoison on just freed page + * intentionally. Although it's rather weird, + * it's how HWPoison flag works at the moment. + */ if (!test_set_page_hwpoison(page)) num_poisoned_pages_inc(); - } else + } + } else { + if (rc != -EAGAIN) { + if (likely(!__PageMovable(page))) { putback_lru_page(page); + goto put_new; } - /* - * If migration was not successful and there's a freeing callback, use - * it. Otherwise, putback_lru_page() will drop the reference grabbed - * during isolation. - */ + lock_page(page); + if (PageMovable(page)) + putback_movable_page(page); + else + __ClearPageIsolated(page); + unlock_page(page); + put_page(page); + } +put_new: if (put_new_page) put_new_page(newpage, private); - else if (unlikely(__is_movable_balloon_page(newpage))) { - /* drop our reference, page already in the balloon */ + else put_page(newpage); - } else - putback_lru_page(newpage); + } if (result) { if (rc) @@ -1023,7 +1186,7 @@ static int unmap_and_move_huge_page(new_page_t get_new_page, free_page_t put_new_page, unsigned long private, struct page *hpage, int force, - enum migrate_mode mode) + enum migrate_mode mode, int reason) { int rc = -EAGAIN; int *result = NULL; @@ -1061,7 +1224,7 @@ if (page_mapped(hpage)) { try_to_unmap(hpage, - TTU_MIGRATION|TTU_IGNORE_MLOCK|TTU_IGNORE_ACCESS); + TTU_MIGRATION|TTU_IGNORE_MLOCK|TTU_IGNORE_ACCESS, NULL); page_was_mapped = 1; } @@ -1081,6 +1244,7 @@ if (rc == MIGRATEPAGE_SUCCESS) { hugetlb_cgroup_migrate(hpage, new_hpage); put_new_page = NULL; + set_page_owner_migrate_reason(new_hpage, reason); } unlock_page(hpage); @@ -1141,6 +1305,8 @@ int swapwrite = current->flags & PF_SWAPWRITE; int rc; + trace_mm_migrate_pages_start(mode, reason); + if (!swapwrite) current->flags |= PF_SWAPWRITE; @@ -1153,7 +1319,7 @@ if (PageHuge(page)) rc = unmap_and_move_huge_page(get_new_page, put_new_page, private, page, - pass > 2, mode); + pass > 2, mode, reason); else rc = unmap_and_move(get_new_page, put_new_page, private, page, pass > 2, mode, @@ -1837,6 +2003,7 @@ set_page_memcg(new_page, page_memcg(page)); set_page_memcg(page, NULL); page_remove_rmap(page); + set_page_owner_migrate_reason(new_page, MR_NUMA_MISPLACED); spin_unlock(ptl); mmu_notifier_invalidate_range_end(mm, mmun_start, mmun_end); diff -ruw linux-4.4.115/mm/mlock.c linux-4.4.115-fbx/mm/mlock.c --- linux-4.4.115/mm/mlock.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/mm/mlock.c 2019-10-29 09:26:25.713223435 +0100 @@ -513,7 +513,7 @@ pgoff = vma->vm_pgoff + ((start - vma->vm_start) >> PAGE_SHIFT); *prev = vma_merge(mm, *prev, start, end, newflags, vma->anon_vma, vma->vm_file, pgoff, vma_policy(vma), - vma->vm_userfaultfd_ctx); + vma->vm_userfaultfd_ctx, vma_get_anon_name(vma)); if (*prev) { vma = *prev; goto success; diff -ruw linux-4.4.115/mm/mmap.c linux-4.4.115-fbx/mm/mmap.c --- linux-4.4.115/mm/mmap.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/mm/mmap.c 2019-10-29 09:26:25.713223435 +0100 @@ -48,6 +48,10 @@ #include #include +#ifdef CONFIG_MSM_APP_SETTINGS +#include +#endif + #include "internal.h" #ifndef arch_mmap_check @@ -58,6 +62,18 @@ #define arch_rebalance_pgtables(addr, len) (addr) #endif +#ifdef CONFIG_HAVE_ARCH_MMAP_RND_BITS +const int mmap_rnd_bits_min = CONFIG_ARCH_MMAP_RND_BITS_MIN; +const int mmap_rnd_bits_max = CONFIG_ARCH_MMAP_RND_BITS_MAX; +int mmap_rnd_bits __read_mostly = CONFIG_ARCH_MMAP_RND_BITS; +#endif +#ifdef CONFIG_HAVE_ARCH_MMAP_RND_COMPAT_BITS +const int mmap_rnd_compat_bits_min = CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN; +const int mmap_rnd_compat_bits_max = CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX; +int mmap_rnd_compat_bits __read_mostly = CONFIG_ARCH_MMAP_RND_COMPAT_BITS; +#endif + + static void unmap_region(struct mm_struct *mm, struct vm_area_struct *vma, struct vm_area_struct *prev, unsigned long start, unsigned long end); @@ -190,6 +206,13 @@ free += global_page_state(NR_SLAB_RECLAIMABLE); /* + * Part of the kernel memory, which can be released + * under memory pressure. + */ + free += global_page_state( + NR_INDIRECTLY_RECLAIMABLE_BYTES) >> PAGE_SHIFT; + + /* * Leave reserved pages. The pages are not for anonymous pages. */ if (free <= totalreserve_pages) @@ -939,7 +962,8 @@ */ static inline int is_mergeable_vma(struct vm_area_struct *vma, struct file *file, unsigned long vm_flags, - struct vm_userfaultfd_ctx vm_userfaultfd_ctx) + struct vm_userfaultfd_ctx vm_userfaultfd_ctx, + const char __user *anon_name) { /* * VM_SOFTDIRTY should not prevent from VMA merging, if we @@ -957,6 +981,8 @@ return 0; if (!is_mergeable_vm_userfaultfd_ctx(vma, vm_userfaultfd_ctx)) return 0; + if (vma_get_anon_name(vma) != anon_name) + return 0; return 1; } @@ -989,9 +1015,10 @@ can_vma_merge_before(struct vm_area_struct *vma, unsigned long vm_flags, struct anon_vma *anon_vma, struct file *file, pgoff_t vm_pgoff, - struct vm_userfaultfd_ctx vm_userfaultfd_ctx) + struct vm_userfaultfd_ctx vm_userfaultfd_ctx, + const char __user *anon_name) { - if (is_mergeable_vma(vma, file, vm_flags, vm_userfaultfd_ctx) && + if (is_mergeable_vma(vma, file, vm_flags, vm_userfaultfd_ctx, anon_name) && is_mergeable_anon_vma(anon_vma, vma->anon_vma, vma)) { if (vma->vm_pgoff == vm_pgoff) return 1; @@ -1010,9 +1037,10 @@ can_vma_merge_after(struct vm_area_struct *vma, unsigned long vm_flags, struct anon_vma *anon_vma, struct file *file, pgoff_t vm_pgoff, - struct vm_userfaultfd_ctx vm_userfaultfd_ctx) + struct vm_userfaultfd_ctx vm_userfaultfd_ctx, + const char __user *anon_name) { - if (is_mergeable_vma(vma, file, vm_flags, vm_userfaultfd_ctx) && + if (is_mergeable_vma(vma, file, vm_flags, vm_userfaultfd_ctx, anon_name) && is_mergeable_anon_vma(anon_vma, vma->anon_vma, vma)) { pgoff_t vm_pglen; vm_pglen = vma_pages(vma); @@ -1023,9 +1051,9 @@ } /* - * Given a mapping request (addr,end,vm_flags,file,pgoff), figure out - * whether that can be merged with its predecessor or its successor. - * Or both (it neatly fills a hole). + * Given a mapping request (addr,end,vm_flags,file,pgoff,anon_name), + * figure out whether that can be merged with its predecessor or its + * successor. Or both (it neatly fills a hole). * * In most cases - when called for mmap, brk or mremap - [addr,end) is * certain not to be mapped by the time vma_merge is called; but when @@ -1056,7 +1084,8 @@ unsigned long end, unsigned long vm_flags, struct anon_vma *anon_vma, struct file *file, pgoff_t pgoff, struct mempolicy *policy, - struct vm_userfaultfd_ctx vm_userfaultfd_ctx) + struct vm_userfaultfd_ctx vm_userfaultfd_ctx, + const char __user *anon_name) { pgoff_t pglen = (end - addr) >> PAGE_SHIFT; struct vm_area_struct *area, *next; @@ -1084,7 +1113,8 @@ mpol_equal(vma_policy(prev), policy) && can_vma_merge_after(prev, vm_flags, anon_vma, file, pgoff, - vm_userfaultfd_ctx)) { + vm_userfaultfd_ctx, + anon_name)) { /* * OK, it can. Can we now merge in the successor as well? */ @@ -1093,7 +1123,8 @@ can_vma_merge_before(next, vm_flags, anon_vma, file, pgoff+pglen, - vm_userfaultfd_ctx) && + vm_userfaultfd_ctx, + anon_name) && is_mergeable_anon_vma(prev->anon_vma, next->anon_vma, NULL)) { /* cases 1, 6 */ @@ -1115,7 +1146,8 @@ mpol_equal(policy, vma_policy(next)) && can_vma_merge_before(next, vm_flags, anon_vma, file, pgoff+pglen, - vm_userfaultfd_ctx)) { + vm_userfaultfd_ctx, + anon_name)) { if (prev && addr < prev->vm_end) /* case 4 */ err = vma_adjust(prev, prev->vm_start, addr, prev->vm_pgoff, NULL); @@ -1290,6 +1322,11 @@ if (!len) return -EINVAL; +#ifdef CONFIG_MSM_APP_SETTINGS + if (use_app_setting) + apply_app_setting_bit(file); +#endif + /* * Does the application expect PROT_READ to imply PROT_EXEC? * @@ -1599,7 +1636,7 @@ * Can we just expand an old mapping? */ vma = vma_merge(mm, prev, addr, addr + len, vm_flags, - NULL, file, pgoff, NULL, NULL_VM_UFFD_CTX); + NULL, file, pgoff, NULL, NULL_VM_UFFD_CTX, NULL); if (vma) goto out; @@ -2649,6 +2686,7 @@ return 0; } +EXPORT_SYMBOL(do_munmap); int vm_munmap(unsigned long start, size_t len) { @@ -2682,8 +2720,7 @@ unsigned long ret = -EINVAL; struct file *file; - pr_warn_once("%s (%d) uses deprecated remap_file_pages() syscall. " - "See Documentation/vm/remap_file_pages.txt.\n", + pr_warn_once("%s (%d) uses deprecated remap_file_pages() syscall. See Documentation/vm/remap_file_pages.txt.\n", current->comm, current->pid); if (prot) @@ -2826,7 +2863,7 @@ /* Can we just expand an old private anonymous mapping? */ vma = vma_merge(mm, prev, addr, addr + len, flags, - NULL, NULL, pgoff, NULL, NULL_VM_UFFD_CTX); + NULL, NULL, pgoff, NULL, NULL_VM_UFFD_CTX, NULL); if (vma) goto out; @@ -2984,7 +3021,7 @@ return NULL; /* should never get here */ new_vma = vma_merge(mm, prev, addr, addr + len, vma->vm_flags, vma->anon_vma, vma->vm_file, pgoff, vma_policy(vma), - vma->vm_userfaultfd_ctx); + vma->vm_userfaultfd_ctx, vma_get_anon_name(vma)); if (new_vma) { /* * Source vma may have been merged into new_vma diff -ruw linux-4.4.115/mm/mprotect.c linux-4.4.115-fbx/mm/mprotect.c --- linux-4.4.115/mm/mprotect.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/mm/mprotect.c 2019-10-29 09:26:25.713223435 +0100 @@ -294,7 +294,7 @@ pgoff = vma->vm_pgoff + ((start - vma->vm_start) >> PAGE_SHIFT); *pprev = vma_merge(mm, *pprev, start, end, newflags, vma->anon_vma, vma->vm_file, pgoff, vma_policy(vma), - vma->vm_userfaultfd_ctx); + vma->vm_userfaultfd_ctx, vma_get_anon_name(vma)); if (*pprev) { vma = *pprev; goto success; diff -ruw linux-4.4.115/mm/nobootmem.c linux-4.4.115-fbx/mm/nobootmem.c --- linux-4.4.115/mm/nobootmem.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/mm/nobootmem.c 2019-01-22 16:16:28.815294510 +0100 @@ -76,7 +76,7 @@ * down, but we are still initializing the system. Pages are given directly * to the page allocator, no bootmem metadata is updated because it is gone. */ -void __init free_bootmem_late(unsigned long addr, unsigned long size) +void free_bootmem_late(unsigned long addr, unsigned long size) { unsigned long cursor, end; diff -ruw linux-4.4.115/mm/oom_kill.c linux-4.4.115-fbx/mm/oom_kill.c --- linux-4.4.115/mm/oom_kill.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/mm/oom_kill.c 2019-10-29 09:26:25.717223474 +0100 @@ -350,7 +350,7 @@ * State information includes task's pid, uid, tgid, vm size, rss, nr_ptes, * swapents, oom_score_adj value, and name. */ -static void dump_tasks(struct mem_cgroup *memcg, const nodemask_t *nodemask) +void dump_tasks(struct mem_cgroup *memcg, const nodemask_t *nodemask) { struct task_struct *p; struct task_struct *task; @@ -386,8 +386,7 @@ static void dump_header(struct oom_control *oc, struct task_struct *p, struct mem_cgroup *memcg) { - pr_warning("%s invoked oom-killer: gfp_mask=0x%x, order=%d, " - "oom_score_adj=%hd\n", + pr_warning("%s invoked oom-killer: gfp_mask=0x%x, order=%d, oom_score_adj=%hd\n", current->comm, oc->gfp_mask, oc->order, current->signal->oom_score_adj); cpuset_print_current_mems_allowed(); diff -ruw linux-4.4.115/mm/page_alloc.c linux-4.4.115-fbx/mm/page_alloc.c --- linux-4.4.115/mm/page_alloc.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/mm/page_alloc.c 2019-10-29 09:26:25.725223553 +0100 @@ -114,13 +114,6 @@ unsigned long totalram_pages __read_mostly; unsigned long totalreserve_pages __read_mostly; unsigned long totalcma_pages __read_mostly; -/* - * When calculating the number of globally allowed dirty pages, there - * is a certain number of per-zone reserves that should not be - * considered dirtyable memory. This is the sum of those reserves - * over all existing zones that contribute dirtyable memory. - */ -unsigned long dirty_balance_reserve __read_mostly; int percpu_pagelist_fraction; gfp_t gfp_allowed_mask __read_mostly = GFP_BOOT_MASK; @@ -230,6 +223,20 @@ }; static void free_compound_page(struct page *page); + +char * const migratetype_names[MIGRATE_TYPES] = { + "Unmovable", + "Movable", + "Reclaimable", +#ifdef CONFIG_CMA + "CMA", +#endif + "HighAtomic", +#ifdef CONFIG_MEMORY_ISOLATION + "Isolate", +#endif +}; + compound_page_dtor * const compound_page_dtors[] = { NULL, free_compound_page, @@ -238,9 +245,21 @@ #endif }; +/* + * Try to keep at least this much lowmem free. Do not allow normal + * allocations below this point, only high priority ones. Automatically + * tuned according to the amount of memory in the system. + */ int min_free_kbytes = 1024; int user_min_free_kbytes = -1; +/* + * Extra memory for the system to try freeing. Used to temporarily + * free memory, to make space for new workloads. Anyone can allocate + * down to the min watermarks controlled by min_free_kbytes above. + */ +int extra_free_kbytes = 0; + static unsigned long __meminitdata nr_kernel_pages; static unsigned long __meminitdata nr_all_pages; static unsigned long __meminitdata dma_reserve; @@ -463,6 +482,7 @@ printk(KERN_ALERT "BUG: Bad page state in process %s pfn:%05lx\n", current->comm, page_to_pfn(page)); dump_page_badflags(page, reason, bad_flags); + dump_page_owner(page); print_modules(); dump_stack(); @@ -509,7 +529,8 @@ #ifdef CONFIG_DEBUG_PAGEALLOC unsigned int _debug_guardpage_minorder; -bool _debug_pagealloc_enabled __read_mostly; +bool _debug_pagealloc_enabled __read_mostly + = IS_ENABLED(CONFIG_DEBUG_PAGEALLOC_ENABLE_DEFAULT); bool _debug_guardpage_enabled __read_mostly; static int __init early_debug_pagealloc(char *buf) @@ -520,6 +541,9 @@ if (strcmp(buf, "on") == 0) _debug_pagealloc_enabled = true; + if (strcmp(buf, "off") == 0) + _debug_pagealloc_enabled = false; + return 0; } early_param("debug_pagealloc", early_debug_pagealloc); @@ -1016,9 +1040,8 @@ trace_mm_page_free(page, order); kmemcheck_free_shadow(page, order); - kasan_free_pages(page, order); - if (PageAnon(page)) + if (PageMappingFlags(page)) page->mapping = NULL; bad += free_pages_check(page); for (i = 1; i < (1 << order); i++) { @@ -1038,7 +1061,9 @@ PAGE_SIZE << order); } arch_free_page(page, order); + kernel_poison_pages(page, 1 << order, 0); kernel_map_pages(page, 1 << order, 0); + kasan_free_pages(page, order); return true; } @@ -1059,8 +1084,7 @@ local_irq_restore(flags); } -static void __init __free_pages_boot_core(struct page *page, - unsigned long pfn, unsigned int order) +static void __init __free_pages_boot_core(struct page *page, unsigned long pfn, unsigned int order) { unsigned int nr_pages = 1 << order; struct page *p = page; @@ -1132,7 +1156,7 @@ #endif -void __init __free_pages_bootmem(struct page *page, unsigned long pfn, +void __free_pages_bootmem(struct page *page, unsigned long pfn, unsigned int order) { if (early_page_uninitialised(pfn)) @@ -1310,6 +1334,11 @@ #endif /* CONFIG_DEFERRED_STRUCT_PAGE_INIT */ #ifdef CONFIG_CMA +bool is_cma_pageblock(struct page *page) +{ + return get_pageblock_migratetype(page) == MIGRATE_CMA; +} + /* Free whole pageblock and set its migration type to MIGRATE_CMA. */ void __init init_cma_reserved_pageblock(struct page *page) { @@ -1417,6 +1446,25 @@ return 0; } +static inline bool free_pages_prezeroed(void) +{ + return IS_ENABLED(CONFIG_PAGE_POISONING_ZERO) && + page_poisoning_enabled(); +} + +inline void post_alloc_hook(struct page *page, unsigned int order, + gfp_t gfp_flags) +{ + set_page_private(page, 0); + set_page_refcounted(page); + + kasan_alloc_pages(page, order); + arch_alloc_page(page, order); + kernel_map_pages(page, 1 << order, 1); + kernel_poison_pages(page, 1 << order, 1); + set_page_owner(page, order, gfp_flags); +} + static int prep_new_page(struct page *page, unsigned int order, gfp_t gfp_flags, int alloc_flags) { @@ -1428,22 +1476,15 @@ return 1; } - set_page_private(page, 0); - set_page_refcounted(page); + post_alloc_hook(page, order, gfp_flags); - arch_alloc_page(page, order); - kernel_map_pages(page, 1 << order, 1); - kasan_alloc_pages(page, order); - - if (gfp_flags & __GFP_ZERO) + if (!free_pages_prezeroed() && (gfp_flags & __GFP_ZERO)) for (i = 0; i < (1 << order); i++) clear_highpage(page + i); if (order && (gfp_flags & __GFP_COMP)) prep_compound_page(page, order); - set_page_owner(page, order, gfp_flags); - /* * page is set pfmemalloc when ALLOC_NO_WATERMARKS was necessary to * allocate the page. The expectation is that the caller is taking @@ -1506,6 +1547,11 @@ #endif }; +int *get_migratetype_fallbacks(int mtype) +{ + return fallbacks[mtype]; +} + #ifdef CONFIG_CMA static struct page *__rmqueue_cma_fallback(struct zone *zone, unsigned int order) @@ -1823,7 +1869,8 @@ page = list_entry(area->free_list[fallback_mt].next, struct page, lru); - if (can_steal) + if (can_steal && + get_pageblock_migratetype(page) != MIGRATE_HIGHATOMIC) steal_suitable_fallback(zone, page, start_migratetype); /* Remove the page from the freelists */ @@ -1862,10 +1909,6 @@ page = __rmqueue_smallest(zone, order, migratetype); if (unlikely(!page)) { - if (migratetype == MIGRATE_MOVABLE) - page = __rmqueue_cma_fallback(zone, order); - - if (!page) page = __rmqueue_fallback(zone, order, migratetype); } @@ -1873,6 +1916,23 @@ return page; } +#ifdef CONFIG_CMA +static struct page *__rmqueue_cma(struct zone *zone, unsigned int order) +{ + struct page *page = 0; + if (IS_ENABLED(CONFIG_CMA)) + if (!zone->cma_alloc) + page = __rmqueue_cma_fallback(zone, order); + trace_mm_page_alloc_zone_locked(page, order, MIGRATE_CMA); + return page; +} +#else +static inline struct page *__rmqueue_cma(struct zone *zone, unsigned int order) +{ + return NULL; +} +#endif + /* * Obtain a specified number of elements from the buddy allocator, all under * a single hold of the lock, for efficiency. Add them to the supplied list. @@ -1886,7 +1946,17 @@ spin_lock(&zone->lock); for (i = 0; i < count; ++i) { - struct page *page = __rmqueue(zone, order, migratetype, 0); + struct page *page; + + /* + * If migrate type CMA is being requested only try to + * satisfy the request with CMA pages to try and increase + * CMA utlization. + */ + if (is_migrate_cma(migratetype)) + page = __rmqueue_cma(zone, order); + else + page = __rmqueue(zone, order, migratetype, 0); if (unlikely(page == NULL)) break; @@ -1913,6 +1983,28 @@ return i; } +/* + * Return the pcp list that corresponds to the migrate type if that list isn't + * empty. + * If the list is empty return NULL. + */ +static struct list_head *get_populated_pcp_list(struct zone *zone, + unsigned int order, struct per_cpu_pages *pcp, + int migratetype, int cold) +{ + struct list_head *list = &pcp->lists[migratetype]; + + if (list_empty(list)) { + pcp->count += rmqueue_bulk(zone, order, + pcp->batch, list, + migratetype, cold); + + if (list_empty(list)) + list = NULL; + } + return list; +} + #ifdef CONFIG_NUMA /* * Called from the vmstat counter updater to drain pagesets of this @@ -2160,7 +2252,6 @@ void split_page(struct page *page, unsigned int order) { int i; - gfp_t gfp_mask; VM_BUG_ON_PAGE(PageCompound(page), page); VM_BUG_ON_PAGE(!page_count(page), page); @@ -2174,12 +2265,9 @@ split_page(virt_to_page(page[0].shadow), order); #endif - gfp_mask = get_page_owner_gfp(page); - set_page_owner(page, 0, gfp_mask); - for (i = 1; i < (1 << order); i++) { + for (i = 1; i < (1 << order); i++) set_page_refcounted(page + i); - set_page_owner(page + i, 0, gfp_mask); - } + split_page_owner(page, order); } EXPORT_SYMBOL_GPL(split_page); @@ -2197,7 +2285,8 @@ if (!is_migrate_isolate(mt)) { /* Obey watermarks as if the page was being allocated */ watermark = low_wmark_pages(zone) + (1 << order); - if (!zone_watermark_ok(zone, 0, watermark, 0, 0)) + if (!is_migrate_cma(mt) && + !zone_watermark_ok(zone, 0, watermark, 0, 0)) return 0; __mod_zone_freepage_state(zone, -(1UL << order), mt); @@ -2208,14 +2297,13 @@ zone->free_area[order].nr_free--; rmv_page_order(page); - set_page_owner(page, order, __GFP_MOVABLE); - /* Set the pageblock if the isolated page is at least a pageblock */ if (order >= pageblock_order - 1) { struct page *endpage = page + (1 << order) - 1; for (; page < endpage; page += pageblock_nr_pages) { int mt = get_pageblock_migratetype(page); - if (!is_migrate_isolate(mt) && !is_migrate_cma(mt)) + if (!is_migrate_isolate(mt) && !is_migrate_cma(mt) + && mt != MIGRATE_HIGHATOMIC) set_pageblock_migratetype(page, MIGRATE_MOVABLE); } @@ -2226,33 +2314,6 @@ } /* - * Similar to split_page except the page is already free. As this is only - * being used for migration, the migratetype of the block also changes. - * As this is called with interrupts disabled, the caller is responsible - * for calling arch_alloc_page() and kernel_map_page() after interrupts - * are enabled. - * - * Note: this is probably too low level an operation for use in drivers. - * Please consult with lkml before using this in your driver. - */ -int split_free_page(struct page *page) -{ - unsigned int order; - int nr_pages; - - order = page_order(page); - - nr_pages = __isolate_free_page(page, order); - if (!nr_pages) - return 0; - - /* Split into individual pages */ - set_page_refcounted(page); - split_page(page, order); - return nr_pages; -} - -/* * Allocate a page from the given zone. Use pcplists for order-0 allocations. */ static inline @@ -2261,21 +2322,32 @@ gfp_t gfp_flags, int alloc_flags, int migratetype) { unsigned long flags; - struct page *page; + struct page *page = NULL; bool cold = ((gfp_flags & __GFP_COLD) != 0); if (likely(order == 0)) { struct per_cpu_pages *pcp; - struct list_head *list; + struct list_head *list = NULL; local_irq_save(flags); pcp = &this_cpu_ptr(zone->pageset)->pcp; - list = &pcp->lists[migratetype]; - if (list_empty(list)) { - pcp->count += rmqueue_bulk(zone, 0, - pcp->batch, list, + + /* First try to get CMA pages */ + if (migratetype == MIGRATE_MOVABLE && + gfp_flags & __GFP_CMA) { + list = get_populated_pcp_list(zone, 0, pcp, + get_cma_migrate_type(), cold); + } + + if (list == NULL) { + /* + * Either CMA is not suitable or there are no free CMA + * pages. + */ + list = get_populated_pcp_list(zone, 0, pcp, migratetype, cold); - if (unlikely(list_empty(list))) + if (unlikely(list == NULL) || + unlikely(list_empty(list))) goto failed; } @@ -2308,8 +2380,13 @@ if (page) trace_mm_page_alloc_zone_locked(page, order, migratetype); } + if (!page && migratetype == MIGRATE_MOVABLE && + gfp_flags & __GFP_CMA) + page = __rmqueue_cma(zone, order); + if (!page) page = __rmqueue(zone, order, migratetype, gfp_flags); + spin_unlock(&zone->lock); if (!page) goto failed; @@ -2469,6 +2546,14 @@ continue; for (mt = 0; mt < MIGRATE_PCPTYPES; mt++) { +#ifdef CONFIG_CMA + /* + * Note that this check is needed only + * when MIGRATE_CMA < MIGRATE_PCPTYPES. + */ + if (mt == MIGRATE_CMA) + continue; +#endif if (!list_empty(&area->free_list[mt])) return true; } @@ -3985,8 +4070,7 @@ user_zonelist_order = ZONELIST_ORDER_ZONE; } else { printk(KERN_WARNING - "Ignoring invalid numa_zonelist_order value: " - "%s\n", s); + "Ignoring invalid numa_zonelist_order value: %s\n", s); return -EINVAL; } return 0; @@ -4451,8 +4535,7 @@ else page_group_by_mobility_disabled = 0; - pr_info("Built %i zonelists in %s order, mobility grouping %s. " - "Total pages: %ld\n", + pr_info("Built %i zonelists in %s order, mobility grouping %s. Total pages: %ld\n", nr_online_nodes, zonelist_order_name[current_zonelist_order], page_group_by_mobility_disabled ? "off" : "on", @@ -5256,6 +5339,9 @@ #endif init_waitqueue_head(&pgdat->kswapd_wait); init_waitqueue_head(&pgdat->pfmemalloc_wait); +#ifdef CONFIG_COMPACTION + init_waitqueue_head(&pgdat->kcompactd_wait); +#endif pgdat_page_ext_init(pgdat); for (j = 0; j < MAX_NR_ZONES; j++) { @@ -5927,14 +6013,13 @@ #undef adj_init_size - pr_info("Memory: %luK/%luK available " - "(%luK kernel code, %luK rwdata, %luK rodata, " - "%luK init, %luK bss, %luK reserved, %luK cma-reserved" + pr_info("Memory: %luK/%luK available (%luK kernel code, %luK rwdata, %luK rodata, %luK init, %luK bss, %luK reserved, %luK cma-reserved" #ifdef CONFIG_HIGHMEM ", %luK highmem" #endif "%s%s)\n", - nr_free_pages() << (PAGE_SHIFT-10), physpages << (PAGE_SHIFT-10), + nr_free_pages() << (PAGE_SHIFT - 10), + physpages << (PAGE_SHIFT - 10), codesize >> 10, datasize >> 10, rosize >> 10, (init_data_size + init_code_size) >> 10, bss_size >> 10, (physpages - totalram_pages - totalcma_pages) << (PAGE_SHIFT-10), @@ -6027,20 +6112,12 @@ if (max > zone->managed_pages) max = zone->managed_pages; + + zone->totalreserve_pages = max; + reserve_pages += max; - /* - * Lowmem reserves are not available to - * GFP_HIGHUSER page cache allocations and - * kswapd tries to balance zones to their high - * watermark. As a result, neither should be - * regarded as dirtyable memory, to prevent a - * situation where reclaim has to clean pages - * in order to balance the zones. - */ - zone->dirty_balance_reserve = max; } } - dirty_balance_reserve = reserve_pages; totalreserve_pages = reserve_pages; } @@ -6086,6 +6163,7 @@ static void __setup_per_zone_wmarks(void) { unsigned long pages_min = min_free_kbytes >> (PAGE_SHIFT - 10); + unsigned long pages_low = extra_free_kbytes >> (PAGE_SHIFT - 10); unsigned long lowmem_pages = 0; struct zone *zone; unsigned long flags; @@ -6097,11 +6175,14 @@ } for_each_zone(zone) { - u64 tmp; + u64 min, low; spin_lock_irqsave(&zone->lock, flags); - tmp = (u64)pages_min * zone->managed_pages; - do_div(tmp, lowmem_pages); + min = (u64)pages_min * zone->managed_pages; + do_div(min, lowmem_pages); + low = (u64)pages_low * zone->managed_pages; + do_div(low, vm_total_pages); + if (is_highmem(zone)) { /* * __GFP_HIGH and PF_MEMALLOC allocations usually don't @@ -6122,11 +6203,13 @@ * If it's a lowmem zone, reserve a number of pages * proportionate to the zone's size. */ - zone->watermark[WMARK_MIN] = tmp; + zone->watermark[WMARK_MIN] = min; } - zone->watermark[WMARK_LOW] = min_wmark_pages(zone) + (tmp >> 2); - zone->watermark[WMARK_HIGH] = min_wmark_pages(zone) + (tmp >> 1); + zone->watermark[WMARK_LOW] = min_wmark_pages(zone) + + low + (min >> 2); + zone->watermark[WMARK_HIGH] = min_wmark_pages(zone) + + low + (min >> 1); __mod_zone_page_state(zone, NR_ALLOC_BATCH, high_wmark_pages(zone) - low_wmark_pages(zone) - @@ -6249,7 +6332,7 @@ /* * min_free_kbytes_sysctl_handler - just a wrapper around proc_dointvec() so * that we can call two helper functions whenever min_free_kbytes - * changes. + * or extra_free_kbytes changes. */ int min_free_kbytes_sysctl_handler(struct ctl_table *table, int write, void __user *buffer, size_t *length, loff_t *ppos) @@ -6795,6 +6878,8 @@ if (ret) return ret; + cc.zone->cma_alloc = 1; + ret = __alloc_contig_migrate_range(&cc, start, end); if (ret) goto done; @@ -6853,6 +6938,7 @@ done: undo_isolate_page_range(pfn_max_align_down(start), pfn_max_align_up(end), migratetype); + cc.zone->cma_alloc = 0; return ret; } diff -ruw linux-4.4.115/mm/page_ext.c linux-4.4.115-fbx/mm/page_ext.c --- linux-4.4.115/mm/page_ext.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/mm/page_ext.c 2019-10-29 09:26:25.725223553 +0100 @@ -54,9 +54,6 @@ static struct page_ext_operations *page_ext_ops[] = { &debug_guardpage_ops, -#ifdef CONFIG_PAGE_POISONING - &page_poisoning_ops, -#endif #ifdef CONFIG_PAGE_OWNER &page_owner_ops, #endif @@ -111,6 +108,9 @@ * page can reach here before the page_ext arrays are * allocated when feeding a range of pages to the allocator * for the first time during bootup or memory hotplug. + * + * This check is also necessary for ensuring page poisoning + * works as expected when enabled */ if (unlikely(!base)) return NULL; @@ -183,6 +183,9 @@ * page can reach here before the page_ext arrays are * allocated when feeding a range of pages to the allocator * for the first time during bootup or memory hotplug. + * + * This check is also necessary for ensuring page poisoning + * works as expected when enabled */ if (!section->page_ext) return NULL; diff -ruw linux-4.4.115/mm/page_isolation.c linux-4.4.115-fbx/mm/page_isolation.c --- linux-4.4.115/mm/page_isolation.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/mm/page_isolation.c 2019-01-22 16:16:28.819294546 +0100 @@ -7,6 +7,8 @@ #include #include #include +#include +#include #include "internal.h" static int set_migratetype_isolate(struct page *page, @@ -105,8 +107,6 @@ if (pfn_valid_within(page_to_pfn(buddy)) && !is_migrate_isolate_page(buddy)) { __isolate_free_page(page, order); - kernel_map_pages(page, (1 << order), 1); - set_page_refcounted(page); isolated_page = page; } } @@ -125,9 +125,11 @@ zone->nr_isolate_pageblock--; out: spin_unlock_irqrestore(&zone->lock, flags); - if (isolated_page) + if (isolated_page) { + post_alloc_hook(page, order, __GFP_MOVABLE); __free_pages(isolated_page, order); } +} static inline struct page * __first_valid_page(unsigned long pfn, unsigned long nr_pages) diff -ruw linux-4.4.115/mm/page_owner.c linux-4.4.115-fbx/mm/page_owner.c --- linux-4.4.115/mm/page_owner.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/mm/page_owner.c 2019-01-22 16:16:28.819294546 +0100 @@ -5,10 +5,24 @@ #include #include #include +#include +#include +#include + #include "internal.h" -static bool page_owner_disabled = true; -bool page_owner_inited __read_mostly; +/* + * TODO: teach PAGE_OWNER_STACK_DEPTH (__dump_page_owner and save_stack) + * to use off stack temporal storage + */ +#define PAGE_OWNER_STACK_DEPTH (16) + +static bool page_owner_disabled = + !IS_ENABLED(CONFIG_PAGE_OWNER_ENABLE_DEFAULT); +DEFINE_STATIC_KEY_FALSE(page_owner_inited); + +static depot_stack_handle_t dummy_handle; +static depot_stack_handle_t failure_handle; static void init_early_allocated_pages(void); @@ -20,6 +34,9 @@ if (strcmp(buf, "on") == 0) page_owner_disabled = false; + if (strcmp(buf, "off") == 0) + page_owner_disabled = true; + return 0; } early_param("page_owner", early_page_owner_param); @@ -32,12 +49,42 @@ return true; } +static noinline void register_dummy_stack(void) +{ + unsigned long entries[4]; + struct stack_trace dummy; + + dummy.nr_entries = 0; + dummy.max_entries = ARRAY_SIZE(entries); + dummy.entries = &entries[0]; + dummy.skip = 0; + + save_stack_trace(&dummy); + dummy_handle = depot_save_stack(&dummy, GFP_KERNEL); +} + +static noinline void register_failure_stack(void) +{ + unsigned long entries[4]; + struct stack_trace failure; + + failure.nr_entries = 0; + failure.max_entries = ARRAY_SIZE(entries); + failure.entries = &entries[0]; + failure.skip = 0; + + save_stack_trace(&failure); + failure_handle = depot_save_stack(&failure, GFP_KERNEL); +} + static void init_page_owner(void) { if (page_owner_disabled) return; - page_owner_inited = true; + register_dummy_stack(); + register_failure_stack(); + static_branch_enable(&page_owner_inited); init_early_allocated_pages(); } @@ -59,52 +106,135 @@ } } -void __set_page_owner(struct page *page, unsigned int order, gfp_t gfp_mask) +static inline bool check_recursive_alloc(struct stack_trace *trace, + unsigned long ip) { - struct page_ext *page_ext = lookup_page_ext(page); + int i, count; + + if (!trace->nr_entries) + return false; + + for (i = 0, count = 0; i < trace->nr_entries; i++) { + if (trace->entries[i] == ip && ++count == 2) + return true; + } + return false; +} + +static noinline depot_stack_handle_t save_stack(gfp_t flags) +{ + unsigned long entries[PAGE_OWNER_STACK_DEPTH]; struct stack_trace trace = { .nr_entries = 0, - .max_entries = ARRAY_SIZE(page_ext->trace_entries), - .entries = &page_ext->trace_entries[0], - .skip = 3, + .entries = entries, + .max_entries = PAGE_OWNER_STACK_DEPTH, + .skip = 2 }; + depot_stack_handle_t handle; + + save_stack_trace(&trace); + if (trace.nr_entries != 0 && + trace.entries[trace.nr_entries-1] == ULONG_MAX) + trace.nr_entries--; + + /* + * We need to check recursion here because our request to stackdepot + * could trigger memory allocation to save new entry. New memory + * allocation would reach here and call depot_save_stack() again + * if we don't catch it. There is still not enough memory in stackdepot + * so it would try to allocate memory again and loop forever. + */ + if (check_recursive_alloc(&trace, _RET_IP_)) + return dummy_handle; + + handle = depot_save_stack(&trace, flags); + if (!handle) + handle = failure_handle; + + return handle; +} + +noinline void __set_page_owner(struct page *page, unsigned int order, + gfp_t gfp_mask) +{ + struct page_ext *page_ext = lookup_page_ext(page); if (unlikely(!page_ext)) return; - save_stack_trace(&trace); - + page_ext->handle = save_stack(gfp_mask); page_ext->order = order; page_ext->gfp_mask = gfp_mask; - page_ext->nr_entries = trace.nr_entries; + page_ext->last_migrate_reason = -1; __set_bit(PAGE_EXT_OWNER, &page_ext->flags); } -gfp_t __get_page_owner_gfp(struct page *page) +void __set_page_owner_migrate_reason(struct page *page, int reason) { struct page_ext *page_ext = lookup_page_ext(page); if (unlikely(!page_ext)) + return; + + page_ext->last_migrate_reason = reason; +} + +void __split_page_owner(struct page *page, unsigned int order) +{ + int i; + struct page_ext *page_ext = lookup_page_ext(page); + if (unlikely(!page_ext)) /* - * The caller just returns 0 if no valid gfp - * So return 0 here too. + * The caller just returns if no valid gfp + * So return here too. */ - return 0; + return; + + page_ext->order = 0; + for (i = 1; i < (1 << order); i++) + __copy_page_owner(page, page + i); +} + +void __copy_page_owner(struct page *oldpage, struct page *newpage) +{ + struct page_ext *old_ext = lookup_page_ext(oldpage); + struct page_ext *new_ext = lookup_page_ext(newpage); + + if (unlikely(!old_ext || !new_ext)) + return; - return page_ext->gfp_mask; + new_ext->order = old_ext->order; + new_ext->gfp_mask = old_ext->gfp_mask; + new_ext->last_migrate_reason = old_ext->last_migrate_reason; + new_ext->handle = old_ext->handle; + + /* + * We don't clear the bit on the oldpage as it's going to be freed + * after migration. Until then, the info can be useful in case of + * a bug, and the overal stats will be off a bit only temporarily. + * Also, migrate_misplaced_transhuge_page() can still fail the + * migration and then we want the oldpage to retain the info. But + * in that case we also don't need to explicitly clear the info from + * the new page, which will be freed. + */ + __set_bit(PAGE_EXT_OWNER, &new_ext->flags); } static ssize_t print_page_owner(char __user *buf, size_t count, unsigned long pfn, - struct page *page, struct page_ext *page_ext) + struct page *page, struct page_ext *page_ext, + depot_stack_handle_t handle) { int ret; int pageblock_mt, page_mt; char *kbuf; + unsigned long entries[PAGE_OWNER_STACK_DEPTH]; struct stack_trace trace = { - .nr_entries = page_ext->nr_entries, - .entries = &page_ext->trace_entries[0], + .nr_entries = 0, + .entries = entries, + .max_entries = PAGE_OWNER_STACK_DEPTH, + .skip = 0 }; kbuf = kmalloc(count, GFP_KERNEL); @@ -112,8 +242,9 @@ return -ENOMEM; ret = snprintf(kbuf, count, - "Page allocated via order %u, mask 0x%x\n", - page_ext->order, page_ext->gfp_mask); + "Page allocated via order %u, mask %#x(%pGg)\n", + page_ext->order, page_ext->gfp_mask, + &page_ext->gfp_mask); if (ret >= count) goto err; @@ -122,31 +253,29 @@ pageblock_mt = get_pfnblock_migratetype(page, pfn); page_mt = gfpflags_to_migratetype(page_ext->gfp_mask); ret += snprintf(kbuf + ret, count - ret, - "PFN %lu Block %lu type %d %s Flags %s%s%s%s%s%s%s%s%s%s%s%s\n", + "PFN %lu type %s Block %lu type %s Flags %#lx(%pGp)\n", pfn, + migratetype_names[page_mt], pfn >> pageblock_order, - pageblock_mt, - pageblock_mt != page_mt ? "Fallback" : " ", - PageLocked(page) ? "K" : " ", - PageError(page) ? "E" : " ", - PageReferenced(page) ? "R" : " ", - PageUptodate(page) ? "U" : " ", - PageDirty(page) ? "D" : " ", - PageLRU(page) ? "L" : " ", - PageActive(page) ? "A" : " ", - PageSlab(page) ? "S" : " ", - PageWriteback(page) ? "W" : " ", - PageCompound(page) ? "C" : " ", - PageSwapCache(page) ? "B" : " ", - PageMappedToDisk(page) ? "M" : " "); + migratetype_names[pageblock_mt], + page->flags, &page->flags); if (ret >= count) goto err; + depot_fetch_stack(handle, &trace); ret += snprint_stack_trace(kbuf + ret, count - ret, &trace, 0); if (ret >= count) goto err; + if (page_ext->last_migrate_reason != -1) { + ret += snprintf(kbuf + ret, count - ret, + "Page has been migrated, last migrate reason: %s\n", + migrate_reason_names[page_ext->last_migrate_reason]); + if (ret >= count) + goto err; + } + ret += snprintf(kbuf + ret, count - ret, "\n"); if (ret >= count) goto err; @@ -162,14 +291,58 @@ return -ENOMEM; } +void __dump_page_owner(struct page *page) +{ + struct page_ext *page_ext = lookup_page_ext(page); + unsigned long entries[PAGE_OWNER_STACK_DEPTH]; + struct stack_trace trace = { + .nr_entries = 0, + .entries = entries, + .max_entries = PAGE_OWNER_STACK_DEPTH, + .skip = 0 + }; + depot_stack_handle_t handle; + gfp_t gfp_mask; + int mt; + + if (unlikely(!page_ext)) { + pr_alert("There is not page extension available.\n"); + return; + } + gfp_mask = page_ext->gfp_mask; + mt = gfpflags_to_migratetype(gfp_mask); + + if (!test_bit(PAGE_EXT_OWNER, &page_ext->flags)) { + pr_alert("page_owner info is not active (free page?)\n"); + return; + } + + handle = READ_ONCE(page_ext->handle); + if (!handle) { + pr_alert("page_owner info is not active (free page?)\n"); + return; + } + + depot_fetch_stack(handle, &trace); + pr_alert("page allocated via order %u, migratetype %s, " + "gfp_mask %#x(%pGg)\n", page_ext->order, + migratetype_names[mt], gfp_mask, &gfp_mask); + print_stack_trace(&trace, 0); + + if (page_ext->last_migrate_reason != -1) + pr_alert("page has been migrated, last migrate reason: %s\n", + migrate_reason_names[page_ext->last_migrate_reason]); +} + static ssize_t read_page_owner(struct file *file, char __user *buf, size_t count, loff_t *ppos) { unsigned long pfn; struct page *page; struct page_ext *page_ext; + depot_stack_handle_t handle; - if (!page_owner_inited) + if (!static_branch_unlikely(&page_owner_inited)) return -EINVAL; page = NULL; @@ -216,10 +389,19 @@ if (!test_bit(PAGE_EXT_OWNER, &page_ext->flags)) continue; + /* + * Access to page_ext->handle isn't synchronous so we should + * be careful to access it. + */ + handle = READ_ONCE(page_ext->handle); + if (!handle) + continue; + /* Record the next PFN to read in the file offset */ *ppos = (pfn - min_low_pfn) + 1; - return print_page_owner(buf, count, pfn, page, page_ext); + return print_page_owner(buf, count, pfn, page, + page_ext, handle); } return 0; @@ -258,6 +440,9 @@ page = pfn_to_page(pfn); + if (page_zone(page) != zone) + continue; + /* * We are safe to check buddy flag and order, because * this is init stage and only single thread runs. @@ -321,7 +506,7 @@ { struct dentry *dentry; - if (!page_owner_inited) { + if (!static_branch_unlikely(&page_owner_inited)) { pr_info("page_owner is disabled\n"); return 0; } diff -ruw linux-4.4.115/mm/page-writeback.c linux-4.4.115-fbx/mm/page-writeback.c --- linux-4.4.115/mm/page-writeback.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/mm/page-writeback.c 2019-10-29 09:26:25.717223474 +0100 @@ -278,7 +278,12 @@ unsigned long nr_pages; nr_pages = zone_page_state(zone, NR_FREE_PAGES); - nr_pages -= min(nr_pages, zone->dirty_balance_reserve); + /* + * Pages reserved for the kernel should not be considered + * dirtyable, to prevent a situation where reclaim has to + * clean pages in order to balance the zones. + */ + nr_pages -= min(nr_pages, zone->totalreserve_pages); nr_pages += zone_page_state(zone, NR_INACTIVE_FILE); nr_pages += zone_page_state(zone, NR_ACTIVE_FILE); @@ -332,7 +337,12 @@ unsigned long x; x = global_page_state(NR_FREE_PAGES); - x -= min(x, dirty_balance_reserve); + /* + * Pages reserved for the kernel should not be considered + * dirtyable, to prevent a situation where reclaim has to + * clean pages in order to balance the zones. + */ + x -= min(x, totalreserve_pages); x += global_page_state(NR_INACTIVE_FILE); x += global_page_state(NR_ACTIVE_FILE); @@ -1944,6 +1954,12 @@ if (global_page_state(NR_UNSTABLE_NFS) + global_page_state(NR_WRITEBACK) <= dirty_thresh) break; + /* Try safe version */ + else if (unlikely(global_page_state_snapshot(NR_UNSTABLE_NFS) + + global_page_state_snapshot(NR_WRITEBACK) <= + dirty_thresh)) + break; + congestion_wait(BLK_RW_ASYNC, HZ/10); /* @@ -1978,11 +1994,11 @@ * We want to write everything out, not just down to the dirty * threshold */ - if (!bdi_has_dirty_io(&q->backing_dev_info)) + if (!bdi_has_dirty_io(q->backing_dev_info)) return; rcu_read_lock(); - list_for_each_entry_rcu(wb, &q->backing_dev_info.wb_list, bdi_node) + list_for_each_entry_rcu(wb, &q->backing_dev_info->wb_list, bdi_node) if (wb_has_dirty_io(wb)) wb_start_writeback(wb, nr_pages, true, WB_REASON_LAPTOP_TIMER); diff -ruw linux-4.4.115/mm/percpu.c linux-4.4.115-fbx/mm/percpu.c --- linux-4.4.115/mm/percpu.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/mm/percpu.c 2019-10-29 09:26:25.725223553 +0100 @@ -889,8 +889,8 @@ size = ALIGN(size, 2); if (unlikely(!size || size > PCPU_MIN_UNIT_SIZE || align > PAGE_SIZE)) { - WARN(true, "illegal size (%zu) or align (%zu) for " - "percpu allocation\n", size, align); + WARN(true, "illegal size (%zu) or align (%zu) for percpu allocation\n", + size, align); return NULL; } diff -ruw linux-4.4.115/mm/readahead.c linux-4.4.115-fbx/mm/readahead.c --- linux-4.4.115/mm/readahead.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/mm/readahead.c 2019-10-29 09:26:25.725223553 +0100 @@ -234,6 +234,8 @@ /* * Set the initial window size, round to next power of 2 and square + * Small size is not dependant on max value - only a one-page read is regarded + * as small. * for small size, x 4 for medium, and x 2 for large * for 128k (32 page) max ra * 1-8 page = 32k initial, > 8 page = 128k initial @@ -242,7 +244,7 @@ { unsigned long newsize = roundup_pow_of_two(size); - if (newsize <= max / 32) + if (newsize <= 1) newsize = newsize * 4; else if (newsize <= max / 4) newsize = newsize * 2; diff -ruw linux-4.4.115/mm/rmap.c linux-4.4.115-fbx/mm/rmap.c --- linux-4.4.115/mm/rmap.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/mm/rmap.c 2019-10-29 09:26:25.729223592 +0100 @@ -1481,9 +1481,12 @@ * try_to_unmap - try to remove all page table mappings to a page * @page: the page to get unmapped * @flags: action and flags + * @vma : target vma for reclaim * * Tries to remove all the page table entries which are mapping this * page, used in the pageout path. Caller must hold the page lock. + * If @vma is not NULL, this function try to remove @page from only @vma + * without peeking all mapped vma for @page. * Return values are: * * SWAP_SUCCESS - we succeeded in removing all mappings @@ -1491,7 +1494,8 @@ * SWAP_FAIL - the page is unswappable * SWAP_MLOCK - page is mlocked. */ -int try_to_unmap(struct page *page, enum ttu_flags flags) +int try_to_unmap(struct page *page, enum ttu_flags flags, + struct vm_area_struct *vma) { int ret; struct rmap_walk_control rwc = { @@ -1499,6 +1503,7 @@ .arg = (void *)flags, .done = page_not_mapped, .anon_lock = page_lock_anon_vma_read, + .target_vma = vma, }; VM_BUG_ON_PAGE(!PageHuge(page) && PageTransHuge(page), page); @@ -1544,6 +1549,7 @@ .arg = (void *)TTU_MUNLOCK, .done = page_not_mapped, .anon_lock = page_lock_anon_vma_read, + .target_vma = NULL, }; @@ -1605,6 +1611,11 @@ struct anon_vma_chain *avc; int ret = SWAP_AGAIN; + if (rwc->target_vma) { + unsigned long address = vma_address(page, rwc->target_vma); + return rwc->rmap_one(page, rwc->target_vma, address, rwc->arg); + } + anon_vma = rmap_walk_anon_lock(page, rwc); if (!anon_vma) return ret; @@ -1647,6 +1658,7 @@ struct address_space *mapping = page->mapping; pgoff_t pgoff; struct vm_area_struct *vma; + unsigned long address; int ret = SWAP_AGAIN; /* @@ -1662,6 +1674,12 @@ pgoff = page_to_pgoff(page); i_mmap_lock_read(mapping); + if (rwc->target_vma) { + address = vma_address(page, rwc->target_vma); + ret = rwc->rmap_one(page, rwc->target_vma, address, rwc->arg); + goto done; + } + vma_interval_tree_foreach(vma, &mapping->i_mmap, pgoff, pgoff) { unsigned long address = vma_address(page, vma); diff -ruw linux-4.4.115/mm/shmem.c linux-4.4.115-fbx/mm/shmem.c --- linux-4.4.115/mm/shmem.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/mm/shmem.c 2019-10-29 09:26:25.729223592 +0100 @@ -3405,6 +3405,14 @@ } EXPORT_SYMBOL_GPL(shmem_file_setup); +void shmem_set_file(struct vm_area_struct *vma, struct file *file) +{ + if (vma->vm_file) + fput(vma->vm_file); + vma->vm_file = file; + vma->vm_ops = &shmem_vm_ops; +} + /** * shmem_zero_setup - setup a shared anonymous mapping * @vma: the vma to be mmapped is prepared by do_mmap_pgoff @@ -3424,10 +3432,7 @@ if (IS_ERR(file)) return PTR_ERR(file); - if (vma->vm_file) - fput(vma->vm_file); - vma->vm_file = file; - vma->vm_ops = &shmem_vm_ops; + shmem_set_file(vma, file); return 0; } diff -ruw linux-4.4.115/mm/slab_common.c linux-4.4.115-fbx/mm/slab_common.c --- linux-4.4.115/mm/slab_common.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/mm/slab_common.c 2019-01-22 16:16:28.827294618 +0100 @@ -35,7 +35,7 @@ */ #define SLAB_NEVER_MERGE (SLAB_RED_ZONE | SLAB_POISON | SLAB_STORE_USER | \ SLAB_TRACE | SLAB_DESTROY_BY_RCU | SLAB_NOLEAKTRACE | \ - SLAB_FAILSLAB) + SLAB_FAILSLAB | SLAB_KASAN) #define SLAB_MERGE_SAME (SLAB_RECLAIM_ACCOUNT | SLAB_CACHE_DMA | SLAB_NOTRACK) @@ -453,6 +453,9 @@ static int shutdown_cache(struct kmem_cache *s, struct list_head *release, bool *need_rcu_barrier) { + /* free asan quarantined objects */ + kasan_cache_shutdown(s); + if (__kmem_cache_shutdown(s) != 0) return -EBUSY; @@ -723,8 +726,8 @@ err = shutdown_cache(s, &release, &need_rcu_barrier); if (err) { - pr_err("kmem_cache_destroy %s: " - "Slab cache still has objects\n", s->name); + pr_err("kmem_cache_destroy %s: Slab cache still has objects\n", + s->name); dump_stack(); } out_unlock: @@ -750,6 +753,7 @@ get_online_cpus(); get_online_mems(); + kasan_cache_shrink(cachep); ret = __kmem_cache_shrink(cachep, false); put_online_mems(); put_online_cpus(); @@ -1010,7 +1014,7 @@ page = alloc_kmem_pages(flags, order); ret = page ? page_address(page) : NULL; kmemleak_alloc(ret, size, 1, flags); - kasan_kmalloc_large(ret, size); + kasan_kmalloc_large(ret, size, flags); return ret; } EXPORT_SYMBOL(kmalloc_order); @@ -1044,13 +1048,11 @@ #else seq_puts(m, "slabinfo - version: 2.1\n"); #endif - seq_puts(m, "# name " - " "); + seq_puts(m, "# name "); seq_puts(m, " : tunables "); seq_puts(m, " : slabdata "); #ifdef CONFIG_DEBUG_SLAB - seq_puts(m, " : globalstat " - " "); + seq_puts(m, " : globalstat "); seq_puts(m, " : cpustat "); #endif seq_putc(m, '\n'); @@ -1191,7 +1193,7 @@ ks = ksize(p); if (ks >= new_size) { - kasan_krealloc((void *)p, new_size); + kasan_krealloc((void *)p, new_size, flags); return (void *)p; } diff -ruw linux-4.4.115/mm/slab.h linux-4.4.115-fbx/mm/slab.h --- linux-4.4.115/mm/slab.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/mm/slab.h 2019-01-22 16:16:28.827294618 +0100 @@ -371,4 +371,6 @@ void slab_stop(struct seq_file *m, void *p); int memcg_slab_show(struct seq_file *m, void *p); +void ___cache_free(struct kmem_cache *cache, void *x, unsigned long addr); + #endif /* MM_SLAB_H */ diff -ruw linux-4.4.115/mm/slub.c linux-4.4.115-fbx/mm/slub.c --- linux-4.4.115/mm/slub.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/mm/slub.c 2019-10-29 09:26:25.733223631 +0100 @@ -124,6 +124,14 @@ #endif } +static inline void *fixup_red_left(struct kmem_cache *s, void *p) +{ + if (kmem_cache_debug(s) && s->flags & SLAB_RED_ZONE) + p += s->red_left_pad; + + return p; +} + static inline bool kmem_cache_has_cpu_partial(struct kmem_cache *s) { #ifdef CONFIG_SLUB_CPU_PARTIAL @@ -224,24 +232,6 @@ * Core slab cache functions *******************************************************************/ -/* Verify that a pointer has an address that is valid within a slab page */ -static inline int check_valid_pointer(struct kmem_cache *s, - struct page *page, const void *object) -{ - void *base; - - if (!object) - return 1; - - base = page_address(page); - if (object < base || object >= base + page->objects * s->size || - (object - base) % s->size) { - return 0; - } - - return 1; -} - static inline void *get_freepointer(struct kmem_cache *s, void *object) { return *(void **)(object + s->offset); @@ -271,11 +261,13 @@ /* Loop over all objects in a slab */ #define for_each_object(__p, __s, __addr, __objects) \ - for (__p = (__addr); __p < (__addr) + (__objects) * (__s)->size;\ + for (__p = fixup_red_left(__s, __addr); \ + __p < (__addr) + (__objects) * (__s)->size; \ __p += (__s)->size) #define for_each_object_idx(__p, __idx, __s, __addr, __objects) \ - for (__p = (__addr), __idx = 1; __idx <= __objects;\ + for (__p = fixup_red_left(__s, __addr), __idx = 1; \ + __idx <= __objects; \ __p += (__s)->size, __idx++) /* Determine object index from a given position */ @@ -295,6 +287,9 @@ return s->object_size; #endif + if (s->flags & SLAB_KASAN) + return s->object_size; + /* * If we have the need to store the freelist pointer * back there or track user information then we can @@ -456,13 +451,27 @@ set_bit(slab_index(p, s, addr), map); } +static inline int size_from_object(struct kmem_cache *s) +{ + if (s->flags & SLAB_RED_ZONE) + return s->size - s->red_left_pad; + + return s->size; +} + +static inline void *restore_red_left(struct kmem_cache *s, void *p) +{ + if (s->flags & SLAB_RED_ZONE) + p -= s->red_left_pad; + + return p; +} + /* * Debug settings: */ #if defined(CONFIG_SLUB_DEBUG_ON) static int slub_debug = DEBUG_DEFAULT_FLAGS; -#elif defined(CONFIG_KASAN) -static int slub_debug = SLAB_STORE_USER; #else static int slub_debug; #endif @@ -489,6 +498,26 @@ /* * Object debugging */ + +/* Verify that a pointer has an address that is valid within a slab page */ +static inline int check_valid_pointer(struct kmem_cache *s, + struct page *page, void *object) +{ + void *base; + + if (!object) + return 1; + + base = page_address(page); + object = restore_red_left(s, object); + if (object < base || object >= base + page->objects * s->size || + (object - base) % s->size) { + return 0; + } + + return 1; +} + static void print_section(char *text, u8 *addr, unsigned int length) { metadata_access_enable(); @@ -628,7 +657,9 @@ pr_err("INFO: Object 0x%p @offset=%tu fp=0x%p\n\n", p, p - addr, get_freepointer(s, p)); - if (p > addr + 16) + if (s->flags & SLAB_RED_ZONE) + print_section("Redzone ", p - s->red_left_pad, s->red_left_pad); + else if (p > addr + 16) print_section("Bytes b4 ", p - 16, 16); print_section("Object ", p, min_t(unsigned long, s->object_size, @@ -645,18 +676,30 @@ if (s->flags & SLAB_STORE_USER) off += 2 * sizeof(struct track); - if (off != s->size) + off += kasan_metadata_size(s); + + if (off != size_from_object(s)) /* Beginning of the filler is the free pointer */ - print_section("Padding ", p + off, s->size - off); + print_section("Padding ", p + off, size_from_object(s) - off); dump_stack(); } +#ifdef CONFIG_SLUB_DEBUG_PANIC_ON +static void slab_panic(const char *cause) +{ + panic("%s\n", cause); +} +#else +static inline void slab_panic(const char *cause) {} +#endif + void object_err(struct kmem_cache *s, struct page *page, u8 *object, char *reason) { slab_bug(s, "%s", reason); print_trailer(s, page, object); + slab_panic(reason); } static void slab_err(struct kmem_cache *s, struct page *page, @@ -671,12 +714,16 @@ slab_bug(s, "%s", buf); print_page_info(page); dump_stack(); + slab_panic("slab error"); } static void init_object(struct kmem_cache *s, void *object, u8 val) { u8 *p = object; + if (s->flags & SLAB_RED_ZONE) + memset(p - s->red_left_pad, val, s->red_left_pad); + if (s->flags & __OBJECT_POISON) { memset(p, POISON_FREE, s->object_size - 1); p[s->object_size - 1] = POISON_END; @@ -689,6 +736,7 @@ static void restore_bytes(struct kmem_cache *s, char *message, u8 data, void *from, void *to) { + slab_panic("object poison overwritten"); slab_fix(s, "Restoring 0x%p-0x%p=0x%x\n", from, to - 1, data); memset(from, data, to - from); } @@ -769,11 +817,13 @@ /* We also have user information there */ off += 2 * sizeof(struct track); - if (s->size == off) + off += kasan_metadata_size(s); + + if (size_from_object(s) == off) return 1; return check_bytes_and_report(s, page, p, "Object padding", - p + off, POISON_INUSE, s->size - off); + p + off, POISON_INUSE, size_from_object(s) - off); } /* Check the pad bytes at the end of a slab page */ @@ -818,6 +868,10 @@ if (s->flags & SLAB_RED_ZONE) { if (!check_bytes_and_report(s, page, object, "Redzone", + object - s->red_left_pad, val, s->red_left_pad)) + return 0; + + if (!check_bytes_and_report(s, page, object, "Redzone", endobject, val, s->inuse - s->object_size)) return 0; } else { @@ -928,14 +982,14 @@ max_objects = MAX_OBJS_PER_PAGE; if (page->objects != max_objects) { - slab_err(s, page, "Wrong number of objects. Found %d but " - "should be %d", page->objects, max_objects); + slab_err(s, page, "Wrong number of objects. Found %d but should be %d", + page->objects, max_objects); page->objects = max_objects; slab_fix(s, "Number of objects adjusted."); } if (page->inuse != page->objects - nr) { - slab_err(s, page, "Wrong object count. Counter is %d but " - "counted were %d", page->inuse, page->objects - nr); + slab_err(s, page, "Wrong object count. Counter is %d but counted were %d", + page->inuse, page->objects - nr); page->inuse = page->objects - nr; slab_fix(s, "Object count adjusted."); } @@ -1099,8 +1153,8 @@ if (unlikely(s != page->slab_cache)) { if (!PageSlab(page)) { - slab_err(s, page, "Attempt to free object(0x%p) " - "outside of slab", object); + slab_err(s, page, "Attempt to free object(0x%p) outside of slab", + object); } else if (!page->slab_cache) { pr_err("SLUB : no slab for object 0x%p.\n", object); @@ -1270,7 +1324,7 @@ static inline void kmalloc_large_node_hook(void *ptr, size_t size, gfp_t flags) { kmemleak_alloc(ptr, size, 1, flags); - kasan_kmalloc_large(ptr, size); + kasan_kmalloc_large(ptr, size, flags); } static inline void kfree_hook(const void *x) @@ -1304,13 +1358,15 @@ kmemcheck_slab_alloc(s, flags, object, slab_ksize(s)); kmemleak_alloc_recursive(object, s->object_size, 1, s->flags, flags); - kasan_slab_alloc(s, object); + kasan_slab_alloc(s, object, flags); } memcg_kmem_put_cache(s); } -static inline void slab_free_hook(struct kmem_cache *s, void *x) +static inline void *slab_free_hook(struct kmem_cache *s, void *x) { + void *freeptr; + kmemleak_free_recursive(x, s->flags); /* @@ -1331,7 +1387,13 @@ if (!(s->flags & SLAB_DEBUG_OBJECTS)) debug_check_no_obj_freed(x, s->object_size); + freeptr = get_freepointer(s, x); + /* + * kasan_slab_free() may put x into memory quarantine, delaying its + * reuse. In this case the object's freelist pointer is changed. + */ kasan_slab_free(s, x); + return freeptr; } static inline void slab_free_freelist_hook(struct kmem_cache *s, @@ -1349,11 +1411,11 @@ void *object = head; void *tail_obj = tail ? : head; + void *freeptr; do { - slab_free_hook(s, object); - } while ((object != tail_obj) && - (object = get_freepointer(s, object))); + freeptr = slab_free_hook(s, object); + } while ((object != tail_obj) && (object = freeptr)); #endif } @@ -1361,6 +1423,7 @@ void *object) { setup_object_debug(s, page, object); + kasan_init_slab_obj(s, object); if (unlikely(s->ctor)) { kasan_unpoison_object_data(s, object); s->ctor(object); @@ -1468,7 +1531,7 @@ set_freepointer(s, p, NULL); } - page->freelist = start; + page->freelist = fixup_red_left(s, start); page->inuse = page->objects; page->frozen = 1; @@ -1526,6 +1589,7 @@ page_mapcount_reset(page); if (current->reclaim_state) current->reclaim_state->reclaimed_slab += pages; + kasan_alloc_pages(page, order); __free_kmem_pages(page, order); } @@ -2588,7 +2652,7 @@ { void *ret = slab_alloc(s, gfpflags, _RET_IP_); trace_kmalloc(_RET_IP_, ret, size, s->size, gfpflags); - kasan_kmalloc(s, ret, size); + kasan_kmalloc(s, ret, size, gfpflags); return ret; } EXPORT_SYMBOL(kmem_cache_alloc_trace); @@ -2616,7 +2680,7 @@ trace_kmalloc_node(_RET_IP_, ret, size, s->size, gfpflags, node); - kasan_kmalloc(s, ret, size); + kasan_kmalloc(s, ret, size, gfpflags); return ret; } EXPORT_SYMBOL(kmem_cache_alloc_node_trace); @@ -2761,16 +2825,13 @@ * same page) possible by specifying head and tail ptr, plus objects * count (cnt). Bulk free indicated by tail pointer being set. */ -static __always_inline void slab_free(struct kmem_cache *s, struct page *page, - void *head, void *tail, int cnt, - unsigned long addr) +static __always_inline void do_slab_free(struct kmem_cache *s, + struct page *page, void *head, void *tail, + int cnt, unsigned long addr) { void *tail_obj = tail ? : head; struct kmem_cache_cpu *c; unsigned long tid; - - slab_free_freelist_hook(s, head, tail); - redo: /* * Determine the currently cpus per cpu slab. @@ -2804,6 +2865,27 @@ } +static __always_inline void slab_free(struct kmem_cache *s, struct page *page, + void *head, void *tail, int cnt, + unsigned long addr) +{ + slab_free_freelist_hook(s, head, tail); + /* + * slab_free_freelist_hook() could have put the items into quarantine. + * If so, no need to free them. + */ + if (s->flags & SLAB_KASAN && !(s->flags & SLAB_DESTROY_BY_RCU)) + return; + do_slab_free(s, page, head, tail, cnt, addr); +} + +#ifdef CONFIG_KASAN +void ___cache_free(struct kmem_cache *cache, void *x, unsigned long addr) +{ + do_slab_free(cache, virt_to_head_page(x), x, NULL, 1, addr); +} +#endif + void kmem_cache_free(struct kmem_cache *s, void *x) { s = cache_from_obj(s, x); @@ -3160,7 +3242,8 @@ init_object(kmem_cache_node, n, SLUB_RED_ACTIVE); init_tracking(kmem_cache_node, n); #endif - kasan_kmalloc(kmem_cache_node, n, sizeof(struct kmem_cache_node)); + kasan_kmalloc(kmem_cache_node, n, sizeof(struct kmem_cache_node), + GFP_KERNEL); init_kmem_cache_node(n); inc_slabs_node(kmem_cache_node, node, page->objects); @@ -3223,7 +3306,7 @@ static int calculate_sizes(struct kmem_cache *s, int forced_order) { unsigned long flags = s->flags; - unsigned long size = s->object_size; + size_t size = s->object_size; int order; /* @@ -3282,8 +3365,11 @@ * the object. */ size += 2 * sizeof(struct track); +#endif - if (flags & SLAB_RED_ZONE) + kasan_cache_create(s, &size, &s->flags); +#ifdef CONFIG_SLUB_DEBUG + if (flags & SLAB_RED_ZONE) { /* * Add some empty padding so that we can catch * overwrites from earlier objects rather than let @@ -3292,6 +3378,11 @@ * of the object. */ size += sizeof(void *); + + s->red_left_pad = sizeof(void *); + s->red_left_pad = ALIGN(s->red_left_pad, s->align); + size += s->red_left_pad; + } #endif /* @@ -3406,8 +3497,7 @@ free_kmem_cache_nodes(s); error: if (flags & SLAB_PANIC) - panic("Cannot create slab %s size=%lu realsize=%u " - "order=%u offset=%u flags=%lx\n", + panic("Cannot create slab %s size=%lu realsize=%u order=%u offset=%u flags=%lx\n", s->name, (unsigned long)s->size, s->size, oo_order(s->oo), s->offset, flags); return -EINVAL; @@ -3533,7 +3623,7 @@ trace_kmalloc(_RET_IP_, ret, size, s->size, flags); - kasan_kmalloc(s, ret, size); + kasan_kmalloc(s, ret, size, flags); return ret; } @@ -3578,13 +3668,53 @@ trace_kmalloc_node(_RET_IP_, ret, size, s->size, flags, node); - kasan_kmalloc(s, ret, size); + kasan_kmalloc(s, ret, size, flags); return ret; } EXPORT_SYMBOL(__kmalloc_node); #endif +#ifdef CONFIG_HARDENED_USERCOPY +/* + * Rejects objects that are incorrectly sized. + * + * Returns NULL if check passes, otherwise const char * to name of cache + * to indicate an error. + */ +const char *__check_heap_object(const void *ptr, unsigned long n, + struct page *page) +{ + struct kmem_cache *s; + unsigned long offset; + size_t object_size; + + /* Find object and usable object size. */ + s = page->slab_cache; + object_size = slab_ksize(s); + + /* Reject impossible pointers. */ + if (ptr < page_address(page)) + return s->name; + + /* Find offset within object. */ + offset = (ptr - page_address(page)) % s->size; + + /* Adjust for redzone and reject if within the redzone. */ + if (kmem_cache_debug(s) && s->flags & SLAB_RED_ZONE) { + if (offset < s->red_left_pad) + return s->name; + offset -= s->red_left_pad; + } + + /* Allow address range falling entirely within object size. */ + if (offset <= object_size && n <= object_size - offset) + return NULL; + + return s->name; +} +#endif /* CONFIG_HARDENED_USERCOPY */ + static size_t __ksize(const void *object) { struct page *page; @@ -3607,7 +3737,7 @@ size_t size = __ksize(object); /* We assume that ksize callers could use whole allocated area, so we need unpoison this area. */ - kasan_krealloc(object, size); + kasan_krealloc(object, size, GFP_NOWAIT); return size; } EXPORT_SYMBOL(ksize); @@ -3626,6 +3756,7 @@ if (unlikely(!PageSlab(page))) { BUG_ON(!PageCompound(page)); kfree_hook(x); + kasan_alloc_pages(page, compound_order(page)); __free_kmem_pages(page, compound_order(page)); return; } diff -ruw linux-4.4.115/mm/sparse.c linux-4.4.115-fbx/mm/sparse.c --- linux-4.4.115/mm/sparse.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/mm/sparse.c 2019-01-22 16:16:28.831294655 +0100 @@ -428,8 +428,8 @@ if (map_map[pnum]) continue; ms = __nr_to_section(pnum); - printk(KERN_ERR "%s: sparsemem memory map backing failed " - "some memory will not be available.\n", __func__); + printk(KERN_ERR "%s: sparsemem memory map backing failed some memory will not be available.\n", + __func__); ms->section_mem_map = 0; } } @@ -456,8 +456,8 @@ if (map) return map; - printk(KERN_ERR "%s: sparsemem memory map backing failed " - "some memory will not be available.\n", __func__); + printk(KERN_ERR "%s: sparsemem memory map backing failed some memory will not be available.\n", + __func__); ms->section_mem_map = 0; return NULL; } diff -ruw linux-4.4.115/mm/sparse-vmemmap.c linux-4.4.115-fbx/mm/sparse-vmemmap.c --- linux-4.4.115/mm/sparse-vmemmap.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/mm/sparse-vmemmap.c 2019-01-22 16:16:28.831294655 +0100 @@ -94,8 +94,8 @@ int actual_node = early_pfn_to_nid(pfn); if (node_distance(actual_node, node) > LOCAL_DISTANCE) - printk(KERN_WARNING "[%lx-%lx] potential offnode " - "page_structs\n", start, end - 1); + printk(KERN_WARNING "[%lx-%lx] potential offnode page_structs\n", + start, end - 1); } pte_t * __meminit vmemmap_pte_populate(pmd_t *pmd, unsigned long addr, int node) @@ -220,8 +220,8 @@ if (map_map[pnum]) continue; ms = __nr_to_section(pnum); - printk(KERN_ERR "%s: sparsemem memory map backing failed " - "some memory will not be available.\n", __func__); + printk(KERN_ERR "%s: sparsemem memory map backing failed some memory will not be available.\n", + __func__); ms->section_mem_map = 0; } diff -ruw linux-4.4.115/mm/truncate.c linux-4.4.115-fbx/mm/truncate.c --- linux-4.4.115/mm/truncate.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/mm/truncate.c 2019-10-29 09:26:25.737223670 +0100 @@ -63,6 +63,171 @@ spin_unlock_irq(&mapping->tree_lock); } +static void do_truncate_inode_pages_range(struct address_space *mapping, + loff_t lstart, loff_t lend, bool fill_zero) +{ + pgoff_t start; /* inclusive */ + pgoff_t end; /* exclusive */ + unsigned int partial_start; /* inclusive */ + unsigned int partial_end; /* exclusive */ + struct pagevec pvec; + pgoff_t indices[PAGEVEC_SIZE]; + pgoff_t index; + int i; + + cleancache_invalidate_inode(mapping); + if (mapping->nrpages == 0 && mapping->nrshadows == 0) + return; + + /* Offsets within partial pages */ + partial_start = lstart & (PAGE_CACHE_SIZE - 1); + partial_end = (lend + 1) & (PAGE_CACHE_SIZE - 1); + + /* + * 'start' and 'end' always covers the range of pages to be fully + * truncated. Partial pages are covered with 'partial_start' at the + * start of the range and 'partial_end' at the end of the range. + * Note that 'end' is exclusive while 'lend' is inclusive. + */ + start = (lstart + PAGE_CACHE_SIZE - 1) >> PAGE_CACHE_SHIFT; + if (lend == -1) + /* + * lend == -1 indicates end-of-file so we have to set 'end' + * to the highest possible pgoff_t and since the type is + * unsigned we're using -1. + */ + end = -1; + else + end = (lend + 1) >> PAGE_CACHE_SHIFT; + + pagevec_init(&pvec, 0); + index = start; + + while (index < end && pagevec_lookup_entries(&pvec, mapping, index, + min(end - index, (pgoff_t)PAGEVEC_SIZE), + indices)) { + for (i = 0; i < pagevec_count(&pvec); i++) { + struct page *page = pvec.pages[i]; + + /* We rely upon deletion not changing page->index */ + index = indices[i]; + if (index >= end) + break; + + if (radix_tree_exceptional_entry(page)) { + clear_exceptional_entry(mapping, index, page); + continue; + } + + if (!trylock_page(page)) + continue; + WARN_ON(page->index != index); + if (PageWriteback(page)) { + unlock_page(page); + continue; + } + truncate_inode_page(mapping, page); + if (fill_zero) + zero_user(page, 0, PAGE_CACHE_SIZE); + unlock_page(page); + } + pagevec_remove_exceptionals(&pvec); + pagevec_release(&pvec); + cond_resched(); + index++; + } + + if (partial_start) { + struct page *page = find_lock_page(mapping, start - 1); + + if (page) { + unsigned int top = PAGE_CACHE_SIZE; + + if (start > end) { + /* Truncation within a single page */ + top = partial_end; + partial_end = 0; + } + wait_on_page_writeback(page); + zero_user_segment(page, partial_start, top); + cleancache_invalidate_page(mapping, page); + if (page_has_private(page)) + do_invalidatepage(page, partial_start, + top - partial_start); + unlock_page(page); + page_cache_release(page); + } + } + if (partial_end) { + struct page *page = find_lock_page(mapping, end); + + if (page) { + wait_on_page_writeback(page); + zero_user_segment(page, 0, partial_end); + cleancache_invalidate_page(mapping, page); + if (page_has_private(page)) + do_invalidatepage(page, 0, + partial_end); + unlock_page(page); + page_cache_release(page); + } + } + /* + * If the truncation happened within a single page no pages + * will be released, just zeroed, so we can bail out now. + */ + if (start >= end) + return; + + index = start; + for ( ; ; ) { + cond_resched(); + if (!pagevec_lookup_entries(&pvec, mapping, index, + min(end - index, (pgoff_t)PAGEVEC_SIZE), indices)) { + /* If all gone from start onwards, we're done */ + if (index == start) + break; + /* Otherwise restart to make sure all gone */ + index = start; + continue; + } + if (index == start && indices[0] >= end) { + /* All gone out of hole to be punched, we're done */ + pagevec_remove_exceptionals(&pvec); + pagevec_release(&pvec); + break; + } + for (i = 0; i < pagevec_count(&pvec); i++) { + struct page *page = pvec.pages[i]; + + /* We rely upon deletion not changing page->index */ + index = indices[i]; + if (index >= end) { + /* Restart punch to make sure all gone */ + index = start - 1; + break; + } + + if (radix_tree_exceptional_entry(page)) { + clear_exceptional_entry(mapping, index, page); + continue; + } + + lock_page(page); + WARN_ON(page->index != index); + wait_on_page_writeback(page); + truncate_inode_page(mapping, page); + if (fill_zero) + zero_user(page, 0, PAGE_CACHE_SIZE); + unlock_page(page); + } + pagevec_remove_exceptionals(&pvec); + pagevec_release(&pvec); + index++; + } + cleancache_invalidate_inode(mapping); +} + /** * do_invalidatepage - invalidate part or all of a page * @page: the page which is affected @@ -218,160 +383,41 @@ void truncate_inode_pages_range(struct address_space *mapping, loff_t lstart, loff_t lend) { - pgoff_t start; /* inclusive */ - pgoff_t end; /* exclusive */ - unsigned int partial_start; /* inclusive */ - unsigned int partial_end; /* exclusive */ - struct pagevec pvec; - pgoff_t indices[PAGEVEC_SIZE]; - pgoff_t index; - int i; - - cleancache_invalidate_inode(mapping); - if (mapping->nrpages == 0 && mapping->nrshadows == 0) - return; - - /* Offsets within partial pages */ - partial_start = lstart & (PAGE_CACHE_SIZE - 1); - partial_end = (lend + 1) & (PAGE_CACHE_SIZE - 1); - - /* - * 'start' and 'end' always covers the range of pages to be fully - * truncated. Partial pages are covered with 'partial_start' at the - * start of the range and 'partial_end' at the end of the range. - * Note that 'end' is exclusive while 'lend' is inclusive. - */ - start = (lstart + PAGE_CACHE_SIZE - 1) >> PAGE_CACHE_SHIFT; - if (lend == -1) - /* - * lend == -1 indicates end-of-file so we have to set 'end' - * to the highest possible pgoff_t and since the type is - * unsigned we're using -1. - */ - end = -1; - else - end = (lend + 1) >> PAGE_CACHE_SHIFT; - - pagevec_init(&pvec, 0); - index = start; - while (index < end && pagevec_lookup_entries(&pvec, mapping, index, - min(end - index, (pgoff_t)PAGEVEC_SIZE), - indices)) { - for (i = 0; i < pagevec_count(&pvec); i++) { - struct page *page = pvec.pages[i]; - - /* We rely upon deletion not changing page->index */ - index = indices[i]; - if (index >= end) - break; - - if (radix_tree_exceptional_entry(page)) { - clear_exceptional_entry(mapping, index, page); - continue; - } - - if (!trylock_page(page)) - continue; - WARN_ON(page->index != index); - if (PageWriteback(page)) { - unlock_page(page); - continue; - } - truncate_inode_page(mapping, page); - unlock_page(page); - } - pagevec_remove_exceptionals(&pvec); - pagevec_release(&pvec); - cond_resched(); - index++; + do_truncate_inode_pages_range(mapping, lstart, lend, false); } +EXPORT_SYMBOL(truncate_inode_pages_range); - if (partial_start) { - struct page *page = find_lock_page(mapping, start - 1); - if (page) { - unsigned int top = PAGE_CACHE_SIZE; - if (start > end) { - /* Truncation within a single page */ - top = partial_end; - partial_end = 0; - } - wait_on_page_writeback(page); - zero_user_segment(page, partial_start, top); - cleancache_invalidate_page(mapping, page); - if (page_has_private(page)) - do_invalidatepage(page, partial_start, - top - partial_start); - unlock_page(page); - page_cache_release(page); - } - } - if (partial_end) { - struct page *page = find_lock_page(mapping, end); - if (page) { - wait_on_page_writeback(page); - zero_user_segment(page, 0, partial_end); - cleancache_invalidate_page(mapping, page); - if (page_has_private(page)) - do_invalidatepage(page, 0, - partial_end); - unlock_page(page); - page_cache_release(page); - } - } - /* - * If the truncation happened within a single page no pages - * will be released, just zeroed, so we can bail out now. +/** + * truncate_inode_pages_range_fill_zero - truncate range of pages specified by start & + * end byte offsets and zero them out + * @mapping: mapping to truncate + * @lstart: offset from which to truncate + * @lend: offset to which to truncate (inclusive) + * + * Truncate the page cache, removing the pages that are between + * specified offsets (and zeroing out partial pages + * if lstart or lend + 1 is not page aligned). + * + * Truncate takes two passes - the first pass is nonblocking. It will not + * block on page locks and it will not block on writeback. The second pass + * will wait. This is to prevent as much IO as possible in the affected region. + * The first pass will remove most pages, so the search cost of the second pass + * is low. + * + * We pass down the cache-hot hint to the page freeing code. Even if the + * mapping is large, it is probably the case that the final pages are the most + * recently touched, and freeing happens in ascending file offset order. + * + * Note that since ->invalidatepage() accepts range to invalidate + * truncate_inode_pages_range is able to handle cases where lend + 1 is not + * page aligned properly. */ - if (start >= end) - return; - - index = start; - for ( ; ; ) { - cond_resched(); - if (!pagevec_lookup_entries(&pvec, mapping, index, - min(end - index, (pgoff_t)PAGEVEC_SIZE), indices)) { - /* If all gone from start onwards, we're done */ - if (index == start) - break; - /* Otherwise restart to make sure all gone */ - index = start; - continue; - } - if (index == start && indices[0] >= end) { - /* All gone out of hole to be punched, we're done */ - pagevec_remove_exceptionals(&pvec); - pagevec_release(&pvec); - break; - } - for (i = 0; i < pagevec_count(&pvec); i++) { - struct page *page = pvec.pages[i]; - - /* We rely upon deletion not changing page->index */ - index = indices[i]; - if (index >= end) { - /* Restart punch to make sure all gone */ - index = start - 1; - break; - } - - if (radix_tree_exceptional_entry(page)) { - clear_exceptional_entry(mapping, index, page); - continue; - } - - lock_page(page); - WARN_ON(page->index != index); - wait_on_page_writeback(page); - truncate_inode_page(mapping, page); - unlock_page(page); - } - pagevec_remove_exceptionals(&pvec); - pagevec_release(&pvec); - index++; - } - cleancache_invalidate_inode(mapping); +void truncate_inode_pages_range_fill_zero(struct address_space *mapping, + loff_t lstart, loff_t lend) +{ + do_truncate_inode_pages_range(mapping, lstart, lend, true); } -EXPORT_SYMBOL(truncate_inode_pages_range); +EXPORT_SYMBOL(truncate_inode_pages_range_fill_zero); /** * truncate_inode_pages - truncate *all* the pages from an offset @@ -392,6 +438,27 @@ EXPORT_SYMBOL(truncate_inode_pages); /** + * truncate_inode_pages_fill_zero - truncate *all* the pages from an offset + * and zero them out + * @mapping: mapping to truncate + * @lstart: offset from which to truncate + * + * Called under (and serialised by) inode->i_mutex. + * + * Note: When this function returns, there can be a page in the process of + * deletion (inside __delete_from_page_cache()) in the specified range. Thus + * mapping->nrpages can be non-zero when this function returns even after + * truncation of the whole mapping. + */ +void truncate_inode_pages_fill_zero(struct address_space *mapping, + loff_t lstart) +{ + truncate_inode_pages_range_fill_zero(mapping, lstart, (loff_t)-1); +} +EXPORT_SYMBOL(truncate_inode_pages_fill_zero); + + +/** * truncate_inode_pages_final - truncate *all* pages before inode dies * @mapping: mapping to truncate * diff -ruw linux-4.4.115/mm/util.c linux-4.4.115-fbx/mm/util.c --- linux-4.4.115/mm/util.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/mm/util.c 2019-10-29 09:26:25.741223709 +0100 @@ -344,10 +344,12 @@ } mapping = (unsigned long)page->mapping; - if (mapping & PAGE_MAPPING_FLAGS) + if ((unsigned long)mapping & PAGE_MAPPING_ANON) return NULL; - return page->mapping; + + return (void *)((unsigned long)mapping & ~PAGE_MAPPING_FLAGS); } +EXPORT_SYMBOL(page_mapping); int overcommit_ratio_handler(struct ctl_table *table, int write, void __user *buffer, size_t *lenp, diff -ruw linux-4.4.115/mm/vmalloc.c linux-4.4.115-fbx/mm/vmalloc.c --- linux-4.4.115/mm/vmalloc.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/mm/vmalloc.c 2019-10-29 09:26:25.741223709 +0100 @@ -274,13 +274,12 @@ /*** Global kva allocator ***/ -#define VM_LAZY_FREE 0x01 -#define VM_LAZY_FREEING 0x02 #define VM_VM_AREA 0x04 static DEFINE_SPINLOCK(vmap_area_lock); /* Export for kexec only */ LIST_HEAD(vmap_area_list); +static LLIST_HEAD(vmap_purge_list); static struct rb_root vmap_area_root = RB_ROOT; /* The vmap cache globals are protected by vmap_area_lock */ @@ -291,6 +290,57 @@ static unsigned long vmap_area_pcpu_hole; +#ifdef CONFIG_ENABLE_VMALLOC_SAVING +#define POSSIBLE_VMALLOC_START PAGE_OFFSET + +#define VMALLOC_BITMAP_SIZE ((VMALLOC_END - PAGE_OFFSET) >> \ + PAGE_SHIFT) +#define VMALLOC_TO_BIT(addr) ((addr - PAGE_OFFSET) >> PAGE_SHIFT) +#define BIT_TO_VMALLOC(i) (PAGE_OFFSET + i * PAGE_SIZE) + +unsigned long total_vmalloc_size; +unsigned long vmalloc_reserved; + +DECLARE_BITMAP(possible_areas, VMALLOC_BITMAP_SIZE); + +void mark_vmalloc_reserved_area(void *x, unsigned long size) +{ + unsigned long addr = (unsigned long)x; + + bitmap_set(possible_areas, VMALLOC_TO_BIT(addr), size >> PAGE_SHIFT); + vmalloc_reserved += size; +} + +int is_vmalloc_addr(const void *x) +{ + unsigned long addr = (unsigned long)x; + + if (addr < POSSIBLE_VMALLOC_START || addr >= VMALLOC_END) + return 0; + + if (test_bit(VMALLOC_TO_BIT(addr), possible_areas)) + return 0; + + return 1; +} + +static void calc_total_vmalloc_size(void) +{ + total_vmalloc_size = VMALLOC_END - POSSIBLE_VMALLOC_START - + vmalloc_reserved; +} +#else +int is_vmalloc_addr(const void *x) +{ + unsigned long addr = (unsigned long)x; + + return addr >= VMALLOC_START && addr < VMALLOC_END; +} + +static void calc_total_vmalloc_size(void) { } +#endif +EXPORT_SYMBOL(is_vmalloc_addr); + static struct vmap_area *__find_vmap_area(unsigned long addr) { struct rb_node *n = vmap_area_root.rb_node; @@ -363,6 +413,8 @@ BUG_ON(offset_in_page(size)); BUG_ON(!is_power_of_2(align)); + might_sleep(); + va = kmalloc_node(sizeof(struct vmap_area), gfp_mask & GFP_RECLAIM_MASK, node); if (unlikely(!va)) @@ -470,8 +522,8 @@ goto retry; } if (printk_ratelimit()) - pr_warn("vmap allocation for size %lu failed: " - "use vmalloc= to increase size.\n", size); + pr_warn("vmap allocation for size %lu failed: use vmalloc= to increase size\n", + size); kfree(va); return ERR_PTR(-EBUSY); } @@ -577,6 +629,13 @@ static atomic_t vmap_lazy_nr = ATOMIC_INIT(0); +/* + * Serialize vmap purging. There is no actual criticial section protected + * by this look, but we want to avoid concurrent calls for performance + * reasons and to make the pcpu_get_vm_areas more deterministic. + */ +static DEFINE_MUTEX(vmap_purge_lock); + /* for per-CPU blocks */ static void purge_fragmented_blocks_allcpus(void); @@ -591,65 +650,40 @@ /* * Purges all lazily-freed vmap areas. - * - * If sync is 0 then don't purge if there is already a purge in progress. - * If force_flush is 1, then flush kernel TLBs between *start and *end even - * if we found no lazy vmap areas to unmap (callers can use this to optimise - * their own TLB flushing). - * Returns with *start = min(*start, lowest purged address) - * *end = max(*end, highest purged address) */ -static void __purge_vmap_area_lazy(unsigned long *start, unsigned long *end, - int sync, int force_flush) +static bool __purge_vmap_area_lazy(unsigned long start, unsigned long end) { - static DEFINE_SPINLOCK(purge_lock); - LIST_HEAD(valist); + struct llist_node *valist; struct vmap_area *va; struct vmap_area *n_va; - int nr = 0; + bool do_free = false; - /* - * If sync is 0 but force_flush is 1, we'll go sync anyway but callers - * should not expect such behaviour. This just simplifies locking for - * the case that isn't actually used at the moment anyway. - */ - if (!sync && !force_flush) { - if (!spin_trylock(&purge_lock)) - return; - } else - spin_lock(&purge_lock); + lockdep_assert_held(&vmap_purge_lock); - if (sync) - purge_fragmented_blocks_allcpus(); - - rcu_read_lock(); - list_for_each_entry_rcu(va, &vmap_area_list, list) { - if (va->flags & VM_LAZY_FREE) { - if (va->va_start < *start) - *start = va->va_start; - if (va->va_end > *end) - *end = va->va_end; - nr += (va->va_end - va->va_start) >> PAGE_SHIFT; - list_add_tail(&va->purge_list, &valist); - va->flags |= VM_LAZY_FREEING; - va->flags &= ~VM_LAZY_FREE; - } + valist = llist_del_all(&vmap_purge_list); + llist_for_each_entry(va, valist, purge_list) { + if (va->va_start < start) + start = va->va_start; + if (va->va_end > end) + end = va->va_end; + do_free = true; } - rcu_read_unlock(); - if (nr) - atomic_sub(nr, &vmap_lazy_nr); + if (!do_free) + return false; - if (nr || force_flush) - flush_tlb_kernel_range(*start, *end); + flush_tlb_kernel_range(start, end); - if (nr) { spin_lock(&vmap_area_lock); - list_for_each_entry_safe(va, n_va, &valist, purge_list) + llist_for_each_entry_safe(va, n_va, valist, purge_list) { + int nr = (va->va_end - va->va_start) >> PAGE_SHIFT; + __free_vmap_area(va); - spin_unlock(&vmap_area_lock); + atomic_sub(nr, &vmap_lazy_nr); + cond_resched_lock(&vmap_area_lock); } - spin_unlock(&purge_lock); + spin_unlock(&vmap_area_lock); + return true; } /* @@ -658,9 +692,10 @@ */ static void try_purge_vmap_area_lazy(void) { - unsigned long start = ULONG_MAX, end = 0; - - __purge_vmap_area_lazy(&start, &end, 0, 0); + if (mutex_trylock(&vmap_purge_lock)) { + __purge_vmap_area_lazy(ULONG_MAX, 0); + mutex_unlock(&vmap_purge_lock); + } } /* @@ -668,9 +703,10 @@ */ static void purge_vmap_area_lazy(void) { - unsigned long start = ULONG_MAX, end = 0; - - __purge_vmap_area_lazy(&start, &end, 1, 0); + mutex_lock(&vmap_purge_lock); + purge_fragmented_blocks_allcpus(); + __purge_vmap_area_lazy(ULONG_MAX, 0); + mutex_unlock(&vmap_purge_lock); } /* @@ -680,20 +716,16 @@ */ static void free_vmap_area_noflush(struct vmap_area *va) { - va->flags |= VM_LAZY_FREE; - atomic_add((va->va_end - va->va_start) >> PAGE_SHIFT, &vmap_lazy_nr); - if (unlikely(atomic_read(&vmap_lazy_nr) > lazy_max_pages())) - try_purge_vmap_area_lazy(); -} + int nr_lazy; -/* - * Free and unmap a vmap area, caller ensuring flush_cache_vunmap had been - * called for the correct range previously. - */ -static void free_unmap_vmap_area_noflush(struct vmap_area *va) -{ - unmap_vmap_area(va); - free_vmap_area_noflush(va); + nr_lazy = atomic_add_return((va->va_end - va->va_start) >> PAGE_SHIFT, + &vmap_lazy_nr); + + /* After this point, we may free va at any time */ + llist_add(&va->purge_list, &vmap_purge_list); + + if (unlikely(nr_lazy > lazy_max_pages())) + try_purge_vmap_area_lazy(); } /* @@ -702,7 +734,8 @@ static void free_unmap_vmap_area(struct vmap_area *va) { flush_cache_vunmap(va->va_start, va->va_end); - free_unmap_vmap_area_noflush(va); + unmap_vmap_area(va); + free_vmap_area_noflush(va); } static struct vmap_area *find_vmap_area(unsigned long addr) @@ -716,16 +749,6 @@ return va; } -static void free_unmap_vmap_area_addr(unsigned long addr) -{ - struct vmap_area *va; - - va = find_vmap_area(addr); - BUG_ON(!va); - free_unmap_vmap_area(va); -} - - /*** Per cpu kva allocator ***/ /* @@ -1046,6 +1069,8 @@ if (unlikely(!vmap_initialized)) return; + might_sleep(); + for_each_possible_cpu(cpu) { struct vmap_block_queue *vbq = &per_cpu(vmap_block_queue, cpu); struct vmap_block *vb; @@ -1070,7 +1095,11 @@ rcu_read_unlock(); } - __purge_vmap_area_lazy(&start, &end, 1, flush); + mutex_lock(&vmap_purge_lock); + purge_fragmented_blocks_allcpus(); + if (!__purge_vmap_area_lazy(start, end) && flush) + flush_tlb_kernel_range(start, end); + mutex_unlock(&vmap_purge_lock); } EXPORT_SYMBOL_GPL(vm_unmap_aliases); @@ -1083,7 +1112,9 @@ { unsigned long size = count << PAGE_SHIFT; unsigned long addr = (unsigned long)mem; + struct vmap_area *va; + might_sleep(); BUG_ON(!addr); BUG_ON(addr < VMALLOC_START); BUG_ON(addr > VMALLOC_END); @@ -1092,10 +1123,14 @@ debug_check_no_locks_freed(mem, size); vmap_debug_free_range(addr, addr+size); - if (likely(count <= VMAP_MAX_ALLOC)) + if (likely(count <= VMAP_MAX_ALLOC)) { vb_free(mem, size); - else - free_unmap_vmap_area_addr(addr); + return; + } + + va = find_vmap_area(addr); + BUG_ON(!va); + free_unmap_vmap_area(va); } EXPORT_SYMBOL(vm_unmap_ram); @@ -1144,6 +1179,33 @@ EXPORT_SYMBOL(vm_map_ram); static struct vm_struct *vmlist __initdata; + +/** + * vm_area_check_early - check if vmap area is already mapped + * @vm: vm_struct to be checked + * + * This function is used to check if the vmap area has been + * mapped already. @vm->addr, @vm->size and @vm->flags should + * contain proper values. + * + */ +int __init vm_area_check_early(struct vm_struct *vm) +{ + struct vm_struct *tmp, **p; + + BUG_ON(vmap_initialized); + for (p = &vmlist; (tmp = *p) != NULL; p = &tmp->next) { + if (tmp->addr >= vm->addr) { + if (tmp->addr < vm->addr + vm->size) + return 1; + } else { + if (tmp->addr + tmp->size > vm->addr) + return 1; + } + } + return 0; +} + /** * vm_area_add_early - add vmap area early during boot * @vm: vm_struct to add @@ -1224,7 +1286,7 @@ } vmap_area_pcpu_hole = VMALLOC_END; - + calc_total_vmalloc_size(); vmap_initialized = true; } @@ -1388,16 +1450,27 @@ */ struct vm_struct *get_vm_area(unsigned long size, unsigned long flags) { +#ifdef CONFIG_ENABLE_VMALLOC_SAVING + return __get_vm_area_node(size, 1, flags, PAGE_OFFSET, VMALLOC_END, + NUMA_NO_NODE, GFP_KERNEL, + __builtin_return_address(0)); +#else return __get_vm_area_node(size, 1, flags, VMALLOC_START, VMALLOC_END, NUMA_NO_NODE, GFP_KERNEL, __builtin_return_address(0)); +#endif } struct vm_struct *get_vm_area_caller(unsigned long size, unsigned long flags, const void *caller) { +#ifdef CONFIG_ENABLE_VMALLOC_SAVING + return __get_vm_area_node(size, 1, flags, PAGE_OFFSET, VMALLOC_END, + NUMA_NO_NODE, GFP_KERNEL, caller); +#else return __get_vm_area_node(size, 1, flags, VMALLOC_START, VMALLOC_END, NUMA_NO_NODE, GFP_KERNEL, caller); +#endif } /** @@ -1431,6 +1504,8 @@ { struct vmap_area *va; + might_sleep(); + va = find_vmap_area((unsigned long)addr); if (va && va->flags & VM_VM_AREA) { struct vm_struct *vm = va->vm; @@ -1490,6 +1565,38 @@ return; } +static inline void __vfree_deferred(const void *addr) +{ + /* + * Use raw_cpu_ptr() because this can be called from preemptible + * context. Preemption is absolutely fine here, because the llist_add() + * implementation is lockless, so it works even if we are adding to + * nother cpu's list. schedule_work() should be fine with this too. + */ + struct vfree_deferred *p = raw_cpu_ptr(&vfree_deferred); + + if (llist_add((struct llist_node *)addr, &p->list)) + schedule_work(&p->wq); +} + +/** + * vfree_atomic - release memory allocated by vmalloc() + * @addr: memory base address + * + * This one is just like vfree() but can be called in any atomic context + * except NMIs. + */ +void vfree_atomic(const void *addr) +{ + BUG_ON(in_nmi()); + + kmemleak_free(addr); + + if (!addr) + return; + __vfree_deferred(addr); +} + /** * vfree - release memory allocated by vmalloc() * @addr: memory base address @@ -1512,11 +1619,9 @@ if (!addr) return; - if (unlikely(in_interrupt())) { - struct vfree_deferred *p = this_cpu_ptr(&vfree_deferred); - if (llist_add((struct llist_node *)addr, &p->list)) - schedule_work(&p->wq); - } else + if (unlikely(in_interrupt())) + __vfree_deferred(addr); + else __vunmap(addr, 1); } EXPORT_SYMBOL(vfree); @@ -2654,6 +2759,9 @@ if (v->flags & VM_VPAGES) seq_puts(m, " vpages"); + if (v->flags & VM_LOWMEM) + seq_puts(m, " lowmem"); + show_numa_info(m, v); seq_putc(m, '\n'); return 0; diff -ruw linux-4.4.115/mm/vmpressure.c linux-4.4.115-fbx/mm/vmpressure.c --- linux-4.4.115/mm/vmpressure.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/mm/vmpressure.c 2019-01-22 16:16:28.835294691 +0100 @@ -22,6 +22,9 @@ #include #include #include +#include +#include +#include #include /* @@ -38,7 +41,7 @@ * TODO: Make the window size depend on machine size, as we do for vmstat * thresholds. Currently we set it to 512 pages (2MB for 4KB pages). */ -static const unsigned long vmpressure_win = SWAP_CLUSTER_MAX * 16; +static unsigned long vmpressure_win = SWAP_CLUSTER_MAX * 16; /* * These thresholds are used when we account memory pressure through @@ -49,6 +52,33 @@ static const unsigned int vmpressure_level_med = 60; static const unsigned int vmpressure_level_critical = 95; +static unsigned long vmpressure_scale_max = 100; +module_param_named(vmpressure_scale_max, vmpressure_scale_max, + ulong, S_IRUGO | S_IWUSR); + +/* vmpressure values >= this will be scaled based on allocstalls */ +static unsigned long allocstall_threshold = 70; +module_param_named(allocstall_threshold, allocstall_threshold, + ulong, S_IRUGO | S_IWUSR); + +static struct vmpressure global_vmpressure; +BLOCKING_NOTIFIER_HEAD(vmpressure_notifier); + +int vmpressure_notifier_register(struct notifier_block *nb) +{ + return blocking_notifier_chain_register(&vmpressure_notifier, nb); +} + +int vmpressure_notifier_unregister(struct notifier_block *nb) +{ + return blocking_notifier_chain_unregister(&vmpressure_notifier, nb); +} + +void vmpressure_notify(unsigned long pressure) +{ + blocking_notifier_call_chain(&vmpressure_notifier, pressure, NULL); +} + /* * When there are too little pages left to scan, vmpressure() may miss the * critical pressure as number of pages will be less than "window size". @@ -75,6 +105,7 @@ return container_of(work, struct vmpressure, work); } +#ifdef CONFIG_MEMCG static struct vmpressure *vmpressure_parent(struct vmpressure *vmpr) { struct cgroup_subsys_state *css = vmpressure_to_css(vmpr); @@ -85,6 +116,12 @@ return NULL; return memcg_to_vmpressure(memcg); } +#else +static struct vmpressure *vmpressure_parent(struct vmpressure *vmpr) +{ + return NULL; +} +#endif enum vmpressure_levels { VMPRESSURE_LOW = 0, @@ -108,7 +145,7 @@ return VMPRESSURE_LOW; } -static enum vmpressure_levels vmpressure_calc_level(unsigned long scanned, +static unsigned long vmpressure_calc_pressure(unsigned long scanned, unsigned long reclaimed) { unsigned long scale = scanned + reclaimed; @@ -135,7 +172,20 @@ pr_debug("%s: %3lu (s: %lu r: %lu)\n", __func__, pressure, scanned, reclaimed); - return vmpressure_level(pressure); + return pressure; +} + +static unsigned long vmpressure_account_stall(unsigned long pressure, + unsigned long stall, unsigned long scanned) +{ + unsigned long scale; + + if (pressure < allocstall_threshold) + return pressure; + + scale = ((vmpressure_scale_max - pressure) * stall) / scanned; + + return pressure + scale; } struct vmpressure_event { @@ -149,9 +199,11 @@ { struct vmpressure_event *ev; enum vmpressure_levels level; + unsigned long pressure; bool signalled = false; - level = vmpressure_calc_level(scanned, reclaimed); + pressure = vmpressure_calc_pressure(scanned, reclaimed); + level = vmpressure_level(pressure); mutex_lock(&vmpr->events_lock); @@ -203,24 +255,13 @@ } while ((vmpr = vmpressure_parent(vmpr))); } -/** - * vmpressure() - Account memory pressure through scanned/reclaimed ratio - * @gfp: reclaimer's gfp mask - * @memcg: cgroup memory controller handle - * @scanned: number of pages scanned - * @reclaimed: number of pages reclaimed - * - * This function should be called from the vmscan reclaim path to account - * "instantaneous" memory pressure (scanned/reclaimed ratio). The raw - * pressure index is then further refined and averaged over time. - * - * This function does not return any value. - */ -void vmpressure(gfp_t gfp, struct mem_cgroup *memcg, +void vmpressure_memcg(gfp_t gfp, struct mem_cgroup *memcg, unsigned long scanned, unsigned long reclaimed) { struct vmpressure *vmpr = memcg_to_vmpressure(memcg); + BUG_ON(!vmpr); + /* * Here we only want to account pressure that userland is able to * help us with. For example, suppose that DMA zone is under @@ -257,6 +298,94 @@ schedule_work(&vmpr->work); } +void calculate_vmpressure_win(void) +{ + long x; + + x = global_page_state(NR_FILE_PAGES) - + global_page_state(NR_SHMEM) - + total_swapcache_pages() + + global_page_state(NR_FREE_PAGES); + if (x < 1) + x = 1; + /* + * For low (free + cached), vmpressure window should be + * small, and high for higher values of (free + cached). + * But it should not be linear as well. This ensures + * timely vmpressure notifications when system is under + * memory pressure, and optimal number of events when + * cached is high. The sqaure root function is empirically + * found to serve the purpose. + */ + x = int_sqrt(x); + vmpressure_win = x; +} + +void vmpressure_global(gfp_t gfp, unsigned long scanned, + unsigned long reclaimed) +{ + struct vmpressure *vmpr = &global_vmpressure; + unsigned long pressure; + unsigned long stall; + + if (!(gfp & (__GFP_HIGHMEM | __GFP_MOVABLE | __GFP_IO | __GFP_FS))) + return; + + if (!scanned) + return; + + spin_lock(&vmpr->sr_lock); + if (!vmpr->scanned) + calculate_vmpressure_win(); + + vmpr->scanned += scanned; + vmpr->reclaimed += reclaimed; + + if (!current_is_kswapd()) + vmpr->stall += scanned; + + stall = vmpr->stall; + scanned = vmpr->scanned; + reclaimed = vmpr->reclaimed; + spin_unlock(&vmpr->sr_lock); + + if (scanned < vmpressure_win) + return; + + spin_lock(&vmpr->sr_lock); + vmpr->scanned = 0; + vmpr->reclaimed = 0; + vmpr->stall = 0; + spin_unlock(&vmpr->sr_lock); + + pressure = vmpressure_calc_pressure(scanned, reclaimed); + pressure = vmpressure_account_stall(pressure, stall, scanned); + vmpressure_notify(pressure); +} + +/** + * vmpressure() - Account memory pressure through scanned/reclaimed ratio + * @gfp: reclaimer's gfp mask + * @memcg: cgroup memory controller handle + * @scanned: number of pages scanned + * @reclaimed: number of pages reclaimed + * + * This function should be called from the vmscan reclaim path to account + * "instantaneous" memory pressure (scanned/reclaimed ratio). The raw + * pressure index is then further refined and averaged over time. + * + * This function does not return any value. + */ +void vmpressure(gfp_t gfp, struct mem_cgroup *memcg, + unsigned long scanned, unsigned long reclaimed) +{ + if (!memcg) + vmpressure_global(gfp, scanned, reclaimed); + + if (IS_ENABLED(CONFIG_MEMCG)) + vmpressure_memcg(gfp, memcg, scanned, reclaimed); +} + /** * vmpressure_prio() - Account memory pressure through reclaimer priority level * @gfp: reclaimer's gfp mask @@ -308,6 +437,8 @@ struct vmpressure_event *ev; int level; + BUG_ON(!vmpr); + for (level = 0; level < VMPRESSURE_NUM_LEVELS; level++) { if (!strcmp(vmpressure_str_levels[level], args)) break; @@ -347,6 +478,8 @@ struct vmpressure *vmpr = memcg_to_vmpressure(memcg); struct vmpressure_event *ev; + BUG_ON(!vmpr); + mutex_lock(&vmpr->events_lock); list_for_each_entry(ev, &vmpr->events, node) { if (ev->efd != eventfd) @@ -388,3 +521,10 @@ */ flush_work(&vmpr->work); } + +int vmpressure_global_init(void) +{ + vmpressure_init(&global_vmpressure); + return 0; +} +late_initcall(vmpressure_global_init); diff -ruw linux-4.4.115/mm/vmscan.c linux-4.4.115-fbx/mm/vmscan.c --- linux-4.4.115/mm/vmscan.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/mm/vmscan.c 2019-10-29 09:26:25.745223748 +0100 @@ -104,6 +104,13 @@ /* Number of pages freed so far during a call to shrink_zones() */ unsigned long nr_reclaimed; + + /* + * Reclaim pages from a vma. If the page is shared by other tasks + * it is zapped from a vma without reclaim so it ends up remaining + * on memory until last task zap it. + */ + struct vm_area_struct *target_vma; }; #define lru_to_page(_head) (list_entry((_head)->prev, struct page, lru)) @@ -146,6 +153,12 @@ */ unsigned long vm_total_pages; +#ifdef CONFIG_KSWAPD_CPU_AFFINITY_MASK +char *kswapd_cpu_mask = CONFIG_KSWAPD_CPU_AFFINITY_MASK; +#else +char *kswapd_cpu_mask = NULL; +#endif + static LIST_HEAD(shrinker_list); static DECLARE_RWSEM(shrinker_rwsem); @@ -278,6 +291,10 @@ long batch_size = shrinker->batch ? shrinker->batch : SHRINK_BATCH; long scanned = 0, next_deferred; + long min_cache_size = batch_size; + + if (current_is_kswapd()) + min_cache_size = 0; freeable = shrinker->count_objects(shrinker, shrinkctl); if (freeable == 0) @@ -345,7 +362,7 @@ * scanning at high prio and therefore should try to reclaim as much as * possible. */ - while (total_scan >= batch_size || + while (total_scan > min_cache_size || total_scan >= freeable) { unsigned long ret; unsigned long nr_to_scan = min(batch_size, total_scan); @@ -382,6 +399,35 @@ return freed; } +static void shrink_slab_lmk(gfp_t gfp_mask, int nid, + struct mem_cgroup *memcg, + unsigned long nr_scanned, + unsigned long nr_eligible) +{ + struct shrinker *shrinker; + + if (nr_scanned == 0) + nr_scanned = SWAP_CLUSTER_MAX; + + if (!down_read_trylock(&shrinker_rwsem)) + goto out; + + list_for_each_entry(shrinker, &shrinker_list, list) { + struct shrink_control sc = { + .gfp_mask = gfp_mask, + }; + + if (!(shrinker->flags & SHRINKER_LMK)) + continue; + + do_shrink_slab(&sc, shrinker, nr_scanned, nr_eligible); + } + + up_read(&shrinker_rwsem); +out: + cond_resched(); +} + /** * shrink_slab - shrink slab caches * @gfp_mask: allocation context @@ -443,6 +489,9 @@ .memcg = memcg, }; + if (shrinker->flags & SHRINKER_LMK) + continue; + if (memcg && !(shrinker->flags & SHRINKER_MEMCG_AWARE)) continue; @@ -912,7 +961,7 @@ struct address_space *mapping; struct page *page; int may_enter_fs; - enum page_references references = PAGEREF_RECLAIM_CLEAN; + enum page_references references = PAGEREF_RECLAIM; bool dirty, writeback; cond_resched(); @@ -924,6 +973,7 @@ goto keep; VM_BUG_ON_PAGE(PageActive(page), page); + if (zone) VM_BUG_ON_PAGE(page_zone(page) != zone, page); sc->nr_scanned++; @@ -1003,7 +1053,7 @@ /* Case 1 above */ if (current_is_kswapd() && PageReclaim(page) && - test_bit(ZONE_WRITEBACK, &zone->flags)) { + (zone && test_bit(ZONE_WRITEBACK, &zone->flags))) { nr_immediate++; goto keep_locked; @@ -1069,7 +1119,8 @@ */ if (page_mapped(page) && mapping) { switch (try_to_unmap(page, - ttu_flags|TTU_BATCH_FLUSH)) { + ttu_flags|TTU_BATCH_FLUSH, + sc->target_vma)) { case SWAP_FAIL: goto activate_locked; case SWAP_AGAIN: @@ -1089,7 +1140,8 @@ */ if (page_is_file_cache(page) && (!current_is_kswapd() || - !test_bit(ZONE_DIRTY, &zone->flags))) { + (zone && + !test_bit(ZONE_DIRTY, &zone->flags)))) { /* * Immediately reclaim when written back. * Similar in principal to deactivate_page() @@ -1201,6 +1253,13 @@ * appear not as the counts should be low */ list_add(&page->lru, &free_pages); + /* + * If pagelist are from multiple zones, we should decrease + * NR_ISOLATED_ANON + x on freed pages in here. + */ + if (!zone) + dec_zone_page_state(page, NR_ISOLATED_ANON + + page_is_file_cache(page)); continue; cull_mlocked: @@ -1212,7 +1271,7 @@ activate_locked: /* Not a candidate for swapping, so reclaim swap space. */ - if (PageSwapCache(page) && vm_swap_full()) + if (PageSwapCache(page) && vm_swap_full(page_swap_info(page))) try_to_free_swap(page); VM_BUG_ON_PAGE(PageActive(page), page); SetPageActive(page); @@ -1246,6 +1305,8 @@ .gfp_mask = GFP_KERNEL, .priority = DEF_PRIORITY, .may_unmap = 1, + /* Doesn't allow to write out dirty page */ + .may_writepage = 0, }; unsigned long ret, dummy1, dummy2, dummy3, dummy4, dummy5; struct page *page, *next; @@ -1253,7 +1314,7 @@ list_for_each_entry_safe(page, next, page_list, lru) { if (page_is_file_cache(page) && !PageDirty(page) && - !isolated_balloon_page(page)) { + !__PageMovable(page)) { ClearPageActive(page); list_move(&page->lru, &clean_pages); } @@ -1267,6 +1328,42 @@ return ret; } +#ifdef CONFIG_PROCESS_RECLAIM +unsigned long reclaim_pages_from_list(struct list_head *page_list, + struct vm_area_struct *vma) +{ + struct scan_control sc = { + .gfp_mask = GFP_KERNEL, + .priority = DEF_PRIORITY, + .may_writepage = 1, + .may_unmap = 1, + .may_swap = 1, + .target_vma = vma, + }; + + unsigned long nr_reclaimed; + struct page *page; + unsigned long dummy1, dummy2, dummy3, dummy4, dummy5; + + list_for_each_entry(page, page_list, lru) + ClearPageActive(page); + + nr_reclaimed = shrink_page_list(page_list, NULL, &sc, + TTU_UNMAP|TTU_IGNORE_ACCESS, + &dummy1, &dummy2, &dummy3, &dummy4, &dummy5, true); + + while (!list_empty(page_list)) { + page = lru_to_page(page_list); + list_del(&page->lru); + dec_zone_page_state(page, NR_ISOLATED_ANON + + page_is_file_cache(page)); + putback_lru_page(page); + } + + return nr_reclaimed; +} +#endif + /* * Attempt to remove the specified page from its LRU. Only take this page * if it is of the appropriate PageActive status. Pages which are being @@ -1453,31 +1550,32 @@ return ret; } -/* - * A direct reclaimer may isolate SWAP_CLUSTER_MAX pages from the LRU list and - * then get resheduled. When there are massive number of tasks doing page - * allocation, such sleeping direct reclaimers may keep piling up on each CPU, - * the LRU list will go small and be scanned faster than necessary, leading to - * unnecessary swapping, thrashing and OOM. - */ -static int too_many_isolated(struct zone *zone, int file, - struct scan_control *sc) +static int __too_many_isolated(struct zone *zone, int file, + struct scan_control *sc, int safe) { unsigned long inactive, isolated; - if (current_is_kswapd()) - return 0; - - if (!sane_reclaim(sc)) - return 0; - if (file) { + if (safe) { + inactive = zone_page_state_snapshot(zone, + NR_INACTIVE_FILE); + isolated = zone_page_state_snapshot(zone, + NR_ISOLATED_FILE); + } else { inactive = zone_page_state(zone, NR_INACTIVE_FILE); isolated = zone_page_state(zone, NR_ISOLATED_FILE); + } + } else { + if (safe) { + inactive = zone_page_state_snapshot(zone, + NR_INACTIVE_ANON); + isolated = zone_page_state_snapshot(zone, + NR_ISOLATED_ANON); } else { inactive = zone_page_state(zone, NR_INACTIVE_ANON); isolated = zone_page_state(zone, NR_ISOLATED_ANON); } + } /* * GFP_NOIO/GFP_NOFS callers are allowed to isolate more pages, so they @@ -1490,6 +1588,32 @@ return isolated > inactive; } +/* + * A direct reclaimer may isolate SWAP_CLUSTER_MAX pages from the LRU list and + * then get resheduled. When there are massive number of tasks doing page + * allocation, such sleeping direct reclaimers may keep piling up on each CPU, + * the LRU list will go small and be scanned faster than necessary, leading to + * unnecessary swapping, thrashing and OOM. + */ +static int too_many_isolated(struct zone *zone, int file, + struct scan_control *sc, int safe) +{ + if (current_is_kswapd()) + return 0; + + if (!sane_reclaim(sc)) + return 0; + + if (unlikely(__too_many_isolated(zone, file, sc, 0))) { + if (safe) + return __too_many_isolated(zone, file, sc, safe); + else + return 1; + } + + return 0; +} + static noinline_for_stack void putback_inactive_pages(struct lruvec *lruvec, struct list_head *page_list) { @@ -1503,6 +1627,7 @@ while (!list_empty(page_list)) { struct page *page = lru_to_page(page_list); int lru; + int file; VM_BUG_ON_PAGE(PageLRU(page), page); list_del(&page->lru); @@ -1519,8 +1644,11 @@ lru = page_lru(page); add_page_to_lru_list(page, lruvec, lru); + file = is_file_lru(lru); + if (IS_ENABLED(CONFIG_ZCACHE)) + if (file) + SetPageWasActive(page); if (is_active_lru(lru)) { - int file = is_file_lru(lru); int numpages = hpage_nr_pages(page); reclaim_stat->recent_rotated[file] += numpages; } @@ -1577,15 +1705,18 @@ unsigned long nr_immediate = 0; isolate_mode_t isolate_mode = 0; int file = is_file_lru(lru); + int safe = 0; struct zone *zone = lruvec_zone(lruvec); struct zone_reclaim_stat *reclaim_stat = &lruvec->reclaim_stat; - while (unlikely(too_many_isolated(zone, file, sc))) { + while (unlikely(too_many_isolated(zone, file, sc, safe))) { congestion_wait(BLK_RW_ASYNC, HZ/10); /* We are about to die and free our memory. Return now. */ if (fatal_signal_pending(current)) return SWAP_CLUSTER_MAX; + + safe = 1; } lru_add_drain(); @@ -1842,6 +1973,12 @@ } ClearPageActive(page); /* we are de-activating */ + if (IS_ENABLED(CONFIG_ZCACHE)) + /* + * For zcache to know whether the page is from active + * file list + */ + SetPageWasActive(page); list_add(&page->lru, &l_inactive); } @@ -2057,7 +2194,8 @@ * There is enough inactive page cache, do not reclaim * anything from the anonymous working set right now. */ - if (!inactive_file_is_low(lruvec)) { + if (!IS_ENABLED(CONFIG_BALANCE_ANON_FILE_RECLAIM) && + !inactive_file_is_low(lruvec)) { scan_balance = SCAN_FILE; goto out; } @@ -2430,15 +2568,23 @@ sc->nr_scanned - nr_scanned, zone_lru_pages); + /* + * Record the subtree's reclaim efficiency. The reclaimed + * pages from slab is excluded here because the corresponding + * scanned pages is not accounted. Moreover, freeing a page + * by slab shrinking depends on each slab's object population, + * making the cost model (i.e. scan:free) different from that + * of LRU. + */ + vmpressure(sc->gfp_mask, sc->target_mem_cgroup, + sc->nr_scanned - nr_scanned, + sc->nr_reclaimed - nr_reclaimed); + if (reclaim_state) { sc->nr_reclaimed += reclaim_state->reclaimed_slab; reclaim_state->reclaimed_slab = 0; } - vmpressure(sc->gfp_mask, sc->target_mem_cgroup, - sc->nr_scanned - nr_scanned, - sc->nr_reclaimed - nr_reclaimed); - if (sc->nr_reclaimed - nr_reclaimed) reclaimable = true; @@ -2512,6 +2658,7 @@ gfp_t orig_mask; enum zone_type requested_highidx = gfp_zone(sc->gfp_mask); bool reclaimable = false; + unsigned long lru_pages = 0; /* * If the number of buffer_heads in the machine exceeds the maximum @@ -2539,6 +2686,7 @@ * to global LRU. */ if (global_reclaim(sc)) { + lru_pages += zone_reclaimable_pages(zone); if (!cpuset_zone_allowed(zone, GFP_KERNEL | __GFP_HARDWALL)) continue; @@ -2589,6 +2737,9 @@ reclaimable = true; } + if (global_reclaim(sc)) + shrink_slab_lmk(sc->gfp_mask, 0, NULL, + sc->nr_scanned, lru_pages); /* * Restore to original mask to avoid the impact on the caller if we * promoted it to __GFP_HIGHMEM. @@ -2947,18 +3098,23 @@ } while (memcg); } -static bool zone_balanced(struct zone *zone, int order, +static bool zone_balanced(struct zone *zone, int order, bool highorder, unsigned long balance_gap, int classzone_idx) { - if (!zone_watermark_ok_safe(zone, order, high_wmark_pages(zone) + - balance_gap, classzone_idx)) - return false; + unsigned long mark = high_wmark_pages(zone) + balance_gap; - if (IS_ENABLED(CONFIG_COMPACTION) && order && compaction_suitable(zone, - order, 0, classzone_idx) == COMPACT_SKIPPED) - return false; + /* + * When checking from pgdat_balanced(), kswapd should stop and sleep + * when it reaches the high order-0 watermark and let kcompactd take + * over. Other callers such as wakeup_kswapd() want to determine the + * true high-order watermark. + */ + if (IS_ENABLED(CONFIG_COMPACTION) && !highorder) { + mark += (1UL << order); + order = 0; + } - return true; + return zone_watermark_ok_safe(zone, order, mark, classzone_idx); } /* @@ -3008,7 +3164,7 @@ continue; } - if (zone_balanced(zone, order, 0, i)) + if (zone_balanced(zone, order, false, 0, i)) balanced_pages += zone->managed_pages; else if (!order) return false; @@ -3063,9 +3219,8 @@ static bool kswapd_shrink_zone(struct zone *zone, int classzone_idx, struct scan_control *sc, - unsigned long *nr_attempted) + unsigned long lru_pages) { - int testorder = sc->order; unsigned long balance_gap; bool lowmem_pressure; @@ -3073,17 +3228,6 @@ sc->nr_to_reclaim = max(SWAP_CLUSTER_MAX, high_wmark_pages(zone)); /* - * Kswapd reclaims only single pages with compaction enabled. Trying - * too hard to reclaim until contiguous free pages have become - * available can hurt performance by evicting too much useful data - * from memory. Do not reclaim more than needed for compaction. - */ - if (IS_ENABLED(CONFIG_COMPACTION) && sc->order && - compaction_suitable(zone, sc->order, 0, classzone_idx) - != COMPACT_SKIPPED) - testorder = 0; - - /* * We put equal pressure on every zone, unless one zone has way too * many pages free already. The "too many pages" is defined as the * high wmark plus a "gap" where the gap is either the low @@ -3097,14 +3241,13 @@ * reclaim is necessary */ lowmem_pressure = (buffer_heads_over_limit && is_highmem(zone)); - if (!lowmem_pressure && zone_balanced(zone, testorder, + if (!lowmem_pressure && zone_balanced(zone, sc->order, false, balance_gap, classzone_idx)) return true; shrink_zone(zone, sc, zone_idx(zone) == classzone_idx); - - /* Account for the number of pages attempted to reclaim */ - *nr_attempted += sc->nr_to_reclaim; + shrink_slab_lmk(sc->gfp_mask, zone_to_nid(zone), NULL, + sc->nr_scanned, lru_pages); clear_bit(ZONE_WRITEBACK, &zone->flags); @@ -3115,7 +3258,7 @@ * waits. */ if (zone_reclaimable(zone) && - zone_balanced(zone, testorder, 0, classzone_idx)) { + zone_balanced(zone, sc->order, false, 0, classzone_idx)) { clear_bit(ZONE_CONGESTED, &zone->flags); clear_bit(ZONE_DIRTY, &zone->flags); } @@ -3127,7 +3270,7 @@ * For kswapd, balance_pgdat() will work across all this node's zones until * they are all at high_wmark_pages(zone). * - * Returns the final order kswapd was reclaiming at + * Returns the highest zone idx kswapd was reclaiming at * * There is special handling here for zones which are full of pinned pages. * This can happen if the pages are all mlocked, or if they are all used by @@ -3144,8 +3287,7 @@ * interoperates with the page allocator fallback scheme to ensure that aging * of pages is balanced across the zones. */ -static unsigned long balance_pgdat(pg_data_t *pgdat, int order, - int *classzone_idx) +static int balance_pgdat(pg_data_t *pgdat, int order, int classzone_idx) { int i; int end_zone = 0; /* Inclusive. 0 = ZONE_DMA */ @@ -3162,9 +3304,8 @@ count_vm_event(PAGEOUTRUN); do { - unsigned long nr_attempted = 0; bool raise_priority = true; - bool pgdat_needs_compaction = (order > 0); + unsigned long lru_pages = 0; sc.nr_reclaimed = 0; @@ -3199,7 +3340,7 @@ break; } - if (!zone_balanced(zone, order, 0, 0)) { + if (!zone_balanced(zone, order, false, 0, 0)) { end_zone = i; break; } else { @@ -3215,32 +3356,23 @@ if (i < 0) goto out; + /* + * If we're getting trouble reclaiming, start doing writepage + * even in laptop mode. + */ + if (sc.priority < DEF_PRIORITY - 2) + sc.may_writepage = 1; + for (i = 0; i <= end_zone; i++) { struct zone *zone = pgdat->node_zones + i; if (!populated_zone(zone)) continue; - /* - * If any zone is currently balanced then kswapd will - * not call compaction as it is expected that the - * necessary pages are already available. - */ - if (pgdat_needs_compaction && - zone_watermark_ok(zone, order, - low_wmark_pages(zone), - *classzone_idx, 0)) - pgdat_needs_compaction = false; + lru_pages += zone_reclaimable_pages(zone); } /* - * If we're getting trouble reclaiming, start doing writepage - * even in laptop mode. - */ - if (sc.priority < DEF_PRIORITY - 2) - sc.may_writepage = 1; - - /* * Now scan the zone in the dma->highmem direction, stopping * at the last zone which needs scanning. * @@ -3276,8 +3408,7 @@ * that that high watermark would be met at 100% * efficiency. */ - if (kswapd_shrink_zone(zone, end_zone, - &sc, &nr_attempted)) + if (kswapd_shrink_zone(zone, end_zone, &sc, lru_pages)) raise_priority = false; } @@ -3290,49 +3421,29 @@ pfmemalloc_watermark_ok(pgdat)) wake_up_all(&pgdat->pfmemalloc_wait); - /* - * Fragmentation may mean that the system cannot be rebalanced - * for high-order allocations in all zones. If twice the - * allocation size has been reclaimed and the zones are still - * not balanced then recheck the watermarks at order-0 to - * prevent kswapd reclaiming excessively. Assume that a - * process requested a high-order can direct reclaim/compact. - */ - if (order && sc.nr_reclaimed >= 2UL << order) - order = sc.order = 0; - /* Check if kswapd should be suspending */ if (try_to_freeze() || kthread_should_stop()) break; /* - * Compact if necessary and kswapd is reclaiming at least the - * high watermark number of pages as requsted - */ - if (pgdat_needs_compaction && sc.nr_reclaimed > nr_attempted) - compact_pgdat(pgdat, order); - - /* * Raise priority if scanning rate is too low or there was no * progress in reclaiming pages */ if (raise_priority || !sc.nr_reclaimed) sc.priority--; } while (sc.priority >= 1 && - !pgdat_balanced(pgdat, order, *classzone_idx)); + !pgdat_balanced(pgdat, order, classzone_idx)); out: /* - * Return the order we were reclaiming at so prepare_kswapd_sleep() - * makes a decision on the order we were last reclaiming at. However, - * if another caller entered the allocator slow path while kswapd - * was awake, order will remain at the higher level + * Return the highest zone idx we were reclaiming at so + * prepare_kswapd_sleep() makes the same decisions as here. */ - *classzone_idx = end_zone; - return order; + return end_zone; } -static void kswapd_try_to_sleep(pg_data_t *pgdat, int order, int classzone_idx) +static void kswapd_try_to_sleep(pg_data_t *pgdat, int order, + int classzone_idx, int balanced_classzone_idx) { long remaining = 0; DEFINE_WAIT(wait); @@ -3343,7 +3454,22 @@ prepare_to_wait(&pgdat->kswapd_wait, &wait, TASK_INTERRUPTIBLE); /* Try to sleep for a short interval */ - if (prepare_kswapd_sleep(pgdat, order, remaining, classzone_idx)) { + if (prepare_kswapd_sleep(pgdat, order, remaining, + balanced_classzone_idx)) { + /* + * Compaction records what page blocks it recently failed to + * isolate pages from and skips them in the future scanning. + * When kswapd is going to sleep, it is reasonable to assume + * that pages and compaction may succeed so reset the cache. + */ + reset_isolation_suitable(pgdat); + + /* + * We have freed the memory, now we should compact it to make + * allocation of the requested order possible. + */ + wakeup_kcompactd(pgdat, order, classzone_idx); + remaining = schedule_timeout(HZ/10); finish_wait(&pgdat->kswapd_wait, &wait); prepare_to_wait(&pgdat->kswapd_wait, &wait, TASK_INTERRUPTIBLE); @@ -3353,7 +3479,8 @@ * After a short sleep, check if it was a premature sleep. If not, then * go fully to sleep until explicitly woken up. */ - if (prepare_kswapd_sleep(pgdat, order, remaining, classzone_idx)) { + if (prepare_kswapd_sleep(pgdat, order, remaining, + balanced_classzone_idx)) { trace_mm_vmscan_kswapd_sleep(pgdat->node_id); /* @@ -3366,14 +3493,6 @@ */ set_pgdat_percpu_threshold(pgdat, calculate_normal_threshold); - /* - * Compaction records what page blocks it recently failed to - * isolate pages from and skips them in the future scanning. - * When kswapd is going to sleep, it is reasonable to assume - * that pages and compaction may succeed so reset the cache. - */ - reset_isolation_suitable(pgdat); - if (!kthread_should_stop()) schedule(); @@ -3403,7 +3522,6 @@ static int kswapd(void *p) { unsigned long order, new_order; - unsigned balanced_order; int classzone_idx, new_classzone_idx; int balanced_classzone_idx; pg_data_t *pgdat = (pg_data_t*)p; @@ -3416,7 +3534,7 @@ lockdep_set_current_reclaim_state(GFP_KERNEL); - if (!cpumask_empty(cpumask)) + if (kswapd_cpu_mask == NULL && !cpumask_empty(cpumask)) set_cpus_allowed_ptr(tsk, cpumask); current->reclaim_state = &reclaim_state; @@ -3436,24 +3554,19 @@ set_freezable(); order = new_order = 0; - balanced_order = 0; classzone_idx = new_classzone_idx = pgdat->nr_zones - 1; balanced_classzone_idx = classzone_idx; for ( ; ; ) { bool ret; /* - * If the last balance_pgdat was unsuccessful it's unlikely a - * new request of a similar or harder type will succeed soon - * so consider going to sleep on the basis we reclaimed at + * While we were reclaiming, there might have been another + * wakeup, so check the values. */ - if (balanced_classzone_idx >= new_classzone_idx && - balanced_order == new_order) { new_order = pgdat->kswapd_max_order; new_classzone_idx = pgdat->classzone_idx; pgdat->kswapd_max_order = 0; pgdat->classzone_idx = pgdat->nr_zones - 1; - } if (order < new_order || classzone_idx > new_classzone_idx) { /* @@ -3463,7 +3576,7 @@ order = new_order; classzone_idx = new_classzone_idx; } else { - kswapd_try_to_sleep(pgdat, balanced_order, + kswapd_try_to_sleep(pgdat, order, classzone_idx, balanced_classzone_idx); order = pgdat->kswapd_max_order; classzone_idx = pgdat->classzone_idx; @@ -3483,9 +3596,8 @@ */ if (!ret) { trace_mm_vmscan_kswapd_wake(pgdat->node_id, order); - balanced_classzone_idx = classzone_idx; - balanced_order = balance_pgdat(pgdat, order, - &balanced_classzone_idx); + balanced_classzone_idx = balance_pgdat(pgdat, order, + classzone_idx); } } @@ -3515,7 +3627,7 @@ } if (!waitqueue_active(&pgdat->kswapd_wait)) return; - if (zone_balanced(zone, order, 0, 0)) + if (zone_balanced(zone, order, true, 0, 0)) return; trace_mm_vmscan_wakeup_kswapd(pgdat->node_id, zone_idx(zone), order); @@ -3586,6 +3698,22 @@ return NOTIFY_OK; } +static int set_kswapd_cpu_mask(pg_data_t *pgdat) +{ + int ret = 0; + cpumask_t tmask; + + if (!kswapd_cpu_mask) + return 0; + + cpumask_clear(&tmask); + ret = cpumask_parse(kswapd_cpu_mask, &tmask); + if (ret) + return ret; + + return set_cpus_allowed_ptr(pgdat->kswapd, &tmask); +} + /* * This kswapd start function will be called by init and node-hot-add. * On node-hot-add, kswapd will moved to proper cpus if cpus are hot-added. @@ -3605,6 +3733,9 @@ pr_err("Failed to start kswapd on node %d\n", nid); ret = PTR_ERR(pgdat->kswapd); pgdat->kswapd = NULL; + } else if (kswapd_cpu_mask) { + if (set_kswapd_cpu_mask(pgdat)) + pr_warn("error setting kswapd cpu affinity mask\n"); } return ret; } @@ -3630,6 +3761,7 @@ swap_setup(); for_each_node_state(nid, N_MEMORY) kswapd_run(nid); + if (kswapd_cpu_mask == NULL) hotcpu_notifier(cpu_callback, 0); return 0; } diff -ruw linux-4.4.115/mm/vmstat.c linux-4.4.115-fbx/mm/vmstat.c --- linux-4.4.115/mm/vmstat.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/mm/vmstat.c 2019-10-29 09:26:25.745223748 +0100 @@ -460,7 +460,7 @@ * * The function returns the number of global counters updated. */ -static int refresh_cpu_vm_stats(void) +static int refresh_cpu_vm_stats(bool do_pagesets) { struct zone *zone; int i; @@ -484,8 +484,9 @@ #endif } } - cond_resched(); #ifdef CONFIG_NUMA + if (do_pagesets) { + cond_resched(); /* * Deal with draining the remote pageset of this * processor @@ -512,6 +513,7 @@ drain_zone_pages(zone, this_cpu_ptr(&p->pcp)); changes++; } + } #endif } changes += fold_diff(global_diff); @@ -762,6 +764,8 @@ "workingset_nodereclaim", "nr_anon_transparent_hugepages", "nr_free_cma", + "nr_swapcache", + "nr_indirectly_reclaimable", /* enum writeback_stat_item counters */ "nr_dirty_threshold", @@ -771,6 +775,7 @@ /* enum vm_event_item counters */ "pgpgin", "pgpgout", + "pgpgoutclean", "pswpin", "pswpout", @@ -824,6 +829,7 @@ "compact_stall", "compact_fail", "compact_success", + "compact_daemon_wake", #endif #ifdef CONFIG_HUGETLB_PAGE @@ -902,6 +908,7 @@ /* Walk all the zones in a node and print using a callback */ static void walk_zones_in_node(struct seq_file *m, pg_data_t *pgdat, + bool nolock, void (*print)(struct seq_file *m, pg_data_t *, struct zone *)) { struct zone *zone; @@ -912,27 +919,16 @@ if (!populated_zone(zone)) continue; + if (!nolock) spin_lock_irqsave(&zone->lock, flags); print(m, pgdat, zone); + if (!nolock) spin_unlock_irqrestore(&zone->lock, flags); } } #endif #ifdef CONFIG_PROC_FS -static char * const migratetype_names[MIGRATE_TYPES] = { - "Unmovable", - "Movable", - "Reclaimable", - "HighAtomic", -#ifdef CONFIG_CMA - "CMA", -#endif -#ifdef CONFIG_MEMORY_ISOLATION - "Isolate", -#endif -}; - static void frag_show_print(struct seq_file *m, pg_data_t *pgdat, struct zone *zone) { @@ -950,7 +946,7 @@ static int frag_show(struct seq_file *m, void *arg) { pg_data_t *pgdat = (pg_data_t *)arg; - walk_zones_in_node(m, pgdat, frag_show_print); + walk_zones_in_node(m, pgdat, false, frag_show_print); return 0; } @@ -991,7 +987,7 @@ seq_printf(m, "%6d ", order); seq_putc(m, '\n'); - walk_zones_in_node(m, pgdat, pagetypeinfo_showfree_print); + walk_zones_in_node(m, pgdat, false, pagetypeinfo_showfree_print); return 0; } @@ -1040,7 +1036,7 @@ for (mtype = 0; mtype < MIGRATE_TYPES; mtype++) seq_printf(m, "%12s ", migratetype_names[mtype]); seq_putc(m, '\n'); - walk_zones_in_node(m, pgdat, pagetypeinfo_showblockcount_print); + walk_zones_in_node(m, pgdat, false, pagetypeinfo_showblockcount_print); return 0; } @@ -1084,7 +1080,11 @@ page = pfn_to_page(pfn); if (PageBuddy(page)) { - pfn += (1UL << page_order(page)) - 1; + unsigned long freepage_order; + + freepage_order = page_order_unsafe(page); + if (freepage_order < MAX_ORDER) + pfn += (1UL << freepage_order) - 1; continue; } @@ -1131,7 +1131,7 @@ #ifdef CONFIG_PAGE_OWNER int mtype; - if (!page_owner_inited) + if (!static_branch_unlikely(&page_owner_inited)) return; drain_all_pages(NULL); @@ -1141,7 +1141,7 @@ seq_printf(m, "%12s ", migratetype_names[mtype]); seq_putc(m, '\n'); - walk_zones_in_node(m, pgdat, pagetypeinfo_showmixedcount_print); + walk_zones_in_node(m, pgdat, true, pagetypeinfo_showmixedcount_print); #endif /* CONFIG_PAGE_OWNER */ } @@ -1274,7 +1274,7 @@ static int zoneinfo_show(struct seq_file *m, void *arg) { pg_data_t *pgdat = (pg_data_t *)arg; - walk_zones_in_node(m, pgdat, zoneinfo_show_print); + walk_zones_in_node(m, pgdat, false, zoneinfo_show_print); return 0; } @@ -1391,7 +1391,7 @@ static void vmstat_update(struct work_struct *w) { - if (refresh_cpu_vm_stats()) { + if (refresh_cpu_vm_stats(true) && !cpu_isolated(smp_processor_id())) { /* * Counters were updated so we expect more updates * to occur in the future. Keep on running the @@ -1403,26 +1403,34 @@ } else { /* * We did not update any counters so the app may be in - * a mode where it does not cause counter updates. + * a mode where it does not cause counter updates or the cpu + * was isolated. * We may be uselessly running vmstat_update. * Defer the checking for differentials to the * shepherd thread on a different processor. */ - int r; - /* - * Shepherd work thread does not race since it never - * changes the bit if its zero but the cpu - * online / off line code may race if - * worker threads are still allowed during - * shutdown / startup. - */ - r = cpumask_test_and_set_cpu(smp_processor_id(), - cpu_stat_off); - VM_BUG_ON(r); + cpumask_set_cpu(smp_processor_id(), cpu_stat_off); } } /* + * Switch off vmstat processing and then fold all the remaining differentials + * until the diffs stay at zero. The function is used by NOHZ and can only be + * invoked when tick processing is not active. + */ +void quiet_vmstat(void) +{ + if (system_state != SYSTEM_RUNNING) + return; + + do { + if (!cpumask_test_and_set_cpu(smp_processor_id(), cpu_stat_off)) + cancel_delayed_work(this_cpu_ptr(&vmstat_work)); + + } while (refresh_cpu_vm_stats(false)); +} + +/* * Check if the diffs for a certain cpu indicate that * an update is needed. */ @@ -1454,7 +1462,7 @@ */ static void vmstat_shepherd(struct work_struct *w); -static DECLARE_DELAYED_WORK(shepherd, vmstat_shepherd); +static DECLARE_DEFERRABLE_WORK(shepherd, vmstat_shepherd); static void vmstat_shepherd(struct work_struct *w) { @@ -1463,7 +1471,7 @@ get_online_cpus(); /* Check processors whose vmstat worker threads have been disabled */ for_each_cpu(cpu, cpu_stat_off) - if (need_update(cpu) && + if (!cpu_isolated(cpu) && need_update(cpu) && cpumask_test_and_clear_cpu(cpu, cpu_stat_off)) queue_delayed_work_on(cpu, vmstat_wq, @@ -1627,7 +1635,7 @@ if (!node_state(pgdat->node_id, N_MEMORY)) return 0; - walk_zones_in_node(m, pgdat, unusable_show_print); + walk_zones_in_node(m, pgdat, false, unusable_show_print); return 0; } @@ -1679,7 +1687,7 @@ { pg_data_t *pgdat = (pg_data_t *)arg; - walk_zones_in_node(m, pgdat, extfrag_show_print); + walk_zones_in_node(m, pgdat, false, extfrag_show_print); return 0; } diff -ruw linux-4.4.115/mm/zsmalloc.c linux-4.4.115-fbx/mm/zsmalloc.c --- linux-4.4.115/mm/zsmalloc.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/mm/zsmalloc.c 2019-10-29 09:26:25.745223748 +0100 @@ -16,32 +16,15 @@ * struct page(s) to form a zspage. * * Usage of struct page fields: - * page->private: points to the first component (0-order) page - * page->index (union with page->freelist): offset of the first object - * starting in this page. For the first page, this is - * always 0, so we use this field (aka freelist) to point - * to the first free object in zspage. - * page->lru: links together all component pages (except the first page) - * of a zspage - * - * For _first_ page only: - * - * page->private: refers to the component page after the first page - * If the page is first_page for huge object, it stores handle. - * Look at size_class->huge. - * page->freelist: points to the first free object in zspage. - * Free objects are linked together using in-place - * metadata. - * page->objects: maximum number of objects we can store in this - * zspage (class->zspage_order * PAGE_SIZE / class->size) - * page->lru: links together first pages of various zspages. - * Basically forming list of zspages in a fullness group. - * page->mapping: class index and fullness group of the zspage - * page->inuse: the number of objects that are used in this zspage + * page->private: points to zspage + * page->freelist(index): links together all component pages of a zspage + * For the huge page, this is always 0, so we use this field + * to store handle. * * Usage of struct page flags: * PG_private: identifies the first component page * PG_private2: identifies the last component page + * PG_owner_priv_1: indentifies the huge component page * */ @@ -64,6 +47,11 @@ #include #include #include +#include +#include +#include + +#define ZSPAGE_MAGIC 0x58 /* * This must be power of 2 and greater than of equal to sizeof(link_free). @@ -86,9 +74,7 @@ * Object location (, ) is encoded as * as single (unsigned long) handle value. * - * Note that object index is relative to system - * page it is stored in, so for each sub-page belonging - * to a zspage, obj_idx starts with 0. + * Note that object index starts from 0. * * This is made more complicated by various memory models and PAE. */ @@ -147,33 +133,29 @@ * ZS_MIN_ALLOC_SIZE and ZS_SIZE_CLASS_DELTA must be multiple of ZS_ALIGN * (reason above) */ -#define ZS_SIZE_CLASS_DELTA (PAGE_SIZE >> 8) +#define ZS_SIZE_CLASS_DELTA (PAGE_SIZE >> CLASS_BITS) /* * We do not maintain any list for completely empty or full pages */ enum fullness_group { - ZS_ALMOST_FULL, - ZS_ALMOST_EMPTY, - _ZS_NR_FULLNESS_GROUPS, - ZS_EMPTY, - ZS_FULL + ZS_ALMOST_EMPTY, + ZS_ALMOST_FULL, + ZS_FULL, + NR_ZS_FULLNESS, }; enum zs_stat_type { + CLASS_EMPTY, + CLASS_ALMOST_EMPTY, + CLASS_ALMOST_FULL, + CLASS_FULL, OBJ_ALLOCATED, OBJ_USED, - CLASS_ALMOST_FULL, - CLASS_ALMOST_EMPTY, + NR_ZS_STAT_TYPE, }; -#ifdef CONFIG_ZSMALLOC_STAT -#define NR_ZS_STAT_TYPE (CLASS_ALMOST_EMPTY + 1) -#else -#define NR_ZS_STAT_TYPE (OBJ_USED + 1) -#endif - struct zs_size_stat { unsigned long objs[NR_ZS_STAT_TYPE]; }; @@ -182,6 +164,10 @@ static struct dentry *zs_stat_root; #endif +#ifdef CONFIG_COMPACTION +static struct vfsmount *zsmalloc_mnt; +#endif + /* * number of size_classes */ @@ -205,35 +191,49 @@ struct size_class { spinlock_t lock; - struct page *fullness_list[_ZS_NR_FULLNESS_GROUPS]; + struct list_head fullness_list[NR_ZS_FULLNESS]; /* * Size of objects stored in this class. Must be multiple * of ZS_ALIGN. */ int size; - unsigned int index; - + int objs_per_zspage; /* Number of PAGE_SIZE sized pages to combine to form a 'zspage' */ int pages_per_zspage; + + unsigned int index; struct zs_size_stat stats; +}; /* huge object: pages_per_zspage == 1 && maxobj_per_zspage == 1 */ - bool huge; -}; +static void SetPageHugeObject(struct page *page) +{ + SetPageOwnerPriv1(page); +} + +static void ClearPageHugeObject(struct page *page) +{ + ClearPageOwnerPriv1(page); +} + +static int PageHugeObject(struct page *page) +{ + return PageOwnerPriv1(page); +} /* * Placed within free objects to form a singly linked list. - * For every zspage, first_page->freelist gives head of this list. + * For every zspage, zspage->freeobj gives head of this list. * * This must be power of 2 and less than or equal to ZS_ALIGN */ struct link_free { union { /* - * Position of next free chunk (encodes ) + * Free object index; * It's valid for non-allocated object */ - void *next; + unsigned long next; /* * Handle of allocated object. */ @@ -246,8 +246,8 @@ struct size_class **size_class; struct kmem_cache *handle_cachep; + struct kmem_cache *zspage_cachep; - gfp_t flags; /* allocation flags used when growing pool */ atomic_long_t pages_allocated; struct zs_pool_stats stats; @@ -262,16 +262,36 @@ #ifdef CONFIG_ZSMALLOC_STAT struct dentry *stat_dentry; #endif +#ifdef CONFIG_COMPACTION + struct inode *inode; + struct work_struct free_work; +#endif }; /* * A zspage's class index and fullness group * are encoded in its (first)page->mapping */ -#define CLASS_IDX_BITS 28 -#define FULLNESS_BITS 4 -#define CLASS_IDX_MASK ((1 << CLASS_IDX_BITS) - 1) -#define FULLNESS_MASK ((1 << FULLNESS_BITS) - 1) +#define FULLNESS_BITS 2 +#define CLASS_BITS 8 +#define ISOLATED_BITS 3 +#define MAGIC_VAL_BITS 8 + +struct zspage { + struct { + unsigned int fullness:FULLNESS_BITS; + unsigned int class:CLASS_BITS; + unsigned int isolated:ISOLATED_BITS; + unsigned int magic:MAGIC_VAL_BITS; + }; + unsigned int inuse; + unsigned int freeobj; + struct page *first_page; + struct list_head list; /* fullness list */ +#ifdef CONFIG_COMPACTION + rwlock_t lock; +#endif +}; struct mapping_area { #ifdef CONFIG_PGTABLE_MAPPING @@ -281,32 +301,76 @@ #endif char *vm_addr; /* address of kmap_atomic()'ed pages */ enum zs_mapmode vm_mm; /* mapping mode */ - bool huge; }; -static int create_handle_cache(struct zs_pool *pool) +#ifdef CONFIG_COMPACTION +static int zs_register_migration(struct zs_pool *pool); +static void zs_unregister_migration(struct zs_pool *pool); +static void migrate_lock_init(struct zspage *zspage); +static void migrate_read_lock(struct zspage *zspage); +static void migrate_read_unlock(struct zspage *zspage); +static void kick_deferred_free(struct zs_pool *pool); +static void init_deferred_free(struct zs_pool *pool); +static void SetZsPageMovable(struct zs_pool *pool, struct zspage *zspage); +#else +static int zsmalloc_mount(void) { return 0; } +static void zsmalloc_unmount(void) {} +static int zs_register_migration(struct zs_pool *pool) { return 0; } +static void zs_unregister_migration(struct zs_pool *pool) {} +static void migrate_lock_init(struct zspage *zspage) {} +static void migrate_read_lock(struct zspage *zspage) {} +static void migrate_read_unlock(struct zspage *zspage) {} +static void kick_deferred_free(struct zs_pool *pool) {} +static void init_deferred_free(struct zs_pool *pool) {} +static void SetZsPageMovable(struct zs_pool *pool, struct zspage *zspage) {} +#endif + +static int create_cache(struct zs_pool *pool) { pool->handle_cachep = kmem_cache_create("zs_handle", ZS_HANDLE_SIZE, 0, 0, NULL); - return pool->handle_cachep ? 0 : 1; + if (!pool->handle_cachep) + return 1; + + pool->zspage_cachep = kmem_cache_create("zspage", sizeof(struct zspage), + 0, 0, NULL); + if (!pool->zspage_cachep) { + kmem_cache_destroy(pool->handle_cachep); + pool->handle_cachep = NULL; + return 1; } -static void destroy_handle_cache(struct zs_pool *pool) + return 0; +} + +static void destroy_cache(struct zs_pool *pool) { kmem_cache_destroy(pool->handle_cachep); + kmem_cache_destroy(pool->zspage_cachep); } -static unsigned long alloc_handle(struct zs_pool *pool) +static unsigned long cache_alloc_handle(struct zs_pool *pool, gfp_t gfp) { return (unsigned long)kmem_cache_alloc(pool->handle_cachep, - pool->flags & ~__GFP_HIGHMEM); + gfp & ~(__GFP_HIGHMEM|__GFP_MOVABLE)); } -static void free_handle(struct zs_pool *pool, unsigned long handle) +static void cache_free_handle(struct zs_pool *pool, unsigned long handle) { kmem_cache_free(pool->handle_cachep, (void *)handle); } +static struct zspage *cache_alloc_zspage(struct zs_pool *pool, gfp_t flags) +{ + return kmem_cache_alloc(pool->zspage_cachep, + flags & ~(__GFP_HIGHMEM|__GFP_MOVABLE)); +}; + +static void cache_free_zspage(struct zs_pool *pool, struct zspage *zspage) +{ + kmem_cache_free(pool->zspage_cachep, zspage); +} + static void record_obj(unsigned long handle, unsigned long obj) { /* @@ -325,7 +389,12 @@ const struct zpool_ops *zpool_ops, struct zpool *zpool) { - return zs_create_pool(name, gfp); + /* + * Ignore global gfp flags: zs_malloc() may be invoked from + * different contexts and its caller must provide a valid + * gfp mask. + */ + return zs_create_pool(name); } static void zs_zpool_destroy(void *pool) @@ -336,7 +405,7 @@ static int zs_zpool_malloc(void *pool, size_t size, gfp_t gfp, unsigned long *handle) { - *handle = zs_malloc(pool, size); + *handle = zs_malloc(pool, size, gfp); return *handle ? 0 : -1; } static void zs_zpool_free(void *pool, unsigned long handle) @@ -404,36 +473,76 @@ /* per-cpu VM mapping areas for zspage accesses that cross page boundaries */ static DEFINE_PER_CPU(struct mapping_area, zs_map_area); +static bool is_zspage_isolated(struct zspage *zspage) +{ + return zspage->isolated; +} + static int is_first_page(struct page *page) { return PagePrivate(page); } -static int is_last_page(struct page *page) +/* Protected by class->lock */ +static inline int get_zspage_inuse(struct zspage *zspage) +{ + return zspage->inuse; +} + +static inline void set_zspage_inuse(struct zspage *zspage, int val) +{ + zspage->inuse = val; +} + +static inline void mod_zspage_inuse(struct zspage *zspage, int val) +{ + zspage->inuse += val; +} + +static inline struct page *get_first_page(struct zspage *zspage) +{ + struct page *first_page = zspage->first_page; + + VM_BUG_ON_PAGE(!is_first_page(first_page), first_page); + return first_page; +} + +static inline int get_first_obj_offset(struct page *page) +{ + return page->units; +} + +static inline void set_first_obj_offset(struct page *page, int offset) +{ + page->units = offset; +} + +static inline unsigned int get_freeobj(struct zspage *zspage) +{ + return zspage->freeobj; +} + +static inline void set_freeobj(struct zspage *zspage, unsigned int obj) { - return PagePrivate2(page); + zspage->freeobj = obj; } -static void get_zspage_mapping(struct page *page, unsigned int *class_idx, +static void get_zspage_mapping(struct zspage *zspage, + unsigned int *class_idx, enum fullness_group *fullness) { - unsigned long m; - BUG_ON(!is_first_page(page)); + BUG_ON(zspage->magic != ZSPAGE_MAGIC); - m = (unsigned long)page->mapping; - *fullness = m & FULLNESS_MASK; - *class_idx = (m >> FULLNESS_BITS) & CLASS_IDX_MASK; + *fullness = zspage->fullness; + *class_idx = zspage->class; } -static void set_zspage_mapping(struct page *page, unsigned int class_idx, +static void set_zspage_mapping(struct zspage *zspage, + unsigned int class_idx, enum fullness_group fullness) { - unsigned long m; - BUG_ON(!is_first_page(page)); - - m = ((class_idx & CLASS_IDX_MASK) << FULLNESS_BITS) | - (fullness & FULLNESS_MASK); - page->mapping = (struct address_space *)m; + zspage->class = class_idx; + zspage->fullness = fullness; } /* @@ -457,23 +566,19 @@ static inline void zs_stat_inc(struct size_class *class, enum zs_stat_type type, unsigned long cnt) { - if (type < NR_ZS_STAT_TYPE) class->stats.objs[type] += cnt; } static inline void zs_stat_dec(struct size_class *class, enum zs_stat_type type, unsigned long cnt) { - if (type < NR_ZS_STAT_TYPE) class->stats.objs[type] -= cnt; } static inline unsigned long zs_stat_get(struct size_class *class, enum zs_stat_type type) { - if (type < NR_ZS_STAT_TYPE) return class->stats.objs[type]; - return 0; } #ifdef CONFIG_ZSMALLOC_STAT @@ -495,6 +600,8 @@ debugfs_remove_recursive(zs_stat_root); } +static unsigned long zs_can_compact(struct size_class *class); + static int zs_stats_size_show(struct seq_file *s, void *v) { int i; @@ -502,14 +609,15 @@ struct size_class *class; int objs_per_zspage; unsigned long class_almost_full, class_almost_empty; - unsigned long obj_allocated, obj_used, pages_used; + unsigned long obj_allocated, obj_used, pages_used, freeable; unsigned long total_class_almost_full = 0, total_class_almost_empty = 0; unsigned long total_objs = 0, total_used_objs = 0, total_pages = 0; + unsigned long total_freeable = 0; - seq_printf(s, " %5s %5s %11s %12s %13s %10s %10s %16s\n", + seq_printf(s, " %5s %5s %11s %12s %13s %10s %10s %16s %8s\n", "class", "size", "almost_full", "almost_empty", "obj_allocated", "obj_used", "pages_used", - "pages_per_zspage"); + "pages_per_zspage", "freeable"); for (i = 0; i < zs_size_classes; i++) { class = pool->size_class[i]; @@ -522,6 +630,7 @@ class_almost_empty = zs_stat_get(class, CLASS_ALMOST_EMPTY); obj_allocated = zs_stat_get(class, OBJ_ALLOCATED); obj_used = zs_stat_get(class, OBJ_USED); + freeable = zs_can_compact(class); spin_unlock(&class->lock); objs_per_zspage = get_maxobj_per_zspage(class->size, @@ -529,23 +638,25 @@ pages_used = obj_allocated / objs_per_zspage * class->pages_per_zspage; - seq_printf(s, " %5u %5u %11lu %12lu %13lu %10lu %10lu %16d\n", + seq_printf(s, " %5u %5u %11lu %12lu %13lu" + " %10lu %10lu %16d %8lu\n", i, class->size, class_almost_full, class_almost_empty, obj_allocated, obj_used, pages_used, - class->pages_per_zspage); + class->pages_per_zspage, freeable); total_class_almost_full += class_almost_full; total_class_almost_empty += class_almost_empty; total_objs += obj_allocated; total_used_objs += obj_used; total_pages += pages_used; + total_freeable += freeable; } seq_puts(s, "\n"); - seq_printf(s, " %5s %5s %11lu %12lu %13lu %10lu %10lu\n", + seq_printf(s, " %5s %5s %11lu %12lu %13lu %10lu %10lu %16s %8lu\n", "Total", "", total_class_almost_full, total_class_almost_empty, total_objs, - total_used_objs, total_pages); + total_used_objs, total_pages, "", total_freeable); return 0; } @@ -562,7 +673,7 @@ .release = single_release, }; -static int zs_pool_stat_create(const char *name, struct zs_pool *pool) +static int zs_pool_stat_create(struct zs_pool *pool, const char *name) { struct dentry *entry; @@ -602,7 +713,7 @@ { } -static inline int zs_pool_stat_create(const char *name, struct zs_pool *pool) +static inline int zs_pool_stat_create(struct zs_pool *pool, const char *name) { return 0; } @@ -620,20 +731,20 @@ * the pool (not yet implemented). This function returns fullness * status of the given page. */ -static enum fullness_group get_fullness_group(struct page *page) +static enum fullness_group get_fullness_group(struct size_class *class, + struct zspage *zspage) { - int inuse, max_objects; + int inuse, objs_per_zspage; enum fullness_group fg; - BUG_ON(!is_first_page(page)); - inuse = page->inuse; - max_objects = page->objects; + inuse = get_zspage_inuse(zspage); + objs_per_zspage = class->objs_per_zspage; if (inuse == 0) fg = ZS_EMPTY; - else if (inuse == max_objects) + else if (inuse == objs_per_zspage) fg = ZS_FULL; - else if (inuse <= 3 * max_objects / fullness_threshold_frac) + else if (inuse <= 3 * objs_per_zspage / fullness_threshold_frac) fg = ZS_ALMOST_EMPTY; else fg = ZS_ALMOST_FULL; @@ -647,59 +758,41 @@ * have. This functions inserts the given zspage into the freelist * identified by . */ -static void insert_zspage(struct page *page, struct size_class *class, +static void insert_zspage(struct size_class *class, + struct zspage *zspage, enum fullness_group fullness) { - struct page **head; - - BUG_ON(!is_first_page(page)); - - if (fullness >= _ZS_NR_FULLNESS_GROUPS) - return; + struct zspage *head; - zs_stat_inc(class, fullness == ZS_ALMOST_EMPTY ? - CLASS_ALMOST_EMPTY : CLASS_ALMOST_FULL, 1); - - head = &class->fullness_list[fullness]; - if (!*head) { - *head = page; + zs_stat_inc(class, fullness, 1); + head = list_first_entry_or_null(&class->fullness_list[fullness], + struct zspage, list); + /* + * We want to see more ZS_FULL pages and less almost empty/full. + * Put pages with higher ->inuse first. + */ + if (head) { + if (get_zspage_inuse(zspage) < get_zspage_inuse(head)) { + list_add(&zspage->list, &head->list); return; } - - /* - * We want to see more ZS_FULL pages and less almost - * empty/full. Put pages with higher ->inuse first. - */ - list_add_tail(&page->lru, &(*head)->lru); - if (page->inuse >= (*head)->inuse) - *head = page; + } + list_add(&zspage->list, &class->fullness_list[fullness]); } /* * This function removes the given zspage from the freelist identified * by . */ -static void remove_zspage(struct page *page, struct size_class *class, +static void remove_zspage(struct size_class *class, + struct zspage *zspage, enum fullness_group fullness) { - struct page **head; - - BUG_ON(!is_first_page(page)); + VM_BUG_ON(list_empty(&class->fullness_list[fullness])); + VM_BUG_ON(is_zspage_isolated(zspage)); - if (fullness >= _ZS_NR_FULLNESS_GROUPS) - return; - - head = &class->fullness_list[fullness]; - BUG_ON(!*head); - if (list_empty(&(*head)->lru)) - *head = NULL; - else if (*head == page) - *head = (struct page *)list_entry((*head)->lru.next, - struct page, lru); - - list_del_init(&page->lru); - zs_stat_dec(class, fullness == ZS_ALMOST_EMPTY ? - CLASS_ALMOST_EMPTY : CLASS_ALMOST_FULL, 1); + list_del_init(&zspage->list); + zs_stat_dec(class, fullness, 1); } /* @@ -712,21 +805,22 @@ * fullness group. */ static enum fullness_group fix_fullness_group(struct size_class *class, - struct page *page) + struct zspage *zspage) { int class_idx; enum fullness_group currfg, newfg; - BUG_ON(!is_first_page(page)); - - get_zspage_mapping(page, &class_idx, &currfg); - newfg = get_fullness_group(page); + get_zspage_mapping(zspage, &class_idx, &currfg); + newfg = get_fullness_group(class, zspage); if (newfg == currfg) goto out; - remove_zspage(page, class, currfg); - insert_zspage(page, class, newfg); - set_zspage_mapping(page, class_idx, newfg); + if (!is_zspage_isolated(zspage)) { + remove_zspage(class, zspage, currfg); + insert_zspage(class, zspage, newfg); + } + + set_zspage_mapping(zspage, class_idx, newfg); out: return newfg; @@ -768,64 +862,49 @@ return max_usedpc_order; } -/* - * A single 'zspage' is composed of many system pages which are - * linked together using fields in struct page. This function finds - * the first/head page, given any component page of a zspage. - */ -static struct page *get_first_page(struct page *page) +static struct zspage *get_zspage(struct page *page) { - if (is_first_page(page)) - return page; - else - return (struct page *)page_private(page); + struct zspage *zspage = (struct zspage *)page->private; + + BUG_ON(zspage->magic != ZSPAGE_MAGIC); + return zspage; } static struct page *get_next_page(struct page *page) { - struct page *next; + if (unlikely(PageHugeObject(page))) + return NULL; - if (is_last_page(page)) - next = NULL; - else if (is_first_page(page)) - next = (struct page *)page_private(page); - else - next = list_entry(page->lru.next, struct page, lru); + return page->freelist; +} - return next; +/** + * obj_to_location - get (, ) from encoded object value + * @page: page object resides in zspage + * @obj_idx: object index + */ +static void obj_to_location(unsigned long obj, struct page **page, + unsigned int *obj_idx) +{ + obj >>= OBJ_TAG_BITS; + *page = pfn_to_page(obj >> OBJ_INDEX_BITS); + *obj_idx = (obj & OBJ_INDEX_MASK); } -/* - * Encode as a single handle value. - * We use the least bit of handle for tagging. +/** + * location_to_obj - get obj value encoded from (, ) + * @page: page object resides in zspage + * @obj_idx: object index */ -static void *location_to_obj(struct page *page, unsigned long obj_idx) +static unsigned long location_to_obj(struct page *page, unsigned int obj_idx) { unsigned long obj; - if (!page) { - BUG_ON(obj_idx); - return NULL; - } - obj = page_to_pfn(page) << OBJ_INDEX_BITS; - obj |= ((obj_idx) & OBJ_INDEX_MASK); + obj |= obj_idx & OBJ_INDEX_MASK; obj <<= OBJ_TAG_BITS; - return (void *)obj; -} - -/* - * Decode pair from the given object handle. We adjust the - * decoded obj_idx back to its original value since it was adjusted in - * location_to_obj(). - */ -static void obj_to_location(unsigned long obj, struct page **page, - unsigned long *obj_idx) -{ - obj >>= OBJ_TAG_BITS; - *page = pfn_to_page(obj >> OBJ_INDEX_BITS); - *obj_idx = (obj & OBJ_INDEX_MASK); + return obj; } static unsigned long handle_to_obj(unsigned long handle) @@ -833,108 +912,146 @@ return *(unsigned long *)handle; } -static unsigned long obj_to_head(struct size_class *class, struct page *page, - void *obj) +static unsigned long obj_to_head(struct page *page, void *obj) { - if (class->huge) { - VM_BUG_ON(!is_first_page(page)); - return page_private(page); + if (unlikely(PageHugeObject(page))) { + VM_BUG_ON_PAGE(!is_first_page(page), page); + return page->index; } else return *(unsigned long *)obj; } -static unsigned long obj_idx_to_offset(struct page *page, - unsigned long obj_idx, int class_size) +static inline int testpin_tag(unsigned long handle) { - unsigned long off = 0; - - if (!is_first_page(page)) - off = page->index; - - return off + obj_idx * class_size; + return bit_spin_is_locked(HANDLE_PIN_BIT, (unsigned long *)handle); } static inline int trypin_tag(unsigned long handle) { - unsigned long *ptr = (unsigned long *)handle; - - return !test_and_set_bit_lock(HANDLE_PIN_BIT, ptr); + return bit_spin_trylock(HANDLE_PIN_BIT, (unsigned long *)handle); } static void pin_tag(unsigned long handle) { - while (!trypin_tag(handle)); + bit_spin_lock(HANDLE_PIN_BIT, (unsigned long *)handle); } static void unpin_tag(unsigned long handle) { - unsigned long *ptr = (unsigned long *)handle; - - clear_bit_unlock(HANDLE_PIN_BIT, ptr); + bit_spin_unlock(HANDLE_PIN_BIT, (unsigned long *)handle); } static void reset_page(struct page *page) { + __ClearPageMovable(page); clear_bit(PG_private, &page->flags); clear_bit(PG_private_2, &page->flags); set_page_private(page, 0); - page->mapping = NULL; - page->freelist = NULL; page_mapcount_reset(page); + ClearPageHugeObject(page); + page->freelist = NULL; +} + +/* + * To prevent zspage destroy during migration, zspage freeing should + * hold locks of all pages in the zspage. + */ +void lock_zspage(struct zspage *zspage) +{ + struct page *page = get_first_page(zspage); + + do { + lock_page(page); + } while ((page = get_next_page(page)) != NULL); } -static void free_zspage(struct page *first_page) +int trylock_zspage(struct zspage *zspage) { - struct page *nextp, *tmp, *head_extra; + struct page *cursor, *fail; - BUG_ON(!is_first_page(first_page)); - BUG_ON(first_page->inuse); + for (cursor = get_first_page(zspage); cursor != NULL; cursor = + get_next_page(cursor)) { + if (!trylock_page(cursor)) { + fail = cursor; + goto unlock; + } + } - head_extra = (struct page *)page_private(first_page); + return 1; +unlock: + for (cursor = get_first_page(zspage); cursor != fail; cursor = + get_next_page(cursor)) + unlock_page(cursor); - reset_page(first_page); - __free_page(first_page); + return 0; +} - /* zspage with only 1 system page */ - if (!head_extra) - return; +static void __free_zspage(struct zs_pool *pool, struct size_class *class, + struct zspage *zspage) +{ + struct page *page, *next; + enum fullness_group fg; + unsigned int class_idx; + + get_zspage_mapping(zspage, &class_idx, &fg); + + assert_spin_locked(&class->lock); + + VM_BUG_ON(get_zspage_inuse(zspage)); + VM_BUG_ON(fg != ZS_EMPTY); + + next = page = get_first_page(zspage); + do { + VM_BUG_ON_PAGE(!PageLocked(page), page); + next = get_next_page(page); + reset_page(page); + unlock_page(page); + put_page(page); + page = next; + } while (page != NULL); + + cache_free_zspage(pool, zspage); + + zs_stat_dec(class, OBJ_ALLOCATED, get_maxobj_per_zspage( + class->size, class->pages_per_zspage)); + atomic_long_sub(class->pages_per_zspage, + &pool->pages_allocated); +} + +static void free_zspage(struct zs_pool *pool, struct size_class *class, + struct zspage *zspage) +{ + VM_BUG_ON(get_zspage_inuse(zspage)); + VM_BUG_ON(list_empty(&zspage->list)); - list_for_each_entry_safe(nextp, tmp, &head_extra->lru, lru) { - list_del(&nextp->lru); - reset_page(nextp); - __free_page(nextp); + if (!trylock_zspage(zspage)) { + kick_deferred_free(pool); + return; } - reset_page(head_extra); - __free_page(head_extra); + + remove_zspage(class, zspage, ZS_EMPTY); + __free_zspage(pool, class, zspage); } /* Initialize a newly allocated zspage */ -static void init_zspage(struct page *first_page, struct size_class *class) +static void init_zspage(struct size_class *class, struct zspage *zspage) { + unsigned int freeobj = 1; unsigned long off = 0; - struct page *page = first_page; + struct page *page = get_first_page(zspage); - BUG_ON(!is_first_page(first_page)); while (page) { struct page *next_page; struct link_free *link; - unsigned int i = 1; void *vaddr; - /* - * page->index stores offset of first object starting - * in the page. For the first page, this is always 0, - * so we use first_page->index (aka ->freelist) to store - * head of corresponding zspage's freelist. - */ - if (page != first_page) - page->index = off; + set_first_obj_offset(page, off); vaddr = kmap_atomic(page); link = (struct link_free *)vaddr + off / sizeof(*link); while ((off += class->size) < PAGE_SIZE) { - link->next = location_to_obj(page, i++); + link->next = freeobj++ << OBJ_ALLOCATED_TAG; link += class->size / sizeof(*link); } @@ -944,87 +1061,108 @@ * page (if present) */ next_page = get_next_page(page); - link->next = location_to_obj(next_page, 0); + if (next_page) { + link->next = freeobj++ << OBJ_ALLOCATED_TAG; + } else { + /* + * Reset OBJ_ALLOCATED_TAG bit to last link to tell + * whether it's allocated object or not. + */ + link->next = -1 << OBJ_ALLOCATED_TAG; + } kunmap_atomic(vaddr); page = next_page; off %= PAGE_SIZE; } + + set_freeobj(zspage, 0); } -/* - * Allocate a zspage for the given size class - */ -static struct page *alloc_zspage(struct size_class *class, gfp_t flags) +static void create_page_chain(struct size_class *class, struct zspage *zspage, + struct page *pages[]) { - int i, error; - struct page *first_page = NULL, *uninitialized_var(prev_page); + int i; + struct page *page; + struct page *prev_page = NULL; + int nr_pages = class->pages_per_zspage; /* * Allocate individual pages and link them together as: - * 1. first page->private = first sub-page - * 2. all sub-pages are linked together using page->lru - * 3. each sub-page is linked to the first page using page->private + * 1. all pages are linked together using page->freelist + * 2. each sub-page point to zspage using page->private * - * For each size class, First/Head pages are linked together using - * page->lru. Also, we set PG_private to identify the first page - * (i.e. no other sub-page has this flag set) and PG_private_2 to - * identify the last page. + * we set PG_private to identify the first page (i.e. no other sub-page + * has this flag set) and PG_private_2 to identify the last page. */ - error = -ENOMEM; - for (i = 0; i < class->pages_per_zspage; i++) { - struct page *page; - - page = alloc_page(flags); - if (!page) - goto cleanup; - - INIT_LIST_HEAD(&page->lru); - if (i == 0) { /* first page */ + for (i = 0; i < nr_pages; i++) { + page = pages[i]; + set_page_private(page, (unsigned long)zspage); + page->freelist = NULL; + if (i == 0) { + zspage->first_page = page; SetPagePrivate(page); - set_page_private(page, 0); - first_page = page; - first_page->inuse = 0; + if (unlikely(class->objs_per_zspage == 1 && + class->pages_per_zspage == 1)) + SetPageHugeObject(page); + } else { + prev_page->freelist = page; } - if (i == 1) - set_page_private(first_page, (unsigned long)page); - if (i >= 1) - set_page_private(page, (unsigned long)first_page); - if (i >= 2) - list_add(&page->lru, &prev_page->lru); - if (i == class->pages_per_zspage - 1) /* last page */ + if (i == nr_pages - 1) SetPagePrivate2(page); prev_page = page; } +} + +/* + * Allocate a zspage for the given size class + */ +static struct zspage *alloc_zspage(struct zs_pool *pool, + struct size_class *class, + gfp_t gfp) +{ + int i; + struct page *pages[ZS_MAX_PAGES_PER_ZSPAGE]; + struct zspage *zspage = cache_alloc_zspage(pool, gfp); + + if (!zspage) + return NULL; - init_zspage(first_page, class); + memset(zspage, 0, sizeof(struct zspage)); + zspage->magic = ZSPAGE_MAGIC; + migrate_lock_init(zspage); - first_page->freelist = location_to_obj(first_page, 0); - /* Maximum number of objects we can store in this zspage */ - first_page->objects = class->pages_per_zspage * PAGE_SIZE / class->size; - - error = 0; /* Success */ - -cleanup: - if (unlikely(error) && first_page) { - free_zspage(first_page); - first_page = NULL; + for (i = 0; i < class->pages_per_zspage; i++) { + struct page *page; + + page = alloc_page(gfp); + if (!page) { + while (--i >= 0) + __free_page(pages[i]); + cache_free_zspage(pool, zspage); + return NULL; + } + pages[i] = page; } - return first_page; + create_page_chain(class, zspage, pages); + init_zspage(class, zspage); + + return zspage; } -static struct page *find_get_zspage(struct size_class *class) +static struct zspage *find_get_zspage(struct size_class *class) { int i; - struct page *page; + struct zspage *zspage; - for (i = 0; i < _ZS_NR_FULLNESS_GROUPS; i++) { - page = class->fullness_list[i]; - if (page) + for (i = ZS_ALMOST_FULL; i >= ZS_EMPTY; i--) { + zspage = list_first_entry_or_null(&class->fullness_list[i], + struct zspage, list); + if (zspage) break; } - return page; + return zspage; } #ifdef CONFIG_PGTABLE_MAPPING @@ -1127,11 +1265,9 @@ goto out; buf = area->vm_buf; - if (!area->huge) { buf = buf + ZS_HANDLE_SIZE; size -= ZS_HANDLE_SIZE; off += ZS_HANDLE_SIZE; - } sizes[0] = PAGE_SIZE - off; sizes[1] = size - sizes[0]; @@ -1231,11 +1367,9 @@ return true; } -static bool zspage_full(struct page *page) +static bool zspage_full(struct size_class *class, struct zspage *zspage) { - BUG_ON(!is_first_page(page)); - - return page->inuse == page->objects; + return get_zspage_inuse(zspage) == class->objs_per_zspage; } unsigned long zs_get_total_pages(struct zs_pool *pool) @@ -1261,8 +1395,10 @@ void *zs_map_object(struct zs_pool *pool, unsigned long handle, enum zs_mapmode mm) { + struct zspage *zspage; struct page *page; - unsigned long obj, obj_idx, off; + unsigned long obj, off; + unsigned int obj_idx; unsigned int class_idx; enum fullness_group fg; @@ -1271,23 +1407,26 @@ struct page *pages[2]; void *ret; - BUG_ON(!handle); - /* * Because we use per-cpu mapping areas shared among the * pools/users, we can't allow mapping in interrupt context * because it can corrupt another users mappings. */ - BUG_ON(in_interrupt()); + WARN_ON_ONCE(in_interrupt()); /* From now on, migration cannot move the object */ pin_tag(handle); obj = handle_to_obj(handle); obj_to_location(obj, &page, &obj_idx); - get_zspage_mapping(get_first_page(page), &class_idx, &fg); + zspage = get_zspage(page); + + /* migration cannot move any subpage in this zspage */ + migrate_read_lock(zspage); + + get_zspage_mapping(zspage, &class_idx, &fg); class = pool->size_class[class_idx]; - off = obj_idx_to_offset(page, obj_idx, class->size); + off = (class->size * obj_idx) & ~PAGE_MASK; area = &get_cpu_var(zs_map_area); area->vm_mm = mm; @@ -1305,7 +1444,7 @@ ret = __zs_map_object(area, pages, off, class->size); out: - if (!class->huge) + if (likely(!PageHugeObject(page))) ret += ZS_HANDLE_SIZE; return ret; @@ -1314,21 +1453,22 @@ void zs_unmap_object(struct zs_pool *pool, unsigned long handle) { + struct zspage *zspage; struct page *page; - unsigned long obj, obj_idx, off; + unsigned long obj, off; + unsigned int obj_idx; unsigned int class_idx; enum fullness_group fg; struct size_class *class; struct mapping_area *area; - BUG_ON(!handle); - obj = handle_to_obj(handle); obj_to_location(obj, &page, &obj_idx); - get_zspage_mapping(get_first_page(page), &class_idx, &fg); + zspage = get_zspage(page); + get_zspage_mapping(zspage, &class_idx, &fg); class = pool->size_class[class_idx]; - off = obj_idx_to_offset(page, obj_idx, class->size); + off = (class->size * obj_idx) & ~PAGE_MASK; area = this_cpu_ptr(&zs_map_area); if (off + class->size <= PAGE_SIZE) @@ -1343,38 +1483,50 @@ __zs_unmap_object(area, pages, off, class->size); } put_cpu_var(zs_map_area); + + migrate_read_unlock(zspage); unpin_tag(handle); } EXPORT_SYMBOL_GPL(zs_unmap_object); -static unsigned long obj_malloc(struct page *first_page, - struct size_class *class, unsigned long handle) +static unsigned long obj_malloc(struct size_class *class, + struct zspage *zspage, unsigned long handle) { + int i, nr_page, offset; unsigned long obj; struct link_free *link; struct page *m_page; - unsigned long m_objidx, m_offset; + unsigned long m_offset; void *vaddr; handle |= OBJ_ALLOCATED_TAG; - obj = (unsigned long)first_page->freelist; - obj_to_location(obj, &m_page, &m_objidx); - m_offset = obj_idx_to_offset(m_page, m_objidx, class->size); + obj = get_freeobj(zspage); + + offset = obj * class->size; + nr_page = offset >> PAGE_SHIFT; + m_offset = offset & ~PAGE_MASK; + m_page = get_first_page(zspage); + + for (i = 0; i < nr_page; i++) + m_page = get_next_page(m_page); vaddr = kmap_atomic(m_page); link = (struct link_free *)vaddr + m_offset / sizeof(*link); - first_page->freelist = link->next; - if (!class->huge) + set_freeobj(zspage, link->next >> OBJ_ALLOCATED_TAG); + if (likely(!PageHugeObject(m_page))) /* record handle in the header of allocated chunk */ link->handle = handle; else - /* record handle in first_page->private */ - set_page_private(first_page, handle); + /* record handle to page->index */ + zspage->first_page->index = handle; + kunmap_atomic(vaddr); - first_page->inuse++; + mod_zspage_inuse(zspage, 1); zs_stat_inc(class, OBJ_USED, 1); + obj = location_to_obj(m_page, obj); + return obj; } @@ -1388,16 +1540,17 @@ * otherwise 0. * Allocation requests with size > ZS_MAX_ALLOC_SIZE will fail. */ -unsigned long zs_malloc(struct zs_pool *pool, size_t size) +unsigned long zs_malloc(struct zs_pool *pool, size_t size, gfp_t gfp) { unsigned long handle, obj; struct size_class *class; - struct page *first_page; + enum fullness_group newfg; + struct zspage *zspage; if (unlikely(!size || size > ZS_MAX_ALLOC_SIZE)) return 0; - handle = alloc_handle(pool); + handle = cache_alloc_handle(pool, gfp); if (!handle) return 0; @@ -1406,71 +1559,79 @@ class = pool->size_class[get_size_class_index(size)]; spin_lock(&class->lock); - first_page = find_get_zspage(class); + zspage = find_get_zspage(class); + if (likely(zspage)) { + obj = obj_malloc(class, zspage, handle); + /* Now move the zspage to another fullness group, if required */ + fix_fullness_group(class, zspage); + record_obj(handle, obj); + spin_unlock(&class->lock); + + return handle; + } - if (!first_page) { spin_unlock(&class->lock); - first_page = alloc_zspage(class, pool->flags); - if (unlikely(!first_page)) { - free_handle(pool, handle); + + zspage = alloc_zspage(pool, class, gfp); + if (!zspage) { + cache_free_handle(pool, handle); return 0; } - set_zspage_mapping(first_page, class->index, ZS_EMPTY); + spin_lock(&class->lock); + obj = obj_malloc(class, zspage, handle); + newfg = get_fullness_group(class, zspage); + insert_zspage(class, zspage, newfg); + set_zspage_mapping(zspage, class->index, newfg); + record_obj(handle, obj); atomic_long_add(class->pages_per_zspage, &pool->pages_allocated); - - spin_lock(&class->lock); zs_stat_inc(class, OBJ_ALLOCATED, get_maxobj_per_zspage( class->size, class->pages_per_zspage)); - } - obj = obj_malloc(first_page, class, handle); - /* Now move the zspage to another fullness group, if required */ - fix_fullness_group(class, first_page); - record_obj(handle, obj); + /* We completely set up zspage so mark them as movable */ + SetZsPageMovable(pool, zspage); spin_unlock(&class->lock); return handle; } EXPORT_SYMBOL_GPL(zs_malloc); -static void obj_free(struct zs_pool *pool, struct size_class *class, - unsigned long obj) +static void obj_free(struct size_class *class, unsigned long obj) { struct link_free *link; - struct page *first_page, *f_page; - unsigned long f_objidx, f_offset; + struct zspage *zspage; + struct page *f_page; + unsigned long f_offset; + unsigned int f_objidx; void *vaddr; - BUG_ON(!obj); - obj &= ~OBJ_ALLOCATED_TAG; obj_to_location(obj, &f_page, &f_objidx); - first_page = get_first_page(f_page); - - f_offset = obj_idx_to_offset(f_page, f_objidx, class->size); + f_offset = (class->size * f_objidx) & ~PAGE_MASK; + zspage = get_zspage(f_page); vaddr = kmap_atomic(f_page); /* Insert this object in containing zspage's freelist */ link = (struct link_free *)(vaddr + f_offset); - link->next = first_page->freelist; - if (class->huge) - set_page_private(first_page, 0); + link->next = get_freeobj(zspage) << OBJ_ALLOCATED_TAG; kunmap_atomic(vaddr); - first_page->freelist = (void *)obj; - first_page->inuse--; + set_freeobj(zspage, f_objidx); + mod_zspage_inuse(zspage, -1); zs_stat_dec(class, OBJ_USED, 1); } void zs_free(struct zs_pool *pool, unsigned long handle) { - struct page *first_page, *f_page; - unsigned long obj, f_objidx; + struct zspage *zspage; + struct page *f_page; + unsigned long obj; + unsigned int f_objidx; int class_idx; struct size_class *class; enum fullness_group fullness; + bool isolated; if (unlikely(!handle)) return; @@ -1478,33 +1639,39 @@ pin_tag(handle); obj = handle_to_obj(handle); obj_to_location(obj, &f_page, &f_objidx); - first_page = get_first_page(f_page); + zspage = get_zspage(f_page); - get_zspage_mapping(first_page, &class_idx, &fullness); + migrate_read_lock(zspage); + + get_zspage_mapping(zspage, &class_idx, &fullness); class = pool->size_class[class_idx]; spin_lock(&class->lock); - obj_free(pool, class, obj); - fullness = fix_fullness_group(class, first_page); - if (fullness == ZS_EMPTY) { - zs_stat_dec(class, OBJ_ALLOCATED, get_maxobj_per_zspage( - class->size, class->pages_per_zspage)); - atomic_long_sub(class->pages_per_zspage, - &pool->pages_allocated); - free_zspage(first_page); + obj_free(class, obj); + fullness = fix_fullness_group(class, zspage); + if (fullness != ZS_EMPTY) { + migrate_read_unlock(zspage); + goto out; } + + isolated = is_zspage_isolated(zspage); + migrate_read_unlock(zspage); + /* If zspage is isolated, zs_page_putback will free the zspage */ + if (likely(!isolated)) + free_zspage(pool, class, zspage); +out: + spin_unlock(&class->lock); unpin_tag(handle); - - free_handle(pool, handle); + cache_free_handle(pool, handle); } EXPORT_SYMBOL_GPL(zs_free); -static void zs_object_copy(unsigned long dst, unsigned long src, - struct size_class *class) +static void zs_object_copy(struct size_class *class, unsigned long dst, + unsigned long src) { struct page *s_page, *d_page; - unsigned long s_objidx, d_objidx; + unsigned int s_objidx, d_objidx; unsigned long s_off, d_off; void *s_addr, *d_addr; int s_size, d_size, size; @@ -1515,8 +1682,8 @@ obj_to_location(src, &s_page, &s_objidx); obj_to_location(dst, &d_page, &d_objidx); - s_off = obj_idx_to_offset(s_page, s_objidx, class->size); - d_off = obj_idx_to_offset(d_page, d_objidx, class->size); + s_off = (class->size * s_objidx) & ~PAGE_MASK; + d_off = (class->size * d_objidx) & ~PAGE_MASK; if (s_off + class->size > PAGE_SIZE) s_size = PAGE_SIZE - s_off; @@ -1544,7 +1711,6 @@ kunmap_atomic(d_addr); kunmap_atomic(s_addr); s_page = get_next_page(s_page); - BUG_ON(!s_page); s_addr = kmap_atomic(s_page); d_addr = kmap_atomic(d_page); s_size = class->size - written; @@ -1554,7 +1720,6 @@ if (d_off >= PAGE_SIZE) { kunmap_atomic(d_addr); d_page = get_next_page(d_page); - BUG_ON(!d_page); d_addr = kmap_atomic(d_page); d_size = class->size - written; d_off = 0; @@ -1569,20 +1734,19 @@ * Find alloced object in zspage from index object and * return handle. */ -static unsigned long find_alloced_obj(struct page *page, int index, - struct size_class *class) +static unsigned long find_alloced_obj(struct size_class *class, + struct page *page, int index) { unsigned long head; int offset = 0; unsigned long handle = 0; void *addr = kmap_atomic(page); - if (!is_first_page(page)) - offset = page->index; + offset = get_first_obj_offset(page); offset += class->size * index; while (offset < PAGE_SIZE) { - head = obj_to_head(class, page, addr + offset); + head = obj_to_head(page, addr + offset); if (head & OBJ_ALLOCATED_TAG) { handle = head & ~OBJ_ALLOCATED_TAG; if (trypin_tag(handle)) @@ -1599,7 +1763,7 @@ } struct zs_compact_control { - /* Source page for migration which could be a subpage of zspage. */ + /* Source spage for migration which could be a subpage of zspage */ struct page *s_page; /* Destination page for migration which should be a first page * of zspage. */ @@ -1620,7 +1784,7 @@ int ret = 0; while (1) { - handle = find_alloced_obj(s_page, index, class); + handle = find_alloced_obj(class, s_page, index); if (!handle) { s_page = get_next_page(s_page); if (!s_page) @@ -1630,15 +1794,15 @@ } /* Stop if there is no more space */ - if (zspage_full(d_page)) { + if (zspage_full(class, get_zspage(d_page))) { unpin_tag(handle); ret = -ENOMEM; break; } used_obj = handle_to_obj(handle); - free_obj = obj_malloc(d_page, class, handle); - zs_object_copy(free_obj, used_obj, class); + free_obj = obj_malloc(class, get_zspage(d_page), handle); + zs_object_copy(class, free_obj, used_obj); index++; /* * record_obj updates handle's value to free_obj and it will @@ -1649,7 +1813,7 @@ free_obj |= BIT(HANDLE_PIN_BIT); record_obj(handle, free_obj); unpin_tag(handle); - obj_free(pool, class, used_obj); + obj_free(class, used_obj); } /* Remember last position in this iteration */ @@ -1659,70 +1823,422 @@ return ret; } -static struct page *isolate_target_page(struct size_class *class) +static struct zspage *isolate_zspage(struct size_class *class, bool source) { int i; - struct page *page; + struct zspage *zspage; + enum fullness_group fg[2] = {ZS_ALMOST_EMPTY, ZS_ALMOST_FULL}; - for (i = 0; i < _ZS_NR_FULLNESS_GROUPS; i++) { - page = class->fullness_list[i]; - if (page) { - remove_zspage(page, class, i); - break; + if (!source) { + fg[0] = ZS_ALMOST_FULL; + fg[1] = ZS_ALMOST_EMPTY; + } + + for (i = 0; i < 2; i++) { + zspage = list_first_entry_or_null(&class->fullness_list[fg[i]], + struct zspage, list); + if (zspage) { + VM_BUG_ON(is_zspage_isolated(zspage)); + remove_zspage(class, zspage, fg[i]); + return zspage; } } - return page; + return zspage; } /* - * putback_zspage - add @first_page into right class's fullness list - * @pool: target pool + * putback_zspage - add @zspage into right class's fullness list * @class: destination class - * @first_page: target page + * @zspage: target page * - * Return @fist_page's fullness_group + * Return @zspage's fullness_group */ -static enum fullness_group putback_zspage(struct zs_pool *pool, - struct size_class *class, - struct page *first_page) +static enum fullness_group putback_zspage(struct size_class *class, + struct zspage *zspage) { enum fullness_group fullness; - BUG_ON(!is_first_page(first_page)); + VM_BUG_ON(is_zspage_isolated(zspage)); - fullness = get_fullness_group(first_page); - insert_zspage(first_page, class, fullness); - set_zspage_mapping(first_page, class->index, fullness); + fullness = get_fullness_group(class, zspage); + insert_zspage(class, zspage, fullness); + set_zspage_mapping(zspage, class->index, fullness); - if (fullness == ZS_EMPTY) { - zs_stat_dec(class, OBJ_ALLOCATED, get_maxobj_per_zspage( - class->size, class->pages_per_zspage)); - atomic_long_sub(class->pages_per_zspage, - &pool->pages_allocated); + return fullness; +} + +#ifdef CONFIG_COMPACTION +static struct dentry *zs_mount(struct file_system_type *fs_type, + int flags, const char *dev_name, void *data) +{ + static const struct dentry_operations ops = { + .d_dname = simple_dname, + }; - free_zspage(first_page); + return mount_pseudo(fs_type, "zsmalloc:", NULL, &ops, ZSMALLOC_MAGIC); } - return fullness; +static struct file_system_type zsmalloc_fs = { + .name = "zsmalloc", + .mount = zs_mount, + .kill_sb = kill_anon_super, +}; + +static int zsmalloc_mount(void) +{ + int ret = 0; + + zsmalloc_mnt = kern_mount(&zsmalloc_fs); + if (IS_ERR(zsmalloc_mnt)) + ret = PTR_ERR(zsmalloc_mnt); + + return ret; +} + +static void zsmalloc_unmount(void) +{ + kern_unmount(zsmalloc_mnt); +} + +static void migrate_lock_init(struct zspage *zspage) +{ + rwlock_init(&zspage->lock); +} + +static void migrate_read_lock(struct zspage *zspage) +{ + read_lock(&zspage->lock); +} + +static void migrate_read_unlock(struct zspage *zspage) +{ + read_unlock(&zspage->lock); +} + +static void migrate_write_lock(struct zspage *zspage) +{ + write_lock(&zspage->lock); } -static struct page *isolate_source_page(struct size_class *class) +static void migrate_write_unlock(struct zspage *zspage) +{ + write_unlock(&zspage->lock); +} + +/* Number of isolated subpage for *page migration* in this zspage */ +static void inc_zspage_isolation(struct zspage *zspage) +{ + zspage->isolated++; +} + +static void dec_zspage_isolation(struct zspage *zspage) +{ + zspage->isolated--; +} + +static void replace_sub_page(struct size_class *class, struct zspage *zspage, + struct page *newpage, struct page *oldpage) +{ + struct page *page; + struct page *pages[ZS_MAX_PAGES_PER_ZSPAGE] = {NULL, }; + int idx = 0; + + page = get_first_page(zspage); + do { + if (page == oldpage) + pages[idx] = newpage; + else + pages[idx] = page; + idx++; + } while ((page = get_next_page(page)) != NULL); + + create_page_chain(class, zspage, pages); + set_first_obj_offset(newpage, get_first_obj_offset(oldpage)); + if (unlikely(PageHugeObject(oldpage))) + newpage->index = oldpage->index; + __SetPageMovable(newpage, page_mapping(oldpage)); +} + +bool zs_page_isolate(struct page *page, isolate_mode_t mode) +{ + struct zs_pool *pool; + struct size_class *class; + int class_idx; + enum fullness_group fullness; + struct zspage *zspage; + struct address_space *mapping; + + /* + * Page is locked so zspage couldn't be destroyed. For detail, look at + * lock_zspage in free_zspage. + */ + VM_BUG_ON_PAGE(!PageMovable(page), page); + VM_BUG_ON_PAGE(PageIsolated(page), page); + + zspage = get_zspage(page); + + /* + * Without class lock, fullness could be stale while class_idx is okay + * because class_idx is constant unless page is freed so we should get + * fullness again under class lock. + */ + get_zspage_mapping(zspage, &class_idx, &fullness); + mapping = page_mapping(page); + pool = mapping->private_data; + class = pool->size_class[class_idx]; + + spin_lock(&class->lock); + if (get_zspage_inuse(zspage) == 0) { + spin_unlock(&class->lock); + return false; + } + + /* zspage is isolated for object migration */ + if (list_empty(&zspage->list) && !is_zspage_isolated(zspage)) { + spin_unlock(&class->lock); + return false; + } + + /* + * If this is first time isolation for the zspage, isolate zspage from + * size_class to prevent further object allocation from the zspage. + */ + if (!list_empty(&zspage->list) && !is_zspage_isolated(zspage)) { + get_zspage_mapping(zspage, &class_idx, &fullness); + remove_zspage(class, zspage, fullness); + } + + inc_zspage_isolation(zspage); + spin_unlock(&class->lock); + + return true; +} + +int zs_page_migrate(struct address_space *mapping, struct page *newpage, + struct page *page, enum migrate_mode mode) +{ + struct zs_pool *pool; + struct size_class *class; + int class_idx; + enum fullness_group fullness; + struct zspage *zspage; + struct page *dummy; + void *s_addr, *d_addr, *addr; + int offset, pos; + unsigned long handle, head; + unsigned long old_obj, new_obj; + unsigned int obj_idx; + int ret = -EAGAIN; + + VM_BUG_ON_PAGE(!PageMovable(page), page); + VM_BUG_ON_PAGE(!PageIsolated(page), page); + + zspage = get_zspage(page); + + /* Concurrent compactor cannot migrate any subpage in zspage */ + migrate_write_lock(zspage); + get_zspage_mapping(zspage, &class_idx, &fullness); + pool = mapping->private_data; + class = pool->size_class[class_idx]; + offset = get_first_obj_offset(page); + + spin_lock(&class->lock); + if (!get_zspage_inuse(zspage)) { + ret = -EBUSY; + goto unlock_class; + } + + pos = offset; + s_addr = kmap_atomic(page); + while (pos < PAGE_SIZE) { + head = obj_to_head(page, s_addr + pos); + if (head & OBJ_ALLOCATED_TAG) { + handle = head & ~OBJ_ALLOCATED_TAG; + if (!trypin_tag(handle)) + goto unpin_objects; + } + pos += class->size; + } + + /* + * Here, any user cannot access all objects in the zspage so let's move. + */ + d_addr = kmap_atomic(newpage); + memcpy(d_addr, s_addr, PAGE_SIZE); + kunmap_atomic(d_addr); + + for (addr = s_addr + offset; addr < s_addr + pos; + addr += class->size) { + head = obj_to_head(page, addr); + if (head & OBJ_ALLOCATED_TAG) { + handle = head & ~OBJ_ALLOCATED_TAG; + if (!testpin_tag(handle)) + BUG(); + + old_obj = handle_to_obj(handle); + obj_to_location(old_obj, &dummy, &obj_idx); + new_obj = (unsigned long)location_to_obj(newpage, + obj_idx); + new_obj |= BIT(HANDLE_PIN_BIT); + record_obj(handle, new_obj); + } + } + + replace_sub_page(class, zspage, newpage, page); + get_page(newpage); + + dec_zspage_isolation(zspage); + + /* + * Page migration is done so let's putback isolated zspage to + * the list if @page is final isolated subpage in the zspage. + */ + if (!is_zspage_isolated(zspage)) + putback_zspage(class, zspage); + + reset_page(page); + put_page(page); + page = newpage; + + ret = MIGRATEPAGE_SUCCESS; +unpin_objects: + for (addr = s_addr + offset; addr < s_addr + pos; + addr += class->size) { + head = obj_to_head(page, addr); + if (head & OBJ_ALLOCATED_TAG) { + handle = head & ~OBJ_ALLOCATED_TAG; + if (!testpin_tag(handle)) + BUG(); + unpin_tag(handle); + } + } + kunmap_atomic(s_addr); +unlock_class: + spin_unlock(&class->lock); + migrate_write_unlock(zspage); + + return ret; +} + +void zs_page_putback(struct page *page) +{ + struct zs_pool *pool; + struct size_class *class; + int class_idx; + enum fullness_group fg; + struct address_space *mapping; + struct zspage *zspage; + + VM_BUG_ON_PAGE(!PageMovable(page), page); + VM_BUG_ON_PAGE(!PageIsolated(page), page); + + zspage = get_zspage(page); + get_zspage_mapping(zspage, &class_idx, &fg); + mapping = page_mapping(page); + pool = mapping->private_data; + class = pool->size_class[class_idx]; + + spin_lock(&class->lock); + dec_zspage_isolation(zspage); + if (!is_zspage_isolated(zspage)) { + fg = putback_zspage(class, zspage); + /* + * Due to page_lock, we cannot free zspage immediately + * so let's defer. + */ + if (fg == ZS_EMPTY) + schedule_work(&pool->free_work); + } + spin_unlock(&class->lock); +} + +const struct address_space_operations zsmalloc_aops = { + .isolate_page = zs_page_isolate, + .migratepage = zs_page_migrate, + .putback_page = zs_page_putback, +}; + +static int zs_register_migration(struct zs_pool *pool) +{ + pool->inode = alloc_anon_inode(zsmalloc_mnt->mnt_sb); + if (IS_ERR(pool->inode)) { + pool->inode = NULL; + return 1; + } + + pool->inode->i_mapping->private_data = pool; + pool->inode->i_mapping->a_ops = &zsmalloc_aops; + return 0; +} + +static void zs_unregister_migration(struct zs_pool *pool) +{ + flush_work(&pool->free_work); + if (pool->inode) + iput(pool->inode); +} + +/* + * Caller should hold page_lock of all pages in the zspage + * In here, we cannot use zspage meta data. + */ +static void async_free_zspage(struct work_struct *work) { int i; - struct page *page = NULL; + struct size_class *class; + unsigned int class_idx; + enum fullness_group fullness; + struct zspage *zspage, *tmp; + LIST_HEAD(free_pages); + struct zs_pool *pool = container_of(work, struct zs_pool, + free_work); - for (i = ZS_ALMOST_EMPTY; i >= ZS_ALMOST_FULL; i--) { - page = class->fullness_list[i]; - if (!page) + for (i = 0; i < zs_size_classes; i++) { + class = pool->size_class[i]; + if (class->index != i) continue; - remove_zspage(page, class, i); - break; + spin_lock(&class->lock); + list_splice_init(&class->fullness_list[ZS_EMPTY], &free_pages); + spin_unlock(&class->lock); } - return page; + + list_for_each_entry_safe(zspage, tmp, &free_pages, list) { + list_del(&zspage->list); + lock_zspage(zspage); + + get_zspage_mapping(zspage, &class_idx, &fullness); + VM_BUG_ON(fullness != ZS_EMPTY); + class = pool->size_class[class_idx]; + spin_lock(&class->lock); + __free_zspage(pool, pool->size_class[class_idx], zspage); + spin_unlock(&class->lock); + } +}; + +static void kick_deferred_free(struct zs_pool *pool) +{ + schedule_work(&pool->free_work); +} + +static void init_deferred_free(struct zs_pool *pool) +{ + INIT_WORK(&pool->free_work, async_free_zspage); +} + +static void SetZsPageMovable(struct zs_pool *pool, struct zspage *zspage) +{ + struct page *page = get_first_page(zspage); + + do { + WARN_ON(!trylock_page(page)); + __SetPageMovable(page, pool->inode->i_mapping); + unlock_page(page); + } while ((page = get_next_page(page)) != NULL); } +#endif /* * @@ -1748,22 +2264,20 @@ static void __zs_compact(struct zs_pool *pool, struct size_class *class) { struct zs_compact_control cc; - struct page *src_page; - struct page *dst_page = NULL; + struct zspage *src_zspage; + struct zspage *dst_zspage = NULL; spin_lock(&class->lock); - while ((src_page = isolate_source_page(class))) { - - BUG_ON(!is_first_page(src_page)); + while ((src_zspage = isolate_zspage(class, true))) { if (!zs_can_compact(class)) break; cc.index = 0; - cc.s_page = src_page; + cc.s_page = get_first_page(src_zspage); - while ((dst_page = isolate_target_page(class))) { - cc.d_page = dst_page; + while ((dst_zspage = isolate_zspage(class, false))) { + cc.d_page = get_first_page(dst_zspage); /* * If there is no more space in dst_page, resched * and see if anyone had allocated another zspage. @@ -1771,23 +2285,25 @@ if (!migrate_zspage(pool, class, &cc)) break; - putback_zspage(pool, class, dst_page); + putback_zspage(class, dst_zspage); } /* Stop if we couldn't find slot */ - if (dst_page == NULL) + if (dst_zspage == NULL) break; - putback_zspage(pool, class, dst_page); - if (putback_zspage(pool, class, src_page) == ZS_EMPTY) + putback_zspage(class, dst_zspage); + if (putback_zspage(class, src_zspage) == ZS_EMPTY) { + free_zspage(pool, class, src_zspage); pool->stats.pages_compacted += class->pages_per_zspage; + } spin_unlock(&class->lock); cond_resched(); spin_lock(&class->lock); } - if (src_page) - putback_zspage(pool, class, src_page); + if (src_zspage) + putback_zspage(class, src_zspage); spin_unlock(&class->lock); } @@ -1884,7 +2400,7 @@ * On success, a pointer to the newly created pool is returned, * otherwise NULL. */ -struct zs_pool *zs_create_pool(const char *name, gfp_t flags) +struct zs_pool *zs_create_pool(const char *name) { int i; struct zs_pool *pool; @@ -1894,6 +2410,7 @@ if (!pool) return NULL; + init_deferred_free(pool); pool->size_class = kcalloc(zs_size_classes, sizeof(struct size_class *), GFP_KERNEL); if (!pool->size_class) { @@ -1905,7 +2422,7 @@ if (!pool->name) goto err; - if (create_handle_cache(pool)) + if (create_cache(pool)) goto err; /* @@ -1916,6 +2433,7 @@ int size; int pages_per_zspage; struct size_class *class; + int fullness = 0; size = ZS_MIN_ALLOC_SIZE + i * ZS_SIZE_CLASS_DELTA; if (size > ZS_MAX_ALLOC_SIZE) @@ -1945,18 +2463,21 @@ class->size = size; class->index = i; class->pages_per_zspage = pages_per_zspage; - if (pages_per_zspage == 1 && - get_maxobj_per_zspage(size, pages_per_zspage) == 1) - class->huge = true; + class->objs_per_zspage = class->pages_per_zspage * + PAGE_SIZE / class->size; spin_lock_init(&class->lock); pool->size_class[i] = class; + for (fullness = ZS_EMPTY; fullness < NR_ZS_FULLNESS; + fullness++) + INIT_LIST_HEAD(&class->fullness_list[fullness]); prev_class = class; } - pool->flags = flags; + if (zs_pool_stat_create(pool, name)) + goto err; - if (zs_pool_stat_create(name, pool)) + if (zs_register_migration(pool)) goto err; /* @@ -1978,6 +2499,7 @@ int i; zs_unregister_shrinker(pool); + zs_unregister_migration(pool); zs_pool_stat_destroy(pool); for (i = 0; i < zs_size_classes; i++) { @@ -1990,8 +2512,8 @@ if (class->index != i) continue; - for (fg = 0; fg < _ZS_NR_FULLNESS_GROUPS; fg++) { - if (class->fullness_list[fg]) { + for (fg = ZS_EMPTY; fg < NR_ZS_FULLNESS; fg++) { + if (!list_empty(&class->fullness_list[fg])) { pr_info("Freeing non-empty class with size %db, fullness group %d\n", class->size, fg); } @@ -1999,7 +2521,7 @@ kfree(class); } - destroy_handle_cache(pool); + destroy_cache(pool); kfree(pool->size_class); kfree(pool->name); kfree(pool); @@ -2008,7 +2530,13 @@ static int __init zs_init(void) { - int ret = zs_register_cpu_notifier(); + int ret; + + ret = zsmalloc_mount(); + if (ret) + goto out; + + ret = zs_register_cpu_notifier(); if (ret) goto notifier_fail; @@ -2032,7 +2560,8 @@ #endif notifier_fail: zs_unregister_cpu_notifier(); - + zsmalloc_unmount(); +out: return ret; } @@ -2041,6 +2570,7 @@ #ifdef CONFIG_ZPOOL zpool_unregister_driver(&zs_zpool_driver); #endif + zsmalloc_unmount(); zs_unregister_cpu_notifier(); zs_stat_exit(); diff -ruw linux-4.4.115/net/8021q/vlan.c linux-4.4.115-fbx/net/8021q/vlan.c --- linux-4.4.115/net/8021q/vlan.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/net/8021q/vlan.c 2019-01-22 16:16:28.843294763 +0100 @@ -203,7 +203,7 @@ /* Attach a VLAN device to a mac address (ie Ethernet Card). * Returns 0 if the device was created or a negative error code otherwise. */ -static int register_vlan_device(struct net_device *real_dev, u16 vlan_id) +int register_vlan_device(struct net_device *real_dev, u16 vlan_id) { struct net_device *new_dev; struct vlan_dev_priv *vlan; diff -ruw linux-4.4.115/net/bluetooth/af_bluetooth.c linux-4.4.115-fbx/net/bluetooth/af_bluetooth.c --- linux-4.4.115/net/bluetooth/af_bluetooth.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/net/bluetooth/af_bluetooth.c 2019-01-22 16:16:28.867294981 +0100 @@ -106,11 +106,40 @@ } EXPORT_SYMBOL(bt_sock_unregister); +#ifdef CONFIG_PARANOID_NETWORK +static inline int current_has_bt_admin(void) +{ + return !current_euid(); +} + +static inline int current_has_bt(void) +{ + return current_has_bt_admin(); +} +# else +static inline int current_has_bt_admin(void) +{ + return 1; +} + +static inline int current_has_bt(void) +{ + return 1; +} +#endif + static int bt_sock_create(struct net *net, struct socket *sock, int proto, int kern) { int err; + if (proto == BTPROTO_RFCOMM || proto == BTPROTO_SCO || + proto == BTPROTO_L2CAP) { + if (!current_has_bt()) + return -EPERM; + } else if (!current_has_bt_admin()) + return -EPERM; + if (net != &init_net) return -EAFNOSUPPORT; @@ -154,7 +183,7 @@ void bt_accept_enqueue(struct sock *parent, struct sock *sk) { - BT_DBG("parent %p, sk %p", parent, sk); + BT_DBG("parent %pK, sk %pK", parent, sk); sock_hold(sk); list_add_tail(&bt_sk(sk)->accept_q, &bt_sk(parent)->accept_q); @@ -165,7 +194,7 @@ void bt_accept_unlink(struct sock *sk) { - BT_DBG("sk %p state %d", sk, sk->sk_state); + BT_DBG("sk %pK state %d", sk, sk->sk_state); list_del_init(&bt_sk(sk)->accept_q); bt_sk(sk)->parent->sk_ack_backlog--; @@ -179,7 +208,7 @@ struct list_head *p, *n; struct sock *sk; - BT_DBG("parent %p", parent); + BT_DBG("parent %pK", parent); list_for_each_safe(p, n, &bt_sk(parent)->accept_q) { sk = (struct sock *) list_entry(p, struct bt_sock, accept_q); @@ -219,7 +248,7 @@ size_t copied; int err; - BT_DBG("sock %p sk %p len %zu", sock, sk, len); + BT_DBG("sock %pK sk %pK len %zu", sock, sk, len); if (flags & MSG_OOB) return -EOPNOTSUPP; @@ -294,7 +323,7 @@ if (flags & MSG_OOB) return -EOPNOTSUPP; - BT_DBG("sk %p size %zu", sk, size); + BT_DBG("sk %pK size %zu", sk, size); lock_sock(sk); @@ -410,7 +439,7 @@ struct sock *sk = sock->sk; unsigned int mask = 0; - BT_DBG("sock %p, sk %p", sock, sk); + BT_DBG("sock %pK, sk %pK", sock, sk); poll_wait(file, sk_sleep(sk), wait); @@ -454,7 +483,7 @@ long amount; int err; - BT_DBG("sk %p cmd %x arg %lx", sk, cmd, arg); + BT_DBG("sk %pK cmd %x arg %lx", sk, cmd, arg); switch (cmd) { case TIOCOUTQ: @@ -501,7 +530,7 @@ DECLARE_WAITQUEUE(wait, current); int err = 0; - BT_DBG("sk %p", sk); + BT_DBG("sk %pK", sk); add_wait_queue(sk_sleep(sk), &wait); set_current_state(TASK_INTERRUPTIBLE); @@ -538,7 +567,7 @@ unsigned long timeo; int err = 0; - BT_DBG("sk %p", sk); + BT_DBG("sk %pK", sk); timeo = sock_sndtimeo(sk, flags & O_NONBLOCK); diff -ruw linux-4.4.115/net/bluetooth/hci_conn.c linux-4.4.115-fbx/net/bluetooth/hci_conn.c --- linux-4.4.115/net/bluetooth/hci_conn.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/net/bluetooth/hci_conn.c 2019-10-29 09:26:25.765223944 +0100 @@ -141,7 +141,7 @@ struct hci_dev *hdev = conn->hdev; struct hci_conn *c = NULL; - BT_DBG("%s hcon %p", hdev->name, conn); + BT_DBG("%s hcon %pK", hdev->name, conn); hci_dev_lock(hdev); @@ -165,7 +165,7 @@ static void hci_connect_le_scan_remove(struct hci_conn *conn) { - BT_DBG("%s hcon %p", conn->hdev->name, conn); + BT_DBG("%s hcon %pK", conn->hdev->name, conn); /* We can't call hci_conn_del/hci_conn_cleanup here since that * could deadlock with another hci_conn_del() call that's holding @@ -187,7 +187,7 @@ struct inquiry_entry *ie; struct hci_cp_create_conn cp; - BT_DBG("hcon %p", conn); + BT_DBG("hcon %pK", conn); conn->state = BT_CONNECT; conn->out = true; @@ -226,7 +226,7 @@ int hci_disconnect(struct hci_conn *conn, __u8 reason) { - BT_DBG("hcon %p", conn); + BT_DBG("hcon %pK", conn); /* When we are master of an established connection and it enters * the disconnect timeout, then go ahead and try to read the @@ -251,7 +251,7 @@ struct hci_dev *hdev = conn->hdev; struct hci_cp_add_sco cp; - BT_DBG("hcon %p", conn); + BT_DBG("hcon %pK", conn); conn->state = BT_CONNECT; conn->out = true; @@ -270,7 +270,7 @@ struct hci_cp_setup_sync_conn cp; const struct sco_param *param; - BT_DBG("hcon %p", conn); + BT_DBG("hcon %pK", conn); conn->state = BT_CONNECT; conn->out = true; @@ -356,7 +356,7 @@ struct hci_dev *hdev = conn->hdev; struct hci_cp_le_start_enc cp; - BT_DBG("hcon %p", conn); + BT_DBG("hcon %pK", conn); memset(&cp, 0, sizeof(cp)); @@ -376,7 +376,7 @@ if (!sco) return; - BT_DBG("hcon %p", conn); + BT_DBG("hcon %pK", conn); if (!status) { if (lmp_esco_capable(conn->hdev)) @@ -395,7 +395,7 @@ disc_work.work); int refcnt = atomic_read(&conn->refcnt); - BT_DBG("hcon %p state %s", conn, state_to_string(conn->state)); + BT_DBG("hcon %pK state %s", conn, state_to_string(conn->state)); WARN_ON(refcnt < 0); @@ -426,7 +426,7 @@ idle_work.work); struct hci_dev *hdev = conn->hdev; - BT_DBG("hcon %p mode %d", conn, conn->mode); + BT_DBG("hcon %pK mode %d", conn, conn->mode); if (!lmp_sniff_capable(hdev) || !lmp_sniff_capable(conn)) return; @@ -566,7 +566,7 @@ { struct hci_dev *hdev = conn->hdev; - BT_DBG("%s hcon %p handle %d", hdev->name, conn, conn->handle); + BT_DBG("%s hcon %pK handle %d", hdev->name, conn, conn->handle); cancel_delayed_work_sync(&conn->disc_work); cancel_delayed_work_sync(&conn->auto_accept_work); @@ -691,6 +691,9 @@ conn = hci_lookup_le_connect(hdev); if (!status) { + if (WARN_ON(!conn)) + goto done; + hci_connect_le_scan_cleanup(conn); goto done; } @@ -1147,7 +1150,7 @@ /* Check link security requirement */ int hci_conn_check_link_mode(struct hci_conn *conn) { - BT_DBG("hcon %p", conn); + BT_DBG("hcon %pK", conn); /* In Secure Connections Only mode, it is required that Secure * Connections is used and the link is encrypted with AES-CCM @@ -1170,7 +1173,7 @@ /* Authenticate remote device */ static int hci_conn_auth(struct hci_conn *conn, __u8 sec_level, __u8 auth_type) { - BT_DBG("hcon %p", conn); + BT_DBG("hcon %pK", conn); if (conn->pending_sec_level > sec_level) sec_level = conn->pending_sec_level; @@ -1207,7 +1210,7 @@ /* Encrypt the the link */ static void hci_conn_encrypt(struct hci_conn *conn) { - BT_DBG("hcon %p", conn); + BT_DBG("hcon %pK", conn); if (!test_and_set_bit(HCI_CONN_ENCRYPT_PEND, &conn->flags)) { struct hci_cp_set_conn_encrypt cp; @@ -1222,7 +1225,7 @@ int hci_conn_security(struct hci_conn *conn, __u8 sec_level, __u8 auth_type, bool initiator) { - BT_DBG("hcon %p", conn); + BT_DBG("hcon %pK", conn); if (conn->type == LE_LINK) return smp_conn_security(conn, sec_level); @@ -1291,7 +1294,7 @@ /* Check secure link requirement */ int hci_conn_check_secure(struct hci_conn *conn, __u8 sec_level) { - BT_DBG("hcon %p", conn); + BT_DBG("hcon %pK", conn); /* Accept if non-secure or higher security level is required */ if (sec_level != BT_SECURITY_HIGH && sec_level != BT_SECURITY_FIPS) @@ -1310,7 +1313,7 @@ /* Switch role */ int hci_conn_switch_role(struct hci_conn *conn, __u8 role) { - BT_DBG("hcon %p", conn); + BT_DBG("hcon %pK", conn); if (role == conn->role) return 1; @@ -1331,7 +1334,7 @@ { struct hci_dev *hdev = conn->hdev; - BT_DBG("hcon %p mode %d", conn, conn->mode); + BT_DBG("hcon %pK mode %d", conn, conn->mode); if (conn->mode != HCI_CM_SNIFF) goto timer; @@ -1511,7 +1514,7 @@ struct hci_dev *hdev = conn->hdev; struct hci_chan *chan; - BT_DBG("%s hcon %p", hdev->name, conn); + BT_DBG("%s hcon %pK", hdev->name, conn); if (test_bit(HCI_CONN_DROP, &conn->flags)) { BT_DBG("Refusing to create new hci_chan"); @@ -1536,7 +1539,7 @@ struct hci_conn *conn = chan->conn; struct hci_dev *hdev = conn->hdev; - BT_DBG("%s hcon %p chan %p", hdev->name, conn, chan); + BT_DBG("%s hcon %pK chan %pK", hdev->name, conn, chan); list_del_rcu(&chan->list); @@ -1555,7 +1558,7 @@ { struct hci_chan *chan, *n; - BT_DBG("hcon %p", conn); + BT_DBG("hcon %pK", conn); list_for_each_entry_safe(chan, n, &conn->chan_list, list) hci_chan_del(chan); diff -ruw linux-4.4.115/net/bluetooth/hci_core.c linux-4.4.115-fbx/net/bluetooth/hci_core.c --- linux-4.4.115/net/bluetooth/hci_core.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/net/bluetooth/hci_core.c 2019-10-29 09:26:25.765223944 +0100 @@ -1131,7 +1131,7 @@ struct discovery_state *cache = &hdev->discovery; struct inquiry_entry *e; - BT_DBG("cache %p, %pMR", cache, bdaddr); + BT_DBG("cache %pK, %pMR", cache, bdaddr); list_for_each_entry(e, &cache->all, all) { if (!bacmp(&e->data.bdaddr, bdaddr)) @@ -1147,7 +1147,7 @@ struct discovery_state *cache = &hdev->discovery; struct inquiry_entry *e; - BT_DBG("cache %p, %pMR", cache, bdaddr); + BT_DBG("cache %pK, %pMR", cache, bdaddr); list_for_each_entry(e, &cache->unknown, list) { if (!bacmp(&e->data.bdaddr, bdaddr)) @@ -1164,7 +1164,7 @@ struct discovery_state *cache = &hdev->discovery; struct inquiry_entry *e; - BT_DBG("cache %p bdaddr %pMR state %d", cache, bdaddr, state); + BT_DBG("cache %pK bdaddr %pMR state %d", cache, bdaddr, state); list_for_each_entry(e, &cache->resolve, list) { if (!bacmp(bdaddr, BDADDR_ANY) && e->name_state == state) @@ -1202,7 +1202,7 @@ struct inquiry_entry *ie; u32 flags = 0; - BT_DBG("cache %p, %pMR", cache, &data->bdaddr); + BT_DBG("cache %pK, %pMR", cache, &data->bdaddr); hci_remove_remote_oob_data(hdev, &data->bdaddr, BDADDR_BREDR); @@ -1281,7 +1281,7 @@ copied++; } - BT_DBG("cache %p, copied %d", cache, copied); + BT_DBG("cache %pK, copied %d", cache, copied); return copied; } @@ -1402,7 +1402,7 @@ { int ret = 0; - BT_DBG("%s %p", hdev->name, hdev); + BT_DBG("%s %pK", hdev->name, hdev); hci_req_lock(hdev); @@ -1639,7 +1639,7 @@ { bool auto_off; - BT_DBG("%s %p", hdev->name, hdev); + BT_DBG("%s %pK", hdev->name, hdev); if (!hci_dev_test_flag(hdev, HCI_UNREGISTER) && !hci_dev_test_flag(hdev, HCI_USER_CHANNEL) && @@ -1788,7 +1788,7 @@ { int ret; - BT_DBG("%s %p", hdev->name, hdev); + BT_DBG("%s %pK", hdev->name, hdev); hci_req_lock(hdev); @@ -2122,7 +2122,7 @@ { struct hci_dev *hdev = data; - BT_DBG("%p name %s blocked %d", hdev, hdev->name, blocked); + BT_DBG("%pK name %s blocked %d", hdev, hdev->name, blocked); if (hci_dev_test_flag(hdev, HCI_USER_CHANNEL)) return -EBUSY; @@ -3017,6 +3017,7 @@ } list_del(¶ms->list); + list_del(¶ms->action); kfree(params); } @@ -3353,7 +3354,7 @@ sprintf(hdev->name, "hci%d", id); hdev->id = id; - BT_DBG("%p name %s bus %d", hdev, hdev->name, hdev->bus); + BT_DBG("%pK name %s bus %d", hdev, hdev->name, hdev->bus); hdev->workqueue = alloc_workqueue("%s", WQ_HIGHPRI | WQ_UNBOUND | WQ_MEM_RECLAIM, 1, hdev->name); @@ -3434,7 +3435,7 @@ { int id; - BT_DBG("%p name %s bus %d", hdev, hdev->name, hdev->bus); + BT_DBG("%pK name %s bus %d", hdev, hdev->name, hdev->bus); hci_dev_set_flag(hdev, HCI_UNREGISTER); @@ -3577,7 +3578,7 @@ int hci_register_cb(struct hci_cb *cb) { - BT_DBG("%p name %s", cb, cb->name); + BT_DBG("%pK name %s", cb, cb->name); mutex_lock(&hci_cb_list_lock); list_add_tail(&cb->list, &hci_cb_list); @@ -3589,7 +3590,7 @@ int hci_unregister_cb(struct hci_cb *cb) { - BT_DBG("%p name %s", cb, cb->name); + BT_DBG("%pK name %s", cb, cb->name); mutex_lock(&hci_cb_list_lock); list_del(&cb->list); @@ -3733,12 +3734,12 @@ list = skb_shinfo(skb)->frag_list; if (!list) { /* Non fragmented */ - BT_DBG("%s nonfrag skb %p len %d", hdev->name, skb, skb->len); + BT_DBG("%s nonfrag skb %pK len %d", hdev->name, skb, skb->len); skb_queue_tail(queue, skb); } else { /* Fragmented */ - BT_DBG("%s frag %p len %d", hdev->name, skb, skb->len); + BT_DBG("%s frag %pK len %d", hdev->name, skb, skb->len); skb_shinfo(skb)->frag_list = NULL; @@ -3759,7 +3760,7 @@ bt_cb(skb)->pkt_type = HCI_ACLDATA_PKT; hci_add_acl_hdr(skb, conn->handle, flags); - BT_DBG("%s frag %p len %d", hdev->name, skb, skb->len); + BT_DBG("%s frag %pK len %d", hdev->name, skb, skb->len); __skb_queue_tail(queue, skb); } while (list); @@ -3772,7 +3773,7 @@ { struct hci_dev *hdev = chan->conn->hdev; - BT_DBG("%s chan %p flags 0x%4.4x", hdev->name, chan, flags); + BT_DBG("%s chan %pK flags 0x%4.4x", hdev->name, chan, flags); hci_queue_acl(chan, &chan->data_q, skb, flags); @@ -3859,7 +3860,7 @@ } else *quote = 0; - BT_DBG("conn %p quote %d", conn, *quote); + BT_DBG("conn %pK quote %d", conn, *quote); return conn; } @@ -3962,7 +3963,7 @@ q = cnt / num; *quote = q ? q : 1; - BT_DBG("chan %p quote %d", chan, *quote); + BT_DBG("chan %pK quote %d", chan, *quote); return chan; } @@ -4004,7 +4005,7 @@ skb->priority = HCI_PRIO_MAX - 1; - BT_DBG("chan %p skb %p promoted to %d", chan, skb, + BT_DBG("chan %pK skb %pK promoted to %d", chan, skb, skb->priority); } @@ -4046,7 +4047,7 @@ (chan = hci_chan_sent(hdev, ACL_LINK, "e))) { u32 priority = (skb_peek(&chan->data_q))->priority; while (quote-- && (skb = skb_peek(&chan->data_q))) { - BT_DBG("chan %p skb %p len %d priority %u", chan, skb, + BT_DBG("chan %pK skb %pK len %d priority %u", chan, skb, skb->len, skb->priority); /* Stop if priority has changed */ @@ -4094,7 +4095,7 @@ while (quote > 0 && (skb = skb_peek(&chan->data_q))) { int blocks; - BT_DBG("chan %p skb %p len %d priority %u", chan, skb, + BT_DBG("chan %pK skb %pK len %d priority %u", chan, skb, skb->len, skb->priority); /* Stop if priority has changed */ @@ -4162,7 +4163,7 @@ while (hdev->sco_cnt && (conn = hci_low_sent(hdev, SCO_LINK, "e))) { while (quote-- && (skb = skb_dequeue(&conn->data_q))) { - BT_DBG("skb %p len %d", skb, skb->len); + BT_DBG("skb %pK len %d", skb, skb->len); hci_send_frame(hdev, skb); conn->sent++; @@ -4186,7 +4187,7 @@ while (hdev->sco_cnt && (conn = hci_low_sent(hdev, ESCO_LINK, "e))) { while (quote-- && (skb = skb_dequeue(&conn->data_q))) { - BT_DBG("skb %p len %d", skb, skb->len); + BT_DBG("skb %pK len %d", skb, skb->len); hci_send_frame(hdev, skb); conn->sent++; @@ -4220,7 +4221,7 @@ while (cnt && (chan = hci_chan_sent(hdev, LE_LINK, "e))) { u32 priority = (skb_peek(&chan->data_q))->priority; while (quote-- && (skb = skb_peek(&chan->data_q))) { - BT_DBG("chan %p skb %p len %d priority %u", chan, skb, + BT_DBG("chan %pK skb %pK len %d priority %u", chan, skb, skb->len, skb->priority); /* Stop if priority has changed */ @@ -4299,6 +4300,11 @@ l2cap_recv_acldata(conn, skb, flags); return; } else { + if (handle == 3804) { + /* qualcomm HCI seems to have a debug log on + * this channel */ + return; + } BT_ERR("%s ACL packet for unknown connection handle %d", hdev->name, handle); } diff -ruw linux-4.4.115/net/bluetooth/hci_event.c linux-4.4.115-fbx/net/bluetooth/hci_event.c --- linux-4.4.115/net/bluetooth/hci_event.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/net/bluetooth/hci_event.c 2019-10-29 09:26:25.769223983 +0100 @@ -1469,7 +1469,7 @@ conn = hci_conn_hash_lookup_ba(hdev, ACL_LINK, &cp->bdaddr); - BT_DBG("%s bdaddr %pMR hcon %p", hdev->name, &cp->bdaddr, conn); + BT_DBG("%s bdaddr %pMR hcon %pK", hdev->name, &cp->bdaddr, conn); if (status) { if (conn && conn->state == BT_CONNECT) { @@ -3235,7 +3235,7 @@ break; default: - BT_ERR("Unknown type %d conn %p", conn->type, conn); + BT_ERR("Unknown type %d conn %pK", conn->type, conn); break; } } @@ -3306,7 +3306,7 @@ break; default: - BT_ERR("Unknown type %d conn %p", conn->type, conn); + BT_ERR("Unknown type %d conn %pK", conn->type, conn); break; } } @@ -4381,7 +4381,7 @@ hchan->handle = le16_to_cpu(ev->handle); - BT_DBG("hcon %p mgr %p hchan %p", hcon, hcon->amp_mgr, hchan); + BT_DBG("hcon %pK mgr %pK hchan %pK", hcon, hcon->amp_mgr, hchan); mgr = hcon->amp_mgr; if (mgr && mgr->bredr_chan) { @@ -4742,8 +4742,8 @@ /* Adjust for actual length */ if (len != real_len) { - BT_ERR_RATELIMITED("%s advertising data length corrected", - hdev->name); + /* BT_ERR_RATELIMITED("%s advertising data length corrected", */ + /* hdev->name); */ len = real_len; } diff -ruw linux-4.4.115/net/bluetooth/hci_sock.c linux-4.4.115-fbx/net/bluetooth/hci_sock.c --- linux-4.4.115/net/bluetooth/hci_sock.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/net/bluetooth/hci_sock.c 2019-10-29 09:26:25.769223983 +0100 @@ -155,7 +155,7 @@ struct sock *sk; struct sk_buff *skb_copy = NULL; - BT_DBG("hdev %p len %d", hdev, skb->len); + BT_DBG("hdev %pK len %d", hdev, skb->len); read_lock(&hci_sk_list.lock); @@ -260,7 +260,7 @@ if (!atomic_read(&monitor_promisc)) return; - BT_DBG("hdev %p len %d", hdev, skb->len); + BT_DBG("hdev %pK len %d", hdev, skb->len); switch (bt_cb(skb)->pkt_type) { case HCI_COMMAND_PKT: @@ -553,7 +553,7 @@ struct sock *sk = sock->sk; struct hci_dev *hdev; - BT_DBG("sock %p sk %p", sock, sk); + BT_DBG("sock %pK sk %pK", sock, sk); if (!sk) return 0; @@ -753,7 +753,7 @@ struct hci_dev *hdev = NULL; int len, err = 0; - BT_DBG("sock %p sk %p", sock, sk); + BT_DBG("sock %pK sk %pK", sock, sk); if (!addr) return -EINVAL; @@ -931,7 +931,7 @@ struct hci_dev *hdev; int err = 0; - BT_DBG("sock %p sk %p", sock, sk); + BT_DBG("sock %pK sk %pK", sock, sk); if (peer) return -EOPNOTSUPP; @@ -999,7 +999,7 @@ struct sk_buff *skb; int copied, err; - BT_DBG("sock %p, sk %p", sock, sk); + BT_DBG("sock %pK, sk %pK", sock, sk); if (flags & MSG_OOB) return -EOPNOTSUPP; @@ -1159,7 +1159,7 @@ struct sk_buff *skb; int err; - BT_DBG("sock %p sk %p", sock, sk); + BT_DBG("sock %pK sk %pK", sock, sk); if (msg->msg_flags & MSG_OOB) return -EOPNOTSUPP; @@ -1289,7 +1289,7 @@ struct sock *sk = sock->sk; int err = 0, opt = 0; - BT_DBG("sk %p, opt %d", sk, optname); + BT_DBG("sk %pK, opt %d", sk, optname); lock_sock(sk); @@ -1372,7 +1372,7 @@ struct sock *sk = sock->sk; int len, opt, err = 0; - BT_DBG("sk %p, opt %d", sk, optname); + BT_DBG("sk %pK, opt %d", sk, optname); if (get_user(len, optlen)) return -EFAULT; @@ -1462,7 +1462,7 @@ { struct sock *sk; - BT_DBG("sock %p", sock); + BT_DBG("sock %pK", sock); if (sock->type != SOCK_RAW) return -ESOCKTNOSUPPORT; diff -ruw linux-4.4.115/net/bluetooth/hci_sysfs.c linux-4.4.115-fbx/net/bluetooth/hci_sysfs.c --- linux-4.4.115/net/bluetooth/hci_sysfs.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/net/bluetooth/hci_sysfs.c 2019-01-22 16:16:28.875295053 +0100 @@ -77,7 +77,7 @@ { struct hci_dev *hdev = conn->hdev; - BT_DBG("conn %p", conn); + BT_DBG("conn %pK", conn); conn->dev.type = &bt_link; conn->dev.class = bt_class; @@ -90,7 +90,7 @@ { struct hci_dev *hdev = conn->hdev; - BT_DBG("conn %p", conn); + BT_DBG("conn %pK", conn); dev_set_name(&conn->dev, "%s:%d", hdev->name, conn->handle); diff -ruw linux-4.4.115/net/bluetooth/l2cap_core.c linux-4.4.115-fbx/net/bluetooth/l2cap_core.c --- linux-4.4.115/net/bluetooth/l2cap_core.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/net/bluetooth/l2cap_core.c 2019-10-29 09:26:25.773224022 +0100 @@ -249,7 +249,7 @@ static void l2cap_state_change(struct l2cap_chan *chan, int state) { - BT_DBG("chan %p %s -> %s", chan, state_to_string(chan->state), + BT_DBG("chan %pK %s -> %s", chan, state_to_string(chan->state), state_to_string(state)); chan->state = state; @@ -400,7 +400,7 @@ struct l2cap_conn *conn = chan->conn; int reason; - BT_DBG("chan %p state %s", chan, state_to_string(chan->state)); + BT_DBG("chan %pK state %s", chan, state_to_string(chan->state)); mutex_lock(&conn->chan_lock); l2cap_chan_lock(chan); @@ -449,7 +449,7 @@ /* This flag is cleared in l2cap_chan_ready() */ set_bit(CONF_NOT_COMPLETE, &chan->conf_state); - BT_DBG("chan %p", chan); + BT_DBG("chan %pK", chan); return chan; } @@ -459,7 +459,7 @@ { struct l2cap_chan *chan = container_of(kref, struct l2cap_chan, kref); - BT_DBG("chan %p", chan); + BT_DBG("chan %pK", chan); write_lock(&chan_list_lock); list_del(&chan->global_l); @@ -470,14 +470,14 @@ void l2cap_chan_hold(struct l2cap_chan *c) { - BT_DBG("chan %p orig refcnt %d", c, atomic_read(&c->kref.refcount)); + BT_DBG("chan %pK orig refcnt %d", c, atomic_read(&c->kref.refcount)); kref_get(&c->kref); } void l2cap_chan_put(struct l2cap_chan *c) { - BT_DBG("chan %p orig refcnt %d", c, atomic_read(&c->kref.refcount)); + BT_DBG("chan %pK orig refcnt %d", c, atomic_read(&c->kref.refcount)); kref_put(&c->kref, l2cap_chan_destroy); } @@ -516,7 +516,7 @@ void __l2cap_chan_add(struct l2cap_conn *conn, struct l2cap_chan *chan) { - BT_DBG("conn %p, psm 0x%2.2x, dcid 0x%4.4x", conn, + BT_DBG("conn %pK, psm 0x%2.2x, dcid 0x%4.4x", conn, __le16_to_cpu(chan->psm), chan->dcid); conn->disc_reason = HCI_ERROR_REMOTE_USER_TERM; @@ -579,7 +579,7 @@ __clear_chan_timer(chan); - BT_DBG("chan %p, conn %p, err %d, state %s", chan, conn, err, + BT_DBG("chan %pK, conn %pK, err %d, state %s", chan, conn, err, state_to_string(chan->state)); chan->ops->teardown(chan, err); @@ -608,7 +608,7 @@ if (chan->hs_hchan) { struct hci_chan *hs_hchan = chan->hs_hchan; - BT_DBG("chan %p disconnect hs_hchan %p", chan, hs_hchan); + BT_DBG("chan %pK disconnect hs_hchan %pK", chan, hs_hchan); amp_disconnect_logical_link(hs_hchan); } @@ -711,7 +711,7 @@ { struct l2cap_conn *conn = chan->conn; - BT_DBG("chan %p state %s", chan, state_to_string(chan->state)); + BT_DBG("chan %pK state %s", chan, state_to_string(chan->state)); switch (chan->state) { case BT_LISTEN: @@ -874,7 +874,7 @@ struct hci_conn *hcon = chan->conn->hcon; u16 flags; - BT_DBG("chan %p, skb %p len %d priority %u", chan, skb, skb->len, + BT_DBG("chan %pK, skb %pK len %d priority %u", chan, skb, skb->len, skb->priority); if (chan->hs_hcon && !__chan_is_moving(chan)) { @@ -1061,7 +1061,7 @@ struct sk_buff *skb; u32 control_field; - BT_DBG("chan %p, control %p", chan, control); + BT_DBG("chan %pK, control %pK", chan, control); if (!control->sframe) return; @@ -1100,7 +1100,7 @@ { struct l2cap_ctrl control; - BT_DBG("chan %p, poll %d", chan, poll); + BT_DBG("chan %pK, poll %d", chan, poll); memset(&control, 0, sizeof(control)); control.sframe = 1; @@ -1189,7 +1189,7 @@ { struct sk_buff *skb; - BT_DBG("chan %p", chan); + BT_DBG("chan %pK", chan); if (chan->mode != L2CAP_MODE_ERTM) return; @@ -1223,7 +1223,7 @@ static void l2cap_move_done(struct l2cap_chan *chan) { u8 move_role = chan->move_role; - BT_DBG("chan %p", chan); + BT_DBG("chan %pK", chan); chan->move_state = L2CAP_MOVE_STABLE; chan->move_role = L2CAP_MOVE_ROLE_NONE; @@ -1302,7 +1302,7 @@ static void l2cap_start_connection(struct l2cap_chan *chan) { if (__amp_capable(chan)) { - BT_DBG("chan %p AMP capable: discover AMPs", chan); + BT_DBG("chan %pK AMP capable: discover AMPs", chan); a2mp_discover_amp(chan); } else if (chan->conn->hcon->type == LE_LINK) { l2cap_le_start(chan); @@ -1399,7 +1399,7 @@ { struct l2cap_chan *chan, *tmp; - BT_DBG("conn %p", conn); + BT_DBG("conn %pK", conn); mutex_lock(&conn->chan_lock); @@ -1477,7 +1477,7 @@ struct hci_conn *hcon = conn->hcon; struct hci_dev *hdev = hcon->hdev; - BT_DBG("%s conn %p", hdev->name, conn); + BT_DBG("%s conn %pK", hdev->name, conn); /* For outgoing pairing which doesn't necessarily have an * associated socket (e.g. mgmt_pair_device). @@ -1510,7 +1510,7 @@ struct l2cap_chan *chan; struct hci_conn *hcon = conn->hcon; - BT_DBG("conn %p", conn); + BT_DBG("conn %pK", conn); if (hcon->type == ACL_LINK) l2cap_request_info(conn); @@ -1551,7 +1551,7 @@ { struct l2cap_chan *chan; - BT_DBG("conn %p", conn); + BT_DBG("conn %pK", conn); mutex_lock(&conn->chan_lock); @@ -1661,7 +1661,7 @@ if (!conn) return; - BT_DBG("hcon %p conn %p, err %d", hcon, conn, err); + BT_DBG("hcon %pK conn %pK, err %d", hcon, conn, err); kfree_skb(conn->rx_skb); @@ -1789,7 +1789,7 @@ struct l2cap_chan *chan = container_of(work, struct l2cap_chan, monitor_timer.work); - BT_DBG("chan %p", chan); + BT_DBG("chan %pK", chan); l2cap_chan_lock(chan); @@ -1810,7 +1810,7 @@ struct l2cap_chan *chan = container_of(work, struct l2cap_chan, retrans_timer.work); - BT_DBG("chan %p", chan); + BT_DBG("chan %pK", chan); l2cap_chan_lock(chan); @@ -1831,7 +1831,7 @@ struct sk_buff *skb; struct l2cap_ctrl *control; - BT_DBG("chan %p, skbs %p", chan, skbs); + BT_DBG("chan %pK, skbs %pK", chan, skbs); if (__chan_is_moving(chan)) return; @@ -1870,7 +1870,7 @@ struct l2cap_ctrl *control; int sent = 0; - BT_DBG("chan %p", chan); + BT_DBG("chan %pK", chan); if (chan->state != BT_CONNECTED) return -ENOTCONN; @@ -1941,7 +1941,7 @@ struct sk_buff *tx_skb; u16 seq; - BT_DBG("chan %p", chan); + BT_DBG("chan %pK", chan); if (test_bit(CONN_REMOTE_BUSY, &chan->conn_state)) return; @@ -2018,7 +2018,7 @@ static void l2cap_retransmit(struct l2cap_chan *chan, struct l2cap_ctrl *control) { - BT_DBG("chan %p, control %p", chan, control); + BT_DBG("chan %pK, control %pK", chan, control); l2cap_seq_list_append(&chan->retrans_list, control->reqseq); l2cap_ertm_resend(chan); @@ -2029,7 +2029,7 @@ { struct sk_buff *skb; - BT_DBG("chan %p, control %p", chan, control); + BT_DBG("chan %pK, control %pK", chan, control); if (control->poll) set_bit(CONN_SEND_FBIT, &chan->conn_state); @@ -2065,7 +2065,7 @@ chan->last_acked_seq); int threshold; - BT_DBG("chan %p last_acked_seq %d buffer_seq %d", + BT_DBG("chan %pK last_acked_seq %d buffer_seq %d", chan, chan->last_acked_seq, chan->buffer_seq); memset(&control, 0, sizeof(control)); @@ -2160,7 +2160,7 @@ int err, count, hlen = L2CAP_HDR_SIZE + L2CAP_PSMLEN_SIZE; struct l2cap_hdr *lh; - BT_DBG("chan %p psm 0x%2.2x len %zu", chan, + BT_DBG("chan %pK psm 0x%2.2x len %zu", chan, __le16_to_cpu(chan->psm), len); count = min_t(unsigned int, (conn->mtu - hlen), len); @@ -2192,7 +2192,7 @@ int err, count; struct l2cap_hdr *lh; - BT_DBG("chan %p len %zu", chan, len); + BT_DBG("chan %pK len %zu", chan, len); count = min_t(unsigned int, (conn->mtu - L2CAP_HDR_SIZE), len); @@ -2223,7 +2223,7 @@ int err, count, hlen; struct l2cap_hdr *lh; - BT_DBG("chan %p len %zu", chan, len); + BT_DBG("chan %pK len %zu", chan, len); if (!conn) return ERR_PTR(-ENOTCONN); @@ -2277,7 +2277,7 @@ size_t pdu_len; u8 sar; - BT_DBG("chan %p, msg %p, len %zu", chan, msg, len); + BT_DBG("chan %pK, msg %pK, len %zu", chan, msg, len); /* It is critical that ERTM PDUs fit in a single HCI fragment, * so fragmented skbs are not used. The HCI layer's handling @@ -2344,7 +2344,7 @@ int err, count, hlen; struct l2cap_hdr *lh; - BT_DBG("chan %p len %zu", chan, len); + BT_DBG("chan %pK len %zu", chan, len); if (!conn) return ERR_PTR(-ENOTCONN); @@ -2386,7 +2386,7 @@ size_t pdu_len; u16 sdu_len; - BT_DBG("chan %p, msg %p, len %zu", chan, msg, len); + BT_DBG("chan %pK, msg %pK, len %zu", chan, msg, len); sdu_len = len; pdu_len = chan->remote_mps - L2CAP_SDULEN_SIZE; @@ -2552,7 +2552,7 @@ struct l2cap_ctrl control; u16 seq; - BT_DBG("chan %p, txseq %u", chan, txseq); + BT_DBG("chan %pK, txseq %u", chan, txseq); memset(&control, 0, sizeof(control)); control.sframe = 1; @@ -2574,7 +2574,7 @@ { struct l2cap_ctrl control; - BT_DBG("chan %p", chan); + BT_DBG("chan %pK", chan); if (chan->srej_list.tail == L2CAP_SEQ_LIST_CLEAR) return; @@ -2592,7 +2592,7 @@ u16 initial_head; u16 seq; - BT_DBG("chan %p, txseq %u", chan, txseq); + BT_DBG("chan %pK, txseq %u", chan, txseq); memset(&control, 0, sizeof(control)); control.sframe = 1; @@ -2617,7 +2617,7 @@ struct sk_buff *acked_skb; u16 ackseq; - BT_DBG("chan %p, reqseq %u", chan, reqseq); + BT_DBG("chan %pK, reqseq %u", chan, reqseq); if (chan->unacked_frames == 0 || reqseq == chan->expected_ack_seq) return; @@ -2646,7 +2646,7 @@ static void l2cap_abort_rx_srej_sent(struct l2cap_chan *chan) { - BT_DBG("chan %p", chan); + BT_DBG("chan %pK", chan); chan->expected_tx_seq = chan->buffer_seq; l2cap_seq_list_clear(&chan->srej_list); @@ -2658,7 +2658,7 @@ struct l2cap_ctrl *control, struct sk_buff_head *skbs, u8 event) { - BT_DBG("chan %p, control %p, skbs %p, event %d", chan, control, skbs, + BT_DBG("chan %pK, control %pK, skbs %pK, event %d", chan, control, skbs, event); switch (event) { @@ -2730,7 +2730,7 @@ struct l2cap_ctrl *control, struct sk_buff_head *skbs, u8 event) { - BT_DBG("chan %p, control %p, skbs %p, event %d", chan, control, skbs, + BT_DBG("chan %pK, control %pK, skbs %pK, event %d", chan, control, skbs, event); switch (event) { @@ -2807,7 +2807,7 @@ static void l2cap_tx(struct l2cap_chan *chan, struct l2cap_ctrl *control, struct sk_buff_head *skbs, u8 event) { - BT_DBG("chan %p, control %p, skbs %p, event %d, state %d", + BT_DBG("chan %pK, control %pK, skbs %pK, event %d, state %d", chan, control, skbs, event, chan->tx_state); switch (chan->tx_state) { @@ -2826,14 +2826,14 @@ static void l2cap_pass_to_tx(struct l2cap_chan *chan, struct l2cap_ctrl *control) { - BT_DBG("chan %p, control %p", chan, control); + BT_DBG("chan %pK, control %pK", chan, control); l2cap_tx(chan, control, NULL, L2CAP_EV_RECV_REQSEQ_AND_FBIT); } static void l2cap_pass_to_tx_fbit(struct l2cap_chan *chan, struct l2cap_ctrl *control) { - BT_DBG("chan %p, control %p", chan, control); + BT_DBG("chan %pK, control %pK", chan, control); l2cap_tx(chan, control, NULL, L2CAP_EV_RECV_FBIT); } @@ -2843,7 +2843,7 @@ struct sk_buff *nskb; struct l2cap_chan *chan; - BT_DBG("conn %p", conn); + BT_DBG("conn %pK", conn); mutex_lock(&conn->chan_lock); @@ -2874,7 +2874,7 @@ struct l2cap_hdr *lh; int len, count; - BT_DBG("conn %p, code 0x%2.2x, ident 0x%2.2x, len %u", + BT_DBG("conn %pK, code 0x%2.2x, ident 0x%2.2x, len %u", conn, code, ident, dlen); if (conn->mtu < L2CAP_HDR_SIZE + L2CAP_CMD_HDR_SIZE) @@ -3036,7 +3036,7 @@ ack_timer.work); u16 frames_to_ack; - BT_DBG("chan %p", chan); + BT_DBG("chan %pK", chan); l2cap_chan_lock(chan); @@ -3181,7 +3181,7 @@ void *endptr = data + data_size; u16 size; - BT_DBG("chan %p", chan); + BT_DBG("chan %pK", chan); if (chan->num_conf_req || chan->num_conf_rsp) goto done; @@ -3311,7 +3311,7 @@ u16 result = L2CAP_CONF_SUCCESS; u16 size; - BT_DBG("chan %p", chan); + BT_DBG("chan %pK", chan); while (len >= L2CAP_CONF_OPT_SIZE) { len -= l2cap_get_conf_opt(&req, &type, &olen, &val); @@ -3522,7 +3522,7 @@ struct l2cap_conf_rfc rfc = { .mode = L2CAP_MODE_BASIC }; struct l2cap_conf_efs efs; - BT_DBG("chan %p, rsp %p, len %d, req %p", chan, rsp, len, data); + BT_DBG("chan %pK, rsp %pK, len %d, req %pK", chan, rsp, len, data); while (len >= L2CAP_CONF_OPT_SIZE) { len -= l2cap_get_conf_opt(&rsp, &type, &olen, &val); @@ -3628,7 +3628,7 @@ struct l2cap_conf_rsp *rsp = data; void *ptr = rsp->data; - BT_DBG("chan %p", chan); + BT_DBG("chan %pK", chan); rsp->scid = cpu_to_le16(chan->dcid); rsp->result = cpu_to_le16(result); @@ -3642,7 +3642,7 @@ struct l2cap_le_conn_rsp rsp; struct l2cap_conn *conn = chan->conn; - BT_DBG("chan %p", chan); + BT_DBG("chan %pK", chan); rsp.dcid = cpu_to_le16(chan->scid); rsp.mtu = cpu_to_le16(chan->imtu); @@ -3671,7 +3671,7 @@ else rsp_code = L2CAP_CONN_RSP; - BT_DBG("chan %p rsp_code %u", chan, rsp_code); + BT_DBG("chan %pK rsp_code %u", chan, rsp_code); l2cap_send_cmd(conn, chan->ident, rsp_code, sizeof(rsp), &rsp); @@ -3699,7 +3699,7 @@ .txwin_size = min_t(u16, chan->ack_win, L2CAP_DEFAULT_TX_WINDOW), }; - BT_DBG("chan %p, rsp %p, len %d", chan, rsp, len); + BT_DBG("chan %pK, rsp %pK, len %d", chan, rsp, len); if ((chan->mode != L2CAP_MODE_ERTM) && (chan->mode != L2CAP_MODE_STREAMING)) return; @@ -4002,7 +4002,7 @@ { struct l2cap_conn *conn = chan->conn; - BT_DBG("conn %p chan %p ident %d flags 0x%4.4x", conn, chan, ident, + BT_DBG("conn %pK chan %pK ident %d flags 0x%4.4x", conn, chan, ident, flags); clear_bit(CONF_LOC_CONF_PEND, &chan->conf_state); @@ -4499,7 +4499,8 @@ return 0; } - BT_DBG("mgr %p bredr_chan %p hs_hcon %p", mgr, chan, hs_hcon); + BT_DBG("mgr %pK bredr_chan %pK hs_hcon %pK", + mgr, chan, hs_hcon); mgr->bredr_chan = chan; chan->hs_hcon = hs_hcon; @@ -4528,7 +4529,7 @@ struct l2cap_move_chan_req req; u8 ident; - BT_DBG("chan %p, dest_amp_id %d", chan, dest_amp_id); + BT_DBG("chan %pK, dest_amp_id %d", chan, dest_amp_id); ident = l2cap_get_ident(chan->conn); chan->ident = ident; @@ -4546,7 +4547,7 @@ { struct l2cap_move_chan_rsp rsp; - BT_DBG("chan %p, result 0x%4.4x", chan, result); + BT_DBG("chan %pK, result 0x%4.4x", chan, result); rsp.icid = cpu_to_le16(chan->dcid); rsp.result = cpu_to_le16(result); @@ -4559,7 +4560,7 @@ { struct l2cap_move_chan_cfm cfm; - BT_DBG("chan %p, result 0x%4.4x", chan, result); + BT_DBG("chan %pK, result 0x%4.4x", chan, result); chan->ident = l2cap_get_ident(chan->conn); @@ -4576,7 +4577,7 @@ { struct l2cap_move_chan_cfm cfm; - BT_DBG("conn %p, icid 0x%4.4x", conn, icid); + BT_DBG("conn %pK, icid 0x%4.4x", conn, icid); cfm.icid = cpu_to_le16(icid); cfm.result = cpu_to_le16(L2CAP_MC_UNCONFIRMED); @@ -4696,7 +4697,7 @@ void l2cap_logical_cfm(struct l2cap_chan *chan, struct hci_chan *hchan, u8 status) { - BT_DBG("chan %p, hchan %p, status %d", chan, hchan, status); + BT_DBG("chan %pK, hchan %pK, status %d", chan, hchan, status); if (status) { l2cap_logical_fail(chan); @@ -4715,7 +4716,7 @@ void l2cap_move_start(struct l2cap_chan *chan) { - BT_DBG("chan %p", chan); + BT_DBG("chan %pK", chan); if (chan->local_amp_id == AMP_ID_BREDR) { if (chan->chan_policy != BT_CHANNEL_POLICY_AMP_PREFERRED) @@ -4735,7 +4736,7 @@ static void l2cap_do_create(struct l2cap_chan *chan, int result, u8 local_amp_id, u8 remote_amp_id) { - BT_DBG("chan %p state %s %u -> %u", chan, state_to_string(chan->state), + BT_DBG("chan %pK state %s %u -> %u", chan, state_to_string(chan->state), local_amp_id, remote_amp_id); chan->fcs = L2CAP_FCS_NONE; @@ -4844,7 +4845,7 @@ u8 local_amp_id = chan->local_amp_id; u8 remote_amp_id = chan->remote_amp_id; - BT_DBG("chan %p, result %d, local_amp_id %d, remote_amp_id %d", + BT_DBG("chan %pK, result %d, local_amp_id %d, remote_amp_id %d", chan, result, local_amp_id, remote_amp_id); if (chan->state == BT_DISCONN || chan->state == BT_CLOSED) { @@ -5216,7 +5217,8 @@ memset(&rsp, 0, sizeof(rsp)); - err = hci_check_conn_params(min, max, latency, to_multiplier); +// err = hci_check_conn_params(min, max, latency, to_multiplier); + err = 1; if (err) rsp.result = cpu_to_le16(L2CAP_CONN_PARAM_REJECTED); else @@ -5767,7 +5769,7 @@ { struct l2cap_ctrl control; - BT_DBG("chan %p", chan); + BT_DBG("chan %pK", chan); memset(&control, 0, sizeof(control)); control.sframe = 1; @@ -5922,7 +5924,7 @@ * until a gap is encountered. */ - BT_DBG("chan %p", chan); + BT_DBG("chan %pK", chan); while (!test_bit(CONN_LOCAL_BUSY, &chan->conn_state)) { struct sk_buff *skb; @@ -5954,7 +5956,7 @@ { struct sk_buff *skb; - BT_DBG("chan %p, control %p", chan, control); + BT_DBG("chan %pK, control %pK", chan, control); if (control->reqseq == chan->next_tx_seq) { BT_DBG("Invalid reqseq %d, disconnecting", control->reqseq); @@ -6012,7 +6014,7 @@ { struct sk_buff *skb; - BT_DBG("chan %p, control %p", chan, control); + BT_DBG("chan %pK, control %pK", chan, control); if (control->reqseq == chan->next_tx_seq) { BT_DBG("Invalid reqseq %d, disconnecting", control->reqseq); @@ -6046,7 +6048,7 @@ static u8 l2cap_classify_txseq(struct l2cap_chan *chan, u16 txseq) { - BT_DBG("chan %p, txseq %d", chan, txseq); + BT_DBG("chan %pK, txseq %d", chan, txseq); BT_DBG("last_acked_seq %d, expected_tx_seq %d", chan->last_acked_seq, chan->expected_tx_seq); @@ -6137,7 +6139,7 @@ int err = 0; bool skb_in_use = false; - BT_DBG("chan %p, control %p, skb %p, event %d", chan, control, skb, + BT_DBG("chan %pK, control %pK, skb %pK, event %d", chan, control, skb, event); switch (event) { @@ -6193,7 +6195,7 @@ */ skb_queue_tail(&chan->srej_q, skb); skb_in_use = true; - BT_DBG("Queued %p (queue len %d)", skb, + BT_DBG("Queued %pK (queue len %d)", skb, skb_queue_len(&chan->srej_q)); clear_bit(CONN_SREJ_ACT, &chan->conn_state); @@ -6257,7 +6259,7 @@ } if (skb && !skb_in_use) { - BT_DBG("Freeing %p", skb); + BT_DBG("Freeing %pK", skb); kfree_skb(skb); } @@ -6272,7 +6274,7 @@ u16 txseq = control->txseq; bool skb_in_use = false; - BT_DBG("chan %p, control %p, skb %p, event %d", chan, control, skb, + BT_DBG("chan %pK, control %pK, skb %pK, event %d", chan, control, skb, event); switch (event) { @@ -6283,7 +6285,7 @@ l2cap_pass_to_tx(chan, control); skb_queue_tail(&chan->srej_q, skb); skb_in_use = true; - BT_DBG("Queued %p (queue len %d)", skb, + BT_DBG("Queued %pK (queue len %d)", skb, skb_queue_len(&chan->srej_q)); chan->expected_tx_seq = __next_seq(chan, txseq); @@ -6294,7 +6296,7 @@ l2cap_pass_to_tx(chan, control); skb_queue_tail(&chan->srej_q, skb); skb_in_use = true; - BT_DBG("Queued %p (queue len %d)", skb, + BT_DBG("Queued %pK (queue len %d)", skb, skb_queue_len(&chan->srej_q)); err = l2cap_rx_queued_iframes(chan); @@ -6309,7 +6311,7 @@ */ skb_queue_tail(&chan->srej_q, skb); skb_in_use = true; - BT_DBG("Queued %p (queue len %d)", skb, + BT_DBG("Queued %pK (queue len %d)", skb, skb_queue_len(&chan->srej_q)); l2cap_pass_to_tx(chan, control); @@ -6323,7 +6325,7 @@ */ skb_queue_tail(&chan->srej_q, skb); skb_in_use = true; - BT_DBG("Queued %p (queue len %d)", skb, + BT_DBG("Queued %pK (queue len %d)", skb, skb_queue_len(&chan->srej_q)); l2cap_pass_to_tx(chan, control); @@ -6400,7 +6402,7 @@ } if (skb && !skb_in_use) { - BT_DBG("Freeing %p", skb); + BT_DBG("Freeing %pK", skb); kfree_skb(skb); } @@ -6409,7 +6411,7 @@ static int l2cap_finish_move(struct l2cap_chan *chan) { - BT_DBG("chan %p", chan); + BT_DBG("chan %pK", chan); chan->rx_state = L2CAP_RX_STATE_RECV; @@ -6427,7 +6429,7 @@ { int err; - BT_DBG("chan %p, control %p, skb %p, event %d", chan, control, skb, + BT_DBG("chan %pK, control %pK, skb %pK, event %d", chan, control, skb, event); if (!control->poll) @@ -6511,7 +6513,7 @@ { int err = 0; - BT_DBG("chan %p, control %p, skb %p, event %d, state %d", chan, + BT_DBG("chan %pK, control %pK, skb %pK, event %d, state %d", chan, control, skb, event, chan->rx_state); if (__valid_reqseq(chan, control->reqseq)) { @@ -6548,7 +6550,7 @@ { int err = 0; - BT_DBG("chan %p, control %p, skb %p, state %d", chan, control, skb, + BT_DBG("chan %pK, control %pK, skb %pK, state %d", chan, control, skb, chan->rx_state); if (l2cap_classify_txseq(chan, control->txseq) == @@ -6570,7 +6572,7 @@ chan->sdu_len = 0; if (skb) { - BT_DBG("Freeing %p", skb); + BT_DBG("Freeing %pK", skb); kfree_skb(skb); } } @@ -6683,7 +6685,7 @@ return_credits = le_max_credits - chan->rx_credits; - BT_DBG("chan %p returning %u credits to sender", chan, return_credits); + BT_DBG("chan %pK returning %u credits to sender", chan, return_credits); chan->rx_credits += return_credits; @@ -6808,7 +6810,7 @@ } } - BT_DBG("chan %p, len %d", chan, skb->len); + BT_DBG("chan %pK, len %d", chan, skb->len); /* If we receive data on a fixed channel before the info req/rsp * procdure is done simply assume that the channel is supported @@ -6848,7 +6850,7 @@ goto done; default: - BT_DBG("chan %p: bad mode 0x%2.2x", chan, chan->mode); + BT_DBG("chan %pK: bad mode 0x%2.2x", chan, chan->mode); break; } @@ -6873,7 +6875,7 @@ if (!chan) goto free_skb; - BT_DBG("chan %p, len %d", chan, skb->len); + BT_DBG("chan %pK, len %d", chan, skb->len); if (chan->state != BT_BOUND && chan->state != BT_CONNECTED) goto drop; @@ -6986,7 +6988,7 @@ conn->hcon = hci_conn_get(hcon); conn->hchan = hchan; - BT_DBG("hcon %p conn %p hchan %p", hcon, conn, hchan); + BT_DBG("hcon %pK conn %pK hchan %pK", hcon, conn, hchan); switch (hcon->type) { case LE_LINK: @@ -7282,7 +7284,7 @@ if (hcon->type != ACL_LINK && hcon->type != LE_LINK) return; - BT_DBG("hcon %p bdaddr %pMR status %d", hcon, &hcon->dst, status); + BT_DBG("hcon %pK bdaddr %pMR status %d", hcon, &hcon->dst, status); if (status) { l2cap_conn_del(hcon, bt_to_errno(status)); @@ -7337,7 +7339,7 @@ { struct l2cap_conn *conn = hcon->l2cap_data; - BT_DBG("hcon %p", hcon); + BT_DBG("hcon %pK", hcon); if (!conn) return HCI_ERROR_REMOTE_USER_TERM; @@ -7349,7 +7351,7 @@ if (hcon->type != ACL_LINK && hcon->type != LE_LINK) return; - BT_DBG("hcon %p reason %d", hcon, reason); + BT_DBG("hcon %pK reason %d", hcon, reason); l2cap_conn_del(hcon, bt_to_errno(reason)); } @@ -7379,14 +7381,14 @@ if (!conn) return; - BT_DBG("conn %p status 0x%2.2x encrypt %u", conn, status, encrypt); + BT_DBG("conn %pK status 0x%2.2x encrypt %u", conn, status, encrypt); mutex_lock(&conn->chan_lock); list_for_each_entry(chan, &conn->chan_l, list) { l2cap_chan_lock(chan); - BT_DBG("chan %p scid 0x%4.4x state %s", chan, chan->scid, + BT_DBG("chan %pK scid 0x%4.4x state %s", chan, chan->scid, state_to_string(chan->state)); if (chan->scid == L2CAP_CID_A2MP) { @@ -7478,7 +7480,7 @@ if (!conn) goto drop; - BT_DBG("conn %p len %d flags 0x%x", conn, skb->len, flags); + BT_DBG("conn %pK len %d flags 0x%x", conn, skb->len, flags); switch (flags) { case ACL_START: diff -ruw linux-4.4.115/net/bluetooth/l2cap_sock.c linux-4.4.115-fbx/net/bluetooth/l2cap_sock.c --- linux-4.4.115/net/bluetooth/l2cap_sock.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/net/bluetooth/l2cap_sock.c 2019-01-22 16:16:28.879295089 +0100 @@ -84,7 +84,7 @@ struct sockaddr_l2 la; int len, err = 0; - BT_DBG("sk %p", sk); + BT_DBG("sk %pK", sk); if (!addr || addr->sa_family != AF_BLUETOOTH) return -EINVAL; @@ -178,7 +178,7 @@ struct sockaddr_l2 la; int len, err = 0; - BT_DBG("sk %p", sk); + BT_DBG("sk %pK", sk); if (!addr || alen < sizeof(addr->sa_family) || addr->sa_family != AF_BLUETOOTH) @@ -254,7 +254,7 @@ struct l2cap_chan *chan = l2cap_pi(sk)->chan; int err = 0; - BT_DBG("sk %p backlog %d", sk, backlog); + BT_DBG("sk %pK backlog %d", sk, backlog); lock_sock(sk); @@ -311,7 +311,7 @@ timeo = sock_rcvtimeo(sk, flags & O_NONBLOCK); - BT_DBG("sk %p timeo %ld", sk, timeo); + BT_DBG("sk %pK timeo %ld", sk, timeo); /* Wait for an incoming connection. (wake-one). */ add_wait_queue_exclusive(sk_sleep(sk), &wait); @@ -348,7 +348,7 @@ newsock->state = SS_CONNECTED; - BT_DBG("new socket %p", nsk); + BT_DBG("new socket %pK", nsk); done: release_sock(sk); @@ -362,7 +362,7 @@ struct sock *sk = sock->sk; struct l2cap_chan *chan = l2cap_pi(sk)->chan; - BT_DBG("sock %p, sk %p", sock, sk); + BT_DBG("sock %pK, sk %pK", sock, sk); if (peer && sk->sk_state != BT_CONNECTED && sk->sk_state != BT_CONNECT && sk->sk_state != BT_CONNECT2 && @@ -398,7 +398,7 @@ int len, err = 0; u32 opt; - BT_DBG("sk %p", sk); + BT_DBG("sk %pK", sk); if (get_user(len, optlen)) return -EFAULT; @@ -500,7 +500,7 @@ struct bt_power pwr; int len, err = 0; - BT_DBG("sk %p", sk); + BT_DBG("sk %pK", sk); if (level == SOL_L2CAP) return l2cap_sock_getsockopt_old(sock, optname, optval, optlen); @@ -636,7 +636,7 @@ int len, err = 0; u32 opt; - BT_DBG("sk %p", sk); + BT_DBG("sk %pK", sk); lock_sock(sk); @@ -750,7 +750,7 @@ int len, err = 0; u32 opt; - BT_DBG("sk %p", sk); + BT_DBG("sk %pK", sk); if (level == SOL_L2CAP) return l2cap_sock_setsockopt_old(sock, optname, optval, optlen); @@ -951,7 +951,7 @@ struct l2cap_chan *chan = l2cap_pi(sk)->chan; int err; - BT_DBG("sock %p, sk %p", sock, sk); + BT_DBG("sock %pK, sk %pK", sock, sk); err = sock_error(sk); if (err) @@ -1045,7 +1045,7 @@ if (!sock_flag(sk, SOCK_ZAPPED) || sk->sk_socket) return; - BT_DBG("sk %p state %s", sk, state_to_string(sk->sk_state)); + BT_DBG("sk %pK state %s", sk, state_to_string(sk->sk_state)); /* Kill poor orphan */ @@ -1106,7 +1106,7 @@ struct l2cap_conn *conn; int err = 0; - BT_DBG("sock %p, sk %p", sock, sk); + BT_DBG("sock %pK, sk %pK", sock, sk); if (!sk) return 0; @@ -1125,7 +1125,7 @@ /* prevent chan structure from being freed whilst unlocked */ l2cap_chan_hold(chan); - BT_DBG("chan %p state %s", chan, state_to_string(chan->state)); + BT_DBG("chan %pK state %s", chan, state_to_string(chan->state)); if (chan->mode == L2CAP_MODE_ERTM && chan->unacked_frames > 0 && @@ -1190,7 +1190,7 @@ struct sock *sk = sock->sk; int err; - BT_DBG("sock %p, sk %p", sock, sk); + BT_DBG("sock %pK, sk %pK", sock, sk); if (!sk) return 0; @@ -1208,14 +1208,14 @@ { struct sock *sk; - BT_DBG("parent %p state %s", parent, + BT_DBG("parent %pK state %s", parent, state_to_string(parent->sk_state)); /* Close not yet accepted channels */ while ((sk = bt_accept_dequeue(parent, NULL))) { struct l2cap_chan *chan = l2cap_pi(sk)->chan; - BT_DBG("child chan %p state %s", chan, + BT_DBG("child chan %pK state %s", chan, state_to_string(chan->state)); l2cap_chan_lock(chan); @@ -1305,7 +1305,7 @@ struct sock *sk = chan->data; struct sock *parent; - BT_DBG("chan %p state %s", chan, state_to_string(chan->state)); + BT_DBG("chan %pK state %s", chan, state_to_string(chan->state)); /* This callback can be called both for server (BT_LISTEN) * sockets as well as "normal" ones. To avoid lockdep warnings @@ -1392,7 +1392,7 @@ parent = bt_sk(sk)->parent; - BT_DBG("sk %p, parent %p", sk, parent); + BT_DBG("sk %pK, parent %pK", sk, parent); sk->sk_state = BT_CONNECTED; sk->sk_state_change(sk); @@ -1471,7 +1471,7 @@ static void l2cap_sock_destruct(struct sock *sk) { - BT_DBG("sk %p", sk); + BT_DBG("sk %pK", sk); if (l2cap_pi(sk)->chan) l2cap_chan_put(l2cap_pi(sk)->chan); @@ -1502,7 +1502,7 @@ { struct l2cap_chan *chan = l2cap_pi(sk)->chan; - BT_DBG("sk %p", sk); + BT_DBG("sk %pK", sk); if (parent) { struct l2cap_chan *pchan = l2cap_pi(parent)->chan; @@ -1609,7 +1609,7 @@ { struct sock *sk; - BT_DBG("sock %p", sock); + BT_DBG("sock %pK", sock); sock->state = SS_UNCONNECTED; diff -ruw linux-4.4.115/net/bluetooth/mgmt.c linux-4.4.115-fbx/net/bluetooth/mgmt.c --- linux-4.4.115/net/bluetooth/mgmt.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/net/bluetooth/mgmt.c 2019-10-29 09:26:25.773224022 +0100 @@ -281,7 +281,7 @@ { struct mgmt_rp_read_version rp; - BT_DBG("sock %p", sk); + BT_DBG("sock %pK", sk); rp.version = MGMT_VERSION; rp.revision = cpu_to_le16(MGMT_REVISION); @@ -298,7 +298,7 @@ size_t rp_size; int i, err; - BT_DBG("sock %p", sk); + BT_DBG("sock %pK", sk); if (hci_sock_test_flag(sk, HCI_SOCK_TRUSTED)) { num_commands = ARRAY_SIZE(mgmt_commands); @@ -351,7 +351,7 @@ u16 count; int err; - BT_DBG("sock %p", sk); + BT_DBG("sock %pK", sk); read_lock(&hci_dev_list_lock); @@ -411,7 +411,7 @@ u16 count; int err; - BT_DBG("sock %p", sk); + BT_DBG("sock %pK", sk); read_lock(&hci_dev_list_lock); @@ -471,7 +471,7 @@ u16 count; int err; - BT_DBG("sock %p", sk); + BT_DBG("sock %pK", sk); read_lock(&hci_dev_list_lock); @@ -588,7 +588,7 @@ struct mgmt_rp_read_config_info rp; u32 options = 0; - BT_DBG("sock %p %s", sk, hdev->name); + BT_DBG("sock %pK %s", sk, hdev->name); hci_dev_lock(hdev); @@ -1373,7 +1373,7 @@ { struct mgmt_rp_read_info rp; - BT_DBG("sock %p %s", sk, hdev->name); + BT_DBG("sock %pK %s", sk, hdev->name); hci_dev_lock(hdev); diff -ruw linux-4.4.115/net/bluetooth/sco.c linux-4.4.115-fbx/net/bluetooth/sco.c --- linux-4.4.115/net/bluetooth/sco.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/net/bluetooth/sco.c 2019-10-29 09:26:25.777224062 +0100 @@ -76,7 +76,7 @@ { struct sock *sk = (struct sock *)arg; - BT_DBG("sock %p state %d", sk, sk->sk_state); + BT_DBG("sock %pK state %d", sk, sk->sk_state); bh_lock_sock(sk); sk->sk_err = ETIMEDOUT; @@ -89,13 +89,13 @@ static void sco_sock_set_timer(struct sock *sk, long timeout) { - BT_DBG("sock %p state %d timeout %ld", sk, sk->sk_state, timeout); + BT_DBG("sock %pK state %d timeout %ld", sk, sk->sk_state, timeout); sk_reset_timer(sk, &sk->sk_timer, jiffies + timeout); } static void sco_sock_clear_timer(struct sock *sk) { - BT_DBG("sock %p state %d", sk, sk->sk_state); + BT_DBG("sock %pK state %d", sk, sk->sk_state); sk_stop_timer(sk, &sk->sk_timer); } @@ -122,7 +122,7 @@ else conn->mtu = 60; - BT_DBG("hcon %p conn %p", hcon, conn); + BT_DBG("hcon %pK conn %pK", hcon, conn); return conn; } @@ -135,7 +135,7 @@ conn = sco_pi(sk)->conn; - BT_DBG("sk %p, conn %p, err %d", sk, conn, err); + BT_DBG("sk %pK, conn %pK, err %d", sk, conn, err); if (conn) { sco_conn_lock(conn); @@ -162,7 +162,7 @@ if (!conn) return; - BT_DBG("hcon %p conn %p, err %d", hcon, conn, err); + BT_DBG("hcon %pK conn %pK, err %d", hcon, conn, err); /* Kill socket */ sco_conn_lock(conn); @@ -186,7 +186,7 @@ static void __sco_chan_add(struct sco_conn *conn, struct sock *sk, struct sock *parent) { - BT_DBG("conn %p", conn); + BT_DBG("conn %pK", conn); sco_pi(sk)->conn = conn; conn->sk = sk; @@ -281,7 +281,7 @@ if (len > conn->mtu) return -EINVAL; - BT_DBG("sk %p len %d", sk, len); + BT_DBG("sk %pK len %d", sk, len); skb = bt_skb_send_alloc(sk, len, msg->msg_flags & MSG_DONTWAIT, &err); if (!skb) @@ -308,7 +308,7 @@ if (!sk) goto drop; - BT_DBG("sk %p len %d", sk, skb->len); + BT_DBG("sk %pK len %d", sk, skb->len); if (sk->sk_state != BT_CONNECTED) goto drop; @@ -365,7 +365,7 @@ static void sco_sock_destruct(struct sock *sk) { - BT_DBG("sk %p", sk); + BT_DBG("sk %pK", sk); skb_queue_purge(&sk->sk_receive_queue); skb_queue_purge(&sk->sk_write_queue); @@ -375,7 +375,7 @@ { struct sock *sk; - BT_DBG("parent %p", parent); + BT_DBG("parent %pK", parent); /* Close not yet accepted channels */ while ((sk = bt_accept_dequeue(parent, NULL))) { @@ -395,7 +395,7 @@ if (!sock_flag(sk, SOCK_ZAPPED) || sk->sk_socket) return; - BT_DBG("sk %p state %d", sk, sk->sk_state); + BT_DBG("sk %pK state %d", sk, sk->sk_state); /* Kill poor orphan */ bt_sock_unlink(&sco_sk_list, sk); @@ -405,7 +405,7 @@ static void __sco_sock_close(struct sock *sk) { - BT_DBG("sk %p state %d socket %p", sk, sk->sk_state, sk->sk_socket); + BT_DBG("sk %pK state %d socket %pK", sk, sk->sk_state, sk->sk_socket); switch (sk->sk_state) { case BT_LISTEN: @@ -449,7 +449,7 @@ static void sco_sock_init(struct sock *sk, struct sock *parent) { - BT_DBG("sk %p", sk); + BT_DBG("sk %pK", sk); if (parent) { sk->sk_type = parent->sk_type; @@ -497,7 +497,7 @@ { struct sock *sk; - BT_DBG("sock %p", sock); + BT_DBG("sock %pK", sock); sock->state = SS_UNCONNECTED; @@ -521,7 +521,7 @@ struct sock *sk = sock->sk; int err = 0; - BT_DBG("sk %p %pMR", sk, &sa->sco_bdaddr); + BT_DBG("sk %pK %pMR", sk, &sa->sco_bdaddr); if (!addr || addr->sa_family != AF_BLUETOOTH) return -EINVAL; @@ -556,7 +556,7 @@ struct sock *sk = sock->sk; int err; - BT_DBG("sk %p", sk); + BT_DBG("sk %pK", sk); if (alen < sizeof(struct sockaddr_sco) || addr->sa_family != AF_BLUETOOTH) @@ -591,7 +591,7 @@ bdaddr_t *src = &sco_pi(sk)->src; int err = 0; - BT_DBG("sk %p backlog %d", sk, backlog); + BT_DBG("sk %pK backlog %d", sk, backlog); lock_sock(sk); @@ -637,7 +637,7 @@ timeo = sock_rcvtimeo(sk, flags & O_NONBLOCK); - BT_DBG("sk %p timeo %ld", sk, timeo); + BT_DBG("sk %pK timeo %ld", sk, timeo); /* Wait for an incoming connection. (wake-one). */ add_wait_queue_exclusive(sk_sleep(sk), &wait); @@ -673,7 +673,7 @@ newsock->state = SS_CONNECTED; - BT_DBG("new socket %p", ch); + BT_DBG("new socket %pK", ch); done: release_sock(sk); @@ -686,7 +686,7 @@ struct sockaddr_sco *sa = (struct sockaddr_sco *) addr; struct sock *sk = sock->sk; - BT_DBG("sock %p, sk %p", sock, sk); + BT_DBG("sock %pK, sk %pK", sock, sk); addr->sa_family = AF_BLUETOOTH; *len = sizeof(struct sockaddr_sco); @@ -705,7 +705,7 @@ struct sock *sk = sock->sk; int err; - BT_DBG("sock %p, sk %p", sock, sk); + BT_DBG("sock %pK, sk %pK", sock, sk); err = sock_error(sk); if (err) @@ -729,7 +729,7 @@ { struct hci_dev *hdev = conn->hdev; - BT_DBG("conn %p", conn); + BT_DBG("conn %pK", conn); conn->state = BT_CONFIG; @@ -799,7 +799,7 @@ struct bt_voice voice; u32 opt; - BT_DBG("sk %p", sk); + BT_DBG("sk %pK", sk); lock_sock(sk); @@ -864,7 +864,7 @@ struct sco_conninfo cinfo; int len, err = 0; - BT_DBG("sk %p", sk); + BT_DBG("sk %pK", sk); if (get_user(len, optlen)) return -EFAULT; @@ -924,7 +924,7 @@ int len, err = 0; struct bt_voice voice; - BT_DBG("sk %p", sk); + BT_DBG("sk %pK", sk); if (level == SOL_SCO) return sco_sock_getsockopt_old(sock, optname, optval, optlen); @@ -971,7 +971,7 @@ struct sock *sk = sock->sk; int err = 0; - BT_DBG("sock %p, sk %p", sock, sk); + BT_DBG("sock %pK, sk %pK", sock, sk); if (!sk) return 0; @@ -1001,7 +1001,7 @@ struct sock *sk = sock->sk; int err = 0; - BT_DBG("sock %p, sk %p", sock, sk); + BT_DBG("sock %pK, sk %pK", sock, sk); if (!sk) return 0; @@ -1025,7 +1025,7 @@ struct sock *parent; struct sock *sk = conn->sk; - BT_DBG("conn %p", conn); + BT_DBG("conn %pK", conn); if (sk) { sco_sock_clear_timer(sk); @@ -1112,7 +1112,7 @@ if (hcon->type != SCO_LINK && hcon->type != ESCO_LINK) return; - BT_DBG("hcon %p bdaddr %pMR status %d", hcon, &hcon->dst, status); + BT_DBG("hcon %pK bdaddr %pMR status %d", hcon, &hcon->dst, status); if (!status) { struct sco_conn *conn; @@ -1129,7 +1129,7 @@ if (hcon->type != SCO_LINK && hcon->type != ESCO_LINK) return; - BT_DBG("hcon %p reason %d", hcon, reason); + BT_DBG("hcon %pK reason %d", hcon, reason); sco_conn_del(hcon, bt_to_errno(reason)); } @@ -1141,7 +1141,7 @@ if (!conn) goto drop; - BT_DBG("conn %p len %d", conn, skb->len); + BT_DBG("conn %pK len %d", conn, skb->len); if (skb->len) { sco_recv_frame(conn, skb); diff -ruw linux-4.4.115/net/bluetooth/smp.c linux-4.4.115-fbx/net/bluetooth/smp.c --- linux-4.4.115/net/bluetooth/smp.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/net/bluetooth/smp.c 2019-10-29 09:26:25.777224062 +0100 @@ -178,7 +178,7 @@ return -EFBIG; if (!tfm) { - BT_ERR("tfm %p", tfm); + BT_ERR("tfm %pK", tfm); return -EINVAL; } @@ -381,7 +381,7 @@ SMP_DBG("k %16phN r %16phN", k, r); if (!tfm) { - BT_ERR("tfm %p", tfm); + BT_ERR("tfm %pK", tfm); return -EINVAL; } @@ -953,7 +953,7 @@ struct smp_cmd_pairing_confirm cp; int ret; - BT_DBG("conn %p", conn); + BT_DBG("conn %pK", conn); ret = smp_c1(smp->tfm_aes, smp->tk, smp->prnd, smp->preq, smp->prsp, conn->hcon->init_addr_type, &conn->hcon->init_addr, @@ -984,7 +984,7 @@ if (IS_ERR_OR_NULL(smp->tfm_aes)) return SMP_UNSPECIFIED; - BT_DBG("conn %p %s", conn, conn->hcon->out ? "master" : "slave"); + BT_DBG("conn %pK %s", conn, conn->hcon->out ? "master" : "slave"); ret = smp_c1(smp->tfm_aes, smp->tk, smp->rrnd, smp->preq, smp->prsp, hcon->init_addr_type, &hcon->init_addr, @@ -1223,7 +1223,7 @@ struct hci_dev *hdev = hcon->hdev; __u8 *keydist; - BT_DBG("conn %p", conn); + BT_DBG("conn %pK", conn); rsp = (void *) &smp->prsp[1]; @@ -1353,7 +1353,7 @@ security_timer.work); struct l2cap_conn *conn = smp->conn; - BT_DBG("conn %p", conn); + BT_DBG("conn %pK", conn); hci_disconnect(conn->hcon, HCI_ERROR_REMOTE_USER_TERM); } @@ -1715,7 +1715,7 @@ u8 key_size, auth, sec_level; int ret; - BT_DBG("conn %p", conn); + BT_DBG("conn %pK", conn); if (skb->len < sizeof(*req)) return SMP_INVALID_PARAMS; @@ -1900,7 +1900,7 @@ u8 key_size, auth; int ret; - BT_DBG("conn %p", conn); + BT_DBG("conn %pK", conn); if (skb->len < sizeof(*rsp)) return SMP_INVALID_PARAMS; @@ -2052,7 +2052,7 @@ struct l2cap_chan *chan = conn->smp; struct smp_chan *smp = chan->data; - BT_DBG("conn %p %s", conn, conn->hcon->out ? "master" : "slave"); + BT_DBG("conn %pK %s", conn, conn->hcon->out ? "master" : "slave"); if (skb->len < sizeof(smp->pcnf)) return SMP_INVALID_PARAMS; @@ -2098,7 +2098,7 @@ u32 passkey; int err; - BT_DBG("conn %p", conn); + BT_DBG("conn %pK", conn); if (skb->len < sizeof(smp->rrnd)) return SMP_INVALID_PARAMS; @@ -2233,7 +2233,7 @@ struct smp_chan *smp; u8 sec_level, auth; - BT_DBG("conn %p", conn); + BT_DBG("conn %pK", conn); if (skb->len < sizeof(*rp)) return SMP_INVALID_PARAMS; @@ -2290,7 +2290,7 @@ __u8 authreq; int ret; - BT_DBG("conn %p hcon %p level 0x%2.2x", conn, hcon, sec_level); + BT_DBG("conn %pK hcon %pK level 0x%2.2x", conn, hcon, sec_level); /* This may be NULL if there's an unexpected disconnection */ if (!conn) @@ -2397,7 +2397,7 @@ struct l2cap_chan *chan = conn->smp; struct smp_chan *smp = chan->data; - BT_DBG("conn %p", conn); + BT_DBG("conn %pK", conn); if (skb->len < sizeof(*rp)) return SMP_INVALID_PARAMS; @@ -2421,7 +2421,7 @@ struct smp_ltk *ltk; u8 authenticated; - BT_DBG("conn %p", conn); + BT_DBG("conn %pK", conn); if (skb->len < sizeof(*rp)) return SMP_INVALID_PARAMS; @@ -2530,7 +2530,7 @@ struct smp_chan *smp = chan->data; struct smp_csrk *csrk; - BT_DBG("conn %p", conn); + BT_DBG("conn %pK", conn); if (skb->len < sizeof(*rp)) return SMP_INVALID_PARAMS; @@ -2609,7 +2609,7 @@ struct smp_cmd_pairing_confirm cfm; int err; - BT_DBG("conn %p", conn); + BT_DBG("conn %pK", conn); if (skb->len < sizeof(*key)) return SMP_INVALID_PARAMS; @@ -2722,7 +2722,7 @@ u8 io_cap[3], r[16], e[16]; int err; - BT_DBG("conn %p", conn); + BT_DBG("conn %pK", conn); if (skb->len < sizeof(*check)) return SMP_INVALID_PARAMS; @@ -2904,7 +2904,7 @@ { struct l2cap_conn *conn = chan->conn; - BT_DBG("chan %p", chan); + BT_DBG("chan %pK", chan); if (chan->data) smp_chan_destroy(conn); @@ -2921,7 +2921,7 @@ struct smp_cmd_pairing req; struct smp_chan *smp; - BT_DBG("chan %p", chan); + BT_DBG("chan %pK", chan); /* Only new pairings are interesting */ if (!test_bit(HCI_CONN_NEW_LINK_KEY, &hcon->flags)) @@ -2987,7 +2987,7 @@ struct l2cap_conn *conn = chan->conn; struct hci_conn *hcon = conn->hcon; - BT_DBG("chan %p", chan); + BT_DBG("chan %pK", chan); if (hcon->type == ACL_LINK) { bredr_pairing(chan); @@ -3010,7 +3010,7 @@ struct l2cap_conn *conn = chan->conn; struct hci_conn *hcon = conn->hcon; - BT_DBG("chan %p", chan); + BT_DBG("chan %pK", chan); /* No need to call l2cap_chan_hold() here since we already own * the reference taken in smp_new_conn_cb(). This is just the @@ -3028,7 +3028,7 @@ { int err; - BT_DBG("chan %p", chan); + BT_DBG("chan %pK", chan); err = smp_sig_channel(chan, skb); if (err) { @@ -3080,7 +3080,7 @@ { struct l2cap_chan *chan; - BT_DBG("pchan %p", pchan); + BT_DBG("pchan %pK", pchan); chan = l2cap_chan_create(); if (!chan) @@ -3101,7 +3101,7 @@ */ atomic_set(&chan->nesting, L2CAP_NESTING_SMP); - BT_DBG("created chan %p", chan); + BT_DBG("created chan %pK", chan); return chan; } @@ -3206,7 +3206,7 @@ { struct smp_dev *smp; - BT_DBG("chan %p", chan); + BT_DBG("chan %pK", chan); smp = chan->data; if (smp) { diff -ruw linux-4.4.115/net/bridge/br_device.c linux-4.4.115-fbx/net/bridge/br_device.c --- linux-4.4.115/net/bridge/br_device.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/net/bridge/br_device.c 2019-01-22 16:16:28.887295162 +0100 @@ -48,16 +48,17 @@ return NETDEV_TX_OK; } - u64_stats_update_begin(&brstats->syncp); - brstats->tx_packets++; - brstats->tx_bytes += skb->len; - u64_stats_update_end(&brstats->syncp); - BR_INPUT_SKB_CB(skb)->brdev = dev; skb_reset_mac_header(skb); skb_pull(skb, ETH_HLEN); + u64_stats_update_begin(&brstats->syncp); + brstats->tx_packets++; + /* Exclude ETH_HLEN from byte stats for consistency with Rx chain */ + brstats->tx_bytes += skb->len; + u64_stats_update_end(&brstats->syncp); + if (!br_allowed_ingress(br, br_vlan_group_rcu(br), skb, &vid)) goto out; diff -ruw linux-4.4.115/net/core/dev.c linux-4.4.115-fbx/net/core/dev.c --- linux-4.4.115/net/core/dev.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/net/core/dev.c 2019-10-29 09:26:25.793224218 +0100 @@ -137,6 +137,8 @@ #include #include #include +#include +#include #include "net-sysfs.h" @@ -1150,8 +1152,6 @@ BUG_ON(!dev_net(dev)); net = dev_net(dev); - if (dev->flags & IFF_UP) - return -EBUSY; write_seqcount_begin(&devnet_rename_seq); @@ -2807,6 +2807,10 @@ if (netif_needs_gso(skb, features)) { struct sk_buff *segs; + __be16 src_port = tcp_hdr(skb)->source; + __be16 dest_port = tcp_hdr(skb)->dest; + + trace_print_skb_gso(skb, src_port, dest_port); segs = skb_gso_segment(skb, features); if (IS_ERR(segs)) { goto out_kfree_skb; @@ -2846,7 +2850,7 @@ struct sk_buff *validate_xmit_skb_list(struct sk_buff *skb, struct net_device *dev) { - struct sk_buff *next, *head = NULL, *tail; + struct sk_buff *next, *head = NULL, *tail = NULL; for (; skb != NULL; skb = next) { next = skb->next; @@ -4159,6 +4163,7 @@ } out: + __this_cpu_add(softnet_data.gro_coalesced, NAPI_GRO_CB(skb)->count > 1); return netif_receive_skb_internal(skb); } @@ -4201,6 +4206,7 @@ unsigned long diffs; NAPI_GRO_CB(p)->flush = 0; + NAPI_GRO_CB(p)->flush_id = 0; if (hash != skb_get_hash_raw(p)) { NAPI_GRO_CB(p)->same_flow = 0; @@ -4579,6 +4585,24 @@ } EXPORT_SYMBOL(__skb_gro_checksum_complete); +static void net_rps_send_ipi(struct softnet_data *remsd) +{ +#ifdef CONFIG_RPS + while (remsd) { + struct softnet_data *next = remsd->rps_ipi_next; + + if (cpu_online(remsd->cpu)) { + smp_call_function_single_async(remsd->cpu, &remsd->csd); + } else { + rps_lock(remsd); + remsd->backlog.state = 0; + rps_unlock(remsd); + } + remsd = next; + } +#endif +} + /* * net_rps_action_and_irq_enable sends any pending IPI's for rps. * Note: called with local irq disabled, but exits with local irq enabled. @@ -4594,14 +4618,7 @@ local_irq_enable(); /* Send pending IPI's to kick RPS processing on remote cpus. */ - while (remsd) { - struct softnet_data *next = remsd->rps_ipi_next; - - if (cpu_online(remsd->cpu)) - smp_call_function_single_async(remsd->cpu, - &remsd->csd); - remsd = next; - } + net_rps_send_ipi(remsd); } else #endif local_irq_enable(); @@ -4642,8 +4659,7 @@ local_irq_disable(); input_queue_head_incr(sd); if (++work >= quota) { - local_irq_enable(); - return work; + goto state_changed; } } @@ -4660,14 +4676,17 @@ napi->state = 0; rps_unlock(sd); - break; + goto state_changed; } skb_queue_splice_tail_init(&sd->input_pkt_queue, &sd->process_queue); rps_unlock(sd); } +state_changed: local_irq_enable(); + napi_gro_flush(napi, false); + sd->current_napi = NULL; return work; } @@ -4703,10 +4722,13 @@ void __napi_complete(struct napi_struct *n) { + struct softnet_data *sd = this_cpu_ptr(&softnet_data); + BUG_ON(!test_bit(NAPI_STATE_SCHED, &n->state)); list_del_init(&n->poll_list); smp_mb__before_atomic(); + sd->current_napi = NULL; clear_bit(NAPI_STATE_SCHED, &n->state); } EXPORT_SYMBOL(__napi_complete); @@ -4856,6 +4878,15 @@ } EXPORT_SYMBOL(netif_napi_del); + +struct napi_struct *get_current_napi_context(void) +{ + struct softnet_data *sd = this_cpu_ptr(&softnet_data); + + return sd->current_napi; +} +EXPORT_SYMBOL(get_current_napi_context); + static int napi_poll(struct napi_struct *n, struct list_head *repoll) { void *have; @@ -4875,6 +4906,9 @@ */ work = 0; if (test_bit(NAPI_STATE_SCHED, &n->state)) { + struct softnet_data *sd = this_cpu_ptr(&softnet_data); + + sd->current_napi = n; work = n->poll(n, weight); trace_napi_poll(n); } @@ -6947,7 +6981,7 @@ rebroadcast_time = jiffies; } - msleep(250); + msleep(1); refcnt = netdev_refcnt_read(dev); @@ -7496,7 +7530,7 @@ struct sk_buff **list_skb; struct sk_buff *skb; unsigned int cpu, oldcpu = (unsigned long)ocpu; - struct softnet_data *sd, *oldsd; + struct softnet_data *sd, *oldsd, *remsd; if (action != CPU_DEAD && action != CPU_DEAD_FROZEN) return NOTIFY_OK; @@ -7540,6 +7574,13 @@ raise_softirq_irqoff(NET_TX_SOFTIRQ); local_irq_enable(); +#ifdef CONFIG_RPS + remsd = oldsd->rps_ipi_list; + oldsd->rps_ipi_list = NULL; +#endif + /* send out pending IPI's on offline CPU */ + net_rps_send_ipi(remsd); + /* Process offline CPU's input_pkt_queue */ while ((skb = __skb_dequeue(&oldsd->process_queue))) { netif_rx_ni(skb); diff -ruw linux-4.4.115/net/core/flow_dissector.c linux-4.4.115-fbx/net/core/flow_dissector.c --- linux-4.4.115/net/core/flow_dissector.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/net/core/flow_dissector.c 2019-10-29 09:26:25.797224257 +0100 @@ -18,6 +18,7 @@ #include #include #include +#include static bool dissector_uses_key(const struct flow_dissector *flow_dissector, enum flow_dissector_key_id key_id) @@ -338,6 +339,40 @@ goto out_good; } + case __constant_htons(ETH_P_MAP): { + struct { + struct rmnet_map_header_s map; + uint8_t proto; + } *map, _map; + unsigned int maplen; + + map = skb_header_pointer(skb, nhoff, sizeof(_map), &_map); + if (!map) + return false; + + /* Is MAP command? */ + if (map->map.cd_bit) + return false; + + /* Is aggregated frame? */ + maplen = ntohs(map->map.pkt_len); + maplen += map->map.pad_len; + maplen += sizeof(struct rmnet_map_header_s); + if (maplen < skb->len) + return false; + + nhoff += sizeof(struct rmnet_map_header_s); + switch (map->proto & RMNET_IP_VER_MASK) { + case RMNET_IPV4: + proto = htons(ETH_P_IP); + goto ip; + case RMNET_IPV6: + proto = htons(ETH_P_IPV6); + goto ipv6; + default: + return false; + } + } case htons(ETH_P_FCOE): key_control->thoff = (u16)(nhoff + FCOE_HEADER_LEN); /* fall through */ diff -ruw linux-4.4.115/net/core/Makefile linux-4.4.115-fbx/net/core/Makefile --- linux-4.4.115/net/core/Makefile 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/net/core/Makefile 2019-10-29 09:26:25.789224179 +0100 @@ -24,3 +24,4 @@ obj-$(CONFIG_CGROUP_NET_PRIO) += netprio_cgroup.o obj-$(CONFIG_CGROUP_NET_CLASSID) += netclassid_cgroup.o obj-$(CONFIG_LWTUNNEL) += lwtunnel.o +obj-$(CONFIG_SOCKEV_NLMCAST) += sockev_nlmcast.o diff -ruw linux-4.4.115/net/core/neighbour.c linux-4.4.115-fbx/net/core/neighbour.c --- linux-4.4.115/net/core/neighbour.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/net/core/neighbour.c 2019-10-29 09:26:25.801224296 +0100 @@ -687,7 +687,7 @@ NEIGH_CACHE_STAT_INC(neigh->tbl, destroys); if (!neigh->dead) { - pr_warn("Destroying alive neighbour %p\n", neigh); + pr_warn("Destroying alive neighbour %pK\n", neigh); dump_stack(); return; } diff -ruw linux-4.4.115/net/core/net-procfs.c linux-4.4.115-fbx/net/core/net-procfs.c --- linux-4.4.115/net/core/net-procfs.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/net/core/net-procfs.c 2019-01-22 16:16:28.915295415 +0100 @@ -159,10 +159,11 @@ #endif seq_printf(seq, - "%08x %08x %08x %08x %08x %08x %08x %08x %08x %08x %08x\n", + "%08x %08x %08x %08x %08x %08x %08x %08x %08x %08x %08x %08x\n", sd->processed, sd->dropped, sd->time_squeeze, 0, 0, 0, 0, 0, /* was fastroute */ - sd->cpu_collision, sd->received_rps, flow_limit_count); + sd->cpu_collision, sd->received_rps, flow_limit_count, + sd->gro_coalesced); return 0; } diff -ruw linux-4.4.115/net/core/net-sysfs.c linux-4.4.115-fbx/net/core/net-sysfs.c --- linux-4.4.115/net/core/net-sysfs.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/net/core/net-sysfs.c 2019-10-29 09:26:25.801224296 +0100 @@ -18,6 +18,7 @@ #include #include #include +#include #include #include #include @@ -608,7 +609,24 @@ }; #if IS_ENABLED(CONFIG_WIRELESS_EXT) || IS_ENABLED(CONFIG_CFG80211) +static ssize_t show_nl80211_iftype(struct device *dev, + struct device_attribute *attr, char *buf) +{ + const struct net_device *netdev = to_net_dev(dev); + ssize_t ret = 0; + + if (!rtnl_trylock()) + return restart_syscall(); + if (netdev->ieee80211_ptr) + ret = sprintf(buf, "%d\n", netdev->ieee80211_ptr->iftype); + rtnl_unlock(); + + return ret; +} +static DEVICE_ATTR(nl80211_iftype, S_IRUGO, show_nl80211_iftype, NULL); + static struct attribute *wireless_attrs[] = { + &dev_attr_nl80211_iftype.attr, NULL }; diff -ruw linux-4.4.115/net/core/skbuff.c linux-4.4.115-fbx/net/core/skbuff.c --- linux-4.4.115/net/core/skbuff.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/net/core/skbuff.c 2019-10-29 09:26:25.809224375 +0100 @@ -208,6 +208,9 @@ u8 *data; bool pfmemalloc; + if (IS_ENABLED(CONFIG_FORCE_ALLOC_FROM_DMA_ZONE)) + gfp_mask |= GFP_DMA; + cache = (flags & SKB_ALLOC_FCLONE) ? skbuff_fclone_cache : skbuff_head_cache; @@ -358,6 +361,9 @@ unsigned long flags; void *data; + if (IS_ENABLED(CONFIG_FORCE_ALLOC_FROM_DMA_ZONE)) + gfp_mask |= GFP_DMA; + local_irq_save(flags); nc = this_cpu_ptr(&netdev_alloc_cache); data = __alloc_page_frag(nc, fragsz, gfp_mask); @@ -404,6 +410,7 @@ * * %NULL is returned if there is no free memory. */ +#ifndef CONFIG_DISABLE_NET_SKB_FRAG_CACHE struct sk_buff *__netdev_alloc_skb(struct net_device *dev, unsigned int len, gfp_t gfp_mask) { @@ -415,6 +422,9 @@ len += NET_SKB_PAD; + if (IS_ENABLED(CONFIG_FORCE_ALLOC_FROM_DMA_ZONE)) + gfp_mask |= GFP_DMA; + if ((len > SKB_WITH_OVERHEAD(PAGE_SIZE)) || (gfp_mask & (__GFP_DIRECT_RECLAIM | GFP_DMA))) { skb = __alloc_skb(len, gfp_mask, SKB_ALLOC_RX, NUMA_NO_NODE); @@ -458,6 +468,22 @@ skb_fail: return skb; } +#else +struct sk_buff *__netdev_alloc_skb(struct net_device *dev, + unsigned int length, gfp_t gfp_mask) +{ + struct sk_buff *skb = NULL; + + skb = __alloc_skb(length + NET_SKB_PAD, gfp_mask, + SKB_ALLOC_RX, NUMA_NO_NODE); + if (likely(skb)) { + skb_reserve(skb, NET_SKB_PAD); + skb->dev = dev; + } + return skb; +} +#endif + EXPORT_SYMBOL(__netdev_alloc_skb); /** diff -ruw linux-4.4.115/net/core/sock.c linux-4.4.115-fbx/net/core/sock.c --- linux-4.4.115/net/core/sock.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/net/core/sock.c 2019-10-29 09:26:25.809224375 +0100 @@ -1439,8 +1439,12 @@ } EXPORT_SYMBOL(sk_alloc); -void sk_destruct(struct sock *sk) +/* Sockets having SOCK_RCU_FREE will call this function after one RCU + * grace period. This is the case for UDP sockets and TCP listeners. + */ +static void __sk_destruct(struct rcu_head *head) { + struct sock *sk = container_of(head, struct sock, sk_rcu); struct sk_filter *filter; if (sk->sk_destruct) @@ -1472,6 +1476,14 @@ sk_prot_free(sk->sk_prot_creator, sk); } +void sk_destruct(struct sock *sk) +{ + if (sock_flag(sk, SOCK_RCU_FREE)) + call_rcu(&sk->sk_rcu, __sk_destruct); + else + __sk_destruct(&sk->sk_rcu); +} + static void __sk_free(struct sock *sk) { if (unlikely(sock_diag_has_destroy_listeners(sk) && sk->sk_net_refcnt)) @@ -2397,8 +2409,11 @@ sk->sk_type = sock->type; sk->sk_wq = sock->wq; sock->sk = sk; - } else + sk->sk_uid = SOCK_INODE(sock)->i_uid; + } else { sk->sk_wq = NULL; + sk->sk_uid = make_kuid(sock_net(sk)->user_ns, 0); + } rwlock_init(&sk->sk_callback_lock); lockdep_set_class_and_name(&sk->sk_callback_lock, diff -ruw linux-4.4.115/net/core/sock_diag.c linux-4.4.115-fbx/net/core/sock_diag.c --- linux-4.4.115/net/core/sock_diag.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/net/core/sock_diag.c 2019-01-22 16:16:28.927295524 +0100 @@ -214,7 +214,7 @@ } EXPORT_SYMBOL_GPL(sock_diag_unregister); -static int __sock_diag_rcv_msg(struct sk_buff *skb, struct nlmsghdr *nlh) +static int __sock_diag_cmd(struct sk_buff *skb, struct nlmsghdr *nlh) { int err; struct sock_diag_req *req = nlmsg_data(nlh); @@ -234,8 +234,12 @@ hndl = sock_diag_handlers[req->sdiag_family]; if (hndl == NULL) err = -ENOENT; - else + else if (nlh->nlmsg_type == SOCK_DIAG_BY_FAMILY) err = hndl->dump(skb, nlh); + else if (nlh->nlmsg_type == SOCK_DESTROY_BACKPORT && hndl->destroy) + err = hndl->destroy(skb, nlh); + else + err = -EOPNOTSUPP; mutex_unlock(&sock_diag_table_mutex); return err; @@ -261,7 +265,8 @@ return ret; case SOCK_DIAG_BY_FAMILY: - return __sock_diag_rcv_msg(skb, nlh); + case SOCK_DESTROY_BACKPORT: + return __sock_diag_cmd(skb, nlh); default: return -EINVAL; } @@ -295,6 +300,18 @@ return 0; } +int sock_diag_destroy(struct sock *sk, int err) +{ + if (!ns_capable(sock_net(sk)->user_ns, CAP_NET_ADMIN)) + return -EPERM; + + if (!sk->sk_prot->diag_destroy) + return -EOPNOTSUPP; + + return sk->sk_prot->diag_destroy(sk, err); +} +EXPORT_SYMBOL_GPL(sock_diag_destroy); + static int __net_init diag_net_init(struct net *net) { struct netlink_kernel_cfg cfg = { diff -ruw linux-4.4.115/net/ipv4/af_inet.c linux-4.4.115-fbx/net/ipv4/af_inet.c --- linux-4.4.115/net/ipv4/af_inet.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/net/ipv4/af_inet.c 2019-10-29 09:26:25.821224492 +0100 @@ -89,6 +89,7 @@ #include #include #include +#include #include @@ -121,6 +122,21 @@ #endif #include +#ifdef CONFIG_ANDROID_PARANOID_NETWORK +#include + +static inline int current_has_network(void) +{ + return in_egroup_p(AID_INET) || capable(CAP_NET_RAW); +} +#else +static inline int current_has_network(void) +{ + return 1; +} +#endif + +int sysctl_reserved_port_bind __read_mostly = 1; /* The inetsw table contains everything that inet_create needs to * build a new socket. @@ -260,6 +276,9 @@ if (protocol < 0 || protocol >= IPPROTO_MAX) return -EINVAL; + if (!current_has_network()) + return -EACCES; + sock->state = SS_UNCONNECTED; /* Look for the requested type/protocol pair. */ @@ -308,8 +327,7 @@ } err = -EPERM; - if (sock->type == SOCK_RAW && !kern && - !ns_capable(net->user_ns, CAP_NET_RAW)) + if (sock->type == SOCK_RAW && !kern && !capable(CAP_NET_RAW)) goto out_rcu_unlock; sock->ops = answer->ops; @@ -398,6 +416,9 @@ if (sk) { long timeout; +#ifdef CONFIG_NETFILTER_XT_MATCH_QTAGUID + qtaguid_untag(sock, true); +#endif /* Applications forget to leave groups before exiting */ ip_mc_drop_socket(sk); @@ -1327,6 +1348,7 @@ for (p = *head; p; p = p->next) { struct iphdr *iph2; + u16 flush_id; if (!NAPI_GRO_CB(p)->same_flow) continue; @@ -1350,14 +1372,24 @@ (iph->tos ^ iph2->tos) | ((iph->frag_off ^ iph2->frag_off) & htons(IP_DF)); - /* Save the IP ID check to be included later when we get to - * the transport layer so only the inner most IP ID is checked. - * This is because some GSO/TSO implementations do not - * correctly increment the IP ID for the outer hdrs. - */ - NAPI_GRO_CB(p)->flush_id = - ((u16)(ntohs(iph2->id) + NAPI_GRO_CB(p)->count) ^ id); NAPI_GRO_CB(p)->flush |= flush; + + /* We must save the offset as it is possible to have multiple + * flows using the same protocol and address pairs so we + * need to wait until we can validate this is part of the + * same flow with a 5-tuple or better to avoid unnecessary + * collisions between flows. We can support one of two + * possible scenarios, either a fixed value with DF bit set + * or an incrementing value with DF either set or unset. + * In the case of a fixed value we will end up losing the + * data that the IP ID was a fixed value, however per RFC + * 6864 in such a case the actual value of the IP ID is + * meant to be ignored anyway. + */ + flush_id = (u16)(id - ntohs(iph2->id)); + if (flush_id || !(iph2->frag_off & htons(IP_DF))) + NAPI_GRO_CB(p)->flush_id |= flush_id ^ + NAPI_GRO_CB(p)->count; } NAPI_GRO_CB(skb)->flush |= flush; diff -ruw linux-4.4.115/net/ipv4/devinet.c linux-4.4.115-fbx/net/ipv4/devinet.c --- linux-4.4.115/net/ipv4/devinet.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/net/ipv4/devinet.c 2019-10-29 09:26:25.825224531 +0100 @@ -2196,6 +2196,8 @@ "promote_secondaries"), DEVINET_SYSCTL_FLUSHING_ENTRY(ROUTE_LOCALNET, "route_localnet"), + DEVINET_SYSCTL_RW_ENTRY(NF_IPV4_DEFRAG_SKIP, + "nf_ipv4_defrag_skip"), }, }; diff -ruw linux-4.4.115/net/ipv4/fib_frontend.c linux-4.4.115-fbx/net/ipv4/fib_frontend.c --- linux-4.4.115/net/ipv4/fib_frontend.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/net/ipv4/fib_frontend.c 2019-10-29 09:26:25.825224531 +0100 @@ -627,6 +627,7 @@ [RTA_FLOW] = { .type = NLA_U32 }, [RTA_ENCAP_TYPE] = { .type = NLA_U16 }, [RTA_ENCAP] = { .type = NLA_NESTED }, + [RTA_UID] = { .type = NLA_U32 }, }; static int rtm_to_fib_config(struct net *net, struct sk_buff *skb, diff -ruw linux-4.4.115/net/ipv4/fib_trie.c linux-4.4.115-fbx/net/ipv4/fib_trie.c --- linux-4.4.115/net/ipv4/fib_trie.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/net/ipv4/fib_trie.c 2019-10-29 09:26:25.829224570 +0100 @@ -1694,7 +1694,7 @@ lt = (struct trie *)local_tb->tb_data; while ((l = leaf_walk_rcu(&tp, key)) != NULL) { - struct key_vector *local_l = NULL, *local_tp; + struct key_vector *local_l = NULL, *local_tp = NULL; hlist_for_each_entry_rcu(fa, &l->leaf, fa_list) { struct fib_alias *new_fa; diff -ruw linux-4.4.115/net/ipv4/icmp.c linux-4.4.115-fbx/net/ipv4/icmp.c --- linux-4.4.115/net/ipv4/icmp.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/net/ipv4/icmp.c 2019-10-29 09:26:25.829224570 +0100 @@ -425,6 +425,7 @@ fl4.daddr = daddr; fl4.saddr = saddr; fl4.flowi4_mark = mark; + fl4.flowi4_uid = sock_net_uid(net, NULL); fl4.flowi4_tos = RT_TOS(ip_hdr(skb)->tos); fl4.flowi4_proto = IPPROTO_ICMP; fl4.flowi4_oif = l3mdev_master_ifindex(skb->dev); @@ -473,6 +474,7 @@ param->replyopts.opt.opt.faddr : iph->saddr); fl4->saddr = saddr; fl4->flowi4_mark = mark; + fl4->flowi4_uid = sock_net_uid(net, NULL); fl4->flowi4_tos = RT_TOS(tos); fl4->flowi4_proto = IPPROTO_ICMP; fl4->fl4_icmp_type = type; diff -ruw linux-4.4.115/net/ipv4/inet_connection_sock.c linux-4.4.115-fbx/net/ipv4/inet_connection_sock.c --- linux-4.4.115/net/ipv4/inet_connection_sock.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/net/ipv4/inet_connection_sock.c 2019-10-29 09:26:25.829224570 +0100 @@ -179,6 +179,13 @@ head = &hashinfo->bhash[inet_bhashfn(net, snum, hashinfo->bhash_size)]; spin_lock(&head->lock); + + if (inet_is_local_reserved_port(net, snum) && + !sysctl_reserved_port_bind) { + ret = 1; + goto fail_unlock; + } + inet_bind_bucket_for_each(tb, &head->chain) if (net_eq(ib_net(tb), net) && tb->port == snum) goto tb_found; @@ -422,7 +429,7 @@ sk->sk_protocol, inet_sk_flowi_flags(sk), (opt && opt->opt.srr) ? opt->opt.faddr : ireq->ir_rmt_addr, ireq->ir_loc_addr, ireq->ir_rmt_port, - htons(ireq->ir_num)); + htons(ireq->ir_num), sk->sk_uid); security_req_classify_flow(req, flowi4_to_flowi(fl4)); rt = ip_route_output_flow(net, fl4, sk); if (IS_ERR(rt)) @@ -458,7 +465,7 @@ sk->sk_protocol, inet_sk_flowi_flags(sk), (opt && opt->opt.srr) ? opt->opt.faddr : ireq->ir_rmt_addr, ireq->ir_loc_addr, ireq->ir_rmt_port, - htons(ireq->ir_num)); + htons(ireq->ir_num), sk->sk_uid); security_req_classify_flow(req, flowi4_to_flowi(fl4)); rt = ip_route_output_flow(net, fl4, sk); if (IS_ERR(rt)) diff -ruw linux-4.4.115/net/ipv4/inet_lro.c linux-4.4.115-fbx/net/ipv4/inet_lro.c --- linux-4.4.115/net/ipv4/inet_lro.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/net/ipv4/inet_lro.c 2019-01-22 16:16:28.955295778 +0100 @@ -145,19 +145,36 @@ } static void lro_init_desc(struct net_lro_desc *lro_desc, struct sk_buff *skb, - struct iphdr *iph, struct tcphdr *tcph) + struct iphdr *iph, struct tcphdr *tcph, + struct net_lro_info *lro_info) { int nr_frags; __be32 *ptr; u32 tcp_data_len = TCP_PAYLOAD_LENGTH(iph, tcph); + u64 hw_marked = 0; + + if (lro_info) + hw_marked = lro_info->valid_fields; nr_frags = skb_shinfo(skb)->nr_frags; lro_desc->parent = skb; lro_desc->next_frag = &(skb_shinfo(skb)->frags[nr_frags]); lro_desc->iph = iph; lro_desc->tcph = tcph; + + if (hw_marked & LRO_TCP_SEQ_NUM) + lro_desc->tcp_next_seq = lro_info->tcp_seq_num + tcp_data_len; + else lro_desc->tcp_next_seq = ntohl(tcph->seq) + tcp_data_len; + + if (hw_marked & LRO_TCP_ACK_NUM) + lro_desc->tcp_ack = htonl(lro_info->tcp_ack_num); + else lro_desc->tcp_ack = tcph->ack_seq; + + if (hw_marked & LRO_TCP_WIN) + lro_desc->tcp_window = htons(lro_info->tcp_win); + else lro_desc->tcp_window = tcph->window; lro_desc->pkt_aggr_cnt = 1; @@ -173,6 +190,9 @@ lro_desc->mss = tcp_data_len; lro_desc->active = 1; + if (hw_marked & LRO_TCP_DATA_CSUM) + lro_desc->data_csum = lro_info->tcp_data_csum; + else lro_desc->data_csum = lro_tcp_data_csum(iph, tcph, tcp_data_len); } @@ -183,15 +203,28 @@ } static void lro_add_common(struct net_lro_desc *lro_desc, struct iphdr *iph, - struct tcphdr *tcph, int tcp_data_len) + struct tcphdr *tcph, int tcp_data_len, + struct net_lro_info *lro_info) { struct sk_buff *parent = lro_desc->parent; __be32 *topt; + u64 hw_marked = 0; + + if (lro_info) + hw_marked = lro_info->valid_fields; lro_desc->pkt_aggr_cnt++; lro_desc->ip_tot_len += tcp_data_len; lro_desc->tcp_next_seq += tcp_data_len; + + if (hw_marked & LRO_TCP_WIN) + lro_desc->tcp_window = htons(lro_info->tcp_win); + else lro_desc->tcp_window = tcph->window; + + if (hw_marked & LRO_TCP_ACK_NUM) + lro_desc->tcp_ack = htonl(lro_info->tcp_ack_num); + else lro_desc->tcp_ack = tcph->ack_seq; /* don't update tcp_rcv_tsval, would not work with PAWS */ @@ -200,8 +233,15 @@ lro_desc->tcp_rcv_tsecr = *(topt + 2); } + if (hw_marked & LRO_TCP_DATA_CSUM) lro_desc->data_csum = csum_block_add(lro_desc->data_csum, - lro_tcp_data_csum(iph, tcph, + lro_info->tcp_data_csum, + parent->len); + else + lro_desc->data_csum = + csum_block_add(lro_desc->data_csum, + lro_tcp_data_csum(iph, + tcph, tcp_data_len), parent->len); @@ -212,12 +252,13 @@ } static void lro_add_packet(struct net_lro_desc *lro_desc, struct sk_buff *skb, - struct iphdr *iph, struct tcphdr *tcph) + struct iphdr *iph, struct tcphdr *tcph, + struct net_lro_info *lro_info) { struct sk_buff *parent = lro_desc->parent; int tcp_data_len = TCP_PAYLOAD_LENGTH(iph, tcph); - lro_add_common(lro_desc, iph, tcph, tcp_data_len); + lro_add_common(lro_desc, iph, tcph, tcp_data_len, lro_info); skb_pull(skb, (skb->len - tcp_data_len)); parent->truesize += skb->truesize; @@ -230,6 +271,29 @@ lro_desc->last_skb = skb; } +static void lro_add_frags(struct net_lro_desc *lro_desc, + int len, int hlen, int truesize, + struct skb_frag_struct *skb_frags, + struct iphdr *iph, struct tcphdr *tcph) +{ + struct sk_buff *skb = lro_desc->parent; + int tcp_data_len = TCP_PAYLOAD_LENGTH(iph, tcph); + + lro_add_common(lro_desc, iph, tcph, tcp_data_len, NULL); + + skb->truesize += truesize; + + skb_frags[0].page_offset += hlen; + skb_frag_size_sub(&skb_frags[0], hlen); + + while (tcp_data_len > 0) { + *lro_desc->next_frag = *skb_frags; + tcp_data_len -= skb_frag_size(skb_frags); + lro_desc->next_frag++; + skb_frags++; + skb_shinfo(skb)->nr_frags++; + } +} static int lro_check_tcp_conn(struct net_lro_desc *lro_desc, struct iphdr *iph, @@ -284,6 +348,8 @@ if (lro_mgr->features & LRO_F_NAPI) netif_receive_skb(lro_desc->parent); + else if (lro_mgr->features & LRO_F_NI) + netif_rx_ni(lro_desc->parent); else netif_rx(lro_desc->parent); @@ -292,12 +358,13 @@ } static int __lro_proc_skb(struct net_lro_mgr *lro_mgr, struct sk_buff *skb, - void *priv) + void *priv, struct net_lro_info *lro_info) { struct net_lro_desc *lro_desc; struct iphdr *iph; struct tcphdr *tcph; u64 flags; + u64 hw_marked = 0; int vlan_hdr_len = 0; if (!lro_mgr->get_skb_header || @@ -308,7 +375,14 @@ if (!(flags & LRO_IPV4) || !(flags & LRO_TCP)) goto out; + if (lro_info) + hw_marked = lro_info->valid_fields; + + if (hw_marked & LRO_DESC) + lro_desc = lro_info->lro_desc; + else lro_desc = lro_get_desc(lro_mgr, lro_mgr->lro_arr, iph, tcph); + if (!lro_desc) goto out; @@ -317,22 +391,38 @@ vlan_hdr_len = VLAN_HLEN; if (!lro_desc->active) { /* start new lro session */ - if (lro_tcp_ip_check(iph, tcph, skb->len - vlan_hdr_len, NULL)) + if (hw_marked & LRO_ELIGIBILITY_CHECKED) { + if (!lro_info->lro_eligible) goto out; + } else { + if (lro_tcp_ip_check(iph, tcph, + skb->len - vlan_hdr_len, NULL)) + goto out; + } skb->ip_summed = lro_mgr->ip_summed_aggr; - lro_init_desc(lro_desc, skb, iph, tcph); + lro_init_desc(lro_desc, skb, iph, tcph, lro_info); LRO_INC_STATS(lro_mgr, aggregated); return 0; } + if (hw_marked & LRO_TCP_SEQ_NUM) { + if (lro_desc->tcp_next_seq != lro_info->tcp_seq_num) + goto out2; + } else { if (lro_desc->tcp_next_seq != ntohl(tcph->seq)) goto out2; + } + if (hw_marked & LRO_ELIGIBILITY_CHECKED) { + if (!lro_info->lro_eligible) + goto out2; + } else { if (lro_tcp_ip_check(iph, tcph, skb->len, lro_desc)) goto out2; + } - lro_add_packet(lro_desc, skb, iph, tcph); + lro_add_packet(lro_desc, skb, iph, tcph, lro_info); LRO_INC_STATS(lro_mgr, aggregated); if ((lro_desc->pkt_aggr_cnt >= lro_mgr->max_aggr) || @@ -348,19 +438,161 @@ return 1; } +static struct sk_buff *lro_gen_skb(struct net_lro_mgr *lro_mgr, + struct skb_frag_struct *frags, + int len, int true_size, + void *mac_hdr, + int hlen, __wsum sum, + u32 ip_summed) +{ + struct sk_buff *skb; + struct skb_frag_struct *skb_frags; + int data_len = len; + int hdr_len = min(len, hlen); + + skb = netdev_alloc_skb(lro_mgr->dev, hlen + lro_mgr->frag_align_pad); + if (!skb) + return NULL; + + skb_reserve(skb, lro_mgr->frag_align_pad); + skb->len = len; + skb->data_len = len - hdr_len; + skb->truesize += true_size; + skb->tail += hdr_len; + + memcpy(skb->data, mac_hdr, hdr_len); + + skb_frags = skb_shinfo(skb)->frags; + while (data_len > 0) { + *skb_frags = *frags; + data_len -= skb_frag_size(frags); + skb_frags++; + frags++; + skb_shinfo(skb)->nr_frags++; + } + + skb_shinfo(skb)->frags[0].page_offset += hdr_len; + skb_frag_size_sub(&skb_shinfo(skb)->frags[0], hdr_len); + + skb->ip_summed = ip_summed; + skb->csum = sum; + skb->protocol = eth_type_trans(skb, lro_mgr->dev); + return skb; +} + +static struct sk_buff *__lro_proc_segment(struct net_lro_mgr *lro_mgr, + struct skb_frag_struct *frags, + int len, int true_size, + void *priv, __wsum sum) +{ + struct net_lro_desc *lro_desc; + struct iphdr *iph; + struct tcphdr *tcph; + struct sk_buff *skb; + u64 flags; + void *mac_hdr; + int mac_hdr_len; + int hdr_len = LRO_MAX_PG_HLEN; + int vlan_hdr_len = 0; + + if (!lro_mgr->get_frag_header || + lro_mgr->get_frag_header(frags, (void *)&mac_hdr, (void *)&iph, + (void *)&tcph, &flags, priv)) { + mac_hdr = skb_frag_address(frags); + goto out1; + } + + if (!(flags & LRO_IPV4) || !(flags & LRO_TCP)) + goto out1; + + hdr_len = (int)((void *)(tcph) + TCP_HDR_LEN(tcph) - mac_hdr); + mac_hdr_len = (int)((void *)(iph) - mac_hdr); + + lro_desc = lro_get_desc(lro_mgr, lro_mgr->lro_arr, iph, tcph); + if (!lro_desc) + goto out1; + + if (!lro_desc->active) { /* start new lro session */ + if (lro_tcp_ip_check(iph, tcph, len - mac_hdr_len, NULL)) + goto out1; + + skb = lro_gen_skb(lro_mgr, frags, len, true_size, mac_hdr, + hdr_len, 0, lro_mgr->ip_summed_aggr); + if (!skb) + goto out; + + if ((skb->protocol == htons(ETH_P_8021Q)) && + !(lro_mgr->features & LRO_F_EXTRACT_VLAN_ID)) + vlan_hdr_len = VLAN_HLEN; + + iph = (void *)(skb->data + vlan_hdr_len); + tcph = (void *)((u8 *)skb->data + vlan_hdr_len + + IP_HDR_LEN(iph)); + + lro_init_desc(lro_desc, skb, iph, tcph, NULL); + LRO_INC_STATS(lro_mgr, aggregated); + return NULL; + } + + if (lro_desc->tcp_next_seq != ntohl(tcph->seq)) + goto out2; + + if (lro_tcp_ip_check(iph, tcph, len - mac_hdr_len, lro_desc)) + goto out2; + + lro_add_frags(lro_desc, len, hdr_len, true_size, frags, iph, tcph); + LRO_INC_STATS(lro_mgr, aggregated); + + if ((skb_shinfo(lro_desc->parent)->nr_frags >= lro_mgr->max_aggr) || + lro_desc->parent->len > (0xFFFF - lro_mgr->dev->mtu)) + lro_flush(lro_mgr, lro_desc); + + return NULL; + +out2: /* send aggregated packets to the stack */ + lro_flush(lro_mgr, lro_desc); + +out1: /* Original packet has to be posted to the stack */ + skb = lro_gen_skb(lro_mgr, frags, len, true_size, mac_hdr, + hdr_len, sum, lro_mgr->ip_summed); +out: + return skb; +} + void lro_receive_skb(struct net_lro_mgr *lro_mgr, struct sk_buff *skb, void *priv) { - if (__lro_proc_skb(lro_mgr, skb, priv)) { + if (__lro_proc_skb(lro_mgr, skb, priv, NULL)) { if (lro_mgr->features & LRO_F_NAPI) netif_receive_skb(skb); + else if (lro_mgr->features & LRO_F_NI) + netif_rx_ni(skb); else netif_rx(skb); } } EXPORT_SYMBOL(lro_receive_skb); +void lro_receive_frags(struct net_lro_mgr *lro_mgr, + struct skb_frag_struct *frags, + int len, int true_size, void *priv, __wsum sum) +{ + struct sk_buff *skb; + + skb = __lro_proc_segment(lro_mgr, frags, len, true_size, priv, sum); + if (!skb) + return; + + if (lro_mgr->features & LRO_F_NAPI) + netif_receive_skb(skb); + else if (lro_mgr->features & LRO_F_NI) + netif_rx_ni(skb); + else + netif_rx(skb); +} +EXPORT_SYMBOL(lro_receive_frags); + void lro_flush_all(struct net_lro_mgr *lro_mgr) { int i; @@ -372,3 +604,35 @@ } } EXPORT_SYMBOL(lro_flush_all); + +void lro_flush_pkt(struct net_lro_mgr *lro_mgr, struct iphdr *iph, + struct tcphdr *tcph) +{ + struct net_lro_desc *lro_desc; + + lro_desc = lro_get_desc(lro_mgr, lro_mgr->lro_arr, iph, tcph); + if (lro_desc && lro_desc->active) + lro_flush(lro_mgr, lro_desc); +} +EXPORT_SYMBOL(lro_flush_pkt); + +void lro_flush_desc(struct net_lro_mgr *lro_mgr, struct net_lro_desc *lro_desc) +{ + if (lro_desc->active) + lro_flush(lro_mgr, lro_desc); +} +EXPORT_SYMBOL(lro_flush_desc); + +void lro_receive_skb_ext(struct net_lro_mgr *lro_mgr, struct sk_buff *skb, + void *priv, struct net_lro_info *lro_info) +{ + if (__lro_proc_skb(lro_mgr, skb, priv, lro_info)) { + if (lro_mgr->features & LRO_F_NAPI) + netif_receive_skb(skb); + else if (lro_mgr->features & LRO_F_NI) + netif_rx_ni(skb); + else + netif_rx(skb); + } +} +EXPORT_SYMBOL(lro_receive_skb_ext); diff -ruw linux-4.4.115/net/ipv4/ipconfig.c linux-4.4.115-fbx/net/ipv4/ipconfig.c --- linux-4.4.115/net/ipv4/ipconfig.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/net/ipv4/ipconfig.c 2019-10-29 09:26:25.837224649 +0100 @@ -193,15 +193,61 @@ static struct ic_device *ic_first_dev __initdata; /* List of open device */ static struct net_device *ic_dev __initdata; /* Selected device */ -static bool __init ic_is_init_dev(struct net_device *dev) +static bool __init ic_is_init_dev(struct net_device *dev, bool partial) { + char *p = NULL; + bool ret; + if (dev->flags & IFF_LOOPBACK) return false; - return user_dev_name[0] ? !strcmp(dev->name, user_dev_name) : + + if (partial) { + p = strchr(user_dev_name, '.'); + if (p) + *p = 0; + } + + ret = false; + if (user_dev_name[0] ? !strcmp(dev->name, user_dev_name) : (!(dev->flags & IFF_LOOPBACK) && (dev->flags & (IFF_POINTOPOINT|IFF_BROADCAST)) && - strncmp(dev->name, "dummy", 5)); + strncmp(dev->name, "dummy", 5))) + ret = true; + if (p) + *p = '.'; + return ret; +} + +#ifdef CONFIG_VLAN_8021Q +int register_vlan_device(struct net_device *real_dev, u16 vlan_id); + +static void __init prepare_vlan(void) +{ + unsigned short oflags; + struct net_device *dev; + char *p; + u16 vid; + + if (!strchr(user_dev_name, '.')) + return; + + p = strchr(user_dev_name, '.'); + *p = 0; + vid = simple_strtoul(p + 1, NULL, 10); + dev = __dev_get_by_name(&init_net, user_dev_name); + if (!dev) + goto fail; + + oflags = dev->flags; + if (dev_change_flags(dev, oflags | IFF_UP) < 0) + goto fail; + + register_vlan_device(dev, vid); + +fail: + *p = '.'; } +#endif static int __init ic_open_devs(void) { @@ -221,8 +267,13 @@ pr_err("IP-Config: Failed to open %s\n", dev->name); } +#ifdef CONFIG_VLAN_8021Q + /* register vlan device if needed */ + prepare_vlan(); +#endif + for_each_netdev(&init_net, dev) { - if (ic_is_init_dev(dev)) { + if (ic_is_init_dev(dev, false)) { int able = 0; if (dev->mtu >= 364) able |= IC_BOOTP; @@ -271,10 +322,12 @@ int wait, elapsed; for_each_netdev(&init_net, dev) - if (ic_is_init_dev(dev) && netif_carrier_ok(dev)) + if (ic_is_init_dev(dev, false) && netif_carrier_ok(dev)) goto have_carrier; + rtnl_unlock(); msleep(1); + rtnl_lock(); if (time_before(jiffies, next_msg)) continue; @@ -1393,7 +1446,7 @@ rtnl_lock(); for_each_netdev(&init_net, dev) { - if (ic_is_init_dev(dev)) { + if (ic_is_init_dev(dev, true)) { found = 1; break; } diff -ruw linux-4.4.115/net/ipv4/ip_output.c linux-4.4.115-fbx/net/ipv4/ip_output.c --- linux-4.4.115/net/ipv4/ip_output.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/net/ipv4/ip_output.c 2019-10-29 09:26:25.833224610 +0100 @@ -926,7 +926,7 @@ (((length + (skb ? skb->len : fragheaderlen)) > mtu) && (skb_queue_len(queue) <= 1) && (sk->sk_protocol == IPPROTO_UDP) && - (rt->dst.dev->features & NETIF_F_UFO) && !rt->dst.header_len && + (rt->dst.dev->features & NETIF_F_UFO) && !dst_xfrm(&rt->dst) && (sk->sk_type == SOCK_DGRAM) && !sk->sk_no_check_tx)) { err = ip_ufo_append_data(sk, queue, getfrag, from, length, hh_len, fragheaderlen, transhdrlen, @@ -1583,7 +1583,8 @@ RT_SCOPE_UNIVERSE, ip_hdr(skb)->protocol, ip_reply_arg_flowi_flags(arg), daddr, saddr, - tcp_hdr(skb)->source, tcp_hdr(skb)->dest); + tcp_hdr(skb)->source, tcp_hdr(skb)->dest, + arg->uid); security_skb_classify_flow(skb, flowi4_to_flowi(&fl4)); rt = ip_route_output_key(net, &fl4); if (IS_ERR(rt)) diff -ruw linux-4.4.115/net/ipv4/Kconfig linux-4.4.115-fbx/net/ipv4/Kconfig --- linux-4.4.115/net/ipv4/Kconfig 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/net/ipv4/Kconfig 2019-10-29 09:26:25.821224492 +0100 @@ -436,6 +436,19 @@ Support for UDP socket monitoring interface used by the ss tool. If unsure, say Y. +config INET_DIAG_DESTROY + bool "INET: allow privileged process to administratively close sockets" + depends on INET_DIAG + default n + ---help--- + Provides a SOCK_DESTROY operation that allows privileged processes + (e.g., a connection manager or a network administration tool such as + ss) to close sockets opened by other processes. Closing a socket in + this way interrupts any blocking read/write/connect operations on + the socket and causes future socket calls to behave as if the socket + had been disconnected. + If unsure, say N. + menuconfig TCP_CONG_ADVANCED bool "TCP: advanced congestion control" ---help--- diff -ruw linux-4.4.115/net/ipv4/Makefile linux-4.4.115-fbx/net/ipv4/Makefile --- linux-4.4.115/net/ipv4/Makefile 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/net/ipv4/Makefile 2019-01-22 16:16:28.947295705 +0100 @@ -16,6 +16,7 @@ obj-$(CONFIG_NET_IP_TUNNEL) += ip_tunnel.o obj-$(CONFIG_SYSCTL) += sysctl_net_ipv4.o +obj-$(CONFIG_SYSFS) += sysfs_net_ipv4.o obj-$(CONFIG_PROC_FS) += proc.o obj-$(CONFIG_IP_MULTIPLE_TABLES) += fib_rules.o obj-$(CONFIG_IP_MROUTE) += ipmr.o diff -ruw linux-4.4.115/net/ipv4/netfilter/ip_tables.c linux-4.4.115-fbx/net/ipv4/netfilter/ip_tables.c --- linux-4.4.115/net/ipv4/netfilter/ip_tables.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/net/ipv4/netfilter/ip_tables.c 2019-10-29 09:26:25.841224688 +0100 @@ -408,9 +408,11 @@ } if (table_base + v != ipt_next_entry(e) && !(e->ip.flags & IPT_F_GOTO)) { + if (unlikely(stackidx >= private->stacksize)) { + verdict = NF_DROP; + break; + } jumpstack[stackidx++] = e; - pr_debug("Pushed %p into pos %u\n", - e, stackidx - 1); } e = get_entry(table_base, v); diff -ruw linux-4.4.115/net/ipv4/netfilter/nf_defrag_ipv4.c linux-4.4.115-fbx/net/ipv4/netfilter/nf_defrag_ipv4.c --- linux-4.4.115/net/ipv4/netfilter/nf_defrag_ipv4.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/net/ipv4/netfilter/nf_defrag_ipv4.c 2019-01-22 16:16:28.975295959 +0100 @@ -11,6 +11,7 @@ #include #include #include +#include #include #include @@ -80,8 +81,13 @@ #endif /* Gather fragments. */ if (ip_is_fragment(ip_hdr(skb))) { - enum ip_defrag_users user = - nf_ct_defrag_user(state->hook, skb); + enum ip_defrag_users user; + + if (skb->dev && + IN_DEV_NF_IPV4_DEFRAG_SKIP(__in_dev_get_rcu(skb->dev))) + return NF_ACCEPT; + + user = nf_ct_defrag_user(state->hook, skb); if (nf_ct_ipv4_gather_frags(state->net, skb, user)) return NF_STOLEN; diff -ruw linux-4.4.115/net/ipv4/ping.c linux-4.4.115-fbx/net/ipv4/ping.c --- linux-4.4.115/net/ipv4/ping.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/net/ipv4/ping.c 2019-10-29 09:26:25.841224688 +0100 @@ -660,7 +660,7 @@ void *user_icmph, size_t icmph_len) { u8 type, code; - if (len > 0xFFFF) + if (len > 0xFFFF || len < icmph_len) return -EMSGSIZE; /* Must have at least a full ICMP header. */ @@ -798,7 +798,8 @@ flowi4_init_output(&fl4, ipc.oif, sk->sk_mark, tos, RT_SCOPE_UNIVERSE, sk->sk_protocol, - inet_sk_flowi_flags(sk), faddr, saddr, 0, 0); + inet_sk_flowi_flags(sk), faddr, saddr, 0, 0, + sk->sk_uid); security_sk_classify_flow(sk, flowi4_to_flowi(&fl4)); rt = ip_route_output_flow(net, &fl4, sk); diff -ruw linux-4.4.115/net/ipv4/raw.c linux-4.4.115-fbx/net/ipv4/raw.c --- linux-4.4.115/net/ipv4/raw.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/net/ipv4/raw.c 2019-10-29 09:26:25.845224727 +0100 @@ -609,7 +609,7 @@ hdrincl ? IPPROTO_RAW : sk->sk_protocol, inet_sk_flowi_flags(sk) | (hdrincl ? FLOWI_FLAG_KNOWN_NH : 0), - daddr, saddr, 0, 0); + daddr, saddr, 0, 0, sk->sk_uid); if (!saddr && ipc.oif) { err = l3mdev_get_saddr(net, ipc.oif, &fl4); diff -ruw linux-4.4.115/net/ipv4/route.c linux-4.4.115-fbx/net/ipv4/route.c --- linux-4.4.115/net/ipv4/route.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/net/ipv4/route.c 2019-10-29 09:26:25.845224727 +0100 @@ -501,7 +501,8 @@ } EXPORT_SYMBOL(__ip_select_ident); -static void __build_flow_key(struct flowi4 *fl4, const struct sock *sk, +static void __build_flow_key(const struct net *net, struct flowi4 *fl4, + const struct sock *sk, const struct iphdr *iph, int oif, u8 tos, u8 prot, u32 mark, int flow_flags) @@ -517,19 +518,21 @@ flowi4_init_output(fl4, oif, mark, tos, RT_SCOPE_UNIVERSE, prot, flow_flags, - iph->daddr, iph->saddr, 0, 0); + iph->daddr, iph->saddr, 0, 0, + sock_net_uid(net, sk)); } static void build_skb_flow_key(struct flowi4 *fl4, const struct sk_buff *skb, const struct sock *sk) { + const struct net *net = dev_net(skb->dev); const struct iphdr *iph = ip_hdr(skb); int oif = skb->dev->ifindex; u8 tos = RT_TOS(iph->tos); u8 prot = iph->protocol; u32 mark = skb->mark; - __build_flow_key(fl4, sk, iph, oif, tos, prot, mark, 0); + __build_flow_key(net, fl4, sk, iph, oif, tos, prot, mark, 0); } static void build_sk_flow_key(struct flowi4 *fl4, const struct sock *sk) @@ -546,7 +549,7 @@ RT_CONN_FLAGS(sk), RT_SCOPE_UNIVERSE, inet->hdrincl ? IPPROTO_RAW : sk->sk_protocol, inet_sk_flowi_flags(sk), - daddr, inet->inet_saddr, 0, 0); + daddr, inet->inet_saddr, 0, 0, sk->sk_uid); rcu_read_unlock(); } @@ -793,6 +796,7 @@ struct rtable *rt; struct flowi4 fl4; const struct iphdr *iph = (const struct iphdr *) skb->data; + struct net *net = dev_net(skb->dev); int oif = skb->dev->ifindex; u8 tos = RT_TOS(iph->tos); u8 prot = iph->protocol; @@ -800,7 +804,7 @@ rt = (struct rtable *) dst; - __build_flow_key(&fl4, sk, iph, oif, tos, prot, mark, 0); + __build_flow_key(net, &fl4, sk, iph, oif, tos, prot, mark, 0); __ip_do_redirect(rt, skb, &fl4, true); } @@ -1018,7 +1022,7 @@ if (!mark) mark = IP4_REPLY_MARK(net, skb->mark); - __build_flow_key(&fl4, NULL, iph, oif, + __build_flow_key(net, &fl4, NULL, iph, oif, RT_TOS(iph->tos), protocol, mark, flow_flags); rt = __ip_route_output_key(net, &fl4); if (!IS_ERR(rt)) { @@ -1034,7 +1038,7 @@ struct flowi4 fl4; struct rtable *rt; - __build_flow_key(&fl4, sk, iph, 0, 0, 0, 0, 0); + __build_flow_key(sock_net(sk), &fl4, sk, iph, 0, 0, 0, 0, 0); if (!fl4.flowi4_mark) fl4.flowi4_mark = IP4_REPLY_MARK(sock_net(sk), skb->mark); @@ -1053,6 +1057,7 @@ struct rtable *rt; struct dst_entry *odst = NULL; bool new = false; + struct net *net = sock_net(sk); bh_lock_sock(sk); @@ -1066,7 +1071,7 @@ goto out; } - __build_flow_key(&fl4, sk, iph, 0, 0, 0, 0, 0); + __build_flow_key(net, &fl4, sk, iph, 0, 0, 0, 0, 0); rt = (struct rtable *)odst; if (odst->obsolete && !odst->ops->check(odst, 0)) { @@ -1106,7 +1111,7 @@ struct flowi4 fl4; struct rtable *rt; - __build_flow_key(&fl4, NULL, iph, oif, + __build_flow_key(net, &fl4, NULL, iph, oif, RT_TOS(iph->tos), protocol, mark, flow_flags); rt = __ip_route_output_key(net, &fl4); if (!IS_ERR(rt)) { @@ -1121,9 +1126,10 @@ const struct iphdr *iph = (const struct iphdr *) skb->data; struct flowi4 fl4; struct rtable *rt; + struct net *net = sock_net(sk); - __build_flow_key(&fl4, sk, iph, 0, 0, 0, 0, 0); - rt = __ip_route_output_key(sock_net(sk), &fl4); + __build_flow_key(net, &fl4, sk, iph, 0, 0, 0, 0, 0); + rt = __ip_route_output_key(net, &fl4); if (!IS_ERR(rt)) { __ip_do_redirect(rt, skb, &fl4, false); ip_rt_put(rt); @@ -2499,6 +2505,11 @@ nla_put_u32(skb, RTA_MARK, fl4->flowi4_mark)) goto nla_put_failure; + if (!uid_eq(fl4->flowi4_uid, INVALID_UID) && + nla_put_u32(skb, RTA_UID, + from_kuid_munged(current_user_ns(), fl4->flowi4_uid))) + goto nla_put_failure; + error = rt->dst.error; if (rt_is_input_route(rt)) { @@ -2551,6 +2562,7 @@ int mark; struct sk_buff *skb; u32 table_id = RT_TABLE_MAIN; + kuid_t uid; err = nlmsg_parse(nlh, sizeof(*rtm), tb, RTA_MAX, rtm_ipv4_policy); if (err < 0) @@ -2578,6 +2590,10 @@ dst = tb[RTA_DST] ? nla_get_in_addr(tb[RTA_DST]) : 0; iif = tb[RTA_IIF] ? nla_get_u32(tb[RTA_IIF]) : 0; mark = tb[RTA_MARK] ? nla_get_u32(tb[RTA_MARK]) : 0; + if (tb[RTA_UID]) + uid = make_kuid(current_user_ns(), nla_get_u32(tb[RTA_UID])); + else + uid = (iif ? INVALID_UID : current_uid()); memset(&fl4, 0, sizeof(fl4)); fl4.daddr = dst; @@ -2585,6 +2601,7 @@ fl4.flowi4_tos = rtm->rtm_tos; fl4.flowi4_oif = tb[RTA_OIF] ? nla_get_u32(tb[RTA_OIF]) : 0; fl4.flowi4_mark = mark; + fl4.flowi4_uid = uid; if (netif_index_is_l3_master(net, fl4.flowi4_oif)) fl4.flowi4_flags = FLOWI_FLAG_L3MDEV_SRC | FLOWI_FLAG_SKIP_NH_OIF; diff -ruw linux-4.4.115/net/ipv4/sysctl_net_ipv4.c linux-4.4.115-fbx/net/ipv4/sysctl_net_ipv4.c --- linux-4.4.115/net/ipv4/sysctl_net_ipv4.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/net/ipv4/sysctl_net_ipv4.c 2019-10-29 09:26:25.849224766 +0100 @@ -42,6 +42,10 @@ static int tcp_syn_retries_max = MAX_TCP_SYNCNT; static int ip_ping_group_range_min[] = { 0, 0 }; static int ip_ping_group_range_max[] = { GID_T_MAX, GID_T_MAX }; +static int tcp_delack_seg_min = TCP_DELACK_MIN; +static int tcp_delack_seg_max = 60; +static int tcp_use_userconfig_min; +static int tcp_use_userconfig_max = 1; /* Update system visible IP port range */ static void set_local_port_range(struct net *net, int range[2]) @@ -152,6 +156,21 @@ return ret; } +/* Validate changes from /proc interface. */ +static int proc_tcp_default_init_rwnd(struct ctl_table *ctl, int write, + void __user *buffer, + size_t *lenp, loff_t *ppos) +{ + int old_value = *(int *)ctl->data; + int ret = proc_dointvec(ctl, write, buffer, lenp, ppos); + int new_value = *(int *)ctl->data; + + if (write && ret == 0 && (new_value < 3 || new_value > 100)) + *(int *)ctl->data = old_value; + + return ret; +} + static int proc_tcp_congestion_control(struct ctl_table *ctl, int write, void __user *buffer, size_t *lenp, loff_t *ppos) { @@ -761,6 +780,13 @@ .proc_handler = proc_dointvec_ms_jiffies, }, { + .procname = "tcp_default_init_rwnd", + .data = &sysctl_tcp_default_init_rwnd, + .maxlen = sizeof(int), + .mode = 0644, + .proc_handler = proc_tcp_default_init_rwnd + }, + { .procname = "icmp_msgs_per_sec", .data = &sysctl_icmp_msgs_per_sec, .maxlen = sizeof(int), @@ -799,6 +825,25 @@ .proc_handler = proc_dointvec_minmax, .extra1 = &one }, + { + .procname = "tcp_delack_seg", + .data = &sysctl_tcp_delack_seg, + .maxlen = sizeof(sysctl_tcp_delack_seg), + .mode = 0644, + .proc_handler = tcp_proc_delayed_ack_control, + .extra1 = &tcp_delack_seg_min, + .extra2 = &tcp_delack_seg_max, + }, + { + .procname = "tcp_use_userconfig", + .data = &sysctl_tcp_use_userconfig, + .maxlen = sizeof(sysctl_tcp_use_userconfig), + .mode = 0644, + .proc_handler = tcp_use_userconfig_sysctl_handler, + .extra1 = &tcp_use_userconfig_min, + .extra2 = &tcp_use_userconfig_max, + }, + { } }; @@ -881,6 +926,13 @@ .proc_handler = proc_do_large_bitmap, }, { + .procname = "reserved_port_bind", + .data = &sysctl_reserved_port_bind, + .maxlen = sizeof(int), + .mode = 0644, + .proc_handler = proc_dointvec + }, + { .procname = "ip_no_pmtu_disc", .data = &init_net.ipv4.sysctl_ip_no_pmtu_disc, .maxlen = sizeof(int), diff -ruw linux-4.4.115/net/ipv4/tcp.c linux-4.4.115-fbx/net/ipv4/tcp.c --- linux-4.4.115/net/ipv4/tcp.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/net/ipv4/tcp.c 2019-10-29 09:26:25.849224766 +0100 @@ -302,6 +302,12 @@ atomic_long_t tcp_memory_allocated; /* Current allocated memory. */ EXPORT_SYMBOL(tcp_memory_allocated); +int sysctl_tcp_delack_seg __read_mostly = TCP_DELACK_SEG; +EXPORT_SYMBOL(sysctl_tcp_delack_seg); + +int sysctl_tcp_use_userconfig __read_mostly; +EXPORT_SYMBOL(sysctl_tcp_use_userconfig); + /* * Current number of TCP sockets. */ @@ -1407,8 +1413,11 @@ /* Delayed ACKs frequently hit locked sockets during bulk * receive. */ if (icsk->icsk_ack.blocked || - /* Once-per-two-segments ACK was not sent by tcp_input.c */ - tp->rcv_nxt - tp->rcv_wup > icsk->icsk_ack.rcv_mss || + /* Once-per-sysctl_tcp_delack_seg segments + * ACK was not sent by tcp_input.c + */ + tp->rcv_nxt - tp->rcv_wup > (icsk->icsk_ack.rcv_mss) * + sysctl_tcp_delack_seg || /* * If this read emptied read buffer, we send ACK, if * connection is not bidirectional, user drained @@ -2425,6 +2434,13 @@ } break; + case TCP_LINEAR_RTO: + if (val < 0 || val > 1) + err = -EINVAL; + else + tp->linear_rto = val; + break; + case TCP_REPAIR: if (!tcp_can_repair_sock(sk)) err = -EPERM; @@ -2730,6 +2746,14 @@ rate64 = rate != ~0U ? rate : ~0ULL; put_unaligned(rate64, &info->tcpi_max_pacing_rate); + /* Expose reference count for socket */ + if (sk->sk_socket) { + struct file *filep = sk->sk_socket->file; + + if (filep) + info->tcpi_count = file_count(filep); + } + do { start = u64_stats_fetch_begin_irq(&tp->syncp); put_unaligned(tp->bytes_acked, &info->tcpi_bytes_acked); @@ -2848,6 +2872,9 @@ case TCP_THIN_DUPACK: val = tp->thin_dupack; break; + case TCP_LINEAR_RTO: + val = tp->linear_rto; + break; case TCP_REPAIR: val = tp->repair; @@ -3103,6 +3130,52 @@ } EXPORT_SYMBOL_GPL(tcp_done); +int tcp_abort(struct sock *sk, int err) +{ + if (!sk_fullsock(sk)) { + if (sk->sk_state == TCP_NEW_SYN_RECV) { + struct request_sock *req = inet_reqsk(sk); + + local_bh_disable(); + inet_csk_reqsk_queue_drop_and_put(req->rsk_listener, + req); + local_bh_enable(); + return 0; + } + sock_gen_put(sk); + return -EOPNOTSUPP; + } + + /* Don't race with userspace socket closes such as tcp_close. */ + lock_sock(sk); + + if (sk->sk_state == TCP_LISTEN) { + tcp_set_state(sk, TCP_CLOSE); + inet_csk_listen_stop(sk); + } + + /* Don't race with BH socket closes such as inet_csk_listen_stop. */ + local_bh_disable(); + bh_lock_sock(sk); + + if (!sock_flag(sk, SOCK_DEAD)) { + sk->sk_err = err; + /* This barrier is coupled with smp_rmb() in tcp_poll() */ + smp_wmb(); + sk->sk_error_report(sk); + if (tcp_need_reset(sk->sk_state)) + tcp_send_active_reset(sk, GFP_ATOMIC); + tcp_done(sk); + } + + bh_unlock_sock(sk); + local_bh_enable(); + release_sock(sk); + sock_put(sk); + return 0; +} +EXPORT_SYMBOL_GPL(tcp_abort); + extern struct tcp_congestion_ops tcp_reno; static __initdata unsigned long thash_entries; diff -ruw linux-4.4.115/net/ipv4/tcp_input.c linux-4.4.115-fbx/net/ipv4/tcp_input.c --- linux-4.4.115/net/ipv4/tcp_input.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/net/ipv4/tcp_input.c 2019-10-29 09:26:25.857224845 +0100 @@ -102,6 +102,7 @@ int sysctl_tcp_moderate_rcvbuf __read_mostly = 1; int sysctl_tcp_early_retrans __read_mostly = 3; int sysctl_tcp_invalid_ratelimit __read_mostly = HZ/2; +int sysctl_tcp_default_init_rwnd __read_mostly = TCP_INIT_CWND * 2; #define FLAG_DATA 0x01 /* Incoming frame contained data. */ #define FLAG_WIN_UPDATE 0x02 /* Incoming ACK was a window update. */ @@ -4963,7 +4964,8 @@ struct tcp_sock *tp = tcp_sk(sk); /* More than one full frame received... */ - if (((tp->rcv_nxt - tp->rcv_wup) > inet_csk(sk)->icsk_ack.rcv_mss && + if (((tp->rcv_nxt - tp->rcv_wup) > (inet_csk(sk)->icsk_ack.rcv_mss) * + sysctl_tcp_delack_seg && /* ... and right edge of window advances far enough. * (tcp_recvmsg() will send ACK otherwise). Or... */ diff -ruw linux-4.4.115/net/ipv4/tcp_ipv4.c linux-4.4.115-fbx/net/ipv4/tcp_ipv4.c --- linux-4.4.115/net/ipv4/tcp_ipv4.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/net/ipv4/tcp_ipv4.c 2019-10-29 09:26:25.861224884 +0100 @@ -691,6 +691,7 @@ arg.bound_dev_if = sk->sk_bound_dev_if; arg.tos = ip_hdr(skb)->tos; + arg.uid = sock_net_uid(net, sk && sk_fullsock(sk) ? sk : NULL); ip_send_unicast_reply(*this_cpu_ptr(net->ipv4.tcp_sk), skb, &TCP_SKB_CB(skb)->header.h4.opt, ip_hdr(skb)->saddr, ip_hdr(skb)->daddr, @@ -712,7 +713,7 @@ outside socket context is ugly, certainly. What can I do? */ -static void tcp_v4_send_ack(struct net *net, +static void tcp_v4_send_ack(const struct sock *sk, struct sk_buff *skb, u32 seq, u32 ack, u32 win, u32 tsval, u32 tsecr, int oif, struct tcp_md5sig_key *key, @@ -727,6 +728,7 @@ #endif ]; } rep; + struct net *net = sock_net(sk); struct ip_reply_arg arg; memset(&rep.th, 0, sizeof(struct tcphdr)); @@ -776,6 +778,7 @@ if (oif) arg.bound_dev_if = oif; arg.tos = tos; + arg.uid = sock_net_uid(net, sk_fullsock(sk) ? sk : NULL); ip_send_unicast_reply(*this_cpu_ptr(net->ipv4.tcp_sk), skb, &TCP_SKB_CB(skb)->header.h4.opt, ip_hdr(skb)->saddr, ip_hdr(skb)->daddr, @@ -789,7 +792,7 @@ struct inet_timewait_sock *tw = inet_twsk(sk); struct tcp_timewait_sock *tcptw = tcp_twsk(sk); - tcp_v4_send_ack(sock_net(sk), skb, + tcp_v4_send_ack(sk, skb, tcptw->tw_snd_nxt, tcptw->tw_rcv_nxt, tcptw->tw_rcv_wnd >> tw->tw_rcv_wscale, tcp_time_stamp + tcptw->tw_ts_offset, @@ -817,7 +820,7 @@ * exception of segments, MUST be right-shifted by * Rcv.Wind.Shift bits: */ - tcp_v4_send_ack(sock_net(sk), skb, seq, + tcp_v4_send_ack(sk, skb, seq, tcp_rsk(req)->rcv_nxt, req->rsk_rcv_wnd >> inet_rsk(req)->rcv_wscale, tcp_time_stamp, @@ -846,7 +849,8 @@ struct sk_buff *skb; /* First, grab a route. */ - if (!dst && (dst = inet_csk_route_req(sk, &fl4, req)) == NULL) + if (!dst && (dst = inet_csk_route_req( + (struct sock *)sk, &fl4, req)) == NULL) return -1; skb = tcp_make_synack(sk, dst, req, foc, attach_req); @@ -1205,7 +1209,8 @@ const struct request_sock *req, bool *strict) { - struct dst_entry *dst = inet_csk_route_req(sk, &fl->u.ip4, req); + struct dst_entry *dst = inet_csk_route_req( + (struct sock *)sk, &fl->u.ip4, req); if (strict) { if (fl->u.ip4.daddr == inet_rsk(req)->ir_rmt_addr) @@ -1583,6 +1588,12 @@ if (!pskb_may_pull(skb, th->doff * 4)) goto discard_it; + /* Assuming a trustworthy entity did the checksum and found the csum + * invalid, drop the packet. + */ + if (skb->ip_summed == CHECKSUM_COMPLETE && skb->csum_valid == 0) + goto csum_error; + /* An explanation is required here, I think. * Packet length and doff are validated by header prediction, * provided case of th->doff==0 is eliminated. @@ -2195,6 +2206,7 @@ __be32 src = inet->inet_rcv_saddr; __u16 destp = ntohs(inet->inet_dport); __u16 srcp = ntohs(inet->inet_sport); + __u8 seq_state = sk->sk_state; int rx_queue; int state; @@ -2214,6 +2226,9 @@ timer_expires = jiffies; } + if (inet->transparent) + seq_state |= 0x80; + state = sk_state_load(sk); if (state == TCP_LISTEN) rx_queue = sk->sk_ack_backlog; @@ -2225,7 +2240,7 @@ seq_printf(f, "%4d: %08X:%04X %08X:%04X %02X %08X:%08X %02X:%08lX " "%08X %5u %8d %lu %d %pK %lu %lu %u %u %d", - i, src, srcp, dest, destp, state, + i, src, srcp, dest, destp, seq_state, tp->write_seq - tp->snd_una, rx_queue, timer_active, @@ -2379,6 +2394,7 @@ .destroy_cgroup = tcp_destroy_cgroup, .proto_cgroup = tcp_proto_cgroup, #endif + .diag_destroy = tcp_abort, }; EXPORT_SYMBOL(tcp_prot); diff -ruw linux-4.4.115/net/ipv4/tcp_output.c linux-4.4.115-fbx/net/ipv4/tcp_output.c --- linux-4.4.115/net/ipv4/tcp_output.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/net/ipv4/tcp_output.c 2019-10-29 09:26:25.861224884 +0100 @@ -191,7 +191,7 @@ * (RFC 3517, Section 4, NextSeg() rule (2)). Further place a * limit when mss is larger than 1460. */ - u32 init_rwnd = TCP_INIT_CWND * 2; + u32 init_rwnd = sysctl_tcp_default_init_rwnd; if (mss > 1460) init_rwnd = max((1460 * init_rwnd) / mss, 2U); diff -ruw linux-4.4.115/net/ipv4/tcp_timer.c linux-4.4.115-fbx/net/ipv4/tcp_timer.c --- linux-4.4.115/net/ipv4/tcp_timer.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/net/ipv4/tcp_timer.c 2019-10-29 09:26:25.865224923 +0100 @@ -32,6 +32,40 @@ int sysctl_tcp_orphan_retries __read_mostly; int sysctl_tcp_thin_linear_timeouts __read_mostly; +/*Function to reset tcp_ack related sysctl on resetting master control */ +void set_tcp_default(void) +{ + sysctl_tcp_delack_seg = TCP_DELACK_SEG; +} + +/*sysctl handler for tcp_ack realted master control */ +int tcp_proc_delayed_ack_control(struct ctl_table *table, int write, + void __user *buffer, size_t *length, + loff_t *ppos) +{ + int ret = proc_dointvec_minmax(table, write, buffer, length, ppos); + + /* The ret value will be 0 if the input validation is successful + * and the values are written to sysctl table. If not, the stack + * will continue to work with currently configured values + */ + return ret; +} + +/*sysctl handler for tcp_ack realted master control */ +int tcp_use_userconfig_sysctl_handler(struct ctl_table *table, int write, + void __user *buffer, size_t *length, + loff_t *ppos) +{ + int ret = proc_dointvec_minmax(table, write, buffer, length, ppos); + + if (write && ret == 0) { + if (!sysctl_tcp_use_userconfig) + set_tcp_default(); + } + return ret; +} + static void tcp_write_err(struct sock *sk) { sk->sk_err = sk->sk_err_soft ? : ETIMEDOUT; @@ -504,6 +538,10 @@ icsk->icsk_retransmits <= TCP_THIN_LINEAR_RETRIES) { icsk->icsk_backoff = 0; icsk->icsk_rto = min(__tcp_set_rto(tp), TCP_RTO_MAX); + + } else if (sk->sk_state == TCP_ESTABLISHED && tp->linear_rto) { + icsk->icsk_backoff = 0; + icsk->icsk_rto = min(__tcp_set_rto(tp), TCP_RTO_MAX); } else { /* Use normal (exponential) backoff */ icsk->icsk_rto = min(icsk->icsk_rto << 1, TCP_RTO_MAX); diff -ruw linux-4.4.115/net/ipv4/udp.c linux-4.4.115-fbx/net/ipv4/udp.c --- linux-4.4.115/net/ipv4/udp.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/net/ipv4/udp.c 2019-10-29 09:26:25.865224923 +0100 @@ -257,6 +257,11 @@ } else { hslot = udp_hashslot(udptable, net, snum); spin_lock_bh(&hslot->lock); + + if (inet_is_local_reserved_port(net, snum) && + !sysctl_reserved_port_bind) + goto fail_unlock; + if (hslot->count > 10) { int exist; unsigned int slot2 = udp_sk(sk)->udp_portaddr_hash ^ snum; @@ -1025,7 +1030,8 @@ flowi4_init_output(fl4, ipc.oif, sk->sk_mark, tos, RT_SCOPE_UNIVERSE, sk->sk_protocol, flow_flags, - faddr, saddr, dport, inet->inet_sport); + faddr, saddr, dport, inet->inet_sport, + sk->sk_uid); if (!saddr && ipc.oif) { err = l3mdev_get_saddr(net, ipc.oif, fl4); @@ -2264,6 +2270,20 @@ } EXPORT_SYMBOL(udp_poll); +int udp_abort(struct sock *sk, int err) +{ + lock_sock(sk); + + sk->sk_err = err; + sk->sk_error_report(sk); + udp_disconnect(sk, 0); + + release_sock(sk); + + return 0; +} +EXPORT_SYMBOL_GPL(udp_abort); + struct proto udp_prot = { .name = "UDP", .owner = THIS_MODULE, @@ -2295,6 +2315,7 @@ .compat_getsockopt = compat_udp_getsockopt, #endif .clear_sk = sk_prot_clear_portaddr_nulls, + .diag_destroy = udp_abort, }; EXPORT_SYMBOL(udp_prot); @@ -2432,14 +2453,20 @@ int bucket) { struct inet_sock *inet = inet_sk(sp); + struct udp_sock *up = udp_sk(sp); __be32 dest = inet->inet_daddr; __be32 src = inet->inet_rcv_saddr; __u16 destp = ntohs(inet->inet_dport); __u16 srcp = ntohs(inet->inet_sport); + __u8 state = sp->sk_state; + if (up->encap_rcv) + state |= 0xF0; + else if (inet->transparent) + state |= 0x80; seq_printf(f, "%5d: %08X:%04X %08X:%04X" " %02X %08X:%08X %02X:%08lX %08X %5u %8d %lu %d %pK %d", - bucket, src, srcp, dest, destp, sp->sk_state, + bucket, src, srcp, dest, destp, state, sk_wmem_alloc_get(sp), sk_rmem_alloc_get(sp), 0, 0L, 0, diff -ruw linux-4.4.115/net/ipv4/xfrm4_policy.c linux-4.4.115-fbx/net/ipv4/xfrm4_policy.c --- linux-4.4.115/net/ipv4/xfrm4_policy.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/net/ipv4/xfrm4_policy.c 2019-10-29 09:26:25.869224962 +0100 @@ -22,14 +22,16 @@ static struct dst_entry *__xfrm4_dst_lookup(struct net *net, struct flowi4 *fl4, int tos, int oif, const xfrm_address_t *saddr, - const xfrm_address_t *daddr) + const xfrm_address_t *daddr, + u32 mark) { struct rtable *rt; memset(fl4, 0, sizeof(*fl4)); fl4->daddr = daddr->a4; fl4->flowi4_tos = tos; - fl4->flowi4_oif = oif; + fl4->flowi4_oif = l3mdev_master_ifindex_by_index(net, oif); + fl4->flowi4_mark = mark; if (saddr) fl4->saddr = saddr->a4; @@ -44,20 +46,22 @@ static struct dst_entry *xfrm4_dst_lookup(struct net *net, int tos, int oif, const xfrm_address_t *saddr, - const xfrm_address_t *daddr) + const xfrm_address_t *daddr, + u32 mark) { struct flowi4 fl4; - return __xfrm4_dst_lookup(net, &fl4, tos, oif, saddr, daddr); + return __xfrm4_dst_lookup(net, &fl4, tos, oif, saddr, daddr, mark); } static int xfrm4_get_saddr(struct net *net, int oif, - xfrm_address_t *saddr, xfrm_address_t *daddr) + xfrm_address_t *saddr, xfrm_address_t *daddr, + u32 mark) { struct dst_entry *dst; struct flowi4 fl4; - dst = __xfrm4_dst_lookup(net, &fl4, 0, oif, NULL, daddr); + dst = __xfrm4_dst_lookup(net, &fl4, 0, oif, NULL, daddr, mark); if (IS_ERR(dst)) return -EHOSTUNREACH; diff -ruw linux-4.4.115/net/ipv6/addrconf.c linux-4.4.115-fbx/net/ipv6/addrconf.c --- linux-4.4.115/net/ipv6/addrconf.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/net/ipv6/addrconf.c 2019-10-29 09:26:25.869224962 +0100 @@ -112,6 +112,27 @@ return (cstamp - INITIAL_JIFFIES) * 100UL / HZ; } +static inline s32 rfc3315_s14_backoff_init(s32 irt) +{ + /* multiply 'initial retransmission time' by 0.9 .. 1.1 */ + u64 tmp = (900000 + prandom_u32() % 200001) * (u64)irt; + do_div(tmp, 1000000); + return (s32)tmp; +} + +static inline s32 rfc3315_s14_backoff_update(s32 rt, s32 mrt) +{ + /* multiply 'retransmission timeout' by 1.9 .. 2.1 */ + u64 tmp = (1900000 + prandom_u32() % 200001) * (u64)rt; + do_div(tmp, 1000000); + if ((s32)tmp > mrt) { + /* multiply 'maximum retransmission time' by 0.9 .. 1.1 */ + tmp = (900000 + prandom_u32() % 200001) * (u64)mrt; + do_div(tmp, 1000000); + } + return (s32)tmp; +} + #ifdef CONFIG_SYSCTL static int addrconf_sysctl_register(struct inet6_dev *idev); static void addrconf_sysctl_unregister(struct inet6_dev *idev); @@ -187,6 +208,7 @@ .dad_transmits = 1, .rtr_solicits = MAX_RTR_SOLICITATIONS, .rtr_solicit_interval = RTR_SOLICITATION_INTERVAL, + .rtr_solicit_max_interval = RTR_SOLICITATION_MAX_INTERVAL, .rtr_solicit_delay = MAX_RTR_SOLICITATION_DELAY, .use_tempaddr = 0, .temp_valid_lft = TEMP_VALID_LIFETIME, @@ -202,9 +224,11 @@ .accept_ra_rtr_pref = 1, .rtr_probe_interval = 60 * HZ, #ifdef CONFIG_IPV6_ROUTE_INFO + .accept_ra_rt_info_min_plen = 0, .accept_ra_rt_info_max_plen = 0, #endif #endif + .accept_ra_rt_table = 0, .proxy_ndp = 0, .accept_source_route = 0, /* we do not accept RH0 by default. */ .disable_ipv6 = 0, @@ -216,6 +240,7 @@ }, .use_oif_addrs_only = 0, .ignore_routes_with_linkdown = 0, + .accept_ra_prefix_route = 1, }; static struct ipv6_devconf ipv6_devconf_dflt __read_mostly = { @@ -231,6 +256,7 @@ .dad_transmits = 1, .rtr_solicits = MAX_RTR_SOLICITATIONS, .rtr_solicit_interval = RTR_SOLICITATION_INTERVAL, + .rtr_solicit_max_interval = RTR_SOLICITATION_MAX_INTERVAL, .rtr_solicit_delay = MAX_RTR_SOLICITATION_DELAY, .use_tempaddr = 0, .temp_valid_lft = TEMP_VALID_LIFETIME, @@ -246,9 +272,11 @@ .accept_ra_rtr_pref = 1, .rtr_probe_interval = 60 * HZ, #ifdef CONFIG_IPV6_ROUTE_INFO + .accept_ra_rt_info_min_plen = 0, .accept_ra_rt_info_max_plen = 0, #endif #endif + .accept_ra_rt_table = 0, .proxy_ndp = 0, .accept_source_route = 0, /* we do not accept RH0 by default. */ .disable_ipv6 = 0, @@ -260,6 +288,7 @@ }, .use_oif_addrs_only = 0, .ignore_routes_with_linkdown = 0, + .accept_ra_prefix_route = 1, }; /* Check if a valid qdisc is available */ @@ -2054,6 +2083,16 @@ return addrconf_ifid_ieee1394(eui, dev); case ARPHRD_TUNNEL6: return addrconf_ifid_ip6tnl(eui, dev); + case ARPHRD_RAWIP: { + struct in6_addr lladdr; + + if (ipv6_get_lladdr(dev, &lladdr, IFA_F_TENTATIVE)) + get_random_bytes(eui, 8); + else + memcpy(eui, lladdr.s6_addr + 8, 8); + + return 0; + } } return -1; } @@ -2146,6 +2185,31 @@ __ipv6_regen_rndid(idev); } +u32 addrconf_rt_table(const struct net_device *dev, u32 default_table) { + /* Determines into what table to put autoconf PIO/RIO/default routes + * learned on this device. + * + * - If 0, use the same table for every device. This puts routes into + * one of RT_TABLE_{PREFIX,INFO,DFLT} depending on the type of route + * (but note that these three are currently all equal to + * RT6_TABLE_MAIN). + * - If > 0, use the specified table. + * - If < 0, put routes into table dev->ifindex + (-rt_table). + */ + struct inet6_dev *idev = in6_dev_get(dev); + u32 table; + int sysctl = idev->cnf.accept_ra_rt_table; + if (sysctl == 0) { + table = default_table; + } else if (sysctl > 0) { + table = (u32) sysctl; + } else { + table = (unsigned) dev->ifindex + (-sysctl); + } + in6_dev_put(idev); + return table; +} + /* * Add prefix route. */ @@ -2155,7 +2219,7 @@ unsigned long expires, u32 flags) { struct fib6_config cfg = { - .fc_table = l3mdev_fib_table(dev) ? : RT6_TABLE_PREFIX, + .fc_table = l3mdev_fib_table(dev) ? : addrconf_rt_table(dev, RT6_TABLE_PREFIX), .fc_metric = IP6_RT_PRIO_ADDRCONF, .fc_ifindex = dev->ifindex, .fc_expires = expires, @@ -2188,7 +2252,7 @@ struct fib6_node *fn; struct rt6_info *rt = NULL; struct fib6_table *table; - u32 tb_id = l3mdev_fib_table(dev) ? : RT6_TABLE_PREFIX; + u32 tb_id = l3mdev_fib_table(dev) ? : addrconf_rt_table(dev, RT6_TABLE_PREFIX); table = fib6_get_table(dev_net(dev), tb_id); if (!table) @@ -2411,9 +2475,12 @@ flags |= RTF_EXPIRES; expires = jiffies_to_clock_t(rt_expires); } - addrconf_prefix_route(&pinfo->prefix, pinfo->prefix_len, + if (dev->ip6_ptr->cnf.accept_ra_prefix_route) { + addrconf_prefix_route(&pinfo->prefix, + pinfo->prefix_len, dev, expires, flags); } + } ip6_rt_put(rt); } @@ -3076,7 +3143,9 @@ (dev->type != ARPHRD_IEEE802154) && (dev->type != ARPHRD_IEEE1394) && (dev->type != ARPHRD_TUNNEL6) && - (dev->type != ARPHRD_6LOWPAN)) { + (dev->type != ARPHRD_6LOWPAN) && + (dev->type != ARPHRD_RAWIP) && + (dev->type != ARPHRD_INFINIBAND)) { /* Alas, we support only Ethernet autoconfiguration. */ return; } @@ -3466,7 +3535,7 @@ if (idev->if_flags & IF_RA_RCVD) goto out; - if (idev->rs_probes++ < idev->cnf.rtr_solicits) { + if (idev->rs_probes++ < idev->cnf.rtr_solicits || idev->cnf.rtr_solicits < 0) { write_unlock(&idev->lock); if (!ipv6_get_lladdr(dev, &lladdr, IFA_F_TENTATIVE)) ndisc_send_rs(dev, &lladdr, @@ -3475,11 +3544,13 @@ goto put; write_lock(&idev->lock); + idev->rs_interval = rfc3315_s14_backoff_update( + idev->rs_interval, idev->cnf.rtr_solicit_max_interval); /* The wait after the last probe can be shorter */ addrconf_mod_rs_timer(idev, (idev->rs_probes == idev->cnf.rtr_solicits) ? idev->cnf.rtr_solicit_delay : - idev->cnf.rtr_solicit_interval); + idev->rs_interval); } else { /* * Note: we do not support deprecated "all on-link" @@ -3707,7 +3778,7 @@ send_mld = ifp->scope == IFA_LINK && ipv6_lonely_lladdr(ifp); send_rs = send_mld && ipv6_accept_ra(ifp->idev) && - ifp->idev->cnf.rtr_solicits > 0 && + ifp->idev->cnf.rtr_solicits != 0 && (dev->flags&IFF_LOOPBACK) == 0; read_unlock_bh(&ifp->idev->lock); @@ -3729,10 +3800,11 @@ write_lock_bh(&ifp->idev->lock); spin_lock(&ifp->lock); + ifp->idev->rs_interval = rfc3315_s14_backoff_init( + ifp->idev->cnf.rtr_solicit_interval); ifp->idev->rs_probes = 1; ifp->idev->if_flags |= IF_RS_SENT; - addrconf_mod_rs_timer(ifp->idev, - ifp->idev->cnf.rtr_solicit_interval); + addrconf_mod_rs_timer(ifp->idev, ifp->idev->rs_interval); spin_unlock(&ifp->lock); write_unlock_bh(&ifp->idev->lock); } @@ -4649,6 +4721,8 @@ array[DEVCONF_RTR_SOLICITS] = cnf->rtr_solicits; array[DEVCONF_RTR_SOLICIT_INTERVAL] = jiffies_to_msecs(cnf->rtr_solicit_interval); + array[DEVCONF_RTR_SOLICIT_MAX_INTERVAL] = + jiffies_to_msecs(cnf->rtr_solicit_max_interval); array[DEVCONF_RTR_SOLICIT_DELAY] = jiffies_to_msecs(cnf->rtr_solicit_delay); array[DEVCONF_FORCE_MLD_VERSION] = cnf->force_mld_version; @@ -4670,9 +4744,11 @@ array[DEVCONF_RTR_PROBE_INTERVAL] = jiffies_to_msecs(cnf->rtr_probe_interval); #ifdef CONFIG_IPV6_ROUTE_INFO + array[DEVCONF_ACCEPT_RA_RT_INFO_MIN_PLEN] = cnf->accept_ra_rt_info_min_plen; array[DEVCONF_ACCEPT_RA_RT_INFO_MAX_PLEN] = cnf->accept_ra_rt_info_max_plen; #endif #endif + array[DEVCONF_ACCEPT_RA_RT_TABLE] = cnf->accept_ra_rt_table; array[DEVCONF_PROXY_NDP] = cnf->proxy_ndp; array[DEVCONF_ACCEPT_SOURCE_ROUTE] = cnf->accept_source_route; #ifdef CONFIG_IPV6_OPTIMISTIC_DAD @@ -4856,7 +4932,7 @@ return -EINVAL; if (!ipv6_accept_ra(idev)) return -EINVAL; - if (idev->cnf.rtr_solicits <= 0) + if (idev->cnf.rtr_solicits == 0) return -EINVAL; write_lock_bh(&idev->lock); @@ -4881,8 +4957,10 @@ if (update_rs) { idev->if_flags |= IF_RS_SENT; + idev->rs_interval = rfc3315_s14_backoff_init( + idev->cnf.rtr_solicit_interval); idev->rs_probes = 1; - addrconf_mod_rs_timer(idev, idev->cnf.rtr_solicit_interval); + addrconf_mod_rs_timer(idev, idev->rs_interval); } /* Well, that's kinda nasty ... */ @@ -5520,6 +5598,13 @@ .proc_handler = proc_dointvec_jiffies, }, { + .procname = "router_solicitation_max_interval", + .data = &ipv6_devconf.rtr_solicit_max_interval, + .maxlen = sizeof(int), + .mode = 0644, + .proc_handler = proc_dointvec_jiffies, + }, + { .procname = "router_solicitation_delay", .data = &ipv6_devconf.rtr_solicit_delay, .maxlen = sizeof(int), @@ -5629,6 +5714,13 @@ }, #ifdef CONFIG_IPV6_ROUTE_INFO { + .procname = "accept_ra_rt_info_min_plen", + .data = &ipv6_devconf.accept_ra_rt_info_min_plen, + .maxlen = sizeof(int), + .mode = 0644, + .proc_handler = proc_dointvec, + }, + { .procname = "accept_ra_rt_info_max_plen", .data = &ipv6_devconf.accept_ra_rt_info_max_plen, .maxlen = sizeof(int), @@ -5638,6 +5730,13 @@ #endif #endif { + .procname = "accept_ra_rt_table", + .data = &ipv6_devconf.accept_ra_rt_table, + .maxlen = sizeof(int), + .mode = 0644, + .proc_handler = proc_dointvec, + }, + { .procname = "proxy_ndp", .data = &ipv6_devconf.proxy_ndp, .maxlen = sizeof(int), @@ -5726,6 +5825,13 @@ .maxlen = sizeof(int), .mode = 0644, .proc_handler = proc_dointvec, + }, + { + .procname = "accept_ra_prefix_route", + .data = &ipv6_devconf.accept_ra_prefix_route, + .maxlen = sizeof(int), + .mode = 0644, + .proc_handler = proc_dointvec, }, { .procname = "stable_secret", diff -ruw linux-4.4.115/net/ipv6/af_inet6.c linux-4.4.115-fbx/net/ipv6/af_inet6.c --- linux-4.4.115/net/ipv6/af_inet6.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/net/ipv6/af_inet6.c 2019-10-29 09:26:25.873225001 +0100 @@ -64,6 +64,20 @@ #include #include +#ifdef CONFIG_ANDROID_PARANOID_NETWORK +#include + +static inline int current_has_network(void) +{ + return in_egroup_p(AID_INET) || capable(CAP_NET_RAW); +} +#else +static inline int current_has_network(void) +{ + return 1; +} +#endif + MODULE_AUTHOR("Cast of dozens"); MODULE_DESCRIPTION("IPv6 protocol stack for Linux"); MODULE_LICENSE("GPL"); @@ -112,6 +126,9 @@ if (protocol < 0 || protocol >= IPPROTO_MAX) return -EINVAL; + if (!current_has_network()) + return -EACCES; + /* Look for the requested type/protocol pair. */ lookup_protocol: err = -ESOCKTNOSUPPORT; @@ -158,8 +175,7 @@ } err = -EPERM; - if (sock->type == SOCK_RAW && !kern && - !ns_capable(net->user_ns, CAP_NET_RAW)) + if (sock->type == SOCK_RAW && !kern && !capable(CAP_NET_RAW)) goto out_rcu_unlock; sock->ops = answer->ops; @@ -661,6 +677,7 @@ fl6.flowi6_mark = sk->sk_mark; fl6.fl6_dport = inet->inet_dport; fl6.fl6_sport = inet->inet_sport; + fl6.flowi6_uid = sk->sk_uid; security_sk_classify_flow(sk, flowi6_to_flowi(&fl6)); rcu_read_lock(); diff -ruw linux-4.4.115/net/ipv6/datagram.c linux-4.4.115-fbx/net/ipv6/datagram.c --- linux-4.4.115/net/ipv6/datagram.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/net/ipv6/datagram.c 2019-10-29 09:26:25.873225001 +0100 @@ -165,6 +165,7 @@ fl6.flowi6_mark = sk->sk_mark; fl6.fl6_dport = inet->inet_dport; fl6.fl6_sport = inet->inet_sport; + fl6.flowi6_uid = sk->sk_uid; if (!fl6.flowi6_oif) fl6.flowi6_oif = np->sticky_pktinfo.ipi6_ifindex; @@ -183,6 +184,11 @@ err = 0; if (IS_ERR(dst)) { err = PTR_ERR(dst); + /* Reset daddr and dport so that udp_v6_early_demux() + * fails to find this socket + */ + memset(&sk->sk_v6_daddr, 0, sizeof(sk->sk_v6_daddr)); + inet->inet_dport = 0; goto out; } @@ -967,9 +973,14 @@ __u16 srcp, __u16 destp, int bucket) { const struct in6_addr *dest, *src; + __u8 state = sp->sk_state; dest = &sp->sk_v6_daddr; src = &sp->sk_v6_rcv_saddr; + + if (inet_sk(sp) && inet_sk(sp)->transparent) + state |= 0x80; + seq_printf(seq, "%5d: %08X%08X%08X%08X:%04X %08X%08X%08X%08X:%04X " "%02X %08X:%08X %02X:%08lX %08X %5u %8d %lu %d %pK %d\n", @@ -978,7 +989,7 @@ src->s6_addr32[2], src->s6_addr32[3], srcp, dest->s6_addr32[0], dest->s6_addr32[1], dest->s6_addr32[2], dest->s6_addr32[3], destp, - sp->sk_state, + state, sk_wmem_alloc_get(sp), sk_rmem_alloc_get(sp), 0, 0L, 0, diff -ruw linux-4.4.115/net/ipv6/exthdrs_core.c linux-4.4.115-fbx/net/ipv6/exthdrs_core.c --- linux-4.4.115/net/ipv6/exthdrs_core.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/net/ipv6/exthdrs_core.c 2019-01-22 16:16:29.007296248 +0100 @@ -166,15 +166,15 @@ * to explore inner IPv6 header, eg. ICMPv6 error messages. * * If target header is found, its offset is set in *offset and return protocol - * number. Otherwise, return -1. + * number. Otherwise, return -ENOENT or -EBADMSG. * * If the first fragment doesn't contain the final protocol header or * NEXTHDR_NONE it is considered invalid. * * Note that non-1st fragment is special case that "the protocol number * of last header" is "next header" field in Fragment header. In this case, - * *offset is meaningless and fragment offset is stored in *fragoff if fragoff - * isn't NULL. + * *offset is meaningless. If fragoff is not NULL, the fragment offset is + * stored in *fragoff; if it is NULL, return -EINVAL. * * if flags is not NULL and it's a fragment, then the frag flag * IP6_FH_F_FRAG will be set. If it's an AH header, the @@ -253,9 +253,12 @@ if (target < 0 && ((!ipv6_ext_hdr(hp->nexthdr)) || hp->nexthdr == NEXTHDR_NONE)) { - if (fragoff) + if (fragoff) { *fragoff = _frag_off; return hp->nexthdr; + } else { + return -EINVAL; + } } if (!found) return -ENOENT; diff -ruw linux-4.4.115/net/ipv6/icmp.c linux-4.4.115-fbx/net/ipv6/icmp.c --- linux-4.4.115/net/ipv6/icmp.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/net/ipv6/icmp.c 2019-01-22 16:16:29.007296248 +0100 @@ -92,13 +92,14 @@ struct net *net = dev_net(skb->dev); if (type == ICMPV6_PKT_TOOBIG) - ip6_update_pmtu(skb, net, info, 0, 0); + ip6_update_pmtu(skb, net, info, 0, 0, sock_net_uid(net, NULL)); else if (type == NDISC_REDIRECT) - ip6_redirect(skb, net, skb->dev->ifindex, 0); + ip6_redirect(skb, net, skb->dev->ifindex, 0, + sock_net_uid(net, NULL)); if (!(type & ICMPV6_INFOMSG_MASK)) if (icmp6->icmp6_type == ICMPV6_ECHO_REQUEST) - ping_err(skb, offset, info); + ping_err(skb, offset, ntohl(info)); } static int icmpv6_rcv(struct sk_buff *skb); @@ -478,6 +479,7 @@ fl6.flowi6_oif = iif; fl6.fl6_icmp_type = type; fl6.fl6_icmp_code = code; + fl6.flowi6_uid = sock_net_uid(net, NULL); security_skb_classify_flow(skb, flowi6_to_flowi(&fl6)); sk = icmpv6_xmit_lock(net); @@ -585,6 +587,7 @@ fl6.flowi6_oif = l3mdev_fib_oif(skb->dev); fl6.fl6_icmp_type = ICMPV6_ECHO_REPLY; fl6.flowi6_mark = mark; + fl6.flowi6_uid = sock_net_uid(net, NULL); security_skb_classify_flow(skb, flowi6_to_flowi(&fl6)); sk = icmpv6_xmit_lock(net); diff -ruw linux-4.4.115/net/ipv6/inet6_connection_sock.c linux-4.4.115-fbx/net/ipv6/inet6_connection_sock.c --- linux-4.4.115/net/ipv6/inet6_connection_sock.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/net/ipv6/inet6_connection_sock.c 2019-01-22 16:16:29.007296248 +0100 @@ -86,6 +86,7 @@ fl6->flowi6_mark = ireq->ir_mark; fl6->fl6_dport = ireq->ir_rmt_port; fl6->fl6_sport = htons(ireq->ir_num); + fl6->flowi6_uid = sk->sk_uid; security_req_classify_flow(req, flowi6_to_flowi(fl6)); dst = ip6_dst_lookup_flow(sk, fl6, final_p); @@ -134,6 +135,7 @@ fl6->flowi6_mark = sk->sk_mark; fl6->fl6_sport = inet->inet_sport; fl6->fl6_dport = inet->inet_dport; + fl6->flowi6_uid = sk->sk_uid; security_sk_classify_flow(sk, flowi6_to_flowi(fl6)); rcu_read_lock(); diff -ruw linux-4.4.115/net/ipv6/ip6_fib.c linux-4.4.115-fbx/net/ipv6/ip6_fib.c --- linux-4.4.115/net/ipv6/ip6_fib.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/net/ipv6/ip6_fib.c 2019-01-22 16:16:29.011296285 +0100 @@ -909,6 +909,7 @@ fn->fn_flags |= RTN_RTINFO; } nsiblings = iter->rt6i_nsiblings; + iter->rt6i_node = NULL; fib6_purge_rt(iter, fn, info->nl_net); if (fn->rr_ptr == iter) fn->rr_ptr = NULL; @@ -923,6 +924,7 @@ break; if (rt6_qualify_for_ecmp(iter)) { *ins = iter->dst.rt6_next; + iter->rt6i_node = NULL; fib6_purge_rt(iter, fn, info->nl_net); if (fn->rr_ptr == iter) fn->rr_ptr = NULL; diff -ruw linux-4.4.115/net/ipv6/ip6_offload.c linux-4.4.115-fbx/net/ipv6/ip6_offload.c --- linux-4.4.115/net/ipv6/ip6_offload.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/net/ipv6/ip6_offload.c 2019-10-29 09:26:25.877225040 +0100 @@ -242,9 +242,6 @@ /* flush if Traffic Class fields are different */ NAPI_GRO_CB(p)->flush |= !!(first_word & htonl(0x0FF00000)); NAPI_GRO_CB(p)->flush |= flush; - - /* Clear flush_id, there's really no concept of ID in IPv6. */ - NAPI_GRO_CB(p)->flush_id = 0; } NAPI_GRO_CB(skb)->flush |= flush; diff -ruw linux-4.4.115/net/ipv6/ip6_output.c linux-4.4.115-fbx/net/ipv6/ip6_output.c --- linux-4.4.115/net/ipv6/ip6_output.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/net/ipv6/ip6_output.c 2019-10-29 09:26:25.877225040 +0100 @@ -1371,7 +1371,7 @@ (((length + (skb ? skb->len : headersize)) > mtu) && (skb_queue_len(queue) <= 1) && (sk->sk_protocol == IPPROTO_UDP) && - (rt->dst.dev->features & NETIF_F_UFO) && + (rt->dst.dev->features & NETIF_F_UFO) && !dst_xfrm(&rt->dst) && (sk->sk_type == SOCK_DGRAM) && !udp_get_no_check6_tx(sk))) { err = ip6_ufo_append_data(sk, queue, getfrag, from, length, hh_len, fragheaderlen, exthdrlen, diff -ruw linux-4.4.115/net/ipv6/ndisc.c linux-4.4.115-fbx/net/ipv6/ndisc.c --- linux-4.4.115/net/ipv6/ndisc.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/net/ipv6/ndisc.c 2019-10-29 09:26:25.881225079 +0100 @@ -1358,6 +1358,8 @@ if (ri->prefix_len == 0 && !in6_dev->cnf.accept_ra_defrtr) continue; + if (ri->prefix_len < in6_dev->cnf.accept_ra_rt_info_min_plen) + continue; if (ri->prefix_len > in6_dev->cnf.accept_ra_rt_info_max_plen) continue; rt6_route_rcv(skb->dev, (u8 *)p, (p->nd_opt_len) << 3, diff -ruw linux-4.4.115/net/ipv6/netfilter/ip6_tables.c linux-4.4.115-fbx/net/ipv6/netfilter/ip6_tables.c --- linux-4.4.115/net/ipv6/netfilter/ip6_tables.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/net/ipv6/netfilter/ip6_tables.c 2019-10-29 09:26:25.885225119 +0100 @@ -94,23 +94,27 @@ { unsigned long ret; const struct ipv6hdr *ipv6 = ipv6_hdr(skb); +#if IS_ENABLED(IP6_NF_IPTABLES_128) + const __uint128_t *ulm1 = (const __uint128_t *)&ip6info->smsk; + const __uint128_t *ulm2 = (const __uint128_t *)&ip6info->dmsk; +#endif #define FWINV(bool, invflg) ((bool) ^ !!(ip6info->invflags & (invflg))) - if (FWINV(ipv6_masked_addr_cmp(&ipv6->saddr, &ip6info->smsk, - &ip6info->src), IP6T_INV_SRCIP) || +#if IS_ENABLED(IP6_NF_IPTABLES_128) + if (*ulm1 || *ulm2) +#endif + { + if (FWINV(ipv6_masked_addr_cmp + (&ipv6->saddr, &ip6info->smsk, &ip6info->src), + IP6T_INV_SRCIP) || FWINV(ipv6_masked_addr_cmp(&ipv6->daddr, &ip6info->dmsk, - &ip6info->dst), IP6T_INV_DSTIP)) { + &ip6info->dst), + IP6T_INV_DSTIP)) { dprintf("Source or dest mismatch.\n"); -/* - dprintf("SRC: %u. Mask: %u. Target: %u.%s\n", ip->saddr, - ipinfo->smsk.s_addr, ipinfo->src.s_addr, - ipinfo->invflags & IP6T_INV_SRCIP ? " (INV)" : ""); - dprintf("DST: %u. Mask: %u. Target: %u.%s\n", ip->daddr, - ipinfo->dmsk.s_addr, ipinfo->dst.s_addr, - ipinfo->invflags & IP6T_INV_DSTIP ? " (INV)" : "");*/ return false; } + } ret = ifname_compare_aligned(indev, ip6info->iniface, ip6info->iniface_mask); @@ -425,6 +429,10 @@ } if (table_base + v != ip6t_next_entry(e) && !(e->ipv6.flags & IP6T_F_GOTO)) { + if (unlikely(stackidx >= private->stacksize)) { + verdict = NF_DROP; + break; + } jumpstack[stackidx++] = e; } diff -ruw linux-4.4.115/net/ipv6/netfilter/Kconfig linux-4.4.115-fbx/net/ipv6/netfilter/Kconfig --- linux-4.4.115/net/ipv6/netfilter/Kconfig 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/net/ipv6/netfilter/Kconfig 2019-01-22 16:16:29.019296357 +0100 @@ -135,6 +135,18 @@ if IP6_NF_IPTABLES +config IP6_NF_IPTABLES_128 + tristate "128 bit arithmetic for iptables matching" + depends on IP6_NF_IPTABLES + help + This enables 128 bit matching in ip6tables to help optimize cases + where there is no match required. ip6tables matching for ipv6 always + has a mask if an address is specified for match. Adding a check for + mask prior to that helps to improve performance as it avoids the + masked comparison. + + Note that this feature depends on the architecture. If unsure, say N. + # The simple matches. config IP6_NF_MATCH_AH tristate '"ah" match support' diff -ruw linux-4.4.115/net/ipv6/netfilter.c linux-4.4.115-fbx/net/ipv6/netfilter.c --- linux-4.4.115/net/ipv6/netfilter.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/net/ipv6/netfilter.c 2019-01-22 16:16:29.019296357 +0100 @@ -26,6 +26,7 @@ struct flowi6 fl6 = { .flowi6_oif = skb->sk ? skb->sk->sk_bound_dev_if : 0, .flowi6_mark = skb->mark, + .flowi6_uid = sock_net_uid(net, skb->sk), .daddr = iph->daddr, .saddr = iph->saddr, }; diff -ruw linux-4.4.115/net/ipv6/ping.c linux-4.4.115-fbx/net/ipv6/ping.c --- linux-4.4.115/net/ipv6/ping.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/net/ipv6/ping.c 2019-10-29 09:26:25.885225119 +0100 @@ -84,7 +84,7 @@ struct icmp6hdr user_icmph; int addr_type; struct in6_addr *daddr; - int iif = 0; + int oif = 0; struct flowi6 fl6; int err; int hlimit; @@ -106,25 +106,30 @@ if (u->sin6_family != AF_INET6) { return -EAFNOSUPPORT; } - if (sk->sk_bound_dev_if && - sk->sk_bound_dev_if != u->sin6_scope_id) { - return -EINVAL; - } daddr = &(u->sin6_addr); - iif = u->sin6_scope_id; + if (__ipv6_addr_needs_scope_id(ipv6_addr_type(daddr))) + oif = u->sin6_scope_id; } else { if (sk->sk_state != TCP_ESTABLISHED) return -EDESTADDRREQ; daddr = &sk->sk_v6_daddr; } - if (!iif) - iif = sk->sk_bound_dev_if; + if (!oif) + oif = sk->sk_bound_dev_if; + + if (!oif) + oif = np->sticky_pktinfo.ipi6_ifindex; + + if (!oif && ipv6_addr_is_multicast(daddr)) + oif = np->mcast_oif; + else if (!oif) + oif = np->ucast_oif; addr_type = ipv6_addr_type(daddr); - if (__ipv6_addr_needs_scope_id(addr_type) && !iif) - return -EINVAL; - if (addr_type & IPV6_ADDR_MAPPED) + if ((__ipv6_addr_needs_scope_id(addr_type) && !oif) || + (addr_type & IPV6_ADDR_MAPPED) || + (oif && sk->sk_bound_dev_if && oif != sk->sk_bound_dev_if)) return -EINVAL; /* TODO: use ip6_datagram_send_ctl to get options from cmsg */ @@ -134,16 +139,13 @@ fl6.flowi6_proto = IPPROTO_ICMPV6; fl6.saddr = np->saddr; fl6.daddr = *daddr; + fl6.flowi6_oif = oif; fl6.flowi6_mark = sk->sk_mark; + fl6.flowi6_uid = sk->sk_uid; fl6.fl6_icmp_type = user_icmph.icmp6_type; fl6.fl6_icmp_code = user_icmph.icmp6_code; security_sk_classify_flow(sk, flowi6_to_flowi(&fl6)); - if (!fl6.flowi6_oif && ipv6_addr_is_multicast(&fl6.daddr)) - fl6.flowi6_oif = np->mcast_oif; - else if (!fl6.flowi6_oif) - fl6.flowi6_oif = np->ucast_oif; - dst = ip6_sk_dst_lookup_flow(sk, &fl6, daddr); if (IS_ERR(dst)) return PTR_ERR(dst); @@ -155,11 +157,6 @@ goto dst_err_out; } - if (!fl6.flowi6_oif && ipv6_addr_is_multicast(&fl6.daddr)) - fl6.flowi6_oif = np->mcast_oif; - else if (!fl6.flowi6_oif) - fl6.flowi6_oif = np->ucast_oif; - pfh.icmph.type = user_icmph.icmp6_type; pfh.icmph.code = user_icmph.icmp6_code; pfh.icmph.checksum = 0; diff -ruw linux-4.4.115/net/ipv6/raw.c linux-4.4.115-fbx/net/ipv6/raw.c --- linux-4.4.115/net/ipv6/raw.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/net/ipv6/raw.c 2019-10-29 09:26:25.885225119 +0100 @@ -774,6 +774,7 @@ memset(&fl6, 0, sizeof(fl6)); fl6.flowi6_mark = sk->sk_mark; + fl6.flowi6_uid = sk->sk_uid; if (sin6) { if (addr_len < SIN6_LEN_RFC2133) diff -ruw linux-4.4.115/net/ipv6/route.c linux-4.4.115-fbx/net/ipv6/route.c --- linux-4.4.115/net/ipv6/route.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/net/ipv6/route.c 2019-10-29 09:26:25.889225158 +0100 @@ -99,13 +99,12 @@ static int rt6_score_route(struct rt6_info *rt, int oif, int strict); #ifdef CONFIG_IPV6_ROUTE_INFO -static struct rt6_info *rt6_add_route_info(struct net *net, +static struct rt6_info *rt6_add_route_info(struct net_device *dev, const struct in6_addr *prefix, int prefixlen, - const struct in6_addr *gwaddr, int ifindex, - unsigned int pref); -static struct rt6_info *rt6_get_route_info(struct net *net, + const struct in6_addr *gwaddr, unsigned int pref); +static struct rt6_info *rt6_get_route_info(struct net_device *dev, const struct in6_addr *prefix, int prefixlen, - const struct in6_addr *gwaddr, int ifindex); + const struct in6_addr *gwaddr); #endif struct uncached_list { @@ -392,17 +391,14 @@ struct net_device *loopback_dev = dev_net(dev)->loopback_dev; - if (dev != loopback_dev) { - if (idev && idev->dev == dev) { - struct inet6_dev *loopback_idev = - in6_dev_get(loopback_dev); + if (idev && idev->dev != loopback_dev) { + struct inet6_dev *loopback_idev = in6_dev_get(loopback_dev); if (loopback_idev) { rt->rt6i_idev = loopback_idev; in6_dev_put(idev); } } } -} static bool __rt6_check_expired(const struct rt6_info *rt) { @@ -755,7 +751,6 @@ int rt6_route_rcv(struct net_device *dev, u8 *opt, int len, const struct in6_addr *gwaddr) { - struct net *net = dev_net(dev); struct route_info *rinfo = (struct route_info *) opt; struct in6_addr prefix_buf, *prefix; unsigned int pref; @@ -800,8 +795,7 @@ if (rinfo->prefix_len == 0) rt = rt6_get_dflt_router(gwaddr, dev); else - rt = rt6_get_route_info(net, prefix, rinfo->prefix_len, - gwaddr, dev->ifindex); + rt = rt6_get_route_info(dev, prefix, rinfo->prefix_len, gwaddr); if (rt && !lifetime) { ip6_del_rt(rt); @@ -809,8 +803,7 @@ } if (!rt && lifetime) - rt = rt6_add_route_info(net, prefix, rinfo->prefix_len, gwaddr, dev->ifindex, - pref); + rt = rt6_add_route_info(dev, prefix, rinfo->prefix_len, gwaddr, pref); else if (rt) rt->rt6i_flags = RTF_ROUTEINFO | (rt->rt6i_flags & ~RTF_PREF_MASK) | RTF_PREF(pref); @@ -1395,7 +1388,7 @@ } void ip6_update_pmtu(struct sk_buff *skb, struct net *net, __be32 mtu, - int oif, u32 mark) + int oif, u32 mark, kuid_t uid) { const struct ipv6hdr *iph = (struct ipv6hdr *) skb->data; struct dst_entry *dst; @@ -1407,6 +1400,7 @@ fl6.daddr = iph->daddr; fl6.saddr = iph->saddr; fl6.flowlabel = ip6_flowinfo(iph); + fl6.flowi6_uid = uid; dst = ip6_route_output(net, NULL, &fl6); if (!dst->error) @@ -1418,7 +1412,7 @@ void ip6_sk_update_pmtu(struct sk_buff *skb, struct sock *sk, __be32 mtu) { ip6_update_pmtu(skb, sock_net(sk), mtu, - sk->sk_bound_dev_if, sk->sk_mark); + sk->sk_bound_dev_if, sk->sk_mark, sk->sk_uid); } EXPORT_SYMBOL_GPL(ip6_sk_update_pmtu); @@ -1499,7 +1493,8 @@ flags, __ip6_route_redirect); } -void ip6_redirect(struct sk_buff *skb, struct net *net, int oif, u32 mark) +void ip6_redirect(struct sk_buff *skb, struct net *net, int oif, u32 mark, + kuid_t uid) { const struct ipv6hdr *iph = (struct ipv6hdr *) skb->data; struct dst_entry *dst; @@ -1512,6 +1507,7 @@ fl6.daddr = iph->daddr; fl6.saddr = iph->saddr; fl6.flowlabel = ip6_flowinfo(iph); + fl6.flowi6_uid = uid; dst = ip6_route_redirect(net, &fl6, &ipv6_hdr(skb)->saddr); rt6_do_redirect(dst, NULL, skb); @@ -1533,6 +1529,7 @@ fl6.flowi6_mark = mark; fl6.daddr = msg->dest; fl6.saddr = iph->daddr; + fl6.flowi6_uid = sock_net_uid(net, NULL); dst = ip6_route_redirect(net, &fl6, &iph->saddr); rt6_do_redirect(dst, NULL, skb); @@ -1541,7 +1538,8 @@ void ip6_sk_redirect(struct sk_buff *skb, struct sock *sk) { - ip6_redirect(skb, sock_net(sk), sk->sk_bound_dev_if, sk->sk_mark); + ip6_redirect(skb, sock_net(sk), sk->sk_bound_dev_if, sk->sk_mark, + sk->sk_uid); } EXPORT_SYMBOL_GPL(ip6_sk_redirect); @@ -2263,15 +2261,16 @@ } #ifdef CONFIG_IPV6_ROUTE_INFO -static struct rt6_info *rt6_get_route_info(struct net *net, +static struct rt6_info *rt6_get_route_info(struct net_device *dev, const struct in6_addr *prefix, int prefixlen, - const struct in6_addr *gwaddr, int ifindex) + const struct in6_addr *gwaddr) { struct fib6_node *fn; struct rt6_info *rt = NULL; struct fib6_table *table; - table = fib6_get_table(net, RT6_TABLE_INFO); + table = fib6_get_table(dev_net(dev), + addrconf_rt_table(dev, RT6_TABLE_INFO)); if (!table) return NULL; @@ -2281,7 +2280,7 @@ goto out; for (rt = fn->leaf; rt; rt = rt->dst.rt6_next) { - if (rt->dst.dev->ifindex != ifindex) + if (rt->dst.dev->ifindex != dev->ifindex) continue; if ((rt->rt6i_flags & (RTF_ROUTEINFO|RTF_GATEWAY)) != (RTF_ROUTEINFO|RTF_GATEWAY)) continue; @@ -2295,23 +2294,22 @@ return rt; } -static struct rt6_info *rt6_add_route_info(struct net *net, +static struct rt6_info *rt6_add_route_info(struct net_device *dev, const struct in6_addr *prefix, int prefixlen, - const struct in6_addr *gwaddr, int ifindex, - unsigned int pref) + const struct in6_addr *gwaddr, unsigned int pref) { struct fib6_config cfg = { .fc_metric = IP6_RT_PRIO_USER, - .fc_ifindex = ifindex, + .fc_ifindex = dev->ifindex, .fc_dst_len = prefixlen, .fc_flags = RTF_GATEWAY | RTF_ADDRCONF | RTF_ROUTEINFO | RTF_UP | RTF_PREF(pref), .fc_nlinfo.portid = 0, .fc_nlinfo.nlh = NULL, - .fc_nlinfo.nl_net = net, + .fc_nlinfo.nl_net = dev_net(dev), }; - cfg.fc_table = l3mdev_fib_table_by_index(net, ifindex) ? : RT6_TABLE_INFO; + cfg.fc_table = l3mdev_fib_table_by_index(dev_net(dev), dev->ifindex) ? : addrconf_rt_table(dev, RT6_TABLE_INFO); cfg.fc_dst = *prefix; cfg.fc_gateway = *gwaddr; @@ -2321,7 +2319,7 @@ ip6_route_add(&cfg); - return rt6_get_route_info(net, prefix, prefixlen, gwaddr, ifindex); + return rt6_get_route_info(dev, prefix, prefixlen, gwaddr); } #endif @@ -2330,7 +2328,8 @@ struct rt6_info *rt; struct fib6_table *table; - table = fib6_get_table(dev_net(dev), RT6_TABLE_DFLT); + table = fib6_get_table(dev_net(dev), + addrconf_rt_table(dev, RT6_TABLE_MAIN)); if (!table) return NULL; @@ -2352,7 +2351,7 @@ unsigned int pref) { struct fib6_config cfg = { - .fc_table = l3mdev_fib_table(dev) ? : RT6_TABLE_DFLT, + .fc_table = l3mdev_fib_table(dev) ? : addrconf_rt_table(dev, RT6_TABLE_DFLT), .fc_metric = IP6_RT_PRIO_USER, .fc_ifindex = dev->ifindex, .fc_flags = RTF_GATEWAY | RTF_ADDRCONF | RTF_DEFAULT | @@ -2369,28 +2368,17 @@ return rt6_get_dflt_router(gwaddr, dev); } -void rt6_purge_dflt_routers(struct net *net) -{ - struct rt6_info *rt; - struct fib6_table *table; - - /* NOTE: Keep consistent with rt6_get_dflt_router */ - table = fib6_get_table(net, RT6_TABLE_DFLT); - if (!table) - return; -restart: - read_lock_bh(&table->tb6_lock); - for (rt = table->tb6_root.leaf; rt; rt = rt->dst.rt6_next) { +int rt6_addrconf_purge(struct rt6_info *rt, void *arg) { if (rt->rt6i_flags & (RTF_DEFAULT | RTF_ADDRCONF) && - (!rt->rt6i_idev || rt->rt6i_idev->cnf.accept_ra != 2)) { - dst_hold(&rt->dst); - read_unlock_bh(&table->tb6_lock); - ip6_del_rt(rt); - goto restart; - } + (!rt->rt6i_idev || rt->rt6i_idev->cnf.accept_ra != 2)) + return -1; + return 0; } - read_unlock_bh(&table->tb6_lock); + +void rt6_purge_dflt_routers(struct net *net) +{ + fib6_clean_all(net, rt6_addrconf_purge, NULL); } static void rtmsg_to_fib6_config(struct net *net, @@ -2715,6 +2703,7 @@ [RTA_PREF] = { .type = NLA_U8 }, [RTA_ENCAP_TYPE] = { .type = NLA_U16 }, [RTA_ENCAP] = { .type = NLA_NESTED }, + [RTA_UID] = { .type = NLA_U32 }, }; static int rtm_to_fib6_config(struct sk_buff *skb, struct nlmsghdr *nlh, @@ -3220,6 +3209,10 @@ { struct rt6_rtnl_dump_arg *arg = (struct rt6_rtnl_dump_arg *) p_arg; int prefix; + struct net *net = arg->net; + + if (rt == net->ipv6.ip6_null_entry) + return 0; if (nlmsg_len(arg->cb->nlh) >= sizeof(struct rtmsg)) { struct rtmsg *rtm = nlmsg_data(arg->cb->nlh); @@ -3227,7 +3220,7 @@ } else prefix = 0; - return rt6_fill_node(arg->net, + return rt6_fill_node(net, arg->skb, rt, NULL, NULL, 0, RTM_NEWROUTE, NETLINK_CB(arg->cb->skb).portid, arg->cb->nlh->nlmsg_seq, prefix, 0, NLM_F_MULTI); @@ -3273,6 +3266,12 @@ if (tb[RTA_MARK]) fl6.flowi6_mark = nla_get_u32(tb[RTA_MARK]); + if (tb[RTA_UID]) + fl6.flowi6_uid = make_kuid(current_user_ns(), + nla_get_u32(tb[RTA_UID])); + else + fl6.flowi6_uid = iif ? INVALID_UID : current_uid(); + if (iif) { struct net_device *dev; int flags = 0; diff -ruw linux-4.4.115/net/ipv6/tcp_ipv6.c linux-4.4.115-fbx/net/ipv6/tcp_ipv6.c --- linux-4.4.115/net/ipv6/tcp_ipv6.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/net/ipv6/tcp_ipv6.c 2019-10-29 09:26:25.893225197 +0100 @@ -239,6 +239,7 @@ fl6.flowi6_mark = sk->sk_mark; fl6.fl6_dport = usin->sin6_port; fl6.fl6_sport = inet->inet_sport; + fl6.flowi6_uid = sk->sk_uid; opt = rcu_dereference_protected(np->opt, sock_owned_by_user(sk)); final_p = fl6_update_dst(&fl6, opt, &final); @@ -820,6 +821,7 @@ fl6.flowi6_mark = IP6_REPLY_MARK(net, skb->mark); fl6.fl6_dport = t1->dest; fl6.fl6_sport = t1->source; + fl6.flowi6_uid = sock_net_uid(net, sk && sk_fullsock(sk) ? sk : NULL); security_skb_classify_flow(skb, flowi6_to_flowi(&fl6)); /* Pass a socket to ip6_dst_lookup either it is for RST @@ -1721,6 +1723,7 @@ const struct fastopen_queue *fastopenq = &icsk->icsk_accept_queue.fastopenq; int rx_queue; int state; + __u8 state_seq = sp->sk_state; dest = &sp->sk_v6_daddr; src = &sp->sk_v6_rcv_saddr; @@ -1752,6 +1755,9 @@ */ rx_queue = max_t(int, tp->rcv_nxt - tp->copied_seq, 0); + if (inet->transparent) + state_seq |= 0x80; + seq_printf(seq, "%4d: %08X%08X%08X%08X:%04X %08X%08X%08X%08X:%04X " "%02X %08X:%08X %02X:%08lX %08X %5u %8d %lu %d %pK %lu %lu %u %u %d\n", @@ -1760,7 +1766,7 @@ src->s6_addr32[2], src->s6_addr32[3], srcp, dest->s6_addr32[0], dest->s6_addr32[1], dest->s6_addr32[2], dest->s6_addr32[3], destp, - state, + state_seq, tp->write_seq - tp->snd_una, rx_queue, timer_active, @@ -1915,6 +1921,7 @@ .proto_cgroup = tcp_proto_cgroup, #endif .clear_sk = tcp_v6_clear_sk, + .diag_destroy = tcp_abort, }; static const struct inet6_protocol tcpv6_protocol = { diff -ruw linux-4.4.115/net/ipv6/udp.c linux-4.4.115-fbx/net/ipv6/udp.c --- linux-4.4.115/net/ipv6/udp.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/net/ipv6/udp.c 2019-10-29 09:26:25.893225197 +0100 @@ -45,6 +45,7 @@ #include #include #include +#include #include #include @@ -958,6 +959,71 @@ return 0; } +static struct sock *__udp6_lib_demux_lookup(struct net *net, + __be16 loc_port, const struct in6_addr *loc_addr, + __be16 rmt_port, const struct in6_addr *rmt_addr, + int dif) +{ + struct sock *sk; + struct hlist_nulls_node *hnode; + unsigned short hnum = ntohs(loc_port); + unsigned int hash2 = udp6_portaddr_hash(net, loc_addr, hnum); + unsigned int slot2 = hash2 & udp_table.mask; + struct udp_hslot *hslot2 = &udp_table.hash2[slot2]; + + const __portpair ports = INET_COMBINED_PORTS(rmt_port, hnum); + + udp_portaddr_for_each_entry_rcu(sk, hnode, &hslot2->head) { + if (sk->sk_state == TCP_ESTABLISHED && + INET6_MATCH(sk, net, rmt_addr, loc_addr, ports, dif)) + return sk; + /* Only check first socket in chain */ + break; + } + return NULL; +} + +static void udp_v6_early_demux(struct sk_buff *skb) +{ + struct net *net = dev_net(skb->dev); + const struct udphdr *uh; + struct sock *sk; + struct dst_entry *dst; + int dif = skb->dev->ifindex; + + if (!pskb_may_pull(skb, skb_transport_offset(skb) + + sizeof(struct udphdr))) + return; + + uh = udp_hdr(skb); + + if (skb->pkt_type == PACKET_HOST) + sk = __udp6_lib_demux_lookup(net, uh->dest, + &ipv6_hdr(skb)->daddr, + uh->source, &ipv6_hdr(skb)->saddr, + dif); + else + return; + + if (!sk || !atomic_inc_not_zero_hint(&sk->sk_refcnt, 2)) + return; + + skb->sk = sk; + skb->destructor = sock_efree; + dst = READ_ONCE(sk->sk_rx_dst); + + if (dst) + dst = dst_check(dst, inet6_sk(sk)->rx_dst_cookie); + if (dst) { + if (dst->flags & DST_NOCACHE) { + if (likely(atomic_inc_not_zero(&dst->__refcnt))) + skb_dst_set(skb, dst); + } else { + skb_dst_set_noref(skb, dst); + } + } +} + static __inline__ int udpv6_rcv(struct sk_buff *skb) { return __udp6_lib_rcv(skb, &udp_table, IPPROTO_UDP); @@ -1249,6 +1315,7 @@ fl6.flowi6_oif = np->sticky_pktinfo.ipi6_ifindex; fl6.flowi6_mark = sk->sk_mark; + fl6.flowi6_uid = sk->sk_uid; if (msg->msg_controllen) { opt = &opt_space; @@ -1465,6 +1532,7 @@ #endif static const struct inet6_protocol udpv6_protocol = { + .early_demux = udp_v6_early_demux, .handler = udpv6_rcv, .err_handler = udpv6_err, .flags = INET6_PROTO_NOPOLICY|INET6_PROTO_FINAL, @@ -1557,6 +1625,7 @@ .compat_getsockopt = compat_udpv6_getsockopt, #endif .clear_sk = udp_v6_clear_sk, + .diag_destroy = udp_abort, }; static struct inet_protosw udpv6_protosw = { diff -ruw linux-4.4.115/net/ipv6/xfrm6_policy.c linux-4.4.115-fbx/net/ipv6/xfrm6_policy.c --- linux-4.4.115/net/ipv6/xfrm6_policy.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/net/ipv6/xfrm6_policy.c 2019-10-29 09:26:25.893225197 +0100 @@ -29,15 +29,17 @@ static struct dst_entry *xfrm6_dst_lookup(struct net *net, int tos, int oif, const xfrm_address_t *saddr, - const xfrm_address_t *daddr) + const xfrm_address_t *daddr, + u32 mark) { struct flowi6 fl6; struct dst_entry *dst; int err; memset(&fl6, 0, sizeof(fl6)); - fl6.flowi6_oif = oif; + fl6.flowi6_oif = l3mdev_master_ifindex_by_index(net, oif); fl6.flowi6_flags = FLOWI_FLAG_SKIP_NH_OIF; + fl6.flowi6_mark = mark; memcpy(&fl6.daddr, daddr, sizeof(fl6.daddr)); if (saddr) memcpy(&fl6.saddr, saddr, sizeof(fl6.saddr)); @@ -54,12 +56,13 @@ } static int xfrm6_get_saddr(struct net *net, int oif, - xfrm_address_t *saddr, xfrm_address_t *daddr) + xfrm_address_t *saddr, xfrm_address_t *daddr, + u32 mark) { struct dst_entry *dst; struct net_device *dev; - dst = xfrm6_dst_lookup(net, 0, oif, NULL, daddr); + dst = xfrm6_dst_lookup(net, 0, oif, NULL, daddr, mark); if (IS_ERR(dst)) return -EHOSTUNREACH; diff -ruw linux-4.4.115/net/Kconfig linux-4.4.115-fbx/net/Kconfig --- linux-4.4.115/net/Kconfig 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/net/Kconfig 2019-10-29 09:26:25.753223827 +0100 @@ -48,6 +48,16 @@ config NET_INGRESS bool +config DISABLE_NET_SKB_FRAG_CACHE + bool "Disable skb fragment cache" + help + Enabling this option ensures that when allocating skbs the network + skb fragment cache is not used. + Disabling use of the fragment cache can be useful on some low end + targets because it reduces memory pressure. + + If you are unsure how to answer this question, answer N. + menu "Networking options" source "net/packet/Kconfig" @@ -86,6 +96,12 @@ endif # if INET +config ANDROID_PARANOID_NETWORK + bool "Only allow certain groups to create sockets" + default y + help + none + config NETWORK_SECMARK bool "Security Marking" help @@ -233,6 +249,7 @@ source "net/hsr/Kconfig" source "net/switchdev/Kconfig" source "net/l3mdev/Kconfig" +source "net/rmnet_data/Kconfig" config RPS bool @@ -297,6 +314,15 @@ with many clients some protection against DoS by a single (spoofed) flow that greatly exceeds average workload. +config SOCKEV_NLMCAST + bool "Enable SOCKEV Netlink Multicast" + default n + ---help--- + Default client for SOCKEV notifier events. Sends multicast netlink + messages whenever the socket event notifier is invoked. Enable if + user space entities need to be notified of socket events without + having to poll /proc + menu "Network testing" config NET_PKTGEN @@ -383,6 +409,8 @@ weight tunnel endpoint. Tunnel encapsulation parameters are stored with light weight tunnel state associated with fib routes. +source "net/ipc_router/Kconfig" + endif # if NET # Used by archs to tell that they support BPF_JIT diff -ruw linux-4.4.115/net/key/af_key.c linux-4.4.115-fbx/net/key/af_key.c --- linux-4.4.115/net/key/af_key.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/net/key/af_key.c 2019-10-29 09:26:25.897225236 +0100 @@ -196,30 +196,22 @@ return 0; } -static int pfkey_broadcast_one(struct sk_buff *skb, struct sk_buff **skb2, - gfp_t allocation, struct sock *sk) +static int pfkey_broadcast_one(struct sk_buff *skb, gfp_t allocation, + struct sock *sk) { int err = -ENOBUFS; - sock_hold(sk); - if (*skb2 == NULL) { - if (atomic_read(&skb->users) != 1) { - *skb2 = skb_clone(skb, allocation); - } else { - *skb2 = skb; - atomic_inc(&skb->users); - } - } - if (*skb2 != NULL) { - if (atomic_read(&sk->sk_rmem_alloc) <= sk->sk_rcvbuf) { - skb_set_owner_r(*skb2, sk); - skb_queue_tail(&sk->sk_receive_queue, *skb2); + if (atomic_read(&sk->sk_rmem_alloc) > sk->sk_rcvbuf) + return err; + + skb = skb_clone(skb, allocation); + + if (skb) { + skb_set_owner_r(skb, sk); + skb_queue_tail(&sk->sk_receive_queue, skb); sk->sk_data_ready(sk); - *skb2 = NULL; err = 0; } - } - sock_put(sk); return err; } @@ -234,7 +226,6 @@ { struct netns_pfkey *net_pfkey = net_generic(net, pfkey_net_id); struct sock *sk; - struct sk_buff *skb2 = NULL; int err = -ESRCH; /* XXX Do we need something like netlink_overrun? I think @@ -253,7 +244,7 @@ * socket. */ if (pfk->promisc) - pfkey_broadcast_one(skb, &skb2, GFP_ATOMIC, sk); + pfkey_broadcast_one(skb, GFP_ATOMIC, sk); /* the exact target will be processed later */ if (sk == one_sk) @@ -268,7 +259,7 @@ continue; } - err2 = pfkey_broadcast_one(skb, &skb2, GFP_ATOMIC, sk); + err2 = pfkey_broadcast_one(skb, GFP_ATOMIC, sk); /* Error is cleared after successful sending to at least one * registered KM */ @@ -278,9 +269,8 @@ rcu_read_unlock(); if (one_sk != NULL) - err = pfkey_broadcast_one(skb, &skb2, allocation, one_sk); + err = pfkey_broadcast_one(skb, allocation, one_sk); - kfree_skb(skb2); kfree_skb(skb); return err; } diff -ruw linux-4.4.115/net/mac80211/ieee80211_i.h linux-4.4.115-fbx/net/mac80211/ieee80211_i.h --- linux-4.4.115/net/mac80211/ieee80211_i.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/net/mac80211/ieee80211_i.h 2019-01-22 16:16:29.087296973 +0100 @@ -807,6 +807,7 @@ struct txq_info { struct sk_buff_head queue; unsigned long flags; + unsigned long byte_cnt; /* keep last! */ struct ieee80211_txq txq; diff -ruw linux-4.4.115/net/mac80211/iface.c linux-4.4.115-fbx/net/mac80211/iface.c --- linux-4.4.115/net/mac80211/iface.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/net/mac80211/iface.c 2019-10-29 09:26:25.909225353 +0100 @@ -979,6 +979,7 @@ spin_lock_bh(&txqi->queue.lock); ieee80211_purge_tx_queue(&local->hw, &txqi->queue); + txqi->byte_cnt = 0; spin_unlock_bh(&txqi->queue.lock); atomic_set(&sdata->txqs_len[txqi->txq.ac], 0); diff -ruw linux-4.4.115/net/mac80211/mesh_hwmp.c linux-4.4.115-fbx/net/mac80211/mesh_hwmp.c --- linux-4.4.115/net/mac80211/mesh_hwmp.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/net/mac80211/mesh_hwmp.c 2019-10-29 09:26:25.909225353 +0100 @@ -530,7 +530,7 @@ const u8 *target_addr, *orig_addr; const u8 *da; u8 target_flags, ttl, flags; - u32 orig_sn, target_sn, lifetime, target_metric; + u32 orig_sn, target_sn, lifetime, target_metric = 0; bool reply = false; bool forward = true; bool root_is_gate; diff -ruw linux-4.4.115/net/mac80211/mlme.c linux-4.4.115-fbx/net/mac80211/mlme.c --- linux-4.4.115/net/mac80211/mlme.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/net/mac80211/mlme.c 2019-10-29 09:26:25.913225393 +0100 @@ -4490,20 +4490,20 @@ return -EOPNOTSUPP; } - auth_data = kzalloc(sizeof(*auth_data) + req->sae_data_len + + auth_data = kzalloc(sizeof(*auth_data) + req->auth_data_len + req->ie_len, GFP_KERNEL); if (!auth_data) return -ENOMEM; auth_data->bss = req->bss; - if (req->sae_data_len >= 4) { - __le16 *pos = (__le16 *) req->sae_data; + if (req->auth_data_len >= 4) { + __le16 *pos = (__le16 *) req->auth_data; auth_data->sae_trans = le16_to_cpu(pos[0]); auth_data->sae_status = le16_to_cpu(pos[1]); - memcpy(auth_data->data, req->sae_data + 4, - req->sae_data_len - 4); - auth_data->data_len += req->sae_data_len - 4; + memcpy(auth_data->data, req->auth_data + 4, + req->auth_data_len - 4); + auth_data->data_len += req->auth_data_len - 4; } if (req->ie && req->ie_len) { diff -ruw linux-4.4.115/net/mac80211/rx.c linux-4.4.115-fbx/net/mac80211/rx.c --- linux-4.4.115/net/mac80211/rx.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/net/mac80211/rx.c 2019-10-29 09:26:25.913225393 +0100 @@ -122,7 +122,8 @@ hdr = (void *)(skb->data + rtap_vendor_space); if (status->flag & (RX_FLAG_FAILED_FCS_CRC | - RX_FLAG_FAILED_PLCP_CRC)) + RX_FLAG_FAILED_PLCP_CRC | + RX_FLAG_ONLY_MONITOR)) return true; if (unlikely(skb->len < 16 + present_fcs_len + rtap_vendor_space)) @@ -507,7 +508,7 @@ return NULL; } - if (!local->monitors) { + if (!local->monitors || (status->flag & RX_FLAG_SKIP_MONITOR)) { if (should_drop_frame(origskb, present_fcs_len, rtap_vendor_space)) { dev_kfree_skb(origskb); @@ -3478,6 +3479,7 @@ * be called with rcu_read_lock protection. */ static void __ieee80211_rx_handle_packet(struct ieee80211_hw *hw, + struct ieee80211_sta *pubsta, struct sk_buff *skb, struct napi_struct *napi) { @@ -3487,7 +3489,6 @@ __le16 fc; struct ieee80211_rx_data rx; struct ieee80211_sub_if_data *prev; - struct sta_info *sta, *prev_sta; struct rhash_head *tmp; int err = 0; @@ -3523,7 +3524,14 @@ ieee80211_is_beacon(hdr->frame_control))) ieee80211_scan_rx(local, skb); - if (ieee80211_is_data(fc)) { + if (pubsta) { + rx.sta = container_of(pubsta, struct sta_info, sta); + rx.sdata = rx.sta->sdata; + if (ieee80211_prepare_and_rx_handle(&rx, skb, true)) + return; + goto out; + } else if (ieee80211_is_data(fc)) { + struct sta_info *sta, *prev_sta; const struct bucket_table *tbl; prev_sta = NULL; @@ -3597,8 +3605,8 @@ * This is the receive path handler. It is called by a low level driver when an * 802.11 MPDU is received from the hardware. */ -void ieee80211_rx_napi(struct ieee80211_hw *hw, struct sk_buff *skb, - struct napi_struct *napi) +void ieee80211_rx_napi(struct ieee80211_hw *hw, struct ieee80211_sta *pubsta, + struct sk_buff *skb, struct napi_struct *napi) { struct ieee80211_local *local = hw_to_local(hw); struct ieee80211_rate *rate = NULL; @@ -3697,7 +3705,8 @@ ieee80211_tpt_led_trig_rx(local, ((struct ieee80211_hdr *)skb->data)->frame_control, skb->len); - __ieee80211_rx_handle_packet(hw, skb, napi); + + __ieee80211_rx_handle_packet(hw, pubsta, skb, napi); rcu_read_unlock(); diff -ruw linux-4.4.115/net/mac80211/sta_info.c linux-4.4.115-fbx/net/mac80211/sta_info.c --- linux-4.4.115/net/mac80211/sta_info.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/net/mac80211/sta_info.c 2019-01-22 16:16:29.099297082 +0100 @@ -115,6 +115,7 @@ ieee80211_purge_tx_queue(&local->hw, &txqi->queue); atomic_sub(n, &sdata->txqs_len[txqi->txq.ac]); + txqi->byte_cnt = 0; } } diff -ruw linux-4.4.115/net/mac80211/tx.c linux-4.4.115-fbx/net/mac80211/tx.c --- linux-4.4.115/net/mac80211/tx.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/net/mac80211/tx.c 2019-10-29 09:26:25.917225432 +0100 @@ -1266,7 +1266,11 @@ if (atomic_read(&sdata->txqs_len[ac]) >= local->hw.txq_ac_max_pending) netif_stop_subqueue(sdata->dev, ac); - skb_queue_tail(&txqi->queue, skb); + spin_lock_bh(&txqi->queue.lock); + txqi->byte_cnt += skb->len; + __skb_queue_tail(&txqi->queue, skb); + spin_unlock_bh(&txqi->queue.lock); + drv_wake_tx_queue(local, txqi); return; @@ -1294,6 +1298,8 @@ if (!skb) goto out; + txqi->byte_cnt -= skb->len; + atomic_dec(&sdata->txqs_len[ac]); if (__netif_subqueue_stopped(sdata->dev, ac)) ieee80211_propagate_queue_wake(local, sdata->vif.hw_queue[ac]); diff -ruw linux-4.4.115/net/mac80211/util.c linux-4.4.115-fbx/net/mac80211/util.c --- linux-4.4.115/net/mac80211/util.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/net/mac80211/util.c 2019-10-29 09:26:25.917225432 +0100 @@ -3198,10 +3198,11 @@ struct ieee80211_local *local = sdata->local; struct ieee80211_sub_if_data *sdata_iter; enum nl80211_iftype iftype = sdata->wdev.iftype; - int num[NUM_NL80211_IFTYPES]; struct ieee80211_chanctx *ctx; - int num_different_channels = 0; int total = 1; + struct iface_combination_params params = { + .radar_detect = radar_detect, + }; lockdep_assert_held(&local->chanctx_mtx); @@ -3212,9 +3213,6 @@ !chandef->chan)) return -EINVAL; - if (chandef) - num_different_channels = 1; - if (WARN_ON(iftype >= NUM_NL80211_IFTYPES)) return -EINVAL; @@ -3225,24 +3223,26 @@ return 0; } - memset(num, 0, sizeof(num)); + if (chandef) + params.num_different_channels = 1; if (iftype != NL80211_IFTYPE_UNSPECIFIED) - num[iftype] = 1; + params.iftype_num[iftype] = 1; list_for_each_entry(ctx, &local->chanctx_list, list) { if (ctx->replace_state == IEEE80211_CHANCTX_WILL_BE_REPLACED) continue; - radar_detect |= ieee80211_chanctx_radar_detect(local, ctx); + params.radar_detect |= + ieee80211_chanctx_radar_detect(local, ctx); if (ctx->mode == IEEE80211_CHANCTX_EXCLUSIVE) { - num_different_channels++; + params.num_different_channels++; continue; } if (chandef && chanmode == IEEE80211_CHANCTX_SHARED && cfg80211_chandef_compatible(chandef, &ctx->conf.def)) continue; - num_different_channels++; + params.num_different_channels++; } list_for_each_entry_rcu(sdata_iter, &local->interfaces, list) { @@ -3255,16 +3255,14 @@ local->hw.wiphy->software_iftypes & BIT(wdev_iter->iftype)) continue; - num[wdev_iter->iftype]++; + params.iftype_num[wdev_iter->iftype]++; total++; } - if (total == 1 && !radar_detect) + if (total == 1 && !params.radar_detect) return 0; - return cfg80211_check_combinations(local->hw.wiphy, - num_different_channels, - radar_detect, num); + return cfg80211_check_combinations(local->hw.wiphy, ¶ms); } static void @@ -3280,12 +3278,10 @@ int ieee80211_max_num_channels(struct ieee80211_local *local) { struct ieee80211_sub_if_data *sdata; - int num[NUM_NL80211_IFTYPES] = {}; struct ieee80211_chanctx *ctx; - int num_different_channels = 0; - u8 radar_detect = 0; u32 max_num_different_channels = 1; int err; + struct iface_combination_params params = {0}; lockdep_assert_held(&local->chanctx_mtx); @@ -3293,17 +3289,17 @@ if (ctx->replace_state == IEEE80211_CHANCTX_WILL_BE_REPLACED) continue; - num_different_channels++; + params.num_different_channels++; - radar_detect |= ieee80211_chanctx_radar_detect(local, ctx); + params.radar_detect |= + ieee80211_chanctx_radar_detect(local, ctx); } list_for_each_entry_rcu(sdata, &local->interfaces, list) - num[sdata->wdev.iftype]++; + params.iftype_num[sdata->wdev.iftype]++; - err = cfg80211_iter_combinations(local->hw.wiphy, - num_different_channels, radar_detect, - num, ieee80211_iter_max_chans, + err = cfg80211_iter_combinations(local->hw.wiphy, ¶ms, + ieee80211_iter_max_chans, &max_num_different_channels); if (err < 0) return err; @@ -3344,3 +3340,17 @@ txqi->txq.ac = IEEE80211_AC_BE; } } + +void ieee80211_txq_get_depth(struct ieee80211_txq *txq, + unsigned long *frame_cnt, + unsigned long *byte_cnt) +{ + struct txq_info *txqi = to_txq_info(txq); + + if (frame_cnt) + *frame_cnt = txqi->queue.qlen; + + if (byte_cnt) + *byte_cnt = txqi->byte_cnt; +} +EXPORT_SYMBOL(ieee80211_txq_get_depth); diff -ruw linux-4.4.115/net/Makefile linux-4.4.115-fbx/net/Makefile --- linux-4.4.115/net/Makefile 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/net/Makefile 2019-01-22 16:16:28.847294800 +0100 @@ -77,3 +77,5 @@ ifneq ($(CONFIG_NET_L3_MASTER_DEV),) obj-y += l3mdev/ endif +obj-$(CONFIG_IPC_ROUTER) += ipc_router/ +obj-$(CONFIG_RMNET_DATA) += rmnet_data/ diff -ruw linux-4.4.115/net/netfilter/core.c linux-4.4.115-fbx/net/netfilter/core.c --- linux-4.4.115/net/netfilter/core.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/net/netfilter/core.c 2019-01-22 16:16:29.111297190 +0100 @@ -123,7 +123,7 @@ void nf_unregister_net_hook(struct net *net, const struct nf_hook_ops *reg) { struct list_head *hook_list; - struct nf_hook_entry *entry; + struct nf_hook_entry *entry = NULL; struct nf_hook_ops *elem; hook_list = nf_find_hook_list(net, reg); diff -ruw linux-4.4.115/net/netfilter/Kconfig linux-4.4.115-fbx/net/netfilter/Kconfig --- linux-4.4.115/net/netfilter/Kconfig 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/net/netfilter/Kconfig 2019-01-22 16:16:29.111297190 +0100 @@ -749,6 +749,20 @@ To compile it as a module, choose M here. If unsure, say N. +config NETFILTER_XT_TARGET_HARDIDLETIMER + tristate "HARDIDLETIMER target support" + depends on NETFILTER_ADVANCED + help + + This option adds the `HARDIDLETIMER' target. Each matching packet + resets the timer associated with label specified when the rule is + added. When the timer expires, it triggers a sysfs notification. + The remaining time for expiration can be read via sysfs. + Compared to IDLETIMER HARDIDLETIMER will send notification when + CPU in suspend too. + + To compile it as a module, choose M here. If unsure, say N. + config NETFILTER_XT_TARGET_LED tristate '"LED" target support' depends on LEDS_CLASS && LEDS_TRIGGERS @@ -1278,6 +1292,8 @@ based on who created the socket: the user or group. It is also possible to check whether a socket actually exists. + Conflicts with '"quota, tag, uid" match' + config NETFILTER_XT_MATCH_POLICY tristate 'IPsec "policy" match support' depends on XFRM @@ -1311,6 +1327,22 @@ To compile it as a module, choose M here. If unsure, say N. +config NETFILTER_XT_MATCH_QTAGUID + bool '"quota, tag, owner" match and stats support' + depends on NETFILTER_XT_MATCH_SOCKET + depends on NETFILTER_XT_MATCH_OWNER=n + help + This option replaces the `owner' match. In addition to matching + on uid, it keeps stats based on a tag assigned to a socket. + The full tag is comprised of a UID and an accounting tag. + The tags are assignable to sockets from user space (e.g. a download + manager can assign the socket to another UID for accounting). + Stats and control are done via /proc/net/xt_qtaguid/. + It replaces owner as it takes the same arguments, but should + really be recognized by the iptables tool. + + If unsure, say `N'. + config NETFILTER_XT_MATCH_QUOTA tristate '"quota" match support' depends on NETFILTER_ADVANCED @@ -1321,6 +1353,29 @@ If you want to compile it as a module, say M here and read . If unsure, say `N'. +config NETFILTER_XT_MATCH_QUOTA2 + tristate '"quota2" match support' + depends on NETFILTER_ADVANCED + help + This option adds a `quota2' match, which allows to match on a + byte counter correctly and not per CPU. + It allows naming the quotas. + This is based on http://xtables-addons.git.sourceforge.net + + If you want to compile it as a module, say M here and read + . If unsure, say `N'. + +config NETFILTER_XT_MATCH_QUOTA2_LOG + bool '"quota2" Netfilter LOG support' + depends on NETFILTER_XT_MATCH_QUOTA2 + default n + help + This option allows `quota2' to log ONCE when a quota limit + is passed. It logs via NETLINK using the NETLINK_NFLOG family. + It logs similarly to how ipt_ULOG would without data. + + If unsure, say `N'. + config NETFILTER_XT_MATCH_RATEEST tristate '"rateest" match support' depends on NETFILTER_ADVANCED diff -ruw linux-4.4.115/net/netfilter/Makefile linux-4.4.115-fbx/net/netfilter/Makefile --- linux-4.4.115/net/netfilter/Makefile 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/net/netfilter/Makefile 2019-01-22 16:16:29.111297190 +0100 @@ -122,6 +122,7 @@ obj-$(CONFIG_NETFILTER_XT_TARGET_TEE) += xt_TEE.o obj-$(CONFIG_NETFILTER_XT_TARGET_TRACE) += xt_TRACE.o obj-$(CONFIG_NETFILTER_XT_TARGET_IDLETIMER) += xt_IDLETIMER.o +obj-$(CONFIG_NETFILTER_XT_TARGET_HARDIDLETIMER) += xt_HARDIDLETIMER.o # matches obj-$(CONFIG_NETFILTER_XT_MATCH_ADDRTYPE) += xt_addrtype.o @@ -156,7 +157,9 @@ obj-$(CONFIG_NETFILTER_XT_MATCH_PHYSDEV) += xt_physdev.o obj-$(CONFIG_NETFILTER_XT_MATCH_PKTTYPE) += xt_pkttype.o obj-$(CONFIG_NETFILTER_XT_MATCH_POLICY) += xt_policy.o +obj-$(CONFIG_NETFILTER_XT_MATCH_QTAGUID) += xt_qtaguid_print.o xt_qtaguid.o obj-$(CONFIG_NETFILTER_XT_MATCH_QUOTA) += xt_quota.o +obj-$(CONFIG_NETFILTER_XT_MATCH_QUOTA2) += xt_quota2.o obj-$(CONFIG_NETFILTER_XT_MATCH_RATEEST) += xt_rateest.o obj-$(CONFIG_NETFILTER_XT_MATCH_REALM) += xt_realm.o obj-$(CONFIG_NETFILTER_XT_MATCH_RECENT) += xt_recent.o diff -ruw linux-4.4.115/net/netfilter/nf_conntrack_core.c linux-4.4.115-fbx/net/netfilter/nf_conntrack_core.c --- linux-4.4.115/net/netfilter/nf_conntrack_core.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/net/netfilter/nf_conntrack_core.c 2019-10-29 09:26:25.929225549 +0100 @@ -237,7 +237,7 @@ static void clean_from_lists(struct nf_conn *ct) { - pr_debug("clean_from_lists(%p)\n", ct); + pr_debug("clean_from_lists(%pK)\n", ct); hlist_nulls_del_rcu(&ct->tuplehash[IP_CT_DIR_ORIGINAL].hnnode); hlist_nulls_del_rcu(&ct->tuplehash[IP_CT_DIR_REPLY].hnnode); @@ -330,7 +330,7 @@ struct net *net = nf_ct_net(ct); struct nf_conntrack_l4proto *l4proto; - pr_debug("destroy_conntrack(%p)\n", ct); + pr_debug("destroy_conntrack(%pK)\n", ct); NF_CT_ASSERT(atomic_read(&nfct->use) == 0); NF_CT_ASSERT(!timer_pending(&ct->timeout)); @@ -361,7 +361,7 @@ if (ct->master) nf_ct_put(ct->master); - pr_debug("destroy_conntrack: returning ct=%p to slab\n", ct); + pr_debug("destroy_conntrack: returning ct=%pK to slab\n", ct); nf_conntrack_free(ct); } @@ -629,7 +629,7 @@ * confirmed us. */ NF_CT_ASSERT(!nf_ct_is_confirmed(ct)); - pr_debug("Confirming conntrack %p\n", ct); + pr_debug("Confirming conntrack %pK\n", ct); /* We have to check the DYING flag after unlink to prevent * a race against nf_ct_get_next_corpse() possibly called from * user context, else we insert an already 'dead' hash, blocking @@ -979,7 +979,7 @@ spin_lock(&nf_conntrack_expect_lock); exp = nf_ct_find_expectation(net, zone, tuple); if (exp) { - pr_debug("conntrack: expectation arrives ct=%p exp=%p\n", + pr_debug("conntrack: expectation arrives ct=%pK exp=%pK\n", ct, exp); /* Welcome, Mr. Bond. We've been expecting you... */ __set_bit(IPS_EXPECTED_BIT, &ct->status); @@ -1070,14 +1070,14 @@ } else { /* Once we've had two way comms, always ESTABLISHED. */ if (test_bit(IPS_SEEN_REPLY_BIT, &ct->status)) { - pr_debug("nf_conntrack_in: normal packet for %p\n", ct); + pr_debug("nf_conntrack_in: normal packet for %pK\n", ct); *ctinfo = IP_CT_ESTABLISHED; } else if (test_bit(IPS_EXPECTED_BIT, &ct->status)) { - pr_debug("nf_conntrack_in: related packet for %p\n", + pr_debug("nf_conntrack_in: related packet for %pK\n", ct); *ctinfo = IP_CT_RELATED; } else { - pr_debug("nf_conntrack_in: new packet for %p\n", ct); + pr_debug("nf_conntrack_in: new packet for %pK\n", ct); *ctinfo = IP_CT_NEW; } *set_reply = 0; @@ -1219,7 +1219,7 @@ /* Should be unconfirmed, so not in hash table yet */ NF_CT_ASSERT(!nf_ct_is_confirmed(ct)); - pr_debug("Altering reply tuple of %p to ", ct); + pr_debug("Altering reply tuple of %pK to ", ct); nf_ct_dump_tuple(newreply); ct->tuplehash[IP_CT_DIR_REPLY].tuple = *newreply; diff -ruw linux-4.4.115/net/netfilter/xt_owner.c linux-4.4.115-fbx/net/netfilter/xt_owner.c --- linux-4.4.115/net/netfilter/xt_owner.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/net/netfilter/xt_owner.c 2019-01-22 16:16:29.143297480 +0100 @@ -29,6 +29,61 @@ return 0; } +static int __owner_match_simple_gid(kgid_t gid, kgid_t gid_min, kgid_t gid_max) +{ + return gid_gte(gid, gid_min) && gid_lte(gid, gid_max); +} + +/* + * see kernel/groups.c:groups_to_user() function, which inspired the + * content of this function. + */ +static int __owner_match_gid_groupinfo(const struct group_info *group_info, + kgid_t gid_min, kgid_t gid_max) +{ + unsigned int count = group_info->ngroups; + unsigned int block; + + for (block = 0; block < group_info->nblocks; ++block) { + unsigned int cp_count = min(NGROUPS_PER_BLOCK, count); + unsigned int i; + + for (i = 0; i < cp_count; ++i) { + if (__owner_match_simple_gid( + group_info->blocks[block][i], + gid_min, gid_max)) { + return 1; + } + count -= cp_count; + } + } + return 0; +} + +static int owner_match_gid(const struct file *filp, + const struct xt_owner_match_info *info) +{ + kgid_t gid_min = make_kgid(&init_user_ns, info->gid_min); + kgid_t gid_max = make_kgid(&init_user_ns, info->gid_max); + + /* + * direct match, this is the simple and only case handled by + * the old code, file fsgid matches info gid range. + */ + if (__owner_match_simple_gid(filp->f_cred->fsgid, gid_min, gid_max)) + return 1; + + /* + * otherwise we need to have a look to the group list available + * in f_cred->group_info. + */ + if (__owner_match_gid_groupinfo(filp->f_cred->group_info, + gid_min, gid_max)) + return 1; + + return 0; +} + static bool owner_mt(const struct sk_buff *skb, struct xt_action_param *par) { @@ -60,10 +115,7 @@ } if (info->match & XT_OWNER_GID) { - kgid_t gid_min = make_kgid(&init_user_ns, info->gid_min); - kgid_t gid_max = make_kgid(&init_user_ns, info->gid_max); - if ((gid_gte(filp->f_cred->fsgid, gid_min) && - gid_lte(filp->f_cred->fsgid, gid_max)) ^ + if (owner_match_gid(filp, info) ^ !(info->invert & XT_OWNER_GID)) return false; } diff -ruw linux-4.4.115/net/netlink/af_netlink.c linux-4.4.115-fbx/net/netlink/af_netlink.c --- linux-4.4.115/net/netlink/af_netlink.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/net/netlink/af_netlink.c 2019-10-29 09:26:25.945225706 +0100 @@ -365,15 +365,6 @@ static void netlink_sock_destruct(struct sock *sk) { - struct netlink_sock *nlk = nlk_sk(sk); - - if (nlk->cb_running) { - if (nlk->cb.done) - nlk->cb.done(&nlk->cb); - module_put(nlk->cb.module); - kfree_skb(nlk->cb.skb); - } - skb_queue_purge(&sk->sk_receive_queue); if (!sock_flag(sk, SOCK_DEAD)) { @@ -386,14 +377,6 @@ WARN_ON(nlk_sk(sk)->groups); } -static void netlink_sock_destruct_work(struct work_struct *work) -{ - struct netlink_sock *nlk = container_of(work, struct netlink_sock, - work); - - sk_free(&nlk->sk); -} - /* This lock without WQ_FLAG_EXCLUSIVE is good on UP and it is _very_ bad on * SMP. Look, when several writers sleep and reader wakes them up, all but one * immediately hit write lock and grab all the cpus. Exclusive sleep solves @@ -504,8 +487,9 @@ rcu_read_lock(); sk = __netlink_lookup(table, portid, net); - if (sk) - sock_hold(sk); + if (sk && !atomic_inc_not_zero(&sk->sk_refcnt)) + sk = NULL; + rcu_read_unlock(); return sk; @@ -632,6 +616,7 @@ } init_waitqueue_head(&nlk->wait); + sock_set_flag(sk, SOCK_RCU_FREE); sk->sk_destruct = netlink_sock_destruct; sk->sk_protocol = protocol; return 0; @@ -696,23 +681,6 @@ goto out; } -static void deferred_put_nlk_sk(struct rcu_head *head) -{ - struct netlink_sock *nlk = container_of(head, struct netlink_sock, rcu); - struct sock *sk = &nlk->sk; - - if (!atomic_dec_and_test(&sk->sk_refcnt)) - return; - - if (nlk->cb_running && nlk->cb.done) { - INIT_WORK(&nlk->work, netlink_sock_destruct_work); - schedule_work(&nlk->work); - return; - } - - sk_free(sk); -} - static int netlink_release(struct socket *sock) { struct sock *sk = sock->sk; @@ -785,7 +753,19 @@ local_bh_disable(); sock_prot_inuse_add(sock_net(sk), &netlink_proto, -1); local_bh_enable(); - call_rcu(&nlk->rcu, deferred_put_nlk_sk); + if (nlk->cb_running) { + mutex_lock(nlk->cb_mutex); + if (nlk->cb_running) { + if (nlk->cb.done) + nlk->cb.done(&nlk->cb); + + module_put(nlk->cb.module); + kfree_skb(nlk->cb.skb); + nlk->cb_running = false; + } + mutex_unlock(nlk->cb_mutex); + } + sock_put(sk); return 0; } diff -ruw linux-4.4.115/net/netlink/af_netlink.h linux-4.4.115-fbx/net/netlink/af_netlink.h --- linux-4.4.115/net/netlink/af_netlink.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/net/netlink/af_netlink.h 2019-01-22 16:16:29.151297552 +0100 @@ -48,7 +48,6 @@ struct module *module; struct rhash_head node; - struct rcu_head rcu; struct work_struct work; }; diff -ruw linux-4.4.115/net/netlink/genetlink.c linux-4.4.115-fbx/net/netlink/genetlink.c --- linux-4.4.115/net/netlink/genetlink.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/net/netlink/genetlink.c 2019-10-29 09:26:25.949225745 +0100 @@ -1009,7 +1009,7 @@ static int genl_bind(struct net *net, int group) { - int i, err = -ENOENT; + int i, err = 0; down_read(&cb_lock); for (i = 0; i < GENL_FAM_TAB_SIZE; i++) { diff -ruw linux-4.4.115/net/packet/af_packet.c linux-4.4.115-fbx/net/packet/af_packet.c --- linux-4.4.115/net/packet/af_packet.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/net/packet/af_packet.c 2019-10-29 09:26:25.953225784 +0100 @@ -1689,7 +1689,7 @@ match->flags = flags; INIT_LIST_HEAD(&match->list); spin_lock_init(&match->lock); - atomic_set(&match->sk_ref, 0); + refcount_set(&match->sk_ref, 0); fanout_init_data(match); match->prot_hook.type = po->prot_hook.type; match->prot_hook.dev = po->prot_hook.dev; @@ -1706,19 +1706,19 @@ match->prot_hook.type == po->prot_hook.type && match->prot_hook.dev == po->prot_hook.dev) { err = -ENOSPC; - if (atomic_read(&match->sk_ref) < PACKET_FANOUT_MAX) { + if (refcount_read(&match->sk_ref) < PACKET_FANOUT_MAX) { __dev_remove_pack(&po->prot_hook); po->fanout = match; po->rollover = rollover; rollover = NULL; - atomic_inc(&match->sk_ref); + refcount_set(&match->sk_ref, refcount_read(&match->sk_ref) + 1); __fanout_link(sk, po); err = 0; } } spin_unlock(&po->bind_lock); - if (err && !atomic_read(&match->sk_ref)) { + if (err && !refcount_read(&match->sk_ref)) { list_del(&match->list); kfree(match); } @@ -1744,7 +1744,7 @@ if (f) { po->fanout = NULL; - if (atomic_dec_and_test(&f->sk_ref)) + if (refcount_dec_and_test(&f->sk_ref)) list_del(&f->list); else f = NULL; diff -ruw linux-4.4.115/net/packet/internal.h linux-4.4.115-fbx/net/packet/internal.h --- linux-4.4.115/net/packet/internal.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/net/packet/internal.h 2019-10-29 09:26:25.953225784 +0100 @@ -1,6 +1,8 @@ #ifndef __PACKET_INTERNAL_H__ #define __PACKET_INTERNAL_H__ +#include + struct packet_mclist { struct packet_mclist *next; int ifindex; @@ -86,7 +88,7 @@ struct list_head list; struct sock *arr[PACKET_FANOUT_MAX]; spinlock_t lock; - atomic_t sk_ref; + refcount_t sk_ref; struct packet_type prot_hook ____cacheline_aligned_in_smp; }; diff -ruw linux-4.4.115/net/rfkill/core.c linux-4.4.115-fbx/net/rfkill/core.c --- linux-4.4.115/net/rfkill/core.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/net/rfkill/core.c 2019-01-22 16:16:29.175297770 +0100 @@ -802,8 +802,7 @@ } EXPORT_SYMBOL(rfkill_resume_polling); -#ifdef CONFIG_PM_SLEEP -static int rfkill_suspend(struct device *dev) +static __maybe_unused int rfkill_suspend(struct device *dev) { struct rfkill *rfkill = to_rfkill(dev); @@ -812,7 +811,7 @@ return 0; } -static int rfkill_resume(struct device *dev) +static __maybe_unused int rfkill_resume(struct device *dev) { struct rfkill *rfkill = to_rfkill(dev); bool cur; @@ -828,17 +827,13 @@ } static SIMPLE_DEV_PM_OPS(rfkill_pm_ops, rfkill_suspend, rfkill_resume); -#define RFKILL_PM_OPS (&rfkill_pm_ops) -#else -#define RFKILL_PM_OPS NULL -#endif static struct class rfkill_class = { .name = "rfkill", .dev_release = rfkill_release, .dev_groups = rfkill_dev_groups, .dev_uevent = rfkill_dev_uevent, - .pm = RFKILL_PM_OPS, + .pm = IS_ENABLED(CONFIG_RFKILL_PM) ? &rfkill_pm_ops : NULL, }; bool rfkill_blocked(struct rfkill *rfkill) diff -ruw linux-4.4.115/net/rfkill/Kconfig linux-4.4.115-fbx/net/rfkill/Kconfig --- linux-4.4.115/net/rfkill/Kconfig 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/net/rfkill/Kconfig 2019-01-22 16:16:29.171297734 +0100 @@ -10,6 +10,11 @@ To compile this driver as a module, choose M here: the module will be called rfkill. +config RFKILL_PM + bool "Power off on suspend" + depends on RFKILL && PM + default y + # LED trigger support config RFKILL_LEDS bool diff -ruw linux-4.4.115/net/socket.c linux-4.4.115-fbx/net/socket.c --- linux-4.4.115/net/socket.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/net/socket.c 2019-10-29 09:26:25.985226097 +0100 @@ -89,6 +89,8 @@ #include #include #include +#include +#include #include #include @@ -115,6 +117,9 @@ static ssize_t sock_read_iter(struct kiocb *iocb, struct iov_iter *to); static ssize_t sock_write_iter(struct kiocb *iocb, struct iov_iter *from); + +static BLOCKING_NOTIFIER_HEAD(sockev_notifier_list); + static int sock_mmap(struct file *file, struct vm_area_struct *vma); static int sock_close(struct inode *inode, struct file *file); @@ -169,6 +174,14 @@ static DEFINE_PER_CPU(int, sockets_in_use); /* + * Socket Event framework helpers + */ +static void sockev_notify(unsigned long event, struct socket *sk) +{ + blocking_notifier_call_chain(&sockev_notifier_list, event, sk); +} + +/** * Support routines. * Move socket addresses back and forth across the kernel/user * divide and look after the messy bits. @@ -520,9 +533,23 @@ return used; } +static int sockfs_setattr(struct dentry *dentry, struct iattr *iattr) +{ + int err = simple_setattr(dentry, iattr); + + if (!err && (iattr->ia_valid & ATTR_UID)) { + struct socket *sock = SOCKET_I(d_inode(dentry)); + + sock->sk->sk_uid = iattr->ia_uid; + } + + return err; +} + static const struct inode_operations sockfs_inode_ops = { .getxattr = sockfs_getxattr, .listxattr = sockfs_listxattr, + .setattr = sockfs_setattr, }; /** @@ -1234,6 +1261,9 @@ if (retval < 0) goto out; + if (retval == 0) + sockev_notify(SOCKEV_SOCKET, sock); + retval = sock_map_fd(sock, flags & (O_CLOEXEC | O_NONBLOCK)); if (retval < 0) goto out_release; @@ -1378,6 +1408,13 @@ (struct sockaddr *) &address, addrlen); } + if (!err) { + if (sock->sk) + sock_hold(sock->sk); + sockev_notify(SOCKEV_BIND, sock); + if (sock->sk) + sock_put(sock->sk); + } fput_light(sock->file, fput_needed); } return err; @@ -1405,6 +1442,13 @@ if (!err) err = sock->ops->listen(sock, backlog); + if (!err) { + if (sock->sk) + sock_hold(sock->sk); + sockev_notify(SOCKEV_LISTEN, sock); + if (sock->sk) + sock_put(sock->sk); + } fput_light(sock->file, fput_needed); } return err; @@ -1492,7 +1536,8 @@ fd_install(newfd, newfile); err = newfd; - + if (!err) + sockev_notify(SOCKEV_ACCEPT, sock); out_put: fput_light(sock->file, fput_needed); out: @@ -1542,6 +1587,8 @@ err = sock->ops->connect(sock, (struct sockaddr *)&address, addrlen, sock->file->f_flags); + if (!err) + sockev_notify(SOCKEV_CONNECT, sock); out_put: fput_light(sock->file, fput_needed); out: @@ -1627,6 +1674,13 @@ struct iovec iov; int fput_needed; + seemp_logk_sendto(fd, buff, len, flags, addr, addr_len); + + if (len > INT_MAX) + len = INT_MAX; + if (unlikely(!access_ok(VERIFY_READ, buff, len))) + return -EFAULT; + err = import_single_range(WRITE, buff, len, &iov, &msg.msg_iter); if (unlikely(err)) return err; @@ -1683,9 +1737,14 @@ int err, err2; int fput_needed; + if (size > INT_MAX) + size = INT_MAX; + if (unlikely(!access_ok(VERIFY_WRITE, ubuf, size))) + return -EFAULT; err = import_single_range(READ, ubuf, size, &iov, &msg.msg_iter); if (unlikely(err)) return err; + sock = sockfd_lookup_light(fd, &err, &fput_needed); if (!sock) goto out; @@ -1800,6 +1859,7 @@ sock = sockfd_lookup_light(fd, &err, &fput_needed); if (sock != NULL) { + sockev_notify(SOCKEV_SHUTDOWN, sock); err = security_socket_shutdown(sock, how); if (!err) err = sock->ops->shutdown(sock, how); @@ -3308,3 +3368,15 @@ return sock->ops->shutdown(sock, how); } EXPORT_SYMBOL(kernel_sock_shutdown); + +int sockev_register_notify(struct notifier_block *nb) +{ + return blocking_notifier_chain_register(&sockev_notifier_list, nb); +} +EXPORT_SYMBOL(sockev_register_notify); + +int sockev_unregister_notify(struct notifier_block *nb) +{ + return blocking_notifier_chain_unregister(&sockev_notifier_list, nb); +} +EXPORT_SYMBOL(sockev_unregister_notify); diff -ruw linux-4.4.115/net/unix/af_unix.c linux-4.4.115-fbx/net/unix/af_unix.c --- linux-4.4.115/net/unix/af_unix.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/net/unix/af_unix.c 2019-10-29 09:26:25.997226215 +0100 @@ -991,7 +991,7 @@ struct sockaddr_un *sunaddr = (struct sockaddr_un *)uaddr; char *sun_path = sunaddr->sun_path; int err; - unsigned int hash; + unsigned int hash = 0; struct unix_address *addr; struct hlist_head *list; struct path path = { NULL, NULL }; diff -ruw linux-4.4.115/net/wireless/ap.c linux-4.4.115-fbx/net/wireless/ap.c --- linux-4.4.115/net/wireless/ap.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/net/wireless/ap.c 2019-01-22 16:16:29.239298349 +0100 @@ -25,13 +25,18 @@ return -ENOENT; err = rdev_stop_ap(rdev, dev); - if (!err) { wdev->beacon_interval = 0; + if (!err) { memset(&wdev->chandef, 0, sizeof(wdev->chandef)); wdev->ssid_len = 0; rdev_set_qos_map(rdev, dev, NULL); if (notify) nl80211_send_ap_stopped(wdev); + + /* Should we apply the grace period during beaconing interface + * shutdown also? + */ + cfg80211_sched_dfs_chan_update(rdev); } return err; diff -ruw linux-4.4.115/net/wireless/chan.c linux-4.4.115-fbx/net/wireless/chan.c --- linux-4.4.115/net/wireless/chan.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/net/wireless/chan.c 2019-01-22 16:16:29.239298349 +0100 @@ -319,7 +319,8 @@ if (!c) return -EINVAL; - if (c->flags & IEEE80211_CHAN_RADAR) + if ((c->flags & IEEE80211_CHAN_RADAR) && + !(wiphy->flags & WIPHY_FLAG_DFS_OFFLOAD)) return 1; } return 0; @@ -455,6 +456,105 @@ return (r1 + r2 > 0); } +/* + * Checks if center frequency of chan falls with in the bandwidth + * range of chandef. + */ +bool cfg80211_is_sub_chan(struct cfg80211_chan_def *chandef, + struct ieee80211_channel *chan) +{ + int width; + u32 cf_offset, freq; + + if (chandef->chan->center_freq == chan->center_freq) + return true; + + width = cfg80211_chandef_get_width(chandef); + if (width <= 20) + return false; + + cf_offset = width / 2 - 10; + + for (freq = chandef->center_freq1 - width / 2 + 10; + freq <= chandef->center_freq1 + width / 2 - 10; freq += 20) { + if (chan->center_freq == freq) + return true; + } + + if (!chandef->center_freq2) + return false; + + for (freq = chandef->center_freq2 - width / 2 + 10; + freq <= chandef->center_freq2 + width / 2 - 10; freq += 20) { + if (chan->center_freq == freq) + return true; + } + + return false; +} + +bool cfg80211_beaconing_iface_active(struct wireless_dev *wdev) +{ + bool active = false; + + ASSERT_WDEV_LOCK(wdev); + + if (!wdev->chandef.chan) + return false; + + switch (wdev->iftype) { + case NL80211_IFTYPE_AP: + case NL80211_IFTYPE_P2P_GO: + active = wdev->beacon_interval != 0; + break; + case NL80211_IFTYPE_ADHOC: + active = wdev->ssid_len != 0; + break; + case NL80211_IFTYPE_MESH_POINT: + active = wdev->mesh_id_len != 0; + break; + case NL80211_IFTYPE_STATION: + case NL80211_IFTYPE_OCB: + case NL80211_IFTYPE_P2P_CLIENT: + case NL80211_IFTYPE_MONITOR: + case NL80211_IFTYPE_AP_VLAN: + case NL80211_IFTYPE_WDS: + case NL80211_IFTYPE_P2P_DEVICE: + break; + case NL80211_IFTYPE_UNSPECIFIED: + case NUM_NL80211_IFTYPES: + WARN_ON(1); + } + + return active; +} + +bool cfg80211_any_wiphy_oper_chan(struct wiphy *wiphy, + struct ieee80211_channel *chan) +{ + struct wireless_dev *wdev; + + ASSERT_RTNL(); + + if (!(chan->flags & IEEE80211_CHAN_RADAR)) + return false; + + list_for_each_entry(wdev, &wiphy->wdev_list, list) { + wdev_lock(wdev); + if (!cfg80211_beaconing_iface_active(wdev)) { + wdev_unlock(wdev); + continue; + } + + if (cfg80211_is_sub_chan(&wdev->chandef, chan)) { + wdev_unlock(wdev); + return true; + } + wdev_unlock(wdev); + } + + return false; +} static bool cfg80211_get_chans_dfs_available(struct wiphy *wiphy, u32 center_freq, @@ -479,7 +579,9 @@ if (c->flags & IEEE80211_CHAN_DISABLED) return false; - if ((c->flags & IEEE80211_CHAN_RADAR) && + /* check for radar flags */ + if ((!(wiphy->flags & WIPHY_FLAG_DFS_OFFLOAD)) && + (c->flags & IEEE80211_CHAN_RADAR) && (c->dfs_state != NL80211_DFS_AVAILABLE)) return false; } @@ -590,10 +692,17 @@ for (freq = start_freq; freq <= end_freq; freq += 20) { c = ieee80211_get_channel(wiphy, freq); - if (!c || c->flags & prohibited_flags) + + if (!c) return false; - } + if ((!(wiphy->flags & WIPHY_FLAG_DFS_OFFLOAD)) && + (c->flags & prohibited_flags & IEEE80211_CHAN_RADAR)) + return false; + + if (c->flags & prohibited_flags & ~IEEE80211_CHAN_RADAR) + return false; + } return true; } @@ -739,7 +848,7 @@ * and thus fail the GO instantiation, consider only the interfaces of * the current registered device. */ - list_for_each_entry(wdev, &rdev->wdev_list, list) { + list_for_each_entry(wdev, &rdev->wiphy.wdev_list, list) { struct ieee80211_channel *other_chan = NULL; int r1, r2; diff -ruw linux-4.4.115/net/wireless/core.c linux-4.4.115-fbx/net/wireless/core.c --- linux-4.4.115/net/wireless/core.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/net/wireless/core.c 2019-10-29 09:26:26.001226254 +0100 @@ -3,6 +3,7 @@ * * Copyright 2006-2010 Johannes Berg * Copyright 2013-2014 Intel Mobile Communications GmbH + * Copyright 2015 Intel Deutschland GmbH */ #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt @@ -157,7 +158,7 @@ if (!(rdev->wiphy.flags & WIPHY_FLAG_NETNS_OK)) return -EOPNOTSUPP; - list_for_each_entry(wdev, &rdev->wdev_list, list) { + list_for_each_entry(wdev, &rdev->wiphy.wdev_list, list) { if (!wdev->netdev) continue; wdev->netdev->features &= ~NETIF_F_NETNS_LOCAL; @@ -171,7 +172,8 @@ /* failed -- clean up to old netns */ net = wiphy_net(&rdev->wiphy); - list_for_each_entry_continue_reverse(wdev, &rdev->wdev_list, + list_for_each_entry_continue_reverse(wdev, + &rdev->wiphy.wdev_list, list) { if (!wdev->netdev) continue; @@ -230,7 +232,7 @@ ASSERT_RTNL(); - list_for_each_entry(wdev, &rdev->wdev_list, list) { + list_for_each_entry(wdev, &rdev->wiphy.wdev_list, list) { if (wdev->netdev) { dev_close(wdev->netdev); continue; @@ -298,7 +300,8 @@ kfree(item); spin_unlock_irq(&rdev->destroy_list_lock); - list_for_each_entry_safe(wdev, tmp, &rdev->wdev_list, list) { + list_for_each_entry_safe(wdev, tmp, + &rdev->wiphy.wdev_list, list) { if (nlportid == wdev->owner_nlportid) rdev_del_virtual_intf(rdev, wdev); } @@ -400,7 +403,7 @@ dev_set_name(&rdev->wiphy.dev, PHY_NAME "%d", rdev->wiphy_idx); } - INIT_LIST_HEAD(&rdev->wdev_list); + INIT_LIST_HEAD(&rdev->wiphy.wdev_list); INIT_LIST_HEAD(&rdev->beacon_registrations); spin_lock_init(&rdev->beacon_registrations_lock); spin_lock_init(&rdev->bss_lock); @@ -616,6 +619,13 @@ !rdev->ops->set_mac_acl))) return -EINVAL; + /* assure only valid behaviours are flagged by driver + * hence subtract 2 as bit 0 is invalid. + */ + if (WARN_ON(wiphy->bss_select_support && + (wiphy->bss_select_support & ~(BIT(__NL80211_BSS_SELECT_ATTR_AFTER_LAST) - 2)))) + return -EINVAL; + if (wiphy->addresses) memcpy(wiphy->perm_addr, wiphy->addresses[0].addr, ETH_ALEN); @@ -730,6 +740,36 @@ nl80211_send_reg_change_event(&request); } + /* Check that nobody globally advertises any capabilities they do not + * advertise on all possible interface types. + */ + if (wiphy->extended_capabilities_len && + wiphy->num_iftype_ext_capab && + wiphy->iftype_ext_capab) { + u8 supported_on_all, j; + const struct wiphy_iftype_ext_capab *capab; + + capab = wiphy->iftype_ext_capab; + for (j = 0; j < wiphy->extended_capabilities_len; j++) { + if (capab[0].extended_capabilities_len > j) + supported_on_all = + capab[0].extended_capabilities[j]; + else + supported_on_all = 0x00; + for (i = 1; i < wiphy->num_iftype_ext_capab; i++) { + if (j >= capab[i].extended_capabilities_len) { + supported_on_all = 0x00; + break; + } + supported_on_all &= + capab[i].extended_capabilities[j]; + } + if (WARN_ON(wiphy->extended_capabilities[j] & + ~supported_on_all)) + break; + } + } + rdev->wiphy.registered = true; rtnl_unlock(); @@ -782,7 +822,7 @@ nl80211_notify_wiphy(rdev, NL80211_CMD_DEL_WIPHY); rdev->wiphy.registered = false; - WARN_ON(!list_empty(&rdev->wdev_list)); + WARN_ON(!list_empty(&rdev->wiphy.wdev_list)); /* * First remove the hardware from everywhere, this makes @@ -905,7 +945,6 @@ sched_scan_req = rtnl_dereference(rdev->sched_scan_req); if (sched_scan_req && dev == sched_scan_req->dev) __cfg80211_stop_sched_scan(rdev, false); - #ifdef CONFIG_CFG80211_WEXT kfree(wdev->wext.ie); wdev->wext.ie = NULL; @@ -914,6 +953,7 @@ #endif cfg80211_disconnect(rdev, dev, WLAN_REASON_DEAUTH_LEAVING, true); + cfg80211_mlme_down(rdev, dev); break; case NL80211_IFTYPE_MESH_POINT: __cfg80211_leave_mesh(rdev, dev); @@ -940,6 +980,7 @@ /* invalid */ break; } + wdev->beacon_interval = 0; } void cfg80211_leave(struct cfg80211_registered_device *rdev, @@ -1004,7 +1045,7 @@ spin_lock_init(&wdev->mgmt_registrations_lock); wdev->identifier = ++rdev->wdev_id; - list_add_rcu(&wdev->list, &rdev->wdev_list); + list_add_rcu(&wdev->list, &rdev->wiphy.wdev_list); rdev->devlist_generation++; /* can only change netns with wiphy */ dev->features |= NETIF_F_NETNS_LOCAL; diff -ruw linux-4.4.115/net/wireless/core.h linux-4.4.115-fbx/net/wireless/core.h --- linux-4.4.115/net/wireless/core.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/net/wireless/core.h 2019-10-29 09:26:26.001226254 +0100 @@ -50,8 +50,7 @@ /* wiphy index, internal only */ int wiphy_idx; - /* associated wireless interfaces, protected by rtnl or RCU */ - struct list_head wdev_list; + /* protected by RTNL */ int devlist_generation, wdev_id; int opencount; /* also protected by devlist_mtx */ wait_queue_head_t dev_wait; @@ -209,14 +208,7 @@ enum cfg80211_event_type type; union { - struct { - u8 bssid[ETH_ALEN]; - const u8 *req_ie; - const u8 *resp_ie; - size_t req_ie_len; - size_t resp_ie_len; - u16 status; - } cr; + struct cfg80211_connect_resp_params cr; struct { const u8 *req_ie; const u8 *resp_ie; @@ -334,7 +326,7 @@ const u8 *ssid, int ssid_len, const u8 *ie, int ie_len, const u8 *key, int key_len, int key_idx, - const u8 *sae_data, int sae_data_len); + const u8 *auth_data, int auth_data_len); int cfg80211_mlme_assoc(struct cfg80211_registered_device *rdev, struct net_device *dev, struct ieee80211_channel *chan, @@ -372,11 +364,9 @@ struct cfg80211_connect_params *connect, struct cfg80211_cached_keys *connkeys, const u8 *prev_bssid); -void __cfg80211_connect_result(struct net_device *dev, const u8 *bssid, - const u8 *req_ie, size_t req_ie_len, - const u8 *resp_ie, size_t resp_ie_len, - u16 status, bool wextev, - struct cfg80211_bss *bss); +void __cfg80211_connect_result(struct net_device *dev, + struct cfg80211_connect_resp_params *params, + bool wextev); void __cfg80211_disconnected(struct net_device *dev, const u8 *ie, size_t ie_len, u16 reason, bool from_ap); int cfg80211_disconnect(struct cfg80211_registered_device *rdev, @@ -448,6 +438,16 @@ cfg80211_chandef_dfs_cac_time(struct wiphy *wiphy, const struct cfg80211_chan_def *chandef); +void cfg80211_sched_dfs_chan_update(struct cfg80211_registered_device *rdev); + +bool cfg80211_any_wiphy_oper_chan(struct wiphy *wiphy, + struct ieee80211_channel *chan); + +bool cfg80211_beaconing_iface_active(struct wireless_dev *wdev); + +bool cfg80211_is_sub_chan(struct cfg80211_chan_def *chandef, + struct ieee80211_channel *chan); + static inline unsigned int elapsed_jiffies_msecs(unsigned long start) { unsigned long end = jiffies; @@ -472,7 +472,7 @@ u32 *mask); int cfg80211_validate_beacon_int(struct cfg80211_registered_device *rdev, - u32 beacon_int); + enum nl80211_iftype iftype, u32 beacon_int); void cfg80211_update_iface_num(struct cfg80211_registered_device *rdev, enum nl80211_iftype iftype, int num); diff -ruw linux-4.4.115/net/wireless/db.txt linux-4.4.115-fbx/net/wireless/db.txt --- linux-4.4.115/net/wireless/db.txt 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/net/wireless/db.txt 2019-10-29 09:26:26.001226254 +0100 @@ -1,17 +1,1536 @@ -# -# This file is a placeholder to prevent accidental build breakage if someone -# enables CONFIG_CFG80211_INTERNAL_REGDB. Almost no one actually needs to -# enable that build option. -# -# You should be using CRDA instead. It is even better if you use the CRDA -# package provided by your distribution, since they will probably keep it -# up-to-date on your behalf. -# -# If you _really_ intend to use CONFIG_CFG80211_INTERNAL_REGDB then you will -# need to replace this file with one containing appropriately formatted -# regulatory rules that cover the regulatory domains you will be using. Your -# best option is to extract the db.txt file from the wireless-regdb git -# repository: -# -# git://git.kernel.org/pub/scm/linux/kernel/git/linville/wireless-regdb.git -# +# This is the world regulatory domain +country 00: + (2402 - 2472 @ 40), (20) + # Channel 12 - 13. + (2457 - 2482 @ 40), (20), PASSIVE-SCAN, NO-IBSS + # Channel 14. Only JP enables this and for 802.11b only + (2474 - 2494 @ 20), (20), PASSIVE-SCAN, NO-IBSS, NO-OFDM + # Channel 36 - 48 + (5170 - 5250 @ 80), (20), PASSIVE-SCAN, NO-IBSS + (5250 - 5330 @ 80), (20), PASSIVE-SCAN, NO-IBSS + (5490 - 5710 @ 80), (20), PASSIVE-SCAN, NO-IBSS + # NB: 5260 MHz - 5700 MHz requies DFS + # Channel 149 - 165 + (5735 - 5835 @ 80), (20), PASSIVE-SCAN, NO-IBSS + # IEEE 802.11ad (60GHz), channels 1..3 + (57240 - 63720 @ 2160), (0) + + +country AE: DFS-ETSI + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 80), (24), AUTO-BW + (5250 - 5330 @ 80), (24), DFS, AUTO-BW + (5490 - 5730 @ 160), (24), DFS + (5735 - 5835 @ 80), (30) + +country AF: DFS-ETSI + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 80), (23), AUTO-BW + (5250 - 5330 @ 80), (23), DFS, AUTO-BW + (5490 - 5710 @ 160), (30), DFS + +country AI: DFS-ETSI + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 80), (23), AUTO-BW + (5250 - 5330 @ 80), (23), DFS, AUTO-BW + (5490 - 5710 @ 160), (30), DFS + +country AL: DFS-ETSI + (2402 - 2482 @ 40), (20) + (5150 - 5250 @ 80), (23), AUTO-BW + (5250 - 5350 @ 80), (23), DFS, AUTO-BW + (5470 - 5710 @ 160), (30), DFS + +country AM: DFS-ETSI + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 20), (18) + (5250 - 5330 @ 20), (18), DFS + +country AN: DFS-ETSI + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 80), (23), AUTO-BW + (5250 - 5330 @ 80), (23), DFS, AUTO-BW + (5490 - 5710 @ 160), (30), DFS + +country AR: + (2402 - 2482 @ 40), (36) + (5170 - 5250 @ 80), (23), AUTO-BW + (5250 - 5330 @ 80), (36), AUTO-BW + (5490 - 5590 @ 80), (36) + (5650 - 5730 @ 80), (36) + (5735 - 5835 @ 80), (36) + # 60 gHz band channels 1-3 + (57240 - 63720 @ 2160), (40), NO-OUTDOOR + +country AS: DFS-FCC + (2402 - 2472 @ 40), (30) + (5170 - 5250 @ 80), (24), AUTO-BW + (5250 - 5330 @ 80), (24), DFS, AUTO-BW + (5490 - 5730 @ 160), (24), DFS + (5735 - 5850 @ 80), (30) + +country AT: DFS-ETSI + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 80), (23), AUTO-BW + (5250 - 5330 @ 80), (23), DFS, AUTO-BW + (5490 - 5710 @ 160), (30), DFS + # 5.9ghz band + # reference: http://www.etsi.org/deliver/etsi_en/302500_302599/302571/01.02.00_20/en_302571v010200a.pdf + (5850 - 5870 @ 10), (30) + (5860 - 5880 @ 10), (30) + (5870 - 5890 @ 10), (30) + (5880 - 5900 @ 10), (30) + (5890 - 5910 @ 10), (30) + (5900 - 5920 @ 10), (30) + (5910 - 5930 @ 10), (30) + # 60 gHz band channels 1-4, ref: Etsi En 302 567 + (57000 - 66000 @ 2160), (40) + +country AU: DFS-FCC + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 80), (24), AUTO-BW + (5250 - 5330 @ 80), (24), DFS, AUTO-BW + (5490 - 5590 @ 80), (24), DFS + (5650 - 5730 @ 80), (24), DFS + (5735 - 5835 @ 80), (30) + # 60 gHz band channels 1-4 + (57240 - 65880 @ 2160), (43), NO-OUTDOOR + +country AW: DFS-ETSI + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 80), (23), AUTO-BW + (5250 - 5330 @ 80), (23), DFS, AUTO-BW + (5490 - 5710 @ 160), (30), DFS + +country AZ: DFS-ETSI + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 80), (18), AUTO-BW + (5250 - 5330 @ 80), (18), DFS, AUTO-BW + +country BA: DFS-ETSI + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 80), (23), AUTO-BW + (5250 - 5330 @ 80), (23), DFS, AUTO-BW + (5490 - 5710 @ 160), (30), DFS + +country BB: DFS-FCC + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 80), (23), AUTO-BW + (5250 - 5330 @ 80), (23), DFS, AUTO-BW + (5735 - 5835 @ 80), (30) + +country BD: + (2402 - 2482 @ 40), (20) + (5735 - 5835 @ 80), (30) + +country BE: DFS-ETSI + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 80), (23), AUTO-BW + (5250 - 5330 @ 80), (23), DFS, AUTO-BW + (5490 - 5710 @ 160), (30), DFS + # 5.9ghz band + # reference: http://www.etsi.org/deliver/etsi_en/302500_302599/302571/01.02.00_20/en_302571v010200a.pdf + (5850 - 5870 @ 10), (30) + (5860 - 5880 @ 10), (30) + (5870 - 5890 @ 10), (30) + (5880 - 5900 @ 10), (30) + (5890 - 5910 @ 10), (30) + (5900 - 5920 @ 10), (30) + (5910 - 5930 @ 10), (30) + # 60 gHz band channels 1-4, ref: Etsi En 302 567 + (57000 - 66000 @ 2160), (40) + +country BF: DFS-FCC + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 80), (24), AUTO-BW + (5250 - 5330 @ 80), (24), DFS, AUTO-BW + (5490 - 5730 @ 160), (24), DFS + (5735 - 5835 @ 80), (30) + +country BG: DFS-ETSI + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 80), (23), AUTO-BW + (5250 - 5330 @ 80), (23), DFS, AUTO-BW + (5490 - 5710 @ 160), (30), DFS + # 5.9ghz band + # reference: http://www.etsi.org/deliver/etsi_en/302500_302599/302571/01.02.00_20/en_302571v010200a.pdf + (5850 - 5870 @ 10), (30) + (5860 - 5880 @ 10), (30) + (5870 - 5890 @ 10), (30) + (5880 - 5900 @ 10), (30) + (5890 - 5910 @ 10), (30) + (5900 - 5920 @ 10), (30) + (5910 - 5930 @ 10), (30) + # 60 gHz band channels 1-4, ref: Etsi En 302 567 + (57000 - 66000 @ 2160), (40) + +country BH: + (2402 - 2482 @ 40), (20) + (5170 - 5330 @ 20), (23) + (5735 - 5835 @ 20), (33) + +country BL: DFS-ETSI + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 80), (23), AUTO-BW + (5250 - 5330 @ 80), (23), DFS, AUTO-BW + (5490 - 5710 @ 160), (30), DFS + +country BM: DFS-FCC + (2402 - 2472 @ 40), (30) + (5170 - 5250 @ 80), (24), AUTO-BW + (5250 - 5330 @ 80), (24), DFS, AUTO-BW + (5490 - 5730 @ 160), (24), DFS + (5735 - 5835 @ 80), (30) + +country BN: DFS-ETSI + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 80), (20), AUTO-BW + (5250 - 5330 @ 80), (20), DFS, AUTO-BW + (5735 - 5835 @ 80), (20) + +country BO: DFS-ETSI + (2402 - 2482 @ 40), (20) + (5250 - 5330 @ 80), (30), DFS + (5735 - 5835 @ 80), (30) + # 60 gHz band channels 1-3, FCC + (57240 - 63720 @ 2160), (40) + +country BR: DFS-FCC + (2402 - 2482 @ 40), (30) + (5170 - 5250 @ 80), (24), AUTO-BW + (5250 - 5330 @ 80), (24), DFS, AUTO-BW + (5490 - 5730 @ 160), (24), DFS + (5735 - 5835 @ 80), (30) + # 60 gHz band channels 1-3 + (57240 - 63720 @ 2160), (40) + +country BS: DFS-FCC + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 80), (24), AUTO-BW + (5250 - 5330 @ 80), (24), DFS, AUTO-BW + (5490 - 5730 @ 160), (24), DFS + (5735 - 5835 @ 80), (30) + +country BT: DFS-ETSI + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 80), (23), AUTO-BW + (5250 - 5330 @ 80), (23), DFS, AUTO-BW + (5490 - 5710 @ 160), (30), DFS + +country BY: DFS-ETSI + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 80), (23), AUTO-BW + (5250 - 5330 @ 80), (23), DFS, AUTO-BW + (5490 - 5710 @ 160), (30), DFS + +country BZ: + (2402 - 2482 @ 40), (20) + (5170 - 5330 @ 160), (23) + (5490 - 5730 @ 160), (30) + (5735 - 5835 @ 80), (30) + +country CA: DFS-FCC + (2402 - 2472 @ 40), (30) + (5170 - 5250 @ 80), (24), AUTO-BW + (5250 - 5330 @ 80), (24), DFS, AUTO-BW + (5490 - 5730 @ 160), (24), DFS + (5735 - 5835 @ 80), (30) + # 60 gHz band channels 1-3 + (57240 - 63720 @ 2160), (40) + +country CF: DFS-FCC + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 40), (24) + (5250 - 5330 @ 40), (24), DFS + (5490 - 5730 @ 40), (24), DFS + (5735 - 5835 @ 40), (30) + +country CH: DFS-ETSI + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 80), (23), AUTO-BW + (5250 - 5330 @ 80), (23), DFS, AUTO-BW + (5490 - 5710 @ 160), (30), DFS + # 5.9ghz band + # reference: http://www.etsi.org/deliver/etsi_en/302500_302599/302571/01.02.00_20/en_302571v010200a.pdf + (5850 - 5870 @ 10), (30) + (5860 - 5880 @ 10), (30) + (5870 - 5890 @ 10), (30) + (5880 - 5900 @ 10), (30) + (5890 - 5910 @ 10), (30) + (5900 - 5920 @ 10), (30) + (5910 - 5930 @ 10), (30) + # 60 gHz band channels 1-4, ref: Etsi En 302 567 + (57000 - 66000 @ 2160), (40) + +country CI: DFS-FCC + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 80), (24), AUTO-BW + (5250 - 5330 @ 80), (24), DFS, AUTO-BW + (5490 - 5730 @ 160), (24), DFS + (5735 - 5835 @ 80), (30) + +country CL: + (2402 - 2482 @ 40), (20) + (5170 - 5330 @ 160), (20) + (5735 - 5835 @ 80), (20) + # 60 gHz band channels 1-3 + (57240 - 63720 @ 2160), (50), NO-OUTDOOR + +country CN: DFS-FCC + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 80), (23), AUTO-BW + (5250 - 5330 @ 80), (23), DFS, AUTO-BW + (5735 - 5835 @ 80), (33) + # 60 gHz band channels 2,3: 44dBm + (59400 - 63720 @ 2160), (44) + +country CO: DFS-FCC + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 80), (24), AUTO-BW + (5250 - 5330 @ 80), (24), DFS, AUTO-BW + (5490 - 5730 @ 160), (24), DFS + (5735 - 5835 @ 80), (30) + +country CR: DFS-FCC + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 20), (24) + (5250 - 5330 @ 20), (24), DFS + (5490 - 5730 @ 20), (24), DFS + (5735 - 5835 @ 20), (30) + # 60 gHz band channels 1-3 + (57240 - 63720 @ 2160), (30) + +country CX: DFS-FCC + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 80), (24), AUTO-BW + (5250 - 5330 @ 80), (24), DFS, AUTO-BW + (5490 - 5730 @ 160), (24), DFS + (5735 - 5835 @ 80), (30) + +country CY: DFS-ETSI + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 80), (23), AUTO-BW + (5250 - 5330 @ 80), (23), DFS, AUTO-BW + (5490 - 5710 @ 160), (30), DFS + # 5.9ghz band + # reference: http://www.etsi.org/deliver/etsi_en/302500_302599/302571/01.02.00_20/en_302571v010200a.pdf + (5850 - 5870 @ 10), (30) + (5860 - 5880 @ 10), (30) + (5870 - 5890 @ 10), (30) + (5880 - 5900 @ 10), (30) + (5890 - 5910 @ 10), (30) + (5900 - 5920 @ 10), (30) + (5910 - 5930 @ 10), (30) + # 60 gHz band channels 1-4, ref: Etsi En 302 567 + (57000 - 66000 @ 2160), (40) + +# Data from http://www.ctu.eu/164/download/VOR/VOR-12-08-2005-34.pdf +# and http://www.ctu.eu/164/download/VOR/VOR-12-05-2007-6-AN.pdf +country CZ: DFS-ETSI + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 80), (23), AUTO-BW + (5250 - 5330 @ 80), (23), DFS, AUTO-BW + (5490 - 5710 @ 160), (30), DFS + # 5.9ghz band + # reference: http://www.etsi.org/deliver/etsi_en/302500_302599/302571/01.02.00_20/en_302571v010200a.pdf + (5850 - 5870 @ 10), (30) + (5860 - 5880 @ 10), (30) + (5870 - 5890 @ 10), (30) + (5880 - 5900 @ 10), (30) + (5890 - 5910 @ 10), (30) + (5900 - 5920 @ 10), (30) + (5910 - 5930 @ 10), (30) + # 60 gHz band channels 1-4, ref: Etsi En 302 567 + (57000 - 66000 @ 2160), (40) + +# Data from "Frequenznutzungsplan" (as published in April 2008), downloaded from +# http://www.bundesnetzagentur.de/cae/servlet/contentblob/38448/publicationFile/2659/Frequenznutzungsplan2008_Id17448pdf.pdf +# For the 5GHz range also see +# http://www.bundesnetzagentur.de/cae/servlet/contentblob/38216/publicationFile/6579/WLAN5GHzVfg7_2010_28042010pdf.pdf + +country DE: DFS-ETSI + # entries 279004 and 280006 + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 80), (23), AUTO-BW + (5250 - 5330 @ 80), (23), DFS, AUTO-BW + (5490 - 5710 @ 160), (30), DFS + # 5.9ghz band + # reference: http://www.etsi.org/deliver/etsi_en/302500_302599/302571/01.02.00_20/en_302571v010200a.pdf + (5850 - 5870 @ 10), (30) + (5860 - 5880 @ 10), (30) + (5870 - 5890 @ 10), (30) + (5880 - 5900 @ 10), (30) + (5890 - 5910 @ 10), (30) + (5900 - 5920 @ 10), (30) + (5910 - 5930 @ 10), (30) + # 60 gHz band channels 1-4, ref: Etsi En 302 567 + (57000 - 66000 @ 2160), (40) + +country DK: DFS-ETSI + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 80), (23), AUTO-BW + (5250 - 5330 @ 80), (23), DFS, AUTO-BW + (5490 - 5710 @ 160), (30), DFS + # 5.9ghz band + # reference: http://www.etsi.org/deliver/etsi_en/302500_302599/302571/01.02.00_20/en_302571v010200a.pdf + (5850 - 5870 @ 10), (30) + (5860 - 5880 @ 10), (30) + (5870 - 5890 @ 10), (30) + (5880 - 5900 @ 10), (30) + (5890 - 5910 @ 10), (30) + (5900 - 5920 @ 10), (30) + (5910 - 5930 @ 10), (30) + # 60 gHz band channels 1-4, ref: Etsi En 302 567 + (57000 - 66000 @ 2160), (40) + +country DM: DFS-FCC + (2402 - 2472 @ 40), (30) + (5170 - 5250 @ 80), (23), AUTO-BW + (5250 - 5330 @ 80), (23), DFS, AUTO-BW + (5735 - 5835 @ 80), (30) + +country DO: DFS-FCC + (2402 - 2472 @ 40), (30) + (5170 - 5250 @ 80), (23), AUTO-BW + (5250 - 5330 @ 80), (23), DFS, AUTO-BW + (5735 - 5835 @ 80), (30) + +country DZ: DFS-ETSI + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 80), (23), AUTO-BW + (5250 - 5330 @ 80), (23), DFS, AUTO-BW + (5490 - 5670 @ 160), (23), DFS + +country EC: DFS-FCC + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 20), (24) + (5250 - 5330 @ 20), (24), DFS + (5490 - 5730 @ 20), (24), DFS + (5735 - 5835 @ 20), (30) + # 60 gHz band channels 1-3, FCC + (57240 - 63720 @ 2160), (40) + +country EE: DFS-ETSI + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 80), (23), AUTO-BW + (5250 - 5330 @ 80), (23), DFS, AUTO-BW + (5490 - 5710 @ 160), (30), DFS + # 5.9ghz band + # reference: http://www.etsi.org/deliver/etsi_en/302500_302599/302571/01.02.00_20/en_302571v010200a.pdf + (5850 - 5870 @ 10), (30) + (5860 - 5880 @ 10), (30) + (5870 - 5890 @ 10), (30) + (5880 - 5900 @ 10), (30) + (5890 - 5910 @ 10), (30) + (5900 - 5920 @ 10), (30) + (5910 - 5930 @ 10), (30) + # 60 gHz band channels 1-4, ref: Etsi En 302 567 + (57000 - 66000 @ 2160), (40) + +country EG: DFS-ETSI + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 40), (23) + (5250 - 5330 @ 40), (23), DFS + +country ES: DFS-ETSI + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 80), (23), AUTO-BW + (5250 - 5330 @ 80), (23), DFS, AUTO-BW + (5490 - 5710 @ 160), (30), DFS + # 5.9ghz band + # reference: http://www.etsi.org/deliver/etsi_en/302500_302599/302571/01.02.00_20/en_302571v010200a.pdf + (5850 - 5870 @ 10), (30) + (5860 - 5880 @ 10), (30) + (5870 - 5890 @ 10), (30) + (5880 - 5900 @ 10), (30) + (5890 - 5910 @ 10), (30) + (5900 - 5920 @ 10), (30) + (5910 - 5930 @ 10), (30) + # 60 gHz band channels 1-4, ref: Etsi En 302 567 + (57000 - 66000 @ 2160), (40) + +country ET: DFS-ETSI + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 80), (23), AUTO-BW + (5250 - 5330 @ 80), (23), DFS, AUTO-BW + (5490 - 5710 @ 160), (30), DFS + +country FI: DFS-ETSI + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 80), (23), AUTO-BW + (5250 - 5330 @ 80), (23), DFS, AUTO-BW + (5490 - 5710 @ 160), (30), DFS + # 5.9ghz band + # reference: http://www.etsi.org/deliver/etsi_en/302500_302599/302571/01.02.00_20/en_302571v010200a.pdf + (5850 - 5870 @ 10), (30) + (5860 - 5880 @ 10), (30) + (5870 - 5890 @ 10), (30) + (5880 - 5900 @ 10), (30) + (5890 - 5910 @ 10), (30) + (5900 - 5920 @ 10), (30) + (5910 - 5930 @ 10), (30) + # 60 gHz band channels 1-4, ref: Etsi En 302 567 + (57000 - 66000 @ 2160), (40) + +country FM: DFS-FCC + (2402 - 2472 @ 40), (30) + (5170 - 5250 @ 80), (24), AUTO-BW + (5250 - 5330 @ 80), (24), DFS, AUTO-BW + (5490 - 5730 @ 160), (24), DFS + (5735 - 5835 @ 80), (30) + +country FR: DFS-ETSI + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 80), (23), AUTO-BW + (5250 - 5330 @ 80), (23), DFS, AUTO-BW + (5490 - 5710 @ 160), (30), DFS + # 5.9ghz band + # reference: http://www.etsi.org/deliver/etsi_en/302500_302599/302571/01.02.00_20/en_302571v010200a.pdf + (5850 - 5870 @ 10), (30) + (5860 - 5880 @ 10), (30) + (5870 - 5890 @ 10), (30) + (5880 - 5900 @ 10), (30) + (5890 - 5910 @ 10), (30) + (5900 - 5920 @ 10), (30) + (5910 - 5930 @ 10), (30) + # 60 gHz band channels 1-4, ref: Etsi En 302 567 + (57000 - 66000 @ 2160), (40) + +country GB: DFS-ETSI + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 80), (23), AUTO-BW + (5250 - 5330 @ 80), (23), DFS, AUTO-BW + (5490 - 5710 @ 160), (30), DFS + # 5.9ghz band + # reference: http://www.etsi.org/deliver/etsi_en/302500_302599/302571/01.02.00_20/en_302571v010200a.pdf + (5850 - 5870 @ 10), (30) + (5860 - 5880 @ 10), (30) + (5870 - 5890 @ 10), (30) + (5880 - 5900 @ 10), (30) + (5890 - 5910 @ 10), (30) + (5900 - 5920 @ 10), (30) + (5910 - 5930 @ 10), (30) + # 60 gHz band channels 1-4, ref: Etsi En 302 567 + (57000 - 66000 @ 2160), (40) + +country GD: DFS-FCC + (2402 - 2472 @ 40), (30) + (5170 - 5250 @ 80), (24), AUTO-BW + (5250 - 5330 @ 80), (24), DFS, AUTO-BW + (5490 - 5730 @ 160), (24), DFS + (5735 - 5835 @ 80), (30) + +country GE: DFS-ETSI + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 80), (18), AUTO-BW + (5250 - 5330 @ 80), (18), DFS, AUTO-BW + +country GF: DFS-ETSI + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 80), (23), AUTO-BW + (5250 - 5330 @ 80), (23), DFS, AUTO-BW + (5490 - 5710 @ 160), (30), DFS + +country GH: DFS-FCC + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 80), (24), AUTO-BW + (5250 - 5330 @ 80), (24), DFS, AUTO-BW + (5490 - 5730 @ 160), (24), DFS + (5735 - 5835 @ 80), (30) + +country GI: DFS-ETSI + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 80), (23), AUTO-BW + (5250 - 5330 @ 80), (23), DFS, AUTO-BW + (5490 - 5710 @ 160), (30), DFS + +country GL: DFS-ETSI + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 80), (23), AUTO-BW + (5250 - 5330 @ 80), (23), DFS, AUTO-BW + (5490 - 5710 @ 160), (30), DFS + +country GP: DFS-ETSI + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 80), (23), AUTO-BW + (5250 - 5330 @ 80), (23), DFS, AUTO-BW + (5490 - 5710 @ 160), (30), DFS + +country GR: DFS-ETSI + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 80), (23), AUTO-BW + (5250 - 5330 @ 80), (23), DFS, AUTO-BW + (5490 - 5710 @ 160), (30), DFS + # 5.9ghz band + # reference: http://www.etsi.org/deliver/etsi_en/302500_302599/302571/01.02.00_20/en_302571v010200a.pdf + (5850 - 5870 @ 10), (30) + (5860 - 5880 @ 10), (30) + (5870 - 5890 @ 10), (30) + (5880 - 5900 @ 10), (30) + (5890 - 5910 @ 10), (30) + (5900 - 5920 @ 10), (30) + (5910 - 5930 @ 10), (30) + # 60 gHz band channels 1-4, ref: Etsi En 302 567 + (57000 - 66000 @ 2160), (40) + +country GT: DFS-ETSI + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 80), (23), AUTO-BW + (5250 - 5330 @ 80), (23), DFS, AUTO-BW + (5490 - 5710 @ 160), (30), DFS + +country GU: DFS-FCC + (2402 - 2472 @ 40), (30) + (5170 - 5250 @ 80), (24), AUTO-BW + (5250 - 5330 @ 80), (24), DFS, AUTO-BW + (5490 - 5730 @ 160), (24), DFS + (5735 - 5835 @ 80), (30) + # 60 gHz band channels 1-3, FCC + (57240 - 63720 @ 2160), (40) + +country GY: + (2402 - 2482 @ 40), (30) + (5735 - 5835 @ 80), (30) + +country HK: DFS-FCC + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 80), (24), AUTO-BW + (5250 - 5330 @ 80), (24), DFS, AUTO-BW + (5490 - 5730 @ 160), (24), DFS + (5735 - 5835 @ 80), (30) + # 60 gHz band channels 1-4, ref: FCC/EU + (57240 - 65880 @ 2160), (40) + +country HN: + (2402 - 2482 @ 40), (20) + (5170 - 5330 @ 160), (24) + (5490 - 5730 @ 160), (24) + (5735 - 5835 @ 80), (30) + # 60 gHz band channels 1-3, FCC + (57240 - 63720 @ 2160), (40) + +country HR: DFS-ETSI + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 80), (23), AUTO-BW + (5250 - 5330 @ 80), (23), DFS, AUTO-BW + (5490 - 5710 @ 160), (30), DFS + # 5.9ghz band + # reference: http://www.etsi.org/deliver/etsi_en/302500_302599/302571/01.02.00_20/en_302571v010200a.pdf + (5850 - 5870 @ 10), (30) + (5860 - 5880 @ 10), (30) + (5870 - 5890 @ 10), (30) + (5880 - 5900 @ 10), (30) + (5890 - 5910 @ 10), (30) + (5900 - 5920 @ 10), (30) + (5910 - 5930 @ 10), (30) + # 60 gHz band channels 1-4, ref: Etsi En 302 567 + (57000 - 66000 @ 2160), (40) + +country HT: DFS-FCC + (2402 - 2472 @ 40), (30) + (5170 - 5250 @ 80), (24), AUTO-BW + (5250 - 5330 @ 80), (24), DFS, AUTO-BW + (5490 - 5730 @ 160), (24), DFS + (5735 - 5835 @ 80), (30) + +country HU: DFS-ETSI + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 80), (23), AUTO-BW + (5250 - 5330 @ 80), (23), DFS, AUTO-BW + (5490 - 5710 @ 160), (30), DFS + # 5.9ghz band + # reference: http://www.etsi.org/deliver/etsi_en/302500_302599/302571/01.02.00_20/en_302571v010200a.pdf + (5850 - 5870 @ 10), (30) + (5860 - 5880 @ 10), (30) + (5870 - 5890 @ 10), (30) + (5880 - 5900 @ 10), (30) + (5890 - 5910 @ 10), (30) + (5900 - 5920 @ 10), (30) + (5910 - 5930 @ 10), (30) + # 60 gHz band channels 1-4, ref: Etsi En 302 567 + (57000 - 66000 @ 2160), (40) + +country ID: + # ref: http://www.postel.go.id/content/ID/regulasi/standardisasi/kepdir/bwa%205,8%20ghz.pdf + (2402 - 2482 @ 40), (30) + (5735 - 5815 @ 20), (30) + +country IE: DFS-ETSI + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 80), (23), AUTO-BW + (5250 - 5330 @ 80), (23), DFS, AUTO-BW + (5490 - 5710 @ 160), (30), DFS + # 5.9ghz band + # reference: http://www.etsi.org/deliver/etsi_en/302500_302599/302571/01.02.00_20/en_302571v010200a.pdf + (5850 - 5870 @ 10), (30) + (5860 - 5880 @ 10), (30) + (5870 - 5890 @ 10), (30) + (5880 - 5900 @ 10), (30) + (5890 - 5910 @ 10), (30) + (5900 - 5920 @ 10), (30) + (5910 - 5930 @ 10), (30) + # 60 gHz band channels 1-4, ref: Etsi En 302 567 + (57000 - 66000 @ 2160), (40) + +country IL: DFS-ETSI + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 80), (23), AUTO-BW + (5250 - 5330 @ 80), (23), DFS, AUTO-BW + # 60 gHz band channels 1-4, base on Etsi En 302 567 + (57000 - 66000 @ 2160), (40) + +country IN: + (2402 - 2482 @ 40), (20) + (5170 - 5330 @ 160), (23) + (5735 - 5835 @ 80), (33) + +country IQ: DFS-ETSI + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 80), (23), AUTO-BW + (5250 - 5330 @ 80), (23), DFS, AUTO-BW + (5490 - 5710 @ 160), (30), DFS + +country IS: DFS-ETSI + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 80), (23), AUTO-BW + (5250 - 5330 @ 80), (23), DFS, AUTO-BW + (5490 - 5710 @ 160), (30), DFS + # 5.9ghz band + # reference: http://www.etsi.org/deliver/etsi_en/302500_302599/302571/01.02.00_20/en_302571v010200a.pdf + (5850 - 5870 @ 10), (30) + (5860 - 5880 @ 10), (30) + (5870 - 5890 @ 10), (30) + (5880 - 5900 @ 10), (30) + (5890 - 5910 @ 10), (30) + (5900 - 5920 @ 10), (30) + (5910 - 5930 @ 10), (30) + # 60 gHz band channels 1-4, ref: Etsi En 302 567 + (57000 - 66000 @ 2160), (40) + +country IT: DFS-ETSI + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 80), (23), AUTO-BW + (5250 - 5330 @ 80), (23), DFS, AUTO-BW + (5490 - 5710 @ 160), (30), DFS + # 5.9ghz band + # reference: http://www.etsi.org/deliver/etsi_en/302500_302599/302571/01.02.00_20/en_302571v010200a.pdf + (5850 - 5870 @ 10), (30) + (5860 - 5880 @ 10), (30) + (5870 - 5890 @ 10), (30) + (5880 - 5900 @ 10), (30) + (5890 - 5910 @ 10), (30) + (5900 - 5920 @ 10), (30) + (5910 - 5930 @ 10), (30) + # 60 gHz band channels 1-4, ref: Etsi En 302 567 + (57000 - 66000 @ 2160), (40) + +country JM: DFS-FCC + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 80), (24), AUTO-BW + (5250 - 5330 @ 80), (24), DFS, AUTO-BW + (5490 - 5730 @ 160), (24), DFS + (5735 - 5835 @ 80), (30) + # 60 gHz band channels 1-3, FCC + (57240 - 63720 @ 2160), (40) + +country JO: + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 80), (23) + (5735 - 5835 @ 80), (23) + # 60 gHz band channels 1-4, ref: Etsi En 302 567 + (57000 - 66000 @ 2160), (40) + +country JP: DFS-JP + (2402 - 2482 @ 40), (20) + (5170 - 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5920 @ 10), (30) + (5910 - 5930 @ 10), (30) + # 60 gHz band channels 1-4, ref: Etsi En 302 567 + (57000 - 66000 @ 2160), (40) + +country LU: DFS-ETSI + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 80), (23), AUTO-BW + (5250 - 5330 @ 80), (23), DFS, AUTO-BW + (5490 - 5710 @ 160), (30), DFS + # 5.9ghz band + # reference: http://www.etsi.org/deliver/etsi_en/302500_302599/302571/01.02.00_20/en_302571v010200a.pdf + (5850 - 5870 @ 10), (30) + (5860 - 5880 @ 10), (30) + (5870 - 5890 @ 10), (30) + (5880 - 5900 @ 10), (30) + (5890 - 5910 @ 10), (30) + (5900 - 5920 @ 10), (30) + (5910 - 5930 @ 10), (30) + # 60 gHz band channels 1-4, ref: Etsi En 302 567 + (57000 - 66000 @ 2160), (40) + +country LV: DFS-ETSI + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 80), (23), AUTO-BW + (5250 - 5330 @ 80), (23), DFS, AUTO-BW + (5490 - 5710 @ 160), (30), DFS + # 5.9ghz band + # reference: http://www.etsi.org/deliver/etsi_en/302500_302599/302571/01.02.00_20/en_302571v010200a.pdf + (5850 - 5870 @ 10), (30) + (5860 - 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5330 @ 80), (23), DFS, AUTO-BW + (5490 - 5710 @ 160), (30), DFS + +country MH: DFS-FCC + (2402 - 2472 @ 40), (30) + (5170 - 5250 @ 80), (24), AUTO-BW + (5250 - 5330 @ 80), (24), DFS, AUTO-BW + (5490 - 5730 @ 160), (24), DFS + (5735 - 5835 @ 80), (30) + +country MK: DFS-ETSI + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 80), (23), AUTO-BW + (5250 - 5330 @ 80), (23), DFS, AUTO-BW + (5490 - 5710 @ 160), (30), DFS + +country MN: DFS-FCC + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 80), (24), AUTO-BW + (5250 - 5330 @ 80), (24), DFS, AUTO-BW + (5490 - 5730 @ 160), (24), DFS + (5735 - 5835 @ 80), (30) + +country MO: DFS-FCC + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 80), (24), AUTO-BW + (5250 - 5330 @ 80), (24), DFS, AUTO-BW + (5490 - 5730 @ 160), (24), DFS + (5735 - 5835 @ 80), (30) + +country MP: DFS-FCC + (2402 - 2472 @ 40), (30) + (5170 - 5250 @ 80), (24), AUTO-BW + (5250 - 5330 @ 80), (24), DFS, AUTO-BW + (5490 - 5730 @ 160), (24), DFS + (5735 - 5835 @ 80), (30) + +country MQ: DFS-ETSI + (2402 - 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5835 @ 80), (30) + +country MV: DFS-ETSI + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 80), (20), AUTO-BW + (5250 - 5330 @ 80), (20), DFS, AUTO-BW + (5735 - 5835 @ 80), (20) + +country MW: DFS-ETSI + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 80), (23), AUTO-BW + (5250 - 5330 @ 80), (23), DFS, AUTO-BW + (5490 - 5710 @ 160), (30), DFS + +country MX: DFS-FCC + (2402 - 2482 @ 40), (30) + (5170 - 5250 @ 80), (24), AUTO-BW + (5250 - 5330 @ 80), (24), DFS, AUTO-BW + (5490 - 5730 @ 160), (24), DFS + (5735 - 5835 @ 80), (30) + # 60 gHz band channels 1-3, FCC + (57240 - 63720 @ 2160), (40) + +country MY: DFS-FCC + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 80), (24), AUTO-BW + (5250 - 5330 @ 80), (24), DFS, AUTO-BW + (5490 - 5650 @ 160), (24), DFS + (5735 - 5835 @ 80), (24) + # 60 gHz band channels 1-3 + (57240 - 63720 @ 2160), (40) + +country NA: DFS-ETSI + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 80), (23), AUTO-BW + (5250 - 5330 @ 80), (23), DFS, AUTO-BW + (5490 - 5730 @ 160), (30), DFS + (5735 - 5835 @ 80), (33) + +country NG: DFS-ETSI + (2402 - 2482 @ 40), (20) + (5250 - 5330 @ 80), (30), DFS + (5735 - 5835 @ 80), (30) + +country NI: DFS-FCC + (2402 - 2472 @ 40), (30) + (5170 - 5250 @ 80), (24), AUTO-BW + (5250 - 5330 @ 80), (24), DFS, AUTO-BW + (5490 - 5730 @ 160), (24), DFS + (5735 - 5835 @ 80), (30) + # 60 gHz band channels 1-3, FCC + (57240 - 63720 @ 2160), (40) + +country NL: DFS-ETSI + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 80), (23), AUTO-BW + (5250 - 5330 @ 80), (23), DFS, AUTO-BW + (5490 - 5710 @ 160), (30), DFS + # 5.9ghz band + # reference: http://www.etsi.org/deliver/etsi_en/302500_302599/302571/01.02.00_20/en_302571v010200a.pdf + (5850 - 5870 @ 10), (30) + (5860 - 5880 @ 10), (30) + (5870 - 5890 @ 10), (30) + (5880 - 5900 @ 10), (30) + (5890 - 5910 @ 10), (30) + (5900 - 5920 @ 10), (30) + (5910 - 5930 @ 10), (30) + # 60 gHz band channels 1-4, ref: Etsi En 302 567 + (57000 - 66000 @ 2160), (40) + +country NO: DFS-ETSI + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 80), (23), AUTO-BW + (5250 - 5330 @ 80), (23), DFS, AUTO-BW + (5490 - 5710 @ 160), (30), DFS + # 5.9ghz band + # reference: http://www.etsi.org/deliver/etsi_en/302500_302599/302571/01.02.00_20/en_302571v010200a.pdf + (5850 - 5870 @ 10), (30) + (5860 - 5880 @ 10), (30) + (5870 - 5890 @ 10), (30) + (5880 - 5900 @ 10), (30) + (5890 - 5910 @ 10), (30) + (5900 - 5920 @ 10), (30) + (5910 - 5930 @ 10), (30) + # 60 gHz band channels 1-4, ref: Etsi En 302 567 + (57000 - 66000 @ 2160), (40) + +country NP: + (2402 - 2482 @ 40), (20) + (5170 - 5330 @ 160), (20) + (5735 - 5835 @ 80), (20) + +country NZ: DFS-FCC + (2402 - 2482 @ 40), (30) + (5170 - 5250 @ 80), (24), AUTO-BW + (5250 - 5330 @ 80), (24), DFS, AUTO-BW + (5490 - 5730 @ 160), (24), DFS + (5735 - 5835 @ 80), (30) + # 60 gHz band channels 1-4, ref: Etsi En 302 567 + (57000 - 66000 @ 2160), (40) + +country OM: DFS-ETSI + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 80), (23), AUTO-BW + (5250 - 5330 @ 80), (23), DFS, AUTO-BW + (5490 - 5710 @ 160), (30), DFS + +country PA: + (2402 - 2472 @ 40), (36) + (5170 - 5250 @ 80), (23), AUT0-BW + (5250 - 5330 @ 80), (30), AUTO-BW + (5735 - 5835 @ 80), (36) + +country PE: DFS-FCC + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 80), (24), AUTO-BW + (5250 - 5330 @ 80), (24), DFS, AUTO-BW + (5490 - 5730 @ 160), (24), DFS + (5735 - 5835 @ 80), (30) + +country PF: DFS-ETSI + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 80), (23), AUTO-BW + (5250 - 5330 @ 80), (23), DFS, AUTO-BW + (5490 - 5710 @ 160), (30), DFS + +country PG: DFS-FCC + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 80), (24), AUTO-BW + (5250 - 5330 @ 80), (24), DFS, AUTO-BW + (5490 - 5730 @ 160), (24), DFS + (5735 - 5835 @ 80), (30) + +country PH: DFS-FCC + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 80), (24), AUTO-BW + (5250 - 5330 @ 80), (24), DFS, AUTO-BW + (5490 - 5730 @ 160), (24), DFS + (5735 - 5835 @ 80), (30) + # 60 gHz band channels 1-4, ref: Etsi En 302 567 + (57000 - 66000 @ 2160), (40) + +country PK: + (2402 - 2482 @ 40), (30) + (5735 - 5835 @ 80), (30) + +country PL: DFS-ETSI + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 80), (23), AUTO-BW + (5250 - 5330 @ 80), (23), DFS, AUTO-BW + (5490 - 5710 @ 160), (30), DFS + # 5.9ghz band + # reference: http://www.etsi.org/deliver/etsi_en/302500_302599/302571/01.02.00_20/en_302571v010200a.pdf + (5850 - 5870 @ 10), (30) + (5860 - 5880 @ 10), (30) + (5870 - 5890 @ 10), (30) + (5880 - 5900 @ 10), (30) + (5890 - 5910 @ 10), (30) + (5900 - 5920 @ 10), (30) + (5910 - 5930 @ 10), (30) + # 60 gHz band channels 1-4, ref: Etsi En 302 567 + (57000 - 66000 @ 2160), (40) + +country PM: DFS-ETSI + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 80), (23), AUTO-BW + (5250 - 5330 @ 80), (23), DFS, AUTO-BW + (5490 - 5710 @ 160), (30), DFS + +country PR: DFS-FCC + (2402 - 2472 @ 40), (30) + (5170 - 5250 @ 80), (24), AUTO-BW + (5250 - 5330 @ 80), (24), DFS, AUTO-BW + (5490 - 5730 @ 160), (24), DFS + (5735 - 5835 @ 80), (30) + +# Public Safety FCCA, FCC4 +# 27dBm [4.9GHz 1/4 rate], 30dBm [1/2 rate], 33dBm [full rate], and 5GHz same as FCC1 +# db.txt cannot express the limitation on 5G so disable all 5G channels for FCC4 +country PS: DFS-FCC + (2402 - 2472 @ 40), (30) + (4940 - 4990 @ 40), (33) + +country PT: DFS-ETSI + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 80), (23), AUTO-BW + (5250 - 5330 @ 80), (23), DFS, AUTO-BW + (5490 - 5710 @ 160), (30), DFS + # 5.9ghz band + # reference: http://www.etsi.org/deliver/etsi_en/302500_302599/302571/01.02.00_20/en_302571v010200a.pdf + (5850 - 5870 @ 10), (30) + (5860 - 5880 @ 10), (30) + (5870 - 5890 @ 10), (30) + (5880 - 5900 @ 10), (30) + (5890 - 5910 @ 10), (30) + (5900 - 5920 @ 10), (30) + (5910 - 5930 @ 10), (30) + # 60 gHz band channels 1-4, ref: Etsi En 302 567 + (57000 - 66000 @ 2160), (40) + +country PW: DFS-FCC + (2402 - 2472 @ 40), (30) + (5170 - 5250 @ 80), (24), AUTO-BW + (5250 - 5330 @ 80), (24), DFS, AUTO-BW + (5490 - 5730 @ 160), (24), DFS + (5735 - 5835 @ 80), (30) + +country PY: DFS-FCC + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 80), (24), AUTO-BW + (5250 - 5330 @ 80), (24), DFS, AUTO-BW + (5490 - 5730 @ 160), (24), DFS + (5735 - 5835 @ 80), (30) + # 60 gHz band channels 1-3, FCC + (57240 - 63720 @ 2160), (40) + +country QA: + (2402 - 2482 @ 40), (20) + (5735 - 5835 @ 80), (30) + +country RE: DFS-ETSI + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 80), (23), AUTO-BW + (5250 - 5330 @ 80), (23), DFS, AUTO-BW + (5490 - 5710 @ 160), (30), DFS + +country RO: DFS-ETSI + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 80), (23), AUTO-BW + (5250 - 5330 @ 80), (23), DFS, AUTO-BW + (5490 - 5710 @ 160), (30), DFS + # 5.9ghz band + # reference: http://www.etsi.org/deliver/etsi_en/302500_302599/302571/01.02.00_20/en_302571v010200a.pdf + (5850 - 5870 @ 10), (30) + (5860 - 5880 @ 10), (30) + (5870 - 5890 @ 10), (30) + (5880 - 5900 @ 10), (30) + (5890 - 5910 @ 10), (30) + (5900 - 5920 @ 10), (30) + (5910 - 5930 @ 10), (30) + # 60 gHz band channels 1-4, ref: Etsi En 302 567 + (57000 - 66000 @ 2160), (40) + +# Source: +# http://www.ratel.rs/upload/documents/Plan_namene/Plan_namene-sl_glasnik.pdf +country RS: DFS-ETSI + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 80), (23), AUTO-BW + (5250 - 5330 @ 80), (23), DFS, AUTO-BW + (5490 - 5710 @ 160), (30), DFS + # 60 gHz band channels 1-4, ref: Etsi En 302 567 + (57000 - 66000 @ 2160), (40) + +country RU: + (2402 - 2482 @ 40), (20) + (5170 - 5330 @ 160), (23) + (5490 - 5730 @ 160), (30) + (5735 - 5835 @ 80), (30) + # 60 gHz band channels 1-4 + (57240 - 65880 @ 2160), (40) + +country RW: DFS-FCC + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 80), (24), AUTO-BW + (5250 - 5330 @ 80), (24), DFS, AUTO-BW + (5490 - 5730 @ 160), (24), DFS + (5735 - 5835 @ 80), (30) + +country SA: DFS-ETSI + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 80), (23), AUTO-BW + (5250 - 5330 @ 80), (23), DFS, AUTO-BW + (5490 - 5710 @ 160), (30), DFS + +country SE: DFS-ETSI + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 80), (23), AUTO-BW + (5250 - 5330 @ 80), (23), DFS, AUTO-BW + (5490 - 5710 @ 160), (30), DFS + # 5.9ghz band + # reference: http://www.etsi.org/deliver/etsi_en/302500_302599/302571/01.02.00_20/en_302571v010200a.pdf + (5850 - 5870 @ 10), (30) + (5860 - 5880 @ 10), (30) + (5870 - 5890 @ 10), (30) + (5880 - 5900 @ 10), (30) + (5890 - 5910 @ 10), (30) + (5900 - 5920 @ 10), (30) + (5910 - 5930 @ 10), (30) + # 60 gHz band channels 1-4, ref: Etsi En 302 567 + (57000 - 66000 @ 2160), (40) + +country SG: DFS-FCC + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 80), (24), AUTO-BW + (5250 - 5330 @ 80), (24), DFS, AUTO-BW + (5490 - 5730 @ 160), (24), DFS + (5735 - 5835 @ 80), (30) + # 60 gHz band channels 1-4, ref: Etsi En 302 567 + (57000 - 66000 @ 2160), (40), NO-OUTDOOR + +country SI: DFS-ETSI + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 80), (23), AUTO-BW + (5250 - 5330 @ 80), (23), DFS, AUTO-BW + (5490 - 5710 @ 160), (30), DFS + # 5.9ghz band + # reference: http://www.etsi.org/deliver/etsi_en/302500_302599/302571/01.02.00_20/en_302571v010200a.pdf + (5850 - 5870 @ 10), (30) + (5860 - 5880 @ 10), (30) + (5870 - 5890 @ 10), (30) + (5880 - 5900 @ 10), (30) + (5890 - 5910 @ 10), (30) + (5900 - 5920 @ 10), (30) + (5910 - 5930 @ 10), (30) + # 60 gHz band channels 1-4, ref: Etsi En 302 567 + (57000 - 66000 @ 2160), (40) + +country SK: DFS-ETSI + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 80), (23), AUTO-BW + (5250 - 5330 @ 80), (23), DFS, AUTO-BW + (5490 - 5710 @ 160), (30), DFS + # 5.9ghz band + # reference: http://www.etsi.org/deliver/etsi_en/302500_302599/302571/01.02.00_20/en_302571v010200a.pdf + (5850 - 5870 @ 10), (30) + (5860 - 5880 @ 10), (30) + (5870 - 5890 @ 10), (30) + (5880 - 5900 @ 10), (30) + (5890 - 5910 @ 10), (30) + (5900 - 5920 @ 10), (30) + (5910 - 5930 @ 10), (30) + # 60 gHz band channels 1-4, ref: Etsi En 302 567 + (57000 - 66000 @ 2160), (40) + +country SN: + (2402 - 2482 @ 40), (20) + (5170 - 5330 @ 160), (24) + (5490 - 5730 @ 160), (24) + (5735 - 5835 @ 80), (30) + +country SR: DFS-ETSI + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 80), (23), AUTO-BW + (5250 - 5330 @ 80), (23), DFS, AUTO-BW + (5490 - 5710 @ 160), (30), DFS + +country SV: DFS-FCC + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 20), (23) + (5250 - 5330 @ 20), (23), DFS + (5735 - 5835 @ 20), (30) + +country TC: DFS-FCC + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 80), (24), AUTO-BW + (5250 - 5330 @ 80), (24), DFS, AUTO-BW + (5490 - 5730 @ 160), (24), DFS + (5735 - 5835 @ 80), (30) + +country TD: DFS-ETSI + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 80), (23), AUTO-BW + (5250 - 5330 @ 80), (23), DFS, AUTO-BW + (5490 - 5710 @ 160), (30), DFS + +country TG: DFS-ETSI + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 40), (23) + (5250 - 5330 @ 40), (23), DFS + (5490 - 5710 @ 40), (30), DFS + +country TH: DFS-FCC + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 80), (24), AUTO-BW + (5250 - 5330 @ 80), (24), DFS, AUTO-BW + (5490 - 5730 @ 160), (24), DFS + (5735 - 5835 @ 80), (30) + # 60 gHz band channels 1-4 + (57240 - 65880 @ 2160), (40) + +country TN: DFS-ETSI + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 80), (23), AUTO-BW + (5250 - 5330 @ 80), (23), DFS, AUTO-BW + +country TR: DFS-ETSI + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 80), (23), AUTO-BW + (5250 - 5330 @ 80), (23), DFS, AUTO-BW + (5490 - 5710 @ 160), (30), DFS + +country TT: + (2402 - 2482 @ 40), (20) + (5170 - 5330 @ 160), (24) + (5490 - 5730 @ 160), (24) + (5735 - 5835 @ 80), (30) + # 60 gHz band channels 1-3, FCC + (57240 - 63720 @ 2160), (40) + +country TW: DFS-FCC + (2402 - 2472 @ 40), (30) + (5170 - 5250 @ 80), (24), AUTO-BW + (5250 - 5330 @ 80), (24), DFS, AUTO-BW + (5490 - 5730 @ 160), (24), DFS + (5735 - 5835 @ 80), (30) + # 60 gHz band channels 1-3, FCC + (57240 - 63720 @ 2160), (40) + +country TZ: + (2402 - 2482 @ 40), (20) + (5735 - 5835 @ 80), (30) + +# Source: +# #914 / 06 Sep 2007: http://www.ucrf.gov.ua/uk/doc/nkrz/1196068874 +# #1174 / 23 Oct 2008: http://www.nkrz.gov.ua/uk/activities/ruling/1225269361 +# (appendix 8) +# Listed 5GHz range is a lowest common denominator for all related +# rules in the referenced laws. Such a range is used because of +# disputable definitions there. +country UA: DFS-ETSI + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 80), (20), AUTO-BW + (5250 - 5330 @ 80), (20), DFS, AUTO-BW + (5490 - 5670 @ 160), (20), DFS + (5735 - 5835 @ 80), (20) + # 60 gHz band channels 1-4, ref: Etsi En 302 567 + (57240 - 65880 @ 2160), (20) + +country UG: DFS-FCC + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 80), (24), AUTO-BW + (5250 - 5330 @ 80), (24), DFS, AUTO-BW + (5490 - 5730 @ 160), (24), DFS + (5735 - 5835 @ 80), (30) + +country US: DFS-FCC + (2402 - 2472 @ 40), (30) + (5170 - 5250 @ 80), (30), AUTO-BW + (5250 - 5330 @ 80), (24), DFS, AUTO-BW + (5490 - 5730 @ 160), (24), DFS + (5735 - 5835 @ 80), (30) + # 5.9ghz band + # reference: https://apps.fcc.gov/edocs_public/attachmatch/FCC-03-324A1.pdf + (5842 - 5863 @ 5), (30) + (5850 - 5870 @ 10), (30) + (5860 - 5880 @ 10), (30) + (5865 - 5885 @ 20), (30) + (5870 - 5890 @ 10), (30) + (5880 - 5900 @ 10), (30) + (5890 - 5910 @ 10), (30) + (5895 - 5915 @ 20), (30) + (5900 - 5920 @ 10), (30) + (5910 - 5930 @ 10), (30) + # 60g band + # reference: http://cfr.regstoday.com/47cfr15.aspx#47_CFR_15p255 + # channels 1,2,3,4,5,6 EIRP=40dBm(43dBm peak) + (57240 - 70200 @ 2160), (40) + +country UY: DFS-FCC + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 80), (23), AUTO-BW + (5250 - 5330 @ 80), (23), DFS, AUTO-BW + (5735 - 5835 @ 80), (30) + # 60 gHz band channels 1-4 + (57240 - 65880 @ 2160), (40) + +country UZ: DFS-ETSI + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 80), (23), AUTO-BW + (5250 - 5330 @ 80), (23), DFS, AUTO-BW + +country VC: DFS-ETSI + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 80), (23), AUTO-BW + (5250 - 5330 @ 80), (23), DFS, AUTO-BW + (5490 - 5710 @ 160), (30), DFS + +country VE: DFS-FCC + (2402 - 2482 @ 40), (30) + (5170 - 5250 @ 80), (23), AUTO-BW + (5250 - 5330 @ 80), (23), DFS, AUTO-BW + (5735 - 5835 @ 80), (30) + +country VI: DFS-FCC + (2402 - 2472 @ 40), (30) + (5170 - 5250 @ 80), (24), AUTO-BW + (5250 - 5330 @ 80), (24), DFS, AUTO-BW + (5490 - 5730 @ 160), (24), DFS + (5735 - 5835 @ 80), (30) + +country VN: DFS-FCC + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 80), (24) + (5250 - 5330 @ 80), (24), DFS + (5490 - 5730 @ 80), (24), DFS + (5735 - 5835 @ 80), (30) + # 60 gHz band channels 1-4 + (57240 - 65880 @ 2160), (40) + +country VU: DFS-FCC + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 80), (24), AUTO-BW + (5250 - 5330 @ 80), (24), DFS, AUTO-BW + (5490 - 5730 @ 160), (24), DFS + (5735 - 5835 @ 80), (30) + +country WF: DFS-ETSI + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 80), (23), AUTO-BW + (5250 - 5330 @ 80), (23), DFS, AUTO-BW + (5490 - 5710 @ 160), (30), DFS + +country WS: DFS-ETSI + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 40), (23) + (5250 - 5330 @ 40), (23), DFS + (5490 - 5710 @ 40), (30), DFS + +country XA: DFS-JP + (2402 - 2482 @ 40), (20) + (2474 - 2494 @ 20), (20), NO-OFDM + (5170 - 5250 @ 80), (20), NO-IR, AUTO-BW, NO-OUTDOOR + (5250 - 5330 @ 80), (20), DFS, AUTO-BW, NO-OUTDOOR + (5490 - 5710 @ 160), (20), DFS + +country YE: + (2402 - 2482 @ 40), (20) + +country YT: DFS-ETSI + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 80), (23), AUTO-BW + (5250 - 5330 @ 80), (23), DFS, AUTO-BW + (5490 - 5710 @ 160), (30), DFS + +country ZA: DFS-FCC + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 80), (24), AUTO-BW + (5250 - 5330 @ 80), (24), DFS, AUTO-BW + (5490 - 5730 @ 160), (24), DFS + (5735 - 5835 @ 80), (30) + # 60 gHz band channels 1-4 + (57240 - 65880 @ 2160), (40), NO-OUTDOOR + +country ZW: DFS-ETSI + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 80), (23), AUTO-BW + (5250 - 5330 @ 80), (23), DFS, AUTO-BW + (5490 - 5710 @ 160), (30), DFS diff -ruw linux-4.4.115/net/wireless/ibss.c linux-4.4.115-fbx/net/wireless/ibss.c --- linux-4.4.115/net/wireless/ibss.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/net/wireless/ibss.c 2019-01-22 16:16:29.239298349 +0100 @@ -186,6 +186,7 @@ if (!nowext) wdev->wext.ibss.ssid_len = 0; #endif + cfg80211_sched_dfs_chan_update(rdev); } void cfg80211_clear_ibss(struct net_device *dev, bool nowext) diff -ruw linux-4.4.115/net/wireless/mesh.c linux-4.4.115-fbx/net/wireless/mesh.c --- linux-4.4.115/net/wireless/mesh.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/net/wireless/mesh.c 2019-01-22 16:16:29.239298349 +0100 @@ -260,6 +260,7 @@ wdev->mesh_id_len = 0; memset(&wdev->chandef, 0, sizeof(wdev->chandef)); rdev_set_qos_map(rdev, dev, NULL); + cfg80211_sched_dfs_chan_update(rdev); } return err; diff -ruw linux-4.4.115/net/wireless/mlme.c linux-4.4.115-fbx/net/wireless/mlme.c --- linux-4.4.115/net/wireless/mlme.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/net/wireless/mlme.c 2019-10-29 09:26:26.001226254 +0100 @@ -26,9 +26,16 @@ struct wiphy *wiphy = wdev->wiphy; struct cfg80211_registered_device *rdev = wiphy_to_rdev(wiphy); struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)buf; - u8 *ie = mgmt->u.assoc_resp.variable; - int ieoffs = offsetof(struct ieee80211_mgmt, u.assoc_resp.variable); - u16 status_code = le16_to_cpu(mgmt->u.assoc_resp.status_code); + struct cfg80211_connect_resp_params cr; + + memset(&cr, 0, sizeof(cr)); + cr.status = (int)le16_to_cpu(mgmt->u.assoc_resp.status_code); + cr.bssid = mgmt->bssid; + cr.bss = bss; + cr.resp_ie = mgmt->u.assoc_resp.variable; + cr.resp_ie_len = + len - offsetof(struct ieee80211_mgmt, u.assoc_resp.variable); + cr.timeout_reason = NL80211_TIMEOUT_UNSPECIFIED; trace_cfg80211_send_rx_assoc(dev, bss); @@ -38,7 +45,7 @@ * and got a reject -- we only try again with an assoc * frame instead of reassoc. */ - if (cfg80211_sme_rx_assoc_resp(wdev, status_code)) { + if (cfg80211_sme_rx_assoc_resp(wdev, cr.status)) { cfg80211_unhold_bss(bss_from_pub(bss)); cfg80211_put_bss(wiphy, bss); return; @@ -46,9 +53,7 @@ nl80211_send_rx_assoc(rdev, dev, buf, len, GFP_KERNEL, uapsd_queues); /* update current_bss etc., consumes the bss reference */ - __cfg80211_connect_result(dev, mgmt->bssid, NULL, 0, ie, len - ieoffs, - status_code, - status_code == WLAN_STATUS_SUCCESS, bss); + __cfg80211_connect_result(dev, &cr, cr.status == WLAN_STATUS_SUCCESS); } EXPORT_SYMBOL(cfg80211_rx_assoc_resp); @@ -216,14 +221,14 @@ const u8 *ssid, int ssid_len, const u8 *ie, int ie_len, const u8 *key, int key_len, int key_idx, - const u8 *sae_data, int sae_data_len) + const u8 *auth_data, int auth_data_len) { struct wireless_dev *wdev = dev->ieee80211_ptr; struct cfg80211_auth_request req = { .ie = ie, .ie_len = ie_len, - .sae_data = sae_data, - .sae_data_len = sae_data_len, + .auth_data = auth_data, + .auth_data_len = auth_data_len, .auth_type = auth_type, .key = key, .key_len = key_len, @@ -656,8 +661,25 @@ return err; } - if (!ether_addr_equal(mgmt->sa, wdev_address(wdev))) + if (!ether_addr_equal(mgmt->sa, wdev_address(wdev))) { + /* Allow random TA to be used with Public Action frames if the + * driver has indicated support for this. Otherwise, only allow + * the local address to be used. + */ + if (!ieee80211_is_action(mgmt->frame_control) || + mgmt->u.action.category != WLAN_CATEGORY_PUBLIC) + return -EINVAL; + if (!wdev->current_bss && + !wiphy_ext_feature_isset( + &rdev->wiphy, + NL80211_EXT_FEATURE_MGMT_TX_RANDOM_TA)) + return -EINVAL; + if (wdev->current_bss && + !wiphy_ext_feature_isset( + &rdev->wiphy, + NL80211_EXT_FEATURE_MGMT_TX_RANDOM_TA_CONNECTED)) return -EINVAL; + } /* Transmit the Action frame as requested by user space */ return rdev_mgmt_tx(rdev, wdev, params, cookie); @@ -721,6 +743,12 @@ } EXPORT_SYMBOL(cfg80211_rx_mgmt); +void cfg80211_sched_dfs_chan_update(struct cfg80211_registered_device *rdev) +{ + cancel_delayed_work(&rdev->dfs_update_channels_wk); + queue_delayed_work(cfg80211_wq, &rdev->dfs_update_channels_wk, 0); +} + void cfg80211_dfs_channels_update_work(struct work_struct *work) { struct delayed_work *delayed_work; @@ -731,6 +759,8 @@ struct wiphy *wiphy; bool check_again = false; unsigned long timeout, next_time = 0; + unsigned long time_dfs_update; + enum nl80211_radar_event radar_event; int bandid, i; delayed_work = container_of(work, struct delayed_work, work); @@ -747,11 +777,27 @@ for (i = 0; i < sband->n_channels; i++) { c = &sband->channels[i]; - if (c->dfs_state != NL80211_DFS_UNAVAILABLE) + if (!(c->flags & IEEE80211_CHAN_RADAR)) continue; - timeout = c->dfs_state_entered + msecs_to_jiffies( - IEEE80211_DFS_MIN_NOP_TIME_MS); + if (c->dfs_state != NL80211_DFS_UNAVAILABLE && + c->dfs_state != NL80211_DFS_AVAILABLE) + continue; + + if (c->dfs_state == NL80211_DFS_UNAVAILABLE) { + time_dfs_update = IEEE80211_DFS_MIN_NOP_TIME_MS; + radar_event = NL80211_RADAR_NOP_FINISHED; + } else { + if (regulatory_pre_cac_allowed(wiphy) || + cfg80211_any_wiphy_oper_chan(wiphy, c)) + continue; + + time_dfs_update = REG_PRE_CAC_EXPIRY_GRACE_MS; + radar_event = NL80211_RADAR_PRE_CAC_EXPIRED; + } + + timeout = c->dfs_state_entered + + msecs_to_jiffies(time_dfs_update); if (time_after_eq(jiffies, timeout)) { c->dfs_state = NL80211_DFS_USABLE; @@ -761,8 +807,8 @@ NL80211_CHAN_NO_HT); nl80211_radar_notify(rdev, &chandef, - NL80211_RADAR_NOP_FINISHED, - NULL, GFP_ATOMIC); + radar_event, NULL, + GFP_ATOMIC); continue; } @@ -787,7 +833,6 @@ gfp_t gfp) { struct cfg80211_registered_device *rdev = wiphy_to_rdev(wiphy); - unsigned long timeout; trace_cfg80211_radar_event(wiphy, chandef); @@ -797,9 +842,7 @@ */ cfg80211_set_dfs_state(wiphy, chandef, NL80211_DFS_UNAVAILABLE); - timeout = msecs_to_jiffies(IEEE80211_DFS_MIN_NOP_TIME_MS); - queue_delayed_work(cfg80211_wq, &rdev->dfs_update_channels_wk, - timeout); + cfg80211_sched_dfs_chan_update(rdev); nl80211_radar_notify(rdev, chandef, NL80211_RADAR_DETECTED, NULL, gfp); } @@ -828,6 +871,7 @@ msecs_to_jiffies(wdev->cac_time_ms); WARN_ON(!time_after_eq(jiffies, timeout)); cfg80211_set_dfs_state(wiphy, chandef, NL80211_DFS_AVAILABLE); + cfg80211_sched_dfs_chan_update(rdev); break; case NL80211_RADAR_CAC_ABORTED: break; diff -ruw linux-4.4.115/net/wireless/nl80211.c linux-4.4.115-fbx/net/wireless/nl80211.c --- linux-4.4.115/net/wireless/nl80211.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/net/wireless/nl80211.c 2019-10-29 09:26:26.009226332 +0100 @@ -103,7 +103,7 @@ if (have_wdev_id && rdev->wiphy_idx != wiphy_idx) continue; - list_for_each_entry(wdev, &rdev->wdev_list, list) { + list_for_each_entry(wdev, &rdev->wiphy.wdev_list, list) { if (have_ifidx && wdev->netdev && wdev->netdev->ifindex == ifidx) { result = wdev; @@ -149,7 +149,7 @@ tmp = cfg80211_rdev_by_wiphy_idx(wdev_id >> 32); if (tmp) { /* make sure wdev exists */ - list_for_each_entry(wdev, &tmp->wdev_list, list) { + list_for_each_entry(wdev, &tmp->wiphy.wdev_list, list) { if (wdev->identifier != (u32)wdev_id) continue; found = true; @@ -353,7 +353,7 @@ [NL80211_ATTR_BG_SCAN_PERIOD] = { .type = NLA_U16 }, [NL80211_ATTR_WDEV] = { .type = NLA_U64 }, [NL80211_ATTR_USER_REG_HINT_TYPE] = { .type = NLA_U32 }, - [NL80211_ATTR_SAE_DATA] = { .type = NLA_BINARY, }, + [NL80211_ATTR_AUTH_DATA] = { .type = NLA_BINARY, }, [NL80211_ATTR_VHT_CAPABILITY] = { .len = NL80211_VHT_CAPABILITY_LEN }, [NL80211_ATTR_SCAN_FLAGS] = { .type = NLA_U32 }, [NL80211_ATTR_P2P_CTWINDOW] = { .type = NLA_U8 }, @@ -401,6 +401,26 @@ [NL80211_ATTR_NETNS_FD] = { .type = NLA_U32 }, [NL80211_ATTR_SCHED_SCAN_DELAY] = { .type = NLA_U32 }, [NL80211_ATTR_REG_INDOOR] = { .type = NLA_FLAG }, + [NL80211_ATTR_PBSS] = { .type = NLA_FLAG }, + [NL80211_ATTR_BSS_SELECT] = { .type = NLA_NESTED }, + [NL80211_ATTR_BSSID] = { .len = ETH_ALEN }, + [NL80211_ATTR_SCHED_SCAN_RELATIVE_RSSI] = { .type = NLA_S8 }, + [NL80211_ATTR_SCHED_SCAN_RSSI_ADJUST] = { + .len = sizeof(struct nl80211_bss_select_rssi_adjust) + }, + [NL80211_ATTR_FILS_KEK] = { .type = NLA_BINARY, + .len = FILS_MAX_KEK_LEN }, + [NL80211_ATTR_FILS_NONCES] = { .len = 2 * FILS_NONCE_LEN }, + [NL80211_ATTR_TIMEOUT_REASON] = { .type = NLA_U32 }, + [NL80211_ATTR_FILS_ERP_USERNAME] = { .type = NLA_BINARY, + .len = FILS_ERP_MAX_USERNAME_LEN }, + [NL80211_ATTR_FILS_ERP_REALM] = { .type = NLA_BINARY, + .len = FILS_ERP_MAX_REALM_LEN }, + [NL80211_ATTR_FILS_ERP_NEXT_SEQ_NUM] = { .type = NLA_U16 }, + [NL80211_ATTR_FILS_ERP_RRK] = { .type = NLA_BINARY, + .len = FILS_ERP_MAX_RRK_LEN }, + [NL80211_ATTR_FILS_CACHE_ID] = { .len = 2 }, + [NL80211_ATTR_PMK] = { .type = NLA_BINARY, .len = PMK_MAX_LEN }, }; /* policy for the key attributes */ @@ -467,7 +487,8 @@ /* policy for GTK rekey offload attributes */ static const struct nla_policy nl80211_rekey_policy[NUM_NL80211_REKEY_DATA] = { - [NL80211_REKEY_DATA_KEK] = { .len = NL80211_KEK_LEN }, + [NL80211_REKEY_DATA_KEK] = { .type = NLA_BINARY, + .len = FILS_MAX_KEK_LEN }, [NL80211_REKEY_DATA_KCK] = { .len = NL80211_KCK_LEN }, [NL80211_REKEY_DATA_REPLAY_CTR] = { .len = NL80211_REPLAY_CTR_LEN }, }; @@ -485,6 +506,15 @@ [NL80211_SCHED_SCAN_PLAN_ITERATIONS] = { .type = NLA_U32 }, }; +static const struct nla_policy +nl80211_bss_select_policy[NL80211_BSS_SELECT_ATTR_MAX + 1] = { + [NL80211_BSS_SELECT_ATTR_RSSI] = { .type = NLA_FLAG }, + [NL80211_BSS_SELECT_ATTR_BAND_PREF] = { .type = NLA_U32 }, + [NL80211_BSS_SELECT_ATTR_RSSI_ADJUST] = { + .len = sizeof(struct nl80211_bss_select_rssi_adjust) + }, +}; + /* policy for packet pattern attributes */ static const struct nla_policy nl80211_packet_pattern_policy[MAX_NL80211_PKTPAT + 1] = { @@ -525,7 +555,7 @@ *rdev = wiphy_to_rdev(wiphy); *wdev = NULL; - list_for_each_entry(tmp, &(*rdev)->wdev_list, list) { + list_for_each_entry(tmp, &(*rdev)->wiphy.wdev_list, list) { if (tmp->identifier == cb->args[1]) { *wdev = tmp; break; @@ -994,6 +1024,10 @@ nla_put_u32(msg, NL80211_IFACE_COMB_RADAR_DETECT_REGIONS, c->radar_detect_regions))) goto nla_put_failure; + if (c->beacon_int_min_gcd && + nla_put_u32(msg, NL80211_IFACE_COMB_BI_MIN_GCD, + c->beacon_int_min_gcd)) + goto nla_put_failure; nla_nest_end(msg, nl_combi); } @@ -1244,7 +1278,7 @@ struct nl80211_dump_wiphy_state { s64 filter_wiphy; long start; - long split_start, band_start, chan_start; + long split_start, band_start, chan_start, capa_start; bool split; }; @@ -1538,6 +1572,7 @@ if (rdev->wiphy.features & NL80211_FEATURE_SUPPORTS_WMM_ADMISSION) CMD(add_tx_ts, ADD_TX_TS); + CMD(update_connect_params, UPDATE_CONNECT_PARAMS); } /* add into the if now */ #undef CMD @@ -1722,6 +1757,66 @@ rdev->wiphy.ext_features)) goto nla_put_failure; + state->split_start++; + break; + case 13: + if (rdev->wiphy.num_iftype_ext_capab && + rdev->wiphy.iftype_ext_capab) { + struct nlattr *nested_ext_capab, *nested; + + nested = nla_nest_start(msg, + NL80211_ATTR_IFTYPE_EXT_CAPA); + if (!nested) + goto nla_put_failure; + + for (i = state->capa_start; + i < rdev->wiphy.num_iftype_ext_capab; i++) { + const struct wiphy_iftype_ext_capab *capab; + + capab = &rdev->wiphy.iftype_ext_capab[i]; + + nested_ext_capab = nla_nest_start(msg, i); + if (!nested_ext_capab || + nla_put_u32(msg, NL80211_ATTR_IFTYPE, + capab->iftype) || + nla_put(msg, NL80211_ATTR_EXT_CAPA, + capab->extended_capabilities_len, + capab->extended_capabilities) || + nla_put(msg, NL80211_ATTR_EXT_CAPA_MASK, + capab->extended_capabilities_len, + capab->extended_capabilities_mask)) + goto nla_put_failure; + + nla_nest_end(msg, nested_ext_capab); + if (state->split) + break; + } + nla_nest_end(msg, nested); + if (i < rdev->wiphy.num_iftype_ext_capab) { + state->capa_start = i + 1; + break; + } + } + + if (rdev->wiphy.bss_select_support) { + struct nlattr *nested; + u32 bss_select_support = rdev->wiphy.bss_select_support; + + nested = nla_nest_start(msg, NL80211_ATTR_BSS_SELECT); + if (!nested) + goto nla_put_failure; + + i = 0; + while (bss_select_support) { + if ((bss_select_support & 1) && + nla_put_flag(msg, i)) + goto nla_put_failure; + i++; + bss_select_support >>= 1; + } + nla_nest_end(msg, nested); + } + /* done */ state->split_start = 0; break; @@ -2450,7 +2545,7 @@ } if_idx = 0; - list_for_each_entry(wdev, &rdev->wdev_list, list) { + list_for_each_entry(wdev, &rdev->wiphy.wdev_list, list) { if (if_idx < if_start) { if_idx++; continue; @@ -2722,7 +2817,7 @@ spin_lock_init(&wdev->mgmt_registrations_lock); wdev->identifier = ++rdev->wdev_id; - list_add_rcu(&wdev->list, &rdev->wdev_list); + list_add_rcu(&wdev->list, &rdev->wiphy.wdev_list); rdev->devlist_generation++; break; default: @@ -3195,6 +3290,291 @@ return err; } +static u32 rateset_to_mask(struct ieee80211_supported_band *sband, + u8 *rates, u8 rates_len) +{ + u8 i; + u32 mask = 0; + + for (i = 0; i < rates_len; i++) { + int rate = (rates[i] & 0x7f) * 5; + int ridx; + + for (ridx = 0; ridx < sband->n_bitrates; ridx++) { + struct ieee80211_rate *srate = + &sband->bitrates[ridx]; + if (rate == srate->bitrate) { + mask |= 1 << ridx; + break; + } + } + if (ridx == sband->n_bitrates) + return 0; /* rate not found */ + } + + return mask; +} + +static bool ht_rateset_to_mask(struct ieee80211_supported_band *sband, + u8 *rates, u8 rates_len, + u8 mcs[IEEE80211_HT_MCS_MASK_LEN]) +{ + u8 i; + + memset(mcs, 0, IEEE80211_HT_MCS_MASK_LEN); + + for (i = 0; i < rates_len; i++) { + int ridx, rbit; + + ridx = rates[i] / 8; + rbit = BIT(rates[i] % 8); + + /* check validity */ + if ((ridx < 0) || (ridx >= IEEE80211_HT_MCS_MASK_LEN)) + return false; + + /* check availability */ + if (sband->ht_cap.mcs.rx_mask[ridx] & rbit) + mcs[ridx] |= rbit; + else + return false; + } + + return true; +} + +static u16 vht_mcs_map_to_mcs_mask(u8 vht_mcs_map) +{ + u16 mcs_mask = 0; + + switch (vht_mcs_map) { + case IEEE80211_VHT_MCS_NOT_SUPPORTED: + break; + case IEEE80211_VHT_MCS_SUPPORT_0_7: + mcs_mask = 0x00FF; + break; + case IEEE80211_VHT_MCS_SUPPORT_0_8: + mcs_mask = 0x01FF; + break; + case IEEE80211_VHT_MCS_SUPPORT_0_9: + mcs_mask = 0x03FF; + break; + default: + break; + } + + return mcs_mask; +} + +static void vht_build_mcs_mask(u16 vht_mcs_map, + u16 vht_mcs_mask[NL80211_VHT_NSS_MAX]) +{ + u8 nss; + + for (nss = 0; nss < NL80211_VHT_NSS_MAX; nss++) { + vht_mcs_mask[nss] = vht_mcs_map_to_mcs_mask(vht_mcs_map & 0x03); + vht_mcs_map >>= 2; + } +} + +static bool vht_set_mcs_mask(struct ieee80211_supported_band *sband, + struct nl80211_txrate_vht *txrate, + u16 mcs[NL80211_VHT_NSS_MAX]) +{ + u16 tx_mcs_map = le16_to_cpu(sband->vht_cap.vht_mcs.tx_mcs_map); + u16 tx_mcs_mask[NL80211_VHT_NSS_MAX] = {}; + u8 i; + + if (!sband->vht_cap.vht_supported) + return false; + + memset(mcs, 0, sizeof(u16) * NL80211_VHT_NSS_MAX); + + /* Build vht_mcs_mask from VHT capabilities */ + vht_build_mcs_mask(tx_mcs_map, tx_mcs_mask); + + for (i = 0; i < NL80211_VHT_NSS_MAX; i++) { + if ((tx_mcs_mask[i] & txrate->mcs[i]) == txrate->mcs[i]) + mcs[i] = txrate->mcs[i]; + else + return false; + } + + return true; +} + +static const struct nla_policy nl80211_txattr_policy[NL80211_TXRATE_MAX + 1] = { + [NL80211_TXRATE_LEGACY] = { .type = NLA_BINARY, + .len = NL80211_MAX_SUPP_RATES }, + [NL80211_TXRATE_HT] = { .type = NLA_BINARY, + .len = NL80211_MAX_SUPP_HT_RATES }, + [NL80211_TXRATE_VHT] = { .len = sizeof(struct nl80211_txrate_vht)}, + [NL80211_TXRATE_GI] = { .type = NLA_U8 }, +}; + +static int nl80211_parse_tx_bitrate_mask(struct genl_info *info, + struct cfg80211_bitrate_mask *mask) +{ + struct nlattr *tb[NL80211_TXRATE_MAX + 1]; + struct cfg80211_registered_device *rdev = info->user_ptr[0]; + int rem, i; + struct nlattr *tx_rates; + struct ieee80211_supported_band *sband; + u16 vht_tx_mcs_map; + + memset(mask, 0, sizeof(*mask)); + /* Default to all rates enabled */ + for (i = 0; i < IEEE80211_NUM_BANDS; i++) { + sband = rdev->wiphy.bands[i]; + + if (!sband) + continue; + + mask->control[i].legacy = (1 << sband->n_bitrates) - 1; + memcpy(mask->control[i].ht_mcs, + sband->ht_cap.mcs.rx_mask, + sizeof(mask->control[i].ht_mcs)); + + if (!sband->vht_cap.vht_supported) + continue; + + vht_tx_mcs_map = le16_to_cpu(sband->vht_cap.vht_mcs.tx_mcs_map); + vht_build_mcs_mask(vht_tx_mcs_map, mask->control[i].vht_mcs); + } + + /* if no rates are given set it back to the defaults */ + if (!info->attrs[NL80211_ATTR_TX_RATES]) + goto out; + + /* The nested attribute uses enum nl80211_band as the index. This maps + * directly to the enum nl80211_band values used in cfg80211. + */ + BUILD_BUG_ON(NL80211_MAX_SUPP_HT_RATES > IEEE80211_HT_MCS_MASK_LEN * 8); + nla_for_each_nested(tx_rates, info->attrs[NL80211_ATTR_TX_RATES], rem) { + enum ieee80211_band band = nla_type(tx_rates); + int err; + + if (band < 0 || band >= IEEE80211_NUM_BANDS) + return -EINVAL; + sband = rdev->wiphy.bands[band]; + if (sband == NULL) + return -EINVAL; + err = nla_parse(tb, NL80211_TXRATE_MAX, nla_data(tx_rates), + nla_len(tx_rates), nl80211_txattr_policy); + if (err) + return err; + if (tb[NL80211_TXRATE_LEGACY]) { + mask->control[band].legacy = rateset_to_mask( + sband, + nla_data(tb[NL80211_TXRATE_LEGACY]), + nla_len(tb[NL80211_TXRATE_LEGACY])); + if ((mask->control[band].legacy == 0) && + nla_len(tb[NL80211_TXRATE_LEGACY])) + return -EINVAL; + } + if (tb[NL80211_TXRATE_HT]) { + if (!ht_rateset_to_mask( + sband, + nla_data(tb[NL80211_TXRATE_HT]), + nla_len(tb[NL80211_TXRATE_HT]), + mask->control[band].ht_mcs)) + return -EINVAL; + } + if (tb[NL80211_TXRATE_VHT]) { + if (!vht_set_mcs_mask( + sband, + nla_data(tb[NL80211_TXRATE_VHT]), + mask->control[band].vht_mcs)) + return -EINVAL; + } + if (tb[NL80211_TXRATE_GI]) { + mask->control[band].gi = + nla_get_u8(tb[NL80211_TXRATE_GI]); + if (mask->control[band].gi > NL80211_TXRATE_FORCE_LGI) + return -EINVAL; + } + + if (mask->control[band].legacy == 0) { + /* don't allow empty legacy rates if HT or VHT + * are not even supported. + */ + if (!(rdev->wiphy.bands[band]->ht_cap.ht_supported || + rdev->wiphy.bands[band]->vht_cap.vht_supported)) + return -EINVAL; + + for (i = 0; i < IEEE80211_HT_MCS_MASK_LEN; i++) + if (mask->control[band].ht_mcs[i]) + goto out; + + for (i = 0; i < NL80211_VHT_NSS_MAX; i++) + if (mask->control[band].vht_mcs[i]) + goto out; + + /* legacy and mcs rates may not be both empty */ + return -EINVAL; + } + } + +out: + return 0; +} + +static int validate_beacon_tx_rate(struct cfg80211_registered_device *rdev, + enum nl80211_band band, + struct cfg80211_bitrate_mask *beacon_rate) +{ + u32 count_ht, count_vht, i; + u32 rate = beacon_rate->control[band].legacy; + + /* Allow only one rate */ + if (hweight32(rate) > 1) + return -EINVAL; + + count_ht = 0; + for (i = 0; i < IEEE80211_HT_MCS_MASK_LEN; i++) { + if (hweight8(beacon_rate->control[band].ht_mcs[i]) > 1) { + return -EINVAL; + } else if (beacon_rate->control[band].ht_mcs[i]) { + count_ht++; + if (count_ht > 1) + return -EINVAL; + } + if (count_ht && rate) + return -EINVAL; + } + + count_vht = 0; + for (i = 0; i < NL80211_VHT_NSS_MAX; i++) { + if (hweight16(beacon_rate->control[band].vht_mcs[i]) > 1) { + return -EINVAL; + } else if (beacon_rate->control[band].vht_mcs[i]) { + count_vht++; + if (count_vht > 1) + return -EINVAL; + } + if (count_vht && rate) + return -EINVAL; + } + + if ((count_ht && count_vht) || (!rate && !count_ht && !count_vht)) + return -EINVAL; + + if (rate && + !wiphy_ext_feature_isset(&rdev->wiphy, + NL80211_EXT_FEATURE_BEACON_RATE_LEGACY)) + return -EINVAL; + if (count_ht && + !wiphy_ext_feature_isset(&rdev->wiphy, + NL80211_EXT_FEATURE_BEACON_RATE_HT)) + return -EINVAL; + if (count_vht && + !wiphy_ext_feature_isset(&rdev->wiphy, + NL80211_EXT_FEATURE_BEACON_RATE_VHT)) + return -EINVAL; + + return 0; +} + static int nl80211_parse_beacon(struct nlattr *attrs[], struct cfg80211_beacon_data *bcn) { @@ -3258,7 +3638,7 @@ struct wireless_dev *wdev; bool ret = false; - list_for_each_entry(wdev, &rdev->wdev_list, list) { + list_for_each_entry(wdev, &rdev->wiphy.wdev_list, list) { if (wdev->iftype != NL80211_IFTYPE_AP && wdev->iftype != NL80211_IFTYPE_P2P_GO) continue; @@ -3286,12 +3666,36 @@ if (!(rdev->wiphy.features & NL80211_FEATURE_SAE) && auth_type == NL80211_AUTHTYPE_SAE) return false; + if (!wiphy_ext_feature_isset(&rdev->wiphy, + NL80211_EXT_FEATURE_FILS_STA) && + (auth_type == NL80211_AUTHTYPE_FILS_SK || + auth_type == NL80211_AUTHTYPE_FILS_SK_PFS || + auth_type == NL80211_AUTHTYPE_FILS_PK)) + return false; return true; case NL80211_CMD_CONNECT: + /* SAE not supported yet */ + if (auth_type == NL80211_AUTHTYPE_SAE) + return false; + /* FILS with SK PFS or PK not supported yet */ + if (auth_type == NL80211_AUTHTYPE_FILS_SK_PFS || + auth_type == NL80211_AUTHTYPE_FILS_PK) + return false; + if (!wiphy_ext_feature_isset( + &rdev->wiphy, + NL80211_EXT_FEATURE_FILS_SK_OFFLOAD) && + auth_type == NL80211_AUTHTYPE_FILS_SK) + return false; + return true; case NL80211_CMD_START_AP: /* SAE not supported yet */ if (auth_type == NL80211_AUTHTYPE_SAE) return false; + /* FILS not supported yet */ + if (auth_type == NL80211_AUTHTYPE_FILS_SK || + auth_type == NL80211_AUTHTYPE_FILS_SK_PFS || + auth_type == NL80211_AUTHTYPE_FILS_PK) + return false; return true; default: return false; @@ -3333,7 +3737,8 @@ params.dtim_period = nla_get_u32(info->attrs[NL80211_ATTR_DTIM_PERIOD]); - err = cfg80211_validate_beacon_int(rdev, params.beacon_interval); + err = cfg80211_validate_beacon_int(rdev, dev->ieee80211_ptr->iftype, + params.beacon_interval); if (err) return err; @@ -3424,6 +3829,17 @@ wdev->iftype)) return -EINVAL; + if (info->attrs[NL80211_ATTR_TX_RATES]) { + err = nl80211_parse_tx_bitrate_mask(info, ¶ms.beacon_rate); + if (err) + return err; + + err = validate_beacon_tx_rate(rdev, params.chandef.chan->band, + ¶ms.beacon_rate); + if (err) + return err; + } + if (info->attrs[NL80211_ATTR_SMPS_MODE]) { params.smps_mode = nla_get_u8(info->attrs[NL80211_ATTR_SMPS_MODE]); @@ -3447,6 +3863,10 @@ params.smps_mode = NL80211_SMPS_OFF; } + params.pbss = nla_get_flag(info->attrs[NL80211_ATTR_PBSS]); + if (params.pbss && !rdev->wiphy.bands[IEEE80211_BAND_60GHZ]) + return -EOPNOTSUPP; + if (info->attrs[NL80211_ATTR_ACL_POLICY]) { params.acl = parse_acl_data(&rdev->wiphy, info); if (IS_ERR(params.acl)) @@ -5737,6 +6157,73 @@ return n_channels; } +static bool is_band_valid(struct wiphy *wiphy, enum ieee80211_band b) +{ + return b < IEEE80211_NUM_BANDS && wiphy->bands[b]; +} + +static int parse_bss_select(struct nlattr *nla, struct wiphy *wiphy, + struct cfg80211_bss_selection *bss_select) +{ + struct nlattr *attr[NL80211_BSS_SELECT_ATTR_MAX + 1]; + struct nlattr *nest; + int err; + bool found = false; + int i; + + /* only process one nested attribute */ + nest = nla_data(nla); + if (!nla_ok(nest, nla_len(nest))) + return -EINVAL; + + err = nla_parse(attr, NL80211_BSS_SELECT_ATTR_MAX, nla_data(nest), + nla_len(nest), nl80211_bss_select_policy); + if (err) + return err; + + /* only one attribute may be given */ + for (i = 0; i <= NL80211_BSS_SELECT_ATTR_MAX; i++) { + if (attr[i]) { + if (found) + return -EINVAL; + found = true; + } + } + + bss_select->behaviour = __NL80211_BSS_SELECT_ATTR_INVALID; + + if (attr[NL80211_BSS_SELECT_ATTR_RSSI]) + bss_select->behaviour = NL80211_BSS_SELECT_ATTR_RSSI; + + if (attr[NL80211_BSS_SELECT_ATTR_BAND_PREF]) { + bss_select->behaviour = NL80211_BSS_SELECT_ATTR_BAND_PREF; + bss_select->param.band_pref = + nla_get_u32(attr[NL80211_BSS_SELECT_ATTR_BAND_PREF]); + if (!is_band_valid(wiphy, bss_select->param.band_pref)) + return -EINVAL; + } + + if (attr[NL80211_BSS_SELECT_ATTR_RSSI_ADJUST]) { + struct nl80211_bss_select_rssi_adjust *adj_param; + + adj_param = nla_data(attr[NL80211_BSS_SELECT_ATTR_RSSI_ADJUST]); + bss_select->behaviour = NL80211_BSS_SELECT_ATTR_RSSI_ADJUST; + bss_select->param.adjust.band = adj_param->band; + bss_select->param.adjust.delta = adj_param->delta; + if (!is_band_valid(wiphy, bss_select->param.adjust.band)) + return -EINVAL; + } + + /* user-space did not provide behaviour attribute */ + if (bss_select->behaviour == __NL80211_BSS_SELECT_ATTR_INVALID) + return -EINVAL; + + if (!(wiphy->bss_select_support & BIT(bss_select->behaviour))) + return -EINVAL; + + return 0; +} + static int nl80211_parse_random_mac(struct nlattr **attrs, u8 *mac_addr, u8 *mac_addr_mask) { @@ -5975,6 +6462,25 @@ request->no_cck = nla_get_flag(info->attrs[NL80211_ATTR_TX_NO_CCK_RATE]); + /* Initial implementation used NL80211_ATTR_MAC to set the specific + * BSSID to scan for. This was problematic because that same attribute + * was already used for another purpose (local random MAC address). The + * NL80211_ATTR_BSSID attribute was added to fix this. For backwards + * compatibility with older userspace components, also use the + * NL80211_ATTR_MAC value here if it can be determined to be used for + * the specific BSSID use case instead of the random MAC address + * (NL80211_ATTR_SCAN_FLAGS is used to enable random MAC address use). + */ + if (info->attrs[NL80211_ATTR_BSSID]) + memcpy(request->bssid, + nla_data(info->attrs[NL80211_ATTR_BSSID]), ETH_ALEN); + else if (!(request->flags & NL80211_SCAN_FLAG_RANDOM_ADDR) && + info->attrs[NL80211_ATTR_MAC]) + memcpy(request->bssid, nla_data(info->attrs[NL80211_ATTR_MAC]), + ETH_ALEN); + else + eth_broadcast_addr(request->bssid); + request->wdev = wdev; request->wiphy = &rdev->wiphy; request->scan_start = jiffies; @@ -6188,6 +6694,12 @@ if (!n_plans || n_plans > wiphy->max_sched_scan_plans) return ERR_PTR(-EINVAL); + if (!wiphy_ext_feature_isset( + wiphy, NL80211_EXT_FEATURE_SCHED_SCAN_RELATIVE_RSSI) && + (attrs[NL80211_ATTR_SCHED_SCAN_RELATIVE_RSSI] || + attrs[NL80211_ATTR_SCHED_SCAN_RSSI_ADJUST])) + return ERR_PTR(-EINVAL); + request = kzalloc(sizeof(*request) + sizeof(*request->ssids) * n_ssids + sizeof(*request->match_sets) * n_match_sets @@ -6393,6 +6905,26 @@ request->delay = nla_get_u32(attrs[NL80211_ATTR_SCHED_SCAN_DELAY]); + if (attrs[NL80211_ATTR_SCHED_SCAN_RELATIVE_RSSI]) { + request->relative_rssi = nla_get_s8( + attrs[NL80211_ATTR_SCHED_SCAN_RELATIVE_RSSI]); + request->relative_rssi_set = true; + } + + if (request->relative_rssi_set && + attrs[NL80211_ATTR_SCHED_SCAN_RSSI_ADJUST]) { + struct nl80211_bss_select_rssi_adjust *rssi_adjust; + + rssi_adjust = nla_data( + attrs[NL80211_ATTR_SCHED_SCAN_RSSI_ADJUST]); + request->rssi_adjust.band = rssi_adjust->band; + request->rssi_adjust.delta = rssi_adjust->delta; + if (!is_band_valid(wiphy, request->rssi_adjust.band)) { + err = -EINVAL; + goto out_free; + } + } + err = nl80211_parse_sched_scan_plans(wiphy, n_plans, request, attrs); if (err) goto out_free; @@ -6406,6 +6938,24 @@ return ERR_PTR(err); } +static int nl80211_abort_scan(struct sk_buff *skb, struct genl_info *info) +{ + struct cfg80211_registered_device *rdev = info->user_ptr[0]; + struct wireless_dev *wdev = info->user_ptr[1]; + + if (!rdev->ops->abort_scan) + return -EOPNOTSUPP; + + if (rdev->scan_msg) + return 0; + + if (!rdev->scan_req) + return -ENOENT; + + rdev_abort_scan(rdev, wdev); + return 0; +} + static int nl80211_start_sched_scan(struct sk_buff *skb, struct genl_info *info) { @@ -6482,6 +7032,9 @@ if (err) return err; + if (rdev->wiphy.flags & WIPHY_FLAG_DFS_OFFLOAD) + return -EOPNOTSUPP; + if (netif_carrier_ok(dev)) return -EBUSY; @@ -6976,8 +7529,8 @@ struct cfg80211_registered_device *rdev = info->user_ptr[0]; struct net_device *dev = info->user_ptr[1]; struct ieee80211_channel *chan; - const u8 *bssid, *ssid, *ie = NULL, *sae_data = NULL; - int err, ssid_len, ie_len = 0, sae_data_len = 0; + const u8 *bssid, *ssid, *ie = NULL, *auth_data = NULL; + int err, ssid_len, ie_len = 0, auth_data_len = 0; enum nl80211_auth_type auth_type; struct key_parse key; bool local_state_change; @@ -7056,17 +7609,23 @@ if (!nl80211_valid_auth_type(rdev, auth_type, NL80211_CMD_AUTHENTICATE)) return -EINVAL; - if (auth_type == NL80211_AUTHTYPE_SAE && - !info->attrs[NL80211_ATTR_SAE_DATA]) + if ((auth_type == NL80211_AUTHTYPE_SAE || + auth_type == NL80211_AUTHTYPE_FILS_SK || + auth_type == NL80211_AUTHTYPE_FILS_SK_PFS || + auth_type == NL80211_AUTHTYPE_FILS_PK) && + !info->attrs[NL80211_ATTR_AUTH_DATA]) return -EINVAL; - if (info->attrs[NL80211_ATTR_SAE_DATA]) { - if (auth_type != NL80211_AUTHTYPE_SAE) + if (info->attrs[NL80211_ATTR_AUTH_DATA]) { + if (auth_type != NL80211_AUTHTYPE_SAE && + auth_type != NL80211_AUTHTYPE_FILS_SK && + auth_type != NL80211_AUTHTYPE_FILS_SK_PFS && + auth_type != NL80211_AUTHTYPE_FILS_PK) return -EINVAL; - sae_data = nla_data(info->attrs[NL80211_ATTR_SAE_DATA]); - sae_data_len = nla_len(info->attrs[NL80211_ATTR_SAE_DATA]); + auth_data = nla_data(info->attrs[NL80211_ATTR_AUTH_DATA]); + auth_data_len = nla_len(info->attrs[NL80211_ATTR_AUTH_DATA]); /* need to include at least Auth Transaction and Status Code */ - if (sae_data_len < 4) + if (auth_data_len < 4) return -EINVAL; } @@ -7083,7 +7642,7 @@ err = cfg80211_mlme_auth(rdev, dev, chan, auth_type, bssid, ssid, ssid_len, ie, ie_len, key.p.key, key.p.key_len, key.idx, - sae_data, sae_data_len); + auth_data, auth_data_len); wdev_unlock(dev->ieee80211_ptr); return err; } @@ -7259,6 +7818,15 @@ req.flags |= ASSOC_REQ_USE_RRM; } + if (info->attrs[NL80211_ATTR_FILS_KEK]) { + req.fils_kek = nla_data(info->attrs[NL80211_ATTR_FILS_KEK]); + req.fils_kek_len = nla_len(info->attrs[NL80211_ATTR_FILS_KEK]); + if (!info->attrs[NL80211_ATTR_FILS_NONCES]) + return -EINVAL; + req.fils_nonces = + nla_data(info->attrs[NL80211_ATTR_FILS_NONCES]); + } + err = nl80211_crypto_settings(rdev, info, &req.crypto, 1); if (!err) { wdev_lock(dev->ieee80211_ptr); @@ -7412,12 +7980,14 @@ ibss.beacon_interval = 100; - if (info->attrs[NL80211_ATTR_BEACON_INTERVAL]) { + if (info->attrs[NL80211_ATTR_BEACON_INTERVAL]) ibss.beacon_interval = nla_get_u32(info->attrs[NL80211_ATTR_BEACON_INTERVAL]); - if (ibss.beacon_interval < 1 || ibss.beacon_interval > 10000) - return -EINVAL; - } + + err = cfg80211_validate_beacon_int(rdev, NL80211_IFTYPE_ADHOC, + ibss.beacon_interval); + if (err) + return err; if (!rdev->ops->join_ibss) return -EOPNOTSUPP; @@ -7886,6 +8456,10 @@ connect.mfp = NL80211_MFP_NO; } + if (info->attrs[NL80211_ATTR_PREV_BSSID]) + connect.prev_bssid = + nla_data(info->attrs[NL80211_ATTR_PREV_BSSID]); + if (info->attrs[NL80211_ATTR_WIPHY_FREQ]) { connect.channel = nl80211_get_valid_chan( wiphy, info->attrs[NL80211_ATTR_WIPHY_FREQ]); @@ -7951,6 +8525,56 @@ connect.flags |= ASSOC_REQ_USE_RRM; } + connect.pbss = nla_get_flag(info->attrs[NL80211_ATTR_PBSS]); + if (connect.pbss && !rdev->wiphy.bands[IEEE80211_BAND_60GHZ]) { + kzfree(connkeys); + return -EOPNOTSUPP; + } + + if (info->attrs[NL80211_ATTR_BSS_SELECT]) { + /* bss selection makes no sense if bssid is set */ + if (connect.bssid) { + kzfree(connkeys); + return -EINVAL; + } + + err = parse_bss_select(info->attrs[NL80211_ATTR_BSS_SELECT], + wiphy, &connect.bss_select); + if (err) { + kzfree(connkeys); + return err; + } + } + + if (wiphy_ext_feature_isset(&rdev->wiphy, + NL80211_EXT_FEATURE_FILS_SK_OFFLOAD) && + info->attrs[NL80211_ATTR_FILS_ERP_USERNAME] && + info->attrs[NL80211_ATTR_FILS_ERP_REALM] && + info->attrs[NL80211_ATTR_FILS_ERP_NEXT_SEQ_NUM] && + info->attrs[NL80211_ATTR_FILS_ERP_RRK]) { + connect.fils_erp_username = + nla_data(info->attrs[NL80211_ATTR_FILS_ERP_USERNAME]); + connect.fils_erp_username_len = + nla_len(info->attrs[NL80211_ATTR_FILS_ERP_USERNAME]); + connect.fils_erp_realm = + nla_data(info->attrs[NL80211_ATTR_FILS_ERP_REALM]); + connect.fils_erp_realm_len = + nla_len(info->attrs[NL80211_ATTR_FILS_ERP_REALM]); + connect.fils_erp_next_seq_num = + nla_get_u16( + info->attrs[NL80211_ATTR_FILS_ERP_NEXT_SEQ_NUM]); + connect.fils_erp_rrk = + nla_data(info->attrs[NL80211_ATTR_FILS_ERP_RRK]); + connect.fils_erp_rrk_len = + nla_len(info->attrs[NL80211_ATTR_FILS_ERP_RRK]); + } else if (info->attrs[NL80211_ATTR_FILS_ERP_USERNAME] || + info->attrs[NL80211_ATTR_FILS_ERP_REALM] || + info->attrs[NL80211_ATTR_FILS_ERP_NEXT_SEQ_NUM] || + info->attrs[NL80211_ATTR_FILS_ERP_RRK]) { + kzfree(connkeys); + return -EINVAL; + } + wdev_lock(dev->ieee80211_ptr); err = cfg80211_connect(rdev, dev, &connect, connkeys, NULL); wdev_unlock(dev->ieee80211_ptr); @@ -7959,6 +8583,76 @@ return err; } +static int nl80211_update_connect_params(struct sk_buff *skb, + struct genl_info *info) +{ + struct cfg80211_connect_params connect = {}; + struct cfg80211_registered_device *rdev = info->user_ptr[0]; + struct net_device *dev = info->user_ptr[1]; + struct wireless_dev *wdev = dev->ieee80211_ptr; + u32 changed = 0; + int ret; + + if (!rdev->ops->update_connect_params) + return -EOPNOTSUPP; + + if (info->attrs[NL80211_ATTR_IE]) { + if (!is_valid_ie_attr(info->attrs[NL80211_ATTR_IE])) + return -EINVAL; + connect.ie = nla_data(info->attrs[NL80211_ATTR_IE]); + connect.ie_len = nla_len(info->attrs[NL80211_ATTR_IE]); + changed |= UPDATE_ASSOC_IES; + } + + if (wiphy_ext_feature_isset(&rdev->wiphy, + NL80211_EXT_FEATURE_FILS_SK_OFFLOAD) && + info->attrs[NL80211_ATTR_FILS_ERP_USERNAME] && + info->attrs[NL80211_ATTR_FILS_ERP_REALM] && + info->attrs[NL80211_ATTR_FILS_ERP_NEXT_SEQ_NUM] && + info->attrs[NL80211_ATTR_FILS_ERP_RRK]) { + connect.fils_erp_username = + nla_data(info->attrs[NL80211_ATTR_FILS_ERP_USERNAME]); + connect.fils_erp_username_len = + nla_len(info->attrs[NL80211_ATTR_FILS_ERP_USERNAME]); + connect.fils_erp_realm = + nla_data(info->attrs[NL80211_ATTR_FILS_ERP_REALM]); + connect.fils_erp_realm_len = + nla_len(info->attrs[NL80211_ATTR_FILS_ERP_REALM]); + connect.fils_erp_next_seq_num = + nla_get_u16( + info->attrs[NL80211_ATTR_FILS_ERP_NEXT_SEQ_NUM]); + connect.fils_erp_rrk = + nla_data(info->attrs[NL80211_ATTR_FILS_ERP_RRK]); + connect.fils_erp_rrk_len = + nla_len(info->attrs[NL80211_ATTR_FILS_ERP_RRK]); + changed |= UPDATE_FILS_ERP_INFO; + } else if (info->attrs[NL80211_ATTR_FILS_ERP_USERNAME] || + info->attrs[NL80211_ATTR_FILS_ERP_REALM] || + info->attrs[NL80211_ATTR_FILS_ERP_NEXT_SEQ_NUM] || + info->attrs[NL80211_ATTR_FILS_ERP_RRK]) { + return -EINVAL; + } + + if (info->attrs[NL80211_ATTR_AUTH_TYPE]) { + u32 auth_type = + nla_get_u32(info->attrs[NL80211_ATTR_AUTH_TYPE]); + if (!nl80211_valid_auth_type(rdev, auth_type, + NL80211_CMD_CONNECT)) + return -EINVAL; + connect.auth_type = auth_type; + changed |= UPDATE_AUTH_TYPE; + } + + wdev_lock(dev->ieee80211_ptr); + if (!wdev->current_bss) + ret = -ENOLINK; + else + ret = rdev_update_connect_params(rdev, dev, &connect, changed); + wdev_unlock(dev->ieee80211_ptr); + + return ret; +} + static int nl80211_disconnect(struct sk_buff *skb, struct genl_info *info) { struct cfg80211_registered_device *rdev = info->user_ptr[0]; @@ -8025,14 +8719,28 @@ memset(&pmksa, 0, sizeof(struct cfg80211_pmksa)); - if (!info->attrs[NL80211_ATTR_MAC]) - return -EINVAL; - if (!info->attrs[NL80211_ATTR_PMKID]) return -EINVAL; pmksa.pmkid = nla_data(info->attrs[NL80211_ATTR_PMKID]); + + if (info->attrs[NL80211_ATTR_MAC]) { pmksa.bssid = nla_data(info->attrs[NL80211_ATTR_MAC]); + } else if (info->attrs[NL80211_ATTR_SSID] && + info->attrs[NL80211_ATTR_FILS_CACHE_ID] && + (info->genlhdr->cmd == NL80211_CMD_DEL_PMKSA || + info->attrs[NL80211_ATTR_PMK])) { + pmksa.ssid = nla_data(info->attrs[NL80211_ATTR_SSID]); + pmksa.ssid_len = nla_len(info->attrs[NL80211_ATTR_SSID]); + pmksa.cache_id = + nla_data(info->attrs[NL80211_ATTR_FILS_CACHE_ID]); + } else { + return -EINVAL; + } + if (info->attrs[NL80211_ATTR_PMK]) { + pmksa.pmk = nla_data(info->attrs[NL80211_ATTR_PMK]); + pmksa.pmk_len = nla_len(info->attrs[NL80211_ATTR_PMK]); + } if (dev->ieee80211_ptr->iftype != NL80211_IFTYPE_STATION && dev->ieee80211_ptr->iftype != NL80211_IFTYPE_P2P_CLIENT) @@ -8212,237 +8920,21 @@ return rdev_cancel_remain_on_channel(rdev, wdev, cookie); } -static u32 rateset_to_mask(struct ieee80211_supported_band *sband, - u8 *rates, u8 rates_len) -{ - u8 i; - u32 mask = 0; - - for (i = 0; i < rates_len; i++) { - int rate = (rates[i] & 0x7f) * 5; - int ridx; - for (ridx = 0; ridx < sband->n_bitrates; ridx++) { - struct ieee80211_rate *srate = - &sband->bitrates[ridx]; - if (rate == srate->bitrate) { - mask |= 1 << ridx; - break; - } - } - if (ridx == sband->n_bitrates) - return 0; /* rate not found */ - } - - return mask; -} - -static bool ht_rateset_to_mask(struct ieee80211_supported_band *sband, - u8 *rates, u8 rates_len, - u8 mcs[IEEE80211_HT_MCS_MASK_LEN]) -{ - u8 i; - - memset(mcs, 0, IEEE80211_HT_MCS_MASK_LEN); - - for (i = 0; i < rates_len; i++) { - int ridx, rbit; - - ridx = rates[i] / 8; - rbit = BIT(rates[i] % 8); - - /* check validity */ - if ((ridx < 0) || (ridx >= IEEE80211_HT_MCS_MASK_LEN)) - return false; - - /* check availability */ - if (sband->ht_cap.mcs.rx_mask[ridx] & rbit) - mcs[ridx] |= rbit; - else - return false; - } - - return true; -} - -static u16 vht_mcs_map_to_mcs_mask(u8 vht_mcs_map) -{ - u16 mcs_mask = 0; - - switch (vht_mcs_map) { - case IEEE80211_VHT_MCS_NOT_SUPPORTED: - break; - case IEEE80211_VHT_MCS_SUPPORT_0_7: - mcs_mask = 0x00FF; - break; - case IEEE80211_VHT_MCS_SUPPORT_0_8: - mcs_mask = 0x01FF; - break; - case IEEE80211_VHT_MCS_SUPPORT_0_9: - mcs_mask = 0x03FF; - break; - default: - break; - } - - return mcs_mask; -} - -static void vht_build_mcs_mask(u16 vht_mcs_map, - u16 vht_mcs_mask[NL80211_VHT_NSS_MAX]) -{ - u8 nss; - - for (nss = 0; nss < NL80211_VHT_NSS_MAX; nss++) { - vht_mcs_mask[nss] = vht_mcs_map_to_mcs_mask(vht_mcs_map & 0x03); - vht_mcs_map >>= 2; - } -} - -static bool vht_set_mcs_mask(struct ieee80211_supported_band *sband, - struct nl80211_txrate_vht *txrate, - u16 mcs[NL80211_VHT_NSS_MAX]) -{ - u16 tx_mcs_map = le16_to_cpu(sband->vht_cap.vht_mcs.tx_mcs_map); - u16 tx_mcs_mask[NL80211_VHT_NSS_MAX] = {}; - u8 i; - - if (!sband->vht_cap.vht_supported) - return false; - - memset(mcs, 0, sizeof(u16) * NL80211_VHT_NSS_MAX); - - /* Build vht_mcs_mask from VHT capabilities */ - vht_build_mcs_mask(tx_mcs_map, tx_mcs_mask); - - for (i = 0; i < NL80211_VHT_NSS_MAX; i++) { - if ((tx_mcs_mask[i] & txrate->mcs[i]) == txrate->mcs[i]) - mcs[i] = txrate->mcs[i]; - else - return false; - } - - return true; -} - -static const struct nla_policy nl80211_txattr_policy[NL80211_TXRATE_MAX + 1] = { - [NL80211_TXRATE_LEGACY] = { .type = NLA_BINARY, - .len = NL80211_MAX_SUPP_RATES }, - [NL80211_TXRATE_HT] = { .type = NLA_BINARY, - .len = NL80211_MAX_SUPP_HT_RATES }, - [NL80211_TXRATE_VHT] = { .len = sizeof(struct nl80211_txrate_vht)}, - [NL80211_TXRATE_GI] = { .type = NLA_U8 }, -}; - static int nl80211_set_tx_bitrate_mask(struct sk_buff *skb, struct genl_info *info) { - struct nlattr *tb[NL80211_TXRATE_MAX + 1]; - struct cfg80211_registered_device *rdev = info->user_ptr[0]; struct cfg80211_bitrate_mask mask; - int rem, i; + struct cfg80211_registered_device *rdev = info->user_ptr[0]; struct net_device *dev = info->user_ptr[1]; - struct nlattr *tx_rates; - struct ieee80211_supported_band *sband; - u16 vht_tx_mcs_map; + int err; if (!rdev->ops->set_bitrate_mask) return -EOPNOTSUPP; - memset(&mask, 0, sizeof(mask)); - /* Default to all rates enabled */ - for (i = 0; i < IEEE80211_NUM_BANDS; i++) { - sband = rdev->wiphy.bands[i]; - - if (!sband) - continue; - - mask.control[i].legacy = (1 << sband->n_bitrates) - 1; - memcpy(mask.control[i].ht_mcs, - sband->ht_cap.mcs.rx_mask, - sizeof(mask.control[i].ht_mcs)); - - if (!sband->vht_cap.vht_supported) - continue; - - vht_tx_mcs_map = le16_to_cpu(sband->vht_cap.vht_mcs.tx_mcs_map); - vht_build_mcs_mask(vht_tx_mcs_map, mask.control[i].vht_mcs); - } - - /* if no rates are given set it back to the defaults */ - if (!info->attrs[NL80211_ATTR_TX_RATES]) - goto out; - - /* - * The nested attribute uses enum nl80211_band as the index. This maps - * directly to the enum ieee80211_band values used in cfg80211. - */ - BUILD_BUG_ON(NL80211_MAX_SUPP_HT_RATES > IEEE80211_HT_MCS_MASK_LEN * 8); - nla_for_each_nested(tx_rates, info->attrs[NL80211_ATTR_TX_RATES], rem) { - enum ieee80211_band band = nla_type(tx_rates); - int err; - - if (band < 0 || band >= IEEE80211_NUM_BANDS) - return -EINVAL; - sband = rdev->wiphy.bands[band]; - if (sband == NULL) - return -EINVAL; - err = nla_parse(tb, NL80211_TXRATE_MAX, nla_data(tx_rates), - nla_len(tx_rates), nl80211_txattr_policy); + err = nl80211_parse_tx_bitrate_mask(info, &mask); if (err) return err; - if (tb[NL80211_TXRATE_LEGACY]) { - mask.control[band].legacy = rateset_to_mask( - sband, - nla_data(tb[NL80211_TXRATE_LEGACY]), - nla_len(tb[NL80211_TXRATE_LEGACY])); - if ((mask.control[band].legacy == 0) && - nla_len(tb[NL80211_TXRATE_LEGACY])) - return -EINVAL; - } - if (tb[NL80211_TXRATE_HT]) { - if (!ht_rateset_to_mask( - sband, - nla_data(tb[NL80211_TXRATE_HT]), - nla_len(tb[NL80211_TXRATE_HT]), - mask.control[band].ht_mcs)) - return -EINVAL; - } - if (tb[NL80211_TXRATE_VHT]) { - if (!vht_set_mcs_mask( - sband, - nla_data(tb[NL80211_TXRATE_VHT]), - mask.control[band].vht_mcs)) - return -EINVAL; - } - if (tb[NL80211_TXRATE_GI]) { - mask.control[band].gi = - nla_get_u8(tb[NL80211_TXRATE_GI]); - if (mask.control[band].gi > NL80211_TXRATE_FORCE_LGI) - return -EINVAL; - } - if (mask.control[band].legacy == 0) { - /* don't allow empty legacy rates if HT or VHT - * are not even supported. - */ - if (!(rdev->wiphy.bands[band]->ht_cap.ht_supported || - rdev->wiphy.bands[band]->vht_cap.vht_supported)) - return -EINVAL; - - for (i = 0; i < IEEE80211_HT_MCS_MASK_LEN; i++) - if (mask.control[band].ht_mcs[i]) - goto out; - - for (i = 0; i < NL80211_VHT_NSS_MAX; i++) - if (mask.control[band].vht_mcs[i]) - goto out; - - /* legacy and mcs rates may not be both empty */ - return -EINVAL; - } - } - -out: return rdev_set_bitrate_mask(rdev, dev, NULL, &mask); } @@ -8861,9 +9353,12 @@ if (info->attrs[NL80211_ATTR_BEACON_INTERVAL]) { setup.beacon_interval = nla_get_u32(info->attrs[NL80211_ATTR_BEACON_INTERVAL]); - if (setup.beacon_interval < 10 || - setup.beacon_interval > 10000) - return -EINVAL; + + err = cfg80211_validate_beacon_int(rdev, + NL80211_IFTYPE_MESH_POINT, + setup.beacon_interval); + if (err) + return err; } if (info->attrs[NL80211_ATTR_DTIM_PERIOD]) { @@ -8909,6 +9404,17 @@ return err; } + if (info->attrs[NL80211_ATTR_TX_RATES] && setup.chandef.chan != NULL) { + err = nl80211_parse_tx_bitrate_mask(info, &setup.beacon_rate); + if (err) + return err; + + err = validate_beacon_tx_rate(rdev, setup.chandef.chan->band, + &setup.beacon_rate); + if (err) + return err; + } + return cfg80211_join_mesh(rdev, dev, &setup, &cfg); } @@ -9018,6 +9524,20 @@ if (nla_put_u32(msg, NL80211_ATTR_SCHED_SCAN_DELAY, req->delay)) return -ENOBUFS; + if (req->relative_rssi_set) { + struct nl80211_bss_select_rssi_adjust rssi_adjust; + + if (nla_put_s8(msg, NL80211_ATTR_SCHED_SCAN_RELATIVE_RSSI, + req->relative_rssi)) + return -ENOBUFS; + + rssi_adjust.band = req->rssi_adjust.band; + rssi_adjust.delta = req->rssi_adjust.delta; + if (nla_put(msg, NL80211_ATTR_SCHED_SCAN_RSSI_ADJUST, + sizeof(rssi_adjust), &rssi_adjust)) + return -ENOBUFS; + } + freqs = nla_nest_start(msg, NL80211_ATTR_SCAN_FREQUENCIES); if (!freqs) return -ENOBUFS; @@ -9794,17 +10314,26 @@ if (err) return err; - if (!tb[NL80211_REKEY_DATA_REPLAY_CTR] || !tb[NL80211_REKEY_DATA_KEK] || - !tb[NL80211_REKEY_DATA_KCK]) + if (!tb[NL80211_REKEY_DATA_KEK] || !tb[NL80211_REKEY_DATA_REPLAY_CTR] || + (!wiphy_ext_feature_isset(&rdev->wiphy, + NL80211_EXT_FEATURE_FILS_SK_OFFLOAD) && + !wiphy_ext_feature_isset(&rdev->wiphy, + NL80211_EXT_FEATURE_FILS_STA) && + !tb[NL80211_REKEY_DATA_KCK])) return -EINVAL; + if (nla_len(tb[NL80211_REKEY_DATA_REPLAY_CTR]) != NL80211_REPLAY_CTR_LEN) return -ERANGE; - if (nla_len(tb[NL80211_REKEY_DATA_KEK]) != NL80211_KEK_LEN) + if (nla_len(tb[NL80211_REKEY_DATA_KEK]) < NL80211_KEK_LEN) return -ERANGE; - if (nla_len(tb[NL80211_REKEY_DATA_KCK]) != NL80211_KCK_LEN) + if (tb[NL80211_REKEY_DATA_KCK] && + nla_len(tb[NL80211_REKEY_DATA_KCK]) != NL80211_KCK_LEN) return -ERANGE; + memset(&rekey_data, 0, sizeof(rekey_data)); rekey_data.kek = nla_data(tb[NL80211_REKEY_DATA_KEK]); + rekey_data.kek_len = nla_len(tb[NL80211_REKEY_DATA_KEK]); + if (tb[NL80211_REKEY_DATA_KCK]) rekey_data.kck = nla_data(tb[NL80211_REKEY_DATA_KCK]); rekey_data.replay_ctr = nla_data(tb[NL80211_REKEY_DATA_REPLAY_CTR]); @@ -10010,6 +10539,7 @@ return -EOPNOTSUPP; if (!info->attrs[NL80211_ATTR_MDID] || + !info->attrs[NL80211_ATTR_IE] || !is_valid_ie_attr(info->attrs[NL80211_ATTR_IE])) return -EINVAL; @@ -10175,7 +10705,7 @@ *wdev = NULL; if (cb->args[1]) { - list_for_each_entry(tmp, &(*rdev)->wdev_list, list) { + list_for_each_entry(tmp, &wiphy->wdev_list, list) { if (tmp->identifier == cb->args[1] - 1) { *wdev = tmp; break; @@ -10949,6 +11479,14 @@ NL80211_FLAG_NEED_RTNL, }, { + .cmd = NL80211_CMD_ABORT_SCAN, + .doit = nl80211_abort_scan, + .policy = nl80211_policy, + .flags = GENL_ADMIN_PERM, + .internal_flags = NL80211_FLAG_NEED_WDEV_UP | + NL80211_FLAG_NEED_RTNL, + }, + { .cmd = NL80211_CMD_GET_SCAN, .policy = nl80211_policy, .dumpit = nl80211_dump_scan, @@ -11038,6 +11576,14 @@ NL80211_FLAG_NEED_RTNL, }, { + .cmd = NL80211_CMD_UPDATE_CONNECT_PARAMS, + .doit = nl80211_update_connect_params, + .policy = nl80211_policy, + .flags = GENL_ADMIN_PERM, + .internal_flags = NL80211_FLAG_NEED_NETDEV_UP | + NL80211_FLAG_NEED_RTNL, + }, + { .cmd = NL80211_CMD_DISCONNECT, .doit = nl80211_disconnect, .policy = nl80211_policy, @@ -11716,7 +12262,7 @@ struct sk_buff *msg; void *hdr; - msg = nlmsg_new(NLMSG_DEFAULT_SIZE, gfp); + msg = nlmsg_new(100 + len, gfp); if (!msg) return; @@ -11860,15 +12406,16 @@ } void nl80211_send_connect_result(struct cfg80211_registered_device *rdev, - struct net_device *netdev, const u8 *bssid, - const u8 *req_ie, size_t req_ie_len, - const u8 *resp_ie, size_t resp_ie_len, - u16 status, gfp_t gfp) + struct net_device *netdev, + struct cfg80211_connect_resp_params *cr, + gfp_t gfp) { struct sk_buff *msg; void *hdr; - msg = nlmsg_new(NLMSG_DEFAULT_SIZE, gfp); + msg = nlmsg_new(100 + cr->req_ie_len + cr->resp_ie_len + + cr->fils_kek_len + cr->pmk_len + + (cr->pmkid ? WLAN_PMKID_LEN : 0), gfp); if (!msg) return; @@ -11880,12 +12427,31 @@ if (nla_put_u32(msg, NL80211_ATTR_WIPHY, rdev->wiphy_idx) || nla_put_u32(msg, NL80211_ATTR_IFINDEX, netdev->ifindex) || - (bssid && nla_put(msg, NL80211_ATTR_MAC, ETH_ALEN, bssid)) || - nla_put_u16(msg, NL80211_ATTR_STATUS_CODE, status) || - (req_ie && - nla_put(msg, NL80211_ATTR_REQ_IE, req_ie_len, req_ie)) || - (resp_ie && - nla_put(msg, NL80211_ATTR_RESP_IE, resp_ie_len, resp_ie))) + (cr->bssid && + nla_put(msg, NL80211_ATTR_MAC, ETH_ALEN, cr->bssid)) || + nla_put_u16(msg, NL80211_ATTR_STATUS_CODE, + cr->status < 0 ? WLAN_STATUS_UNSPECIFIED_FAILURE : + cr->status) || + (cr->status < 0 && + (nla_put_flag(msg, NL80211_ATTR_TIMED_OUT) || + nla_put_u32(msg, NL80211_ATTR_TIMEOUT_REASON, + cr->timeout_reason))) || + (cr->req_ie && + nla_put(msg, NL80211_ATTR_REQ_IE, cr->req_ie_len, cr->req_ie)) || + (cr->resp_ie && + nla_put(msg, NL80211_ATTR_RESP_IE, cr->resp_ie_len, + cr->resp_ie)) || + (cr->update_erp_next_seq_num && + nla_put_u16(msg, NL80211_ATTR_FILS_ERP_NEXT_SEQ_NUM, + cr->fils_erp_next_seq_num)) || + (cr->status == WLAN_STATUS_SUCCESS && + ((cr->fils_kek && + nla_put(msg, NL80211_ATTR_FILS_KEK, cr->fils_kek_len, + cr->fils_kek)) || + (cr->pmk && + nla_put(msg, NL80211_ATTR_PMK, cr->pmk_len, cr->pmk)) || + (cr->pmkid && + nla_put(msg, NL80211_ATTR_PMKID, WLAN_PMKID_LEN, cr->pmkid))))) goto nla_put_failure; genlmsg_end(msg, hdr); @@ -11908,7 +12474,7 @@ struct sk_buff *msg; void *hdr; - msg = nlmsg_new(NLMSG_DEFAULT_SIZE, gfp); + msg = nlmsg_new(100 + req_ie_len + resp_ie_len, gfp); if (!msg) return; @@ -11946,7 +12512,7 @@ struct sk_buff *msg; void *hdr; - msg = nlmsg_new(NLMSG_DEFAULT_SIZE, GFP_KERNEL); + msg = nlmsg_new(100 + ie_len, GFP_KERNEL); if (!msg) return; @@ -12023,7 +12589,7 @@ trace_cfg80211_notify_new_peer_candidate(dev, addr); - msg = nlmsg_new(NLMSG_DEFAULT_SIZE, gfp); + msg = nlmsg_new(100 + ie_len, gfp); if (!msg) return; @@ -12392,7 +12958,7 @@ struct sk_buff *msg; void *hdr; - msg = nlmsg_new(NLMSG_DEFAULT_SIZE, gfp); + msg = nlmsg_new(100 + len, gfp); if (!msg) return -ENOMEM; @@ -12435,7 +13001,7 @@ trace_cfg80211_mgmt_tx_status(wdev, cookie, ack); - msg = nlmsg_new(NLMSG_DEFAULT_SIZE, gfp); + msg = nlmsg_new(100 + len, gfp); if (!msg) return; @@ -13180,7 +13746,7 @@ schedule_work(&rdev->sched_scan_stop_wk); } - list_for_each_entry_rcu(wdev, &rdev->wdev_list, list) { + list_for_each_entry_rcu(wdev, &rdev->wiphy.wdev_list, list) { cfg80211_mlme_unregister_socket(wdev, notify->portid); if (wdev->owner_nlportid == notify->portid) @@ -13239,7 +13805,7 @@ if (!ft_event->target_ap) return; - msg = nlmsg_new(NLMSG_DEFAULT_SIZE, GFP_KERNEL); + msg = nlmsg_new(100 + ft_event->ric_ies_len, GFP_KERNEL); if (!msg) return; @@ -13338,6 +13904,16 @@ nlmsg_free(msg); } +void cfg80211_ap_stopped(struct net_device *netdev, gfp_t gfp) +{ + struct wireless_dev *wdev = netdev->ieee80211_ptr; + struct cfg80211_registered_device *rdev = wiphy_to_rdev(wdev->wiphy); + + nl80211_send_mlme_event(rdev, netdev, NULL, 0, + NL80211_CMD_STOP_AP, gfp, -1); +} +EXPORT_SYMBOL(cfg80211_ap_stopped); + /* initialisation/exit functions */ int nl80211_init(void) diff -ruw linux-4.4.115/net/wireless/nl80211.h linux-4.4.115-fbx/net/wireless/nl80211.h --- linux-4.4.115/net/wireless/nl80211.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/net/wireless/nl80211.h 2019-01-22 16:16:29.247298422 +0100 @@ -52,10 +52,9 @@ struct net_device *netdev, const u8 *addr, gfp_t gfp); void nl80211_send_connect_result(struct cfg80211_registered_device *rdev, - struct net_device *netdev, const u8 *bssid, - const u8 *req_ie, size_t req_ie_len, - const u8 *resp_ie, size_t resp_ie_len, - u16 status, gfp_t gfp); + struct net_device *netdev, + struct cfg80211_connect_resp_params *params, + gfp_t gfp); void nl80211_send_roamed(struct cfg80211_registered_device *rdev, struct net_device *netdev, const u8 *bssid, const u8 *req_ie, size_t req_ie_len, diff -ruw linux-4.4.115/net/wireless/rdev-ops.h linux-4.4.115-fbx/net/wireless/rdev-ops.h --- linux-4.4.115/net/wireless/rdev-ops.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/net/wireless/rdev-ops.h 2019-10-29 09:26:26.009226332 +0100 @@ -427,6 +427,14 @@ return ret; } +static inline void rdev_abort_scan(struct cfg80211_registered_device *rdev, + struct wireless_dev *wdev) +{ + trace_rdev_abort_scan(&rdev->wiphy, wdev); + rdev->ops->abort_scan(&rdev->wiphy, wdev); + trace_rdev_return_void(&rdev->wiphy); +} + static inline int rdev_auth(struct cfg80211_registered_device *rdev, struct net_device *dev, struct cfg80211_auth_request *req) @@ -481,6 +489,18 @@ trace_rdev_return_int(&rdev->wiphy, ret); return ret; } + +static inline int +rdev_update_connect_params(struct cfg80211_registered_device *rdev, + struct net_device *dev, + struct cfg80211_connect_params *sme, u32 changed) +{ + int ret; + trace_rdev_update_connect_params(&rdev->wiphy, dev, sme, changed); + ret = rdev->ops->update_connect_params(&rdev->wiphy, dev, sme, changed); + trace_rdev_return_int(&rdev->wiphy, ret); + return ret; +} static inline int rdev_disconnect(struct cfg80211_registered_device *rdev, struct net_device *dev, u16 reason_code) diff -ruw linux-4.4.115/net/wireless/reg.c linux-4.4.115-fbx/net/wireless/reg.c --- linux-4.4.115/net/wireless/reg.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/net/wireless/reg.c 2019-10-29 09:26:26.009226332 +0100 @@ -425,6 +425,11 @@ return true; } +static bool is_cfg80211_regdom_intersected(void) +{ + return is_intersected_alpha2(get_cfg80211_regdom()->alpha2); +} + static const struct ieee80211_regdomain * reg_copy_regd(const struct ieee80211_regdomain *src_regd) { @@ -1676,12 +1681,48 @@ { struct wireless_dev *wdev; struct cfg80211_registered_device *rdev = wiphy_to_rdev(wiphy); + struct net_device *dev; + struct cfg80211_sched_scan_request *sched_scan_req; + ASSERT_RTNL(); + list_for_each_entry(wdev, &rdev->wiphy.wdev_list, list) + if (!reg_wdev_chan_valid(wiphy, wdev)) { + dev = wdev->netdev; + switch (wdev->iftype) { + case NL80211_IFTYPE_ADHOC: + cfg80211_leave_ibss(rdev, dev, true); + break; + case NL80211_IFTYPE_P2P_CLIENT: + case NL80211_IFTYPE_STATION: ASSERT_RTNL(); + sched_scan_req = rtnl_dereference(rdev->sched_scan_req); + if (sched_scan_req && dev == sched_scan_req->dev) + __cfg80211_stop_sched_scan(rdev, false); - list_for_each_entry(wdev, &rdev->wdev_list, list) - if (!reg_wdev_chan_valid(wiphy, wdev)) - cfg80211_leave(rdev, wdev); + wdev_lock(wdev); +#ifdef CONFIG_CFG80211_WEXT + kfree(wdev->wext.ie); + wdev->wext.ie = NULL; + wdev->wext.ie_len = 0; + wdev->wext.connect.auth_type = + NL80211_AUTHTYPE_AUTOMATIC; +#endif + cfg80211_disconnect(rdev, dev, + WLAN_REASON_DEAUTH_LEAVING, true); + cfg80211_mlme_down(rdev, dev); + wdev_unlock(wdev); + break; + case NL80211_IFTYPE_MESH_POINT: + cfg80211_leave_mesh(rdev, dev); + break; + case NL80211_IFTYPE_AP: + cfg80211_stop_ap(rdev, dev, false); + break; + default: + break; + } + wdev->beacon_interval = 0; + } } static void reg_check_chans_work(struct work_struct *work) @@ -1719,11 +1760,13 @@ if (ignore_reg_update(wiphy, initiator)) { /* * Regulatory updates set by CORE are ignored for custom - * regulatory cards. Let us notify the changes to the driver, + * regulatory cards and for self managed regulatory. + * Let us notify the changes to the driver, * as some drivers used this to restore its orig_* reg domain. */ - if (initiator == NL80211_REGDOM_SET_BY_CORE && - wiphy->regulatory_flags & REGULATORY_CUSTOM_REG) + if ((initiator == NL80211_REGDOM_SET_BY_CORE && + wiphy->regulatory_flags & REGULATORY_CUSTOM_REG) || + (wiphy->regulatory_flags & REGULATORY_WIPHY_SELF_MANAGED)) reg_call_notifier(wiphy, lr); return; } @@ -1941,9 +1984,14 @@ */ if ((lr->initiator == NL80211_REGDOM_SET_BY_CORE || lr->initiator == NL80211_REGDOM_SET_BY_DRIVER || - lr->initiator == NL80211_REGDOM_SET_BY_USER) && - regdom_changes(lr->alpha2)) + lr->initiator == NL80211_REGDOM_SET_BY_USER)) { + if (lr->intersect) { + if (!is_cfg80211_regdom_intersected()) + return REG_REQ_IGNORE; + } else if (regdom_changes(lr->alpha2)) { return REG_REQ_IGNORE; + } + } if (!regdom_changes(user_request->alpha2)) return REG_REQ_ALREADY_SET; @@ -2201,7 +2249,7 @@ reg_free_request(reg_request); } -static bool reg_only_self_managed_wiphys(void) +static bool reg_only_self_managed_wiphys(struct regulatory_request *reg_request) { struct cfg80211_registered_device *rdev; struct wiphy *wiphy; @@ -2211,11 +2259,13 @@ list_for_each_entry(rdev, &cfg80211_rdev_list, list) { wiphy = &rdev->wiphy; - if (wiphy->regulatory_flags & REGULATORY_WIPHY_SELF_MANAGED) + if (wiphy->regulatory_flags & REGULATORY_WIPHY_SELF_MANAGED) { self_managed_found = true; - else + reg_call_notifier(wiphy, reg_request); + } else { return false; } + } /* make sure at least one self-managed wiphy exists */ return self_managed_found; @@ -2252,7 +2302,7 @@ spin_unlock(®_requests_lock); - if (reg_only_self_managed_wiphys()) { + if (reg_only_self_managed_wiphys(reg_request)) { reg_free_request(reg_request); return; } @@ -2399,6 +2449,7 @@ return 0; } +EXPORT_SYMBOL(regulatory_hint_user); int regulatory_hint_indoor(bool is_indoor, u32 portid) { @@ -3200,6 +3251,34 @@ return reg_is_indoor; } +bool regulatory_pre_cac_allowed(struct wiphy *wiphy) +{ + const struct ieee80211_regdomain *regd = NULL; + const struct ieee80211_regdomain *wiphy_regd = NULL; + bool pre_cac_allowed = false; + + rcu_read_lock(); + + regd = rcu_dereference(cfg80211_regdomain); + wiphy_regd = rcu_dereference(wiphy->regd); + if (!wiphy_regd) { + if (regd->dfs_region == NL80211_DFS_ETSI) + pre_cac_allowed = true; + + rcu_read_unlock(); + + return pre_cac_allowed; + } + + if (regd->dfs_region == wiphy_regd->dfs_region && + wiphy_regd->dfs_region == NL80211_DFS_ETSI) + pre_cac_allowed = true; + + rcu_read_unlock(); + + return pre_cac_allowed; +} + int __init regulatory_init(void) { int err = 0; diff -ruw linux-4.4.115/net/wireless/reg.h linux-4.4.115-fbx/net/wireless/reg.h --- linux-4.4.115/net/wireless/reg.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/net/wireless/reg.h 2019-01-22 16:16:29.247298422 +0100 @@ -143,4 +143,18 @@ */ bool regulatory_indoor_allowed(void); +/* + * Grace period to timeout pre-CAC results on the dfs channels. This timeout + * value is used for Non-ETSI domain. + * TODO: May be make this timeout available through regdb? + */ +#define REG_PRE_CAC_EXPIRY_GRACE_MS 2000 + +/** + * regulatory_pre_cac_allowed - if pre-CAC allowed in the current dfs domain + * @wiphy: wiphy for which pre-CAC capability is checked. + + * Pre-CAC is allowed only in ETSI domain. + */ +bool regulatory_pre_cac_allowed(struct wiphy *wiphy); #endif /* __NET_WIRELESS_REG_H */ diff -ruw linux-4.4.115/net/wireless/scan.c linux-4.4.115-fbx/net/wireless/scan.c --- linux-4.4.115/net/wireless/scan.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/net/wireless/scan.c 2019-01-22 16:16:29.247298422 +0100 @@ -1362,6 +1362,8 @@ if (wiphy->bands[i]) creq->rates[i] = (1 << wiphy->bands[i]->n_bitrates) - 1; + eth_broadcast_addr(creq->bssid); + rdev->scan_req = creq; err = rdev_scan(rdev, creq); if (err) { diff -ruw linux-4.4.115/net/wireless/sme.c linux-4.4.115-fbx/net/wireless/sme.c --- linux-4.4.115/net/wireless/sme.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/net/wireless/sme.c 2019-10-29 09:26:26.009226332 +0100 @@ -34,10 +34,11 @@ CFG80211_CONN_SCAN_AGAIN, CFG80211_CONN_AUTHENTICATE_NEXT, CFG80211_CONN_AUTHENTICATING, - CFG80211_CONN_AUTH_FAILED, + CFG80211_CONN_AUTH_FAILED_TIMEOUT, CFG80211_CONN_ASSOCIATE_NEXT, CFG80211_CONN_ASSOCIATING, CFG80211_CONN_ASSOC_FAILED, + CFG80211_CONN_ASSOC_FAILED_TIMEOUT, CFG80211_CONN_DEAUTH, CFG80211_CONN_ABANDON, CFG80211_CONN_CONNECTED, @@ -48,6 +49,29 @@ bool auto_auth, prev_bssid_valid; }; +static bool cfg80211_is_all_countryie_ignore(void) +{ + struct cfg80211_registered_device *rdev; + struct wireless_dev *wdev; + bool is_all_countryie_ignore = true; + + list_for_each_entry(rdev, &cfg80211_rdev_list, list) { + list_for_each_entry(wdev, &rdev->wiphy.wdev_list, list) { + wdev_lock(wdev); + if (!(wdev->wiphy->regulatory_flags & + REGULATORY_COUNTRY_IE_IGNORE)) { + is_all_countryie_ignore = false; + wdev_unlock(wdev); + goto out; + } + wdev_unlock(wdev); + } + } + +out: + return is_all_countryie_ignore; +} + static void cfg80211_sme_free(struct wireless_dev *wdev) { if (!wdev->conn) @@ -120,6 +144,8 @@ wdev->conn->params.ssid_len); request->ssids[0].ssid_len = wdev->conn->params.ssid_len; + eth_broadcast_addr(request->bssid); + request->wdev = wdev; request->wiphy = &rdev->wiphy; request->scan_start = jiffies; @@ -138,7 +164,8 @@ return err; } -static int cfg80211_conn_do_work(struct wireless_dev *wdev) +static int cfg80211_conn_do_work(struct wireless_dev *wdev, + enum nl80211_timeout_reason *treason) { struct cfg80211_registered_device *rdev = wiphy_to_rdev(wdev->wiphy); struct cfg80211_connect_params *params; @@ -169,7 +196,8 @@ NULL, 0, params->key, params->key_len, params->key_idx, NULL, 0); - case CFG80211_CONN_AUTH_FAILED: + case CFG80211_CONN_AUTH_FAILED_TIMEOUT: + *treason = NL80211_TIMEOUT_AUTH; return -ENOTCONN; case CFG80211_CONN_ASSOCIATE_NEXT: if (WARN_ON(!rdev->ops->assoc)) @@ -196,6 +224,9 @@ WLAN_REASON_DEAUTH_LEAVING, false); return err; + case CFG80211_CONN_ASSOC_FAILED_TIMEOUT: + *treason = NL80211_TIMEOUT_ASSOC; + /* fall through */ case CFG80211_CONN_ASSOC_FAILED: cfg80211_mlme_deauth(rdev, wdev->netdev, params->bssid, NULL, 0, @@ -221,10 +252,11 @@ container_of(work, struct cfg80211_registered_device, conn_work); struct wireless_dev *wdev; u8 bssid_buf[ETH_ALEN], *bssid = NULL; + enum nl80211_timeout_reason treason; rtnl_lock(); - list_for_each_entry(wdev, &rdev->wdev_list, list) { + list_for_each_entry(wdev, &rdev->wiphy.wdev_list, list) { if (!wdev->netdev) continue; @@ -242,12 +274,15 @@ memcpy(bssid_buf, wdev->conn->params.bssid, ETH_ALEN); bssid = bssid_buf; } - if (cfg80211_conn_do_work(wdev)) { - __cfg80211_connect_result( - wdev->netdev, bssid, - NULL, 0, NULL, 0, - WLAN_STATUS_UNSPECIFIED_FAILURE, - false, NULL); + treason = NL80211_TIMEOUT_UNSPECIFIED; + if (cfg80211_conn_do_work(wdev, &treason)) { + struct cfg80211_connect_resp_params cr; + + memset(&cr, 0, sizeof(cr)); + cr.status = -1; + cr.bssid = bssid; + cr.timeout_reason = treason; + __cfg80211_connect_result(wdev->netdev, &cr, false); } wdev_unlock(wdev); } @@ -267,7 +302,7 @@ wdev->conn->params.bssid, wdev->conn->params.ssid, wdev->conn->params.ssid_len, - IEEE80211_BSS_TYPE_ESS, + wdev->conn_bss_type, IEEE80211_PRIVACY(wdev->conn->params.privacy)); if (!bss) return NULL; @@ -350,9 +385,13 @@ wdev->conn->state = CFG80211_CONN_AUTHENTICATE_NEXT; schedule_work(&rdev->conn_work); } else if (status_code != WLAN_STATUS_SUCCESS) { - __cfg80211_connect_result(wdev->netdev, mgmt->bssid, - NULL, 0, NULL, 0, - status_code, false, NULL); + struct cfg80211_connect_resp_params cr; + + memset(&cr, 0, sizeof(cr)); + cr.status = status_code; + cr.bssid = mgmt->bssid; + cr.timeout_reason = NL80211_TIMEOUT_UNSPECIFIED; + __cfg80211_connect_result(wdev->netdev, &cr, false); } else if (wdev->conn->state == CFG80211_CONN_AUTHENTICATING) { wdev->conn->state = CFG80211_CONN_ASSOCIATE_NEXT; schedule_work(&rdev->conn_work); @@ -400,7 +439,7 @@ if (!wdev->conn) return; - wdev->conn->state = CFG80211_CONN_AUTH_FAILED; + wdev->conn->state = CFG80211_CONN_AUTH_FAILED_TIMEOUT; schedule_work(&rdev->conn_work); } @@ -422,7 +461,7 @@ if (!wdev->conn) return; - wdev->conn->state = CFG80211_CONN_ASSOC_FAILED; + wdev->conn->state = CFG80211_CONN_ASSOC_FAILED_TIMEOUT; schedule_work(&rdev->conn_work); } @@ -554,7 +593,9 @@ /* we're good if we have a matching bss struct */ if (bss) { - err = cfg80211_conn_do_work(wdev); + enum nl80211_timeout_reason treason; + + err = cfg80211_conn_do_work(wdev, &treason); cfg80211_put_bss(wdev->wiphy, bss); } else { /* otherwise we'll need to scan for the AP first */ @@ -619,7 +660,7 @@ * count as new regulatory hints. */ list_for_each_entry(rdev, &cfg80211_rdev_list, list) { - list_for_each_entry(wdev, &rdev->wdev_list, list) { + list_for_each_entry(wdev, &rdev->wiphy.wdev_list, list) { wdev_lock(wdev); if (wdev->conn || wdev->current_bss) is_all_idle = false; @@ -633,7 +674,8 @@ static void disconnect_work(struct work_struct *work) { rtnl_lock(); - if (cfg80211_is_all_idle()) + if (cfg80211_is_all_idle() && + !cfg80211_is_all_countryie_ignore()) regulatory_hint_disconnect(); rtnl_unlock(); } @@ -647,11 +689,9 @@ */ /* This method must consume bss one way or another */ -void __cfg80211_connect_result(struct net_device *dev, const u8 *bssid, - const u8 *req_ie, size_t req_ie_len, - const u8 *resp_ie, size_t resp_ie_len, - u16 status, bool wextev, - struct cfg80211_bss *bss) +void __cfg80211_connect_result(struct net_device *dev, + struct cfg80211_connect_resp_params *cr, + bool wextev) { struct wireless_dev *wdev = dev->ieee80211_ptr; const u8 *country_ie; @@ -663,48 +703,48 @@ if (WARN_ON(wdev->iftype != NL80211_IFTYPE_STATION && wdev->iftype != NL80211_IFTYPE_P2P_CLIENT)) { - cfg80211_put_bss(wdev->wiphy, bss); + cfg80211_put_bss(wdev->wiphy, cr->bss); return; } - nl80211_send_connect_result(wiphy_to_rdev(wdev->wiphy), dev, - bssid, req_ie, req_ie_len, - resp_ie, resp_ie_len, - status, GFP_KERNEL); + nl80211_send_connect_result(wiphy_to_rdev(wdev->wiphy), dev, cr, + GFP_KERNEL); #ifdef CONFIG_CFG80211_WEXT if (wextev) { - if (req_ie && status == WLAN_STATUS_SUCCESS) { + if (cr->req_ie && cr->status == WLAN_STATUS_SUCCESS) { memset(&wrqu, 0, sizeof(wrqu)); - wrqu.data.length = req_ie_len; - wireless_send_event(dev, IWEVASSOCREQIE, &wrqu, req_ie); + wrqu.data.length = cr->req_ie_len; + wireless_send_event(dev, IWEVASSOCREQIE, &wrqu, + cr->req_ie); } - if (resp_ie && status == WLAN_STATUS_SUCCESS) { + if (cr->resp_ie && cr->status == WLAN_STATUS_SUCCESS) { memset(&wrqu, 0, sizeof(wrqu)); - wrqu.data.length = resp_ie_len; - wireless_send_event(dev, IWEVASSOCRESPIE, &wrqu, resp_ie); + wrqu.data.length = cr->resp_ie_len; + wireless_send_event(dev, IWEVASSOCRESPIE, &wrqu, + cr->resp_ie); } memset(&wrqu, 0, sizeof(wrqu)); wrqu.ap_addr.sa_family = ARPHRD_ETHER; - if (bssid && status == WLAN_STATUS_SUCCESS) { - memcpy(wrqu.ap_addr.sa_data, bssid, ETH_ALEN); - memcpy(wdev->wext.prev_bssid, bssid, ETH_ALEN); + if (cr->bssid && cr->status == WLAN_STATUS_SUCCESS) { + memcpy(wrqu.ap_addr.sa_data, cr->bssid, ETH_ALEN); + memcpy(wdev->wext.prev_bssid, cr->bssid, ETH_ALEN); wdev->wext.prev_bssid_valid = true; } wireless_send_event(dev, SIOCGIWAP, &wrqu, NULL); } #endif - if (!bss && (status == WLAN_STATUS_SUCCESS)) { + if (!cr->bss && (cr->status == WLAN_STATUS_SUCCESS)) { WARN_ON_ONCE(!wiphy_to_rdev(wdev->wiphy)->ops->connect); - bss = cfg80211_get_bss(wdev->wiphy, NULL, bssid, + cr->bss = cfg80211_get_bss(wdev->wiphy, NULL, cr->bssid, wdev->ssid, wdev->ssid_len, - IEEE80211_BSS_TYPE_ESS, + wdev->conn_bss_type, IEEE80211_PRIVACY_ANY); - if (bss) - cfg80211_hold_bss(bss_from_pub(bss)); + if (cr->bss) + cfg80211_hold_bss(bss_from_pub(cr->bss)); } if (wdev->current_bss) { @@ -713,27 +753,27 @@ wdev->current_bss = NULL; } - if (status != WLAN_STATUS_SUCCESS) { + if (cr->status != WLAN_STATUS_SUCCESS) { kzfree(wdev->connect_keys); wdev->connect_keys = NULL; wdev->ssid_len = 0; - if (bss) { - cfg80211_unhold_bss(bss_from_pub(bss)); - cfg80211_put_bss(wdev->wiphy, bss); + if (cr->bss) { + cfg80211_unhold_bss(bss_from_pub(cr->bss)); + cfg80211_put_bss(wdev->wiphy, cr->bss); } cfg80211_sme_free(wdev); return; } - if (WARN_ON(!bss)) + if (WARN_ON(!cr->bss)) return; - wdev->current_bss = bss_from_pub(bss); + wdev->current_bss = bss_from_pub(cr->bss); cfg80211_upload_connect_keys(wdev); rcu_read_lock(); - country_ie = ieee80211_bss_get_ie(bss, WLAN_EID_COUNTRY); + country_ie = ieee80211_bss_get_ie(cr->bss, WLAN_EID_COUNTRY); if (!country_ie) { rcu_read_unlock(); return; @@ -750,46 +790,95 @@ * - country_ie + 2, the start of the country ie data, and * - and country_ie[1] which is the IE length */ - regulatory_hint_country_ie(wdev->wiphy, bss->channel->band, + regulatory_hint_country_ie(wdev->wiphy, cr->bss->channel->band, country_ie + 2, country_ie[1]); kfree(country_ie); } -void cfg80211_connect_result(struct net_device *dev, const u8 *bssid, - const u8 *req_ie, size_t req_ie_len, - const u8 *resp_ie, size_t resp_ie_len, - u16 status, gfp_t gfp) +/* Consumes bss object one way or another */ +void cfg80211_connect_done(struct net_device *dev, + struct cfg80211_connect_resp_params *params, + gfp_t gfp) { struct wireless_dev *wdev = dev->ieee80211_ptr; struct cfg80211_registered_device *rdev = wiphy_to_rdev(wdev->wiphy); struct cfg80211_event *ev; unsigned long flags; + u8 *next; - ev = kzalloc(sizeof(*ev) + req_ie_len + resp_ie_len, gfp); - if (!ev) + if (params->bss) { + /* Make sure the bss entry provided by the driver is valid. */ + struct cfg80211_internal_bss *ibss = bss_from_pub(params->bss); + + if (WARN_ON(list_empty(&ibss->list))) { + cfg80211_put_bss(wdev->wiphy, params->bss); return; + } + } - ev->type = EVENT_CONNECT_RESULT; - if (bssid) - memcpy(ev->cr.bssid, bssid, ETH_ALEN); - if (req_ie_len) { - ev->cr.req_ie = ((u8 *)ev) + sizeof(*ev); - ev->cr.req_ie_len = req_ie_len; - memcpy((void *)ev->cr.req_ie, req_ie, req_ie_len); - } - if (resp_ie_len) { - ev->cr.resp_ie = ((u8 *)ev) + sizeof(*ev) + req_ie_len; - ev->cr.resp_ie_len = resp_ie_len; - memcpy((void *)ev->cr.resp_ie, resp_ie, resp_ie_len); + ev = kzalloc(sizeof(*ev) + (params->bssid ? ETH_ALEN : 0) + + params->req_ie_len + params->resp_ie_len + + params->fils_kek_len + params->pmk_len + + (params->pmkid ? WLAN_PMKID_LEN : 0), gfp); + if (!ev) { + cfg80211_put_bss(wdev->wiphy, params->bss); + return; } - ev->cr.status = status; + + ev->type = EVENT_CONNECT_RESULT; + next = ((u8 *)ev) + sizeof(*ev); + if (params->bssid) { + ev->cr.bssid = next; + memcpy((void *)ev->cr.bssid, params->bssid, ETH_ALEN); + next += ETH_ALEN; + } + if (params->req_ie_len) { + ev->cr.req_ie = next; + ev->cr.req_ie_len = params->req_ie_len; + memcpy((void *)ev->cr.req_ie, params->req_ie, + params->req_ie_len); + next += params->req_ie_len; + } + if (params->resp_ie_len) { + ev->cr.resp_ie = next; + ev->cr.resp_ie_len = params->resp_ie_len; + memcpy((void *)ev->cr.resp_ie, params->resp_ie, + params->resp_ie_len); + next += params->resp_ie_len; + } + if (params->fils_kek_len) { + ev->cr.fils_kek = next; + ev->cr.fils_kek_len = params->fils_kek_len; + memcpy((void *)ev->cr.fils_kek, params->fils_kek, + params->fils_kek_len); + next += params->fils_kek_len; + } + if (params->pmk_len) { + ev->cr.pmk = next; + ev->cr.pmk_len = params->pmk_len; + memcpy((void *)ev->cr.pmk, params->pmk, params->pmk_len); + next += params->pmk_len; + } + if (params->pmkid) { + ev->cr.pmkid = next; + memcpy((void *)ev->cr.pmkid, params->pmkid, WLAN_PMKID_LEN); + next += WLAN_PMKID_LEN; + } + ev->cr.update_erp_next_seq_num = params->update_erp_next_seq_num; + if (params->update_erp_next_seq_num) + ev->cr.fils_erp_next_seq_num = params->fils_erp_next_seq_num; + if (params->bss) + cfg80211_hold_bss(bss_from_pub(params->bss)); + ev->cr.bss = params->bss; + ev->cr.status = params->status; + ev->cr.timeout_reason = params->timeout_reason; spin_lock_irqsave(&wdev->event_lock, flags); list_add_tail(&ev->list, &wdev->event_list); spin_unlock_irqrestore(&wdev->event_lock, flags); queue_work(cfg80211_wq, &rdev->event_work); } -EXPORT_SYMBOL(cfg80211_connect_result); +EXPORT_SYMBOL(cfg80211_connect_done); /* Consumes bss object one way or another */ void __cfg80211_roamed(struct wireless_dev *wdev, @@ -860,7 +949,7 @@ bss = cfg80211_get_bss(wdev->wiphy, channel, bssid, wdev->ssid, wdev->ssid_len, - IEEE80211_BSS_TYPE_ESS, IEEE80211_PRIVACY_ANY); + wdev->conn_bss_type, IEEE80211_PRIVACY_ANY); if (WARN_ON(!bss)) return; @@ -1031,6 +1120,9 @@ memcpy(wdev->ssid, connect->ssid, connect->ssid_len); wdev->ssid_len = connect->ssid_len; + wdev->conn_bss_type = connect->pbss ? IEEE80211_BSS_TYPE_PBSS : + IEEE80211_BSS_TYPE_ESS; + if (!rdev->ops->connect) err = cfg80211_sme_connect(wdev, connect, prev_bssid); else diff -ruw linux-4.4.115/net/wireless/sysfs.c linux-4.4.115-fbx/net/wireless/sysfs.c --- linux-4.4.115/net/wireless/sysfs.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/net/wireless/sysfs.c 2019-01-22 16:16:29.247298422 +0100 @@ -87,14 +87,6 @@ } #ifdef CONFIG_PM_SLEEP -static void cfg80211_leave_all(struct cfg80211_registered_device *rdev) -{ - struct wireless_dev *wdev; - - list_for_each_entry(wdev, &rdev->wdev_list, list) - cfg80211_leave(rdev, wdev); -} - static int wiphy_suspend(struct device *dev) { struct cfg80211_registered_device *rdev = dev_to_rdev(dev); @@ -103,17 +95,9 @@ rdev->suspend_at = get_seconds(); rtnl_lock(); - if (rdev->wiphy.registered) { - if (!rdev->wiphy.wowlan_config) - cfg80211_leave_all(rdev); + if (rdev->wiphy.registered) if (rdev->ops->suspend) ret = rdev_suspend(rdev, rdev->wiphy.wowlan_config); - if (ret == 1) { - /* Driver refuse to configure wowlan */ - cfg80211_leave_all(rdev); - ret = rdev_suspend(rdev, NULL); - } - } rtnl_unlock(); return ret; diff -ruw linux-4.4.115/net/wireless/trace.h linux-4.4.115-fbx/net/wireless/trace.h --- linux-4.4.115/net/wireless/trace.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/net/wireless/trace.h 2019-10-29 09:26:26.013226371 +0100 @@ -1221,6 +1221,7 @@ __field(bool, privacy) __field(u32, wpa_versions) __field(u32, flags) + MAC_ENTRY(prev_bssid) ), TP_fast_assign( WIPHY_ASSIGN; @@ -1232,13 +1233,32 @@ __entry->privacy = sme->privacy; __entry->wpa_versions = sme->crypto.wpa_versions; __entry->flags = sme->flags; + MAC_ASSIGN(prev_bssid, sme->prev_bssid); ), TP_printk(WIPHY_PR_FMT ", " NETDEV_PR_FMT ", bssid: " MAC_PR_FMT ", ssid: %s, auth type: %d, privacy: %s, wpa versions: %u, " - "flags: %u", + "flags: %u, previous bssid: " MAC_PR_FMT, WIPHY_PR_ARG, NETDEV_PR_ARG, MAC_PR_ARG(bssid), __entry->ssid, __entry->auth_type, BOOL_TO_STR(__entry->privacy), - __entry->wpa_versions, __entry->flags) + __entry->wpa_versions, __entry->flags, MAC_PR_ARG(prev_bssid)) +); + +TRACE_EVENT(rdev_update_connect_params, + TP_PROTO(struct wiphy *wiphy, struct net_device *netdev, + struct cfg80211_connect_params *sme, u32 changed), + TP_ARGS(wiphy, netdev, sme, changed), + TP_STRUCT__entry( + WIPHY_ENTRY + NETDEV_ENTRY + __field(u32, changed) + ), + TP_fast_assign( + WIPHY_ASSIGN; + NETDEV_ASSIGN; + __entry->changed = changed; + ), + TP_printk(WIPHY_PR_FMT ", " NETDEV_PR_FMT ", parameters changed: %u", + WIPHY_PR_ARG, NETDEV_PR_ARG, __entry->changed) ); TRACE_EVENT(rdev_set_cqm_rssi_config, @@ -2803,6 +2823,11 @@ WIPHY_PR_ARG, NETDEV_PR_ARG, MAC_PR_ARG(target_ap)) ); +DEFINE_EVENT(wiphy_wdev_evt, rdev_abort_scan, + TP_PROTO(struct wiphy *wiphy, struct wireless_dev *wdev), + TP_ARGS(wiphy, wdev) +); + TRACE_EVENT(cfg80211_stop_iface, TP_PROTO(struct wiphy *wiphy, struct wireless_dev *wdev), TP_ARGS(wiphy, wdev), diff -ruw linux-4.4.115/net/wireless/util.c linux-4.4.115-fbx/net/wireless/util.c --- linux-4.4.115/net/wireless/util.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/net/wireless/util.c 2019-10-29 09:26:26.013226371 +0100 @@ -13,6 +13,7 @@ #include #include #include +#include #include "core.h" #include "rdev-ops.h" @@ -857,7 +858,6 @@ { struct cfg80211_event *ev; unsigned long flags; - const u8 *bssid = NULL; spin_lock_irqsave(&wdev->event_lock, flags); while (!list_empty(&wdev->event_list)) { @@ -869,15 +869,10 @@ wdev_lock(wdev); switch (ev->type) { case EVENT_CONNECT_RESULT: - if (!is_zero_ether_addr(ev->cr.bssid)) - bssid = ev->cr.bssid; __cfg80211_connect_result( - wdev->netdev, bssid, - ev->cr.req_ie, ev->cr.req_ie_len, - ev->cr.resp_ie, ev->cr.resp_ie_len, - ev->cr.status, - ev->cr.status == WLAN_STATUS_SUCCESS, - NULL); + wdev->netdev, + &ev->cr, + ev->cr.status == WLAN_STATUS_SUCCESS); break; case EVENT_ROAMED: __cfg80211_roamed(wdev, ev->rm.bss, ev->rm.req_ie, @@ -913,7 +908,7 @@ ASSERT_RTNL(); - list_for_each_entry(wdev, &rdev->wdev_list, list) + list_for_each_entry(wdev, &rdev->wiphy.wdev_list, list) cfg80211_process_wdev_events(wdev); } @@ -1082,7 +1077,7 @@ 58500000, 65000000, 78000000, - 0, + 86500000, }, { 13500000, 27000000, @@ -1485,31 +1480,57 @@ } EXPORT_SYMBOL(ieee80211_chandef_to_operating_class); -int cfg80211_validate_beacon_int(struct cfg80211_registered_device *rdev, - u32 beacon_int) +static void cfg80211_calculate_bi_data(struct wiphy *wiphy, u32 new_beacon_int, + u32 *beacon_int_gcd, + bool *beacon_int_different) { struct wireless_dev *wdev; - int res = 0; - if (!beacon_int) - return -EINVAL; + *beacon_int_gcd = 0; + *beacon_int_different = false; - list_for_each_entry(wdev, &rdev->wdev_list, list) { + list_for_each_entry(wdev, &wiphy->wdev_list, list) { if (!wdev->beacon_interval) continue; - if (wdev->beacon_interval != beacon_int) { - res = -EINVAL; - break; + + if (!*beacon_int_gcd) { + *beacon_int_gcd = wdev->beacon_interval; + continue; + } + + if (wdev->beacon_interval == *beacon_int_gcd) + continue; + + *beacon_int_different = true; + *beacon_int_gcd = gcd(*beacon_int_gcd, wdev->beacon_interval); + } + + if (new_beacon_int && *beacon_int_gcd != new_beacon_int) { + if (*beacon_int_gcd) + *beacon_int_different = true; + *beacon_int_gcd = gcd(*beacon_int_gcd, new_beacon_int); } } - return res; +int cfg80211_validate_beacon_int(struct cfg80211_registered_device *rdev, + enum nl80211_iftype iftype, u32 beacon_int) +{ + /* + * This is just a basic pre-condition check; if interface combinations + * are possible the driver must already be checking those with a call + * to cfg80211_check_combinations(), in which case we'll validate more + * through the cfg80211_calculate_bi_data() call and code in + * cfg80211_iter_combinations(). + */ + + if (beacon_int < 10 || beacon_int > 10000) + return -EINVAL; + + return 0; } int cfg80211_iter_combinations(struct wiphy *wiphy, - const int num_different_channels, - const u8 radar_detect, - const int iftype_num[NUM_NL80211_IFTYPES], + struct iface_combination_params *params, void (*iter)(const struct ieee80211_iface_combination *c, void *data), void *data) @@ -1519,8 +1540,23 @@ int i, j, iftype; int num_interfaces = 0; u32 used_iftypes = 0; + u32 beacon_int_gcd; + bool beacon_int_different; + + /* + * This is a bit strange, since the iteration used to rely only on + * the data given by the driver, but here it now relies on context, + * in form of the currently operating interfaces. + * This is OK for all current users, and saves us from having to + * push the GCD calculations into all the drivers. + * In the future, this should probably rely more on data that's in + * cfg80211 already - the only thing not would appear to be any new + * interfaces (while being brought up) and channel/radar data. + */ + cfg80211_calculate_bi_data(wiphy, params->new_beacon_int, + &beacon_int_gcd, &beacon_int_different); - if (radar_detect) { + if (params->radar_detect) { rcu_read_lock(); regdom = rcu_dereference(cfg80211_regdomain); if (regdom) @@ -1529,8 +1565,8 @@ } for (iftype = 0; iftype < NUM_NL80211_IFTYPES; iftype++) { - num_interfaces += iftype_num[iftype]; - if (iftype_num[iftype] > 0 && + num_interfaces += params->iftype_num[iftype]; + if (params->iftype_num[iftype] > 0 && !(wiphy->software_iftypes & BIT(iftype))) used_iftypes |= BIT(iftype); } @@ -1544,7 +1580,7 @@ if (num_interfaces > c->max_interfaces) continue; - if (num_different_channels > c->num_different_channels) + if (params->num_different_channels > c->num_different_channels) continue; limits = kmemdup(c->limits, sizeof(limits[0]) * c->n_limits, @@ -1559,16 +1595,17 @@ all_iftypes |= limits[j].types; if (!(limits[j].types & BIT(iftype))) continue; - if (limits[j].max < iftype_num[iftype]) + if (limits[j].max < params->iftype_num[iftype]) goto cont; - limits[j].max -= iftype_num[iftype]; + limits[j].max -= params->iftype_num[iftype]; } } - if (radar_detect != (c->radar_detect_widths & radar_detect)) + if (params->radar_detect != + (c->radar_detect_widths & params->radar_detect)) goto cont; - if (radar_detect && c->radar_detect_regions && + if (params->radar_detect && c->radar_detect_regions && !(c->radar_detect_regions & BIT(region))) goto cont; @@ -1580,6 +1617,14 @@ if ((all_iftypes & used_iftypes) != used_iftypes) goto cont; + if (beacon_int_gcd) { + if (c->beacon_int_min_gcd && + beacon_int_gcd < c->beacon_int_min_gcd) + goto cont; + if (!c->beacon_int_min_gcd && beacon_int_different) + goto cont; + } + /* This combination covered all interface types and * supported the requested numbers, so we're good. */ @@ -1602,14 +1647,11 @@ } int cfg80211_check_combinations(struct wiphy *wiphy, - const int num_different_channels, - const u8 radar_detect, - const int iftype_num[NUM_NL80211_IFTYPES]) + struct iface_combination_params *params) { int err, num = 0; - err = cfg80211_iter_combinations(wiphy, num_different_channels, - radar_detect, iftype_num, + err = cfg80211_iter_combinations(wiphy, params, cfg80211_iter_sum_ifcombs, &num); if (err) return err; @@ -1628,14 +1670,15 @@ u8 radar_detect) { struct wireless_dev *wdev_iter; - int num[NUM_NL80211_IFTYPES]; struct ieee80211_channel *used_channels[CFG80211_MAX_NUM_DIFFERENT_CHANNELS]; struct ieee80211_channel *ch; enum cfg80211_chan_mode chmode; - int num_different_channels = 0; int total = 1; int i; + struct iface_combination_params params = { + .radar_detect = radar_detect, + }; ASSERT_RTNL(); @@ -1652,10 +1695,9 @@ return 0; } - memset(num, 0, sizeof(num)); memset(used_channels, 0, sizeof(used_channels)); - num[iftype] = 1; + params.iftype_num[iftype] = 1; /* TODO: We'll probably not need this anymore, since this * should only be called with CHAN_MODE_UNDEFINED. There are @@ -1668,14 +1710,14 @@ case CHAN_MODE_SHARED: WARN_ON(!chan); used_channels[0] = chan; - num_different_channels++; + params.num_different_channels++; break; case CHAN_MODE_EXCLUSIVE: - num_different_channels++; + params.num_different_channels++; break; } - list_for_each_entry(wdev_iter, &rdev->wdev_list, list) { + list_for_each_entry(wdev_iter, &rdev->wiphy.wdev_list, list) { if (wdev_iter == wdev) continue; if (wdev_iter->iftype == NL80211_IFTYPE_P2P_DEVICE) { @@ -1699,7 +1741,8 @@ */ mutex_lock_nested(&wdev_iter->mtx, 1); __acquire(wdev_iter->mtx); - cfg80211_get_chan_state(wdev_iter, &ch, &chmode, &radar_detect); + cfg80211_get_chan_state(wdev_iter, &ch, &chmode, + ¶ms.radar_detect); wdev_unlock(wdev_iter); switch (chmode) { @@ -1715,23 +1758,22 @@ if (used_channels[i] == NULL) { used_channels[i] = ch; - num_different_channels++; + params.num_different_channels++; } break; case CHAN_MODE_EXCLUSIVE: - num_different_channels++; + params.num_different_channels++; break; } - num[wdev_iter->iftype]++; + params.iftype_num[wdev_iter->iftype]++; total++; } - if (total == 1 && !radar_detect) + if (total == 1 && !params.radar_detect) return 0; - return cfg80211_check_combinations(&rdev->wiphy, num_different_channels, - radar_detect, num); + return cfg80211_check_combinations(&rdev->wiphy, ¶ms); } int ieee80211_get_ratemask(struct ieee80211_supported_band *sband, @@ -1813,3 +1855,54 @@ const unsigned char bridge_tunnel_header[] __aligned(2) = { 0xaa, 0xaa, 0x03, 0x00, 0x00, 0xf8 }; EXPORT_SYMBOL(bridge_tunnel_header); + +bool cfg80211_is_gratuitous_arp_unsolicited_na(struct sk_buff *skb) +{ + const struct ethhdr *eth = (void *)skb->data; + const struct { + struct arphdr hdr; + u8 ar_sha[ETH_ALEN]; + u8 ar_sip[4]; + u8 ar_tha[ETH_ALEN]; + u8 ar_tip[4]; + } __packed *arp; + const struct ipv6hdr *ipv6; + const struct icmp6hdr *icmpv6; + + switch (eth->h_proto) { + case cpu_to_be16(ETH_P_ARP): + /* can't say - but will probably be dropped later anyway */ + if (!pskb_may_pull(skb, sizeof(*eth) + sizeof(*arp))) + return false; + + arp = (void *)(eth + 1); + + if ((arp->hdr.ar_op == cpu_to_be16(ARPOP_REPLY) || + arp->hdr.ar_op == cpu_to_be16(ARPOP_REQUEST)) && + !memcmp(arp->ar_sip, arp->ar_tip, sizeof(arp->ar_sip))) + return true; + break; + case cpu_to_be16(ETH_P_IPV6): + /* can't say - but will probably be dropped later anyway */ + if (!pskb_may_pull(skb, sizeof(*eth) + sizeof(*ipv6) + + sizeof(*icmpv6))) + return false; + + ipv6 = (void *)(eth + 1); + icmpv6 = (void *)(ipv6 + 1); + + if (icmpv6->icmp6_type == NDISC_NEIGHBOUR_ADVERTISEMENT && + !memcmp(&ipv6->saddr, &ipv6->daddr, sizeof(ipv6->saddr))) + return true; + break; + default: + /* + * no need to support other protocols, proxy service isn't + * specified for any others + */ + break; + } + + return false; +} +EXPORT_SYMBOL(cfg80211_is_gratuitous_arp_unsolicited_na); diff -ruw linux-4.4.115/net/xfrm/xfrm_algo.c linux-4.4.115-fbx/net/xfrm/xfrm_algo.c --- linux-4.4.115/net/xfrm/xfrm_algo.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/net/xfrm/xfrm_algo.c 2019-01-22 16:16:29.255298494 +0100 @@ -239,7 +239,7 @@ .uinfo = { .auth = { - .icv_truncbits = 96, + .icv_truncbits = 128, .icv_fullbits = 256, } }, diff -ruw linux-4.4.115/net/xfrm/xfrm_output.c linux-4.4.115-fbx/net/xfrm/xfrm_output.c --- linux-4.4.115/net/xfrm/xfrm_output.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/net/xfrm/xfrm_output.c 2019-01-22 16:16:29.255298494 +0100 @@ -66,6 +66,9 @@ goto error_nolock; } + if (x->props.output_mark) + skb->mark = x->props.output_mark; + err = x->outer_mode->output(x, skb); if (err) { XFRM_INC_STATS(net, LINUX_MIB_XFRMOUTSTATEMODEERROR); diff -ruw linux-4.4.115/net/xfrm/xfrm_policy.c linux-4.4.115-fbx/net/xfrm/xfrm_policy.c --- linux-4.4.115/net/xfrm/xfrm_policy.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/net/xfrm/xfrm_policy.c 2019-10-29 09:26:26.017226410 +0100 @@ -119,7 +119,7 @@ int tos, int oif, const xfrm_address_t *saddr, const xfrm_address_t *daddr, - int family) + int family, u32 mark) { struct xfrm_policy_afinfo *afinfo; struct dst_entry *dst; @@ -128,7 +128,7 @@ if (unlikely(afinfo == NULL)) return ERR_PTR(-EAFNOSUPPORT); - dst = afinfo->dst_lookup(net, tos, oif, saddr, daddr); + dst = afinfo->dst_lookup(net, tos, oif, saddr, daddr, mark); xfrm_policy_put_afinfo(afinfo); @@ -139,7 +139,7 @@ int tos, int oif, xfrm_address_t *prev_saddr, xfrm_address_t *prev_daddr, - int family) + int family, u32 mark) { struct net *net = xs_net(x); xfrm_address_t *saddr = &x->props.saddr; @@ -155,7 +155,7 @@ daddr = x->coaddr; } - dst = __xfrm_dst_lookup(net, tos, oif, saddr, daddr, family); + dst = __xfrm_dst_lookup(net, tos, oif, saddr, daddr, family, mark); if (!IS_ERR(dst)) { if (prev_saddr != saddr) @@ -1225,9 +1225,15 @@ read_lock_bh(&net->xfrm.xfrm_policy_lock); pol = rcu_dereference(sk->sk_policy[dir]); if (pol != NULL) { - bool match = xfrm_selector_match(&pol->selector, fl, family); + bool match; int err = 0; + if (pol->family != family) { + pol = NULL; + goto out; + } + + match = xfrm_selector_match(&pol->selector, fl, family); if (match) { if ((sk->sk_mark & pol->mark.m) != pol->mark.v) { pol = NULL; @@ -1307,7 +1313,7 @@ int xfrm_sk_policy_insert(struct sock *sk, int dir, struct xfrm_policy *pol) { - struct net *net = xp_net(pol); + struct net *net = sock_net(sk); struct xfrm_policy *old_pol; #ifdef CONFIG_XFRM_SUB_POLICY @@ -1396,14 +1402,14 @@ static int xfrm_get_saddr(struct net *net, int oif, xfrm_address_t *local, - xfrm_address_t *remote, unsigned short family) + xfrm_address_t *remote, unsigned short family, u32 mark) { int err; struct xfrm_policy_afinfo *afinfo = xfrm_policy_get_afinfo(family); if (unlikely(afinfo == NULL)) return -EINVAL; - err = afinfo->get_saddr(net, oif, local, remote); + err = afinfo->get_saddr(net, oif, local, remote, mark); xfrm_policy_put_afinfo(afinfo); return err; } @@ -1434,7 +1440,7 @@ if (xfrm_addr_any(local, tmpl->encap_family)) { error = xfrm_get_saddr(net, fl->flowi_oif, &tmp, remote, - tmpl->encap_family); + tmpl->encap_family, 0); if (error) goto fail; local = &tmp; @@ -1713,7 +1719,8 @@ if (xfrm[i]->props.mode != XFRM_MODE_TRANSPORT) { family = xfrm[i]->props.family; dst = xfrm_dst_lookup(xfrm[i], tos, fl->flowi_oif, - &saddr, &daddr, family); + &saddr, &daddr, family, + xfrm[i]->props.output_mark); err = PTR_ERR(dst); if (IS_ERR(dst)) goto put_states; diff -ruw linux-4.4.115/net/xfrm/xfrm_state.c linux-4.4.115-fbx/net/xfrm/xfrm_state.c --- linux-4.4.115/net/xfrm/xfrm_state.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/net/xfrm/xfrm_state.c 2019-10-29 09:26:26.017226410 +0100 @@ -1845,6 +1845,13 @@ struct xfrm_mgr *km; struct xfrm_policy *pol = NULL; + if (!optval && !optlen) { + xfrm_sk_policy_insert(sk, XFRM_POLICY_IN, NULL); + xfrm_sk_policy_insert(sk, XFRM_POLICY_OUT, NULL); + __sk_dst_reset(sk); + return 0; + } + if (optlen <= 0 || optlen > PAGE_SIZE) return -EMSGSIZE; @@ -1869,6 +1876,7 @@ if (err >= 0) { xfrm_sk_policy_insert(sk, err, pol); xfrm_pol_put(pol); + __sk_dst_reset(sk); err = 0; } diff -ruw linux-4.4.115/net/xfrm/xfrm_user.c linux-4.4.115-fbx/net/xfrm/xfrm_user.c --- linux-4.4.115/net/xfrm/xfrm_user.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/net/xfrm/xfrm_user.c 2019-10-29 09:26:26.017226410 +0100 @@ -584,6 +584,9 @@ xfrm_mark_get(attrs, &x->mark); + if (attrs[XFRMA_OUTPUT_MARK]) + x->props.output_mark = nla_get_u32(attrs[XFRMA_OUTPUT_MARK]); + err = __xfrm_init_state(x, false); if (err) goto error; @@ -867,6 +870,11 @@ goto out; if (x->security) ret = copy_sec_ctx(x->security, skb); + if (x->props.output_mark) { + ret = nla_put_u32(skb, XFRMA_OUTPUT_MARK, x->props.output_mark); + if (ret) + goto out; + } out: return ret; } @@ -1376,11 +1384,14 @@ static int validate_tmpl(int nr, struct xfrm_user_tmpl *ut, u16 family) { + u16 prev_family; int i; if (nr > XFRM_MAX_DEPTH) return -EINVAL; + prev_family = family; + for (i = 0; i < nr; i++) { /* We never validated the ut->family value, so many * applications simply leave it at zero. The check was @@ -1392,6 +1403,15 @@ if (!ut[i].family) ut[i].family = family; + if ((ut[i].mode == XFRM_MODE_TRANSPORT) && + (ut[i].family != prev_family)) + return -EINVAL; + + if (ut[i].mode >= XFRM_MODE_MAX) + return -EINVAL; + + prev_family = ut[i].family; + switch (ut[i].family) { case AF_INET: break; @@ -1693,6 +1713,10 @@ struct sk_buff *skb; int err; + err = verify_policy_dir(dir); + if (err) + return ERR_PTR(err); + skb = nlmsg_new(NLMSG_DEFAULT_SIZE, GFP_KERNEL); if (!skb) return ERR_PTR(-ENOMEM); @@ -2218,6 +2242,10 @@ int n = 0; struct net *net = sock_net(skb->sk); + err = verify_policy_dir(pi->dir); + if (err) + return err; + if (attrs[XFRMA_MIGRATE] == NULL) return -EINVAL; @@ -2333,6 +2361,11 @@ { struct net *net = &init_net; struct sk_buff *skb; + int err; + + err = verify_policy_dir(dir); + if (err) + return err; skb = nlmsg_new(xfrm_migrate_msgsize(num_migrate, !!k), GFP_ATOMIC); if (skb == NULL) @@ -2408,6 +2441,7 @@ [XFRMA_SA_EXTRA_FLAGS] = { .type = NLA_U32 }, [XFRMA_PROTO] = { .type = NLA_U8 }, [XFRMA_ADDRESS_FILTER] = { .len = sizeof(struct xfrm_address_filter) }, + [XFRMA_OUTPUT_MARK] = { .len = NLA_U32 }, }; static const struct nla_policy xfrma_spd_policy[XFRMA_SPD_MAX+1] = { @@ -2627,6 +2661,8 @@ l += nla_total_size(sizeof(*x->coaddr)); if (x->props.extra_flags) l += nla_total_size(sizeof(x->props.extra_flags)); + if (x->props.output_mark) + l += nla_total_size(sizeof(x->props.output_mark)); /* Must count x->lastused as it may become non-zero behind our back. */ l += nla_total_size(sizeof(u64)); @@ -2990,6 +3026,11 @@ static int xfrm_send_policy_notify(struct xfrm_policy *xp, int dir, const struct km_event *c) { + int err; + + err = verify_policy_dir(dir); + if (err) + return err; switch (c->event) { case XFRM_MSG_NEWPOLICY: diff -ruw linux-4.4.115/scripts/dtc/libfdt/fdt.c linux-4.4.115-fbx/scripts/dtc/libfdt/fdt.c --- linux-4.4.115/scripts/dtc/libfdt/fdt.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/scripts/dtc/libfdt/fdt.c 2019-10-29 09:26:26.025226489 +0100 @@ -71,6 +71,20 @@ return -FDT_ERR_BADMAGIC; } + if (fdt_off_dt_struct(fdt) > (UINT_MAX - fdt_size_dt_struct(fdt))) + return FDT_ERR_BADOFFSET; + + if (fdt_off_dt_strings(fdt) > (UINT_MAX - fdt_size_dt_strings(fdt))) + return FDT_ERR_BADOFFSET; + + if ((fdt_off_dt_struct(fdt) + fdt_size_dt_struct(fdt)) + > fdt_totalsize(fdt)) + return FDT_ERR_BADOFFSET; + + if ((fdt_off_dt_strings(fdt) + fdt_size_dt_strings(fdt)) + > fdt_totalsize(fdt)) + return FDT_ERR_BADOFFSET; + return 0; } diff -ruw linux-4.4.115/scripts/dtc/libfdt/fdt_rw.c linux-4.4.115-fbx/scripts/dtc/libfdt/fdt_rw.c --- linux-4.4.115/scripts/dtc/libfdt/fdt_rw.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/scripts/dtc/libfdt/fdt_rw.c 2019-10-29 09:26:26.025226489 +0100 @@ -394,7 +394,7 @@ static void _fdt_packblocks(const char *old, char *new, int mem_rsv_size, int struct_size) { - int mem_rsv_off, struct_off, strings_off; + uint32_t mem_rsv_off, struct_off, strings_off; mem_rsv_off = FDT_ALIGN(sizeof(struct fdt_header), 8); struct_off = mem_rsv_off + mem_rsv_size; diff -ruw linux-4.4.115/scripts/dtc/Makefile linux-4.4.115-fbx/scripts/dtc/Makefile --- linux-4.4.115/scripts/dtc/Makefile 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/scripts/dtc/Makefile 2019-01-22 16:16:29.279298712 +0100 @@ -1,7 +1,9 @@ # scripts/dtc makefile hostprogs-y := dtc +ifeq ($(DTC_EXT),) always := $(hostprogs-y) +endif dtc-objs := dtc.o flattree.o fstree.o data.o livetree.o treesource.o \ srcpos.o checks.o util.o diff -ruw linux-4.4.115/scripts/Kbuild.include linux-4.4.115-fbx/scripts/Kbuild.include --- linux-4.4.115/scripts/Kbuild.include 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/scripts/Kbuild.include 2019-10-29 09:26:26.017226410 +0100 @@ -107,16 +107,30 @@ as-instr = $(call try-run,\ printf "%b\n" "$(1)" | $(CC) $(KBUILD_AFLAGS) -c -x assembler -o "$$TMP" -,$(2),$(3)) +# __cc-option +# Usage: MY_CFLAGS += $(call __cc-option,$(CC),$(MY_CFLAGS),-march=winchip-c6,-march=i586) +__cc-option = $(call try-run,\ + $(1) -Werror $(2) $(3) -c -x c /dev/null -o "$$TMP",$(3),$(4)) + +# Do not attempt to build with gcc plugins during cc-option tests. +# (And this uses delayed resolution so the flags will be up to date.) +CC_OPTION_CFLAGS = $(filter-out $(GCC_PLUGINS_CFLAGS),$(KBUILD_CFLAGS)) + # cc-option # Usage: cflags-y += $(call cc-option,-march=winchip-c6,-march=i586) -cc-option = $(call try-run,\ - $(CC) $(KBUILD_CPPFLAGS) $(KBUILD_CFLAGS) $(1) -c -x c /dev/null -o "$$TMP",$(1),$(2)) +cc-option = $(call __cc-option, $(CC),\ + $(KBUILD_CPPFLAGS) $(KBUILD_CFLAGS),$(1),$(2)) + +# hostcc-option +# Usage: cflags-y += $(call hostcc-option,-march=winchip-c6,-march=i586) +hostcc-option = $(call __cc-option, $(HOSTCC),\ + $(HOSTCFLAGS) $(HOST_EXTRACFLAGS),$(1),$(2)) # cc-option-yn # Usage: flag := $(call cc-option-yn,-march=winchip-c6) cc-option-yn = $(call try-run,\ - $(CC) $(KBUILD_CPPFLAGS) $(KBUILD_CFLAGS) $(1) -c -x c /dev/null -o "$$TMP",y,n) + $(CC) -Werror $(KBUILD_CPPFLAGS) $(KBUILD_CFLAGS) $(1) -c -x c /dev/null -o "$$TMP",y,n) # cc-option-align # Prefix align with either -falign or -malign @@ -126,7 +140,7 @@ # cc-disable-warning # Usage: cflags-y += $(call cc-disable-warning,unused-but-set-variable) cc-disable-warning = $(call try-run,\ - $(CC) $(KBUILD_CPPFLAGS) $(KBUILD_CFLAGS) -W$(strip $(1)) -c -x c /dev/null -o "$$TMP",-Wno-$(strip $(1))) + $(CC) -Werror $(KBUILD_CPPFLAGS) $(KBUILD_CFLAGS) -W$(strip $(1)) -c -x c /dev/null -o "$$TMP",-Wno-$(strip $(1))) # cc-name # Expands to either gcc or clang diff -ruw linux-4.4.115/scripts/Makefile.build linux-4.4.115-fbx/scripts/Makefile.build --- linux-4.4.115/scripts/Makefile.build 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/scripts/Makefile.build 2019-01-22 16:16:29.267298603 +0100 @@ -64,6 +64,11 @@ include scripts/Makefile.host endif +# Do not include host rules unless needed +ifneq ($(dtbo-y),) +include scripts/Makefile.dtbo +endif + ifneq ($(KBUILD_SRC),) # Create output directory if not already present _dummy := $(shell [ -d $(obj) ] || mkdir -p $(obj)) @@ -175,6 +180,14 @@ $(obj)/%.symtypes : $(src)/%.c FORCE $(call cmd,cc_symtypes_c) +# LLVM assembly +# Generate .ll files from .c +quiet_cmd_cc_ll_c = CC $(quiet_modtag) $@ + cmd_cc_ll_c = $(CC) $(c_flags) -emit-llvm -S -o $@ $< + +$(obj)/%.ll: $(src)/%.c FORCE + $(call if_changed_dep,cc_ll_c) + # C (.c) files # The C file is compiled and updated dependency information is generated. # (See cmd_cc_o_c + relevant part of rule_cc_o_c) diff -ruw linux-4.4.115/scripts/Makefile.clean linux-4.4.115-fbx/scripts/Makefile.clean --- linux-4.4.115/scripts/Makefile.clean 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/scripts/Makefile.clean 2019-01-22 16:16:29.267298603 +0100 @@ -11,7 +11,7 @@ # The filename Kbuild has precedence over Makefile kbuild-dir := $(if $(filter /%,$(src)),$(src),$(srctree)/$(src)) -include $(if $(wildcard $(kbuild-dir)/Kbuild), $(kbuild-dir)/Kbuild, $(kbuild-dir)/Makefile) +-include $(if $(wildcard $(kbuild-dir)/Kbuild), $(kbuild-dir)/Kbuild, $(kbuild-dir)/Makefile) # Figure out what we need to build from the various variables # ========================================================================== diff -ruw linux-4.4.115/scripts/Makefile.extrawarn linux-4.4.115-fbx/scripts/Makefile.extrawarn --- linux-4.4.115/scripts/Makefile.extrawarn 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/scripts/Makefile.extrawarn 2019-10-29 09:26:26.017226410 +0100 @@ -61,7 +61,6 @@ KBUILD_CFLAGS += $(call cc-disable-warning, initializer-overrides) KBUILD_CFLAGS += $(call cc-disable-warning, unused-value) KBUILD_CFLAGS += $(call cc-disable-warning, format) -KBUILD_CFLAGS += $(call cc-disable-warning, unknown-warning-option) KBUILD_CFLAGS += $(call cc-disable-warning, sign-compare) KBUILD_CFLAGS += $(call cc-disable-warning, format-zero-length) KBUILD_CFLAGS += $(call cc-disable-warning, uninitialized) diff -ruw linux-4.4.115/scripts/Makefile.headersinst linux-4.4.115-fbx/scripts/Makefile.headersinst --- linux-4.4.115/scripts/Makefile.headersinst 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/scripts/Makefile.headersinst 2019-01-22 16:16:29.267298603 +0100 @@ -124,7 +124,7 @@ # Recursion .PHONY: $(subdirs) $(subdirs): - $(Q)$(MAKE) $(hdr-inst)=$(obj)/$@ dst=$(_dst)/$@ + $(Q)$(MAKE) $(hdr-inst)=$(obj)/$@ dst=$(_dst)/$(patsubst ../../../drivers/%,%,$@) targets := $(wildcard $(sort $(targets))) cmd_files := $(wildcard \ diff -ruw linux-4.4.115/scripts/Makefile.lib linux-4.4.115-fbx/scripts/Makefile.lib --- linux-4.4.115/scripts/Makefile.lib 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/scripts/Makefile.lib 2019-10-29 09:26:26.021226449 +0100 @@ -129,6 +129,18 @@ $(CFLAGS_KASAN)) endif +ifeq ($(CONFIG_UBSAN),y) +_c_flags += $(if $(patsubst n%,, \ + $(UBSAN_SANITIZE_$(basetarget).o)$(UBSAN_SANITIZE)$(CONFIG_UBSAN_SANITIZE_ALL)), \ + $(CFLAGS_UBSAN)) +endif + +ifeq ($(CONFIG_KCOV),y) +_c_flags += $(if $(patsubst n%,, \ + $(KCOV_INSTRUMENT_$(basetarget).o)$(KCOV_INSTRUMENT)y), \ + $(CFLAGS_KCOV)) +endif + # If building the kernel in a separate objtree expand all occurrences # of -Idir to -I$(srctree)/dir except for absolute paths (starting with '/'). @@ -281,10 +293,16 @@ $(obj)/%.dtb.S: $(obj)/%.dtb $(call cmd,dt_S_dtb) +ifneq ($(DTC_EXT),) +DTC = $(DTC_EXT) +else +DTC = $(objtree)/scripts/dtc/dtc +endif + quiet_cmd_dtc = DTC $@ cmd_dtc = mkdir -p $(dir ${dtc-tmp}) ; \ $(CPP) $(dtc_cpp_flags) -x assembler-with-cpp -o $(dtc-tmp) $< ; \ - $(objtree)/scripts/dtc/dtc -O dtb -o $@ -b 0 \ + $(DTC) -O dtb -o $@ -b 0 \ -i $(dir $<) $(DTC_FLAGS) \ -d $(depfile).dtc.tmp $(dtc-tmp) ; \ cat $(depfile).pre.tmp $(depfile).dtc.tmp > $(depfile) @@ -294,6 +312,24 @@ dtc-tmp = $(subst $(comma),_,$(dot-target).dts.tmp) +# Helper targets for Installing DTBs into the boot directory +quiet_cmd_dtb_install = INSTALL $< + cmd_dtb_install = cp $< $(2) + +_dtbinst_pre_: + $(Q)if [ -d $(INSTALL_DTBS_PATH).old ]; then rm -rf $(INSTALL_DTBS_PATH).old; fi + $(Q)if [ -d $(INSTALL_DTBS_PATH) ]; then mv $(INSTALL_DTBS_PATH) $(INSTALL_DTBS_PATH).old; fi + $(Q)mkdir -p $(INSTALL_DTBS_PATH) + +%.dtb_dtbinst_: $(obj)/%.dtb _dtbinst_pre_ + $(call cmd,dtb_install,$(INSTALL_DTBS_PATH)) + +# cat +# --------------------------------------------------------------------------- +# Concatentate multiple files together +quiet_cmd_cat = CAT $@ +cmd_cat = (cat $(filter-out FORCE,$^) > $@) || (rm -f $@; false) + # Bzip2 # --------------------------------------------------------------------------- @@ -388,3 +424,34 @@ cmd_xzmisc = (cat $(filter-out FORCE,$^) | \ xz --check=crc32 --lzma2=dict=1MiB) > $@ || \ (rm -f $@ ; false) + +# ASM offsets +# --------------------------------------------------------------------------- + +# Default sed regexp - multiline due to syntax constraints +# +# Use [:space:] because LLVM's integrated assembler inserts around +# the .ascii directive whereas GCC keeps the as-is. +define sed-offsets + 's:^[[:space:]]*\.ascii[[:space:]]*"\(.*\)".*:\1:; \ + /^->/{s:->#\(.*\):/* \1 */:; \ + s:^->\([^ ]*\) [\$$#]*\([^ ]*\) \(.*\):#define \1 \2 /* \3 */:; \ + s:->::; p;}' +endef + +# Use filechk to avoid rebuilds when a header changes, but the resulting file +# does not +define filechk_offsets + (set -e; \ + echo "#ifndef $2"; \ + echo "#define $2"; \ + echo "/*"; \ + echo " * DO NOT MODIFY."; \ + echo " *"; \ + echo " * This file was generated by Kbuild"; \ + echo " */"; \ + echo ""; \ + sed -ne $(sed-offsets); \ + echo ""; \ + echo "#endif" ) +endef diff -ruw linux-4.4.115/scripts/mod/Makefile linux-4.4.115-fbx/scripts/mod/Makefile --- linux-4.4.115/scripts/mod/Makefile 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/scripts/mod/Makefile 2019-01-22 16:16:29.299298893 +0100 @@ -5,32 +5,8 @@ devicetable-offsets-file := devicetable-offsets.h -define sed-y - "/^->/{s:->#\(.*\):/* \1 */:; \ - s:^->\([^ ]*\) [\$$#]*\([-0-9]*\) \(.*\):#define \1 \2 /* \3 */:; \ - s:^->\([^ ]*\) [\$$#]*\([^ ]*\) \(.*\):#define \1 \2 /* \3 */:; \ - s:->::; p;}" -endef - -quiet_cmd_offsets = GEN $@ -define cmd_offsets - (set -e; \ - echo "#ifndef __DEVICETABLE_OFFSETS_H__"; \ - echo "#define __DEVICETABLE_OFFSETS_H__"; \ - echo "/*"; \ - echo " * DO NOT MODIFY."; \ - echo " *"; \ - echo " * This file was generated by Kbuild"; \ - echo " *"; \ - echo " */"; \ - echo ""; \ - sed -ne $(sed-y) $<; \ - echo ""; \ - echo "#endif" ) > $@ -endef - -$(obj)/$(devicetable-offsets-file): $(obj)/devicetable-offsets.s - $(call if_changed,offsets) +$(obj)/$(devicetable-offsets-file): $(obj)/devicetable-offsets.s FORCE + $(call filechk,offsets,__DEVICETABLE_OFFSETS_H__) targets += $(devicetable-offsets-file) devicetable-offsets.s diff -ruw linux-4.4.115/scripts/setlocalversion linux-4.4.115-fbx/scripts/setlocalversion --- linux-4.4.115/scripts/setlocalversion 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/scripts/setlocalversion 2019-10-29 09:26:26.037226606 +0100 @@ -48,7 +48,20 @@ # If we are at a tagged commit (like "v2.6.30-rc6"), we ignore # it, because this version is defined in the top level Makefile. - if [ -z "`git describe --exact-match 2>/dev/null`" ]; then + if atag="`git describe --exact-match --abbrev=0 2>/dev/null`"; then + # Make sure we're at the tag that matches the Makefile. + # If not place the hash of the tag as well for + # v2.6.30-rc5-g314aef + if [ "x$atag" != "x$VERSION" ]; then + # If only the short version is requested, + # don't bother running further git commands + if $short; then + echo "+" + return + fi + printf '%s%s' -g "`git show-ref -s --abbrev --tags $atag 2>/dev/null`" + fi + else # If only the short version is requested, don't bother # running further git commands @@ -57,10 +70,12 @@ return fi # If we are past a tagged commit (like - # "v2.6.30-rc5-302-g72357d5"), we pretty print it. + # "v2.6.30-rc5-302-g72357d5"), we pretty print it and + # include the hash of any new tag on top. if atag="`git describe 2>/dev/null`"; then - echo "$atag" | awk -F- '{printf("-%05d-%s", $(NF-1),$(NF))}' - + tag="`git describe --abbrev=0 2>/dev/null`" + commit="`echo "$atag" | awk -F- '{printf("-%05d-%s", $(NF-1),$(NF))}'`" + printf '%s%s%s' -g "`git show-ref -s --abbrev --tags $tag 2>/dev/null`" $commit # If we don't have a tag at all we print -g{commitish}. else printf '%s%s' -g $head diff -ruw linux-4.4.115/scripts/sortextable.c linux-4.4.115-fbx/scripts/sortextable.c --- linux-4.4.115/scripts/sortextable.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/scripts/sortextable.c 2019-01-22 16:16:29.303298929 +0100 @@ -266,9 +266,9 @@ break; } /* end switch */ if (memcmp(ELFMAG, ehdr->e_ident, SELFMAG) != 0 - || r2(&ehdr->e_type) != ET_EXEC + || (r2(&ehdr->e_type) != ET_EXEC && r2(&ehdr->e_type) != ET_DYN) || ehdr->e_ident[EI_VERSION] != EV_CURRENT) { - fprintf(stderr, "unrecognized ET_EXEC file %s\n", fname); + fprintf(stderr, "unrecognized ET_EXEC/ET_DYN file %s\n", fname); fail_file(); } @@ -282,12 +282,13 @@ case EM_386: case EM_X86_64: case EM_S390: + case EM_AARCH64: + case EM_PARISC: custom_sort = sort_relative_table; break; case EM_ARCOMPACT: case EM_ARCV2: case EM_ARM: - case EM_AARCH64: case EM_MICROBLAZE: case EM_MIPS: case EM_XTENSA: @@ -304,7 +305,7 @@ if (r2(&ehdr->e_ehsize) != sizeof(Elf32_Ehdr) || r2(&ehdr->e_shentsize) != sizeof(Elf32_Shdr)) { fprintf(stderr, - "unrecognized ET_EXEC file: %s\n", fname); + "unrecognized ET_EXEC/ET_DYN file: %s\n", fname); fail_file(); } do32(ehdr, fname, custom_sort); @@ -314,7 +315,7 @@ if (r2(&ghdr->e_ehsize) != sizeof(Elf64_Ehdr) || r2(&ghdr->e_shentsize) != sizeof(Elf64_Shdr)) { fprintf(stderr, - "unrecognized ET_EXEC file: %s\n", fname); + "unrecognized ET_EXEC/ET_DYN file: %s\n", fname); fail_file(); } do64(ghdr, fname, custom_sort); diff -ruw linux-4.4.115/security/commoncap.c linux-4.4.115-fbx/security/commoncap.c --- linux-4.4.115/security/commoncap.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/security/commoncap.c 2019-01-22 16:16:29.307298965 +0100 @@ -31,6 +31,10 @@ #include #include +#ifdef CONFIG_ANDROID_PARANOID_NETWORK +#include +#endif + /* * If a non-root user executes a setuid-root binary in * !secure(SECURE_NOROOT) mode, then we raise capabilities. @@ -73,6 +77,13 @@ { struct user_namespace *ns = targ_ns; +#ifdef CONFIG_ANDROID_PARANOID_NETWORK + if (cap == CAP_NET_RAW && in_egroup_p(AID_NET_RAW)) + return 0; + if (cap == CAP_NET_ADMIN && in_egroup_p(AID_NET_ADMIN)) + return 0; +#endif + /* See if cred has the capability in the target user namespace * by examining the target user namespace and all of the target * user namespace's parents. diff -ruw linux-4.4.115/security/Kconfig linux-4.4.115-fbx/security/Kconfig --- linux-4.4.115/security/Kconfig 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/security/Kconfig 2019-01-22 16:16:29.303298929 +0100 @@ -6,6 +6,11 @@ source security/keys/Kconfig +if ARCH_QCOM +source security/pfe/Kconfig +endif + + config SECURITY_DMESG_RESTRICT bool "Restrict unprivileged access to the kernel syslog" default n @@ -18,6 +23,15 @@ If you are unsure how to answer this question, answer N. +config SECURITY_PERF_EVENTS_RESTRICT + bool "Restrict unprivileged use of performance events" + depends on PERF_EVENTS + help + If you say Y here, the kernel.perf_event_paranoid sysctl + will be set to 3 by default, and no unprivileged use of the + perf_event_open syscall will be permitted unless it is + changed. + config SECURITY bool "Enable different security models" depends on SYSFS @@ -128,6 +142,46 @@ this low address space will need the permission specific to the systems running LSM. +config HAVE_HARDENED_USERCOPY_ALLOCATOR + bool + help + The heap allocator implements __check_heap_object() for + validating memory ranges against heap object sizes in + support of CONFIG_HARDENED_USERCOPY. + +config HAVE_ARCH_HARDENED_USERCOPY + bool + help + The architecture supports CONFIG_HARDENED_USERCOPY by + calling check_object_size() just before performing the + userspace copies in the low level implementation of + copy_to_user() and copy_from_user(). + +config HARDENED_USERCOPY + bool "Harden memory copies between kernel and userspace" + depends on HAVE_ARCH_HARDENED_USERCOPY + depends on HAVE_HARDENED_USERCOPY_ALLOCATOR + select BUG + help + This option checks for obviously wrong memory regions when + copying memory to/from the kernel (via copy_to_user() and + copy_from_user() functions) by rejecting memory ranges that + are larger than the specified heap object, span multiple + separately allocates pages, are not on the process stack, + or are part of the kernel text. This kills entire classes + of heap overflow exploits and similar kernel memory exposures. + +config HARDENED_USERCOPY_PAGESPAN + bool "Refuse to copy allocations that span multiple pages" + depends on HARDENED_USERCOPY + depends on !COMPILE_TEST + help + When a multi-page allocation is done without __GFP_COMP, + hardened usercopy will reject attempts to copy it. There are, + however, several cases of this in the kernel that have not all + been removed. This config is intended to be used only while + trying to find such users. + source security/selinux/Kconfig source security/smack/Kconfig source security/tomoyo/Kconfig diff -ruw linux-4.4.115/security/lsm_audit.c linux-4.4.115-fbx/security/lsm_audit.c --- linux-4.4.115/security/lsm_audit.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/security/lsm_audit.c 2019-10-29 09:26:26.045226684 +0100 @@ -220,7 +220,7 @@ */ BUILD_BUG_ON(sizeof(a->u) > sizeof(void *)*2); - audit_log_format(ab, " pid=%d comm=", task_pid_nr(current)); + audit_log_format(ab, " pid=%d comm=", task_tgid_nr(current)); audit_log_untrustedstring(ab, memcpy(comm, current->comm, sizeof(comm))); switch (a->type) { @@ -294,7 +294,7 @@ case LSM_AUDIT_DATA_TASK: { struct task_struct *tsk = a->u.tsk; if (tsk) { - pid_t pid = task_pid_nr(tsk); + pid_t pid = task_tgid_nr(tsk); if (pid) { char comm[sizeof(tsk->comm)]; audit_log_format(ab, " opid=%d ocomm=", pid); diff -ruw linux-4.4.115/security/Makefile linux-4.4.115-fbx/security/Makefile --- linux-4.4.115/security/Makefile 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/security/Makefile 2019-01-22 16:16:29.303298929 +0100 @@ -8,6 +8,7 @@ subdir-$(CONFIG_SECURITY_TOMOYO) += tomoyo subdir-$(CONFIG_SECURITY_APPARMOR) += apparmor subdir-$(CONFIG_SECURITY_YAMA) += yama +subdir-$(CONFIG_ARCH_QCOM) += pfe # always enable default capabilities obj-y += commoncap.o @@ -22,6 +23,7 @@ obj-$(CONFIG_SECURITY_TOMOYO) += tomoyo/ obj-$(CONFIG_SECURITY_APPARMOR) += apparmor/ obj-$(CONFIG_SECURITY_YAMA) += yama/ +obj-$(CONFIG_ARCH_QCOM) += pfe/ obj-$(CONFIG_CGROUP_DEVICE) += device_cgroup.o # Object integrity file lists diff -ruw linux-4.4.115/sound/core/compress_offload.c linux-4.4.115-fbx/sound/core/compress_offload.c --- linux-4.4.115/sound/core/compress_offload.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/sound/core/compress_offload.c 2019-10-29 09:26:26.053226763 +0100 @@ -168,10 +168,13 @@ static int snd_compr_update_tstamp(struct snd_compr_stream *stream, struct snd_compr_tstamp *tstamp) { + int err = 0; if (!stream->ops->pointer) return -ENOTSUPP; - stream->ops->pointer(stream, tstamp); - pr_debug("dsp consumed till %d total %d bytes\n", + err = stream->ops->pointer(stream, tstamp); + if (err) + return err; + pr_debug("dsp consumed till %d total %llu bytes\n", tstamp->byte_offset, tstamp->copied_total); if (stream->direction == SND_COMPRESS_PLAYBACK) stream->runtime->total_bytes_transferred = tstamp->copied_total; @@ -251,8 +254,8 @@ (app_pointer * runtime->buffer_size); dstn = runtime->buffer + app_pointer; - pr_debug("copying %ld at %lld\n", - (unsigned long)count, app_pointer); + pr_debug("copying %zu at %lld\n", + count, app_pointer); if (count < runtime->buffer_size - app_pointer) { if (copy_from_user(dstn, buf, count)) return -EFAULT; @@ -290,7 +293,7 @@ } avail = snd_compr_get_avail(stream); - pr_debug("avail returned %ld\n", (unsigned long)avail); + pr_debug("avail returned %zu\n", avail); /* calculate how much we can write to buffer */ if (avail > count) avail = count; @@ -345,7 +348,7 @@ } avail = snd_compr_get_avail(stream); - pr_debug("avail returned %ld\n", (unsigned long)avail); + pr_debug("avail returned %zu\n", avail); /* calculate how much we can read from buffer */ if (avail > count) avail = count; @@ -398,7 +401,7 @@ poll_wait(f, &stream->runtime->sleep, wait); avail = snd_compr_get_avail(stream); - pr_debug("avail is %ld\n", (unsigned long)avail); + pr_debug("avail is %zu\n", avail); /* check if we have at least one fragment to fill */ switch (stream->runtime->state) { case SNDRV_PCM_STATE_DRAINING: @@ -500,7 +503,7 @@ { /* first let's check the buffer parameter's */ if (params->buffer.fragment_size == 0 || - params->buffer.fragments > INT_MAX / params->buffer.fragment_size) + params->buffer.fragments > U32_MAX / params->buffer.fragment_size) return -EINVAL; /* now codec parameters */ @@ -630,9 +633,10 @@ static inline int snd_compr_tstamp(struct snd_compr_stream *stream, unsigned long arg) { - struct snd_compr_tstamp tstamp = {0}; + struct snd_compr_tstamp tstamp; int ret; + memset(&tstamp, 0, sizeof(tstamp)); ret = snd_compr_update_tstamp(stream, &tstamp); if (ret == 0) ret = copy_to_user((struct snd_compr_tstamp __user *)arg, @@ -685,64 +689,39 @@ return -EPERM; retval = stream->ops->trigger(stream, SNDRV_PCM_TRIGGER_STOP); if (!retval) { - snd_compr_drain_notify(stream); + stream->runtime->state = SNDRV_PCM_STATE_SETUP; + wake_up(&stream->runtime->sleep); stream->runtime->total_bytes_available = 0; stream->runtime->total_bytes_transferred = 0; } return retval; } -static int snd_compress_wait_for_drain(struct snd_compr_stream *stream) -{ - int ret; - - /* - * We are called with lock held. So drop the lock while we wait for - * drain complete notfication from the driver - * - * It is expected that driver will notify the drain completion and then - * stream will be moved to SETUP state, even if draining resulted in an - * error. We can trigger next track after this. +/* this fn is called without lock being held and we change stream states here + * so while using the stream state auquire the lock but relase before invoking + * DSP as the call will possibly take a while */ - stream->runtime->state = SNDRV_PCM_STATE_DRAINING; - mutex_unlock(&stream->device->lock); - - /* we wait for drain to complete here, drain can return when - * interruption occurred, wait returned error or success. - * For the first two cases we don't do anything different here and - * return after waking up - */ - - ret = wait_event_interruptible(stream->runtime->sleep, - (stream->runtime->state != SNDRV_PCM_STATE_DRAINING)); - if (ret == -ERESTARTSYS) - pr_debug("wait aborted by a signal"); - else if (ret) - pr_debug("wait for drain failed with %d\n", ret); - - - wake_up(&stream->runtime->sleep); - mutex_lock(&stream->device->lock); - - return ret; -} - static int snd_compr_drain(struct snd_compr_stream *stream) { int retval; + mutex_lock(&stream->device->lock); if (stream->runtime->state == SNDRV_PCM_STATE_PREPARED || - stream->runtime->state == SNDRV_PCM_STATE_SETUP) - return -EPERM; - + stream->runtime->state == SNDRV_PCM_STATE_SETUP) { + retval = -EPERM; + goto ret; + } + mutex_unlock(&stream->device->lock); retval = stream->ops->trigger(stream, SND_COMPR_TRIGGER_DRAIN); - if (retval) { - pr_debug("SND_COMPR_TRIGGER_DRAIN failed %d\n", retval); + mutex_lock(&stream->device->lock); + if (!retval) { + stream->runtime->state = SNDRV_PCM_STATE_DRAINING; wake_up(&stream->runtime->sleep); - return retval; } - return snd_compress_wait_for_drain(stream); +ret: + mutex_unlock(&stream->device->lock); + return retval; } static int snd_compr_next_track(struct snd_compr_stream *stream) @@ -770,22 +749,87 @@ static int snd_compr_partial_drain(struct snd_compr_stream *stream) { int retval; + + mutex_lock(&stream->device->lock); if (stream->runtime->state == SNDRV_PCM_STATE_PREPARED || - stream->runtime->state == SNDRV_PCM_STATE_SETUP) + stream->runtime->state == SNDRV_PCM_STATE_SETUP) { + mutex_unlock(&stream->device->lock); return -EPERM; + } + mutex_unlock(&stream->device->lock); /* stream can be drained only when next track has been signalled */ if (stream->next_track == false) return -EPERM; retval = stream->ops->trigger(stream, SND_COMPR_TRIGGER_PARTIAL_DRAIN); - if (retval) { - pr_debug("Partial drain returned failure\n"); - wake_up(&stream->runtime->sleep); + + stream->next_track = false; return retval; } - stream->next_track = false; - return snd_compress_wait_for_drain(stream); +static int snd_compr_set_next_track_param(struct snd_compr_stream *stream, + unsigned long arg) +{ + union snd_codec_options codec_options; + int retval; + + /* set next track params when stream is running or has been setup */ + if (stream->runtime->state != SNDRV_PCM_STATE_SETUP && + stream->runtime->state != SNDRV_PCM_STATE_RUNNING) + return -EPERM; + + if (copy_from_user(&codec_options, (void __user *)arg, + sizeof(codec_options))) + return -EFAULT; + + retval = stream->ops->set_next_track_param(stream, &codec_options); + return retval; +} + +static int snd_compress_simple_ioctls(struct file *file, + struct snd_compr_stream *stream, + unsigned int cmd, unsigned long arg) +{ + int retval = -ENOTTY; + + switch (_IOC_NR(cmd)) { + case _IOC_NR(SNDRV_COMPRESS_IOCTL_VERSION): + retval = put_user(SNDRV_COMPRESS_VERSION, + (int __user *)arg) ? -EFAULT : 0; + break; + + case _IOC_NR(SNDRV_COMPRESS_GET_CAPS): + retval = snd_compr_get_caps(stream, arg); + break; + + case _IOC_NR(SNDRV_COMPRESS_GET_CODEC_CAPS): + retval = snd_compr_get_codec_caps(stream, arg); + break; + + + case _IOC_NR(SNDRV_COMPRESS_TSTAMP): + retval = snd_compr_tstamp(stream, arg); + break; + + case _IOC_NR(SNDRV_COMPRESS_AVAIL): + retval = snd_compr_ioctl_avail(stream, arg); + break; + + /* drain and partial drain need special handling + * we need to drop the locks here as the streams would get blocked on + * the dsp to get drained. The locking would be handled in respective + * function here + */ + case _IOC_NR(SNDRV_COMPRESS_DRAIN): + retval = snd_compr_drain(stream); + break; + + case _IOC_NR(SNDRV_COMPRESS_PARTIAL_DRAIN): + retval = snd_compr_partial_drain(stream); + break; + } + + return retval; } static long snd_compr_ioctl(struct file *f, unsigned int cmd, unsigned long arg) @@ -799,15 +843,9 @@ stream = &data->stream; if (snd_BUG_ON(!stream)) return -EFAULT; + mutex_lock(&stream->device->lock); switch (_IOC_NR(cmd)) { - case _IOC_NR(SNDRV_COMPRESS_IOCTL_VERSION): - retval = put_user(SNDRV_COMPRESS_VERSION, - (int __user *)arg) ? -EFAULT : 0; - break; - case _IOC_NR(SNDRV_COMPRESS_GET_CAPS): - retval = snd_compr_get_caps(stream, arg); - break; #ifndef COMPR_CODEC_CAPS_OVERFLOW case _IOC_NR(SNDRV_COMPRESS_GET_CODEC_CAPS): retval = snd_compr_get_codec_caps(stream, arg); @@ -816,44 +854,49 @@ case _IOC_NR(SNDRV_COMPRESS_SET_PARAMS): retval = snd_compr_set_params(stream, arg); break; + case _IOC_NR(SNDRV_COMPRESS_GET_PARAMS): retval = snd_compr_get_params(stream, arg); break; + case _IOC_NR(SNDRV_COMPRESS_SET_METADATA): retval = snd_compr_set_metadata(stream, arg); break; + case _IOC_NR(SNDRV_COMPRESS_GET_METADATA): retval = snd_compr_get_metadata(stream, arg); break; - case _IOC_NR(SNDRV_COMPRESS_TSTAMP): - retval = snd_compr_tstamp(stream, arg); - break; - case _IOC_NR(SNDRV_COMPRESS_AVAIL): - retval = snd_compr_ioctl_avail(stream, arg); - break; + case _IOC_NR(SNDRV_COMPRESS_PAUSE): retval = snd_compr_pause(stream); break; + case _IOC_NR(SNDRV_COMPRESS_RESUME): retval = snd_compr_resume(stream); break; + case _IOC_NR(SNDRV_COMPRESS_START): retval = snd_compr_start(stream); break; + case _IOC_NR(SNDRV_COMPRESS_STOP): retval = snd_compr_stop(stream); break; - case _IOC_NR(SNDRV_COMPRESS_DRAIN): - retval = snd_compr_drain(stream); - break; - case _IOC_NR(SNDRV_COMPRESS_PARTIAL_DRAIN): - retval = snd_compr_partial_drain(stream); - break; + case _IOC_NR(SNDRV_COMPRESS_NEXT_TRACK): retval = snd_compr_next_track(stream); break; + case _IOC_NR(SNDRV_COMPRESS_SET_NEXT_TRACK_PARAM): + retval = snd_compr_set_next_track_param(stream, arg); + break; + + default: + mutex_unlock(&stream->device->lock); + return snd_compress_simple_ioctls(f, stream, cmd, arg); + } + mutex_unlock(&stream->device->lock); return retval; } @@ -865,6 +908,7 @@ .write = snd_compr_write, .read = snd_compr_read, .unlocked_ioctl = snd_compr_ioctl, + .compat_ioctl = snd_compr_ioctl, .mmap = snd_compr_mmap, .poll = snd_compr_poll, }; @@ -937,6 +981,17 @@ } EXPORT_SYMBOL_GPL(snd_compress_new); +/* + * snd_compress_free: free compress device + * @card: sound card pointer + * @compr: compress device pointer + */ +void snd_compress_free(struct snd_card *card, struct snd_compr *compr) +{ + snd_device_free(card, compr); +} +EXPORT_SYMBOL_GPL(snd_compress_free); + static int snd_compress_add_device(struct snd_compr *device) { int ret; diff -ruw linux-4.4.115/sound/core/info.c linux-4.4.115-fbx/sound/core/info.c --- linux-4.4.115/sound/core/info.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/sound/core/info.c 2019-10-29 09:26:26.057226802 +0100 @@ -619,6 +619,36 @@ return 0; } +/* + * snd_register_module_info - create and register module + * @module: the module pointer + * @name: the module name + * @parent: the parent directory + * + * Creates and registers new module entry. + * + * Return: The pointer of the new instance, or NULL on failure. + */ +struct snd_info_entry *snd_register_module_info(struct module *module, + const char *name, + struct snd_info_entry *parent) +{ + struct snd_info_entry *entry; + + entry = snd_info_create_module_entry(module, name, parent); + if (!entry) + return NULL; + + entry->mode = S_IFDIR | S_IRUGO | S_IXUGO; + + if (snd_info_register(entry) < 0) { + snd_info_free_entry(entry); + return NULL; + } + + return entry; +} +EXPORT_SYMBOL(snd_register_module_info); /** * snd_info_get_line - read one line from the procfs buffer @@ -724,8 +754,11 @@ INIT_LIST_HEAD(&entry->children); INIT_LIST_HEAD(&entry->list); entry->parent = parent; - if (parent) + if (parent) { + mutex_lock(&parent->access); list_add_tail(&entry->list, &parent->children); + mutex_unlock(&parent->access); + } return entry; } diff -ruw linux-4.4.115/sound/core/init.c linux-4.4.115-fbx/sound/core/init.c --- linux-4.4.115/sound/core/init.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/sound/core/init.c 2019-10-29 09:26:26.057226802 +0100 @@ -58,6 +58,8 @@ module_param_array(slots, charp, NULL, 0444); MODULE_PARM_DESC(slots, "Module names assigned to the slots."); +#define SND_CARD_STATE_MAX_LEN 16 + /* return non-zero if the given index is reserved for the given * module via slots option */ @@ -107,9 +109,39 @@ snd_iprintf(buffer, "%s\n", entry->card->id); } +static ssize_t snd_card_state_read(struct snd_info_entry *entry, + void *file_private_data, struct file *file, + char __user *buf, size_t count, loff_t pos) +{ + int len; + char buffer[SND_CARD_STATE_MAX_LEN]; + + /* make sure offline is updated prior to wake up */ + rmb(); + len = snprintf(buffer, sizeof(buffer), "%s\n", + entry->card->offline ? "OFFLINE" : "ONLINE"); + return simple_read_from_buffer(buf, count, &pos, buffer, len); +} + +static unsigned int snd_card_state_poll(struct snd_info_entry *entry, + void *private_data, struct file *file, + poll_table *wait) +{ + poll_wait(file, &entry->card->offline_poll_wait, wait); + if (xchg(&entry->card->offline_change, 0)) + return POLLIN | POLLPRI | POLLRDNORM; + else + return 0; +} + +static struct snd_info_entry_ops snd_card_state_proc_ops = { + .read = snd_card_state_read, + .poll = snd_card_state_poll, +}; + static int init_info_for_card(struct snd_card *card) { - struct snd_info_entry *entry; + struct snd_info_entry *entry, *entry_state; entry = snd_info_create_card_entry(card, "id", card->proc_root); if (!entry) { @@ -119,6 +151,17 @@ entry->c.text.read = snd_card_id_read; card->proc_id = entry; + entry_state = snd_info_create_card_entry(card, "state", + card->proc_root); + if (!entry_state) { + dev_dbg(card->dev, "unable to create card entry state\n"); + card->proc_id = NULL; + return -ENOMEM; + } + entry_state->size = SND_CARD_STATE_MAX_LEN; + entry_state->content = SNDRV_INFO_CONTENT_DATA; + entry_state->c.ops = &snd_card_state_proc_ops; + return snd_info_card_register(card); } #else /* !CONFIG_SND_PROC_FS */ @@ -258,6 +301,7 @@ init_waitqueue_head(&card->power_sleep); #endif + init_waitqueue_head(&card->offline_poll_wait); device_initialize(&card->card_dev); card->card_dev.parent = parent; card->card_dev.class = sound_class; @@ -972,6 +1016,35 @@ EXPORT_SYMBOL(snd_card_file_remove); +/** + * snd_card_change_online_state - mark card's online/offline state + * @card: Card to mark + * @online: whether online of offline + * + * Mutes the DAI DAC. + */ +void snd_card_change_online_state(struct snd_card *card, int online) +{ + snd_printd("snd card %s state change %d -> %d\n", + card->shortname, !card->offline, online); + card->offline = !online; + /* make sure offline is updated prior to wake up */ + wmb(); + xchg(&card->offline_change, 1); + wake_up_interruptible(&card->offline_poll_wait); +} +EXPORT_SYMBOL(snd_card_change_online_state); + +/** + * snd_card_is_online_state - return true if card is online state + * @card: Card to query + */ +bool snd_card_is_online_state(struct snd_card *card) +{ + return !card->offline; +} +EXPORT_SYMBOL(snd_card_is_online_state); + #ifdef CONFIG_PM /** * snd_power_wait - wait until the power-state is changed. diff -ruw linux-4.4.115/sound/core/jack.c linux-4.4.115-fbx/sound/core/jack.c --- linux-4.4.115/sound/core/jack.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/sound/core/jack.c 2019-01-22 16:16:29.343299291 +0100 @@ -32,13 +32,17 @@ unsigned int mask_bits; /* only masked status bits are reported via kctl */ }; -static int jack_switch_types[SND_JACK_SWITCH_TYPES] = { +static int jack_switch_types[] = { SW_HEADPHONE_INSERT, SW_MICROPHONE_INSERT, SW_LINEOUT_INSERT, SW_JACK_PHYSICAL_INSERT, SW_VIDEOOUT_INSERT, SW_LINEIN_INSERT, + SW_HPHL_OVERCURRENT, + SW_HPHR_OVERCURRENT, + SW_UNSUPPORT_INSERT, + SW_MICROPHONE2_INSERT, }; static int snd_jack_dev_disconnect(struct snd_device *device) @@ -240,7 +244,7 @@ jack->type = type; - for (i = 0; i < SND_JACK_SWITCH_TYPES; i++) + for (i = 0; i < ARRAY_SIZE(jack_switch_types); i++) if (type & (1 << i)) input_set_capability(jack->input_dev, EV_SW, jack_switch_types[i]); diff -ruw linux-4.4.115/sound/core/pcm.c linux-4.4.115-fbx/sound/core/pcm.c --- linux-4.4.115/sound/core/pcm.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/sound/core/pcm.c 2019-10-29 09:26:26.057226802 +0100 @@ -744,6 +744,7 @@ } substream->group = &substream->self_group; spin_lock_init(&substream->self_group.lock); + spin_lock_init(&substream->runtime_lock); mutex_init(&substream->self_group.mutex); INIT_LIST_HEAD(&substream->self_group.substreams); list_add_tail(&substream->link_list, &substream->self_group.substreams); @@ -857,6 +858,14 @@ snd_ctl_remove(pstr->pcm->card, pstr->chmap_kctl); pstr->chmap_kctl = NULL; } + if (pstr->vol_kctl) { + snd_ctl_remove(pstr->pcm->card, pstr->vol_kctl); + pstr->vol_kctl = NULL; + } + if (pstr->usr_kctl) { + snd_ctl_remove(pstr->pcm->card, pstr->usr_kctl); + pstr->usr_kctl = NULL; + } } static void snd_pcm_free_stream(struct snd_pcm_str * pstr) @@ -1014,9 +1023,11 @@ void snd_pcm_detach_substream(struct snd_pcm_substream *substream) { struct snd_pcm_runtime *runtime; + unsigned long flags = 0; if (PCM_RUNTIME_CHECK(substream)) return; + spin_lock_irqsave(&substream->runtime_lock, flags); runtime = substream->runtime; if (runtime->private_free != NULL) runtime->private_free(runtime); @@ -1030,6 +1041,7 @@ put_pid(substream->pid); substream->pid = NULL; substream->pstr->substream_opened--; + spin_unlock_irqrestore(&substream->runtime_lock, flags); } static ssize_t show_pcm_class(struct device *dev, diff -ruw linux-4.4.115/sound/core/pcm_compat.c linux-4.4.115-fbx/sound/core/pcm_compat.c --- linux-4.4.115/sound/core/pcm_compat.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/sound/core/pcm_compat.c 2019-10-29 09:26:26.057226802 +0100 @@ -655,6 +655,39 @@ #endif /* CONFIG_X86_X32 */ }; +static int snd_compressed_ioctl32(struct snd_pcm_substream *substream, + unsigned int cmd, void __user *arg) +{ + struct snd_pcm_runtime *runtime; + int err = 0; + + if (PCM_RUNTIME_CHECK(substream)) + return -ENXIO; + runtime = substream->runtime; + if (substream->ops->compat_ioctl) { + err = substream->ops->compat_ioctl(substream, cmd, arg); + } else { + err = -ENOIOCTLCMD; + pr_err("%s failed cmd = %d\n", __func__, cmd); + } + pr_debug("%s called with cmd = %d\n", __func__, cmd); + return err; +} +static int snd_user_ioctl32(struct snd_pcm_substream *substream, + unsigned int cmd, void __user *arg) +{ + struct snd_pcm_runtime *runtime; + int err = -ENOIOCTLCMD; + + if (PCM_RUNTIME_CHECK(substream)) + return -ENXIO; + runtime = substream->runtime; + if (substream->ops->compat_ioctl) + err = substream->ops->compat_ioctl(substream, cmd, arg); + return err; +} + + static long snd_pcm_ioctl_compat(struct file *file, unsigned int cmd, unsigned long arg) { struct snd_pcm_file *pcm_file; @@ -734,6 +767,11 @@ case SNDRV_PCM_IOCTL_CHANNEL_INFO_X32: return snd_pcm_ioctl_channel_info_x32(substream, argp); #endif /* CONFIG_X86_X32 */ + default: + if (_IOC_TYPE(cmd) == 'C') + return snd_compressed_ioctl32(substream, cmd, argp); + else if (_IOC_TYPE(cmd) == 'U') + return snd_user_ioctl32(substream, cmd, argp); } return -ENOIOCTLCMD; diff -ruw linux-4.4.115/sound/core/pcm_lib.c linux-4.4.115-fbx/sound/core/pcm_lib.c --- linux-4.4.115/sound/core/pcm_lib.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/sound/core/pcm_lib.c 2019-10-29 09:26:26.057226802 +0100 @@ -41,6 +41,9 @@ #define trace_hw_ptr_error(substream, reason) #endif +#define STRING_LENGTH_OF_INT 12 +#define MAX_USR_CTRL_CNT 128 + /* * fill ring buffer with silence * runtime->silence_start: starting pointer to silence area @@ -374,7 +377,8 @@ * the elapsed time to detect xruns. */ jdelta = curr_jiffies - runtime->hw_ptr_jiffies; - if (jdelta < runtime->hw_ptr_buffer_jiffies / 2) + if ((jdelta < runtime->hw_ptr_buffer_jiffies / 2) || + (runtime->hw_ptr_buffer_jiffies <= 0)) goto no_delta_check; hdelta = jdelta - delta * HZ / runtime->rate; xrun_threshold = runtime->hw_ptr_buffer_jiffies / 2 + 1; @@ -1791,6 +1795,11 @@ switch (runtime->access) { case SNDRV_PCM_ACCESS_MMAP_INTERLEAVED: case SNDRV_PCM_ACCESS_RW_INTERLEAVED: + if ((UINT_MAX/width) < info->channel) { + snd_printd("%s: integer overflow while multiply\n", + __func__); + return -EINVAL; + } info->first = info->channel * width; info->step = runtime->channels * width; break; @@ -1798,6 +1807,12 @@ case SNDRV_PCM_ACCESS_RW_NONINTERLEAVED: { size_t size = runtime->dma_bytes / runtime->channels; + + if ((size > 0) && ((UINT_MAX/(size * 8)) < info->channel)) { + snd_printd("%s: integer overflow while multiply\n", + __func__); + return -EINVAL; + } info->first = info->channel * size * 8; info->step = width; break; @@ -1843,8 +1858,6 @@ unsigned int cmd, void *arg) { switch (cmd) { - case SNDRV_PCM_IOCTL1_INFO: - return 0; case SNDRV_PCM_IOCTL1_RESET: return snd_pcm_lib_ioctl_reset(substream, arg); case SNDRV_PCM_IOCTL1_CHANNEL_INFO: @@ -2116,6 +2129,9 @@ struct snd_pcm_runtime *runtime; if (PCM_RUNTIME_CHECK(substream)) return -ENXIO; + /* TODO: consider and -EINVAL here */ + if (substream->hw_no_buffer) + snd_printd("%s: warning this PCM is host less\n", __func__); runtime = substream->runtime; if (snd_BUG_ON(!substream->ops->copy && !runtime->dma_area)) return -EINVAL; @@ -2566,6 +2582,23 @@ kfree(info); } +static int pcm_volume_ctl_info(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_info *uinfo) +{ + uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; + uinfo->count = 1; + uinfo->value.integer.min = 0; + uinfo->value.integer.max = 0x2000; + return 0; +} + +static void pcm_volume_ctl_private_free(struct snd_kcontrol *kcontrol) +{ + struct snd_pcm_volume *info = snd_kcontrol_chip(kcontrol); + info->pcm->streams[info->stream].vol_kctl = NULL; + kfree(info); +} + /** * snd_pcm_add_chmap_ctls - create channel-mapping control elements * @pcm: the assigned PCM instance @@ -2625,3 +2658,166 @@ return 0; } EXPORT_SYMBOL_GPL(snd_pcm_add_chmap_ctls); + +/** + * snd_pcm_add_volume_ctls - create volume control elements + * @pcm: the assigned PCM instance + * @stream: stream direction + * @max_length: the max length of the volume parameter of stream + * @private_value: the value passed to each kcontrol's private_value field + * @info_ret: store struct snd_pcm_volume instance if non-NULL + * + * Create volume control elements assigned to the given PCM stream(s). + * Returns zero if succeed, or a negative error value. + */ +int snd_pcm_add_volume_ctls(struct snd_pcm *pcm, int stream, + const struct snd_pcm_volume_elem *volume, + int max_length, + unsigned long private_value, + struct snd_pcm_volume **info_ret) +{ + struct snd_pcm_volume *info; + struct snd_kcontrol_new knew = { + .iface = SNDRV_CTL_ELEM_IFACE_MIXER, + .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ | + SNDRV_CTL_ELEM_ACCESS_READWRITE, + .info = pcm_volume_ctl_info, + }; + int err; + int size; + + info = kzalloc(sizeof(*info), GFP_KERNEL); + if (!info) + return -ENOMEM; + info->pcm = pcm; + info->stream = stream; + info->volume = volume; + info->max_length = max_length; + size = sizeof("Playback ") + sizeof(" Volume") + + STRING_LENGTH_OF_INT*sizeof(char) + 1; + knew.name = kzalloc(size, GFP_KERNEL); + if (!knew.name) { + kfree(info); + return -ENOMEM; + } + if (stream == SNDRV_PCM_STREAM_PLAYBACK) + snprintf((char *)knew.name, size, "%s %d %s", + "Playback", pcm->device, "Volume"); + else + snprintf((char *)knew.name, size, "%s %d %s", + "Capture", pcm->device, "Volume"); + knew.device = pcm->device; + knew.count = pcm->streams[stream].substream_count; + knew.private_value = private_value; + info->kctl = snd_ctl_new1(&knew, info); + if (!info->kctl) { + kfree(info); + kfree(knew.name); + return -ENOMEM; + } + info->kctl->private_free = pcm_volume_ctl_private_free; + err = snd_ctl_add(pcm->card, info->kctl); + if (err < 0) { + kfree(info); + kfree(knew.name); + return -ENOMEM; + } + pcm->streams[stream].vol_kctl = info->kctl; + if (info_ret) + *info_ret = info; + kfree(knew.name); + return 0; +} +EXPORT_SYMBOL_GPL(snd_pcm_add_volume_ctls); + +static int pcm_usr_ctl_info(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_info *uinfo) +{ + uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; + uinfo->count = MAX_USR_CTRL_CNT; + uinfo->value.integer.min = 0; + uinfo->value.integer.max = INT_MAX; + return 0; +} + +static void pcm_usr_ctl_private_free(struct snd_kcontrol *kcontrol) +{ + struct snd_pcm_usr *info = snd_kcontrol_chip(kcontrol); + info->pcm->streams[info->stream].usr_kctl = NULL; + kfree(info); +} + +/** + * snd_pcm_add_usr_ctls - create user control elements + * @pcm: the assigned PCM instance + * @stream: stream direction + * @max_length: the max length of the user parameter of stream + * @private_value: the value passed to each kcontrol's private_value field + * @info_ret: store struct snd_pcm_usr instance if non-NULL + * + * Create usr control elements assigned to the given PCM stream(s). + * Returns zero if succeed, or a negative error value. + */ +int snd_pcm_add_usr_ctls(struct snd_pcm *pcm, int stream, + const struct snd_pcm_usr_elem *usr, + int max_length, int max_kctrl_str_len, + unsigned long private_value, + struct snd_pcm_usr **info_ret) +{ + struct snd_pcm_usr *info; + struct snd_kcontrol_new knew = { + .iface = SNDRV_CTL_ELEM_IFACE_MIXER, + .access = SNDRV_CTL_ELEM_ACCESS_READWRITE, + .info = pcm_usr_ctl_info, + }; + int err; + char *buf; + + info = kzalloc(sizeof(*info), GFP_KERNEL); + if (!info) { + pr_err("%s: snd_pcm_usr alloc failed\n", __func__); + return -ENOMEM; + } + info->pcm = pcm; + info->stream = stream; + info->usr = usr; + info->max_length = max_length; + buf = kzalloc(max_kctrl_str_len, GFP_KERNEL); + if (!buf) { + pr_err("%s: buffer allocation failed\n", __func__); + kfree(info); + return -ENOMEM; + } + knew.name = buf; + if (stream == SNDRV_PCM_STREAM_PLAYBACK) + snprintf(buf, max_kctrl_str_len, "%s %d %s", + "Playback", pcm->device, "User kcontrol"); + else + snprintf(buf, max_kctrl_str_len, "%s %d %s", + "Capture", pcm->device, "User kcontrol"); + knew.device = pcm->device; + knew.count = pcm->streams[stream].substream_count; + knew.private_value = private_value; + info->kctl = snd_ctl_new1(&knew, info); + if (!info->kctl) { + kfree(info); + kfree(knew.name); + pr_err("%s: snd_ctl_new failed\n", __func__); + return -ENOMEM; + } + info->kctl->private_free = pcm_usr_ctl_private_free; + err = snd_ctl_add(pcm->card, info->kctl); + if (err < 0) { + kfree(info); + kfree(knew.name); + pr_err("%s: snd_ctl_add failed:%d\n", __func__, + err); + return -ENOMEM; + } + pcm->streams[stream].usr_kctl = info->kctl; + if (info_ret) + *info_ret = info; + kfree(knew.name); + return 0; +} +EXPORT_SYMBOL(snd_pcm_add_usr_ctls); diff -ruw linux-4.4.115/sound/core/pcm_misc.c linux-4.4.115-fbx/sound/core/pcm_misc.c --- linux-4.4.115/sound/core/pcm_misc.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/sound/core/pcm_misc.c 2019-01-22 16:16:29.343299291 +0100 @@ -168,7 +168,9 @@ .le = -1, .signd = -1, }, [SNDRV_PCM_FORMAT_SPECIAL] = { - .le = -1, .signd = -1, + /* set the width and phys same as S16_LE */ + .width = 16, .phys = 16, .le = -1, .signd = -1, + .silence = {}, }, [SNDRV_PCM_FORMAT_S24_3LE] = { .width = 24, .phys = 24, .le = 1, .signd = 1, diff -ruw linux-4.4.115/sound/core/pcm_native.c linux-4.4.115-fbx/sound/core/pcm_native.c --- linux-4.4.115/sound/core/pcm_native.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/sound/core/pcm_native.c 2019-10-29 09:26:26.061226841 +0100 @@ -29,6 +29,7 @@ #include #include #include +#include #include #include #include @@ -196,7 +197,6 @@ int snd_pcm_info(struct snd_pcm_substream *substream, struct snd_pcm_info *info) { - struct snd_pcm_runtime *runtime; struct snd_pcm *pcm = substream->pcm; struct snd_pcm_str *pstr = substream->pstr; @@ -212,12 +212,7 @@ info->subdevices_count = pstr->substream_count; info->subdevices_avail = pstr->substream_count - pstr->substream_opened; strlcpy(info->subname, substream->name, sizeof(info->subname)); - runtime = substream->runtime; - /* AB: FIXME!!! This is definitely nonsense */ - if (runtime) { - info->sync = runtime->sync; - substream->ops->ioctl(substream, SNDRV_PCM_IOCTL1_INFO, info); - } + return 0; } @@ -587,7 +582,8 @@ runtime->silence_threshold = 0; runtime->silence_size = 0; runtime->boundary = runtime->buffer_size; - while (runtime->boundary * 2 <= LONG_MAX - runtime->buffer_size) + while (runtime->boundary * 2 * runtime->channels <= + LONG_MAX - runtime->buffer_size) runtime->boundary *= 2; snd_pcm_timer_resolution_change(substream); @@ -652,7 +648,9 @@ if (substream->ops->hw_free) result = substream->ops->hw_free(substream); snd_pcm_set_state(substream, SNDRV_PCM_STATE_OPEN); + if (pm_qos_request_active(&substream->latency_pm_qos_req)) pm_qos_remove_request(&substream->latency_pm_qos_req); + return result; } @@ -1034,6 +1032,7 @@ if (runtime->status->state != SNDRV_PCM_STATE_PREPARED) return -EBADFD; if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK && + !substream->hw_no_buffer && !snd_pcm_playback_data(substream)) return -EPIPE; runtime->trigger_tstamp_latched = false; @@ -1087,6 +1086,33 @@ SNDRV_PCM_STATE_RUNNING); } +static int snd_compressed_ioctl(struct snd_pcm_substream *substream, + unsigned int cmd, void __user *arg) +{ + struct snd_pcm_runtime *runtime; + int err = 0; + + if (PCM_RUNTIME_CHECK(substream)) + return -ENXIO; + runtime = substream->runtime; + pr_debug("%s called with cmd = %d\n", __func__, cmd); + err = substream->ops->ioctl(substream, cmd, arg); + return err; +} + +static int snd_user_ioctl(struct snd_pcm_substream *substream, + unsigned int cmd, void __user *arg) +{ + struct snd_pcm_runtime *runtime; + int err = 0; + + if (PCM_RUNTIME_CHECK(substream)) + return -ENXIO; + runtime = substream->runtime; + err = substream->ops->ioctl(substream, cmd, arg); + return err; +} + /* * stop callbacks */ @@ -1986,7 +2012,8 @@ #endif static unsigned int rates[] = { 5512, 8000, 11025, 16000, 22050, 32000, 44100, - 48000, 64000, 88200, 96000, 176400, 192000 }; + 48000, 64000, 88200, 96000, 176400, 192000, + 352800, 384000 }; const struct snd_pcm_hw_constraint_list snd_pcm_known_rates = { .count = ARRAY_SIZE(rates), @@ -2701,6 +2728,7 @@ volatile struct snd_pcm_mmap_status *status; volatile struct snd_pcm_mmap_control *control; int err; + snd_pcm_uframes_t hw_avail; memset(&sync_ptr, 0, sizeof(sync_ptr)); if (get_user(sync_ptr.flags, (unsigned __user *)&(_sync_ptr->flags))) @@ -2723,6 +2751,16 @@ control->avail_min = sync_ptr.c.control.avail_min; else sync_ptr.c.control.avail_min = control->avail_min; + + if (runtime->render_flag & SNDRV_NON_DMA_MODE) { + hw_avail = snd_pcm_playback_hw_avail(runtime); + if ((hw_avail >= runtime->start_threshold) + && (runtime->render_flag & + SNDRV_RENDER_STOPPED)) { + if (substream->ops->restart) + substream->ops->restart(substream); + } + } sync_ptr.s.status.state = status->state; sync_ptr.s.status.hw_ptr = status->hw_ptr; sync_ptr.s.status.tstamp = status->tstamp; @@ -2811,6 +2849,16 @@ snd_pcm_stream_unlock_irq(substream); return res; } + case SNDRV_COMPRESS_GET_CAPS: + case SNDRV_COMPRESS_GET_CODEC_CAPS: + case SNDRV_COMPRESS_SET_PARAMS: + case SNDRV_COMPRESS_GET_PARAMS: + case SNDRV_COMPRESS_TSTAMP: + case SNDRV_COMPRESS_DRAIN: + return snd_compressed_ioctl(substream, cmd, arg); + default: + if (((cmd >> 8) & 0xff) == 'U') + return snd_user_ioctl(substream, cmd, arg); } pcm_dbg(substream->pcm, "unknown ioctl = 0x%x\n", cmd); return -ENOTTY; @@ -2980,10 +3028,12 @@ unsigned long arg) { struct snd_pcm_file *pcm_file; + unsigned char ioctl_magic; pcm_file = file->private_data; + ioctl_magic = ((cmd >> 8) & 0xff); - if (((cmd >> 8) & 0xff) != 'A') + if (ioctl_magic != 'A' && ioctl_magic != 'C' && ioctl_magic != 'U') return -ENOTTY; return snd_pcm_playback_ioctl1(file, pcm_file->substream, cmd, @@ -2994,10 +3044,12 @@ unsigned long arg) { struct snd_pcm_file *pcm_file; + unsigned char ioctl_magic; pcm_file = file->private_data; + ioctl_magic = ((cmd >> 8) & 0xff); - if (((cmd >> 8) & 0xff) != 'A') + if (ioctl_magic != 'A' && ioctl_magic != 'U') return -ENOTTY; return snd_pcm_capture_ioctl1(file, pcm_file->substream, cmd, diff -ruw linux-4.4.115/sound/core/pcm_timer.c linux-4.4.115-fbx/sound/core/pcm_timer.c --- linux-4.4.115/sound/core/pcm_timer.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/sound/core/pcm_timer.c 2019-01-22 16:16:29.347299327 +0100 @@ -65,9 +65,16 @@ static unsigned long snd_pcm_timer_resolution(struct snd_timer * timer) { struct snd_pcm_substream *substream; + unsigned long ret = 0, flags = 0; substream = timer->private_data; - return substream->runtime ? substream->runtime->timer_resolution : 0; + spin_lock_irqsave(&substream->runtime_lock, flags); + if (substream->runtime) + ret = substream->runtime->timer_resolution; + else + ret = 0; + spin_unlock_irqrestore(&substream->runtime_lock, flags); + return ret; } static int snd_pcm_timer_start(struct snd_timer * timer) diff -ruw linux-4.4.115/sound/core/rawmidi.c linux-4.4.115-fbx/sound/core/rawmidi.c --- linux-4.4.115/sound/core/rawmidi.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/sound/core/rawmidi.c 2019-10-29 09:26:26.061226841 +0100 @@ -115,6 +115,7 @@ return -ENOMEM; runtime->substream = substream; spin_lock_init(&runtime->lock); + mutex_init(&runtime->realloc_mutex); init_waitqueue_head(&runtime->sleep); INIT_WORK(&runtime->event_work, snd_rawmidi_input_event_work); runtime->event = NULL; @@ -636,7 +637,9 @@ struct snd_rawmidi_params * params) { char *newbuf; + char *oldbuf; struct snd_rawmidi_runtime *runtime = substream->runtime; + unsigned long flags; if (substream->append && substream->use_count > 1) return -EBUSY; @@ -648,13 +651,22 @@ return -EINVAL; } if (params->buffer_size != runtime->buffer_size) { - newbuf = krealloc(runtime->buffer, params->buffer_size, + mutex_lock(&runtime->realloc_mutex); + newbuf = __krealloc(runtime->buffer, params->buffer_size, GFP_KERNEL); - if (!newbuf) + if (!newbuf) { + mutex_unlock(&runtime->realloc_mutex); return -ENOMEM; + } + spin_lock_irqsave(&runtime->lock, flags); + oldbuf = runtime->buffer; runtime->buffer = newbuf; runtime->buffer_size = params->buffer_size; runtime->avail = runtime->buffer_size; + spin_unlock_irqrestore(&runtime->lock, flags); + if (oldbuf != newbuf) + kfree(oldbuf); + mutex_unlock(&runtime->realloc_mutex); } runtime->avail_min = params->avail_min; substream->active_sensing = !params->no_active_sensing; @@ -666,7 +678,9 @@ struct snd_rawmidi_params * params) { char *newbuf; + char *oldbuf; struct snd_rawmidi_runtime *runtime = substream->runtime; + unsigned long flags; snd_rawmidi_drain_input(substream); if (params->buffer_size < 32 || params->buffer_size > 1024L * 1024L) { @@ -676,12 +690,21 @@ return -EINVAL; } if (params->buffer_size != runtime->buffer_size) { - newbuf = krealloc(runtime->buffer, params->buffer_size, + mutex_lock(&runtime->realloc_mutex); + newbuf = __krealloc(runtime->buffer, params->buffer_size, GFP_KERNEL); - if (!newbuf) + if (!newbuf) { + mutex_unlock(&runtime->realloc_mutex); return -ENOMEM; + } + spin_lock_irqsave(&runtime->lock, flags); + oldbuf = runtime->buffer; runtime->buffer = newbuf; runtime->buffer_size = params->buffer_size; + spin_unlock_irqrestore(&runtime->lock, flags); + if (oldbuf != newbuf) + kfree(oldbuf); + mutex_unlock(&runtime->realloc_mutex); } runtime->avail_min = params->avail_min; return 0; @@ -953,6 +976,8 @@ struct snd_rawmidi_runtime *runtime = substream->runtime; unsigned long appl_ptr; + if (userbuf) + mutex_lock(&runtime->realloc_mutex); spin_lock_irqsave(&runtime->lock, flags); while (count > 0 && runtime->avail) { count1 = runtime->buffer_size - runtime->appl_ptr; @@ -973,6 +998,7 @@ spin_unlock_irqrestore(&runtime->lock, flags); if (copy_to_user(userbuf + result, runtime->buffer + appl_ptr, count1)) { + mutex_unlock(&runtime->realloc_mutex); return result > 0 ? result : -EFAULT; } spin_lock_irqsave(&runtime->lock, flags); @@ -981,6 +1007,8 @@ count -= count1; } spin_unlock_irqrestore(&runtime->lock, flags); + if (userbuf) + mutex_unlock(&runtime->realloc_mutex); return result; } @@ -1245,10 +1273,14 @@ return -EINVAL; result = 0; + if (userbuf) + mutex_lock(&runtime->realloc_mutex); spin_lock_irqsave(&runtime->lock, flags); if (substream->append) { if ((long)runtime->avail < count) { spin_unlock_irqrestore(&runtime->lock, flags); + if (userbuf) + mutex_unlock(&runtime->realloc_mutex); return -EAGAIN; } } @@ -1284,6 +1316,8 @@ __end: count1 = runtime->avail < runtime->buffer_size; spin_unlock_irqrestore(&runtime->lock, flags); + if (userbuf) + mutex_unlock(&runtime->realloc_mutex); if (count1) snd_rawmidi_output_trigger(substream, 1); return result; diff -ruw linux-4.4.115/sound/core/timer.c linux-4.4.115-fbx/sound/core/timer.c --- linux-4.4.115/sound/core/timer.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/sound/core/timer.c 2019-10-29 09:26:26.065226880 +0100 @@ -318,8 +318,6 @@ return 0; } -static int _snd_timer_stop(struct snd_timer_instance *timeri, int event); - /* * close a timer instance */ @@ -408,7 +406,6 @@ static void snd_timer_notify1(struct snd_timer_instance *ti, int event) { struct snd_timer *timer; - unsigned long flags; unsigned long resolution = 0; struct snd_timer_instance *ts; struct timespec tstamp; @@ -432,34 +429,66 @@ return; if (timer->hw.flags & SNDRV_TIMER_HW_SLAVE) return; - spin_lock_irqsave(&timer->lock, flags); list_for_each_entry(ts, &ti->slave_active_head, active_list) if (ts->ccallback) ts->ccallback(ts, event + 100, &tstamp, resolution); - spin_unlock_irqrestore(&timer->lock, flags); } -static int snd_timer_start1(struct snd_timer *timer, struct snd_timer_instance *timeri, - unsigned long sticks) +/* start/continue a master timer */ +static int snd_timer_start1(struct snd_timer_instance *timeri, + bool start, unsigned long ticks) { + struct snd_timer *timer; + int result; + unsigned long flags; + + timer = timeri->timer; + if (!timer) + return -EINVAL; + + spin_lock_irqsave(&timer->lock, flags); + if (timer->card && timer->card->shutdown) { + result = -ENODEV; + goto unlock; + } + if (timeri->flags & (SNDRV_TIMER_IFLG_RUNNING | + SNDRV_TIMER_IFLG_START)) { + result = -EBUSY; + goto unlock; + } + + if (start) + timeri->ticks = timeri->cticks = ticks; + else if (!timeri->cticks) + timeri->cticks = 1; + timeri->pticks = 0; + list_move_tail(&timeri->active_list, &timer->active_list_head); if (timer->running) { if (timer->hw.flags & SNDRV_TIMER_HW_SLAVE) goto __start_now; timer->flags |= SNDRV_TIMER_FLG_RESCHED; timeri->flags |= SNDRV_TIMER_IFLG_START; - return 1; /* delayed start */ + result = 1; /* delayed start */ } else { - timer->sticks = sticks; + if (start) + timer->sticks = ticks; timer->hw.start(timer); __start_now: timer->running++; timeri->flags |= SNDRV_TIMER_IFLG_RUNNING; - return 0; + result = 0; } + snd_timer_notify1(timeri, start ? SNDRV_TIMER_EVENT_START : + SNDRV_TIMER_EVENT_CONTINUE); + unlock: + spin_unlock_irqrestore(&timer->lock, flags); + return result; } -static int snd_timer_start_slave(struct snd_timer_instance *timeri) +/* start/continue a slave timer */ +static int snd_timer_start_slave(struct snd_timer_instance *timeri, + bool start) { unsigned long flags; @@ -473,107 +502,92 @@ spin_lock(&timeri->timer->lock); list_add_tail(&timeri->active_list, &timeri->master->slave_active_head); + snd_timer_notify1(timeri, start ? SNDRV_TIMER_EVENT_START : + SNDRV_TIMER_EVENT_CONTINUE); spin_unlock(&timeri->timer->lock); } spin_unlock_irqrestore(&slave_active_lock, flags); return 1; /* delayed start */ } -/* - * start the timer instance - */ -int snd_timer_start(struct snd_timer_instance *timeri, unsigned int ticks) +/* stop/pause a master timer */ +static int snd_timer_stop1(struct snd_timer_instance *timeri, bool stop) { struct snd_timer *timer; - int result = -EINVAL; + int result = 0; unsigned long flags; - if (timeri == NULL || ticks < 1) - return -EINVAL; - if (timeri->flags & SNDRV_TIMER_IFLG_SLAVE) { - result = snd_timer_start_slave(timeri); - if (result >= 0) - snd_timer_notify1(timeri, SNDRV_TIMER_EVENT_START); - return result; - } timer = timeri->timer; - if (timer == NULL) + if (!timer) return -EINVAL; - if (timer->card && timer->card->shutdown) - return -ENODEV; spin_lock_irqsave(&timer->lock, flags); - if (timeri->flags & (SNDRV_TIMER_IFLG_RUNNING | - SNDRV_TIMER_IFLG_START)) { + if (!(timeri->flags & (SNDRV_TIMER_IFLG_RUNNING | + SNDRV_TIMER_IFLG_START))) { result = -EBUSY; goto unlock; } - timeri->ticks = timeri->cticks = ticks; + list_del_init(&timeri->ack_list); + list_del_init(&timeri->active_list); + if (timer->card && timer->card->shutdown) + goto unlock; + if (stop) { + timeri->cticks = timeri->ticks; timeri->pticks = 0; - result = snd_timer_start1(timer, timeri, ticks); + } + if ((timeri->flags & SNDRV_TIMER_IFLG_RUNNING) && + !(--timer->running)) { + timer->hw.stop(timer); + if (timer->flags & SNDRV_TIMER_FLG_RESCHED) { + timer->flags &= ~SNDRV_TIMER_FLG_RESCHED; + snd_timer_reschedule(timer, 0); + if (timer->flags & SNDRV_TIMER_FLG_CHANGE) { + timer->flags &= ~SNDRV_TIMER_FLG_CHANGE; + timer->hw.start(timer); + } + } + } + timeri->flags &= ~(SNDRV_TIMER_IFLG_RUNNING | SNDRV_TIMER_IFLG_START); + snd_timer_notify1(timeri, stop ? SNDRV_TIMER_EVENT_STOP : + SNDRV_TIMER_EVENT_CONTINUE); unlock: spin_unlock_irqrestore(&timer->lock, flags); - if (result >= 0) - snd_timer_notify1(timeri, SNDRV_TIMER_EVENT_START); return result; } -static int _snd_timer_stop(struct snd_timer_instance *timeri, int event) +/* stop/pause a slave timer */ +static int snd_timer_stop_slave(struct snd_timer_instance *timeri, bool stop) { - struct snd_timer *timer; unsigned long flags; - if (snd_BUG_ON(!timeri)) - return -ENXIO; - - if (timeri->flags & SNDRV_TIMER_IFLG_SLAVE) { spin_lock_irqsave(&slave_active_lock, flags); if (!(timeri->flags & SNDRV_TIMER_IFLG_RUNNING)) { spin_unlock_irqrestore(&slave_active_lock, flags); return -EBUSY; } - if (timeri->timer) - spin_lock(&timeri->timer->lock); timeri->flags &= ~SNDRV_TIMER_IFLG_RUNNING; + if (timeri->timer) { + spin_lock(&timeri->timer->lock); list_del_init(&timeri->ack_list); list_del_init(&timeri->active_list); - if (timeri->timer) + snd_timer_notify1(timeri, stop ? SNDRV_TIMER_EVENT_STOP : + SNDRV_TIMER_EVENT_CONTINUE); spin_unlock(&timeri->timer->lock); - spin_unlock_irqrestore(&slave_active_lock, flags); - goto __end; } - timer = timeri->timer; - if (!timer) - return -EINVAL; - spin_lock_irqsave(&timer->lock, flags); - if (!(timeri->flags & (SNDRV_TIMER_IFLG_RUNNING | - SNDRV_TIMER_IFLG_START))) { - spin_unlock_irqrestore(&timer->lock, flags); - return -EBUSY; - } - list_del_init(&timeri->ack_list); - list_del_init(&timeri->active_list); - if (timer->card && timer->card->shutdown) { - spin_unlock_irqrestore(&timer->lock, flags); + spin_unlock_irqrestore(&slave_active_lock, flags); return 0; } - if ((timeri->flags & SNDRV_TIMER_IFLG_RUNNING) && - !(--timer->running)) { - timer->hw.stop(timer); - if (timer->flags & SNDRV_TIMER_FLG_RESCHED) { - timer->flags &= ~SNDRV_TIMER_FLG_RESCHED; - snd_timer_reschedule(timer, 0); - if (timer->flags & SNDRV_TIMER_FLG_CHANGE) { - timer->flags &= ~SNDRV_TIMER_FLG_CHANGE; - timer->hw.start(timer); - } - } - } - timeri->flags &= ~(SNDRV_TIMER_IFLG_RUNNING | SNDRV_TIMER_IFLG_START); - spin_unlock_irqrestore(&timer->lock, flags); - __end: - if (event != SNDRV_TIMER_EVENT_RESOLUTION) - snd_timer_notify1(timeri, event); - return 0; + +/* + * start the timer instance + */ +int snd_timer_start(struct snd_timer_instance *timeri, unsigned int ticks) +{ + if (timeri == NULL || ticks < 1) + return -EINVAL; + if (timeri->flags & SNDRV_TIMER_IFLG_SLAVE) + return snd_timer_start_slave(timeri, true); + else + return snd_timer_start1(timeri, true, ticks); } /* @@ -583,21 +597,10 @@ */ int snd_timer_stop(struct snd_timer_instance *timeri) { - struct snd_timer *timer; - unsigned long flags; - int err; - - err = _snd_timer_stop(timeri, SNDRV_TIMER_EVENT_STOP); - if (err < 0) - return err; - timer = timeri->timer; - if (!timer) - return -EINVAL; - spin_lock_irqsave(&timer->lock, flags); - timeri->cticks = timeri->ticks; - timeri->pticks = 0; - spin_unlock_irqrestore(&timer->lock, flags); - return 0; + if (timeri->flags & SNDRV_TIMER_IFLG_SLAVE) + return snd_timer_stop_slave(timeri, true); + else + return snd_timer_stop1(timeri, true); } /* @@ -605,32 +608,10 @@ */ int snd_timer_continue(struct snd_timer_instance *timeri) { - struct snd_timer *timer; - int result = -EINVAL; - unsigned long flags; - - if (timeri == NULL) - return result; if (timeri->flags & SNDRV_TIMER_IFLG_SLAVE) - return snd_timer_start_slave(timeri); - timer = timeri->timer; - if (! timer) - return -EINVAL; - if (timer->card && timer->card->shutdown) - return -ENODEV; - spin_lock_irqsave(&timer->lock, flags); - if (timeri->flags & SNDRV_TIMER_IFLG_RUNNING) { - result = -EBUSY; - goto unlock; - } - if (!timeri->cticks) - timeri->cticks = 1; - timeri->pticks = 0; - result = snd_timer_start1(timer, timeri, timer->sticks); - unlock: - spin_unlock_irqrestore(&timer->lock, flags); - snd_timer_notify1(timeri, SNDRV_TIMER_EVENT_CONTINUE); - return result; + return snd_timer_start_slave(timeri, false); + else + return snd_timer_start1(timeri, false, 0); } /* @@ -638,7 +619,10 @@ */ int snd_timer_pause(struct snd_timer_instance * timeri) { - return _snd_timer_stop(timeri, SNDRV_TIMER_EVENT_PAUSE); + if (timeri->flags & SNDRV_TIMER_IFLG_SLAVE) + return snd_timer_stop_slave(timeri, false); + else + return snd_timer_stop1(timeri, false); } /* @@ -1135,7 +1119,11 @@ mutex_lock(®ister_mutex); list_for_each_entry(timer, &snd_timer_list, device_list) { - if (timer->card && timer->card->shutdown) + if (timer->card == NULL) { + pr_debug("%s: timer->card is NULL\n", __func__); + continue; + } + if (timer->card->shutdown) continue; switch (timer->tmr_class) { case SNDRV_TIMER_CLASS_GLOBAL: diff -ruw linux-4.4.115/sound/soc/codecs/Kconfig linux-4.4.115-fbx/sound/soc/codecs/Kconfig --- linux-4.4.115/sound/soc/codecs/Kconfig 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/sound/soc/codecs/Kconfig 2019-10-29 09:26:26.109227311 +0100 @@ -81,6 +81,7 @@ select SND_SOC_MAX9877 if I2C select SND_SOC_MC13783 if MFD_MC13XXX select SND_SOC_ML26124 if I2C + select SND_SOC_HDMI_CODEC select SND_SOC_NAU8825 if I2C select SND_SOC_PCM1681 if I2C select SND_SOC_PCM1792A if SPI_MASTER @@ -97,6 +98,7 @@ select SND_SOC_RT5677 if I2C && SPI_MASTER select SND_SOC_SGTL5000 if I2C select SND_SOC_SI476X if MFD_SI476X_CORE + select SND_SOC_SIL9437 if I2C select SND_SOC_SIRF_AUDIO_CODEC select SND_SOC_SN95031 if INTEL_SCU_IPC select SND_SOC_SPDIF @@ -112,6 +114,7 @@ select SND_SOC_TAS2552 if I2C select SND_SOC_TAS5086 if I2C select SND_SOC_TAS571X if I2C + select SND_SOC_TAS5766 if I2C select SND_SOC_TFA9879 if I2C select SND_SOC_TLV320AIC23_I2C if I2C select SND_SOC_TLV320AIC23_SPI if SPI_MASTER @@ -454,6 +457,9 @@ config SND_SOC_DMIC tristate +config SND_SOC_HDMI_CODEC + tristate "HDMI stub CODEC" + config SND_SOC_ES8328 tristate "Everest Semi ES8328 CODEC" @@ -582,6 +588,11 @@ config SND_SOC_SI476X tristate +config SND_SOC_SIL9437 + tristate "Silicon Image Sil9437 ARC/eARC receiver" + depends on I2C + select REGMAP_I2C + config SND_SOC_SIGMADSP tristate select CRC32 @@ -656,6 +667,10 @@ tristate "Texas Instruments TAS5711/TAS5717/TAS5719 power amplifiers" depends on I2C +config SND_SOC_TAS5766 + tristate "Texas Instruments TAS5766 power amplifiers" + depends on I2C + config SND_SOC_TFA9879 tristate "NXP Semiconductors TFA9879 amplifier" depends on I2C @@ -709,6 +724,71 @@ config SND_SOC_UDA1380 tristate +config SND_SOC_WCD934X_DSD + tristate + +config SND_SOC_WCD9320 + tristate + +config SND_SOC_WCD9330 + tristate + depends on WCD9330_CODEC + +config SND_SOC_WCD9335 + tristate + depends on WCD9335_CODEC + +config SND_SOC_WCD934X + tristate + depends on WCD934X_CODEC + select SND_SOC_WCD9XXX_V2 + select AUDIO_EXT_CLK + select SND_SOC_WCD_DSP_MGR + select SND_SOC_WCD_SPI + select SND_SOC_WCD934X_MBHC + select SND_SOC_WCD934X_DSD + +config SND_SOC_WCD934X_MBHC + tristate + depends on SND_SOC_WCD934X + select SND_SOC_WCD_MBHC + +config SND_SOC_WSA881X + tristate + select MSM_CDC_PINCTRL + select REGMAP_SWR + +config SND_SOC_WSA881X_ANALOG + tristate + select REGMAP_I2C + +config SND_SOC_WCD9XXX + tristate + default y if SND_SOC_WCD9320=y || SND_SOC_WCD9330=y || SND_SOC_WCD9335=y + +config SND_SOC_WCD9XXX_V2 + tristate + default y if SND_SOC_WCD9335=y + +config SND_SOC_WCD_CPE + tristate + default y if SND_SOC_WCD9330=y || SND_SOC_WCD9335=y + +config AUDIO_EXT_CLK + tristate + default y if SND_SOC_WCD9335=y || SND_SOC_WCD9330=y || SND_SOC_SDM660_CDC=y + +config SND_SOC_WCD_MBHC + tristate + default y if (SND_SOC_MSM8909_WCD=y || SND_SOC_SDM660_CDC=y || SND_SOC_WCD9335=y) && SND_SOC_MDMCALIFORNIUM!=y + +config SND_SOC_WCD_DSP_MGR + tristate + +config SND_SOC_WCD_SPI + depends on SPI + tristate + config SND_SOC_WL1273 tristate @@ -915,4 +995,17 @@ tristate "Texas Instruments TPA6130A2 headphone amplifier" depends on I2C +config SND_SOC_MSM_STUB + tristate + +config SND_SOC_MSM_HDMI_CODEC_RX + bool "HDMI Audio Playback" + depends on FB_MSM_MDSS_HDMI_PANEL && (SND_SOC_APQ8084 || SND_SOC_MSM8994 || SND_SOC_MSM8996 || SND_SOC_MSM8998 || SND_SOC_SDM660_COMMON) + help + HDMI audio drivers should be built only if the platform + supports hdmi panel. + +source "sound/soc/codecs/sdm660_cdc/Kconfig" +source "sound/soc/codecs/msm_sdw/Kconfig" + endmenu diff -ruw linux-4.4.115/sound/soc/codecs/Makefile linux-4.4.115-fbx/sound/soc/codecs/Makefile --- linux-4.4.115/sound/soc/codecs/Makefile 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/sound/soc/codecs/Makefile 2019-01-22 16:16:29.499300704 +0100 @@ -74,6 +74,7 @@ snd-soc-max9850-objs := max9850.o snd-soc-mc13783-objs := mc13783.o snd-soc-ml26124-objs := ml26124.o +snd-soc-hdmi-codec-objs := hdmi.o snd-soc-nau8825-objs := nau8825.o snd-soc-pcm1681-objs := pcm1681.o snd-soc-pcm1792a-codec-objs := pcm1792a.o @@ -99,6 +100,7 @@ snd-soc-sigmadsp-i2c-objs := sigmadsp-i2c.o snd-soc-sigmadsp-regmap-objs := sigmadsp-regmap.o snd-soc-si476x-objs := si476x.o +snd-soc-sil9437-objs := sil9437.o snd-soc-sirf-audio-codec-objs := sirf-audio-codec.o snd-soc-sn95031-objs := sn95031.o snd-soc-spdif-tx-objs := spdif_transmitter.o @@ -115,6 +117,7 @@ snd-soc-sti-sas-objs := sti-sas.o snd-soc-tas5086-objs := tas5086.o snd-soc-tas571x-objs := tas571x.o +snd-soc-tas5766-objs := tas5766.o snd-soc-tfa9879-objs := tfa9879.o snd-soc-tlv320aic23-objs := tlv320aic23.o snd-soc-tlv320aic23-i2c-objs := tlv320aic23-i2c.o @@ -129,6 +132,27 @@ snd-soc-twl6040-objs := twl6040.o snd-soc-uda134x-objs := uda134x.o snd-soc-uda1380-objs := uda1380.o +snd-soc-wcd9320-objs := wcd9320.o wcd9320-tables.o +snd-soc-wcd9330-objs := wcd9330.o wcd9330-tables.o +snd-soc-wcd9335-objs := wcd9335.o +snd-soc-wcd934x-objs := wcd934x.o +snd-soc-wcd9xxx-objs := wcd9xxx-resmgr.o wcd9xxx-mbhc.o wcd9xxx-common.o wcdcal-hwdep.o +snd-soc-wcd9xxx-v2-objs := wcd9xxx-common-v2.o wcd9xxx-resmgr-v2.o +ifeq ($(CONFIG_COMMON_CLK_MSM), y) + audio-ext-clock-objs := audio-ext-clk.o +endif + +ifeq ($(CONFIG_COMMON_CLK_QCOM), y) + audio-ext-clock-up-objs := audio-ext-clk-up.o +endif +snd-soc-wcd-cpe-objs := wcd_cpe_services.o wcd_cpe_core.o +snd-soc-wsa881x-objs := wsa881x.o wsa881x-tables.o wsa881x-regmap.o wsa881x-temp-sensor.o +snd-soc-wcd-mbhc-objs := wcd-mbhc-v2.o +snd-soc-wsa881x-analog-objs := wsa881x-analog.o wsa881x-tables-analog.o +snd-soc-wsa881x-analog-objs += wsa881x-regmap-analog.o wsa881x-irq.o +snd-soc-wcd-dsp-utils-objs := wcd-dsp-utils.o +snd-soc-wcd-dsp-mgr-objs := wcd-dsp-mgr.o +snd-soc-wcd-spi-objs := wcd-spi.o snd-soc-wl1273-objs := wl1273.o snd-soc-wm-adsp-objs := wm_adsp.o snd-soc-wm0010-objs := wm0010.o @@ -185,6 +209,8 @@ snd-soc-wm9712-objs := wm9712.o snd-soc-wm9713-objs := wm9713.o snd-soc-wm-hubs-objs := wm_hubs.o +snd-soc-msm-stub-objs := msm_stub.o +obj-$(CONFIG_SND_SOC_MSM_HDMI_CODEC_RX) := msm_hdmi_codec_rx.o # Amp snd-soc-max9877-objs := max9877.o @@ -269,6 +295,7 @@ obj-$(CONFIG_SND_SOC_MAX9850) += snd-soc-max9850.o obj-$(CONFIG_SND_SOC_MC13783) += snd-soc-mc13783.o obj-$(CONFIG_SND_SOC_ML26124) += snd-soc-ml26124.o +obj-$(CONFIG_SND_SOC_HDMI_CODEC) += snd-soc-hdmi-codec.o obj-$(CONFIG_SND_SOC_NAU8825) += snd-soc-nau8825.o obj-$(CONFIG_SND_SOC_PCM1681) += snd-soc-pcm1681.o obj-$(CONFIG_SND_SOC_PCM1792A) += snd-soc-pcm1792a-codec.o @@ -292,6 +319,7 @@ obj-$(CONFIG_SND_SOC_SIGMADSP_I2C) += snd-soc-sigmadsp-i2c.o obj-$(CONFIG_SND_SOC_SIGMADSP_REGMAP) += snd-soc-sigmadsp-regmap.o obj-$(CONFIG_SND_SOC_SI476X) += snd-soc-si476x.o +obj-$(CONFIG_SND_SOC_SIL9437) += snd-soc-sil9437.o obj-$(CONFIG_SND_SOC_SN95031) +=snd-soc-sn95031.o obj-$(CONFIG_SND_SOC_SPDIF) += snd-soc-spdif-rx.o snd-soc-spdif-tx.o obj-$(CONFIG_SND_SOC_SSM2518) += snd-soc-ssm2518.o @@ -307,6 +335,7 @@ obj-$(CONFIG_SND_SOC_TAS2552) += snd-soc-tas2552.o obj-$(CONFIG_SND_SOC_TAS5086) += snd-soc-tas5086.o obj-$(CONFIG_SND_SOC_TAS571X) += snd-soc-tas571x.o +obj-$(CONFIG_SND_SOC_TAS5766) += snd-soc-tas5766.o obj-$(CONFIG_SND_SOC_TFA9879) += snd-soc-tfa9879.o obj-$(CONFIG_SND_SOC_TLV320AIC23) += snd-soc-tlv320aic23.o obj-$(CONFIG_SND_SOC_TLV320AIC23_I2C) += snd-soc-tlv320aic23-i2c.o @@ -321,7 +350,25 @@ obj-$(CONFIG_SND_SOC_TWL6040) += snd-soc-twl6040.o obj-$(CONFIG_SND_SOC_UDA134X) += snd-soc-uda134x.o obj-$(CONFIG_SND_SOC_UDA1380) += snd-soc-uda1380.o +obj-$(CONFIG_SND_SOC_WCD9320) += snd-soc-wcd9320.o +obj-$(CONFIG_SND_SOC_WCD9330) += snd-soc-wcd9330.o +obj-$(CONFIG_SND_SOC_WCD9335) += snd-soc-wcd9335.o +obj-$(CONFIG_SND_SOC_WCD934X) += wcd934x/ +ifeq ($(CONFIG_COMMON_CLK_MSM), y) + obj-$(CONFIG_AUDIO_EXT_CLK) += audio-ext-clock.o +endif +ifeq ($(CONFIG_COMMON_CLK_QCOM), y) + obj-$(CONFIG_AUDIO_EXT_CLK) += audio-ext-clock-up.o +endif +obj-$(CONFIG_SND_SOC_WCD9XXX) += snd-soc-wcd9xxx.o +obj-$(CONFIG_SND_SOC_WCD9XXX_V2) += snd-soc-wcd9xxx-v2.o +obj-$(CONFIG_SND_SOC_WCD_CPE) += snd-soc-wcd-cpe.o +obj-$(CONFIG_SND_SOC_WCD_MBHC) += snd-soc-wcd-mbhc.o +obj-$(CONFIG_SND_SOC_WSA881X) += snd-soc-wsa881x.o +obj-$(CONFIG_SND_SOC_WSA881X_ANALOG) += snd-soc-wsa881x-analog.o obj-$(CONFIG_SND_SOC_WL1273) += snd-soc-wl1273.o +obj-$(CONFIG_SND_SOC_WCD_DSP_MGR) += snd-soc-wcd-dsp-mgr.o snd-soc-wcd-dsp-utils.o +obj-$(CONFIG_SND_SOC_WCD_SPI) += snd-soc-wcd-spi.o obj-$(CONFIG_SND_SOC_WM0010) += snd-soc-wm0010.o obj-$(CONFIG_SND_SOC_WM1250_EV1) += snd-soc-wm1250-ev1.o obj-$(CONFIG_SND_SOC_WM2000) += snd-soc-wm2000.o @@ -377,7 +424,10 @@ obj-$(CONFIG_SND_SOC_WM9713) += snd-soc-wm9713.o obj-$(CONFIG_SND_SOC_WM_ADSP) += snd-soc-wm-adsp.o obj-$(CONFIG_SND_SOC_WM_HUBS) += snd-soc-wm-hubs.o +obj-$(CONFIG_SND_SOC_MSM_STUB) += snd-soc-msm-stub.o # Amp obj-$(CONFIG_SND_SOC_MAX9877) += snd-soc-max9877.o obj-$(CONFIG_SND_SOC_TPA6130A2) += snd-soc-tpa6130a2.o +obj-y += sdm660_cdc/ +obj-y += msm_sdw/ diff -ruw linux-4.4.115/sound/soc/codecs/wm8804.c linux-4.4.115-fbx/sound/soc/codecs/wm8804.c --- linux-4.4.115/sound/soc/codecs/wm8804.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/sound/soc/codecs/wm8804.c 2019-07-17 21:26:01.529863250 +0200 @@ -542,7 +542,70 @@ .symmetric_rates = 1 }; +static irqreturn_t wm8804_irq(int irq, void *data) +{ + struct snd_soc_codec *codec = data; + int irq_val, spd_val; + + irq_val = snd_soc_read(codec, WM8804_INTSTAT); + if (irq_val < 0) { + dev_err(codec->dev, "Failed to read IRQ status: %d\n", + irq_val); + return IRQ_NONE; + } + + if (irq_val & BIT(4)) { + spd_val = snd_soc_read(codec, WM8804_SPDSTAT); + if ((spd_val & BIT(0)) || (spd_val & BIT(1))) { + /* AUDIO_N or PCM_N, disable ALWAYSVALID flag to + * output zeroes until clients enables it again */ + snd_soc_update_bits(codec, WM8804_PLL6, BIT(6), 0); + } + } + + return IRQ_HANDLED; +} + +static int wm8804_codec_probe(struct snd_soc_codec *codec) +{ + struct gpio_desc *gpio_int; + int irq; + int ret; + + gpio_int = devm_gpiod_get_optional(codec->dev, "wlf,irq", GPIOD_IN); + if (IS_ERR(gpio_int)) { + dev_err(codec->dev, "Failed to get irq line\n"); + return PTR_ERR(gpio_int); + } + + if (gpio_int == NULL) { + dev_dbg(codec->dev, "No irq line\n"); + return 0; + } + + irq = gpiod_to_irq(gpio_int); + if (irq < 0) { + dev_err(codec->dev, "no irq resource found\n"); + return irq; + } + + ret = devm_request_threaded_irq(codec->dev, irq, NULL, + wm8804_irq, + IRQF_TRIGGER_FALLING | IRQF_ONESHOT, + "wm8804_irq", codec); + if (ret < 0) { + dev_err(codec->dev, "Failed to request IRQ: %d\n", ret); + return ret; + } + + /* Unmask UPD_AUDIO_N */ + snd_soc_write(codec, WM8804_INTMASK, ~BIT(4)); + + return 0; +} + static const struct snd_soc_codec_driver soc_codec_dev_wm8804 = { + .probe = wm8804_codec_probe, .idle_bias_off = true, .dapm_widgets = wm8804_dapm_widgets, diff -ruw linux-4.4.115/sound/soc/Kconfig linux-4.4.115-fbx/sound/soc/Kconfig --- linux-4.4.115/sound/soc/Kconfig 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/sound/soc/Kconfig 2019-01-22 16:16:29.491300631 +0100 @@ -51,6 +51,7 @@ source "sound/soc/omap/Kconfig" source "sound/soc/kirkwood/Kconfig" source "sound/soc/intel/Kconfig" +source "sound/soc/msm/Kconfig" source "sound/soc/mediatek/Kconfig" source "sound/soc/mxs/Kconfig" source "sound/soc/pxa/Kconfig" diff -ruw linux-4.4.115/sound/soc/Makefile linux-4.4.115-fbx/sound/soc/Makefile --- linux-4.4.115/sound/soc/Makefile 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/sound/soc/Makefile 2019-01-22 16:16:29.491300631 +0100 @@ -28,6 +28,7 @@ obj-$(CONFIG_SND_SOC) += fsl/ obj-$(CONFIG_SND_SOC) += jz4740/ obj-$(CONFIG_SND_SOC) += intel/ +obj-$(CONFIG_SND_SOC) += msm/ obj-$(CONFIG_SND_SOC) += mediatek/ obj-$(CONFIG_SND_SOC) += mxs/ obj-$(CONFIG_SND_SOC) += nuc900/ diff -ruw linux-4.4.115/sound/soc/soc-compress.c linux-4.4.115-fbx/sound/soc/soc-compress.c --- linux-4.4.115/sound/soc/soc-compress.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/sound/soc/soc-compress.c 2019-01-22 16:16:29.671302261 +0100 @@ -409,6 +409,37 @@ return ret; } +static void dpcm_be_hw_params_prepare(void *data) +{ + struct snd_compr_stream *cstream = data; + struct snd_soc_pcm_runtime *fe = cstream->private_data; + struct snd_soc_pcm_runtime *be = cstream->be; + int stream, ret; + + if (cstream->direction == SND_COMPRESS_PLAYBACK) + stream = SNDRV_PCM_STREAM_PLAYBACK; + else + stream = SNDRV_PCM_STREAM_CAPTURE; + + ret = dpcm_fe_dai_hw_params_be(fe, be, + &fe->dpcm[stream].hw_params, stream); + if (ret < 0) { + fe->err_ops = ret; + return; + } + + ret = dpcm_fe_dai_prepare_be(fe, be, stream); + if (ret < 0) { + fe->err_ops = ret; + return; + } +} + +static void dpcm_be_hw_params_prepare_async(void *data, async_cookie_t cookie) +{ + dpcm_be_hw_params_prepare(data); +} + static int soc_compr_set_params_fe(struct snd_compr_stream *cstream, struct snd_compr_params *params) { @@ -416,7 +447,11 @@ struct snd_pcm_substream *fe_substream = fe->pcm->streams[cstream->direction].substream; struct snd_soc_platform *platform = fe->platform; - int ret = 0, stream; + struct snd_soc_pcm_runtime *be_list[DPCM_MAX_BE_USERS]; + struct snd_soc_dpcm *dpcm; + int ret = 0, stream, i, j = 0; + + ASYNC_DOMAIN_EXCLUSIVE(async_domain); if (cstream->direction == SND_COMPRESS_PLAYBACK) stream = SNDRV_PCM_STREAM_PLAYBACK; @@ -425,22 +460,35 @@ mutex_lock_nested(&fe->card->mutex, SND_SOC_CARD_CLASS_RUNTIME); - if (platform->driver->compr_ops && platform->driver->compr_ops->set_params) { - ret = platform->driver->compr_ops->set_params(cstream, params); + if (!(fe->dai_link->async_ops & ASYNC_DPCM_SND_SOC_HW_PARAMS)) { + /* first we call set_params for the platform driver + * this should configure the soc side + * if the machine has compressed ops then we call that as well + * expectation is that platform and machine will configure + * everything for this compress path, like configuring pcm + * port for codec + */ + if (platform->driver->compr_ops && + platform->driver->compr_ops->set_params) { + ret = platform->driver->compr_ops->set_params(cstream, + params); if (ret < 0) goto out; } - if (fe->dai_link->compr_ops && fe->dai_link->compr_ops->set_params) { + if (fe->dai_link->compr_ops && + fe->dai_link->compr_ops->set_params) { ret = fe->dai_link->compr_ops->set_params(cstream); if (ret < 0) goto out; } /* - * Create an empty hw_params for the BE as the machine driver must - * fix this up to match DSP decoder and ASRC configuration. - * I.e. machine driver fixup for compressed BE is mandatory. + * Create an empty hw_params for the BE as the machine + * driver must fix this up to match DSP decoder and + * ASRC configuration. + * I.e. machine driver fixup for compressed BE is + * mandatory. */ memset(&fe->dpcm[fe_substream->stream].hw_params, 0, sizeof(struct snd_pcm_hw_params)); @@ -454,7 +502,70 @@ ret = dpcm_be_dai_prepare(fe, stream); if (ret < 0) goto out; + } else { + /* + * Create an empty hw_params for the BE as the machine + * driver must fix this up to match DSP decoder and + * ASRC configuration. + * I.e. machine driver fixup for compressed BE is + * mandatory. + */ + memset(&fe->dpcm[fe_substream->stream].hw_params, 0, + sizeof(struct snd_pcm_hw_params)); + + fe->dpcm[stream].runtime_update = SND_SOC_DPCM_UPDATE_FE; + list_for_each_entry(dpcm, + &fe->dpcm[stream].be_clients, list_be) { + struct snd_soc_pcm_runtime *be = dpcm->be; + + if (be->dai_link->async_ops & + ASYNC_DPCM_SND_SOC_HW_PARAMS) { + cstream->be = be; + async_schedule_domain( + dpcm_be_hw_params_prepare_async, + cstream, &async_domain); + } else { + be_list[j++] = be; + if (j == DPCM_MAX_BE_USERS) { + dev_dbg(fe->dev, + "ASoC: MAX backend users!\n"); + break; + } + } + } + for (i = 0; i < j; i++) { + cstream->be = be_list[i]; + dpcm_be_hw_params_prepare(cstream); + } + /* first we call set_params for the platform driver + * this should configure the soc side + * if the machine has compressed ops then we call that as well + * expectation is that platform and machine will configure + * everything this compress path, like configuring pcm port + * for codec + */ + if (platform->driver->compr_ops && + platform->driver->compr_ops->set_params) { + ret = platform->driver->compr_ops->set_params(cstream, + params); + if (ret < 0) + goto exit; + } + + dpcm_dapm_stream_event(fe, stream, SND_SOC_DAPM_STREAM_START); + + if (fe->dai_link->compr_ops && + fe->dai_link->compr_ops->set_params) { + ret = fe->dai_link->compr_ops->set_params(cstream); + if (ret < 0) + goto exit; + } +exit: + async_synchronize_full_domain(&async_domain); + if (fe->err_ops < 0 || ret < 0) + goto out; + } dpcm_dapm_stream_event(fe, stream, SND_SOC_DAPM_STREAM_START); fe->dpcm[stream].state = SND_SOC_DPCM_STATE_PREPARE; @@ -532,14 +643,15 @@ { struct snd_soc_pcm_runtime *rtd = cstream->private_data; struct snd_soc_platform *platform = rtd->platform; + int ret = 0; mutex_lock_nested(&rtd->pcm_mutex, rtd->pcm_subclass); if (platform->driver->compr_ops && platform->driver->compr_ops->pointer) - platform->driver->compr_ops->pointer(cstream, tstamp); + ret = platform->driver->compr_ops->pointer(cstream, tstamp); mutex_unlock(&rtd->pcm_mutex); - return 0; + return ret; } static int soc_compr_copy(struct snd_compr_stream *cstream, @@ -558,6 +670,22 @@ return ret; } +static int sst_compr_set_next_track_param(struct snd_compr_stream *cstream, + union snd_codec_options *codec_options) +{ + struct snd_soc_pcm_runtime *rtd = cstream->private_data; + struct snd_soc_platform *platform = rtd->platform; + int ret = 0; + + if (platform->driver->compr_ops && + platform->driver->compr_ops->set_next_track_param) + ret = platform->driver->compr_ops->set_next_track_param(cstream, + codec_options); + + return ret; +} + + static int soc_compr_set_metadata(struct snd_compr_stream *cstream, struct snd_compr_metadata *metadata) { @@ -590,6 +718,7 @@ .free = soc_compr_free, .set_params = soc_compr_set_params, .set_metadata = soc_compr_set_metadata, + .set_next_track_param = sst_compr_set_next_track_param, .get_metadata = soc_compr_get_metadata, .get_params = soc_compr_get_params, .trigger = soc_compr_trigger, @@ -606,6 +735,7 @@ .set_params = soc_compr_set_params_fe, .get_params = soc_compr_get_params, .set_metadata = soc_compr_set_metadata, + .set_next_track_param = sst_compr_set_next_track_param, .get_metadata = soc_compr_get_metadata, .trigger = soc_compr_trigger_fe, .pointer = soc_compr_pointer, @@ -721,8 +851,16 @@ rtd->compr = compr; compr->private_data = rtd; - printk(KERN_INFO "compress asoc: %s <-> %s mapping ok\n", codec_dai->name, - cpu_dai->name); + if (platform->driver->pcm_new) { + ret = platform->driver->pcm_new(rtd); + if (ret < 0) { + pr_err("asoc: compress pcm constructor failed\n"); + goto compr_err; + } + } + + dev_dbg(rtd->card->dev, "compress asoc: %s <-> %s mapping ok\n", + codec_dai->name, cpu_dai->name); return ret; compr_err: diff -ruw linux-4.4.115/sound/soc/soc-core.c linux-4.4.115-fbx/sound/soc/soc-core.c --- linux-4.4.115/sound/soc/soc-core.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/sound/soc/soc-core.c 2019-10-29 09:26:26.181228015 +0100 @@ -303,7 +303,7 @@ } if (!component->debugfs_root) { - dev_warn(component->dev, + dev_dbg(component->dev, "ASoC: Failed to create component debugfs directory\n"); return; } @@ -328,7 +328,7 @@ codec->component.debugfs_root, codec, &codec_reg_fops); if (!codec->debugfs_reg) - dev_warn(codec->dev, + dev_dbg(codec->dev, "ASoC: Failed to create codec register debugfs file\n"); } @@ -861,11 +861,27 @@ static const struct snd_soc_dai_ops null_dai_ops = { }; -static struct snd_soc_component *soc_find_component( +/** + * soc_find_component: find a component from component_list in ASoC core + * + * @of_node: of_node of the component to query. + * @name: name of the component to query. + * + * function to find out if a component is already registered with ASoC core. + * + * Returns component handle for success, else NULL error. + */ +struct snd_soc_component *soc_find_component( const struct device_node *of_node, const char *name) { struct snd_soc_component *component; + if (!of_node && !name) { + pr_err("%s: Either of_node or name must be valid\n", + __func__); + return NULL; + } + lockdep_assert_held(&client_mutex); list_for_each_entry(component, &component_list, list) { @@ -879,6 +895,7 @@ return NULL; } +EXPORT_SYMBOL(soc_find_component); static struct snd_soc_dai *snd_soc_find_dai( const struct snd_soc_dai_link_component *dlc) @@ -2294,8 +2311,7 @@ if (dai->driver->ops->mute_stream) return dai->driver->ops->mute_stream(dai, mute, direction); - else if (direction == SNDRV_PCM_STREAM_PLAYBACK && - dai->driver->ops->digital_mute) + else if (dai->driver->ops->digital_mute) return dai->driver->ops->digital_mute(dai, mute); else return -ENOTSUPP; @@ -2437,6 +2453,7 @@ card->instantiated = 0; mutex_init(&card->mutex); mutex_init(&card->dapm_mutex); + mutex_init(&card->dapm_power_mutex); ret = snd_soc_instantiate_card(card); if (ret != 0) @@ -3040,6 +3057,18 @@ } /** + * snd_soc_card_change_online_state - Mark if soc card is online/offline + * + * @soc_card : soc_card to mark + */ +void snd_soc_card_change_online_state(struct snd_soc_card *soc_card, int online) +{ + if (soc_card && soc_card->snd_card) + snd_card_change_online_state(soc_card->snd_card, online); +} +EXPORT_SYMBOL(snd_soc_card_change_online_state); + +/** * snd_soc_register_codec - Register a codec with the ASoC core * * @dev: The parent device for this codec @@ -3588,6 +3617,63 @@ return ret; } +/** + * snd_soc_info_multi_ext - external single mixer info callback + * @kcontrol: mixer control + * @uinfo: control element information + * + * Callback to provide information about a single external mixer control. + * that accepts multiple input. + * + * Returns 0 for success. + */ +int snd_soc_info_multi_ext(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_info *uinfo) +{ + struct soc_multi_mixer_control *mc = + (struct soc_multi_mixer_control *)kcontrol->private_value; + int platform_max; + + if (!mc->platform_max) + mc->platform_max = mc->max; + platform_max = mc->platform_max; + + if (platform_max == 1 && !strnstr(kcontrol->id.name, " Volume", 30)) + uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN; + else + uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; + + uinfo->count = mc->count; + uinfo->value.integer.min = 0; + uinfo->value.integer.max = platform_max; + return 0; +} +EXPORT_SYMBOL_GPL(snd_soc_info_multi_ext); + +/** + * snd_soc_dai_get_channel_map - configure DAI audio channel map + * @dai: DAI + * @tx_num: how many TX channels + * @tx_slot: pointer to an array which imply the TX slot number channel + * 0~num-1 uses + * @rx_num: how many RX channels + * @rx_slot: pointer to an array which imply the RX slot number channel + * 0~num-1 uses + * + * configure the relationship between channel number and TDM slot number. + */ +int snd_soc_dai_get_channel_map(struct snd_soc_dai *dai, + unsigned int *tx_num, unsigned int *tx_slot, + unsigned int *rx_num, unsigned int *rx_slot) +{ + if (dai->driver && dai->driver->ops->get_channel_map) + return dai->driver->ops->get_channel_map(dai, tx_num, tx_slot, + rx_num, rx_slot); + else + return -EINVAL; +} +EXPORT_SYMBOL_GPL(snd_soc_dai_get_channel_map); + int snd_soc_of_get_dai_name(struct device_node *of_node, const char **dai_name) { diff -ruw linux-4.4.115/sound/soc/soc-dapm.c linux-4.4.115-fbx/sound/soc/soc-dapm.c --- linux-4.4.115/sound/soc/soc-dapm.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/sound/soc/soc-dapm.c 2019-10-29 09:26:26.181228015 +0100 @@ -78,8 +78,7 @@ [snd_soc_dapm_dai_link] = 2, [snd_soc_dapm_dai_in] = 4, [snd_soc_dapm_dai_out] = 4, - [snd_soc_dapm_aif_in] = 4, - [snd_soc_dapm_aif_out] = 4, + [snd_soc_dapm_adc] = 4, [snd_soc_dapm_mic] = 5, [snd_soc_dapm_mux] = 6, [snd_soc_dapm_demux] = 6, @@ -88,7 +87,8 @@ [snd_soc_dapm_mixer] = 8, [snd_soc_dapm_mixer_named_ctl] = 8, [snd_soc_dapm_pga] = 9, - [snd_soc_dapm_adc] = 10, + [snd_soc_dapm_aif_in] = 9, + [snd_soc_dapm_aif_out] = 9, [snd_soc_dapm_out_drv] = 11, [snd_soc_dapm_hp] = 11, [snd_soc_dapm_spk] = 11, @@ -100,7 +100,9 @@ static int dapm_down_seq[] = { [snd_soc_dapm_pre] = 0, [snd_soc_dapm_kcontrol] = 1, - [snd_soc_dapm_adc] = 2, + [snd_soc_dapm_aif_in] = 2, + [snd_soc_dapm_aif_out] = 2, + [snd_soc_dapm_adc] = 5, [snd_soc_dapm_hp] = 3, [snd_soc_dapm_spk] = 3, [snd_soc_dapm_line] = 3, @@ -114,8 +116,6 @@ [snd_soc_dapm_micbias] = 8, [snd_soc_dapm_mux] = 9, [snd_soc_dapm_demux] = 9, - [snd_soc_dapm_aif_in] = 10, - [snd_soc_dapm_aif_out] = 10, [snd_soc_dapm_dai_in] = 10, [snd_soc_dapm_dai_out] = 10, [snd_soc_dapm_dai_link] = 11, @@ -282,6 +282,8 @@ mutex_lock(&card->dapm_mutex); list_for_each_entry(w, &card->widgets, list) { + if (w->ignore_suspend) + continue; if (w->is_ep) { dapm_mark_dirty(w, "Rechecking endpoints"); if (w->is_ep & SND_SOC_DAPM_EP_SINK) @@ -429,13 +431,14 @@ kfree(data); } -static struct snd_soc_dapm_widget_list *dapm_kcontrol_get_wlist( +struct snd_soc_dapm_widget_list *dapm_kcontrol_get_wlist( const struct snd_kcontrol *kcontrol) { struct dapm_kcontrol_data *data = snd_kcontrol_chip(kcontrol); return data->wlist; } +EXPORT_SYMBOL(dapm_kcontrol_get_wlist); static int dapm_kcontrol_add_widget(struct snd_kcontrol *kcontrol, struct snd_soc_dapm_widget *widget) @@ -740,7 +743,7 @@ unsigned int max = mc->max; unsigned int mask = (1 << fls(max)) - 1; unsigned int invert = mc->invert; - unsigned int val; + unsigned int val = 0; if (reg != SND_SOC_NOPM) { soc_dapm_read(p->sink->dapm, reg, &val); @@ -1490,7 +1493,7 @@ /* Do we need to apply any queued changes? */ if (sort[w->id] != cur_sort || w->reg != cur_reg || w->dapm != cur_dapm || w->subseq != cur_subseq) { - if (!list_empty(&pending)) + if (cur_dapm && !list_empty(&pending)) dapm_seq_run_coalesced(card, &pending); if (cur_dapm && cur_dapm->seq_notifier) { @@ -1548,12 +1551,17 @@ break; } + /* Add this debug log to keep track of widgets being + * powered-up and powered-down */ + dev_dbg(w->dapm->dev, "dapm: powering %s widget %s\n", + power_up ? "up" : "down", w->name); + if (ret < 0) dev_err(w->dapm->dev, "ASoC: Failed to apply widget power: %d\n", ret); } - if (!list_empty(&pending)) + if (cur_dapm && !list_empty(&pending)) dapm_seq_run_coalesced(card, &pending); if (cur_dapm && cur_dapm->seq_notifier) { @@ -1785,10 +1793,13 @@ LIST_HEAD(down_list); ASYNC_DOMAIN_EXCLUSIVE(async_domain); enum snd_soc_bias_level bias; + struct snd_soc_platform *p; + struct snd_soc_codec *c; lockdep_assert_held(&card->dapm_mutex); trace_snd_soc_dapm_start(card); + mutex_lock(&card->dapm_power_mutex); list_for_each_entry(d, &card->dapm_list, list) { if (dapm_idle_bias_off(d)) @@ -1866,7 +1877,9 @@ dapm_pre_sequence_async(&card->dapm, 0); /* Run other bias changes in parallel */ list_for_each_entry(d, &card->dapm_list, list) { - if (d != &card->dapm) + p = snd_soc_dapm_to_platform(d); + c = snd_soc_dapm_to_codec(d); + if ((d != &card->dapm) && (c || p)) async_schedule_domain(dapm_pre_sequence_async, d, &async_domain); } @@ -1890,7 +1903,9 @@ /* Run all the bias changes in parallel */ list_for_each_entry(d, &card->dapm_list, list) { - if (d != &card->dapm) + p = snd_soc_dapm_to_platform(d); + c = snd_soc_dapm_to_codec(d); + if ((d != &card->dapm) && (c || p)) async_schedule_domain(dapm_post_sequence_async, d, &async_domain); } @@ -1907,6 +1922,7 @@ pop_dbg(card->dev, card->pop_time, "DAPM sequencing finished, waiting %dms\n", card->pop_time); pop_wait(card->pop_time); + mutex_unlock(&card->dapm_power_mutex); trace_snd_soc_dapm_done(card); @@ -2616,7 +2632,6 @@ dapm_mark_dirty(widgets[dir], "Route added"); } - if (dapm->card->instantiated && path->connect) dapm_path_invalidate(path); return 0; @@ -3905,6 +3920,9 @@ for (i = 0; i < rtd->num_codecs; i++) { struct snd_soc_dai *codec_dai = rtd->codec_dais[i]; + if (!cpu_dai->component->codec) + continue; + /* connect BE DAI playback if widgets are valid */ if (codec_dai->playback_widget && cpu_dai->playback_widget) { source = cpu_dai->playback_widget; diff -ruw linux-4.4.115/sound/soc/soc-ops.c linux-4.4.115-fbx/sound/soc/soc-ops.c --- linux-4.4.115/sound/soc/soc-ops.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/sound/soc/soc-ops.c 2019-10-29 09:26:26.181228015 +0100 @@ -201,7 +201,10 @@ uinfo->count = snd_soc_volsw_is_stereo(mc) ? 2 : 1; uinfo->value.integer.min = 0; + if (uinfo->type == SNDRV_CTL_ELEM_TYPE_INTEGER) uinfo->value.integer.max = platform_max - mc->min; + else + uinfo->value.integer.max = platform_max; return 0; } EXPORT_SYMBOL_GPL(snd_soc_info_volsw); @@ -221,14 +224,12 @@ int snd_soc_info_volsw_sx(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) { - struct soc_mixer_control *mc = - (struct soc_mixer_control *)kcontrol->private_value; - snd_soc_info_volsw(kcontrol, uinfo); /* Max represents the number of levels in an SX control not the - * maximum value, so add the minimum value back on + * maximum value. + * uinfo->value.integer.max is set to number of levels + * in snd_soc_info_volsw_sx. No further adjustment is necessary. */ - uinfo->value.integer.max += mc->min; return 0; } @@ -779,11 +780,11 @@ switch (op_flag) { case SNDRV_CTL_TLV_OP_READ: if (params->get) - ret = params->get(tlv, count); + ret = params->get(kcontrol, tlv, count); break; case SNDRV_CTL_TLV_OP_WRITE: if (params->put) - ret = params->put(tlv, count); + ret = params->put(kcontrol, tlv, count); break; } return ret; diff -ruw linux-4.4.115/sound/soc/soc-pcm.c linux-4.4.115-fbx/sound/soc/soc-pcm.c --- linux-4.4.115/sound/soc/soc-pcm.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/sound/soc/soc-pcm.c 2019-10-29 09:26:26.185228054 +0100 @@ -25,6 +25,7 @@ #include #include #include +#include #include #include #include @@ -52,6 +53,26 @@ return codec_stream->rates; } +static const struct snd_pcm_hardware no_host_hardware = { + .info = SNDRV_PCM_INFO_MMAP | + SNDRV_PCM_INFO_MMAP_VALID | + SNDRV_PCM_INFO_INTERLEAVED | + SNDRV_PCM_INFO_PAUSE | + SNDRV_PCM_INFO_RESUME, + .formats = SNDRV_PCM_FMTBIT_S16_LE | + SNDRV_PCM_FMTBIT_S32_LE, + .period_bytes_min = PAGE_SIZE >> 2, + .period_bytes_max = PAGE_SIZE >> 1, + .periods_min = 2, + .periods_max = 4, + /* + * Increase the max buffer bytes as PAGE_SIZE bytes is + * not enough to encompass all the scenarios sent by + * userspapce. + */ + .buffer_bytes_max = PAGE_SIZE * 4, +}; + /** * snd_soc_runtime_activate() - Increment active count for PCM runtime components * @rtd: ASoC PCM runtime that is activated @@ -156,6 +177,8 @@ const struct snd_pcm_hardware *hw) { struct snd_pcm_runtime *runtime = substream->runtime; + if (!runtime) + return 0; runtime->hw.info = hw->info; runtime->hw.formats = hw->formats; runtime->hw.period_bytes_min = hw->period_bytes_min; @@ -182,8 +205,10 @@ be->dai_link->name, event, dir); if ((event == SND_SOC_DAPM_STREAM_STOP) && - (be->dpcm[dir].users >= 1)) + (be->dpcm[dir].users >= 1)) { + pr_debug("%s Don't close BE \n", __func__); continue; + } snd_soc_dapm_stream_event(be, dir, event); } @@ -468,6 +493,8 @@ pm_runtime_get_sync(platform->dev); mutex_lock_nested(&rtd->pcm_mutex, rtd->pcm_subclass); + if (rtd->dai_link->no_host_mode == SND_SOC_DAI_LINK_NO_HOST) + snd_soc_set_runtime_hwparams(substream, &no_host_hardware); /* startup the audio subsystem */ if (cpu_dai->driver->ops && cpu_dai->driver->ops->startup) { @@ -598,7 +625,7 @@ platform->driver->ops->close(substream); platform_err: - if (cpu_dai->driver->ops->shutdown) + if (cpu_dai->driver->ops && cpu_dai->driver->ops->shutdown) cpu_dai->driver->ops->shutdown(substream, cpu_dai); out: mutex_unlock(&rtd->pcm_mutex); @@ -674,6 +701,20 @@ snd_soc_dai_digital_mute(cpu_dai, 1, substream->stream); + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { + if (snd_soc_runtime_ignore_pmdown_time(rtd)) { + /* powered down playback stream now */ + snd_soc_dapm_stream_event(rtd, + SNDRV_PCM_STREAM_PLAYBACK, + SND_SOC_DAPM_STREAM_STOP); + } else { + /* start delayed pop wq here for playback streams */ + rtd->pop_wait = 1; + queue_delayed_work(system_power_efficient_wq, + &rtd->delayed_work, + msecs_to_jiffies(rtd->pmdown_time)); + } + } if (cpu_dai->driver->ops->shutdown) cpu_dai->driver->ops->shutdown(substream, cpu_dai); @@ -689,20 +730,7 @@ if (platform->driver->ops && platform->driver->ops->close) platform->driver->ops->close(substream); - if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { - if (snd_soc_runtime_ignore_pmdown_time(rtd)) { - /* powered down playback stream now */ - snd_soc_dapm_stream_event(rtd, - SNDRV_PCM_STREAM_PLAYBACK, - SND_SOC_DAPM_STREAM_STOP); - } else { - /* start delayed pop wq here for playback streams */ - rtd->pop_wait = 1; - queue_delayed_work(system_power_efficient_wq, - &rtd->delayed_work, - msecs_to_jiffies(rtd->pmdown_time)); - } - } else { + if (substream->stream != SNDRV_PCM_STREAM_PLAYBACK) { /* capture streams can be powered down now */ snd_soc_dapm_stream_event(rtd, SNDRV_PCM_STREAM_CAPTURE, SND_SOC_DAPM_STREAM_STOP); @@ -739,6 +767,11 @@ mutex_lock_nested(&rtd->pcm_mutex, rtd->pcm_subclass); + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) + snd_soc_dapm_stream_event(rtd, + SNDRV_PCM_STREAM_PLAYBACK, + SND_SOC_DAPM_STREAM_START); + if (rtd->dai_link->ops && rtd->dai_link->ops->prepare) { ret = rtd->dai_link->ops->prepare(substream); if (ret < 0) { @@ -787,8 +820,15 @@ cancel_delayed_work(&rtd->delayed_work); } - snd_soc_dapm_stream_event(rtd, substream->stream, + if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) { + for (i = 0; i < rtd->num_codecs; i++) { + codec_dai = rtd->codec_dais[i]; + if (codec_dai->capture_active == 1) + snd_soc_dapm_stream_event(rtd, + SNDRV_PCM_STREAM_CAPTURE, SND_SOC_DAPM_STREAM_START); + } + } for (i = 0; i < rtd->num_codecs; i++) snd_soc_dai_digital_mute(rtd->codec_dais[i], 0, @@ -796,6 +836,13 @@ snd_soc_dai_digital_mute(cpu_dai, 0, substream->stream); out: + if (ret < 0 && substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { + pr_err("%s: Issue stop stream for codec_dai due to op failure %d = ret\n", + __func__, ret); + snd_soc_dapm_stream_event(rtd, + SNDRV_PCM_STREAM_PLAYBACK, + SND_SOC_DAPM_STREAM_STOP); + } mutex_unlock(&rtd->pcm_mutex); return ret; } @@ -844,10 +891,31 @@ mutex_lock_nested(&rtd->pcm_mutex, rtd->pcm_subclass); + /* perform any hw_params fixups */ + if ((rtd->dai_link->no_host_mode == SND_SOC_DAI_LINK_NO_HOST) && + rtd->dai_link->be_hw_params_fixup) { + ret = rtd->dai_link->be_hw_params_fixup(rtd, + params); + if (ret < 0) + dev_err(rtd->card->dev, "ASoC: fixup failed for %s\n", + rtd->dai_link->name); + } + ret = soc_pcm_params_symmetry(substream, params); if (ret) goto out; + /* perform any hw_params fixups */ + if ((rtd->dai_link->no_host_mode == SND_SOC_DAI_LINK_NO_HOST) && + rtd->dai_link->be_hw_params_fixup) { + ret = rtd->dai_link->be_hw_params_fixup(rtd, + params); + if (ret < 0) { + dev_err(rtd->card->dev, "ASoC: fixup failed for %s\n", + rtd->dai_link->name); + } + } + if (rtd->dai_link->ops && rtd->dai_link->ops->hw_params) { ret = rtd->dai_link->ops->hw_params(substream, params); if (ret < 0) { @@ -917,6 +985,22 @@ cpu_dai->channels = params_channels(params); cpu_dai->sample_bits = snd_pcm_format_physical_width(params_format(params)); + /* malloc a page for hostless IO. + * FIXME: rework with alsa-lib changes so that this malloc is not required. + */ + if (rtd->dai_link->no_host_mode == SND_SOC_DAI_LINK_NO_HOST) { + substream->dma_buffer.dev.type = SNDRV_DMA_TYPE_DEV; + substream->dma_buffer.dev.dev = rtd->dev; + substream->dma_buffer.dev.dev->coherent_dma_mask = + DMA_BIT_MASK(sizeof(dma_addr_t) * 8); + substream->dma_buffer.private_data = NULL; + + arch_setup_dma_ops(substream->dma_buffer.dev.dev, + 0, 0, NULL, 0); + ret = snd_pcm_lib_malloc_pages(substream, PAGE_SIZE); + if (ret < 0) + goto platform_err; + } out: mutex_unlock(&rtd->pcm_mutex); @@ -1000,6 +1084,9 @@ if (cpu_dai->driver->ops && cpu_dai->driver->ops->hw_free) cpu_dai->driver->ops->hw_free(substream, cpu_dai); + if (rtd->dai_link->no_host_mode == SND_SOC_DAI_LINK_NO_HOST) + snd_pcm_lib_free_pages(substream); + mutex_unlock(&rtd->pcm_mutex); return 0; } @@ -1096,6 +1183,9 @@ if (platform->driver->ops && platform->driver->ops->pointer) offset = platform->driver->ops->pointer(substream); + if (platform->driver->delay_blk) + return offset; + if (cpu_dai->driver->ops && cpu_dai->driver->ops->delay) delay += cpu_dai->driver->ops->delay(substream, cpu_dai); @@ -1120,6 +1210,22 @@ return offset; } +static int soc_pcm_delay_blk(struct snd_pcm_substream *substream) +{ + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct snd_soc_platform *platform = rtd->platform; + struct snd_pcm_runtime *runtime = substream->runtime; + snd_pcm_sframes_t delay = 0; + + if (platform->driver->delay_blk) + delay = platform->driver->delay_blk(substream, + rtd->codec_dais[0]); + + runtime->delay = delay; + + return 0; +} + /* connect a FE and BE */ static int dpcm_be_connect(struct snd_soc_pcm_runtime *fe, struct snd_soc_pcm_runtime *be, int stream) @@ -1226,7 +1332,11 @@ if (!be->dai_link->no_pcm) continue; - if (be->cpu_dai->playback_widget == widget) + if ((be->cpu_dai->playback_widget == widget && + (be->dai_link->stream_name && + !strcmp(be->dai_link->stream_name, + be->cpu_dai->playback_widget->sname))) || + be->codec_dai->playback_widget == widget) return be; for (j = 0; j < be->num_codecs; j++) { @@ -1243,7 +1353,11 @@ if (!be->dai_link->no_pcm) continue; - if (be->cpu_dai->capture_widget == widget) + if ((be->cpu_dai->capture_widget == widget && + (be->dai_link->stream_name && + !strcmp(be->dai_link->stream_name, + be->cpu_dai->capture_widget->sname))) || + be->codec_dai->capture_widget == widget) return be; for (j = 0; j < be->num_codecs; j++) { @@ -1703,14 +1817,14 @@ dpcm_set_fe_update_state(fe, stream, SND_SOC_DPCM_UPDATE_FE); - /* shutdown the BEs */ - dpcm_be_dai_shutdown(fe, substream->stream); - dev_dbg(fe->dev, "ASoC: close FE %s\n", fe->dai_link->name); /* now shutdown the frontend */ soc_pcm_close(substream); + /* shutdown the BEs */ + dpcm_be_dai_shutdown(fe, substream->stream); + /* run the stream event for each BE */ dpcm_dapm_stream_event(fe, stream, SND_SOC_DAPM_STREAM_STOP); @@ -1789,6 +1903,81 @@ return 0; } +int dpcm_fe_dai_hw_params_be(struct snd_soc_pcm_runtime *fe, + struct snd_soc_pcm_runtime *be, + struct snd_pcm_hw_params *params, int stream) +{ + int ret; + struct snd_soc_dpcm *dpcm; + struct snd_pcm_substream *be_substream = + snd_soc_dpcm_get_substream(be, stream); + + /* is this op for this BE ? */ + if (!snd_soc_dpcm_be_can_update(fe, be, stream)) + return 0; + + /* only allow hw_params() if no connected FEs are running */ + if (!snd_soc_dpcm_can_be_params(fe, be, stream)) + return 0; + + if ((be->dpcm[stream].state != SND_SOC_DPCM_STATE_OPEN) && + (be->dpcm[stream].state != + SND_SOC_DPCM_STATE_HW_PARAMS) && + (be->dpcm[stream].state != SND_SOC_DPCM_STATE_HW_FREE)) + return 0; + + dev_dbg(be->dev, "ASoC: hw_params BE %s\n", + fe->dai_link->name); + + /* perform any hw_params fixups */ + if (be->dai_link->be_hw_params_fixup) { + ret = be->dai_link->be_hw_params_fixup(be, + params); + if (ret < 0) { + dev_err(be->dev, + "ASoC: hw_params BE fixup failed %d\n", + ret); + goto unwind; + } + } + + ret = soc_pcm_hw_params(be_substream, params); + if (ret < 0) { + dev_err(be->dev, "ASoC: hw_params BE failed %d\n", ret); + goto unwind; + } + + be->dpcm[stream].state = SND_SOC_DPCM_STATE_HW_PARAMS; + return 0; + +unwind: + /* disable any enabled and non active backends */ + list_for_each_entry(dpcm, &fe->dpcm[stream].be_clients, list_be) { + struct snd_soc_pcm_runtime *be = dpcm->be; + struct snd_pcm_substream *be_substream = + snd_soc_dpcm_get_substream(be, stream); + + if (!snd_soc_dpcm_be_can_update(fe, be, stream)) + continue; + + /* only allow hw_free() if no connected FEs are running */ + if (!snd_soc_dpcm_can_be_free_stop(fe, be, stream)) + continue; + + if ((be->dpcm[stream].state != SND_SOC_DPCM_STATE_OPEN) && + (be->dpcm[stream].state + != SND_SOC_DPCM_STATE_HW_PARAMS) && + (be->dpcm[stream].state + != SND_SOC_DPCM_STATE_HW_FREE) && + (be->dpcm[stream].state != SND_SOC_DPCM_STATE_STOP)) + continue; + + soc_pcm_hw_free(be_substream); + } + + return ret; +} + int dpcm_be_dai_hw_params(struct snd_soc_pcm_runtime *fe, int stream) { struct snd_soc_dpcm *dpcm; @@ -2089,6 +2278,35 @@ return ret; } +int dpcm_fe_dai_prepare_be(struct snd_soc_pcm_runtime *fe, + struct snd_soc_pcm_runtime *be, int stream) +{ + struct snd_pcm_substream *be_substream = + snd_soc_dpcm_get_substream(be, stream); + int ret = 0; + + /* is this op for this BE ? */ + if (!snd_soc_dpcm_be_can_update(fe, be, stream)) + return 0; + + if ((be->dpcm[stream].state != SND_SOC_DPCM_STATE_HW_PARAMS) && + (be->dpcm[stream].state != SND_SOC_DPCM_STATE_STOP)) + return 0; + + dev_dbg(be->dev, "ASoC: prepare BE %s\n", + fe->dai_link->name); + + ret = soc_pcm_prepare(be_substream); + if (ret < 0) { + dev_err(be->dev, "ASoC: backend prepare failed %d\n", + ret); + return ret; + } + + be->dpcm[stream].state = SND_SOC_DPCM_STATE_PREPARE; + return ret; +} + static int dpcm_fe_dai_trigger(struct snd_pcm_substream *substream, int cmd) { struct snd_soc_pcm_runtime *fe = substream->private_data; @@ -2140,13 +2358,94 @@ return ret; } +static void dpcm_be_async_prepare(void *data, async_cookie_t cookie) +{ + struct snd_soc_dpcm *dpcm = data; + struct snd_soc_pcm_runtime *be = dpcm->be; + int stream = dpcm->stream; + struct snd_pcm_substream *be_substream = + snd_soc_dpcm_get_substream(be, stream); + int ret; + + dev_dbg(be->dev, "%s ASoC: prepare BE %s\n", __func__, + dpcm->fe->dai_link->name); + ret = soc_pcm_prepare(be_substream); + if (ret < 0) { + be->err_ops = ret; + dev_err(be->dev, "ASoC: backend prepare failed %d\n", + ret); + return; + } + be->dpcm[stream].state = SND_SOC_DPCM_STATE_PREPARE; +} + +void dpcm_be_dai_prepare_async(struct snd_soc_pcm_runtime *fe, int stream, + struct async_domain *domain) +{ + struct snd_soc_dpcm *dpcm; + struct snd_soc_dpcm *dpcm_async[DPCM_MAX_BE_USERS]; + int i = 0, j; + + list_for_each_entry(dpcm, &fe->dpcm[stream].be_clients, list_be) { + struct snd_soc_pcm_runtime *be = dpcm->be; + + be->err_ops = 0; + /* is this op for this BE ? */ + if (!snd_soc_dpcm_be_can_update(fe, be, stream)) + continue; + + if ((be->dpcm[stream].state != SND_SOC_DPCM_STATE_HW_PARAMS) && + (be->dpcm[stream].state != SND_SOC_DPCM_STATE_STOP)) + continue; + + /* does this BE support async op ?*/ + if ((fe->dai_link->async_ops & ASYNC_DPCM_SND_SOC_PREPARE) && + (be->dai_link->async_ops & ASYNC_DPCM_SND_SOC_PREPARE)) { + dpcm->stream = stream; + async_schedule_domain(dpcm_be_async_prepare, + dpcm, domain); + } else { + dpcm_async[i++] = dpcm; + if (i == DPCM_MAX_BE_USERS) { + dev_dbg(fe->dev, "ASoC: MAX backend users!\n"); + break; + } + } + } + + for (j = 0; j < i; j++) { + struct snd_soc_dpcm *dpcm = dpcm_async[j]; + struct snd_soc_pcm_runtime *be = dpcm->be; + struct snd_pcm_substream *be_substream = + snd_soc_dpcm_get_substream(be, stream); + int ret; + + dev_dbg(be->dev, "ASoC: prepare BE %s\n", + dpcm->fe->dai_link->name); + + ret = soc_pcm_prepare(be_substream); + if (ret < 0) { + dev_err(be->dev, "ASoC: backend prepare failed %d\n", + ret); + be->err_ops = ret; + return; + } + + be->dpcm[stream].state = SND_SOC_DPCM_STATE_PREPARE; + } +} + static int dpcm_fe_dai_prepare(struct snd_pcm_substream *substream) { struct snd_soc_pcm_runtime *fe = substream->private_data; + struct snd_soc_dpcm *dpcm; int stream = substream->stream, ret = 0; + ASYNC_DOMAIN_EXCLUSIVE(async_domain); mutex_lock_nested(&fe->card->mutex, SND_SOC_CARD_CLASS_RUNTIME); + fe->err_ops = 0; + dev_dbg(fe->dev, "ASoC: prepare FE %s\n", fe->dai_link->name); dpcm_set_fe_update_state(fe, stream, SND_SOC_DPCM_UPDATE_FE); @@ -2159,17 +2458,48 @@ goto out; } + if (!(fe->dai_link->async_ops & ASYNC_DPCM_SND_SOC_PREPARE)) { ret = dpcm_be_dai_prepare(fe, substream->stream); if (ret < 0) goto out; + /* call prepare on the frontend */ + ret = soc_pcm_prepare(substream); + if (ret < 0) { + dev_err(fe->dev, "ASoC: prepare FE %s failed\n", + fe->dai_link->name); + goto out; + } + } else { + dpcm_be_dai_prepare_async(fe, substream->stream, + &async_domain); /* call prepare on the frontend */ ret = soc_pcm_prepare(substream); if (ret < 0) { + fe->err_ops = ret; dev_err(fe->dev,"ASoC: prepare FE %s failed\n", fe->dai_link->name); + } + + async_synchronize_full_domain(&async_domain); + + /* check if any BE failed */ + list_for_each_entry(dpcm, &fe->dpcm[stream].be_clients, + list_be) { + struct snd_soc_pcm_runtime *be = dpcm->be; + + if (be->err_ops < 0) { + ret = be->err_ops; goto out; } + } + + /* check if FE failed */ + if (fe->err_ops < 0) { + ret = fe->err_ops; + goto out; + } + } /* run the stream event for each BE */ dpcm_dapm_stream_event(fe, stream, SND_SOC_DAPM_STREAM_START); @@ -2182,6 +2512,18 @@ return ret; } +static int soc_pcm_compat_ioctl(struct snd_pcm_substream *substream, + unsigned int cmd, void *arg) +{ + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct snd_soc_platform *platform = rtd->platform; + + if (platform->driver->ops->compat_ioctl) + return platform->driver->ops->compat_ioctl(substream, + cmd, arg); + return snd_pcm_lib_ioctl(substream, cmd, arg); +} + static int soc_pcm_ioctl(struct snd_pcm_substream *substream, unsigned int cmd, void *arg) { @@ -2610,9 +2952,27 @@ pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream->private_data = rtd; if (capture) pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream->private_data = rtd; + if (platform->driver->pcm_new) + rtd->platform->driver->pcm_new(rtd); goto out; } + /* setup any hostless PCMs - i.e. no host IO is performed */ + if (rtd->dai_link->no_host_mode) { + if (pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream) { + pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream->hw_no_buffer = 1; + snd_soc_set_runtime_hwparams( + pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream, + &no_host_hardware); + } + if (pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream) { + pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream->hw_no_buffer = 1; + snd_soc_set_runtime_hwparams( + pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream, + &no_host_hardware); + } + } + /* ASoC PCM operations */ if (rtd->dai_link->dynamic) { rtd->ops.open = dpcm_fe_dai_open; @@ -2622,7 +2982,9 @@ rtd->ops.hw_free = dpcm_fe_dai_hw_free; rtd->ops.close = dpcm_fe_dai_close; rtd->ops.pointer = soc_pcm_pointer; + rtd->ops.delay_blk = soc_pcm_delay_blk; rtd->ops.ioctl = soc_pcm_ioctl; + rtd->ops.compat_ioctl = soc_pcm_compat_ioctl; } else { rtd->ops.open = soc_pcm_open; rtd->ops.hw_params = soc_pcm_hw_params; @@ -2631,7 +2993,9 @@ rtd->ops.hw_free = soc_pcm_hw_free; rtd->ops.close = soc_pcm_close; rtd->ops.pointer = soc_pcm_pointer; + rtd->ops.delay_blk = soc_pcm_delay_blk; rtd->ops.ioctl = soc_pcm_ioctl; + rtd->ops.compat_ioctl = soc_pcm_compat_ioctl; } if (platform->driver->ops) { @@ -2660,7 +3024,7 @@ pcm->private_free = platform->driver->pcm_free; out: - dev_info(rtd->card->dev, "%s <-> %s mapping ok\n", + dev_dbg(rtd->card->dev, "%s <-> %s mapping ok\n", (rtd->num_codecs > 1) ? "multicodec" : rtd->codec_dai->name, cpu_dai->name); return ret; diff -ruw linux-4.4.115/sound/soc/soc-utils.c linux-4.4.115-fbx/sound/soc/soc-utils.c --- linux-4.4.115/sound/soc/soc-utils.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/sound/soc/soc-utils.c 2019-01-22 16:16:29.679302334 +0100 @@ -139,6 +139,9 @@ { int ret; + memset(&dummy_codec, 0, + sizeof(struct snd_soc_codec_driver)); + ret = snd_soc_register_codec(&pdev->dev, &dummy_codec, &dummy_dai, 1); if (ret < 0) return ret; diff -ruw linux-4.4.115/sound/usb/card.c linux-4.4.115-fbx/sound/usb/card.c --- linux-4.4.115/sound/usb/card.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/sound/usb/card.c 2019-10-29 09:26:26.189228093 +0100 @@ -45,6 +45,7 @@ #include #include #include +#include #include #include @@ -110,6 +111,71 @@ static struct snd_usb_audio *usb_chip[SNDRV_CARDS]; static struct usb_driver usb_audio_driver; +struct snd_usb_substream *find_snd_usb_substream(unsigned int card_num, + unsigned int pcm_idx, unsigned int direction, struct snd_usb_audio + **uchip, void (*disconnect_cb)(struct snd_usb_audio *chip)) +{ + int idx; + struct snd_usb_stream *as; + struct snd_usb_substream *subs = NULL; + struct snd_usb_audio *chip = NULL; + + mutex_lock(®ister_mutex); + /* + * legacy audio snd card number assignment is dynamic. Hence + * search using chip->card->number + */ + for (idx = 0; idx < SNDRV_CARDS; idx++) { + if (!usb_chip[idx]) + continue; + if (usb_chip[idx]->card->number == card_num) { + chip = usb_chip[idx]; + break; + } + } + + if (!chip || atomic_read(&chip->shutdown)) { + pr_debug("%s: instance of usb crad # %d does not exist\n", + __func__, card_num); + goto err; + } + + if (pcm_idx >= chip->pcm_devs) { + pr_err("%s: invalid pcm dev number %u > %d\n", __func__, + pcm_idx, chip->pcm_devs); + goto err; + } + + if (direction > SNDRV_PCM_STREAM_CAPTURE) { + pr_err("%s: invalid direction %u\n", __func__, direction); + goto err; + } + + list_for_each_entry(as, &chip->pcm_list, list) { + if (as->pcm_index == pcm_idx) { + subs = &as->substream[direction]; + if (subs->interface < 0 && !subs->data_endpoint && + !subs->sync_endpoint) { + pr_debug("%s: stream disconnected, bail out\n", + __func__); + subs = NULL; + goto err; + } + goto done; + } + } + +done: + chip->card_num = card_num; + chip->disconnect_cb = disconnect_cb; +err: + *uchip = chip; + if (!subs) + pr_debug("%s: substream instance not found\n", __func__); + mutex_unlock(®ister_mutex); + return subs; +} + /* * disconnect streams * called from usb_audio_disconnect() @@ -215,18 +281,45 @@ struct usb_device *dev = chip->dev; struct usb_host_interface *host_iface; struct usb_interface_descriptor *altsd; - void *control_header; + struct usb_interface *usb_iface; int i, protocol; - int rest_bytes; + + usb_iface = usb_ifnum_to_if(dev, ctrlif); + if (!usb_iface) { + snd_printk(KERN_ERR "%d:%u : does not exist\n", + dev->devnum, ctrlif); + return -EINVAL; + } /* find audiocontrol interface */ - host_iface = &usb_ifnum_to_if(dev, ctrlif)->altsetting[0]; - control_header = snd_usb_find_csint_desc(host_iface->extra, - host_iface->extralen, - NULL, UAC_HEADER); + host_iface = &usb_iface->altsetting[0]; + if (!host_iface) { + snd_printk(KERN_ERR "Audio Control interface is not available."); + return -EINVAL; + } + altsd = get_iface_desc(host_iface); protocol = altsd->bInterfaceProtocol; + /* + * UAC 1.0 devices use AC HEADER Desc for linking AS interfaces; + * UAC 2.0 and 3.0 devices use IAD for linking AS interfaces + */ + + switch (protocol) { + default: + dev_warn(&dev->dev, + "unknown interface protocol %#02x, assuming v1\n", + protocol); + /* fall through */ + + case UAC_VERSION_1: { + void *control_header; + struct uac1_ac_header_descriptor *h1; + int rest_bytes; + + control_header = snd_usb_find_csint_desc(host_iface->extra, + host_iface->extralen, NULL, UAC_HEADER); if (!control_header) { dev_err(&dev->dev, "cannot find UAC_HEADER\n"); return -EINVAL; @@ -241,15 +334,7 @@ return -EINVAL; } - switch (protocol) { - default: - dev_warn(&dev->dev, - "unknown interface protocol %#02x, assuming v1\n", - protocol); - /* fall through */ - - case UAC_VERSION_1: { - struct uac1_ac_header_descriptor *h1 = control_header; + h1 = control_header; if (rest_bytes < sizeof(*h1)) { dev_err(&dev->dev, "too short v1 buffer descriptor\n"); @@ -277,10 +362,10 @@ break; } - case UAC_VERSION_2: { + case UAC_VERSION_2: + case UAC_VERSION_3: { struct usb_interface_assoc_descriptor *assoc = - usb_ifnum_to_if(dev, ctrlif)->intf_assoc; - + usb_iface->intf_assoc; if (!assoc) { /* * Firmware writers cannot count to three. So to find @@ -297,7 +382,8 @@ } if (!assoc) { - dev_err(&dev->dev, "Audio class v2 interfaces need an interface association\n"); + dev_err(&dev->dev, "Audio class V%d interfaces need an interface association\n", + protocol); return -EINVAL; } @@ -329,6 +415,7 @@ list_for_each_entry_safe(ep, n, &chip->ep_list, list) snd_usb_endpoint_free(ep); + mutex_destroy(&chip->dev_lock); mutex_destroy(&chip->mutex); kfree(chip); return 0; @@ -384,6 +471,7 @@ } mutex_init(&chip->mutex); + mutex_init(&chip->dev_lock); init_waitqueue_head(&chip->shutdown_wait); chip->index = idx; chip->dev = dev; @@ -495,6 +583,15 @@ struct usb_host_interface *alts; int ifnum; u32 id; + struct usb_interface_assoc_descriptor *assoc; + + assoc = intf->intf_assoc; + if (assoc && assoc->bFunctionClass == USB_CLASS_AUDIO && + assoc->bFunctionProtocol == UAC_VERSION_3 && + assoc->bFunctionSubClass == FULL_ADC_PROFILE) { + dev_info(&dev->dev, "No support for full-fledged ADC 3.0 yet!!\n"); + return -EINVAL; + } alts = &intf->altsetting[0]; ifnum = get_iface_desc(alts)->bInterfaceNumber; @@ -583,6 +680,8 @@ usb_chip[chip->index] = chip; chip->num_interfaces++; usb_set_intfdata(intf, chip); + intf->needs_remote_wakeup = 1; + usb_enable_autosuspend(chip->dev); atomic_dec(&chip->active); mutex_unlock(®ister_mutex); return 0; @@ -612,6 +711,9 @@ card = chip->card; + if (chip->disconnect_cb) + chip->disconnect_cb(chip); + mutex_lock(®ister_mutex); if (atomic_inc_return(&chip->shutdown) == 1) { struct snd_usb_stream *as; diff -ruw linux-4.4.115/sound/usb/card.h linux-4.4.115-fbx/sound/usb/card.h --- linux-4.4.115/sound/usb/card.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/sound/usb/card.h 2019-01-22 16:16:29.695302479 +0100 @@ -167,4 +167,8 @@ struct list_head list; }; +struct snd_usb_substream *find_snd_usb_substream(unsigned int card_num, + unsigned int pcm_idx, unsigned int direction, struct snd_usb_audio + **uchip, void (*disconnect_cb)(struct snd_usb_audio *chip)); + #endif /* __USBAUDIO_CARD_H */ diff -ruw linux-4.4.115/sound/usb/clock.c linux-4.4.115-fbx/sound/usb/clock.c --- linux-4.4.115/sound/usb/clock.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/sound/usb/clock.c 2019-01-22 16:16:29.695302479 +0100 @@ -427,6 +427,10 @@ case UAC_VERSION_2: return set_sample_rate_v2(chip, iface, alts, fmt, rate); + + /* Clock rate is fixed at 48 kHz for BADD devices */ + case UAC_VERSION_3: + return 0; } } diff -ruw linux-4.4.115/sound/usb/endpoint.c linux-4.4.115-fbx/sound/usb/endpoint.c --- linux-4.4.115/sound/usb/endpoint.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/sound/usb/endpoint.c 2019-01-22 16:16:29.695302479 +0100 @@ -357,7 +357,7 @@ err = usb_submit_urb(ctx->urb, GFP_ATOMIC); if (err < 0) usb_audio_err(ep->chip, - "Unable to submit urb #%d: %d (urb %p)\n", + "Unable to submit urb #%d: %d (urb %pK)\n", ctx->index, err, ctx->urb); else set_bit(ctx->index, &ep->active_mask); @@ -462,7 +462,7 @@ ep->iface == alts->desc.bInterfaceNumber && ep->altsetting == alts->desc.bAlternateSetting) { usb_audio_dbg(ep->chip, - "Re-using EP %x in iface %d,%d @%p\n", + "Re-using EP %x in iface %d,%d @%pK\n", ep_num, ep->iface, ep->altsetting, ep); goto __exit_unlock; } diff -ruw linux-4.4.115/sound/usb/format.c linux-4.4.115-fbx/sound/usb/format.c --- linux-4.4.115/sound/usb/format.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/sound/usb/format.c 2019-01-22 16:16:29.695302479 +0100 @@ -20,6 +20,7 @@ #include #include #include +#include #include #include @@ -69,6 +70,35 @@ format <<= 1; break; } + + case UAC_VERSION_3: { + switch (fp->maxpacksize) { + case BADD_MAXPSIZE_SYNC_MONO_16: + case BADD_MAXPSIZE_SYNC_STEREO_16: + case BADD_MAXPSIZE_ASYNC_MONO_16: + case BADD_MAXPSIZE_ASYNC_STEREO_16: { + sample_width = BIT_RES_16_BIT; + sample_bytes = SUBSLOTSIZE_16_BIT; + break; + } + + case BADD_MAXPSIZE_SYNC_MONO_24: + case BADD_MAXPSIZE_SYNC_STEREO_24: + case BADD_MAXPSIZE_ASYNC_MONO_24: + case BADD_MAXPSIZE_ASYNC_STEREO_24: { + sample_width = BIT_RES_24_BIT; + sample_bytes = SUBSLOTSIZE_24_BIT; + break; + } + + default: + usb_audio_err(chip, "%u:%d : Invalid wMaxPacketSize\n", + fp->iface, fp->altsetting); + return pcm_formats; + } + format = 1 << format; + break; + } } if ((pcm_formats == 0) && @@ -366,6 +396,22 @@ return ret; } +static int badd_set_audio_rate_v3(struct snd_usb_audio *chip, + struct audioformat *fp) +{ + unsigned int rate; + + fp->rate_table = kmalloc(sizeof(int), GFP_KERNEL); + if (fp->rate_table == NULL) + return -ENOMEM; + + fp->nr_rates = 1; + rate = BADD_SAMPLING_RATE; + fp->rate_min = fp->rate_max = fp->rate_table[0] = rate; + fp->rates |= snd_pcm_rate_to_rate_bit(rate); + return 0; +} + /* * parse the format type I and III descriptors */ @@ -415,6 +461,9 @@ /* fp->channels is already set in this case */ ret = parse_audio_format_rates_v2(chip, fp); break; + case UAC_VERSION_3: + ret = badd_set_audio_rate_v3(chip, fp); + break; } if (fp->channels < 1) { @@ -502,6 +551,9 @@ fmt->bFormatType); return -ENOTSUPP; } + if (fp->protocol == UAC_VERSION_3) + fp->fmt_type = UAC_FORMAT_TYPE_I; + else fp->fmt_type = fmt->bFormatType; if (err < 0) return err; diff -ruw linux-4.4.115/sound/usb/Kconfig linux-4.4.115-fbx/sound/usb/Kconfig --- linux-4.4.115/sound/usb/Kconfig 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/sound/usb/Kconfig 2019-01-22 16:16:29.691302442 +0100 @@ -162,5 +162,13 @@ source "sound/usb/line6/Kconfig" +config SND_USB_AUDIO_QMI + tristate "USB Audio QMI Service driver" + depends on MSM_QMI_INTERFACE + help + Starts USB Audio QMI server to communicate with remote entity + to perform operations like enable or disable particular audio + stream on a connected USB device. + endif # SND_USB diff -ruw linux-4.4.115/sound/usb/Makefile linux-4.4.115-fbx/sound/usb/Makefile --- linux-4.4.115/sound/usb/Makefile 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/sound/usb/Makefile 2019-01-22 16:16:29.691302442 +0100 @@ -13,7 +13,8 @@ pcm.o \ proc.o \ quirks.o \ - stream.o + stream.o \ + badd.o snd-usbmidi-lib-objs := midi.o @@ -26,3 +27,4 @@ obj-$(CONFIG_SND) += misc/ usx2y/ caiaq/ 6fire/ hiface/ bcd2000/ obj-$(CONFIG_SND_USB_LINE6) += line6/ +obj-$(CONFIG_SND_USB_AUDIO_QMI) += usb_audio_qmi_v01.o usb_audio_qmi_svc.o diff -ruw linux-4.4.115/sound/usb/mixer.c linux-4.4.115-fbx/sound/usb/mixer.c --- linux-4.4.115/sound/usb/mixer.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/sound/usb/mixer.c 2019-10-29 09:26:26.193228133 +0100 @@ -50,6 +50,7 @@ #include #include #include +#include #include #include @@ -184,6 +185,17 @@ /* we just parse the header */ struct uac_feature_unit_descriptor *hdr = NULL; + if (state->mixer->protocol == UAC_VERSION_3) { + int i; + + for (i = 0; i < NUM_BADD_DESCS; i++) { + hdr = (void *)badd_desc_list[i]; + if (hdr->bUnitID == unit) + return hdr; + } + + return NULL; + } while ((hdr = snd_usb_find_desc(state->buffer, state->buflen, hdr, USB_DT_CS_INTERFACE)) != NULL) { if (hdr->bLength >= 4 && @@ -203,11 +215,6 @@ int index, char *buf, int maxlen) { int len = usb_string(state->chip->dev, index, buf, maxlen - 1); - - if (len < 0) - return 0; - - buf[len] = 0; return len; } @@ -723,7 +730,7 @@ term->channels = d->bNrChannels; term->chconfig = le16_to_cpu(d->wChannelConfig); term->name = d->iTerminal; - } else { /* UAC_VERSION_2 */ + } else if (state->mixer->protocol == UAC_VERSION_2) { struct uac2_input_terminal_descriptor *d = p1; /* call recursively to verify that the @@ -740,6 +747,24 @@ term->channels = d->bNrChannels; term->chconfig = le32_to_cpu(d->bmChannelConfig); term->name = d->iTerminal; + } else { /* UAC_VERSION_3 */ + struct uac3_input_terminal_descriptor *d = p1; + + err = check_input_term(state, + d->bCSourceID, term); + if (err < 0) + return err; + + term->id = id; + term->type = d->wTerminalType; + if (d->wClusterDescrID == CLUSTER_ID_MONO) { + term->channels = NUM_CHANNELS_MONO; + term->chconfig = BADD_CH_CONFIG_MONO; + } else { + term->channels = NUM_CHANNELS_STEREO; + term->chconfig = BADD_CH_CONFIG_STEREO; + } + term->name = d->wTerminalDescrStr; } return 0; case UAC_FEATURE_UNIT: { @@ -757,28 +782,61 @@ return 0; } case UAC_SELECTOR_UNIT: - case UAC2_CLOCK_SELECTOR: { + /* UAC3_MIXER_UNIT_V3 */ + case UAC2_CLOCK_SELECTOR: + /* UAC3_CLOCK_SOURCE */ { + if (state->mixer->protocol == UAC_VERSION_3 + && hdr[2] == UAC3_CLOCK_SOURCE) { + struct uac3_clock_source_descriptor *d = p1; + + term->type = d->bDescriptorSubtype << 16; + term->id = id; + term->name = d->wClockSourceStr; + } else if (state->mixer->protocol == UAC_VERSION_3 + && hdr[2] == UAC3_MIXER_UNIT_V3) { + struct uac3_mixer_unit_descriptor *d = p1; + + term->type = d->bDescriptorSubtype << 16; + if (d->wClusterDescrID == CLUSTER_ID_MONO) { + term->channels = NUM_CHANNELS_MONO; + term->chconfig = BADD_CH_CONFIG_MONO; + } else { + term->channels = NUM_CHANNELS_STEREO; + term->chconfig = BADD_CH_CONFIG_STEREO; + } + term->name = d->wMixerDescrStr; + } else { struct uac_selector_unit_descriptor *d = p1; - /* call recursively to retrieve the channel info */ - err = check_input_term(state, d->baSourceID[0], term); + /* call recursively to retrieve channel info */ + err = check_input_term(state, + d->baSourceID[0], term); if (err < 0) return err; - term->type = d->bDescriptorSubtype << 16; /* virtual type */ + /* virtual type */ + term->type = d->bDescriptorSubtype << 16; term->id = id; term->name = uac_selector_unit_iSelector(d); + } return 0; } case UAC1_PROCESSING_UNIT: case UAC1_EXTENSION_UNIT: /* UAC2_PROCESSING_UNIT_V2 */ /* UAC2_EFFECT_UNIT */ + /* UAC3_FEATURE_UNIT_V3 */ case UAC2_EXTENSION_UNIT_V2: { + if (state->mixer->protocol == UAC_VERSION_3) { + struct uac_feature_unit_descriptor *d = p1; + + id = d->bSourceID; + } else { struct uac_processing_unit_descriptor *d = p1; if (state->mixer->protocol == UAC_VERSION_2 && hdr[2] == UAC2_EFFECT_UNIT) { /* UAC2/UAC1 unit IDs overlap here in an - * uncompatible way. Ignore this unit for now. + * uncompatible way. Ignore this unit + * for now. */ return 0; } @@ -787,12 +845,19 @@ id = d->baSourceID[0]; break; /* continue to parse */ } - term->type = d->bDescriptorSubtype << 16; /* virtual type */ - term->channels = uac_processing_unit_bNrChannels(d); - term->chconfig = uac_processing_unit_wChannelConfig(d, state->mixer->protocol); - term->name = uac_processing_unit_iProcessing(d, state->mixer->protocol); + /* virtual type */ + term->type = d->bDescriptorSubtype << 16; + term->channels = + uac_processing_unit_bNrChannels(d); + term->chconfig = + uac_processing_unit_wChannelConfig( + d, state->mixer->protocol); + term->name = uac_processing_unit_iProcessing( + d, state->mixer->protocol); return 0; } + break; + } case UAC2_CLOCK_SOURCE: { struct uac_clock_source_descriptor *d = p1; term->type = d->bDescriptorSubtype << 16; /* virtual type */ @@ -948,6 +1013,17 @@ cval->res = 384; } break; + + case USB_ID(0x1130, 0x1620): /* Logitech Speakers S150 */ + /* This audio device has 2 channels and it explicitly requires the + * host to send SET_CUR command on the volume control of both the + * channels. 7936 = 0x1F00 is the default value. + */ + if (cval->channels == 2) + snd_usb_mixer_set_ctl_value(cval, UAC_SET_CUR, + (cval->control << 8) | 2, 7936); + break; + } } @@ -1043,8 +1119,10 @@ /* USB descriptions contain the dB scale in 1/256 dB unit * while ALSA TLV contains in 1/100 dB unit */ - cval->dBmin = (convert_signed_value(cval, cval->min) * 100) / 256; - cval->dBmax = (convert_signed_value(cval, cval->max) * 100) / 256; + cval->dBmin = + (convert_signed_value(cval, cval->min) * 100) / (cval->res); + cval->dBmax = + (convert_signed_value(cval, cval->max) * 100) / (cval->res); if (cval->dBmin > cval->dBmax) { /* something is wrong; assume it's either from/to 0dB */ if (cval->dBmin < 0) @@ -1236,12 +1314,18 @@ struct usb_feature_control_info *ctl_info; unsigned int len = 0; int mapped_name = 0; - int nameid = uac_feature_unit_iFeature(desc); + int nameid; struct snd_kcontrol *kctl; struct usb_mixer_elem_info *cval; const struct usbmix_name_map *map; unsigned int range; + if (state->mixer->protocol == UAC_VERSION_3) + nameid = ((struct uac3_feature_unit_descriptor *) + raw_desc)->wFeatureDescrStr; + else + nameid = uac_feature_unit_iFeature(desc); + control++; /* change from zero-based to 1-based value */ if (control == UAC_FU_GRAPHIC_EQUALIZER) { @@ -1262,7 +1346,7 @@ ctl_info = &audio_feature_info[control-1]; if (state->mixer->protocol == UAC_VERSION_1) cval->val_type = ctl_info->type; - else /* UAC_VERSION_2 */ + else /* UAC_VERSION_2 or UAC_VERSION_3*/ cval->val_type = ctl_info->type_uac2 >= 0 ? ctl_info->type_uac2 : ctl_info->type; @@ -1385,6 +1469,62 @@ snd_usb_mixer_add_control(&cval->head, kctl); } +static int find_num_channels(struct mixer_build *state, int dir) +{ + int num_ch = -EINVAL, num, i, j, wMaxPacketSize; + int ctrlif = get_iface_desc(state->mixer->hostif)->bInterfaceNumber; + struct usb_interface *usb_iface = + usb_ifnum_to_if(state->mixer->chip->dev, ctrlif); + struct usb_interface_assoc_descriptor *assoc = usb_iface->intf_assoc; + struct usb_host_interface *alts; + + for (i = 0; i < assoc->bInterfaceCount; i++) { + int intf = assoc->bFirstInterface + i; + + if (intf != ctrlif) { + struct usb_interface *iface = + usb_ifnum_to_if(state->mixer->chip->dev, intf); + + alts = &iface->altsetting[1]; + if (dir == USB_DIR_OUT && + get_endpoint(alts, 0)->bEndpointAddress & + USB_DIR_IN) + continue; + if (dir == USB_DIR_IN && + !(get_endpoint(alts, 0)->bEndpointAddress & + USB_DIR_IN)) + continue; + num = iface->num_altsetting; + for (j = 1; j < num; j++) { + num_ch = NUM_CHANNELS_MONO; + alts = &iface->altsetting[j]; + wMaxPacketSize = le16_to_cpu( + get_endpoint(alts, 0)-> + wMaxPacketSize); + switch (wMaxPacketSize) { + case BADD_MAXPSIZE_SYNC_MONO_16: + case BADD_MAXPSIZE_SYNC_MONO_24: + case BADD_MAXPSIZE_ASYNC_MONO_16: + case BADD_MAXPSIZE_ASYNC_MONO_24: + break; + case BADD_MAXPSIZE_SYNC_STEREO_16: + case BADD_MAXPSIZE_SYNC_STEREO_24: + case BADD_MAXPSIZE_ASYNC_STEREO_16: + case BADD_MAXPSIZE_ASYNC_STEREO_24: + num_ch = NUM_CHANNELS_STEREO; + break; + } + if (num_ch == NUM_CHANNELS_MONO) + continue; + else + break; + } + } + } + + return num_ch; +} + /* * parse a feature unit * @@ -1422,7 +1562,7 @@ unitid); return -EINVAL; } - } else { + } else if (state->mixer->protocol == UAC_VERSION_2) { struct uac2_feature_unit_descriptor *ftr = _ftr; if (hdr->bLength < 6) { usb_audio_err(state->chip, @@ -1439,11 +1579,118 @@ unitid); return -EINVAL; } + } else { + struct usb_interface *usb_iface = + usb_ifnum_to_if(state->mixer->chip->dev, + get_iface_desc(state->mixer->hostif)->bInterfaceNumber); + struct usb_interface_assoc_descriptor *assoc = + usb_iface->intf_assoc; + + csize = 4; + switch (unitid) { + case BADD_FU_ID_BAIOF: + channels = NUM_CHANNELS_MONO; + bmaControls = monoControls; + badd_baif_in_term_desc.wClusterDescrID = + CLUSTER_ID_MONO; + break; + + case BADD_FU_ID_BAOF: + switch (assoc->bFunctionSubClass) { + case PROF_HEADPHONE: + case PROF_HEADSET_ADAPTER: + channels = NUM_CHANNELS_STEREO; + bmaControls = stereoControls; + badd_baiof_mu_desc.wClusterDescrID = + CLUSTER_ID_MONO; + break; + case PROF_SPEAKERPHONE: + channels = NUM_CHANNELS_MONO; + bmaControls = monoControls; + badd_baof_in_term_desc.wClusterDescrID = + CLUSTER_ID_MONO; + break; + default: + channels = find_num_channels(state, + USB_DIR_OUT); + if (channels < 0) { + usb_audio_err(state->chip, + "unit %u: Cant find num of channels\n", + unitid); + return channels; + } + + bmaControls = (channels == NUM_CHANNELS_MONO) ? + monoControls : stereoControls; + badd_baof_in_term_desc.wClusterDescrID = + (channels == NUM_CHANNELS_MONO) ? + CLUSTER_ID_MONO : CLUSTER_ID_STEREO; + break; + } + break; + + case BADD_FU_ID_BAIF: + switch (assoc->bFunctionSubClass) { + case PROF_HEADSET: + case PROF_HEADSET_ADAPTER: + case PROF_SPEAKERPHONE: + channels = NUM_CHANNELS_MONO; + bmaControls = monoControls; + badd_baif_in_term_desc.wClusterDescrID = + CLUSTER_ID_MONO; + break; + default: + channels = find_num_channels(state, USB_DIR_IN); + if (channels < 0) { + usb_audio_err(state->chip, + "unit %u: Cant find num of channels\n", + unitid); + return channels; + } + + bmaControls = (channels == NUM_CHANNELS_MONO) ? + monoControls : stereoControls; + badd_baif_in_term_desc.wClusterDescrID = + (channels == NUM_CHANNELS_MONO) ? + CLUSTER_ID_MONO : CLUSTER_ID_STEREO; + break; + } + break; + + default: + usb_audio_err(state->chip, "Invalid unit %u\n", unitid); + return -EINVAL; + } } /* parse the source unit */ - if ((err = parse_audio_unit(state, hdr->bSourceID)) < 0) + if (state->mixer->protocol != UAC_VERSION_3) { + err = parse_audio_unit(state, hdr->bSourceID); + if (err < 0) + return err; + } else { + struct usb_interface *usb_iface = + usb_ifnum_to_if(state->mixer->chip->dev, + get_iface_desc(state->mixer->hostif)->bInterfaceNumber); + struct usb_interface_assoc_descriptor *assoc = + usb_iface->intf_assoc; + + switch (unitid) { + case BADD_FU_ID_BAOF: + switch (assoc->bFunctionSubClass) { + case PROF_HEADSET: + case PROF_HEADSET_ADAPTER: + hdr->bSourceID = BADD_MU_ID_BAIOF; + break; + default: + hdr->bSourceID = BADD_IN_TERM_ID_BAOF; + break; + } + } + err = parse_audio_unit(state, hdr->bSourceID); + if (err < 0) return err; + } /* determine the input source type and name */ err = check_input_term(state, hdr->bSourceID, &iterm); @@ -1497,7 +1744,7 @@ build_feature_ctl(state, _ftr, 0, i, &iterm, unitid, 0); } - } else { /* UAC_VERSION_2 */ + } else { /* UAC_VERSION_2 or UAC_VERSION_3*/ for (i = 0; i < ARRAY_SIZE(audio_feature_info); i++) { unsigned int ch_bits = 0; unsigned int ch_read_only = 0; @@ -1615,6 +1862,12 @@ int input_pins, num_ins, num_outs; int pin, ich, err; + if (state->mixer->protocol == UAC_VERSION_3) { + input_pins = badd_baiof_mu_desc.bNrInPins; + num_outs = + (badd_baiof_mu_desc.wClusterDescrID == CLUSTER_ID_MONO) ? + NUM_CHANNELS_MONO : NUM_CHANNELS_STEREO; + } else { if (desc->bLength < 11 || !(input_pins = desc->bNrInPins) || !(num_outs = uac_mixer_unit_bNrChannels(desc))) { usb_audio_err(state->chip, @@ -1622,6 +1875,7 @@ unitid); return -EINVAL; } + } num_ins = 0; ich = 0; @@ -1640,9 +1894,14 @@ int och, ich_has_controls = 0; for (och = 0; och < num_outs; och++) { - __u8 *c = uac_mixer_unit_bmControls(desc, - state->mixer->protocol); + __u8 *c = NULL; + if (state->mixer->protocol == UAC_VERSION_3) + c = + &(badd_baiof_mu_desc.bmMixerControls); + else + c = uac_mixer_unit_bmControls(desc, + state->mixer->protocol); if (check_matrix_bitmap(c, ich, och, num_outs)) { ich_has_controls = 1; break; @@ -2157,16 +2416,28 @@ case UAC_MIXER_UNIT: return parse_audio_mixer_unit(state, unitid, p1); case UAC_SELECTOR_UNIT: + /* UAC3_MIXER_UNIT_V3 has the same value */ case UAC2_CLOCK_SELECTOR: + /* UAC3_CLOCK_SOURCE has the same value */ + if (state->mixer->protocol == UAC_VERSION_3 && + p1[2] == UAC3_CLOCK_SOURCE) + return 0; /* NOP */ + else if (state->mixer->protocol == UAC_VERSION_3 + && p1[2] == UAC3_MIXER_UNIT_V3) + return parse_audio_mixer_unit(state, unitid, p1); + else return parse_audio_selector_unit(state, unitid, p1); case UAC_FEATURE_UNIT: return parse_audio_feature_unit(state, unitid, p1); case UAC1_PROCESSING_UNIT: /* UAC2_EFFECT_UNIT has the same value */ + /* UAC3_FEATURE_UNIT_V3 has the same value */ if (state->mixer->protocol == UAC_VERSION_1) return parse_audio_processing_unit(state, unitid, p1); - else + else if (state->mixer->protocol == UAC_VERSION_2) return 0; /* FIXME - effect units not implemented yet */ + else + return parse_audio_feature_unit(state, unitid, p1); case UAC1_EXTENSION_UNIT: /* UAC2_PROCESSING_UNIT_V2 has the same value */ if (state->mixer->protocol == UAC_VERSION_1) @@ -2204,6 +2475,23 @@ return 0; } +static int make_out_term(struct mixer_build state, int wTerminalType) +{ + struct uac3_output_terminal_descriptor *desc = NULL; + + if (wTerminalType == UAC_TERMINAL_STREAMING) + desc = &badd_baif_out_term_desc; + else { + desc = &badd_baof_out_term_desc; + desc->wTerminalType = wTerminalType; + } + set_bit(desc->bTerminalID, state.unitbitmap); + state.oterm.id = desc->bTerminalID; + state.oterm.type = desc->wTerminalType; + state.oterm.name = desc->wTerminalDescrStr; + return parse_audio_unit(&state, desc->bSourceID); +} + /* * create mixer controls * @@ -2212,9 +2500,8 @@ static int snd_usb_mixer_controls(struct usb_mixer_interface *mixer) { struct mixer_build state; - int err; + int err = -EINVAL; const struct usbmix_ctl_map *map; - void *p; memset(&state, 0, sizeof(state)); state.chip = mixer->chip; @@ -2232,46 +2519,110 @@ } } + if (mixer->protocol == UAC_VERSION_3) { + struct usb_interface *usb_iface = + usb_ifnum_to_if(mixer->chip->dev, + get_iface_desc(mixer->hostif)->bInterfaceNumber); + struct usb_interface_assoc_descriptor *assoc = + usb_iface->intf_assoc; + + switch (assoc->bFunctionSubClass) { + case PROF_GENERIC_IO: { + if (assoc->bInterfaceCount == 0x02) { + if (get_endpoint(mixer->hostif, + 0)->bEndpointAddress | USB_DIR_IN) + err = make_out_term(state, + UAC_TERMINAL_STREAMING); + else + err = make_out_term(state, + UAC_OUTPUT_TERMINAL_UNDEFINED); + } else { + err = make_out_term(state, + UAC_OUTPUT_TERMINAL_UNDEFINED); + if (err < 0 && err != -EINVAL) + return err; + err = make_out_term(state, + UAC_TERMINAL_STREAMING); + } + break; + } + + case PROF_HEADPHONE: + err = make_out_term(state, + UAC_OUTPUT_TERMINAL_HEADPHONES); + break; + case PROF_SPEAKER: + err = make_out_term(state, UAC_OUTPUT_TERMINAL_SPEAKER); + break; + case PROF_MICROPHONE: + err = make_out_term(state, UAC_TERMINAL_STREAMING); + break; + case PROF_HEADSET: + case PROF_HEADSET_ADAPTER: + err = make_out_term(state, UAC_BIDIR_TERMINAL_HEADSET); + if (err < 0 && err != -EINVAL) + return err; + err = make_out_term(state, UAC_TERMINAL_STREAMING); + break; + case PROF_SPEAKERPHONE: + err = make_out_term(state, + UAC_BIDIR_TERMINAL_SPEAKERPHONE); + if (err < 0 && err != -EINVAL) + return err; + err = make_out_term(state, UAC_TERMINAL_STREAMING); + break; + } + if (err < 0 && err != -EINVAL) + return err; + } else { + void *p; + p = NULL; while ((p = snd_usb_find_csint_desc(mixer->hostif->extra, - mixer->hostif->extralen, - p, UAC_OUTPUT_TERMINAL)) != NULL) { + mixer->hostif->extralen, p, + UAC_OUTPUT_TERMINAL)) != NULL) { if (mixer->protocol == UAC_VERSION_1) { - struct uac1_output_terminal_descriptor *desc = p; + struct uac1_output_terminal_descriptor *desc = + p; if (desc->bLength < sizeof(*desc)) continue; /* invalid descriptor? */ /* mark terminal ID as visited */ set_bit(desc->bTerminalID, state.unitbitmap); state.oterm.id = desc->bTerminalID; - state.oterm.type = le16_to_cpu(desc->wTerminalType); + state.oterm.type = + le16_to_cpu(desc->wTerminalType); state.oterm.name = desc->iTerminal; err = parse_audio_unit(&state, desc->bSourceID); if (err < 0 && err != -EINVAL) return err; } else { /* UAC_VERSION_2 */ - struct uac2_output_terminal_descriptor *desc = p; + struct uac2_output_terminal_descriptor *desc = + p; if (desc->bLength < sizeof(*desc)) continue; /* invalid descriptor? */ /* mark terminal ID as visited */ set_bit(desc->bTerminalID, state.unitbitmap); state.oterm.id = desc->bTerminalID; - state.oterm.type = le16_to_cpu(desc->wTerminalType); + state.oterm.type = + le16_to_cpu(desc->wTerminalType); state.oterm.name = desc->iTerminal; err = parse_audio_unit(&state, desc->bSourceID); if (err < 0 && err != -EINVAL) return err; /* - * For UAC2, use the same approach to also add the - * clock selectors + * For UAC2, use the same approach to also add + * the clock selectors */ - err = parse_audio_unit(&state, desc->bCSourceID); + err = parse_audio_unit(&state, + desc->bCSourceID); if (err < 0 && err != -EINVAL) return err; } } + } return 0; } @@ -2504,6 +2855,9 @@ case UAC_VERSION_2: mixer->protocol = UAC_VERSION_2; break; + case UAC_VERSION_3: + mixer->protocol = UAC_VERSION_3; + break; } if ((err = snd_usb_mixer_controls(mixer)) < 0 || diff -ruw linux-4.4.115/sound/usb/pcm.c linux-4.4.115-fbx/sound/usb/pcm.c --- linux-4.4.115/sound/usb/pcm.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/sound/usb/pcm.c 2019-10-29 09:26:26.193228133 +0100 @@ -228,7 +228,7 @@ if (!test_and_set_bit(SUBSTREAM_FLAG_DATA_EP_STARTED, &subs->flags)) { struct snd_usb_endpoint *ep = subs->data_endpoint; - dev_dbg(&subs->dev->dev, "Starting data EP @%p\n", ep); + dev_dbg(&subs->dev->dev, "Starting data EP @%pK\n", ep); ep->data_subs = subs; err = snd_usb_endpoint_start(ep); @@ -257,7 +257,7 @@ } } - dev_dbg(&subs->dev->dev, "Starting sync EP @%p\n", ep); + dev_dbg(&subs->dev->dev, "Starting sync EP @%pK\n", ep); ep->sync_slave = subs->data_endpoint; err = snd_usb_endpoint_start(ep); @@ -554,6 +554,64 @@ return 0; } +int snd_usb_enable_audio_stream(struct snd_usb_substream *subs, + bool enable) +{ + struct audioformat *fmt; + struct usb_host_interface *alts; + struct usb_interface *iface; + int ret; + + if (!enable) { + if (subs->interface >= 0) { + usb_set_interface(subs->dev, subs->interface, 0); + subs->altset_idx = 0; + subs->interface = -1; + subs->cur_audiofmt = NULL; + } + + snd_usb_autosuspend(subs->stream->chip); + return 0; + } + + snd_usb_autoresume(subs->stream->chip); + fmt = find_format(subs); + if (!fmt) { + dev_err(&subs->dev->dev, + "cannot set format: format = %#x, rate = %d, channels = %d\n", + subs->pcm_format, subs->cur_rate, subs->channels); + return -EINVAL; + } + + subs->altset_idx = 0; + subs->interface = -1; + if (atomic_read(&subs->stream->chip->shutdown)) { + ret = -ENODEV; + } else { + ret = set_format(subs, fmt); + if (ret < 0) + return ret; + + iface = usb_ifnum_to_if(subs->dev, subs->cur_audiofmt->iface); + alts = &iface->altsetting[subs->cur_audiofmt->altset_idx]; + ret = snd_usb_init_sample_rate(subs->stream->chip, + subs->cur_audiofmt->iface, + alts, + subs->cur_audiofmt, + subs->cur_rate); + if (ret < 0) { + dev_err(&subs->dev->dev, "failed to set rate %d\n", + subs->cur_rate); + return ret; + } + } + + subs->interface = fmt->iface; + subs->altset_idx = fmt->altset_idx; + + return 0; +} + /* * Return the score of matching two audioformats. * Veto the audioformat if: @@ -571,13 +629,13 @@ if (fp->channels < 1) { dev_dbg(&subs->dev->dev, - "%s: (fmt @%p) no channels\n", __func__, fp); + "%s: (fmt @%pK) no channels\n", __func__, fp); return 0; } if (!(fp->formats & pcm_format_to_bits(pcm_format))) { dev_dbg(&subs->dev->dev, - "%s: (fmt @%p) no match for format %d\n", __func__, + "%s: (fmt @%pK) no match for format %d\n", __func__, fp, pcm_format); return 0; } @@ -590,7 +648,7 @@ } if (!score) { dev_dbg(&subs->dev->dev, - "%s: (fmt @%p) no match for rate %d\n", __func__, + "%s: (fmt @%pK) no match for rate %d\n", __func__, fp, rate); return 0; } @@ -599,7 +657,7 @@ score++; dev_dbg(&subs->dev->dev, - "%s: (fmt @%p) score %d\n", __func__, fp, score); + "%s: (fmt @%pK) score %d\n", __func__, fp, score); return score; } diff -ruw linux-4.4.115/sound/usb/pcm.h linux-4.4.115-fbx/sound/usb/pcm.h --- linux-4.4.115/sound/usb/pcm.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/sound/usb/pcm.h 2019-01-22 16:16:29.699302515 +0100 @@ -9,6 +9,7 @@ int snd_usb_init_pitch(struct snd_usb_audio *chip, int iface, struct usb_host_interface *alts, struct audioformat *fmt); - +int snd_usb_enable_audio_stream(struct snd_usb_substream *subs, + bool enable); #endif /* __USBAUDIO_PCM_H */ diff -ruw linux-4.4.115/sound/usb/stream.c linux-4.4.115-fbx/sound/usb/stream.c --- linux-4.4.115/sound/usb/stream.c 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/sound/usb/stream.c 2019-01-22 16:16:29.703302551 +0100 @@ -20,6 +20,7 @@ #include #include #include +#include #include #include @@ -69,9 +70,14 @@ static void snd_usb_audio_pcm_free(struct snd_pcm *pcm) { struct snd_usb_stream *stream = pcm->private_data; + struct snd_usb_audio *chip; + if (stream) { + mutex_lock(&stream->chip->dev_lock); + chip = stream->chip; stream->pcm = NULL; snd_usb_audio_stream_free(stream); + mutex_unlock(&chip->dev_lock); } } @@ -279,8 +285,6 @@ 0 /* terminator */ }; struct snd_pcm_chmap_elem *chmap; - const unsigned int *maps; - int c; if (channels > ARRAY_SIZE(chmap->map)) return NULL; @@ -289,26 +293,41 @@ if (!chmap) return NULL; - maps = protocol == UAC_VERSION_2 ? uac2_maps : uac1_maps; chmap->channels = channels; - c = 0; + + if (protocol == UAC_VERSION_3) { + switch (channels) { + case 1: + chmap->map[0] = SNDRV_CHMAP_MONO; + break; + case 2: + chmap->map[0] = SNDRV_CHMAP_FL; + chmap->map[1] = SNDRV_CHMAP_FR; + break; + } + } else { + int c = 0; + const unsigned int *maps = + protocol == UAC_VERSION_2 ? uac2_maps : uac1_maps; if (bits) { for (; bits && *maps; maps++, bits >>= 1) if (bits & 1) chmap->map[c++] = *maps; } else { - /* If we're missing wChannelConfig, then guess something - to make sure the channel map is not skipped entirely */ + /* + * If we're missing wChannelConfig, then guess something + * to make sure the channel map is not skipped entirely + */ if (channels == 1) chmap->map[c++] = SNDRV_CHMAP_MONO; else for (; c < channels && *maps; maps++) chmap->map[c++] = *maps; } - for (; c < channels; c++) chmap->map[c] = SNDRV_CHMAP_UNKNOWN; + } return chmap; } @@ -406,6 +425,9 @@ struct usb_interface_descriptor *altsd = get_iface_desc(alts); int attributes = 0; + if (protocol == UAC_VERSION_3) + return 0; + csep = snd_usb_find_desc(alts->endpoint[0].extra, alts->endpoint[0].extralen, NULL, USB_DT_CS_ENDPOINT); /* Creamware Noah has this descriptor after the 2nd endpoint */ @@ -626,6 +648,50 @@ iface_no, altno, as->bTerminalLink); continue; } + + case UAC_VERSION_3: { + int wMaxPacketSize; + + /* + * Allocate a dummy instance of fmt and set format type + * to UAC_FORMAT_TYPE_I for BADD support; free fmt + * after its last usage + */ + fmt = kzalloc(sizeof(*fmt), GFP_KERNEL); + if (!fmt) + return -ENOMEM; + + fmt->bFormatType = UAC_FORMAT_TYPE_I; + format = UAC_FORMAT_TYPE_I_PCM; + clock = BADD_CLOCK_SOURCE; + wMaxPacketSize = le16_to_cpu(get_endpoint(alts, 0) + ->wMaxPacketSize); + switch (wMaxPacketSize) { + case BADD_MAXPSIZE_SYNC_MONO_16: + case BADD_MAXPSIZE_SYNC_MONO_24: + case BADD_MAXPSIZE_ASYNC_MONO_16: + case BADD_MAXPSIZE_ASYNC_MONO_24: { + num_channels = NUM_CHANNELS_MONO; + chconfig = BADD_CH_CONFIG_MONO; + goto populate_fp; + } + + case BADD_MAXPSIZE_SYNC_STEREO_16: + case BADD_MAXPSIZE_SYNC_STEREO_24: + case BADD_MAXPSIZE_ASYNC_STEREO_16: + case BADD_MAXPSIZE_ASYNC_STEREO_24: { + num_channels = NUM_CHANNELS_STEREO; + chconfig = BADD_CH_CONFIG_STEREO; + goto populate_fp; + } + default: + dev_err(&dev->dev, + "%u:%d: invalid wMaxPacketSize\n", + iface_no, altno); + kfree(fmt); + continue; + } + } } /* get format type */ @@ -659,6 +725,7 @@ fp->maxpacksize * 2) continue; +populate_fp: fp = kzalloc(sizeof(*fp), GFP_KERNEL); if (! fp) { dev_err(&dev->dev, "cannot malloc\n"); @@ -720,6 +787,8 @@ continue; } + if (protocol == UAC_VERSION_3) + kfree(fmt); /* Create chmap */ if (fp->channels != num_channels) chconfig = 0; diff -ruw linux-4.4.115/sound/usb/usbaudio.h linux-4.4.115-fbx/sound/usb/usbaudio.h --- linux-4.4.115/sound/usb/usbaudio.h 2018-02-03 17:04:31.000000000 +0100 +++ linux-4.4.115-fbx/sound/usb/usbaudio.h 2019-01-22 16:16:29.703302551 +0100 @@ -60,6 +60,10 @@ bool autoclock; /* from the 'autoclock' module param */ struct usb_host_interface *ctrl_intf; /* the audio control interface */ + + struct mutex dev_lock; /* to protect any race with disconnect */ + int card_num; /* cache pcm card number to use upon disconnect */ + void (*disconnect_cb)(struct snd_usb_audio *chip); }; #define usb_audio_err(chip, fmt, args...) \ --- /dev/null 2019-10-24 16:47:25.704025805 +0200 +++ linux-4.4.115-fbx/arch/arm/boot/dts/include/dt-bindings/clock/audio-ext-clk.h 2019-01-22 16:16:28.167288642 +0100 @@ -0,0 +1,30 @@ +/* Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __AUDIO_EXT_CLK_H +#define __AUDIO_EXT_CLK_H + +/* Audio External Clocks */ +#define AUDIO_PMI_CLK 0 +#define AUDIO_PMIC_LNBB_CLK 0 +#define AUDIO_AP_CLK 1 +#define AUDIO_AP_CLK2 2 +#define AUDIO_LPASS_MCLK 3 +#define AUDIO_LPASS_MCLK2 4 + +#define clk_audio_ap_clk 0x9b5727cb +#define clk_audio_pmi_clk 0xcbfe416d +#define clk_audio_ap_clk2 0x454d1e91 +#define clk_audio_lpass_mclk 0xf0f2a284 +#define clk_audio_pmi_lnbb_clk 0x57312343 + +#endif --- /dev/null 2019-10-24 16:47:25.704025805 +0200 +++ linux-4.4.115-fbx/arch/arm/boot/dts/include/dt-bindings/clock/msm-clocks-8996.h 2019-01-22 16:16:28.171288678 +0100 @@ -0,0 +1,574 @@ +/* Copyright (c) 2014-2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __MSM_CLOCKS_8996_H +#define __MSM_CLOCKS_8996_H + +#include "audio-ext-clk.h" + +/* clock_gcc controlled clocks */ +#define clk_cxo_clk_src 0x79e95308 +#define clk_pnoc_clk 0x4325d220 +#define clk_pnoc_a_clk 0x2808c12b +#define clk_bimc_clk 0x4b80bf00 +#define clk_bimc_a_clk 0x4b25668a +#define clk_cnoc_clk 0xd5ccb7f4 +#define clk_cnoc_a_clk 0xd8fe2ccc +#define clk_snoc_clk 0x2c341aa0 +#define clk_snoc_a_clk 0x8fcef2af +#define clk_bb_clk1 0xf5304268 +#define clk_bb_clk1_ao 0xfa113810 +#define clk_bb_clk1_pin 0x6dd0a779 +#define clk_bb_clk1_pin_ao 0x9b637772 +#define clk_bb_clk2 0xfe15cb87 +#define clk_bb_clk2_ao 0x59682706 +#define clk_bb_clk2_pin 0x498938e5 +#define clk_bb_clk2_pin_ao 0x52513787 +#define clk_bimc_msmbus_clk 0xd212feea +#define clk_bimc_msmbus_a_clk 0x71d1a499 +#define clk_ce1_a_clk 0x44a833fe +#define clk_cnoc_msmbus_clk 0x62228b5d +#define clk_cnoc_msmbus_a_clk 0x67442955 +#define clk_cxo_clk_src_ao 0x64eb6004 +#define clk_cxo_dwc3_clk 0xf79c19f6 +#define clk_cxo_lpm_clk 0x94adbf3d +#define clk_cxo_otg_clk 0x4eec0bb9 +#define clk_cxo_pil_lpass_clk 0xe17f0ff6 +#define clk_cxo_pil_ssc_clk 0x81832015 +#define clk_div_clk1 0xaa1157a6 +#define clk_div_clk1_ao 0x6b943d68 +#define clk_div_clk2 0xd454019f +#define clk_div_clk2_ao 0x53f9e788 +#define clk_div_clk3 0xa9a55a68 +#define clk_div_clk3_ao 0x3d6725a8 +#define clk_ipa_a_clk 0xeeec2919 +#define clk_ipa_clk 0xfa685cda +#define clk_ln_bb_clk 0x3ab0b36d +#define clk_ln_bb_a_clk 0xc7257ea8 +#define clk_ln_bb_clk_pin 0x1b1c476a +#define clk_ln_bb_a_clk_pin 0x9cbb5411 +#define clk_mcd_ce1_clk 0xbb615d26 +#define clk_pnoc_keepalive_a_clk 0xf8f91f0b +#define clk_pnoc_msmbus_clk 0x38b95c77 +#define clk_pnoc_msmbus_a_clk 0x8c9b4e93 +#define clk_pnoc_pm_clk 0xd6f7dfb9 +#define clk_pnoc_sps_clk 0xd482ecc7 +#define clk_qdss_a_clk 0xdd121669 +#define clk_qdss_clk 0x1492202a +#define clk_rf_clk1 0xaabeea5a +#define clk_rf_clk1_ao 0x72a10cb8 +#define clk_rf_clk1_pin 0x8f463562 +#define clk_rf_clk1_pin_ao 0x62549ff6 +#define clk_rf_clk2 0x24a30992 +#define clk_rf_clk2_ao 0x944d8bbd +#define clk_rf_clk2_pin 0xa7c5602a +#define clk_rf_clk2_pin_ao 0x2d75eb4d +#define clk_snoc_msmbus_clk 0xe6900bb6 +#define clk_snoc_msmbus_a_clk 0x5d4683bd +#define clk_mcd_ce1_clk 0xbb615d26 +#define clk_qcedev_ce1_clk 0x293f97b0 +#define clk_qcrypto_ce1_clk 0xa6ac14df +#define clk_qseecom_ce1_clk 0xaa858373 +#define clk_scm_ce1_clk 0xd8ebcc62 +#define clk_ce1_clk 0x42229c55 +#define clk_gcc_ce1_ahb_m_clk 0x2eb28c01 +#define clk_gcc_ce1_axi_m_clk 0xc174dfba +#define clk_measure_only_bimc_hmss_axi_clk 0xc1cc4f11 +#define clk_aggre1_noc_clk 0x049abba8 +#define clk_aggre1_noc_a_clk 0xc12e4220 +#define clk_aggre2_noc_clk 0xaa681404 +#define clk_aggre2_noc_a_clk 0xcab67089 +#define clk_mmssnoc_axi_rpm_clk 0x4d7f8cdc +#define clk_mmssnoc_axi_rpm_a_clk 0xfbea899b +#define clk_mmssnoc_axi_clk 0xdb4b31e6 +#define clk_mmssnoc_axi_a_clk 0xd4970614 +#define clk_mmssnoc_gds_clk 0x06a22afa + +#define clk_gpll0 0x1ebe3bc4 +#define clk_gpll0_ao 0xa1368304 +#define clk_gpll0_out_main 0xe9374de7 +#define clk_gpll4 0xb3b5d85b +#define clk_gpll4_out_main 0xa9a0ab9d +#define clk_ufs_axi_clk_src 0x297ca380 +#define clk_pcie_aux_clk_src 0xebc50566 +#define clk_usb30_master_clk_src 0xc6262f89 +#define clk_usb20_master_clk_src 0x5680ac83 +#define clk_ufs_ice_core_clk_src 0xda8e7119 +#define clk_blsp1_qup1_i2c_apps_clk_src 0x17f78f5e +#define clk_blsp1_qup1_spi_apps_clk_src 0xf534c4fa +#define clk_blsp1_qup2_i2c_apps_clk_src 0x8de71c79 +#define clk_blsp1_qup2_spi_apps_clk_src 0x33cf809a +#define clk_blsp1_qup3_i2c_apps_clk_src 0xf161b902 +#define clk_blsp1_qup3_spi_apps_clk_src 0x5e95683f +#define clk_blsp1_qup4_i2c_apps_clk_src 0xb2ecce68 +#define clk_blsp1_qup4_spi_apps_clk_src 0xddb5bbdb +#define clk_blsp1_qup5_i2c_apps_clk_src 0x71ea7804 +#define clk_blsp1_qup5_spi_apps_clk_src 0x9752f35f +#define clk_blsp1_qup6_i2c_apps_clk_src 0x28806803 +#define clk_blsp1_qup6_spi_apps_clk_src 0x44a1edc4 +#define clk_blsp1_uart1_apps_clk_src 0xf8146114 +#define clk_blsp1_uart2_apps_clk_src 0xfc9c2f73 +#define clk_blsp1_uart3_apps_clk_src 0x600497f2 +#define clk_blsp1_uart4_apps_clk_src 0x56bff15c +#define clk_blsp1_uart5_apps_clk_src 0x218ef697 +#define clk_blsp1_uart6_apps_clk_src 0x8fbdbe4c +#define clk_blsp2_qup1_i2c_apps_clk_src 0xd6d1e95d +#define clk_blsp2_qup1_spi_apps_clk_src 0xcc1b8365 +#define clk_blsp2_qup2_i2c_apps_clk_src 0x603b5c51 +#define clk_blsp2_qup2_spi_apps_clk_src 0xd577dc44 +#define clk_blsp2_qup3_i2c_apps_clk_src 0xea82959c +#define clk_blsp2_qup3_spi_apps_clk_src 0xd04b1e92 +#define clk_blsp2_qup4_i2c_apps_clk_src 0x73dc968c +#define clk_blsp2_qup4_spi_apps_clk_src 0x25d4a2b1 +#define clk_blsp2_qup5_i2c_apps_clk_src 0xcc3698bd +#define clk_blsp2_qup5_spi_apps_clk_src 0xfa0cf45e +#define clk_blsp2_qup6_i2c_apps_clk_src 0x2fa53151 +#define clk_blsp2_qup6_spi_apps_clk_src 0x5ca86755 +#define clk_blsp2_uart1_apps_clk_src 0x562c66dc +#define clk_blsp2_uart2_apps_clk_src 0xdd448080 +#define clk_blsp2_uart3_apps_clk_src 0x46b2e90f +#define clk_blsp2_uart4_apps_clk_src 0x23a093d2 +#define clk_blsp2_uart5_apps_clk_src 0xe067616a +#define clk_blsp2_uart6_apps_clk_src 0xe02d2829 +#define clk_gp1_clk_src 0xad85b97a +#define clk_gp2_clk_src 0xfb1f0065 +#define clk_gp3_clk_src 0x63b693d6 +#define clk_hmss_rbcpr_clk_src 0xedd9a474 +#define clk_pdm2_clk_src 0x31e494fd +#define clk_sdcc1_apps_clk_src 0xd4975db2 +#define clk_sdcc2_apps_clk_src 0xfc46c821 +#define clk_sdcc3_apps_clk_src 0xea34c7f4 +#define clk_sdcc4_apps_clk_src 0x7aaaaa0c +#define clk_tsif_ref_clk_src 0x4e9042d1 +#define clk_usb20_mock_utmi_clk_src 0xc3aaeecb +#define clk_usb30_mock_utmi_clk_src 0xa024a976 +#define clk_usb3_phy_aux_clk_src 0x15eec63c +#define clk_gcc_qusb2phy_prim_reset 0x07550fa1 +#define clk_gcc_qusb2phy_sec_reset 0x3f3a87d0 +#define clk_gcc_periph_noc_usb20_ahb_clk 0xfb9f26e9 +#define clk_gcc_mmss_gcc_dbg_clk 0xe89d461c +#define clk_cpu_dbg_clk 0x6550dfa9 +#define clk_gcc_blsp1_ahb_clk 0x8caa5b4f +#define clk_gcc_blsp1_qup1_i2c_apps_clk 0xc303fae9 +#define clk_gcc_blsp1_qup1_spi_apps_clk 0x759a76b0 +#define clk_gcc_blsp1_qup2_i2c_apps_clk 0x1076f220 +#define clk_gcc_blsp1_qup2_spi_apps_clk 0x3e77d48f +#define clk_gcc_blsp1_qup3_i2c_apps_clk 0x9e25ac82 +#define clk_gcc_blsp1_qup3_spi_apps_clk 0xfb978880 +#define clk_gcc_blsp1_qup4_i2c_apps_clk 0xd7f40f6f +#define clk_gcc_blsp1_qup4_spi_apps_clk 0x80f8722f +#define clk_gcc_blsp1_qup5_i2c_apps_clk 0xacae5604 +#define clk_gcc_blsp1_qup5_spi_apps_clk 0xbf3e15d7 +#define clk_gcc_blsp1_qup6_i2c_apps_clk 0x5c6ad820 +#define clk_gcc_blsp1_qup6_spi_apps_clk 0x780d9f85 +#define clk_gcc_blsp1_uart1_apps_clk 0xc7c62f90 +#define clk_gcc_blsp1_uart2_apps_clk 0xf8a61c96 +#define clk_gcc_blsp1_uart3_apps_clk 0xc3298bd7 +#define clk_gcc_blsp1_uart4_apps_clk 0x26be16c0 +#define clk_gcc_blsp1_uart5_apps_clk 0x28a6bc74 +#define clk_gcc_blsp1_uart6_apps_clk 0x28fd3466 +#define clk_gcc_blsp2_ahb_clk 0x8f283c1d +#define clk_gcc_blsp2_qup1_i2c_apps_clk 0x9ace11dd +#define clk_gcc_blsp2_qup1_spi_apps_clk 0xa32604cc +#define clk_gcc_blsp2_qup2_i2c_apps_clk 0x1bf9a57e +#define clk_gcc_blsp2_qup2_spi_apps_clk 0xbf54ca6d +#define clk_gcc_blsp2_qup3_i2c_apps_clk 0x336d4170 +#define clk_gcc_blsp2_qup3_spi_apps_clk 0xc68509d6 +#define clk_gcc_blsp2_qup4_i2c_apps_clk 0xbd22539d +#define clk_gcc_blsp2_qup4_spi_apps_clk 0x01a72b93 +#define clk_gcc_blsp2_qup5_i2c_apps_clk 0xe2b2ce1d +#define clk_gcc_blsp2_qup5_spi_apps_clk 0xf40999cd +#define clk_gcc_blsp2_qup6_i2c_apps_clk 0x894bcea4 +#define clk_gcc_blsp2_qup6_spi_apps_clk 0xfe1bd34a +#define clk_gcc_blsp2_uart1_apps_clk 0x8c3512ff +#define clk_gcc_blsp2_uart2_apps_clk 0x1e1965a3 +#define clk_gcc_blsp2_uart3_apps_clk 0x382415ab +#define clk_gcc_blsp2_uart4_apps_clk 0x87a44b42 +#define clk_gcc_blsp2_uart5_apps_clk 0x5cd30649 +#define clk_gcc_blsp2_uart6_apps_clk 0x8feee5ab +#define clk_gcc_boot_rom_ahb_clk 0xde2adeb1 +#define clk_gcc_gp1_clk 0x057f7b69 +#define clk_gcc_gp2_clk 0x9bf83ffd +#define clk_gcc_gp3_clk 0xec6539ee +#define clk_gcc_hmss_rbcpr_clk 0x699183be +#define clk_gcc_mmss_noc_cfg_ahb_clk 0xb41a9d99 +#define clk_gcc_pcie_0_aux_clk 0x3d2e3ece +#define clk_gcc_pcie_0_cfg_ahb_clk 0x4dd325c3 +#define clk_gcc_pcie_0_mstr_axi_clk 0x3f85285b +#define clk_gcc_pcie_0_slv_axi_clk 0xd69638a1 +#define clk_gcc_pcie_0_pipe_clk 0x4f37621e +#define clk_gcc_pcie_0_phy_reset 0xdc3201c1 +#define clk_gcc_pcie_1_aux_clk 0xc9bb962c +#define clk_gcc_pcie_1_cfg_ahb_clk 0xb6338658 +#define clk_gcc_pcie_1_mstr_axi_clk 0xc20f6269 +#define clk_gcc_pcie_1_slv_axi_clk 0xd54e40d6 +#define clk_gcc_pcie_1_pipe_clk 0xc1627422 +#define clk_gcc_pcie_1_phy_reset 0x674481bb +#define clk_gcc_pcie_2_aux_clk 0xa4dc7ae8 +#define clk_gcc_pcie_2_cfg_ahb_clk 0x4f1d3121 +#define clk_gcc_pcie_2_mstr_axi_clk 0x9e81724a +#define clk_gcc_pcie_2_slv_axi_clk 0x7990d8b2 +#define clk_gcc_pcie_2_pipe_clk 0xa757a834 +#define clk_gcc_pcie_2_phy_reset 0x82634880 +#define clk_gcc_pcie_phy_reset 0x9bc3c959 +#define clk_gcc_pcie_phy_com_reset 0x8bf513e6 +#define clk_gcc_pcie_phy_nocsr_com_phy_reset 0x0c16a2da +#define clk_gcc_pcie_phy_aux_clk 0x4746e74f +#define clk_gcc_pcie_phy_cfg_ahb_clk 0x8533671a +#define clk_gcc_pdm2_clk 0x99d55711 +#define clk_gcc_pdm_ahb_clk 0x365664f6 +#define clk_gcc_prng_ahb_clk 0x397e7eaa +#define clk_gcc_sdcc1_ahb_clk 0x691e0caa +#define clk_gcc_sdcc1_apps_clk 0x9ad6fb96 +#define clk_gcc_sdcc2_ahb_clk 0x23d5727f +#define clk_gcc_sdcc2_apps_clk 0x861b20ac +#define clk_gcc_sdcc3_ahb_clk 0x565b2c03 +#define clk_gcc_sdcc3_apps_clk 0x0b27aeac +#define clk_gcc_sdcc4_ahb_clk 0x64f3e6a8 +#define clk_gcc_sdcc4_apps_clk 0xbf7c4dc8 +#define clk_gcc_tsif_ahb_clk 0x88d2822c +#define clk_gcc_tsif_ref_clk 0x8f1ed2c2 +#define clk_gcc_ufs_ahb_clk 0x1914bb84 +#define clk_gcc_ufs_axi_clk 0x47c743a7 +#define clk_gcc_ufs_ice_core_clk 0x310b0710 +#define clk_gcc_ufs_rx_cfg_clk 0xa6747786 +#define clk_gcc_ufs_rx_symbol_0_clk 0x7f43251c +#define clk_gcc_ufs_rx_symbol_1_clk 0x03182fde +#define clk_gcc_ufs_tx_cfg_clk 0xba2cf8b5 +#define clk_gcc_ufs_tx_symbol_0_clk 0x6a9f747a +#define clk_gcc_ufs_unipro_core_clk 0x2daf7fd2 +#define clk_gcc_ufs_sys_clk_core_clk 0x360e5ac8 +#define clk_gcc_ufs_tx_symbol_clk_core_clk 0xf6fb0df7 +#define clk_gcc_usb20_master_clk 0x24c3b66a +#define clk_gcc_usb20_mock_utmi_clk 0xe8db8203 +#define clk_gcc_usb20_sleep_clk 0x6e8cb4b2 +#define clk_gcc_usb30_master_clk 0xb3b4e2cb +#define clk_gcc_usb30_mock_utmi_clk 0xa800b65a +#define clk_gcc_usb30_sleep_clk 0xd0b65c92 +#define clk_gcc_usb3_phy_aux_clk 0x0d9a36e0 +#define clk_gcc_usb3_phy_pipe_clk 0xf279aff2 +#define clk_gcc_usb_phy_cfg_ahb2phy_clk 0xd1231a0e +#define clk_gcc_aggre0_cnoc_ahb_clk 0x53a35559 +#define clk_gcc_aggre0_snoc_axi_clk 0x3c446400 +#define clk_gcc_aggre0_noc_qosgen_extref_clk 0x8c4356ba +#define clk_hlos1_vote_lpass_core_smmu_clk 0x3aaa1743 +#define clk_hlos1_vote_lpass_adsp_smmu_clk 0xc76f702f +#define clk_gcc_usb3_phy_reset 0x03d559f1 +#define clk_gcc_usb3phy_phy_reset 0xb1a4f885 +#define clk_gcc_usb3_clkref_clk 0xb6cc8f01 +#define clk_gcc_hdmi_clkref_clk 0x4d4eec04 +#define clk_gcc_edp_clkref_clk 0xa8685c3f +#define clk_gcc_ufs_clkref_clk 0x92aa126f +#define clk_gcc_pcie_clkref_clk 0xa2e247fa +#define clk_gcc_rx2_usb2_clkref_clk 0x27ec24ba +#define clk_gcc_rx1_usb2_clkref_clk 0x53351d25 +#define clk_gcc_smmu_aggre0_ahb_clk 0x47a06ce4 +#define clk_gcc_smmu_aggre0_axi_clk 0x3cac4a6c +#define clk_gcc_sys_noc_usb3_axi_clk 0x94d26800 +#define clk_gcc_sys_noc_ufs_axi_clk 0x19d38312 +#define clk_gcc_aggre2_usb3_axi_clk 0xd5822a8e +#define clk_gcc_aggre2_ufs_axi_clk 0xb31e5191 +#define clk_gcc_mmss_gpll0_div_clk 0xdd06848d +#define clk_gcc_mmss_bimc_gfx_clk 0xe4f28754 +#define clk_gcc_bimc_gfx_clk 0x3edd69ad +#define clk_gcc_qspi_ahb_clk 0x96969dc8 +#define clk_gcc_qspi_ser_clk 0xfaf1e266 +#define clk_qspi_ser_clk_src 0x426676ee +#define clk_sdcc1_ice_core_clk_src 0xfd6a4301 +#define clk_gcc_sdcc1_ice_core_clk 0x0fd5680a +#define clk_gcc_mss_cfg_ahb_clk 0x111cde81 +#define clk_gcc_mss_snoc_axi_clk 0x0e71de85 +#define clk_gcc_mss_q6_bimc_axi_clk 0x67544d62 +#define clk_gcc_mss_mnoc_bimc_axi_clk 0xf665d03f +#define clk_gpll0_out_msscc 0x7d794829 +#define clk_gcc_debug_mux_v2 0xf7e749f0 +#define clk_gcc_dcc_ahb_clk 0xfa14a88c +#define clk_gcc_aggre0_noc_mpu_cfg_ahb_clk 0x5c1bb8e2 + +/* clock_mmss controlled clocks */ +#define clk_mmsscc_xo 0x05e63704 +#define clk_mmsscc_gpll0 0xe900c515 +#define clk_mmsscc_gpll0_div 0x73892e05 +#define clk_mmsscc_mmssnoc_ahb 0x7b4bd6f7 +#define clk_mmpll0 0xdd83b751 +#define clk_mmpll0_out_main 0x2f996a31 +#define clk_mmpll1 0x6da7fb90 +#define clk_mmpll1_out_main 0xa0d3a7da +#define clk_mmpll4 0x22c063c1 +#define clk_mmpll4_out_main 0xfb21c2fd +#define clk_mmpll3 0x18c76899 +#define clk_mmpll3_out_main 0x6eb6328f +#define clk_ahb_clk_src 0x86f49203 +#define clk_mmpll2 0x1190e4d8 +#define clk_mmpll2_out_main 0x1e9e24a8 +#define clk_mmpll8 0xd06ad45e +#define clk_mmpll8_out_main 0x75b1f386 +#define clk_mmpll9 0x1c50684c +#define clk_mmpll9_out_main 0x16b74937 +#define clk_mmpll5 0xa41e1936 +#define clk_mmpll5_out_main 0xcc1897bf +#define clk_csi0_clk_src 0x227e65bc +#define clk_vfe0_clk_src 0xa0c2bd8f +#define clk_vfe1_clk_src 0x4e357366 +#define clk_csi1_clk_src 0x6a2a6c36 +#define clk_csi2_clk_src 0x4113589f +#define clk_csi3_clk_src 0xfd934012 +#define clk_maxi_clk_src 0x52c09777 +#define clk_cpp_clk_src 0x8382f56d +#define clk_jpeg0_clk_src 0x9a0a0ac3 +#define clk_jpeg2_clk_src 0x5ad927f3 +#define clk_jpeg_dma_clk_src 0xb68afcea +#define clk_mdp_clk_src 0x6dc1f8f1 +#define clk_video_core_clk_src 0x8be4c944 +#define clk_fd_core_clk_src 0xe4799ab7 +#define clk_cci_clk_src 0x822f3d97 +#define clk_csiphy0_3p_clk_src 0xd2474b12 +#define clk_csiphy1_3p_clk_src 0x46a02aff +#define clk_csiphy2_3p_clk_src 0x1447813f +#define clk_camss_gp0_clk_src 0x6b57cfe6 +#define clk_camss_gp1_clk_src 0xf735368a +#define clk_jpeg_dma_clk_src 0xb68afcea +#define clk_mclk0_clk_src 0x266b3853 +#define clk_mclk1_clk_src 0xa73cad0c +#define clk_mclk2_clk_src 0x42545468 +#define clk_mclk3_clk_src 0x2bfbb714 +#define clk_csi0phytimer_clk_src 0xc8a309be +#define clk_csi1phytimer_clk_src 0x7c0fe23a +#define clk_csi2phytimer_clk_src 0x62ffea9c +#define clk_rbbmtimer_clk_src 0x17649ecc +#define clk_esc0_clk_src 0xb41d7c38 +#define clk_esc1_clk_src 0x3b0afa42 +#define clk_hdmi_clk_src 0xb40aeea9 +#define clk_vsync_clk_src 0xecb43940 +#define clk_rbcpr_clk_src 0x2c2e9af2 +#define clk_video_subcore0_clk_src 0x88d79636 +#define clk_video_subcore1_clk_src 0x4966930c +#define clk_mmss_bto_ahb_clk 0xfdf8c361 +#define clk_camss_ahb_clk 0xc4ff91d4 +#define clk_camss_cci_ahb_clk 0x04c4441a +#define clk_camss_cci_clk 0xd6cb5eb9 +#define clk_camss_cpp_ahb_clk 0x12e9a87b +#define clk_camss_cpp_clk 0xb82f366b +#define clk_camss_cpp_axi_clk 0x5598c804 +#define clk_camss_cpp_vbif_ahb_clk 0xb5f31be4 +#define clk_camss_csi0_ahb_clk 0x6e29c972 +#define clk_camss_csi0_clk 0x30862ddb +#define clk_camss_csi0phy_clk 0x2cecfb84 +#define clk_camss_csi0pix_clk 0x6946f77b +#define clk_camss_csi0rdi_clk 0x83645ef5 +#define clk_camss_csi1_ahb_clk 0xccc15f06 +#define clk_camss_csi1_clk 0xb150f052 +#define clk_camss_csi1phy_clk 0xb989f06d +#define clk_camss_csi1pix_clk 0x58d19bf3 +#define clk_camss_csi1rdi_clk 0x4d2f3352 +#define clk_camss_csi2_ahb_clk 0x92d02d75 +#define clk_camss_csi2_clk 0x74fc92e8 +#define clk_camss_csi2phy_clk 0xda05d9d8 +#define clk_camss_csi2pix_clk 0xf8ed0731 +#define clk_camss_csi2rdi_clk 0xdc1b2081 +#define clk_camss_csi3_ahb_clk 0xee5e459c +#define clk_camss_csi3_clk 0x39488fdd +#define clk_camss_csi3phy_clk 0x8b6063b9 +#define clk_camss_csi3pix_clk 0xd82bd467 +#define clk_camss_csi3rdi_clk 0xb6750046 +#define clk_camss_csi_vfe0_clk 0x3023937a +#define clk_camss_csi_vfe1_clk 0xe66fa522 +#define clk_camss_csiphy0_3p_clk 0xf2a54f5a +#define clk_camss_csiphy1_3p_clk 0x8bf70cb2 +#define clk_camss_csiphy2_3p_clk 0x1c14c939 +#define clk_camss_gp0_clk 0xcee7e51d +#define clk_camss_gp1_clk 0x41f1c2e3 +#define clk_camss_ispif_ahb_clk 0x9a212c6d +#define clk_camss_jpeg0_clk 0x0b0e2db7 +#define clk_camss_jpeg2_clk 0xd7291c8d +#define clk_camss_jpeg_ahb_clk 0x1f47fd28 +#define clk_camss_jpeg_axi_clk 0x9e5545c8 +#define clk_camss_jpeg_dma_clk 0x2336e65d +#define clk_camss_mclk0_clk 0xcf0c61e0 +#define clk_camss_mclk1_clk 0xd1410ed4 +#define clk_camss_mclk2_clk 0x851286f2 +#define clk_camss_mclk3_clk 0x4db11c45 +#define clk_camss_micro_ahb_clk 0x33a23277 +#define clk_camss_csi0phytimer_clk 0xff93b3c8 +#define clk_camss_csi1phytimer_clk 0x6c399ab6 +#define clk_camss_csi2phytimer_clk 0x24f47f49 +#define clk_camss_top_ahb_clk 0x8f8b2d33 +#define clk_camss_vfe_ahb_clk 0x595197bc +#define clk_camss_vfe_axi_clk 0x273d4c31 +#define clk_camss_vfe0_ahb_clk 0x4652833c +#define clk_camss_vfe0_clk 0x1e9bb8c4 +#define clk_camss_vfe0_stream_clk 0x22835fa4 +#define clk_camss_vfe1_ahb_clk 0x6a56abd3 +#define clk_camss_vfe1_clk 0x5bffa69b +#define clk_camss_vfe1_stream_clk 0x92f849b9 +#define clk_fd_ahb_clk 0x868a2c5c +#define clk_fd_core_clk 0x3badcae4 +#define clk_fd_core_uar_clk 0x7e624e15 +#define clk_gpu_ahb_clk 0xf97f1d43 +#define clk_gpu_aon_isense_clk 0xa9e9b297 +#define clk_gpu_gx_gfx3d_clk 0xb7ece823 +#define clk_gpu_mx_clk 0xb80ccedf +#define clk_gpu_gx_rbbmtimer_clk 0xdeba634e +#define clk_mdss_ahb_clk 0x684ccb41 +#define clk_mdss_axi_clk 0xcc07d687 +#define clk_mdss_esc0_clk 0x28cafbe6 +#define clk_mdss_esc1_clk 0xc22c6883 +#define clk_mdss_hdmi_ahb_clk 0x01cef516 +#define clk_mdss_hdmi_clk 0x097a6de9 +#define clk_mdss_mdp_clk 0x618336ac +#define clk_mdss_vsync_clk 0x42a022d3 +#define clk_mmss_misc_ahb_clk 0xea30b0e7 +#define clk_mmss_misc_cxo_clk 0xe620cd80 +#define clk_mmagic_bimc_noc_cfg_ahb_clk 0x12d5ba72 +#define clk_mmagic_camss_axi_clk 0xa8b1c16b +#define clk_mmagic_camss_noc_cfg_ahb_clk 0x5182c819 +#define clk_mmss_mmagic_cfg_ahb_clk 0x5e94a822 +#define clk_mmagic_mdss_axi_clk 0xa0359d10 +#define clk_mmagic_mdss_noc_cfg_ahb_clk 0x9c6d5482 +#define clk_mmagic_video_axi_clk 0x7b9219c3 +#define clk_mmagic_video_noc_cfg_ahb_clk 0x5124d256 +#define clk_mmss_mmagic_ahb_clk 0x3d15f2b0 +#define clk_mmss_mmagic_maxi_clk 0xbdaf5af7 +#define clk_mmss_rbcpr_ahb_clk 0x623ba55f +#define clk_mmss_rbcpr_clk 0x69a23a6f +#define clk_mmss_spdm_cpp_clk 0xefe35cd2 +#define clk_mmss_spdm_jpeg_dma_clk 0xcb7bd5a0 +#define clk_smmu_cpp_ahb_clk 0x3ad82d84 +#define clk_smmu_cpp_axi_clk 0xa6bb2f4a +#define clk_smmu_jpeg_ahb_clk 0x10c436ec +#define clk_smmu_jpeg_axi_clk 0x41112f37 +#define clk_smmu_mdp_ahb_clk 0x04994cb2 +#define clk_smmu_mdp_axi_clk 0x7fd71687 +#define clk_smmu_rot_ahb_clk 0xa30772c9 +#define clk_smmu_rot_axi_clk 0xfed7c078 +#define clk_smmu_vfe_ahb_clk 0x4dabebe7 +#define clk_smmu_vfe_axi_clk 0xde483725 +#define clk_smmu_video_ahb_clk 0x2d738e2c +#define clk_smmu_video_axi_clk 0xe2b5b887 +#define clk_video_ahb_clk 0x90775cfb +#define clk_video_axi_clk 0xe6c16dba +#define clk_video_core_clk 0x7e876ec3 +#define clk_video_maxi_clk 0x97749db6 +#define clk_video_subcore0_clk 0xb6f63e6c +#define clk_video_subcore1_clk 0x26c29cb4 +#define clk_vmem_ahb_clk 0xab6223ff +#define clk_vmem_maxi_clk 0x15ef32db +#define clk_mmss_debug_mux 0xe646ffda +#define clk_mmss_gcc_dbg_clk 0xafa4d48a +#define clk_gfx3d_clk_src 0x917f76ef +#define clk_extpclk_clk_src 0xb2c31abd +#define clk_mdss_byte0_clk 0xf5a03f64 +#define clk_mdss_byte1_clk 0xb8c7067d +#define clk_mdss_extpclk_clk 0xfa5aadb0 +#define clk_mdss_pclk0_clk 0x3487234a +#define clk_mdss_pclk1_clk 0xd5804246 +#define clk_gpu_gcc_dbg_clk 0x0ccc42cd +#define clk_mdss_mdp_vote_clk 0x588460a4 +#define clk_mdss_rotator_vote_clk 0x5b1f675e +#define clk_mmpll2_postdiv_clk 0x4fdeaaba +#define clk_mmpll8_postdiv_clk 0xedf57882 +#define clk_mmpll9_postdiv_clk 0x3064b618 +#define clk_gfx3d_clk_src_v2 0x4210acb7 +#define clk_byte0_clk_src 0x75cc885b +#define clk_byte1_clk_src 0x63c2c955 +#define clk_pclk0_clk_src 0xccac1f35 +#define clk_pclk1_clk_src 0x090f68ac +#define clk_ext_byte0_clk_src 0xfb32f31e +#define clk_ext_byte1_clk_src 0x585ef6d4 +#define clk_ext_pclk0_clk_src 0x087c1612 +#define clk_ext_pclk1_clk_src 0x8067c5a3 + +/* clock_debug controlled clocks */ +#define clk_gcc_debug_mux 0x8121ac15 + +/* external multimedia clocks */ +#define clk_dsi0pll_pixel_clk_mux 0x792379e1 +#define clk_dsi0pll_byte_clk_mux 0x60e83f06 +#define clk_dsi0pll_byte_clk_src 0xbbaa30be +#define clk_dsi0pll_pixel_clk_src 0x45b3260f +#define clk_dsi0pll_n2_div_clk 0x1474c213 +#define clk_dsi0pll_post_n1_div_clk 0xdab8c389 +#define clk_dsi0pll_vco_clk 0x15940d40 +#define clk_dsi1pll_pixel_clk_mux 0x36458019 +#define clk_dsi1pll_byte_clk_mux 0xb5a42b7b +#define clk_dsi1pll_byte_clk_src 0x63930a8f +#define clk_dsi1pll_pixel_clk_src 0x0e4c9b56 +#define clk_dsi1pll_n2_div_clk 0x2c9d4007 +#define clk_dsi1pll_post_n1_div_clk 0x03020041 +#define clk_dsi1pll_vco_clk 0x99797b50 +#define clk_mdss_dsi1_vco_clk_src 0xfcd15658 +#define clk_hdmi_vco_clk 0x66003284 + +#define clk_dsi0pll_shadow_byte_clk_src 0x177c029c +#define clk_dsi0pll_shadow_pixel_clk_src 0x98ae3c92 +#define clk_dsi0pll_shadow_n2_div_clk 0xd5f0dad9 +#define clk_dsi0pll_shadow_post_n1_div_clk 0x1f7c8cf8 +#define clk_dsi0pll_shadow_vco_clk 0xb100ca83 +#define clk_dsi1pll_shadow_byte_clk_src 0xfc021ce5 +#define clk_dsi1pll_shadow_pixel_clk_src 0xdcca3ffc +#define clk_dsi1pll_shadow_n2_div_clk 0x189541bf +#define clk_dsi1pll_shadow_post_n1_div_clk 0x1637020e +#define clk_dsi1pll_shadow_vco_clk 0x68d8b6f7 + +/* CPU clocks */ +#define clk_pwrcl_clk 0xc554130e +#define clk_pwrcl_pll 0x25454ca1 +#define clk_pwrcl_alt_pll 0xc445471b +#define clk_pwrcl_pll_main 0x28948e22 +#define clk_pwrcl_alt_pll_main 0x25c8270e +#define clk_pwrcl_hf_mux 0x77706ae6 +#define clk_pwrcl_lf_mux 0xd99e334d +#define clk_perfcl_clk 0x58869997 +#define clk_perfcl_pll 0x97dcec1c +#define clk_perfcl_alt_pll 0xfe2eaea1 +#define clk_perfcl_pll_main 0x0dbf0c0b +#define clk_perfcl_alt_pll_main 0x0b892aab +#define clk_perfcl_hf_mux 0x9e8bbe59 +#define clk_perfcl_lf_mux 0x2f9c278d +#define clk_cbf_pll 0xfe2e96a3 +#define clk_cbf_pll_main 0x2b05cf95 +#define clk_cbf_hf_mux 0x71244f73 +#define clk_cbf_clk 0x48e9e16b +#define clk_xo_ao 0x428c856d +#define clk_sys_apcsaux_clk 0x0b0dd513 +#define clk_cpu_debug_mux 0xc7acaa31 + +/* GCC block resets */ +#define QUSB2PHY_PRIM_BCR 0 +#define QUSB2PHY_SEC_BCR 1 +#define BLSP1_BCR 2 +#define BLSP2_BCR 3 +#define BOOT_ROM_BCR 4 +#define PRNG_BCR 5 +#define UFS_BCR 6 +#define USB_20_BCR 7 +#define USB_30_BCR 8 +#define USB3_PHY_BCR 9 +#define USB3PHY_PHY_BCR 10 +#define PCIE_0_PHY_BCR 11 +#define PCIE_1_PHY_BCR 12 +#define PCIE_2_PHY_BCR 13 +#define PCIE_PHY_BCR 14 +#define PCIE_PHY_COM_BCR 15 +#define PCIE_PHY_NOCSR_COM_PHY_BCR 16 + +/* MMSS Block resets */ +#define VIDEO_BCR 0 +#define MDSS_BCR 1 +#define CAMSS_MICRO_BCR 2 +#define CAMSS_JPEG_BCR 3 +#define CAMSS_VFE0_BCR 4 +#define CAMSS_VFE1_BCR 5 +#define FD_BCR 6 +#define GPU_GX_BCR 7 + +#endif --- /dev/null 2019-10-24 16:47:25.704025805 +0200 +++ linux-4.4.115-fbx/arch/arm/boot/dts/include/dt-bindings/clock/msm-clocks-8998.h 2019-01-22 16:16:28.171288678 +0100 @@ -0,0 +1,534 @@ +/* Copyright (c) 2015-2017, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __MSM_CLOCKS_8998_H +#define __MSM_CLOCKS_8998_H + +#include "audio-ext-clk.h" + +/* clock_rpm controlled clocks */ +#define clk_ce1_clk 0x42229c55 +#define clk_ce1_a_clk 0x44a833fe +#define clk_cxo_clk_src 0x79e95308 +#define clk_bimc_clk 0x4b80bf00 +#define clk_bimc_a_clk 0x4b25668a +#define clk_cnoc_clk 0xd5ccb7f4 +#define clk_cnoc_a_clk 0xd8fe2ccc +#define clk_snoc_clk 0x2c341aa0 +#define clk_snoc_a_clk 0x8fcef2af +#define clk_cnoc_periph_clk 0xb11e9cf9 +#define clk_cnoc_periph_a_clk 0x1d7faa2e +#define clk_cnoc_periph_keepalive_a_clk 0x7287aef2 +#define clk_ln_bb_clk1 0xb867b147 +#define clk_ln_bb_clk1_ao 0x7f63a93a +#define clk_ln_bb_clk1_pin 0x6fc5653c +#define clk_ln_bb_clk1_pin_ao 0x25d625bf +#define clk_ln_bb_clk2 0xf83e6387 +#define clk_ln_bb_clk2_ao 0x96f09628 +#define clk_ln_bb_clk2_pin 0xa9ebe8d5 +#define clk_ln_bb_clk2_pin_ao 0x89a1226f +#define clk_ln_bb_clk3 0x4f52a39e +#define clk_ln_bb_clk3_ao 0xb15eba76 +#define clk_ln_bb_clk3_pin 0xc4de7dad +#define clk_ln_bb_clk3_pin_ao 0xc01022e8 +#define clk_bimc_msmbus_clk 0xd212feea +#define clk_bimc_msmbus_a_clk 0x71d1a499 +#define clk_cnoc_msmbus_clk 0x62228b5d +#define clk_cnoc_msmbus_a_clk 0x67442955 +#define clk_cxo_clk_src_ao 0x64eb6004 +#define clk_cxo_dwc3_clk 0xf79c19f6 +#define clk_cxo_lpm_clk 0x94adbf3d +#define clk_cxo_otg_clk 0x4eec0bb9 +#define clk_cxo_pil_lpass_clk 0xe17f0ff6 +#define clk_cxo_pil_ssc_clk 0x81832015 +#define clk_cxo_pil_spss_clk 0x5cd71a61 +#define clk_div_clk1 0xaa1157a6 +#define clk_div_clk1_ao 0x6b943d68 +#define clk_div_clk2 0xd454019f +#define clk_div_clk2_ao 0x53f9e788 +#define clk_div_clk3 0xa9a55a68 +#define clk_div_clk3_ao 0x3d6725a8 +#define clk_ipa_clk 0xfa685cda +#define clk_ipa_a_clk 0xeeec2919 +#define clk_mcd_ce1_clk 0xbb615d26 +#define clk_mmssnoc_axi_clk 0xdb4b31e6 +#define clk_mmssnoc_axi_a_clk 0xd4970614 +#define clk_qcedev_ce1_clk 0x293f97b0 +#define clk_qcrypto_ce1_clk 0xa6ac14df +#define clk_qdss_clk 0x1492202a +#define clk_qdss_a_clk 0xdd121669 +#define clk_qseecom_ce1_clk 0xaa858373 +#define clk_rf_clk1 0xaabeea5a +#define clk_rf_clk1_ao 0x72a10cb8 +#define clk_rf_clk1_pin 0x8f463562 +#define clk_rf_clk1_pin_ao 0x62549ff6 +#define clk_rf_clk2 0x24a30992 +#define clk_rf_clk2_ao 0x944d8bbd +#define clk_rf_clk2_pin 0xa7c5602a +#define clk_rf_clk2_pin_ao 0x2d75eb4d +#define clk_rf_clk3 0xb673936b +#define clk_rf_clk3_ao 0x038bb968 +#define clk_rf_clk3_pin 0x726f53f5 +#define clk_rf_clk3_pin_ao 0x76f9240f +#define clk_scm_ce1_clk 0xd8ebcc62 +#define clk_snoc_msmbus_clk 0xe6900bb6 +#define clk_snoc_msmbus_a_clk 0x5d4683bd +#define clk_gcc_ce1_ahb_m_clk 0x2eb28c01 +#define clk_gcc_ce1_axi_m_clk 0xc174dfba +#define clk_aggre1_noc_clk 0x049abba8 +#define clk_aggre1_noc_a_clk 0xc12e4220 +#define clk_aggre2_noc_clk 0xaa681404 +#define clk_aggre2_noc_a_clk 0xcab67089 +#define clk_measure_only_bimc_hmss_axi_clk 0xc1cc4f11 + +/* clock_gcc controlled clocks*/ +#define clk_debug_mmss_clk 0x977c99b6 +#define clk_debug_rpm_clk 0x8e2b07ca +#define clk_debug_cpu_clk 0x0e696b2b +#define clk_gpu_gcc_debug_clk 0x3eb88190 +#define clk_gfx_gcc_debug_clk 0xa3a64fec +#define clk_gpll0 0x1ebe3bc4 +#define clk_gpll0_out_main 0xe9374de7 +#define clk_gpll0_ao 0xa1368304 +#define clk_gcc_mmss_gpll0_clk 0x8050f008 +#define clk_gcc_mmss_gpll0_div_clk 0xdd06848d +#define clk_gcc_gpu_gpll0_clk 0xdad7a7a4 +#define clk_gcc_gpu_gpll0_div_clk 0x07d16c6a +#define clk_gpll4 0xb3b5d85b +#define clk_gpll4_out_main 0xa9a0ab9d +#define clk_usb30_master_clk_src 0xc6262f89 +#define clk_pcie_aux_clk_src 0xebc50566 +#define clk_ufs_axi_clk_src 0x297ca380 +#define clk_blsp1_qup1_i2c_apps_clk_src 0x17f78f5e +#define clk_blsp1_qup1_spi_apps_clk_src 0xf534c4fa +#define clk_blsp1_qup2_i2c_apps_clk_src 0x8de71c79 +#define clk_blsp1_qup2_spi_apps_clk_src 0x33cf809a +#define clk_blsp1_qup3_i2c_apps_clk_src 0xf161b902 +#define clk_blsp1_qup3_spi_apps_clk_src 0x5e95683f +#define clk_blsp1_qup4_i2c_apps_clk_src 0xb2ecce68 +#define clk_blsp1_qup4_spi_apps_clk_src 0xddb5bbdb +#define clk_blsp1_qup5_i2c_apps_clk_src 0x71ea7804 +#define clk_blsp1_qup5_spi_apps_clk_src 0x9752f35f +#define clk_blsp1_qup6_i2c_apps_clk_src 0x28806803 +#define clk_blsp1_qup6_spi_apps_clk_src 0x44a1edc4 +#define clk_blsp1_uart1_apps_clk_src 0xf8146114 +#define clk_blsp1_uart2_apps_clk_src 0xfc9c2f73 +#define clk_blsp1_uart3_apps_clk_src 0x600497f2 +#define clk_blsp2_qup1_i2c_apps_clk_src 0xd6d1e95d +#define clk_blsp2_qup1_spi_apps_clk_src 0xcc1b8365 +#define clk_blsp2_qup2_i2c_apps_clk_src 0x603b5c51 +#define clk_blsp2_qup2_spi_apps_clk_src 0xd577dc44 +#define clk_blsp2_qup3_i2c_apps_clk_src 0xea82959c +#define clk_blsp2_qup3_spi_apps_clk_src 0xd04b1e92 +#define clk_blsp2_qup4_i2c_apps_clk_src 0x73dc968c +#define clk_blsp2_qup4_spi_apps_clk_src 0x25d4a2b1 +#define clk_blsp2_qup5_i2c_apps_clk_src 0xcc3698bd +#define clk_blsp2_qup5_spi_apps_clk_src 0xfa0cf45e +#define clk_blsp2_qup6_i2c_apps_clk_src 0x2fa53151 +#define clk_blsp2_qup6_spi_apps_clk_src 0x5ca86755 +#define clk_blsp2_uart1_apps_clk_src 0x562c66dc +#define clk_blsp2_uart2_apps_clk_src 0xdd448080 +#define clk_blsp2_uart3_apps_clk_src 0x46b2e90f +#define clk_gp1_clk_src 0xad85b97a +#define clk_gp2_clk_src 0xfb1f0065 +#define clk_gp3_clk_src 0x63b693d6 +#define clk_hmss_rbcpr_clk_src 0xedd9a474 +#define clk_pdm2_clk_src 0x31e494fd +#define clk_sdcc2_apps_clk_src 0xfc46c821 +#define clk_sdcc4_apps_clk_src 0x7aaaaa0c +#define clk_tsif_ref_clk_src 0x4e9042d1 +#define clk_ufs_ice_core_clk_src 0xda8e7119 +#define clk_ufs_phy_aux_clk_src 0xc6bca085 +#define clk_ufs_unipro_core_clk_src 0x179e80a9 +#define clk_usb30_mock_utmi_clk_src 0xa024a976 +#define clk_usb3_phy_aux_clk_src 0x15eec63c +#define clk_qspi_ref_clk_src 0xfe6b8e11 +#define clk_gcc_pcie_phy_0_reset 0x6bb4df33 +#define clk_gcc_usb3_phy_reset 0x03d559f1 +#define clk_gcc_usb3phy_phy_reset 0xb1a4f885 +#define clk_gcc_aggre1_ufs_axi_clk 0x873459d8 +#define clk_gcc_aggre1_ufs_axi_hw_ctl_clk 0x117a6f39 +#define clk_gcc_aggre1_usb3_axi_clk 0xc5c3fbe8 +#define clk_gcc_bimc_mss_q6_axi_clk 0x7437988f +#define clk_gcc_blsp1_ahb_clk 0x8caa5b4f +#define clk_gcc_blsp1_qup1_i2c_apps_clk 0xc303fae9 +#define clk_gcc_blsp1_qup1_spi_apps_clk 0x759a76b0 +#define clk_gcc_blsp1_qup2_i2c_apps_clk 0x1076f220 +#define clk_gcc_blsp1_qup2_spi_apps_clk 0x3e77d48f +#define clk_gcc_blsp1_qup3_i2c_apps_clk 0x9e25ac82 +#define clk_gcc_blsp1_qup3_spi_apps_clk 0xfb978880 +#define clk_gcc_blsp1_qup4_i2c_apps_clk 0xd7f40f6f +#define clk_gcc_blsp1_qup4_spi_apps_clk 0x80f8722f +#define clk_gcc_blsp1_qup5_i2c_apps_clk 0xacae5604 +#define clk_gcc_blsp1_qup5_spi_apps_clk 0xbf3e15d7 +#define clk_gcc_blsp1_qup6_i2c_apps_clk 0x5c6ad820 +#define clk_gcc_blsp1_qup6_spi_apps_clk 0x780d9f85 +#define clk_gcc_blsp1_uart1_apps_clk 0xc7c62f90 +#define clk_gcc_blsp1_uart2_apps_clk 0xf8a61c96 +#define clk_gcc_blsp1_uart3_apps_clk 0xc3298bd7 +#define clk_gcc_blsp2_ahb_clk 0x8f283c1d +#define clk_gcc_blsp2_qup1_i2c_apps_clk 0x9ace11dd +#define clk_gcc_blsp2_qup1_spi_apps_clk 0xa32604cc +#define clk_gcc_blsp2_qup2_i2c_apps_clk 0x1bf9a57e +#define clk_gcc_blsp2_qup2_spi_apps_clk 0xbf54ca6d +#define clk_gcc_blsp2_qup3_i2c_apps_clk 0x336d4170 +#define clk_gcc_blsp2_qup3_spi_apps_clk 0xc68509d6 +#define clk_gcc_blsp2_qup4_i2c_apps_clk 0xbd22539d +#define clk_gcc_blsp2_qup4_spi_apps_clk 0x01a72b93 +#define clk_gcc_blsp2_qup5_i2c_apps_clk 0xe2b2ce1d +#define clk_gcc_blsp2_qup5_spi_apps_clk 0xf40999cd +#define clk_gcc_blsp2_qup6_i2c_apps_clk 0x894bcea4 +#define clk_gcc_blsp2_qup6_spi_apps_clk 0xfe1bd34a +#define clk_gcc_blsp2_uart1_apps_clk 0x8c3512ff +#define clk_gcc_blsp2_uart2_apps_clk 0x1e1965a3 +#define clk_gcc_blsp2_uart3_apps_clk 0x382415ab +#define clk_gcc_boot_rom_ahb_clk 0xde2adeb1 +#define clk_gcc_bimc_gfx_clk 0x3edd69ad +#define clk_gcc_cfg_noc_usb3_axi_clk 0x9ea4c2d9 +#define clk_gcc_gp1_clk 0x057f7b69 +#define clk_gcc_gp2_clk 0x9bf83ffd +#define clk_gcc_gp3_clk 0xec6539ee +#define clk_gcc_gpu_bimc_gfx_clk 0x3909459b +#define clk_gcc_gpu_cfg_ahb_clk 0x72f20a57 +#define clk_gcc_gpu_iref_clk 0xfd82abad +#define clk_gcc_hmss_dvm_bus_clk 0x17cc8b53 +#define clk_gcc_hmss_rbcpr_clk 0x699183be +#define clk_hmss_gpll0_clk_src 0x17eb05d0 +#define clk_hmss_gpll4_clk_src 0x20456cae +#define clk_gcc_mmss_sys_noc_axi_clk 0x4467b15b +#define clk_gcc_mss_at_clk 0x1692c5aa +#define clk_nav_gcc_dbg_clk 0x2221c544 +#define clk_gcc_pcie_0_aux_clk 0x3d2e3ece +#define clk_gcc_pcie_0_cfg_ahb_clk 0x4dd325c3 +#define clk_gcc_pcie_0_mstr_axi_clk 0x3f85285b +#define clk_gcc_pcie_0_pipe_clk 0x4f37621e +#define clk_gcc_pcie_0_slv_axi_clk 0xd69638a1 +#define clk_gcc_pcie_phy_aux_clk 0x4746e74f +#define clk_gcc_pdm2_clk 0x99d55711 +#define clk_gcc_pdm_ahb_clk 0x365664f6 +#define clk_gcc_prng_ahb_clk 0x397e7eaa +#define clk_gcc_sdcc2_ahb_clk 0x23d5727f +#define clk_gcc_sdcc2_apps_clk 0x861b20ac +#define clk_gcc_sdcc4_ahb_clk 0x64f3e6a8 +#define clk_gcc_sdcc4_apps_clk 0xbf7c4dc8 +#define clk_gcc_tsif_ahb_clk 0x88d2822c +#define clk_gcc_tsif_ref_clk 0x8f1ed2c2 +#define clk_gcc_ufs_ahb_clk 0x1914bb84 +#define clk_gcc_ufs_axi_clk 0x47c743a7 +#define clk_gcc_ufs_axi_hw_ctl_clk 0x69385b45 +#define clk_gcc_ufs_ice_core_clk 0x310b0710 +#define clk_gcc_ufs_ice_core_hw_ctl_clk 0x84e15a5b +#define clk_gcc_ufs_phy_aux_clk 0x17acc8fb +#define clk_gcc_ufs_phy_aux_hw_ctl_clk 0x7dbdb2e2 +#define clk_gcc_ufs_rx_symbol_0_clk 0x7f43251c +#define clk_gcc_ufs_rx_symbol_1_clk 0x03182fde +#define clk_gcc_ufs_tx_symbol_0_clk 0x6a9f747a +#define clk_ufs_tx_symbol_0_clk 0xb3fcd0f7 +#define clk_ufs_rx_symbol_0_clk 0x17a0f1cd +#define clk_gcc_ufs_unipro_core_clk 0x2daf7fd2 +#define clk_gcc_ufs_unipro_core_hw_ctl_clk 0x4a4e0f3d +#define clk_gcc_usb30_master_clk 0xb3b4e2cb +#define clk_gcc_usb30_mock_utmi_clk 0xa800b65a +#define clk_gcc_usb30_sleep_clk 0xd0b65c92 +#define clk_gcc_usb3_phy_aux_clk 0x0d9a36e0 +#define clk_gcc_usb3_phy_pipe_clk 0xf279aff2 +#define clk_gcc_usb3_clkref_clk 0xb6cc8f00 +#define clk_gcc_hdmi_clkref_clk 0x4d4eec04 +#define clk_gcc_edp_clkref_clk 0xa8685c3f +#define clk_gcc_ufs_clkref_clk 0x92aa126f +#define clk_gcc_pcie_clkref_clk 0xa2e247fa +#define clk_gcc_rx2_qlink_clkref_clk 0xd0ba986d +#define clk_gcc_rx1_usb2_clkref_clk 0x53351d25 +#define clk_gcc_pcie_phy_reset 0x9bc3c959 +#define clk_gcc_pcie_phy_com_reset 0x8bf513e6 +#define clk_gcc_pcie_phy_nocsr_com_phy_reset 0x0c16a2da +#define clk_gcc_qusb2phy_prim_reset 0x07550fa1 +#define clk_gcc_qusb2phy_sec_reset 0x3f3a87d0 +#define clk_gcc_mmss_noc_cfg_ahb_clk 0xb41a9d99 +#define clk_gcc_dcc_ahb_clk 0xfa14a88c +#define clk_hlos1_vote_lpass_core_smmu_clk 0x3aaa1743 +#define clk_hlos1_vote_lpass_adsp_smmu_clk 0xc76f702f +#define clk_gcc_mss_cfg_ahb_clk 0x111cde81 +#define clk_gcc_mss_q6_bimc_axi_clk 0x67544d62 +#define clk_gcc_mss_mnoc_bimc_axi_clk 0xf665d03f +#define clk_gpll0_out_msscc 0x7d794829 +#define clk_gcc_mss_snoc_axi_clk 0x0e71de85 +#define clk_gcc_qspi_ref_clk 0x766a0f7c +#define clk_gcc_qspi_ahb_clk 0x96969dc8 +#define clk_gcc_debug_mux 0x8121ac15 + +/* clock_mmss controlled clocks */ +#define clk_mmsscc_xo 0x05e63704 +#define clk_mmsscc_gpll0 0xe900c515 +#define clk_mmsscc_gpll0_div 0x73892e05 +#define clk_mmpll0_pll 0x361e3cfd +#define clk_mmpll1_pll 0x198e426b +#define clk_mmpll3_pll 0x18c76899 +#define clk_mmpll4_pll 0x22c063c1 +#define clk_mmpll5_pll 0xa41e1936 +#define clk_mmpll6_pll 0xc56fb440 +#define clk_mmpll7_pll 0x3ac216af +#define clk_mmpll10_pll 0x2561263b +#define clk_mmpll0_pll_out 0x1e9e24a8 +#define clk_mmpll1_pll_out 0x5fa32257 +#define clk_mmpll3_pll_out 0x6eb6328f +#define clk_mmpll4_pll_out 0xfb21c2fd +#define clk_mmpll5_pll_out 0xcc1897bf +#define clk_mmpll6_pll_out 0xfb1060bd +#define clk_mmpll7_pll_out 0x767758ed +#define clk_mmpll10_pll_out 0x3c5668f3 +#define clk_ahb_clk_src 0x86f49203 +#define clk_csi0_clk_src 0x227e65bc +#define clk_vfe0_clk_src 0xa0c2bd8f +#define clk_vfe1_clk_src 0x4e357366 +#define clk_mdp_clk_src 0x6dc1f8f1 +#define clk_maxi_clk_src 0x52c09777 +#define clk_cpp_clk_src 0x8382f56d +#define clk_jpeg0_clk_src 0x9a0a0ac3 +#define clk_rot_clk_src 0xce49b56c +#define clk_video_core_clk_src 0x8be4c944 +#define clk_csi1_clk_src 0x6a2a6c36 +#define clk_csi2_clk_src 0x4113589f +#define clk_csi3_clk_src 0xfd934012 +#define clk_fd_core_clk_src 0xe4799ab7 +#define clk_ext_dp_phy_pll_vco 0x441b576b +#define clk_ext_dp_phy_pll_link 0xea12644c +#define clk_dp_link_clk_src 0x370d0626 +#define clk_dp_crypto_clk_src 0xf8faa811 +#define clk_dp_pixel_clk_src 0xf5dfbabf +#define clk_ext_extpclk_clk_src 0xe5b273af +#define clk_ext_pclk0_clk_src 0x087c1612 +#define clk_ext_pclk1_clk_src 0x8067c5a3 +#define clk_pclk0_clk_src 0xccac1f35 +#define clk_pclk1_clk_src 0x090f68ac +#define clk_video_subcore0_clk_src 0x88d79636 +#define clk_video_subcore1_clk_src 0x4966930c +#define clk_cci_clk_src 0x822f3d97 +#define clk_camss_gp0_clk_src 0x43b063e9 +#define clk_camss_gp1_clk_src 0xa3315f1b +#define clk_mclk0_clk_src 0x266b3853 +#define clk_mclk1_clk_src 0xa73cad0c +#define clk_mclk2_clk_src 0x42545468 +#define clk_mclk3_clk_src 0x2bfbb714 +#define clk_csiphy_clk_src 0x8cceb70a +#define clk_csi0phytimer_clk_src 0xc8a309be +#define clk_csi1phytimer_clk_src 0x7c0fe23a +#define clk_csi2phytimer_clk_src 0x62ffea9c +#define clk_ext_byte0_clk_src 0xfb32f31e +#define clk_ext_byte1_clk_src 0x585ef6d4 +#define clk_byte0_clk_src 0x75cc885b +#define clk_byte1_clk_src 0x63c2c955 +#define clk_dp_aux_clk_src 0x2b6e972b +#define clk_dp_gtc_clk_src 0xc5a86a42 +#define clk_esc0_clk_src 0xb41d7c38 +#define clk_esc1_clk_src 0x3b0afa42 +#define clk_extpclk_clk_src 0xb2c31abd +#define clk_hdmi_clk_src 0xb40aeea9 +#define clk_vsync_clk_src 0xecb43940 +#define clk_mmss_bimc_smmu_ahb_clk 0x4825baf4 +#define clk_mmss_bimc_smmu_axi_clk 0xc365ac39 +#define clk_mmss_snoc_dvm_axi_clk 0x2c159a11 +#define clk_mmss_camss_ahb_clk 0xa51f2c1d +#define clk_mmss_camss_cci_ahb_clk 0xfda8bb6a +#define clk_mmss_camss_cci_clk 0x71bb5c97 +#define clk_mmss_camss_cpp_ahb_clk 0xd5554f15 +#define clk_mmss_camss_cpp_clk 0x8e99ef57 +#define clk_mmss_camss_cpp_axi_clk 0xd84e390b +#define clk_mmss_camss_cpp_vbif_ahb_clk 0x1b33a88e +#define clk_mmss_camss_cphy_csid0_clk 0x56114361 +#define clk_mmss_camss_csi0_ahb_clk 0x2b58d241 +#define clk_mmss_camss_csi0_clk 0xccfe39ef +#define clk_mmss_camss_csi0pix_clk 0x9e26509d +#define clk_mmss_camss_csi0rdi_clk 0x01d5bf83 +#define clk_mmss_camss_cphy_csid1_clk 0x79fbcd8a +#define clk_mmss_camss_csi1_ahb_clk 0x7073244b +#define clk_mmss_camss_csi1_clk 0x3eeeaac0 +#define clk_mmss_camss_csi1pix_clk 0xf1375139 +#define clk_mmss_camss_csi1rdi_clk 0x43185024 +#define clk_mmss_camss_cphy_csid2_clk 0xf295e3ef +#define clk_mmss_camss_csi2_ahb_clk 0x681c1479 +#define clk_mmss_camss_csi2_clk 0x94524569 +#define clk_mmss_camss_csi2pix_clk 0xf4de617d +#define clk_mmss_camss_csi2rdi_clk 0x4bf01dc5 +#define clk_mmss_camss_cphy_csid3_clk 0x100188e9 +#define clk_mmss_camss_csi3_ahb_clk 0xfae7c29b +#define clk_mmss_camss_csi3_clk 0x55e4bbae +#define clk_mmss_camss_csi3pix_clk 0xc166a015 +#define clk_mmss_camss_csi3rdi_clk 0x6983a4cd +#define clk_mmss_camss_csi_vfe0_clk 0x3b30b798 +#define clk_mmss_camss_csi_vfe1_clk 0xfe729af7 +#define clk_mmss_camss_csiphy0_clk 0x96c81af8 +#define clk_mmss_camss_csiphy1_clk 0xee9ac2bb +#define clk_mmss_camss_csiphy2_clk 0x3365e70e +#define clk_mmss_fd_ahb_clk 0x4ff1da4d +#define clk_mmss_fd_core_clk 0x749e7eb0 +#define clk_mmss_fd_core_uar_clk 0x8ea480c5 +#define clk_mmss_camss_gp0_clk 0x3f7f6c87 +#define clk_mmss_camss_gp1_clk 0xdccdd730 +#define clk_mmss_camss_ispif_ahb_clk 0xbda4f0e3 +#define clk_mmss_camss_jpeg0_clk 0x4cc73b07 +#define clk_mmss_camss_jpeg0_vote_clk 0xc9efa6ac +#define clk_mmss_camss_jpeg0_dma_vote_clk 0x371ec109 +#define clk_mmss_camss_jpeg_ahb_clk 0xde1fece3 +#define clk_mmss_camss_jpeg_axi_clk 0x7534616b +#define clk_mmss_camss_mclk0_clk 0x056293a7 +#define clk_mmss_camss_mclk1_clk 0x96c7b69b +#define clk_mmss_camss_mclk2_clk 0x8820556e +#define clk_mmss_camss_mclk3_clk 0xf90ffb67 +#define clk_mmss_camss_micro_ahb_clk 0x6c6fd3c7 +#define clk_mmss_camss_csi0phytimer_clk 0x7a78864e +#define clk_mmss_camss_csi1phytimer_clk 0x6e6c1de5 +#define clk_mmss_camss_csi2phytimer_clk 0x0235e2de +#define clk_mmss_camss_top_ahb_clk 0x120618d6 +#define clk_mmss_camss_vfe0_ahb_clk 0x137bd0bd +#define clk_mmss_camss_vfe0_clk 0xead28288 +#define clk_mmss_camss_vfe0_stream_clk 0xa0428287 +#define clk_mmss_camss_vfe1_ahb_clk 0xac0154c0 +#define clk_mmss_camss_vfe1_clk 0xc216b14d +#define clk_mmss_camss_vfe1_stream_clk 0x745af3b6 +#define clk_mmss_camss_vfe_vbif_ahb_clk 0x0109a9c6 +#define clk_mmss_camss_vfe_vbif_axi_clk 0xe626d8a1 +#define clk_mmss_mdss_ahb_clk 0x85d37ab5 +#define clk_mmss_mdss_axi_clk 0xdf04fc1d +#define clk_mmss_mdss_byte0_clk 0x38105d25 +#define clk_mmss_mdss_byte0_intf_clk 0x38e5aa79 +#define clk_mmss_mdss_byte0_intf_div_clk 0x8604f181 +#define clk_mmss_mdss_byte1_clk 0xe0c21354 +#define clk_mmss_mdss_byte1_intf_clk 0xcf654d8e +#define clk_mmss_mdss_byte1_intf_div_clk 0xcdf334c5 +#define clk_mmss_mdss_dp_aux_clk 0x23125eb6 +#define clk_mmss_mdss_dp_crypto_clk 0x9a072d4e +#define clk_mmss_mdss_dp_link_clk 0x8dd302d1 +#define clk_mmss_mdss_dp_link_intf_clk 0x70e386e6 +#define clk_mmss_mdss_dp_pixel_clk 0xb707b765 +#define clk_mmss_mdss_dp_gtc_clk 0xb59c151a +#define clk_mmss_mdss_esc0_clk 0x5721ff83 +#define clk_mmss_mdss_esc1_clk 0xc3d0376b +#define clk_mmss_mdss_extpclk_clk 0x74d5a954 +#define clk_mmss_mdss_hdmi_clk 0x28460a6d +#define clk_mmss_mdss_hdmi_dp_ahb_clk 0x5448519f +#define clk_mmss_mdss_mdp_clk 0x43539b0e +#define clk_mmss_mdss_mdp_lut_clk 0x00627b2b +#define clk_mmss_mdss_pclk0_clk 0xcc0e909d +#define clk_mmss_mdss_pclk1_clk 0x850d9146 +#define clk_mmss_mdss_rot_clk 0xbb7e71c4 +#define clk_mmss_mdss_vsync_clk 0x629b36dc +#define clk_mmss_misc_ahb_clk 0xea30b0e7 +#define clk_mmss_misc_cxo_clk 0xe620cd80 +#define clk_mmss_mnoc_ahb_clk 0x49a394f4 +#define clk_mmss_mnoc_maxi_clk 0xd8b7278f +#define clk_mmss_video_subcore0_clk 0x23fae359 +#define clk_mmss_video_subcore1_clk 0x5213a0c7 +#define clk_mmss_video_ahb_clk 0x94334ae9 +#define clk_mmss_video_axi_clk 0xf3178ba5 +#define clk_mmss_video_core_clk 0x78f14c85 +#define clk_mmss_video_maxi_clk 0x1785ef88 +#define clk_mmss_vmem_ahb_clk 0x4b18955b +#define clk_mmss_vmem_maxi_clk 0xb6067889 +#define clk_mmss_debug_mux 0xe646ffda + +/* external multimedia clocks */ +#define clk_dsi0pll_byteclk_mux 0xecf2c434 +#define clk_dsi0pll_byteclk_src 0x6f6f740f +#define clk_dsi0pll_pclk_mux 0x6c9da335 +#define clk_dsi0pll_pclk_src 0x5efd85d4 +#define clk_dsi0pll_pclk_src_mux 0x84b14663 +#define clk_dsi0pll_post_bit_div 0xf46dcf27 +#define clk_dsi0pll_pll_out_div1 0xeda5b7fe +#define clk_dsi0pll_pll_out_div2 0x97fa476d +#define clk_dsi0pll_pll_out_div4 0x90a98ce0 +#define clk_dsi0pll_pll_out_div8 0x9d9d85cf +#define clk_dsi0pll_pll_out_mux 0x179c27ca +#define clk_dsi0pll_post_vco_mux 0xfaf9bd1f +#define clk_dsi0pll_post_vco_div1 0xabb50b2a +#define clk_dsi0pll_post_vco_div4 0xbe51c091 +#define clk_dsi0pll_bitclk_src 0x36c3c437 +#define clk_dsi0pll_vco_clk 0x15940d40 + +#define clk_dsi1pll_byteclk_mux 0x14e2f38f +#define clk_dsi1pll_byteclk_src 0x4b65c298 +#define clk_dsi1pll_pclk_mux 0x4c0518b5 +#define clk_dsi1pll_pclk_src 0xeddcd80e +#define clk_dsi1pll_pclk_src_mux 0x3651feb3 +#define clk_dsi1pll_post_bit_div 0x712f0260 +#define clk_dsi1pll_pll_out_div8 0x87628ddb +#define clk_dsi1pll_pll_out_div4 0x0d9a384b +#define clk_dsi1pll_pll_out_div2 0x0c9b5748 +#define clk_dsi1pll_pll_out_div1 0x3193164e +#define clk_dsi1pll_pll_out_mux 0x171bf8fd +#define clk_dsi1pll_post_vco_mux 0xc6a90d20 +#define clk_dsi1pll_post_vco_div1 0x6f47ca7d +#define clk_dsi1pll_post_vco_div4 0x90628974 +#define clk_dsi1pll_bitclk_src 0x13ab045b +#define clk_dsi1pll_vco_clk 0x99797b50 + +#define clk_dp_vco_clk 0xfcaaeec7 +#define clk_dp_link_2x_clk_divsel_five 0xcfe3f5dd +#define clk_vco_divsel_four_clk_src 0xe0da19c0 +#define clk_vco_divsel_two_clk_src 0xb5cfc6a8 +#define clk_vco_divided_clk_src_mux 0x3f8197c2 +#define clk_hdmi_vco_clk 0xbb7dc20d + +/* clock_gpu controlled clocks*/ +#define clk_gpucc_xo 0xc4e1a890 +#define clk_gpucc_gpll0 0x0db0e37f +#define clk_gfx3d_clk_src 0x917f76ef +#define clk_rbbmtimer_clk_src 0x17649ecc +#define clk_gfx3d_isense_clk_src 0xecc3eafa +#define clk_rbcpr_clk_src 0x2c2e9af2 +#define clk_gpu_debug_div_clk 0x75d6f53f +#define clk_gpucc_gfx3d_clk 0x95f01bd5 +#define clk_gpucc_rbbmtimer_clk 0x58a0a7ca +#define clk_gpucc_gfx3d_isense_clk 0xb2678e80 +#define clk_gpucc_cxo_clk 0x6532dcae +#define clk_gpucc_rbcpr_clk 0x7bd750e8 +#define clk_gpu_pll0_pll 0x0e61ab4d +#define clk_gpu_pll0_pll_out_even 0xb0ed5009 +#define clk_gpu_pll0_pll_out_odd 0x08c5a8a5 +#define clk_gpu_pll0_postdiv_clk 0x76c19f3c +#define clk_gpucc_mx_clk 0x1edbb879 +#define clk_gpucc_gcc_dbg_clk 0x9ae8cd3c +#define clk_gfxcc_dbg_clk 0x3ed47625 + +/* CPU clocks */ +#define clk_pwrcl_clk 0xc554130e +#define clk_perfcl_clk 0x58869997 +#define clk_sys_apcsaux_clk_gcc 0xf905e862 +#define clk_xo_ao 0x428c856d +#define clk_osm_clk_src 0xaabe68c3 +#define clk_cpu_debug_mux 0x3ae8bcb2 + +/* Audio External Clocks */ +#define clk_audio_ap_clk 0x9b5727cb +#define clk_audio_pmi_clk 0xcbfe416d +#define clk_audio_ap_clk2 0x454d1e91 + +/* GCC block resets */ +#define QUSB2PHY_PRIM_BCR 0 +#define QUSB2PHY_SEC_BCR 1 +#define BLSP1_BCR 2 +#define BLSP2_BCR 3 +#define BOOT_ROM_BCR 4 +#define PRNG_BCR 5 +#define UFS_BCR 6 +#define USB_30_BCR 7 +#define USB3_PHY_BCR 8 +#define USB3PHY_PHY_BCR 9 +#define PCIE_0_PHY_BCR 10 +#define PCIE_PHY_BCR 11 +#define PCIE_PHY_COM_BCR 12 +#define PCIE_PHY_NOCSR_COM_PHY_BCR 13 + +/* MMSS block resets */ +#define CAMSS_MICRO_BCR 0 + +#endif --- /dev/null 2019-10-24 16:47:25.704025805 +0200 +++ linux-4.4.115-fbx/arch/arm/boot/dts/include/dt-bindings/clock/msm-clocks-hwio-8998.h 2019-01-22 16:16:28.171288678 +0100 @@ -0,0 +1,395 @@ +/* Copyright (c) 2015-2017, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define CLKFLAG_NO_RATE_CACHE 0x00004000 + +#define FMAX_LOWER 0 +#define FMAX_LOW 1 +#define FMAX_NOM 2 +#define FMAX_TURBO 3 + +#define HALT_CHECK_DELAY 5 + +#define RPM_MISC_CLK_TYPE 0x306b6c63 +#define RPM_BUS_CLK_TYPE 0x316b6c63 +#define RPM_MEM_CLK_TYPE 0x326b6c63 +#define RPM_IPA_CLK_TYPE 0x617069 +#define RPM_CE_CLK_TYPE 0x6563 +#define RPM_AGGR_CLK_TYPE 0x72676761 +#define RPM_SMD_KEY_ENABLE 0x62616E45 +#define RPM_MMAXI_CLK_TYPE 0x69786d6d + +#define CXO_CLK_SRC_ID 0x0 +#define QDSS_CLK_ID 0x1 +#define SNOC_CLK_ID 0x1 +#define CNOC_CLK_ID 0x2 +#define CNOC_PERIPH_CLK_ID 0x0 +#define BIMC_CLK_ID 0x0 +#define IPA_CLK_ID 0x0 +#define CE1_CLK_ID 0x0 +#define RF_CLK1_ID 0x4 +#define RF_CLK2_ID 0x5 +#define RF_CLK3_ID 0x6 +#define LN_BB_CLK1_ID 0x1 +#define LN_BB_CLK2_ID 0x2 +#define LN_BB_CLK3_ID 0x3 +#define DIV_CLK1_ID 0xb +#define DIV_CLK2_ID 0xc +#define DIV_CLK3_ID 0xd +#define RF_CLK1_PIN_ID 0x4 +#define RF_CLK2_PIN_ID 0x5 +#define RF_CLK3_PIN_ID 0x6 +#define LN_BB_CLK1_PIN_ID 0x1 +#define LN_BB_CLK2_PIN_ID 0x2 +#define LN_BB_CLK3_PIN_ID 0x3 +#define AGGR1_NOC_ID 0x1 +#define AGGR2_NOC_ID 0x2 +#define MMSSNOC_AXI_CLK_ID 0x0 + +#define APCS_COMMON_LMH_CMD_RCGR 0x0012C + +#define GCC_APCS_GPLL_ENA_VOTE 0x52000 +#define GCC_APCS_CLOCK_BRANCH_ENA_VOTE 0x52004 +#define GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1 0x5200C +#define PLLTEST_PAD_CFG 0x6200C +#define GCC_XO_DIV4_CBCR 0x43008 +#define CLOCK_FRQ_MEASURE_CTL 0x62004 +#define CLOCK_FRQ_MEASURE_STATUS 0x62008 +#define GCC_GPLL0_MODE 0x00000 +#define GCC_GPLL4_MODE 0x77000 +#define GCC_USB30_MASTER_CMD_RCGR 0x0F014 +#define GCC_PCIE_AUX_CMD_RCGR 0x6C000 +#define GCC_UFS_AXI_CMD_RCGR 0x75018 +#define GCC_BLSP1_QUP1_I2C_APPS_CMD_RCGR 0x19020 +#define GCC_BLSP1_QUP1_SPI_APPS_CMD_RCGR 0x1900C +#define GCC_BLSP1_QUP2_I2C_APPS_CMD_RCGR 0x1B020 +#define GCC_BLSP1_QUP2_SPI_APPS_CMD_RCGR 0x1B00C +#define GCC_BLSP1_QUP3_I2C_APPS_CMD_RCGR 0x1D020 +#define GCC_BLSP1_QUP3_SPI_APPS_CMD_RCGR 0x1D00C +#define GCC_BLSP1_QUP4_I2C_APPS_CMD_RCGR 0x1F020 +#define GCC_BLSP1_QUP4_SPI_APPS_CMD_RCGR 0x1F00C +#define GCC_BLSP1_QUP5_I2C_APPS_CMD_RCGR 0x21020 +#define GCC_BLSP1_QUP5_SPI_APPS_CMD_RCGR 0x2100C +#define GCC_BLSP1_QUP6_I2C_APPS_CMD_RCGR 0x23020 +#define GCC_BLSP1_QUP6_SPI_APPS_CMD_RCGR 0x2300C +#define GCC_BLSP1_UART1_APPS_CMD_RCGR 0x1A00C +#define GCC_BLSP1_UART2_APPS_CMD_RCGR 0x1C00C +#define GCC_BLSP1_UART3_APPS_CMD_RCGR 0x1E00C +#define GCC_BLSP2_QUP1_I2C_APPS_CMD_RCGR 0x26020 +#define GCC_BLSP2_QUP2_I2C_APPS_CMD_RCGR 0x28020 +#define GCC_BLSP2_QUP3_I2C_APPS_CMD_RCGR 0x2A020 +#define GCC_BLSP2_QUP4_I2C_APPS_CMD_RCGR 0x2C020 +#define GCC_BLSP2_QUP5_I2C_APPS_CMD_RCGR 0x2E020 +#define GCC_BLSP2_QUP6_I2C_APPS_CMD_RCGR 0x30020 +#define GCC_BLSP2_QUP1_SPI_APPS_CMD_RCGR 0x2600C +#define GCC_BLSP2_QUP2_SPI_APPS_CMD_RCGR 0x2800C +#define GCC_BLSP2_QUP3_SPI_APPS_CMD_RCGR 0x2A00C +#define GCC_BLSP2_QUP4_SPI_APPS_CMD_RCGR 0x2C00C +#define GCC_BLSP2_QUP5_SPI_APPS_CMD_RCGR 0x2E00C +#define GCC_BLSP2_QUP6_SPI_APPS_CMD_RCGR 0x3000C +#define GCC_BLSP2_UART1_APPS_CMD_RCGR 0x2700C +#define GCC_BLSP2_UART2_APPS_CMD_RCGR 0x2900C +#define GCC_BLSP2_UART3_APPS_CMD_RCGR 0x2B00C +#define GCC_GP1_CMD_RCGR 0x64004 +#define GCC_GP2_CMD_RCGR 0x65004 +#define GCC_GP3_CMD_RCGR 0x66004 +#define GCC_HMSS_RBCPR_CMD_RCGR 0x48044 +#define GCC_PDM2_CMD_RCGR 0x33010 +#define GCC_SDCC2_APPS_CMD_RCGR 0x14010 +#define GCC_SDCC4_APPS_CMD_RCGR 0x16010 +#define GCC_TSIF_REF_CMD_RCGR 0x36010 +#define GCC_UFS_ICE_CORE_CMD_RCGR 0x76010 +#define GCC_UFS_PHY_AUX_CMD_RCGR 0x76044 +#define GCC_UFS_UNIPRO_CORE_CMD_RCGR 0x76028 +#define GCC_USB30_MOCK_UTMI_CMD_RCGR 0x0F028 +#define GCC_USB3_PHY_AUX_CMD_RCGR 0x5000C +#define GCC_QSPI_REF_CMD_RCGR 0x9000C +#define GCC_PCIE_0_PHY_BCR 0x6C01C +#define GCC_HDMI_CLKREF_EN 0x88000 +#define GCC_UFS_CLKREF_EN 0x88004 +#define GCC_USB3_CLKREF_EN 0x88008 +#define GCC_PCIE_CLKREF_EN 0x8800C +#define GCC_RX1_USB2_CLKREF_EN 0x88014 +#define GCC_USB3_PHY_BCR 0x50020 +#define GCC_AGGRE1_NOC_XO_CBCR 0x8202C +#define GCC_AGGRE1_UFS_AXI_CBCR 0x82028 +#define GCC_AGGRE1_USB3_AXI_CBCR 0x82024 +#define GCC_BIMC_MSS_Q6_AXI_CBCR 0x4401C +#define GCC_BLSP1_AHB_CBCR 0x17004 +#define GCC_BLSP1_BCR 0x17000 +#define GCC_BLSP1_QUP1_SPI_APPS_CBCR 0x19004 +#define GCC_BLSP1_QUP1_I2C_APPS_CBCR 0x19008 +#define GCC_BLSP1_QUP2_SPI_APPS_CBCR 0x1B004 +#define GCC_BLSP1_QUP2_I2C_APPS_CBCR 0x1B008 +#define GCC_BLSP1_QUP3_SPI_APPS_CBCR 0x1D004 +#define GCC_BLSP1_QUP3_I2C_APPS_CBCR 0x1D008 +#define GCC_BLSP1_QUP4_SPI_APPS_CBCR 0x1F004 +#define GCC_BLSP1_QUP4_I2C_APPS_CBCR 0x1F008 +#define GCC_BLSP1_QUP5_SPI_APPS_CBCR 0x21004 +#define GCC_BLSP1_QUP5_I2C_APPS_CBCR 0x21008 +#define GCC_BLSP1_QUP6_SPI_APPS_CBCR 0x23004 +#define GCC_BLSP1_QUP6_I2C_APPS_CBCR 0x23008 +#define GCC_BLSP1_UART1_APPS_CBCR 0x1A004 +#define GCC_BLSP1_UART2_APPS_CBCR 0x1C004 +#define GCC_BLSP1_UART3_APPS_CBCR 0x1E004 +#define GCC_BLSP2_AHB_CBCR 0x25004 +#define GCC_BLSP2_BCR 0x25000 +#define GCC_BLSP2_QUP1_SPI_APPS_CBCR 0x26004 +#define GCC_BLSP2_QUP1_I2C_APPS_CBCR 0x26008 +#define GCC_BLSP2_QUP2_I2C_APPS_CBCR 0x28008 +#define GCC_BLSP2_QUP2_SPI_APPS_CBCR 0x28004 +#define GCC_BLSP2_QUP3_SPI_APPS_CBCR 0x2A004 +#define GCC_BLSP2_QUP3_I2C_APPS_CBCR 0x2A008 +#define GCC_BLSP2_QUP4_SPI_APPS_CBCR 0x2C004 +#define GCC_BLSP2_QUP4_I2C_APPS_CBCR 0x2C008 +#define GCC_BLSP2_QUP5_SPI_APPS_CBCR 0x2E004 +#define GCC_BLSP2_QUP5_I2C_APPS_CBCR 0x2E008 +#define GCC_BLSP2_QUP6_SPI_APPS_CBCR 0x30004 +#define GCC_BLSP2_QUP6_I2C_APPS_CBCR 0x30008 +#define GCC_BLSP2_UART1_APPS_CBCR 0x27004 +#define GCC_BLSP2_UART2_APPS_CBCR 0x29004 +#define GCC_BLSP2_UART3_APPS_CBCR 0x2B004 +#define GCC_BOOT_ROM_AHB_CBCR 0x38004 +#define GCC_BOOT_ROM_BCR 0x38000 +#define GCC_CFG_NOC_USB3_AXI_CBCR 0x05018 +#define GCC_BIMC_GFX_CBCR 0x46040 +#define GCC_GP1_CBCR 0x64000 +#define GCC_GP2_CBCR 0x65000 +#define GCC_GP3_CBCR 0x66000 +#define GCC_GPU_BIMC_GFX_CBCR 0x71010 +#define GCC_GPU_CFG_AHB_CBCR 0x71004 +#define GCC_GPU_IREF_EN 0x88010 +#define GCC_HMSS_DVM_BUS_CBCR 0x4808C +#define GCC_HMSS_RBCPR_CBCR 0x48008 +#define GCC_MMSS_SYS_NOC_AXI_CBCR 0x09000 +#define GCC_MMSS_NOC_CFG_AHB_CBCR 0x09004 +#define GCC_PCIE_0_SLV_AXI_CBCR 0x6B008 +#define GCC_PCIE_0_MSTR_AXI_CBCR 0x6B00C +#define GCC_PCIE_0_CFG_AHB_CBCR 0x6B010 +#define GCC_PCIE_0_AUX_CBCR 0x6B014 +#define GCC_PCIE_0_PIPE_CBCR 0x6B018 +#define GCC_PCIE_PHY_AUX_CBCR 0x6F004 +#define GCC_PCIE_PHY_BCR 0x6F000 +#define GCC_PCIE_PHY_COM_BCR 0x6F014 +#define GCC_PCIE_PHY_NOCSR_COM_PHY_BCR 0x6F00C +#define GCC_QUSB2PHY_PRIM_BCR 0x12000 +#define GCC_QUSB2PHY_SEC_BCR 0x12004 +#define GCC_PDM2_CBCR 0x3300C +#define GCC_PDM_AHB_CBCR 0x33004 +#define GCC_PRNG_AHB_CBCR 0x34004 +#define GCC_PRNG_BCR 0x34000 +#define GCC_SDCC2_APPS_CBCR 0x14004 +#define GCC_SDCC2_AHB_CBCR 0x14008 +#define GCC_SDCC4_APPS_CBCR 0x16004 +#define GCC_SDCC4_AHB_CBCR 0x16008 +#define GCC_TSIF_AHB_CBCR 0x36004 +#define GCC_TSIF_REF_CBCR 0x36008 +#define GCC_UFS_AXI_CBCR 0x75008 +#define GCC_UFS_BCR 0x75000 +#define GCC_UFS_AHB_CBCR 0x7500C +#define GCC_UFS_TX_SYMBOL_0_CBCR 0x75010 +#define GCC_UFS_RX_SYMBOL_0_CBCR 0x75014 +#define GCC_UFS_RX_SYMBOL_1_CBCR 0x7605C +#define GCC_UFS_UNIPRO_CORE_CBCR 0x76008 +#define GCC_UFS_ICE_CORE_CBCR 0x7600C +#define GCC_UFS_PHY_AUX_CBCR 0x76040 +#define GCC_USB30_MASTER_CBCR 0x0F008 +#define GCC_USB30_SLEEP_CBCR 0x0F00C +#define GCC_USB30_MOCK_UTMI_CBCR 0x0F010 +#define GCC_USB_30_BCR 0x0F000 +#define GCC_USB3_PHY_AUX_CBCR 0x50000 +#define GCC_USB3_PHY_PIPE_CBCR 0x50004 +#define GCC_USB3PHY_PHY_BCR 0x50024 +#define GCC_APCS_CLOCK_SLEEP_ENA_VOTE 0x52008 +#define GCC_MSS_CFG_AHB_CBCR 0x8A000 +#define GCC_MSS_Q6_BIMC_AXI_CBCR 0x8A040 +#define GCC_MSS_MNOC_BIMC_AXI_CBCR 0x8A004 +#define GCC_MSS_SNOC_AXI_CBCR 0x8A03C +#define GCC_HMSS_GPLL0_CMD_RCGR 0x4805C +#define GCC_MSS_CFG_AHB_CBCR 0x8A000 +#define GCC_MSS_Q6_BIMC_AXI_CBCR 0x8A040 +#define GCC_MSS_MNOC_BIMC_AXI_CBCR 0x8A004 +#define GCC_MSS_SNOC_AXI_CBCR 0x8A03C +#define GCC_DCC_AHB_CBCR 0x84004 +#define GCC_HLOS1_VOTE_LPASS_CORE_SMMU_CBCR 0x7D010 +#define GCC_HLOS1_VOTE_LPASS_ADSP_SMMU_CBCR 0x7D014 +#define GCC_QSPI_AHB_CBCR 0x90004 +#define GCC_QSPI_REF_CBCR 0x90008 +#define GCC_MMSS_MISC 0x0902C +#define GCC_GPU_MISC 0x71028 + +#define GPUCC_GPU_PLL0_PLL_MODE 0x00000 +#define GPUCC_GPU_PLL0_USER_CTL_MODE 0x0000C +#define GPUCC_GFX3D_CMD_RCGR 0x01070 +#define GPUCC_RBBMTIMER_CMD_RCGR 0x010B0 +#define GPUCC_GFX3D_ISENSE_CMD_RCGR 0x01100 +#define GPUCC_RBCPR_CMD_RCGR 0x01030 +#define GPUCC_GFX3D_CBCR 0x01098 +#define GPUCC_RBBMTIMER_CBCR 0x010D0 +#define GPUCC_GFX3D_ISENSE_CBCR 0x01124 +#define GPUCC_CXO_CBCR 0x01020 +#define GPUCC_RBCPR_CBCR 0x01054 +#define GPU_GX_BCR 0x01090 +#define GPUCC_GX_DOMAIN_MISC 0x00130 +#define GPUCC_GPU_DD_WRAP_CTRL 0x00430 +#define GPUCC_DEBUG_CLK_CTL 0x00120 + +#define MMSS_PLL_VOTE_APCS 0x001E0 +#define MMSS_MMPLL0_PLL_MODE 0x0C000 +#define MMSS_MMPLL1_PLL_MODE 0x0C050 +#define MMSS_MMPLL3_PLL_MODE 0x00000 +#define MMSS_MMPLL4_PLL_MODE 0x00050 +#define MMSS_MMPLL5_PLL_MODE 0x000A0 +#define MMSS_MMPLL6_PLL_MODE 0x000F0 +#define MMSS_MMPLL7_PLL_MODE 0x00140 +#define MMSS_MMPLL10_PLL_MODE 0x00190 +#define MMSS_AHB_CMD_RCGR 0x05000 +#define MMSS_CSI0_CMD_RCGR 0x03090 +#define MMSS_VFE0_CMD_RCGR 0x03600 +#define MMSS_VFE1_CMD_RCGR 0x03620 +#define MMSS_MDP_CMD_RCGR 0x02040 +#define MMSS_MAXI_CMD_RCGR 0x0F020 +#define MMSS_CPP_CMD_RCGR 0x03640 +#define MMSS_JPEG0_CMD_RCGR 0x03500 +#define MMSS_ROT_CMD_RCGR 0x021A0 +#define MMSS_VIDEO_CORE_CMD_RCGR 0x01000 +#define MMSS_CSI1_CMD_RCGR 0x03100 +#define MMSS_CSI2_CMD_RCGR 0x03160 +#define MMSS_CSI3_CMD_RCGR 0x031C0 +#define MMSS_FD_CORE_CMD_RCGR 0x03B00 +#define MMSS_BYTE0_CMD_RCGR 0x02120 +#define MMSS_BYTE1_CMD_RCGR 0x02140 +#define MMSS_PCLK0_CMD_RCGR 0x02000 +#define MMSS_PCLK1_CMD_RCGR 0x02020 +#define MMSS_VIDEO_SUBCORE0_CMD_RCGR 0x01060 +#define MMSS_VIDEO_SUBCORE1_CMD_RCGR 0x01080 +#define MMSS_CSIPHY_CMD_RCGR 0x03800 +#define MMSS_CCI_CMD_RCGR 0x03300 +#define MMSS_CAMSS_GP0_CMD_RCGR 0x03420 +#define MMSS_CAMSS_GP1_CMD_RCGR 0x03450 +#define MMSS_MCLK0_CMD_RCGR 0x03360 +#define MMSS_MCLK1_CMD_RCGR 0x03390 +#define MMSS_MCLK2_CMD_RCGR 0x033C0 +#define MMSS_MCLK3_CMD_RCGR 0x033F0 +#define MMSS_CAMSS_CSI2PHYTIMER_CBCR 0x03084 +#define MMSS_CSI0PHYTIMER_CMD_RCGR 0x03000 +#define MMSS_CSI1PHYTIMER_CMD_RCGR 0x03030 +#define MMSS_CSI2PHYTIMER_CMD_RCGR 0x03060 +#define MMSS_DP_GTC_CMD_RCGR 0x02280 +#define MMSS_ESC0_CMD_RCGR 0x02160 +#define MMSS_ESC1_CMD_RCGR 0x02180 +#define MMSS_EXTPCLK_CMD_RCGR 0x02060 +#define MMSS_HDMI_CMD_RCGR 0x02100 +#define MMSS_VSYNC_CMD_RCGR 0x02080 +#define MMSS_BIMC_SMMU_AHB_CBCR 0x0E004 +#define MMSS_BIMC_SMMU_AXI_CBCR 0x0E008 +#define MMSS_SNOC_DVM_AXI_CBCR 0x0E040 +#define MMSS_CAMSS_AHB_CBCR 0x0348C +#define MMSS_CAMSS_CCI_AHB_CBCR 0x03348 +#define MMSS_CAMSS_CCI_CBCR 0x03344 +#define MMSS_CAMSS_CPP_AHB_CBCR 0x036B4 +#define MMSS_CAMSS_CPP_CBCR 0x036B0 +#define MMSS_CAMSS_CPP_AXI_CBCR 0x036C4 +#define MMSS_CAMSS_CPP_VBIF_AHB_CBCR 0x036C8 +#define MMSS_CAMSS_CPHY_CSID0_CBCR 0x03730 +#define MMSS_CAMSS_CSI0_AHB_CBCR 0x030BC +#define MMSS_CAMSS_CSI0_CBCR 0x030B4 +#define MMSS_CAMSS_CSI0PIX_CBCR 0x030E4 +#define MMSS_CAMSS_CSI0RDI_CBCR 0x030D4 +#define MMSS_CAMSS_CPHY_CSID1_CBCR 0x03734 +#define MMSS_CAMSS_CSI1_AHB_CBCR 0x03128 +#define MMSS_CAMSS_CSI1_CBCR 0x03124 +#define MMSS_CAMSS_CSI1PIX_CBCR 0x03154 +#define MMSS_CAMSS_CSI1RDI_CBCR 0x03144 +#define MMSS_CAMSS_CPHY_CSID2_CBCR 0x03738 +#define MMSS_CAMSS_CSI2_AHB_CBCR 0x03188 +#define MMSS_CAMSS_CSI2_CBCR 0x03184 +#define MMSS_CAMSS_CSI2PIX_CBCR 0x031B4 +#define MMSS_CAMSS_CSI2RDI_CBCR 0x031A4 +#define MMSS_CAMSS_CPHY_CSID3_CBCR 0x0373C +#define MMSS_CAMSS_CSI3_AHB_CBCR 0x031E8 +#define MMSS_CAMSS_CSI3_CBCR 0x031E4 +#define MMSS_CAMSS_CSI3PIX_CBCR 0x03214 +#define MMSS_CAMSS_CSI3RDI_CBCR 0x03204 +#define MMSS_CAMSS_CSI_VFE0_CBCR 0x03704 +#define MMSS_CAMSS_CSI_VFE1_CBCR 0x03714 +#define MMSS_CAMSS_CSIPHY0_CBCR 0x03740 +#define MMSS_CAMSS_CSIPHY1_CBCR 0x03744 +#define MMSS_CAMSS_CSIPHY2_CBCR 0x03748 +#define MMSS_FD_AHB_CBCR 0x03B74 +#define MMSS_FD_CORE_CBCR 0x03B68 +#define MMSS_FD_CORE_UAR_CBCR 0x03B6C +#define MMSS_CAMSS_GP0_CBCR 0x03444 +#define MMSS_CAMSS_GP1_CBCR 0x03474 +#define MMSS_CAMSS_ISPIF_AHB_CBCR 0x03224 +#define MMSS_CAMSS_JPEG0_CBCR 0x035A8 +#define MMSS_CAMSS_JPEG_AHB_CBCR 0x035B4 +#define MMSS_CAMSS_JPEG_AXI_CBCR 0x035B8 +#define MMSS_CAMSS_MCLK0_CBCR 0x03384 +#define MMSS_CAMSS_MCLK1_CBCR 0x033B4 +#define MMSS_CAMSS_MCLK2_CBCR 0x033E4 +#define MMSS_CAMSS_MCLK3_CBCR 0x03414 +#define MMSS_CAMSS_MICRO_AHB_CBCR 0x03494 +#define MMSS_CAMSS_CSI0PHYTIMER_CBCR 0x03024 +#define MMSS_CAMSS_CSI1PHYTIMER_CBCR 0x03054 +#define MMSS_CSI2PHYTIMER_CMD_RCGR 0x03060 +#define MMSS_CAMSS_TOP_AHB_CBCR 0x03484 +#define MMSS_CAMSS_VFE0_AHB_CBCR 0x03668 +#define MMSS_CAMSS_VFE0_CBCR 0x036A8 +#define MMSS_CAMSS_VFE0_STREAM_CBCR 0x03720 +#define MMSS_CAMSS_VFE1_AHB_CBCR 0x03678 +#define MMSS_CAMSS_VFE1_CBCR 0x036AC +#define MMSS_CAMSS_VFE1_STREAM_CBCR 0x03724 +#define MMSS_CAMSS_VFE_VBIF_AHB_CBCR 0x036B8 +#define MMSS_CAMSS_VFE_VBIF_AXI_CBCR 0x036BC +#define MMSS_MDSS_AHB_CBCR 0x02308 +#define MMSS_MDSS_AXI_CBCR 0x02310 +#define MMSS_MDSS_BYTE0_CBCR 0x0233C +#define MMSS_MDSS_BYTE0_INTF_CBCR 0x02374 +#define MMSS_MDSS_BYTE0_INTF_DIV 0x0237C +#define MMSS_MDSS_BYTE1_CBCR 0x02340 +#define MMSS_MDSS_BYTE1_INTF_CBCR 0x02378 +#define MMSS_MDSS_BYTE1_INTF_DIV 0x02380 +#define MMSS_MDSS_DP_AUX_CBCR 0x02364 +#define MMSS_MDSS_DP_CRYPTO_CBCR 0x0235C +#define MMSS_MDSS_DP_GTC_CBCR 0x02368 +#define MMSS_MDSS_DP_LINK_CBCR 0x02354 +#define MMSS_MDSS_DP_LINK_INTF_CBCR 0x02358 +#define MMSS_MDSS_DP_PIXEL_CBCR 0x02360 +#define MMSS_MDSS_ESC0_CBCR 0x02344 +#define MMSS_MDSS_ESC1_CBCR 0x02348 +#define MMSS_MDSS_EXTPCLK_CBCR 0x02324 +#define MMSS_MDSS_HDMI_CBCR 0x02338 +#define MMSS_MDSS_HDMI_DP_AHB_CBCR 0x0230C +#define MMSS_MDSS_MDP_CBCR 0x0231C +#define MMSS_MDSS_MDP_LUT_CBCR 0x02320 +#define MMSS_MDSS_PCLK0_CBCR 0x02314 +#define MMSS_MDSS_PCLK1_CBCR 0x02318 +#define MMSS_MDSS_ROT_CBCR 0x02350 +#define MMSS_MDSS_VSYNC_CBCR 0x02328 +#define MMSS_MISC_AHB_CBCR 0x00328 +#define MMSS_MISC_CXO_CBCR 0x00324 +#define MMSS_MNOC_AHB_CBCR 0x05024 +#define MMSS_MNOC_MAXI_CBCR 0x0F004 +#define MMSS_VIDEO_SUBCORE0_CBCR 0x01048 +#define MMSS_VIDEO_SUBCORE1_CBCR 0x0104C +#define MMSS_VIDEO_AHB_CBCR 0x01030 +#define MMSS_VIDEO_AXI_CBCR 0x01034 +#define MMSS_VIDEO_CORE_CBCR 0x01028 +#define MMSS_VIDEO_MAXI_CBCR 0x01038 +#define MMSS_VMEM_AHB_CBCR 0x0F068 +#define MMSS_VMEM_MAXI_CBCR 0x0F064 +#define MMSS_DP_AUX_CMD_RCGR 0x02260 +#define MMSS_DP_CRYPTO_CMD_RCGR 0x02220 +#define MMSS_DP_LINK_CMD_RCGR 0x02200 +#define MMSS_DP_PIXEL_CMD_RCGR 0x02240 +#define MMSS_DEBUG_CLK_CTL 0x00900 diff -Nruw linux-4.4.115-fbx/arch/arm/boot/dts/include/dt-bindings/msm./msm-bus-ids.h linux-4.4.115-fbx/arch/arm/boot/dts/include/dt-bindings/msm/msm-bus-ids.h --- linux-4.4.115-fbx/arch/arm/boot/dts/include/dt-bindings/msm./msm-bus-ids.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-4.4.115-fbx/arch/arm/boot/dts/include/dt-bindings/msm/msm-bus-ids.h 2019-01-22 16:16:28.179288750 +0100 @@ -0,0 +1,887 @@ +/* Copyright (c) 2014-2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __MSM_BUS_IDS_H +#define __MSM_BUS_IDS_H + +/* Aggregation types */ +#define AGG_SCHEME_NONE 0 +#define AGG_SCHEME_LEG 1 +#define AGG_SCHEME_1 2 + +/* Topology related enums */ +#define MSM_BUS_FAB_DEFAULT 0 +#define MSM_BUS_FAB_APPSS 0 +#define MSM_BUS_FAB_SYSTEM 1024 +#define MSM_BUS_FAB_MMSS 2048 +#define MSM_BUS_FAB_SYSTEM_FPB 3072 +#define MSM_BUS_FAB_CPSS_FPB 4096 + +#define MSM_BUS_FAB_BIMC 0 +#define MSM_BUS_FAB_SYS_NOC 1024 +#define MSM_BUS_FAB_MMSS_NOC 2048 +#define MSM_BUS_FAB_OCMEM_NOC 3072 +#define MSM_BUS_FAB_PERIPH_NOC 4096 +#define MSM_BUS_FAB_CONFIG_NOC 5120 +#define MSM_BUS_FAB_OCMEM_VNOC 6144 +#define MSM_BUS_FAB_MMSS_AHB 2049 +#define MSM_BUS_FAB_A0_NOC 6145 +#define MSM_BUS_FAB_A1_NOC 6146 +#define MSM_BUS_FAB_A2_NOC 6147 +#define MSM_BUS_FAB_GNOC 6148 +#define MSM_BUS_FAB_CR_VIRT 6149 + +#define MSM_BUS_MASTER_FIRST 1 +#define MSM_BUS_MASTER_AMPSS_M0 1 +#define MSM_BUS_MASTER_AMPSS_M1 2 +#define MSM_BUS_APPSS_MASTER_FAB_MMSS 3 +#define MSM_BUS_APPSS_MASTER_FAB_SYSTEM 4 +#define MSM_BUS_SYSTEM_MASTER_FAB_APPSS 5 +#define MSM_BUS_MASTER_SPS 6 +#define MSM_BUS_MASTER_ADM_PORT0 7 +#define MSM_BUS_MASTER_ADM_PORT1 8 +#define MSM_BUS_SYSTEM_MASTER_ADM1_PORT0 9 +#define MSM_BUS_MASTER_ADM1_PORT1 10 +#define MSM_BUS_MASTER_LPASS_PROC 11 +#define MSM_BUS_MASTER_MSS_PROCI 12 +#define MSM_BUS_MASTER_MSS_PROCD 13 +#define MSM_BUS_MASTER_MSS_MDM_PORT0 14 +#define MSM_BUS_MASTER_LPASS 15 +#define MSM_BUS_SYSTEM_MASTER_CPSS_FPB 16 +#define MSM_BUS_SYSTEM_MASTER_SYSTEM_FPB 17 +#define MSM_BUS_SYSTEM_MASTER_MMSS_FPB 18 +#define MSM_BUS_MASTER_ADM1_CI 19 +#define MSM_BUS_MASTER_ADM0_CI 20 +#define MSM_BUS_MASTER_MSS_MDM_PORT1 21 +#define MSM_BUS_MASTER_MDP_PORT0 22 +#define MSM_BUS_MASTER_MDP_PORT1 23 +#define MSM_BUS_MMSS_MASTER_ADM1_PORT0 24 +#define MSM_BUS_MASTER_ROTATOR 25 +#define MSM_BUS_MASTER_GRAPHICS_3D 26 +#define MSM_BUS_MASTER_JPEG_DEC 27 +#define MSM_BUS_MASTER_GRAPHICS_2D_CORE0 28 +#define MSM_BUS_MASTER_VFE 29 +#define MSM_BUS_MASTER_VFE0 MSM_BUS_MASTER_VFE +#define MSM_BUS_MASTER_VPE 30 +#define MSM_BUS_MASTER_JPEG_ENC 31 +#define MSM_BUS_MASTER_GRAPHICS_2D_CORE1 32 +#define MSM_BUS_MMSS_MASTER_APPS_FAB 33 +#define MSM_BUS_MASTER_HD_CODEC_PORT0 34 +#define MSM_BUS_MASTER_HD_CODEC_PORT1 35 +#define MSM_BUS_MASTER_SPDM 36 +#define MSM_BUS_MASTER_RPM 37 +#define MSM_BUS_MASTER_MSS 38 +#define MSM_BUS_MASTER_RIVA 39 +#define MSM_BUS_MASTER_SNOC_VMEM 40 +#define MSM_BUS_MASTER_MSS_SW_PROC 41 +#define MSM_BUS_MASTER_MSS_FW_PROC 42 +#define MSM_BUS_MASTER_HMSS 43 +#define MSM_BUS_MASTER_GSS_NAV 44 +#define MSM_BUS_MASTER_PCIE 45 +#define MSM_BUS_MASTER_SATA 46 +#define MSM_BUS_MASTER_CRYPTO 47 +#define MSM_BUS_MASTER_VIDEO_CAP 48 +#define MSM_BUS_MASTER_GRAPHICS_3D_PORT1 49 +#define MSM_BUS_MASTER_VIDEO_ENC 50 +#define MSM_BUS_MASTER_VIDEO_DEC 51 +#define MSM_BUS_MASTER_LPASS_AHB 52 +#define MSM_BUS_MASTER_QDSS_BAM 53 +#define MSM_BUS_MASTER_SNOC_CFG 54 +#define MSM_BUS_MASTER_CRYPTO_CORE0 55 +#define MSM_BUS_MASTER_CRYPTO_CORE1 56 +#define MSM_BUS_MASTER_MSS_NAV 57 +#define MSM_BUS_MASTER_OCMEM_DMA 58 +#define MSM_BUS_MASTER_WCSS 59 +#define MSM_BUS_MASTER_QDSS_ETR 60 +#define MSM_BUS_MASTER_USB3 61 +#define MSM_BUS_MASTER_JPEG 62 +#define MSM_BUS_MASTER_VIDEO_P0 63 +#define MSM_BUS_MASTER_VIDEO_P1 64 +#define MSM_BUS_MASTER_MSS_PROC 65 +#define MSM_BUS_MASTER_JPEG_OCMEM 66 +#define MSM_BUS_MASTER_MDP_OCMEM 67 +#define MSM_BUS_MASTER_VIDEO_P0_OCMEM 68 +#define MSM_BUS_MASTER_VIDEO_P1_OCMEM 69 +#define MSM_BUS_MASTER_VFE_OCMEM 70 +#define MSM_BUS_MASTER_CNOC_ONOC_CFG 71 +#define MSM_BUS_MASTER_RPM_INST 72 +#define MSM_BUS_MASTER_RPM_DATA 73 +#define MSM_BUS_MASTER_RPM_SYS 74 +#define MSM_BUS_MASTER_DEHR 75 +#define MSM_BUS_MASTER_QDSS_DAP 76 +#define MSM_BUS_MASTER_TIC 77 +#define MSM_BUS_MASTER_SDCC_1 78 +#define MSM_BUS_MASTER_SDCC_3 79 +#define MSM_BUS_MASTER_SDCC_4 80 +#define MSM_BUS_MASTER_SDCC_2 81 +#define MSM_BUS_MASTER_TSIF 82 +#define MSM_BUS_MASTER_BAM_DMA 83 +#define MSM_BUS_MASTER_BLSP_2 84 +#define MSM_BUS_MASTER_USB_HSIC 85 +#define MSM_BUS_MASTER_BLSP_1 86 +#define MSM_BUS_MASTER_USB_HS 87 +#define MSM_BUS_MASTER_PNOC_CFG 88 +#define MSM_BUS_MASTER_V_OCMEM_GFX3D 89 +#define MSM_BUS_MASTER_IPA 90 +#define MSM_BUS_MASTER_QPIC 91 +#define MSM_BUS_MASTER_MDPE 92 +#define MSM_BUS_MASTER_USB_HS2 93 +#define MSM_BUS_MASTER_VPU 94 +#define MSM_BUS_MASTER_UFS 95 +#define MSM_BUS_MASTER_BCAST 96 +#define MSM_BUS_MASTER_CRYPTO_CORE2 97 +#define MSM_BUS_MASTER_EMAC 98 +#define MSM_BUS_MASTER_VPU_1 99 +#define MSM_BUS_MASTER_PCIE_1 100 +#define MSM_BUS_MASTER_USB3_1 101 +#define MSM_BUS_MASTER_CNOC_MNOC_MMSS_CFG 102 +#define MSM_BUS_MASTER_CNOC_MNOC_CFG 103 +#define MSM_BUS_MASTER_TCU_0 104 +#define MSM_BUS_MASTER_TCU_1 105 +#define MSM_BUS_MASTER_CPP 106 +#define MSM_BUS_MASTER_AUDIO 107 +#define MSM_BUS_MASTER_PCIE_2 108 +#define MSM_BUS_MASTER_VFE1 109 +#define MSM_BUS_MASTER_XM_USB_HS1 110 +#define MSM_BUS_MASTER_PCNOC_BIMC_1 111 +#define MSM_BUS_MASTER_BIMC_PCNOC 112 +#define MSM_BUS_MASTER_XI_USB_HSIC 113 +#define MSM_BUS_MASTER_SGMII 114 +#define MSM_BUS_SPMI_FETCHER 115 +#define MSM_BUS_MASTER_GNOC_BIMC 116 +#define MSM_BUS_MASTER_CRVIRT_A2NOC 117 +#define MSM_BUS_MASTER_CNOC_A2NOC 118 +#define MSM_BUS_MASTER_WLAN 119 +#define MSM_BUS_MASTER_MSS_CE 120 +#define MSM_BUS_MASTER_CDSP_PROC 121 +#define MSM_BUS_MASTER_GNOC_SNOC 122 +#define MSM_BUS_MASTER_PIMEM 123 +#define MSM_BUS_MASTER_MASTER_LAST 124 + +#define MSM_BUS_SYSTEM_FPB_MASTER_SYSTEM MSM_BUS_SYSTEM_MASTER_SYSTEM_FPB +#define MSM_BUS_CPSS_FPB_MASTER_SYSTEM MSM_BUS_SYSTEM_MASTER_CPSS_FPB + +#define MSM_BUS_SNOC_MM_INT_0 10000 +#define MSM_BUS_SNOC_MM_INT_1 10001 +#define MSM_BUS_SNOC_MM_INT_2 10002 +#define MSM_BUS_SNOC_MM_INT_BIMC 10003 +#define MSM_BUS_SNOC_INT_0 10004 +#define MSM_BUS_SNOC_INT_1 10005 +#define MSM_BUS_SNOC_INT_BIMC 10006 +#define MSM_BUS_SNOC_BIMC_0_MAS 10007 +#define MSM_BUS_SNOC_BIMC_1_MAS 10008 +#define MSM_BUS_SNOC_QDSS_INT 10009 +#define MSM_BUS_PNOC_SNOC_MAS 10010 +#define MSM_BUS_PNOC_SNOC_SLV 10011 +#define MSM_BUS_PNOC_INT_0 10012 +#define MSM_BUS_PNOC_INT_1 10013 +#define MSM_BUS_PNOC_M_0 10014 +#define MSM_BUS_PNOC_M_1 10015 +#define MSM_BUS_BIMC_SNOC_MAS 10016 +#define MSM_BUS_BIMC_SNOC_SLV 10017 +#define MSM_BUS_PNOC_SLV_0 10018 +#define MSM_BUS_PNOC_SLV_1 10019 +#define MSM_BUS_PNOC_SLV_2 10020 +#define MSM_BUS_PNOC_SLV_3 10021 +#define MSM_BUS_PNOC_SLV_4 10022 +#define MSM_BUS_PNOC_SLV_8 10023 +#define MSM_BUS_PNOC_SLV_9 10024 +#define MSM_BUS_SNOC_BIMC_0_SLV 10025 +#define MSM_BUS_SNOC_BIMC_1_SLV 10026 +#define MSM_BUS_MNOC_BIMC_MAS 10027 +#define MSM_BUS_MNOC_BIMC_SLV 10028 +#define MSM_BUS_BIMC_MNOC_MAS 10029 +#define MSM_BUS_BIMC_MNOC_SLV 10030 +#define MSM_BUS_SNOC_BIMC_MAS 10031 +#define MSM_BUS_SNOC_BIMC_SLV 10032 +#define MSM_BUS_CNOC_SNOC_MAS 10033 +#define MSM_BUS_CNOC_SNOC_SLV 10034 +#define MSM_BUS_SNOC_CNOC_MAS 10035 +#define MSM_BUS_SNOC_CNOC_SLV 10036 +#define MSM_BUS_OVNOC_SNOC_MAS 10037 +#define MSM_BUS_OVNOC_SNOC_SLV 10038 +#define MSM_BUS_SNOC_OVNOC_MAS 10039 +#define MSM_BUS_SNOC_OVNOC_SLV 10040 +#define MSM_BUS_SNOC_PNOC_MAS 10041 +#define MSM_BUS_SNOC_PNOC_SLV 10042 +#define MSM_BUS_BIMC_INT_APPS_EBI 10043 +#define MSM_BUS_BIMC_INT_APPS_SNOC 10044 +#define MSM_BUS_SNOC_BIMC_2_MAS 10045 +#define MSM_BUS_SNOC_BIMC_2_SLV 10046 +#define MSM_BUS_PNOC_SLV_5 10047 +#define MSM_BUS_PNOC_SLV_7 10048 +#define MSM_BUS_PNOC_INT_2 10049 +#define MSM_BUS_PNOC_INT_3 10050 +#define MSM_BUS_PNOC_INT_4 10051 +#define MSM_BUS_PNOC_INT_5 10052 +#define MSM_BUS_PNOC_INT_6 10053 +#define MSM_BUS_PNOC_INT_7 10054 +#define MSM_BUS_BIMC_SNOC_1_MAS 10055 +#define MSM_BUS_BIMC_SNOC_1_SLV 10056 +#define MSM_BUS_PNOC_A1NOC_MAS 10057 +#define MSM_BUS_PNOC_A1NOC_SLV 10058 +#define MSM_BUS_CNOC_A1NOC_MAS 10059 +#define MSM_BUS_A0NOC_SNOC_MAS 10060 +#define MSM_BUS_A0NOC_SNOC_SLV 10061 +#define MSM_BUS_A1NOC_SNOC_SLV 10062 +#define MSM_BUS_A1NOC_SNOC_MAS 10063 +#define MSM_BUS_A2NOC_SNOC_MAS 10064 +#define MSM_BUS_A2NOC_SNOC_SLV 10065 +#define MSM_BUS_SNOC_INT_2 10066 +#define MSM_BUS_A0NOC_QDSS_INT 10067 +#define MSM_BUS_INT_LAST 10068 + +#define MSM_BUS_INT_TEST_ID 20000 +#define MSM_BUS_INT_TEST_LAST 20050 + +#define MSM_BUS_SLAVE_FIRST 512 +#define MSM_BUS_SLAVE_EBI_CH0 512 +#define MSM_BUS_SLAVE_EBI_CH1 513 +#define MSM_BUS_SLAVE_AMPSS_L2 514 +#define MSM_BUS_APPSS_SLAVE_FAB_MMSS 515 +#define MSM_BUS_APPSS_SLAVE_FAB_SYSTEM 516 +#define MSM_BUS_SYSTEM_SLAVE_FAB_APPS 517 +#define MSM_BUS_SLAVE_SPS 518 +#define MSM_BUS_SLAVE_SYSTEM_IMEM 519 +#define MSM_BUS_SLAVE_AMPSS 520 +#define MSM_BUS_SLAVE_MSS 521 +#define MSM_BUS_SLAVE_LPASS 522 +#define MSM_BUS_SYSTEM_SLAVE_CPSS_FPB 523 +#define MSM_BUS_SYSTEM_SLAVE_SYSTEM_FPB 524 +#define MSM_BUS_SYSTEM_SLAVE_MMSS_FPB 525 +#define MSM_BUS_SLAVE_CORESIGHT 526 +#define MSM_BUS_SLAVE_RIVA 527 +#define MSM_BUS_SLAVE_SMI 528 +#define MSM_BUS_MMSS_SLAVE_FAB_APPS 529 +#define MSM_BUS_MMSS_SLAVE_FAB_APPS_1 530 +#define MSM_BUS_SLAVE_MM_IMEM 531 +#define MSM_BUS_SLAVE_CRYPTO 532 +#define MSM_BUS_SLAVE_SPDM 533 +#define MSM_BUS_SLAVE_RPM 534 +#define MSM_BUS_SLAVE_RPM_MSG_RAM 535 +#define MSM_BUS_SLAVE_MPM 536 +#define MSM_BUS_SLAVE_PMIC1_SSBI1_A 537 +#define MSM_BUS_SLAVE_PMIC1_SSBI1_B 538 +#define MSM_BUS_SLAVE_PMIC1_SSBI1_C 539 +#define MSM_BUS_SLAVE_PMIC2_SSBI2_A 540 +#define MSM_BUS_SLAVE_PMIC2_SSBI2_B 541 +#define MSM_BUS_SLAVE_GSBI1_UART 542 +#define MSM_BUS_SLAVE_GSBI2_UART 543 +#define MSM_BUS_SLAVE_GSBI3_UART 544 +#define MSM_BUS_SLAVE_GSBI4_UART 545 +#define MSM_BUS_SLAVE_GSBI5_UART 546 +#define MSM_BUS_SLAVE_GSBI6_UART 547 +#define MSM_BUS_SLAVE_GSBI7_UART 548 +#define MSM_BUS_SLAVE_GSBI8_UART 549 +#define MSM_BUS_SLAVE_GSBI9_UART 550 +#define MSM_BUS_SLAVE_GSBI10_UART 551 +#define MSM_BUS_SLAVE_GSBI11_UART 552 +#define MSM_BUS_SLAVE_GSBI12_UART 553 +#define MSM_BUS_SLAVE_GSBI1_QUP 554 +#define MSM_BUS_SLAVE_GSBI2_QUP 555 +#define MSM_BUS_SLAVE_GSBI3_QUP 556 +#define MSM_BUS_SLAVE_GSBI4_QUP 557 +#define MSM_BUS_SLAVE_GSBI5_QUP 558 +#define MSM_BUS_SLAVE_GSBI6_QUP 559 +#define MSM_BUS_SLAVE_GSBI7_QUP 560 +#define MSM_BUS_SLAVE_GSBI8_QUP 561 +#define MSM_BUS_SLAVE_GSBI9_QUP 562 +#define MSM_BUS_SLAVE_GSBI10_QUP 563 +#define MSM_BUS_SLAVE_GSBI11_QUP 564 +#define MSM_BUS_SLAVE_GSBI12_QUP 565 +#define MSM_BUS_SLAVE_EBI2_NAND 566 +#define MSM_BUS_SLAVE_EBI2_CS0 567 +#define MSM_BUS_SLAVE_EBI2_CS1 568 +#define MSM_BUS_SLAVE_EBI2_CS2 569 +#define MSM_BUS_SLAVE_EBI2_CS3 570 +#define MSM_BUS_SLAVE_EBI2_CS4 571 +#define MSM_BUS_SLAVE_EBI2_CS5 572 +#define MSM_BUS_SLAVE_USB_FS1 573 +#define MSM_BUS_SLAVE_USB_FS2 574 +#define MSM_BUS_SLAVE_TSIF 575 +#define MSM_BUS_SLAVE_MSM_TSSC 576 +#define MSM_BUS_SLAVE_MSM_PDM 577 +#define MSM_BUS_SLAVE_MSM_DIMEM 578 +#define MSM_BUS_SLAVE_MSM_TCSR 579 +#define MSM_BUS_SLAVE_MSM_PRNG 580 +#define MSM_BUS_SLAVE_GSS 581 +#define MSM_BUS_SLAVE_SATA 582 +#define MSM_BUS_SLAVE_USB3 583 +#define MSM_BUS_SLAVE_WCSS 584 +#define MSM_BUS_SLAVE_OCIMEM 585 +#define MSM_BUS_SLAVE_SNOC_OCMEM 586 +#define MSM_BUS_SLAVE_SERVICE_SNOC 587 +#define MSM_BUS_SLAVE_QDSS_STM 588 +#define MSM_BUS_SLAVE_CAMERA_CFG 589 +#define MSM_BUS_SLAVE_DISPLAY_CFG 590 +#define MSM_BUS_SLAVE_OCMEM_CFG 591 +#define MSM_BUS_SLAVE_CPR_CFG 592 +#define MSM_BUS_SLAVE_CPR_XPU_CFG 593 +#define MSM_BUS_SLAVE_MISC_CFG 594 +#define MSM_BUS_SLAVE_MISC_XPU_CFG 595 +#define MSM_BUS_SLAVE_VENUS_CFG 596 +#define MSM_BUS_SLAVE_MISC_VENUS_CFG 597 +#define MSM_BUS_SLAVE_GRAPHICS_3D_CFG 598 +#define MSM_BUS_SLAVE_MMSS_CLK_CFG 599 +#define MSM_BUS_SLAVE_MMSS_CLK_XPU_CFG 600 +#define MSM_BUS_SLAVE_MNOC_MPU_CFG 601 +#define MSM_BUS_SLAVE_ONOC_MPU_CFG 602 +#define MSM_BUS_SLAVE_SERVICE_MNOC 603 +#define MSM_BUS_SLAVE_OCMEM 604 +#define MSM_BUS_SLAVE_SERVICE_ONOC 605 +#define MSM_BUS_SLAVE_SDCC_1 606 +#define MSM_BUS_SLAVE_SDCC_3 607 +#define MSM_BUS_SLAVE_SDCC_2 608 +#define MSM_BUS_SLAVE_SDCC_4 609 +#define MSM_BUS_SLAVE_BAM_DMA 610 +#define MSM_BUS_SLAVE_BLSP_2 611 +#define MSM_BUS_SLAVE_USB_HSIC 612 +#define MSM_BUS_SLAVE_BLSP_1 613 +#define MSM_BUS_SLAVE_USB_HS 614 +#define MSM_BUS_SLAVE_PDM 615 +#define MSM_BUS_SLAVE_PERIPH_APU_CFG 616 +#define MSM_BUS_SLAVE_PNOC_MPU_CFG 617 +#define MSM_BUS_SLAVE_PRNG 618 +#define MSM_BUS_SLAVE_SERVICE_PNOC 619 +#define MSM_BUS_SLAVE_CLK_CTL 620 +#define MSM_BUS_SLAVE_CNOC_MSS 621 +#define MSM_BUS_SLAVE_SECURITY 622 +#define MSM_BUS_SLAVE_TCSR 623 +#define MSM_BUS_SLAVE_TLMM 624 +#define MSM_BUS_SLAVE_CRYPTO_0_CFG 625 +#define MSM_BUS_SLAVE_CRYPTO_1_CFG 626 +#define MSM_BUS_SLAVE_IMEM_CFG 627 +#define MSM_BUS_SLAVE_MESSAGE_RAM 628 +#define MSM_BUS_SLAVE_BIMC_CFG 629 +#define MSM_BUS_SLAVE_BOOT_ROM 630 +#define MSM_BUS_SLAVE_CNOC_MNOC_MMSS_CFG 631 +#define MSM_BUS_SLAVE_PMIC_ARB 632 +#define MSM_BUS_SLAVE_SPDM_WRAPPER 633 +#define MSM_BUS_SLAVE_DEHR_CFG 634 +#define MSM_BUS_SLAVE_QDSS_CFG 635 +#define MSM_BUS_SLAVE_RBCPR_CFG 636 +#define MSM_BUS_SLAVE_RBCPR_QDSS_APU_CFG 637 +#define MSM_BUS_SLAVE_SNOC_MPU_CFG 638 +#define MSM_BUS_SLAVE_CNOC_ONOC_CFG 639 +#define MSM_BUS_SLAVE_CNOC_MNOC_CFG 640 +#define MSM_BUS_SLAVE_PNOC_CFG 641 +#define MSM_BUS_SLAVE_SNOC_CFG 642 +#define MSM_BUS_SLAVE_EBI1_DLL_CFG 643 +#define MSM_BUS_SLAVE_PHY_APU_CFG 644 +#define MSM_BUS_SLAVE_EBI1_PHY_CFG 645 +#define MSM_BUS_SLAVE_SERVICE_CNOC 646 +#define MSM_BUS_SLAVE_IPS_CFG 647 +#define MSM_BUS_SLAVE_QPIC 648 +#define MSM_BUS_SLAVE_DSI_CFG 649 +#define MSM_BUS_SLAVE_UFS_CFG 650 +#define MSM_BUS_SLAVE_RBCPR_CX_CFG 651 +#define MSM_BUS_SLAVE_RBCPR_MX_CFG 652 +#define MSM_BUS_SLAVE_PCIE_CFG 653 +#define MSM_BUS_SLAVE_USB_PHYS_CFG 654 +#define MSM_BUS_SLAVE_VIDEO_CAP_CFG 655 +#define MSM_BUS_SLAVE_AVSYNC_CFG 656 +#define MSM_BUS_SLAVE_CRYPTO_2_CFG 657 +#define MSM_BUS_SLAVE_VPU_CFG 658 +#define MSM_BUS_SLAVE_BCAST_CFG 659 +#define MSM_BUS_SLAVE_KLM_CFG 660 +#define MSM_BUS_SLAVE_GENI_IR_CFG 661 +#define MSM_BUS_SLAVE_OCMEM_GFX 662 +#define MSM_BUS_SLAVE_CATS_128 663 +#define MSM_BUS_SLAVE_OCMEM_64 664 +#define MSM_BUS_SLAVE_PCIE_0 665 +#define MSM_BUS_SLAVE_PCIE_1 666 +#define MSM_BUS_SLAVE_PCIE_0_CFG 667 +#define MSM_BUS_SLAVE_PCIE_1_CFG 668 +#define MSM_BUS_SLAVE_SRVC_MNOC 669 +#define MSM_BUS_SLAVE_USB_HS2 670 +#define MSM_BUS_SLAVE_AUDIO 671 +#define MSM_BUS_SLAVE_TCU 672 +#define MSM_BUS_SLAVE_APPSS 673 +#define MSM_BUS_SLAVE_PCIE_PARF 674 +#define MSM_BUS_SLAVE_USB3_PHY_CFG 675 +#define MSM_BUS_SLAVE_IPA_CFG 676 +#define MSM_BUS_SLAVE_A0NOC_SNOC 677 +#define MSM_BUS_SLAVE_A1NOC_SNOC 678 +#define MSM_BUS_SLAVE_A2NOC_SNOC 679 +#define MSM_BUS_SLAVE_HMSS_L3 680 +#define MSM_BUS_SLAVE_PIMEM_CFG 681 +#define MSM_BUS_SLAVE_DCC_CFG 682 +#define MSM_BUS_SLAVE_QDSS_RBCPR_APU_CFG 683 +#define MSM_BUS_SLAVE_PCIE_2_CFG 684 +#define MSM_BUS_SLAVE_PCIE20_AHB2PHY 685 +#define MSM_BUS_SLAVE_A0NOC_CFG 686 +#define MSM_BUS_SLAVE_A1NOC_CFG 687 +#define MSM_BUS_SLAVE_A2NOC_CFG 688 +#define MSM_BUS_SLAVE_A1NOC_MPU_CFG 689 +#define MSM_BUS_SLAVE_A2NOC_MPU_CFG 690 +#define MSM_BUS_SLAVE_A0NOC_SMMU_CFG 691 +#define MSM_BUS_SLAVE_A1NOC_SMMU_CFG 692 +#define MSM_BUS_SLAVE_A2NOC_SMMU_CFG 693 +#define MSM_BUS_SLAVE_LPASS_SMMU_CFG 694 +#define MSM_BUS_SLAVE_MMAGIC_CFG 695 +#define MSM_BUS_SLAVE_VENUS_THROTTLE_CFG 696 +#define MSM_BUS_SLAVE_SSC_CFG 697 +#define MSM_BUS_SLAVE_DSA_CFG 698 +#define MSM_BUS_SLAVE_DSA_MPU_CFG 699 +#define MSM_BUS_SLAVE_DISPLAY_THROTTLE_CFG 700 +#define MSM_BUS_SLAVE_SMMU_CPP_CFG 701 +#define MSM_BUS_SLAVE_SMMU_JPEG_CFG 702 +#define MSM_BUS_SLAVE_SMMU_MDP_CFG 703 +#define MSM_BUS_SLAVE_SMMU_ROTATOR_CFG 704 +#define MSM_BUS_SLAVE_SMMU_VENUS_CFG 705 +#define MSM_BUS_SLAVE_SMMU_VFE_CFG 706 +#define MSM_BUS_SLAVE_A0NOC_MPU_CFG 707 +#define MSM_BUS_SLAVE_VMEM_CFG 708 +#define MSM_BUS_SLAVE_CAMERA_THROTTLE_CFG 709 +#define MSM_BUS_SLAVE_VMEM 710 +#define MSM_BUS_SLAVE_AHB2PHY 711 +#define MSM_BUS_SLAVE_PIMEM 712 +#define MSM_BUS_SLAVE_SNOC_VMEM 713 +#define MSM_BUS_SLAVE_PCIE_2 714 +#define MSM_BUS_SLAVE_RBCPR_MX 715 +#define MSM_BUS_SLAVE_RBCPR_CX 716 +#define MSM_BUS_SLAVE_BIMC_PCNOC 717 +#define MSM_BUS_SLAVE_PCNOC_BIMC_1 718 +#define MSM_BUS_SLAVE_SGMII 719 +#define MSM_BUS_SLAVE_SPMI_FETCHER 720 +#define MSM_BUS_PNOC_SLV_6 721 +#define MSM_BUS_SLAVE_MMSS_SMMU_CFG 722 +#define MSM_BUS_SLAVE_WLAN 723 +#define MSM_BUS_SLAVE_CRVIRT_A2NOC 724 +#define MSM_BUS_SLAVE_CNOC_A2NOC 725 +#define MSM_BUS_SLAVE_GLM 726 +#define MSM_BUS_SLAVE_GNOC_BIMC 727 +#define MSM_BUS_SLAVE_GNOC_SNOC 728 +#define MSM_BUS_SLAVE_QM_CFG 729 +#define MSM_BUS_SLAVE_TLMM_EAST 730 +#define MSM_BUS_SLAVE_TLMM_NORTH 731 +#define MSM_BUS_SLAVE_TLMM_WEST 732 +#define MSM_BUS_SLAVE_SKL 733 +#define MSM_BUS_SLAVE_LPASS_TCM 734 +#define MSM_BUS_SLAVE_TLMM_SOUTH 735 +#define MSM_BUS_SLAVE_TLMM_CENTER 736 +#define MSM_BUS_MSS_NAV_CE_MPU_CFG 737 +#define MSM_BUS_SLAVE_A2NOC_THROTTLE_CFG 738 +#define MSM_BUS_SLAVE_CDSP 739 +#define MSM_BUS_SLAVE_CDSP_SMMU_CFG 740 +#define MSM_BUS_SLAVE_LPASS_MPU_CFG 741 +#define MSM_BUS_SLAVE_CSI_PHY_CFG 742 +#define MSM_BUS_SLAVE_LAST 743 + +#define MSM_BUS_SYSTEM_FPB_SLAVE_SYSTEM MSM_BUS_SYSTEM_SLAVE_SYSTEM_FPB +#define MSM_BUS_CPSS_FPB_SLAVE_SYSTEM MSM_BUS_SYSTEM_SLAVE_CPSS_FPB + +/* + * ID's used in RPM messages + */ +#define ICBID_MASTER_APPSS_PROC 0 +#define ICBID_MASTER_MSS_PROC 1 +#define ICBID_MASTER_MNOC_BIMC 2 +#define ICBID_MASTER_SNOC_BIMC 3 +#define ICBID_MASTER_SNOC_BIMC_0 ICBID_MASTER_SNOC_BIMC +#define ICBID_MASTER_CNOC_MNOC_MMSS_CFG 4 +#define ICBID_MASTER_CNOC_MNOC_CFG 5 +#define ICBID_MASTER_GFX3D 6 +#define ICBID_MASTER_JPEG 7 +#define ICBID_MASTER_MDP 8 +#define ICBID_MASTER_MDP0 ICBID_MASTER_MDP +#define ICBID_MASTER_MDPS ICBID_MASTER_MDP +#define ICBID_MASTER_VIDEO 9 +#define ICBID_MASTER_VIDEO_P0 ICBID_MASTER_VIDEO +#define ICBID_MASTER_VIDEO_P1 10 +#define ICBID_MASTER_VFE 11 +#define ICBID_MASTER_VFE0 ICBID_MASTER_VFE +#define ICBID_MASTER_CNOC_ONOC_CFG 12 +#define ICBID_MASTER_JPEG_OCMEM 13 +#define ICBID_MASTER_MDP_OCMEM 14 +#define ICBID_MASTER_VIDEO_P0_OCMEM 15 +#define ICBID_MASTER_VIDEO_P1_OCMEM 16 +#define ICBID_MASTER_VFE_OCMEM 17 +#define ICBID_MASTER_LPASS_AHB 18 +#define ICBID_MASTER_QDSS_BAM 19 +#define ICBID_MASTER_SNOC_CFG 20 +#define ICBID_MASTER_BIMC_SNOC 21 +#define ICBID_MASTER_BIMC_SNOC_0 ICBID_MASTER_BIMC_SNOC +#define ICBID_MASTER_CNOC_SNOC 22 +#define ICBID_MASTER_CRYPTO 23 +#define ICBID_MASTER_CRYPTO_CORE0 ICBID_MASTER_CRYPTO +#define ICBID_MASTER_CRYPTO_CORE1 24 +#define ICBID_MASTER_LPASS_PROC 25 +#define ICBID_MASTER_MSS 26 +#define ICBID_MASTER_MSS_NAV 27 +#define ICBID_MASTER_OCMEM_DMA 28 +#define ICBID_MASTER_PNOC_SNOC 29 +#define ICBID_MASTER_WCSS 30 +#define ICBID_MASTER_QDSS_ETR 31 +#define ICBID_MASTER_USB3 32 +#define ICBID_MASTER_USB3_0 ICBID_MASTER_USB3 +#define ICBID_MASTER_SDCC_1 33 +#define ICBID_MASTER_SDCC_3 34 +#define ICBID_MASTER_SDCC_2 35 +#define ICBID_MASTER_SDCC_4 36 +#define ICBID_MASTER_TSIF 37 +#define ICBID_MASTER_BAM_DMA 38 +#define ICBID_MASTER_BLSP_2 39 +#define ICBID_MASTER_USB_HSIC 40 +#define ICBID_MASTER_BLSP_1 41 +#define ICBID_MASTER_USB_HS 42 +#define ICBID_MASTER_USB_HS1 ICBID_MASTER_USB_HS +#define ICBID_MASTER_PNOC_CFG 43 +#define ICBID_MASTER_SNOC_PNOC 44 +#define ICBID_MASTER_RPM_INST 45 +#define ICBID_MASTER_RPM_DATA 46 +#define ICBID_MASTER_RPM_SYS 47 +#define ICBID_MASTER_DEHR 48 +#define ICBID_MASTER_QDSS_DAP 49 +#define ICBID_MASTER_SPDM 50 +#define ICBID_MASTER_TIC 51 +#define ICBID_MASTER_SNOC_CNOC 52 +#define ICBID_MASTER_GFX3D_OCMEM 53 +#define ICBID_MASTER_GFX3D_GMEM ICBID_MASTER_GFX3D_OCMEM +#define ICBID_MASTER_OVIRT_SNOC 54 +#define ICBID_MASTER_SNOC_OVIRT 55 +#define ICBID_MASTER_SNOC_GVIRT ICBID_MASTER_SNOC_OVIRT +#define ICBID_MASTER_ONOC_OVIRT 56 +#define ICBID_MASTER_USB_HS2 57 +#define ICBID_MASTER_QPIC 58 +#define ICBID_MASTER_IPA 59 +#define ICBID_MASTER_DSI 60 +#define ICBID_MASTER_MDP1 61 +#define ICBID_MASTER_MDPE ICBID_MASTER_MDP1 +#define ICBID_MASTER_VPU_PROC 62 +#define ICBID_MASTER_VPU 63 +#define ICBID_MASTER_VPU0 ICBID_MASTER_VPU +#define ICBID_MASTER_CRYPTO_CORE2 64 +#define ICBID_MASTER_PCIE_0 65 +#define ICBID_MASTER_PCIE_1 66 +#define ICBID_MASTER_SATA 67 +#define ICBID_MASTER_UFS 68 +#define ICBID_MASTER_USB3_1 69 +#define ICBID_MASTER_VIDEO_OCMEM 70 +#define ICBID_MASTER_VPU1 71 +#define ICBID_MASTER_VCAP 72 +#define ICBID_MASTER_EMAC 73 +#define ICBID_MASTER_BCAST 74 +#define ICBID_MASTER_MMSS_PROC 75 +#define ICBID_MASTER_SNOC_BIMC_1 76 +#define ICBID_MASTER_SNOC_PCNOC 77 +#define ICBID_MASTER_AUDIO 78 +#define ICBID_MASTER_MM_INT_0 79 +#define ICBID_MASTER_MM_INT_1 80 +#define ICBID_MASTER_MM_INT_2 81 +#define ICBID_MASTER_MM_INT_BIMC 82 +#define ICBID_MASTER_MSS_INT 83 +#define ICBID_MASTER_PCNOC_CFG 84 +#define ICBID_MASTER_PCNOC_INT_0 85 +#define ICBID_MASTER_PCNOC_INT_1 86 +#define ICBID_MASTER_PCNOC_M_0 87 +#define ICBID_MASTER_PCNOC_M_1 88 +#define ICBID_MASTER_PCNOC_S_0 89 +#define ICBID_MASTER_PCNOC_S_1 90 +#define ICBID_MASTER_PCNOC_S_2 91 +#define ICBID_MASTER_PCNOC_S_3 92 +#define ICBID_MASTER_PCNOC_S_4 93 +#define ICBID_MASTER_PCNOC_S_6 94 +#define ICBID_MASTER_PCNOC_S_7 95 +#define ICBID_MASTER_PCNOC_S_8 96 +#define ICBID_MASTER_PCNOC_S_9 97 +#define ICBID_MASTER_QDSS_INT 98 +#define ICBID_MASTER_SNOC_INT_0 99 +#define ICBID_MASTER_SNOC_INT_1 100 +#define ICBID_MASTER_SNOC_INT_BIMC 101 +#define ICBID_MASTER_TCU_0 102 +#define ICBID_MASTER_TCU_1 103 +#define ICBID_MASTER_BIMC_INT_0 104 +#define ICBID_MASTER_BIMC_INT_1 105 +#define ICBID_MASTER_CAMERA 106 +#define ICBID_MASTER_RICA 107 +#define ICBID_MASTER_SNOC_BIMC_2 108 +#define ICBID_MASTER_BIMC_SNOC_1 109 +#define ICBID_MASTER_A0NOC_SNOC 110 +#define ICBID_MASTER_A1NOC_SNOC 111 +#define ICBID_MASTER_A2NOC_SNOC 112 +#define ICBID_MASTER_PIMEM 113 +#define ICBID_MASTER_SNOC_VMEM 114 +#define ICBID_MASTER_CPP 115 +#define ICBID_MASTER_CNOC_A1NOC 116 +#define ICBID_MASTER_PNOC_A1NOC 117 +#define ICBID_MASTER_HMSS 118 +#define ICBID_MASTER_PCIE_2 119 +#define ICBID_MASTER_ROTATOR 120 +#define ICBID_MASTER_VENUS_VMEM 121 +#define ICBID_MASTER_DCC 122 +#define ICBID_MASTER_MCDMA 123 +#define ICBID_MASTER_PCNOC_INT_2 124 +#define ICBID_MASTER_PCNOC_INT_3 125 +#define ICBID_MASTER_PCNOC_INT_4 126 +#define ICBID_MASTER_PCNOC_INT_5 127 +#define ICBID_MASTER_PCNOC_INT_6 128 +#define ICBID_MASTER_PCNOC_S_5 129 +#define ICBID_MASTER_SENSORS_AHB 130 +#define ICBID_MASTER_SENSORS_PROC 131 +#define ICBID_MASTER_QSPI 132 +#define ICBID_MASTER_VFE1 133 +#define ICBID_MASTER_SNOC_INT_2 134 +#define ICBID_MASTER_SMMNOC_BIMC 135 +#define ICBID_MASTER_CRVIRT_A1NOC 136 +#define ICBID_MASTER_XM_USB_HS1 137 +#define ICBID_MASTER_XI_USB_HS1 138 +#define ICBID_MASTER_PCNOC_BIMC_1 139 +#define ICBID_MASTER_BIMC_PCNOC 140 +#define ICBID_MASTER_XI_HSIC 141 +#define ICBID_MASTER_SGMII 142 +#define ICBID_MASTER_SPMI_FETCHER 143 +#define ICBID_MASTER_GNOC_BIMC 144 +#define ICBID_MASTER_CRVIRT_A2NOC 145 +#define ICBID_MASTER_CNOC_A2NOC 146 +#define ICBID_MASTER_WLAN 147 +#define ICBID_MASTER_MSS_CE 148 +#define ICBID_MASTER_CDSP_PROC 149 +#define ICBID_MASTER_GNOC_SNOC 150 + +#define ICBID_SLAVE_EBI1 0 +#define ICBID_SLAVE_APPSS_L2 1 +#define ICBID_SLAVE_BIMC_SNOC 2 +#define ICBID_SLAVE_BIMC_SNOC_0 ICBID_SLAVE_BIMC_SNOC +#define ICBID_SLAVE_CAMERA_CFG 3 +#define ICBID_SLAVE_DISPLAY_CFG 4 +#define ICBID_SLAVE_OCMEM_CFG 5 +#define ICBID_SLAVE_CPR_CFG 6 +#define ICBID_SLAVE_CPR_XPU_CFG 7 +#define ICBID_SLAVE_MISC_CFG 8 +#define ICBID_SLAVE_MISC_XPU_CFG 9 +#define ICBID_SLAVE_VENUS_CFG 10 +#define ICBID_SLAVE_GFX3D_CFG 11 +#define ICBID_SLAVE_MMSS_CLK_CFG 12 +#define ICBID_SLAVE_MMSS_CLK_XPU_CFG 13 +#define ICBID_SLAVE_MNOC_MPU_CFG 14 +#define ICBID_SLAVE_ONOC_MPU_CFG 15 +#define ICBID_SLAVE_MNOC_BIMC 16 +#define ICBID_SLAVE_SERVICE_MNOC 17 +#define ICBID_SLAVE_OCMEM 18 +#define ICBID_SLAVE_GMEM ICBID_SLAVE_OCMEM +#define ICBID_SLAVE_SERVICE_ONOC 19 +#define ICBID_SLAVE_APPSS 20 +#define ICBID_SLAVE_LPASS 21 +#define ICBID_SLAVE_USB3 22 +#define ICBID_SLAVE_USB3_0 ICBID_SLAVE_USB3 +#define ICBID_SLAVE_WCSS 23 +#define ICBID_SLAVE_SNOC_BIMC 24 +#define ICBID_SLAVE_SNOC_BIMC_0 ICBID_SLAVE_SNOC_BIMC +#define ICBID_SLAVE_SNOC_CNOC 25 +#define ICBID_SLAVE_IMEM 26 +#define ICBID_SLAVE_OCIMEM ICBID_SLAVE_IMEM +#define ICBID_SLAVE_SNOC_OVIRT 27 +#define ICBID_SLAVE_SNOC_GVIRT ICBID_SLAVE_SNOC_OVIRT +#define ICBID_SLAVE_SNOC_PNOC 28 +#define ICBID_SLAVE_SNOC_PCNOC ICBID_SLAVE_SNOC_PNOC +#define ICBID_SLAVE_SERVICE_SNOC 29 +#define ICBID_SLAVE_QDSS_STM 30 +#define ICBID_SLAVE_SDCC_1 31 +#define ICBID_SLAVE_SDCC_3 32 +#define ICBID_SLAVE_SDCC_2 33 +#define ICBID_SLAVE_SDCC_4 34 +#define ICBID_SLAVE_TSIF 35 +#define ICBID_SLAVE_BAM_DMA 36 +#define ICBID_SLAVE_BLSP_2 37 +#define ICBID_SLAVE_USB_HSIC 38 +#define ICBID_SLAVE_BLSP_1 39 +#define ICBID_SLAVE_USB_HS 40 +#define ICBID_SLAVE_USB_HS1 ICBID_SLAVE_USB_HS +#define ICBID_SLAVE_PDM 41 +#define ICBID_SLAVE_PERIPH_APU_CFG 42 +#define ICBID_SLAVE_PNOC_MPU_CFG 43 +#define ICBID_SLAVE_PRNG 44 +#define ICBID_SLAVE_PNOC_SNOC 45 +#define ICBID_SLAVE_PCNOC_SNOC ICBID_SLAVE_PNOC_SNOC +#define ICBID_SLAVE_SERVICE_PNOC 46 +#define ICBID_SLAVE_CLK_CTL 47 +#define ICBID_SLAVE_CNOC_MSS 48 +#define ICBID_SLAVE_PCNOC_MSS ICBID_SLAVE_CNOC_MSS +#define ICBID_SLAVE_SECURITY 49 +#define ICBID_SLAVE_TCSR 50 +#define ICBID_SLAVE_TLMM 51 +#define ICBID_SLAVE_CRYPTO_0_CFG 52 +#define ICBID_SLAVE_CRYPTO_1_CFG 53 +#define ICBID_SLAVE_IMEM_CFG 54 +#define ICBID_SLAVE_MESSAGE_RAM 55 +#define ICBID_SLAVE_BIMC_CFG 56 +#define ICBID_SLAVE_BOOT_ROM 57 +#define ICBID_SLAVE_CNOC_MNOC_MMSS_CFG 58 +#define ICBID_SLAVE_PMIC_ARB 59 +#define ICBID_SLAVE_SPDM_WRAPPER 60 +#define ICBID_SLAVE_DEHR_CFG 61 +#define ICBID_SLAVE_MPM 62 +#define ICBID_SLAVE_QDSS_CFG 63 +#define ICBID_SLAVE_RBCPR_CFG 64 +#define ICBID_SLAVE_RBCPR_CX_CFG ICBID_SLAVE_RBCPR_CFG +#define ICBID_SLAVE_RBCPR_QDSS_APU_CFG 65 +#define ICBID_SLAVE_CNOC_MNOC_CFG 66 +#define ICBID_SLAVE_SNOC_MPU_CFG 67 +#define ICBID_SLAVE_CNOC_ONOC_CFG 68 +#define ICBID_SLAVE_PNOC_CFG 69 +#define ICBID_SLAVE_SNOC_CFG 70 +#define ICBID_SLAVE_EBI1_DLL_CFG 71 +#define ICBID_SLAVE_PHY_APU_CFG 72 +#define ICBID_SLAVE_EBI1_PHY_CFG 73 +#define ICBID_SLAVE_RPM 74 +#define ICBID_SLAVE_CNOC_SNOC 75 +#define ICBID_SLAVE_SERVICE_CNOC 76 +#define ICBID_SLAVE_OVIRT_SNOC 77 +#define ICBID_SLAVE_OVIRT_OCMEM 78 +#define ICBID_SLAVE_USB_HS2 79 +#define ICBID_SLAVE_QPIC 80 +#define ICBID_SLAVE_IPS_CFG 81 +#define ICBID_SLAVE_DSI_CFG 82 +#define ICBID_SLAVE_USB3_1 83 +#define ICBID_SLAVE_PCIE_0 84 +#define ICBID_SLAVE_PCIE_1 85 +#define ICBID_SLAVE_PSS_SMMU_CFG 86 +#define ICBID_SLAVE_CRYPTO_2_CFG 87 +#define ICBID_SLAVE_PCIE_0_CFG 88 +#define ICBID_SLAVE_PCIE_1_CFG 89 +#define ICBID_SLAVE_SATA_CFG 90 +#define ICBID_SLAVE_SPSS_GENI_IR 91 +#define ICBID_SLAVE_UFS_CFG 92 +#define ICBID_SLAVE_AVSYNC_CFG 93 +#define ICBID_SLAVE_VPU_CFG 94 +#define ICBID_SLAVE_USB_PHY_CFG 95 +#define ICBID_SLAVE_RBCPR_MX_CFG 96 +#define ICBID_SLAVE_PCIE_PARF 97 +#define ICBID_SLAVE_VCAP_CFG 98 +#define ICBID_SLAVE_EMAC_CFG 99 +#define ICBID_SLAVE_BCAST_CFG 100 +#define ICBID_SLAVE_KLM_CFG 101 +#define ICBID_SLAVE_DISPLAY_PWM 102 +#define ICBID_SLAVE_GENI 103 +#define ICBID_SLAVE_SNOC_BIMC_1 104 +#define ICBID_SLAVE_AUDIO 105 +#define ICBID_SLAVE_CATS_0 106 +#define ICBID_SLAVE_CATS_1 107 +#define ICBID_SLAVE_MM_INT_0 108 +#define ICBID_SLAVE_MM_INT_1 109 +#define ICBID_SLAVE_MM_INT_2 110 +#define ICBID_SLAVE_MM_INT_BIMC 111 +#define ICBID_SLAVE_MMU_MODEM_XPU_CFG 112 +#define ICBID_SLAVE_MSS_INT 113 +#define ICBID_SLAVE_PCNOC_INT_0 114 +#define ICBID_SLAVE_PCNOC_INT_1 115 +#define ICBID_SLAVE_PCNOC_M_0 116 +#define ICBID_SLAVE_PCNOC_M_1 117 +#define ICBID_SLAVE_PCNOC_S_0 118 +#define ICBID_SLAVE_PCNOC_S_1 119 +#define ICBID_SLAVE_PCNOC_S_2 120 +#define ICBID_SLAVE_PCNOC_S_3 121 +#define ICBID_SLAVE_PCNOC_S_4 122 +#define ICBID_SLAVE_PCNOC_S_6 123 +#define ICBID_SLAVE_PCNOC_S_7 124 +#define ICBID_SLAVE_PCNOC_S_8 125 +#define ICBID_SLAVE_PCNOC_S_9 126 +#define ICBID_SLAVE_PRNG_XPU_CFG 127 +#define ICBID_SLAVE_QDSS_INT 128 +#define ICBID_SLAVE_RPM_XPU_CFG 129 +#define ICBID_SLAVE_SNOC_INT_0 130 +#define ICBID_SLAVE_SNOC_INT_1 131 +#define ICBID_SLAVE_SNOC_INT_BIMC 132 +#define ICBID_SLAVE_TCU 133 +#define ICBID_SLAVE_BIMC_INT_0 134 +#define ICBID_SLAVE_BIMC_INT_1 135 +#define ICBID_SLAVE_RICA_CFG 136 +#define ICBID_SLAVE_SNOC_BIMC_2 137 +#define ICBID_SLAVE_BIMC_SNOC_1 138 +#define ICBID_SLAVE_PNOC_A1NOC 139 +#define ICBID_SLAVE_SNOC_VMEM 140 +#define ICBID_SLAVE_A0NOC_SNOC 141 +#define ICBID_SLAVE_A1NOC_SNOC 142 +#define ICBID_SLAVE_A2NOC_SNOC 143 +#define ICBID_SLAVE_A0NOC_CFG 144 +#define ICBID_SLAVE_A0NOC_MPU_CFG 145 +#define ICBID_SLAVE_A0NOC_SMMU_CFG 146 +#define ICBID_SLAVE_A1NOC_CFG 147 +#define ICBID_SLAVE_A1NOC_MPU_CFG 148 +#define ICBID_SLAVE_A1NOC_SMMU_CFG 149 +#define ICBID_SLAVE_A2NOC_CFG 150 +#define ICBID_SLAVE_A2NOC_MPU_CFG 151 +#define ICBID_SLAVE_A2NOC_SMMU_CFG 152 +#define ICBID_SLAVE_AHB2PHY 153 +#define ICBID_SLAVE_CAMERA_THROTTLE_CFG 154 +#define ICBID_SLAVE_DCC_CFG 155 +#define ICBID_SLAVE_DISPLAY_THROTTLE_CFG 156 +#define ICBID_SLAVE_DSA_CFG 157 +#define ICBID_SLAVE_DSA_MPU_CFG 158 +#define ICBID_SLAVE_SSC_MPU_CFG 159 +#define ICBID_SLAVE_HMSS_L3 160 +#define ICBID_SLAVE_LPASS_SMMU_CFG 161 +#define ICBID_SLAVE_MMAGIC_CFG 162 +#define ICBID_SLAVE_PCIE20_AHB2PHY 163 +#define ICBID_SLAVE_PCIE_2 164 +#define ICBID_SLAVE_PCIE_2_CFG 165 +#define ICBID_SLAVE_PIMEM 166 +#define ICBID_SLAVE_PIMEM_CFG 167 +#define ICBID_SLAVE_QDSS_RBCPR_APU_CFG 168 +#define ICBID_SLAVE_RBCPR_CX 169 +#define ICBID_SLAVE_RBCPR_MX 170 +#define ICBID_SLAVE_SMMU_CPP_CFG 171 +#define ICBID_SLAVE_SMMU_JPEG_CFG 172 +#define ICBID_SLAVE_SMMU_MDP_CFG 173 +#define ICBID_SLAVE_SMMU_ROTATOR_CFG 174 +#define ICBID_SLAVE_SMMU_VENUS_CFG 175 +#define ICBID_SLAVE_SMMU_VFE_CFG 176 +#define ICBID_SLAVE_SSC_CFG 177 +#define ICBID_SLAVE_VENUS_THROTTLE_CFG 178 +#define ICBID_SLAVE_VMEM 179 +#define ICBID_SLAVE_VMEM_CFG 180 +#define ICBID_SLAVE_QDSS_MPU_CFG 181 +#define ICBID_SLAVE_USB3_PHY_CFG 182 +#define ICBID_SLAVE_IPA_CFG 183 +#define ICBID_SLAVE_PCNOC_INT_2 184 +#define ICBID_SLAVE_PCNOC_INT_3 185 +#define ICBID_SLAVE_PCNOC_INT_4 186 +#define ICBID_SLAVE_PCNOC_INT_5 187 +#define ICBID_SLAVE_PCNOC_INT_6 188 +#define ICBID_SLAVE_PCNOC_S_5 189 +#define ICBID_SLAVE_QSPI 190 +#define ICBID_SLAVE_A1NOC_MS_MPU_CFG 191 +#define ICBID_SLAVE_A2NOC_MS_MPU_CFG 192 +#define ICBID_SLAVE_MODEM_Q6_SMMU_CFG 193 +#define ICBID_SLAVE_MSS_MPU_CFG 194 +#define ICBID_SLAVE_MSS_PROC_MS_MPU_CFG 195 +#define ICBID_SLAVE_SKL 196 +#define ICBID_SLAVE_SNOC_INT_2 197 +#define ICBID_SLAVE_SMMNOC_BIMC 198 +#define ICBID_SLAVE_CRVIRT_A1NOC 199 +#define ICBID_SLAVE_SGMII 200 +#define ICBID_SLAVE_QHS4_APPS 201 +#define ICBID_SLAVE_BIMC_PCNOC 202 +#define ICBID_SLAVE_PCNOC_BIMC_1 203 +#define ICBID_SLAVE_SPMI_FETCHER 204 +#define ICBID_SLAVE_MMSS_SMMU_CFG 205 +#define ICBID_SLAVE_WLAN 206 +#define ICBID_SLAVE_CRVIRT_A2NOC 207 +#define ICBID_SLAVE_CNOC_A2NOC 208 +#define ICBID_SLAVE_GLM 209 +#define ICBID_SLAVE_GNOC_BIMC 210 +#define ICBID_SLAVE_GNOC_SNOC 211 +#define ICBID_SLAVE_QM_CFG 212 +#define ICBID_SLAVE_TLMM_EAST 213 +#define ICBID_SLAVE_TLMM_NORTH 214 +#define ICBID_SLAVE_TLMM_WEST 215 +#define ICBID_SLAVE_LPASS_TCM 216 +#define ICBID_SLAVE_TLMM_SOUTH 217 +#define ICBID_SLAVE_TLMM_CENTER 218 +#define ICBID_SLAVE_MSS_NAV_CE_MPU_CFG 219 +#define ICBID_SLAVE_A2NOC_THROTTLE_CFG 220 +#define ICBID_SLAVE_CDSP 221 +#define ICBID_SLAVE_CDSP_SMMU_CFG 222 +#define ICBID_SLAVE_LPASS_MPU_CFG 223 +#define ICBID_SLAVE_CSI_PHY_CFG 224 +#endif diff -Nruw linux-4.4.115-fbx/arch/arm/boot/dts/include/dt-bindings/msm./msm-bus-rule-ops.h linux-4.4.115-fbx/arch/arm/boot/dts/include/dt-bindings/msm/msm-bus-rule-ops.h --- linux-4.4.115-fbx/arch/arm/boot/dts/include/dt-bindings/msm./msm-bus-rule-ops.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-4.4.115-fbx/arch/arm/boot/dts/include/dt-bindings/msm/msm-bus-rule-ops.h 2019-01-22 16:16:28.179288750 +0100 @@ -0,0 +1,34 @@ +/* Copyright (c) 2014, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __MSM_BUS_RULE_OPS_H +#define __MSM_BUS_RULE_OPS_H + +#define FLD_IB 0 +#define FLD_AB 1 +#define FLD_CLK 2 + +#define OP_LE 0 +#define OP_LT 1 +#define OP_GE 2 +#define OP_GT 3 +#define OP_NOOP 4 + +#define RULE_STATE_NOT_APPLIED 0 +#define RULE_STATE_APPLIED 1 + +#define THROTTLE_ON 0 +#define THROTTLE_OFF 1 +#define THROTTLE_REG 2 + + +#endif diff -Nruw linux-4.4.115-fbx/arch/arm/boot/dts/include/dt-bindings/msm./pm.h linux-4.4.115-fbx/arch/arm/boot/dts/include/dt-bindings/msm/pm.h --- linux-4.4.115-fbx/arch/arm/boot/dts/include/dt-bindings/msm./pm.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-4.4.115-fbx/arch/arm/boot/dts/include/dt-bindings/msm/pm.h 2019-01-22 16:16:28.179288750 +0100 @@ -0,0 +1,25 @@ +/* Copyright (c) 2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __DT_MSM_PM_H__ +#define __DT_MSM_PM_H__ + +#define LPM_RESET_LVL_NONE 0 +#define LPM_RESET_LVL_RET 1 +#define LPM_RESET_LVL_GDHS 2 +#define LPM_RESET_LVL_PC 3 + +#define LPM_AFF_LVL_CPU 0 +#define LPM_AFF_LVL_L2 1 +#define LPM_AFF_LVL_CCI 2 + +#endif diff -Nruw linux-4.4.115-fbx/arch/arm/boot/dts/include/dt-bindings/msm./power-on.h linux-4.4.115-fbx/arch/arm/boot/dts/include/dt-bindings/msm/power-on.h --- linux-4.4.115-fbx/arch/arm/boot/dts/include/dt-bindings/msm./power-on.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-4.4.115-fbx/arch/arm/boot/dts/include/dt-bindings/msm/power-on.h 2019-01-22 16:16:28.179288750 +0100 @@ -0,0 +1,24 @@ +/* Copyright (c) 2015, 2017, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __MSM_POWER_ON_H__ +#define __MSM_POWER_ON_H__ + +#define PON_POWER_OFF_RESERVED 0x00 +#define PON_POWER_OFF_WARM_RESET 0x01 +#define PON_POWER_OFF_SHUTDOWN 0x04 +#define PON_POWER_OFF_DVDD_SHUTDOWN 0x05 +#define PON_POWER_OFF_HARD_RESET 0x07 +#define PON_POWER_OFF_DVDD_HARD_RESET 0x08 +#define PON_POWER_OFF_MAX_TYPE 0x10 + +#endif --- /dev/null 2019-10-24 16:47:25.704025805 +0200 +++ linux-4.4.115-fbx/arch/arm/boot/dts/include/dt-bindings/regulator/qcom,rpm-smd-regulator.h 2019-01-22 16:16:28.183288787 +0100 @@ -0,0 +1,28 @@ +/* Copyright (c) 2015, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __QCOM_RPM_SMD_REGULATOR_H +#define __QCOM_RPM_SMD_REGULATOR_H + +#define RPM_SMD_REGULATOR_LEVEL_NONE 0 +#define RPM_SMD_REGULATOR_LEVEL_RETENTION 16 +#define RPM_SMD_REGULATOR_LEVEL_RETENTION_PLUS 32 +#define RPM_SMD_REGULATOR_LEVEL_MIN_SVS 48 +#define RPM_SMD_REGULATOR_LEVEL_LOW_SVS 64 +#define RPM_SMD_REGULATOR_LEVEL_SVS 128 +#define RPM_SMD_REGULATOR_LEVEL_SVS_PLUS 192 +#define RPM_SMD_REGULATOR_LEVEL_NOM 256 +#define RPM_SMD_REGULATOR_LEVEL_NOM_PLUS 320 +#define RPM_SMD_REGULATOR_LEVEL_TURBO 384 +#define RPM_SMD_REGULATOR_LEVEL_BINNING 512 + +#endif diff -Nruw linux-4.4.115-fbx/arch/arm/boot/dts/qcom./apq8098-freebox-batfish.dts linux-4.4.115-fbx/arch/arm/boot/dts/qcom/apq8098-freebox-batfish.dts --- linux-4.4.115-fbx/arch/arm/boot/dts/qcom./apq8098-freebox-batfish.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-4.4.115-fbx/arch/arm/boot/dts/qcom/apq8098-freebox-batfish.dts 2019-01-22 16:16:21.171225289 +0100 @@ -0,0 +1,692 @@ +/* Copyright (c) 2017, Freebox SAS. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +#include +#include +#include "apq8098-v2.1.dtsi" +#include "msm8998-audio-freebox.dtsi" + +#include "msm8998-ramoops.dtsi" + +/ { + model = "Freebox Batfish"; + compatible = "freebox,fbx7hd-batfish", "freebox,fbx7hd", "qcom,apq8098"; + qcom,board-id = <5 2>; + + ir: ir-receiver { + compatible = "gpio-ir-receiver"; + gpios = <&tlmm 120 1>; + pinctrl-names = "default"; + pinctrl-0 = <&ir_int>; + linux,rc-map-name = "rc-rc6-freebox"; + }; + + fbxgpio@0 { + compatible = "fbx,fbxgpio"; + + pinctrl-names = "default"; + pinctrl-0 = < + &hdmi_en + &hdmi_fault + &force_test_mode + &usb_hub_rst + &spdif_src_sel + >; + + hdmi-enable { + name = "hdmi-enable"; + gpio = <&tlmm 17 GPIO_ACTIVE_HIGH>; + output-low; + }; + + hdmi-fault { + name = "hdmi-fault"; + gpio = <&tlmm 133 GPIO_ACTIVE_LOW>; + input; + }; + + test-mode { + name = "test-mode"; + gpio = <&tlmm 29 GPIO_ACTIVE_LOW>; + input; + }; + + usb-reset { + name = "usb-reset"; + gpio = <&tlmm 24 GPIO_ACTIVE_LOW>; + output-low; + }; + + spdif-src { + name = "spdif-src"; + gpio = <&tlmm 8 GPIO_ACTIVE_LOW>; + output-low; + }; + }; + + fbxgpio@1 { + compatible = "fbx,fbxgpio"; + + top-wcharging-ledr { + name = "top-wcharging-ledr"; + gpio = <&exp1 0 GPIO_ACTIVE_LOW>; + input; + }; + + top-wcharging-ledg { + name = "top-wcharging-ledg"; + gpio = <&exp1 1 GPIO_ACTIVE_LOW>; + input; + }; + + top-nfc-enable { + name = "top-nfc-enable"; + gpio = <&exp1 2 GPIO_ACTIVE_LOW>; + output-low; + }; + + top-nfc-int { + name = "top-nfc-int"; + gpio = <&exp1 3 GPIO_ACTIVE_LOW>; + input; + }; + + top-dsp-reset { + name = "top-dsp-reset"; + gpio = <&exp1 4 GPIO_ACTIVE_LOW>; + output-low; + }; + + top-mic-mute { + name = "top-mic-mute"; + gpio = <&exp1 7 GPIO_ACTIVE_HIGH>; + input; + }; + + top-wcharging-stby { + name = "top-wcharging-stby"; + gpio = <&exp1 8 GPIO_ACTIVE_LOW>; + output-low; + }; + + top-dsp-int { + name = "top-dsp-int"; + gpio = <&exp1 15 GPIO_ACTIVE_HIGH>; + input; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-0 = <&force_bank0>; + pinctrl-names = "default"; + + button@1 { + label = "Factory Reset Button"; + linux,code = ; + gpios = <&tlmm 18 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&vendor { + bluetooth: bt_wcn3990 { + compatible = "qca,wcn3990"; + qca,bt-vdd-io-supply = <&pm8998_s3>; + qca,bt-vdd-xtal-supply = <&pm8998_s5>; + qca,bt-vdd-core-supply = <&pm8998_l7>; + qca,bt-vdd-pa-supply = <&pm8998_l17>; + qca,bt-vdd-ldo-supply = <&pm8998_l25>; + //qca,bt-chip-pwd-supply = <&pmi8998_bob_pin1>; + clocks = <&clock_gcc clk_rf_clk2_pin>; + clock-names = "rf_clk2"; + + qca,bt-vdd-io-voltage-level = <1352000 1352000>; + qca,bt-vdd-xtal-voltage-level = <2040000 2040000>; + qca,bt-vdd-core-voltage-level = <1800000 1800000>; + qca,bt-vdd-pa-voltage-level = <1304000 1304000>; + qca,bt-vdd-ldo-voltage-level = <3312000 3312000>; + qca,bt-chip-pwd-voltage-level = <3600000 3600000>; + + qca,bt-vdd-io-current-level = <1>; /* LPM/PFM */ + qca,bt-vdd-xtal-current-level = <1>; /* LPM/PFM */ + qca,bt-vdd-core-current-level = <1>; /* LPM/PFM */ + qca,bt-vdd-pa-current-level = <1>; /* LPM/PFM */ + qca,bt-vdd-ldo-current-level = <1>; /* LPM/PFM */ + }; +}; + +&blsp1_uart3_hs { + status = "ok"; +}; + +&uartblsp2dm1 { + status = "ok"; + pinctrl-names = "default"; + pinctrl-0 = <&uart_console_active>; +}; + +&ufsphy1 { + vdda-phy-supply = <&pm8998_l1>; + vdda-pll-supply = <&pm8998_l2>; + vddp-ref-clk-supply = <&pm8998_l26>; + vdda-phy-max-microamp = <51400>; + vdda-pll-max-microamp = <14600>; + vddp-ref-clk-max-microamp = <100>; + vddp-ref-clk-always-on; + status = "ok"; +}; + +&ufs1 { + vdd-hba-supply = <&gdsc_ufs>; + vdd-hba-fixed-regulator; + vcc-supply = <&pm8998_l20>; + vccq-supply = <&pm8998_l26>; + vccq2-supply = <&pm8998_s4>; + vcc-max-microamp = <750000>; + vccq-max-microamp = <560000>; + vccq2-max-microamp = <750000>; + status = "ok"; +}; + +&ufs_ice { + status = "ok"; +}; + +&i2c_5 { + status = "okay"; + + qcom,clk-freq-out = <100000>; + + // ti8020@44 + // usbmux@47 + // si2157@60 + // si2168@64 + // leadtrend@68 +}; + +&i2c_4 { + status = "okay"; + + qcom,clk-freq-out = <100000>; + + lm75@48 { + compatible = "national,lm75"; + reg = <0x48>; + }; + + tas5766@4c { + compatible = "ti,tas5766"; + reg = <0x4c>; + }; + + tas5766@4d { + compatible = "ti,tas5766"; + reg = <0x4d>; + }; + + tas5766@4e { + compatible = "ti,tas5766"; + reg = <0x4e>; + }; + + // at24_audio@53 + // at24_carrier@57 +}; + +&i2c_6 { + status = "okay"; + + qcom,clk-freq-out = <100000>; + + exp1: gpio@74 { + compatible = "ti,tca9539"; + reg = <0x74>; + gpio-controller; + #gpio-cells = <2>; + reset-gpios = <&tlmm 96 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&top_exp_rst>; + }; + + // at24_top@53 +}; + +&i2c_7 { + status = "okay"; + + wm8804@3b { + compatible = "wlf,wm8804"; + reg = <0x3b>; + wlf,reset-gpio = <&tlmm 100 GPIO_ACTIVE_HIGH>; + wlf,irq-gpio = <&tlmm 110 GPIO_ACTIVE_LOW>; + }; + + sil9437@31 { + compatible = "sil,sil9437"; + reg = <0x31>; + sil,reset-gpio = <&tlmm 12 GPIO_ACTIVE_LOW>; + sil,irq-gpio = <&tlmm 118 GPIO_ACTIVE_LOW>; + sil,irq-open-drain; + sil,irq-active-low; + }; + + // hdmi_redriver@5e +}; + +&spi_1 { + status = "okay"; + + pinctrl-0 = <&spi_1_active &spi_1b_active &top_psoc_rst>; + pinctrl-1 = <&spi_1_sleep &spi_1b_sleep &top_psoc_rst>; + cs-gpios = <&tlmm 2 GPIO_ACTIVE_HIGH>, <&tlmm 23 GPIO_ACTIVE_HIGH>, <&tlmm 23 GPIO_ACTIVE_HIGH>, <&tlmm 23 GPIO_ACTIVE_HIGH>; + + spidev@0 { + /* PSOC for LED & touch control */ + compatible = "freebox,fbx7hd-top-psoc"; + spi-max-frequency = <1200000>; + irq-gpio = <&tlmm 122 GPIO_ACTIVE_LOW>; + reset-gpio = <&tlmm 97 GPIO_ACTIVE_LOW>; + reg = <0>; + }; + + spidev@3 { + /* XMOS */ + compatible = "spidev"; + spi-max-frequency = <1200000>; + reg = <3>; + }; +}; + +&spi_9 { + status = "okay"; + switch@0 { + compatible = "realtek,rtl8367c-spi"; + reg = <0>; + reset-gpios = <&tlmm 30 GPIO_ACTIVE_LOW>; + spi-max-frequency = <5000000>; + }; +}; + +&tlmm { + force_bank0: force_bank0 { + mux { + pins = "gpio18"; + function = "gpio"; + }; + + config { + pins = "gpio18"; + drive-strength = <2>; + bias-disable; + }; + }; + + force_test_mode: force_test_mode { + mux { + pins = "gpio29"; + function = "gpio"; + }; + + config { + pins = "gpio29"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + hdmi_en: hdmi_en { + mux { + pins = "gpio17"; + function = "gpio"; + }; + + config { + pins = "gpio17"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + hdmi_fault: hdmi_fault { + mux { + pins = "gpio133"; + function = "gpio"; + }; + + config { + pins = "gpio133"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + usb_hub_rst: usb_hub_rst { + mux { + pins = "gpio24"; + function = "gpio"; + }; + + config { + pins = "gpio24"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + spdif_src_sel: spdif_src_sel { + mux { + pins = "gpio8"; + function = "gpio"; + }; + + config { + pins = "gpio8"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + top_exp_rst: top_exp_rst { + mux { + pins = "gpio96"; + function = "gpio"; + }; + + config { + pins = "gpio96"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + top_psoc_rst: top_psoc_rst { + mux { + pins = "gpio97"; + function = "gpio"; + }; + + config { + pins = "gpio97"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + ir_int: ir_int { + mux { + pins = "gpio120"; + function = "gpio"; + }; + config { + pins = "gpio120"; + drive-strength = <6>; + bias-pull-up; + }; + }; + + top_exp_psoc_irq: top_exp_psoc_irq { + mux { + pins = "gpio122"; + function = "gpio"; + }; + + config { + pins = "gpio122"; + drive-strength = <2>; + bias-pull-down; + }; + }; +}; + +&usb3 { + /delete-property/ extcon; + dwc3@a800000 { + dr_mode = "host"; + }; +}; + +&sde_hdmi { + qcom,display-type = "primary"; +}; + +&sde_hdmi_tx { + /* disable 5V HPD pin */ + /delete-property/ qcom,hdmi-tx-hpd5v-gpio; + pinctrl-0 = <&mdss_hdmi_hpd_active + &mdss_hdmi_ddc_active>; + pinctrl-1 = <&mdss_hdmi_hpd_suspend + &mdss_hdmi_ddc_suspend>; +}; + +&spmi_bus { + qcom,pmi8998@2 { + status = "disabled"; + }; + qcom,pmi8998@3 { + status = "disabled"; + }; +}; + +&pmi8998_wled { + status = "disabled"; +}; + +&pm8998_gpios { + gpio@cc00 { /* GPIO 13 */ + qcom,mode = <1>; + qcom,output-type = <0>; + qcom,pull = <5>; + qcom,vin-sel = <0>; + qcom,out-strength = <1>; + qcom,src-sel = <3>; + qcom,master-en = <1>; + status = "okay"; + }; +}; + +&pm8998_vadc { + chan@83 { + label = "vph_pwr"; + reg = <0x83>; + qcom,decimation = <2>; + qcom,pre-div-channel-scaling = <1>; + qcom,calibration-type = "absolute"; + qcom,scale-function = <0>; + qcom,hw-settle-time = <0>; + qcom,fast-avg-setup = <0>; + }; + + chan@85 { + label = "vcoin"; + reg = <0x85>; + qcom,decimation = <2>; + qcom,pre-div-channel-scaling = <1>; + qcom,calibration-type = "absolute"; + qcom,scale-function = <0>; + qcom,hw-settle-time = <0>; + qcom,fast-avg-setup = <0>; + }; + + chan@4c { + label = "xo_therm"; + reg = <0x4c>; + qcom,decimation = <2>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "ratiometric"; + qcom,scale-function = <4>; + qcom,hw-settle-time = <2>; + qcom,fast-avg-setup = <0>; + }; + + chan@4d { + label = "msm_therm"; + reg = <0x4d>; + qcom,decimation = <2>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "ratiometric"; + qcom,scale-function = <2>; + qcom,hw-settle-time = <2>; + qcom,fast-avg-setup = <0>; + }; + + chan@51 { + label = "quiet_therm"; + reg = <0x51>; + qcom,decimation = <2>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "ratiometric"; + qcom,scale-function = <2>; + qcom,hw-settle-time = <2>; + qcom,fast-avg-setup = <0>; + }; +}; + +&pm8998_adc_tm { + chan@83 { + label = "vph_pwr"; + reg = <0x83>; + qcom,pre-div-channel-scaling = <1>; + qcom,calibration-type = "absolute"; + qcom,scale-function = <0>; + qcom,hw-settle-time = <0>; + qcom,btm-channel-number = <0x60>; + }; + + chan@4d { + label = "msm_therm"; + reg = <0x4d>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "ratiometric"; + qcom,scale-function = <2>; + qcom,hw-settle-time = <2>; + qcom,btm-channel-number = <0x68>; + qcom,thermal-node; + }; + + chan@51 { + label = "quiet_therm"; + reg = <0x51>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "ratiometric"; + qcom,scale-function = <2>; + qcom,hw-settle-time = <2>; + qcom,btm-channel-number = <0x70>; + qcom,thermal-node; + }; + + chan@4c { + label = "xo_therm"; + reg = <0x4c>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "ratiometric"; + qcom,scale-function = <4>; + qcom,hw-settle-time = <2>; + qcom,btm-channel-number = <0x78>; + qcom,thermal-node; + }; +}; + +&soc { + qcom,msm-dai-tdm-sec-rx { + qcom,msm-cpudai-tdm-group-id = <37136>; + qcom,msm-cpudai-tdm-group-num-ports = <1>; + qcom,msm-cpudai-tdm-group-port-id = <36880>; + qcom,msm-cpudai-tdm-clk-rate = <12288000>; + qcom,msm-cpudai-tdm-clk-internal = <1>; + qcom,msm-cpudai-tdm-sync-mode = <1>; + qcom,msm-cpudai-tdm-sync-src = <1>; + qcom,msm-cpudai-tdm-data-out = <1>; + qcom,msm-cpudai-tdm-invert-sync = <0>; + qcom,msm-cpudai-tdm-data-delay = <0>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sec_aux_pcm_active + &sec_aux_pcm_dout_active>; + pinctrl-1 = <&sec_aux_pcm_sleep + &sec_aux_pcm_dout_sleep>; + }; + + qcom,msm-dai-mi2s { + dai_mi2s0: qcom,msm-dai-q6-mi2s-prim { + qcom,msm-mi2s-rx-lines = <1>; + qcom,msm-mi2s-tx-lines = <0>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pri_mi2s_mclk_active + &pri_mi2s_sck_active + &pri_mi2s_ws_active + &pri_mi2s_sd0_active>; + pinctrl-1 = <&pri_mi2s_mclk_sleep + &pri_mi2s_sck_sleep + &pri_mi2s_ws_sleep + &pri_mi2s_sd0_sleep>; + }; + + dai_mi2s2: qcom,msm-dai-q6-mi2s-tert { + qcom,msm-mi2s-rx-lines = <0>; + qcom,msm-mi2s-tx-lines = <1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&tert_mi2s_active + &tert_mi2s_sd0_active>; + pinctrl-1 = <&tert_mi2s_sleep + &tert_mi2s_sd0_sleep>; + }; + + dai_mi2s3: qcom,msm-dai-q6-mi2s-quat { + qcom,msm-mi2s-rx-lines = <0>; + qcom,msm-mi2s-tx-lines = <15>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&quat_mi2s_active + &quat_mi2s_sd0_active + &quat_mi2s_sd1_active + &quat_mi2s_sd2_active + &quat_mi2s_sd3_active>; + pinctrl-1 = <&quat_mi2s_sleep + &quat_mi2s_sd0_sleep + &quat_mi2s_sd1_sleep + &quat_mi2s_sd2_sleep + &quat_mi2s_sd3_sleep>; + }; + }; + + sound-freebox { + fbx,spdif-wm8804; + fbx,arc-sil9437; + }; +}; + +&soc { + qcom,bcl { + /delete-property/ qcom,bcl-enable; + }; +}; + +&pcie0 { + qcom,boot-option = <0>; +}; + +&msm_ath10k_wlan { + status = "ok"; +}; + +&tspp { + pinctrl-names = "disabled", "tsif0-mode1", "tsif0-mode2"; + + tsin0: port@0 { + tsin-num = <0>; + i2c-bus = <&i2c_5>; + reset-gpios = <&tlmm 84 GPIO_ACTIVE_LOW>; + }; +}; diff -Nruw linux-4.4.115-fbx/arch/arm/boot/dts/qcom./apq8098-freebox-oarfish.dts linux-4.4.115-fbx/arch/arm/boot/dts/qcom/apq8098-freebox-oarfish.dts --- linux-4.4.115-fbx/arch/arm/boot/dts/qcom./apq8098-freebox-oarfish.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-4.4.115-fbx/arch/arm/boot/dts/qcom/apq8098-freebox-oarfish.dts 2019-01-22 16:16:21.171225289 +0100 @@ -0,0 +1,402 @@ +/* Copyright (c) 2017, Freebox SAS. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +#include +#include +#include "apq8098-v2.1.dtsi" +#include "msm8998-audio-freebox.dtsi" + +#include "msm8998-ramoops.dtsi" + +/ { + model = "Freebox Oarfish"; + compatible = "freebox,fbx7hd-oarfish", "freebox,fbx7hd", "qcom,apq8098"; + qcom,board-id = <5 3>; + + ir: ir-receiver { + compatible = "gpio-ir-receiver"; + gpios = <&tlmm 120 1>; + pinctrl-names = "default"; + pinctrl-0 = <&ir_int>; + linux,rc-map-name = "rc-rc6-freebox"; + }; + + fbxgpio@0 { + compatible = "fbx,fbxgpio"; + + pinctrl-names = "default"; + pinctrl-0 = < + &hdmi_en + &hdmi_fault + &force_test_mode + >; + + hdmi-enable { + name = "hdmi-enable"; + gpio = <&tlmm 17 GPIO_ACTIVE_HIGH>; + output-low; + }; + + hdmi-fault { + name = "hdmi-fault"; + gpio = <&tlmm 133 GPIO_ACTIVE_LOW>; + input; + }; + + test-mode { + name = "test-mode"; + gpio = <&tlmm 29 GPIO_ACTIVE_LOW>; + input; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-0 = <&force_bank0>; + pinctrl-names = "default"; + + button@1 { + label = "Factory Reset Button"; + linux,code = ; + gpios = <&tlmm 18 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&vendor { + bluetooth: bt_wcn3990 { + compatible = "qca,wcn3990"; + qca,bt-vdd-io-supply = <&pm8998_s3>; + qca,bt-vdd-xtal-supply = <&pm8998_s5>; + qca,bt-vdd-core-supply = <&pm8998_l7>; + qca,bt-vdd-pa-supply = <&pm8998_l17>; + qca,bt-vdd-ldo-supply = <&pm8998_l25>; + //qca,bt-chip-pwd-supply = <&pmi8998_bob_pin1>; + clocks = <&clock_gcc clk_rf_clk2_pin>; + clock-names = "rf_clk2"; + + qca,bt-vdd-io-voltage-level = <1352000 1352000>; + qca,bt-vdd-xtal-voltage-level = <2040000 2040000>; + qca,bt-vdd-core-voltage-level = <1800000 1800000>; + qca,bt-vdd-pa-voltage-level = <1304000 1304000>; + qca,bt-vdd-ldo-voltage-level = <3312000 3312000>; + qca,bt-chip-pwd-voltage-level = <3600000 3600000>; + + qca,bt-vdd-io-current-level = <1>; /* LPM/PFM */ + qca,bt-vdd-xtal-current-level = <1>; /* LPM/PFM */ + qca,bt-vdd-core-current-level = <1>; /* LPM/PFM */ + qca,bt-vdd-pa-current-level = <1>; /* LPM/PFM */ + qca,bt-vdd-ldo-current-level = <1>; /* LPM/PFM */ + }; +}; + +&blsp1_uart3_hs { + status = "ok"; +}; + +&uartblsp2dm1 { + status = "ok"; + pinctrl-names = "default"; + pinctrl-0 = <&uart_console_active>; +}; + +&ufsphy1 { + vdda-phy-supply = <&pm8998_l1>; + vdda-pll-supply = <&pm8998_l2>; + vddp-ref-clk-supply = <&pm8998_l26>; + vdda-phy-max-microamp = <51400>; + vdda-pll-max-microamp = <14600>; + vddp-ref-clk-max-microamp = <100>; + vddp-ref-clk-always-on; + status = "ok"; +}; + +&ufs1 { + vdd-hba-supply = <&gdsc_ufs>; + vdd-hba-fixed-regulator; + vcc-supply = <&pm8998_l20>; + vccq-supply = <&pm8998_l26>; + vccq2-supply = <&pm8998_s4>; + vcc-max-microamp = <750000>; + vccq-max-microamp = <560000>; + vccq2-max-microamp = <750000>; + status = "ok"; +}; + +&ufs_ice { + status = "ok"; +}; + +&i2c_5 { + status = "okay"; + + qcom,clk-freq-out = <100000>; + + // usbmux@47 + // si2168@64 +}; + +&i2c_4 { + status = "okay"; + + qcom,clk-freq-out = <100000>; + + // at24_carrier@57 +}; + +&i2c_7 { + status = "okay"; + + // hdmi_redriver@5e +}; + +&tlmm { + force_bank0: force_bank0 { + mux { + pins = "gpio18"; + function = "gpio"; + }; + + config { + pins = "gpio18"; + drive-strength = <2>; + bias-disable; + }; + }; + + force_test_mode: force_test_mode { + mux { + pins = "gpio29"; + function = "gpio"; + }; + + config { + pins = "gpio29"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + hdmi_en: hdmi_en { + mux { + pins = "gpio17"; + function = "gpio"; + }; + + config { + pins = "gpio17"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + hdmi_fault: hdmi_fault { + mux { + pins = "gpio133"; + function = "gpio"; + }; + + config { + pins = "gpio133"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + ir_int: ir_int { + mux { + pins = "gpio120"; + function = "gpio"; + }; + config { + pins = "gpio120"; + drive-strength = <6>; + bias-pull-up; + }; + }; +}; + +&usb3 { + /delete-property/ extcon; + dwc3@a800000 { + dr_mode = "host"; + }; +}; + +&sde_hdmi { + qcom,display-type = "primary"; +}; + +&sde_hdmi_tx { + /* disable 5V HPD pin */ + /delete-property/ qcom,hdmi-tx-hpd5v-gpio; + pinctrl-0 = <&mdss_hdmi_hpd_active + &mdss_hdmi_ddc_active>; + pinctrl-1 = <&mdss_hdmi_hpd_suspend + &mdss_hdmi_ddc_suspend>; +}; + +&spmi_bus { + qcom,pmi8998@2 { + status = "disabled"; + }; + qcom,pmi8998@3 { + status = "disabled"; + }; +}; + +&pmi8998_wled { + status = "disabled"; +}; + +&pm8998_gpios { + gpio@cc00 { /* GPIO 13 */ + qcom,mode = <1>; + qcom,output-type = <0>; + qcom,pull = <5>; + qcom,vin-sel = <0>; + qcom,out-strength = <1>; + qcom,src-sel = <3>; + qcom,master-en = <1>; + status = "okay"; + }; +}; + +&pm8998_vadc { + chan@83 { + label = "vph_pwr"; + reg = <0x83>; + qcom,decimation = <2>; + qcom,pre-div-channel-scaling = <1>; + qcom,calibration-type = "absolute"; + qcom,scale-function = <0>; + qcom,hw-settle-time = <0>; + qcom,fast-avg-setup = <0>; + }; + + chan@85 { + label = "vcoin"; + reg = <0x85>; + qcom,decimation = <2>; + qcom,pre-div-channel-scaling = <1>; + qcom,calibration-type = "absolute"; + qcom,scale-function = <0>; + qcom,hw-settle-time = <0>; + qcom,fast-avg-setup = <0>; + }; + + chan@4c { + label = "xo_therm"; + reg = <0x4c>; + qcom,decimation = <2>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "ratiometric"; + qcom,scale-function = <4>; + qcom,hw-settle-time = <2>; + qcom,fast-avg-setup = <0>; + }; + + chan@4d { + label = "msm_therm"; + reg = <0x4d>; + qcom,decimation = <2>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "ratiometric"; + qcom,scale-function = <2>; + qcom,hw-settle-time = <2>; + qcom,fast-avg-setup = <0>; + }; + + chan@51 { + label = "quiet_therm"; + reg = <0x51>; + qcom,decimation = <2>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "ratiometric"; + qcom,scale-function = <2>; + qcom,hw-settle-time = <2>; + qcom,fast-avg-setup = <0>; + }; +}; + +&pm8998_adc_tm { + chan@83 { + label = "vph_pwr"; + reg = <0x83>; + qcom,pre-div-channel-scaling = <1>; + qcom,calibration-type = "absolute"; + qcom,scale-function = <0>; + qcom,hw-settle-time = <0>; + qcom,btm-channel-number = <0x60>; + }; + + chan@4d { + label = "msm_therm"; + reg = <0x4d>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "ratiometric"; + qcom,scale-function = <2>; + qcom,hw-settle-time = <2>; + qcom,btm-channel-number = <0x68>; + qcom,thermal-node; + }; + + chan@51 { + label = "quiet_therm"; + reg = <0x51>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "ratiometric"; + qcom,scale-function = <2>; + qcom,hw-settle-time = <2>; + qcom,btm-channel-number = <0x70>; + qcom,thermal-node; + }; + + chan@4c { + label = "xo_therm"; + reg = <0x4c>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "ratiometric"; + qcom,scale-function = <4>; + qcom,hw-settle-time = <2>; + qcom,btm-channel-number = <0x78>; + qcom,thermal-node; + }; +}; + +&soc { + qcom,bcl { + /delete-property/ qcom,bcl-enable; + }; +}; + +&pcie0 { + qcom,boot-option = <0>; +}; + +&msm_ath10k_wlan { + status = "ok"; +}; + +&tspp { + pinctrl-names = "disabled", "tsif0-mode1", "tsif0-mode2"; + + tsin0: port@0 { + tsin-num = <0>; + i2c-bus = <&i2c_5>; + reset-gpios = <&tlmm 84 GPIO_ACTIVE_LOW>; + }; +}; diff -Nruw linux-4.4.115-fbx/arch/arm/boot/dts/qcom./apq8098-freebox-proto.dts linux-4.4.115-fbx/arch/arm/boot/dts/qcom/apq8098-freebox-proto.dts --- linux-4.4.115-fbx/arch/arm/boot/dts/qcom./apq8098-freebox-proto.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-4.4.115-fbx/arch/arm/boot/dts/qcom/apq8098-freebox-proto.dts 2019-01-22 16:16:21.171225289 +0100 @@ -0,0 +1,515 @@ +/* Copyright (c) 2017, Freebox SAS. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +#include +#include "apq8098-v2.1.dtsi" +#include "msm8998-audio-freebox.dtsi" + +#include "msm8998-ramoops.dtsi" + +/ { + model = "Freebox Test Carrier"; + compatible = "freebox,fbx7hd-carrier", "freebox,fbx7hd", "qcom,apq8098"; + qcom,board-id = <5 1>; + + ir: ir-receiver { + compatible = "gpio-ir-receiver"; + gpios = <&tlmm 120 1>; + pinctrl-names = "default"; + pinctrl-0 = <&ir_int>; + linux,rc-map-name = "rc-rc6-freebox"; + }; + + fbxgpio@0 { + compatible = "fbx,fbxgpio"; + + pinctrl-names = "default"; + pinctrl-0 = < + &hdmi_fault + &nfc_enable + &nfc_int + >; + + hdmi-fault { + name = "hdmi-fault"; + gpio = <&tlmm 133 GPIO_ACTIVE_LOW>; + input; + }; + + nfcc-enable { + name = "nfcc-enable"; + gpio = <&tlmm 96 GPIO_ACTIVE_HIGH>; + output-low; + }; + + nfcc-irq { + name = "nfcc-irq"; + gpio = <&tlmm 97 GPIO_ACTIVE_HIGH>; + input; + }; + }; +}; + +&vendor { + bluetooth: bt_wcn3990 { + compatible = "qca,wcn3990"; + qca,bt-vdd-io-supply = <&pm8998_s3>; + qca,bt-vdd-xtal-supply = <&pm8998_s5>; + qca,bt-vdd-core-supply = <&pm8998_l7>; + qca,bt-vdd-pa-supply = <&pm8998_l17>; + qca,bt-vdd-ldo-supply = <&pm8998_l25>; + //qca,bt-chip-pwd-supply = <&pmi8998_bob_pin1>; + clocks = <&clock_gcc clk_rf_clk2_pin>; + clock-names = "rf_clk2"; + + qca,bt-vdd-io-voltage-level = <1352000 1352000>; + qca,bt-vdd-xtal-voltage-level = <2040000 2040000>; + qca,bt-vdd-core-voltage-level = <1800000 1800000>; + qca,bt-vdd-pa-voltage-level = <1304000 1304000>; + qca,bt-vdd-ldo-voltage-level = <3312000 3312000>; + qca,bt-chip-pwd-voltage-level = <3600000 3600000>; + + qca,bt-vdd-io-current-level = <1>; /* LPM/PFM */ + qca,bt-vdd-xtal-current-level = <1>; /* LPM/PFM */ + qca,bt-vdd-core-current-level = <1>; /* LPM/PFM */ + qca,bt-vdd-pa-current-level = <1>; /* LPM/PFM */ + qca,bt-vdd-ldo-current-level = <1>; /* LPM/PFM */ + }; +}; + +&blsp1_uart3_hs { + status = "ok"; +}; + +&uartblsp2dm1 { + status = "ok"; + pinctrl-names = "default"; + pinctrl-0 = <&uart_console_active>; +}; + +&ufsphy1 { + vdda-phy-supply = <&pm8998_l1>; + vdda-pll-supply = <&pm8998_l2>; + vddp-ref-clk-supply = <&pm8998_l26>; + vdda-phy-max-microamp = <51400>; + vdda-pll-max-microamp = <14600>; + vddp-ref-clk-max-microamp = <100>; + vddp-ref-clk-always-on; + status = "ok"; +}; + +&ufs1 { + vdd-hba-supply = <&gdsc_ufs>; + vdd-hba-fixed-regulator; + vcc-supply = <&pm8998_l20>; + vccq-supply = <&pm8998_l26>; + vccq2-supply = <&pm8998_s4>; + vcc-max-microamp = <750000>; + vccq-max-microamp = <560000>; + vccq2-max-microamp = <750000>; + status = "ok"; +}; + +&ufs_ice { + status = "ok"; +}; + +&i2c_5 { + status = "okay"; + // si2168@64 +}; + +&i2c_4 { + status = "okay"; + + qcom,clk-freq-out = <100000>; + + lm75@48 { + compatible = "national,lm75"; + reg = <0x48>; + }; + + tas5766@4c { + compatible = "ti,tas5766"; + reg = <0x4c>; + }; + + tas5766@4d { + compatible = "ti,tas5766"; + reg = <0x4d>; + }; + + tas5766@4e { + compatible = "ti,tas5766"; + reg = <0x4e>; + }; +}; + +&i2c_6 { + status = "okay"; +}; + +&i2c_7 { + status = "okay"; + + wm8804@3b { + compatible = "wlf,wm8804"; + reg = <0x3b>; + wlf,reset-gpio = <&tlmm 100 GPIO_ACTIVE_HIGH>; + }; + + sil9437@31 { + compatible = "sil,sil9437"; + reg = <0x31>; + sil,reset-gpio = <&tlmm 12 GPIO_ACTIVE_LOW>; + sil,irq-gpio = <&tlmm 118 GPIO_ACTIVE_LOW>; + sil,irq-open-drain; + sil,irq-active-low; + }; + + /delete-node/ qcom,smb138x@8; +}; + +&spi_9 { + status = "okay"; + switch@0 { + compatible = "realtek,rtl8367c-spi"; + reg = <0>; + reset-gpios = <&tlmm 30 GPIO_ACTIVE_LOW>; + spi-max-frequency = <5000000>; + }; +}; + +&spi_10 { + status = "disabled"; +}; + +&tlmm { + cdc_reset_ctrl_batfish { + cdc_reset_batfish_sleep: cdc_reset_batfish_sleep { + mux { + pins = "gpio25"; + function = "gpio"; + }; + config { + pins = "gpio25"; + drive-strength = <16>; + bias-disable; + output-low; + }; + }; + cdc_reset_batfish_active:cdc_reset_batfish_active { + mux { + pins = "gpio25"; + function = "gpio"; + }; + config { + pins = "gpio25"; + drive-strength = <16>; + bias-pull-down; + output-high; + }; + }; + }; + + nfc { + nfc_enable: nfc_enable { + mux { + pins = "gpio96"; + function = "gpio"; + }; + + config { + pins = "gpio96"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + nfc_int: nfc_int { + mux { + pins = "gpio97"; + function = "gpio"; + }; + + config { + pins = "gpio97"; + drive-strength = <2>; + bias-pull-down; + }; + }; + }; + + hdmi_fault: hdmi_fault { + mux { + pins = "gpio133"; + function = "gpio"; + }; + + config { + pins = "gpio133"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + ir_int: ir_int { + mux { + pins = "gpio120"; + function = "gpio"; + }; + config { + pins = "gpio120"; + drive-strength = <6>; + bias-pull-up; + }; + }; +}; + +&usb3 { + /delete-property/ extcon; + dwc3@a800000 { + dr_mode = "host"; + }; +}; + +&sde_hdmi { + qcom,display-type = "primary"; +}; + +&sde_hdmi_tx { + /* disable 5V HPD pin */ + /delete-property/ qcom,hdmi-tx-hpd5v-gpio; + pinctrl-0 = <&mdss_hdmi_hpd_active + &mdss_hdmi_ddc_active>; + pinctrl-1 = <&mdss_hdmi_hpd_suspend + &mdss_hdmi_ddc_suspend>; +}; + +&spmi_bus { + qcom,pmi8998@2 { + status = "disabled"; + }; + qcom,pmi8998@3 { + status = "disabled"; + }; +}; + +&pmi8998_wled { + status = "disabled"; +}; + +&pm8998_gpios { + gpio@cc00 { /* GPIO 13 */ + qcom,mode = <1>; + qcom,output-type = <0>; + qcom,pull = <5>; + qcom,vin-sel = <0>; + qcom,out-strength = <1>; + qcom,src-sel = <3>; + qcom,master-en = <1>; + status = "okay"; + }; +}; + +&pm8998_vadc { + chan@83 { + label = "vph_pwr"; + reg = <0x83>; + qcom,decimation = <2>; + qcom,pre-div-channel-scaling = <1>; + qcom,calibration-type = "absolute"; + qcom,scale-function = <0>; + qcom,hw-settle-time = <0>; + qcom,fast-avg-setup = <0>; + }; + + chan@85 { + label = "vcoin"; + reg = <0x85>; + qcom,decimation = <2>; + qcom,pre-div-channel-scaling = <1>; + qcom,calibration-type = "absolute"; + qcom,scale-function = <0>; + qcom,hw-settle-time = <0>; + qcom,fast-avg-setup = <0>; + }; + + chan@4c { + label = "xo_therm"; + reg = <0x4c>; + qcom,decimation = <2>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "ratiometric"; + qcom,scale-function = <4>; + qcom,hw-settle-time = <2>; + qcom,fast-avg-setup = <0>; + }; + + chan@4d { + label = "msm_therm"; + reg = <0x4d>; + qcom,decimation = <2>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "ratiometric"; + qcom,scale-function = <2>; + qcom,hw-settle-time = <2>; + qcom,fast-avg-setup = <0>; + }; + + chan@51 { + label = "quiet_therm"; + reg = <0x51>; + qcom,decimation = <2>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "ratiometric"; + qcom,scale-function = <2>; + qcom,hw-settle-time = <2>; + qcom,fast-avg-setup = <0>; + }; +}; + +&pm8998_adc_tm { + chan@83 { + label = "vph_pwr"; + reg = <0x83>; + qcom,pre-div-channel-scaling = <1>; + qcom,calibration-type = "absolute"; + qcom,scale-function = <0>; + qcom,hw-settle-time = <0>; + qcom,btm-channel-number = <0x60>; + }; + + chan@4d { + label = "msm_therm"; + reg = <0x4d>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "ratiometric"; + qcom,scale-function = <2>; + qcom,hw-settle-time = <2>; + qcom,btm-channel-number = <0x68>; + qcom,thermal-node; + }; + + chan@51 { + label = "quiet_therm"; + reg = <0x51>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "ratiometric"; + qcom,scale-function = <2>; + qcom,hw-settle-time = <2>; + qcom,btm-channel-number = <0x70>; + qcom,thermal-node; + }; + + chan@4c { + label = "xo_therm"; + reg = <0x4c>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "ratiometric"; + qcom,scale-function = <4>; + qcom,hw-settle-time = <2>; + qcom,btm-channel-number = <0x78>; + qcom,thermal-node; + }; +}; + +&soc { + qcom,msm-dai-tdm-sec-rx { + qcom,msm-cpudai-tdm-group-id = <37136>; + qcom,msm-cpudai-tdm-group-num-ports = <1>; + qcom,msm-cpudai-tdm-group-port-id = <36880>; + qcom,msm-cpudai-tdm-clk-rate = <12288000>; + qcom,msm-cpudai-tdm-clk-internal = <1>; + qcom,msm-cpudai-tdm-sync-mode = <1>; + qcom,msm-cpudai-tdm-sync-src = <1>; + qcom,msm-cpudai-tdm-data-out = <1>; + qcom,msm-cpudai-tdm-invert-sync = <0>; + qcom,msm-cpudai-tdm-data-delay = <0>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sec_aux_pcm_active + &sec_aux_pcm_dout_active>; + pinctrl-1 = <&sec_aux_pcm_sleep + &sec_aux_pcm_dout_sleep>; + }; + + qcom,msm-dai-mi2s { + dai_mi2s0: qcom,msm-dai-q6-mi2s-prim { + qcom,msm-mi2s-rx-lines = <1>; + qcom,msm-mi2s-tx-lines = <0>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pri_mi2s_sck_active + &pri_mi2s_ws_active + &pri_mi2s_sd0_active>; + pinctrl-1 = <&pri_mi2s_sck_sleep + &pri_mi2s_ws_sleep + &pri_mi2s_sd0_sleep>; + }; + + dai_mi2s2: qcom,msm-dai-q6-mi2s-tert { + qcom,msm-mi2s-rx-lines = <0>; + qcom,msm-mi2s-tx-lines = <1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&tert_mi2s_active + &tert_mi2s_sd0_active>; + pinctrl-1 = <&tert_mi2s_sleep + &tert_mi2s_sd0_sleep>; + }; + + dai_mi2s3: qcom,msm-dai-q6-mi2s-quat { + qcom,msm-mi2s-rx-lines = <0>; + qcom,msm-mi2s-tx-lines = <15>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&quat_mi2s_active + &quat_mi2s_sd0_active + &quat_mi2s_sd1_active + &quat_mi2s_sd2_active + &quat_mi2s_sd3_active>; + pinctrl-1 = <&quat_mi2s_sleep + &quat_mi2s_sd0_sleep + &quat_mi2s_sd1_sleep + &quat_mi2s_sd2_sleep + &quat_mi2s_sd3_sleep>; + }; + }; + + sound-freebox { + fbx,spdif-wm8804; + fbx,arc-sil9437; + }; +}; + +&soc { + qcom,bcl { + /delete-property/ qcom,bcl-enable; + }; +}; + +&pcie0 { + qcom,boot-option = <0>; +}; + +&msm_ath10k_wlan { + status = "ok"; +}; + +&tspp { + pinctrl-names = "disabled", "tsif0-mode1", "tsif0-mode2"; + + tsin0: port@0 { + tsin-num = <0>; + i2c-bus = <&i2c_5>; + reset-gpios = <&tlmm 84 GPIO_ACTIVE_LOW>; + }; +}; diff -Nruw linux-4.4.115-fbx/arch/arm/boot/dts/qcom./apq8098-v2.1.dtsi linux-4.4.115-fbx/arch/arm/boot/dts/qcom/apq8098-v2.1.dtsi --- linux-4.4.115-fbx/arch/arm/boot/dts/qcom./apq8098-v2.1.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ linux-4.4.115-fbx/arch/arm/boot/dts/qcom/apq8098-v2.1.dtsi 2019-01-22 16:16:21.171225289 +0100 @@ -0,0 +1,28 @@ +/* Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "msm8998-v2.1.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. APQ 8098 V2.1"; + qcom,msm-id = <319 0x20001>; +}; + +&soc { + qcom,rmnet-ipa { + status = "disabled"; + }; +}; + +&ipa_hw { + status = "disabled"; +}; diff -Nruw linux-4.4.115-fbx/arch/arm/boot/dts/qcom./apq8098-v2.1-mediabox.dts linux-4.4.115-fbx/arch/arm/boot/dts/qcom/apq8098-v2.1-mediabox.dts --- linux-4.4.115-fbx/arch/arm/boot/dts/qcom./apq8098-v2.1-mediabox.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-4.4.115-fbx/arch/arm/boot/dts/qcom/apq8098-v2.1-mediabox.dts 2019-10-29 09:26:22.905195956 +0100 @@ -0,0 +1,222 @@ +/* Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +#include "apq8098-v2.1.dtsi" +#include "msm8998-cdp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. APQ 8098 V2.1 mediabox"; + compatible = "qcom,apq8098-cdp", "qcom,apq8098", "qcom,cdp"; + qcom,board-id = <8 1>; +}; + +&spi_10 { + status = "disabled"; +}; + +&pcie0 { + /delete-property/ qcom,boot-option; +}; + +&msm_ath10k_wlan { + status = "ok"; +}; + +&sde_hdmi { + qcom,display-type = "primary"; +}; + +&slim_aud { + tasha_codec { + wsa_spkr_sd1: msm_cdc_pinctrll { + compatible = "qcom,msm-cdc-pinctrl"; + pinctrl-names = "aud_active", "aud_sleep"; + pinctrl-0 = <&spkr_1_sd_active_mediabox>; + pinctrl-1 = <&spkr_1_sd_sleep_mediabox>; + }; + + wsa_spkr_sd2: msm_cdc_pinctrlr { + compatible = "qcom,msm-cdc-pinctrl"; + pinctrl-names = "aud_active", "aud_sleep"; + pinctrl-0 = <&spkr_2_sd_active_mediabox>; + pinctrl-1 = <&spkr_2_sd_sleep_mediabox>; + }; + }; +}; + +&sdhc_2 { + vdd-supply = <&pm8998_l21>; + qcom,vdd-voltage-level = <2950000 2960000>; + qcom,vdd-current-level = <200 800000>; + + vdd-io-supply = <&pm8998_l13>; + qcom,vdd-io-voltage-level = <1808000 2960000>; + qcom,vdd-io-current-level = <200 22000>; + + pinctrl-names = "active", "sleep"; + pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on + &sdc2_cd_on_mediabox>; + pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off + &sdc2_cd_off_mediabox>; + + qcom,clk-rates = <400000 20000000 25000000 + 50000000 100000000 200000000>; + qcom,bus-speed-mode = "SDR12", "SDR25", "SDR50", "DDR50", "SDR104"; + + cd-gpios = <&tlmm 86 0x1>; + + status = "ok"; +}; + +&tspp { + qcom,lpass-timer-tts = <1>; +}; + +&snd_9335 { + qcom,msm-mi2s-master = <1>, <1>, <1>, <0>; + qcom,msm-mbhc-hphl-swh = <1>; +}; + +&wcd_usbc_analog_en1_gpio { + status = "disabled"; +}; + +&wcd_usbc_analog_en2n_gpio { + status = "disabled"; +}; + +&pcie0 { + qcom,boot-option = <0x0>; +}; + +&soc { + qcom,msm-dai-mi2s { + dai_mi2s3: qcom,msm-dai-q6-mi2s-quat { + /* SD0 (1 << 0) | SD1 (1 << 1) | SD2 (1 << 2) */ + qcom,msm-mi2s-rx-lines = <0>; + qcom,msm-mi2s-tx-lines = <15>; /* SD3 (1 << 3) */ + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&quat_mi2s_active &quat_mi2s_sd0_active + &quat_mi2s_sd1_active + &quat_mi2s_sd2_active + &quat_mi2s_sd3_active>; + pinctrl-1 = <&quat_mi2s_sleep &quat_mi2s_sd0_sleep + &quat_mi2s_sd1_sleep + &quat_mi2s_sd2_sleep + &quat_mi2s_sd3_sleep>; + }; + }; + + ir: ir-receiver { + compatible = "gpio-ir-receiver"; + gpios = <&tlmm 120 1>; + pinctrl-names = "default"; + pinctrl-0 = <&ir_int>; + linux,rc-map-name = "rc-rc6-freebox"; + }; +}; + +&tlmm { + ir_int: ir_int { + mux { + pins = "gpio120"; + function = "gpio"; + }; + config { + pins = "gpio120"; + drive-strength = <6>; + bias-pull-up; + }; + }; + + spkr_1_sd_mediabox { + spkr_1_sd_sleep_mediabox: spkr_1_sd_sleep_mediabox { + mux { + pins = "gpio85"; + function = "gpio"; + }; + config { + pins = "gpio85"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; + input-enable; + }; + }; + spkr_1_sd_active_mediabox: spkr_1_sd_active_mediabox { + mux { + pins = "gpio85"; + function = "gpio"; + }; + config { + pins = "gpio85"; + drive-strength = <8>; /* 8 mA */ + bias-disable; + output-high; + }; + }; + }; + + spkr_2_sd_mediabox_mediabox { + spkr_2_sd_sleep_mediabox: spkr_2_sd_sleep_mediabox { + mux { + pins = "gpio112"; + function = "gpio"; + }; + config { + pins = "gpio112"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; + input-enable; + }; + }; + spkr_2_sd_active_mediabox: spkr_2_sd_active_mediabox { + mux { + pins = "gpio112"; + function = "gpio"; + }; + config { + pins = "gpio112"; + drive-strength = <8>; /* 8 mA */ + bias-disable; + output-high; + }; + }; + }; + + sdc2_cd_on_mediabox: sdc2_cd_on_mediabox { + mux { + pins = "gpio86"; + function = "gpio"; + }; + + config { + pins = "gpio86"; + bias-pull-up; /* pull up */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + sdc2_cd_off_mediabox: sdc2_cd_off_mediabox { + mux { + pins = "gpio86"; + function = "gpio"; + }; + + config { + pins = "gpio86"; + bias-pull-up; /* pull up */ + drive-strength = <2>; /* 2 MA */ + }; + }; +}; diff -Nruw linux-4.4.115-fbx/arch/arm/boot/dts/qcom./Makefile linux-4.4.115-fbx/arch/arm/boot/dts/qcom/Makefile --- linux-4.4.115-fbx/arch/arm/boot/dts/qcom./Makefile 1970-01-01 01:00:00.000000000 +0100 +++ linux-4.4.115-fbx/arch/arm/boot/dts/qcom/Makefile 2019-10-29 09:26:22.901195917 +0100 @@ -0,0 +1,263 @@ +dtb-$(CONFIG_ARCH_MSM8996) += msm8996-v2-pmi8994-cdp.dtb \ + msm8996-v2-pmi8994-mtp.dtb \ + msm8996-v2-pmi8994-pmk8001-cdp.dtb \ + msm8996-v2-pmi8994-pmk8001-mtp.dtb \ + msm8996-v2-pmi8994-pm8004-cdp.dtb \ + msm8996-v2-pmi8994-pm8004-mtp.dtb \ + msm8996-v2-pmi8994-pm8004-pmk8001-cdp.dtb \ + msm8996-v2-pmi8994-pm8004-pmk8001-mtp.dtb \ + msm8996-v2-fluid.dtb \ + msm8996-v2-liquid.dtb \ + msm8996-v2-dtp.dtb \ + msm8996-v3-auto-cdp.dtb \ + msm8996-v3-auto-adp.dtb \ + msm8996-v3-pmi8994-cdp.dtb \ + msm8996-v3-pmi8994-mtp.dtb \ + msm8996-v3-pmi8994-pmk8001-cdp.dtb \ + msm8996-v3-pmi8994-pmk8001-mtp.dtb \ + msm8996-v3-pmi8994-pm8004-cdp.dtb \ + msm8996-v3-pmi8994-pm8004-mtp.dtb \ + msm8996-v3-pmi8994-pm8004-pmk8001-cdp.dtb \ + msm8996-v3-pmi8994-pm8004-pmk8001-mtp.dtb \ + msm8996-v3-pmi8996-cdp.dtb \ + msm8996-v3-pmi8996-mtp.dtb \ + msm8996-v3-pmi8996-pmk8001-cdp.dtb \ + msm8996-v3-pmi8996-pmk8001-mtp.dtb \ + msm8996-v3-fluid.dtb \ + msm8996-v3-liquid.dtb \ + msm8996-v3-dtp.dtb \ + msm8996-v3-pm8004-mmxf-adp.dtb \ + msm8996-v3-pm8004-agave-adp.dtb \ + msm8996-v3-pm8004-agave-adp-lite.dtb \ + msm8996pro-auto-adp.dtb \ + msm8996pro-auto-adp-lite.dtb \ + msm8996pro-auto-cdp.dtb \ + msm8996pro-auto-cv2x.dtb \ + msm8996pro-pmi8994-cdp.dtb \ + msm8996pro-pmi8994-mtp.dtb \ + msm8996pro-pmi8994-pmk8001-cdp.dtb \ + msm8996pro-pmi8994-pmk8001-mtp.dtb \ + msm8996pro-pmi8994-pm8004-cdp.dtb \ + msm8996pro-pmi8994-pm8004-mtp.dtb \ + msm8996pro-pmi8994-pm8004-pmk8001-cdp.dtb \ + msm8996pro-pmi8994-pm8004-pmk8001-mtp.dtb \ + msm8996pro-pmi8996-cdp.dtb \ + msm8996pro-pmi8996-mtp.dtb \ + msm8996pro-pmi8996-pmk8001-cdp.dtb \ + msm8996pro-pmi8996-pmk8001-mtp.dtb \ + msm8996pro-v1.1-auto-cdp.dtb \ + msm8996pro-v1.1-pmi8994-cdp.dtb \ + msm8996pro-v1.1-pmi8994-mtp.dtb \ + msm8996pro-v1.1-pmi8994-pmk8001-cdp.dtb \ + msm8996pro-v1.1-pmi8994-pmk8001-mtp.dtb \ + msm8996pro-v1.1-pmi8994-pm8004-cdp.dtb \ + msm8996pro-v1.1-pmi8994-pm8004-mtp.dtb \ + msm8996pro-v1.1-pmi8994-pm8004-pmk8001-cdp.dtb \ + msm8996pro-v1.1-pmi8994-pm8004-pmk8001-mtp.dtb \ + msm8996pro-v1.1-pmi8996-cdp.dtb \ + msm8996pro-v1.1-pmi8996-mtp.dtb \ + msm8996pro-v1.1-pmi8996-pmk8001-cdp.dtb \ + msm8996pro-v1.1-pmi8996-pmk8001-mtp.dtb \ + apq8096pro-auto-cdp.dtb \ + apq8096pro-v1.1-auto-adp.dtb \ + apq8096pro-v1.1-auto-adp-lite.dtb \ + apq8096pro-liquid.dtb \ + apq8096pro-v1.1-auto-cdp.dtb \ + msm8996-v3.0-pmi8994-cdp.dtb \ + msm8996-v3.0-pmi8994-mtp.dtb \ + msm8996-v3.0-pmi8994-pm8004-cdp.dtb \ + msm8996-v3.0-pmi8994-pm8004-mtp.dtb \ + msm8996-v3.0-pmi8994-pm8004-pmk8001-cdp.dtb \ + msm8996-v3.0-pmi8994-pmk8001-cdp.dtb \ + msm8996-v3.0-pmi8996-cdp.dtb \ + msm8996-v3.0-pmi8996-mtp.dtb \ + msm8996-v3.0-fluid.dtb \ + msm8996-v3.0-liquid.dtb \ + msm8996-v3.0-dtp.dtb \ + apq8096-v2-pmi8994-cdp.dtb \ + apq8096-v2-pmi8994-mtp.dtb \ + apq8096-v2-pmi8994-pmk8001-cdp.dtb \ + apq8096-v2-pmi8994-pm8004-cdp.dtb \ + apq8096-v2-pmi8994-pm8004-pmk8001-cdp.dtb \ + apq8096-v2-liquid.dtb \ + apq8096-v2-dragonboard.dtb \ + apq8096-v2-auto-dragonboard.dtb \ + apq8096-v3-pmi8994-cdp.dtb \ + apq8096-v3-pmi8994-mtp.dtb \ + apq8096-v3-pmi8994-pmk8001-cdp.dtb \ + apq8096-v3-pmi8994-pm8004-cdp.dtb \ + apq8096-v3-pmi8994-pm8004-pmk8001-cdp.dtb \ + apq8096-v3-pmi8996-cdp.dtb \ + apq8096-v3-pmi8996-mtp.dtb \ + apq8096-v3-liquid.dtb \ + apq8096-v3-dragonboard.dtb \ + apq8096-v3-sbc.dtb \ + apq8096-v3-auto-dragonboard.dtb \ + apq8096-v3-auto-adp.dtb \ + apq8096-v3-auto-cdp.dtb \ + apq8096-v3.0-pmi8994-cdp.dtb \ + apq8096-v3.0-pmi8994-mtp.dtb \ + apq8096-v3.0-pmi8994-pm8004-cdp.dtb \ + apq8096-v3.0-pmi8994-pm8004-pmk8001-cdp.dtb \ + apq8096-v3.0-pmi8994-pmk8001-cdp.dtb \ + apq8096-v3.0-pmi8996-cdp.dtb \ + apq8096-v3.0-pmi8996-mtp.dtb \ + apq8096-v3.0-liquid.dtb \ + apq8096-v3.0-dragonboard.dtb \ + apq8096-v3-pmi8994-mdm9x55-i2s-cdp.dtb \ + apq8096-v3-pmi8994-pm8004-mdm9x55-i2s-cdp.dtb \ + apq8096-v3-pmi8994-pm8004-pmk8001-mdm9x55-i2s-cdp.dtb \ + apq8096-v3-pmi8994-pmk8001-mdm9x55-i2s-cdp.dtb \ + apq8096-v3-pmi8996-mdm9x55-i2s-cdp.dtb \ + apq8096-v3-pmi8994-mdm9x55-i2s-mtp.dtb \ + apq8096-v3-pmi8994-mdm9x55-slimbus-mtp.dtb \ + apq8096-v3-pmi8996-mdm9x55-i2s-mtp.dtb \ + apq8096-v3-pmi8996-mdm9x55-slimbus-mtp.dtb \ + apq8096-v3-pmi8996-dragonboard.dtb \ + msm8996-auto-mizar.dtb + +dtb-$(CONFIG_MSM_GVM_QUIN) += vplatform-lfv-msm8996-telematics.dtb \ + vplatform-lfv-msm8996-ivi.dtb \ + vplatform-lfv-msm8996-baseline.dtb \ + vplatform-lfv-msm8996-ivi-la.dtb \ + vplatform-lfv-msm8996-ivi-lv-mt.dtb + +dtb-$(CONFIG_ARCH_MSM8998) += \ + apq8098-v2.1-mediabox.dtb \ + apq8098-freebox-proto.dtb \ + apq8098-freebox-oarfish.dtb \ + apq8098-freebox-batfish.dtb + +dtb-$(CONFIG_ARCH_MSMHAMSTER) += msmhamster-rumi.dtb + +dtb-$(CONFIG_ARCH_SDM660) += sdm660-sim.dtb \ + sdm660-internal-codec-cdp.dtb \ + sdm660-internal-codec-mtp.dtb \ + sdm660-internal-codec-rcm.dtb \ + sdm660-cdp.dtb \ + sdm660-mtp.dtb \ + sdm660-qrd.dtb \ + sdm660-rcm.dtb \ + sdm660-rumi.dtb \ + sdm660-pm660a-cdp.dtb \ + sdm660-pm660a-mtp.dtb \ + sdm660-pm660a-qrd.dtb \ + sdm660-pm660a-rcm.dtb \ + sdm660-pm660a-rumi.dtb \ + sdm660-internal-codec-pm660a-cdp.dtb \ + sdm660-internal-codec-pm660a-mtp.dtb \ + sdm660-internal-codec-pm660a-rcm.dtb \ + sdm660-pm660a-sim.dtb \ + sda660-cdp.dtb \ + sda660-mtp.dtb \ + sda660-rcm.dtb \ + sda660-pm660a-cdp.dtb \ + sda660-pm660a-mtp.dtb \ + sda660-pm660a-rcm.dtb \ + sda660-pm660a-qrd-hdk.dtb \ + sdm660-headset-jacktype-no-cdp.dtb \ + sdm660-headset-jacktype-no-rcm.dtb \ + sdm660-pm660a-headset-jacktype-no-cdp.dtb \ + sdm660-pm660a-headset-jacktype-no-rcm.dtb \ + sdm660-usbc-audio-mtp.dtb \ + sdm660-usbc-audio-rcm.dtb \ + sdm660-fhd-cdp.dtb \ + sdm660-pm660a-fhd-cdp.dtb \ + sdm658-mtp.dtb \ + sdm658-cdp.dtb \ + sdm658-rcm.dtb \ + sdm658-qrd.dtb \ + sdm658-pm660a-mtp.dtb \ + sdm658-pm660a-cdp.dtb \ + sdm658-pm660a-rcm.dtb \ + sdm658-pm660a-qrd.dtb \ + sdm658-internal-codec-mtp.dtb \ + sdm658-internal-codec-cdp.dtb \ + sdm658-internal-codec-rcm.dtb \ + sdm658-internal-codec-pm660a-mtp.dtb \ + sdm658-internal-codec-pm660a-cdp.dtb \ + sdm658-internal-codec-pm660a-rcm.dtb \ + sda658-cdp.dtb \ + sda658-mtp.dtb \ + sda658-rcm.dtb \ + sda658-pm660a-mtp.dtb \ + sda658-pm660a-cdp.dtb \ + sda658-pm660a-rcm.dtb \ + sdm636-cdp.dtb \ + sdm636-mtp.dtb \ + sdm636-qrd.dtb \ + sdm636-rcm.dtb \ + sdm636-headset-jacktype-no-cdp.dtb \ + sdm636-headset-jacktype-no-rcm.dtb \ + sdm636-internal-codec-cdp.dtb \ + sdm636-internal-codec-mtp.dtb \ + sdm636-internal-codec-pm660a-cdp.dtb \ + sdm636-internal-codec-pm660a-mtp.dtb \ + sdm636-internal-codec-pm660a-rcm.dtb \ + sdm636-internal-codec-rcm.dtb \ + sdm636-pm660a-headset-jacktype-no-cdp.dtb \ + sdm636-pm660a-headset-jacktype-no-rcm.dtb \ + sdm636-pm660a-cdp.dtb \ + sdm636-pm660a-mtp.dtb \ + sdm636-pm660a-qrd.dtb \ + sdm636-pm660a-rcm.dtb \ + sdm636-usbc-audio-mtp.dtb \ + sdm636-usbc-audio-rcm.dtb \ + sda636-cdp.dtb \ + sda636-mtp.dtb \ + sda636-rcm.dtb \ + sda636-pm660a-cdp.dtb \ + sda636-pm660a-mtp.dtb \ + sda636-pm660a-qrd-hdk.dtb \ + sda636-pm660a-rcm.dtb + +dtb-$(CONFIG_ARCH_SDM630) += sdm630-rumi.dtb \ + sdm630-pm660a-rumi.dtb \ + sdm630-mtp.dtb \ + sdm630-usbc-audio-mtp.dtb \ + sdm630-usbc-audio-rcm.dtb \ + sdm630-cdp.dtb \ + sdm630-rcm.dtb \ + sdm630-internal-codec-mtp.dtb \ + sdm630-internal-codec-cdp.dtb \ + sdm630-internal-codec-rcm.dtb \ + sdm630-pm660a-cdp.dtb \ + sdm630-pm660a-mtp.dtb \ + sdm630-pm660a-rcm.dtb \ + sdm630-pm660a-qrd.dtb \ + sdm630-internal-codec-pm660a-cdp.dtb \ + sdm630-internal-codec-pm660a-mtp.dtb \ + sdm630-internal-codec-pm660a-rcm.dtb \ + sda630-mtp.dtb \ + sda630-cdp.dtb \ + sda630-rcm.dtb \ + sda630-pm660a-mtp.dtb \ + sda630-pm660a-cdp.dtb \ + sda630-pm660a-rcm.dtb \ + sda630-pm660a-qrd-hdk.dtb \ + sdm630-headset-jacktype-no-cdp.dtb \ + sdm630-headset-jacktype-no-rcm.dtb \ + sdm630-pm660a-headset-jacktype-no-cdp.dtb \ + sdm630-pm660a-headset-jacktype-no-rcm.dtb + +ifeq ($(CONFIG_ARM64),y) +always := $(dtb-y) qcom_dtbs +always += $(dtbo-y) +subdir-y := $(dts-dirs) +else +targets += dtbs +targets += $(addprefix ../, $(dtb-y)) + +$(obj)/../%.dtb: $(src)/%.dts FORCE + $(call if_changed_dep,dtc) + +dtbs: $(addprefix $(obj)/../,$(dtb-y)) +endif +clean-files := *.dtbo *.dtb qcom_dtbs qcom_dtbs.cmpxz + +cmd_dtbs = ./scripts/dtbs.sh $@ $^ +quiet_cmd_dtbs = DTBS $@ + +DTB_ALIGN=32 +$(obj)/qcom_dtbs: $(addprefix $(obj)/,$(dtb-y)) + $(call cmd,dtbs) diff -Nruw linux-4.4.115-fbx/arch/arm/boot/dts/qcom./msm8998-audio.dtsi linux-4.4.115-fbx/arch/arm/boot/dts/qcom/msm8998-audio.dtsi --- linux-4.4.115-fbx/arch/arm/boot/dts/qcom./msm8998-audio.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ linux-4.4.115-fbx/arch/arm/boot/dts/qcom/msm8998-audio.dtsi 2019-10-29 09:26:22.917196073 +0100 @@ -0,0 +1,56 @@ +/* + * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&msm_audio_ion { + qcom,smmu-version = <2>; + iommus = <&lpass_q6_smmu 1>; +}; + +&soc { + qcom,avtimer@170f7000 { + compatible = "qcom,avtimer"; + reg = <0x170f700c 0x4>, + <0x170f7010 0x4>; + reg-names = "avtimer_lsb_addr", "avtimer_msb_addr"; + qcom,clk-div = <27>; + }; + + clock_audio: audio_ext_clk { + status = "ok"; + compatible = "qcom,audio-ref-clk"; + qcom,audio-ref-clk-gpio = <&pm8998_gpios 13 0>; + clock-names = "osr_clk"; + clocks = <&clock_gcc clk_div_clk1>; + qcom,node_has_rpm_clock; + #clock-cells = <1>; + pinctrl-names = "sleep", "active"; + pinctrl-0 = <&spkr_i2s_clk_sleep>; + pinctrl-1 = <&spkr_i2s_clk_active>; + }; + + clock_audio_lnbb: audio_ext_clk_lnbb { + status = "ok"; + compatible = "qcom,audio-ref-clk"; + clock-names = "osr_clk"; + clocks = <&clock_gcc clk_ln_bb_clk2>; + qcom,node_has_rpm_clock; + #clock-cells = <1>; + }; +}; + +&slim_aud { + msm_dai_slim { + compatible = "qcom,msm-dai-slim"; + elemental-addr = [ff ff ff fe 17 02]; + }; +}; diff -Nruw linux-4.4.115-fbx/arch/arm/boot/dts/qcom./msm8998-audio-freebox.dtsi linux-4.4.115-fbx/arch/arm/boot/dts/qcom/msm8998-audio-freebox.dtsi --- linux-4.4.115-fbx/arch/arm/boot/dts/qcom./msm8998-audio-freebox.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ linux-4.4.115-fbx/arch/arm/boot/dts/qcom/msm8998-audio-freebox.dtsi 2019-01-22 16:16:21.191225470 +0100 @@ -0,0 +1,87 @@ +/* + * Copyright (c) 2018, Freebox SAS. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&soc { + snd_freebox: sound-freebox { + compatible = "qcom,msm8998-asoc-snd-freebox"; + qcom,model = "msm8998-freebox-snd-card"; + qcom,ext-disp-audio-rx; + qcom,mi2s-audio-intf; + qcom,msm-mi2s-master = <1>, <1>, <0>, <0>; + qcom,msm-mi2s-ext-mclk = <1>, <0>, <0>, <0>; + + reg = <0x1711a000 0x4>, + <0x1711b000 0x4>, + <0x1711c000 0x4>, + <0x1711d000 0x4>; + reg-names = "lpaif_pri_mode_muxsel", + "lpaif_sec_mode_muxsel", + "lpaif_tert_mode_muxsel", + "lpaif_quat_mode_muxsel"; + + asoc-platform = <&pcm0>, <&pcm1>, <&pcm2>, <&voip>, <&voice>, + <&loopback>, <&compress>, <&hostless>, + <&afe>, <&lsm>, <&routing>, <&compr>, + <&pcm_noirq>, <&trans_loopback>; + asoc-platform-names = "msm-pcm-dsp.0", "msm-pcm-dsp.1", + "msm-pcm-dsp.2", "msm-voip-dsp", + "msm-pcm-voice", "msm-pcm-loopback", + "msm-compress-dsp", "msm-pcm-hostless", + "msm-pcm-afe", "msm-lsm-client", + "msm-pcm-routing", "msm-compr-dsp", + "msm-pcm-dsp-noirq", "msm-transcode-loopback"; + asoc-cpu = <&dai_hdmi>, <&dai_dp>, + <&dai_mi2s0>, <&dai_mi2s1>, + <&dai_mi2s2>, <&dai_mi2s3>, + <&dai_pri_auxpcm>, <&dai_sec_auxpcm>, + <&dai_tert_auxpcm>, <&dai_quat_auxpcm>, + <&sb_0_rx>, <&sb_0_tx>, <&sb_1_rx>, <&sb_1_tx>, + <&sb_2_rx>, <&sb_2_tx>, <&sb_3_rx>, <&sb_3_tx>, + <&sb_4_rx>, <&sb_4_tx>, <&sb_5_tx>, + <&afe_pcm_rx>, <&afe_pcm_tx>, <&afe_proxy_rx>, + <&afe_proxy_tx>, <&incall_record_rx>, + <&incall_record_tx>, <&incall_music_rx>, + <&incall_music_2_rx>, <&sb_5_rx>, <&sb_6_rx>, + <&sb_7_rx>, <&sb_7_tx>, <&sb_8_tx>, + <&usb_audio_rx>, <&usb_audio_tx>, + <&dai_pri_tdm_rx_0>, <&dai_pri_tdm_tx_0>, + <&dai_sec_tdm_rx_0>, <&dai_sec_tdm_tx_0>, + <&dai_tert_tdm_rx_0>, <&dai_tert_tdm_tx_0>, + <&dai_quat_tdm_rx_0>, <&dai_quat_tdm_tx_0>; + asoc-cpu-names = "msm-dai-q6-hdmi.8", "msm-dai-q6-dp.24608", + "msm-dai-q6-mi2s.0", "msm-dai-q6-mi2s.1", + "msm-dai-q6-mi2s.2", "msm-dai-q6-mi2s.3", + "msm-dai-q6-auxpcm.1", "msm-dai-q6-auxpcm.2", + "msm-dai-q6-auxpcm.3", "msm-dai-q6-auxpcm.4", + "msm-dai-q6-dev.16384", "msm-dai-q6-dev.16385", + "msm-dai-q6-dev.16386", "msm-dai-q6-dev.16387", + "msm-dai-q6-dev.16388", "msm-dai-q6-dev.16389", + "msm-dai-q6-dev.16390", "msm-dai-q6-dev.16391", + "msm-dai-q6-dev.16392", "msm-dai-q6-dev.16393", + "msm-dai-q6-dev.16395", "msm-dai-q6-dev.224", + "msm-dai-q6-dev.225", "msm-dai-q6-dev.241", + "msm-dai-q6-dev.240", "msm-dai-q6-dev.32771", + "msm-dai-q6-dev.32772", "msm-dai-q6-dev.32773", + "msm-dai-q6-dev.32770", "msm-dai-q6-dev.16394", + "msm-dai-q6-dev.16396", "msm-dai-q6-dev.16398", + "msm-dai-q6-dev.16399", "msm-dai-q6-dev.16401", + "msm-dai-q6-dev.28672", "msm-dai-q6-dev.28673", + "msm-dai-q6-tdm.36864", "msm-dai-q6-tdm.36865", + "msm-dai-q6-tdm.36880", "msm-dai-q6-tdm.36881", + "msm-dai-q6-tdm.36896", "msm-dai-q6-tdm.36897", + "msm-dai-q6-tdm.36912", "msm-dai-q6-tdm.36913"; + asoc-codec = <&stub_codec>, <&ext_disp_audio_codec>; + asoc-codec-names = "msm-stub-codec.1", + "msm-ext-disp-audio-codec-rx"; + }; +}; diff -Nruw linux-4.4.115-fbx/arch/arm/boot/dts/qcom./msm8998-audio-wcd.dtsi linux-4.4.115-fbx/arch/arm/boot/dts/qcom/msm8998-audio-wcd.dtsi --- linux-4.4.115-fbx/arch/arm/boot/dts/qcom./msm8998-audio-wcd.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ linux-4.4.115-fbx/arch/arm/boot/dts/qcom/msm8998-audio-wcd.dtsi 2019-01-22 16:16:21.191225470 +0100 @@ -0,0 +1,632 @@ +/* + * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "msm8998-wsa881x.dtsi" + +&spi_10 { + status = "ok"; +}; + +&soc { + snd_9335: sound-9335 { + compatible = "qcom,msm8998-asoc-snd-tasha"; + qcom,model = "msm8998-tasha-snd-card"; + qcom,ext-disp-audio-rx; + qcom,wcn-btfm; + qcom,mi2s-audio-intf; + qcom,auxpcm-audio-intf; + qcom,msm-mi2s-master = <1>, <1>, <1>, <1>; + + reg = <0x1711a000 0x4>, + <0x1711b000 0x4>, + <0x1711c000 0x4>, + <0x1711d000 0x4>; + reg-names = "lpaif_pri_mode_muxsel", + "lpaif_sec_mode_muxsel", + "lpaif_tert_mode_muxsel", + "lpaif_quat_mode_muxsel"; + + qcom,audio-routing = + "AIF4 VI", "MCLK", + "RX_BIAS", "MCLK", + "MADINPUT", "MCLK", + "hifi amp", "LINEOUT1", + "hifi amp", "LINEOUT2", + "AMIC2", "MIC BIAS2", + "MIC BIAS2", "Headset Mic", + "AMIC3", "MIC BIAS2", + "MIC BIAS2", "ANCRight Headset Mic", + "AMIC4", "MIC BIAS2", + "MIC BIAS2", "ANCLeft Headset Mic", + "AMIC5", "MIC BIAS3", + "MIC BIAS3", "Handset Mic", + "AMIC6", "MIC BIAS4", + "MIC BIAS4", "Analog Mic6", + "DMIC0", "MIC BIAS1", + "MIC BIAS1", "Digital Mic0", + "DMIC1", "MIC BIAS1", + "MIC BIAS1", "Digital Mic1", + "DMIC2", "MIC BIAS3", + "MIC BIAS3", "Digital Mic2", + "DMIC3", "MIC BIAS3", + "MIC BIAS3", "Digital Mic3", + "DMIC4", "MIC BIAS4", + "MIC BIAS4", "Digital Mic4", + "DMIC5", "MIC BIAS4", + "MIC BIAS4", "Digital Mic5", + "SpkrLeft IN", "SPK1 OUT", + "SpkrRight IN", "SPK2 OUT"; + + qcom,msm-mbhc-hphl-swh = <0>; + qcom,msm-mbhc-gnd-swh = <0>; + qcom,us-euro-gpios = <&wcd_us_euro_gpio>; + qcom,hph-en0-gpio = <&hph_en0_gpio>; + qcom,hph-en1-gpio = <&hph_en1_gpio>; + qcom,tasha-mclk-clk-freq = <9600000>; + asoc-platform = <&pcm0>, <&pcm1>, <&pcm2>, <&voip>, <&voice>, + <&loopback>, <&compress>, <&hostless>, + <&afe>, <&lsm>, <&routing>, <&cpe>, <&compr>, + <&pcm_noirq>, <&cpe3>, <&trans_loopback>; + asoc-platform-names = "msm-pcm-dsp.0", "msm-pcm-dsp.1", + "msm-pcm-dsp.2", "msm-voip-dsp", + "msm-pcm-voice", "msm-pcm-loopback", + "msm-compress-dsp", "msm-pcm-hostless", + "msm-pcm-afe", "msm-lsm-client", + "msm-pcm-routing", "msm-cpe-lsm", + "msm-compr-dsp", "msm-pcm-dsp-noirq", + "msm-cpe-lsm.3", "msm-transcode-loopback"; + asoc-cpu = <&dai_hdmi>, <&dai_dp>, + <&dai_mi2s0>, <&dai_mi2s1>, + <&dai_mi2s2>, <&dai_mi2s3>, + <&dai_pri_auxpcm>, <&dai_sec_auxpcm>, + <&dai_tert_auxpcm>, <&dai_quat_auxpcm>, + <&sb_0_rx>, <&sb_0_tx>, <&sb_1_rx>, <&sb_1_tx>, + <&sb_2_rx>, <&sb_2_tx>, <&sb_3_rx>, <&sb_3_tx>, + <&sb_4_rx>, <&sb_4_tx>, <&sb_5_tx>, + <&afe_pcm_rx>, <&afe_pcm_tx>, <&afe_proxy_rx>, + <&afe_proxy_tx>, <&incall_record_rx>, + <&incall_record_tx>, <&incall_music_rx>, + <&incall_music_2_rx>, <&sb_5_rx>, <&sb_6_rx>, + <&sb_7_rx>, <&sb_7_tx>, <&sb_8_tx>, + <&usb_audio_rx>, <&usb_audio_tx>, + <&dai_pri_tdm_rx_0>, <&dai_pri_tdm_tx_0>, + <&dai_sec_tdm_rx_0>, <&dai_sec_tdm_tx_0>, + <&dai_tert_tdm_rx_0>, <&dai_tert_tdm_tx_0>, + <&dai_quat_tdm_rx_0>, <&dai_quat_tdm_tx_0>; + asoc-cpu-names = "msm-dai-q6-hdmi.8", "msm-dai-q6-dp.24608", + "msm-dai-q6-mi2s.0", "msm-dai-q6-mi2s.1", + "msm-dai-q6-mi2s.2", "msm-dai-q6-mi2s.3", + "msm-dai-q6-auxpcm.1", "msm-dai-q6-auxpcm.2", + "msm-dai-q6-auxpcm.3", "msm-dai-q6-auxpcm.4", + "msm-dai-q6-dev.16384", "msm-dai-q6-dev.16385", + "msm-dai-q6-dev.16386", "msm-dai-q6-dev.16387", + "msm-dai-q6-dev.16388", "msm-dai-q6-dev.16389", + "msm-dai-q6-dev.16390", "msm-dai-q6-dev.16391", + "msm-dai-q6-dev.16392", "msm-dai-q6-dev.16393", + "msm-dai-q6-dev.16395", "msm-dai-q6-dev.224", + "msm-dai-q6-dev.225", "msm-dai-q6-dev.241", + "msm-dai-q6-dev.240", "msm-dai-q6-dev.32771", + "msm-dai-q6-dev.32772", "msm-dai-q6-dev.32773", + "msm-dai-q6-dev.32770", "msm-dai-q6-dev.16394", + "msm-dai-q6-dev.16396", "msm-dai-q6-dev.16398", + "msm-dai-q6-dev.16399", "msm-dai-q6-dev.16401", + "msm-dai-q6-dev.28672", "msm-dai-q6-dev.28673", + "msm-dai-q6-tdm.36864", "msm-dai-q6-tdm.36865", + "msm-dai-q6-tdm.36880", "msm-dai-q6-tdm.36881", + "msm-dai-q6-tdm.36896", "msm-dai-q6-tdm.36897", + "msm-dai-q6-tdm.36912", "msm-dai-q6-tdm.36913"; + asoc-codec = <&stub_codec>, <&ext_disp_audio_codec>; + asoc-codec-names = "msm-stub-codec.1", + "msm-ext-disp-audio-codec-rx"; + qcom,wsa-max-devs = <2>; + qcom,wsa-devs = <&wsa881x_211>, <&wsa881x_212>, + <&wsa881x_213>, <&wsa881x_214>; + qcom,wsa-aux-dev-prefix = "SpkrLeft", "SpkrRight", + "SpkrLeft", "SpkrRight"; + + hph_en0_gpio: msm_cdc_pinctrl@67 { + compatible = "qcom,msm-cdc-pinctrl"; + pinctrl-names = "aud_active", "aud_sleep"; + pinctrl-0 = <&hph_en0_active>; + pinctrl-1 = <&hph_en0_idle>; + }; + + hph_en1_gpio: msm_cdc_pinctrl@68 { + compatible = "qcom,msm-cdc-pinctrl"; + pinctrl-names = "aud_active", "aud_sleep"; + pinctrl-0 = <&hph_en1_active>; + pinctrl-1 = <&hph_en1_idle>; + }; + }; + + snd_934x: sound-tavil { + compatible = "qcom,msm8998-asoc-snd-tavil"; + qcom,model = "msm8998-tavil-snd-card"; + qcom,ext-disp-audio-rx; + qcom,wcn-btfm; + qcom,mi2s-audio-intf; + qcom,auxpcm-audio-intf; + qcom,msm-mi2s-master = <1>, <1>, <1>, <1>; + + reg = <0x1711a000 0x4>, + <0x1711b000 0x4>, + <0x1711c000 0x4>, + <0x1711d000 0x4>; + reg-names = "lpaif_pri_mode_muxsel", + "lpaif_sec_mode_muxsel", + "lpaif_tert_mode_muxsel", + "lpaif_quat_mode_muxsel"; + + qcom,audio-routing = + "AIF4 VI", "MCLK", + "RX_BIAS", "MCLK", + "MADINPUT", "MCLK", + "hifi amp", "LINEOUT1", + "hifi amp", "LINEOUT2", + "AMIC2", "MIC BIAS2", + "MIC BIAS2", "Headset Mic", + "AMIC3", "MIC BIAS2", + "MIC BIAS2", "ANCRight Headset Mic", + "AMIC4", "MIC BIAS2", + "MIC BIAS2", "ANCLeft Headset Mic", + "AMIC5", "MIC BIAS3", + "MIC BIAS3", "Handset Mic", + "DMIC0", "MIC BIAS1", + "MIC BIAS1", "Digital Mic0", + "DMIC1", "MIC BIAS1", + "MIC BIAS1", "Digital Mic1", + "DMIC2", "MIC BIAS3", + "MIC BIAS3", "Digital Mic2", + "DMIC3", "MIC BIAS3", + "MIC BIAS3", "Digital Mic3", + "DMIC4", "MIC BIAS4", + "MIC BIAS4", "Digital Mic4", + "DMIC5", "MIC BIAS4", + "MIC BIAS4", "Digital Mic5", + "SpkrLeft IN", "SPK1 OUT", + "SpkrRight IN", "SPK2 OUT"; + + qcom,msm-mbhc-hphl-swh = <0>; + qcom,msm-mbhc-gnd-swh = <0>; + qcom,us-euro-gpios = <&tavil_us_euro_sw>; + qcom,hph-en0-gpio = <&tavil_hph_en0>; + qcom,hph-en1-gpio = <&tavil_hph_en1>; + qcom,tavil-mclk-clk-freq = <9600000>; + + qcom,usbc-analog-en1_gpio = <&wcd_usbc_analog_en1_gpio>; + qcom,usbc-analog-en2_n_gpio = <&wcd_usbc_analog_en2n_gpio>; + + asoc-platform = <&pcm0>, <&pcm1>, <&pcm2>, <&voip>, <&voice>, + <&loopback>, <&compress>, <&hostless>, + <&afe>, <&lsm>, <&routing>, <&cpe>, <&compr>, + <&pcm_noirq>, <&trans_loopback>; + asoc-platform-names = "msm-pcm-dsp.0", "msm-pcm-dsp.1", + "msm-pcm-dsp.2", "msm-voip-dsp", + "msm-pcm-voice", "msm-pcm-loopback", + "msm-compress-dsp", "msm-pcm-hostless", + "msm-pcm-afe", "msm-lsm-client", + "msm-pcm-routing", "msm-cpe-lsm", + "msm-compr-dsp", "msm-pcm-dsp-noirq", + "msm-transcode-loopback"; + asoc-cpu = <&dai_hdmi>, <&dai_dp>, + <&dai_mi2s0>, <&dai_mi2s1>, + <&dai_mi2s2>, <&dai_mi2s3>, + <&dai_pri_auxpcm>, <&dai_sec_auxpcm>, + <&dai_tert_auxpcm>, <&dai_quat_auxpcm>, + <&sb_0_rx>, <&sb_0_tx>, <&sb_1_rx>, <&sb_1_tx>, + <&sb_2_rx>, <&sb_2_tx>, <&sb_3_rx>, <&sb_3_tx>, + <&sb_4_rx>, <&sb_4_tx>, <&sb_5_tx>, + <&afe_pcm_rx>, <&afe_pcm_tx>, <&afe_proxy_rx>, + <&afe_proxy_tx>, <&incall_record_rx>, + <&incall_record_tx>, <&incall_music_rx>, + <&incall_music_2_rx>, <&sb_5_rx>, <&sb_6_rx>, + <&sb_7_rx>, <&sb_7_tx>, <&sb_8_tx>, + <&usb_audio_rx>, <&usb_audio_tx>, + <&dai_pri_tdm_rx_0>, <&dai_pri_tdm_tx_0>, + <&dai_sec_tdm_rx_0>, <&dai_sec_tdm_tx_0>, + <&dai_tert_tdm_rx_0>, <&dai_tert_tdm_tx_0>, + <&dai_quat_tdm_rx_0>, <&dai_quat_tdm_tx_0>; + asoc-cpu-names = "msm-dai-q6-hdmi.8", "msm-dai-q6-dp.24608", + "msm-dai-q6-mi2s.0", "msm-dai-q6-mi2s.1", + "msm-dai-q6-mi2s.2", "msm-dai-q6-mi2s.3", + "msm-dai-q6-auxpcm.1", "msm-dai-q6-auxpcm.2", + "msm-dai-q6-auxpcm.3", "msm-dai-q6-auxpcm.4", + "msm-dai-q6-dev.16384", "msm-dai-q6-dev.16385", + "msm-dai-q6-dev.16386", "msm-dai-q6-dev.16387", + "msm-dai-q6-dev.16388", "msm-dai-q6-dev.16389", + "msm-dai-q6-dev.16390", "msm-dai-q6-dev.16391", + "msm-dai-q6-dev.16392", "msm-dai-q6-dev.16393", + "msm-dai-q6-dev.16395", "msm-dai-q6-dev.224", + "msm-dai-q6-dev.225", "msm-dai-q6-dev.241", + "msm-dai-q6-dev.240", "msm-dai-q6-dev.32771", + "msm-dai-q6-dev.32772", "msm-dai-q6-dev.32773", + "msm-dai-q6-dev.32770", "msm-dai-q6-dev.16394", + "msm-dai-q6-dev.16396", "msm-dai-q6-dev.16398", + "msm-dai-q6-dev.16399", "msm-dai-q6-dev.16401", + "msm-dai-q6-dev.28672", "msm-dai-q6-dev.28673", + "msm-dai-q6-tdm.36864", "msm-dai-q6-tdm.36865", + "msm-dai-q6-tdm.36880", "msm-dai-q6-tdm.36881", + "msm-dai-q6-tdm.36896", "msm-dai-q6-tdm.36897", + "msm-dai-q6-tdm.36912", "msm-dai-q6-tdm.36913"; + asoc-codec = <&stub_codec>, <&ext_disp_audio_codec>; + asoc-codec-names = "msm-stub-codec.1", + "msm-ext-disp-audio-codec-rx"; + qcom,wsa-max-devs = <2>; + qcom,wsa-devs = <&wsa881x_0211>, <&wsa881x_0212>, + <&wsa881x_0213>, <&wsa881x_0214>; + qcom,wsa-aux-dev-prefix = "SpkrLeft", "SpkrRight", + "SpkrLeft", "SpkrRight"; + }; + + cpe: qcom,msm-cpe-lsm { + compatible = "qcom,msm-cpe-lsm"; + qcom,msm-cpe-lsm-id = <1>; + }; + + cpe3: qcom,msm-cpe-lsm@3 { + compatible = "qcom,msm-cpe-lsm"; + qcom,msm-cpe-lsm-id = <3>; + }; + + qcom,wcd-dsp-mgr { + compatible = "qcom,wcd-dsp-mgr"; + qcom,wdsp-components = <&wcd934x_cdc 0>, + <&wcd_spi_0 1>, + <&glink_spi_xprt_wdsp 2>; + qcom,img-filename = "cpe_9340"; + }; + + wcd_us_euro_gpio: msm_cdc_pinctrl@75 { + compatible = "qcom,msm-cdc-pinctrl"; + pinctrl-names = "aud_active", "aud_sleep"; + pinctrl-0 = <&wcd_gnd_mic_swap_active>; + pinctrl-1 = <&wcd_gnd_mic_swap_idle>; + }; + + wcd_usbc_analog_en1_gpio: msm_cdc_pinctrl@59 { + compatible = "qcom,msm-cdc-pinctrl"; + pinctrl-names = "aud_active", "aud_sleep"; + pinctrl-0 = <&wcd_usbc_analog_en1_active>; + pinctrl-1 = <&wcd_usbc_analog_en1_idle>; + }; + + wcd_usbc_analog_en2n_gpio: msm_cdc_pinctrl@60 { + compatible = "qcom,msm-cdc-pinctrl"; + pinctrl-names = "aud_active", "aud_sleep"; + pinctrl-0 = <&wcd_usbc_analog_en2n_active>; + pinctrl-1 = <&wcd_usbc_analog_en2n_idle>; + }; + + wcd9xxx_intc: wcd9xxx-irq { + status = "ok"; + compatible = "qcom,wcd9xxx-irq"; + interrupt-controller; + #interrupt-cells = <1>; + interrupt-parent = <&tlmm>; + qcom,gpio-connect = <&tlmm 54 0>; + pinctrl-names = "default"; + pinctrl-0 = <&wcd_intr_default>; + }; + + wcd_rst_gpio: msm_cdc_pinctrl@64 { + compatible = "qcom,msm-cdc-pinctrl"; + qcom,cdc-rst-n-gpio = <&tlmm 64 0>; + pinctrl-names = "aud_active", "aud_sleep"; + pinctrl-0 = <&cdc_reset_active>; + pinctrl-1 = <&cdc_reset_sleep>; + }; + + qocm,wcd-dsp-glink { + compatible = "qcom,wcd-dsp-glink"; + }; +}; + +&slim_aud { + tasha_codec { + compatible = "qcom,tasha-slim-pgd"; + elemental-addr = [00 01 A0 01 17 02]; + + interrupt-parent = <&wcd9xxx_intc>; + interrupts = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 + 17 18 19 20 21 22 23 24 25 26 27 28 29 + 30>; + + qcom,wcd-rst-gpio-node = <&wcd_rst_gpio>; + + clock-names = "wcd_clk", "wcd_native_clk"; + clocks = <&clock_audio clk_audio_pmi_clk>, + <&clock_audio clk_audio_ap_clk2>; + + cdc-vdd-buck-supply = <&pm8998_s4>; + qcom,cdc-vdd-buck-voltage = <1800000 1800000>; + qcom,cdc-vdd-buck-current = <650000>; + + cdc-buck-sido-supply = <&pm8998_s4>; + qcom,cdc-buck-sido-voltage = <1800000 1800000>; + qcom,cdc-buck-sido-current = <250000>; + + cdc-vdd-tx-h-supply = <&pm8998_s4>; + qcom,cdc-vdd-tx-h-voltage = <1800000 1800000>; + qcom,cdc-vdd-tx-h-current = <25000>; + + cdc-vdd-rx-h-supply = <&pm8998_s4>; + qcom,cdc-vdd-rx-h-voltage = <1800000 1800000>; + qcom,cdc-vdd-rx-h-current = <25000>; + + cdc-vddpx-1-supply = <&pm8998_s4>; + qcom,cdc-vddpx-1-voltage = <1800000 1800000>; + qcom,cdc-vddpx-1-current = <10000>; + + qcom,cdc-static-supplies = "cdc-vdd-buck", + "cdc-buck-sido", + "cdc-vdd-tx-h", + "cdc-vdd-rx-h", + "cdc-vddpx-1"; + + qcom,cdc-micbias1-mv = <1800>; + qcom,cdc-micbias2-mv = <1800>; + qcom,cdc-micbias3-mv = <1800>; + qcom,cdc-micbias4-mv = <1800>; + + qcom,cdc-mclk-clk-rate = <9600000>; + qcom,cdc-slim-ifd = "tasha-slim-ifd"; + qcom,cdc-slim-ifd-elemental-addr = [00 00 A0 01 17 02]; + qcom,cdc-dmic-sample-rate = <4800000>; + qcom,cdc-mad-dmic-rate = <600000>; + qcom,cdc-ecpp-dmic-rate = <1200000>; + }; + + wcd934x_cdc: tavil_codec { + compatible = "qcom,tavil-slim-pgd"; + elemental-addr = [00 01 50 02 17 02]; + + interrupt-parent = <&wcd9xxx_intc>; + interrupts = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 + 17 18 19 20 21 22 23 24 25 26 27 28 29 + 30 31>; + + qcom,wcd-rst-gpio-node = <&wcd_rst_gpio>; + + clock-names = "wcd_clk"; + clocks = <&clock_audio_lnbb clk_audio_pmi_lnbb_clk>; + + cdc-vdd-buck-supply = <&pm8998_s4>; + qcom,cdc-vdd-buck-voltage = <1800000 1800000>; + qcom,cdc-vdd-buck-current = <650000>; + + cdc-buck-sido-supply = <&pm8998_s4>; + qcom,cdc-buck-sido-voltage = <1800000 1800000>; + qcom,cdc-buck-sido-current = <250000>; + + cdc-vdd-tx-h-supply = <&pm8998_s4>; + qcom,cdc-vdd-tx-h-voltage = <1800000 1800000>; + qcom,cdc-vdd-tx-h-current = <25000>; + + cdc-vdd-rx-h-supply = <&pm8998_s4>; + qcom,cdc-vdd-rx-h-voltage = <1800000 1800000>; + qcom,cdc-vdd-rx-h-current = <25000>; + + cdc-vddpx-1-supply = <&pm8998_s4>; + qcom,cdc-vddpx-1-voltage = <1800000 1800000>; + qcom,cdc-vddpx-1-current = <10000>; + + qcom,cdc-static-supplies = "cdc-vdd-buck", + "cdc-buck-sido", + "cdc-vdd-tx-h", + "cdc-vdd-rx-h", + "cdc-vddpx-1"; + + qcom,cdc-micbias1-mv = <1800>; + qcom,cdc-micbias2-mv = <1800>; + qcom,cdc-micbias3-mv = <1800>; + qcom,cdc-micbias4-mv = <1800>; + + qcom,cdc-mclk-clk-rate = <9600000>; + qcom,cdc-slim-ifd = "tavil-slim-ifd"; + qcom,cdc-slim-ifd-elemental-addr = [00 00 50 02 17 02]; + qcom,cdc-dmic-sample-rate = <4800000>; + qcom,cdc-mad-dmic-rate = <600000>; + + qcom,wdsp-cmpnt-dev-name = "tavil_codec"; + + wcd_spi_0: wcd_spi { + compatible = "qcom,wcd-spi-v2"; + qcom,master-bus-num = <10>; + qcom,chip-select = <0>; + qcom,max-frequency = <24000000>; + qcom,mem-base-addr = <0x100000>; + }; + }; +}; + +&tlmm { + wcd9xxx_intr { + wcd_intr_default: wcd_intr_default{ + mux { + pins = "gpio54"; + function = "gpio"; + }; + + config { + pins = "gpio54"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* pull down */ + input-enable; + }; + }; + }; + + hph_en0_ctrl { + hph_en0_idle: hph_en0_idle { + mux { + pins = "gpio67"; + function = "gpio"; + }; + config { + pins = "gpio67"; + drive-strength = <2>; + bias-pull-down; + output-low; + }; + }; + hph_en0_active: hph_en0_active { + mux { + pins = "gpio67"; + function = "gpio"; + }; + config { + pins = "gpio67"; + drive-strength = <2>; + bias-disable; + output-high; + }; + }; + }; + + hph_en1_ctrl { + hph_en1_idle: hph_en1_idle { + mux { + pins = "gpio68"; + function = "gpio"; + }; + config { + pins = "gpio68"; + drive-strength = <2>; + bias-pull-down; + output-low; + }; + }; + hph_en1_active: hph_en1_active { + mux { + pins = "gpio68"; + function = "gpio"; + }; + config { + pins = "gpio68"; + drive-strength = <2>; + bias-disable; + output-high; + }; + }; + }; + + wcd_gnd_mic_swap { + wcd_gnd_mic_swap_idle: wcd_gnd_mic_swap_idle { + mux { + pins = "gpio75"; + function = "gpio"; + }; + config { + pins = "gpio75"; + drive-strength = <2>; + bias-pull-down; + output-low; + }; + }; + wcd_gnd_mic_swap_active: wcd_gnd_mic_swap_active { + mux { + pins = "gpio75"; + function = "gpio"; + }; + config { + pins = "gpio75"; + drive-strength = <2>; + bias-disable; + output-high; + }; + }; + }; + + wcd_usbc_analog_en1 { + wcd_usbc_analog_en1_idle: wcd_usbc_ana_en1_idle { + mux { + pins = "gpio59"; + function = "gpio"; + }; + config { + pins = "gpio59"; + drive-strength = <2>; + bias-pull-down; + output-low; + }; + }; + + wcd_usbc_analog_en1_active: wcd_usbc_ana_en1_active { + mux { + pins = "gpio59"; + function = "gpio"; + }; + config { + pins = "gpio59"; + drive-strength = <2>; + bias-disable; + output-high; + }; + }; + }; + + wcd_usbc_analog_en2n { + wcd_usbc_analog_en2n_idle: wcd_usbc_ana_en2n_idle { + mux { + pins = "gpio60"; + function = "gpio"; + }; + config { + pins = "gpio60"; + drive-strength = <2>; + bias-disable; + output-high; + }; + }; + + wcd_usbc_analog_en2n_active: wcd_usbc_ana_en2n_active { + mux { + pins = "gpio60"; + function = "gpio"; + }; + config { + pins = "gpio60"; + drive-strength = <2>; + bias-pull-down; + output-low; + }; + }; + }; + + cdc_reset_ctrl { + cdc_reset_sleep: cdc_reset_sleep { + mux { + pins = "gpio64"; + function = "gpio"; + }; + config { + pins = "gpio64"; + drive-strength = <16>; + bias-disable; + output-low; + }; + }; + cdc_reset_active:cdc_reset_active { + mux { + pins = "gpio64"; + function = "gpio"; + }; + config { + pins = "gpio64"; + drive-strength = <16>; + bias-pull-down; + output-high; + }; + }; + }; +}; diff -Nruw linux-4.4.115-fbx/arch/arm/boot/dts/qcom./msm8998-blsp.dtsi linux-4.4.115-fbx/arch/arm/boot/dts/qcom/msm8998-blsp.dtsi --- linux-4.4.115-fbx/arch/arm/boot/dts/qcom./msm8998-blsp.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ linux-4.4.115-fbx/arch/arm/boot/dts/qcom/msm8998-blsp.dtsi 2019-01-22 16:16:21.191225470 +0100 @@ -0,0 +1,863 @@ +/* + * Copyright (c) 2015-2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +/ { + aliases { + i2c1 = &i2c_1; + i2c2 = &i2c_2; + i2c3 = &i2c_3; + i2c4 = &i2c_4; + i2c5 = &i2c_5; + i2c6 = &i2c_6; + i2c7 = &i2c_7; + i2c8 = &i2c_8; + i2c9 = &i2c_9; + i2c10 = &i2c_10; + i2c11 = &i2c_11; + i2c12 = &i2c_12; + spi1 = &spi_1; + spi2 = &spi_2; + spi3 = &spi_3; + spi4 = &spi_4; + spi5 = &spi_5; + spi6 = &spi_6; + spi7 = &spi_7; + spi8 = &spi_8; + spi9 = &spi_9; + spi10 = &spi_10; + spi11 = &spi_11; + spi12 = &spi_12; + }; +}; + +#include "msm8998-pinctrl.dtsi" + +&soc { + dma_blsp1: qcom,sps-dma@0xc144000 { /* BLSP1 */ + #dma-cells = <4>; + compatible = "qcom,sps-dma"; + reg = <0xc144000 0x25000>; + interrupts = <0 238 0>; + qcom,summing-threshold = <0x10>; + }; + + dma_blsp2: qcom,sps-dma@0xc184000 { /* BLSP2 */ + #dma-cells = <4>; + compatible = "qcom,sps-dma"; + reg = <0xc184000 0x25000>; + interrupts = <0 239 0>; + qcom,summing-threshold = <0x10>; + }; + + i2c_1: i2c@c175000 { /* BLSP1 QUP1 */ + compatible = "qcom,i2c-msm-v2"; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "qup_phys_addr"; + reg = <0xC175000 0x600>; + interrupt-names = "qup_irq"; + interrupts = <0 95 0>; + dmas = <&dma_blsp1 6 64 0x20000020 0x20>, + <&dma_blsp1 7 32 0x20000020 0x20>; + dma-names = "tx", "rx"; + qcom,master-id = <86>; + qcom,clk-freq-out = <400000>; + qcom,clk-freq-in = <19200000>; + clock-names = "iface_clk", "core_clk"; + clocks = <&clock_gcc clk_gcc_blsp1_ahb_clk>, + <&clock_gcc clk_gcc_blsp1_qup1_i2c_apps_clk>; + pinctrl-names = "i2c_active", "i2c_sleep"; + pinctrl-0 = <&i2c_1_active>; + pinctrl-1 = <&i2c_1_sleep>; + status = "disabled"; + }; + + i2c_2: i2c@c176000 { /* BLSP1 QUP2 */ + compatible = "qcom,i2c-msm-v2"; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "qup_phys_addr"; + reg = <0xC176000 0x600>; + interrupt-names = "qup_irq"; + interrupts = <0 96 0>; + dmas = <&dma_blsp1 8 64 0x20000020 0x20>, + <&dma_blsp1 9 32 0x20000020 0x20>; + dma-names = "tx", "rx"; + qcom,master-id = <86>; + qcom,clk-freq-out = <400000>; + qcom,clk-freq-in = <19200000>; + clock-names = "iface_clk", "core_clk"; + clocks = <&clock_gcc clk_gcc_blsp1_ahb_clk>, + <&clock_gcc clk_gcc_blsp1_qup2_i2c_apps_clk>; + pinctrl-names = "i2c_active", "i2c_sleep"; + pinctrl-0 = <&i2c_2_active>; + pinctrl-1 = <&i2c_2_sleep>; + status = "disabled"; + }; + + i2c_3: i2c@c177000 { /* BLSP1 QUP3 */ + compatible = "qcom,i2c-msm-v2"; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "qup_phys_addr"; + reg = <0xC177000 0x600>; + interrupt-names = "qup_irq"; + interrupts = <0 97 0>; + dmas = <&dma_blsp1 10 64 0x20000020 0x20>, + <&dma_blsp1 11 32 0x20000020 0x20>; + dma-names = "tx", "rx"; + qcom,master-id = <86>; + qcom,clk-freq-out = <400000>; + qcom,clk-freq-in = <19200000>; + clock-names = "iface_clk", "core_clk"; + clocks = <&clock_gcc clk_gcc_blsp1_ahb_clk>, + <&clock_gcc clk_gcc_blsp1_qup3_i2c_apps_clk>; + pinctrl-names = "i2c_active", "i2c_sleep"; + pinctrl-0 = <&i2c_3_active>; + pinctrl-1 = <&i2c_3_sleep>; + status = "disabled"; + }; + + i2c_4: i2c@c178000 { /* BLSP1 QUP4 */ + compatible = "qcom,i2c-msm-v2"; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "qup_phys_addr"; + reg = <0xC178000 0x600>; + interrupt-names = "qup_irq"; + interrupts = <0 98 0>; + dmas = <&dma_blsp1 12 64 0x20000020 0x20>, + <&dma_blsp1 13 32 0x20000020 0x20>; + dma-names = "tx", "rx"; + qcom,master-id = <86>; + qcom,clk-freq-out = <400000>; + qcom,clk-freq-in = <19200000>; + clock-names = "iface_clk", "core_clk"; + clocks = <&clock_gcc clk_gcc_blsp1_ahb_clk>, + <&clock_gcc clk_gcc_blsp1_qup4_i2c_apps_clk>; + pinctrl-names = "i2c_active", "i2c_sleep"; + pinctrl-0 = <&i2c_4_active>; + pinctrl-1 = <&i2c_4_sleep>; + status = "disabled"; + }; + + i2c_5: i2c@c179000 { /* BLSP1 QUP5 */ + compatible = "qcom,i2c-msm-v2"; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "qup_phys_addr"; + reg = <0xC179000 0x600>; + interrupt-names = "qup_irq"; + interrupts = <0 99 0>; + dmas = <&dma_blsp1 14 64 0x20000020 0x20>, + <&dma_blsp1 15 32 0x20000020 0x20>; + dma-names = "tx", "rx"; + qcom,master-id = <86>; + qcom,clk-freq-out = <400000>; + qcom,clk-freq-in = <19200000>; + clock-names = "iface_clk", "core_clk"; + clocks = <&clock_gcc clk_gcc_blsp1_ahb_clk>, + <&clock_gcc clk_gcc_blsp1_qup5_i2c_apps_clk>; + pinctrl-names = "i2c_active", "i2c_sleep"; + pinctrl-0 = <&i2c_5_active>; + pinctrl-1 = <&i2c_5_sleep>; + status = "disabled"; + }; + + i2c_6: i2c@c17a000 { /* BLSP1 QUP6 */ + compatible = "qcom,i2c-msm-v2"; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "qup_phys_addr"; + reg = <0xC17A000 0x600>; + interrupt-names = "qup_irq"; + interrupts = <0 100 0>; + dmas = <&dma_blsp1 16 64 0x20000020 0x20>, + <&dma_blsp1 17 32 0x20000020 0x20>; + dma-names = "tx", "rx"; + qcom,master-id = <86>; + qcom,clk-freq-out = <400000>; + qcom,clk-freq-in = <19200000>; + clock-names = "iface_clk", "core_clk"; + clocks = <&clock_gcc clk_gcc_blsp1_ahb_clk>, + <&clock_gcc clk_gcc_blsp1_qup6_i2c_apps_clk>; + pinctrl-names = "i2c_active", "i2c_sleep"; + pinctrl-0 = <&i2c_6_active>; + pinctrl-1 = <&i2c_6_sleep>; + status = "disabled"; + }; + + i2c_7: i2c@c1b5000 { /* BLSP2 QUP1 */ + compatible = "qcom,i2c-msm-v2"; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "qup_phys_addr"; + reg = <0xC1B5000 0x600>; + interrupt-names = "qup_irq"; + interrupts = <0 101 0>; + dmas = <&dma_blsp2 6 64 0x20000020 0x20>, + <&dma_blsp2 7 32 0x20000020 0x20>; + dma-names = "tx", "rx"; + qcom,master-id = <84>; + qcom,clk-freq-out = <400000>; + qcom,clk-freq-in = <19200000>; + clock-names = "iface_clk", "core_clk"; + clocks = <&clock_gcc clk_gcc_blsp2_ahb_clk>, + <&clock_gcc clk_gcc_blsp2_qup1_i2c_apps_clk>; + pinctrl-names = "i2c_active", "i2c_sleep"; + pinctrl-0 = <&i2c_7_active>; + pinctrl-1 = <&i2c_7_sleep>; + status = "disabled"; + }; + + i2c_8: i2c@c1b6000 { /* BLSP2 QUP2 */ + compatible = "qcom,i2c-msm-v2"; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "qup_phys_addr"; + reg = <0xC1B6000 0x600>; + interrupt-names = "qup_irq"; + interrupts = <0 102 0>; + dmas = <&dma_blsp2 8 64 0x20000020 0x20>, + <&dma_blsp2 9 32 0x20000020 0x20>; + dma-names = "tx", "rx"; + qcom,master-id = <84>; + qcom,clk-freq-out = <400000>; + qcom,clk-freq-in = <19200000>; + clock-names = "iface_clk", "core_clk"; + clocks = <&clock_gcc clk_gcc_blsp2_ahb_clk>, + <&clock_gcc clk_gcc_blsp2_qup2_i2c_apps_clk>; + pinctrl-names = "i2c_active", "i2c_sleep"; + pinctrl-0 = <&i2c_8_active>; + pinctrl-1 = <&i2c_8_sleep>; + status = "disabled"; + }; + + i2c_9: i2c@c1b7000 { /* BLSP2 QUP3 */ + compatible = "qcom,i2c-msm-v2"; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "qup_phys_addr"; + reg = <0xC1B7000 0x600>; + interrupt-names = "qup_irq"; + interrupts = <0 103 0>; + dmas = <&dma_blsp2 10 64 0x20000020 0x20>, + <&dma_blsp2 11 32 0x20000020 0x20>; + dma-names = "tx", "rx"; + qcom,master-id = <84>; + qcom,clk-freq-out = <400000>; + qcom,clk-freq-in = <19200000>; + clock-names = "iface_clk", "core_clk"; + clocks = <&clock_gcc clk_gcc_blsp2_ahb_clk>, + <&clock_gcc clk_gcc_blsp2_qup3_i2c_apps_clk>; + pinctrl-names = "i2c_active", "i2c_sleep"; + pinctrl-0 = <&i2c_9_active>; + pinctrl-1 = <&i2c_9_sleep>; + status = "disabled"; + }; + + i2c_10: i2c@c1b8000 { /* BLSP2 QUP4 */ + compatible = "qcom,i2c-msm-v2"; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "qup_phys_addr"; + reg = <0xC1B8000 0x600>; + interrupt-names = "qup_irq"; + interrupts = <0 104 0>; + dmas = <&dma_blsp2 12 64 0x20000020 0x20>, + <&dma_blsp2 13 32 0x20000020 0x20>; + dma-names = "tx", "rx"; + qcom,master-id = <84>; + qcom,clk-freq-out = <400000>; + qcom,clk-freq-in = <19200000>; + clock-names = "iface_clk", "core_clk"; + clocks = <&clock_gcc clk_gcc_blsp2_ahb_clk>, + <&clock_gcc clk_gcc_blsp2_qup4_i2c_apps_clk>; + pinctrl-names = "i2c_active", "i2c_sleep"; + pinctrl-0 = <&i2c_10_active>; + pinctrl-1 = <&i2c_10_sleep>; + status = "disabled"; + }; + + i2c_11: i2c@c1b9000 { /* BLSP2 QUP5 */ + compatible = "qcom,i2c-msm-v2"; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "qup_phys_addr"; + reg = <0xC1B9000 0x600>; + interrupt-names = "qup_irq"; + interrupts = <0 105 0>; + dmas = <&dma_blsp2 14 64 0x20000020 0x20>, + <&dma_blsp2 15 32 0x20000020 0x20>; + dma-names = "tx", "rx"; + qcom,master-id = <84>; + qcom,clk-freq-out = <400000>; + qcom,clk-freq-in = <19200000>; + clock-names = "iface_clk", "core_clk"; + clocks = <&clock_gcc clk_gcc_blsp2_ahb_clk>, + <&clock_gcc clk_gcc_blsp2_qup5_i2c_apps_clk>; + pinctrl-names = "i2c_active", "i2c_sleep"; + pinctrl-0 = <&i2c_11_active>; + pinctrl-1 = <&i2c_11_sleep>; + status = "disabled"; + }; + + i2c_12: i2c@c1ba000 { /* BLSP2 QUP6 */ + compatible = "qcom,i2c-msm-v2"; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "qup_phys_addr"; + reg = <0xC1BA000 0x600>; + interrupt-names = "qup_irq"; + interrupts = <0 106 0>; + dmas = <&dma_blsp2 16 64 0x20000020 0x20>, + <&dma_blsp2 17 32 0x20000020 0x20>; + dma-names = "tx", "rx"; + qcom,master-id = <84>; + qcom,clk-freq-out = <400000>; + qcom,clk-freq-in = <19200000>; + clock-names = "iface_clk", "core_clk"; + clocks = <&clock_gcc clk_gcc_blsp2_ahb_clk>, + <&clock_gcc clk_gcc_blsp2_qup6_i2c_apps_clk>; + pinctrl-names = "i2c_active", "i2c_sleep"; + pinctrl-0 = <&i2c_12_active>; + pinctrl-1 = <&i2c_12_sleep>; + status = "disabled"; + }; + + spi_1: spi@c175000 { /* BLSP1 QUP1 */ + compatible = "qcom,spi-qup-v2"; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "spi_physical", "spi_bam_physical"; + reg = <0xC175000 0x600>, + <0xC144000 0x25000>; + interrupt-names = "spi_irq", "spi_bam_irq"; + interrupts = <0 95 0>, <0 238 0>; + spi-max-frequency = <50000000>; + qcom,use-bam; + qcom,ver-reg-exists; + qcom,bam-consumer-pipe-index = <6>; + qcom,bam-producer-pipe-index = <7>; + qcom,master-id = <86>; + qcom,use-pinctrl; + pinctrl-names = "spi_default", "spi_sleep"; + pinctrl-0 = <&spi_1_active>; + pinctrl-1 = <&spi_1_sleep>; + clock-names = "iface_clk", "core_clk"; + clocks = <&clock_gcc clk_gcc_blsp1_ahb_clk>, + <&clock_gcc clk_gcc_blsp1_qup1_spi_apps_clk>; + status = "disabled"; + }; + + spi_2: spi@c176000 { /* BLSP1 QUP2 */ + compatible = "qcom,spi-qup-v2"; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "spi_physical", "spi_bam_physical"; + reg = <0xC176000 0x600>, + <0xC144000 0x25000>; + interrupt-names = "spi_irq", "spi_bam_irq"; + interrupts = <0 96 0>, <0 238 0>; + spi-max-frequency = <50000000>; + qcom,use-bam; + qcom,ver-reg-exists; + qcom,bam-consumer-pipe-index = <8>; + qcom,bam-producer-pipe-index = <9>; + qcom,master-id = <86>; + qcom,use-pinctrl; + pinctrl-names = "spi_default", "spi_sleep"; + pinctrl-0 = <&spi_2_active>; + pinctrl-1 = <&spi_2_sleep>; + clock-names = "iface_clk", "core_clk"; + clocks = <&clock_gcc clk_gcc_blsp1_ahb_clk>, + <&clock_gcc clk_gcc_blsp1_qup2_spi_apps_clk>; + status = "disabled"; + }; + + spi_3: spi@c177000 { /* BLSP1 QUP3 */ + compatible = "qcom,spi-qup-v2"; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "spi_physical", "spi_bam_physical"; + reg = <0xC177000 0x600>, + <0xC144000 0x25000>; + interrupt-names = "spi_irq", "spi_bam_irq"; + interrupts = <0 97 0>, <0 238 0>; + spi-max-frequency = <50000000>; + qcom,use-bam; + qcom,ver-reg-exists; + qcom,bam-consumer-pipe-index = <10>; + qcom,bam-producer-pipe-index = <11>; + qcom,master-id = <86>; + qcom,use-pinctrl; + pinctrl-names = "spi_default", "spi_sleep"; + pinctrl-0 = <&spi_3_active>; + pinctrl-1 = <&spi_3_sleep>; + clock-names = "iface_clk", "core_clk"; + clocks = <&clock_gcc clk_gcc_blsp1_ahb_clk>, + <&clock_gcc clk_gcc_blsp1_qup3_spi_apps_clk>; + status = "disabled"; + }; + + spi_4: spi@c178000 { /* BLSP1 QUP4 */ + compatible = "qcom,spi-qup-v2"; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "spi_physical", "spi_bam_physical"; + reg = <0xC178000 0x600>, + <0xC144000 0x25000>; + interrupt-names = "spi_irq", "spi_bam_irq"; + interrupts = <0 98 0>, <0 238 0>; + spi-max-frequency = <50000000>; + qcom,use-bam; + qcom,ver-reg-exists; + qcom,bam-consumer-pipe-index = <12>; + qcom,bam-producer-pipe-index = <13>; + qcom,master-id = <86>; + qcom,use-pinctrl; + pinctrl-names = "spi_default", "spi_sleep"; + pinctrl-0 = <&spi_4_active>; + pinctrl-1 = <&spi_4_sleep>; + clock-names = "iface_clk", "core_clk"; + clocks = <&clock_gcc clk_gcc_blsp1_ahb_clk>, + <&clock_gcc clk_gcc_blsp1_qup4_spi_apps_clk>; + status = "disabled"; + }; + + spi_5: spi@c179000 { /* BLSP1 QUP5 */ + compatible = "qcom,spi-qup-v2"; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "spi_physical", "spi_bam_physical"; + reg = <0xC179000 0x600>, + <0xC144000 0x25000>; + interrupt-names = "spi_irq", "spi_bam_irq"; + interrupts = <0 99 0>, <0 238 0>; + spi-max-frequency = <50000000>; + qcom,use-bam; + qcom,ver-reg-exists; + qcom,bam-consumer-pipe-index = <14>; + qcom,bam-producer-pipe-index = <15>; + qcom,master-id = <86>; + qcom,use-pinctrl; + pinctrl-names = "spi_default", "spi_sleep"; + pinctrl-0 = <&spi_5_active>; + pinctrl-1 = <&spi_5_sleep>; + clock-names = "iface_clk", "core_clk"; + clocks = <&clock_gcc clk_gcc_blsp1_ahb_clk>, + <&clock_gcc clk_gcc_blsp1_qup5_spi_apps_clk>; + status = "disabled"; + }; + + spi_6: spi@c17a000 { /* BLSP1 QUP6 */ + compatible = "qcom,spi-qup-v2"; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "spi_physical", "spi_bam_physical"; + reg = <0xC17A000 0x600>, + <0xC144000 0x25000>; + interrupt-names = "spi_irq", "spi_bam_irq"; + interrupts = <0 100 0>, <0 238 0>; + spi-max-frequency = <50000000>; + qcom,use-bam; + qcom,ver-reg-exists; + qcom,bam-consumer-pipe-index = <16>; + qcom,bam-producer-pipe-index = <17>; + qcom,master-id = <86>; + qcom,use-pinctrl; + pinctrl-names = "spi_default", "spi_sleep"; + pinctrl-0 = <&spi_6_active>; + pinctrl-1 = <&spi_6_sleep>; + clock-names = "iface_clk", "core_clk"; + clocks = <&clock_gcc clk_gcc_blsp1_ahb_clk>, + <&clock_gcc clk_gcc_blsp1_qup6_spi_apps_clk>; + status = "disabled"; + }; + + + spi_7: spi@c1b5000 { /* BLSP2 QUP1 */ + compatible = "qcom,spi-qup-v2"; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "spi_physical", "spi_bam_physical"; + reg = <0xC1B5000 0x600>, + <0xC184000 0x25000>; + interrupt-names = "spi_irq", "spi_bam_irq"; + interrupts = <0 101 0>, <0 239 0>; + spi-max-frequency = <50000000>; + qcom,use-bam; + qcom,ver-reg-exists; + qcom,bam-consumer-pipe-index = <6>; + qcom,bam-producer-pipe-index = <7>; + qcom,master-id = <84>; + qcom,use-pinctrl; + pinctrl-names = "spi_default", "spi_sleep"; + pinctrl-0 = <&spi_7_active>; + pinctrl-1 = <&spi_7_sleep>; + clock-names = "iface_clk", "core_clk"; + clocks = <&clock_gcc clk_gcc_blsp2_ahb_clk>, + <&clock_gcc clk_gcc_blsp2_qup1_spi_apps_clk>; + status = "disabled"; + }; + + spi_8: spi@c1b6000 { /* BLSP2 QUP2 */ + compatible = "qcom,spi-qup-v2"; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "spi_physical", "spi_bam_physical"; + reg = <0xC1B6000 0x600>, + <0xC184000 0x25000>; + interrupt-names = "spi_irq", "spi_bam_irq"; + interrupts = <0 102 0>, <0 239 0>; + spi-max-frequency = <50000000>; + qcom,use-bam; + qcom,ver-reg-exists; + qcom,bam-consumer-pipe-index = <8>; + qcom,bam-producer-pipe-index = <9>; + qcom,master-id = <84>; + qcom,use-pinctrl; + pinctrl-names = "spi_default", "spi_sleep"; + pinctrl-0 = <&spi_8_active>; + pinctrl-1 = <&spi_8_sleep>; + clock-names = "iface_clk", "core_clk"; + clocks = <&clock_gcc clk_gcc_blsp2_ahb_clk>, + <&clock_gcc clk_gcc_blsp2_qup2_spi_apps_clk>; + status = "disabled"; + }; + + spi_9: spi@c1b7000 { /* BLSP2 QUP3 */ + compatible = "qcom,spi-qup-v2"; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "spi_physical", "spi_bam_physical"; + reg = <0xC1B7000 0x600>, + <0xC184000 0x25000>; + interrupt-names = "spi_irq", "spi_bam_irq"; + interrupts = <0 103 0>, <0 239 0>; + spi-max-frequency = <50000000>; + qcom,use-bam; + qcom,ver-reg-exists; + qcom,bam-consumer-pipe-index = <10>; + qcom,bam-producer-pipe-index = <11>; + qcom,master-id = <84>; + qcom,use-pinctrl; + pinctrl-names = "spi_default", "spi_sleep"; + pinctrl-0 = <&spi_9_active>; + pinctrl-1 = <&spi_9_sleep>; + clock-names = "iface_clk", "core_clk"; + clocks = <&clock_gcc clk_gcc_blsp2_ahb_clk>, + <&clock_gcc clk_gcc_blsp2_qup3_spi_apps_clk>; + status = "disabled"; + }; + + spi_10: spi@c1b8000 { /* BLSP2 QUP4 */ + compatible = "qcom,spi-qup-v2"; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "spi_physical", "spi_bam_physical"; + reg = <0xC1B8000 0x600>, + <0xC184000 0x25000>; + interrupt-names = "spi_irq", "spi_bam_irq"; + interrupts = <0 104 0>, <0 239 0>; + spi-max-frequency = <50000000>; + qcom,use-bam; + qcom,ver-reg-exists; + qcom,bam-consumer-pipe-index = <12>; + qcom,bam-producer-pipe-index = <13>; + qcom,master-id = <84>; + qcom,use-pinctrl; + pinctrl-names = "spi_default", "spi_sleep"; + pinctrl-0 = <&spi_10_active>; + pinctrl-1 = <&spi_10_sleep>; + clock-names = "iface_clk", "core_clk"; + clocks = <&clock_gcc clk_gcc_blsp2_ahb_clk>, + <&clock_gcc clk_gcc_blsp2_qup4_spi_apps_clk>; + status = "disabled"; + }; + + spi_11: spi@c1b9000 { /* BLSP2 QUP5 */ + compatible = "qcom,spi-qup-v2"; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "spi_physical", "spi_bam_physical"; + reg = <0xC1B9000 0x600>, + <0xC184000 0x25000>; + interrupt-names = "spi_irq", "spi_bam_irq"; + interrupts = <0 105 0>, <0 239 0>; + spi-max-frequency = <50000000>; + qcom,use-bam; + qcom,ver-reg-exists; + + qcom,bam-consumer-pipe-index = <14>; + qcom,bam-producer-pipe-index = <15>; + qcom,master-id = <84>; + qcom,use-pinctrl; + pinctrl-names = "spi_default", "spi_sleep"; + pinctrl-0 = <&spi_11_active>; + pinctrl-1 = <&spi_11_sleep>; + clock-names = "iface_clk", "core_clk"; + clocks = <&clock_gcc clk_gcc_blsp2_ahb_clk>, + <&clock_gcc clk_gcc_blsp2_qup5_spi_apps_clk>; + status = "disabled"; + }; + + spi_12: spi@c1ba000 { /* BLSP2 QUP6 */ + compatible = "qcom,spi-qup-v2"; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "spi_physical", "spi_bam_physical"; + reg = <0xC1BA000 0x600>, + <0xC184000 0x25000>; + interrupt-names = "spi_irq", "spi_bam_irq"; + interrupts = <0 106 0>, <0 239 0>; + spi-max-frequency = <50000000>; + qcom,use-bam; + qcom,ver-reg-exists; + qcom,bam-consumer-pipe-index = <16>; + qcom,bam-producer-pipe-index = <17>; + qcom,master-id = <84>; + qcom,use-pinctrl; + pinctrl-names = "spi_default", "spi_sleep"; + pinctrl-0 = <&spi_12_active>; + pinctrl-1 = <&spi_12_sleep>; + clock-names = "iface_clk", "core_clk"; + clocks = <&clock_gcc clk_gcc_blsp2_ahb_clk>, + <&clock_gcc clk_gcc_blsp2_qup6_spi_apps_clk>; + status = "disabled"; + }; + + + blsp1_uart1_hs: uart@c16f000 { /* BLSP1 UART1 */ + compatible = "qcom,msm-hsuart-v14"; + reg = <0xC16F000 0x200>, + <0xC144000 0x25000>; + reg-names = "core_mem", "bam_mem"; + interrupt-names = "core_irq", "bam_irq", "wakeup_irq"; + #address-cells = <0>; + interrupt-parent = <&blsp1_uart1_hs>; + interrupts = <0 1 2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0xffffffff>; + interrupt-map = <0 &intc 0 0 107 0 + 1 &intc 0 0 238 0 + 2 &tlmm 1 0>; + + qcom,inject-rx-on-wakeup; + qcom,rx-char-to-inject = <0xFD>; + + qcom,bam-tx-ep-pipe-index = <0>; + qcom,bam-rx-ep-pipe-index = <1>; + qcom,master-id = <86>; + clock-names = "core_clk", "iface_clk"; + clocks = <&clock_gcc clk_gcc_blsp1_uart1_apps_clk>, + <&clock_gcc clk_gcc_blsp1_ahb_clk>; + pinctrl-names = "sleep", "default"; + pinctrl-0 = <&blsp1_uart1_sleep>; + pinctrl-1 = <&blsp1_uart1_active>; + + qcom,msm-bus,name = "buart1"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <86 512 0 0>, + <86 512 500 800>; + status = "disabled"; + }; + + blsp1_uart2_hs: uart@c170000 { /* BLSP1 UART2 */ + compatible = "qcom,msm-hsuart-v14"; + reg = <0xC170000 0x200>, + <0xC144000 0x25000>; + reg-names = "core_mem", "bam_mem"; + interrupt-names = "core_irq", "bam_irq", "wakeup_irq"; + #address-cells = <0>; + interrupt-parent = <&blsp1_uart2_hs>; + interrupts = <0 1 2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0xffffffff>; + interrupt-map = <0 &intc 0 0 108 0 + 1 &intc 0 0 238 0 + 2 &tlmm 34 0>; + + qcom,inject-rx-on-wakeup; + qcom,rx-char-to-inject = <0xFD>; + + qcom,bam-tx-ep-pipe-index = <2>; + qcom,bam-rx-ep-pipe-index = <3>; + qcom,master-id = <86>; + clock-names = "core_clk", "iface_clk"; + clocks = <&clock_gcc clk_gcc_blsp1_uart2_apps_clk>, + <&clock_gcc clk_gcc_blsp1_ahb_clk>; + pinctrl-names = "sleep", "default"; + pinctrl-0 = <&blsp1_uart2_sleep>; + pinctrl-1 = <&blsp1_uart2_active>; + + qcom,msm-bus,name = "buart2"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <86 512 0 0>, + <86 512 500 800>; + status = "disabled"; + }; + + blsp1_uart3_hs: uart@c171000 { /* BLSP1 UART3 */ + compatible = "qcom,msm-hsuart-v14"; + reg = <0xC171000 0x200>, + <0xC144000 0x25000>; + reg-names = "core_mem", "bam_mem"; + interrupt-names = "core_irq", "bam_irq", "wakeup_irq"; + #address-cells = <0>; + interrupt-parent = <&blsp1_uart3_hs>; + interrupts = <0 1 2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0xffffffff>; + interrupt-map = <0 &intc 0 0 109 0 + 1 &intc 0 0 238 0 + 2 &tlmm 46 0>; + + qcom,inject-rx-on-wakeup; + qcom,rx-char-to-inject = <0xFD>; + + qcom,bam-tx-ep-pipe-index = <4>; + qcom,bam-rx-ep-pipe-index = <5>; + qcom,master-id = <86>; + clock-names = "core_clk", "iface_clk"; + clocks = <&clock_gcc clk_gcc_blsp1_uart3_apps_clk>, + <&clock_gcc clk_gcc_blsp1_ahb_clk>; + pinctrl-names = "sleep", "default"; + pinctrl-0 = <&blsp1_uart3_tx_sleep>, <&blsp1_uart3_rxcts_sleep>, + <&blsp1_uart3_rfr_sleep>; + pinctrl-1 = <&blsp1_uart3_tx_active>, + <&blsp1_uart3_rxcts_active>, <&blsp1_uart3_rfr_active>; + + qcom,msm-bus,name = "buart3"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <86 512 0 0>, + <86 512 500 800>; + status = "disabled"; + }; + + blsp2_uart1_hs: uart@c1af000 { /* BLSP2 UART1 */ + compatible = "qcom,msm-hsuart-v14"; + reg = <0xC1AF000 0x200>, + <0xC184000 0x25000>; + reg-names = "core_mem", "bam_mem"; + interrupt-names = "core_irq", "bam_irq", "wakeup_irq"; + #address-cells = <0>; + interrupt-parent = <&blsp2_uart1_hs>; + interrupts = <0 1 2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0xffffffff>; + interrupt-map = <0 &intc 0 0 113 0 + 1 &intc 0 0 239 0 + 2 &tlmm 54 0>; + + qcom,inject-rx-on-wakeup; + qcom,rx-char-to-inject = <0xFD>; + + qcom,bam-tx-ep-pipe-index = <0>; + qcom,bam-rx-ep-pipe-index = <1>; + qcom,master-id = <84>; + clock-names = "core_clk", "iface_clk"; + clocks = <&clock_gcc clk_gcc_blsp2_uart1_apps_clk>, + <&clock_gcc clk_gcc_blsp2_ahb_clk>; + pinctrl-names = "sleep", "default"; + pinctrl-0 = <&blsp2_uart1_sleep>; + pinctrl-1 = <&blsp2_uart1_active>; + + qcom,msm-bus,name = "buart1"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <86 512 0 0>, + <86 512 500 800>; + status = "disabled"; + }; + + blsp2_uart2_hs: uart@c1b0000 { /* BLSP2 UART2 */ + compatible = "qcom,msm-hsuart-v14"; + reg = <0xC1B0000 0x200>, + <0xC184000 0x25000>; + reg-names = "core_mem", "bam_mem"; + interrupt-names = "core_irq", "bam_irq", "wakeup_irq"; + #address-cells = <0>; + interrupt-parent = <&blsp2_uart2_hs>; + interrupts = <0 1 2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0xffffffff>; + interrupt-map = <0 &intc 0 0 114 0 + 1 &intc 0 0 239 0 + 2 &tlmm 5 0>; + + qcom,inject-rx-on-wakeup; + qcom,rx-char-to-inject = <0xFD>; + + qcom,bam-tx-ep-pipe-index = <2>; + qcom,bam-rx-ep-pipe-index = <3>; + qcom,master-id = <84>; + clock-names = "core_clk", "iface_clk"; + clocks = <&clock_gcc clk_gcc_blsp2_uart2_apps_clk>, + <&clock_gcc clk_gcc_blsp2_ahb_clk>; + pinctrl-names = "sleep", "default"; + pinctrl-0 = <&blsp2_uart2_sleep>; + pinctrl-1 = <&blsp2_uart2_active>; + + qcom,msm-bus,name = "buart2"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <86 512 0 0>, + <86 512 500 800>; + status = "disabled"; + }; + + blsp2_uart3_hs: uart@c1b1000 { /* BLSP2 UART3 */ + compatible = "qcom,msm-hsuart-v14"; + reg = <0xC1B1000 0x200>, + <0xC184000 0x25000>; + reg-names = "core_mem", "bam_mem"; + interrupt-names = "core_irq", "bam_irq", "wakeup_irq"; + #address-cells = <0>; + interrupt-parent = <&blsp2_uart3_hs>; + interrupts = <0 1 2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0xffffffff>; + interrupt-map = <0 &intc 0 0 115 0 + 1 &intc 0 0 239 0 + 2 &tlmm 50 0>; + + qcom,inject-rx-on-wakeup; + qcom,rx-char-to-inject = <0xFD>; + + qcom,bam-tx-ep-pipe-index = <4>; + qcom,bam-rx-ep-pipe-index = <5>; + qcom,master-id = <84>; + clock-names = "core_clk", "iface_clk"; + clocks = <&clock_gcc clk_gcc_blsp2_uart3_apps_clk>, + <&clock_gcc clk_gcc_blsp2_ahb_clk>; + pinctrl-names = "sleep", "default"; + pinctrl-0 = <&blsp2_uart3_sleep>; + pinctrl-1 = <&blsp2_uart3_active>; + + qcom,msm-bus,name = "buart3"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <86 512 0 0>, + <86 512 500 800>; + status = "disabled"; + }; +}; diff -Nruw linux-4.4.115-fbx/arch/arm/boot/dts/qcom./msm8998-bus.dtsi linux-4.4.115-fbx/arch/arm/boot/dts/qcom/msm8998-bus.dtsi --- linux-4.4.115-fbx/arch/arm/boot/dts/qcom./msm8998-bus.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ linux-4.4.115-fbx/arch/arm/boot/dts/qcom/msm8998-bus.dtsi 2019-01-22 16:16:21.191225470 +0100 @@ -0,0 +1,1467 @@ +/* Copyright (c) 2016, The Linux Foundation. All rights reserved. + * + * This program is Mree software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +&soc { + ad_hoc_bus: ad-hoc-bus { + /*Version = 4 */ + compatible = "qcom,msm-bus-device"; + reg = <0x1620000 0x40000>, + <0x1000000 0x80000>, + <0x1500000 0x10000>, + <0x1660000 0x60000>, + <0x1700000 0x60000>, + <0x17900000 0x10000>, + <0x1740000 0x10000>, + <0x1740000 0x10000>; + + reg-names = "snoc-base", "bimc-base", "cnoc-base", + "a1noc-base", "a2noc-base", "gnoc-base", + "mmnoc-ahb-base", "mnoc-base"; + + /*Buses*/ + fab_a1noc: fab-a1noc { + cell-id = ; + label = "fab-a1noc"; + qcom,fab-dev; + qcom,base-name = "a1noc-base"; + qcom,bus-type = <1>; + qcom,qos-off = <4096>; + qcom,base-offset = <36864>; + clock-names = "bus_clk", "bus_a_clk"; + clocks = <&clock_gcc clk_aggre1_noc_clk>, + <&clock_gcc clk_aggre1_noc_a_clk>; + qcom,node-qos-clks { + clock-names = + "clk-ufs-axi-clk", + "clk-aggre1-ufs-axi-no-rate", + "clk-aggre1-usb3-axi-cfg-no-rate", + "clk-blsp2-ahb-no-rate"; + clocks = + <&clock_gcc clk_gcc_ufs_axi_clk>, + <&clock_gcc clk_gcc_aggre1_ufs_axi_clk>, + <&clock_gcc clk_gcc_aggre1_usb3_axi_clk>, + <&clock_gcc clk_gcc_blsp2_ahb_clk>; + }; + }; + + fab_a2noc: fab-a2noc { + cell-id = ; + label = "fab-a2noc"; + qcom,fab-dev; + qcom,base-name = "a2noc-base"; + qcom,bus-type = <1>; + qcom,qos-off = <4096>; + qcom,base-offset = <20480>; + clock-names = "bus_clk", "bus_a_clk"; + clocks = <&clock_gcc clk_aggre2_noc_clk>, + <&clock_gcc clk_aggre2_noc_a_clk>; + qcom,node-qos-clks { + clock-names = + "clk-ipa-clk", + "clk-sdcc2-ahb-no-rate", + "clk-sdcc4-ahb-no-rate", + "clk-blsp1-ahb-no-rate"; + clocks = + <&clock_gcc clk_ipa_clk>, + <&clock_gcc clk_gcc_sdcc2_ahb_clk>, + <&clock_gcc clk_gcc_sdcc4_ahb_clk>, + <&clock_gcc clk_gcc_blsp1_ahb_clk>; + }; + }; + + fab_bimc: fab-bimc { + cell-id = ; + label = "fab-bimc"; + qcom,fab-dev; + qcom,base-name = "bimc-base"; + qcom,bus-type = <2>; + qcom,util-fact = <153>; + clock-names = "bus_clk", "bus_a_clk"; + clocks = <&clock_gcc clk_bimc_msmbus_clk>, + <&clock_gcc clk_bimc_msmbus_a_clk>; + }; + + fab_cnoc: fab-cnoc { + cell-id = ; + label = "fab-cnoc"; + qcom,fab-dev; + qcom,base-name = "cnoc-base"; + qcom,bus-type = <1>; + clock-names = "bus_clk", "bus_a_clk"; + clocks = <&clock_gcc clk_cnoc_clk>, + <&clock_gcc clk_cnoc_a_clk>; + }; + + fab_cr_virt: fab-cr_virt { + cell-id = ; + label = "fab-cr_virt"; + qcom,virt-dev; + qcom,base-name = "cr_virt-base"; + qcom,bypass-qos-prg; + }; + + fab_gnoc: fab-gnoc { + cell-id = ; + label = "fab-gnoc"; + qcom,virt-dev; + qcom,base-name = "gnoc-base"; + qcom,bypass-qos-prg; + }; + + fab_mnoc: fab-mnoc { + cell-id = ; + label = "fab-mnoc"; + qcom,fab-dev; + qcom,base-name = "mnoc-base"; + qcom,bus-type = <1>; + qcom,qos-off = <4096>; + qcom,base-offset = <16384>; + qcom,util-fact = <153>; + clock-names = "bus_clk", "bus_a_clk"; + clocks = <&clock_gcc clk_mmssnoc_axi_clk>, + <&clock_gcc clk_mmssnoc_axi_a_clk>; + clk-camss-ahb-no-rate-supply = + <&gdsc_camss_top>; + clk-video-ahb-no-rate-supply = + <&gdsc_venus>; + clk-video-axi-no-rate-supply = + <&gdsc_venus>; + qcom,node-qos-clks { + clock-names = + "clk-noc-cfg-ahb-no-rate", + "clk-mnoc-ahb-no-rate", + "clk-camss-ahb-no-rate", + "clk-video-ahb-no-rate", + "clk-video-axi-no-rate"; + clocks = + <&clock_gcc clk_mmssnoc_axi_clk>, + <&clock_gcc clk_gcc_mmss_noc_cfg_ahb_clk>, + <&clock_mmss clk_mmss_mnoc_ahb_clk>, + <&clock_mmss clk_mmss_camss_ahb_clk>, + <&clock_mmss clk_mmss_video_ahb_clk>, + <&clock_mmss clk_mmss_video_axi_clk>; + }; + + }; + + fab_snoc: fab-snoc { + cell-id = ; + label = "fab-snoc"; + qcom,fab-dev; + qcom,base-name = "snoc-base"; + qcom,bus-type = <1>; + qcom,qos-off = <4096>; + qcom,base-offset = <20480>; + clock-names = "bus_clk", "bus_a_clk"; + clocks = <&clock_gcc clk_snoc_clk>, + <&clock_gcc clk_snoc_a_clk>; + }; + + fab_mnoc_ahb: fab-mnoc-ahb { + cell-id = ; + label = "fab-mnoc-ahb"; + qcom,fab-dev; + qcom,base-name = "mmnoc-ahb-base"; + qcom,bypass-qos-prg; + qcom,setrate-only-clk; + qcom,bus-type = <1>; + clock-names = "bus_clk", "bus_a_clk"; + clocks = <&clock_mmss clk_ahb_clk_src>, + <&clock_mmss clk_ahb_clk_src>; + }; + + + /*Masters*/ + + mas_pcie_0: mas-pcie-0 { + cell-id = ; + label = "mas-pcie-0"; + qcom,buswidth = <16>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,qport = <1>; + qcom,qos-mode = "fixed"; + qcom,connections = <&slv_a1noc_snoc>; + qcom,prio1 = <1>; + qcom,prio0 = <1>; + qcom,bus-dev = <&fab_a1noc>; + qcom,mas-rpm-id = ; + }; + + mas_usb3: mas-usb3 { + cell-id = ; + label = "mas-usb3"; + qcom,buswidth = <16>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,qport = <2>; + qcom,qos-mode = "fixed"; + qcom,connections = <&slv_a1noc_snoc>; + qcom,prio1 = <1>; + qcom,prio0 = <1>; + qcom,bus-dev = <&fab_a1noc>; + qcom,mas-rpm-id = ; + }; + + mas_ufs: mas-ufs { + cell-id = ; + label = "mas-ufs"; + qcom,buswidth = <16>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,qport = <0>; + qcom,qos-mode = "fixed"; + qcom,connections = <&slv_a1noc_snoc>; + qcom,prio1 = <1>; + qcom,prio0 = <1>; + qcom,bus-dev = <&fab_a1noc>; + qcom,mas-rpm-id = ; + }; + + mas_blsp_2: mas-blsp-2 { + cell-id = ; + label = "mas-blsp-2"; + qcom,buswidth = <16>; + qcom,agg-ports = <1>; + qcom,qport = <4>; + qcom,qos-mode = "fixed"; + qcom,connections = <&slv_a1noc_snoc>; + qcom,bus-dev = <&fab_a1noc>; + qcom,mas-rpm-id = ; + }; + + mas_cnoc_a2noc: mas-cnoc-a2noc { + cell-id = <0>; + label = "mas-cnoc-a2noc"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,connections = <&slv_a2noc_snoc>; + qcom,bus-dev = <&fab_a2noc>; + qcom,mas-rpm-id = ; + }; + + mas_ipa: mas-ipa { + cell-id = ; + label = "mas-ipa"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,qport = <1>; + qcom,qos-mode = "fixed"; + qcom,connections = <&slv_a2noc_snoc>; + qcom,prio1 = <1>; + qcom,prio0 = <1>; + qcom,bus-dev = <&fab_a2noc>; + qcom,mas-rpm-id = ; + }; + + mas_sdcc_2: mas-sdcc-2 { + cell-id = ; + label = "mas-sdcc-2"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,qport = <6>; + qcom,qos-mode = "fixed"; + qcom,connections = <&slv_a2noc_snoc>; + qcom,bus-dev = <&fab_a2noc>; + qcom,mas-rpm-id = ; + }; + + mas_sdcc_4: mas-sdcc-4 { + cell-id = ; + label = "mas-sdcc-4"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,qport = <7>; + qcom,qos-mode = "fixed"; + qcom,connections = <&slv_a2noc_snoc>; + qcom,bus-dev = <&fab_a2noc>; + qcom,mas-rpm-id = ; + }; + + mas_tsif: mas-tsif { + cell-id = ; + label = "mas-tsif"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,connections = <&slv_a2noc_snoc>; + qcom,bus-dev = <&fab_a2noc>; + qcom,mas-rpm-id = ; + }; + + mas_blsp_1: mas-blsp-1 { + cell-id = ; + label = "mas-blsp-1"; + qcom,buswidth = <16>; + qcom,agg-ports = <1>; + qcom,qport = <8>; + qcom,qos-mode = "fixed"; + qcom,connections = <&slv_a2noc_snoc>; + qcom,bus-dev = <&fab_a2noc>; + qcom,mas-rpm-id = ; + }; + + mas_cr_virt_a2noc: mas-cr-virt-a2noc { + cell-id = ; + label = "mas-cr-virt-a2noc"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,qport = <9>; + qcom,qos-mode = "fixed"; + qcom,connections = <&slv_a2noc_snoc>; + qcom,bus-dev = <&fab_a2noc>; + qcom,mas-rpm-id = ; + }; + + mas_gnoc_bimc: mas-gnoc-bimc { + cell-id = ; + label = "mas-gnoc-bimc"; + qcom,buswidth = <8>; + qcom,agg-ports = <2>; + qcom,ap-owned; + qcom,qport = <0>; + qcom,qos-mode = "fixed"; + qcom,connections = <&slv_ebi &slv_bimc_snoc_0>; + qcom,prio-lvl = <0>; + qcom,prio-rd = <0>; + qcom,prio-wr = <0>; + qcom,bus-dev = <&fab_bimc>; + qcom,mas-rpm-id = ; + }; + + mas_oxili: mas-oxili { + cell-id = ; + label = "mas-oxili"; + qcom,buswidth = <8>; + qcom,agg-ports = <2>; + qcom,ap-owned; + qcom,qport = <1>; + qcom,qos-mode = "bypass"; + qcom,connections = < &slv_bimc_snoc_1 + &slv_hmss_l3&slv_ebi &slv_bimc_snoc_0>; + qcom,bus-dev = <&fab_bimc>; + qcom,mas-rpm-id = ; + }; + + mas_mnoc_bimc: mas-mnoc-bimc { + cell-id = ; + label = "mas-mnoc-bimc"; + qcom,buswidth = <8>; + qcom,agg-ports = <2>; + qcom,ap-owned; + qcom,qport = <2>; + qcom,qos-mode = "bypass"; + qcom,connections = < &slv_bimc_snoc_1 + &slv_hmss_l3&slv_ebi &slv_bimc_snoc_0>; + qcom,bus-dev = <&fab_bimc>; + qcom,mas-rpm-id = ; + }; + + mas_snoc_bimc: mas-snoc-bimc { + cell-id = ; + label = "mas-snoc-bimc"; + qcom,buswidth = <8>; + qcom,agg-ports = <2>; + qcom,qport = <3>; + qcom,qos-mode = "bypass"; + qcom,connections = < &slv_hmss_l3&slv_ebi>; + qcom,bus-dev = <&fab_bimc>; + qcom,mas-rpm-id = ; + }; + + mas_snoc_cnoc: mas-snoc-cnoc { + cell-id = ; + label = "mas-snoc-cnoc"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,connections = < &slv_skl &slv_blsp_2 + &slv_message_ram + &slv_tlmm_west &slv_tsif + &slv_mpm &slv_bimc_cfg + &slv_tlmm_east &slv_spdm + &slv_pimem_cfg &slv_a1noc_smmu_cfg + &slv_blsp_1 &slv_clk_ctl + &slv_prng &slv_usb3_0 + &slv_qdss_cfg &slv_qm_cfg + &slv_a2noc_cfg &slv_pmic_arb + &slv_ufs_cfg &slv_srvc_cnoc + &slv_ahb2phy &slv_ipa + &slv_glm &slv_snoc_cfg + &slv_ssc_cfg &slv_sdcc_2 + &slv_sdcc_4 &slv_pdm + &slv_cnoc_mnoc_mmss_cfg &slv_cnoc_mnoc_cfg + &slv_mss_cfg &slv_imem_cfg + &slv_a1noc_cfg &slv_gpuss_cfg + &slv_tcsr &slv_tlmm_north>; + qcom,bus-dev = <&fab_cnoc>; + qcom,mas-rpm-id = ; + }; + + mas_qdss_dap: mas-qdss-dap { + cell-id = ; + label = "mas-qdss-dap"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,connections = < &slv_skl &slv_blsp_2 + &slv_message_ram + &slv_tlmm_west &slv_tsif + &slv_mpm &slv_bimc_cfg + &slv_tlmm_east &slv_spdm + &slv_pimem_cfg &slv_a1noc_smmu_cfg + &slv_blsp_1 &slv_clk_ctl + &slv_prng &slv_usb3_0 + &slv_qdss_cfg &slv_qm_cfg + &slv_a2noc_cfg &slv_pmic_arb + &slv_ufs_cfg &slv_srvc_cnoc + &slv_ahb2phy &slv_ipa + &slv_glm &slv_snoc_cfg + &slv_sdcc_2 &slv_sdcc_4 + &slv_pdm &slv_cnoc_mnoc_mmss_cfg + &slv_cnoc_mnoc_cfg &slv_mss_cfg + &slv_imem_cfg &slv_a1noc_cfg + &slv_gpuss_cfg &slv_ssc_cfg + &slv_tcsr &slv_tlmm_north + &slv_cnoc_a2noc>; + qcom,bus-dev = <&fab_cnoc>; + qcom,mas-rpm-id = ; + }; + + mas_crypto_c0: mas-crypto-c0 { + cell-id = ; + label = "mas-crypto-c0"; + qcom,buswidth = <650>; + qcom,agg-ports = <1>; + qcom,connections = <&slv_cr_virt_a2noc>; + qcom,bus-dev = <&fab_a2noc>; + qcom,mas-rpm-id = ; + }; + + mas_apps_proc: mas-apps-proc { + cell-id = ; + label = "mas-apps-proc"; + qcom,buswidth = <32>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,connections = <&slv_gnoc_bimc>; + qcom,bus-dev = <&fab_gnoc>; + qcom,mas-rpm-id = ; + }; + + mas_cnoc_mnoc_mmss_cfg: mas-cnoc-mnoc-mmss-cfg { + cell-id = ; + label = "mas-cnoc-mnoc-mmss-cfg"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,connections = < &slv_camera_throttle_cfg + &slv_venus_cfg &slv_misc_cfg + &slv_camera_cfg &slv_display_throttle_cfg + &slv_venus_throttle_cfg &slv_display_cfg + &slv_mmss_clk_cfg &slv_vmem_cfg + &slv_mmss_clk_xpu_cfg &slv_smmu_cfg>; + qcom,bus-dev = <&fab_mnoc_ahb>; + qcom,mas-rpm-id = ; + }; + + mas_cnoc_mnoc_cfg: mas-cnoc-mnoc-cfg { + cell-id = ; + label = "mas-cnoc-mnoc-cfg"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,connections = <&slv_srvc_mnoc>; + qcom,bus-dev = <&fab_mnoc>; + qcom,mas-rpm-id = ; + }; + + mas_cpp: mas-cpp { + cell-id = ; + label = "mas-cpp"; + qcom,buswidth = <32>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,qport = <5>; + qcom,qos-mode = "bypass"; + qcom,connections = <&slv_mnoc_bimc>; + qcom,bus-dev = <&fab_mnoc>; + qcom,mas-rpm-id = ; + }; + + mas_jpeg: mas-jpeg { + cell-id = ; + label = "mas-jpeg"; + qcom,buswidth = <32>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,qport = <7>; + qcom,qos-mode = "bypass"; + qcom,connections = <&slv_mnoc_bimc>; + qcom,bus-dev = <&fab_mnoc>; + qcom,mas-rpm-id = ; + }; + + mas_mdp_p0: mas-mdp-p0 { + cell-id = ; + label = "mas-mdp-p0"; + qcom,buswidth = <32>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,qport = <1>; + qcom,qos-mode = "bypass"; + qcom,connections = <&slv_mnoc_bimc>; + qcom,bus-dev = <&fab_mnoc>; + qcom,vrail-comp = <25>; + qcom,mas-rpm-id = ; + clk-mdss-axi-no-rate-supply = + <&gdsc_mdss>; + clk-mdss-ahb-no-rate-supply = + <&gdsc_mdss>; + qcom,node-qos-clks { + clock-names = + "clk-mdss-ahb-no-rate", + "clk-mdss-axi-no-rate"; + clocks = + <&clock_mmss clk_mmss_mdss_ahb_clk>, + <&clock_mmss clk_mmss_mdss_axi_clk>; + }; + + }; + + mas_mdp_p1: mas-mdp-p1 { + cell-id = ; + label = "mas-mdp-p1"; + qcom,buswidth = <32>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,qport = <2>; + qcom,qos-mode = "bypass"; + qcom,connections = <&slv_mnoc_bimc>; + qcom,bus-dev = <&fab_mnoc>; + qcom,vrail-comp = <25>; + qcom,mas-rpm-id = ; + }; + + mas_rotator: mas-rotator { + cell-id = ; + label = "mas-rotator"; + qcom,buswidth = <32>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,qport = <0>; + qcom,qos-mode = "bypass"; + qcom,connections = <&slv_mnoc_bimc>; + qcom,bus-dev = <&fab_mnoc>; + qcom,mas-rpm-id = ; + }; + + mas_venus: mas-venus { + cell-id = ; + label = "mas-venus"; + qcom,buswidth = <32>; + qcom,agg-ports = <2>; + qcom,ap-owned; + qcom,qport = <3 4>; + qcom,qos-mode = "bypass"; + qcom,connections = <&slv_mnoc_bimc>; + qcom,bus-dev = <&fab_mnoc>; + qcom,mas-rpm-id = ; + }; + + mas_vfe: mas-vfe { + cell-id = ; + label = "mas-vfe"; + qcom,buswidth = <32>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,qport = <6>; + qcom,qos-mode = "bypass"; + qcom,connections = <&slv_mnoc_bimc>; + qcom,bus-dev = <&fab_mnoc>; + qcom,mas-rpm-id = ; + }; + + mas_venus_vmem: mas-venus-vmem { + cell-id = ; + label = "mas-venus-vmem"; + qcom,buswidth = <32>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,connections = <&slv_vmem>; + qcom,bus-dev = <&fab_mnoc>; + qcom,mas-rpm-id = ; + }; + + mas_hmss: mas-hmss { + cell-id = ; + label = "mas-hmss"; + qcom,buswidth = <16>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,qport = <3>; + qcom,qos-mode = "fixed"; + qcom,connections = < &slv_pimem &slv_imem + &slv_snoc_bimc>; + qcom,prio1 = <1>; + qcom,prio0 = <1>; + qcom,bus-dev = <&fab_snoc>; + qcom,mas-rpm-id = ; + }; + + mas_qdss_bam: mas-qdss-bam { + cell-id = ; + label = "mas-qdss-bam"; + qcom,buswidth = <16>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,qport = <1>; + qcom,qos-mode = "fixed"; + qcom,connections = < &slv_imem &slv_pimem &slv_snoc_cnoc + &slv_snoc_bimc>; + qcom,prio1 = <1>; + qcom,prio0 = <1>; + qcom,bus-dev = <&fab_snoc>; + qcom,mas-rpm-id = ; + }; + + mas_snoc_cfg: mas-snoc-cfg { + cell-id = ; + label = "mas-snoc-cfg"; + qcom,buswidth = <16>; + qcom,agg-ports = <1>; + qcom,connections = <&slv_srvc_snoc>; + qcom,bus-dev = <&fab_snoc>; + qcom,mas-rpm-id = ; + }; + + mas_bimc_snoc_0: mas-bimc-snoc-0 { + cell-id = ; + label = "mas-bimc-snoc-0"; + qcom,buswidth = <16>; + qcom,agg-ports = <1>; + qcom,connections = < &slv_pimem &slv_lpass&slv_hmss + &slv_wlan &slv_snoc_cnoc + &slv_imem &slv_qdss_stm>; + qcom,bus-dev = <&fab_snoc>; + qcom,mas-rpm-id = ; + }; + + mas_bimc_snoc_1: mas-bimc-snoc-1 { + cell-id = ; + label = "mas-bimc-snoc-1"; + qcom,buswidth = <16>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,connections = <&slv_pcie_0>; + qcom,bus-dev = <&fab_snoc>; + qcom,mas-rpm-id = ; + }; + + mas_a1noc_snoc: mas-a1noc-snoc { + cell-id = ; + label = "mas-a1noc-snoc"; + qcom,buswidth = <16>; + qcom,agg-ports = <1>; + qcom,connections = < &slv_pimem &slv_pcie_0 &slv_lpass + &slv_hmss &slv_snoc_bimc + &slv_snoc_cnoc &slv_imem + &slv_qdss_stm>; + qcom,bus-dev = <&fab_snoc>; + qcom,mas-rpm-id = ; + }; + + mas_a2noc_snoc: mas-a2noc-snoc { + cell-id = ; + label = "mas-a2noc-snoc"; + qcom,buswidth = <16>; + qcom,agg-ports = <1>; + qcom,connections = < &slv_pimem &slv_pcie_0 &slv_lpass + &slv_hmss &slv_snoc_bimc + &slv_wlan &slv_snoc_cnoc + &slv_imem &slv_qdss_stm>; + qcom,bus-dev = <&fab_snoc>; + qcom,mas-rpm-id = ; + }; + + mas_qdss_etr: mas-qdss-etr { + cell-id = ; + label = "mas-qdss-etr"; + qcom,buswidth = <16>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,qport = <2>; + qcom,qos-mode = "fixed"; + qcom,connections = < &slv_imem &slv_pimem &slv_snoc_cnoc + &slv_snoc_bimc>; + qcom,prio1 = <1>; + qcom,prio0 = <1>; + qcom,bus-dev = <&fab_snoc>; + qcom,mas-rpm-id = ; + }; + + /*Internal nodes*/ + + /*Slaves*/ + + slv_a1noc_snoc:slv-a1noc-snoc { + cell-id = ; + label = "slv-a1noc-snoc"; + qcom,buswidth = <16>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_a1noc>; + qcom,connections = <&mas_a1noc_snoc>; + qcom,slv-rpm-id = ; + }; + + slv_a2noc_snoc:slv-a2noc-snoc { + cell-id = ; + label = "slv-a2noc-snoc"; + qcom,buswidth = <16>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_a2noc>; + qcom,connections = <&mas_a2noc_snoc>; + qcom,slv-rpm-id = ; + }; + + slv_ebi:slv-ebi { + cell-id = ; + label = "slv-ebi"; + qcom,buswidth = <8>; + qcom,agg-ports = <2>; + qcom,bus-dev = <&fab_bimc>; + qcom,slv-rpm-id = ; + }; + + slv_hmss_l3:slv-hmss-l3 { + cell-id = ; + label = "slv-hmss-l3"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_bimc>; + qcom,slv-rpm-id = ; + }; + + slv_bimc_snoc_0:slv-bimc-snoc-0 { + cell-id = ; + label = "slv-bimc-snoc-0"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_bimc>; + qcom,connections = <&mas_bimc_snoc_0>; + qcom,slv-rpm-id = ; + }; + + slv_bimc_snoc_1:slv-bimc-snoc-1 { + cell-id = ; + label = "slv-bimc-snoc-1"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_bimc>; + qcom,connections = <&mas_bimc_snoc_1>; + qcom,slv-rpm-id = ; + }; + + slv_cnoc_a2noc:slv-cnoc-a2noc { + cell-id = ; + label = "slv-cnoc-a2noc"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_cnoc>; + qcom,connections = <&mas_cnoc_a2noc>; + qcom,slv-rpm-id = ; + }; + + slv_ssc_cfg:slv-ssc-cfg { + cell-id = ; + label = "slv-ssc-cfg"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_cnoc>; + qcom,slv-rpm-id = ; + }; + + slv_mpm:slv-mpm { + cell-id = ; + label = "slv-mpm"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_cnoc>; + qcom,slv-rpm-id = ; + }; + + slv_pmic_arb:slv-pmic-arb { + cell-id = ; + label = "slv-pmic-arb"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_cnoc>; + qcom,slv-rpm-id = ; + }; + slv_tlmm_north:slv-tlmm-north { + cell-id = ; + label = "slv-tlmm-north"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_cnoc>; + qcom,slv-rpm-id = ; + }; + slv_pimem_cfg:slv-pimem-cfg { + cell-id = ; + label = "slv-pimem-cfg"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_cnoc>; + qcom,slv-rpm-id = ; + }; + + slv_imem_cfg:slv-imem-cfg { + cell-id = ; + label = "slv-imem-cfg"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_cnoc>; + qcom,slv-rpm-id = ; + }; + + slv_message_ram:slv-message-ram { + cell-id = ; + label = "slv-message-ram"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_cnoc>; + qcom,slv-rpm-id = ; + }; + + slv_skl:slv-skl { + cell-id = ; + label = "slv-skl"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_cnoc>; + qcom,slv-rpm-id = ; + }; + + slv_bimc_cfg:slv-bimc-cfg { + cell-id = ; + label = "slv-bimc-cfg"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_cnoc>; + qcom,slv-rpm-id = ; + }; + + slv_prng:slv-prng { + cell-id = ; + label = "slv-prng"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_cnoc>; + qcom,slv-rpm-id = ; + }; + + slv_a2noc_cfg:slv-a2noc-cfg { + cell-id = ; + label = "slv-a2noc-cfg"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_cnoc>; + qcom,slv-rpm-id = ; + }; + + slv_ipa:slv-ipa { + cell-id = ; + label = "slv-ipa"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_cnoc>; + qcom,slv-rpm-id = ; + }; + + slv_tcsr:slv-tcsr { + cell-id = ; + label = "slv-tcsr"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_cnoc>; + qcom,slv-rpm-id = ; + }; + + slv_snoc_cfg:slv-snoc-cfg { + cell-id = ; + label = "slv-snoc-cfg"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_cnoc>; + qcom,slv-rpm-id = ; + }; + + slv_clk_ctl:slv-clk-ctl { + cell-id = ; + label = "slv-clk-ctl"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_cnoc>; + qcom,slv-rpm-id = ; + }; + + slv_glm:slv-glm { + cell-id = ; + label = "slv-glm"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_cnoc>; + qcom,slv-rpm-id = ; + }; + + slv_spdm:slv-spdm { + cell-id = ; + label = "slv-spdm"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_cnoc>; + qcom,slv-rpm-id = ; + }; + + slv_gpuss_cfg:slv-gpuss-cfg { + cell-id = ; + label = "slv-gpuss-cfg"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_cnoc>; + qcom,slv-rpm-id = ; + }; + + slv_cnoc_mnoc_cfg:slv-cnoc-mnoc-cfg { + cell-id = ; + label = "slv-cnoc-mnoc-cfg"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_cnoc>; + qcom,connections = <&mas_cnoc_mnoc_cfg>; + qcom,slv-rpm-id = ; + }; + + slv_qm_cfg:slv-qm-cfg { + cell-id = ; + label = "slv-qm-cfg"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_cnoc>; + qcom,slv-rpm-id = ; + }; + + slv_mss_cfg:slv-mss-cfg { + cell-id = ; + label = "slv-mss-cfg"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_cnoc>; + qcom,slv-rpm-id = ; + }; + + slv_ufs_cfg:slv-ufs-cfg { + cell-id = ; + label = "slv-ufs-cfg"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_cnoc>; + qcom,slv-rpm-id = ; + }; + + slv_tlmm_west:slv-tlmm-west { + cell-id = ; + label = "slv-tlmm-west"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_cnoc>; + qcom,slv-rpm-id = ; + }; + + slv_a1noc_cfg:slv-a1noc-cfg { + cell-id = ; + label = "slv-a1noc-cfg"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_cnoc>; + qcom,slv-rpm-id = ; + }; + + slv_ahb2phy:slv-ahb2phy { + cell-id = ; + label = "slv-ahb2phy"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_cnoc>; + qcom,slv-rpm-id = ; + }; + + slv_blsp_2:slv-blsp-2 { + cell-id = ; + label = "slv-blsp-2"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_cnoc>; + qcom,slv-rpm-id = ; + }; + + slv_pdm:slv-pdm { + cell-id = ; + label = "slv-pdm"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_cnoc>; + qcom,slv-rpm-id = ; + }; + + slv_usb3_0:slv-usb3-0 { + cell-id = ; + label = "slv-usb3-0"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_cnoc>; + qcom,slv-rpm-id = ; + }; + + slv_a1noc_smmu_cfg:slv-a1noc-smmu-cfg { + cell-id = ; + label = "slv-a1noc-smmu-cfg"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_cnoc>; + qcom,slv-rpm-id = ; + }; + + slv_blsp_1:slv-blsp-1 { + cell-id = ; + label = "slv-blsp-1"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_cnoc>; + qcom,slv-rpm-id = ; + }; + + slv_sdcc_2:slv-sdcc-2 { + cell-id = ; + label = "slv-sdcc-2"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_cnoc>; + qcom,slv-rpm-id = ; + }; + + slv_sdcc_4:slv-sdcc-4 { + cell-id = ; + label = "slv-sdcc-4"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_cnoc>; + qcom,slv-rpm-id = ; + }; + + slv_tsif:slv-tsif { + cell-id = ; + label = "slv-tsif"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_cnoc>; + qcom,slv-rpm-id = ; + }; + + slv_qdss_cfg:slv-qdss-cfg { + cell-id = ; + label = "slv-qdss-cfg"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_cnoc>; + qcom,slv-rpm-id = ; + }; + + slv_tlmm_east:slv-tlmm-east { + cell-id = ; + label = "slv-tlmm-east"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_cnoc>; + qcom,slv-rpm-id = ; + }; + + slv_cnoc_mnoc_mmss_cfg:slv-cnoc-mnoc-mmss-cfg { + cell-id = ; + label = "slv-cnoc-mnoc-mmss-cfg"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_cnoc>; + qcom,connections = <&mas_cnoc_mnoc_mmss_cfg>; + qcom,slv-rpm-id = ; + }; + + slv_srvc_cnoc:slv-srvc-cnoc { + cell-id = ; + label = "slv-srvc-cnoc"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_cnoc>; + qcom,slv-rpm-id = ; + }; + + slv_cr_virt_a2noc:slv-cr-virt-a2noc { + cell-id = ; + label = "slv-cr-virt-a2noc"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_a2noc>; + qcom,connections = <&mas_cr_virt_a2noc>; + qcom,slv-rpm-id = ; + }; + + slv_gnoc_bimc:slv-gnoc-bimc { + cell-id = ; + label = "slv-gnoc-bimc"; + qcom,buswidth = <32>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_gnoc>; + qcom,connections = <&mas_gnoc_bimc>; + qcom,slv-rpm-id = ; + }; + + slv_camera_cfg:slv-camera-cfg { + cell-id = ; + label = "slv-camera-cfg"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_mnoc_ahb>; + qcom,slv-rpm-id = ; + }; + + slv_camera_throttle_cfg:slv-camera-throttle-cfg { + cell-id = ; + label = "slv-camera-throttle-cfg"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_mnoc_ahb>; + qcom,slv-rpm-id = ; + }; + + slv_misc_cfg:slv-misc-cfg { + cell-id = ; + label = "slv-misc-cfg"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_mnoc_ahb>; + qcom,slv-rpm-id = ; + }; + + slv_venus_throttle_cfg:slv-venus-throttle-cfg { + cell-id = ; + label = "slv-venus-throttle-cfg"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_mnoc_ahb>; + qcom,slv-rpm-id = ; + }; + + slv_venus_cfg:slv-venus-cfg { + cell-id = ; + label = "slv-venus-cfg"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_mnoc_ahb>; + qcom,slv-rpm-id = ; + }; + + slv_vmem_cfg:slv-vmem-cfg { + cell-id = ; + label = "slv-vmem-cfg"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_mnoc_ahb>; + qcom,slv-rpm-id = ; + qcom,enable-only-clk; + clock-names = "node_clk"; + clocks = <&clock_mmss clk_mmss_mnoc_maxi_clk>; + }; + + slv_mmss_clk_xpu_cfg:slv-mmss-clk-xpu-cfg { + cell-id = ; + label = "slv-mmss-clk-xpu-cfg"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_mnoc_ahb>; + qcom,slv-rpm-id = ; + }; + + slv_mmss_clk_cfg:slv-mmss-clk-cfg { + cell-id = ; + label = "slv-mmss-clk-cfg"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_mnoc_ahb>; + qcom,slv-rpm-id = ; + }; + + slv_display_cfg:slv-display-cfg { + cell-id = ; + label = "slv-display-cfg"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_mnoc_ahb>; + qcom,slv-rpm-id = ; + }; + + slv_display_throttle_cfg:slv-display-throttle-cfg { + cell-id = ; + label = "slv-display-throttle-cfg"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_mnoc_ahb>; + qcom,slv-rpm-id = ; + }; + + slv_smmu_cfg:slv-smmu-cfg { + cell-id = ; + label = "slv-smmu-cfg"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_mnoc_ahb>; + qcom,slv-rpm-id = ; + }; + + slv_mnoc_bimc:slv-mnoc-bimc { + cell-id = ; + label = "slv-mnoc-bimc"; + qcom,buswidth = <32>; + qcom,agg-ports = <2>; + qcom,ap-owned; + qcom,bus-dev = <&fab_mnoc>; + qcom,connections = <&mas_mnoc_bimc>; + qcom,slv-rpm-id = ; + qcom,enable-only-clk; + clock-names = "node_clk"; + clocks = <&clock_gcc clk_mmssnoc_axi_clk>; + }; + + slv_vmem: slv-vmem { + cell-id = ; + label = "slv-vmem"; + qcom,buswidth = <32>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_mnoc>; + qcom,slv-rpm-id = ; + clock-names = "node_clk"; + clocks = <&clock_mmss clk_mmss_mnoc_maxi_clk>; + }; + + slv_srvc_mnoc:slv-srvc-mnoc { + cell-id = ; + label = "slv-srvc-mnoc"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_mnoc>; + qcom,slv-rpm-id = ; + }; + + slv_hmss:slv-hmss { + cell-id = ; + label = "slv-hmss"; + qcom,buswidth = <16>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_snoc>; + qcom,slv-rpm-id = ; + }; + + slv_lpass:slv-lpass { + cell-id = ; + label = "slv-lpass"; + qcom,buswidth = <16>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_snoc>; + qcom,slv-rpm-id = ; + }; + + slv_wlan:slv-wlan { + cell-id = ; + label = "slv-wlan"; + qcom,buswidth = <16>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_snoc>; + qcom,slv-rpm-id = ; + }; + + slv_snoc_bimc:slv-snoc-bimc { + cell-id = ; + label = "slv-snoc-bimc"; + qcom,buswidth = <32>; + qcom,agg-ports = <2>; + qcom,bus-dev = <&fab_snoc>; + qcom,connections = <&mas_snoc_bimc>; + qcom,slv-rpm-id = ; + }; + + slv_snoc_cnoc:slv-snoc-cnoc { + cell-id = ; + label = "slv-snoc-cnoc"; + qcom,buswidth = <16>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_snoc>; + qcom,connections = <&mas_snoc_cnoc>; + qcom,slv-rpm-id = ; + }; + + slv_imem:slv-imem { + cell-id = ; + label = "slv-imem"; + qcom,buswidth = <16>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_snoc>; + qcom,slv-rpm-id = ; + }; + + slv_pimem:slv-pimem { + cell-id = ; + label = "slv-pimem"; + qcom,buswidth = <16>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_snoc>; + qcom,slv-rpm-id = ; + }; + + slv_qdss_stm:slv-qdss-stm { + cell-id = ; + label = "slv-qdss-stm"; + qcom,buswidth = <16>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_snoc>; + qcom,slv-rpm-id = ; + }; + + slv_pcie_0:slv-pcie-0 { + cell-id = ; + label = "slv-pcie-0"; + qcom,buswidth = <16>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_snoc>; + qcom,slv-rpm-id = ; + }; + + slv_srvc_snoc:slv-srvc-snoc { + cell-id = ; + label = "slv-srvc-snoc"; + qcom,buswidth = <16>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_snoc>; + qcom,slv-rpm-id = ; + }; + }; + + devfreq_spdm_cpu { + compatible = "qcom,devfreq_spdm"; + qcom,msm-bus,name = "devfreq_spdm"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <1 512 0 0>, + <1 512 0 0>; + qcom,msm-bus,active-only; + qcom,spdm-client = <0>; + + qcom,bw-upstep = <1000>; + qcom,bw-dwnstep = <1000>; + qcom,max-vote = <10000>; + qcom,up-step-multp = <2>; + qcom,spdm-interval = <100>; + + qcom,ports = <24>; + qcom,alpha-up = <12>; + qcom,alpha-down = <15>; + qcom,bucket-size = <8>; + + /*max pl1 freq, max pl2 freq*/ + qcom,pl-freqs = <260000 770000>; + + /* pl1 low, pl1 high, pl2 low, pl2 high, pl3 low, pl3 high */ + qcom,reject-rate = <5000 5000 5000 5000 5000 5000>; + /* pl1 low, pl1 high, pl2 low, pl2 high, pl3 low, pl3 high */ + qcom,response-time-us = <10000 10000 10000 10000 10000 10000>; + /* pl1 low, pl1 high, pl2 low, pl2 high, pl3 low, pl3 high */ + qcom,cci-response-time-us = <10000 10000 10000 + 10000 10000 10000>; + qcom,max-cci-freq = <1036800>; + }; + + devfreq_spdm_gov { + compatible = "qcom,gov_spdm_hyp"; + interrupt-names = "spdm-irq"; + interrupts = <0 192 IRQ_TYPE_EDGE_RISING>; + }; +}; diff -Nruw linux-4.4.115-fbx/arch/arm/boot/dts/qcom./msm8998-camera.dtsi linux-4.4.115-fbx/arch/arm/boot/dts/qcom/msm8998-camera.dtsi --- linux-4.4.115-fbx/arch/arm/boot/dts/qcom./msm8998-camera.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ linux-4.4.115-fbx/arch/arm/boot/dts/qcom/msm8998-camera.dtsi 2019-01-22 16:16:21.195225506 +0100 @@ -0,0 +1,909 @@ +/* + * Copyright (c) 2015-2017, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&soc { + qcom,msm-cam@8c0000 { + compatible = "qcom,msm-cam"; + reg = <0x8c0000 0x40000>; + reg-names = "msm-cam"; + status = "ok"; + bus-vectors = "suspend", "svs", "nominal", "turbo"; + qcom,bus-votes = <0 300000000 640000000 640000000>; + }; + + qcom,csiphy@ca34000 { + cell-index = <0>; + compatible = "qcom,csiphy-v5.0", "qcom,csiphy"; + reg = <0xca34000 0x1000>; + reg-names = "csiphy"; + interrupts = <0 78 0>; + interrupt-names = "csiphy"; + gdscr-supply = <&gdsc_camss_top>; + bimc_smmu-supply = <&gdsc_bimc_smmu>; + qcom,cam-vreg-name = "gdscr", "bimc_smmu"; + clocks = <&clock_gcc clk_mmssnoc_axi_clk>, + <&clock_mmss clk_mmss_mnoc_ahb_clk>, + <&clock_mmss clk_mmss_bimc_smmu_ahb_clk>, + <&clock_mmss clk_mmss_bimc_smmu_axi_clk>, + <&clock_mmss clk_mmss_camss_ahb_clk>, + <&clock_mmss clk_mmss_camss_top_ahb_clk>, + <&clock_mmss clk_csi0_clk_src>, + <&clock_mmss clk_mmss_camss_csi0_clk>, + <&clock_mmss clk_mmss_camss_cphy_csid0_clk>, + <&clock_mmss clk_csi0phytimer_clk_src>, + <&clock_mmss clk_mmss_camss_csi0phytimer_clk>, + <&clock_mmss clk_mmss_camss_ispif_ahb_clk>, + <&clock_mmss clk_csiphy_clk_src>, + <&clock_mmss clk_mmss_camss_csiphy0_clk>; + clock-names = "mmssnoc_axi", "mnoc_ahb", + "bmic_smmu_ahb", "bmic_smmu_axi", + "camss_ahb_clk", "camss_top_ahb_clk", + "csi_src_clk", "csi_clk", "cphy_csid_clk", + "csiphy_timer_src_clk", "csiphy_timer_clk", + "camss_ispif_ahb_clk", "csiphy_clk_src", "csiphy_clk"; + qcom,clock-rates = <0 0 0 0 0 0 274290000 0 0 200000000 0 + 0 274290000 0>; + status = "ok"; + }; + + qcom,csiphy@ca35000 { + cell-index = <1>; + compatible = "qcom,csiphy-v5.0", "qcom,csiphy"; + reg = <0xca35000 0x1000>; + reg-names = "csiphy"; + interrupts = <0 79 0>; + interrupt-names = "csiphy"; + gdscr-supply = <&gdsc_camss_top>; + bimc_smmu-supply = <&gdsc_bimc_smmu>; + qcom,cam-vreg-name = "gdscr", "bimc_smmu"; + clocks = <&clock_gcc clk_mmssnoc_axi_clk>, + <&clock_mmss clk_mmss_mnoc_ahb_clk>, + <&clock_mmss clk_mmss_bimc_smmu_ahb_clk>, + <&clock_mmss clk_mmss_bimc_smmu_axi_clk>, + <&clock_mmss clk_mmss_camss_ahb_clk>, + <&clock_mmss clk_mmss_camss_top_ahb_clk>, + <&clock_mmss clk_csi1_clk_src>, + <&clock_mmss clk_mmss_camss_csi1_clk>, + <&clock_mmss clk_mmss_camss_cphy_csid1_clk>, + <&clock_mmss clk_csi1phytimer_clk_src>, + <&clock_mmss clk_mmss_camss_csi1phytimer_clk>, + <&clock_mmss clk_mmss_camss_ispif_ahb_clk>, + <&clock_mmss clk_csiphy_clk_src>, + <&clock_mmss clk_mmss_camss_csiphy1_clk>; + clock-names = "mmssnoc_axi", "mnoc_ahb", + "bmic_smmu_ahb", "bmic_smmu_axi", + "camss_ahb_clk", "camss_top_ahb_clk", + "csi_src_clk", "csi_clk", "cphy_csid_clk", + "csiphy_timer_src_clk", "csiphy_timer_clk", + "camss_ispif_ahb_clk", "csiphy_clk_src", "csiphy_clk"; + qcom,clock-rates = <0 0 0 0 0 0 274290000 0 0 200000000 0 + 0 274290000 0>; + status = "ok"; + }; + + qcom,csiphy@ca36000 { + cell-index = <2>; + compatible = "qcom,csiphy-v5.0", "qcom,csiphy"; + reg = <0xca36000 0x1000>; + reg-names = "csiphy"; + interrupts = <0 80 0>; + interrupt-names = "csiphy"; + gdscr-supply = <&gdsc_camss_top>; + bimc_smmu-supply = <&gdsc_bimc_smmu>; + qcom,cam-vreg-name = "gdscr", "bimc_smmu"; + clocks = <&clock_gcc clk_mmssnoc_axi_clk>, + <&clock_mmss clk_mmss_mnoc_ahb_clk>, + <&clock_mmss clk_mmss_bimc_smmu_ahb_clk>, + <&clock_mmss clk_mmss_bimc_smmu_axi_clk>, + <&clock_mmss clk_mmss_camss_ahb_clk>, + <&clock_mmss clk_mmss_camss_top_ahb_clk>, + <&clock_mmss clk_csi2_clk_src>, + <&clock_mmss clk_mmss_camss_csi2_clk>, + <&clock_mmss clk_mmss_camss_cphy_csid2_clk>, + <&clock_mmss clk_csi2phytimer_clk_src>, + <&clock_mmss clk_mmss_camss_csi2phytimer_clk>, + <&clock_mmss clk_mmss_camss_ispif_ahb_clk>, + <&clock_mmss clk_csiphy_clk_src>, + <&clock_mmss clk_mmss_camss_csiphy2_clk>; + clock-names = "mmssnoc_axi", "mnoc_ahb", + "bmic_smmu_ahb", "bmic_smmu_axi", + "camss_ahb_clk", "camss_top_ahb_clk", + "csi_src_clk", "csi_clk", "cphy_csid_clk", + "csiphy_timer_src_clk", "csiphy_timer_clk", + "camss_ispif_ahb_clk", "csiphy_clk_src", "csiphy_clk"; + qcom,clock-rates = <0 0 0 0 0 0 274290000 0 0 200000000 0 + 0 274290000 0>; + status = "ok"; + }; + + qcom,csid@ca30000 { + cell-index = <0>; + compatible = "qcom,csid-v5.0", "qcom,csid"; + reg = <0xca30000 0x400>; + reg-names = "csid"; + interrupts = <0 296 0>; + interrupt-names = "csid"; + qcom,csi-vdd-voltage = <1200000>; + qcom,mipi-csi-vdd-supply = <&pm8998_l2>; + gdscr-supply = <&gdsc_camss_top>; + vdd_sec-supply = <&pm8998_l1>; + bimc_smmu-supply = <&gdsc_bimc_smmu>; + qcom,cam-vreg-name = "vdd_sec", "gdscr", "bimc_smmu"; + clocks = <&clock_gcc clk_mmssnoc_axi_clk>, + <&clock_mmss clk_mmss_mnoc_ahb_clk>, + <&clock_mmss clk_mmss_bimc_smmu_ahb_clk>, + <&clock_mmss clk_mmss_bimc_smmu_axi_clk>, + <&clock_mmss clk_mmss_camss_ahb_clk>, + <&clock_mmss clk_mmss_camss_top_ahb_clk>, + <&clock_mmss clk_mmss_camss_ispif_ahb_clk>, + <&clock_mmss clk_csi0_clk_src>, + <&clock_mmss clk_csiphy_clk_src>, + <&clock_mmss clk_mmss_camss_csi0_clk>, + <&clock_mmss clk_mmss_camss_csi0_ahb_clk>, + <&clock_mmss clk_mmss_camss_csi0rdi_clk>, + <&clock_mmss clk_mmss_camss_csi0pix_clk>, + <&clock_mmss clk_mmss_camss_cphy_csid0_clk>; + clock-names = "mmssnoc_axi", "mnoc_ahb", + "bmic_smmu_ahb", "bmic_smmu_axi", + "camss_ahb_clk", "camss_top_ahb_clk", + "ispif_ahb_clk", "csi_src_clk", "csiphy_clk_src", + "csi_clk", "csi_ahb_clk", "csi_rdi_clk", + "csi_pix_clk", "cphy_csid_clk"; + qcom,clock-rates = <0 0 0 0 0 0 0 274290000 274290000 + 0 0 0 0 0>; + status = "ok"; + }; + + qcom,csid@ca30400 { + cell-index = <1>; + compatible = "qcom,csid-v5.0", "qcom,csid"; + reg = <0xca30400 0x400>; + reg-names = "csid"; + interrupts = <0 297 0>; + interrupt-names = "csid"; + qcom,csi-vdd-voltage = <1200000>; + qcom,mipi-csi-vdd-supply = <&pm8998_l2>; + gdscr-supply = <&gdsc_camss_top>; + vdd_sec-supply = <&pm8998_l1>; + bimc_smmu-supply = <&gdsc_bimc_smmu>; + qcom,cam-vreg-name = "vdd_sec", "gdscr", "bimc_smmu"; + clocks = <&clock_gcc clk_mmssnoc_axi_clk>, + <&clock_mmss clk_mmss_mnoc_ahb_clk>, + <&clock_mmss clk_mmss_bimc_smmu_ahb_clk>, + <&clock_mmss clk_mmss_bimc_smmu_axi_clk>, + <&clock_mmss clk_mmss_camss_ahb_clk>, + <&clock_mmss clk_mmss_camss_top_ahb_clk>, + <&clock_mmss clk_mmss_camss_ispif_ahb_clk>, + <&clock_mmss clk_csi1_clk_src>, + <&clock_mmss clk_csiphy_clk_src>, + <&clock_mmss clk_mmss_camss_csi1_clk>, + <&clock_mmss clk_mmss_camss_csi1_ahb_clk>, + <&clock_mmss clk_mmss_camss_csi1rdi_clk>, + <&clock_mmss clk_mmss_camss_csi1pix_clk>, + <&clock_mmss clk_mmss_camss_cphy_csid1_clk>; + clock-names = "mmssnoc_axi", "mnoc_ahb", + "bmic_smmu_ahb", "bmic_smmu_axi", + "camss_ahb_clk", "camss_top_ahb_clk", + "ispif_ahb_clk", "csi_src_clk", "csiphy_clk_src", + "csi_clk", "csi_ahb_clk", "csi_rdi_clk", + "csi_pix_clk", "cphy_csid_clk"; + qcom,clock-rates = <0 0 0 0 0 0 0 274290000 274290000 + 0 0 0 0 0>; + status = "ok"; + }; + + qcom,csid@ca30800 { + cell-index = <2>; + compatible = "qcom,csid-v5.0", "qcom,csid"; + reg = <0xca30800 0x400>; + reg-names = "csid"; + interrupts = <0 298 0>; + interrupt-names = "csid"; + qcom,csi-vdd-voltage = <1200000>; + qcom,mipi-csi-vdd-supply = <&pm8998_l2>; + gdscr-supply = <&gdsc_camss_top>; + vdd_sec-supply = <&pm8998_l1>; + bimc_smmu-supply = <&gdsc_bimc_smmu>; + qcom,cam-vreg-name = "vdd_sec", "gdscr", "bimc_smmu"; + clocks = <&clock_gcc clk_mmssnoc_axi_clk>, + <&clock_mmss clk_mmss_mnoc_ahb_clk>, + <&clock_mmss clk_mmss_bimc_smmu_ahb_clk>, + <&clock_mmss clk_mmss_bimc_smmu_axi_clk>, + <&clock_mmss clk_mmss_camss_ahb_clk>, + <&clock_mmss clk_mmss_camss_top_ahb_clk>, + <&clock_mmss clk_mmss_camss_ispif_ahb_clk>, + <&clock_mmss clk_csi2_clk_src>, + <&clock_mmss clk_csiphy_clk_src>, + <&clock_mmss clk_mmss_camss_csi2_clk>, + <&clock_mmss clk_mmss_camss_csi2_ahb_clk>, + <&clock_mmss clk_mmss_camss_csi2rdi_clk>, + <&clock_mmss clk_mmss_camss_csi2pix_clk>, + <&clock_mmss clk_mmss_camss_cphy_csid2_clk>; + clock-names = "mmssnoc_axi", "mnoc_ahb", + "bmic_smmu_ahb", "bmic_smmu_axi", + "camss_ahb_clk", "camss_top_ahb_clk", + "ispif_ahb_clk", "csi_src_clk", "csiphy_clk_src", + "csi_clk", "csi_ahb_clk", "csi_rdi_clk", + "csi_pix_clk", "cphy_csid_clk"; + qcom,clock-rates = <0 0 0 0 0 0 0 274290000 274290000 + 0 0 0 0 0>; + status = "ok"; + }; + + qcom,csid@ca30c00 { + cell-index = <3>; + compatible = "qcom,csid-v5.0", "qcom,csid"; + reg = <0xca30c00 0x400>; + reg-names = "csid"; + interrupts = <0 299 0>; + interrupt-names = "csid"; + qcom,csi-vdd-voltage = <1200000>; + qcom,mipi-csi-vdd-supply = <&pm8998_l2>; + gdscr-supply = <&gdsc_camss_top>; + vdd_sec-supply = <&pm8998_l1>; + bimc_smmu-supply = <&gdsc_bimc_smmu>; + qcom,cam-vreg-name = "vdd_sec", "gdscr", "bimc_smmu"; + clocks = <&clock_gcc clk_mmssnoc_axi_clk>, + <&clock_mmss clk_mmss_mnoc_ahb_clk>, + <&clock_mmss clk_mmss_bimc_smmu_ahb_clk>, + <&clock_mmss clk_mmss_bimc_smmu_axi_clk>, + <&clock_mmss clk_mmss_camss_ahb_clk>, + <&clock_mmss clk_mmss_camss_top_ahb_clk>, + <&clock_mmss clk_mmss_camss_ispif_ahb_clk>, + <&clock_mmss clk_csi3_clk_src>, + <&clock_mmss clk_csiphy_clk_src>, + <&clock_mmss clk_mmss_camss_csi3_clk>, + <&clock_mmss clk_mmss_camss_csi3_ahb_clk>, + <&clock_mmss clk_mmss_camss_csi3rdi_clk>, + <&clock_mmss clk_mmss_camss_csi3pix_clk>, + <&clock_mmss clk_mmss_camss_cphy_csid3_clk>; + clock-names = "mmssnoc_axi", "mnoc_ahb", + "bmic_smmu_ahb", "bmic_smmu_axi", + "camss_ahb_clk", "camss_top_ahb_clk", + "ispif_ahb_clk", "csi_src_clk", "csiphy_clk_src", + "csi_clk", "csi_ahb_clk", "csi_rdi_clk", + "csi_pix_clk", "cphy_csid_clk"; + qcom,clock-rates = <0 0 0 0 0 0 0 274290000 274290000 + 0 0 0 0 0>; + status = "ok"; + }; + + qcom,cam_smmu { + compatible = "qcom,msm-cam-smmu"; + status = "ok"; + + msm_cam_smmu_cb1 { + compatible = "qcom,msm-cam-smmu-cb"; + iommus = <&mmss_smmu 0xc00>, + <&mmss_smmu 0xc01>, + <&mmss_smmu 0xc02>, + <&mmss_smmu 0xc03>; + label = "vfe"; + qcom,scratch-buf-support; + }; + + msm_cam_smmu_cb2 { + compatible = "qcom,msm-cam-smmu-cb"; + iommus = <&mmss_smmu 0xa00>; + label = "cpp"; + }; + + msm_cam_smmu_cb3 { + compatible = "qcom,msm-cam-smmu-cb"; + iommus = <&mmss_smmu 0xa01>; + label = "camera_fd"; + }; + + msm_cam_smmu_cb4 { + compatible = "qcom,msm-cam-smmu-cb"; + iommus = <&mmss_smmu 0x800>; + label = "jpeg_enc0"; + }; + + msm_cam_smmu_cb5 { + compatible = "qcom,msm-cam-smmu-cb"; + iommus = <&mmss_smmu 0x801>; + label = "jpeg_dma"; + }; + }; + + qcom,fd@caa4000 { + cell-index = <0>; + compatible = "qcom,face-detection"; + reg = <0xcaa4000 0x800>, + <0xcaa5000 0x400>, + <0xca80000 0x3000>; + reg-names = "fd_core", "fd_misc", "fd_vbif"; + interrupts = <0 293 0>; + interrupt-names = "fd"; + smmu-vdd-supply = <&gdsc_bimc_smmu>; + camss-vdd-supply = <&gdsc_camss_top>; + vdd-supply = <&gdsc_cpp>; + qcom,vdd-names = "smmu-vdd", "camss-vdd", "vdd"; + clocks = <&clock_gcc clk_mmssnoc_axi_clk>, + <&clock_mmss clk_mmss_mnoc_ahb_clk>, + <&clock_mmss clk_mmss_bimc_smmu_ahb_clk>, + <&clock_mmss clk_mmss_bimc_smmu_axi_clk>, + <&clock_mmss clk_mmss_camss_ahb_clk>, + <&clock_mmss clk_mmss_camss_top_ahb_clk>, + <&clock_mmss clk_mmss_fd_core_clk>, + <&clock_mmss clk_mmss_fd_core_uar_clk>, + <&clock_mmss clk_mmss_fd_ahb_clk>, + <&clock_mmss clk_mmss_camss_cpp_axi_clk>, + <&clock_mmss clk_mmss_camss_cpp_vbif_ahb_clk>; + clock-names = "mmssnoc_axi", + "mmss_mnoc_ahb_clk", + "mmss_bimc_smmu_ahb_clk", + "mmss_bimc_smmu_axi_clk", + "mmss_camss_ahb_clk", + "mmss_camss_top_ahb_clk", + "mmss_fd_core_clk", + "mmss_fd_core_uar_clk", + "mmss_fd_ahb_clk", + "mmss_camss_cpp_axi_clk", + "mmss_camss_cpp_vbif_ahb_clk"; + qcom,clock-rates = + <0 0 0 0 0 0 404000000 0 0 0 0>, + <0 0 0 0 0 0 100000000 0 0 0 0>, + <0 0 0 0 0 0 404000000 0 0 0 0>, + <0 0 0 0 0 0 404000000 0 0 0 0>; + qcom,msm-bus,name = "msm_camera_fd"; + qcom,msm-bus,num-cases = <4>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = <106 512 0 0>, + <106 512 1625 0>, + <106 512 2995 0>, + <106 512 7200 0>; + qcom,fd-vbif-reg-settings = <0x20 0x10000000 0x30000000>, + <0x24 0x10000000 0x30000000>, + <0x28 0x10000000 0x30000000>, + <0x2c 0x10000000 0x30000000>; + qcom,fd-misc-reg-settings = <0x20 0x2 0x3>, + <0x24 0x2 0x3>; + status = "ok"; + }; + + qcom,cpp@ca04000 { + cell-index = <0>; + compatible = "qcom,cpp"; + reg = <0xca04000 0x100>, + <0xca80000 0x3000>, + <0xca18000 0x3000>, + <0xc8c36D4 0x4>; + reg-names = "cpp", "cpp_vbif", "cpp_hw", "camss_cpp"; + interrupts = <0 294 0>; + interrupt-names = "cpp"; + smmu-vdd-supply = <&gdsc_bimc_smmu>; + camss-vdd-supply = <&gdsc_camss_top>; + vdd-supply = <&gdsc_cpp>; + qcom,vdd-names = "smmu-vdd", "camss-vdd", "vdd"; + clocks = <&clock_gcc clk_mmssnoc_axi_clk>, + <&clock_mmss clk_mmss_mnoc_ahb_clk>, + <&clock_mmss clk_mmss_camss_ahb_clk>, + <&clock_mmss clk_mmss_camss_top_ahb_clk>, + <&clock_mmss clk_cpp_clk_src>, + <&clock_mmss clk_mmss_camss_cpp_clk>, + <&clock_mmss clk_mmss_camss_cpp_ahb_clk>, + <&clock_mmss clk_mmss_camss_cpp_axi_clk>, + <&clock_mmss clk_mmss_camss_micro_ahb_clk>, + <&clock_mmss clk_mmss_bimc_smmu_axi_clk>, + <&clock_mmss clk_mmss_camss_cpp_vbif_ahb_clk>; + clock-names = "mmssnoc_axi_clk", + "mnoc_ahb_clk", + "camss_ahb_clk", "camss_top_ahb_clk", + "cpp_src_clk", + "cpp_core_clk", "camss_cpp_ahb_clk", + "camss_cpp_axi_clk", "micro_iface_clk", + "mmss_smmu_axi_clk", "cpp_vbif_ahb_clk"; + qcom,clock-rates = <0 0 0 0 200000000 200000000 0 0 0 0 0>; + qcom,min-clock-rate = <200000000>; + qcom,bus-master = <1>; + qcom,vbif-qos-setting = <0x550 0x33333333>, + <0x554 0x03333333>, + <0x558 0x33333333>, + <0x55c 0x03333333>, + <0x560 0x33333333>, + <0x564 0x03333333>, + <0x568 0x33333333>, + <0x56c 0x03333333>, + <0x570 0x33333333>, + <0x574 0x03333333>, + <0x578 0x33333333>, + <0x57c 0x03333333>, + <0x580 0x33333333>, + <0x584 0x03333333>, + <0x588 0x33333333>, + <0x58c 0x03333333>; + status = "ok"; + qcom,msm-bus,name = "msm_camera_cpp"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <106 512 0 0>, + <106 512 0 0>; + qcom,msm-bus-vector-dyn-vote; + resets = <&clock_mmss CAMSS_MICRO_BCR>; + reset-names = "micro_iface_reset"; + qcom,src-clock-rates = <100000000 200000000 576000000 + 600000000>; + qcom,micro-reset; + qcom,cpp-fw-payload-info { + qcom,stripe-base = <790>; + qcom,plane-base = <715>; + qcom,stripe-size = <63>; + qcom,plane-size = <25>; + qcom,fe-ptr-off = <11>; + qcom,we-ptr-off = <23>; + qcom,ref-fe-ptr-off = <17>; + qcom,ref-we-ptr-off = <36>; + qcom,we-meta-ptr-off = <42>; + qcom,fe-mmu-pf-ptr-off = <7>; + qcom,ref-fe-mmu-pf-ptr-off = <10>; + qcom,we-mmu-pf-ptr-off = <13>; + qcom,dup-we-mmu-pf-ptr-off = <18>; + qcom,ref-we-mmu-pf-ptr-off = <23>; + qcom,set-group-buffer-len = <135>; + qcom,dup-frame-indicator-off = <70>; + }; + }; + + qcom,ispif@ca31000 { + cell-index = <0>; + compatible = "qcom,ispif-v3.0", "qcom,ispif"; + reg = <0xca31000 0xc00>, + <0xca00020 0x4>; + reg-names = "ispif", "csi_clk_mux"; + interrupts = <0 309 0>; + interrupt-names = "ispif"; + qcom,num-isps = <0x2>; + camss-vdd-supply = <&gdsc_camss_top>; + vfe0-vdd-supply = <&gdsc_vfe0>; + vfe1-vdd-supply = <&gdsc_vfe1>; + qcom,vdd-names = "camss-vdd", "vfe0-vdd", + "vfe1-vdd"; + qcom,clock-cntl-support; + clocks = <&clock_gcc clk_mmssnoc_axi_clk>, + <&clock_mmss clk_mmss_mnoc_ahb_clk>, + <&clock_mmss clk_mmss_camss_ahb_clk>, + <&clock_mmss clk_mmss_camss_top_ahb_clk>, + <&clock_mmss clk_mmss_camss_ispif_ahb_clk>, + <&clock_mmss clk_csi0_clk_src>, + <&clock_mmss clk_csi1_clk_src>, + <&clock_mmss clk_csi2_clk_src>, + <&clock_mmss clk_csi3_clk_src>, + <&clock_mmss clk_mmss_camss_csi0rdi_clk>, + <&clock_mmss clk_mmss_camss_csi1rdi_clk>, + <&clock_mmss clk_mmss_camss_csi2rdi_clk>, + <&clock_mmss clk_mmss_camss_csi3rdi_clk>, + <&clock_mmss clk_mmss_camss_csi0pix_clk>, + <&clock_mmss clk_mmss_camss_csi1pix_clk>, + <&clock_mmss clk_mmss_camss_csi2pix_clk>, + <&clock_mmss clk_mmss_camss_csi3pix_clk>, + <&clock_mmss clk_mmss_camss_csi0_clk>, + <&clock_mmss clk_mmss_camss_csi1_clk>, + <&clock_mmss clk_mmss_camss_csi2_clk>, + <&clock_mmss clk_mmss_camss_csi3_clk>, + <&clock_mmss clk_vfe0_clk_src>, + <&clock_mmss clk_mmss_camss_vfe0_clk>, + <&clock_mmss clk_mmss_camss_csi_vfe0_clk>, + <&clock_mmss clk_vfe1_clk_src>, + <&clock_mmss clk_mmss_camss_vfe1_clk>, + <&clock_mmss clk_mmss_camss_csi_vfe1_clk>; + clock-names = "mmssnoc_axi", "mnoc_ahb_clk", + "camss_ahb_clk", + "camss_top_ahb_clk", "ispif_ahb_clk", + "csi0_src_clk", "csi1_src_clk", + "csi2_src_clk", "csi3_src_clk", + "csi0_rdi_clk", "csi1_rdi_clk", + "csi2_rdi_clk", "csi3_rdi_clk", + "csi0_pix_clk", "csi1_pix_clk", + "csi2_pix_clk", "csi3_pix_clk", + "camss_csi0_clk", "camss_csi1_clk", + "camss_csi2_clk", "camss_csi3_clk", + "vfe0_clk_src", + "camss_vfe_vfe0_clk", + "camss_csi_vfe0_clk", + "vfe1_clk_src", + "camss_vfe_vfe1_clk", + "camss_csi_vfe1_clk"; + qcom,clock-rates = <0 0 0 0 0 + 0 0 0 0 + 0 0 0 0 + 0 0 0 0 + 0 0 0 0 + 0 0 0 + 0 0 0>; + qcom,clock-control = "INIT_RATE", "NO_SET_RATE", + "NO_SET_RATE", "NO_SET_RATE", + "NO_SET_RATE", + "INIT_RATE", "INIT_RATE", + "INIT_RATE", "INIT_RATE", + "NO_SET_RATE", "NO_SET_RATE", + "NO_SET_RATE", "NO_SET_RATE", + "NO_SET_RATE", "NO_SET_RATE", + "NO_SET_RATE", "NO_SET_RATE", + "NO_SET_RATE", "NO_SET_RATE", + "NO_SET_RATE", "NO_SET_RATE", + "INIT_RATE", + "NO_SET_RATE", "NO_SET_RATE", + "INIT_RATE", + "NO_SET_RATE", "NO_SET_RATE"; + status = "ok"; + }; + + vfe0: qcom,vfe0@ca10000 { + cell-index = <0>; + compatible = "qcom,vfe48"; + reg = <0xca10000 0x4000>, + <0xca40000 0x3000>; + reg-names = "vfe", "vfe_vbif"; + interrupts = <0 314 0>; + interrupt-names = "vfe"; + vdd-supply = <&gdsc_vfe0>; + camss-vdd-supply = <&gdsc_camss_top>; + smmu-vdd-supply = <&gdsc_bimc_smmu>; + qcom,vdd-names = "vdd", "camss-vdd", "smmu-vdd"; + clocks = <&clock_gcc clk_mmssnoc_axi_clk>, + <&clock_mmss clk_mmss_mnoc_ahb_clk>, + <&clock_mmss clk_mmss_bimc_smmu_ahb_clk>, + <&clock_mmss clk_mmss_bimc_smmu_axi_clk>, + <&clock_mmss clk_mmss_camss_ahb_clk>, + <&clock_mmss clk_mmss_camss_top_ahb_clk>, + <&clock_mmss clk_vfe0_clk_src>, + <&clock_mmss clk_mmss_camss_vfe0_clk>, + <&clock_mmss clk_mmss_camss_vfe0_stream_clk>, + <&clock_mmss clk_mmss_camss_vfe0_ahb_clk>, + <&clock_mmss clk_mmss_camss_vfe_vbif_ahb_clk>, + <&clock_mmss clk_mmss_camss_vfe_vbif_axi_clk>, + <&clock_mmss clk_mmss_camss_csi_vfe0_clk>; + clock-names = "mmssnoc_axi", "mnoc_ahb_clk", + "bimc_smmu_ahb_clk", "bimc_smmu_axi_clk", + "camss_ahb_clk", "camss_top_ahb_clk", "vfe_clk_src", + "camss_vfe_clk", "camss_vfe_stream_clk", + "camss_vfe_ahb_clk", "camss_vfe_vbif_ahb_clk", + "camss_vfe_vbif_axi_clk", + "camss_csi_vfe_clk"; + qcom,clock-rates = <0 0 0 0 0 0 480000000 0 0 0 0 0 0 + 0 0 0 0 0 0 576000000 0 0 0 0 0 0 + 0 0 0 0 0 0 600000000 0 0 0 0 0 0>; + status = "ok"; + qos-entries = <8>; + qos-regs = <0x404 0x408 0x40c 0x410 0x414 0x418 + 0x41c 0x420>; + qos-settings = <0xaaa9aaa9 + 0xaaa9aaa9 + 0xaaa9aaa9 + 0xaaa9aaa9 + 0xaaa9aaa9 + 0xaaa9aaa9 + 0xaaa9aaa9 + 0xaaa9aaa9>; + vbif-entries = <1>; + vbif-regs = <0x124>; + vbif-settings = <0x3>; + ds-entries = <17>; + ds-regs = <0x424 0x428 0x42c 0x430 0x434 + 0x438 0x43c 0x440 0x444 0x448 0x44c + 0x450 0x454 0x458 0x45c 0x460 0x464>; + ds-settings = <0xcccc0011 + 0xcccc0011 + 0xcccc0011 + 0xcccc0011 + 0xcccc0011 + 0xcccc0011 + 0xcccc0011 + 0xcccc0011 + 0xcccc0011 + 0xcccc0011 + 0xcccc0011 + 0xcccc0011 + 0xcccc0011 + 0xcccc0011 + 0xcccc0011 + 0xcccc0011 + 0x40000103>; + qcom,msm-bus,name = "msm_camera_vfe"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <29 512 0 0>, + <29 512 100000000 100000000>; + qcom,msm-bus-vector-dyn-vote; + }; + + vfe1: qcom,vfe1@ca14000 { + cell-index = <1>; + compatible = "qcom,vfe48"; + reg = <0xca14000 0x4000>, + <0xca40000 0x3000>; + reg-names = "vfe", "vfe_vbif"; + interrupts = <0 315 0>; + interrupt-names = "vfe"; + vdd-supply = <&gdsc_vfe1>; + camss-vdd-supply = <&gdsc_camss_top>; + smmu-vdd-supply = <&gdsc_bimc_smmu>; + qcom,vdd-names = "vdd", "camss-vdd", "smmu-vdd"; + clocks = <&clock_gcc clk_mmssnoc_axi_clk>, + <&clock_mmss clk_mmss_mnoc_ahb_clk>, + <&clock_mmss clk_mmss_bimc_smmu_ahb_clk>, + <&clock_mmss clk_mmss_bimc_smmu_axi_clk>, + <&clock_mmss clk_mmss_camss_ahb_clk>, + <&clock_mmss clk_mmss_camss_top_ahb_clk>, + <&clock_mmss clk_vfe1_clk_src>, + <&clock_mmss clk_mmss_camss_vfe1_clk>, + <&clock_mmss clk_mmss_camss_vfe1_stream_clk>, + <&clock_mmss clk_mmss_camss_vfe1_ahb_clk>, + <&clock_mmss clk_mmss_camss_vfe_vbif_ahb_clk>, + <&clock_mmss clk_mmss_camss_vfe_vbif_axi_clk>, + <&clock_mmss clk_mmss_camss_csi_vfe1_clk>; + clock-names = "mmssnoc_axi", "mnoc_ahb_clk", + "bimc_smmu_ahb_clk", "bimc_smmu_axi_clk", + "camss_ahb_clk", "camss_top_ahb_clk", "vfe_clk_src", + "camss_vfe_clk", "camss_vfe_stream_clk", + "camss_vfe_ahb_clk", "camss_vfe_vbif_ahb_clk", + "camss_vfe_vbif_axi_clk", + "camss_csi_vfe_clk"; + qcom,clock-rates = <0 0 0 0 0 0 480000000 0 0 0 0 0 0 + 0 0 0 0 0 0 576000000 0 0 0 0 0 0 + 0 0 0 0 0 0 600000000 0 0 0 0 0 0>; + status = "ok"; + qos-entries = <8>; + qos-regs = <0x404 0x408 0x40c 0x410 0x414 0x418 + 0x41c 0x420>; + qos-settings = <0xaaa9aaa9 + 0xaaa9aaa9 + 0xaaa9aaa9 + 0xaaa9aaa9 + 0xaaa9aaa9 + 0xaaa9aaa9 + 0xaaa9aaa9 + 0xaaa9aaa9>; + vbif-entries = <1>; + vbif-regs = <0x124>; + vbif-settings = <0x3>; + ds-entries = <17>; + ds-regs = <0x424 0x428 0x42c 0x430 0x434 + 0x438 0x43c 0x440 0x444 0x448 0x44c + 0x450 0x454 0x458 0x45c 0x460 0x464>; + ds-settings = <0xcccc0011 + 0xcccc0011 + 0xcccc0011 + 0xcccc0011 + 0xcccc0011 + 0xcccc0011 + 0xcccc0011 + 0xcccc0011 + 0xcccc0011 + 0xcccc0011 + 0xcccc0011 + 0xcccc0011 + 0xcccc0011 + 0xcccc0011 + 0xcccc0011 + 0xcccc0011 + 0x40000103>; + qcom,msm-bus,name = "msm_camera_vfe"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <29 512 0 0>, + <29 512 100000000 100000000>; + qcom,msm-bus-vector-dyn-vote; + }; + + qcom,vfe { + compatible = "qcom,vfe"; + num_child = <2>; + }; + + cci: qcom,cci@ca0c000 { + cell-index = <0>; + compatible = "qcom,cci"; + reg = <0xca0c000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "cci"; + interrupts = <0 295 0>; + interrupt-names = "cci"; + status = "ok"; + mmagic-supply = <&gdsc_bimc_smmu>; + gdscr-supply = <&gdsc_camss_top>; + qcom,cam-vreg-name = "mmagic", "gdscr"; + clocks = <&clock_gcc clk_mmssnoc_axi_clk>, + <&clock_mmss clk_mmss_mnoc_ahb_clk>, + <&clock_mmss clk_mmss_bimc_smmu_ahb_clk>, + <&clock_mmss clk_mmss_bimc_smmu_axi_clk>, + <&clock_mmss clk_mmss_camss_ahb_clk>, + <&clock_mmss clk_mmss_camss_top_ahb_clk>, + <&clock_mmss clk_cci_clk_src>, + <&clock_mmss clk_mmss_camss_cci_ahb_clk>, + <&clock_mmss clk_mmss_camss_cci_clk>; + clock-names = "mmssnoc_axi", "mnoc_ahb", "smmu_ahb", "smmu_axi", + "camss_ahb_clk", "camss_top_ahb_clk", + "cci_src_clk", "cci_ahb_clk", "camss_cci_clk"; + qcom,clock-rates = <0 0 0 0 0 0 19200000 0 0>, + <0 0 0 0 0 0 37500000 0 0>; + pinctrl-names = "cci_default", "cci_suspend"; + pinctrl-0 = <&cci0_active &cci1_active>; + pinctrl-1 = <&cci0_suspend &cci1_suspend>; + gpios = <&tlmm 17 0>, + <&tlmm 18 0>, + <&tlmm 19 0>, + <&tlmm 20 0>; + qcom,gpio-tbl-num = <0 1 2 3>; + qcom,gpio-tbl-flags = <1 1 1 1>; + qcom,gpio-tbl-label = "CCI_I2C_DATA0", + "CCI_I2C_CLK0", + "CCI_I2C_DATA1", + "CCI_I2C_CLK1"; + i2c_freq_100Khz: qcom,i2c_standard_mode { + status = "disabled"; + }; + i2c_freq_400Khz: qcom,i2c_fast_mode { + status = "disabled"; + }; + i2c_freq_custom: qcom,i2c_custom_mode { + status = "disabled"; + }; + i2c_freq_1Mhz: qcom,i2c_fast_plus_mode { + status = "disabled"; + }; + }; + + qcom,jpeg@ca1c000 { + cell-index = <0>; + compatible = "qcom,jpeg"; + reg = <0xca1c000 0x4000>, + <0xca60000 0x3000>; + reg-names = "jpeg_hw", "jpeg_vbif"; + interrupts = <0 316 0>; + interrupt-names = "jpeg"; + smmu-vdd-supply = <&gdsc_bimc_smmu>; + camss-vdd-supply = <&gdsc_camss_top>; + qcom,vdd-names = "smmu-vdd", "camss-vdd"; + clock-names = "mmssnoc_axi", + "mmss_mnoc_ahb_clk", + "mmss_bimc_smmu_ahb_clk", + "mmss_bimc_smmu_axi_clk", + "mmss_camss_ahb_clk", + "mmss_camss_top_ahb_clk", + "core_clk", + "mmss_camss_jpeg_ahb_clk", + "mmss_camss_jpeg_axi_clk"; + clocks = <&clock_gcc clk_mmssnoc_axi_clk>, + <&clock_mmss clk_mmss_mnoc_ahb_clk>, + <&clock_mmss clk_mmss_bimc_smmu_ahb_clk>, + <&clock_mmss clk_mmss_bimc_smmu_axi_clk>, + <&clock_mmss clk_mmss_camss_ahb_clk>, + <&clock_mmss clk_mmss_camss_top_ahb_clk>, + <&clock_mmss clk_mmss_camss_jpeg0_vote_clk>, + <&clock_mmss clk_mmss_camss_jpeg_ahb_clk>, + <&clock_mmss clk_mmss_camss_jpeg_axi_clk>; + qcom,clock-rates = <0 0 0 0 0 0 480000000 0 0>; + qcom,vbif-reg-settings = <0x4 0x1>; + qcom,prefetch-reg-settings = <0x30c 0x1111>, + <0x318 0x31>, + <0x324 0x31>, + <0x330 0x31>, + <0x33c 0x0>; + qcom,msm-bus,name = "msm_camera_jpeg0"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = <62 512 0 0>, + <62 512 1920000 2880000>; + status = "ok"; + }; + + qcom,jpeg@caa0000 { + cell-index = <3>; + compatible = "qcom,jpegdma"; + reg = <0xcaa0000 0x4000>, + <0xca60000 0x3000>; + reg-names = "jpeg_hw", "jpeg_vbif"; + interrupts = <0 304 0>; + interrupt-names = "jpeg"; + smmu-vdd-supply = <&gdsc_bimc_smmu>; + camss-vdd-supply = <&gdsc_camss_top>; + qcom,vdd-names = "smmu-vdd", "camss-vdd"; + clock-names = "mmssnoc_axi", + "mmss_mnoc_ahb_clk", + "mmss_bimc_smmu_ahb_clk", + "mmss_bimc_smmu_axi_clk", + "mmss_camss_ahb_clk", + "mmss_camss_top_ahb_clk", + "core_clk", + "mmss_camss_jpeg_ahb_clk", + "mmss_camss_jpeg_axi_clk"; + clocks = <&clock_gcc clk_mmssnoc_axi_clk>, + <&clock_mmss clk_mmss_mnoc_ahb_clk>, + <&clock_mmss clk_mmss_bimc_smmu_ahb_clk>, + <&clock_mmss clk_mmss_bimc_smmu_axi_clk>, + <&clock_mmss clk_mmss_camss_ahb_clk>, + <&clock_mmss clk_mmss_camss_top_ahb_clk>, + <&clock_mmss clk_mmss_camss_jpeg0_dma_vote_clk>, + <&clock_mmss clk_mmss_camss_jpeg_ahb_clk>, + <&clock_mmss clk_mmss_camss_jpeg_axi_clk>; + qcom,clock-rates = <0 0 0 0 0 0 480000000 0 0>; + qcom,vbif-reg-settings = <0x4 0x1>; + qcom,prefetch-reg-settings = <0x18c 0x11>, + <0x1a0 0x31>, + <0x1b0 0x31>; + qcom,msm-bus,name = "msm_camera_jpeg_dma"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = <62 512 0 0>, + <62 512 1920000 2880000>; + qcom,max-ds-factor = <128>; + status = "ok"; + }; +}; + +&i2c_freq_100Khz { + qcom,hw-thigh = <201>; + qcom,hw-tlow = <174>; + qcom,hw-tsu-sto = <204>; + qcom,hw-tsu-sta = <231>; + qcom,hw-thd-dat = <22>; + qcom,hw-thd-sta = <162>; + qcom,hw-tbuf = <227>; + qcom,hw-scl-stretch-en = <0>; + qcom,hw-trdhld = <6>; + qcom,hw-tsp = <3>; + qcom,cci-clk-src = <37500000>; + status = "ok"; +}; + +&i2c_freq_400Khz { + qcom,hw-thigh = <38>; + qcom,hw-tlow = <56>; + qcom,hw-tsu-sto = <40>; + qcom,hw-tsu-sta = <40>; + qcom,hw-thd-dat = <22>; + qcom,hw-thd-sta = <35>; + qcom,hw-tbuf = <62>; + qcom,hw-scl-stretch-en = <0>; + qcom,hw-trdhld = <6>; + qcom,hw-tsp = <3>; + qcom,cci-clk-src = <37500000>; + status = "ok"; +}; + +&i2c_freq_custom { + qcom,hw-thigh = <38>; + qcom,hw-tlow = <56>; + qcom,hw-tsu-sto = <40>; + qcom,hw-tsu-sta = <40>; + qcom,hw-thd-dat = <22>; + qcom,hw-thd-sta = <35>; + qcom,hw-tbuf = <62>; + qcom,hw-scl-stretch-en = <1>; + qcom,hw-trdhld = <6>; + qcom,hw-tsp = <3>; + qcom,cci-clk-src = <37500000>; + status = "ok"; +}; + +&i2c_freq_1Mhz { + qcom,hw-thigh = <16>; + qcom,hw-tlow = <22>; + qcom,hw-tsu-sto = <17>; + qcom,hw-tsu-sta = <18>; + qcom,hw-thd-dat = <16>; + qcom,hw-thd-sta = <15>; + qcom,hw-tbuf = <24>; + qcom,hw-scl-stretch-en = <0>; + qcom,hw-trdhld = <3>; + qcom,hw-tsp = <3>; + qcom,cci-clk-src = <37500000>; + status = "ok"; +}; diff -Nruw linux-4.4.115-fbx/arch/arm/boot/dts/qcom./msm8998-cdp.dtsi linux-4.4.115-fbx/arch/arm/boot/dts/qcom/msm8998-cdp.dtsi --- linux-4.4.115-fbx/arch/arm/boot/dts/qcom./msm8998-cdp.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ linux-4.4.115-fbx/arch/arm/boot/dts/qcom/msm8998-cdp.dtsi 2019-10-29 09:26:22.917196073 +0100 @@ -0,0 +1,348 @@ +/* Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "msm8998-audio-wcd.dtsi" +#include "msm-smb138x.dtsi" + +&vendor { + bluetooth: bt_wcn3990 { + compatible = "qca,wcn3990"; + qca,bt-vdd-io-supply = <&pm8998_s3>; + qca,bt-vdd-xtal-supply = <&pm8998_s5>; + qca,bt-vdd-core-supply = <&pm8998_l7>; + qca,bt-vdd-pa-supply = <&pm8998_l17>; + qca,bt-vdd-ldo-supply = <&pm8998_l25>; + qca,bt-chip-pwd-supply = <&pmi8998_bob_pin1>; + clocks = <&clock_gcc clk_rf_clk2_pin>; + clock-names = "rf_clk2"; + + qca,bt-vdd-io-voltage-level = <1352000 1352000>; + qca,bt-vdd-xtal-voltage-level = <2040000 2040000>; + qca,bt-vdd-core-voltage-level = <1800000 1800000>; + qca,bt-vdd-pa-voltage-level = <1304000 1304000>; + qca,bt-vdd-ldo-voltage-level = <3312000 3312000>; + qca,bt-chip-pwd-voltage-level = <3600000 3600000>; + + qca,bt-vdd-io-current-level = <1>; /* LPM/PFM */ + qca,bt-vdd-xtal-current-level = <1>; /* LPM/PFM */ + qca,bt-vdd-core-current-level = <1>; /* LPM/PFM */ + qca,bt-vdd-pa-current-level = <1>; /* LPM/PFM */ + qca,bt-vdd-ldo-current-level = <1>; /* LPM/PFM */ + }; +}; + +&blsp1_uart3_hs { + status = "ok"; +}; + +&ufsphy1 { + vdda-phy-supply = <&pm8998_l1>; + vdda-pll-supply = <&pm8998_l2>; + vddp-ref-clk-supply = <&pm8998_l26>; + vdda-phy-max-microamp = <51400>; + vdda-pll-max-microamp = <14600>; + vddp-ref-clk-max-microamp = <100>; + vddp-ref-clk-always-on; + status = "ok"; +}; + +&ufs1 { + vdd-hba-supply = <&gdsc_ufs>; + vdd-hba-fixed-regulator; + vcc-supply = <&pm8998_l20>; + vccq-supply = <&pm8998_l26>; + vccq2-supply = <&pm8998_s4>; + vcc-max-microamp = <750000>; + vccq-max-microamp = <560000>; + vccq2-max-microamp = <750000>; + status = "ok"; +}; + +&ufs_ice { + status = "ok"; +}; + +&sdhc_2 { + vdd-supply = <&pm8998_l21>; + qcom,vdd-voltage-level = <2950000 2960000>; + qcom,vdd-current-level = <200 800000>; + + vdd-io-supply = <&pm8998_l13>; + qcom,vdd-io-voltage-level = <1808000 2960000>; + qcom,vdd-io-current-level = <200 22000>; + + pinctrl-names = "active", "sleep"; + pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>; + pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>; + + qcom,clk-rates = <400000 20000000 25000000 + 50000000 100000000 200000000>; + qcom,bus-speed-mode = "SDR12", "SDR25", "SDR50", "DDR50", "SDR104"; + + cd-gpios = <&tlmm 95 0x1>; + + status = "ok"; +}; + +&uartblsp2dm1 { + status = "ok"; + pinctrl-names = "default"; + pinctrl-0 = <&uart_console_active>; +}; + +&pm8998_gpios { + /* GPIO 5 for Home Key */ + gpio@c400 { + status = "okay"; + qcom,mode = <0>; + qcom,pull = <0>; + qcom,vin-sel = <0>; + qcom,src-sel = <0>; + qcom,out-strength = <1>; + }; + + /* GPIO 6 for Vol+ Key */ + gpio@c500 { + status = "okay"; + qcom,mode = <0>; + qcom,pull = <0>; + qcom,vin-sel = <0>; + qcom,src-sel = <0>; + qcom,out-strength = <1>; + }; + + /* GPIO 7 for Snapshot Key */ + gpio@c600 { + status = "okay"; + qcom,mode = <0>; + qcom,pull = <0>; + qcom,vin-sel = <0>; + qcom,src-sel = <0>; + qcom,out-strength = <1>; + }; + + /* GPIO 8 for Focus Key */ + gpio@c700 { + status = "okay"; + qcom,mode = <0>; + qcom,pull = <0>; + qcom,vin-sel = <0>; + qcom,src-sel = <0>; + qcom,out-strength = <1>; + }; + + gpio@cc00 { /* GPIO 13 */ + qcom,mode = <1>; + qcom,output-type = <0>; + qcom,pull = <5>; + qcom,vin-sel = <0>; + qcom,out-strength = <1>; + qcom,src-sel = <3>; + qcom,master-en = <1>; + status = "okay"; + }; + + gpio@d200 { /* GPIO 19 - wil6210 refclk3_en */ + qcom,mode = <0>; /* Input */ + qcom,pull = <5>; /* No Pull */ + qcom,vin-sel = <1>; /* VIN1 GPIO_MV */ + qcom,src-sel = <0>; /* GPIO */ + qcom,invert = <0>; /* Invert */ + qcom,master-en = <1>; /* Enable GPIO */ + status = "okay"; + }; + + /* GPIO 21 (NFC_CLK_REQ) */ + gpio@d400 { + qcom,mode = <0>; + qcom,vin-sel = <1>; + qcom,src-sel = <0>; + qcom,master-en = <1>; + status = "okay"; + }; +}; + +&labibb { + status = "ok"; + qcom,qpnp-labibb-mode = "lcd"; +}; + +&pmi8998_wled { + qcom,led-strings-list = [00 01]; +}; + +&pmi8998_charger { + qcom,batteryless-platform; +}; + +&pmi8998_haptics { + status = "okay"; +}; + +&pm8998_vadc { + chan@83 { + label = "vph_pwr"; + reg = <0x83>; + qcom,decimation = <2>; + qcom,pre-div-channel-scaling = <1>; + qcom,calibration-type = "absolute"; + qcom,scale-function = <0>; + qcom,hw-settle-time = <0>; + qcom,fast-avg-setup = <0>; + }; + + chan@85 { + label = "vcoin"; + reg = <0x85>; + qcom,decimation = <2>; + qcom,pre-div-channel-scaling = <1>; + qcom,calibration-type = "absolute"; + qcom,scale-function = <0>; + qcom,hw-settle-time = <0>; + qcom,fast-avg-setup = <0>; + }; + + chan@4c { + label = "xo_therm"; + reg = <0x4c>; + qcom,decimation = <2>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "ratiometric"; + qcom,scale-function = <4>; + qcom,hw-settle-time = <2>; + qcom,fast-avg-setup = <0>; + }; + + chan@4d { + label = "msm_therm"; + reg = <0x4d>; + qcom,decimation = <2>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "ratiometric"; + qcom,scale-function = <2>; + qcom,hw-settle-time = <2>; + qcom,fast-avg-setup = <0>; + }; + + chan@51 { + label = "quiet_therm"; + reg = <0x51>; + qcom,decimation = <2>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "ratiometric"; + qcom,scale-function = <2>; + qcom,hw-settle-time = <2>; + qcom,fast-avg-setup = <0>; + }; +}; + +&pm8998_adc_tm { + chan@83 { + label = "vph_pwr"; + reg = <0x83>; + qcom,pre-div-channel-scaling = <1>; + qcom,calibration-type = "absolute"; + qcom,scale-function = <0>; + qcom,hw-settle-time = <0>; + qcom,btm-channel-number = <0x60>; + }; + + chan@4d { + label = "msm_therm"; + reg = <0x4d>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "ratiometric"; + qcom,scale-function = <2>; + qcom,hw-settle-time = <2>; + qcom,btm-channel-number = <0x68>; + qcom,thermal-node; + }; + + chan@51 { + label = "quiet_therm"; + reg = <0x51>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "ratiometric"; + qcom,scale-function = <2>; + qcom,hw-settle-time = <2>; + qcom,btm-channel-number = <0x70>; + qcom,thermal-node; + }; + + chan@4c { + label = "xo_therm"; + reg = <0x4c>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "ratiometric"; + qcom,scale-function = <4>; + qcom,hw-settle-time = <2>; + qcom,btm-channel-number = <0x78>; + qcom,thermal-node; + }; +}; + +&wil6210 { + status = "ok"; +}; + +&snd_9335 { + qcom,mbhc-audio-jack-type = "6-pole-jack"; +}; + +&snd_934x { + qcom,mbhc-audio-jack-type = "6-pole-jack"; +}; + +&soc { + gpio_keys { + compatible = "gpio-keys"; + input-name = "gpio-keys"; + status = "okay"; + + home { + label = "home"; + gpios = <&pm8998_gpios 5 0x1>; + linux,input-type = <1>; + linux,code = <102>; + gpio-key,wakeup; + debounce-interval = <15>; + + }; + + vol_up { + label = "volume_up"; + gpios = <&pm8998_gpios 6 0x1>; + linux,input-type = <1>; + linux,code = <115>; + gpio-key,wakeup; + debounce-interval = <15>; + }; + + cam_snapshot { + label = "cam_snapshot"; + gpios = <&pm8998_gpios 7 0x1>; + linux,input-type = <1>; + linux,code = <766>; + gpio-key,wakeup; + debounce-interval = <15>; + }; + + cam_focus { + label = "cam_focus"; + gpios = <&pm8998_gpios 8 0x1>; + linux,input-type = <1>; + linux,code = <528>; + gpio-key,wakeup; + debounce-interval = <15>; + }; + }; +}; diff -Nruw linux-4.4.115-fbx/arch/arm/boot/dts/qcom./msm8998-coresight.dtsi linux-4.4.115-fbx/arch/arm/boot/dts/qcom/msm8998-coresight.dtsi --- linux-4.4.115-fbx/arch/arm/boot/dts/qcom./msm8998-coresight.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ linux-4.4.115-fbx/arch/arm/boot/dts/qcom/msm8998-coresight.dtsi 2019-01-22 16:16:21.195225506 +0100 @@ -0,0 +1,1622 @@ +/* Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&soc { + tmc_etr: tmc@6048000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b961>; + + reg = <0x6048000 0x1000>, + <0x6064000 0x15000>; + reg-names = "tmc-base", "bam-base"; + + arm,buffer-size = <0x400000>; + arm,sg-enable; + + coresight-ctis = <&cti0 &cti8>; + + coresight-name = "coresight-tmc-etr"; + + clocks = <&clock_gcc clk_qdss_clk>, + <&clock_gcc clk_qdss_a_clk>; + clock-names = "apb_pclk", "core_a_clk"; + + port{ + tmc_etr_in_replicator: endpoint { + slave-mode; + remote-endpoint = <&replicator_out_tmc_etr>; + }; + }; + }; + + replicator: replicator@6046000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b909>; + + reg = <0x6046000 0x1000>; + reg-names = "replicator-base"; + + coresight-name = "coresight-replicator"; + + clocks = <&clock_gcc clk_qdss_clk>, + <&clock_gcc clk_qdss_a_clk>; + clock-names = "apb_pclk", "core_a_clk"; + + ports{ + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + replicator_out_tmc_etr:endpoint { + remote-endpoint = + <&tmc_etr_in_replicator>; + }; + }; + port@1 { + reg = <0>; + replicator_in_tmc_etf:endpoint { + slave-mode; + remote-endpoint = + <&tmc_etf_out_replicator>; + }; + }; + }; + }; + + tmc_etf: tmc@6047000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b961>; + + reg = <0x6047000 0x1000>; + reg-names = "tmc-base"; + + coresight-ctis = <&cti0 &cti8>; + + coresight-name = "coresight-tmc-etf"; + + arm,default-sink; + + clocks = <&clock_gcc clk_qdss_clk>, + <&clock_gcc clk_qdss_a_clk>; + clock-names = "apb_pclk", "core_a_clk"; + + ports{ + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + tmc_etf_out_replicator:endpoint { + remote-endpoint = + <&replicator_in_tmc_etf>; + }; + }; + port@1 { + reg = <0>; + tmc_etf_in_funnel_merg:endpoint { + slave-mode; + remote-endpoint = + <&funnel_merg_out_tmc_etf>; + }; + }; + }; + }; + + funnel_merg: funnel@6045000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b908>; + + reg = <0x6045000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-merg"; + + clocks = <&clock_gcc clk_qdss_clk>, + <&clock_gcc clk_qdss_a_clk>; + clock-names = "apb_pclk", "core_a_clk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_merg_out_tmc_etf:endpoint { + remote-endpoint = + <&tmc_etf_in_funnel_merg>; + }; + }; + port@1 { + reg = <0>; + funnel_merg_in_funnel_in0:endpoint { + slave-mode; + remote-endpoint = + <&funnel_in0_out_funnel_merg>; + }; + }; + port@2 { + reg = <1>; + funnel_merg_in_funnel_in1:endpoint { + slave-mode; + remote-endpoint = + <&funnel_in1_out_funnel_merg>; + }; + }; + }; + }; + + funnel_in0: funnel@6041000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b908>; + + reg = <0x6041000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-in0"; + + clocks = <&clock_gcc clk_qdss_clk>, + <&clock_gcc clk_qdss_a_clk>; + clock-names = "apb_pclk", "core_a_clk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_in0_out_funnel_merg: endpoint { + remote-endpoint = + <&funnel_merg_in_funnel_in0>; + }; + }; + port@1 { + reg = <0>; + funnel_in0_in_rpm_etm0: endpoint { + slave-mode; + remote-endpoint = + <&rpm_etm0_out_funnel_in0>; + }; + }; + port@2 { + reg = <3>; + funnel_in0_in_funnel_spss: endpoint { + slave-mode; + remote-endpoint = + <&funnel_spss_out_funnel_in0>; + }; + }; + port@3 { + reg = <6>; + funnel_in0_in_funnel_qatb: endpoint { + slave-mode; + remote-endpoint = + <&funnel_qatb_out_funnel_in0>; + }; + }; + port@4 { + reg = <7>; + funnel_in0_in_stm: endpoint { + slave-mode; + remote-endpoint = <&stm_out_funnel_in0>; + }; + }; + }; + }; + + funnel_in1: funnel@6042000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b908>; + + reg = <0x6042000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-in1"; + + clocks = <&clock_gcc clk_qdss_clk>, + <&clock_gcc clk_qdss_a_clk>; + clock-names = "apb_pclk", "core_a_clk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_in1_out_funnel_merg: endpoint { + remote-endpoint = + <&funnel_merg_in_funnel_in1>; + }; + }; + port@1 { + reg = <2>; + funnel_in1_in_tpda_nav: endpoint { + slave-mode; + remote-endpoint = + <&tpda_nav_out_funnel_in1>; + }; + }; + port@2 { + reg = <3>; + funnel_in1_in_tpda_mss: endpoint { + slave-mode; + remote-endpoint = + <&tpda_mss_out_funnel_in1>; + }; + }; + port@3 { + reg = <4>; + funnel_in1_in_audio_etm0: endpoint { + slave-mode; + remote-endpoint = + <&audio_etm0_out_funnel_in1>; + }; + }; + port@4 { + reg = <5>; + funnel_in1_in_modem_etm0: endpoint { + slave-mode; + remote-endpoint = + <&modem_etm0_out_funnel_in1>; + }; + }; + port@5 { + reg = <6>; + funnel_in1_in_funnel_apss_merg: endpoint { + slave-mode; + remote-endpoint = + <&funnel_apss_merg_out_funnel_in1>; + }; + }; + port@6 { + reg = <7>; + funnel_in1_in_gfx: endpoint { + slave-mode; + remote-endpoint = + <&gfx_out_funnel_in1>; + }; + }; + }; + }; + + funnel_apss_merg: funnel@7b70000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b908>; + + reg = <0x7b70000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-apss-merg"; + + clocks = <&clock_gcc clk_qdss_clk>, + <&clock_gcc clk_qdss_a_clk>; + clock-names = "apb_pclk", "core_a_clk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_apss_merg_out_funnel_in1: endpoint { + remote-endpoint = + <&funnel_in1_in_funnel_apss_merg>; + }; + }; + port@1 { + reg = <0>; + funnel_apss_merg_in_funnel_apss: endpoint { + slave-mode; + remote-endpoint = + <&funnel_apss_out_funnel_apss_merg>; + }; + }; + port@2 { + reg = <1>; + funnel_apss_merg_in_tpda_olc: endpoint { + slave-mode; + remote-endpoint = + <&tpda_olc_out_funnel_apss_merg>; + }; + }; + port@3 { + reg = <3>; + funnel_apss_merg_in_tpda_apss: endpoint { + slave-mode; + remote-endpoint = + <&tpda_apss_out_funnel_apss_merg>; + }; + }; + }; + }; + + funnel_apss: funnel@7b60000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b908>; + + reg = <0x7b60000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-apss"; + + clocks = <&clock_gcc clk_qdss_clk>, + <&clock_gcc clk_qdss_a_clk>; + clock-names = "apb_pclk", "core_a_clk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_apss_out_funnel_apss_merg: endpoint { + remote-endpoint = + <&funnel_apss_merg_in_funnel_apss>; + }; + }; + port@1 { + reg = <0>; + funnel_apss_in_etm0: endpoint { + slave-mode; + remote-endpoint = + <&etm0_out_funnel_apss>; + }; + }; + port@2 { + reg = <1>; + funnel_apss_in_etm1: endpoint { + slave-mode; + remote-endpoint = + <&etm1_out_funnel_apss>; + }; + }; + port@3 { + reg = <2>; + funnel_apss_in_etm2: endpoint { + slave-mode; + remote-endpoint = + <&etm2_out_funnel_apss>; + }; + }; + port@4 { + reg = <3>; + funnel_apss_in_etm3: endpoint { + slave-mode; + remote-endpoint = + <&etm3_out_funnel_apss>; + }; + }; + port@5 { + reg = <4>; + funnel_apss_in_etm4: endpoint { + slave-mode; + remote-endpoint = + <&etm4_out_funnel_apss>; + }; + }; + port@6 { + reg = <5>; + funnel_apss_in_etm5: endpoint { + slave-mode; + remote-endpoint = + <&etm5_out_funnel_apss>; + }; + }; + port@7 { + reg = <6>; + funnel_apss_in_etm6: endpoint { + slave-mode; + remote-endpoint = + <&etm6_out_funnel_apss>; + }; + }; + port@8 { + reg = <7>; + funnel_apss_in_etm7: endpoint { + slave-mode; + remote-endpoint = + <&etm7_out_funnel_apss>; + }; + }; + }; + }; + + stm: stm@6002000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b962>; + + reg = <0x6002000 0x1000>, + <0x16280000 0x180000>; + reg-names = "stm-base", "stm-data-base"; + + coresight-name = "coresight-stm"; + + clocks = <&clock_gcc clk_qdss_clk>, + <&clock_gcc clk_qdss_a_clk>; + clock-names = "apb_pclk", "core_a_clk"; + + port{ + stm_out_funnel_in0: endpoint { + remote-endpoint = <&funnel_in0_in_stm>; + }; + }; + }; + + etm0: etm@7840000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b95d>; + + reg = <0x7840000 0x1000>; + cpu = <&CPU0>; + + coresight-name = "coresight-etm0"; + + clocks = <&clock_gcc clk_qdss_clk>, + <&clock_gcc clk_qdss_a_clk>; + clock-names = "apb_pclk", "core_a_clk"; + + port{ + etm0_out_funnel_apss: endpoint { + remote-endpoint = <&funnel_apss_in_etm0>; + }; + }; + }; + + etm1: etm@7940000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b95d>; + + reg = <0x7940000 0x1000>; + cpu = <&CPU1>; + + coresight-name = "coresight-etm1"; + + clocks = <&clock_gcc clk_qdss_clk>, + <&clock_gcc clk_qdss_a_clk>; + clock-names = "apb_pclk", "core_a_clk"; + + port{ + etm1_out_funnel_apss: endpoint { + remote-endpoint = <&funnel_apss_in_etm1>; + }; + }; + }; + + etm2: etm@7A40000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b95d>; + + reg = <0x7A40000 0x1000>; + cpu = <&CPU2>; + + coresight-name = "coresight-etm2"; + + clocks = <&clock_gcc clk_qdss_clk>, + <&clock_gcc clk_qdss_a_clk>; + clock-names = "apb_pclk", "core_a_clk"; + + port{ + etm2_out_funnel_apss: endpoint { + remote-endpoint = <&funnel_apss_in_etm2>; + }; + }; + }; + + etm3: etm@7B40000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b95d>; + + reg = <0x7B40000 0x1000>; + cpu = <&CPU3>; + + coresight-name = "coresight-etm3"; + + clocks = <&clock_gcc clk_qdss_clk>, + <&clock_gcc clk_qdss_a_clk>; + clock-names = "apb_pclk", "core_a_clk"; + + port{ + etm3_out_funnel_apss: endpoint { + remote-endpoint = <&funnel_apss_in_etm3>; + }; + }; + }; + + etm4: etm@7C40000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b95d>; + + reg = <0x7C40000 0x1000>; + cpu = <&CPU4>; + + coresight-name = "coresight-etm4"; + + clocks = <&clock_gcc clk_qdss_clk>, + <&clock_gcc clk_qdss_a_clk>; + clock-names = "apb_pclk", "core_a_clk"; + + port{ + etm4_out_funnel_apss: endpoint { + remote-endpoint = <&funnel_apss_in_etm4>; + }; + }; + }; + + etm5: etm@7D40000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b95d>; + + reg = <0x7D40000 0x1000>; + cpu = <&CPU5>; + + coresight-name = "coresight-etm5"; + + clocks = <&clock_gcc clk_qdss_clk>, + <&clock_gcc clk_qdss_a_clk>; + clock-names = "apb_pclk", "core_a_clk"; + + port{ + etm5_out_funnel_apss: endpoint { + remote-endpoint = <&funnel_apss_in_etm5>; + }; + }; + }; + + etm6: etm@7E40000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b95d>; + + reg = <0x7E40000 0x1000>; + cpu = <&CPU6>; + + coresight-name = "coresight-etm6"; + + clocks = <&clock_gcc clk_qdss_clk>, + <&clock_gcc clk_qdss_a_clk>; + clock-names = "apb_pclk", "core_a_clk"; + + port{ + etm6_out_funnel_apss: endpoint { + remote-endpoint = <&funnel_apss_in_etm6>; + }; + }; + }; + + etm7: etm@7F40000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b95d>; + + reg = <0x7F40000 0x1000>; + cpu = <&CPU7>; + + coresight-name = "coresight-etm7"; + + clocks = <&clock_gcc clk_qdss_clk>, + <&clock_gcc clk_qdss_a_clk>; + clock-names = "apb_pclk", "core_a_clk"; + + port{ + etm7_out_funnel_apss: endpoint { + remote-endpoint = <&funnel_apss_in_etm7>; + }; + }; + }; + + cti0: cti@6010000 { + compatible = "arm,coresight-cti"; + reg = <0x6010000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti0"; + + clocks = <&clock_gcc clk_qdss_clk>, + <&clock_gcc clk_qdss_a_clk>; + clock-names = "core_clk", "core_a_clk"; + }; + + cti1: cti@6011000 { + compatible = "arm,coresight-cti"; + reg = <0x6011000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti1"; + + clocks = <&clock_gcc clk_qdss_clk>, + <&clock_gcc clk_qdss_a_clk>; + clock-names = "core_clk", "core_a_clk"; + }; + + cti2: cti@6012000 { + compatible = "arm,coresight-cti"; + reg = <0x6012000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti2"; + + clocks = <&clock_gcc clk_qdss_clk>, + <&clock_gcc clk_qdss_a_clk>; + clock-names = "core_clk", "core_a_clk"; + + qcom,cti-gpio-trigout = <4>; + pinctrl-names = "cti-trigout-pctrl"; + pinctrl-0 = <&trigout_a>; + }; + + cti3: cti@6013000 { + compatible = "arm,coresight-cti"; + reg = <0x6013000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti3"; + + clocks = <&clock_gcc clk_qdss_clk>, + <&clock_gcc clk_qdss_a_clk>; + clock-names = "core_clk", "core_a_clk"; + }; + + cti4: cti@6014000 { + compatible = "arm,coresight-cti"; + reg = <0x6014000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti4"; + + clocks = <&clock_gcc clk_qdss_clk>, + <&clock_gcc clk_qdss_a_clk>; + clock-names = "core_clk", "core_a_clk"; + }; + + cti5: cti@6015000 { + compatible = "arm,coresight-cti"; + reg = <0x6015000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti5"; + + clocks = <&clock_gcc clk_qdss_clk>, + <&clock_gcc clk_qdss_a_clk>; + clock-names = "core_clk", "core_a_clk"; + }; + + cti6: cti@6016000 { + compatible = "arm,coresight-cti"; + reg = <0x6016000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti6"; + + clocks = <&clock_gcc clk_qdss_clk>, + <&clock_gcc clk_qdss_a_clk>; + clock-names = "core_clk", "core_a_clk"; + }; + + cti7: cti@6017000 { + compatible = "arm,coresight-cti"; + reg = <0x6017000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti7"; + + clocks = <&clock_gcc clk_qdss_clk>, + <&clock_gcc clk_qdss_a_clk>; + clock-names = "core_clk", "core_a_clk"; + }; + + cti8: cti@6018000 { + compatible = "arm,coresight-cti"; + reg = <0x6018000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti8"; + + clocks = <&clock_gcc clk_qdss_clk>, + <&clock_gcc clk_qdss_a_clk>; + clock-names = "core_clk", "core_a_clk"; + }; + + cti9: cti@6019000 { + compatible = "arm,coresight-cti"; + reg = <0x6019000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti9"; + + clocks = <&clock_gcc clk_qdss_clk>, + <&clock_gcc clk_qdss_a_clk>; + clock-names = "core_clk", "core_a_clk"; + }; + + cti10: cti@601a000 { + compatible = "arm,coresight-cti"; + reg = <0x601a000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti10"; + + clocks = <&clock_gcc clk_qdss_clk>, + <&clock_gcc clk_qdss_a_clk>; + clock-names = "core_clk", "core_a_clk"; + }; + + cti11: cti@601b000 { + compatible = "arm,coresight-cti"; + reg = <0x601b000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti11"; + + clocks = <&clock_gcc clk_qdss_clk>, + <&clock_gcc clk_qdss_a_clk>; + clock-names = "core_clk", "core_a_clk"; + }; + + cti12: cti@601c000 { + compatible = "arm,coresight-cti"; + reg = <0x601c000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti12"; + + clocks = <&clock_gcc clk_qdss_clk>, + <&clock_gcc clk_qdss_a_clk>; + clock-names = "core_clk", "core_a_clk"; + }; + + cti13: cti@601d000 { + compatible = "arm,coresight-cti"; + reg = <0x601d000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti13"; + + clocks = <&clock_gcc clk_qdss_clk>, + <&clock_gcc clk_qdss_a_clk>; + clock-names = "core_clk", "core_a_clk"; + }; + + cti14: cti@601e000 { + compatible = "arm,coresight-cti"; + reg = <0x601e000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti14"; + + clocks = <&clock_gcc clk_qdss_clk>, + <&clock_gcc clk_qdss_a_clk>; + clock-names = "core_clk", "core_a_clk"; + }; + + cti15: cti@601f000 { + compatible = "arm,coresight-cti"; + reg = <0x601f000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti15"; + + clocks = <&clock_gcc clk_qdss_clk>, + <&clock_gcc clk_qdss_a_clk>; + clock-names = "core_clk", "core_a_clk"; + }; + + cti_cpu0: cti@7820000 { + compatible = "arm,coresight-cti"; + reg = <0x7820000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-cpu0"; + cpu = <&CPU0>; + + clocks = <&clock_gcc clk_qdss_clk>, + <&clock_gcc clk_qdss_a_clk>; + clock-names = "core_clk", "core_a_clk"; + }; + + cti_cpu1: cti@7920000 { + compatible = "arm,coresight-cti"; + reg = <0x7920000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-cpu1"; + cpu = <&CPU1>; + + clocks = <&clock_gcc clk_qdss_clk>, + <&clock_gcc clk_qdss_a_clk>; + clock-names = "core_clk", "core_a_clk"; + }; + + cti_cpu2: cti@7a20000 { + compatible = "arm,coresight-cti"; + reg = <0x7a20000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-cpu2"; + cpu = <&CPU2>; + + clocks = <&clock_gcc clk_qdss_clk>, + <&clock_gcc clk_qdss_a_clk>; + clock-names = "core_clk", "core_a_clk"; + }; + + cti_cpu3: cti@7b20000 { + compatible = "arm,coresight-cti"; + reg = <0x7b20000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-cpu3"; + cpu = <&CPU3>; + + clocks = <&clock_gcc clk_qdss_clk>, + <&clock_gcc clk_qdss_a_clk>; + clock-names = "core_clk", "core_a_clk"; + }; + + cti_cpu4: cti@7c20000 { + compatible = "arm,coresight-cti"; + reg = <0x7c20000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-cpu4"; + cpu = <&CPU4>; + + clocks = <&clock_gcc clk_qdss_clk>, + <&clock_gcc clk_qdss_a_clk>; + clock-names = "core_clk", "core_a_clk"; + }; + + cti_cpu5: cti@7d20000 { + compatible = "arm,coresight-cti"; + reg = <0x7d20000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-cpu5"; + cpu = <&CPU5>; + + clocks = <&clock_gcc clk_qdss_clk>, + <&clock_gcc clk_qdss_a_clk>; + clock-names = "core_clk", "core_a_clk"; + }; + + cti_cpu6: cti@7e20000 { + compatible = "arm,coresight-cti"; + reg = <0x7e20000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-cpu6"; + cpu = <&CPU6>; + + clocks = <&clock_gcc clk_qdss_clk>, + <&clock_gcc clk_qdss_a_clk>; + clock-names = "core_clk", "core_a_clk"; + }; + + cti_cpu7: cti@7f20000 { + compatible = "arm,coresight-cti"; + reg = <0x7f20000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-cpu7"; + cpu = <&CPU7>; + + clocks = <&clock_gcc clk_qdss_clk>, + <&clock_gcc clk_qdss_a_clk>; + clock-names = "core_clk", "core_a_clk"; + }; + + cti_apss: cti@7b80000 { + compatible = "arm,coresight-cti"; + reg = <0x7b80000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-apss"; + + clocks = <&clock_gcc clk_qdss_clk>, + <&clock_gcc clk_qdss_a_clk>; + clock-names = "core_clk", "core_a_clk"; + }; + + cti_apss_dl: cti@7bc1000 { + compatible = "arm,coresight-cti"; + reg = <0x7bc1000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-apss-dl"; + + clocks = <&clock_gcc clk_qdss_clk>, + <&clock_gcc clk_qdss_a_clk>; + clock-names = "core_clk", "core_a_clk"; + }; + + cti_olc: cti@7b91000 { + compatible = "arm,coresight-cti"; + reg = <0x7b91000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-olc"; + + clocks = <&clock_gcc clk_qdss_clk>, + <&clock_gcc clk_qdss_a_clk>; + clock-names = "core_clk", "core_a_clk"; + }; + + funnel_qatb: funnel@6005000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b908>; + + reg = <0x6005000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-qatb"; + + clocks = <&clock_gcc clk_qdss_clk>, + <&clock_gcc clk_qdss_a_clk>; + clock-names = "apb_pclk", "core_a_clk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_qatb_out_funnel_in0: endpoint { + remote-endpoint = + <&funnel_in0_in_funnel_qatb>; + }; + }; + port@1 { + reg = <0>; + funnel_qatb_in_tpda: endpoint { + slave-mode; + remote-endpoint = + <&tpda_out_funnel_qatb>; + }; + }; + port@2 { + reg = <3>; + funnel_qatb_in_funnel_dlet_qatb: endpoint { + slave-mode; + remote-endpoint = + <&funnel_dlet_qatb_out_funnel_qatb>; + }; + }; + }; + }; + + tpda: tpda@6004000 { + compatible = "qcom,coresight-tpda"; + reg = <0x6004000 0x1000>; + reg-names = "tpda-base"; + + coresight-name = "coresight-tpda"; + + qcom,tpda-atid = <65>; + qcom,bc-elem-size = <7 32>, + <9 32>; + qcom,tc-elem-size = <3 32>, + <6 32>, + <9 32>; + qcom,dsb-elem-size = <7 32>, + <9 32>; + qcom,cmb-elem-size = <3 32>, + <4 32>, + <5 32>, + <9 64>; + + clocks = <&clock_gcc clk_qdss_clk>, + <&clock_gcc clk_qdss_a_clk>; + clock-names = "core_clk", "core_a_clk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + tpda_out_funnel_qatb: endpoint { + remote-endpoint = + <&funnel_qatb_in_tpda>; + }; + }; + port@1 { + reg = <3>; + tpda_in_tpdm_vsense: endpoint { + slave-mode; + remote-endpoint = + <&tpdm_vsense_out_tpda>; + }; + }; + port@2 { + reg = <4>; + tpda_in_tpdm_dcc: endpoint { + slave-mode; + remote-endpoint = + <&tpdm_dcc_out_tpda>; + }; + }; + port@3 { + reg = <5>; + tpda_in_tpdm_prng: endpoint { + slave-mode; + remote-endpoint = + <&tpdm_prng_out_tpda>; + }; + }; + port@4 { + reg = <7>; + tpda_in_tpdm_qm: endpoint { + slave-mode; + remote-endpoint = + <&tpdm_qm_out_tpda>; + }; + }; + port@5 { + reg = <9>; + tpda_in_tpdm_pimem: endpoint { + slave-mode; + remote-endpoint = + <&tpdm_pimem_out_tpda>; + }; + }; + }; + }; + + tpdm_vsense: tpdm@7038000 { + compatible = "qcom,coresight-tpdm"; + reg = <0x7038000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-vsense"; + + clocks = <&clock_gcc clk_qdss_clk>, + <&clock_gcc clk_qdss_a_clk>; + clock-names = "core_clk", "core_a_clk"; + + port{ + tpdm_vsense_out_tpda: endpoint { + remote-endpoint = <&tpda_in_tpdm_vsense>; + }; + }; + }; + + tpdm_dcc: tpdm@7054000 { + compatible = "qcom,coresight-tpdm"; + reg = <0x7054000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-dcc"; + + clocks = <&clock_gcc clk_qdss_clk>, + <&clock_gcc clk_qdss_a_clk>; + clock-names = "core_clk", "core_a_clk"; + + port{ + tpdm_dcc_out_tpda: endpoint { + remote-endpoint = <&tpda_in_tpdm_dcc>; + }; + }; + }; + + tpdm_prng: tpdm@704c000 { + compatible = "qcom,coresight-tpdm"; + reg = <0x704c000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-prng"; + + clocks = <&clock_gcc clk_qdss_clk>, + <&clock_gcc clk_qdss_a_clk>; + clock-names = "core_clk", "core_a_clk"; + + port{ + tpdm_prng_out_tpda: endpoint { + remote-endpoint = <&tpda_in_tpdm_prng>; + }; + }; + }; + + tpdm_qm: tpdm@71d0000 { + compatible = "qcom,coresight-tpdm"; + reg = <0x71d0000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-qm"; + + clocks = <&clock_gcc clk_qdss_clk>, + <&clock_gcc clk_qdss_a_clk>; + clock-names = "core_clk", "core_a_clk"; + + qcom,msr-fix-req; + + port{ + tpdm_qm_out_tpda: endpoint { + remote-endpoint = <&tpda_in_tpdm_qm>; + }; + }; + + }; + + tpdm_pimem: tpdm@7050000 { + compatible = "qcom,coresight-tpdm"; + reg = <0x7050000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-pimem"; + + clocks = <&clock_gcc clk_qdss_clk>, + <&clock_gcc clk_qdss_a_clk>; + clock-names = "core_clk", "core_a_clk"; + + qcom,msr-fix-req; + + port{ + tpdm_pimem_out_tpda: endpoint { + remote-endpoint = <&tpda_in_tpdm_pimem>; + }; + }; + + }; + + tpda_apss: tpda@7bc2000 { + compatible = "qcom,coresight-tpda"; + reg = <0x7bc2000 0x1000>; + reg-names = "tpda-base"; + + coresight-name = "coresight-tpda-apss"; + + qcom,tpda-atid = <66>; + qcom,dsb-elem-size = <0 32>; + + clocks = <&clock_gcc clk_qdss_clk>, + <&clock_gcc clk_qdss_a_clk>; + clock-names = "core_clk", "core_a_clk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + tpda_apss_out_funnel_apss_merg: endpoint { + remote-endpoint = + <&funnel_apss_merg_in_tpda_apss>; + }; + }; + port@1 { + reg = <0>; + tpda_apss_in_tpdm_apss: endpoint { + slave-mode; + remote-endpoint = + <&tpdm_apss_out_tpda_apss>; + }; + }; + }; + }; + + tpdm_apss: tpdm@7bc0000 { + compatible = "qcom,coresight-tpdm"; + reg = <0x7bc0000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-apss"; + + clocks = <&clock_gcc clk_qdss_clk>, + <&clock_gcc clk_qdss_a_clk>; + clock-names = "core_clk", "core_a_clk"; + + qcom,msr-fix-req; + + port{ + tpdm_apss_out_tpda_apss: endpoint { + remote-endpoint = <&tpda_apss_in_tpdm_apss>; + }; + }; + }; + + tpda_mss: tpda@7043000 { + compatible = "qcom,coresight-tpda"; + reg = <0x7043000 0x1000>; + reg-names = "tpda-base"; + + coresight-name = "coresight-tpda-mss"; + + qcom,tpda-atid = <67>; + qcom,dsb-elem-size = <0 32>; + qcom,cmb-elem-size = <0 32>; + + clocks = <&clock_gcc clk_qdss_clk>, + <&clock_gcc clk_qdss_a_clk>; + clock-names = "core_clk", "core_a_clk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + tpda_mss_out_funnel_in1: endpoint { + remote-endpoint = + <&funnel_in1_in_tpda_mss>; + }; + }; + port@1 { + reg = <0>; + tpda_mss_in_tpdm_mss: endpoint { + slave-mode; + remote-endpoint = + <&tpdm_mss_out_tpda_mss>; + }; + }; + }; + }; + + tpdm_mss: tpdm@7042000 { + compatible = "qcom,coresight-tpdm"; + reg = <0x7042000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-mss"; + + clocks = <&clock_gcc clk_qdss_clk>, + <&clock_gcc clk_qdss_a_clk>; + clock-names = "core_clk", "core_a_clk"; + + qcom,msr-fix-req; + + port{ + tpdm_mss_out_tpda_mss: endpoint { + remote-endpoint = <&tpda_mss_in_tpdm_mss>; + }; + }; + }; + + tpda_nav: tpda@7191000 { + compatible = "qcom,coresight-tpda"; + reg = <0x7191000 0x1000>; + reg-names = "tpda-base"; + + coresight-name = "coresight-tpda-nav"; + + qcom,tpda-atid = <68>; + qcom,cmb-elem-size = <0 32>; + + clocks = <&clock_gcc clk_qdss_clk>, + <&clock_gcc clk_qdss_a_clk>; + clock-names = "core_clk", "core_a_clk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + tpda_nav_out_funnel_in1: endpoint { + remote-endpoint = + <&funnel_in1_in_tpda_nav>; + }; + }; + port@1 { + reg = <0>; + tpda_nav_in_tpdm_nav: endpoint { + slave-mode; + remote-endpoint = + <&tpdm_nav_out_tpda_nav>; + }; + }; + }; + }; + + tpdm_nav: tpdm@7190000 { + compatible = "qcom,coresight-tpdm"; + reg = <0x7190000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-nav"; + + clocks = <&clock_gcc clk_qdss_clk>, + <&clock_gcc clk_qdss_a_clk>; + clock-names = "core_clk", "core_a_clk"; + + port{ + tpdm_nav_out_tpda_nav: endpoint { + remote-endpoint = <&tpda_nav_in_tpdm_nav>; + }; + }; + }; + + tpda_olc: tpda@7b92000 { + compatible = "qcom,coresight-tpda"; + reg = <0x7b92000 0x1000>; + reg-names = "tpda-base"; + + coresight-name = "coresight-tpda-olc"; + + qcom,tpda-atid = <69>; + qcom,cmb-elem-size = <0 64>; + + clocks = <&clock_gcc clk_qdss_clk>, + <&clock_gcc clk_qdss_a_clk>; + clock-names = "core_clk", "core_a_clk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + tpda_olc_out_funnel_apss_merg: endpoint { + remote-endpoint = + <&funnel_apss_merg_in_tpda_olc>; + }; + }; + port@1 { + reg = <0>; + tpda_olc_in_tpdm_olc: endpoint { + slave-mode; + remote-endpoint = + <&tpdm_olc_out_tpda_olc>; + }; + }; + }; + }; + + tpdm_olc: tpdm@7b90000 { + compatible = "qcom,coresight-tpdm"; + reg = <0x7b90000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-olc"; + + clocks = <&clock_gcc clk_qdss_clk>, + <&clock_gcc clk_qdss_a_clk>; + clock-names = "core_clk", "core_a_clk"; + + port{ + tpdm_olc_out_tpda_olc: endpoint { + remote-endpoint = <&tpda_olc_in_tpdm_olc>; + }; + }; + }; + + funnel_spss: funnel@7083000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b908>; + + reg = <0x7083000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-spss"; + + clocks = <&clock_gcc clk_qdss_clk>, + <&clock_gcc clk_qdss_a_clk>; + clock-names = "apb_pclk", "core_a_clk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_spss_out_funnel_in0: endpoint { + remote-endpoint = + <&funnel_in0_in_funnel_spss>; + }; + }; + port@1 { + reg = <0>; + funnel_spss_in_tpda_spss: endpoint { + slave-mode; + remote-endpoint = + <&tpda_spss_out_funnel_spss>; + }; + }; + port@2 { + reg = <1>; + funnel_spss_in_spss_etm0: endpoint { + slave-mode; + remote-endpoint = + <&spss_etm0_out_funnel_spss>; + }; + }; + }; + }; + + tpda_spss: tpda@7082000 { + compatible = "qcom,coresight-tpda"; + reg = <0x7082000 0x1000>; + reg-names = "tpda-base"; + + coresight-name = "coresight-tpda-spss"; + + qcom,tpda-atid = <70>; + qcom,dsb-elem-size = <0 32>; + + clocks = <&clock_gcc clk_qdss_clk>, + <&clock_gcc clk_qdss_a_clk>; + clock-names = "core_clk", "core_a_clk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + tpda_spss_out_funnel_spss: endpoint { + remote-endpoint = + <&funnel_spss_in_tpda_spss>; + }; + }; + port@1 { + reg = <0>; + tpda_spss_in_tpdm_spss: endpoint { + slave-mode; + remote-endpoint = + <&tpdm_spss_out_tpda_spss>; + }; + }; + }; + }; + + tpdm_spss: tpdm@7080000 { + compatible = "qcom,coresight-tpdm"; + reg = <0x7080000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-spss"; + + clocks = <&clock_gcc clk_qdss_clk>, + <&clock_gcc clk_qdss_a_clk>; + clock-names = "core_clk", "core_a_clk"; + + qcom,msr-fix-req; + + port{ + tpdm_spss_out_tpda_spss: endpoint { + remote-endpoint = <&tpda_spss_in_tpdm_spss>; + }; + }; + }; + + hwevent: hwevent@158000 { + compatible = "qcom,coresight-hwevent"; + reg = <0x158000 0x80>, + <0x17091000 0x80>, + <0x1730200c 0x4>, + <0xc90137c 0x4>, + <0xc828018 0x80>, + <0x1c00058 0x80>, + <0x5e02038 0x4>, + <0x5e02028 0x10>, + <0x1fcb360 0x80>, + <0x1fcb760 0x80>, + <0x1fcbf60 0x80>, + <0xa8f8860 0x4>, + <0x500c260 0x4>, + <0x500d040 0x4>, + <0x1da6400 0x80>; + reg-names = "gcc-ctrl", "lpass-stm", "lpass-qdsp", "mdss-mdp", + "mdss-misc", "pcie0-hwev", "ssc-en", "ssc-hwev", + "tcsr-qdss", "tcsr-mss0", "tcsr-mss1", "usb-ctrl", + "vbif-stm", "vbif-stm-en", "ufs-mux"; + + coresight-name = "coresight-hwevent"; + + clocks = <&clock_gcc clk_qdss_clk>, + <&clock_gcc clk_qdss_a_clk>, + <&clock_mmss clk_mmss_misc_ahb_clk>; + clock-names = "core_clk", "core_a_clk", "core_mmss_clk"; + + qcom,hwevent-clks = "core_mmss_clk"; + }; + + csr: csr@6001000 { + compatible = "qcom,coresight-csr"; + reg = <0x6001000 0x1000>; + reg-names = "csr-base"; + + coresight-name = "coresight-csr"; + + qcom,blk-size = <1>; + }; + + modem_etm0 { + compatible = "qcom,coresight-remote-etm"; + + coresight-name = "coresight-modem-etm0"; + qcom,inst-id = <2>; + + port{ + modem_etm0_out_funnel_in1: endpoint { + remote-endpoint = <&funnel_in1_in_modem_etm0>; + }; + }; + }; + + audio_etm0 { + compatible = "qcom,coresight-remote-etm"; + + coresight-name = "coresight-audio-etm0"; + qcom,inst-id = <5>; + + port{ + audio_etm0_out_funnel_in1: endpoint { + remote-endpoint = <&funnel_in1_in_audio_etm0>; + }; + }; + }; + + rpm_etm0 { + compatible = "qcom,coresight-remote-etm"; + + coresight-name = "coresight-rpm-etm0"; + qcom,inst-id = <4>; + + port{ + rpm_etm0_out_funnel_in0: endpoint { + remote-endpoint = <&funnel_in0_in_rpm_etm0>; + }; + }; + }; + + funnel_dlet_qatb: funnel@7225000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b908>; + + reg = <0x7225000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-dlet-qatb"; + + clocks = <&clock_gcc clk_qdss_clk>, + <&clock_gcc clk_qdss_a_clk>; + clock-names = "apb_pclk", "core_a_clk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_dlet_qatb_out_funnel_qatb: endpoint { + remote-endpoint = + <&funnel_qatb_in_funnel_dlet_qatb>; + }; + }; + port@1 { + reg = <1>; + funnel_dlet_qatb_in_tpdm_wcss: endpoint { + slave-mode; + remote-endpoint = + <&tpdm_wcss_out_funnel_dlet_qatb>; + }; + }; + }; + }; + + dummy-tpdm-wcss { + compatible = "qcom,coresight-dummy"; + + coresight-name = "coresight-tpdm-wcss"; + + port{ + tpdm_wcss_out_funnel_dlet_qatb: endpoint { + remote-endpoint = + <&funnel_dlet_qatb_in_tpdm_wcss>; + }; + }; + }; + + dummy-spss-etm0 { + compatible = "qcom,coresight-dummy"; + + coresight-name = "coresight-spss-etm0"; + + port{ + spss_etm0_out_funnel_spss: endpoint { + remote-endpoint = + <&funnel_spss_in_spss_etm0>; + }; + }; + }; +}; diff -Nruw linux-4.4.115-fbx/arch/arm/boot/dts/qcom./msm8998.dtsi linux-4.4.115-fbx/arch/arm/boot/dts/qcom/msm8998.dtsi --- linux-4.4.115-fbx/arch/arm/boot/dts/qcom./msm8998.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ linux-4.4.115-fbx/arch/arm/boot/dts/qcom/msm8998.dtsi 2019-10-29 09:26:22.921196113 +0100 @@ -0,0 +1,3351 @@ +/* Copyright (c) 2015-2017, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "skeleton64.dtsi" +#include +#include +#include + +/ { + model = "Qualcomm Technologies, Inc. MSM 8998"; + compatible = "qcom,msm8998"; + qcom,msm-id = <292 0x0>; + interrupt-parent = <&intc>; + + aliases { + serial0 = &uartblsp2dm1; + pci-domain0 = &pcie0; + sdhc2 = &sdhc_2; /* SDC2 SD card slot */ + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + chosen { + stdout-path = "serial0"; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + CPU0: cpu@0 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x0>; + qcom,limits-info = <&mitigation_profile0>; + qcom,lmh-dcvs = <&lmh_dcvs0>; + enable-method = "psci"; + efficiency = <1024>; + next-level-cache = <&L2_0>; + qcom,ea = <&ea0>; + L2_0: l2-cache { + compatible = "arm,arch-cache"; + cache-level = <2>; + qcom,dump-size = <0x0>; /* A53 L2 dump not supported */ + }; + L1_I_0: l1-icache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x9040>; + }; + L1_D_0: l1-dcache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x9040>; + }; + L1_TLB_0: l1-tlb { + qcom,dump-size = <0x2000>; + }; + }; + + CPU1: cpu@1 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x1>; + qcom,limits-info = <&mitigation_profile1>; + qcom,lmh-dcvs = <&lmh_dcvs0>; + enable-method = "psci"; + efficiency = <1024>; + next-level-cache = <&L2_0>; + qcom,ea = <&ea1>; + L1_I_1: l1-icache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x9040>; + }; + L1_D_1: l1-dcache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x9040>; + }; + L1_TLB_1: l1-tlb { + qcom,dump-size = <0x2000>; + }; + }; + + CPU2: cpu@2 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x2>; + qcom,limits-info = <&mitigation_profile2>; + qcom,lmh-dcvs = <&lmh_dcvs0>; + enable-method = "psci"; + efficiency = <1024>; + next-level-cache = <&L2_0>; + qcom,ea = <&ea2>; + L1_I_2: l1-icache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x9040>; + }; + L1_D_2: l1-dcache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x9040>; + }; + L1_TLB_2: l1-tlb { + qcom,dump-size = <0x2000>; + }; + }; + + CPU3: cpu@3 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x3>; + qcom,limits-info = <&mitigation_profile3>; + qcom,lmh-dcvs = <&lmh_dcvs0>; + enable-method = "psci"; + efficiency = <1024>; + next-level-cache = <&L2_0>; + qcom,ea = <&ea3>; + L1_I_3: l1-icache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x9040>; + }; + L1_D_3: l1-dcache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x9040>; + }; + L1_TLB_3: l1-tlb { + qcom,dump-size = <0x2000>; + }; + }; + + CPU4: cpu@100 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x100>; + qcom,limits-info = <&mitigation_profile4>; + qcom,lmh-dcvs = <&lmh_dcvs1>; + enable-method = "psci"; + efficiency = <1536>; + next-level-cache = <&L2_1>; + qcom,ea = <&ea4>; + L2_1: l2-cache { + compatible = "arm,arch-cache"; + cache-level = <2>; + }; + L1_I_100: l1-icache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x12000>; + }; + L1_D_100: l1-dcache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x12000>; + }; + L1_TLB_100: l1-tlb { + qcom,dump-size = <0x4800>; + }; + }; + + CPU5: cpu@101 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x101>; + qcom,limits-info = <&mitigation_profile5>; + qcom,lmh-dcvs = <&lmh_dcvs1>; + enable-method = "psci"; + efficiency = <1536>; + next-level-cache = <&L2_1>; + qcom,ea = <&ea5>; + L1_I_101: l1-icache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x12000>; + }; + L1_D_101: l1-dcache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x12000>; + }; + L1_TLB_101: l1-tlb { + qcom,dump-size = <0x4800>; + }; + }; + + CPU6: cpu@102 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x102>; + qcom,limits-info = <&mitigation_profile6>; + qcom,lmh-dcvs = <&lmh_dcvs1>; + enable-method = "psci"; + efficiency = <1536>; + next-level-cache = <&L2_1>; + qcom,ea = <&ea6>; + L1_I_102: l1-icache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x12000>; + }; + L1_D_102: l1-dcache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x12000>; + }; + L1_TLB_102: l1-tlb { + qcom,dump-size = <0x4800>; + }; + }; + + CPU7: cpu@103 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x103>; + qcom,limits-info = <&mitigation_profile7>; + qcom,lmh-dcvs = <&lmh_dcvs1>; + enable-method = "psci"; + efficiency = <1536>; + next-level-cache = <&L2_1>; + qcom,ea = <&ea7>; + L1_I_103: l1-icache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x12000>; + }; + L1_D_103: l1-dcache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x12000>; + }; + L1_TLB_103: l1-tlb { + qcom,dump-size = <0x4800>; + }; + }; + + cpu-map { + cluster0 { + core0 { + cpu = <&CPU0>; + }; + + core1 { + cpu = <&CPU1>; + }; + + core2 { + cpu = <&CPU2>; + }; + + core3 { + cpu = <&CPU3>; + }; + }; + + cluster1 { + core0 { + cpu = <&CPU4>; + }; + + core1 { + cpu = <&CPU5>; + }; + + core2 { + cpu = <&CPU6>; + }; + + core3 { + cpu = <&CPU7>; + }; + }; + }; + }; + + soc: soc { }; + + vendor: vendor { + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0 0xffffffff>; + compatible = "simple-bus"; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + removed_regions: removed_regions@85800000 { + compatible = "removed-dma-pool"; + no-map; + reg = <0 0x85800000 0 0x3700000>; + }; + + pil_slpi_mem: pil_slpi_region@94400000 { + compatible = "removed-dma-pool"; + no-map; + reg = <0 0x94400000 0 0xf00000>; + }; + + pil_ipa_gpu_mem: pil_ipa_gpu_region@94300000 { + compatible = "removed-dma-pool"; + no-map; + reg = <0 0x94300000 0 0x100000>; + }; + + pil_mba_mem: pil_mba_region@94100000 { + compatible = "removed-dma-pool"; + no-map; + reg = <0 0x94100000 0 0x200000>; + }; + + pil_video_mem: pil_video_region@93c00000 { + compatible = "removed-dma-pool"; + no-map; + reg = <0 0x93c00000 0 0x500000>; + }; + + modem_mem: modem_region@8cc00000 { + compatible = "removed-dma-pool"; + no-map; + reg = <0 0x8cc00000 0 0x7000000>; + }; + + pil_adsp_mem: pil_adsp_region@0x8b200000 { + compatible = "removed-dma-pool"; + no-map; + reg = <0 0x8b200000 0 0x1a00000>; + }; + + spss_mem: spss_region@8ab00000 { /* for SPSS-PIL */ + compatible = "removed-dma-pool"; + no-map; + reg = <0 0x8ab00000 0 0x700000>; + }; + + adsp_mem: adsp_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0 0x00000000 0 0xffffffff>; + reusable; + alignment = <0 0x400000>; + size = <0 0x800000>; + }; + + qseecom_mem: qseecom_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0 0x00000000 0 0xffffffff>; + reusable; + alignment = <0 0x400000>; + size = <0 0x1400000>; + }; + + sp_mem: sp_region { /* SPSS-HLOS ION shared mem */ + compatible = "shared-dma-pool"; + alloc-ranges = <0 0x00000000 0 0xffffffff>; /* 32-bit */ + reusable; + alignment = <0 0x100000>; + size = <0 0x800000>; + }; + + secure_display_memory: secure_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0 0x00000000 0 0xffffffff>; + reusable; + alignment = <0 0x200000>; + size = <0 0x8000000>; + }; + + /* global autoconfigured region for contiguous allocations */ + linux,cma { + compatible = "shared-dma-pool"; + alloc-ranges = <0 0x00000000 0 0xffffffff>; + reusable; + alignment = <0 0x400000>; + size = <0 0x2000000>; + linux,cma-default; + }; + + cont_splash_mem: splash_region@9d600000 { + reg = <0x0 0x9d600000 0x0 0x02400000>; + label = "cont_splash_mem"; + }; + }; +}; + +#include "msm8998-smp2p.dtsi" +#include "msm-gdsc-8998.dtsi" + +&soc { + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0 0xffffffff>; + compatible = "simple-bus"; + + intc: interrupt-controller@17a00000 { + compatible = "arm,gic-v3"; + reg = <0x17a00000 0x10000>, /* GICD */ + <0x17b00000 0x100000>; /* GICR * 8 */ + #interrupt-cells = <3>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + interrupt-controller; + #redistributor-regions = <1>; + redistributor-stride = <0x0 0x20000>; + interrupts = <1 9 4>; + + gic-its@0x17a20000{ + compatible = "arm,gic-v3-its"; + msi-contoller; + reg = <0x17a20000 0x20000>; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <1 1 0xf08>, + <1 2 0xf08>, + <1 3 0xf08>, + <1 0 0xf08>; + clock-frequency = <19200000>; + }; + + restart@10ac000 { + compatible = "qcom,pshold"; + reg = <0x10ac000 0x4>, + <0x1fd3000 0x4>; + reg-names = "pshold-base", "tcsr-boot-misc-detect"; + }; + + spmi_bus: qcom,spmi@800f000 { + compatible = "qcom,spmi-pmic-arb"; + reg = <0x800f000 0x1000>, + <0x8400000 0x1000000>, + <0x9400000 0x1000000>, + <0xa400000 0x220000>, + <0x800a000 0x3000>; + reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; + interrupt-names = "periph_irq"; + interrupts = ; + qcom,ee = <0>; + qcom,channel = <0>; + qcom,reserved-chan = <511>; + #address-cells = <2>; + #size-cells = <0>; + interrupt-controller; + #interrupt-cells = <4>; + cell-index = <0>; + }; + + qcom,sps { + compatible = "qcom,msm_sps_4k"; + qcom,device-type = <3>; + qcom,pipe-attr-ee; + }; + + uartblsp1dm1: serial@0c170000 { + compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; + reg = <0xc170000 0x1000>; + interrupts = <0 108 0>; + status = "disabled"; + clocks = <&clock_gcc clk_gcc_blsp1_uart2_apps_clk>, + <&clock_gcc clk_gcc_blsp1_ahb_clk>; + clock-names = "core", "iface"; + }; + + uartblsp2dm1: serial@0c1b0000 { + compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; + reg = <0xc1b0000 0x1000>; + interrupts = <0 114 0>; + status = "disabled"; + clocks = <&clock_gcc clk_gcc_blsp2_uart2_apps_clk>, + <&clock_gcc clk_gcc_blsp2_ahb_clk>; + clock-names = "core", "iface"; + }; + + slim_aud: slim@171c0000 { + cell-index = <1>; + compatible = "qcom,slim-ngd"; + reg = <0x171c0000 0x2C000>, + <0x17184000 0x32000>; + reg-names = "slimbus_physical", "slimbus_bam_physical"; + interrupts = <0 163 0>, <0 164 0>; + interrupt-names = "slimbus_irq", "slimbus_bam_irq"; + qcom,apps-ch-pipes = <0x00001f80>; + qcom,ea-pc = <0x210>; + }; + + slim_qca: slim@17240000 { + status = "ok"; + cell-index = <3>; + compatible = "qcom,slim-ngd"; + reg = <0x17240000 0x2C000>, + <0x17204000 0x26000>; + reg-names = "slimbus_physical", "slimbus_bam_physical"; + interrupts = <0 291 0>, <0 292 0>; + interrupt-names = "slimbus_irq", "slimbus_bam_irq"; + + /* Slimbus Slave DT for WCN3990 */ + btfmslim_codec: wcn3990 { + compatible = "qcom,btfmslim_slave"; + elemental-addr = [00 01 20 02 17 02]; + qcom,btfm-slim-ifd = "btfmslim_slave_ifd"; + qcom,btfm-slim-ifd-elemental-addr = [00 00 20 02 17 02]; + }; + }; + + timer@17920000 { + #address-cells = <1>; + #size-cells = <1>; + ranges; + compatible = "arm,armv7-timer-mem"; + reg = <0x17920000 0x1000>; + clock-frequency = <19200000>; + + frame@17921000 { + frame-number = <0>; + interrupts = <0 8 0x4>, + <0 7 0x4>; + reg = <0x17921000 0x1000>, + <0x17922000 0x1000>; + }; + + frame@17923000 { + frame-number = <1>; + interrupts = <0 9 0x4>; + reg = <0x17923000 0x1000>; + status = "disabled"; + }; + + frame@17924000 { + frame-number = <2>; + interrupts = <0 10 0x4>; + reg = <0x17924000 0x1000>; + status = "disabled"; + }; + + frame@17925000 { + frame-number = <3>; + interrupts = <0 11 0x4>; + reg = <0x17925000 0x1000>; + status = "disabled"; + }; + + frame@17926000 { + frame-number = <4>; + interrupts = <0 12 0x4>; + reg = <0x17926000 0x1000>; + status = "disabled"; + }; + + frame@17927000 { + frame-number = <5>; + interrupts = <0 13 0x4>; + reg = <0x17927000 0x1000>; + status = "disabled"; + }; + + frame@17928000 { + frame-number = <6>; + interrupts = <0 14 0x4>; + reg = <0x17928000 0x1000>; + status = "disabled"; + }; + }; + + cpubw: qcom,cpubw { + compatible = "qcom,devbw"; + governor = "performance"; + qcom,src-dst-ports = <1 512>; + qcom,active-only; + qcom,bw-tbl = + < 762 /* 100 MHz */ >, + < 1144 /* 150 MHz */ >, + < 1525 /* 200 MHz */ >, + < 2288 /* 300 MHz */ >, + < 3143 /* 412 MHz */ >, + < 4173 /* 547 MHz */ >, + < 5195 /* 681 MHz */ >, + < 5859 /* 768 MHz */ >, + < 7759 /* 1017 MHz */ >, + < 9887 /* 1296 MHz */ >, + < 11863 /* 1555 MHz */ >, + < 13763 /* 1804 MHz */ >; + }; + + bwmon: qcom,cpu-bwmon { + compatible = "qcom,bimc-bwmon3"; + reg = <0x01008000 0x300>, <0x01001000 0x200>; + reg-names = "base", "global_base"; + interrupts = <0 183 4>; + qcom,mport = <0>; + qcom,target-dev = <&cpubw>; + }; + + mincpubw: qcom,mincpubw { + compatible = "qcom,devbw"; + governor = "powersave"; + qcom,src-dst-ports = <1 512>; + qcom,active-only; + qcom,bw-tbl = + < 762 /* 100 MHz */ >, + < 1144 /* 150 MHz */ >, + < 1525 /* 200 MHz */ >, + < 2288 /* 300 MHz */ >, + < 3143 /* 412 MHz */ >, + < 4173 /* 547 MHz */ >, + < 5195 /* 681 MHz */ >, + < 5859 /* 768 MHz */ >, + < 7759 /* 1017 MHz */ >, + < 9887 /* 1296 MHz */ >, + < 11863 /* 1555 MHz */ >, + < 13763 /* 1804 MHz */ >; + }; + + memlat_cpu0: qcom,memlat-cpu0 { + compatible = "qcom,devbw"; + governor = "powersave"; + qcom,src-dst-ports = <1 512>; + qcom,active-only; + qcom,bw-tbl = + < 762 /* 100 MHz */ >, + < 1144 /* 150 MHz */ >, + < 1525 /* 200 MHz */ >, + < 2288 /* 300 MHz */ >, + < 3143 /* 412 MHz */ >, + < 4173 /* 547 MHz */ >, + < 5195 /* 681 MHz */ >, + < 5859 /* 768 MHz */ >, + < 7759 /* 1017 MHz */ >, + < 9887 /* 1296 MHz */ >, + < 11863 /* 1555 MHz */ >, + < 13763 /* 1804 MHz */ >; + }; + + memlat_cpu4: qcom,memlat-cpu4 { + compatible = "qcom,devbw"; + governor = "powersave"; + qcom,src-dst-ports = <1 512>; + qcom,active-only; + status = "ok"; + qcom,bw-tbl = + < 762 /* 100 MHz */ >, + < 1144 /* 150 MHz */ >, + < 1525 /* 200 MHz */ >, + < 2288 /* 300 MHz */ >, + < 3143 /* 412 MHz */ >, + < 4173 /* 547 MHz */ >, + < 5195 /* 681 MHz */ >, + < 5859 /* 768 MHz */ >, + < 7759 /* 1017 MHz */ >, + < 9887 /* 1296 MHz */ >, + < 11863 /* 1555 MHz */ >, + < 13763 /* 1804 MHz */ >; + }; + + devfreq_memlat_0: qcom,arm-memlat-mon-0 { + compatible = "qcom,arm-memlat-mon"; + qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3>; + qcom,target-dev = <&memlat_cpu0>; + qcom,core-dev-table = + < 300000 1525 >, + < 499200 3143 >, + < 1113600 4173 >, + < 1881600 5859 >; + }; + + devfreq_memlat_4: qcom,arm-memlat-mon-4 { + compatible = "qcom,arm-memlat-mon"; + qcom,cpulist = <&CPU4 &CPU5 &CPU6 &CPU7>; + qcom,target-dev = <&memlat_cpu4>; + qcom,core-dev-table = + < 300000 1525 >, + < 480000 3143 >, + < 900000 4173 >, + < 1017000 7759 >, + < 1296000 9887 >, + < 1555000 11863 >, + < 1804000 13763 >; + }; + + devfreq_cpufreq: devfreq-cpufreq { + mincpubw-cpufreq { + target-dev = <&mincpubw>; + cpu-to-dev-map-0 = + < 1881600 1525 >; + cpu-to-dev-map-4 = + < 2016000 1525 >, + < 2092800 5195 >; + }; + }; + + msm_cpufreq: qcom,msm-cpufreq { + compatible = "qcom,msm-cpufreq"; + clock-names = "cpu0_clk", "cpu1_clk", "cpu2_clk", + "cpu3_clk", "cpu4_clk", "cpu5_clk", + "cpu6_clk", "cpu7_clk"; + clocks = <&clock_cpu clk_pwrcl_clk>, + <&clock_cpu clk_pwrcl_clk>, + <&clock_cpu clk_pwrcl_clk>, + <&clock_cpu clk_pwrcl_clk>, + <&clock_cpu clk_perfcl_clk>, + <&clock_cpu clk_perfcl_clk>, + <&clock_cpu clk_perfcl_clk>, + <&clock_cpu clk_perfcl_clk>; + + qcom,governor-per-policy; + + qcom,cpufreq-table-0 = + < 300000 >, + < 345600 >, + < 422400 >, + < 499200 >, + < 576000 >, + < 633600 >, + < 710400 >, + < 806400 >, + < 883200 >, + < 960000 >, + < 1036800 >, + < 1113600 >, + < 1190400 >, + < 1248000 >, + < 1324800 >, + < 1401600 >, + < 1478400 >, + < 1574400 >, + < 1651200 >, + < 1728000 >, + < 1804800 >, + < 1881600 >; + + qcom,cpufreq-table-4 = + < 300000 >, + < 345600 >, + < 422400 >, + < 480000 >, + < 556800 >, + < 633600 >, + < 710400 >, + < 787200 >, + < 844800 >, + < 902400 >, + < 979200 >, + < 1056000 >, + < 1171200 >, + < 1248000 >, + < 1324800 >, + < 1401600 >, + < 1478400 >, + < 1536000 >, + < 1632000 >, + < 1708800 >, + < 1785600 >, + < 1862400 >, + < 1939200 >, + < 2016000 >, + < 2092800 >; + }; + + arm64-cpu-erp { + compatible = "arm,arm64-cpu-erp"; + interrupts = <0 43 4>, + <0 44 4>, + <0 41 4>, + <0 42 4>; + + interrupt-names = "pri-dbe-irq", + "sec-dbe-irq", + "pri-ext-irq", + "sec-ext-irq"; + + poll-delay-ms = <5000>; + }; + + clock_gcc: qcom,gcc@100000 { + compatible = "qcom,gcc-8998"; + reg = <0x100000 0xb0000>; + reg-names = "cc_base"; + vdd_dig-supply = <&pm8998_s1_level>; + vdd_dig_ao-supply = <&pm8998_s1_level_ao>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + clock_mmss: qcom,mmsscc@c8c0000 { + compatible = "qcom,mmsscc-8998"; + reg = <0xc8c0000 0x40000>; + reg-names = "cc_base"; + vdd_dig-supply = <&pm8998_s1_level>; + vdd_mmsscc_mx-supply = <&pm8998_s9_level>; + clock-names = "xo", "gpll0", "gpll0_div", + "pclk0_src", "pclk1_src", + "byte0_src", "byte1_src", + "dp_link_src", "dp_vco_div", + "extpclk_src"; + clocks = <&clock_gcc clk_cxo_clk_src>, + <&clock_gcc clk_gcc_mmss_gpll0_clk>, + <&clock_gcc clk_gcc_mmss_gpll0_div_clk>, + <&mdss_dsi0_pll clk_dsi0pll_pclk_mux>, + <&mdss_dsi1_pll clk_dsi1pll_pclk_mux>, + <&mdss_dsi0_pll clk_dsi0pll_byteclk_mux>, + <&mdss_dsi1_pll clk_dsi1pll_byteclk_mux>, + <&mdss_dp_pll clk_dp_link_2x_clk_divsel_five>, + <&mdss_dp_pll clk_vco_divided_clk_src_mux>, + <&mdss_hdmi_pll clk_hdmi_vco_clk>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + clock_gpu: qcom,gpucc@5065000 { + compatible = "qcom,gpucc-8998"; + reg = <0x5065000 0x9000>; + reg-names = "cc_base"; + vdd_dig-supply = <&pm8998_s1_level>; + clock-names = "xo_ao", "gpll0"; + clocks = <&clock_gcc clk_cxo_clk_src_ao>, + <&clock_gcc clk_gcc_gpu_gpll0_clk>; + #clock-cells = <1>; + }; + + clock_gfx: qcom,gfxcc@5065000 { + compatible = "qcom,gfxcc-8998"; + reg = <0x5065000 0x9000>; + reg-names = "cc_base"; + vdd_gpucc-supply = <&gfx_vreg>; + vdd_mx-supply = <&pm8998_s9_level>; + vdd_gpu_mx-supply = <&pm8998_s9_level>; + qcom,gfx3d_clk_src-opp-handle = <&msm_gpu>; + qcom,gfxfreq-speedbin0 = + < 0 0 0 >, + < 171000000 1 RPM_SMD_REGULATOR_LEVEL_SVS >, + < 251000000 2 RPM_SMD_REGULATOR_LEVEL_SVS >, + < 332000000 3 RPM_SMD_REGULATOR_LEVEL_SVS >, + < 403000000 4 RPM_SMD_REGULATOR_LEVEL_SVS >, + < 504000000 5 RPM_SMD_REGULATOR_LEVEL_NOM >, + < 650000000 6 RPM_SMD_REGULATOR_LEVEL_TURBO >; + qcom,gfxfreq-mx-speedbin0 = + < 0 0 >, + < 171000000 RPM_SMD_REGULATOR_LEVEL_SVS >, + < 251000000 RPM_SMD_REGULATOR_LEVEL_SVS >, + < 332000000 RPM_SMD_REGULATOR_LEVEL_SVS >, + < 403000000 RPM_SMD_REGULATOR_LEVEL_SVS >, + < 504000000 RPM_SMD_REGULATOR_LEVEL_NOM >, + < 650000000 RPM_SMD_REGULATOR_LEVEL_TURBO >; + #clock-cells = <1>; + }; + + clock_cpu: qcom,cpu-clock-8998@179c0000 { + compatible = "qcom,cpu-clock-osm-msm8998-v1"; + reg = <0x179c0000 0x4000>, + <0x17916000 0x1000>, + <0x17816000 0x1000>, + <0x179d1000 0x1000>, + <0x00784130 0x8>, + <0x1791101c 0x8>; + reg-names = "osm", "pwrcl_pll", "perfcl_pll", + "apcs_common", "perfcl_efuse", "debug"; + + vdd-pwrcl-supply = <&apc0_pwrcl_vreg>; + vdd-perfcl-supply = <&apc1_perfcl_vreg>; + + interrupts = , + ; + interrupt-names = "pwrcl-irq", "perfcl-irq"; + + qcom,pwrcl-speedbin0-v0 = + < 300000000 0x0004000f 0x01200020 0x1 1 >, + < 345600000 0x05040012 0x02200020 0x1 2 >, + < 422400000 0x05040016 0x02200020 0x1 3 >, + < 499200000 0x0504001a 0x02200020 0x1 4 >, + < 576000000 0x0504001e 0x03200020 0x1 5 >, + < 633600000 0x05040021 0x03200020 0x1 6 >, + < 710400000 0x05040025 0x03200020 0x1 7 >, + < 806400000 0x0504002a 0x04200020 0x1 8 >, + < 883200000 0x0404002e 0x04250025 0x1 9 >, + < 960000000 0x04040032 0x05280028 0x1 10 >, + < 1036800000 0x04040036 0x052b002b 0x2 11 >, + < 1113600000 0x0404003a 0x052e002e 0x2 12 >, + < 1190400000 0x0404003e 0x06320032 0x2 13 >, + < 1248000000 0x04040041 0x06340034 0x2 14 >, + < 1324800000 0x04040045 0x06370037 0x2 15 >, + < 1401600000 0x04040049 0x073a003a 0x2 16 >, + < 1478400000 0x0404004d 0x073e003e 0x2 17 >, + < 1574400000 0x04040052 0x08420042 0x2 18 >, + < 1651200000 0x04040056 0x08450045 0x2 19 >, + < 1728000000 0x0404005a 0x08480048 0x2 20 >, + < 1804800000 0x0404005e 0x094b004b 0x3 21 >, + < 1881600000 0x04040062 0x094e004e 0x3 22 >; + + qcom,perfcl-speedbin0-v0 = + < 300000000 0x0004000f 0x01200020 0x1 1 >, + < 345600000 0x05040012 0x02200020 0x1 2 >, + < 422400000 0x05040016 0x02200020 0x1 3 >, + < 480000000 0x05040019 0x02200020 0x1 4 >, + < 556800000 0x0504001d 0x03200020 0x1 5 >, + < 633600000 0x05040021 0x03200020 0x1 6 >, + < 710400000 0x05040025 0x03200020 0x1 7 >, + < 787200000 0x05040029 0x04200020 0x1 8 >, + < 844800000 0x0404002c 0x04230023 0x1 9 >, + < 902400000 0x0404002f 0x04260026 0x1 10 >, + < 979200000 0x04040033 0x05290029 0x1 11 >, + < 1056000000 0x04040037 0x052c002c 0x1 12 >, + < 1171200000 0x0404003d 0x06310031 0x2 13 >, + < 1248000000 0x04040041 0x06340034 0x2 14 >, + < 1324800000 0x04040045 0x06370037 0x2 15 >, + < 1401600000 0x04040049 0x073a003a 0x2 16 >, + < 1478400000 0x0404004d 0x073e003e 0x2 17 >, + < 1536000000 0x04040050 0x07400040 0x2 18 >, + < 1632000000 0x04040055 0x08440044 0x2 19 >, + < 1708800000 0x04040059 0x08470047 0x2 20 >, + < 1785600000 0x0404005d 0x094a004a 0x2 21 >, + < 1862400000 0x04040061 0x094e004e 0x2 22 >, + < 1939200000 0x04040065 0x09510051 0x3 23 >, + < 2016000000 0x04040069 0x0a540054 0x3 24 >, + < 2092800000 0x0404006d 0x0a570057 0x3 25 >; + + qcom,up-timer = + <1000 1000>; + qcom,down-timer = + <1000 1000>; + qcom,pc-override-index = + <0 0>; + qcom,set-ret-inactive; + qcom,enable-llm-freq-vote; + qcom,llm-freq-up-timer = + <327675 327675>; + qcom,llm-freq-down-timer = + <327675 327675>; + qcom,enable-llm-volt-vote; + qcom,llm-volt-up-timer = + <327675 327675>; + qcom,llm-volt-down-timer = + <327675 327675>; + qcom,cc-reads = <10>; + qcom,cc-delay = <5>; + qcom,cc-factor = <100>; + qcom,osm-clk-rate = <200000000>; + qcom,xo-clk-rate = <19200000>; + + qcom,l-val-base = + <0x17916004 0x17816004>; + qcom,apcs-itm-present = + <0x179d143c 0x179d143c>; + qcom,apcs-pll-user-ctl = + <0x1791600c 0x1781600c>; + qcom,apcs-cfg-rcgr = + <0x17911054 0x17811054>; + qcom,apcs-cmd-rcgr = + <0x17911050 0x17811050>; + qcom,apm-mode-ctl = + <0x179d0004 0x179d0010>; + qcom,apm-ctrl-status = + <0x179d000c 0x179d0018>; + qcom,llm-sw-overr= + <0x8fff0036 0x8fff003a 0x0fff0036>, + <0x8fff003d 0x8fff0041 0x0fff003d>; + + qcom,apm-threshold-voltage = <832000>; + qcom,boost-fsm-en; + qcom,safe-fsm-en; + qcom,ps-fsm-en; + qcom,droop-fsm-en; + qcom,wfx-fsm-en; + qcom,pc-fsm-en; + + qcom,pwrcl-apcs-mem-acc-cfg = + <0x179d1360 0x179d1364 0x179d1364>; + qcom,perfcl-apcs-mem-acc-cfg = + <0x179d1368 0x179d136C 0x179d1370>; + qcom,pwrcl-apcs-mem-acc-val = + <0x00000000 0x80000000 0x80000000>, + <0x00000000 0x00000000 0x00000000>, + <0x00000000 0x00000001 0x00000001>; + qcom,perfcl-apcs-mem-acc-val = + <0x00000000 0x00000000 0x80000000>, + <0x00000000 0x00000000 0x00000000>, + <0x00000000 0x00000000 0x00000001>; + + clock-names = "aux_clk", "xo_ao"; + clocks = <&clock_gcc clk_hmss_gpll0_clk_src>, + <&clock_gcc clk_cxo_clk_src_ao>; + #clock-cells = <1>; + }; + + clock_debug: qcom,debugcc@162000 { + compatible = "qcom,cc-debug-8998"; + reg = <0x162000 0x4>; + reg-names = "cc_base"; + clock-names = "debug_gpu_clk", "debug_gfx_clk", + "debug_mmss_clk", "debug_cpu_clk"; + clocks = <&clock_gpu clk_gpucc_gcc_dbg_clk>, + <&clock_gfx clk_gfxcc_dbg_clk>, + <&clock_mmss clk_mmss_debug_mux>, + <&clock_cpu clk_cpu_debug_mux>; + #clock-cells = <1>; + }; + + qcom,rmtfs_sharedmem@0 { + compatible = "qcom,sharedmem-uio"; + reg = <0x0 0x00200000>; + reg-names = "rmtfs"; + qcom,client-id = <0x00000001>; + }; + + qcom,msm_gsi { + compatible = "qcom,msm_gsi"; + }; + + qcom,rmnet-ipa { + compatible = "qcom,rmnet-ipa3"; + qcom,rmnet-ipa-ssr; + qcom,ipa-loaduC; + qcom,ipa-advertise-sg-support; + }; + + ipa_hw: qcom,ipa@01e00000 { + compatible = "qcom,ipa"; + reg = <0x01e00000 0x34000>, + <0x01e84000 0x31fff>, + <0x01e04000 0x2c000>; + reg-names = "ipa-base", "bam-base", "gsi-base"; + interrupts = + <0 333 0>, + <0 432 0>, + <0 432 0>; + interrupt-names = "ipa-irq", "bam-irq", "gsi-irq"; + qcom,ipa-hw-ver = <11>; /* IPA core version = IPAv3.1 */ + qcom,ipa-hw-mode = <0>; /* IPA hw type = Normal */ + qcom,ee = <0>; + qcom,use-gsi; + qcom,use-ipa-tethering-bridge; + qcom,modem-cfg-emb-pipe-flt; + qcom,do-not-use-ch-gsi-20; + qcom,ipa-wdi2; + qcom,use-64-bit-dma-mask; + clocks = <&clock_gcc clk_ipa_clk>; + clock-names = "core_clk"; + qcom,arm-smmu; + qcom,smmu-disable-htw; + qcom,smmu-s1-bypass; + qcom,msm-bus,name = "ipa"; + qcom,msm-bus,num-cases = <4>; + qcom,msm-bus,num-paths = <4>; + qcom,msm-bus,vectors-KBps = + /* No vote */ + <90 512 0 0>, + <90 585 0 0>, + <1 676 0 0>, + /* SMMU smmu_aggre2_noc_clk */ + <81 10065 0 0>, + /* SVS */ + <90 512 80000 640000>, + <90 585 80000 640000>, + <1 676 80000 80000>, + /* SMMU smmu_aggre2_noc_clk */ + <81 10065 0 16000>, + /* NOMINAL */ + <90 512 206000 960000>, + <90 585 206000 960000>, + <1 676 206000 160000>, + /* SMMU smmu_aggre2_noc_clk */ + <81 10065 0 16000>, + /* TURBO */ + <90 512 206000 3600000>, + <90 585 206000 3600000>, + <1 676 206000 300000>, + /* SMMU smmu_aggre2_noc_clk */ + <81 10065 0 16000>; + qcom,bus-vector-names = "MIN", "SVS", "NOMINAL", "TURBO"; + + /* IPA RAM mmap */ + qcom,ipa-ram-mmap = < + 0x280 /* ofst_start; */ + 0x0 /* nat_ofst; */ + 0x0 /* nat_size; */ + 0x288 /* v4_flt_hash_ofst; */ + 0x78 /* v4_flt_hash_size; */ + 0x4000 /* v4_flt_hash_size_ddr; */ + 0x308 /* v4_flt_nhash_ofst; */ + 0x78 /* v4_flt_nhash_size; */ + 0x4000 /* v4_flt_nhash_size_ddr; */ + 0x388 /* v6_flt_hash_ofst; */ + 0x78 /* v6_flt_hash_size; */ + 0x4000 /* v6_flt_hash_size_ddr; */ + 0x408 /* v6_flt_nhash_ofst; */ + 0x78 /* v6_flt_nhash_size; */ + 0x4000 /* v6_flt_nhash_size_ddr; */ + 0xf /* v4_rt_num_index; */ + 0x0 /* v4_modem_rt_index_lo; */ + 0x7 /* v4_modem_rt_index_hi; */ + 0x8 /* v4_apps_rt_index_lo; */ + 0xe /* v4_apps_rt_index_hi; */ + 0x488 /* v4_rt_hash_ofst; */ + 0x78 /* v4_rt_hash_size; */ + 0x4000 /* v4_rt_hash_size_ddr; */ + 0x508 /* v4_rt_nhash_ofst; */ + 0x78 /* v4_rt_nhash_size; */ + 0x4000 /* v4_rt_nhash_size_ddr; */ + 0xf /* v6_rt_num_index; */ + 0x0 /* v6_modem_rt_index_lo; */ + 0x7 /* v6_modem_rt_index_hi; */ + 0x8 /* v6_apps_rt_index_lo; */ + 0xe /* v6_apps_rt_index_hi; */ + 0x588 /* v6_rt_hash_ofst; */ + 0x78 /* v6_rt_hash_size; */ + 0x4000 /* v6_rt_hash_size_ddr; */ + 0x608 /* v6_rt_nhash_ofst; */ + 0x78 /* v6_rt_nhash_size; */ + 0x4000 /* v6_rt_nhash_size_ddr; */ + 0x688 /* modem_hdr_ofst; */ + 0x140 /* modem_hdr_size; */ + 0x7c8 /* apps_hdr_ofst; */ + 0x0 /* apps_hdr_size; */ + 0x800 /* apps_hdr_size_ddr; */ + 0x7d0 /* modem_hdr_proc_ctx_ofst; */ + 0x200 /* modem_hdr_proc_ctx_size; */ + 0x9d0 /* apps_hdr_proc_ctx_ofst; */ + 0x200 /* apps_hdr_proc_ctx_size; */ + 0x0 /* apps_hdr_proc_ctx_size_ddr; */ + 0x0 /* modem_comp_decomp_ofst; diff */ + 0x0 /* modem_comp_decomp_size; diff */ + 0xbd8 /* modem_ofst; */ + 0x1424 /* modem_size; */ + 0x1ffc /* apps_v4_flt_hash_ofst; */ + 0x0 /* apps_v4_flt_hash_size; */ + 0x1ffc /* apps_v4_flt_nhash_ofst; */ + 0x0 /* apps_v4_flt_nhash_size; */ + 0x1ffc /* apps_v6_flt_hash_ofst; */ + 0x0 /* apps_v6_flt_hash_size; */ + 0x1ffc /* apps_v6_flt_nhash_ofst; */ + 0x0 /* apps_v6_flt_nhash_size; */ + 0x80 /* uc_info_ofst; */ + 0x200 /* uc_info_size; */ + 0x2000 /* end_ofst; */ + 0x1ffc /* apps_v4_rt_hash_ofst; */ + 0x0 /* apps_v4_rt_hash_size; */ + 0x1ffc /* apps_v4_rt_nhash_ofst; */ + 0x0 /* apps_v4_rt_nhash_size; */ + 0x1ffc /* apps_v6_rt_hash_ofst; */ + 0x0 /* apps_v6_rt_hash_size; */ + 0x1ffc /* apps_v6_rt_nhash_ofst; */ + 0x0 /* apps_v6_rt_nhash_size; */ + >; + + /* smp2p gpio information */ + qcom,smp2pgpio_map_ipa_1_out { + compatible = "qcom,smp2pgpio-map-ipa-1-out"; + gpios = <&smp2pgpio_ipa_1_out 0 0>; + }; + + qcom,smp2pgpio_map_ipa_1_in { + compatible = "qcom,smp2pgpio-map-ipa-1-in"; + gpios = <&smp2pgpio_ipa_1_in 0 0>; + }; + + ipa_smmu_ap: ipa_smmu_ap { + compatible = "qcom,ipa-smmu-ap-cb"; + iommus = <&anoc2_smmu 0x18e0>; + qcom,iova-mapping = <0x10000000 0x40000000>; + }; + + ipa_smmu_wlan: ipa_smmu_wlan { + compatible = "qcom,ipa-smmu-wlan-cb"; + iommus = <&anoc2_smmu 0x18e1>; + }; + + ipa_smmu_uc: ipa_smmu_uc { + compatible = "qcom,ipa-smmu-uc-cb"; + iommus = <&anoc2_smmu 0x18e2>; + qcom,iova-mapping = <0x40000000 0x20000000>; + }; + }; + + qcom,ipa_fws@1e08000 { + compatible = "qcom,pil-tz-generic"; + qcom,pas-id = <0xF>; + qcom,firmware-name = "ipa_fws"; + }; + + qcom,chd_silver { + compatible = "qcom,core-hang-detect"; + label = "silver"; + qcom,threshold-arr = <0x179880b0 0x179980b0 + 0x179a80b0 0x179b80b0>; + qcom,config-arr = <0x179880b8 0x179980b8 + 0x179a80b8 0x179b80b8>; + }; + + qcom,chd_gold { + compatible = "qcom,core-hang-detect"; + label = "gold"; + qcom,threshold-arr = <0x178880b0 0x178980b0 + 0x178a80b0 0x178b80b0>; + qcom,config-arr = <0x178880b8 0x178980b8 + 0x178a80b8 0x178b80b8>; + }; + + qcom,ipc-spinlock@1f40000 { + compatible = "qcom,ipc-spinlock-sfpb"; + reg = <0x1f40000 0x8000>; + qcom,num-locks = <8>; + }; + + qcom,ghd { + compatible = "qcom,gladiator-hang-detect"; + qcom,threshold-arr = <0x179d141c 0x179d1420 + 0x179d1424 0x179d1428 0x179d142c 0x179d1430>; + qcom,config-reg = <0x179d1434>; + }; + + qcom,msm-gladiator-v2@17900000 { + compatible = "qcom,msm-gladiator-v2"; + reg = <0x17900000 0xe000>; + reg-names = "gladiator_base"; + interrupts = <0 22 0>; + clock-names = "atb_clk"; + clocks = <&clock_gcc clk_qdss_clk>; + }; + + qcom,smem@86000000 { + compatible = "qcom,smem"; + reg = <0x86000000 0x200000>, + <0x17911008 0x4>, + <0x778000 0x7000>, + <0x1fd4000 0x8>; + reg-names = "smem", "irq-reg-base", "aux-mem1", + "smem_targ_info_reg"; + qcom,mpu-enabled; + }; + + qcom,msm-adsprpc-mem { + compatible = "qcom,msm-adsprpc-mem-region"; + memory-region = <&adsp_mem>; + }; + + qcom,msm_fastrpc { + compatible = "qcom,msm-fastrpc-adsp"; + qcom,fastrpc-glink; + + qcom,msm_fastrpc_cpz_cb1 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "adsprpc-smd"; + iommus = <&lpass_q6_smmu 2>; + qcom,secure-context-bank; + dma-coherent; + }; + qcom,msm_fastrpc_compute_cb1 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "adsprpc-smd"; + iommus = <&lpass_q6_smmu 8>; + dma-coherent; + }; + qcom,msm_fastrpc_compute_cb2 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "adsprpc-smd"; + iommus = <&lpass_q6_smmu 9>; + dma-coherent; + }; + qcom,msm_fastrpc_compute_cb3 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "adsprpc-smd"; + iommus = <&lpass_q6_smmu 10>; + dma-coherent; + }; + qcom,msm_fastrpc_compute_cb4 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "adsprpc-smd"; + iommus = <&lpass_q6_smmu 11>; + dma-coherent; + }; + qcom,msm_fastrpc_compute_cb6 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "adsprpc-smd"; + iommus = <&lpass_q6_smmu 5>; + dma-coherent; + }; + qcom,msm_fastrpc_compute_cb7 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "adsprpc-smd"; + iommus = <&lpass_q6_smmu 6>; + dma-coherent; + }; + qcom,msm_fastrpc_compute_cb8 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "adsprpc-smd"; + iommus = <&lpass_q6_smmu 7>; + dma-coherent; + }; + }; + + rpm_bus: qcom,rpm-smd { + compatible = "qcom,rpm-glink"; + qcom,glink-edge = "rpm"; + rpm-channel-name = "rpm_requests"; + }; + + glink_mpss: qcom,glink-ssr-modem { + compatible = "qcom,glink_ssr"; + label = "modem"; + qcom,edge = "mpss"; + qcom,notify-edges = <&glink_lpass>, <&glink_dsps>, <&glink_rpm>; + qcom,xprt = "smem"; + }; + + glink_lpass: qcom,glink-ssr-adsp { + compatible = "qcom,glink_ssr"; + label = "adsp"; + qcom,edge = "lpass"; + qcom,notify-edges = <&glink_mpss>, <&glink_dsps>, <&glink_rpm>; + qcom,xprt = "smem"; + }; + + glink_dsps: qcom,glink-ssr-dsps { + compatible = "qcom,glink_ssr"; + label = "slpi"; + qcom,edge = "dsps"; + qcom,notify-edges = <&glink_mpss>, <&glink_lpass>, <&glink_rpm>; + qcom,xprt = "smem"; + }; + + glink_rpm: qcom,glink-ssr-rpm { + compatible = "qcom,glink_ssr"; + label = "rpm"; + qcom,edge = "rpm"; + qcom,notify-edges = <&glink_lpass>, <&glink_mpss>, + <&glink_dsps>, <&glink_spss>; + qcom,xprt = "smem"; + }; + + glink_spss: qcom,glink-ssr-spss { + compatible = "qcom,glink_ssr"; + label = "spss"; + qcom,edge = "spss"; + qcom,notify-edges = <&glink_mpss>, <&glink_lpass>, + <&glink_dsps>, <&glink_rpm>; + qcom,xprt = "mailbox"; + }; + + qcom,glink-smem-native-xprt-modem@86000000 { + compatible = "qcom,glink-smem-native-xprt"; + reg = <0x86000000 0x200000>, + <0x17911008 0x4>; + reg-names = "smem", "irq-reg-base"; + qcom,irq-mask = <0x8000>; + interrupts = <0 452 1>; + label = "mpss"; + }; + + qcom,glink-smem-native-xprt-adsp@86000000 { + compatible = "qcom,glink-smem-native-xprt"; + reg = <0x86000000 0x200000>, + <0x17911008 0x4>; + reg-names = "smem", "irq-reg-base"; + qcom,irq-mask = <0x200>; + interrupts = <0 157 1>; + label = "lpass"; + qcom,qos-config = <&glink_qos_adsp>; + qcom,ramp-time = <0xaf>; + }; + + glink_qos_adsp: qcom,glink-qos-config-adsp { + compatible = "qcom,glink-qos-config"; + qcom,flow-info = <0x3c 0x0>, + <0x3c 0x0>, + <0x3c 0x0>, + <0x3c 0x0>; + qcom,mtu-size = <0x800>; + qcom,tput-stats-cycle = <0xa>; + }; + + qcom,glink-smem-native-xprt-dsps@86000000 { + compatible = "qcom,glink-smem-native-xprt"; + reg = <0x86000000 0x200000>, + <0x17911008 0x4>; + reg-names = "smem", "irq-reg-base"; + qcom,irq-mask = <0x8000000>; + interrupts = <0 179 1>; + label = "dsps"; + }; + + qcom,glink-smem-native-xprt-rpm@778000 { + compatible = "qcom,glink-rpm-native-xprt"; + reg = <0x778000 0x7000>, + <0x17911008 0x4>; + reg-names = "msgram", "irq-reg-base"; + qcom,irq-mask = <0x1>; + interrupts = <0 168 1>; + label = "rpm"; + }; + + qcom,glink-mailbox-xprt-spss@1d05008 { + compatible = "qcom,glink-mailbox-xprt"; + reg = <0x1d05008 0x8>, + <0x1d05010 0x4>, + <0x1d0501c 0x4>, + <0x1d06008 0x4>; + reg-names = "mbox-loc-addr", "mbox-loc-size", "irq-reg-base", + "irq-rx-reset"; + qcom,irq-mask = <0x1>; + interrupts = <0 348 4>; + label = "spss"; + qcom,tx-ring-size = <0x800>; + qcom,rx-ring-size = <0x800>; + }; + + glink_spi_xprt_wdsp: qcom,glink-spi-xprt-wdsp { + compatible = "qcom,glink-spi-xprt"; + label = "wdsp"; + qcom,remote-fifo-config = <&glink_fifo_wdsp>; + qcom,qos-config = <&glink_qos_wdsp>; + qcom,ramp-time = <0x10>, + <0x20>, + <0x30>, + <0x40>; + }; + + glink_fifo_wdsp: qcom,glink-fifo-config-wdsp { + compatible = "qcom,glink-fifo-config"; + qcom,out-read-idx-reg = <0x12000>; + qcom,out-write-idx-reg = <0x12004>; + qcom,in-read-idx-reg = <0x1200C>; + qcom,in-write-idx-reg = <0x12010>; + }; + + glink_qos_wdsp: qcom,glink-qos-config-wdsp { + compatible = "qcom,glink-qos-config"; + qcom,flow-info = <0x80 0x0>, + <0x70 0x1>, + <0x60 0x2>, + <0x50 0x3>; + qcom,mtu-size = <0x800>; + qcom,tput-stats-cycle = <0xa>; + }; + + qcom,glink_pkt { + compatible = "qcom,glinkpkt"; + + qcom,glinkpkt-at-mdm0 { + qcom,glinkpkt-transport = "smem"; + qcom,glinkpkt-edge = "mpss"; + qcom,glinkpkt-ch-name = "DS"; + qcom,glinkpkt-dev-name = "at_mdm0"; + }; + + qcom,glinkpkt-loopback_cntl { + qcom,glinkpkt-transport = "lloop"; + qcom,glinkpkt-edge = "local"; + qcom,glinkpkt-ch-name = "LOCAL_LOOPBACK_CLNT"; + qcom,glinkpkt-dev-name = "glink_pkt_loopback_ctrl"; + }; + + qcom,glinkpkt-loopback_data { + qcom,glinkpkt-transport = "lloop"; + qcom,glinkpkt-edge = "local"; + qcom,glinkpkt-ch-name = "glink_pkt_lloop_CLNT"; + qcom,glinkpkt-dev-name = "glink_pkt_loopback"; + }; + + qcom,glinkpkt-apr-apps2 { + qcom,glinkpkt-transport = "smem"; + qcom,glinkpkt-edge = "adsp"; + qcom,glinkpkt-ch-name = "apr_apps2"; + qcom,glinkpkt-dev-name = "apr_apps2"; + }; + + qcom,glinkpkt-data40-cntl { + qcom,glinkpkt-transport = "smem"; + qcom,glinkpkt-edge = "mpss"; + qcom,glinkpkt-ch-name = "DATA40_CNTL"; + qcom,glinkpkt-dev-name = "smdcntl8"; + }; + + qcom,glinkpkt-data1 { + qcom,glinkpkt-transport = "smem"; + qcom,glinkpkt-edge = "mpss"; + qcom,glinkpkt-ch-name = "DATA1"; + qcom,glinkpkt-dev-name = "smd7"; + }; + + qcom,glinkpkt-data4 { + qcom,glinkpkt-transport = "smem"; + qcom,glinkpkt-edge = "mpss"; + qcom,glinkpkt-ch-name = "DATA4"; + qcom,glinkpkt-dev-name = "smd8"; + }; + + qcom,glinkpkt-data11 { + qcom,glinkpkt-transport = "smem"; + qcom,glinkpkt-edge = "mpss"; + qcom,glinkpkt-ch-name = "DATA11"; + qcom,glinkpkt-dev-name = "smd11"; + }; + }; + + qcom,ipc_router { + compatible = "qcom,ipc_router"; + qcom,node-id = <1>; + }; + + qcom,ipc_router_modem_xprt { + compatible = "qcom,ipc_router_glink_xprt"; + qcom,ch-name = "IPCRTR"; + qcom,xprt-remote = "mpss"; + qcom,glink-xprt = "smem"; + qcom,xprt-linkid = <1>; + qcom,xprt-version = <1>; + qcom,fragmented-data; + }; + + qcom,ipc_router_q6_xprt { + compatible = "qcom,ipc_router_glink_xprt"; + qcom,ch-name = "IPCRTR"; + qcom,xprt-remote = "lpass"; + qcom,glink-xprt = "smem"; + qcom,xprt-linkid = <1>; + qcom,xprt-version = <1>; + qcom,fragmented-data; + }; + + qcom,ipc_router_dsps_xprt { + compatible = "qcom,ipc_router_glink_xprt"; + qcom,ch-name = "IPCRTR"; + qcom,xprt-remote = "dsps"; + qcom,glink-xprt = "smem"; + qcom,xprt-linkid = <1>; + qcom,xprt-version = <1>; + qcom,fragmented-data; + qcom,dynamic-wakeup-source; + }; + + qcom,spcom { + compatible = "qcom,spcom"; + + /* predefined channels, remote side is server */ + qcom,spcom-ch-names = "sp_kernel" , "sp_ssr"; + status = "ok"; + }; + + spss_utils: qcom,spss_utils { + compatible = "qcom,spss-utils"; + /* spss fuses physical address */ + qcom,spss-fuse1-addr = <0x007841c4>; + qcom,spss-fuse1-bit = <27>; + qcom,spss-fuse2-addr = <0x0078413c>; + qcom,spss-fuse2-bit = <31>; + qcom,spss-test-firmware-name = "spss"; /* default name */ + qcom,spss-prod-firmware-name = "spss1p"; /* 8 chars max */ + qcom,spss-hybr-firmware-name = "spss1h"; /* 8 chars max */ + qcom,spss-debug-reg-addr = <0x01d06020>; + status = "ok"; + }; + + sdhc_2: sdhci@c0a4900 { + compatible = "qcom,sdhci-msm"; + reg = <0xc0a4900 0x314>, <0xc0a4000 0x800>; + reg-names = "hc_mem", "core_mem"; + + interrupts = <0 125 0>, <0 221 0>; + interrupt-names = "hc_irq", "pwr_irq"; + + clock-names = "iface_clk", "core_clk"; + clocks = <&clock_gcc clk_gcc_sdcc2_ahb_clk>, + <&clock_gcc clk_gcc_sdcc2_apps_clk>; + + qcom,large-address-bus; + qcom,bus-width = <4>; + qcom,cpu-dma-latency-us = <701>; + + qcom,devfreq,freq-table = <52000000 200000000>; + + qcom,msm-bus,name = "sdhc2"; + qcom,msm-bus,num-cases = <8>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = <81 512 0 0>, /* No vote */ + <81 512 1600 3200>, /* 400 KB/s*/ + <81 512 80000 160000>, /* 20 MB/s */ + <81 512 100000 200000>, /* 25 MB/s */ + <81 512 200000 400000>, /* 50 MB/s */ + <81 512 400000 800000>, /* 100 MB/s */ + <81 512 800000 800000>, /* 200 MB/s */ + <81 512 2048000 4096000>; /* Max. bandwidth */ + qcom,bus-bw-vectors-bps = <0 400000 20000000 25000000 50000000 + 100000000 200000000 4294967295>; + + qcom,sdr104-wa; + + status = "disabled"; + }; + + ufsphy1: ufsphy@1da7000 { + compatible = "qcom,ufs-phy-qmp-v3"; + reg = <0x1da7000 0xda8>; + reg-names = "phy_mem"; + #phy-cells = <0>; + clock-names = "ref_clk_src", + "ref_clk", + "ref_aux_clk"; + clocks = <&clock_gcc clk_ln_bb_clk1>, + <&clock_gcc clk_gcc_ufs_clkref_clk>, + <&clock_gcc clk_gcc_ufs_phy_aux_hw_ctl_clk>; + status = "disabled"; + }; + + ufs_ice: ufsice@1db0000 { + compatible = "qcom,ice"; + reg = <0x1db0000 0x8000>; + qcom,enable-ice-clk; + clock-names = "ufs_core_clk", + "bus_clk", + "iface_clk", + "ice_core_clk"; + clocks = <&clock_gcc clk_gcc_ufs_axi_clk>, + <&clock_gcc clk_gcc_aggre1_ufs_axi_clk>, + <&clock_gcc clk_gcc_ufs_ahb_clk>, + <&clock_gcc clk_gcc_ufs_ice_core_clk>; + qcom,op-freq-hz = <0>, + <0>, + <0>, + <300000000>; + vdd-hba-supply = <&gdsc_ufs>; + qcom,msm-bus,name = "ufs_ice_noc"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <1 650 0 0>, /* No vote */ + <1 650 1000 0>; /* Max. bandwidth */ + qcom,bus-vector-names = "MIN", + "MAX"; + qcom,instance-type = "ufs"; + status = "disabled"; + }; + + ufs1: ufshc@1da4000 { + compatible = "qcom,ufshc"; + reg = <0x1da4000 0x2500>; + interrupts = <0 265 0>; + phys = <&ufsphy1>; + phy-names = "ufsphy"; + ufs-qcom-crypto = <&ufs_ice>; + + clock-names = + "core_clk", + "bus_aggr_clk", + "iface_clk", + "core_clk_unipro", + "core_clk_ice", + "ref_clk", + "tx_lane0_sync_clk", + "rx_lane0_sync_clk"; + clocks = + <&clock_gcc clk_gcc_ufs_axi_hw_ctl_clk>, + <&clock_gcc clk_gcc_aggre1_ufs_axi_hw_ctl_clk>, + <&clock_gcc clk_gcc_ufs_ahb_clk>, + <&clock_gcc clk_gcc_ufs_unipro_core_hw_ctl_clk>, + <&clock_gcc clk_gcc_ufs_ice_core_hw_ctl_clk>, + <&clock_gcc clk_ln_bb_clk1>, + <&clock_gcc clk_gcc_ufs_tx_symbol_0_clk>, + <&clock_gcc clk_gcc_ufs_rx_symbol_0_clk>; + freq-table-hz = + <50000000 200000000>, + <0 0>, + <0 0>, + <37500000 150000000>, + <75000000 300000000>, + <0 0>, + <0 0>, + <0 0>; + + lanes-per-direction = <1>; + + qcom,msm-bus,name = "ufs1"; + qcom,msm-bus,num-cases = <22>; + qcom,msm-bus,num-paths = <2>; + qcom,msm-bus,vectors-KBps = + /* + * During HS G3 UFS runs at nominal voltage corner, vote + * higher bandwidth to push other buses in the data path + * to run at nominal to achieve max throughput. + * 4GBps pushes BIMC to run at nominal. + * 200MBps pushes CNOC to run at nominal. + * Vote for half of this bandwidth for HS G3 1-lane. + * For max bandwidth, vote high enough to push the buses + * to run in turbo voltage corner. + */ + <95 512 0 0>, <1 650 0 0>, /* No vote */ + <95 512 922 0>, <1 650 1000 0>, /* PWM G1 */ + <95 512 1844 0>, <1 650 1000 0>, /* PWM G2 */ + <95 512 3688 0>, <1 650 1000 0>, /* PWM G3 */ + <95 512 7376 0>, <1 650 1000 0>, /* PWM G4 */ + <95 512 1844 0>, <1 650 1000 0>, /* PWM G1 L2 */ + <95 512 3688 0>, <1 650 1000 0>, /* PWM G2 L2 */ + <95 512 7376 0>, <1 650 1000 0>, /* PWM G3 L2 */ + <95 512 14752 0>, <1 650 1000 0>, /* PWM G4 L2 */ + <95 512 127796 0>, <1 650 1000 0>, /* HS G1 RA */ + <95 512 255591 0>, <1 650 1000 0>, /* HS G2 RA */ + <95 512 2097152 0>, <1 650 102400 0>, /* HS G3 RA */ + <95 512 255591 0>, <1 650 1000 0>, /* HS G1 RA L2 */ + <95 512 511181 0>, <1 650 1000 0>, /* HS G2 RA L2 */ + <95 512 4194304 0>, <1 650 204800 0>, /* HS G3 RA L2 */ + <95 512 149422 0>, <1 650 1000 0>, /* HS G1 RB */ + <95 512 298189 0>, <1 650 1000 0>, /* HS G2 RB */ + <95 512 2097152 0>, <1 650 102400 0>, /* HS G3 RB */ + <95 512 298189 0>, <1 650 1000 0>, /* HS G1 RB L2 */ + <95 512 596378 0>, <1 650 1000 0>, /* HS G2 RB L2 */ + <95 512 4194304 0>, <1 650 204800 0>, /* HS G3 RB L2 */ + <95 512 7643136 0>, <1 650 307200 0>; /* Max. bandwidth */ + qcom,bus-vector-names = "MIN", + "PWM_G1_L1", "PWM_G2_L1", "PWM_G3_L1", "PWM_G4_L1", + "PWM_G1_L2", "PWM_G2_L2", "PWM_G3_L2", "PWM_G4_L2", + "HS_RA_G1_L1", "HS_RA_G2_L1", "HS_RA_G3_L1", + "HS_RA_G1_L2", "HS_RA_G2_L2", "HS_RA_G3_L2", + "HS_RB_G1_L1", "HS_RB_G2_L1", "HS_RB_G3_L1", + "HS_RB_G1_L2", "HS_RB_G2_L2", "HS_RB_G3_L2", + "MAX"; + + /* PM QoS */ + qcom,pm-qos-cpu-groups = <0x0F 0xF0>; + qcom,pm-qos-cpu-group-latency-us = <70 70>; + qcom,pm-qos-default-cpu = <0>; + + pinctrl-names = "dev-reset-assert", "dev-reset-deassert"; + pinctrl-0 = <&ufs_dev_reset_assert>; + pinctrl-1 = <&ufs_dev_reset_deassert>; + + resets = <&clock_gcc UFS_BCR>; + reset-names = "core_reset"; + + status = "disabled"; + }; + + usb3: ssusb@a800000 { + compatible = "qcom,dwc-usb3-msm"; + reg = <0x0a800000 0xf8c00>, + <0x0c016000 0x400>; + reg-names = "core_base", "ahb2phy_base"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + interrupts = <0 347 0>, <0 243 0>, <0 180 0>; + interrupt-names = "hs_phy_irq", "ss_phy_irq", "pwr_event_irq"; + + USB3_GDSC-supply = <&gdsc_usb30>; + qcom,usb-dbm = <&dbm_1p5>; + qcom,msm-bus,name = "usb3"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <61 512 0 0>, + <61 512 240000 800000>; + + qcom,dwc-usb3-msm-tx-fifo-size = <21288>; + extcon = <&pmi8998_pdphy>; + + clocks = <&clock_gcc clk_gcc_usb30_master_clk>, + <&clock_gcc clk_gcc_cfg_noc_usb3_axi_clk>, + <&clock_gcc clk_gcc_aggre1_usb3_axi_clk>, + <&clock_gcc clk_gcc_usb30_mock_utmi_clk>, + <&clock_gcc clk_gcc_usb30_sleep_clk>, + <&clock_gcc clk_cxo_dwc3_clk>; + + clock-names = "core_clk", "iface_clk", "bus_aggr_clk", + "utmi_clk", "sleep_clk", "xo"; + + qcom,core-clk-rate = <120000000>; + qcom,core-clk-rate-hs = <60000000>; + + resets = <&clock_gcc USB_30_BCR>; + reset-names = "core_reset"; + + dwc3@a800000 { + compatible = "snps,dwc3"; + reg = <0x0a800000 0xcd00>; + interrupt-parent = <&intc>; + interrupts = <0 131 0>; + usb-phy = <&qusb_phy0>, <&ssphy>; + tx-fifo-resize; + snps,nominal-elastic-buffer; + snps,disable-clk-gating; + snps,has-lpm-erratum; + snps,hird-threshold = /bits/ 8 <0x10>; + snps,num-gsi-evt-buffs = <0x3>; + }; + + qcom,usbbam@a904000 { + compatible = "qcom,usb-bam-msm"; + reg = <0xa904000 0x17000>; + interrupt-parent = <&intc>; + interrupts = <0 132 0>; + + qcom,bam-type = <0>; + qcom,usb-bam-fifo-baseaddr = <0x146bb000>; + qcom,usb-bam-num-pipes = <8>; + qcom,ignore-core-reset-ack; + qcom,disable-clk-gating; + qcom,usb-bam-override-threshold = <0x4001>; + qcom,usb-bam-max-mbps-highspeed = <400>; + qcom,usb-bam-max-mbps-superspeed = <3600>; + qcom,reset-bam-on-connect; + + qcom,pipe0 { + label = "ssusb-qdss-in-0"; + qcom,usb-bam-mem-type = <2>; + qcom,dir = <1>; + qcom,pipe-num = <0>; + qcom,peer-bam = <0>; + qcom,peer-bam-physical-address = <0x6064000>; + qcom,src-bam-pipe-index = <0>; + qcom,dst-bam-pipe-index = <0>; + qcom,data-fifo-offset = <0x0>; + qcom,data-fifo-size = <0x1800>; + qcom,descriptor-fifo-offset = <0x1800>; + qcom,descriptor-fifo-size = <0x800>; + }; + }; + }; + + qusb_phy0: qusb@c012000 { + compatible = "qcom,qusb2phy-v2"; + reg = <0x0c012000 0x2a8>, + <0x01fcb24c 0x4>; + reg-names = "qusb_phy_base", + "tcsr_clamp_dig_n_1p8"; + vdd-supply = <&pm8998_l1>; + vdda12-supply = <&pm8998_l2>; + vdda18-supply = <&pm8998_l12>; + vdda33-supply = <&pm8998_l24>; + qcom,vdd-voltage-level = <0 880000 880000>; + qcom,vdda33-voltage-level = <2400000 3088000 3088000>; + qcom,qusb-phy-init-seq = + /* */ + <0x80 0x0 + 0x13 0x04 + 0x7c 0x18c + 0x80 0x2c + 0x0a 0x184 + 0x00 0x240>; + phy_type= "utmi"; + + clocks = <&clock_gcc clk_ln_bb_clk1>, + <&clock_gcc clk_gcc_rx1_usb2_clkref_clk>; + clock-names = "ref_clk_src", "ref_clk"; + + resets = <&clock_gcc QUSB2PHY_PRIM_BCR>; + reset-names = "phy_reset"; + }; + + ssphy: ssphy@c010000 { + compatible = "qcom,usb-ssphy-qmp-v2"; + reg = <0x0c010000 0xe0c>, + <0x01fcb244 0x4>, + <0x01fcb248 0x4>; + reg-names = "qmp_phy_base", + "vls_clamp_reg", + "tcsr_usb3_dp_phymode"; + vdd-supply = <&pm8998_l1>; + core-supply = <&pm8998_l2>; + qcom,vdd-voltage-level = <0 880000 880000>; + qcom,vbus-valid-override; + qcom,qmp-phy-init-seq = + /* */ + <0x138 0x30 0x00 + 0x034 0x04 0x01 + 0x080 0x14 0x00 + 0x03c 0x06 0x00 + 0x08c 0x08 0x00 + 0x15c 0x06 0x00 + 0x164 0x01 0x00 + 0x13c 0x80 0x00 + 0x0b0 0x82 0x00 + 0x0b8 0xab 0x00 + 0x0bc 0xea 0x00 + 0x0c0 0x02 0x00 + 0x060 0x06 0x00 + 0x068 0x16 0x00 + 0x070 0x36 0x00 + 0x0dc 0x00 0x00 + 0x0d8 0x3f 0x00 + 0x0f8 0x01 0x00 + 0x0f4 0xc9 0x00 + 0x148 0x0a 0x00 + 0x0a0 0x00 0x00 + 0x09c 0x34 0x00 + 0x098 0x15 0x00 + 0x090 0x04 0x00 + 0x154 0x00 0x00 + 0x094 0x00 0x00 + 0x0f0 0x00 0x00 + 0x00c 0x0a 0x00 + 0x048 0x07 0x00 + 0x0d0 0x80 0x00 + 0x184 0x01 0x00 + 0x010 0x01 0x00 + 0x01c 0x31 0x00 + 0x020 0x01 0x00 + 0x014 0x00 0x00 + 0x018 0x00 0x00 + 0x024 0x85 0x00 + 0x028 0x07 0x00 + 0x430 0x0b 0x00 + 0x4d4 0x0f 0x00 + 0x4d8 0x4e 0x00 + 0x4dc 0x18 0x00 + 0x4f8 0x07 0x00 + 0x4fc 0x80 0x00 + 0x504 0x43 0x00 + 0x50c 0x1c 0x00 + 0x434 0x75 0x00 + 0x43c 0x00 0x00 + 0x440 0x00 0x00 + 0x444 0x80 0x00 + 0x408 0x0a 0x00 + 0x414 0x06 0x00 + 0x500 0x00 0x00 + 0x4c0 0x03 0x00 + 0x564 0x05 0x00 + 0x830 0x0b 0x00 + 0x8d4 0x0f 0x00 + 0x8d8 0x4e 0x00 + 0x8dc 0x18 0x00 + 0x8f8 0x07 0x00 + 0x8fc 0x80 0x00 + 0x904 0x43 0x00 + 0x90c 0x1c 0x00 + 0x834 0x75 0x00 + 0x83c 0x00 0x00 + 0x840 0x00 0x00 + 0x844 0x80 0x00 + 0x808 0x0a 0x00 + 0x814 0x06 0x00 + 0x900 0x00 0x00 + 0x8c0 0x03 0x00 + 0x964 0x05 0x00 + 0x260 0x10 0x00 + 0x2a4 0x12 0x00 + 0x28c 0x16 0x00 + 0x244 0x00 0x00 + 0x660 0x10 0x00 + 0x6a4 0x12 0x00 + 0x68c 0x16 0x00 + 0x644 0x00 0x00 + 0xcc8 0x83 0x00 + 0xccc 0x09 0x00 + 0xcd0 0xa2 0x00 + 0xcd4 0x40 0x00 + 0xcc4 0x02 0x00 + 0xc80 0xd1 0x00 + 0xc84 0x1f 0x00 + 0xc88 0x47 0x00 + 0xc64 0x1b 0x00 + 0xc0c 0x9f 0x00 + 0xc10 0x9f 0x00 + 0xc14 0xb7 0x00 + 0xc18 0x4e 0x00 + 0xc1c 0x65 0x00 + 0xc20 0x6b 0x00 + 0xc24 0x15 0x00 + 0xc28 0x0d 0x00 + 0xc2c 0x15 0x00 + 0xc30 0x0d 0x00 + 0xc34 0x15 0x00 + 0xc38 0x0d 0x00 + 0xc3c 0x15 0x00 + 0xc40 0x0d 0x00 + 0xc44 0x15 0x00 + 0xc48 0x0d 0x00 + 0xc4c 0x15 0x00 + 0xc50 0x0d 0x00 + 0xc5c 0x02 0x00 + 0xca0 0x04 0x00 + 0xc8c 0x44 0x00 + 0xc70 0xe7 0x00 + 0xc74 0x03 0x00 + 0xc78 0x40 0x00 + 0xc7c 0x00 0x00 + 0xdd8 0x8a 0x00 + 0xcb8 0x75 0x00 + 0xcb0 0x86 0x00 + 0xcbc 0x13 0x00 + 0xffffffff 0xffffffff 0x00>; + + qcom,qmp-phy-reg-offset = + <0xd74 /* USB3_PHY_PCS_STATUS */ + 0xcd8 /* USB3_PHY_AUTONOMOUS_MODE_CTRL */ + 0xcdc /* USB3_PHY_LFPS_RXTERM_IRQ_CLEAR */ + 0xc04 /* USB3_PHY_POWER_DOWN_CONTROL */ + 0xc00 /* USB3_PHY_SW_RESET */ + 0xc08 /* USB3_PHY_START */ + 0xa00>; /* USB3PHY_PCS_MISC_TYPEC_CTRL */ + + clocks = <&clock_gcc clk_gcc_usb3_phy_aux_clk>, + <&clock_gcc clk_gcc_usb3_phy_pipe_clk>, + <&clock_gcc clk_ln_bb_clk1>, + <&clock_gcc clk_gcc_usb3_clkref_clk>; + + clock-names = "aux_clk", "pipe_clk", "ref_clk_src", + "ref_clk"; + + resets = <&clock_gcc USB3_PHY_BCR>, + <&clock_gcc USB3PHY_PHY_BCR>; + reset-names = "phy_reset", "phy_phy_reset"; + }; + + usb_audio_qmi_dev { + compatible = "qcom,usb-audio-qmi-dev"; + iommus = <&lpass_q6_smmu 12>; + qcom,usb-audio-stream-id = <12>; + qcom,usb-audio-intr-num = <2>; + }; + + dbm_1p5: dbm@a8f8000 { + compatible = "qcom,usb-dbm-1p5"; + reg = <0xa8f8000 0x300>; + qcom,reset-ep-after-lpm-resume; + }; + + usb_nop_phy: usb_nop_phy { + compatible = "usb-nop-xceiv"; + }; + + qcom,lpass@17300000 { + compatible = "qcom,pil-tz-generic"; + reg = <0x17300000 0x00100>; + interrupts = <0 162 1>; + + vdd_cx-supply = <&pm8998_s1_level>; + qcom,proxy-reg-names = "vdd_cx"; + qcom,vdd_cx-uV-uA = ; + + clocks = <&clock_gcc clk_cxo_pil_lpass_clk>; + clock-names = "xo"; + qcom,proxy-clock-names = "xo"; + + qcom,pas-id = <1>; + qcom,proxy-timeout-ms = <10000>; + qcom,smem-id = <423>; + qcom,sysmon-id = <1>; + status = "ok"; + qcom,ssctl-instance-id = <0x14>; + qcom,firmware-name = "adsp"; + memory-region = <&pil_adsp_mem>; + + /* GPIO inputs from lpass */ + qcom,gpio-err-fatal = <&smp2pgpio_ssr_smp2p_2_in 0 0>; + qcom,gpio-proxy-unvote = <&smp2pgpio_ssr_smp2p_2_in 2 0>; + qcom,gpio-err-ready = <&smp2pgpio_ssr_smp2p_2_in 1 0>; + qcom,gpio-stop-ack = <&smp2pgpio_ssr_smp2p_2_in 3 0>; + + /* GPIO output to lpass */ + qcom,gpio-force-stop = <&smp2pgpio_ssr_smp2p_2_out 0 0>; + }; + + qcom,memshare { + compatible = "qcom,memshare"; + + qcom,client_1 { + compatible = "qcom,memshare-peripheral"; + qcom,peripheral-size = <0x200000>; + qcom,client-id = <0>; + qcom,allocate-boot-time; + label = "modem"; + }; + + qcom,client_2 { + compatible = "qcom,memshare-peripheral"; + qcom,peripheral-size = <0x300000>; + qcom,client-id = <2>; + label = "modem"; + }; + + mem_client_3_size: qcom,client_3 { + compatible = "qcom,memshare-peripheral"; + qcom,peripheral-size = <0x0>; + qcom,client-id = <1>; + qcom,allocate-boot-time; + label = "modem"; + }; + }; + + pil_modem: qcom,mss@4080000 { + compatible = "qcom,pil-q6v55-mss"; + reg = <0x4080000 0x100>, + <0x1f63000 0x008>, + <0x1f65000 0x008>, + <0x1f64000 0x008>, + <0x4180000 0x020>, + <0x00179000 0x004>; + reg-names = "qdsp6_base", "halt_q6", "halt_modem", + "halt_nc", "rmb_base", "restart_reg"; + + clocks = <&clock_gcc clk_cxo_clk_src>, + <&clock_gcc clk_gcc_mss_cfg_ahb_clk>, + <&clock_gcc clk_gcc_bimc_mss_q6_axi_clk>, + <&clock_gcc clk_gcc_boot_rom_ahb_clk>, + <&clock_gcc clk_gpll0_out_msscc>, + <&clock_gcc clk_gcc_mss_snoc_axi_clk>, + <&clock_gcc clk_gcc_mss_mnoc_bimc_axi_clk>, + <&clock_gcc clk_qdss_clk>; + clock-names = "xo", "iface_clk", "bus_clk", + "mem_clk", "gpll0_mss_clk", "snoc_axi_clk", + "mnoc_axi_clk", "qdss_clk"; + qcom,proxy-clock-names = "xo", "qdss_clk", "mem_clk"; + qcom,active-clock-names = "iface_clk", "bus_clk", + "gpll0_mss_clk", "snoc_axi_clk", "mnoc_axi_clk"; + + interrupts = <0 448 1>; + vdd_cx-supply = <&pm8998_s1_level>; + vdd_cx-voltage = ; + vdd_mx-supply = <&pm8998_s9_level>; + vdd_mx-uV = ; + qcom,firmware-name = "modem"; + qcom,pil-self-auth; + qcom,sysmon-id = <0>; + qcom,ssctl-instance-id = <0x12>; + qcom,qdsp6v62-1-2; + status = "ok"; + memory-region = <&modem_mem>; + qcom,mem-protect-id = <0xF>; + + /* GPIO inputs from mss */ + qcom,gpio-err-fatal = <&smp2pgpio_ssr_smp2p_1_in 0 0>; + qcom,gpio-err-ready = <&smp2pgpio_ssr_smp2p_1_in 1 0>; + qcom,gpio-proxy-unvote = <&smp2pgpio_ssr_smp2p_1_in 2 0>; + qcom,gpio-stop-ack = <&smp2pgpio_ssr_smp2p_1_in 3 0>; + qcom,gpio-shutdown-ack = <&smp2pgpio_ssr_smp2p_1_in 7 0>; + + /* GPIO output to mss */ + qcom,gpio-force-stop = <&smp2pgpio_ssr_smp2p_1_out 0 0>; + qcom,mba-mem@0 { + compatible = "qcom,pil-mba-mem"; + memory-region = <&pil_mba_mem>; + }; + }; + + tsens0: tsens@10aa000 { + compatible = "qcom,msm8998-tsens"; + reg = <0x10aa000 0x2000>; + reg-names = "tsens_physical"; + interrupts = <0 458 0>, <0 445 0>; + interrupt-names = "tsens-upper-lower", "tsens-critical"; + qcom,client-id = <0 1 2 3 4 7 8 9 10 11 12 13>; + qcom,sensor-id = <0 1 2 3 4 7 8 9 10 11 12 13>; + qcom,sensors = <12>; + }; + + tsens1: tsens@10ad000 { + compatible = "qcom,msm8998-tsens"; + reg = <0x10ad000 0x2000>; + reg-names = "tsens_physical"; + interrupts = <0 184 0>, <0 430 0>; + interrupt-names = "tsens-upper-lower", "tsens-critical"; + qcom,client-id = <14 15 16 17 18 19 20 21>; + qcom,sensor-id = <0 1 3 4 5 6 7 2>; + qcom,sensors = <8>; + }; + + qcom,qbt1000 { + compatible = "qcom,qbt1000"; + clock-names = "core", "iface"; + clocks = <&clock_gcc clk_gcc_blsp2_qup6_spi_apps_clk>, + <&clock_gcc clk_gcc_blsp2_ahb_clk>; + clock-frequency = <15000000>; + qcom,ipc-gpio = <&tlmm 121 0>; + qcom,finger-detect-gpio = <&pm8998_gpios 2 0>; + }; + + qcom,sensor-information { + compatible = "qcom,sensor-information"; + sensor_information0: qcom,sensor-information-0 { + qcom,sensor-type = "tsens"; + qcom,sensor-name = "tsens_tz_sensor0"; + qcom,scaling-factor = <10>; + }; + sensor_information1: qcom,sensor-information-1 { + qcom,sensor-type = "tsens"; + qcom,sensor-name = "tsens_tz_sensor1"; + qcom,scaling-factor = <10>; + }; + sensor_information2: qcom,sensor-information-2 { + qcom,sensor-type = "tsens"; + qcom,sensor-name = "tsens_tz_sensor2"; + qcom,scaling-factor = <10>; + }; + sensor_information3: qcom,sensor-information-3 { + qcom,sensor-type = "tsens"; + qcom,sensor-name = "tsens_tz_sensor3"; + qcom,scaling-factor = <10>; + }; + sensor_information4: qcom,sensor-information-4 { + qcom,sensor-type = "tsens"; + qcom,sensor-name = "tsens_tz_sensor4"; + qcom,scaling-factor = <10>; + }; + sensor_information7: qcom,sensor-information-7 { + qcom,sensor-type = "tsens"; + qcom,sensor-name = "tsens_tz_sensor7"; + qcom,scaling-factor = <10>; + }; + sensor_information8: qcom,sensor-information-8 { + qcom,sensor-type = "tsens"; + qcom,sensor-name = "tsens_tz_sensor8"; + qcom,scaling-factor = <10>; + }; + sensor_information9: qcom,sensor-information-9 { + qcom,sensor-type = "tsens"; + qcom,sensor-name = "tsens_tz_sensor9"; + qcom,scaling-factor = <10>; + }; + sensor_information10: qcom,sensor-information-10 { + qcom,sensor-type = "tsens"; + qcom,sensor-name = "tsens_tz_sensor10"; + qcom,scaling-factor = <10>; + }; + sensor_information11: qcom,sensor-information-11 { + qcom,sensor-type = "tsens"; + qcom,sensor-name = "tsens_tz_sensor11"; + qcom,scaling-factor = <10>; + }; + sensor_information12: qcom,sensor-information-12 { + qcom,sensor-type = "tsens"; + qcom,sensor-name = "tsens_tz_sensor12"; + qcom,scaling-factor = <10>; + qcom,alias-name = "gpu_1"; + }; + sensor_information13: qcom,sensor-information-13 { + qcom,sensor-type = "tsens"; + qcom,sensor-name = "tsens_tz_sensor13"; + qcom,scaling-factor = <10>; + qcom,alias-name = "gpu"; + }; + sensor_information14: qcom,sensor-information-14 { + qcom,sensor-type = "tsens"; + qcom,sensor-name = "tsens_tz_sensor14"; + qcom,scaling-factor = <10>; + }; + sensor_information15: qcom,sensor-information-15 { + qcom,sensor-type = "tsens"; + qcom,sensor-name = "tsens_tz_sensor15"; + qcom,scaling-factor = <10>; + qcom,alias-name = "modem_dsp"; + }; + sensor_information16: qcom,sensor-information-16 { + qcom,sensor-type = "tsens"; + qcom,sensor-name = "tsens_tz_sensor16"; + qcom,scaling-factor = <10>; + }; + sensor_information17: qcom,sensor-information-17 { + qcom,sensor-type = "tsens"; + qcom,sensor-name = "tsens_tz_sensor17"; + qcom,scaling-factor = <10>; + qcom,alias-name = "hvx"; + }; + sensor_information18: qcom,sensor-information-18 { + qcom,sensor-type = "tsens"; + qcom,sensor-name = "tsens_tz_sensor18"; + qcom,scaling-factor = <10>; + qcom,alias-name = "camera"; + }; + sensor_information19: qcom,sensor-information-19 { + qcom,sensor-type = "tsens"; + qcom,sensor-name = "tsens_tz_sensor19"; + qcom,scaling-factor = <10>; + qcom,alias-name = "multi_media_ss"; + }; + sensor_information20: qcom,sensor-information-20 { + qcom,sensor-type = "tsens"; + qcom,sensor-name = "tsens_tz_sensor20"; + qcom,scaling-factor = <10>; + qcom,alias-name = "modem"; + }; + sensor_information21: qcom,sensor-information-21 { + qcom,sensor-type = "tsens"; + qcom,sensor-name = "tsens_tz_sensor21"; + qcom,scaling-factor = <10>; + qcom,alias-name = "pop_mem"; + }; + sensor_information22: qcom,sensor-information-22 { + qcom,sensor-type = "alarm"; + qcom,sensor-name = "pm8998_tz"; + qcom,scaling-factor = <1000>; + }; + sensor_information23: qcom,sensor-information-23 { + qcom,sensor-type = "adc"; + qcom,sensor-name = "msm_therm"; + }; + sensor_information24: qcom,sensor-information-24 { + qcom,sensor-type = "adc"; + qcom,sensor-name = "emmc_therm"; + }; + sensor_information25: qcom,sensor-information-25 { + qcom,sensor-type = "adc"; + qcom,sensor-name = "pa_therm0"; + }; + sensor_information26: qcom,sensor-information-26 { + qcom,sensor-type = "adc"; + qcom,sensor-name = "pa_therm1"; + }; + sensor_information27: qcom,sensor-information-27 { + qcom,sensor-type = "adc"; + qcom,sensor-name = "quiet_therm"; + }; + sensor_information28: qcom,sensor-information-28 { + qcom,sensor-type = "llm"; + qcom,sensor-name = "limits_sensor-01"; + }; + sensor_information29: qcom,sensor-information-29 { + qcom,sensor-type = "llm"; + qcom,sensor-name = "limits_sensor-02"; + }; + }; + + qcom_seecom: qseecom@86600000 { + compatible = "qcom,qseecom"; + reg = <0x86600000 0x2200000>; + reg-names = "secapp-region"; + qcom,hlos-num-ce-hw-instances = <1>; + qcom,hlos-ce-hw-instance = <0>; + qcom,qsee-ce-hw-instance = <0>; + qcom,disk-encrypt-pipe-pair = <2>; + qcom,support-fde; + qcom,no-clock-support; + qcom,appsbl-qseecom-support; + qcom,fde-key-size; + qcom,commonlib64-loaded-by-uefi; + qcom,msm-bus,name = "qseecom-noc"; + qcom,msm-bus,num-cases = <4>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <55 512 0 0>, + <55 512 0 0>, + <55 512 120000 1200000>, + <55 512 393600 3936000>; + clock-names = "core_clk_src", "core_clk", + "iface_clk", "bus_clk"; + clocks = <&clock_gcc clk_ce1_clk>, + <&clock_gcc clk_qseecom_ce1_clk>, + <&clock_gcc clk_gcc_ce1_ahb_m_clk>, + <&clock_gcc clk_gcc_ce1_axi_m_clk>; + qcom,ce-opp-freq = <171430000>; + qcom,qsee-reentrancy-support = <2>; + }; + + qcom_tzlog: tz-log@146BF720 { + compatible = "qcom,tz-log"; + reg = <0x146BF720 0x3000>; + qcom,hyplog-enabled; + hyplog-address-offset = <0x410>; /* 0x066BFB30 */ + hyplog-size-offset = <0x414>; /* 0x066BFB34 */ + }; + + qcom_msmhdcp: qcom,msm_hdcp { + compatible = "qcom,msm-hdcp"; + }; + + qcom_crypto: qcrypto@1DE0000 { + compatible = "qcom,qcrypto"; + reg = <0x1DE0000 0x20000>, + <0x1DC4000 0x24000>; + reg-names = "crypto-base","crypto-bam-base"; + interrupts = <0 206 0>; + qcom,bam-pipe-pair = <2>; + qcom,ce-hw-instance = <0>; + qcom,ce-device = <0>; + qcom,bam-ee = <0>; + qcom,ce-hw-shared; + qcom,clk-mgmt-sus-res; + qcom,msm-bus,name = "qcrypto-noc"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <55 512 0 0>, + <55 512 3936000 393600>; + clock-names = "core_clk_src", "core_clk", + "iface_clk", "bus_clk"; + clocks = <&clock_gcc clk_qcrypto_ce1_clk>, + <&clock_gcc clk_qcrypto_ce1_clk>, + <&clock_gcc clk_gcc_ce1_ahb_m_clk>, + <&clock_gcc clk_gcc_ce1_axi_m_clk>; + qcom,ce-opp-freq = <171430000>; + qcom,use-sw-aes-cbc-ecb-ctr-algo; + qcom,use-sw-aes-xts-algo; + qcom,use-sw-aes-ccm-algo; + qcom,use-sw-ahash-algo; + qcom,use-sw-aead-algo; + qcom,use-sw-hmac-algo; + }; + + qcom_cedev: qcedev@1DE0000{ + compatible = "qcom,qcedev"; + reg = <0x1DE0000 0x20000>, + <0x1DC4000 0x24000>; + reg-names = "crypto-base","crypto-bam-base"; + interrupts = <0 206 0>; + qcom,bam-pipe-pair = <1>; + qcom,ce-hw-instance = <0>; + qcom,ce-device = <0>; + qcom,ce-hw-shared; + qcom,bam-ee = <0>; + qcom,msm-bus,name = "qcedev-noc"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <55 512 0 0>, + <55 512 3936000 393600>; + clock-names = "core_clk_src", "core_clk", + "iface_clk", "bus_clk"; + clocks = <&clock_gcc clk_qcedev_ce1_clk>, + <&clock_gcc clk_qcedev_ce1_clk>, + <&clock_gcc clk_gcc_ce1_ahb_m_clk>, + <&clock_gcc clk_gcc_ce1_axi_m_clk>; + qcom,ce-opp-freq = <171430000>; + }; + + qcom_rng: qrng@793000 { + compatible = "qcom,msm-rng"; + reg = <0x793000 0x1000>; + qcom,msm-rng-iface-clk; + qcom,no-qrng-config; + qcom,msm-bus,name = "msm-rng-noc"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <1 618 0 0>, /* No vote */ + <1 618 0 800>; /* 100 MB/s */ + clocks = <&clock_gcc clk_gcc_prng_ahb_clk>; + clock-names = "iface_clk"; + }; + + mitigation_profile0: qcom,limit_info-0 { + qcom,temperature-sensor = <&sensor_information1>; + qcom,hotplug-mitigation-enable; + }; + + mitigation_profile1: qcom,limit_info-1 { + qcom,temperature-sensor = <&sensor_information2>; + qcom,hotplug-mitigation-enable; + }; + + mitigation_profile2: qcom,limit_info-2 { + qcom,temperature-sensor = <&sensor_information3>; + qcom,hotplug-mitigation-enable; + }; + + mitigation_profile3: qcom,limit_info-3 { + qcom,temperature-sensor = <&sensor_information4>; + qcom,hotplug-mitigation-enable; + }; + + mitigation_profile4: qcom,limit_info-4 { + qcom,temperature-sensor = <&sensor_information7>; + qcom,hotplug-mitigation-enable; + }; + + mitigation_profile5: qcom,limit_info-5 { + qcom,temperature-sensor = <&sensor_information8>; + qcom,hotplug-mitigation-enable; + }; + + mitigation_profile6: qcom,limit_info-6 { + qcom,temperature-sensor = <&sensor_information9>; + qcom,hotplug-mitigation-enable; + }; + + mitigation_profile7: qcom,limit_info-7 { + qcom,temperature-sensor = <&sensor_information10>; + qcom,hotplug-mitigation-enable; + }; + + qcom,lmh { + compatible = "qcom,lmh_v1"; + interrupts = ; + }; + + qcom,msm-thermal { + compatible = "qcom,msm-thermal"; + qcom,sensor-id = <1>; + qcom,poll-ms = <100>; + qcom,therm-reset-temp = <115>; + qcom,core-limit-temp = <90>; + qcom,core-temp-hysteresis = <10>; + qcom,hotplug-temp = <105>; + qcom,hotplug-temp-hysteresis = <20>; + qcom,online-hotplug-core; + qcom,synchronous-cluster-id = <0 1>; + qcom,synchronous-cluster-map = <0 4 &CPU0 &CPU1 &CPU2 &CPU3>, + <1 4 &CPU4 &CPU5 &CPU6 &CPU7>; + clock-names = "osm"; + clocks = <&clock_cpu clk_pwrcl_clk>; + + qcom,vdd-restriction-temp = <5>; + qcom,vdd-restriction-temp-hysteresis = <10>; + + vdd-dig-supply = <&pm8998_s1_floor_level>; + vdd-gfx-supply = <&gfx_vreg>; + + qcom,vdd-dig-rstr{ + qcom,vdd-rstr-reg = "vdd-dig"; + qcom,levels = ; + /* Nominal, Super Turbo, Super Turbo */ + qcom,min-level = ; + /* No Request */ + }; + + qcom,vdd-gfx-rstr{ + qcom,vdd-rstr-reg = "vdd-gfx"; + qcom,levels = <5 6 6>; /* Nominal, Turbo, Turbo */ + qcom,min-level = <1>; /* No Request */ + }; + + msm_thermal_freq: qcom,vdd-apps-rstr{ + qcom,vdd-rstr-reg = "vdd-apps"; + qcom,levels = <1248000>; + qcom,freq-req; + }; + }; + + pcie0: qcom,pcie@01c00000 { + compatible = "qcom,pci-msm"; + cell-index = <0>; + + reg = <0x1c00000 0x2000>, + <0x1c06000 0x1000>, + <0x1b000000 0xf1d>, + <0x1b000f20 0xa8>, + <0x1b100000 0x100000>, + <0x1b200000 0x100000>, + <0x1b300000 0xd00000>; + + reg-names = "parf", "phy", "dm_core", "elbi", + "conf", "io", "bars"; + + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x01000000 0x0 0x1b200000 0x1b200000 0x0 0x100000>, + <0x02000000 0x0 0x1b300000 0x1b300000 0x0 0xd00000>; + interrupt-parent = <&pcie0>; + interrupts = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 + 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 + 36 37>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0xffffffff>; + interrupt-map = <0 0 0 0 &intc 0 0 405 0 + 0 0 0 1 &intc 0 0 135 0 + 0 0 0 2 &intc 0 0 136 0 + 0 0 0 3 &intc 0 0 138 0 + 0 0 0 4 &intc 0 0 139 0 + 0 0 0 5 &intc 0 0 278 0 + 0 0 0 6 &intc 0 0 576 0 + 0 0 0 7 &intc 0 0 577 0 + 0 0 0 8 &intc 0 0 578 0 + 0 0 0 9 &intc 0 0 579 0 + 0 0 0 10 &intc 0 0 580 0 + 0 0 0 11 &intc 0 0 581 0 + 0 0 0 12 &intc 0 0 582 0 + 0 0 0 13 &intc 0 0 583 0 + 0 0 0 14 &intc 0 0 584 0 + 0 0 0 15 &intc 0 0 585 0 + 0 0 0 16 &intc 0 0 586 0 + 0 0 0 17 &intc 0 0 587 0 + 0 0 0 18 &intc 0 0 588 0 + 0 0 0 19 &intc 0 0 589 0 + 0 0 0 20 &intc 0 0 590 0 + 0 0 0 21 &intc 0 0 591 0 + 0 0 0 22 &intc 0 0 592 0 + 0 0 0 23 &intc 0 0 593 0 + 0 0 0 24 &intc 0 0 594 0 + 0 0 0 25 &intc 0 0 595 0 + 0 0 0 26 &intc 0 0 596 0 + 0 0 0 27 &intc 0 0 597 0 + 0 0 0 28 &intc 0 0 598 0 + 0 0 0 29 &intc 0 0 599 0 + 0 0 0 30 &intc 0 0 600 0 + 0 0 0 31 &intc 0 0 601 0 + 0 0 0 32 &intc 0 0 602 0 + 0 0 0 33 &intc 0 0 603 0 + 0 0 0 34 &intc 0 0 604 0 + 0 0 0 35 &intc 0 0 605 0 + 0 0 0 36 &intc 0 0 606 0 + 0 0 0 37 &intc 0 0 607 0>; + + interrupt-names = "int_msi", "int_a", "int_b", "int_c", + "int_d", "int_global_int", + "msi_0", "msi_1", "msi_2", "msi_3", + "msi_4", "msi_5", "msi_6", "msi_7", + "msi_8", "msi_9", "msi_10", "msi_11", + "msi_12", "msi_13", "msi_14", "msi_15", + "msi_16", "msi_17", "msi_18", "msi_19", + "msi_20", "msi_21", "msi_22", "msi_23", + "msi_24", "msi_25", "msi_26", "msi_27", + "msi_28", "msi_29", "msi_30", "msi_31"; + + qcom,phy-sequence = <0x804 0x01 0x00 + 0x034 0x14 0x00 + 0x138 0x30 0x00 + 0x048 0x0f 0x00 + 0x15c 0x06 0x00 + 0x090 0x01 0x00 + 0x088 0x20 0x00 + 0x0f0 0x00 0x00 + 0x0f8 0x01 0x00 + 0x0f4 0xc9 0x00 + 0x11c 0xff 0x00 + 0x120 0x3f 0x00 + 0x164 0x01 0x00 + 0x154 0x00 0x00 + 0x148 0x0a 0x00 + 0x05C 0x19 0x00 + 0x038 0x90 0x00 + 0x0b0 0x82 0x00 + 0x0c0 0x03 0x00 + 0x0bc 0x55 0x00 + 0x0b8 0x55 0x00 + 0x0a0 0x00 0x00 + 0x09c 0x0d 0x00 + 0x098 0x04 0x00 + 0x13c 0x00 0x00 + 0x060 0x08 0x00 + 0x068 0x16 0x00 + 0x070 0x34 0x00 + 0x15c 0x06 0x00 + 0x138 0x33 0x00 + 0x03c 0x02 0x00 + 0x040 0x0e 0x00 + 0x080 0x04 0x00 + 0x0dc 0x00 0x00 + 0x0d8 0x3f 0x00 + 0x00c 0x09 0x00 + 0x010 0x01 0x00 + 0x01c 0x40 0x00 + 0x020 0x01 0x00 + 0x014 0x02 0x00 + 0x018 0x00 0x00 + 0x024 0x7e 0x00 + 0x028 0x15 0x00 + 0x244 0x02 0x00 + 0x2a4 0x12 0x00 + 0x260 0x10 0x00 + 0x28c 0x06 0x00 + 0x504 0x03 0x00 + 0x500 0x10 0x00 + 0x50c 0x14 0x00 + 0x4d4 0x0a 0x00 + 0x4d8 0x04 0x00 + 0x4dc 0x1a 0x00 + 0x434 0x4b 0x00 + 0x414 0x04 0x00 + 0x40c 0x04 0x00 + 0x4f8 0x00 0x00 + 0x4fc 0x80 0x00 + 0x51c 0x40 0x00 + 0x444 0x71 0x00 + 0x43c 0x40 0x00 + 0x854 0x04 0x00 + 0x62c 0x52 0x00 + 0x9ac 0x00 0x00 + 0x8a0 0x01 0x00 + 0x9e0 0x00 0x00 + 0x9dc 0x20 0x00 + 0x9a8 0x00 0x00 + 0x8a4 0x01 0x00 + 0x8a8 0x73 0x00 + 0x9d8 0xaa 0x00 + 0x9b0 0x03 0x00 + 0x804 0x03 0x00 + 0x800 0x00 0x00 + 0x808 0x03 0x00>; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pcie0_clkreq_default + &pcie0_perst_default + &pcie0_wake_default>; + pinctrl-1 = <&pcie0_clkreq_default + &pcie0_perst_default + &pcie0_wake_sleep>; + + perst-gpio = <&tlmm 35 0>; + wake-gpio = <&tlmm 37 0>; + + gdsc-vdd-supply = <&gdsc_pcie_0>; + vreg-1.8-supply = <&pm8998_l2>; + vreg-0.9-supply = <&pm8998_l1>; + vreg-cx-supply = <&pm8998_s1_level>; + + qcom,vreg-1.8-voltage-level = <1200000 1200000 24000>; + qcom,vreg-0.9-voltage-level = <880000 880000 24000>; + qcom,vreg-cx-voltage-level = ; + + qcom,l1-supported; + qcom,l1ss-supported; + qcom,aux-clk-sync; + + qcom,ep-latency = <10>; + + qcom,boot-option = <0x1>; + + linux,pci-domain = <0>; + + qcom,msi-gicm-addr = <0x17a00040>; + qcom,msi-gicm-base = <0x260>; + + qcom,pcie-phy-ver = <0x20>; + qcom,use-19p2mhz-aux-clk; + + iommus = <&anoc1_smmu>; + qcom,smmu-exist; + qcom,smmu-sid-base = <0x1480>; + + qcom,msm-bus,name = "pcie0"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <45 512 0 0>, + <45 512 500 800>; + + clocks = <&clock_gcc clk_gcc_pcie_0_pipe_clk>, + <&clock_gcc clk_ln_bb_clk1>, + <&clock_gcc clk_gcc_pcie_0_aux_clk>, + <&clock_gcc clk_gcc_pcie_0_cfg_ahb_clk>, + <&clock_gcc clk_gcc_pcie_0_mstr_axi_clk>, + <&clock_gcc clk_gcc_pcie_0_slv_axi_clk>, + <&clock_gcc clk_gcc_pcie_clkref_clk>; + + clock-names = "pcie_0_pipe_clk", "pcie_0_ref_clk_src", + "pcie_0_aux_clk", "pcie_0_cfg_ahb_clk", + "pcie_0_mstr_axi_clk", "pcie_0_slv_axi_clk", + "pcie_0_ldo"; + + max-clock-frequency-hz = <0>, <0>, <19200000>, + <0>, <0>, <0>, <0>, <0>, <0>, + <0>, <0>, <0>, <0>, <0>, <0>, + <0>, <0>; + + resets = <&clock_gcc PCIE_PHY_BCR>, + <&clock_gcc PCIE_0_PHY_BCR>, + <&clock_gcc PCIE_0_PHY_BCR>; + + reset-names = "pcie_phy_reset", + "pcie_0_phy_reset", + "pcie_0_phy_pipe_reset"; + }; + + qcom,bcl { + compatible = "qcom,bcl"; + qcom,bcl-enable; + qcom,bcl-framework-interface; + qcom,bcl-freq-control-list = <&CPU4 &CPU5 &CPU6 &CPU7>; + qcom,bcl-hotplug-list = <&CPU4 &CPU5 &CPU6 &CPU7>; + qcom,bcl-soc-hotplug-list = <&CPU4 &CPU5 &CPU6 &CPU7>; + qcom,ibat-monitor { + qcom,low-threshold-uamp = <3400000>; + qcom,high-threshold-uamp = <4200000>; + qcom,mitigation-freq-khz = <576000>; + qcom,vph-high-threshold-uv = <3500000>; + qcom,vph-low-threshold-uv = <3300000>; + qcom,soc-low-threshold = <10>; + qcom,thermal-handle = <&msm_thermal_freq>; + }; + }; + + qcom,ssc@5c00000 { + compatible = "qcom,pil-tz-generic"; + reg = <0x5c00000 0x4000>; + interrupts = <0 390 1>; + + vdd_cx-supply = <&pm8998_l27_level>; + vdd_px-supply = <&pm8998_lvs2>; + qcom,vdd_cx-uV-uA = ; + qcom,proxy-reg-names = "vdd_cx", "vdd_px"; + qcom,keep-proxy-regs-on; + + clocks = <&clock_gcc clk_cxo_pil_ssc_clk>, + <&clock_gcc clk_aggre2_noc_clk>; + clock-names = "xo", "aggre2"; + qcom,proxy-clock-names = "xo", "aggre2"; + + qcom,pas-id = <12>; + qcom,proxy-timeout-ms = <10000>; + qcom,smem-id = <424>; + qcom,sysmon-id = <3>; + qcom,ssctl-instance-id = <0x16>; + qcom,firmware-name = "slpi"; + status = "ok"; + memory-region = <&pil_slpi_mem>; + + /* GPIO inputs from ssc */ + qcom,gpio-err-fatal = <&smp2pgpio_ssr_smp2p_3_in 0 0>; + qcom,gpio-proxy-unvote = <&smp2pgpio_ssr_smp2p_3_in 2 0>; + qcom,gpio-err-ready = <&smp2pgpio_ssr_smp2p_3_in 1 0>; + qcom,gpio-stop-ack = <&smp2pgpio_ssr_smp2p_3_in 3 0>; + + /* GPIO output to ssc */ + qcom,gpio-force-stop = <&smp2pgpio_ssr_smp2p_3_out 0 0>; + }; + + qcom,venus@cce0000 { + compatible = "qcom,pil-tz-generic"; + reg = <0xcce0000 0x4000>; + + vdd-supply = <&gdsc_venus>; + qcom,proxy-reg-names = "vdd"; + + clocks = <&clock_mmss clk_mmss_video_core_clk>, + <&clock_mmss clk_mmss_mnoc_ahb_clk>, + <&clock_mmss clk_mmss_video_ahb_clk>, + <&clock_gcc clk_mmssnoc_axi_clk>, + <&clock_mmss clk_mmss_video_axi_clk>, + <&clock_mmss clk_mmss_video_maxi_clk>; + clock-names = "core_clk", "mnoc_ahb_clk", "iface_clk", + "noc_axi_clk", "bus_clk", "maxi_clk"; + qcom,proxy-clock-names = "core_clk","mnoc_ahb_clk", + "iface_clk", "noc_axi_clk", "bus_clk", "maxi_clk"; + + qcom,pas-id = <9>; + qcom,msm-bus,name = "pil-venus"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <63 512 0 0>, + <63 512 0 304000>; + qcom,proxy-timeout-ms = <100>; + qcom,firmware-name = "venus"; + memory-region = <&pil_video_mem>; + status = "ok"; + }; + + wdog: qcom,wdt@17817000 { + compatible = "qcom,msm-watchdog"; + reg = <0x17817000 0x1000>; + reg-names = "wdt-base"; + interrupts = <0 3 0>, <0 4 0>; + qcom,bark-time = <11000>; + qcom,pet-time = <10000>; + qcom,ipi-ping; + qcom,wakeup-enable; + qcom,scandump-size = <0x40000>; + }; + + qcom,spss@1d00000 { + compatible = "qcom,pil-tz-generic"; + reg = <0x1d0101c 0x4>, + <0x1d01024 0x4>, + <0x1d01028 0x4>, + <0x1d0103c 0x4>, + <0x1d02030 0x4>; + reg-names = "sp2soc_irq_status", "sp2soc_irq_clr", + "sp2soc_irq_mask", "rmb_err", "rmb_err_spare2"; + interrupts = <0 352 1>; + + vdd_cx-supply = <&pm8998_s1_level>; + qcom,proxy-reg-names = "vdd_cx"; + qcom,vdd_cx-uV-uA = ; + + clocks = <&clock_gcc clk_cxo_pil_spss_clk>; + clock-names = "xo"; + qcom,proxy-clock-names = "xo"; + qcom,pil-generic-irq-handler; + status = "ok"; + + qcom,pas-id = <14>; + qcom,proxy-timeout-ms = <10000>; + qcom,firmware-name = "spss"; + memory-region = <&spss_mem>; + qcom,spss-scsr-bits = <24 25>; + }; + + qcom,msm-rtb { + compatible = "qcom,msm-rtb"; + qcom,rtb-size = <0x100000>; + }; + + qcom,mpm2-sleep-counter@10a3000 { + compatible = "qcom,mpm2-sleep-counter"; + reg = <0x010a3000 0x1000>; + clock-frequency = <32768>; + }; + + qcom,msm-imem@146bf000 { + compatible = "qcom,msm-imem"; + reg = <0x146bf000 0x1000>; + ranges = <0x0 0x146bf000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + + mem_dump_table@10 { + compatible = "qcom,msm-imem-mem_dump_table"; + reg = <0x10 8>; + }; + + dload_type@18 { + compatible = "qcom,msm-imem-dload-type"; + reg = <0x18 4>; + }; + + restart_reason@65c { + compatible = "qcom,msm-imem-restart_reason"; + reg = <0x65c 4>; + }; + + boot_stats@6b0 { + compatible = "qcom,msm-imem-boot_stats"; + reg = <0x6b0 32>; + }; + + kaslr_offset@6d0 { + compatible = "qcom,msm-imem-kaslr_offset"; + reg = <0x6d0 12>; + }; + + pil@94c { + compatible = "qcom,msm-imem-pil"; + reg = <0x94c 200>; + }; + + diag_dload@c8 { + compatible = "qcom,msm-imem-diag-dload"; + reg = <0xc8 200>; + }; + }; + + cpu_pmu: cpu-pmu { + compatible = "arm,armv8-pmuv3"; + qcom,irq-is-percpu; + interrupts = <1 6 4>; + }; + + cpuss_dump { + compatible = "qcom,cpuss-dump"; + qcom,l1_i_cache0 { + qcom,dump-node = <&L1_I_0>; + qcom,dump-id = <0x60>; + }; + qcom,l1_i_cache1 { + qcom,dump-node = <&L1_I_1>; + qcom,dump-id = <0x61>; + }; + qcom,l1_i_cache2 { + qcom,dump-node = <&L1_I_2>; + qcom,dump-id = <0x62>; + }; + qcom,l1_i_cache3 { + qcom,dump-node = <&L1_I_3>; + qcom,dump-id = <0x63>; + }; + qcom,l1_i_cache100 { + qcom,dump-node = <&L1_I_100>; + qcom,dump-id = <0x64>; + }; + qcom,l1_i_cache101 { + qcom,dump-node = <&L1_I_101>; + qcom,dump-id = <0x65>; + }; + qcom,l1_i_cache102 { + qcom,dump-node = <&L1_I_102>; + qcom,dump-id = <0x66>; + }; + qcom,l1_i_cache103 { + qcom,dump-node = <&L1_I_103>; + qcom,dump-id = <0x67>; + }; + qcom,l1_d_cache0 { + qcom,dump-node = <&L1_D_0>; + qcom,dump-id = <0x80>; + }; + qcom,l1_d_cache1 { + qcom,dump-node = <&L1_D_1>; + qcom,dump-id = <0x81>; + }; + qcom,l1_d_cache2 { + qcom,dump-node = <&L1_D_2>; + qcom,dump-id = <0x82>; + }; + qcom,l1_d_cache3 { + qcom,dump-node = <&L1_D_3>; + qcom,dump-id = <0x83>; + }; + qcom,l1_d_cache100 { + qcom,dump-node = <&L1_D_100>; + qcom,dump-id = <0x84>; + }; + qcom,l1_d_cache101 { + qcom,dump-node = <&L1_D_101>; + qcom,dump-id = <0x85>; + }; + qcom,l1_d_cache102 { + qcom,dump-node = <&L1_D_102>; + qcom,dump-id = <0x86>; + }; + qcom,l1_d_cache103 { + qcom,dump-node = <&L1_D_103>; + qcom,dump-id = <0x87>; + }; + qcom,l1_tlb_dump0 { + qcom,dump-node = <&L1_TLB_0>; + qcom,dump-id = <0x20>; + }; + qcom,l1_tlb_dump1 { + qcom,dump-node = <&L1_TLB_1>; + qcom,dump-id = <0x21>; + }; + qcom,l1_tlb_dump2 { + qcom,dump-node = <&L1_TLB_2>; + qcom,dump-id = <0x22>; + }; + qcom,l1_tlb_dump3 { + qcom,dump-node = <&L1_TLB_3>; + qcom,dump-id = <0x23>; + }; + qcom,l1_tlb_dump100 { + qcom,dump-node = <&L1_TLB_100>; + qcom,dump-id = <0x24>; + }; + qcom,l1_tlb_dump101 { + qcom,dump-node = <&L1_TLB_101>; + qcom,dump-id = <0x25>; + }; + qcom,l1_tlb_dump102 { + qcom,dump-node = <&L1_TLB_102>; + qcom,dump-id = <0x26>; + }; + qcom,l1_tlb_dump103 { + qcom,dump-node = <&L1_TLB_103>; + qcom,dump-id = <0x27>; + }; + }; + + ssc_sensors: qcom,msm-ssc-sensors { + compatible = "qcom,msm-ssc-sensors"; + status = "ok"; + qcom,firmware-name = "slpi_v1"; + }; + + dcc: dcc@10b3000 { + compatible = "qcom,dcc"; + reg = <0x10b3000 0x1000>, + <0x10b4000 0x2000>; + reg-names = "dcc-base", "dcc-ram-base"; + + clocks = <&clock_gcc clk_gcc_dcc_ahb_clk>; + clock-names = "dcc_clk"; + }; + + qcom,msm-core@780000 { + compatible = "qcom,apss-core-ea"; + reg = <0x780000 0x1000>; + qcom,low-hyst-temp = <100>; + qcom,high-hyst-temp = <100>; + qcom,polling-interval = <50>; + + ea0: ea0 { + sensor = <&sensor_information1>; + }; + + ea1: ea1 { + sensor = <&sensor_information2>; + }; + + ea2: ea2 { + sensor = <&sensor_information3>; + }; + + ea3: ea3 { + sensor = <&sensor_information4>; + }; + + ea4: ea4 { + sensor = <&sensor_information7>; + }; + + ea5: ea5 { + sensor = <&sensor_information8>; + }; + + ea6: ea6 { + sensor = <&sensor_information9>; + }; + + ea7: ea7 { + sensor = <&sensor_information10>; + }; + + }; + + msm_ath10k_wlan: qcom,msm_ath10k_wlan { + status = "disabled"; + compatible = "qcom,wcn3990-wifi"; + reg = <0x18800000 0x800000>; + reg-names = "membase"; + clocks = <&clock_gcc clk_rf_clk2_pin>; + clock-names = "cxo_ref_clk_pin"; + interrupts = + <0 413 0 /* CE0 */ >, + <0 414 0 /* CE1 */ >, + <0 415 0 /* CE2 */ >, + <0 416 0 /* CE3 */ >, + <0 417 0 /* CE4 */ >, + <0 418 0 /* CE5 */ >, + <0 420 0 /* CE6 */ >, + <0 421 0 /* CE7 */ >, + <0 422 0 /* CE8 */ >, + <0 423 0 /* CE9 */ >, + <0 424 0 /* CE10 */ >, + <0 425 0 /* CE11 */ >; + vdd-0.8-cx-mx-supply = <&pm8998_l5>; + vdd-1.8-xo-supply = <&pm8998_l7_pin_ctrl>; + vdd-1.3-rfa-supply = <&pm8998_l17_pin_ctrl>; + vdd-3.3-ch0-supply = <&pm8998_l25_pin_ctrl>; + qcom,vdd-0.8-cx-mx-config = <800000 800000>; + qcom,vdd-3.3-ch0-config = <3104000 3312000>; + }; + + qcom,icnss@18800000 { + compatible = "qcom,icnss"; + reg = <0x18800000 0x800000>, + <0xa0000000 0x10000000>, + <0xb0000000 0x10000>; + reg-names = "membase", "smmu_iova_base", "smmu_iova_ipa"; + clocks = <&clock_gcc clk_rf_clk2_pin>; + clock-names = "cxo_ref_clk_pin"; + iommus = <&anoc2_smmu 0x1900>, + <&anoc2_smmu 0x1901>; + interrupts = <0 413 0 /* CE0 */ >, + <0 414 0 /* CE1 */ >, + <0 415 0 /* CE2 */ >, + <0 416 0 /* CE3 */ >, + <0 417 0 /* CE4 */ >, + <0 418 0 /* CE5 */ >, + <0 420 0 /* CE6 */ >, + <0 421 0 /* CE7 */ >, + <0 422 0 /* CE8 */ >, + <0 423 0 /* CE9 */ >, + <0 424 0 /* CE10 */ >, + <0 425 0 /* CE11 */ >; + qcom,wlan-msa-memory = <0x100000>; + vdd-0.8-cx-mx-supply = <&pm8998_l5>; + vdd-1.8-xo-supply = <&pm8998_l7_pin_ctrl>; + vdd-1.3-rfa-supply = <&pm8998_l17_pin_ctrl>; + vdd-3.3-ch0-supply = <&pm8998_l25_pin_ctrl>; + qcom,vdd-0.8-cx-mx-config = <800000 800000>; + qcom,vdd-3.3-ch0-config = <3104000 3312000>; + qcom,icnss-vadc = <&pm8998_vadc>; + qcom,icnss-adc_tm = <&pm8998_adc_tm>; + }; + + tspp: msm_tspp@0c1e7000 { + compatible = "qcom,msm_tspp"; + reg = <0x0c1e7000 0x200>, /* MSM_TSIF0_PHYS */ + <0x0c1e8000 0x200>, /* MSM_TSIF1_PHYS */ + <0x0c1e9000 0x1000>, /* MSM_TSPP_PHYS */ + <0x0c1c4000 0x23000>; /* MSM_TSPP_BAM_PHYS */ + reg-names = "MSM_TSIF0_PHYS", + "MSM_TSIF1_PHYS", + "MSM_TSPP_PHYS", + "MSM_TSPP_BAM_PHYS"; + interrupts = <0 121 0>, /* TSIF_TSPP_IRQ */ + <0 119 0>, /* TSIF0_IRQ */ + <0 120 0>, /* TSIF1_IRQ */ + <0 122 0>; /* TSIF_BAM_IRQ */ + interrupt-names = "TSIF_TSPP_IRQ", + "TSIF0_IRQ", + "TSIF1_IRQ", + "TSIF_BAM_IRQ"; + + clock-names = "iface_clk", "ref_clk"; + clocks = <&clock_gcc clk_gcc_tsif_ahb_clk>, + <&clock_gcc clk_gcc_tsif_ref_clk>; + + qcom,msm-bus,name = "tsif"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <82 512 0 0>, /* No vote */ + <82 512 12288 24576>; + /* Max. bandwidth, 2xTSIF, each max of 96Mbps */ + + pinctrl-names = "disabled", + "tsif0-mode1", "tsif0-mode2", + "tsif1-mode1", "tsif1-mode2", + "dual-tsif-mode1", "dual-tsif-mode2"; + + pinctrl-0 = <>; /* disabled */ + pinctrl-1 = <&tsif0_signals_active>; /* tsif0-mode1 */ + pinctrl-2 = <&tsif0_signals_active + &tsif0_sync_active>; /* tsif0-mode2 */ + pinctrl-3 = <&tsif1_signals_active>; /* tsif1-mode1 */ + pinctrl-4 = <&tsif1_signals_active + &tsif1_sync_active>; /* tsif1-mode2 */ + pinctrl-5 = <&tsif0_signals_active + &tsif1_signals_active>; /* dual-tsif-mode1 */ + pinctrl-6 = <&tsif0_signals_active + &tsif0_sync_active + &tsif1_signals_active + &tsif1_sync_active>; /* dual-tsif-mode2 */ + }; + + wil6210: qcom,wil6210 { + status = "disabled"; + compatible = "qcom,wil6210"; + qcom,pcie-parent = <&pcie0>; + qcom,wigig-en = <&tlmm 80 0>; + qcom,msm-bus,name = "wil6210"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <45 512 0 0>, + <45 512 600000 800000>; /* ~4.6Gbps (MCS12) */ + qcom,use-ext-supply; + vdd-supply= <&pm8998_s7>; + vddio-supply= <&pm8998_s5>; + qcom,use-ext-clocks; + clocks = <&clock_gcc clk_rf_clk3>, + <&clock_gcc clk_rf_clk3_pin>; + clock-names = "rf_clk3_clk", "rf_clk3_pin_clk"; + qcom,smmu-support; + qcom,smmu-s1-en; + qcom,smmu-fast-map; + qcom,smmu-coherent; + qcom,smmu-mapping = <0x20000000 0xe0000000>; + qcom,keep-radio-on-during-sleep; + }; + + qcom,qsee_ipc_irq_bridge { + compatible = "qcom,qsee-ipc-irq-bridge"; + + qcom,qsee-ipc-irq-spss { + qcom,rx-irq-clr = <0x1d08008 0x4>; + qcom,rx-irq-clr-mask = <0x1>; + qcom,dev-name = "qsee_ipc_irq_spss"; + interrupts = <0 349 4>; + label = "spss"; + }; + }; +}; + +&clock_cpu { + lmh_dcvs0: qcom,limits-dcvs@0 { + compatible = "qcom,msm-hw-limits"; + interrupts = ; + }; + + lmh_dcvs1: qcom,limits-dcvs@1 { + compatible = "qcom,msm-hw-limits"; + interrupts = ; + }; +}; + +&gdsc_usb30 { + status = "ok"; +}; + +&gdsc_pcie_0 { + status = "ok"; +}; + +&gdsc_ufs { + status = "ok"; +}; + +&gdsc_bimc_smmu { + clock-names = "bus_clk"; + clocks = <&clock_mmss clk_mmss_bimc_smmu_axi_clk>; + proxy-supply = <&gdsc_bimc_smmu>; + qcom,proxy-consumer-enable; + status = "ok"; +}; + +&gdsc_hlos1_vote_lpass_adsp { + status = "ok"; +}; + +&gdsc_hlos1_vote_lpass_core { + status = "ok"; +}; + +&gdsc_venus { + status = "ok"; +}; + +&gdsc_venus_core0 { + status = "ok"; + qcom,support-hw-trigger; +}; + +&gdsc_venus_core1 { + status = "ok"; + qcom,support-hw-trigger; +}; + +&gdsc_camss_top { + status = "ok"; +}; + +&gdsc_vfe0 { + parent-supply = <&gdsc_camss_top>; + status = "ok"; +}; + +&gdsc_vfe1 { + parent-supply = <&gdsc_camss_top>; + status = "ok"; +}; + +&gdsc_cpp { + parent-supply = <&gdsc_camss_top>; + qcom,support-hw-trigger; + status = "ok"; +}; + +&gdsc_mdss { + proxy-supply = <&gdsc_mdss>; + qcom,proxy-consumer-enable; + status = "ok"; +}; + +&gdsc_gpu_gx { + clock-names = "core_root_clk"; + clocks = <&clock_gfx clk_gfx3d_clk_src>; + qcom,force-enable-root-clk; + parent-supply = <&gfx_vreg>; + status = "ok"; +}; + +&gdsc_gpu_cx { + status = "ok"; +}; + +#include "msm-pm8998.dtsi" +#include "msm-pmi8998.dtsi" +#include "msm-pm8005.dtsi" +#include "msm-pm8998-rpm-regulator.dtsi" +#include "msm8998-regulator.dtsi" + +#include "msm8998-pm.dtsi" +#include "msm-arm-smmu-8998.dtsi" +#include "msm-arm-smmu-impl-defs-8998.dtsi" +#include "msm8998-ion.dtsi" +#include "msm8998-camera.dtsi" +#include "msm8998-vidc.dtsi" +#include "msm8998-coresight.dtsi" +#include "msm8998-bus.dtsi" +#include "msm8998-gpu.dtsi" +#include "msm8998-pinctrl.dtsi" +#include "msm-audio-lpass.dtsi" +#include "msm8998-mdss-pll.dtsi" +#include "msm-rdbg.dtsi" +#include "msm8998-blsp.dtsi" +#include "msm8998-audio.dtsi" +#include "msm8998-sde.dtsi" diff -Nruw linux-4.4.115-fbx/arch/arm/boot/dts/qcom./msm8998-gpu.dtsi linux-4.4.115-fbx/arch/arm/boot/dts/qcom/msm8998-gpu.dtsi --- linux-4.4.115-fbx/arch/arm/boot/dts/qcom./msm8998-gpu.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ linux-4.4.115-fbx/arch/arm/boot/dts/qcom/msm8998-gpu.dtsi 2019-01-22 16:16:21.195225506 +0100 @@ -0,0 +1,277 @@ +/* Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&soc { + + pil_gpu: qcom,kgsl-hyp { + compatible = "qcom,pil-tz-generic"; + qcom,pas-id = <13>; + qcom,firmware-name = "a540_zap"; + }; + + msm_bus: qcom,kgsl-busmon{ + label = "kgsl-busmon"; + compatible = "qcom,kgsl-busmon"; + }; + + gpubw: qcom,gpubw { + compatible = "qcom,devbw"; + governor = "bw_vbif"; + qcom,src-dst-ports = <26 512>; + /* + * active-only flag is used while registering the bus + * governor.It helps release the bus vote when the CPU + * subsystem is inactiv3 + */ + qcom,active-only; + qcom,bw-tbl = + < 0 /* off */ >, + < 762 /* 100 MHz */ >, + < 1144 /* 150 MHz */ >, + < 1525 /* 200 MHz */ >, + < 2288 /* 300 MHz */ >, + < 3143 /* 412 MHz */ >, + < 4173 /* 547 MHz */ >, + < 5195 /* 681 MHz */ >, + < 5859 /* 768 MHz */ >, + < 7759 /* 1017 MHz */ >, + < 9887 /* 1296 MHz */ >, + < 11863 /* 1555 MHz */ >, + < 13763 /* 1804 MHz */ >; + }; + + msm_gpu: qcom,kgsl-3d0@5000000 { + label = "kgsl-3d0"; + compatible = "qcom,kgsl-3d0", "qcom,kgsl-3d"; + status = "ok"; + reg = <0x5000000 0x40000>; + reg-names = "kgsl_3d0_reg_memory"; + interrupts = <0 300 0>; + interrupt-names = "kgsl_3d0_irq"; + qcom,id = <0>; + + qcom,chipid = <0x05040000>; + qcom,gpu-efuse-leakage = <0x00070130 24>; + qcom,base-leakage-coefficient = <34>; + qcom,lm-limit = <6000>; + + qcom,initial-pwrlevel = <4>; + + qcom,idle-timeout = <80>; // + qcom,no-nap; + + qcom,highest-bank-bit = <15>; + + qcom,snapshot-size = <1048576>; //bytes + + qcom,gpu-qdss-stm = <0x161c0000 0x40000>; // base addr, size + + qcom,gpu-qtimer = <0x17921000 0x1000>; // base addr, size + + qcom,tsens-name = "tsens_tz_sensor12"; + + /* Avoid L2PC on big cluster CPUs (CPU 4,5,6,7) */ + qcom,l2pc-cpu-mask = <0x000000f0>; + + /* Quirks */ + qcom,gpu-quirk-lmloadkill-disable; + + /* DRM settings */ + qcom,gpmu-tsens = <0x000c000d>; + qcom,max-power = <5448>; + qcom,gpmu-firmware = "a540_gpmu.fw2"; + qcom,gpmu-version = <3 0>; + qcom,zap-shader = "a540_zap"; + + clocks = <&clock_gfx clk_gpucc_gfx3d_clk>, + <&clock_gcc clk_gcc_gpu_cfg_ahb_clk>, + <&clock_gpu clk_gpucc_rbbmtimer_clk>, + <&clock_gcc clk_gcc_bimc_gfx_clk>, + <&clock_gcc clk_gcc_gpu_bimc_gfx_clk>, + <&clock_gpu clk_gpucc_gfx3d_isense_clk>, + <&clock_gpu clk_gpucc_rbcpr_clk>, + <&clock_gcc clk_gcc_gpu_iref_clk>; + + clock-names = "core_clk", "iface_clk", "rbbmtimer_clk", + "mem_clk", "mem_iface_clk", "isense_clk", "rbcpr_clk", + "iref_clk"; + + qcom,isense-clk-on-level = <1>; + /* Bus Scale Settings */ + qcom,gpubw-dev = <&gpubw>; + qcom,bus-control; + qcom,msm-bus,name = "grp3d"; + qcom,bus-width = <32>; + qcom,msm-bus,num-cases = <13>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <26 512 0 0>, + + <26 512 0 800000>, // 1 bus=100 + <26 512 0 1200000>, // 2 bus=150 + <26 512 0 1600000>, // 3 bus=200 + <26 512 0 2400000>, // 4 bus=300 + <26 512 0 3296000>, // 5 bus=412 + <26 512 0 4376000>, // 6 bus=547 + <26 512 0 5448000>, // 7 bus=681 + <26 512 0 6144000>, // 8 bus=768 + <26 512 0 8136000>, // 9 bus=1017 + <26 512 0 10368000>, // 10 bus=1296 + <26 512 0 12440000>, // 11 bus=1555 + <26 512 0 14432000>; // 12 bus=1804 + + /* GDSC regulator names */ + regulator-names = "vddcx", "vdd"; + /* GDSC oxili regulators */ + vddcx-supply = <&gdsc_gpu_cx>; + vdd-supply = <&gdsc_gpu_gx>; + + /* Trace bus */ + coresight-name = "coresight-gfx"; + coresight-atid = <3>; + port { + gfx_out_funnel_in1: endpoint { + remote-endpoint = <&funnel_in1_in_gfx>; + }; + }; + + /* GPU Mempools */ + qcom,gpu-mempools { + #address-cells= <1>; + #size-cells = <0>; + compatible = "qcom,gpu-mempools"; + + /* 4K Page Pool configuration */ + qcom,gpu-mempool@0 { + reg = <0>; + qcom,mempool-page-size = <4096>; + qcom,mempool-reserved = <2048>; + qcom,mempool-allocate; + }; + /* 8K Page Pool configuration */ + qcom,gpu-mempool@1 { + reg = <1>; + qcom,mempool-page-size = <8192>; + qcom,mempool-reserved = <1024>; + qcom,mempool-allocate; + }; + /* 64K Page Pool configuration */ + qcom,gpu-mempool@2 { + reg = <2>; + qcom,mempool-page-size = <65536>; + qcom,mempool-reserved = <256>; + }; + /* 1M Page Pool configuration */ + qcom,gpu-mempool@3 { + reg = <3>; + qcom,mempool-page-size = <1048576>; + qcom,mempool-reserved = <32>; + }; + }; + + /* Power levels */ + qcom,gpu-pwrlevels { + #address-cells = <1>; + #size-cells = <0>; + + compatible = "qcom,gpu-pwrlevels"; + + qcom,gpu-pwrlevel@0 { + reg = <0>; + qcom,gpu-freq = <650000000>; + qcom,bus-freq = <12>; + qcom,bus-min = <11>; + qcom,bus-max = <12>; + }; + + + qcom,gpu-pwrlevel@1 { + reg = <1>; + qcom,gpu-freq = <504000000>; + qcom,bus-freq = <11>; + qcom,bus-min = <10>; + qcom,bus-max = <12>; + }; + + qcom,gpu-pwrlevel@2 { + reg = <2>; + qcom,gpu-freq = <403000000>; + qcom,bus-freq = <10>; + qcom,bus-min = <9>; + qcom,bus-max = <11>; + }; + + qcom,gpu-pwrlevel@3 { + reg = <3>; + qcom,gpu-freq = <332000000>; + qcom,bus-freq = <7>; + qcom,bus-min = <6>; + qcom,bus-max = <8>; + }; + + qcom,gpu-pwrlevel@4 { + reg = <4>; + qcom,gpu-freq = <251000000>; + qcom,bus-freq = <4>; + qcom,bus-min = <3>; + qcom,bus-max = <5>; + }; + + qcom,gpu-pwrlevel@5 { + reg = <5>; + qcom,gpu-freq = <171000000>; + qcom,bus-freq = <3>; + qcom,bus-min = <1>; + qcom,bus-max = <4>; + }; + + qcom,gpu-pwrlevel@6 { + reg = <6>; + qcom,gpu-freq = <27000000>; + qcom,bus-freq = <0>; + qcom,bus-min = <0>; + qcom,bus-max = <0>; + }; + }; + + }; + + kgsl_msm_iommu: qcom,kgsl-iommu { + compatible = "qcom,kgsl-smmu-v2"; + + reg = <0x05040000 0x10000>; + qcom,protect = <0x40000 0x10000>; + qcom,micro-mmu-control = <0x6000>; + + clocks =<&clock_gcc clk_gcc_gpu_cfg_ahb_clk>, + <&clock_gcc clk_gcc_bimc_gfx_clk>, + <&clock_gcc clk_gcc_gpu_bimc_gfx_clk>; + + clock-names = "iface_clk", "mem_clk", "mem_iface_clk"; + + qcom,secure_align_mask = <0xfff>; + qcom,retention; + qcom,hyp_secure_alloc; + + gfx3d_user: gfx3d_user { + compatible = "qcom,smmu-kgsl-cb"; + label = "gfx3d_user"; + iommus = <&kgsl_smmu 0>; + qcom,gpu-offset = <0x48000>; + }; + + gfx3d_secure: gfx3d_secure { + compatible = "qcom,smmu-kgsl-cb"; + iommus = <&kgsl_smmu 2>; + }; + }; +}; diff -Nruw linux-4.4.115-fbx/arch/arm/boot/dts/qcom./msm8998-ion.dtsi linux-4.4.115-fbx/arch/arm/boot/dts/qcom/msm8998-ion.dtsi --- linux-4.4.115-fbx/arch/arm/boot/dts/qcom./msm8998-ion.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ linux-4.4.115-fbx/arch/arm/boot/dts/qcom/msm8998-ion.dtsi 2019-01-22 16:16:21.195225506 +0100 @@ -0,0 +1,53 @@ +/* Copyright (c) 2015-2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&soc { + qcom,ion { + compatible = "qcom,msm-ion"; + #address-cells = <1>; + #size-cells = <0>; + + system_heap: qcom,ion-heap@25 { + reg = <25>; + qcom,ion-heap-type = "SYSTEM"; + }; + + qcom,ion-heap@22 { /* ADSP HEAP */ + reg = <22>; + memory-region = <&adsp_mem>; + qcom,ion-heap-type = "DMA"; + }; + + qcom,ion-heap@27 { /* QSEECOM HEAP */ + reg = <27>; + memory-region = <&qseecom_mem>; + qcom,ion-heap-type = "DMA"; + }; + + qcom,ion-heap@13 { /* SPSS HEAP */ + reg = <13>; + memory-region = <&sp_mem>; + qcom,ion-heap-type = "DMA"; + }; + + qcom,ion-heap@10 { /* SECURE DISPLAY HEAP */ + reg = <10>; + memory-region = <&secure_display_memory>; + qcom,ion-heap-type = "HYP_CMA"; + }; + + qcom,ion-heap@9 { + reg = <9>; + qcom,ion-heap-type = "SYSTEM_SECURE"; + }; + }; +}; diff -Nruw linux-4.4.115-fbx/arch/arm/boot/dts/qcom./msm8998-mdss-pll.dtsi linux-4.4.115-fbx/arch/arm/boot/dts/qcom/msm8998-mdss-pll.dtsi --- linux-4.4.115-fbx/arch/arm/boot/dts/qcom./msm8998-mdss-pll.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ linux-4.4.115-fbx/arch/arm/boot/dts/qcom/msm8998-mdss-pll.dtsi 2019-01-22 16:16:21.195225506 +0100 @@ -0,0 +1,173 @@ +/* Copyright (c) 2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&soc { + mdss_dsi0_pll: qcom,mdss_dsi_pll@c994400 { + compatible = "qcom,mdss_dsi_pll_8998"; + status = "ok"; + label = "MDSS DSI 0 PLL"; + cell-index = <0>; + #clock-cells = <1>; + + reg = <0xc994a00 0x1c0>, + <0xc994400 0x7c0>, + <0x0c8c2300 0x8>; + reg-names = "pll_base", "phy_base", "gdsc_base"; + + gdsc-supply = <&gdsc_mdss>; + + clocks = <&clock_mmss clk_mmss_mdss_ahb_clk>; + clock-names = "iface_clk"; + clock-rate = <0>; + qcom,dsi-pll-ssc-en; + qcom,dsi-pll-ssc-mode = "down-spread"; + + qcom,platform-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,platform-supply-entry@0 { + reg = <0>; + qcom,supply-name = "gdsc"; + qcom,supply-min-voltage = <0>; + qcom,supply-max-voltage = <0>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + }; + + }; + }; + + mdss_dsi1_pll: qcom,mdss_dsi_pll@c996400 { + compatible = "qcom,mdss_dsi_pll_8998"; + status = "ok"; + label = "MDSS DSI 1 PLL"; + cell-index = <1>; + #clock-cells = <1>; + + reg = <0x0c996a00 0x1c0>, + <0x0c996400 0x7c0>, + <0x008c2300 0x8>; + reg-names = "pll_base", "phy_base", "gdsc_base"; + + gdsc-supply = <&gdsc_mdss>; + + clocks = <&clock_mmss clk_mmss_mdss_ahb_clk>; + clock-names = "iface_clk"; + clock-rate = <0>; + qcom,dsi-pll-ssc-en; + qcom,dsi-pll-ssc-mode = "down-spread"; + + qcom,platform-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,platform-supply-entry@0 { + reg = <0>; + qcom,supply-name = "gdsc"; + qcom,supply-min-voltage = <0>; + qcom,supply-max-voltage = <0>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + }; + }; + }; + + mdss_dp_pll: qcom,mdss_dp_pll@c011000 { + compatible = "qcom,mdss_dp_pll_8998"; + status = "ok"; + label = "MDSS DP PLL"; + cell-index = <0>; + #clock-cells = <1>; + + reg = <0xc011c00 0x190>, + <0xc011000 0x910>, + <0x0c8c2300 0x8>; + reg-names = "pll_base", "phy_base", "gdsc_base"; + + gdsc-supply = <&gdsc_mdss>; + + clocks = <&clock_mmss clk_mmss_mdss_ahb_clk>, + <&clock_gcc clk_ln_bb_clk1>, + <&clock_gcc clk_gcc_usb3_clkref_clk>; + clock-names = "iface_clk", "ref_clk_src", "ref_clk"; + clock-rate = <0>; + + qcom,platform-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,platform-supply-entry@0 { + reg = <0>; + qcom,supply-name = "gdsc"; + qcom,supply-min-voltage = <0>; + qcom,supply-max-voltage = <0>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + }; + + }; + }; + + mdss_hdmi_pll: qcom,mdss_hdmi_pll@0xc9a0600 { + compatible = "qcom,mdss_hdmi_pll_8998"; + label = "MDSS HDMI PLL"; + cell-index = <2>; + #clock-cells = <1>; + + reg = <0xc9a0600 0xb10>, + <0xc9a1200 0x0e4>, + <0xc8c2300 0x8>; + reg-names = "pll_base", "phy_base", "gdsc_base"; + + gdsc-supply = <&gdsc_mdss>; + vdda-pll-supply = <&pm8998_l2>; + vdda-phy-supply = <&pm8998_l12>; + + clocks = <&clock_mmss clk_mmss_mdss_ahb_clk>, + <&clock_gcc clk_gcc_hdmi_clkref_clk>, + <&clock_gcc clk_ln_bb_clk1>; + clock-names = "iface_clk", "ref_clk", "ref_clk_src"; + clock-rate = <0>; + + qcom,platform-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,platform-supply-entry@0 { + reg = <0>; + qcom,supply-name = "gdsc"; + qcom,supply-min-voltage = <0>; + qcom,supply-max-voltage = <0>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + }; + qcom,platform-supply-entry@1 { + reg = <1>; + qcom,supply-name = "vdda-pll"; + qcom,supply-min-voltage = <1200000>; + qcom,supply-max-voltage = <1200000>; + qcom,supply-enable-load = <14200>; + qcom,supply-disable-load = <1>; + }; + + qcom,platform-supply-entry@2 { + reg = <2>; + qcom,supply-name = "vdda-phy"; + qcom,supply-min-voltage = <1800000>; + qcom,supply-max-voltage = <1800000>; + qcom,supply-enable-load = <13100>; + qcom,supply-disable-load = <4>; + }; + }; + }; +}; diff -Nruw linux-4.4.115-fbx/arch/arm/boot/dts/qcom./msm8998-pinctrl.dtsi linux-4.4.115-fbx/arch/arm/boot/dts/qcom/msm8998-pinctrl.dtsi --- linux-4.4.115-fbx/arch/arm/boot/dts/qcom./msm8998-pinctrl.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ linux-4.4.115-fbx/arch/arm/boot/dts/qcom/msm8998-pinctrl.dtsi 2019-01-22 16:16:21.195225506 +0100 @@ -0,0 +1,2460 @@ +/* Copyright (c) 2015-2017, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&soc { + tlmm: pinctrl@03400000 { + compatible = "qcom,msm8998-pinctrl"; + reg = <0x03400000 0xc00000>; + interrupts = <0 208 0>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + + uart_console_active: uart_console_active { + mux { + pins = "gpio4", "gpio5"; + function = "blsp_uart8_a"; + }; + + config { + pins = "gpio4", "gpio5"; + drive-strength = <2>; + bias-disable; + }; + }; + + /* HS UART CONFIGURATION */ + blsp1_uart1_active: blsp1_uart1_active { + mux { + pins = "gpio0", "gpio1", "gpio2", "gpio3"; + function = "blsp_uart1_a"; + }; + + config { + pins = "gpio0", "gpio1", "gpio2", "gpio3"; + drive-strength = <2>; + bias-disable; + }; + }; + + blsp1_uart1_sleep: blsp1_uart1_sleep { + mux { + pins = "gpio0", "gpio1", "gpio2", "gpio3"; + function = "gpio"; + }; + + config { + pins = "gpio0", "gpio1", "gpio2", "gpio3"; + drive-strength = <2>; + bias-disable; + }; + }; + + blsp1_uart2_active: blsp1_uart2_active { + mux { + pins = "gpio31", "gpio34", "gpio33", "gpio32"; + function = "blsp_uart2_a"; + }; + + config { + pins = "gpio31", "gpio34", "gpio33", "gpio32"; + drive-strength = <2>; + bias-disable; + }; + }; + + blsp1_uart2_sleep: blsp1_uart2_sleep { + mux { + pins = "gpio31", "gpio34", "gpio33", "gpio32"; + function = "gpio"; + }; + + config { + pins = "gpio31", "gpio34", "gpio33", "gpio32"; + drive-strength = <2>; + bias-disable; + }; + }; + + blsp1_uart3: blsp1_uart3 { + blsp1_uart3_tx_active: blsp1_uart3_tx_active { + mux { + pins = "gpio45"; + function = "blsp_uart3_a"; + }; + + config { + pins = "gpio45"; + drive-strength = <2>; + bias-disable; + }; + }; + + blsp1_uart3_tx_sleep: blsp1_uart3_tx_sleep { + mux { + pins = "gpio45"; + function = "gpio"; + }; + + config { + pins = "gpio45"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + blsp1_uart3_rxcts_active: blsp1_uart3_rxcts_active { + mux { + pins = "gpio46", "gpio47"; + function = "blsp_uart3_a"; + }; + + config { + pins = "gpio46", "gpio47"; + drive-strength = <2>; + bias-disable; + }; + }; + + blsp1_uart3_rxcts_sleep: blsp1_uart3_rxcts_sleep { + mux { + pins = "gpio46", "gpio47"; + function = "gpio"; + }; + + config { + pins = "gpio46", "gpio47"; + drive-strength = <2>; + bias-no-pull; + }; + }; + + blsp1_uart3_rfr_active: blsp1_uart3_rfr_active { + mux { + pins = "gpio48"; + function = "blsp_uart3_a"; + }; + + config { + pins = "gpio48"; + drive-strength = <2>; + bias-disable; + }; + }; + + blsp1_uart3_rfr_sleep: blsp1_uart3_rfr_sleep { + mux { + pins = "gpio48"; + function = "gpio"; + }; + + config { + pins = "gpio48"; + drive-strength = <2>; + bias-no-pull; + }; + }; + }; + + blsp2_uart1_active: blsp2_uart1_active { + mux { + pins = "gpio53", "gpio54", "gpio55", "gpio56"; + function = "blsp_uart7_a"; + }; + + config { + pins = "gpio53", "gpio54", "gpio55", "gpio56"; + drive-strength = <2>; + bias-disable; + }; + }; + + blsp2_uart1_sleep: blsp2_uart1_sleep { + mux { + pins = "gpio53", "gpio54", "gpio55", "gpio56"; + function = "gpio"; + }; + + config { + pins = "gpio53", "gpio54", "gpio55", "gpio56"; + drive-strength = <2>; + bias-disable; + }; + }; + + blsp2_uart2_active: blsp2_uart2_active { + mux { + pins = "gpio4", "gpio5", "gpio6", "gpio7"; + function = "blsp_uart8_a"; + }; + + config { + pins = "gpio4", "gpio5", "gpio6", "gpio7"; + drive-strength = <2>; + bias-disable; + }; + }; + + blsp2_uart2_sleep: blsp2_uart2_sleep { + mux { + pins = "gpio4", "gpio5", "gpio6", "gpio7"; + function = "gpio"; + }; + + config { + pins = "gpio4", "gpio5", "gpio6", "gpio7"; + drive-strength = <2>; + bias-disable; + }; + }; + + blsp2_uart3_active: blsp2_uart3_active { + mux { + pins = "gpio49", "gpio50", "gpio51", "gpio52"; + function = "blsp_uart9_a"; + }; + + config { + pins = "gpio49", "gpio50", "gpio51", "gpio52"; + drive-strength = <2>; + bias-disable; + }; + }; + + blsp2_uart3_sleep: blsp2_uart3_sleep { + mux { + pins = "gpio49", "gpio50", "gpio51", "gpio52"; + function = "gpio"; + }; + + config { + pins = "gpio49", "gpio50", "gpio51", "gpio52"; + drive-strength = <2>; + bias-disable; + }; + }; + + /* PCIE CONFIGURATION */ + + pcie0 { + pcie0_clkreq_default: pcie0_clkreq_default { + mux { + pins = "gpio36"; + function = "pci_e0"; + }; + + config { + pins = "gpio36"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + pcie0_perst_default: pcie0_perst_default { + mux { + pins = "gpio35"; + function = "gpio"; + }; + + config { + pins = "gpio35"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + pcie0_wake_default: pcie0_wake_default { + mux { + pins = "gpio37"; + function = "gpio"; + }; + + config { + pins = "gpio37"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + pcie0_wake_sleep: pcie0_wake_sleep { + mux { + pins = "gpio37"; + function = "gpio"; + }; + + config { + pins = "gpio37"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + /* I2C CONFIGURATION */ + i2c_1 { + i2c_1_active: i2c_1_active { + mux { + pins = "gpio2", "gpio3"; + function = "blsp_i2c1"; + }; + + config { + pins = "gpio2", "gpio3"; + drive-strength = <2>; + bias-disable; + }; + }; + + i2c_1_sleep: i2c_1_sleep { + mux { + pins = "gpio2", "gpio3"; + function = "blsp_i2c1"; + }; + + config { + pins = "gpio2", "gpio3"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + i2c_2 { + i2c_2_active: i2c_2_active { + mux { + pins = "gpio32", "gpio33"; + function = "blsp_i2c2"; + }; + + config { + pins = "gpio32", "gpio33"; + drive-strength = <2>; + bias-disable; + }; + }; + + i2c_2_sleep: i2c_2_sleep { + mux { + pins = "gpio32", "gpio33"; + function = "blsp_i2c2"; + }; + + config { + pins = "gpio32", "gpio33"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + i2c_3 { + i2c_3_active: i2c_3_active { + mux { + pins = "gpio47", "gpio48"; + function = "blsp_i2c3"; + }; + + config { + pins = "gpio47", "gpio48"; + drive-strength = <2>; + bias-disable; + }; + }; + + i2c_3_sleep: i2c_3_sleep { + mux { + pins = "gpio47", "gpio48"; + function = "blsp_i2c3"; + }; + + config { + pins = "gpio47", "gpio48"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + i2c_4 { + i2c_4_active: i2c_4_active { + mux { + pins = "gpio10", "gpio11"; + function = "blsp_i2c4"; + }; + + config { + pins = "gpio10", "gpio11"; + drive-strength = <2>; + bias-disable; + }; + }; + + i2c_4_sleep: i2c_4_sleep { + mux { + pins = "gpio10", "gpio11"; + function = "blsp_i2c4"; + }; + + config { + pins = "gpio10", "gpio11"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + i2c_5 { + i2c_5_active: i2c_5_active { + mux { + pins = "gpio87", "gpio88"; + function = "blsp_i2c5"; + }; + + config { + pins = "gpio87", "gpio88"; + drive-strength = <2>; + bias-disable; + }; + }; + + i2c_5_sleep: i2c_5_sleep { + mux { + pins = "gpio87", "gpio88"; + function = "blsp_i2c5"; + }; + + config { + pins = "gpio87", "gpio88"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + i2c_6 { + i2c_6_active: i2c_6_active { + mux { + pins = "gpio43", "gpio44"; + function = "blsp_i2c6"; + }; + + config { + pins = "gpio43", "gpio44"; + drive-strength = <2>; + bias-disable; + }; + }; + + i2c_6_sleep: i2c_6_sleep { + mux { + pins = "gpio43", "gpio44"; + function = "blsp_i2c6"; + }; + + config { + pins = "gpio43", "gpio44"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + i2c_7 { + i2c_7_active: i2c_7_active { + mux { + pins = "gpio55", "gpio56"; + function = "blsp_i2c7"; + }; + + config { + pins = "gpio55", "gpio56"; + drive-strength = <2>; + bias-disable; + }; + }; + + i2c_7_sleep: i2c_7_sleep { + mux { + pins = "gpio55", "gpio56"; + function = "blsp_i2c7"; + }; + + config { + pins = "gpio55", "gpio56"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + i2c_8 { + i2c_8_active: i2c_8_active { + mux { + pins = "gpio6", "gpio7"; + function = "blsp_i2c8"; + }; + + config { + pins = "gpio6", "gpio7"; + drive-strength = <2>; + bias-disable; + }; + }; + + i2c_8_sleep: i2c_8_sleep { + mux { + pins = "gpio6", "gpio7"; + function = "blsp_i2c8"; + }; + + config { + pins = "gpio6", "gpio7"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + i2c_9 { + i2c_9_active: i2c_9_active { + mux { + pins = "gpio51", "gpio52"; + function = "blsp_i2c9"; + }; + + config { + pins = "gpio51", "gpio52"; + drive-strength = <2>; + bias-disable; + }; + }; + + i2c_9_sleep: i2c_9_sleep { + mux { + pins = "gpio51", "gpio52"; + function = "blsp_i2c9"; + }; + + config { + pins = "gpio51", "gpio52"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + i2c_10 { + i2c_10_active: i2c_10_active { + mux { + pins = "gpio67", "gpio68"; + function = "blsp_i2c10"; + }; + + config { + pins = "gpio67", "gpio68"; + drive-strength = <2>; + bias-disable; + }; + }; + + i2c_10_sleep: i2c_10_sleep { + mux { + pins = "gpio67", "gpio68"; + function = "blsp_i2c10"; + }; + + config { + pins = "gpio67", "gpio68"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + i2c_11 { + i2c_11_active: i2c_11_active { + mux { + pins = "gpio60", "gpio61"; + function = "blsp_i2c11"; + }; + + config { + pins = "gpio60", "gpio61"; + drive-strength = <2>; + bias-disable; + }; + }; + + i2c_11_sleep: i2c_11_sleep { + mux { + pins = "gpio60", "gpio61"; + function = "blsp_i2c11"; + }; + + config { + pins = "gpio60", "gpio61"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + i2c_12 { + i2c_12_active: i2c_12_active { + mux { + pins = "gpio83", "gpio84"; + function = "blsp_i2c12"; + }; + + config { + pins = "gpio83", "gpio84"; + drive-strength = <2>; + bias-disable; + }; + }; + + i2c_12_sleep: i2c_12_sleep { + mux { + pins = "gpio83", "gpio84"; + function = "blsp_i2c12"; + }; + + config { + pins = "gpio83", "gpio84"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + /* SPI CONFIGURATION */ + + spi_1 { + spi_1_active: spi_1_active { + mux { + pins = "gpio0", "gpio1", + "gpio2", "gpio3"; + function = "blsp_spi1"; + }; + + config { + pins = "gpio0", "gpio1", + "gpio2", "gpio3"; + drive-strength = <6>; + bias-disable; + }; + }; + + spi_1_sleep: spi_1_sleep { + mux { + pins = "gpio0", "gpio1", + "gpio2", "gpio3"; + function = "blsp_spi1"; + }; + + config { + pins = "gpio0", "gpio1", + "gpio2", "gpio3"; + drive-strength = <6>; + bias-disable; + }; + }; + + spi_1b_active: spi_1b_active { + mux { + pins = "gpio23", "gpio28"; + function = "blsp1_spi_b"; + }; + + config { + pins = "gpio23", "gpio28"; + drive-strength = <6>; + bias-disable; + }; + }; + + spi_1b_sleep: spi_1b_sleep { + mux { + pins = "gpio23", "gpio28"; + function = "blsp1_spi_b"; + }; + + config { + pins = "gpio23", "gpio28"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + spi_2 { + spi_2_active: spi_2_active { + mux { + pins = "gpio31", "gpio34", + "gpio32", "gpio33"; + function = "blsp_spi2"; + }; + + config { + pins = "gpio31", "gpio34", + "gpio32", "gpio33"; + drive-strength = <6>; + bias-disable; + }; + }; + + spi_2_sleep: spi_2_sleep { + mux { + pins = "gpio31", "gpio34", + "gpio32", "gpio33"; + function = "blsp_spi2"; + }; + + config { + pins = "gpio31", "gpio34", + "gpio32", "gpio33"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + spi_3 { + spi_3_active: spi_3_active { + mux { + pins = "gpio45", "gpio46", + "gpio47", "gpio48"; + function = "blsp_spi3"; + }; + + config { + pins = "gpio45", "gpio46", + "gpio47", "gpio48"; + drive-strength = <6>; + bias-disable; + }; + }; + + spi_3_sleep: spi_3_sleep { + mux { + pins = "gpio45", "gpio46", + "gpio47", "gpio48"; + function = "blsp_spi3"; + }; + + config { + pins = "gpio45", "gpio46", + "gpio47", "gpio48"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + spi_4 { + spi_4_active: spi_4_active { + mux { + pins = "gpio8", "gpio9", + "gpio10", "gpio11"; + function = "blsp_spi4"; + }; + + config { + pins = "gpio8", "gpio9", + "gpio10", "gpio11"; + drive-strength = <6>; + bias-disable; + }; + }; + + spi_4_sleep: spi_4_sleep { + mux { + pins = "gpio8", "gpio9", + "gpio10", "gpio11"; + function = "blsp_spi4"; + }; + + config { + pins = "gpio8", "gpio9", + "gpio10", "gpio11"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + spi_5 { + spi_5_active: spi_5_active { + mux { + pins = "gpio85", "gpio86", + "gpio87", "gpio88"; + function = "blsp_spi5"; + }; + + config { + pins = "gpio85", "gpio86", + "gpio87", "gpio88"; + drive-strength = <6>; + bias-disable; + }; + }; + + spi_5_sleep: spi_5_sleep { + mux { + pins = "gpio85", "gpio86", + "gpio87", "gpio88"; + function = "blsp_spi5"; + }; + + config { + pins = "gpio85", "gpio86", + "gpio87", "gpio88"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + spi_6 { + spi_6_active: spi_6_active { + mux { + pins = "gpio41", "gpio42", + "gpio43", "gpio44"; + function = "blsp_spi6"; + }; + + config { + pins = "gpio41", "gpio42", + "gpio43", "gpio44"; + drive-strength = <6>; + bias-disable; + }; + }; + + spi_6_sleep: spi_6_sleep { + mux { + pins = "gpio41", "gpio42", + "gpio43", "gpio44"; + function = "blsp_spi6"; + }; + + config { + pins = "gpio41", "gpio42", + "gpio43", "gpio44"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + spi_7 { + spi_7_active: spi_7_active { + mux { + pins = "gpio53", "gpio54", + "gpio55", "gpio56"; + function = "blsp_spi7"; + }; + + config { + pins = "gpio53", "gpio54", + "gpio55", "gpio56"; + drive-strength = <6>; + bias-disable; + }; + }; + + spi_7_sleep: spi_7_sleep { + mux { + pins = "gpio53", "gpio54", + "gpio55", "gpio56"; + function = "blsp_spi7"; + }; + + config { + pins = "gpio53", "gpio54", + "gpio55", "gpio56"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + spi_8 { + spi_8_active: spi_8_active { + mux { + pins = "gpio4", "gpio5", + "gpio6", "gpio7"; + function = "blsp_spi8"; + }; + + config { + pins = "gpio4", "gpio5", + "gpio6", "gpio7"; + drive-strength = <6>; + bias-disable; + }; + }; + + spi_8_sleep: spi_8_sleep { + mux { + pins = "gpio4", "gpio5", + "gpio6", "gpio7"; + function = "blsp_spi8"; + }; + + config { + pins = "gpio4", "gpio5", + "gpio6", "gpio7"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + spi_9 { + spi_9_active: spi_9_active { + mux { + pins = "gpio49", "gpio50", + "gpio51", "gpio52"; + function = "blsp_spi9"; + }; + + config { + pins = "gpio49", "gpio50", + "gpio51", "gpio52"; + drive-strength = <6>; + bias-disable; + }; + }; + + spi_9_sleep: spi_9_sleep { + mux { + pins = "gpio49", "gpio50", + "gpio51", "gpio52"; + function = "blsp_spi9"; + }; + + config { + pins = "gpio49", "gpio50", + "gpio51", "gpio52"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + spi_10 { + spi_10_active: spi_10_active { + mux { + pins = "gpio65", "gpio66", + "gpio67", "gpio68"; + function = "blsp_spi10"; + }; + + config { + pins = "gpio65", "gpio66", + "gpio67", "gpio68"; + drive-strength = <6>; + bias-disable; + }; + }; + + spi_10_sleep: spi_10_sleep { + mux { + pins = "gpio65", "gpio66", + "gpio67", "gpio68"; + function = "blsp_spi10"; + }; + + config { + pins = "gpio65", "gpio66", + "gpio67", "gpio68"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + spi_11 { + spi_11_active: spi_11_active { + mux { + pins = "gpio58", "gpio59", + "gpio60", "gpio61"; + function = "blsp_spi11"; + }; + + config { + pins = "gpio58", "gpio59", + "gpio60", "gpio61"; + drive-strength = <6>; + bias-disable; + }; + }; + + spi_11_sleep: spi_11_sleep { + mux { + pins = "gpio58", "gpio59", + "gpio60", "gpio61"; + function = "blsp_spi11"; + }; + + config { + pins = "gpio58", "gpio59", + "gpio60", "gpio61"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + spi_12 { + spi_12_active: spi_12_active { + mux { + pins = "gpio81", "gpio82", + "gpio83", "gpio84"; + function = "blsp_spi12"; + }; + + config { + pins = "gpio81", "gpio82", + "gpio83", "gpio84"; + drive-strength = <6>; + bias-disable; + }; + }; + + spi_12_sleep: spi_12_sleep { + mux { + pins = "gpio81", "gpio82", + "gpio83", "gpio84"; + function = "blsp_spi12"; + }; + + config { + pins = "gpio81", "gpio82", + "gpio83", "gpio84"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + /* CAMERA CONFIGURATION */ + + cci0_active: cci0_active { + mux { + /* CLK, DATA */ + pins = "gpio17","gpio18"; // Only 2 + function = "cci_i2c"; + }; + + config { + pins = "gpio17","gpio18"; + bias-pull-up; /* PULL UP*/ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci0_suspend: cci0_suspend { + mux { + /* CLK, DATA */ + pins = "gpio17","gpio18"; + function = "cci_i2c"; + }; + + config { + pins = "gpio17","gpio18"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci1_active: cci1_active { + mux { + /* CLK, DATA */ + pins = "gpio19","gpio20"; + function = "cci_i2c"; + }; + + config { + pins = "gpio19","gpio20"; + bias-pull-up; /* PULL UP*/ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci1_suspend: cci1_suspend { + mux { + /* CLK, DATA */ + pins = "gpio19","gpio20"; + function = "cci_i2c"; + }; + + config { + pins = "gpio19","gpio20"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + /* MDSS CONFIGURATION */ + + mdss_dp_aux_active: mdss_dp_aux_active { + mux { + pins = "gpio77", "gpio78"; + function = "gpio"; + }; + + config { + pins = "gpio77", "gpio78"; + bias-disable = <0>; /* no pull */ + drive-strength = <8>; + }; + }; + + mdss_dp_aux_suspend: mdss_dp_aux_suspend { + mux { + pins = "gpio77", "gpio78"; + function = "gpio"; + }; + + config { + pins = "gpio77", "gpio78"; + bias-pull-down; + drive-strength = <2>; + }; + }; + + mdss_dp_usbplug_cc_active: mdss_dp_usbplug_cc_active { + mux { + pins = "gpio38"; + function = "gpio"; + }; + + config { + pins = "gpio38"; + bias-disable; + drive-strength = <16>; + }; + }; + + mdss_dp_usbplug_cc_suspend: mdss_dp_usbplug_cc_suspend { + mux { + pins = "gpio38"; + function = "gpio"; + }; + + config { + pins = "gpio38"; + bias-pull-down; + drive-strength = <2>; + }; + }; + + mdss_dp_hpd_active: mdss_dp_hpd_active { + mux { + pins = "gpio34"; + function = "edp_hot"; + }; + + config { + pins = "gpio34"; + bias-pull-down; + drive-strength = <16>; + }; + }; + + mdss_dp_hpd_suspend: mdss_dp_hpd_suspend { + mux { + pins = "gpio34"; + function = "edp_hot"; + }; + + config { + pins = "gpio34"; + bias-pull-down; + drive-strength = <2>; + }; + }; + + mdss_hdmi_5v_active: mdss_hdmi_5v_active { + mux { + pins = "gpio133"; + function = "gpio"; + }; + + config { + pins = "gpio133"; + bias-pull-up; + drive-strength = <16>; + }; + }; + + mdss_hdmi_5v_suspend: mdss_hdmi_5v_suspend { + mux { + pins = "gpio133"; + function = "gpio"; + }; + + config { + pins = "gpio133"; + bias-pull-down; + drive-strength = <2>; + }; + }; + + mdss_hdmi_hpd_active: mdss_hdmi_hpd_active { + mux { + pins = "gpio34"; + function = "hdmi_hot"; + }; + + config { + pins = "gpio34"; + bias-pull-down; + drive-strength = <16>; + }; + }; + + mdss_hdmi_hpd_suspend: mdss_hdmi_hpd_suspend { + mux { + pins = "gpio34"; + function = "hdmi_hot"; + }; + + config { + pins = "gpio34"; + bias-pull-down; + drive-strength = <2>; + }; + }; + + mdss_hdmi_ddc_active: mdss_hdmi_ddc_active { + mux { + pins = "gpio32", "gpio33"; + function = "hdmi_ddc"; + }; + + config { + pins = "gpio32", "gpio33"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + mdss_hdmi_ddc_suspend: mdss_hdmi_ddc_suspend { + mux { + pins = "gpio32", "gpio33"; + function = "hdmi_ddc"; + }; + + config { + pins = "gpio32", "gpio33"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + mdss_hdmi_cec_active: mdss_hdmi_cec_active { + mux { + pins = "gpio31"; + function = "hdmi_cec"; + }; + + config { + pins = "gpio31"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + mdss_hdmi_cec_suspend: mdss_hdmi_cec_suspend { + mux { + pins = "gpio31"; + function = "hdmi_cec"; + }; + + config { + pins = "gpio31"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + /* UFS CONFIGURATION */ + + ufs_dev_reset_assert: ufs_dev_reset_assert { + config { + pins = "ufs_reset"; + bias-pull-down; /* default: pull down */ + /* + * UFS_RESET driver strengths are having + * different values/steps compared to typical + * GPIO drive strengths. + * + * Following table clarifies: + * + * HDRV value | UFS_RESET | Typical GPIO + * (dec) | (mA) | (mA) + * 0 | 0.8 | 2 + * 1 | 1.55 | 4 + * 2 | 2.35 | 6 + * 3 | 3.1 | 8 + * 4 | 3.9 | 10 + * 5 | 4.65 | 12 + * 6 | 5.4 | 14 + * 7 | 6.15 | 16 + * + * POR value for UFS_RESET HDRV is 3 which means + * 3.1mA and we want to use that. Hence just + * specify 8mA to "drive-strength" binding and + * that should result into writing 3 to HDRV + * field. + */ + drive-strength = <8>; /* default: 3.1 mA */ + output-low; /* active low reset */ + }; + }; + + ufs_dev_reset_deassert: ufs_dev_reset_deassert { + config { + pins = "ufs_reset"; + bias-pull-down; /* default: pull down */ + /* + * default: 3.1 mA + * check comments under ufs_dev_reset_assert + */ + drive-strength = <8>; + output-high; /* active low reset */ + }; + }; + + /* SHDCI CONFIGURATION */ + + sdc2_clk_on: sdc2_clk_on { + config { + pins = "sdc2_clk"; + bias-disable; /* NO pull */ + drive-strength = <16>; /* 16 MA */ + }; + }; + + sdc2_clk_off: sdc2_clk_off { + config { + pins = "sdc2_clk"; + bias-disable; /* NO pull */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + sdc2_cmd_on: sdc2_cmd_on { + config { + pins = "sdc2_cmd"; + bias-pull-up; /* pull up */ + drive-strength = <10>; /* 10 MA */ + }; + }; + + sdc2_cmd_off: sdc2_cmd_off { + config { + pins = "sdc2_cmd"; + bias-pull-up; /* pull up */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + sdc2_data_on: sdc2_data_on { + config { + pins = "sdc2_data"; + bias-pull-up; /* pull up */ + drive-strength = <10>; /* 10 MA */ + }; + }; + + sdc2_data_off: sdc2_data_off { + config { + pins = "sdc2_data"; + bias-pull-up; /* pull up */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + sdc2_cd_on: sdc2_cd_on { + mux { + pins = "gpio95"; + function = "gpio"; + }; + + config { + pins = "gpio95"; + bias-pull-up; /* pull up */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + sdc2_cd_off: sdc2_cd_off { + mux { + pins = "gpio95"; + function = "gpio"; + }; + + config { + pins = "gpio95"; + bias-pull-up; /* pull up */ + drive-strength = <2>; /* 2 MA */ + }; + + }; + + /* CORESIGHT */ + + trigout_a: trigout_a { + mux { + pins = "gpio58"; + function = "qdss_cti1_a"; + }; + + config { + pins = "gpio58"; + drive-strength = <2>; + bias-disable; + }; + }; + + /* TSPP CONFIGURATION */ + + tsif0_signals_active: tsif0_signals_active { + tsif1_clk { + pins = "gpio89"; /* TSIF0 CLK */ + function = "tsif1_clk"; + }; + tsif1_en { + pins = "gpio90"; /* TSIF0 Enable */ + function = "tsif1_en"; + }; + tsif1_data { + pins = "gpio91"; /* TSIF0 DATA */ + function = "tsif1_data"; + }; + signals_cfg { + pins = "gpio89", "gpio90", "gpio91"; + drive_strength = <2>; /* 2 mA */ + bias-pull-down; /* pull down */ + }; + }; + + tsif0_sync_active: tsif0_sync_active { + tsif1_sync { + pins = "gpio9"; /* TSIF0 SYNC */ + function = "tsif1_sync"; + drive_strength = <2>; /* 2 mA */ + bias-pull-down; /* pull down */ + }; + }; + + tsif1_signals_active: tsif1_signals_active { + tsif2_clk { + pins = "gpio93"; /* TSIF1 CLK */ + function = "tsif2_clk"; + }; + tsif2_en { + pins = "gpio94"; /* TSIF1 Enable */ + function = "tsif2_en"; + }; + tsif2_data { + pins = "gpio95"; /* TSIF1 DATA */ + function = "tsif2_data"; + }; + signals_cfg { + pins = "gpio93", "gpio94", "gpio95"; + drive_strength = <2>; /* 2 mA */ + bias-pull-down; /* pull down */ + }; + }; + + tsif1_sync_active: tsif1_sync_active { + tsif2_sync { + pins = "gpio96"; /* TSIF1 SYNC */ + function = "tsif2_sync"; + drive_strength = <2>; /* 2 mA */ + bias-pull-down; /* pull down */ + }; + }; + + /* DIGITAL AUDIO CONFIGURATION */ + + pri_aux_pcm_clk { + pri_aux_pcm_clk_sleep: pri_aux_pcm_clk_sleep { + mux { + pins = "gpio65"; + function = "gpio"; + }; + + config { + pins = "gpio65"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + pri_aux_pcm_clk_active: pri_aux_pcm_clk_active { + mux { + pins = "gpio65"; + function = "pri_mi2s"; + }; + + config { + pins = "gpio65"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + pri_aux_pcm_sync { + pri_aux_pcm_sync_sleep: pri_aux_pcm_sync_sleep { + mux { + pins = "gpio66"; + function = "gpio"; + }; + + config { + pins = "gpio66"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + pri_aux_pcm_sync_active: pri_aux_pcm_sync_active { + mux { + pins = "gpio66"; + function = "pri_mi2s_ws"; + }; + + config { + pins = "gpio66"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + pri_aux_pcm_din { + pri_aux_pcm_din_sleep: pri_aux_pcm_din_sleep { + mux { + pins = "gpio67"; + function = "gpio"; + }; + + config { + pins = "gpio67"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + pri_aux_pcm_din_active: pri_aux_pcm_din_active { + mux { + pins = "gpio67"; + function = "pri_mi2s"; + }; + + config { + pins = "gpio67"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + pri_aux_pcm_dout { + pri_aux_pcm_dout_sleep: pri_aux_pcm_dout_sleep { + mux { + pins = "gpio68"; + function = "gpio"; + }; + + config { + pins = "gpio68"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + pri_aux_pcm_dout_active: pri_aux_pcm_dout_active { + mux { + pins = "gpio68"; + function = "pri_mi2s"; + }; + + config { + pins = "gpio68"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + sec_aux_pcm { + sec_aux_pcm_sleep: sec_aux_pcm_sleep { + mux { + pins = "gpio80", "gpio81"; + function = "gpio"; + }; + + config { + pins = "gpio80", "gpio81"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + sec_aux_pcm_active: sec_aux_pcm_active { + mux { + pins = "gpio80", "gpio81"; + function = "sec_mi2s"; + }; + + config { + pins = "gpio80", "gpio81"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + sec_aux_pcm_din { + sec_aux_pcm_din_sleep: sec_aux_pcm_din_sleep { + mux { + pins = "gpio82"; + function = "gpio"; + }; + + config { + pins = "gpio82"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + sec_aux_pcm_din_active: sec_aux_pcm_din_active { + mux { + pins = "gpio82"; + function = "sec_mi2s"; + }; + + config { + pins = "gpio82"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + sec_aux_pcm_dout { + sec_aux_pcm_dout_sleep: sec_aux_pcm_dout_sleep { + mux { + pins = "gpio83"; + function = "gpio"; + }; + + config { + pins = "gpio83"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + sec_aux_pcm_dout_active: sec_aux_pcm_dout_active { + mux { + pins = "gpio83"; + function = "sec_mi2s"; + }; + + config { + pins = "gpio83"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + tert_aux_pcm { + tert_aux_pcm_sleep: tert_aux_pcm_sleep { + mux { + pins = "gpio75", "gpio76"; + function = "gpio"; + }; + + config { + pins = "gpio75", "gpio76"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + tert_aux_pcm_active: tert_aux_pcm_active { + mux { + pins = "gpio75", "gpio76"; + function = "ter_mi2s"; + }; + + config { + pins = "gpio75", "gpio76"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + tert_aux_pcm_din { + tert_aux_pcm_din_sleep: tert_aux_pcm_din_sleep { + mux { + pins = "gpio77"; + function = "gpio"; + }; + + config { + pins = "gpio77"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + tert_aux_pcm_din_active: tert_aux_pcm_din_active { + mux { + pins = "gpio77"; + function = "ter_mi2s"; + }; + + config { + pins = "gpio77"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + tert_aux_pcm_dout { + tert_aux_pcm_dout_sleep: tert_aux_pcm_dout_sleep { + mux { + pins = "gpio78"; + function = "gpio"; + }; + + config { + pins = "gpio78"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + tert_aux_pcm_dout_active: tert_aux_pcm_dout_active { + mux { + pins = "gpio78"; + function = "ter_mi2s"; + }; + + config { + pins = "gpio78"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + quat_aux_pcm { + quat_aux_pcm_sleep: quat_aux_pcm_sleep { + mux { + pins = "gpio58", "gpio59"; + function = "gpio"; + }; + + config { + pins = "gpio58", "gpio59"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + quat_aux_pcm_active: quat_aux_pcm_active { + mux { + pins = "gpio58", "gpio59"; + function = "qua_mi2s"; + }; + + config { + pins = "gpio58", "gpio59"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + quat_aux_pcm_din { + quat_aux_pcm_din_sleep: quat_aux_pcm_din_sleep { + mux { + pins = "gpio60"; + function = "gpio"; + }; + + config { + pins = "gpio60"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + quat_aux_pcm_din_active: quat_aux_pcm_din_active { + mux { + pins = "gpio60"; + function = "qua_mi2s"; + }; + + config { + pins = "gpio60"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + quat_aux_pcm_dout { + quat_aux_pcm_dout_sleep: quat_aux_pcm_dout_sleep { + mux { + pins = "gpio61"; + function = "gpio"; + }; + + config { + pins = "gpio61"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + quat_aux_pcm_dout_active: quat_aux_pcm_dout_active { + mux { + pins = "gpio61"; + function = "qua_mi2s"; + }; + + config { + pins = "gpio61"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + pri_mi2s_mclk { + pri_mi2s_mclk_sleep: pri_mi2s_mclk_sleep { + mux { + pins = "gpio64"; + function = "gpio"; + }; + + config { + pins = "gpio64"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + pri_mi2s_mclk_active: pri_mi2s_mclk_active { + mux { + pins = "gpio64"; + function = "pri_mi2s"; + }; + + config { + pins = "gpio64"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + pri_mi2s_sck { + pri_mi2s_sck_sleep: pri_mi2s_sck_sleep { + mux { + pins = "gpio65"; + function = "gpio"; + }; + + config { + pins = "gpio65"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + pri_mi2s_sck_active: pri_mi2s_sck_active { + mux { + pins = "gpio65"; + function = "pri_mi2s"; + }; + + config { + pins = "gpio65"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + pri_mi2s_ws { + pri_mi2s_ws_sleep: pri_mi2s_ws_sleep { + mux { + pins = "gpio66"; + function = "gpio"; + }; + + config { + pins = "gpio66"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + pri_mi2s_ws_active: pri_mi2s_ws_active { + mux { + pins = "gpio66"; + function = "pri_mi2s_ws"; + }; + + config { + pins = "gpio66"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + pri_mi2s_sd0 { + pri_mi2s_sd0_sleep: pri_mi2s_sd0_sleep { + mux { + pins = "gpio67"; + function = "gpio"; + }; + + config { + pins = "gpio67"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + pri_mi2s_sd0_active: pri_mi2s_sd0_active { + mux { + pins = "gpio67"; + function = "pri_mi2s"; + }; + + config { + pins = "gpio67"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + pri_mi2s_sd1 { + pri_mi2s_sd1_sleep: pri_mi2s_sd1_sleep { + mux { + pins = "gpio68"; + function = "gpio"; + }; + + config { + pins = "gpio68"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + pri_mi2s_sd1_active: pri_mi2s_sd1_active { + mux { + pins = "gpio68"; + function = "pri_mi2s"; + }; + + config { + pins = "gpio68"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + sec_mi2s_mclk { + sec_mi2s_mclk_sleep: sec_mi2s_mclk_sleep { + mux { + pins = "gpio79"; + function = "gpio"; + }; + + config { + pins = "gpio79"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + sec_mi2s_mclk_active: sec_mi2s_mclk_active { + mux { + pins = "gpio79"; + function = "sec_mi2s"; + }; + + config { + pins = "gpio79"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + sec_mi2s { + sec_mi2s_sleep: sec_mi2s_sleep { + mux { + pins = "gpio80", "gpio81"; + function = "gpio"; + }; + + config { + pins = "gpio80", "gpio81"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + sec_mi2s_active: sec_mi2s_active { + mux { + pins = "gpio80", "gpio81"; + function = "sec_mi2s"; + }; + + config { + pins = "gpio80", "gpio81"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + sec_mi2s_sd0 { + sec_mi2s_sd0_sleep: sec_mi2s_sd0_sleep { + mux { + pins = "gpio82"; + function = "gpio"; + }; + + config { + pins = "gpio82"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + sec_mi2s_sd0_active: sec_mi2s_sd0_active { + mux { + pins = "gpio82"; + function = "sec_mi2s"; + }; + + config { + pins = "gpio82"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + sec_mi2s_sd1 { + sec_mi2s_sd1_sleep: sec_mi2s_sd1_sleep { + mux { + pins = "gpio83"; + function = "gpio"; + }; + + config { + pins = "gpio83"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + sec_mi2s_sd1_active: sec_mi2s_sd1_active { + mux { + pins = "gpio83"; + function = "sec_mi2s"; + }; + + config { + pins = "gpio83"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + tert_mi2s_mclk { + tert_mi2s_mclk_sleep: tert_mi2s_mclk_sleep { + mux { + pins = "gpio74"; + function = "gpio"; + }; + + config { + pins = "gpio74"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + tert_mi2s_mclk_active: tert_mi2s_mclk_active { + mux { + pins = "gpio74"; + function = "ter_mi2s"; + }; + + config { + pins = "gpio74"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + tert_mi2s { + tert_mi2s_sleep: tert_mi2s_sleep { + mux { + pins = "gpio75", "gpio76"; + function = "gpio"; + }; + + config { + pins = "gpio75", "gpio76"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + tert_mi2s_active: tert_mi2s_active { + mux { + pins = "gpio75", "gpio76"; + function = "ter_mi2s"; + }; + + config { + pins = "gpio75", "gpio76"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + tert_mi2s_sd0 { + tert_mi2s_sd0_sleep: tert_mi2s_sd0_sleep { + mux { + pins = "gpio77"; + function = "gpio"; + }; + + config { + pins = "gpio77"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + tert_mi2s_sd0_active: tert_mi2s_sd0_active { + mux { + pins = "gpio77"; + function = "ter_mi2s"; + }; + + config { + pins = "gpio77"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + tert_mi2s_sd1 { + tert_mi2s_sd1_sleep: tert_mi2s_sd1_sleep { + mux { + pins = "gpio78"; + function = "gpio"; + }; + + config { + pins = "gpio78"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + tert_mi2s_sd1_active: tert_mi2s_sd1_active { + mux { + pins = "gpio78"; + function = "ter_mi2s"; + }; + + config { + pins = "gpio78"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + quat_mi2s_mclk { + quat_mi2s_mclk_sleep: quat_mi2s_mclk_sleep { + mux { + pins = "gpio57"; + function = "gpio"; + }; + + config { + pins = "gpio57"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + quat_mi2s_mclk_active: quat_mi2s_mclk_active { + mux { + pins = "gpio57"; + function = "qua_mi2s"; + }; + + config { + pins = "gpio57"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + quat_mi2s { + quat_mi2s_sleep: quat_mi2s_sleep { + mux { + pins = "gpio58", "gpio59"; + function = "gpio"; + }; + + config { + pins = "gpio58", "gpio59"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + quat_mi2s_active: quat_mi2s_active { + mux { + pins = "gpio58", "gpio59"; + function = "qua_mi2s"; + }; + + config { + pins = "gpio58", "gpio59"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + quat_mi2s_sd0 { + quat_mi2s_sd0_sleep: quat_mi2s_sd0_sleep { + mux { + pins = "gpio60"; + function = "gpio"; + }; + + config { + pins = "gpio60"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + quat_mi2s_sd0_active: quat_mi2s_sd0_active { + mux { + pins = "gpio60"; + function = "qua_mi2s"; + }; + + config { + pins = "gpio60"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + quat_mi2s_sd1 { + quat_mi2s_sd1_sleep: quat_mi2s_sd1_sleep { + mux { + pins = "gpio61"; + function = "gpio"; + }; + + config { + pins = "gpio61"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + quat_mi2s_sd1_active: quat_mi2s_sd1_active { + mux { + pins = "gpio61"; + function = "qua_mi2s"; + }; + + config { + pins = "gpio61"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + quat_mi2s_sd2 { + quat_mi2s_sd2_sleep: quat_mi2s_sd2_sleep { + mux { + pins = "gpio62"; + function = "gpio"; + }; + + config { + pins = "gpio62"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + quat_mi2s_sd2_active: quat_mi2s_sd2_active { + mux { + pins = "gpio62"; + function = "qua_mi2s"; + }; + + config { + pins = "gpio62"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + quat_mi2s_sd3 { + quat_mi2s_sd3_sleep: quat_mi2s_sd3_sleep { + mux { + pins = "gpio63"; + function = "gpio"; + }; + + config { + pins = "gpio63"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + quat_mi2s_sd3_active: quat_mi2s_sd3_active { + mux { + pins = "gpio63"; + function = "qua_mi2s"; + }; + + config { + pins = "gpio63"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + spkr_i2s_clk_pin { + spkr_i2s_clk_sleep: spkr_i2s_clk_sleep { + mux { + pins = "gpio69"; + function = "spkr_i2s"; + }; + + config { + pins = "gpio69"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + }; + }; + + spkr_i2s_clk_active: spkr_i2s_clk_active { + mux { + pins = "gpio69"; + function = "spkr_i2s"; + }; + + config { + pins = "gpio69"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + }; +}; diff -Nruw linux-4.4.115-fbx/arch/arm/boot/dts/qcom./msm8998-pm.dtsi linux-4.4.115-fbx/arch/arm/boot/dts/qcom/msm8998-pm.dtsi --- linux-4.4.115-fbx/arch/arm/boot/dts/qcom./msm8998-pm.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ linux-4.4.115-fbx/arch/arm/boot/dts/qcom/msm8998-pm.dtsi 2019-01-22 16:16:21.195225506 +0100 @@ -0,0 +1,807 @@ +/* Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include + +&soc { + qcom,spm@178120000 { + compatible = "qcom,spm-v2"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x17812000 0x1000>; + qcom,name = "gold-l2"; /* Gold L2 SAW */ + qcom,saw2-ver-reg = <0xfd0>; + qcom,cpu-vctl-list = <&CPU4 &CPU5 &CPU6 &CPU7>; + qcom,vctl-timeout-us = <500>; + qcom,vctl-port = <0x0>; + qcom,phase-port = <0x1>; + qcom,saw2-avs-ctl = <0x1010031>; + qcom,saw2-avs-limit = <0x4580458>; + qcom,pfm-port = <0x2>; + }; + + qcom,spm@179120000 { + compatible = "qcom,spm-v2"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x17912000 0x1000>; + qcom,name = "silver-l2"; /* Silver L2 SAW */ + qcom,saw2-ver-reg = <0xfd0>; + qcom,cpu-vctl-list = <&CPU0 &CPU1 &CPU2 &CPU3>; + qcom,vctl-timeout-us = <500>; + qcom,vctl-port = <0x0>; + qcom,phase-port = <0x1>; + qcom,saw2-avs-ctl = <0x1010031>; + qcom,saw2-avs-limit = <0x4580458>; + qcom,pfm-port = <0x2>; + }; + + qcom,lpm-levels { + compatible = "qcom,lpm-levels"; + qcom,use-psci; + #address-cells = <1>; + #size-cells = <0>; + qcom,pm-cluster@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + label = "system"; + qcom,spm-device-names = "cci"; + qcom,psci-mode-shift = <8>; + qcom,psci-mode-mask = <0xf>; + + qcom,pm-cluster-level@0{ + reg = <0>; + label = "system-wfi"; + qcom,psci-mode = <0x0>; + qcom,latency-us = <100>; + qcom,ss-power = <725>; + qcom,energy-overhead = <85000>; + qcom,time-overhead = <120>; + }; + + qcom,pm-cluster-level@1{ /* E3 */ + reg = <1>; + label = "system-pc"; + qcom,psci-mode = <0x3>; + qcom,latency-us = <5534>; + qcom,ss-power = <399>; + qcom,energy-overhead = <3340281>; + qcom,time-overhead = <16744>; + qcom,min-child-idx = <3>; + qcom,is-reset; + qcom,notify-rpm; + }; + + qcom,pm-cluster@0{ + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + label = "pwr"; + qcom,spm-device-names = "l2"; + qcom,cpu = <&CPU0 &CPU1 &CPU2 &CPU3>; + qcom,psci-mode-shift = <4>; + qcom,psci-mode-mask = <0xf>; + + qcom,pm-cluster-level@0{ /* D1 */ + reg = <0>; + label = "pwr-l2-wfi"; + qcom,psci-mode = <0x1>; + qcom,latency-us = <51>; + qcom,ss-power = <452>; + qcom,energy-overhead = <69355>; + qcom,time-overhead = <99>; + }; + qcom,pm-cluster-level@1{ /* D2D */ + reg = <1>; + label = "pwr-l2-dynret"; + qcom,psci-mode = <0x2>; + qcom,latency-us = <659>; + qcom,ss-power = <434>; + qcom,energy-overhead = <465725>; + qcom,time-overhead = <976>; + qcom,min-child-idx = <1>; + }; + + qcom,pm-cluster-level@2{ /* D2E */ + reg = <2>; + label = "pwr-l2-ret"; + qcom,psci-mode = <0x3>; + qcom,latency-us = <743>; + qcom,ss-power = <425>; + qcom,energy-overhead = <629936>; + qcom,time-overhead = <1312>; + qcom,min-child-idx = <2>; + }; + + qcom,pm-cluster-level@3{ /* D4 */ + reg = <3>; + label = "pwr-l2-pc"; + qcom,psci-mode = <0x4>; + qcom,latency-us = <4562>; + qcom,ss-power = <408>; + qcom,energy-overhead = <2421840>; + qcom,time-overhead = <5376>; + qcom,min-child-idx = <2>; + qcom,is-reset; + }; + + qcom,pm-cpu { + #address-cells = <1>; + #size-cells = <0>; + qcom,psci-mode-shift = <0>; + qcom,psci-mode-mask = <0xf>; + + qcom,pm-cpu-level@0 { /* C1 */ + reg = <0>; + qcom,spm-cpu-mode = "wfi"; + qcom,psci-cpu-mode = <0x1>; + qcom,latency-us = <43>; + qcom,ss-power = <454>; + qcom,energy-overhead = <38639>; + qcom,time-overhead = <83>; + }; + + qcom,pm-cpu-level@1 { /* C2D */ + reg = <1>; + qcom,psci-cpu-mode = <2>; + qcom,spm-cpu-mode = "ret"; + qcom,latency-us = <86>; + qcom,ss-power = <449>; + qcom,energy-overhead = <78456>; + qcom,time-overhead = <167>; + }; + + qcom,pm-cpu-level@2 { /* C3 */ + reg = <2>; + qcom,spm-cpu-mode = "pc"; + qcom,psci-cpu-mode = <0x3>; + qcom,latency-us = <612>; + qcom,ss-power = <436>; + qcom,energy-overhead = <418225>; + qcom,time-overhead = <885>; + qcom,is-reset; + }; + }; + }; + + qcom,pm-cluster@1{ + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + label = "perf"; + qcom,spm-device-names = "l2"; + qcom,cpu = <&CPU4 &CPU5 &CPU6 &CPU7>; + qcom,psci-mode-shift = <4>; + qcom,psci-mode-mask = <0xf>; + + qcom,pm-cluster-level@0{ /* D1 */ + reg = <0>; + label = "perf-l2-wfi"; + qcom,psci-mode = <0x1>; + qcom,latency-us = <51>; + qcom,ss-power = <512>; + qcom,energy-overhead = <99986>; + qcom,time-overhead = <99>; + }; + + qcom,pm-cluster-level@1{ /* D2D */ + reg = <1>; + label = "perf-l2-dynret"; + qcom,psci-mode = <2>; + qcom,latency-us = <529>; + qcom,ss-power = <468>; + qcom,energy-overhead = <496783>; + qcom,time-overhead = <871>; + qcom,min-child-idx = <1>; + }; + + qcom,pm-cluster-level@2{ /* D2E */ + reg = <2>; + label = "perf-l2-ret"; + qcom,psci-mode = <3>; + qcom,latency-us = <605>; + qcom,ss-power = <456>; + qcom,energy-overhead = <597126>; + qcom,time-overhead = <1025>; + qcom,min-child-idx = <2>; + }; + + qcom,pm-cluster-level@3{ /* D4 */ + reg = <3>; + label = "perf-l2-pc"; + qcom,psci-mode = <0x4>; + qcom,latency-us = <2027>; + qcom,ss-power = <420>; + qcom,energy-overhead = <1624216>; + qcom,time-overhead = <2751>; + qcom,min-child-idx = <2>; + qcom,is-reset; + }; + + qcom,pm-cpu { + #address-cells = <1>; + #size-cells = <0>; + qcom,psci-mode-shift = <0>; + qcom,psci-mode-mask = <0xf>; + + qcom,pm-cpu-level@0 { /* C1 */ + reg = <0>; + qcom,spm-cpu-mode = "wfi"; + qcom,psci-cpu-mode = <0x1>; + qcom,latency-us = <43>; + qcom,ss-power = <515>; + qcom,energy-overhead = <48502>; + qcom,time-overhead = <86>; + }; + + qcom,pm-cpu-level@1 { /* C2D */ + reg = <1>; + qcom,psci-cpu-mode = <2>; + qcom,spm-cpu-mode = "ret"; + qcom,latency-us = <82>; + qcom,ss-power = <505>; + qcom,energy-overhead = <98530>; + qcom,time-overhead = <161>; + }; + + qcom,pm-cpu-level@2 { /* C3 */ + reg = <2>; + qcom,spm-cpu-mode = "pc"; + qcom,psci-cpu-mode = <0x3>; + qcom,latency-us = <525>; + qcom,ss-power = <476>; + qcom,energy-overhead = <485037>; + qcom,time-overhead = <861>; + qcom,is-reset; + }; + }; + }; + }; + }; + + qcom,rpm-stats@200000 { + compatible = "qcom,rpm-stats"; + reg = <0x200000 0x1000>, + <0x290014 0x4>, + <0x29001c 0x4>; + reg-names = "phys_addr_base", + "offset_addr", + "heap_phys_addrbase"; + qcom,sleep-stats-version = <2>; + }; + + qcom,rpm-rail-stats@200000 { + compatible = "qcom,rpm-rail-stats"; + reg = <0x200000 0x100>, + <0x29000c 0x4>; + reg-names = "phys_addr_base", + "offset_addr"; + }; + + qcom,rpm-log@200000 { + compatible = "qcom,rpm-log"; + reg = <0x200000 0x4000>, + <0x290018 0x4>; + qcom,rpm-addr-phys = <0x200000>; + qcom,offset-version = <4>; + qcom,offset-page-buffer-addr = <36>; + qcom,offset-log-len = <40>; + qcom,offset-log-len-mask = <44>; + qcom,offset-page-indices = <56>; + }; + + qcom,rpm-master-stats@778150 { + compatible = "qcom,rpm-master-stats"; + reg = <0x778150 0x5000>; + qcom,masters = "APSS", "MPSS", "ADSP", "SLPI", "TZ", "SPSS"; + qcom,master-stats-version = <2>; + qcom,master-offset = <4096>; + }; + + rpm_msg_ram: memory@0x200000 { + compatible = "qcom,rpm-msg-ram"; + reg = <0x200000 0x1000>, + <0x290000 0x1000>; + }; + + rpm_code_ram: rpm-memory@0x778000 { + compatible = "qcom,rpm-code-ram"; + reg = <0x778000 0x5000>; + }; + + qcom,system-stats { + compatible = "qcom,system-stats"; + qcom,rpm-msg-ram = <&rpm_msg_ram>; + qcom,rpm-code-ram = <&rpm_code_ram>; + qcom,masters = "APSS", "MPSS", "ADSP", "SLPI", "TZ", "SPSS"; + }; + + qcom,mpm@7781b8 { + compatible = "qcom,mpm-v2"; + reg = <0x7781b8 0x1000>, /* MSM_RPM_MPM_BASE 4K */ + <0x17911008 0x4>; /* MSM_APCS_GCC_BASE 4K */ + reg-names = "vmpm", "ipc"; + interrupts = ; + clocks = <&clock_gcc clk_cxo_lpm_clk>; + clock-names = "xo"; + qcom,num-mpm-irqs = <96>; + + qcom,ipc-bit-offset = <1>; + + qcom,gic-parent = <&intc>; + qcom,gic-map = + <0x1f 212>, /* usb30_power_event_irq */ + <0x2 216>, /* tsens1_upper_lower_int */ + <0x34 275>, /* qmp_usb3_lfps_rxterm_irq_cx */ + <0x57 358>, /* spmi_periph_irq[0] */ + <0x4f 379>, /* usb2phy_intr: qusb2phy_dmse_hv */ + <0x51 379>, /* usb2phy_intr: qusb2phy_dpse_hv */ + <0x50 384>, /* sp_rmb_sp2soc_irq */ + <0xff 16>, /* APC0_qgicQTmrHypPhysIrptReq */ + <0xff 17>, /* APC3_qgicQTmrSecPhysIrptReq */ + <0xff 18>, /* APC0_qgicQTmrNonSecPhysIrptReq */ + <0xff 19>, /* APC3_qgicQTmrVirtIrptReq */ + <0xff 20>, /* APC0_dbgCommRxFull */ + <0xff 21>, /* APC3_dbgCommTxEmpty */ + <0xff 22>, /* APC0_qgicPerfMonIrptReq */ + <0xff 23>, /* corespm_vote_int[7] */ + <0xff 24>, /* APC0_qgicExtFaultIrptReq */ + <0xff 28>, /* qgicWakeupSync */ + <0xff 29>, /* APCC_cti_SPI_intx */ + <0xff 30>, /* APCC_cti_SPI_inty */ + <0xff 32>, /* l2spm_vote_int[0] */ + <0xff 33>, /* l2spm_vote_int[1] */ + <0xff 34>, /* APCC_qgicL2ErrorIrptReq */ + <0xff 35>, /* WDT_barkInt */ + <0xff 36>, /* WDT_biteExpired */ + <0xff 39>, /* QTMR_qgicFrm0VirtIrq */ + <0xff 40>, /* QTMR_qgicFrm0PhyIrq */ + <0xff 41>, /* QTMR_qgicFrm1PhyIrq */ + <0xff 42>, /* QTMR_qgicFrm2PhyIrq */ + <0xff 43>, /* QTMR_qgicFrm3PhyIrq */ + <0xff 44>, /* QTMR_qgicFrm4PhyIrq */ + <0xff 45>, /* QTMR_qgicFrm5PhyIrq */ + <0xff 46>, /* QTMR_qgicFrm6PhyIrq */ + <0xff 47>, /* rbif_Irq[0] */ + <0xff 48>, /* rbif_Irq[1] */ + <0xff 52>, /* cci_spm_vote_summary_int */ + <0xff 54>, /* ~nERRORIRQ */ + <0xff 55>, /* nEVNTCNTOVERFLOW_cci */ + <0xff 56>, /* QTMR_qgicFrm0VirtIrq */ + <0xff 57>, /* QTMR_qgicFrm0PhyIrq */ + <0xff 58>, /* QTMR_qgicFrm1PhyIrq */ + <0xff 59>, /* QTMR_qgicFrm2PhyIrq */ + <0xff 60>, /* QTMR_qgicFrm3PhyIrq */ + <0xff 61>, /* QTMR_qgicFrm4PhyIrq */ + <0xff 62>, /* QTMR_qgicFrm5PhyIrq */ + <0xff 63>, /* QTMR_qgicFrm6PhyIrq */ + <0xff 64>, /* wakeup_counter_irq_OR */ + <0xff 65>, /* apc0_vs_alarm */ + <0xff 66>, /* apc1_vs_alarm */ + <0xff 67>, /* o_pwr_osm_irq */ + <0xff 68>, /* o_perf_osm_irq */ + <0xff 69>, /* o_pwr_dcvsh_interrupt */ + <0xff 70>, /* o_perf_dcvsh_interrupt */ + <0xff 73>, /* L2_EXTERRIRQ_C0 */ + <0xff 74>, /* L2_EXTERRIRQ_C1 */ + <0xff 75>, /* L2_INTERRIRQ_C0 */ + <0xff 76>, /* L2_INTERRIRQ_C1 */ + <0xff 77>, /* L2SPM_svicInt[0] */ + <0xff 78>, /* L2SPM_svicInt[1] */ + <0xff 79>, /* L2SPM_svicIntSwDone[0] */ + <0xff 80>, /* L2SPM_svicIntSwDone[1] */ + <0xff 81>, /* l2_avs_err[0] */ + <0xff 82>, /* l2_avs_err[1] */ + <0xff 83>, /* l2_avs_ack[0] */ + <0xff 84>, /* l2_avs_ack[1] */ + <0xff 96>, /* uart_dm_intr */ + <0xff 97>, /* uart_dm_intr */ + <0xff 98>, /* o_qm_interrupt */ + <0xff 100>, /* jpeg_vbif_irpt */ + <0xff 101>, /* processor_1_user_int */ + <0xff 102>, /* processor_1_kernel_int */ + <0xff 106>, /* dir_conn_irq_lpa_dsp_2 */ + <0xff 107>, /* dir_conn_irq_lpa_dsp_1 */ + <0xff 109>, /* camss_vbif_0_irq */ + <0xff 110>, /* csiphy_irq */ + <0xff 111>, /* csiphy_irq */ + <0xff 112>, /* csiphy_irq */ + <0xff 115>, /* mdp_irq */ + <0xff 116>, /* vbif_irpt */ + <0xff 117>, /* dir_conn_irq_lpa_dsp_0 */ + <0xff 119>, /* lcc_audio_wrapper_q6 */ + <0xff 122>, /* PIMEM TPDM BC interrupt */ + <0xff 123>, /* PIMEM TPDM TC interrupt */ + <0xff 124>, /* dir_conn_irq_sensors_1 */ + <0xff 125>, /* dir_conn_irq_sensors_0 */ + <0xff 126>, /* qup_irq */ + <0xff 127>, /* qup_irq */ + <0xff 128>, /* qup_irq */ + <0xff 129>, /* qup_irq */ + <0xff 130>, /* qup_irq */ + <0xff 131>, /* qup_irq */ + <0xff 132>, /* qup_irq */ + <0xff 133>, /* qup_irq */ + <0xff 134>, /* qup_irq */ + <0xff 135>, /* qup_irq */ + <0xff 136>, /* qup_irq */ + <0xff 137>, /* qup_irq */ + <0xff 138>, /* qup_irq */ + <0xff 139>, /* uart_dm_intr */ + <0xff 140>, /* uart_dm_intr */ + <0xff 141>, /* uart_dm_intr */ + <0xff 145>, /* uart_dm_intr */ + <0xff 146>, /* uart_dm_intr */ + <0xff 147>, /* uart_dm_intr */ + <0xff 148>, /* osmmu_Cirpt[4] */ + <0xff 149>, /* osmmu_Cirpt[5] */ + <0xff 151>, /* tsif_irq[0] */ + <0xff 152>, /* tsif_irq[1] */ + <0xff 153>, /* tspp_irq */ + <0xff 154>, /* bam_irq */ + <0xff 155>, /* dir_conn_irq_lpa_dsp_5 */ + <0xff 156>, /* dir_conn_irq_lpa_dsp_4 */ + <0xff 157>, /* sdcc_irq */ + <0xff 158>, /* sdcc_irq */ + <0xff 159>, /* lpass_qos_apps_interrupt */ + <0xff 160>, /* smmu_PMIrpt */ + <0xff 161>, /* sdcc_irq */ + <0xff 162>, /* sdcc_irq */ + <0xff 163>, /* usb30_ctrl_irq[0] */ + <0xff 164>, /* usb30_bam_irq */ + <0xff 165>, /* usb30_hs_phy_irq */ + <0xff 166>, /* o_lm_int_2qgic */ + <0xff 167>, /* pcie20_inta */ + <0xff 168>, /* pcie20_intb */ + <0xff 169>, /* smmu_Cirpt[12] */ + <0xff 170>, /* pcie20_intc */ + <0xff 171>, /* pcie20_intd */ + <0xff 172>, /* dcvs_int(8) */ + <0xff 173>, /* dcvs_int(9) */ + <0xff 184>, /* dir_conn_irq_lpa_dsp_3 */ + <0xff 185>, /* camss_vbif_2_irq */ + <0xff 186>, /* mnoc_obs_mainFault */ + <0xff 188>, /* q6ss_irq_out(4) */ + <0xff 189>, /* q6ss_irq_out(5) */ + <0xff 190>, /* q6ss_irq_out(6) */ + <0xff 191>, /* q6ss_irq_out(7) */ + <0xff 192>, /* audio_out0_irq */ + <0xff 194>, /* q6ss_wdog_exp_irq */ + <0xff 195>, /* lpass_slimbus_core_ee1_irq */ + <0xff 196>, /* lpass_slimbus_bam_ee1_irq */ + <0xff 197>, /* resampler_irq[0] */ + <0xff 199>, /* qdss_usb_trace_bam_irq */ + <0xff 200>, /* rpm_ipc[4] */ + <0xff 201>, /* rpm_ipc[5] */ + <0xff 202>, /* rpm_ipc[6] */ + <0xff 203>, /* rpm_ipc[7] */ + <0xff 204>, /* rpm_ipc[20] */ + <0xff 205>, /* rpm_ipc[21] */ + <0xff 206>, /* rpm_ipc[22] */ + <0xff 207>, /* rpm_ipc[23] */ + <0xff 208>, /* q6ss_irq_out(4) */ + <0xff 209>, /* q6ss_irq_out(5) */ + <0xff 210>, /* q6ss_irq_out(6) */ + <0xff 211>, /* q6ss_irq_out(7) */ + <0xff 213>, /* secure_wdog_bark_irq */ + <0xff 214>, /* tsens1_tsens_max_min_int */ + <0xff 215>, /* o_bimc_intr[0] */ + <0xff 217>, /* ocimem_nonsec_irq */ + <0xff 218>, /* sscaon_tmr_timeout_irq */ + <0xff 219>, /* q6ss_irq_out(28) */ + <0xff 220>, /* spmi_protocol_irq */ + <0xff 221>, /* q6ss_irq_out(29) */ + <0xff 222>, /* q6ss_irq_out(30) */ + <0xff 223>, /* spdm_offline_irq */ + <0xff 224>, /* spdm_realtime_irq */ + <0xff 225>, /* snoc_obs_mainFault */ + <0xff 226>, /* cnoc_obs_mainFault */ + <0xff 227>, /* o_ss_xpu3_sec_intr */ + <0xff 228>, /* o_tcsr_xpu3_non_sec_summary_intr */ + <0xff 229>, /* o_timeout_slave_kpss_summary_intr */ + <0xff 230>, /* o_tcsr_vmidmt_client_sec_summary_intr */ + <0xff 231>, /* o_tcsr_vmidmt_client_non_sec */ + <0xff 232>, /* o_tcsr_vmidmt_cfg_sec_summary_intr */ + <0xff 233>, /* o_tcsr_vmidmt_cfg_non_sec */ + <0xff 234>, /* q6ss_irq_out(31) */ + <0xff 235>, /* cpr_irq[0] */ + <0xff 236>, /* crypto_core_irq[0] */ + <0xff 237>, /* crypto_core_irq[1] */ + <0xff 238>, /* crypto_bam_irq[0] */ + <0xff 239>, /* crypto_bam_irq[1] */ + <0xff 240>, /* summary_irq_hmss */ + <0xff 241>, /* dir_conn_irq_hmss_7 */ + <0xff 242>, /* dir_conn_irq_hmss_6 */ + <0xff 243>, /* dir_conn_irq_hmss_5 */ + <0xff 244>, /* dir_conn_irq_hmss_4 */ + <0xff 245>, /* dir_conn_irq_hmss_3 */ + <0xff 246>, /* dir_conn_irq_hmss_2 */ + <0xff 247>, /* dir_conn_irq_hmss_1 */ + <0xff 248>, /* dir_conn_irq_hmss_0 */ + <0xff 249>, /* summary_irq_hmss_tz */ + <0xff 250>, /* cpr_irq[3] */ + <0xff 251>, /* cpr_irq[2] */ + <0xff 252>, /* cpr_irq[1] */ + <0xff 253>, /* sdcc_pwr_cmd_irq */ + <0xff 254>, /* sdio_wakeup_irq */ + <0xff 255>, /* cpr_irq[0] */ + <0xff 256>, /* smmu_Cirpt[13] */ + <0xff 257>, /* smmu_Cirpt[14] */ + <0xff 258>, /* smmu_Cirpt[0] */ + <0xff 259>, /* sdcc_pwr_cmd_irq */ + <0xff 260>, /* sdio_wakeup_irq */ + <0xff 261>, /* o_tcsr_mmu_nsgcfglrpt_summary_intr */ + <0xff 262>, /* o_tcsr_mmu_gcfglrpt_summary_intr */ + <0xff 263>, /* o_tcsr_mmu_nsglrpt_summary_intr */ + <0xff 264>, /* o_tcsr_mmu_glrpt_summary_intr */ + <0xff 265>, /* vbif_irpt */ + <0xff 266>, /* smmu_PMIrpt */ + <0xff 267>, /* smmu_Cirpt[3] */ + <0xff 268>, /* q6ss_irq_out(31) */ + <0xff 269>, /* rpm_wdog_expired_irq */ + <0xff 270>, /* bam_irq */ + <0xff 271>, /* bam_irq */ + <0xff 272>, /* q6ss_irq_out(28) */ + <0xff 273>, /* q6ss_irq_out(29) */ + <0xff 274>, /* q6ss_irq_out(30) */ + <0xff 276>, /* osmmu_Cirpt [4] */ + <0xff 277>, /* osmmu_Cirpt [5] */ + <0xff 278>, /* usb30_ctrl_irq[1] */ + <0xff 279>, /* osmmu_Cirpt [6] */ + <0xff 280>, /* osmmu_Cirpt [7] */ + <0xff 281>, /* osmmu_Cirpt [8] */ + <0xff 282>, /* osmmu_Cirpt [9] */ + <0xff 283>, /* osmmu_Cirpt [10] */ + <0xff 284>, /* osmmu_Cirpt [11] */ + <0xff 285>, /* osmmu_Cirpt [12] */ + <0xff 286>, /* osmmu_Cirpt [13] */ + <0xff 287>, /* osmmu_Cirpt [14] */ + <0xff 288>, /* osmmu_Cirpt [15] */ + <0xff 289>, /* ufs_ice_sec_level_irq */ + <0xff 290>, /* cpr_irq[4] */ + <0xff 291>, /* smmu_Cirpt[2] */ + <0xff 292>, /* osmmu_Cirpt [16] */ + <0xff 293>, /* osmmu_Cirpt [17] */ + <0xff 294>, /* osmmu_Cirpt [18] */ + <0xff 295>, /* osmmu_Cirpt [0] */ + <0xff 296>, /* osmmu_PMIrpt */ + <0xff 297>, /* ufs_intrq */ + <0xff 298>, /* osmmu_Cirpt [1] */ + <0xff 299>, /* osmmu_Cirpt [2] */ + <0xff 300>, /* osmmu_Cirpt [3] */ + <0xff 301>, /* smmu_Cirpt[1] */ + <0xff 302>, /* qdss_etrbytecnt_irq */ + <0xff 303>, /* smmu_Cirpt[0] */ + <0xff 304>, /* osmmu_Cirpt [19] */ + <0xff 305>, /* osmmu_Cirpt [20] */ + <0xff 306>, /* osmmu_Cirpt [21] */ + <0xff 307>, /* osmmu_Cirpt [22] */ + <0xff 308>, /* osmmu_Cirpt [23] */ + <0xff 310>, /* pcie20_global_int */ + <0xff 311>, /* pcie20_int_edma_int */ + <0xff 316>, /* lpass_hdmitx_interrupt_ext */ + <0xff 317>, /* rbif_irq */ + <0xff 318>, /* gpu_cc_gpu_cx_gds_hw_ctrl_irq_out */ + <0xff 319>, /* VENUS_IRQ */ + <0xff 323>, /* lpass_slimbus1_core_ee1_irq */ + <0xff 324>, /* lpass_slimbus1_bam_ee1_irq */ + <0xff 325>, /* camss_irq18 */ + <0xff 326>, /* camss_irq0 */ + <0xff 327>, /* camss_irq1 */ + <0xff 328>, /* camss_irq2 */ + <0xff 329>, /* camss_irq3 */ + <0xff 330>, /* camss_irq4 */ + <0xff 331>, /* camss_irq5 */ + <0xff 332>, /* GC_SYS_irq_0 */ + <0xff 333>, /* GC_SYS_irq_1 */ + <0xff 334>, /* GC_SYS_irq_2 */ + <0xff 335>, /* GC_SYS_irq_3 */ + <0xff 336>, /* camss_irq13 */ + <0xff 337>, /* camss_irq14 */ + <0xff 338>, /* camss_irq15 */ + <0xff 339>, /* camss_irq16 */ + <0xff 340>, /* camss_irq17 */ + <0xff 341>, /* camss_irq6 */ + <0xff 342>, /* smmu_Cirpt[15] */ + <0xff 343>, /* bam_irq[0] */ + <0xff 344>, /* uart_dm_intr */ + <0xff 345>, /* camss_irq7 */ + <0xff 346>, /* camss_irq8 */ + <0xff 347>, /* camss_irq9 */ + <0xff 348>, /* camss_irq10 */ + <0xff 350>, /* camss_irq12 */ + <0xff 351>, /* sif_aud_dec_out_irq_ext */ + <0xff 356>, /* vbif_nrt_irpt */ + <0xff 357>, /* Nonfatal pIMEM interrupt */ + <0xff 359>, /* spmi_periph_irq[1] */ + <0xff 360>, /* fatal pIMEM interrupt */ + <0xff 361>, /* osmmu_Cirpt[0] */ + <0xff 362>, /* osmmu_Cirpt[1] */ + <0xff 363>, /* osmmu_Cirpt[2] */ + <0xff 364>, /* osmmu_Cirpt[3] */ + <0xff 365>, /* ipa_irq(0) */ + <0xff 366>, /* osmmu_PMIrpt */ + <0xff 380>, /* sp_sp2apps_irq[0] */ + <0xff 381>, /* sp_sp2apps_irq[1] */ + <0xff 382>, /* sp_sp2apps_irq[2] */ + <0xff 383>, /* sp_sp2apps_irq[3] */ + <0xff 385>, /* osmmu_CIrpt[12] */ + <0xff 386>, /* osmmu_CIrpt[13] */ + <0xff 387>, /* osmmu_CIrpt[14] */ + <0xff 388>, /* osmmu_CIrpt[15] */ + <0xff 389>, /* osmmu_CIrpt[16] */ + <0xff 390>, /* osmmu_CIrpt[17] */ + <0xff 391>, /* osmmu_CIrpt[18] */ + <0xff 392>, /* osmmu_CIrpt[19] */ + <0xff 393>, /* o_dcc_crc_fail_int */ + <0xff 395>, /* aggre1_obs_mainfault */ + <0xff 396>, /* aggr1_smmu_cirpt[0] */ + <0xff 397>, /* aggr1_smmu_cirpt[1] */ + <0xff 398>, /* aggr1_smmu_cirpt[2] */ + <0xff 399>, /* aggr1_smmu_cirpt[3] */ + <0xff 400>, /* aggr1_smmu_cirpt[4] */ + <0xff 401>, /* aggr1_smmu_cirpt[5] */ + <0xff 402>, /* aggr1_smmu_cirpt[6] */ + <0xff 403>, /* aggr1_smmu_pmirpt */ + <0xff 404>, /* aggre2noc_obs_mainFault */ + <0xff 405>, /* osmmu_CIrpt[0] */ + <0xff 406>, /* osmmu_CIrpt[1] */ + <0xff 407>, /* osmmu_CIrpt[2] */ + <0xff 408>, /* osmmu_CIrpt[3] */ + <0xff 409>, /* osmmu_CIrpt[4] */ + <0xff 410>, /* osmmu_CIrpt[5] */ + <0xff 411>, /* o_dcc_task_done_int */ + <0xff 412>, /* vsense_alarm_irq */ + <0xff 413>, /* osmmu_PMIrpt */ + <0xff 414>, /* pmic_arb_trans_done_irq[0] */ + <0xff 415>, /* pmic_arb_trans_done_irq[1] */ + <0xff 416>, /* rpm_ipc[28] */ + <0xff 417>, /* rpm_ipc[29] */ + <0xff 418>, /* rpm_ipc[30] */ + <0xff 419>, /* rpm_ipc[31] */ + <0xff 420>, /* qup_irq */ + <0xff 421>, /* qup_irq */ + <0xff 422>, /* wd_bite_apps */ + <0xff 423>, /* lpass_qos_apps_interrupt */ + <0xff 424>, /* ipa_irq(2) */ + <0xff 425>, /* smmu_Cirpt[1] */ + <0xff 426>, /* smmu_Cirpt[2] */ + <0xff 427>, /* smmu_Cirpt[3] */ + <0xff 428>, /* smmu_Cirpt[4] */ + <0xff 429>, /* smmu_Cirpt[5] */ + <0xff 430>, /* smmu_Cirpt[6] */ + <0xff 431>, /* smmu_Cirpt[7] */ + <0xff 432>, /* smmu_Cirpt[8] */ + <0xff 433>, /* smmu_Cirpt[9] */ + <0xff 434>, /* smmu_Cirpt[10] */ + <0xff 435>, /* smmu_Cirpt[11] */ + <0xff 436>, /* smmu_Cirpt[16] */ + <0xff 437>, /* pcie20_0_int_msi_dev0 */ + <0xff 438>, /* pcie20_0_int_msi_dev1 */ + <0xff 439>, /* pcie20_0_int_msi_dev2 */ + <0xff 440>, /* pcie20_0_int_msi_dev3 */ + <0xff 441>, /* pcie20_0_int_msi_dev4 */ + <0xff 442>, /* pcie20_0_int_msi_dev5 */ + <0xff 443>, /* pcie20_0_int_msi_dev6 */ + <0xff 444>, /* pcie20_0_int_msi_dev7 */ + <0xff 445>, /* o_wcss_apps_intr[0] */ + <0xff 446>, /* o_wcss_apps_intr[1] */ + <0xff 447>, /* o_wcss_apps_intr[2] */ + <0xff 448>, /* o_wcss_apps_intr[3] */ + <0xff 449>, /* o_wcss_apps_intr[4] */ + <0xff 450>, /* o_wcss_apps_intr[5] */ + <0xff 452>, /* o_wcss_apps_intr[6] */ + <0xff 453>, /* o_wcss_apps_intr[7] */ + <0xff 454>, /* o_wcss_apps_intr[8] */ + <0xff 455>, /* o_wcss_apps_intr[9] */ + <0xff 456>, /* o_wcss_apps_intr[10] */ + <0xff 457>, /* o_wcss_apps_intr[11] */ + <0xff 458>, /* o_wcss_apps_intr[12] */ + <0xff 461>, /* o_ocimem_nonsec_irq */ + <0xff 462>, /* tsens1_tsens_critical_int */ + <0xff 463>, /* aggr1_smmu_cirpt[7] */ + <0xff 464>, /* ipa_bam_irq(0) */ + <0xff 465>, /* ipa_bam_irq(2) */ + <0xff 466>, /* ssc_uart_int */ + <0xff 468>, /* cri_cm_irq_tz */ + <0xff 469>, /* cri_cm_irq_hyp */ + <0xff 471>, /* mmss_bimc_smmu_gds_hw_ctrl_irq_out */ + <0xff 472>, /* gcc_gds_hw_ctrl_irq_out */ + <0xff 473>, /* lcc_audio_core_smmu_gds_hw_ctrl */ + <0xff 477>, /* tsens0_tsens_critical_int */ + <0xff 478>, /* tsens0_tsens_max_min_int */ + <0xff 480>, /* q6ss_wdog_expired_irq */ + <0xff 481>, /* mss_ipc_out_irq[4] */ + <0xff 482>, /* mss_ipc_out_irq[5] */ + <0xff 483>, /* mss_ipc_out_irq[6] */ + <0xff 484>, /* mss_ipc_out_irq[7] */ + <0xff 485>, /* mss_ipc_out_irq[28] */ + <0xff 486>, /* mss_ipc_out_irq[29] */ + <0xff 487>, /* mss_ipc_out_irq[30] */ + <0xff 488>, /* mss_ipc_out_irq[31] */ + <0xff 489>, /* skl_core_irq */ + <0xff 490>, /* tsens0_upper_lower_int */ + <0xff 494>, /* osmmu_CIrpt[6] */ + <0xff 495>, /* osmmu_CIrpt[7] */ + <0xff 496>, /* osmmu_CIrpt[8] */ + <0xff 497>, /* osmmu_CIrpt[9] */ + <0xff 498>, /* osmmu_CIrpt[10] */ + <0xff 499>, /* osmmu_CIrpt[11] */ + <0xff 503>; /* o_bimc_intr[1] */ + + qcom,gpio-parent = <&tlmm>; + qcom,gpio-map = <3 1>, + <4 5>, + <5 9>, + <6 11>, + <7 66>, + <8 22>, + <9 24>, + <10 26>, + <11 34>, + <12 36>, + <13 37>, /* PCIe0 */ + <14 38>, + <15 40>, + <16 42>, + <17 46>, + <18 50>, + <19 53>, + <20 54>, + <21 56>, + <22 57>, + <23 58>, + <24 59>, + <25 60>, + <26 61>, + <27 62>, + <28 63>, + <29 64>, + <30 71>, + <31 73>, + <32 77>, + <33 78>, + <34 79>, + <35 80>, + <36 82>, + <37 86>, + <38 91>, + <39 92>, + <40 95>, + <41 97>, + <42 101>, + <43 104>, + <44 106>, + <45 108>, + <46 112>, + <47 113>, + <48 110>, + <50 127>, + <51 115>, + <54 116>, /* PCIe2 */ + <55 117>, + <56 118>, + <57 119>, + <58 120>, + <59 121>, + <60 122>, + <61 123>, + <62 124>, + <63 125>, + <64 126>, + <65 129>, + <66 131>, + <67 132>, /* PCIe1 */ + <68 133>, + <69 145>; + }; +}; diff -Nruw linux-4.4.115-fbx/arch/arm/boot/dts/qcom./msm8998-ramoops.dtsi linux-4.4.115-fbx/arch/arm/boot/dts/qcom/msm8998-ramoops.dtsi --- linux-4.4.115-fbx/arch/arm/boot/dts/qcom./msm8998-ramoops.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ linux-4.4.115-fbx/arch/arm/boot/dts/qcom/msm8998-ramoops.dtsi 2019-01-22 16:16:21.199225542 +0100 @@ -0,0 +1,21 @@ + +/ { + reserved-memory { + + /* pstore test */ + ramoops_mem: ramoops_mem@0x88f00000 { + compatible = "removed-dma-pool"; + no-map; + reg = <0x0 0x88f00000 0x0 0x100000>; /* 1 MB */ + }; + }; + + /* pstore test */ + ramoops { + compatible = "ramoops"; + memory-region = <&ramoops_mem>; + record-size = <0x00100000>; /* 512 KB */ + ecc-size = <16>; + no-dump-oops; + }; +}; diff -Nruw linux-4.4.115-fbx/arch/arm/boot/dts/qcom./msm8998-regulator.dtsi linux-4.4.115-fbx/arch/arm/boot/dts/qcom/msm8998-regulator.dtsi --- linux-4.4.115-fbx/arch/arm/boot/dts/qcom./msm8998-regulator.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ linux-4.4.115-fbx/arch/arm/boot/dts/qcom/msm8998-regulator.dtsi 2019-01-22 16:16:21.199225542 +0100 @@ -0,0 +1,1145 @@ +/* Copyright (c) 2015-2017, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include + +&rpm_bus { + /* PM8998 S1 + S6 = VDD_CX supply */ + rpm-regulator-smpa1 { + status = "okay"; + pm8998_s1_level: regulator-s1-level { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm8998_s1_level"; + qcom,set = <3>; + regulator-min-microvolt = + ; + regulator-max-microvolt = + ; + qcom,use-voltage-level; + }; + + pm8998_s1_floor_level: regulator-s1-floor-level { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm8998_s1_floor_level"; + qcom,set = <3>; + regulator-min-microvolt = + ; + regulator-max-microvolt = + ; + qcom,use-voltage-floor-level; + qcom,always-send-voltage; + }; + + pm8998_s1_level_ao: regulator-s1-level-ao { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm8998_s1_level_ao"; + qcom,set = <1>; + regulator-min-microvolt = + ; + regulator-max-microvolt = + ; + qcom,use-voltage-level; + }; + }; + + rpm-regulator-smpa2 { + status = "okay"; + pm8998_s2: regulator-s2 { + regulator-min-microvolt = <1128000>; + regulator-max-microvolt = <1128000>; + status = "okay"; + }; + }; + + rpm-regulator-smpa3 { + status = "okay"; + pm8998_s3: regulator-s3 { + regulator-min-microvolt = <1352000>; + regulator-max-microvolt = <1352000>; + status = "okay"; + }; + }; + + rpm-regulator-smpa4 { + status = "okay"; + pm8998_s4: regulator-s4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + status = "okay"; + }; + }; + + rpm-regulator-smpa5 { + status = "okay"; + pm8998_s5: regulator-s5 { + regulator-min-microvolt = <1904000>; + regulator-max-microvolt = <2040000>; + qcom,init-pin-ctrl-mode = <8>; /* PMIC_AWAKE */ + qcom,send-defaults; + status = "okay"; + }; + }; + + rpm-regulator-smpa7 { + status = "okay"; + pm8998_s7: regulator-s7 { + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1028000>; + qcom,init-pin-ctrl-mode = <8>; /* PMIC_AWAKE */ + qcom,send-defaults; + status = "okay"; + }; + }; + + rpm-regulator-smpa8 { + status = "okay"; + pm8998_s8: regulator-s8 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <800000>; + status = "okay"; + }; + }; + + /* PM8998 S9 = VDD_MX supply */ + rpm-regulator-smpa9 { + status = "okay"; + pm8998_s9_level: regulator-s9-level { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm8998_s9_level"; + qcom,set = <3>; + regulator-min-microvolt = + ; + regulator-max-microvolt = + ; + qcom,use-voltage-level; + }; + + pm8998_s9_floor_level: regulator-s9-floor-level { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm8998_s9_floor_level"; + qcom,set = <3>; + regulator-min-microvolt = + ; + regulator-max-microvolt = + ; + qcom,use-voltage-floor-level; + qcom,always-send-voltage; + }; + + pm8998_s9_level_ao: regulator-s9-level-ao { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm8998_s9_level_ao"; + qcom,set = <1>; + regulator-min-microvolt = + ; + regulator-max-microvolt = + ; + qcom,use-voltage-level; + }; + }; + + rpm-regulator-ldoa1 { + status = "okay"; + pm8998_l1: regulator-l1 { + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + proxy-supply = <&pm8998_l1>; + qcom,proxy-consumer-enable; + qcom,proxy-consumer-current = <73400>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa2 { + status = "okay"; + pm8998_l2: regulator-l2 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + proxy-supply = <&pm8998_l2>; + qcom,proxy-consumer-enable; + qcom,proxy-consumer-current = <12560>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa3 { + status = "okay"; + pm8998_l3: regulator-l3 { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + status = "okay"; + }; + }; + + /* PM8998 L4 = VDD_SSC_MX supply */ + rpm-regulator-ldoa4 { + status = "okay"; + pm8998_l4_level: regulator-l4-level { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm8998_l4_level"; + qcom,set = <3>; + regulator-min-microvolt = + ; + regulator-max-microvolt = + ; + qcom,use-voltage-level; + }; + + pm8998_l4_floor_level: regulator-l4-floor-level { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm8998_l4_floor_level"; + qcom,set = <3>; + regulator-min-microvolt = + ; + regulator-max-microvolt = + ; + qcom,use-voltage-floor-level; + qcom,always-send-voltage; + }; + }; + + rpm-regulator-ldoa5 { + status = "okay"; + pm8998_l5: regulator-l5 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <800000>; + /* Force NPM follows HW0_EN */ + qcom,init-pin-ctrl-mode = <1>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa6 { + status = "okay"; + pm8998_l6: regulator-l6 { + regulator-min-microvolt = <1808000>; + regulator-max-microvolt = <1808000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa7 { + status = "okay"; + pm8998_l7: regulator-l7 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + status = "okay"; + }; + + pm8998_l7_pin_ctrl: regulator-l7-pin-ctrl { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm8998_l7_pin_ctrl"; + qcom,set = <3>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + /* Force NPM follows HW_EN2 */ + qcom,init-pin-ctrl-mode = <4>; + /* Enable follows HW_EN2 */ + qcom,enable-with-pin-ctrl = <0 4>; + }; + }; + + rpm-regulator-ldoa8 { + status = "okay"; + pm8998_l8: regulator-l8 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa9 { + status = "okay"; + pm8998_l9: regulator-l9 { + regulator-min-microvolt = <1808000>; + regulator-max-microvolt = <2960000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa10 { + status = "okay"; + pm8998_l10: regulator-l10 { + regulator-min-microvolt = <1808000>; + regulator-max-microvolt = <2960000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa11 { + status = "okay"; + pm8998_l11: regulator-l11 { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa12 { + status = "okay"; + pm8998_l12: regulator-l12 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa13 { + status = "okay"; + pm8998_l13: regulator-l13 { + regulator-min-microvolt = <1808000>; + regulator-max-microvolt = <2960000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa14 { + status = "okay"; + pm8998_l14: regulator-l14 { + regulator-min-microvolt = <1880000>; + regulator-max-microvolt = <1880000>; + proxy-supply = <&pm8998_l14>; + qcom,proxy-consumer-enable; + qcom,proxy-consumer-current = <32000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa15 { + status = "okay"; + pm8998_l15: regulator-l15 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa16 { + status = "okay"; + pm8998_l16: regulator-l16 { + regulator-min-microvolt = <2704000>; + regulator-max-microvolt = <2704000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa17 { + status = "okay"; + pm8998_l17: regulator-l17 { + regulator-min-microvolt = <1304000>; + regulator-max-microvolt = <1304000>; + status = "okay"; + }; + + pm8998_l17_pin_ctrl: regulator-l17-pin-ctrl { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm8998_l17_pin_ctrl"; + qcom,set = <3>; + regulator-min-microvolt = <1304000>; + regulator-max-microvolt = <1304000>; + /* Force NPM follows HW_EN2 */ + qcom,init-pin-ctrl-mode = <4>; + /* Enable follows HW_EN2 */ + qcom,enable-with-pin-ctrl = <0 4>; + }; + }; + + rpm-regulator-ldoa18 { + status = "okay"; + pm8998_l18: regulator-l18 { + regulator-min-microvolt = <2704000>; + regulator-max-microvolt = <2704000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa19 { + status = "okay"; + pm8998_l19: regulator-l19 { + regulator-min-microvolt = <3008000>; + regulator-max-microvolt = <3008000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa20 { + status = "okay"; + pm8998_l20: regulator-l20 { + regulator-min-microvolt = <2960000>; + regulator-max-microvolt = <2960000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa21 { + status = "okay"; + pm8998_l21: regulator-l21 { + regulator-min-microvolt = <2960000>; + regulator-max-microvolt = <2960000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa22 { + status = "okay"; + pm8998_l22: regulator-l22 { + regulator-min-microvolt = <2864000>; + regulator-max-microvolt = <2864000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa23 { + status = "okay"; + pm8998_l23: regulator-l23 { + regulator-min-microvolt = <3312000>; + regulator-max-microvolt = <3312000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa24 { + status = "okay"; + pm8998_l24: regulator-l24 { + regulator-min-microvolt = <1848000>; + regulator-max-microvolt = <3088000>; + parent-supply = <&pm8998_l12>; + status = "okay"; + }; + }; + rpm-regulator-ldoa25 { + status = "okay"; + pm8998_l25: regulator-l25 { + regulator-min-microvolt = <3104000>; + regulator-max-microvolt = <3312000>; + status = "okay"; + }; + + pm8998_l25_pin_ctrl: regulator-l25-pin-ctrl { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm8998_l25_pin_ctrl"; + qcom,set = <3>; + regulator-min-microvolt = <3104000>; + regulator-max-microvolt = <3312000>; + /* Force NPM follows HW_EN2 */ + qcom,init-pin-ctrl-mode = <4>; + /* Enable follows HW_EN2 */ + qcom,enable-with-pin-ctrl = <0 4>; + }; + }; + + rpm-regulator-ldoa26 { + status = "okay"; + pm8998_l26: regulator-l26 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + status = "okay"; + }; + }; + + /* PM8998 L27 = VDD_SSC_CX supply */ + rpm-regulator-ldoa27 { + status = "okay"; + pm8998_l27_level: regulator-l27-level { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm8998_l27_level"; + qcom,set = <3>; + regulator-min-microvolt = + ; + regulator-max-microvolt = + ; + qcom,use-voltage-level; + }; + + pm8998_l27_floor_level: regulator-l27-floor-level { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm8998_l27_floor_level"; + qcom,set = <3>; + regulator-min-microvolt = + ; + regulator-max-microvolt = + ; + qcom,use-voltage-floor-level; + qcom,always-send-voltage; + }; + }; + + rpm-regulator-ldoa28 { + status = "okay"; + pm8998_l28: regulator-l28 { + regulator-min-microvolt = <3008000>; + regulator-max-microvolt = <3008000>; + status = "okay"; + }; + }; + + rpm-regulator-vsa1 { + status = "okay"; + pm8998_lvs1: regulator-lvs1 { + status = "okay"; + }; + }; + + rpm-regulator-vsa2 { + status = "okay"; + pm8998_lvs2: regulator-lvs2 { + status = "okay"; + }; + }; + + rpm-regulator-bobb { + status = "okay"; + pmi8998_bob: regulator-bob { + regulator-min-microvolt = <3312000>; + regulator-max-microvolt = <3600000>; + qcom,pwm-threshold-current = <2000000>; + qcom,init-bob-mode = <2>; + status = "okay"; + }; + pmi8998_bob_pin1: regulator-bob-pin1 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm8998_bob_pin1"; + qcom,set = <3>; + regulator-min-microvolt = <3312000>; + regulator-max-microvolt = <3600000>; + qcom,pwm-threshold-current = <2000000>; + qcom,init-bob-mode = <2>; + qcom,use-pin-ctrl-voltage1; + }; + pmi8998_bob_pin2: regulator-bob-pin2 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm8998_bob_pin2"; + qcom,set = <3>; + regulator-min-microvolt = <3312000>; + regulator-max-microvolt = <3600000>; + qcom,pwm-threshold-current = <2000000>; + qcom,init-bob-mode = <2>; + qcom,use-pin-ctrl-voltage2; + }; + pmi8998_bob_pin3: regulator-bob-pin3 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm8998_bob_pin3"; + qcom,set = <3>; + regulator-min-microvolt = <3312000>; + regulator-max-microvolt = <3600000>; + qcom,pwm-threshold-current = <2000000>; + qcom,init-bob-mode = <2>; + qcom,use-pin-ctrl-voltage3; + }; + }; +}; + +&spmi_bus { + qcom,pm8005@5 { + /* PM8005 S1 + S4 = 2 phase VDD_GFX supply */ + pm8005_s1: regulator@1400 { + regulator-name = "pm8005_s1"; + status = "okay"; + regulator-min-microvolt = <524000>; + regulator-max-microvolt = <1100000>; + qcom,enable-time = <500>; + }; + }; + + qcom,pm8998@1 { + pm8998_s10: regulator@2f00 { + compatible = "qcom,qpnp-regulator"; + reg = <0x2f00 0x100>; + regulator-name = "pm8998_s10"; + regulator-min-microvolt = <572000>; + regulator-max-microvolt = <1112000>; + qcom,enable-time = <500>; + regulator-always-on; + }; + + pm8998_s13: regulator@3800 { + compatible = "qcom,qpnp-regulator"; + reg = <0x3800 0x100>; + regulator-name = "pm8998_s13"; + regulator-min-microvolt = <572000>; + regulator-max-microvolt = <1112000>; + qcom,enable-time = <500>; + regulator-always-on; + }; + }; +}; + +/* Stub regulators */ + +/ { + gfx_stub_vreg: regulator-gfx-stub { + compatible = "qcom,stub-regulator"; + regulator-name = "gfx_stub_corner"; + qcom,hpm-min-load = <100000>; + regulator-min-microvolt = <1>; + regulator-max-microvolt = <6>; + status = "disabled"; + }; +}; + +&soc { +/* CPR controller regulators */ + apc0_cpr: cprh-ctrl@179c8000 { + compatible = "qcom,cprh-msm8998-v1-kbss-regulator"; + reg = <0x179c8000 0x4000>, <0x00784000 0x1000>; + reg-names = "cpr_ctrl", "fuse_base"; + clocks = <&clock_gcc clk_gcc_hmss_rbcpr_clk>; + clock-names = "core_clk"; + qcom,cpr-ctrl-name = "apc0"; + qcom,cpr-controller-id = <0>; + + qcom,cpr-sensor-time = <1000>; + qcom,cpr-loop-time = <5000000>; + qcom,cpr-idle-cycles = <15>; + qcom,cpr-up-down-delay-time = <3000>; + qcom,cpr-step-quot-init-min = <11>; + qcom,cpr-step-quot-init-max = <12>; + qcom,cpr-count-mode = <0>; /* All at once */ + qcom,cpr-count-repeat = <1>; + qcom,cpr-down-error-step-limit = <1>; + qcom,cpr-up-error-step-limit = <1>; + qcom,cpr-corner-switch-delay-time = <209>; + qcom,cpr-voltage-settling-time = <1760>; + + qcom,apm-threshold-voltage = <832000>; + qcom,apm-crossover-voltage = <880000>; + qcom,apm-hysteresis-voltage = <32000>; + qcom,voltage-step = <4000>; + qcom,voltage-base = <352000>; + qcom,cpr-saw-use-unit-mV; + + qcom,cpr-enable; + qcom,cpr-hw-closed-loop; + + qcom,cpr-panic-reg-addr-list = + <0x179cbaa4 0x17912c18>; + qcom,cpr-panic-reg-name-list = + "PWR_CPRH_STATUS", "APCLUS0_L2_SAW4_PMIC_STS"; + + qcom,cpr-aging-ref-voltage = <1112000>; + vdd-supply = <&pm8998_s10>; + + thread@0 { + qcom,cpr-thread-id = <0>; + qcom,cpr-consecutive-up = <0>; + qcom,cpr-consecutive-down = <2>; + qcom,cpr-up-threshold = <2>; + qcom,cpr-down-threshold = <2>; + + apc0_pwrcl_vreg: regulator { + regulator-name = "apc0_pwrcl_corner"; + regulator-min-microvolt = <1>; + regulator-max-microvolt = <23>; + + qcom,cpr-fuse-corners = <4>; + qcom,cpr-fuse-combos = <8>; + qcom,cpr-corners = <22>; + + qcom,cpr-corner-fmax-map = <7 10 17 22>; + + qcom,cpr-voltage-ceiling = + <896000 896000 896000 896000 896000 + 896000 896000 896000 896000 896000 + 896000 896000 896000 896000 896000 + 896000 896000 1032000 1032000 1032000 + 1112000 1112000>; + + qcom,cpr-voltage-floor = + <896000 896000 896000 896000 896000 + 896000 896000 896000 896000 896000 + 896000 896000 896000 896000 896000 + 896000 896000 896000 896000 896000 + 896000 896000>, + <572000 572000 572000 572000 572000 + 572000 572000 572000 572000 572000 + 664000 664000 664000 664000 664000 + 664000 664000 752000 752000 752000 + 752000 752000>, + <572000 572000 572000 572000 572000 + 572000 572000 572000 572000 572000 + 664000 664000 664000 664000 664000 + 664000 664000 752000 752000 752000 + 752000 752000>, + <572000 572000 572000 572000 572000 + 572000 572000 572000 572000 572000 + 664000 664000 664000 664000 664000 + 664000 664000 752000 752000 752000 + 752000 752000>, + <572000 572000 572000 572000 572000 + 572000 572000 572000 572000 572000 + 664000 664000 664000 664000 664000 + 664000 664000 752000 752000 752000 + 752000 752000>, + <572000 572000 572000 572000 572000 + 572000 572000 572000 572000 572000 + 664000 664000 664000 664000 664000 + 664000 664000 752000 752000 752000 + 752000 752000>, + <572000 572000 572000 572000 572000 + 572000 572000 572000 572000 572000 + 664000 664000 664000 664000 664000 + 664000 664000 752000 752000 752000 + 752000 752000>, + <572000 572000 572000 572000 572000 + 572000 572000 572000 572000 572000 + 664000 664000 664000 664000 664000 + 664000 664000 752000 752000 752000 + 752000 752000>; + + qcom,cpr-floor-to-ceiling-max-range = + <55000 55000 55000 55000 + 55000 55000 55000 55000 + 55000 55000 65000 65000 + 65000 65000 65000 65000 + 65000 65000 65000 65000 + 65000 65000>; + + qcom,corner-frequencies = + <300000000 345600000 422400000 + 499200000 576000000 633600000 + 710400000 806400000 883200000 + 960000000 1036800000 1113600000 + 1190400000 1248000000 1324800000 + 1401600000 1478400000 1574400000 + 1651200000 1728000000 1804800000 + 1881600000>; + + qcom,cpr-ro-scaling-factor = + <3430 3512 3262 3426 3100 3238 2463 + 2725 1749 2891 4058 4014 3195 2866 + 0 0>, + <3430 3512 3262 3426 3100 3238 2463 + 2725 1749 2891 4058 4014 3195 2866 + 0 0>, + <3162 3153 3163 3261 3037 3135 2645 + 2857 1864 2417 3499 3706 3315 2771 + 0 0>, + <2632 2539 2835 2857 2767 2813 2690 + 2827 1857 1632 2596 3068 3212 2454 + 0 0>; + + qcom,cpr-open-loop-voltage-fuse-adjustment = + <0 0 0 0>, + <40000 24000 0 0>, + <40000 24000 0 0>, + <40000 24000 0 0>, + <40000 24000 0 0>, + <40000 24000 0 0>, + <40000 24000 0 0>, + <40000 24000 0 0>; + + qcom,cpr-closed-loop-voltage-fuse-adjustment = + <0 0 0 0>, + <20000 26000 0 0>, + <20000 26000 0 0>, + <20000 26000 0 0>, + <20000 26000 0 0>, + <20000 26000 0 0>, + <20000 26000 0 0>, + <20000 26000 0 0>; + + qcom,allow-voltage-interpolation; + qcom,allow-quotient-interpolation; + qcom,cpr-scaled-open-loop-voltage-as-ceiling; + + qcom,cpr-aging-max-voltage-adjustment = <15000>; + qcom,cpr-aging-ref-corner = <22>; + qcom,cpr-aging-ro-scaling-factor = <1620>; + qcom,allow-aging-voltage-adjustment = <0>; + qcom,allow-aging-open-loop-voltage-adjustment = + <1>; + }; + }; + }; + + apc1_cpr: cprh-ctrl@179c4000{ + compatible = "qcom,cprh-msm8998-v1-kbss-regulator"; + reg = <0x179c4000 0x4000>, <0x00784000 0x1000>; + reg-names = "cpr_ctrl", "fuse_base"; + clocks = <&clock_gcc clk_gcc_hmss_rbcpr_clk>; + clock-names = "core_clk"; + qcom,cpr-ctrl-name = "apc1"; + qcom,cpr-controller-id = <1>; + + qcom,cpr-sensor-time = <1000>; + qcom,cpr-loop-time = <5000000>; + qcom,cpr-idle-cycles = <15>; + qcom,cpr-up-down-delay-time = <3000>; + qcom,cpr-step-quot-init-min = <9>; + qcom,cpr-step-quot-init-max = <14>; + qcom,cpr-count-mode = <0>; /* All at once */ + qcom,cpr-count-repeat = <1>; + qcom,cpr-down-error-step-limit = <1>; + qcom,cpr-up-error-step-limit = <1>; + qcom,cpr-corner-switch-delay-time = <209>; + qcom,cpr-voltage-settling-time = <1760>; + + qcom,apm-threshold-voltage = <832000>; + qcom,apm-crossover-voltage = <880000>; + qcom,apm-hysteresis-voltage = <32000>; + qcom,voltage-step = <4000>; + qcom,voltage-base = <352000>; + qcom,cpr-saw-use-unit-mV; + + qcom,cpr-enable; + qcom,cpr-hw-closed-loop; + + qcom,cpr-panic-reg-addr-list = + <0x179c7aa4 0x17812c18>; + qcom,cpr-panic-reg-name-list = + "PERF_CPRH_STATUS", "APCLUS1_L2_SAW4_PMIC_STS"; + + qcom,cpr-aging-ref-voltage = <1112000>; + vdd-supply = <&pm8998_s13>; + + thread@0 { + qcom,cpr-thread-id = <0>; + qcom,cpr-consecutive-up = <0>; + qcom,cpr-consecutive-down = <2>; + qcom,cpr-up-threshold = <2>; + qcom,cpr-down-threshold = <2>; + + apc1_perfcl_vreg: regulator { + regulator-name = "apc1_perfcl_corner"; + regulator-min-microvolt = <1>; + regulator-max-microvolt = <26>; + + qcom,cpr-fuse-corners = <4>; + qcom,cpr-fuse-combos = <8>; + qcom,cpr-corners = <25>; + + qcom,cpr-corner-fmax-map = <8 12 18 25>; + + qcom,cpr-voltage-ceiling = + <896000 896000 896000 896000 + 896000 896000 896000 896000 + 896000 896000 896000 896000 + 896000 896000 896000 896000 + 896000 896000 1032000 1032000 + 1032000 1032000 1112000 1112000 + 1112000>; + + qcom,cpr-voltage-floor = + <896000 896000 896000 896000 + 896000 896000 896000 896000 + 896000 896000 896000 896000 + 896000 896000 896000 896000 + 896000 896000 896000 896000 + 896000 896000 896000 896000 + 896000>, + <572000 572000 572000 572000 + 572000 572000 572000 572000 + 572000 572000 572000 572000 + 664000 664000 664000 664000 + 664000 664000 752000 752000 + 752000 752000 752000 752000 + 752000>, + <572000 572000 572000 572000 + 572000 572000 572000 572000 + 572000 572000 572000 572000 + 664000 664000 664000 664000 + 664000 664000 752000 752000 + 752000 752000 752000 752000 + 752000>, + <572000 572000 572000 572000 + 572000 572000 572000 572000 + 572000 572000 572000 572000 + 664000 664000 664000 664000 + 664000 664000 752000 752000 + 752000 752000 752000 752000 + 752000>, + <572000 572000 572000 572000 + 572000 572000 572000 572000 + 572000 572000 572000 572000 + 664000 664000 664000 664000 + 664000 664000 752000 752000 + 752000 752000 752000 752000 + 752000>, + <572000 572000 572000 572000 + 572000 572000 572000 572000 + 572000 572000 572000 572000 + 664000 664000 664000 664000 + 664000 664000 752000 752000 + 752000 752000 752000 752000 + 752000>, + <572000 572000 572000 572000 + 572000 572000 572000 572000 + 572000 572000 572000 572000 + 664000 664000 664000 664000 + 664000 664000 752000 752000 + 752000 752000 752000 752000 + 752000>, + <572000 572000 572000 572000 + 572000 572000 572000 572000 + 572000 572000 572000 572000 + 664000 664000 664000 664000 + 664000 664000 752000 752000 + 752000 752000 752000 752000 + 752000>; + + qcom,cpr-floor-to-ceiling-max-range = + <55000 55000 55000 55000 + 55000 55000 55000 55000 + 55000 55000 55000 55000 + 65000 65000 65000 65000 + 65000 65000 65000 65000 + 65000 65000 65000 65000 + 65000>; + + qcom,corner-frequencies = + <300000000 345600000 422400000 + 480000000 556800000 633600000 + 710400000 787200000 844800000 + 902400000 979200000 1056000000 + 1171200000 1248000000 1324800000 + 1401600000 1478400000 1536000000 + 1632000000 1708800000 1785600000 + 1862400000 1939200000 2016000000 + 2092800000>; + + qcom,cpr-ro-scaling-factor = + <3430 3512 3262 3426 3100 3238 2463 + 2725 1749 2891 4058 4014 3195 2866 + 0 0>, + <3430 3512 3262 3426 3100 3238 2463 + 2725 1749 2891 4058 4014 3195 2866 + 0 0>, + <3162 3153 3163 3261 3037 3135 2645 + 2857 1864 2417 3499 3706 3315 2771 + 0 0>, + <2632 2539 2835 2857 2767 2813 2690 + 2827 1857 1632 2596 3068 3212 2454 + 0 0>; + + qcom,cpr-open-loop-voltage-fuse-adjustment = + <0 0 0 0>, + <8000 0 0 52000>, + <8000 0 0 52000>, + <8000 0 0 52000>, + <8000 0 0 52000>, + <8000 0 0 52000>, + <8000 0 0 52000>, + <8000 0 0 52000>; + + qcom,cpr-closed-loop-voltage-fuse-adjustment = + <0 0 0 0>, + <0 0 0 50000>, + <0 0 0 50000>, + <0 0 0 50000>, + <0 0 0 50000>, + <0 0 0 50000>, + <0 0 0 50000>, + <0 0 0 50000>; + + qcom,allow-voltage-interpolation; + qcom,allow-quotient-interpolation; + qcom,cpr-scaled-open-loop-voltage-as-ceiling; + + qcom,cpr-aging-max-voltage-adjustment = <15000>; + qcom,cpr-aging-ref-corner = <25>; + qcom,cpr-aging-ro-scaling-factor = <1700>; + qcom,allow-aging-voltage-adjustment = <0>; + qcom,allow-aging-open-loop-voltage-adjustment = + <1>; + }; + }; + }; + + gfx_cpr: cpr4-ctrl@5061000 { + compatible = "qcom,cpr4-msm8998-v1-mmss-regulator"; + reg = <0x05061000 0x4000>, + <0x00784000 0x1000>, + <0x05065204 0x4>; + reg-names = "cpr_ctrl", "fuse_base", "aging_allowed"; + clocks = <&clock_gpu clk_gpucc_rbcpr_clk>, + <&clock_gcc clk_cnoc_clk>; + clock-names = "core_clk", "bus_clk"; + interrupts = ; + interrupt-names = "cpr"; + qcom,cpr-ctrl-name = "gfx"; + + qcom,cpr-sensor-time = <1000>; + qcom,cpr-loop-time = <5000000>; + qcom,cpr-idle-cycles = <15>; + qcom,cpr-step-quot-init-min = <8>; + qcom,cpr-step-quot-init-max = <12>; + qcom,cpr-count-mode = <0>; /* All-at-once min */ + qcom,cpr-count-repeat = <1>; + + vdd-supply = <&pm8005_s1>; + qcom,voltage-step = <4000>; + mem-acc-supply = <&gfx_mem_acc_vreg>; + qcom,cpr-aging-ref-voltage = <1032000>; + qcom,cpr-aging-allowed-reg-mask = <0x00000003>; + qcom,cpr-aging-allowed-reg-value = <0x00000003>; + + qcom,cpr-enable; + + thread@0 { + qcom,cpr-thread-id = <0>; + qcom,cpr-consecutive-up = <0>; + qcom,cpr-consecutive-down = <2>; + qcom,cpr-up-threshold = <0>; + qcom,cpr-down-threshold = <2>; + + gfx_vreg: regulator { + regulator-name = "gfx_corner"; + regulator-min-microvolt = <1>; + regulator-max-microvolt = <6>; + + qcom,cpr-fuse-corners = <4>; + qcom,cpr-fuse-combos = <8>; + qcom,cpr-corners = <6>; + + qcom,cpr-corner-fmax-map = <1 3 5 6>; + + qcom,cpr-voltage-ceiling = + <896000 896000 896000 896000 896000 + 1032000>, + <672000 740000 800000 868000 976000 + 1100000>, + <672000 740000 800000 868000 976000 + 1100000>, + <672000 740000 800000 868000 976000 + 1100000>, + <672000 740000 800000 868000 976000 + 1100000>, + <672000 740000 800000 868000 976000 + 1100000>, + <672000 740000 800000 868000 976000 + 1100000>, + <672000 740000 800000 868000 976000 + 1100000>; + + qcom,cpr-voltage-floor = + <896000 896000 896000 896000 896000 + 896000>, + <528000 528000 568000 612000 664000 + 752000>, + <528000 528000 568000 612000 664000 + 752000>, + <528000 528000 568000 612000 664000 + 752000>, + <528000 528000 568000 612000 664000 + 752000>, + <528000 528000 568000 612000 664000 + 752000>, + <528000 528000 568000 612000 664000 + 752000>, + <528000 528000 568000 612000 664000 + 752000>; + + qcom,mem-acc-voltage = <1 1 1 2 2 2>; + + qcom,corner-frequencies = + <171000000 251000000 332000000 + 403000000 504000000 650000000>; + + qcom,cpr-target-quotients = + < 0 0 404 478 363 411 140 176 + 105 0 0 0 0 0 0 0>, + < 0 0 574 651 532 584 266 319 + 196 0 0 0 0 0 0 0>, + < 0 0 743 830 693 753 389 456 + 285 0 0 0 0 0 0 0>, + < 0 0 879 977 829 893 495 570 + 365 0 0 0 0 0 0 0>, + < 0 0 1168 1270 1097 1150 0 0 + 0 0 0 1406 899 805 0 0>, + <1669 1757 0 0 0 0 0 0 + 0 1359 1902 1740 0 1033 0 0>; + + qcom,cpr-ro-scaling-factor = + <2389 2287 2985 3112 2873 2904 2159 2399 + 1580 1602 2158 3042 2780 2069 0 0>, + <2389 2287 2985 3112 2873 2904 2159 2399 + 1580 1602 2158 3042 2780 2069 0 0>, + <2389 2287 2985 3112 2873 2904 2159 2399 + 1580 1602 2158 3042 2780 2069 0 0>, + <2389 2287 2985 3112 2873 2904 2159 2399 + 1580 1602 2158 3042 2780 2069 0 0>, + <2389 2287 2985 3112 2873 2904 2159 2399 + 1580 1602 2158 3042 2780 2069 0 0>, + <2389 2287 2985 3112 2873 2904 2159 2399 + 1580 1602 2158 3042 2780 2069 0 0>; + + qcom,cpr-open-loop-voltage-fuse-adjustment = + < 72000 0 0 0>, + < 72000 0 0 0>, + < 72000 0 0 0>, + < 72000 0 0 0>, + < 72000 0 0 0>, + < 72000 0 0 0>, + < 72000 0 0 0>, + < 72000 0 0 0>; + + qcom,cpr-closed-loop-voltage-adjustment = + < 65000 26000 8000 0 + 0 0>, + < 65000 26000 8000 0 + 0 0>, + < 65000 26000 8000 0 + 0 0>, + < 65000 26000 8000 0 + 0 0>, + < 65000 26000 8000 0 + 0 0>, + < 65000 26000 8000 0 + 0 0>, + < 65000 26000 8000 0 + 0 0>, + < 65000 26000 8000 0 + 0 0>; + + qcom,cpr-floor-to-ceiling-max-range = + <75000 75000 75000 75000 75000 75000>; + + qcom,cpr-fused-closed-loop-voltage-adjustment-map = + <0 0 1 2 3 4>; + + qcom,allow-voltage-interpolation; + qcom,cpr-scaled-open-loop-voltage-as-ceiling; + + qcom,cpr-aging-max-voltage-adjustment = <15000>; + qcom,cpr-aging-ref-corner = <6>; + qcom,cpr-aging-ro-scaling-factor = <2950>; + qcom,allow-aging-voltage-adjustment = <0>; + qcom,allow-aging-open-loop-voltage-adjustment = + <1>; + }; + }; + }; + + gfx_mem_acc_vreg: regulator@1fcf004 { + compatible = "qcom,mem-acc-regulator"; + reg = <0x01fcf004 0x4>; + reg-names = "acc-sel-l1"; + regulator-name = "gfx_mem_acc_corner"; + regulator-min-microvolt = <1>; + regulator-max-microvolt = <2>; + + qcom,corner-acc-map = <0x1 0x0>; + qcom,acc-sel-l1-bit-pos = <0>; + qcom,acc-sel-l1-bit-size = <1>; + }; +}; + +&pmi8998_charger { + smb2_vbus: qcom,smb2-vbus { + regulator-name = "smb2-vbus"; + }; + + smb2_vconn: qcom,smb2-vconn { + regulator-name = "smb2-vconn"; + }; +}; diff -Nruw linux-4.4.115-fbx/arch/arm/boot/dts/qcom./msm8998-sde-display.dtsi linux-4.4.115-fbx/arch/arm/boot/dts/qcom/msm8998-sde-display.dtsi --- linux-4.4.115-fbx/arch/arm/boot/dts/qcom./msm8998-sde-display.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ linux-4.4.115-fbx/arch/arm/boot/dts/qcom/msm8998-sde-display.dtsi 2019-01-22 16:16:21.199225542 +0100 @@ -0,0 +1,75 @@ +/* Copyright (c) 2017, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&soc { + + sde_wb: qcom,wb-display@0 { + compatible = "qcom,wb-display"; + cell-index = <0>; + label = "wb_display"; + }; + + msm_ext_disp: qcom,msm_ext_disp { + compatible = "qcom,msm-ext-disp"; + + ext_disp_audio_codec: qcom,msm-ext-disp-audio-codec-rx { + compatible = "qcom,msm-ext-disp-audio-codec-rx"; + qcom,msm_ext_disp = <&msm_ext_disp>; + }; + }; + + sde_hdmi: qcom,hdmi-display { + compatible = "qcom,hdmi-display"; + label = "sde_hdmi"; + qcom,display-type = "secondary"; + qcom,msm_ext_disp = <&msm_ext_disp>; + }; + + sde_hdmi_cec: qcom,hdmi-cec@c9a0000 { + compatible = "qcom,hdmi-cec"; + label = "sde_hdmi_cec"; + qcom,hdmi-dev = <&sde_hdmi>; + interrupt-parent = <&sde_hdmi_tx>; + interrupts = <1 0>; + + reg = <0xc9a0000 0x50c>; + reg-names = "hdmi_cec"; + + clocks = <&clock_mmss clk_mmss_mnoc_ahb_clk>, + <&clock_mmss clk_mmss_mdss_ahb_clk>, + <&clock_mmss clk_mmss_mdss_hdmi_clk>; + clock-names = "cec_mnoc_clk", "cec_iface_clk", "cec_core_clk"; + + pinctrl-names = "cec_active", "cec_sleep"; + pinctrl-0 = <&mdss_hdmi_cec_active>; + pinctrl-1 = <&mdss_hdmi_cec_suspend>; + + cec-gdsc-supply = <&gdsc_mdss>; + qcom,platform-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,platform-supply-entry@0 { + reg = <0>; + qcom,supply-name = "cec-gdsc"; + qcom,supply-min-voltage = <0>; + qcom,supply-max-voltage = <0>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + }; + }; + }; +}; + +&sde_kms { + connectors = <&sde_hdmi_tx &sde_hdmi &sde_wb>; +}; diff -Nruw linux-4.4.115-fbx/arch/arm/boot/dts/qcom./msm8998-sde.dtsi linux-4.4.115-fbx/arch/arm/boot/dts/qcom/msm8998-sde.dtsi --- linux-4.4.115-fbx/arch/arm/boot/dts/qcom./msm8998-sde.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ linux-4.4.115-fbx/arch/arm/boot/dts/qcom/msm8998-sde.dtsi 2019-01-22 16:16:21.199225542 +0100 @@ -0,0 +1,245 @@ +/* Copyright (c) 2017, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&soc { + sde_kms: qcom,sde_kms@c900000 { + compatible = "qcom,sde-kms"; + reg = <0x0c900000 0x90000>, + <0x0c9b0000 0x2008>; + reg-names = "mdp_phys", "vbif_phys"; + + /* clock and supply entries */ + clocks = <&clock_gcc clk_mmssnoc_axi_clk>, + <&clock_mmss clk_mmss_mnoc_ahb_clk>, + <&clock_mmss clk_mmss_bimc_smmu_ahb_clk>, + <&clock_mmss clk_mmss_bimc_smmu_axi_clk>, + <&clock_mmss clk_mmss_mnoc_ahb_clk>, + <&clock_mmss clk_mmss_mdss_ahb_clk>, + <&clock_mmss clk_mmss_mdss_axi_clk>, + <&clock_mmss clk_mdp_clk_src>, + <&clock_mmss clk_mmss_mdss_mdp_clk>, + <&clock_mmss clk_mmss_mdss_vsync_clk>, + <&clock_mmss clk_mmss_mdss_mdp_lut_clk>; + clock-names = "mmss_noc_axi_clk", + "mmss_noc_ahb_clk", + "mmss_smmu_ahb_clk", + "mmss_smmu_axi_clk", + "mnoc_clk", "iface_clk", "bus_clk", + "core_clk_src", "core_clk", "vsync_clk", + "lut_clk"; + clock-rate = <0 0 0 0 0 0 0 330000000 0 0 0 0>; + clock-max-rate = <0 0 0 0 0 0 412500000 412500000 0 0 0 0>; + qcom,sde-max-bw-low-kbps = <6700000>; + qcom,sde-max-bw-high-kbps = <6700000>; + + /* interrupt config */ + interrupt-parent = <&intc>; + interrupts = <0 83 0>; + interrupt-controller; + #interrupt-cells = <1>; + iommus = <&mmss_smmu 0>; + + gpus = <&msm_gpu>; + + /* hw blocks */ + qcom,sde-off = <0x1000>; + qcom,sde-len = <0x458>; + + qcom,sde-ctl-off = <0x2000 0x2200 0x2400 + 0x2600 0x2800>; + qcom,sde-ctl-size = <0x94>; + + qcom,sde-mixer-off = <0x45000 0x46000 0x47000 + 0x48000 0x49000 0x4a000>; + qcom,sde-mixer-size = <0x31c>; + + qcom,sde-dspp-off = <0x55000 0x57000>; + qcom,sde-dspp-size = <0x17e0>; + + qcom,sde-wb-off = <0x66000>; + qcom,sde-wb-size = <0x2dc>; + + qcom,sde-wb-id = <2>; + qcom,sde-wb-xin-id = <6>; + qcom,sde-wb-clk-ctrl = <0x2bc 0x10>; + qcom,sde-intf-off = <0x6b000 0x6b800 + 0x6c000 0x6c800>; + qcom,sde-intf-size = <0x280>; + + qcom,sde-intf-type = "dp", "dsi", "dsi", "hdmi"; + + qcom,sde-pp-off = <0x71000 0x71800 + 0x72000 0x72800 0x73000>; + qcom,sde-pp-slave = <0x0 0x0 0x0 0x0 0x1>; + + qcom,sde-pp-size = <0xd4>; + + qcom,sde-te2-off = <0x2000 0x2000 0x0 0x0 0x0>; + qcom,sde-cdm-off = <0x7a200>; + qcom,sde-cdm-size = <0x224>; + + qcom,sde-dsc-off = <0x81000 0x81400>; + qcom,sde-dsc-size = <0x140>; + + qcom,sde-intf-max-prefetch-lines = <0x15 0x15 0x15 0x15>; + + qcom,sde-sspp-type = "vig", "vig", "vig", "vig", + "dma", "dma", "dma", "dma", + "cursor", "cursor"; + + qcom,sde-sspp-off = <0x5000 0x7000 0x9000 0xb000 + 0x25000 0x27000 0x29000 0x2b000 + 0x35000 0x37000>; + qcom,sde-sspp-src-size = <0x1ac>; + + qcom,sde-sspp-xin-id = <0 4 8 12 1 5 9 13 2 10>; + + /* offsets are relative to "mdp_phys + qcom,sde-off */ + qcom,sde-sspp-clk-ctrl = <0x2ac 0x8>, <0x2b4 0x8>, + <0x2c4 0x8>, <0x2c4 0xc>, <0x3a8 0x10>, + <0x3b0 0x10>; + + qcom,sde-qseed-type = "qseedv3"; + qcom,sde-mixer-linewidth = <2560>; + qcom,sde-sspp-linewidth = <2560>; + qcom,sde-mixer-blendstages = <0x7>; + qcom,sde-highest-bank-bit = <0x2>; + qcom,sde-panic-per-pipe; + qcom,sde-has-cdp; + qcom,sde-has-src-split; + qcom,sde-sspp-danger-lut = <0x000f 0xffff 0x0000>; + qcom,sde-sspp-safe-lut = <0xfffc 0xff00 0xffff>; + + qcom,sde-vbif-off = <0>; + qcom,sde-vbif-id = <0>; + qcom,sde-vbif-default-ot-rd-limit = <32>; + qcom,sde-vbif-default-ot-wr-limit = <32>; + qcom,sde-vbif-dynamic-ot-rd-limit = <62208000 2>, + <124416000 4>, <248832000 16>; + qcom,sde-vbif-dynamic-ot-wr-limit = <62208000 2>, + <124416000 4>, <248832000 16>; + + vdd-supply = <&gdsc_mdss>; + gdsc-mmagic-mdss-supply = <&gdsc_bimc_smmu>; + qcom,sde-csc-type = "csc-10bit"; + + qcom,sde-sspp-vig-blocks { + qcom,sde-vig-csc-off = <0x1a00>; + qcom,sde-vig-qseed-off = <0xa00>; + qcom,sde-vig-qseed-size = <0xa0>; + }; + + qcom,platform-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,platform-supply-entry@0 { + reg = <0>; + qcom,supply-name = "gdsc-mmagic-mdss"; + qcom,supply-min-voltage = <0>; + qcom,supply-max-voltage = <0>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + }; + + qcom,platform-supply-entry@1 { + reg = <1>; + qcom,supply-name = "vdd"; + qcom,supply-min-voltage = <0>; + qcom,supply-max-voltage = <0>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + }; + }; + + smmu_kms_unsec: qcom,smmu_kms_unsec_cb { + compatible = "qcom,smmu_sde_unsec"; + iommus = <&mmss_smmu 0>; + }; + + smmu_kms_sec: qcom,smmu_kms_sec_cb { + compatible = "qcom,smmu_sde_sec"; + iommus = <&mmss_smmu 1>; + }; + + /* data and reg bus scale settings */ + qcom,sde-data-bus { + qcom,msm-bus,name = "mdss_sde"; + qcom,msm-bus,num-cases = <3>; + qcom,msm-bus,num-paths = <2>; + qcom,msm-bus,vectors-KBps = + <22 512 0 0>, <23 512 0 0>, + <22 512 0 6400000>, <23 512 0 6400000>, + <22 512 0 6400000>, <23 512 0 6400000>; + }; + qcom,sde-reg-bus { + qcom,msm-bus,name = "mdss_reg"; + qcom,msm-bus,num-cases = <4>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,active-only; + qcom,msm-bus,vectors-KBps = + <1 590 0 0>, + <1 590 0 76800>, + <1 590 0 160000>, + <1 590 0 320000>; + }; + }; + + sde_hdmi_tx: qcom,hdmi_tx_8998@c9a0000 { + cell-index = <0>; + compatible = "qcom,hdmi-tx-8998"; + reg = <0xc9a0000 0x50c>, + <0x780000 0x621c>, + <0xc9e0000 0x28>; + reg-names = "core_physical", "qfprom_physical", "hdcp_physical"; + interrupt-parent = <&sde_kms>; + interrupts = <8 0>; + interrupt-controller; + #interrupt-cells = <1>; + qcom,hdmi-tx-ddc-clk-gpio = <&tlmm 32 0>; + qcom,hdmi-tx-ddc-data-gpio = <&tlmm 33 0>; + qcom,hdmi-tx-hpd-gpio = <&tlmm 34 0>; + qcom,hdmi-tx-hpd5v-gpio = <&tlmm 133 0>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&mdss_hdmi_hpd_active + &mdss_hdmi_ddc_active + &mdss_hdmi_5v_active>; + pinctrl-1 = <&mdss_hdmi_hpd_suspend + &mdss_hdmi_ddc_suspend + &mdss_hdmi_5v_suspend>; + hpd-gdsc-supply = <&gdsc_mdss>; + qcom,supply-names = "hpd-gdsc"; + qcom,min-voltage-level = <0>; + qcom,max-voltage-level = <0>; + qcom,enable-load = <0>; + qcom,disable-load = <0>; + + clocks = <&clock_mmss clk_mmss_mnoc_ahb_clk>, + <&clock_mmss clk_mmss_mdss_ahb_clk>, + <&clock_mmss clk_mmss_mdss_hdmi_clk>, + <&clock_mmss clk_mmss_mdss_mdp_clk>, + <&clock_mmss clk_mmss_mdss_hdmi_dp_ahb_clk>, + <&clock_mmss clk_mmss_mdss_extpclk_clk>, + <&clock_mmss clk_mmss_mnoc_ahb_clk>, + <&clock_mmss clk_mmss_misc_ahb_clk>, + <&clock_mmss clk_mmss_mdss_axi_clk>; + clock-names = "hpd_mnoc_clk", "hpd_iface_clk", + "hpd_core_clk", "hpd_mdp_core_clk", + "hpd_alt_iface_clk", "core_extp_clk", + "mnoc_clk","hpd_misc_ahb_clk", + "hpd_bus_clk"; + + /*qcom,mdss-fb-map = <&mdss_fb2>;*/ + qcom,pluggable; + }; +}; +#include "msm8998-sde-display.dtsi" diff -Nruw linux-4.4.115-fbx/arch/arm/boot/dts/qcom./msm8998-smp2p.dtsi linux-4.4.115-fbx/arch/arm/boot/dts/qcom/msm8998-smp2p.dtsi --- linux-4.4.115-fbx/arch/arm/boot/dts/qcom./msm8998-smp2p.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ linux-4.4.115-fbx/arch/arm/boot/dts/qcom/msm8998-smp2p.dtsi 2019-01-22 16:16:21.199225542 +0100 @@ -0,0 +1,267 @@ +/* Copyright (c) 2015-2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +&soc { + qcom,smp2p-modem@17911008 { + compatible = "qcom,smp2p"; + reg = <0x17911008 0x4>; + qcom,remote-pid = <1>; + qcom,irq-bitmask = <0x4000>; + interrupts = <0 451 1>; + }; + + qcom,smp2p-adsp@17911008 { + compatible = "qcom,smp2p"; + reg = <0x17911008 0x4>; + qcom,remote-pid = <2>; + qcom,irq-bitmask = <0x400>; + interrupts = <0 158 1>; + }; + + qcom,smp2p-dsps@17911008 { + compatible = "qcom,smp2p"; + reg = <0x17911008 0x4>; + qcom,remote-pid = <3>; + qcom,irq-bitmask = <0x4000000>; + interrupts = <0 178 1>; + }; + + smp2pgpio_smp2p_15_in: qcom,smp2pgpio-smp2p-15-in { + compatible = "qcom,smp2pgpio"; + qcom,entry-name = "smp2p"; + qcom,remote-pid = <15>; + qcom,is-inbound; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + qcom,smp2pgpio_test_smp2p_15_in { + compatible = "qcom,smp2pgpio_test_smp2p_15_in"; + gpios = <&smp2pgpio_smp2p_15_in 0 0>; + }; + + smp2pgpio_smp2p_15_out: qcom,smp2pgpio-smp2p-15-out { + compatible = "qcom,smp2pgpio"; + qcom,entry-name = "smp2p"; + qcom,remote-pid = <15>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + qcom,smp2pgpio_test_smp2p_15_out { + compatible = "qcom,smp2pgpio_test_smp2p_15_out"; + gpios = <&smp2pgpio_smp2p_15_out 0 0>; + }; + + smp2pgpio_smp2p_1_in: qcom,smp2pgpio-smp2p-1-in { + compatible = "qcom,smp2pgpio"; + qcom,entry-name = "smp2p"; + qcom,remote-pid = <1>; + qcom,is-inbound; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + qcom,smp2pgpio_test_smp2p_1_in { + compatible = "qcom,smp2pgpio_test_smp2p_1_in"; + gpios = <&smp2pgpio_smp2p_1_in 0 0>; + }; + + smp2pgpio_smp2p_1_out: qcom,smp2pgpio-smp2p-1-out { + compatible = "qcom,smp2pgpio"; + qcom,entry-name = "smp2p"; + qcom,remote-pid = <1>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + qcom,smp2pgpio_test_smp2p_1_out { + compatible = "qcom,smp2pgpio_test_smp2p_1_out"; + gpios = <&smp2pgpio_smp2p_1_out 0 0>; + }; + + smp2pgpio_smp2p_2_in: qcom,smp2pgpio-smp2p-2-in { + compatible = "qcom,smp2pgpio"; + qcom,entry-name = "smp2p"; + qcom,remote-pid = <2>; + qcom,is-inbound; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + qcom,smp2pgpio_test_smp2p_2_in { + compatible = "qcom,smp2pgpio_test_smp2p_2_in"; + gpios = <&smp2pgpio_smp2p_2_in 0 0>; + }; + + smp2pgpio_smp2p_2_out: qcom,smp2pgpio-smp2p-2-out { + compatible = "qcom,smp2pgpio"; + qcom,entry-name = "smp2p"; + qcom,remote-pid = <2>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + qcom,smp2pgpio_test_smp2p_2_out { + compatible = "qcom,smp2pgpio_test_smp2p_2_out"; + gpios = <&smp2pgpio_smp2p_2_out 0 0>; + }; + + smp2pgpio_smp2p_3_in: qcom,smp2pgpio-smp2p-3-in { + compatible = "qcom,smp2pgpio"; + qcom,entry-name = "smp2p"; + qcom,remote-pid = <3>; + qcom,is-inbound; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + qcom,smp2pgpio_test_smp2p_3_in { + compatible = "qcom,smp2pgpio_test_smp2p_3_in"; + gpios = <&smp2pgpio_smp2p_3_in 0 0>; + }; + + smp2pgpio_smp2p_3_out: qcom,smp2pgpio-smp2p-3-out { + compatible = "qcom,smp2pgpio"; + qcom,entry-name = "smp2p"; + qcom,remote-pid = <3>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + /* ssr - inbound entry from mss */ + smp2pgpio_ssr_smp2p_1_in: qcom,smp2pgpio-ssr-smp2p-1-in { + compatible = "qcom,smp2pgpio"; + qcom,entry-name = "slave-kernel"; + qcom,remote-pid = <1>; + qcom,is-inbound; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + /* ssr - outbound entry to mss */ + smp2pgpio_ssr_smp2p_1_out: qcom,smp2pgpio-ssr-smp2p-1-out { + compatible = "qcom,smp2pgpio"; + qcom,entry-name = "master-kernel"; + qcom,remote-pid = <1>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + /* ssr - inbound entry from lpass */ + smp2pgpio_ssr_smp2p_2_in: qcom,smp2pgpio-ssr-smp2p-2-in { + compatible = "qcom,smp2pgpio"; + qcom,entry-name = "slave-kernel"; + qcom,remote-pid = <2>; + qcom,is-inbound; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + /* ssr - outbound entry to lpass */ + smp2pgpio_ssr_smp2p_2_out: qcom,smp2pgpio-ssr-smp2p-2-out { + compatible = "qcom,smp2pgpio"; + qcom,entry-name = "master-kernel"; + qcom,remote-pid = <2>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + /* ssr - inbound entry from ssc */ + smp2pgpio_ssr_smp2p_3_in: qcom,smp2pgpio-ssr-smp2p-3-in { + compatible = "qcom,smp2pgpio"; + qcom,entry-name = "slave-kernel"; + qcom,remote-pid = <3>; + qcom,is-inbound; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + /* ssr - outbound entry to ssc */ + smp2pgpio_ssr_smp2p_3_out: qcom,smp2pgpio-ssr-smp2p-3-out { + compatible = "qcom,smp2pgpio"; + qcom,entry-name = "master-kernel"; + qcom,remote-pid = <3>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + qcom,smp2pgpio_test_smp2p_3_out { + compatible = "qcom,smp2pgpio_test_smp2p_3_out"; + gpios = <&smp2pgpio_smp2p_3_out 0 0>; + }; + + smp2pgpio_sleepstate_3_out: qcom,smp2pgpio-sleepstate-gpio-3-out { + compatible = "qcom,smp2pgpio"; + qcom,entry-name = "sleepstate"; + qcom,remote-pid = <3>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + qcom,smp2pgpio-sleepstate-3-out { + compatible = "qcom,smp2pgpio_sleepstate_3_out"; + gpios = <&smp2pgpio_sleepstate_3_out 0 0>; + }; + + /* ipa - outbound entry to mss */ + smp2pgpio_ipa_1_out: qcom,smp2pgpio-ipa-1-out { + compatible = "qcom,smp2pgpio"; + qcom,entry-name = "ipa"; + qcom,remote-pid = <1>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + /* ipa - inbound entry from mss */ + smp2pgpio_ipa_1_in: qcom,smp2pgpio-ipa-1-in { + compatible = "qcom,smp2pgpio"; + qcom,entry-name = "ipa"; + qcom,remote-pid = <1>; + qcom,is-inbound; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; +}; diff -Nruw linux-4.4.115-fbx/arch/arm/boot/dts/qcom./msm8998-v2.1.dtsi linux-4.4.115-fbx/arch/arm/boot/dts/qcom/msm8998-v2.1.dtsi --- linux-4.4.115-fbx/arch/arm/boot/dts/qcom./msm8998-v2.1.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ linux-4.4.115-fbx/arch/arm/boot/dts/qcom/msm8998-v2.1.dtsi 2019-01-22 16:16:21.199225542 +0100 @@ -0,0 +1,18 @@ +/* Copyright (c) 2016 The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "msm8998-v2.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. MSM8998 v2.1"; + qcom,msm-id = <292 0x20001>; +}; diff -Nruw linux-4.4.115-fbx/arch/arm/boot/dts/qcom./msm8998-v2-camera.dtsi linux-4.4.115-fbx/arch/arm/boot/dts/qcom/msm8998-v2-camera.dtsi --- linux-4.4.115-fbx/arch/arm/boot/dts/qcom./msm8998-v2-camera.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ linux-4.4.115-fbx/arch/arm/boot/dts/qcom/msm8998-v2-camera.dtsi 2019-01-22 16:16:21.199225542 +0100 @@ -0,0 +1,192 @@ +/* + * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&soc { + qcom,csiphy@ca34000 { + cell-index = <0>; + compatible = "qcom,csiphy-v5.01", "qcom,csiphy"; + reg = <0xca34000 0x1000>; + reg-names = "csiphy"; + interrupts = <0 78 0>; + interrupt-names = "csiphy"; + gdscr-supply = <&gdsc_camss_top>; + bimc_smmu-supply = <&gdsc_bimc_smmu>; + qcom,cam-vreg-name = "gdscr", "bimc_smmu"; + clocks = <&clock_gcc clk_mmssnoc_axi_clk>, + <&clock_mmss clk_mmss_mnoc_ahb_clk>, + <&clock_mmss clk_mmss_bimc_smmu_ahb_clk>, + <&clock_mmss clk_mmss_bimc_smmu_axi_clk>, + <&clock_mmss clk_mmss_camss_ahb_clk>, + <&clock_mmss clk_mmss_camss_top_ahb_clk>, + <&clock_mmss clk_csi0_clk_src>, + <&clock_mmss clk_mmss_camss_csi0_clk>, + <&clock_mmss clk_mmss_camss_cphy_csid0_clk>, + <&clock_mmss clk_csi0phytimer_clk_src>, + <&clock_mmss clk_mmss_camss_csi0phytimer_clk>, + <&clock_mmss clk_mmss_camss_ispif_ahb_clk>, + <&clock_mmss clk_csiphy_clk_src>, + <&clock_mmss clk_mmss_camss_csiphy0_clk>; + clock-names = "mmssnoc_axi", "mnoc_ahb", + "bmic_smmu_ahb", "bmic_smmu_axi", + "camss_ahb_clk", "camss_top_ahb_clk", + "csi_src_clk", "csi_clk", "cphy_csid_clk", + "csiphy_timer_src_clk", "csiphy_timer_clk", + "camss_ispif_ahb_clk", "csiphy_clk_src", "csiphy_clk"; + qcom,clock-rates = <0 0 0 0 0 0 274290000 0 0 200000000 0 + 0 274290000 0>; + status = "ok"; + }; + + qcom,csiphy@ca35000 { + cell-index = <1>; + compatible = "qcom,csiphy-v5.01", "qcom,csiphy"; + reg = <0xca35000 0x1000>; + reg-names = "csiphy"; + interrupts = <0 79 0>; + interrupt-names = "csiphy"; + gdscr-supply = <&gdsc_camss_top>; + bimc_smmu-supply = <&gdsc_bimc_smmu>; + qcom,cam-vreg-name = "gdscr", "bimc_smmu"; + clocks = <&clock_gcc clk_mmssnoc_axi_clk>, + <&clock_mmss clk_mmss_mnoc_ahb_clk>, + <&clock_mmss clk_mmss_bimc_smmu_ahb_clk>, + <&clock_mmss clk_mmss_bimc_smmu_axi_clk>, + <&clock_mmss clk_mmss_camss_ahb_clk>, + <&clock_mmss clk_mmss_camss_top_ahb_clk>, + <&clock_mmss clk_csi1_clk_src>, + <&clock_mmss clk_mmss_camss_csi1_clk>, + <&clock_mmss clk_mmss_camss_cphy_csid1_clk>, + <&clock_mmss clk_csi1phytimer_clk_src>, + <&clock_mmss clk_mmss_camss_csi1phytimer_clk>, + <&clock_mmss clk_mmss_camss_ispif_ahb_clk>, + <&clock_mmss clk_csiphy_clk_src>, + <&clock_mmss clk_mmss_camss_csiphy1_clk>; + clock-names = "mmssnoc_axi", "mnoc_ahb", + "bmic_smmu_ahb", "bmic_smmu_axi", + "camss_ahb_clk", "camss_top_ahb_clk", + "csi_src_clk", "csi_clk", "cphy_csid_clk", + "csiphy_timer_src_clk", "csiphy_timer_clk", + "camss_ispif_ahb_clk", "csiphy_clk_src", "csiphy_clk"; + qcom,clock-rates = <0 0 0 0 0 0 274290000 0 0 200000000 0 + 0 274290000 0>; + status = "ok"; + }; + + qcom,csiphy@ca36000 { + cell-index = <2>; + compatible = "qcom,csiphy-v5.01", "qcom,csiphy"; + reg = <0xca36000 0x1000>; + reg-names = "csiphy"; + interrupts = <0 80 0>; + interrupt-names = "csiphy"; + gdscr-supply = <&gdsc_camss_top>; + bimc_smmu-supply = <&gdsc_bimc_smmu>; + qcom,cam-vreg-name = "gdscr", "bimc_smmu"; + clocks = <&clock_gcc clk_mmssnoc_axi_clk>, + <&clock_mmss clk_mmss_mnoc_ahb_clk>, + <&clock_mmss clk_mmss_bimc_smmu_ahb_clk>, + <&clock_mmss clk_mmss_bimc_smmu_axi_clk>, + <&clock_mmss clk_mmss_camss_ahb_clk>, + <&clock_mmss clk_mmss_camss_top_ahb_clk>, + <&clock_mmss clk_csi2_clk_src>, + <&clock_mmss clk_mmss_camss_csi2_clk>, + <&clock_mmss clk_mmss_camss_cphy_csid2_clk>, + <&clock_mmss clk_csi2phytimer_clk_src>, + <&clock_mmss clk_mmss_camss_csi2phytimer_clk>, + <&clock_mmss clk_mmss_camss_ispif_ahb_clk>, + <&clock_mmss clk_csiphy_clk_src>, + <&clock_mmss clk_mmss_camss_csiphy2_clk>; + clock-names = "mmssnoc_axi", "mnoc_ahb", + "bmic_smmu_ahb", "bmic_smmu_axi", + "camss_ahb_clk", "camss_top_ahb_clk", + "csi_src_clk", "csi_clk", "cphy_csid_clk", + "csiphy_timer_src_clk", "csiphy_timer_clk", + "camss_ispif_ahb_clk", "csiphy_clk_src", "csiphy_clk"; + qcom,clock-rates = <0 0 0 0 0 0 274290000 0 0 200000000 0 + 0 274290000 0>; + status = "ok"; + }; + + qcom,cpp@ca04000 { + cell-index = <0>; + compatible = "qcom,cpp"; + reg = <0xca04000 0x100>, + <0xca80000 0x3000>, + <0xca18000 0x3000>, + <0xc8c36d4 0x4>; + reg-names = "cpp", "cpp_vbif", "cpp_hw", "camss_cpp"; + interrupts = <0 294 0>; + interrupt-names = "cpp"; + smmu-vdd-supply = <&gdsc_bimc_smmu>; + camss-vdd-supply = <&gdsc_camss_top>; + vdd-supply = <&gdsc_cpp>; + qcom,vdd-names = "smmu-vdd", "camss-vdd", "vdd"; + clocks = <&clock_gcc clk_mmssnoc_axi_clk>, + <&clock_mmss clk_mmss_mnoc_ahb_clk>, + <&clock_mmss clk_mmss_camss_ahb_clk>, + <&clock_mmss clk_mmss_camss_top_ahb_clk>, + <&clock_mmss clk_cpp_clk_src>, + <&clock_mmss clk_mmss_camss_cpp_clk>, + <&clock_mmss clk_mmss_camss_cpp_ahb_clk>, + <&clock_mmss clk_mmss_camss_cpp_axi_clk>, + <&clock_mmss clk_mmss_camss_micro_ahb_clk>, + <&clock_mmss clk_mmss_bimc_smmu_axi_clk>, + <&clock_mmss clk_mmss_camss_cpp_vbif_ahb_clk>; + clock-names = "mmssnoc_axi_clk", + "mnoc_ahb_clk", + "camss_ahb_clk", "camss_top_ahb_clk", + "cpp_src_clk", + "cpp_core_clk", "camss_cpp_ahb_clk", + "camss_cpp_axi_clk", "micro_iface_clk", + "mmss_smmu_axi_clk", "cpp_vbif_ahb_clk"; + qcom,clock-rates = <0 0 0 0 200000000 200000000 0 0 0 0 0>; + qcom,min-clock-rate = <200000000>; + qcom,bus-master = <1>; + qcom,vbif-qos-setting = <0x20 0x10000000>, + <0x24 0x10000000>, + <0x28 0x10000000>, + <0x2C 0x10000000>; + status = "ok"; + qcom,msm-bus,name = "msm_camera_cpp"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <106 512 0 0>, + <106 512 0 0>; + qcom,msm-bus-vector-dyn-vote; + resets = <&clock_mmss CAMSS_MICRO_BCR>; + reset-names = "micro_iface_reset"; + qcom,src-clock-rates = <100000000 200000000 384000000 404000000 + 480000000 576000000 600000000>; + qcom,micro-reset; + qcom,cpp-fw-payload-info { + qcom,stripe-base = <790>; + qcom,plane-base = <715>; + qcom,stripe-size = <63>; + qcom,plane-size = <25>; + qcom,fe-ptr-off = <11>; + qcom,we-ptr-off = <23>; + qcom,ref-fe-ptr-off = <17>; + qcom,ref-we-ptr-off = <36>; + qcom,we-meta-ptr-off = <42>; + qcom,fe-mmu-pf-ptr-off = <7>; + qcom,ref-fe-mmu-pf-ptr-off = <10>; + qcom,we-mmu-pf-ptr-off = <13>; + qcom,dup-we-mmu-pf-ptr-off = <18>; + qcom,ref-we-mmu-pf-ptr-off = <23>; + qcom,set-group-buffer-len = <135>; + qcom,dup-frame-indicator-off = <70>; + }; + }; +}; + diff -Nruw linux-4.4.115-fbx/arch/arm/boot/dts/qcom./msm8998-v2.dtsi linux-4.4.115-fbx/arch/arm/boot/dts/qcom/msm8998-v2.dtsi --- linux-4.4.115-fbx/arch/arm/boot/dts/qcom./msm8998-v2.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ linux-4.4.115-fbx/arch/arm/boot/dts/qcom/msm8998-v2.dtsi 2019-01-22 16:16:21.203225578 +0100 @@ -0,0 +1,1312 @@ +/* Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * As a general rule, only version-specific property overrides should be placed + * inside this file. Common device definitions should be placed inside the + * msm8998.dtsi file. + */ + +#include "msm8998.dtsi" +#include "msm8998-v2-camera.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. MSM8998 v2"; + qcom,msm-id = <292 0x20000>; +}; + +&clock_cpu { + compatible = "qcom,cpu-clock-osm-msm8998-v2"; + reg = <0x179c0000 0x4000>, + <0x17916000 0x1000>, + <0x17816000 0x1000>, + <0x179d1000 0x1000>, + <0x17914800 0x800>, + <0x17814800 0x800>, + <0x00784130 0x8>, + <0x1791101c 0x8>; + reg-names = "osm", "pwrcl_pll", "perfcl_pll", + "apcs_common", "pwrcl_acd", "perfcl_acd", + "perfcl_efuse", "debug"; + + qcom,acdtd-val = <0x00009611 0x00009611>; + qcom,acdcr-val = <0x002b5ffd 0x002b5ffd>; + qcom,acdsscr-val = <0x00000501 0x00000501>; + qcom,acdextint0-val = <0x2cf9ae8 0x2cf9ae8>; + qcom,acdextint1-val = <0x2cf9afe 0x2cf9afe>; + qcom,acdautoxfer-val = <0x00000015 0x00000015>; + qcom,pwrcl-apcs-mem-acc-threshold-voltage = <852000>; + qcom,perfcl-apcs-mem-acc-threshold-voltage = <852000>; + qcom,apm-threshold-voltage = <800000>; + + /delete-property/ qcom,llm-sw-overr; + qcom,pwrcl-speedbin0-v0 = + < 300000000 0x0004000f 0x01200020 0x1 1 >, + < 364800000 0x05040013 0x01200020 0x1 2 >, + < 441600000 0x05040017 0x02200020 0x1 3 >, + < 518400000 0x0504001b 0x02200020 0x1 4 >, + < 595200000 0x0504001f 0x02200020 0x1 5 >, + < 672000000 0x05040023 0x03200020 0x1 6 >, + < 748800000 0x05040027 0x03200020 0x1 7 >, + < 825600000 0x0404002b 0x03220022 0x1 8 >, + < 883200000 0x0404002e 0x04250025 0x1 9 >, + < 960000000 0x04040032 0x04280028 0x1 10 >, + < 1036800000 0x04040036 0x042b002b 0x1 11 >, + < 1094400000 0x04040039 0x052e002e 0x2 12 >, + < 1171200000 0x0404003d 0x05310031 0x2 13 >, + < 1248000000 0x04040041 0x05340034 0x2 14 >, + < 1324800000 0x04040045 0x06370037 0x2 15 >, + < 1401600000 0x04040049 0x063a003a 0x2 16 >, + < 1478400000 0x0404004d 0x073e003e 0x2 17 >, + < 1555200000 0x04040051 0x07410041 0x2 18 >, + < 1670400000 0x04040057 0x08460046 0x2 19 >, + < 1747200000 0x0404005b 0x08490049 0x2 20 >, + < 1824000000 0x0404005f 0x084c004c 0x3 21 >, + < 1900800000 0x04040063 0x094f004f 0x3 22 >; + + qcom,perfcl-speedbin0-v0 = + < 300000000 0x0004000f 0x01200020 0x1 1 >, + < 345600000 0x05040012 0x01200020 0x1 2 >, + < 422400000 0x05040016 0x02200020 0x1 3 >, + < 499200000 0x0504001a 0x02200020 0x1 4 >, + < 576000000 0x0504001e 0x02200020 0x1 5 >, + < 652800000 0x05040022 0x03200020 0x1 6 >, + < 729600000 0x05040026 0x03200020 0x1 7 >, + < 806400000 0x0504002a 0x03220022 0x1 8 >, + < 902400000 0x0404002f 0x04260026 0x1 9 >, + < 979200000 0x04040033 0x04290029 0x1 10 >, + < 1056000000 0x04040037 0x052c002c 0x1 11 >, + < 1132800000 0x0404003b 0x052f002f 0x1 12 >, + < 1190400000 0x0404003e 0x05320032 0x2 13 >, + < 1267200000 0x04040042 0x06350035 0x2 14 >, + < 1344000000 0x04040046 0x06380038 0x2 15 >, + < 1420800000 0x0404004a 0x063b003b 0x2 16 >, + < 1497600000 0x0404004e 0x073e003e 0x2 17 >, + < 1574400000 0x04040052 0x07420042 0x2 18 >, + < 1651200000 0x04040056 0x07450045 0x2 19 >, + < 1728000000 0x0404005a 0x08480048 0x2 20 >, + < 1804800000 0x0404005e 0x084b004b 0x2 21 >, + < 1881600000 0x04040062 0x094e004e 0x2 22 >, + < 1958400000 0x04040066 0x09520052 0x2 23 >, + < 2035200000 0x0404006a 0x09550055 0x3 24 >, + < 2112000000 0x0404006e 0x0a580058 0x3 25 >, + < 2208000000 0x04040073 0x0a5c005c 0x3 26 >, + < 2265600000 0x04010076 0x0a5e005e 0x3 26 >, + < 2265600000 0x04040076 0x0a5e005e 0x3 27 >, + < 2342400000 0x0401007a 0x0a620062 0x3 27 >, + < 2342400000 0x0404007a 0x0a620062 0x3 28 >, + < 2419200000 0x0401007e 0x0a650065 0x3 28 >, + < 2419200000 0x0404007e 0x0a650065 0x3 29 >, + < 2496000000 0x04010082 0x0a680068 0x3 29 >, + < 2457600000 0x04040080 0x0a660066 0x3 30 >, + < 2553600000 0x04010085 0x0a6a006a 0x3 30 >, + < 2476800000 0x04040081 0x0a670067 0x3 31 >, + < 2572800000 0x04010086 0x0a6b006b 0x3 31 >, + < 2496000000 0x04040082 0x0a680068 0x3 32 >, + < 2592000000 0x04010087 0x0a6c006c 0x3 32 >; + + qcom,perfcl-speedbin1-v0 = + < 300000000 0x0004000f 0x01200020 0x1 1 >, + < 345600000 0x05040012 0x01200020 0x1 2 >, + < 422400000 0x05040016 0x02200020 0x1 3 >, + < 499200000 0x0504001a 0x02200020 0x1 4 >, + < 576000000 0x0504001e 0x02200020 0x1 5 >, + < 652800000 0x05040022 0x03200020 0x1 6 >, + < 729600000 0x05040026 0x03200020 0x1 7 >, + < 806400000 0x0504002a 0x03220022 0x1 8 >, + < 902400000 0x0404002f 0x04260026 0x1 9 >, + < 979200000 0x04040033 0x04290029 0x1 10 >, + < 1056000000 0x04040037 0x052c002c 0x1 11 >, + < 1132800000 0x0404003b 0x052f002f 0x1 12 >, + < 1190400000 0x0404003e 0x05320032 0x2 13 >, + < 1267200000 0x04040042 0x06350035 0x2 14 >, + < 1344000000 0x04040046 0x06380038 0x2 15 >, + < 1420800000 0x0404004a 0x063b003b 0x2 16 >, + < 1497600000 0x0404004e 0x073e003e 0x2 17 >, + < 1574400000 0x04040052 0x07420042 0x2 18 >, + < 1651200000 0x04040056 0x07450045 0x2 19 >, + < 1728000000 0x0404005a 0x08480048 0x2 20 >, + < 1804800000 0x0404005e 0x084b004b 0x2 21 >, + < 1881600000 0x04040062 0x094e004e 0x2 22 >, + < 1958400000 0x04040066 0x09520052 0x2 23 >, + < 2035200000 0x0404006a 0x09550055 0x3 24 >, + < 2112000000 0x0404006e 0x0a580058 0x3 25 >, + < 2208000000 0x04040073 0x0a5c005c 0x3 26 >, + < 2304000000 0x04010078 0x0a600060 0x3 26 >; + + qcom,perfcl-speedbin2-v0 = + < 300000000 0x0004000f 0x01200020 0x1 1 >, + < 345600000 0x05040012 0x01200020 0x1 2 >, + < 422400000 0x05040016 0x02200020 0x1 3 >, + < 499200000 0x0504001a 0x02200020 0x1 4 >, + < 576000000 0x0504001e 0x02200020 0x1 5 >, + < 652800000 0x05040022 0x03200020 0x1 6 >, + < 729600000 0x05040026 0x03200020 0x1 7 >, + < 806400000 0x0504002a 0x03220022 0x1 8 >, + < 902400000 0x0404002f 0x04260026 0x1 9 >, + < 979200000 0x04040033 0x04290029 0x1 10 >, + < 1056000000 0x04040037 0x052c002c 0x1 11 >, + < 1132800000 0x0404003b 0x052f002f 0x1 12 >, + < 1190400000 0x0404003e 0x05320032 0x2 13 >, + < 1267200000 0x04040042 0x06350035 0x2 14 >, + < 1344000000 0x04040046 0x06380038 0x2 15 >, + < 1420800000 0x0404004a 0x063b003b 0x2 16 >, + < 1497600000 0x0404004e 0x073e003e 0x2 17 >, + < 1574400000 0x04040052 0x07420042 0x2 18 >, + < 1651200000 0x04040056 0x07450045 0x2 19 >, + < 1728000000 0x0404005a 0x08480048 0x2 20 >, + < 1804800000 0x0404005e 0x084b004b 0x2 21 >, + < 1881600000 0x04040062 0x094e004e 0x2 22 >, + < 1958400000 0x04040066 0x09520052 0x2 23 >, + < 2035200000 0x0404006a 0x09550055 0x3 24 >, + < 2112000000 0x0404006e 0x0a580058 0x3 25 >, + < 2208000000 0x04040073 0x0a5c005c 0x3 26 >, + < 2265600000 0x04010076 0x0a5e005e 0x3 26 >, + < 2265600000 0x04040076 0x0a5e005e 0x3 27 >, + < 2342400000 0x0401007a 0x0a620062 0x3 27 >, + < 2323200000 0x04040079 0x0a610061 0x3 28 >, + < 2419200000 0x0401007e 0x0a650065 0x3 28 >, + < 2342400000 0x0404007a 0x0a620062 0x3 29 >, + < 2438400000 0x0401007f 0x0a660066 0x3 29 >, + < 2361600000 0x0404007b 0x0a620062 0x3 30 >, + < 2457600000 0x04010080 0x0a660066 0x3 30 >; + + qcom,perfcl-speedbin3-v0 = + < 300000000 0x0004000f 0x01200020 0x1 1 >, + < 345600000 0x05040012 0x01200020 0x1 2 >, + < 422400000 0x05040016 0x02200020 0x1 3 >, + < 499200000 0x0504001a 0x02200020 0x1 4 >, + < 576000000 0x0504001e 0x02200020 0x1 5 >, + < 652800000 0x05040022 0x03200020 0x1 6 >, + < 729600000 0x05040026 0x03200020 0x1 7 >, + < 806400000 0x0504002a 0x03220022 0x1 8 >, + < 902400000 0x0404002f 0x04260026 0x1 9 >, + < 979200000 0x04040033 0x04290029 0x1 10 >, + < 1056000000 0x04040037 0x052c002c 0x1 11 >, + < 1132800000 0x0404003b 0x052f002f 0x1 12 >, + < 1190400000 0x0404003e 0x05320032 0x2 13 >, + < 1267200000 0x04040042 0x06350035 0x2 14 >, + < 1344000000 0x04040046 0x06380038 0x2 15 >, + < 1420800000 0x0404004a 0x063b003b 0x2 16 >, + < 1497600000 0x0404004e 0x073e003e 0x2 17 >, + < 1574400000 0x04040052 0x07420042 0x2 18 >, + < 1651200000 0x04040056 0x07450045 0x2 19 >, + < 1728000000 0x0404005a 0x08480048 0x2 20 >, + < 1804800000 0x0404005e 0x084b004b 0x2 21 >, + < 1881600000 0x04040062 0x094e004e 0x2 22 >, + < 1958400000 0x04040066 0x09520052 0x2 23 >, + < 2035200000 0x0404006a 0x09550055 0x3 24 >, + < 2112000000 0x0404006e 0x0a580058 0x3 25 >, + < 2208000000 0x04040073 0x0a5c005c 0x3 26 >, + < 2265600000 0x04010076 0x0a5e005e 0x3 26 >, + < 2265600000 0x04040076 0x0a5e005e 0x3 27 >, + < 2342400000 0x0401007a 0x0a620062 0x3 27 >, + < 2323200000 0x04040079 0x0a610061 0x3 28 >, + < 2419200000 0x0401007e 0x0a650065 0x3 28 >, + < 2342400000 0x0404007a 0x0a620062 0x3 29 >, + < 2438400000 0x0401007f 0x0a660066 0x3 29 >, + < 2361600000 0x0404007b 0x0a620062 0x3 30 >, + < 2457600000 0x04010080 0x0a660066 0x3 30 >; +}; + +&msm_cpufreq { + qcom,cpufreq-table-0 = + < 300000 >, + < 364800 >, + < 441600 >, + < 518400 >, + < 595200 >, + < 672000 >, + < 748800 >, + < 825600 >, + < 883200 >, + < 960000 >, + < 1036800 >, + < 1094400 >, + < 1171200 >, + < 1248000 >, + < 1324800 >, + < 1401600 >, + < 1478400 >, + < 1555200 >, + < 1670400 >, + < 1747200 >, + < 1824000 >, + < 1900800 >; + + qcom,cpufreq-table-4 = + < 300000 >, + < 345600 >, + < 422400 >, + < 499200 >, + < 576000 >, + < 652800 >, + < 729600 >, + < 806400 >, + < 902400 >, + < 979200 >, + < 1056000 >, + < 1132800 >, + < 1190400 >, + < 1267200 >, + < 1344000 >, + < 1420800 >, + < 1497600 >, + < 1574400 >, + < 1651200 >, + < 1728000 >, + < 1804800 >, + < 1881600 >, + < 1958400 >, + < 2035200 >, + < 2112000 >, + < 2208000 >, + < 2265600 >, + < 2304000 >, + < 2323200 >, + < 2342400 >, + < 2361600 >, + < 2419200 >, + < 2457600 >, + < 2476800 >, + < 2496000 >, + < 2592000 >; +}; + +&bwmon { + compatible = "qcom,bimc-bwmon4"; + qcom,hw-timer-hz = <19200000>; +}; + +&devfreq_cpufreq { + mincpubw-cpufreq { + cpu-to-dev-map-0 = + < 1900800 1525 >; + cpu-to-dev-map-4 = + < 2112000 1525 >, + < 2342400 5195 >, + < 2496000 13763 >; + }; +}; + +&devfreq_memlat_0 { + qcom,core-dev-table = + < 300000 1525 >, + < 595200 3143 >, + < 1324800 4173 >, + < 1555200 5859 >, + < 1747200 5859 >, + < 1900800 7759 >; +}; + +&devfreq_memlat_4 { + qcom,core-dev-table = + < 576000 3143 >, + < 1132800 4173 >, + < 1344000 5859 >, + < 1728000 7759 >, + < 1958400 11863 >, + < 2208000 13763 >; +}; +&clock_gcc { + compatible = "qcom,gcc-8998-v2"; +}; + +&clock_mmss { + compatible = "qcom,mmsscc-8998-v2"; +}; + +&clock_gpu { + compatible = "qcom,gpucc-8998-v2"; +}; + +&clock_gfx { + compatible = "qcom,gfxcc-8998-v2"; + qcom,gfxfreq-speedbin0 = + < 0 0 0 >, + < 180000000 1 RPM_SMD_REGULATOR_LEVEL_SVS >, + < 257000000 2 RPM_SMD_REGULATOR_LEVEL_SVS >, + < 342000000 3 RPM_SMD_REGULATOR_LEVEL_SVS >, + < 414000000 4 RPM_SMD_REGULATOR_LEVEL_SVS >, + < 515000000 5 RPM_SMD_REGULATOR_LEVEL_NOM >, + < 596000000 6 RPM_SMD_REGULATOR_LEVEL_NOM >, + < 670000000 7 RPM_SMD_REGULATOR_LEVEL_TURBO >, + < 710000000 8 RPM_SMD_REGULATOR_LEVEL_TURBO >; + qcom,gfxfreq-mx-speedbin0 = + < 0 0 >, + < 180000000 RPM_SMD_REGULATOR_LEVEL_SVS >, + < 257000000 RPM_SMD_REGULATOR_LEVEL_SVS >, + < 342000000 RPM_SMD_REGULATOR_LEVEL_SVS >, + < 414000000 RPM_SMD_REGULATOR_LEVEL_SVS >, + < 515000000 RPM_SMD_REGULATOR_LEVEL_NOM >, + < 596000000 RPM_SMD_REGULATOR_LEVEL_NOM >, + < 670000000 RPM_SMD_REGULATOR_LEVEL_TURBO >, + < 710000000 RPM_SMD_REGULATOR_LEVEL_TURBO >; +}; + +&pm8998_s10 { + regulator-min-microvolt = <568000>; + regulator-max-microvolt = <1056000>; +}; + +&pm8998_s13 { + regulator-min-microvolt = <568000>; + regulator-max-microvolt = <1136000>; +}; + +&pcie0 { + qcom,phy-sequence = <0x804 0x01 0x00 + 0x034 0x14 0x00 + 0x138 0x30 0x00 + 0x048 0x0f 0x00 + 0x15c 0x06 0x00 + 0x090 0x01 0x00 + 0x088 0x20 0x00 + 0x0f0 0x00 0x00 + 0x0f8 0x01 0x00 + 0x0f4 0xc9 0x00 + 0x11c 0xff 0x00 + 0x120 0x3f 0x00 + 0x164 0x01 0x00 + 0x154 0x00 0x00 + 0x148 0x0a 0x00 + 0x05C 0x19 0x00 + 0x038 0x90 0x00 + 0x0b0 0x82 0x00 + 0x0c0 0x03 0x00 + 0x0bc 0x55 0x00 + 0x0b8 0x55 0x00 + 0x0a0 0x00 0x00 + 0x09c 0x0d 0x00 + 0x098 0x04 0x00 + 0x13c 0x00 0x00 + 0x060 0x08 0x00 + 0x068 0x16 0x00 + 0x070 0x34 0x00 + 0x15c 0x06 0x00 + 0x138 0x33 0x00 + 0x03c 0x02 0x00 + 0x040 0x07 0x00 + 0x080 0x04 0x00 + 0x0dc 0x00 0x00 + 0x0d8 0x3f 0x00 + 0x00c 0x09 0x00 + 0x010 0x01 0x00 + 0x01c 0x40 0x00 + 0x020 0x01 0x00 + 0x014 0x02 0x00 + 0x018 0x00 0x00 + 0x024 0x7e 0x00 + 0x028 0x15 0x00 + 0x244 0x02 0x00 + 0x2a4 0x12 0x00 + 0x260 0x10 0x00 + 0x28c 0x06 0x00 + 0x504 0x03 0x00 + 0x500 0x1c 0x00 + 0x50c 0x14 0x00 + 0x4d4 0x0a 0x00 + 0x4d8 0x04 0x00 + 0x4dc 0x1a 0x00 + 0x434 0x4b 0x00 + 0x414 0x04 0x00 + 0x40c 0x04 0x00 + 0x4f8 0x00 0x00 + 0x4fc 0x80 0x00 + 0x51c 0x40 0x00 + 0x444 0x71 0x00 + 0x43c 0x40 0x00 + 0x854 0x04 0x00 + 0x62c 0x52 0x00 + 0x9ac 0x00 0x00 + 0x8a0 0x01 0x00 + 0x9e0 0x00 0x00 + 0x9dc 0x20 0x00 + 0x9a8 0x00 0x00 + 0x8a4 0x01 0x00 + 0x8a8 0x73 0x00 + 0x9d8 0x99 0x00 + 0x9b0 0x03 0x00 + 0x804 0x03 0x00 + 0x800 0x00 0x00 + 0x808 0x03 0x00>; +}; + +&apc0_cpr { + compatible = "qcom,cprh-msm8998-v2-kbss-regulator"; + qcom,cpr-corner-switch-delay-time = <1042>; + qcom,cpr-aging-ref-voltage = <1056000>; + qcom,apm-threshold-voltage = <800000>; + qcom,apm-hysteresis-voltage = <0>; + qcom,mem-acc-threshold-voltage = <852000>; + qcom,mem-acc-crossover-voltage = <852000>; +}; + +&apc0_pwrcl_vreg { + regulator-max-microvolt = <23>; + + qcom,cpr-fuse-combos = <32>; + qcom,cpr-speed-bins = <4>; + qcom,cpr-speed-bin-corners = <22 22 22 22>; + qcom,cpr-corners = <22>; + + qcom,cpr-corner-fmax-map = <8 11 18 22>; + + qcom,cpr-voltage-ceiling = + <828000 828000 828000 828000 828000 + 828000 828000 828000 828000 828000 + 828000 900000 900000 900000 900000 + 900000 900000 900000 952000 952000 + 1056000 1056000>; + + qcom,cpr-voltage-floor = + <568000 568000 568000 568000 568000 + 568000 568000 568000 568000 568000 + 568000 632000 632000 632000 632000 + 632000 632000 632000 712000 712000 + 772000 772000>; + + qcom,cpr-floor-to-ceiling-max-range = + <32000 32000 32000 32000 + 32000 32000 32000 32000 + 32000 32000 32000 32000 + 32000 32000 32000 32000 + 32000 32000 40000 40000 + 40000 40000>; + + qcom,corner-frequencies = + <300000000 364800000 441600000 + 518400000 595200000 672000000 + 748800000 825600000 883200000 + 960000000 1036800000 1094400000 + 1171200000 1248000000 1324800000 + 1401600000 1478400000 1555200000 + 1670400000 1747200000 1824000000 + 1900800000>; + + qcom,cpr-ro-scaling-factor = + <2595 2794 2577 2762 2471 2674 2199 + 2553 3189 3255 3192 2962 3054 2982 + 2042 2945>, + <2595 2794 2577 2762 2471 2674 2199 + 2553 3189 3255 3192 2962 3054 2982 + 2042 2945>, + <2391 2550 2483 2638 2382 2564 2259 + 2555 2766 3041 2988 2935 2873 2688 + 2013 2784>, + <2066 2153 2300 2434 2220 2386 2288 + 2465 2028 2511 2487 2734 2554 2117 + 1892 2377>; + + qcom,cpr-open-loop-voltage-fuse-adjustment = + /* Speed bin 0 */ + <40000 24000 12000 30000>, + <40000 24000 12000 30000>, + <40000 24000 12000 30000>, + <40000 24000 12000 30000>, + <40000 24000 12000 30000>, + <40000 24000 12000 30000>, + <40000 24000 12000 30000>, + <40000 24000 12000 30000>, + /* Speed bin 1 */ + <40000 24000 12000 30000>, + <40000 24000 12000 30000>, + <40000 24000 12000 30000>, + <40000 24000 12000 30000>, + <40000 24000 12000 30000>, + <40000 24000 12000 30000>, + <40000 24000 12000 30000>, + <40000 24000 12000 30000>, + /* Speed bin 2 */ + <40000 24000 12000 30000>, + <40000 24000 12000 30000>, + <40000 24000 12000 30000>, + <40000 24000 12000 30000>, + <40000 24000 12000 30000>, + <40000 24000 12000 30000>, + <40000 24000 12000 30000>, + <40000 24000 12000 30000>, + /* Speed bin 3 */ + <40000 24000 12000 30000>, + <40000 24000 12000 30000>, + <40000 24000 12000 30000>, + <40000 24000 12000 30000>, + <40000 24000 12000 30000>, + <40000 24000 12000 30000>, + <40000 24000 12000 30000>, + <40000 24000 12000 30000>; + + qcom,cpr-closed-loop-voltage-fuse-adjustment = + /* Speed bin 0 */ + <20000 26000 12000 30000>, + <20000 26000 12000 30000>, + <20000 26000 12000 30000>, + <20000 26000 12000 30000>, + <20000 26000 12000 30000>, + <20000 26000 12000 30000>, + <20000 26000 12000 30000>, + <20000 26000 12000 30000>, + /* Speed bin 1 */ + <20000 26000 12000 30000>, + <20000 26000 12000 30000>, + <20000 26000 12000 30000>, + <20000 26000 12000 30000>, + <20000 26000 12000 30000>, + <20000 26000 12000 30000>, + <20000 26000 12000 30000>, + <20000 26000 12000 30000>, + /* Speed bin 2 */ + <20000 26000 12000 30000>, + <20000 26000 12000 30000>, + <20000 26000 12000 30000>, + <20000 26000 12000 30000>, + <20000 26000 12000 30000>, + <20000 26000 12000 30000>, + <20000 26000 12000 30000>, + <20000 26000 12000 30000>, + /* Speed bin 3 */ + <20000 26000 12000 30000>, + <20000 26000 12000 30000>, + <20000 26000 12000 30000>, + <20000 26000 12000 30000>, + <20000 26000 12000 30000>, + <20000 26000 12000 30000>, + <20000 26000 12000 30000>, + <20000 26000 12000 30000>; + + qcom,cpr-open-loop-voltage-adjustment = + /* Speed bin 0 */ + < 0 0 0 0 0 + 0 0 0 0 0 + 0 (-12000) (-12000) (-12000) (-12000) + (-12000) (-16000) (-16000) (-20000) (-24000) + (-28000) (-28000)>, + /* Speed bin 1 */ + < 0 0 0 0 0 + 0 0 0 0 0 + 0 (-12000) (-12000) (-12000) (-12000) + (-12000) (-16000) (-16000) (-20000) (-24000) + (-28000) (-28000)>, + /* Speed bin 2 */ + < 0 0 0 0 0 + 0 0 0 0 0 + 0 (-12000) (-12000) (-12000) (-12000) + (-12000) (-16000) (-16000) (-20000) (-24000) + (-28000) (-28000)>, + /* Speed bin 3 */ + < 0 0 0 0 0 + 0 0 0 0 0 + 0 (-12000) (-12000) (-12000) (-12000) + (-12000) (-16000) (-16000) (-20000) (-24000) + (-28000) (-28000)>; + + qcom,cpr-closed-loop-voltage-adjustment = + /* Speed bin 0 */ + < 0 0 0 0 0 + 0 0 0 0 0 + 0 (-10000) (-11000) (-12000) (-13000) + (-14000) (-14000) (-15000) (-21000) (-24000) + (-26000) (-28000)>, + /* Speed bin 1 */ + < 0 0 0 0 0 + 0 0 0 0 0 + 0 (-10000) (-11000) (-12000) (-13000) + (-14000) (-14000) (-15000) (-21000) (-24000) + (-26000) (-28000)>, + /* Speed bin 2 */ + < 0 0 0 0 0 + 0 0 0 0 0 + 0 (-10000) (-11000) (-12000) (-13000) + (-14000) (-14000) (-15000) (-21000) (-24000) + (-26000) (-28000)>, + /* Speed bin 3 */ + < 0 0 0 0 0 + 0 0 0 0 0 + 0 (-10000) (-11000) (-12000) (-13000) + (-14000) (-14000) (-15000) (-21000) (-24000) + (-26000) (-28000)>; + + qcom,allow-voltage-interpolation; + qcom,allow-quotient-interpolation; + qcom,cpr-scaled-open-loop-voltage-as-ceiling; + + qcom,cpr-aging-ref-corner = <22>; + qcom,cpr-aging-ro-scaling-factor = <1620>; + qcom,allow-aging-voltage-adjustment = <0>; +}; + +&apc1_cpr { + compatible = "qcom,cprh-msm8998-v2-kbss-regulator"; + qcom,cpr-corner-switch-delay-time = <1042>; + qcom,cpr-aging-ref-voltage = <1136000>; + qcom,apm-threshold-voltage = <800000>; + qcom,apm-hysteresis-voltage = <0>; + qcom,mem-acc-threshold-voltage = <852000>; + qcom,mem-acc-crossover-voltage = <852000>; +}; + +&apc1_perfcl_vreg { + regulator-max-microvolt = <34>; + + qcom,cpr-fuse-combos = <32>; + qcom,cpr-speed-bins = <4>; + qcom,cpr-speed-bin-corners = <32 26 30 31>; + qcom,cpr-corners = + /* Speed bin 0 */ + <32 32 32 32 32 32 32 32>, + /* Speed bin 1 */ + <26 26 26 26 26 26 26 26>, + /* Speed bin 2 */ + <30 30 30 30 30 30 30 30>, + /* Speed bin 3 */ + <31 31 31 31 31 31 31 31>; + + qcom,cpr-corner-fmax-map = + /* Speed bin 0 */ + <8 12 20 32>, + /* Speed bin 1 */ + <8 12 20 26>, + /* Speed bin 2 */ + <8 12 20 30>, + /* Speed bin 3 */ + <8 12 20 31>; + + qcom,cpr-voltage-ceiling = + /* Speed bin 0 */ + <828000 828000 828000 828000 828000 + 828000 828000 828000 828000 828000 + 828000 828000 900000 900000 900000 + 900000 900000 900000 900000 900000 + 952000 952000 952000 1136000 1136000 + 1136000 1136000 1136000 1136000 1136000 + 1136000 1136000>, + /* Speed bin 1 */ + <828000 828000 828000 828000 828000 + 828000 828000 828000 828000 828000 + 828000 828000 900000 900000 900000 + 900000 900000 900000 900000 900000 + 952000 952000 952000 1136000 1136000 + 1136000>, + /* Speed bin 2 */ + <828000 828000 828000 828000 828000 + 828000 828000 828000 828000 828000 + 828000 828000 900000 900000 900000 + 900000 900000 900000 900000 900000 + 952000 952000 952000 1136000 1136000 + 1136000 1136000 1136000 1136000 1136000>, + /* Speed bin 3 */ + <828000 828000 828000 828000 828000 + 828000 828000 828000 828000 828000 + 828000 828000 900000 900000 900000 + 900000 900000 900000 900000 900000 + 952000 952000 952000 1136000 1136000 + 1136000 1136000 1136000 1136000 1136000 + 1136000>; + + qcom,cpr-voltage-floor = + /* Speed bin 0 */ + <568000 568000 568000 568000 568000 + 568000 568000 568000 568000 568000 + 568000 568000 632000 632000 632000 + 632000 632000 632000 632000 632000 + 712000 712000 712000 772000 772000 + 772000 772000 772000 772000 772000 + 772000 772000>, + /* Speed bin 1 */ + <568000 568000 568000 568000 568000 + 568000 568000 568000 568000 568000 + 568000 568000 632000 632000 632000 + 632000 632000 632000 632000 632000 + 712000 712000 712000 772000 772000 + 772000>, + /* Speed bin 2 */ + <568000 568000 568000 568000 568000 + 568000 568000 568000 568000 568000 + 568000 568000 632000 632000 632000 + 632000 632000 632000 632000 632000 + 712000 712000 712000 772000 772000 + 772000 772000 772000 772000 772000>, + /* Speed bin 3 */ + <568000 568000 568000 568000 568000 + 568000 568000 568000 568000 568000 + 568000 568000 632000 632000 632000 + 632000 632000 632000 632000 632000 + 712000 712000 712000 772000 772000 + 772000 772000 772000 772000 772000 + 772000>; + + qcom,cpr-floor-to-ceiling-max-range = + /* Speed bin 0 */ + <32000 32000 32000 32000 + 32000 32000 32000 32000 + 32000 32000 32000 32000 + 32000 32000 32000 32000 + 32000 32000 32000 32000 + 40000 40000 40000 40000 + 40000 40000 40000 40000 + 40000 40000 40000 40000>, + /* Speed bin 1 */ + <32000 32000 32000 32000 + 32000 32000 32000 32000 + 32000 32000 32000 32000 + 32000 32000 32000 32000 + 32000 32000 32000 32000 + 40000 40000 40000 40000 + 40000 40000>, + /* Speed bin 2 */ + <32000 32000 32000 32000 + 32000 32000 32000 32000 + 32000 32000 32000 32000 + 32000 32000 32000 32000 + 32000 32000 32000 32000 + 40000 40000 40000 40000 + 40000 40000 40000 40000 + 40000 40000>, + /* Speed bin 3 */ + <32000 32000 32000 32000 + 32000 32000 32000 32000 + 32000 32000 32000 32000 + 32000 32000 32000 32000 + 32000 32000 32000 32000 + 40000 40000 40000 40000 + 40000 40000 40000 40000 + 40000 40000 40000>; + + qcom,corner-frequencies = + /* Speed bin 0 */ + <300000000 345600000 422400000 + 499200000 576000000 652800000 + 729600000 806400000 902400000 + 979200000 1056000000 1132800000 + 1190400000 1267200000 1344000000 + 1420800000 1497600000 1574400000 + 1651200000 1728000000 1804800000 + 1881600000 1958400000 2035200000 + 2112000000 2208000000 2265600000 + 2342400000 2419200000 2457600000 + 2476800000 2496000000>, + /* Speed bin 1 */ + <300000000 345600000 422400000 + 499200000 576000000 652800000 + 729600000 806400000 902400000 + 979200000 1056000000 1132800000 + 1190400000 1267200000 1344000000 + 1420800000 1497600000 1574400000 + 1651200000 1728000000 1804800000 + 1881600000 1958400000 2035200000 + 2112000000 2208000000>, + /* Speed bin 2 */ + <300000000 345600000 422400000 + 499200000 576000000 652800000 + 729600000 806400000 902400000 + 979200000 1056000000 1132800000 + 1190400000 1267200000 1344000000 + 1420800000 1497600000 1574400000 + 1651200000 1728000000 1804800000 + 1881600000 1958400000 2035200000 + 2112000000 2208000000 2265600000 + 2323200000 2342400000 2361600000>, + /* Speed bin 3 */ + <300000000 345600000 422400000 + 499200000 576000000 652800000 + 729600000 806400000 902400000 + 979200000 1056000000 1132800000 + 1190400000 1267200000 1344000000 + 1420800000 1497600000 1574400000 + 1651200000 1728000000 1804800000 + 1881600000 1958400000 2035200000 + 2112000000 2208000000 2265600000 + 2323200000 2342400000 2361600000 + 2457600000>; + + qcom,cpr-ro-scaling-factor = + <2857 3057 2828 2952 2699 2798 2446 + 2631 2629 2578 2244 3344 3289 3137 + 3164 2655>, + <2857 3057 2828 2952 2699 2798 2446 + 2631 2629 2578 2244 3344 3289 3137 + 3164 2655>, + <2603 2755 2676 2777 2573 2685 2465 + 2610 2312 2423 2243 3104 3022 3036 + 2740 2303>, + <1901 2016 2096 2228 2034 2161 2077 + 2188 1565 1870 1925 2235 2205 2413 + 1762 1478>; + + qcom,cpr-open-loop-voltage-fuse-adjustment = + /* Speed bin 0 */ + < 8000 0 12000 52000>, + < 8000 0 12000 52000>, + < 8000 0 12000 52000>, + < 8000 0 12000 52000>, + < 8000 0 12000 52000>, + < 8000 0 12000 52000>, + < 8000 0 12000 52000>, + < 8000 0 12000 52000>, + /* Speed bin 1 */ + < 8000 0 12000 52000>, + < 8000 0 12000 52000>, + < 8000 0 12000 52000>, + < 8000 0 12000 52000>, + < 8000 0 12000 52000>, + < 8000 0 12000 52000>, + < 8000 0 12000 52000>, + < 8000 0 12000 52000>, + /* Speed bin 2 */ + < 8000 0 12000 52000>, + < 8000 0 12000 52000>, + < 8000 0 12000 52000>, + < 8000 0 12000 52000>, + < 8000 0 12000 52000>, + < 8000 0 12000 52000>, + < 8000 0 12000 52000>, + < 8000 0 12000 52000>, + /* Speed bin 3 */ + < 8000 0 12000 52000>, + < 8000 0 12000 52000>, + < 8000 0 12000 52000>, + < 8000 0 12000 52000>, + < 8000 0 12000 52000>, + < 8000 0 12000 52000>, + < 8000 0 12000 52000>, + < 8000 0 12000 52000>; + + qcom,cpr-closed-loop-voltage-fuse-adjustment = + /* Speed bin 0 */ + < 0 0 12000 50000>, + < 0 0 12000 50000>, + < 0 0 12000 50000>, + < 0 0 12000 50000>, + < 0 0 12000 50000>, + < 0 0 12000 50000>, + < 0 0 12000 50000>, + < 0 0 12000 50000>, + /* Speed bin 1 */ + < 0 0 12000 50000>, + < 0 0 12000 50000>, + < 0 0 12000 50000>, + < 0 0 12000 50000>, + < 0 0 12000 50000>, + < 0 0 12000 50000>, + < 0 0 12000 50000>, + < 0 0 12000 50000>, + /* Speed bin 2 */ + < 0 0 12000 50000>, + < 0 0 12000 50000>, + < 0 0 12000 50000>, + < 0 0 12000 50000>, + < 0 0 12000 50000>, + < 0 0 12000 50000>, + < 0 0 12000 50000>, + < 0 0 12000 50000>, + /* Speed bin 3 */ + < 0 0 12000 50000>, + < 0 0 12000 50000>, + < 0 0 12000 50000>, + < 0 0 12000 50000>, + < 0 0 12000 50000>, + < 0 0 12000 50000>, + < 0 0 12000 50000>, + < 0 0 12000 50000>; + + qcom,cpr-open-loop-voltage-adjustment = + /* Speed bin 0 */ + < 0 0 0 0 0 + 0 0 0 0 0 + 0 (-8000) (-12000) (-12000) (-12000) + (-12000) (-12000) (-12000) (-16000) (-16000) + (-20000) (-16000) (-16000) (-16000) (-12000) + (-28000) (-28000) (-28000) (-28000) (-28000) + (-28000) (-28000)>, + /* Speed bin 1 */ + < 0 0 0 0 0 + 0 0 0 0 0 + 0 (-8000) (-12000) (-12000) (-12000) + (-12000) (-12000) (-12000) (-16000) (-16000) + (-20000) (-16000) (-16000) (-16000) (-16000) + (-28000)>, + /* Speed bin 2 */ + < 0 0 0 0 0 + 0 0 0 0 0 + 0 (-8000) (-12000) (-12000) (-12000) + (-12000) (-12000) (-12000) (-16000) (-16000) + (-20000) (-16000) (-16000) (-16000) (-12000) + (-28000) (-28000) (-28000) (-28000) (-28000)>, + /* Speed bin 3 */ + < 0 0 0 0 0 + 0 0 0 0 0 + 0 (-8000) (-12000) (-12000) (-12000) + (-12000) (-12000) (-12000) (-16000) (-16000) + (-20000) (-16000) (-16000) (-16000) (-12000) + (-28000) (-28000) (-28000) (-28000) (-28000) + (-28000)>; + + qcom,cpr-closed-loop-voltage-adjustment = + /* Speed bin 0 */ + < 0 0 0 0 0 + 0 0 0 0 0 + 0 (-10000) (-10000) (-11000) (-12000) + (-12000) (-13000) (-14000) (-14000) (-15000) + (-16000) (-16000) (-17000) (-15000) (-13000) + (-26000) (-26000) (-27000) (-27000) (-28000) + (-28000) (-28000)>, + /* Speed bin 1 */ + < 0 0 0 0 0 + 0 0 0 0 0 + 0 (-10000) (-10000) (-11000) (-12000) + (-12000) (-13000) (-14000) (-14000) (-15000) + (-16000) (-16000) (-17000) (-16000) (-15000) + (-28000)>, + /* Speed bin 2 */ + < 0 0 0 0 0 + 0 0 0 0 0 + 0 (-10000) (-10000) (-11000) (-12000) + (-12000) (-13000) (-14000) (-14000) (-15000) + (-16000) (-16000) (-17000) (-15000) (-14000) + (-27000) (-27000) (-28000) (-28000) (-28000)>, + /* Speed bin 3 */ + < 0 0 0 0 0 + 0 0 0 0 0 + 0 (-10000) (-10000) (-11000) (-12000) + (-12000) (-13000) (-14000) (-14000) (-15000) + (-16000) (-16000) (-17000) (-15000) (-14000) + (-26000) (-27000) (-27000) (-28000) (-28000) + (-28000)>; + + qcom,allow-voltage-interpolation; + qcom,allow-quotient-interpolation; + qcom,cpr-scaled-open-loop-voltage-as-ceiling; + + qcom,cpr-aging-ref-corner = <32 26 30 31>; + qcom,cpr-aging-ro-scaling-factor = <1700>; + qcom,allow-aging-voltage-adjustment = <0>; +}; + +&pm8005_s1 { + regulator-min-microvolt = <516000>; + regulator-max-microvolt = <1088000>; +}; + +&gfx_cpr { + compatible = "qcom,cpr4-msm8998-v2-mmss-regulator"; + qcom,cpr-aging-ref-voltage = <1088000>; +}; + +&gfx_vreg { + regulator-min-microvolt = <1>; + regulator-max-microvolt = <8>; + + qcom,cpr-fuse-corners = <4>; + qcom,cpr-fuse-combos = <8>; + qcom,cpr-corners = <8>; + + qcom,cpr-corner-fmax-map = <1 3 5 8>; + + qcom,cpr-voltage-ceiling = + <716000 716000 772000 880000 908000 948000 1016000 1088000>, + <724000 724000 772000 832000 916000 968000 1024000 1088000>, + <724000 724000 772000 832000 916000 968000 1024000 1088000>, + <724000 724000 772000 832000 916000 968000 1024000 1088000>, + <724000 724000 772000 832000 916000 968000 1024000 1088000>, + <724000 724000 772000 832000 916000 968000 1024000 1088000>, + <724000 724000 772000 832000 916000 968000 1024000 1088000>, + <724000 724000 772000 832000 916000 968000 1024000 1088000>; + + qcom,cpr-voltage-floor = + <516000 516000 532000 584000 632000 672000 712000 756000>; + + qcom,mem-acc-voltage = <1 1 1 2 2 2 2 2>; + + qcom,corner-frequencies = + <180000000 257000000 342000000 414000000 + 515000000 596000000 670000000 710000000>; + + qcom,cpr-target-quotients = + < 0 0 0 0 331 357 0 0 + 0 0 0 0 0 0 115 0>, + < 0 0 0 0 467 500 0 0 + 0 0 0 0 0 0 199 0>, + < 0 0 0 0 628 665 0 0 + 0 0 0 0 0 0 290 0>, + < 0 0 0 0 762 805 0 0 + 0 0 0 0 0 0 397 0>, + < 0 0 0 0 964 1013 0 0 + 0 0 1143 0 1138 1055 0 0>, + < 0 0 0 0 0 0 0 0 + 0 0 1306 0 1289 1168 0 0>, + < 0 0 0 0 0 0 0 0 + 0 0 1468 0 1429 1256 0 0>, + < 0 0 0 0 0 0 0 0 + 0 0 1627 0 1578 1353 0 0>; + + qcom,cpr-ro-scaling-factor = + < 0 0 0 0 2377 2571 0 0 + 0 0 2168 0 2209 1849 1997 0>, + < 0 0 0 0 2377 2571 0 0 + 0 0 2168 0 2209 1849 1997 0>, + < 0 0 0 0 2377 2571 0 0 + 0 0 2168 0 2209 1849 1997 0>, + < 0 0 0 0 2377 2571 0 0 + 0 0 2168 0 2209 1849 1997 0>, + < 0 0 0 0 2377 2571 0 0 + 0 0 2168 0 2209 1849 1997 0>, + < 0 0 0 0 2377 2571 0 0 + 0 0 2168 0 2209 1849 1997 0>, + < 0 0 0 0 2377 2571 0 0 + 0 0 2168 0 2209 1849 1997 0>, + < 0 0 0 0 2377 2571 0 0 + 0 0 2168 0 2209 1849 1997 0>; + + qcom,cpr-open-loop-voltage-fuse-adjustment = + < 60000 0 0 0>, + < 60000 0 0 0>, + < 60000 0 0 0>, + < 60000 0 0 0>, + < 60000 0 0 0>, + < 60000 0 0 0>, + < 60000 0 0 0>, + < 60000 0 0 0>; + + qcom,cpr-closed-loop-voltage-adjustment = + < 90000 38000 28000 8000 + 0 29000 11000 0>, + < 90000 38000 28000 8000 + 0 29000 11000 0>, + < 90000 38000 28000 8000 + 0 29000 11000 0>, + < 90000 38000 28000 8000 + 0 29000 11000 0>, + < 90000 38000 28000 8000 + 0 29000 11000 0>, + < 90000 38000 28000 8000 + 0 29000 11000 0>, + < 90000 38000 28000 8000 + 0 29000 11000 0>, + < 90000 38000 28000 8000 + 0 29000 11000 0>; + + qcom,cpr-floor-to-ceiling-max-range = + <40000 40000 40000 40000 40000 40000 50000 50000>; + + qcom,cpr-fused-closed-loop-voltage-adjustment-map = + <0 0 0 0 1 2 3 4>; + + qcom,allow-voltage-interpolation; + qcom,cpr-scaled-open-loop-voltage-as-ceiling; + + qcom,cpr-aging-max-voltage-adjustment = <15000>; + qcom,cpr-aging-ref-corner = <8>; + qcom,cpr-aging-ro-scaling-factor = <1620>; + qcom,allow-aging-voltage-adjustment = <0>; +}; + +&qusb_phy0 { + reg = <0x0c012000 0x2a8>, + <0x01fcb24c 0x4>, + <0x00784238 0x4>; + reg-names = "qusb_phy_base", + "tcsr_clamp_dig_n_1p8", + "efuse_addr"; + qcom,efuse-bit-pos = <16>; + qcom,efuse-num-bits = <4>; + qcom,qusb-phy-init-seq = + /* */ + <0x13 0x04 /* analog_controls_two */ + 0x7c 0x18c /* pll_clock_inverter */ + 0x80 0x2c /* pll_cmode */ + 0x0a 0x184 /* pll_lock_delay */ + 0xa5 0x23c /* tune1 */ + 0x09 0x240 /* tune2 */ + 0x19 0xb4>; /* digital_timers_two */ +}; + +&msm_vidc { + qcom,load-freq-tbl = + /* Encoders */ + <1105920 533000000 0x55555555>, /* 4kx2304@30 */ /*TURBO*/ + <1036800 444000000 0x55555555>, /* 720p@240, 1080p@120,1440p@60, + * UHD@30 */ /*NOMINAL*/ + < 829440 355200000 0x55555555>, /* UHD/4096x2160@30 SVSL1 */ + < 489600 269330000 0x55555555>, /* 1080p@60, 720p@120 SVS */ + < 345600 200000000 0x55555555>, /* 2560x1440@24, 1080p@30 */ + /* SVS2 */ + + /* Decoders */ + <2211840 533000000 0xffffffff>, /* 4kx2304@60, 1080p@240 */ + /* TURBO */ + <1728000 444000000 0xffffffff>, /* 2560x1440@120 */ + /* NOMINAL */ + <1675472 355200000 0xffffffff>, /* 4kx2304@44 */ /*SVSL1*/ + <1105920 269330000 0xffffffff>, /* UHD/4k2304@30, 1080p@120 */ + /* SVS */ + < 829440 200000000 0xffffffff>; /* 720p@120, 1080p@60 */ + /* SVS2 */ + + qcom,imem-ab-tbl = + <200000000 1560000>,/* imem @ svs2 freq 75 Mhz */ + <269330000 3570000>,/* imem @ svs freq 171 Mhz */ + <355200000 3570000>,/* imem @ svs freq 171 Mhz */ + <444000000 6750000>,/* imem @ nom freq 323 Mhz */ + <533000000 8490000>;/* imem @ turbo freq 406 Mhz */ + + qcom,dcvs-tbl = /* minLoad LoadLow LoadHigh CodecCheck */ + /* Decode */ + /* Load > Nominal, Nominal <-> Turbo Eg.3840x2160@60 */ + <1728000 1728000 2211840 0x3f00000c>, + /* Encoder */ + /* Load > Nominal, Nominal <-> Turbo Eg. 4kx2304@30 */ + <1036800 1036800 1105920 0x04000004>, + /* Load > SVSL1, SVSL1<-> Nominal Eg. 3840x2160@30 */ + < 829440 829440 1036800 0x04000004>, + /* Load > SVS , SVS <-> SVSL1 Eg. 4kx2304@24 */ + < 489600 489600 829440 0x04000004>; + + qcom,dcvs-limit = /* Min Frame size, Min MBs/sec */ + <32400 30>, /* Encoder 3840x2160@30 */ + <32400 60>; /* Decoder 3840x2160@60 */ + +}; + +&soc { + /* Gold L2 SAW */ + qcom,spm@178120000 { + qcom,saw2-avs-limit = <0x4700470>; + }; + + /* Silver L2 SAW */ + qcom,spm@179120000 { + qcom,saw2-avs-limit = <0x4200420>; + }; +}; + +/* GPU overrides */ +&msm_gpu { + /* Updated chip ID */ + qcom,chipid = <0x05040001>; + qcom,initial-pwrlevel = <6>; + + qcom,gpu-pwrlevels { + #address-cells = <1>; + #size-cells = <0>; + + compatible = "qcom,gpu-pwrlevels"; + + qcom,gpu-pwrlevel@0 { + reg = <0>; + qcom,gpu-freq = <710000000>; + qcom,bus-freq = <12>; + qcom,bus-min = <12>; + qcom,bus-max = <12>; + }; + + qcom,gpu-pwrlevel@1 { + reg = <1>; + qcom,gpu-freq = <670000000>; + qcom,bus-freq = <12>; + qcom,bus-min = <11>; + qcom,bus-max = <12>; + }; + + qcom,gpu-pwrlevel@2 { + reg = <2>; + qcom,gpu-freq = <596000000>; + qcom,bus-freq = <11>; + qcom,bus-min = <9>; + qcom,bus-max = <12>; + }; + + qcom,gpu-pwrlevel@3 { + reg = <3>; + qcom,gpu-freq = <515000000>; + qcom,bus-freq = <11>; + qcom,bus-min = <9>; + qcom,bus-max = <12>; + }; + + qcom,gpu-pwrlevel@4 { + reg = <4>; + qcom,gpu-freq = <414000000>; + qcom,bus-freq = <9>; + qcom,bus-min = <8>; + qcom,bus-max = <11>; + }; + + qcom,gpu-pwrlevel@5 { + reg = <5>; + qcom,gpu-freq = <342000000>; + qcom,bus-freq = <8>; + qcom,bus-min = <5>; + qcom,bus-max = <9>; + }; + + qcom,gpu-pwrlevel@6 { + reg = <6>; + qcom,gpu-freq = <257000000>; + qcom,bus-freq = <5>; + qcom,bus-min = <3>; + qcom,bus-max = <8>; + }; + + qcom,gpu-pwrlevel@7 { + reg = <7>; + qcom,gpu-freq = <27000000>; + qcom,bus-freq = <0>; + qcom,bus-min = <0>; + qcom,bus-max = <0>; + }; + }; +}; + +&spss_utils { + qcom,spss-test-firmware-name = "spss2t"; /* 8 chars max */ + qcom,spss-prod-firmware-name = "spss2p"; /* 8 chars max */ + qcom,spss-hybr-firmware-name = "spss2h"; /* 8 chars max */ +}; + +&ufs1 { + clock-names = + "core_clk", + "bus_aggr_clk", + "iface_clk", + "core_clk_unipro", + "core_clk_ice", + "ref_clk", + "tx_lane0_sync_clk", + "rx_lane0_sync_clk", + "rx_lane1_sync_clk"; + clocks = + <&clock_gcc clk_gcc_ufs_axi_hw_ctl_clk>, + <&clock_gcc clk_gcc_aggre1_ufs_axi_clk>, + <&clock_gcc clk_gcc_ufs_ahb_clk>, + <&clock_gcc clk_gcc_ufs_unipro_core_hw_ctl_clk>, + <&clock_gcc clk_gcc_ufs_ice_core_hw_ctl_clk>, + <&clock_gcc clk_ln_bb_clk1>, + <&clock_gcc clk_gcc_ufs_tx_symbol_0_clk>, + <&clock_gcc clk_gcc_ufs_rx_symbol_0_clk>, + <&clock_gcc clk_gcc_ufs_rx_symbol_1_clk>; + freq-table-hz = + <50000000 200000000>, + <0 0>, + <0 0>, + <37500000 150000000>, + <75000000 300000000>, + <0 0>, + <0 0>, + <0 0>, + <0 0>; + + lanes-per-direction = <2>; +}; + +&ssc_sensors { + qcom,firmware-name = "slpi_v2"; +}; diff -Nruw linux-4.4.115-fbx/arch/arm/boot/dts/qcom./msm8998-vidc.dtsi linux-4.4.115-fbx/arch/arm/boot/dts/qcom/msm8998-vidc.dtsi --- linux-4.4.115-fbx/arch/arm/boot/dts/qcom./msm8998-vidc.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ linux-4.4.115-fbx/arch/arm/boot/dts/qcom/msm8998-vidc.dtsi 2019-01-22 16:16:21.203225578 +0100 @@ -0,0 +1,251 @@ +/* Copyright (c) 2014-2017, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include + +&soc { + msm_vidc: qcom,vidc@cc00000 { + compatible = "qcom,msm-vidc"; + status = "ok"; + reg = <0xcc00000 0x100000>; + interrupts = ; + qcom,hfi = "venus"; + qcom,hfi-version = "3xx"; + qcom,firmware-name = "venus"; + qcom,never-unload-fw; + qcom,sw-power-collapse; + qcom,max-secure-instances = <5>; + qcom,reg-presets = + <0x80124 0x00000003>, + <0x80550 0x01111111>, + <0x80560 0x01111111>, + <0x80568 0x01111111>, + <0x80570 0x01111111>, + <0x80580 0x01111111>, + <0x80588 0x01111111>, + <0xe2010 0x00000000>; + + qcom,imem-size = <524288>; /* 512 kB */ + qcom,max-hw-load = <2563200>; /* Full 4k @ 60 + 1080p @ 60 */ + qcom,power-conf = <8294400>; /* WxH - 3840*2160 */ + qcom,load-freq-tbl = + /* Encoders */ + <972000 465000000 0x55555555>, /* 4k UHD @ 30 */ + <489600 360000000 0x55555555>, /* 1080p @ 60 */ + <244800 186000000 0x55555555>, /* 1080p @ 30 */ + <108000 100000000 0x55555555>, /* 720p @ 30 */ + + /* Decoders */ + <1944000 465000000 0xffffffff>, /* 4k UHD @ 60 */ + < 972000 360000000 0xffffffff>, /* 4k UHD @ 30 */ + < 489600 186000000 0xffffffff>, /* 1080p @ 60 */ + < 244800 100000000 0xffffffff>; /* 1080p @ 30 */ + + qcom,dcvs-tbl = + <972000 972000 19944000 0x3f00000c>, /* UHD 30 */ + <489600 489600 972000 0x3f00000c>, /* 1080p 60 */ + <244800 244800 489600 0x3f00000c>, /* 1080p 30 */ + <829440 489600 972000 0x04000004>; /* DCI 24 */ + + qcom,dcvs-limit = + <32400 30>, /* Encoder UHD */ + <14400 30>; /* Decoder WQHD */ + + /* Table lists pairs. + * imem_ab value determines the imem clock frequency for the + * corresponding video core frequency. + */ + qcom,imem-ab-tbl = + <100000000 1560000>, /* imem @ svs2 freq 75 Mhz */ + <186000000 3570000>, /* imem @ svs freq 171 Mhz */ + <360000000 6750000>, /* imem @ nom freq 323 Mhz */ + <465000000 8490000>; /* imem @ turbo freq 406 Mhz */ + + /* Regulators */ + smmu-vdd-supply = <&gdsc_bimc_smmu>; + venus-supply = <&gdsc_venus>; + venus-core0-supply = <&gdsc_venus_core0>; + venus-core1-supply = <&gdsc_venus_core1>; + + /* Clocks */ + clock-names = "sys_noc_axi_clk", + "noc_axi_clk", "mnoc_ahb_clk", + "smmu_ahb_clk", "smmu_axi_clk", + "mnoc_maxi_clk", + "core_clk", "iface_clk", "bus_clk", + "maxi_clk", "core0_clk", "core1_clk"; + clocks = <&clock_gcc clk_gcc_mmss_sys_noc_axi_clk>, + <&clock_gcc clk_mmssnoc_axi_clk>, + <&clock_mmss clk_mmss_mnoc_ahb_clk>, + <&clock_mmss clk_mmss_bimc_smmu_ahb_clk>, + <&clock_mmss clk_mmss_bimc_smmu_axi_clk>, + <&clock_mmss clk_mmss_mnoc_maxi_clk>, + <&clock_mmss clk_mmss_video_core_clk>, + <&clock_mmss clk_mmss_video_ahb_clk>, + <&clock_mmss clk_mmss_video_axi_clk>, + <&clock_mmss clk_mmss_video_maxi_clk>, + <&clock_mmss clk_mmss_video_subcore0_clk>, + <&clock_mmss clk_mmss_video_subcore1_clk>; + qcom,clock-configs = <0x0 0x0 0x0 0x0 0x0 0x0 + 0x3 0x0 0x2 0x2 0x3 0x3>; + + /* Buses */ + bus_cnoc { + compatible = "qcom,msm-vidc,bus"; + label = "cnoc"; + qcom,bus-master = ; + qcom,bus-slave = ; + qcom,bus-governor = "performance"; + qcom,bus-range-kbps = <1 1>; + }; + + venus_bus_ddr { + compatible = "qcom,msm-vidc,bus"; + label = "venus-ddr"; + qcom,bus-master = ; + qcom,bus-slave = ; + qcom,bus-governor = "msm-vidc-ddr"; + qcom,bus-range-kbps = <1000 4946000>; + }; + + venus_bus_vmem { + compatible = "qcom,msm-vidc,bus"; + label = "venus-vmem"; + qcom,bus-master = ; + qcom,bus-slave = ; + qcom,bus-governor = "msm-vidc-vmem+"; + qcom,bus-range-kbps = <1000 8490000>; + }; + + arm9_bus_ddr { + compatible = "qcom,msm-vidc,bus"; + label = "venus-arm9-ddr"; + qcom,bus-master = ; + qcom,bus-slave = ; + qcom,bus-governor = "performance"; + qcom,bus-range-kbps = <1 1>; + }; + + + /* MMUs */ + non_secure_cb { + compatible = "qcom,msm-vidc,context-bank"; + label = "venus_ns"; + iommus = + <&mmss_smmu 0x400>, + <&mmss_smmu 0x401>, + <&mmss_smmu 0x40a>, + <&mmss_smmu 0x407>, + <&mmss_smmu 0x40e>, + <&mmss_smmu 0x40f>, + <&mmss_smmu 0x408>, + <&mmss_smmu 0x409>, + <&mmss_smmu 0x40b>, + <&mmss_smmu 0x40c>, + <&mmss_smmu 0x40d>, + <&mmss_smmu 0x410>, + <&mmss_smmu 0x421>, + <&mmss_smmu 0x428>, + <&mmss_smmu 0x429>, + <&mmss_smmu 0x42b>, + <&mmss_smmu 0x42c>, + <&mmss_smmu 0x42d>, + <&mmss_smmu 0x411>, + <&mmss_smmu 0x431>; + buffer-types = <0xfff>; + virtual-addr-pool = <0x70800000 0x6f800000>; + }; + + firmware_cb { + compatible = "qcom,msm-vidc,context-bank"; + qcom,fw-context-bank; + iommus = <&mmss_smmu 0x580>, + <&mmss_smmu 0x586>; + }; + secure_bitstream_cb { + compatible = "qcom,msm-vidc,context-bank"; + label = "venus_sec_bitstream"; + iommus = <&mmss_smmu 0x500>, + <&mmss_smmu 0x502>, + <&mmss_smmu 0x509>, + <&mmss_smmu 0x50a>, + <&mmss_smmu 0x50b>, + <&mmss_smmu 0x50e>, + <&mmss_smmu 0x526>, + <&mmss_smmu 0x529>, + <&mmss_smmu 0x52b>; + buffer-types = <0x241>; + virtual-addr-pool = <0x4b000000 0x25800000>; + qcom,secure-context-bank; + }; + + venus_secure_pixel_cb: secure_pixel_cb { + compatible = "qcom,msm-vidc,context-bank"; + label = "venus_sec_pixel"; + iommus = <&mmss_smmu 0x504>, + <&mmss_smmu 0x50c>, + <&mmss_smmu 0x510>, + <&mmss_smmu 0x52c>; + buffer-types = <0x106>; + virtual-addr-pool = <0x25800000 0x25800000>; + qcom,secure-context-bank; + }; + + venus_secure_non_pixel_cb: secure_non_pixel_cb { + compatible = "qcom,msm-vidc,context-bank"; + label = "venus_sec_non_pixel"; + iommus = <&mmss_smmu 0x505>, + <&mmss_smmu 0x507>, + <&mmss_smmu 0x508>, + <&mmss_smmu 0x50d>, + <&mmss_smmu 0x50f>, + <&mmss_smmu 0x525>, + <&mmss_smmu 0x528>, + <&mmss_smmu 0x52d>, + <&mmss_smmu 0x540>; + buffer-types = <0x480>; + virtual-addr-pool = <0x1000000 0x24800000>; + qcom,secure-context-bank; + }; + }; + + qcom,vmem@c880000 { + compatible = "qcom,msm-vmem"; + status = "ok"; + interrupts = ; + + reg = <0xc880000 0x6b>, + <0x14800000 0x80000>; + reg-names = "reg-base", "mem-base"; + + clocks = <&clock_mmss clk_mmss_mnoc_ahb_clk>, + <&clock_mmss clk_mmss_mnoc_maxi_clk>, + <&clock_mmss clk_mmss_vmem_ahb_clk>, + <&clock_mmss clk_mmss_vmem_maxi_clk>; + clock-names = "mnoc_ahb","mnoc_maxi", + "ahb", "maxi"; + clock-config = <0x0 0x0 0x0 0x1>; + + qcom,msm-bus,name = "vmem"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <2>; + qcom,msm-bus,vectors-KBps = + , + , + , + ; + + qcom,bank-size = <131072>; /* 128 kB */ + }; +}; diff -Nruw linux-4.4.115-fbx/arch/arm/boot/dts/qcom./msm8998-wcd.dtsi linux-4.4.115-fbx/arch/arm/boot/dts/qcom/msm8998-wcd.dtsi --- linux-4.4.115-fbx/arch/arm/boot/dts/qcom./msm8998-wcd.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ linux-4.4.115-fbx/arch/arm/boot/dts/qcom/msm8998-wcd.dtsi 2019-01-22 16:16:21.203225578 +0100 @@ -0,0 +1,239 @@ +/* Copyright (c) 2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&slim_aud { + tasha_codec { + wsa_spkr_sd1: msm_cdc_pinctrll { + compatible = "qcom,msm-cdc-pinctrl"; + pinctrl-names = "aud_active", "aud_sleep"; + pinctrl-0 = <&spkr_1_sd_n_active>; + pinctrl-1 = <&spkr_1_sd_n_sleep>; + }; + + wsa_spkr_sd2: msm_cdc_pinctrlr { + compatible = "qcom,msm-cdc-pinctrl"; + pinctrl-names = "aud_active", "aud_sleep"; + pinctrl-0 = <&spkr_2_sd_n_active>; + pinctrl-1 = <&spkr_2_sd_n_sleep>; + }; + }; + + tavil_codec { + wcd: wcd_pinctrl@5 { + compatible = "qcom,wcd-pinctrl"; + qcom,num-gpios = <5>; + gpio-controller; + #gpio-cells = <2>; + + us_euro_sw_wcd_active: us_euro_sw_wcd_active { + mux { + pins = "gpio1"; + }; + + config { + pins = "gpio1"; + output-high; + }; + }; + + us_euro_sw_wcd_sleep: us_euro_sw_wcd_sleep { + mux { + pins = "gpio1"; + }; + + config { + pins = "gpio1"; + output-low; + }; + }; + + spkr_1_wcd_en_active: spkr_1_wcd_en_active { + mux { + pins = "gpio2"; + }; + + config { + pins = "gpio2"; + output-high; + }; + }; + + spkr_1_wcd_en_sleep: spkr_1_wcd_en_sleep { + mux { + pins = "gpio2"; + }; + + config { + pins = "gpio2"; + input-enable; + }; + }; + + spkr_2_wcd_en_active: spkr_2_sd_n_active { + mux { + pins = "gpio3"; + }; + + config { + pins = "gpio3"; + output-high; + }; + }; + + spkr_2_wcd_en_sleep: spkr_2_sd_n_sleep { + mux { + pins = "gpio3"; + }; + + config { + pins = "gpio3"; + input-enable; + }; + }; + + hph_en0_wcd_active: hph_en0_wcd_active { + mux { + pins = "gpio4"; + }; + + config { + pins = "gpio4"; + output-high; + }; + }; + + hph_en0_wcd_sleep: hph_en0_wcd_sleep { + mux { + pins = "gpio4"; + }; + + config { + pins = "gpio4"; + output-low; + }; + }; + + hph_en1_wcd_active: hph_en1_wcd_active { + mux { + pins = "gpio5"; + }; + + config { + pins = "gpio5"; + output-high; + }; + }; + + hph_en1_wcd_sleep: hph_en1_wcd_sleep { + mux { + pins = "gpio5"; + }; + + config { + pins = "gpio5"; + output-low; + }; + }; + }; + + wsa_spkr_wcd_sd1: msm_cdc_pinctrll { + compatible = "qcom,msm-cdc-pinctrl"; + pinctrl-names = "aud_active", "aud_sleep"; + pinctrl-0 = <&spkr_1_wcd_en_active>; + pinctrl-1 = <&spkr_1_wcd_en_sleep>; + }; + + wsa_spkr_wcd_sd2: msm_cdc_pinctrlr { + compatible = "qcom,msm-cdc-pinctrl"; + pinctrl-names = "aud_active", "aud_sleep"; + pinctrl-0 = <&spkr_2_wcd_en_active>; + pinctrl-1 = <&spkr_2_wcd_en_sleep>; + }; + + tavil_us_euro_sw: msm_cdc_pinctrl_us_euro_sw { + compatible = "qcom,msm-cdc-pinctrl"; + pinctrl-names = "aud_active", "aud_sleep"; + pinctrl-0 = <&us_euro_sw_wcd_active>; + pinctrl-1 = <&us_euro_sw_wcd_sleep>; + }; + + tavil_hph_en0: msm_cdc_pinctrl_hph_en0 { + compatible = "qcom,msm-cdc-pinctrl"; + pinctrl-names = "aud_active", "aud_sleep"; + pinctrl-0 = <&hph_en0_wcd_active>; + pinctrl-1 = <&hph_en0_wcd_sleep>; + }; + + tavil_hph_en1: msm_cdc_pinctrl_hph_en1 { + compatible = "qcom,msm-cdc-pinctrl"; + pinctrl-names = "aud_active", "aud_sleep"; + pinctrl-0 = <&hph_en1_wcd_active>; + pinctrl-1 = <&hph_en1_wcd_sleep>; + }; + }; +}; + +&tlmm { + spkr_1_sd_n { + spkr_1_sd_n_sleep: spkr_1_sd_n_sleep { + mux { + pins = "gpio65"; + function = "gpio"; + }; + config { + pins = "gpio65"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; + input-enable; + }; + }; + spkr_1_sd_n_active: spkr_1_sd_n_active { + mux { + pins = "gpio65"; + function = "gpio"; + }; + config { + pins = "gpio65"; + drive-strength = <16>; /* 16 mA */ + bias-disable; + output-high; + }; + }; + }; + + spkr_2_sd_n { + spkr_2_sd_n_sleep: spkr_2_sd_n_sleep { + mux { + pins = "gpio66"; + function = "gpio"; + }; + config { + pins = "gpio66"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; + input-enable; + }; + }; + spkr_2_sd_n_active: spkr_2_sd_n_active { + mux { + pins = "gpio66"; + function = "gpio"; + }; + config { + pins = "gpio66"; + drive-strength = <16>; /* 16 mA */ + bias-disable; + output-high; + }; + }; + }; +}; diff -Nruw linux-4.4.115-fbx/arch/arm/boot/dts/qcom./msm8998-wsa881x.dtsi linux-4.4.115-fbx/arch/arm/boot/dts/qcom/msm8998-wsa881x.dtsi --- linux-4.4.115-fbx/arch/arm/boot/dts/qcom./msm8998-wsa881x.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ linux-4.4.115-fbx/arch/arm/boot/dts/qcom/msm8998-wsa881x.dtsi 2019-01-22 16:16:21.203225578 +0100 @@ -0,0 +1,78 @@ +/* Copyright (c) 2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include "msm8998-wcd.dtsi" + +&slim_aud { + tasha_codec { + swr_master { + compatible = "qcom,swr-wcd"; + #address-cells = <2>; + #size-cells = <0>; + + wsa881x_211: wsa881x@20170211 { + compatible = "qcom,wsa881x"; + reg = <0x00 0x20170211>; + qcom,spkr-sd-n-node = <&wsa_spkr_sd1>; + }; + + wsa881x_212: wsa881x@20170212 { + compatible = "qcom,wsa881x"; + reg = <0x00 0x20170212>; + qcom,spkr-sd-n-node = <&wsa_spkr_sd2>; + }; + + wsa881x_213: wsa881x@21170213 { + compatible = "qcom,wsa881x"; + reg = <0x00 0x21170213>; + qcom,spkr-sd-n-node = <&wsa_spkr_sd1>; + }; + + wsa881x_214: wsa881x@21170214 { + compatible = "qcom,wsa881x"; + reg = <0x00 0x21170214>; + qcom,spkr-sd-n-node = <&wsa_spkr_sd2>; + }; + }; + }; + + tavil_codec { + swr_master { + compatible = "qcom,swr-wcd"; + #address-cells = <2>; + #size-cells = <0>; + + wsa881x_0211: wsa881x@20170211 { + compatible = "qcom,wsa881x"; + reg = <0x00 0x20170211>; + qcom,spkr-sd-n-node = <&wsa_spkr_wcd_sd1>; + }; + + wsa881x_0212: wsa881x@20170212 { + compatible = "qcom,wsa881x"; + reg = <0x00 0x20170212>; + qcom,spkr-sd-n-node = <&wsa_spkr_wcd_sd2>; + }; + + wsa881x_0213: wsa881x@21170213 { + compatible = "qcom,wsa881x"; + reg = <0x00 0x21170213>; + qcom,spkr-sd-n-node = <&wsa_spkr_wcd_sd1>; + }; + + wsa881x_0214: wsa881x@21170214 { + compatible = "qcom,wsa881x"; + reg = <0x00 0x21170214>; + qcom,spkr-sd-n-node = <&wsa_spkr_wcd_sd2>; + }; + }; + }; +}; diff -Nruw linux-4.4.115-fbx/arch/arm/boot/dts/qcom./msm-arm-smmu-8998.dtsi linux-4.4.115-fbx/arch/arm/boot/dts/qcom/msm-arm-smmu-8998.dtsi --- linux-4.4.115-fbx/arch/arm/boot/dts/qcom./msm-arm-smmu-8998.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ linux-4.4.115-fbx/arch/arm/boot/dts/qcom/msm-arm-smmu-8998.dtsi 2019-01-22 16:16:21.179225361 +0100 @@ -0,0 +1,192 @@ +/* Copyright (c) 2015-2017, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include + +&soc { + anoc1_smmu: arm,smmu-anoc1@1680000 { + status = "ok"; + compatible = "qcom,smmu-v2"; + reg = <0x1680000 0x10000>; + #iommu-cells = <0>; + qcom,register-save; + qcom,skip-init; + #global-interrupts = <0>; + interrupts = , + , + , + , + , + ; + qcom,msm-bus,name = "smmu-bus-client-anoc1"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,active-only; + qcom,msm-bus,num-paths = <1>; + /* aggre1_noc_clk */ + qcom,msm-bus,vectors-KBps = + <84 10062 0 0>, + <84 10062 0 1000>; + }; + + anoc2_smmu: arm,smmu-anoc2@16c0000 { + status = "ok"; + compatible = "qcom,smmu-v2"; + reg = <0x16c0000 0x40000>; + #iommu-cells = <1>; + qcom,register-save; + qcom,skip-init; + #global-interrupts = <0>; + interrupts = , + , + , + , + , + , + , + , + , + ; + qcom,msm-bus,name = "smmu-bus-client-anoc2"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,active-only; + qcom,msm-bus,num-paths = <1>; + /* aggre2_noc_clk */ + qcom,msm-bus,vectors-KBps = + <117 10065 0 0>, + <117 10065 0 1000>; + }; + + lpass_q6_smmu: arm,smmu-lpass_q6@5100000 { + status = "ok"; + compatible = "qcom,smmu-v2"; + reg = <0x5100000 0x40000>; + #iommu-cells = <1>; + qcom,tz-device-id = "LPASS"; + qcom,register-save; + qcom,skip-init; + #global-interrupts = <0>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + ; + vdd-supply = <&gdsc_hlos1_vote_lpass_adsp>; + clocks = <&clock_gcc clk_hlos1_vote_lpass_adsp_smmu_clk>; + clock-names = "lpass_q6_smmu_clk"; + #clock-cells = <1>; + }; + + mmss_smmu: arm,smmu-mmss@cd00000 { + status = "ok"; + compatible = "qcom,smmu-v2"; + reg = <0xcd00000 0x40000>; + #iommu-cells = <1>; + qcom,register-save; + qcom,no-smr-check; + qcom,skip-init; + #global-interrupts = <0>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + vdd-supply = <&gdsc_bimc_smmu>; + clocks = <&clock_mmss clk_mmss_mnoc_ahb_clk>, + <&clock_mmss clk_mmss_bimc_smmu_ahb_clk>, + <&clock_mmss clk_mmss_bimc_smmu_axi_clk>; + clock-names = "mmss_mnoc_ahb_clk", + "mmss_bimc_smmu_ahb_clk", + "mmss_bimc_smmu_axi_clk"; + #clock-cells = <1>; + qcom,msm-bus,name = "smmu-bus-client-mmss"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,active-only; + qcom,msm-bus,num-paths = <2>; + /* ahb_clk_src, mmssnoc_axi_clk */ + qcom,msm-bus,vectors-KBps = + <102 722 0 0>, <29 512 0 0>, + <102 722 0 1000>, <29 512 0 1000>; + }; + + kgsl_smmu: arm,smmu-kgsl@5040000 { + status = "ok"; + compatible = "qcom,smmu-v2"; + reg = <0x5040000 0x10000>; + #iommu-cells = <1>; + qcom-tz-device-id = "GPU"; + qcom,dynamic; + qcom,register-save; + qcom,skip-init; + #global-interrupts = <0>; + interrupts = , + , + ; + qcom,deferred-regulator-disable-delay = <80>; + vdd-supply = <&gdsc_gpu_cx>; + clocks = <&clock_gcc clk_gcc_gpu_cfg_ahb_clk>, + <&clock_gcc clk_gcc_bimc_gfx_clk>, + <&clock_gcc clk_gcc_gpu_bimc_gfx_clk>; + + clock-names = "gcc_gpu_cfg_ahb_clk", + "gcc_bimc_gfx_clk", + "gcc_gpu_bimc_gfx_clk"; + #clock-cells = <1>; + }; + + iommu_test_device { + compatible = "iommu-debug-test"; + /* + * 42 shouldn't be used by anyone on the mmss_smmu. We just + * need _something_ here to get this node recognized by the + * SMMU driver. Our test uses ATOS, which doesn't use SIDs + * anyways, so using a dummy value is ok. + */ + iommus = <&mmss_smmu 42>; + }; + + iommu_coherent_test_device { + compatible = "iommu-debug-test"; + /* + * 43 shouldn't be used by anyone on the mmss_smmu. We just + * need _something_ here to get this node recognized by the + * SMMU driver. Our test uses ATOS, which doesn't use SIDs + * anyways, so using a dummy value is ok. + */ + iommus = <&mmss_smmu 43>; + dma-coherent; + }; +}; diff -Nruw linux-4.4.115-fbx/arch/arm/boot/dts/qcom./msm-arm-smmu-impl-defs-8998.dtsi linux-4.4.115-fbx/arch/arm/boot/dts/qcom/msm-arm-smmu-impl-defs-8998.dtsi --- linux-4.4.115-fbx/arch/arm/boot/dts/qcom./msm-arm-smmu-impl-defs-8998.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ linux-4.4.115-fbx/arch/arm/boot/dts/qcom/msm-arm-smmu-impl-defs-8998.dtsi 2019-01-22 16:16:21.179225361 +0100 @@ -0,0 +1,565 @@ +/* Copyright (c) 2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +&kgsl_smmu { + attach-impl-defs = <0x6000 0x2378>, + <0x6060 0x1055>, + <0x6470 0x110011>, + <0x6478 0x0>, + <0x647c 0x1000100>, + <0x6480 0x81108110>, + <0x6484 0x81108110>, + <0x6488 0x3e003e0>, + <0x648c 0x3e003e0>, + <0x6490 0x80008010>, + <0x6494 0x8020>, + <0x649c 0x6>, + <0x6800 0x6>, + <0x6900 0x3ff>, + <0x6924 0x604>, + <0x6928 0x11000>, + <0x6930 0x800>, + <0x6960 0x3>, + <0x6b64 0x1a5551>, + <0x6b68 0x2aaa2f82>; +}; + +&lpass_q6_smmu { + attach-impl-defs = <0x6000 0x3270>, + <0x6060 0x1055>, + <0x6070 0xe0>, + <0x6074 0xe0>, + <0x6078 0xe0>, + <0x607c 0xe0>, + <0x60f0 0xc0>, + <0x60f4 0xc8>, + <0x60f8 0xd0>, + <0x60fc 0xd8>, + <0x6170 0x0>, + <0x6174 0x30>, + <0x6178 0x60>, + <0x617c 0x90>, + <0x6270 0x0>, + <0x6274 0x2>, + <0x6278 0x4>, + <0x627c 0x6>, + <0x62f0 0x8>, + <0x62f4 0xe>, + <0x62f8 0x14>, + <0x62fc 0x1a>, + <0x6370 0x20>, + <0x6374 0x40>, + <0x6378 0x60>, + <0x637c 0x80>, + <0x67a0 0x0>, + <0x67a4 0x0>, + <0x67a8 0x20>, + <0x67b0 0x0>, + <0x67b4 0x8>, + <0x67b8 0xc8>, + <0x67d0 0x4>, + <0x67dc 0x8>, + <0x67e0 0x8>, + <0x6800 0x6>, + <0x6900 0x3ff>, + <0x6924 0x202>, + <0x6928 0x10a00>, + <0x6930 0x500>, + <0x6b64 0x121151>, + <0x6b68 0x8a840080>, + <0x6c00 0x0>, + <0x6c04 0x0>, + <0x6c08 0x0>, + <0x6c0c 0x0>, + <0x6c10 0x1>, + <0x6c14 0x1>, + <0x6c18 0x1>, + <0x6c1c 0x1>, + <0x6c20 0x2>, + <0x6c24 0x2>, + <0x6c28 0x2>, + <0x6c2c 0x2>, + <0x6c30 0x3>, + <0x6c34 0x3>, + <0x6c38 0x3>, + <0x6c3c 0x3>; +}; + +&mmss_smmu { + attach-impl-defs = <0x6000 0x3270>, + <0x6060 0x1055>, + <0x6800 0x6>, + <0x6900 0x3ff>, + <0x6924 0x204>, + <0x6928 0x11002>, + <0x6930 0x800>, + <0x6960 0xffffffff>, + <0x6964 0xffffffff>, + <0x6968 0xffffffff>, + <0x696c 0xffffffff>, + <0x6b48 0x330330>, + <0x6b4c 0x81>, + <0x6b50 0x3333>, + <0x6b54 0x3333>, + <0x6b64 0x1a5555>, + <0x6b68 0x9aaa892a>, + <0x6b70 0x10100002>, + <0x6b74 0x10100002>, + <0x6b78 0x10100002>, + <0x6b80 0x20042004>, + <0x6b84 0x20042004>; +}; + +&anoc1_smmu { + attach-impl-defs = <0x6000 0x3270>, + <0x6060 0x1055>, + <0x6070 0x19>, + <0x6074 0x39>, + <0x6078 0x41>, + <0x607c 0x59>, + <0x6080 0x95>, + <0x6084 0x98>, + <0x6088 0xc0>, + <0x608c 0xc0>, + <0x60f0 0x0>, + <0x60f4 0x2>, + <0x60f8 0x5>, + <0x60fc 0x8>, + <0x6100 0x16>, + <0x6104 0x17>, + <0x6108 0x19>, + <0x610c 0x19>, + <0x6170 0x0>, + <0x6174 0x0>, + <0x6178 0x0>, + <0x617c 0x0>, + <0x6180 0x0>, + <0x6184 0x0>, + <0x6188 0x0>, + <0x618c 0x0>, + <0x6270 0x0>, + <0x6274 0xd>, + <0x6278 0xe>, + <0x627c 0x12>, + <0x6280 0x16>, + <0x6284 0x16>, + <0x6288 0x18>, + <0x628c 0x18>, + <0x62f0 0x18>, + <0x62f4 0x1b>, + <0x62f8 0x1c>, + <0x62fc 0x24>, + <0x6300 0x28>, + <0x6304 0x2b>, + <0x6308 0x31>, + <0x630c 0x31>, + <0x6370 0x31>, + <0x6374 0x34>, + <0x6378 0x35>, + <0x637c 0x47>, + <0x6380 0x4f>, + <0x6384 0x54>, + <0x6388 0x60>, + <0x638c 0x60>, + <0x67a0 0x0>, + <0x67a4 0xa7>, + <0x67a8 0xc0>, + <0x67b0 0x0>, + <0x67b4 0x18>, + <0x67b8 0x7c>, + <0x67d0 0x0>, + <0x67dc 0x4>, + <0x67e0 0x8>, + <0x6800 0x6>, + <0x6900 0x3ff>, + <0x6b64 0x121151>, + <0x6b68 0xbb804080>, + <0x6c00 0x0>, + <0x6c04 0x0>, + <0x6c08 0x0>, + <0x6c0c 0x0>, + <0x6c10 0x0>, + <0x6c14 0x0>, + <0x6c18 0x0>, + <0x6c1c 0x0>, + <0x6c20 0x0>, + <0x6c24 0x0>, + <0x6c28 0x0>, + <0x6c2c 0x0>, + <0x6c30 0x0>, + <0x6c34 0x0>, + <0x6c38 0x0>, + <0x6c3c 0x0>, + <0x6c40 0x0>, + <0x6c44 0x0>, + <0x6c48 0x0>, + <0x6c4c 0x0>, + <0x6c50 0x0>, + <0x6c54 0x0>, + <0x6c58 0x0>, + <0x6c5c 0x0>, + <0x6c60 0x0>, + <0x6c64 0x0>, + <0x6c68 0x0>, + <0x6c6c 0x0>, + <0x6c70 0x0>, + <0x6c74 0x0>, + <0x6c78 0x0>, + <0x6c7c 0x0>, + <0x6c80 0x0>, + <0x6c84 0x1>, + <0x6c88 0x0>, + <0x6c8c 0x0>, + <0x6c90 0x4>, + <0x6c94 0x3>, + <0x6c98 0x2>, + <0x6c9c 0x0>, + <0x6ca0 0x5>, + <0x6ca4 0x5>, + <0x6ca8 0x0>, + <0x6cac 0x0>, + <0x6cb0 0x0>, + <0x6cb4 0x0>, + <0x6cb8 0x0>, + <0x6cbc 0x0>, + <0x6cc0 0x0>, + <0x6cc4 0x0>, + <0x6cc8 0x0>, + <0x6ccc 0x0>, + <0x6cd0 0x0>, + <0x6cd4 0x0>, + <0x6cd8 0x0>, + <0x6cdc 0x0>, + <0x6ce0 0x0>, + <0x6ce4 0x0>, + <0x6ce8 0x0>, + <0x6cec 0x0>, + <0x6cf0 0x0>, + <0x6cf4 0x0>, + <0x6cf8 0x0>, + <0x6cfc 0x0>, + <0x6d00 0x0>, + <0x6d04 0x0>, + <0x6d08 0x0>, + <0x6d0c 0x0>, + <0x6d10 0x0>, + <0x6d14 0x0>, + <0x6d18 0x0>, + <0x6d1c 0x0>, + <0x6d20 0x0>, + <0x6d24 0x0>, + <0x6d28 0x0>, + <0x6d2c 0x0>, + <0x6d30 0x0>, + <0x6d34 0x0>, + <0x6d38 0x0>, + <0x6d3c 0x0>, + <0x6d40 0x0>, + <0x6d44 0x0>, + <0x6d48 0x0>, + <0x6d4c 0x0>, + <0x6d50 0x0>, + <0x6d54 0x0>, + <0x6d58 0x0>, + <0x6d5c 0x0>, + <0x6d60 0x0>, + <0x6d64 0x0>, + <0x6d68 0x0>, + <0x6d6c 0x0>, + <0x6d70 0x0>, + <0x6d74 0x0>, + <0x6d78 0x0>, + <0x6d7c 0x0>, + <0x6d80 0x0>, + <0x6d84 0x0>, + <0x6d88 0x0>, + <0x6d8c 0x0>, + <0x6d90 0x0>, + <0x6d94 0x0>, + <0x6d98 0x0>, + <0x6d9c 0x0>, + <0x6da0 0x0>, + <0x6da4 0x0>, + <0x6da8 0x0>, + <0x6dac 0x0>, + <0x6db0 0x0>, + <0x6db4 0x0>, + <0x6db8 0x0>, + <0x6dbc 0x0>, + <0x6dc0 0x0>, + <0x6dc4 0x0>, + <0x6dc8 0x0>, + <0x6dcc 0x0>, + <0x6dd0 0x0>, + <0x6dd4 0x0>, + <0x6dd8 0x0>, + <0x6ddc 0x0>, + <0x6de0 0x0>, + <0x6de4 0x0>, + <0x6de8 0x0>, + <0x6dec 0x0>, + <0x6df0 0x0>, + <0x6df4 0x0>, + <0x6df8 0x0>, + <0x6dfc 0x0>; +}; + +&anoc2_smmu { + attach-impl-defs = <0x6000 0x3270>, + <0x6060 0x1055>, + <0x6070 0x12>, + <0x6074 0x26>, + <0x6078 0x3a>, + <0x607c 0x3c>, + <0x6080 0x3f>, + <0x6084 0x67>, + <0x6088 0x6c>, + <0x608c 0x74>, + <0x6090 0x7c>, + <0x6094 0x80>, + <0x6098 0xa0>, + <0x609c 0xa0>, + <0x60a0 0xa0>, + <0x60a4 0xa0>, + <0x60a8 0xa0>, + <0x60ac 0xa0>, + <0x60f0 0x0>, + <0x60f4 0x1>, + <0x60f8 0x3>, + <0x60fc 0x4>, + <0x6100 0x5>, + <0x6104 0x7>, + <0x6108 0x8>, + <0x610c 0x10>, + <0x6110 0x10>, + <0x6114 0x10>, + <0x6118 0x12>, + <0x611c 0x12>, + <0x6120 0x12>, + <0x6124 0x12>, + <0x6128 0x12>, + <0x612c 0x12>, + <0x6170 0x0>, + <0x6174 0x0>, + <0x6178 0x0>, + <0x617c 0x0>, + <0x6180 0x0>, + <0x6184 0x0>, + <0x6188 0x0>, + <0x618c 0x0>, + <0x6190 0x0>, + <0x6194 0x0>, + <0x6198 0x0>, + <0x619c 0x0>, + <0x61a0 0x0>, + <0x61a4 0x0>, + <0x61a8 0x0>, + <0x61ac 0x0>, + <0x6270 0x0>, + <0x6274 0x1>, + <0x6278 0x2>, + <0x627c 0x4>, + <0x6280 0x4>, + <0x6284 0x6>, + <0x6288 0x6>, + <0x628c 0x18>, + <0x6290 0x1a>, + <0x6294 0x1a>, + <0x6298 0x1e>, + <0x629c 0x1e>, + <0x62a0 0x1e>, + <0x62a4 0x1e>, + <0x62a8 0x1e>, + <0x62ac 0x1e>, + <0x62f0 0x1e>, + <0x62f4 0x24>, + <0x62f8 0x2a>, + <0x62fc 0x2c>, + <0x6300 0x2d>, + <0x6304 0x33>, + <0x6308 0x34>, + <0x630c 0x3a>, + <0x6310 0x3c>, + <0x6314 0x44>, + <0x6318 0x48>, + <0x631c 0x48>, + <0x6320 0x48>, + <0x6324 0x48>, + <0x6328 0x48>, + <0x632c 0x48>, + <0x6370 0x48>, + <0x6374 0x4d>, + <0x6378 0x52>, + <0x637c 0x56>, + <0x6380 0x59>, + <0x6384 0x63>, + <0x6388 0x68>, + <0x638c 0x70>, + <0x6390 0x78>, + <0x6394 0x88>, + <0x6398 0x90>, + <0x639c 0x90>, + <0x63a0 0x90>, + <0x63a4 0x90>, + <0x63a8 0x90>, + <0x63ac 0x90>, + <0x67a0 0x0>, + <0x67a4 0x8e>, + <0x67a8 0xa0>, + <0x67b0 0x0>, + <0x67b4 0x1e>, + <0x67b8 0xc6>, + <0x67d0 0x0>, + <0x67dc 0x4>, + <0x67e0 0x8>, + <0x6800 0x6>, + <0x6900 0x3ff>, + <0x6b48 0x330331>, + <0x6b4c 0x81>, + <0x6b50 0x1313>, + <0x6b64 0x121155>, + <0x6b68 0xea880920>, + <0x6b70 0x10100101>, + <0x6b74 0xc0c0000>, + <0x6b78 0xc0c0000>, + <0x6b80 0x20012001>, + <0x6b84 0x20012001>, + <0x6c00 0x5>, + <0x6c04 0x0>, + <0x6c08 0x5>, + <0x6c0c 0x0>, + <0x6c10 0x5>, + <0x6c14 0x0>, + <0x6c18 0x5>, + <0x6c1c 0x0>, + <0x6c20 0x5>, + <0x6c24 0x0>, + <0x6c28 0x0>, + <0x6c2c 0x0>, + <0x6c30 0x0>, + <0x6c34 0x0>, + <0x6c38 0x0>, + <0x6c3c 0x0>, + <0x6c40 0x0>, + <0x6c44 0x0>, + <0x6c48 0x0>, + <0x6c4c 0x0>, + <0x6c50 0x0>, + <0x6c54 0x0>, + <0x6c58 0x0>, + <0x6c5c 0x0>, + <0x6c60 0x0>, + <0x6c64 0x0>, + <0x6c68 0x0>, + <0x6c6c 0x0>, + <0x6c70 0x0>, + <0x6c74 0x0>, + <0x6c78 0x0>, + <0x6c7c 0x0>, + <0x6c80 0x0>, + <0x6c84 0x0>, + <0x6c88 0x0>, + <0x6c8c 0x0>, + <0x6c90 0x0>, + <0x6c94 0x0>, + <0x6c98 0x0>, + <0x6c9c 0x0>, + <0x6ca0 0x0>, + <0x6ca4 0x0>, + <0x6ca8 0x0>, + <0x6cac 0x0>, + <0x6cb0 0x0>, + <0x6cb4 0x0>, + <0x6cb8 0x0>, + <0x6cbc 0x0>, + <0x6cc0 0x0>, + <0x6cc4 0x0>, + <0x6cc8 0x0>, + <0x6ccc 0x0>, + <0x6cd0 0x0>, + <0x6cd4 0x0>, + <0x6cd8 0x0>, + <0x6cdc 0x0>, + <0x6ce0 0x0>, + <0x6ce4 0x0>, + <0x6ce8 0x0>, + <0x6cec 0x0>, + <0x6cf0 0x0>, + <0x6cf4 0x0>, + <0x6cf8 0x0>, + <0x6cfc 0x0>, + <0x6d00 0x8>, + <0x6d04 0x0>, + <0x6d08 0x8>, + <0x6d0c 0x0>, + <0x6d10 0x7>, + <0x6d14 0x0>, + <0x6d18 0x3>, + <0x6d1c 0x2>, + <0x6d20 0x4>, + <0x6d24 0x0>, + <0x6d28 0x4>, + <0x6d2c 0x0>, + <0x6d30 0x6>, + <0x6d34 0x0>, + <0x6d38 0x9>, + <0x6d3c 0x0>, + <0x6d40 0x0>, + <0x6d44 0x1>, + <0x6d48 0x4>, + <0x6d4c 0x0>, + <0x6d50 0x4>, + <0x6d54 0x0>, + <0x6d58 0x0>, + <0x6d5c 0x0>, + <0x6d60 0x0>, + <0x6d64 0x0>, + <0x6d68 0x0>, + <0x6d6c 0x0>, + <0x6d70 0x0>, + <0x6d74 0x0>, + <0x6d78 0x0>, + <0x6d7c 0x0>, + <0x6d80 0x0>, + <0x6d84 0x0>, + <0x6d88 0x0>, + <0x6d8c 0x0>, + <0x6d90 0x0>, + <0x6d94 0x0>, + <0x6d98 0x0>, + <0x6d9c 0x0>, + <0x6da0 0x0>, + <0x6da4 0x0>, + <0x6da8 0x0>, + <0x6dac 0x0>, + <0x6db0 0x0>, + <0x6db4 0x0>, + <0x6db8 0x0>, + <0x6dbc 0x0>, + <0x6dc0 0x0>, + <0x6dc4 0x0>, + <0x6dc8 0x0>, + <0x6dcc 0x0>, + <0x6dd0 0x0>, + <0x6dd4 0x0>, + <0x6dd8 0x0>, + <0x6ddc 0x0>, + <0x6de0 0x0>, + <0x6de4 0x0>, + <0x6de8 0x0>, + <0x6dec 0x0>, + <0x6df0 0x0>, + <0x6df4 0x0>, + <0x6df8 0x0>, + <0x6dfc 0x0>; +}; diff -Nruw linux-4.4.115-fbx/arch/arm/boot/dts/qcom./msm-audio-lpass.dtsi linux-4.4.115-fbx/arch/arm/boot/dts/qcom/msm-audio-lpass.dtsi --- linux-4.4.115-fbx/arch/arm/boot/dts/qcom./msm-audio-lpass.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ linux-4.4.115-fbx/arch/arm/boot/dts/qcom/msm-audio-lpass.dtsi 2019-10-29 09:26:22.905195956 +0100 @@ -0,0 +1,529 @@ +/* + * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&soc { + + pcm0: qcom,msm-pcm { + compatible = "qcom,msm-pcm-dsp"; + qcom,msm-pcm-dsp-id = <0>; + }; + + routing: qcom,msm-pcm-routing { + compatible = "qcom,msm-pcm-routing"; + }; + + compr: qcom,msm-compr-dsp { + compatible = "qcom,msm-compr-dsp"; + }; + + pcm1: qcom,msm-pcm-low-latency { + compatible = "qcom,msm-pcm-dsp"; + qcom,msm-pcm-dsp-id = <1>; + qcom,msm-pcm-low-latency; + qcom,latency-level = "regular"; + }; + + pcm2: qcom,msm-ultra-low-latency { + compatible = "qcom,msm-pcm-dsp"; + qcom,msm-pcm-dsp-id = <2>; + qcom,msm-pcm-low-latency; + qcom,latency-level = "ultra"; + }; + + pcm_noirq: qcom,msm-pcm-dsp-noirq { + compatible = "qcom,msm-pcm-dsp-noirq"; + qcom,msm-pcm-low-latency; + qcom,latency-level = "ultra"; + }; + + compress: qcom,msm-compress-dsp { + compatible = "qcom,msm-compress-dsp"; + }; + + voip: qcom,msm-voip-dsp { + compatible = "qcom,msm-voip-dsp"; + }; + + voice: qcom,msm-pcm-voice { + compatible = "qcom,msm-pcm-voice"; + qcom,destroy-cvd; + }; + + stub_codec: qcom,msm-stub-codec { + compatible = "qcom,msm-stub-codec"; + }; + + qcom,msm-dai-fe { + compatible = "qcom,msm-dai-fe"; + }; + + afe: qcom,msm-pcm-afe { + compatible = "qcom,msm-pcm-afe"; + }; + + dai_hdmi: qcom,msm-dai-q6-hdmi { + compatible = "qcom,msm-dai-q6-hdmi"; + qcom,msm-dai-q6-dev-id = <8>; + }; + + dai_dp: qcom,msm-dai-q6-dp { + compatible = "qcom,msm-dai-q6-hdmi"; + qcom,msm-dai-q6-dev-id = <24608>; + }; + + loopback: qcom,msm-pcm-loopback { + compatible = "qcom,msm-pcm-loopback"; + }; + + trans_loopback: qcom,msm-transcode-loopback { + compatible = "qcom,msm-transcode-loopback"; + }; + + qcom,msm-dai-mi2s { + compatible = "qcom,msm-dai-mi2s"; + dai_mi2s0: qcom,msm-dai-q6-mi2s-prim { + compatible = "qcom,msm-dai-q6-mi2s"; + qcom,msm-dai-q6-mi2s-dev-id = <0>; + qcom,msm-mi2s-rx-lines = <3>; + qcom,msm-mi2s-tx-lines = <0>; + }; + + dai_mi2s1: qcom,msm-dai-q6-mi2s-sec { + compatible = "qcom,msm-dai-q6-mi2s"; + qcom,msm-dai-q6-mi2s-dev-id = <1>; + qcom,msm-mi2s-rx-lines = <1>; + qcom,msm-mi2s-tx-lines = <0>; + }; + + dai_mi2s2: qcom,msm-dai-q6-mi2s-tert { + compatible = "qcom,msm-dai-q6-mi2s"; + qcom,msm-dai-q6-mi2s-dev-id = <2>; + qcom,msm-mi2s-rx-lines = <0>; + qcom,msm-mi2s-tx-lines = <3>; + }; + + dai_mi2s3: qcom,msm-dai-q6-mi2s-quat { + compatible = "qcom,msm-dai-q6-mi2s"; + qcom,msm-dai-q6-mi2s-dev-id = <3>; + qcom,msm-mi2s-rx-lines = <1>; + qcom,msm-mi2s-tx-lines = <2>; + }; + + dai_mi2s4: qcom,msm-dai-q6-mi2s-quin { + compatible = "qcom,msm-dai-q6-mi2s"; + qcom,msm-dai-q6-mi2s-dev-id = <5>; + qcom,msm-mi2s-rx-lines = <1>; + qcom,msm-mi2s-tx-lines = <2>; + }; + + dai_mi2s5: qcom,msm-dai-q6-mi2s-senary { + compatible = "qcom,msm-dai-q6-mi2s"; + qcom,msm-dai-q6-mi2s-dev-id = <6>; + qcom,msm-mi2s-rx-lines = <0>; + qcom,msm-mi2s-tx-lines = <3>; + }; + }; + + lsm: qcom,msm-lsm-client { + compatible = "qcom,msm-lsm-client"; + }; + + qcom,msm-dai-q6 { + compatible = "qcom,msm-dai-q6"; + sb_0_rx: qcom,msm-dai-q6-sb-0-rx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <16384>; + }; + + sb_0_tx: qcom,msm-dai-q6-sb-0-tx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <16385>; + }; + + sb_1_rx: qcom,msm-dai-q6-sb-1-rx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <16386>; + }; + + sb_1_tx: qcom,msm-dai-q6-sb-1-tx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <16387>; + }; + + sb_2_rx: qcom,msm-dai-q6-sb-2-rx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <16388>; + }; + + sb_2_tx: qcom,msm-dai-q6-sb-2-tx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <16389>; + }; + + + sb_3_rx: qcom,msm-dai-q6-sb-3-rx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <16390>; + }; + + sb_3_tx: qcom,msm-dai-q6-sb-3-tx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <16391>; + }; + + sb_4_rx: qcom,msm-dai-q6-sb-4-rx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <16392>; + }; + + sb_4_tx: qcom,msm-dai-q6-sb-4-tx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <16393>; + }; + + sb_5_tx: qcom,msm-dai-q6-sb-5-tx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <16395>; + }; + + sb_5_rx: qcom,msm-dai-q6-sb-5-rx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <16394>; + }; + + sb_6_rx: qcom,msm-dai-q6-sb-6-rx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <16396>; + }; + + sb_7_rx: qcom,msm-dai-q6-sb-7-rx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <16398>; + }; + + sb_7_tx: qcom,msm-dai-q6-sb-7-tx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <16399>; + }; + + sb_8_rx: qcom,msm-dai-q6-sb-8-rx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <16400>; + }; + + sb_8_tx: qcom,msm-dai-q6-sb-8-tx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <16401>; + }; + + bt_sco_rx: qcom,msm-dai-q6-bt-sco-rx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <12288>; + }; + + bt_sco_tx: qcom,msm-dai-q6-bt-sco-tx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <12289>; + }; + + int_fm_rx: qcom,msm-dai-q6-int-fm-rx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <12292>; + }; + + int_fm_tx: qcom,msm-dai-q6-int-fm-tx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <12293>; + }; + + afe_pcm_rx: qcom,msm-dai-q6-be-afe-pcm-rx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <224>; + }; + + afe_pcm_tx: qcom,msm-dai-q6-be-afe-pcm-tx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <225>; + }; + + afe_proxy_rx: qcom,msm-dai-q6-afe-proxy-rx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <241>; + }; + + afe_proxy_tx: qcom,msm-dai-q6-afe-proxy-tx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <240>; + }; + + incall_record_rx: qcom,msm-dai-q6-incall-record-rx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <32771>; + }; + + incall_record_tx: qcom,msm-dai-q6-incall-record-tx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <32772>; + }; + + incall_music_rx: qcom,msm-dai-q6-incall-music-rx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <32773>; + }; + + incall_music_2_rx: qcom,msm-dai-q6-incall-music-2-rx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <32770>; + }; + + usb_audio_rx: qcom,msm-dai-q6-usb-audio-rx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <28672>; + }; + + usb_audio_tx: qcom,msm-dai-q6-usb-audio-tx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <28673>; + }; + }; + + hostless: qcom,msm-pcm-hostless { + compatible = "qcom,msm-pcm-hostless"; + }; + + dai_pri_auxpcm: qcom,msm-pri-auxpcm { + compatible = "qcom,msm-auxpcm-dev"; + qcom,msm-cpudai-auxpcm-mode = <0>, <0>; + qcom,msm-cpudai-auxpcm-sync = <1>, <1>; + qcom,msm-cpudai-auxpcm-frame = <5>, <4>; + qcom,msm-cpudai-auxpcm-quant = <2>, <2>; + qcom,msm-cpudai-auxpcm-num-slots = <1>, <1>; + qcom,msm-cpudai-auxpcm-slot-mapping = <1>, <1>; + qcom,msm-cpudai-auxpcm-data = <0>, <0>; + qcom,msm-cpudai-auxpcm-pcm-clk-rate = <2048000>, <2048000>; + qcom,msm-auxpcm-interface = "primary"; + qcom,msm-cpudai-afe-clk-ver = <2>; + }; + + dai_sec_auxpcm: qcom,msm-sec-auxpcm { + compatible = "qcom,msm-auxpcm-dev"; + qcom,msm-cpudai-auxpcm-mode = <0>, <0>; + qcom,msm-cpudai-auxpcm-sync = <1>, <1>; + qcom,msm-cpudai-auxpcm-frame = <5>, <4>; + qcom,msm-cpudai-auxpcm-quant = <2>, <2>; + qcom,msm-cpudai-auxpcm-num-slots = <1>, <1>; + qcom,msm-cpudai-auxpcm-slot-mapping = <1>, <1>; + qcom,msm-cpudai-auxpcm-data = <0>, <0>; + qcom,msm-cpudai-auxpcm-pcm-clk-rate = <2048000>, <2048000>; + qcom,msm-auxpcm-interface = "secondary"; + qcom,msm-cpudai-afe-clk-ver = <2>; + }; + + dai_tert_auxpcm: qcom,msm-tert-auxpcm { + compatible = "qcom,msm-auxpcm-dev"; + qcom,msm-cpudai-auxpcm-mode = <0>, <0>; + qcom,msm-cpudai-auxpcm-sync = <1>, <1>; + qcom,msm-cpudai-auxpcm-frame = <5>, <4>; + qcom,msm-cpudai-auxpcm-quant = <2>, <2>; + qcom,msm-cpudai-auxpcm-num-slots = <1>, <1>; + qcom,msm-cpudai-auxpcm-slot-mapping = <1>, <1>; + qcom,msm-cpudai-auxpcm-data = <0>, <0>; + qcom,msm-cpudai-auxpcm-pcm-clk-rate = <2048000>, <2048000>; + qcom,msm-auxpcm-interface = "tertiary"; + qcom,msm-cpudai-afe-clk-ver = <2>; + }; + + dai_quat_auxpcm: qcom,msm-quat-auxpcm { + compatible = "qcom,msm-auxpcm-dev"; + qcom,msm-cpudai-auxpcm-mode = <0>, <0>; + qcom,msm-cpudai-auxpcm-sync = <1>, <1>; + qcom,msm-cpudai-auxpcm-frame = <5>, <4>; + qcom,msm-cpudai-auxpcm-quant = <2>, <2>; + qcom,msm-cpudai-auxpcm-num-slots = <1>, <1>; + qcom,msm-cpudai-auxpcm-slot-mapping = <1>, <1>; + qcom,msm-cpudai-auxpcm-data = <0>, <0>; + qcom,msm-cpudai-auxpcm-pcm-clk-rate = <2048000>, <2048000>; + qcom,msm-auxpcm-interface = "quaternary"; + qcom,msm-cpudai-afe-clk-ver = <2>; + }; + + hdmi_dba: qcom,msm-hdmi-dba-codec-rx { + compatible = "qcom,msm-hdmi-dba-codec-rx"; + qcom,dba-bridge-chip = "adv7533"; + }; + + msm_audio_ion: qcom,msm-audio-ion { + compatible = "qcom,msm-audio-ion"; + qcom,smmu-version = <1>; + qcom,smmu-enabled; + iommus = <&adsp_io 1>; + }; + + qcom,msm-adsp-loader { + status = "ok"; + compatible = "qcom,adsp-loader"; + qcom,adsp-state = <0>; + }; + + qcom,msm-dai-tdm-pri-rx { + compatible = "qcom,msm-dai-tdm"; + qcom,msm-cpudai-tdm-group-id = <37120>; + qcom,msm-cpudai-tdm-group-num-ports = <1>; + qcom,msm-cpudai-tdm-group-port-id = <36864>; + qcom,msm-cpudai-tdm-clk-rate = <1536000>; + qcom,msm-cpudai-tdm-clk-internal = <1>; + qcom,msm-cpudai-tdm-sync-mode = <1>; + qcom,msm-cpudai-tdm-sync-src = <1>; + qcom,msm-cpudai-tdm-data-out = <0>; + qcom,msm-cpudai-tdm-invert-sync = <1>; + qcom,msm-cpudai-tdm-data-delay = <1>; + dai_pri_tdm_rx_0: qcom,msm-dai-q6-tdm-pri-rx-0 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36864>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + }; + + qcom,msm-dai-tdm-pri-tx { + compatible = "qcom,msm-dai-tdm"; + qcom,msm-cpudai-tdm-group-id = <37121>; + qcom,msm-cpudai-tdm-group-num-ports = <1>; + qcom,msm-cpudai-tdm-group-port-id = <36865>; + qcom,msm-cpudai-tdm-clk-rate = <1536000>; + qcom,msm-cpudai-tdm-clk-internal = <1>; + qcom,msm-cpudai-tdm-sync-mode = <1>; + qcom,msm-cpudai-tdm-sync-src = <1>; + qcom,msm-cpudai-tdm-data-out = <0>; + qcom,msm-cpudai-tdm-invert-sync = <1>; + qcom,msm-cpudai-tdm-data-delay = <1>; + dai_pri_tdm_tx_0: qcom,msm-dai-q6-tdm-pri-tx-0 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36865>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + }; + + qcom,msm-dai-tdm-sec-rx { + compatible = "qcom,msm-dai-tdm"; + qcom,msm-cpudai-tdm-group-id = <37136>; + qcom,msm-cpudai-tdm-group-num-ports = <1>; + qcom,msm-cpudai-tdm-group-port-id = <36880>; + qcom,msm-cpudai-tdm-clk-rate = <1536000>; + qcom,msm-cpudai-tdm-clk-internal = <1>; + qcom,msm-cpudai-tdm-sync-mode = <1>; + qcom,msm-cpudai-tdm-sync-src = <1>; + qcom,msm-cpudai-tdm-data-out = <0>; + qcom,msm-cpudai-tdm-invert-sync = <1>; + qcom,msm-cpudai-tdm-data-delay = <1>; + dai_sec_tdm_rx_0: qcom,msm-dai-q6-tdm-sec-rx-0 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36880>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + }; + + qcom,msm-dai-tdm-sec-tx { + compatible = "qcom,msm-dai-tdm"; + qcom,msm-cpudai-tdm-group-id = <37137>; + qcom,msm-cpudai-tdm-group-num-ports = <1>; + qcom,msm-cpudai-tdm-group-port-id = <36881>; + qcom,msm-cpudai-tdm-clk-rate = <1536000>; + qcom,msm-cpudai-tdm-clk-internal = <1>; + qcom,msm-cpudai-tdm-sync-mode = <1>; + qcom,msm-cpudai-tdm-sync-src = <1>; + qcom,msm-cpudai-tdm-data-out = <0>; + qcom,msm-cpudai-tdm-invert-sync = <1>; + qcom,msm-cpudai-tdm-data-delay = <1>; + dai_sec_tdm_tx_0: qcom,msm-dai-q6-tdm-sec-tx-0 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36881>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + }; + + qcom,msm-dai-tdm-tert-rx { + compatible = "qcom,msm-dai-tdm"; + qcom,msm-cpudai-tdm-group-id = <37152>; + qcom,msm-cpudai-tdm-group-num-ports = <1>; + qcom,msm-cpudai-tdm-group-port-id = <36896>; + qcom,msm-cpudai-tdm-clk-rate = <1536000>; + qcom,msm-cpudai-tdm-clk-internal = <1>; + qcom,msm-cpudai-tdm-sync-mode = <1>; + qcom,msm-cpudai-tdm-sync-src = <1>; + qcom,msm-cpudai-tdm-data-out = <0>; + qcom,msm-cpudai-tdm-invert-sync = <1>; + qcom,msm-cpudai-tdm-data-delay = <1>; + dai_tert_tdm_rx_0: qcom,msm-dai-q6-tdm-tert-rx-0 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36896>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + }; + + qcom,msm-dai-tdm-tert-tx { + compatible = "qcom,msm-dai-tdm"; + qcom,msm-cpudai-tdm-group-id = <37153>; + qcom,msm-cpudai-tdm-group-num-ports = <1>; + qcom,msm-cpudai-tdm-group-port-id = <36897 >; + qcom,msm-cpudai-tdm-clk-rate = <1536000>; + qcom,msm-cpudai-tdm-clk-internal = <1>; + qcom,msm-cpudai-tdm-sync-mode = <1>; + qcom,msm-cpudai-tdm-sync-src = <1>; + qcom,msm-cpudai-tdm-data-out = <0>; + qcom,msm-cpudai-tdm-invert-sync = <1>; + qcom,msm-cpudai-tdm-data-delay = <1>; + dai_tert_tdm_tx_0: qcom,msm-dai-q6-tdm-tert-tx-0 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36897 >; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + }; + + qcom,msm-dai-tdm-quat-rx { + compatible = "qcom,msm-dai-tdm"; + qcom,msm-cpudai-tdm-group-id = <37168>; + qcom,msm-cpudai-tdm-group-num-ports = <1>; + qcom,msm-cpudai-tdm-group-port-id = <36912>; + qcom,msm-cpudai-tdm-clk-rate = <1536000>; + qcom,msm-cpudai-tdm-clk-internal = <1>; + qcom,msm-cpudai-tdm-sync-mode = <1>; + qcom,msm-cpudai-tdm-sync-src = <1>; + qcom,msm-cpudai-tdm-data-out = <0>; + qcom,msm-cpudai-tdm-invert-sync = <1>; + qcom,msm-cpudai-tdm-data-delay = <1>; + dai_quat_tdm_rx_0: qcom,msm-dai-q6-tdm-quat-rx-0 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36912>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + }; + + qcom,msm-dai-tdm-quat-tx { + compatible = "qcom,msm-dai-tdm"; + qcom,msm-cpudai-tdm-group-id = <37169>; + qcom,msm-cpudai-tdm-group-num-ports = <1>; + qcom,msm-cpudai-tdm-group-port-id = <36913 >; + qcom,msm-cpudai-tdm-clk-rate = <1536000>; + qcom,msm-cpudai-tdm-clk-internal = <1>; + qcom,msm-cpudai-tdm-sync-mode = <1>; + qcom,msm-cpudai-tdm-sync-src = <1>; + qcom,msm-cpudai-tdm-data-out = <0>; + qcom,msm-cpudai-tdm-invert-sync = <1>; + qcom,msm-cpudai-tdm-data-delay = <1>; + dai_quat_tdm_tx_0: qcom,msm-dai-q6-tdm-quat-tx-0 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36913 >; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + }; +}; diff -Nruw linux-4.4.115-fbx/arch/arm/boot/dts/qcom./msm-gdsc-8998.dtsi linux-4.4.115-fbx/arch/arm/boot/dts/qcom/msm-gdsc-8998.dtsi --- linux-4.4.115-fbx/arch/arm/boot/dts/qcom./msm-gdsc-8998.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ linux-4.4.115-fbx/arch/arm/boot/dts/qcom/msm-gdsc-8998.dtsi 2019-01-22 16:16:21.179225361 +0100 @@ -0,0 +1,146 @@ +/* + * Copyright (c) 2015-2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&soc { + /* GCC GDSCs */ + gdsc_usb30: qcom,gdsc@10f004 { + compatible = "qcom,gdsc"; + regulator-name = "gdsc_usb30"; + reg = <0x10f004 0x4>; + status = "disabled"; + }; + + gdsc_pcie_0: qcom,gdsc@16b004 { + compatible = "qcom,gdsc"; + regulator-name = "gdsc_pcie_0"; + reg = <0x16b004 0x4>; + status = "disabled"; + }; + + gdsc_ufs: qcom,gdsc@175004 { + compatible = "qcom,gdsc"; + regulator-name = "gdsc_ufs"; + reg = <0x175004 0x4>; + status = "disabled"; + }; + + gdsc_hlos1_vote_lpass_adsp: qcom,gdsc@17d034 { + compatible = "qcom,gdsc"; + regulator-name = "gdsc_hlos1_vote_lpass_adsp"; + reg = <0x17d034 0x4>; + qcom,no-status-check-on-disable; + qcom,gds-timeout = <500>; + status = "disabled"; + }; + + gdsc_hlos1_vote_lpass_core: qcom,gdsc@17d038 { + compatible = "qcom,gdsc"; + regulator-name = "gdsc_hlos1_vote_lpass_core"; + reg = <0x17d038 0x4>; + qcom,no-status-check-on-disable; + qcom,gds-timeout = <500>; + status = "disabled"; + }; + + /* MMSS GDSCs */ + gdsc_bimc_smmu: qcom,gdsc@c8ce020 { + compatible = "qcom,gdsc"; + regulator-name = "gdsc_bimc_smmu"; + reg = <0xc8ce020 0x4>, + <0xc8ce024 0x4>; + reg-names = "base", "hw_ctrl_addr"; + qcom,no-status-check-on-disable; + qcom,gds-timeout = <500>; + status = "disabled"; + }; + + gdsc_venus: qcom,gdsc@c8c1024 { + compatible = "qcom,gdsc"; + regulator-name = "gdsc_venus"; + reg = <0xc8c1024 0x4>; + status = "disabled"; + }; + + gdsc_venus_core0: qcom,gdsc@c8c1040 { + compatible = "qcom,gdsc"; + regulator-name = "gdsc_venus_core0"; + reg = <0xc8c1040 0x4>; + status = "disabled"; + }; + + gdsc_venus_core1: qcom,gdsc@c8c1044 { + compatible = "qcom,gdsc"; + regulator-name = "gdsc_venus_core1"; + reg = <0xc8c1044 0x4>; + status = "disabled"; + }; + + gdsc_camss_top: qcom,gdsc@c8c34a0 { + compatible = "qcom,gdsc"; + regulator-name = "gdsc_camss_top"; + reg = <0xc8c34a0 0x4>; + status = "disabled"; + }; + + gdsc_vfe0: qcom,gdsc@c8c3664 { + compatible = "qcom,gdsc"; + regulator-name = "gdsc_vfe0"; + reg = <0xc8c3664 0x4>; + status = "disabled"; + }; + + gdsc_vfe1: qcom,gdsc@c8c3674 { + compatible = "qcom,gdsc"; + regulator-name = "gdsc_vfe1"; + reg = <0xc8c3674 0x4>; + status = "disabled"; + }; + + gdsc_cpp: qcom,gdsc@c8c36d4 { + compatible = "qcom,gdsc"; + regulator-name = "gdsc_cpp"; + reg = <0xc8c36d4 0x4>; + status = "disabled"; + }; + + gdsc_mdss: qcom,gdsc@c8c2304 { + compatible = "qcom,gdsc"; + regulator-name = "gdsc_mdss"; + reg = <0xc8c2304 0x4>; + status = "disabled"; + }; + + /* GPU GDSCs */ + gdsc_gpu_cx: qcom,gdsc@5066004 { + compatible = "qcom,gdsc"; + regulator-name = "gdsc_gpu_cx"; + reg = <0x5066004 0x4>, + <0x5066008 0x4>; + reg-names = "base", "hw_ctrl_addr"; + qcom,no-status-check-on-disable; + qcom,gds-timeout = <500>; + status = "disabled"; + }; + + gdsc_gpu_gx: qcom,gdsc@5066094 { + compatible = "qcom,gdsc"; + regulator-name = "gdsc_gpu_gx"; + reg = <0x5066094 0x4>, + <0x5065130 0x4>, + <0x5066090 0x4>; + reg-names = "base", "domain_addr", "sw_reset"; + qcom,retain-periph; + qcom,reset-aon-logic; + status = "disabled"; + }; +}; diff -Nruw linux-4.4.115-fbx/arch/arm/boot/dts/qcom./msm-pm8005.dtsi linux-4.4.115-fbx/arch/arm/boot/dts/qcom/msm-pm8005.dtsi --- linux-4.4.115-fbx/arch/arm/boot/dts/qcom./msm-pm8005.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ linux-4.4.115-fbx/arch/arm/boot/dts/qcom/msm-pm8005.dtsi 2019-01-22 16:16:21.179225361 +0100 @@ -0,0 +1,103 @@ +/* Copyright (c) 2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include + +&spmi_bus { + qcom,pm8005@4 { + compatible = "qcom,spmi-pmic"; + reg = <0x4 SPMI_USID>; + #address-cells = <2>; + #size-cells = <0>; + + pm8005_revid: qcom,revid@100 { + compatible = "qcom,qpnp-revid"; + reg = <0x100 0x100>; + }; + + qcom,temp-alarm@2400 { + compatible = "qcom,qpnp-temp-alarm"; + reg = <0x2400 0x100>; + interrupts = <0x4 0x24 0x0 IRQ_TYPE_EDGE_RISING>; + label = "pm8005_tz"; + }; + + pm8005_gpios: gpios { + compatible = "qcom,qpnp-pin"; + gpio-controller; + #gpio-cells = <2>; + #address-cells = <1>; + #size-cells = <1>; + label = "pm8005-gpio"; + + gpio@c000 { + reg = <0xc000 0x100>; + qcom,pin-num = <1>; + status = "disabled"; + }; + + gpio@c100 { + reg = <0xc100 0x100>; + qcom,pin-num = <2>; + status = "disabled"; + }; + + gpio@c200 { + reg = <0xc200 0x100>; + qcom,pin-num = <3>; + status = "disabled"; + }; + + gpio@c300 { + reg = <0xc300 0x100>; + qcom,pin-num = <4>; + status = "disabled"; + }; + }; + }; + + qcom,pm8005@5 { + compatible ="qcom,spmi-pmic"; + reg = <0x5 SPMI_USID>; + #address-cells = <2>; + #size-cells = <0>; + + regulator@1400 { + compatible = "qcom,qpnp-regulator"; + reg = <0x1400 0x100>; + regulator-name = "pm8005_s1"; + status = "disabled"; + }; + + regulator@1700 { + compatible = "qcom,qpnp-regulator"; + reg = <0x1700 0x100>; + regulator-name = "pm8005_s2"; + status = "disabled"; + }; + + regulator@1a00 { + compatible = "qcom,qpnp-regulator"; + reg = <0x1a00 0x100>; + regulator-name = "pm8005_s3"; + status = "disabled"; + }; + + regulator@1d00 { + compatible = "qcom,qpnp-regulator"; + reg = <0x1d00 0x100>; + regulator-name = "pm8005_s4"; + status = "disabled"; + }; + }; +}; diff -Nruw linux-4.4.115-fbx/arch/arm/boot/dts/qcom./msm-pm8998.dtsi linux-4.4.115-fbx/arch/arm/boot/dts/qcom/msm-pm8998.dtsi --- linux-4.4.115-fbx/arch/arm/boot/dts/qcom./msm-pm8998.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ linux-4.4.115-fbx/arch/arm/boot/dts/qcom/msm-pm8998.dtsi 2019-01-22 16:16:21.179225361 +0100 @@ -0,0 +1,328 @@ +/* Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include + +&spmi_bus { + qcom,pm8998@0 { + compatible ="qcom,spmi-pmic"; + reg = <0x0 SPMI_USID>; + #address-cells = <2>; + #size-cells = <0>; + + pm8998_revid: qcom,revid@100 { + compatible = "qcom,qpnp-revid"; + reg = <0x100 0x100>; + }; + + qcom,power-on@800 { + compatible = "qcom,qpnp-power-on"; + reg = <0x800 0x100>; + interrupts = <0x0 0x8 0x0 IRQ_TYPE_NONE>, + <0x0 0x8 0x1 IRQ_TYPE_NONE>, + <0x0 0x8 0x4 IRQ_TYPE_NONE>, + <0x0 0x8 0x5 IRQ_TYPE_NONE>; + interrupt-names = "kpdpwr", "resin", + "resin-bark", "kpdpwr-resin-bark"; + qcom,pon-dbc-delay = <15625>; + qcom,system-reset; + qcom,store-hard-reset-reason; + + qcom,pon_1 { + qcom,pon-type = <0>; + qcom,pull-up = <1>; + linux,code = <116>; + }; + + qcom,pon_2 { + qcom,pon-type = <1>; + qcom,pull-up = <1>; + linux,code = <114>; + }; + + qcom,pon_3 { + qcom,pon-type = <3>; + qcom,support-reset = <1>; + qcom,pull-up = <1>; + qcom,s1-timer = <6720>; + qcom,s2-timer = <2000>; + qcom,s2-type = ; + qcom,use-bark; + }; + }; + + qcom,temp-alarm@2400 { + compatible = "qcom,qpnp-temp-alarm"; + reg = <0x2400 0x100>; + interrupts = <0x0 0x24 0x0 IRQ_TYPE_EDGE_RISING>; + label = "pm8998_tz"; + qcom,channel-num = <6>; + qcom,temp_alarm-vadc = <&pm8998_vadc>; + }; + + pm8998_gpios: gpios { + compatible = "qcom,qpnp-pin"; + gpio-controller; + #gpio-cells = <2>; + #address-cells = <1>; + #size-cells = <1>; + label = "pm8998-gpio"; + + gpio@c000 { + reg = <0xc000 0x100>; + qcom,pin-num = <1>; + status = "disabled"; + }; + + gpio@c100 { + reg = <0xc100 0x100>; + qcom,pin-num = <2>; + status = "disabled"; + }; + + gpio@c200 { + reg = <0xc200 0x100>; + qcom,pin-num = <3>; + status = "disabled"; + }; + + gpio@c300 { + reg = <0xc300 0x100>; + qcom,pin-num = <4>; + status = "disabled"; + }; + + gpio@c400 { + reg = <0xc400 0x100>; + qcom,pin-num = <5>; + status = "disabled"; + }; + + gpio@c500 { + reg = <0xc500 0x100>; + qcom,pin-num = <6>; + status = "disabled"; + }; + + gpio@c600 { + reg = <0xc600 0x100>; + qcom,pin-num = <7>; + status = "disabled"; + }; + + gpio@c700 { + reg = <0xc700 0x100>; + qcom,pin-num = <8>; + status = "disabled"; + }; + + gpio@c800 { + reg = <0xc800 0x100>; + qcom,pin-num = <9>; + status = "disabled"; + }; + + gpio@c900 { + reg = <0xc900 0x100>; + qcom,pin-num = <10>; + status = "disabled"; + }; + + gpio@ca00 { + reg = <0xca00 0x100>; + qcom,pin-num = <11>; + status = "disabled"; + }; + + gpio@cb00 { + reg = <0xcb00 0x100>; + qcom,pin-num = <12>; + status = "disabled"; + }; + + gpio@cc00 { + reg = <0xcc00 0x100>; + qcom,pin-num = <13>; + status = "disabled"; + }; + + gpio@cd00 { + reg = <0xcd00 0x100>; + qcom,pin-num = <14>; + status = "disabled"; + }; + + gpio@ce00 { + reg = <0xce00 0x100>; + qcom,pin-num = <15>; + status = "disabled"; + }; + + gpio@cf00 { + reg = <0xcf00 0x100>; + qcom,pin-num = <16>; + status = "disabled"; + }; + + gpio@d000 { + reg = <0xd000 0x100>; + qcom,pin-num = <17>; + status = "disabled"; + }; + + gpio@d100 { + reg = <0xd100 0x100>; + qcom,pin-num = <18>; + status = "disabled"; + }; + + gpio@d200 { + reg = <0xd200 0x100>; + qcom,pin-num = <19>; + status = "disabled"; + }; + + gpio@d300 { + reg = <0xd300 0x100>; + qcom,pin-num = <20>; + status = "disabled"; + }; + + gpio@d400 { + reg = <0xd400 0x100>; + qcom,pin-num = <21>; + status = "disabled"; + }; + + gpio@d500 { + reg = <0xd500 0x100>; + qcom,pin-num = <22>; + status = "disabled"; + }; + + gpio@d600 { + reg = <0xd600 0x100>; + qcom,pin-num = <23>; + status = "disabled"; + }; + + gpio@d700 { + reg = <0xd700 0x100>; + qcom,pin-num = <24>; + status = "disabled"; + }; + + gpio@d800 { + reg = <0xd800 0x100>; + qcom,pin-num = <25>; + status = "disabled"; + }; + + gpio@d900 { + reg = <0xd900 0x100>; + qcom,pin-num = <26>; + status = "disabled"; + }; + }; + + pm8998_coincell: qcom,coincell@2800 { + compatible = "qcom,qpnp-coincell"; + reg = <0x2800 0x100>; + }; + + pm8998_rtc: qcom,pm8998_rtc { + compatible = "qcom,qpnp-rtc"; + #address-cells = <1>; + #size-cells = <1>; + qcom,qpnp-rtc-write = <0>; + qcom,qpnp-rtc-alarm-pwrup = <0>; + + qcom,pm8998_rtc_rw@6000 { + reg = <0x6000 0x100>; + }; + qcom,pm8998_rtc_alarm@6100 { + reg = <0x6100 0x100>; + interrupts = <0x0 0x61 0x1 IRQ_TYPE_NONE>; + }; + }; + + pm8998_vadc: vadc@3100 { + compatible = "qcom,qpnp-vadc-hc"; + reg = <0x3100 0x100>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "eoc-int-en-set"; + qcom,adc-bit-resolution = <15>; + qcom,adc-vdd-reference = <1875>; + + chan@6 { + label = "die_temp"; + reg = <6>; + qcom,decimation = <2>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "absolute"; + qcom,scale-function = <3>; + qcom,hw-settle-time = <0>; + qcom,fast-avg-setup = <0>; + qcom,cal-val = <0>; + }; + + chan@0 { + label = "ref_gnd"; + reg = <0>; + qcom,decimation = <2>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "absolute"; + qcom,scale-function = <0>; + qcom,hw-settle-time = <0>; + qcom,fast-avg-setup = <0>; + qcom,cal-val = <0>; + }; + + chan@1 { + label = "ref_1250v"; + reg = <1>; + qcom,decimation = <2>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "absolute"; + qcom,scale-function = <0>; + qcom,hw-settle-time = <0>; + qcom,fast-avg-setup = <0>; + qcom,cal-val = <0>; + }; + }; + + pm8998_adc_tm: vadc@3400 { + compatible = "qcom,qpnp-adc-tm-hc"; + reg = <0x3400 0x100>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0x0 0x34 0x0 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "eoc-int-en-set"; + qcom,adc-bit-resolution = <15>; + qcom,adc-vdd-reference = <1875>; + qcom,adc_tm-vadc = <&pm8998_vadc>; + qcom,decimation = <0>; + qcom,fast-avg-setup = <0>; + }; + }; + + qcom,pm8998@1 { + compatible ="qcom,spmi-pmic"; + reg = <0x1 SPMI_USID>; + #address-cells = <2>; + #size-cells = <0>; + }; +}; diff -Nruw linux-4.4.115-fbx/arch/arm/boot/dts/qcom./msm-pm8998-rpm-regulator.dtsi linux-4.4.115-fbx/arch/arm/boot/dts/qcom/msm-pm8998-rpm-regulator.dtsi --- linux-4.4.115-fbx/arch/arm/boot/dts/qcom./msm-pm8998-rpm-regulator.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ linux-4.4.115-fbx/arch/arm/boot/dts/qcom/msm-pm8998-rpm-regulator.dtsi 2019-01-22 16:16:21.179225361 +0100 @@ -0,0 +1,600 @@ +/* Copyright (c) 2015-2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&rpm_bus { + /* PM8998 S1 + S6 = VDD_CX supply */ + rpm-regulator-smpa1 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "rwcx"; + qcom,resource-id = <0>; + qcom,regulator-type = <1>; + status = "disabled"; + + regulator-s1 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm8998_s1"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-smpa2 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "smpa"; + qcom,resource-id = <2>; + qcom,regulator-type = <1>; + status = "disabled"; + + regulator-s2 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm8998_s2"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-smpa3 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "smpa"; + qcom,resource-id = <3>; + qcom,regulator-type = <1>; + status = "disabled"; + + regulator-s3 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm8998_s3"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-smpa4 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "smpa"; + qcom,resource-id = <4>; + qcom,regulator-type = <1>; + status = "disabled"; + + regulator-s4 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm8998_s4"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-smpa5 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "smpa"; + qcom,resource-id = <5>; + qcom,regulator-type = <1>; + status = "disabled"; + + regulator-s5 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm8998_s5"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-smpa7 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "smpa"; + qcom,resource-id = <7>; + qcom,regulator-type = <1>; + status = "disabled"; + + regulator-s7 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm8998_s7"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-smpa8 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "smpa"; + qcom,resource-id = <8>; + qcom,regulator-type = <1>; + status = "disabled"; + + regulator-s8 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm8998_s8"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + /* PM8998 S9 = VDD_MX supply */ + rpm-regulator-smpa9 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "rwmx"; + qcom,resource-id = <0>; + qcom,regulator-type = <1>; + status = "disabled"; + + regulator-s9 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm8998_s9"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa1 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <1>; + qcom,regulator-type = <0>; + status = "disabled"; + + regulator-l1 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm8998_l1"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa2 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <2>; + qcom,regulator-type = <0>; + status = "disabled"; + + regulator-l2 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm8998_l2"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa3 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <3>; + qcom,regulator-type = <0>; + status = "disabled"; + + regulator-l3 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm8998_l3"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa4 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "rwsm"; + qcom,resource-id = <0>; + qcom,regulator-type = <0>; + status = "disabled"; + + regulator-l4 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm8998_l4"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa5 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <5>; + qcom,regulator-type = <0>; + status = "disabled"; + + regulator-l5 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm8998_l5"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa6 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <6>; + qcom,regulator-type = <0>; + status = "disabled"; + + regulator-l6 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm8998_l6"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa7 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <7>; + qcom,regulator-type = <0>; + status = "disabled"; + + regulator-l7 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm8998_l7"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa8 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <8>; + qcom,regulator-type = <0>; + status = "disabled"; + + regulator-l8 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm8998_l8"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa9 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <9>; + qcom,regulator-type = <0>; + status = "disabled"; + + regulator-l9 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm8998_l9"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa10 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <10>; + qcom,regulator-type = <0>; + status = "disabled"; + + regulator-l10 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm8998_l10"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa11 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <11>; + qcom,regulator-type = <0>; + status = "disabled"; + + regulator-l11 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm8998_l11"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa12 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <12>; + qcom,regulator-type = <0>; + status = "disabled"; + + regulator-l12 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm8998_l12"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa13 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <13>; + qcom,regulator-type = <0>; + status = "disabled"; + + regulator-l13 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm8998_l13"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa14 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <14>; + qcom,regulator-type = <0>; + status = "disabled"; + + regulator-l14 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm8998_l14"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa15 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <15>; + qcom,regulator-type = <0>; + status = "disabled"; + + regulator-l15 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm8998_l15"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa16 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <16>; + qcom,regulator-type = <0>; + status = "disabled"; + + regulator-l16 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm8998_l16"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa17 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <17>; + qcom,regulator-type = <0>; + status = "disabled"; + + regulator-l17 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm8998_l17"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa18 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <18>; + qcom,regulator-type = <0>; + status = "disabled"; + + regulator-l18 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm8998_l18"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa19 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <19>; + qcom,regulator-type = <0>; + status = "disabled"; + + regulator-l19 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm8998_l19"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa20 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <20>; + qcom,regulator-type = <0>; + status = "disabled"; + + regulator-l20 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm8998_l20"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa21 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <21>; + qcom,regulator-type = <0>; + status = "disabled"; + + regulator-l21 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm8998_l21"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa22 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <22>; + qcom,regulator-type = <0>; + status = "disabled"; + + regulator-l22 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm8998_l22"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa23 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <23>; + qcom,regulator-type = <0>; + status = "disabled"; + + regulator-l23 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm8998_l23"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa24 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <24>; + qcom,regulator-type = <0>; + status = "disabled"; + + regulator-l24 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm8998_l24"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa25 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <25>; + qcom,regulator-type = <0>; + status = "disabled"; + + regulator-l25 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm8998_l25"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa26 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <26>; + qcom,regulator-type = <0>; + status = "disabled"; + + regulator-l26 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm8998_l26"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa27 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "rwsc"; + qcom,resource-id = <0>; + qcom,regulator-type = <0>; + status = "disabled"; + + regulator-l27 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm8998_l27"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa28 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <28>; + qcom,regulator-type = <0>; + status = "disabled"; + + regulator-l28 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm8998_l28"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-vsa1 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "vsa"; + qcom,resource-id = <1>; + qcom,regulator-type = <2>; + status = "disabled"; + + regulator-lvs1 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm8998_lvs1"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-vsa2 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "vsa"; + qcom,resource-id = <2>; + qcom,regulator-type = <2>; + status = "disabled"; + + regulator-lvs2 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm8998_lvs2"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-bobb { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "bobb"; + qcom,resource-id = <1>; + qcom,regulator-type = <4>; + status = "disabled"; + + regulator-bob { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm8998_bob"; + qcom,set = <3>; + status = "disabled"; + }; + }; +}; diff -Nruw linux-4.4.115-fbx/arch/arm/boot/dts/qcom./msm-pmi8998.dtsi linux-4.4.115-fbx/arch/arm/boot/dts/qcom/msm-pmi8998.dtsi --- linux-4.4.115-fbx/arch/arm/boot/dts/qcom./msm-pmi8998.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ linux-4.4.115-fbx/arch/arm/boot/dts/qcom/msm-pmi8998.dtsi 2019-01-22 16:16:21.179225361 +0100 @@ -0,0 +1,777 @@ +/* Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include + +&spmi_bus { + qcom,pmi8998@2 { + compatible = "qcom,spmi-pmic"; + reg = <0x2 SPMI_USID>; + #address-cells = <2>; + #size-cells = <0>; + + pmi8998_revid: qcom,revid@100 { + compatible = "qcom,qpnp-revid"; + reg = <0x100 0x100>; + qcom,fab-id-valid; + }; + + qcom,power-on@800 { + compatible = "qcom,qpnp-power-on"; + reg = <0x800 0x100>; + }; + + pmi8998_misc: qcom,misc@900 { + compatible = "qcom,qpnp-misc"; + reg = <0x900 0x100>; + }; + + qcom,temp-alarm@2400 { + compatible = "qcom,qpnp-temp-alarm"; + reg = <0x2400 0x100>; + interrupts = <0x2 0x24 0x0 IRQ_TYPE_EDGE_RISING>; + label = "pmi8998_tz"; + }; + + pmi8998_gpios: gpios { + compatible = "qcom,qpnp-pin"; + gpio-controller; + #gpio-cells = <2>; + #address-cells = <1>; + #size-cells = <1>; + label = "pmi8998-gpio"; + + gpio@c000 { + reg = <0xc000 0x100>; + qcom,pin-num = <1>; + status = "disabled"; + }; + + gpio@c100 { + reg = <0xc100 0x100>; + qcom,pin-num = <2>; + status = "disabled"; + }; + + gpio@c200 { + reg = <0xc200 0x100>; + qcom,pin-num = <3>; + status = "disabled"; + }; + + gpio@c300 { + reg = <0xc300 0x100>; + qcom,pin-num = <4>; + status = "disabled"; + }; + + gpio@c400 { + reg = <0xc400 0x100>; + qcom,pin-num = <5>; + status = "disabled"; + }; + + gpio@c500 { + reg = <0xc500 0x100>; + qcom,pin-num = <6>; + status = "disabled"; + }; + + gpio@c600 { + reg = <0xc600 0x100>; + qcom,pin-num = <7>; + status = "disabled"; + }; + + gpio@c700 { + reg = <0xc700 0x100>; + qcom,pin-num = <8>; + status = "disabled"; + }; + + gpio@c800 { + reg = <0xc800 0x100>; + qcom,pin-num = <9>; + status = "disabled"; + }; + + gpio@c900 { + reg = <0xc900 0x100>; + qcom,pin-num = <10>; + status = "disabled"; + }; + + gpio@ca00 { + reg = <0xca00 0x100>; + qcom,pin-num = <11>; + status = "disabled"; + }; + + gpio@cb00 { + reg = <0xcb00 0x100>; + qcom,pin-num = <12>; + status = "disabled"; + }; + + gpio@cc00 { + reg = <0xcc00 0x100>; + qcom,pin-num = <13>; + status = "disabled"; + }; + + gpio@cd00 { + reg = <0xcd00 0x100>; + qcom,pin-num = <14>; + status = "disabled"; + }; + }; + + qcom,qpnp-qnovo@1500 { + compatible = "qcom,qpnp-qnovo"; + reg = <0x1500 0x100>; + interrupts = <0x2 0x15 0x0 IRQ_TYPE_NONE>; + interrupt-names = "ptrain-done"; + qcom,pmic-revid = <&pmi8998_revid>; + }; + + pmi8998_charger: qcom,qpnp-smb2 { + compatible = "qcom,qpnp-smb2"; + #address-cells = <1>; + #size-cells = <1>; + + qcom,pmic-revid = <&pmi8998_revid>; + + io-channels = <&pmi8998_rradc 8>, + <&pmi8998_rradc 10>, + <&pmi8998_rradc 3>, + <&pmi8998_rradc 4>; + io-channel-names = "charger_temp", + "charger_temp_max", + "usbin_i", + "usbin_v"; + + qcom,boost-threshold-ua = <100000>; + qcom,wipower-max-uw = <5000000>; + dpdm-supply = <&qusb_phy0>; + + qcom,thermal-mitigation + = <3000000 1500000 1000000 500000>; + + qcom,chgr@1000 { + reg = <0x1000 0x100>; + interrupts = + <0x2 0x10 0x0 IRQ_TYPE_EDGE_RISING>, + <0x2 0x10 0x1 IRQ_TYPE_EDGE_RISING>, + <0x2 0x10 0x2 IRQ_TYPE_EDGE_RISING>, + <0x2 0x10 0x3 IRQ_TYPE_EDGE_RISING>, + <0x2 0x10 0x4 IRQ_TYPE_EDGE_RISING>; + + interrupt-names = "chg-error", + "chg-state-change", + "step-chg-state-change", + "step-chg-soc-update-fail", + "step-chg-soc-update-request"; + }; + + qcom,otg@1100 { + reg = <0x1100 0x100>; + interrupts = <0x2 0x11 0x0 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x11 0x1 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x11 0x2 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x11 0x3 IRQ_TYPE_EDGE_BOTH>; + + interrupt-names = "otg-fail", + "otg-overcurrent", + "otg-oc-dis-sw-sts", + "testmode-change-detect"; + }; + + qcom,bat-if@1200 { + reg = <0x1200 0x100>; + interrupts = + <0x2 0x12 0x0 IRQ_TYPE_EDGE_RISING>, + <0x2 0x12 0x1 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x12 0x2 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x12 0x3 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x12 0x4 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x12 0x5 IRQ_TYPE_EDGE_BOTH>; + + interrupt-names = "bat-temp", + "bat-ocp", + "bat-ov", + "bat-low", + "bat-therm-or-id-missing", + "bat-terminal-missing"; + }; + + qcom,usb-chgpth@1300 { + reg = <0x1300 0x100>; + interrupts = + <0x2 0x13 0x0 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x13 0x1 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x13 0x2 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x13 0x3 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x13 0x4 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x13 0x5 IRQ_TYPE_EDGE_RISING>, + <0x2 0x13 0x6 IRQ_TYPE_EDGE_RISING>, + <0x2 0x13 0x7 IRQ_TYPE_EDGE_RISING>; + + interrupt-names = "usbin-collapse", + "usbin-lt-3p6v", + "usbin-uv", + "usbin-ov", + "usbin-plugin", + "usbin-src-change", + "usbin-icl-change", + "type-c-change"; + }; + + qcom,dc-chgpth@1400 { + reg = <0x1400 0x100>; + interrupts = + <0x2 0x14 0x0 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x14 0x1 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x14 0x2 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x14 0x3 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x14 0x4 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x14 0x5 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x14 0x6 IRQ_TYPE_EDGE_RISING>; + + interrupt-names = "dcin-collapse", + "dcin-lt-3p6v", + "dcin-uv", + "dcin-ov", + "dcin-plugin", + "div2-en-dg", + "dcin-icl-change"; + }; + + qcom,chgr-misc@1600 { + reg = <0x1600 0x100>; + interrupts = + <0x2 0x16 0x0 IRQ_TYPE_EDGE_RISING>, + <0x2 0x16 0x1 IRQ_TYPE_EDGE_RISING>, + <0x2 0x16 0x2 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x16 0x3 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x16 0x4 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x16 0x5 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x16 0x6 IRQ_TYPE_EDGE_FALLING>, + <0x2 0x16 0x7 IRQ_TYPE_EDGE_BOTH>; + + interrupt-names = "wdog-snarl", + "wdog-bark", + "aicl-fail", + "aicl-done", + "high-duty-cycle", + "input-current-limiting", + "temperature-change", + "switcher-power-ok"; + }; + }; + + pmi8998_pdphy: qcom,usb-pdphy@1700 { + compatible = "qcom,qpnp-pdphy"; + reg = <0x1700 0x100>; + vdd-pdphy-supply = <&pm8998_l24>; + vbus-supply = <&smb2_vbus>; + vconn-supply = <&smb2_vconn>; + interrupts = <0x2 0x17 0x0 IRQ_TYPE_EDGE_RISING>, + <0x2 0x17 0x1 IRQ_TYPE_EDGE_RISING>, + <0x2 0x17 0x2 IRQ_TYPE_EDGE_RISING>, + <0x2 0x17 0x3 IRQ_TYPE_EDGE_RISING>, + <0x2 0x17 0x4 IRQ_TYPE_EDGE_RISING>, + <0x2 0x17 0x5 IRQ_TYPE_EDGE_RISING>, + <0x2 0x17 0x6 IRQ_TYPE_EDGE_RISING>; + + interrupt-names = "sig-tx", + "sig-rx", + "msg-tx", + "msg-rx", + "msg-tx-failed", + "msg-tx-discarded", + "msg-rx-discarded"; + + qcom,default-sink-caps = <5000 3000>, /* 5V @ 3A */ + <9000 3000>, /* 9V @ 3A */ + <12000 2250>; /* 12V @ 2.25A */ + }; + + bcl@4200 { + compatible = "qcom,msm-bcl-lmh"; + reg = <0x4200 0xff>, + <0x4300 0xff>; + reg-names = "fg_user_adc", + "fg_lmh"; + interrupts = <0x2 0x42 0x0 IRQ_TYPE_NONE>, + <0x2 0x42 0x2 IRQ_TYPE_NONE>; + interrupt-names = "bcl-high-ibat-int", + "bcl-low-vbat-int"; + qcom,vbat-polling-delay-ms = <100>; + qcom,ibat-polling-delay-ms = <100>; + }; + + pmi8998_rradc: rradc@4500 { + compatible = "qcom,rradc"; + reg = <0x4500 0x100>; + #address-cells = <1>; + #size-cells = <0>; + #io-channel-cells = <1>; + qcom,pmic-revid = <&pmi8998_revid>; + }; + + pmi8998_fg: qpnp,fg { + compatible = "qcom,fg-gen3"; + #address-cells = <1>; + #size-cells = <1>; + qcom,pmic-revid = <&pmi8998_revid>; + io-channels = <&pmi8998_rradc 0>; + io-channel-names = "rradc_batt_id"; + qcom,rradc-base = <0x4500>; + qcom,fg-esr-timer-awake = <96 96>; + qcom,fg-esr-timer-asleep = <256 256>; + qcom,fg-esr-timer-charging = <0 96>; + qcom,cycle-counter-en; + status = "okay"; + + qcom,fg-batt-soc@4000 { + status = "okay"; + reg = <0x4000 0x100>; + interrupts = <0x2 0x40 0x0 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x40 0x1 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x40 0x2 + IRQ_TYPE_EDGE_RISING>, + <0x2 0x40 0x3 + IRQ_TYPE_EDGE_RISING>, + <0x2 0x40 0x4 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x40 0x5 + IRQ_TYPE_EDGE_RISING>, + <0x2 0x40 0x6 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x40 0x7 IRQ_TYPE_EDGE_BOTH>; + interrupt-names = "soc-update", + "soc-ready", + "bsoc-delta", + "msoc-delta", + "msoc-low", + "msoc-empty", + "msoc-high", + "msoc-full"; + }; + + qcom,fg-batt-info@4100 { + status = "okay"; + reg = <0x4100 0x100>; + interrupts = <0x2 0x41 0x0 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x41 0x1 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x41 0x2 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x41 0x3 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x41 0x6 IRQ_TYPE_EDGE_BOTH>; + interrupt-names = "vbatt-pred-delta", + "vbatt-low", + "esr-delta", + "batt-missing", + "batt-temp-delta"; + }; + + qcom,fg-memif@4400 { + status = "okay"; + reg = <0x4400 0x100>; + interrupts = <0x2 0x44 0x0 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x44 0x1 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x44 0x2 IRQ_TYPE_EDGE_BOTH>; + interrupt-names = "ima-rdy", + "mem-xcp", + "dma-grant"; + }; + }; + }; + + qcom,pmi8998@3 { + compatible ="qcom,spmi-pmic"; + reg = <0x3 SPMI_USID>; + #address-cells = <2>; + #size-cells = <0>; + + pmi8998_pwm_1: pwm@b100 { + compatible = "qcom,qpnp-pwm"; + reg = <0xb100 0x100>, + <0xb042 0x7e>; + reg-names = "qpnp-lpg-channel-base", + "qpnp-lpg-lut-base"; + qcom,lpg-lut-size = <0x7e>; + qcom,channel-id = <1>; + qcom,supported-sizes = <6>, <9>; + qcom,ramp-index = <0>; + #pwm-cells = <2>; + status = "disabled"; + }; + + pmi8998_pwm_2: pwm@b200 { + compatible = "qcom,qpnp-pwm"; + reg = <0xb200 0x100>, + <0xb042 0x7e>; + reg-names = "qpnp-lpg-channel-base", + "qpnp-lpg-lut-base"; + qcom,lpg-lut-size = <0x7e>; + qcom,channel-id = <2>; + qcom,supported-sizes = <6>, <9>; + qcom,ramp-index = <1>; + #pwm-cells = <2>; + status = "disabled"; + }; + + pmi8998_pwm_3: pwm@b300 { + compatible = "qcom,qpnp-pwm"; + reg = <0xb300 0x100>, + <0xb042 0x7e>; + reg-names = "qpnp-lpg-channel-base", + "qpnp-lpg-lut-base"; + qcom,lpg-lut-size = <0x7e>; + qcom,channel-id = <3>; + qcom,supported-sizes = <6>, <9>; + qcom,ramp-index = <2>; + #pwm-cells = <2>; + }; + + pmi8998_pwm_4: pwm@b400 { + compatible = "qcom,qpnp-pwm"; + reg = <0xb400 0x100>, + <0xb042 0x7e>; + reg-names = "qpnp-lpg-channel-base", + "qpnp-lpg-lut-base"; + qcom,lpg-lut-size = <0x7e>; + qcom,channel-id = <4>; + qcom,supported-sizes = <6>, <9>; + qcom,ramp-index = <3>; + #pwm-cells = <2>; + }; + + pmi8998_pwm_5: pwm@b500 { + compatible = "qcom,qpnp-pwm"; + reg = <0xb500 0x100>, + <0xb042 0x7e>; + reg-names = "qpnp-lpg-channel-base", + "qpnp-lpg-lut-base"; + qcom,lpg-lut-size = <0x7e>; + qcom,channel-id = <5>; + qcom,supported-sizes = <6>, <9>; + qcom,ramp-index = <4>; + #pwm-cells = <2>; + }; + + pmi8998_pwm_6: pwm@b600 { + compatible = "qcom,qpnp-pwm"; + reg = <0xb600 0x100>, + <0xb042 0x7e>; + reg-names = "qpnp-lpg-channel-base", + "qpnp-lpg-lut-base"; + qcom,lpg-lut-size = <0x7e>; + qcom,channel-id = <6>; + qcom,supported-sizes = <6>, <9>; + qcom,ramp-index = <5>; + #pwm-cells = <2>; + status = "disabled"; + }; + + qcom,leds@d000 { + compatible = "qcom,leds-qpnp"; + reg = <0xd000 0x100>; + label = "rgb"; + status = "okay"; + + red_led: qcom,rgb_0 { + label = "rgb"; + qcom,id = <3>; + qcom,mode = "pwm"; + pwms = <&pmi8998_pwm_5 0 0>; + qcom,pwm-us = <1000>; + qcom,max-current = <12>; + qcom,default-state = "off"; + linux,name = "red"; + linux,default-trigger = + "battery-charging"; + }; + + green_led: qcom,rgb_1 { + label = "rgb"; + qcom,id = <4>; + qcom,mode = "pwm"; + pwms = <&pmi8998_pwm_4 0 0>; + qcom,pwm-us = <1000>; + qcom,max-current = <12>; + qcom,default-state = "off"; + linux,name = "green"; + linux,default-trigger = "battery-full"; + }; + + blue_led: qcom,rgb_2 { + label = "rgb"; + qcom,id = <5>; + qcom,mode = "pwm"; + pwms = <&pmi8998_pwm_3 0 0>; + qcom,pwm-us = <1000>; + qcom,max-current = <12>; + qcom,default-state = "off"; + linux,name = "blue"; + linux,default-trigger = "boot-indication"; + }; + }; + + labibb: qpnp-labibb-regulator { + compatible = "qcom,qpnp-labibb-regulator"; + #address-cells = <1>; + #size-cells = <1>; + qcom,pmic-revid = <&pmi8998_revid>; + status = "disabled"; + + ibb_regulator: qcom,ibb@dc00 { + reg = <0xdc00 0x100>; + reg-names = "ibb_reg"; + regulator-name = "ibb_reg"; + + regulator-min-microvolt = <4600000>; + regulator-max-microvolt = <6000000>; + + interrupts = <0x3 0xdc 0x2 + IRQ_TYPE_EDGE_RISING>; + interrupt-names = "ibb-sc-err"; + + qcom,qpnp-ibb-min-voltage = <1400000>; + qcom,qpnp-ibb-step-size = <100000>; + qcom,qpnp-ibb-slew-rate = <2000000>; + qcom,qpnp-ibb-use-default-voltage; + qcom,qpnp-ibb-init-voltage = <5500000>; + qcom,qpnp-ibb-init-amoled-voltage = <4000000>; + qcom,qpnp-ibb-init-lcd-voltage = <5500000>; + + qcom,qpnp-ibb-soft-start = <1000>; + + qcom,qpnp-ibb-lab-pwrup-delay = <8000>; + qcom,qpnp-ibb-lab-pwrdn-delay = <8000>; + qcom,qpnp-ibb-en-discharge; + + qcom,qpnp-ibb-full-pull-down; + qcom,qpnp-ibb-pull-down-enable; + qcom,qpnp-ibb-switching-clock-frequency = + <1480>; + qcom,qpnp-ibb-limit-maximum-current = <1550>; + qcom,qpnp-ibb-debounce-cycle = <16>; + qcom,qpnp-ibb-limit-max-current-enable; + qcom,qpnp-ibb-ps-enable; + }; + + lab_regulator: qcom,lab@de00 { + reg = <0xde00 0x100>; + reg-names = "lab"; + regulator-name = "lab_reg"; + + regulator-min-microvolt = <4600000>; + regulator-max-microvolt = <6000000>; + + interrupts = <0x3 0xde 0x0 + IRQ_TYPE_EDGE_RISING>, + <0x3 0xde 0x1 + IRQ_TYPE_EDGE_RISING>; + interrupt-names = "lab-vreg-ok", "lab-sc-err"; + + qcom,qpnp-lab-min-voltage = <4600000>; + qcom,qpnp-lab-step-size = <100000>; + qcom,qpnp-lab-slew-rate = <5000>; + qcom,qpnp-lab-use-default-voltage; + qcom,qpnp-lab-init-voltage = <5500000>; + qcom,qpnp-lab-init-amoled-voltage = <4600000>; + qcom,qpnp-lab-init-lcd-voltage = <5500000>; + + qcom,qpnp-lab-soft-start = <800>; + + qcom,qpnp-lab-full-pull-down; + qcom,qpnp-lab-pull-down-enable; + qcom,qpnp-lab-switching-clock-frequency = + <1600>; + qcom,qpnp-lab-limit-maximum-current = <1600>; + qcom,qpnp-lab-limit-max-current-enable; + qcom,qpnp-lab-ps-threshold = <70>; + qcom,qpnp-lab-ps-enable; + qcom,qpnp-lab-nfet-size = <100>; + qcom,qpnp-lab-pfet-size = <100>; + qcom,qpnp-lab-max-precharge-time = <500>; + }; + }; + + pmi8998_wled: qcom,leds@d800 { + compatible = "qcom,qpnp-wled"; + reg = <0xd800 0x100>, + <0xd900 0x100>; + reg-names = "qpnp-wled-ctrl-base", + "qpnp-wled-sink-base"; + interrupts = <0x3 0xd8 0x1 IRQ_TYPE_EDGE_RISING>, + <0x3 0xd8 0x2 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "ovp-irq", "sc-irq"; + linux,name = "wled"; + linux,default-trigger = "bkl-trigger"; + qcom,fdbk-output = "auto"; + qcom,vref-uv = <127500>; + qcom,switch-freq-khz = <800>; + qcom,ovp-mv = <29600>; + qcom,ilim-ma = <970>; + qcom,boost-duty-ns = <26>; + qcom,mod-freq-khz = <9600>; + qcom,dim-mode = "hybrid"; + qcom,hyb-thres = <625>; + qcom,sync-dly-us = <800>; + qcom,fs-curr-ua = <25000>; + qcom,cons-sync-write-delay-us = <1000>; + qcom,led-strings-list = [00 01 02 03]; + qcom,en-ext-pfet-sc-pro; + qcom,pmic-revid = <&pmi8998_revid>; + qcom,loop-auto-gm-en; + qcom,auto-calibration-enable; + status = "okay"; + }; + + pmi8998_haptics: qcom,haptic@c000 { + status = "disabled"; + compatible = "qcom,qpnp-haptic"; + reg = <0xc000 0x100>; + interrupts = <0x3 0xc0 0x0 IRQ_TYPE_EDGE_BOTH>, + <0x3 0xc0 0x1 IRQ_TYPE_EDGE_BOTH>; + interrupt-names = "sc-irq", "play-irq"; + qcom,pmic-revid = <&pmi8998_revid>; + qcom,pmic-misc = <&pmi8998_misc>; + qcom,misc-clk-trim-error-reg = <0xf3>; + qcom,actuator-type = "lra"; + qcom,play-mode = "direct"; + qcom,vmax-mv = <3200>; + qcom,ilim-ma = <800>; + qcom,wave-shape = "square"; + qcom,wave-play-rate-us = <6667>; + qcom,int-pwm-freq-khz = <505>; + qcom,sc-deb-cycles = <8>; + qcom,en-brake; + qcom,brake-pattern = [03 03 00 00]; + qcom,lra-high-z = "opt1"; + qcom,lra-auto-res-mode = "qwd"; + qcom,lra-res-cal-period = <4>; + qcom,correct-lra-drive-freq; + }; + + flash_led: qcom,leds@d300 { + compatible = "qcom,qpnp-flash-led-v2"; + status = "okay"; + reg = <0xd300 0x100>; + label = "flash"; + interrupts = <0x3 0xd3 0x0 IRQ_TYPE_EDGE_RISING>, + <0x3 0xd3 0x3 IRQ_TYPE_EDGE_RISING>, + <0x3 0xd3 0x4 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "led-fault-irq", + "all-ramp-down-done-irq", + "all-ramp-up-done-irq"; + qcom,hdrm-auto-mode; + qcom,short-circuit-det; + qcom,open-circuit-det; + qcom,vph-droop-det; + qcom,thermal-derate-en; + qcom,thermal-derate-current = <200 500 1000>; + qcom,isc-delay = <192>; + qcom,pmic-revid = <&pmi8998_revid>; + + pmi8998_flash0: qcom,flash_0 { + label = "flash"; + qcom,led-name = "led:flash_0"; + qcom,max-current = <1500>; + qcom,default-led-trigger = "flash0_trigger"; + qcom,id = <0>; + qcom,current-ma = <1000>; + qcom,duration-ms = <1280>; + qcom,ires-ua = <12500>; + qcom,hdrm-voltage-mv = <325>; + qcom,hdrm-vol-hi-lo-win-mv = <100>; + }; + + pmi8998_flash1: qcom,flash_1 { + label = "flash"; + qcom,led-name = "led:flash_1"; + qcom,max-current = <1500>; + qcom,default-led-trigger = "flash1_trigger"; + qcom,id = <1>; + qcom,current-ma = <1000>; + qcom,duration-ms = <1280>; + qcom,ires-ua = <12500>; + qcom,hdrm-voltage-mv = <325>; + qcom,hdrm-vol-hi-lo-win-mv = <100>; + }; + + pmi8998_flash2: qcom,flash_2 { + label = "flash"; + qcom,led-name = "led:flash_2"; + qcom,max-current = <750>; + qcom,default-led-trigger = "flash2_trigger"; + qcom,id = <2>; + qcom,current-ma = <500>; + qcom,duration-ms = <1280>; + qcom,ires-ua = <12500>; + qcom,hdrm-voltage-mv = <325>; + qcom,hdrm-vol-hi-lo-win-mv = <100>; + }; + + pmi8998_torch0: qcom,torch_0 { + label = "torch"; + qcom,led-name = "led:torch_0"; + qcom,max-current = <500>; + qcom,default-led-trigger = "torch0_trigger"; + qcom,id = <0>; + qcom,current-ma = <300>; + qcom,ires-ua = <12500>; + qcom,hdrm-voltage-mv = <325>; + qcom,hdrm-vol-hi-lo-win-mv = <100>; + }; + + pmi8998_torch1: qcom,torch_1 { + label = "torch"; + qcom,led-name = "led:torch_1"; + qcom,max-current = <500>; + qcom,default-led-trigger = "torch1_trigger"; + qcom,id = <1>; + qcom,current-ma = <300>; + qcom,ires-ua = <12500>; + qcom,hdrm-voltage-mv = <325>; + qcom,hdrm-vol-hi-lo-win-mv = <100>; + }; + + pmi8998_torch2: qcom,torch_2 { + label = "torch"; + qcom,led-name = "led:torch_2"; + qcom,max-current = <500>; + qcom,default-led-trigger = "torch2_trigger"; + qcom,id = <2>; + qcom,current-ma = <300>; + qcom,ires-ua = <12500>; + qcom,hdrm-voltage-mv = <325>; + qcom,hdrm-vol-hi-lo-win-mv = <100>; + }; + + pmi8998_switch0: qcom,led_switch_0 { + label = "switch"; + qcom,led-name = "led:switch_0"; + qcom,led-mask = <3>; + qcom,default-led-trigger = "switch0_trigger"; + }; + + pmi8998_switch1: qcom,led_switch_1 { + label = "switch"; + qcom,led-name = "led:switch_1"; + qcom,led-mask = <4>; + qcom,default-led-trigger = "switch1_trigger"; + }; + }; + }; +}; diff -Nruw linux-4.4.115-fbx/arch/arm/boot/dts/qcom./msm-rdbg.dtsi linux-4.4.115-fbx/arch/arm/boot/dts/qcom/msm-rdbg.dtsi --- linux-4.4.115-fbx/arch/arm/boot/dts/qcom./msm-rdbg.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ linux-4.4.115-fbx/arch/arm/boot/dts/qcom/msm-rdbg.dtsi 2019-01-22 16:16:21.179225361 +0100 @@ -0,0 +1,106 @@ +/* Copyright (c) 2015, 2017, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&soc { + smp2pgpio_rdbg_2_in: qcom,smp2pgpio-rdbg-2-in { + compatible = "qcom,smp2pgpio"; + qcom,entry-name = "rdbg"; + qcom,remote-pid = <2>; + qcom,is-inbound; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + qcom,smp2pgpio_client_rdbg_2_in { + compatible = "qcom,smp2pgpio_client_rdbg_2_in"; + gpios = <&smp2pgpio_rdbg_2_in 0 0>; + }; + + smp2pgpio_rdbg_2_out: qcom,smp2pgpio-rdbg-2-out { + compatible = "qcom,smp2pgpio"; + qcom,entry-name = "rdbg"; + qcom,remote-pid = <2>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + qcom,smp2pgpio_client_rdbg_2_out { + compatible = "qcom,smp2pgpio_client_rdbg_2_out"; + gpios = <&smp2pgpio_rdbg_2_out 0 0>; + }; + + smp2pgpio_rdbg_1_in: qcom,smp2pgpio-rdbg-1-in { + compatible = "qcom,smp2pgpio"; + qcom,entry-name = "rdbg"; + qcom,remote-pid = <1>; + qcom,is-inbound; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + qcom,smp2pgpio_client_rdbg_1_in { + compatible = "qcom,smp2pgpio_client_rdbg_1_in"; + gpios = <&smp2pgpio_rdbg_1_in 0 0>; + }; + + smp2pgpio_rdbg_1_out: qcom,smp2pgpio-rdbg-1-out { + compatible = "qcom,smp2pgpio"; + qcom,entry-name = "rdbg"; + qcom,remote-pid = <1>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + qcom,smp2pgpio_client_rdbg_1_out { + compatible = "qcom,smp2pgpio_client_rdbg_1_out"; + gpios = <&smp2pgpio_rdbg_1_out 0 0>; + }; + + smp2pgpio_rdbg_5_in: qcom,smp2pgpio-rdbg-5-in { + compatible = "qcom,smp2pgpio"; + qcom,entry-name = "rdbg"; + qcom,remote-pid = <5>; + qcom,is-inbound; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + qcom,smp2pgpio_client_rdbg_5_in { + compatible = "qcom,smp2pgpio_client_rdbg_5_in"; + gpios = <&smp2pgpio_rdbg_5_in 0 0>; + }; + + smp2pgpio_rdbg_5_out: qcom,smp2pgpio-rdbg-5-out { + compatible = "qcom,smp2pgpio"; + qcom,entry-name = "rdbg"; + qcom,remote-pid = <5>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + qcom,smp2pgpio_client_rdbg_5_out { + compatible = "qcom,smp2pgpio_client_rdbg_5_out"; + gpios = <&smp2pgpio_rdbg_5_out 0 0>; + }; +}; diff -Nruw linux-4.4.115-fbx/arch/arm/boot/dts/qcom./msm-smb138x.dtsi linux-4.4.115-fbx/arch/arm/boot/dts/qcom/msm-smb138x.dtsi --- linux-4.4.115-fbx/arch/arm/boot/dts/qcom./msm-smb138x.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ linux-4.4.115-fbx/arch/arm/boot/dts/qcom/msm-smb138x.dtsi 2019-01-22 16:16:21.179225361 +0100 @@ -0,0 +1,137 @@ +/* Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +&i2c_7 { + status = "okay"; + smb138x: qcom,smb138x@8 { + compatible = "qcom,i2c-pmic"; + reg = <0x8>; + #address-cells = <1>; + #size-cells = <0>; + interrupt-parent = <&spmi_bus>; + interrupts = <0x0 0xd1 0x0 IRQ_TYPE_LEVEL_LOW>; + interrupt_names = "smb138x"; + interrupt-controller; + #interrupt-cells = <3>; + qcom,periph-map = <0x10 0x11 0x12 0x13 0x14 0x16 0x36>; + + smb138x_revid: qcom,revid@100 { + compatible = "qcom,qpnp-revid"; + reg = <0x100 0x100>; + }; + + smb138x_tadc: qcom,tadc@3600 { + compatible = "qcom,tadc"; + reg = <0x3600 0x100>; + #address-cells = <1>; + #size-cells = <0>; + #io-channel-cells = <1>; + interrupt-parent = <&smb138x>; + interrupts = <0x36 0x0 IRQ_TYPE_EDGE_BOTH>; + interrupt-names = "eoc"; + + batt_temp@0 { + reg = <0>; + qcom,rbias = <68100>; + qcom,rtherm-at-25degc = <68000>; + qcom,beta-coefficient = <3450>; + }; + + skin_temp@1 { + reg = <1>; + qcom,rbias = <33000>; + qcom,rtherm-at-25degc = <68000>; + qcom,beta-coefficient = <3450>; + }; + + die_temp@2 { + reg = <2>; + qcom,scale = <(-1306)>; + qcom,offset = <397904>; + }; + + batt_i@3 { + reg = <3>; + qcom,channel = <3>; + qcom,scale = <(-20000000)>; + }; + + batt_v@4 { + reg = <4>; + qcom,scale = <5000000>; + }; + + input_i@5 { + reg = <5>; + qcom,scale = <14285714>; + }; + + input_v@6 { + reg = <6>; + qcom,scale = <25000000>; + }; + + otg_i@7 { + reg = <7>; + qcom,scale = <5714286>; + }; + }; + + smb1381_charger: qcom,smb1381-charger@1000 { + compatible = "qcom,smb138x-parallel-slave"; + qcom,pmic-revid = <&smb138x_revid>; + reg = <0x1000 0x700>; + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&smb138x>; + io-channels = + <&smb138x_tadc 1>, + <&smb138x_tadc 2>, + <&smb138x_tadc 3>, + <&smb138x_tadc 14>, + <&smb138x_tadc 15>, + <&smb138x_tadc 16>, + <&smb138x_tadc 17>; + io-channel-names = + "connector_temp", + "charger_temp", + "batt_i", + "connector_temp_thr1", + "connector_temp_thr2", + "connector_temp_thr3", + "charger_temp_max"; + + qcom,chgr@1000 { + reg = <0x1000 0x100>; + interrupts = <0x10 0x1 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "chg-state-change"; + }; + + qcom,chgr-misc@1600 { + reg = <0x1600 0x100>; + interrupts = <0x16 0x1 IRQ_TYPE_EDGE_RISING>, + <0x16 0x6 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog-bark", + "temperature-change"; + }; + }; + }; +}; + +&smb1381_charger { + smb138x_vbus: qcom,smb138x-vbus { + status = "disabled"; + regulator-name = "smb138x-vbus"; + }; +}; diff -Nruw linux-4.4.115-fbx/arch/arm/boot/dts/qcom./skeleton64.dtsi linux-4.4.115-fbx/arch/arm/boot/dts/qcom/skeleton64.dtsi --- linux-4.4.115-fbx/arch/arm/boot/dts/qcom./skeleton64.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ linux-4.4.115-fbx/arch/arm/boot/dts/qcom/skeleton64.dtsi 2019-01-22 16:16:21.215225687 +0100 @@ -0,0 +1,15 @@ +/* + * Skeleton device tree in the 64 bits version; the bare minimum + * needed to boot; just include and add a compatible value. The + * bootloader will typically populate the memory node. + */ + +/ { + #address-cells = <2>; + #size-cells = <2>; + cpus { }; + soc { }; + chosen { }; + aliases { }; + memory { device_type = "memory"; reg = <0 0 0 0>; }; +}; --- /dev/null 2019-10-24 16:47:25.704025805 +0200 +++ linux-4.4.115-fbx/arch/arm64/boot/dts/include/dt-bindings/clock/audio-ext-clk.h 2019-01-22 16:16:28.167288642 +0100 @@ -0,0 +1,30 @@ +/* Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __AUDIO_EXT_CLK_H +#define __AUDIO_EXT_CLK_H + +/* Audio External Clocks */ +#define AUDIO_PMI_CLK 0 +#define AUDIO_PMIC_LNBB_CLK 0 +#define AUDIO_AP_CLK 1 +#define AUDIO_AP_CLK2 2 +#define AUDIO_LPASS_MCLK 3 +#define AUDIO_LPASS_MCLK2 4 + +#define clk_audio_ap_clk 0x9b5727cb +#define clk_audio_pmi_clk 0xcbfe416d +#define clk_audio_ap_clk2 0x454d1e91 +#define clk_audio_lpass_mclk 0xf0f2a284 +#define clk_audio_pmi_lnbb_clk 0x57312343 + +#endif --- /dev/null 2019-10-24 16:47:25.704025805 +0200 +++ linux-4.4.115-fbx/arch/arm64/boot/dts/include/dt-bindings/clock/msm-clocks-8996.h 2019-01-22 16:16:28.171288678 +0100 @@ -0,0 +1,574 @@ +/* Copyright (c) 2014-2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __MSM_CLOCKS_8996_H +#define __MSM_CLOCKS_8996_H + +#include "audio-ext-clk.h" + +/* clock_gcc controlled clocks */ +#define clk_cxo_clk_src 0x79e95308 +#define clk_pnoc_clk 0x4325d220 +#define clk_pnoc_a_clk 0x2808c12b +#define clk_bimc_clk 0x4b80bf00 +#define clk_bimc_a_clk 0x4b25668a +#define clk_cnoc_clk 0xd5ccb7f4 +#define clk_cnoc_a_clk 0xd8fe2ccc +#define clk_snoc_clk 0x2c341aa0 +#define clk_snoc_a_clk 0x8fcef2af +#define clk_bb_clk1 0xf5304268 +#define clk_bb_clk1_ao 0xfa113810 +#define clk_bb_clk1_pin 0x6dd0a779 +#define clk_bb_clk1_pin_ao 0x9b637772 +#define clk_bb_clk2 0xfe15cb87 +#define clk_bb_clk2_ao 0x59682706 +#define clk_bb_clk2_pin 0x498938e5 +#define clk_bb_clk2_pin_ao 0x52513787 +#define clk_bimc_msmbus_clk 0xd212feea +#define clk_bimc_msmbus_a_clk 0x71d1a499 +#define clk_ce1_a_clk 0x44a833fe +#define clk_cnoc_msmbus_clk 0x62228b5d +#define clk_cnoc_msmbus_a_clk 0x67442955 +#define clk_cxo_clk_src_ao 0x64eb6004 +#define clk_cxo_dwc3_clk 0xf79c19f6 +#define clk_cxo_lpm_clk 0x94adbf3d +#define clk_cxo_otg_clk 0x4eec0bb9 +#define clk_cxo_pil_lpass_clk 0xe17f0ff6 +#define clk_cxo_pil_ssc_clk 0x81832015 +#define clk_div_clk1 0xaa1157a6 +#define clk_div_clk1_ao 0x6b943d68 +#define clk_div_clk2 0xd454019f +#define clk_div_clk2_ao 0x53f9e788 +#define clk_div_clk3 0xa9a55a68 +#define clk_div_clk3_ao 0x3d6725a8 +#define clk_ipa_a_clk 0xeeec2919 +#define clk_ipa_clk 0xfa685cda +#define clk_ln_bb_clk 0x3ab0b36d +#define clk_ln_bb_a_clk 0xc7257ea8 +#define clk_ln_bb_clk_pin 0x1b1c476a +#define clk_ln_bb_a_clk_pin 0x9cbb5411 +#define clk_mcd_ce1_clk 0xbb615d26 +#define clk_pnoc_keepalive_a_clk 0xf8f91f0b +#define clk_pnoc_msmbus_clk 0x38b95c77 +#define clk_pnoc_msmbus_a_clk 0x8c9b4e93 +#define clk_pnoc_pm_clk 0xd6f7dfb9 +#define clk_pnoc_sps_clk 0xd482ecc7 +#define clk_qdss_a_clk 0xdd121669 +#define clk_qdss_clk 0x1492202a +#define clk_rf_clk1 0xaabeea5a +#define clk_rf_clk1_ao 0x72a10cb8 +#define clk_rf_clk1_pin 0x8f463562 +#define clk_rf_clk1_pin_ao 0x62549ff6 +#define clk_rf_clk2 0x24a30992 +#define clk_rf_clk2_ao 0x944d8bbd +#define clk_rf_clk2_pin 0xa7c5602a +#define clk_rf_clk2_pin_ao 0x2d75eb4d +#define clk_snoc_msmbus_clk 0xe6900bb6 +#define clk_snoc_msmbus_a_clk 0x5d4683bd +#define clk_mcd_ce1_clk 0xbb615d26 +#define clk_qcedev_ce1_clk 0x293f97b0 +#define clk_qcrypto_ce1_clk 0xa6ac14df +#define clk_qseecom_ce1_clk 0xaa858373 +#define clk_scm_ce1_clk 0xd8ebcc62 +#define clk_ce1_clk 0x42229c55 +#define clk_gcc_ce1_ahb_m_clk 0x2eb28c01 +#define clk_gcc_ce1_axi_m_clk 0xc174dfba +#define clk_measure_only_bimc_hmss_axi_clk 0xc1cc4f11 +#define clk_aggre1_noc_clk 0x049abba8 +#define clk_aggre1_noc_a_clk 0xc12e4220 +#define clk_aggre2_noc_clk 0xaa681404 +#define clk_aggre2_noc_a_clk 0xcab67089 +#define clk_mmssnoc_axi_rpm_clk 0x4d7f8cdc +#define clk_mmssnoc_axi_rpm_a_clk 0xfbea899b +#define clk_mmssnoc_axi_clk 0xdb4b31e6 +#define clk_mmssnoc_axi_a_clk 0xd4970614 +#define clk_mmssnoc_gds_clk 0x06a22afa + +#define clk_gpll0 0x1ebe3bc4 +#define clk_gpll0_ao 0xa1368304 +#define clk_gpll0_out_main 0xe9374de7 +#define clk_gpll4 0xb3b5d85b +#define clk_gpll4_out_main 0xa9a0ab9d +#define clk_ufs_axi_clk_src 0x297ca380 +#define clk_pcie_aux_clk_src 0xebc50566 +#define clk_usb30_master_clk_src 0xc6262f89 +#define clk_usb20_master_clk_src 0x5680ac83 +#define clk_ufs_ice_core_clk_src 0xda8e7119 +#define clk_blsp1_qup1_i2c_apps_clk_src 0x17f78f5e +#define clk_blsp1_qup1_spi_apps_clk_src 0xf534c4fa +#define clk_blsp1_qup2_i2c_apps_clk_src 0x8de71c79 +#define clk_blsp1_qup2_spi_apps_clk_src 0x33cf809a +#define clk_blsp1_qup3_i2c_apps_clk_src 0xf161b902 +#define clk_blsp1_qup3_spi_apps_clk_src 0x5e95683f +#define clk_blsp1_qup4_i2c_apps_clk_src 0xb2ecce68 +#define clk_blsp1_qup4_spi_apps_clk_src 0xddb5bbdb +#define clk_blsp1_qup5_i2c_apps_clk_src 0x71ea7804 +#define clk_blsp1_qup5_spi_apps_clk_src 0x9752f35f +#define clk_blsp1_qup6_i2c_apps_clk_src 0x28806803 +#define clk_blsp1_qup6_spi_apps_clk_src 0x44a1edc4 +#define clk_blsp1_uart1_apps_clk_src 0xf8146114 +#define clk_blsp1_uart2_apps_clk_src 0xfc9c2f73 +#define clk_blsp1_uart3_apps_clk_src 0x600497f2 +#define clk_blsp1_uart4_apps_clk_src 0x56bff15c +#define clk_blsp1_uart5_apps_clk_src 0x218ef697 +#define clk_blsp1_uart6_apps_clk_src 0x8fbdbe4c +#define clk_blsp2_qup1_i2c_apps_clk_src 0xd6d1e95d +#define clk_blsp2_qup1_spi_apps_clk_src 0xcc1b8365 +#define clk_blsp2_qup2_i2c_apps_clk_src 0x603b5c51 +#define clk_blsp2_qup2_spi_apps_clk_src 0xd577dc44 +#define clk_blsp2_qup3_i2c_apps_clk_src 0xea82959c +#define clk_blsp2_qup3_spi_apps_clk_src 0xd04b1e92 +#define clk_blsp2_qup4_i2c_apps_clk_src 0x73dc968c +#define clk_blsp2_qup4_spi_apps_clk_src 0x25d4a2b1 +#define clk_blsp2_qup5_i2c_apps_clk_src 0xcc3698bd +#define clk_blsp2_qup5_spi_apps_clk_src 0xfa0cf45e +#define clk_blsp2_qup6_i2c_apps_clk_src 0x2fa53151 +#define clk_blsp2_qup6_spi_apps_clk_src 0x5ca86755 +#define clk_blsp2_uart1_apps_clk_src 0x562c66dc +#define clk_blsp2_uart2_apps_clk_src 0xdd448080 +#define clk_blsp2_uart3_apps_clk_src 0x46b2e90f +#define clk_blsp2_uart4_apps_clk_src 0x23a093d2 +#define clk_blsp2_uart5_apps_clk_src 0xe067616a +#define clk_blsp2_uart6_apps_clk_src 0xe02d2829 +#define clk_gp1_clk_src 0xad85b97a +#define clk_gp2_clk_src 0xfb1f0065 +#define clk_gp3_clk_src 0x63b693d6 +#define clk_hmss_rbcpr_clk_src 0xedd9a474 +#define clk_pdm2_clk_src 0x31e494fd +#define clk_sdcc1_apps_clk_src 0xd4975db2 +#define clk_sdcc2_apps_clk_src 0xfc46c821 +#define clk_sdcc3_apps_clk_src 0xea34c7f4 +#define clk_sdcc4_apps_clk_src 0x7aaaaa0c +#define clk_tsif_ref_clk_src 0x4e9042d1 +#define clk_usb20_mock_utmi_clk_src 0xc3aaeecb +#define clk_usb30_mock_utmi_clk_src 0xa024a976 +#define clk_usb3_phy_aux_clk_src 0x15eec63c +#define clk_gcc_qusb2phy_prim_reset 0x07550fa1 +#define clk_gcc_qusb2phy_sec_reset 0x3f3a87d0 +#define clk_gcc_periph_noc_usb20_ahb_clk 0xfb9f26e9 +#define clk_gcc_mmss_gcc_dbg_clk 0xe89d461c +#define clk_cpu_dbg_clk 0x6550dfa9 +#define clk_gcc_blsp1_ahb_clk 0x8caa5b4f +#define clk_gcc_blsp1_qup1_i2c_apps_clk 0xc303fae9 +#define clk_gcc_blsp1_qup1_spi_apps_clk 0x759a76b0 +#define clk_gcc_blsp1_qup2_i2c_apps_clk 0x1076f220 +#define clk_gcc_blsp1_qup2_spi_apps_clk 0x3e77d48f +#define clk_gcc_blsp1_qup3_i2c_apps_clk 0x9e25ac82 +#define clk_gcc_blsp1_qup3_spi_apps_clk 0xfb978880 +#define clk_gcc_blsp1_qup4_i2c_apps_clk 0xd7f40f6f +#define clk_gcc_blsp1_qup4_spi_apps_clk 0x80f8722f +#define clk_gcc_blsp1_qup5_i2c_apps_clk 0xacae5604 +#define clk_gcc_blsp1_qup5_spi_apps_clk 0xbf3e15d7 +#define clk_gcc_blsp1_qup6_i2c_apps_clk 0x5c6ad820 +#define clk_gcc_blsp1_qup6_spi_apps_clk 0x780d9f85 +#define clk_gcc_blsp1_uart1_apps_clk 0xc7c62f90 +#define clk_gcc_blsp1_uart2_apps_clk 0xf8a61c96 +#define clk_gcc_blsp1_uart3_apps_clk 0xc3298bd7 +#define clk_gcc_blsp1_uart4_apps_clk 0x26be16c0 +#define clk_gcc_blsp1_uart5_apps_clk 0x28a6bc74 +#define clk_gcc_blsp1_uart6_apps_clk 0x28fd3466 +#define clk_gcc_blsp2_ahb_clk 0x8f283c1d +#define clk_gcc_blsp2_qup1_i2c_apps_clk 0x9ace11dd +#define clk_gcc_blsp2_qup1_spi_apps_clk 0xa32604cc +#define clk_gcc_blsp2_qup2_i2c_apps_clk 0x1bf9a57e +#define clk_gcc_blsp2_qup2_spi_apps_clk 0xbf54ca6d +#define clk_gcc_blsp2_qup3_i2c_apps_clk 0x336d4170 +#define clk_gcc_blsp2_qup3_spi_apps_clk 0xc68509d6 +#define clk_gcc_blsp2_qup4_i2c_apps_clk 0xbd22539d +#define clk_gcc_blsp2_qup4_spi_apps_clk 0x01a72b93 +#define clk_gcc_blsp2_qup5_i2c_apps_clk 0xe2b2ce1d +#define clk_gcc_blsp2_qup5_spi_apps_clk 0xf40999cd +#define clk_gcc_blsp2_qup6_i2c_apps_clk 0x894bcea4 +#define clk_gcc_blsp2_qup6_spi_apps_clk 0xfe1bd34a +#define clk_gcc_blsp2_uart1_apps_clk 0x8c3512ff +#define clk_gcc_blsp2_uart2_apps_clk 0x1e1965a3 +#define clk_gcc_blsp2_uart3_apps_clk 0x382415ab +#define clk_gcc_blsp2_uart4_apps_clk 0x87a44b42 +#define clk_gcc_blsp2_uart5_apps_clk 0x5cd30649 +#define clk_gcc_blsp2_uart6_apps_clk 0x8feee5ab +#define clk_gcc_boot_rom_ahb_clk 0xde2adeb1 +#define clk_gcc_gp1_clk 0x057f7b69 +#define clk_gcc_gp2_clk 0x9bf83ffd +#define clk_gcc_gp3_clk 0xec6539ee +#define clk_gcc_hmss_rbcpr_clk 0x699183be +#define clk_gcc_mmss_noc_cfg_ahb_clk 0xb41a9d99 +#define clk_gcc_pcie_0_aux_clk 0x3d2e3ece +#define clk_gcc_pcie_0_cfg_ahb_clk 0x4dd325c3 +#define clk_gcc_pcie_0_mstr_axi_clk 0x3f85285b +#define clk_gcc_pcie_0_slv_axi_clk 0xd69638a1 +#define clk_gcc_pcie_0_pipe_clk 0x4f37621e +#define clk_gcc_pcie_0_phy_reset 0xdc3201c1 +#define clk_gcc_pcie_1_aux_clk 0xc9bb962c +#define clk_gcc_pcie_1_cfg_ahb_clk 0xb6338658 +#define clk_gcc_pcie_1_mstr_axi_clk 0xc20f6269 +#define clk_gcc_pcie_1_slv_axi_clk 0xd54e40d6 +#define clk_gcc_pcie_1_pipe_clk 0xc1627422 +#define clk_gcc_pcie_1_phy_reset 0x674481bb +#define clk_gcc_pcie_2_aux_clk 0xa4dc7ae8 +#define clk_gcc_pcie_2_cfg_ahb_clk 0x4f1d3121 +#define clk_gcc_pcie_2_mstr_axi_clk 0x9e81724a +#define clk_gcc_pcie_2_slv_axi_clk 0x7990d8b2 +#define clk_gcc_pcie_2_pipe_clk 0xa757a834 +#define clk_gcc_pcie_2_phy_reset 0x82634880 +#define clk_gcc_pcie_phy_reset 0x9bc3c959 +#define clk_gcc_pcie_phy_com_reset 0x8bf513e6 +#define clk_gcc_pcie_phy_nocsr_com_phy_reset 0x0c16a2da +#define clk_gcc_pcie_phy_aux_clk 0x4746e74f +#define clk_gcc_pcie_phy_cfg_ahb_clk 0x8533671a +#define clk_gcc_pdm2_clk 0x99d55711 +#define clk_gcc_pdm_ahb_clk 0x365664f6 +#define clk_gcc_prng_ahb_clk 0x397e7eaa +#define clk_gcc_sdcc1_ahb_clk 0x691e0caa +#define clk_gcc_sdcc1_apps_clk 0x9ad6fb96 +#define clk_gcc_sdcc2_ahb_clk 0x23d5727f +#define clk_gcc_sdcc2_apps_clk 0x861b20ac +#define clk_gcc_sdcc3_ahb_clk 0x565b2c03 +#define clk_gcc_sdcc3_apps_clk 0x0b27aeac +#define clk_gcc_sdcc4_ahb_clk 0x64f3e6a8 +#define clk_gcc_sdcc4_apps_clk 0xbf7c4dc8 +#define clk_gcc_tsif_ahb_clk 0x88d2822c +#define clk_gcc_tsif_ref_clk 0x8f1ed2c2 +#define clk_gcc_ufs_ahb_clk 0x1914bb84 +#define clk_gcc_ufs_axi_clk 0x47c743a7 +#define clk_gcc_ufs_ice_core_clk 0x310b0710 +#define clk_gcc_ufs_rx_cfg_clk 0xa6747786 +#define clk_gcc_ufs_rx_symbol_0_clk 0x7f43251c +#define clk_gcc_ufs_rx_symbol_1_clk 0x03182fde +#define clk_gcc_ufs_tx_cfg_clk 0xba2cf8b5 +#define clk_gcc_ufs_tx_symbol_0_clk 0x6a9f747a +#define clk_gcc_ufs_unipro_core_clk 0x2daf7fd2 +#define clk_gcc_ufs_sys_clk_core_clk 0x360e5ac8 +#define clk_gcc_ufs_tx_symbol_clk_core_clk 0xf6fb0df7 +#define clk_gcc_usb20_master_clk 0x24c3b66a +#define clk_gcc_usb20_mock_utmi_clk 0xe8db8203 +#define clk_gcc_usb20_sleep_clk 0x6e8cb4b2 +#define clk_gcc_usb30_master_clk 0xb3b4e2cb +#define clk_gcc_usb30_mock_utmi_clk 0xa800b65a +#define clk_gcc_usb30_sleep_clk 0xd0b65c92 +#define clk_gcc_usb3_phy_aux_clk 0x0d9a36e0 +#define clk_gcc_usb3_phy_pipe_clk 0xf279aff2 +#define clk_gcc_usb_phy_cfg_ahb2phy_clk 0xd1231a0e +#define clk_gcc_aggre0_cnoc_ahb_clk 0x53a35559 +#define clk_gcc_aggre0_snoc_axi_clk 0x3c446400 +#define clk_gcc_aggre0_noc_qosgen_extref_clk 0x8c4356ba +#define clk_hlos1_vote_lpass_core_smmu_clk 0x3aaa1743 +#define clk_hlos1_vote_lpass_adsp_smmu_clk 0xc76f702f +#define clk_gcc_usb3_phy_reset 0x03d559f1 +#define clk_gcc_usb3phy_phy_reset 0xb1a4f885 +#define clk_gcc_usb3_clkref_clk 0xb6cc8f01 +#define clk_gcc_hdmi_clkref_clk 0x4d4eec04 +#define clk_gcc_edp_clkref_clk 0xa8685c3f +#define clk_gcc_ufs_clkref_clk 0x92aa126f +#define clk_gcc_pcie_clkref_clk 0xa2e247fa +#define clk_gcc_rx2_usb2_clkref_clk 0x27ec24ba +#define clk_gcc_rx1_usb2_clkref_clk 0x53351d25 +#define clk_gcc_smmu_aggre0_ahb_clk 0x47a06ce4 +#define clk_gcc_smmu_aggre0_axi_clk 0x3cac4a6c +#define clk_gcc_sys_noc_usb3_axi_clk 0x94d26800 +#define clk_gcc_sys_noc_ufs_axi_clk 0x19d38312 +#define clk_gcc_aggre2_usb3_axi_clk 0xd5822a8e +#define clk_gcc_aggre2_ufs_axi_clk 0xb31e5191 +#define clk_gcc_mmss_gpll0_div_clk 0xdd06848d +#define clk_gcc_mmss_bimc_gfx_clk 0xe4f28754 +#define clk_gcc_bimc_gfx_clk 0x3edd69ad +#define clk_gcc_qspi_ahb_clk 0x96969dc8 +#define clk_gcc_qspi_ser_clk 0xfaf1e266 +#define clk_qspi_ser_clk_src 0x426676ee +#define clk_sdcc1_ice_core_clk_src 0xfd6a4301 +#define clk_gcc_sdcc1_ice_core_clk 0x0fd5680a +#define clk_gcc_mss_cfg_ahb_clk 0x111cde81 +#define clk_gcc_mss_snoc_axi_clk 0x0e71de85 +#define clk_gcc_mss_q6_bimc_axi_clk 0x67544d62 +#define clk_gcc_mss_mnoc_bimc_axi_clk 0xf665d03f +#define clk_gpll0_out_msscc 0x7d794829 +#define clk_gcc_debug_mux_v2 0xf7e749f0 +#define clk_gcc_dcc_ahb_clk 0xfa14a88c +#define clk_gcc_aggre0_noc_mpu_cfg_ahb_clk 0x5c1bb8e2 + +/* clock_mmss controlled clocks */ +#define clk_mmsscc_xo 0x05e63704 +#define clk_mmsscc_gpll0 0xe900c515 +#define clk_mmsscc_gpll0_div 0x73892e05 +#define clk_mmsscc_mmssnoc_ahb 0x7b4bd6f7 +#define clk_mmpll0 0xdd83b751 +#define clk_mmpll0_out_main 0x2f996a31 +#define clk_mmpll1 0x6da7fb90 +#define clk_mmpll1_out_main 0xa0d3a7da +#define clk_mmpll4 0x22c063c1 +#define clk_mmpll4_out_main 0xfb21c2fd +#define clk_mmpll3 0x18c76899 +#define clk_mmpll3_out_main 0x6eb6328f +#define clk_ahb_clk_src 0x86f49203 +#define clk_mmpll2 0x1190e4d8 +#define clk_mmpll2_out_main 0x1e9e24a8 +#define clk_mmpll8 0xd06ad45e +#define clk_mmpll8_out_main 0x75b1f386 +#define clk_mmpll9 0x1c50684c +#define clk_mmpll9_out_main 0x16b74937 +#define clk_mmpll5 0xa41e1936 +#define clk_mmpll5_out_main 0xcc1897bf +#define clk_csi0_clk_src 0x227e65bc +#define clk_vfe0_clk_src 0xa0c2bd8f +#define clk_vfe1_clk_src 0x4e357366 +#define clk_csi1_clk_src 0x6a2a6c36 +#define clk_csi2_clk_src 0x4113589f +#define clk_csi3_clk_src 0xfd934012 +#define clk_maxi_clk_src 0x52c09777 +#define clk_cpp_clk_src 0x8382f56d +#define clk_jpeg0_clk_src 0x9a0a0ac3 +#define clk_jpeg2_clk_src 0x5ad927f3 +#define clk_jpeg_dma_clk_src 0xb68afcea +#define clk_mdp_clk_src 0x6dc1f8f1 +#define clk_video_core_clk_src 0x8be4c944 +#define clk_fd_core_clk_src 0xe4799ab7 +#define clk_cci_clk_src 0x822f3d97 +#define clk_csiphy0_3p_clk_src 0xd2474b12 +#define clk_csiphy1_3p_clk_src 0x46a02aff +#define clk_csiphy2_3p_clk_src 0x1447813f +#define clk_camss_gp0_clk_src 0x6b57cfe6 +#define clk_camss_gp1_clk_src 0xf735368a +#define clk_jpeg_dma_clk_src 0xb68afcea +#define clk_mclk0_clk_src 0x266b3853 +#define clk_mclk1_clk_src 0xa73cad0c +#define clk_mclk2_clk_src 0x42545468 +#define clk_mclk3_clk_src 0x2bfbb714 +#define clk_csi0phytimer_clk_src 0xc8a309be +#define clk_csi1phytimer_clk_src 0x7c0fe23a +#define clk_csi2phytimer_clk_src 0x62ffea9c +#define clk_rbbmtimer_clk_src 0x17649ecc +#define clk_esc0_clk_src 0xb41d7c38 +#define clk_esc1_clk_src 0x3b0afa42 +#define clk_hdmi_clk_src 0xb40aeea9 +#define clk_vsync_clk_src 0xecb43940 +#define clk_rbcpr_clk_src 0x2c2e9af2 +#define clk_video_subcore0_clk_src 0x88d79636 +#define clk_video_subcore1_clk_src 0x4966930c +#define clk_mmss_bto_ahb_clk 0xfdf8c361 +#define clk_camss_ahb_clk 0xc4ff91d4 +#define clk_camss_cci_ahb_clk 0x04c4441a +#define clk_camss_cci_clk 0xd6cb5eb9 +#define clk_camss_cpp_ahb_clk 0x12e9a87b +#define clk_camss_cpp_clk 0xb82f366b +#define clk_camss_cpp_axi_clk 0x5598c804 +#define clk_camss_cpp_vbif_ahb_clk 0xb5f31be4 +#define clk_camss_csi0_ahb_clk 0x6e29c972 +#define clk_camss_csi0_clk 0x30862ddb +#define clk_camss_csi0phy_clk 0x2cecfb84 +#define clk_camss_csi0pix_clk 0x6946f77b +#define clk_camss_csi0rdi_clk 0x83645ef5 +#define clk_camss_csi1_ahb_clk 0xccc15f06 +#define clk_camss_csi1_clk 0xb150f052 +#define clk_camss_csi1phy_clk 0xb989f06d +#define clk_camss_csi1pix_clk 0x58d19bf3 +#define clk_camss_csi1rdi_clk 0x4d2f3352 +#define clk_camss_csi2_ahb_clk 0x92d02d75 +#define clk_camss_csi2_clk 0x74fc92e8 +#define clk_camss_csi2phy_clk 0xda05d9d8 +#define clk_camss_csi2pix_clk 0xf8ed0731 +#define clk_camss_csi2rdi_clk 0xdc1b2081 +#define clk_camss_csi3_ahb_clk 0xee5e459c +#define clk_camss_csi3_clk 0x39488fdd +#define clk_camss_csi3phy_clk 0x8b6063b9 +#define clk_camss_csi3pix_clk 0xd82bd467 +#define clk_camss_csi3rdi_clk 0xb6750046 +#define clk_camss_csi_vfe0_clk 0x3023937a +#define clk_camss_csi_vfe1_clk 0xe66fa522 +#define clk_camss_csiphy0_3p_clk 0xf2a54f5a +#define clk_camss_csiphy1_3p_clk 0x8bf70cb2 +#define clk_camss_csiphy2_3p_clk 0x1c14c939 +#define clk_camss_gp0_clk 0xcee7e51d +#define clk_camss_gp1_clk 0x41f1c2e3 +#define clk_camss_ispif_ahb_clk 0x9a212c6d +#define clk_camss_jpeg0_clk 0x0b0e2db7 +#define clk_camss_jpeg2_clk 0xd7291c8d +#define clk_camss_jpeg_ahb_clk 0x1f47fd28 +#define clk_camss_jpeg_axi_clk 0x9e5545c8 +#define clk_camss_jpeg_dma_clk 0x2336e65d +#define clk_camss_mclk0_clk 0xcf0c61e0 +#define clk_camss_mclk1_clk 0xd1410ed4 +#define clk_camss_mclk2_clk 0x851286f2 +#define clk_camss_mclk3_clk 0x4db11c45 +#define clk_camss_micro_ahb_clk 0x33a23277 +#define clk_camss_csi0phytimer_clk 0xff93b3c8 +#define clk_camss_csi1phytimer_clk 0x6c399ab6 +#define clk_camss_csi2phytimer_clk 0x24f47f49 +#define clk_camss_top_ahb_clk 0x8f8b2d33 +#define clk_camss_vfe_ahb_clk 0x595197bc +#define clk_camss_vfe_axi_clk 0x273d4c31 +#define clk_camss_vfe0_ahb_clk 0x4652833c +#define clk_camss_vfe0_clk 0x1e9bb8c4 +#define clk_camss_vfe0_stream_clk 0x22835fa4 +#define clk_camss_vfe1_ahb_clk 0x6a56abd3 +#define clk_camss_vfe1_clk 0x5bffa69b +#define clk_camss_vfe1_stream_clk 0x92f849b9 +#define clk_fd_ahb_clk 0x868a2c5c +#define clk_fd_core_clk 0x3badcae4 +#define clk_fd_core_uar_clk 0x7e624e15 +#define clk_gpu_ahb_clk 0xf97f1d43 +#define clk_gpu_aon_isense_clk 0xa9e9b297 +#define clk_gpu_gx_gfx3d_clk 0xb7ece823 +#define clk_gpu_mx_clk 0xb80ccedf +#define clk_gpu_gx_rbbmtimer_clk 0xdeba634e +#define clk_mdss_ahb_clk 0x684ccb41 +#define clk_mdss_axi_clk 0xcc07d687 +#define clk_mdss_esc0_clk 0x28cafbe6 +#define clk_mdss_esc1_clk 0xc22c6883 +#define clk_mdss_hdmi_ahb_clk 0x01cef516 +#define clk_mdss_hdmi_clk 0x097a6de9 +#define clk_mdss_mdp_clk 0x618336ac +#define clk_mdss_vsync_clk 0x42a022d3 +#define clk_mmss_misc_ahb_clk 0xea30b0e7 +#define clk_mmss_misc_cxo_clk 0xe620cd80 +#define clk_mmagic_bimc_noc_cfg_ahb_clk 0x12d5ba72 +#define clk_mmagic_camss_axi_clk 0xa8b1c16b +#define clk_mmagic_camss_noc_cfg_ahb_clk 0x5182c819 +#define clk_mmss_mmagic_cfg_ahb_clk 0x5e94a822 +#define clk_mmagic_mdss_axi_clk 0xa0359d10 +#define clk_mmagic_mdss_noc_cfg_ahb_clk 0x9c6d5482 +#define clk_mmagic_video_axi_clk 0x7b9219c3 +#define clk_mmagic_video_noc_cfg_ahb_clk 0x5124d256 +#define clk_mmss_mmagic_ahb_clk 0x3d15f2b0 +#define clk_mmss_mmagic_maxi_clk 0xbdaf5af7 +#define clk_mmss_rbcpr_ahb_clk 0x623ba55f +#define clk_mmss_rbcpr_clk 0x69a23a6f +#define clk_mmss_spdm_cpp_clk 0xefe35cd2 +#define clk_mmss_spdm_jpeg_dma_clk 0xcb7bd5a0 +#define clk_smmu_cpp_ahb_clk 0x3ad82d84 +#define clk_smmu_cpp_axi_clk 0xa6bb2f4a +#define clk_smmu_jpeg_ahb_clk 0x10c436ec +#define clk_smmu_jpeg_axi_clk 0x41112f37 +#define clk_smmu_mdp_ahb_clk 0x04994cb2 +#define clk_smmu_mdp_axi_clk 0x7fd71687 +#define clk_smmu_rot_ahb_clk 0xa30772c9 +#define clk_smmu_rot_axi_clk 0xfed7c078 +#define clk_smmu_vfe_ahb_clk 0x4dabebe7 +#define clk_smmu_vfe_axi_clk 0xde483725 +#define clk_smmu_video_ahb_clk 0x2d738e2c +#define clk_smmu_video_axi_clk 0xe2b5b887 +#define clk_video_ahb_clk 0x90775cfb +#define clk_video_axi_clk 0xe6c16dba +#define clk_video_core_clk 0x7e876ec3 +#define clk_video_maxi_clk 0x97749db6 +#define clk_video_subcore0_clk 0xb6f63e6c +#define clk_video_subcore1_clk 0x26c29cb4 +#define clk_vmem_ahb_clk 0xab6223ff +#define clk_vmem_maxi_clk 0x15ef32db +#define clk_mmss_debug_mux 0xe646ffda +#define clk_mmss_gcc_dbg_clk 0xafa4d48a +#define clk_gfx3d_clk_src 0x917f76ef +#define clk_extpclk_clk_src 0xb2c31abd +#define clk_mdss_byte0_clk 0xf5a03f64 +#define clk_mdss_byte1_clk 0xb8c7067d +#define clk_mdss_extpclk_clk 0xfa5aadb0 +#define clk_mdss_pclk0_clk 0x3487234a +#define clk_mdss_pclk1_clk 0xd5804246 +#define clk_gpu_gcc_dbg_clk 0x0ccc42cd +#define clk_mdss_mdp_vote_clk 0x588460a4 +#define clk_mdss_rotator_vote_clk 0x5b1f675e +#define clk_mmpll2_postdiv_clk 0x4fdeaaba +#define clk_mmpll8_postdiv_clk 0xedf57882 +#define clk_mmpll9_postdiv_clk 0x3064b618 +#define clk_gfx3d_clk_src_v2 0x4210acb7 +#define clk_byte0_clk_src 0x75cc885b +#define clk_byte1_clk_src 0x63c2c955 +#define clk_pclk0_clk_src 0xccac1f35 +#define clk_pclk1_clk_src 0x090f68ac +#define clk_ext_byte0_clk_src 0xfb32f31e +#define clk_ext_byte1_clk_src 0x585ef6d4 +#define clk_ext_pclk0_clk_src 0x087c1612 +#define clk_ext_pclk1_clk_src 0x8067c5a3 + +/* clock_debug controlled clocks */ +#define clk_gcc_debug_mux 0x8121ac15 + +/* external multimedia clocks */ +#define clk_dsi0pll_pixel_clk_mux 0x792379e1 +#define clk_dsi0pll_byte_clk_mux 0x60e83f06 +#define clk_dsi0pll_byte_clk_src 0xbbaa30be +#define clk_dsi0pll_pixel_clk_src 0x45b3260f +#define clk_dsi0pll_n2_div_clk 0x1474c213 +#define clk_dsi0pll_post_n1_div_clk 0xdab8c389 +#define clk_dsi0pll_vco_clk 0x15940d40 +#define clk_dsi1pll_pixel_clk_mux 0x36458019 +#define clk_dsi1pll_byte_clk_mux 0xb5a42b7b +#define clk_dsi1pll_byte_clk_src 0x63930a8f +#define clk_dsi1pll_pixel_clk_src 0x0e4c9b56 +#define clk_dsi1pll_n2_div_clk 0x2c9d4007 +#define clk_dsi1pll_post_n1_div_clk 0x03020041 +#define clk_dsi1pll_vco_clk 0x99797b50 +#define clk_mdss_dsi1_vco_clk_src 0xfcd15658 +#define clk_hdmi_vco_clk 0x66003284 + +#define clk_dsi0pll_shadow_byte_clk_src 0x177c029c +#define clk_dsi0pll_shadow_pixel_clk_src 0x98ae3c92 +#define clk_dsi0pll_shadow_n2_div_clk 0xd5f0dad9 +#define clk_dsi0pll_shadow_post_n1_div_clk 0x1f7c8cf8 +#define clk_dsi0pll_shadow_vco_clk 0xb100ca83 +#define clk_dsi1pll_shadow_byte_clk_src 0xfc021ce5 +#define clk_dsi1pll_shadow_pixel_clk_src 0xdcca3ffc +#define clk_dsi1pll_shadow_n2_div_clk 0x189541bf +#define clk_dsi1pll_shadow_post_n1_div_clk 0x1637020e +#define clk_dsi1pll_shadow_vco_clk 0x68d8b6f7 + +/* CPU clocks */ +#define clk_pwrcl_clk 0xc554130e +#define clk_pwrcl_pll 0x25454ca1 +#define clk_pwrcl_alt_pll 0xc445471b +#define clk_pwrcl_pll_main 0x28948e22 +#define clk_pwrcl_alt_pll_main 0x25c8270e +#define clk_pwrcl_hf_mux 0x77706ae6 +#define clk_pwrcl_lf_mux 0xd99e334d +#define clk_perfcl_clk 0x58869997 +#define clk_perfcl_pll 0x97dcec1c +#define clk_perfcl_alt_pll 0xfe2eaea1 +#define clk_perfcl_pll_main 0x0dbf0c0b +#define clk_perfcl_alt_pll_main 0x0b892aab +#define clk_perfcl_hf_mux 0x9e8bbe59 +#define clk_perfcl_lf_mux 0x2f9c278d +#define clk_cbf_pll 0xfe2e96a3 +#define clk_cbf_pll_main 0x2b05cf95 +#define clk_cbf_hf_mux 0x71244f73 +#define clk_cbf_clk 0x48e9e16b +#define clk_xo_ao 0x428c856d +#define clk_sys_apcsaux_clk 0x0b0dd513 +#define clk_cpu_debug_mux 0xc7acaa31 + +/* GCC block resets */ +#define QUSB2PHY_PRIM_BCR 0 +#define QUSB2PHY_SEC_BCR 1 +#define BLSP1_BCR 2 +#define BLSP2_BCR 3 +#define BOOT_ROM_BCR 4 +#define PRNG_BCR 5 +#define UFS_BCR 6 +#define USB_20_BCR 7 +#define USB_30_BCR 8 +#define USB3_PHY_BCR 9 +#define USB3PHY_PHY_BCR 10 +#define PCIE_0_PHY_BCR 11 +#define PCIE_1_PHY_BCR 12 +#define PCIE_2_PHY_BCR 13 +#define PCIE_PHY_BCR 14 +#define PCIE_PHY_COM_BCR 15 +#define PCIE_PHY_NOCSR_COM_PHY_BCR 16 + +/* MMSS Block resets */ +#define VIDEO_BCR 0 +#define MDSS_BCR 1 +#define CAMSS_MICRO_BCR 2 +#define CAMSS_JPEG_BCR 3 +#define CAMSS_VFE0_BCR 4 +#define CAMSS_VFE1_BCR 5 +#define FD_BCR 6 +#define GPU_GX_BCR 7 + +#endif --- /dev/null 2019-10-24 16:47:25.704025805 +0200 +++ linux-4.4.115-fbx/arch/arm64/boot/dts/include/dt-bindings/clock/msm-clocks-8998.h 2019-01-22 16:16:28.171288678 +0100 @@ -0,0 +1,534 @@ +/* Copyright (c) 2015-2017, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __MSM_CLOCKS_8998_H +#define __MSM_CLOCKS_8998_H + +#include "audio-ext-clk.h" + +/* clock_rpm controlled clocks */ +#define clk_ce1_clk 0x42229c55 +#define clk_ce1_a_clk 0x44a833fe +#define clk_cxo_clk_src 0x79e95308 +#define clk_bimc_clk 0x4b80bf00 +#define clk_bimc_a_clk 0x4b25668a +#define clk_cnoc_clk 0xd5ccb7f4 +#define clk_cnoc_a_clk 0xd8fe2ccc +#define clk_snoc_clk 0x2c341aa0 +#define clk_snoc_a_clk 0x8fcef2af +#define clk_cnoc_periph_clk 0xb11e9cf9 +#define clk_cnoc_periph_a_clk 0x1d7faa2e +#define clk_cnoc_periph_keepalive_a_clk 0x7287aef2 +#define clk_ln_bb_clk1 0xb867b147 +#define clk_ln_bb_clk1_ao 0x7f63a93a +#define clk_ln_bb_clk1_pin 0x6fc5653c +#define clk_ln_bb_clk1_pin_ao 0x25d625bf +#define clk_ln_bb_clk2 0xf83e6387 +#define clk_ln_bb_clk2_ao 0x96f09628 +#define clk_ln_bb_clk2_pin 0xa9ebe8d5 +#define clk_ln_bb_clk2_pin_ao 0x89a1226f +#define clk_ln_bb_clk3 0x4f52a39e +#define clk_ln_bb_clk3_ao 0xb15eba76 +#define clk_ln_bb_clk3_pin 0xc4de7dad +#define clk_ln_bb_clk3_pin_ao 0xc01022e8 +#define clk_bimc_msmbus_clk 0xd212feea +#define clk_bimc_msmbus_a_clk 0x71d1a499 +#define clk_cnoc_msmbus_clk 0x62228b5d +#define clk_cnoc_msmbus_a_clk 0x67442955 +#define clk_cxo_clk_src_ao 0x64eb6004 +#define clk_cxo_dwc3_clk 0xf79c19f6 +#define clk_cxo_lpm_clk 0x94adbf3d +#define clk_cxo_otg_clk 0x4eec0bb9 +#define clk_cxo_pil_lpass_clk 0xe17f0ff6 +#define clk_cxo_pil_ssc_clk 0x81832015 +#define clk_cxo_pil_spss_clk 0x5cd71a61 +#define clk_div_clk1 0xaa1157a6 +#define clk_div_clk1_ao 0x6b943d68 +#define clk_div_clk2 0xd454019f +#define clk_div_clk2_ao 0x53f9e788 +#define clk_div_clk3 0xa9a55a68 +#define clk_div_clk3_ao 0x3d6725a8 +#define clk_ipa_clk 0xfa685cda +#define clk_ipa_a_clk 0xeeec2919 +#define clk_mcd_ce1_clk 0xbb615d26 +#define clk_mmssnoc_axi_clk 0xdb4b31e6 +#define clk_mmssnoc_axi_a_clk 0xd4970614 +#define clk_qcedev_ce1_clk 0x293f97b0 +#define clk_qcrypto_ce1_clk 0xa6ac14df +#define clk_qdss_clk 0x1492202a +#define clk_qdss_a_clk 0xdd121669 +#define clk_qseecom_ce1_clk 0xaa858373 +#define clk_rf_clk1 0xaabeea5a +#define clk_rf_clk1_ao 0x72a10cb8 +#define clk_rf_clk1_pin 0x8f463562 +#define clk_rf_clk1_pin_ao 0x62549ff6 +#define clk_rf_clk2 0x24a30992 +#define clk_rf_clk2_ao 0x944d8bbd +#define clk_rf_clk2_pin 0xa7c5602a +#define clk_rf_clk2_pin_ao 0x2d75eb4d +#define clk_rf_clk3 0xb673936b +#define clk_rf_clk3_ao 0x038bb968 +#define clk_rf_clk3_pin 0x726f53f5 +#define clk_rf_clk3_pin_ao 0x76f9240f +#define clk_scm_ce1_clk 0xd8ebcc62 +#define clk_snoc_msmbus_clk 0xe6900bb6 +#define clk_snoc_msmbus_a_clk 0x5d4683bd +#define clk_gcc_ce1_ahb_m_clk 0x2eb28c01 +#define clk_gcc_ce1_axi_m_clk 0xc174dfba +#define clk_aggre1_noc_clk 0x049abba8 +#define clk_aggre1_noc_a_clk 0xc12e4220 +#define clk_aggre2_noc_clk 0xaa681404 +#define clk_aggre2_noc_a_clk 0xcab67089 +#define clk_measure_only_bimc_hmss_axi_clk 0xc1cc4f11 + +/* clock_gcc controlled clocks*/ +#define clk_debug_mmss_clk 0x977c99b6 +#define clk_debug_rpm_clk 0x8e2b07ca +#define clk_debug_cpu_clk 0x0e696b2b +#define clk_gpu_gcc_debug_clk 0x3eb88190 +#define clk_gfx_gcc_debug_clk 0xa3a64fec +#define clk_gpll0 0x1ebe3bc4 +#define clk_gpll0_out_main 0xe9374de7 +#define clk_gpll0_ao 0xa1368304 +#define clk_gcc_mmss_gpll0_clk 0x8050f008 +#define clk_gcc_mmss_gpll0_div_clk 0xdd06848d +#define clk_gcc_gpu_gpll0_clk 0xdad7a7a4 +#define clk_gcc_gpu_gpll0_div_clk 0x07d16c6a +#define clk_gpll4 0xb3b5d85b +#define clk_gpll4_out_main 0xa9a0ab9d +#define clk_usb30_master_clk_src 0xc6262f89 +#define clk_pcie_aux_clk_src 0xebc50566 +#define clk_ufs_axi_clk_src 0x297ca380 +#define clk_blsp1_qup1_i2c_apps_clk_src 0x17f78f5e +#define clk_blsp1_qup1_spi_apps_clk_src 0xf534c4fa +#define clk_blsp1_qup2_i2c_apps_clk_src 0x8de71c79 +#define clk_blsp1_qup2_spi_apps_clk_src 0x33cf809a +#define clk_blsp1_qup3_i2c_apps_clk_src 0xf161b902 +#define clk_blsp1_qup3_spi_apps_clk_src 0x5e95683f +#define clk_blsp1_qup4_i2c_apps_clk_src 0xb2ecce68 +#define clk_blsp1_qup4_spi_apps_clk_src 0xddb5bbdb +#define clk_blsp1_qup5_i2c_apps_clk_src 0x71ea7804 +#define clk_blsp1_qup5_spi_apps_clk_src 0x9752f35f +#define clk_blsp1_qup6_i2c_apps_clk_src 0x28806803 +#define clk_blsp1_qup6_spi_apps_clk_src 0x44a1edc4 +#define clk_blsp1_uart1_apps_clk_src 0xf8146114 +#define clk_blsp1_uart2_apps_clk_src 0xfc9c2f73 +#define clk_blsp1_uart3_apps_clk_src 0x600497f2 +#define clk_blsp2_qup1_i2c_apps_clk_src 0xd6d1e95d +#define clk_blsp2_qup1_spi_apps_clk_src 0xcc1b8365 +#define clk_blsp2_qup2_i2c_apps_clk_src 0x603b5c51 +#define clk_blsp2_qup2_spi_apps_clk_src 0xd577dc44 +#define clk_blsp2_qup3_i2c_apps_clk_src 0xea82959c +#define clk_blsp2_qup3_spi_apps_clk_src 0xd04b1e92 +#define clk_blsp2_qup4_i2c_apps_clk_src 0x73dc968c +#define clk_blsp2_qup4_spi_apps_clk_src 0x25d4a2b1 +#define clk_blsp2_qup5_i2c_apps_clk_src 0xcc3698bd +#define clk_blsp2_qup5_spi_apps_clk_src 0xfa0cf45e +#define clk_blsp2_qup6_i2c_apps_clk_src 0x2fa53151 +#define clk_blsp2_qup6_spi_apps_clk_src 0x5ca86755 +#define clk_blsp2_uart1_apps_clk_src 0x562c66dc +#define clk_blsp2_uart2_apps_clk_src 0xdd448080 +#define clk_blsp2_uart3_apps_clk_src 0x46b2e90f +#define clk_gp1_clk_src 0xad85b97a +#define clk_gp2_clk_src 0xfb1f0065 +#define clk_gp3_clk_src 0x63b693d6 +#define clk_hmss_rbcpr_clk_src 0xedd9a474 +#define clk_pdm2_clk_src 0x31e494fd +#define clk_sdcc2_apps_clk_src 0xfc46c821 +#define clk_sdcc4_apps_clk_src 0x7aaaaa0c +#define clk_tsif_ref_clk_src 0x4e9042d1 +#define clk_ufs_ice_core_clk_src 0xda8e7119 +#define clk_ufs_phy_aux_clk_src 0xc6bca085 +#define clk_ufs_unipro_core_clk_src 0x179e80a9 +#define clk_usb30_mock_utmi_clk_src 0xa024a976 +#define clk_usb3_phy_aux_clk_src 0x15eec63c +#define clk_qspi_ref_clk_src 0xfe6b8e11 +#define clk_gcc_pcie_phy_0_reset 0x6bb4df33 +#define clk_gcc_usb3_phy_reset 0x03d559f1 +#define clk_gcc_usb3phy_phy_reset 0xb1a4f885 +#define clk_gcc_aggre1_ufs_axi_clk 0x873459d8 +#define clk_gcc_aggre1_ufs_axi_hw_ctl_clk 0x117a6f39 +#define clk_gcc_aggre1_usb3_axi_clk 0xc5c3fbe8 +#define clk_gcc_bimc_mss_q6_axi_clk 0x7437988f +#define clk_gcc_blsp1_ahb_clk 0x8caa5b4f +#define clk_gcc_blsp1_qup1_i2c_apps_clk 0xc303fae9 +#define clk_gcc_blsp1_qup1_spi_apps_clk 0x759a76b0 +#define clk_gcc_blsp1_qup2_i2c_apps_clk 0x1076f220 +#define clk_gcc_blsp1_qup2_spi_apps_clk 0x3e77d48f +#define clk_gcc_blsp1_qup3_i2c_apps_clk 0x9e25ac82 +#define clk_gcc_blsp1_qup3_spi_apps_clk 0xfb978880 +#define clk_gcc_blsp1_qup4_i2c_apps_clk 0xd7f40f6f +#define clk_gcc_blsp1_qup4_spi_apps_clk 0x80f8722f +#define clk_gcc_blsp1_qup5_i2c_apps_clk 0xacae5604 +#define clk_gcc_blsp1_qup5_spi_apps_clk 0xbf3e15d7 +#define clk_gcc_blsp1_qup6_i2c_apps_clk 0x5c6ad820 +#define clk_gcc_blsp1_qup6_spi_apps_clk 0x780d9f85 +#define clk_gcc_blsp1_uart1_apps_clk 0xc7c62f90 +#define clk_gcc_blsp1_uart2_apps_clk 0xf8a61c96 +#define clk_gcc_blsp1_uart3_apps_clk 0xc3298bd7 +#define clk_gcc_blsp2_ahb_clk 0x8f283c1d +#define clk_gcc_blsp2_qup1_i2c_apps_clk 0x9ace11dd +#define clk_gcc_blsp2_qup1_spi_apps_clk 0xa32604cc +#define clk_gcc_blsp2_qup2_i2c_apps_clk 0x1bf9a57e +#define clk_gcc_blsp2_qup2_spi_apps_clk 0xbf54ca6d +#define clk_gcc_blsp2_qup3_i2c_apps_clk 0x336d4170 +#define clk_gcc_blsp2_qup3_spi_apps_clk 0xc68509d6 +#define clk_gcc_blsp2_qup4_i2c_apps_clk 0xbd22539d +#define clk_gcc_blsp2_qup4_spi_apps_clk 0x01a72b93 +#define clk_gcc_blsp2_qup5_i2c_apps_clk 0xe2b2ce1d +#define clk_gcc_blsp2_qup5_spi_apps_clk 0xf40999cd +#define clk_gcc_blsp2_qup6_i2c_apps_clk 0x894bcea4 +#define clk_gcc_blsp2_qup6_spi_apps_clk 0xfe1bd34a +#define clk_gcc_blsp2_uart1_apps_clk 0x8c3512ff +#define clk_gcc_blsp2_uart2_apps_clk 0x1e1965a3 +#define clk_gcc_blsp2_uart3_apps_clk 0x382415ab +#define clk_gcc_boot_rom_ahb_clk 0xde2adeb1 +#define clk_gcc_bimc_gfx_clk 0x3edd69ad +#define clk_gcc_cfg_noc_usb3_axi_clk 0x9ea4c2d9 +#define clk_gcc_gp1_clk 0x057f7b69 +#define clk_gcc_gp2_clk 0x9bf83ffd +#define clk_gcc_gp3_clk 0xec6539ee +#define clk_gcc_gpu_bimc_gfx_clk 0x3909459b +#define clk_gcc_gpu_cfg_ahb_clk 0x72f20a57 +#define clk_gcc_gpu_iref_clk 0xfd82abad +#define clk_gcc_hmss_dvm_bus_clk 0x17cc8b53 +#define clk_gcc_hmss_rbcpr_clk 0x699183be +#define clk_hmss_gpll0_clk_src 0x17eb05d0 +#define clk_hmss_gpll4_clk_src 0x20456cae +#define clk_gcc_mmss_sys_noc_axi_clk 0x4467b15b +#define clk_gcc_mss_at_clk 0x1692c5aa +#define clk_nav_gcc_dbg_clk 0x2221c544 +#define clk_gcc_pcie_0_aux_clk 0x3d2e3ece +#define clk_gcc_pcie_0_cfg_ahb_clk 0x4dd325c3 +#define clk_gcc_pcie_0_mstr_axi_clk 0x3f85285b +#define clk_gcc_pcie_0_pipe_clk 0x4f37621e +#define clk_gcc_pcie_0_slv_axi_clk 0xd69638a1 +#define clk_gcc_pcie_phy_aux_clk 0x4746e74f +#define clk_gcc_pdm2_clk 0x99d55711 +#define clk_gcc_pdm_ahb_clk 0x365664f6 +#define clk_gcc_prng_ahb_clk 0x397e7eaa +#define clk_gcc_sdcc2_ahb_clk 0x23d5727f +#define clk_gcc_sdcc2_apps_clk 0x861b20ac +#define clk_gcc_sdcc4_ahb_clk 0x64f3e6a8 +#define clk_gcc_sdcc4_apps_clk 0xbf7c4dc8 +#define clk_gcc_tsif_ahb_clk 0x88d2822c +#define clk_gcc_tsif_ref_clk 0x8f1ed2c2 +#define clk_gcc_ufs_ahb_clk 0x1914bb84 +#define clk_gcc_ufs_axi_clk 0x47c743a7 +#define clk_gcc_ufs_axi_hw_ctl_clk 0x69385b45 +#define clk_gcc_ufs_ice_core_clk 0x310b0710 +#define clk_gcc_ufs_ice_core_hw_ctl_clk 0x84e15a5b +#define clk_gcc_ufs_phy_aux_clk 0x17acc8fb +#define clk_gcc_ufs_phy_aux_hw_ctl_clk 0x7dbdb2e2 +#define clk_gcc_ufs_rx_symbol_0_clk 0x7f43251c +#define clk_gcc_ufs_rx_symbol_1_clk 0x03182fde +#define clk_gcc_ufs_tx_symbol_0_clk 0x6a9f747a +#define clk_ufs_tx_symbol_0_clk 0xb3fcd0f7 +#define clk_ufs_rx_symbol_0_clk 0x17a0f1cd +#define clk_gcc_ufs_unipro_core_clk 0x2daf7fd2 +#define clk_gcc_ufs_unipro_core_hw_ctl_clk 0x4a4e0f3d +#define clk_gcc_usb30_master_clk 0xb3b4e2cb +#define clk_gcc_usb30_mock_utmi_clk 0xa800b65a +#define clk_gcc_usb30_sleep_clk 0xd0b65c92 +#define clk_gcc_usb3_phy_aux_clk 0x0d9a36e0 +#define clk_gcc_usb3_phy_pipe_clk 0xf279aff2 +#define clk_gcc_usb3_clkref_clk 0xb6cc8f00 +#define clk_gcc_hdmi_clkref_clk 0x4d4eec04 +#define clk_gcc_edp_clkref_clk 0xa8685c3f +#define clk_gcc_ufs_clkref_clk 0x92aa126f +#define clk_gcc_pcie_clkref_clk 0xa2e247fa +#define clk_gcc_rx2_qlink_clkref_clk 0xd0ba986d +#define clk_gcc_rx1_usb2_clkref_clk 0x53351d25 +#define clk_gcc_pcie_phy_reset 0x9bc3c959 +#define clk_gcc_pcie_phy_com_reset 0x8bf513e6 +#define clk_gcc_pcie_phy_nocsr_com_phy_reset 0x0c16a2da +#define clk_gcc_qusb2phy_prim_reset 0x07550fa1 +#define clk_gcc_qusb2phy_sec_reset 0x3f3a87d0 +#define clk_gcc_mmss_noc_cfg_ahb_clk 0xb41a9d99 +#define clk_gcc_dcc_ahb_clk 0xfa14a88c +#define clk_hlos1_vote_lpass_core_smmu_clk 0x3aaa1743 +#define clk_hlos1_vote_lpass_adsp_smmu_clk 0xc76f702f +#define clk_gcc_mss_cfg_ahb_clk 0x111cde81 +#define clk_gcc_mss_q6_bimc_axi_clk 0x67544d62 +#define clk_gcc_mss_mnoc_bimc_axi_clk 0xf665d03f +#define clk_gpll0_out_msscc 0x7d794829 +#define clk_gcc_mss_snoc_axi_clk 0x0e71de85 +#define clk_gcc_qspi_ref_clk 0x766a0f7c +#define clk_gcc_qspi_ahb_clk 0x96969dc8 +#define clk_gcc_debug_mux 0x8121ac15 + +/* clock_mmss controlled clocks */ +#define clk_mmsscc_xo 0x05e63704 +#define clk_mmsscc_gpll0 0xe900c515 +#define clk_mmsscc_gpll0_div 0x73892e05 +#define clk_mmpll0_pll 0x361e3cfd +#define clk_mmpll1_pll 0x198e426b +#define clk_mmpll3_pll 0x18c76899 +#define clk_mmpll4_pll 0x22c063c1 +#define clk_mmpll5_pll 0xa41e1936 +#define clk_mmpll6_pll 0xc56fb440 +#define clk_mmpll7_pll 0x3ac216af +#define clk_mmpll10_pll 0x2561263b +#define clk_mmpll0_pll_out 0x1e9e24a8 +#define clk_mmpll1_pll_out 0x5fa32257 +#define clk_mmpll3_pll_out 0x6eb6328f +#define clk_mmpll4_pll_out 0xfb21c2fd +#define clk_mmpll5_pll_out 0xcc1897bf +#define clk_mmpll6_pll_out 0xfb1060bd +#define clk_mmpll7_pll_out 0x767758ed +#define clk_mmpll10_pll_out 0x3c5668f3 +#define clk_ahb_clk_src 0x86f49203 +#define clk_csi0_clk_src 0x227e65bc +#define clk_vfe0_clk_src 0xa0c2bd8f +#define clk_vfe1_clk_src 0x4e357366 +#define clk_mdp_clk_src 0x6dc1f8f1 +#define clk_maxi_clk_src 0x52c09777 +#define clk_cpp_clk_src 0x8382f56d +#define clk_jpeg0_clk_src 0x9a0a0ac3 +#define clk_rot_clk_src 0xce49b56c +#define clk_video_core_clk_src 0x8be4c944 +#define clk_csi1_clk_src 0x6a2a6c36 +#define clk_csi2_clk_src 0x4113589f +#define clk_csi3_clk_src 0xfd934012 +#define clk_fd_core_clk_src 0xe4799ab7 +#define clk_ext_dp_phy_pll_vco 0x441b576b +#define clk_ext_dp_phy_pll_link 0xea12644c +#define clk_dp_link_clk_src 0x370d0626 +#define clk_dp_crypto_clk_src 0xf8faa811 +#define clk_dp_pixel_clk_src 0xf5dfbabf +#define clk_ext_extpclk_clk_src 0xe5b273af +#define clk_ext_pclk0_clk_src 0x087c1612 +#define clk_ext_pclk1_clk_src 0x8067c5a3 +#define clk_pclk0_clk_src 0xccac1f35 +#define clk_pclk1_clk_src 0x090f68ac +#define clk_video_subcore0_clk_src 0x88d79636 +#define clk_video_subcore1_clk_src 0x4966930c +#define clk_cci_clk_src 0x822f3d97 +#define clk_camss_gp0_clk_src 0x43b063e9 +#define clk_camss_gp1_clk_src 0xa3315f1b +#define clk_mclk0_clk_src 0x266b3853 +#define clk_mclk1_clk_src 0xa73cad0c +#define clk_mclk2_clk_src 0x42545468 +#define clk_mclk3_clk_src 0x2bfbb714 +#define clk_csiphy_clk_src 0x8cceb70a +#define clk_csi0phytimer_clk_src 0xc8a309be +#define clk_csi1phytimer_clk_src 0x7c0fe23a +#define clk_csi2phytimer_clk_src 0x62ffea9c +#define clk_ext_byte0_clk_src 0xfb32f31e +#define clk_ext_byte1_clk_src 0x585ef6d4 +#define clk_byte0_clk_src 0x75cc885b +#define clk_byte1_clk_src 0x63c2c955 +#define clk_dp_aux_clk_src 0x2b6e972b +#define clk_dp_gtc_clk_src 0xc5a86a42 +#define clk_esc0_clk_src 0xb41d7c38 +#define clk_esc1_clk_src 0x3b0afa42 +#define clk_extpclk_clk_src 0xb2c31abd +#define clk_hdmi_clk_src 0xb40aeea9 +#define clk_vsync_clk_src 0xecb43940 +#define clk_mmss_bimc_smmu_ahb_clk 0x4825baf4 +#define clk_mmss_bimc_smmu_axi_clk 0xc365ac39 +#define clk_mmss_snoc_dvm_axi_clk 0x2c159a11 +#define clk_mmss_camss_ahb_clk 0xa51f2c1d +#define clk_mmss_camss_cci_ahb_clk 0xfda8bb6a +#define clk_mmss_camss_cci_clk 0x71bb5c97 +#define clk_mmss_camss_cpp_ahb_clk 0xd5554f15 +#define clk_mmss_camss_cpp_clk 0x8e99ef57 +#define clk_mmss_camss_cpp_axi_clk 0xd84e390b +#define clk_mmss_camss_cpp_vbif_ahb_clk 0x1b33a88e +#define clk_mmss_camss_cphy_csid0_clk 0x56114361 +#define clk_mmss_camss_csi0_ahb_clk 0x2b58d241 +#define clk_mmss_camss_csi0_clk 0xccfe39ef +#define clk_mmss_camss_csi0pix_clk 0x9e26509d +#define clk_mmss_camss_csi0rdi_clk 0x01d5bf83 +#define clk_mmss_camss_cphy_csid1_clk 0x79fbcd8a +#define clk_mmss_camss_csi1_ahb_clk 0x7073244b +#define clk_mmss_camss_csi1_clk 0x3eeeaac0 +#define clk_mmss_camss_csi1pix_clk 0xf1375139 +#define clk_mmss_camss_csi1rdi_clk 0x43185024 +#define clk_mmss_camss_cphy_csid2_clk 0xf295e3ef +#define clk_mmss_camss_csi2_ahb_clk 0x681c1479 +#define clk_mmss_camss_csi2_clk 0x94524569 +#define clk_mmss_camss_csi2pix_clk 0xf4de617d +#define clk_mmss_camss_csi2rdi_clk 0x4bf01dc5 +#define clk_mmss_camss_cphy_csid3_clk 0x100188e9 +#define clk_mmss_camss_csi3_ahb_clk 0xfae7c29b +#define clk_mmss_camss_csi3_clk 0x55e4bbae +#define clk_mmss_camss_csi3pix_clk 0xc166a015 +#define clk_mmss_camss_csi3rdi_clk 0x6983a4cd +#define clk_mmss_camss_csi_vfe0_clk 0x3b30b798 +#define clk_mmss_camss_csi_vfe1_clk 0xfe729af7 +#define clk_mmss_camss_csiphy0_clk 0x96c81af8 +#define clk_mmss_camss_csiphy1_clk 0xee9ac2bb +#define clk_mmss_camss_csiphy2_clk 0x3365e70e +#define clk_mmss_fd_ahb_clk 0x4ff1da4d +#define clk_mmss_fd_core_clk 0x749e7eb0 +#define clk_mmss_fd_core_uar_clk 0x8ea480c5 +#define clk_mmss_camss_gp0_clk 0x3f7f6c87 +#define clk_mmss_camss_gp1_clk 0xdccdd730 +#define clk_mmss_camss_ispif_ahb_clk 0xbda4f0e3 +#define clk_mmss_camss_jpeg0_clk 0x4cc73b07 +#define clk_mmss_camss_jpeg0_vote_clk 0xc9efa6ac +#define clk_mmss_camss_jpeg0_dma_vote_clk 0x371ec109 +#define clk_mmss_camss_jpeg_ahb_clk 0xde1fece3 +#define clk_mmss_camss_jpeg_axi_clk 0x7534616b +#define clk_mmss_camss_mclk0_clk 0x056293a7 +#define clk_mmss_camss_mclk1_clk 0x96c7b69b +#define clk_mmss_camss_mclk2_clk 0x8820556e +#define clk_mmss_camss_mclk3_clk 0xf90ffb67 +#define clk_mmss_camss_micro_ahb_clk 0x6c6fd3c7 +#define clk_mmss_camss_csi0phytimer_clk 0x7a78864e +#define clk_mmss_camss_csi1phytimer_clk 0x6e6c1de5 +#define clk_mmss_camss_csi2phytimer_clk 0x0235e2de +#define clk_mmss_camss_top_ahb_clk 0x120618d6 +#define clk_mmss_camss_vfe0_ahb_clk 0x137bd0bd +#define clk_mmss_camss_vfe0_clk 0xead28288 +#define clk_mmss_camss_vfe0_stream_clk 0xa0428287 +#define clk_mmss_camss_vfe1_ahb_clk 0xac0154c0 +#define clk_mmss_camss_vfe1_clk 0xc216b14d +#define clk_mmss_camss_vfe1_stream_clk 0x745af3b6 +#define clk_mmss_camss_vfe_vbif_ahb_clk 0x0109a9c6 +#define clk_mmss_camss_vfe_vbif_axi_clk 0xe626d8a1 +#define clk_mmss_mdss_ahb_clk 0x85d37ab5 +#define clk_mmss_mdss_axi_clk 0xdf04fc1d +#define clk_mmss_mdss_byte0_clk 0x38105d25 +#define clk_mmss_mdss_byte0_intf_clk 0x38e5aa79 +#define clk_mmss_mdss_byte0_intf_div_clk 0x8604f181 +#define clk_mmss_mdss_byte1_clk 0xe0c21354 +#define clk_mmss_mdss_byte1_intf_clk 0xcf654d8e +#define clk_mmss_mdss_byte1_intf_div_clk 0xcdf334c5 +#define clk_mmss_mdss_dp_aux_clk 0x23125eb6 +#define clk_mmss_mdss_dp_crypto_clk 0x9a072d4e +#define clk_mmss_mdss_dp_link_clk 0x8dd302d1 +#define clk_mmss_mdss_dp_link_intf_clk 0x70e386e6 +#define clk_mmss_mdss_dp_pixel_clk 0xb707b765 +#define clk_mmss_mdss_dp_gtc_clk 0xb59c151a +#define clk_mmss_mdss_esc0_clk 0x5721ff83 +#define clk_mmss_mdss_esc1_clk 0xc3d0376b +#define clk_mmss_mdss_extpclk_clk 0x74d5a954 +#define clk_mmss_mdss_hdmi_clk 0x28460a6d +#define clk_mmss_mdss_hdmi_dp_ahb_clk 0x5448519f +#define clk_mmss_mdss_mdp_clk 0x43539b0e +#define clk_mmss_mdss_mdp_lut_clk 0x00627b2b +#define clk_mmss_mdss_pclk0_clk 0xcc0e909d +#define clk_mmss_mdss_pclk1_clk 0x850d9146 +#define clk_mmss_mdss_rot_clk 0xbb7e71c4 +#define clk_mmss_mdss_vsync_clk 0x629b36dc +#define clk_mmss_misc_ahb_clk 0xea30b0e7 +#define clk_mmss_misc_cxo_clk 0xe620cd80 +#define clk_mmss_mnoc_ahb_clk 0x49a394f4 +#define clk_mmss_mnoc_maxi_clk 0xd8b7278f +#define clk_mmss_video_subcore0_clk 0x23fae359 +#define clk_mmss_video_subcore1_clk 0x5213a0c7 +#define clk_mmss_video_ahb_clk 0x94334ae9 +#define clk_mmss_video_axi_clk 0xf3178ba5 +#define clk_mmss_video_core_clk 0x78f14c85 +#define clk_mmss_video_maxi_clk 0x1785ef88 +#define clk_mmss_vmem_ahb_clk 0x4b18955b +#define clk_mmss_vmem_maxi_clk 0xb6067889 +#define clk_mmss_debug_mux 0xe646ffda + +/* external multimedia clocks */ +#define clk_dsi0pll_byteclk_mux 0xecf2c434 +#define clk_dsi0pll_byteclk_src 0x6f6f740f +#define clk_dsi0pll_pclk_mux 0x6c9da335 +#define clk_dsi0pll_pclk_src 0x5efd85d4 +#define clk_dsi0pll_pclk_src_mux 0x84b14663 +#define clk_dsi0pll_post_bit_div 0xf46dcf27 +#define clk_dsi0pll_pll_out_div1 0xeda5b7fe +#define clk_dsi0pll_pll_out_div2 0x97fa476d +#define clk_dsi0pll_pll_out_div4 0x90a98ce0 +#define clk_dsi0pll_pll_out_div8 0x9d9d85cf +#define clk_dsi0pll_pll_out_mux 0x179c27ca +#define clk_dsi0pll_post_vco_mux 0xfaf9bd1f +#define clk_dsi0pll_post_vco_div1 0xabb50b2a +#define clk_dsi0pll_post_vco_div4 0xbe51c091 +#define clk_dsi0pll_bitclk_src 0x36c3c437 +#define clk_dsi0pll_vco_clk 0x15940d40 + +#define clk_dsi1pll_byteclk_mux 0x14e2f38f +#define clk_dsi1pll_byteclk_src 0x4b65c298 +#define clk_dsi1pll_pclk_mux 0x4c0518b5 +#define clk_dsi1pll_pclk_src 0xeddcd80e +#define clk_dsi1pll_pclk_src_mux 0x3651feb3 +#define clk_dsi1pll_post_bit_div 0x712f0260 +#define clk_dsi1pll_pll_out_div8 0x87628ddb +#define clk_dsi1pll_pll_out_div4 0x0d9a384b +#define clk_dsi1pll_pll_out_div2 0x0c9b5748 +#define clk_dsi1pll_pll_out_div1 0x3193164e +#define clk_dsi1pll_pll_out_mux 0x171bf8fd +#define clk_dsi1pll_post_vco_mux 0xc6a90d20 +#define clk_dsi1pll_post_vco_div1 0x6f47ca7d +#define clk_dsi1pll_post_vco_div4 0x90628974 +#define clk_dsi1pll_bitclk_src 0x13ab045b +#define clk_dsi1pll_vco_clk 0x99797b50 + +#define clk_dp_vco_clk 0xfcaaeec7 +#define clk_dp_link_2x_clk_divsel_five 0xcfe3f5dd +#define clk_vco_divsel_four_clk_src 0xe0da19c0 +#define clk_vco_divsel_two_clk_src 0xb5cfc6a8 +#define clk_vco_divided_clk_src_mux 0x3f8197c2 +#define clk_hdmi_vco_clk 0xbb7dc20d + +/* clock_gpu controlled clocks*/ +#define clk_gpucc_xo 0xc4e1a890 +#define clk_gpucc_gpll0 0x0db0e37f +#define clk_gfx3d_clk_src 0x917f76ef +#define clk_rbbmtimer_clk_src 0x17649ecc +#define clk_gfx3d_isense_clk_src 0xecc3eafa +#define clk_rbcpr_clk_src 0x2c2e9af2 +#define clk_gpu_debug_div_clk 0x75d6f53f +#define clk_gpucc_gfx3d_clk 0x95f01bd5 +#define clk_gpucc_rbbmtimer_clk 0x58a0a7ca +#define clk_gpucc_gfx3d_isense_clk 0xb2678e80 +#define clk_gpucc_cxo_clk 0x6532dcae +#define clk_gpucc_rbcpr_clk 0x7bd750e8 +#define clk_gpu_pll0_pll 0x0e61ab4d +#define clk_gpu_pll0_pll_out_even 0xb0ed5009 +#define clk_gpu_pll0_pll_out_odd 0x08c5a8a5 +#define clk_gpu_pll0_postdiv_clk 0x76c19f3c +#define clk_gpucc_mx_clk 0x1edbb879 +#define clk_gpucc_gcc_dbg_clk 0x9ae8cd3c +#define clk_gfxcc_dbg_clk 0x3ed47625 + +/* CPU clocks */ +#define clk_pwrcl_clk 0xc554130e +#define clk_perfcl_clk 0x58869997 +#define clk_sys_apcsaux_clk_gcc 0xf905e862 +#define clk_xo_ao 0x428c856d +#define clk_osm_clk_src 0xaabe68c3 +#define clk_cpu_debug_mux 0x3ae8bcb2 + +/* Audio External Clocks */ +#define clk_audio_ap_clk 0x9b5727cb +#define clk_audio_pmi_clk 0xcbfe416d +#define clk_audio_ap_clk2 0x454d1e91 + +/* GCC block resets */ +#define QUSB2PHY_PRIM_BCR 0 +#define QUSB2PHY_SEC_BCR 1 +#define BLSP1_BCR 2 +#define BLSP2_BCR 3 +#define BOOT_ROM_BCR 4 +#define PRNG_BCR 5 +#define UFS_BCR 6 +#define USB_30_BCR 7 +#define USB3_PHY_BCR 8 +#define USB3PHY_PHY_BCR 9 +#define PCIE_0_PHY_BCR 10 +#define PCIE_PHY_BCR 11 +#define PCIE_PHY_COM_BCR 12 +#define PCIE_PHY_NOCSR_COM_PHY_BCR 13 + +/* MMSS block resets */ +#define CAMSS_MICRO_BCR 0 + +#endif --- /dev/null 2019-10-24 16:47:25.704025805 +0200 +++ linux-4.4.115-fbx/arch/arm64/boot/dts/include/dt-bindings/clock/msm-clocks-hwio-8998.h 2019-01-22 16:16:28.171288678 +0100 @@ -0,0 +1,395 @@ +/* Copyright (c) 2015-2017, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define CLKFLAG_NO_RATE_CACHE 0x00004000 + +#define FMAX_LOWER 0 +#define FMAX_LOW 1 +#define FMAX_NOM 2 +#define FMAX_TURBO 3 + +#define HALT_CHECK_DELAY 5 + +#define RPM_MISC_CLK_TYPE 0x306b6c63 +#define RPM_BUS_CLK_TYPE 0x316b6c63 +#define RPM_MEM_CLK_TYPE 0x326b6c63 +#define RPM_IPA_CLK_TYPE 0x617069 +#define RPM_CE_CLK_TYPE 0x6563 +#define RPM_AGGR_CLK_TYPE 0x72676761 +#define RPM_SMD_KEY_ENABLE 0x62616E45 +#define RPM_MMAXI_CLK_TYPE 0x69786d6d + +#define CXO_CLK_SRC_ID 0x0 +#define QDSS_CLK_ID 0x1 +#define SNOC_CLK_ID 0x1 +#define CNOC_CLK_ID 0x2 +#define CNOC_PERIPH_CLK_ID 0x0 +#define BIMC_CLK_ID 0x0 +#define IPA_CLK_ID 0x0 +#define CE1_CLK_ID 0x0 +#define RF_CLK1_ID 0x4 +#define RF_CLK2_ID 0x5 +#define RF_CLK3_ID 0x6 +#define LN_BB_CLK1_ID 0x1 +#define LN_BB_CLK2_ID 0x2 +#define LN_BB_CLK3_ID 0x3 +#define DIV_CLK1_ID 0xb +#define DIV_CLK2_ID 0xc +#define DIV_CLK3_ID 0xd +#define RF_CLK1_PIN_ID 0x4 +#define RF_CLK2_PIN_ID 0x5 +#define RF_CLK3_PIN_ID 0x6 +#define LN_BB_CLK1_PIN_ID 0x1 +#define LN_BB_CLK2_PIN_ID 0x2 +#define LN_BB_CLK3_PIN_ID 0x3 +#define AGGR1_NOC_ID 0x1 +#define AGGR2_NOC_ID 0x2 +#define MMSSNOC_AXI_CLK_ID 0x0 + +#define APCS_COMMON_LMH_CMD_RCGR 0x0012C + +#define GCC_APCS_GPLL_ENA_VOTE 0x52000 +#define GCC_APCS_CLOCK_BRANCH_ENA_VOTE 0x52004 +#define GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1 0x5200C +#define PLLTEST_PAD_CFG 0x6200C +#define GCC_XO_DIV4_CBCR 0x43008 +#define CLOCK_FRQ_MEASURE_CTL 0x62004 +#define CLOCK_FRQ_MEASURE_STATUS 0x62008 +#define GCC_GPLL0_MODE 0x00000 +#define GCC_GPLL4_MODE 0x77000 +#define GCC_USB30_MASTER_CMD_RCGR 0x0F014 +#define GCC_PCIE_AUX_CMD_RCGR 0x6C000 +#define GCC_UFS_AXI_CMD_RCGR 0x75018 +#define GCC_BLSP1_QUP1_I2C_APPS_CMD_RCGR 0x19020 +#define GCC_BLSP1_QUP1_SPI_APPS_CMD_RCGR 0x1900C +#define GCC_BLSP1_QUP2_I2C_APPS_CMD_RCGR 0x1B020 +#define GCC_BLSP1_QUP2_SPI_APPS_CMD_RCGR 0x1B00C +#define GCC_BLSP1_QUP3_I2C_APPS_CMD_RCGR 0x1D020 +#define GCC_BLSP1_QUP3_SPI_APPS_CMD_RCGR 0x1D00C +#define GCC_BLSP1_QUP4_I2C_APPS_CMD_RCGR 0x1F020 +#define GCC_BLSP1_QUP4_SPI_APPS_CMD_RCGR 0x1F00C +#define GCC_BLSP1_QUP5_I2C_APPS_CMD_RCGR 0x21020 +#define GCC_BLSP1_QUP5_SPI_APPS_CMD_RCGR 0x2100C +#define GCC_BLSP1_QUP6_I2C_APPS_CMD_RCGR 0x23020 +#define GCC_BLSP1_QUP6_SPI_APPS_CMD_RCGR 0x2300C +#define GCC_BLSP1_UART1_APPS_CMD_RCGR 0x1A00C +#define GCC_BLSP1_UART2_APPS_CMD_RCGR 0x1C00C +#define GCC_BLSP1_UART3_APPS_CMD_RCGR 0x1E00C +#define GCC_BLSP2_QUP1_I2C_APPS_CMD_RCGR 0x26020 +#define GCC_BLSP2_QUP2_I2C_APPS_CMD_RCGR 0x28020 +#define GCC_BLSP2_QUP3_I2C_APPS_CMD_RCGR 0x2A020 +#define GCC_BLSP2_QUP4_I2C_APPS_CMD_RCGR 0x2C020 +#define GCC_BLSP2_QUP5_I2C_APPS_CMD_RCGR 0x2E020 +#define GCC_BLSP2_QUP6_I2C_APPS_CMD_RCGR 0x30020 +#define GCC_BLSP2_QUP1_SPI_APPS_CMD_RCGR 0x2600C +#define GCC_BLSP2_QUP2_SPI_APPS_CMD_RCGR 0x2800C +#define GCC_BLSP2_QUP3_SPI_APPS_CMD_RCGR 0x2A00C +#define GCC_BLSP2_QUP4_SPI_APPS_CMD_RCGR 0x2C00C +#define GCC_BLSP2_QUP5_SPI_APPS_CMD_RCGR 0x2E00C +#define GCC_BLSP2_QUP6_SPI_APPS_CMD_RCGR 0x3000C +#define GCC_BLSP2_UART1_APPS_CMD_RCGR 0x2700C +#define GCC_BLSP2_UART2_APPS_CMD_RCGR 0x2900C +#define GCC_BLSP2_UART3_APPS_CMD_RCGR 0x2B00C +#define GCC_GP1_CMD_RCGR 0x64004 +#define GCC_GP2_CMD_RCGR 0x65004 +#define GCC_GP3_CMD_RCGR 0x66004 +#define GCC_HMSS_RBCPR_CMD_RCGR 0x48044 +#define GCC_PDM2_CMD_RCGR 0x33010 +#define GCC_SDCC2_APPS_CMD_RCGR 0x14010 +#define GCC_SDCC4_APPS_CMD_RCGR 0x16010 +#define GCC_TSIF_REF_CMD_RCGR 0x36010 +#define GCC_UFS_ICE_CORE_CMD_RCGR 0x76010 +#define GCC_UFS_PHY_AUX_CMD_RCGR 0x76044 +#define GCC_UFS_UNIPRO_CORE_CMD_RCGR 0x76028 +#define GCC_USB30_MOCK_UTMI_CMD_RCGR 0x0F028 +#define GCC_USB3_PHY_AUX_CMD_RCGR 0x5000C +#define GCC_QSPI_REF_CMD_RCGR 0x9000C +#define GCC_PCIE_0_PHY_BCR 0x6C01C +#define GCC_HDMI_CLKREF_EN 0x88000 +#define GCC_UFS_CLKREF_EN 0x88004 +#define GCC_USB3_CLKREF_EN 0x88008 +#define GCC_PCIE_CLKREF_EN 0x8800C +#define GCC_RX1_USB2_CLKREF_EN 0x88014 +#define GCC_USB3_PHY_BCR 0x50020 +#define GCC_AGGRE1_NOC_XO_CBCR 0x8202C +#define GCC_AGGRE1_UFS_AXI_CBCR 0x82028 +#define GCC_AGGRE1_USB3_AXI_CBCR 0x82024 +#define GCC_BIMC_MSS_Q6_AXI_CBCR 0x4401C +#define GCC_BLSP1_AHB_CBCR 0x17004 +#define GCC_BLSP1_BCR 0x17000 +#define GCC_BLSP1_QUP1_SPI_APPS_CBCR 0x19004 +#define GCC_BLSP1_QUP1_I2C_APPS_CBCR 0x19008 +#define GCC_BLSP1_QUP2_SPI_APPS_CBCR 0x1B004 +#define GCC_BLSP1_QUP2_I2C_APPS_CBCR 0x1B008 +#define GCC_BLSP1_QUP3_SPI_APPS_CBCR 0x1D004 +#define GCC_BLSP1_QUP3_I2C_APPS_CBCR 0x1D008 +#define GCC_BLSP1_QUP4_SPI_APPS_CBCR 0x1F004 +#define GCC_BLSP1_QUP4_I2C_APPS_CBCR 0x1F008 +#define GCC_BLSP1_QUP5_SPI_APPS_CBCR 0x21004 +#define GCC_BLSP1_QUP5_I2C_APPS_CBCR 0x21008 +#define GCC_BLSP1_QUP6_SPI_APPS_CBCR 0x23004 +#define GCC_BLSP1_QUP6_I2C_APPS_CBCR 0x23008 +#define GCC_BLSP1_UART1_APPS_CBCR 0x1A004 +#define GCC_BLSP1_UART2_APPS_CBCR 0x1C004 +#define GCC_BLSP1_UART3_APPS_CBCR 0x1E004 +#define GCC_BLSP2_AHB_CBCR 0x25004 +#define GCC_BLSP2_BCR 0x25000 +#define GCC_BLSP2_QUP1_SPI_APPS_CBCR 0x26004 +#define GCC_BLSP2_QUP1_I2C_APPS_CBCR 0x26008 +#define GCC_BLSP2_QUP2_I2C_APPS_CBCR 0x28008 +#define GCC_BLSP2_QUP2_SPI_APPS_CBCR 0x28004 +#define GCC_BLSP2_QUP3_SPI_APPS_CBCR 0x2A004 +#define GCC_BLSP2_QUP3_I2C_APPS_CBCR 0x2A008 +#define GCC_BLSP2_QUP4_SPI_APPS_CBCR 0x2C004 +#define GCC_BLSP2_QUP4_I2C_APPS_CBCR 0x2C008 +#define GCC_BLSP2_QUP5_SPI_APPS_CBCR 0x2E004 +#define GCC_BLSP2_QUP5_I2C_APPS_CBCR 0x2E008 +#define GCC_BLSP2_QUP6_SPI_APPS_CBCR 0x30004 +#define GCC_BLSP2_QUP6_I2C_APPS_CBCR 0x30008 +#define GCC_BLSP2_UART1_APPS_CBCR 0x27004 +#define GCC_BLSP2_UART2_APPS_CBCR 0x29004 +#define GCC_BLSP2_UART3_APPS_CBCR 0x2B004 +#define GCC_BOOT_ROM_AHB_CBCR 0x38004 +#define GCC_BOOT_ROM_BCR 0x38000 +#define GCC_CFG_NOC_USB3_AXI_CBCR 0x05018 +#define GCC_BIMC_GFX_CBCR 0x46040 +#define GCC_GP1_CBCR 0x64000 +#define GCC_GP2_CBCR 0x65000 +#define GCC_GP3_CBCR 0x66000 +#define GCC_GPU_BIMC_GFX_CBCR 0x71010 +#define GCC_GPU_CFG_AHB_CBCR 0x71004 +#define GCC_GPU_IREF_EN 0x88010 +#define GCC_HMSS_DVM_BUS_CBCR 0x4808C +#define GCC_HMSS_RBCPR_CBCR 0x48008 +#define GCC_MMSS_SYS_NOC_AXI_CBCR 0x09000 +#define GCC_MMSS_NOC_CFG_AHB_CBCR 0x09004 +#define GCC_PCIE_0_SLV_AXI_CBCR 0x6B008 +#define GCC_PCIE_0_MSTR_AXI_CBCR 0x6B00C +#define GCC_PCIE_0_CFG_AHB_CBCR 0x6B010 +#define GCC_PCIE_0_AUX_CBCR 0x6B014 +#define GCC_PCIE_0_PIPE_CBCR 0x6B018 +#define GCC_PCIE_PHY_AUX_CBCR 0x6F004 +#define GCC_PCIE_PHY_BCR 0x6F000 +#define GCC_PCIE_PHY_COM_BCR 0x6F014 +#define GCC_PCIE_PHY_NOCSR_COM_PHY_BCR 0x6F00C +#define GCC_QUSB2PHY_PRIM_BCR 0x12000 +#define GCC_QUSB2PHY_SEC_BCR 0x12004 +#define GCC_PDM2_CBCR 0x3300C +#define GCC_PDM_AHB_CBCR 0x33004 +#define GCC_PRNG_AHB_CBCR 0x34004 +#define GCC_PRNG_BCR 0x34000 +#define GCC_SDCC2_APPS_CBCR 0x14004 +#define GCC_SDCC2_AHB_CBCR 0x14008 +#define GCC_SDCC4_APPS_CBCR 0x16004 +#define GCC_SDCC4_AHB_CBCR 0x16008 +#define GCC_TSIF_AHB_CBCR 0x36004 +#define GCC_TSIF_REF_CBCR 0x36008 +#define GCC_UFS_AXI_CBCR 0x75008 +#define GCC_UFS_BCR 0x75000 +#define GCC_UFS_AHB_CBCR 0x7500C +#define GCC_UFS_TX_SYMBOL_0_CBCR 0x75010 +#define GCC_UFS_RX_SYMBOL_0_CBCR 0x75014 +#define GCC_UFS_RX_SYMBOL_1_CBCR 0x7605C +#define GCC_UFS_UNIPRO_CORE_CBCR 0x76008 +#define GCC_UFS_ICE_CORE_CBCR 0x7600C +#define GCC_UFS_PHY_AUX_CBCR 0x76040 +#define GCC_USB30_MASTER_CBCR 0x0F008 +#define GCC_USB30_SLEEP_CBCR 0x0F00C +#define GCC_USB30_MOCK_UTMI_CBCR 0x0F010 +#define GCC_USB_30_BCR 0x0F000 +#define GCC_USB3_PHY_AUX_CBCR 0x50000 +#define GCC_USB3_PHY_PIPE_CBCR 0x50004 +#define GCC_USB3PHY_PHY_BCR 0x50024 +#define GCC_APCS_CLOCK_SLEEP_ENA_VOTE 0x52008 +#define GCC_MSS_CFG_AHB_CBCR 0x8A000 +#define GCC_MSS_Q6_BIMC_AXI_CBCR 0x8A040 +#define GCC_MSS_MNOC_BIMC_AXI_CBCR 0x8A004 +#define GCC_MSS_SNOC_AXI_CBCR 0x8A03C +#define GCC_HMSS_GPLL0_CMD_RCGR 0x4805C +#define GCC_MSS_CFG_AHB_CBCR 0x8A000 +#define GCC_MSS_Q6_BIMC_AXI_CBCR 0x8A040 +#define GCC_MSS_MNOC_BIMC_AXI_CBCR 0x8A004 +#define GCC_MSS_SNOC_AXI_CBCR 0x8A03C +#define GCC_DCC_AHB_CBCR 0x84004 +#define GCC_HLOS1_VOTE_LPASS_CORE_SMMU_CBCR 0x7D010 +#define GCC_HLOS1_VOTE_LPASS_ADSP_SMMU_CBCR 0x7D014 +#define GCC_QSPI_AHB_CBCR 0x90004 +#define GCC_QSPI_REF_CBCR 0x90008 +#define GCC_MMSS_MISC 0x0902C +#define GCC_GPU_MISC 0x71028 + +#define GPUCC_GPU_PLL0_PLL_MODE 0x00000 +#define GPUCC_GPU_PLL0_USER_CTL_MODE 0x0000C +#define GPUCC_GFX3D_CMD_RCGR 0x01070 +#define GPUCC_RBBMTIMER_CMD_RCGR 0x010B0 +#define GPUCC_GFX3D_ISENSE_CMD_RCGR 0x01100 +#define GPUCC_RBCPR_CMD_RCGR 0x01030 +#define GPUCC_GFX3D_CBCR 0x01098 +#define GPUCC_RBBMTIMER_CBCR 0x010D0 +#define GPUCC_GFX3D_ISENSE_CBCR 0x01124 +#define GPUCC_CXO_CBCR 0x01020 +#define GPUCC_RBCPR_CBCR 0x01054 +#define GPU_GX_BCR 0x01090 +#define GPUCC_GX_DOMAIN_MISC 0x00130 +#define GPUCC_GPU_DD_WRAP_CTRL 0x00430 +#define GPUCC_DEBUG_CLK_CTL 0x00120 + +#define MMSS_PLL_VOTE_APCS 0x001E0 +#define MMSS_MMPLL0_PLL_MODE 0x0C000 +#define MMSS_MMPLL1_PLL_MODE 0x0C050 +#define MMSS_MMPLL3_PLL_MODE 0x00000 +#define MMSS_MMPLL4_PLL_MODE 0x00050 +#define MMSS_MMPLL5_PLL_MODE 0x000A0 +#define MMSS_MMPLL6_PLL_MODE 0x000F0 +#define MMSS_MMPLL7_PLL_MODE 0x00140 +#define MMSS_MMPLL10_PLL_MODE 0x00190 +#define MMSS_AHB_CMD_RCGR 0x05000 +#define MMSS_CSI0_CMD_RCGR 0x03090 +#define MMSS_VFE0_CMD_RCGR 0x03600 +#define MMSS_VFE1_CMD_RCGR 0x03620 +#define MMSS_MDP_CMD_RCGR 0x02040 +#define MMSS_MAXI_CMD_RCGR 0x0F020 +#define MMSS_CPP_CMD_RCGR 0x03640 +#define MMSS_JPEG0_CMD_RCGR 0x03500 +#define MMSS_ROT_CMD_RCGR 0x021A0 +#define MMSS_VIDEO_CORE_CMD_RCGR 0x01000 +#define MMSS_CSI1_CMD_RCGR 0x03100 +#define MMSS_CSI2_CMD_RCGR 0x03160 +#define MMSS_CSI3_CMD_RCGR 0x031C0 +#define MMSS_FD_CORE_CMD_RCGR 0x03B00 +#define MMSS_BYTE0_CMD_RCGR 0x02120 +#define MMSS_BYTE1_CMD_RCGR 0x02140 +#define MMSS_PCLK0_CMD_RCGR 0x02000 +#define MMSS_PCLK1_CMD_RCGR 0x02020 +#define MMSS_VIDEO_SUBCORE0_CMD_RCGR 0x01060 +#define MMSS_VIDEO_SUBCORE1_CMD_RCGR 0x01080 +#define MMSS_CSIPHY_CMD_RCGR 0x03800 +#define MMSS_CCI_CMD_RCGR 0x03300 +#define MMSS_CAMSS_GP0_CMD_RCGR 0x03420 +#define MMSS_CAMSS_GP1_CMD_RCGR 0x03450 +#define MMSS_MCLK0_CMD_RCGR 0x03360 +#define MMSS_MCLK1_CMD_RCGR 0x03390 +#define MMSS_MCLK2_CMD_RCGR 0x033C0 +#define MMSS_MCLK3_CMD_RCGR 0x033F0 +#define MMSS_CAMSS_CSI2PHYTIMER_CBCR 0x03084 +#define MMSS_CSI0PHYTIMER_CMD_RCGR 0x03000 +#define MMSS_CSI1PHYTIMER_CMD_RCGR 0x03030 +#define MMSS_CSI2PHYTIMER_CMD_RCGR 0x03060 +#define MMSS_DP_GTC_CMD_RCGR 0x02280 +#define MMSS_ESC0_CMD_RCGR 0x02160 +#define MMSS_ESC1_CMD_RCGR 0x02180 +#define MMSS_EXTPCLK_CMD_RCGR 0x02060 +#define MMSS_HDMI_CMD_RCGR 0x02100 +#define MMSS_VSYNC_CMD_RCGR 0x02080 +#define MMSS_BIMC_SMMU_AHB_CBCR 0x0E004 +#define MMSS_BIMC_SMMU_AXI_CBCR 0x0E008 +#define MMSS_SNOC_DVM_AXI_CBCR 0x0E040 +#define MMSS_CAMSS_AHB_CBCR 0x0348C +#define MMSS_CAMSS_CCI_AHB_CBCR 0x03348 +#define MMSS_CAMSS_CCI_CBCR 0x03344 +#define MMSS_CAMSS_CPP_AHB_CBCR 0x036B4 +#define MMSS_CAMSS_CPP_CBCR 0x036B0 +#define MMSS_CAMSS_CPP_AXI_CBCR 0x036C4 +#define MMSS_CAMSS_CPP_VBIF_AHB_CBCR 0x036C8 +#define MMSS_CAMSS_CPHY_CSID0_CBCR 0x03730 +#define MMSS_CAMSS_CSI0_AHB_CBCR 0x030BC +#define MMSS_CAMSS_CSI0_CBCR 0x030B4 +#define MMSS_CAMSS_CSI0PIX_CBCR 0x030E4 +#define MMSS_CAMSS_CSI0RDI_CBCR 0x030D4 +#define MMSS_CAMSS_CPHY_CSID1_CBCR 0x03734 +#define MMSS_CAMSS_CSI1_AHB_CBCR 0x03128 +#define MMSS_CAMSS_CSI1_CBCR 0x03124 +#define MMSS_CAMSS_CSI1PIX_CBCR 0x03154 +#define MMSS_CAMSS_CSI1RDI_CBCR 0x03144 +#define MMSS_CAMSS_CPHY_CSID2_CBCR 0x03738 +#define MMSS_CAMSS_CSI2_AHB_CBCR 0x03188 +#define MMSS_CAMSS_CSI2_CBCR 0x03184 +#define MMSS_CAMSS_CSI2PIX_CBCR 0x031B4 +#define MMSS_CAMSS_CSI2RDI_CBCR 0x031A4 +#define MMSS_CAMSS_CPHY_CSID3_CBCR 0x0373C +#define MMSS_CAMSS_CSI3_AHB_CBCR 0x031E8 +#define MMSS_CAMSS_CSI3_CBCR 0x031E4 +#define MMSS_CAMSS_CSI3PIX_CBCR 0x03214 +#define MMSS_CAMSS_CSI3RDI_CBCR 0x03204 +#define MMSS_CAMSS_CSI_VFE0_CBCR 0x03704 +#define MMSS_CAMSS_CSI_VFE1_CBCR 0x03714 +#define MMSS_CAMSS_CSIPHY0_CBCR 0x03740 +#define MMSS_CAMSS_CSIPHY1_CBCR 0x03744 +#define MMSS_CAMSS_CSIPHY2_CBCR 0x03748 +#define MMSS_FD_AHB_CBCR 0x03B74 +#define MMSS_FD_CORE_CBCR 0x03B68 +#define MMSS_FD_CORE_UAR_CBCR 0x03B6C +#define MMSS_CAMSS_GP0_CBCR 0x03444 +#define MMSS_CAMSS_GP1_CBCR 0x03474 +#define MMSS_CAMSS_ISPIF_AHB_CBCR 0x03224 +#define MMSS_CAMSS_JPEG0_CBCR 0x035A8 +#define MMSS_CAMSS_JPEG_AHB_CBCR 0x035B4 +#define MMSS_CAMSS_JPEG_AXI_CBCR 0x035B8 +#define MMSS_CAMSS_MCLK0_CBCR 0x03384 +#define MMSS_CAMSS_MCLK1_CBCR 0x033B4 +#define MMSS_CAMSS_MCLK2_CBCR 0x033E4 +#define MMSS_CAMSS_MCLK3_CBCR 0x03414 +#define MMSS_CAMSS_MICRO_AHB_CBCR 0x03494 +#define MMSS_CAMSS_CSI0PHYTIMER_CBCR 0x03024 +#define MMSS_CAMSS_CSI1PHYTIMER_CBCR 0x03054 +#define MMSS_CSI2PHYTIMER_CMD_RCGR 0x03060 +#define MMSS_CAMSS_TOP_AHB_CBCR 0x03484 +#define MMSS_CAMSS_VFE0_AHB_CBCR 0x03668 +#define MMSS_CAMSS_VFE0_CBCR 0x036A8 +#define MMSS_CAMSS_VFE0_STREAM_CBCR 0x03720 +#define MMSS_CAMSS_VFE1_AHB_CBCR 0x03678 +#define MMSS_CAMSS_VFE1_CBCR 0x036AC +#define MMSS_CAMSS_VFE1_STREAM_CBCR 0x03724 +#define MMSS_CAMSS_VFE_VBIF_AHB_CBCR 0x036B8 +#define MMSS_CAMSS_VFE_VBIF_AXI_CBCR 0x036BC +#define MMSS_MDSS_AHB_CBCR 0x02308 +#define MMSS_MDSS_AXI_CBCR 0x02310 +#define MMSS_MDSS_BYTE0_CBCR 0x0233C +#define MMSS_MDSS_BYTE0_INTF_CBCR 0x02374 +#define MMSS_MDSS_BYTE0_INTF_DIV 0x0237C +#define MMSS_MDSS_BYTE1_CBCR 0x02340 +#define MMSS_MDSS_BYTE1_INTF_CBCR 0x02378 +#define MMSS_MDSS_BYTE1_INTF_DIV 0x02380 +#define MMSS_MDSS_DP_AUX_CBCR 0x02364 +#define MMSS_MDSS_DP_CRYPTO_CBCR 0x0235C +#define MMSS_MDSS_DP_GTC_CBCR 0x02368 +#define MMSS_MDSS_DP_LINK_CBCR 0x02354 +#define MMSS_MDSS_DP_LINK_INTF_CBCR 0x02358 +#define MMSS_MDSS_DP_PIXEL_CBCR 0x02360 +#define MMSS_MDSS_ESC0_CBCR 0x02344 +#define MMSS_MDSS_ESC1_CBCR 0x02348 +#define MMSS_MDSS_EXTPCLK_CBCR 0x02324 +#define MMSS_MDSS_HDMI_CBCR 0x02338 +#define MMSS_MDSS_HDMI_DP_AHB_CBCR 0x0230C +#define MMSS_MDSS_MDP_CBCR 0x0231C +#define MMSS_MDSS_MDP_LUT_CBCR 0x02320 +#define MMSS_MDSS_PCLK0_CBCR 0x02314 +#define MMSS_MDSS_PCLK1_CBCR 0x02318 +#define MMSS_MDSS_ROT_CBCR 0x02350 +#define MMSS_MDSS_VSYNC_CBCR 0x02328 +#define MMSS_MISC_AHB_CBCR 0x00328 +#define MMSS_MISC_CXO_CBCR 0x00324 +#define MMSS_MNOC_AHB_CBCR 0x05024 +#define MMSS_MNOC_MAXI_CBCR 0x0F004 +#define MMSS_VIDEO_SUBCORE0_CBCR 0x01048 +#define MMSS_VIDEO_SUBCORE1_CBCR 0x0104C +#define MMSS_VIDEO_AHB_CBCR 0x01030 +#define MMSS_VIDEO_AXI_CBCR 0x01034 +#define MMSS_VIDEO_CORE_CBCR 0x01028 +#define MMSS_VIDEO_MAXI_CBCR 0x01038 +#define MMSS_VMEM_AHB_CBCR 0x0F068 +#define MMSS_VMEM_MAXI_CBCR 0x0F064 +#define MMSS_DP_AUX_CMD_RCGR 0x02260 +#define MMSS_DP_CRYPTO_CMD_RCGR 0x02220 +#define MMSS_DP_LINK_CMD_RCGR 0x02200 +#define MMSS_DP_PIXEL_CMD_RCGR 0x02240 +#define MMSS_DEBUG_CLK_CTL 0x00900 diff -Nruw linux-4.4.115-fbx/arch/arm64/boot/dts/include/dt-bindings/msm./msm-bus-ids.h linux-4.4.115-fbx/arch/arm64/boot/dts/include/dt-bindings/msm/msm-bus-ids.h --- linux-4.4.115-fbx/arch/arm64/boot/dts/include/dt-bindings/msm./msm-bus-ids.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-4.4.115-fbx/arch/arm64/boot/dts/include/dt-bindings/msm/msm-bus-ids.h 2019-01-22 16:16:28.179288750 +0100 @@ -0,0 +1,887 @@ +/* Copyright (c) 2014-2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __MSM_BUS_IDS_H +#define __MSM_BUS_IDS_H + +/* Aggregation types */ +#define AGG_SCHEME_NONE 0 +#define AGG_SCHEME_LEG 1 +#define AGG_SCHEME_1 2 + +/* Topology related enums */ +#define MSM_BUS_FAB_DEFAULT 0 +#define MSM_BUS_FAB_APPSS 0 +#define MSM_BUS_FAB_SYSTEM 1024 +#define MSM_BUS_FAB_MMSS 2048 +#define MSM_BUS_FAB_SYSTEM_FPB 3072 +#define MSM_BUS_FAB_CPSS_FPB 4096 + +#define MSM_BUS_FAB_BIMC 0 +#define MSM_BUS_FAB_SYS_NOC 1024 +#define MSM_BUS_FAB_MMSS_NOC 2048 +#define MSM_BUS_FAB_OCMEM_NOC 3072 +#define MSM_BUS_FAB_PERIPH_NOC 4096 +#define MSM_BUS_FAB_CONFIG_NOC 5120 +#define MSM_BUS_FAB_OCMEM_VNOC 6144 +#define MSM_BUS_FAB_MMSS_AHB 2049 +#define MSM_BUS_FAB_A0_NOC 6145 +#define MSM_BUS_FAB_A1_NOC 6146 +#define MSM_BUS_FAB_A2_NOC 6147 +#define MSM_BUS_FAB_GNOC 6148 +#define MSM_BUS_FAB_CR_VIRT 6149 + +#define MSM_BUS_MASTER_FIRST 1 +#define MSM_BUS_MASTER_AMPSS_M0 1 +#define MSM_BUS_MASTER_AMPSS_M1 2 +#define MSM_BUS_APPSS_MASTER_FAB_MMSS 3 +#define MSM_BUS_APPSS_MASTER_FAB_SYSTEM 4 +#define MSM_BUS_SYSTEM_MASTER_FAB_APPSS 5 +#define MSM_BUS_MASTER_SPS 6 +#define MSM_BUS_MASTER_ADM_PORT0 7 +#define MSM_BUS_MASTER_ADM_PORT1 8 +#define MSM_BUS_SYSTEM_MASTER_ADM1_PORT0 9 +#define MSM_BUS_MASTER_ADM1_PORT1 10 +#define MSM_BUS_MASTER_LPASS_PROC 11 +#define MSM_BUS_MASTER_MSS_PROCI 12 +#define MSM_BUS_MASTER_MSS_PROCD 13 +#define MSM_BUS_MASTER_MSS_MDM_PORT0 14 +#define MSM_BUS_MASTER_LPASS 15 +#define MSM_BUS_SYSTEM_MASTER_CPSS_FPB 16 +#define MSM_BUS_SYSTEM_MASTER_SYSTEM_FPB 17 +#define MSM_BUS_SYSTEM_MASTER_MMSS_FPB 18 +#define MSM_BUS_MASTER_ADM1_CI 19 +#define MSM_BUS_MASTER_ADM0_CI 20 +#define MSM_BUS_MASTER_MSS_MDM_PORT1 21 +#define MSM_BUS_MASTER_MDP_PORT0 22 +#define MSM_BUS_MASTER_MDP_PORT1 23 +#define MSM_BUS_MMSS_MASTER_ADM1_PORT0 24 +#define MSM_BUS_MASTER_ROTATOR 25 +#define MSM_BUS_MASTER_GRAPHICS_3D 26 +#define MSM_BUS_MASTER_JPEG_DEC 27 +#define MSM_BUS_MASTER_GRAPHICS_2D_CORE0 28 +#define MSM_BUS_MASTER_VFE 29 +#define MSM_BUS_MASTER_VFE0 MSM_BUS_MASTER_VFE +#define MSM_BUS_MASTER_VPE 30 +#define MSM_BUS_MASTER_JPEG_ENC 31 +#define MSM_BUS_MASTER_GRAPHICS_2D_CORE1 32 +#define MSM_BUS_MMSS_MASTER_APPS_FAB 33 +#define MSM_BUS_MASTER_HD_CODEC_PORT0 34 +#define MSM_BUS_MASTER_HD_CODEC_PORT1 35 +#define MSM_BUS_MASTER_SPDM 36 +#define MSM_BUS_MASTER_RPM 37 +#define MSM_BUS_MASTER_MSS 38 +#define MSM_BUS_MASTER_RIVA 39 +#define MSM_BUS_MASTER_SNOC_VMEM 40 +#define MSM_BUS_MASTER_MSS_SW_PROC 41 +#define MSM_BUS_MASTER_MSS_FW_PROC 42 +#define MSM_BUS_MASTER_HMSS 43 +#define MSM_BUS_MASTER_GSS_NAV 44 +#define MSM_BUS_MASTER_PCIE 45 +#define MSM_BUS_MASTER_SATA 46 +#define MSM_BUS_MASTER_CRYPTO 47 +#define MSM_BUS_MASTER_VIDEO_CAP 48 +#define MSM_BUS_MASTER_GRAPHICS_3D_PORT1 49 +#define MSM_BUS_MASTER_VIDEO_ENC 50 +#define MSM_BUS_MASTER_VIDEO_DEC 51 +#define MSM_BUS_MASTER_LPASS_AHB 52 +#define MSM_BUS_MASTER_QDSS_BAM 53 +#define MSM_BUS_MASTER_SNOC_CFG 54 +#define MSM_BUS_MASTER_CRYPTO_CORE0 55 +#define MSM_BUS_MASTER_CRYPTO_CORE1 56 +#define MSM_BUS_MASTER_MSS_NAV 57 +#define MSM_BUS_MASTER_OCMEM_DMA 58 +#define MSM_BUS_MASTER_WCSS 59 +#define MSM_BUS_MASTER_QDSS_ETR 60 +#define MSM_BUS_MASTER_USB3 61 +#define MSM_BUS_MASTER_JPEG 62 +#define MSM_BUS_MASTER_VIDEO_P0 63 +#define MSM_BUS_MASTER_VIDEO_P1 64 +#define MSM_BUS_MASTER_MSS_PROC 65 +#define MSM_BUS_MASTER_JPEG_OCMEM 66 +#define MSM_BUS_MASTER_MDP_OCMEM 67 +#define MSM_BUS_MASTER_VIDEO_P0_OCMEM 68 +#define MSM_BUS_MASTER_VIDEO_P1_OCMEM 69 +#define MSM_BUS_MASTER_VFE_OCMEM 70 +#define MSM_BUS_MASTER_CNOC_ONOC_CFG 71 +#define MSM_BUS_MASTER_RPM_INST 72 +#define MSM_BUS_MASTER_RPM_DATA 73 +#define MSM_BUS_MASTER_RPM_SYS 74 +#define MSM_BUS_MASTER_DEHR 75 +#define MSM_BUS_MASTER_QDSS_DAP 76 +#define MSM_BUS_MASTER_TIC 77 +#define MSM_BUS_MASTER_SDCC_1 78 +#define MSM_BUS_MASTER_SDCC_3 79 +#define MSM_BUS_MASTER_SDCC_4 80 +#define MSM_BUS_MASTER_SDCC_2 81 +#define MSM_BUS_MASTER_TSIF 82 +#define MSM_BUS_MASTER_BAM_DMA 83 +#define MSM_BUS_MASTER_BLSP_2 84 +#define MSM_BUS_MASTER_USB_HSIC 85 +#define MSM_BUS_MASTER_BLSP_1 86 +#define MSM_BUS_MASTER_USB_HS 87 +#define MSM_BUS_MASTER_PNOC_CFG 88 +#define MSM_BUS_MASTER_V_OCMEM_GFX3D 89 +#define MSM_BUS_MASTER_IPA 90 +#define MSM_BUS_MASTER_QPIC 91 +#define MSM_BUS_MASTER_MDPE 92 +#define MSM_BUS_MASTER_USB_HS2 93 +#define MSM_BUS_MASTER_VPU 94 +#define MSM_BUS_MASTER_UFS 95 +#define MSM_BUS_MASTER_BCAST 96 +#define MSM_BUS_MASTER_CRYPTO_CORE2 97 +#define MSM_BUS_MASTER_EMAC 98 +#define MSM_BUS_MASTER_VPU_1 99 +#define MSM_BUS_MASTER_PCIE_1 100 +#define MSM_BUS_MASTER_USB3_1 101 +#define MSM_BUS_MASTER_CNOC_MNOC_MMSS_CFG 102 +#define MSM_BUS_MASTER_CNOC_MNOC_CFG 103 +#define MSM_BUS_MASTER_TCU_0 104 +#define MSM_BUS_MASTER_TCU_1 105 +#define MSM_BUS_MASTER_CPP 106 +#define MSM_BUS_MASTER_AUDIO 107 +#define MSM_BUS_MASTER_PCIE_2 108 +#define MSM_BUS_MASTER_VFE1 109 +#define MSM_BUS_MASTER_XM_USB_HS1 110 +#define MSM_BUS_MASTER_PCNOC_BIMC_1 111 +#define MSM_BUS_MASTER_BIMC_PCNOC 112 +#define MSM_BUS_MASTER_XI_USB_HSIC 113 +#define MSM_BUS_MASTER_SGMII 114 +#define MSM_BUS_SPMI_FETCHER 115 +#define MSM_BUS_MASTER_GNOC_BIMC 116 +#define MSM_BUS_MASTER_CRVIRT_A2NOC 117 +#define MSM_BUS_MASTER_CNOC_A2NOC 118 +#define MSM_BUS_MASTER_WLAN 119 +#define MSM_BUS_MASTER_MSS_CE 120 +#define MSM_BUS_MASTER_CDSP_PROC 121 +#define MSM_BUS_MASTER_GNOC_SNOC 122 +#define MSM_BUS_MASTER_PIMEM 123 +#define MSM_BUS_MASTER_MASTER_LAST 124 + +#define MSM_BUS_SYSTEM_FPB_MASTER_SYSTEM MSM_BUS_SYSTEM_MASTER_SYSTEM_FPB +#define MSM_BUS_CPSS_FPB_MASTER_SYSTEM MSM_BUS_SYSTEM_MASTER_CPSS_FPB + +#define MSM_BUS_SNOC_MM_INT_0 10000 +#define MSM_BUS_SNOC_MM_INT_1 10001 +#define MSM_BUS_SNOC_MM_INT_2 10002 +#define MSM_BUS_SNOC_MM_INT_BIMC 10003 +#define MSM_BUS_SNOC_INT_0 10004 +#define MSM_BUS_SNOC_INT_1 10005 +#define MSM_BUS_SNOC_INT_BIMC 10006 +#define MSM_BUS_SNOC_BIMC_0_MAS 10007 +#define MSM_BUS_SNOC_BIMC_1_MAS 10008 +#define MSM_BUS_SNOC_QDSS_INT 10009 +#define MSM_BUS_PNOC_SNOC_MAS 10010 +#define MSM_BUS_PNOC_SNOC_SLV 10011 +#define MSM_BUS_PNOC_INT_0 10012 +#define MSM_BUS_PNOC_INT_1 10013 +#define MSM_BUS_PNOC_M_0 10014 +#define MSM_BUS_PNOC_M_1 10015 +#define MSM_BUS_BIMC_SNOC_MAS 10016 +#define MSM_BUS_BIMC_SNOC_SLV 10017 +#define MSM_BUS_PNOC_SLV_0 10018 +#define MSM_BUS_PNOC_SLV_1 10019 +#define MSM_BUS_PNOC_SLV_2 10020 +#define MSM_BUS_PNOC_SLV_3 10021 +#define MSM_BUS_PNOC_SLV_4 10022 +#define MSM_BUS_PNOC_SLV_8 10023 +#define MSM_BUS_PNOC_SLV_9 10024 +#define MSM_BUS_SNOC_BIMC_0_SLV 10025 +#define MSM_BUS_SNOC_BIMC_1_SLV 10026 +#define MSM_BUS_MNOC_BIMC_MAS 10027 +#define MSM_BUS_MNOC_BIMC_SLV 10028 +#define MSM_BUS_BIMC_MNOC_MAS 10029 +#define MSM_BUS_BIMC_MNOC_SLV 10030 +#define MSM_BUS_SNOC_BIMC_MAS 10031 +#define MSM_BUS_SNOC_BIMC_SLV 10032 +#define MSM_BUS_CNOC_SNOC_MAS 10033 +#define MSM_BUS_CNOC_SNOC_SLV 10034 +#define MSM_BUS_SNOC_CNOC_MAS 10035 +#define MSM_BUS_SNOC_CNOC_SLV 10036 +#define MSM_BUS_OVNOC_SNOC_MAS 10037 +#define MSM_BUS_OVNOC_SNOC_SLV 10038 +#define MSM_BUS_SNOC_OVNOC_MAS 10039 +#define MSM_BUS_SNOC_OVNOC_SLV 10040 +#define MSM_BUS_SNOC_PNOC_MAS 10041 +#define MSM_BUS_SNOC_PNOC_SLV 10042 +#define MSM_BUS_BIMC_INT_APPS_EBI 10043 +#define MSM_BUS_BIMC_INT_APPS_SNOC 10044 +#define MSM_BUS_SNOC_BIMC_2_MAS 10045 +#define MSM_BUS_SNOC_BIMC_2_SLV 10046 +#define MSM_BUS_PNOC_SLV_5 10047 +#define MSM_BUS_PNOC_SLV_7 10048 +#define MSM_BUS_PNOC_INT_2 10049 +#define MSM_BUS_PNOC_INT_3 10050 +#define MSM_BUS_PNOC_INT_4 10051 +#define MSM_BUS_PNOC_INT_5 10052 +#define MSM_BUS_PNOC_INT_6 10053 +#define MSM_BUS_PNOC_INT_7 10054 +#define MSM_BUS_BIMC_SNOC_1_MAS 10055 +#define MSM_BUS_BIMC_SNOC_1_SLV 10056 +#define MSM_BUS_PNOC_A1NOC_MAS 10057 +#define MSM_BUS_PNOC_A1NOC_SLV 10058 +#define MSM_BUS_CNOC_A1NOC_MAS 10059 +#define MSM_BUS_A0NOC_SNOC_MAS 10060 +#define MSM_BUS_A0NOC_SNOC_SLV 10061 +#define MSM_BUS_A1NOC_SNOC_SLV 10062 +#define MSM_BUS_A1NOC_SNOC_MAS 10063 +#define MSM_BUS_A2NOC_SNOC_MAS 10064 +#define MSM_BUS_A2NOC_SNOC_SLV 10065 +#define MSM_BUS_SNOC_INT_2 10066 +#define MSM_BUS_A0NOC_QDSS_INT 10067 +#define MSM_BUS_INT_LAST 10068 + +#define MSM_BUS_INT_TEST_ID 20000 +#define MSM_BUS_INT_TEST_LAST 20050 + +#define MSM_BUS_SLAVE_FIRST 512 +#define MSM_BUS_SLAVE_EBI_CH0 512 +#define MSM_BUS_SLAVE_EBI_CH1 513 +#define MSM_BUS_SLAVE_AMPSS_L2 514 +#define MSM_BUS_APPSS_SLAVE_FAB_MMSS 515 +#define MSM_BUS_APPSS_SLAVE_FAB_SYSTEM 516 +#define MSM_BUS_SYSTEM_SLAVE_FAB_APPS 517 +#define MSM_BUS_SLAVE_SPS 518 +#define MSM_BUS_SLAVE_SYSTEM_IMEM 519 +#define MSM_BUS_SLAVE_AMPSS 520 +#define MSM_BUS_SLAVE_MSS 521 +#define MSM_BUS_SLAVE_LPASS 522 +#define MSM_BUS_SYSTEM_SLAVE_CPSS_FPB 523 +#define MSM_BUS_SYSTEM_SLAVE_SYSTEM_FPB 524 +#define MSM_BUS_SYSTEM_SLAVE_MMSS_FPB 525 +#define MSM_BUS_SLAVE_CORESIGHT 526 +#define MSM_BUS_SLAVE_RIVA 527 +#define MSM_BUS_SLAVE_SMI 528 +#define MSM_BUS_MMSS_SLAVE_FAB_APPS 529 +#define MSM_BUS_MMSS_SLAVE_FAB_APPS_1 530 +#define MSM_BUS_SLAVE_MM_IMEM 531 +#define MSM_BUS_SLAVE_CRYPTO 532 +#define MSM_BUS_SLAVE_SPDM 533 +#define MSM_BUS_SLAVE_RPM 534 +#define MSM_BUS_SLAVE_RPM_MSG_RAM 535 +#define MSM_BUS_SLAVE_MPM 536 +#define MSM_BUS_SLAVE_PMIC1_SSBI1_A 537 +#define MSM_BUS_SLAVE_PMIC1_SSBI1_B 538 +#define MSM_BUS_SLAVE_PMIC1_SSBI1_C 539 +#define MSM_BUS_SLAVE_PMIC2_SSBI2_A 540 +#define MSM_BUS_SLAVE_PMIC2_SSBI2_B 541 +#define MSM_BUS_SLAVE_GSBI1_UART 542 +#define MSM_BUS_SLAVE_GSBI2_UART 543 +#define MSM_BUS_SLAVE_GSBI3_UART 544 +#define MSM_BUS_SLAVE_GSBI4_UART 545 +#define MSM_BUS_SLAVE_GSBI5_UART 546 +#define MSM_BUS_SLAVE_GSBI6_UART 547 +#define MSM_BUS_SLAVE_GSBI7_UART 548 +#define MSM_BUS_SLAVE_GSBI8_UART 549 +#define MSM_BUS_SLAVE_GSBI9_UART 550 +#define MSM_BUS_SLAVE_GSBI10_UART 551 +#define MSM_BUS_SLAVE_GSBI11_UART 552 +#define MSM_BUS_SLAVE_GSBI12_UART 553 +#define MSM_BUS_SLAVE_GSBI1_QUP 554 +#define MSM_BUS_SLAVE_GSBI2_QUP 555 +#define MSM_BUS_SLAVE_GSBI3_QUP 556 +#define MSM_BUS_SLAVE_GSBI4_QUP 557 +#define MSM_BUS_SLAVE_GSBI5_QUP 558 +#define MSM_BUS_SLAVE_GSBI6_QUP 559 +#define MSM_BUS_SLAVE_GSBI7_QUP 560 +#define MSM_BUS_SLAVE_GSBI8_QUP 561 +#define MSM_BUS_SLAVE_GSBI9_QUP 562 +#define MSM_BUS_SLAVE_GSBI10_QUP 563 +#define MSM_BUS_SLAVE_GSBI11_QUP 564 +#define MSM_BUS_SLAVE_GSBI12_QUP 565 +#define MSM_BUS_SLAVE_EBI2_NAND 566 +#define MSM_BUS_SLAVE_EBI2_CS0 567 +#define MSM_BUS_SLAVE_EBI2_CS1 568 +#define MSM_BUS_SLAVE_EBI2_CS2 569 +#define MSM_BUS_SLAVE_EBI2_CS3 570 +#define MSM_BUS_SLAVE_EBI2_CS4 571 +#define MSM_BUS_SLAVE_EBI2_CS5 572 +#define MSM_BUS_SLAVE_USB_FS1 573 +#define MSM_BUS_SLAVE_USB_FS2 574 +#define MSM_BUS_SLAVE_TSIF 575 +#define MSM_BUS_SLAVE_MSM_TSSC 576 +#define MSM_BUS_SLAVE_MSM_PDM 577 +#define MSM_BUS_SLAVE_MSM_DIMEM 578 +#define MSM_BUS_SLAVE_MSM_TCSR 579 +#define MSM_BUS_SLAVE_MSM_PRNG 580 +#define MSM_BUS_SLAVE_GSS 581 +#define MSM_BUS_SLAVE_SATA 582 +#define MSM_BUS_SLAVE_USB3 583 +#define MSM_BUS_SLAVE_WCSS 584 +#define MSM_BUS_SLAVE_OCIMEM 585 +#define MSM_BUS_SLAVE_SNOC_OCMEM 586 +#define MSM_BUS_SLAVE_SERVICE_SNOC 587 +#define MSM_BUS_SLAVE_QDSS_STM 588 +#define MSM_BUS_SLAVE_CAMERA_CFG 589 +#define MSM_BUS_SLAVE_DISPLAY_CFG 590 +#define MSM_BUS_SLAVE_OCMEM_CFG 591 +#define MSM_BUS_SLAVE_CPR_CFG 592 +#define MSM_BUS_SLAVE_CPR_XPU_CFG 593 +#define MSM_BUS_SLAVE_MISC_CFG 594 +#define MSM_BUS_SLAVE_MISC_XPU_CFG 595 +#define MSM_BUS_SLAVE_VENUS_CFG 596 +#define MSM_BUS_SLAVE_MISC_VENUS_CFG 597 +#define MSM_BUS_SLAVE_GRAPHICS_3D_CFG 598 +#define MSM_BUS_SLAVE_MMSS_CLK_CFG 599 +#define MSM_BUS_SLAVE_MMSS_CLK_XPU_CFG 600 +#define MSM_BUS_SLAVE_MNOC_MPU_CFG 601 +#define MSM_BUS_SLAVE_ONOC_MPU_CFG 602 +#define MSM_BUS_SLAVE_SERVICE_MNOC 603 +#define MSM_BUS_SLAVE_OCMEM 604 +#define MSM_BUS_SLAVE_SERVICE_ONOC 605 +#define MSM_BUS_SLAVE_SDCC_1 606 +#define MSM_BUS_SLAVE_SDCC_3 607 +#define MSM_BUS_SLAVE_SDCC_2 608 +#define MSM_BUS_SLAVE_SDCC_4 609 +#define MSM_BUS_SLAVE_BAM_DMA 610 +#define MSM_BUS_SLAVE_BLSP_2 611 +#define MSM_BUS_SLAVE_USB_HSIC 612 +#define MSM_BUS_SLAVE_BLSP_1 613 +#define MSM_BUS_SLAVE_USB_HS 614 +#define MSM_BUS_SLAVE_PDM 615 +#define MSM_BUS_SLAVE_PERIPH_APU_CFG 616 +#define MSM_BUS_SLAVE_PNOC_MPU_CFG 617 +#define MSM_BUS_SLAVE_PRNG 618 +#define MSM_BUS_SLAVE_SERVICE_PNOC 619 +#define MSM_BUS_SLAVE_CLK_CTL 620 +#define MSM_BUS_SLAVE_CNOC_MSS 621 +#define MSM_BUS_SLAVE_SECURITY 622 +#define MSM_BUS_SLAVE_TCSR 623 +#define MSM_BUS_SLAVE_TLMM 624 +#define MSM_BUS_SLAVE_CRYPTO_0_CFG 625 +#define MSM_BUS_SLAVE_CRYPTO_1_CFG 626 +#define MSM_BUS_SLAVE_IMEM_CFG 627 +#define MSM_BUS_SLAVE_MESSAGE_RAM 628 +#define MSM_BUS_SLAVE_BIMC_CFG 629 +#define MSM_BUS_SLAVE_BOOT_ROM 630 +#define MSM_BUS_SLAVE_CNOC_MNOC_MMSS_CFG 631 +#define MSM_BUS_SLAVE_PMIC_ARB 632 +#define MSM_BUS_SLAVE_SPDM_WRAPPER 633 +#define MSM_BUS_SLAVE_DEHR_CFG 634 +#define MSM_BUS_SLAVE_QDSS_CFG 635 +#define MSM_BUS_SLAVE_RBCPR_CFG 636 +#define MSM_BUS_SLAVE_RBCPR_QDSS_APU_CFG 637 +#define MSM_BUS_SLAVE_SNOC_MPU_CFG 638 +#define MSM_BUS_SLAVE_CNOC_ONOC_CFG 639 +#define MSM_BUS_SLAVE_CNOC_MNOC_CFG 640 +#define MSM_BUS_SLAVE_PNOC_CFG 641 +#define MSM_BUS_SLAVE_SNOC_CFG 642 +#define MSM_BUS_SLAVE_EBI1_DLL_CFG 643 +#define MSM_BUS_SLAVE_PHY_APU_CFG 644 +#define MSM_BUS_SLAVE_EBI1_PHY_CFG 645 +#define MSM_BUS_SLAVE_SERVICE_CNOC 646 +#define MSM_BUS_SLAVE_IPS_CFG 647 +#define MSM_BUS_SLAVE_QPIC 648 +#define MSM_BUS_SLAVE_DSI_CFG 649 +#define MSM_BUS_SLAVE_UFS_CFG 650 +#define MSM_BUS_SLAVE_RBCPR_CX_CFG 651 +#define MSM_BUS_SLAVE_RBCPR_MX_CFG 652 +#define MSM_BUS_SLAVE_PCIE_CFG 653 +#define MSM_BUS_SLAVE_USB_PHYS_CFG 654 +#define MSM_BUS_SLAVE_VIDEO_CAP_CFG 655 +#define MSM_BUS_SLAVE_AVSYNC_CFG 656 +#define MSM_BUS_SLAVE_CRYPTO_2_CFG 657 +#define MSM_BUS_SLAVE_VPU_CFG 658 +#define MSM_BUS_SLAVE_BCAST_CFG 659 +#define MSM_BUS_SLAVE_KLM_CFG 660 +#define MSM_BUS_SLAVE_GENI_IR_CFG 661 +#define MSM_BUS_SLAVE_OCMEM_GFX 662 +#define MSM_BUS_SLAVE_CATS_128 663 +#define MSM_BUS_SLAVE_OCMEM_64 664 +#define MSM_BUS_SLAVE_PCIE_0 665 +#define MSM_BUS_SLAVE_PCIE_1 666 +#define MSM_BUS_SLAVE_PCIE_0_CFG 667 +#define MSM_BUS_SLAVE_PCIE_1_CFG 668 +#define MSM_BUS_SLAVE_SRVC_MNOC 669 +#define MSM_BUS_SLAVE_USB_HS2 670 +#define MSM_BUS_SLAVE_AUDIO 671 +#define MSM_BUS_SLAVE_TCU 672 +#define MSM_BUS_SLAVE_APPSS 673 +#define MSM_BUS_SLAVE_PCIE_PARF 674 +#define MSM_BUS_SLAVE_USB3_PHY_CFG 675 +#define MSM_BUS_SLAVE_IPA_CFG 676 +#define MSM_BUS_SLAVE_A0NOC_SNOC 677 +#define MSM_BUS_SLAVE_A1NOC_SNOC 678 +#define MSM_BUS_SLAVE_A2NOC_SNOC 679 +#define MSM_BUS_SLAVE_HMSS_L3 680 +#define MSM_BUS_SLAVE_PIMEM_CFG 681 +#define MSM_BUS_SLAVE_DCC_CFG 682 +#define MSM_BUS_SLAVE_QDSS_RBCPR_APU_CFG 683 +#define MSM_BUS_SLAVE_PCIE_2_CFG 684 +#define MSM_BUS_SLAVE_PCIE20_AHB2PHY 685 +#define MSM_BUS_SLAVE_A0NOC_CFG 686 +#define MSM_BUS_SLAVE_A1NOC_CFG 687 +#define MSM_BUS_SLAVE_A2NOC_CFG 688 +#define MSM_BUS_SLAVE_A1NOC_MPU_CFG 689 +#define MSM_BUS_SLAVE_A2NOC_MPU_CFG 690 +#define MSM_BUS_SLAVE_A0NOC_SMMU_CFG 691 +#define MSM_BUS_SLAVE_A1NOC_SMMU_CFG 692 +#define MSM_BUS_SLAVE_A2NOC_SMMU_CFG 693 +#define MSM_BUS_SLAVE_LPASS_SMMU_CFG 694 +#define MSM_BUS_SLAVE_MMAGIC_CFG 695 +#define MSM_BUS_SLAVE_VENUS_THROTTLE_CFG 696 +#define MSM_BUS_SLAVE_SSC_CFG 697 +#define MSM_BUS_SLAVE_DSA_CFG 698 +#define MSM_BUS_SLAVE_DSA_MPU_CFG 699 +#define MSM_BUS_SLAVE_DISPLAY_THROTTLE_CFG 700 +#define MSM_BUS_SLAVE_SMMU_CPP_CFG 701 +#define MSM_BUS_SLAVE_SMMU_JPEG_CFG 702 +#define MSM_BUS_SLAVE_SMMU_MDP_CFG 703 +#define MSM_BUS_SLAVE_SMMU_ROTATOR_CFG 704 +#define MSM_BUS_SLAVE_SMMU_VENUS_CFG 705 +#define MSM_BUS_SLAVE_SMMU_VFE_CFG 706 +#define MSM_BUS_SLAVE_A0NOC_MPU_CFG 707 +#define MSM_BUS_SLAVE_VMEM_CFG 708 +#define MSM_BUS_SLAVE_CAMERA_THROTTLE_CFG 709 +#define MSM_BUS_SLAVE_VMEM 710 +#define MSM_BUS_SLAVE_AHB2PHY 711 +#define MSM_BUS_SLAVE_PIMEM 712 +#define MSM_BUS_SLAVE_SNOC_VMEM 713 +#define MSM_BUS_SLAVE_PCIE_2 714 +#define MSM_BUS_SLAVE_RBCPR_MX 715 +#define MSM_BUS_SLAVE_RBCPR_CX 716 +#define MSM_BUS_SLAVE_BIMC_PCNOC 717 +#define MSM_BUS_SLAVE_PCNOC_BIMC_1 718 +#define MSM_BUS_SLAVE_SGMII 719 +#define MSM_BUS_SLAVE_SPMI_FETCHER 720 +#define MSM_BUS_PNOC_SLV_6 721 +#define MSM_BUS_SLAVE_MMSS_SMMU_CFG 722 +#define MSM_BUS_SLAVE_WLAN 723 +#define MSM_BUS_SLAVE_CRVIRT_A2NOC 724 +#define MSM_BUS_SLAVE_CNOC_A2NOC 725 +#define MSM_BUS_SLAVE_GLM 726 +#define MSM_BUS_SLAVE_GNOC_BIMC 727 +#define MSM_BUS_SLAVE_GNOC_SNOC 728 +#define MSM_BUS_SLAVE_QM_CFG 729 +#define MSM_BUS_SLAVE_TLMM_EAST 730 +#define MSM_BUS_SLAVE_TLMM_NORTH 731 +#define MSM_BUS_SLAVE_TLMM_WEST 732 +#define MSM_BUS_SLAVE_SKL 733 +#define MSM_BUS_SLAVE_LPASS_TCM 734 +#define MSM_BUS_SLAVE_TLMM_SOUTH 735 +#define MSM_BUS_SLAVE_TLMM_CENTER 736 +#define MSM_BUS_MSS_NAV_CE_MPU_CFG 737 +#define MSM_BUS_SLAVE_A2NOC_THROTTLE_CFG 738 +#define MSM_BUS_SLAVE_CDSP 739 +#define MSM_BUS_SLAVE_CDSP_SMMU_CFG 740 +#define MSM_BUS_SLAVE_LPASS_MPU_CFG 741 +#define MSM_BUS_SLAVE_CSI_PHY_CFG 742 +#define MSM_BUS_SLAVE_LAST 743 + +#define MSM_BUS_SYSTEM_FPB_SLAVE_SYSTEM MSM_BUS_SYSTEM_SLAVE_SYSTEM_FPB +#define MSM_BUS_CPSS_FPB_SLAVE_SYSTEM MSM_BUS_SYSTEM_SLAVE_CPSS_FPB + +/* + * ID's used in RPM messages + */ +#define ICBID_MASTER_APPSS_PROC 0 +#define ICBID_MASTER_MSS_PROC 1 +#define ICBID_MASTER_MNOC_BIMC 2 +#define ICBID_MASTER_SNOC_BIMC 3 +#define ICBID_MASTER_SNOC_BIMC_0 ICBID_MASTER_SNOC_BIMC +#define ICBID_MASTER_CNOC_MNOC_MMSS_CFG 4 +#define ICBID_MASTER_CNOC_MNOC_CFG 5 +#define ICBID_MASTER_GFX3D 6 +#define ICBID_MASTER_JPEG 7 +#define ICBID_MASTER_MDP 8 +#define ICBID_MASTER_MDP0 ICBID_MASTER_MDP +#define ICBID_MASTER_MDPS ICBID_MASTER_MDP +#define ICBID_MASTER_VIDEO 9 +#define ICBID_MASTER_VIDEO_P0 ICBID_MASTER_VIDEO +#define ICBID_MASTER_VIDEO_P1 10 +#define ICBID_MASTER_VFE 11 +#define ICBID_MASTER_VFE0 ICBID_MASTER_VFE +#define ICBID_MASTER_CNOC_ONOC_CFG 12 +#define ICBID_MASTER_JPEG_OCMEM 13 +#define ICBID_MASTER_MDP_OCMEM 14 +#define ICBID_MASTER_VIDEO_P0_OCMEM 15 +#define ICBID_MASTER_VIDEO_P1_OCMEM 16 +#define ICBID_MASTER_VFE_OCMEM 17 +#define ICBID_MASTER_LPASS_AHB 18 +#define ICBID_MASTER_QDSS_BAM 19 +#define ICBID_MASTER_SNOC_CFG 20 +#define ICBID_MASTER_BIMC_SNOC 21 +#define ICBID_MASTER_BIMC_SNOC_0 ICBID_MASTER_BIMC_SNOC +#define ICBID_MASTER_CNOC_SNOC 22 +#define ICBID_MASTER_CRYPTO 23 +#define ICBID_MASTER_CRYPTO_CORE0 ICBID_MASTER_CRYPTO +#define ICBID_MASTER_CRYPTO_CORE1 24 +#define ICBID_MASTER_LPASS_PROC 25 +#define ICBID_MASTER_MSS 26 +#define ICBID_MASTER_MSS_NAV 27 +#define ICBID_MASTER_OCMEM_DMA 28 +#define ICBID_MASTER_PNOC_SNOC 29 +#define ICBID_MASTER_WCSS 30 +#define ICBID_MASTER_QDSS_ETR 31 +#define ICBID_MASTER_USB3 32 +#define ICBID_MASTER_USB3_0 ICBID_MASTER_USB3 +#define ICBID_MASTER_SDCC_1 33 +#define ICBID_MASTER_SDCC_3 34 +#define ICBID_MASTER_SDCC_2 35 +#define ICBID_MASTER_SDCC_4 36 +#define ICBID_MASTER_TSIF 37 +#define ICBID_MASTER_BAM_DMA 38 +#define ICBID_MASTER_BLSP_2 39 +#define ICBID_MASTER_USB_HSIC 40 +#define ICBID_MASTER_BLSP_1 41 +#define ICBID_MASTER_USB_HS 42 +#define ICBID_MASTER_USB_HS1 ICBID_MASTER_USB_HS +#define ICBID_MASTER_PNOC_CFG 43 +#define ICBID_MASTER_SNOC_PNOC 44 +#define ICBID_MASTER_RPM_INST 45 +#define ICBID_MASTER_RPM_DATA 46 +#define ICBID_MASTER_RPM_SYS 47 +#define ICBID_MASTER_DEHR 48 +#define ICBID_MASTER_QDSS_DAP 49 +#define ICBID_MASTER_SPDM 50 +#define ICBID_MASTER_TIC 51 +#define ICBID_MASTER_SNOC_CNOC 52 +#define ICBID_MASTER_GFX3D_OCMEM 53 +#define ICBID_MASTER_GFX3D_GMEM ICBID_MASTER_GFX3D_OCMEM +#define ICBID_MASTER_OVIRT_SNOC 54 +#define ICBID_MASTER_SNOC_OVIRT 55 +#define ICBID_MASTER_SNOC_GVIRT ICBID_MASTER_SNOC_OVIRT +#define ICBID_MASTER_ONOC_OVIRT 56 +#define ICBID_MASTER_USB_HS2 57 +#define ICBID_MASTER_QPIC 58 +#define ICBID_MASTER_IPA 59 +#define ICBID_MASTER_DSI 60 +#define ICBID_MASTER_MDP1 61 +#define ICBID_MASTER_MDPE ICBID_MASTER_MDP1 +#define ICBID_MASTER_VPU_PROC 62 +#define ICBID_MASTER_VPU 63 +#define ICBID_MASTER_VPU0 ICBID_MASTER_VPU +#define ICBID_MASTER_CRYPTO_CORE2 64 +#define ICBID_MASTER_PCIE_0 65 +#define ICBID_MASTER_PCIE_1 66 +#define ICBID_MASTER_SATA 67 +#define ICBID_MASTER_UFS 68 +#define ICBID_MASTER_USB3_1 69 +#define ICBID_MASTER_VIDEO_OCMEM 70 +#define ICBID_MASTER_VPU1 71 +#define ICBID_MASTER_VCAP 72 +#define ICBID_MASTER_EMAC 73 +#define ICBID_MASTER_BCAST 74 +#define ICBID_MASTER_MMSS_PROC 75 +#define ICBID_MASTER_SNOC_BIMC_1 76 +#define ICBID_MASTER_SNOC_PCNOC 77 +#define ICBID_MASTER_AUDIO 78 +#define ICBID_MASTER_MM_INT_0 79 +#define ICBID_MASTER_MM_INT_1 80 +#define ICBID_MASTER_MM_INT_2 81 +#define ICBID_MASTER_MM_INT_BIMC 82 +#define ICBID_MASTER_MSS_INT 83 +#define ICBID_MASTER_PCNOC_CFG 84 +#define ICBID_MASTER_PCNOC_INT_0 85 +#define ICBID_MASTER_PCNOC_INT_1 86 +#define ICBID_MASTER_PCNOC_M_0 87 +#define ICBID_MASTER_PCNOC_M_1 88 +#define ICBID_MASTER_PCNOC_S_0 89 +#define ICBID_MASTER_PCNOC_S_1 90 +#define ICBID_MASTER_PCNOC_S_2 91 +#define ICBID_MASTER_PCNOC_S_3 92 +#define ICBID_MASTER_PCNOC_S_4 93 +#define ICBID_MASTER_PCNOC_S_6 94 +#define ICBID_MASTER_PCNOC_S_7 95 +#define ICBID_MASTER_PCNOC_S_8 96 +#define ICBID_MASTER_PCNOC_S_9 97 +#define ICBID_MASTER_QDSS_INT 98 +#define ICBID_MASTER_SNOC_INT_0 99 +#define ICBID_MASTER_SNOC_INT_1 100 +#define ICBID_MASTER_SNOC_INT_BIMC 101 +#define ICBID_MASTER_TCU_0 102 +#define ICBID_MASTER_TCU_1 103 +#define ICBID_MASTER_BIMC_INT_0 104 +#define ICBID_MASTER_BIMC_INT_1 105 +#define ICBID_MASTER_CAMERA 106 +#define ICBID_MASTER_RICA 107 +#define ICBID_MASTER_SNOC_BIMC_2 108 +#define ICBID_MASTER_BIMC_SNOC_1 109 +#define ICBID_MASTER_A0NOC_SNOC 110 +#define ICBID_MASTER_A1NOC_SNOC 111 +#define ICBID_MASTER_A2NOC_SNOC 112 +#define ICBID_MASTER_PIMEM 113 +#define ICBID_MASTER_SNOC_VMEM 114 +#define ICBID_MASTER_CPP 115 +#define ICBID_MASTER_CNOC_A1NOC 116 +#define ICBID_MASTER_PNOC_A1NOC 117 +#define ICBID_MASTER_HMSS 118 +#define ICBID_MASTER_PCIE_2 119 +#define ICBID_MASTER_ROTATOR 120 +#define ICBID_MASTER_VENUS_VMEM 121 +#define ICBID_MASTER_DCC 122 +#define ICBID_MASTER_MCDMA 123 +#define ICBID_MASTER_PCNOC_INT_2 124 +#define ICBID_MASTER_PCNOC_INT_3 125 +#define ICBID_MASTER_PCNOC_INT_4 126 +#define ICBID_MASTER_PCNOC_INT_5 127 +#define ICBID_MASTER_PCNOC_INT_6 128 +#define ICBID_MASTER_PCNOC_S_5 129 +#define ICBID_MASTER_SENSORS_AHB 130 +#define ICBID_MASTER_SENSORS_PROC 131 +#define ICBID_MASTER_QSPI 132 +#define ICBID_MASTER_VFE1 133 +#define ICBID_MASTER_SNOC_INT_2 134 +#define ICBID_MASTER_SMMNOC_BIMC 135 +#define ICBID_MASTER_CRVIRT_A1NOC 136 +#define ICBID_MASTER_XM_USB_HS1 137 +#define ICBID_MASTER_XI_USB_HS1 138 +#define ICBID_MASTER_PCNOC_BIMC_1 139 +#define ICBID_MASTER_BIMC_PCNOC 140 +#define ICBID_MASTER_XI_HSIC 141 +#define ICBID_MASTER_SGMII 142 +#define ICBID_MASTER_SPMI_FETCHER 143 +#define ICBID_MASTER_GNOC_BIMC 144 +#define ICBID_MASTER_CRVIRT_A2NOC 145 +#define ICBID_MASTER_CNOC_A2NOC 146 +#define ICBID_MASTER_WLAN 147 +#define ICBID_MASTER_MSS_CE 148 +#define ICBID_MASTER_CDSP_PROC 149 +#define ICBID_MASTER_GNOC_SNOC 150 + +#define ICBID_SLAVE_EBI1 0 +#define ICBID_SLAVE_APPSS_L2 1 +#define ICBID_SLAVE_BIMC_SNOC 2 +#define ICBID_SLAVE_BIMC_SNOC_0 ICBID_SLAVE_BIMC_SNOC +#define ICBID_SLAVE_CAMERA_CFG 3 +#define ICBID_SLAVE_DISPLAY_CFG 4 +#define ICBID_SLAVE_OCMEM_CFG 5 +#define ICBID_SLAVE_CPR_CFG 6 +#define ICBID_SLAVE_CPR_XPU_CFG 7 +#define ICBID_SLAVE_MISC_CFG 8 +#define ICBID_SLAVE_MISC_XPU_CFG 9 +#define ICBID_SLAVE_VENUS_CFG 10 +#define ICBID_SLAVE_GFX3D_CFG 11 +#define ICBID_SLAVE_MMSS_CLK_CFG 12 +#define ICBID_SLAVE_MMSS_CLK_XPU_CFG 13 +#define ICBID_SLAVE_MNOC_MPU_CFG 14 +#define ICBID_SLAVE_ONOC_MPU_CFG 15 +#define ICBID_SLAVE_MNOC_BIMC 16 +#define ICBID_SLAVE_SERVICE_MNOC 17 +#define ICBID_SLAVE_OCMEM 18 +#define ICBID_SLAVE_GMEM ICBID_SLAVE_OCMEM +#define ICBID_SLAVE_SERVICE_ONOC 19 +#define ICBID_SLAVE_APPSS 20 +#define ICBID_SLAVE_LPASS 21 +#define ICBID_SLAVE_USB3 22 +#define ICBID_SLAVE_USB3_0 ICBID_SLAVE_USB3 +#define ICBID_SLAVE_WCSS 23 +#define ICBID_SLAVE_SNOC_BIMC 24 +#define ICBID_SLAVE_SNOC_BIMC_0 ICBID_SLAVE_SNOC_BIMC +#define ICBID_SLAVE_SNOC_CNOC 25 +#define ICBID_SLAVE_IMEM 26 +#define ICBID_SLAVE_OCIMEM ICBID_SLAVE_IMEM +#define ICBID_SLAVE_SNOC_OVIRT 27 +#define ICBID_SLAVE_SNOC_GVIRT ICBID_SLAVE_SNOC_OVIRT +#define ICBID_SLAVE_SNOC_PNOC 28 +#define ICBID_SLAVE_SNOC_PCNOC ICBID_SLAVE_SNOC_PNOC +#define ICBID_SLAVE_SERVICE_SNOC 29 +#define ICBID_SLAVE_QDSS_STM 30 +#define ICBID_SLAVE_SDCC_1 31 +#define ICBID_SLAVE_SDCC_3 32 +#define ICBID_SLAVE_SDCC_2 33 +#define ICBID_SLAVE_SDCC_4 34 +#define ICBID_SLAVE_TSIF 35 +#define ICBID_SLAVE_BAM_DMA 36 +#define ICBID_SLAVE_BLSP_2 37 +#define ICBID_SLAVE_USB_HSIC 38 +#define ICBID_SLAVE_BLSP_1 39 +#define ICBID_SLAVE_USB_HS 40 +#define ICBID_SLAVE_USB_HS1 ICBID_SLAVE_USB_HS +#define ICBID_SLAVE_PDM 41 +#define ICBID_SLAVE_PERIPH_APU_CFG 42 +#define ICBID_SLAVE_PNOC_MPU_CFG 43 +#define ICBID_SLAVE_PRNG 44 +#define ICBID_SLAVE_PNOC_SNOC 45 +#define ICBID_SLAVE_PCNOC_SNOC ICBID_SLAVE_PNOC_SNOC +#define ICBID_SLAVE_SERVICE_PNOC 46 +#define ICBID_SLAVE_CLK_CTL 47 +#define ICBID_SLAVE_CNOC_MSS 48 +#define ICBID_SLAVE_PCNOC_MSS ICBID_SLAVE_CNOC_MSS +#define ICBID_SLAVE_SECURITY 49 +#define ICBID_SLAVE_TCSR 50 +#define ICBID_SLAVE_TLMM 51 +#define ICBID_SLAVE_CRYPTO_0_CFG 52 +#define ICBID_SLAVE_CRYPTO_1_CFG 53 +#define ICBID_SLAVE_IMEM_CFG 54 +#define ICBID_SLAVE_MESSAGE_RAM 55 +#define ICBID_SLAVE_BIMC_CFG 56 +#define ICBID_SLAVE_BOOT_ROM 57 +#define ICBID_SLAVE_CNOC_MNOC_MMSS_CFG 58 +#define ICBID_SLAVE_PMIC_ARB 59 +#define ICBID_SLAVE_SPDM_WRAPPER 60 +#define ICBID_SLAVE_DEHR_CFG 61 +#define ICBID_SLAVE_MPM 62 +#define ICBID_SLAVE_QDSS_CFG 63 +#define ICBID_SLAVE_RBCPR_CFG 64 +#define ICBID_SLAVE_RBCPR_CX_CFG ICBID_SLAVE_RBCPR_CFG +#define ICBID_SLAVE_RBCPR_QDSS_APU_CFG 65 +#define ICBID_SLAVE_CNOC_MNOC_CFG 66 +#define ICBID_SLAVE_SNOC_MPU_CFG 67 +#define ICBID_SLAVE_CNOC_ONOC_CFG 68 +#define ICBID_SLAVE_PNOC_CFG 69 +#define ICBID_SLAVE_SNOC_CFG 70 +#define ICBID_SLAVE_EBI1_DLL_CFG 71 +#define ICBID_SLAVE_PHY_APU_CFG 72 +#define ICBID_SLAVE_EBI1_PHY_CFG 73 +#define ICBID_SLAVE_RPM 74 +#define ICBID_SLAVE_CNOC_SNOC 75 +#define ICBID_SLAVE_SERVICE_CNOC 76 +#define ICBID_SLAVE_OVIRT_SNOC 77 +#define ICBID_SLAVE_OVIRT_OCMEM 78 +#define ICBID_SLAVE_USB_HS2 79 +#define ICBID_SLAVE_QPIC 80 +#define ICBID_SLAVE_IPS_CFG 81 +#define ICBID_SLAVE_DSI_CFG 82 +#define ICBID_SLAVE_USB3_1 83 +#define ICBID_SLAVE_PCIE_0 84 +#define ICBID_SLAVE_PCIE_1 85 +#define ICBID_SLAVE_PSS_SMMU_CFG 86 +#define ICBID_SLAVE_CRYPTO_2_CFG 87 +#define ICBID_SLAVE_PCIE_0_CFG 88 +#define ICBID_SLAVE_PCIE_1_CFG 89 +#define ICBID_SLAVE_SATA_CFG 90 +#define ICBID_SLAVE_SPSS_GENI_IR 91 +#define ICBID_SLAVE_UFS_CFG 92 +#define ICBID_SLAVE_AVSYNC_CFG 93 +#define ICBID_SLAVE_VPU_CFG 94 +#define ICBID_SLAVE_USB_PHY_CFG 95 +#define ICBID_SLAVE_RBCPR_MX_CFG 96 +#define ICBID_SLAVE_PCIE_PARF 97 +#define ICBID_SLAVE_VCAP_CFG 98 +#define ICBID_SLAVE_EMAC_CFG 99 +#define ICBID_SLAVE_BCAST_CFG 100 +#define ICBID_SLAVE_KLM_CFG 101 +#define ICBID_SLAVE_DISPLAY_PWM 102 +#define ICBID_SLAVE_GENI 103 +#define ICBID_SLAVE_SNOC_BIMC_1 104 +#define ICBID_SLAVE_AUDIO 105 +#define ICBID_SLAVE_CATS_0 106 +#define ICBID_SLAVE_CATS_1 107 +#define ICBID_SLAVE_MM_INT_0 108 +#define ICBID_SLAVE_MM_INT_1 109 +#define ICBID_SLAVE_MM_INT_2 110 +#define ICBID_SLAVE_MM_INT_BIMC 111 +#define ICBID_SLAVE_MMU_MODEM_XPU_CFG 112 +#define ICBID_SLAVE_MSS_INT 113 +#define ICBID_SLAVE_PCNOC_INT_0 114 +#define ICBID_SLAVE_PCNOC_INT_1 115 +#define ICBID_SLAVE_PCNOC_M_0 116 +#define ICBID_SLAVE_PCNOC_M_1 117 +#define ICBID_SLAVE_PCNOC_S_0 118 +#define ICBID_SLAVE_PCNOC_S_1 119 +#define ICBID_SLAVE_PCNOC_S_2 120 +#define ICBID_SLAVE_PCNOC_S_3 121 +#define ICBID_SLAVE_PCNOC_S_4 122 +#define ICBID_SLAVE_PCNOC_S_6 123 +#define ICBID_SLAVE_PCNOC_S_7 124 +#define ICBID_SLAVE_PCNOC_S_8 125 +#define ICBID_SLAVE_PCNOC_S_9 126 +#define ICBID_SLAVE_PRNG_XPU_CFG 127 +#define ICBID_SLAVE_QDSS_INT 128 +#define ICBID_SLAVE_RPM_XPU_CFG 129 +#define ICBID_SLAVE_SNOC_INT_0 130 +#define ICBID_SLAVE_SNOC_INT_1 131 +#define ICBID_SLAVE_SNOC_INT_BIMC 132 +#define ICBID_SLAVE_TCU 133 +#define ICBID_SLAVE_BIMC_INT_0 134 +#define ICBID_SLAVE_BIMC_INT_1 135 +#define ICBID_SLAVE_RICA_CFG 136 +#define ICBID_SLAVE_SNOC_BIMC_2 137 +#define ICBID_SLAVE_BIMC_SNOC_1 138 +#define ICBID_SLAVE_PNOC_A1NOC 139 +#define ICBID_SLAVE_SNOC_VMEM 140 +#define ICBID_SLAVE_A0NOC_SNOC 141 +#define ICBID_SLAVE_A1NOC_SNOC 142 +#define ICBID_SLAVE_A2NOC_SNOC 143 +#define ICBID_SLAVE_A0NOC_CFG 144 +#define ICBID_SLAVE_A0NOC_MPU_CFG 145 +#define ICBID_SLAVE_A0NOC_SMMU_CFG 146 +#define ICBID_SLAVE_A1NOC_CFG 147 +#define ICBID_SLAVE_A1NOC_MPU_CFG 148 +#define ICBID_SLAVE_A1NOC_SMMU_CFG 149 +#define ICBID_SLAVE_A2NOC_CFG 150 +#define ICBID_SLAVE_A2NOC_MPU_CFG 151 +#define ICBID_SLAVE_A2NOC_SMMU_CFG 152 +#define ICBID_SLAVE_AHB2PHY 153 +#define ICBID_SLAVE_CAMERA_THROTTLE_CFG 154 +#define ICBID_SLAVE_DCC_CFG 155 +#define ICBID_SLAVE_DISPLAY_THROTTLE_CFG 156 +#define ICBID_SLAVE_DSA_CFG 157 +#define ICBID_SLAVE_DSA_MPU_CFG 158 +#define ICBID_SLAVE_SSC_MPU_CFG 159 +#define ICBID_SLAVE_HMSS_L3 160 +#define ICBID_SLAVE_LPASS_SMMU_CFG 161 +#define ICBID_SLAVE_MMAGIC_CFG 162 +#define ICBID_SLAVE_PCIE20_AHB2PHY 163 +#define ICBID_SLAVE_PCIE_2 164 +#define ICBID_SLAVE_PCIE_2_CFG 165 +#define ICBID_SLAVE_PIMEM 166 +#define ICBID_SLAVE_PIMEM_CFG 167 +#define ICBID_SLAVE_QDSS_RBCPR_APU_CFG 168 +#define ICBID_SLAVE_RBCPR_CX 169 +#define ICBID_SLAVE_RBCPR_MX 170 +#define ICBID_SLAVE_SMMU_CPP_CFG 171 +#define ICBID_SLAVE_SMMU_JPEG_CFG 172 +#define ICBID_SLAVE_SMMU_MDP_CFG 173 +#define ICBID_SLAVE_SMMU_ROTATOR_CFG 174 +#define ICBID_SLAVE_SMMU_VENUS_CFG 175 +#define ICBID_SLAVE_SMMU_VFE_CFG 176 +#define ICBID_SLAVE_SSC_CFG 177 +#define ICBID_SLAVE_VENUS_THROTTLE_CFG 178 +#define ICBID_SLAVE_VMEM 179 +#define ICBID_SLAVE_VMEM_CFG 180 +#define ICBID_SLAVE_QDSS_MPU_CFG 181 +#define ICBID_SLAVE_USB3_PHY_CFG 182 +#define ICBID_SLAVE_IPA_CFG 183 +#define ICBID_SLAVE_PCNOC_INT_2 184 +#define ICBID_SLAVE_PCNOC_INT_3 185 +#define ICBID_SLAVE_PCNOC_INT_4 186 +#define ICBID_SLAVE_PCNOC_INT_5 187 +#define ICBID_SLAVE_PCNOC_INT_6 188 +#define ICBID_SLAVE_PCNOC_S_5 189 +#define ICBID_SLAVE_QSPI 190 +#define ICBID_SLAVE_A1NOC_MS_MPU_CFG 191 +#define ICBID_SLAVE_A2NOC_MS_MPU_CFG 192 +#define ICBID_SLAVE_MODEM_Q6_SMMU_CFG 193 +#define ICBID_SLAVE_MSS_MPU_CFG 194 +#define ICBID_SLAVE_MSS_PROC_MS_MPU_CFG 195 +#define ICBID_SLAVE_SKL 196 +#define ICBID_SLAVE_SNOC_INT_2 197 +#define ICBID_SLAVE_SMMNOC_BIMC 198 +#define ICBID_SLAVE_CRVIRT_A1NOC 199 +#define ICBID_SLAVE_SGMII 200 +#define ICBID_SLAVE_QHS4_APPS 201 +#define ICBID_SLAVE_BIMC_PCNOC 202 +#define ICBID_SLAVE_PCNOC_BIMC_1 203 +#define ICBID_SLAVE_SPMI_FETCHER 204 +#define ICBID_SLAVE_MMSS_SMMU_CFG 205 +#define ICBID_SLAVE_WLAN 206 +#define ICBID_SLAVE_CRVIRT_A2NOC 207 +#define ICBID_SLAVE_CNOC_A2NOC 208 +#define ICBID_SLAVE_GLM 209 +#define ICBID_SLAVE_GNOC_BIMC 210 +#define ICBID_SLAVE_GNOC_SNOC 211 +#define ICBID_SLAVE_QM_CFG 212 +#define ICBID_SLAVE_TLMM_EAST 213 +#define ICBID_SLAVE_TLMM_NORTH 214 +#define ICBID_SLAVE_TLMM_WEST 215 +#define ICBID_SLAVE_LPASS_TCM 216 +#define ICBID_SLAVE_TLMM_SOUTH 217 +#define ICBID_SLAVE_TLMM_CENTER 218 +#define ICBID_SLAVE_MSS_NAV_CE_MPU_CFG 219 +#define ICBID_SLAVE_A2NOC_THROTTLE_CFG 220 +#define ICBID_SLAVE_CDSP 221 +#define ICBID_SLAVE_CDSP_SMMU_CFG 222 +#define ICBID_SLAVE_LPASS_MPU_CFG 223 +#define ICBID_SLAVE_CSI_PHY_CFG 224 +#endif diff -Nruw linux-4.4.115-fbx/arch/arm64/boot/dts/include/dt-bindings/msm./msm-bus-rule-ops.h linux-4.4.115-fbx/arch/arm64/boot/dts/include/dt-bindings/msm/msm-bus-rule-ops.h --- linux-4.4.115-fbx/arch/arm64/boot/dts/include/dt-bindings/msm./msm-bus-rule-ops.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-4.4.115-fbx/arch/arm64/boot/dts/include/dt-bindings/msm/msm-bus-rule-ops.h 2019-01-22 16:16:28.179288750 +0100 @@ -0,0 +1,34 @@ +/* Copyright (c) 2014, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __MSM_BUS_RULE_OPS_H +#define __MSM_BUS_RULE_OPS_H + +#define FLD_IB 0 +#define FLD_AB 1 +#define FLD_CLK 2 + +#define OP_LE 0 +#define OP_LT 1 +#define OP_GE 2 +#define OP_GT 3 +#define OP_NOOP 4 + +#define RULE_STATE_NOT_APPLIED 0 +#define RULE_STATE_APPLIED 1 + +#define THROTTLE_ON 0 +#define THROTTLE_OFF 1 +#define THROTTLE_REG 2 + + +#endif diff -Nruw linux-4.4.115-fbx/arch/arm64/boot/dts/include/dt-bindings/msm./pm.h linux-4.4.115-fbx/arch/arm64/boot/dts/include/dt-bindings/msm/pm.h --- linux-4.4.115-fbx/arch/arm64/boot/dts/include/dt-bindings/msm./pm.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-4.4.115-fbx/arch/arm64/boot/dts/include/dt-bindings/msm/pm.h 2019-01-22 16:16:28.179288750 +0100 @@ -0,0 +1,25 @@ +/* Copyright (c) 2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __DT_MSM_PM_H__ +#define __DT_MSM_PM_H__ + +#define LPM_RESET_LVL_NONE 0 +#define LPM_RESET_LVL_RET 1 +#define LPM_RESET_LVL_GDHS 2 +#define LPM_RESET_LVL_PC 3 + +#define LPM_AFF_LVL_CPU 0 +#define LPM_AFF_LVL_L2 1 +#define LPM_AFF_LVL_CCI 2 + +#endif diff -Nruw linux-4.4.115-fbx/arch/arm64/boot/dts/include/dt-bindings/msm./power-on.h linux-4.4.115-fbx/arch/arm64/boot/dts/include/dt-bindings/msm/power-on.h --- linux-4.4.115-fbx/arch/arm64/boot/dts/include/dt-bindings/msm./power-on.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-4.4.115-fbx/arch/arm64/boot/dts/include/dt-bindings/msm/power-on.h 2019-01-22 16:16:28.179288750 +0100 @@ -0,0 +1,24 @@ +/* Copyright (c) 2015, 2017, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __MSM_POWER_ON_H__ +#define __MSM_POWER_ON_H__ + +#define PON_POWER_OFF_RESERVED 0x00 +#define PON_POWER_OFF_WARM_RESET 0x01 +#define PON_POWER_OFF_SHUTDOWN 0x04 +#define PON_POWER_OFF_DVDD_SHUTDOWN 0x05 +#define PON_POWER_OFF_HARD_RESET 0x07 +#define PON_POWER_OFF_DVDD_HARD_RESET 0x08 +#define PON_POWER_OFF_MAX_TYPE 0x10 + +#endif --- /dev/null 2019-10-24 16:47:25.704025805 +0200 +++ linux-4.4.115-fbx/arch/arm64/boot/dts/include/dt-bindings/regulator/qcom,rpm-smd-regulator.h 2019-01-22 16:16:28.183288787 +0100 @@ -0,0 +1,28 @@ +/* Copyright (c) 2015, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __QCOM_RPM_SMD_REGULATOR_H +#define __QCOM_RPM_SMD_REGULATOR_H + +#define RPM_SMD_REGULATOR_LEVEL_NONE 0 +#define RPM_SMD_REGULATOR_LEVEL_RETENTION 16 +#define RPM_SMD_REGULATOR_LEVEL_RETENTION_PLUS 32 +#define RPM_SMD_REGULATOR_LEVEL_MIN_SVS 48 +#define RPM_SMD_REGULATOR_LEVEL_LOW_SVS 64 +#define RPM_SMD_REGULATOR_LEVEL_SVS 128 +#define RPM_SMD_REGULATOR_LEVEL_SVS_PLUS 192 +#define RPM_SMD_REGULATOR_LEVEL_NOM 256 +#define RPM_SMD_REGULATOR_LEVEL_NOM_PLUS 320 +#define RPM_SMD_REGULATOR_LEVEL_TURBO 384 +#define RPM_SMD_REGULATOR_LEVEL_BINNING 512 + +#endif --- /dev/null 2019-10-24 16:47:25.704025805 +0200 +++ linux-4.4.115-fbx/arch/arm64/boot/dts/qcom/apq8098-freebox-batfish.dts 2019-01-22 16:16:21.171225289 +0100 @@ -0,0 +1,692 @@ +/* Copyright (c) 2017, Freebox SAS. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +#include +#include +#include "apq8098-v2.1.dtsi" +#include "msm8998-audio-freebox.dtsi" + +#include "msm8998-ramoops.dtsi" + +/ { + model = "Freebox Batfish"; + compatible = "freebox,fbx7hd-batfish", "freebox,fbx7hd", "qcom,apq8098"; + qcom,board-id = <5 2>; + + ir: ir-receiver { + compatible = "gpio-ir-receiver"; + gpios = <&tlmm 120 1>; + pinctrl-names = "default"; + pinctrl-0 = <&ir_int>; + linux,rc-map-name = "rc-rc6-freebox"; + }; + + fbxgpio@0 { + compatible = "fbx,fbxgpio"; + + pinctrl-names = "default"; + pinctrl-0 = < + &hdmi_en + &hdmi_fault + &force_test_mode + &usb_hub_rst + &spdif_src_sel + >; + + hdmi-enable { + name = "hdmi-enable"; + gpio = <&tlmm 17 GPIO_ACTIVE_HIGH>; + output-low; + }; + + hdmi-fault { + name = "hdmi-fault"; + gpio = <&tlmm 133 GPIO_ACTIVE_LOW>; + input; + }; + + test-mode { + name = "test-mode"; + gpio = <&tlmm 29 GPIO_ACTIVE_LOW>; + input; + }; + + usb-reset { + name = "usb-reset"; + gpio = <&tlmm 24 GPIO_ACTIVE_LOW>; + output-low; + }; + + spdif-src { + name = "spdif-src"; + gpio = <&tlmm 8 GPIO_ACTIVE_LOW>; + output-low; + }; + }; + + fbxgpio@1 { + compatible = "fbx,fbxgpio"; + + top-wcharging-ledr { + name = "top-wcharging-ledr"; + gpio = <&exp1 0 GPIO_ACTIVE_LOW>; + input; + }; + + top-wcharging-ledg { + name = "top-wcharging-ledg"; + gpio = <&exp1 1 GPIO_ACTIVE_LOW>; + input; + }; + + top-nfc-enable { + name = "top-nfc-enable"; + gpio = <&exp1 2 GPIO_ACTIVE_LOW>; + output-low; + }; + + top-nfc-int { + name = "top-nfc-int"; + gpio = <&exp1 3 GPIO_ACTIVE_LOW>; + input; + }; + + top-dsp-reset { + name = "top-dsp-reset"; + gpio = <&exp1 4 GPIO_ACTIVE_LOW>; + output-low; + }; + + top-mic-mute { + name = "top-mic-mute"; + gpio = <&exp1 7 GPIO_ACTIVE_HIGH>; + input; + }; + + top-wcharging-stby { + name = "top-wcharging-stby"; + gpio = <&exp1 8 GPIO_ACTIVE_LOW>; + output-low; + }; + + top-dsp-int { + name = "top-dsp-int"; + gpio = <&exp1 15 GPIO_ACTIVE_HIGH>; + input; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-0 = <&force_bank0>; + pinctrl-names = "default"; + + button@1 { + label = "Factory Reset Button"; + linux,code = ; + gpios = <&tlmm 18 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&vendor { + bluetooth: bt_wcn3990 { + compatible = "qca,wcn3990"; + qca,bt-vdd-io-supply = <&pm8998_s3>; + qca,bt-vdd-xtal-supply = <&pm8998_s5>; + qca,bt-vdd-core-supply = <&pm8998_l7>; + qca,bt-vdd-pa-supply = <&pm8998_l17>; + qca,bt-vdd-ldo-supply = <&pm8998_l25>; + //qca,bt-chip-pwd-supply = <&pmi8998_bob_pin1>; + clocks = <&clock_gcc clk_rf_clk2_pin>; + clock-names = "rf_clk2"; + + qca,bt-vdd-io-voltage-level = <1352000 1352000>; + qca,bt-vdd-xtal-voltage-level = <2040000 2040000>; + qca,bt-vdd-core-voltage-level = <1800000 1800000>; + qca,bt-vdd-pa-voltage-level = <1304000 1304000>; + qca,bt-vdd-ldo-voltage-level = <3312000 3312000>; + qca,bt-chip-pwd-voltage-level = <3600000 3600000>; + + qca,bt-vdd-io-current-level = <1>; /* LPM/PFM */ + qca,bt-vdd-xtal-current-level = <1>; /* LPM/PFM */ + qca,bt-vdd-core-current-level = <1>; /* LPM/PFM */ + qca,bt-vdd-pa-current-level = <1>; /* LPM/PFM */ + qca,bt-vdd-ldo-current-level = <1>; /* LPM/PFM */ + }; +}; + +&blsp1_uart3_hs { + status = "ok"; +}; + +&uartblsp2dm1 { + status = "ok"; + pinctrl-names = "default"; + pinctrl-0 = <&uart_console_active>; +}; + +&ufsphy1 { + vdda-phy-supply = <&pm8998_l1>; + vdda-pll-supply = <&pm8998_l2>; + vddp-ref-clk-supply = <&pm8998_l26>; + vdda-phy-max-microamp = <51400>; + vdda-pll-max-microamp = <14600>; + vddp-ref-clk-max-microamp = <100>; + vddp-ref-clk-always-on; + status = "ok"; +}; + +&ufs1 { + vdd-hba-supply = <&gdsc_ufs>; + vdd-hba-fixed-regulator; + vcc-supply = <&pm8998_l20>; + vccq-supply = <&pm8998_l26>; + vccq2-supply = <&pm8998_s4>; + vcc-max-microamp = <750000>; + vccq-max-microamp = <560000>; + vccq2-max-microamp = <750000>; + status = "ok"; +}; + +&ufs_ice { + status = "ok"; +}; + +&i2c_5 { + status = "okay"; + + qcom,clk-freq-out = <100000>; + + // ti8020@44 + // usbmux@47 + // si2157@60 + // si2168@64 + // leadtrend@68 +}; + +&i2c_4 { + status = "okay"; + + qcom,clk-freq-out = <100000>; + + lm75@48 { + compatible = "national,lm75"; + reg = <0x48>; + }; + + tas5766@4c { + compatible = "ti,tas5766"; + reg = <0x4c>; + }; + + tas5766@4d { + compatible = "ti,tas5766"; + reg = <0x4d>; + }; + + tas5766@4e { + compatible = "ti,tas5766"; + reg = <0x4e>; + }; + + // at24_audio@53 + // at24_carrier@57 +}; + +&i2c_6 { + status = "okay"; + + qcom,clk-freq-out = <100000>; + + exp1: gpio@74 { + compatible = "ti,tca9539"; + reg = <0x74>; + gpio-controller; + #gpio-cells = <2>; + reset-gpios = <&tlmm 96 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&top_exp_rst>; + }; + + // at24_top@53 +}; + +&i2c_7 { + status = "okay"; + + wm8804@3b { + compatible = "wlf,wm8804"; + reg = <0x3b>; + wlf,reset-gpio = <&tlmm 100 GPIO_ACTIVE_HIGH>; + wlf,irq-gpio = <&tlmm 110 GPIO_ACTIVE_LOW>; + }; + + sil9437@31 { + compatible = "sil,sil9437"; + reg = <0x31>; + sil,reset-gpio = <&tlmm 12 GPIO_ACTIVE_LOW>; + sil,irq-gpio = <&tlmm 118 GPIO_ACTIVE_LOW>; + sil,irq-open-drain; + sil,irq-active-low; + }; + + // hdmi_redriver@5e +}; + +&spi_1 { + status = "okay"; + + pinctrl-0 = <&spi_1_active &spi_1b_active &top_psoc_rst>; + pinctrl-1 = <&spi_1_sleep &spi_1b_sleep &top_psoc_rst>; + cs-gpios = <&tlmm 2 GPIO_ACTIVE_HIGH>, <&tlmm 23 GPIO_ACTIVE_HIGH>, <&tlmm 23 GPIO_ACTIVE_HIGH>, <&tlmm 23 GPIO_ACTIVE_HIGH>; + + spidev@0 { + /* PSOC for LED & touch control */ + compatible = "freebox,fbx7hd-top-psoc"; + spi-max-frequency = <1200000>; + irq-gpio = <&tlmm 122 GPIO_ACTIVE_LOW>; + reset-gpio = <&tlmm 97 GPIO_ACTIVE_LOW>; + reg = <0>; + }; + + spidev@3 { + /* XMOS */ + compatible = "spidev"; + spi-max-frequency = <1200000>; + reg = <3>; + }; +}; + +&spi_9 { + status = "okay"; + switch@0 { + compatible = "realtek,rtl8367c-spi"; + reg = <0>; + reset-gpios = <&tlmm 30 GPIO_ACTIVE_LOW>; + spi-max-frequency = <5000000>; + }; +}; + +&tlmm { + force_bank0: force_bank0 { + mux { + pins = "gpio18"; + function = "gpio"; + }; + + config { + pins = "gpio18"; + drive-strength = <2>; + bias-disable; + }; + }; + + force_test_mode: force_test_mode { + mux { + pins = "gpio29"; + function = "gpio"; + }; + + config { + pins = "gpio29"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + hdmi_en: hdmi_en { + mux { + pins = "gpio17"; + function = "gpio"; + }; + + config { + pins = "gpio17"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + hdmi_fault: hdmi_fault { + mux { + pins = "gpio133"; + function = "gpio"; + }; + + config { + pins = "gpio133"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + usb_hub_rst: usb_hub_rst { + mux { + pins = "gpio24"; + function = "gpio"; + }; + + config { + pins = "gpio24"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + spdif_src_sel: spdif_src_sel { + mux { + pins = "gpio8"; + function = "gpio"; + }; + + config { + pins = "gpio8"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + top_exp_rst: top_exp_rst { + mux { + pins = "gpio96"; + function = "gpio"; + }; + + config { + pins = "gpio96"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + top_psoc_rst: top_psoc_rst { + mux { + pins = "gpio97"; + function = "gpio"; + }; + + config { + pins = "gpio97"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + ir_int: ir_int { + mux { + pins = "gpio120"; + function = "gpio"; + }; + config { + pins = "gpio120"; + drive-strength = <6>; + bias-pull-up; + }; + }; + + top_exp_psoc_irq: top_exp_psoc_irq { + mux { + pins = "gpio122"; + function = "gpio"; + }; + + config { + pins = "gpio122"; + drive-strength = <2>; + bias-pull-down; + }; + }; +}; + +&usb3 { + /delete-property/ extcon; + dwc3@a800000 { + dr_mode = "host"; + }; +}; + +&sde_hdmi { + qcom,display-type = "primary"; +}; + +&sde_hdmi_tx { + /* disable 5V HPD pin */ + /delete-property/ qcom,hdmi-tx-hpd5v-gpio; + pinctrl-0 = <&mdss_hdmi_hpd_active + &mdss_hdmi_ddc_active>; + pinctrl-1 = <&mdss_hdmi_hpd_suspend + &mdss_hdmi_ddc_suspend>; +}; + +&spmi_bus { + qcom,pmi8998@2 { + status = "disabled"; + }; + qcom,pmi8998@3 { + status = "disabled"; + }; +}; + +&pmi8998_wled { + status = "disabled"; +}; + +&pm8998_gpios { + gpio@cc00 { /* GPIO 13 */ + qcom,mode = <1>; + qcom,output-type = <0>; + qcom,pull = <5>; + qcom,vin-sel = <0>; + qcom,out-strength = <1>; + qcom,src-sel = <3>; + qcom,master-en = <1>; + status = "okay"; + }; +}; + +&pm8998_vadc { + chan@83 { + label = "vph_pwr"; + reg = <0x83>; + qcom,decimation = <2>; + qcom,pre-div-channel-scaling = <1>; + qcom,calibration-type = "absolute"; + qcom,scale-function = <0>; + qcom,hw-settle-time = <0>; + qcom,fast-avg-setup = <0>; + }; + + chan@85 { + label = "vcoin"; + reg = <0x85>; + qcom,decimation = <2>; + qcom,pre-div-channel-scaling = <1>; + qcom,calibration-type = "absolute"; + qcom,scale-function = <0>; + qcom,hw-settle-time = <0>; + qcom,fast-avg-setup = <0>; + }; + + chan@4c { + label = "xo_therm"; + reg = <0x4c>; + qcom,decimation = <2>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "ratiometric"; + qcom,scale-function = <4>; + qcom,hw-settle-time = <2>; + qcom,fast-avg-setup = <0>; + }; + + chan@4d { + label = "msm_therm"; + reg = <0x4d>; + qcom,decimation = <2>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "ratiometric"; + qcom,scale-function = <2>; + qcom,hw-settle-time = <2>; + qcom,fast-avg-setup = <0>; + }; + + chan@51 { + label = "quiet_therm"; + reg = <0x51>; + qcom,decimation = <2>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "ratiometric"; + qcom,scale-function = <2>; + qcom,hw-settle-time = <2>; + qcom,fast-avg-setup = <0>; + }; +}; + +&pm8998_adc_tm { + chan@83 { + label = "vph_pwr"; + reg = <0x83>; + qcom,pre-div-channel-scaling = <1>; + qcom,calibration-type = "absolute"; + qcom,scale-function = <0>; + qcom,hw-settle-time = <0>; + qcom,btm-channel-number = <0x60>; + }; + + chan@4d { + label = "msm_therm"; + reg = <0x4d>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "ratiometric"; + qcom,scale-function = <2>; + qcom,hw-settle-time = <2>; + qcom,btm-channel-number = <0x68>; + qcom,thermal-node; + }; + + chan@51 { + label = "quiet_therm"; + reg = <0x51>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "ratiometric"; + qcom,scale-function = <2>; + qcom,hw-settle-time = <2>; + qcom,btm-channel-number = <0x70>; + qcom,thermal-node; + }; + + chan@4c { + label = "xo_therm"; + reg = <0x4c>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "ratiometric"; + qcom,scale-function = <4>; + qcom,hw-settle-time = <2>; + qcom,btm-channel-number = <0x78>; + qcom,thermal-node; + }; +}; + +&soc { + qcom,msm-dai-tdm-sec-rx { + qcom,msm-cpudai-tdm-group-id = <37136>; + qcom,msm-cpudai-tdm-group-num-ports = <1>; + qcom,msm-cpudai-tdm-group-port-id = <36880>; + qcom,msm-cpudai-tdm-clk-rate = <12288000>; + qcom,msm-cpudai-tdm-clk-internal = <1>; + qcom,msm-cpudai-tdm-sync-mode = <1>; + qcom,msm-cpudai-tdm-sync-src = <1>; + qcom,msm-cpudai-tdm-data-out = <1>; + qcom,msm-cpudai-tdm-invert-sync = <0>; + qcom,msm-cpudai-tdm-data-delay = <0>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sec_aux_pcm_active + &sec_aux_pcm_dout_active>; + pinctrl-1 = <&sec_aux_pcm_sleep + &sec_aux_pcm_dout_sleep>; + }; + + qcom,msm-dai-mi2s { + dai_mi2s0: qcom,msm-dai-q6-mi2s-prim { + qcom,msm-mi2s-rx-lines = <1>; + qcom,msm-mi2s-tx-lines = <0>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pri_mi2s_mclk_active + &pri_mi2s_sck_active + &pri_mi2s_ws_active + &pri_mi2s_sd0_active>; + pinctrl-1 = <&pri_mi2s_mclk_sleep + &pri_mi2s_sck_sleep + &pri_mi2s_ws_sleep + &pri_mi2s_sd0_sleep>; + }; + + dai_mi2s2: qcom,msm-dai-q6-mi2s-tert { + qcom,msm-mi2s-rx-lines = <0>; + qcom,msm-mi2s-tx-lines = <1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&tert_mi2s_active + &tert_mi2s_sd0_active>; + pinctrl-1 = <&tert_mi2s_sleep + &tert_mi2s_sd0_sleep>; + }; + + dai_mi2s3: qcom,msm-dai-q6-mi2s-quat { + qcom,msm-mi2s-rx-lines = <0>; + qcom,msm-mi2s-tx-lines = <15>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&quat_mi2s_active + &quat_mi2s_sd0_active + &quat_mi2s_sd1_active + &quat_mi2s_sd2_active + &quat_mi2s_sd3_active>; + pinctrl-1 = <&quat_mi2s_sleep + &quat_mi2s_sd0_sleep + &quat_mi2s_sd1_sleep + &quat_mi2s_sd2_sleep + &quat_mi2s_sd3_sleep>; + }; + }; + + sound-freebox { + fbx,spdif-wm8804; + fbx,arc-sil9437; + }; +}; + +&soc { + qcom,bcl { + /delete-property/ qcom,bcl-enable; + }; +}; + +&pcie0 { + qcom,boot-option = <0>; +}; + +&msm_ath10k_wlan { + status = "ok"; +}; + +&tspp { + pinctrl-names = "disabled", "tsif0-mode1", "tsif0-mode2"; + + tsin0: port@0 { + tsin-num = <0>; + i2c-bus = <&i2c_5>; + reset-gpios = <&tlmm 84 GPIO_ACTIVE_LOW>; + }; +}; --- /dev/null 2019-10-24 16:47:25.704025805 +0200 +++ linux-4.4.115-fbx/arch/arm64/boot/dts/qcom/apq8098-freebox-oarfish.dts 2019-01-22 16:16:21.171225289 +0100 @@ -0,0 +1,402 @@ +/* Copyright (c) 2017, Freebox SAS. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +#include +#include +#include "apq8098-v2.1.dtsi" +#include "msm8998-audio-freebox.dtsi" + +#include "msm8998-ramoops.dtsi" + +/ { + model = "Freebox Oarfish"; + compatible = "freebox,fbx7hd-oarfish", "freebox,fbx7hd", "qcom,apq8098"; + qcom,board-id = <5 3>; + + ir: ir-receiver { + compatible = "gpio-ir-receiver"; + gpios = <&tlmm 120 1>; + pinctrl-names = "default"; + pinctrl-0 = <&ir_int>; + linux,rc-map-name = "rc-rc6-freebox"; + }; + + fbxgpio@0 { + compatible = "fbx,fbxgpio"; + + pinctrl-names = "default"; + pinctrl-0 = < + &hdmi_en + &hdmi_fault + &force_test_mode + >; + + hdmi-enable { + name = "hdmi-enable"; + gpio = <&tlmm 17 GPIO_ACTIVE_HIGH>; + output-low; + }; + + hdmi-fault { + name = "hdmi-fault"; + gpio = <&tlmm 133 GPIO_ACTIVE_LOW>; + input; + }; + + test-mode { + name = "test-mode"; + gpio = <&tlmm 29 GPIO_ACTIVE_LOW>; + input; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-0 = <&force_bank0>; + pinctrl-names = "default"; + + button@1 { + label = "Factory Reset Button"; + linux,code = ; + gpios = <&tlmm 18 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&vendor { + bluetooth: bt_wcn3990 { + compatible = "qca,wcn3990"; + qca,bt-vdd-io-supply = <&pm8998_s3>; + qca,bt-vdd-xtal-supply = <&pm8998_s5>; + qca,bt-vdd-core-supply = <&pm8998_l7>; + qca,bt-vdd-pa-supply = <&pm8998_l17>; + qca,bt-vdd-ldo-supply = <&pm8998_l25>; + //qca,bt-chip-pwd-supply = <&pmi8998_bob_pin1>; + clocks = <&clock_gcc clk_rf_clk2_pin>; + clock-names = "rf_clk2"; + + qca,bt-vdd-io-voltage-level = <1352000 1352000>; + qca,bt-vdd-xtal-voltage-level = <2040000 2040000>; + qca,bt-vdd-core-voltage-level = <1800000 1800000>; + qca,bt-vdd-pa-voltage-level = <1304000 1304000>; + qca,bt-vdd-ldo-voltage-level = <3312000 3312000>; + qca,bt-chip-pwd-voltage-level = <3600000 3600000>; + + qca,bt-vdd-io-current-level = <1>; /* LPM/PFM */ + qca,bt-vdd-xtal-current-level = <1>; /* LPM/PFM */ + qca,bt-vdd-core-current-level = <1>; /* LPM/PFM */ + qca,bt-vdd-pa-current-level = <1>; /* LPM/PFM */ + qca,bt-vdd-ldo-current-level = <1>; /* LPM/PFM */ + }; +}; + +&blsp1_uart3_hs { + status = "ok"; +}; + +&uartblsp2dm1 { + status = "ok"; + pinctrl-names = "default"; + pinctrl-0 = <&uart_console_active>; +}; + +&ufsphy1 { + vdda-phy-supply = <&pm8998_l1>; + vdda-pll-supply = <&pm8998_l2>; + vddp-ref-clk-supply = <&pm8998_l26>; + vdda-phy-max-microamp = <51400>; + vdda-pll-max-microamp = <14600>; + vddp-ref-clk-max-microamp = <100>; + vddp-ref-clk-always-on; + status = "ok"; +}; + +&ufs1 { + vdd-hba-supply = <&gdsc_ufs>; + vdd-hba-fixed-regulator; + vcc-supply = <&pm8998_l20>; + vccq-supply = <&pm8998_l26>; + vccq2-supply = <&pm8998_s4>; + vcc-max-microamp = <750000>; + vccq-max-microamp = <560000>; + vccq2-max-microamp = <750000>; + status = "ok"; +}; + +&ufs_ice { + status = "ok"; +}; + +&i2c_5 { + status = "okay"; + + qcom,clk-freq-out = <100000>; + + // usbmux@47 + // si2168@64 +}; + +&i2c_4 { + status = "okay"; + + qcom,clk-freq-out = <100000>; + + // at24_carrier@57 +}; + +&i2c_7 { + status = "okay"; + + // hdmi_redriver@5e +}; + +&tlmm { + force_bank0: force_bank0 { + mux { + pins = "gpio18"; + function = "gpio"; + }; + + config { + pins = "gpio18"; + drive-strength = <2>; + bias-disable; + }; + }; + + force_test_mode: force_test_mode { + mux { + pins = "gpio29"; + function = "gpio"; + }; + + config { + pins = "gpio29"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + hdmi_en: hdmi_en { + mux { + pins = "gpio17"; + function = "gpio"; + }; + + config { + pins = "gpio17"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + hdmi_fault: hdmi_fault { + mux { + pins = "gpio133"; + function = "gpio"; + }; + + config { + pins = "gpio133"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + ir_int: ir_int { + mux { + pins = "gpio120"; + function = "gpio"; + }; + config { + pins = "gpio120"; + drive-strength = <6>; + bias-pull-up; + }; + }; +}; + +&usb3 { + /delete-property/ extcon; + dwc3@a800000 { + dr_mode = "host"; + }; +}; + +&sde_hdmi { + qcom,display-type = "primary"; +}; + +&sde_hdmi_tx { + /* disable 5V HPD pin */ + /delete-property/ qcom,hdmi-tx-hpd5v-gpio; + pinctrl-0 = <&mdss_hdmi_hpd_active + &mdss_hdmi_ddc_active>; + pinctrl-1 = <&mdss_hdmi_hpd_suspend + &mdss_hdmi_ddc_suspend>; +}; + +&spmi_bus { + qcom,pmi8998@2 { + status = "disabled"; + }; + qcom,pmi8998@3 { + status = "disabled"; + }; +}; + +&pmi8998_wled { + status = "disabled"; +}; + +&pm8998_gpios { + gpio@cc00 { /* GPIO 13 */ + qcom,mode = <1>; + qcom,output-type = <0>; + qcom,pull = <5>; + qcom,vin-sel = <0>; + qcom,out-strength = <1>; + qcom,src-sel = <3>; + qcom,master-en = <1>; + status = "okay"; + }; +}; + +&pm8998_vadc { + chan@83 { + label = "vph_pwr"; + reg = <0x83>; + qcom,decimation = <2>; + qcom,pre-div-channel-scaling = <1>; + qcom,calibration-type = "absolute"; + qcom,scale-function = <0>; + qcom,hw-settle-time = <0>; + qcom,fast-avg-setup = <0>; + }; + + chan@85 { + label = "vcoin"; + reg = <0x85>; + qcom,decimation = <2>; + qcom,pre-div-channel-scaling = <1>; + qcom,calibration-type = "absolute"; + qcom,scale-function = <0>; + qcom,hw-settle-time = <0>; + qcom,fast-avg-setup = <0>; + }; + + chan@4c { + label = "xo_therm"; + reg = <0x4c>; + qcom,decimation = <2>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "ratiometric"; + qcom,scale-function = <4>; + qcom,hw-settle-time = <2>; + qcom,fast-avg-setup = <0>; + }; + + chan@4d { + label = "msm_therm"; + reg = <0x4d>; + qcom,decimation = <2>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "ratiometric"; + qcom,scale-function = <2>; + qcom,hw-settle-time = <2>; + qcom,fast-avg-setup = <0>; + }; + + chan@51 { + label = "quiet_therm"; + reg = <0x51>; + qcom,decimation = <2>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "ratiometric"; + qcom,scale-function = <2>; + qcom,hw-settle-time = <2>; + qcom,fast-avg-setup = <0>; + }; +}; + +&pm8998_adc_tm { + chan@83 { + label = "vph_pwr"; + reg = <0x83>; + qcom,pre-div-channel-scaling = <1>; + qcom,calibration-type = "absolute"; + qcom,scale-function = <0>; + qcom,hw-settle-time = <0>; + qcom,btm-channel-number = <0x60>; + }; + + chan@4d { + label = "msm_therm"; + reg = <0x4d>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "ratiometric"; + qcom,scale-function = <2>; + qcom,hw-settle-time = <2>; + qcom,btm-channel-number = <0x68>; + qcom,thermal-node; + }; + + chan@51 { + label = "quiet_therm"; + reg = <0x51>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "ratiometric"; + qcom,scale-function = <2>; + qcom,hw-settle-time = <2>; + qcom,btm-channel-number = <0x70>; + qcom,thermal-node; + }; + + chan@4c { + label = "xo_therm"; + reg = <0x4c>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "ratiometric"; + qcom,scale-function = <4>; + qcom,hw-settle-time = <2>; + qcom,btm-channel-number = <0x78>; + qcom,thermal-node; + }; +}; + +&soc { + qcom,bcl { + /delete-property/ qcom,bcl-enable; + }; +}; + +&pcie0 { + qcom,boot-option = <0>; +}; + +&msm_ath10k_wlan { + status = "ok"; +}; + +&tspp { + pinctrl-names = "disabled", "tsif0-mode1", "tsif0-mode2"; + + tsin0: port@0 { + tsin-num = <0>; + i2c-bus = <&i2c_5>; + reset-gpios = <&tlmm 84 GPIO_ACTIVE_LOW>; + }; +}; --- /dev/null 2019-10-24 16:47:25.704025805 +0200 +++ linux-4.4.115-fbx/arch/arm64/boot/dts/qcom/apq8098-freebox-proto.dts 2019-01-22 16:16:21.171225289 +0100 @@ -0,0 +1,515 @@ +/* Copyright (c) 2017, Freebox SAS. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +#include +#include "apq8098-v2.1.dtsi" +#include "msm8998-audio-freebox.dtsi" + +#include "msm8998-ramoops.dtsi" + +/ { + model = "Freebox Test Carrier"; + compatible = "freebox,fbx7hd-carrier", "freebox,fbx7hd", "qcom,apq8098"; + qcom,board-id = <5 1>; + + ir: ir-receiver { + compatible = "gpio-ir-receiver"; + gpios = <&tlmm 120 1>; + pinctrl-names = "default"; + pinctrl-0 = <&ir_int>; + linux,rc-map-name = "rc-rc6-freebox"; + }; + + fbxgpio@0 { + compatible = "fbx,fbxgpio"; + + pinctrl-names = "default"; + pinctrl-0 = < + &hdmi_fault + &nfc_enable + &nfc_int + >; + + hdmi-fault { + name = "hdmi-fault"; + gpio = <&tlmm 133 GPIO_ACTIVE_LOW>; + input; + }; + + nfcc-enable { + name = "nfcc-enable"; + gpio = <&tlmm 96 GPIO_ACTIVE_HIGH>; + output-low; + }; + + nfcc-irq { + name = "nfcc-irq"; + gpio = <&tlmm 97 GPIO_ACTIVE_HIGH>; + input; + }; + }; +}; + +&vendor { + bluetooth: bt_wcn3990 { + compatible = "qca,wcn3990"; + qca,bt-vdd-io-supply = <&pm8998_s3>; + qca,bt-vdd-xtal-supply = <&pm8998_s5>; + qca,bt-vdd-core-supply = <&pm8998_l7>; + qca,bt-vdd-pa-supply = <&pm8998_l17>; + qca,bt-vdd-ldo-supply = <&pm8998_l25>; + //qca,bt-chip-pwd-supply = <&pmi8998_bob_pin1>; + clocks = <&clock_gcc clk_rf_clk2_pin>; + clock-names = "rf_clk2"; + + qca,bt-vdd-io-voltage-level = <1352000 1352000>; + qca,bt-vdd-xtal-voltage-level = <2040000 2040000>; + qca,bt-vdd-core-voltage-level = <1800000 1800000>; + qca,bt-vdd-pa-voltage-level = <1304000 1304000>; + qca,bt-vdd-ldo-voltage-level = <3312000 3312000>; + qca,bt-chip-pwd-voltage-level = <3600000 3600000>; + + qca,bt-vdd-io-current-level = <1>; /* LPM/PFM */ + qca,bt-vdd-xtal-current-level = <1>; /* LPM/PFM */ + qca,bt-vdd-core-current-level = <1>; /* LPM/PFM */ + qca,bt-vdd-pa-current-level = <1>; /* LPM/PFM */ + qca,bt-vdd-ldo-current-level = <1>; /* LPM/PFM */ + }; +}; + +&blsp1_uart3_hs { + status = "ok"; +}; + +&uartblsp2dm1 { + status = "ok"; + pinctrl-names = "default"; + pinctrl-0 = <&uart_console_active>; +}; + +&ufsphy1 { + vdda-phy-supply = <&pm8998_l1>; + vdda-pll-supply = <&pm8998_l2>; + vddp-ref-clk-supply = <&pm8998_l26>; + vdda-phy-max-microamp = <51400>; + vdda-pll-max-microamp = <14600>; + vddp-ref-clk-max-microamp = <100>; + vddp-ref-clk-always-on; + status = "ok"; +}; + +&ufs1 { + vdd-hba-supply = <&gdsc_ufs>; + vdd-hba-fixed-regulator; + vcc-supply = <&pm8998_l20>; + vccq-supply = <&pm8998_l26>; + vccq2-supply = <&pm8998_s4>; + vcc-max-microamp = <750000>; + vccq-max-microamp = <560000>; + vccq2-max-microamp = <750000>; + status = "ok"; +}; + +&ufs_ice { + status = "ok"; +}; + +&i2c_5 { + status = "okay"; + // si2168@64 +}; + +&i2c_4 { + status = "okay"; + + qcom,clk-freq-out = <100000>; + + lm75@48 { + compatible = "national,lm75"; + reg = <0x48>; + }; + + tas5766@4c { + compatible = "ti,tas5766"; + reg = <0x4c>; + }; + + tas5766@4d { + compatible = "ti,tas5766"; + reg = <0x4d>; + }; + + tas5766@4e { + compatible = "ti,tas5766"; + reg = <0x4e>; + }; +}; + +&i2c_6 { + status = "okay"; +}; + +&i2c_7 { + status = "okay"; + + wm8804@3b { + compatible = "wlf,wm8804"; + reg = <0x3b>; + wlf,reset-gpio = <&tlmm 100 GPIO_ACTIVE_HIGH>; + }; + + sil9437@31 { + compatible = "sil,sil9437"; + reg = <0x31>; + sil,reset-gpio = <&tlmm 12 GPIO_ACTIVE_LOW>; + sil,irq-gpio = <&tlmm 118 GPIO_ACTIVE_LOW>; + sil,irq-open-drain; + sil,irq-active-low; + }; + + /delete-node/ qcom,smb138x@8; +}; + +&spi_9 { + status = "okay"; + switch@0 { + compatible = "realtek,rtl8367c-spi"; + reg = <0>; + reset-gpios = <&tlmm 30 GPIO_ACTIVE_LOW>; + spi-max-frequency = <5000000>; + }; +}; + +&spi_10 { + status = "disabled"; +}; + +&tlmm { + cdc_reset_ctrl_batfish { + cdc_reset_batfish_sleep: cdc_reset_batfish_sleep { + mux { + pins = "gpio25"; + function = "gpio"; + }; + config { + pins = "gpio25"; + drive-strength = <16>; + bias-disable; + output-low; + }; + }; + cdc_reset_batfish_active:cdc_reset_batfish_active { + mux { + pins = "gpio25"; + function = "gpio"; + }; + config { + pins = "gpio25"; + drive-strength = <16>; + bias-pull-down; + output-high; + }; + }; + }; + + nfc { + nfc_enable: nfc_enable { + mux { + pins = "gpio96"; + function = "gpio"; + }; + + config { + pins = "gpio96"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + nfc_int: nfc_int { + mux { + pins = "gpio97"; + function = "gpio"; + }; + + config { + pins = "gpio97"; + drive-strength = <2>; + bias-pull-down; + }; + }; + }; + + hdmi_fault: hdmi_fault { + mux { + pins = "gpio133"; + function = "gpio"; + }; + + config { + pins = "gpio133"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + ir_int: ir_int { + mux { + pins = "gpio120"; + function = "gpio"; + }; + config { + pins = "gpio120"; + drive-strength = <6>; + bias-pull-up; + }; + }; +}; + +&usb3 { + /delete-property/ extcon; + dwc3@a800000 { + dr_mode = "host"; + }; +}; + +&sde_hdmi { + qcom,display-type = "primary"; +}; + +&sde_hdmi_tx { + /* disable 5V HPD pin */ + /delete-property/ qcom,hdmi-tx-hpd5v-gpio; + pinctrl-0 = <&mdss_hdmi_hpd_active + &mdss_hdmi_ddc_active>; + pinctrl-1 = <&mdss_hdmi_hpd_suspend + &mdss_hdmi_ddc_suspend>; +}; + +&spmi_bus { + qcom,pmi8998@2 { + status = "disabled"; + }; + qcom,pmi8998@3 { + status = "disabled"; + }; +}; + +&pmi8998_wled { + status = "disabled"; +}; + +&pm8998_gpios { + gpio@cc00 { /* GPIO 13 */ + qcom,mode = <1>; + qcom,output-type = <0>; + qcom,pull = <5>; + qcom,vin-sel = <0>; + qcom,out-strength = <1>; + qcom,src-sel = <3>; + qcom,master-en = <1>; + status = "okay"; + }; +}; + +&pm8998_vadc { + chan@83 { + label = "vph_pwr"; + reg = <0x83>; + qcom,decimation = <2>; + qcom,pre-div-channel-scaling = <1>; + qcom,calibration-type = "absolute"; + qcom,scale-function = <0>; + qcom,hw-settle-time = <0>; + qcom,fast-avg-setup = <0>; + }; + + chan@85 { + label = "vcoin"; + reg = <0x85>; + qcom,decimation = <2>; + qcom,pre-div-channel-scaling = <1>; + qcom,calibration-type = "absolute"; + qcom,scale-function = <0>; + qcom,hw-settle-time = <0>; + qcom,fast-avg-setup = <0>; + }; + + chan@4c { + label = "xo_therm"; + reg = <0x4c>; + qcom,decimation = <2>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "ratiometric"; + qcom,scale-function = <4>; + qcom,hw-settle-time = <2>; + qcom,fast-avg-setup = <0>; + }; + + chan@4d { + label = "msm_therm"; + reg = <0x4d>; + qcom,decimation = <2>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "ratiometric"; + qcom,scale-function = <2>; + qcom,hw-settle-time = <2>; + qcom,fast-avg-setup = <0>; + }; + + chan@51 { + label = "quiet_therm"; + reg = <0x51>; + qcom,decimation = <2>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "ratiometric"; + qcom,scale-function = <2>; + qcom,hw-settle-time = <2>; + qcom,fast-avg-setup = <0>; + }; +}; + +&pm8998_adc_tm { + chan@83 { + label = "vph_pwr"; + reg = <0x83>; + qcom,pre-div-channel-scaling = <1>; + qcom,calibration-type = "absolute"; + qcom,scale-function = <0>; + qcom,hw-settle-time = <0>; + qcom,btm-channel-number = <0x60>; + }; + + chan@4d { + label = "msm_therm"; + reg = <0x4d>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "ratiometric"; + qcom,scale-function = <2>; + qcom,hw-settle-time = <2>; + qcom,btm-channel-number = <0x68>; + qcom,thermal-node; + }; + + chan@51 { + label = "quiet_therm"; + reg = <0x51>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "ratiometric"; + qcom,scale-function = <2>; + qcom,hw-settle-time = <2>; + qcom,btm-channel-number = <0x70>; + qcom,thermal-node; + }; + + chan@4c { + label = "xo_therm"; + reg = <0x4c>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "ratiometric"; + qcom,scale-function = <4>; + qcom,hw-settle-time = <2>; + qcom,btm-channel-number = <0x78>; + qcom,thermal-node; + }; +}; + +&soc { + qcom,msm-dai-tdm-sec-rx { + qcom,msm-cpudai-tdm-group-id = <37136>; + qcom,msm-cpudai-tdm-group-num-ports = <1>; + qcom,msm-cpudai-tdm-group-port-id = <36880>; + qcom,msm-cpudai-tdm-clk-rate = <12288000>; + qcom,msm-cpudai-tdm-clk-internal = <1>; + qcom,msm-cpudai-tdm-sync-mode = <1>; + qcom,msm-cpudai-tdm-sync-src = <1>; + qcom,msm-cpudai-tdm-data-out = <1>; + qcom,msm-cpudai-tdm-invert-sync = <0>; + qcom,msm-cpudai-tdm-data-delay = <0>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sec_aux_pcm_active + &sec_aux_pcm_dout_active>; + pinctrl-1 = <&sec_aux_pcm_sleep + &sec_aux_pcm_dout_sleep>; + }; + + qcom,msm-dai-mi2s { + dai_mi2s0: qcom,msm-dai-q6-mi2s-prim { + qcom,msm-mi2s-rx-lines = <1>; + qcom,msm-mi2s-tx-lines = <0>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pri_mi2s_sck_active + &pri_mi2s_ws_active + &pri_mi2s_sd0_active>; + pinctrl-1 = <&pri_mi2s_sck_sleep + &pri_mi2s_ws_sleep + &pri_mi2s_sd0_sleep>; + }; + + dai_mi2s2: qcom,msm-dai-q6-mi2s-tert { + qcom,msm-mi2s-rx-lines = <0>; + qcom,msm-mi2s-tx-lines = <1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&tert_mi2s_active + &tert_mi2s_sd0_active>; + pinctrl-1 = <&tert_mi2s_sleep + &tert_mi2s_sd0_sleep>; + }; + + dai_mi2s3: qcom,msm-dai-q6-mi2s-quat { + qcom,msm-mi2s-rx-lines = <0>; + qcom,msm-mi2s-tx-lines = <15>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&quat_mi2s_active + &quat_mi2s_sd0_active + &quat_mi2s_sd1_active + &quat_mi2s_sd2_active + &quat_mi2s_sd3_active>; + pinctrl-1 = <&quat_mi2s_sleep + &quat_mi2s_sd0_sleep + &quat_mi2s_sd1_sleep + &quat_mi2s_sd2_sleep + &quat_mi2s_sd3_sleep>; + }; + }; + + sound-freebox { + fbx,spdif-wm8804; + fbx,arc-sil9437; + }; +}; + +&soc { + qcom,bcl { + /delete-property/ qcom,bcl-enable; + }; +}; + +&pcie0 { + qcom,boot-option = <0>; +}; + +&msm_ath10k_wlan { + status = "ok"; +}; + +&tspp { + pinctrl-names = "disabled", "tsif0-mode1", "tsif0-mode2"; + + tsin0: port@0 { + tsin-num = <0>; + i2c-bus = <&i2c_5>; + reset-gpios = <&tlmm 84 GPIO_ACTIVE_LOW>; + }; +}; --- /dev/null 2019-10-24 16:47:25.704025805 +0200 +++ linux-4.4.115-fbx/arch/arm64/boot/dts/qcom/apq8098-v2.1.dtsi 2019-01-22 16:16:21.171225289 +0100 @@ -0,0 +1,28 @@ +/* Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "msm8998-v2.1.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. APQ 8098 V2.1"; + qcom,msm-id = <319 0x20001>; +}; + +&soc { + qcom,rmnet-ipa { + status = "disabled"; + }; +}; + +&ipa_hw { + status = "disabled"; +}; --- /dev/null 2019-10-24 16:47:25.704025805 +0200 +++ linux-4.4.115-fbx/arch/arm64/boot/dts/qcom/apq8098-v2.1-mediabox.dts 2019-10-29 09:26:22.905195956 +0100 @@ -0,0 +1,222 @@ +/* Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +#include "apq8098-v2.1.dtsi" +#include "msm8998-cdp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. APQ 8098 V2.1 mediabox"; + compatible = "qcom,apq8098-cdp", "qcom,apq8098", "qcom,cdp"; + qcom,board-id = <8 1>; +}; + +&spi_10 { + status = "disabled"; +}; + +&pcie0 { + /delete-property/ qcom,boot-option; +}; + +&msm_ath10k_wlan { + status = "ok"; +}; + +&sde_hdmi { + qcom,display-type = "primary"; +}; + +&slim_aud { + tasha_codec { + wsa_spkr_sd1: msm_cdc_pinctrll { + compatible = "qcom,msm-cdc-pinctrl"; + pinctrl-names = "aud_active", "aud_sleep"; + pinctrl-0 = <&spkr_1_sd_active_mediabox>; + pinctrl-1 = <&spkr_1_sd_sleep_mediabox>; + }; + + wsa_spkr_sd2: msm_cdc_pinctrlr { + compatible = "qcom,msm-cdc-pinctrl"; + pinctrl-names = "aud_active", "aud_sleep"; + pinctrl-0 = <&spkr_2_sd_active_mediabox>; + pinctrl-1 = <&spkr_2_sd_sleep_mediabox>; + }; + }; +}; + +&sdhc_2 { + vdd-supply = <&pm8998_l21>; + qcom,vdd-voltage-level = <2950000 2960000>; + qcom,vdd-current-level = <200 800000>; + + vdd-io-supply = <&pm8998_l13>; + qcom,vdd-io-voltage-level = <1808000 2960000>; + qcom,vdd-io-current-level = <200 22000>; + + pinctrl-names = "active", "sleep"; + pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on + &sdc2_cd_on_mediabox>; + pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off + &sdc2_cd_off_mediabox>; + + qcom,clk-rates = <400000 20000000 25000000 + 50000000 100000000 200000000>; + qcom,bus-speed-mode = "SDR12", "SDR25", "SDR50", "DDR50", "SDR104"; + + cd-gpios = <&tlmm 86 0x1>; + + status = "ok"; +}; + +&tspp { + qcom,lpass-timer-tts = <1>; +}; + +&snd_9335 { + qcom,msm-mi2s-master = <1>, <1>, <1>, <0>; + qcom,msm-mbhc-hphl-swh = <1>; +}; + +&wcd_usbc_analog_en1_gpio { + status = "disabled"; +}; + +&wcd_usbc_analog_en2n_gpio { + status = "disabled"; +}; + +&pcie0 { + qcom,boot-option = <0x0>; +}; + +&soc { + qcom,msm-dai-mi2s { + dai_mi2s3: qcom,msm-dai-q6-mi2s-quat { + /* SD0 (1 << 0) | SD1 (1 << 1) | SD2 (1 << 2) */ + qcom,msm-mi2s-rx-lines = <0>; + qcom,msm-mi2s-tx-lines = <15>; /* SD3 (1 << 3) */ + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&quat_mi2s_active &quat_mi2s_sd0_active + &quat_mi2s_sd1_active + &quat_mi2s_sd2_active + &quat_mi2s_sd3_active>; + pinctrl-1 = <&quat_mi2s_sleep &quat_mi2s_sd0_sleep + &quat_mi2s_sd1_sleep + &quat_mi2s_sd2_sleep + &quat_mi2s_sd3_sleep>; + }; + }; + + ir: ir-receiver { + compatible = "gpio-ir-receiver"; + gpios = <&tlmm 120 1>; + pinctrl-names = "default"; + pinctrl-0 = <&ir_int>; + linux,rc-map-name = "rc-rc6-freebox"; + }; +}; + +&tlmm { + ir_int: ir_int { + mux { + pins = "gpio120"; + function = "gpio"; + }; + config { + pins = "gpio120"; + drive-strength = <6>; + bias-pull-up; + }; + }; + + spkr_1_sd_mediabox { + spkr_1_sd_sleep_mediabox: spkr_1_sd_sleep_mediabox { + mux { + pins = "gpio85"; + function = "gpio"; + }; + config { + pins = "gpio85"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; + input-enable; + }; + }; + spkr_1_sd_active_mediabox: spkr_1_sd_active_mediabox { + mux { + pins = "gpio85"; + function = "gpio"; + }; + config { + pins = "gpio85"; + drive-strength = <8>; /* 8 mA */ + bias-disable; + output-high; + }; + }; + }; + + spkr_2_sd_mediabox_mediabox { + spkr_2_sd_sleep_mediabox: spkr_2_sd_sleep_mediabox { + mux { + pins = "gpio112"; + function = "gpio"; + }; + config { + pins = "gpio112"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; + input-enable; + }; + }; + spkr_2_sd_active_mediabox: spkr_2_sd_active_mediabox { + mux { + pins = "gpio112"; + function = "gpio"; + }; + config { + pins = "gpio112"; + drive-strength = <8>; /* 8 mA */ + bias-disable; + output-high; + }; + }; + }; + + sdc2_cd_on_mediabox: sdc2_cd_on_mediabox { + mux { + pins = "gpio86"; + function = "gpio"; + }; + + config { + pins = "gpio86"; + bias-pull-up; /* pull up */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + sdc2_cd_off_mediabox: sdc2_cd_off_mediabox { + mux { + pins = "gpio86"; + function = "gpio"; + }; + + config { + pins = "gpio86"; + bias-pull-up; /* pull up */ + drive-strength = <2>; /* 2 MA */ + }; + }; +}; --- /dev/null 2019-10-24 16:47:25.704025805 +0200 +++ linux-4.4.115-fbx/arch/arm64/boot/dts/qcom/msm8998-audio.dtsi 2019-10-29 09:26:22.917196073 +0100 @@ -0,0 +1,56 @@ +/* + * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&msm_audio_ion { + qcom,smmu-version = <2>; + iommus = <&lpass_q6_smmu 1>; +}; + +&soc { + qcom,avtimer@170f7000 { + compatible = "qcom,avtimer"; + reg = <0x170f700c 0x4>, + <0x170f7010 0x4>; + reg-names = "avtimer_lsb_addr", "avtimer_msb_addr"; + qcom,clk-div = <27>; + }; + + clock_audio: audio_ext_clk { + status = "ok"; + compatible = "qcom,audio-ref-clk"; + qcom,audio-ref-clk-gpio = <&pm8998_gpios 13 0>; + clock-names = "osr_clk"; + clocks = <&clock_gcc clk_div_clk1>; + qcom,node_has_rpm_clock; + #clock-cells = <1>; + pinctrl-names = "sleep", "active"; + pinctrl-0 = <&spkr_i2s_clk_sleep>; + pinctrl-1 = <&spkr_i2s_clk_active>; + }; + + clock_audio_lnbb: audio_ext_clk_lnbb { + status = "ok"; + compatible = "qcom,audio-ref-clk"; + clock-names = "osr_clk"; + clocks = <&clock_gcc clk_ln_bb_clk2>; + qcom,node_has_rpm_clock; + #clock-cells = <1>; + }; +}; + +&slim_aud { + msm_dai_slim { + compatible = "qcom,msm-dai-slim"; + elemental-addr = [ff ff ff fe 17 02]; + }; +}; --- /dev/null 2019-10-24 16:47:25.704025805 +0200 +++ linux-4.4.115-fbx/arch/arm64/boot/dts/qcom/msm8998-audio-freebox.dtsi 2019-01-22 16:16:21.191225470 +0100 @@ -0,0 +1,87 @@ +/* + * Copyright (c) 2018, Freebox SAS. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&soc { + snd_freebox: sound-freebox { + compatible = "qcom,msm8998-asoc-snd-freebox"; + qcom,model = "msm8998-freebox-snd-card"; + qcom,ext-disp-audio-rx; + qcom,mi2s-audio-intf; + qcom,msm-mi2s-master = <1>, <1>, <0>, <0>; + qcom,msm-mi2s-ext-mclk = <1>, <0>, <0>, <0>; + + reg = <0x1711a000 0x4>, + <0x1711b000 0x4>, + <0x1711c000 0x4>, + <0x1711d000 0x4>; + reg-names = "lpaif_pri_mode_muxsel", + "lpaif_sec_mode_muxsel", + "lpaif_tert_mode_muxsel", + "lpaif_quat_mode_muxsel"; + + asoc-platform = <&pcm0>, <&pcm1>, <&pcm2>, <&voip>, <&voice>, + <&loopback>, <&compress>, <&hostless>, + <&afe>, <&lsm>, <&routing>, <&compr>, + <&pcm_noirq>, <&trans_loopback>; + asoc-platform-names = "msm-pcm-dsp.0", "msm-pcm-dsp.1", + "msm-pcm-dsp.2", "msm-voip-dsp", + "msm-pcm-voice", "msm-pcm-loopback", + "msm-compress-dsp", "msm-pcm-hostless", + "msm-pcm-afe", "msm-lsm-client", + "msm-pcm-routing", "msm-compr-dsp", + "msm-pcm-dsp-noirq", "msm-transcode-loopback"; + asoc-cpu = <&dai_hdmi>, <&dai_dp>, + <&dai_mi2s0>, <&dai_mi2s1>, + <&dai_mi2s2>, <&dai_mi2s3>, + <&dai_pri_auxpcm>, <&dai_sec_auxpcm>, + <&dai_tert_auxpcm>, <&dai_quat_auxpcm>, + <&sb_0_rx>, <&sb_0_tx>, <&sb_1_rx>, <&sb_1_tx>, + <&sb_2_rx>, <&sb_2_tx>, <&sb_3_rx>, <&sb_3_tx>, + <&sb_4_rx>, <&sb_4_tx>, <&sb_5_tx>, + <&afe_pcm_rx>, <&afe_pcm_tx>, <&afe_proxy_rx>, + <&afe_proxy_tx>, <&incall_record_rx>, + <&incall_record_tx>, <&incall_music_rx>, + <&incall_music_2_rx>, <&sb_5_rx>, <&sb_6_rx>, + <&sb_7_rx>, <&sb_7_tx>, <&sb_8_tx>, + <&usb_audio_rx>, <&usb_audio_tx>, + <&dai_pri_tdm_rx_0>, <&dai_pri_tdm_tx_0>, + <&dai_sec_tdm_rx_0>, <&dai_sec_tdm_tx_0>, + <&dai_tert_tdm_rx_0>, <&dai_tert_tdm_tx_0>, + <&dai_quat_tdm_rx_0>, <&dai_quat_tdm_tx_0>; + asoc-cpu-names = "msm-dai-q6-hdmi.8", "msm-dai-q6-dp.24608", + "msm-dai-q6-mi2s.0", "msm-dai-q6-mi2s.1", + "msm-dai-q6-mi2s.2", "msm-dai-q6-mi2s.3", + "msm-dai-q6-auxpcm.1", "msm-dai-q6-auxpcm.2", + "msm-dai-q6-auxpcm.3", "msm-dai-q6-auxpcm.4", + "msm-dai-q6-dev.16384", "msm-dai-q6-dev.16385", + "msm-dai-q6-dev.16386", "msm-dai-q6-dev.16387", + "msm-dai-q6-dev.16388", "msm-dai-q6-dev.16389", + "msm-dai-q6-dev.16390", "msm-dai-q6-dev.16391", + "msm-dai-q6-dev.16392", "msm-dai-q6-dev.16393", + "msm-dai-q6-dev.16395", "msm-dai-q6-dev.224", + "msm-dai-q6-dev.225", "msm-dai-q6-dev.241", + "msm-dai-q6-dev.240", "msm-dai-q6-dev.32771", + "msm-dai-q6-dev.32772", "msm-dai-q6-dev.32773", + "msm-dai-q6-dev.32770", "msm-dai-q6-dev.16394", + "msm-dai-q6-dev.16396", "msm-dai-q6-dev.16398", + "msm-dai-q6-dev.16399", "msm-dai-q6-dev.16401", + "msm-dai-q6-dev.28672", "msm-dai-q6-dev.28673", + "msm-dai-q6-tdm.36864", "msm-dai-q6-tdm.36865", + "msm-dai-q6-tdm.36880", "msm-dai-q6-tdm.36881", + "msm-dai-q6-tdm.36896", "msm-dai-q6-tdm.36897", + "msm-dai-q6-tdm.36912", "msm-dai-q6-tdm.36913"; + asoc-codec = <&stub_codec>, <&ext_disp_audio_codec>; + asoc-codec-names = "msm-stub-codec.1", + "msm-ext-disp-audio-codec-rx"; + }; +}; --- /dev/null 2019-10-24 16:47:25.704025805 +0200 +++ linux-4.4.115-fbx/arch/arm64/boot/dts/qcom/msm8998-audio-wcd.dtsi 2019-01-22 16:16:21.191225470 +0100 @@ -0,0 +1,632 @@ +/* + * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "msm8998-wsa881x.dtsi" + +&spi_10 { + status = "ok"; +}; + +&soc { + snd_9335: sound-9335 { + compatible = "qcom,msm8998-asoc-snd-tasha"; + qcom,model = "msm8998-tasha-snd-card"; + qcom,ext-disp-audio-rx; + qcom,wcn-btfm; + qcom,mi2s-audio-intf; + qcom,auxpcm-audio-intf; + qcom,msm-mi2s-master = <1>, <1>, <1>, <1>; + + reg = <0x1711a000 0x4>, + <0x1711b000 0x4>, + <0x1711c000 0x4>, + <0x1711d000 0x4>; + reg-names = "lpaif_pri_mode_muxsel", + "lpaif_sec_mode_muxsel", + "lpaif_tert_mode_muxsel", + "lpaif_quat_mode_muxsel"; + + qcom,audio-routing = + "AIF4 VI", "MCLK", + "RX_BIAS", "MCLK", + "MADINPUT", "MCLK", + "hifi amp", "LINEOUT1", + "hifi amp", "LINEOUT2", + "AMIC2", "MIC BIAS2", + "MIC BIAS2", "Headset Mic", + "AMIC3", "MIC BIAS2", + "MIC BIAS2", "ANCRight Headset Mic", + "AMIC4", "MIC BIAS2", + "MIC BIAS2", "ANCLeft Headset Mic", + "AMIC5", "MIC BIAS3", + "MIC BIAS3", "Handset Mic", + "AMIC6", "MIC BIAS4", + "MIC BIAS4", "Analog Mic6", + "DMIC0", "MIC BIAS1", + "MIC BIAS1", "Digital Mic0", + "DMIC1", "MIC BIAS1", + "MIC BIAS1", "Digital Mic1", + "DMIC2", "MIC BIAS3", + "MIC BIAS3", "Digital Mic2", + "DMIC3", "MIC BIAS3", + "MIC BIAS3", "Digital Mic3", + "DMIC4", "MIC BIAS4", + "MIC BIAS4", "Digital Mic4", + "DMIC5", "MIC BIAS4", + "MIC BIAS4", "Digital Mic5", + "SpkrLeft IN", "SPK1 OUT", + "SpkrRight IN", "SPK2 OUT"; + + qcom,msm-mbhc-hphl-swh = <0>; + qcom,msm-mbhc-gnd-swh = <0>; + qcom,us-euro-gpios = <&wcd_us_euro_gpio>; + qcom,hph-en0-gpio = <&hph_en0_gpio>; + qcom,hph-en1-gpio = <&hph_en1_gpio>; + qcom,tasha-mclk-clk-freq = <9600000>; + asoc-platform = <&pcm0>, <&pcm1>, <&pcm2>, <&voip>, <&voice>, + <&loopback>, <&compress>, <&hostless>, + <&afe>, <&lsm>, <&routing>, <&cpe>, <&compr>, + <&pcm_noirq>, <&cpe3>, <&trans_loopback>; + asoc-platform-names = "msm-pcm-dsp.0", "msm-pcm-dsp.1", + "msm-pcm-dsp.2", "msm-voip-dsp", + "msm-pcm-voice", "msm-pcm-loopback", + "msm-compress-dsp", "msm-pcm-hostless", + "msm-pcm-afe", "msm-lsm-client", + "msm-pcm-routing", "msm-cpe-lsm", + "msm-compr-dsp", "msm-pcm-dsp-noirq", + "msm-cpe-lsm.3", "msm-transcode-loopback"; + asoc-cpu = <&dai_hdmi>, <&dai_dp>, + <&dai_mi2s0>, <&dai_mi2s1>, + <&dai_mi2s2>, <&dai_mi2s3>, + <&dai_pri_auxpcm>, <&dai_sec_auxpcm>, + <&dai_tert_auxpcm>, <&dai_quat_auxpcm>, + <&sb_0_rx>, <&sb_0_tx>, <&sb_1_rx>, <&sb_1_tx>, + <&sb_2_rx>, <&sb_2_tx>, <&sb_3_rx>, <&sb_3_tx>, + <&sb_4_rx>, <&sb_4_tx>, <&sb_5_tx>, + <&afe_pcm_rx>, <&afe_pcm_tx>, <&afe_proxy_rx>, + <&afe_proxy_tx>, <&incall_record_rx>, + <&incall_record_tx>, <&incall_music_rx>, + <&incall_music_2_rx>, <&sb_5_rx>, <&sb_6_rx>, + <&sb_7_rx>, <&sb_7_tx>, <&sb_8_tx>, + <&usb_audio_rx>, <&usb_audio_tx>, + <&dai_pri_tdm_rx_0>, <&dai_pri_tdm_tx_0>, + <&dai_sec_tdm_rx_0>, <&dai_sec_tdm_tx_0>, + <&dai_tert_tdm_rx_0>, <&dai_tert_tdm_tx_0>, + <&dai_quat_tdm_rx_0>, <&dai_quat_tdm_tx_0>; + asoc-cpu-names = "msm-dai-q6-hdmi.8", "msm-dai-q6-dp.24608", + "msm-dai-q6-mi2s.0", "msm-dai-q6-mi2s.1", + "msm-dai-q6-mi2s.2", "msm-dai-q6-mi2s.3", + "msm-dai-q6-auxpcm.1", "msm-dai-q6-auxpcm.2", + "msm-dai-q6-auxpcm.3", "msm-dai-q6-auxpcm.4", + "msm-dai-q6-dev.16384", "msm-dai-q6-dev.16385", + "msm-dai-q6-dev.16386", "msm-dai-q6-dev.16387", + "msm-dai-q6-dev.16388", "msm-dai-q6-dev.16389", + "msm-dai-q6-dev.16390", "msm-dai-q6-dev.16391", + "msm-dai-q6-dev.16392", "msm-dai-q6-dev.16393", + "msm-dai-q6-dev.16395", "msm-dai-q6-dev.224", + "msm-dai-q6-dev.225", "msm-dai-q6-dev.241", + "msm-dai-q6-dev.240", "msm-dai-q6-dev.32771", + "msm-dai-q6-dev.32772", "msm-dai-q6-dev.32773", + "msm-dai-q6-dev.32770", "msm-dai-q6-dev.16394", + "msm-dai-q6-dev.16396", "msm-dai-q6-dev.16398", + "msm-dai-q6-dev.16399", "msm-dai-q6-dev.16401", + "msm-dai-q6-dev.28672", "msm-dai-q6-dev.28673", + "msm-dai-q6-tdm.36864", "msm-dai-q6-tdm.36865", + "msm-dai-q6-tdm.36880", "msm-dai-q6-tdm.36881", + "msm-dai-q6-tdm.36896", "msm-dai-q6-tdm.36897", + "msm-dai-q6-tdm.36912", "msm-dai-q6-tdm.36913"; + asoc-codec = <&stub_codec>, <&ext_disp_audio_codec>; + asoc-codec-names = "msm-stub-codec.1", + "msm-ext-disp-audio-codec-rx"; + qcom,wsa-max-devs = <2>; + qcom,wsa-devs = <&wsa881x_211>, <&wsa881x_212>, + <&wsa881x_213>, <&wsa881x_214>; + qcom,wsa-aux-dev-prefix = "SpkrLeft", "SpkrRight", + "SpkrLeft", "SpkrRight"; + + hph_en0_gpio: msm_cdc_pinctrl@67 { + compatible = "qcom,msm-cdc-pinctrl"; + pinctrl-names = "aud_active", "aud_sleep"; + pinctrl-0 = <&hph_en0_active>; + pinctrl-1 = <&hph_en0_idle>; + }; + + hph_en1_gpio: msm_cdc_pinctrl@68 { + compatible = "qcom,msm-cdc-pinctrl"; + pinctrl-names = "aud_active", "aud_sleep"; + pinctrl-0 = <&hph_en1_active>; + pinctrl-1 = <&hph_en1_idle>; + }; + }; + + snd_934x: sound-tavil { + compatible = "qcom,msm8998-asoc-snd-tavil"; + qcom,model = "msm8998-tavil-snd-card"; + qcom,ext-disp-audio-rx; + qcom,wcn-btfm; + qcom,mi2s-audio-intf; + qcom,auxpcm-audio-intf; + qcom,msm-mi2s-master = <1>, <1>, <1>, <1>; + + reg = <0x1711a000 0x4>, + <0x1711b000 0x4>, + <0x1711c000 0x4>, + <0x1711d000 0x4>; + reg-names = "lpaif_pri_mode_muxsel", + "lpaif_sec_mode_muxsel", + "lpaif_tert_mode_muxsel", + "lpaif_quat_mode_muxsel"; + + qcom,audio-routing = + "AIF4 VI", "MCLK", + "RX_BIAS", "MCLK", + "MADINPUT", "MCLK", + "hifi amp", "LINEOUT1", + "hifi amp", "LINEOUT2", + "AMIC2", "MIC BIAS2", + "MIC BIAS2", "Headset Mic", + "AMIC3", "MIC BIAS2", + "MIC BIAS2", "ANCRight Headset Mic", + "AMIC4", "MIC BIAS2", + "MIC BIAS2", "ANCLeft Headset Mic", + "AMIC5", "MIC BIAS3", + "MIC BIAS3", "Handset Mic", + "DMIC0", "MIC BIAS1", + "MIC BIAS1", "Digital Mic0", + "DMIC1", "MIC BIAS1", + "MIC BIAS1", "Digital Mic1", + "DMIC2", "MIC BIAS3", + "MIC BIAS3", "Digital Mic2", + "DMIC3", "MIC BIAS3", + "MIC BIAS3", "Digital Mic3", + "DMIC4", "MIC BIAS4", + "MIC BIAS4", "Digital Mic4", + "DMIC5", "MIC BIAS4", + "MIC BIAS4", "Digital Mic5", + "SpkrLeft IN", "SPK1 OUT", + "SpkrRight IN", "SPK2 OUT"; + + qcom,msm-mbhc-hphl-swh = <0>; + qcom,msm-mbhc-gnd-swh = <0>; + qcom,us-euro-gpios = <&tavil_us_euro_sw>; + qcom,hph-en0-gpio = <&tavil_hph_en0>; + qcom,hph-en1-gpio = <&tavil_hph_en1>; + qcom,tavil-mclk-clk-freq = <9600000>; + + qcom,usbc-analog-en1_gpio = <&wcd_usbc_analog_en1_gpio>; + qcom,usbc-analog-en2_n_gpio = <&wcd_usbc_analog_en2n_gpio>; + + asoc-platform = <&pcm0>, <&pcm1>, <&pcm2>, <&voip>, <&voice>, + <&loopback>, <&compress>, <&hostless>, + <&afe>, <&lsm>, <&routing>, <&cpe>, <&compr>, + <&pcm_noirq>, <&trans_loopback>; + asoc-platform-names = "msm-pcm-dsp.0", "msm-pcm-dsp.1", + "msm-pcm-dsp.2", "msm-voip-dsp", + "msm-pcm-voice", "msm-pcm-loopback", + "msm-compress-dsp", "msm-pcm-hostless", + "msm-pcm-afe", "msm-lsm-client", + "msm-pcm-routing", "msm-cpe-lsm", + "msm-compr-dsp", "msm-pcm-dsp-noirq", + "msm-transcode-loopback"; + asoc-cpu = <&dai_hdmi>, <&dai_dp>, + <&dai_mi2s0>, <&dai_mi2s1>, + <&dai_mi2s2>, <&dai_mi2s3>, + <&dai_pri_auxpcm>, <&dai_sec_auxpcm>, + <&dai_tert_auxpcm>, <&dai_quat_auxpcm>, + <&sb_0_rx>, <&sb_0_tx>, <&sb_1_rx>, <&sb_1_tx>, + <&sb_2_rx>, <&sb_2_tx>, <&sb_3_rx>, <&sb_3_tx>, + <&sb_4_rx>, <&sb_4_tx>, <&sb_5_tx>, + <&afe_pcm_rx>, <&afe_pcm_tx>, <&afe_proxy_rx>, + <&afe_proxy_tx>, <&incall_record_rx>, + <&incall_record_tx>, <&incall_music_rx>, + <&incall_music_2_rx>, <&sb_5_rx>, <&sb_6_rx>, + <&sb_7_rx>, <&sb_7_tx>, <&sb_8_tx>, + <&usb_audio_rx>, <&usb_audio_tx>, + <&dai_pri_tdm_rx_0>, <&dai_pri_tdm_tx_0>, + <&dai_sec_tdm_rx_0>, <&dai_sec_tdm_tx_0>, + <&dai_tert_tdm_rx_0>, <&dai_tert_tdm_tx_0>, + <&dai_quat_tdm_rx_0>, <&dai_quat_tdm_tx_0>; + asoc-cpu-names = "msm-dai-q6-hdmi.8", "msm-dai-q6-dp.24608", + "msm-dai-q6-mi2s.0", "msm-dai-q6-mi2s.1", + "msm-dai-q6-mi2s.2", "msm-dai-q6-mi2s.3", + "msm-dai-q6-auxpcm.1", "msm-dai-q6-auxpcm.2", + "msm-dai-q6-auxpcm.3", "msm-dai-q6-auxpcm.4", + "msm-dai-q6-dev.16384", "msm-dai-q6-dev.16385", + "msm-dai-q6-dev.16386", "msm-dai-q6-dev.16387", + "msm-dai-q6-dev.16388", "msm-dai-q6-dev.16389", + "msm-dai-q6-dev.16390", "msm-dai-q6-dev.16391", + "msm-dai-q6-dev.16392", "msm-dai-q6-dev.16393", + "msm-dai-q6-dev.16395", "msm-dai-q6-dev.224", + "msm-dai-q6-dev.225", "msm-dai-q6-dev.241", + "msm-dai-q6-dev.240", "msm-dai-q6-dev.32771", + "msm-dai-q6-dev.32772", "msm-dai-q6-dev.32773", + "msm-dai-q6-dev.32770", "msm-dai-q6-dev.16394", + "msm-dai-q6-dev.16396", "msm-dai-q6-dev.16398", + "msm-dai-q6-dev.16399", "msm-dai-q6-dev.16401", + "msm-dai-q6-dev.28672", "msm-dai-q6-dev.28673", + "msm-dai-q6-tdm.36864", "msm-dai-q6-tdm.36865", + "msm-dai-q6-tdm.36880", "msm-dai-q6-tdm.36881", + "msm-dai-q6-tdm.36896", "msm-dai-q6-tdm.36897", + "msm-dai-q6-tdm.36912", "msm-dai-q6-tdm.36913"; + asoc-codec = <&stub_codec>, <&ext_disp_audio_codec>; + asoc-codec-names = "msm-stub-codec.1", + "msm-ext-disp-audio-codec-rx"; + qcom,wsa-max-devs = <2>; + qcom,wsa-devs = <&wsa881x_0211>, <&wsa881x_0212>, + <&wsa881x_0213>, <&wsa881x_0214>; + qcom,wsa-aux-dev-prefix = "SpkrLeft", "SpkrRight", + "SpkrLeft", "SpkrRight"; + }; + + cpe: qcom,msm-cpe-lsm { + compatible = "qcom,msm-cpe-lsm"; + qcom,msm-cpe-lsm-id = <1>; + }; + + cpe3: qcom,msm-cpe-lsm@3 { + compatible = "qcom,msm-cpe-lsm"; + qcom,msm-cpe-lsm-id = <3>; + }; + + qcom,wcd-dsp-mgr { + compatible = "qcom,wcd-dsp-mgr"; + qcom,wdsp-components = <&wcd934x_cdc 0>, + <&wcd_spi_0 1>, + <&glink_spi_xprt_wdsp 2>; + qcom,img-filename = "cpe_9340"; + }; + + wcd_us_euro_gpio: msm_cdc_pinctrl@75 { + compatible = "qcom,msm-cdc-pinctrl"; + pinctrl-names = "aud_active", "aud_sleep"; + pinctrl-0 = <&wcd_gnd_mic_swap_active>; + pinctrl-1 = <&wcd_gnd_mic_swap_idle>; + }; + + wcd_usbc_analog_en1_gpio: msm_cdc_pinctrl@59 { + compatible = "qcom,msm-cdc-pinctrl"; + pinctrl-names = "aud_active", "aud_sleep"; + pinctrl-0 = <&wcd_usbc_analog_en1_active>; + pinctrl-1 = <&wcd_usbc_analog_en1_idle>; + }; + + wcd_usbc_analog_en2n_gpio: msm_cdc_pinctrl@60 { + compatible = "qcom,msm-cdc-pinctrl"; + pinctrl-names = "aud_active", "aud_sleep"; + pinctrl-0 = <&wcd_usbc_analog_en2n_active>; + pinctrl-1 = <&wcd_usbc_analog_en2n_idle>; + }; + + wcd9xxx_intc: wcd9xxx-irq { + status = "ok"; + compatible = "qcom,wcd9xxx-irq"; + interrupt-controller; + #interrupt-cells = <1>; + interrupt-parent = <&tlmm>; + qcom,gpio-connect = <&tlmm 54 0>; + pinctrl-names = "default"; + pinctrl-0 = <&wcd_intr_default>; + }; + + wcd_rst_gpio: msm_cdc_pinctrl@64 { + compatible = "qcom,msm-cdc-pinctrl"; + qcom,cdc-rst-n-gpio = <&tlmm 64 0>; + pinctrl-names = "aud_active", "aud_sleep"; + pinctrl-0 = <&cdc_reset_active>; + pinctrl-1 = <&cdc_reset_sleep>; + }; + + qocm,wcd-dsp-glink { + compatible = "qcom,wcd-dsp-glink"; + }; +}; + +&slim_aud { + tasha_codec { + compatible = "qcom,tasha-slim-pgd"; + elemental-addr = [00 01 A0 01 17 02]; + + interrupt-parent = <&wcd9xxx_intc>; + interrupts = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 + 17 18 19 20 21 22 23 24 25 26 27 28 29 + 30>; + + qcom,wcd-rst-gpio-node = <&wcd_rst_gpio>; + + clock-names = "wcd_clk", "wcd_native_clk"; + clocks = <&clock_audio clk_audio_pmi_clk>, + <&clock_audio clk_audio_ap_clk2>; + + cdc-vdd-buck-supply = <&pm8998_s4>; + qcom,cdc-vdd-buck-voltage = <1800000 1800000>; + qcom,cdc-vdd-buck-current = <650000>; + + cdc-buck-sido-supply = <&pm8998_s4>; + qcom,cdc-buck-sido-voltage = <1800000 1800000>; + qcom,cdc-buck-sido-current = <250000>; + + cdc-vdd-tx-h-supply = <&pm8998_s4>; + qcom,cdc-vdd-tx-h-voltage = <1800000 1800000>; + qcom,cdc-vdd-tx-h-current = <25000>; + + cdc-vdd-rx-h-supply = <&pm8998_s4>; + qcom,cdc-vdd-rx-h-voltage = <1800000 1800000>; + qcom,cdc-vdd-rx-h-current = <25000>; + + cdc-vddpx-1-supply = <&pm8998_s4>; + qcom,cdc-vddpx-1-voltage = <1800000 1800000>; + qcom,cdc-vddpx-1-current = <10000>; + + qcom,cdc-static-supplies = "cdc-vdd-buck", + "cdc-buck-sido", + "cdc-vdd-tx-h", + "cdc-vdd-rx-h", + "cdc-vddpx-1"; + + qcom,cdc-micbias1-mv = <1800>; + qcom,cdc-micbias2-mv = <1800>; + qcom,cdc-micbias3-mv = <1800>; + qcom,cdc-micbias4-mv = <1800>; + + qcom,cdc-mclk-clk-rate = <9600000>; + qcom,cdc-slim-ifd = "tasha-slim-ifd"; + qcom,cdc-slim-ifd-elemental-addr = [00 00 A0 01 17 02]; + qcom,cdc-dmic-sample-rate = <4800000>; + qcom,cdc-mad-dmic-rate = <600000>; + qcom,cdc-ecpp-dmic-rate = <1200000>; + }; + + wcd934x_cdc: tavil_codec { + compatible = "qcom,tavil-slim-pgd"; + elemental-addr = [00 01 50 02 17 02]; + + interrupt-parent = <&wcd9xxx_intc>; + interrupts = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 + 17 18 19 20 21 22 23 24 25 26 27 28 29 + 30 31>; + + qcom,wcd-rst-gpio-node = <&wcd_rst_gpio>; + + clock-names = "wcd_clk"; + clocks = <&clock_audio_lnbb clk_audio_pmi_lnbb_clk>; + + cdc-vdd-buck-supply = <&pm8998_s4>; + qcom,cdc-vdd-buck-voltage = <1800000 1800000>; + qcom,cdc-vdd-buck-current = <650000>; + + cdc-buck-sido-supply = <&pm8998_s4>; + qcom,cdc-buck-sido-voltage = <1800000 1800000>; + qcom,cdc-buck-sido-current = <250000>; + + cdc-vdd-tx-h-supply = <&pm8998_s4>; + qcom,cdc-vdd-tx-h-voltage = <1800000 1800000>; + qcom,cdc-vdd-tx-h-current = <25000>; + + cdc-vdd-rx-h-supply = <&pm8998_s4>; + qcom,cdc-vdd-rx-h-voltage = <1800000 1800000>; + qcom,cdc-vdd-rx-h-current = <25000>; + + cdc-vddpx-1-supply = <&pm8998_s4>; + qcom,cdc-vddpx-1-voltage = <1800000 1800000>; + qcom,cdc-vddpx-1-current = <10000>; + + qcom,cdc-static-supplies = "cdc-vdd-buck", + "cdc-buck-sido", + "cdc-vdd-tx-h", + "cdc-vdd-rx-h", + "cdc-vddpx-1"; + + qcom,cdc-micbias1-mv = <1800>; + qcom,cdc-micbias2-mv = <1800>; + qcom,cdc-micbias3-mv = <1800>; + qcom,cdc-micbias4-mv = <1800>; + + qcom,cdc-mclk-clk-rate = <9600000>; + qcom,cdc-slim-ifd = "tavil-slim-ifd"; + qcom,cdc-slim-ifd-elemental-addr = [00 00 50 02 17 02]; + qcom,cdc-dmic-sample-rate = <4800000>; + qcom,cdc-mad-dmic-rate = <600000>; + + qcom,wdsp-cmpnt-dev-name = "tavil_codec"; + + wcd_spi_0: wcd_spi { + compatible = "qcom,wcd-spi-v2"; + qcom,master-bus-num = <10>; + qcom,chip-select = <0>; + qcom,max-frequency = <24000000>; + qcom,mem-base-addr = <0x100000>; + }; + }; +}; + +&tlmm { + wcd9xxx_intr { + wcd_intr_default: wcd_intr_default{ + mux { + pins = "gpio54"; + function = "gpio"; + }; + + config { + pins = "gpio54"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* pull down */ + input-enable; + }; + }; + }; + + hph_en0_ctrl { + hph_en0_idle: hph_en0_idle { + mux { + pins = "gpio67"; + function = "gpio"; + }; + config { + pins = "gpio67"; + drive-strength = <2>; + bias-pull-down; + output-low; + }; + }; + hph_en0_active: hph_en0_active { + mux { + pins = "gpio67"; + function = "gpio"; + }; + config { + pins = "gpio67"; + drive-strength = <2>; + bias-disable; + output-high; + }; + }; + }; + + hph_en1_ctrl { + hph_en1_idle: hph_en1_idle { + mux { + pins = "gpio68"; + function = "gpio"; + }; + config { + pins = "gpio68"; + drive-strength = <2>; + bias-pull-down; + output-low; + }; + }; + hph_en1_active: hph_en1_active { + mux { + pins = "gpio68"; + function = "gpio"; + }; + config { + pins = "gpio68"; + drive-strength = <2>; + bias-disable; + output-high; + }; + }; + }; + + wcd_gnd_mic_swap { + wcd_gnd_mic_swap_idle: wcd_gnd_mic_swap_idle { + mux { + pins = "gpio75"; + function = "gpio"; + }; + config { + pins = "gpio75"; + drive-strength = <2>; + bias-pull-down; + output-low; + }; + }; + wcd_gnd_mic_swap_active: wcd_gnd_mic_swap_active { + mux { + pins = "gpio75"; + function = "gpio"; + }; + config { + pins = "gpio75"; + drive-strength = <2>; + bias-disable; + output-high; + }; + }; + }; + + wcd_usbc_analog_en1 { + wcd_usbc_analog_en1_idle: wcd_usbc_ana_en1_idle { + mux { + pins = "gpio59"; + function = "gpio"; + }; + config { + pins = "gpio59"; + drive-strength = <2>; + bias-pull-down; + output-low; + }; + }; + + wcd_usbc_analog_en1_active: wcd_usbc_ana_en1_active { + mux { + pins = "gpio59"; + function = "gpio"; + }; + config { + pins = "gpio59"; + drive-strength = <2>; + bias-disable; + output-high; + }; + }; + }; + + wcd_usbc_analog_en2n { + wcd_usbc_analog_en2n_idle: wcd_usbc_ana_en2n_idle { + mux { + pins = "gpio60"; + function = "gpio"; + }; + config { + pins = "gpio60"; + drive-strength = <2>; + bias-disable; + output-high; + }; + }; + + wcd_usbc_analog_en2n_active: wcd_usbc_ana_en2n_active { + mux { + pins = "gpio60"; + function = "gpio"; + }; + config { + pins = "gpio60"; + drive-strength = <2>; + bias-pull-down; + output-low; + }; + }; + }; + + cdc_reset_ctrl { + cdc_reset_sleep: cdc_reset_sleep { + mux { + pins = "gpio64"; + function = "gpio"; + }; + config { + pins = "gpio64"; + drive-strength = <16>; + bias-disable; + output-low; + }; + }; + cdc_reset_active:cdc_reset_active { + mux { + pins = "gpio64"; + function = "gpio"; + }; + config { + pins = "gpio64"; + drive-strength = <16>; + bias-pull-down; + output-high; + }; + }; + }; +}; --- /dev/null 2019-10-24 16:47:25.704025805 +0200 +++ linux-4.4.115-fbx/arch/arm64/boot/dts/qcom/msm8998-blsp.dtsi 2019-01-22 16:16:21.191225470 +0100 @@ -0,0 +1,863 @@ +/* + * Copyright (c) 2015-2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +/ { + aliases { + i2c1 = &i2c_1; + i2c2 = &i2c_2; + i2c3 = &i2c_3; + i2c4 = &i2c_4; + i2c5 = &i2c_5; + i2c6 = &i2c_6; + i2c7 = &i2c_7; + i2c8 = &i2c_8; + i2c9 = &i2c_9; + i2c10 = &i2c_10; + i2c11 = &i2c_11; + i2c12 = &i2c_12; + spi1 = &spi_1; + spi2 = &spi_2; + spi3 = &spi_3; + spi4 = &spi_4; + spi5 = &spi_5; + spi6 = &spi_6; + spi7 = &spi_7; + spi8 = &spi_8; + spi9 = &spi_9; + spi10 = &spi_10; + spi11 = &spi_11; + spi12 = &spi_12; + }; +}; + +#include "msm8998-pinctrl.dtsi" + +&soc { + dma_blsp1: qcom,sps-dma@0xc144000 { /* BLSP1 */ + #dma-cells = <4>; + compatible = "qcom,sps-dma"; + reg = <0xc144000 0x25000>; + interrupts = <0 238 0>; + qcom,summing-threshold = <0x10>; + }; + + dma_blsp2: qcom,sps-dma@0xc184000 { /* BLSP2 */ + #dma-cells = <4>; + compatible = "qcom,sps-dma"; + reg = <0xc184000 0x25000>; + interrupts = <0 239 0>; + qcom,summing-threshold = <0x10>; + }; + + i2c_1: i2c@c175000 { /* BLSP1 QUP1 */ + compatible = "qcom,i2c-msm-v2"; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "qup_phys_addr"; + reg = <0xC175000 0x600>; + interrupt-names = "qup_irq"; + interrupts = <0 95 0>; + dmas = <&dma_blsp1 6 64 0x20000020 0x20>, + <&dma_blsp1 7 32 0x20000020 0x20>; + dma-names = "tx", "rx"; + qcom,master-id = <86>; + qcom,clk-freq-out = <400000>; + qcom,clk-freq-in = <19200000>; + clock-names = "iface_clk", "core_clk"; + clocks = <&clock_gcc clk_gcc_blsp1_ahb_clk>, + <&clock_gcc clk_gcc_blsp1_qup1_i2c_apps_clk>; + pinctrl-names = "i2c_active", "i2c_sleep"; + pinctrl-0 = <&i2c_1_active>; + pinctrl-1 = <&i2c_1_sleep>; + status = "disabled"; + }; + + i2c_2: i2c@c176000 { /* BLSP1 QUP2 */ + compatible = "qcom,i2c-msm-v2"; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "qup_phys_addr"; + reg = <0xC176000 0x600>; + interrupt-names = "qup_irq"; + interrupts = <0 96 0>; + dmas = <&dma_blsp1 8 64 0x20000020 0x20>, + <&dma_blsp1 9 32 0x20000020 0x20>; + dma-names = "tx", "rx"; + qcom,master-id = <86>; + qcom,clk-freq-out = <400000>; + qcom,clk-freq-in = <19200000>; + clock-names = "iface_clk", "core_clk"; + clocks = <&clock_gcc clk_gcc_blsp1_ahb_clk>, + <&clock_gcc clk_gcc_blsp1_qup2_i2c_apps_clk>; + pinctrl-names = "i2c_active", "i2c_sleep"; + pinctrl-0 = <&i2c_2_active>; + pinctrl-1 = <&i2c_2_sleep>; + status = "disabled"; + }; + + i2c_3: i2c@c177000 { /* BLSP1 QUP3 */ + compatible = "qcom,i2c-msm-v2"; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "qup_phys_addr"; + reg = <0xC177000 0x600>; + interrupt-names = "qup_irq"; + interrupts = <0 97 0>; + dmas = <&dma_blsp1 10 64 0x20000020 0x20>, + <&dma_blsp1 11 32 0x20000020 0x20>; + dma-names = "tx", "rx"; + qcom,master-id = <86>; + qcom,clk-freq-out = <400000>; + qcom,clk-freq-in = <19200000>; + clock-names = "iface_clk", "core_clk"; + clocks = <&clock_gcc clk_gcc_blsp1_ahb_clk>, + <&clock_gcc clk_gcc_blsp1_qup3_i2c_apps_clk>; + pinctrl-names = "i2c_active", "i2c_sleep"; + pinctrl-0 = <&i2c_3_active>; + pinctrl-1 = <&i2c_3_sleep>; + status = "disabled"; + }; + + i2c_4: i2c@c178000 { /* BLSP1 QUP4 */ + compatible = "qcom,i2c-msm-v2"; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "qup_phys_addr"; + reg = <0xC178000 0x600>; + interrupt-names = "qup_irq"; + interrupts = <0 98 0>; + dmas = <&dma_blsp1 12 64 0x20000020 0x20>, + <&dma_blsp1 13 32 0x20000020 0x20>; + dma-names = "tx", "rx"; + qcom,master-id = <86>; + qcom,clk-freq-out = <400000>; + qcom,clk-freq-in = <19200000>; + clock-names = "iface_clk", "core_clk"; + clocks = <&clock_gcc clk_gcc_blsp1_ahb_clk>, + <&clock_gcc clk_gcc_blsp1_qup4_i2c_apps_clk>; + pinctrl-names = "i2c_active", "i2c_sleep"; + pinctrl-0 = <&i2c_4_active>; + pinctrl-1 = <&i2c_4_sleep>; + status = "disabled"; + }; + + i2c_5: i2c@c179000 { /* BLSP1 QUP5 */ + compatible = "qcom,i2c-msm-v2"; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "qup_phys_addr"; + reg = <0xC179000 0x600>; + interrupt-names = "qup_irq"; + interrupts = <0 99 0>; + dmas = <&dma_blsp1 14 64 0x20000020 0x20>, + <&dma_blsp1 15 32 0x20000020 0x20>; + dma-names = "tx", "rx"; + qcom,master-id = <86>; + qcom,clk-freq-out = <400000>; + qcom,clk-freq-in = <19200000>; + clock-names = "iface_clk", "core_clk"; + clocks = <&clock_gcc clk_gcc_blsp1_ahb_clk>, + <&clock_gcc clk_gcc_blsp1_qup5_i2c_apps_clk>; + pinctrl-names = "i2c_active", "i2c_sleep"; + pinctrl-0 = <&i2c_5_active>; + pinctrl-1 = <&i2c_5_sleep>; + status = "disabled"; + }; + + i2c_6: i2c@c17a000 { /* BLSP1 QUP6 */ + compatible = "qcom,i2c-msm-v2"; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "qup_phys_addr"; + reg = <0xC17A000 0x600>; + interrupt-names = "qup_irq"; + interrupts = <0 100 0>; + dmas = <&dma_blsp1 16 64 0x20000020 0x20>, + <&dma_blsp1 17 32 0x20000020 0x20>; + dma-names = "tx", "rx"; + qcom,master-id = <86>; + qcom,clk-freq-out = <400000>; + qcom,clk-freq-in = <19200000>; + clock-names = "iface_clk", "core_clk"; + clocks = <&clock_gcc clk_gcc_blsp1_ahb_clk>, + <&clock_gcc clk_gcc_blsp1_qup6_i2c_apps_clk>; + pinctrl-names = "i2c_active", "i2c_sleep"; + pinctrl-0 = <&i2c_6_active>; + pinctrl-1 = <&i2c_6_sleep>; + status = "disabled"; + }; + + i2c_7: i2c@c1b5000 { /* BLSP2 QUP1 */ + compatible = "qcom,i2c-msm-v2"; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "qup_phys_addr"; + reg = <0xC1B5000 0x600>; + interrupt-names = "qup_irq"; + interrupts = <0 101 0>; + dmas = <&dma_blsp2 6 64 0x20000020 0x20>, + <&dma_blsp2 7 32 0x20000020 0x20>; + dma-names = "tx", "rx"; + qcom,master-id = <84>; + qcom,clk-freq-out = <400000>; + qcom,clk-freq-in = <19200000>; + clock-names = "iface_clk", "core_clk"; + clocks = <&clock_gcc clk_gcc_blsp2_ahb_clk>, + <&clock_gcc clk_gcc_blsp2_qup1_i2c_apps_clk>; + pinctrl-names = "i2c_active", "i2c_sleep"; + pinctrl-0 = <&i2c_7_active>; + pinctrl-1 = <&i2c_7_sleep>; + status = "disabled"; + }; + + i2c_8: i2c@c1b6000 { /* BLSP2 QUP2 */ + compatible = "qcom,i2c-msm-v2"; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "qup_phys_addr"; + reg = <0xC1B6000 0x600>; + interrupt-names = "qup_irq"; + interrupts = <0 102 0>; + dmas = <&dma_blsp2 8 64 0x20000020 0x20>, + <&dma_blsp2 9 32 0x20000020 0x20>; + dma-names = "tx", "rx"; + qcom,master-id = <84>; + qcom,clk-freq-out = <400000>; + qcom,clk-freq-in = <19200000>; + clock-names = "iface_clk", "core_clk"; + clocks = <&clock_gcc clk_gcc_blsp2_ahb_clk>, + <&clock_gcc clk_gcc_blsp2_qup2_i2c_apps_clk>; + pinctrl-names = "i2c_active", "i2c_sleep"; + pinctrl-0 = <&i2c_8_active>; + pinctrl-1 = <&i2c_8_sleep>; + status = "disabled"; + }; + + i2c_9: i2c@c1b7000 { /* BLSP2 QUP3 */ + compatible = "qcom,i2c-msm-v2"; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "qup_phys_addr"; + reg = <0xC1B7000 0x600>; + interrupt-names = "qup_irq"; + interrupts = <0 103 0>; + dmas = <&dma_blsp2 10 64 0x20000020 0x20>, + <&dma_blsp2 11 32 0x20000020 0x20>; + dma-names = "tx", "rx"; + qcom,master-id = <84>; + qcom,clk-freq-out = <400000>; + qcom,clk-freq-in = <19200000>; + clock-names = "iface_clk", "core_clk"; + clocks = <&clock_gcc clk_gcc_blsp2_ahb_clk>, + <&clock_gcc clk_gcc_blsp2_qup3_i2c_apps_clk>; + pinctrl-names = "i2c_active", "i2c_sleep"; + pinctrl-0 = <&i2c_9_active>; + pinctrl-1 = <&i2c_9_sleep>; + status = "disabled"; + }; + + i2c_10: i2c@c1b8000 { /* BLSP2 QUP4 */ + compatible = "qcom,i2c-msm-v2"; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "qup_phys_addr"; + reg = <0xC1B8000 0x600>; + interrupt-names = "qup_irq"; + interrupts = <0 104 0>; + dmas = <&dma_blsp2 12 64 0x20000020 0x20>, + <&dma_blsp2 13 32 0x20000020 0x20>; + dma-names = "tx", "rx"; + qcom,master-id = <84>; + qcom,clk-freq-out = <400000>; + qcom,clk-freq-in = <19200000>; + clock-names = "iface_clk", "core_clk"; + clocks = <&clock_gcc clk_gcc_blsp2_ahb_clk>, + <&clock_gcc clk_gcc_blsp2_qup4_i2c_apps_clk>; + pinctrl-names = "i2c_active", "i2c_sleep"; + pinctrl-0 = <&i2c_10_active>; + pinctrl-1 = <&i2c_10_sleep>; + status = "disabled"; + }; + + i2c_11: i2c@c1b9000 { /* BLSP2 QUP5 */ + compatible = "qcom,i2c-msm-v2"; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "qup_phys_addr"; + reg = <0xC1B9000 0x600>; + interrupt-names = "qup_irq"; + interrupts = <0 105 0>; + dmas = <&dma_blsp2 14 64 0x20000020 0x20>, + <&dma_blsp2 15 32 0x20000020 0x20>; + dma-names = "tx", "rx"; + qcom,master-id = <84>; + qcom,clk-freq-out = <400000>; + qcom,clk-freq-in = <19200000>; + clock-names = "iface_clk", "core_clk"; + clocks = <&clock_gcc clk_gcc_blsp2_ahb_clk>, + <&clock_gcc clk_gcc_blsp2_qup5_i2c_apps_clk>; + pinctrl-names = "i2c_active", "i2c_sleep"; + pinctrl-0 = <&i2c_11_active>; + pinctrl-1 = <&i2c_11_sleep>; + status = "disabled"; + }; + + i2c_12: i2c@c1ba000 { /* BLSP2 QUP6 */ + compatible = "qcom,i2c-msm-v2"; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "qup_phys_addr"; + reg = <0xC1BA000 0x600>; + interrupt-names = "qup_irq"; + interrupts = <0 106 0>; + dmas = <&dma_blsp2 16 64 0x20000020 0x20>, + <&dma_blsp2 17 32 0x20000020 0x20>; + dma-names = "tx", "rx"; + qcom,master-id = <84>; + qcom,clk-freq-out = <400000>; + qcom,clk-freq-in = <19200000>; + clock-names = "iface_clk", "core_clk"; + clocks = <&clock_gcc clk_gcc_blsp2_ahb_clk>, + <&clock_gcc clk_gcc_blsp2_qup6_i2c_apps_clk>; + pinctrl-names = "i2c_active", "i2c_sleep"; + pinctrl-0 = <&i2c_12_active>; + pinctrl-1 = <&i2c_12_sleep>; + status = "disabled"; + }; + + spi_1: spi@c175000 { /* BLSP1 QUP1 */ + compatible = "qcom,spi-qup-v2"; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "spi_physical", "spi_bam_physical"; + reg = <0xC175000 0x600>, + <0xC144000 0x25000>; + interrupt-names = "spi_irq", "spi_bam_irq"; + interrupts = <0 95 0>, <0 238 0>; + spi-max-frequency = <50000000>; + qcom,use-bam; + qcom,ver-reg-exists; + qcom,bam-consumer-pipe-index = <6>; + qcom,bam-producer-pipe-index = <7>; + qcom,master-id = <86>; + qcom,use-pinctrl; + pinctrl-names = "spi_default", "spi_sleep"; + pinctrl-0 = <&spi_1_active>; + pinctrl-1 = <&spi_1_sleep>; + clock-names = "iface_clk", "core_clk"; + clocks = <&clock_gcc clk_gcc_blsp1_ahb_clk>, + <&clock_gcc clk_gcc_blsp1_qup1_spi_apps_clk>; + status = "disabled"; + }; + + spi_2: spi@c176000 { /* BLSP1 QUP2 */ + compatible = "qcom,spi-qup-v2"; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "spi_physical", "spi_bam_physical"; + reg = <0xC176000 0x600>, + <0xC144000 0x25000>; + interrupt-names = "spi_irq", "spi_bam_irq"; + interrupts = <0 96 0>, <0 238 0>; + spi-max-frequency = <50000000>; + qcom,use-bam; + qcom,ver-reg-exists; + qcom,bam-consumer-pipe-index = <8>; + qcom,bam-producer-pipe-index = <9>; + qcom,master-id = <86>; + qcom,use-pinctrl; + pinctrl-names = "spi_default", "spi_sleep"; + pinctrl-0 = <&spi_2_active>; + pinctrl-1 = <&spi_2_sleep>; + clock-names = "iface_clk", "core_clk"; + clocks = <&clock_gcc clk_gcc_blsp1_ahb_clk>, + <&clock_gcc clk_gcc_blsp1_qup2_spi_apps_clk>; + status = "disabled"; + }; + + spi_3: spi@c177000 { /* BLSP1 QUP3 */ + compatible = "qcom,spi-qup-v2"; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "spi_physical", "spi_bam_physical"; + reg = <0xC177000 0x600>, + <0xC144000 0x25000>; + interrupt-names = "spi_irq", "spi_bam_irq"; + interrupts = <0 97 0>, <0 238 0>; + spi-max-frequency = <50000000>; + qcom,use-bam; + qcom,ver-reg-exists; + qcom,bam-consumer-pipe-index = <10>; + qcom,bam-producer-pipe-index = <11>; + qcom,master-id = <86>; + qcom,use-pinctrl; + pinctrl-names = "spi_default", "spi_sleep"; + pinctrl-0 = <&spi_3_active>; + pinctrl-1 = <&spi_3_sleep>; + clock-names = "iface_clk", "core_clk"; + clocks = <&clock_gcc clk_gcc_blsp1_ahb_clk>, + <&clock_gcc clk_gcc_blsp1_qup3_spi_apps_clk>; + status = "disabled"; + }; + + spi_4: spi@c178000 { /* BLSP1 QUP4 */ + compatible = "qcom,spi-qup-v2"; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "spi_physical", "spi_bam_physical"; + reg = <0xC178000 0x600>, + <0xC144000 0x25000>; + interrupt-names = "spi_irq", "spi_bam_irq"; + interrupts = <0 98 0>, <0 238 0>; + spi-max-frequency = <50000000>; + qcom,use-bam; + qcom,ver-reg-exists; + qcom,bam-consumer-pipe-index = <12>; + qcom,bam-producer-pipe-index = <13>; + qcom,master-id = <86>; + qcom,use-pinctrl; + pinctrl-names = "spi_default", "spi_sleep"; + pinctrl-0 = <&spi_4_active>; + pinctrl-1 = <&spi_4_sleep>; + clock-names = "iface_clk", "core_clk"; + clocks = <&clock_gcc clk_gcc_blsp1_ahb_clk>, + <&clock_gcc clk_gcc_blsp1_qup4_spi_apps_clk>; + status = "disabled"; + }; + + spi_5: spi@c179000 { /* BLSP1 QUP5 */ + compatible = "qcom,spi-qup-v2"; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "spi_physical", "spi_bam_physical"; + reg = <0xC179000 0x600>, + <0xC144000 0x25000>; + interrupt-names = "spi_irq", "spi_bam_irq"; + interrupts = <0 99 0>, <0 238 0>; + spi-max-frequency = <50000000>; + qcom,use-bam; + qcom,ver-reg-exists; + qcom,bam-consumer-pipe-index = <14>; + qcom,bam-producer-pipe-index = <15>; + qcom,master-id = <86>; + qcom,use-pinctrl; + pinctrl-names = "spi_default", "spi_sleep"; + pinctrl-0 = <&spi_5_active>; + pinctrl-1 = <&spi_5_sleep>; + clock-names = "iface_clk", "core_clk"; + clocks = <&clock_gcc clk_gcc_blsp1_ahb_clk>, + <&clock_gcc clk_gcc_blsp1_qup5_spi_apps_clk>; + status = "disabled"; + }; + + spi_6: spi@c17a000 { /* BLSP1 QUP6 */ + compatible = "qcom,spi-qup-v2"; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "spi_physical", "spi_bam_physical"; + reg = <0xC17A000 0x600>, + <0xC144000 0x25000>; + interrupt-names = "spi_irq", "spi_bam_irq"; + interrupts = <0 100 0>, <0 238 0>; + spi-max-frequency = <50000000>; + qcom,use-bam; + qcom,ver-reg-exists; + qcom,bam-consumer-pipe-index = <16>; + qcom,bam-producer-pipe-index = <17>; + qcom,master-id = <86>; + qcom,use-pinctrl; + pinctrl-names = "spi_default", "spi_sleep"; + pinctrl-0 = <&spi_6_active>; + pinctrl-1 = <&spi_6_sleep>; + clock-names = "iface_clk", "core_clk"; + clocks = <&clock_gcc clk_gcc_blsp1_ahb_clk>, + <&clock_gcc clk_gcc_blsp1_qup6_spi_apps_clk>; + status = "disabled"; + }; + + + spi_7: spi@c1b5000 { /* BLSP2 QUP1 */ + compatible = "qcom,spi-qup-v2"; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "spi_physical", "spi_bam_physical"; + reg = <0xC1B5000 0x600>, + <0xC184000 0x25000>; + interrupt-names = "spi_irq", "spi_bam_irq"; + interrupts = <0 101 0>, <0 239 0>; + spi-max-frequency = <50000000>; + qcom,use-bam; + qcom,ver-reg-exists; + qcom,bam-consumer-pipe-index = <6>; + qcom,bam-producer-pipe-index = <7>; + qcom,master-id = <84>; + qcom,use-pinctrl; + pinctrl-names = "spi_default", "spi_sleep"; + pinctrl-0 = <&spi_7_active>; + pinctrl-1 = <&spi_7_sleep>; + clock-names = "iface_clk", "core_clk"; + clocks = <&clock_gcc clk_gcc_blsp2_ahb_clk>, + <&clock_gcc clk_gcc_blsp2_qup1_spi_apps_clk>; + status = "disabled"; + }; + + spi_8: spi@c1b6000 { /* BLSP2 QUP2 */ + compatible = "qcom,spi-qup-v2"; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "spi_physical", "spi_bam_physical"; + reg = <0xC1B6000 0x600>, + <0xC184000 0x25000>; + interrupt-names = "spi_irq", "spi_bam_irq"; + interrupts = <0 102 0>, <0 239 0>; + spi-max-frequency = <50000000>; + qcom,use-bam; + qcom,ver-reg-exists; + qcom,bam-consumer-pipe-index = <8>; + qcom,bam-producer-pipe-index = <9>; + qcom,master-id = <84>; + qcom,use-pinctrl; + pinctrl-names = "spi_default", "spi_sleep"; + pinctrl-0 = <&spi_8_active>; + pinctrl-1 = <&spi_8_sleep>; + clock-names = "iface_clk", "core_clk"; + clocks = <&clock_gcc clk_gcc_blsp2_ahb_clk>, + <&clock_gcc clk_gcc_blsp2_qup2_spi_apps_clk>; + status = "disabled"; + }; + + spi_9: spi@c1b7000 { /* BLSP2 QUP3 */ + compatible = "qcom,spi-qup-v2"; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "spi_physical", "spi_bam_physical"; + reg = <0xC1B7000 0x600>, + <0xC184000 0x25000>; + interrupt-names = "spi_irq", "spi_bam_irq"; + interrupts = <0 103 0>, <0 239 0>; + spi-max-frequency = <50000000>; + qcom,use-bam; + qcom,ver-reg-exists; + qcom,bam-consumer-pipe-index = <10>; + qcom,bam-producer-pipe-index = <11>; + qcom,master-id = <84>; + qcom,use-pinctrl; + pinctrl-names = "spi_default", "spi_sleep"; + pinctrl-0 = <&spi_9_active>; + pinctrl-1 = <&spi_9_sleep>; + clock-names = "iface_clk", "core_clk"; + clocks = <&clock_gcc clk_gcc_blsp2_ahb_clk>, + <&clock_gcc clk_gcc_blsp2_qup3_spi_apps_clk>; + status = "disabled"; + }; + + spi_10: spi@c1b8000 { /* BLSP2 QUP4 */ + compatible = "qcom,spi-qup-v2"; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "spi_physical", "spi_bam_physical"; + reg = <0xC1B8000 0x600>, + <0xC184000 0x25000>; + interrupt-names = "spi_irq", "spi_bam_irq"; + interrupts = <0 104 0>, <0 239 0>; + spi-max-frequency = <50000000>; + qcom,use-bam; + qcom,ver-reg-exists; + qcom,bam-consumer-pipe-index = <12>; + qcom,bam-producer-pipe-index = <13>; + qcom,master-id = <84>; + qcom,use-pinctrl; + pinctrl-names = "spi_default", "spi_sleep"; + pinctrl-0 = <&spi_10_active>; + pinctrl-1 = <&spi_10_sleep>; + clock-names = "iface_clk", "core_clk"; + clocks = <&clock_gcc clk_gcc_blsp2_ahb_clk>, + <&clock_gcc clk_gcc_blsp2_qup4_spi_apps_clk>; + status = "disabled"; + }; + + spi_11: spi@c1b9000 { /* BLSP2 QUP5 */ + compatible = "qcom,spi-qup-v2"; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "spi_physical", "spi_bam_physical"; + reg = <0xC1B9000 0x600>, + <0xC184000 0x25000>; + interrupt-names = "spi_irq", "spi_bam_irq"; + interrupts = <0 105 0>, <0 239 0>; + spi-max-frequency = <50000000>; + qcom,use-bam; + qcom,ver-reg-exists; + + qcom,bam-consumer-pipe-index = <14>; + qcom,bam-producer-pipe-index = <15>; + qcom,master-id = <84>; + qcom,use-pinctrl; + pinctrl-names = "spi_default", "spi_sleep"; + pinctrl-0 = <&spi_11_active>; + pinctrl-1 = <&spi_11_sleep>; + clock-names = "iface_clk", "core_clk"; + clocks = <&clock_gcc clk_gcc_blsp2_ahb_clk>, + <&clock_gcc clk_gcc_blsp2_qup5_spi_apps_clk>; + status = "disabled"; + }; + + spi_12: spi@c1ba000 { /* BLSP2 QUP6 */ + compatible = "qcom,spi-qup-v2"; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "spi_physical", "spi_bam_physical"; + reg = <0xC1BA000 0x600>, + <0xC184000 0x25000>; + interrupt-names = "spi_irq", "spi_bam_irq"; + interrupts = <0 106 0>, <0 239 0>; + spi-max-frequency = <50000000>; + qcom,use-bam; + qcom,ver-reg-exists; + qcom,bam-consumer-pipe-index = <16>; + qcom,bam-producer-pipe-index = <17>; + qcom,master-id = <84>; + qcom,use-pinctrl; + pinctrl-names = "spi_default", "spi_sleep"; + pinctrl-0 = <&spi_12_active>; + pinctrl-1 = <&spi_12_sleep>; + clock-names = "iface_clk", "core_clk"; + clocks = <&clock_gcc clk_gcc_blsp2_ahb_clk>, + <&clock_gcc clk_gcc_blsp2_qup6_spi_apps_clk>; + status = "disabled"; + }; + + + blsp1_uart1_hs: uart@c16f000 { /* BLSP1 UART1 */ + compatible = "qcom,msm-hsuart-v14"; + reg = <0xC16F000 0x200>, + <0xC144000 0x25000>; + reg-names = "core_mem", "bam_mem"; + interrupt-names = "core_irq", "bam_irq", "wakeup_irq"; + #address-cells = <0>; + interrupt-parent = <&blsp1_uart1_hs>; + interrupts = <0 1 2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0xffffffff>; + interrupt-map = <0 &intc 0 0 107 0 + 1 &intc 0 0 238 0 + 2 &tlmm 1 0>; + + qcom,inject-rx-on-wakeup; + qcom,rx-char-to-inject = <0xFD>; + + qcom,bam-tx-ep-pipe-index = <0>; + qcom,bam-rx-ep-pipe-index = <1>; + qcom,master-id = <86>; + clock-names = "core_clk", "iface_clk"; + clocks = <&clock_gcc clk_gcc_blsp1_uart1_apps_clk>, + <&clock_gcc clk_gcc_blsp1_ahb_clk>; + pinctrl-names = "sleep", "default"; + pinctrl-0 = <&blsp1_uart1_sleep>; + pinctrl-1 = <&blsp1_uart1_active>; + + qcom,msm-bus,name = "buart1"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <86 512 0 0>, + <86 512 500 800>; + status = "disabled"; + }; + + blsp1_uart2_hs: uart@c170000 { /* BLSP1 UART2 */ + compatible = "qcom,msm-hsuart-v14"; + reg = <0xC170000 0x200>, + <0xC144000 0x25000>; + reg-names = "core_mem", "bam_mem"; + interrupt-names = "core_irq", "bam_irq", "wakeup_irq"; + #address-cells = <0>; + interrupt-parent = <&blsp1_uart2_hs>; + interrupts = <0 1 2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0xffffffff>; + interrupt-map = <0 &intc 0 0 108 0 + 1 &intc 0 0 238 0 + 2 &tlmm 34 0>; + + qcom,inject-rx-on-wakeup; + qcom,rx-char-to-inject = <0xFD>; + + qcom,bam-tx-ep-pipe-index = <2>; + qcom,bam-rx-ep-pipe-index = <3>; + qcom,master-id = <86>; + clock-names = "core_clk", "iface_clk"; + clocks = <&clock_gcc clk_gcc_blsp1_uart2_apps_clk>, + <&clock_gcc clk_gcc_blsp1_ahb_clk>; + pinctrl-names = "sleep", "default"; + pinctrl-0 = <&blsp1_uart2_sleep>; + pinctrl-1 = <&blsp1_uart2_active>; + + qcom,msm-bus,name = "buart2"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <86 512 0 0>, + <86 512 500 800>; + status = "disabled"; + }; + + blsp1_uart3_hs: uart@c171000 { /* BLSP1 UART3 */ + compatible = "qcom,msm-hsuart-v14"; + reg = <0xC171000 0x200>, + <0xC144000 0x25000>; + reg-names = "core_mem", "bam_mem"; + interrupt-names = "core_irq", "bam_irq", "wakeup_irq"; + #address-cells = <0>; + interrupt-parent = <&blsp1_uart3_hs>; + interrupts = <0 1 2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0xffffffff>; + interrupt-map = <0 &intc 0 0 109 0 + 1 &intc 0 0 238 0 + 2 &tlmm 46 0>; + + qcom,inject-rx-on-wakeup; + qcom,rx-char-to-inject = <0xFD>; + + qcom,bam-tx-ep-pipe-index = <4>; + qcom,bam-rx-ep-pipe-index = <5>; + qcom,master-id = <86>; + clock-names = "core_clk", "iface_clk"; + clocks = <&clock_gcc clk_gcc_blsp1_uart3_apps_clk>, + <&clock_gcc clk_gcc_blsp1_ahb_clk>; + pinctrl-names = "sleep", "default"; + pinctrl-0 = <&blsp1_uart3_tx_sleep>, <&blsp1_uart3_rxcts_sleep>, + <&blsp1_uart3_rfr_sleep>; + pinctrl-1 = <&blsp1_uart3_tx_active>, + <&blsp1_uart3_rxcts_active>, <&blsp1_uart3_rfr_active>; + + qcom,msm-bus,name = "buart3"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <86 512 0 0>, + <86 512 500 800>; + status = "disabled"; + }; + + blsp2_uart1_hs: uart@c1af000 { /* BLSP2 UART1 */ + compatible = "qcom,msm-hsuart-v14"; + reg = <0xC1AF000 0x200>, + <0xC184000 0x25000>; + reg-names = "core_mem", "bam_mem"; + interrupt-names = "core_irq", "bam_irq", "wakeup_irq"; + #address-cells = <0>; + interrupt-parent = <&blsp2_uart1_hs>; + interrupts = <0 1 2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0xffffffff>; + interrupt-map = <0 &intc 0 0 113 0 + 1 &intc 0 0 239 0 + 2 &tlmm 54 0>; + + qcom,inject-rx-on-wakeup; + qcom,rx-char-to-inject = <0xFD>; + + qcom,bam-tx-ep-pipe-index = <0>; + qcom,bam-rx-ep-pipe-index = <1>; + qcom,master-id = <84>; + clock-names = "core_clk", "iface_clk"; + clocks = <&clock_gcc clk_gcc_blsp2_uart1_apps_clk>, + <&clock_gcc clk_gcc_blsp2_ahb_clk>; + pinctrl-names = "sleep", "default"; + pinctrl-0 = <&blsp2_uart1_sleep>; + pinctrl-1 = <&blsp2_uart1_active>; + + qcom,msm-bus,name = "buart1"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <86 512 0 0>, + <86 512 500 800>; + status = "disabled"; + }; + + blsp2_uart2_hs: uart@c1b0000 { /* BLSP2 UART2 */ + compatible = "qcom,msm-hsuart-v14"; + reg = <0xC1B0000 0x200>, + <0xC184000 0x25000>; + reg-names = "core_mem", "bam_mem"; + interrupt-names = "core_irq", "bam_irq", "wakeup_irq"; + #address-cells = <0>; + interrupt-parent = <&blsp2_uart2_hs>; + interrupts = <0 1 2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0xffffffff>; + interrupt-map = <0 &intc 0 0 114 0 + 1 &intc 0 0 239 0 + 2 &tlmm 5 0>; + + qcom,inject-rx-on-wakeup; + qcom,rx-char-to-inject = <0xFD>; + + qcom,bam-tx-ep-pipe-index = <2>; + qcom,bam-rx-ep-pipe-index = <3>; + qcom,master-id = <84>; + clock-names = "core_clk", "iface_clk"; + clocks = <&clock_gcc clk_gcc_blsp2_uart2_apps_clk>, + <&clock_gcc clk_gcc_blsp2_ahb_clk>; + pinctrl-names = "sleep", "default"; + pinctrl-0 = <&blsp2_uart2_sleep>; + pinctrl-1 = <&blsp2_uart2_active>; + + qcom,msm-bus,name = "buart2"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <86 512 0 0>, + <86 512 500 800>; + status = "disabled"; + }; + + blsp2_uart3_hs: uart@c1b1000 { /* BLSP2 UART3 */ + compatible = "qcom,msm-hsuart-v14"; + reg = <0xC1B1000 0x200>, + <0xC184000 0x25000>; + reg-names = "core_mem", "bam_mem"; + interrupt-names = "core_irq", "bam_irq", "wakeup_irq"; + #address-cells = <0>; + interrupt-parent = <&blsp2_uart3_hs>; + interrupts = <0 1 2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0xffffffff>; + interrupt-map = <0 &intc 0 0 115 0 + 1 &intc 0 0 239 0 + 2 &tlmm 50 0>; + + qcom,inject-rx-on-wakeup; + qcom,rx-char-to-inject = <0xFD>; + + qcom,bam-tx-ep-pipe-index = <4>; + qcom,bam-rx-ep-pipe-index = <5>; + qcom,master-id = <84>; + clock-names = "core_clk", "iface_clk"; + clocks = <&clock_gcc clk_gcc_blsp2_uart3_apps_clk>, + <&clock_gcc clk_gcc_blsp2_ahb_clk>; + pinctrl-names = "sleep", "default"; + pinctrl-0 = <&blsp2_uart3_sleep>; + pinctrl-1 = <&blsp2_uart3_active>; + + qcom,msm-bus,name = "buart3"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <86 512 0 0>, + <86 512 500 800>; + status = "disabled"; + }; +}; --- /dev/null 2019-10-24 16:47:25.704025805 +0200 +++ linux-4.4.115-fbx/arch/arm64/boot/dts/qcom/msm8998-bus.dtsi 2019-01-22 16:16:21.191225470 +0100 @@ -0,0 +1,1467 @@ +/* Copyright (c) 2016, The Linux Foundation. All rights reserved. + * + * This program is Mree software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +&soc { + ad_hoc_bus: ad-hoc-bus { + /*Version = 4 */ + compatible = "qcom,msm-bus-device"; + reg = <0x1620000 0x40000>, + <0x1000000 0x80000>, + <0x1500000 0x10000>, + <0x1660000 0x60000>, + <0x1700000 0x60000>, + <0x17900000 0x10000>, + <0x1740000 0x10000>, + <0x1740000 0x10000>; + + reg-names = "snoc-base", "bimc-base", "cnoc-base", + "a1noc-base", "a2noc-base", "gnoc-base", + "mmnoc-ahb-base", "mnoc-base"; + + /*Buses*/ + fab_a1noc: fab-a1noc { + cell-id = ; + label = "fab-a1noc"; + qcom,fab-dev; + qcom,base-name = "a1noc-base"; + qcom,bus-type = <1>; + qcom,qos-off = <4096>; + qcom,base-offset = <36864>; + clock-names = "bus_clk", "bus_a_clk"; + clocks = <&clock_gcc clk_aggre1_noc_clk>, + <&clock_gcc clk_aggre1_noc_a_clk>; + qcom,node-qos-clks { + clock-names = + "clk-ufs-axi-clk", + "clk-aggre1-ufs-axi-no-rate", + "clk-aggre1-usb3-axi-cfg-no-rate", + "clk-blsp2-ahb-no-rate"; + clocks = + <&clock_gcc clk_gcc_ufs_axi_clk>, + <&clock_gcc clk_gcc_aggre1_ufs_axi_clk>, + <&clock_gcc clk_gcc_aggre1_usb3_axi_clk>, + <&clock_gcc clk_gcc_blsp2_ahb_clk>; + }; + }; + + fab_a2noc: fab-a2noc { + cell-id = ; + label = "fab-a2noc"; + qcom,fab-dev; + qcom,base-name = "a2noc-base"; + qcom,bus-type = <1>; + qcom,qos-off = <4096>; + qcom,base-offset = <20480>; + clock-names = "bus_clk", "bus_a_clk"; + clocks = <&clock_gcc clk_aggre2_noc_clk>, + <&clock_gcc clk_aggre2_noc_a_clk>; + qcom,node-qos-clks { + clock-names = + "clk-ipa-clk", + "clk-sdcc2-ahb-no-rate", + "clk-sdcc4-ahb-no-rate", + "clk-blsp1-ahb-no-rate"; + clocks = + <&clock_gcc clk_ipa_clk>, + <&clock_gcc clk_gcc_sdcc2_ahb_clk>, + <&clock_gcc clk_gcc_sdcc4_ahb_clk>, + <&clock_gcc clk_gcc_blsp1_ahb_clk>; + }; + }; + + fab_bimc: fab-bimc { + cell-id = ; + label = "fab-bimc"; + qcom,fab-dev; + qcom,base-name = "bimc-base"; + qcom,bus-type = <2>; + qcom,util-fact = <153>; + clock-names = "bus_clk", "bus_a_clk"; + clocks = <&clock_gcc clk_bimc_msmbus_clk>, + <&clock_gcc clk_bimc_msmbus_a_clk>; + }; + + fab_cnoc: fab-cnoc { + cell-id = ; + label = "fab-cnoc"; + qcom,fab-dev; + qcom,base-name = "cnoc-base"; + qcom,bus-type = <1>; + clock-names = "bus_clk", "bus_a_clk"; + clocks = <&clock_gcc clk_cnoc_clk>, + <&clock_gcc clk_cnoc_a_clk>; + }; + + fab_cr_virt: fab-cr_virt { + cell-id = ; + label = "fab-cr_virt"; + qcom,virt-dev; + qcom,base-name = "cr_virt-base"; + qcom,bypass-qos-prg; + }; + + fab_gnoc: fab-gnoc { + cell-id = ; + label = "fab-gnoc"; + qcom,virt-dev; + qcom,base-name = "gnoc-base"; + qcom,bypass-qos-prg; + }; + + fab_mnoc: fab-mnoc { + cell-id = ; + label = "fab-mnoc"; + qcom,fab-dev; + qcom,base-name = "mnoc-base"; + qcom,bus-type = <1>; + qcom,qos-off = <4096>; + qcom,base-offset = <16384>; + qcom,util-fact = <153>; + clock-names = "bus_clk", "bus_a_clk"; + clocks = <&clock_gcc clk_mmssnoc_axi_clk>, + <&clock_gcc clk_mmssnoc_axi_a_clk>; + clk-camss-ahb-no-rate-supply = + <&gdsc_camss_top>; + clk-video-ahb-no-rate-supply = + <&gdsc_venus>; + clk-video-axi-no-rate-supply = + <&gdsc_venus>; + qcom,node-qos-clks { + clock-names = + "clk-noc-cfg-ahb-no-rate", + "clk-mnoc-ahb-no-rate", + "clk-camss-ahb-no-rate", + "clk-video-ahb-no-rate", + "clk-video-axi-no-rate"; + clocks = + <&clock_gcc clk_mmssnoc_axi_clk>, + <&clock_gcc clk_gcc_mmss_noc_cfg_ahb_clk>, + <&clock_mmss clk_mmss_mnoc_ahb_clk>, + <&clock_mmss clk_mmss_camss_ahb_clk>, + <&clock_mmss clk_mmss_video_ahb_clk>, + <&clock_mmss clk_mmss_video_axi_clk>; + }; + + }; + + fab_snoc: fab-snoc { + cell-id = ; + label = "fab-snoc"; + qcom,fab-dev; + qcom,base-name = "snoc-base"; + qcom,bus-type = <1>; + qcom,qos-off = <4096>; + qcom,base-offset = <20480>; + clock-names = "bus_clk", "bus_a_clk"; + clocks = <&clock_gcc clk_snoc_clk>, + <&clock_gcc clk_snoc_a_clk>; + }; + + fab_mnoc_ahb: fab-mnoc-ahb { + cell-id = ; + label = "fab-mnoc-ahb"; + qcom,fab-dev; + qcom,base-name = "mmnoc-ahb-base"; + qcom,bypass-qos-prg; + qcom,setrate-only-clk; + qcom,bus-type = <1>; + clock-names = "bus_clk", "bus_a_clk"; + clocks = <&clock_mmss clk_ahb_clk_src>, + <&clock_mmss clk_ahb_clk_src>; + }; + + + /*Masters*/ + + mas_pcie_0: mas-pcie-0 { + cell-id = ; + label = "mas-pcie-0"; + qcom,buswidth = <16>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,qport = <1>; + qcom,qos-mode = "fixed"; + qcom,connections = <&slv_a1noc_snoc>; + qcom,prio1 = <1>; + qcom,prio0 = <1>; + qcom,bus-dev = <&fab_a1noc>; + qcom,mas-rpm-id = ; + }; + + mas_usb3: mas-usb3 { + cell-id = ; + label = "mas-usb3"; + qcom,buswidth = <16>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,qport = <2>; + qcom,qos-mode = "fixed"; + qcom,connections = <&slv_a1noc_snoc>; + qcom,prio1 = <1>; + qcom,prio0 = <1>; + qcom,bus-dev = <&fab_a1noc>; + qcom,mas-rpm-id = ; + }; + + mas_ufs: mas-ufs { + cell-id = ; + label = "mas-ufs"; + qcom,buswidth = <16>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,qport = <0>; + qcom,qos-mode = "fixed"; + qcom,connections = <&slv_a1noc_snoc>; + qcom,prio1 = <1>; + qcom,prio0 = <1>; + qcom,bus-dev = <&fab_a1noc>; + qcom,mas-rpm-id = ; + }; + + mas_blsp_2: mas-blsp-2 { + cell-id = ; + label = "mas-blsp-2"; + qcom,buswidth = <16>; + qcom,agg-ports = <1>; + qcom,qport = <4>; + qcom,qos-mode = "fixed"; + qcom,connections = <&slv_a1noc_snoc>; + qcom,bus-dev = <&fab_a1noc>; + qcom,mas-rpm-id = ; + }; + + mas_cnoc_a2noc: mas-cnoc-a2noc { + cell-id = <0>; + label = "mas-cnoc-a2noc"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,connections = <&slv_a2noc_snoc>; + qcom,bus-dev = <&fab_a2noc>; + qcom,mas-rpm-id = ; + }; + + mas_ipa: mas-ipa { + cell-id = ; + label = "mas-ipa"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,qport = <1>; + qcom,qos-mode = "fixed"; + qcom,connections = <&slv_a2noc_snoc>; + qcom,prio1 = <1>; + qcom,prio0 = <1>; + qcom,bus-dev = <&fab_a2noc>; + qcom,mas-rpm-id = ; + }; + + mas_sdcc_2: mas-sdcc-2 { + cell-id = ; + label = "mas-sdcc-2"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,qport = <6>; + qcom,qos-mode = "fixed"; + qcom,connections = <&slv_a2noc_snoc>; + qcom,bus-dev = <&fab_a2noc>; + qcom,mas-rpm-id = ; + }; + + mas_sdcc_4: mas-sdcc-4 { + cell-id = ; + label = "mas-sdcc-4"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,qport = <7>; + qcom,qos-mode = "fixed"; + qcom,connections = <&slv_a2noc_snoc>; + qcom,bus-dev = <&fab_a2noc>; + qcom,mas-rpm-id = ; + }; + + mas_tsif: mas-tsif { + cell-id = ; + label = "mas-tsif"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,connections = <&slv_a2noc_snoc>; + qcom,bus-dev = <&fab_a2noc>; + qcom,mas-rpm-id = ; + }; + + mas_blsp_1: mas-blsp-1 { + cell-id = ; + label = "mas-blsp-1"; + qcom,buswidth = <16>; + qcom,agg-ports = <1>; + qcom,qport = <8>; + qcom,qos-mode = "fixed"; + qcom,connections = <&slv_a2noc_snoc>; + qcom,bus-dev = <&fab_a2noc>; + qcom,mas-rpm-id = ; + }; + + mas_cr_virt_a2noc: mas-cr-virt-a2noc { + cell-id = ; + label = "mas-cr-virt-a2noc"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,qport = <9>; + qcom,qos-mode = "fixed"; + qcom,connections = <&slv_a2noc_snoc>; + qcom,bus-dev = <&fab_a2noc>; + qcom,mas-rpm-id = ; + }; + + mas_gnoc_bimc: mas-gnoc-bimc { + cell-id = ; + label = "mas-gnoc-bimc"; + qcom,buswidth = <8>; + qcom,agg-ports = <2>; + qcom,ap-owned; + qcom,qport = <0>; + qcom,qos-mode = "fixed"; + qcom,connections = <&slv_ebi &slv_bimc_snoc_0>; + qcom,prio-lvl = <0>; + qcom,prio-rd = <0>; + qcom,prio-wr = <0>; + qcom,bus-dev = <&fab_bimc>; + qcom,mas-rpm-id = ; + }; + + mas_oxili: mas-oxili { + cell-id = ; + label = "mas-oxili"; + qcom,buswidth = <8>; + qcom,agg-ports = <2>; + qcom,ap-owned; + qcom,qport = <1>; + qcom,qos-mode = "bypass"; + qcom,connections = < &slv_bimc_snoc_1 + &slv_hmss_l3&slv_ebi &slv_bimc_snoc_0>; + qcom,bus-dev = <&fab_bimc>; + qcom,mas-rpm-id = ; + }; + + mas_mnoc_bimc: mas-mnoc-bimc { + cell-id = ; + label = "mas-mnoc-bimc"; + qcom,buswidth = <8>; + qcom,agg-ports = <2>; + qcom,ap-owned; + qcom,qport = <2>; + qcom,qos-mode = "bypass"; + qcom,connections = < &slv_bimc_snoc_1 + &slv_hmss_l3&slv_ebi &slv_bimc_snoc_0>; + qcom,bus-dev = <&fab_bimc>; + qcom,mas-rpm-id = ; + }; + + mas_snoc_bimc: mas-snoc-bimc { + cell-id = ; + label = "mas-snoc-bimc"; + qcom,buswidth = <8>; + qcom,agg-ports = <2>; + qcom,qport = <3>; + qcom,qos-mode = "bypass"; + qcom,connections = < &slv_hmss_l3&slv_ebi>; + qcom,bus-dev = <&fab_bimc>; + qcom,mas-rpm-id = ; + }; + + mas_snoc_cnoc: mas-snoc-cnoc { + cell-id = ; + label = "mas-snoc-cnoc"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,connections = < &slv_skl &slv_blsp_2 + &slv_message_ram + &slv_tlmm_west &slv_tsif + &slv_mpm &slv_bimc_cfg + &slv_tlmm_east &slv_spdm + &slv_pimem_cfg &slv_a1noc_smmu_cfg + &slv_blsp_1 &slv_clk_ctl + &slv_prng &slv_usb3_0 + &slv_qdss_cfg &slv_qm_cfg + &slv_a2noc_cfg &slv_pmic_arb + &slv_ufs_cfg &slv_srvc_cnoc + &slv_ahb2phy &slv_ipa + &slv_glm &slv_snoc_cfg + &slv_ssc_cfg &slv_sdcc_2 + &slv_sdcc_4 &slv_pdm + &slv_cnoc_mnoc_mmss_cfg &slv_cnoc_mnoc_cfg + &slv_mss_cfg &slv_imem_cfg + &slv_a1noc_cfg &slv_gpuss_cfg + &slv_tcsr &slv_tlmm_north>; + qcom,bus-dev = <&fab_cnoc>; + qcom,mas-rpm-id = ; + }; + + mas_qdss_dap: mas-qdss-dap { + cell-id = ; + label = "mas-qdss-dap"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,connections = < &slv_skl &slv_blsp_2 + &slv_message_ram + &slv_tlmm_west &slv_tsif + &slv_mpm &slv_bimc_cfg + &slv_tlmm_east &slv_spdm + &slv_pimem_cfg &slv_a1noc_smmu_cfg + &slv_blsp_1 &slv_clk_ctl + &slv_prng &slv_usb3_0 + &slv_qdss_cfg &slv_qm_cfg + &slv_a2noc_cfg &slv_pmic_arb + &slv_ufs_cfg &slv_srvc_cnoc + &slv_ahb2phy &slv_ipa + &slv_glm &slv_snoc_cfg + &slv_sdcc_2 &slv_sdcc_4 + &slv_pdm &slv_cnoc_mnoc_mmss_cfg + &slv_cnoc_mnoc_cfg &slv_mss_cfg + &slv_imem_cfg &slv_a1noc_cfg + &slv_gpuss_cfg &slv_ssc_cfg + &slv_tcsr &slv_tlmm_north + &slv_cnoc_a2noc>; + qcom,bus-dev = <&fab_cnoc>; + qcom,mas-rpm-id = ; + }; + + mas_crypto_c0: mas-crypto-c0 { + cell-id = ; + label = "mas-crypto-c0"; + qcom,buswidth = <650>; + qcom,agg-ports = <1>; + qcom,connections = <&slv_cr_virt_a2noc>; + qcom,bus-dev = <&fab_a2noc>; + qcom,mas-rpm-id = ; + }; + + mas_apps_proc: mas-apps-proc { + cell-id = ; + label = "mas-apps-proc"; + qcom,buswidth = <32>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,connections = <&slv_gnoc_bimc>; + qcom,bus-dev = <&fab_gnoc>; + qcom,mas-rpm-id = ; + }; + + mas_cnoc_mnoc_mmss_cfg: mas-cnoc-mnoc-mmss-cfg { + cell-id = ; + label = "mas-cnoc-mnoc-mmss-cfg"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,connections = < &slv_camera_throttle_cfg + &slv_venus_cfg &slv_misc_cfg + &slv_camera_cfg &slv_display_throttle_cfg + &slv_venus_throttle_cfg &slv_display_cfg + &slv_mmss_clk_cfg &slv_vmem_cfg + &slv_mmss_clk_xpu_cfg &slv_smmu_cfg>; + qcom,bus-dev = <&fab_mnoc_ahb>; + qcom,mas-rpm-id = ; + }; + + mas_cnoc_mnoc_cfg: mas-cnoc-mnoc-cfg { + cell-id = ; + label = "mas-cnoc-mnoc-cfg"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,connections = <&slv_srvc_mnoc>; + qcom,bus-dev = <&fab_mnoc>; + qcom,mas-rpm-id = ; + }; + + mas_cpp: mas-cpp { + cell-id = ; + label = "mas-cpp"; + qcom,buswidth = <32>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,qport = <5>; + qcom,qos-mode = "bypass"; + qcom,connections = <&slv_mnoc_bimc>; + qcom,bus-dev = <&fab_mnoc>; + qcom,mas-rpm-id = ; + }; + + mas_jpeg: mas-jpeg { + cell-id = ; + label = "mas-jpeg"; + qcom,buswidth = <32>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,qport = <7>; + qcom,qos-mode = "bypass"; + qcom,connections = <&slv_mnoc_bimc>; + qcom,bus-dev = <&fab_mnoc>; + qcom,mas-rpm-id = ; + }; + + mas_mdp_p0: mas-mdp-p0 { + cell-id = ; + label = "mas-mdp-p0"; + qcom,buswidth = <32>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,qport = <1>; + qcom,qos-mode = "bypass"; + qcom,connections = <&slv_mnoc_bimc>; + qcom,bus-dev = <&fab_mnoc>; + qcom,vrail-comp = <25>; + qcom,mas-rpm-id = ; + clk-mdss-axi-no-rate-supply = + <&gdsc_mdss>; + clk-mdss-ahb-no-rate-supply = + <&gdsc_mdss>; + qcom,node-qos-clks { + clock-names = + "clk-mdss-ahb-no-rate", + "clk-mdss-axi-no-rate"; + clocks = + <&clock_mmss clk_mmss_mdss_ahb_clk>, + <&clock_mmss clk_mmss_mdss_axi_clk>; + }; + + }; + + mas_mdp_p1: mas-mdp-p1 { + cell-id = ; + label = "mas-mdp-p1"; + qcom,buswidth = <32>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,qport = <2>; + qcom,qos-mode = "bypass"; + qcom,connections = <&slv_mnoc_bimc>; + qcom,bus-dev = <&fab_mnoc>; + qcom,vrail-comp = <25>; + qcom,mas-rpm-id = ; + }; + + mas_rotator: mas-rotator { + cell-id = ; + label = "mas-rotator"; + qcom,buswidth = <32>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,qport = <0>; + qcom,qos-mode = "bypass"; + qcom,connections = <&slv_mnoc_bimc>; + qcom,bus-dev = <&fab_mnoc>; + qcom,mas-rpm-id = ; + }; + + mas_venus: mas-venus { + cell-id = ; + label = "mas-venus"; + qcom,buswidth = <32>; + qcom,agg-ports = <2>; + qcom,ap-owned; + qcom,qport = <3 4>; + qcom,qos-mode = "bypass"; + qcom,connections = <&slv_mnoc_bimc>; + qcom,bus-dev = <&fab_mnoc>; + qcom,mas-rpm-id = ; + }; + + mas_vfe: mas-vfe { + cell-id = ; + label = "mas-vfe"; + qcom,buswidth = <32>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,qport = <6>; + qcom,qos-mode = "bypass"; + qcom,connections = <&slv_mnoc_bimc>; + qcom,bus-dev = <&fab_mnoc>; + qcom,mas-rpm-id = ; + }; + + mas_venus_vmem: mas-venus-vmem { + cell-id = ; + label = "mas-venus-vmem"; + qcom,buswidth = <32>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,connections = <&slv_vmem>; + qcom,bus-dev = <&fab_mnoc>; + qcom,mas-rpm-id = ; + }; + + mas_hmss: mas-hmss { + cell-id = ; + label = "mas-hmss"; + qcom,buswidth = <16>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,qport = <3>; + qcom,qos-mode = "fixed"; + qcom,connections = < &slv_pimem &slv_imem + &slv_snoc_bimc>; + qcom,prio1 = <1>; + qcom,prio0 = <1>; + qcom,bus-dev = <&fab_snoc>; + qcom,mas-rpm-id = ; + }; + + mas_qdss_bam: mas-qdss-bam { + cell-id = ; + label = "mas-qdss-bam"; + qcom,buswidth = <16>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,qport = <1>; + qcom,qos-mode = "fixed"; + qcom,connections = < &slv_imem &slv_pimem &slv_snoc_cnoc + &slv_snoc_bimc>; + qcom,prio1 = <1>; + qcom,prio0 = <1>; + qcom,bus-dev = <&fab_snoc>; + qcom,mas-rpm-id = ; + }; + + mas_snoc_cfg: mas-snoc-cfg { + cell-id = ; + label = "mas-snoc-cfg"; + qcom,buswidth = <16>; + qcom,agg-ports = <1>; + qcom,connections = <&slv_srvc_snoc>; + qcom,bus-dev = <&fab_snoc>; + qcom,mas-rpm-id = ; + }; + + mas_bimc_snoc_0: mas-bimc-snoc-0 { + cell-id = ; + label = "mas-bimc-snoc-0"; + qcom,buswidth = <16>; + qcom,agg-ports = <1>; + qcom,connections = < &slv_pimem &slv_lpass&slv_hmss + &slv_wlan &slv_snoc_cnoc + &slv_imem &slv_qdss_stm>; + qcom,bus-dev = <&fab_snoc>; + qcom,mas-rpm-id = ; + }; + + mas_bimc_snoc_1: mas-bimc-snoc-1 { + cell-id = ; + label = "mas-bimc-snoc-1"; + qcom,buswidth = <16>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,connections = <&slv_pcie_0>; + qcom,bus-dev = <&fab_snoc>; + qcom,mas-rpm-id = ; + }; + + mas_a1noc_snoc: mas-a1noc-snoc { + cell-id = ; + label = "mas-a1noc-snoc"; + qcom,buswidth = <16>; + qcom,agg-ports = <1>; + qcom,connections = < &slv_pimem &slv_pcie_0 &slv_lpass + &slv_hmss &slv_snoc_bimc + &slv_snoc_cnoc &slv_imem + &slv_qdss_stm>; + qcom,bus-dev = <&fab_snoc>; + qcom,mas-rpm-id = ; + }; + + mas_a2noc_snoc: mas-a2noc-snoc { + cell-id = ; + label = "mas-a2noc-snoc"; + qcom,buswidth = <16>; + qcom,agg-ports = <1>; + qcom,connections = < &slv_pimem &slv_pcie_0 &slv_lpass + &slv_hmss &slv_snoc_bimc + &slv_wlan &slv_snoc_cnoc + &slv_imem &slv_qdss_stm>; + qcom,bus-dev = <&fab_snoc>; + qcom,mas-rpm-id = ; + }; + + mas_qdss_etr: mas-qdss-etr { + cell-id = ; + label = "mas-qdss-etr"; + qcom,buswidth = <16>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,qport = <2>; + qcom,qos-mode = "fixed"; + qcom,connections = < &slv_imem &slv_pimem &slv_snoc_cnoc + &slv_snoc_bimc>; + qcom,prio1 = <1>; + qcom,prio0 = <1>; + qcom,bus-dev = <&fab_snoc>; + qcom,mas-rpm-id = ; + }; + + /*Internal nodes*/ + + /*Slaves*/ + + slv_a1noc_snoc:slv-a1noc-snoc { + cell-id = ; + label = "slv-a1noc-snoc"; + qcom,buswidth = <16>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_a1noc>; + qcom,connections = <&mas_a1noc_snoc>; + qcom,slv-rpm-id = ; + }; + + slv_a2noc_snoc:slv-a2noc-snoc { + cell-id = ; + label = "slv-a2noc-snoc"; + qcom,buswidth = <16>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_a2noc>; + qcom,connections = <&mas_a2noc_snoc>; + qcom,slv-rpm-id = ; + }; + + slv_ebi:slv-ebi { + cell-id = ; + label = "slv-ebi"; + qcom,buswidth = <8>; + qcom,agg-ports = <2>; + qcom,bus-dev = <&fab_bimc>; + qcom,slv-rpm-id = ; + }; + + slv_hmss_l3:slv-hmss-l3 { + cell-id = ; + label = "slv-hmss-l3"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_bimc>; + qcom,slv-rpm-id = ; + }; + + slv_bimc_snoc_0:slv-bimc-snoc-0 { + cell-id = ; + label = "slv-bimc-snoc-0"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_bimc>; + qcom,connections = <&mas_bimc_snoc_0>; + qcom,slv-rpm-id = ; + }; + + slv_bimc_snoc_1:slv-bimc-snoc-1 { + cell-id = ; + label = "slv-bimc-snoc-1"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_bimc>; + qcom,connections = <&mas_bimc_snoc_1>; + qcom,slv-rpm-id = ; + }; + + slv_cnoc_a2noc:slv-cnoc-a2noc { + cell-id = ; + label = "slv-cnoc-a2noc"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_cnoc>; + qcom,connections = <&mas_cnoc_a2noc>; + qcom,slv-rpm-id = ; + }; + + slv_ssc_cfg:slv-ssc-cfg { + cell-id = ; + label = "slv-ssc-cfg"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_cnoc>; + qcom,slv-rpm-id = ; + }; + + slv_mpm:slv-mpm { + cell-id = ; + label = "slv-mpm"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_cnoc>; + qcom,slv-rpm-id = ; + }; + + slv_pmic_arb:slv-pmic-arb { + cell-id = ; + label = "slv-pmic-arb"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_cnoc>; + qcom,slv-rpm-id = ; + }; + slv_tlmm_north:slv-tlmm-north { + cell-id = ; + label = "slv-tlmm-north"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_cnoc>; + qcom,slv-rpm-id = ; + }; + slv_pimem_cfg:slv-pimem-cfg { + cell-id = ; + label = "slv-pimem-cfg"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_cnoc>; + qcom,slv-rpm-id = ; + }; + + slv_imem_cfg:slv-imem-cfg { + cell-id = ; + label = "slv-imem-cfg"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_cnoc>; + qcom,slv-rpm-id = ; + }; + + slv_message_ram:slv-message-ram { + cell-id = ; + label = "slv-message-ram"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_cnoc>; + qcom,slv-rpm-id = ; + }; + + slv_skl:slv-skl { + cell-id = ; + label = "slv-skl"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_cnoc>; + qcom,slv-rpm-id = ; + }; + + slv_bimc_cfg:slv-bimc-cfg { + cell-id = ; + label = "slv-bimc-cfg"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_cnoc>; + qcom,slv-rpm-id = ; + }; + + slv_prng:slv-prng { + cell-id = ; + label = "slv-prng"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_cnoc>; + qcom,slv-rpm-id = ; + }; + + slv_a2noc_cfg:slv-a2noc-cfg { + cell-id = ; + label = "slv-a2noc-cfg"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_cnoc>; + qcom,slv-rpm-id = ; + }; + + slv_ipa:slv-ipa { + cell-id = ; + label = "slv-ipa"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_cnoc>; + qcom,slv-rpm-id = ; + }; + + slv_tcsr:slv-tcsr { + cell-id = ; + label = "slv-tcsr"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_cnoc>; + qcom,slv-rpm-id = ; + }; + + slv_snoc_cfg:slv-snoc-cfg { + cell-id = ; + label = "slv-snoc-cfg"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_cnoc>; + qcom,slv-rpm-id = ; + }; + + slv_clk_ctl:slv-clk-ctl { + cell-id = ; + label = "slv-clk-ctl"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_cnoc>; + qcom,slv-rpm-id = ; + }; + + slv_glm:slv-glm { + cell-id = ; + label = "slv-glm"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_cnoc>; + qcom,slv-rpm-id = ; + }; + + slv_spdm:slv-spdm { + cell-id = ; + label = "slv-spdm"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_cnoc>; + qcom,slv-rpm-id = ; + }; + + slv_gpuss_cfg:slv-gpuss-cfg { + cell-id = ; + label = "slv-gpuss-cfg"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_cnoc>; + qcom,slv-rpm-id = ; + }; + + slv_cnoc_mnoc_cfg:slv-cnoc-mnoc-cfg { + cell-id = ; + label = "slv-cnoc-mnoc-cfg"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_cnoc>; + qcom,connections = <&mas_cnoc_mnoc_cfg>; + qcom,slv-rpm-id = ; + }; + + slv_qm_cfg:slv-qm-cfg { + cell-id = ; + label = "slv-qm-cfg"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_cnoc>; + qcom,slv-rpm-id = ; + }; + + slv_mss_cfg:slv-mss-cfg { + cell-id = ; + label = "slv-mss-cfg"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_cnoc>; + qcom,slv-rpm-id = ; + }; + + slv_ufs_cfg:slv-ufs-cfg { + cell-id = ; + label = "slv-ufs-cfg"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_cnoc>; + qcom,slv-rpm-id = ; + }; + + slv_tlmm_west:slv-tlmm-west { + cell-id = ; + label = "slv-tlmm-west"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_cnoc>; + qcom,slv-rpm-id = ; + }; + + slv_a1noc_cfg:slv-a1noc-cfg { + cell-id = ; + label = "slv-a1noc-cfg"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_cnoc>; + qcom,slv-rpm-id = ; + }; + + slv_ahb2phy:slv-ahb2phy { + cell-id = ; + label = "slv-ahb2phy"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_cnoc>; + qcom,slv-rpm-id = ; + }; + + slv_blsp_2:slv-blsp-2 { + cell-id = ; + label = "slv-blsp-2"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_cnoc>; + qcom,slv-rpm-id = ; + }; + + slv_pdm:slv-pdm { + cell-id = ; + label = "slv-pdm"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_cnoc>; + qcom,slv-rpm-id = ; + }; + + slv_usb3_0:slv-usb3-0 { + cell-id = ; + label = "slv-usb3-0"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_cnoc>; + qcom,slv-rpm-id = ; + }; + + slv_a1noc_smmu_cfg:slv-a1noc-smmu-cfg { + cell-id = ; + label = "slv-a1noc-smmu-cfg"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_cnoc>; + qcom,slv-rpm-id = ; + }; + + slv_blsp_1:slv-blsp-1 { + cell-id = ; + label = "slv-blsp-1"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_cnoc>; + qcom,slv-rpm-id = ; + }; + + slv_sdcc_2:slv-sdcc-2 { + cell-id = ; + label = "slv-sdcc-2"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_cnoc>; + qcom,slv-rpm-id = ; + }; + + slv_sdcc_4:slv-sdcc-4 { + cell-id = ; + label = "slv-sdcc-4"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_cnoc>; + qcom,slv-rpm-id = ; + }; + + slv_tsif:slv-tsif { + cell-id = ; + label = "slv-tsif"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_cnoc>; + qcom,slv-rpm-id = ; + }; + + slv_qdss_cfg:slv-qdss-cfg { + cell-id = ; + label = "slv-qdss-cfg"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_cnoc>; + qcom,slv-rpm-id = ; + }; + + slv_tlmm_east:slv-tlmm-east { + cell-id = ; + label = "slv-tlmm-east"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_cnoc>; + qcom,slv-rpm-id = ; + }; + + slv_cnoc_mnoc_mmss_cfg:slv-cnoc-mnoc-mmss-cfg { + cell-id = ; + label = "slv-cnoc-mnoc-mmss-cfg"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_cnoc>; + qcom,connections = <&mas_cnoc_mnoc_mmss_cfg>; + qcom,slv-rpm-id = ; + }; + + slv_srvc_cnoc:slv-srvc-cnoc { + cell-id = ; + label = "slv-srvc-cnoc"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_cnoc>; + qcom,slv-rpm-id = ; + }; + + slv_cr_virt_a2noc:slv-cr-virt-a2noc { + cell-id = ; + label = "slv-cr-virt-a2noc"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_a2noc>; + qcom,connections = <&mas_cr_virt_a2noc>; + qcom,slv-rpm-id = ; + }; + + slv_gnoc_bimc:slv-gnoc-bimc { + cell-id = ; + label = "slv-gnoc-bimc"; + qcom,buswidth = <32>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_gnoc>; + qcom,connections = <&mas_gnoc_bimc>; + qcom,slv-rpm-id = ; + }; + + slv_camera_cfg:slv-camera-cfg { + cell-id = ; + label = "slv-camera-cfg"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_mnoc_ahb>; + qcom,slv-rpm-id = ; + }; + + slv_camera_throttle_cfg:slv-camera-throttle-cfg { + cell-id = ; + label = "slv-camera-throttle-cfg"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_mnoc_ahb>; + qcom,slv-rpm-id = ; + }; + + slv_misc_cfg:slv-misc-cfg { + cell-id = ; + label = "slv-misc-cfg"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_mnoc_ahb>; + qcom,slv-rpm-id = ; + }; + + slv_venus_throttle_cfg:slv-venus-throttle-cfg { + cell-id = ; + label = "slv-venus-throttle-cfg"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_mnoc_ahb>; + qcom,slv-rpm-id = ; + }; + + slv_venus_cfg:slv-venus-cfg { + cell-id = ; + label = "slv-venus-cfg"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_mnoc_ahb>; + qcom,slv-rpm-id = ; + }; + + slv_vmem_cfg:slv-vmem-cfg { + cell-id = ; + label = "slv-vmem-cfg"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_mnoc_ahb>; + qcom,slv-rpm-id = ; + qcom,enable-only-clk; + clock-names = "node_clk"; + clocks = <&clock_mmss clk_mmss_mnoc_maxi_clk>; + }; + + slv_mmss_clk_xpu_cfg:slv-mmss-clk-xpu-cfg { + cell-id = ; + label = "slv-mmss-clk-xpu-cfg"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_mnoc_ahb>; + qcom,slv-rpm-id = ; + }; + + slv_mmss_clk_cfg:slv-mmss-clk-cfg { + cell-id = ; + label = "slv-mmss-clk-cfg"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_mnoc_ahb>; + qcom,slv-rpm-id = ; + }; + + slv_display_cfg:slv-display-cfg { + cell-id = ; + label = "slv-display-cfg"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_mnoc_ahb>; + qcom,slv-rpm-id = ; + }; + + slv_display_throttle_cfg:slv-display-throttle-cfg { + cell-id = ; + label = "slv-display-throttle-cfg"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_mnoc_ahb>; + qcom,slv-rpm-id = ; + }; + + slv_smmu_cfg:slv-smmu-cfg { + cell-id = ; + label = "slv-smmu-cfg"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_mnoc_ahb>; + qcom,slv-rpm-id = ; + }; + + slv_mnoc_bimc:slv-mnoc-bimc { + cell-id = ; + label = "slv-mnoc-bimc"; + qcom,buswidth = <32>; + qcom,agg-ports = <2>; + qcom,ap-owned; + qcom,bus-dev = <&fab_mnoc>; + qcom,connections = <&mas_mnoc_bimc>; + qcom,slv-rpm-id = ; + qcom,enable-only-clk; + clock-names = "node_clk"; + clocks = <&clock_gcc clk_mmssnoc_axi_clk>; + }; + + slv_vmem: slv-vmem { + cell-id = ; + label = "slv-vmem"; + qcom,buswidth = <32>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_mnoc>; + qcom,slv-rpm-id = ; + clock-names = "node_clk"; + clocks = <&clock_mmss clk_mmss_mnoc_maxi_clk>; + }; + + slv_srvc_mnoc:slv-srvc-mnoc { + cell-id = ; + label = "slv-srvc-mnoc"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_mnoc>; + qcom,slv-rpm-id = ; + }; + + slv_hmss:slv-hmss { + cell-id = ; + label = "slv-hmss"; + qcom,buswidth = <16>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_snoc>; + qcom,slv-rpm-id = ; + }; + + slv_lpass:slv-lpass { + cell-id = ; + label = "slv-lpass"; + qcom,buswidth = <16>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_snoc>; + qcom,slv-rpm-id = ; + }; + + slv_wlan:slv-wlan { + cell-id = ; + label = "slv-wlan"; + qcom,buswidth = <16>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_snoc>; + qcom,slv-rpm-id = ; + }; + + slv_snoc_bimc:slv-snoc-bimc { + cell-id = ; + label = "slv-snoc-bimc"; + qcom,buswidth = <32>; + qcom,agg-ports = <2>; + qcom,bus-dev = <&fab_snoc>; + qcom,connections = <&mas_snoc_bimc>; + qcom,slv-rpm-id = ; + }; + + slv_snoc_cnoc:slv-snoc-cnoc { + cell-id = ; + label = "slv-snoc-cnoc"; + qcom,buswidth = <16>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_snoc>; + qcom,connections = <&mas_snoc_cnoc>; + qcom,slv-rpm-id = ; + }; + + slv_imem:slv-imem { + cell-id = ; + label = "slv-imem"; + qcom,buswidth = <16>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_snoc>; + qcom,slv-rpm-id = ; + }; + + slv_pimem:slv-pimem { + cell-id = ; + label = "slv-pimem"; + qcom,buswidth = <16>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_snoc>; + qcom,slv-rpm-id = ; + }; + + slv_qdss_stm:slv-qdss-stm { + cell-id = ; + label = "slv-qdss-stm"; + qcom,buswidth = <16>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_snoc>; + qcom,slv-rpm-id = ; + }; + + slv_pcie_0:slv-pcie-0 { + cell-id = ; + label = "slv-pcie-0"; + qcom,buswidth = <16>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_snoc>; + qcom,slv-rpm-id = ; + }; + + slv_srvc_snoc:slv-srvc-snoc { + cell-id = ; + label = "slv-srvc-snoc"; + qcom,buswidth = <16>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_snoc>; + qcom,slv-rpm-id = ; + }; + }; + + devfreq_spdm_cpu { + compatible = "qcom,devfreq_spdm"; + qcom,msm-bus,name = "devfreq_spdm"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <1 512 0 0>, + <1 512 0 0>; + qcom,msm-bus,active-only; + qcom,spdm-client = <0>; + + qcom,bw-upstep = <1000>; + qcom,bw-dwnstep = <1000>; + qcom,max-vote = <10000>; + qcom,up-step-multp = <2>; + qcom,spdm-interval = <100>; + + qcom,ports = <24>; + qcom,alpha-up = <12>; + qcom,alpha-down = <15>; + qcom,bucket-size = <8>; + + /*max pl1 freq, max pl2 freq*/ + qcom,pl-freqs = <260000 770000>; + + /* pl1 low, pl1 high, pl2 low, pl2 high, pl3 low, pl3 high */ + qcom,reject-rate = <5000 5000 5000 5000 5000 5000>; + /* pl1 low, pl1 high, pl2 low, pl2 high, pl3 low, pl3 high */ + qcom,response-time-us = <10000 10000 10000 10000 10000 10000>; + /* pl1 low, pl1 high, pl2 low, pl2 high, pl3 low, pl3 high */ + qcom,cci-response-time-us = <10000 10000 10000 + 10000 10000 10000>; + qcom,max-cci-freq = <1036800>; + }; + + devfreq_spdm_gov { + compatible = "qcom,gov_spdm_hyp"; + interrupt-names = "spdm-irq"; + interrupts = <0 192 IRQ_TYPE_EDGE_RISING>; + }; +}; --- /dev/null 2019-10-24 16:47:25.704025805 +0200 +++ linux-4.4.115-fbx/arch/arm64/boot/dts/qcom/msm8998-camera.dtsi 2019-01-22 16:16:21.195225506 +0100 @@ -0,0 +1,909 @@ +/* + * Copyright (c) 2015-2017, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&soc { + qcom,msm-cam@8c0000 { + compatible = "qcom,msm-cam"; + reg = <0x8c0000 0x40000>; + reg-names = "msm-cam"; + status = "ok"; + bus-vectors = "suspend", "svs", "nominal", "turbo"; + qcom,bus-votes = <0 300000000 640000000 640000000>; + }; + + qcom,csiphy@ca34000 { + cell-index = <0>; + compatible = "qcom,csiphy-v5.0", "qcom,csiphy"; + reg = <0xca34000 0x1000>; + reg-names = "csiphy"; + interrupts = <0 78 0>; + interrupt-names = "csiphy"; + gdscr-supply = <&gdsc_camss_top>; + bimc_smmu-supply = <&gdsc_bimc_smmu>; + qcom,cam-vreg-name = "gdscr", "bimc_smmu"; + clocks = <&clock_gcc clk_mmssnoc_axi_clk>, + <&clock_mmss clk_mmss_mnoc_ahb_clk>, + <&clock_mmss clk_mmss_bimc_smmu_ahb_clk>, + <&clock_mmss clk_mmss_bimc_smmu_axi_clk>, + <&clock_mmss clk_mmss_camss_ahb_clk>, + <&clock_mmss clk_mmss_camss_top_ahb_clk>, + <&clock_mmss clk_csi0_clk_src>, + <&clock_mmss clk_mmss_camss_csi0_clk>, + <&clock_mmss clk_mmss_camss_cphy_csid0_clk>, + <&clock_mmss clk_csi0phytimer_clk_src>, + <&clock_mmss clk_mmss_camss_csi0phytimer_clk>, + <&clock_mmss clk_mmss_camss_ispif_ahb_clk>, + <&clock_mmss clk_csiphy_clk_src>, + <&clock_mmss clk_mmss_camss_csiphy0_clk>; + clock-names = "mmssnoc_axi", "mnoc_ahb", + "bmic_smmu_ahb", "bmic_smmu_axi", + "camss_ahb_clk", "camss_top_ahb_clk", + "csi_src_clk", "csi_clk", "cphy_csid_clk", + "csiphy_timer_src_clk", "csiphy_timer_clk", + "camss_ispif_ahb_clk", "csiphy_clk_src", "csiphy_clk"; + qcom,clock-rates = <0 0 0 0 0 0 274290000 0 0 200000000 0 + 0 274290000 0>; + status = "ok"; + }; + + qcom,csiphy@ca35000 { + cell-index = <1>; + compatible = "qcom,csiphy-v5.0", "qcom,csiphy"; + reg = <0xca35000 0x1000>; + reg-names = "csiphy"; + interrupts = <0 79 0>; + interrupt-names = "csiphy"; + gdscr-supply = <&gdsc_camss_top>; + bimc_smmu-supply = <&gdsc_bimc_smmu>; + qcom,cam-vreg-name = "gdscr", "bimc_smmu"; + clocks = <&clock_gcc clk_mmssnoc_axi_clk>, + <&clock_mmss clk_mmss_mnoc_ahb_clk>, + <&clock_mmss clk_mmss_bimc_smmu_ahb_clk>, + <&clock_mmss clk_mmss_bimc_smmu_axi_clk>, + <&clock_mmss clk_mmss_camss_ahb_clk>, + <&clock_mmss clk_mmss_camss_top_ahb_clk>, + <&clock_mmss clk_csi1_clk_src>, + <&clock_mmss clk_mmss_camss_csi1_clk>, + <&clock_mmss clk_mmss_camss_cphy_csid1_clk>, + <&clock_mmss clk_csi1phytimer_clk_src>, + <&clock_mmss clk_mmss_camss_csi1phytimer_clk>, + <&clock_mmss clk_mmss_camss_ispif_ahb_clk>, + <&clock_mmss clk_csiphy_clk_src>, + <&clock_mmss clk_mmss_camss_csiphy1_clk>; + clock-names = "mmssnoc_axi", "mnoc_ahb", + "bmic_smmu_ahb", "bmic_smmu_axi", + "camss_ahb_clk", "camss_top_ahb_clk", + "csi_src_clk", "csi_clk", "cphy_csid_clk", + "csiphy_timer_src_clk", "csiphy_timer_clk", + "camss_ispif_ahb_clk", "csiphy_clk_src", "csiphy_clk"; + qcom,clock-rates = <0 0 0 0 0 0 274290000 0 0 200000000 0 + 0 274290000 0>; + status = "ok"; + }; + + qcom,csiphy@ca36000 { + cell-index = <2>; + compatible = "qcom,csiphy-v5.0", "qcom,csiphy"; + reg = <0xca36000 0x1000>; + reg-names = "csiphy"; + interrupts = <0 80 0>; + interrupt-names = "csiphy"; + gdscr-supply = <&gdsc_camss_top>; + bimc_smmu-supply = <&gdsc_bimc_smmu>; + qcom,cam-vreg-name = "gdscr", "bimc_smmu"; + clocks = <&clock_gcc clk_mmssnoc_axi_clk>, + <&clock_mmss clk_mmss_mnoc_ahb_clk>, + <&clock_mmss clk_mmss_bimc_smmu_ahb_clk>, + <&clock_mmss clk_mmss_bimc_smmu_axi_clk>, + <&clock_mmss clk_mmss_camss_ahb_clk>, + <&clock_mmss clk_mmss_camss_top_ahb_clk>, + <&clock_mmss clk_csi2_clk_src>, + <&clock_mmss clk_mmss_camss_csi2_clk>, + <&clock_mmss clk_mmss_camss_cphy_csid2_clk>, + <&clock_mmss clk_csi2phytimer_clk_src>, + <&clock_mmss clk_mmss_camss_csi2phytimer_clk>, + <&clock_mmss clk_mmss_camss_ispif_ahb_clk>, + <&clock_mmss clk_csiphy_clk_src>, + <&clock_mmss clk_mmss_camss_csiphy2_clk>; + clock-names = "mmssnoc_axi", "mnoc_ahb", + "bmic_smmu_ahb", "bmic_smmu_axi", + "camss_ahb_clk", "camss_top_ahb_clk", + "csi_src_clk", "csi_clk", "cphy_csid_clk", + "csiphy_timer_src_clk", "csiphy_timer_clk", + "camss_ispif_ahb_clk", "csiphy_clk_src", "csiphy_clk"; + qcom,clock-rates = <0 0 0 0 0 0 274290000 0 0 200000000 0 + 0 274290000 0>; + status = "ok"; + }; + + qcom,csid@ca30000 { + cell-index = <0>; + compatible = "qcom,csid-v5.0", "qcom,csid"; + reg = <0xca30000 0x400>; + reg-names = "csid"; + interrupts = <0 296 0>; + interrupt-names = "csid"; + qcom,csi-vdd-voltage = <1200000>; + qcom,mipi-csi-vdd-supply = <&pm8998_l2>; + gdscr-supply = <&gdsc_camss_top>; + vdd_sec-supply = <&pm8998_l1>; + bimc_smmu-supply = <&gdsc_bimc_smmu>; + qcom,cam-vreg-name = "vdd_sec", "gdscr", "bimc_smmu"; + clocks = <&clock_gcc clk_mmssnoc_axi_clk>, + <&clock_mmss clk_mmss_mnoc_ahb_clk>, + <&clock_mmss clk_mmss_bimc_smmu_ahb_clk>, + <&clock_mmss clk_mmss_bimc_smmu_axi_clk>, + <&clock_mmss clk_mmss_camss_ahb_clk>, + <&clock_mmss clk_mmss_camss_top_ahb_clk>, + <&clock_mmss clk_mmss_camss_ispif_ahb_clk>, + <&clock_mmss clk_csi0_clk_src>, + <&clock_mmss clk_csiphy_clk_src>, + <&clock_mmss clk_mmss_camss_csi0_clk>, + <&clock_mmss clk_mmss_camss_csi0_ahb_clk>, + <&clock_mmss clk_mmss_camss_csi0rdi_clk>, + <&clock_mmss clk_mmss_camss_csi0pix_clk>, + <&clock_mmss clk_mmss_camss_cphy_csid0_clk>; + clock-names = "mmssnoc_axi", "mnoc_ahb", + "bmic_smmu_ahb", "bmic_smmu_axi", + "camss_ahb_clk", "camss_top_ahb_clk", + "ispif_ahb_clk", "csi_src_clk", "csiphy_clk_src", + "csi_clk", "csi_ahb_clk", "csi_rdi_clk", + "csi_pix_clk", "cphy_csid_clk"; + qcom,clock-rates = <0 0 0 0 0 0 0 274290000 274290000 + 0 0 0 0 0>; + status = "ok"; + }; + + qcom,csid@ca30400 { + cell-index = <1>; + compatible = "qcom,csid-v5.0", "qcom,csid"; + reg = <0xca30400 0x400>; + reg-names = "csid"; + interrupts = <0 297 0>; + interrupt-names = "csid"; + qcom,csi-vdd-voltage = <1200000>; + qcom,mipi-csi-vdd-supply = <&pm8998_l2>; + gdscr-supply = <&gdsc_camss_top>; + vdd_sec-supply = <&pm8998_l1>; + bimc_smmu-supply = <&gdsc_bimc_smmu>; + qcom,cam-vreg-name = "vdd_sec", "gdscr", "bimc_smmu"; + clocks = <&clock_gcc clk_mmssnoc_axi_clk>, + <&clock_mmss clk_mmss_mnoc_ahb_clk>, + <&clock_mmss clk_mmss_bimc_smmu_ahb_clk>, + <&clock_mmss clk_mmss_bimc_smmu_axi_clk>, + <&clock_mmss clk_mmss_camss_ahb_clk>, + <&clock_mmss clk_mmss_camss_top_ahb_clk>, + <&clock_mmss clk_mmss_camss_ispif_ahb_clk>, + <&clock_mmss clk_csi1_clk_src>, + <&clock_mmss clk_csiphy_clk_src>, + <&clock_mmss clk_mmss_camss_csi1_clk>, + <&clock_mmss clk_mmss_camss_csi1_ahb_clk>, + <&clock_mmss clk_mmss_camss_csi1rdi_clk>, + <&clock_mmss clk_mmss_camss_csi1pix_clk>, + <&clock_mmss clk_mmss_camss_cphy_csid1_clk>; + clock-names = "mmssnoc_axi", "mnoc_ahb", + "bmic_smmu_ahb", "bmic_smmu_axi", + "camss_ahb_clk", "camss_top_ahb_clk", + "ispif_ahb_clk", "csi_src_clk", "csiphy_clk_src", + "csi_clk", "csi_ahb_clk", "csi_rdi_clk", + "csi_pix_clk", "cphy_csid_clk"; + qcom,clock-rates = <0 0 0 0 0 0 0 274290000 274290000 + 0 0 0 0 0>; + status = "ok"; + }; + + qcom,csid@ca30800 { + cell-index = <2>; + compatible = "qcom,csid-v5.0", "qcom,csid"; + reg = <0xca30800 0x400>; + reg-names = "csid"; + interrupts = <0 298 0>; + interrupt-names = "csid"; + qcom,csi-vdd-voltage = <1200000>; + qcom,mipi-csi-vdd-supply = <&pm8998_l2>; + gdscr-supply = <&gdsc_camss_top>; + vdd_sec-supply = <&pm8998_l1>; + bimc_smmu-supply = <&gdsc_bimc_smmu>; + qcom,cam-vreg-name = "vdd_sec", "gdscr", "bimc_smmu"; + clocks = <&clock_gcc clk_mmssnoc_axi_clk>, + <&clock_mmss clk_mmss_mnoc_ahb_clk>, + <&clock_mmss clk_mmss_bimc_smmu_ahb_clk>, + <&clock_mmss clk_mmss_bimc_smmu_axi_clk>, + <&clock_mmss clk_mmss_camss_ahb_clk>, + <&clock_mmss clk_mmss_camss_top_ahb_clk>, + <&clock_mmss clk_mmss_camss_ispif_ahb_clk>, + <&clock_mmss clk_csi2_clk_src>, + <&clock_mmss clk_csiphy_clk_src>, + <&clock_mmss clk_mmss_camss_csi2_clk>, + <&clock_mmss clk_mmss_camss_csi2_ahb_clk>, + <&clock_mmss clk_mmss_camss_csi2rdi_clk>, + <&clock_mmss clk_mmss_camss_csi2pix_clk>, + <&clock_mmss clk_mmss_camss_cphy_csid2_clk>; + clock-names = "mmssnoc_axi", "mnoc_ahb", + "bmic_smmu_ahb", "bmic_smmu_axi", + "camss_ahb_clk", "camss_top_ahb_clk", + "ispif_ahb_clk", "csi_src_clk", "csiphy_clk_src", + "csi_clk", "csi_ahb_clk", "csi_rdi_clk", + "csi_pix_clk", "cphy_csid_clk"; + qcom,clock-rates = <0 0 0 0 0 0 0 274290000 274290000 + 0 0 0 0 0>; + status = "ok"; + }; + + qcom,csid@ca30c00 { + cell-index = <3>; + compatible = "qcom,csid-v5.0", "qcom,csid"; + reg = <0xca30c00 0x400>; + reg-names = "csid"; + interrupts = <0 299 0>; + interrupt-names = "csid"; + qcom,csi-vdd-voltage = <1200000>; + qcom,mipi-csi-vdd-supply = <&pm8998_l2>; + gdscr-supply = <&gdsc_camss_top>; + vdd_sec-supply = <&pm8998_l1>; + bimc_smmu-supply = <&gdsc_bimc_smmu>; + qcom,cam-vreg-name = "vdd_sec", "gdscr", "bimc_smmu"; + clocks = <&clock_gcc clk_mmssnoc_axi_clk>, + <&clock_mmss clk_mmss_mnoc_ahb_clk>, + <&clock_mmss clk_mmss_bimc_smmu_ahb_clk>, + <&clock_mmss clk_mmss_bimc_smmu_axi_clk>, + <&clock_mmss clk_mmss_camss_ahb_clk>, + <&clock_mmss clk_mmss_camss_top_ahb_clk>, + <&clock_mmss clk_mmss_camss_ispif_ahb_clk>, + <&clock_mmss clk_csi3_clk_src>, + <&clock_mmss clk_csiphy_clk_src>, + <&clock_mmss clk_mmss_camss_csi3_clk>, + <&clock_mmss clk_mmss_camss_csi3_ahb_clk>, + <&clock_mmss clk_mmss_camss_csi3rdi_clk>, + <&clock_mmss clk_mmss_camss_csi3pix_clk>, + <&clock_mmss clk_mmss_camss_cphy_csid3_clk>; + clock-names = "mmssnoc_axi", "mnoc_ahb", + "bmic_smmu_ahb", "bmic_smmu_axi", + "camss_ahb_clk", "camss_top_ahb_clk", + "ispif_ahb_clk", "csi_src_clk", "csiphy_clk_src", + "csi_clk", "csi_ahb_clk", "csi_rdi_clk", + "csi_pix_clk", "cphy_csid_clk"; + qcom,clock-rates = <0 0 0 0 0 0 0 274290000 274290000 + 0 0 0 0 0>; + status = "ok"; + }; + + qcom,cam_smmu { + compatible = "qcom,msm-cam-smmu"; + status = "ok"; + + msm_cam_smmu_cb1 { + compatible = "qcom,msm-cam-smmu-cb"; + iommus = <&mmss_smmu 0xc00>, + <&mmss_smmu 0xc01>, + <&mmss_smmu 0xc02>, + <&mmss_smmu 0xc03>; + label = "vfe"; + qcom,scratch-buf-support; + }; + + msm_cam_smmu_cb2 { + compatible = "qcom,msm-cam-smmu-cb"; + iommus = <&mmss_smmu 0xa00>; + label = "cpp"; + }; + + msm_cam_smmu_cb3 { + compatible = "qcom,msm-cam-smmu-cb"; + iommus = <&mmss_smmu 0xa01>; + label = "camera_fd"; + }; + + msm_cam_smmu_cb4 { + compatible = "qcom,msm-cam-smmu-cb"; + iommus = <&mmss_smmu 0x800>; + label = "jpeg_enc0"; + }; + + msm_cam_smmu_cb5 { + compatible = "qcom,msm-cam-smmu-cb"; + iommus = <&mmss_smmu 0x801>; + label = "jpeg_dma"; + }; + }; + + qcom,fd@caa4000 { + cell-index = <0>; + compatible = "qcom,face-detection"; + reg = <0xcaa4000 0x800>, + <0xcaa5000 0x400>, + <0xca80000 0x3000>; + reg-names = "fd_core", "fd_misc", "fd_vbif"; + interrupts = <0 293 0>; + interrupt-names = "fd"; + smmu-vdd-supply = <&gdsc_bimc_smmu>; + camss-vdd-supply = <&gdsc_camss_top>; + vdd-supply = <&gdsc_cpp>; + qcom,vdd-names = "smmu-vdd", "camss-vdd", "vdd"; + clocks = <&clock_gcc clk_mmssnoc_axi_clk>, + <&clock_mmss clk_mmss_mnoc_ahb_clk>, + <&clock_mmss clk_mmss_bimc_smmu_ahb_clk>, + <&clock_mmss clk_mmss_bimc_smmu_axi_clk>, + <&clock_mmss clk_mmss_camss_ahb_clk>, + <&clock_mmss clk_mmss_camss_top_ahb_clk>, + <&clock_mmss clk_mmss_fd_core_clk>, + <&clock_mmss clk_mmss_fd_core_uar_clk>, + <&clock_mmss clk_mmss_fd_ahb_clk>, + <&clock_mmss clk_mmss_camss_cpp_axi_clk>, + <&clock_mmss clk_mmss_camss_cpp_vbif_ahb_clk>; + clock-names = "mmssnoc_axi", + "mmss_mnoc_ahb_clk", + "mmss_bimc_smmu_ahb_clk", + "mmss_bimc_smmu_axi_clk", + "mmss_camss_ahb_clk", + "mmss_camss_top_ahb_clk", + "mmss_fd_core_clk", + "mmss_fd_core_uar_clk", + "mmss_fd_ahb_clk", + "mmss_camss_cpp_axi_clk", + "mmss_camss_cpp_vbif_ahb_clk"; + qcom,clock-rates = + <0 0 0 0 0 0 404000000 0 0 0 0>, + <0 0 0 0 0 0 100000000 0 0 0 0>, + <0 0 0 0 0 0 404000000 0 0 0 0>, + <0 0 0 0 0 0 404000000 0 0 0 0>; + qcom,msm-bus,name = "msm_camera_fd"; + qcom,msm-bus,num-cases = <4>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = <106 512 0 0>, + <106 512 1625 0>, + <106 512 2995 0>, + <106 512 7200 0>; + qcom,fd-vbif-reg-settings = <0x20 0x10000000 0x30000000>, + <0x24 0x10000000 0x30000000>, + <0x28 0x10000000 0x30000000>, + <0x2c 0x10000000 0x30000000>; + qcom,fd-misc-reg-settings = <0x20 0x2 0x3>, + <0x24 0x2 0x3>; + status = "ok"; + }; + + qcom,cpp@ca04000 { + cell-index = <0>; + compatible = "qcom,cpp"; + reg = <0xca04000 0x100>, + <0xca80000 0x3000>, + <0xca18000 0x3000>, + <0xc8c36D4 0x4>; + reg-names = "cpp", "cpp_vbif", "cpp_hw", "camss_cpp"; + interrupts = <0 294 0>; + interrupt-names = "cpp"; + smmu-vdd-supply = <&gdsc_bimc_smmu>; + camss-vdd-supply = <&gdsc_camss_top>; + vdd-supply = <&gdsc_cpp>; + qcom,vdd-names = "smmu-vdd", "camss-vdd", "vdd"; + clocks = <&clock_gcc clk_mmssnoc_axi_clk>, + <&clock_mmss clk_mmss_mnoc_ahb_clk>, + <&clock_mmss clk_mmss_camss_ahb_clk>, + <&clock_mmss clk_mmss_camss_top_ahb_clk>, + <&clock_mmss clk_cpp_clk_src>, + <&clock_mmss clk_mmss_camss_cpp_clk>, + <&clock_mmss clk_mmss_camss_cpp_ahb_clk>, + <&clock_mmss clk_mmss_camss_cpp_axi_clk>, + <&clock_mmss clk_mmss_camss_micro_ahb_clk>, + <&clock_mmss clk_mmss_bimc_smmu_axi_clk>, + <&clock_mmss clk_mmss_camss_cpp_vbif_ahb_clk>; + clock-names = "mmssnoc_axi_clk", + "mnoc_ahb_clk", + "camss_ahb_clk", "camss_top_ahb_clk", + "cpp_src_clk", + "cpp_core_clk", "camss_cpp_ahb_clk", + "camss_cpp_axi_clk", "micro_iface_clk", + "mmss_smmu_axi_clk", "cpp_vbif_ahb_clk"; + qcom,clock-rates = <0 0 0 0 200000000 200000000 0 0 0 0 0>; + qcom,min-clock-rate = <200000000>; + qcom,bus-master = <1>; + qcom,vbif-qos-setting = <0x550 0x33333333>, + <0x554 0x03333333>, + <0x558 0x33333333>, + <0x55c 0x03333333>, + <0x560 0x33333333>, + <0x564 0x03333333>, + <0x568 0x33333333>, + <0x56c 0x03333333>, + <0x570 0x33333333>, + <0x574 0x03333333>, + <0x578 0x33333333>, + <0x57c 0x03333333>, + <0x580 0x33333333>, + <0x584 0x03333333>, + <0x588 0x33333333>, + <0x58c 0x03333333>; + status = "ok"; + qcom,msm-bus,name = "msm_camera_cpp"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <106 512 0 0>, + <106 512 0 0>; + qcom,msm-bus-vector-dyn-vote; + resets = <&clock_mmss CAMSS_MICRO_BCR>; + reset-names = "micro_iface_reset"; + qcom,src-clock-rates = <100000000 200000000 576000000 + 600000000>; + qcom,micro-reset; + qcom,cpp-fw-payload-info { + qcom,stripe-base = <790>; + qcom,plane-base = <715>; + qcom,stripe-size = <63>; + qcom,plane-size = <25>; + qcom,fe-ptr-off = <11>; + qcom,we-ptr-off = <23>; + qcom,ref-fe-ptr-off = <17>; + qcom,ref-we-ptr-off = <36>; + qcom,we-meta-ptr-off = <42>; + qcom,fe-mmu-pf-ptr-off = <7>; + qcom,ref-fe-mmu-pf-ptr-off = <10>; + qcom,we-mmu-pf-ptr-off = <13>; + qcom,dup-we-mmu-pf-ptr-off = <18>; + qcom,ref-we-mmu-pf-ptr-off = <23>; + qcom,set-group-buffer-len = <135>; + qcom,dup-frame-indicator-off = <70>; + }; + }; + + qcom,ispif@ca31000 { + cell-index = <0>; + compatible = "qcom,ispif-v3.0", "qcom,ispif"; + reg = <0xca31000 0xc00>, + <0xca00020 0x4>; + reg-names = "ispif", "csi_clk_mux"; + interrupts = <0 309 0>; + interrupt-names = "ispif"; + qcom,num-isps = <0x2>; + camss-vdd-supply = <&gdsc_camss_top>; + vfe0-vdd-supply = <&gdsc_vfe0>; + vfe1-vdd-supply = <&gdsc_vfe1>; + qcom,vdd-names = "camss-vdd", "vfe0-vdd", + "vfe1-vdd"; + qcom,clock-cntl-support; + clocks = <&clock_gcc clk_mmssnoc_axi_clk>, + <&clock_mmss clk_mmss_mnoc_ahb_clk>, + <&clock_mmss clk_mmss_camss_ahb_clk>, + <&clock_mmss clk_mmss_camss_top_ahb_clk>, + <&clock_mmss clk_mmss_camss_ispif_ahb_clk>, + <&clock_mmss clk_csi0_clk_src>, + <&clock_mmss clk_csi1_clk_src>, + <&clock_mmss clk_csi2_clk_src>, + <&clock_mmss clk_csi3_clk_src>, + <&clock_mmss clk_mmss_camss_csi0rdi_clk>, + <&clock_mmss clk_mmss_camss_csi1rdi_clk>, + <&clock_mmss clk_mmss_camss_csi2rdi_clk>, + <&clock_mmss clk_mmss_camss_csi3rdi_clk>, + <&clock_mmss clk_mmss_camss_csi0pix_clk>, + <&clock_mmss clk_mmss_camss_csi1pix_clk>, + <&clock_mmss clk_mmss_camss_csi2pix_clk>, + <&clock_mmss clk_mmss_camss_csi3pix_clk>, + <&clock_mmss clk_mmss_camss_csi0_clk>, + <&clock_mmss clk_mmss_camss_csi1_clk>, + <&clock_mmss clk_mmss_camss_csi2_clk>, + <&clock_mmss clk_mmss_camss_csi3_clk>, + <&clock_mmss clk_vfe0_clk_src>, + <&clock_mmss clk_mmss_camss_vfe0_clk>, + <&clock_mmss clk_mmss_camss_csi_vfe0_clk>, + <&clock_mmss clk_vfe1_clk_src>, + <&clock_mmss clk_mmss_camss_vfe1_clk>, + <&clock_mmss clk_mmss_camss_csi_vfe1_clk>; + clock-names = "mmssnoc_axi", "mnoc_ahb_clk", + "camss_ahb_clk", + "camss_top_ahb_clk", "ispif_ahb_clk", + "csi0_src_clk", "csi1_src_clk", + "csi2_src_clk", "csi3_src_clk", + "csi0_rdi_clk", "csi1_rdi_clk", + "csi2_rdi_clk", "csi3_rdi_clk", + "csi0_pix_clk", "csi1_pix_clk", + "csi2_pix_clk", "csi3_pix_clk", + "camss_csi0_clk", "camss_csi1_clk", + "camss_csi2_clk", "camss_csi3_clk", + "vfe0_clk_src", + "camss_vfe_vfe0_clk", + "camss_csi_vfe0_clk", + "vfe1_clk_src", + "camss_vfe_vfe1_clk", + "camss_csi_vfe1_clk"; + qcom,clock-rates = <0 0 0 0 0 + 0 0 0 0 + 0 0 0 0 + 0 0 0 0 + 0 0 0 0 + 0 0 0 + 0 0 0>; + qcom,clock-control = "INIT_RATE", "NO_SET_RATE", + "NO_SET_RATE", "NO_SET_RATE", + "NO_SET_RATE", + "INIT_RATE", "INIT_RATE", + "INIT_RATE", "INIT_RATE", + "NO_SET_RATE", "NO_SET_RATE", + "NO_SET_RATE", "NO_SET_RATE", + "NO_SET_RATE", "NO_SET_RATE", + "NO_SET_RATE", "NO_SET_RATE", + "NO_SET_RATE", "NO_SET_RATE", + "NO_SET_RATE", "NO_SET_RATE", + "INIT_RATE", + "NO_SET_RATE", "NO_SET_RATE", + "INIT_RATE", + "NO_SET_RATE", "NO_SET_RATE"; + status = "ok"; + }; + + vfe0: qcom,vfe0@ca10000 { + cell-index = <0>; + compatible = "qcom,vfe48"; + reg = <0xca10000 0x4000>, + <0xca40000 0x3000>; + reg-names = "vfe", "vfe_vbif"; + interrupts = <0 314 0>; + interrupt-names = "vfe"; + vdd-supply = <&gdsc_vfe0>; + camss-vdd-supply = <&gdsc_camss_top>; + smmu-vdd-supply = <&gdsc_bimc_smmu>; + qcom,vdd-names = "vdd", "camss-vdd", "smmu-vdd"; + clocks = <&clock_gcc clk_mmssnoc_axi_clk>, + <&clock_mmss clk_mmss_mnoc_ahb_clk>, + <&clock_mmss clk_mmss_bimc_smmu_ahb_clk>, + <&clock_mmss clk_mmss_bimc_smmu_axi_clk>, + <&clock_mmss clk_mmss_camss_ahb_clk>, + <&clock_mmss clk_mmss_camss_top_ahb_clk>, + <&clock_mmss clk_vfe0_clk_src>, + <&clock_mmss clk_mmss_camss_vfe0_clk>, + <&clock_mmss clk_mmss_camss_vfe0_stream_clk>, + <&clock_mmss clk_mmss_camss_vfe0_ahb_clk>, + <&clock_mmss clk_mmss_camss_vfe_vbif_ahb_clk>, + <&clock_mmss clk_mmss_camss_vfe_vbif_axi_clk>, + <&clock_mmss clk_mmss_camss_csi_vfe0_clk>; + clock-names = "mmssnoc_axi", "mnoc_ahb_clk", + "bimc_smmu_ahb_clk", "bimc_smmu_axi_clk", + "camss_ahb_clk", "camss_top_ahb_clk", "vfe_clk_src", + "camss_vfe_clk", "camss_vfe_stream_clk", + "camss_vfe_ahb_clk", "camss_vfe_vbif_ahb_clk", + "camss_vfe_vbif_axi_clk", + "camss_csi_vfe_clk"; + qcom,clock-rates = <0 0 0 0 0 0 480000000 0 0 0 0 0 0 + 0 0 0 0 0 0 576000000 0 0 0 0 0 0 + 0 0 0 0 0 0 600000000 0 0 0 0 0 0>; + status = "ok"; + qos-entries = <8>; + qos-regs = <0x404 0x408 0x40c 0x410 0x414 0x418 + 0x41c 0x420>; + qos-settings = <0xaaa9aaa9 + 0xaaa9aaa9 + 0xaaa9aaa9 + 0xaaa9aaa9 + 0xaaa9aaa9 + 0xaaa9aaa9 + 0xaaa9aaa9 + 0xaaa9aaa9>; + vbif-entries = <1>; + vbif-regs = <0x124>; + vbif-settings = <0x3>; + ds-entries = <17>; + ds-regs = <0x424 0x428 0x42c 0x430 0x434 + 0x438 0x43c 0x440 0x444 0x448 0x44c + 0x450 0x454 0x458 0x45c 0x460 0x464>; + ds-settings = <0xcccc0011 + 0xcccc0011 + 0xcccc0011 + 0xcccc0011 + 0xcccc0011 + 0xcccc0011 + 0xcccc0011 + 0xcccc0011 + 0xcccc0011 + 0xcccc0011 + 0xcccc0011 + 0xcccc0011 + 0xcccc0011 + 0xcccc0011 + 0xcccc0011 + 0xcccc0011 + 0x40000103>; + qcom,msm-bus,name = "msm_camera_vfe"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <29 512 0 0>, + <29 512 100000000 100000000>; + qcom,msm-bus-vector-dyn-vote; + }; + + vfe1: qcom,vfe1@ca14000 { + cell-index = <1>; + compatible = "qcom,vfe48"; + reg = <0xca14000 0x4000>, + <0xca40000 0x3000>; + reg-names = "vfe", "vfe_vbif"; + interrupts = <0 315 0>; + interrupt-names = "vfe"; + vdd-supply = <&gdsc_vfe1>; + camss-vdd-supply = <&gdsc_camss_top>; + smmu-vdd-supply = <&gdsc_bimc_smmu>; + qcom,vdd-names = "vdd", "camss-vdd", "smmu-vdd"; + clocks = <&clock_gcc clk_mmssnoc_axi_clk>, + <&clock_mmss clk_mmss_mnoc_ahb_clk>, + <&clock_mmss clk_mmss_bimc_smmu_ahb_clk>, + <&clock_mmss clk_mmss_bimc_smmu_axi_clk>, + <&clock_mmss clk_mmss_camss_ahb_clk>, + <&clock_mmss clk_mmss_camss_top_ahb_clk>, + <&clock_mmss clk_vfe1_clk_src>, + <&clock_mmss clk_mmss_camss_vfe1_clk>, + <&clock_mmss clk_mmss_camss_vfe1_stream_clk>, + <&clock_mmss clk_mmss_camss_vfe1_ahb_clk>, + <&clock_mmss clk_mmss_camss_vfe_vbif_ahb_clk>, + <&clock_mmss clk_mmss_camss_vfe_vbif_axi_clk>, + <&clock_mmss clk_mmss_camss_csi_vfe1_clk>; + clock-names = "mmssnoc_axi", "mnoc_ahb_clk", + "bimc_smmu_ahb_clk", "bimc_smmu_axi_clk", + "camss_ahb_clk", "camss_top_ahb_clk", "vfe_clk_src", + "camss_vfe_clk", "camss_vfe_stream_clk", + "camss_vfe_ahb_clk", "camss_vfe_vbif_ahb_clk", + "camss_vfe_vbif_axi_clk", + "camss_csi_vfe_clk"; + qcom,clock-rates = <0 0 0 0 0 0 480000000 0 0 0 0 0 0 + 0 0 0 0 0 0 576000000 0 0 0 0 0 0 + 0 0 0 0 0 0 600000000 0 0 0 0 0 0>; + status = "ok"; + qos-entries = <8>; + qos-regs = <0x404 0x408 0x40c 0x410 0x414 0x418 + 0x41c 0x420>; + qos-settings = <0xaaa9aaa9 + 0xaaa9aaa9 + 0xaaa9aaa9 + 0xaaa9aaa9 + 0xaaa9aaa9 + 0xaaa9aaa9 + 0xaaa9aaa9 + 0xaaa9aaa9>; + vbif-entries = <1>; + vbif-regs = <0x124>; + vbif-settings = <0x3>; + ds-entries = <17>; + ds-regs = <0x424 0x428 0x42c 0x430 0x434 + 0x438 0x43c 0x440 0x444 0x448 0x44c + 0x450 0x454 0x458 0x45c 0x460 0x464>; + ds-settings = <0xcccc0011 + 0xcccc0011 + 0xcccc0011 + 0xcccc0011 + 0xcccc0011 + 0xcccc0011 + 0xcccc0011 + 0xcccc0011 + 0xcccc0011 + 0xcccc0011 + 0xcccc0011 + 0xcccc0011 + 0xcccc0011 + 0xcccc0011 + 0xcccc0011 + 0xcccc0011 + 0x40000103>; + qcom,msm-bus,name = "msm_camera_vfe"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <29 512 0 0>, + <29 512 100000000 100000000>; + qcom,msm-bus-vector-dyn-vote; + }; + + qcom,vfe { + compatible = "qcom,vfe"; + num_child = <2>; + }; + + cci: qcom,cci@ca0c000 { + cell-index = <0>; + compatible = "qcom,cci"; + reg = <0xca0c000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "cci"; + interrupts = <0 295 0>; + interrupt-names = "cci"; + status = "ok"; + mmagic-supply = <&gdsc_bimc_smmu>; + gdscr-supply = <&gdsc_camss_top>; + qcom,cam-vreg-name = "mmagic", "gdscr"; + clocks = <&clock_gcc clk_mmssnoc_axi_clk>, + <&clock_mmss clk_mmss_mnoc_ahb_clk>, + <&clock_mmss clk_mmss_bimc_smmu_ahb_clk>, + <&clock_mmss clk_mmss_bimc_smmu_axi_clk>, + <&clock_mmss clk_mmss_camss_ahb_clk>, + <&clock_mmss clk_mmss_camss_top_ahb_clk>, + <&clock_mmss clk_cci_clk_src>, + <&clock_mmss clk_mmss_camss_cci_ahb_clk>, + <&clock_mmss clk_mmss_camss_cci_clk>; + clock-names = "mmssnoc_axi", "mnoc_ahb", "smmu_ahb", "smmu_axi", + "camss_ahb_clk", "camss_top_ahb_clk", + "cci_src_clk", "cci_ahb_clk", "camss_cci_clk"; + qcom,clock-rates = <0 0 0 0 0 0 19200000 0 0>, + <0 0 0 0 0 0 37500000 0 0>; + pinctrl-names = "cci_default", "cci_suspend"; + pinctrl-0 = <&cci0_active &cci1_active>; + pinctrl-1 = <&cci0_suspend &cci1_suspend>; + gpios = <&tlmm 17 0>, + <&tlmm 18 0>, + <&tlmm 19 0>, + <&tlmm 20 0>; + qcom,gpio-tbl-num = <0 1 2 3>; + qcom,gpio-tbl-flags = <1 1 1 1>; + qcom,gpio-tbl-label = "CCI_I2C_DATA0", + "CCI_I2C_CLK0", + "CCI_I2C_DATA1", + "CCI_I2C_CLK1"; + i2c_freq_100Khz: qcom,i2c_standard_mode { + status = "disabled"; + }; + i2c_freq_400Khz: qcom,i2c_fast_mode { + status = "disabled"; + }; + i2c_freq_custom: qcom,i2c_custom_mode { + status = "disabled"; + }; + i2c_freq_1Mhz: qcom,i2c_fast_plus_mode { + status = "disabled"; + }; + }; + + qcom,jpeg@ca1c000 { + cell-index = <0>; + compatible = "qcom,jpeg"; + reg = <0xca1c000 0x4000>, + <0xca60000 0x3000>; + reg-names = "jpeg_hw", "jpeg_vbif"; + interrupts = <0 316 0>; + interrupt-names = "jpeg"; + smmu-vdd-supply = <&gdsc_bimc_smmu>; + camss-vdd-supply = <&gdsc_camss_top>; + qcom,vdd-names = "smmu-vdd", "camss-vdd"; + clock-names = "mmssnoc_axi", + "mmss_mnoc_ahb_clk", + "mmss_bimc_smmu_ahb_clk", + "mmss_bimc_smmu_axi_clk", + "mmss_camss_ahb_clk", + "mmss_camss_top_ahb_clk", + "core_clk", + "mmss_camss_jpeg_ahb_clk", + "mmss_camss_jpeg_axi_clk"; + clocks = <&clock_gcc clk_mmssnoc_axi_clk>, + <&clock_mmss clk_mmss_mnoc_ahb_clk>, + <&clock_mmss clk_mmss_bimc_smmu_ahb_clk>, + <&clock_mmss clk_mmss_bimc_smmu_axi_clk>, + <&clock_mmss clk_mmss_camss_ahb_clk>, + <&clock_mmss clk_mmss_camss_top_ahb_clk>, + <&clock_mmss clk_mmss_camss_jpeg0_vote_clk>, + <&clock_mmss clk_mmss_camss_jpeg_ahb_clk>, + <&clock_mmss clk_mmss_camss_jpeg_axi_clk>; + qcom,clock-rates = <0 0 0 0 0 0 480000000 0 0>; + qcom,vbif-reg-settings = <0x4 0x1>; + qcom,prefetch-reg-settings = <0x30c 0x1111>, + <0x318 0x31>, + <0x324 0x31>, + <0x330 0x31>, + <0x33c 0x0>; + qcom,msm-bus,name = "msm_camera_jpeg0"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = <62 512 0 0>, + <62 512 1920000 2880000>; + status = "ok"; + }; + + qcom,jpeg@caa0000 { + cell-index = <3>; + compatible = "qcom,jpegdma"; + reg = <0xcaa0000 0x4000>, + <0xca60000 0x3000>; + reg-names = "jpeg_hw", "jpeg_vbif"; + interrupts = <0 304 0>; + interrupt-names = "jpeg"; + smmu-vdd-supply = <&gdsc_bimc_smmu>; + camss-vdd-supply = <&gdsc_camss_top>; + qcom,vdd-names = "smmu-vdd", "camss-vdd"; + clock-names = "mmssnoc_axi", + "mmss_mnoc_ahb_clk", + "mmss_bimc_smmu_ahb_clk", + "mmss_bimc_smmu_axi_clk", + "mmss_camss_ahb_clk", + "mmss_camss_top_ahb_clk", + "core_clk", + "mmss_camss_jpeg_ahb_clk", + "mmss_camss_jpeg_axi_clk"; + clocks = <&clock_gcc clk_mmssnoc_axi_clk>, + <&clock_mmss clk_mmss_mnoc_ahb_clk>, + <&clock_mmss clk_mmss_bimc_smmu_ahb_clk>, + <&clock_mmss clk_mmss_bimc_smmu_axi_clk>, + <&clock_mmss clk_mmss_camss_ahb_clk>, + <&clock_mmss clk_mmss_camss_top_ahb_clk>, + <&clock_mmss clk_mmss_camss_jpeg0_dma_vote_clk>, + <&clock_mmss clk_mmss_camss_jpeg_ahb_clk>, + <&clock_mmss clk_mmss_camss_jpeg_axi_clk>; + qcom,clock-rates = <0 0 0 0 0 0 480000000 0 0>; + qcom,vbif-reg-settings = <0x4 0x1>; + qcom,prefetch-reg-settings = <0x18c 0x11>, + <0x1a0 0x31>, + <0x1b0 0x31>; + qcom,msm-bus,name = "msm_camera_jpeg_dma"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = <62 512 0 0>, + <62 512 1920000 2880000>; + qcom,max-ds-factor = <128>; + status = "ok"; + }; +}; + +&i2c_freq_100Khz { + qcom,hw-thigh = <201>; + qcom,hw-tlow = <174>; + qcom,hw-tsu-sto = <204>; + qcom,hw-tsu-sta = <231>; + qcom,hw-thd-dat = <22>; + qcom,hw-thd-sta = <162>; + qcom,hw-tbuf = <227>; + qcom,hw-scl-stretch-en = <0>; + qcom,hw-trdhld = <6>; + qcom,hw-tsp = <3>; + qcom,cci-clk-src = <37500000>; + status = "ok"; +}; + +&i2c_freq_400Khz { + qcom,hw-thigh = <38>; + qcom,hw-tlow = <56>; + qcom,hw-tsu-sto = <40>; + qcom,hw-tsu-sta = <40>; + qcom,hw-thd-dat = <22>; + qcom,hw-thd-sta = <35>; + qcom,hw-tbuf = <62>; + qcom,hw-scl-stretch-en = <0>; + qcom,hw-trdhld = <6>; + qcom,hw-tsp = <3>; + qcom,cci-clk-src = <37500000>; + status = "ok"; +}; + +&i2c_freq_custom { + qcom,hw-thigh = <38>; + qcom,hw-tlow = <56>; + qcom,hw-tsu-sto = <40>; + qcom,hw-tsu-sta = <40>; + qcom,hw-thd-dat = <22>; + qcom,hw-thd-sta = <35>; + qcom,hw-tbuf = <62>; + qcom,hw-scl-stretch-en = <1>; + qcom,hw-trdhld = <6>; + qcom,hw-tsp = <3>; + qcom,cci-clk-src = <37500000>; + status = "ok"; +}; + +&i2c_freq_1Mhz { + qcom,hw-thigh = <16>; + qcom,hw-tlow = <22>; + qcom,hw-tsu-sto = <17>; + qcom,hw-tsu-sta = <18>; + qcom,hw-thd-dat = <16>; + qcom,hw-thd-sta = <15>; + qcom,hw-tbuf = <24>; + qcom,hw-scl-stretch-en = <0>; + qcom,hw-trdhld = <3>; + qcom,hw-tsp = <3>; + qcom,cci-clk-src = <37500000>; + status = "ok"; +}; --- /dev/null 2019-10-24 16:47:25.704025805 +0200 +++ linux-4.4.115-fbx/arch/arm64/boot/dts/qcom/msm8998-cdp.dtsi 2019-10-29 09:26:22.917196073 +0100 @@ -0,0 +1,348 @@ +/* Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "msm8998-audio-wcd.dtsi" +#include "msm-smb138x.dtsi" + +&vendor { + bluetooth: bt_wcn3990 { + compatible = "qca,wcn3990"; + qca,bt-vdd-io-supply = <&pm8998_s3>; + qca,bt-vdd-xtal-supply = <&pm8998_s5>; + qca,bt-vdd-core-supply = <&pm8998_l7>; + qca,bt-vdd-pa-supply = <&pm8998_l17>; + qca,bt-vdd-ldo-supply = <&pm8998_l25>; + qca,bt-chip-pwd-supply = <&pmi8998_bob_pin1>; + clocks = <&clock_gcc clk_rf_clk2_pin>; + clock-names = "rf_clk2"; + + qca,bt-vdd-io-voltage-level = <1352000 1352000>; + qca,bt-vdd-xtal-voltage-level = <2040000 2040000>; + qca,bt-vdd-core-voltage-level = <1800000 1800000>; + qca,bt-vdd-pa-voltage-level = <1304000 1304000>; + qca,bt-vdd-ldo-voltage-level = <3312000 3312000>; + qca,bt-chip-pwd-voltage-level = <3600000 3600000>; + + qca,bt-vdd-io-current-level = <1>; /* LPM/PFM */ + qca,bt-vdd-xtal-current-level = <1>; /* LPM/PFM */ + qca,bt-vdd-core-current-level = <1>; /* LPM/PFM */ + qca,bt-vdd-pa-current-level = <1>; /* LPM/PFM */ + qca,bt-vdd-ldo-current-level = <1>; /* LPM/PFM */ + }; +}; + +&blsp1_uart3_hs { + status = "ok"; +}; + +&ufsphy1 { + vdda-phy-supply = <&pm8998_l1>; + vdda-pll-supply = <&pm8998_l2>; + vddp-ref-clk-supply = <&pm8998_l26>; + vdda-phy-max-microamp = <51400>; + vdda-pll-max-microamp = <14600>; + vddp-ref-clk-max-microamp = <100>; + vddp-ref-clk-always-on; + status = "ok"; +}; + +&ufs1 { + vdd-hba-supply = <&gdsc_ufs>; + vdd-hba-fixed-regulator; + vcc-supply = <&pm8998_l20>; + vccq-supply = <&pm8998_l26>; + vccq2-supply = <&pm8998_s4>; + vcc-max-microamp = <750000>; + vccq-max-microamp = <560000>; + vccq2-max-microamp = <750000>; + status = "ok"; +}; + +&ufs_ice { + status = "ok"; +}; + +&sdhc_2 { + vdd-supply = <&pm8998_l21>; + qcom,vdd-voltage-level = <2950000 2960000>; + qcom,vdd-current-level = <200 800000>; + + vdd-io-supply = <&pm8998_l13>; + qcom,vdd-io-voltage-level = <1808000 2960000>; + qcom,vdd-io-current-level = <200 22000>; + + pinctrl-names = "active", "sleep"; + pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>; + pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>; + + qcom,clk-rates = <400000 20000000 25000000 + 50000000 100000000 200000000>; + qcom,bus-speed-mode = "SDR12", "SDR25", "SDR50", "DDR50", "SDR104"; + + cd-gpios = <&tlmm 95 0x1>; + + status = "ok"; +}; + +&uartblsp2dm1 { + status = "ok"; + pinctrl-names = "default"; + pinctrl-0 = <&uart_console_active>; +}; + +&pm8998_gpios { + /* GPIO 5 for Home Key */ + gpio@c400 { + status = "okay"; + qcom,mode = <0>; + qcom,pull = <0>; + qcom,vin-sel = <0>; + qcom,src-sel = <0>; + qcom,out-strength = <1>; + }; + + /* GPIO 6 for Vol+ Key */ + gpio@c500 { + status = "okay"; + qcom,mode = <0>; + qcom,pull = <0>; + qcom,vin-sel = <0>; + qcom,src-sel = <0>; + qcom,out-strength = <1>; + }; + + /* GPIO 7 for Snapshot Key */ + gpio@c600 { + status = "okay"; + qcom,mode = <0>; + qcom,pull = <0>; + qcom,vin-sel = <0>; + qcom,src-sel = <0>; + qcom,out-strength = <1>; + }; + + /* GPIO 8 for Focus Key */ + gpio@c700 { + status = "okay"; + qcom,mode = <0>; + qcom,pull = <0>; + qcom,vin-sel = <0>; + qcom,src-sel = <0>; + qcom,out-strength = <1>; + }; + + gpio@cc00 { /* GPIO 13 */ + qcom,mode = <1>; + qcom,output-type = <0>; + qcom,pull = <5>; + qcom,vin-sel = <0>; + qcom,out-strength = <1>; + qcom,src-sel = <3>; + qcom,master-en = <1>; + status = "okay"; + }; + + gpio@d200 { /* GPIO 19 - wil6210 refclk3_en */ + qcom,mode = <0>; /* Input */ + qcom,pull = <5>; /* No Pull */ + qcom,vin-sel = <1>; /* VIN1 GPIO_MV */ + qcom,src-sel = <0>; /* GPIO */ + qcom,invert = <0>; /* Invert */ + qcom,master-en = <1>; /* Enable GPIO */ + status = "okay"; + }; + + /* GPIO 21 (NFC_CLK_REQ) */ + gpio@d400 { + qcom,mode = <0>; + qcom,vin-sel = <1>; + qcom,src-sel = <0>; + qcom,master-en = <1>; + status = "okay"; + }; +}; + +&labibb { + status = "ok"; + qcom,qpnp-labibb-mode = "lcd"; +}; + +&pmi8998_wled { + qcom,led-strings-list = [00 01]; +}; + +&pmi8998_charger { + qcom,batteryless-platform; +}; + +&pmi8998_haptics { + status = "okay"; +}; + +&pm8998_vadc { + chan@83 { + label = "vph_pwr"; + reg = <0x83>; + qcom,decimation = <2>; + qcom,pre-div-channel-scaling = <1>; + qcom,calibration-type = "absolute"; + qcom,scale-function = <0>; + qcom,hw-settle-time = <0>; + qcom,fast-avg-setup = <0>; + }; + + chan@85 { + label = "vcoin"; + reg = <0x85>; + qcom,decimation = <2>; + qcom,pre-div-channel-scaling = <1>; + qcom,calibration-type = "absolute"; + qcom,scale-function = <0>; + qcom,hw-settle-time = <0>; + qcom,fast-avg-setup = <0>; + }; + + chan@4c { + label = "xo_therm"; + reg = <0x4c>; + qcom,decimation = <2>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "ratiometric"; + qcom,scale-function = <4>; + qcom,hw-settle-time = <2>; + qcom,fast-avg-setup = <0>; + }; + + chan@4d { + label = "msm_therm"; + reg = <0x4d>; + qcom,decimation = <2>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "ratiometric"; + qcom,scale-function = <2>; + qcom,hw-settle-time = <2>; + qcom,fast-avg-setup = <0>; + }; + + chan@51 { + label = "quiet_therm"; + reg = <0x51>; + qcom,decimation = <2>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "ratiometric"; + qcom,scale-function = <2>; + qcom,hw-settle-time = <2>; + qcom,fast-avg-setup = <0>; + }; +}; + +&pm8998_adc_tm { + chan@83 { + label = "vph_pwr"; + reg = <0x83>; + qcom,pre-div-channel-scaling = <1>; + qcom,calibration-type = "absolute"; + qcom,scale-function = <0>; + qcom,hw-settle-time = <0>; + qcom,btm-channel-number = <0x60>; + }; + + chan@4d { + label = "msm_therm"; + reg = <0x4d>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "ratiometric"; + qcom,scale-function = <2>; + qcom,hw-settle-time = <2>; + qcom,btm-channel-number = <0x68>; + qcom,thermal-node; + }; + + chan@51 { + label = "quiet_therm"; + reg = <0x51>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "ratiometric"; + qcom,scale-function = <2>; + qcom,hw-settle-time = <2>; + qcom,btm-channel-number = <0x70>; + qcom,thermal-node; + }; + + chan@4c { + label = "xo_therm"; + reg = <0x4c>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "ratiometric"; + qcom,scale-function = <4>; + qcom,hw-settle-time = <2>; + qcom,btm-channel-number = <0x78>; + qcom,thermal-node; + }; +}; + +&wil6210 { + status = "ok"; +}; + +&snd_9335 { + qcom,mbhc-audio-jack-type = "6-pole-jack"; +}; + +&snd_934x { + qcom,mbhc-audio-jack-type = "6-pole-jack"; +}; + +&soc { + gpio_keys { + compatible = "gpio-keys"; + input-name = "gpio-keys"; + status = "okay"; + + home { + label = "home"; + gpios = <&pm8998_gpios 5 0x1>; + linux,input-type = <1>; + linux,code = <102>; + gpio-key,wakeup; + debounce-interval = <15>; + + }; + + vol_up { + label = "volume_up"; + gpios = <&pm8998_gpios 6 0x1>; + linux,input-type = <1>; + linux,code = <115>; + gpio-key,wakeup; + debounce-interval = <15>; + }; + + cam_snapshot { + label = "cam_snapshot"; + gpios = <&pm8998_gpios 7 0x1>; + linux,input-type = <1>; + linux,code = <766>; + gpio-key,wakeup; + debounce-interval = <15>; + }; + + cam_focus { + label = "cam_focus"; + gpios = <&pm8998_gpios 8 0x1>; + linux,input-type = <1>; + linux,code = <528>; + gpio-key,wakeup; + debounce-interval = <15>; + }; + }; +}; --- /dev/null 2019-10-24 16:47:25.704025805 +0200 +++ linux-4.4.115-fbx/arch/arm64/boot/dts/qcom/msm8998-coresight.dtsi 2019-01-22 16:16:21.195225506 +0100 @@ -0,0 +1,1622 @@ +/* Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&soc { + tmc_etr: tmc@6048000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b961>; + + reg = <0x6048000 0x1000>, + <0x6064000 0x15000>; + reg-names = "tmc-base", "bam-base"; + + arm,buffer-size = <0x400000>; + arm,sg-enable; + + coresight-ctis = <&cti0 &cti8>; + + coresight-name = "coresight-tmc-etr"; + + clocks = <&clock_gcc clk_qdss_clk>, + <&clock_gcc clk_qdss_a_clk>; + clock-names = "apb_pclk", "core_a_clk"; + + port{ + tmc_etr_in_replicator: endpoint { + slave-mode; + remote-endpoint = <&replicator_out_tmc_etr>; + }; + }; + }; + + replicator: replicator@6046000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b909>; + + reg = <0x6046000 0x1000>; + reg-names = "replicator-base"; + + coresight-name = "coresight-replicator"; + + clocks = <&clock_gcc clk_qdss_clk>, + <&clock_gcc clk_qdss_a_clk>; + clock-names = "apb_pclk", "core_a_clk"; + + ports{ + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + replicator_out_tmc_etr:endpoint { + remote-endpoint = + <&tmc_etr_in_replicator>; + }; + }; + port@1 { + reg = <0>; + replicator_in_tmc_etf:endpoint { + slave-mode; + remote-endpoint = + <&tmc_etf_out_replicator>; + }; + }; + }; + }; + + tmc_etf: tmc@6047000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b961>; + + reg = <0x6047000 0x1000>; + reg-names = "tmc-base"; + + coresight-ctis = <&cti0 &cti8>; + + coresight-name = "coresight-tmc-etf"; + + arm,default-sink; + + clocks = <&clock_gcc clk_qdss_clk>, + <&clock_gcc clk_qdss_a_clk>; + clock-names = "apb_pclk", "core_a_clk"; + + ports{ + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + tmc_etf_out_replicator:endpoint { + remote-endpoint = + <&replicator_in_tmc_etf>; + }; + }; + port@1 { + reg = <0>; + tmc_etf_in_funnel_merg:endpoint { + slave-mode; + remote-endpoint = + <&funnel_merg_out_tmc_etf>; + }; + }; + }; + }; + + funnel_merg: funnel@6045000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b908>; + + reg = <0x6045000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-merg"; + + clocks = <&clock_gcc clk_qdss_clk>, + <&clock_gcc clk_qdss_a_clk>; + clock-names = "apb_pclk", "core_a_clk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_merg_out_tmc_etf:endpoint { + remote-endpoint = + <&tmc_etf_in_funnel_merg>; + }; + }; + port@1 { + reg = <0>; + funnel_merg_in_funnel_in0:endpoint { + slave-mode; + remote-endpoint = + <&funnel_in0_out_funnel_merg>; + }; + }; + port@2 { + reg = <1>; + funnel_merg_in_funnel_in1:endpoint { + slave-mode; + remote-endpoint = + <&funnel_in1_out_funnel_merg>; + }; + }; + }; + }; + + funnel_in0: funnel@6041000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b908>; + + reg = <0x6041000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-in0"; + + clocks = <&clock_gcc clk_qdss_clk>, + <&clock_gcc clk_qdss_a_clk>; + clock-names = "apb_pclk", "core_a_clk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_in0_out_funnel_merg: endpoint { + remote-endpoint = + <&funnel_merg_in_funnel_in0>; + }; + }; + port@1 { + reg = <0>; + funnel_in0_in_rpm_etm0: endpoint { + slave-mode; + remote-endpoint = + <&rpm_etm0_out_funnel_in0>; + }; + }; + port@2 { + reg = <3>; + funnel_in0_in_funnel_spss: endpoint { + slave-mode; + remote-endpoint = + <&funnel_spss_out_funnel_in0>; + }; + }; + port@3 { + reg = <6>; + funnel_in0_in_funnel_qatb: endpoint { + slave-mode; + remote-endpoint = + <&funnel_qatb_out_funnel_in0>; + }; + }; + port@4 { + reg = <7>; + funnel_in0_in_stm: endpoint { + slave-mode; + remote-endpoint = <&stm_out_funnel_in0>; + }; + }; + }; + }; + + funnel_in1: funnel@6042000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b908>; + + reg = <0x6042000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-in1"; + + clocks = <&clock_gcc clk_qdss_clk>, + <&clock_gcc clk_qdss_a_clk>; + clock-names = "apb_pclk", "core_a_clk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_in1_out_funnel_merg: endpoint { + remote-endpoint = + <&funnel_merg_in_funnel_in1>; + }; + }; + port@1 { + reg = <2>; + funnel_in1_in_tpda_nav: endpoint { + slave-mode; + remote-endpoint = + <&tpda_nav_out_funnel_in1>; + }; + }; + port@2 { + reg = <3>; + funnel_in1_in_tpda_mss: endpoint { + slave-mode; + remote-endpoint = + <&tpda_mss_out_funnel_in1>; + }; + }; + port@3 { + reg = <4>; + funnel_in1_in_audio_etm0: endpoint { + slave-mode; + remote-endpoint = + <&audio_etm0_out_funnel_in1>; + }; + }; + port@4 { + reg = <5>; + funnel_in1_in_modem_etm0: endpoint { + slave-mode; + remote-endpoint = + <&modem_etm0_out_funnel_in1>; + }; + }; + port@5 { + reg = <6>; + funnel_in1_in_funnel_apss_merg: endpoint { + slave-mode; + remote-endpoint = + <&funnel_apss_merg_out_funnel_in1>; + }; + }; + port@6 { + reg = <7>; + funnel_in1_in_gfx: endpoint { + slave-mode; + remote-endpoint = + <&gfx_out_funnel_in1>; + }; + }; + }; + }; + + funnel_apss_merg: funnel@7b70000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b908>; + + reg = <0x7b70000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-apss-merg"; + + clocks = <&clock_gcc clk_qdss_clk>, + <&clock_gcc clk_qdss_a_clk>; + clock-names = "apb_pclk", "core_a_clk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_apss_merg_out_funnel_in1: endpoint { + remote-endpoint = + <&funnel_in1_in_funnel_apss_merg>; + }; + }; + port@1 { + reg = <0>; + funnel_apss_merg_in_funnel_apss: endpoint { + slave-mode; + remote-endpoint = + <&funnel_apss_out_funnel_apss_merg>; + }; + }; + port@2 { + reg = <1>; + funnel_apss_merg_in_tpda_olc: endpoint { + slave-mode; + remote-endpoint = + <&tpda_olc_out_funnel_apss_merg>; + }; + }; + port@3 { + reg = <3>; + funnel_apss_merg_in_tpda_apss: endpoint { + slave-mode; + remote-endpoint = + <&tpda_apss_out_funnel_apss_merg>; + }; + }; + }; + }; + + funnel_apss: funnel@7b60000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b908>; + + reg = <0x7b60000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-apss"; + + clocks = <&clock_gcc clk_qdss_clk>, + <&clock_gcc clk_qdss_a_clk>; + clock-names = "apb_pclk", "core_a_clk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_apss_out_funnel_apss_merg: endpoint { + remote-endpoint = + <&funnel_apss_merg_in_funnel_apss>; + }; + }; + port@1 { + reg = <0>; + funnel_apss_in_etm0: endpoint { + slave-mode; + remote-endpoint = + <&etm0_out_funnel_apss>; + }; + }; + port@2 { + reg = <1>; + funnel_apss_in_etm1: endpoint { + slave-mode; + remote-endpoint = + <&etm1_out_funnel_apss>; + }; + }; + port@3 { + reg = <2>; + funnel_apss_in_etm2: endpoint { + slave-mode; + remote-endpoint = + <&etm2_out_funnel_apss>; + }; + }; + port@4 { + reg = <3>; + funnel_apss_in_etm3: endpoint { + slave-mode; + remote-endpoint = + <&etm3_out_funnel_apss>; + }; + }; + port@5 { + reg = <4>; + funnel_apss_in_etm4: endpoint { + slave-mode; + remote-endpoint = + <&etm4_out_funnel_apss>; + }; + }; + port@6 { + reg = <5>; + funnel_apss_in_etm5: endpoint { + slave-mode; + remote-endpoint = + <&etm5_out_funnel_apss>; + }; + }; + port@7 { + reg = <6>; + funnel_apss_in_etm6: endpoint { + slave-mode; + remote-endpoint = + <&etm6_out_funnel_apss>; + }; + }; + port@8 { + reg = <7>; + funnel_apss_in_etm7: endpoint { + slave-mode; + remote-endpoint = + <&etm7_out_funnel_apss>; + }; + }; + }; + }; + + stm: stm@6002000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b962>; + + reg = <0x6002000 0x1000>, + <0x16280000 0x180000>; + reg-names = "stm-base", "stm-data-base"; + + coresight-name = "coresight-stm"; + + clocks = <&clock_gcc clk_qdss_clk>, + <&clock_gcc clk_qdss_a_clk>; + clock-names = "apb_pclk", "core_a_clk"; + + port{ + stm_out_funnel_in0: endpoint { + remote-endpoint = <&funnel_in0_in_stm>; + }; + }; + }; + + etm0: etm@7840000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b95d>; + + reg = <0x7840000 0x1000>; + cpu = <&CPU0>; + + coresight-name = "coresight-etm0"; + + clocks = <&clock_gcc clk_qdss_clk>, + <&clock_gcc clk_qdss_a_clk>; + clock-names = "apb_pclk", "core_a_clk"; + + port{ + etm0_out_funnel_apss: endpoint { + remote-endpoint = <&funnel_apss_in_etm0>; + }; + }; + }; + + etm1: etm@7940000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b95d>; + + reg = <0x7940000 0x1000>; + cpu = <&CPU1>; + + coresight-name = "coresight-etm1"; + + clocks = <&clock_gcc clk_qdss_clk>, + <&clock_gcc clk_qdss_a_clk>; + clock-names = "apb_pclk", "core_a_clk"; + + port{ + etm1_out_funnel_apss: endpoint { + remote-endpoint = <&funnel_apss_in_etm1>; + }; + }; + }; + + etm2: etm@7A40000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b95d>; + + reg = <0x7A40000 0x1000>; + cpu = <&CPU2>; + + coresight-name = "coresight-etm2"; + + clocks = <&clock_gcc clk_qdss_clk>, + <&clock_gcc clk_qdss_a_clk>; + clock-names = "apb_pclk", "core_a_clk"; + + port{ + etm2_out_funnel_apss: endpoint { + remote-endpoint = <&funnel_apss_in_etm2>; + }; + }; + }; + + etm3: etm@7B40000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b95d>; + + reg = <0x7B40000 0x1000>; + cpu = <&CPU3>; + + coresight-name = "coresight-etm3"; + + clocks = <&clock_gcc clk_qdss_clk>, + <&clock_gcc clk_qdss_a_clk>; + clock-names = "apb_pclk", "core_a_clk"; + + port{ + etm3_out_funnel_apss: endpoint { + remote-endpoint = <&funnel_apss_in_etm3>; + }; + }; + }; + + etm4: etm@7C40000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b95d>; + + reg = <0x7C40000 0x1000>; + cpu = <&CPU4>; + + coresight-name = "coresight-etm4"; + + clocks = <&clock_gcc clk_qdss_clk>, + <&clock_gcc clk_qdss_a_clk>; + clock-names = "apb_pclk", "core_a_clk"; + + port{ + etm4_out_funnel_apss: endpoint { + remote-endpoint = <&funnel_apss_in_etm4>; + }; + }; + }; + + etm5: etm@7D40000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b95d>; + + reg = <0x7D40000 0x1000>; + cpu = <&CPU5>; + + coresight-name = "coresight-etm5"; + + clocks = <&clock_gcc clk_qdss_clk>, + <&clock_gcc clk_qdss_a_clk>; + clock-names = "apb_pclk", "core_a_clk"; + + port{ + etm5_out_funnel_apss: endpoint { + remote-endpoint = <&funnel_apss_in_etm5>; + }; + }; + }; + + etm6: etm@7E40000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b95d>; + + reg = <0x7E40000 0x1000>; + cpu = <&CPU6>; + + coresight-name = "coresight-etm6"; + + clocks = <&clock_gcc clk_qdss_clk>, + <&clock_gcc clk_qdss_a_clk>; + clock-names = "apb_pclk", "core_a_clk"; + + port{ + etm6_out_funnel_apss: endpoint { + remote-endpoint = <&funnel_apss_in_etm6>; + }; + }; + }; + + etm7: etm@7F40000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b95d>; + + reg = <0x7F40000 0x1000>; + cpu = <&CPU7>; + + coresight-name = "coresight-etm7"; + + clocks = <&clock_gcc clk_qdss_clk>, + <&clock_gcc clk_qdss_a_clk>; + clock-names = "apb_pclk", "core_a_clk"; + + port{ + etm7_out_funnel_apss: endpoint { + remote-endpoint = <&funnel_apss_in_etm7>; + }; + }; + }; + + cti0: cti@6010000 { + compatible = "arm,coresight-cti"; + reg = <0x6010000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti0"; + + clocks = <&clock_gcc clk_qdss_clk>, + <&clock_gcc clk_qdss_a_clk>; + clock-names = "core_clk", "core_a_clk"; + }; + + cti1: cti@6011000 { + compatible = "arm,coresight-cti"; + reg = <0x6011000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti1"; + + clocks = <&clock_gcc clk_qdss_clk>, + <&clock_gcc clk_qdss_a_clk>; + clock-names = "core_clk", "core_a_clk"; + }; + + cti2: cti@6012000 { + compatible = "arm,coresight-cti"; + reg = <0x6012000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti2"; + + clocks = <&clock_gcc clk_qdss_clk>, + <&clock_gcc clk_qdss_a_clk>; + clock-names = "core_clk", "core_a_clk"; + + qcom,cti-gpio-trigout = <4>; + pinctrl-names = "cti-trigout-pctrl"; + pinctrl-0 = <&trigout_a>; + }; + + cti3: cti@6013000 { + compatible = "arm,coresight-cti"; + reg = <0x6013000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti3"; + + clocks = <&clock_gcc clk_qdss_clk>, + <&clock_gcc clk_qdss_a_clk>; + clock-names = "core_clk", "core_a_clk"; + }; + + cti4: cti@6014000 { + compatible = "arm,coresight-cti"; + reg = <0x6014000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti4"; + + clocks = <&clock_gcc clk_qdss_clk>, + <&clock_gcc clk_qdss_a_clk>; + clock-names = "core_clk", "core_a_clk"; + }; + + cti5: cti@6015000 { + compatible = "arm,coresight-cti"; + reg = <0x6015000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti5"; + + clocks = <&clock_gcc clk_qdss_clk>, + <&clock_gcc clk_qdss_a_clk>; + clock-names = "core_clk", "core_a_clk"; + }; + + cti6: cti@6016000 { + compatible = "arm,coresight-cti"; + reg = <0x6016000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti6"; + + clocks = <&clock_gcc clk_qdss_clk>, + <&clock_gcc clk_qdss_a_clk>; + clock-names = "core_clk", "core_a_clk"; + }; + + cti7: cti@6017000 { + compatible = "arm,coresight-cti"; + reg = <0x6017000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti7"; + + clocks = <&clock_gcc clk_qdss_clk>, + <&clock_gcc clk_qdss_a_clk>; + clock-names = "core_clk", "core_a_clk"; + }; + + cti8: cti@6018000 { + compatible = "arm,coresight-cti"; + reg = <0x6018000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti8"; + + clocks = <&clock_gcc clk_qdss_clk>, + <&clock_gcc clk_qdss_a_clk>; + clock-names = "core_clk", "core_a_clk"; + }; + + cti9: cti@6019000 { + compatible = "arm,coresight-cti"; + reg = <0x6019000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti9"; + + clocks = <&clock_gcc clk_qdss_clk>, + <&clock_gcc clk_qdss_a_clk>; + clock-names = "core_clk", "core_a_clk"; + }; + + cti10: cti@601a000 { + compatible = "arm,coresight-cti"; + reg = <0x601a000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti10"; + + clocks = <&clock_gcc clk_qdss_clk>, + <&clock_gcc clk_qdss_a_clk>; + clock-names = "core_clk", "core_a_clk"; + }; + + cti11: cti@601b000 { + compatible = "arm,coresight-cti"; + reg = <0x601b000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti11"; + + clocks = <&clock_gcc clk_qdss_clk>, + <&clock_gcc clk_qdss_a_clk>; + clock-names = "core_clk", "core_a_clk"; + }; + + cti12: cti@601c000 { + compatible = "arm,coresight-cti"; + reg = <0x601c000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti12"; + + clocks = <&clock_gcc clk_qdss_clk>, + <&clock_gcc clk_qdss_a_clk>; + clock-names = "core_clk", "core_a_clk"; + }; + + cti13: cti@601d000 { + compatible = "arm,coresight-cti"; + reg = <0x601d000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti13"; + + clocks = <&clock_gcc clk_qdss_clk>, + <&clock_gcc clk_qdss_a_clk>; + clock-names = "core_clk", "core_a_clk"; + }; + + cti14: cti@601e000 { + compatible = "arm,coresight-cti"; + reg = <0x601e000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti14"; + + clocks = <&clock_gcc clk_qdss_clk>, + <&clock_gcc clk_qdss_a_clk>; + clock-names = "core_clk", "core_a_clk"; + }; + + cti15: cti@601f000 { + compatible = "arm,coresight-cti"; + reg = <0x601f000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti15"; + + clocks = <&clock_gcc clk_qdss_clk>, + <&clock_gcc clk_qdss_a_clk>; + clock-names = "core_clk", "core_a_clk"; + }; + + cti_cpu0: cti@7820000 { + compatible = "arm,coresight-cti"; + reg = <0x7820000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-cpu0"; + cpu = <&CPU0>; + + clocks = <&clock_gcc clk_qdss_clk>, + <&clock_gcc clk_qdss_a_clk>; + clock-names = "core_clk", "core_a_clk"; + }; + + cti_cpu1: cti@7920000 { + compatible = "arm,coresight-cti"; + reg = <0x7920000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-cpu1"; + cpu = <&CPU1>; + + clocks = <&clock_gcc clk_qdss_clk>, + <&clock_gcc clk_qdss_a_clk>; + clock-names = "core_clk", "core_a_clk"; + }; + + cti_cpu2: cti@7a20000 { + compatible = "arm,coresight-cti"; + reg = <0x7a20000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-cpu2"; + cpu = <&CPU2>; + + clocks = <&clock_gcc clk_qdss_clk>, + <&clock_gcc clk_qdss_a_clk>; + clock-names = "core_clk", "core_a_clk"; + }; + + cti_cpu3: cti@7b20000 { + compatible = "arm,coresight-cti"; + reg = <0x7b20000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-cpu3"; + cpu = <&CPU3>; + + clocks = <&clock_gcc clk_qdss_clk>, + <&clock_gcc clk_qdss_a_clk>; + clock-names = "core_clk", "core_a_clk"; + }; + + cti_cpu4: cti@7c20000 { + compatible = "arm,coresight-cti"; + reg = <0x7c20000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-cpu4"; + cpu = <&CPU4>; + + clocks = <&clock_gcc clk_qdss_clk>, + <&clock_gcc clk_qdss_a_clk>; + clock-names = "core_clk", "core_a_clk"; + }; + + cti_cpu5: cti@7d20000 { + compatible = "arm,coresight-cti"; + reg = <0x7d20000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-cpu5"; + cpu = <&CPU5>; + + clocks = <&clock_gcc clk_qdss_clk>, + <&clock_gcc clk_qdss_a_clk>; + clock-names = "core_clk", "core_a_clk"; + }; + + cti_cpu6: cti@7e20000 { + compatible = "arm,coresight-cti"; + reg = <0x7e20000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-cpu6"; + cpu = <&CPU6>; + + clocks = <&clock_gcc clk_qdss_clk>, + <&clock_gcc clk_qdss_a_clk>; + clock-names = "core_clk", "core_a_clk"; + }; + + cti_cpu7: cti@7f20000 { + compatible = "arm,coresight-cti"; + reg = <0x7f20000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-cpu7"; + cpu = <&CPU7>; + + clocks = <&clock_gcc clk_qdss_clk>, + <&clock_gcc clk_qdss_a_clk>; + clock-names = "core_clk", "core_a_clk"; + }; + + cti_apss: cti@7b80000 { + compatible = "arm,coresight-cti"; + reg = <0x7b80000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-apss"; + + clocks = <&clock_gcc clk_qdss_clk>, + <&clock_gcc clk_qdss_a_clk>; + clock-names = "core_clk", "core_a_clk"; + }; + + cti_apss_dl: cti@7bc1000 { + compatible = "arm,coresight-cti"; + reg = <0x7bc1000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-apss-dl"; + + clocks = <&clock_gcc clk_qdss_clk>, + <&clock_gcc clk_qdss_a_clk>; + clock-names = "core_clk", "core_a_clk"; + }; + + cti_olc: cti@7b91000 { + compatible = "arm,coresight-cti"; + reg = <0x7b91000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-olc"; + + clocks = <&clock_gcc clk_qdss_clk>, + <&clock_gcc clk_qdss_a_clk>; + clock-names = "core_clk", "core_a_clk"; + }; + + funnel_qatb: funnel@6005000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b908>; + + reg = <0x6005000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-qatb"; + + clocks = <&clock_gcc clk_qdss_clk>, + <&clock_gcc clk_qdss_a_clk>; + clock-names = "apb_pclk", "core_a_clk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_qatb_out_funnel_in0: endpoint { + remote-endpoint = + <&funnel_in0_in_funnel_qatb>; + }; + }; + port@1 { + reg = <0>; + funnel_qatb_in_tpda: endpoint { + slave-mode; + remote-endpoint = + <&tpda_out_funnel_qatb>; + }; + }; + port@2 { + reg = <3>; + funnel_qatb_in_funnel_dlet_qatb: endpoint { + slave-mode; + remote-endpoint = + <&funnel_dlet_qatb_out_funnel_qatb>; + }; + }; + }; + }; + + tpda: tpda@6004000 { + compatible = "qcom,coresight-tpda"; + reg = <0x6004000 0x1000>; + reg-names = "tpda-base"; + + coresight-name = "coresight-tpda"; + + qcom,tpda-atid = <65>; + qcom,bc-elem-size = <7 32>, + <9 32>; + qcom,tc-elem-size = <3 32>, + <6 32>, + <9 32>; + qcom,dsb-elem-size = <7 32>, + <9 32>; + qcom,cmb-elem-size = <3 32>, + <4 32>, + <5 32>, + <9 64>; + + clocks = <&clock_gcc clk_qdss_clk>, + <&clock_gcc clk_qdss_a_clk>; + clock-names = "core_clk", "core_a_clk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + tpda_out_funnel_qatb: endpoint { + remote-endpoint = + <&funnel_qatb_in_tpda>; + }; + }; + port@1 { + reg = <3>; + tpda_in_tpdm_vsense: endpoint { + slave-mode; + remote-endpoint = + <&tpdm_vsense_out_tpda>; + }; + }; + port@2 { + reg = <4>; + tpda_in_tpdm_dcc: endpoint { + slave-mode; + remote-endpoint = + <&tpdm_dcc_out_tpda>; + }; + }; + port@3 { + reg = <5>; + tpda_in_tpdm_prng: endpoint { + slave-mode; + remote-endpoint = + <&tpdm_prng_out_tpda>; + }; + }; + port@4 { + reg = <7>; + tpda_in_tpdm_qm: endpoint { + slave-mode; + remote-endpoint = + <&tpdm_qm_out_tpda>; + }; + }; + port@5 { + reg = <9>; + tpda_in_tpdm_pimem: endpoint { + slave-mode; + remote-endpoint = + <&tpdm_pimem_out_tpda>; + }; + }; + }; + }; + + tpdm_vsense: tpdm@7038000 { + compatible = "qcom,coresight-tpdm"; + reg = <0x7038000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-vsense"; + + clocks = <&clock_gcc clk_qdss_clk>, + <&clock_gcc clk_qdss_a_clk>; + clock-names = "core_clk", "core_a_clk"; + + port{ + tpdm_vsense_out_tpda: endpoint { + remote-endpoint = <&tpda_in_tpdm_vsense>; + }; + }; + }; + + tpdm_dcc: tpdm@7054000 { + compatible = "qcom,coresight-tpdm"; + reg = <0x7054000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-dcc"; + + clocks = <&clock_gcc clk_qdss_clk>, + <&clock_gcc clk_qdss_a_clk>; + clock-names = "core_clk", "core_a_clk"; + + port{ + tpdm_dcc_out_tpda: endpoint { + remote-endpoint = <&tpda_in_tpdm_dcc>; + }; + }; + }; + + tpdm_prng: tpdm@704c000 { + compatible = "qcom,coresight-tpdm"; + reg = <0x704c000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-prng"; + + clocks = <&clock_gcc clk_qdss_clk>, + <&clock_gcc clk_qdss_a_clk>; + clock-names = "core_clk", "core_a_clk"; + + port{ + tpdm_prng_out_tpda: endpoint { + remote-endpoint = <&tpda_in_tpdm_prng>; + }; + }; + }; + + tpdm_qm: tpdm@71d0000 { + compatible = "qcom,coresight-tpdm"; + reg = <0x71d0000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-qm"; + + clocks = <&clock_gcc clk_qdss_clk>, + <&clock_gcc clk_qdss_a_clk>; + clock-names = "core_clk", "core_a_clk"; + + qcom,msr-fix-req; + + port{ + tpdm_qm_out_tpda: endpoint { + remote-endpoint = <&tpda_in_tpdm_qm>; + }; + }; + + }; + + tpdm_pimem: tpdm@7050000 { + compatible = "qcom,coresight-tpdm"; + reg = <0x7050000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-pimem"; + + clocks = <&clock_gcc clk_qdss_clk>, + <&clock_gcc clk_qdss_a_clk>; + clock-names = "core_clk", "core_a_clk"; + + qcom,msr-fix-req; + + port{ + tpdm_pimem_out_tpda: endpoint { + remote-endpoint = <&tpda_in_tpdm_pimem>; + }; + }; + + }; + + tpda_apss: tpda@7bc2000 { + compatible = "qcom,coresight-tpda"; + reg = <0x7bc2000 0x1000>; + reg-names = "tpda-base"; + + coresight-name = "coresight-tpda-apss"; + + qcom,tpda-atid = <66>; + qcom,dsb-elem-size = <0 32>; + + clocks = <&clock_gcc clk_qdss_clk>, + <&clock_gcc clk_qdss_a_clk>; + clock-names = "core_clk", "core_a_clk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + tpda_apss_out_funnel_apss_merg: endpoint { + remote-endpoint = + <&funnel_apss_merg_in_tpda_apss>; + }; + }; + port@1 { + reg = <0>; + tpda_apss_in_tpdm_apss: endpoint { + slave-mode; + remote-endpoint = + <&tpdm_apss_out_tpda_apss>; + }; + }; + }; + }; + + tpdm_apss: tpdm@7bc0000 { + compatible = "qcom,coresight-tpdm"; + reg = <0x7bc0000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-apss"; + + clocks = <&clock_gcc clk_qdss_clk>, + <&clock_gcc clk_qdss_a_clk>; + clock-names = "core_clk", "core_a_clk"; + + qcom,msr-fix-req; + + port{ + tpdm_apss_out_tpda_apss: endpoint { + remote-endpoint = <&tpda_apss_in_tpdm_apss>; + }; + }; + }; + + tpda_mss: tpda@7043000 { + compatible = "qcom,coresight-tpda"; + reg = <0x7043000 0x1000>; + reg-names = "tpda-base"; + + coresight-name = "coresight-tpda-mss"; + + qcom,tpda-atid = <67>; + qcom,dsb-elem-size = <0 32>; + qcom,cmb-elem-size = <0 32>; + + clocks = <&clock_gcc clk_qdss_clk>, + <&clock_gcc clk_qdss_a_clk>; + clock-names = "core_clk", "core_a_clk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + tpda_mss_out_funnel_in1: endpoint { + remote-endpoint = + <&funnel_in1_in_tpda_mss>; + }; + }; + port@1 { + reg = <0>; + tpda_mss_in_tpdm_mss: endpoint { + slave-mode; + remote-endpoint = + <&tpdm_mss_out_tpda_mss>; + }; + }; + }; + }; + + tpdm_mss: tpdm@7042000 { + compatible = "qcom,coresight-tpdm"; + reg = <0x7042000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-mss"; + + clocks = <&clock_gcc clk_qdss_clk>, + <&clock_gcc clk_qdss_a_clk>; + clock-names = "core_clk", "core_a_clk"; + + qcom,msr-fix-req; + + port{ + tpdm_mss_out_tpda_mss: endpoint { + remote-endpoint = <&tpda_mss_in_tpdm_mss>; + }; + }; + }; + + tpda_nav: tpda@7191000 { + compatible = "qcom,coresight-tpda"; + reg = <0x7191000 0x1000>; + reg-names = "tpda-base"; + + coresight-name = "coresight-tpda-nav"; + + qcom,tpda-atid = <68>; + qcom,cmb-elem-size = <0 32>; + + clocks = <&clock_gcc clk_qdss_clk>, + <&clock_gcc clk_qdss_a_clk>; + clock-names = "core_clk", "core_a_clk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + tpda_nav_out_funnel_in1: endpoint { + remote-endpoint = + <&funnel_in1_in_tpda_nav>; + }; + }; + port@1 { + reg = <0>; + tpda_nav_in_tpdm_nav: endpoint { + slave-mode; + remote-endpoint = + <&tpdm_nav_out_tpda_nav>; + }; + }; + }; + }; + + tpdm_nav: tpdm@7190000 { + compatible = "qcom,coresight-tpdm"; + reg = <0x7190000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-nav"; + + clocks = <&clock_gcc clk_qdss_clk>, + <&clock_gcc clk_qdss_a_clk>; + clock-names = "core_clk", "core_a_clk"; + + port{ + tpdm_nav_out_tpda_nav: endpoint { + remote-endpoint = <&tpda_nav_in_tpdm_nav>; + }; + }; + }; + + tpda_olc: tpda@7b92000 { + compatible = "qcom,coresight-tpda"; + reg = <0x7b92000 0x1000>; + reg-names = "tpda-base"; + + coresight-name = "coresight-tpda-olc"; + + qcom,tpda-atid = <69>; + qcom,cmb-elem-size = <0 64>; + + clocks = <&clock_gcc clk_qdss_clk>, + <&clock_gcc clk_qdss_a_clk>; + clock-names = "core_clk", "core_a_clk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + tpda_olc_out_funnel_apss_merg: endpoint { + remote-endpoint = + <&funnel_apss_merg_in_tpda_olc>; + }; + }; + port@1 { + reg = <0>; + tpda_olc_in_tpdm_olc: endpoint { + slave-mode; + remote-endpoint = + <&tpdm_olc_out_tpda_olc>; + }; + }; + }; + }; + + tpdm_olc: tpdm@7b90000 { + compatible = "qcom,coresight-tpdm"; + reg = <0x7b90000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-olc"; + + clocks = <&clock_gcc clk_qdss_clk>, + <&clock_gcc clk_qdss_a_clk>; + clock-names = "core_clk", "core_a_clk"; + + port{ + tpdm_olc_out_tpda_olc: endpoint { + remote-endpoint = <&tpda_olc_in_tpdm_olc>; + }; + }; + }; + + funnel_spss: funnel@7083000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b908>; + + reg = <0x7083000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-spss"; + + clocks = <&clock_gcc clk_qdss_clk>, + <&clock_gcc clk_qdss_a_clk>; + clock-names = "apb_pclk", "core_a_clk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_spss_out_funnel_in0: endpoint { + remote-endpoint = + <&funnel_in0_in_funnel_spss>; + }; + }; + port@1 { + reg = <0>; + funnel_spss_in_tpda_spss: endpoint { + slave-mode; + remote-endpoint = + <&tpda_spss_out_funnel_spss>; + }; + }; + port@2 { + reg = <1>; + funnel_spss_in_spss_etm0: endpoint { + slave-mode; + remote-endpoint = + <&spss_etm0_out_funnel_spss>; + }; + }; + }; + }; + + tpda_spss: tpda@7082000 { + compatible = "qcom,coresight-tpda"; + reg = <0x7082000 0x1000>; + reg-names = "tpda-base"; + + coresight-name = "coresight-tpda-spss"; + + qcom,tpda-atid = <70>; + qcom,dsb-elem-size = <0 32>; + + clocks = <&clock_gcc clk_qdss_clk>, + <&clock_gcc clk_qdss_a_clk>; + clock-names = "core_clk", "core_a_clk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + tpda_spss_out_funnel_spss: endpoint { + remote-endpoint = + <&funnel_spss_in_tpda_spss>; + }; + }; + port@1 { + reg = <0>; + tpda_spss_in_tpdm_spss: endpoint { + slave-mode; + remote-endpoint = + <&tpdm_spss_out_tpda_spss>; + }; + }; + }; + }; + + tpdm_spss: tpdm@7080000 { + compatible = "qcom,coresight-tpdm"; + reg = <0x7080000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-spss"; + + clocks = <&clock_gcc clk_qdss_clk>, + <&clock_gcc clk_qdss_a_clk>; + clock-names = "core_clk", "core_a_clk"; + + qcom,msr-fix-req; + + port{ + tpdm_spss_out_tpda_spss: endpoint { + remote-endpoint = <&tpda_spss_in_tpdm_spss>; + }; + }; + }; + + hwevent: hwevent@158000 { + compatible = "qcom,coresight-hwevent"; + reg = <0x158000 0x80>, + <0x17091000 0x80>, + <0x1730200c 0x4>, + <0xc90137c 0x4>, + <0xc828018 0x80>, + <0x1c00058 0x80>, + <0x5e02038 0x4>, + <0x5e02028 0x10>, + <0x1fcb360 0x80>, + <0x1fcb760 0x80>, + <0x1fcbf60 0x80>, + <0xa8f8860 0x4>, + <0x500c260 0x4>, + <0x500d040 0x4>, + <0x1da6400 0x80>; + reg-names = "gcc-ctrl", "lpass-stm", "lpass-qdsp", "mdss-mdp", + "mdss-misc", "pcie0-hwev", "ssc-en", "ssc-hwev", + "tcsr-qdss", "tcsr-mss0", "tcsr-mss1", "usb-ctrl", + "vbif-stm", "vbif-stm-en", "ufs-mux"; + + coresight-name = "coresight-hwevent"; + + clocks = <&clock_gcc clk_qdss_clk>, + <&clock_gcc clk_qdss_a_clk>, + <&clock_mmss clk_mmss_misc_ahb_clk>; + clock-names = "core_clk", "core_a_clk", "core_mmss_clk"; + + qcom,hwevent-clks = "core_mmss_clk"; + }; + + csr: csr@6001000 { + compatible = "qcom,coresight-csr"; + reg = <0x6001000 0x1000>; + reg-names = "csr-base"; + + coresight-name = "coresight-csr"; + + qcom,blk-size = <1>; + }; + + modem_etm0 { + compatible = "qcom,coresight-remote-etm"; + + coresight-name = "coresight-modem-etm0"; + qcom,inst-id = <2>; + + port{ + modem_etm0_out_funnel_in1: endpoint { + remote-endpoint = <&funnel_in1_in_modem_etm0>; + }; + }; + }; + + audio_etm0 { + compatible = "qcom,coresight-remote-etm"; + + coresight-name = "coresight-audio-etm0"; + qcom,inst-id = <5>; + + port{ + audio_etm0_out_funnel_in1: endpoint { + remote-endpoint = <&funnel_in1_in_audio_etm0>; + }; + }; + }; + + rpm_etm0 { + compatible = "qcom,coresight-remote-etm"; + + coresight-name = "coresight-rpm-etm0"; + qcom,inst-id = <4>; + + port{ + rpm_etm0_out_funnel_in0: endpoint { + remote-endpoint = <&funnel_in0_in_rpm_etm0>; + }; + }; + }; + + funnel_dlet_qatb: funnel@7225000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b908>; + + reg = <0x7225000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-dlet-qatb"; + + clocks = <&clock_gcc clk_qdss_clk>, + <&clock_gcc clk_qdss_a_clk>; + clock-names = "apb_pclk", "core_a_clk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_dlet_qatb_out_funnel_qatb: endpoint { + remote-endpoint = + <&funnel_qatb_in_funnel_dlet_qatb>; + }; + }; + port@1 { + reg = <1>; + funnel_dlet_qatb_in_tpdm_wcss: endpoint { + slave-mode; + remote-endpoint = + <&tpdm_wcss_out_funnel_dlet_qatb>; + }; + }; + }; + }; + + dummy-tpdm-wcss { + compatible = "qcom,coresight-dummy"; + + coresight-name = "coresight-tpdm-wcss"; + + port{ + tpdm_wcss_out_funnel_dlet_qatb: endpoint { + remote-endpoint = + <&funnel_dlet_qatb_in_tpdm_wcss>; + }; + }; + }; + + dummy-spss-etm0 { + compatible = "qcom,coresight-dummy"; + + coresight-name = "coresight-spss-etm0"; + + port{ + spss_etm0_out_funnel_spss: endpoint { + remote-endpoint = + <&funnel_spss_in_spss_etm0>; + }; + }; + }; +}; --- /dev/null 2019-10-24 16:47:25.704025805 +0200 +++ linux-4.4.115-fbx/arch/arm64/boot/dts/qcom/msm8998.dtsi 2019-10-29 09:26:22.921196113 +0100 @@ -0,0 +1,3351 @@ +/* Copyright (c) 2015-2017, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "skeleton64.dtsi" +#include +#include +#include + +/ { + model = "Qualcomm Technologies, Inc. MSM 8998"; + compatible = "qcom,msm8998"; + qcom,msm-id = <292 0x0>; + interrupt-parent = <&intc>; + + aliases { + serial0 = &uartblsp2dm1; + pci-domain0 = &pcie0; + sdhc2 = &sdhc_2; /* SDC2 SD card slot */ + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + chosen { + stdout-path = "serial0"; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + CPU0: cpu@0 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x0>; + qcom,limits-info = <&mitigation_profile0>; + qcom,lmh-dcvs = <&lmh_dcvs0>; + enable-method = "psci"; + efficiency = <1024>; + next-level-cache = <&L2_0>; + qcom,ea = <&ea0>; + L2_0: l2-cache { + compatible = "arm,arch-cache"; + cache-level = <2>; + qcom,dump-size = <0x0>; /* A53 L2 dump not supported */ + }; + L1_I_0: l1-icache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x9040>; + }; + L1_D_0: l1-dcache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x9040>; + }; + L1_TLB_0: l1-tlb { + qcom,dump-size = <0x2000>; + }; + }; + + CPU1: cpu@1 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x1>; + qcom,limits-info = <&mitigation_profile1>; + qcom,lmh-dcvs = <&lmh_dcvs0>; + enable-method = "psci"; + efficiency = <1024>; + next-level-cache = <&L2_0>; + qcom,ea = <&ea1>; + L1_I_1: l1-icache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x9040>; + }; + L1_D_1: l1-dcache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x9040>; + }; + L1_TLB_1: l1-tlb { + qcom,dump-size = <0x2000>; + }; + }; + + CPU2: cpu@2 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x2>; + qcom,limits-info = <&mitigation_profile2>; + qcom,lmh-dcvs = <&lmh_dcvs0>; + enable-method = "psci"; + efficiency = <1024>; + next-level-cache = <&L2_0>; + qcom,ea = <&ea2>; + L1_I_2: l1-icache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x9040>; + }; + L1_D_2: l1-dcache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x9040>; + }; + L1_TLB_2: l1-tlb { + qcom,dump-size = <0x2000>; + }; + }; + + CPU3: cpu@3 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x3>; + qcom,limits-info = <&mitigation_profile3>; + qcom,lmh-dcvs = <&lmh_dcvs0>; + enable-method = "psci"; + efficiency = <1024>; + next-level-cache = <&L2_0>; + qcom,ea = <&ea3>; + L1_I_3: l1-icache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x9040>; + }; + L1_D_3: l1-dcache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x9040>; + }; + L1_TLB_3: l1-tlb { + qcom,dump-size = <0x2000>; + }; + }; + + CPU4: cpu@100 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x100>; + qcom,limits-info = <&mitigation_profile4>; + qcom,lmh-dcvs = <&lmh_dcvs1>; + enable-method = "psci"; + efficiency = <1536>; + next-level-cache = <&L2_1>; + qcom,ea = <&ea4>; + L2_1: l2-cache { + compatible = "arm,arch-cache"; + cache-level = <2>; + }; + L1_I_100: l1-icache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x12000>; + }; + L1_D_100: l1-dcache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x12000>; + }; + L1_TLB_100: l1-tlb { + qcom,dump-size = <0x4800>; + }; + }; + + CPU5: cpu@101 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x101>; + qcom,limits-info = <&mitigation_profile5>; + qcom,lmh-dcvs = <&lmh_dcvs1>; + enable-method = "psci"; + efficiency = <1536>; + next-level-cache = <&L2_1>; + qcom,ea = <&ea5>; + L1_I_101: l1-icache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x12000>; + }; + L1_D_101: l1-dcache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x12000>; + }; + L1_TLB_101: l1-tlb { + qcom,dump-size = <0x4800>; + }; + }; + + CPU6: cpu@102 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x102>; + qcom,limits-info = <&mitigation_profile6>; + qcom,lmh-dcvs = <&lmh_dcvs1>; + enable-method = "psci"; + efficiency = <1536>; + next-level-cache = <&L2_1>; + qcom,ea = <&ea6>; + L1_I_102: l1-icache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x12000>; + }; + L1_D_102: l1-dcache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x12000>; + }; + L1_TLB_102: l1-tlb { + qcom,dump-size = <0x4800>; + }; + }; + + CPU7: cpu@103 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x103>; + qcom,limits-info = <&mitigation_profile7>; + qcom,lmh-dcvs = <&lmh_dcvs1>; + enable-method = "psci"; + efficiency = <1536>; + next-level-cache = <&L2_1>; + qcom,ea = <&ea7>; + L1_I_103: l1-icache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x12000>; + }; + L1_D_103: l1-dcache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x12000>; + }; + L1_TLB_103: l1-tlb { + qcom,dump-size = <0x4800>; + }; + }; + + cpu-map { + cluster0 { + core0 { + cpu = <&CPU0>; + }; + + core1 { + cpu = <&CPU1>; + }; + + core2 { + cpu = <&CPU2>; + }; + + core3 { + cpu = <&CPU3>; + }; + }; + + cluster1 { + core0 { + cpu = <&CPU4>; + }; + + core1 { + cpu = <&CPU5>; + }; + + core2 { + cpu = <&CPU6>; + }; + + core3 { + cpu = <&CPU7>; + }; + }; + }; + }; + + soc: soc { }; + + vendor: vendor { + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0 0xffffffff>; + compatible = "simple-bus"; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + removed_regions: removed_regions@85800000 { + compatible = "removed-dma-pool"; + no-map; + reg = <0 0x85800000 0 0x3700000>; + }; + + pil_slpi_mem: pil_slpi_region@94400000 { + compatible = "removed-dma-pool"; + no-map; + reg = <0 0x94400000 0 0xf00000>; + }; + + pil_ipa_gpu_mem: pil_ipa_gpu_region@94300000 { + compatible = "removed-dma-pool"; + no-map; + reg = <0 0x94300000 0 0x100000>; + }; + + pil_mba_mem: pil_mba_region@94100000 { + compatible = "removed-dma-pool"; + no-map; + reg = <0 0x94100000 0 0x200000>; + }; + + pil_video_mem: pil_video_region@93c00000 { + compatible = "removed-dma-pool"; + no-map; + reg = <0 0x93c00000 0 0x500000>; + }; + + modem_mem: modem_region@8cc00000 { + compatible = "removed-dma-pool"; + no-map; + reg = <0 0x8cc00000 0 0x7000000>; + }; + + pil_adsp_mem: pil_adsp_region@0x8b200000 { + compatible = "removed-dma-pool"; + no-map; + reg = <0 0x8b200000 0 0x1a00000>; + }; + + spss_mem: spss_region@8ab00000 { /* for SPSS-PIL */ + compatible = "removed-dma-pool"; + no-map; + reg = <0 0x8ab00000 0 0x700000>; + }; + + adsp_mem: adsp_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0 0x00000000 0 0xffffffff>; + reusable; + alignment = <0 0x400000>; + size = <0 0x800000>; + }; + + qseecom_mem: qseecom_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0 0x00000000 0 0xffffffff>; + reusable; + alignment = <0 0x400000>; + size = <0 0x1400000>; + }; + + sp_mem: sp_region { /* SPSS-HLOS ION shared mem */ + compatible = "shared-dma-pool"; + alloc-ranges = <0 0x00000000 0 0xffffffff>; /* 32-bit */ + reusable; + alignment = <0 0x100000>; + size = <0 0x800000>; + }; + + secure_display_memory: secure_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0 0x00000000 0 0xffffffff>; + reusable; + alignment = <0 0x200000>; + size = <0 0x8000000>; + }; + + /* global autoconfigured region for contiguous allocations */ + linux,cma { + compatible = "shared-dma-pool"; + alloc-ranges = <0 0x00000000 0 0xffffffff>; + reusable; + alignment = <0 0x400000>; + size = <0 0x2000000>; + linux,cma-default; + }; + + cont_splash_mem: splash_region@9d600000 { + reg = <0x0 0x9d600000 0x0 0x02400000>; + label = "cont_splash_mem"; + }; + }; +}; + +#include "msm8998-smp2p.dtsi" +#include "msm-gdsc-8998.dtsi" + +&soc { + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0 0xffffffff>; + compatible = "simple-bus"; + + intc: interrupt-controller@17a00000 { + compatible = "arm,gic-v3"; + reg = <0x17a00000 0x10000>, /* GICD */ + <0x17b00000 0x100000>; /* GICR * 8 */ + #interrupt-cells = <3>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + interrupt-controller; + #redistributor-regions = <1>; + redistributor-stride = <0x0 0x20000>; + interrupts = <1 9 4>; + + gic-its@0x17a20000{ + compatible = "arm,gic-v3-its"; + msi-contoller; + reg = <0x17a20000 0x20000>; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <1 1 0xf08>, + <1 2 0xf08>, + <1 3 0xf08>, + <1 0 0xf08>; + clock-frequency = <19200000>; + }; + + restart@10ac000 { + compatible = "qcom,pshold"; + reg = <0x10ac000 0x4>, + <0x1fd3000 0x4>; + reg-names = "pshold-base", "tcsr-boot-misc-detect"; + }; + + spmi_bus: qcom,spmi@800f000 { + compatible = "qcom,spmi-pmic-arb"; + reg = <0x800f000 0x1000>, + <0x8400000 0x1000000>, + <0x9400000 0x1000000>, + <0xa400000 0x220000>, + <0x800a000 0x3000>; + reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; + interrupt-names = "periph_irq"; + interrupts = ; + qcom,ee = <0>; + qcom,channel = <0>; + qcom,reserved-chan = <511>; + #address-cells = <2>; + #size-cells = <0>; + interrupt-controller; + #interrupt-cells = <4>; + cell-index = <0>; + }; + + qcom,sps { + compatible = "qcom,msm_sps_4k"; + qcom,device-type = <3>; + qcom,pipe-attr-ee; + }; + + uartblsp1dm1: serial@0c170000 { + compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; + reg = <0xc170000 0x1000>; + interrupts = <0 108 0>; + status = "disabled"; + clocks = <&clock_gcc clk_gcc_blsp1_uart2_apps_clk>, + <&clock_gcc clk_gcc_blsp1_ahb_clk>; + clock-names = "core", "iface"; + }; + + uartblsp2dm1: serial@0c1b0000 { + compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; + reg = <0xc1b0000 0x1000>; + interrupts = <0 114 0>; + status = "disabled"; + clocks = <&clock_gcc clk_gcc_blsp2_uart2_apps_clk>, + <&clock_gcc clk_gcc_blsp2_ahb_clk>; + clock-names = "core", "iface"; + }; + + slim_aud: slim@171c0000 { + cell-index = <1>; + compatible = "qcom,slim-ngd"; + reg = <0x171c0000 0x2C000>, + <0x17184000 0x32000>; + reg-names = "slimbus_physical", "slimbus_bam_physical"; + interrupts = <0 163 0>, <0 164 0>; + interrupt-names = "slimbus_irq", "slimbus_bam_irq"; + qcom,apps-ch-pipes = <0x00001f80>; + qcom,ea-pc = <0x210>; + }; + + slim_qca: slim@17240000 { + status = "ok"; + cell-index = <3>; + compatible = "qcom,slim-ngd"; + reg = <0x17240000 0x2C000>, + <0x17204000 0x26000>; + reg-names = "slimbus_physical", "slimbus_bam_physical"; + interrupts = <0 291 0>, <0 292 0>; + interrupt-names = "slimbus_irq", "slimbus_bam_irq"; + + /* Slimbus Slave DT for WCN3990 */ + btfmslim_codec: wcn3990 { + compatible = "qcom,btfmslim_slave"; + elemental-addr = [00 01 20 02 17 02]; + qcom,btfm-slim-ifd = "btfmslim_slave_ifd"; + qcom,btfm-slim-ifd-elemental-addr = [00 00 20 02 17 02]; + }; + }; + + timer@17920000 { + #address-cells = <1>; + #size-cells = <1>; + ranges; + compatible = "arm,armv7-timer-mem"; + reg = <0x17920000 0x1000>; + clock-frequency = <19200000>; + + frame@17921000 { + frame-number = <0>; + interrupts = <0 8 0x4>, + <0 7 0x4>; + reg = <0x17921000 0x1000>, + <0x17922000 0x1000>; + }; + + frame@17923000 { + frame-number = <1>; + interrupts = <0 9 0x4>; + reg = <0x17923000 0x1000>; + status = "disabled"; + }; + + frame@17924000 { + frame-number = <2>; + interrupts = <0 10 0x4>; + reg = <0x17924000 0x1000>; + status = "disabled"; + }; + + frame@17925000 { + frame-number = <3>; + interrupts = <0 11 0x4>; + reg = <0x17925000 0x1000>; + status = "disabled"; + }; + + frame@17926000 { + frame-number = <4>; + interrupts = <0 12 0x4>; + reg = <0x17926000 0x1000>; + status = "disabled"; + }; + + frame@17927000 { + frame-number = <5>; + interrupts = <0 13 0x4>; + reg = <0x17927000 0x1000>; + status = "disabled"; + }; + + frame@17928000 { + frame-number = <6>; + interrupts = <0 14 0x4>; + reg = <0x17928000 0x1000>; + status = "disabled"; + }; + }; + + cpubw: qcom,cpubw { + compatible = "qcom,devbw"; + governor = "performance"; + qcom,src-dst-ports = <1 512>; + qcom,active-only; + qcom,bw-tbl = + < 762 /* 100 MHz */ >, + < 1144 /* 150 MHz */ >, + < 1525 /* 200 MHz */ >, + < 2288 /* 300 MHz */ >, + < 3143 /* 412 MHz */ >, + < 4173 /* 547 MHz */ >, + < 5195 /* 681 MHz */ >, + < 5859 /* 768 MHz */ >, + < 7759 /* 1017 MHz */ >, + < 9887 /* 1296 MHz */ >, + < 11863 /* 1555 MHz */ >, + < 13763 /* 1804 MHz */ >; + }; + + bwmon: qcom,cpu-bwmon { + compatible = "qcom,bimc-bwmon3"; + reg = <0x01008000 0x300>, <0x01001000 0x200>; + reg-names = "base", "global_base"; + interrupts = <0 183 4>; + qcom,mport = <0>; + qcom,target-dev = <&cpubw>; + }; + + mincpubw: qcom,mincpubw { + compatible = "qcom,devbw"; + governor = "powersave"; + qcom,src-dst-ports = <1 512>; + qcom,active-only; + qcom,bw-tbl = + < 762 /* 100 MHz */ >, + < 1144 /* 150 MHz */ >, + < 1525 /* 200 MHz */ >, + < 2288 /* 300 MHz */ >, + < 3143 /* 412 MHz */ >, + < 4173 /* 547 MHz */ >, + < 5195 /* 681 MHz */ >, + < 5859 /* 768 MHz */ >, + < 7759 /* 1017 MHz */ >, + < 9887 /* 1296 MHz */ >, + < 11863 /* 1555 MHz */ >, + < 13763 /* 1804 MHz */ >; + }; + + memlat_cpu0: qcom,memlat-cpu0 { + compatible = "qcom,devbw"; + governor = "powersave"; + qcom,src-dst-ports = <1 512>; + qcom,active-only; + qcom,bw-tbl = + < 762 /* 100 MHz */ >, + < 1144 /* 150 MHz */ >, + < 1525 /* 200 MHz */ >, + < 2288 /* 300 MHz */ >, + < 3143 /* 412 MHz */ >, + < 4173 /* 547 MHz */ >, + < 5195 /* 681 MHz */ >, + < 5859 /* 768 MHz */ >, + < 7759 /* 1017 MHz */ >, + < 9887 /* 1296 MHz */ >, + < 11863 /* 1555 MHz */ >, + < 13763 /* 1804 MHz */ >; + }; + + memlat_cpu4: qcom,memlat-cpu4 { + compatible = "qcom,devbw"; + governor = "powersave"; + qcom,src-dst-ports = <1 512>; + qcom,active-only; + status = "ok"; + qcom,bw-tbl = + < 762 /* 100 MHz */ >, + < 1144 /* 150 MHz */ >, + < 1525 /* 200 MHz */ >, + < 2288 /* 300 MHz */ >, + < 3143 /* 412 MHz */ >, + < 4173 /* 547 MHz */ >, + < 5195 /* 681 MHz */ >, + < 5859 /* 768 MHz */ >, + < 7759 /* 1017 MHz */ >, + < 9887 /* 1296 MHz */ >, + < 11863 /* 1555 MHz */ >, + < 13763 /* 1804 MHz */ >; + }; + + devfreq_memlat_0: qcom,arm-memlat-mon-0 { + compatible = "qcom,arm-memlat-mon"; + qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3>; + qcom,target-dev = <&memlat_cpu0>; + qcom,core-dev-table = + < 300000 1525 >, + < 499200 3143 >, + < 1113600 4173 >, + < 1881600 5859 >; + }; + + devfreq_memlat_4: qcom,arm-memlat-mon-4 { + compatible = "qcom,arm-memlat-mon"; + qcom,cpulist = <&CPU4 &CPU5 &CPU6 &CPU7>; + qcom,target-dev = <&memlat_cpu4>; + qcom,core-dev-table = + < 300000 1525 >, + < 480000 3143 >, + < 900000 4173 >, + < 1017000 7759 >, + < 1296000 9887 >, + < 1555000 11863 >, + < 1804000 13763 >; + }; + + devfreq_cpufreq: devfreq-cpufreq { + mincpubw-cpufreq { + target-dev = <&mincpubw>; + cpu-to-dev-map-0 = + < 1881600 1525 >; + cpu-to-dev-map-4 = + < 2016000 1525 >, + < 2092800 5195 >; + }; + }; + + msm_cpufreq: qcom,msm-cpufreq { + compatible = "qcom,msm-cpufreq"; + clock-names = "cpu0_clk", "cpu1_clk", "cpu2_clk", + "cpu3_clk", "cpu4_clk", "cpu5_clk", + "cpu6_clk", "cpu7_clk"; + clocks = <&clock_cpu clk_pwrcl_clk>, + <&clock_cpu clk_pwrcl_clk>, + <&clock_cpu clk_pwrcl_clk>, + <&clock_cpu clk_pwrcl_clk>, + <&clock_cpu clk_perfcl_clk>, + <&clock_cpu clk_perfcl_clk>, + <&clock_cpu clk_perfcl_clk>, + <&clock_cpu clk_perfcl_clk>; + + qcom,governor-per-policy; + + qcom,cpufreq-table-0 = + < 300000 >, + < 345600 >, + < 422400 >, + < 499200 >, + < 576000 >, + < 633600 >, + < 710400 >, + < 806400 >, + < 883200 >, + < 960000 >, + < 1036800 >, + < 1113600 >, + < 1190400 >, + < 1248000 >, + < 1324800 >, + < 1401600 >, + < 1478400 >, + < 1574400 >, + < 1651200 >, + < 1728000 >, + < 1804800 >, + < 1881600 >; + + qcom,cpufreq-table-4 = + < 300000 >, + < 345600 >, + < 422400 >, + < 480000 >, + < 556800 >, + < 633600 >, + < 710400 >, + < 787200 >, + < 844800 >, + < 902400 >, + < 979200 >, + < 1056000 >, + < 1171200 >, + < 1248000 >, + < 1324800 >, + < 1401600 >, + < 1478400 >, + < 1536000 >, + < 1632000 >, + < 1708800 >, + < 1785600 >, + < 1862400 >, + < 1939200 >, + < 2016000 >, + < 2092800 >; + }; + + arm64-cpu-erp { + compatible = "arm,arm64-cpu-erp"; + interrupts = <0 43 4>, + <0 44 4>, + <0 41 4>, + <0 42 4>; + + interrupt-names = "pri-dbe-irq", + "sec-dbe-irq", + "pri-ext-irq", + "sec-ext-irq"; + + poll-delay-ms = <5000>; + }; + + clock_gcc: qcom,gcc@100000 { + compatible = "qcom,gcc-8998"; + reg = <0x100000 0xb0000>; + reg-names = "cc_base"; + vdd_dig-supply = <&pm8998_s1_level>; + vdd_dig_ao-supply = <&pm8998_s1_level_ao>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + clock_mmss: qcom,mmsscc@c8c0000 { + compatible = "qcom,mmsscc-8998"; + reg = <0xc8c0000 0x40000>; + reg-names = "cc_base"; + vdd_dig-supply = <&pm8998_s1_level>; + vdd_mmsscc_mx-supply = <&pm8998_s9_level>; + clock-names = "xo", "gpll0", "gpll0_div", + "pclk0_src", "pclk1_src", + "byte0_src", "byte1_src", + "dp_link_src", "dp_vco_div", + "extpclk_src"; + clocks = <&clock_gcc clk_cxo_clk_src>, + <&clock_gcc clk_gcc_mmss_gpll0_clk>, + <&clock_gcc clk_gcc_mmss_gpll0_div_clk>, + <&mdss_dsi0_pll clk_dsi0pll_pclk_mux>, + <&mdss_dsi1_pll clk_dsi1pll_pclk_mux>, + <&mdss_dsi0_pll clk_dsi0pll_byteclk_mux>, + <&mdss_dsi1_pll clk_dsi1pll_byteclk_mux>, + <&mdss_dp_pll clk_dp_link_2x_clk_divsel_five>, + <&mdss_dp_pll clk_vco_divided_clk_src_mux>, + <&mdss_hdmi_pll clk_hdmi_vco_clk>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + clock_gpu: qcom,gpucc@5065000 { + compatible = "qcom,gpucc-8998"; + reg = <0x5065000 0x9000>; + reg-names = "cc_base"; + vdd_dig-supply = <&pm8998_s1_level>; + clock-names = "xo_ao", "gpll0"; + clocks = <&clock_gcc clk_cxo_clk_src_ao>, + <&clock_gcc clk_gcc_gpu_gpll0_clk>; + #clock-cells = <1>; + }; + + clock_gfx: qcom,gfxcc@5065000 { + compatible = "qcom,gfxcc-8998"; + reg = <0x5065000 0x9000>; + reg-names = "cc_base"; + vdd_gpucc-supply = <&gfx_vreg>; + vdd_mx-supply = <&pm8998_s9_level>; + vdd_gpu_mx-supply = <&pm8998_s9_level>; + qcom,gfx3d_clk_src-opp-handle = <&msm_gpu>; + qcom,gfxfreq-speedbin0 = + < 0 0 0 >, + < 171000000 1 RPM_SMD_REGULATOR_LEVEL_SVS >, + < 251000000 2 RPM_SMD_REGULATOR_LEVEL_SVS >, + < 332000000 3 RPM_SMD_REGULATOR_LEVEL_SVS >, + < 403000000 4 RPM_SMD_REGULATOR_LEVEL_SVS >, + < 504000000 5 RPM_SMD_REGULATOR_LEVEL_NOM >, + < 650000000 6 RPM_SMD_REGULATOR_LEVEL_TURBO >; + qcom,gfxfreq-mx-speedbin0 = + < 0 0 >, + < 171000000 RPM_SMD_REGULATOR_LEVEL_SVS >, + < 251000000 RPM_SMD_REGULATOR_LEVEL_SVS >, + < 332000000 RPM_SMD_REGULATOR_LEVEL_SVS >, + < 403000000 RPM_SMD_REGULATOR_LEVEL_SVS >, + < 504000000 RPM_SMD_REGULATOR_LEVEL_NOM >, + < 650000000 RPM_SMD_REGULATOR_LEVEL_TURBO >; + #clock-cells = <1>; + }; + + clock_cpu: qcom,cpu-clock-8998@179c0000 { + compatible = "qcom,cpu-clock-osm-msm8998-v1"; + reg = <0x179c0000 0x4000>, + <0x17916000 0x1000>, + <0x17816000 0x1000>, + <0x179d1000 0x1000>, + <0x00784130 0x8>, + <0x1791101c 0x8>; + reg-names = "osm", "pwrcl_pll", "perfcl_pll", + "apcs_common", "perfcl_efuse", "debug"; + + vdd-pwrcl-supply = <&apc0_pwrcl_vreg>; + vdd-perfcl-supply = <&apc1_perfcl_vreg>; + + interrupts = , + ; + interrupt-names = "pwrcl-irq", "perfcl-irq"; + + qcom,pwrcl-speedbin0-v0 = + < 300000000 0x0004000f 0x01200020 0x1 1 >, + < 345600000 0x05040012 0x02200020 0x1 2 >, + < 422400000 0x05040016 0x02200020 0x1 3 >, + < 499200000 0x0504001a 0x02200020 0x1 4 >, + < 576000000 0x0504001e 0x03200020 0x1 5 >, + < 633600000 0x05040021 0x03200020 0x1 6 >, + < 710400000 0x05040025 0x03200020 0x1 7 >, + < 806400000 0x0504002a 0x04200020 0x1 8 >, + < 883200000 0x0404002e 0x04250025 0x1 9 >, + < 960000000 0x04040032 0x05280028 0x1 10 >, + < 1036800000 0x04040036 0x052b002b 0x2 11 >, + < 1113600000 0x0404003a 0x052e002e 0x2 12 >, + < 1190400000 0x0404003e 0x06320032 0x2 13 >, + < 1248000000 0x04040041 0x06340034 0x2 14 >, + < 1324800000 0x04040045 0x06370037 0x2 15 >, + < 1401600000 0x04040049 0x073a003a 0x2 16 >, + < 1478400000 0x0404004d 0x073e003e 0x2 17 >, + < 1574400000 0x04040052 0x08420042 0x2 18 >, + < 1651200000 0x04040056 0x08450045 0x2 19 >, + < 1728000000 0x0404005a 0x08480048 0x2 20 >, + < 1804800000 0x0404005e 0x094b004b 0x3 21 >, + < 1881600000 0x04040062 0x094e004e 0x3 22 >; + + qcom,perfcl-speedbin0-v0 = + < 300000000 0x0004000f 0x01200020 0x1 1 >, + < 345600000 0x05040012 0x02200020 0x1 2 >, + < 422400000 0x05040016 0x02200020 0x1 3 >, + < 480000000 0x05040019 0x02200020 0x1 4 >, + < 556800000 0x0504001d 0x03200020 0x1 5 >, + < 633600000 0x05040021 0x03200020 0x1 6 >, + < 710400000 0x05040025 0x03200020 0x1 7 >, + < 787200000 0x05040029 0x04200020 0x1 8 >, + < 844800000 0x0404002c 0x04230023 0x1 9 >, + < 902400000 0x0404002f 0x04260026 0x1 10 >, + < 979200000 0x04040033 0x05290029 0x1 11 >, + < 1056000000 0x04040037 0x052c002c 0x1 12 >, + < 1171200000 0x0404003d 0x06310031 0x2 13 >, + < 1248000000 0x04040041 0x06340034 0x2 14 >, + < 1324800000 0x04040045 0x06370037 0x2 15 >, + < 1401600000 0x04040049 0x073a003a 0x2 16 >, + < 1478400000 0x0404004d 0x073e003e 0x2 17 >, + < 1536000000 0x04040050 0x07400040 0x2 18 >, + < 1632000000 0x04040055 0x08440044 0x2 19 >, + < 1708800000 0x04040059 0x08470047 0x2 20 >, + < 1785600000 0x0404005d 0x094a004a 0x2 21 >, + < 1862400000 0x04040061 0x094e004e 0x2 22 >, + < 1939200000 0x04040065 0x09510051 0x3 23 >, + < 2016000000 0x04040069 0x0a540054 0x3 24 >, + < 2092800000 0x0404006d 0x0a570057 0x3 25 >; + + qcom,up-timer = + <1000 1000>; + qcom,down-timer = + <1000 1000>; + qcom,pc-override-index = + <0 0>; + qcom,set-ret-inactive; + qcom,enable-llm-freq-vote; + qcom,llm-freq-up-timer = + <327675 327675>; + qcom,llm-freq-down-timer = + <327675 327675>; + qcom,enable-llm-volt-vote; + qcom,llm-volt-up-timer = + <327675 327675>; + qcom,llm-volt-down-timer = + <327675 327675>; + qcom,cc-reads = <10>; + qcom,cc-delay = <5>; + qcom,cc-factor = <100>; + qcom,osm-clk-rate = <200000000>; + qcom,xo-clk-rate = <19200000>; + + qcom,l-val-base = + <0x17916004 0x17816004>; + qcom,apcs-itm-present = + <0x179d143c 0x179d143c>; + qcom,apcs-pll-user-ctl = + <0x1791600c 0x1781600c>; + qcom,apcs-cfg-rcgr = + <0x17911054 0x17811054>; + qcom,apcs-cmd-rcgr = + <0x17911050 0x17811050>; + qcom,apm-mode-ctl = + <0x179d0004 0x179d0010>; + qcom,apm-ctrl-status = + <0x179d000c 0x179d0018>; + qcom,llm-sw-overr= + <0x8fff0036 0x8fff003a 0x0fff0036>, + <0x8fff003d 0x8fff0041 0x0fff003d>; + + qcom,apm-threshold-voltage = <832000>; + qcom,boost-fsm-en; + qcom,safe-fsm-en; + qcom,ps-fsm-en; + qcom,droop-fsm-en; + qcom,wfx-fsm-en; + qcom,pc-fsm-en; + + qcom,pwrcl-apcs-mem-acc-cfg = + <0x179d1360 0x179d1364 0x179d1364>; + qcom,perfcl-apcs-mem-acc-cfg = + <0x179d1368 0x179d136C 0x179d1370>; + qcom,pwrcl-apcs-mem-acc-val = + <0x00000000 0x80000000 0x80000000>, + <0x00000000 0x00000000 0x00000000>, + <0x00000000 0x00000001 0x00000001>; + qcom,perfcl-apcs-mem-acc-val = + <0x00000000 0x00000000 0x80000000>, + <0x00000000 0x00000000 0x00000000>, + <0x00000000 0x00000000 0x00000001>; + + clock-names = "aux_clk", "xo_ao"; + clocks = <&clock_gcc clk_hmss_gpll0_clk_src>, + <&clock_gcc clk_cxo_clk_src_ao>; + #clock-cells = <1>; + }; + + clock_debug: qcom,debugcc@162000 { + compatible = "qcom,cc-debug-8998"; + reg = <0x162000 0x4>; + reg-names = "cc_base"; + clock-names = "debug_gpu_clk", "debug_gfx_clk", + "debug_mmss_clk", "debug_cpu_clk"; + clocks = <&clock_gpu clk_gpucc_gcc_dbg_clk>, + <&clock_gfx clk_gfxcc_dbg_clk>, + <&clock_mmss clk_mmss_debug_mux>, + <&clock_cpu clk_cpu_debug_mux>; + #clock-cells = <1>; + }; + + qcom,rmtfs_sharedmem@0 { + compatible = "qcom,sharedmem-uio"; + reg = <0x0 0x00200000>; + reg-names = "rmtfs"; + qcom,client-id = <0x00000001>; + }; + + qcom,msm_gsi { + compatible = "qcom,msm_gsi"; + }; + + qcom,rmnet-ipa { + compatible = "qcom,rmnet-ipa3"; + qcom,rmnet-ipa-ssr; + qcom,ipa-loaduC; + qcom,ipa-advertise-sg-support; + }; + + ipa_hw: qcom,ipa@01e00000 { + compatible = "qcom,ipa"; + reg = <0x01e00000 0x34000>, + <0x01e84000 0x31fff>, + <0x01e04000 0x2c000>; + reg-names = "ipa-base", "bam-base", "gsi-base"; + interrupts = + <0 333 0>, + <0 432 0>, + <0 432 0>; + interrupt-names = "ipa-irq", "bam-irq", "gsi-irq"; + qcom,ipa-hw-ver = <11>; /* IPA core version = IPAv3.1 */ + qcom,ipa-hw-mode = <0>; /* IPA hw type = Normal */ + qcom,ee = <0>; + qcom,use-gsi; + qcom,use-ipa-tethering-bridge; + qcom,modem-cfg-emb-pipe-flt; + qcom,do-not-use-ch-gsi-20; + qcom,ipa-wdi2; + qcom,use-64-bit-dma-mask; + clocks = <&clock_gcc clk_ipa_clk>; + clock-names = "core_clk"; + qcom,arm-smmu; + qcom,smmu-disable-htw; + qcom,smmu-s1-bypass; + qcom,msm-bus,name = "ipa"; + qcom,msm-bus,num-cases = <4>; + qcom,msm-bus,num-paths = <4>; + qcom,msm-bus,vectors-KBps = + /* No vote */ + <90 512 0 0>, + <90 585 0 0>, + <1 676 0 0>, + /* SMMU smmu_aggre2_noc_clk */ + <81 10065 0 0>, + /* SVS */ + <90 512 80000 640000>, + <90 585 80000 640000>, + <1 676 80000 80000>, + /* SMMU smmu_aggre2_noc_clk */ + <81 10065 0 16000>, + /* NOMINAL */ + <90 512 206000 960000>, + <90 585 206000 960000>, + <1 676 206000 160000>, + /* SMMU smmu_aggre2_noc_clk */ + <81 10065 0 16000>, + /* TURBO */ + <90 512 206000 3600000>, + <90 585 206000 3600000>, + <1 676 206000 300000>, + /* SMMU smmu_aggre2_noc_clk */ + <81 10065 0 16000>; + qcom,bus-vector-names = "MIN", "SVS", "NOMINAL", "TURBO"; + + /* IPA RAM mmap */ + qcom,ipa-ram-mmap = < + 0x280 /* ofst_start; */ + 0x0 /* nat_ofst; */ + 0x0 /* nat_size; */ + 0x288 /* v4_flt_hash_ofst; */ + 0x78 /* v4_flt_hash_size; */ + 0x4000 /* v4_flt_hash_size_ddr; */ + 0x308 /* v4_flt_nhash_ofst; */ + 0x78 /* v4_flt_nhash_size; */ + 0x4000 /* v4_flt_nhash_size_ddr; */ + 0x388 /* v6_flt_hash_ofst; */ + 0x78 /* v6_flt_hash_size; */ + 0x4000 /* v6_flt_hash_size_ddr; */ + 0x408 /* v6_flt_nhash_ofst; */ + 0x78 /* v6_flt_nhash_size; */ + 0x4000 /* v6_flt_nhash_size_ddr; */ + 0xf /* v4_rt_num_index; */ + 0x0 /* v4_modem_rt_index_lo; */ + 0x7 /* v4_modem_rt_index_hi; */ + 0x8 /* v4_apps_rt_index_lo; */ + 0xe /* v4_apps_rt_index_hi; */ + 0x488 /* v4_rt_hash_ofst; */ + 0x78 /* v4_rt_hash_size; */ + 0x4000 /* v4_rt_hash_size_ddr; */ + 0x508 /* v4_rt_nhash_ofst; */ + 0x78 /* v4_rt_nhash_size; */ + 0x4000 /* v4_rt_nhash_size_ddr; */ + 0xf /* v6_rt_num_index; */ + 0x0 /* v6_modem_rt_index_lo; */ + 0x7 /* v6_modem_rt_index_hi; */ + 0x8 /* v6_apps_rt_index_lo; */ + 0xe /* v6_apps_rt_index_hi; */ + 0x588 /* v6_rt_hash_ofst; */ + 0x78 /* v6_rt_hash_size; */ + 0x4000 /* v6_rt_hash_size_ddr; */ + 0x608 /* v6_rt_nhash_ofst; */ + 0x78 /* v6_rt_nhash_size; */ + 0x4000 /* v6_rt_nhash_size_ddr; */ + 0x688 /* modem_hdr_ofst; */ + 0x140 /* modem_hdr_size; */ + 0x7c8 /* apps_hdr_ofst; */ + 0x0 /* apps_hdr_size; */ + 0x800 /* apps_hdr_size_ddr; */ + 0x7d0 /* modem_hdr_proc_ctx_ofst; */ + 0x200 /* modem_hdr_proc_ctx_size; */ + 0x9d0 /* apps_hdr_proc_ctx_ofst; */ + 0x200 /* apps_hdr_proc_ctx_size; */ + 0x0 /* apps_hdr_proc_ctx_size_ddr; */ + 0x0 /* modem_comp_decomp_ofst; diff */ + 0x0 /* modem_comp_decomp_size; diff */ + 0xbd8 /* modem_ofst; */ + 0x1424 /* modem_size; */ + 0x1ffc /* apps_v4_flt_hash_ofst; */ + 0x0 /* apps_v4_flt_hash_size; */ + 0x1ffc /* apps_v4_flt_nhash_ofst; */ + 0x0 /* apps_v4_flt_nhash_size; */ + 0x1ffc /* apps_v6_flt_hash_ofst; */ + 0x0 /* apps_v6_flt_hash_size; */ + 0x1ffc /* apps_v6_flt_nhash_ofst; */ + 0x0 /* apps_v6_flt_nhash_size; */ + 0x80 /* uc_info_ofst; */ + 0x200 /* uc_info_size; */ + 0x2000 /* end_ofst; */ + 0x1ffc /* apps_v4_rt_hash_ofst; */ + 0x0 /* apps_v4_rt_hash_size; */ + 0x1ffc /* apps_v4_rt_nhash_ofst; */ + 0x0 /* apps_v4_rt_nhash_size; */ + 0x1ffc /* apps_v6_rt_hash_ofst; */ + 0x0 /* apps_v6_rt_hash_size; */ + 0x1ffc /* apps_v6_rt_nhash_ofst; */ + 0x0 /* apps_v6_rt_nhash_size; */ + >; + + /* smp2p gpio information */ + qcom,smp2pgpio_map_ipa_1_out { + compatible = "qcom,smp2pgpio-map-ipa-1-out"; + gpios = <&smp2pgpio_ipa_1_out 0 0>; + }; + + qcom,smp2pgpio_map_ipa_1_in { + compatible = "qcom,smp2pgpio-map-ipa-1-in"; + gpios = <&smp2pgpio_ipa_1_in 0 0>; + }; + + ipa_smmu_ap: ipa_smmu_ap { + compatible = "qcom,ipa-smmu-ap-cb"; + iommus = <&anoc2_smmu 0x18e0>; + qcom,iova-mapping = <0x10000000 0x40000000>; + }; + + ipa_smmu_wlan: ipa_smmu_wlan { + compatible = "qcom,ipa-smmu-wlan-cb"; + iommus = <&anoc2_smmu 0x18e1>; + }; + + ipa_smmu_uc: ipa_smmu_uc { + compatible = "qcom,ipa-smmu-uc-cb"; + iommus = <&anoc2_smmu 0x18e2>; + qcom,iova-mapping = <0x40000000 0x20000000>; + }; + }; + + qcom,ipa_fws@1e08000 { + compatible = "qcom,pil-tz-generic"; + qcom,pas-id = <0xF>; + qcom,firmware-name = "ipa_fws"; + }; + + qcom,chd_silver { + compatible = "qcom,core-hang-detect"; + label = "silver"; + qcom,threshold-arr = <0x179880b0 0x179980b0 + 0x179a80b0 0x179b80b0>; + qcom,config-arr = <0x179880b8 0x179980b8 + 0x179a80b8 0x179b80b8>; + }; + + qcom,chd_gold { + compatible = "qcom,core-hang-detect"; + label = "gold"; + qcom,threshold-arr = <0x178880b0 0x178980b0 + 0x178a80b0 0x178b80b0>; + qcom,config-arr = <0x178880b8 0x178980b8 + 0x178a80b8 0x178b80b8>; + }; + + qcom,ipc-spinlock@1f40000 { + compatible = "qcom,ipc-spinlock-sfpb"; + reg = <0x1f40000 0x8000>; + qcom,num-locks = <8>; + }; + + qcom,ghd { + compatible = "qcom,gladiator-hang-detect"; + qcom,threshold-arr = <0x179d141c 0x179d1420 + 0x179d1424 0x179d1428 0x179d142c 0x179d1430>; + qcom,config-reg = <0x179d1434>; + }; + + qcom,msm-gladiator-v2@17900000 { + compatible = "qcom,msm-gladiator-v2"; + reg = <0x17900000 0xe000>; + reg-names = "gladiator_base"; + interrupts = <0 22 0>; + clock-names = "atb_clk"; + clocks = <&clock_gcc clk_qdss_clk>; + }; + + qcom,smem@86000000 { + compatible = "qcom,smem"; + reg = <0x86000000 0x200000>, + <0x17911008 0x4>, + <0x778000 0x7000>, + <0x1fd4000 0x8>; + reg-names = "smem", "irq-reg-base", "aux-mem1", + "smem_targ_info_reg"; + qcom,mpu-enabled; + }; + + qcom,msm-adsprpc-mem { + compatible = "qcom,msm-adsprpc-mem-region"; + memory-region = <&adsp_mem>; + }; + + qcom,msm_fastrpc { + compatible = "qcom,msm-fastrpc-adsp"; + qcom,fastrpc-glink; + + qcom,msm_fastrpc_cpz_cb1 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "adsprpc-smd"; + iommus = <&lpass_q6_smmu 2>; + qcom,secure-context-bank; + dma-coherent; + }; + qcom,msm_fastrpc_compute_cb1 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "adsprpc-smd"; + iommus = <&lpass_q6_smmu 8>; + dma-coherent; + }; + qcom,msm_fastrpc_compute_cb2 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "adsprpc-smd"; + iommus = <&lpass_q6_smmu 9>; + dma-coherent; + }; + qcom,msm_fastrpc_compute_cb3 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "adsprpc-smd"; + iommus = <&lpass_q6_smmu 10>; + dma-coherent; + }; + qcom,msm_fastrpc_compute_cb4 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "adsprpc-smd"; + iommus = <&lpass_q6_smmu 11>; + dma-coherent; + }; + qcom,msm_fastrpc_compute_cb6 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "adsprpc-smd"; + iommus = <&lpass_q6_smmu 5>; + dma-coherent; + }; + qcom,msm_fastrpc_compute_cb7 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "adsprpc-smd"; + iommus = <&lpass_q6_smmu 6>; + dma-coherent; + }; + qcom,msm_fastrpc_compute_cb8 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "adsprpc-smd"; + iommus = <&lpass_q6_smmu 7>; + dma-coherent; + }; + }; + + rpm_bus: qcom,rpm-smd { + compatible = "qcom,rpm-glink"; + qcom,glink-edge = "rpm"; + rpm-channel-name = "rpm_requests"; + }; + + glink_mpss: qcom,glink-ssr-modem { + compatible = "qcom,glink_ssr"; + label = "modem"; + qcom,edge = "mpss"; + qcom,notify-edges = <&glink_lpass>, <&glink_dsps>, <&glink_rpm>; + qcom,xprt = "smem"; + }; + + glink_lpass: qcom,glink-ssr-adsp { + compatible = "qcom,glink_ssr"; + label = "adsp"; + qcom,edge = "lpass"; + qcom,notify-edges = <&glink_mpss>, <&glink_dsps>, <&glink_rpm>; + qcom,xprt = "smem"; + }; + + glink_dsps: qcom,glink-ssr-dsps { + compatible = "qcom,glink_ssr"; + label = "slpi"; + qcom,edge = "dsps"; + qcom,notify-edges = <&glink_mpss>, <&glink_lpass>, <&glink_rpm>; + qcom,xprt = "smem"; + }; + + glink_rpm: qcom,glink-ssr-rpm { + compatible = "qcom,glink_ssr"; + label = "rpm"; + qcom,edge = "rpm"; + qcom,notify-edges = <&glink_lpass>, <&glink_mpss>, + <&glink_dsps>, <&glink_spss>; + qcom,xprt = "smem"; + }; + + glink_spss: qcom,glink-ssr-spss { + compatible = "qcom,glink_ssr"; + label = "spss"; + qcom,edge = "spss"; + qcom,notify-edges = <&glink_mpss>, <&glink_lpass>, + <&glink_dsps>, <&glink_rpm>; + qcom,xprt = "mailbox"; + }; + + qcom,glink-smem-native-xprt-modem@86000000 { + compatible = "qcom,glink-smem-native-xprt"; + reg = <0x86000000 0x200000>, + <0x17911008 0x4>; + reg-names = "smem", "irq-reg-base"; + qcom,irq-mask = <0x8000>; + interrupts = <0 452 1>; + label = "mpss"; + }; + + qcom,glink-smem-native-xprt-adsp@86000000 { + compatible = "qcom,glink-smem-native-xprt"; + reg = <0x86000000 0x200000>, + <0x17911008 0x4>; + reg-names = "smem", "irq-reg-base"; + qcom,irq-mask = <0x200>; + interrupts = <0 157 1>; + label = "lpass"; + qcom,qos-config = <&glink_qos_adsp>; + qcom,ramp-time = <0xaf>; + }; + + glink_qos_adsp: qcom,glink-qos-config-adsp { + compatible = "qcom,glink-qos-config"; + qcom,flow-info = <0x3c 0x0>, + <0x3c 0x0>, + <0x3c 0x0>, + <0x3c 0x0>; + qcom,mtu-size = <0x800>; + qcom,tput-stats-cycle = <0xa>; + }; + + qcom,glink-smem-native-xprt-dsps@86000000 { + compatible = "qcom,glink-smem-native-xprt"; + reg = <0x86000000 0x200000>, + <0x17911008 0x4>; + reg-names = "smem", "irq-reg-base"; + qcom,irq-mask = <0x8000000>; + interrupts = <0 179 1>; + label = "dsps"; + }; + + qcom,glink-smem-native-xprt-rpm@778000 { + compatible = "qcom,glink-rpm-native-xprt"; + reg = <0x778000 0x7000>, + <0x17911008 0x4>; + reg-names = "msgram", "irq-reg-base"; + qcom,irq-mask = <0x1>; + interrupts = <0 168 1>; + label = "rpm"; + }; + + qcom,glink-mailbox-xprt-spss@1d05008 { + compatible = "qcom,glink-mailbox-xprt"; + reg = <0x1d05008 0x8>, + <0x1d05010 0x4>, + <0x1d0501c 0x4>, + <0x1d06008 0x4>; + reg-names = "mbox-loc-addr", "mbox-loc-size", "irq-reg-base", + "irq-rx-reset"; + qcom,irq-mask = <0x1>; + interrupts = <0 348 4>; + label = "spss"; + qcom,tx-ring-size = <0x800>; + qcom,rx-ring-size = <0x800>; + }; + + glink_spi_xprt_wdsp: qcom,glink-spi-xprt-wdsp { + compatible = "qcom,glink-spi-xprt"; + label = "wdsp"; + qcom,remote-fifo-config = <&glink_fifo_wdsp>; + qcom,qos-config = <&glink_qos_wdsp>; + qcom,ramp-time = <0x10>, + <0x20>, + <0x30>, + <0x40>; + }; + + glink_fifo_wdsp: qcom,glink-fifo-config-wdsp { + compatible = "qcom,glink-fifo-config"; + qcom,out-read-idx-reg = <0x12000>; + qcom,out-write-idx-reg = <0x12004>; + qcom,in-read-idx-reg = <0x1200C>; + qcom,in-write-idx-reg = <0x12010>; + }; + + glink_qos_wdsp: qcom,glink-qos-config-wdsp { + compatible = "qcom,glink-qos-config"; + qcom,flow-info = <0x80 0x0>, + <0x70 0x1>, + <0x60 0x2>, + <0x50 0x3>; + qcom,mtu-size = <0x800>; + qcom,tput-stats-cycle = <0xa>; + }; + + qcom,glink_pkt { + compatible = "qcom,glinkpkt"; + + qcom,glinkpkt-at-mdm0 { + qcom,glinkpkt-transport = "smem"; + qcom,glinkpkt-edge = "mpss"; + qcom,glinkpkt-ch-name = "DS"; + qcom,glinkpkt-dev-name = "at_mdm0"; + }; + + qcom,glinkpkt-loopback_cntl { + qcom,glinkpkt-transport = "lloop"; + qcom,glinkpkt-edge = "local"; + qcom,glinkpkt-ch-name = "LOCAL_LOOPBACK_CLNT"; + qcom,glinkpkt-dev-name = "glink_pkt_loopback_ctrl"; + }; + + qcom,glinkpkt-loopback_data { + qcom,glinkpkt-transport = "lloop"; + qcom,glinkpkt-edge = "local"; + qcom,glinkpkt-ch-name = "glink_pkt_lloop_CLNT"; + qcom,glinkpkt-dev-name = "glink_pkt_loopback"; + }; + + qcom,glinkpkt-apr-apps2 { + qcom,glinkpkt-transport = "smem"; + qcom,glinkpkt-edge = "adsp"; + qcom,glinkpkt-ch-name = "apr_apps2"; + qcom,glinkpkt-dev-name = "apr_apps2"; + }; + + qcom,glinkpkt-data40-cntl { + qcom,glinkpkt-transport = "smem"; + qcom,glinkpkt-edge = "mpss"; + qcom,glinkpkt-ch-name = "DATA40_CNTL"; + qcom,glinkpkt-dev-name = "smdcntl8"; + }; + + qcom,glinkpkt-data1 { + qcom,glinkpkt-transport = "smem"; + qcom,glinkpkt-edge = "mpss"; + qcom,glinkpkt-ch-name = "DATA1"; + qcom,glinkpkt-dev-name = "smd7"; + }; + + qcom,glinkpkt-data4 { + qcom,glinkpkt-transport = "smem"; + qcom,glinkpkt-edge = "mpss"; + qcom,glinkpkt-ch-name = "DATA4"; + qcom,glinkpkt-dev-name = "smd8"; + }; + + qcom,glinkpkt-data11 { + qcom,glinkpkt-transport = "smem"; + qcom,glinkpkt-edge = "mpss"; + qcom,glinkpkt-ch-name = "DATA11"; + qcom,glinkpkt-dev-name = "smd11"; + }; + }; + + qcom,ipc_router { + compatible = "qcom,ipc_router"; + qcom,node-id = <1>; + }; + + qcom,ipc_router_modem_xprt { + compatible = "qcom,ipc_router_glink_xprt"; + qcom,ch-name = "IPCRTR"; + qcom,xprt-remote = "mpss"; + qcom,glink-xprt = "smem"; + qcom,xprt-linkid = <1>; + qcom,xprt-version = <1>; + qcom,fragmented-data; + }; + + qcom,ipc_router_q6_xprt { + compatible = "qcom,ipc_router_glink_xprt"; + qcom,ch-name = "IPCRTR"; + qcom,xprt-remote = "lpass"; + qcom,glink-xprt = "smem"; + qcom,xprt-linkid = <1>; + qcom,xprt-version = <1>; + qcom,fragmented-data; + }; + + qcom,ipc_router_dsps_xprt { + compatible = "qcom,ipc_router_glink_xprt"; + qcom,ch-name = "IPCRTR"; + qcom,xprt-remote = "dsps"; + qcom,glink-xprt = "smem"; + qcom,xprt-linkid = <1>; + qcom,xprt-version = <1>; + qcom,fragmented-data; + qcom,dynamic-wakeup-source; + }; + + qcom,spcom { + compatible = "qcom,spcom"; + + /* predefined channels, remote side is server */ + qcom,spcom-ch-names = "sp_kernel" , "sp_ssr"; + status = "ok"; + }; + + spss_utils: qcom,spss_utils { + compatible = "qcom,spss-utils"; + /* spss fuses physical address */ + qcom,spss-fuse1-addr = <0x007841c4>; + qcom,spss-fuse1-bit = <27>; + qcom,spss-fuse2-addr = <0x0078413c>; + qcom,spss-fuse2-bit = <31>; + qcom,spss-test-firmware-name = "spss"; /* default name */ + qcom,spss-prod-firmware-name = "spss1p"; /* 8 chars max */ + qcom,spss-hybr-firmware-name = "spss1h"; /* 8 chars max */ + qcom,spss-debug-reg-addr = <0x01d06020>; + status = "ok"; + }; + + sdhc_2: sdhci@c0a4900 { + compatible = "qcom,sdhci-msm"; + reg = <0xc0a4900 0x314>, <0xc0a4000 0x800>; + reg-names = "hc_mem", "core_mem"; + + interrupts = <0 125 0>, <0 221 0>; + interrupt-names = "hc_irq", "pwr_irq"; + + clock-names = "iface_clk", "core_clk"; + clocks = <&clock_gcc clk_gcc_sdcc2_ahb_clk>, + <&clock_gcc clk_gcc_sdcc2_apps_clk>; + + qcom,large-address-bus; + qcom,bus-width = <4>; + qcom,cpu-dma-latency-us = <701>; + + qcom,devfreq,freq-table = <52000000 200000000>; + + qcom,msm-bus,name = "sdhc2"; + qcom,msm-bus,num-cases = <8>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = <81 512 0 0>, /* No vote */ + <81 512 1600 3200>, /* 400 KB/s*/ + <81 512 80000 160000>, /* 20 MB/s */ + <81 512 100000 200000>, /* 25 MB/s */ + <81 512 200000 400000>, /* 50 MB/s */ + <81 512 400000 800000>, /* 100 MB/s */ + <81 512 800000 800000>, /* 200 MB/s */ + <81 512 2048000 4096000>; /* Max. bandwidth */ + qcom,bus-bw-vectors-bps = <0 400000 20000000 25000000 50000000 + 100000000 200000000 4294967295>; + + qcom,sdr104-wa; + + status = "disabled"; + }; + + ufsphy1: ufsphy@1da7000 { + compatible = "qcom,ufs-phy-qmp-v3"; + reg = <0x1da7000 0xda8>; + reg-names = "phy_mem"; + #phy-cells = <0>; + clock-names = "ref_clk_src", + "ref_clk", + "ref_aux_clk"; + clocks = <&clock_gcc clk_ln_bb_clk1>, + <&clock_gcc clk_gcc_ufs_clkref_clk>, + <&clock_gcc clk_gcc_ufs_phy_aux_hw_ctl_clk>; + status = "disabled"; + }; + + ufs_ice: ufsice@1db0000 { + compatible = "qcom,ice"; + reg = <0x1db0000 0x8000>; + qcom,enable-ice-clk; + clock-names = "ufs_core_clk", + "bus_clk", + "iface_clk", + "ice_core_clk"; + clocks = <&clock_gcc clk_gcc_ufs_axi_clk>, + <&clock_gcc clk_gcc_aggre1_ufs_axi_clk>, + <&clock_gcc clk_gcc_ufs_ahb_clk>, + <&clock_gcc clk_gcc_ufs_ice_core_clk>; + qcom,op-freq-hz = <0>, + <0>, + <0>, + <300000000>; + vdd-hba-supply = <&gdsc_ufs>; + qcom,msm-bus,name = "ufs_ice_noc"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <1 650 0 0>, /* No vote */ + <1 650 1000 0>; /* Max. bandwidth */ + qcom,bus-vector-names = "MIN", + "MAX"; + qcom,instance-type = "ufs"; + status = "disabled"; + }; + + ufs1: ufshc@1da4000 { + compatible = "qcom,ufshc"; + reg = <0x1da4000 0x2500>; + interrupts = <0 265 0>; + phys = <&ufsphy1>; + phy-names = "ufsphy"; + ufs-qcom-crypto = <&ufs_ice>; + + clock-names = + "core_clk", + "bus_aggr_clk", + "iface_clk", + "core_clk_unipro", + "core_clk_ice", + "ref_clk", + "tx_lane0_sync_clk", + "rx_lane0_sync_clk"; + clocks = + <&clock_gcc clk_gcc_ufs_axi_hw_ctl_clk>, + <&clock_gcc clk_gcc_aggre1_ufs_axi_hw_ctl_clk>, + <&clock_gcc clk_gcc_ufs_ahb_clk>, + <&clock_gcc clk_gcc_ufs_unipro_core_hw_ctl_clk>, + <&clock_gcc clk_gcc_ufs_ice_core_hw_ctl_clk>, + <&clock_gcc clk_ln_bb_clk1>, + <&clock_gcc clk_gcc_ufs_tx_symbol_0_clk>, + <&clock_gcc clk_gcc_ufs_rx_symbol_0_clk>; + freq-table-hz = + <50000000 200000000>, + <0 0>, + <0 0>, + <37500000 150000000>, + <75000000 300000000>, + <0 0>, + <0 0>, + <0 0>; + + lanes-per-direction = <1>; + + qcom,msm-bus,name = "ufs1"; + qcom,msm-bus,num-cases = <22>; + qcom,msm-bus,num-paths = <2>; + qcom,msm-bus,vectors-KBps = + /* + * During HS G3 UFS runs at nominal voltage corner, vote + * higher bandwidth to push other buses in the data path + * to run at nominal to achieve max throughput. + * 4GBps pushes BIMC to run at nominal. + * 200MBps pushes CNOC to run at nominal. + * Vote for half of this bandwidth for HS G3 1-lane. + * For max bandwidth, vote high enough to push the buses + * to run in turbo voltage corner. + */ + <95 512 0 0>, <1 650 0 0>, /* No vote */ + <95 512 922 0>, <1 650 1000 0>, /* PWM G1 */ + <95 512 1844 0>, <1 650 1000 0>, /* PWM G2 */ + <95 512 3688 0>, <1 650 1000 0>, /* PWM G3 */ + <95 512 7376 0>, <1 650 1000 0>, /* PWM G4 */ + <95 512 1844 0>, <1 650 1000 0>, /* PWM G1 L2 */ + <95 512 3688 0>, <1 650 1000 0>, /* PWM G2 L2 */ + <95 512 7376 0>, <1 650 1000 0>, /* PWM G3 L2 */ + <95 512 14752 0>, <1 650 1000 0>, /* PWM G4 L2 */ + <95 512 127796 0>, <1 650 1000 0>, /* HS G1 RA */ + <95 512 255591 0>, <1 650 1000 0>, /* HS G2 RA */ + <95 512 2097152 0>, <1 650 102400 0>, /* HS G3 RA */ + <95 512 255591 0>, <1 650 1000 0>, /* HS G1 RA L2 */ + <95 512 511181 0>, <1 650 1000 0>, /* HS G2 RA L2 */ + <95 512 4194304 0>, <1 650 204800 0>, /* HS G3 RA L2 */ + <95 512 149422 0>, <1 650 1000 0>, /* HS G1 RB */ + <95 512 298189 0>, <1 650 1000 0>, /* HS G2 RB */ + <95 512 2097152 0>, <1 650 102400 0>, /* HS G3 RB */ + <95 512 298189 0>, <1 650 1000 0>, /* HS G1 RB L2 */ + <95 512 596378 0>, <1 650 1000 0>, /* HS G2 RB L2 */ + <95 512 4194304 0>, <1 650 204800 0>, /* HS G3 RB L2 */ + <95 512 7643136 0>, <1 650 307200 0>; /* Max. bandwidth */ + qcom,bus-vector-names = "MIN", + "PWM_G1_L1", "PWM_G2_L1", "PWM_G3_L1", "PWM_G4_L1", + "PWM_G1_L2", "PWM_G2_L2", "PWM_G3_L2", "PWM_G4_L2", + "HS_RA_G1_L1", "HS_RA_G2_L1", "HS_RA_G3_L1", + "HS_RA_G1_L2", "HS_RA_G2_L2", "HS_RA_G3_L2", + "HS_RB_G1_L1", "HS_RB_G2_L1", "HS_RB_G3_L1", + "HS_RB_G1_L2", "HS_RB_G2_L2", "HS_RB_G3_L2", + "MAX"; + + /* PM QoS */ + qcom,pm-qos-cpu-groups = <0x0F 0xF0>; + qcom,pm-qos-cpu-group-latency-us = <70 70>; + qcom,pm-qos-default-cpu = <0>; + + pinctrl-names = "dev-reset-assert", "dev-reset-deassert"; + pinctrl-0 = <&ufs_dev_reset_assert>; + pinctrl-1 = <&ufs_dev_reset_deassert>; + + resets = <&clock_gcc UFS_BCR>; + reset-names = "core_reset"; + + status = "disabled"; + }; + + usb3: ssusb@a800000 { + compatible = "qcom,dwc-usb3-msm"; + reg = <0x0a800000 0xf8c00>, + <0x0c016000 0x400>; + reg-names = "core_base", "ahb2phy_base"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + interrupts = <0 347 0>, <0 243 0>, <0 180 0>; + interrupt-names = "hs_phy_irq", "ss_phy_irq", "pwr_event_irq"; + + USB3_GDSC-supply = <&gdsc_usb30>; + qcom,usb-dbm = <&dbm_1p5>; + qcom,msm-bus,name = "usb3"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <61 512 0 0>, + <61 512 240000 800000>; + + qcom,dwc-usb3-msm-tx-fifo-size = <21288>; + extcon = <&pmi8998_pdphy>; + + clocks = <&clock_gcc clk_gcc_usb30_master_clk>, + <&clock_gcc clk_gcc_cfg_noc_usb3_axi_clk>, + <&clock_gcc clk_gcc_aggre1_usb3_axi_clk>, + <&clock_gcc clk_gcc_usb30_mock_utmi_clk>, + <&clock_gcc clk_gcc_usb30_sleep_clk>, + <&clock_gcc clk_cxo_dwc3_clk>; + + clock-names = "core_clk", "iface_clk", "bus_aggr_clk", + "utmi_clk", "sleep_clk", "xo"; + + qcom,core-clk-rate = <120000000>; + qcom,core-clk-rate-hs = <60000000>; + + resets = <&clock_gcc USB_30_BCR>; + reset-names = "core_reset"; + + dwc3@a800000 { + compatible = "snps,dwc3"; + reg = <0x0a800000 0xcd00>; + interrupt-parent = <&intc>; + interrupts = <0 131 0>; + usb-phy = <&qusb_phy0>, <&ssphy>; + tx-fifo-resize; + snps,nominal-elastic-buffer; + snps,disable-clk-gating; + snps,has-lpm-erratum; + snps,hird-threshold = /bits/ 8 <0x10>; + snps,num-gsi-evt-buffs = <0x3>; + }; + + qcom,usbbam@a904000 { + compatible = "qcom,usb-bam-msm"; + reg = <0xa904000 0x17000>; + interrupt-parent = <&intc>; + interrupts = <0 132 0>; + + qcom,bam-type = <0>; + qcom,usb-bam-fifo-baseaddr = <0x146bb000>; + qcom,usb-bam-num-pipes = <8>; + qcom,ignore-core-reset-ack; + qcom,disable-clk-gating; + qcom,usb-bam-override-threshold = <0x4001>; + qcom,usb-bam-max-mbps-highspeed = <400>; + qcom,usb-bam-max-mbps-superspeed = <3600>; + qcom,reset-bam-on-connect; + + qcom,pipe0 { + label = "ssusb-qdss-in-0"; + qcom,usb-bam-mem-type = <2>; + qcom,dir = <1>; + qcom,pipe-num = <0>; + qcom,peer-bam = <0>; + qcom,peer-bam-physical-address = <0x6064000>; + qcom,src-bam-pipe-index = <0>; + qcom,dst-bam-pipe-index = <0>; + qcom,data-fifo-offset = <0x0>; + qcom,data-fifo-size = <0x1800>; + qcom,descriptor-fifo-offset = <0x1800>; + qcom,descriptor-fifo-size = <0x800>; + }; + }; + }; + + qusb_phy0: qusb@c012000 { + compatible = "qcom,qusb2phy-v2"; + reg = <0x0c012000 0x2a8>, + <0x01fcb24c 0x4>; + reg-names = "qusb_phy_base", + "tcsr_clamp_dig_n_1p8"; + vdd-supply = <&pm8998_l1>; + vdda12-supply = <&pm8998_l2>; + vdda18-supply = <&pm8998_l12>; + vdda33-supply = <&pm8998_l24>; + qcom,vdd-voltage-level = <0 880000 880000>; + qcom,vdda33-voltage-level = <2400000 3088000 3088000>; + qcom,qusb-phy-init-seq = + /* */ + <0x80 0x0 + 0x13 0x04 + 0x7c 0x18c + 0x80 0x2c + 0x0a 0x184 + 0x00 0x240>; + phy_type= "utmi"; + + clocks = <&clock_gcc clk_ln_bb_clk1>, + <&clock_gcc clk_gcc_rx1_usb2_clkref_clk>; + clock-names = "ref_clk_src", "ref_clk"; + + resets = <&clock_gcc QUSB2PHY_PRIM_BCR>; + reset-names = "phy_reset"; + }; + + ssphy: ssphy@c010000 { + compatible = "qcom,usb-ssphy-qmp-v2"; + reg = <0x0c010000 0xe0c>, + <0x01fcb244 0x4>, + <0x01fcb248 0x4>; + reg-names = "qmp_phy_base", + "vls_clamp_reg", + "tcsr_usb3_dp_phymode"; + vdd-supply = <&pm8998_l1>; + core-supply = <&pm8998_l2>; + qcom,vdd-voltage-level = <0 880000 880000>; + qcom,vbus-valid-override; + qcom,qmp-phy-init-seq = + /* */ + <0x138 0x30 0x00 + 0x034 0x04 0x01 + 0x080 0x14 0x00 + 0x03c 0x06 0x00 + 0x08c 0x08 0x00 + 0x15c 0x06 0x00 + 0x164 0x01 0x00 + 0x13c 0x80 0x00 + 0x0b0 0x82 0x00 + 0x0b8 0xab 0x00 + 0x0bc 0xea 0x00 + 0x0c0 0x02 0x00 + 0x060 0x06 0x00 + 0x068 0x16 0x00 + 0x070 0x36 0x00 + 0x0dc 0x00 0x00 + 0x0d8 0x3f 0x00 + 0x0f8 0x01 0x00 + 0x0f4 0xc9 0x00 + 0x148 0x0a 0x00 + 0x0a0 0x00 0x00 + 0x09c 0x34 0x00 + 0x098 0x15 0x00 + 0x090 0x04 0x00 + 0x154 0x00 0x00 + 0x094 0x00 0x00 + 0x0f0 0x00 0x00 + 0x00c 0x0a 0x00 + 0x048 0x07 0x00 + 0x0d0 0x80 0x00 + 0x184 0x01 0x00 + 0x010 0x01 0x00 + 0x01c 0x31 0x00 + 0x020 0x01 0x00 + 0x014 0x00 0x00 + 0x018 0x00 0x00 + 0x024 0x85 0x00 + 0x028 0x07 0x00 + 0x430 0x0b 0x00 + 0x4d4 0x0f 0x00 + 0x4d8 0x4e 0x00 + 0x4dc 0x18 0x00 + 0x4f8 0x07 0x00 + 0x4fc 0x80 0x00 + 0x504 0x43 0x00 + 0x50c 0x1c 0x00 + 0x434 0x75 0x00 + 0x43c 0x00 0x00 + 0x440 0x00 0x00 + 0x444 0x80 0x00 + 0x408 0x0a 0x00 + 0x414 0x06 0x00 + 0x500 0x00 0x00 + 0x4c0 0x03 0x00 + 0x564 0x05 0x00 + 0x830 0x0b 0x00 + 0x8d4 0x0f 0x00 + 0x8d8 0x4e 0x00 + 0x8dc 0x18 0x00 + 0x8f8 0x07 0x00 + 0x8fc 0x80 0x00 + 0x904 0x43 0x00 + 0x90c 0x1c 0x00 + 0x834 0x75 0x00 + 0x83c 0x00 0x00 + 0x840 0x00 0x00 + 0x844 0x80 0x00 + 0x808 0x0a 0x00 + 0x814 0x06 0x00 + 0x900 0x00 0x00 + 0x8c0 0x03 0x00 + 0x964 0x05 0x00 + 0x260 0x10 0x00 + 0x2a4 0x12 0x00 + 0x28c 0x16 0x00 + 0x244 0x00 0x00 + 0x660 0x10 0x00 + 0x6a4 0x12 0x00 + 0x68c 0x16 0x00 + 0x644 0x00 0x00 + 0xcc8 0x83 0x00 + 0xccc 0x09 0x00 + 0xcd0 0xa2 0x00 + 0xcd4 0x40 0x00 + 0xcc4 0x02 0x00 + 0xc80 0xd1 0x00 + 0xc84 0x1f 0x00 + 0xc88 0x47 0x00 + 0xc64 0x1b 0x00 + 0xc0c 0x9f 0x00 + 0xc10 0x9f 0x00 + 0xc14 0xb7 0x00 + 0xc18 0x4e 0x00 + 0xc1c 0x65 0x00 + 0xc20 0x6b 0x00 + 0xc24 0x15 0x00 + 0xc28 0x0d 0x00 + 0xc2c 0x15 0x00 + 0xc30 0x0d 0x00 + 0xc34 0x15 0x00 + 0xc38 0x0d 0x00 + 0xc3c 0x15 0x00 + 0xc40 0x0d 0x00 + 0xc44 0x15 0x00 + 0xc48 0x0d 0x00 + 0xc4c 0x15 0x00 + 0xc50 0x0d 0x00 + 0xc5c 0x02 0x00 + 0xca0 0x04 0x00 + 0xc8c 0x44 0x00 + 0xc70 0xe7 0x00 + 0xc74 0x03 0x00 + 0xc78 0x40 0x00 + 0xc7c 0x00 0x00 + 0xdd8 0x8a 0x00 + 0xcb8 0x75 0x00 + 0xcb0 0x86 0x00 + 0xcbc 0x13 0x00 + 0xffffffff 0xffffffff 0x00>; + + qcom,qmp-phy-reg-offset = + <0xd74 /* USB3_PHY_PCS_STATUS */ + 0xcd8 /* USB3_PHY_AUTONOMOUS_MODE_CTRL */ + 0xcdc /* USB3_PHY_LFPS_RXTERM_IRQ_CLEAR */ + 0xc04 /* USB3_PHY_POWER_DOWN_CONTROL */ + 0xc00 /* USB3_PHY_SW_RESET */ + 0xc08 /* USB3_PHY_START */ + 0xa00>; /* USB3PHY_PCS_MISC_TYPEC_CTRL */ + + clocks = <&clock_gcc clk_gcc_usb3_phy_aux_clk>, + <&clock_gcc clk_gcc_usb3_phy_pipe_clk>, + <&clock_gcc clk_ln_bb_clk1>, + <&clock_gcc clk_gcc_usb3_clkref_clk>; + + clock-names = "aux_clk", "pipe_clk", "ref_clk_src", + "ref_clk"; + + resets = <&clock_gcc USB3_PHY_BCR>, + <&clock_gcc USB3PHY_PHY_BCR>; + reset-names = "phy_reset", "phy_phy_reset"; + }; + + usb_audio_qmi_dev { + compatible = "qcom,usb-audio-qmi-dev"; + iommus = <&lpass_q6_smmu 12>; + qcom,usb-audio-stream-id = <12>; + qcom,usb-audio-intr-num = <2>; + }; + + dbm_1p5: dbm@a8f8000 { + compatible = "qcom,usb-dbm-1p5"; + reg = <0xa8f8000 0x300>; + qcom,reset-ep-after-lpm-resume; + }; + + usb_nop_phy: usb_nop_phy { + compatible = "usb-nop-xceiv"; + }; + + qcom,lpass@17300000 { + compatible = "qcom,pil-tz-generic"; + reg = <0x17300000 0x00100>; + interrupts = <0 162 1>; + + vdd_cx-supply = <&pm8998_s1_level>; + qcom,proxy-reg-names = "vdd_cx"; + qcom,vdd_cx-uV-uA = ; + + clocks = <&clock_gcc clk_cxo_pil_lpass_clk>; + clock-names = "xo"; + qcom,proxy-clock-names = "xo"; + + qcom,pas-id = <1>; + qcom,proxy-timeout-ms = <10000>; + qcom,smem-id = <423>; + qcom,sysmon-id = <1>; + status = "ok"; + qcom,ssctl-instance-id = <0x14>; + qcom,firmware-name = "adsp"; + memory-region = <&pil_adsp_mem>; + + /* GPIO inputs from lpass */ + qcom,gpio-err-fatal = <&smp2pgpio_ssr_smp2p_2_in 0 0>; + qcom,gpio-proxy-unvote = <&smp2pgpio_ssr_smp2p_2_in 2 0>; + qcom,gpio-err-ready = <&smp2pgpio_ssr_smp2p_2_in 1 0>; + qcom,gpio-stop-ack = <&smp2pgpio_ssr_smp2p_2_in 3 0>; + + /* GPIO output to lpass */ + qcom,gpio-force-stop = <&smp2pgpio_ssr_smp2p_2_out 0 0>; + }; + + qcom,memshare { + compatible = "qcom,memshare"; + + qcom,client_1 { + compatible = "qcom,memshare-peripheral"; + qcom,peripheral-size = <0x200000>; + qcom,client-id = <0>; + qcom,allocate-boot-time; + label = "modem"; + }; + + qcom,client_2 { + compatible = "qcom,memshare-peripheral"; + qcom,peripheral-size = <0x300000>; + qcom,client-id = <2>; + label = "modem"; + }; + + mem_client_3_size: qcom,client_3 { + compatible = "qcom,memshare-peripheral"; + qcom,peripheral-size = <0x0>; + qcom,client-id = <1>; + qcom,allocate-boot-time; + label = "modem"; + }; + }; + + pil_modem: qcom,mss@4080000 { + compatible = "qcom,pil-q6v55-mss"; + reg = <0x4080000 0x100>, + <0x1f63000 0x008>, + <0x1f65000 0x008>, + <0x1f64000 0x008>, + <0x4180000 0x020>, + <0x00179000 0x004>; + reg-names = "qdsp6_base", "halt_q6", "halt_modem", + "halt_nc", "rmb_base", "restart_reg"; + + clocks = <&clock_gcc clk_cxo_clk_src>, + <&clock_gcc clk_gcc_mss_cfg_ahb_clk>, + <&clock_gcc clk_gcc_bimc_mss_q6_axi_clk>, + <&clock_gcc clk_gcc_boot_rom_ahb_clk>, + <&clock_gcc clk_gpll0_out_msscc>, + <&clock_gcc clk_gcc_mss_snoc_axi_clk>, + <&clock_gcc clk_gcc_mss_mnoc_bimc_axi_clk>, + <&clock_gcc clk_qdss_clk>; + clock-names = "xo", "iface_clk", "bus_clk", + "mem_clk", "gpll0_mss_clk", "snoc_axi_clk", + "mnoc_axi_clk", "qdss_clk"; + qcom,proxy-clock-names = "xo", "qdss_clk", "mem_clk"; + qcom,active-clock-names = "iface_clk", "bus_clk", + "gpll0_mss_clk", "snoc_axi_clk", "mnoc_axi_clk"; + + interrupts = <0 448 1>; + vdd_cx-supply = <&pm8998_s1_level>; + vdd_cx-voltage = ; + vdd_mx-supply = <&pm8998_s9_level>; + vdd_mx-uV = ; + qcom,firmware-name = "modem"; + qcom,pil-self-auth; + qcom,sysmon-id = <0>; + qcom,ssctl-instance-id = <0x12>; + qcom,qdsp6v62-1-2; + status = "ok"; + memory-region = <&modem_mem>; + qcom,mem-protect-id = <0xF>; + + /* GPIO inputs from mss */ + qcom,gpio-err-fatal = <&smp2pgpio_ssr_smp2p_1_in 0 0>; + qcom,gpio-err-ready = <&smp2pgpio_ssr_smp2p_1_in 1 0>; + qcom,gpio-proxy-unvote = <&smp2pgpio_ssr_smp2p_1_in 2 0>; + qcom,gpio-stop-ack = <&smp2pgpio_ssr_smp2p_1_in 3 0>; + qcom,gpio-shutdown-ack = <&smp2pgpio_ssr_smp2p_1_in 7 0>; + + /* GPIO output to mss */ + qcom,gpio-force-stop = <&smp2pgpio_ssr_smp2p_1_out 0 0>; + qcom,mba-mem@0 { + compatible = "qcom,pil-mba-mem"; + memory-region = <&pil_mba_mem>; + }; + }; + + tsens0: tsens@10aa000 { + compatible = "qcom,msm8998-tsens"; + reg = <0x10aa000 0x2000>; + reg-names = "tsens_physical"; + interrupts = <0 458 0>, <0 445 0>; + interrupt-names = "tsens-upper-lower", "tsens-critical"; + qcom,client-id = <0 1 2 3 4 7 8 9 10 11 12 13>; + qcom,sensor-id = <0 1 2 3 4 7 8 9 10 11 12 13>; + qcom,sensors = <12>; + }; + + tsens1: tsens@10ad000 { + compatible = "qcom,msm8998-tsens"; + reg = <0x10ad000 0x2000>; + reg-names = "tsens_physical"; + interrupts = <0 184 0>, <0 430 0>; + interrupt-names = "tsens-upper-lower", "tsens-critical"; + qcom,client-id = <14 15 16 17 18 19 20 21>; + qcom,sensor-id = <0 1 3 4 5 6 7 2>; + qcom,sensors = <8>; + }; + + qcom,qbt1000 { + compatible = "qcom,qbt1000"; + clock-names = "core", "iface"; + clocks = <&clock_gcc clk_gcc_blsp2_qup6_spi_apps_clk>, + <&clock_gcc clk_gcc_blsp2_ahb_clk>; + clock-frequency = <15000000>; + qcom,ipc-gpio = <&tlmm 121 0>; + qcom,finger-detect-gpio = <&pm8998_gpios 2 0>; + }; + + qcom,sensor-information { + compatible = "qcom,sensor-information"; + sensor_information0: qcom,sensor-information-0 { + qcom,sensor-type = "tsens"; + qcom,sensor-name = "tsens_tz_sensor0"; + qcom,scaling-factor = <10>; + }; + sensor_information1: qcom,sensor-information-1 { + qcom,sensor-type = "tsens"; + qcom,sensor-name = "tsens_tz_sensor1"; + qcom,scaling-factor = <10>; + }; + sensor_information2: qcom,sensor-information-2 { + qcom,sensor-type = "tsens"; + qcom,sensor-name = "tsens_tz_sensor2"; + qcom,scaling-factor = <10>; + }; + sensor_information3: qcom,sensor-information-3 { + qcom,sensor-type = "tsens"; + qcom,sensor-name = "tsens_tz_sensor3"; + qcom,scaling-factor = <10>; + }; + sensor_information4: qcom,sensor-information-4 { + qcom,sensor-type = "tsens"; + qcom,sensor-name = "tsens_tz_sensor4"; + qcom,scaling-factor = <10>; + }; + sensor_information7: qcom,sensor-information-7 { + qcom,sensor-type = "tsens"; + qcom,sensor-name = "tsens_tz_sensor7"; + qcom,scaling-factor = <10>; + }; + sensor_information8: qcom,sensor-information-8 { + qcom,sensor-type = "tsens"; + qcom,sensor-name = "tsens_tz_sensor8"; + qcom,scaling-factor = <10>; + }; + sensor_information9: qcom,sensor-information-9 { + qcom,sensor-type = "tsens"; + qcom,sensor-name = "tsens_tz_sensor9"; + qcom,scaling-factor = <10>; + }; + sensor_information10: qcom,sensor-information-10 { + qcom,sensor-type = "tsens"; + qcom,sensor-name = "tsens_tz_sensor10"; + qcom,scaling-factor = <10>; + }; + sensor_information11: qcom,sensor-information-11 { + qcom,sensor-type = "tsens"; + qcom,sensor-name = "tsens_tz_sensor11"; + qcom,scaling-factor = <10>; + }; + sensor_information12: qcom,sensor-information-12 { + qcom,sensor-type = "tsens"; + qcom,sensor-name = "tsens_tz_sensor12"; + qcom,scaling-factor = <10>; + qcom,alias-name = "gpu_1"; + }; + sensor_information13: qcom,sensor-information-13 { + qcom,sensor-type = "tsens"; + qcom,sensor-name = "tsens_tz_sensor13"; + qcom,scaling-factor = <10>; + qcom,alias-name = "gpu"; + }; + sensor_information14: qcom,sensor-information-14 { + qcom,sensor-type = "tsens"; + qcom,sensor-name = "tsens_tz_sensor14"; + qcom,scaling-factor = <10>; + }; + sensor_information15: qcom,sensor-information-15 { + qcom,sensor-type = "tsens"; + qcom,sensor-name = "tsens_tz_sensor15"; + qcom,scaling-factor = <10>; + qcom,alias-name = "modem_dsp"; + }; + sensor_information16: qcom,sensor-information-16 { + qcom,sensor-type = "tsens"; + qcom,sensor-name = "tsens_tz_sensor16"; + qcom,scaling-factor = <10>; + }; + sensor_information17: qcom,sensor-information-17 { + qcom,sensor-type = "tsens"; + qcom,sensor-name = "tsens_tz_sensor17"; + qcom,scaling-factor = <10>; + qcom,alias-name = "hvx"; + }; + sensor_information18: qcom,sensor-information-18 { + qcom,sensor-type = "tsens"; + qcom,sensor-name = "tsens_tz_sensor18"; + qcom,scaling-factor = <10>; + qcom,alias-name = "camera"; + }; + sensor_information19: qcom,sensor-information-19 { + qcom,sensor-type = "tsens"; + qcom,sensor-name = "tsens_tz_sensor19"; + qcom,scaling-factor = <10>; + qcom,alias-name = "multi_media_ss"; + }; + sensor_information20: qcom,sensor-information-20 { + qcom,sensor-type = "tsens"; + qcom,sensor-name = "tsens_tz_sensor20"; + qcom,scaling-factor = <10>; + qcom,alias-name = "modem"; + }; + sensor_information21: qcom,sensor-information-21 { + qcom,sensor-type = "tsens"; + qcom,sensor-name = "tsens_tz_sensor21"; + qcom,scaling-factor = <10>; + qcom,alias-name = "pop_mem"; + }; + sensor_information22: qcom,sensor-information-22 { + qcom,sensor-type = "alarm"; + qcom,sensor-name = "pm8998_tz"; + qcom,scaling-factor = <1000>; + }; + sensor_information23: qcom,sensor-information-23 { + qcom,sensor-type = "adc"; + qcom,sensor-name = "msm_therm"; + }; + sensor_information24: qcom,sensor-information-24 { + qcom,sensor-type = "adc"; + qcom,sensor-name = "emmc_therm"; + }; + sensor_information25: qcom,sensor-information-25 { + qcom,sensor-type = "adc"; + qcom,sensor-name = "pa_therm0"; + }; + sensor_information26: qcom,sensor-information-26 { + qcom,sensor-type = "adc"; + qcom,sensor-name = "pa_therm1"; + }; + sensor_information27: qcom,sensor-information-27 { + qcom,sensor-type = "adc"; + qcom,sensor-name = "quiet_therm"; + }; + sensor_information28: qcom,sensor-information-28 { + qcom,sensor-type = "llm"; + qcom,sensor-name = "limits_sensor-01"; + }; + sensor_information29: qcom,sensor-information-29 { + qcom,sensor-type = "llm"; + qcom,sensor-name = "limits_sensor-02"; + }; + }; + + qcom_seecom: qseecom@86600000 { + compatible = "qcom,qseecom"; + reg = <0x86600000 0x2200000>; + reg-names = "secapp-region"; + qcom,hlos-num-ce-hw-instances = <1>; + qcom,hlos-ce-hw-instance = <0>; + qcom,qsee-ce-hw-instance = <0>; + qcom,disk-encrypt-pipe-pair = <2>; + qcom,support-fde; + qcom,no-clock-support; + qcom,appsbl-qseecom-support; + qcom,fde-key-size; + qcom,commonlib64-loaded-by-uefi; + qcom,msm-bus,name = "qseecom-noc"; + qcom,msm-bus,num-cases = <4>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <55 512 0 0>, + <55 512 0 0>, + <55 512 120000 1200000>, + <55 512 393600 3936000>; + clock-names = "core_clk_src", "core_clk", + "iface_clk", "bus_clk"; + clocks = <&clock_gcc clk_ce1_clk>, + <&clock_gcc clk_qseecom_ce1_clk>, + <&clock_gcc clk_gcc_ce1_ahb_m_clk>, + <&clock_gcc clk_gcc_ce1_axi_m_clk>; + qcom,ce-opp-freq = <171430000>; + qcom,qsee-reentrancy-support = <2>; + }; + + qcom_tzlog: tz-log@146BF720 { + compatible = "qcom,tz-log"; + reg = <0x146BF720 0x3000>; + qcom,hyplog-enabled; + hyplog-address-offset = <0x410>; /* 0x066BFB30 */ + hyplog-size-offset = <0x414>; /* 0x066BFB34 */ + }; + + qcom_msmhdcp: qcom,msm_hdcp { + compatible = "qcom,msm-hdcp"; + }; + + qcom_crypto: qcrypto@1DE0000 { + compatible = "qcom,qcrypto"; + reg = <0x1DE0000 0x20000>, + <0x1DC4000 0x24000>; + reg-names = "crypto-base","crypto-bam-base"; + interrupts = <0 206 0>; + qcom,bam-pipe-pair = <2>; + qcom,ce-hw-instance = <0>; + qcom,ce-device = <0>; + qcom,bam-ee = <0>; + qcom,ce-hw-shared; + qcom,clk-mgmt-sus-res; + qcom,msm-bus,name = "qcrypto-noc"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <55 512 0 0>, + <55 512 3936000 393600>; + clock-names = "core_clk_src", "core_clk", + "iface_clk", "bus_clk"; + clocks = <&clock_gcc clk_qcrypto_ce1_clk>, + <&clock_gcc clk_qcrypto_ce1_clk>, + <&clock_gcc clk_gcc_ce1_ahb_m_clk>, + <&clock_gcc clk_gcc_ce1_axi_m_clk>; + qcom,ce-opp-freq = <171430000>; + qcom,use-sw-aes-cbc-ecb-ctr-algo; + qcom,use-sw-aes-xts-algo; + qcom,use-sw-aes-ccm-algo; + qcom,use-sw-ahash-algo; + qcom,use-sw-aead-algo; + qcom,use-sw-hmac-algo; + }; + + qcom_cedev: qcedev@1DE0000{ + compatible = "qcom,qcedev"; + reg = <0x1DE0000 0x20000>, + <0x1DC4000 0x24000>; + reg-names = "crypto-base","crypto-bam-base"; + interrupts = <0 206 0>; + qcom,bam-pipe-pair = <1>; + qcom,ce-hw-instance = <0>; + qcom,ce-device = <0>; + qcom,ce-hw-shared; + qcom,bam-ee = <0>; + qcom,msm-bus,name = "qcedev-noc"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <55 512 0 0>, + <55 512 3936000 393600>; + clock-names = "core_clk_src", "core_clk", + "iface_clk", "bus_clk"; + clocks = <&clock_gcc clk_qcedev_ce1_clk>, + <&clock_gcc clk_qcedev_ce1_clk>, + <&clock_gcc clk_gcc_ce1_ahb_m_clk>, + <&clock_gcc clk_gcc_ce1_axi_m_clk>; + qcom,ce-opp-freq = <171430000>; + }; + + qcom_rng: qrng@793000 { + compatible = "qcom,msm-rng"; + reg = <0x793000 0x1000>; + qcom,msm-rng-iface-clk; + qcom,no-qrng-config; + qcom,msm-bus,name = "msm-rng-noc"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <1 618 0 0>, /* No vote */ + <1 618 0 800>; /* 100 MB/s */ + clocks = <&clock_gcc clk_gcc_prng_ahb_clk>; + clock-names = "iface_clk"; + }; + + mitigation_profile0: qcom,limit_info-0 { + qcom,temperature-sensor = <&sensor_information1>; + qcom,hotplug-mitigation-enable; + }; + + mitigation_profile1: qcom,limit_info-1 { + qcom,temperature-sensor = <&sensor_information2>; + qcom,hotplug-mitigation-enable; + }; + + mitigation_profile2: qcom,limit_info-2 { + qcom,temperature-sensor = <&sensor_information3>; + qcom,hotplug-mitigation-enable; + }; + + mitigation_profile3: qcom,limit_info-3 { + qcom,temperature-sensor = <&sensor_information4>; + qcom,hotplug-mitigation-enable; + }; + + mitigation_profile4: qcom,limit_info-4 { + qcom,temperature-sensor = <&sensor_information7>; + qcom,hotplug-mitigation-enable; + }; + + mitigation_profile5: qcom,limit_info-5 { + qcom,temperature-sensor = <&sensor_information8>; + qcom,hotplug-mitigation-enable; + }; + + mitigation_profile6: qcom,limit_info-6 { + qcom,temperature-sensor = <&sensor_information9>; + qcom,hotplug-mitigation-enable; + }; + + mitigation_profile7: qcom,limit_info-7 { + qcom,temperature-sensor = <&sensor_information10>; + qcom,hotplug-mitigation-enable; + }; + + qcom,lmh { + compatible = "qcom,lmh_v1"; + interrupts = ; + }; + + qcom,msm-thermal { + compatible = "qcom,msm-thermal"; + qcom,sensor-id = <1>; + qcom,poll-ms = <100>; + qcom,therm-reset-temp = <115>; + qcom,core-limit-temp = <90>; + qcom,core-temp-hysteresis = <10>; + qcom,hotplug-temp = <105>; + qcom,hotplug-temp-hysteresis = <20>; + qcom,online-hotplug-core; + qcom,synchronous-cluster-id = <0 1>; + qcom,synchronous-cluster-map = <0 4 &CPU0 &CPU1 &CPU2 &CPU3>, + <1 4 &CPU4 &CPU5 &CPU6 &CPU7>; + clock-names = "osm"; + clocks = <&clock_cpu clk_pwrcl_clk>; + + qcom,vdd-restriction-temp = <5>; + qcom,vdd-restriction-temp-hysteresis = <10>; + + vdd-dig-supply = <&pm8998_s1_floor_level>; + vdd-gfx-supply = <&gfx_vreg>; + + qcom,vdd-dig-rstr{ + qcom,vdd-rstr-reg = "vdd-dig"; + qcom,levels = ; + /* Nominal, Super Turbo, Super Turbo */ + qcom,min-level = ; + /* No Request */ + }; + + qcom,vdd-gfx-rstr{ + qcom,vdd-rstr-reg = "vdd-gfx"; + qcom,levels = <5 6 6>; /* Nominal, Turbo, Turbo */ + qcom,min-level = <1>; /* No Request */ + }; + + msm_thermal_freq: qcom,vdd-apps-rstr{ + qcom,vdd-rstr-reg = "vdd-apps"; + qcom,levels = <1248000>; + qcom,freq-req; + }; + }; + + pcie0: qcom,pcie@01c00000 { + compatible = "qcom,pci-msm"; + cell-index = <0>; + + reg = <0x1c00000 0x2000>, + <0x1c06000 0x1000>, + <0x1b000000 0xf1d>, + <0x1b000f20 0xa8>, + <0x1b100000 0x100000>, + <0x1b200000 0x100000>, + <0x1b300000 0xd00000>; + + reg-names = "parf", "phy", "dm_core", "elbi", + "conf", "io", "bars"; + + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x01000000 0x0 0x1b200000 0x1b200000 0x0 0x100000>, + <0x02000000 0x0 0x1b300000 0x1b300000 0x0 0xd00000>; + interrupt-parent = <&pcie0>; + interrupts = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 + 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 + 36 37>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0xffffffff>; + interrupt-map = <0 0 0 0 &intc 0 0 405 0 + 0 0 0 1 &intc 0 0 135 0 + 0 0 0 2 &intc 0 0 136 0 + 0 0 0 3 &intc 0 0 138 0 + 0 0 0 4 &intc 0 0 139 0 + 0 0 0 5 &intc 0 0 278 0 + 0 0 0 6 &intc 0 0 576 0 + 0 0 0 7 &intc 0 0 577 0 + 0 0 0 8 &intc 0 0 578 0 + 0 0 0 9 &intc 0 0 579 0 + 0 0 0 10 &intc 0 0 580 0 + 0 0 0 11 &intc 0 0 581 0 + 0 0 0 12 &intc 0 0 582 0 + 0 0 0 13 &intc 0 0 583 0 + 0 0 0 14 &intc 0 0 584 0 + 0 0 0 15 &intc 0 0 585 0 + 0 0 0 16 &intc 0 0 586 0 + 0 0 0 17 &intc 0 0 587 0 + 0 0 0 18 &intc 0 0 588 0 + 0 0 0 19 &intc 0 0 589 0 + 0 0 0 20 &intc 0 0 590 0 + 0 0 0 21 &intc 0 0 591 0 + 0 0 0 22 &intc 0 0 592 0 + 0 0 0 23 &intc 0 0 593 0 + 0 0 0 24 &intc 0 0 594 0 + 0 0 0 25 &intc 0 0 595 0 + 0 0 0 26 &intc 0 0 596 0 + 0 0 0 27 &intc 0 0 597 0 + 0 0 0 28 &intc 0 0 598 0 + 0 0 0 29 &intc 0 0 599 0 + 0 0 0 30 &intc 0 0 600 0 + 0 0 0 31 &intc 0 0 601 0 + 0 0 0 32 &intc 0 0 602 0 + 0 0 0 33 &intc 0 0 603 0 + 0 0 0 34 &intc 0 0 604 0 + 0 0 0 35 &intc 0 0 605 0 + 0 0 0 36 &intc 0 0 606 0 + 0 0 0 37 &intc 0 0 607 0>; + + interrupt-names = "int_msi", "int_a", "int_b", "int_c", + "int_d", "int_global_int", + "msi_0", "msi_1", "msi_2", "msi_3", + "msi_4", "msi_5", "msi_6", "msi_7", + "msi_8", "msi_9", "msi_10", "msi_11", + "msi_12", "msi_13", "msi_14", "msi_15", + "msi_16", "msi_17", "msi_18", "msi_19", + "msi_20", "msi_21", "msi_22", "msi_23", + "msi_24", "msi_25", "msi_26", "msi_27", + "msi_28", "msi_29", "msi_30", "msi_31"; + + qcom,phy-sequence = <0x804 0x01 0x00 + 0x034 0x14 0x00 + 0x138 0x30 0x00 + 0x048 0x0f 0x00 + 0x15c 0x06 0x00 + 0x090 0x01 0x00 + 0x088 0x20 0x00 + 0x0f0 0x00 0x00 + 0x0f8 0x01 0x00 + 0x0f4 0xc9 0x00 + 0x11c 0xff 0x00 + 0x120 0x3f 0x00 + 0x164 0x01 0x00 + 0x154 0x00 0x00 + 0x148 0x0a 0x00 + 0x05C 0x19 0x00 + 0x038 0x90 0x00 + 0x0b0 0x82 0x00 + 0x0c0 0x03 0x00 + 0x0bc 0x55 0x00 + 0x0b8 0x55 0x00 + 0x0a0 0x00 0x00 + 0x09c 0x0d 0x00 + 0x098 0x04 0x00 + 0x13c 0x00 0x00 + 0x060 0x08 0x00 + 0x068 0x16 0x00 + 0x070 0x34 0x00 + 0x15c 0x06 0x00 + 0x138 0x33 0x00 + 0x03c 0x02 0x00 + 0x040 0x0e 0x00 + 0x080 0x04 0x00 + 0x0dc 0x00 0x00 + 0x0d8 0x3f 0x00 + 0x00c 0x09 0x00 + 0x010 0x01 0x00 + 0x01c 0x40 0x00 + 0x020 0x01 0x00 + 0x014 0x02 0x00 + 0x018 0x00 0x00 + 0x024 0x7e 0x00 + 0x028 0x15 0x00 + 0x244 0x02 0x00 + 0x2a4 0x12 0x00 + 0x260 0x10 0x00 + 0x28c 0x06 0x00 + 0x504 0x03 0x00 + 0x500 0x10 0x00 + 0x50c 0x14 0x00 + 0x4d4 0x0a 0x00 + 0x4d8 0x04 0x00 + 0x4dc 0x1a 0x00 + 0x434 0x4b 0x00 + 0x414 0x04 0x00 + 0x40c 0x04 0x00 + 0x4f8 0x00 0x00 + 0x4fc 0x80 0x00 + 0x51c 0x40 0x00 + 0x444 0x71 0x00 + 0x43c 0x40 0x00 + 0x854 0x04 0x00 + 0x62c 0x52 0x00 + 0x9ac 0x00 0x00 + 0x8a0 0x01 0x00 + 0x9e0 0x00 0x00 + 0x9dc 0x20 0x00 + 0x9a8 0x00 0x00 + 0x8a4 0x01 0x00 + 0x8a8 0x73 0x00 + 0x9d8 0xaa 0x00 + 0x9b0 0x03 0x00 + 0x804 0x03 0x00 + 0x800 0x00 0x00 + 0x808 0x03 0x00>; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pcie0_clkreq_default + &pcie0_perst_default + &pcie0_wake_default>; + pinctrl-1 = <&pcie0_clkreq_default + &pcie0_perst_default + &pcie0_wake_sleep>; + + perst-gpio = <&tlmm 35 0>; + wake-gpio = <&tlmm 37 0>; + + gdsc-vdd-supply = <&gdsc_pcie_0>; + vreg-1.8-supply = <&pm8998_l2>; + vreg-0.9-supply = <&pm8998_l1>; + vreg-cx-supply = <&pm8998_s1_level>; + + qcom,vreg-1.8-voltage-level = <1200000 1200000 24000>; + qcom,vreg-0.9-voltage-level = <880000 880000 24000>; + qcom,vreg-cx-voltage-level = ; + + qcom,l1-supported; + qcom,l1ss-supported; + qcom,aux-clk-sync; + + qcom,ep-latency = <10>; + + qcom,boot-option = <0x1>; + + linux,pci-domain = <0>; + + qcom,msi-gicm-addr = <0x17a00040>; + qcom,msi-gicm-base = <0x260>; + + qcom,pcie-phy-ver = <0x20>; + qcom,use-19p2mhz-aux-clk; + + iommus = <&anoc1_smmu>; + qcom,smmu-exist; + qcom,smmu-sid-base = <0x1480>; + + qcom,msm-bus,name = "pcie0"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <45 512 0 0>, + <45 512 500 800>; + + clocks = <&clock_gcc clk_gcc_pcie_0_pipe_clk>, + <&clock_gcc clk_ln_bb_clk1>, + <&clock_gcc clk_gcc_pcie_0_aux_clk>, + <&clock_gcc clk_gcc_pcie_0_cfg_ahb_clk>, + <&clock_gcc clk_gcc_pcie_0_mstr_axi_clk>, + <&clock_gcc clk_gcc_pcie_0_slv_axi_clk>, + <&clock_gcc clk_gcc_pcie_clkref_clk>; + + clock-names = "pcie_0_pipe_clk", "pcie_0_ref_clk_src", + "pcie_0_aux_clk", "pcie_0_cfg_ahb_clk", + "pcie_0_mstr_axi_clk", "pcie_0_slv_axi_clk", + "pcie_0_ldo"; + + max-clock-frequency-hz = <0>, <0>, <19200000>, + <0>, <0>, <0>, <0>, <0>, <0>, + <0>, <0>, <0>, <0>, <0>, <0>, + <0>, <0>; + + resets = <&clock_gcc PCIE_PHY_BCR>, + <&clock_gcc PCIE_0_PHY_BCR>, + <&clock_gcc PCIE_0_PHY_BCR>; + + reset-names = "pcie_phy_reset", + "pcie_0_phy_reset", + "pcie_0_phy_pipe_reset"; + }; + + qcom,bcl { + compatible = "qcom,bcl"; + qcom,bcl-enable; + qcom,bcl-framework-interface; + qcom,bcl-freq-control-list = <&CPU4 &CPU5 &CPU6 &CPU7>; + qcom,bcl-hotplug-list = <&CPU4 &CPU5 &CPU6 &CPU7>; + qcom,bcl-soc-hotplug-list = <&CPU4 &CPU5 &CPU6 &CPU7>; + qcom,ibat-monitor { + qcom,low-threshold-uamp = <3400000>; + qcom,high-threshold-uamp = <4200000>; + qcom,mitigation-freq-khz = <576000>; + qcom,vph-high-threshold-uv = <3500000>; + qcom,vph-low-threshold-uv = <3300000>; + qcom,soc-low-threshold = <10>; + qcom,thermal-handle = <&msm_thermal_freq>; + }; + }; + + qcom,ssc@5c00000 { + compatible = "qcom,pil-tz-generic"; + reg = <0x5c00000 0x4000>; + interrupts = <0 390 1>; + + vdd_cx-supply = <&pm8998_l27_level>; + vdd_px-supply = <&pm8998_lvs2>; + qcom,vdd_cx-uV-uA = ; + qcom,proxy-reg-names = "vdd_cx", "vdd_px"; + qcom,keep-proxy-regs-on; + + clocks = <&clock_gcc clk_cxo_pil_ssc_clk>, + <&clock_gcc clk_aggre2_noc_clk>; + clock-names = "xo", "aggre2"; + qcom,proxy-clock-names = "xo", "aggre2"; + + qcom,pas-id = <12>; + qcom,proxy-timeout-ms = <10000>; + qcom,smem-id = <424>; + qcom,sysmon-id = <3>; + qcom,ssctl-instance-id = <0x16>; + qcom,firmware-name = "slpi"; + status = "ok"; + memory-region = <&pil_slpi_mem>; + + /* GPIO inputs from ssc */ + qcom,gpio-err-fatal = <&smp2pgpio_ssr_smp2p_3_in 0 0>; + qcom,gpio-proxy-unvote = <&smp2pgpio_ssr_smp2p_3_in 2 0>; + qcom,gpio-err-ready = <&smp2pgpio_ssr_smp2p_3_in 1 0>; + qcom,gpio-stop-ack = <&smp2pgpio_ssr_smp2p_3_in 3 0>; + + /* GPIO output to ssc */ + qcom,gpio-force-stop = <&smp2pgpio_ssr_smp2p_3_out 0 0>; + }; + + qcom,venus@cce0000 { + compatible = "qcom,pil-tz-generic"; + reg = <0xcce0000 0x4000>; + + vdd-supply = <&gdsc_venus>; + qcom,proxy-reg-names = "vdd"; + + clocks = <&clock_mmss clk_mmss_video_core_clk>, + <&clock_mmss clk_mmss_mnoc_ahb_clk>, + <&clock_mmss clk_mmss_video_ahb_clk>, + <&clock_gcc clk_mmssnoc_axi_clk>, + <&clock_mmss clk_mmss_video_axi_clk>, + <&clock_mmss clk_mmss_video_maxi_clk>; + clock-names = "core_clk", "mnoc_ahb_clk", "iface_clk", + "noc_axi_clk", "bus_clk", "maxi_clk"; + qcom,proxy-clock-names = "core_clk","mnoc_ahb_clk", + "iface_clk", "noc_axi_clk", "bus_clk", "maxi_clk"; + + qcom,pas-id = <9>; + qcom,msm-bus,name = "pil-venus"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <63 512 0 0>, + <63 512 0 304000>; + qcom,proxy-timeout-ms = <100>; + qcom,firmware-name = "venus"; + memory-region = <&pil_video_mem>; + status = "ok"; + }; + + wdog: qcom,wdt@17817000 { + compatible = "qcom,msm-watchdog"; + reg = <0x17817000 0x1000>; + reg-names = "wdt-base"; + interrupts = <0 3 0>, <0 4 0>; + qcom,bark-time = <11000>; + qcom,pet-time = <10000>; + qcom,ipi-ping; + qcom,wakeup-enable; + qcom,scandump-size = <0x40000>; + }; + + qcom,spss@1d00000 { + compatible = "qcom,pil-tz-generic"; + reg = <0x1d0101c 0x4>, + <0x1d01024 0x4>, + <0x1d01028 0x4>, + <0x1d0103c 0x4>, + <0x1d02030 0x4>; + reg-names = "sp2soc_irq_status", "sp2soc_irq_clr", + "sp2soc_irq_mask", "rmb_err", "rmb_err_spare2"; + interrupts = <0 352 1>; + + vdd_cx-supply = <&pm8998_s1_level>; + qcom,proxy-reg-names = "vdd_cx"; + qcom,vdd_cx-uV-uA = ; + + clocks = <&clock_gcc clk_cxo_pil_spss_clk>; + clock-names = "xo"; + qcom,proxy-clock-names = "xo"; + qcom,pil-generic-irq-handler; + status = "ok"; + + qcom,pas-id = <14>; + qcom,proxy-timeout-ms = <10000>; + qcom,firmware-name = "spss"; + memory-region = <&spss_mem>; + qcom,spss-scsr-bits = <24 25>; + }; + + qcom,msm-rtb { + compatible = "qcom,msm-rtb"; + qcom,rtb-size = <0x100000>; + }; + + qcom,mpm2-sleep-counter@10a3000 { + compatible = "qcom,mpm2-sleep-counter"; + reg = <0x010a3000 0x1000>; + clock-frequency = <32768>; + }; + + qcom,msm-imem@146bf000 { + compatible = "qcom,msm-imem"; + reg = <0x146bf000 0x1000>; + ranges = <0x0 0x146bf000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + + mem_dump_table@10 { + compatible = "qcom,msm-imem-mem_dump_table"; + reg = <0x10 8>; + }; + + dload_type@18 { + compatible = "qcom,msm-imem-dload-type"; + reg = <0x18 4>; + }; + + restart_reason@65c { + compatible = "qcom,msm-imem-restart_reason"; + reg = <0x65c 4>; + }; + + boot_stats@6b0 { + compatible = "qcom,msm-imem-boot_stats"; + reg = <0x6b0 32>; + }; + + kaslr_offset@6d0 { + compatible = "qcom,msm-imem-kaslr_offset"; + reg = <0x6d0 12>; + }; + + pil@94c { + compatible = "qcom,msm-imem-pil"; + reg = <0x94c 200>; + }; + + diag_dload@c8 { + compatible = "qcom,msm-imem-diag-dload"; + reg = <0xc8 200>; + }; + }; + + cpu_pmu: cpu-pmu { + compatible = "arm,armv8-pmuv3"; + qcom,irq-is-percpu; + interrupts = <1 6 4>; + }; + + cpuss_dump { + compatible = "qcom,cpuss-dump"; + qcom,l1_i_cache0 { + qcom,dump-node = <&L1_I_0>; + qcom,dump-id = <0x60>; + }; + qcom,l1_i_cache1 { + qcom,dump-node = <&L1_I_1>; + qcom,dump-id = <0x61>; + }; + qcom,l1_i_cache2 { + qcom,dump-node = <&L1_I_2>; + qcom,dump-id = <0x62>; + }; + qcom,l1_i_cache3 { + qcom,dump-node = <&L1_I_3>; + qcom,dump-id = <0x63>; + }; + qcom,l1_i_cache100 { + qcom,dump-node = <&L1_I_100>; + qcom,dump-id = <0x64>; + }; + qcom,l1_i_cache101 { + qcom,dump-node = <&L1_I_101>; + qcom,dump-id = <0x65>; + }; + qcom,l1_i_cache102 { + qcom,dump-node = <&L1_I_102>; + qcom,dump-id = <0x66>; + }; + qcom,l1_i_cache103 { + qcom,dump-node = <&L1_I_103>; + qcom,dump-id = <0x67>; + }; + qcom,l1_d_cache0 { + qcom,dump-node = <&L1_D_0>; + qcom,dump-id = <0x80>; + }; + qcom,l1_d_cache1 { + qcom,dump-node = <&L1_D_1>; + qcom,dump-id = <0x81>; + }; + qcom,l1_d_cache2 { + qcom,dump-node = <&L1_D_2>; + qcom,dump-id = <0x82>; + }; + qcom,l1_d_cache3 { + qcom,dump-node = <&L1_D_3>; + qcom,dump-id = <0x83>; + }; + qcom,l1_d_cache100 { + qcom,dump-node = <&L1_D_100>; + qcom,dump-id = <0x84>; + }; + qcom,l1_d_cache101 { + qcom,dump-node = <&L1_D_101>; + qcom,dump-id = <0x85>; + }; + qcom,l1_d_cache102 { + qcom,dump-node = <&L1_D_102>; + qcom,dump-id = <0x86>; + }; + qcom,l1_d_cache103 { + qcom,dump-node = <&L1_D_103>; + qcom,dump-id = <0x87>; + }; + qcom,l1_tlb_dump0 { + qcom,dump-node = <&L1_TLB_0>; + qcom,dump-id = <0x20>; + }; + qcom,l1_tlb_dump1 { + qcom,dump-node = <&L1_TLB_1>; + qcom,dump-id = <0x21>; + }; + qcom,l1_tlb_dump2 { + qcom,dump-node = <&L1_TLB_2>; + qcom,dump-id = <0x22>; + }; + qcom,l1_tlb_dump3 { + qcom,dump-node = <&L1_TLB_3>; + qcom,dump-id = <0x23>; + }; + qcom,l1_tlb_dump100 { + qcom,dump-node = <&L1_TLB_100>; + qcom,dump-id = <0x24>; + }; + qcom,l1_tlb_dump101 { + qcom,dump-node = <&L1_TLB_101>; + qcom,dump-id = <0x25>; + }; + qcom,l1_tlb_dump102 { + qcom,dump-node = <&L1_TLB_102>; + qcom,dump-id = <0x26>; + }; + qcom,l1_tlb_dump103 { + qcom,dump-node = <&L1_TLB_103>; + qcom,dump-id = <0x27>; + }; + }; + + ssc_sensors: qcom,msm-ssc-sensors { + compatible = "qcom,msm-ssc-sensors"; + status = "ok"; + qcom,firmware-name = "slpi_v1"; + }; + + dcc: dcc@10b3000 { + compatible = "qcom,dcc"; + reg = <0x10b3000 0x1000>, + <0x10b4000 0x2000>; + reg-names = "dcc-base", "dcc-ram-base"; + + clocks = <&clock_gcc clk_gcc_dcc_ahb_clk>; + clock-names = "dcc_clk"; + }; + + qcom,msm-core@780000 { + compatible = "qcom,apss-core-ea"; + reg = <0x780000 0x1000>; + qcom,low-hyst-temp = <100>; + qcom,high-hyst-temp = <100>; + qcom,polling-interval = <50>; + + ea0: ea0 { + sensor = <&sensor_information1>; + }; + + ea1: ea1 { + sensor = <&sensor_information2>; + }; + + ea2: ea2 { + sensor = <&sensor_information3>; + }; + + ea3: ea3 { + sensor = <&sensor_information4>; + }; + + ea4: ea4 { + sensor = <&sensor_information7>; + }; + + ea5: ea5 { + sensor = <&sensor_information8>; + }; + + ea6: ea6 { + sensor = <&sensor_information9>; + }; + + ea7: ea7 { + sensor = <&sensor_information10>; + }; + + }; + + msm_ath10k_wlan: qcom,msm_ath10k_wlan { + status = "disabled"; + compatible = "qcom,wcn3990-wifi"; + reg = <0x18800000 0x800000>; + reg-names = "membase"; + clocks = <&clock_gcc clk_rf_clk2_pin>; + clock-names = "cxo_ref_clk_pin"; + interrupts = + <0 413 0 /* CE0 */ >, + <0 414 0 /* CE1 */ >, + <0 415 0 /* CE2 */ >, + <0 416 0 /* CE3 */ >, + <0 417 0 /* CE4 */ >, + <0 418 0 /* CE5 */ >, + <0 420 0 /* CE6 */ >, + <0 421 0 /* CE7 */ >, + <0 422 0 /* CE8 */ >, + <0 423 0 /* CE9 */ >, + <0 424 0 /* CE10 */ >, + <0 425 0 /* CE11 */ >; + vdd-0.8-cx-mx-supply = <&pm8998_l5>; + vdd-1.8-xo-supply = <&pm8998_l7_pin_ctrl>; + vdd-1.3-rfa-supply = <&pm8998_l17_pin_ctrl>; + vdd-3.3-ch0-supply = <&pm8998_l25_pin_ctrl>; + qcom,vdd-0.8-cx-mx-config = <800000 800000>; + qcom,vdd-3.3-ch0-config = <3104000 3312000>; + }; + + qcom,icnss@18800000 { + compatible = "qcom,icnss"; + reg = <0x18800000 0x800000>, + <0xa0000000 0x10000000>, + <0xb0000000 0x10000>; + reg-names = "membase", "smmu_iova_base", "smmu_iova_ipa"; + clocks = <&clock_gcc clk_rf_clk2_pin>; + clock-names = "cxo_ref_clk_pin"; + iommus = <&anoc2_smmu 0x1900>, + <&anoc2_smmu 0x1901>; + interrupts = <0 413 0 /* CE0 */ >, + <0 414 0 /* CE1 */ >, + <0 415 0 /* CE2 */ >, + <0 416 0 /* CE3 */ >, + <0 417 0 /* CE4 */ >, + <0 418 0 /* CE5 */ >, + <0 420 0 /* CE6 */ >, + <0 421 0 /* CE7 */ >, + <0 422 0 /* CE8 */ >, + <0 423 0 /* CE9 */ >, + <0 424 0 /* CE10 */ >, + <0 425 0 /* CE11 */ >; + qcom,wlan-msa-memory = <0x100000>; + vdd-0.8-cx-mx-supply = <&pm8998_l5>; + vdd-1.8-xo-supply = <&pm8998_l7_pin_ctrl>; + vdd-1.3-rfa-supply = <&pm8998_l17_pin_ctrl>; + vdd-3.3-ch0-supply = <&pm8998_l25_pin_ctrl>; + qcom,vdd-0.8-cx-mx-config = <800000 800000>; + qcom,vdd-3.3-ch0-config = <3104000 3312000>; + qcom,icnss-vadc = <&pm8998_vadc>; + qcom,icnss-adc_tm = <&pm8998_adc_tm>; + }; + + tspp: msm_tspp@0c1e7000 { + compatible = "qcom,msm_tspp"; + reg = <0x0c1e7000 0x200>, /* MSM_TSIF0_PHYS */ + <0x0c1e8000 0x200>, /* MSM_TSIF1_PHYS */ + <0x0c1e9000 0x1000>, /* MSM_TSPP_PHYS */ + <0x0c1c4000 0x23000>; /* MSM_TSPP_BAM_PHYS */ + reg-names = "MSM_TSIF0_PHYS", + "MSM_TSIF1_PHYS", + "MSM_TSPP_PHYS", + "MSM_TSPP_BAM_PHYS"; + interrupts = <0 121 0>, /* TSIF_TSPP_IRQ */ + <0 119 0>, /* TSIF0_IRQ */ + <0 120 0>, /* TSIF1_IRQ */ + <0 122 0>; /* TSIF_BAM_IRQ */ + interrupt-names = "TSIF_TSPP_IRQ", + "TSIF0_IRQ", + "TSIF1_IRQ", + "TSIF_BAM_IRQ"; + + clock-names = "iface_clk", "ref_clk"; + clocks = <&clock_gcc clk_gcc_tsif_ahb_clk>, + <&clock_gcc clk_gcc_tsif_ref_clk>; + + qcom,msm-bus,name = "tsif"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <82 512 0 0>, /* No vote */ + <82 512 12288 24576>; + /* Max. bandwidth, 2xTSIF, each max of 96Mbps */ + + pinctrl-names = "disabled", + "tsif0-mode1", "tsif0-mode2", + "tsif1-mode1", "tsif1-mode2", + "dual-tsif-mode1", "dual-tsif-mode2"; + + pinctrl-0 = <>; /* disabled */ + pinctrl-1 = <&tsif0_signals_active>; /* tsif0-mode1 */ + pinctrl-2 = <&tsif0_signals_active + &tsif0_sync_active>; /* tsif0-mode2 */ + pinctrl-3 = <&tsif1_signals_active>; /* tsif1-mode1 */ + pinctrl-4 = <&tsif1_signals_active + &tsif1_sync_active>; /* tsif1-mode2 */ + pinctrl-5 = <&tsif0_signals_active + &tsif1_signals_active>; /* dual-tsif-mode1 */ + pinctrl-6 = <&tsif0_signals_active + &tsif0_sync_active + &tsif1_signals_active + &tsif1_sync_active>; /* dual-tsif-mode2 */ + }; + + wil6210: qcom,wil6210 { + status = "disabled"; + compatible = "qcom,wil6210"; + qcom,pcie-parent = <&pcie0>; + qcom,wigig-en = <&tlmm 80 0>; + qcom,msm-bus,name = "wil6210"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <45 512 0 0>, + <45 512 600000 800000>; /* ~4.6Gbps (MCS12) */ + qcom,use-ext-supply; + vdd-supply= <&pm8998_s7>; + vddio-supply= <&pm8998_s5>; + qcom,use-ext-clocks; + clocks = <&clock_gcc clk_rf_clk3>, + <&clock_gcc clk_rf_clk3_pin>; + clock-names = "rf_clk3_clk", "rf_clk3_pin_clk"; + qcom,smmu-support; + qcom,smmu-s1-en; + qcom,smmu-fast-map; + qcom,smmu-coherent; + qcom,smmu-mapping = <0x20000000 0xe0000000>; + qcom,keep-radio-on-during-sleep; + }; + + qcom,qsee_ipc_irq_bridge { + compatible = "qcom,qsee-ipc-irq-bridge"; + + qcom,qsee-ipc-irq-spss { + qcom,rx-irq-clr = <0x1d08008 0x4>; + qcom,rx-irq-clr-mask = <0x1>; + qcom,dev-name = "qsee_ipc_irq_spss"; + interrupts = <0 349 4>; + label = "spss"; + }; + }; +}; + +&clock_cpu { + lmh_dcvs0: qcom,limits-dcvs@0 { + compatible = "qcom,msm-hw-limits"; + interrupts = ; + }; + + lmh_dcvs1: qcom,limits-dcvs@1 { + compatible = "qcom,msm-hw-limits"; + interrupts = ; + }; +}; + +&gdsc_usb30 { + status = "ok"; +}; + +&gdsc_pcie_0 { + status = "ok"; +}; + +&gdsc_ufs { + status = "ok"; +}; + +&gdsc_bimc_smmu { + clock-names = "bus_clk"; + clocks = <&clock_mmss clk_mmss_bimc_smmu_axi_clk>; + proxy-supply = <&gdsc_bimc_smmu>; + qcom,proxy-consumer-enable; + status = "ok"; +}; + +&gdsc_hlos1_vote_lpass_adsp { + status = "ok"; +}; + +&gdsc_hlos1_vote_lpass_core { + status = "ok"; +}; + +&gdsc_venus { + status = "ok"; +}; + +&gdsc_venus_core0 { + status = "ok"; + qcom,support-hw-trigger; +}; + +&gdsc_venus_core1 { + status = "ok"; + qcom,support-hw-trigger; +}; + +&gdsc_camss_top { + status = "ok"; +}; + +&gdsc_vfe0 { + parent-supply = <&gdsc_camss_top>; + status = "ok"; +}; + +&gdsc_vfe1 { + parent-supply = <&gdsc_camss_top>; + status = "ok"; +}; + +&gdsc_cpp { + parent-supply = <&gdsc_camss_top>; + qcom,support-hw-trigger; + status = "ok"; +}; + +&gdsc_mdss { + proxy-supply = <&gdsc_mdss>; + qcom,proxy-consumer-enable; + status = "ok"; +}; + +&gdsc_gpu_gx { + clock-names = "core_root_clk"; + clocks = <&clock_gfx clk_gfx3d_clk_src>; + qcom,force-enable-root-clk; + parent-supply = <&gfx_vreg>; + status = "ok"; +}; + +&gdsc_gpu_cx { + status = "ok"; +}; + +#include "msm-pm8998.dtsi" +#include "msm-pmi8998.dtsi" +#include "msm-pm8005.dtsi" +#include "msm-pm8998-rpm-regulator.dtsi" +#include "msm8998-regulator.dtsi" + +#include "msm8998-pm.dtsi" +#include "msm-arm-smmu-8998.dtsi" +#include "msm-arm-smmu-impl-defs-8998.dtsi" +#include "msm8998-ion.dtsi" +#include "msm8998-camera.dtsi" +#include "msm8998-vidc.dtsi" +#include "msm8998-coresight.dtsi" +#include "msm8998-bus.dtsi" +#include "msm8998-gpu.dtsi" +#include "msm8998-pinctrl.dtsi" +#include "msm-audio-lpass.dtsi" +#include "msm8998-mdss-pll.dtsi" +#include "msm-rdbg.dtsi" +#include "msm8998-blsp.dtsi" +#include "msm8998-audio.dtsi" +#include "msm8998-sde.dtsi" --- /dev/null 2019-10-24 16:47:25.704025805 +0200 +++ linux-4.4.115-fbx/arch/arm64/boot/dts/qcom/msm8998-gpu.dtsi 2019-01-22 16:16:21.195225506 +0100 @@ -0,0 +1,277 @@ +/* Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&soc { + + pil_gpu: qcom,kgsl-hyp { + compatible = "qcom,pil-tz-generic"; + qcom,pas-id = <13>; + qcom,firmware-name = "a540_zap"; + }; + + msm_bus: qcom,kgsl-busmon{ + label = "kgsl-busmon"; + compatible = "qcom,kgsl-busmon"; + }; + + gpubw: qcom,gpubw { + compatible = "qcom,devbw"; + governor = "bw_vbif"; + qcom,src-dst-ports = <26 512>; + /* + * active-only flag is used while registering the bus + * governor.It helps release the bus vote when the CPU + * subsystem is inactiv3 + */ + qcom,active-only; + qcom,bw-tbl = + < 0 /* off */ >, + < 762 /* 100 MHz */ >, + < 1144 /* 150 MHz */ >, + < 1525 /* 200 MHz */ >, + < 2288 /* 300 MHz */ >, + < 3143 /* 412 MHz */ >, + < 4173 /* 547 MHz */ >, + < 5195 /* 681 MHz */ >, + < 5859 /* 768 MHz */ >, + < 7759 /* 1017 MHz */ >, + < 9887 /* 1296 MHz */ >, + < 11863 /* 1555 MHz */ >, + < 13763 /* 1804 MHz */ >; + }; + + msm_gpu: qcom,kgsl-3d0@5000000 { + label = "kgsl-3d0"; + compatible = "qcom,kgsl-3d0", "qcom,kgsl-3d"; + status = "ok"; + reg = <0x5000000 0x40000>; + reg-names = "kgsl_3d0_reg_memory"; + interrupts = <0 300 0>; + interrupt-names = "kgsl_3d0_irq"; + qcom,id = <0>; + + qcom,chipid = <0x05040000>; + qcom,gpu-efuse-leakage = <0x00070130 24>; + qcom,base-leakage-coefficient = <34>; + qcom,lm-limit = <6000>; + + qcom,initial-pwrlevel = <4>; + + qcom,idle-timeout = <80>; // + qcom,no-nap; + + qcom,highest-bank-bit = <15>; + + qcom,snapshot-size = <1048576>; //bytes + + qcom,gpu-qdss-stm = <0x161c0000 0x40000>; // base addr, size + + qcom,gpu-qtimer = <0x17921000 0x1000>; // base addr, size + + qcom,tsens-name = "tsens_tz_sensor12"; + + /* Avoid L2PC on big cluster CPUs (CPU 4,5,6,7) */ + qcom,l2pc-cpu-mask = <0x000000f0>; + + /* Quirks */ + qcom,gpu-quirk-lmloadkill-disable; + + /* DRM settings */ + qcom,gpmu-tsens = <0x000c000d>; + qcom,max-power = <5448>; + qcom,gpmu-firmware = "a540_gpmu.fw2"; + qcom,gpmu-version = <3 0>; + qcom,zap-shader = "a540_zap"; + + clocks = <&clock_gfx clk_gpucc_gfx3d_clk>, + <&clock_gcc clk_gcc_gpu_cfg_ahb_clk>, + <&clock_gpu clk_gpucc_rbbmtimer_clk>, + <&clock_gcc clk_gcc_bimc_gfx_clk>, + <&clock_gcc clk_gcc_gpu_bimc_gfx_clk>, + <&clock_gpu clk_gpucc_gfx3d_isense_clk>, + <&clock_gpu clk_gpucc_rbcpr_clk>, + <&clock_gcc clk_gcc_gpu_iref_clk>; + + clock-names = "core_clk", "iface_clk", "rbbmtimer_clk", + "mem_clk", "mem_iface_clk", "isense_clk", "rbcpr_clk", + "iref_clk"; + + qcom,isense-clk-on-level = <1>; + /* Bus Scale Settings */ + qcom,gpubw-dev = <&gpubw>; + qcom,bus-control; + qcom,msm-bus,name = "grp3d"; + qcom,bus-width = <32>; + qcom,msm-bus,num-cases = <13>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <26 512 0 0>, + + <26 512 0 800000>, // 1 bus=100 + <26 512 0 1200000>, // 2 bus=150 + <26 512 0 1600000>, // 3 bus=200 + <26 512 0 2400000>, // 4 bus=300 + <26 512 0 3296000>, // 5 bus=412 + <26 512 0 4376000>, // 6 bus=547 + <26 512 0 5448000>, // 7 bus=681 + <26 512 0 6144000>, // 8 bus=768 + <26 512 0 8136000>, // 9 bus=1017 + <26 512 0 10368000>, // 10 bus=1296 + <26 512 0 12440000>, // 11 bus=1555 + <26 512 0 14432000>; // 12 bus=1804 + + /* GDSC regulator names */ + regulator-names = "vddcx", "vdd"; + /* GDSC oxili regulators */ + vddcx-supply = <&gdsc_gpu_cx>; + vdd-supply = <&gdsc_gpu_gx>; + + /* Trace bus */ + coresight-name = "coresight-gfx"; + coresight-atid = <3>; + port { + gfx_out_funnel_in1: endpoint { + remote-endpoint = <&funnel_in1_in_gfx>; + }; + }; + + /* GPU Mempools */ + qcom,gpu-mempools { + #address-cells= <1>; + #size-cells = <0>; + compatible = "qcom,gpu-mempools"; + + /* 4K Page Pool configuration */ + qcom,gpu-mempool@0 { + reg = <0>; + qcom,mempool-page-size = <4096>; + qcom,mempool-reserved = <2048>; + qcom,mempool-allocate; + }; + /* 8K Page Pool configuration */ + qcom,gpu-mempool@1 { + reg = <1>; + qcom,mempool-page-size = <8192>; + qcom,mempool-reserved = <1024>; + qcom,mempool-allocate; + }; + /* 64K Page Pool configuration */ + qcom,gpu-mempool@2 { + reg = <2>; + qcom,mempool-page-size = <65536>; + qcom,mempool-reserved = <256>; + }; + /* 1M Page Pool configuration */ + qcom,gpu-mempool@3 { + reg = <3>; + qcom,mempool-page-size = <1048576>; + qcom,mempool-reserved = <32>; + }; + }; + + /* Power levels */ + qcom,gpu-pwrlevels { + #address-cells = <1>; + #size-cells = <0>; + + compatible = "qcom,gpu-pwrlevels"; + + qcom,gpu-pwrlevel@0 { + reg = <0>; + qcom,gpu-freq = <650000000>; + qcom,bus-freq = <12>; + qcom,bus-min = <11>; + qcom,bus-max = <12>; + }; + + + qcom,gpu-pwrlevel@1 { + reg = <1>; + qcom,gpu-freq = <504000000>; + qcom,bus-freq = <11>; + qcom,bus-min = <10>; + qcom,bus-max = <12>; + }; + + qcom,gpu-pwrlevel@2 { + reg = <2>; + qcom,gpu-freq = <403000000>; + qcom,bus-freq = <10>; + qcom,bus-min = <9>; + qcom,bus-max = <11>; + }; + + qcom,gpu-pwrlevel@3 { + reg = <3>; + qcom,gpu-freq = <332000000>; + qcom,bus-freq = <7>; + qcom,bus-min = <6>; + qcom,bus-max = <8>; + }; + + qcom,gpu-pwrlevel@4 { + reg = <4>; + qcom,gpu-freq = <251000000>; + qcom,bus-freq = <4>; + qcom,bus-min = <3>; + qcom,bus-max = <5>; + }; + + qcom,gpu-pwrlevel@5 { + reg = <5>; + qcom,gpu-freq = <171000000>; + qcom,bus-freq = <3>; + qcom,bus-min = <1>; + qcom,bus-max = <4>; + }; + + qcom,gpu-pwrlevel@6 { + reg = <6>; + qcom,gpu-freq = <27000000>; + qcom,bus-freq = <0>; + qcom,bus-min = <0>; + qcom,bus-max = <0>; + }; + }; + + }; + + kgsl_msm_iommu: qcom,kgsl-iommu { + compatible = "qcom,kgsl-smmu-v2"; + + reg = <0x05040000 0x10000>; + qcom,protect = <0x40000 0x10000>; + qcom,micro-mmu-control = <0x6000>; + + clocks =<&clock_gcc clk_gcc_gpu_cfg_ahb_clk>, + <&clock_gcc clk_gcc_bimc_gfx_clk>, + <&clock_gcc clk_gcc_gpu_bimc_gfx_clk>; + + clock-names = "iface_clk", "mem_clk", "mem_iface_clk"; + + qcom,secure_align_mask = <0xfff>; + qcom,retention; + qcom,hyp_secure_alloc; + + gfx3d_user: gfx3d_user { + compatible = "qcom,smmu-kgsl-cb"; + label = "gfx3d_user"; + iommus = <&kgsl_smmu 0>; + qcom,gpu-offset = <0x48000>; + }; + + gfx3d_secure: gfx3d_secure { + compatible = "qcom,smmu-kgsl-cb"; + iommus = <&kgsl_smmu 2>; + }; + }; +}; --- /dev/null 2019-10-24 16:47:25.704025805 +0200 +++ linux-4.4.115-fbx/arch/arm64/boot/dts/qcom/msm8998-ion.dtsi 2019-01-22 16:16:21.195225506 +0100 @@ -0,0 +1,53 @@ +/* Copyright (c) 2015-2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&soc { + qcom,ion { + compatible = "qcom,msm-ion"; + #address-cells = <1>; + #size-cells = <0>; + + system_heap: qcom,ion-heap@25 { + reg = <25>; + qcom,ion-heap-type = "SYSTEM"; + }; + + qcom,ion-heap@22 { /* ADSP HEAP */ + reg = <22>; + memory-region = <&adsp_mem>; + qcom,ion-heap-type = "DMA"; + }; + + qcom,ion-heap@27 { /* QSEECOM HEAP */ + reg = <27>; + memory-region = <&qseecom_mem>; + qcom,ion-heap-type = "DMA"; + }; + + qcom,ion-heap@13 { /* SPSS HEAP */ + reg = <13>; + memory-region = <&sp_mem>; + qcom,ion-heap-type = "DMA"; + }; + + qcom,ion-heap@10 { /* SECURE DISPLAY HEAP */ + reg = <10>; + memory-region = <&secure_display_memory>; + qcom,ion-heap-type = "HYP_CMA"; + }; + + qcom,ion-heap@9 { + reg = <9>; + qcom,ion-heap-type = "SYSTEM_SECURE"; + }; + }; +}; --- /dev/null 2019-10-24 16:47:25.704025805 +0200 +++ linux-4.4.115-fbx/arch/arm64/boot/dts/qcom/msm8998-mdss-pll.dtsi 2019-01-22 16:16:21.195225506 +0100 @@ -0,0 +1,173 @@ +/* Copyright (c) 2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&soc { + mdss_dsi0_pll: qcom,mdss_dsi_pll@c994400 { + compatible = "qcom,mdss_dsi_pll_8998"; + status = "ok"; + label = "MDSS DSI 0 PLL"; + cell-index = <0>; + #clock-cells = <1>; + + reg = <0xc994a00 0x1c0>, + <0xc994400 0x7c0>, + <0x0c8c2300 0x8>; + reg-names = "pll_base", "phy_base", "gdsc_base"; + + gdsc-supply = <&gdsc_mdss>; + + clocks = <&clock_mmss clk_mmss_mdss_ahb_clk>; + clock-names = "iface_clk"; + clock-rate = <0>; + qcom,dsi-pll-ssc-en; + qcom,dsi-pll-ssc-mode = "down-spread"; + + qcom,platform-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,platform-supply-entry@0 { + reg = <0>; + qcom,supply-name = "gdsc"; + qcom,supply-min-voltage = <0>; + qcom,supply-max-voltage = <0>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + }; + + }; + }; + + mdss_dsi1_pll: qcom,mdss_dsi_pll@c996400 { + compatible = "qcom,mdss_dsi_pll_8998"; + status = "ok"; + label = "MDSS DSI 1 PLL"; + cell-index = <1>; + #clock-cells = <1>; + + reg = <0x0c996a00 0x1c0>, + <0x0c996400 0x7c0>, + <0x008c2300 0x8>; + reg-names = "pll_base", "phy_base", "gdsc_base"; + + gdsc-supply = <&gdsc_mdss>; + + clocks = <&clock_mmss clk_mmss_mdss_ahb_clk>; + clock-names = "iface_clk"; + clock-rate = <0>; + qcom,dsi-pll-ssc-en; + qcom,dsi-pll-ssc-mode = "down-spread"; + + qcom,platform-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,platform-supply-entry@0 { + reg = <0>; + qcom,supply-name = "gdsc"; + qcom,supply-min-voltage = <0>; + qcom,supply-max-voltage = <0>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + }; + }; + }; + + mdss_dp_pll: qcom,mdss_dp_pll@c011000 { + compatible = "qcom,mdss_dp_pll_8998"; + status = "ok"; + label = "MDSS DP PLL"; + cell-index = <0>; + #clock-cells = <1>; + + reg = <0xc011c00 0x190>, + <0xc011000 0x910>, + <0x0c8c2300 0x8>; + reg-names = "pll_base", "phy_base", "gdsc_base"; + + gdsc-supply = <&gdsc_mdss>; + + clocks = <&clock_mmss clk_mmss_mdss_ahb_clk>, + <&clock_gcc clk_ln_bb_clk1>, + <&clock_gcc clk_gcc_usb3_clkref_clk>; + clock-names = "iface_clk", "ref_clk_src", "ref_clk"; + clock-rate = <0>; + + qcom,platform-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,platform-supply-entry@0 { + reg = <0>; + qcom,supply-name = "gdsc"; + qcom,supply-min-voltage = <0>; + qcom,supply-max-voltage = <0>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + }; + + }; + }; + + mdss_hdmi_pll: qcom,mdss_hdmi_pll@0xc9a0600 { + compatible = "qcom,mdss_hdmi_pll_8998"; + label = "MDSS HDMI PLL"; + cell-index = <2>; + #clock-cells = <1>; + + reg = <0xc9a0600 0xb10>, + <0xc9a1200 0x0e4>, + <0xc8c2300 0x8>; + reg-names = "pll_base", "phy_base", "gdsc_base"; + + gdsc-supply = <&gdsc_mdss>; + vdda-pll-supply = <&pm8998_l2>; + vdda-phy-supply = <&pm8998_l12>; + + clocks = <&clock_mmss clk_mmss_mdss_ahb_clk>, + <&clock_gcc clk_gcc_hdmi_clkref_clk>, + <&clock_gcc clk_ln_bb_clk1>; + clock-names = "iface_clk", "ref_clk", "ref_clk_src"; + clock-rate = <0>; + + qcom,platform-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,platform-supply-entry@0 { + reg = <0>; + qcom,supply-name = "gdsc"; + qcom,supply-min-voltage = <0>; + qcom,supply-max-voltage = <0>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + }; + qcom,platform-supply-entry@1 { + reg = <1>; + qcom,supply-name = "vdda-pll"; + qcom,supply-min-voltage = <1200000>; + qcom,supply-max-voltage = <1200000>; + qcom,supply-enable-load = <14200>; + qcom,supply-disable-load = <1>; + }; + + qcom,platform-supply-entry@2 { + reg = <2>; + qcom,supply-name = "vdda-phy"; + qcom,supply-min-voltage = <1800000>; + qcom,supply-max-voltage = <1800000>; + qcom,supply-enable-load = <13100>; + qcom,supply-disable-load = <4>; + }; + }; + }; +}; --- /dev/null 2019-10-24 16:47:25.704025805 +0200 +++ linux-4.4.115-fbx/arch/arm64/boot/dts/qcom/msm8998-pinctrl.dtsi 2019-01-22 16:16:21.195225506 +0100 @@ -0,0 +1,2460 @@ +/* Copyright (c) 2015-2017, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&soc { + tlmm: pinctrl@03400000 { + compatible = "qcom,msm8998-pinctrl"; + reg = <0x03400000 0xc00000>; + interrupts = <0 208 0>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + + uart_console_active: uart_console_active { + mux { + pins = "gpio4", "gpio5"; + function = "blsp_uart8_a"; + }; + + config { + pins = "gpio4", "gpio5"; + drive-strength = <2>; + bias-disable; + }; + }; + + /* HS UART CONFIGURATION */ + blsp1_uart1_active: blsp1_uart1_active { + mux { + pins = "gpio0", "gpio1", "gpio2", "gpio3"; + function = "blsp_uart1_a"; + }; + + config { + pins = "gpio0", "gpio1", "gpio2", "gpio3"; + drive-strength = <2>; + bias-disable; + }; + }; + + blsp1_uart1_sleep: blsp1_uart1_sleep { + mux { + pins = "gpio0", "gpio1", "gpio2", "gpio3"; + function = "gpio"; + }; + + config { + pins = "gpio0", "gpio1", "gpio2", "gpio3"; + drive-strength = <2>; + bias-disable; + }; + }; + + blsp1_uart2_active: blsp1_uart2_active { + mux { + pins = "gpio31", "gpio34", "gpio33", "gpio32"; + function = "blsp_uart2_a"; + }; + + config { + pins = "gpio31", "gpio34", "gpio33", "gpio32"; + drive-strength = <2>; + bias-disable; + }; + }; + + blsp1_uart2_sleep: blsp1_uart2_sleep { + mux { + pins = "gpio31", "gpio34", "gpio33", "gpio32"; + function = "gpio"; + }; + + config { + pins = "gpio31", "gpio34", "gpio33", "gpio32"; + drive-strength = <2>; + bias-disable; + }; + }; + + blsp1_uart3: blsp1_uart3 { + blsp1_uart3_tx_active: blsp1_uart3_tx_active { + mux { + pins = "gpio45"; + function = "blsp_uart3_a"; + }; + + config { + pins = "gpio45"; + drive-strength = <2>; + bias-disable; + }; + }; + + blsp1_uart3_tx_sleep: blsp1_uart3_tx_sleep { + mux { + pins = "gpio45"; + function = "gpio"; + }; + + config { + pins = "gpio45"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + blsp1_uart3_rxcts_active: blsp1_uart3_rxcts_active { + mux { + pins = "gpio46", "gpio47"; + function = "blsp_uart3_a"; + }; + + config { + pins = "gpio46", "gpio47"; + drive-strength = <2>; + bias-disable; + }; + }; + + blsp1_uart3_rxcts_sleep: blsp1_uart3_rxcts_sleep { + mux { + pins = "gpio46", "gpio47"; + function = "gpio"; + }; + + config { + pins = "gpio46", "gpio47"; + drive-strength = <2>; + bias-no-pull; + }; + }; + + blsp1_uart3_rfr_active: blsp1_uart3_rfr_active { + mux { + pins = "gpio48"; + function = "blsp_uart3_a"; + }; + + config { + pins = "gpio48"; + drive-strength = <2>; + bias-disable; + }; + }; + + blsp1_uart3_rfr_sleep: blsp1_uart3_rfr_sleep { + mux { + pins = "gpio48"; + function = "gpio"; + }; + + config { + pins = "gpio48"; + drive-strength = <2>; + bias-no-pull; + }; + }; + }; + + blsp2_uart1_active: blsp2_uart1_active { + mux { + pins = "gpio53", "gpio54", "gpio55", "gpio56"; + function = "blsp_uart7_a"; + }; + + config { + pins = "gpio53", "gpio54", "gpio55", "gpio56"; + drive-strength = <2>; + bias-disable; + }; + }; + + blsp2_uart1_sleep: blsp2_uart1_sleep { + mux { + pins = "gpio53", "gpio54", "gpio55", "gpio56"; + function = "gpio"; + }; + + config { + pins = "gpio53", "gpio54", "gpio55", "gpio56"; + drive-strength = <2>; + bias-disable; + }; + }; + + blsp2_uart2_active: blsp2_uart2_active { + mux { + pins = "gpio4", "gpio5", "gpio6", "gpio7"; + function = "blsp_uart8_a"; + }; + + config { + pins = "gpio4", "gpio5", "gpio6", "gpio7"; + drive-strength = <2>; + bias-disable; + }; + }; + + blsp2_uart2_sleep: blsp2_uart2_sleep { + mux { + pins = "gpio4", "gpio5", "gpio6", "gpio7"; + function = "gpio"; + }; + + config { + pins = "gpio4", "gpio5", "gpio6", "gpio7"; + drive-strength = <2>; + bias-disable; + }; + }; + + blsp2_uart3_active: blsp2_uart3_active { + mux { + pins = "gpio49", "gpio50", "gpio51", "gpio52"; + function = "blsp_uart9_a"; + }; + + config { + pins = "gpio49", "gpio50", "gpio51", "gpio52"; + drive-strength = <2>; + bias-disable; + }; + }; + + blsp2_uart3_sleep: blsp2_uart3_sleep { + mux { + pins = "gpio49", "gpio50", "gpio51", "gpio52"; + function = "gpio"; + }; + + config { + pins = "gpio49", "gpio50", "gpio51", "gpio52"; + drive-strength = <2>; + bias-disable; + }; + }; + + /* PCIE CONFIGURATION */ + + pcie0 { + pcie0_clkreq_default: pcie0_clkreq_default { + mux { + pins = "gpio36"; + function = "pci_e0"; + }; + + config { + pins = "gpio36"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + pcie0_perst_default: pcie0_perst_default { + mux { + pins = "gpio35"; + function = "gpio"; + }; + + config { + pins = "gpio35"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + pcie0_wake_default: pcie0_wake_default { + mux { + pins = "gpio37"; + function = "gpio"; + }; + + config { + pins = "gpio37"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + pcie0_wake_sleep: pcie0_wake_sleep { + mux { + pins = "gpio37"; + function = "gpio"; + }; + + config { + pins = "gpio37"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + /* I2C CONFIGURATION */ + i2c_1 { + i2c_1_active: i2c_1_active { + mux { + pins = "gpio2", "gpio3"; + function = "blsp_i2c1"; + }; + + config { + pins = "gpio2", "gpio3"; + drive-strength = <2>; + bias-disable; + }; + }; + + i2c_1_sleep: i2c_1_sleep { + mux { + pins = "gpio2", "gpio3"; + function = "blsp_i2c1"; + }; + + config { + pins = "gpio2", "gpio3"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + i2c_2 { + i2c_2_active: i2c_2_active { + mux { + pins = "gpio32", "gpio33"; + function = "blsp_i2c2"; + }; + + config { + pins = "gpio32", "gpio33"; + drive-strength = <2>; + bias-disable; + }; + }; + + i2c_2_sleep: i2c_2_sleep { + mux { + pins = "gpio32", "gpio33"; + function = "blsp_i2c2"; + }; + + config { + pins = "gpio32", "gpio33"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + i2c_3 { + i2c_3_active: i2c_3_active { + mux { + pins = "gpio47", "gpio48"; + function = "blsp_i2c3"; + }; + + config { + pins = "gpio47", "gpio48"; + drive-strength = <2>; + bias-disable; + }; + }; + + i2c_3_sleep: i2c_3_sleep { + mux { + pins = "gpio47", "gpio48"; + function = "blsp_i2c3"; + }; + + config { + pins = "gpio47", "gpio48"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + i2c_4 { + i2c_4_active: i2c_4_active { + mux { + pins = "gpio10", "gpio11"; + function = "blsp_i2c4"; + }; + + config { + pins = "gpio10", "gpio11"; + drive-strength = <2>; + bias-disable; + }; + }; + + i2c_4_sleep: i2c_4_sleep { + mux { + pins = "gpio10", "gpio11"; + function = "blsp_i2c4"; + }; + + config { + pins = "gpio10", "gpio11"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + i2c_5 { + i2c_5_active: i2c_5_active { + mux { + pins = "gpio87", "gpio88"; + function = "blsp_i2c5"; + }; + + config { + pins = "gpio87", "gpio88"; + drive-strength = <2>; + bias-disable; + }; + }; + + i2c_5_sleep: i2c_5_sleep { + mux { + pins = "gpio87", "gpio88"; + function = "blsp_i2c5"; + }; + + config { + pins = "gpio87", "gpio88"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + i2c_6 { + i2c_6_active: i2c_6_active { + mux { + pins = "gpio43", "gpio44"; + function = "blsp_i2c6"; + }; + + config { + pins = "gpio43", "gpio44"; + drive-strength = <2>; + bias-disable; + }; + }; + + i2c_6_sleep: i2c_6_sleep { + mux { + pins = "gpio43", "gpio44"; + function = "blsp_i2c6"; + }; + + config { + pins = "gpio43", "gpio44"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + i2c_7 { + i2c_7_active: i2c_7_active { + mux { + pins = "gpio55", "gpio56"; + function = "blsp_i2c7"; + }; + + config { + pins = "gpio55", "gpio56"; + drive-strength = <2>; + bias-disable; + }; + }; + + i2c_7_sleep: i2c_7_sleep { + mux { + pins = "gpio55", "gpio56"; + function = "blsp_i2c7"; + }; + + config { + pins = "gpio55", "gpio56"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + i2c_8 { + i2c_8_active: i2c_8_active { + mux { + pins = "gpio6", "gpio7"; + function = "blsp_i2c8"; + }; + + config { + pins = "gpio6", "gpio7"; + drive-strength = <2>; + bias-disable; + }; + }; + + i2c_8_sleep: i2c_8_sleep { + mux { + pins = "gpio6", "gpio7"; + function = "blsp_i2c8"; + }; + + config { + pins = "gpio6", "gpio7"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + i2c_9 { + i2c_9_active: i2c_9_active { + mux { + pins = "gpio51", "gpio52"; + function = "blsp_i2c9"; + }; + + config { + pins = "gpio51", "gpio52"; + drive-strength = <2>; + bias-disable; + }; + }; + + i2c_9_sleep: i2c_9_sleep { + mux { + pins = "gpio51", "gpio52"; + function = "blsp_i2c9"; + }; + + config { + pins = "gpio51", "gpio52"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + i2c_10 { + i2c_10_active: i2c_10_active { + mux { + pins = "gpio67", "gpio68"; + function = "blsp_i2c10"; + }; + + config { + pins = "gpio67", "gpio68"; + drive-strength = <2>; + bias-disable; + }; + }; + + i2c_10_sleep: i2c_10_sleep { + mux { + pins = "gpio67", "gpio68"; + function = "blsp_i2c10"; + }; + + config { + pins = "gpio67", "gpio68"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + i2c_11 { + i2c_11_active: i2c_11_active { + mux { + pins = "gpio60", "gpio61"; + function = "blsp_i2c11"; + }; + + config { + pins = "gpio60", "gpio61"; + drive-strength = <2>; + bias-disable; + }; + }; + + i2c_11_sleep: i2c_11_sleep { + mux { + pins = "gpio60", "gpio61"; + function = "blsp_i2c11"; + }; + + config { + pins = "gpio60", "gpio61"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + i2c_12 { + i2c_12_active: i2c_12_active { + mux { + pins = "gpio83", "gpio84"; + function = "blsp_i2c12"; + }; + + config { + pins = "gpio83", "gpio84"; + drive-strength = <2>; + bias-disable; + }; + }; + + i2c_12_sleep: i2c_12_sleep { + mux { + pins = "gpio83", "gpio84"; + function = "blsp_i2c12"; + }; + + config { + pins = "gpio83", "gpio84"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + /* SPI CONFIGURATION */ + + spi_1 { + spi_1_active: spi_1_active { + mux { + pins = "gpio0", "gpio1", + "gpio2", "gpio3"; + function = "blsp_spi1"; + }; + + config { + pins = "gpio0", "gpio1", + "gpio2", "gpio3"; + drive-strength = <6>; + bias-disable; + }; + }; + + spi_1_sleep: spi_1_sleep { + mux { + pins = "gpio0", "gpio1", + "gpio2", "gpio3"; + function = "blsp_spi1"; + }; + + config { + pins = "gpio0", "gpio1", + "gpio2", "gpio3"; + drive-strength = <6>; + bias-disable; + }; + }; + + spi_1b_active: spi_1b_active { + mux { + pins = "gpio23", "gpio28"; + function = "blsp1_spi_b"; + }; + + config { + pins = "gpio23", "gpio28"; + drive-strength = <6>; + bias-disable; + }; + }; + + spi_1b_sleep: spi_1b_sleep { + mux { + pins = "gpio23", "gpio28"; + function = "blsp1_spi_b"; + }; + + config { + pins = "gpio23", "gpio28"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + spi_2 { + spi_2_active: spi_2_active { + mux { + pins = "gpio31", "gpio34", + "gpio32", "gpio33"; + function = "blsp_spi2"; + }; + + config { + pins = "gpio31", "gpio34", + "gpio32", "gpio33"; + drive-strength = <6>; + bias-disable; + }; + }; + + spi_2_sleep: spi_2_sleep { + mux { + pins = "gpio31", "gpio34", + "gpio32", "gpio33"; + function = "blsp_spi2"; + }; + + config { + pins = "gpio31", "gpio34", + "gpio32", "gpio33"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + spi_3 { + spi_3_active: spi_3_active { + mux { + pins = "gpio45", "gpio46", + "gpio47", "gpio48"; + function = "blsp_spi3"; + }; + + config { + pins = "gpio45", "gpio46", + "gpio47", "gpio48"; + drive-strength = <6>; + bias-disable; + }; + }; + + spi_3_sleep: spi_3_sleep { + mux { + pins = "gpio45", "gpio46", + "gpio47", "gpio48"; + function = "blsp_spi3"; + }; + + config { + pins = "gpio45", "gpio46", + "gpio47", "gpio48"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + spi_4 { + spi_4_active: spi_4_active { + mux { + pins = "gpio8", "gpio9", + "gpio10", "gpio11"; + function = "blsp_spi4"; + }; + + config { + pins = "gpio8", "gpio9", + "gpio10", "gpio11"; + drive-strength = <6>; + bias-disable; + }; + }; + + spi_4_sleep: spi_4_sleep { + mux { + pins = "gpio8", "gpio9", + "gpio10", "gpio11"; + function = "blsp_spi4"; + }; + + config { + pins = "gpio8", "gpio9", + "gpio10", "gpio11"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + spi_5 { + spi_5_active: spi_5_active { + mux { + pins = "gpio85", "gpio86", + "gpio87", "gpio88"; + function = "blsp_spi5"; + }; + + config { + pins = "gpio85", "gpio86", + "gpio87", "gpio88"; + drive-strength = <6>; + bias-disable; + }; + }; + + spi_5_sleep: spi_5_sleep { + mux { + pins = "gpio85", "gpio86", + "gpio87", "gpio88"; + function = "blsp_spi5"; + }; + + config { + pins = "gpio85", "gpio86", + "gpio87", "gpio88"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + spi_6 { + spi_6_active: spi_6_active { + mux { + pins = "gpio41", "gpio42", + "gpio43", "gpio44"; + function = "blsp_spi6"; + }; + + config { + pins = "gpio41", "gpio42", + "gpio43", "gpio44"; + drive-strength = <6>; + bias-disable; + }; + }; + + spi_6_sleep: spi_6_sleep { + mux { + pins = "gpio41", "gpio42", + "gpio43", "gpio44"; + function = "blsp_spi6"; + }; + + config { + pins = "gpio41", "gpio42", + "gpio43", "gpio44"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + spi_7 { + spi_7_active: spi_7_active { + mux { + pins = "gpio53", "gpio54", + "gpio55", "gpio56"; + function = "blsp_spi7"; + }; + + config { + pins = "gpio53", "gpio54", + "gpio55", "gpio56"; + drive-strength = <6>; + bias-disable; + }; + }; + + spi_7_sleep: spi_7_sleep { + mux { + pins = "gpio53", "gpio54", + "gpio55", "gpio56"; + function = "blsp_spi7"; + }; + + config { + pins = "gpio53", "gpio54", + "gpio55", "gpio56"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + spi_8 { + spi_8_active: spi_8_active { + mux { + pins = "gpio4", "gpio5", + "gpio6", "gpio7"; + function = "blsp_spi8"; + }; + + config { + pins = "gpio4", "gpio5", + "gpio6", "gpio7"; + drive-strength = <6>; + bias-disable; + }; + }; + + spi_8_sleep: spi_8_sleep { + mux { + pins = "gpio4", "gpio5", + "gpio6", "gpio7"; + function = "blsp_spi8"; + }; + + config { + pins = "gpio4", "gpio5", + "gpio6", "gpio7"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + spi_9 { + spi_9_active: spi_9_active { + mux { + pins = "gpio49", "gpio50", + "gpio51", "gpio52"; + function = "blsp_spi9"; + }; + + config { + pins = "gpio49", "gpio50", + "gpio51", "gpio52"; + drive-strength = <6>; + bias-disable; + }; + }; + + spi_9_sleep: spi_9_sleep { + mux { + pins = "gpio49", "gpio50", + "gpio51", "gpio52"; + function = "blsp_spi9"; + }; + + config { + pins = "gpio49", "gpio50", + "gpio51", "gpio52"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + spi_10 { + spi_10_active: spi_10_active { + mux { + pins = "gpio65", "gpio66", + "gpio67", "gpio68"; + function = "blsp_spi10"; + }; + + config { + pins = "gpio65", "gpio66", + "gpio67", "gpio68"; + drive-strength = <6>; + bias-disable; + }; + }; + + spi_10_sleep: spi_10_sleep { + mux { + pins = "gpio65", "gpio66", + "gpio67", "gpio68"; + function = "blsp_spi10"; + }; + + config { + pins = "gpio65", "gpio66", + "gpio67", "gpio68"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + spi_11 { + spi_11_active: spi_11_active { + mux { + pins = "gpio58", "gpio59", + "gpio60", "gpio61"; + function = "blsp_spi11"; + }; + + config { + pins = "gpio58", "gpio59", + "gpio60", "gpio61"; + drive-strength = <6>; + bias-disable; + }; + }; + + spi_11_sleep: spi_11_sleep { + mux { + pins = "gpio58", "gpio59", + "gpio60", "gpio61"; + function = "blsp_spi11"; + }; + + config { + pins = "gpio58", "gpio59", + "gpio60", "gpio61"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + spi_12 { + spi_12_active: spi_12_active { + mux { + pins = "gpio81", "gpio82", + "gpio83", "gpio84"; + function = "blsp_spi12"; + }; + + config { + pins = "gpio81", "gpio82", + "gpio83", "gpio84"; + drive-strength = <6>; + bias-disable; + }; + }; + + spi_12_sleep: spi_12_sleep { + mux { + pins = "gpio81", "gpio82", + "gpio83", "gpio84"; + function = "blsp_spi12"; + }; + + config { + pins = "gpio81", "gpio82", + "gpio83", "gpio84"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + /* CAMERA CONFIGURATION */ + + cci0_active: cci0_active { + mux { + /* CLK, DATA */ + pins = "gpio17","gpio18"; // Only 2 + function = "cci_i2c"; + }; + + config { + pins = "gpio17","gpio18"; + bias-pull-up; /* PULL UP*/ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci0_suspend: cci0_suspend { + mux { + /* CLK, DATA */ + pins = "gpio17","gpio18"; + function = "cci_i2c"; + }; + + config { + pins = "gpio17","gpio18"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci1_active: cci1_active { + mux { + /* CLK, DATA */ + pins = "gpio19","gpio20"; + function = "cci_i2c"; + }; + + config { + pins = "gpio19","gpio20"; + bias-pull-up; /* PULL UP*/ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci1_suspend: cci1_suspend { + mux { + /* CLK, DATA */ + pins = "gpio19","gpio20"; + function = "cci_i2c"; + }; + + config { + pins = "gpio19","gpio20"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + /* MDSS CONFIGURATION */ + + mdss_dp_aux_active: mdss_dp_aux_active { + mux { + pins = "gpio77", "gpio78"; + function = "gpio"; + }; + + config { + pins = "gpio77", "gpio78"; + bias-disable = <0>; /* no pull */ + drive-strength = <8>; + }; + }; + + mdss_dp_aux_suspend: mdss_dp_aux_suspend { + mux { + pins = "gpio77", "gpio78"; + function = "gpio"; + }; + + config { + pins = "gpio77", "gpio78"; + bias-pull-down; + drive-strength = <2>; + }; + }; + + mdss_dp_usbplug_cc_active: mdss_dp_usbplug_cc_active { + mux { + pins = "gpio38"; + function = "gpio"; + }; + + config { + pins = "gpio38"; + bias-disable; + drive-strength = <16>; + }; + }; + + mdss_dp_usbplug_cc_suspend: mdss_dp_usbplug_cc_suspend { + mux { + pins = "gpio38"; + function = "gpio"; + }; + + config { + pins = "gpio38"; + bias-pull-down; + drive-strength = <2>; + }; + }; + + mdss_dp_hpd_active: mdss_dp_hpd_active { + mux { + pins = "gpio34"; + function = "edp_hot"; + }; + + config { + pins = "gpio34"; + bias-pull-down; + drive-strength = <16>; + }; + }; + + mdss_dp_hpd_suspend: mdss_dp_hpd_suspend { + mux { + pins = "gpio34"; + function = "edp_hot"; + }; + + config { + pins = "gpio34"; + bias-pull-down; + drive-strength = <2>; + }; + }; + + mdss_hdmi_5v_active: mdss_hdmi_5v_active { + mux { + pins = "gpio133"; + function = "gpio"; + }; + + config { + pins = "gpio133"; + bias-pull-up; + drive-strength = <16>; + }; + }; + + mdss_hdmi_5v_suspend: mdss_hdmi_5v_suspend { + mux { + pins = "gpio133"; + function = "gpio"; + }; + + config { + pins = "gpio133"; + bias-pull-down; + drive-strength = <2>; + }; + }; + + mdss_hdmi_hpd_active: mdss_hdmi_hpd_active { + mux { + pins = "gpio34"; + function = "hdmi_hot"; + }; + + config { + pins = "gpio34"; + bias-pull-down; + drive-strength = <16>; + }; + }; + + mdss_hdmi_hpd_suspend: mdss_hdmi_hpd_suspend { + mux { + pins = "gpio34"; + function = "hdmi_hot"; + }; + + config { + pins = "gpio34"; + bias-pull-down; + drive-strength = <2>; + }; + }; + + mdss_hdmi_ddc_active: mdss_hdmi_ddc_active { + mux { + pins = "gpio32", "gpio33"; + function = "hdmi_ddc"; + }; + + config { + pins = "gpio32", "gpio33"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + mdss_hdmi_ddc_suspend: mdss_hdmi_ddc_suspend { + mux { + pins = "gpio32", "gpio33"; + function = "hdmi_ddc"; + }; + + config { + pins = "gpio32", "gpio33"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + mdss_hdmi_cec_active: mdss_hdmi_cec_active { + mux { + pins = "gpio31"; + function = "hdmi_cec"; + }; + + config { + pins = "gpio31"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + mdss_hdmi_cec_suspend: mdss_hdmi_cec_suspend { + mux { + pins = "gpio31"; + function = "hdmi_cec"; + }; + + config { + pins = "gpio31"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + /* UFS CONFIGURATION */ + + ufs_dev_reset_assert: ufs_dev_reset_assert { + config { + pins = "ufs_reset"; + bias-pull-down; /* default: pull down */ + /* + * UFS_RESET driver strengths are having + * different values/steps compared to typical + * GPIO drive strengths. + * + * Following table clarifies: + * + * HDRV value | UFS_RESET | Typical GPIO + * (dec) | (mA) | (mA) + * 0 | 0.8 | 2 + * 1 | 1.55 | 4 + * 2 | 2.35 | 6 + * 3 | 3.1 | 8 + * 4 | 3.9 | 10 + * 5 | 4.65 | 12 + * 6 | 5.4 | 14 + * 7 | 6.15 | 16 + * + * POR value for UFS_RESET HDRV is 3 which means + * 3.1mA and we want to use that. Hence just + * specify 8mA to "drive-strength" binding and + * that should result into writing 3 to HDRV + * field. + */ + drive-strength = <8>; /* default: 3.1 mA */ + output-low; /* active low reset */ + }; + }; + + ufs_dev_reset_deassert: ufs_dev_reset_deassert { + config { + pins = "ufs_reset"; + bias-pull-down; /* default: pull down */ + /* + * default: 3.1 mA + * check comments under ufs_dev_reset_assert + */ + drive-strength = <8>; + output-high; /* active low reset */ + }; + }; + + /* SHDCI CONFIGURATION */ + + sdc2_clk_on: sdc2_clk_on { + config { + pins = "sdc2_clk"; + bias-disable; /* NO pull */ + drive-strength = <16>; /* 16 MA */ + }; + }; + + sdc2_clk_off: sdc2_clk_off { + config { + pins = "sdc2_clk"; + bias-disable; /* NO pull */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + sdc2_cmd_on: sdc2_cmd_on { + config { + pins = "sdc2_cmd"; + bias-pull-up; /* pull up */ + drive-strength = <10>; /* 10 MA */ + }; + }; + + sdc2_cmd_off: sdc2_cmd_off { + config { + pins = "sdc2_cmd"; + bias-pull-up; /* pull up */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + sdc2_data_on: sdc2_data_on { + config { + pins = "sdc2_data"; + bias-pull-up; /* pull up */ + drive-strength = <10>; /* 10 MA */ + }; + }; + + sdc2_data_off: sdc2_data_off { + config { + pins = "sdc2_data"; + bias-pull-up; /* pull up */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + sdc2_cd_on: sdc2_cd_on { + mux { + pins = "gpio95"; + function = "gpio"; + }; + + config { + pins = "gpio95"; + bias-pull-up; /* pull up */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + sdc2_cd_off: sdc2_cd_off { + mux { + pins = "gpio95"; + function = "gpio"; + }; + + config { + pins = "gpio95"; + bias-pull-up; /* pull up */ + drive-strength = <2>; /* 2 MA */ + }; + + }; + + /* CORESIGHT */ + + trigout_a: trigout_a { + mux { + pins = "gpio58"; + function = "qdss_cti1_a"; + }; + + config { + pins = "gpio58"; + drive-strength = <2>; + bias-disable; + }; + }; + + /* TSPP CONFIGURATION */ + + tsif0_signals_active: tsif0_signals_active { + tsif1_clk { + pins = "gpio89"; /* TSIF0 CLK */ + function = "tsif1_clk"; + }; + tsif1_en { + pins = "gpio90"; /* TSIF0 Enable */ + function = "tsif1_en"; + }; + tsif1_data { + pins = "gpio91"; /* TSIF0 DATA */ + function = "tsif1_data"; + }; + signals_cfg { + pins = "gpio89", "gpio90", "gpio91"; + drive_strength = <2>; /* 2 mA */ + bias-pull-down; /* pull down */ + }; + }; + + tsif0_sync_active: tsif0_sync_active { + tsif1_sync { + pins = "gpio9"; /* TSIF0 SYNC */ + function = "tsif1_sync"; + drive_strength = <2>; /* 2 mA */ + bias-pull-down; /* pull down */ + }; + }; + + tsif1_signals_active: tsif1_signals_active { + tsif2_clk { + pins = "gpio93"; /* TSIF1 CLK */ + function = "tsif2_clk"; + }; + tsif2_en { + pins = "gpio94"; /* TSIF1 Enable */ + function = "tsif2_en"; + }; + tsif2_data { + pins = "gpio95"; /* TSIF1 DATA */ + function = "tsif2_data"; + }; + signals_cfg { + pins = "gpio93", "gpio94", "gpio95"; + drive_strength = <2>; /* 2 mA */ + bias-pull-down; /* pull down */ + }; + }; + + tsif1_sync_active: tsif1_sync_active { + tsif2_sync { + pins = "gpio96"; /* TSIF1 SYNC */ + function = "tsif2_sync"; + drive_strength = <2>; /* 2 mA */ + bias-pull-down; /* pull down */ + }; + }; + + /* DIGITAL AUDIO CONFIGURATION */ + + pri_aux_pcm_clk { + pri_aux_pcm_clk_sleep: pri_aux_pcm_clk_sleep { + mux { + pins = "gpio65"; + function = "gpio"; + }; + + config { + pins = "gpio65"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + pri_aux_pcm_clk_active: pri_aux_pcm_clk_active { + mux { + pins = "gpio65"; + function = "pri_mi2s"; + }; + + config { + pins = "gpio65"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + pri_aux_pcm_sync { + pri_aux_pcm_sync_sleep: pri_aux_pcm_sync_sleep { + mux { + pins = "gpio66"; + function = "gpio"; + }; + + config { + pins = "gpio66"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + pri_aux_pcm_sync_active: pri_aux_pcm_sync_active { + mux { + pins = "gpio66"; + function = "pri_mi2s_ws"; + }; + + config { + pins = "gpio66"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + pri_aux_pcm_din { + pri_aux_pcm_din_sleep: pri_aux_pcm_din_sleep { + mux { + pins = "gpio67"; + function = "gpio"; + }; + + config { + pins = "gpio67"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + pri_aux_pcm_din_active: pri_aux_pcm_din_active { + mux { + pins = "gpio67"; + function = "pri_mi2s"; + }; + + config { + pins = "gpio67"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + pri_aux_pcm_dout { + pri_aux_pcm_dout_sleep: pri_aux_pcm_dout_sleep { + mux { + pins = "gpio68"; + function = "gpio"; + }; + + config { + pins = "gpio68"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + pri_aux_pcm_dout_active: pri_aux_pcm_dout_active { + mux { + pins = "gpio68"; + function = "pri_mi2s"; + }; + + config { + pins = "gpio68"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + sec_aux_pcm { + sec_aux_pcm_sleep: sec_aux_pcm_sleep { + mux { + pins = "gpio80", "gpio81"; + function = "gpio"; + }; + + config { + pins = "gpio80", "gpio81"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + sec_aux_pcm_active: sec_aux_pcm_active { + mux { + pins = "gpio80", "gpio81"; + function = "sec_mi2s"; + }; + + config { + pins = "gpio80", "gpio81"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + sec_aux_pcm_din { + sec_aux_pcm_din_sleep: sec_aux_pcm_din_sleep { + mux { + pins = "gpio82"; + function = "gpio"; + }; + + config { + pins = "gpio82"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + sec_aux_pcm_din_active: sec_aux_pcm_din_active { + mux { + pins = "gpio82"; + function = "sec_mi2s"; + }; + + config { + pins = "gpio82"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + sec_aux_pcm_dout { + sec_aux_pcm_dout_sleep: sec_aux_pcm_dout_sleep { + mux { + pins = "gpio83"; + function = "gpio"; + }; + + config { + pins = "gpio83"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + sec_aux_pcm_dout_active: sec_aux_pcm_dout_active { + mux { + pins = "gpio83"; + function = "sec_mi2s"; + }; + + config { + pins = "gpio83"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + tert_aux_pcm { + tert_aux_pcm_sleep: tert_aux_pcm_sleep { + mux { + pins = "gpio75", "gpio76"; + function = "gpio"; + }; + + config { + pins = "gpio75", "gpio76"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + tert_aux_pcm_active: tert_aux_pcm_active { + mux { + pins = "gpio75", "gpio76"; + function = "ter_mi2s"; + }; + + config { + pins = "gpio75", "gpio76"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + tert_aux_pcm_din { + tert_aux_pcm_din_sleep: tert_aux_pcm_din_sleep { + mux { + pins = "gpio77"; + function = "gpio"; + }; + + config { + pins = "gpio77"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + tert_aux_pcm_din_active: tert_aux_pcm_din_active { + mux { + pins = "gpio77"; + function = "ter_mi2s"; + }; + + config { + pins = "gpio77"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + tert_aux_pcm_dout { + tert_aux_pcm_dout_sleep: tert_aux_pcm_dout_sleep { + mux { + pins = "gpio78"; + function = "gpio"; + }; + + config { + pins = "gpio78"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + tert_aux_pcm_dout_active: tert_aux_pcm_dout_active { + mux { + pins = "gpio78"; + function = "ter_mi2s"; + }; + + config { + pins = "gpio78"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + quat_aux_pcm { + quat_aux_pcm_sleep: quat_aux_pcm_sleep { + mux { + pins = "gpio58", "gpio59"; + function = "gpio"; + }; + + config { + pins = "gpio58", "gpio59"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + quat_aux_pcm_active: quat_aux_pcm_active { + mux { + pins = "gpio58", "gpio59"; + function = "qua_mi2s"; + }; + + config { + pins = "gpio58", "gpio59"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + quat_aux_pcm_din { + quat_aux_pcm_din_sleep: quat_aux_pcm_din_sleep { + mux { + pins = "gpio60"; + function = "gpio"; + }; + + config { + pins = "gpio60"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + quat_aux_pcm_din_active: quat_aux_pcm_din_active { + mux { + pins = "gpio60"; + function = "qua_mi2s"; + }; + + config { + pins = "gpio60"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + quat_aux_pcm_dout { + quat_aux_pcm_dout_sleep: quat_aux_pcm_dout_sleep { + mux { + pins = "gpio61"; + function = "gpio"; + }; + + config { + pins = "gpio61"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + quat_aux_pcm_dout_active: quat_aux_pcm_dout_active { + mux { + pins = "gpio61"; + function = "qua_mi2s"; + }; + + config { + pins = "gpio61"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + pri_mi2s_mclk { + pri_mi2s_mclk_sleep: pri_mi2s_mclk_sleep { + mux { + pins = "gpio64"; + function = "gpio"; + }; + + config { + pins = "gpio64"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + pri_mi2s_mclk_active: pri_mi2s_mclk_active { + mux { + pins = "gpio64"; + function = "pri_mi2s"; + }; + + config { + pins = "gpio64"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + pri_mi2s_sck { + pri_mi2s_sck_sleep: pri_mi2s_sck_sleep { + mux { + pins = "gpio65"; + function = "gpio"; + }; + + config { + pins = "gpio65"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + pri_mi2s_sck_active: pri_mi2s_sck_active { + mux { + pins = "gpio65"; + function = "pri_mi2s"; + }; + + config { + pins = "gpio65"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + pri_mi2s_ws { + pri_mi2s_ws_sleep: pri_mi2s_ws_sleep { + mux { + pins = "gpio66"; + function = "gpio"; + }; + + config { + pins = "gpio66"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + pri_mi2s_ws_active: pri_mi2s_ws_active { + mux { + pins = "gpio66"; + function = "pri_mi2s_ws"; + }; + + config { + pins = "gpio66"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + pri_mi2s_sd0 { + pri_mi2s_sd0_sleep: pri_mi2s_sd0_sleep { + mux { + pins = "gpio67"; + function = "gpio"; + }; + + config { + pins = "gpio67"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + pri_mi2s_sd0_active: pri_mi2s_sd0_active { + mux { + pins = "gpio67"; + function = "pri_mi2s"; + }; + + config { + pins = "gpio67"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + pri_mi2s_sd1 { + pri_mi2s_sd1_sleep: pri_mi2s_sd1_sleep { + mux { + pins = "gpio68"; + function = "gpio"; + }; + + config { + pins = "gpio68"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + pri_mi2s_sd1_active: pri_mi2s_sd1_active { + mux { + pins = "gpio68"; + function = "pri_mi2s"; + }; + + config { + pins = "gpio68"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + sec_mi2s_mclk { + sec_mi2s_mclk_sleep: sec_mi2s_mclk_sleep { + mux { + pins = "gpio79"; + function = "gpio"; + }; + + config { + pins = "gpio79"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + sec_mi2s_mclk_active: sec_mi2s_mclk_active { + mux { + pins = "gpio79"; + function = "sec_mi2s"; + }; + + config { + pins = "gpio79"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + sec_mi2s { + sec_mi2s_sleep: sec_mi2s_sleep { + mux { + pins = "gpio80", "gpio81"; + function = "gpio"; + }; + + config { + pins = "gpio80", "gpio81"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + sec_mi2s_active: sec_mi2s_active { + mux { + pins = "gpio80", "gpio81"; + function = "sec_mi2s"; + }; + + config { + pins = "gpio80", "gpio81"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + sec_mi2s_sd0 { + sec_mi2s_sd0_sleep: sec_mi2s_sd0_sleep { + mux { + pins = "gpio82"; + function = "gpio"; + }; + + config { + pins = "gpio82"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + sec_mi2s_sd0_active: sec_mi2s_sd0_active { + mux { + pins = "gpio82"; + function = "sec_mi2s"; + }; + + config { + pins = "gpio82"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + sec_mi2s_sd1 { + sec_mi2s_sd1_sleep: sec_mi2s_sd1_sleep { + mux { + pins = "gpio83"; + function = "gpio"; + }; + + config { + pins = "gpio83"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + sec_mi2s_sd1_active: sec_mi2s_sd1_active { + mux { + pins = "gpio83"; + function = "sec_mi2s"; + }; + + config { + pins = "gpio83"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + tert_mi2s_mclk { + tert_mi2s_mclk_sleep: tert_mi2s_mclk_sleep { + mux { + pins = "gpio74"; + function = "gpio"; + }; + + config { + pins = "gpio74"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + tert_mi2s_mclk_active: tert_mi2s_mclk_active { + mux { + pins = "gpio74"; + function = "ter_mi2s"; + }; + + config { + pins = "gpio74"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + tert_mi2s { + tert_mi2s_sleep: tert_mi2s_sleep { + mux { + pins = "gpio75", "gpio76"; + function = "gpio"; + }; + + config { + pins = "gpio75", "gpio76"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + tert_mi2s_active: tert_mi2s_active { + mux { + pins = "gpio75", "gpio76"; + function = "ter_mi2s"; + }; + + config { + pins = "gpio75", "gpio76"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + tert_mi2s_sd0 { + tert_mi2s_sd0_sleep: tert_mi2s_sd0_sleep { + mux { + pins = "gpio77"; + function = "gpio"; + }; + + config { + pins = "gpio77"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + tert_mi2s_sd0_active: tert_mi2s_sd0_active { + mux { + pins = "gpio77"; + function = "ter_mi2s"; + }; + + config { + pins = "gpio77"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + tert_mi2s_sd1 { + tert_mi2s_sd1_sleep: tert_mi2s_sd1_sleep { + mux { + pins = "gpio78"; + function = "gpio"; + }; + + config { + pins = "gpio78"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + tert_mi2s_sd1_active: tert_mi2s_sd1_active { + mux { + pins = "gpio78"; + function = "ter_mi2s"; + }; + + config { + pins = "gpio78"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + quat_mi2s_mclk { + quat_mi2s_mclk_sleep: quat_mi2s_mclk_sleep { + mux { + pins = "gpio57"; + function = "gpio"; + }; + + config { + pins = "gpio57"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + quat_mi2s_mclk_active: quat_mi2s_mclk_active { + mux { + pins = "gpio57"; + function = "qua_mi2s"; + }; + + config { + pins = "gpio57"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + quat_mi2s { + quat_mi2s_sleep: quat_mi2s_sleep { + mux { + pins = "gpio58", "gpio59"; + function = "gpio"; + }; + + config { + pins = "gpio58", "gpio59"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + quat_mi2s_active: quat_mi2s_active { + mux { + pins = "gpio58", "gpio59"; + function = "qua_mi2s"; + }; + + config { + pins = "gpio58", "gpio59"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + quat_mi2s_sd0 { + quat_mi2s_sd0_sleep: quat_mi2s_sd0_sleep { + mux { + pins = "gpio60"; + function = "gpio"; + }; + + config { + pins = "gpio60"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + quat_mi2s_sd0_active: quat_mi2s_sd0_active { + mux { + pins = "gpio60"; + function = "qua_mi2s"; + }; + + config { + pins = "gpio60"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + quat_mi2s_sd1 { + quat_mi2s_sd1_sleep: quat_mi2s_sd1_sleep { + mux { + pins = "gpio61"; + function = "gpio"; + }; + + config { + pins = "gpio61"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + quat_mi2s_sd1_active: quat_mi2s_sd1_active { + mux { + pins = "gpio61"; + function = "qua_mi2s"; + }; + + config { + pins = "gpio61"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + quat_mi2s_sd2 { + quat_mi2s_sd2_sleep: quat_mi2s_sd2_sleep { + mux { + pins = "gpio62"; + function = "gpio"; + }; + + config { + pins = "gpio62"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + quat_mi2s_sd2_active: quat_mi2s_sd2_active { + mux { + pins = "gpio62"; + function = "qua_mi2s"; + }; + + config { + pins = "gpio62"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + quat_mi2s_sd3 { + quat_mi2s_sd3_sleep: quat_mi2s_sd3_sleep { + mux { + pins = "gpio63"; + function = "gpio"; + }; + + config { + pins = "gpio63"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + quat_mi2s_sd3_active: quat_mi2s_sd3_active { + mux { + pins = "gpio63"; + function = "qua_mi2s"; + }; + + config { + pins = "gpio63"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + spkr_i2s_clk_pin { + spkr_i2s_clk_sleep: spkr_i2s_clk_sleep { + mux { + pins = "gpio69"; + function = "spkr_i2s"; + }; + + config { + pins = "gpio69"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + }; + }; + + spkr_i2s_clk_active: spkr_i2s_clk_active { + mux { + pins = "gpio69"; + function = "spkr_i2s"; + }; + + config { + pins = "gpio69"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + }; +}; --- /dev/null 2019-10-24 16:47:25.704025805 +0200 +++ linux-4.4.115-fbx/arch/arm64/boot/dts/qcom/msm8998-pm.dtsi 2019-01-22 16:16:21.195225506 +0100 @@ -0,0 +1,807 @@ +/* Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include + +&soc { + qcom,spm@178120000 { + compatible = "qcom,spm-v2"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x17812000 0x1000>; + qcom,name = "gold-l2"; /* Gold L2 SAW */ + qcom,saw2-ver-reg = <0xfd0>; + qcom,cpu-vctl-list = <&CPU4 &CPU5 &CPU6 &CPU7>; + qcom,vctl-timeout-us = <500>; + qcom,vctl-port = <0x0>; + qcom,phase-port = <0x1>; + qcom,saw2-avs-ctl = <0x1010031>; + qcom,saw2-avs-limit = <0x4580458>; + qcom,pfm-port = <0x2>; + }; + + qcom,spm@179120000 { + compatible = "qcom,spm-v2"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x17912000 0x1000>; + qcom,name = "silver-l2"; /* Silver L2 SAW */ + qcom,saw2-ver-reg = <0xfd0>; + qcom,cpu-vctl-list = <&CPU0 &CPU1 &CPU2 &CPU3>; + qcom,vctl-timeout-us = <500>; + qcom,vctl-port = <0x0>; + qcom,phase-port = <0x1>; + qcom,saw2-avs-ctl = <0x1010031>; + qcom,saw2-avs-limit = <0x4580458>; + qcom,pfm-port = <0x2>; + }; + + qcom,lpm-levels { + compatible = "qcom,lpm-levels"; + qcom,use-psci; + #address-cells = <1>; + #size-cells = <0>; + qcom,pm-cluster@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + label = "system"; + qcom,spm-device-names = "cci"; + qcom,psci-mode-shift = <8>; + qcom,psci-mode-mask = <0xf>; + + qcom,pm-cluster-level@0{ + reg = <0>; + label = "system-wfi"; + qcom,psci-mode = <0x0>; + qcom,latency-us = <100>; + qcom,ss-power = <725>; + qcom,energy-overhead = <85000>; + qcom,time-overhead = <120>; + }; + + qcom,pm-cluster-level@1{ /* E3 */ + reg = <1>; + label = "system-pc"; + qcom,psci-mode = <0x3>; + qcom,latency-us = <5534>; + qcom,ss-power = <399>; + qcom,energy-overhead = <3340281>; + qcom,time-overhead = <16744>; + qcom,min-child-idx = <3>; + qcom,is-reset; + qcom,notify-rpm; + }; + + qcom,pm-cluster@0{ + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + label = "pwr"; + qcom,spm-device-names = "l2"; + qcom,cpu = <&CPU0 &CPU1 &CPU2 &CPU3>; + qcom,psci-mode-shift = <4>; + qcom,psci-mode-mask = <0xf>; + + qcom,pm-cluster-level@0{ /* D1 */ + reg = <0>; + label = "pwr-l2-wfi"; + qcom,psci-mode = <0x1>; + qcom,latency-us = <51>; + qcom,ss-power = <452>; + qcom,energy-overhead = <69355>; + qcom,time-overhead = <99>; + }; + qcom,pm-cluster-level@1{ /* D2D */ + reg = <1>; + label = "pwr-l2-dynret"; + qcom,psci-mode = <0x2>; + qcom,latency-us = <659>; + qcom,ss-power = <434>; + qcom,energy-overhead = <465725>; + qcom,time-overhead = <976>; + qcom,min-child-idx = <1>; + }; + + qcom,pm-cluster-level@2{ /* D2E */ + reg = <2>; + label = "pwr-l2-ret"; + qcom,psci-mode = <0x3>; + qcom,latency-us = <743>; + qcom,ss-power = <425>; + qcom,energy-overhead = <629936>; + qcom,time-overhead = <1312>; + qcom,min-child-idx = <2>; + }; + + qcom,pm-cluster-level@3{ /* D4 */ + reg = <3>; + label = "pwr-l2-pc"; + qcom,psci-mode = <0x4>; + qcom,latency-us = <4562>; + qcom,ss-power = <408>; + qcom,energy-overhead = <2421840>; + qcom,time-overhead = <5376>; + qcom,min-child-idx = <2>; + qcom,is-reset; + }; + + qcom,pm-cpu { + #address-cells = <1>; + #size-cells = <0>; + qcom,psci-mode-shift = <0>; + qcom,psci-mode-mask = <0xf>; + + qcom,pm-cpu-level@0 { /* C1 */ + reg = <0>; + qcom,spm-cpu-mode = "wfi"; + qcom,psci-cpu-mode = <0x1>; + qcom,latency-us = <43>; + qcom,ss-power = <454>; + qcom,energy-overhead = <38639>; + qcom,time-overhead = <83>; + }; + + qcom,pm-cpu-level@1 { /* C2D */ + reg = <1>; + qcom,psci-cpu-mode = <2>; + qcom,spm-cpu-mode = "ret"; + qcom,latency-us = <86>; + qcom,ss-power = <449>; + qcom,energy-overhead = <78456>; + qcom,time-overhead = <167>; + }; + + qcom,pm-cpu-level@2 { /* C3 */ + reg = <2>; + qcom,spm-cpu-mode = "pc"; + qcom,psci-cpu-mode = <0x3>; + qcom,latency-us = <612>; + qcom,ss-power = <436>; + qcom,energy-overhead = <418225>; + qcom,time-overhead = <885>; + qcom,is-reset; + }; + }; + }; + + qcom,pm-cluster@1{ + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + label = "perf"; + qcom,spm-device-names = "l2"; + qcom,cpu = <&CPU4 &CPU5 &CPU6 &CPU7>; + qcom,psci-mode-shift = <4>; + qcom,psci-mode-mask = <0xf>; + + qcom,pm-cluster-level@0{ /* D1 */ + reg = <0>; + label = "perf-l2-wfi"; + qcom,psci-mode = <0x1>; + qcom,latency-us = <51>; + qcom,ss-power = <512>; + qcom,energy-overhead = <99986>; + qcom,time-overhead = <99>; + }; + + qcom,pm-cluster-level@1{ /* D2D */ + reg = <1>; + label = "perf-l2-dynret"; + qcom,psci-mode = <2>; + qcom,latency-us = <529>; + qcom,ss-power = <468>; + qcom,energy-overhead = <496783>; + qcom,time-overhead = <871>; + qcom,min-child-idx = <1>; + }; + + qcom,pm-cluster-level@2{ /* D2E */ + reg = <2>; + label = "perf-l2-ret"; + qcom,psci-mode = <3>; + qcom,latency-us = <605>; + qcom,ss-power = <456>; + qcom,energy-overhead = <597126>; + qcom,time-overhead = <1025>; + qcom,min-child-idx = <2>; + }; + + qcom,pm-cluster-level@3{ /* D4 */ + reg = <3>; + label = "perf-l2-pc"; + qcom,psci-mode = <0x4>; + qcom,latency-us = <2027>; + qcom,ss-power = <420>; + qcom,energy-overhead = <1624216>; + qcom,time-overhead = <2751>; + qcom,min-child-idx = <2>; + qcom,is-reset; + }; + + qcom,pm-cpu { + #address-cells = <1>; + #size-cells = <0>; + qcom,psci-mode-shift = <0>; + qcom,psci-mode-mask = <0xf>; + + qcom,pm-cpu-level@0 { /* C1 */ + reg = <0>; + qcom,spm-cpu-mode = "wfi"; + qcom,psci-cpu-mode = <0x1>; + qcom,latency-us = <43>; + qcom,ss-power = <515>; + qcom,energy-overhead = <48502>; + qcom,time-overhead = <86>; + }; + + qcom,pm-cpu-level@1 { /* C2D */ + reg = <1>; + qcom,psci-cpu-mode = <2>; + qcom,spm-cpu-mode = "ret"; + qcom,latency-us = <82>; + qcom,ss-power = <505>; + qcom,energy-overhead = <98530>; + qcom,time-overhead = <161>; + }; + + qcom,pm-cpu-level@2 { /* C3 */ + reg = <2>; + qcom,spm-cpu-mode = "pc"; + qcom,psci-cpu-mode = <0x3>; + qcom,latency-us = <525>; + qcom,ss-power = <476>; + qcom,energy-overhead = <485037>; + qcom,time-overhead = <861>; + qcom,is-reset; + }; + }; + }; + }; + }; + + qcom,rpm-stats@200000 { + compatible = "qcom,rpm-stats"; + reg = <0x200000 0x1000>, + <0x290014 0x4>, + <0x29001c 0x4>; + reg-names = "phys_addr_base", + "offset_addr", + "heap_phys_addrbase"; + qcom,sleep-stats-version = <2>; + }; + + qcom,rpm-rail-stats@200000 { + compatible = "qcom,rpm-rail-stats"; + reg = <0x200000 0x100>, + <0x29000c 0x4>; + reg-names = "phys_addr_base", + "offset_addr"; + }; + + qcom,rpm-log@200000 { + compatible = "qcom,rpm-log"; + reg = <0x200000 0x4000>, + <0x290018 0x4>; + qcom,rpm-addr-phys = <0x200000>; + qcom,offset-version = <4>; + qcom,offset-page-buffer-addr = <36>; + qcom,offset-log-len = <40>; + qcom,offset-log-len-mask = <44>; + qcom,offset-page-indices = <56>; + }; + + qcom,rpm-master-stats@778150 { + compatible = "qcom,rpm-master-stats"; + reg = <0x778150 0x5000>; + qcom,masters = "APSS", "MPSS", "ADSP", "SLPI", "TZ", "SPSS"; + qcom,master-stats-version = <2>; + qcom,master-offset = <4096>; + }; + + rpm_msg_ram: memory@0x200000 { + compatible = "qcom,rpm-msg-ram"; + reg = <0x200000 0x1000>, + <0x290000 0x1000>; + }; + + rpm_code_ram: rpm-memory@0x778000 { + compatible = "qcom,rpm-code-ram"; + reg = <0x778000 0x5000>; + }; + + qcom,system-stats { + compatible = "qcom,system-stats"; + qcom,rpm-msg-ram = <&rpm_msg_ram>; + qcom,rpm-code-ram = <&rpm_code_ram>; + qcom,masters = "APSS", "MPSS", "ADSP", "SLPI", "TZ", "SPSS"; + }; + + qcom,mpm@7781b8 { + compatible = "qcom,mpm-v2"; + reg = <0x7781b8 0x1000>, /* MSM_RPM_MPM_BASE 4K */ + <0x17911008 0x4>; /* MSM_APCS_GCC_BASE 4K */ + reg-names = "vmpm", "ipc"; + interrupts = ; + clocks = <&clock_gcc clk_cxo_lpm_clk>; + clock-names = "xo"; + qcom,num-mpm-irqs = <96>; + + qcom,ipc-bit-offset = <1>; + + qcom,gic-parent = <&intc>; + qcom,gic-map = + <0x1f 212>, /* usb30_power_event_irq */ + <0x2 216>, /* tsens1_upper_lower_int */ + <0x34 275>, /* qmp_usb3_lfps_rxterm_irq_cx */ + <0x57 358>, /* spmi_periph_irq[0] */ + <0x4f 379>, /* usb2phy_intr: qusb2phy_dmse_hv */ + <0x51 379>, /* usb2phy_intr: qusb2phy_dpse_hv */ + <0x50 384>, /* sp_rmb_sp2soc_irq */ + <0xff 16>, /* APC0_qgicQTmrHypPhysIrptReq */ + <0xff 17>, /* APC3_qgicQTmrSecPhysIrptReq */ + <0xff 18>, /* APC0_qgicQTmrNonSecPhysIrptReq */ + <0xff 19>, /* APC3_qgicQTmrVirtIrptReq */ + <0xff 20>, /* APC0_dbgCommRxFull */ + <0xff 21>, /* APC3_dbgCommTxEmpty */ + <0xff 22>, /* APC0_qgicPerfMonIrptReq */ + <0xff 23>, /* corespm_vote_int[7] */ + <0xff 24>, /* APC0_qgicExtFaultIrptReq */ + <0xff 28>, /* qgicWakeupSync */ + <0xff 29>, /* APCC_cti_SPI_intx */ + <0xff 30>, /* APCC_cti_SPI_inty */ + <0xff 32>, /* l2spm_vote_int[0] */ + <0xff 33>, /* l2spm_vote_int[1] */ + <0xff 34>, /* APCC_qgicL2ErrorIrptReq */ + <0xff 35>, /* WDT_barkInt */ + <0xff 36>, /* WDT_biteExpired */ + <0xff 39>, /* QTMR_qgicFrm0VirtIrq */ + <0xff 40>, /* QTMR_qgicFrm0PhyIrq */ + <0xff 41>, /* QTMR_qgicFrm1PhyIrq */ + <0xff 42>, /* QTMR_qgicFrm2PhyIrq */ + <0xff 43>, /* QTMR_qgicFrm3PhyIrq */ + <0xff 44>, /* QTMR_qgicFrm4PhyIrq */ + <0xff 45>, /* QTMR_qgicFrm5PhyIrq */ + <0xff 46>, /* QTMR_qgicFrm6PhyIrq */ + <0xff 47>, /* rbif_Irq[0] */ + <0xff 48>, /* rbif_Irq[1] */ + <0xff 52>, /* cci_spm_vote_summary_int */ + <0xff 54>, /* ~nERRORIRQ */ + <0xff 55>, /* nEVNTCNTOVERFLOW_cci */ + <0xff 56>, /* QTMR_qgicFrm0VirtIrq */ + <0xff 57>, /* QTMR_qgicFrm0PhyIrq */ + <0xff 58>, /* QTMR_qgicFrm1PhyIrq */ + <0xff 59>, /* QTMR_qgicFrm2PhyIrq */ + <0xff 60>, /* QTMR_qgicFrm3PhyIrq */ + <0xff 61>, /* QTMR_qgicFrm4PhyIrq */ + <0xff 62>, /* QTMR_qgicFrm5PhyIrq */ + <0xff 63>, /* QTMR_qgicFrm6PhyIrq */ + <0xff 64>, /* wakeup_counter_irq_OR */ + <0xff 65>, /* apc0_vs_alarm */ + <0xff 66>, /* apc1_vs_alarm */ + <0xff 67>, /* o_pwr_osm_irq */ + <0xff 68>, /* o_perf_osm_irq */ + <0xff 69>, /* o_pwr_dcvsh_interrupt */ + <0xff 70>, /* o_perf_dcvsh_interrupt */ + <0xff 73>, /* L2_EXTERRIRQ_C0 */ + <0xff 74>, /* L2_EXTERRIRQ_C1 */ + <0xff 75>, /* L2_INTERRIRQ_C0 */ + <0xff 76>, /* L2_INTERRIRQ_C1 */ + <0xff 77>, /* L2SPM_svicInt[0] */ + <0xff 78>, /* L2SPM_svicInt[1] */ + <0xff 79>, /* L2SPM_svicIntSwDone[0] */ + <0xff 80>, /* L2SPM_svicIntSwDone[1] */ + <0xff 81>, /* l2_avs_err[0] */ + <0xff 82>, /* l2_avs_err[1] */ + <0xff 83>, /* l2_avs_ack[0] */ + <0xff 84>, /* l2_avs_ack[1] */ + <0xff 96>, /* uart_dm_intr */ + <0xff 97>, /* uart_dm_intr */ + <0xff 98>, /* o_qm_interrupt */ + <0xff 100>, /* jpeg_vbif_irpt */ + <0xff 101>, /* processor_1_user_int */ + <0xff 102>, /* processor_1_kernel_int */ + <0xff 106>, /* dir_conn_irq_lpa_dsp_2 */ + <0xff 107>, /* dir_conn_irq_lpa_dsp_1 */ + <0xff 109>, /* camss_vbif_0_irq */ + <0xff 110>, /* csiphy_irq */ + <0xff 111>, /* csiphy_irq */ + <0xff 112>, /* csiphy_irq */ + <0xff 115>, /* mdp_irq */ + <0xff 116>, /* vbif_irpt */ + <0xff 117>, /* dir_conn_irq_lpa_dsp_0 */ + <0xff 119>, /* lcc_audio_wrapper_q6 */ + <0xff 122>, /* PIMEM TPDM BC interrupt */ + <0xff 123>, /* PIMEM TPDM TC interrupt */ + <0xff 124>, /* dir_conn_irq_sensors_1 */ + <0xff 125>, /* dir_conn_irq_sensors_0 */ + <0xff 126>, /* qup_irq */ + <0xff 127>, /* qup_irq */ + <0xff 128>, /* qup_irq */ + <0xff 129>, /* qup_irq */ + <0xff 130>, /* qup_irq */ + <0xff 131>, /* qup_irq */ + <0xff 132>, /* qup_irq */ + <0xff 133>, /* qup_irq */ + <0xff 134>, /* qup_irq */ + <0xff 135>, /* qup_irq */ + <0xff 136>, /* qup_irq */ + <0xff 137>, /* qup_irq */ + <0xff 138>, /* qup_irq */ + <0xff 139>, /* uart_dm_intr */ + <0xff 140>, /* uart_dm_intr */ + <0xff 141>, /* uart_dm_intr */ + <0xff 145>, /* uart_dm_intr */ + <0xff 146>, /* uart_dm_intr */ + <0xff 147>, /* uart_dm_intr */ + <0xff 148>, /* osmmu_Cirpt[4] */ + <0xff 149>, /* osmmu_Cirpt[5] */ + <0xff 151>, /* tsif_irq[0] */ + <0xff 152>, /* tsif_irq[1] */ + <0xff 153>, /* tspp_irq */ + <0xff 154>, /* bam_irq */ + <0xff 155>, /* dir_conn_irq_lpa_dsp_5 */ + <0xff 156>, /* dir_conn_irq_lpa_dsp_4 */ + <0xff 157>, /* sdcc_irq */ + <0xff 158>, /* sdcc_irq */ + <0xff 159>, /* lpass_qos_apps_interrupt */ + <0xff 160>, /* smmu_PMIrpt */ + <0xff 161>, /* sdcc_irq */ + <0xff 162>, /* sdcc_irq */ + <0xff 163>, /* usb30_ctrl_irq[0] */ + <0xff 164>, /* usb30_bam_irq */ + <0xff 165>, /* usb30_hs_phy_irq */ + <0xff 166>, /* o_lm_int_2qgic */ + <0xff 167>, /* pcie20_inta */ + <0xff 168>, /* pcie20_intb */ + <0xff 169>, /* smmu_Cirpt[12] */ + <0xff 170>, /* pcie20_intc */ + <0xff 171>, /* pcie20_intd */ + <0xff 172>, /* dcvs_int(8) */ + <0xff 173>, /* dcvs_int(9) */ + <0xff 184>, /* dir_conn_irq_lpa_dsp_3 */ + <0xff 185>, /* camss_vbif_2_irq */ + <0xff 186>, /* mnoc_obs_mainFault */ + <0xff 188>, /* q6ss_irq_out(4) */ + <0xff 189>, /* q6ss_irq_out(5) */ + <0xff 190>, /* q6ss_irq_out(6) */ + <0xff 191>, /* q6ss_irq_out(7) */ + <0xff 192>, /* audio_out0_irq */ + <0xff 194>, /* q6ss_wdog_exp_irq */ + <0xff 195>, /* lpass_slimbus_core_ee1_irq */ + <0xff 196>, /* lpass_slimbus_bam_ee1_irq */ + <0xff 197>, /* resampler_irq[0] */ + <0xff 199>, /* qdss_usb_trace_bam_irq */ + <0xff 200>, /* rpm_ipc[4] */ + <0xff 201>, /* rpm_ipc[5] */ + <0xff 202>, /* rpm_ipc[6] */ + <0xff 203>, /* rpm_ipc[7] */ + <0xff 204>, /* rpm_ipc[20] */ + <0xff 205>, /* rpm_ipc[21] */ + <0xff 206>, /* rpm_ipc[22] */ + <0xff 207>, /* rpm_ipc[23] */ + <0xff 208>, /* q6ss_irq_out(4) */ + <0xff 209>, /* q6ss_irq_out(5) */ + <0xff 210>, /* q6ss_irq_out(6) */ + <0xff 211>, /* q6ss_irq_out(7) */ + <0xff 213>, /* secure_wdog_bark_irq */ + <0xff 214>, /* tsens1_tsens_max_min_int */ + <0xff 215>, /* o_bimc_intr[0] */ + <0xff 217>, /* ocimem_nonsec_irq */ + <0xff 218>, /* sscaon_tmr_timeout_irq */ + <0xff 219>, /* q6ss_irq_out(28) */ + <0xff 220>, /* spmi_protocol_irq */ + <0xff 221>, /* q6ss_irq_out(29) */ + <0xff 222>, /* q6ss_irq_out(30) */ + <0xff 223>, /* spdm_offline_irq */ + <0xff 224>, /* spdm_realtime_irq */ + <0xff 225>, /* snoc_obs_mainFault */ + <0xff 226>, /* cnoc_obs_mainFault */ + <0xff 227>, /* o_ss_xpu3_sec_intr */ + <0xff 228>, /* o_tcsr_xpu3_non_sec_summary_intr */ + <0xff 229>, /* o_timeout_slave_kpss_summary_intr */ + <0xff 230>, /* o_tcsr_vmidmt_client_sec_summary_intr */ + <0xff 231>, /* o_tcsr_vmidmt_client_non_sec */ + <0xff 232>, /* o_tcsr_vmidmt_cfg_sec_summary_intr */ + <0xff 233>, /* o_tcsr_vmidmt_cfg_non_sec */ + <0xff 234>, /* q6ss_irq_out(31) */ + <0xff 235>, /* cpr_irq[0] */ + <0xff 236>, /* crypto_core_irq[0] */ + <0xff 237>, /* crypto_core_irq[1] */ + <0xff 238>, /* crypto_bam_irq[0] */ + <0xff 239>, /* crypto_bam_irq[1] */ + <0xff 240>, /* summary_irq_hmss */ + <0xff 241>, /* dir_conn_irq_hmss_7 */ + <0xff 242>, /* dir_conn_irq_hmss_6 */ + <0xff 243>, /* dir_conn_irq_hmss_5 */ + <0xff 244>, /* dir_conn_irq_hmss_4 */ + <0xff 245>, /* dir_conn_irq_hmss_3 */ + <0xff 246>, /* dir_conn_irq_hmss_2 */ + <0xff 247>, /* dir_conn_irq_hmss_1 */ + <0xff 248>, /* dir_conn_irq_hmss_0 */ + <0xff 249>, /* summary_irq_hmss_tz */ + <0xff 250>, /* cpr_irq[3] */ + <0xff 251>, /* cpr_irq[2] */ + <0xff 252>, /* cpr_irq[1] */ + <0xff 253>, /* sdcc_pwr_cmd_irq */ + <0xff 254>, /* sdio_wakeup_irq */ + <0xff 255>, /* cpr_irq[0] */ + <0xff 256>, /* smmu_Cirpt[13] */ + <0xff 257>, /* smmu_Cirpt[14] */ + <0xff 258>, /* smmu_Cirpt[0] */ + <0xff 259>, /* sdcc_pwr_cmd_irq */ + <0xff 260>, /* sdio_wakeup_irq */ + <0xff 261>, /* o_tcsr_mmu_nsgcfglrpt_summary_intr */ + <0xff 262>, /* o_tcsr_mmu_gcfglrpt_summary_intr */ + <0xff 263>, /* o_tcsr_mmu_nsglrpt_summary_intr */ + <0xff 264>, /* o_tcsr_mmu_glrpt_summary_intr */ + <0xff 265>, /* vbif_irpt */ + <0xff 266>, /* smmu_PMIrpt */ + <0xff 267>, /* smmu_Cirpt[3] */ + <0xff 268>, /* q6ss_irq_out(31) */ + <0xff 269>, /* rpm_wdog_expired_irq */ + <0xff 270>, /* bam_irq */ + <0xff 271>, /* bam_irq */ + <0xff 272>, /* q6ss_irq_out(28) */ + <0xff 273>, /* q6ss_irq_out(29) */ + <0xff 274>, /* q6ss_irq_out(30) */ + <0xff 276>, /* osmmu_Cirpt [4] */ + <0xff 277>, /* osmmu_Cirpt [5] */ + <0xff 278>, /* usb30_ctrl_irq[1] */ + <0xff 279>, /* osmmu_Cirpt [6] */ + <0xff 280>, /* osmmu_Cirpt [7] */ + <0xff 281>, /* osmmu_Cirpt [8] */ + <0xff 282>, /* osmmu_Cirpt [9] */ + <0xff 283>, /* osmmu_Cirpt [10] */ + <0xff 284>, /* osmmu_Cirpt [11] */ + <0xff 285>, /* osmmu_Cirpt [12] */ + <0xff 286>, /* osmmu_Cirpt [13] */ + <0xff 287>, /* osmmu_Cirpt [14] */ + <0xff 288>, /* osmmu_Cirpt [15] */ + <0xff 289>, /* ufs_ice_sec_level_irq */ + <0xff 290>, /* cpr_irq[4] */ + <0xff 291>, /* smmu_Cirpt[2] */ + <0xff 292>, /* osmmu_Cirpt [16] */ + <0xff 293>, /* osmmu_Cirpt [17] */ + <0xff 294>, /* osmmu_Cirpt [18] */ + <0xff 295>, /* osmmu_Cirpt [0] */ + <0xff 296>, /* osmmu_PMIrpt */ + <0xff 297>, /* ufs_intrq */ + <0xff 298>, /* osmmu_Cirpt [1] */ + <0xff 299>, /* osmmu_Cirpt [2] */ + <0xff 300>, /* osmmu_Cirpt [3] */ + <0xff 301>, /* smmu_Cirpt[1] */ + <0xff 302>, /* qdss_etrbytecnt_irq */ + <0xff 303>, /* smmu_Cirpt[0] */ + <0xff 304>, /* osmmu_Cirpt [19] */ + <0xff 305>, /* osmmu_Cirpt [20] */ + <0xff 306>, /* osmmu_Cirpt [21] */ + <0xff 307>, /* osmmu_Cirpt [22] */ + <0xff 308>, /* osmmu_Cirpt [23] */ + <0xff 310>, /* pcie20_global_int */ + <0xff 311>, /* pcie20_int_edma_int */ + <0xff 316>, /* lpass_hdmitx_interrupt_ext */ + <0xff 317>, /* rbif_irq */ + <0xff 318>, /* gpu_cc_gpu_cx_gds_hw_ctrl_irq_out */ + <0xff 319>, /* VENUS_IRQ */ + <0xff 323>, /* lpass_slimbus1_core_ee1_irq */ + <0xff 324>, /* lpass_slimbus1_bam_ee1_irq */ + <0xff 325>, /* camss_irq18 */ + <0xff 326>, /* camss_irq0 */ + <0xff 327>, /* camss_irq1 */ + <0xff 328>, /* camss_irq2 */ + <0xff 329>, /* camss_irq3 */ + <0xff 330>, /* camss_irq4 */ + <0xff 331>, /* camss_irq5 */ + <0xff 332>, /* GC_SYS_irq_0 */ + <0xff 333>, /* GC_SYS_irq_1 */ + <0xff 334>, /* GC_SYS_irq_2 */ + <0xff 335>, /* GC_SYS_irq_3 */ + <0xff 336>, /* camss_irq13 */ + <0xff 337>, /* camss_irq14 */ + <0xff 338>, /* camss_irq15 */ + <0xff 339>, /* camss_irq16 */ + <0xff 340>, /* camss_irq17 */ + <0xff 341>, /* camss_irq6 */ + <0xff 342>, /* smmu_Cirpt[15] */ + <0xff 343>, /* bam_irq[0] */ + <0xff 344>, /* uart_dm_intr */ + <0xff 345>, /* camss_irq7 */ + <0xff 346>, /* camss_irq8 */ + <0xff 347>, /* camss_irq9 */ + <0xff 348>, /* camss_irq10 */ + <0xff 350>, /* camss_irq12 */ + <0xff 351>, /* sif_aud_dec_out_irq_ext */ + <0xff 356>, /* vbif_nrt_irpt */ + <0xff 357>, /* Nonfatal pIMEM interrupt */ + <0xff 359>, /* spmi_periph_irq[1] */ + <0xff 360>, /* fatal pIMEM interrupt */ + <0xff 361>, /* osmmu_Cirpt[0] */ + <0xff 362>, /* osmmu_Cirpt[1] */ + <0xff 363>, /* osmmu_Cirpt[2] */ + <0xff 364>, /* osmmu_Cirpt[3] */ + <0xff 365>, /* ipa_irq(0) */ + <0xff 366>, /* osmmu_PMIrpt */ + <0xff 380>, /* sp_sp2apps_irq[0] */ + <0xff 381>, /* sp_sp2apps_irq[1] */ + <0xff 382>, /* sp_sp2apps_irq[2] */ + <0xff 383>, /* sp_sp2apps_irq[3] */ + <0xff 385>, /* osmmu_CIrpt[12] */ + <0xff 386>, /* osmmu_CIrpt[13] */ + <0xff 387>, /* osmmu_CIrpt[14] */ + <0xff 388>, /* osmmu_CIrpt[15] */ + <0xff 389>, /* osmmu_CIrpt[16] */ + <0xff 390>, /* osmmu_CIrpt[17] */ + <0xff 391>, /* osmmu_CIrpt[18] */ + <0xff 392>, /* osmmu_CIrpt[19] */ + <0xff 393>, /* o_dcc_crc_fail_int */ + <0xff 395>, /* aggre1_obs_mainfault */ + <0xff 396>, /* aggr1_smmu_cirpt[0] */ + <0xff 397>, /* aggr1_smmu_cirpt[1] */ + <0xff 398>, /* aggr1_smmu_cirpt[2] */ + <0xff 399>, /* aggr1_smmu_cirpt[3] */ + <0xff 400>, /* aggr1_smmu_cirpt[4] */ + <0xff 401>, /* aggr1_smmu_cirpt[5] */ + <0xff 402>, /* aggr1_smmu_cirpt[6] */ + <0xff 403>, /* aggr1_smmu_pmirpt */ + <0xff 404>, /* aggre2noc_obs_mainFault */ + <0xff 405>, /* osmmu_CIrpt[0] */ + <0xff 406>, /* osmmu_CIrpt[1] */ + <0xff 407>, /* osmmu_CIrpt[2] */ + <0xff 408>, /* osmmu_CIrpt[3] */ + <0xff 409>, /* osmmu_CIrpt[4] */ + <0xff 410>, /* osmmu_CIrpt[5] */ + <0xff 411>, /* o_dcc_task_done_int */ + <0xff 412>, /* vsense_alarm_irq */ + <0xff 413>, /* osmmu_PMIrpt */ + <0xff 414>, /* pmic_arb_trans_done_irq[0] */ + <0xff 415>, /* pmic_arb_trans_done_irq[1] */ + <0xff 416>, /* rpm_ipc[28] */ + <0xff 417>, /* rpm_ipc[29] */ + <0xff 418>, /* rpm_ipc[30] */ + <0xff 419>, /* rpm_ipc[31] */ + <0xff 420>, /* qup_irq */ + <0xff 421>, /* qup_irq */ + <0xff 422>, /* wd_bite_apps */ + <0xff 423>, /* lpass_qos_apps_interrupt */ + <0xff 424>, /* ipa_irq(2) */ + <0xff 425>, /* smmu_Cirpt[1] */ + <0xff 426>, /* smmu_Cirpt[2] */ + <0xff 427>, /* smmu_Cirpt[3] */ + <0xff 428>, /* smmu_Cirpt[4] */ + <0xff 429>, /* smmu_Cirpt[5] */ + <0xff 430>, /* smmu_Cirpt[6] */ + <0xff 431>, /* smmu_Cirpt[7] */ + <0xff 432>, /* smmu_Cirpt[8] */ + <0xff 433>, /* smmu_Cirpt[9] */ + <0xff 434>, /* smmu_Cirpt[10] */ + <0xff 435>, /* smmu_Cirpt[11] */ + <0xff 436>, /* smmu_Cirpt[16] */ + <0xff 437>, /* pcie20_0_int_msi_dev0 */ + <0xff 438>, /* pcie20_0_int_msi_dev1 */ + <0xff 439>, /* pcie20_0_int_msi_dev2 */ + <0xff 440>, /* pcie20_0_int_msi_dev3 */ + <0xff 441>, /* pcie20_0_int_msi_dev4 */ + <0xff 442>, /* pcie20_0_int_msi_dev5 */ + <0xff 443>, /* pcie20_0_int_msi_dev6 */ + <0xff 444>, /* pcie20_0_int_msi_dev7 */ + <0xff 445>, /* o_wcss_apps_intr[0] */ + <0xff 446>, /* o_wcss_apps_intr[1] */ + <0xff 447>, /* o_wcss_apps_intr[2] */ + <0xff 448>, /* o_wcss_apps_intr[3] */ + <0xff 449>, /* o_wcss_apps_intr[4] */ + <0xff 450>, /* o_wcss_apps_intr[5] */ + <0xff 452>, /* o_wcss_apps_intr[6] */ + <0xff 453>, /* o_wcss_apps_intr[7] */ + <0xff 454>, /* o_wcss_apps_intr[8] */ + <0xff 455>, /* o_wcss_apps_intr[9] */ + <0xff 456>, /* o_wcss_apps_intr[10] */ + <0xff 457>, /* o_wcss_apps_intr[11] */ + <0xff 458>, /* o_wcss_apps_intr[12] */ + <0xff 461>, /* o_ocimem_nonsec_irq */ + <0xff 462>, /* tsens1_tsens_critical_int */ + <0xff 463>, /* aggr1_smmu_cirpt[7] */ + <0xff 464>, /* ipa_bam_irq(0) */ + <0xff 465>, /* ipa_bam_irq(2) */ + <0xff 466>, /* ssc_uart_int */ + <0xff 468>, /* cri_cm_irq_tz */ + <0xff 469>, /* cri_cm_irq_hyp */ + <0xff 471>, /* mmss_bimc_smmu_gds_hw_ctrl_irq_out */ + <0xff 472>, /* gcc_gds_hw_ctrl_irq_out */ + <0xff 473>, /* lcc_audio_core_smmu_gds_hw_ctrl */ + <0xff 477>, /* tsens0_tsens_critical_int */ + <0xff 478>, /* tsens0_tsens_max_min_int */ + <0xff 480>, /* q6ss_wdog_expired_irq */ + <0xff 481>, /* mss_ipc_out_irq[4] */ + <0xff 482>, /* mss_ipc_out_irq[5] */ + <0xff 483>, /* mss_ipc_out_irq[6] */ + <0xff 484>, /* mss_ipc_out_irq[7] */ + <0xff 485>, /* mss_ipc_out_irq[28] */ + <0xff 486>, /* mss_ipc_out_irq[29] */ + <0xff 487>, /* mss_ipc_out_irq[30] */ + <0xff 488>, /* mss_ipc_out_irq[31] */ + <0xff 489>, /* skl_core_irq */ + <0xff 490>, /* tsens0_upper_lower_int */ + <0xff 494>, /* osmmu_CIrpt[6] */ + <0xff 495>, /* osmmu_CIrpt[7] */ + <0xff 496>, /* osmmu_CIrpt[8] */ + <0xff 497>, /* osmmu_CIrpt[9] */ + <0xff 498>, /* osmmu_CIrpt[10] */ + <0xff 499>, /* osmmu_CIrpt[11] */ + <0xff 503>; /* o_bimc_intr[1] */ + + qcom,gpio-parent = <&tlmm>; + qcom,gpio-map = <3 1>, + <4 5>, + <5 9>, + <6 11>, + <7 66>, + <8 22>, + <9 24>, + <10 26>, + <11 34>, + <12 36>, + <13 37>, /* PCIe0 */ + <14 38>, + <15 40>, + <16 42>, + <17 46>, + <18 50>, + <19 53>, + <20 54>, + <21 56>, + <22 57>, + <23 58>, + <24 59>, + <25 60>, + <26 61>, + <27 62>, + <28 63>, + <29 64>, + <30 71>, + <31 73>, + <32 77>, + <33 78>, + <34 79>, + <35 80>, + <36 82>, + <37 86>, + <38 91>, + <39 92>, + <40 95>, + <41 97>, + <42 101>, + <43 104>, + <44 106>, + <45 108>, + <46 112>, + <47 113>, + <48 110>, + <50 127>, + <51 115>, + <54 116>, /* PCIe2 */ + <55 117>, + <56 118>, + <57 119>, + <58 120>, + <59 121>, + <60 122>, + <61 123>, + <62 124>, + <63 125>, + <64 126>, + <65 129>, + <66 131>, + <67 132>, /* PCIe1 */ + <68 133>, + <69 145>; + }; +}; --- /dev/null 2019-10-24 16:47:25.704025805 +0200 +++ linux-4.4.115-fbx/arch/arm64/boot/dts/qcom/msm8998-ramoops.dtsi 2019-01-22 16:16:21.199225542 +0100 @@ -0,0 +1,21 @@ + +/ { + reserved-memory { + + /* pstore test */ + ramoops_mem: ramoops_mem@0x88f00000 { + compatible = "removed-dma-pool"; + no-map; + reg = <0x0 0x88f00000 0x0 0x100000>; /* 1 MB */ + }; + }; + + /* pstore test */ + ramoops { + compatible = "ramoops"; + memory-region = <&ramoops_mem>; + record-size = <0x00100000>; /* 512 KB */ + ecc-size = <16>; + no-dump-oops; + }; +}; --- /dev/null 2019-10-24 16:47:25.704025805 +0200 +++ linux-4.4.115-fbx/arch/arm64/boot/dts/qcom/msm8998-regulator.dtsi 2019-01-22 16:16:21.199225542 +0100 @@ -0,0 +1,1145 @@ +/* Copyright (c) 2015-2017, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include + +&rpm_bus { + /* PM8998 S1 + S6 = VDD_CX supply */ + rpm-regulator-smpa1 { + status = "okay"; + pm8998_s1_level: regulator-s1-level { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm8998_s1_level"; + qcom,set = <3>; + regulator-min-microvolt = + ; + regulator-max-microvolt = + ; + qcom,use-voltage-level; + }; + + pm8998_s1_floor_level: regulator-s1-floor-level { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm8998_s1_floor_level"; + qcom,set = <3>; + regulator-min-microvolt = + ; + regulator-max-microvolt = + ; + qcom,use-voltage-floor-level; + qcom,always-send-voltage; + }; + + pm8998_s1_level_ao: regulator-s1-level-ao { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm8998_s1_level_ao"; + qcom,set = <1>; + regulator-min-microvolt = + ; + regulator-max-microvolt = + ; + qcom,use-voltage-level; + }; + }; + + rpm-regulator-smpa2 { + status = "okay"; + pm8998_s2: regulator-s2 { + regulator-min-microvolt = <1128000>; + regulator-max-microvolt = <1128000>; + status = "okay"; + }; + }; + + rpm-regulator-smpa3 { + status = "okay"; + pm8998_s3: regulator-s3 { + regulator-min-microvolt = <1352000>; + regulator-max-microvolt = <1352000>; + status = "okay"; + }; + }; + + rpm-regulator-smpa4 { + status = "okay"; + pm8998_s4: regulator-s4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + status = "okay"; + }; + }; + + rpm-regulator-smpa5 { + status = "okay"; + pm8998_s5: regulator-s5 { + regulator-min-microvolt = <1904000>; + regulator-max-microvolt = <2040000>; + qcom,init-pin-ctrl-mode = <8>; /* PMIC_AWAKE */ + qcom,send-defaults; + status = "okay"; + }; + }; + + rpm-regulator-smpa7 { + status = "okay"; + pm8998_s7: regulator-s7 { + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1028000>; + qcom,init-pin-ctrl-mode = <8>; /* PMIC_AWAKE */ + qcom,send-defaults; + status = "okay"; + }; + }; + + rpm-regulator-smpa8 { + status = "okay"; + pm8998_s8: regulator-s8 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <800000>; + status = "okay"; + }; + }; + + /* PM8998 S9 = VDD_MX supply */ + rpm-regulator-smpa9 { + status = "okay"; + pm8998_s9_level: regulator-s9-level { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm8998_s9_level"; + qcom,set = <3>; + regulator-min-microvolt = + ; + regulator-max-microvolt = + ; + qcom,use-voltage-level; + }; + + pm8998_s9_floor_level: regulator-s9-floor-level { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm8998_s9_floor_level"; + qcom,set = <3>; + regulator-min-microvolt = + ; + regulator-max-microvolt = + ; + qcom,use-voltage-floor-level; + qcom,always-send-voltage; + }; + + pm8998_s9_level_ao: regulator-s9-level-ao { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm8998_s9_level_ao"; + qcom,set = <1>; + regulator-min-microvolt = + ; + regulator-max-microvolt = + ; + qcom,use-voltage-level; + }; + }; + + rpm-regulator-ldoa1 { + status = "okay"; + pm8998_l1: regulator-l1 { + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + proxy-supply = <&pm8998_l1>; + qcom,proxy-consumer-enable; + qcom,proxy-consumer-current = <73400>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa2 { + status = "okay"; + pm8998_l2: regulator-l2 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + proxy-supply = <&pm8998_l2>; + qcom,proxy-consumer-enable; + qcom,proxy-consumer-current = <12560>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa3 { + status = "okay"; + pm8998_l3: regulator-l3 { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + status = "okay"; + }; + }; + + /* PM8998 L4 = VDD_SSC_MX supply */ + rpm-regulator-ldoa4 { + status = "okay"; + pm8998_l4_level: regulator-l4-level { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm8998_l4_level"; + qcom,set = <3>; + regulator-min-microvolt = + ; + regulator-max-microvolt = + ; + qcom,use-voltage-level; + }; + + pm8998_l4_floor_level: regulator-l4-floor-level { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm8998_l4_floor_level"; + qcom,set = <3>; + regulator-min-microvolt = + ; + regulator-max-microvolt = + ; + qcom,use-voltage-floor-level; + qcom,always-send-voltage; + }; + }; + + rpm-regulator-ldoa5 { + status = "okay"; + pm8998_l5: regulator-l5 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <800000>; + /* Force NPM follows HW0_EN */ + qcom,init-pin-ctrl-mode = <1>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa6 { + status = "okay"; + pm8998_l6: regulator-l6 { + regulator-min-microvolt = <1808000>; + regulator-max-microvolt = <1808000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa7 { + status = "okay"; + pm8998_l7: regulator-l7 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + status = "okay"; + }; + + pm8998_l7_pin_ctrl: regulator-l7-pin-ctrl { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm8998_l7_pin_ctrl"; + qcom,set = <3>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + /* Force NPM follows HW_EN2 */ + qcom,init-pin-ctrl-mode = <4>; + /* Enable follows HW_EN2 */ + qcom,enable-with-pin-ctrl = <0 4>; + }; + }; + + rpm-regulator-ldoa8 { + status = "okay"; + pm8998_l8: regulator-l8 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa9 { + status = "okay"; + pm8998_l9: regulator-l9 { + regulator-min-microvolt = <1808000>; + regulator-max-microvolt = <2960000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa10 { + status = "okay"; + pm8998_l10: regulator-l10 { + regulator-min-microvolt = <1808000>; + regulator-max-microvolt = <2960000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa11 { + status = "okay"; + pm8998_l11: regulator-l11 { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa12 { + status = "okay"; + pm8998_l12: regulator-l12 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa13 { + status = "okay"; + pm8998_l13: regulator-l13 { + regulator-min-microvolt = <1808000>; + regulator-max-microvolt = <2960000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa14 { + status = "okay"; + pm8998_l14: regulator-l14 { + regulator-min-microvolt = <1880000>; + regulator-max-microvolt = <1880000>; + proxy-supply = <&pm8998_l14>; + qcom,proxy-consumer-enable; + qcom,proxy-consumer-current = <32000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa15 { + status = "okay"; + pm8998_l15: regulator-l15 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa16 { + status = "okay"; + pm8998_l16: regulator-l16 { + regulator-min-microvolt = <2704000>; + regulator-max-microvolt = <2704000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa17 { + status = "okay"; + pm8998_l17: regulator-l17 { + regulator-min-microvolt = <1304000>; + regulator-max-microvolt = <1304000>; + status = "okay"; + }; + + pm8998_l17_pin_ctrl: regulator-l17-pin-ctrl { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm8998_l17_pin_ctrl"; + qcom,set = <3>; + regulator-min-microvolt = <1304000>; + regulator-max-microvolt = <1304000>; + /* Force NPM follows HW_EN2 */ + qcom,init-pin-ctrl-mode = <4>; + /* Enable follows HW_EN2 */ + qcom,enable-with-pin-ctrl = <0 4>; + }; + }; + + rpm-regulator-ldoa18 { + status = "okay"; + pm8998_l18: regulator-l18 { + regulator-min-microvolt = <2704000>; + regulator-max-microvolt = <2704000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa19 { + status = "okay"; + pm8998_l19: regulator-l19 { + regulator-min-microvolt = <3008000>; + regulator-max-microvolt = <3008000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa20 { + status = "okay"; + pm8998_l20: regulator-l20 { + regulator-min-microvolt = <2960000>; + regulator-max-microvolt = <2960000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa21 { + status = "okay"; + pm8998_l21: regulator-l21 { + regulator-min-microvolt = <2960000>; + regulator-max-microvolt = <2960000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa22 { + status = "okay"; + pm8998_l22: regulator-l22 { + regulator-min-microvolt = <2864000>; + regulator-max-microvolt = <2864000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa23 { + status = "okay"; + pm8998_l23: regulator-l23 { + regulator-min-microvolt = <3312000>; + regulator-max-microvolt = <3312000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa24 { + status = "okay"; + pm8998_l24: regulator-l24 { + regulator-min-microvolt = <1848000>; + regulator-max-microvolt = <3088000>; + parent-supply = <&pm8998_l12>; + status = "okay"; + }; + }; + rpm-regulator-ldoa25 { + status = "okay"; + pm8998_l25: regulator-l25 { + regulator-min-microvolt = <3104000>; + regulator-max-microvolt = <3312000>; + status = "okay"; + }; + + pm8998_l25_pin_ctrl: regulator-l25-pin-ctrl { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm8998_l25_pin_ctrl"; + qcom,set = <3>; + regulator-min-microvolt = <3104000>; + regulator-max-microvolt = <3312000>; + /* Force NPM follows HW_EN2 */ + qcom,init-pin-ctrl-mode = <4>; + /* Enable follows HW_EN2 */ + qcom,enable-with-pin-ctrl = <0 4>; + }; + }; + + rpm-regulator-ldoa26 { + status = "okay"; + pm8998_l26: regulator-l26 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + status = "okay"; + }; + }; + + /* PM8998 L27 = VDD_SSC_CX supply */ + rpm-regulator-ldoa27 { + status = "okay"; + pm8998_l27_level: regulator-l27-level { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm8998_l27_level"; + qcom,set = <3>; + regulator-min-microvolt = + ; + regulator-max-microvolt = + ; + qcom,use-voltage-level; + }; + + pm8998_l27_floor_level: regulator-l27-floor-level { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm8998_l27_floor_level"; + qcom,set = <3>; + regulator-min-microvolt = + ; + regulator-max-microvolt = + ; + qcom,use-voltage-floor-level; + qcom,always-send-voltage; + }; + }; + + rpm-regulator-ldoa28 { + status = "okay"; + pm8998_l28: regulator-l28 { + regulator-min-microvolt = <3008000>; + regulator-max-microvolt = <3008000>; + status = "okay"; + }; + }; + + rpm-regulator-vsa1 { + status = "okay"; + pm8998_lvs1: regulator-lvs1 { + status = "okay"; + }; + }; + + rpm-regulator-vsa2 { + status = "okay"; + pm8998_lvs2: regulator-lvs2 { + status = "okay"; + }; + }; + + rpm-regulator-bobb { + status = "okay"; + pmi8998_bob: regulator-bob { + regulator-min-microvolt = <3312000>; + regulator-max-microvolt = <3600000>; + qcom,pwm-threshold-current = <2000000>; + qcom,init-bob-mode = <2>; + status = "okay"; + }; + pmi8998_bob_pin1: regulator-bob-pin1 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm8998_bob_pin1"; + qcom,set = <3>; + regulator-min-microvolt = <3312000>; + regulator-max-microvolt = <3600000>; + qcom,pwm-threshold-current = <2000000>; + qcom,init-bob-mode = <2>; + qcom,use-pin-ctrl-voltage1; + }; + pmi8998_bob_pin2: regulator-bob-pin2 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm8998_bob_pin2"; + qcom,set = <3>; + regulator-min-microvolt = <3312000>; + regulator-max-microvolt = <3600000>; + qcom,pwm-threshold-current = <2000000>; + qcom,init-bob-mode = <2>; + qcom,use-pin-ctrl-voltage2; + }; + pmi8998_bob_pin3: regulator-bob-pin3 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm8998_bob_pin3"; + qcom,set = <3>; + regulator-min-microvolt = <3312000>; + regulator-max-microvolt = <3600000>; + qcom,pwm-threshold-current = <2000000>; + qcom,init-bob-mode = <2>; + qcom,use-pin-ctrl-voltage3; + }; + }; +}; + +&spmi_bus { + qcom,pm8005@5 { + /* PM8005 S1 + S4 = 2 phase VDD_GFX supply */ + pm8005_s1: regulator@1400 { + regulator-name = "pm8005_s1"; + status = "okay"; + regulator-min-microvolt = <524000>; + regulator-max-microvolt = <1100000>; + qcom,enable-time = <500>; + }; + }; + + qcom,pm8998@1 { + pm8998_s10: regulator@2f00 { + compatible = "qcom,qpnp-regulator"; + reg = <0x2f00 0x100>; + regulator-name = "pm8998_s10"; + regulator-min-microvolt = <572000>; + regulator-max-microvolt = <1112000>; + qcom,enable-time = <500>; + regulator-always-on; + }; + + pm8998_s13: regulator@3800 { + compatible = "qcom,qpnp-regulator"; + reg = <0x3800 0x100>; + regulator-name = "pm8998_s13"; + regulator-min-microvolt = <572000>; + regulator-max-microvolt = <1112000>; + qcom,enable-time = <500>; + regulator-always-on; + }; + }; +}; + +/* Stub regulators */ + +/ { + gfx_stub_vreg: regulator-gfx-stub { + compatible = "qcom,stub-regulator"; + regulator-name = "gfx_stub_corner"; + qcom,hpm-min-load = <100000>; + regulator-min-microvolt = <1>; + regulator-max-microvolt = <6>; + status = "disabled"; + }; +}; + +&soc { +/* CPR controller regulators */ + apc0_cpr: cprh-ctrl@179c8000 { + compatible = "qcom,cprh-msm8998-v1-kbss-regulator"; + reg = <0x179c8000 0x4000>, <0x00784000 0x1000>; + reg-names = "cpr_ctrl", "fuse_base"; + clocks = <&clock_gcc clk_gcc_hmss_rbcpr_clk>; + clock-names = "core_clk"; + qcom,cpr-ctrl-name = "apc0"; + qcom,cpr-controller-id = <0>; + + qcom,cpr-sensor-time = <1000>; + qcom,cpr-loop-time = <5000000>; + qcom,cpr-idle-cycles = <15>; + qcom,cpr-up-down-delay-time = <3000>; + qcom,cpr-step-quot-init-min = <11>; + qcom,cpr-step-quot-init-max = <12>; + qcom,cpr-count-mode = <0>; /* All at once */ + qcom,cpr-count-repeat = <1>; + qcom,cpr-down-error-step-limit = <1>; + qcom,cpr-up-error-step-limit = <1>; + qcom,cpr-corner-switch-delay-time = <209>; + qcom,cpr-voltage-settling-time = <1760>; + + qcom,apm-threshold-voltage = <832000>; + qcom,apm-crossover-voltage = <880000>; + qcom,apm-hysteresis-voltage = <32000>; + qcom,voltage-step = <4000>; + qcom,voltage-base = <352000>; + qcom,cpr-saw-use-unit-mV; + + qcom,cpr-enable; + qcom,cpr-hw-closed-loop; + + qcom,cpr-panic-reg-addr-list = + <0x179cbaa4 0x17912c18>; + qcom,cpr-panic-reg-name-list = + "PWR_CPRH_STATUS", "APCLUS0_L2_SAW4_PMIC_STS"; + + qcom,cpr-aging-ref-voltage = <1112000>; + vdd-supply = <&pm8998_s10>; + + thread@0 { + qcom,cpr-thread-id = <0>; + qcom,cpr-consecutive-up = <0>; + qcom,cpr-consecutive-down = <2>; + qcom,cpr-up-threshold = <2>; + qcom,cpr-down-threshold = <2>; + + apc0_pwrcl_vreg: regulator { + regulator-name = "apc0_pwrcl_corner"; + regulator-min-microvolt = <1>; + regulator-max-microvolt = <23>; + + qcom,cpr-fuse-corners = <4>; + qcom,cpr-fuse-combos = <8>; + qcom,cpr-corners = <22>; + + qcom,cpr-corner-fmax-map = <7 10 17 22>; + + qcom,cpr-voltage-ceiling = + <896000 896000 896000 896000 896000 + 896000 896000 896000 896000 896000 + 896000 896000 896000 896000 896000 + 896000 896000 1032000 1032000 1032000 + 1112000 1112000>; + + qcom,cpr-voltage-floor = + <896000 896000 896000 896000 896000 + 896000 896000 896000 896000 896000 + 896000 896000 896000 896000 896000 + 896000 896000 896000 896000 896000 + 896000 896000>, + <572000 572000 572000 572000 572000 + 572000 572000 572000 572000 572000 + 664000 664000 664000 664000 664000 + 664000 664000 752000 752000 752000 + 752000 752000>, + <572000 572000 572000 572000 572000 + 572000 572000 572000 572000 572000 + 664000 664000 664000 664000 664000 + 664000 664000 752000 752000 752000 + 752000 752000>, + <572000 572000 572000 572000 572000 + 572000 572000 572000 572000 572000 + 664000 664000 664000 664000 664000 + 664000 664000 752000 752000 752000 + 752000 752000>, + <572000 572000 572000 572000 572000 + 572000 572000 572000 572000 572000 + 664000 664000 664000 664000 664000 + 664000 664000 752000 752000 752000 + 752000 752000>, + <572000 572000 572000 572000 572000 + 572000 572000 572000 572000 572000 + 664000 664000 664000 664000 664000 + 664000 664000 752000 752000 752000 + 752000 752000>, + <572000 572000 572000 572000 572000 + 572000 572000 572000 572000 572000 + 664000 664000 664000 664000 664000 + 664000 664000 752000 752000 752000 + 752000 752000>, + <572000 572000 572000 572000 572000 + 572000 572000 572000 572000 572000 + 664000 664000 664000 664000 664000 + 664000 664000 752000 752000 752000 + 752000 752000>; + + qcom,cpr-floor-to-ceiling-max-range = + <55000 55000 55000 55000 + 55000 55000 55000 55000 + 55000 55000 65000 65000 + 65000 65000 65000 65000 + 65000 65000 65000 65000 + 65000 65000>; + + qcom,corner-frequencies = + <300000000 345600000 422400000 + 499200000 576000000 633600000 + 710400000 806400000 883200000 + 960000000 1036800000 1113600000 + 1190400000 1248000000 1324800000 + 1401600000 1478400000 1574400000 + 1651200000 1728000000 1804800000 + 1881600000>; + + qcom,cpr-ro-scaling-factor = + <3430 3512 3262 3426 3100 3238 2463 + 2725 1749 2891 4058 4014 3195 2866 + 0 0>, + <3430 3512 3262 3426 3100 3238 2463 + 2725 1749 2891 4058 4014 3195 2866 + 0 0>, + <3162 3153 3163 3261 3037 3135 2645 + 2857 1864 2417 3499 3706 3315 2771 + 0 0>, + <2632 2539 2835 2857 2767 2813 2690 + 2827 1857 1632 2596 3068 3212 2454 + 0 0>; + + qcom,cpr-open-loop-voltage-fuse-adjustment = + <0 0 0 0>, + <40000 24000 0 0>, + <40000 24000 0 0>, + <40000 24000 0 0>, + <40000 24000 0 0>, + <40000 24000 0 0>, + <40000 24000 0 0>, + <40000 24000 0 0>; + + qcom,cpr-closed-loop-voltage-fuse-adjustment = + <0 0 0 0>, + <20000 26000 0 0>, + <20000 26000 0 0>, + <20000 26000 0 0>, + <20000 26000 0 0>, + <20000 26000 0 0>, + <20000 26000 0 0>, + <20000 26000 0 0>; + + qcom,allow-voltage-interpolation; + qcom,allow-quotient-interpolation; + qcom,cpr-scaled-open-loop-voltage-as-ceiling; + + qcom,cpr-aging-max-voltage-adjustment = <15000>; + qcom,cpr-aging-ref-corner = <22>; + qcom,cpr-aging-ro-scaling-factor = <1620>; + qcom,allow-aging-voltage-adjustment = <0>; + qcom,allow-aging-open-loop-voltage-adjustment = + <1>; + }; + }; + }; + + apc1_cpr: cprh-ctrl@179c4000{ + compatible = "qcom,cprh-msm8998-v1-kbss-regulator"; + reg = <0x179c4000 0x4000>, <0x00784000 0x1000>; + reg-names = "cpr_ctrl", "fuse_base"; + clocks = <&clock_gcc clk_gcc_hmss_rbcpr_clk>; + clock-names = "core_clk"; + qcom,cpr-ctrl-name = "apc1"; + qcom,cpr-controller-id = <1>; + + qcom,cpr-sensor-time = <1000>; + qcom,cpr-loop-time = <5000000>; + qcom,cpr-idle-cycles = <15>; + qcom,cpr-up-down-delay-time = <3000>; + qcom,cpr-step-quot-init-min = <9>; + qcom,cpr-step-quot-init-max = <14>; + qcom,cpr-count-mode = <0>; /* All at once */ + qcom,cpr-count-repeat = <1>; + qcom,cpr-down-error-step-limit = <1>; + qcom,cpr-up-error-step-limit = <1>; + qcom,cpr-corner-switch-delay-time = <209>; + qcom,cpr-voltage-settling-time = <1760>; + + qcom,apm-threshold-voltage = <832000>; + qcom,apm-crossover-voltage = <880000>; + qcom,apm-hysteresis-voltage = <32000>; + qcom,voltage-step = <4000>; + qcom,voltage-base = <352000>; + qcom,cpr-saw-use-unit-mV; + + qcom,cpr-enable; + qcom,cpr-hw-closed-loop; + + qcom,cpr-panic-reg-addr-list = + <0x179c7aa4 0x17812c18>; + qcom,cpr-panic-reg-name-list = + "PERF_CPRH_STATUS", "APCLUS1_L2_SAW4_PMIC_STS"; + + qcom,cpr-aging-ref-voltage = <1112000>; + vdd-supply = <&pm8998_s13>; + + thread@0 { + qcom,cpr-thread-id = <0>; + qcom,cpr-consecutive-up = <0>; + qcom,cpr-consecutive-down = <2>; + qcom,cpr-up-threshold = <2>; + qcom,cpr-down-threshold = <2>; + + apc1_perfcl_vreg: regulator { + regulator-name = "apc1_perfcl_corner"; + regulator-min-microvolt = <1>; + regulator-max-microvolt = <26>; + + qcom,cpr-fuse-corners = <4>; + qcom,cpr-fuse-combos = <8>; + qcom,cpr-corners = <25>; + + qcom,cpr-corner-fmax-map = <8 12 18 25>; + + qcom,cpr-voltage-ceiling = + <896000 896000 896000 896000 + 896000 896000 896000 896000 + 896000 896000 896000 896000 + 896000 896000 896000 896000 + 896000 896000 1032000 1032000 + 1032000 1032000 1112000 1112000 + 1112000>; + + qcom,cpr-voltage-floor = + <896000 896000 896000 896000 + 896000 896000 896000 896000 + 896000 896000 896000 896000 + 896000 896000 896000 896000 + 896000 896000 896000 896000 + 896000 896000 896000 896000 + 896000>, + <572000 572000 572000 572000 + 572000 572000 572000 572000 + 572000 572000 572000 572000 + 664000 664000 664000 664000 + 664000 664000 752000 752000 + 752000 752000 752000 752000 + 752000>, + <572000 572000 572000 572000 + 572000 572000 572000 572000 + 572000 572000 572000 572000 + 664000 664000 664000 664000 + 664000 664000 752000 752000 + 752000 752000 752000 752000 + 752000>, + <572000 572000 572000 572000 + 572000 572000 572000 572000 + 572000 572000 572000 572000 + 664000 664000 664000 664000 + 664000 664000 752000 752000 + 752000 752000 752000 752000 + 752000>, + <572000 572000 572000 572000 + 572000 572000 572000 572000 + 572000 572000 572000 572000 + 664000 664000 664000 664000 + 664000 664000 752000 752000 + 752000 752000 752000 752000 + 752000>, + <572000 572000 572000 572000 + 572000 572000 572000 572000 + 572000 572000 572000 572000 + 664000 664000 664000 664000 + 664000 664000 752000 752000 + 752000 752000 752000 752000 + 752000>, + <572000 572000 572000 572000 + 572000 572000 572000 572000 + 572000 572000 572000 572000 + 664000 664000 664000 664000 + 664000 664000 752000 752000 + 752000 752000 752000 752000 + 752000>, + <572000 572000 572000 572000 + 572000 572000 572000 572000 + 572000 572000 572000 572000 + 664000 664000 664000 664000 + 664000 664000 752000 752000 + 752000 752000 752000 752000 + 752000>; + + qcom,cpr-floor-to-ceiling-max-range = + <55000 55000 55000 55000 + 55000 55000 55000 55000 + 55000 55000 55000 55000 + 65000 65000 65000 65000 + 65000 65000 65000 65000 + 65000 65000 65000 65000 + 65000>; + + qcom,corner-frequencies = + <300000000 345600000 422400000 + 480000000 556800000 633600000 + 710400000 787200000 844800000 + 902400000 979200000 1056000000 + 1171200000 1248000000 1324800000 + 1401600000 1478400000 1536000000 + 1632000000 1708800000 1785600000 + 1862400000 1939200000 2016000000 + 2092800000>; + + qcom,cpr-ro-scaling-factor = + <3430 3512 3262 3426 3100 3238 2463 + 2725 1749 2891 4058 4014 3195 2866 + 0 0>, + <3430 3512 3262 3426 3100 3238 2463 + 2725 1749 2891 4058 4014 3195 2866 + 0 0>, + <3162 3153 3163 3261 3037 3135 2645 + 2857 1864 2417 3499 3706 3315 2771 + 0 0>, + <2632 2539 2835 2857 2767 2813 2690 + 2827 1857 1632 2596 3068 3212 2454 + 0 0>; + + qcom,cpr-open-loop-voltage-fuse-adjustment = + <0 0 0 0>, + <8000 0 0 52000>, + <8000 0 0 52000>, + <8000 0 0 52000>, + <8000 0 0 52000>, + <8000 0 0 52000>, + <8000 0 0 52000>, + <8000 0 0 52000>; + + qcom,cpr-closed-loop-voltage-fuse-adjustment = + <0 0 0 0>, + <0 0 0 50000>, + <0 0 0 50000>, + <0 0 0 50000>, + <0 0 0 50000>, + <0 0 0 50000>, + <0 0 0 50000>, + <0 0 0 50000>; + + qcom,allow-voltage-interpolation; + qcom,allow-quotient-interpolation; + qcom,cpr-scaled-open-loop-voltage-as-ceiling; + + qcom,cpr-aging-max-voltage-adjustment = <15000>; + qcom,cpr-aging-ref-corner = <25>; + qcom,cpr-aging-ro-scaling-factor = <1700>; + qcom,allow-aging-voltage-adjustment = <0>; + qcom,allow-aging-open-loop-voltage-adjustment = + <1>; + }; + }; + }; + + gfx_cpr: cpr4-ctrl@5061000 { + compatible = "qcom,cpr4-msm8998-v1-mmss-regulator"; + reg = <0x05061000 0x4000>, + <0x00784000 0x1000>, + <0x05065204 0x4>; + reg-names = "cpr_ctrl", "fuse_base", "aging_allowed"; + clocks = <&clock_gpu clk_gpucc_rbcpr_clk>, + <&clock_gcc clk_cnoc_clk>; + clock-names = "core_clk", "bus_clk"; + interrupts = ; + interrupt-names = "cpr"; + qcom,cpr-ctrl-name = "gfx"; + + qcom,cpr-sensor-time = <1000>; + qcom,cpr-loop-time = <5000000>; + qcom,cpr-idle-cycles = <15>; + qcom,cpr-step-quot-init-min = <8>; + qcom,cpr-step-quot-init-max = <12>; + qcom,cpr-count-mode = <0>; /* All-at-once min */ + qcom,cpr-count-repeat = <1>; + + vdd-supply = <&pm8005_s1>; + qcom,voltage-step = <4000>; + mem-acc-supply = <&gfx_mem_acc_vreg>; + qcom,cpr-aging-ref-voltage = <1032000>; + qcom,cpr-aging-allowed-reg-mask = <0x00000003>; + qcom,cpr-aging-allowed-reg-value = <0x00000003>; + + qcom,cpr-enable; + + thread@0 { + qcom,cpr-thread-id = <0>; + qcom,cpr-consecutive-up = <0>; + qcom,cpr-consecutive-down = <2>; + qcom,cpr-up-threshold = <0>; + qcom,cpr-down-threshold = <2>; + + gfx_vreg: regulator { + regulator-name = "gfx_corner"; + regulator-min-microvolt = <1>; + regulator-max-microvolt = <6>; + + qcom,cpr-fuse-corners = <4>; + qcom,cpr-fuse-combos = <8>; + qcom,cpr-corners = <6>; + + qcom,cpr-corner-fmax-map = <1 3 5 6>; + + qcom,cpr-voltage-ceiling = + <896000 896000 896000 896000 896000 + 1032000>, + <672000 740000 800000 868000 976000 + 1100000>, + <672000 740000 800000 868000 976000 + 1100000>, + <672000 740000 800000 868000 976000 + 1100000>, + <672000 740000 800000 868000 976000 + 1100000>, + <672000 740000 800000 868000 976000 + 1100000>, + <672000 740000 800000 868000 976000 + 1100000>, + <672000 740000 800000 868000 976000 + 1100000>; + + qcom,cpr-voltage-floor = + <896000 896000 896000 896000 896000 + 896000>, + <528000 528000 568000 612000 664000 + 752000>, + <528000 528000 568000 612000 664000 + 752000>, + <528000 528000 568000 612000 664000 + 752000>, + <528000 528000 568000 612000 664000 + 752000>, + <528000 528000 568000 612000 664000 + 752000>, + <528000 528000 568000 612000 664000 + 752000>, + <528000 528000 568000 612000 664000 + 752000>; + + qcom,mem-acc-voltage = <1 1 1 2 2 2>; + + qcom,corner-frequencies = + <171000000 251000000 332000000 + 403000000 504000000 650000000>; + + qcom,cpr-target-quotients = + < 0 0 404 478 363 411 140 176 + 105 0 0 0 0 0 0 0>, + < 0 0 574 651 532 584 266 319 + 196 0 0 0 0 0 0 0>, + < 0 0 743 830 693 753 389 456 + 285 0 0 0 0 0 0 0>, + < 0 0 879 977 829 893 495 570 + 365 0 0 0 0 0 0 0>, + < 0 0 1168 1270 1097 1150 0 0 + 0 0 0 1406 899 805 0 0>, + <1669 1757 0 0 0 0 0 0 + 0 1359 1902 1740 0 1033 0 0>; + + qcom,cpr-ro-scaling-factor = + <2389 2287 2985 3112 2873 2904 2159 2399 + 1580 1602 2158 3042 2780 2069 0 0>, + <2389 2287 2985 3112 2873 2904 2159 2399 + 1580 1602 2158 3042 2780 2069 0 0>, + <2389 2287 2985 3112 2873 2904 2159 2399 + 1580 1602 2158 3042 2780 2069 0 0>, + <2389 2287 2985 3112 2873 2904 2159 2399 + 1580 1602 2158 3042 2780 2069 0 0>, + <2389 2287 2985 3112 2873 2904 2159 2399 + 1580 1602 2158 3042 2780 2069 0 0>, + <2389 2287 2985 3112 2873 2904 2159 2399 + 1580 1602 2158 3042 2780 2069 0 0>; + + qcom,cpr-open-loop-voltage-fuse-adjustment = + < 72000 0 0 0>, + < 72000 0 0 0>, + < 72000 0 0 0>, + < 72000 0 0 0>, + < 72000 0 0 0>, + < 72000 0 0 0>, + < 72000 0 0 0>, + < 72000 0 0 0>; + + qcom,cpr-closed-loop-voltage-adjustment = + < 65000 26000 8000 0 + 0 0>, + < 65000 26000 8000 0 + 0 0>, + < 65000 26000 8000 0 + 0 0>, + < 65000 26000 8000 0 + 0 0>, + < 65000 26000 8000 0 + 0 0>, + < 65000 26000 8000 0 + 0 0>, + < 65000 26000 8000 0 + 0 0>, + < 65000 26000 8000 0 + 0 0>; + + qcom,cpr-floor-to-ceiling-max-range = + <75000 75000 75000 75000 75000 75000>; + + qcom,cpr-fused-closed-loop-voltage-adjustment-map = + <0 0 1 2 3 4>; + + qcom,allow-voltage-interpolation; + qcom,cpr-scaled-open-loop-voltage-as-ceiling; + + qcom,cpr-aging-max-voltage-adjustment = <15000>; + qcom,cpr-aging-ref-corner = <6>; + qcom,cpr-aging-ro-scaling-factor = <2950>; + qcom,allow-aging-voltage-adjustment = <0>; + qcom,allow-aging-open-loop-voltage-adjustment = + <1>; + }; + }; + }; + + gfx_mem_acc_vreg: regulator@1fcf004 { + compatible = "qcom,mem-acc-regulator"; + reg = <0x01fcf004 0x4>; + reg-names = "acc-sel-l1"; + regulator-name = "gfx_mem_acc_corner"; + regulator-min-microvolt = <1>; + regulator-max-microvolt = <2>; + + qcom,corner-acc-map = <0x1 0x0>; + qcom,acc-sel-l1-bit-pos = <0>; + qcom,acc-sel-l1-bit-size = <1>; + }; +}; + +&pmi8998_charger { + smb2_vbus: qcom,smb2-vbus { + regulator-name = "smb2-vbus"; + }; + + smb2_vconn: qcom,smb2-vconn { + regulator-name = "smb2-vconn"; + }; +}; --- /dev/null 2019-10-24 16:47:25.704025805 +0200 +++ linux-4.4.115-fbx/arch/arm64/boot/dts/qcom/msm8998-sde-display.dtsi 2019-01-22 16:16:21.199225542 +0100 @@ -0,0 +1,75 @@ +/* Copyright (c) 2017, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&soc { + + sde_wb: qcom,wb-display@0 { + compatible = "qcom,wb-display"; + cell-index = <0>; + label = "wb_display"; + }; + + msm_ext_disp: qcom,msm_ext_disp { + compatible = "qcom,msm-ext-disp"; + + ext_disp_audio_codec: qcom,msm-ext-disp-audio-codec-rx { + compatible = "qcom,msm-ext-disp-audio-codec-rx"; + qcom,msm_ext_disp = <&msm_ext_disp>; + }; + }; + + sde_hdmi: qcom,hdmi-display { + compatible = "qcom,hdmi-display"; + label = "sde_hdmi"; + qcom,display-type = "secondary"; + qcom,msm_ext_disp = <&msm_ext_disp>; + }; + + sde_hdmi_cec: qcom,hdmi-cec@c9a0000 { + compatible = "qcom,hdmi-cec"; + label = "sde_hdmi_cec"; + qcom,hdmi-dev = <&sde_hdmi>; + interrupt-parent = <&sde_hdmi_tx>; + interrupts = <1 0>; + + reg = <0xc9a0000 0x50c>; + reg-names = "hdmi_cec"; + + clocks = <&clock_mmss clk_mmss_mnoc_ahb_clk>, + <&clock_mmss clk_mmss_mdss_ahb_clk>, + <&clock_mmss clk_mmss_mdss_hdmi_clk>; + clock-names = "cec_mnoc_clk", "cec_iface_clk", "cec_core_clk"; + + pinctrl-names = "cec_active", "cec_sleep"; + pinctrl-0 = <&mdss_hdmi_cec_active>; + pinctrl-1 = <&mdss_hdmi_cec_suspend>; + + cec-gdsc-supply = <&gdsc_mdss>; + qcom,platform-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,platform-supply-entry@0 { + reg = <0>; + qcom,supply-name = "cec-gdsc"; + qcom,supply-min-voltage = <0>; + qcom,supply-max-voltage = <0>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + }; + }; + }; +}; + +&sde_kms { + connectors = <&sde_hdmi_tx &sde_hdmi &sde_wb>; +}; --- /dev/null 2019-10-24 16:47:25.704025805 +0200 +++ linux-4.4.115-fbx/arch/arm64/boot/dts/qcom/msm8998-sde.dtsi 2019-01-22 16:16:21.199225542 +0100 @@ -0,0 +1,245 @@ +/* Copyright (c) 2017, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&soc { + sde_kms: qcom,sde_kms@c900000 { + compatible = "qcom,sde-kms"; + reg = <0x0c900000 0x90000>, + <0x0c9b0000 0x2008>; + reg-names = "mdp_phys", "vbif_phys"; + + /* clock and supply entries */ + clocks = <&clock_gcc clk_mmssnoc_axi_clk>, + <&clock_mmss clk_mmss_mnoc_ahb_clk>, + <&clock_mmss clk_mmss_bimc_smmu_ahb_clk>, + <&clock_mmss clk_mmss_bimc_smmu_axi_clk>, + <&clock_mmss clk_mmss_mnoc_ahb_clk>, + <&clock_mmss clk_mmss_mdss_ahb_clk>, + <&clock_mmss clk_mmss_mdss_axi_clk>, + <&clock_mmss clk_mdp_clk_src>, + <&clock_mmss clk_mmss_mdss_mdp_clk>, + <&clock_mmss clk_mmss_mdss_vsync_clk>, + <&clock_mmss clk_mmss_mdss_mdp_lut_clk>; + clock-names = "mmss_noc_axi_clk", + "mmss_noc_ahb_clk", + "mmss_smmu_ahb_clk", + "mmss_smmu_axi_clk", + "mnoc_clk", "iface_clk", "bus_clk", + "core_clk_src", "core_clk", "vsync_clk", + "lut_clk"; + clock-rate = <0 0 0 0 0 0 0 330000000 0 0 0 0>; + clock-max-rate = <0 0 0 0 0 0 412500000 412500000 0 0 0 0>; + qcom,sde-max-bw-low-kbps = <6700000>; + qcom,sde-max-bw-high-kbps = <6700000>; + + /* interrupt config */ + interrupt-parent = <&intc>; + interrupts = <0 83 0>; + interrupt-controller; + #interrupt-cells = <1>; + iommus = <&mmss_smmu 0>; + + gpus = <&msm_gpu>; + + /* hw blocks */ + qcom,sde-off = <0x1000>; + qcom,sde-len = <0x458>; + + qcom,sde-ctl-off = <0x2000 0x2200 0x2400 + 0x2600 0x2800>; + qcom,sde-ctl-size = <0x94>; + + qcom,sde-mixer-off = <0x45000 0x46000 0x47000 + 0x48000 0x49000 0x4a000>; + qcom,sde-mixer-size = <0x31c>; + + qcom,sde-dspp-off = <0x55000 0x57000>; + qcom,sde-dspp-size = <0x17e0>; + + qcom,sde-wb-off = <0x66000>; + qcom,sde-wb-size = <0x2dc>; + + qcom,sde-wb-id = <2>; + qcom,sde-wb-xin-id = <6>; + qcom,sde-wb-clk-ctrl = <0x2bc 0x10>; + qcom,sde-intf-off = <0x6b000 0x6b800 + 0x6c000 0x6c800>; + qcom,sde-intf-size = <0x280>; + + qcom,sde-intf-type = "dp", "dsi", "dsi", "hdmi"; + + qcom,sde-pp-off = <0x71000 0x71800 + 0x72000 0x72800 0x73000>; + qcom,sde-pp-slave = <0x0 0x0 0x0 0x0 0x1>; + + qcom,sde-pp-size = <0xd4>; + + qcom,sde-te2-off = <0x2000 0x2000 0x0 0x0 0x0>; + qcom,sde-cdm-off = <0x7a200>; + qcom,sde-cdm-size = <0x224>; + + qcom,sde-dsc-off = <0x81000 0x81400>; + qcom,sde-dsc-size = <0x140>; + + qcom,sde-intf-max-prefetch-lines = <0x15 0x15 0x15 0x15>; + + qcom,sde-sspp-type = "vig", "vig", "vig", "vig", + "dma", "dma", "dma", "dma", + "cursor", "cursor"; + + qcom,sde-sspp-off = <0x5000 0x7000 0x9000 0xb000 + 0x25000 0x27000 0x29000 0x2b000 + 0x35000 0x37000>; + qcom,sde-sspp-src-size = <0x1ac>; + + qcom,sde-sspp-xin-id = <0 4 8 12 1 5 9 13 2 10>; + + /* offsets are relative to "mdp_phys + qcom,sde-off */ + qcom,sde-sspp-clk-ctrl = <0x2ac 0x8>, <0x2b4 0x8>, + <0x2c4 0x8>, <0x2c4 0xc>, <0x3a8 0x10>, + <0x3b0 0x10>; + + qcom,sde-qseed-type = "qseedv3"; + qcom,sde-mixer-linewidth = <2560>; + qcom,sde-sspp-linewidth = <2560>; + qcom,sde-mixer-blendstages = <0x7>; + qcom,sde-highest-bank-bit = <0x2>; + qcom,sde-panic-per-pipe; + qcom,sde-has-cdp; + qcom,sde-has-src-split; + qcom,sde-sspp-danger-lut = <0x000f 0xffff 0x0000>; + qcom,sde-sspp-safe-lut = <0xfffc 0xff00 0xffff>; + + qcom,sde-vbif-off = <0>; + qcom,sde-vbif-id = <0>; + qcom,sde-vbif-default-ot-rd-limit = <32>; + qcom,sde-vbif-default-ot-wr-limit = <32>; + qcom,sde-vbif-dynamic-ot-rd-limit = <62208000 2>, + <124416000 4>, <248832000 16>; + qcom,sde-vbif-dynamic-ot-wr-limit = <62208000 2>, + <124416000 4>, <248832000 16>; + + vdd-supply = <&gdsc_mdss>; + gdsc-mmagic-mdss-supply = <&gdsc_bimc_smmu>; + qcom,sde-csc-type = "csc-10bit"; + + qcom,sde-sspp-vig-blocks { + qcom,sde-vig-csc-off = <0x1a00>; + qcom,sde-vig-qseed-off = <0xa00>; + qcom,sde-vig-qseed-size = <0xa0>; + }; + + qcom,platform-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,platform-supply-entry@0 { + reg = <0>; + qcom,supply-name = "gdsc-mmagic-mdss"; + qcom,supply-min-voltage = <0>; + qcom,supply-max-voltage = <0>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + }; + + qcom,platform-supply-entry@1 { + reg = <1>; + qcom,supply-name = "vdd"; + qcom,supply-min-voltage = <0>; + qcom,supply-max-voltage = <0>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + }; + }; + + smmu_kms_unsec: qcom,smmu_kms_unsec_cb { + compatible = "qcom,smmu_sde_unsec"; + iommus = <&mmss_smmu 0>; + }; + + smmu_kms_sec: qcom,smmu_kms_sec_cb { + compatible = "qcom,smmu_sde_sec"; + iommus = <&mmss_smmu 1>; + }; + + /* data and reg bus scale settings */ + qcom,sde-data-bus { + qcom,msm-bus,name = "mdss_sde"; + qcom,msm-bus,num-cases = <3>; + qcom,msm-bus,num-paths = <2>; + qcom,msm-bus,vectors-KBps = + <22 512 0 0>, <23 512 0 0>, + <22 512 0 6400000>, <23 512 0 6400000>, + <22 512 0 6400000>, <23 512 0 6400000>; + }; + qcom,sde-reg-bus { + qcom,msm-bus,name = "mdss_reg"; + qcom,msm-bus,num-cases = <4>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,active-only; + qcom,msm-bus,vectors-KBps = + <1 590 0 0>, + <1 590 0 76800>, + <1 590 0 160000>, + <1 590 0 320000>; + }; + }; + + sde_hdmi_tx: qcom,hdmi_tx_8998@c9a0000 { + cell-index = <0>; + compatible = "qcom,hdmi-tx-8998"; + reg = <0xc9a0000 0x50c>, + <0x780000 0x621c>, + <0xc9e0000 0x28>; + reg-names = "core_physical", "qfprom_physical", "hdcp_physical"; + interrupt-parent = <&sde_kms>; + interrupts = <8 0>; + interrupt-controller; + #interrupt-cells = <1>; + qcom,hdmi-tx-ddc-clk-gpio = <&tlmm 32 0>; + qcom,hdmi-tx-ddc-data-gpio = <&tlmm 33 0>; + qcom,hdmi-tx-hpd-gpio = <&tlmm 34 0>; + qcom,hdmi-tx-hpd5v-gpio = <&tlmm 133 0>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&mdss_hdmi_hpd_active + &mdss_hdmi_ddc_active + &mdss_hdmi_5v_active>; + pinctrl-1 = <&mdss_hdmi_hpd_suspend + &mdss_hdmi_ddc_suspend + &mdss_hdmi_5v_suspend>; + hpd-gdsc-supply = <&gdsc_mdss>; + qcom,supply-names = "hpd-gdsc"; + qcom,min-voltage-level = <0>; + qcom,max-voltage-level = <0>; + qcom,enable-load = <0>; + qcom,disable-load = <0>; + + clocks = <&clock_mmss clk_mmss_mnoc_ahb_clk>, + <&clock_mmss clk_mmss_mdss_ahb_clk>, + <&clock_mmss clk_mmss_mdss_hdmi_clk>, + <&clock_mmss clk_mmss_mdss_mdp_clk>, + <&clock_mmss clk_mmss_mdss_hdmi_dp_ahb_clk>, + <&clock_mmss clk_mmss_mdss_extpclk_clk>, + <&clock_mmss clk_mmss_mnoc_ahb_clk>, + <&clock_mmss clk_mmss_misc_ahb_clk>, + <&clock_mmss clk_mmss_mdss_axi_clk>; + clock-names = "hpd_mnoc_clk", "hpd_iface_clk", + "hpd_core_clk", "hpd_mdp_core_clk", + "hpd_alt_iface_clk", "core_extp_clk", + "mnoc_clk","hpd_misc_ahb_clk", + "hpd_bus_clk"; + + /*qcom,mdss-fb-map = <&mdss_fb2>;*/ + qcom,pluggable; + }; +}; +#include "msm8998-sde-display.dtsi" --- /dev/null 2019-10-24 16:47:25.704025805 +0200 +++ linux-4.4.115-fbx/arch/arm64/boot/dts/qcom/msm8998-smp2p.dtsi 2019-01-22 16:16:21.199225542 +0100 @@ -0,0 +1,267 @@ +/* Copyright (c) 2015-2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +&soc { + qcom,smp2p-modem@17911008 { + compatible = "qcom,smp2p"; + reg = <0x17911008 0x4>; + qcom,remote-pid = <1>; + qcom,irq-bitmask = <0x4000>; + interrupts = <0 451 1>; + }; + + qcom,smp2p-adsp@17911008 { + compatible = "qcom,smp2p"; + reg = <0x17911008 0x4>; + qcom,remote-pid = <2>; + qcom,irq-bitmask = <0x400>; + interrupts = <0 158 1>; + }; + + qcom,smp2p-dsps@17911008 { + compatible = "qcom,smp2p"; + reg = <0x17911008 0x4>; + qcom,remote-pid = <3>; + qcom,irq-bitmask = <0x4000000>; + interrupts = <0 178 1>; + }; + + smp2pgpio_smp2p_15_in: qcom,smp2pgpio-smp2p-15-in { + compatible = "qcom,smp2pgpio"; + qcom,entry-name = "smp2p"; + qcom,remote-pid = <15>; + qcom,is-inbound; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + qcom,smp2pgpio_test_smp2p_15_in { + compatible = "qcom,smp2pgpio_test_smp2p_15_in"; + gpios = <&smp2pgpio_smp2p_15_in 0 0>; + }; + + smp2pgpio_smp2p_15_out: qcom,smp2pgpio-smp2p-15-out { + compatible = "qcom,smp2pgpio"; + qcom,entry-name = "smp2p"; + qcom,remote-pid = <15>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + qcom,smp2pgpio_test_smp2p_15_out { + compatible = "qcom,smp2pgpio_test_smp2p_15_out"; + gpios = <&smp2pgpio_smp2p_15_out 0 0>; + }; + + smp2pgpio_smp2p_1_in: qcom,smp2pgpio-smp2p-1-in { + compatible = "qcom,smp2pgpio"; + qcom,entry-name = "smp2p"; + qcom,remote-pid = <1>; + qcom,is-inbound; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + qcom,smp2pgpio_test_smp2p_1_in { + compatible = "qcom,smp2pgpio_test_smp2p_1_in"; + gpios = <&smp2pgpio_smp2p_1_in 0 0>; + }; + + smp2pgpio_smp2p_1_out: qcom,smp2pgpio-smp2p-1-out { + compatible = "qcom,smp2pgpio"; + qcom,entry-name = "smp2p"; + qcom,remote-pid = <1>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + qcom,smp2pgpio_test_smp2p_1_out { + compatible = "qcom,smp2pgpio_test_smp2p_1_out"; + gpios = <&smp2pgpio_smp2p_1_out 0 0>; + }; + + smp2pgpio_smp2p_2_in: qcom,smp2pgpio-smp2p-2-in { + compatible = "qcom,smp2pgpio"; + qcom,entry-name = "smp2p"; + qcom,remote-pid = <2>; + qcom,is-inbound; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + qcom,smp2pgpio_test_smp2p_2_in { + compatible = "qcom,smp2pgpio_test_smp2p_2_in"; + gpios = <&smp2pgpio_smp2p_2_in 0 0>; + }; + + smp2pgpio_smp2p_2_out: qcom,smp2pgpio-smp2p-2-out { + compatible = "qcom,smp2pgpio"; + qcom,entry-name = "smp2p"; + qcom,remote-pid = <2>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + qcom,smp2pgpio_test_smp2p_2_out { + compatible = "qcom,smp2pgpio_test_smp2p_2_out"; + gpios = <&smp2pgpio_smp2p_2_out 0 0>; + }; + + smp2pgpio_smp2p_3_in: qcom,smp2pgpio-smp2p-3-in { + compatible = "qcom,smp2pgpio"; + qcom,entry-name = "smp2p"; + qcom,remote-pid = <3>; + qcom,is-inbound; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + qcom,smp2pgpio_test_smp2p_3_in { + compatible = "qcom,smp2pgpio_test_smp2p_3_in"; + gpios = <&smp2pgpio_smp2p_3_in 0 0>; + }; + + smp2pgpio_smp2p_3_out: qcom,smp2pgpio-smp2p-3-out { + compatible = "qcom,smp2pgpio"; + qcom,entry-name = "smp2p"; + qcom,remote-pid = <3>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + /* ssr - inbound entry from mss */ + smp2pgpio_ssr_smp2p_1_in: qcom,smp2pgpio-ssr-smp2p-1-in { + compatible = "qcom,smp2pgpio"; + qcom,entry-name = "slave-kernel"; + qcom,remote-pid = <1>; + qcom,is-inbound; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + /* ssr - outbound entry to mss */ + smp2pgpio_ssr_smp2p_1_out: qcom,smp2pgpio-ssr-smp2p-1-out { + compatible = "qcom,smp2pgpio"; + qcom,entry-name = "master-kernel"; + qcom,remote-pid = <1>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + /* ssr - inbound entry from lpass */ + smp2pgpio_ssr_smp2p_2_in: qcom,smp2pgpio-ssr-smp2p-2-in { + compatible = "qcom,smp2pgpio"; + qcom,entry-name = "slave-kernel"; + qcom,remote-pid = <2>; + qcom,is-inbound; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + /* ssr - outbound entry to lpass */ + smp2pgpio_ssr_smp2p_2_out: qcom,smp2pgpio-ssr-smp2p-2-out { + compatible = "qcom,smp2pgpio"; + qcom,entry-name = "master-kernel"; + qcom,remote-pid = <2>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + /* ssr - inbound entry from ssc */ + smp2pgpio_ssr_smp2p_3_in: qcom,smp2pgpio-ssr-smp2p-3-in { + compatible = "qcom,smp2pgpio"; + qcom,entry-name = "slave-kernel"; + qcom,remote-pid = <3>; + qcom,is-inbound; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + /* ssr - outbound entry to ssc */ + smp2pgpio_ssr_smp2p_3_out: qcom,smp2pgpio-ssr-smp2p-3-out { + compatible = "qcom,smp2pgpio"; + qcom,entry-name = "master-kernel"; + qcom,remote-pid = <3>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + qcom,smp2pgpio_test_smp2p_3_out { + compatible = "qcom,smp2pgpio_test_smp2p_3_out"; + gpios = <&smp2pgpio_smp2p_3_out 0 0>; + }; + + smp2pgpio_sleepstate_3_out: qcom,smp2pgpio-sleepstate-gpio-3-out { + compatible = "qcom,smp2pgpio"; + qcom,entry-name = "sleepstate"; + qcom,remote-pid = <3>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + qcom,smp2pgpio-sleepstate-3-out { + compatible = "qcom,smp2pgpio_sleepstate_3_out"; + gpios = <&smp2pgpio_sleepstate_3_out 0 0>; + }; + + /* ipa - outbound entry to mss */ + smp2pgpio_ipa_1_out: qcom,smp2pgpio-ipa-1-out { + compatible = "qcom,smp2pgpio"; + qcom,entry-name = "ipa"; + qcom,remote-pid = <1>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + /* ipa - inbound entry from mss */ + smp2pgpio_ipa_1_in: qcom,smp2pgpio-ipa-1-in { + compatible = "qcom,smp2pgpio"; + qcom,entry-name = "ipa"; + qcom,remote-pid = <1>; + qcom,is-inbound; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; +}; --- /dev/null 2019-10-24 16:47:25.704025805 +0200 +++ linux-4.4.115-fbx/arch/arm64/boot/dts/qcom/msm8998-v2.1.dtsi 2019-01-22 16:16:21.199225542 +0100 @@ -0,0 +1,18 @@ +/* Copyright (c) 2016 The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "msm8998-v2.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. MSM8998 v2.1"; + qcom,msm-id = <292 0x20001>; +}; --- /dev/null 2019-10-24 16:47:25.704025805 +0200 +++ linux-4.4.115-fbx/arch/arm64/boot/dts/qcom/msm8998-v2-camera.dtsi 2019-01-22 16:16:21.199225542 +0100 @@ -0,0 +1,192 @@ +/* + * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&soc { + qcom,csiphy@ca34000 { + cell-index = <0>; + compatible = "qcom,csiphy-v5.01", "qcom,csiphy"; + reg = <0xca34000 0x1000>; + reg-names = "csiphy"; + interrupts = <0 78 0>; + interrupt-names = "csiphy"; + gdscr-supply = <&gdsc_camss_top>; + bimc_smmu-supply = <&gdsc_bimc_smmu>; + qcom,cam-vreg-name = "gdscr", "bimc_smmu"; + clocks = <&clock_gcc clk_mmssnoc_axi_clk>, + <&clock_mmss clk_mmss_mnoc_ahb_clk>, + <&clock_mmss clk_mmss_bimc_smmu_ahb_clk>, + <&clock_mmss clk_mmss_bimc_smmu_axi_clk>, + <&clock_mmss clk_mmss_camss_ahb_clk>, + <&clock_mmss clk_mmss_camss_top_ahb_clk>, + <&clock_mmss clk_csi0_clk_src>, + <&clock_mmss clk_mmss_camss_csi0_clk>, + <&clock_mmss clk_mmss_camss_cphy_csid0_clk>, + <&clock_mmss clk_csi0phytimer_clk_src>, + <&clock_mmss clk_mmss_camss_csi0phytimer_clk>, + <&clock_mmss clk_mmss_camss_ispif_ahb_clk>, + <&clock_mmss clk_csiphy_clk_src>, + <&clock_mmss clk_mmss_camss_csiphy0_clk>; + clock-names = "mmssnoc_axi", "mnoc_ahb", + "bmic_smmu_ahb", "bmic_smmu_axi", + "camss_ahb_clk", "camss_top_ahb_clk", + "csi_src_clk", "csi_clk", "cphy_csid_clk", + "csiphy_timer_src_clk", "csiphy_timer_clk", + "camss_ispif_ahb_clk", "csiphy_clk_src", "csiphy_clk"; + qcom,clock-rates = <0 0 0 0 0 0 274290000 0 0 200000000 0 + 0 274290000 0>; + status = "ok"; + }; + + qcom,csiphy@ca35000 { + cell-index = <1>; + compatible = "qcom,csiphy-v5.01", "qcom,csiphy"; + reg = <0xca35000 0x1000>; + reg-names = "csiphy"; + interrupts = <0 79 0>; + interrupt-names = "csiphy"; + gdscr-supply = <&gdsc_camss_top>; + bimc_smmu-supply = <&gdsc_bimc_smmu>; + qcom,cam-vreg-name = "gdscr", "bimc_smmu"; + clocks = <&clock_gcc clk_mmssnoc_axi_clk>, + <&clock_mmss clk_mmss_mnoc_ahb_clk>, + <&clock_mmss clk_mmss_bimc_smmu_ahb_clk>, + <&clock_mmss clk_mmss_bimc_smmu_axi_clk>, + <&clock_mmss clk_mmss_camss_ahb_clk>, + <&clock_mmss clk_mmss_camss_top_ahb_clk>, + <&clock_mmss clk_csi1_clk_src>, + <&clock_mmss clk_mmss_camss_csi1_clk>, + <&clock_mmss clk_mmss_camss_cphy_csid1_clk>, + <&clock_mmss clk_csi1phytimer_clk_src>, + <&clock_mmss clk_mmss_camss_csi1phytimer_clk>, + <&clock_mmss clk_mmss_camss_ispif_ahb_clk>, + <&clock_mmss clk_csiphy_clk_src>, + <&clock_mmss clk_mmss_camss_csiphy1_clk>; + clock-names = "mmssnoc_axi", "mnoc_ahb", + "bmic_smmu_ahb", "bmic_smmu_axi", + "camss_ahb_clk", "camss_top_ahb_clk", + "csi_src_clk", "csi_clk", "cphy_csid_clk", + "csiphy_timer_src_clk", "csiphy_timer_clk", + "camss_ispif_ahb_clk", "csiphy_clk_src", "csiphy_clk"; + qcom,clock-rates = <0 0 0 0 0 0 274290000 0 0 200000000 0 + 0 274290000 0>; + status = "ok"; + }; + + qcom,csiphy@ca36000 { + cell-index = <2>; + compatible = "qcom,csiphy-v5.01", "qcom,csiphy"; + reg = <0xca36000 0x1000>; + reg-names = "csiphy"; + interrupts = <0 80 0>; + interrupt-names = "csiphy"; + gdscr-supply = <&gdsc_camss_top>; + bimc_smmu-supply = <&gdsc_bimc_smmu>; + qcom,cam-vreg-name = "gdscr", "bimc_smmu"; + clocks = <&clock_gcc clk_mmssnoc_axi_clk>, + <&clock_mmss clk_mmss_mnoc_ahb_clk>, + <&clock_mmss clk_mmss_bimc_smmu_ahb_clk>, + <&clock_mmss clk_mmss_bimc_smmu_axi_clk>, + <&clock_mmss clk_mmss_camss_ahb_clk>, + <&clock_mmss clk_mmss_camss_top_ahb_clk>, + <&clock_mmss clk_csi2_clk_src>, + <&clock_mmss clk_mmss_camss_csi2_clk>, + <&clock_mmss clk_mmss_camss_cphy_csid2_clk>, + <&clock_mmss clk_csi2phytimer_clk_src>, + <&clock_mmss clk_mmss_camss_csi2phytimer_clk>, + <&clock_mmss clk_mmss_camss_ispif_ahb_clk>, + <&clock_mmss clk_csiphy_clk_src>, + <&clock_mmss clk_mmss_camss_csiphy2_clk>; + clock-names = "mmssnoc_axi", "mnoc_ahb", + "bmic_smmu_ahb", "bmic_smmu_axi", + "camss_ahb_clk", "camss_top_ahb_clk", + "csi_src_clk", "csi_clk", "cphy_csid_clk", + "csiphy_timer_src_clk", "csiphy_timer_clk", + "camss_ispif_ahb_clk", "csiphy_clk_src", "csiphy_clk"; + qcom,clock-rates = <0 0 0 0 0 0 274290000 0 0 200000000 0 + 0 274290000 0>; + status = "ok"; + }; + + qcom,cpp@ca04000 { + cell-index = <0>; + compatible = "qcom,cpp"; + reg = <0xca04000 0x100>, + <0xca80000 0x3000>, + <0xca18000 0x3000>, + <0xc8c36d4 0x4>; + reg-names = "cpp", "cpp_vbif", "cpp_hw", "camss_cpp"; + interrupts = <0 294 0>; + interrupt-names = "cpp"; + smmu-vdd-supply = <&gdsc_bimc_smmu>; + camss-vdd-supply = <&gdsc_camss_top>; + vdd-supply = <&gdsc_cpp>; + qcom,vdd-names = "smmu-vdd", "camss-vdd", "vdd"; + clocks = <&clock_gcc clk_mmssnoc_axi_clk>, + <&clock_mmss clk_mmss_mnoc_ahb_clk>, + <&clock_mmss clk_mmss_camss_ahb_clk>, + <&clock_mmss clk_mmss_camss_top_ahb_clk>, + <&clock_mmss clk_cpp_clk_src>, + <&clock_mmss clk_mmss_camss_cpp_clk>, + <&clock_mmss clk_mmss_camss_cpp_ahb_clk>, + <&clock_mmss clk_mmss_camss_cpp_axi_clk>, + <&clock_mmss clk_mmss_camss_micro_ahb_clk>, + <&clock_mmss clk_mmss_bimc_smmu_axi_clk>, + <&clock_mmss clk_mmss_camss_cpp_vbif_ahb_clk>; + clock-names = "mmssnoc_axi_clk", + "mnoc_ahb_clk", + "camss_ahb_clk", "camss_top_ahb_clk", + "cpp_src_clk", + "cpp_core_clk", "camss_cpp_ahb_clk", + "camss_cpp_axi_clk", "micro_iface_clk", + "mmss_smmu_axi_clk", "cpp_vbif_ahb_clk"; + qcom,clock-rates = <0 0 0 0 200000000 200000000 0 0 0 0 0>; + qcom,min-clock-rate = <200000000>; + qcom,bus-master = <1>; + qcom,vbif-qos-setting = <0x20 0x10000000>, + <0x24 0x10000000>, + <0x28 0x10000000>, + <0x2C 0x10000000>; + status = "ok"; + qcom,msm-bus,name = "msm_camera_cpp"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <106 512 0 0>, + <106 512 0 0>; + qcom,msm-bus-vector-dyn-vote; + resets = <&clock_mmss CAMSS_MICRO_BCR>; + reset-names = "micro_iface_reset"; + qcom,src-clock-rates = <100000000 200000000 384000000 404000000 + 480000000 576000000 600000000>; + qcom,micro-reset; + qcom,cpp-fw-payload-info { + qcom,stripe-base = <790>; + qcom,plane-base = <715>; + qcom,stripe-size = <63>; + qcom,plane-size = <25>; + qcom,fe-ptr-off = <11>; + qcom,we-ptr-off = <23>; + qcom,ref-fe-ptr-off = <17>; + qcom,ref-we-ptr-off = <36>; + qcom,we-meta-ptr-off = <42>; + qcom,fe-mmu-pf-ptr-off = <7>; + qcom,ref-fe-mmu-pf-ptr-off = <10>; + qcom,we-mmu-pf-ptr-off = <13>; + qcom,dup-we-mmu-pf-ptr-off = <18>; + qcom,ref-we-mmu-pf-ptr-off = <23>; + qcom,set-group-buffer-len = <135>; + qcom,dup-frame-indicator-off = <70>; + }; + }; +}; + --- /dev/null 2019-10-24 16:47:25.704025805 +0200 +++ linux-4.4.115-fbx/arch/arm64/boot/dts/qcom/msm8998-v2.dtsi 2019-01-22 16:16:21.203225578 +0100 @@ -0,0 +1,1312 @@ +/* Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * As a general rule, only version-specific property overrides should be placed + * inside this file. Common device definitions should be placed inside the + * msm8998.dtsi file. + */ + +#include "msm8998.dtsi" +#include "msm8998-v2-camera.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. MSM8998 v2"; + qcom,msm-id = <292 0x20000>; +}; + +&clock_cpu { + compatible = "qcom,cpu-clock-osm-msm8998-v2"; + reg = <0x179c0000 0x4000>, + <0x17916000 0x1000>, + <0x17816000 0x1000>, + <0x179d1000 0x1000>, + <0x17914800 0x800>, + <0x17814800 0x800>, + <0x00784130 0x8>, + <0x1791101c 0x8>; + reg-names = "osm", "pwrcl_pll", "perfcl_pll", + "apcs_common", "pwrcl_acd", "perfcl_acd", + "perfcl_efuse", "debug"; + + qcom,acdtd-val = <0x00009611 0x00009611>; + qcom,acdcr-val = <0x002b5ffd 0x002b5ffd>; + qcom,acdsscr-val = <0x00000501 0x00000501>; + qcom,acdextint0-val = <0x2cf9ae8 0x2cf9ae8>; + qcom,acdextint1-val = <0x2cf9afe 0x2cf9afe>; + qcom,acdautoxfer-val = <0x00000015 0x00000015>; + qcom,pwrcl-apcs-mem-acc-threshold-voltage = <852000>; + qcom,perfcl-apcs-mem-acc-threshold-voltage = <852000>; + qcom,apm-threshold-voltage = <800000>; + + /delete-property/ qcom,llm-sw-overr; + qcom,pwrcl-speedbin0-v0 = + < 300000000 0x0004000f 0x01200020 0x1 1 >, + < 364800000 0x05040013 0x01200020 0x1 2 >, + < 441600000 0x05040017 0x02200020 0x1 3 >, + < 518400000 0x0504001b 0x02200020 0x1 4 >, + < 595200000 0x0504001f 0x02200020 0x1 5 >, + < 672000000 0x05040023 0x03200020 0x1 6 >, + < 748800000 0x05040027 0x03200020 0x1 7 >, + < 825600000 0x0404002b 0x03220022 0x1 8 >, + < 883200000 0x0404002e 0x04250025 0x1 9 >, + < 960000000 0x04040032 0x04280028 0x1 10 >, + < 1036800000 0x04040036 0x042b002b 0x1 11 >, + < 1094400000 0x04040039 0x052e002e 0x2 12 >, + < 1171200000 0x0404003d 0x05310031 0x2 13 >, + < 1248000000 0x04040041 0x05340034 0x2 14 >, + < 1324800000 0x04040045 0x06370037 0x2 15 >, + < 1401600000 0x04040049 0x063a003a 0x2 16 >, + < 1478400000 0x0404004d 0x073e003e 0x2 17 >, + < 1555200000 0x04040051 0x07410041 0x2 18 >, + < 1670400000 0x04040057 0x08460046 0x2 19 >, + < 1747200000 0x0404005b 0x08490049 0x2 20 >, + < 1824000000 0x0404005f 0x084c004c 0x3 21 >, + < 1900800000 0x04040063 0x094f004f 0x3 22 >; + + qcom,perfcl-speedbin0-v0 = + < 300000000 0x0004000f 0x01200020 0x1 1 >, + < 345600000 0x05040012 0x01200020 0x1 2 >, + < 422400000 0x05040016 0x02200020 0x1 3 >, + < 499200000 0x0504001a 0x02200020 0x1 4 >, + < 576000000 0x0504001e 0x02200020 0x1 5 >, + < 652800000 0x05040022 0x03200020 0x1 6 >, + < 729600000 0x05040026 0x03200020 0x1 7 >, + < 806400000 0x0504002a 0x03220022 0x1 8 >, + < 902400000 0x0404002f 0x04260026 0x1 9 >, + < 979200000 0x04040033 0x04290029 0x1 10 >, + < 1056000000 0x04040037 0x052c002c 0x1 11 >, + < 1132800000 0x0404003b 0x052f002f 0x1 12 >, + < 1190400000 0x0404003e 0x05320032 0x2 13 >, + < 1267200000 0x04040042 0x06350035 0x2 14 >, + < 1344000000 0x04040046 0x06380038 0x2 15 >, + < 1420800000 0x0404004a 0x063b003b 0x2 16 >, + < 1497600000 0x0404004e 0x073e003e 0x2 17 >, + < 1574400000 0x04040052 0x07420042 0x2 18 >, + < 1651200000 0x04040056 0x07450045 0x2 19 >, + < 1728000000 0x0404005a 0x08480048 0x2 20 >, + < 1804800000 0x0404005e 0x084b004b 0x2 21 >, + < 1881600000 0x04040062 0x094e004e 0x2 22 >, + < 1958400000 0x04040066 0x09520052 0x2 23 >, + < 2035200000 0x0404006a 0x09550055 0x3 24 >, + < 2112000000 0x0404006e 0x0a580058 0x3 25 >, + < 2208000000 0x04040073 0x0a5c005c 0x3 26 >, + < 2265600000 0x04010076 0x0a5e005e 0x3 26 >, + < 2265600000 0x04040076 0x0a5e005e 0x3 27 >, + < 2342400000 0x0401007a 0x0a620062 0x3 27 >, + < 2342400000 0x0404007a 0x0a620062 0x3 28 >, + < 2419200000 0x0401007e 0x0a650065 0x3 28 >, + < 2419200000 0x0404007e 0x0a650065 0x3 29 >, + < 2496000000 0x04010082 0x0a680068 0x3 29 >, + < 2457600000 0x04040080 0x0a660066 0x3 30 >, + < 2553600000 0x04010085 0x0a6a006a 0x3 30 >, + < 2476800000 0x04040081 0x0a670067 0x3 31 >, + < 2572800000 0x04010086 0x0a6b006b 0x3 31 >, + < 2496000000 0x04040082 0x0a680068 0x3 32 >, + < 2592000000 0x04010087 0x0a6c006c 0x3 32 >; + + qcom,perfcl-speedbin1-v0 = + < 300000000 0x0004000f 0x01200020 0x1 1 >, + < 345600000 0x05040012 0x01200020 0x1 2 >, + < 422400000 0x05040016 0x02200020 0x1 3 >, + < 499200000 0x0504001a 0x02200020 0x1 4 >, + < 576000000 0x0504001e 0x02200020 0x1 5 >, + < 652800000 0x05040022 0x03200020 0x1 6 >, + < 729600000 0x05040026 0x03200020 0x1 7 >, + < 806400000 0x0504002a 0x03220022 0x1 8 >, + < 902400000 0x0404002f 0x04260026 0x1 9 >, + < 979200000 0x04040033 0x04290029 0x1 10 >, + < 1056000000 0x04040037 0x052c002c 0x1 11 >, + < 1132800000 0x0404003b 0x052f002f 0x1 12 >, + < 1190400000 0x0404003e 0x05320032 0x2 13 >, + < 1267200000 0x04040042 0x06350035 0x2 14 >, + < 1344000000 0x04040046 0x06380038 0x2 15 >, + < 1420800000 0x0404004a 0x063b003b 0x2 16 >, + < 1497600000 0x0404004e 0x073e003e 0x2 17 >, + < 1574400000 0x04040052 0x07420042 0x2 18 >, + < 1651200000 0x04040056 0x07450045 0x2 19 >, + < 1728000000 0x0404005a 0x08480048 0x2 20 >, + < 1804800000 0x0404005e 0x084b004b 0x2 21 >, + < 1881600000 0x04040062 0x094e004e 0x2 22 >, + < 1958400000 0x04040066 0x09520052 0x2 23 >, + < 2035200000 0x0404006a 0x09550055 0x3 24 >, + < 2112000000 0x0404006e 0x0a580058 0x3 25 >, + < 2208000000 0x04040073 0x0a5c005c 0x3 26 >, + < 2304000000 0x04010078 0x0a600060 0x3 26 >; + + qcom,perfcl-speedbin2-v0 = + < 300000000 0x0004000f 0x01200020 0x1 1 >, + < 345600000 0x05040012 0x01200020 0x1 2 >, + < 422400000 0x05040016 0x02200020 0x1 3 >, + < 499200000 0x0504001a 0x02200020 0x1 4 >, + < 576000000 0x0504001e 0x02200020 0x1 5 >, + < 652800000 0x05040022 0x03200020 0x1 6 >, + < 729600000 0x05040026 0x03200020 0x1 7 >, + < 806400000 0x0504002a 0x03220022 0x1 8 >, + < 902400000 0x0404002f 0x04260026 0x1 9 >, + < 979200000 0x04040033 0x04290029 0x1 10 >, + < 1056000000 0x04040037 0x052c002c 0x1 11 >, + < 1132800000 0x0404003b 0x052f002f 0x1 12 >, + < 1190400000 0x0404003e 0x05320032 0x2 13 >, + < 1267200000 0x04040042 0x06350035 0x2 14 >, + < 1344000000 0x04040046 0x06380038 0x2 15 >, + < 1420800000 0x0404004a 0x063b003b 0x2 16 >, + < 1497600000 0x0404004e 0x073e003e 0x2 17 >, + < 1574400000 0x04040052 0x07420042 0x2 18 >, + < 1651200000 0x04040056 0x07450045 0x2 19 >, + < 1728000000 0x0404005a 0x08480048 0x2 20 >, + < 1804800000 0x0404005e 0x084b004b 0x2 21 >, + < 1881600000 0x04040062 0x094e004e 0x2 22 >, + < 1958400000 0x04040066 0x09520052 0x2 23 >, + < 2035200000 0x0404006a 0x09550055 0x3 24 >, + < 2112000000 0x0404006e 0x0a580058 0x3 25 >, + < 2208000000 0x04040073 0x0a5c005c 0x3 26 >, + < 2265600000 0x04010076 0x0a5e005e 0x3 26 >, + < 2265600000 0x04040076 0x0a5e005e 0x3 27 >, + < 2342400000 0x0401007a 0x0a620062 0x3 27 >, + < 2323200000 0x04040079 0x0a610061 0x3 28 >, + < 2419200000 0x0401007e 0x0a650065 0x3 28 >, + < 2342400000 0x0404007a 0x0a620062 0x3 29 >, + < 2438400000 0x0401007f 0x0a660066 0x3 29 >, + < 2361600000 0x0404007b 0x0a620062 0x3 30 >, + < 2457600000 0x04010080 0x0a660066 0x3 30 >; + + qcom,perfcl-speedbin3-v0 = + < 300000000 0x0004000f 0x01200020 0x1 1 >, + < 345600000 0x05040012 0x01200020 0x1 2 >, + < 422400000 0x05040016 0x02200020 0x1 3 >, + < 499200000 0x0504001a 0x02200020 0x1 4 >, + < 576000000 0x0504001e 0x02200020 0x1 5 >, + < 652800000 0x05040022 0x03200020 0x1 6 >, + < 729600000 0x05040026 0x03200020 0x1 7 >, + < 806400000 0x0504002a 0x03220022 0x1 8 >, + < 902400000 0x0404002f 0x04260026 0x1 9 >, + < 979200000 0x04040033 0x04290029 0x1 10 >, + < 1056000000 0x04040037 0x052c002c 0x1 11 >, + < 1132800000 0x0404003b 0x052f002f 0x1 12 >, + < 1190400000 0x0404003e 0x05320032 0x2 13 >, + < 1267200000 0x04040042 0x06350035 0x2 14 >, + < 1344000000 0x04040046 0x06380038 0x2 15 >, + < 1420800000 0x0404004a 0x063b003b 0x2 16 >, + < 1497600000 0x0404004e 0x073e003e 0x2 17 >, + < 1574400000 0x04040052 0x07420042 0x2 18 >, + < 1651200000 0x04040056 0x07450045 0x2 19 >, + < 1728000000 0x0404005a 0x08480048 0x2 20 >, + < 1804800000 0x0404005e 0x084b004b 0x2 21 >, + < 1881600000 0x04040062 0x094e004e 0x2 22 >, + < 1958400000 0x04040066 0x09520052 0x2 23 >, + < 2035200000 0x0404006a 0x09550055 0x3 24 >, + < 2112000000 0x0404006e 0x0a580058 0x3 25 >, + < 2208000000 0x04040073 0x0a5c005c 0x3 26 >, + < 2265600000 0x04010076 0x0a5e005e 0x3 26 >, + < 2265600000 0x04040076 0x0a5e005e 0x3 27 >, + < 2342400000 0x0401007a 0x0a620062 0x3 27 >, + < 2323200000 0x04040079 0x0a610061 0x3 28 >, + < 2419200000 0x0401007e 0x0a650065 0x3 28 >, + < 2342400000 0x0404007a 0x0a620062 0x3 29 >, + < 2438400000 0x0401007f 0x0a660066 0x3 29 >, + < 2361600000 0x0404007b 0x0a620062 0x3 30 >, + < 2457600000 0x04010080 0x0a660066 0x3 30 >; +}; + +&msm_cpufreq { + qcom,cpufreq-table-0 = + < 300000 >, + < 364800 >, + < 441600 >, + < 518400 >, + < 595200 >, + < 672000 >, + < 748800 >, + < 825600 >, + < 883200 >, + < 960000 >, + < 1036800 >, + < 1094400 >, + < 1171200 >, + < 1248000 >, + < 1324800 >, + < 1401600 >, + < 1478400 >, + < 1555200 >, + < 1670400 >, + < 1747200 >, + < 1824000 >, + < 1900800 >; + + qcom,cpufreq-table-4 = + < 300000 >, + < 345600 >, + < 422400 >, + < 499200 >, + < 576000 >, + < 652800 >, + < 729600 >, + < 806400 >, + < 902400 >, + < 979200 >, + < 1056000 >, + < 1132800 >, + < 1190400 >, + < 1267200 >, + < 1344000 >, + < 1420800 >, + < 1497600 >, + < 1574400 >, + < 1651200 >, + < 1728000 >, + < 1804800 >, + < 1881600 >, + < 1958400 >, + < 2035200 >, + < 2112000 >, + < 2208000 >, + < 2265600 >, + < 2304000 >, + < 2323200 >, + < 2342400 >, + < 2361600 >, + < 2419200 >, + < 2457600 >, + < 2476800 >, + < 2496000 >, + < 2592000 >; +}; + +&bwmon { + compatible = "qcom,bimc-bwmon4"; + qcom,hw-timer-hz = <19200000>; +}; + +&devfreq_cpufreq { + mincpubw-cpufreq { + cpu-to-dev-map-0 = + < 1900800 1525 >; + cpu-to-dev-map-4 = + < 2112000 1525 >, + < 2342400 5195 >, + < 2496000 13763 >; + }; +}; + +&devfreq_memlat_0 { + qcom,core-dev-table = + < 300000 1525 >, + < 595200 3143 >, + < 1324800 4173 >, + < 1555200 5859 >, + < 1747200 5859 >, + < 1900800 7759 >; +}; + +&devfreq_memlat_4 { + qcom,core-dev-table = + < 576000 3143 >, + < 1132800 4173 >, + < 1344000 5859 >, + < 1728000 7759 >, + < 1958400 11863 >, + < 2208000 13763 >; +}; +&clock_gcc { + compatible = "qcom,gcc-8998-v2"; +}; + +&clock_mmss { + compatible = "qcom,mmsscc-8998-v2"; +}; + +&clock_gpu { + compatible = "qcom,gpucc-8998-v2"; +}; + +&clock_gfx { + compatible = "qcom,gfxcc-8998-v2"; + qcom,gfxfreq-speedbin0 = + < 0 0 0 >, + < 180000000 1 RPM_SMD_REGULATOR_LEVEL_SVS >, + < 257000000 2 RPM_SMD_REGULATOR_LEVEL_SVS >, + < 342000000 3 RPM_SMD_REGULATOR_LEVEL_SVS >, + < 414000000 4 RPM_SMD_REGULATOR_LEVEL_SVS >, + < 515000000 5 RPM_SMD_REGULATOR_LEVEL_NOM >, + < 596000000 6 RPM_SMD_REGULATOR_LEVEL_NOM >, + < 670000000 7 RPM_SMD_REGULATOR_LEVEL_TURBO >, + < 710000000 8 RPM_SMD_REGULATOR_LEVEL_TURBO >; + qcom,gfxfreq-mx-speedbin0 = + < 0 0 >, + < 180000000 RPM_SMD_REGULATOR_LEVEL_SVS >, + < 257000000 RPM_SMD_REGULATOR_LEVEL_SVS >, + < 342000000 RPM_SMD_REGULATOR_LEVEL_SVS >, + < 414000000 RPM_SMD_REGULATOR_LEVEL_SVS >, + < 515000000 RPM_SMD_REGULATOR_LEVEL_NOM >, + < 596000000 RPM_SMD_REGULATOR_LEVEL_NOM >, + < 670000000 RPM_SMD_REGULATOR_LEVEL_TURBO >, + < 710000000 RPM_SMD_REGULATOR_LEVEL_TURBO >; +}; + +&pm8998_s10 { + regulator-min-microvolt = <568000>; + regulator-max-microvolt = <1056000>; +}; + +&pm8998_s13 { + regulator-min-microvolt = <568000>; + regulator-max-microvolt = <1136000>; +}; + +&pcie0 { + qcom,phy-sequence = <0x804 0x01 0x00 + 0x034 0x14 0x00 + 0x138 0x30 0x00 + 0x048 0x0f 0x00 + 0x15c 0x06 0x00 + 0x090 0x01 0x00 + 0x088 0x20 0x00 + 0x0f0 0x00 0x00 + 0x0f8 0x01 0x00 + 0x0f4 0xc9 0x00 + 0x11c 0xff 0x00 + 0x120 0x3f 0x00 + 0x164 0x01 0x00 + 0x154 0x00 0x00 + 0x148 0x0a 0x00 + 0x05C 0x19 0x00 + 0x038 0x90 0x00 + 0x0b0 0x82 0x00 + 0x0c0 0x03 0x00 + 0x0bc 0x55 0x00 + 0x0b8 0x55 0x00 + 0x0a0 0x00 0x00 + 0x09c 0x0d 0x00 + 0x098 0x04 0x00 + 0x13c 0x00 0x00 + 0x060 0x08 0x00 + 0x068 0x16 0x00 + 0x070 0x34 0x00 + 0x15c 0x06 0x00 + 0x138 0x33 0x00 + 0x03c 0x02 0x00 + 0x040 0x07 0x00 + 0x080 0x04 0x00 + 0x0dc 0x00 0x00 + 0x0d8 0x3f 0x00 + 0x00c 0x09 0x00 + 0x010 0x01 0x00 + 0x01c 0x40 0x00 + 0x020 0x01 0x00 + 0x014 0x02 0x00 + 0x018 0x00 0x00 + 0x024 0x7e 0x00 + 0x028 0x15 0x00 + 0x244 0x02 0x00 + 0x2a4 0x12 0x00 + 0x260 0x10 0x00 + 0x28c 0x06 0x00 + 0x504 0x03 0x00 + 0x500 0x1c 0x00 + 0x50c 0x14 0x00 + 0x4d4 0x0a 0x00 + 0x4d8 0x04 0x00 + 0x4dc 0x1a 0x00 + 0x434 0x4b 0x00 + 0x414 0x04 0x00 + 0x40c 0x04 0x00 + 0x4f8 0x00 0x00 + 0x4fc 0x80 0x00 + 0x51c 0x40 0x00 + 0x444 0x71 0x00 + 0x43c 0x40 0x00 + 0x854 0x04 0x00 + 0x62c 0x52 0x00 + 0x9ac 0x00 0x00 + 0x8a0 0x01 0x00 + 0x9e0 0x00 0x00 + 0x9dc 0x20 0x00 + 0x9a8 0x00 0x00 + 0x8a4 0x01 0x00 + 0x8a8 0x73 0x00 + 0x9d8 0x99 0x00 + 0x9b0 0x03 0x00 + 0x804 0x03 0x00 + 0x800 0x00 0x00 + 0x808 0x03 0x00>; +}; + +&apc0_cpr { + compatible = "qcom,cprh-msm8998-v2-kbss-regulator"; + qcom,cpr-corner-switch-delay-time = <1042>; + qcom,cpr-aging-ref-voltage = <1056000>; + qcom,apm-threshold-voltage = <800000>; + qcom,apm-hysteresis-voltage = <0>; + qcom,mem-acc-threshold-voltage = <852000>; + qcom,mem-acc-crossover-voltage = <852000>; +}; + +&apc0_pwrcl_vreg { + regulator-max-microvolt = <23>; + + qcom,cpr-fuse-combos = <32>; + qcom,cpr-speed-bins = <4>; + qcom,cpr-speed-bin-corners = <22 22 22 22>; + qcom,cpr-corners = <22>; + + qcom,cpr-corner-fmax-map = <8 11 18 22>; + + qcom,cpr-voltage-ceiling = + <828000 828000 828000 828000 828000 + 828000 828000 828000 828000 828000 + 828000 900000 900000 900000 900000 + 900000 900000 900000 952000 952000 + 1056000 1056000>; + + qcom,cpr-voltage-floor = + <568000 568000 568000 568000 568000 + 568000 568000 568000 568000 568000 + 568000 632000 632000 632000 632000 + 632000 632000 632000 712000 712000 + 772000 772000>; + + qcom,cpr-floor-to-ceiling-max-range = + <32000 32000 32000 32000 + 32000 32000 32000 32000 + 32000 32000 32000 32000 + 32000 32000 32000 32000 + 32000 32000 40000 40000 + 40000 40000>; + + qcom,corner-frequencies = + <300000000 364800000 441600000 + 518400000 595200000 672000000 + 748800000 825600000 883200000 + 960000000 1036800000 1094400000 + 1171200000 1248000000 1324800000 + 1401600000 1478400000 1555200000 + 1670400000 1747200000 1824000000 + 1900800000>; + + qcom,cpr-ro-scaling-factor = + <2595 2794 2577 2762 2471 2674 2199 + 2553 3189 3255 3192 2962 3054 2982 + 2042 2945>, + <2595 2794 2577 2762 2471 2674 2199 + 2553 3189 3255 3192 2962 3054 2982 + 2042 2945>, + <2391 2550 2483 2638 2382 2564 2259 + 2555 2766 3041 2988 2935 2873 2688 + 2013 2784>, + <2066 2153 2300 2434 2220 2386 2288 + 2465 2028 2511 2487 2734 2554 2117 + 1892 2377>; + + qcom,cpr-open-loop-voltage-fuse-adjustment = + /* Speed bin 0 */ + <40000 24000 12000 30000>, + <40000 24000 12000 30000>, + <40000 24000 12000 30000>, + <40000 24000 12000 30000>, + <40000 24000 12000 30000>, + <40000 24000 12000 30000>, + <40000 24000 12000 30000>, + <40000 24000 12000 30000>, + /* Speed bin 1 */ + <40000 24000 12000 30000>, + <40000 24000 12000 30000>, + <40000 24000 12000 30000>, + <40000 24000 12000 30000>, + <40000 24000 12000 30000>, + <40000 24000 12000 30000>, + <40000 24000 12000 30000>, + <40000 24000 12000 30000>, + /* Speed bin 2 */ + <40000 24000 12000 30000>, + <40000 24000 12000 30000>, + <40000 24000 12000 30000>, + <40000 24000 12000 30000>, + <40000 24000 12000 30000>, + <40000 24000 12000 30000>, + <40000 24000 12000 30000>, + <40000 24000 12000 30000>, + /* Speed bin 3 */ + <40000 24000 12000 30000>, + <40000 24000 12000 30000>, + <40000 24000 12000 30000>, + <40000 24000 12000 30000>, + <40000 24000 12000 30000>, + <40000 24000 12000 30000>, + <40000 24000 12000 30000>, + <40000 24000 12000 30000>; + + qcom,cpr-closed-loop-voltage-fuse-adjustment = + /* Speed bin 0 */ + <20000 26000 12000 30000>, + <20000 26000 12000 30000>, + <20000 26000 12000 30000>, + <20000 26000 12000 30000>, + <20000 26000 12000 30000>, + <20000 26000 12000 30000>, + <20000 26000 12000 30000>, + <20000 26000 12000 30000>, + /* Speed bin 1 */ + <20000 26000 12000 30000>, + <20000 26000 12000 30000>, + <20000 26000 12000 30000>, + <20000 26000 12000 30000>, + <20000 26000 12000 30000>, + <20000 26000 12000 30000>, + <20000 26000 12000 30000>, + <20000 26000 12000 30000>, + /* Speed bin 2 */ + <20000 26000 12000 30000>, + <20000 26000 12000 30000>, + <20000 26000 12000 30000>, + <20000 26000 12000 30000>, + <20000 26000 12000 30000>, + <20000 26000 12000 30000>, + <20000 26000 12000 30000>, + <20000 26000 12000 30000>, + /* Speed bin 3 */ + <20000 26000 12000 30000>, + <20000 26000 12000 30000>, + <20000 26000 12000 30000>, + <20000 26000 12000 30000>, + <20000 26000 12000 30000>, + <20000 26000 12000 30000>, + <20000 26000 12000 30000>, + <20000 26000 12000 30000>; + + qcom,cpr-open-loop-voltage-adjustment = + /* Speed bin 0 */ + < 0 0 0 0 0 + 0 0 0 0 0 + 0 (-12000) (-12000) (-12000) (-12000) + (-12000) (-16000) (-16000) (-20000) (-24000) + (-28000) (-28000)>, + /* Speed bin 1 */ + < 0 0 0 0 0 + 0 0 0 0 0 + 0 (-12000) (-12000) (-12000) (-12000) + (-12000) (-16000) (-16000) (-20000) (-24000) + (-28000) (-28000)>, + /* Speed bin 2 */ + < 0 0 0 0 0 + 0 0 0 0 0 + 0 (-12000) (-12000) (-12000) (-12000) + (-12000) (-16000) (-16000) (-20000) (-24000) + (-28000) (-28000)>, + /* Speed bin 3 */ + < 0 0 0 0 0 + 0 0 0 0 0 + 0 (-12000) (-12000) (-12000) (-12000) + (-12000) (-16000) (-16000) (-20000) (-24000) + (-28000) (-28000)>; + + qcom,cpr-closed-loop-voltage-adjustment = + /* Speed bin 0 */ + < 0 0 0 0 0 + 0 0 0 0 0 + 0 (-10000) (-11000) (-12000) (-13000) + (-14000) (-14000) (-15000) (-21000) (-24000) + (-26000) (-28000)>, + /* Speed bin 1 */ + < 0 0 0 0 0 + 0 0 0 0 0 + 0 (-10000) (-11000) (-12000) (-13000) + (-14000) (-14000) (-15000) (-21000) (-24000) + (-26000) (-28000)>, + /* Speed bin 2 */ + < 0 0 0 0 0 + 0 0 0 0 0 + 0 (-10000) (-11000) (-12000) (-13000) + (-14000) (-14000) (-15000) (-21000) (-24000) + (-26000) (-28000)>, + /* Speed bin 3 */ + < 0 0 0 0 0 + 0 0 0 0 0 + 0 (-10000) (-11000) (-12000) (-13000) + (-14000) (-14000) (-15000) (-21000) (-24000) + (-26000) (-28000)>; + + qcom,allow-voltage-interpolation; + qcom,allow-quotient-interpolation; + qcom,cpr-scaled-open-loop-voltage-as-ceiling; + + qcom,cpr-aging-ref-corner = <22>; + qcom,cpr-aging-ro-scaling-factor = <1620>; + qcom,allow-aging-voltage-adjustment = <0>; +}; + +&apc1_cpr { + compatible = "qcom,cprh-msm8998-v2-kbss-regulator"; + qcom,cpr-corner-switch-delay-time = <1042>; + qcom,cpr-aging-ref-voltage = <1136000>; + qcom,apm-threshold-voltage = <800000>; + qcom,apm-hysteresis-voltage = <0>; + qcom,mem-acc-threshold-voltage = <852000>; + qcom,mem-acc-crossover-voltage = <852000>; +}; + +&apc1_perfcl_vreg { + regulator-max-microvolt = <34>; + + qcom,cpr-fuse-combos = <32>; + qcom,cpr-speed-bins = <4>; + qcom,cpr-speed-bin-corners = <32 26 30 31>; + qcom,cpr-corners = + /* Speed bin 0 */ + <32 32 32 32 32 32 32 32>, + /* Speed bin 1 */ + <26 26 26 26 26 26 26 26>, + /* Speed bin 2 */ + <30 30 30 30 30 30 30 30>, + /* Speed bin 3 */ + <31 31 31 31 31 31 31 31>; + + qcom,cpr-corner-fmax-map = + /* Speed bin 0 */ + <8 12 20 32>, + /* Speed bin 1 */ + <8 12 20 26>, + /* Speed bin 2 */ + <8 12 20 30>, + /* Speed bin 3 */ + <8 12 20 31>; + + qcom,cpr-voltage-ceiling = + /* Speed bin 0 */ + <828000 828000 828000 828000 828000 + 828000 828000 828000 828000 828000 + 828000 828000 900000 900000 900000 + 900000 900000 900000 900000 900000 + 952000 952000 952000 1136000 1136000 + 1136000 1136000 1136000 1136000 1136000 + 1136000 1136000>, + /* Speed bin 1 */ + <828000 828000 828000 828000 828000 + 828000 828000 828000 828000 828000 + 828000 828000 900000 900000 900000 + 900000 900000 900000 900000 900000 + 952000 952000 952000 1136000 1136000 + 1136000>, + /* Speed bin 2 */ + <828000 828000 828000 828000 828000 + 828000 828000 828000 828000 828000 + 828000 828000 900000 900000 900000 + 900000 900000 900000 900000 900000 + 952000 952000 952000 1136000 1136000 + 1136000 1136000 1136000 1136000 1136000>, + /* Speed bin 3 */ + <828000 828000 828000 828000 828000 + 828000 828000 828000 828000 828000 + 828000 828000 900000 900000 900000 + 900000 900000 900000 900000 900000 + 952000 952000 952000 1136000 1136000 + 1136000 1136000 1136000 1136000 1136000 + 1136000>; + + qcom,cpr-voltage-floor = + /* Speed bin 0 */ + <568000 568000 568000 568000 568000 + 568000 568000 568000 568000 568000 + 568000 568000 632000 632000 632000 + 632000 632000 632000 632000 632000 + 712000 712000 712000 772000 772000 + 772000 772000 772000 772000 772000 + 772000 772000>, + /* Speed bin 1 */ + <568000 568000 568000 568000 568000 + 568000 568000 568000 568000 568000 + 568000 568000 632000 632000 632000 + 632000 632000 632000 632000 632000 + 712000 712000 712000 772000 772000 + 772000>, + /* Speed bin 2 */ + <568000 568000 568000 568000 568000 + 568000 568000 568000 568000 568000 + 568000 568000 632000 632000 632000 + 632000 632000 632000 632000 632000 + 712000 712000 712000 772000 772000 + 772000 772000 772000 772000 772000>, + /* Speed bin 3 */ + <568000 568000 568000 568000 568000 + 568000 568000 568000 568000 568000 + 568000 568000 632000 632000 632000 + 632000 632000 632000 632000 632000 + 712000 712000 712000 772000 772000 + 772000 772000 772000 772000 772000 + 772000>; + + qcom,cpr-floor-to-ceiling-max-range = + /* Speed bin 0 */ + <32000 32000 32000 32000 + 32000 32000 32000 32000 + 32000 32000 32000 32000 + 32000 32000 32000 32000 + 32000 32000 32000 32000 + 40000 40000 40000 40000 + 40000 40000 40000 40000 + 40000 40000 40000 40000>, + /* Speed bin 1 */ + <32000 32000 32000 32000 + 32000 32000 32000 32000 + 32000 32000 32000 32000 + 32000 32000 32000 32000 + 32000 32000 32000 32000 + 40000 40000 40000 40000 + 40000 40000>, + /* Speed bin 2 */ + <32000 32000 32000 32000 + 32000 32000 32000 32000 + 32000 32000 32000 32000 + 32000 32000 32000 32000 + 32000 32000 32000 32000 + 40000 40000 40000 40000 + 40000 40000 40000 40000 + 40000 40000>, + /* Speed bin 3 */ + <32000 32000 32000 32000 + 32000 32000 32000 32000 + 32000 32000 32000 32000 + 32000 32000 32000 32000 + 32000 32000 32000 32000 + 40000 40000 40000 40000 + 40000 40000 40000 40000 + 40000 40000 40000>; + + qcom,corner-frequencies = + /* Speed bin 0 */ + <300000000 345600000 422400000 + 499200000 576000000 652800000 + 729600000 806400000 902400000 + 979200000 1056000000 1132800000 + 1190400000 1267200000 1344000000 + 1420800000 1497600000 1574400000 + 1651200000 1728000000 1804800000 + 1881600000 1958400000 2035200000 + 2112000000 2208000000 2265600000 + 2342400000 2419200000 2457600000 + 2476800000 2496000000>, + /* Speed bin 1 */ + <300000000 345600000 422400000 + 499200000 576000000 652800000 + 729600000 806400000 902400000 + 979200000 1056000000 1132800000 + 1190400000 1267200000 1344000000 + 1420800000 1497600000 1574400000 + 1651200000 1728000000 1804800000 + 1881600000 1958400000 2035200000 + 2112000000 2208000000>, + /* Speed bin 2 */ + <300000000 345600000 422400000 + 499200000 576000000 652800000 + 729600000 806400000 902400000 + 979200000 1056000000 1132800000 + 1190400000 1267200000 1344000000 + 1420800000 1497600000 1574400000 + 1651200000 1728000000 1804800000 + 1881600000 1958400000 2035200000 + 2112000000 2208000000 2265600000 + 2323200000 2342400000 2361600000>, + /* Speed bin 3 */ + <300000000 345600000 422400000 + 499200000 576000000 652800000 + 729600000 806400000 902400000 + 979200000 1056000000 1132800000 + 1190400000 1267200000 1344000000 + 1420800000 1497600000 1574400000 + 1651200000 1728000000 1804800000 + 1881600000 1958400000 2035200000 + 2112000000 2208000000 2265600000 + 2323200000 2342400000 2361600000 + 2457600000>; + + qcom,cpr-ro-scaling-factor = + <2857 3057 2828 2952 2699 2798 2446 + 2631 2629 2578 2244 3344 3289 3137 + 3164 2655>, + <2857 3057 2828 2952 2699 2798 2446 + 2631 2629 2578 2244 3344 3289 3137 + 3164 2655>, + <2603 2755 2676 2777 2573 2685 2465 + 2610 2312 2423 2243 3104 3022 3036 + 2740 2303>, + <1901 2016 2096 2228 2034 2161 2077 + 2188 1565 1870 1925 2235 2205 2413 + 1762 1478>; + + qcom,cpr-open-loop-voltage-fuse-adjustment = + /* Speed bin 0 */ + < 8000 0 12000 52000>, + < 8000 0 12000 52000>, + < 8000 0 12000 52000>, + < 8000 0 12000 52000>, + < 8000 0 12000 52000>, + < 8000 0 12000 52000>, + < 8000 0 12000 52000>, + < 8000 0 12000 52000>, + /* Speed bin 1 */ + < 8000 0 12000 52000>, + < 8000 0 12000 52000>, + < 8000 0 12000 52000>, + < 8000 0 12000 52000>, + < 8000 0 12000 52000>, + < 8000 0 12000 52000>, + < 8000 0 12000 52000>, + < 8000 0 12000 52000>, + /* Speed bin 2 */ + < 8000 0 12000 52000>, + < 8000 0 12000 52000>, + < 8000 0 12000 52000>, + < 8000 0 12000 52000>, + < 8000 0 12000 52000>, + < 8000 0 12000 52000>, + < 8000 0 12000 52000>, + < 8000 0 12000 52000>, + /* Speed bin 3 */ + < 8000 0 12000 52000>, + < 8000 0 12000 52000>, + < 8000 0 12000 52000>, + < 8000 0 12000 52000>, + < 8000 0 12000 52000>, + < 8000 0 12000 52000>, + < 8000 0 12000 52000>, + < 8000 0 12000 52000>; + + qcom,cpr-closed-loop-voltage-fuse-adjustment = + /* Speed bin 0 */ + < 0 0 12000 50000>, + < 0 0 12000 50000>, + < 0 0 12000 50000>, + < 0 0 12000 50000>, + < 0 0 12000 50000>, + < 0 0 12000 50000>, + < 0 0 12000 50000>, + < 0 0 12000 50000>, + /* Speed bin 1 */ + < 0 0 12000 50000>, + < 0 0 12000 50000>, + < 0 0 12000 50000>, + < 0 0 12000 50000>, + < 0 0 12000 50000>, + < 0 0 12000 50000>, + < 0 0 12000 50000>, + < 0 0 12000 50000>, + /* Speed bin 2 */ + < 0 0 12000 50000>, + < 0 0 12000 50000>, + < 0 0 12000 50000>, + < 0 0 12000 50000>, + < 0 0 12000 50000>, + < 0 0 12000 50000>, + < 0 0 12000 50000>, + < 0 0 12000 50000>, + /* Speed bin 3 */ + < 0 0 12000 50000>, + < 0 0 12000 50000>, + < 0 0 12000 50000>, + < 0 0 12000 50000>, + < 0 0 12000 50000>, + < 0 0 12000 50000>, + < 0 0 12000 50000>, + < 0 0 12000 50000>; + + qcom,cpr-open-loop-voltage-adjustment = + /* Speed bin 0 */ + < 0 0 0 0 0 + 0 0 0 0 0 + 0 (-8000) (-12000) (-12000) (-12000) + (-12000) (-12000) (-12000) (-16000) (-16000) + (-20000) (-16000) (-16000) (-16000) (-12000) + (-28000) (-28000) (-28000) (-28000) (-28000) + (-28000) (-28000)>, + /* Speed bin 1 */ + < 0 0 0 0 0 + 0 0 0 0 0 + 0 (-8000) (-12000) (-12000) (-12000) + (-12000) (-12000) (-12000) (-16000) (-16000) + (-20000) (-16000) (-16000) (-16000) (-16000) + (-28000)>, + /* Speed bin 2 */ + < 0 0 0 0 0 + 0 0 0 0 0 + 0 (-8000) (-12000) (-12000) (-12000) + (-12000) (-12000) (-12000) (-16000) (-16000) + (-20000) (-16000) (-16000) (-16000) (-12000) + (-28000) (-28000) (-28000) (-28000) (-28000)>, + /* Speed bin 3 */ + < 0 0 0 0 0 + 0 0 0 0 0 + 0 (-8000) (-12000) (-12000) (-12000) + (-12000) (-12000) (-12000) (-16000) (-16000) + (-20000) (-16000) (-16000) (-16000) (-12000) + (-28000) (-28000) (-28000) (-28000) (-28000) + (-28000)>; + + qcom,cpr-closed-loop-voltage-adjustment = + /* Speed bin 0 */ + < 0 0 0 0 0 + 0 0 0 0 0 + 0 (-10000) (-10000) (-11000) (-12000) + (-12000) (-13000) (-14000) (-14000) (-15000) + (-16000) (-16000) (-17000) (-15000) (-13000) + (-26000) (-26000) (-27000) (-27000) (-28000) + (-28000) (-28000)>, + /* Speed bin 1 */ + < 0 0 0 0 0 + 0 0 0 0 0 + 0 (-10000) (-10000) (-11000) (-12000) + (-12000) (-13000) (-14000) (-14000) (-15000) + (-16000) (-16000) (-17000) (-16000) (-15000) + (-28000)>, + /* Speed bin 2 */ + < 0 0 0 0 0 + 0 0 0 0 0 + 0 (-10000) (-10000) (-11000) (-12000) + (-12000) (-13000) (-14000) (-14000) (-15000) + (-16000) (-16000) (-17000) (-15000) (-14000) + (-27000) (-27000) (-28000) (-28000) (-28000)>, + /* Speed bin 3 */ + < 0 0 0 0 0 + 0 0 0 0 0 + 0 (-10000) (-10000) (-11000) (-12000) + (-12000) (-13000) (-14000) (-14000) (-15000) + (-16000) (-16000) (-17000) (-15000) (-14000) + (-26000) (-27000) (-27000) (-28000) (-28000) + (-28000)>; + + qcom,allow-voltage-interpolation; + qcom,allow-quotient-interpolation; + qcom,cpr-scaled-open-loop-voltage-as-ceiling; + + qcom,cpr-aging-ref-corner = <32 26 30 31>; + qcom,cpr-aging-ro-scaling-factor = <1700>; + qcom,allow-aging-voltage-adjustment = <0>; +}; + +&pm8005_s1 { + regulator-min-microvolt = <516000>; + regulator-max-microvolt = <1088000>; +}; + +&gfx_cpr { + compatible = "qcom,cpr4-msm8998-v2-mmss-regulator"; + qcom,cpr-aging-ref-voltage = <1088000>; +}; + +&gfx_vreg { + regulator-min-microvolt = <1>; + regulator-max-microvolt = <8>; + + qcom,cpr-fuse-corners = <4>; + qcom,cpr-fuse-combos = <8>; + qcom,cpr-corners = <8>; + + qcom,cpr-corner-fmax-map = <1 3 5 8>; + + qcom,cpr-voltage-ceiling = + <716000 716000 772000 880000 908000 948000 1016000 1088000>, + <724000 724000 772000 832000 916000 968000 1024000 1088000>, + <724000 724000 772000 832000 916000 968000 1024000 1088000>, + <724000 724000 772000 832000 916000 968000 1024000 1088000>, + <724000 724000 772000 832000 916000 968000 1024000 1088000>, + <724000 724000 772000 832000 916000 968000 1024000 1088000>, + <724000 724000 772000 832000 916000 968000 1024000 1088000>, + <724000 724000 772000 832000 916000 968000 1024000 1088000>; + + qcom,cpr-voltage-floor = + <516000 516000 532000 584000 632000 672000 712000 756000>; + + qcom,mem-acc-voltage = <1 1 1 2 2 2 2 2>; + + qcom,corner-frequencies = + <180000000 257000000 342000000 414000000 + 515000000 596000000 670000000 710000000>; + + qcom,cpr-target-quotients = + < 0 0 0 0 331 357 0 0 + 0 0 0 0 0 0 115 0>, + < 0 0 0 0 467 500 0 0 + 0 0 0 0 0 0 199 0>, + < 0 0 0 0 628 665 0 0 + 0 0 0 0 0 0 290 0>, + < 0 0 0 0 762 805 0 0 + 0 0 0 0 0 0 397 0>, + < 0 0 0 0 964 1013 0 0 + 0 0 1143 0 1138 1055 0 0>, + < 0 0 0 0 0 0 0 0 + 0 0 1306 0 1289 1168 0 0>, + < 0 0 0 0 0 0 0 0 + 0 0 1468 0 1429 1256 0 0>, + < 0 0 0 0 0 0 0 0 + 0 0 1627 0 1578 1353 0 0>; + + qcom,cpr-ro-scaling-factor = + < 0 0 0 0 2377 2571 0 0 + 0 0 2168 0 2209 1849 1997 0>, + < 0 0 0 0 2377 2571 0 0 + 0 0 2168 0 2209 1849 1997 0>, + < 0 0 0 0 2377 2571 0 0 + 0 0 2168 0 2209 1849 1997 0>, + < 0 0 0 0 2377 2571 0 0 + 0 0 2168 0 2209 1849 1997 0>, + < 0 0 0 0 2377 2571 0 0 + 0 0 2168 0 2209 1849 1997 0>, + < 0 0 0 0 2377 2571 0 0 + 0 0 2168 0 2209 1849 1997 0>, + < 0 0 0 0 2377 2571 0 0 + 0 0 2168 0 2209 1849 1997 0>, + < 0 0 0 0 2377 2571 0 0 + 0 0 2168 0 2209 1849 1997 0>; + + qcom,cpr-open-loop-voltage-fuse-adjustment = + < 60000 0 0 0>, + < 60000 0 0 0>, + < 60000 0 0 0>, + < 60000 0 0 0>, + < 60000 0 0 0>, + < 60000 0 0 0>, + < 60000 0 0 0>, + < 60000 0 0 0>; + + qcom,cpr-closed-loop-voltage-adjustment = + < 90000 38000 28000 8000 + 0 29000 11000 0>, + < 90000 38000 28000 8000 + 0 29000 11000 0>, + < 90000 38000 28000 8000 + 0 29000 11000 0>, + < 90000 38000 28000 8000 + 0 29000 11000 0>, + < 90000 38000 28000 8000 + 0 29000 11000 0>, + < 90000 38000 28000 8000 + 0 29000 11000 0>, + < 90000 38000 28000 8000 + 0 29000 11000 0>, + < 90000 38000 28000 8000 + 0 29000 11000 0>; + + qcom,cpr-floor-to-ceiling-max-range = + <40000 40000 40000 40000 40000 40000 50000 50000>; + + qcom,cpr-fused-closed-loop-voltage-adjustment-map = + <0 0 0 0 1 2 3 4>; + + qcom,allow-voltage-interpolation; + qcom,cpr-scaled-open-loop-voltage-as-ceiling; + + qcom,cpr-aging-max-voltage-adjustment = <15000>; + qcom,cpr-aging-ref-corner = <8>; + qcom,cpr-aging-ro-scaling-factor = <1620>; + qcom,allow-aging-voltage-adjustment = <0>; +}; + +&qusb_phy0 { + reg = <0x0c012000 0x2a8>, + <0x01fcb24c 0x4>, + <0x00784238 0x4>; + reg-names = "qusb_phy_base", + "tcsr_clamp_dig_n_1p8", + "efuse_addr"; + qcom,efuse-bit-pos = <16>; + qcom,efuse-num-bits = <4>; + qcom,qusb-phy-init-seq = + /* */ + <0x13 0x04 /* analog_controls_two */ + 0x7c 0x18c /* pll_clock_inverter */ + 0x80 0x2c /* pll_cmode */ + 0x0a 0x184 /* pll_lock_delay */ + 0xa5 0x23c /* tune1 */ + 0x09 0x240 /* tune2 */ + 0x19 0xb4>; /* digital_timers_two */ +}; + +&msm_vidc { + qcom,load-freq-tbl = + /* Encoders */ + <1105920 533000000 0x55555555>, /* 4kx2304@30 */ /*TURBO*/ + <1036800 444000000 0x55555555>, /* 720p@240, 1080p@120,1440p@60, + * UHD@30 */ /*NOMINAL*/ + < 829440 355200000 0x55555555>, /* UHD/4096x2160@30 SVSL1 */ + < 489600 269330000 0x55555555>, /* 1080p@60, 720p@120 SVS */ + < 345600 200000000 0x55555555>, /* 2560x1440@24, 1080p@30 */ + /* SVS2 */ + + /* Decoders */ + <2211840 533000000 0xffffffff>, /* 4kx2304@60, 1080p@240 */ + /* TURBO */ + <1728000 444000000 0xffffffff>, /* 2560x1440@120 */ + /* NOMINAL */ + <1675472 355200000 0xffffffff>, /* 4kx2304@44 */ /*SVSL1*/ + <1105920 269330000 0xffffffff>, /* UHD/4k2304@30, 1080p@120 */ + /* SVS */ + < 829440 200000000 0xffffffff>; /* 720p@120, 1080p@60 */ + /* SVS2 */ + + qcom,imem-ab-tbl = + <200000000 1560000>,/* imem @ svs2 freq 75 Mhz */ + <269330000 3570000>,/* imem @ svs freq 171 Mhz */ + <355200000 3570000>,/* imem @ svs freq 171 Mhz */ + <444000000 6750000>,/* imem @ nom freq 323 Mhz */ + <533000000 8490000>;/* imem @ turbo freq 406 Mhz */ + + qcom,dcvs-tbl = /* minLoad LoadLow LoadHigh CodecCheck */ + /* Decode */ + /* Load > Nominal, Nominal <-> Turbo Eg.3840x2160@60 */ + <1728000 1728000 2211840 0x3f00000c>, + /* Encoder */ + /* Load > Nominal, Nominal <-> Turbo Eg. 4kx2304@30 */ + <1036800 1036800 1105920 0x04000004>, + /* Load > SVSL1, SVSL1<-> Nominal Eg. 3840x2160@30 */ + < 829440 829440 1036800 0x04000004>, + /* Load > SVS , SVS <-> SVSL1 Eg. 4kx2304@24 */ + < 489600 489600 829440 0x04000004>; + + qcom,dcvs-limit = /* Min Frame size, Min MBs/sec */ + <32400 30>, /* Encoder 3840x2160@30 */ + <32400 60>; /* Decoder 3840x2160@60 */ + +}; + +&soc { + /* Gold L2 SAW */ + qcom,spm@178120000 { + qcom,saw2-avs-limit = <0x4700470>; + }; + + /* Silver L2 SAW */ + qcom,spm@179120000 { + qcom,saw2-avs-limit = <0x4200420>; + }; +}; + +/* GPU overrides */ +&msm_gpu { + /* Updated chip ID */ + qcom,chipid = <0x05040001>; + qcom,initial-pwrlevel = <6>; + + qcom,gpu-pwrlevels { + #address-cells = <1>; + #size-cells = <0>; + + compatible = "qcom,gpu-pwrlevels"; + + qcom,gpu-pwrlevel@0 { + reg = <0>; + qcom,gpu-freq = <710000000>; + qcom,bus-freq = <12>; + qcom,bus-min = <12>; + qcom,bus-max = <12>; + }; + + qcom,gpu-pwrlevel@1 { + reg = <1>; + qcom,gpu-freq = <670000000>; + qcom,bus-freq = <12>; + qcom,bus-min = <11>; + qcom,bus-max = <12>; + }; + + qcom,gpu-pwrlevel@2 { + reg = <2>; + qcom,gpu-freq = <596000000>; + qcom,bus-freq = <11>; + qcom,bus-min = <9>; + qcom,bus-max = <12>; + }; + + qcom,gpu-pwrlevel@3 { + reg = <3>; + qcom,gpu-freq = <515000000>; + qcom,bus-freq = <11>; + qcom,bus-min = <9>; + qcom,bus-max = <12>; + }; + + qcom,gpu-pwrlevel@4 { + reg = <4>; + qcom,gpu-freq = <414000000>; + qcom,bus-freq = <9>; + qcom,bus-min = <8>; + qcom,bus-max = <11>; + }; + + qcom,gpu-pwrlevel@5 { + reg = <5>; + qcom,gpu-freq = <342000000>; + qcom,bus-freq = <8>; + qcom,bus-min = <5>; + qcom,bus-max = <9>; + }; + + qcom,gpu-pwrlevel@6 { + reg = <6>; + qcom,gpu-freq = <257000000>; + qcom,bus-freq = <5>; + qcom,bus-min = <3>; + qcom,bus-max = <8>; + }; + + qcom,gpu-pwrlevel@7 { + reg = <7>; + qcom,gpu-freq = <27000000>; + qcom,bus-freq = <0>; + qcom,bus-min = <0>; + qcom,bus-max = <0>; + }; + }; +}; + +&spss_utils { + qcom,spss-test-firmware-name = "spss2t"; /* 8 chars max */ + qcom,spss-prod-firmware-name = "spss2p"; /* 8 chars max */ + qcom,spss-hybr-firmware-name = "spss2h"; /* 8 chars max */ +}; + +&ufs1 { + clock-names = + "core_clk", + "bus_aggr_clk", + "iface_clk", + "core_clk_unipro", + "core_clk_ice", + "ref_clk", + "tx_lane0_sync_clk", + "rx_lane0_sync_clk", + "rx_lane1_sync_clk"; + clocks = + <&clock_gcc clk_gcc_ufs_axi_hw_ctl_clk>, + <&clock_gcc clk_gcc_aggre1_ufs_axi_clk>, + <&clock_gcc clk_gcc_ufs_ahb_clk>, + <&clock_gcc clk_gcc_ufs_unipro_core_hw_ctl_clk>, + <&clock_gcc clk_gcc_ufs_ice_core_hw_ctl_clk>, + <&clock_gcc clk_ln_bb_clk1>, + <&clock_gcc clk_gcc_ufs_tx_symbol_0_clk>, + <&clock_gcc clk_gcc_ufs_rx_symbol_0_clk>, + <&clock_gcc clk_gcc_ufs_rx_symbol_1_clk>; + freq-table-hz = + <50000000 200000000>, + <0 0>, + <0 0>, + <37500000 150000000>, + <75000000 300000000>, + <0 0>, + <0 0>, + <0 0>, + <0 0>; + + lanes-per-direction = <2>; +}; + +&ssc_sensors { + qcom,firmware-name = "slpi_v2"; +}; --- /dev/null 2019-10-24 16:47:25.704025805 +0200 +++ linux-4.4.115-fbx/arch/arm64/boot/dts/qcom/msm8998-vidc.dtsi 2019-01-22 16:16:21.203225578 +0100 @@ -0,0 +1,251 @@ +/* Copyright (c) 2014-2017, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include + +&soc { + msm_vidc: qcom,vidc@cc00000 { + compatible = "qcom,msm-vidc"; + status = "ok"; + reg = <0xcc00000 0x100000>; + interrupts = ; + qcom,hfi = "venus"; + qcom,hfi-version = "3xx"; + qcom,firmware-name = "venus"; + qcom,never-unload-fw; + qcom,sw-power-collapse; + qcom,max-secure-instances = <5>; + qcom,reg-presets = + <0x80124 0x00000003>, + <0x80550 0x01111111>, + <0x80560 0x01111111>, + <0x80568 0x01111111>, + <0x80570 0x01111111>, + <0x80580 0x01111111>, + <0x80588 0x01111111>, + <0xe2010 0x00000000>; + + qcom,imem-size = <524288>; /* 512 kB */ + qcom,max-hw-load = <2563200>; /* Full 4k @ 60 + 1080p @ 60 */ + qcom,power-conf = <8294400>; /* WxH - 3840*2160 */ + qcom,load-freq-tbl = + /* Encoders */ + <972000 465000000 0x55555555>, /* 4k UHD @ 30 */ + <489600 360000000 0x55555555>, /* 1080p @ 60 */ + <244800 186000000 0x55555555>, /* 1080p @ 30 */ + <108000 100000000 0x55555555>, /* 720p @ 30 */ + + /* Decoders */ + <1944000 465000000 0xffffffff>, /* 4k UHD @ 60 */ + < 972000 360000000 0xffffffff>, /* 4k UHD @ 30 */ + < 489600 186000000 0xffffffff>, /* 1080p @ 60 */ + < 244800 100000000 0xffffffff>; /* 1080p @ 30 */ + + qcom,dcvs-tbl = + <972000 972000 19944000 0x3f00000c>, /* UHD 30 */ + <489600 489600 972000 0x3f00000c>, /* 1080p 60 */ + <244800 244800 489600 0x3f00000c>, /* 1080p 30 */ + <829440 489600 972000 0x04000004>; /* DCI 24 */ + + qcom,dcvs-limit = + <32400 30>, /* Encoder UHD */ + <14400 30>; /* Decoder WQHD */ + + /* Table lists pairs. + * imem_ab value determines the imem clock frequency for the + * corresponding video core frequency. + */ + qcom,imem-ab-tbl = + <100000000 1560000>, /* imem @ svs2 freq 75 Mhz */ + <186000000 3570000>, /* imem @ svs freq 171 Mhz */ + <360000000 6750000>, /* imem @ nom freq 323 Mhz */ + <465000000 8490000>; /* imem @ turbo freq 406 Mhz */ + + /* Regulators */ + smmu-vdd-supply = <&gdsc_bimc_smmu>; + venus-supply = <&gdsc_venus>; + venus-core0-supply = <&gdsc_venus_core0>; + venus-core1-supply = <&gdsc_venus_core1>; + + /* Clocks */ + clock-names = "sys_noc_axi_clk", + "noc_axi_clk", "mnoc_ahb_clk", + "smmu_ahb_clk", "smmu_axi_clk", + "mnoc_maxi_clk", + "core_clk", "iface_clk", "bus_clk", + "maxi_clk", "core0_clk", "core1_clk"; + clocks = <&clock_gcc clk_gcc_mmss_sys_noc_axi_clk>, + <&clock_gcc clk_mmssnoc_axi_clk>, + <&clock_mmss clk_mmss_mnoc_ahb_clk>, + <&clock_mmss clk_mmss_bimc_smmu_ahb_clk>, + <&clock_mmss clk_mmss_bimc_smmu_axi_clk>, + <&clock_mmss clk_mmss_mnoc_maxi_clk>, + <&clock_mmss clk_mmss_video_core_clk>, + <&clock_mmss clk_mmss_video_ahb_clk>, + <&clock_mmss clk_mmss_video_axi_clk>, + <&clock_mmss clk_mmss_video_maxi_clk>, + <&clock_mmss clk_mmss_video_subcore0_clk>, + <&clock_mmss clk_mmss_video_subcore1_clk>; + qcom,clock-configs = <0x0 0x0 0x0 0x0 0x0 0x0 + 0x3 0x0 0x2 0x2 0x3 0x3>; + + /* Buses */ + bus_cnoc { + compatible = "qcom,msm-vidc,bus"; + label = "cnoc"; + qcom,bus-master = ; + qcom,bus-slave = ; + qcom,bus-governor = "performance"; + qcom,bus-range-kbps = <1 1>; + }; + + venus_bus_ddr { + compatible = "qcom,msm-vidc,bus"; + label = "venus-ddr"; + qcom,bus-master = ; + qcom,bus-slave = ; + qcom,bus-governor = "msm-vidc-ddr"; + qcom,bus-range-kbps = <1000 4946000>; + }; + + venus_bus_vmem { + compatible = "qcom,msm-vidc,bus"; + label = "venus-vmem"; + qcom,bus-master = ; + qcom,bus-slave = ; + qcom,bus-governor = "msm-vidc-vmem+"; + qcom,bus-range-kbps = <1000 8490000>; + }; + + arm9_bus_ddr { + compatible = "qcom,msm-vidc,bus"; + label = "venus-arm9-ddr"; + qcom,bus-master = ; + qcom,bus-slave = ; + qcom,bus-governor = "performance"; + qcom,bus-range-kbps = <1 1>; + }; + + + /* MMUs */ + non_secure_cb { + compatible = "qcom,msm-vidc,context-bank"; + label = "venus_ns"; + iommus = + <&mmss_smmu 0x400>, + <&mmss_smmu 0x401>, + <&mmss_smmu 0x40a>, + <&mmss_smmu 0x407>, + <&mmss_smmu 0x40e>, + <&mmss_smmu 0x40f>, + <&mmss_smmu 0x408>, + <&mmss_smmu 0x409>, + <&mmss_smmu 0x40b>, + <&mmss_smmu 0x40c>, + <&mmss_smmu 0x40d>, + <&mmss_smmu 0x410>, + <&mmss_smmu 0x421>, + <&mmss_smmu 0x428>, + <&mmss_smmu 0x429>, + <&mmss_smmu 0x42b>, + <&mmss_smmu 0x42c>, + <&mmss_smmu 0x42d>, + <&mmss_smmu 0x411>, + <&mmss_smmu 0x431>; + buffer-types = <0xfff>; + virtual-addr-pool = <0x70800000 0x6f800000>; + }; + + firmware_cb { + compatible = "qcom,msm-vidc,context-bank"; + qcom,fw-context-bank; + iommus = <&mmss_smmu 0x580>, + <&mmss_smmu 0x586>; + }; + secure_bitstream_cb { + compatible = "qcom,msm-vidc,context-bank"; + label = "venus_sec_bitstream"; + iommus = <&mmss_smmu 0x500>, + <&mmss_smmu 0x502>, + <&mmss_smmu 0x509>, + <&mmss_smmu 0x50a>, + <&mmss_smmu 0x50b>, + <&mmss_smmu 0x50e>, + <&mmss_smmu 0x526>, + <&mmss_smmu 0x529>, + <&mmss_smmu 0x52b>; + buffer-types = <0x241>; + virtual-addr-pool = <0x4b000000 0x25800000>; + qcom,secure-context-bank; + }; + + venus_secure_pixel_cb: secure_pixel_cb { + compatible = "qcom,msm-vidc,context-bank"; + label = "venus_sec_pixel"; + iommus = <&mmss_smmu 0x504>, + <&mmss_smmu 0x50c>, + <&mmss_smmu 0x510>, + <&mmss_smmu 0x52c>; + buffer-types = <0x106>; + virtual-addr-pool = <0x25800000 0x25800000>; + qcom,secure-context-bank; + }; + + venus_secure_non_pixel_cb: secure_non_pixel_cb { + compatible = "qcom,msm-vidc,context-bank"; + label = "venus_sec_non_pixel"; + iommus = <&mmss_smmu 0x505>, + <&mmss_smmu 0x507>, + <&mmss_smmu 0x508>, + <&mmss_smmu 0x50d>, + <&mmss_smmu 0x50f>, + <&mmss_smmu 0x525>, + <&mmss_smmu 0x528>, + <&mmss_smmu 0x52d>, + <&mmss_smmu 0x540>; + buffer-types = <0x480>; + virtual-addr-pool = <0x1000000 0x24800000>; + qcom,secure-context-bank; + }; + }; + + qcom,vmem@c880000 { + compatible = "qcom,msm-vmem"; + status = "ok"; + interrupts = ; + + reg = <0xc880000 0x6b>, + <0x14800000 0x80000>; + reg-names = "reg-base", "mem-base"; + + clocks = <&clock_mmss clk_mmss_mnoc_ahb_clk>, + <&clock_mmss clk_mmss_mnoc_maxi_clk>, + <&clock_mmss clk_mmss_vmem_ahb_clk>, + <&clock_mmss clk_mmss_vmem_maxi_clk>; + clock-names = "mnoc_ahb","mnoc_maxi", + "ahb", "maxi"; + clock-config = <0x0 0x0 0x0 0x1>; + + qcom,msm-bus,name = "vmem"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <2>; + qcom,msm-bus,vectors-KBps = + , + , + , + ; + + qcom,bank-size = <131072>; /* 128 kB */ + }; +}; --- /dev/null 2019-10-24 16:47:25.704025805 +0200 +++ linux-4.4.115-fbx/arch/arm64/boot/dts/qcom/msm8998-wcd.dtsi 2019-01-22 16:16:21.203225578 +0100 @@ -0,0 +1,239 @@ +/* Copyright (c) 2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&slim_aud { + tasha_codec { + wsa_spkr_sd1: msm_cdc_pinctrll { + compatible = "qcom,msm-cdc-pinctrl"; + pinctrl-names = "aud_active", "aud_sleep"; + pinctrl-0 = <&spkr_1_sd_n_active>; + pinctrl-1 = <&spkr_1_sd_n_sleep>; + }; + + wsa_spkr_sd2: msm_cdc_pinctrlr { + compatible = "qcom,msm-cdc-pinctrl"; + pinctrl-names = "aud_active", "aud_sleep"; + pinctrl-0 = <&spkr_2_sd_n_active>; + pinctrl-1 = <&spkr_2_sd_n_sleep>; + }; + }; + + tavil_codec { + wcd: wcd_pinctrl@5 { + compatible = "qcom,wcd-pinctrl"; + qcom,num-gpios = <5>; + gpio-controller; + #gpio-cells = <2>; + + us_euro_sw_wcd_active: us_euro_sw_wcd_active { + mux { + pins = "gpio1"; + }; + + config { + pins = "gpio1"; + output-high; + }; + }; + + us_euro_sw_wcd_sleep: us_euro_sw_wcd_sleep { + mux { + pins = "gpio1"; + }; + + config { + pins = "gpio1"; + output-low; + }; + }; + + spkr_1_wcd_en_active: spkr_1_wcd_en_active { + mux { + pins = "gpio2"; + }; + + config { + pins = "gpio2"; + output-high; + }; + }; + + spkr_1_wcd_en_sleep: spkr_1_wcd_en_sleep { + mux { + pins = "gpio2"; + }; + + config { + pins = "gpio2"; + input-enable; + }; + }; + + spkr_2_wcd_en_active: spkr_2_sd_n_active { + mux { + pins = "gpio3"; + }; + + config { + pins = "gpio3"; + output-high; + }; + }; + + spkr_2_wcd_en_sleep: spkr_2_sd_n_sleep { + mux { + pins = "gpio3"; + }; + + config { + pins = "gpio3"; + input-enable; + }; + }; + + hph_en0_wcd_active: hph_en0_wcd_active { + mux { + pins = "gpio4"; + }; + + config { + pins = "gpio4"; + output-high; + }; + }; + + hph_en0_wcd_sleep: hph_en0_wcd_sleep { + mux { + pins = "gpio4"; + }; + + config { + pins = "gpio4"; + output-low; + }; + }; + + hph_en1_wcd_active: hph_en1_wcd_active { + mux { + pins = "gpio5"; + }; + + config { + pins = "gpio5"; + output-high; + }; + }; + + hph_en1_wcd_sleep: hph_en1_wcd_sleep { + mux { + pins = "gpio5"; + }; + + config { + pins = "gpio5"; + output-low; + }; + }; + }; + + wsa_spkr_wcd_sd1: msm_cdc_pinctrll { + compatible = "qcom,msm-cdc-pinctrl"; + pinctrl-names = "aud_active", "aud_sleep"; + pinctrl-0 = <&spkr_1_wcd_en_active>; + pinctrl-1 = <&spkr_1_wcd_en_sleep>; + }; + + wsa_spkr_wcd_sd2: msm_cdc_pinctrlr { + compatible = "qcom,msm-cdc-pinctrl"; + pinctrl-names = "aud_active", "aud_sleep"; + pinctrl-0 = <&spkr_2_wcd_en_active>; + pinctrl-1 = <&spkr_2_wcd_en_sleep>; + }; + + tavil_us_euro_sw: msm_cdc_pinctrl_us_euro_sw { + compatible = "qcom,msm-cdc-pinctrl"; + pinctrl-names = "aud_active", "aud_sleep"; + pinctrl-0 = <&us_euro_sw_wcd_active>; + pinctrl-1 = <&us_euro_sw_wcd_sleep>; + }; + + tavil_hph_en0: msm_cdc_pinctrl_hph_en0 { + compatible = "qcom,msm-cdc-pinctrl"; + pinctrl-names = "aud_active", "aud_sleep"; + pinctrl-0 = <&hph_en0_wcd_active>; + pinctrl-1 = <&hph_en0_wcd_sleep>; + }; + + tavil_hph_en1: msm_cdc_pinctrl_hph_en1 { + compatible = "qcom,msm-cdc-pinctrl"; + pinctrl-names = "aud_active", "aud_sleep"; + pinctrl-0 = <&hph_en1_wcd_active>; + pinctrl-1 = <&hph_en1_wcd_sleep>; + }; + }; +}; + +&tlmm { + spkr_1_sd_n { + spkr_1_sd_n_sleep: spkr_1_sd_n_sleep { + mux { + pins = "gpio65"; + function = "gpio"; + }; + config { + pins = "gpio65"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; + input-enable; + }; + }; + spkr_1_sd_n_active: spkr_1_sd_n_active { + mux { + pins = "gpio65"; + function = "gpio"; + }; + config { + pins = "gpio65"; + drive-strength = <16>; /* 16 mA */ + bias-disable; + output-high; + }; + }; + }; + + spkr_2_sd_n { + spkr_2_sd_n_sleep: spkr_2_sd_n_sleep { + mux { + pins = "gpio66"; + function = "gpio"; + }; + config { + pins = "gpio66"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; + input-enable; + }; + }; + spkr_2_sd_n_active: spkr_2_sd_n_active { + mux { + pins = "gpio66"; + function = "gpio"; + }; + config { + pins = "gpio66"; + drive-strength = <16>; /* 16 mA */ + bias-disable; + output-high; + }; + }; + }; +}; --- /dev/null 2019-10-24 16:47:25.704025805 +0200 +++ linux-4.4.115-fbx/arch/arm64/boot/dts/qcom/msm8998-wsa881x.dtsi 2019-01-22 16:16:21.203225578 +0100 @@ -0,0 +1,78 @@ +/* Copyright (c) 2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include "msm8998-wcd.dtsi" + +&slim_aud { + tasha_codec { + swr_master { + compatible = "qcom,swr-wcd"; + #address-cells = <2>; + #size-cells = <0>; + + wsa881x_211: wsa881x@20170211 { + compatible = "qcom,wsa881x"; + reg = <0x00 0x20170211>; + qcom,spkr-sd-n-node = <&wsa_spkr_sd1>; + }; + + wsa881x_212: wsa881x@20170212 { + compatible = "qcom,wsa881x"; + reg = <0x00 0x20170212>; + qcom,spkr-sd-n-node = <&wsa_spkr_sd2>; + }; + + wsa881x_213: wsa881x@21170213 { + compatible = "qcom,wsa881x"; + reg = <0x00 0x21170213>; + qcom,spkr-sd-n-node = <&wsa_spkr_sd1>; + }; + + wsa881x_214: wsa881x@21170214 { + compatible = "qcom,wsa881x"; + reg = <0x00 0x21170214>; + qcom,spkr-sd-n-node = <&wsa_spkr_sd2>; + }; + }; + }; + + tavil_codec { + swr_master { + compatible = "qcom,swr-wcd"; + #address-cells = <2>; + #size-cells = <0>; + + wsa881x_0211: wsa881x@20170211 { + compatible = "qcom,wsa881x"; + reg = <0x00 0x20170211>; + qcom,spkr-sd-n-node = <&wsa_spkr_wcd_sd1>; + }; + + wsa881x_0212: wsa881x@20170212 { + compatible = "qcom,wsa881x"; + reg = <0x00 0x20170212>; + qcom,spkr-sd-n-node = <&wsa_spkr_wcd_sd2>; + }; + + wsa881x_0213: wsa881x@21170213 { + compatible = "qcom,wsa881x"; + reg = <0x00 0x21170213>; + qcom,spkr-sd-n-node = <&wsa_spkr_wcd_sd1>; + }; + + wsa881x_0214: wsa881x@21170214 { + compatible = "qcom,wsa881x"; + reg = <0x00 0x21170214>; + qcom,spkr-sd-n-node = <&wsa_spkr_wcd_sd2>; + }; + }; + }; +}; --- /dev/null 2019-10-24 16:47:25.704025805 +0200 +++ linux-4.4.115-fbx/arch/arm64/boot/dts/qcom/msm-arm-smmu-8998.dtsi 2019-01-22 16:16:21.179225361 +0100 @@ -0,0 +1,192 @@ +/* Copyright (c) 2015-2017, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include + +&soc { + anoc1_smmu: arm,smmu-anoc1@1680000 { + status = "ok"; + compatible = "qcom,smmu-v2"; + reg = <0x1680000 0x10000>; + #iommu-cells = <0>; + qcom,register-save; + qcom,skip-init; + #global-interrupts = <0>; + interrupts = , + , + , + , + , + ; + qcom,msm-bus,name = "smmu-bus-client-anoc1"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,active-only; + qcom,msm-bus,num-paths = <1>; + /* aggre1_noc_clk */ + qcom,msm-bus,vectors-KBps = + <84 10062 0 0>, + <84 10062 0 1000>; + }; + + anoc2_smmu: arm,smmu-anoc2@16c0000 { + status = "ok"; + compatible = "qcom,smmu-v2"; + reg = <0x16c0000 0x40000>; + #iommu-cells = <1>; + qcom,register-save; + qcom,skip-init; + #global-interrupts = <0>; + interrupts = , + , + , + , + , + , + , + , + , + ; + qcom,msm-bus,name = "smmu-bus-client-anoc2"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,active-only; + qcom,msm-bus,num-paths = <1>; + /* aggre2_noc_clk */ + qcom,msm-bus,vectors-KBps = + <117 10065 0 0>, + <117 10065 0 1000>; + }; + + lpass_q6_smmu: arm,smmu-lpass_q6@5100000 { + status = "ok"; + compatible = "qcom,smmu-v2"; + reg = <0x5100000 0x40000>; + #iommu-cells = <1>; + qcom,tz-device-id = "LPASS"; + qcom,register-save; + qcom,skip-init; + #global-interrupts = <0>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + ; + vdd-supply = <&gdsc_hlos1_vote_lpass_adsp>; + clocks = <&clock_gcc clk_hlos1_vote_lpass_adsp_smmu_clk>; + clock-names = "lpass_q6_smmu_clk"; + #clock-cells = <1>; + }; + + mmss_smmu: arm,smmu-mmss@cd00000 { + status = "ok"; + compatible = "qcom,smmu-v2"; + reg = <0xcd00000 0x40000>; + #iommu-cells = <1>; + qcom,register-save; + qcom,no-smr-check; + qcom,skip-init; + #global-interrupts = <0>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + vdd-supply = <&gdsc_bimc_smmu>; + clocks = <&clock_mmss clk_mmss_mnoc_ahb_clk>, + <&clock_mmss clk_mmss_bimc_smmu_ahb_clk>, + <&clock_mmss clk_mmss_bimc_smmu_axi_clk>; + clock-names = "mmss_mnoc_ahb_clk", + "mmss_bimc_smmu_ahb_clk", + "mmss_bimc_smmu_axi_clk"; + #clock-cells = <1>; + qcom,msm-bus,name = "smmu-bus-client-mmss"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,active-only; + qcom,msm-bus,num-paths = <2>; + /* ahb_clk_src, mmssnoc_axi_clk */ + qcom,msm-bus,vectors-KBps = + <102 722 0 0>, <29 512 0 0>, + <102 722 0 1000>, <29 512 0 1000>; + }; + + kgsl_smmu: arm,smmu-kgsl@5040000 { + status = "ok"; + compatible = "qcom,smmu-v2"; + reg = <0x5040000 0x10000>; + #iommu-cells = <1>; + qcom-tz-device-id = "GPU"; + qcom,dynamic; + qcom,register-save; + qcom,skip-init; + #global-interrupts = <0>; + interrupts = , + , + ; + qcom,deferred-regulator-disable-delay = <80>; + vdd-supply = <&gdsc_gpu_cx>; + clocks = <&clock_gcc clk_gcc_gpu_cfg_ahb_clk>, + <&clock_gcc clk_gcc_bimc_gfx_clk>, + <&clock_gcc clk_gcc_gpu_bimc_gfx_clk>; + + clock-names = "gcc_gpu_cfg_ahb_clk", + "gcc_bimc_gfx_clk", + "gcc_gpu_bimc_gfx_clk"; + #clock-cells = <1>; + }; + + iommu_test_device { + compatible = "iommu-debug-test"; + /* + * 42 shouldn't be used by anyone on the mmss_smmu. We just + * need _something_ here to get this node recognized by the + * SMMU driver. Our test uses ATOS, which doesn't use SIDs + * anyways, so using a dummy value is ok. + */ + iommus = <&mmss_smmu 42>; + }; + + iommu_coherent_test_device { + compatible = "iommu-debug-test"; + /* + * 43 shouldn't be used by anyone on the mmss_smmu. We just + * need _something_ here to get this node recognized by the + * SMMU driver. Our test uses ATOS, which doesn't use SIDs + * anyways, so using a dummy value is ok. + */ + iommus = <&mmss_smmu 43>; + dma-coherent; + }; +}; --- /dev/null 2019-10-24 16:47:25.704025805 +0200 +++ linux-4.4.115-fbx/arch/arm64/boot/dts/qcom/msm-arm-smmu-impl-defs-8998.dtsi 2019-01-22 16:16:21.179225361 +0100 @@ -0,0 +1,565 @@ +/* Copyright (c) 2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +&kgsl_smmu { + attach-impl-defs = <0x6000 0x2378>, + <0x6060 0x1055>, + <0x6470 0x110011>, + <0x6478 0x0>, + <0x647c 0x1000100>, + <0x6480 0x81108110>, + <0x6484 0x81108110>, + <0x6488 0x3e003e0>, + <0x648c 0x3e003e0>, + <0x6490 0x80008010>, + <0x6494 0x8020>, + <0x649c 0x6>, + <0x6800 0x6>, + <0x6900 0x3ff>, + <0x6924 0x604>, + <0x6928 0x11000>, + <0x6930 0x800>, + <0x6960 0x3>, + <0x6b64 0x1a5551>, + <0x6b68 0x2aaa2f82>; +}; + +&lpass_q6_smmu { + attach-impl-defs = <0x6000 0x3270>, + <0x6060 0x1055>, + <0x6070 0xe0>, + <0x6074 0xe0>, + <0x6078 0xe0>, + <0x607c 0xe0>, + <0x60f0 0xc0>, + <0x60f4 0xc8>, + <0x60f8 0xd0>, + <0x60fc 0xd8>, + <0x6170 0x0>, + <0x6174 0x30>, + <0x6178 0x60>, + <0x617c 0x90>, + <0x6270 0x0>, + <0x6274 0x2>, + <0x6278 0x4>, + <0x627c 0x6>, + <0x62f0 0x8>, + <0x62f4 0xe>, + <0x62f8 0x14>, + <0x62fc 0x1a>, + <0x6370 0x20>, + <0x6374 0x40>, + <0x6378 0x60>, + <0x637c 0x80>, + <0x67a0 0x0>, + <0x67a4 0x0>, + <0x67a8 0x20>, + <0x67b0 0x0>, + <0x67b4 0x8>, + <0x67b8 0xc8>, + <0x67d0 0x4>, + <0x67dc 0x8>, + <0x67e0 0x8>, + <0x6800 0x6>, + <0x6900 0x3ff>, + <0x6924 0x202>, + <0x6928 0x10a00>, + <0x6930 0x500>, + <0x6b64 0x121151>, + <0x6b68 0x8a840080>, + <0x6c00 0x0>, + <0x6c04 0x0>, + <0x6c08 0x0>, + <0x6c0c 0x0>, + <0x6c10 0x1>, + <0x6c14 0x1>, + <0x6c18 0x1>, + <0x6c1c 0x1>, + <0x6c20 0x2>, + <0x6c24 0x2>, + <0x6c28 0x2>, + <0x6c2c 0x2>, + <0x6c30 0x3>, + <0x6c34 0x3>, + <0x6c38 0x3>, + <0x6c3c 0x3>; +}; + +&mmss_smmu { + attach-impl-defs = <0x6000 0x3270>, + <0x6060 0x1055>, + <0x6800 0x6>, + <0x6900 0x3ff>, + <0x6924 0x204>, + <0x6928 0x11002>, + <0x6930 0x800>, + <0x6960 0xffffffff>, + <0x6964 0xffffffff>, + <0x6968 0xffffffff>, + <0x696c 0xffffffff>, + <0x6b48 0x330330>, + <0x6b4c 0x81>, + <0x6b50 0x3333>, + <0x6b54 0x3333>, + <0x6b64 0x1a5555>, + <0x6b68 0x9aaa892a>, + <0x6b70 0x10100002>, + <0x6b74 0x10100002>, + <0x6b78 0x10100002>, + <0x6b80 0x20042004>, + <0x6b84 0x20042004>; +}; + +&anoc1_smmu { + attach-impl-defs = <0x6000 0x3270>, + <0x6060 0x1055>, + <0x6070 0x19>, + <0x6074 0x39>, + <0x6078 0x41>, + <0x607c 0x59>, + <0x6080 0x95>, + <0x6084 0x98>, + <0x6088 0xc0>, + <0x608c 0xc0>, + <0x60f0 0x0>, + <0x60f4 0x2>, + <0x60f8 0x5>, + <0x60fc 0x8>, + <0x6100 0x16>, + <0x6104 0x17>, + <0x6108 0x19>, + <0x610c 0x19>, + <0x6170 0x0>, + <0x6174 0x0>, + <0x6178 0x0>, + <0x617c 0x0>, + <0x6180 0x0>, + <0x6184 0x0>, + <0x6188 0x0>, + <0x618c 0x0>, + <0x6270 0x0>, + <0x6274 0xd>, + <0x6278 0xe>, + <0x627c 0x12>, + <0x6280 0x16>, + <0x6284 0x16>, + <0x6288 0x18>, + <0x628c 0x18>, + <0x62f0 0x18>, + <0x62f4 0x1b>, + <0x62f8 0x1c>, + <0x62fc 0x24>, + <0x6300 0x28>, + <0x6304 0x2b>, + <0x6308 0x31>, + <0x630c 0x31>, + <0x6370 0x31>, + <0x6374 0x34>, + <0x6378 0x35>, + <0x637c 0x47>, + <0x6380 0x4f>, + <0x6384 0x54>, + <0x6388 0x60>, + <0x638c 0x60>, + <0x67a0 0x0>, + <0x67a4 0xa7>, + <0x67a8 0xc0>, + <0x67b0 0x0>, + <0x67b4 0x18>, + <0x67b8 0x7c>, + <0x67d0 0x0>, + <0x67dc 0x4>, + <0x67e0 0x8>, + <0x6800 0x6>, + <0x6900 0x3ff>, + <0x6b64 0x121151>, + <0x6b68 0xbb804080>, + <0x6c00 0x0>, + <0x6c04 0x0>, + <0x6c08 0x0>, + <0x6c0c 0x0>, + <0x6c10 0x0>, + <0x6c14 0x0>, + <0x6c18 0x0>, + <0x6c1c 0x0>, + <0x6c20 0x0>, + <0x6c24 0x0>, + <0x6c28 0x0>, + <0x6c2c 0x0>, + <0x6c30 0x0>, + <0x6c34 0x0>, + <0x6c38 0x0>, + <0x6c3c 0x0>, + <0x6c40 0x0>, + <0x6c44 0x0>, + <0x6c48 0x0>, + <0x6c4c 0x0>, + <0x6c50 0x0>, + <0x6c54 0x0>, + <0x6c58 0x0>, + <0x6c5c 0x0>, + <0x6c60 0x0>, + <0x6c64 0x0>, + <0x6c68 0x0>, + <0x6c6c 0x0>, + <0x6c70 0x0>, + <0x6c74 0x0>, + <0x6c78 0x0>, + <0x6c7c 0x0>, + <0x6c80 0x0>, + <0x6c84 0x1>, + <0x6c88 0x0>, + <0x6c8c 0x0>, + <0x6c90 0x4>, + <0x6c94 0x3>, + <0x6c98 0x2>, + <0x6c9c 0x0>, + <0x6ca0 0x5>, + <0x6ca4 0x5>, + <0x6ca8 0x0>, + <0x6cac 0x0>, + <0x6cb0 0x0>, + <0x6cb4 0x0>, + <0x6cb8 0x0>, + <0x6cbc 0x0>, + <0x6cc0 0x0>, + <0x6cc4 0x0>, + <0x6cc8 0x0>, + <0x6ccc 0x0>, + <0x6cd0 0x0>, + <0x6cd4 0x0>, + <0x6cd8 0x0>, + <0x6cdc 0x0>, + <0x6ce0 0x0>, + <0x6ce4 0x0>, + <0x6ce8 0x0>, + <0x6cec 0x0>, + <0x6cf0 0x0>, + <0x6cf4 0x0>, + <0x6cf8 0x0>, + <0x6cfc 0x0>, + <0x6d00 0x0>, + <0x6d04 0x0>, + <0x6d08 0x0>, + <0x6d0c 0x0>, + <0x6d10 0x0>, + <0x6d14 0x0>, + <0x6d18 0x0>, + <0x6d1c 0x0>, + <0x6d20 0x0>, + <0x6d24 0x0>, + <0x6d28 0x0>, + <0x6d2c 0x0>, + <0x6d30 0x0>, + <0x6d34 0x0>, + <0x6d38 0x0>, + <0x6d3c 0x0>, + <0x6d40 0x0>, + <0x6d44 0x0>, + <0x6d48 0x0>, + <0x6d4c 0x0>, + <0x6d50 0x0>, + <0x6d54 0x0>, + <0x6d58 0x0>, + <0x6d5c 0x0>, + <0x6d60 0x0>, + <0x6d64 0x0>, + <0x6d68 0x0>, + <0x6d6c 0x0>, + <0x6d70 0x0>, + <0x6d74 0x0>, + <0x6d78 0x0>, + <0x6d7c 0x0>, + <0x6d80 0x0>, + <0x6d84 0x0>, + <0x6d88 0x0>, + <0x6d8c 0x0>, + <0x6d90 0x0>, + <0x6d94 0x0>, + <0x6d98 0x0>, + <0x6d9c 0x0>, + <0x6da0 0x0>, + <0x6da4 0x0>, + <0x6da8 0x0>, + <0x6dac 0x0>, + <0x6db0 0x0>, + <0x6db4 0x0>, + <0x6db8 0x0>, + <0x6dbc 0x0>, + <0x6dc0 0x0>, + <0x6dc4 0x0>, + <0x6dc8 0x0>, + <0x6dcc 0x0>, + <0x6dd0 0x0>, + <0x6dd4 0x0>, + <0x6dd8 0x0>, + <0x6ddc 0x0>, + <0x6de0 0x0>, + <0x6de4 0x0>, + <0x6de8 0x0>, + <0x6dec 0x0>, + <0x6df0 0x0>, + <0x6df4 0x0>, + <0x6df8 0x0>, + <0x6dfc 0x0>; +}; + +&anoc2_smmu { + attach-impl-defs = <0x6000 0x3270>, + <0x6060 0x1055>, + <0x6070 0x12>, + <0x6074 0x26>, + <0x6078 0x3a>, + <0x607c 0x3c>, + <0x6080 0x3f>, + <0x6084 0x67>, + <0x6088 0x6c>, + <0x608c 0x74>, + <0x6090 0x7c>, + <0x6094 0x80>, + <0x6098 0xa0>, + <0x609c 0xa0>, + <0x60a0 0xa0>, + <0x60a4 0xa0>, + <0x60a8 0xa0>, + <0x60ac 0xa0>, + <0x60f0 0x0>, + <0x60f4 0x1>, + <0x60f8 0x3>, + <0x60fc 0x4>, + <0x6100 0x5>, + <0x6104 0x7>, + <0x6108 0x8>, + <0x610c 0x10>, + <0x6110 0x10>, + <0x6114 0x10>, + <0x6118 0x12>, + <0x611c 0x12>, + <0x6120 0x12>, + <0x6124 0x12>, + <0x6128 0x12>, + <0x612c 0x12>, + <0x6170 0x0>, + <0x6174 0x0>, + <0x6178 0x0>, + <0x617c 0x0>, + <0x6180 0x0>, + <0x6184 0x0>, + <0x6188 0x0>, + <0x618c 0x0>, + <0x6190 0x0>, + <0x6194 0x0>, + <0x6198 0x0>, + <0x619c 0x0>, + <0x61a0 0x0>, + <0x61a4 0x0>, + <0x61a8 0x0>, + <0x61ac 0x0>, + <0x6270 0x0>, + <0x6274 0x1>, + <0x6278 0x2>, + <0x627c 0x4>, + <0x6280 0x4>, + <0x6284 0x6>, + <0x6288 0x6>, + <0x628c 0x18>, + <0x6290 0x1a>, + <0x6294 0x1a>, + <0x6298 0x1e>, + <0x629c 0x1e>, + <0x62a0 0x1e>, + <0x62a4 0x1e>, + <0x62a8 0x1e>, + <0x62ac 0x1e>, + <0x62f0 0x1e>, + <0x62f4 0x24>, + <0x62f8 0x2a>, + <0x62fc 0x2c>, + <0x6300 0x2d>, + <0x6304 0x33>, + <0x6308 0x34>, + <0x630c 0x3a>, + <0x6310 0x3c>, + <0x6314 0x44>, + <0x6318 0x48>, + <0x631c 0x48>, + <0x6320 0x48>, + <0x6324 0x48>, + <0x6328 0x48>, + <0x632c 0x48>, + <0x6370 0x48>, + <0x6374 0x4d>, + <0x6378 0x52>, + <0x637c 0x56>, + <0x6380 0x59>, + <0x6384 0x63>, + <0x6388 0x68>, + <0x638c 0x70>, + <0x6390 0x78>, + <0x6394 0x88>, + <0x6398 0x90>, + <0x639c 0x90>, + <0x63a0 0x90>, + <0x63a4 0x90>, + <0x63a8 0x90>, + <0x63ac 0x90>, + <0x67a0 0x0>, + <0x67a4 0x8e>, + <0x67a8 0xa0>, + <0x67b0 0x0>, + <0x67b4 0x1e>, + <0x67b8 0xc6>, + <0x67d0 0x0>, + <0x67dc 0x4>, + <0x67e0 0x8>, + <0x6800 0x6>, + <0x6900 0x3ff>, + <0x6b48 0x330331>, + <0x6b4c 0x81>, + <0x6b50 0x1313>, + <0x6b64 0x121155>, + <0x6b68 0xea880920>, + <0x6b70 0x10100101>, + <0x6b74 0xc0c0000>, + <0x6b78 0xc0c0000>, + <0x6b80 0x20012001>, + <0x6b84 0x20012001>, + <0x6c00 0x5>, + <0x6c04 0x0>, + <0x6c08 0x5>, + <0x6c0c 0x0>, + <0x6c10 0x5>, + <0x6c14 0x0>, + <0x6c18 0x5>, + <0x6c1c 0x0>, + <0x6c20 0x5>, + <0x6c24 0x0>, + <0x6c28 0x0>, + <0x6c2c 0x0>, + <0x6c30 0x0>, + <0x6c34 0x0>, + <0x6c38 0x0>, + <0x6c3c 0x0>, + <0x6c40 0x0>, + <0x6c44 0x0>, + <0x6c48 0x0>, + <0x6c4c 0x0>, + <0x6c50 0x0>, + <0x6c54 0x0>, + <0x6c58 0x0>, + <0x6c5c 0x0>, + <0x6c60 0x0>, + <0x6c64 0x0>, + <0x6c68 0x0>, + <0x6c6c 0x0>, + <0x6c70 0x0>, + <0x6c74 0x0>, + <0x6c78 0x0>, + <0x6c7c 0x0>, + <0x6c80 0x0>, + <0x6c84 0x0>, + <0x6c88 0x0>, + <0x6c8c 0x0>, + <0x6c90 0x0>, + <0x6c94 0x0>, + <0x6c98 0x0>, + <0x6c9c 0x0>, + <0x6ca0 0x0>, + <0x6ca4 0x0>, + <0x6ca8 0x0>, + <0x6cac 0x0>, + <0x6cb0 0x0>, + <0x6cb4 0x0>, + <0x6cb8 0x0>, + <0x6cbc 0x0>, + <0x6cc0 0x0>, + <0x6cc4 0x0>, + <0x6cc8 0x0>, + <0x6ccc 0x0>, + <0x6cd0 0x0>, + <0x6cd4 0x0>, + <0x6cd8 0x0>, + <0x6cdc 0x0>, + <0x6ce0 0x0>, + <0x6ce4 0x0>, + <0x6ce8 0x0>, + <0x6cec 0x0>, + <0x6cf0 0x0>, + <0x6cf4 0x0>, + <0x6cf8 0x0>, + <0x6cfc 0x0>, + <0x6d00 0x8>, + <0x6d04 0x0>, + <0x6d08 0x8>, + <0x6d0c 0x0>, + <0x6d10 0x7>, + <0x6d14 0x0>, + <0x6d18 0x3>, + <0x6d1c 0x2>, + <0x6d20 0x4>, + <0x6d24 0x0>, + <0x6d28 0x4>, + <0x6d2c 0x0>, + <0x6d30 0x6>, + <0x6d34 0x0>, + <0x6d38 0x9>, + <0x6d3c 0x0>, + <0x6d40 0x0>, + <0x6d44 0x1>, + <0x6d48 0x4>, + <0x6d4c 0x0>, + <0x6d50 0x4>, + <0x6d54 0x0>, + <0x6d58 0x0>, + <0x6d5c 0x0>, + <0x6d60 0x0>, + <0x6d64 0x0>, + <0x6d68 0x0>, + <0x6d6c 0x0>, + <0x6d70 0x0>, + <0x6d74 0x0>, + <0x6d78 0x0>, + <0x6d7c 0x0>, + <0x6d80 0x0>, + <0x6d84 0x0>, + <0x6d88 0x0>, + <0x6d8c 0x0>, + <0x6d90 0x0>, + <0x6d94 0x0>, + <0x6d98 0x0>, + <0x6d9c 0x0>, + <0x6da0 0x0>, + <0x6da4 0x0>, + <0x6da8 0x0>, + <0x6dac 0x0>, + <0x6db0 0x0>, + <0x6db4 0x0>, + <0x6db8 0x0>, + <0x6dbc 0x0>, + <0x6dc0 0x0>, + <0x6dc4 0x0>, + <0x6dc8 0x0>, + <0x6dcc 0x0>, + <0x6dd0 0x0>, + <0x6dd4 0x0>, + <0x6dd8 0x0>, + <0x6ddc 0x0>, + <0x6de0 0x0>, + <0x6de4 0x0>, + <0x6de8 0x0>, + <0x6dec 0x0>, + <0x6df0 0x0>, + <0x6df4 0x0>, + <0x6df8 0x0>, + <0x6dfc 0x0>; +}; --- /dev/null 2019-10-24 16:47:25.704025805 +0200 +++ linux-4.4.115-fbx/arch/arm64/boot/dts/qcom/msm-audio-lpass.dtsi 2019-10-29 09:26:22.905195956 +0100 @@ -0,0 +1,529 @@ +/* + * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&soc { + + pcm0: qcom,msm-pcm { + compatible = "qcom,msm-pcm-dsp"; + qcom,msm-pcm-dsp-id = <0>; + }; + + routing: qcom,msm-pcm-routing { + compatible = "qcom,msm-pcm-routing"; + }; + + compr: qcom,msm-compr-dsp { + compatible = "qcom,msm-compr-dsp"; + }; + + pcm1: qcom,msm-pcm-low-latency { + compatible = "qcom,msm-pcm-dsp"; + qcom,msm-pcm-dsp-id = <1>; + qcom,msm-pcm-low-latency; + qcom,latency-level = "regular"; + }; + + pcm2: qcom,msm-ultra-low-latency { + compatible = "qcom,msm-pcm-dsp"; + qcom,msm-pcm-dsp-id = <2>; + qcom,msm-pcm-low-latency; + qcom,latency-level = "ultra"; + }; + + pcm_noirq: qcom,msm-pcm-dsp-noirq { + compatible = "qcom,msm-pcm-dsp-noirq"; + qcom,msm-pcm-low-latency; + qcom,latency-level = "ultra"; + }; + + compress: qcom,msm-compress-dsp { + compatible = "qcom,msm-compress-dsp"; + }; + + voip: qcom,msm-voip-dsp { + compatible = "qcom,msm-voip-dsp"; + }; + + voice: qcom,msm-pcm-voice { + compatible = "qcom,msm-pcm-voice"; + qcom,destroy-cvd; + }; + + stub_codec: qcom,msm-stub-codec { + compatible = "qcom,msm-stub-codec"; + }; + + qcom,msm-dai-fe { + compatible = "qcom,msm-dai-fe"; + }; + + afe: qcom,msm-pcm-afe { + compatible = "qcom,msm-pcm-afe"; + }; + + dai_hdmi: qcom,msm-dai-q6-hdmi { + compatible = "qcom,msm-dai-q6-hdmi"; + qcom,msm-dai-q6-dev-id = <8>; + }; + + dai_dp: qcom,msm-dai-q6-dp { + compatible = "qcom,msm-dai-q6-hdmi"; + qcom,msm-dai-q6-dev-id = <24608>; + }; + + loopback: qcom,msm-pcm-loopback { + compatible = "qcom,msm-pcm-loopback"; + }; + + trans_loopback: qcom,msm-transcode-loopback { + compatible = "qcom,msm-transcode-loopback"; + }; + + qcom,msm-dai-mi2s { + compatible = "qcom,msm-dai-mi2s"; + dai_mi2s0: qcom,msm-dai-q6-mi2s-prim { + compatible = "qcom,msm-dai-q6-mi2s"; + qcom,msm-dai-q6-mi2s-dev-id = <0>; + qcom,msm-mi2s-rx-lines = <3>; + qcom,msm-mi2s-tx-lines = <0>; + }; + + dai_mi2s1: qcom,msm-dai-q6-mi2s-sec { + compatible = "qcom,msm-dai-q6-mi2s"; + qcom,msm-dai-q6-mi2s-dev-id = <1>; + qcom,msm-mi2s-rx-lines = <1>; + qcom,msm-mi2s-tx-lines = <0>; + }; + + dai_mi2s2: qcom,msm-dai-q6-mi2s-tert { + compatible = "qcom,msm-dai-q6-mi2s"; + qcom,msm-dai-q6-mi2s-dev-id = <2>; + qcom,msm-mi2s-rx-lines = <0>; + qcom,msm-mi2s-tx-lines = <3>; + }; + + dai_mi2s3: qcom,msm-dai-q6-mi2s-quat { + compatible = "qcom,msm-dai-q6-mi2s"; + qcom,msm-dai-q6-mi2s-dev-id = <3>; + qcom,msm-mi2s-rx-lines = <1>; + qcom,msm-mi2s-tx-lines = <2>; + }; + + dai_mi2s4: qcom,msm-dai-q6-mi2s-quin { + compatible = "qcom,msm-dai-q6-mi2s"; + qcom,msm-dai-q6-mi2s-dev-id = <5>; + qcom,msm-mi2s-rx-lines = <1>; + qcom,msm-mi2s-tx-lines = <2>; + }; + + dai_mi2s5: qcom,msm-dai-q6-mi2s-senary { + compatible = "qcom,msm-dai-q6-mi2s"; + qcom,msm-dai-q6-mi2s-dev-id = <6>; + qcom,msm-mi2s-rx-lines = <0>; + qcom,msm-mi2s-tx-lines = <3>; + }; + }; + + lsm: qcom,msm-lsm-client { + compatible = "qcom,msm-lsm-client"; + }; + + qcom,msm-dai-q6 { + compatible = "qcom,msm-dai-q6"; + sb_0_rx: qcom,msm-dai-q6-sb-0-rx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <16384>; + }; + + sb_0_tx: qcom,msm-dai-q6-sb-0-tx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <16385>; + }; + + sb_1_rx: qcom,msm-dai-q6-sb-1-rx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <16386>; + }; + + sb_1_tx: qcom,msm-dai-q6-sb-1-tx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <16387>; + }; + + sb_2_rx: qcom,msm-dai-q6-sb-2-rx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <16388>; + }; + + sb_2_tx: qcom,msm-dai-q6-sb-2-tx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <16389>; + }; + + + sb_3_rx: qcom,msm-dai-q6-sb-3-rx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <16390>; + }; + + sb_3_tx: qcom,msm-dai-q6-sb-3-tx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <16391>; + }; + + sb_4_rx: qcom,msm-dai-q6-sb-4-rx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <16392>; + }; + + sb_4_tx: qcom,msm-dai-q6-sb-4-tx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <16393>; + }; + + sb_5_tx: qcom,msm-dai-q6-sb-5-tx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <16395>; + }; + + sb_5_rx: qcom,msm-dai-q6-sb-5-rx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <16394>; + }; + + sb_6_rx: qcom,msm-dai-q6-sb-6-rx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <16396>; + }; + + sb_7_rx: qcom,msm-dai-q6-sb-7-rx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <16398>; + }; + + sb_7_tx: qcom,msm-dai-q6-sb-7-tx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <16399>; + }; + + sb_8_rx: qcom,msm-dai-q6-sb-8-rx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <16400>; + }; + + sb_8_tx: qcom,msm-dai-q6-sb-8-tx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <16401>; + }; + + bt_sco_rx: qcom,msm-dai-q6-bt-sco-rx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <12288>; + }; + + bt_sco_tx: qcom,msm-dai-q6-bt-sco-tx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <12289>; + }; + + int_fm_rx: qcom,msm-dai-q6-int-fm-rx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <12292>; + }; + + int_fm_tx: qcom,msm-dai-q6-int-fm-tx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <12293>; + }; + + afe_pcm_rx: qcom,msm-dai-q6-be-afe-pcm-rx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <224>; + }; + + afe_pcm_tx: qcom,msm-dai-q6-be-afe-pcm-tx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <225>; + }; + + afe_proxy_rx: qcom,msm-dai-q6-afe-proxy-rx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <241>; + }; + + afe_proxy_tx: qcom,msm-dai-q6-afe-proxy-tx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <240>; + }; + + incall_record_rx: qcom,msm-dai-q6-incall-record-rx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <32771>; + }; + + incall_record_tx: qcom,msm-dai-q6-incall-record-tx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <32772>; + }; + + incall_music_rx: qcom,msm-dai-q6-incall-music-rx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <32773>; + }; + + incall_music_2_rx: qcom,msm-dai-q6-incall-music-2-rx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <32770>; + }; + + usb_audio_rx: qcom,msm-dai-q6-usb-audio-rx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <28672>; + }; + + usb_audio_tx: qcom,msm-dai-q6-usb-audio-tx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <28673>; + }; + }; + + hostless: qcom,msm-pcm-hostless { + compatible = "qcom,msm-pcm-hostless"; + }; + + dai_pri_auxpcm: qcom,msm-pri-auxpcm { + compatible = "qcom,msm-auxpcm-dev"; + qcom,msm-cpudai-auxpcm-mode = <0>, <0>; + qcom,msm-cpudai-auxpcm-sync = <1>, <1>; + qcom,msm-cpudai-auxpcm-frame = <5>, <4>; + qcom,msm-cpudai-auxpcm-quant = <2>, <2>; + qcom,msm-cpudai-auxpcm-num-slots = <1>, <1>; + qcom,msm-cpudai-auxpcm-slot-mapping = <1>, <1>; + qcom,msm-cpudai-auxpcm-data = <0>, <0>; + qcom,msm-cpudai-auxpcm-pcm-clk-rate = <2048000>, <2048000>; + qcom,msm-auxpcm-interface = "primary"; + qcom,msm-cpudai-afe-clk-ver = <2>; + }; + + dai_sec_auxpcm: qcom,msm-sec-auxpcm { + compatible = "qcom,msm-auxpcm-dev"; + qcom,msm-cpudai-auxpcm-mode = <0>, <0>; + qcom,msm-cpudai-auxpcm-sync = <1>, <1>; + qcom,msm-cpudai-auxpcm-frame = <5>, <4>; + qcom,msm-cpudai-auxpcm-quant = <2>, <2>; + qcom,msm-cpudai-auxpcm-num-slots = <1>, <1>; + qcom,msm-cpudai-auxpcm-slot-mapping = <1>, <1>; + qcom,msm-cpudai-auxpcm-data = <0>, <0>; + qcom,msm-cpudai-auxpcm-pcm-clk-rate = <2048000>, <2048000>; + qcom,msm-auxpcm-interface = "secondary"; + qcom,msm-cpudai-afe-clk-ver = <2>; + }; + + dai_tert_auxpcm: qcom,msm-tert-auxpcm { + compatible = "qcom,msm-auxpcm-dev"; + qcom,msm-cpudai-auxpcm-mode = <0>, <0>; + qcom,msm-cpudai-auxpcm-sync = <1>, <1>; + qcom,msm-cpudai-auxpcm-frame = <5>, <4>; + qcom,msm-cpudai-auxpcm-quant = <2>, <2>; + qcom,msm-cpudai-auxpcm-num-slots = <1>, <1>; + qcom,msm-cpudai-auxpcm-slot-mapping = <1>, <1>; + qcom,msm-cpudai-auxpcm-data = <0>, <0>; + qcom,msm-cpudai-auxpcm-pcm-clk-rate = <2048000>, <2048000>; + qcom,msm-auxpcm-interface = "tertiary"; + qcom,msm-cpudai-afe-clk-ver = <2>; + }; + + dai_quat_auxpcm: qcom,msm-quat-auxpcm { + compatible = "qcom,msm-auxpcm-dev"; + qcom,msm-cpudai-auxpcm-mode = <0>, <0>; + qcom,msm-cpudai-auxpcm-sync = <1>, <1>; + qcom,msm-cpudai-auxpcm-frame = <5>, <4>; + qcom,msm-cpudai-auxpcm-quant = <2>, <2>; + qcom,msm-cpudai-auxpcm-num-slots = <1>, <1>; + qcom,msm-cpudai-auxpcm-slot-mapping = <1>, <1>; + qcom,msm-cpudai-auxpcm-data = <0>, <0>; + qcom,msm-cpudai-auxpcm-pcm-clk-rate = <2048000>, <2048000>; + qcom,msm-auxpcm-interface = "quaternary"; + qcom,msm-cpudai-afe-clk-ver = <2>; + }; + + hdmi_dba: qcom,msm-hdmi-dba-codec-rx { + compatible = "qcom,msm-hdmi-dba-codec-rx"; + qcom,dba-bridge-chip = "adv7533"; + }; + + msm_audio_ion: qcom,msm-audio-ion { + compatible = "qcom,msm-audio-ion"; + qcom,smmu-version = <1>; + qcom,smmu-enabled; + iommus = <&adsp_io 1>; + }; + + qcom,msm-adsp-loader { + status = "ok"; + compatible = "qcom,adsp-loader"; + qcom,adsp-state = <0>; + }; + + qcom,msm-dai-tdm-pri-rx { + compatible = "qcom,msm-dai-tdm"; + qcom,msm-cpudai-tdm-group-id = <37120>; + qcom,msm-cpudai-tdm-group-num-ports = <1>; + qcom,msm-cpudai-tdm-group-port-id = <36864>; + qcom,msm-cpudai-tdm-clk-rate = <1536000>; + qcom,msm-cpudai-tdm-clk-internal = <1>; + qcom,msm-cpudai-tdm-sync-mode = <1>; + qcom,msm-cpudai-tdm-sync-src = <1>; + qcom,msm-cpudai-tdm-data-out = <0>; + qcom,msm-cpudai-tdm-invert-sync = <1>; + qcom,msm-cpudai-tdm-data-delay = <1>; + dai_pri_tdm_rx_0: qcom,msm-dai-q6-tdm-pri-rx-0 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36864>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + }; + + qcom,msm-dai-tdm-pri-tx { + compatible = "qcom,msm-dai-tdm"; + qcom,msm-cpudai-tdm-group-id = <37121>; + qcom,msm-cpudai-tdm-group-num-ports = <1>; + qcom,msm-cpudai-tdm-group-port-id = <36865>; + qcom,msm-cpudai-tdm-clk-rate = <1536000>; + qcom,msm-cpudai-tdm-clk-internal = <1>; + qcom,msm-cpudai-tdm-sync-mode = <1>; + qcom,msm-cpudai-tdm-sync-src = <1>; + qcom,msm-cpudai-tdm-data-out = <0>; + qcom,msm-cpudai-tdm-invert-sync = <1>; + qcom,msm-cpudai-tdm-data-delay = <1>; + dai_pri_tdm_tx_0: qcom,msm-dai-q6-tdm-pri-tx-0 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36865>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + }; + + qcom,msm-dai-tdm-sec-rx { + compatible = "qcom,msm-dai-tdm"; + qcom,msm-cpudai-tdm-group-id = <37136>; + qcom,msm-cpudai-tdm-group-num-ports = <1>; + qcom,msm-cpudai-tdm-group-port-id = <36880>; + qcom,msm-cpudai-tdm-clk-rate = <1536000>; + qcom,msm-cpudai-tdm-clk-internal = <1>; + qcom,msm-cpudai-tdm-sync-mode = <1>; + qcom,msm-cpudai-tdm-sync-src = <1>; + qcom,msm-cpudai-tdm-data-out = <0>; + qcom,msm-cpudai-tdm-invert-sync = <1>; + qcom,msm-cpudai-tdm-data-delay = <1>; + dai_sec_tdm_rx_0: qcom,msm-dai-q6-tdm-sec-rx-0 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36880>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + }; + + qcom,msm-dai-tdm-sec-tx { + compatible = "qcom,msm-dai-tdm"; + qcom,msm-cpudai-tdm-group-id = <37137>; + qcom,msm-cpudai-tdm-group-num-ports = <1>; + qcom,msm-cpudai-tdm-group-port-id = <36881>; + qcom,msm-cpudai-tdm-clk-rate = <1536000>; + qcom,msm-cpudai-tdm-clk-internal = <1>; + qcom,msm-cpudai-tdm-sync-mode = <1>; + qcom,msm-cpudai-tdm-sync-src = <1>; + qcom,msm-cpudai-tdm-data-out = <0>; + qcom,msm-cpudai-tdm-invert-sync = <1>; + qcom,msm-cpudai-tdm-data-delay = <1>; + dai_sec_tdm_tx_0: qcom,msm-dai-q6-tdm-sec-tx-0 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36881>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + }; + + qcom,msm-dai-tdm-tert-rx { + compatible = "qcom,msm-dai-tdm"; + qcom,msm-cpudai-tdm-group-id = <37152>; + qcom,msm-cpudai-tdm-group-num-ports = <1>; + qcom,msm-cpudai-tdm-group-port-id = <36896>; + qcom,msm-cpudai-tdm-clk-rate = <1536000>; + qcom,msm-cpudai-tdm-clk-internal = <1>; + qcom,msm-cpudai-tdm-sync-mode = <1>; + qcom,msm-cpudai-tdm-sync-src = <1>; + qcom,msm-cpudai-tdm-data-out = <0>; + qcom,msm-cpudai-tdm-invert-sync = <1>; + qcom,msm-cpudai-tdm-data-delay = <1>; + dai_tert_tdm_rx_0: qcom,msm-dai-q6-tdm-tert-rx-0 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36896>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + }; + + qcom,msm-dai-tdm-tert-tx { + compatible = "qcom,msm-dai-tdm"; + qcom,msm-cpudai-tdm-group-id = <37153>; + qcom,msm-cpudai-tdm-group-num-ports = <1>; + qcom,msm-cpudai-tdm-group-port-id = <36897 >; + qcom,msm-cpudai-tdm-clk-rate = <1536000>; + qcom,msm-cpudai-tdm-clk-internal = <1>; + qcom,msm-cpudai-tdm-sync-mode = <1>; + qcom,msm-cpudai-tdm-sync-src = <1>; + qcom,msm-cpudai-tdm-data-out = <0>; + qcom,msm-cpudai-tdm-invert-sync = <1>; + qcom,msm-cpudai-tdm-data-delay = <1>; + dai_tert_tdm_tx_0: qcom,msm-dai-q6-tdm-tert-tx-0 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36897 >; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + }; + + qcom,msm-dai-tdm-quat-rx { + compatible = "qcom,msm-dai-tdm"; + qcom,msm-cpudai-tdm-group-id = <37168>; + qcom,msm-cpudai-tdm-group-num-ports = <1>; + qcom,msm-cpudai-tdm-group-port-id = <36912>; + qcom,msm-cpudai-tdm-clk-rate = <1536000>; + qcom,msm-cpudai-tdm-clk-internal = <1>; + qcom,msm-cpudai-tdm-sync-mode = <1>; + qcom,msm-cpudai-tdm-sync-src = <1>; + qcom,msm-cpudai-tdm-data-out = <0>; + qcom,msm-cpudai-tdm-invert-sync = <1>; + qcom,msm-cpudai-tdm-data-delay = <1>; + dai_quat_tdm_rx_0: qcom,msm-dai-q6-tdm-quat-rx-0 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36912>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + }; + + qcom,msm-dai-tdm-quat-tx { + compatible = "qcom,msm-dai-tdm"; + qcom,msm-cpudai-tdm-group-id = <37169>; + qcom,msm-cpudai-tdm-group-num-ports = <1>; + qcom,msm-cpudai-tdm-group-port-id = <36913 >; + qcom,msm-cpudai-tdm-clk-rate = <1536000>; + qcom,msm-cpudai-tdm-clk-internal = <1>; + qcom,msm-cpudai-tdm-sync-mode = <1>; + qcom,msm-cpudai-tdm-sync-src = <1>; + qcom,msm-cpudai-tdm-data-out = <0>; + qcom,msm-cpudai-tdm-invert-sync = <1>; + qcom,msm-cpudai-tdm-data-delay = <1>; + dai_quat_tdm_tx_0: qcom,msm-dai-q6-tdm-quat-tx-0 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36913 >; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + }; +}; --- /dev/null 2019-10-24 16:47:25.704025805 +0200 +++ linux-4.4.115-fbx/arch/arm64/boot/dts/qcom/msm-gdsc-8998.dtsi 2019-01-22 16:16:21.179225361 +0100 @@ -0,0 +1,146 @@ +/* + * Copyright (c) 2015-2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&soc { + /* GCC GDSCs */ + gdsc_usb30: qcom,gdsc@10f004 { + compatible = "qcom,gdsc"; + regulator-name = "gdsc_usb30"; + reg = <0x10f004 0x4>; + status = "disabled"; + }; + + gdsc_pcie_0: qcom,gdsc@16b004 { + compatible = "qcom,gdsc"; + regulator-name = "gdsc_pcie_0"; + reg = <0x16b004 0x4>; + status = "disabled"; + }; + + gdsc_ufs: qcom,gdsc@175004 { + compatible = "qcom,gdsc"; + regulator-name = "gdsc_ufs"; + reg = <0x175004 0x4>; + status = "disabled"; + }; + + gdsc_hlos1_vote_lpass_adsp: qcom,gdsc@17d034 { + compatible = "qcom,gdsc"; + regulator-name = "gdsc_hlos1_vote_lpass_adsp"; + reg = <0x17d034 0x4>; + qcom,no-status-check-on-disable; + qcom,gds-timeout = <500>; + status = "disabled"; + }; + + gdsc_hlos1_vote_lpass_core: qcom,gdsc@17d038 { + compatible = "qcom,gdsc"; + regulator-name = "gdsc_hlos1_vote_lpass_core"; + reg = <0x17d038 0x4>; + qcom,no-status-check-on-disable; + qcom,gds-timeout = <500>; + status = "disabled"; + }; + + /* MMSS GDSCs */ + gdsc_bimc_smmu: qcom,gdsc@c8ce020 { + compatible = "qcom,gdsc"; + regulator-name = "gdsc_bimc_smmu"; + reg = <0xc8ce020 0x4>, + <0xc8ce024 0x4>; + reg-names = "base", "hw_ctrl_addr"; + qcom,no-status-check-on-disable; + qcom,gds-timeout = <500>; + status = "disabled"; + }; + + gdsc_venus: qcom,gdsc@c8c1024 { + compatible = "qcom,gdsc"; + regulator-name = "gdsc_venus"; + reg = <0xc8c1024 0x4>; + status = "disabled"; + }; + + gdsc_venus_core0: qcom,gdsc@c8c1040 { + compatible = "qcom,gdsc"; + regulator-name = "gdsc_venus_core0"; + reg = <0xc8c1040 0x4>; + status = "disabled"; + }; + + gdsc_venus_core1: qcom,gdsc@c8c1044 { + compatible = "qcom,gdsc"; + regulator-name = "gdsc_venus_core1"; + reg = <0xc8c1044 0x4>; + status = "disabled"; + }; + + gdsc_camss_top: qcom,gdsc@c8c34a0 { + compatible = "qcom,gdsc"; + regulator-name = "gdsc_camss_top"; + reg = <0xc8c34a0 0x4>; + status = "disabled"; + }; + + gdsc_vfe0: qcom,gdsc@c8c3664 { + compatible = "qcom,gdsc"; + regulator-name = "gdsc_vfe0"; + reg = <0xc8c3664 0x4>; + status = "disabled"; + }; + + gdsc_vfe1: qcom,gdsc@c8c3674 { + compatible = "qcom,gdsc"; + regulator-name = "gdsc_vfe1"; + reg = <0xc8c3674 0x4>; + status = "disabled"; + }; + + gdsc_cpp: qcom,gdsc@c8c36d4 { + compatible = "qcom,gdsc"; + regulator-name = "gdsc_cpp"; + reg = <0xc8c36d4 0x4>; + status = "disabled"; + }; + + gdsc_mdss: qcom,gdsc@c8c2304 { + compatible = "qcom,gdsc"; + regulator-name = "gdsc_mdss"; + reg = <0xc8c2304 0x4>; + status = "disabled"; + }; + + /* GPU GDSCs */ + gdsc_gpu_cx: qcom,gdsc@5066004 { + compatible = "qcom,gdsc"; + regulator-name = "gdsc_gpu_cx"; + reg = <0x5066004 0x4>, + <0x5066008 0x4>; + reg-names = "base", "hw_ctrl_addr"; + qcom,no-status-check-on-disable; + qcom,gds-timeout = <500>; + status = "disabled"; + }; + + gdsc_gpu_gx: qcom,gdsc@5066094 { + compatible = "qcom,gdsc"; + regulator-name = "gdsc_gpu_gx"; + reg = <0x5066094 0x4>, + <0x5065130 0x4>, + <0x5066090 0x4>; + reg-names = "base", "domain_addr", "sw_reset"; + qcom,retain-periph; + qcom,reset-aon-logic; + status = "disabled"; + }; +}; --- /dev/null 2019-10-24 16:47:25.704025805 +0200 +++ linux-4.4.115-fbx/arch/arm64/boot/dts/qcom/msm-pm8005.dtsi 2019-01-22 16:16:21.179225361 +0100 @@ -0,0 +1,103 @@ +/* Copyright (c) 2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include + +&spmi_bus { + qcom,pm8005@4 { + compatible = "qcom,spmi-pmic"; + reg = <0x4 SPMI_USID>; + #address-cells = <2>; + #size-cells = <0>; + + pm8005_revid: qcom,revid@100 { + compatible = "qcom,qpnp-revid"; + reg = <0x100 0x100>; + }; + + qcom,temp-alarm@2400 { + compatible = "qcom,qpnp-temp-alarm"; + reg = <0x2400 0x100>; + interrupts = <0x4 0x24 0x0 IRQ_TYPE_EDGE_RISING>; + label = "pm8005_tz"; + }; + + pm8005_gpios: gpios { + compatible = "qcom,qpnp-pin"; + gpio-controller; + #gpio-cells = <2>; + #address-cells = <1>; + #size-cells = <1>; + label = "pm8005-gpio"; + + gpio@c000 { + reg = <0xc000 0x100>; + qcom,pin-num = <1>; + status = "disabled"; + }; + + gpio@c100 { + reg = <0xc100 0x100>; + qcom,pin-num = <2>; + status = "disabled"; + }; + + gpio@c200 { + reg = <0xc200 0x100>; + qcom,pin-num = <3>; + status = "disabled"; + }; + + gpio@c300 { + reg = <0xc300 0x100>; + qcom,pin-num = <4>; + status = "disabled"; + }; + }; + }; + + qcom,pm8005@5 { + compatible ="qcom,spmi-pmic"; + reg = <0x5 SPMI_USID>; + #address-cells = <2>; + #size-cells = <0>; + + regulator@1400 { + compatible = "qcom,qpnp-regulator"; + reg = <0x1400 0x100>; + regulator-name = "pm8005_s1"; + status = "disabled"; + }; + + regulator@1700 { + compatible = "qcom,qpnp-regulator"; + reg = <0x1700 0x100>; + regulator-name = "pm8005_s2"; + status = "disabled"; + }; + + regulator@1a00 { + compatible = "qcom,qpnp-regulator"; + reg = <0x1a00 0x100>; + regulator-name = "pm8005_s3"; + status = "disabled"; + }; + + regulator@1d00 { + compatible = "qcom,qpnp-regulator"; + reg = <0x1d00 0x100>; + regulator-name = "pm8005_s4"; + status = "disabled"; + }; + }; +}; --- /dev/null 2019-10-24 16:47:25.704025805 +0200 +++ linux-4.4.115-fbx/arch/arm64/boot/dts/qcom/msm-pm8998.dtsi 2019-01-22 16:16:21.179225361 +0100 @@ -0,0 +1,328 @@ +/* Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include + +&spmi_bus { + qcom,pm8998@0 { + compatible ="qcom,spmi-pmic"; + reg = <0x0 SPMI_USID>; + #address-cells = <2>; + #size-cells = <0>; + + pm8998_revid: qcom,revid@100 { + compatible = "qcom,qpnp-revid"; + reg = <0x100 0x100>; + }; + + qcom,power-on@800 { + compatible = "qcom,qpnp-power-on"; + reg = <0x800 0x100>; + interrupts = <0x0 0x8 0x0 IRQ_TYPE_NONE>, + <0x0 0x8 0x1 IRQ_TYPE_NONE>, + <0x0 0x8 0x4 IRQ_TYPE_NONE>, + <0x0 0x8 0x5 IRQ_TYPE_NONE>; + interrupt-names = "kpdpwr", "resin", + "resin-bark", "kpdpwr-resin-bark"; + qcom,pon-dbc-delay = <15625>; + qcom,system-reset; + qcom,store-hard-reset-reason; + + qcom,pon_1 { + qcom,pon-type = <0>; + qcom,pull-up = <1>; + linux,code = <116>; + }; + + qcom,pon_2 { + qcom,pon-type = <1>; + qcom,pull-up = <1>; + linux,code = <114>; + }; + + qcom,pon_3 { + qcom,pon-type = <3>; + qcom,support-reset = <1>; + qcom,pull-up = <1>; + qcom,s1-timer = <6720>; + qcom,s2-timer = <2000>; + qcom,s2-type = ; + qcom,use-bark; + }; + }; + + qcom,temp-alarm@2400 { + compatible = "qcom,qpnp-temp-alarm"; + reg = <0x2400 0x100>; + interrupts = <0x0 0x24 0x0 IRQ_TYPE_EDGE_RISING>; + label = "pm8998_tz"; + qcom,channel-num = <6>; + qcom,temp_alarm-vadc = <&pm8998_vadc>; + }; + + pm8998_gpios: gpios { + compatible = "qcom,qpnp-pin"; + gpio-controller; + #gpio-cells = <2>; + #address-cells = <1>; + #size-cells = <1>; + label = "pm8998-gpio"; + + gpio@c000 { + reg = <0xc000 0x100>; + qcom,pin-num = <1>; + status = "disabled"; + }; + + gpio@c100 { + reg = <0xc100 0x100>; + qcom,pin-num = <2>; + status = "disabled"; + }; + + gpio@c200 { + reg = <0xc200 0x100>; + qcom,pin-num = <3>; + status = "disabled"; + }; + + gpio@c300 { + reg = <0xc300 0x100>; + qcom,pin-num = <4>; + status = "disabled"; + }; + + gpio@c400 { + reg = <0xc400 0x100>; + qcom,pin-num = <5>; + status = "disabled"; + }; + + gpio@c500 { + reg = <0xc500 0x100>; + qcom,pin-num = <6>; + status = "disabled"; + }; + + gpio@c600 { + reg = <0xc600 0x100>; + qcom,pin-num = <7>; + status = "disabled"; + }; + + gpio@c700 { + reg = <0xc700 0x100>; + qcom,pin-num = <8>; + status = "disabled"; + }; + + gpio@c800 { + reg = <0xc800 0x100>; + qcom,pin-num = <9>; + status = "disabled"; + }; + + gpio@c900 { + reg = <0xc900 0x100>; + qcom,pin-num = <10>; + status = "disabled"; + }; + + gpio@ca00 { + reg = <0xca00 0x100>; + qcom,pin-num = <11>; + status = "disabled"; + }; + + gpio@cb00 { + reg = <0xcb00 0x100>; + qcom,pin-num = <12>; + status = "disabled"; + }; + + gpio@cc00 { + reg = <0xcc00 0x100>; + qcom,pin-num = <13>; + status = "disabled"; + }; + + gpio@cd00 { + reg = <0xcd00 0x100>; + qcom,pin-num = <14>; + status = "disabled"; + }; + + gpio@ce00 { + reg = <0xce00 0x100>; + qcom,pin-num = <15>; + status = "disabled"; + }; + + gpio@cf00 { + reg = <0xcf00 0x100>; + qcom,pin-num = <16>; + status = "disabled"; + }; + + gpio@d000 { + reg = <0xd000 0x100>; + qcom,pin-num = <17>; + status = "disabled"; + }; + + gpio@d100 { + reg = <0xd100 0x100>; + qcom,pin-num = <18>; + status = "disabled"; + }; + + gpio@d200 { + reg = <0xd200 0x100>; + qcom,pin-num = <19>; + status = "disabled"; + }; + + gpio@d300 { + reg = <0xd300 0x100>; + qcom,pin-num = <20>; + status = "disabled"; + }; + + gpio@d400 { + reg = <0xd400 0x100>; + qcom,pin-num = <21>; + status = "disabled"; + }; + + gpio@d500 { + reg = <0xd500 0x100>; + qcom,pin-num = <22>; + status = "disabled"; + }; + + gpio@d600 { + reg = <0xd600 0x100>; + qcom,pin-num = <23>; + status = "disabled"; + }; + + gpio@d700 { + reg = <0xd700 0x100>; + qcom,pin-num = <24>; + status = "disabled"; + }; + + gpio@d800 { + reg = <0xd800 0x100>; + qcom,pin-num = <25>; + status = "disabled"; + }; + + gpio@d900 { + reg = <0xd900 0x100>; + qcom,pin-num = <26>; + status = "disabled"; + }; + }; + + pm8998_coincell: qcom,coincell@2800 { + compatible = "qcom,qpnp-coincell"; + reg = <0x2800 0x100>; + }; + + pm8998_rtc: qcom,pm8998_rtc { + compatible = "qcom,qpnp-rtc"; + #address-cells = <1>; + #size-cells = <1>; + qcom,qpnp-rtc-write = <0>; + qcom,qpnp-rtc-alarm-pwrup = <0>; + + qcom,pm8998_rtc_rw@6000 { + reg = <0x6000 0x100>; + }; + qcom,pm8998_rtc_alarm@6100 { + reg = <0x6100 0x100>; + interrupts = <0x0 0x61 0x1 IRQ_TYPE_NONE>; + }; + }; + + pm8998_vadc: vadc@3100 { + compatible = "qcom,qpnp-vadc-hc"; + reg = <0x3100 0x100>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "eoc-int-en-set"; + qcom,adc-bit-resolution = <15>; + qcom,adc-vdd-reference = <1875>; + + chan@6 { + label = "die_temp"; + reg = <6>; + qcom,decimation = <2>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "absolute"; + qcom,scale-function = <3>; + qcom,hw-settle-time = <0>; + qcom,fast-avg-setup = <0>; + qcom,cal-val = <0>; + }; + + chan@0 { + label = "ref_gnd"; + reg = <0>; + qcom,decimation = <2>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "absolute"; + qcom,scale-function = <0>; + qcom,hw-settle-time = <0>; + qcom,fast-avg-setup = <0>; + qcom,cal-val = <0>; + }; + + chan@1 { + label = "ref_1250v"; + reg = <1>; + qcom,decimation = <2>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "absolute"; + qcom,scale-function = <0>; + qcom,hw-settle-time = <0>; + qcom,fast-avg-setup = <0>; + qcom,cal-val = <0>; + }; + }; + + pm8998_adc_tm: vadc@3400 { + compatible = "qcom,qpnp-adc-tm-hc"; + reg = <0x3400 0x100>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0x0 0x34 0x0 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "eoc-int-en-set"; + qcom,adc-bit-resolution = <15>; + qcom,adc-vdd-reference = <1875>; + qcom,adc_tm-vadc = <&pm8998_vadc>; + qcom,decimation = <0>; + qcom,fast-avg-setup = <0>; + }; + }; + + qcom,pm8998@1 { + compatible ="qcom,spmi-pmic"; + reg = <0x1 SPMI_USID>; + #address-cells = <2>; + #size-cells = <0>; + }; +}; --- /dev/null 2019-10-24 16:47:25.704025805 +0200 +++ linux-4.4.115-fbx/arch/arm64/boot/dts/qcom/msm-pm8998-rpm-regulator.dtsi 2019-01-22 16:16:21.179225361 +0100 @@ -0,0 +1,600 @@ +/* Copyright (c) 2015-2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&rpm_bus { + /* PM8998 S1 + S6 = VDD_CX supply */ + rpm-regulator-smpa1 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "rwcx"; + qcom,resource-id = <0>; + qcom,regulator-type = <1>; + status = "disabled"; + + regulator-s1 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm8998_s1"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-smpa2 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "smpa"; + qcom,resource-id = <2>; + qcom,regulator-type = <1>; + status = "disabled"; + + regulator-s2 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm8998_s2"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-smpa3 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "smpa"; + qcom,resource-id = <3>; + qcom,regulator-type = <1>; + status = "disabled"; + + regulator-s3 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm8998_s3"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-smpa4 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "smpa"; + qcom,resource-id = <4>; + qcom,regulator-type = <1>; + status = "disabled"; + + regulator-s4 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm8998_s4"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-smpa5 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "smpa"; + qcom,resource-id = <5>; + qcom,regulator-type = <1>; + status = "disabled"; + + regulator-s5 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm8998_s5"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-smpa7 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "smpa"; + qcom,resource-id = <7>; + qcom,regulator-type = <1>; + status = "disabled"; + + regulator-s7 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm8998_s7"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-smpa8 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "smpa"; + qcom,resource-id = <8>; + qcom,regulator-type = <1>; + status = "disabled"; + + regulator-s8 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm8998_s8"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + /* PM8998 S9 = VDD_MX supply */ + rpm-regulator-smpa9 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "rwmx"; + qcom,resource-id = <0>; + qcom,regulator-type = <1>; + status = "disabled"; + + regulator-s9 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm8998_s9"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa1 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <1>; + qcom,regulator-type = <0>; + status = "disabled"; + + regulator-l1 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm8998_l1"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa2 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <2>; + qcom,regulator-type = <0>; + status = "disabled"; + + regulator-l2 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm8998_l2"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa3 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <3>; + qcom,regulator-type = <0>; + status = "disabled"; + + regulator-l3 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm8998_l3"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa4 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "rwsm"; + qcom,resource-id = <0>; + qcom,regulator-type = <0>; + status = "disabled"; + + regulator-l4 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm8998_l4"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa5 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <5>; + qcom,regulator-type = <0>; + status = "disabled"; + + regulator-l5 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm8998_l5"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa6 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <6>; + qcom,regulator-type = <0>; + status = "disabled"; + + regulator-l6 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm8998_l6"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa7 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <7>; + qcom,regulator-type = <0>; + status = "disabled"; + + regulator-l7 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm8998_l7"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa8 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <8>; + qcom,regulator-type = <0>; + status = "disabled"; + + regulator-l8 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm8998_l8"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa9 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <9>; + qcom,regulator-type = <0>; + status = "disabled"; + + regulator-l9 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm8998_l9"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa10 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <10>; + qcom,regulator-type = <0>; + status = "disabled"; + + regulator-l10 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm8998_l10"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa11 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <11>; + qcom,regulator-type = <0>; + status = "disabled"; + + regulator-l11 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm8998_l11"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa12 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <12>; + qcom,regulator-type = <0>; + status = "disabled"; + + regulator-l12 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm8998_l12"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa13 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <13>; + qcom,regulator-type = <0>; + status = "disabled"; + + regulator-l13 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm8998_l13"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa14 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <14>; + qcom,regulator-type = <0>; + status = "disabled"; + + regulator-l14 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm8998_l14"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa15 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <15>; + qcom,regulator-type = <0>; + status = "disabled"; + + regulator-l15 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm8998_l15"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa16 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <16>; + qcom,regulator-type = <0>; + status = "disabled"; + + regulator-l16 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm8998_l16"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa17 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <17>; + qcom,regulator-type = <0>; + status = "disabled"; + + regulator-l17 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm8998_l17"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa18 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <18>; + qcom,regulator-type = <0>; + status = "disabled"; + + regulator-l18 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm8998_l18"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa19 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <19>; + qcom,regulator-type = <0>; + status = "disabled"; + + regulator-l19 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm8998_l19"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa20 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <20>; + qcom,regulator-type = <0>; + status = "disabled"; + + regulator-l20 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm8998_l20"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa21 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <21>; + qcom,regulator-type = <0>; + status = "disabled"; + + regulator-l21 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm8998_l21"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa22 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <22>; + qcom,regulator-type = <0>; + status = "disabled"; + + regulator-l22 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm8998_l22"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa23 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <23>; + qcom,regulator-type = <0>; + status = "disabled"; + + regulator-l23 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm8998_l23"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa24 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <24>; + qcom,regulator-type = <0>; + status = "disabled"; + + regulator-l24 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm8998_l24"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa25 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <25>; + qcom,regulator-type = <0>; + status = "disabled"; + + regulator-l25 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm8998_l25"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa26 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <26>; + qcom,regulator-type = <0>; + status = "disabled"; + + regulator-l26 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm8998_l26"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa27 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "rwsc"; + qcom,resource-id = <0>; + qcom,regulator-type = <0>; + status = "disabled"; + + regulator-l27 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm8998_l27"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa28 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <28>; + qcom,regulator-type = <0>; + status = "disabled"; + + regulator-l28 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm8998_l28"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-vsa1 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "vsa"; + qcom,resource-id = <1>; + qcom,regulator-type = <2>; + status = "disabled"; + + regulator-lvs1 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm8998_lvs1"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-vsa2 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "vsa"; + qcom,resource-id = <2>; + qcom,regulator-type = <2>; + status = "disabled"; + + regulator-lvs2 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm8998_lvs2"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-bobb { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "bobb"; + qcom,resource-id = <1>; + qcom,regulator-type = <4>; + status = "disabled"; + + regulator-bob { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm8998_bob"; + qcom,set = <3>; + status = "disabled"; + }; + }; +}; --- /dev/null 2019-10-24 16:47:25.704025805 +0200 +++ linux-4.4.115-fbx/arch/arm64/boot/dts/qcom/msm-pmi8998.dtsi 2019-01-22 16:16:21.179225361 +0100 @@ -0,0 +1,777 @@ +/* Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include + +&spmi_bus { + qcom,pmi8998@2 { + compatible = "qcom,spmi-pmic"; + reg = <0x2 SPMI_USID>; + #address-cells = <2>; + #size-cells = <0>; + + pmi8998_revid: qcom,revid@100 { + compatible = "qcom,qpnp-revid"; + reg = <0x100 0x100>; + qcom,fab-id-valid; + }; + + qcom,power-on@800 { + compatible = "qcom,qpnp-power-on"; + reg = <0x800 0x100>; + }; + + pmi8998_misc: qcom,misc@900 { + compatible = "qcom,qpnp-misc"; + reg = <0x900 0x100>; + }; + + qcom,temp-alarm@2400 { + compatible = "qcom,qpnp-temp-alarm"; + reg = <0x2400 0x100>; + interrupts = <0x2 0x24 0x0 IRQ_TYPE_EDGE_RISING>; + label = "pmi8998_tz"; + }; + + pmi8998_gpios: gpios { + compatible = "qcom,qpnp-pin"; + gpio-controller; + #gpio-cells = <2>; + #address-cells = <1>; + #size-cells = <1>; + label = "pmi8998-gpio"; + + gpio@c000 { + reg = <0xc000 0x100>; + qcom,pin-num = <1>; + status = "disabled"; + }; + + gpio@c100 { + reg = <0xc100 0x100>; + qcom,pin-num = <2>; + status = "disabled"; + }; + + gpio@c200 { + reg = <0xc200 0x100>; + qcom,pin-num = <3>; + status = "disabled"; + }; + + gpio@c300 { + reg = <0xc300 0x100>; + qcom,pin-num = <4>; + status = "disabled"; + }; + + gpio@c400 { + reg = <0xc400 0x100>; + qcom,pin-num = <5>; + status = "disabled"; + }; + + gpio@c500 { + reg = <0xc500 0x100>; + qcom,pin-num = <6>; + status = "disabled"; + }; + + gpio@c600 { + reg = <0xc600 0x100>; + qcom,pin-num = <7>; + status = "disabled"; + }; + + gpio@c700 { + reg = <0xc700 0x100>; + qcom,pin-num = <8>; + status = "disabled"; + }; + + gpio@c800 { + reg = <0xc800 0x100>; + qcom,pin-num = <9>; + status = "disabled"; + }; + + gpio@c900 { + reg = <0xc900 0x100>; + qcom,pin-num = <10>; + status = "disabled"; + }; + + gpio@ca00 { + reg = <0xca00 0x100>; + qcom,pin-num = <11>; + status = "disabled"; + }; + + gpio@cb00 { + reg = <0xcb00 0x100>; + qcom,pin-num = <12>; + status = "disabled"; + }; + + gpio@cc00 { + reg = <0xcc00 0x100>; + qcom,pin-num = <13>; + status = "disabled"; + }; + + gpio@cd00 { + reg = <0xcd00 0x100>; + qcom,pin-num = <14>; + status = "disabled"; + }; + }; + + qcom,qpnp-qnovo@1500 { + compatible = "qcom,qpnp-qnovo"; + reg = <0x1500 0x100>; + interrupts = <0x2 0x15 0x0 IRQ_TYPE_NONE>; + interrupt-names = "ptrain-done"; + qcom,pmic-revid = <&pmi8998_revid>; + }; + + pmi8998_charger: qcom,qpnp-smb2 { + compatible = "qcom,qpnp-smb2"; + #address-cells = <1>; + #size-cells = <1>; + + qcom,pmic-revid = <&pmi8998_revid>; + + io-channels = <&pmi8998_rradc 8>, + <&pmi8998_rradc 10>, + <&pmi8998_rradc 3>, + <&pmi8998_rradc 4>; + io-channel-names = "charger_temp", + "charger_temp_max", + "usbin_i", + "usbin_v"; + + qcom,boost-threshold-ua = <100000>; + qcom,wipower-max-uw = <5000000>; + dpdm-supply = <&qusb_phy0>; + + qcom,thermal-mitigation + = <3000000 1500000 1000000 500000>; + + qcom,chgr@1000 { + reg = <0x1000 0x100>; + interrupts = + <0x2 0x10 0x0 IRQ_TYPE_EDGE_RISING>, + <0x2 0x10 0x1 IRQ_TYPE_EDGE_RISING>, + <0x2 0x10 0x2 IRQ_TYPE_EDGE_RISING>, + <0x2 0x10 0x3 IRQ_TYPE_EDGE_RISING>, + <0x2 0x10 0x4 IRQ_TYPE_EDGE_RISING>; + + interrupt-names = "chg-error", + "chg-state-change", + "step-chg-state-change", + "step-chg-soc-update-fail", + "step-chg-soc-update-request"; + }; + + qcom,otg@1100 { + reg = <0x1100 0x100>; + interrupts = <0x2 0x11 0x0 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x11 0x1 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x11 0x2 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x11 0x3 IRQ_TYPE_EDGE_BOTH>; + + interrupt-names = "otg-fail", + "otg-overcurrent", + "otg-oc-dis-sw-sts", + "testmode-change-detect"; + }; + + qcom,bat-if@1200 { + reg = <0x1200 0x100>; + interrupts = + <0x2 0x12 0x0 IRQ_TYPE_EDGE_RISING>, + <0x2 0x12 0x1 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x12 0x2 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x12 0x3 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x12 0x4 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x12 0x5 IRQ_TYPE_EDGE_BOTH>; + + interrupt-names = "bat-temp", + "bat-ocp", + "bat-ov", + "bat-low", + "bat-therm-or-id-missing", + "bat-terminal-missing"; + }; + + qcom,usb-chgpth@1300 { + reg = <0x1300 0x100>; + interrupts = + <0x2 0x13 0x0 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x13 0x1 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x13 0x2 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x13 0x3 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x13 0x4 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x13 0x5 IRQ_TYPE_EDGE_RISING>, + <0x2 0x13 0x6 IRQ_TYPE_EDGE_RISING>, + <0x2 0x13 0x7 IRQ_TYPE_EDGE_RISING>; + + interrupt-names = "usbin-collapse", + "usbin-lt-3p6v", + "usbin-uv", + "usbin-ov", + "usbin-plugin", + "usbin-src-change", + "usbin-icl-change", + "type-c-change"; + }; + + qcom,dc-chgpth@1400 { + reg = <0x1400 0x100>; + interrupts = + <0x2 0x14 0x0 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x14 0x1 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x14 0x2 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x14 0x3 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x14 0x4 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x14 0x5 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x14 0x6 IRQ_TYPE_EDGE_RISING>; + + interrupt-names = "dcin-collapse", + "dcin-lt-3p6v", + "dcin-uv", + "dcin-ov", + "dcin-plugin", + "div2-en-dg", + "dcin-icl-change"; + }; + + qcom,chgr-misc@1600 { + reg = <0x1600 0x100>; + interrupts = + <0x2 0x16 0x0 IRQ_TYPE_EDGE_RISING>, + <0x2 0x16 0x1 IRQ_TYPE_EDGE_RISING>, + <0x2 0x16 0x2 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x16 0x3 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x16 0x4 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x16 0x5 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x16 0x6 IRQ_TYPE_EDGE_FALLING>, + <0x2 0x16 0x7 IRQ_TYPE_EDGE_BOTH>; + + interrupt-names = "wdog-snarl", + "wdog-bark", + "aicl-fail", + "aicl-done", + "high-duty-cycle", + "input-current-limiting", + "temperature-change", + "switcher-power-ok"; + }; + }; + + pmi8998_pdphy: qcom,usb-pdphy@1700 { + compatible = "qcom,qpnp-pdphy"; + reg = <0x1700 0x100>; + vdd-pdphy-supply = <&pm8998_l24>; + vbus-supply = <&smb2_vbus>; + vconn-supply = <&smb2_vconn>; + interrupts = <0x2 0x17 0x0 IRQ_TYPE_EDGE_RISING>, + <0x2 0x17 0x1 IRQ_TYPE_EDGE_RISING>, + <0x2 0x17 0x2 IRQ_TYPE_EDGE_RISING>, + <0x2 0x17 0x3 IRQ_TYPE_EDGE_RISING>, + <0x2 0x17 0x4 IRQ_TYPE_EDGE_RISING>, + <0x2 0x17 0x5 IRQ_TYPE_EDGE_RISING>, + <0x2 0x17 0x6 IRQ_TYPE_EDGE_RISING>; + + interrupt-names = "sig-tx", + "sig-rx", + "msg-tx", + "msg-rx", + "msg-tx-failed", + "msg-tx-discarded", + "msg-rx-discarded"; + + qcom,default-sink-caps = <5000 3000>, /* 5V @ 3A */ + <9000 3000>, /* 9V @ 3A */ + <12000 2250>; /* 12V @ 2.25A */ + }; + + bcl@4200 { + compatible = "qcom,msm-bcl-lmh"; + reg = <0x4200 0xff>, + <0x4300 0xff>; + reg-names = "fg_user_adc", + "fg_lmh"; + interrupts = <0x2 0x42 0x0 IRQ_TYPE_NONE>, + <0x2 0x42 0x2 IRQ_TYPE_NONE>; + interrupt-names = "bcl-high-ibat-int", + "bcl-low-vbat-int"; + qcom,vbat-polling-delay-ms = <100>; + qcom,ibat-polling-delay-ms = <100>; + }; + + pmi8998_rradc: rradc@4500 { + compatible = "qcom,rradc"; + reg = <0x4500 0x100>; + #address-cells = <1>; + #size-cells = <0>; + #io-channel-cells = <1>; + qcom,pmic-revid = <&pmi8998_revid>; + }; + + pmi8998_fg: qpnp,fg { + compatible = "qcom,fg-gen3"; + #address-cells = <1>; + #size-cells = <1>; + qcom,pmic-revid = <&pmi8998_revid>; + io-channels = <&pmi8998_rradc 0>; + io-channel-names = "rradc_batt_id"; + qcom,rradc-base = <0x4500>; + qcom,fg-esr-timer-awake = <96 96>; + qcom,fg-esr-timer-asleep = <256 256>; + qcom,fg-esr-timer-charging = <0 96>; + qcom,cycle-counter-en; + status = "okay"; + + qcom,fg-batt-soc@4000 { + status = "okay"; + reg = <0x4000 0x100>; + interrupts = <0x2 0x40 0x0 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x40 0x1 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x40 0x2 + IRQ_TYPE_EDGE_RISING>, + <0x2 0x40 0x3 + IRQ_TYPE_EDGE_RISING>, + <0x2 0x40 0x4 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x40 0x5 + IRQ_TYPE_EDGE_RISING>, + <0x2 0x40 0x6 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x40 0x7 IRQ_TYPE_EDGE_BOTH>; + interrupt-names = "soc-update", + "soc-ready", + "bsoc-delta", + "msoc-delta", + "msoc-low", + "msoc-empty", + "msoc-high", + "msoc-full"; + }; + + qcom,fg-batt-info@4100 { + status = "okay"; + reg = <0x4100 0x100>; + interrupts = <0x2 0x41 0x0 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x41 0x1 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x41 0x2 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x41 0x3 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x41 0x6 IRQ_TYPE_EDGE_BOTH>; + interrupt-names = "vbatt-pred-delta", + "vbatt-low", + "esr-delta", + "batt-missing", + "batt-temp-delta"; + }; + + qcom,fg-memif@4400 { + status = "okay"; + reg = <0x4400 0x100>; + interrupts = <0x2 0x44 0x0 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x44 0x1 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x44 0x2 IRQ_TYPE_EDGE_BOTH>; + interrupt-names = "ima-rdy", + "mem-xcp", + "dma-grant"; + }; + }; + }; + + qcom,pmi8998@3 { + compatible ="qcom,spmi-pmic"; + reg = <0x3 SPMI_USID>; + #address-cells = <2>; + #size-cells = <0>; + + pmi8998_pwm_1: pwm@b100 { + compatible = "qcom,qpnp-pwm"; + reg = <0xb100 0x100>, + <0xb042 0x7e>; + reg-names = "qpnp-lpg-channel-base", + "qpnp-lpg-lut-base"; + qcom,lpg-lut-size = <0x7e>; + qcom,channel-id = <1>; + qcom,supported-sizes = <6>, <9>; + qcom,ramp-index = <0>; + #pwm-cells = <2>; + status = "disabled"; + }; + + pmi8998_pwm_2: pwm@b200 { + compatible = "qcom,qpnp-pwm"; + reg = <0xb200 0x100>, + <0xb042 0x7e>; + reg-names = "qpnp-lpg-channel-base", + "qpnp-lpg-lut-base"; + qcom,lpg-lut-size = <0x7e>; + qcom,channel-id = <2>; + qcom,supported-sizes = <6>, <9>; + qcom,ramp-index = <1>; + #pwm-cells = <2>; + status = "disabled"; + }; + + pmi8998_pwm_3: pwm@b300 { + compatible = "qcom,qpnp-pwm"; + reg = <0xb300 0x100>, + <0xb042 0x7e>; + reg-names = "qpnp-lpg-channel-base", + "qpnp-lpg-lut-base"; + qcom,lpg-lut-size = <0x7e>; + qcom,channel-id = <3>; + qcom,supported-sizes = <6>, <9>; + qcom,ramp-index = <2>; + #pwm-cells = <2>; + }; + + pmi8998_pwm_4: pwm@b400 { + compatible = "qcom,qpnp-pwm"; + reg = <0xb400 0x100>, + <0xb042 0x7e>; + reg-names = "qpnp-lpg-channel-base", + "qpnp-lpg-lut-base"; + qcom,lpg-lut-size = <0x7e>; + qcom,channel-id = <4>; + qcom,supported-sizes = <6>, <9>; + qcom,ramp-index = <3>; + #pwm-cells = <2>; + }; + + pmi8998_pwm_5: pwm@b500 { + compatible = "qcom,qpnp-pwm"; + reg = <0xb500 0x100>, + <0xb042 0x7e>; + reg-names = "qpnp-lpg-channel-base", + "qpnp-lpg-lut-base"; + qcom,lpg-lut-size = <0x7e>; + qcom,channel-id = <5>; + qcom,supported-sizes = <6>, <9>; + qcom,ramp-index = <4>; + #pwm-cells = <2>; + }; + + pmi8998_pwm_6: pwm@b600 { + compatible = "qcom,qpnp-pwm"; + reg = <0xb600 0x100>, + <0xb042 0x7e>; + reg-names = "qpnp-lpg-channel-base", + "qpnp-lpg-lut-base"; + qcom,lpg-lut-size = <0x7e>; + qcom,channel-id = <6>; + qcom,supported-sizes = <6>, <9>; + qcom,ramp-index = <5>; + #pwm-cells = <2>; + status = "disabled"; + }; + + qcom,leds@d000 { + compatible = "qcom,leds-qpnp"; + reg = <0xd000 0x100>; + label = "rgb"; + status = "okay"; + + red_led: qcom,rgb_0 { + label = "rgb"; + qcom,id = <3>; + qcom,mode = "pwm"; + pwms = <&pmi8998_pwm_5 0 0>; + qcom,pwm-us = <1000>; + qcom,max-current = <12>; + qcom,default-state = "off"; + linux,name = "red"; + linux,default-trigger = + "battery-charging"; + }; + + green_led: qcom,rgb_1 { + label = "rgb"; + qcom,id = <4>; + qcom,mode = "pwm"; + pwms = <&pmi8998_pwm_4 0 0>; + qcom,pwm-us = <1000>; + qcom,max-current = <12>; + qcom,default-state = "off"; + linux,name = "green"; + linux,default-trigger = "battery-full"; + }; + + blue_led: qcom,rgb_2 { + label = "rgb"; + qcom,id = <5>; + qcom,mode = "pwm"; + pwms = <&pmi8998_pwm_3 0 0>; + qcom,pwm-us = <1000>; + qcom,max-current = <12>; + qcom,default-state = "off"; + linux,name = "blue"; + linux,default-trigger = "boot-indication"; + }; + }; + + labibb: qpnp-labibb-regulator { + compatible = "qcom,qpnp-labibb-regulator"; + #address-cells = <1>; + #size-cells = <1>; + qcom,pmic-revid = <&pmi8998_revid>; + status = "disabled"; + + ibb_regulator: qcom,ibb@dc00 { + reg = <0xdc00 0x100>; + reg-names = "ibb_reg"; + regulator-name = "ibb_reg"; + + regulator-min-microvolt = <4600000>; + regulator-max-microvolt = <6000000>; + + interrupts = <0x3 0xdc 0x2 + IRQ_TYPE_EDGE_RISING>; + interrupt-names = "ibb-sc-err"; + + qcom,qpnp-ibb-min-voltage = <1400000>; + qcom,qpnp-ibb-step-size = <100000>; + qcom,qpnp-ibb-slew-rate = <2000000>; + qcom,qpnp-ibb-use-default-voltage; + qcom,qpnp-ibb-init-voltage = <5500000>; + qcom,qpnp-ibb-init-amoled-voltage = <4000000>; + qcom,qpnp-ibb-init-lcd-voltage = <5500000>; + + qcom,qpnp-ibb-soft-start = <1000>; + + qcom,qpnp-ibb-lab-pwrup-delay = <8000>; + qcom,qpnp-ibb-lab-pwrdn-delay = <8000>; + qcom,qpnp-ibb-en-discharge; + + qcom,qpnp-ibb-full-pull-down; + qcom,qpnp-ibb-pull-down-enable; + qcom,qpnp-ibb-switching-clock-frequency = + <1480>; + qcom,qpnp-ibb-limit-maximum-current = <1550>; + qcom,qpnp-ibb-debounce-cycle = <16>; + qcom,qpnp-ibb-limit-max-current-enable; + qcom,qpnp-ibb-ps-enable; + }; + + lab_regulator: qcom,lab@de00 { + reg = <0xde00 0x100>; + reg-names = "lab"; + regulator-name = "lab_reg"; + + regulator-min-microvolt = <4600000>; + regulator-max-microvolt = <6000000>; + + interrupts = <0x3 0xde 0x0 + IRQ_TYPE_EDGE_RISING>, + <0x3 0xde 0x1 + IRQ_TYPE_EDGE_RISING>; + interrupt-names = "lab-vreg-ok", "lab-sc-err"; + + qcom,qpnp-lab-min-voltage = <4600000>; + qcom,qpnp-lab-step-size = <100000>; + qcom,qpnp-lab-slew-rate = <5000>; + qcom,qpnp-lab-use-default-voltage; + qcom,qpnp-lab-init-voltage = <5500000>; + qcom,qpnp-lab-init-amoled-voltage = <4600000>; + qcom,qpnp-lab-init-lcd-voltage = <5500000>; + + qcom,qpnp-lab-soft-start = <800>; + + qcom,qpnp-lab-full-pull-down; + qcom,qpnp-lab-pull-down-enable; + qcom,qpnp-lab-switching-clock-frequency = + <1600>; + qcom,qpnp-lab-limit-maximum-current = <1600>; + qcom,qpnp-lab-limit-max-current-enable; + qcom,qpnp-lab-ps-threshold = <70>; + qcom,qpnp-lab-ps-enable; + qcom,qpnp-lab-nfet-size = <100>; + qcom,qpnp-lab-pfet-size = <100>; + qcom,qpnp-lab-max-precharge-time = <500>; + }; + }; + + pmi8998_wled: qcom,leds@d800 { + compatible = "qcom,qpnp-wled"; + reg = <0xd800 0x100>, + <0xd900 0x100>; + reg-names = "qpnp-wled-ctrl-base", + "qpnp-wled-sink-base"; + interrupts = <0x3 0xd8 0x1 IRQ_TYPE_EDGE_RISING>, + <0x3 0xd8 0x2 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "ovp-irq", "sc-irq"; + linux,name = "wled"; + linux,default-trigger = "bkl-trigger"; + qcom,fdbk-output = "auto"; + qcom,vref-uv = <127500>; + qcom,switch-freq-khz = <800>; + qcom,ovp-mv = <29600>; + qcom,ilim-ma = <970>; + qcom,boost-duty-ns = <26>; + qcom,mod-freq-khz = <9600>; + qcom,dim-mode = "hybrid"; + qcom,hyb-thres = <625>; + qcom,sync-dly-us = <800>; + qcom,fs-curr-ua = <25000>; + qcom,cons-sync-write-delay-us = <1000>; + qcom,led-strings-list = [00 01 02 03]; + qcom,en-ext-pfet-sc-pro; + qcom,pmic-revid = <&pmi8998_revid>; + qcom,loop-auto-gm-en; + qcom,auto-calibration-enable; + status = "okay"; + }; + + pmi8998_haptics: qcom,haptic@c000 { + status = "disabled"; + compatible = "qcom,qpnp-haptic"; + reg = <0xc000 0x100>; + interrupts = <0x3 0xc0 0x0 IRQ_TYPE_EDGE_BOTH>, + <0x3 0xc0 0x1 IRQ_TYPE_EDGE_BOTH>; + interrupt-names = "sc-irq", "play-irq"; + qcom,pmic-revid = <&pmi8998_revid>; + qcom,pmic-misc = <&pmi8998_misc>; + qcom,misc-clk-trim-error-reg = <0xf3>; + qcom,actuator-type = "lra"; + qcom,play-mode = "direct"; + qcom,vmax-mv = <3200>; + qcom,ilim-ma = <800>; + qcom,wave-shape = "square"; + qcom,wave-play-rate-us = <6667>; + qcom,int-pwm-freq-khz = <505>; + qcom,sc-deb-cycles = <8>; + qcom,en-brake; + qcom,brake-pattern = [03 03 00 00]; + qcom,lra-high-z = "opt1"; + qcom,lra-auto-res-mode = "qwd"; + qcom,lra-res-cal-period = <4>; + qcom,correct-lra-drive-freq; + }; + + flash_led: qcom,leds@d300 { + compatible = "qcom,qpnp-flash-led-v2"; + status = "okay"; + reg = <0xd300 0x100>; + label = "flash"; + interrupts = <0x3 0xd3 0x0 IRQ_TYPE_EDGE_RISING>, + <0x3 0xd3 0x3 IRQ_TYPE_EDGE_RISING>, + <0x3 0xd3 0x4 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "led-fault-irq", + "all-ramp-down-done-irq", + "all-ramp-up-done-irq"; + qcom,hdrm-auto-mode; + qcom,short-circuit-det; + qcom,open-circuit-det; + qcom,vph-droop-det; + qcom,thermal-derate-en; + qcom,thermal-derate-current = <200 500 1000>; + qcom,isc-delay = <192>; + qcom,pmic-revid = <&pmi8998_revid>; + + pmi8998_flash0: qcom,flash_0 { + label = "flash"; + qcom,led-name = "led:flash_0"; + qcom,max-current = <1500>; + qcom,default-led-trigger = "flash0_trigger"; + qcom,id = <0>; + qcom,current-ma = <1000>; + qcom,duration-ms = <1280>; + qcom,ires-ua = <12500>; + qcom,hdrm-voltage-mv = <325>; + qcom,hdrm-vol-hi-lo-win-mv = <100>; + }; + + pmi8998_flash1: qcom,flash_1 { + label = "flash"; + qcom,led-name = "led:flash_1"; + qcom,max-current = <1500>; + qcom,default-led-trigger = "flash1_trigger"; + qcom,id = <1>; + qcom,current-ma = <1000>; + qcom,duration-ms = <1280>; + qcom,ires-ua = <12500>; + qcom,hdrm-voltage-mv = <325>; + qcom,hdrm-vol-hi-lo-win-mv = <100>; + }; + + pmi8998_flash2: qcom,flash_2 { + label = "flash"; + qcom,led-name = "led:flash_2"; + qcom,max-current = <750>; + qcom,default-led-trigger = "flash2_trigger"; + qcom,id = <2>; + qcom,current-ma = <500>; + qcom,duration-ms = <1280>; + qcom,ires-ua = <12500>; + qcom,hdrm-voltage-mv = <325>; + qcom,hdrm-vol-hi-lo-win-mv = <100>; + }; + + pmi8998_torch0: qcom,torch_0 { + label = "torch"; + qcom,led-name = "led:torch_0"; + qcom,max-current = <500>; + qcom,default-led-trigger = "torch0_trigger"; + qcom,id = <0>; + qcom,current-ma = <300>; + qcom,ires-ua = <12500>; + qcom,hdrm-voltage-mv = <325>; + qcom,hdrm-vol-hi-lo-win-mv = <100>; + }; + + pmi8998_torch1: qcom,torch_1 { + label = "torch"; + qcom,led-name = "led:torch_1"; + qcom,max-current = <500>; + qcom,default-led-trigger = "torch1_trigger"; + qcom,id = <1>; + qcom,current-ma = <300>; + qcom,ires-ua = <12500>; + qcom,hdrm-voltage-mv = <325>; + qcom,hdrm-vol-hi-lo-win-mv = <100>; + }; + + pmi8998_torch2: qcom,torch_2 { + label = "torch"; + qcom,led-name = "led:torch_2"; + qcom,max-current = <500>; + qcom,default-led-trigger = "torch2_trigger"; + qcom,id = <2>; + qcom,current-ma = <300>; + qcom,ires-ua = <12500>; + qcom,hdrm-voltage-mv = <325>; + qcom,hdrm-vol-hi-lo-win-mv = <100>; + }; + + pmi8998_switch0: qcom,led_switch_0 { + label = "switch"; + qcom,led-name = "led:switch_0"; + qcom,led-mask = <3>; + qcom,default-led-trigger = "switch0_trigger"; + }; + + pmi8998_switch1: qcom,led_switch_1 { + label = "switch"; + qcom,led-name = "led:switch_1"; + qcom,led-mask = <4>; + qcom,default-led-trigger = "switch1_trigger"; + }; + }; + }; +}; --- /dev/null 2019-10-24 16:47:25.704025805 +0200 +++ linux-4.4.115-fbx/arch/arm64/boot/dts/qcom/msm-rdbg.dtsi 2019-01-22 16:16:21.179225361 +0100 @@ -0,0 +1,106 @@ +/* Copyright (c) 2015, 2017, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&soc { + smp2pgpio_rdbg_2_in: qcom,smp2pgpio-rdbg-2-in { + compatible = "qcom,smp2pgpio"; + qcom,entry-name = "rdbg"; + qcom,remote-pid = <2>; + qcom,is-inbound; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + qcom,smp2pgpio_client_rdbg_2_in { + compatible = "qcom,smp2pgpio_client_rdbg_2_in"; + gpios = <&smp2pgpio_rdbg_2_in 0 0>; + }; + + smp2pgpio_rdbg_2_out: qcom,smp2pgpio-rdbg-2-out { + compatible = "qcom,smp2pgpio"; + qcom,entry-name = "rdbg"; + qcom,remote-pid = <2>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + qcom,smp2pgpio_client_rdbg_2_out { + compatible = "qcom,smp2pgpio_client_rdbg_2_out"; + gpios = <&smp2pgpio_rdbg_2_out 0 0>; + }; + + smp2pgpio_rdbg_1_in: qcom,smp2pgpio-rdbg-1-in { + compatible = "qcom,smp2pgpio"; + qcom,entry-name = "rdbg"; + qcom,remote-pid = <1>; + qcom,is-inbound; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + qcom,smp2pgpio_client_rdbg_1_in { + compatible = "qcom,smp2pgpio_client_rdbg_1_in"; + gpios = <&smp2pgpio_rdbg_1_in 0 0>; + }; + + smp2pgpio_rdbg_1_out: qcom,smp2pgpio-rdbg-1-out { + compatible = "qcom,smp2pgpio"; + qcom,entry-name = "rdbg"; + qcom,remote-pid = <1>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + qcom,smp2pgpio_client_rdbg_1_out { + compatible = "qcom,smp2pgpio_client_rdbg_1_out"; + gpios = <&smp2pgpio_rdbg_1_out 0 0>; + }; + + smp2pgpio_rdbg_5_in: qcom,smp2pgpio-rdbg-5-in { + compatible = "qcom,smp2pgpio"; + qcom,entry-name = "rdbg"; + qcom,remote-pid = <5>; + qcom,is-inbound; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + qcom,smp2pgpio_client_rdbg_5_in { + compatible = "qcom,smp2pgpio_client_rdbg_5_in"; + gpios = <&smp2pgpio_rdbg_5_in 0 0>; + }; + + smp2pgpio_rdbg_5_out: qcom,smp2pgpio-rdbg-5-out { + compatible = "qcom,smp2pgpio"; + qcom,entry-name = "rdbg"; + qcom,remote-pid = <5>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + qcom,smp2pgpio_client_rdbg_5_out { + compatible = "qcom,smp2pgpio_client_rdbg_5_out"; + gpios = <&smp2pgpio_rdbg_5_out 0 0>; + }; +}; --- /dev/null 2019-10-24 16:47:25.704025805 +0200 +++ linux-4.4.115-fbx/arch/arm64/boot/dts/qcom/msm-smb138x.dtsi 2019-01-22 16:16:21.179225361 +0100 @@ -0,0 +1,137 @@ +/* Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +&i2c_7 { + status = "okay"; + smb138x: qcom,smb138x@8 { + compatible = "qcom,i2c-pmic"; + reg = <0x8>; + #address-cells = <1>; + #size-cells = <0>; + interrupt-parent = <&spmi_bus>; + interrupts = <0x0 0xd1 0x0 IRQ_TYPE_LEVEL_LOW>; + interrupt_names = "smb138x"; + interrupt-controller; + #interrupt-cells = <3>; + qcom,periph-map = <0x10 0x11 0x12 0x13 0x14 0x16 0x36>; + + smb138x_revid: qcom,revid@100 { + compatible = "qcom,qpnp-revid"; + reg = <0x100 0x100>; + }; + + smb138x_tadc: qcom,tadc@3600 { + compatible = "qcom,tadc"; + reg = <0x3600 0x100>; + #address-cells = <1>; + #size-cells = <0>; + #io-channel-cells = <1>; + interrupt-parent = <&smb138x>; + interrupts = <0x36 0x0 IRQ_TYPE_EDGE_BOTH>; + interrupt-names = "eoc"; + + batt_temp@0 { + reg = <0>; + qcom,rbias = <68100>; + qcom,rtherm-at-25degc = <68000>; + qcom,beta-coefficient = <3450>; + }; + + skin_temp@1 { + reg = <1>; + qcom,rbias = <33000>; + qcom,rtherm-at-25degc = <68000>; + qcom,beta-coefficient = <3450>; + }; + + die_temp@2 { + reg = <2>; + qcom,scale = <(-1306)>; + qcom,offset = <397904>; + }; + + batt_i@3 { + reg = <3>; + qcom,channel = <3>; + qcom,scale = <(-20000000)>; + }; + + batt_v@4 { + reg = <4>; + qcom,scale = <5000000>; + }; + + input_i@5 { + reg = <5>; + qcom,scale = <14285714>; + }; + + input_v@6 { + reg = <6>; + qcom,scale = <25000000>; + }; + + otg_i@7 { + reg = <7>; + qcom,scale = <5714286>; + }; + }; + + smb1381_charger: qcom,smb1381-charger@1000 { + compatible = "qcom,smb138x-parallel-slave"; + qcom,pmic-revid = <&smb138x_revid>; + reg = <0x1000 0x700>; + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&smb138x>; + io-channels = + <&smb138x_tadc 1>, + <&smb138x_tadc 2>, + <&smb138x_tadc 3>, + <&smb138x_tadc 14>, + <&smb138x_tadc 15>, + <&smb138x_tadc 16>, + <&smb138x_tadc 17>; + io-channel-names = + "connector_temp", + "charger_temp", + "batt_i", + "connector_temp_thr1", + "connector_temp_thr2", + "connector_temp_thr3", + "charger_temp_max"; + + qcom,chgr@1000 { + reg = <0x1000 0x100>; + interrupts = <0x10 0x1 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "chg-state-change"; + }; + + qcom,chgr-misc@1600 { + reg = <0x1600 0x100>; + interrupts = <0x16 0x1 IRQ_TYPE_EDGE_RISING>, + <0x16 0x6 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog-bark", + "temperature-change"; + }; + }; + }; +}; + +&smb1381_charger { + smb138x_vbus: qcom,smb138x-vbus { + status = "disabled"; + regulator-name = "smb138x-vbus"; + }; +}; --- /dev/null 2019-10-24 16:47:25.704025805 +0200 +++ linux-4.4.115-fbx/arch/arm64/boot/dts/qcom/skeleton64.dtsi 2019-01-22 16:16:21.215225687 +0100 @@ -0,0 +1,15 @@ +/* + * Skeleton device tree in the 64 bits version; the bare minimum + * needed to boot; just include and add a compatible value. The + * bootloader will typically populate the memory node. + */ + +/ { + #address-cells = <2>; + #size-cells = <2>; + cpus { }; + soc { }; + chosen { }; + aliases { }; + memory { device_type = "memory"; reg = <0 0 0 0>; }; +}; --- /dev/null 2019-10-24 16:47:25.704025805 +0200 +++ linux-4.4.115-fbx/arch/arm64/crypto/poly-hash-ce-core.S 2019-01-22 16:16:21.535228585 +0100 @@ -0,0 +1,163 @@ +/* + * Accelerated poly_hash implementation with ARMv8 PMULL instructions. + * + * Based on ghash-ce-core.S. + * + * Copyright (C) 2014 Linaro Ltd. + * Copyright (C) 2017 Google, Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include + + KEY .req v0 + KEY2 .req v1 + T1 .req v2 + T2 .req v3 + GSTAR .req v4 + XL .req v5 + XM .req v6 + XH .req v7 + + .text + .arch armv8-a+crypto + + /* 16-byte aligned (2**4 = 16); not required, but might as well */ + .align 4 +.Lgstar: + .quad 0x87, 0x87 + +/* + * void pmull_poly_hash_update(le128 *digest, const le128 *key, + * const u8 *src, unsigned int blocks, + * unsigned int partial); + */ +ENTRY(pmull_poly_hash_update) + + /* Load digest into XL */ + ld1 {XL.16b}, [x0] + + /* Load key into KEY */ + ld1 {KEY.16b}, [x1] + + /* Load g*(x) = g(x) + x^128 = x^7 + x^2 + x + 1 into both halves of + * GSTAR */ + adr x1, .Lgstar + ld1 {GSTAR.2d}, [x1] + + /* Set KEY2 to (KEY[1]+KEY[0]):(KEY[1]+KEY[0]). This is needed for + * Karatsuba multiplication. */ + ext KEY2.16b, KEY.16b, KEY.16b, #8 + eor KEY2.16b, KEY2.16b, KEY.16b + + /* If 'partial' is nonzero, then we're finishing a pending block and + * should go right to the multiplication. */ + cbnz w4, 1f + +0: + /* Add the next block from 'src' to the digest */ + ld1 {T1.16b}, [x2], #16 + eor XL.16b, XL.16b, T1.16b + sub w3, w3, #1 + +1: + /* + * Multiply the current 128-bit digest (a1:a0, in XL) by the 128-bit key + * (b1:b0, in KEY) using Karatsuba multiplication. + */ + + /* T1 = (a1+a0):(a1+a0) */ + ext T1.16b, XL.16b, XL.16b, #8 + eor T1.16b, T1.16b, XL.16b + + /* XH = a1 * b1 */ + pmull2 XH.1q, XL.2d, KEY.2d + + /* XL = a0 * b0 */ + pmull XL.1q, XL.1d, KEY.1d + + /* XM = (a1+a0) * (b1+b0) */ + pmull XM.1q, T1.1d, KEY2.1d + + /* XM += (XH[0]:XL[1]) + XL + XH */ + ext T1.16b, XL.16b, XH.16b, #8 + eor T2.16b, XL.16b, XH.16b + eor XM.16b, XM.16b, T1.16b + eor XM.16b, XM.16b, T2.16b + + /* + * Now the 256-bit product is in XH[1]:XM:XL[0]. It represents a + * polynomial over GF(2) with degree as large as 255. We need to + * compute its remainder modulo g(x) = x^128+x^7+x^2+x+1. For this it + * is sufficient to compute the remainder of the high half 'c(x)x^128' + * add it to the low half. To reduce the high half we use the Barrett + * reduction method. The basic idea is that we can express the + * remainder p(x) as g(x)q(x) mod x^128, where q(x) = (c(x)x^128)/g(x). + * As detailed in [1], to avoid having to divide by g(x) at runtime the + * following equivalent expression can be derived: + * + * p(x) = [ g*(x)((c(x)q+(x))/x^128) ] mod x^128 + * + * where g*(x) = x^128+g(x) = x^7+x^2+x+1, and q+(x) = x^256/g(x) = g(x) + * in this case. This is also equivalent to: + * + * p(x) = [ g*(x)((c(x)(x^128 + g*(x)))/x^128) ] mod x^128 + * = [ g*(x)(c(x) + (c(x)g*(x))/x^128) ] mod x^128 + * + * Since deg g*(x) < 64: + * + * p(x) = [ g*(x)(c(x) + ((c(x)/x^64)g*(x))/x^64) ] mod x^128 + * = [ g*(x)((c(x)/x^64)x^64 + (c(x) mod x^64) + + * ((c(x)/x^64)g*(x))/x^64) ] mod x^128 + * + * Letting t(x) = g*(x)(c(x)/x^64): + * + * p(x) = [ t(x)x^64 + g*(x)((c(x) mod x^64) + t(x)/x^64) ] mod x^128 + * + * Therefore, to do the reduction we only need to issue two 64-bit => + * 128-bit carryless multiplications: g*(x) times c(x)/x^64, and g*(x) + * times ((c(x) mod x^64) + t(x)/x^64). (Multiplication by x^64 doesn't + * count since it is simply a shift or move.) + * + * An alternate reduction method, also based on Barrett reduction and + * described in [1], uses only shifts and XORs --- no multiplications. + * However, the method with multiplications requires fewer instructions + * and is faster on processors with fast carryless multiplication. + * + * [1] "Intel Carry-Less Multiplication Instruction and its Usage for + * Computing the GCM Mode", + * https://software.intel.com/sites/default/files/managed/72/cc/clmul-wp-rev-2.02-2014-04-20.pdf + */ + + /* 256-bit product is XH[1]:XM:XL[0], so c(x) is XH[1]:XM[1] */ + + /* T1 = t(x) = g*(x)(c(x)/x^64) */ + pmull2 T1.1q, GSTAR.2d, XH.2d + + /* T2 = g*(x)((c(x) mod x^64) + t(x)/x^64) */ + eor T2.16b, XM.16b, T1.16b + pmull2 T2.1q, GSTAR.2d, T2.2d + + /* Make XL[0] be the low half of the 128-bit result by adding the low 64 + * bits of the T2 term to what was already there. The 't(x)x^64' term + * makes no difference, so skip it. */ + eor XL.16b, XL.16b, T2.16b + + /* Make XL[1] be the high half of the 128-bit result by adding the high + * 64 bits of the 't(x)x^64' and T2 terms to what was already in XM[0], + * then moving XM[0] to XL[1]. */ + eor XM.16b, XM.16b, T1.16b + ext T2.16b, T2.16b, T2.16b, #8 + eor XM.16b, XM.16b, T2.16b + mov XL.d[1], XM.d[0] + + /* If more blocks remain, then loop back to process the next block; + * else, store the digest and return. */ + cbnz w3, 0b + st1 {XL.16b}, [x0] + ret +ENDPROC(pmull_poly_hash_update) --- /dev/null 2019-10-24 16:47:25.704025805 +0200 +++ linux-4.4.115-fbx/arch/arm64/crypto/poly-hash-ce-glue.c 2019-01-22 16:16:21.535228585 +0100 @@ -0,0 +1,166 @@ +/* + * Accelerated poly_hash implementation with ARMv8 PMULL instructions. + * + * Based on ghash-ce-glue.c. + * + * poly_hash is part of the HEH (Hash-Encrypt-Hash) encryption mode, proposed in + * Internet Draft https://tools.ietf.org/html/draft-cope-heh-01. + * + * poly_hash is very similar to GHASH: both algorithms are keyed hashes which + * interpret their input data as coefficients of a polynomial over GF(2^128), + * then calculate a hash value by evaluating that polynomial at the point given + * by the key, e.g. using Horner's rule. The difference is that poly_hash uses + * the more natural "ble" convention to represent GF(2^128) elements, whereas + * GHASH uses the less natural "lle" convention (see include/crypto/gf128mul.h). + * The ble convention makes it simpler to implement GF(2^128) multiplication. + * + * Copyright (C) 2014 Linaro Ltd. + * Copyright (C) 2017 Google Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include + +/* + * Note: in this algorithm we currently use 'le128' to represent GF(2^128) + * elements, even though poly_hash-generic uses 'be128'. Both types are + * actually "wrong" because the elements are actually in 'ble' format, and there + * should be a ble type to represent this --- as well as lle, bbe, and lbe types + * for the other conventions for representing GF(2^128) elements. But + * practically it doesn't matter which type we choose here, so we just use le128 + * since it's arguably more accurate, while poly_hash-generic still has to use + * be128 because the generic GF(2^128) multiplication functions all take be128. + */ + +struct poly_hash_desc_ctx { + le128 digest; + unsigned int count; +}; + +asmlinkage void pmull_poly_hash_update(le128 *digest, const le128 *key, + const u8 *src, unsigned int blocks, + unsigned int partial); + +static int poly_hash_setkey(struct crypto_shash *tfm, + const u8 *key, unsigned int keylen) +{ + if (keylen != sizeof(le128)) { + crypto_shash_set_flags(tfm, CRYPTO_TFM_RES_BAD_KEY_LEN); + return -EINVAL; + } + + memcpy(crypto_shash_ctx(tfm), key, sizeof(le128)); + return 0; +} + +static int poly_hash_init(struct shash_desc *desc) +{ + struct poly_hash_desc_ctx *ctx = shash_desc_ctx(desc); + + ctx->digest = (le128) { 0 }; + ctx->count = 0; + return 0; +} + +static int poly_hash_update(struct shash_desc *desc, const u8 *src, + unsigned int len) +{ + struct poly_hash_desc_ctx *ctx = shash_desc_ctx(desc); + unsigned int partial = ctx->count % sizeof(le128); + u8 *dst = (u8 *)&ctx->digest + partial; + + ctx->count += len; + + /* Finishing at least one block? */ + if (partial + len >= sizeof(le128)) { + const le128 *key = crypto_shash_ctx(desc->tfm); + + if (partial) { + /* Finish the pending block. */ + unsigned int n = sizeof(le128) - partial; + + len -= n; + do { + *dst++ ^= *src++; + } while (--n); + } + + /* + * Do the real work. If 'partial' is nonzero, this starts by + * multiplying 'digest' by 'key'. Then for each additional full + * block it adds the block to 'digest' and multiplies by 'key'. + */ + kernel_neon_begin_partial(8); + pmull_poly_hash_update(&ctx->digest, key, src, + len / sizeof(le128), partial); + kernel_neon_end(); + + src += len - (len % sizeof(le128)); + len %= sizeof(le128); + dst = (u8 *)&ctx->digest; + } + + /* Continue adding the next block to 'digest'. */ + while (len--) + *dst++ ^= *src++; + return 0; +} + +static int poly_hash_final(struct shash_desc *desc, u8 *out) +{ + struct poly_hash_desc_ctx *ctx = shash_desc_ctx(desc); + unsigned int partial = ctx->count % sizeof(le128); + + /* Finish the last block if needed. */ + if (partial) { + const le128 *key = crypto_shash_ctx(desc->tfm); + + kernel_neon_begin_partial(8); + pmull_poly_hash_update(&ctx->digest, key, NULL, 0, partial); + kernel_neon_end(); + } + + memcpy(out, &ctx->digest, sizeof(le128)); + return 0; +} + +static struct shash_alg poly_hash_alg = { + .digestsize = sizeof(le128), + .init = poly_hash_init, + .update = poly_hash_update, + .final = poly_hash_final, + .setkey = poly_hash_setkey, + .descsize = sizeof(struct poly_hash_desc_ctx), + .base = { + .cra_name = "poly_hash", + .cra_driver_name = "poly_hash-ce", + .cra_priority = 300, + .cra_ctxsize = sizeof(le128), + .cra_module = THIS_MODULE, + }, +}; + +static int __init poly_hash_ce_mod_init(void) +{ + return crypto_register_shash(&poly_hash_alg); +} + +static void __exit poly_hash_ce_mod_exit(void) +{ + crypto_unregister_shash(&poly_hash_alg); +} + +MODULE_DESCRIPTION("Polynomial evaluation hash using ARMv8 Crypto Extensions"); +MODULE_AUTHOR("Eric Biggers "); +MODULE_LICENSE("GPL v2"); + +module_cpu_feature_match(PMULL, poly_hash_ce_mod_init); +module_exit(poly_hash_ce_mod_exit); --- /dev/null 2019-10-24 16:47:25.704025805 +0200 +++ linux-4.4.115-fbx/arch/arm64/include/asm/app_api.h 2019-01-22 16:16:21.535228585 +0100 @@ -0,0 +1,50 @@ +/* Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __ASM_APP_API_H +#define __ASM_APP_API_H + +#include +#include +#include + +#define APP_SETTING_BIT 30 +#define MAX_ENTRIES 10 + +/* + * APIs to set / clear the app setting bits + * in the register. + */ +#ifdef CONFIG_MSM_APP_API +extern void set_app_setting_bit(uint32_t bit); +extern void clear_app_setting_bit(uint32_t bit); +extern void set_app_setting_bit_for_32bit_apps(void); +extern void clear_app_setting_bit_for_32bit_apps(void); +#else +static inline void set_app_setting_bit(uint32_t bit) {} +static inline void clear_app_setting_bit(uint32_t bit) {} +static inline void set_app_setting_bit_for_32bit_apps(void) {} +static inline void clear_app_setting_bit_for_32bit_apps(void) {} +#endif + +#ifdef CONFIG_MSM_APP_SETTINGS +extern void switch_app_setting_bit(struct task_struct *prev, + struct task_struct *next); +extern void switch_32bit_app_setting_bit(struct task_struct *prev, + struct task_struct *next); +extern void apply_app_setting_bit(struct file *file); +extern bool use_app_setting; +extern bool use_32bit_app_setting; +extern bool use_32bit_app_setting_pro; +#endif + +#endif --- /dev/null 2019-10-24 16:47:25.704025805 +0200 +++ linux-4.4.115-fbx/arch/arm64/include/asm/brk-imm.h 2019-01-22 16:16:21.535228585 +0100 @@ -0,0 +1,25 @@ +/* + * Copyright (C) 2012 ARM Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __ASM_BRK_IMM_H +#define __ASM_BRK_IMM_H + +/* + * #imm16 values used for BRK instruction generation + * Allowed values for kgdb are 0x400 - 0x7ff + * 0x100: for triggering a fault on purpose (reserved) + * 0x400: for dynamic BRK instruction + * 0x401: for compile time BRK instruction + * 0x800: kernel-mode BUG() and WARN() traps + */ +#define FAULT_BRK_IMM 0x100 +#define KGDB_DYN_DBG_BRK_IMM 0x400 +#define KGDB_COMPILED_DBG_BRK_IMM 0x401 +#define BUG_BRK_IMM 0x800 + +#endif --- /dev/null 2019-10-24 16:47:25.704025805 +0200 +++ linux-4.4.115-fbx/arch/arm64/include/asm/checksum.h 2019-01-22 16:16:21.535228585 +0100 @@ -0,0 +1,51 @@ +/* + * Copyright (C) 2016 ARM Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +#ifndef __ASM_CHECKSUM_H +#define __ASM_CHECKSUM_H + +#include + +static inline __sum16 csum_fold(__wsum csum) +{ + u32 sum = (__force u32)csum; + sum += (sum >> 16) | (sum << 16); + return ~(__force __sum16)(sum >> 16); +} +#define csum_fold csum_fold + +static inline __sum16 ip_fast_csum(const void *iph, unsigned int ihl) +{ + __uint128_t tmp; + u64 sum; + + tmp = *(const __uint128_t *)iph; + iph += 16; + ihl -= 4; + tmp += ((tmp >> 64) | (tmp << 64)); + sum = tmp >> 64; + do { + sum += *(const u32 *)iph; + iph += 4; + } while (--ihl); + + sum += ((sum >> 32) | (sum << 32)); + return csum_fold(sum >> 32); +} +#define ip_fast_csum ip_fast_csum + +#include + +#endif /* __ASM_CHECKSUM_H */ --- /dev/null 2019-10-24 16:47:25.704025805 +0200 +++ linux-4.4.115-fbx/arch/arm64/include/asm/current.h 2019-01-22 16:16:21.535228585 +0100 @@ -0,0 +1,35 @@ +#ifndef __ASM_CURRENT_H +#define __ASM_CURRENT_H + +#include + +#include + +#ifndef __ASSEMBLY__ + +#ifdef CONFIG_THREAD_INFO_IN_TASK +struct task_struct; + +/* + * We don't use read_sysreg() as we want the compiler to cache the value where + * possible. + */ +static __always_inline struct task_struct *get_current(void) +{ + unsigned long sp_el0; + + asm ("mrs %0, sp_el0" : "=r" (sp_el0)); + + return (struct task_struct *)sp_el0; +} +#define current get_current() +#else +#include +#define get_current() (current_thread_info()->task) +#define current get_current() +#endif + +#endif /* __ASSEMBLY__ */ + +#endif /* __ASM_CURRENT_H */ + --- /dev/null 2019-10-24 16:47:25.704025805 +0200 +++ linux-4.4.115-fbx/arch/arm64/include/asm/debugv8.h 2019-01-22 16:16:21.539228621 +0100 @@ -0,0 +1,229 @@ +/* Copyright (c) 2014, 2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __ASM_DEBUGV8_H +#define __ASM_DEBUGV8_H + +#include + +/* 32 bit register reads for aarch 64 bit */ +#define dbg_readl(reg) RSYSL_##reg() +/* 64 bit register reads for aarch 64 bit */ +#define dbg_readq(reg) RSYSQ_##reg() +/* 32 and 64 bit register writes for aarch 64 bit */ +#define dbg_write(val, reg) WSYS_##reg(val) + +#define MRSL(reg) \ +({ \ +uint32_t val; \ +asm volatile("mrs %0, "#reg : "=r" (val)); \ +val; \ +}) + +#define MRSQ(reg) \ +({ \ +uint64_t val; \ +asm volatile("mrs %0, "#reg : "=r" (val)); \ +val; \ +}) + +#define MSR(val, reg) \ +({ \ +asm volatile("msr "#reg", %0" : : "r" (val)); \ +}) + +/* + * Debug Feature Register + * + * Read only + */ +#define RSYSQ_ID_AA64DFR0_EL1() MRSQ(ID_AA64DFR0_EL1) + +/* + * Debug Registers + * + * Available only in DBGv8 + * + * Read only + * MDCCSR_EL0, MDRAR_EL1, OSLSR_EL1, DBGDTRRX_EL0, DBGAUTHSTATUS_EL1 + * + * Write only + * DBGDTRTX_EL0, OSLAR_EL1 + */ +/* 32 bit registers */ +#define RSYSL_DBGDTRRX_EL0() MRSL(DBGDTRRX_EL0) +#define RSYSL_MDCCSR_EL0() MRSL(MDCCSR_EL0) +#define RSYSL_MDSCR_EL1() MRSL(MDSCR_EL1) +#define RSYSL_OSDTRRX_EL1() MRSL(OSDTRRX_EL1) +#define RSYSL_OSDTRTX_EL1() MRSL(OSDTRTX_EL1) +#define RSYSL_OSDLR_EL1() MRSL(OSDLR_EL1) +#define RSYSL_OSLSR_EL1() MRSL(OSLSR_EL1) +#define RSYSL_MDCCINT_EL1() MRSL(MDCCINT_EL1) +#define RSYSL_OSECCR_EL1() MRSL(OSECCR_EL1) +#define RSYSL_DBGPRCR_EL1() MRSL(DBGPRCR_EL1) +#define RSYSL_DBGBCR0_EL1() MRSL(DBGBCR0_EL1) +#define RSYSL_DBGBCR1_EL1() MRSL(DBGBCR1_EL1) +#define RSYSL_DBGBCR2_EL1() MRSL(DBGBCR2_EL1) +#define RSYSL_DBGBCR3_EL1() MRSL(DBGBCR3_EL1) +#define RSYSL_DBGBCR4_EL1() MRSL(DBGBCR4_EL1) +#define RSYSL_DBGBCR5_EL1() MRSL(DBGBCR5_EL1) +#define RSYSL_DBGBCR6_EL1() MRSL(DBGBCR6_EL1) +#define RSYSL_DBGBCR7_EL1() MRSL(DBGBCR7_EL1) +#define RSYSL_DBGBCR8_EL1() MRSL(DBGBCR8_EL1) +#define RSYSL_DBGBCR9_EL1() MRSL(DBGBCR9_EL1) +#define RSYSL_DBGBCR10_EL1() MRSL(DBGBCR10_EL1) +#define RSYSL_DBGBCR11_EL1() MRSL(DBGBCR11_EL1) +#define RSYSL_DBGBCR12_EL1() MRSL(DBGBCR12_EL1) +#define RSYSL_DBGBCR13_EL1() MRSL(DBGBCR13_EL1) +#define RSYSL_DBGBCR14_EL1() MRSL(DBGBCR14_EL1) +#define RSYSL_DBGBCR15_EL1() MRSL(DBGBCR15_EL1) +#define RSYSL_DBGWCR0_EL1() MRSL(DBGWCR0_EL1) +#define RSYSL_DBGWCR1_EL1() MRSL(DBGWCR1_EL1) +#define RSYSL_DBGWCR2_EL1() MRSL(DBGWCR2_EL1) +#define RSYSL_DBGWCR3_EL1() MRSL(DBGWCR3_EL1) +#define RSYSL_DBGWCR4_EL1() MRSL(DBGWCR4_EL1) +#define RSYSL_DBGWCR5_EL1() MRSL(DBGWCR5_EL1) +#define RSYSL_DBGWCR6_EL1() MRSL(DBGWCR6_EL1) +#define RSYSL_DBGWCR7_EL1() MRSL(DBGWCR7_EL1) +#define RSYSL_DBGWCR8_EL1() MRSL(DBGWCR8_EL1) +#define RSYSL_DBGWCR9_EL1() MRSL(DBGWCR9_EL1) +#define RSYSL_DBGWCR10_EL1() MRSL(DBGWCR10_EL1) +#define RSYSL_DBGWCR11_EL1() MRSL(DBGWCR11_EL1) +#define RSYSL_DBGWCR12_EL1() MRSL(DBGWCR12_EL1) +#define RSYSL_DBGWCR13_EL1() MRSL(DBGWCR13_EL1) +#define RSYSL_DBGWCR14_EL1() MRSL(DBGWCR14_EL1) +#define RSYSL_DBGWCR15_EL1() MRSL(DBGWCR15_EL1) +#define RSYSL_DBGCLAIMSET_EL1() MRSL(DBGCLAIMSET_EL1) +#define RSYSL_DBGCLAIMCLR_EL1() MRSL(DBGCLAIMCLR_EL1) +#define RSYSL_DBGAUTHSTATUS_EL1() MRSL(DBGAUTHSTATUS_EL1) +#define RSYSL_DBGVCR32_EL2() MRSL(DBGVCR32_EL2) +#define RSYSL_MDCR_EL2() MRSL(MDCR_EL2) +#define RSYSL_MDCR_EL3() MRSL(MDCR_EL3) +/* 64 bit registers */ +#define RSYSQ_DBGDTR_EL0() MRSQ(DBGDTR_EL0) +#define RSYSQ_MDRAR_EL1() MRSQ(MDRAR_EL1) +#define RSYSQ_DBGBVR0_EL1() MRSQ(DBGBVR0_EL1) +#define RSYSQ_DBGBVR1_EL1() MRSQ(DBGBVR1_EL1) +#define RSYSQ_DBGBVR2_EL1() MRSQ(DBGBVR2_EL1) +#define RSYSQ_DBGBVR3_EL1() MRSQ(DBGBVR3_EL1) +#define RSYSQ_DBGBVR4_EL1() MRSQ(DBGBVR4_EL1) +#define RSYSQ_DBGBVR5_EL1() MRSQ(DBGBVR5_EL1) +#define RSYSQ_DBGBVR6_EL1() MRSQ(DBGBVR6_EL1) +#define RSYSQ_DBGBVR7_EL1() MRSQ(DBGBVR7_EL1) +#define RSYSQ_DBGBVR8_EL1() MRSQ(DBGBVR8_EL1) +#define RSYSQ_DBGBVR9_EL1() MRSQ(DBGBVR9_EL1) +#define RSYSQ_DBGBVR10_EL1() MRSQ(DBGBVR10_EL1) +#define RSYSQ_DBGBVR11_EL1() MRSQ(DBGBVR11_EL1) +#define RSYSQ_DBGBVR12_EL1() MRSQ(DBGBVR12_EL1) +#define RSYSQ_DBGBVR13_EL1() MRSQ(DBGBVR13_EL1) +#define RSYSQ_DBGBVR14_EL1() MRSQ(DBGBVR14_EL1) +#define RSYSQ_DBGBVR15_EL1() MRSQ(DBGBVR15_EL1) +#define RSYSQ_DBGWVR0_EL1() MRSQ(DBGWVR0_EL1) +#define RSYSQ_DBGWVR1_EL1() MRSQ(DBGWVR1_EL1) +#define RSYSQ_DBGWVR2_EL1() MRSQ(DBGWVR2_EL1) +#define RSYSQ_DBGWVR3_EL1() MRSQ(DBGWVR3_EL1) +#define RSYSQ_DBGWVR4_EL1() MRSQ(DBGWVR4_EL1) +#define RSYSQ_DBGWVR5_EL1() MRSQ(DBGWVR5_EL1) +#define RSYSQ_DBGWVR6_EL1() MRSQ(DBGWVR6_EL1) +#define RSYSQ_DBGWVR7_EL1() MRSQ(DBGWVR7_EL1) +#define RSYSQ_DBGWVR8_EL1() MRSQ(DBGWVR8_EL1) +#define RSYSQ_DBGWVR9_EL1() MRSQ(DBGWVR9_EL1) +#define RSYSQ_DBGWVR10_EL1() MRSQ(DBGWVR10_EL1) +#define RSYSQ_DBGWVR11_EL1() MRSQ(DBGWVR11_EL1) +#define RSYSQ_DBGWVR12_EL1() MRSQ(DBGWVR12_EL1) +#define RSYSQ_DBGWVR13_EL1() MRSQ(DBGWVR13_EL1) +#define RSYSQ_DBGWVR14_EL1() MRSQ(DBGWVR14_EL1) +#define RSYSQ_DBGWVR15_EL1() MRSQ(DBGWVR15_EL1) + +/* 32 bit registers */ +#define WSYS_DBGDTRTX_EL0(val) MSR(val, DBGDTRTX_EL0) +#define WSYS_MDCCINT_EL1(val) MSR(val, MDCCINT_EL1) +#define WSYS_MDSCR_EL1(val) MSR(val, MDSCR_EL1) +#define WSYS_OSDTRRX_EL1(val) MSR(val, OSDTRRX_EL1) +#define WSYS_OSDTRTX_EL1(val) MSR(val, OSDTRTX_EL1) +#define WSYS_OSDLR_EL1(val) MSR(val, OSDLR_EL1) +#define WSYS_OSECCR_EL1(val) MSR(val, OSECCR_EL1) +#define WSYS_DBGPRCR_EL1(val) MSR(val, DBGPRCR_EL1) +#define WSYS_DBGBCR0_EL1(val) MSR(val, DBGBCR0_EL1) +#define WSYS_DBGBCR1_EL1(val) MSR(val, DBGBCR1_EL1) +#define WSYS_DBGBCR2_EL1(val) MSR(val, DBGBCR2_EL1) +#define WSYS_DBGBCR3_EL1(val) MSR(val, DBGBCR3_EL1) +#define WSYS_DBGBCR4_EL1(val) MSR(val, DBGBCR4_EL1) +#define WSYS_DBGBCR5_EL1(val) MSR(val, DBGBCR5_EL1) +#define WSYS_DBGBCR6_EL1(val) MSR(val, DBGBCR6_EL1) +#define WSYS_DBGBCR7_EL1(val) MSR(val, DBGBCR7_EL1) +#define WSYS_DBGBCR8_EL1(val) MSR(val, DBGBCR8_EL1) +#define WSYS_DBGBCR9_EL1(val) MSR(val, DBGBCR9_EL1) +#define WSYS_DBGBCR10_EL1(val) MSR(val, DBGBCR10_EL1) +#define WSYS_DBGBCR11_EL1(val) MSR(val, DBGBCR11_EL1) +#define WSYS_DBGBCR12_EL1(val) MSR(val, DBGBCR12_EL1) +#define WSYS_DBGBCR13_EL1(val) MSR(val, DBGBCR13_EL1) +#define WSYS_DBGBCR14_EL1(val) MSR(val, DBGBCR14_EL1) +#define WSYS_DBGBCR15_EL1(val) MSR(val, DBGBCR15_EL1) +#define WSYS_DBGWCR0_EL1(val) MSR(val, DBGWCR0_EL1) +#define WSYS_DBGWCR1_EL1(val) MSR(val, DBGWCR1_EL1) +#define WSYS_DBGWCR2_EL1(val) MSR(val, DBGWCR2_EL1) +#define WSYS_DBGWCR3_EL1(val) MSR(val, DBGWCR3_EL1) +#define WSYS_DBGWCR4_EL1(val) MSR(val, DBGWCR4_EL1) +#define WSYS_DBGWCR5_EL1(val) MSR(val, DBGWCR5_EL1) +#define WSYS_DBGWCR6_EL1(val) MSR(val, DBGWCR6_EL1) +#define WSYS_DBGWCR7_EL1(val) MSR(val, DBGWCR7_EL1) +#define WSYS_DBGWCR8_EL1(val) MSR(val, DBGWCR8_EL1) +#define WSYS_DBGWCR9_EL1(val) MSR(val, DBGWCR9_EL1) +#define WSYS_DBGWCR10_EL1(val) MSR(val, DBGWCR10_EL1) +#define WSYS_DBGWCR11_EL1(val) MSR(val, DBGWCR11_EL1) +#define WSYS_DBGWCR12_EL1(val) MSR(val, DBGWCR12_EL1) +#define WSYS_DBGWCR13_EL1(val) MSR(val, DBGWCR13_EL1) +#define WSYS_DBGWCR14_EL1(val) MSR(val, DBGWCR14_EL1) +#define WSYS_DBGWCR15_EL1(val) MSR(val, DBGWCR15_EL1) +#define WSYS_DBGCLAIMSET_EL1(val) MSR(val, DBGCLAIMSET_EL1) +#define WSYS_DBGCLAIMCLR_EL1(val) MSR(val, DBGCLAIMCLR_EL1) +#define WSYS_OSLAR_EL1(val) MSR(val, OSLAR_EL1) +#define WSYS_DBGVCR32_EL2(val) MSR(val, DBGVCR32_EL2) +#define WSYS_MDCR_EL2(val) MSR(val, MDCR_EL2) +#define WSYS_MDCR_EL3(val) MSR(val, MDCR_EL3) +/* 64 bit registers */ +#define WSYS_DBGDTR_EL0(val) MSR(val, DBGDTR_EL0) +#define WSYS_DBGBVR0_EL1(val) MSR(val, DBGBVR0_EL1) +#define WSYS_DBGBVR1_EL1(val) MSR(val, DBGBVR1_EL1) +#define WSYS_DBGBVR2_EL1(val) MSR(val, DBGBVR2_EL1) +#define WSYS_DBGBVR3_EL1(val) MSR(val, DBGBVR3_EL1) +#define WSYS_DBGBVR4_EL1(val) MSR(val, DBGBVR4_EL1) +#define WSYS_DBGBVR5_EL1(val) MSR(val, DBGBVR5_EL1) +#define WSYS_DBGBVR6_EL1(val) MSR(val, DBGBVR6_EL1) +#define WSYS_DBGBVR7_EL1(val) MSR(val, DBGBVR7_EL1) +#define WSYS_DBGBVR8_EL1(val) MSR(val, DBGBVR8_EL1) +#define WSYS_DBGBVR9_EL1(val) MSR(val, DBGBVR9_EL1) +#define WSYS_DBGBVR10_EL1(val) MSR(val, DBGBVR10_EL1) +#define WSYS_DBGBVR11_EL1(val) MSR(val, DBGBVR11_EL1) +#define WSYS_DBGBVR12_EL1(val) MSR(val, DBGBVR12_EL1) +#define WSYS_DBGBVR13_EL1(val) MSR(val, DBGBVR13_EL1) +#define WSYS_DBGBVR14_EL1(val) MSR(val, DBGBVR14_EL1) +#define WSYS_DBGBVR15_EL1(val) MSR(val, DBGBVR15_EL1) +#define WSYS_DBGWVR0_EL1(val) MSR(val, DBGWVR0_EL1) +#define WSYS_DBGWVR1_EL1(val) MSR(val, DBGWVR1_EL1) +#define WSYS_DBGWVR2_EL1(val) MSR(val, DBGWVR2_EL1) +#define WSYS_DBGWVR3_EL1(val) MSR(val, DBGWVR3_EL1) +#define WSYS_DBGWVR4_EL1(val) MSR(val, DBGWVR4_EL1) +#define WSYS_DBGWVR5_EL1(val) MSR(val, DBGWVR5_EL1) +#define WSYS_DBGWVR6_EL1(val) MSR(val, DBGWVR6_EL1) +#define WSYS_DBGWVR7_EL1(val) MSR(val, DBGWVR7_EL1) +#define WSYS_DBGWVR8_EL1(val) MSR(val, DBGWVR8_EL1) +#define WSYS_DBGWVR9_EL1(val) MSR(val, DBGWVR9_EL1) +#define WSYS_DBGWVR10_EL1(val) MSR(val, DBGWVR10_EL1) +#define WSYS_DBGWVR11_EL1(val) MSR(val, DBGWVR11_EL1) +#define WSYS_DBGWVR12_EL1(val) MSR(val, DBGWVR12_EL1) +#define WSYS_DBGWVR13_EL1(val) MSR(val, DBGWVR13_EL1) +#define WSYS_DBGWVR14_EL1(val) MSR(val, DBGWVR14_EL1) +#define WSYS_DBGWVR15_EL1(val) MSR(val, DBGWVR15_EL1) + +#endif --- /dev/null 2019-10-24 16:47:25.704025805 +0200 +++ linux-4.4.115-fbx/arch/arm64/include/asm/dma-contiguous.h 2019-01-22 16:16:21.539228621 +0100 @@ -0,0 +1,24 @@ +/* + * Copyright (c) 2013,2016-2017, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _ASM_DMA_CONTIGUOUS_H +#define _ASM_DMA_CONTIGUOUS_H + +#ifdef __KERNEL__ + +#include + +void dma_contiguous_early_fixup(phys_addr_t base, unsigned long size); + +#endif +#endif --- /dev/null 2019-10-24 16:47:25.704025805 +0200 +++ linux-4.4.115-fbx/arch/arm64/include/asm/dma-iommu.h 2019-01-22 16:16:21.539228621 +0100 @@ -0,0 +1,64 @@ +#ifndef ASMARM_DMA_IOMMU_H +#define ASMARM_DMA_IOMMU_H + +#ifdef __KERNEL__ + +#include +#include +#include +#include +#include +#include + +struct dma_iommu_mapping { + /* iommu specific data */ + struct iommu_domain *domain; + + void *bitmap; + size_t bits; + dma_addr_t base; + + spinlock_t lock; + struct kref kref; +#ifdef CONFIG_IOMMU_IO_PGTABLE_FAST + struct dma_fast_smmu_mapping *fast; +#endif +}; + +#ifdef CONFIG_ARM64_DMA_USE_IOMMU + +struct dma_iommu_mapping * +arm_iommu_create_mapping(struct bus_type *bus, dma_addr_t base, size_t size); + +void arm_iommu_release_mapping(struct dma_iommu_mapping *mapping); + +int arm_iommu_attach_device(struct device *dev, + struct dma_iommu_mapping *mapping); +void arm_iommu_detach_device(struct device *dev); + +#else /* !CONFIG_ARM64_DMA_USE_IOMMU */ + +static inline struct dma_iommu_mapping * +arm_iommu_create_mapping(struct bus_type *bus, dma_addr_t base, size_t size) +{ + return ERR_PTR(-ENOMEM); +} + +static inline void arm_iommu_release_mapping(struct dma_iommu_mapping *mapping) +{ +} + +static inline int arm_iommu_attach_device(struct device *dev, + struct dma_iommu_mapping *mapping) +{ + return -ENODEV; +} + +static inline void arm_iommu_detach_device(struct device *dev) +{ +} + +#endif /* CONFIG_ARM64_DMA_USE_IOMMU */ + +#endif /* __KERNEL__ */ +#endif --- /dev/null 2019-10-24 16:47:25.704025805 +0200 +++ linux-4.4.115-fbx/arch/arm64/include/asm/edac.h 2019-01-22 16:16:21.539228621 +0100 @@ -0,0 +1,28 @@ +/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef ASM_EDAC_H +#define ASM_EDAC_H + +#if defined(CONFIG_EDAC_CORTEX_ARM64) && \ + !defined(CONFIG_EDAC_CORTEX_ARM64_DBE_IRQ_ONLY) +void arm64_check_cache_ecc(void *info); +#else +static inline void arm64_check_cache_ecc(void *info) { } +#endif + +static inline void atomic_scrub(void *addr, int size) +{ + return; +} + +#endif --- /dev/null 2019-10-24 16:47:25.704025805 +0200 +++ linux-4.4.115-fbx/arch/arm64/include/asm/etmv4x.h 2019-01-22 16:16:21.539228621 +0100 @@ -0,0 +1,385 @@ +/* Copyright (c) 2015-2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __ASM_ETMV4X_H +#define __ASM_ETMV4X_H + +#include + +/* 32 bit register reads for AArch64 */ +#define trc_readl(reg) RSYSL_##reg() +/* 64 bit register reads for AArch64 */ +#define trc_readq(reg) RSYSQ_##reg() +/* 32 and 64 bit register writes for AArch64 */ +#define trc_write(val, reg) WSYS_##reg(val) + +#define MRSL(op0, op1, crn, crm, op2) \ +({ \ +uint32_t val; \ +asm volatile("mrs %0, S"#op0"_"#op1"_"#crn"_"#crm"_"#op2 : "=r" (val)); \ +val; \ +}) + +#define MRSQ(op0, op1, crn, crm, op2) \ +({ \ +uint64_t val; \ +asm volatile("mrs %0, S"#op0"_"#op1"_"#crn"_"#crm"_"#op2 : "=r" (val)); \ +val; \ +}) + +#define MSR(val, op0, op1, crn, crm, op2) \ +({ \ +asm volatile("msr S"#op0"_"#op1"_"#crn"_"#crm"_"#op2", %0" : : "r" (val)); \ +}) + +/* Clock and Power Management Register */ +#define RSYSL_CPMR_EL1() MRSL(3, 7, c15, c0, 5) +#define WSYS_CPMR_EL1(val) MSR(val, 3, 7, c15, c0, 5) + +/* + * ETMv4 Registers + * + * Read only + * ETMAUTHSTATUS, ETMDEVARCH, ETMDEVID, ETMIDRn[0-13], ETMOSLSR, ETMSTATR + * + * Write only + * ETMOSLAR + */ +/* 32 bit registers */ +#define RSYSL_ETMAUTHSTATUS() MRSL(2, 1, c7, c14, 6) +#define RSYSL_ETMAUXCTLR() MRSL(2, 1, c0, c6, 0) +#define RSYSL_ETMCCCTLR() MRSL(2, 1, c0, c14, 0) +#define RSYSL_ETMCIDCCTLR0() MRSL(2, 1, c3, c0, 2) +#define RSYSL_ETMCNTCTLR0() MRSL(2, 1, c0, c4, 5) +#define RSYSL_ETMCNTCTLR1() MRSL(2, 1, c0, c5, 5) +#define RSYSL_ETMCNTCTLR2() MRSL(2, 1, c0, c6, 5) +#define RSYSL_ETMCNTCTLR3() MRSL(2, 1, c0, c7, 5) +#define RSYSL_ETMCNTRLDVR0() MRSL(2, 1, c0, c0, 5) +#define RSYSL_ETMCNTRLDVR1() MRSL(2, 1, c0, c1, 5) +#define RSYSL_ETMCNTRLDVR2() MRSL(2, 1, c0, c2, 5) +#define RSYSL_ETMCNTRLDVR3() MRSL(2, 1, c0, c3, 5) +#define RSYSL_ETMCNTVR0() MRSL(2, 1, c0, c8, 5) +#define RSYSL_ETMCNTVR1() MRSL(2, 1, c0, c9, 5) +#define RSYSL_ETMCNTVR2() MRSL(2, 1, c0, c10, 5) +#define RSYSL_ETMCNTVR3() MRSL(2, 1, c0, c11, 5) +#define RSYSL_ETMCONFIGR() MRSL(2, 1, c0, c4, 0) +#define RSYSL_ETMDEVARCH() MRSL(2, 1, c7, c15, 6) +#define RSYSL_ETMDEVID() MRSL(2, 1, c7, c2, 7) +#define RSYSL_ETMEVENTCTL0R() MRSL(2, 1, c0, c8, 0) +#define RSYSL_ETMEVENTCTL1R() MRSL(2, 1, c0, c9, 0) +#define RSYSL_ETMEXTINSELR() MRSL(2, 1, c0, c8, 4) +#define RSYSL_ETMIDR0() MRSL(2, 1, c0, c8, 7) +#define RSYSL_ETMIDR1() MRSL(2, 1, c0, c9, 7) +#define RSYSL_ETMIDR10() MRSL(2, 1, c0, c2, 6) +#define RSYSL_ETMIDR11() MRSL(2, 1, c0, c3, 6) +#define RSYSL_ETMIDR12() MRSL(2, 1, c0, c4, 6) +#define RSYSL_ETMIDR13() MRSL(2, 1, c0, c5, 6) +#define RSYSL_ETMIDR2() MRSL(2, 1, c0, c10, 7) +#define RSYSL_ETMIDR3() MRSL(2, 1, c0, c11, 7) +#define RSYSL_ETMIDR4() MRSL(2, 1, c0, c12, 7) +#define RSYSL_ETMIDR5() MRSL(2, 1, c0, c13, 7) +#define RSYSL_ETMIDR6() MRSL(2, 1, c0, c14, 7) +#define RSYSL_ETMIDR7() MRSL(2, 1, c0, c15, 7) +#define RSYSL_ETMIDR8() MRSL(2, 1, c0, c0, 6) +#define RSYSL_ETMIDR9() MRSL(2, 1, c0, c1, 6) +#define RSYSL_ETMIMSPEC0() MRSL(2, 1, c0, c0, 7) +#define RSYSL_ETMOSLSR() MRSL(2, 1, c1, c1, 4) +#define RSYSL_ETMPRGCTLR() MRSL(2, 1, c0, c1, 0) +#define RSYSL_ETMRSCTLR10() MRSL(2, 1, c1, c10, 0) +#define RSYSL_ETMRSCTLR11() MRSL(2, 1, c1, c11, 0) +#define RSYSL_ETMRSCTLR12() MRSL(2, 1, c1, c12, 0) +#define RSYSL_ETMRSCTLR13() MRSL(2, 1, c1, c13, 0) +#define RSYSL_ETMRSCTLR14() MRSL(2, 1, c1, c14, 0) +#define RSYSL_ETMRSCTLR15() MRSL(2, 1, c1, c15, 0) +#define RSYSL_ETMRSCTLR2() MRSL(2, 1, c1, c2, 0) +#define RSYSL_ETMRSCTLR3() MRSL(2, 1, c1, c3, 0) +#define RSYSL_ETMRSCTLR4() MRSL(2, 1, c1, c4, 0) +#define RSYSL_ETMRSCTLR5() MRSL(2, 1, c1, c5, 0) +#define RSYSL_ETMRSCTLR6() MRSL(2, 1, c1, c6, 0) +#define RSYSL_ETMRSCTLR7() MRSL(2, 1, c1, c7, 0) +#define RSYSL_ETMRSCTLR8() MRSL(2, 1, c1, c8, 0) +#define RSYSL_ETMRSCTLR9() MRSL(2, 1, c1, c9, 0) +#define RSYSL_ETMRSCTLR16() MRSL(2, 1, c1, c0, 1) +#define RSYSL_ETMRSCTLR17() MRSL(2, 1, c1, c1, 1) +#define RSYSL_ETMRSCTLR18() MRSL(2, 1, c1, c2, 1) +#define RSYSL_ETMRSCTLR19() MRSL(2, 1, c1, c3, 1) +#define RSYSL_ETMRSCTLR20() MRSL(2, 1, c1, c4, 1) +#define RSYSL_ETMRSCTLR21() MRSL(2, 1, c1, c5, 1) +#define RSYSL_ETMRSCTLR22() MRSL(2, 1, c1, c6, 1) +#define RSYSL_ETMRSCTLR23() MRSL(2, 1, c1, c7, 1) +#define RSYSL_ETMRSCTLR24() MRSL(2, 1, c1, c8, 1) +#define RSYSL_ETMRSCTLR25() MRSL(2, 1, c1, c9, 1) +#define RSYSL_ETMRSCTLR26() MRSL(2, 1, c1, c10, 1) +#define RSYSL_ETMRSCTLR27() MRSL(2, 1, c1, c11, 1) +#define RSYSL_ETMRSCTLR28() MRSL(2, 1, c1, c12, 1) +#define RSYSL_ETMRSCTLR29() MRSL(2, 1, c1, c13, 1) +#define RSYSL_ETMRSCTLR30() MRSL(2, 1, c1, c14, 1) +#define RSYSL_ETMRSCTLR31() MRSL(2, 1, c1, c15, 1) +#define RSYSL_ETMSEQEVR0() MRSL(2, 1, c0, c0, 4) +#define RSYSL_ETMSEQEVR1() MRSL(2, 1, c0, c1, 4) +#define RSYSL_ETMSEQEVR2() MRSL(2, 1, c0, c2, 4) +#define RSYSL_ETMSEQRSTEVR() MRSL(2, 1, c0, c6, 4) +#define RSYSL_ETMSEQSTR() MRSL(2, 1, c0, c7, 4) +#define RSYSL_ETMSTALLCTLR() MRSL(2, 1, c0, c11, 0) +#define RSYSL_ETMSTATR() MRSL(2, 1, c0, c3, 0) +#define RSYSL_ETMSYNCPR() MRSL(2, 1, c0, c13, 0) +#define RSYSL_ETMTRACEIDR() MRSL(2, 1, c0, c0, 1) +#define RSYSL_ETMTSCTLR() MRSL(2, 1, c0, c12, 0) +#define RSYSL_ETMVICTLR() MRSL(2, 1, c0, c0, 2) +#define RSYSL_ETMVIIECTLR() MRSL(2, 1, c0, c1, 2) +#define RSYSL_ETMVISSCTLR() MRSL(2, 1, c0, c2, 2) +#define RSYSL_ETMSSCCR0() MRSL(2, 1, c1, c0, 2) +#define RSYSL_ETMSSCCR1() MRSL(2, 1, c1, c1, 2) +#define RSYSL_ETMSSCCR2() MRSL(2, 1, c1, c2, 2) +#define RSYSL_ETMSSCCR3() MRSL(2, 1, c1, c3, 2) +#define RSYSL_ETMSSCCR4() MRSL(2, 1, c1, c4, 2) +#define RSYSL_ETMSSCCR5() MRSL(2, 1, c1, c5, 2) +#define RSYSL_ETMSSCCR6() MRSL(2, 1, c1, c6, 2) +#define RSYSL_ETMSSCCR7() MRSL(2, 1, c1, c7, 2) +#define RSYSL_ETMSSCSR0() MRSL(2, 1, c1, c8, 2) +#define RSYSL_ETMSSCSR1() MRSL(2, 1, c1, c9, 2) +#define RSYSL_ETMSSCSR2() MRSL(2, 1, c1, c10, 2) +#define RSYSL_ETMSSCSR3() MRSL(2, 1, c1, c11, 2) +#define RSYSL_ETMSSCSR4() MRSL(2, 1, c1, c12, 2) +#define RSYSL_ETMSSCSR5() MRSL(2, 1, c1, c13, 2) +#define RSYSL_ETMSSCSR6() MRSL(2, 1, c1, c14, 2) +#define RSYSL_ETMSSCSR7() MRSL(2, 1, c1, c15, 2) +#define RSYSL_ETMSSPCICR0() MRSL(2, 1, c1, c0, 3) +#define RSYSL_ETMSSPCICR1() MRSL(2, 1, c1, c1, 3) +#define RSYSL_ETMSSPCICR2() MRSL(2, 1, c1, c2, 3) +#define RSYSL_ETMSSPCICR3() MRSL(2, 1, c1, c3, 3) +#define RSYSL_ETMSSPCICR4() MRSL(2, 1, c1, c4, 3) +#define RSYSL_ETMSSPCICR5() MRSL(2, 1, c1, c5, 3) +#define RSYSL_ETMSSPCICR6() MRSL(2, 1, c1, c6, 3) +#define RSYSL_ETMSSPCICR7() MRSL(2, 1, c1, c7, 3) + +/* 64 bit registers */ +#define RSYSQ_ETMACATR0() MRSQ(2, 1, c2, c0, 2) +#define RSYSQ_ETMACATR1() MRSQ(2, 1, c2, c2, 2) +#define RSYSQ_ETMACATR2() MRSQ(2, 1, c2, c4, 2) +#define RSYSQ_ETMACATR3() MRSQ(2, 1, c2, c6, 2) +#define RSYSQ_ETMACATR4() MRSQ(2, 1, c2, c8, 2) +#define RSYSQ_ETMACATR5() MRSQ(2, 1, c2, c10, 2) +#define RSYSQ_ETMACATR6() MRSQ(2, 1, c2, c12, 2) +#define RSYSQ_ETMACATR7() MRSQ(2, 1, c2, c14, 2) +#define RSYSQ_ETMACATR8() MRSQ(2, 1, c2, c0, 3) +#define RSYSQ_ETMACATR9() MRSQ(2, 1, c2, c2, 3) +#define RSYSQ_ETMACATR10() MRSQ(2, 1, c2, c4, 3) +#define RSYSQ_ETMACATR11() MRSQ(2, 1, c2, c6, 3) +#define RSYSQ_ETMACATR12() MRSQ(2, 1, c2, c8, 3) +#define RSYSQ_ETMACATR13() MRSQ(2, 1, c2, c10, 3) +#define RSYSQ_ETMACATR14() MRSQ(2, 1, c2, c12, 3) +#define RSYSQ_ETMACATR15() MRSQ(2, 1, c2, c14, 3) +#define RSYSQ_ETMCIDCVR0() MRSQ(2, 1, c3, c0, 0) +#define RSYSQ_ETMCIDCVR1() MRSQ(2, 1, c3, c2, 0) +#define RSYSQ_ETMCIDCVR2() MRSQ(2, 1, c3, c4, 0) +#define RSYSQ_ETMCIDCVR3() MRSQ(2, 1, c3, c6, 0) +#define RSYSQ_ETMCIDCVR4() MRSQ(2, 1, c3, c8, 0) +#define RSYSQ_ETMCIDCVR5() MRSQ(2, 1, c3, c10, 0) +#define RSYSQ_ETMCIDCVR6() MRSQ(2, 1, c3, c12, 0) +#define RSYSQ_ETMCIDCVR7() MRSQ(2, 1, c3, c14, 0) +#define RSYSQ_ETMACVR0() MRSQ(2, 1, c2, c0, 0) +#define RSYSQ_ETMACVR1() MRSQ(2, 1, c2, c2, 0) +#define RSYSQ_ETMACVR2() MRSQ(2, 1, c2, c4, 0) +#define RSYSQ_ETMACVR3() MRSQ(2, 1, c2, c6, 0) +#define RSYSQ_ETMACVR4() MRSQ(2, 1, c2, c8, 0) +#define RSYSQ_ETMACVR5() MRSQ(2, 1, c2, c10, 0) +#define RSYSQ_ETMACVR6() MRSQ(2, 1, c2, c12, 0) +#define RSYSQ_ETMACVR7() MRSQ(2, 1, c2, c14, 0) +#define RSYSQ_ETMACVR8() MRSQ(2, 1, c2, c0, 1) +#define RSYSQ_ETMACVR9() MRSQ(2, 1, c2, c2, 1) +#define RSYSQ_ETMACVR10() MRSQ(2, 1, c2, c4, 1) +#define RSYSQ_ETMACVR11() MRSQ(2, 1, c2, c6, 1) +#define RSYSQ_ETMACVR12() MRSQ(2, 1, c2, c8, 1) +#define RSYSQ_ETMACVR13() MRSQ(2, 1, c2, c10, 1) +#define RSYSQ_ETMACVR14() MRSQ(2, 1, c2, c12, 1) +#define RSYSQ_ETMACVR15() MRSQ(2, 1, c2, c14, 1) +#define RSYSQ_ETMVMIDCVR0() MRSQ(2, 1, c3, c0, 1) +#define RSYSQ_ETMVMIDCVR1() MRSQ(2, 1, c3, c2, 1) +#define RSYSQ_ETMVMIDCVR2() MRSQ(2, 1, c3, c4, 1) +#define RSYSQ_ETMVMIDCVR3() MRSQ(2, 1, c3, c6, 1) +#define RSYSQ_ETMVMIDCVR4() MRSQ(2, 1, c3, c8, 1) +#define RSYSQ_ETMVMIDCVR5() MRSQ(2, 1, c3, c10, 1) +#define RSYSQ_ETMVMIDCVR6() MRSQ(2, 1, c3, c12, 1) +#define RSYSQ_ETMVMIDCVR7() MRSQ(2, 1, c3, c14, 1) +#define RSYSQ_ETMDVCVR0() MRSQ(2, 1, c2, c0, 4) +#define RSYSQ_ETMDVCVR1() MRSQ(2, 1, c2, c4, 4) +#define RSYSQ_ETMDVCVR2() MRSQ(2, 1, c2, c8, 4) +#define RSYSQ_ETMDVCVR3() MRSQ(2, 1, c2, c12, 4) +#define RSYSQ_ETMDVCVR4() MRSQ(2, 1, c2, c0, 5) +#define RSYSQ_ETMDVCVR5() MRSQ(2, 1, c2, c4, 5) +#define RSYSQ_ETMDVCVR6() MRSQ(2, 1, c2, c8, 5) +#define RSYSQ_ETMDVCVR7() MRSQ(2, 1, c2, c12, 5) +#define RSYSQ_ETMDVCMR0() MRSQ(2, 1, c2, c0, 6) +#define RSYSQ_ETMDVCMR1() MRSQ(2, 1, c2, c4, 6) +#define RSYSQ_ETMDVCMR2() MRSQ(2, 1, c2, c8, 6) +#define RSYSQ_ETMDVCMR3() MRSQ(2, 1, c2, c12, 6) +#define RSYSQ_ETMDVCMR4() MRSQ(2, 1, c2, c0, 7) +#define RSYSQ_ETMDVCMR5() MRSQ(2, 1, c2, c4, 7) +#define RSYSQ_ETMDVCMR6() MRSQ(2, 1, c2, c8, 7) +#define RSYSQ_ETMDVCMR7() MRSQ(2, 1, c2, c12, 7) + +/* 32 and 64 bit registers */ +#define WSYS_ETMAUXCTLR(val) MSR(val, 2, 1, c0, c6, 0) +#define WSYS_ETMACATR0(val) MSR(val, 2, 1, c2, c0, 2) +#define WSYS_ETMACATR1(val) MSR(val, 2, 1, c2, c2, 2) +#define WSYS_ETMACATR2(val) MSR(val, 2, 1, c2, c4, 2) +#define WSYS_ETMACATR3(val) MSR(val, 2, 1, c2, c6, 2) +#define WSYS_ETMACATR4(val) MSR(val, 2, 1, c2, c8, 2) +#define WSYS_ETMACATR5(val) MSR(val, 2, 1, c2, c10, 2) +#define WSYS_ETMACATR6(val) MSR(val, 2, 1, c2, c12, 2) +#define WSYS_ETMACATR7(val) MSR(val, 2, 1, c2, c14, 2) +#define WSYS_ETMACATR8(val) MSR(val, 2, 1, c2, c0, 3) +#define WSYS_ETMACATR9(val) MSR(val, 2, 1, c2, c2, 3) +#define WSYS_ETMACATR10(val) MSR(val, 2, 1, c2, c4, 3) +#define WSYS_ETMACATR11(val) MSR(val, 2, 1, c2, c6, 3) +#define WSYS_ETMACATR12(val) MSR(val, 2, 1, c2, c8, 3) +#define WSYS_ETMACATR13(val) MSR(val, 2, 1, c2, c10, 3) +#define WSYS_ETMACATR14(val) MSR(val, 2, 1, c2, c12, 3) +#define WSYS_ETMACATR15(val) MSR(val, 2, 1, c2, c14, 3) +#define WSYS_ETMACVR0(val) MSR(val, 2, 1, c2, c0, 0) +#define WSYS_ETMACVR1(val) MSR(val, 2, 1, c2, c2, 0) +#define WSYS_ETMACVR2(val) MSR(val, 2, 1, c2, c4, 0) +#define WSYS_ETMACVR3(val) MSR(val, 2, 1, c2, c6, 0) +#define WSYS_ETMACVR4(val) MSR(val, 2, 1, c2, c8, 0) +#define WSYS_ETMACVR5(val) MSR(val, 2, 1, c2, c10, 0) +#define WSYS_ETMACVR6(val) MSR(val, 2, 1, c2, c12, 0) +#define WSYS_ETMACVR7(val) MSR(val, 2, 1, c2, c14, 0) +#define WSYS_ETMACVR8(val) MSR(val, 2, 1, c2, c0, 1) +#define WSYS_ETMACVR9(val) MSR(val, 2, 1, c2, c2, 1) +#define WSYS_ETMACVR10(val) MSR(val, 2, 1, c2, c4, 1) +#define WSYS_ETMACVR11(val) MSR(val, 2, 1, c2, c6, 1) +#define WSYS_ETMACVR12(val) MSR(val, 2, 1, c2, c8, 1) +#define WSYS_ETMACVR13(val) MSR(val, 2, 1, c2, c10, 1) +#define WSYS_ETMACVR14(val) MSR(val, 2, 1, c2, c12, 1) +#define WSYS_ETMACVR15(val) MSR(val, 2, 1, c2, c14, 1) +#define WSYS_ETMCCCTLR(val) MSR(val, 2, 1, c0, c14, 0) +#define WSYS_ETMCIDCCTLR0(val) MSR(val, 2, 1, c3, c0, 2) +#define WSYS_ETMCIDCVR0(val) MSR(val, 2, 1, c3, c0, 0) +#define WSYS_ETMCIDCVR1(val) MSR(val, 2, 1, c3, c2, 0) +#define WSYS_ETMCIDCVR2(val) MSR(val, 2, 1, c3, c4, 0) +#define WSYS_ETMCIDCVR3(val) MSR(val, 2, 1, c3, c6, 0) +#define WSYS_ETMCIDCVR4(val) MSR(val, 2, 1, c3, c8, 0) +#define WSYS_ETMCIDCVR5(val) MSR(val, 2, 1, c3, c10, 0) +#define WSYS_ETMCIDCVR6(val) MSR(val, 2, 1, c3, c12, 0) +#define WSYS_ETMCIDCVR7(val) MSR(val, 2, 1, c3, c14, 0) +#define WSYS_ETMCNTCTLR0(val) MSR(val, 2, 1, c0, c4, 5) +#define WSYS_ETMCNTCTLR1(val) MSR(val, 2, 1, c0, c5, 5) +#define WSYS_ETMCNTCTLR2(val) MSR(val, 2, 1, c0, c6, 5) +#define WSYS_ETMCNTCTLR3(val) MSR(val, 2, 1, c0, c7, 5) +#define WSYS_ETMCNTRLDVR0(val) MSR(val, 2, 1, c0, c0, 5) +#define WSYS_ETMCNTRLDVR1(val) MSR(val, 2, 1, c0, c1, 5) +#define WSYS_ETMCNTRLDVR2(val) MSR(val, 2, 1, c0, c2, 5) +#define WSYS_ETMCNTRLDVR3(val) MSR(val, 2, 1, c0, c3, 5) +#define WSYS_ETMCNTVR0(val) MSR(val, 2, 1, c0, c8, 5) +#define WSYS_ETMCNTVR1(val) MSR(val, 2, 1, c0, c9, 5) +#define WSYS_ETMCNTVR2(val) MSR(val, 2, 1, c0, c10, 5) +#define WSYS_ETMCNTVR3(val) MSR(val, 2, 1, c0, c11, 5) +#define WSYS_ETMCONFIGR(val) MSR(val, 2, 1, c0, c4, 0) +#define WSYS_ETMEVENTCTL0R(val) MSR(val, 2, 1, c0, c8, 0) +#define WSYS_ETMEVENTCTL1R(val) MSR(val, 2, 1, c0, c9, 0) +#define WSYS_ETMEXTINSELR(val) MSR(val, 2, 1, c0, c8, 4) +#define WSYS_ETMIMSPEC0(val) MSR(val, 2, 1, c0, c0, 7) +#define WSYS_ETMOSLAR(val) MSR(val, 2, 1, c1, c0, 4) +#define WSYS_ETMPRGCTLR(val) MSR(val, 2, 1, c0, c1, 0) +#define WSYS_ETMRSCTLR10(val) MSR(val, 2, 1, c1, c10, 0) +#define WSYS_ETMRSCTLR11(val) MSR(val, 2, 1, c1, c11, 0) +#define WSYS_ETMRSCTLR12(val) MSR(val, 2, 1, c1, c12, 0) +#define WSYS_ETMRSCTLR13(val) MSR(val, 2, 1, c1, c13, 0) +#define WSYS_ETMRSCTLR14(val) MSR(val, 2, 1, c1, c14, 0) +#define WSYS_ETMRSCTLR15(val) MSR(val, 2, 1, c1, c15, 0) +#define WSYS_ETMRSCTLR2(val) MSR(val, 2, 1, c1, c2, 0) +#define WSYS_ETMRSCTLR3(val) MSR(val, 2, 1, c1, c3, 0) +#define WSYS_ETMRSCTLR4(val) MSR(val, 2, 1, c1, c4, 0) +#define WSYS_ETMRSCTLR5(val) MSR(val, 2, 1, c1, c5, 0) +#define WSYS_ETMRSCTLR6(val) MSR(val, 2, 1, c1, c6, 0) +#define WSYS_ETMRSCTLR7(val) MSR(val, 2, 1, c1, c7, 0) +#define WSYS_ETMRSCTLR8(val) MSR(val, 2, 1, c1, c8, 0) +#define WSYS_ETMRSCTLR9(val) MSR(val, 2, 1, c1, c9, 0) +#define WSYS_ETMRSCTLR16(val) MSR(val, 2, 1, c1, c0, 1) +#define WSYS_ETMRSCTLR17(val) MSR(val, 2, 1, c1, c1, 1) +#define WSYS_ETMRSCTLR18(val) MSR(val, 2, 1, c1, c2, 1) +#define WSYS_ETMRSCTLR19(val) MSR(val, 2, 1, c1, c3, 1) +#define WSYS_ETMRSCTLR20(val) MSR(val, 2, 1, c1, c4, 1) +#define WSYS_ETMRSCTLR21(val) MSR(val, 2, 1, c1, c5, 1) +#define WSYS_ETMRSCTLR22(val) MSR(val, 2, 1, c1, c6, 1) +#define WSYS_ETMRSCTLR23(val) MSR(val, 2, 1, c1, c7, 1) +#define WSYS_ETMRSCTLR24(val) MSR(val, 2, 1, c1, c8, 1) +#define WSYS_ETMRSCTLR25(val) MSR(val, 2, 1, c1, c9, 1) +#define WSYS_ETMRSCTLR26(val) MSR(val, 2, 1, c1, c10, 1) +#define WSYS_ETMRSCTLR27(val) MSR(val, 2, 1, c1, c11, 1) +#define WSYS_ETMRSCTLR28(val) MSR(val, 2, 1, c1, c12, 1) +#define WSYS_ETMRSCTLR29(val) MSR(val, 2, 1, c1, c13, 1) +#define WSYS_ETMRSCTLR30(val) MSR(val, 2, 1, c1, c14, 1) +#define WSYS_ETMRSCTLR31(val) MSR(val, 2, 1, c1, c15, 1) +#define WSYS_ETMSEQEVR0(val) MSR(val, 2, 1, c0, c0, 4) +#define WSYS_ETMSEQEVR1(val) MSR(val, 2, 1, c0, c1, 4) +#define WSYS_ETMSEQEVR2(val) MSR(val, 2, 1, c0, c2, 4) +#define WSYS_ETMSEQRSTEVR(val) MSR(val, 2, 1, c0, c6, 4) +#define WSYS_ETMSEQSTR(val) MSR(val, 2, 1, c0, c7, 4) +#define WSYS_ETMSTALLCTLR(val) MSR(val, 2, 1, c0, c11, 0) +#define WSYS_ETMSYNCPR(val) MSR(val, 2, 1, c0, c13, 0) +#define WSYS_ETMTRACEIDR(val) MSR(val, 2, 1, c0, c0, 1) +#define WSYS_ETMTSCTLR(val) MSR(val, 2, 1, c0, c12, 0) +#define WSYS_ETMVICTLR(val) MSR(val, 2, 1, c0, c0, 2) +#define WSYS_ETMVIIECTLR(val) MSR(val, 2, 1, c0, c1, 2) +#define WSYS_ETMVISSCTLR(val) MSR(val, 2, 1, c0, c2, 2) +#define WSYS_ETMVMIDCVR0(val) MSR(val, 2, 1, c3, c0, 1) +#define WSYS_ETMVMIDCVR1(val) MSR(val, 2, 1, c3, c2, 1) +#define WSYS_ETMVMIDCVR2(val) MSR(val, 2, 1, c3, c4, 1) +#define WSYS_ETMVMIDCVR3(val) MSR(val, 2, 1, c3, c6, 1) +#define WSYS_ETMVMIDCVR4(val) MSR(val, 2, 1, c3, c8, 1) +#define WSYS_ETMVMIDCVR5(val) MSR(val, 2, 1, c3, c10, 1) +#define WSYS_ETMVMIDCVR6(val) MSR(val, 2, 1, c3, c12, 1) +#define WSYS_ETMVMIDCVR7(val) MSR(val, 2, 1, c3, c14, 1) +#define WSYS_ETMDVCVR0(val) MSR(val, 2, 1, c2, c0, 4) +#define WSYS_ETMDVCVR1(val) MSR(val, 2, 1, c2, c4, 4) +#define WSYS_ETMDVCVR2(val) MSR(val, 2, 1, c2, c8, 4) +#define WSYS_ETMDVCVR3(val) MSR(val, 2, 1, c2, c12, 4) +#define WSYS_ETMDVCVR4(val) MSR(val, 2, 1, c2, c0, 5) +#define WSYS_ETMDVCVR5(val) MSR(val, 2, 1, c2, c4, 5) +#define WSYS_ETMDVCVR6(val) MSR(val, 2, 1, c2, c8, 5) +#define WSYS_ETMDVCVR7(val) MSR(val, 2, 1, c2, c12, 5) +#define WSYS_ETMDVCMR0(val) MSR(val, 2, 1, c2, c0, 6) +#define WSYS_ETMDVCMR1(val) MSR(val, 2, 1, c2, c4, 6) +#define WSYS_ETMDVCMR2(val) MSR(val, 2, 1, c2, c8, 6) +#define WSYS_ETMDVCMR3(val) MSR(val, 2, 1, c2, c12, 6) +#define WSYS_ETMDVCMR4(val) MSR(val, 2, 1, c2, c0, 7) +#define WSYS_ETMDVCMR5(val) MSR(val, 2, 1, c2, c4, 7) +#define WSYS_ETMDVCMR6(val) MSR(val, 2, 1, c2, c8, 7) +#define WSYS_ETMDVCMR7(val) MSR(val, 2, 1, c2, c12, 7) +#define WSYS_ETMSSCCR0(val) MSR(val, 2, 1, c1, c0, 2) +#define WSYS_ETMSSCCR1(val) MSR(val, 2, 1, c1, c1, 2) +#define WSYS_ETMSSCCR2(val) MSR(val, 2, 1, c1, c2, 2) +#define WSYS_ETMSSCCR3(val) MSR(val, 2, 1, c1, c3, 2) +#define WSYS_ETMSSCCR4(val) MSR(val, 2, 1, c1, c4, 2) +#define WSYS_ETMSSCCR5(val) MSR(val, 2, 1, c1, c5, 2) +#define WSYS_ETMSSCCR6(val) MSR(val, 2, 1, c1, c6, 2) +#define WSYS_ETMSSCCR7(val) MSR(val, 2, 1, c1, c7, 2) +#define WSYS_ETMSSCSR0(val) MSR(val, 2, 1, c1, c8, 2) +#define WSYS_ETMSSCSR1(val) MSR(val, 2, 1, c1, c9, 2) +#define WSYS_ETMSSCSR2(val) MSR(val, 2, 1, c1, c10, 2) +#define WSYS_ETMSSCSR3(val) MSR(val, 2, 1, c1, c11, 2) +#define WSYS_ETMSSCSR4(val) MSR(val, 2, 1, c1, c12, 2) +#define WSYS_ETMSSCSR5(val) MSR(val, 2, 1, c1, c13, 2) +#define WSYS_ETMSSCSR6(val) MSR(val, 2, 1, c1, c14, 2) +#define WSYS_ETMSSCSR7(val) MSR(val, 2, 1, c1, c15, 2) +#define WSYS_ETMSSPCICR0(val) MSR(val, 2, 1, c1, c0, 3) +#define WSYS_ETMSSPCICR1(val) MSR(val, 2, 1, c1, c1, 3) +#define WSYS_ETMSSPCICR2(val) MSR(val, 2, 1, c1, c2, 3) +#define WSYS_ETMSSPCICR3(val) MSR(val, 2, 1, c1, c3, 3) +#define WSYS_ETMSSPCICR4(val) MSR(val, 2, 1, c1, c4, 3) +#define WSYS_ETMSSPCICR5(val) MSR(val, 2, 1, c1, c5, 3) +#define WSYS_ETMSSPCICR6(val) MSR(val, 2, 1, c1, c6, 3) +#define WSYS_ETMSSPCICR7(val) MSR(val, 2, 1, c1, c7, 3) + +#endif --- /dev/null 2019-10-24 16:47:25.704025805 +0200 +++ linux-4.4.115-fbx/arch/arm64/include/asm/gpio.h 2019-01-22 16:16:21.539228621 +0100 @@ -0,0 +1,32 @@ +#ifndef _ARCH_ARM64_GPIO_H +#define _ARCH_ARM64_GPIO_H + +#if CONFIG_ARCH_NR_GPIO > 0 +#define ARCH_NR_GPIOS CONFIG_ARCH_NR_GPIO +#endif + +/* not all ARM64 platforms necessarily support this API ... */ +#ifdef CONFIG_NEED_MACH_GPIO_H +#include +#endif + +#ifndef __ARM64_GPIOLIB_COMPLEX +/* Note: this may rely upon the value of ARCH_NR_GPIOS set in mach/gpio.h */ +#include + +/* The trivial gpiolib dispatchers */ +#define gpio_get_value __gpio_get_value +#define gpio_set_value __gpio_set_value +#define gpio_cansleep __gpio_cansleep +#endif + +/* + * Provide a default gpio_to_irq() which should satisfy every case. + * However, some platforms want to do this differently, so allow them + * to override it. + */ +#ifndef gpio_to_irq +#define gpio_to_irq __gpio_to_irq +#endif + +#endif /* _ARCH_ARM64_GPIO_H */ --- /dev/null 2019-10-24 16:47:25.704025805 +0200 +++ linux-4.4.115-fbx/arch/arm64/include/asm/stack_pointer.h 2019-01-22 16:16:21.543228657 +0100 @@ -0,0 +1,9 @@ +#ifndef __ASM_STACK_POINTER_H +#define __ASM_STACK_POINTER_H + +/* + * how to get the current stack pointer from C + */ +register unsigned long current_stack_pointer asm ("sp"); + +#endif /* __ASM_STACK_POINTER_H */ --- /dev/null 2019-10-24 16:47:25.704025805 +0200 +++ linux-4.4.115-fbx/arch/arm64/kernel/perf_debug.c 2019-01-22 16:16:21.551228730 +0100 @@ -0,0 +1,73 @@ +/* Copyright (c) 2014-2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include + +/* + * Subsequent patches should add an entry to end of this string. + * Format is incrementing sequence number followed by text of + * patch commit title with newline. + * Note trailing ';' is on its own line to simplify addition of + * future strings. + */ +static char *descriptions = + " 0 arm64: perf: add debug patch logging framework\n" + " 1 Perf: arm64: Add L1 counters to tracepoints\n" + " 5 Perf: arm64: add perf user-mode permissions\n" + " 6 Perf: arm64: Add debugfs node to clear PMU\n" + " 7 Perf: arm64: Update PMU force reset\n" + "10 Perf: arm64: tracectr: initialize counts after hotplug\n" + "11 Perf: arm64: Refine disable/enable in tracecounters\n" + "15 Perf: arm64: make debug dir handle exportable\n" + "16 Perf: arm64: add perf trace user\n" + "17 Perf: arm64: add support for kryo pmu\n" +; + +static ssize_t desc_read(struct file *fp, char __user *buf, + size_t count, loff_t *pos) +{ + return simple_read_from_buffer(buf, count, pos, descriptions, + strlen(descriptions)); +} + +static const struct file_operations perf_debug_desc_fops = { + .read = desc_read, +}; + +static int perf_debugfs_init(void) +{ + int ret = 0; + struct dentry *dir; + struct dentry *file; + + dir = debugfs_create_dir("msm-perf-patches", NULL); + if (IS_ERR_OR_NULL(dir)) { + pr_err("failed to create msm-perf-patches dir in debugfs\n"); + ret = PTR_ERR(dir); + goto init_exit; + } + + file = debugfs_create_file("descriptions", 0444, dir, NULL, + &perf_debug_desc_fops); + if (IS_ERR_OR_NULL(file)) { + debugfs_remove(dir); + pr_err("failed to create descriptions file for msm-perf-patches\n"); + ret = PTR_ERR(file); + goto init_exit; + } + +init_exit: + return ret; +} +late_initcall(perf_debugfs_init); --- /dev/null 2019-10-24 16:47:25.704025805 +0200 +++ linux-4.4.115-fbx/arch/arm64/kernel/perf_trace_counters.c 2019-01-22 16:16:21.551228730 +0100 @@ -0,0 +1,180 @@ +/* Copyright (c) 2013-2014, 2017 The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include +#include +#include +#include +#include +#define CREATE_TRACE_POINTS +#include "perf_trace_counters.h" + +static unsigned int tp_pid_state; + +DEFINE_PER_CPU(u32, cntenset_val); +DEFINE_PER_CPU(u32, previous_ccnt); +DEFINE_PER_CPU(u32[NUM_L1_CTRS], previous_l1_cnts); +DEFINE_PER_CPU(u32, old_pid); +DEFINE_PER_CPU(u32, hotplug_flag); + +static int tracectr_cpu_hotplug_notifier(struct notifier_block *self, + unsigned long action, void *hcpu) +{ + unsigned long cpu = (unsigned long)hcpu; + + if ((action & (~CPU_TASKS_FROZEN)) == CPU_STARTING) + per_cpu(hotplug_flag, cpu) = 1; + + return NOTIFY_OK; +} + +static struct notifier_block tracectr_cpu_hotplug_notifier_block = { + .notifier_call = tracectr_cpu_hotplug_notifier, +}; + +static void setup_prev_cnts(u32 cpu, u32 cnten_val) +{ + int i; + + if (cnten_val & CC) + asm volatile("mrs %0, pmccntr_el0" + : "=r"(per_cpu(previous_ccnt, cpu))); + + for (i = 0; i < NUM_L1_CTRS; i++) { + if (cnten_val & (1 << i)) { + /* Select */ + asm volatile("msr pmselr_el0, %0" : : "r"(i)); + isb(); + /* Read value */ + asm volatile("mrs %0, pmxevcntr_el0" + : "=r"(per_cpu(previous_l1_cnts[i], cpu))); + } + } +} + +void tracectr_notifier(void *ignore, bool preempt, + struct task_struct *prev, struct task_struct *next) +{ + u32 cnten_val; + int current_pid; + u32 cpu = task_cpu(next); + + if (tp_pid_state != 1) + return; + current_pid = next->pid; + if (per_cpu(old_pid, cpu) != -1) { + asm volatile("mrs %0, pmcntenset_el0" : "=r" (cnten_val)); + per_cpu(cntenset_val, cpu) = cnten_val; + /* Disable all the counters that were enabled */ + asm volatile("msr pmcntenclr_el0, %0" : : "r" (cnten_val)); + + if (per_cpu(hotplug_flag, cpu) == 1) { + per_cpu(hotplug_flag, cpu) = 0; + setup_prev_cnts(cpu, cnten_val); + } else { + trace_sched_switch_with_ctrs(per_cpu(old_pid, cpu), + current_pid); + } + + /* Enable all the counters that were disabled */ + asm volatile("msr pmcntenset_el0, %0" : : "r" (cnten_val)); + } + per_cpu(old_pid, cpu) = current_pid; +} + +static void enable_tp_pid(void) +{ + if (tp_pid_state == 0) { + tp_pid_state = 1; + register_trace_sched_switch(tracectr_notifier, NULL); + } +} + +static void disable_tp_pid(void) +{ + if (tp_pid_state == 1) { + tp_pid_state = 0; + unregister_trace_sched_switch(tracectr_notifier, NULL); + } +} + +static ssize_t read_enabled_perftp_file_bool(struct file *file, + char __user *user_buf, size_t count, loff_t *ppos) +{ + char buf[2]; + buf[1] = '\n'; + if (tp_pid_state == 0) + buf[0] = '0'; + else + buf[0] = '1'; + return simple_read_from_buffer(user_buf, count, ppos, buf, 2); +} + +static ssize_t write_enabled_perftp_file_bool(struct file *file, + const char __user *user_buf, size_t count, loff_t *ppos) +{ + char buf[32]; + size_t buf_size; + + buf[0] = 0; + buf_size = min(count, (sizeof(buf)-1)); + if (copy_from_user(buf, user_buf, buf_size)) + return -EFAULT; + switch (buf[0]) { + case 'y': + case 'Y': + case '1': + enable_tp_pid(); + break; + case 'n': + case 'N': + case '0': + disable_tp_pid(); + break; + } + + return count; +} + +static const struct file_operations fops_perftp = { + .read = read_enabled_perftp_file_bool, + .write = write_enabled_perftp_file_bool, + .llseek = default_llseek, +}; + +int __init init_tracecounters(void) +{ + struct dentry *dir; + struct dentry *file; + unsigned int value = 1; + int cpu; + + dir = debugfs_create_dir("perf_debug_tp", NULL); + if (!dir) + return -ENOMEM; + file = debugfs_create_file("enabled", 0660, dir, + &value, &fops_perftp); + if (!file) { + debugfs_remove(dir); + return -ENOMEM; + } + for_each_possible_cpu(cpu) + per_cpu(old_pid, cpu) = -1; + register_cpu_notifier(&tracectr_cpu_hotplug_notifier_block); + return 0; +} + +int __exit exit_tracecounters(void) +{ + unregister_cpu_notifier(&tracectr_cpu_hotplug_notifier_block); + return 0; +} +late_initcall(init_tracecounters); --- /dev/null 2019-10-24 16:47:25.704025805 +0200 +++ linux-4.4.115-fbx/arch/arm64/kernel/perf_trace_counters.h 2019-01-22 16:16:21.551228730 +0100 @@ -0,0 +1,111 @@ +/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#undef TRACE_SYSTEM +#define TRACE_SYSTEM perf_trace_counters + +#if !defined(_PERF_TRACE_COUNTERS_H_) || defined(TRACE_HEADER_MULTI_READ) +#define _PERF_TRACE_COUNTERS_H_ + +/* Ctr index for PMCNTENSET/CLR */ +#define CC 0x80000000 +#define C0 0x1 +#define C1 0x2 +#define C2 0x4 +#define C3 0x8 +#define C4 0x10 +#define C5 0x20 +#define C_ALL (CC | C0 | C1 | C2 | C3 | C4 | C5) +#define NUM_L1_CTRS 6 + +#include +#include +#include + +DECLARE_PER_CPU(u32, cntenset_val); +DECLARE_PER_CPU(u32, previous_ccnt); +DECLARE_PER_CPU(u32[NUM_L1_CTRS], previous_l1_cnts); +TRACE_EVENT(sched_switch_with_ctrs, + + TP_PROTO(pid_t prev, pid_t next), + + TP_ARGS(prev, next), + + TP_STRUCT__entry( + __field(pid_t, old_pid) + __field(pid_t, new_pid) + __field(u32, cctr) + __field(u32, ctr0) + __field(u32, ctr1) + __field(u32, ctr2) + __field(u32, ctr3) + __field(u32, ctr4) + __field(u32, ctr5) + ), + + TP_fast_assign( + u32 cpu = smp_processor_id(); + u32 i; + u32 cnten_val; + u32 total_ccnt = 0; + u32 total_cnt = 0; + u32 delta_l1_cnts[NUM_L1_CTRS]; + __entry->old_pid = prev; + __entry->new_pid = next; + + cnten_val = per_cpu(cntenset_val, cpu); + + if (cnten_val & CC) { + asm volatile("mrs %0, pmccntr_el0" + : "=r" (total_ccnt)); + /* Read value */ + __entry->cctr = total_ccnt - + per_cpu(previous_ccnt, cpu); + per_cpu(previous_ccnt, cpu) = total_ccnt; + } + for (i = 0; i < NUM_L1_CTRS; i++) { + if (cnten_val & (1 << i)) { + /* Select */ + asm volatile("msr pmselr_el0, %0" + : : "r" (i)); + isb(); + asm volatile("mrs %0, pmxevcntr_el0" + : "=r" (total_cnt)); + /* Read value */ + delta_l1_cnts[i] = total_cnt - + per_cpu(previous_l1_cnts[i], cpu); + per_cpu(previous_l1_cnts[i], cpu) = + total_cnt; + } else + delta_l1_cnts[i] = 0; + } + + __entry->ctr0 = delta_l1_cnts[0]; + __entry->ctr1 = delta_l1_cnts[1]; + __entry->ctr2 = delta_l1_cnts[2]; + __entry->ctr3 = delta_l1_cnts[3]; + __entry->ctr4 = delta_l1_cnts[4]; + __entry->ctr5 = delta_l1_cnts[5]; + ), + + TP_printk("prev_pid=%d, next_pid=%d, CCNTR: %u, CTR0: %u, CTR1: %u, CTR2: %u, CTR3: %u, CTR4: %u, CTR5: %u", + __entry->old_pid, __entry->new_pid, + __entry->cctr, __entry->ctr0, __entry->ctr1, + __entry->ctr2, __entry->ctr3, + __entry->ctr4, __entry->ctr5) +); + +#endif +#undef TRACE_INCLUDE_PATH +#define TRACE_INCLUDE_PATH ../../arch/arm64/kernel +#define TRACE_INCLUDE_FILE perf_trace_counters +#include --- /dev/null 2019-10-24 16:47:25.704025805 +0200 +++ linux-4.4.115-fbx/arch/arm64/kernel/perf_trace_user.c 2019-01-22 16:16:21.551228730 +0100 @@ -0,0 +1,96 @@ +/* Copyright (c) 2014, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include +#include +#include +#include +#include +#include +#include +#include + +#define CREATE_TRACE_POINTS +#include "perf_trace_user.h" + +#undef TRACE_SYSTEM +#define TRACE_SYSTEM perf_trace_counters + +#define TRACE_USER_MAX_BUF_SIZE 100 + +static ssize_t perf_trace_write(struct file *file, + const char __user *user_string_in, + size_t len, loff_t *ppos) +{ + u32 cnten_val; + int rc; + char buf[TRACE_USER_MAX_BUF_SIZE + 1]; + ssize_t length; + + if (len == 0) + return 0; + + length = len > TRACE_USER_MAX_BUF_SIZE ? TRACE_USER_MAX_BUF_SIZE : len; + + rc = copy_from_user(buf, user_string_in, length); + if (rc) { + pr_err("%s copy_from_user failed, rc=%d\n", __func__, rc); + return length; + } + + /* Remove any trailing newline and make sure string is terminated */ + if (buf[length - 1] == '\n') + buf[length - 1] = '\0'; + else + buf[length] = '\0'; + + /* + * Disable preemption to ensure that all the performance counter + * accesses happen on the same cpu + */ + preempt_disable(); + /* stop counters, call the trace function, restart them */ + + asm volatile("mrs %0, pmcntenset_el0" : "=r" (cnten_val)); + /* Disable all the counters that were enabled */ + asm volatile("msr pmcntenclr_el0, %0" : : "r" (cnten_val)); + + trace_perf_trace_user(buf, cnten_val); + + /* Enable all the counters that were disabled */ + asm volatile("msr pmcntenset_el0, %0" : : "r" (cnten_val)); + preempt_enable(); + + return length; +} + +static const struct file_operations perf_trace_fops = { + .write = perf_trace_write +}; + +static int __init init_perf_trace(void) +{ + struct dentry *dir; + struct dentry *file; + unsigned int value = 1; + + dir = perf_create_debug_dir(); + if (!dir) + return -ENOMEM; + file = debugfs_create_file("trace_marker", S_IWUSR | S_IWGRP, dir, + &value, &perf_trace_fops); + if (!file) + return -ENOMEM; + + return 0; +} + +late_initcall(init_perf_trace); --- /dev/null 2019-10-24 16:47:25.704025805 +0200 +++ linux-4.4.115-fbx/arch/arm64/kernel/perf_trace_user.h 2019-01-22 16:16:21.551228730 +0100 @@ -0,0 +1,85 @@ +/* Copyright (c) 2014, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#if !defined(_PERF_TRACE_USER_H_) || defined(TRACE_HEADER_MULTI_READ) +#define _PERF_TRACE_USER_H_ + +#undef TRACE_SYSTEM +#define TRACE_SYSTEM perf_trace_counters + +#include + +#define CNTENSET_CC 0x80000000 +#define NUM_L1_CTRS 4 + +TRACE_EVENT(perf_trace_user, + TP_PROTO(char *string, u32 cnten_val), + TP_ARGS(string, cnten_val), + + TP_STRUCT__entry( + __field(u32, cctr) + __field(u32, ctr0) + __field(u32, ctr1) + __field(u32, ctr2) + __field(u32, ctr3) + __field(u32, lctr0) + __field(u32, lctr1) + __string(user_string, string) + ), + + TP_fast_assign( + u32 cnt; + u32 l1_cnts[NUM_L1_CTRS]; + int i; + + if (cnten_val & CNTENSET_CC) { + /* Read value */ + asm volatile("mrs %0, pmccntr_el0" : "=r" (cnt)); + __entry->cctr = cnt; + } else + __entry->cctr = 0; + for (i = 0; i < NUM_L1_CTRS; i++) { + if (cnten_val & (1 << i)) { + /* Select */ + asm volatile("msr pmselr_el0, %0" + : : "r" (i)); + isb(); + /* Read value */ + asm volatile("mrs %0, pmxevcntr_el0" + : "=r" (cnt)); + l1_cnts[i] = cnt; + } else { + l1_cnts[i] = 0; + } + } + + __entry->ctr0 = l1_cnts[0]; + __entry->ctr1 = l1_cnts[1]; + __entry->ctr2 = l1_cnts[2]; + __entry->ctr3 = l1_cnts[3]; + __entry->lctr0 = 0; + __entry->lctr1 = 0; + __assign_str(user_string, string); + ), + + TP_printk("CCNTR: %u, CTR0: %u, CTR1: %u, CTR2: %u, CTR3: %u, L2CTR0: %u, L2CTR1: %u, MSG=%s", + __entry->cctr, __entry->ctr0, __entry->ctr1, + __entry->ctr2, __entry->ctr3, + __entry->lctr0, __entry->lctr1, + __get_str(user_string) + ) + ); + +#endif +#undef TRACE_INCLUDE_PATH +#define TRACE_INCLUDE_PATH ../../arch/arm64/kernel +#define TRACE_INCLUDE_FILE perf_trace_user +#include diff -Nruw linux-4.4.115-fbx/arch/arm64/kernel/probes./Makefile linux-4.4.115-fbx/arch/arm64/kernel/probes/Makefile --- linux-4.4.115-fbx/arch/arm64/kernel/probes./Makefile 1970-01-01 01:00:00.000000000 +0100 +++ linux-4.4.115-fbx/arch/arm64/kernel/probes/Makefile 2019-01-22 16:16:21.551228730 +0100 @@ -0,0 +1,3 @@ +obj-$(CONFIG_KPROBES) += kprobes.o decode-insn.o \ + kprobes_trampoline.o \ + simulate-insn.o --- /dev/null 2019-10-24 16:47:25.704025805 +0200 +++ linux-4.4.115-fbx/arch/arm64/kernel/smccc-call.S 2019-01-22 16:16:21.555228766 +0100 @@ -0,0 +1,43 @@ +/* + * Copyright (c) 2015, Linaro Limited + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License Version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ +#include +#include + + .macro SMCCC instr + .cfi_startproc + \instr #0 + ldr x4, [sp] + stp x0, x1, [x4, #ARM_SMCCC_RES_X0_OFFS] + stp x2, x3, [x4, #ARM_SMCCC_RES_X2_OFFS] + ret + .cfi_endproc + .endm + +/* + * void arm_smccc_smc(unsigned long a0, unsigned long a1, unsigned long a2, + * unsigned long a3, unsigned long a4, unsigned long a5, + * unsigned long a6, unsigned long a7, struct arm_smccc_res *res) + */ +ENTRY(arm_smccc_smc) + SMCCC smc +ENDPROC(arm_smccc_smc) + +/* + * void arm_smccc_hvc(unsigned long a0, unsigned long a1, unsigned long a2, + * unsigned long a3, unsigned long a4, unsigned long a5, + * unsigned long a6, unsigned long a7, struct arm_smccc_res *res) + */ +ENTRY(arm_smccc_hvc) + SMCCC hvc +ENDPROC(arm_smccc_hvc) diff -Nruw linux-4.4.115-fbx/arch/arm64/kvm/hyp./Makefile linux-4.4.115-fbx/arch/arm64/kvm/hyp/Makefile --- linux-4.4.115-fbx/arch/arm64/kvm/hyp./Makefile 1970-01-01 01:00:00.000000000 +0100 +++ linux-4.4.115-fbx/arch/arm64/kvm/hyp/Makefile 2019-01-22 16:16:21.555228766 +0100 @@ -0,0 +1,14 @@ +# +# Makefile for Kernel-based Virtual Machine module, HYP part +# + +obj-$(CONFIG_KVM_ARM_HOST) += vgic-v2-sr.o +obj-$(CONFIG_KVM_ARM_HOST) += vgic-v3-sr.o +obj-$(CONFIG_KVM_ARM_HOST) += timer-sr.o +obj-$(CONFIG_KVM_ARM_HOST) += sysreg-sr.o +obj-$(CONFIG_KVM_ARM_HOST) += debug-sr.o +obj-$(CONFIG_KVM_ARM_HOST) += entry.o +obj-$(CONFIG_KVM_ARM_HOST) += switch.o +obj-$(CONFIG_KVM_ARM_HOST) += fpsimd.o +obj-$(CONFIG_KVM_ARM_HOST) += tlb.o +obj-$(CONFIG_KVM_ARM_HOST) += hyp-entry.o --- /dev/null 2019-10-24 16:47:25.704025805 +0200 +++ linux-4.4.115-fbx/arch/cris/boot/dts/include/dt-bindings/clock/audio-ext-clk.h 2019-01-22 16:16:28.167288642 +0100 @@ -0,0 +1,30 @@ +/* Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __AUDIO_EXT_CLK_H +#define __AUDIO_EXT_CLK_H + +/* Audio External Clocks */ +#define AUDIO_PMI_CLK 0 +#define AUDIO_PMIC_LNBB_CLK 0 +#define AUDIO_AP_CLK 1 +#define AUDIO_AP_CLK2 2 +#define AUDIO_LPASS_MCLK 3 +#define AUDIO_LPASS_MCLK2 4 + +#define clk_audio_ap_clk 0x9b5727cb +#define clk_audio_pmi_clk 0xcbfe416d +#define clk_audio_ap_clk2 0x454d1e91 +#define clk_audio_lpass_mclk 0xf0f2a284 +#define clk_audio_pmi_lnbb_clk 0x57312343 + +#endif --- /dev/null 2019-10-24 16:47:25.704025805 +0200 +++ linux-4.4.115-fbx/arch/cris/boot/dts/include/dt-bindings/clock/msm-clocks-8996.h 2019-01-22 16:16:28.171288678 +0100 @@ -0,0 +1,574 @@ +/* Copyright (c) 2014-2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __MSM_CLOCKS_8996_H +#define __MSM_CLOCKS_8996_H + +#include "audio-ext-clk.h" + +/* clock_gcc controlled clocks */ +#define clk_cxo_clk_src 0x79e95308 +#define clk_pnoc_clk 0x4325d220 +#define clk_pnoc_a_clk 0x2808c12b +#define clk_bimc_clk 0x4b80bf00 +#define clk_bimc_a_clk 0x4b25668a +#define clk_cnoc_clk 0xd5ccb7f4 +#define clk_cnoc_a_clk 0xd8fe2ccc +#define clk_snoc_clk 0x2c341aa0 +#define clk_snoc_a_clk 0x8fcef2af +#define clk_bb_clk1 0xf5304268 +#define clk_bb_clk1_ao 0xfa113810 +#define clk_bb_clk1_pin 0x6dd0a779 +#define clk_bb_clk1_pin_ao 0x9b637772 +#define clk_bb_clk2 0xfe15cb87 +#define clk_bb_clk2_ao 0x59682706 +#define clk_bb_clk2_pin 0x498938e5 +#define clk_bb_clk2_pin_ao 0x52513787 +#define clk_bimc_msmbus_clk 0xd212feea +#define clk_bimc_msmbus_a_clk 0x71d1a499 +#define clk_ce1_a_clk 0x44a833fe +#define clk_cnoc_msmbus_clk 0x62228b5d +#define clk_cnoc_msmbus_a_clk 0x67442955 +#define clk_cxo_clk_src_ao 0x64eb6004 +#define clk_cxo_dwc3_clk 0xf79c19f6 +#define clk_cxo_lpm_clk 0x94adbf3d +#define clk_cxo_otg_clk 0x4eec0bb9 +#define clk_cxo_pil_lpass_clk 0xe17f0ff6 +#define clk_cxo_pil_ssc_clk 0x81832015 +#define clk_div_clk1 0xaa1157a6 +#define clk_div_clk1_ao 0x6b943d68 +#define clk_div_clk2 0xd454019f +#define clk_div_clk2_ao 0x53f9e788 +#define clk_div_clk3 0xa9a55a68 +#define clk_div_clk3_ao 0x3d6725a8 +#define clk_ipa_a_clk 0xeeec2919 +#define clk_ipa_clk 0xfa685cda +#define clk_ln_bb_clk 0x3ab0b36d +#define clk_ln_bb_a_clk 0xc7257ea8 +#define clk_ln_bb_clk_pin 0x1b1c476a +#define clk_ln_bb_a_clk_pin 0x9cbb5411 +#define clk_mcd_ce1_clk 0xbb615d26 +#define clk_pnoc_keepalive_a_clk 0xf8f91f0b +#define clk_pnoc_msmbus_clk 0x38b95c77 +#define clk_pnoc_msmbus_a_clk 0x8c9b4e93 +#define clk_pnoc_pm_clk 0xd6f7dfb9 +#define clk_pnoc_sps_clk 0xd482ecc7 +#define clk_qdss_a_clk 0xdd121669 +#define clk_qdss_clk 0x1492202a +#define clk_rf_clk1 0xaabeea5a +#define clk_rf_clk1_ao 0x72a10cb8 +#define clk_rf_clk1_pin 0x8f463562 +#define clk_rf_clk1_pin_ao 0x62549ff6 +#define clk_rf_clk2 0x24a30992 +#define clk_rf_clk2_ao 0x944d8bbd +#define clk_rf_clk2_pin 0xa7c5602a +#define clk_rf_clk2_pin_ao 0x2d75eb4d +#define clk_snoc_msmbus_clk 0xe6900bb6 +#define clk_snoc_msmbus_a_clk 0x5d4683bd +#define clk_mcd_ce1_clk 0xbb615d26 +#define clk_qcedev_ce1_clk 0x293f97b0 +#define clk_qcrypto_ce1_clk 0xa6ac14df +#define clk_qseecom_ce1_clk 0xaa858373 +#define clk_scm_ce1_clk 0xd8ebcc62 +#define clk_ce1_clk 0x42229c55 +#define clk_gcc_ce1_ahb_m_clk 0x2eb28c01 +#define clk_gcc_ce1_axi_m_clk 0xc174dfba +#define clk_measure_only_bimc_hmss_axi_clk 0xc1cc4f11 +#define clk_aggre1_noc_clk 0x049abba8 +#define clk_aggre1_noc_a_clk 0xc12e4220 +#define clk_aggre2_noc_clk 0xaa681404 +#define clk_aggre2_noc_a_clk 0xcab67089 +#define clk_mmssnoc_axi_rpm_clk 0x4d7f8cdc +#define clk_mmssnoc_axi_rpm_a_clk 0xfbea899b +#define clk_mmssnoc_axi_clk 0xdb4b31e6 +#define clk_mmssnoc_axi_a_clk 0xd4970614 +#define clk_mmssnoc_gds_clk 0x06a22afa + +#define clk_gpll0 0x1ebe3bc4 +#define clk_gpll0_ao 0xa1368304 +#define clk_gpll0_out_main 0xe9374de7 +#define clk_gpll4 0xb3b5d85b +#define clk_gpll4_out_main 0xa9a0ab9d +#define clk_ufs_axi_clk_src 0x297ca380 +#define clk_pcie_aux_clk_src 0xebc50566 +#define clk_usb30_master_clk_src 0xc6262f89 +#define clk_usb20_master_clk_src 0x5680ac83 +#define clk_ufs_ice_core_clk_src 0xda8e7119 +#define clk_blsp1_qup1_i2c_apps_clk_src 0x17f78f5e +#define clk_blsp1_qup1_spi_apps_clk_src 0xf534c4fa +#define clk_blsp1_qup2_i2c_apps_clk_src 0x8de71c79 +#define clk_blsp1_qup2_spi_apps_clk_src 0x33cf809a +#define clk_blsp1_qup3_i2c_apps_clk_src 0xf161b902 +#define clk_blsp1_qup3_spi_apps_clk_src 0x5e95683f +#define clk_blsp1_qup4_i2c_apps_clk_src 0xb2ecce68 +#define clk_blsp1_qup4_spi_apps_clk_src 0xddb5bbdb +#define clk_blsp1_qup5_i2c_apps_clk_src 0x71ea7804 +#define clk_blsp1_qup5_spi_apps_clk_src 0x9752f35f +#define clk_blsp1_qup6_i2c_apps_clk_src 0x28806803 +#define clk_blsp1_qup6_spi_apps_clk_src 0x44a1edc4 +#define clk_blsp1_uart1_apps_clk_src 0xf8146114 +#define clk_blsp1_uart2_apps_clk_src 0xfc9c2f73 +#define clk_blsp1_uart3_apps_clk_src 0x600497f2 +#define clk_blsp1_uart4_apps_clk_src 0x56bff15c +#define clk_blsp1_uart5_apps_clk_src 0x218ef697 +#define clk_blsp1_uart6_apps_clk_src 0x8fbdbe4c +#define clk_blsp2_qup1_i2c_apps_clk_src 0xd6d1e95d +#define clk_blsp2_qup1_spi_apps_clk_src 0xcc1b8365 +#define clk_blsp2_qup2_i2c_apps_clk_src 0x603b5c51 +#define clk_blsp2_qup2_spi_apps_clk_src 0xd577dc44 +#define clk_blsp2_qup3_i2c_apps_clk_src 0xea82959c +#define clk_blsp2_qup3_spi_apps_clk_src 0xd04b1e92 +#define clk_blsp2_qup4_i2c_apps_clk_src 0x73dc968c +#define clk_blsp2_qup4_spi_apps_clk_src 0x25d4a2b1 +#define clk_blsp2_qup5_i2c_apps_clk_src 0xcc3698bd +#define clk_blsp2_qup5_spi_apps_clk_src 0xfa0cf45e +#define clk_blsp2_qup6_i2c_apps_clk_src 0x2fa53151 +#define clk_blsp2_qup6_spi_apps_clk_src 0x5ca86755 +#define clk_blsp2_uart1_apps_clk_src 0x562c66dc +#define clk_blsp2_uart2_apps_clk_src 0xdd448080 +#define clk_blsp2_uart3_apps_clk_src 0x46b2e90f +#define clk_blsp2_uart4_apps_clk_src 0x23a093d2 +#define clk_blsp2_uart5_apps_clk_src 0xe067616a +#define clk_blsp2_uart6_apps_clk_src 0xe02d2829 +#define clk_gp1_clk_src 0xad85b97a +#define clk_gp2_clk_src 0xfb1f0065 +#define clk_gp3_clk_src 0x63b693d6 +#define clk_hmss_rbcpr_clk_src 0xedd9a474 +#define clk_pdm2_clk_src 0x31e494fd +#define clk_sdcc1_apps_clk_src 0xd4975db2 +#define clk_sdcc2_apps_clk_src 0xfc46c821 +#define clk_sdcc3_apps_clk_src 0xea34c7f4 +#define clk_sdcc4_apps_clk_src 0x7aaaaa0c +#define clk_tsif_ref_clk_src 0x4e9042d1 +#define clk_usb20_mock_utmi_clk_src 0xc3aaeecb +#define clk_usb30_mock_utmi_clk_src 0xa024a976 +#define clk_usb3_phy_aux_clk_src 0x15eec63c +#define clk_gcc_qusb2phy_prim_reset 0x07550fa1 +#define clk_gcc_qusb2phy_sec_reset 0x3f3a87d0 +#define clk_gcc_periph_noc_usb20_ahb_clk 0xfb9f26e9 +#define clk_gcc_mmss_gcc_dbg_clk 0xe89d461c +#define clk_cpu_dbg_clk 0x6550dfa9 +#define clk_gcc_blsp1_ahb_clk 0x8caa5b4f +#define clk_gcc_blsp1_qup1_i2c_apps_clk 0xc303fae9 +#define clk_gcc_blsp1_qup1_spi_apps_clk 0x759a76b0 +#define clk_gcc_blsp1_qup2_i2c_apps_clk 0x1076f220 +#define clk_gcc_blsp1_qup2_spi_apps_clk 0x3e77d48f +#define clk_gcc_blsp1_qup3_i2c_apps_clk 0x9e25ac82 +#define clk_gcc_blsp1_qup3_spi_apps_clk 0xfb978880 +#define clk_gcc_blsp1_qup4_i2c_apps_clk 0xd7f40f6f +#define clk_gcc_blsp1_qup4_spi_apps_clk 0x80f8722f +#define clk_gcc_blsp1_qup5_i2c_apps_clk 0xacae5604 +#define clk_gcc_blsp1_qup5_spi_apps_clk 0xbf3e15d7 +#define clk_gcc_blsp1_qup6_i2c_apps_clk 0x5c6ad820 +#define clk_gcc_blsp1_qup6_spi_apps_clk 0x780d9f85 +#define clk_gcc_blsp1_uart1_apps_clk 0xc7c62f90 +#define clk_gcc_blsp1_uart2_apps_clk 0xf8a61c96 +#define clk_gcc_blsp1_uart3_apps_clk 0xc3298bd7 +#define clk_gcc_blsp1_uart4_apps_clk 0x26be16c0 +#define clk_gcc_blsp1_uart5_apps_clk 0x28a6bc74 +#define clk_gcc_blsp1_uart6_apps_clk 0x28fd3466 +#define clk_gcc_blsp2_ahb_clk 0x8f283c1d +#define clk_gcc_blsp2_qup1_i2c_apps_clk 0x9ace11dd +#define clk_gcc_blsp2_qup1_spi_apps_clk 0xa32604cc +#define clk_gcc_blsp2_qup2_i2c_apps_clk 0x1bf9a57e +#define clk_gcc_blsp2_qup2_spi_apps_clk 0xbf54ca6d +#define clk_gcc_blsp2_qup3_i2c_apps_clk 0x336d4170 +#define clk_gcc_blsp2_qup3_spi_apps_clk 0xc68509d6 +#define clk_gcc_blsp2_qup4_i2c_apps_clk 0xbd22539d +#define clk_gcc_blsp2_qup4_spi_apps_clk 0x01a72b93 +#define clk_gcc_blsp2_qup5_i2c_apps_clk 0xe2b2ce1d +#define clk_gcc_blsp2_qup5_spi_apps_clk 0xf40999cd +#define clk_gcc_blsp2_qup6_i2c_apps_clk 0x894bcea4 +#define clk_gcc_blsp2_qup6_spi_apps_clk 0xfe1bd34a +#define clk_gcc_blsp2_uart1_apps_clk 0x8c3512ff +#define clk_gcc_blsp2_uart2_apps_clk 0x1e1965a3 +#define clk_gcc_blsp2_uart3_apps_clk 0x382415ab +#define clk_gcc_blsp2_uart4_apps_clk 0x87a44b42 +#define clk_gcc_blsp2_uart5_apps_clk 0x5cd30649 +#define clk_gcc_blsp2_uart6_apps_clk 0x8feee5ab +#define clk_gcc_boot_rom_ahb_clk 0xde2adeb1 +#define clk_gcc_gp1_clk 0x057f7b69 +#define clk_gcc_gp2_clk 0x9bf83ffd +#define clk_gcc_gp3_clk 0xec6539ee +#define clk_gcc_hmss_rbcpr_clk 0x699183be +#define clk_gcc_mmss_noc_cfg_ahb_clk 0xb41a9d99 +#define clk_gcc_pcie_0_aux_clk 0x3d2e3ece +#define clk_gcc_pcie_0_cfg_ahb_clk 0x4dd325c3 +#define clk_gcc_pcie_0_mstr_axi_clk 0x3f85285b +#define clk_gcc_pcie_0_slv_axi_clk 0xd69638a1 +#define clk_gcc_pcie_0_pipe_clk 0x4f37621e +#define clk_gcc_pcie_0_phy_reset 0xdc3201c1 +#define clk_gcc_pcie_1_aux_clk 0xc9bb962c +#define clk_gcc_pcie_1_cfg_ahb_clk 0xb6338658 +#define clk_gcc_pcie_1_mstr_axi_clk 0xc20f6269 +#define clk_gcc_pcie_1_slv_axi_clk 0xd54e40d6 +#define clk_gcc_pcie_1_pipe_clk 0xc1627422 +#define clk_gcc_pcie_1_phy_reset 0x674481bb +#define clk_gcc_pcie_2_aux_clk 0xa4dc7ae8 +#define clk_gcc_pcie_2_cfg_ahb_clk 0x4f1d3121 +#define clk_gcc_pcie_2_mstr_axi_clk 0x9e81724a +#define clk_gcc_pcie_2_slv_axi_clk 0x7990d8b2 +#define clk_gcc_pcie_2_pipe_clk 0xa757a834 +#define clk_gcc_pcie_2_phy_reset 0x82634880 +#define clk_gcc_pcie_phy_reset 0x9bc3c959 +#define clk_gcc_pcie_phy_com_reset 0x8bf513e6 +#define clk_gcc_pcie_phy_nocsr_com_phy_reset 0x0c16a2da +#define clk_gcc_pcie_phy_aux_clk 0x4746e74f +#define clk_gcc_pcie_phy_cfg_ahb_clk 0x8533671a +#define clk_gcc_pdm2_clk 0x99d55711 +#define clk_gcc_pdm_ahb_clk 0x365664f6 +#define clk_gcc_prng_ahb_clk 0x397e7eaa +#define clk_gcc_sdcc1_ahb_clk 0x691e0caa +#define clk_gcc_sdcc1_apps_clk 0x9ad6fb96 +#define clk_gcc_sdcc2_ahb_clk 0x23d5727f +#define clk_gcc_sdcc2_apps_clk 0x861b20ac +#define clk_gcc_sdcc3_ahb_clk 0x565b2c03 +#define clk_gcc_sdcc3_apps_clk 0x0b27aeac +#define clk_gcc_sdcc4_ahb_clk 0x64f3e6a8 +#define clk_gcc_sdcc4_apps_clk 0xbf7c4dc8 +#define clk_gcc_tsif_ahb_clk 0x88d2822c +#define clk_gcc_tsif_ref_clk 0x8f1ed2c2 +#define clk_gcc_ufs_ahb_clk 0x1914bb84 +#define clk_gcc_ufs_axi_clk 0x47c743a7 +#define clk_gcc_ufs_ice_core_clk 0x310b0710 +#define clk_gcc_ufs_rx_cfg_clk 0xa6747786 +#define clk_gcc_ufs_rx_symbol_0_clk 0x7f43251c +#define clk_gcc_ufs_rx_symbol_1_clk 0x03182fde +#define clk_gcc_ufs_tx_cfg_clk 0xba2cf8b5 +#define clk_gcc_ufs_tx_symbol_0_clk 0x6a9f747a +#define clk_gcc_ufs_unipro_core_clk 0x2daf7fd2 +#define clk_gcc_ufs_sys_clk_core_clk 0x360e5ac8 +#define clk_gcc_ufs_tx_symbol_clk_core_clk 0xf6fb0df7 +#define clk_gcc_usb20_master_clk 0x24c3b66a +#define clk_gcc_usb20_mock_utmi_clk 0xe8db8203 +#define clk_gcc_usb20_sleep_clk 0x6e8cb4b2 +#define clk_gcc_usb30_master_clk 0xb3b4e2cb +#define clk_gcc_usb30_mock_utmi_clk 0xa800b65a +#define clk_gcc_usb30_sleep_clk 0xd0b65c92 +#define clk_gcc_usb3_phy_aux_clk 0x0d9a36e0 +#define clk_gcc_usb3_phy_pipe_clk 0xf279aff2 +#define clk_gcc_usb_phy_cfg_ahb2phy_clk 0xd1231a0e +#define clk_gcc_aggre0_cnoc_ahb_clk 0x53a35559 +#define clk_gcc_aggre0_snoc_axi_clk 0x3c446400 +#define clk_gcc_aggre0_noc_qosgen_extref_clk 0x8c4356ba +#define clk_hlos1_vote_lpass_core_smmu_clk 0x3aaa1743 +#define clk_hlos1_vote_lpass_adsp_smmu_clk 0xc76f702f +#define clk_gcc_usb3_phy_reset 0x03d559f1 +#define clk_gcc_usb3phy_phy_reset 0xb1a4f885 +#define clk_gcc_usb3_clkref_clk 0xb6cc8f01 +#define clk_gcc_hdmi_clkref_clk 0x4d4eec04 +#define clk_gcc_edp_clkref_clk 0xa8685c3f +#define clk_gcc_ufs_clkref_clk 0x92aa126f +#define clk_gcc_pcie_clkref_clk 0xa2e247fa +#define clk_gcc_rx2_usb2_clkref_clk 0x27ec24ba +#define clk_gcc_rx1_usb2_clkref_clk 0x53351d25 +#define clk_gcc_smmu_aggre0_ahb_clk 0x47a06ce4 +#define clk_gcc_smmu_aggre0_axi_clk 0x3cac4a6c +#define clk_gcc_sys_noc_usb3_axi_clk 0x94d26800 +#define clk_gcc_sys_noc_ufs_axi_clk 0x19d38312 +#define clk_gcc_aggre2_usb3_axi_clk 0xd5822a8e +#define clk_gcc_aggre2_ufs_axi_clk 0xb31e5191 +#define clk_gcc_mmss_gpll0_div_clk 0xdd06848d +#define clk_gcc_mmss_bimc_gfx_clk 0xe4f28754 +#define clk_gcc_bimc_gfx_clk 0x3edd69ad +#define clk_gcc_qspi_ahb_clk 0x96969dc8 +#define clk_gcc_qspi_ser_clk 0xfaf1e266 +#define clk_qspi_ser_clk_src 0x426676ee +#define clk_sdcc1_ice_core_clk_src 0xfd6a4301 +#define clk_gcc_sdcc1_ice_core_clk 0x0fd5680a +#define clk_gcc_mss_cfg_ahb_clk 0x111cde81 +#define clk_gcc_mss_snoc_axi_clk 0x0e71de85 +#define clk_gcc_mss_q6_bimc_axi_clk 0x67544d62 +#define clk_gcc_mss_mnoc_bimc_axi_clk 0xf665d03f +#define clk_gpll0_out_msscc 0x7d794829 +#define clk_gcc_debug_mux_v2 0xf7e749f0 +#define clk_gcc_dcc_ahb_clk 0xfa14a88c +#define clk_gcc_aggre0_noc_mpu_cfg_ahb_clk 0x5c1bb8e2 + +/* clock_mmss controlled clocks */ +#define clk_mmsscc_xo 0x05e63704 +#define clk_mmsscc_gpll0 0xe900c515 +#define clk_mmsscc_gpll0_div 0x73892e05 +#define clk_mmsscc_mmssnoc_ahb 0x7b4bd6f7 +#define clk_mmpll0 0xdd83b751 +#define clk_mmpll0_out_main 0x2f996a31 +#define clk_mmpll1 0x6da7fb90 +#define clk_mmpll1_out_main 0xa0d3a7da +#define clk_mmpll4 0x22c063c1 +#define clk_mmpll4_out_main 0xfb21c2fd +#define clk_mmpll3 0x18c76899 +#define clk_mmpll3_out_main 0x6eb6328f +#define clk_ahb_clk_src 0x86f49203 +#define clk_mmpll2 0x1190e4d8 +#define clk_mmpll2_out_main 0x1e9e24a8 +#define clk_mmpll8 0xd06ad45e +#define clk_mmpll8_out_main 0x75b1f386 +#define clk_mmpll9 0x1c50684c +#define clk_mmpll9_out_main 0x16b74937 +#define clk_mmpll5 0xa41e1936 +#define clk_mmpll5_out_main 0xcc1897bf +#define clk_csi0_clk_src 0x227e65bc +#define clk_vfe0_clk_src 0xa0c2bd8f +#define clk_vfe1_clk_src 0x4e357366 +#define clk_csi1_clk_src 0x6a2a6c36 +#define clk_csi2_clk_src 0x4113589f +#define clk_csi3_clk_src 0xfd934012 +#define clk_maxi_clk_src 0x52c09777 +#define clk_cpp_clk_src 0x8382f56d +#define clk_jpeg0_clk_src 0x9a0a0ac3 +#define clk_jpeg2_clk_src 0x5ad927f3 +#define clk_jpeg_dma_clk_src 0xb68afcea +#define clk_mdp_clk_src 0x6dc1f8f1 +#define clk_video_core_clk_src 0x8be4c944 +#define clk_fd_core_clk_src 0xe4799ab7 +#define clk_cci_clk_src 0x822f3d97 +#define clk_csiphy0_3p_clk_src 0xd2474b12 +#define clk_csiphy1_3p_clk_src 0x46a02aff +#define clk_csiphy2_3p_clk_src 0x1447813f +#define clk_camss_gp0_clk_src 0x6b57cfe6 +#define clk_camss_gp1_clk_src 0xf735368a +#define clk_jpeg_dma_clk_src 0xb68afcea +#define clk_mclk0_clk_src 0x266b3853 +#define clk_mclk1_clk_src 0xa73cad0c +#define clk_mclk2_clk_src 0x42545468 +#define clk_mclk3_clk_src 0x2bfbb714 +#define clk_csi0phytimer_clk_src 0xc8a309be +#define clk_csi1phytimer_clk_src 0x7c0fe23a +#define clk_csi2phytimer_clk_src 0x62ffea9c +#define clk_rbbmtimer_clk_src 0x17649ecc +#define clk_esc0_clk_src 0xb41d7c38 +#define clk_esc1_clk_src 0x3b0afa42 +#define clk_hdmi_clk_src 0xb40aeea9 +#define clk_vsync_clk_src 0xecb43940 +#define clk_rbcpr_clk_src 0x2c2e9af2 +#define clk_video_subcore0_clk_src 0x88d79636 +#define clk_video_subcore1_clk_src 0x4966930c +#define clk_mmss_bto_ahb_clk 0xfdf8c361 +#define clk_camss_ahb_clk 0xc4ff91d4 +#define clk_camss_cci_ahb_clk 0x04c4441a +#define clk_camss_cci_clk 0xd6cb5eb9 +#define clk_camss_cpp_ahb_clk 0x12e9a87b +#define clk_camss_cpp_clk 0xb82f366b +#define clk_camss_cpp_axi_clk 0x5598c804 +#define clk_camss_cpp_vbif_ahb_clk 0xb5f31be4 +#define clk_camss_csi0_ahb_clk 0x6e29c972 +#define clk_camss_csi0_clk 0x30862ddb +#define clk_camss_csi0phy_clk 0x2cecfb84 +#define clk_camss_csi0pix_clk 0x6946f77b +#define clk_camss_csi0rdi_clk 0x83645ef5 +#define clk_camss_csi1_ahb_clk 0xccc15f06 +#define clk_camss_csi1_clk 0xb150f052 +#define clk_camss_csi1phy_clk 0xb989f06d +#define clk_camss_csi1pix_clk 0x58d19bf3 +#define clk_camss_csi1rdi_clk 0x4d2f3352 +#define clk_camss_csi2_ahb_clk 0x92d02d75 +#define clk_camss_csi2_clk 0x74fc92e8 +#define clk_camss_csi2phy_clk 0xda05d9d8 +#define clk_camss_csi2pix_clk 0xf8ed0731 +#define clk_camss_csi2rdi_clk 0xdc1b2081 +#define clk_camss_csi3_ahb_clk 0xee5e459c +#define clk_camss_csi3_clk 0x39488fdd +#define clk_camss_csi3phy_clk 0x8b6063b9 +#define clk_camss_csi3pix_clk 0xd82bd467 +#define clk_camss_csi3rdi_clk 0xb6750046 +#define clk_camss_csi_vfe0_clk 0x3023937a +#define clk_camss_csi_vfe1_clk 0xe66fa522 +#define clk_camss_csiphy0_3p_clk 0xf2a54f5a +#define clk_camss_csiphy1_3p_clk 0x8bf70cb2 +#define clk_camss_csiphy2_3p_clk 0x1c14c939 +#define clk_camss_gp0_clk 0xcee7e51d +#define clk_camss_gp1_clk 0x41f1c2e3 +#define clk_camss_ispif_ahb_clk 0x9a212c6d +#define clk_camss_jpeg0_clk 0x0b0e2db7 +#define clk_camss_jpeg2_clk 0xd7291c8d +#define clk_camss_jpeg_ahb_clk 0x1f47fd28 +#define clk_camss_jpeg_axi_clk 0x9e5545c8 +#define clk_camss_jpeg_dma_clk 0x2336e65d +#define clk_camss_mclk0_clk 0xcf0c61e0 +#define clk_camss_mclk1_clk 0xd1410ed4 +#define clk_camss_mclk2_clk 0x851286f2 +#define clk_camss_mclk3_clk 0x4db11c45 +#define clk_camss_micro_ahb_clk 0x33a23277 +#define clk_camss_csi0phytimer_clk 0xff93b3c8 +#define clk_camss_csi1phytimer_clk 0x6c399ab6 +#define clk_camss_csi2phytimer_clk 0x24f47f49 +#define clk_camss_top_ahb_clk 0x8f8b2d33 +#define clk_camss_vfe_ahb_clk 0x595197bc +#define clk_camss_vfe_axi_clk 0x273d4c31 +#define clk_camss_vfe0_ahb_clk 0x4652833c +#define clk_camss_vfe0_clk 0x1e9bb8c4 +#define clk_camss_vfe0_stream_clk 0x22835fa4 +#define clk_camss_vfe1_ahb_clk 0x6a56abd3 +#define clk_camss_vfe1_clk 0x5bffa69b +#define clk_camss_vfe1_stream_clk 0x92f849b9 +#define clk_fd_ahb_clk 0x868a2c5c +#define clk_fd_core_clk 0x3badcae4 +#define clk_fd_core_uar_clk 0x7e624e15 +#define clk_gpu_ahb_clk 0xf97f1d43 +#define clk_gpu_aon_isense_clk 0xa9e9b297 +#define clk_gpu_gx_gfx3d_clk 0xb7ece823 +#define clk_gpu_mx_clk 0xb80ccedf +#define clk_gpu_gx_rbbmtimer_clk 0xdeba634e +#define clk_mdss_ahb_clk 0x684ccb41 +#define clk_mdss_axi_clk 0xcc07d687 +#define clk_mdss_esc0_clk 0x28cafbe6 +#define clk_mdss_esc1_clk 0xc22c6883 +#define clk_mdss_hdmi_ahb_clk 0x01cef516 +#define clk_mdss_hdmi_clk 0x097a6de9 +#define clk_mdss_mdp_clk 0x618336ac +#define clk_mdss_vsync_clk 0x42a022d3 +#define clk_mmss_misc_ahb_clk 0xea30b0e7 +#define clk_mmss_misc_cxo_clk 0xe620cd80 +#define clk_mmagic_bimc_noc_cfg_ahb_clk 0x12d5ba72 +#define clk_mmagic_camss_axi_clk 0xa8b1c16b +#define clk_mmagic_camss_noc_cfg_ahb_clk 0x5182c819 +#define clk_mmss_mmagic_cfg_ahb_clk 0x5e94a822 +#define clk_mmagic_mdss_axi_clk 0xa0359d10 +#define clk_mmagic_mdss_noc_cfg_ahb_clk 0x9c6d5482 +#define clk_mmagic_video_axi_clk 0x7b9219c3 +#define clk_mmagic_video_noc_cfg_ahb_clk 0x5124d256 +#define clk_mmss_mmagic_ahb_clk 0x3d15f2b0 +#define clk_mmss_mmagic_maxi_clk 0xbdaf5af7 +#define clk_mmss_rbcpr_ahb_clk 0x623ba55f +#define clk_mmss_rbcpr_clk 0x69a23a6f +#define clk_mmss_spdm_cpp_clk 0xefe35cd2 +#define clk_mmss_spdm_jpeg_dma_clk 0xcb7bd5a0 +#define clk_smmu_cpp_ahb_clk 0x3ad82d84 +#define clk_smmu_cpp_axi_clk 0xa6bb2f4a +#define clk_smmu_jpeg_ahb_clk 0x10c436ec +#define clk_smmu_jpeg_axi_clk 0x41112f37 +#define clk_smmu_mdp_ahb_clk 0x04994cb2 +#define clk_smmu_mdp_axi_clk 0x7fd71687 +#define clk_smmu_rot_ahb_clk 0xa30772c9 +#define clk_smmu_rot_axi_clk 0xfed7c078 +#define clk_smmu_vfe_ahb_clk 0x4dabebe7 +#define clk_smmu_vfe_axi_clk 0xde483725 +#define clk_smmu_video_ahb_clk 0x2d738e2c +#define clk_smmu_video_axi_clk 0xe2b5b887 +#define clk_video_ahb_clk 0x90775cfb +#define clk_video_axi_clk 0xe6c16dba +#define clk_video_core_clk 0x7e876ec3 +#define clk_video_maxi_clk 0x97749db6 +#define clk_video_subcore0_clk 0xb6f63e6c +#define clk_video_subcore1_clk 0x26c29cb4 +#define clk_vmem_ahb_clk 0xab6223ff +#define clk_vmem_maxi_clk 0x15ef32db +#define clk_mmss_debug_mux 0xe646ffda +#define clk_mmss_gcc_dbg_clk 0xafa4d48a +#define clk_gfx3d_clk_src 0x917f76ef +#define clk_extpclk_clk_src 0xb2c31abd +#define clk_mdss_byte0_clk 0xf5a03f64 +#define clk_mdss_byte1_clk 0xb8c7067d +#define clk_mdss_extpclk_clk 0xfa5aadb0 +#define clk_mdss_pclk0_clk 0x3487234a +#define clk_mdss_pclk1_clk 0xd5804246 +#define clk_gpu_gcc_dbg_clk 0x0ccc42cd +#define clk_mdss_mdp_vote_clk 0x588460a4 +#define clk_mdss_rotator_vote_clk 0x5b1f675e +#define clk_mmpll2_postdiv_clk 0x4fdeaaba +#define clk_mmpll8_postdiv_clk 0xedf57882 +#define clk_mmpll9_postdiv_clk 0x3064b618 +#define clk_gfx3d_clk_src_v2 0x4210acb7 +#define clk_byte0_clk_src 0x75cc885b +#define clk_byte1_clk_src 0x63c2c955 +#define clk_pclk0_clk_src 0xccac1f35 +#define clk_pclk1_clk_src 0x090f68ac +#define clk_ext_byte0_clk_src 0xfb32f31e +#define clk_ext_byte1_clk_src 0x585ef6d4 +#define clk_ext_pclk0_clk_src 0x087c1612 +#define clk_ext_pclk1_clk_src 0x8067c5a3 + +/* clock_debug controlled clocks */ +#define clk_gcc_debug_mux 0x8121ac15 + +/* external multimedia clocks */ +#define clk_dsi0pll_pixel_clk_mux 0x792379e1 +#define clk_dsi0pll_byte_clk_mux 0x60e83f06 +#define clk_dsi0pll_byte_clk_src 0xbbaa30be +#define clk_dsi0pll_pixel_clk_src 0x45b3260f +#define clk_dsi0pll_n2_div_clk 0x1474c213 +#define clk_dsi0pll_post_n1_div_clk 0xdab8c389 +#define clk_dsi0pll_vco_clk 0x15940d40 +#define clk_dsi1pll_pixel_clk_mux 0x36458019 +#define clk_dsi1pll_byte_clk_mux 0xb5a42b7b +#define clk_dsi1pll_byte_clk_src 0x63930a8f +#define clk_dsi1pll_pixel_clk_src 0x0e4c9b56 +#define clk_dsi1pll_n2_div_clk 0x2c9d4007 +#define clk_dsi1pll_post_n1_div_clk 0x03020041 +#define clk_dsi1pll_vco_clk 0x99797b50 +#define clk_mdss_dsi1_vco_clk_src 0xfcd15658 +#define clk_hdmi_vco_clk 0x66003284 + +#define clk_dsi0pll_shadow_byte_clk_src 0x177c029c +#define clk_dsi0pll_shadow_pixel_clk_src 0x98ae3c92 +#define clk_dsi0pll_shadow_n2_div_clk 0xd5f0dad9 +#define clk_dsi0pll_shadow_post_n1_div_clk 0x1f7c8cf8 +#define clk_dsi0pll_shadow_vco_clk 0xb100ca83 +#define clk_dsi1pll_shadow_byte_clk_src 0xfc021ce5 +#define clk_dsi1pll_shadow_pixel_clk_src 0xdcca3ffc +#define clk_dsi1pll_shadow_n2_div_clk 0x189541bf +#define clk_dsi1pll_shadow_post_n1_div_clk 0x1637020e +#define clk_dsi1pll_shadow_vco_clk 0x68d8b6f7 + +/* CPU clocks */ +#define clk_pwrcl_clk 0xc554130e +#define clk_pwrcl_pll 0x25454ca1 +#define clk_pwrcl_alt_pll 0xc445471b +#define clk_pwrcl_pll_main 0x28948e22 +#define clk_pwrcl_alt_pll_main 0x25c8270e +#define clk_pwrcl_hf_mux 0x77706ae6 +#define clk_pwrcl_lf_mux 0xd99e334d +#define clk_perfcl_clk 0x58869997 +#define clk_perfcl_pll 0x97dcec1c +#define clk_perfcl_alt_pll 0xfe2eaea1 +#define clk_perfcl_pll_main 0x0dbf0c0b +#define clk_perfcl_alt_pll_main 0x0b892aab +#define clk_perfcl_hf_mux 0x9e8bbe59 +#define clk_perfcl_lf_mux 0x2f9c278d +#define clk_cbf_pll 0xfe2e96a3 +#define clk_cbf_pll_main 0x2b05cf95 +#define clk_cbf_hf_mux 0x71244f73 +#define clk_cbf_clk 0x48e9e16b +#define clk_xo_ao 0x428c856d +#define clk_sys_apcsaux_clk 0x0b0dd513 +#define clk_cpu_debug_mux 0xc7acaa31 + +/* GCC block resets */ +#define QUSB2PHY_PRIM_BCR 0 +#define QUSB2PHY_SEC_BCR 1 +#define BLSP1_BCR 2 +#define BLSP2_BCR 3 +#define BOOT_ROM_BCR 4 +#define PRNG_BCR 5 +#define UFS_BCR 6 +#define USB_20_BCR 7 +#define USB_30_BCR 8 +#define USB3_PHY_BCR 9 +#define USB3PHY_PHY_BCR 10 +#define PCIE_0_PHY_BCR 11 +#define PCIE_1_PHY_BCR 12 +#define PCIE_2_PHY_BCR 13 +#define PCIE_PHY_BCR 14 +#define PCIE_PHY_COM_BCR 15 +#define PCIE_PHY_NOCSR_COM_PHY_BCR 16 + +/* MMSS Block resets */ +#define VIDEO_BCR 0 +#define MDSS_BCR 1 +#define CAMSS_MICRO_BCR 2 +#define CAMSS_JPEG_BCR 3 +#define CAMSS_VFE0_BCR 4 +#define CAMSS_VFE1_BCR 5 +#define FD_BCR 6 +#define GPU_GX_BCR 7 + +#endif --- /dev/null 2019-10-24 16:47:25.704025805 +0200 +++ linux-4.4.115-fbx/arch/cris/boot/dts/include/dt-bindings/clock/msm-clocks-8998.h 2019-01-22 16:16:28.171288678 +0100 @@ -0,0 +1,534 @@ +/* Copyright (c) 2015-2017, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __MSM_CLOCKS_8998_H +#define __MSM_CLOCKS_8998_H + +#include "audio-ext-clk.h" + +/* clock_rpm controlled clocks */ +#define clk_ce1_clk 0x42229c55 +#define clk_ce1_a_clk 0x44a833fe +#define clk_cxo_clk_src 0x79e95308 +#define clk_bimc_clk 0x4b80bf00 +#define clk_bimc_a_clk 0x4b25668a +#define clk_cnoc_clk 0xd5ccb7f4 +#define clk_cnoc_a_clk 0xd8fe2ccc +#define clk_snoc_clk 0x2c341aa0 +#define clk_snoc_a_clk 0x8fcef2af +#define clk_cnoc_periph_clk 0xb11e9cf9 +#define clk_cnoc_periph_a_clk 0x1d7faa2e +#define clk_cnoc_periph_keepalive_a_clk 0x7287aef2 +#define clk_ln_bb_clk1 0xb867b147 +#define clk_ln_bb_clk1_ao 0x7f63a93a +#define clk_ln_bb_clk1_pin 0x6fc5653c +#define clk_ln_bb_clk1_pin_ao 0x25d625bf +#define clk_ln_bb_clk2 0xf83e6387 +#define clk_ln_bb_clk2_ao 0x96f09628 +#define clk_ln_bb_clk2_pin 0xa9ebe8d5 +#define clk_ln_bb_clk2_pin_ao 0x89a1226f +#define clk_ln_bb_clk3 0x4f52a39e +#define clk_ln_bb_clk3_ao 0xb15eba76 +#define clk_ln_bb_clk3_pin 0xc4de7dad +#define clk_ln_bb_clk3_pin_ao 0xc01022e8 +#define clk_bimc_msmbus_clk 0xd212feea +#define clk_bimc_msmbus_a_clk 0x71d1a499 +#define clk_cnoc_msmbus_clk 0x62228b5d +#define clk_cnoc_msmbus_a_clk 0x67442955 +#define clk_cxo_clk_src_ao 0x64eb6004 +#define clk_cxo_dwc3_clk 0xf79c19f6 +#define clk_cxo_lpm_clk 0x94adbf3d +#define clk_cxo_otg_clk 0x4eec0bb9 +#define clk_cxo_pil_lpass_clk 0xe17f0ff6 +#define clk_cxo_pil_ssc_clk 0x81832015 +#define clk_cxo_pil_spss_clk 0x5cd71a61 +#define clk_div_clk1 0xaa1157a6 +#define clk_div_clk1_ao 0x6b943d68 +#define clk_div_clk2 0xd454019f +#define clk_div_clk2_ao 0x53f9e788 +#define clk_div_clk3 0xa9a55a68 +#define clk_div_clk3_ao 0x3d6725a8 +#define clk_ipa_clk 0xfa685cda +#define clk_ipa_a_clk 0xeeec2919 +#define clk_mcd_ce1_clk 0xbb615d26 +#define clk_mmssnoc_axi_clk 0xdb4b31e6 +#define clk_mmssnoc_axi_a_clk 0xd4970614 +#define clk_qcedev_ce1_clk 0x293f97b0 +#define clk_qcrypto_ce1_clk 0xa6ac14df +#define clk_qdss_clk 0x1492202a +#define clk_qdss_a_clk 0xdd121669 +#define clk_qseecom_ce1_clk 0xaa858373 +#define clk_rf_clk1 0xaabeea5a +#define clk_rf_clk1_ao 0x72a10cb8 +#define clk_rf_clk1_pin 0x8f463562 +#define clk_rf_clk1_pin_ao 0x62549ff6 +#define clk_rf_clk2 0x24a30992 +#define clk_rf_clk2_ao 0x944d8bbd +#define clk_rf_clk2_pin 0xa7c5602a +#define clk_rf_clk2_pin_ao 0x2d75eb4d +#define clk_rf_clk3 0xb673936b +#define clk_rf_clk3_ao 0x038bb968 +#define clk_rf_clk3_pin 0x726f53f5 +#define clk_rf_clk3_pin_ao 0x76f9240f +#define clk_scm_ce1_clk 0xd8ebcc62 +#define clk_snoc_msmbus_clk 0xe6900bb6 +#define clk_snoc_msmbus_a_clk 0x5d4683bd +#define clk_gcc_ce1_ahb_m_clk 0x2eb28c01 +#define clk_gcc_ce1_axi_m_clk 0xc174dfba +#define clk_aggre1_noc_clk 0x049abba8 +#define clk_aggre1_noc_a_clk 0xc12e4220 +#define clk_aggre2_noc_clk 0xaa681404 +#define clk_aggre2_noc_a_clk 0xcab67089 +#define clk_measure_only_bimc_hmss_axi_clk 0xc1cc4f11 + +/* clock_gcc controlled clocks*/ +#define clk_debug_mmss_clk 0x977c99b6 +#define clk_debug_rpm_clk 0x8e2b07ca +#define clk_debug_cpu_clk 0x0e696b2b +#define clk_gpu_gcc_debug_clk 0x3eb88190 +#define clk_gfx_gcc_debug_clk 0xa3a64fec +#define clk_gpll0 0x1ebe3bc4 +#define clk_gpll0_out_main 0xe9374de7 +#define clk_gpll0_ao 0xa1368304 +#define clk_gcc_mmss_gpll0_clk 0x8050f008 +#define clk_gcc_mmss_gpll0_div_clk 0xdd06848d +#define clk_gcc_gpu_gpll0_clk 0xdad7a7a4 +#define clk_gcc_gpu_gpll0_div_clk 0x07d16c6a +#define clk_gpll4 0xb3b5d85b +#define clk_gpll4_out_main 0xa9a0ab9d +#define clk_usb30_master_clk_src 0xc6262f89 +#define clk_pcie_aux_clk_src 0xebc50566 +#define clk_ufs_axi_clk_src 0x297ca380 +#define clk_blsp1_qup1_i2c_apps_clk_src 0x17f78f5e +#define clk_blsp1_qup1_spi_apps_clk_src 0xf534c4fa +#define clk_blsp1_qup2_i2c_apps_clk_src 0x8de71c79 +#define clk_blsp1_qup2_spi_apps_clk_src 0x33cf809a +#define clk_blsp1_qup3_i2c_apps_clk_src 0xf161b902 +#define clk_blsp1_qup3_spi_apps_clk_src 0x5e95683f +#define clk_blsp1_qup4_i2c_apps_clk_src 0xb2ecce68 +#define clk_blsp1_qup4_spi_apps_clk_src 0xddb5bbdb +#define clk_blsp1_qup5_i2c_apps_clk_src 0x71ea7804 +#define clk_blsp1_qup5_spi_apps_clk_src 0x9752f35f +#define clk_blsp1_qup6_i2c_apps_clk_src 0x28806803 +#define clk_blsp1_qup6_spi_apps_clk_src 0x44a1edc4 +#define clk_blsp1_uart1_apps_clk_src 0xf8146114 +#define clk_blsp1_uart2_apps_clk_src 0xfc9c2f73 +#define clk_blsp1_uart3_apps_clk_src 0x600497f2 +#define clk_blsp2_qup1_i2c_apps_clk_src 0xd6d1e95d +#define clk_blsp2_qup1_spi_apps_clk_src 0xcc1b8365 +#define clk_blsp2_qup2_i2c_apps_clk_src 0x603b5c51 +#define clk_blsp2_qup2_spi_apps_clk_src 0xd577dc44 +#define clk_blsp2_qup3_i2c_apps_clk_src 0xea82959c +#define clk_blsp2_qup3_spi_apps_clk_src 0xd04b1e92 +#define clk_blsp2_qup4_i2c_apps_clk_src 0x73dc968c +#define clk_blsp2_qup4_spi_apps_clk_src 0x25d4a2b1 +#define clk_blsp2_qup5_i2c_apps_clk_src 0xcc3698bd +#define clk_blsp2_qup5_spi_apps_clk_src 0xfa0cf45e +#define clk_blsp2_qup6_i2c_apps_clk_src 0x2fa53151 +#define clk_blsp2_qup6_spi_apps_clk_src 0x5ca86755 +#define clk_blsp2_uart1_apps_clk_src 0x562c66dc +#define clk_blsp2_uart2_apps_clk_src 0xdd448080 +#define clk_blsp2_uart3_apps_clk_src 0x46b2e90f +#define clk_gp1_clk_src 0xad85b97a +#define clk_gp2_clk_src 0xfb1f0065 +#define clk_gp3_clk_src 0x63b693d6 +#define clk_hmss_rbcpr_clk_src 0xedd9a474 +#define clk_pdm2_clk_src 0x31e494fd +#define clk_sdcc2_apps_clk_src 0xfc46c821 +#define clk_sdcc4_apps_clk_src 0x7aaaaa0c +#define clk_tsif_ref_clk_src 0x4e9042d1 +#define clk_ufs_ice_core_clk_src 0xda8e7119 +#define clk_ufs_phy_aux_clk_src 0xc6bca085 +#define clk_ufs_unipro_core_clk_src 0x179e80a9 +#define clk_usb30_mock_utmi_clk_src 0xa024a976 +#define clk_usb3_phy_aux_clk_src 0x15eec63c +#define clk_qspi_ref_clk_src 0xfe6b8e11 +#define clk_gcc_pcie_phy_0_reset 0x6bb4df33 +#define clk_gcc_usb3_phy_reset 0x03d559f1 +#define clk_gcc_usb3phy_phy_reset 0xb1a4f885 +#define clk_gcc_aggre1_ufs_axi_clk 0x873459d8 +#define clk_gcc_aggre1_ufs_axi_hw_ctl_clk 0x117a6f39 +#define clk_gcc_aggre1_usb3_axi_clk 0xc5c3fbe8 +#define clk_gcc_bimc_mss_q6_axi_clk 0x7437988f +#define clk_gcc_blsp1_ahb_clk 0x8caa5b4f +#define clk_gcc_blsp1_qup1_i2c_apps_clk 0xc303fae9 +#define clk_gcc_blsp1_qup1_spi_apps_clk 0x759a76b0 +#define clk_gcc_blsp1_qup2_i2c_apps_clk 0x1076f220 +#define clk_gcc_blsp1_qup2_spi_apps_clk 0x3e77d48f +#define clk_gcc_blsp1_qup3_i2c_apps_clk 0x9e25ac82 +#define clk_gcc_blsp1_qup3_spi_apps_clk 0xfb978880 +#define clk_gcc_blsp1_qup4_i2c_apps_clk 0xd7f40f6f +#define clk_gcc_blsp1_qup4_spi_apps_clk 0x80f8722f +#define clk_gcc_blsp1_qup5_i2c_apps_clk 0xacae5604 +#define clk_gcc_blsp1_qup5_spi_apps_clk 0xbf3e15d7 +#define clk_gcc_blsp1_qup6_i2c_apps_clk 0x5c6ad820 +#define clk_gcc_blsp1_qup6_spi_apps_clk 0x780d9f85 +#define clk_gcc_blsp1_uart1_apps_clk 0xc7c62f90 +#define clk_gcc_blsp1_uart2_apps_clk 0xf8a61c96 +#define clk_gcc_blsp1_uart3_apps_clk 0xc3298bd7 +#define clk_gcc_blsp2_ahb_clk 0x8f283c1d +#define clk_gcc_blsp2_qup1_i2c_apps_clk 0x9ace11dd +#define clk_gcc_blsp2_qup1_spi_apps_clk 0xa32604cc +#define clk_gcc_blsp2_qup2_i2c_apps_clk 0x1bf9a57e +#define clk_gcc_blsp2_qup2_spi_apps_clk 0xbf54ca6d +#define clk_gcc_blsp2_qup3_i2c_apps_clk 0x336d4170 +#define clk_gcc_blsp2_qup3_spi_apps_clk 0xc68509d6 +#define clk_gcc_blsp2_qup4_i2c_apps_clk 0xbd22539d +#define clk_gcc_blsp2_qup4_spi_apps_clk 0x01a72b93 +#define clk_gcc_blsp2_qup5_i2c_apps_clk 0xe2b2ce1d +#define clk_gcc_blsp2_qup5_spi_apps_clk 0xf40999cd +#define clk_gcc_blsp2_qup6_i2c_apps_clk 0x894bcea4 +#define clk_gcc_blsp2_qup6_spi_apps_clk 0xfe1bd34a +#define clk_gcc_blsp2_uart1_apps_clk 0x8c3512ff +#define clk_gcc_blsp2_uart2_apps_clk 0x1e1965a3 +#define clk_gcc_blsp2_uart3_apps_clk 0x382415ab +#define clk_gcc_boot_rom_ahb_clk 0xde2adeb1 +#define clk_gcc_bimc_gfx_clk 0x3edd69ad +#define clk_gcc_cfg_noc_usb3_axi_clk 0x9ea4c2d9 +#define clk_gcc_gp1_clk 0x057f7b69 +#define clk_gcc_gp2_clk 0x9bf83ffd +#define clk_gcc_gp3_clk 0xec6539ee +#define clk_gcc_gpu_bimc_gfx_clk 0x3909459b +#define clk_gcc_gpu_cfg_ahb_clk 0x72f20a57 +#define clk_gcc_gpu_iref_clk 0xfd82abad +#define clk_gcc_hmss_dvm_bus_clk 0x17cc8b53 +#define clk_gcc_hmss_rbcpr_clk 0x699183be +#define clk_hmss_gpll0_clk_src 0x17eb05d0 +#define clk_hmss_gpll4_clk_src 0x20456cae +#define clk_gcc_mmss_sys_noc_axi_clk 0x4467b15b +#define clk_gcc_mss_at_clk 0x1692c5aa +#define clk_nav_gcc_dbg_clk 0x2221c544 +#define clk_gcc_pcie_0_aux_clk 0x3d2e3ece +#define clk_gcc_pcie_0_cfg_ahb_clk 0x4dd325c3 +#define clk_gcc_pcie_0_mstr_axi_clk 0x3f85285b +#define clk_gcc_pcie_0_pipe_clk 0x4f37621e +#define clk_gcc_pcie_0_slv_axi_clk 0xd69638a1 +#define clk_gcc_pcie_phy_aux_clk 0x4746e74f +#define clk_gcc_pdm2_clk 0x99d55711 +#define clk_gcc_pdm_ahb_clk 0x365664f6 +#define clk_gcc_prng_ahb_clk 0x397e7eaa +#define clk_gcc_sdcc2_ahb_clk 0x23d5727f +#define clk_gcc_sdcc2_apps_clk 0x861b20ac +#define clk_gcc_sdcc4_ahb_clk 0x64f3e6a8 +#define clk_gcc_sdcc4_apps_clk 0xbf7c4dc8 +#define clk_gcc_tsif_ahb_clk 0x88d2822c +#define clk_gcc_tsif_ref_clk 0x8f1ed2c2 +#define clk_gcc_ufs_ahb_clk 0x1914bb84 +#define clk_gcc_ufs_axi_clk 0x47c743a7 +#define clk_gcc_ufs_axi_hw_ctl_clk 0x69385b45 +#define clk_gcc_ufs_ice_core_clk 0x310b0710 +#define clk_gcc_ufs_ice_core_hw_ctl_clk 0x84e15a5b +#define clk_gcc_ufs_phy_aux_clk 0x17acc8fb +#define clk_gcc_ufs_phy_aux_hw_ctl_clk 0x7dbdb2e2 +#define clk_gcc_ufs_rx_symbol_0_clk 0x7f43251c +#define clk_gcc_ufs_rx_symbol_1_clk 0x03182fde +#define clk_gcc_ufs_tx_symbol_0_clk 0x6a9f747a +#define clk_ufs_tx_symbol_0_clk 0xb3fcd0f7 +#define clk_ufs_rx_symbol_0_clk 0x17a0f1cd +#define clk_gcc_ufs_unipro_core_clk 0x2daf7fd2 +#define clk_gcc_ufs_unipro_core_hw_ctl_clk 0x4a4e0f3d +#define clk_gcc_usb30_master_clk 0xb3b4e2cb +#define clk_gcc_usb30_mock_utmi_clk 0xa800b65a +#define clk_gcc_usb30_sleep_clk 0xd0b65c92 +#define clk_gcc_usb3_phy_aux_clk 0x0d9a36e0 +#define clk_gcc_usb3_phy_pipe_clk 0xf279aff2 +#define clk_gcc_usb3_clkref_clk 0xb6cc8f00 +#define clk_gcc_hdmi_clkref_clk 0x4d4eec04 +#define clk_gcc_edp_clkref_clk 0xa8685c3f +#define clk_gcc_ufs_clkref_clk 0x92aa126f +#define clk_gcc_pcie_clkref_clk 0xa2e247fa +#define clk_gcc_rx2_qlink_clkref_clk 0xd0ba986d +#define clk_gcc_rx1_usb2_clkref_clk 0x53351d25 +#define clk_gcc_pcie_phy_reset 0x9bc3c959 +#define clk_gcc_pcie_phy_com_reset 0x8bf513e6 +#define clk_gcc_pcie_phy_nocsr_com_phy_reset 0x0c16a2da +#define clk_gcc_qusb2phy_prim_reset 0x07550fa1 +#define clk_gcc_qusb2phy_sec_reset 0x3f3a87d0 +#define clk_gcc_mmss_noc_cfg_ahb_clk 0xb41a9d99 +#define clk_gcc_dcc_ahb_clk 0xfa14a88c +#define clk_hlos1_vote_lpass_core_smmu_clk 0x3aaa1743 +#define clk_hlos1_vote_lpass_adsp_smmu_clk 0xc76f702f +#define clk_gcc_mss_cfg_ahb_clk 0x111cde81 +#define clk_gcc_mss_q6_bimc_axi_clk 0x67544d62 +#define clk_gcc_mss_mnoc_bimc_axi_clk 0xf665d03f +#define clk_gpll0_out_msscc 0x7d794829 +#define clk_gcc_mss_snoc_axi_clk 0x0e71de85 +#define clk_gcc_qspi_ref_clk 0x766a0f7c +#define clk_gcc_qspi_ahb_clk 0x96969dc8 +#define clk_gcc_debug_mux 0x8121ac15 + +/* clock_mmss controlled clocks */ +#define clk_mmsscc_xo 0x05e63704 +#define clk_mmsscc_gpll0 0xe900c515 +#define clk_mmsscc_gpll0_div 0x73892e05 +#define clk_mmpll0_pll 0x361e3cfd +#define clk_mmpll1_pll 0x198e426b +#define clk_mmpll3_pll 0x18c76899 +#define clk_mmpll4_pll 0x22c063c1 +#define clk_mmpll5_pll 0xa41e1936 +#define clk_mmpll6_pll 0xc56fb440 +#define clk_mmpll7_pll 0x3ac216af +#define clk_mmpll10_pll 0x2561263b +#define clk_mmpll0_pll_out 0x1e9e24a8 +#define clk_mmpll1_pll_out 0x5fa32257 +#define clk_mmpll3_pll_out 0x6eb6328f +#define clk_mmpll4_pll_out 0xfb21c2fd +#define clk_mmpll5_pll_out 0xcc1897bf +#define clk_mmpll6_pll_out 0xfb1060bd +#define clk_mmpll7_pll_out 0x767758ed +#define clk_mmpll10_pll_out 0x3c5668f3 +#define clk_ahb_clk_src 0x86f49203 +#define clk_csi0_clk_src 0x227e65bc +#define clk_vfe0_clk_src 0xa0c2bd8f +#define clk_vfe1_clk_src 0x4e357366 +#define clk_mdp_clk_src 0x6dc1f8f1 +#define clk_maxi_clk_src 0x52c09777 +#define clk_cpp_clk_src 0x8382f56d +#define clk_jpeg0_clk_src 0x9a0a0ac3 +#define clk_rot_clk_src 0xce49b56c +#define clk_video_core_clk_src 0x8be4c944 +#define clk_csi1_clk_src 0x6a2a6c36 +#define clk_csi2_clk_src 0x4113589f +#define clk_csi3_clk_src 0xfd934012 +#define clk_fd_core_clk_src 0xe4799ab7 +#define clk_ext_dp_phy_pll_vco 0x441b576b +#define clk_ext_dp_phy_pll_link 0xea12644c +#define clk_dp_link_clk_src 0x370d0626 +#define clk_dp_crypto_clk_src 0xf8faa811 +#define clk_dp_pixel_clk_src 0xf5dfbabf +#define clk_ext_extpclk_clk_src 0xe5b273af +#define clk_ext_pclk0_clk_src 0x087c1612 +#define clk_ext_pclk1_clk_src 0x8067c5a3 +#define clk_pclk0_clk_src 0xccac1f35 +#define clk_pclk1_clk_src 0x090f68ac +#define clk_video_subcore0_clk_src 0x88d79636 +#define clk_video_subcore1_clk_src 0x4966930c +#define clk_cci_clk_src 0x822f3d97 +#define clk_camss_gp0_clk_src 0x43b063e9 +#define clk_camss_gp1_clk_src 0xa3315f1b +#define clk_mclk0_clk_src 0x266b3853 +#define clk_mclk1_clk_src 0xa73cad0c +#define clk_mclk2_clk_src 0x42545468 +#define clk_mclk3_clk_src 0x2bfbb714 +#define clk_csiphy_clk_src 0x8cceb70a +#define clk_csi0phytimer_clk_src 0xc8a309be +#define clk_csi1phytimer_clk_src 0x7c0fe23a +#define clk_csi2phytimer_clk_src 0x62ffea9c +#define clk_ext_byte0_clk_src 0xfb32f31e +#define clk_ext_byte1_clk_src 0x585ef6d4 +#define clk_byte0_clk_src 0x75cc885b +#define clk_byte1_clk_src 0x63c2c955 +#define clk_dp_aux_clk_src 0x2b6e972b +#define clk_dp_gtc_clk_src 0xc5a86a42 +#define clk_esc0_clk_src 0xb41d7c38 +#define clk_esc1_clk_src 0x3b0afa42 +#define clk_extpclk_clk_src 0xb2c31abd +#define clk_hdmi_clk_src 0xb40aeea9 +#define clk_vsync_clk_src 0xecb43940 +#define clk_mmss_bimc_smmu_ahb_clk 0x4825baf4 +#define clk_mmss_bimc_smmu_axi_clk 0xc365ac39 +#define clk_mmss_snoc_dvm_axi_clk 0x2c159a11 +#define clk_mmss_camss_ahb_clk 0xa51f2c1d +#define clk_mmss_camss_cci_ahb_clk 0xfda8bb6a +#define clk_mmss_camss_cci_clk 0x71bb5c97 +#define clk_mmss_camss_cpp_ahb_clk 0xd5554f15 +#define clk_mmss_camss_cpp_clk 0x8e99ef57 +#define clk_mmss_camss_cpp_axi_clk 0xd84e390b +#define clk_mmss_camss_cpp_vbif_ahb_clk 0x1b33a88e +#define clk_mmss_camss_cphy_csid0_clk 0x56114361 +#define clk_mmss_camss_csi0_ahb_clk 0x2b58d241 +#define clk_mmss_camss_csi0_clk 0xccfe39ef +#define clk_mmss_camss_csi0pix_clk 0x9e26509d +#define clk_mmss_camss_csi0rdi_clk 0x01d5bf83 +#define clk_mmss_camss_cphy_csid1_clk 0x79fbcd8a +#define clk_mmss_camss_csi1_ahb_clk 0x7073244b +#define clk_mmss_camss_csi1_clk 0x3eeeaac0 +#define clk_mmss_camss_csi1pix_clk 0xf1375139 +#define clk_mmss_camss_csi1rdi_clk 0x43185024 +#define clk_mmss_camss_cphy_csid2_clk 0xf295e3ef +#define clk_mmss_camss_csi2_ahb_clk 0x681c1479 +#define clk_mmss_camss_csi2_clk 0x94524569 +#define clk_mmss_camss_csi2pix_clk 0xf4de617d +#define clk_mmss_camss_csi2rdi_clk 0x4bf01dc5 +#define clk_mmss_camss_cphy_csid3_clk 0x100188e9 +#define clk_mmss_camss_csi3_ahb_clk 0xfae7c29b +#define clk_mmss_camss_csi3_clk 0x55e4bbae +#define clk_mmss_camss_csi3pix_clk 0xc166a015 +#define clk_mmss_camss_csi3rdi_clk 0x6983a4cd +#define clk_mmss_camss_csi_vfe0_clk 0x3b30b798 +#define clk_mmss_camss_csi_vfe1_clk 0xfe729af7 +#define clk_mmss_camss_csiphy0_clk 0x96c81af8 +#define clk_mmss_camss_csiphy1_clk 0xee9ac2bb +#define clk_mmss_camss_csiphy2_clk 0x3365e70e +#define clk_mmss_fd_ahb_clk 0x4ff1da4d +#define clk_mmss_fd_core_clk 0x749e7eb0 +#define clk_mmss_fd_core_uar_clk 0x8ea480c5 +#define clk_mmss_camss_gp0_clk 0x3f7f6c87 +#define clk_mmss_camss_gp1_clk 0xdccdd730 +#define clk_mmss_camss_ispif_ahb_clk 0xbda4f0e3 +#define clk_mmss_camss_jpeg0_clk 0x4cc73b07 +#define clk_mmss_camss_jpeg0_vote_clk 0xc9efa6ac +#define clk_mmss_camss_jpeg0_dma_vote_clk 0x371ec109 +#define clk_mmss_camss_jpeg_ahb_clk 0xde1fece3 +#define clk_mmss_camss_jpeg_axi_clk 0x7534616b +#define clk_mmss_camss_mclk0_clk 0x056293a7 +#define clk_mmss_camss_mclk1_clk 0x96c7b69b +#define clk_mmss_camss_mclk2_clk 0x8820556e +#define clk_mmss_camss_mclk3_clk 0xf90ffb67 +#define clk_mmss_camss_micro_ahb_clk 0x6c6fd3c7 +#define clk_mmss_camss_csi0phytimer_clk 0x7a78864e +#define clk_mmss_camss_csi1phytimer_clk 0x6e6c1de5 +#define clk_mmss_camss_csi2phytimer_clk 0x0235e2de +#define clk_mmss_camss_top_ahb_clk 0x120618d6 +#define clk_mmss_camss_vfe0_ahb_clk 0x137bd0bd +#define clk_mmss_camss_vfe0_clk 0xead28288 +#define clk_mmss_camss_vfe0_stream_clk 0xa0428287 +#define clk_mmss_camss_vfe1_ahb_clk 0xac0154c0 +#define clk_mmss_camss_vfe1_clk 0xc216b14d +#define clk_mmss_camss_vfe1_stream_clk 0x745af3b6 +#define clk_mmss_camss_vfe_vbif_ahb_clk 0x0109a9c6 +#define clk_mmss_camss_vfe_vbif_axi_clk 0xe626d8a1 +#define clk_mmss_mdss_ahb_clk 0x85d37ab5 +#define clk_mmss_mdss_axi_clk 0xdf04fc1d +#define clk_mmss_mdss_byte0_clk 0x38105d25 +#define clk_mmss_mdss_byte0_intf_clk 0x38e5aa79 +#define clk_mmss_mdss_byte0_intf_div_clk 0x8604f181 +#define clk_mmss_mdss_byte1_clk 0xe0c21354 +#define clk_mmss_mdss_byte1_intf_clk 0xcf654d8e +#define clk_mmss_mdss_byte1_intf_div_clk 0xcdf334c5 +#define clk_mmss_mdss_dp_aux_clk 0x23125eb6 +#define clk_mmss_mdss_dp_crypto_clk 0x9a072d4e +#define clk_mmss_mdss_dp_link_clk 0x8dd302d1 +#define clk_mmss_mdss_dp_link_intf_clk 0x70e386e6 +#define clk_mmss_mdss_dp_pixel_clk 0xb707b765 +#define clk_mmss_mdss_dp_gtc_clk 0xb59c151a +#define clk_mmss_mdss_esc0_clk 0x5721ff83 +#define clk_mmss_mdss_esc1_clk 0xc3d0376b +#define clk_mmss_mdss_extpclk_clk 0x74d5a954 +#define clk_mmss_mdss_hdmi_clk 0x28460a6d +#define clk_mmss_mdss_hdmi_dp_ahb_clk 0x5448519f +#define clk_mmss_mdss_mdp_clk 0x43539b0e +#define clk_mmss_mdss_mdp_lut_clk 0x00627b2b +#define clk_mmss_mdss_pclk0_clk 0xcc0e909d +#define clk_mmss_mdss_pclk1_clk 0x850d9146 +#define clk_mmss_mdss_rot_clk 0xbb7e71c4 +#define clk_mmss_mdss_vsync_clk 0x629b36dc +#define clk_mmss_misc_ahb_clk 0xea30b0e7 +#define clk_mmss_misc_cxo_clk 0xe620cd80 +#define clk_mmss_mnoc_ahb_clk 0x49a394f4 +#define clk_mmss_mnoc_maxi_clk 0xd8b7278f +#define clk_mmss_video_subcore0_clk 0x23fae359 +#define clk_mmss_video_subcore1_clk 0x5213a0c7 +#define clk_mmss_video_ahb_clk 0x94334ae9 +#define clk_mmss_video_axi_clk 0xf3178ba5 +#define clk_mmss_video_core_clk 0x78f14c85 +#define clk_mmss_video_maxi_clk 0x1785ef88 +#define clk_mmss_vmem_ahb_clk 0x4b18955b +#define clk_mmss_vmem_maxi_clk 0xb6067889 +#define clk_mmss_debug_mux 0xe646ffda + +/* external multimedia clocks */ +#define clk_dsi0pll_byteclk_mux 0xecf2c434 +#define clk_dsi0pll_byteclk_src 0x6f6f740f +#define clk_dsi0pll_pclk_mux 0x6c9da335 +#define clk_dsi0pll_pclk_src 0x5efd85d4 +#define clk_dsi0pll_pclk_src_mux 0x84b14663 +#define clk_dsi0pll_post_bit_div 0xf46dcf27 +#define clk_dsi0pll_pll_out_div1 0xeda5b7fe +#define clk_dsi0pll_pll_out_div2 0x97fa476d +#define clk_dsi0pll_pll_out_div4 0x90a98ce0 +#define clk_dsi0pll_pll_out_div8 0x9d9d85cf +#define clk_dsi0pll_pll_out_mux 0x179c27ca +#define clk_dsi0pll_post_vco_mux 0xfaf9bd1f +#define clk_dsi0pll_post_vco_div1 0xabb50b2a +#define clk_dsi0pll_post_vco_div4 0xbe51c091 +#define clk_dsi0pll_bitclk_src 0x36c3c437 +#define clk_dsi0pll_vco_clk 0x15940d40 + +#define clk_dsi1pll_byteclk_mux 0x14e2f38f +#define clk_dsi1pll_byteclk_src 0x4b65c298 +#define clk_dsi1pll_pclk_mux 0x4c0518b5 +#define clk_dsi1pll_pclk_src 0xeddcd80e +#define clk_dsi1pll_pclk_src_mux 0x3651feb3 +#define clk_dsi1pll_post_bit_div 0x712f0260 +#define clk_dsi1pll_pll_out_div8 0x87628ddb +#define clk_dsi1pll_pll_out_div4 0x0d9a384b +#define clk_dsi1pll_pll_out_div2 0x0c9b5748 +#define clk_dsi1pll_pll_out_div1 0x3193164e +#define clk_dsi1pll_pll_out_mux 0x171bf8fd +#define clk_dsi1pll_post_vco_mux 0xc6a90d20 +#define clk_dsi1pll_post_vco_div1 0x6f47ca7d +#define clk_dsi1pll_post_vco_div4 0x90628974 +#define clk_dsi1pll_bitclk_src 0x13ab045b +#define clk_dsi1pll_vco_clk 0x99797b50 + +#define clk_dp_vco_clk 0xfcaaeec7 +#define clk_dp_link_2x_clk_divsel_five 0xcfe3f5dd +#define clk_vco_divsel_four_clk_src 0xe0da19c0 +#define clk_vco_divsel_two_clk_src 0xb5cfc6a8 +#define clk_vco_divided_clk_src_mux 0x3f8197c2 +#define clk_hdmi_vco_clk 0xbb7dc20d + +/* clock_gpu controlled clocks*/ +#define clk_gpucc_xo 0xc4e1a890 +#define clk_gpucc_gpll0 0x0db0e37f +#define clk_gfx3d_clk_src 0x917f76ef +#define clk_rbbmtimer_clk_src 0x17649ecc +#define clk_gfx3d_isense_clk_src 0xecc3eafa +#define clk_rbcpr_clk_src 0x2c2e9af2 +#define clk_gpu_debug_div_clk 0x75d6f53f +#define clk_gpucc_gfx3d_clk 0x95f01bd5 +#define clk_gpucc_rbbmtimer_clk 0x58a0a7ca +#define clk_gpucc_gfx3d_isense_clk 0xb2678e80 +#define clk_gpucc_cxo_clk 0x6532dcae +#define clk_gpucc_rbcpr_clk 0x7bd750e8 +#define clk_gpu_pll0_pll 0x0e61ab4d +#define clk_gpu_pll0_pll_out_even 0xb0ed5009 +#define clk_gpu_pll0_pll_out_odd 0x08c5a8a5 +#define clk_gpu_pll0_postdiv_clk 0x76c19f3c +#define clk_gpucc_mx_clk 0x1edbb879 +#define clk_gpucc_gcc_dbg_clk 0x9ae8cd3c +#define clk_gfxcc_dbg_clk 0x3ed47625 + +/* CPU clocks */ +#define clk_pwrcl_clk 0xc554130e +#define clk_perfcl_clk 0x58869997 +#define clk_sys_apcsaux_clk_gcc 0xf905e862 +#define clk_xo_ao 0x428c856d +#define clk_osm_clk_src 0xaabe68c3 +#define clk_cpu_debug_mux 0x3ae8bcb2 + +/* Audio External Clocks */ +#define clk_audio_ap_clk 0x9b5727cb +#define clk_audio_pmi_clk 0xcbfe416d +#define clk_audio_ap_clk2 0x454d1e91 + +/* GCC block resets */ +#define QUSB2PHY_PRIM_BCR 0 +#define QUSB2PHY_SEC_BCR 1 +#define BLSP1_BCR 2 +#define BLSP2_BCR 3 +#define BOOT_ROM_BCR 4 +#define PRNG_BCR 5 +#define UFS_BCR 6 +#define USB_30_BCR 7 +#define USB3_PHY_BCR 8 +#define USB3PHY_PHY_BCR 9 +#define PCIE_0_PHY_BCR 10 +#define PCIE_PHY_BCR 11 +#define PCIE_PHY_COM_BCR 12 +#define PCIE_PHY_NOCSR_COM_PHY_BCR 13 + +/* MMSS block resets */ +#define CAMSS_MICRO_BCR 0 + +#endif --- /dev/null 2019-10-24 16:47:25.704025805 +0200 +++ linux-4.4.115-fbx/arch/cris/boot/dts/include/dt-bindings/clock/msm-clocks-hwio-8998.h 2019-01-22 16:16:28.171288678 +0100 @@ -0,0 +1,395 @@ +/* Copyright (c) 2015-2017, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define CLKFLAG_NO_RATE_CACHE 0x00004000 + +#define FMAX_LOWER 0 +#define FMAX_LOW 1 +#define FMAX_NOM 2 +#define FMAX_TURBO 3 + +#define HALT_CHECK_DELAY 5 + +#define RPM_MISC_CLK_TYPE 0x306b6c63 +#define RPM_BUS_CLK_TYPE 0x316b6c63 +#define RPM_MEM_CLK_TYPE 0x326b6c63 +#define RPM_IPA_CLK_TYPE 0x617069 +#define RPM_CE_CLK_TYPE 0x6563 +#define RPM_AGGR_CLK_TYPE 0x72676761 +#define RPM_SMD_KEY_ENABLE 0x62616E45 +#define RPM_MMAXI_CLK_TYPE 0x69786d6d + +#define CXO_CLK_SRC_ID 0x0 +#define QDSS_CLK_ID 0x1 +#define SNOC_CLK_ID 0x1 +#define CNOC_CLK_ID 0x2 +#define CNOC_PERIPH_CLK_ID 0x0 +#define BIMC_CLK_ID 0x0 +#define IPA_CLK_ID 0x0 +#define CE1_CLK_ID 0x0 +#define RF_CLK1_ID 0x4 +#define RF_CLK2_ID 0x5 +#define RF_CLK3_ID 0x6 +#define LN_BB_CLK1_ID 0x1 +#define LN_BB_CLK2_ID 0x2 +#define LN_BB_CLK3_ID 0x3 +#define DIV_CLK1_ID 0xb +#define DIV_CLK2_ID 0xc +#define DIV_CLK3_ID 0xd +#define RF_CLK1_PIN_ID 0x4 +#define RF_CLK2_PIN_ID 0x5 +#define RF_CLK3_PIN_ID 0x6 +#define LN_BB_CLK1_PIN_ID 0x1 +#define LN_BB_CLK2_PIN_ID 0x2 +#define LN_BB_CLK3_PIN_ID 0x3 +#define AGGR1_NOC_ID 0x1 +#define AGGR2_NOC_ID 0x2 +#define MMSSNOC_AXI_CLK_ID 0x0 + +#define APCS_COMMON_LMH_CMD_RCGR 0x0012C + +#define GCC_APCS_GPLL_ENA_VOTE 0x52000 +#define GCC_APCS_CLOCK_BRANCH_ENA_VOTE 0x52004 +#define GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1 0x5200C +#define PLLTEST_PAD_CFG 0x6200C +#define GCC_XO_DIV4_CBCR 0x43008 +#define CLOCK_FRQ_MEASURE_CTL 0x62004 +#define CLOCK_FRQ_MEASURE_STATUS 0x62008 +#define GCC_GPLL0_MODE 0x00000 +#define GCC_GPLL4_MODE 0x77000 +#define GCC_USB30_MASTER_CMD_RCGR 0x0F014 +#define GCC_PCIE_AUX_CMD_RCGR 0x6C000 +#define GCC_UFS_AXI_CMD_RCGR 0x75018 +#define GCC_BLSP1_QUP1_I2C_APPS_CMD_RCGR 0x19020 +#define GCC_BLSP1_QUP1_SPI_APPS_CMD_RCGR 0x1900C +#define GCC_BLSP1_QUP2_I2C_APPS_CMD_RCGR 0x1B020 +#define GCC_BLSP1_QUP2_SPI_APPS_CMD_RCGR 0x1B00C +#define GCC_BLSP1_QUP3_I2C_APPS_CMD_RCGR 0x1D020 +#define GCC_BLSP1_QUP3_SPI_APPS_CMD_RCGR 0x1D00C +#define GCC_BLSP1_QUP4_I2C_APPS_CMD_RCGR 0x1F020 +#define GCC_BLSP1_QUP4_SPI_APPS_CMD_RCGR 0x1F00C +#define GCC_BLSP1_QUP5_I2C_APPS_CMD_RCGR 0x21020 +#define GCC_BLSP1_QUP5_SPI_APPS_CMD_RCGR 0x2100C +#define GCC_BLSP1_QUP6_I2C_APPS_CMD_RCGR 0x23020 +#define GCC_BLSP1_QUP6_SPI_APPS_CMD_RCGR 0x2300C +#define GCC_BLSP1_UART1_APPS_CMD_RCGR 0x1A00C +#define GCC_BLSP1_UART2_APPS_CMD_RCGR 0x1C00C +#define GCC_BLSP1_UART3_APPS_CMD_RCGR 0x1E00C +#define GCC_BLSP2_QUP1_I2C_APPS_CMD_RCGR 0x26020 +#define GCC_BLSP2_QUP2_I2C_APPS_CMD_RCGR 0x28020 +#define GCC_BLSP2_QUP3_I2C_APPS_CMD_RCGR 0x2A020 +#define GCC_BLSP2_QUP4_I2C_APPS_CMD_RCGR 0x2C020 +#define GCC_BLSP2_QUP5_I2C_APPS_CMD_RCGR 0x2E020 +#define GCC_BLSP2_QUP6_I2C_APPS_CMD_RCGR 0x30020 +#define GCC_BLSP2_QUP1_SPI_APPS_CMD_RCGR 0x2600C +#define GCC_BLSP2_QUP2_SPI_APPS_CMD_RCGR 0x2800C +#define GCC_BLSP2_QUP3_SPI_APPS_CMD_RCGR 0x2A00C +#define GCC_BLSP2_QUP4_SPI_APPS_CMD_RCGR 0x2C00C +#define GCC_BLSP2_QUP5_SPI_APPS_CMD_RCGR 0x2E00C +#define GCC_BLSP2_QUP6_SPI_APPS_CMD_RCGR 0x3000C +#define GCC_BLSP2_UART1_APPS_CMD_RCGR 0x2700C +#define GCC_BLSP2_UART2_APPS_CMD_RCGR 0x2900C +#define GCC_BLSP2_UART3_APPS_CMD_RCGR 0x2B00C +#define GCC_GP1_CMD_RCGR 0x64004 +#define GCC_GP2_CMD_RCGR 0x65004 +#define GCC_GP3_CMD_RCGR 0x66004 +#define GCC_HMSS_RBCPR_CMD_RCGR 0x48044 +#define GCC_PDM2_CMD_RCGR 0x33010 +#define GCC_SDCC2_APPS_CMD_RCGR 0x14010 +#define GCC_SDCC4_APPS_CMD_RCGR 0x16010 +#define GCC_TSIF_REF_CMD_RCGR 0x36010 +#define GCC_UFS_ICE_CORE_CMD_RCGR 0x76010 +#define GCC_UFS_PHY_AUX_CMD_RCGR 0x76044 +#define GCC_UFS_UNIPRO_CORE_CMD_RCGR 0x76028 +#define GCC_USB30_MOCK_UTMI_CMD_RCGR 0x0F028 +#define GCC_USB3_PHY_AUX_CMD_RCGR 0x5000C +#define GCC_QSPI_REF_CMD_RCGR 0x9000C +#define GCC_PCIE_0_PHY_BCR 0x6C01C +#define GCC_HDMI_CLKREF_EN 0x88000 +#define GCC_UFS_CLKREF_EN 0x88004 +#define GCC_USB3_CLKREF_EN 0x88008 +#define GCC_PCIE_CLKREF_EN 0x8800C +#define GCC_RX1_USB2_CLKREF_EN 0x88014 +#define GCC_USB3_PHY_BCR 0x50020 +#define GCC_AGGRE1_NOC_XO_CBCR 0x8202C +#define GCC_AGGRE1_UFS_AXI_CBCR 0x82028 +#define GCC_AGGRE1_USB3_AXI_CBCR 0x82024 +#define GCC_BIMC_MSS_Q6_AXI_CBCR 0x4401C +#define GCC_BLSP1_AHB_CBCR 0x17004 +#define GCC_BLSP1_BCR 0x17000 +#define GCC_BLSP1_QUP1_SPI_APPS_CBCR 0x19004 +#define GCC_BLSP1_QUP1_I2C_APPS_CBCR 0x19008 +#define GCC_BLSP1_QUP2_SPI_APPS_CBCR 0x1B004 +#define GCC_BLSP1_QUP2_I2C_APPS_CBCR 0x1B008 +#define GCC_BLSP1_QUP3_SPI_APPS_CBCR 0x1D004 +#define GCC_BLSP1_QUP3_I2C_APPS_CBCR 0x1D008 +#define GCC_BLSP1_QUP4_SPI_APPS_CBCR 0x1F004 +#define GCC_BLSP1_QUP4_I2C_APPS_CBCR 0x1F008 +#define GCC_BLSP1_QUP5_SPI_APPS_CBCR 0x21004 +#define GCC_BLSP1_QUP5_I2C_APPS_CBCR 0x21008 +#define GCC_BLSP1_QUP6_SPI_APPS_CBCR 0x23004 +#define GCC_BLSP1_QUP6_I2C_APPS_CBCR 0x23008 +#define GCC_BLSP1_UART1_APPS_CBCR 0x1A004 +#define GCC_BLSP1_UART2_APPS_CBCR 0x1C004 +#define GCC_BLSP1_UART3_APPS_CBCR 0x1E004 +#define GCC_BLSP2_AHB_CBCR 0x25004 +#define GCC_BLSP2_BCR 0x25000 +#define GCC_BLSP2_QUP1_SPI_APPS_CBCR 0x26004 +#define GCC_BLSP2_QUP1_I2C_APPS_CBCR 0x26008 +#define GCC_BLSP2_QUP2_I2C_APPS_CBCR 0x28008 +#define GCC_BLSP2_QUP2_SPI_APPS_CBCR 0x28004 +#define GCC_BLSP2_QUP3_SPI_APPS_CBCR 0x2A004 +#define GCC_BLSP2_QUP3_I2C_APPS_CBCR 0x2A008 +#define GCC_BLSP2_QUP4_SPI_APPS_CBCR 0x2C004 +#define GCC_BLSP2_QUP4_I2C_APPS_CBCR 0x2C008 +#define GCC_BLSP2_QUP5_SPI_APPS_CBCR 0x2E004 +#define GCC_BLSP2_QUP5_I2C_APPS_CBCR 0x2E008 +#define GCC_BLSP2_QUP6_SPI_APPS_CBCR 0x30004 +#define GCC_BLSP2_QUP6_I2C_APPS_CBCR 0x30008 +#define GCC_BLSP2_UART1_APPS_CBCR 0x27004 +#define GCC_BLSP2_UART2_APPS_CBCR 0x29004 +#define GCC_BLSP2_UART3_APPS_CBCR 0x2B004 +#define GCC_BOOT_ROM_AHB_CBCR 0x38004 +#define GCC_BOOT_ROM_BCR 0x38000 +#define GCC_CFG_NOC_USB3_AXI_CBCR 0x05018 +#define GCC_BIMC_GFX_CBCR 0x46040 +#define GCC_GP1_CBCR 0x64000 +#define GCC_GP2_CBCR 0x65000 +#define GCC_GP3_CBCR 0x66000 +#define GCC_GPU_BIMC_GFX_CBCR 0x71010 +#define GCC_GPU_CFG_AHB_CBCR 0x71004 +#define GCC_GPU_IREF_EN 0x88010 +#define GCC_HMSS_DVM_BUS_CBCR 0x4808C +#define GCC_HMSS_RBCPR_CBCR 0x48008 +#define GCC_MMSS_SYS_NOC_AXI_CBCR 0x09000 +#define GCC_MMSS_NOC_CFG_AHB_CBCR 0x09004 +#define GCC_PCIE_0_SLV_AXI_CBCR 0x6B008 +#define GCC_PCIE_0_MSTR_AXI_CBCR 0x6B00C +#define GCC_PCIE_0_CFG_AHB_CBCR 0x6B010 +#define GCC_PCIE_0_AUX_CBCR 0x6B014 +#define GCC_PCIE_0_PIPE_CBCR 0x6B018 +#define GCC_PCIE_PHY_AUX_CBCR 0x6F004 +#define GCC_PCIE_PHY_BCR 0x6F000 +#define GCC_PCIE_PHY_COM_BCR 0x6F014 +#define GCC_PCIE_PHY_NOCSR_COM_PHY_BCR 0x6F00C +#define GCC_QUSB2PHY_PRIM_BCR 0x12000 +#define GCC_QUSB2PHY_SEC_BCR 0x12004 +#define GCC_PDM2_CBCR 0x3300C +#define GCC_PDM_AHB_CBCR 0x33004 +#define GCC_PRNG_AHB_CBCR 0x34004 +#define GCC_PRNG_BCR 0x34000 +#define GCC_SDCC2_APPS_CBCR 0x14004 +#define GCC_SDCC2_AHB_CBCR 0x14008 +#define GCC_SDCC4_APPS_CBCR 0x16004 +#define GCC_SDCC4_AHB_CBCR 0x16008 +#define GCC_TSIF_AHB_CBCR 0x36004 +#define GCC_TSIF_REF_CBCR 0x36008 +#define GCC_UFS_AXI_CBCR 0x75008 +#define GCC_UFS_BCR 0x75000 +#define GCC_UFS_AHB_CBCR 0x7500C +#define GCC_UFS_TX_SYMBOL_0_CBCR 0x75010 +#define GCC_UFS_RX_SYMBOL_0_CBCR 0x75014 +#define GCC_UFS_RX_SYMBOL_1_CBCR 0x7605C +#define GCC_UFS_UNIPRO_CORE_CBCR 0x76008 +#define GCC_UFS_ICE_CORE_CBCR 0x7600C +#define GCC_UFS_PHY_AUX_CBCR 0x76040 +#define GCC_USB30_MASTER_CBCR 0x0F008 +#define GCC_USB30_SLEEP_CBCR 0x0F00C +#define GCC_USB30_MOCK_UTMI_CBCR 0x0F010 +#define GCC_USB_30_BCR 0x0F000 +#define GCC_USB3_PHY_AUX_CBCR 0x50000 +#define GCC_USB3_PHY_PIPE_CBCR 0x50004 +#define GCC_USB3PHY_PHY_BCR 0x50024 +#define GCC_APCS_CLOCK_SLEEP_ENA_VOTE 0x52008 +#define GCC_MSS_CFG_AHB_CBCR 0x8A000 +#define GCC_MSS_Q6_BIMC_AXI_CBCR 0x8A040 +#define GCC_MSS_MNOC_BIMC_AXI_CBCR 0x8A004 +#define GCC_MSS_SNOC_AXI_CBCR 0x8A03C +#define GCC_HMSS_GPLL0_CMD_RCGR 0x4805C +#define GCC_MSS_CFG_AHB_CBCR 0x8A000 +#define GCC_MSS_Q6_BIMC_AXI_CBCR 0x8A040 +#define GCC_MSS_MNOC_BIMC_AXI_CBCR 0x8A004 +#define GCC_MSS_SNOC_AXI_CBCR 0x8A03C +#define GCC_DCC_AHB_CBCR 0x84004 +#define GCC_HLOS1_VOTE_LPASS_CORE_SMMU_CBCR 0x7D010 +#define GCC_HLOS1_VOTE_LPASS_ADSP_SMMU_CBCR 0x7D014 +#define GCC_QSPI_AHB_CBCR 0x90004 +#define GCC_QSPI_REF_CBCR 0x90008 +#define GCC_MMSS_MISC 0x0902C +#define GCC_GPU_MISC 0x71028 + +#define GPUCC_GPU_PLL0_PLL_MODE 0x00000 +#define GPUCC_GPU_PLL0_USER_CTL_MODE 0x0000C +#define GPUCC_GFX3D_CMD_RCGR 0x01070 +#define GPUCC_RBBMTIMER_CMD_RCGR 0x010B0 +#define GPUCC_GFX3D_ISENSE_CMD_RCGR 0x01100 +#define GPUCC_RBCPR_CMD_RCGR 0x01030 +#define GPUCC_GFX3D_CBCR 0x01098 +#define GPUCC_RBBMTIMER_CBCR 0x010D0 +#define GPUCC_GFX3D_ISENSE_CBCR 0x01124 +#define GPUCC_CXO_CBCR 0x01020 +#define GPUCC_RBCPR_CBCR 0x01054 +#define GPU_GX_BCR 0x01090 +#define GPUCC_GX_DOMAIN_MISC 0x00130 +#define GPUCC_GPU_DD_WRAP_CTRL 0x00430 +#define GPUCC_DEBUG_CLK_CTL 0x00120 + +#define MMSS_PLL_VOTE_APCS 0x001E0 +#define MMSS_MMPLL0_PLL_MODE 0x0C000 +#define MMSS_MMPLL1_PLL_MODE 0x0C050 +#define MMSS_MMPLL3_PLL_MODE 0x00000 +#define MMSS_MMPLL4_PLL_MODE 0x00050 +#define MMSS_MMPLL5_PLL_MODE 0x000A0 +#define MMSS_MMPLL6_PLL_MODE 0x000F0 +#define MMSS_MMPLL7_PLL_MODE 0x00140 +#define MMSS_MMPLL10_PLL_MODE 0x00190 +#define MMSS_AHB_CMD_RCGR 0x05000 +#define MMSS_CSI0_CMD_RCGR 0x03090 +#define MMSS_VFE0_CMD_RCGR 0x03600 +#define MMSS_VFE1_CMD_RCGR 0x03620 +#define MMSS_MDP_CMD_RCGR 0x02040 +#define MMSS_MAXI_CMD_RCGR 0x0F020 +#define MMSS_CPP_CMD_RCGR 0x03640 +#define MMSS_JPEG0_CMD_RCGR 0x03500 +#define MMSS_ROT_CMD_RCGR 0x021A0 +#define MMSS_VIDEO_CORE_CMD_RCGR 0x01000 +#define MMSS_CSI1_CMD_RCGR 0x03100 +#define MMSS_CSI2_CMD_RCGR 0x03160 +#define MMSS_CSI3_CMD_RCGR 0x031C0 +#define MMSS_FD_CORE_CMD_RCGR 0x03B00 +#define MMSS_BYTE0_CMD_RCGR 0x02120 +#define MMSS_BYTE1_CMD_RCGR 0x02140 +#define MMSS_PCLK0_CMD_RCGR 0x02000 +#define MMSS_PCLK1_CMD_RCGR 0x02020 +#define MMSS_VIDEO_SUBCORE0_CMD_RCGR 0x01060 +#define MMSS_VIDEO_SUBCORE1_CMD_RCGR 0x01080 +#define MMSS_CSIPHY_CMD_RCGR 0x03800 +#define MMSS_CCI_CMD_RCGR 0x03300 +#define MMSS_CAMSS_GP0_CMD_RCGR 0x03420 +#define MMSS_CAMSS_GP1_CMD_RCGR 0x03450 +#define MMSS_MCLK0_CMD_RCGR 0x03360 +#define MMSS_MCLK1_CMD_RCGR 0x03390 +#define MMSS_MCLK2_CMD_RCGR 0x033C0 +#define MMSS_MCLK3_CMD_RCGR 0x033F0 +#define MMSS_CAMSS_CSI2PHYTIMER_CBCR 0x03084 +#define MMSS_CSI0PHYTIMER_CMD_RCGR 0x03000 +#define MMSS_CSI1PHYTIMER_CMD_RCGR 0x03030 +#define MMSS_CSI2PHYTIMER_CMD_RCGR 0x03060 +#define MMSS_DP_GTC_CMD_RCGR 0x02280 +#define MMSS_ESC0_CMD_RCGR 0x02160 +#define MMSS_ESC1_CMD_RCGR 0x02180 +#define MMSS_EXTPCLK_CMD_RCGR 0x02060 +#define MMSS_HDMI_CMD_RCGR 0x02100 +#define MMSS_VSYNC_CMD_RCGR 0x02080 +#define MMSS_BIMC_SMMU_AHB_CBCR 0x0E004 +#define MMSS_BIMC_SMMU_AXI_CBCR 0x0E008 +#define MMSS_SNOC_DVM_AXI_CBCR 0x0E040 +#define MMSS_CAMSS_AHB_CBCR 0x0348C +#define MMSS_CAMSS_CCI_AHB_CBCR 0x03348 +#define MMSS_CAMSS_CCI_CBCR 0x03344 +#define MMSS_CAMSS_CPP_AHB_CBCR 0x036B4 +#define MMSS_CAMSS_CPP_CBCR 0x036B0 +#define MMSS_CAMSS_CPP_AXI_CBCR 0x036C4 +#define MMSS_CAMSS_CPP_VBIF_AHB_CBCR 0x036C8 +#define MMSS_CAMSS_CPHY_CSID0_CBCR 0x03730 +#define MMSS_CAMSS_CSI0_AHB_CBCR 0x030BC +#define MMSS_CAMSS_CSI0_CBCR 0x030B4 +#define MMSS_CAMSS_CSI0PIX_CBCR 0x030E4 +#define MMSS_CAMSS_CSI0RDI_CBCR 0x030D4 +#define MMSS_CAMSS_CPHY_CSID1_CBCR 0x03734 +#define MMSS_CAMSS_CSI1_AHB_CBCR 0x03128 +#define MMSS_CAMSS_CSI1_CBCR 0x03124 +#define MMSS_CAMSS_CSI1PIX_CBCR 0x03154 +#define MMSS_CAMSS_CSI1RDI_CBCR 0x03144 +#define MMSS_CAMSS_CPHY_CSID2_CBCR 0x03738 +#define MMSS_CAMSS_CSI2_AHB_CBCR 0x03188 +#define MMSS_CAMSS_CSI2_CBCR 0x03184 +#define MMSS_CAMSS_CSI2PIX_CBCR 0x031B4 +#define MMSS_CAMSS_CSI2RDI_CBCR 0x031A4 +#define MMSS_CAMSS_CPHY_CSID3_CBCR 0x0373C +#define MMSS_CAMSS_CSI3_AHB_CBCR 0x031E8 +#define MMSS_CAMSS_CSI3_CBCR 0x031E4 +#define MMSS_CAMSS_CSI3PIX_CBCR 0x03214 +#define MMSS_CAMSS_CSI3RDI_CBCR 0x03204 +#define MMSS_CAMSS_CSI_VFE0_CBCR 0x03704 +#define MMSS_CAMSS_CSI_VFE1_CBCR 0x03714 +#define MMSS_CAMSS_CSIPHY0_CBCR 0x03740 +#define MMSS_CAMSS_CSIPHY1_CBCR 0x03744 +#define MMSS_CAMSS_CSIPHY2_CBCR 0x03748 +#define MMSS_FD_AHB_CBCR 0x03B74 +#define MMSS_FD_CORE_CBCR 0x03B68 +#define MMSS_FD_CORE_UAR_CBCR 0x03B6C +#define MMSS_CAMSS_GP0_CBCR 0x03444 +#define MMSS_CAMSS_GP1_CBCR 0x03474 +#define MMSS_CAMSS_ISPIF_AHB_CBCR 0x03224 +#define MMSS_CAMSS_JPEG0_CBCR 0x035A8 +#define MMSS_CAMSS_JPEG_AHB_CBCR 0x035B4 +#define MMSS_CAMSS_JPEG_AXI_CBCR 0x035B8 +#define MMSS_CAMSS_MCLK0_CBCR 0x03384 +#define MMSS_CAMSS_MCLK1_CBCR 0x033B4 +#define MMSS_CAMSS_MCLK2_CBCR 0x033E4 +#define MMSS_CAMSS_MCLK3_CBCR 0x03414 +#define MMSS_CAMSS_MICRO_AHB_CBCR 0x03494 +#define MMSS_CAMSS_CSI0PHYTIMER_CBCR 0x03024 +#define MMSS_CAMSS_CSI1PHYTIMER_CBCR 0x03054 +#define MMSS_CSI2PHYTIMER_CMD_RCGR 0x03060 +#define MMSS_CAMSS_TOP_AHB_CBCR 0x03484 +#define MMSS_CAMSS_VFE0_AHB_CBCR 0x03668 +#define MMSS_CAMSS_VFE0_CBCR 0x036A8 +#define MMSS_CAMSS_VFE0_STREAM_CBCR 0x03720 +#define MMSS_CAMSS_VFE1_AHB_CBCR 0x03678 +#define MMSS_CAMSS_VFE1_CBCR 0x036AC +#define MMSS_CAMSS_VFE1_STREAM_CBCR 0x03724 +#define MMSS_CAMSS_VFE_VBIF_AHB_CBCR 0x036B8 +#define MMSS_CAMSS_VFE_VBIF_AXI_CBCR 0x036BC +#define MMSS_MDSS_AHB_CBCR 0x02308 +#define MMSS_MDSS_AXI_CBCR 0x02310 +#define MMSS_MDSS_BYTE0_CBCR 0x0233C +#define MMSS_MDSS_BYTE0_INTF_CBCR 0x02374 +#define MMSS_MDSS_BYTE0_INTF_DIV 0x0237C +#define MMSS_MDSS_BYTE1_CBCR 0x02340 +#define MMSS_MDSS_BYTE1_INTF_CBCR 0x02378 +#define MMSS_MDSS_BYTE1_INTF_DIV 0x02380 +#define MMSS_MDSS_DP_AUX_CBCR 0x02364 +#define MMSS_MDSS_DP_CRYPTO_CBCR 0x0235C +#define MMSS_MDSS_DP_GTC_CBCR 0x02368 +#define MMSS_MDSS_DP_LINK_CBCR 0x02354 +#define MMSS_MDSS_DP_LINK_INTF_CBCR 0x02358 +#define MMSS_MDSS_DP_PIXEL_CBCR 0x02360 +#define MMSS_MDSS_ESC0_CBCR 0x02344 +#define MMSS_MDSS_ESC1_CBCR 0x02348 +#define MMSS_MDSS_EXTPCLK_CBCR 0x02324 +#define MMSS_MDSS_HDMI_CBCR 0x02338 +#define MMSS_MDSS_HDMI_DP_AHB_CBCR 0x0230C +#define MMSS_MDSS_MDP_CBCR 0x0231C +#define MMSS_MDSS_MDP_LUT_CBCR 0x02320 +#define MMSS_MDSS_PCLK0_CBCR 0x02314 +#define MMSS_MDSS_PCLK1_CBCR 0x02318 +#define MMSS_MDSS_ROT_CBCR 0x02350 +#define MMSS_MDSS_VSYNC_CBCR 0x02328 +#define MMSS_MISC_AHB_CBCR 0x00328 +#define MMSS_MISC_CXO_CBCR 0x00324 +#define MMSS_MNOC_AHB_CBCR 0x05024 +#define MMSS_MNOC_MAXI_CBCR 0x0F004 +#define MMSS_VIDEO_SUBCORE0_CBCR 0x01048 +#define MMSS_VIDEO_SUBCORE1_CBCR 0x0104C +#define MMSS_VIDEO_AHB_CBCR 0x01030 +#define MMSS_VIDEO_AXI_CBCR 0x01034 +#define MMSS_VIDEO_CORE_CBCR 0x01028 +#define MMSS_VIDEO_MAXI_CBCR 0x01038 +#define MMSS_VMEM_AHB_CBCR 0x0F068 +#define MMSS_VMEM_MAXI_CBCR 0x0F064 +#define MMSS_DP_AUX_CMD_RCGR 0x02260 +#define MMSS_DP_CRYPTO_CMD_RCGR 0x02220 +#define MMSS_DP_LINK_CMD_RCGR 0x02200 +#define MMSS_DP_PIXEL_CMD_RCGR 0x02240 +#define MMSS_DEBUG_CLK_CTL 0x00900 diff -Nruw linux-4.4.115-fbx/arch/cris/boot/dts/include/dt-bindings/msm./msm-bus-ids.h linux-4.4.115-fbx/arch/cris/boot/dts/include/dt-bindings/msm/msm-bus-ids.h --- linux-4.4.115-fbx/arch/cris/boot/dts/include/dt-bindings/msm./msm-bus-ids.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-4.4.115-fbx/arch/cris/boot/dts/include/dt-bindings/msm/msm-bus-ids.h 2019-01-22 16:16:28.179288750 +0100 @@ -0,0 +1,887 @@ +/* Copyright (c) 2014-2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __MSM_BUS_IDS_H +#define __MSM_BUS_IDS_H + +/* Aggregation types */ +#define AGG_SCHEME_NONE 0 +#define AGG_SCHEME_LEG 1 +#define AGG_SCHEME_1 2 + +/* Topology related enums */ +#define MSM_BUS_FAB_DEFAULT 0 +#define MSM_BUS_FAB_APPSS 0 +#define MSM_BUS_FAB_SYSTEM 1024 +#define MSM_BUS_FAB_MMSS 2048 +#define MSM_BUS_FAB_SYSTEM_FPB 3072 +#define MSM_BUS_FAB_CPSS_FPB 4096 + +#define MSM_BUS_FAB_BIMC 0 +#define MSM_BUS_FAB_SYS_NOC 1024 +#define MSM_BUS_FAB_MMSS_NOC 2048 +#define MSM_BUS_FAB_OCMEM_NOC 3072 +#define MSM_BUS_FAB_PERIPH_NOC 4096 +#define MSM_BUS_FAB_CONFIG_NOC 5120 +#define MSM_BUS_FAB_OCMEM_VNOC 6144 +#define MSM_BUS_FAB_MMSS_AHB 2049 +#define MSM_BUS_FAB_A0_NOC 6145 +#define MSM_BUS_FAB_A1_NOC 6146 +#define MSM_BUS_FAB_A2_NOC 6147 +#define MSM_BUS_FAB_GNOC 6148 +#define MSM_BUS_FAB_CR_VIRT 6149 + +#define MSM_BUS_MASTER_FIRST 1 +#define MSM_BUS_MASTER_AMPSS_M0 1 +#define MSM_BUS_MASTER_AMPSS_M1 2 +#define MSM_BUS_APPSS_MASTER_FAB_MMSS 3 +#define MSM_BUS_APPSS_MASTER_FAB_SYSTEM 4 +#define MSM_BUS_SYSTEM_MASTER_FAB_APPSS 5 +#define MSM_BUS_MASTER_SPS 6 +#define MSM_BUS_MASTER_ADM_PORT0 7 +#define MSM_BUS_MASTER_ADM_PORT1 8 +#define MSM_BUS_SYSTEM_MASTER_ADM1_PORT0 9 +#define MSM_BUS_MASTER_ADM1_PORT1 10 +#define MSM_BUS_MASTER_LPASS_PROC 11 +#define MSM_BUS_MASTER_MSS_PROCI 12 +#define MSM_BUS_MASTER_MSS_PROCD 13 +#define MSM_BUS_MASTER_MSS_MDM_PORT0 14 +#define MSM_BUS_MASTER_LPASS 15 +#define MSM_BUS_SYSTEM_MASTER_CPSS_FPB 16 +#define MSM_BUS_SYSTEM_MASTER_SYSTEM_FPB 17 +#define MSM_BUS_SYSTEM_MASTER_MMSS_FPB 18 +#define MSM_BUS_MASTER_ADM1_CI 19 +#define MSM_BUS_MASTER_ADM0_CI 20 +#define MSM_BUS_MASTER_MSS_MDM_PORT1 21 +#define MSM_BUS_MASTER_MDP_PORT0 22 +#define MSM_BUS_MASTER_MDP_PORT1 23 +#define MSM_BUS_MMSS_MASTER_ADM1_PORT0 24 +#define MSM_BUS_MASTER_ROTATOR 25 +#define MSM_BUS_MASTER_GRAPHICS_3D 26 +#define MSM_BUS_MASTER_JPEG_DEC 27 +#define MSM_BUS_MASTER_GRAPHICS_2D_CORE0 28 +#define MSM_BUS_MASTER_VFE 29 +#define MSM_BUS_MASTER_VFE0 MSM_BUS_MASTER_VFE +#define MSM_BUS_MASTER_VPE 30 +#define MSM_BUS_MASTER_JPEG_ENC 31 +#define MSM_BUS_MASTER_GRAPHICS_2D_CORE1 32 +#define MSM_BUS_MMSS_MASTER_APPS_FAB 33 +#define MSM_BUS_MASTER_HD_CODEC_PORT0 34 +#define MSM_BUS_MASTER_HD_CODEC_PORT1 35 +#define MSM_BUS_MASTER_SPDM 36 +#define MSM_BUS_MASTER_RPM 37 +#define MSM_BUS_MASTER_MSS 38 +#define MSM_BUS_MASTER_RIVA 39 +#define MSM_BUS_MASTER_SNOC_VMEM 40 +#define MSM_BUS_MASTER_MSS_SW_PROC 41 +#define MSM_BUS_MASTER_MSS_FW_PROC 42 +#define MSM_BUS_MASTER_HMSS 43 +#define MSM_BUS_MASTER_GSS_NAV 44 +#define MSM_BUS_MASTER_PCIE 45 +#define MSM_BUS_MASTER_SATA 46 +#define MSM_BUS_MASTER_CRYPTO 47 +#define MSM_BUS_MASTER_VIDEO_CAP 48 +#define MSM_BUS_MASTER_GRAPHICS_3D_PORT1 49 +#define MSM_BUS_MASTER_VIDEO_ENC 50 +#define MSM_BUS_MASTER_VIDEO_DEC 51 +#define MSM_BUS_MASTER_LPASS_AHB 52 +#define MSM_BUS_MASTER_QDSS_BAM 53 +#define MSM_BUS_MASTER_SNOC_CFG 54 +#define MSM_BUS_MASTER_CRYPTO_CORE0 55 +#define MSM_BUS_MASTER_CRYPTO_CORE1 56 +#define MSM_BUS_MASTER_MSS_NAV 57 +#define MSM_BUS_MASTER_OCMEM_DMA 58 +#define MSM_BUS_MASTER_WCSS 59 +#define MSM_BUS_MASTER_QDSS_ETR 60 +#define MSM_BUS_MASTER_USB3 61 +#define MSM_BUS_MASTER_JPEG 62 +#define MSM_BUS_MASTER_VIDEO_P0 63 +#define MSM_BUS_MASTER_VIDEO_P1 64 +#define MSM_BUS_MASTER_MSS_PROC 65 +#define MSM_BUS_MASTER_JPEG_OCMEM 66 +#define MSM_BUS_MASTER_MDP_OCMEM 67 +#define MSM_BUS_MASTER_VIDEO_P0_OCMEM 68 +#define MSM_BUS_MASTER_VIDEO_P1_OCMEM 69 +#define MSM_BUS_MASTER_VFE_OCMEM 70 +#define MSM_BUS_MASTER_CNOC_ONOC_CFG 71 +#define MSM_BUS_MASTER_RPM_INST 72 +#define MSM_BUS_MASTER_RPM_DATA 73 +#define MSM_BUS_MASTER_RPM_SYS 74 +#define MSM_BUS_MASTER_DEHR 75 +#define MSM_BUS_MASTER_QDSS_DAP 76 +#define MSM_BUS_MASTER_TIC 77 +#define MSM_BUS_MASTER_SDCC_1 78 +#define MSM_BUS_MASTER_SDCC_3 79 +#define MSM_BUS_MASTER_SDCC_4 80 +#define MSM_BUS_MASTER_SDCC_2 81 +#define MSM_BUS_MASTER_TSIF 82 +#define MSM_BUS_MASTER_BAM_DMA 83 +#define MSM_BUS_MASTER_BLSP_2 84 +#define MSM_BUS_MASTER_USB_HSIC 85 +#define MSM_BUS_MASTER_BLSP_1 86 +#define MSM_BUS_MASTER_USB_HS 87 +#define MSM_BUS_MASTER_PNOC_CFG 88 +#define MSM_BUS_MASTER_V_OCMEM_GFX3D 89 +#define MSM_BUS_MASTER_IPA 90 +#define MSM_BUS_MASTER_QPIC 91 +#define MSM_BUS_MASTER_MDPE 92 +#define MSM_BUS_MASTER_USB_HS2 93 +#define MSM_BUS_MASTER_VPU 94 +#define MSM_BUS_MASTER_UFS 95 +#define MSM_BUS_MASTER_BCAST 96 +#define MSM_BUS_MASTER_CRYPTO_CORE2 97 +#define MSM_BUS_MASTER_EMAC 98 +#define MSM_BUS_MASTER_VPU_1 99 +#define MSM_BUS_MASTER_PCIE_1 100 +#define MSM_BUS_MASTER_USB3_1 101 +#define MSM_BUS_MASTER_CNOC_MNOC_MMSS_CFG 102 +#define MSM_BUS_MASTER_CNOC_MNOC_CFG 103 +#define MSM_BUS_MASTER_TCU_0 104 +#define MSM_BUS_MASTER_TCU_1 105 +#define MSM_BUS_MASTER_CPP 106 +#define MSM_BUS_MASTER_AUDIO 107 +#define MSM_BUS_MASTER_PCIE_2 108 +#define MSM_BUS_MASTER_VFE1 109 +#define MSM_BUS_MASTER_XM_USB_HS1 110 +#define MSM_BUS_MASTER_PCNOC_BIMC_1 111 +#define MSM_BUS_MASTER_BIMC_PCNOC 112 +#define MSM_BUS_MASTER_XI_USB_HSIC 113 +#define MSM_BUS_MASTER_SGMII 114 +#define MSM_BUS_SPMI_FETCHER 115 +#define MSM_BUS_MASTER_GNOC_BIMC 116 +#define MSM_BUS_MASTER_CRVIRT_A2NOC 117 +#define MSM_BUS_MASTER_CNOC_A2NOC 118 +#define MSM_BUS_MASTER_WLAN 119 +#define MSM_BUS_MASTER_MSS_CE 120 +#define MSM_BUS_MASTER_CDSP_PROC 121 +#define MSM_BUS_MASTER_GNOC_SNOC 122 +#define MSM_BUS_MASTER_PIMEM 123 +#define MSM_BUS_MASTER_MASTER_LAST 124 + +#define MSM_BUS_SYSTEM_FPB_MASTER_SYSTEM MSM_BUS_SYSTEM_MASTER_SYSTEM_FPB +#define MSM_BUS_CPSS_FPB_MASTER_SYSTEM MSM_BUS_SYSTEM_MASTER_CPSS_FPB + +#define MSM_BUS_SNOC_MM_INT_0 10000 +#define MSM_BUS_SNOC_MM_INT_1 10001 +#define MSM_BUS_SNOC_MM_INT_2 10002 +#define MSM_BUS_SNOC_MM_INT_BIMC 10003 +#define MSM_BUS_SNOC_INT_0 10004 +#define MSM_BUS_SNOC_INT_1 10005 +#define MSM_BUS_SNOC_INT_BIMC 10006 +#define MSM_BUS_SNOC_BIMC_0_MAS 10007 +#define MSM_BUS_SNOC_BIMC_1_MAS 10008 +#define MSM_BUS_SNOC_QDSS_INT 10009 +#define MSM_BUS_PNOC_SNOC_MAS 10010 +#define MSM_BUS_PNOC_SNOC_SLV 10011 +#define MSM_BUS_PNOC_INT_0 10012 +#define MSM_BUS_PNOC_INT_1 10013 +#define MSM_BUS_PNOC_M_0 10014 +#define MSM_BUS_PNOC_M_1 10015 +#define MSM_BUS_BIMC_SNOC_MAS 10016 +#define MSM_BUS_BIMC_SNOC_SLV 10017 +#define MSM_BUS_PNOC_SLV_0 10018 +#define MSM_BUS_PNOC_SLV_1 10019 +#define MSM_BUS_PNOC_SLV_2 10020 +#define MSM_BUS_PNOC_SLV_3 10021 +#define MSM_BUS_PNOC_SLV_4 10022 +#define MSM_BUS_PNOC_SLV_8 10023 +#define MSM_BUS_PNOC_SLV_9 10024 +#define MSM_BUS_SNOC_BIMC_0_SLV 10025 +#define MSM_BUS_SNOC_BIMC_1_SLV 10026 +#define MSM_BUS_MNOC_BIMC_MAS 10027 +#define MSM_BUS_MNOC_BIMC_SLV 10028 +#define MSM_BUS_BIMC_MNOC_MAS 10029 +#define MSM_BUS_BIMC_MNOC_SLV 10030 +#define MSM_BUS_SNOC_BIMC_MAS 10031 +#define MSM_BUS_SNOC_BIMC_SLV 10032 +#define MSM_BUS_CNOC_SNOC_MAS 10033 +#define MSM_BUS_CNOC_SNOC_SLV 10034 +#define MSM_BUS_SNOC_CNOC_MAS 10035 +#define MSM_BUS_SNOC_CNOC_SLV 10036 +#define MSM_BUS_OVNOC_SNOC_MAS 10037 +#define MSM_BUS_OVNOC_SNOC_SLV 10038 +#define MSM_BUS_SNOC_OVNOC_MAS 10039 +#define MSM_BUS_SNOC_OVNOC_SLV 10040 +#define MSM_BUS_SNOC_PNOC_MAS 10041 +#define MSM_BUS_SNOC_PNOC_SLV 10042 +#define MSM_BUS_BIMC_INT_APPS_EBI 10043 +#define MSM_BUS_BIMC_INT_APPS_SNOC 10044 +#define MSM_BUS_SNOC_BIMC_2_MAS 10045 +#define MSM_BUS_SNOC_BIMC_2_SLV 10046 +#define MSM_BUS_PNOC_SLV_5 10047 +#define MSM_BUS_PNOC_SLV_7 10048 +#define MSM_BUS_PNOC_INT_2 10049 +#define MSM_BUS_PNOC_INT_3 10050 +#define MSM_BUS_PNOC_INT_4 10051 +#define MSM_BUS_PNOC_INT_5 10052 +#define MSM_BUS_PNOC_INT_6 10053 +#define MSM_BUS_PNOC_INT_7 10054 +#define MSM_BUS_BIMC_SNOC_1_MAS 10055 +#define MSM_BUS_BIMC_SNOC_1_SLV 10056 +#define MSM_BUS_PNOC_A1NOC_MAS 10057 +#define MSM_BUS_PNOC_A1NOC_SLV 10058 +#define MSM_BUS_CNOC_A1NOC_MAS 10059 +#define MSM_BUS_A0NOC_SNOC_MAS 10060 +#define MSM_BUS_A0NOC_SNOC_SLV 10061 +#define MSM_BUS_A1NOC_SNOC_SLV 10062 +#define MSM_BUS_A1NOC_SNOC_MAS 10063 +#define MSM_BUS_A2NOC_SNOC_MAS 10064 +#define MSM_BUS_A2NOC_SNOC_SLV 10065 +#define MSM_BUS_SNOC_INT_2 10066 +#define MSM_BUS_A0NOC_QDSS_INT 10067 +#define MSM_BUS_INT_LAST 10068 + +#define MSM_BUS_INT_TEST_ID 20000 +#define MSM_BUS_INT_TEST_LAST 20050 + +#define MSM_BUS_SLAVE_FIRST 512 +#define MSM_BUS_SLAVE_EBI_CH0 512 +#define MSM_BUS_SLAVE_EBI_CH1 513 +#define MSM_BUS_SLAVE_AMPSS_L2 514 +#define MSM_BUS_APPSS_SLAVE_FAB_MMSS 515 +#define MSM_BUS_APPSS_SLAVE_FAB_SYSTEM 516 +#define MSM_BUS_SYSTEM_SLAVE_FAB_APPS 517 +#define MSM_BUS_SLAVE_SPS 518 +#define MSM_BUS_SLAVE_SYSTEM_IMEM 519 +#define MSM_BUS_SLAVE_AMPSS 520 +#define MSM_BUS_SLAVE_MSS 521 +#define MSM_BUS_SLAVE_LPASS 522 +#define MSM_BUS_SYSTEM_SLAVE_CPSS_FPB 523 +#define MSM_BUS_SYSTEM_SLAVE_SYSTEM_FPB 524 +#define MSM_BUS_SYSTEM_SLAVE_MMSS_FPB 525 +#define MSM_BUS_SLAVE_CORESIGHT 526 +#define MSM_BUS_SLAVE_RIVA 527 +#define MSM_BUS_SLAVE_SMI 528 +#define MSM_BUS_MMSS_SLAVE_FAB_APPS 529 +#define MSM_BUS_MMSS_SLAVE_FAB_APPS_1 530 +#define MSM_BUS_SLAVE_MM_IMEM 531 +#define MSM_BUS_SLAVE_CRYPTO 532 +#define MSM_BUS_SLAVE_SPDM 533 +#define MSM_BUS_SLAVE_RPM 534 +#define MSM_BUS_SLAVE_RPM_MSG_RAM 535 +#define MSM_BUS_SLAVE_MPM 536 +#define MSM_BUS_SLAVE_PMIC1_SSBI1_A 537 +#define MSM_BUS_SLAVE_PMIC1_SSBI1_B 538 +#define MSM_BUS_SLAVE_PMIC1_SSBI1_C 539 +#define MSM_BUS_SLAVE_PMIC2_SSBI2_A 540 +#define MSM_BUS_SLAVE_PMIC2_SSBI2_B 541 +#define MSM_BUS_SLAVE_GSBI1_UART 542 +#define MSM_BUS_SLAVE_GSBI2_UART 543 +#define MSM_BUS_SLAVE_GSBI3_UART 544 +#define MSM_BUS_SLAVE_GSBI4_UART 545 +#define MSM_BUS_SLAVE_GSBI5_UART 546 +#define MSM_BUS_SLAVE_GSBI6_UART 547 +#define MSM_BUS_SLAVE_GSBI7_UART 548 +#define MSM_BUS_SLAVE_GSBI8_UART 549 +#define MSM_BUS_SLAVE_GSBI9_UART 550 +#define MSM_BUS_SLAVE_GSBI10_UART 551 +#define MSM_BUS_SLAVE_GSBI11_UART 552 +#define MSM_BUS_SLAVE_GSBI12_UART 553 +#define MSM_BUS_SLAVE_GSBI1_QUP 554 +#define MSM_BUS_SLAVE_GSBI2_QUP 555 +#define MSM_BUS_SLAVE_GSBI3_QUP 556 +#define MSM_BUS_SLAVE_GSBI4_QUP 557 +#define MSM_BUS_SLAVE_GSBI5_QUP 558 +#define MSM_BUS_SLAVE_GSBI6_QUP 559 +#define MSM_BUS_SLAVE_GSBI7_QUP 560 +#define MSM_BUS_SLAVE_GSBI8_QUP 561 +#define MSM_BUS_SLAVE_GSBI9_QUP 562 +#define MSM_BUS_SLAVE_GSBI10_QUP 563 +#define MSM_BUS_SLAVE_GSBI11_QUP 564 +#define MSM_BUS_SLAVE_GSBI12_QUP 565 +#define MSM_BUS_SLAVE_EBI2_NAND 566 +#define MSM_BUS_SLAVE_EBI2_CS0 567 +#define MSM_BUS_SLAVE_EBI2_CS1 568 +#define MSM_BUS_SLAVE_EBI2_CS2 569 +#define MSM_BUS_SLAVE_EBI2_CS3 570 +#define MSM_BUS_SLAVE_EBI2_CS4 571 +#define MSM_BUS_SLAVE_EBI2_CS5 572 +#define MSM_BUS_SLAVE_USB_FS1 573 +#define MSM_BUS_SLAVE_USB_FS2 574 +#define MSM_BUS_SLAVE_TSIF 575 +#define MSM_BUS_SLAVE_MSM_TSSC 576 +#define MSM_BUS_SLAVE_MSM_PDM 577 +#define MSM_BUS_SLAVE_MSM_DIMEM 578 +#define MSM_BUS_SLAVE_MSM_TCSR 579 +#define MSM_BUS_SLAVE_MSM_PRNG 580 +#define MSM_BUS_SLAVE_GSS 581 +#define MSM_BUS_SLAVE_SATA 582 +#define MSM_BUS_SLAVE_USB3 583 +#define MSM_BUS_SLAVE_WCSS 584 +#define MSM_BUS_SLAVE_OCIMEM 585 +#define MSM_BUS_SLAVE_SNOC_OCMEM 586 +#define MSM_BUS_SLAVE_SERVICE_SNOC 587 +#define MSM_BUS_SLAVE_QDSS_STM 588 +#define MSM_BUS_SLAVE_CAMERA_CFG 589 +#define MSM_BUS_SLAVE_DISPLAY_CFG 590 +#define MSM_BUS_SLAVE_OCMEM_CFG 591 +#define MSM_BUS_SLAVE_CPR_CFG 592 +#define MSM_BUS_SLAVE_CPR_XPU_CFG 593 +#define MSM_BUS_SLAVE_MISC_CFG 594 +#define MSM_BUS_SLAVE_MISC_XPU_CFG 595 +#define MSM_BUS_SLAVE_VENUS_CFG 596 +#define MSM_BUS_SLAVE_MISC_VENUS_CFG 597 +#define MSM_BUS_SLAVE_GRAPHICS_3D_CFG 598 +#define MSM_BUS_SLAVE_MMSS_CLK_CFG 599 +#define MSM_BUS_SLAVE_MMSS_CLK_XPU_CFG 600 +#define MSM_BUS_SLAVE_MNOC_MPU_CFG 601 +#define MSM_BUS_SLAVE_ONOC_MPU_CFG 602 +#define MSM_BUS_SLAVE_SERVICE_MNOC 603 +#define MSM_BUS_SLAVE_OCMEM 604 +#define MSM_BUS_SLAVE_SERVICE_ONOC 605 +#define MSM_BUS_SLAVE_SDCC_1 606 +#define MSM_BUS_SLAVE_SDCC_3 607 +#define MSM_BUS_SLAVE_SDCC_2 608 +#define MSM_BUS_SLAVE_SDCC_4 609 +#define MSM_BUS_SLAVE_BAM_DMA 610 +#define MSM_BUS_SLAVE_BLSP_2 611 +#define MSM_BUS_SLAVE_USB_HSIC 612 +#define MSM_BUS_SLAVE_BLSP_1 613 +#define MSM_BUS_SLAVE_USB_HS 614 +#define MSM_BUS_SLAVE_PDM 615 +#define MSM_BUS_SLAVE_PERIPH_APU_CFG 616 +#define MSM_BUS_SLAVE_PNOC_MPU_CFG 617 +#define MSM_BUS_SLAVE_PRNG 618 +#define MSM_BUS_SLAVE_SERVICE_PNOC 619 +#define MSM_BUS_SLAVE_CLK_CTL 620 +#define MSM_BUS_SLAVE_CNOC_MSS 621 +#define MSM_BUS_SLAVE_SECURITY 622 +#define MSM_BUS_SLAVE_TCSR 623 +#define MSM_BUS_SLAVE_TLMM 624 +#define MSM_BUS_SLAVE_CRYPTO_0_CFG 625 +#define MSM_BUS_SLAVE_CRYPTO_1_CFG 626 +#define MSM_BUS_SLAVE_IMEM_CFG 627 +#define MSM_BUS_SLAVE_MESSAGE_RAM 628 +#define MSM_BUS_SLAVE_BIMC_CFG 629 +#define MSM_BUS_SLAVE_BOOT_ROM 630 +#define MSM_BUS_SLAVE_CNOC_MNOC_MMSS_CFG 631 +#define MSM_BUS_SLAVE_PMIC_ARB 632 +#define MSM_BUS_SLAVE_SPDM_WRAPPER 633 +#define MSM_BUS_SLAVE_DEHR_CFG 634 +#define MSM_BUS_SLAVE_QDSS_CFG 635 +#define MSM_BUS_SLAVE_RBCPR_CFG 636 +#define MSM_BUS_SLAVE_RBCPR_QDSS_APU_CFG 637 +#define MSM_BUS_SLAVE_SNOC_MPU_CFG 638 +#define MSM_BUS_SLAVE_CNOC_ONOC_CFG 639 +#define MSM_BUS_SLAVE_CNOC_MNOC_CFG 640 +#define MSM_BUS_SLAVE_PNOC_CFG 641 +#define MSM_BUS_SLAVE_SNOC_CFG 642 +#define MSM_BUS_SLAVE_EBI1_DLL_CFG 643 +#define MSM_BUS_SLAVE_PHY_APU_CFG 644 +#define MSM_BUS_SLAVE_EBI1_PHY_CFG 645 +#define MSM_BUS_SLAVE_SERVICE_CNOC 646 +#define MSM_BUS_SLAVE_IPS_CFG 647 +#define MSM_BUS_SLAVE_QPIC 648 +#define MSM_BUS_SLAVE_DSI_CFG 649 +#define MSM_BUS_SLAVE_UFS_CFG 650 +#define MSM_BUS_SLAVE_RBCPR_CX_CFG 651 +#define MSM_BUS_SLAVE_RBCPR_MX_CFG 652 +#define MSM_BUS_SLAVE_PCIE_CFG 653 +#define MSM_BUS_SLAVE_USB_PHYS_CFG 654 +#define MSM_BUS_SLAVE_VIDEO_CAP_CFG 655 +#define MSM_BUS_SLAVE_AVSYNC_CFG 656 +#define MSM_BUS_SLAVE_CRYPTO_2_CFG 657 +#define MSM_BUS_SLAVE_VPU_CFG 658 +#define MSM_BUS_SLAVE_BCAST_CFG 659 +#define MSM_BUS_SLAVE_KLM_CFG 660 +#define MSM_BUS_SLAVE_GENI_IR_CFG 661 +#define MSM_BUS_SLAVE_OCMEM_GFX 662 +#define MSM_BUS_SLAVE_CATS_128 663 +#define MSM_BUS_SLAVE_OCMEM_64 664 +#define MSM_BUS_SLAVE_PCIE_0 665 +#define MSM_BUS_SLAVE_PCIE_1 666 +#define MSM_BUS_SLAVE_PCIE_0_CFG 667 +#define MSM_BUS_SLAVE_PCIE_1_CFG 668 +#define MSM_BUS_SLAVE_SRVC_MNOC 669 +#define MSM_BUS_SLAVE_USB_HS2 670 +#define MSM_BUS_SLAVE_AUDIO 671 +#define MSM_BUS_SLAVE_TCU 672 +#define MSM_BUS_SLAVE_APPSS 673 +#define MSM_BUS_SLAVE_PCIE_PARF 674 +#define MSM_BUS_SLAVE_USB3_PHY_CFG 675 +#define MSM_BUS_SLAVE_IPA_CFG 676 +#define MSM_BUS_SLAVE_A0NOC_SNOC 677 +#define MSM_BUS_SLAVE_A1NOC_SNOC 678 +#define MSM_BUS_SLAVE_A2NOC_SNOC 679 +#define MSM_BUS_SLAVE_HMSS_L3 680 +#define MSM_BUS_SLAVE_PIMEM_CFG 681 +#define MSM_BUS_SLAVE_DCC_CFG 682 +#define MSM_BUS_SLAVE_QDSS_RBCPR_APU_CFG 683 +#define MSM_BUS_SLAVE_PCIE_2_CFG 684 +#define MSM_BUS_SLAVE_PCIE20_AHB2PHY 685 +#define MSM_BUS_SLAVE_A0NOC_CFG 686 +#define MSM_BUS_SLAVE_A1NOC_CFG 687 +#define MSM_BUS_SLAVE_A2NOC_CFG 688 +#define MSM_BUS_SLAVE_A1NOC_MPU_CFG 689 +#define MSM_BUS_SLAVE_A2NOC_MPU_CFG 690 +#define MSM_BUS_SLAVE_A0NOC_SMMU_CFG 691 +#define MSM_BUS_SLAVE_A1NOC_SMMU_CFG 692 +#define MSM_BUS_SLAVE_A2NOC_SMMU_CFG 693 +#define MSM_BUS_SLAVE_LPASS_SMMU_CFG 694 +#define MSM_BUS_SLAVE_MMAGIC_CFG 695 +#define MSM_BUS_SLAVE_VENUS_THROTTLE_CFG 696 +#define MSM_BUS_SLAVE_SSC_CFG 697 +#define MSM_BUS_SLAVE_DSA_CFG 698 +#define MSM_BUS_SLAVE_DSA_MPU_CFG 699 +#define MSM_BUS_SLAVE_DISPLAY_THROTTLE_CFG 700 +#define MSM_BUS_SLAVE_SMMU_CPP_CFG 701 +#define MSM_BUS_SLAVE_SMMU_JPEG_CFG 702 +#define MSM_BUS_SLAVE_SMMU_MDP_CFG 703 +#define MSM_BUS_SLAVE_SMMU_ROTATOR_CFG 704 +#define MSM_BUS_SLAVE_SMMU_VENUS_CFG 705 +#define MSM_BUS_SLAVE_SMMU_VFE_CFG 706 +#define MSM_BUS_SLAVE_A0NOC_MPU_CFG 707 +#define MSM_BUS_SLAVE_VMEM_CFG 708 +#define MSM_BUS_SLAVE_CAMERA_THROTTLE_CFG 709 +#define MSM_BUS_SLAVE_VMEM 710 +#define MSM_BUS_SLAVE_AHB2PHY 711 +#define MSM_BUS_SLAVE_PIMEM 712 +#define MSM_BUS_SLAVE_SNOC_VMEM 713 +#define MSM_BUS_SLAVE_PCIE_2 714 +#define MSM_BUS_SLAVE_RBCPR_MX 715 +#define MSM_BUS_SLAVE_RBCPR_CX 716 +#define MSM_BUS_SLAVE_BIMC_PCNOC 717 +#define MSM_BUS_SLAVE_PCNOC_BIMC_1 718 +#define MSM_BUS_SLAVE_SGMII 719 +#define MSM_BUS_SLAVE_SPMI_FETCHER 720 +#define MSM_BUS_PNOC_SLV_6 721 +#define MSM_BUS_SLAVE_MMSS_SMMU_CFG 722 +#define MSM_BUS_SLAVE_WLAN 723 +#define MSM_BUS_SLAVE_CRVIRT_A2NOC 724 +#define MSM_BUS_SLAVE_CNOC_A2NOC 725 +#define MSM_BUS_SLAVE_GLM 726 +#define MSM_BUS_SLAVE_GNOC_BIMC 727 +#define MSM_BUS_SLAVE_GNOC_SNOC 728 +#define MSM_BUS_SLAVE_QM_CFG 729 +#define MSM_BUS_SLAVE_TLMM_EAST 730 +#define MSM_BUS_SLAVE_TLMM_NORTH 731 +#define MSM_BUS_SLAVE_TLMM_WEST 732 +#define MSM_BUS_SLAVE_SKL 733 +#define MSM_BUS_SLAVE_LPASS_TCM 734 +#define MSM_BUS_SLAVE_TLMM_SOUTH 735 +#define MSM_BUS_SLAVE_TLMM_CENTER 736 +#define MSM_BUS_MSS_NAV_CE_MPU_CFG 737 +#define MSM_BUS_SLAVE_A2NOC_THROTTLE_CFG 738 +#define MSM_BUS_SLAVE_CDSP 739 +#define MSM_BUS_SLAVE_CDSP_SMMU_CFG 740 +#define MSM_BUS_SLAVE_LPASS_MPU_CFG 741 +#define MSM_BUS_SLAVE_CSI_PHY_CFG 742 +#define MSM_BUS_SLAVE_LAST 743 + +#define MSM_BUS_SYSTEM_FPB_SLAVE_SYSTEM MSM_BUS_SYSTEM_SLAVE_SYSTEM_FPB +#define MSM_BUS_CPSS_FPB_SLAVE_SYSTEM MSM_BUS_SYSTEM_SLAVE_CPSS_FPB + +/* + * ID's used in RPM messages + */ +#define ICBID_MASTER_APPSS_PROC 0 +#define ICBID_MASTER_MSS_PROC 1 +#define ICBID_MASTER_MNOC_BIMC 2 +#define ICBID_MASTER_SNOC_BIMC 3 +#define ICBID_MASTER_SNOC_BIMC_0 ICBID_MASTER_SNOC_BIMC +#define ICBID_MASTER_CNOC_MNOC_MMSS_CFG 4 +#define ICBID_MASTER_CNOC_MNOC_CFG 5 +#define ICBID_MASTER_GFX3D 6 +#define ICBID_MASTER_JPEG 7 +#define ICBID_MASTER_MDP 8 +#define ICBID_MASTER_MDP0 ICBID_MASTER_MDP +#define ICBID_MASTER_MDPS ICBID_MASTER_MDP +#define ICBID_MASTER_VIDEO 9 +#define ICBID_MASTER_VIDEO_P0 ICBID_MASTER_VIDEO +#define ICBID_MASTER_VIDEO_P1 10 +#define ICBID_MASTER_VFE 11 +#define ICBID_MASTER_VFE0 ICBID_MASTER_VFE +#define ICBID_MASTER_CNOC_ONOC_CFG 12 +#define ICBID_MASTER_JPEG_OCMEM 13 +#define ICBID_MASTER_MDP_OCMEM 14 +#define ICBID_MASTER_VIDEO_P0_OCMEM 15 +#define ICBID_MASTER_VIDEO_P1_OCMEM 16 +#define ICBID_MASTER_VFE_OCMEM 17 +#define ICBID_MASTER_LPASS_AHB 18 +#define ICBID_MASTER_QDSS_BAM 19 +#define ICBID_MASTER_SNOC_CFG 20 +#define ICBID_MASTER_BIMC_SNOC 21 +#define ICBID_MASTER_BIMC_SNOC_0 ICBID_MASTER_BIMC_SNOC +#define ICBID_MASTER_CNOC_SNOC 22 +#define ICBID_MASTER_CRYPTO 23 +#define ICBID_MASTER_CRYPTO_CORE0 ICBID_MASTER_CRYPTO +#define ICBID_MASTER_CRYPTO_CORE1 24 +#define ICBID_MASTER_LPASS_PROC 25 +#define ICBID_MASTER_MSS 26 +#define ICBID_MASTER_MSS_NAV 27 +#define ICBID_MASTER_OCMEM_DMA 28 +#define ICBID_MASTER_PNOC_SNOC 29 +#define ICBID_MASTER_WCSS 30 +#define ICBID_MASTER_QDSS_ETR 31 +#define ICBID_MASTER_USB3 32 +#define ICBID_MASTER_USB3_0 ICBID_MASTER_USB3 +#define ICBID_MASTER_SDCC_1 33 +#define ICBID_MASTER_SDCC_3 34 +#define ICBID_MASTER_SDCC_2 35 +#define ICBID_MASTER_SDCC_4 36 +#define ICBID_MASTER_TSIF 37 +#define ICBID_MASTER_BAM_DMA 38 +#define ICBID_MASTER_BLSP_2 39 +#define ICBID_MASTER_USB_HSIC 40 +#define ICBID_MASTER_BLSP_1 41 +#define ICBID_MASTER_USB_HS 42 +#define ICBID_MASTER_USB_HS1 ICBID_MASTER_USB_HS +#define ICBID_MASTER_PNOC_CFG 43 +#define ICBID_MASTER_SNOC_PNOC 44 +#define ICBID_MASTER_RPM_INST 45 +#define ICBID_MASTER_RPM_DATA 46 +#define ICBID_MASTER_RPM_SYS 47 +#define ICBID_MASTER_DEHR 48 +#define ICBID_MASTER_QDSS_DAP 49 +#define ICBID_MASTER_SPDM 50 +#define ICBID_MASTER_TIC 51 +#define ICBID_MASTER_SNOC_CNOC 52 +#define ICBID_MASTER_GFX3D_OCMEM 53 +#define ICBID_MASTER_GFX3D_GMEM ICBID_MASTER_GFX3D_OCMEM +#define ICBID_MASTER_OVIRT_SNOC 54 +#define ICBID_MASTER_SNOC_OVIRT 55 +#define ICBID_MASTER_SNOC_GVIRT ICBID_MASTER_SNOC_OVIRT +#define ICBID_MASTER_ONOC_OVIRT 56 +#define ICBID_MASTER_USB_HS2 57 +#define ICBID_MASTER_QPIC 58 +#define ICBID_MASTER_IPA 59 +#define ICBID_MASTER_DSI 60 +#define ICBID_MASTER_MDP1 61 +#define ICBID_MASTER_MDPE ICBID_MASTER_MDP1 +#define ICBID_MASTER_VPU_PROC 62 +#define ICBID_MASTER_VPU 63 +#define ICBID_MASTER_VPU0 ICBID_MASTER_VPU +#define ICBID_MASTER_CRYPTO_CORE2 64 +#define ICBID_MASTER_PCIE_0 65 +#define ICBID_MASTER_PCIE_1 66 +#define ICBID_MASTER_SATA 67 +#define ICBID_MASTER_UFS 68 +#define ICBID_MASTER_USB3_1 69 +#define ICBID_MASTER_VIDEO_OCMEM 70 +#define ICBID_MASTER_VPU1 71 +#define ICBID_MASTER_VCAP 72 +#define ICBID_MASTER_EMAC 73 +#define ICBID_MASTER_BCAST 74 +#define ICBID_MASTER_MMSS_PROC 75 +#define ICBID_MASTER_SNOC_BIMC_1 76 +#define ICBID_MASTER_SNOC_PCNOC 77 +#define ICBID_MASTER_AUDIO 78 +#define ICBID_MASTER_MM_INT_0 79 +#define ICBID_MASTER_MM_INT_1 80 +#define ICBID_MASTER_MM_INT_2 81 +#define ICBID_MASTER_MM_INT_BIMC 82 +#define ICBID_MASTER_MSS_INT 83 +#define ICBID_MASTER_PCNOC_CFG 84 +#define ICBID_MASTER_PCNOC_INT_0 85 +#define ICBID_MASTER_PCNOC_INT_1 86 +#define ICBID_MASTER_PCNOC_M_0 87 +#define ICBID_MASTER_PCNOC_M_1 88 +#define ICBID_MASTER_PCNOC_S_0 89 +#define ICBID_MASTER_PCNOC_S_1 90 +#define ICBID_MASTER_PCNOC_S_2 91 +#define ICBID_MASTER_PCNOC_S_3 92 +#define ICBID_MASTER_PCNOC_S_4 93 +#define ICBID_MASTER_PCNOC_S_6 94 +#define ICBID_MASTER_PCNOC_S_7 95 +#define ICBID_MASTER_PCNOC_S_8 96 +#define ICBID_MASTER_PCNOC_S_9 97 +#define ICBID_MASTER_QDSS_INT 98 +#define ICBID_MASTER_SNOC_INT_0 99 +#define ICBID_MASTER_SNOC_INT_1 100 +#define ICBID_MASTER_SNOC_INT_BIMC 101 +#define ICBID_MASTER_TCU_0 102 +#define ICBID_MASTER_TCU_1 103 +#define ICBID_MASTER_BIMC_INT_0 104 +#define ICBID_MASTER_BIMC_INT_1 105 +#define ICBID_MASTER_CAMERA 106 +#define ICBID_MASTER_RICA 107 +#define ICBID_MASTER_SNOC_BIMC_2 108 +#define ICBID_MASTER_BIMC_SNOC_1 109 +#define ICBID_MASTER_A0NOC_SNOC 110 +#define ICBID_MASTER_A1NOC_SNOC 111 +#define ICBID_MASTER_A2NOC_SNOC 112 +#define ICBID_MASTER_PIMEM 113 +#define ICBID_MASTER_SNOC_VMEM 114 +#define ICBID_MASTER_CPP 115 +#define ICBID_MASTER_CNOC_A1NOC 116 +#define ICBID_MASTER_PNOC_A1NOC 117 +#define ICBID_MASTER_HMSS 118 +#define ICBID_MASTER_PCIE_2 119 +#define ICBID_MASTER_ROTATOR 120 +#define ICBID_MASTER_VENUS_VMEM 121 +#define ICBID_MASTER_DCC 122 +#define ICBID_MASTER_MCDMA 123 +#define ICBID_MASTER_PCNOC_INT_2 124 +#define ICBID_MASTER_PCNOC_INT_3 125 +#define ICBID_MASTER_PCNOC_INT_4 126 +#define ICBID_MASTER_PCNOC_INT_5 127 +#define ICBID_MASTER_PCNOC_INT_6 128 +#define ICBID_MASTER_PCNOC_S_5 129 +#define ICBID_MASTER_SENSORS_AHB 130 +#define ICBID_MASTER_SENSORS_PROC 131 +#define ICBID_MASTER_QSPI 132 +#define ICBID_MASTER_VFE1 133 +#define ICBID_MASTER_SNOC_INT_2 134 +#define ICBID_MASTER_SMMNOC_BIMC 135 +#define ICBID_MASTER_CRVIRT_A1NOC 136 +#define ICBID_MASTER_XM_USB_HS1 137 +#define ICBID_MASTER_XI_USB_HS1 138 +#define ICBID_MASTER_PCNOC_BIMC_1 139 +#define ICBID_MASTER_BIMC_PCNOC 140 +#define ICBID_MASTER_XI_HSIC 141 +#define ICBID_MASTER_SGMII 142 +#define ICBID_MASTER_SPMI_FETCHER 143 +#define ICBID_MASTER_GNOC_BIMC 144 +#define ICBID_MASTER_CRVIRT_A2NOC 145 +#define ICBID_MASTER_CNOC_A2NOC 146 +#define ICBID_MASTER_WLAN 147 +#define ICBID_MASTER_MSS_CE 148 +#define ICBID_MASTER_CDSP_PROC 149 +#define ICBID_MASTER_GNOC_SNOC 150 + +#define ICBID_SLAVE_EBI1 0 +#define ICBID_SLAVE_APPSS_L2 1 +#define ICBID_SLAVE_BIMC_SNOC 2 +#define ICBID_SLAVE_BIMC_SNOC_0 ICBID_SLAVE_BIMC_SNOC +#define ICBID_SLAVE_CAMERA_CFG 3 +#define ICBID_SLAVE_DISPLAY_CFG 4 +#define ICBID_SLAVE_OCMEM_CFG 5 +#define ICBID_SLAVE_CPR_CFG 6 +#define ICBID_SLAVE_CPR_XPU_CFG 7 +#define ICBID_SLAVE_MISC_CFG 8 +#define ICBID_SLAVE_MISC_XPU_CFG 9 +#define ICBID_SLAVE_VENUS_CFG 10 +#define ICBID_SLAVE_GFX3D_CFG 11 +#define ICBID_SLAVE_MMSS_CLK_CFG 12 +#define ICBID_SLAVE_MMSS_CLK_XPU_CFG 13 +#define ICBID_SLAVE_MNOC_MPU_CFG 14 +#define ICBID_SLAVE_ONOC_MPU_CFG 15 +#define ICBID_SLAVE_MNOC_BIMC 16 +#define ICBID_SLAVE_SERVICE_MNOC 17 +#define ICBID_SLAVE_OCMEM 18 +#define ICBID_SLAVE_GMEM ICBID_SLAVE_OCMEM +#define ICBID_SLAVE_SERVICE_ONOC 19 +#define ICBID_SLAVE_APPSS 20 +#define ICBID_SLAVE_LPASS 21 +#define ICBID_SLAVE_USB3 22 +#define ICBID_SLAVE_USB3_0 ICBID_SLAVE_USB3 +#define ICBID_SLAVE_WCSS 23 +#define ICBID_SLAVE_SNOC_BIMC 24 +#define ICBID_SLAVE_SNOC_BIMC_0 ICBID_SLAVE_SNOC_BIMC +#define ICBID_SLAVE_SNOC_CNOC 25 +#define ICBID_SLAVE_IMEM 26 +#define ICBID_SLAVE_OCIMEM ICBID_SLAVE_IMEM +#define ICBID_SLAVE_SNOC_OVIRT 27 +#define ICBID_SLAVE_SNOC_GVIRT ICBID_SLAVE_SNOC_OVIRT +#define ICBID_SLAVE_SNOC_PNOC 28 +#define ICBID_SLAVE_SNOC_PCNOC ICBID_SLAVE_SNOC_PNOC +#define ICBID_SLAVE_SERVICE_SNOC 29 +#define ICBID_SLAVE_QDSS_STM 30 +#define ICBID_SLAVE_SDCC_1 31 +#define ICBID_SLAVE_SDCC_3 32 +#define ICBID_SLAVE_SDCC_2 33 +#define ICBID_SLAVE_SDCC_4 34 +#define ICBID_SLAVE_TSIF 35 +#define ICBID_SLAVE_BAM_DMA 36 +#define ICBID_SLAVE_BLSP_2 37 +#define ICBID_SLAVE_USB_HSIC 38 +#define ICBID_SLAVE_BLSP_1 39 +#define ICBID_SLAVE_USB_HS 40 +#define ICBID_SLAVE_USB_HS1 ICBID_SLAVE_USB_HS +#define ICBID_SLAVE_PDM 41 +#define ICBID_SLAVE_PERIPH_APU_CFG 42 +#define ICBID_SLAVE_PNOC_MPU_CFG 43 +#define ICBID_SLAVE_PRNG 44 +#define ICBID_SLAVE_PNOC_SNOC 45 +#define ICBID_SLAVE_PCNOC_SNOC ICBID_SLAVE_PNOC_SNOC +#define ICBID_SLAVE_SERVICE_PNOC 46 +#define ICBID_SLAVE_CLK_CTL 47 +#define ICBID_SLAVE_CNOC_MSS 48 +#define ICBID_SLAVE_PCNOC_MSS ICBID_SLAVE_CNOC_MSS +#define ICBID_SLAVE_SECURITY 49 +#define ICBID_SLAVE_TCSR 50 +#define ICBID_SLAVE_TLMM 51 +#define ICBID_SLAVE_CRYPTO_0_CFG 52 +#define ICBID_SLAVE_CRYPTO_1_CFG 53 +#define ICBID_SLAVE_IMEM_CFG 54 +#define ICBID_SLAVE_MESSAGE_RAM 55 +#define ICBID_SLAVE_BIMC_CFG 56 +#define ICBID_SLAVE_BOOT_ROM 57 +#define ICBID_SLAVE_CNOC_MNOC_MMSS_CFG 58 +#define ICBID_SLAVE_PMIC_ARB 59 +#define ICBID_SLAVE_SPDM_WRAPPER 60 +#define ICBID_SLAVE_DEHR_CFG 61 +#define ICBID_SLAVE_MPM 62 +#define ICBID_SLAVE_QDSS_CFG 63 +#define ICBID_SLAVE_RBCPR_CFG 64 +#define ICBID_SLAVE_RBCPR_CX_CFG ICBID_SLAVE_RBCPR_CFG +#define ICBID_SLAVE_RBCPR_QDSS_APU_CFG 65 +#define ICBID_SLAVE_CNOC_MNOC_CFG 66 +#define ICBID_SLAVE_SNOC_MPU_CFG 67 +#define ICBID_SLAVE_CNOC_ONOC_CFG 68 +#define ICBID_SLAVE_PNOC_CFG 69 +#define ICBID_SLAVE_SNOC_CFG 70 +#define ICBID_SLAVE_EBI1_DLL_CFG 71 +#define ICBID_SLAVE_PHY_APU_CFG 72 +#define ICBID_SLAVE_EBI1_PHY_CFG 73 +#define ICBID_SLAVE_RPM 74 +#define ICBID_SLAVE_CNOC_SNOC 75 +#define ICBID_SLAVE_SERVICE_CNOC 76 +#define ICBID_SLAVE_OVIRT_SNOC 77 +#define ICBID_SLAVE_OVIRT_OCMEM 78 +#define ICBID_SLAVE_USB_HS2 79 +#define ICBID_SLAVE_QPIC 80 +#define ICBID_SLAVE_IPS_CFG 81 +#define ICBID_SLAVE_DSI_CFG 82 +#define ICBID_SLAVE_USB3_1 83 +#define ICBID_SLAVE_PCIE_0 84 +#define ICBID_SLAVE_PCIE_1 85 +#define ICBID_SLAVE_PSS_SMMU_CFG 86 +#define ICBID_SLAVE_CRYPTO_2_CFG 87 +#define ICBID_SLAVE_PCIE_0_CFG 88 +#define ICBID_SLAVE_PCIE_1_CFG 89 +#define ICBID_SLAVE_SATA_CFG 90 +#define ICBID_SLAVE_SPSS_GENI_IR 91 +#define ICBID_SLAVE_UFS_CFG 92 +#define ICBID_SLAVE_AVSYNC_CFG 93 +#define ICBID_SLAVE_VPU_CFG 94 +#define ICBID_SLAVE_USB_PHY_CFG 95 +#define ICBID_SLAVE_RBCPR_MX_CFG 96 +#define ICBID_SLAVE_PCIE_PARF 97 +#define ICBID_SLAVE_VCAP_CFG 98 +#define ICBID_SLAVE_EMAC_CFG 99 +#define ICBID_SLAVE_BCAST_CFG 100 +#define ICBID_SLAVE_KLM_CFG 101 +#define ICBID_SLAVE_DISPLAY_PWM 102 +#define ICBID_SLAVE_GENI 103 +#define ICBID_SLAVE_SNOC_BIMC_1 104 +#define ICBID_SLAVE_AUDIO 105 +#define ICBID_SLAVE_CATS_0 106 +#define ICBID_SLAVE_CATS_1 107 +#define ICBID_SLAVE_MM_INT_0 108 +#define ICBID_SLAVE_MM_INT_1 109 +#define ICBID_SLAVE_MM_INT_2 110 +#define ICBID_SLAVE_MM_INT_BIMC 111 +#define ICBID_SLAVE_MMU_MODEM_XPU_CFG 112 +#define ICBID_SLAVE_MSS_INT 113 +#define ICBID_SLAVE_PCNOC_INT_0 114 +#define ICBID_SLAVE_PCNOC_INT_1 115 +#define ICBID_SLAVE_PCNOC_M_0 116 +#define ICBID_SLAVE_PCNOC_M_1 117 +#define ICBID_SLAVE_PCNOC_S_0 118 +#define ICBID_SLAVE_PCNOC_S_1 119 +#define ICBID_SLAVE_PCNOC_S_2 120 +#define ICBID_SLAVE_PCNOC_S_3 121 +#define ICBID_SLAVE_PCNOC_S_4 122 +#define ICBID_SLAVE_PCNOC_S_6 123 +#define ICBID_SLAVE_PCNOC_S_7 124 +#define ICBID_SLAVE_PCNOC_S_8 125 +#define ICBID_SLAVE_PCNOC_S_9 126 +#define ICBID_SLAVE_PRNG_XPU_CFG 127 +#define ICBID_SLAVE_QDSS_INT 128 +#define ICBID_SLAVE_RPM_XPU_CFG 129 +#define ICBID_SLAVE_SNOC_INT_0 130 +#define ICBID_SLAVE_SNOC_INT_1 131 +#define ICBID_SLAVE_SNOC_INT_BIMC 132 +#define ICBID_SLAVE_TCU 133 +#define ICBID_SLAVE_BIMC_INT_0 134 +#define ICBID_SLAVE_BIMC_INT_1 135 +#define ICBID_SLAVE_RICA_CFG 136 +#define ICBID_SLAVE_SNOC_BIMC_2 137 +#define ICBID_SLAVE_BIMC_SNOC_1 138 +#define ICBID_SLAVE_PNOC_A1NOC 139 +#define ICBID_SLAVE_SNOC_VMEM 140 +#define ICBID_SLAVE_A0NOC_SNOC 141 +#define ICBID_SLAVE_A1NOC_SNOC 142 +#define ICBID_SLAVE_A2NOC_SNOC 143 +#define ICBID_SLAVE_A0NOC_CFG 144 +#define ICBID_SLAVE_A0NOC_MPU_CFG 145 +#define ICBID_SLAVE_A0NOC_SMMU_CFG 146 +#define ICBID_SLAVE_A1NOC_CFG 147 +#define ICBID_SLAVE_A1NOC_MPU_CFG 148 +#define ICBID_SLAVE_A1NOC_SMMU_CFG 149 +#define ICBID_SLAVE_A2NOC_CFG 150 +#define ICBID_SLAVE_A2NOC_MPU_CFG 151 +#define ICBID_SLAVE_A2NOC_SMMU_CFG 152 +#define ICBID_SLAVE_AHB2PHY 153 +#define ICBID_SLAVE_CAMERA_THROTTLE_CFG 154 +#define ICBID_SLAVE_DCC_CFG 155 +#define ICBID_SLAVE_DISPLAY_THROTTLE_CFG 156 +#define ICBID_SLAVE_DSA_CFG 157 +#define ICBID_SLAVE_DSA_MPU_CFG 158 +#define ICBID_SLAVE_SSC_MPU_CFG 159 +#define ICBID_SLAVE_HMSS_L3 160 +#define ICBID_SLAVE_LPASS_SMMU_CFG 161 +#define ICBID_SLAVE_MMAGIC_CFG 162 +#define ICBID_SLAVE_PCIE20_AHB2PHY 163 +#define ICBID_SLAVE_PCIE_2 164 +#define ICBID_SLAVE_PCIE_2_CFG 165 +#define ICBID_SLAVE_PIMEM 166 +#define ICBID_SLAVE_PIMEM_CFG 167 +#define ICBID_SLAVE_QDSS_RBCPR_APU_CFG 168 +#define ICBID_SLAVE_RBCPR_CX 169 +#define ICBID_SLAVE_RBCPR_MX 170 +#define ICBID_SLAVE_SMMU_CPP_CFG 171 +#define ICBID_SLAVE_SMMU_JPEG_CFG 172 +#define ICBID_SLAVE_SMMU_MDP_CFG 173 +#define ICBID_SLAVE_SMMU_ROTATOR_CFG 174 +#define ICBID_SLAVE_SMMU_VENUS_CFG 175 +#define ICBID_SLAVE_SMMU_VFE_CFG 176 +#define ICBID_SLAVE_SSC_CFG 177 +#define ICBID_SLAVE_VENUS_THROTTLE_CFG 178 +#define ICBID_SLAVE_VMEM 179 +#define ICBID_SLAVE_VMEM_CFG 180 +#define ICBID_SLAVE_QDSS_MPU_CFG 181 +#define ICBID_SLAVE_USB3_PHY_CFG 182 +#define ICBID_SLAVE_IPA_CFG 183 +#define ICBID_SLAVE_PCNOC_INT_2 184 +#define ICBID_SLAVE_PCNOC_INT_3 185 +#define ICBID_SLAVE_PCNOC_INT_4 186 +#define ICBID_SLAVE_PCNOC_INT_5 187 +#define ICBID_SLAVE_PCNOC_INT_6 188 +#define ICBID_SLAVE_PCNOC_S_5 189 +#define ICBID_SLAVE_QSPI 190 +#define ICBID_SLAVE_A1NOC_MS_MPU_CFG 191 +#define ICBID_SLAVE_A2NOC_MS_MPU_CFG 192 +#define ICBID_SLAVE_MODEM_Q6_SMMU_CFG 193 +#define ICBID_SLAVE_MSS_MPU_CFG 194 +#define ICBID_SLAVE_MSS_PROC_MS_MPU_CFG 195 +#define ICBID_SLAVE_SKL 196 +#define ICBID_SLAVE_SNOC_INT_2 197 +#define ICBID_SLAVE_SMMNOC_BIMC 198 +#define ICBID_SLAVE_CRVIRT_A1NOC 199 +#define ICBID_SLAVE_SGMII 200 +#define ICBID_SLAVE_QHS4_APPS 201 +#define ICBID_SLAVE_BIMC_PCNOC 202 +#define ICBID_SLAVE_PCNOC_BIMC_1 203 +#define ICBID_SLAVE_SPMI_FETCHER 204 +#define ICBID_SLAVE_MMSS_SMMU_CFG 205 +#define ICBID_SLAVE_WLAN 206 +#define ICBID_SLAVE_CRVIRT_A2NOC 207 +#define ICBID_SLAVE_CNOC_A2NOC 208 +#define ICBID_SLAVE_GLM 209 +#define ICBID_SLAVE_GNOC_BIMC 210 +#define ICBID_SLAVE_GNOC_SNOC 211 +#define ICBID_SLAVE_QM_CFG 212 +#define ICBID_SLAVE_TLMM_EAST 213 +#define ICBID_SLAVE_TLMM_NORTH 214 +#define ICBID_SLAVE_TLMM_WEST 215 +#define ICBID_SLAVE_LPASS_TCM 216 +#define ICBID_SLAVE_TLMM_SOUTH 217 +#define ICBID_SLAVE_TLMM_CENTER 218 +#define ICBID_SLAVE_MSS_NAV_CE_MPU_CFG 219 +#define ICBID_SLAVE_A2NOC_THROTTLE_CFG 220 +#define ICBID_SLAVE_CDSP 221 +#define ICBID_SLAVE_CDSP_SMMU_CFG 222 +#define ICBID_SLAVE_LPASS_MPU_CFG 223 +#define ICBID_SLAVE_CSI_PHY_CFG 224 +#endif diff -Nruw linux-4.4.115-fbx/arch/cris/boot/dts/include/dt-bindings/msm./msm-bus-rule-ops.h linux-4.4.115-fbx/arch/cris/boot/dts/include/dt-bindings/msm/msm-bus-rule-ops.h --- linux-4.4.115-fbx/arch/cris/boot/dts/include/dt-bindings/msm./msm-bus-rule-ops.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-4.4.115-fbx/arch/cris/boot/dts/include/dt-bindings/msm/msm-bus-rule-ops.h 2019-01-22 16:16:28.179288750 +0100 @@ -0,0 +1,34 @@ +/* Copyright (c) 2014, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __MSM_BUS_RULE_OPS_H +#define __MSM_BUS_RULE_OPS_H + +#define FLD_IB 0 +#define FLD_AB 1 +#define FLD_CLK 2 + +#define OP_LE 0 +#define OP_LT 1 +#define OP_GE 2 +#define OP_GT 3 +#define OP_NOOP 4 + +#define RULE_STATE_NOT_APPLIED 0 +#define RULE_STATE_APPLIED 1 + +#define THROTTLE_ON 0 +#define THROTTLE_OFF 1 +#define THROTTLE_REG 2 + + +#endif diff -Nruw linux-4.4.115-fbx/arch/cris/boot/dts/include/dt-bindings/msm./pm.h linux-4.4.115-fbx/arch/cris/boot/dts/include/dt-bindings/msm/pm.h --- linux-4.4.115-fbx/arch/cris/boot/dts/include/dt-bindings/msm./pm.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-4.4.115-fbx/arch/cris/boot/dts/include/dt-bindings/msm/pm.h 2019-01-22 16:16:28.179288750 +0100 @@ -0,0 +1,25 @@ +/* Copyright (c) 2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __DT_MSM_PM_H__ +#define __DT_MSM_PM_H__ + +#define LPM_RESET_LVL_NONE 0 +#define LPM_RESET_LVL_RET 1 +#define LPM_RESET_LVL_GDHS 2 +#define LPM_RESET_LVL_PC 3 + +#define LPM_AFF_LVL_CPU 0 +#define LPM_AFF_LVL_L2 1 +#define LPM_AFF_LVL_CCI 2 + +#endif diff -Nruw linux-4.4.115-fbx/arch/cris/boot/dts/include/dt-bindings/msm./power-on.h linux-4.4.115-fbx/arch/cris/boot/dts/include/dt-bindings/msm/power-on.h --- linux-4.4.115-fbx/arch/cris/boot/dts/include/dt-bindings/msm./power-on.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-4.4.115-fbx/arch/cris/boot/dts/include/dt-bindings/msm/power-on.h 2019-01-22 16:16:28.179288750 +0100 @@ -0,0 +1,24 @@ +/* Copyright (c) 2015, 2017, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __MSM_POWER_ON_H__ +#define __MSM_POWER_ON_H__ + +#define PON_POWER_OFF_RESERVED 0x00 +#define PON_POWER_OFF_WARM_RESET 0x01 +#define PON_POWER_OFF_SHUTDOWN 0x04 +#define PON_POWER_OFF_DVDD_SHUTDOWN 0x05 +#define PON_POWER_OFF_HARD_RESET 0x07 +#define PON_POWER_OFF_DVDD_HARD_RESET 0x08 +#define PON_POWER_OFF_MAX_TYPE 0x10 + +#endif --- /dev/null 2019-10-24 16:47:25.704025805 +0200 +++ linux-4.4.115-fbx/arch/cris/boot/dts/include/dt-bindings/regulator/qcom,rpm-smd-regulator.h 2019-01-22 16:16:28.183288787 +0100 @@ -0,0 +1,28 @@ +/* Copyright (c) 2015, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __QCOM_RPM_SMD_REGULATOR_H +#define __QCOM_RPM_SMD_REGULATOR_H + +#define RPM_SMD_REGULATOR_LEVEL_NONE 0 +#define RPM_SMD_REGULATOR_LEVEL_RETENTION 16 +#define RPM_SMD_REGULATOR_LEVEL_RETENTION_PLUS 32 +#define RPM_SMD_REGULATOR_LEVEL_MIN_SVS 48 +#define RPM_SMD_REGULATOR_LEVEL_LOW_SVS 64 +#define RPM_SMD_REGULATOR_LEVEL_SVS 128 +#define RPM_SMD_REGULATOR_LEVEL_SVS_PLUS 192 +#define RPM_SMD_REGULATOR_LEVEL_NOM 256 +#define RPM_SMD_REGULATOR_LEVEL_NOM_PLUS 320 +#define RPM_SMD_REGULATOR_LEVEL_TURBO 384 +#define RPM_SMD_REGULATOR_LEVEL_BINNING 512 + +#endif --- /dev/null 2019-10-24 16:47:25.704025805 +0200 +++ linux-4.4.115-fbx/arch/metag/boot/dts/include/dt-bindings/clock/audio-ext-clk.h 2019-01-22 16:16:28.167288642 +0100 @@ -0,0 +1,30 @@ +/* Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __AUDIO_EXT_CLK_H +#define __AUDIO_EXT_CLK_H + +/* Audio External Clocks */ +#define AUDIO_PMI_CLK 0 +#define AUDIO_PMIC_LNBB_CLK 0 +#define AUDIO_AP_CLK 1 +#define AUDIO_AP_CLK2 2 +#define AUDIO_LPASS_MCLK 3 +#define AUDIO_LPASS_MCLK2 4 + +#define clk_audio_ap_clk 0x9b5727cb +#define clk_audio_pmi_clk 0xcbfe416d +#define clk_audio_ap_clk2 0x454d1e91 +#define clk_audio_lpass_mclk 0xf0f2a284 +#define clk_audio_pmi_lnbb_clk 0x57312343 + +#endif --- /dev/null 2019-10-24 16:47:25.704025805 +0200 +++ linux-4.4.115-fbx/arch/metag/boot/dts/include/dt-bindings/clock/msm-clocks-8996.h 2019-01-22 16:16:28.171288678 +0100 @@ -0,0 +1,574 @@ +/* Copyright (c) 2014-2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __MSM_CLOCKS_8996_H +#define __MSM_CLOCKS_8996_H + +#include "audio-ext-clk.h" + +/* clock_gcc controlled clocks */ +#define clk_cxo_clk_src 0x79e95308 +#define clk_pnoc_clk 0x4325d220 +#define clk_pnoc_a_clk 0x2808c12b +#define clk_bimc_clk 0x4b80bf00 +#define clk_bimc_a_clk 0x4b25668a +#define clk_cnoc_clk 0xd5ccb7f4 +#define clk_cnoc_a_clk 0xd8fe2ccc +#define clk_snoc_clk 0x2c341aa0 +#define clk_snoc_a_clk 0x8fcef2af +#define clk_bb_clk1 0xf5304268 +#define clk_bb_clk1_ao 0xfa113810 +#define clk_bb_clk1_pin 0x6dd0a779 +#define clk_bb_clk1_pin_ao 0x9b637772 +#define clk_bb_clk2 0xfe15cb87 +#define clk_bb_clk2_ao 0x59682706 +#define clk_bb_clk2_pin 0x498938e5 +#define clk_bb_clk2_pin_ao 0x52513787 +#define clk_bimc_msmbus_clk 0xd212feea +#define clk_bimc_msmbus_a_clk 0x71d1a499 +#define clk_ce1_a_clk 0x44a833fe +#define clk_cnoc_msmbus_clk 0x62228b5d +#define clk_cnoc_msmbus_a_clk 0x67442955 +#define clk_cxo_clk_src_ao 0x64eb6004 +#define clk_cxo_dwc3_clk 0xf79c19f6 +#define clk_cxo_lpm_clk 0x94adbf3d +#define clk_cxo_otg_clk 0x4eec0bb9 +#define clk_cxo_pil_lpass_clk 0xe17f0ff6 +#define clk_cxo_pil_ssc_clk 0x81832015 +#define clk_div_clk1 0xaa1157a6 +#define clk_div_clk1_ao 0x6b943d68 +#define clk_div_clk2 0xd454019f +#define clk_div_clk2_ao 0x53f9e788 +#define clk_div_clk3 0xa9a55a68 +#define clk_div_clk3_ao 0x3d6725a8 +#define clk_ipa_a_clk 0xeeec2919 +#define clk_ipa_clk 0xfa685cda +#define clk_ln_bb_clk 0x3ab0b36d +#define clk_ln_bb_a_clk 0xc7257ea8 +#define clk_ln_bb_clk_pin 0x1b1c476a +#define clk_ln_bb_a_clk_pin 0x9cbb5411 +#define clk_mcd_ce1_clk 0xbb615d26 +#define clk_pnoc_keepalive_a_clk 0xf8f91f0b +#define clk_pnoc_msmbus_clk 0x38b95c77 +#define clk_pnoc_msmbus_a_clk 0x8c9b4e93 +#define clk_pnoc_pm_clk 0xd6f7dfb9 +#define clk_pnoc_sps_clk 0xd482ecc7 +#define clk_qdss_a_clk 0xdd121669 +#define clk_qdss_clk 0x1492202a +#define clk_rf_clk1 0xaabeea5a +#define clk_rf_clk1_ao 0x72a10cb8 +#define clk_rf_clk1_pin 0x8f463562 +#define clk_rf_clk1_pin_ao 0x62549ff6 +#define clk_rf_clk2 0x24a30992 +#define clk_rf_clk2_ao 0x944d8bbd +#define clk_rf_clk2_pin 0xa7c5602a +#define clk_rf_clk2_pin_ao 0x2d75eb4d +#define clk_snoc_msmbus_clk 0xe6900bb6 +#define clk_snoc_msmbus_a_clk 0x5d4683bd +#define clk_mcd_ce1_clk 0xbb615d26 +#define clk_qcedev_ce1_clk 0x293f97b0 +#define clk_qcrypto_ce1_clk 0xa6ac14df +#define clk_qseecom_ce1_clk 0xaa858373 +#define clk_scm_ce1_clk 0xd8ebcc62 +#define clk_ce1_clk 0x42229c55 +#define clk_gcc_ce1_ahb_m_clk 0x2eb28c01 +#define clk_gcc_ce1_axi_m_clk 0xc174dfba +#define clk_measure_only_bimc_hmss_axi_clk 0xc1cc4f11 +#define clk_aggre1_noc_clk 0x049abba8 +#define clk_aggre1_noc_a_clk 0xc12e4220 +#define clk_aggre2_noc_clk 0xaa681404 +#define clk_aggre2_noc_a_clk 0xcab67089 +#define clk_mmssnoc_axi_rpm_clk 0x4d7f8cdc +#define clk_mmssnoc_axi_rpm_a_clk 0xfbea899b +#define clk_mmssnoc_axi_clk 0xdb4b31e6 +#define clk_mmssnoc_axi_a_clk 0xd4970614 +#define clk_mmssnoc_gds_clk 0x06a22afa + +#define clk_gpll0 0x1ebe3bc4 +#define clk_gpll0_ao 0xa1368304 +#define clk_gpll0_out_main 0xe9374de7 +#define clk_gpll4 0xb3b5d85b +#define clk_gpll4_out_main 0xa9a0ab9d +#define clk_ufs_axi_clk_src 0x297ca380 +#define clk_pcie_aux_clk_src 0xebc50566 +#define clk_usb30_master_clk_src 0xc6262f89 +#define clk_usb20_master_clk_src 0x5680ac83 +#define clk_ufs_ice_core_clk_src 0xda8e7119 +#define clk_blsp1_qup1_i2c_apps_clk_src 0x17f78f5e +#define clk_blsp1_qup1_spi_apps_clk_src 0xf534c4fa +#define clk_blsp1_qup2_i2c_apps_clk_src 0x8de71c79 +#define clk_blsp1_qup2_spi_apps_clk_src 0x33cf809a +#define clk_blsp1_qup3_i2c_apps_clk_src 0xf161b902 +#define clk_blsp1_qup3_spi_apps_clk_src 0x5e95683f +#define clk_blsp1_qup4_i2c_apps_clk_src 0xb2ecce68 +#define clk_blsp1_qup4_spi_apps_clk_src 0xddb5bbdb +#define clk_blsp1_qup5_i2c_apps_clk_src 0x71ea7804 +#define clk_blsp1_qup5_spi_apps_clk_src 0x9752f35f +#define clk_blsp1_qup6_i2c_apps_clk_src 0x28806803 +#define clk_blsp1_qup6_spi_apps_clk_src 0x44a1edc4 +#define clk_blsp1_uart1_apps_clk_src 0xf8146114 +#define clk_blsp1_uart2_apps_clk_src 0xfc9c2f73 +#define clk_blsp1_uart3_apps_clk_src 0x600497f2 +#define clk_blsp1_uart4_apps_clk_src 0x56bff15c +#define clk_blsp1_uart5_apps_clk_src 0x218ef697 +#define clk_blsp1_uart6_apps_clk_src 0x8fbdbe4c +#define clk_blsp2_qup1_i2c_apps_clk_src 0xd6d1e95d +#define clk_blsp2_qup1_spi_apps_clk_src 0xcc1b8365 +#define clk_blsp2_qup2_i2c_apps_clk_src 0x603b5c51 +#define clk_blsp2_qup2_spi_apps_clk_src 0xd577dc44 +#define clk_blsp2_qup3_i2c_apps_clk_src 0xea82959c +#define clk_blsp2_qup3_spi_apps_clk_src 0xd04b1e92 +#define clk_blsp2_qup4_i2c_apps_clk_src 0x73dc968c +#define clk_blsp2_qup4_spi_apps_clk_src 0x25d4a2b1 +#define clk_blsp2_qup5_i2c_apps_clk_src 0xcc3698bd +#define clk_blsp2_qup5_spi_apps_clk_src 0xfa0cf45e +#define clk_blsp2_qup6_i2c_apps_clk_src 0x2fa53151 +#define clk_blsp2_qup6_spi_apps_clk_src 0x5ca86755 +#define clk_blsp2_uart1_apps_clk_src 0x562c66dc +#define clk_blsp2_uart2_apps_clk_src 0xdd448080 +#define clk_blsp2_uart3_apps_clk_src 0x46b2e90f +#define clk_blsp2_uart4_apps_clk_src 0x23a093d2 +#define clk_blsp2_uart5_apps_clk_src 0xe067616a +#define clk_blsp2_uart6_apps_clk_src 0xe02d2829 +#define clk_gp1_clk_src 0xad85b97a +#define clk_gp2_clk_src 0xfb1f0065 +#define clk_gp3_clk_src 0x63b693d6 +#define clk_hmss_rbcpr_clk_src 0xedd9a474 +#define clk_pdm2_clk_src 0x31e494fd +#define clk_sdcc1_apps_clk_src 0xd4975db2 +#define clk_sdcc2_apps_clk_src 0xfc46c821 +#define clk_sdcc3_apps_clk_src 0xea34c7f4 +#define clk_sdcc4_apps_clk_src 0x7aaaaa0c +#define clk_tsif_ref_clk_src 0x4e9042d1 +#define clk_usb20_mock_utmi_clk_src 0xc3aaeecb +#define clk_usb30_mock_utmi_clk_src 0xa024a976 +#define clk_usb3_phy_aux_clk_src 0x15eec63c +#define clk_gcc_qusb2phy_prim_reset 0x07550fa1 +#define clk_gcc_qusb2phy_sec_reset 0x3f3a87d0 +#define clk_gcc_periph_noc_usb20_ahb_clk 0xfb9f26e9 +#define clk_gcc_mmss_gcc_dbg_clk 0xe89d461c +#define clk_cpu_dbg_clk 0x6550dfa9 +#define clk_gcc_blsp1_ahb_clk 0x8caa5b4f +#define clk_gcc_blsp1_qup1_i2c_apps_clk 0xc303fae9 +#define clk_gcc_blsp1_qup1_spi_apps_clk 0x759a76b0 +#define clk_gcc_blsp1_qup2_i2c_apps_clk 0x1076f220 +#define clk_gcc_blsp1_qup2_spi_apps_clk 0x3e77d48f +#define clk_gcc_blsp1_qup3_i2c_apps_clk 0x9e25ac82 +#define clk_gcc_blsp1_qup3_spi_apps_clk 0xfb978880 +#define clk_gcc_blsp1_qup4_i2c_apps_clk 0xd7f40f6f +#define clk_gcc_blsp1_qup4_spi_apps_clk 0x80f8722f +#define clk_gcc_blsp1_qup5_i2c_apps_clk 0xacae5604 +#define clk_gcc_blsp1_qup5_spi_apps_clk 0xbf3e15d7 +#define clk_gcc_blsp1_qup6_i2c_apps_clk 0x5c6ad820 +#define clk_gcc_blsp1_qup6_spi_apps_clk 0x780d9f85 +#define clk_gcc_blsp1_uart1_apps_clk 0xc7c62f90 +#define clk_gcc_blsp1_uart2_apps_clk 0xf8a61c96 +#define clk_gcc_blsp1_uart3_apps_clk 0xc3298bd7 +#define clk_gcc_blsp1_uart4_apps_clk 0x26be16c0 +#define clk_gcc_blsp1_uart5_apps_clk 0x28a6bc74 +#define clk_gcc_blsp1_uart6_apps_clk 0x28fd3466 +#define clk_gcc_blsp2_ahb_clk 0x8f283c1d +#define clk_gcc_blsp2_qup1_i2c_apps_clk 0x9ace11dd +#define clk_gcc_blsp2_qup1_spi_apps_clk 0xa32604cc +#define clk_gcc_blsp2_qup2_i2c_apps_clk 0x1bf9a57e +#define clk_gcc_blsp2_qup2_spi_apps_clk 0xbf54ca6d +#define clk_gcc_blsp2_qup3_i2c_apps_clk 0x336d4170 +#define clk_gcc_blsp2_qup3_spi_apps_clk 0xc68509d6 +#define clk_gcc_blsp2_qup4_i2c_apps_clk 0xbd22539d +#define clk_gcc_blsp2_qup4_spi_apps_clk 0x01a72b93 +#define clk_gcc_blsp2_qup5_i2c_apps_clk 0xe2b2ce1d +#define clk_gcc_blsp2_qup5_spi_apps_clk 0xf40999cd +#define clk_gcc_blsp2_qup6_i2c_apps_clk 0x894bcea4 +#define clk_gcc_blsp2_qup6_spi_apps_clk 0xfe1bd34a +#define clk_gcc_blsp2_uart1_apps_clk 0x8c3512ff +#define clk_gcc_blsp2_uart2_apps_clk 0x1e1965a3 +#define clk_gcc_blsp2_uart3_apps_clk 0x382415ab +#define clk_gcc_blsp2_uart4_apps_clk 0x87a44b42 +#define clk_gcc_blsp2_uart5_apps_clk 0x5cd30649 +#define clk_gcc_blsp2_uart6_apps_clk 0x8feee5ab +#define clk_gcc_boot_rom_ahb_clk 0xde2adeb1 +#define clk_gcc_gp1_clk 0x057f7b69 +#define clk_gcc_gp2_clk 0x9bf83ffd +#define clk_gcc_gp3_clk 0xec6539ee +#define clk_gcc_hmss_rbcpr_clk 0x699183be +#define clk_gcc_mmss_noc_cfg_ahb_clk 0xb41a9d99 +#define clk_gcc_pcie_0_aux_clk 0x3d2e3ece +#define clk_gcc_pcie_0_cfg_ahb_clk 0x4dd325c3 +#define clk_gcc_pcie_0_mstr_axi_clk 0x3f85285b +#define clk_gcc_pcie_0_slv_axi_clk 0xd69638a1 +#define clk_gcc_pcie_0_pipe_clk 0x4f37621e +#define clk_gcc_pcie_0_phy_reset 0xdc3201c1 +#define clk_gcc_pcie_1_aux_clk 0xc9bb962c +#define clk_gcc_pcie_1_cfg_ahb_clk 0xb6338658 +#define clk_gcc_pcie_1_mstr_axi_clk 0xc20f6269 +#define clk_gcc_pcie_1_slv_axi_clk 0xd54e40d6 +#define clk_gcc_pcie_1_pipe_clk 0xc1627422 +#define clk_gcc_pcie_1_phy_reset 0x674481bb +#define clk_gcc_pcie_2_aux_clk 0xa4dc7ae8 +#define clk_gcc_pcie_2_cfg_ahb_clk 0x4f1d3121 +#define clk_gcc_pcie_2_mstr_axi_clk 0x9e81724a +#define clk_gcc_pcie_2_slv_axi_clk 0x7990d8b2 +#define clk_gcc_pcie_2_pipe_clk 0xa757a834 +#define clk_gcc_pcie_2_phy_reset 0x82634880 +#define clk_gcc_pcie_phy_reset 0x9bc3c959 +#define clk_gcc_pcie_phy_com_reset 0x8bf513e6 +#define clk_gcc_pcie_phy_nocsr_com_phy_reset 0x0c16a2da +#define clk_gcc_pcie_phy_aux_clk 0x4746e74f +#define clk_gcc_pcie_phy_cfg_ahb_clk 0x8533671a +#define clk_gcc_pdm2_clk 0x99d55711 +#define clk_gcc_pdm_ahb_clk 0x365664f6 +#define clk_gcc_prng_ahb_clk 0x397e7eaa +#define clk_gcc_sdcc1_ahb_clk 0x691e0caa +#define clk_gcc_sdcc1_apps_clk 0x9ad6fb96 +#define clk_gcc_sdcc2_ahb_clk 0x23d5727f +#define clk_gcc_sdcc2_apps_clk 0x861b20ac +#define clk_gcc_sdcc3_ahb_clk 0x565b2c03 +#define clk_gcc_sdcc3_apps_clk 0x0b27aeac +#define clk_gcc_sdcc4_ahb_clk 0x64f3e6a8 +#define clk_gcc_sdcc4_apps_clk 0xbf7c4dc8 +#define clk_gcc_tsif_ahb_clk 0x88d2822c +#define clk_gcc_tsif_ref_clk 0x8f1ed2c2 +#define clk_gcc_ufs_ahb_clk 0x1914bb84 +#define clk_gcc_ufs_axi_clk 0x47c743a7 +#define clk_gcc_ufs_ice_core_clk 0x310b0710 +#define clk_gcc_ufs_rx_cfg_clk 0xa6747786 +#define clk_gcc_ufs_rx_symbol_0_clk 0x7f43251c +#define clk_gcc_ufs_rx_symbol_1_clk 0x03182fde +#define clk_gcc_ufs_tx_cfg_clk 0xba2cf8b5 +#define clk_gcc_ufs_tx_symbol_0_clk 0x6a9f747a +#define clk_gcc_ufs_unipro_core_clk 0x2daf7fd2 +#define clk_gcc_ufs_sys_clk_core_clk 0x360e5ac8 +#define clk_gcc_ufs_tx_symbol_clk_core_clk 0xf6fb0df7 +#define clk_gcc_usb20_master_clk 0x24c3b66a +#define clk_gcc_usb20_mock_utmi_clk 0xe8db8203 +#define clk_gcc_usb20_sleep_clk 0x6e8cb4b2 +#define clk_gcc_usb30_master_clk 0xb3b4e2cb +#define clk_gcc_usb30_mock_utmi_clk 0xa800b65a +#define clk_gcc_usb30_sleep_clk 0xd0b65c92 +#define clk_gcc_usb3_phy_aux_clk 0x0d9a36e0 +#define clk_gcc_usb3_phy_pipe_clk 0xf279aff2 +#define clk_gcc_usb_phy_cfg_ahb2phy_clk 0xd1231a0e +#define clk_gcc_aggre0_cnoc_ahb_clk 0x53a35559 +#define clk_gcc_aggre0_snoc_axi_clk 0x3c446400 +#define clk_gcc_aggre0_noc_qosgen_extref_clk 0x8c4356ba +#define clk_hlos1_vote_lpass_core_smmu_clk 0x3aaa1743 +#define clk_hlos1_vote_lpass_adsp_smmu_clk 0xc76f702f +#define clk_gcc_usb3_phy_reset 0x03d559f1 +#define clk_gcc_usb3phy_phy_reset 0xb1a4f885 +#define clk_gcc_usb3_clkref_clk 0xb6cc8f01 +#define clk_gcc_hdmi_clkref_clk 0x4d4eec04 +#define clk_gcc_edp_clkref_clk 0xa8685c3f +#define clk_gcc_ufs_clkref_clk 0x92aa126f +#define clk_gcc_pcie_clkref_clk 0xa2e247fa +#define clk_gcc_rx2_usb2_clkref_clk 0x27ec24ba +#define clk_gcc_rx1_usb2_clkref_clk 0x53351d25 +#define clk_gcc_smmu_aggre0_ahb_clk 0x47a06ce4 +#define clk_gcc_smmu_aggre0_axi_clk 0x3cac4a6c +#define clk_gcc_sys_noc_usb3_axi_clk 0x94d26800 +#define clk_gcc_sys_noc_ufs_axi_clk 0x19d38312 +#define clk_gcc_aggre2_usb3_axi_clk 0xd5822a8e +#define clk_gcc_aggre2_ufs_axi_clk 0xb31e5191 +#define clk_gcc_mmss_gpll0_div_clk 0xdd06848d +#define clk_gcc_mmss_bimc_gfx_clk 0xe4f28754 +#define clk_gcc_bimc_gfx_clk 0x3edd69ad +#define clk_gcc_qspi_ahb_clk 0x96969dc8 +#define clk_gcc_qspi_ser_clk 0xfaf1e266 +#define clk_qspi_ser_clk_src 0x426676ee +#define clk_sdcc1_ice_core_clk_src 0xfd6a4301 +#define clk_gcc_sdcc1_ice_core_clk 0x0fd5680a +#define clk_gcc_mss_cfg_ahb_clk 0x111cde81 +#define clk_gcc_mss_snoc_axi_clk 0x0e71de85 +#define clk_gcc_mss_q6_bimc_axi_clk 0x67544d62 +#define clk_gcc_mss_mnoc_bimc_axi_clk 0xf665d03f +#define clk_gpll0_out_msscc 0x7d794829 +#define clk_gcc_debug_mux_v2 0xf7e749f0 +#define clk_gcc_dcc_ahb_clk 0xfa14a88c +#define clk_gcc_aggre0_noc_mpu_cfg_ahb_clk 0x5c1bb8e2 + +/* clock_mmss controlled clocks */ +#define clk_mmsscc_xo 0x05e63704 +#define clk_mmsscc_gpll0 0xe900c515 +#define clk_mmsscc_gpll0_div 0x73892e05 +#define clk_mmsscc_mmssnoc_ahb 0x7b4bd6f7 +#define clk_mmpll0 0xdd83b751 +#define clk_mmpll0_out_main 0x2f996a31 +#define clk_mmpll1 0x6da7fb90 +#define clk_mmpll1_out_main 0xa0d3a7da +#define clk_mmpll4 0x22c063c1 +#define clk_mmpll4_out_main 0xfb21c2fd +#define clk_mmpll3 0x18c76899 +#define clk_mmpll3_out_main 0x6eb6328f +#define clk_ahb_clk_src 0x86f49203 +#define clk_mmpll2 0x1190e4d8 +#define clk_mmpll2_out_main 0x1e9e24a8 +#define clk_mmpll8 0xd06ad45e +#define clk_mmpll8_out_main 0x75b1f386 +#define clk_mmpll9 0x1c50684c +#define clk_mmpll9_out_main 0x16b74937 +#define clk_mmpll5 0xa41e1936 +#define clk_mmpll5_out_main 0xcc1897bf +#define clk_csi0_clk_src 0x227e65bc +#define clk_vfe0_clk_src 0xa0c2bd8f +#define clk_vfe1_clk_src 0x4e357366 +#define clk_csi1_clk_src 0x6a2a6c36 +#define clk_csi2_clk_src 0x4113589f +#define clk_csi3_clk_src 0xfd934012 +#define clk_maxi_clk_src 0x52c09777 +#define clk_cpp_clk_src 0x8382f56d +#define clk_jpeg0_clk_src 0x9a0a0ac3 +#define clk_jpeg2_clk_src 0x5ad927f3 +#define clk_jpeg_dma_clk_src 0xb68afcea +#define clk_mdp_clk_src 0x6dc1f8f1 +#define clk_video_core_clk_src 0x8be4c944 +#define clk_fd_core_clk_src 0xe4799ab7 +#define clk_cci_clk_src 0x822f3d97 +#define clk_csiphy0_3p_clk_src 0xd2474b12 +#define clk_csiphy1_3p_clk_src 0x46a02aff +#define clk_csiphy2_3p_clk_src 0x1447813f +#define clk_camss_gp0_clk_src 0x6b57cfe6 +#define clk_camss_gp1_clk_src 0xf735368a +#define clk_jpeg_dma_clk_src 0xb68afcea +#define clk_mclk0_clk_src 0x266b3853 +#define clk_mclk1_clk_src 0xa73cad0c +#define clk_mclk2_clk_src 0x42545468 +#define clk_mclk3_clk_src 0x2bfbb714 +#define clk_csi0phytimer_clk_src 0xc8a309be +#define clk_csi1phytimer_clk_src 0x7c0fe23a +#define clk_csi2phytimer_clk_src 0x62ffea9c +#define clk_rbbmtimer_clk_src 0x17649ecc +#define clk_esc0_clk_src 0xb41d7c38 +#define clk_esc1_clk_src 0x3b0afa42 +#define clk_hdmi_clk_src 0xb40aeea9 +#define clk_vsync_clk_src 0xecb43940 +#define clk_rbcpr_clk_src 0x2c2e9af2 +#define clk_video_subcore0_clk_src 0x88d79636 +#define clk_video_subcore1_clk_src 0x4966930c +#define clk_mmss_bto_ahb_clk 0xfdf8c361 +#define clk_camss_ahb_clk 0xc4ff91d4 +#define clk_camss_cci_ahb_clk 0x04c4441a +#define clk_camss_cci_clk 0xd6cb5eb9 +#define clk_camss_cpp_ahb_clk 0x12e9a87b +#define clk_camss_cpp_clk 0xb82f366b +#define clk_camss_cpp_axi_clk 0x5598c804 +#define clk_camss_cpp_vbif_ahb_clk 0xb5f31be4 +#define clk_camss_csi0_ahb_clk 0x6e29c972 +#define clk_camss_csi0_clk 0x30862ddb +#define clk_camss_csi0phy_clk 0x2cecfb84 +#define clk_camss_csi0pix_clk 0x6946f77b +#define clk_camss_csi0rdi_clk 0x83645ef5 +#define clk_camss_csi1_ahb_clk 0xccc15f06 +#define clk_camss_csi1_clk 0xb150f052 +#define clk_camss_csi1phy_clk 0xb989f06d +#define clk_camss_csi1pix_clk 0x58d19bf3 +#define clk_camss_csi1rdi_clk 0x4d2f3352 +#define clk_camss_csi2_ahb_clk 0x92d02d75 +#define clk_camss_csi2_clk 0x74fc92e8 +#define clk_camss_csi2phy_clk 0xda05d9d8 +#define clk_camss_csi2pix_clk 0xf8ed0731 +#define clk_camss_csi2rdi_clk 0xdc1b2081 +#define clk_camss_csi3_ahb_clk 0xee5e459c +#define clk_camss_csi3_clk 0x39488fdd +#define clk_camss_csi3phy_clk 0x8b6063b9 +#define clk_camss_csi3pix_clk 0xd82bd467 +#define clk_camss_csi3rdi_clk 0xb6750046 +#define clk_camss_csi_vfe0_clk 0x3023937a +#define clk_camss_csi_vfe1_clk 0xe66fa522 +#define clk_camss_csiphy0_3p_clk 0xf2a54f5a +#define clk_camss_csiphy1_3p_clk 0x8bf70cb2 +#define clk_camss_csiphy2_3p_clk 0x1c14c939 +#define clk_camss_gp0_clk 0xcee7e51d +#define clk_camss_gp1_clk 0x41f1c2e3 +#define clk_camss_ispif_ahb_clk 0x9a212c6d +#define clk_camss_jpeg0_clk 0x0b0e2db7 +#define clk_camss_jpeg2_clk 0xd7291c8d +#define clk_camss_jpeg_ahb_clk 0x1f47fd28 +#define clk_camss_jpeg_axi_clk 0x9e5545c8 +#define clk_camss_jpeg_dma_clk 0x2336e65d +#define clk_camss_mclk0_clk 0xcf0c61e0 +#define clk_camss_mclk1_clk 0xd1410ed4 +#define clk_camss_mclk2_clk 0x851286f2 +#define clk_camss_mclk3_clk 0x4db11c45 +#define clk_camss_micro_ahb_clk 0x33a23277 +#define clk_camss_csi0phytimer_clk 0xff93b3c8 +#define clk_camss_csi1phytimer_clk 0x6c399ab6 +#define clk_camss_csi2phytimer_clk 0x24f47f49 +#define clk_camss_top_ahb_clk 0x8f8b2d33 +#define clk_camss_vfe_ahb_clk 0x595197bc +#define clk_camss_vfe_axi_clk 0x273d4c31 +#define clk_camss_vfe0_ahb_clk 0x4652833c +#define clk_camss_vfe0_clk 0x1e9bb8c4 +#define clk_camss_vfe0_stream_clk 0x22835fa4 +#define clk_camss_vfe1_ahb_clk 0x6a56abd3 +#define clk_camss_vfe1_clk 0x5bffa69b +#define clk_camss_vfe1_stream_clk 0x92f849b9 +#define clk_fd_ahb_clk 0x868a2c5c +#define clk_fd_core_clk 0x3badcae4 +#define clk_fd_core_uar_clk 0x7e624e15 +#define clk_gpu_ahb_clk 0xf97f1d43 +#define clk_gpu_aon_isense_clk 0xa9e9b297 +#define clk_gpu_gx_gfx3d_clk 0xb7ece823 +#define clk_gpu_mx_clk 0xb80ccedf +#define clk_gpu_gx_rbbmtimer_clk 0xdeba634e +#define clk_mdss_ahb_clk 0x684ccb41 +#define clk_mdss_axi_clk 0xcc07d687 +#define clk_mdss_esc0_clk 0x28cafbe6 +#define clk_mdss_esc1_clk 0xc22c6883 +#define clk_mdss_hdmi_ahb_clk 0x01cef516 +#define clk_mdss_hdmi_clk 0x097a6de9 +#define clk_mdss_mdp_clk 0x618336ac +#define clk_mdss_vsync_clk 0x42a022d3 +#define clk_mmss_misc_ahb_clk 0xea30b0e7 +#define clk_mmss_misc_cxo_clk 0xe620cd80 +#define clk_mmagic_bimc_noc_cfg_ahb_clk 0x12d5ba72 +#define clk_mmagic_camss_axi_clk 0xa8b1c16b +#define clk_mmagic_camss_noc_cfg_ahb_clk 0x5182c819 +#define clk_mmss_mmagic_cfg_ahb_clk 0x5e94a822 +#define clk_mmagic_mdss_axi_clk 0xa0359d10 +#define clk_mmagic_mdss_noc_cfg_ahb_clk 0x9c6d5482 +#define clk_mmagic_video_axi_clk 0x7b9219c3 +#define clk_mmagic_video_noc_cfg_ahb_clk 0x5124d256 +#define clk_mmss_mmagic_ahb_clk 0x3d15f2b0 +#define clk_mmss_mmagic_maxi_clk 0xbdaf5af7 +#define clk_mmss_rbcpr_ahb_clk 0x623ba55f +#define clk_mmss_rbcpr_clk 0x69a23a6f +#define clk_mmss_spdm_cpp_clk 0xefe35cd2 +#define clk_mmss_spdm_jpeg_dma_clk 0xcb7bd5a0 +#define clk_smmu_cpp_ahb_clk 0x3ad82d84 +#define clk_smmu_cpp_axi_clk 0xa6bb2f4a +#define clk_smmu_jpeg_ahb_clk 0x10c436ec +#define clk_smmu_jpeg_axi_clk 0x41112f37 +#define clk_smmu_mdp_ahb_clk 0x04994cb2 +#define clk_smmu_mdp_axi_clk 0x7fd71687 +#define clk_smmu_rot_ahb_clk 0xa30772c9 +#define clk_smmu_rot_axi_clk 0xfed7c078 +#define clk_smmu_vfe_ahb_clk 0x4dabebe7 +#define clk_smmu_vfe_axi_clk 0xde483725 +#define clk_smmu_video_ahb_clk 0x2d738e2c +#define clk_smmu_video_axi_clk 0xe2b5b887 +#define clk_video_ahb_clk 0x90775cfb +#define clk_video_axi_clk 0xe6c16dba +#define clk_video_core_clk 0x7e876ec3 +#define clk_video_maxi_clk 0x97749db6 +#define clk_video_subcore0_clk 0xb6f63e6c +#define clk_video_subcore1_clk 0x26c29cb4 +#define clk_vmem_ahb_clk 0xab6223ff +#define clk_vmem_maxi_clk 0x15ef32db +#define clk_mmss_debug_mux 0xe646ffda +#define clk_mmss_gcc_dbg_clk 0xafa4d48a +#define clk_gfx3d_clk_src 0x917f76ef +#define clk_extpclk_clk_src 0xb2c31abd +#define clk_mdss_byte0_clk 0xf5a03f64 +#define clk_mdss_byte1_clk 0xb8c7067d +#define clk_mdss_extpclk_clk 0xfa5aadb0 +#define clk_mdss_pclk0_clk 0x3487234a +#define clk_mdss_pclk1_clk 0xd5804246 +#define clk_gpu_gcc_dbg_clk 0x0ccc42cd +#define clk_mdss_mdp_vote_clk 0x588460a4 +#define clk_mdss_rotator_vote_clk 0x5b1f675e +#define clk_mmpll2_postdiv_clk 0x4fdeaaba +#define clk_mmpll8_postdiv_clk 0xedf57882 +#define clk_mmpll9_postdiv_clk 0x3064b618 +#define clk_gfx3d_clk_src_v2 0x4210acb7 +#define clk_byte0_clk_src 0x75cc885b +#define clk_byte1_clk_src 0x63c2c955 +#define clk_pclk0_clk_src 0xccac1f35 +#define clk_pclk1_clk_src 0x090f68ac +#define clk_ext_byte0_clk_src 0xfb32f31e +#define clk_ext_byte1_clk_src 0x585ef6d4 +#define clk_ext_pclk0_clk_src 0x087c1612 +#define clk_ext_pclk1_clk_src 0x8067c5a3 + +/* clock_debug controlled clocks */ +#define clk_gcc_debug_mux 0x8121ac15 + +/* external multimedia clocks */ +#define clk_dsi0pll_pixel_clk_mux 0x792379e1 +#define clk_dsi0pll_byte_clk_mux 0x60e83f06 +#define clk_dsi0pll_byte_clk_src 0xbbaa30be +#define clk_dsi0pll_pixel_clk_src 0x45b3260f +#define clk_dsi0pll_n2_div_clk 0x1474c213 +#define clk_dsi0pll_post_n1_div_clk 0xdab8c389 +#define clk_dsi0pll_vco_clk 0x15940d40 +#define clk_dsi1pll_pixel_clk_mux 0x36458019 +#define clk_dsi1pll_byte_clk_mux 0xb5a42b7b +#define clk_dsi1pll_byte_clk_src 0x63930a8f +#define clk_dsi1pll_pixel_clk_src 0x0e4c9b56 +#define clk_dsi1pll_n2_div_clk 0x2c9d4007 +#define clk_dsi1pll_post_n1_div_clk 0x03020041 +#define clk_dsi1pll_vco_clk 0x99797b50 +#define clk_mdss_dsi1_vco_clk_src 0xfcd15658 +#define clk_hdmi_vco_clk 0x66003284 + +#define clk_dsi0pll_shadow_byte_clk_src 0x177c029c +#define clk_dsi0pll_shadow_pixel_clk_src 0x98ae3c92 +#define clk_dsi0pll_shadow_n2_div_clk 0xd5f0dad9 +#define clk_dsi0pll_shadow_post_n1_div_clk 0x1f7c8cf8 +#define clk_dsi0pll_shadow_vco_clk 0xb100ca83 +#define clk_dsi1pll_shadow_byte_clk_src 0xfc021ce5 +#define clk_dsi1pll_shadow_pixel_clk_src 0xdcca3ffc +#define clk_dsi1pll_shadow_n2_div_clk 0x189541bf +#define clk_dsi1pll_shadow_post_n1_div_clk 0x1637020e +#define clk_dsi1pll_shadow_vco_clk 0x68d8b6f7 + +/* CPU clocks */ +#define clk_pwrcl_clk 0xc554130e +#define clk_pwrcl_pll 0x25454ca1 +#define clk_pwrcl_alt_pll 0xc445471b +#define clk_pwrcl_pll_main 0x28948e22 +#define clk_pwrcl_alt_pll_main 0x25c8270e +#define clk_pwrcl_hf_mux 0x77706ae6 +#define clk_pwrcl_lf_mux 0xd99e334d +#define clk_perfcl_clk 0x58869997 +#define clk_perfcl_pll 0x97dcec1c +#define clk_perfcl_alt_pll 0xfe2eaea1 +#define clk_perfcl_pll_main 0x0dbf0c0b +#define clk_perfcl_alt_pll_main 0x0b892aab +#define clk_perfcl_hf_mux 0x9e8bbe59 +#define clk_perfcl_lf_mux 0x2f9c278d +#define clk_cbf_pll 0xfe2e96a3 +#define clk_cbf_pll_main 0x2b05cf95 +#define clk_cbf_hf_mux 0x71244f73 +#define clk_cbf_clk 0x48e9e16b +#define clk_xo_ao 0x428c856d +#define clk_sys_apcsaux_clk 0x0b0dd513 +#define clk_cpu_debug_mux 0xc7acaa31 + +/* GCC block resets */ +#define QUSB2PHY_PRIM_BCR 0 +#define QUSB2PHY_SEC_BCR 1 +#define BLSP1_BCR 2 +#define BLSP2_BCR 3 +#define BOOT_ROM_BCR 4 +#define PRNG_BCR 5 +#define UFS_BCR 6 +#define USB_20_BCR 7 +#define USB_30_BCR 8 +#define USB3_PHY_BCR 9 +#define USB3PHY_PHY_BCR 10 +#define PCIE_0_PHY_BCR 11 +#define PCIE_1_PHY_BCR 12 +#define PCIE_2_PHY_BCR 13 +#define PCIE_PHY_BCR 14 +#define PCIE_PHY_COM_BCR 15 +#define PCIE_PHY_NOCSR_COM_PHY_BCR 16 + +/* MMSS Block resets */ +#define VIDEO_BCR 0 +#define MDSS_BCR 1 +#define CAMSS_MICRO_BCR 2 +#define CAMSS_JPEG_BCR 3 +#define CAMSS_VFE0_BCR 4 +#define CAMSS_VFE1_BCR 5 +#define FD_BCR 6 +#define GPU_GX_BCR 7 + +#endif --- /dev/null 2019-10-24 16:47:25.704025805 +0200 +++ linux-4.4.115-fbx/arch/metag/boot/dts/include/dt-bindings/clock/msm-clocks-8998.h 2019-01-22 16:16:28.171288678 +0100 @@ -0,0 +1,534 @@ +/* Copyright (c) 2015-2017, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __MSM_CLOCKS_8998_H +#define __MSM_CLOCKS_8998_H + +#include "audio-ext-clk.h" + +/* clock_rpm controlled clocks */ +#define clk_ce1_clk 0x42229c55 +#define clk_ce1_a_clk 0x44a833fe +#define clk_cxo_clk_src 0x79e95308 +#define clk_bimc_clk 0x4b80bf00 +#define clk_bimc_a_clk 0x4b25668a +#define clk_cnoc_clk 0xd5ccb7f4 +#define clk_cnoc_a_clk 0xd8fe2ccc +#define clk_snoc_clk 0x2c341aa0 +#define clk_snoc_a_clk 0x8fcef2af +#define clk_cnoc_periph_clk 0xb11e9cf9 +#define clk_cnoc_periph_a_clk 0x1d7faa2e +#define clk_cnoc_periph_keepalive_a_clk 0x7287aef2 +#define clk_ln_bb_clk1 0xb867b147 +#define clk_ln_bb_clk1_ao 0x7f63a93a +#define clk_ln_bb_clk1_pin 0x6fc5653c +#define clk_ln_bb_clk1_pin_ao 0x25d625bf +#define clk_ln_bb_clk2 0xf83e6387 +#define clk_ln_bb_clk2_ao 0x96f09628 +#define clk_ln_bb_clk2_pin 0xa9ebe8d5 +#define clk_ln_bb_clk2_pin_ao 0x89a1226f +#define clk_ln_bb_clk3 0x4f52a39e +#define clk_ln_bb_clk3_ao 0xb15eba76 +#define clk_ln_bb_clk3_pin 0xc4de7dad +#define clk_ln_bb_clk3_pin_ao 0xc01022e8 +#define clk_bimc_msmbus_clk 0xd212feea +#define clk_bimc_msmbus_a_clk 0x71d1a499 +#define clk_cnoc_msmbus_clk 0x62228b5d +#define clk_cnoc_msmbus_a_clk 0x67442955 +#define clk_cxo_clk_src_ao 0x64eb6004 +#define clk_cxo_dwc3_clk 0xf79c19f6 +#define clk_cxo_lpm_clk 0x94adbf3d +#define clk_cxo_otg_clk 0x4eec0bb9 +#define clk_cxo_pil_lpass_clk 0xe17f0ff6 +#define clk_cxo_pil_ssc_clk 0x81832015 +#define clk_cxo_pil_spss_clk 0x5cd71a61 +#define clk_div_clk1 0xaa1157a6 +#define clk_div_clk1_ao 0x6b943d68 +#define clk_div_clk2 0xd454019f +#define clk_div_clk2_ao 0x53f9e788 +#define clk_div_clk3 0xa9a55a68 +#define clk_div_clk3_ao 0x3d6725a8 +#define clk_ipa_clk 0xfa685cda +#define clk_ipa_a_clk 0xeeec2919 +#define clk_mcd_ce1_clk 0xbb615d26 +#define clk_mmssnoc_axi_clk 0xdb4b31e6 +#define clk_mmssnoc_axi_a_clk 0xd4970614 +#define clk_qcedev_ce1_clk 0x293f97b0 +#define clk_qcrypto_ce1_clk 0xa6ac14df +#define clk_qdss_clk 0x1492202a +#define clk_qdss_a_clk 0xdd121669 +#define clk_qseecom_ce1_clk 0xaa858373 +#define clk_rf_clk1 0xaabeea5a +#define clk_rf_clk1_ao 0x72a10cb8 +#define clk_rf_clk1_pin 0x8f463562 +#define clk_rf_clk1_pin_ao 0x62549ff6 +#define clk_rf_clk2 0x24a30992 +#define clk_rf_clk2_ao 0x944d8bbd +#define clk_rf_clk2_pin 0xa7c5602a +#define clk_rf_clk2_pin_ao 0x2d75eb4d +#define clk_rf_clk3 0xb673936b +#define clk_rf_clk3_ao 0x038bb968 +#define clk_rf_clk3_pin 0x726f53f5 +#define clk_rf_clk3_pin_ao 0x76f9240f +#define clk_scm_ce1_clk 0xd8ebcc62 +#define clk_snoc_msmbus_clk 0xe6900bb6 +#define clk_snoc_msmbus_a_clk 0x5d4683bd +#define clk_gcc_ce1_ahb_m_clk 0x2eb28c01 +#define clk_gcc_ce1_axi_m_clk 0xc174dfba +#define clk_aggre1_noc_clk 0x049abba8 +#define clk_aggre1_noc_a_clk 0xc12e4220 +#define clk_aggre2_noc_clk 0xaa681404 +#define clk_aggre2_noc_a_clk 0xcab67089 +#define clk_measure_only_bimc_hmss_axi_clk 0xc1cc4f11 + +/* clock_gcc controlled clocks*/ +#define clk_debug_mmss_clk 0x977c99b6 +#define clk_debug_rpm_clk 0x8e2b07ca +#define clk_debug_cpu_clk 0x0e696b2b +#define clk_gpu_gcc_debug_clk 0x3eb88190 +#define clk_gfx_gcc_debug_clk 0xa3a64fec +#define clk_gpll0 0x1ebe3bc4 +#define clk_gpll0_out_main 0xe9374de7 +#define clk_gpll0_ao 0xa1368304 +#define clk_gcc_mmss_gpll0_clk 0x8050f008 +#define clk_gcc_mmss_gpll0_div_clk 0xdd06848d +#define clk_gcc_gpu_gpll0_clk 0xdad7a7a4 +#define clk_gcc_gpu_gpll0_div_clk 0x07d16c6a +#define clk_gpll4 0xb3b5d85b +#define clk_gpll4_out_main 0xa9a0ab9d +#define clk_usb30_master_clk_src 0xc6262f89 +#define clk_pcie_aux_clk_src 0xebc50566 +#define clk_ufs_axi_clk_src 0x297ca380 +#define clk_blsp1_qup1_i2c_apps_clk_src 0x17f78f5e +#define clk_blsp1_qup1_spi_apps_clk_src 0xf534c4fa +#define clk_blsp1_qup2_i2c_apps_clk_src 0x8de71c79 +#define clk_blsp1_qup2_spi_apps_clk_src 0x33cf809a +#define clk_blsp1_qup3_i2c_apps_clk_src 0xf161b902 +#define clk_blsp1_qup3_spi_apps_clk_src 0x5e95683f +#define clk_blsp1_qup4_i2c_apps_clk_src 0xb2ecce68 +#define clk_blsp1_qup4_spi_apps_clk_src 0xddb5bbdb +#define clk_blsp1_qup5_i2c_apps_clk_src 0x71ea7804 +#define clk_blsp1_qup5_spi_apps_clk_src 0x9752f35f +#define clk_blsp1_qup6_i2c_apps_clk_src 0x28806803 +#define clk_blsp1_qup6_spi_apps_clk_src 0x44a1edc4 +#define clk_blsp1_uart1_apps_clk_src 0xf8146114 +#define clk_blsp1_uart2_apps_clk_src 0xfc9c2f73 +#define clk_blsp1_uart3_apps_clk_src 0x600497f2 +#define clk_blsp2_qup1_i2c_apps_clk_src 0xd6d1e95d +#define clk_blsp2_qup1_spi_apps_clk_src 0xcc1b8365 +#define clk_blsp2_qup2_i2c_apps_clk_src 0x603b5c51 +#define clk_blsp2_qup2_spi_apps_clk_src 0xd577dc44 +#define clk_blsp2_qup3_i2c_apps_clk_src 0xea82959c +#define clk_blsp2_qup3_spi_apps_clk_src 0xd04b1e92 +#define clk_blsp2_qup4_i2c_apps_clk_src 0x73dc968c +#define clk_blsp2_qup4_spi_apps_clk_src 0x25d4a2b1 +#define clk_blsp2_qup5_i2c_apps_clk_src 0xcc3698bd +#define clk_blsp2_qup5_spi_apps_clk_src 0xfa0cf45e +#define clk_blsp2_qup6_i2c_apps_clk_src 0x2fa53151 +#define clk_blsp2_qup6_spi_apps_clk_src 0x5ca86755 +#define clk_blsp2_uart1_apps_clk_src 0x562c66dc +#define clk_blsp2_uart2_apps_clk_src 0xdd448080 +#define clk_blsp2_uart3_apps_clk_src 0x46b2e90f +#define clk_gp1_clk_src 0xad85b97a +#define clk_gp2_clk_src 0xfb1f0065 +#define clk_gp3_clk_src 0x63b693d6 +#define clk_hmss_rbcpr_clk_src 0xedd9a474 +#define clk_pdm2_clk_src 0x31e494fd +#define clk_sdcc2_apps_clk_src 0xfc46c821 +#define clk_sdcc4_apps_clk_src 0x7aaaaa0c +#define clk_tsif_ref_clk_src 0x4e9042d1 +#define clk_ufs_ice_core_clk_src 0xda8e7119 +#define clk_ufs_phy_aux_clk_src 0xc6bca085 +#define clk_ufs_unipro_core_clk_src 0x179e80a9 +#define clk_usb30_mock_utmi_clk_src 0xa024a976 +#define clk_usb3_phy_aux_clk_src 0x15eec63c +#define clk_qspi_ref_clk_src 0xfe6b8e11 +#define clk_gcc_pcie_phy_0_reset 0x6bb4df33 +#define clk_gcc_usb3_phy_reset 0x03d559f1 +#define clk_gcc_usb3phy_phy_reset 0xb1a4f885 +#define clk_gcc_aggre1_ufs_axi_clk 0x873459d8 +#define clk_gcc_aggre1_ufs_axi_hw_ctl_clk 0x117a6f39 +#define clk_gcc_aggre1_usb3_axi_clk 0xc5c3fbe8 +#define clk_gcc_bimc_mss_q6_axi_clk 0x7437988f +#define clk_gcc_blsp1_ahb_clk 0x8caa5b4f +#define clk_gcc_blsp1_qup1_i2c_apps_clk 0xc303fae9 +#define clk_gcc_blsp1_qup1_spi_apps_clk 0x759a76b0 +#define clk_gcc_blsp1_qup2_i2c_apps_clk 0x1076f220 +#define clk_gcc_blsp1_qup2_spi_apps_clk 0x3e77d48f +#define clk_gcc_blsp1_qup3_i2c_apps_clk 0x9e25ac82 +#define clk_gcc_blsp1_qup3_spi_apps_clk 0xfb978880 +#define clk_gcc_blsp1_qup4_i2c_apps_clk 0xd7f40f6f +#define clk_gcc_blsp1_qup4_spi_apps_clk 0x80f8722f +#define clk_gcc_blsp1_qup5_i2c_apps_clk 0xacae5604 +#define clk_gcc_blsp1_qup5_spi_apps_clk 0xbf3e15d7 +#define clk_gcc_blsp1_qup6_i2c_apps_clk 0x5c6ad820 +#define clk_gcc_blsp1_qup6_spi_apps_clk 0x780d9f85 +#define clk_gcc_blsp1_uart1_apps_clk 0xc7c62f90 +#define clk_gcc_blsp1_uart2_apps_clk 0xf8a61c96 +#define clk_gcc_blsp1_uart3_apps_clk 0xc3298bd7 +#define clk_gcc_blsp2_ahb_clk 0x8f283c1d +#define clk_gcc_blsp2_qup1_i2c_apps_clk 0x9ace11dd +#define clk_gcc_blsp2_qup1_spi_apps_clk 0xa32604cc +#define clk_gcc_blsp2_qup2_i2c_apps_clk 0x1bf9a57e +#define clk_gcc_blsp2_qup2_spi_apps_clk 0xbf54ca6d +#define clk_gcc_blsp2_qup3_i2c_apps_clk 0x336d4170 +#define clk_gcc_blsp2_qup3_spi_apps_clk 0xc68509d6 +#define clk_gcc_blsp2_qup4_i2c_apps_clk 0xbd22539d +#define clk_gcc_blsp2_qup4_spi_apps_clk 0x01a72b93 +#define clk_gcc_blsp2_qup5_i2c_apps_clk 0xe2b2ce1d +#define clk_gcc_blsp2_qup5_spi_apps_clk 0xf40999cd +#define clk_gcc_blsp2_qup6_i2c_apps_clk 0x894bcea4 +#define clk_gcc_blsp2_qup6_spi_apps_clk 0xfe1bd34a +#define clk_gcc_blsp2_uart1_apps_clk 0x8c3512ff +#define clk_gcc_blsp2_uart2_apps_clk 0x1e1965a3 +#define clk_gcc_blsp2_uart3_apps_clk 0x382415ab +#define clk_gcc_boot_rom_ahb_clk 0xde2adeb1 +#define clk_gcc_bimc_gfx_clk 0x3edd69ad +#define clk_gcc_cfg_noc_usb3_axi_clk 0x9ea4c2d9 +#define clk_gcc_gp1_clk 0x057f7b69 +#define clk_gcc_gp2_clk 0x9bf83ffd +#define clk_gcc_gp3_clk 0xec6539ee +#define clk_gcc_gpu_bimc_gfx_clk 0x3909459b +#define clk_gcc_gpu_cfg_ahb_clk 0x72f20a57 +#define clk_gcc_gpu_iref_clk 0xfd82abad +#define clk_gcc_hmss_dvm_bus_clk 0x17cc8b53 +#define clk_gcc_hmss_rbcpr_clk 0x699183be +#define clk_hmss_gpll0_clk_src 0x17eb05d0 +#define clk_hmss_gpll4_clk_src 0x20456cae +#define clk_gcc_mmss_sys_noc_axi_clk 0x4467b15b +#define clk_gcc_mss_at_clk 0x1692c5aa +#define clk_nav_gcc_dbg_clk 0x2221c544 +#define clk_gcc_pcie_0_aux_clk 0x3d2e3ece +#define clk_gcc_pcie_0_cfg_ahb_clk 0x4dd325c3 +#define clk_gcc_pcie_0_mstr_axi_clk 0x3f85285b +#define clk_gcc_pcie_0_pipe_clk 0x4f37621e +#define clk_gcc_pcie_0_slv_axi_clk 0xd69638a1 +#define clk_gcc_pcie_phy_aux_clk 0x4746e74f +#define clk_gcc_pdm2_clk 0x99d55711 +#define clk_gcc_pdm_ahb_clk 0x365664f6 +#define clk_gcc_prng_ahb_clk 0x397e7eaa +#define clk_gcc_sdcc2_ahb_clk 0x23d5727f +#define clk_gcc_sdcc2_apps_clk 0x861b20ac +#define clk_gcc_sdcc4_ahb_clk 0x64f3e6a8 +#define clk_gcc_sdcc4_apps_clk 0xbf7c4dc8 +#define clk_gcc_tsif_ahb_clk 0x88d2822c +#define clk_gcc_tsif_ref_clk 0x8f1ed2c2 +#define clk_gcc_ufs_ahb_clk 0x1914bb84 +#define clk_gcc_ufs_axi_clk 0x47c743a7 +#define clk_gcc_ufs_axi_hw_ctl_clk 0x69385b45 +#define clk_gcc_ufs_ice_core_clk 0x310b0710 +#define clk_gcc_ufs_ice_core_hw_ctl_clk 0x84e15a5b +#define clk_gcc_ufs_phy_aux_clk 0x17acc8fb +#define clk_gcc_ufs_phy_aux_hw_ctl_clk 0x7dbdb2e2 +#define clk_gcc_ufs_rx_symbol_0_clk 0x7f43251c +#define clk_gcc_ufs_rx_symbol_1_clk 0x03182fde +#define clk_gcc_ufs_tx_symbol_0_clk 0x6a9f747a +#define clk_ufs_tx_symbol_0_clk 0xb3fcd0f7 +#define clk_ufs_rx_symbol_0_clk 0x17a0f1cd +#define clk_gcc_ufs_unipro_core_clk 0x2daf7fd2 +#define clk_gcc_ufs_unipro_core_hw_ctl_clk 0x4a4e0f3d +#define clk_gcc_usb30_master_clk 0xb3b4e2cb +#define clk_gcc_usb30_mock_utmi_clk 0xa800b65a +#define clk_gcc_usb30_sleep_clk 0xd0b65c92 +#define clk_gcc_usb3_phy_aux_clk 0x0d9a36e0 +#define clk_gcc_usb3_phy_pipe_clk 0xf279aff2 +#define clk_gcc_usb3_clkref_clk 0xb6cc8f00 +#define clk_gcc_hdmi_clkref_clk 0x4d4eec04 +#define clk_gcc_edp_clkref_clk 0xa8685c3f +#define clk_gcc_ufs_clkref_clk 0x92aa126f +#define clk_gcc_pcie_clkref_clk 0xa2e247fa +#define clk_gcc_rx2_qlink_clkref_clk 0xd0ba986d +#define clk_gcc_rx1_usb2_clkref_clk 0x53351d25 +#define clk_gcc_pcie_phy_reset 0x9bc3c959 +#define clk_gcc_pcie_phy_com_reset 0x8bf513e6 +#define clk_gcc_pcie_phy_nocsr_com_phy_reset 0x0c16a2da +#define clk_gcc_qusb2phy_prim_reset 0x07550fa1 +#define clk_gcc_qusb2phy_sec_reset 0x3f3a87d0 +#define clk_gcc_mmss_noc_cfg_ahb_clk 0xb41a9d99 +#define clk_gcc_dcc_ahb_clk 0xfa14a88c +#define clk_hlos1_vote_lpass_core_smmu_clk 0x3aaa1743 +#define clk_hlos1_vote_lpass_adsp_smmu_clk 0xc76f702f +#define clk_gcc_mss_cfg_ahb_clk 0x111cde81 +#define clk_gcc_mss_q6_bimc_axi_clk 0x67544d62 +#define clk_gcc_mss_mnoc_bimc_axi_clk 0xf665d03f +#define clk_gpll0_out_msscc 0x7d794829 +#define clk_gcc_mss_snoc_axi_clk 0x0e71de85 +#define clk_gcc_qspi_ref_clk 0x766a0f7c +#define clk_gcc_qspi_ahb_clk 0x96969dc8 +#define clk_gcc_debug_mux 0x8121ac15 + +/* clock_mmss controlled clocks */ +#define clk_mmsscc_xo 0x05e63704 +#define clk_mmsscc_gpll0 0xe900c515 +#define clk_mmsscc_gpll0_div 0x73892e05 +#define clk_mmpll0_pll 0x361e3cfd +#define clk_mmpll1_pll 0x198e426b +#define clk_mmpll3_pll 0x18c76899 +#define clk_mmpll4_pll 0x22c063c1 +#define clk_mmpll5_pll 0xa41e1936 +#define clk_mmpll6_pll 0xc56fb440 +#define clk_mmpll7_pll 0x3ac216af +#define clk_mmpll10_pll 0x2561263b +#define clk_mmpll0_pll_out 0x1e9e24a8 +#define clk_mmpll1_pll_out 0x5fa32257 +#define clk_mmpll3_pll_out 0x6eb6328f +#define clk_mmpll4_pll_out 0xfb21c2fd +#define clk_mmpll5_pll_out 0xcc1897bf +#define clk_mmpll6_pll_out 0xfb1060bd +#define clk_mmpll7_pll_out 0x767758ed +#define clk_mmpll10_pll_out 0x3c5668f3 +#define clk_ahb_clk_src 0x86f49203 +#define clk_csi0_clk_src 0x227e65bc +#define clk_vfe0_clk_src 0xa0c2bd8f +#define clk_vfe1_clk_src 0x4e357366 +#define clk_mdp_clk_src 0x6dc1f8f1 +#define clk_maxi_clk_src 0x52c09777 +#define clk_cpp_clk_src 0x8382f56d +#define clk_jpeg0_clk_src 0x9a0a0ac3 +#define clk_rot_clk_src 0xce49b56c +#define clk_video_core_clk_src 0x8be4c944 +#define clk_csi1_clk_src 0x6a2a6c36 +#define clk_csi2_clk_src 0x4113589f +#define clk_csi3_clk_src 0xfd934012 +#define clk_fd_core_clk_src 0xe4799ab7 +#define clk_ext_dp_phy_pll_vco 0x441b576b +#define clk_ext_dp_phy_pll_link 0xea12644c +#define clk_dp_link_clk_src 0x370d0626 +#define clk_dp_crypto_clk_src 0xf8faa811 +#define clk_dp_pixel_clk_src 0xf5dfbabf +#define clk_ext_extpclk_clk_src 0xe5b273af +#define clk_ext_pclk0_clk_src 0x087c1612 +#define clk_ext_pclk1_clk_src 0x8067c5a3 +#define clk_pclk0_clk_src 0xccac1f35 +#define clk_pclk1_clk_src 0x090f68ac +#define clk_video_subcore0_clk_src 0x88d79636 +#define clk_video_subcore1_clk_src 0x4966930c +#define clk_cci_clk_src 0x822f3d97 +#define clk_camss_gp0_clk_src 0x43b063e9 +#define clk_camss_gp1_clk_src 0xa3315f1b +#define clk_mclk0_clk_src 0x266b3853 +#define clk_mclk1_clk_src 0xa73cad0c +#define clk_mclk2_clk_src 0x42545468 +#define clk_mclk3_clk_src 0x2bfbb714 +#define clk_csiphy_clk_src 0x8cceb70a +#define clk_csi0phytimer_clk_src 0xc8a309be +#define clk_csi1phytimer_clk_src 0x7c0fe23a +#define clk_csi2phytimer_clk_src 0x62ffea9c +#define clk_ext_byte0_clk_src 0xfb32f31e +#define clk_ext_byte1_clk_src 0x585ef6d4 +#define clk_byte0_clk_src 0x75cc885b +#define clk_byte1_clk_src 0x63c2c955 +#define clk_dp_aux_clk_src 0x2b6e972b +#define clk_dp_gtc_clk_src 0xc5a86a42 +#define clk_esc0_clk_src 0xb41d7c38 +#define clk_esc1_clk_src 0x3b0afa42 +#define clk_extpclk_clk_src 0xb2c31abd +#define clk_hdmi_clk_src 0xb40aeea9 +#define clk_vsync_clk_src 0xecb43940 +#define clk_mmss_bimc_smmu_ahb_clk 0x4825baf4 +#define clk_mmss_bimc_smmu_axi_clk 0xc365ac39 +#define clk_mmss_snoc_dvm_axi_clk 0x2c159a11 +#define clk_mmss_camss_ahb_clk 0xa51f2c1d +#define clk_mmss_camss_cci_ahb_clk 0xfda8bb6a +#define clk_mmss_camss_cci_clk 0x71bb5c97 +#define clk_mmss_camss_cpp_ahb_clk 0xd5554f15 +#define clk_mmss_camss_cpp_clk 0x8e99ef57 +#define clk_mmss_camss_cpp_axi_clk 0xd84e390b +#define clk_mmss_camss_cpp_vbif_ahb_clk 0x1b33a88e +#define clk_mmss_camss_cphy_csid0_clk 0x56114361 +#define clk_mmss_camss_csi0_ahb_clk 0x2b58d241 +#define clk_mmss_camss_csi0_clk 0xccfe39ef +#define clk_mmss_camss_csi0pix_clk 0x9e26509d +#define clk_mmss_camss_csi0rdi_clk 0x01d5bf83 +#define clk_mmss_camss_cphy_csid1_clk 0x79fbcd8a +#define clk_mmss_camss_csi1_ahb_clk 0x7073244b +#define clk_mmss_camss_csi1_clk 0x3eeeaac0 +#define clk_mmss_camss_csi1pix_clk 0xf1375139 +#define clk_mmss_camss_csi1rdi_clk 0x43185024 +#define clk_mmss_camss_cphy_csid2_clk 0xf295e3ef +#define clk_mmss_camss_csi2_ahb_clk 0x681c1479 +#define clk_mmss_camss_csi2_clk 0x94524569 +#define clk_mmss_camss_csi2pix_clk 0xf4de617d +#define clk_mmss_camss_csi2rdi_clk 0x4bf01dc5 +#define clk_mmss_camss_cphy_csid3_clk 0x100188e9 +#define clk_mmss_camss_csi3_ahb_clk 0xfae7c29b +#define clk_mmss_camss_csi3_clk 0x55e4bbae +#define clk_mmss_camss_csi3pix_clk 0xc166a015 +#define clk_mmss_camss_csi3rdi_clk 0x6983a4cd +#define clk_mmss_camss_csi_vfe0_clk 0x3b30b798 +#define clk_mmss_camss_csi_vfe1_clk 0xfe729af7 +#define clk_mmss_camss_csiphy0_clk 0x96c81af8 +#define clk_mmss_camss_csiphy1_clk 0xee9ac2bb +#define clk_mmss_camss_csiphy2_clk 0x3365e70e +#define clk_mmss_fd_ahb_clk 0x4ff1da4d +#define clk_mmss_fd_core_clk 0x749e7eb0 +#define clk_mmss_fd_core_uar_clk 0x8ea480c5 +#define clk_mmss_camss_gp0_clk 0x3f7f6c87 +#define clk_mmss_camss_gp1_clk 0xdccdd730 +#define clk_mmss_camss_ispif_ahb_clk 0xbda4f0e3 +#define clk_mmss_camss_jpeg0_clk 0x4cc73b07 +#define clk_mmss_camss_jpeg0_vote_clk 0xc9efa6ac +#define clk_mmss_camss_jpeg0_dma_vote_clk 0x371ec109 +#define clk_mmss_camss_jpeg_ahb_clk 0xde1fece3 +#define clk_mmss_camss_jpeg_axi_clk 0x7534616b +#define clk_mmss_camss_mclk0_clk 0x056293a7 +#define clk_mmss_camss_mclk1_clk 0x96c7b69b +#define clk_mmss_camss_mclk2_clk 0x8820556e +#define clk_mmss_camss_mclk3_clk 0xf90ffb67 +#define clk_mmss_camss_micro_ahb_clk 0x6c6fd3c7 +#define clk_mmss_camss_csi0phytimer_clk 0x7a78864e +#define clk_mmss_camss_csi1phytimer_clk 0x6e6c1de5 +#define clk_mmss_camss_csi2phytimer_clk 0x0235e2de +#define clk_mmss_camss_top_ahb_clk 0x120618d6 +#define clk_mmss_camss_vfe0_ahb_clk 0x137bd0bd +#define clk_mmss_camss_vfe0_clk 0xead28288 +#define clk_mmss_camss_vfe0_stream_clk 0xa0428287 +#define clk_mmss_camss_vfe1_ahb_clk 0xac0154c0 +#define clk_mmss_camss_vfe1_clk 0xc216b14d +#define clk_mmss_camss_vfe1_stream_clk 0x745af3b6 +#define clk_mmss_camss_vfe_vbif_ahb_clk 0x0109a9c6 +#define clk_mmss_camss_vfe_vbif_axi_clk 0xe626d8a1 +#define clk_mmss_mdss_ahb_clk 0x85d37ab5 +#define clk_mmss_mdss_axi_clk 0xdf04fc1d +#define clk_mmss_mdss_byte0_clk 0x38105d25 +#define clk_mmss_mdss_byte0_intf_clk 0x38e5aa79 +#define clk_mmss_mdss_byte0_intf_div_clk 0x8604f181 +#define clk_mmss_mdss_byte1_clk 0xe0c21354 +#define clk_mmss_mdss_byte1_intf_clk 0xcf654d8e +#define clk_mmss_mdss_byte1_intf_div_clk 0xcdf334c5 +#define clk_mmss_mdss_dp_aux_clk 0x23125eb6 +#define clk_mmss_mdss_dp_crypto_clk 0x9a072d4e +#define clk_mmss_mdss_dp_link_clk 0x8dd302d1 +#define clk_mmss_mdss_dp_link_intf_clk 0x70e386e6 +#define clk_mmss_mdss_dp_pixel_clk 0xb707b765 +#define clk_mmss_mdss_dp_gtc_clk 0xb59c151a +#define clk_mmss_mdss_esc0_clk 0x5721ff83 +#define clk_mmss_mdss_esc1_clk 0xc3d0376b +#define clk_mmss_mdss_extpclk_clk 0x74d5a954 +#define clk_mmss_mdss_hdmi_clk 0x28460a6d +#define clk_mmss_mdss_hdmi_dp_ahb_clk 0x5448519f +#define clk_mmss_mdss_mdp_clk 0x43539b0e +#define clk_mmss_mdss_mdp_lut_clk 0x00627b2b +#define clk_mmss_mdss_pclk0_clk 0xcc0e909d +#define clk_mmss_mdss_pclk1_clk 0x850d9146 +#define clk_mmss_mdss_rot_clk 0xbb7e71c4 +#define clk_mmss_mdss_vsync_clk 0x629b36dc +#define clk_mmss_misc_ahb_clk 0xea30b0e7 +#define clk_mmss_misc_cxo_clk 0xe620cd80 +#define clk_mmss_mnoc_ahb_clk 0x49a394f4 +#define clk_mmss_mnoc_maxi_clk 0xd8b7278f +#define clk_mmss_video_subcore0_clk 0x23fae359 +#define clk_mmss_video_subcore1_clk 0x5213a0c7 +#define clk_mmss_video_ahb_clk 0x94334ae9 +#define clk_mmss_video_axi_clk 0xf3178ba5 +#define clk_mmss_video_core_clk 0x78f14c85 +#define clk_mmss_video_maxi_clk 0x1785ef88 +#define clk_mmss_vmem_ahb_clk 0x4b18955b +#define clk_mmss_vmem_maxi_clk 0xb6067889 +#define clk_mmss_debug_mux 0xe646ffda + +/* external multimedia clocks */ +#define clk_dsi0pll_byteclk_mux 0xecf2c434 +#define clk_dsi0pll_byteclk_src 0x6f6f740f +#define clk_dsi0pll_pclk_mux 0x6c9da335 +#define clk_dsi0pll_pclk_src 0x5efd85d4 +#define clk_dsi0pll_pclk_src_mux 0x84b14663 +#define clk_dsi0pll_post_bit_div 0xf46dcf27 +#define clk_dsi0pll_pll_out_div1 0xeda5b7fe +#define clk_dsi0pll_pll_out_div2 0x97fa476d +#define clk_dsi0pll_pll_out_div4 0x90a98ce0 +#define clk_dsi0pll_pll_out_div8 0x9d9d85cf +#define clk_dsi0pll_pll_out_mux 0x179c27ca +#define clk_dsi0pll_post_vco_mux 0xfaf9bd1f +#define clk_dsi0pll_post_vco_div1 0xabb50b2a +#define clk_dsi0pll_post_vco_div4 0xbe51c091 +#define clk_dsi0pll_bitclk_src 0x36c3c437 +#define clk_dsi0pll_vco_clk 0x15940d40 + +#define clk_dsi1pll_byteclk_mux 0x14e2f38f +#define clk_dsi1pll_byteclk_src 0x4b65c298 +#define clk_dsi1pll_pclk_mux 0x4c0518b5 +#define clk_dsi1pll_pclk_src 0xeddcd80e +#define clk_dsi1pll_pclk_src_mux 0x3651feb3 +#define clk_dsi1pll_post_bit_div 0x712f0260 +#define clk_dsi1pll_pll_out_div8 0x87628ddb +#define clk_dsi1pll_pll_out_div4 0x0d9a384b +#define clk_dsi1pll_pll_out_div2 0x0c9b5748 +#define clk_dsi1pll_pll_out_div1 0x3193164e +#define clk_dsi1pll_pll_out_mux 0x171bf8fd +#define clk_dsi1pll_post_vco_mux 0xc6a90d20 +#define clk_dsi1pll_post_vco_div1 0x6f47ca7d +#define clk_dsi1pll_post_vco_div4 0x90628974 +#define clk_dsi1pll_bitclk_src 0x13ab045b +#define clk_dsi1pll_vco_clk 0x99797b50 + +#define clk_dp_vco_clk 0xfcaaeec7 +#define clk_dp_link_2x_clk_divsel_five 0xcfe3f5dd +#define clk_vco_divsel_four_clk_src 0xe0da19c0 +#define clk_vco_divsel_two_clk_src 0xb5cfc6a8 +#define clk_vco_divided_clk_src_mux 0x3f8197c2 +#define clk_hdmi_vco_clk 0xbb7dc20d + +/* clock_gpu controlled clocks*/ +#define clk_gpucc_xo 0xc4e1a890 +#define clk_gpucc_gpll0 0x0db0e37f +#define clk_gfx3d_clk_src 0x917f76ef +#define clk_rbbmtimer_clk_src 0x17649ecc +#define clk_gfx3d_isense_clk_src 0xecc3eafa +#define clk_rbcpr_clk_src 0x2c2e9af2 +#define clk_gpu_debug_div_clk 0x75d6f53f +#define clk_gpucc_gfx3d_clk 0x95f01bd5 +#define clk_gpucc_rbbmtimer_clk 0x58a0a7ca +#define clk_gpucc_gfx3d_isense_clk 0xb2678e80 +#define clk_gpucc_cxo_clk 0x6532dcae +#define clk_gpucc_rbcpr_clk 0x7bd750e8 +#define clk_gpu_pll0_pll 0x0e61ab4d +#define clk_gpu_pll0_pll_out_even 0xb0ed5009 +#define clk_gpu_pll0_pll_out_odd 0x08c5a8a5 +#define clk_gpu_pll0_postdiv_clk 0x76c19f3c +#define clk_gpucc_mx_clk 0x1edbb879 +#define clk_gpucc_gcc_dbg_clk 0x9ae8cd3c +#define clk_gfxcc_dbg_clk 0x3ed47625 + +/* CPU clocks */ +#define clk_pwrcl_clk 0xc554130e +#define clk_perfcl_clk 0x58869997 +#define clk_sys_apcsaux_clk_gcc 0xf905e862 +#define clk_xo_ao 0x428c856d +#define clk_osm_clk_src 0xaabe68c3 +#define clk_cpu_debug_mux 0x3ae8bcb2 + +/* Audio External Clocks */ +#define clk_audio_ap_clk 0x9b5727cb +#define clk_audio_pmi_clk 0xcbfe416d +#define clk_audio_ap_clk2 0x454d1e91 + +/* GCC block resets */ +#define QUSB2PHY_PRIM_BCR 0 +#define QUSB2PHY_SEC_BCR 1 +#define BLSP1_BCR 2 +#define BLSP2_BCR 3 +#define BOOT_ROM_BCR 4 +#define PRNG_BCR 5 +#define UFS_BCR 6 +#define USB_30_BCR 7 +#define USB3_PHY_BCR 8 +#define USB3PHY_PHY_BCR 9 +#define PCIE_0_PHY_BCR 10 +#define PCIE_PHY_BCR 11 +#define PCIE_PHY_COM_BCR 12 +#define PCIE_PHY_NOCSR_COM_PHY_BCR 13 + +/* MMSS block resets */ +#define CAMSS_MICRO_BCR 0 + +#endif --- /dev/null 2019-10-24 16:47:25.704025805 +0200 +++ linux-4.4.115-fbx/arch/metag/boot/dts/include/dt-bindings/clock/msm-clocks-hwio-8998.h 2019-01-22 16:16:28.171288678 +0100 @@ -0,0 +1,395 @@ +/* Copyright (c) 2015-2017, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define CLKFLAG_NO_RATE_CACHE 0x00004000 + +#define FMAX_LOWER 0 +#define FMAX_LOW 1 +#define FMAX_NOM 2 +#define FMAX_TURBO 3 + +#define HALT_CHECK_DELAY 5 + +#define RPM_MISC_CLK_TYPE 0x306b6c63 +#define RPM_BUS_CLK_TYPE 0x316b6c63 +#define RPM_MEM_CLK_TYPE 0x326b6c63 +#define RPM_IPA_CLK_TYPE 0x617069 +#define RPM_CE_CLK_TYPE 0x6563 +#define RPM_AGGR_CLK_TYPE 0x72676761 +#define RPM_SMD_KEY_ENABLE 0x62616E45 +#define RPM_MMAXI_CLK_TYPE 0x69786d6d + +#define CXO_CLK_SRC_ID 0x0 +#define QDSS_CLK_ID 0x1 +#define SNOC_CLK_ID 0x1 +#define CNOC_CLK_ID 0x2 +#define CNOC_PERIPH_CLK_ID 0x0 +#define BIMC_CLK_ID 0x0 +#define IPA_CLK_ID 0x0 +#define CE1_CLK_ID 0x0 +#define RF_CLK1_ID 0x4 +#define RF_CLK2_ID 0x5 +#define RF_CLK3_ID 0x6 +#define LN_BB_CLK1_ID 0x1 +#define LN_BB_CLK2_ID 0x2 +#define LN_BB_CLK3_ID 0x3 +#define DIV_CLK1_ID 0xb +#define DIV_CLK2_ID 0xc +#define DIV_CLK3_ID 0xd +#define RF_CLK1_PIN_ID 0x4 +#define RF_CLK2_PIN_ID 0x5 +#define RF_CLK3_PIN_ID 0x6 +#define LN_BB_CLK1_PIN_ID 0x1 +#define LN_BB_CLK2_PIN_ID 0x2 +#define LN_BB_CLK3_PIN_ID 0x3 +#define AGGR1_NOC_ID 0x1 +#define AGGR2_NOC_ID 0x2 +#define MMSSNOC_AXI_CLK_ID 0x0 + +#define APCS_COMMON_LMH_CMD_RCGR 0x0012C + +#define GCC_APCS_GPLL_ENA_VOTE 0x52000 +#define GCC_APCS_CLOCK_BRANCH_ENA_VOTE 0x52004 +#define GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1 0x5200C +#define PLLTEST_PAD_CFG 0x6200C +#define GCC_XO_DIV4_CBCR 0x43008 +#define CLOCK_FRQ_MEASURE_CTL 0x62004 +#define CLOCK_FRQ_MEASURE_STATUS 0x62008 +#define GCC_GPLL0_MODE 0x00000 +#define GCC_GPLL4_MODE 0x77000 +#define GCC_USB30_MASTER_CMD_RCGR 0x0F014 +#define GCC_PCIE_AUX_CMD_RCGR 0x6C000 +#define GCC_UFS_AXI_CMD_RCGR 0x75018 +#define GCC_BLSP1_QUP1_I2C_APPS_CMD_RCGR 0x19020 +#define GCC_BLSP1_QUP1_SPI_APPS_CMD_RCGR 0x1900C +#define GCC_BLSP1_QUP2_I2C_APPS_CMD_RCGR 0x1B020 +#define GCC_BLSP1_QUP2_SPI_APPS_CMD_RCGR 0x1B00C +#define GCC_BLSP1_QUP3_I2C_APPS_CMD_RCGR 0x1D020 +#define GCC_BLSP1_QUP3_SPI_APPS_CMD_RCGR 0x1D00C +#define GCC_BLSP1_QUP4_I2C_APPS_CMD_RCGR 0x1F020 +#define GCC_BLSP1_QUP4_SPI_APPS_CMD_RCGR 0x1F00C +#define GCC_BLSP1_QUP5_I2C_APPS_CMD_RCGR 0x21020 +#define GCC_BLSP1_QUP5_SPI_APPS_CMD_RCGR 0x2100C +#define GCC_BLSP1_QUP6_I2C_APPS_CMD_RCGR 0x23020 +#define GCC_BLSP1_QUP6_SPI_APPS_CMD_RCGR 0x2300C +#define GCC_BLSP1_UART1_APPS_CMD_RCGR 0x1A00C +#define GCC_BLSP1_UART2_APPS_CMD_RCGR 0x1C00C +#define GCC_BLSP1_UART3_APPS_CMD_RCGR 0x1E00C +#define GCC_BLSP2_QUP1_I2C_APPS_CMD_RCGR 0x26020 +#define GCC_BLSP2_QUP2_I2C_APPS_CMD_RCGR 0x28020 +#define GCC_BLSP2_QUP3_I2C_APPS_CMD_RCGR 0x2A020 +#define GCC_BLSP2_QUP4_I2C_APPS_CMD_RCGR 0x2C020 +#define GCC_BLSP2_QUP5_I2C_APPS_CMD_RCGR 0x2E020 +#define GCC_BLSP2_QUP6_I2C_APPS_CMD_RCGR 0x30020 +#define GCC_BLSP2_QUP1_SPI_APPS_CMD_RCGR 0x2600C +#define GCC_BLSP2_QUP2_SPI_APPS_CMD_RCGR 0x2800C +#define GCC_BLSP2_QUP3_SPI_APPS_CMD_RCGR 0x2A00C +#define GCC_BLSP2_QUP4_SPI_APPS_CMD_RCGR 0x2C00C +#define GCC_BLSP2_QUP5_SPI_APPS_CMD_RCGR 0x2E00C +#define GCC_BLSP2_QUP6_SPI_APPS_CMD_RCGR 0x3000C +#define GCC_BLSP2_UART1_APPS_CMD_RCGR 0x2700C +#define GCC_BLSP2_UART2_APPS_CMD_RCGR 0x2900C +#define GCC_BLSP2_UART3_APPS_CMD_RCGR 0x2B00C +#define GCC_GP1_CMD_RCGR 0x64004 +#define GCC_GP2_CMD_RCGR 0x65004 +#define GCC_GP3_CMD_RCGR 0x66004 +#define GCC_HMSS_RBCPR_CMD_RCGR 0x48044 +#define GCC_PDM2_CMD_RCGR 0x33010 +#define GCC_SDCC2_APPS_CMD_RCGR 0x14010 +#define GCC_SDCC4_APPS_CMD_RCGR 0x16010 +#define GCC_TSIF_REF_CMD_RCGR 0x36010 +#define GCC_UFS_ICE_CORE_CMD_RCGR 0x76010 +#define GCC_UFS_PHY_AUX_CMD_RCGR 0x76044 +#define GCC_UFS_UNIPRO_CORE_CMD_RCGR 0x76028 +#define GCC_USB30_MOCK_UTMI_CMD_RCGR 0x0F028 +#define GCC_USB3_PHY_AUX_CMD_RCGR 0x5000C +#define GCC_QSPI_REF_CMD_RCGR 0x9000C +#define GCC_PCIE_0_PHY_BCR 0x6C01C +#define GCC_HDMI_CLKREF_EN 0x88000 +#define GCC_UFS_CLKREF_EN 0x88004 +#define GCC_USB3_CLKREF_EN 0x88008 +#define GCC_PCIE_CLKREF_EN 0x8800C +#define GCC_RX1_USB2_CLKREF_EN 0x88014 +#define GCC_USB3_PHY_BCR 0x50020 +#define GCC_AGGRE1_NOC_XO_CBCR 0x8202C +#define GCC_AGGRE1_UFS_AXI_CBCR 0x82028 +#define GCC_AGGRE1_USB3_AXI_CBCR 0x82024 +#define GCC_BIMC_MSS_Q6_AXI_CBCR 0x4401C +#define GCC_BLSP1_AHB_CBCR 0x17004 +#define GCC_BLSP1_BCR 0x17000 +#define GCC_BLSP1_QUP1_SPI_APPS_CBCR 0x19004 +#define GCC_BLSP1_QUP1_I2C_APPS_CBCR 0x19008 +#define GCC_BLSP1_QUP2_SPI_APPS_CBCR 0x1B004 +#define GCC_BLSP1_QUP2_I2C_APPS_CBCR 0x1B008 +#define GCC_BLSP1_QUP3_SPI_APPS_CBCR 0x1D004 +#define GCC_BLSP1_QUP3_I2C_APPS_CBCR 0x1D008 +#define GCC_BLSP1_QUP4_SPI_APPS_CBCR 0x1F004 +#define GCC_BLSP1_QUP4_I2C_APPS_CBCR 0x1F008 +#define GCC_BLSP1_QUP5_SPI_APPS_CBCR 0x21004 +#define GCC_BLSP1_QUP5_I2C_APPS_CBCR 0x21008 +#define GCC_BLSP1_QUP6_SPI_APPS_CBCR 0x23004 +#define GCC_BLSP1_QUP6_I2C_APPS_CBCR 0x23008 +#define GCC_BLSP1_UART1_APPS_CBCR 0x1A004 +#define GCC_BLSP1_UART2_APPS_CBCR 0x1C004 +#define GCC_BLSP1_UART3_APPS_CBCR 0x1E004 +#define GCC_BLSP2_AHB_CBCR 0x25004 +#define GCC_BLSP2_BCR 0x25000 +#define GCC_BLSP2_QUP1_SPI_APPS_CBCR 0x26004 +#define GCC_BLSP2_QUP1_I2C_APPS_CBCR 0x26008 +#define GCC_BLSP2_QUP2_I2C_APPS_CBCR 0x28008 +#define GCC_BLSP2_QUP2_SPI_APPS_CBCR 0x28004 +#define GCC_BLSP2_QUP3_SPI_APPS_CBCR 0x2A004 +#define GCC_BLSP2_QUP3_I2C_APPS_CBCR 0x2A008 +#define GCC_BLSP2_QUP4_SPI_APPS_CBCR 0x2C004 +#define GCC_BLSP2_QUP4_I2C_APPS_CBCR 0x2C008 +#define GCC_BLSP2_QUP5_SPI_APPS_CBCR 0x2E004 +#define GCC_BLSP2_QUP5_I2C_APPS_CBCR 0x2E008 +#define GCC_BLSP2_QUP6_SPI_APPS_CBCR 0x30004 +#define GCC_BLSP2_QUP6_I2C_APPS_CBCR 0x30008 +#define GCC_BLSP2_UART1_APPS_CBCR 0x27004 +#define GCC_BLSP2_UART2_APPS_CBCR 0x29004 +#define GCC_BLSP2_UART3_APPS_CBCR 0x2B004 +#define GCC_BOOT_ROM_AHB_CBCR 0x38004 +#define GCC_BOOT_ROM_BCR 0x38000 +#define GCC_CFG_NOC_USB3_AXI_CBCR 0x05018 +#define GCC_BIMC_GFX_CBCR 0x46040 +#define GCC_GP1_CBCR 0x64000 +#define GCC_GP2_CBCR 0x65000 +#define GCC_GP3_CBCR 0x66000 +#define GCC_GPU_BIMC_GFX_CBCR 0x71010 +#define GCC_GPU_CFG_AHB_CBCR 0x71004 +#define GCC_GPU_IREF_EN 0x88010 +#define GCC_HMSS_DVM_BUS_CBCR 0x4808C +#define GCC_HMSS_RBCPR_CBCR 0x48008 +#define GCC_MMSS_SYS_NOC_AXI_CBCR 0x09000 +#define GCC_MMSS_NOC_CFG_AHB_CBCR 0x09004 +#define GCC_PCIE_0_SLV_AXI_CBCR 0x6B008 +#define GCC_PCIE_0_MSTR_AXI_CBCR 0x6B00C +#define GCC_PCIE_0_CFG_AHB_CBCR 0x6B010 +#define GCC_PCIE_0_AUX_CBCR 0x6B014 +#define GCC_PCIE_0_PIPE_CBCR 0x6B018 +#define GCC_PCIE_PHY_AUX_CBCR 0x6F004 +#define GCC_PCIE_PHY_BCR 0x6F000 +#define GCC_PCIE_PHY_COM_BCR 0x6F014 +#define GCC_PCIE_PHY_NOCSR_COM_PHY_BCR 0x6F00C +#define GCC_QUSB2PHY_PRIM_BCR 0x12000 +#define GCC_QUSB2PHY_SEC_BCR 0x12004 +#define GCC_PDM2_CBCR 0x3300C +#define GCC_PDM_AHB_CBCR 0x33004 +#define GCC_PRNG_AHB_CBCR 0x34004 +#define GCC_PRNG_BCR 0x34000 +#define GCC_SDCC2_APPS_CBCR 0x14004 +#define GCC_SDCC2_AHB_CBCR 0x14008 +#define GCC_SDCC4_APPS_CBCR 0x16004 +#define GCC_SDCC4_AHB_CBCR 0x16008 +#define GCC_TSIF_AHB_CBCR 0x36004 +#define GCC_TSIF_REF_CBCR 0x36008 +#define GCC_UFS_AXI_CBCR 0x75008 +#define GCC_UFS_BCR 0x75000 +#define GCC_UFS_AHB_CBCR 0x7500C +#define GCC_UFS_TX_SYMBOL_0_CBCR 0x75010 +#define GCC_UFS_RX_SYMBOL_0_CBCR 0x75014 +#define GCC_UFS_RX_SYMBOL_1_CBCR 0x7605C +#define GCC_UFS_UNIPRO_CORE_CBCR 0x76008 +#define GCC_UFS_ICE_CORE_CBCR 0x7600C +#define GCC_UFS_PHY_AUX_CBCR 0x76040 +#define GCC_USB30_MASTER_CBCR 0x0F008 +#define GCC_USB30_SLEEP_CBCR 0x0F00C +#define GCC_USB30_MOCK_UTMI_CBCR 0x0F010 +#define GCC_USB_30_BCR 0x0F000 +#define GCC_USB3_PHY_AUX_CBCR 0x50000 +#define GCC_USB3_PHY_PIPE_CBCR 0x50004 +#define GCC_USB3PHY_PHY_BCR 0x50024 +#define GCC_APCS_CLOCK_SLEEP_ENA_VOTE 0x52008 +#define GCC_MSS_CFG_AHB_CBCR 0x8A000 +#define GCC_MSS_Q6_BIMC_AXI_CBCR 0x8A040 +#define GCC_MSS_MNOC_BIMC_AXI_CBCR 0x8A004 +#define GCC_MSS_SNOC_AXI_CBCR 0x8A03C +#define GCC_HMSS_GPLL0_CMD_RCGR 0x4805C +#define GCC_MSS_CFG_AHB_CBCR 0x8A000 +#define GCC_MSS_Q6_BIMC_AXI_CBCR 0x8A040 +#define GCC_MSS_MNOC_BIMC_AXI_CBCR 0x8A004 +#define GCC_MSS_SNOC_AXI_CBCR 0x8A03C +#define GCC_DCC_AHB_CBCR 0x84004 +#define GCC_HLOS1_VOTE_LPASS_CORE_SMMU_CBCR 0x7D010 +#define GCC_HLOS1_VOTE_LPASS_ADSP_SMMU_CBCR 0x7D014 +#define GCC_QSPI_AHB_CBCR 0x90004 +#define GCC_QSPI_REF_CBCR 0x90008 +#define GCC_MMSS_MISC 0x0902C +#define GCC_GPU_MISC 0x71028 + +#define GPUCC_GPU_PLL0_PLL_MODE 0x00000 +#define GPUCC_GPU_PLL0_USER_CTL_MODE 0x0000C +#define GPUCC_GFX3D_CMD_RCGR 0x01070 +#define GPUCC_RBBMTIMER_CMD_RCGR 0x010B0 +#define GPUCC_GFX3D_ISENSE_CMD_RCGR 0x01100 +#define GPUCC_RBCPR_CMD_RCGR 0x01030 +#define GPUCC_GFX3D_CBCR 0x01098 +#define GPUCC_RBBMTIMER_CBCR 0x010D0 +#define GPUCC_GFX3D_ISENSE_CBCR 0x01124 +#define GPUCC_CXO_CBCR 0x01020 +#define GPUCC_RBCPR_CBCR 0x01054 +#define GPU_GX_BCR 0x01090 +#define GPUCC_GX_DOMAIN_MISC 0x00130 +#define GPUCC_GPU_DD_WRAP_CTRL 0x00430 +#define GPUCC_DEBUG_CLK_CTL 0x00120 + +#define MMSS_PLL_VOTE_APCS 0x001E0 +#define MMSS_MMPLL0_PLL_MODE 0x0C000 +#define MMSS_MMPLL1_PLL_MODE 0x0C050 +#define MMSS_MMPLL3_PLL_MODE 0x00000 +#define MMSS_MMPLL4_PLL_MODE 0x00050 +#define MMSS_MMPLL5_PLL_MODE 0x000A0 +#define MMSS_MMPLL6_PLL_MODE 0x000F0 +#define MMSS_MMPLL7_PLL_MODE 0x00140 +#define MMSS_MMPLL10_PLL_MODE 0x00190 +#define MMSS_AHB_CMD_RCGR 0x05000 +#define MMSS_CSI0_CMD_RCGR 0x03090 +#define MMSS_VFE0_CMD_RCGR 0x03600 +#define MMSS_VFE1_CMD_RCGR 0x03620 +#define MMSS_MDP_CMD_RCGR 0x02040 +#define MMSS_MAXI_CMD_RCGR 0x0F020 +#define MMSS_CPP_CMD_RCGR 0x03640 +#define MMSS_JPEG0_CMD_RCGR 0x03500 +#define MMSS_ROT_CMD_RCGR 0x021A0 +#define MMSS_VIDEO_CORE_CMD_RCGR 0x01000 +#define MMSS_CSI1_CMD_RCGR 0x03100 +#define MMSS_CSI2_CMD_RCGR 0x03160 +#define MMSS_CSI3_CMD_RCGR 0x031C0 +#define MMSS_FD_CORE_CMD_RCGR 0x03B00 +#define MMSS_BYTE0_CMD_RCGR 0x02120 +#define MMSS_BYTE1_CMD_RCGR 0x02140 +#define MMSS_PCLK0_CMD_RCGR 0x02000 +#define MMSS_PCLK1_CMD_RCGR 0x02020 +#define MMSS_VIDEO_SUBCORE0_CMD_RCGR 0x01060 +#define MMSS_VIDEO_SUBCORE1_CMD_RCGR 0x01080 +#define MMSS_CSIPHY_CMD_RCGR 0x03800 +#define MMSS_CCI_CMD_RCGR 0x03300 +#define MMSS_CAMSS_GP0_CMD_RCGR 0x03420 +#define MMSS_CAMSS_GP1_CMD_RCGR 0x03450 +#define MMSS_MCLK0_CMD_RCGR 0x03360 +#define MMSS_MCLK1_CMD_RCGR 0x03390 +#define MMSS_MCLK2_CMD_RCGR 0x033C0 +#define MMSS_MCLK3_CMD_RCGR 0x033F0 +#define MMSS_CAMSS_CSI2PHYTIMER_CBCR 0x03084 +#define MMSS_CSI0PHYTIMER_CMD_RCGR 0x03000 +#define MMSS_CSI1PHYTIMER_CMD_RCGR 0x03030 +#define MMSS_CSI2PHYTIMER_CMD_RCGR 0x03060 +#define MMSS_DP_GTC_CMD_RCGR 0x02280 +#define MMSS_ESC0_CMD_RCGR 0x02160 +#define MMSS_ESC1_CMD_RCGR 0x02180 +#define MMSS_EXTPCLK_CMD_RCGR 0x02060 +#define MMSS_HDMI_CMD_RCGR 0x02100 +#define MMSS_VSYNC_CMD_RCGR 0x02080 +#define MMSS_BIMC_SMMU_AHB_CBCR 0x0E004 +#define MMSS_BIMC_SMMU_AXI_CBCR 0x0E008 +#define MMSS_SNOC_DVM_AXI_CBCR 0x0E040 +#define MMSS_CAMSS_AHB_CBCR 0x0348C +#define MMSS_CAMSS_CCI_AHB_CBCR 0x03348 +#define MMSS_CAMSS_CCI_CBCR 0x03344 +#define MMSS_CAMSS_CPP_AHB_CBCR 0x036B4 +#define MMSS_CAMSS_CPP_CBCR 0x036B0 +#define MMSS_CAMSS_CPP_AXI_CBCR 0x036C4 +#define MMSS_CAMSS_CPP_VBIF_AHB_CBCR 0x036C8 +#define MMSS_CAMSS_CPHY_CSID0_CBCR 0x03730 +#define MMSS_CAMSS_CSI0_AHB_CBCR 0x030BC +#define MMSS_CAMSS_CSI0_CBCR 0x030B4 +#define MMSS_CAMSS_CSI0PIX_CBCR 0x030E4 +#define MMSS_CAMSS_CSI0RDI_CBCR 0x030D4 +#define MMSS_CAMSS_CPHY_CSID1_CBCR 0x03734 +#define MMSS_CAMSS_CSI1_AHB_CBCR 0x03128 +#define MMSS_CAMSS_CSI1_CBCR 0x03124 +#define MMSS_CAMSS_CSI1PIX_CBCR 0x03154 +#define MMSS_CAMSS_CSI1RDI_CBCR 0x03144 +#define MMSS_CAMSS_CPHY_CSID2_CBCR 0x03738 +#define MMSS_CAMSS_CSI2_AHB_CBCR 0x03188 +#define MMSS_CAMSS_CSI2_CBCR 0x03184 +#define MMSS_CAMSS_CSI2PIX_CBCR 0x031B4 +#define MMSS_CAMSS_CSI2RDI_CBCR 0x031A4 +#define MMSS_CAMSS_CPHY_CSID3_CBCR 0x0373C +#define MMSS_CAMSS_CSI3_AHB_CBCR 0x031E8 +#define MMSS_CAMSS_CSI3_CBCR 0x031E4 +#define MMSS_CAMSS_CSI3PIX_CBCR 0x03214 +#define MMSS_CAMSS_CSI3RDI_CBCR 0x03204 +#define MMSS_CAMSS_CSI_VFE0_CBCR 0x03704 +#define MMSS_CAMSS_CSI_VFE1_CBCR 0x03714 +#define MMSS_CAMSS_CSIPHY0_CBCR 0x03740 +#define MMSS_CAMSS_CSIPHY1_CBCR 0x03744 +#define MMSS_CAMSS_CSIPHY2_CBCR 0x03748 +#define MMSS_FD_AHB_CBCR 0x03B74 +#define MMSS_FD_CORE_CBCR 0x03B68 +#define MMSS_FD_CORE_UAR_CBCR 0x03B6C +#define MMSS_CAMSS_GP0_CBCR 0x03444 +#define MMSS_CAMSS_GP1_CBCR 0x03474 +#define MMSS_CAMSS_ISPIF_AHB_CBCR 0x03224 +#define MMSS_CAMSS_JPEG0_CBCR 0x035A8 +#define MMSS_CAMSS_JPEG_AHB_CBCR 0x035B4 +#define MMSS_CAMSS_JPEG_AXI_CBCR 0x035B8 +#define MMSS_CAMSS_MCLK0_CBCR 0x03384 +#define MMSS_CAMSS_MCLK1_CBCR 0x033B4 +#define MMSS_CAMSS_MCLK2_CBCR 0x033E4 +#define MMSS_CAMSS_MCLK3_CBCR 0x03414 +#define MMSS_CAMSS_MICRO_AHB_CBCR 0x03494 +#define MMSS_CAMSS_CSI0PHYTIMER_CBCR 0x03024 +#define MMSS_CAMSS_CSI1PHYTIMER_CBCR 0x03054 +#define MMSS_CSI2PHYTIMER_CMD_RCGR 0x03060 +#define MMSS_CAMSS_TOP_AHB_CBCR 0x03484 +#define MMSS_CAMSS_VFE0_AHB_CBCR 0x03668 +#define MMSS_CAMSS_VFE0_CBCR 0x036A8 +#define MMSS_CAMSS_VFE0_STREAM_CBCR 0x03720 +#define MMSS_CAMSS_VFE1_AHB_CBCR 0x03678 +#define MMSS_CAMSS_VFE1_CBCR 0x036AC +#define MMSS_CAMSS_VFE1_STREAM_CBCR 0x03724 +#define MMSS_CAMSS_VFE_VBIF_AHB_CBCR 0x036B8 +#define MMSS_CAMSS_VFE_VBIF_AXI_CBCR 0x036BC +#define MMSS_MDSS_AHB_CBCR 0x02308 +#define MMSS_MDSS_AXI_CBCR 0x02310 +#define MMSS_MDSS_BYTE0_CBCR 0x0233C +#define MMSS_MDSS_BYTE0_INTF_CBCR 0x02374 +#define MMSS_MDSS_BYTE0_INTF_DIV 0x0237C +#define MMSS_MDSS_BYTE1_CBCR 0x02340 +#define MMSS_MDSS_BYTE1_INTF_CBCR 0x02378 +#define MMSS_MDSS_BYTE1_INTF_DIV 0x02380 +#define MMSS_MDSS_DP_AUX_CBCR 0x02364 +#define MMSS_MDSS_DP_CRYPTO_CBCR 0x0235C +#define MMSS_MDSS_DP_GTC_CBCR 0x02368 +#define MMSS_MDSS_DP_LINK_CBCR 0x02354 +#define MMSS_MDSS_DP_LINK_INTF_CBCR 0x02358 +#define MMSS_MDSS_DP_PIXEL_CBCR 0x02360 +#define MMSS_MDSS_ESC0_CBCR 0x02344 +#define MMSS_MDSS_ESC1_CBCR 0x02348 +#define MMSS_MDSS_EXTPCLK_CBCR 0x02324 +#define MMSS_MDSS_HDMI_CBCR 0x02338 +#define MMSS_MDSS_HDMI_DP_AHB_CBCR 0x0230C +#define MMSS_MDSS_MDP_CBCR 0x0231C +#define MMSS_MDSS_MDP_LUT_CBCR 0x02320 +#define MMSS_MDSS_PCLK0_CBCR 0x02314 +#define MMSS_MDSS_PCLK1_CBCR 0x02318 +#define MMSS_MDSS_ROT_CBCR 0x02350 +#define MMSS_MDSS_VSYNC_CBCR 0x02328 +#define MMSS_MISC_AHB_CBCR 0x00328 +#define MMSS_MISC_CXO_CBCR 0x00324 +#define MMSS_MNOC_AHB_CBCR 0x05024 +#define MMSS_MNOC_MAXI_CBCR 0x0F004 +#define MMSS_VIDEO_SUBCORE0_CBCR 0x01048 +#define MMSS_VIDEO_SUBCORE1_CBCR 0x0104C +#define MMSS_VIDEO_AHB_CBCR 0x01030 +#define MMSS_VIDEO_AXI_CBCR 0x01034 +#define MMSS_VIDEO_CORE_CBCR 0x01028 +#define MMSS_VIDEO_MAXI_CBCR 0x01038 +#define MMSS_VMEM_AHB_CBCR 0x0F068 +#define MMSS_VMEM_MAXI_CBCR 0x0F064 +#define MMSS_DP_AUX_CMD_RCGR 0x02260 +#define MMSS_DP_CRYPTO_CMD_RCGR 0x02220 +#define MMSS_DP_LINK_CMD_RCGR 0x02200 +#define MMSS_DP_PIXEL_CMD_RCGR 0x02240 +#define MMSS_DEBUG_CLK_CTL 0x00900 diff -Nruw linux-4.4.115-fbx/arch/metag/boot/dts/include/dt-bindings/msm./msm-bus-ids.h linux-4.4.115-fbx/arch/metag/boot/dts/include/dt-bindings/msm/msm-bus-ids.h --- linux-4.4.115-fbx/arch/metag/boot/dts/include/dt-bindings/msm./msm-bus-ids.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-4.4.115-fbx/arch/metag/boot/dts/include/dt-bindings/msm/msm-bus-ids.h 2019-01-22 16:16:28.179288750 +0100 @@ -0,0 +1,887 @@ +/* Copyright (c) 2014-2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __MSM_BUS_IDS_H +#define __MSM_BUS_IDS_H + +/* Aggregation types */ +#define AGG_SCHEME_NONE 0 +#define AGG_SCHEME_LEG 1 +#define AGG_SCHEME_1 2 + +/* Topology related enums */ +#define MSM_BUS_FAB_DEFAULT 0 +#define MSM_BUS_FAB_APPSS 0 +#define MSM_BUS_FAB_SYSTEM 1024 +#define MSM_BUS_FAB_MMSS 2048 +#define MSM_BUS_FAB_SYSTEM_FPB 3072 +#define MSM_BUS_FAB_CPSS_FPB 4096 + +#define MSM_BUS_FAB_BIMC 0 +#define MSM_BUS_FAB_SYS_NOC 1024 +#define MSM_BUS_FAB_MMSS_NOC 2048 +#define MSM_BUS_FAB_OCMEM_NOC 3072 +#define MSM_BUS_FAB_PERIPH_NOC 4096 +#define MSM_BUS_FAB_CONFIG_NOC 5120 +#define MSM_BUS_FAB_OCMEM_VNOC 6144 +#define MSM_BUS_FAB_MMSS_AHB 2049 +#define MSM_BUS_FAB_A0_NOC 6145 +#define MSM_BUS_FAB_A1_NOC 6146 +#define MSM_BUS_FAB_A2_NOC 6147 +#define MSM_BUS_FAB_GNOC 6148 +#define MSM_BUS_FAB_CR_VIRT 6149 + +#define MSM_BUS_MASTER_FIRST 1 +#define MSM_BUS_MASTER_AMPSS_M0 1 +#define MSM_BUS_MASTER_AMPSS_M1 2 +#define MSM_BUS_APPSS_MASTER_FAB_MMSS 3 +#define MSM_BUS_APPSS_MASTER_FAB_SYSTEM 4 +#define MSM_BUS_SYSTEM_MASTER_FAB_APPSS 5 +#define MSM_BUS_MASTER_SPS 6 +#define MSM_BUS_MASTER_ADM_PORT0 7 +#define MSM_BUS_MASTER_ADM_PORT1 8 +#define MSM_BUS_SYSTEM_MASTER_ADM1_PORT0 9 +#define MSM_BUS_MASTER_ADM1_PORT1 10 +#define MSM_BUS_MASTER_LPASS_PROC 11 +#define MSM_BUS_MASTER_MSS_PROCI 12 +#define MSM_BUS_MASTER_MSS_PROCD 13 +#define MSM_BUS_MASTER_MSS_MDM_PORT0 14 +#define MSM_BUS_MASTER_LPASS 15 +#define MSM_BUS_SYSTEM_MASTER_CPSS_FPB 16 +#define MSM_BUS_SYSTEM_MASTER_SYSTEM_FPB 17 +#define MSM_BUS_SYSTEM_MASTER_MMSS_FPB 18 +#define MSM_BUS_MASTER_ADM1_CI 19 +#define MSM_BUS_MASTER_ADM0_CI 20 +#define MSM_BUS_MASTER_MSS_MDM_PORT1 21 +#define MSM_BUS_MASTER_MDP_PORT0 22 +#define MSM_BUS_MASTER_MDP_PORT1 23 +#define MSM_BUS_MMSS_MASTER_ADM1_PORT0 24 +#define MSM_BUS_MASTER_ROTATOR 25 +#define MSM_BUS_MASTER_GRAPHICS_3D 26 +#define MSM_BUS_MASTER_JPEG_DEC 27 +#define MSM_BUS_MASTER_GRAPHICS_2D_CORE0 28 +#define MSM_BUS_MASTER_VFE 29 +#define MSM_BUS_MASTER_VFE0 MSM_BUS_MASTER_VFE +#define MSM_BUS_MASTER_VPE 30 +#define MSM_BUS_MASTER_JPEG_ENC 31 +#define MSM_BUS_MASTER_GRAPHICS_2D_CORE1 32 +#define MSM_BUS_MMSS_MASTER_APPS_FAB 33 +#define MSM_BUS_MASTER_HD_CODEC_PORT0 34 +#define MSM_BUS_MASTER_HD_CODEC_PORT1 35 +#define MSM_BUS_MASTER_SPDM 36 +#define MSM_BUS_MASTER_RPM 37 +#define MSM_BUS_MASTER_MSS 38 +#define MSM_BUS_MASTER_RIVA 39 +#define MSM_BUS_MASTER_SNOC_VMEM 40 +#define MSM_BUS_MASTER_MSS_SW_PROC 41 +#define MSM_BUS_MASTER_MSS_FW_PROC 42 +#define MSM_BUS_MASTER_HMSS 43 +#define MSM_BUS_MASTER_GSS_NAV 44 +#define MSM_BUS_MASTER_PCIE 45 +#define MSM_BUS_MASTER_SATA 46 +#define MSM_BUS_MASTER_CRYPTO 47 +#define MSM_BUS_MASTER_VIDEO_CAP 48 +#define MSM_BUS_MASTER_GRAPHICS_3D_PORT1 49 +#define MSM_BUS_MASTER_VIDEO_ENC 50 +#define MSM_BUS_MASTER_VIDEO_DEC 51 +#define MSM_BUS_MASTER_LPASS_AHB 52 +#define MSM_BUS_MASTER_QDSS_BAM 53 +#define MSM_BUS_MASTER_SNOC_CFG 54 +#define MSM_BUS_MASTER_CRYPTO_CORE0 55 +#define MSM_BUS_MASTER_CRYPTO_CORE1 56 +#define MSM_BUS_MASTER_MSS_NAV 57 +#define MSM_BUS_MASTER_OCMEM_DMA 58 +#define MSM_BUS_MASTER_WCSS 59 +#define MSM_BUS_MASTER_QDSS_ETR 60 +#define MSM_BUS_MASTER_USB3 61 +#define MSM_BUS_MASTER_JPEG 62 +#define MSM_BUS_MASTER_VIDEO_P0 63 +#define MSM_BUS_MASTER_VIDEO_P1 64 +#define MSM_BUS_MASTER_MSS_PROC 65 +#define MSM_BUS_MASTER_JPEG_OCMEM 66 +#define MSM_BUS_MASTER_MDP_OCMEM 67 +#define MSM_BUS_MASTER_VIDEO_P0_OCMEM 68 +#define MSM_BUS_MASTER_VIDEO_P1_OCMEM 69 +#define MSM_BUS_MASTER_VFE_OCMEM 70 +#define MSM_BUS_MASTER_CNOC_ONOC_CFG 71 +#define MSM_BUS_MASTER_RPM_INST 72 +#define MSM_BUS_MASTER_RPM_DATA 73 +#define MSM_BUS_MASTER_RPM_SYS 74 +#define MSM_BUS_MASTER_DEHR 75 +#define MSM_BUS_MASTER_QDSS_DAP 76 +#define MSM_BUS_MASTER_TIC 77 +#define MSM_BUS_MASTER_SDCC_1 78 +#define MSM_BUS_MASTER_SDCC_3 79 +#define MSM_BUS_MASTER_SDCC_4 80 +#define MSM_BUS_MASTER_SDCC_2 81 +#define MSM_BUS_MASTER_TSIF 82 +#define MSM_BUS_MASTER_BAM_DMA 83 +#define MSM_BUS_MASTER_BLSP_2 84 +#define MSM_BUS_MASTER_USB_HSIC 85 +#define MSM_BUS_MASTER_BLSP_1 86 +#define MSM_BUS_MASTER_USB_HS 87 +#define MSM_BUS_MASTER_PNOC_CFG 88 +#define MSM_BUS_MASTER_V_OCMEM_GFX3D 89 +#define MSM_BUS_MASTER_IPA 90 +#define MSM_BUS_MASTER_QPIC 91 +#define MSM_BUS_MASTER_MDPE 92 +#define MSM_BUS_MASTER_USB_HS2 93 +#define MSM_BUS_MASTER_VPU 94 +#define MSM_BUS_MASTER_UFS 95 +#define MSM_BUS_MASTER_BCAST 96 +#define MSM_BUS_MASTER_CRYPTO_CORE2 97 +#define MSM_BUS_MASTER_EMAC 98 +#define MSM_BUS_MASTER_VPU_1 99 +#define MSM_BUS_MASTER_PCIE_1 100 +#define MSM_BUS_MASTER_USB3_1 101 +#define MSM_BUS_MASTER_CNOC_MNOC_MMSS_CFG 102 +#define MSM_BUS_MASTER_CNOC_MNOC_CFG 103 +#define MSM_BUS_MASTER_TCU_0 104 +#define MSM_BUS_MASTER_TCU_1 105 +#define MSM_BUS_MASTER_CPP 106 +#define MSM_BUS_MASTER_AUDIO 107 +#define MSM_BUS_MASTER_PCIE_2 108 +#define MSM_BUS_MASTER_VFE1 109 +#define MSM_BUS_MASTER_XM_USB_HS1 110 +#define MSM_BUS_MASTER_PCNOC_BIMC_1 111 +#define MSM_BUS_MASTER_BIMC_PCNOC 112 +#define MSM_BUS_MASTER_XI_USB_HSIC 113 +#define MSM_BUS_MASTER_SGMII 114 +#define MSM_BUS_SPMI_FETCHER 115 +#define MSM_BUS_MASTER_GNOC_BIMC 116 +#define MSM_BUS_MASTER_CRVIRT_A2NOC 117 +#define MSM_BUS_MASTER_CNOC_A2NOC 118 +#define MSM_BUS_MASTER_WLAN 119 +#define MSM_BUS_MASTER_MSS_CE 120 +#define MSM_BUS_MASTER_CDSP_PROC 121 +#define MSM_BUS_MASTER_GNOC_SNOC 122 +#define MSM_BUS_MASTER_PIMEM 123 +#define MSM_BUS_MASTER_MASTER_LAST 124 + +#define MSM_BUS_SYSTEM_FPB_MASTER_SYSTEM MSM_BUS_SYSTEM_MASTER_SYSTEM_FPB +#define MSM_BUS_CPSS_FPB_MASTER_SYSTEM MSM_BUS_SYSTEM_MASTER_CPSS_FPB + +#define MSM_BUS_SNOC_MM_INT_0 10000 +#define MSM_BUS_SNOC_MM_INT_1 10001 +#define MSM_BUS_SNOC_MM_INT_2 10002 +#define MSM_BUS_SNOC_MM_INT_BIMC 10003 +#define MSM_BUS_SNOC_INT_0 10004 +#define MSM_BUS_SNOC_INT_1 10005 +#define MSM_BUS_SNOC_INT_BIMC 10006 +#define MSM_BUS_SNOC_BIMC_0_MAS 10007 +#define MSM_BUS_SNOC_BIMC_1_MAS 10008 +#define MSM_BUS_SNOC_QDSS_INT 10009 +#define MSM_BUS_PNOC_SNOC_MAS 10010 +#define MSM_BUS_PNOC_SNOC_SLV 10011 +#define MSM_BUS_PNOC_INT_0 10012 +#define MSM_BUS_PNOC_INT_1 10013 +#define MSM_BUS_PNOC_M_0 10014 +#define MSM_BUS_PNOC_M_1 10015 +#define MSM_BUS_BIMC_SNOC_MAS 10016 +#define MSM_BUS_BIMC_SNOC_SLV 10017 +#define MSM_BUS_PNOC_SLV_0 10018 +#define MSM_BUS_PNOC_SLV_1 10019 +#define MSM_BUS_PNOC_SLV_2 10020 +#define MSM_BUS_PNOC_SLV_3 10021 +#define MSM_BUS_PNOC_SLV_4 10022 +#define MSM_BUS_PNOC_SLV_8 10023 +#define MSM_BUS_PNOC_SLV_9 10024 +#define MSM_BUS_SNOC_BIMC_0_SLV 10025 +#define MSM_BUS_SNOC_BIMC_1_SLV 10026 +#define MSM_BUS_MNOC_BIMC_MAS 10027 +#define MSM_BUS_MNOC_BIMC_SLV 10028 +#define MSM_BUS_BIMC_MNOC_MAS 10029 +#define MSM_BUS_BIMC_MNOC_SLV 10030 +#define MSM_BUS_SNOC_BIMC_MAS 10031 +#define MSM_BUS_SNOC_BIMC_SLV 10032 +#define MSM_BUS_CNOC_SNOC_MAS 10033 +#define MSM_BUS_CNOC_SNOC_SLV 10034 +#define MSM_BUS_SNOC_CNOC_MAS 10035 +#define MSM_BUS_SNOC_CNOC_SLV 10036 +#define MSM_BUS_OVNOC_SNOC_MAS 10037 +#define MSM_BUS_OVNOC_SNOC_SLV 10038 +#define MSM_BUS_SNOC_OVNOC_MAS 10039 +#define MSM_BUS_SNOC_OVNOC_SLV 10040 +#define MSM_BUS_SNOC_PNOC_MAS 10041 +#define MSM_BUS_SNOC_PNOC_SLV 10042 +#define MSM_BUS_BIMC_INT_APPS_EBI 10043 +#define MSM_BUS_BIMC_INT_APPS_SNOC 10044 +#define MSM_BUS_SNOC_BIMC_2_MAS 10045 +#define MSM_BUS_SNOC_BIMC_2_SLV 10046 +#define MSM_BUS_PNOC_SLV_5 10047 +#define MSM_BUS_PNOC_SLV_7 10048 +#define MSM_BUS_PNOC_INT_2 10049 +#define MSM_BUS_PNOC_INT_3 10050 +#define MSM_BUS_PNOC_INT_4 10051 +#define MSM_BUS_PNOC_INT_5 10052 +#define MSM_BUS_PNOC_INT_6 10053 +#define MSM_BUS_PNOC_INT_7 10054 +#define MSM_BUS_BIMC_SNOC_1_MAS 10055 +#define MSM_BUS_BIMC_SNOC_1_SLV 10056 +#define MSM_BUS_PNOC_A1NOC_MAS 10057 +#define MSM_BUS_PNOC_A1NOC_SLV 10058 +#define MSM_BUS_CNOC_A1NOC_MAS 10059 +#define MSM_BUS_A0NOC_SNOC_MAS 10060 +#define MSM_BUS_A0NOC_SNOC_SLV 10061 +#define MSM_BUS_A1NOC_SNOC_SLV 10062 +#define MSM_BUS_A1NOC_SNOC_MAS 10063 +#define MSM_BUS_A2NOC_SNOC_MAS 10064 +#define MSM_BUS_A2NOC_SNOC_SLV 10065 +#define MSM_BUS_SNOC_INT_2 10066 +#define MSM_BUS_A0NOC_QDSS_INT 10067 +#define MSM_BUS_INT_LAST 10068 + +#define MSM_BUS_INT_TEST_ID 20000 +#define MSM_BUS_INT_TEST_LAST 20050 + +#define MSM_BUS_SLAVE_FIRST 512 +#define MSM_BUS_SLAVE_EBI_CH0 512 +#define MSM_BUS_SLAVE_EBI_CH1 513 +#define MSM_BUS_SLAVE_AMPSS_L2 514 +#define MSM_BUS_APPSS_SLAVE_FAB_MMSS 515 +#define MSM_BUS_APPSS_SLAVE_FAB_SYSTEM 516 +#define MSM_BUS_SYSTEM_SLAVE_FAB_APPS 517 +#define MSM_BUS_SLAVE_SPS 518 +#define MSM_BUS_SLAVE_SYSTEM_IMEM 519 +#define MSM_BUS_SLAVE_AMPSS 520 +#define MSM_BUS_SLAVE_MSS 521 +#define MSM_BUS_SLAVE_LPASS 522 +#define MSM_BUS_SYSTEM_SLAVE_CPSS_FPB 523 +#define MSM_BUS_SYSTEM_SLAVE_SYSTEM_FPB 524 +#define MSM_BUS_SYSTEM_SLAVE_MMSS_FPB 525 +#define MSM_BUS_SLAVE_CORESIGHT 526 +#define MSM_BUS_SLAVE_RIVA 527 +#define MSM_BUS_SLAVE_SMI 528 +#define MSM_BUS_MMSS_SLAVE_FAB_APPS 529 +#define MSM_BUS_MMSS_SLAVE_FAB_APPS_1 530 +#define MSM_BUS_SLAVE_MM_IMEM 531 +#define MSM_BUS_SLAVE_CRYPTO 532 +#define MSM_BUS_SLAVE_SPDM 533 +#define MSM_BUS_SLAVE_RPM 534 +#define MSM_BUS_SLAVE_RPM_MSG_RAM 535 +#define MSM_BUS_SLAVE_MPM 536 +#define MSM_BUS_SLAVE_PMIC1_SSBI1_A 537 +#define MSM_BUS_SLAVE_PMIC1_SSBI1_B 538 +#define MSM_BUS_SLAVE_PMIC1_SSBI1_C 539 +#define MSM_BUS_SLAVE_PMIC2_SSBI2_A 540 +#define MSM_BUS_SLAVE_PMIC2_SSBI2_B 541 +#define MSM_BUS_SLAVE_GSBI1_UART 542 +#define MSM_BUS_SLAVE_GSBI2_UART 543 +#define MSM_BUS_SLAVE_GSBI3_UART 544 +#define MSM_BUS_SLAVE_GSBI4_UART 545 +#define MSM_BUS_SLAVE_GSBI5_UART 546 +#define MSM_BUS_SLAVE_GSBI6_UART 547 +#define MSM_BUS_SLAVE_GSBI7_UART 548 +#define MSM_BUS_SLAVE_GSBI8_UART 549 +#define MSM_BUS_SLAVE_GSBI9_UART 550 +#define MSM_BUS_SLAVE_GSBI10_UART 551 +#define MSM_BUS_SLAVE_GSBI11_UART 552 +#define MSM_BUS_SLAVE_GSBI12_UART 553 +#define MSM_BUS_SLAVE_GSBI1_QUP 554 +#define MSM_BUS_SLAVE_GSBI2_QUP 555 +#define MSM_BUS_SLAVE_GSBI3_QUP 556 +#define MSM_BUS_SLAVE_GSBI4_QUP 557 +#define MSM_BUS_SLAVE_GSBI5_QUP 558 +#define MSM_BUS_SLAVE_GSBI6_QUP 559 +#define MSM_BUS_SLAVE_GSBI7_QUP 560 +#define MSM_BUS_SLAVE_GSBI8_QUP 561 +#define MSM_BUS_SLAVE_GSBI9_QUP 562 +#define MSM_BUS_SLAVE_GSBI10_QUP 563 +#define MSM_BUS_SLAVE_GSBI11_QUP 564 +#define MSM_BUS_SLAVE_GSBI12_QUP 565 +#define MSM_BUS_SLAVE_EBI2_NAND 566 +#define MSM_BUS_SLAVE_EBI2_CS0 567 +#define MSM_BUS_SLAVE_EBI2_CS1 568 +#define MSM_BUS_SLAVE_EBI2_CS2 569 +#define MSM_BUS_SLAVE_EBI2_CS3 570 +#define MSM_BUS_SLAVE_EBI2_CS4 571 +#define MSM_BUS_SLAVE_EBI2_CS5 572 +#define MSM_BUS_SLAVE_USB_FS1 573 +#define MSM_BUS_SLAVE_USB_FS2 574 +#define MSM_BUS_SLAVE_TSIF 575 +#define MSM_BUS_SLAVE_MSM_TSSC 576 +#define MSM_BUS_SLAVE_MSM_PDM 577 +#define MSM_BUS_SLAVE_MSM_DIMEM 578 +#define MSM_BUS_SLAVE_MSM_TCSR 579 +#define MSM_BUS_SLAVE_MSM_PRNG 580 +#define MSM_BUS_SLAVE_GSS 581 +#define MSM_BUS_SLAVE_SATA 582 +#define MSM_BUS_SLAVE_USB3 583 +#define MSM_BUS_SLAVE_WCSS 584 +#define MSM_BUS_SLAVE_OCIMEM 585 +#define MSM_BUS_SLAVE_SNOC_OCMEM 586 +#define MSM_BUS_SLAVE_SERVICE_SNOC 587 +#define MSM_BUS_SLAVE_QDSS_STM 588 +#define MSM_BUS_SLAVE_CAMERA_CFG 589 +#define MSM_BUS_SLAVE_DISPLAY_CFG 590 +#define MSM_BUS_SLAVE_OCMEM_CFG 591 +#define MSM_BUS_SLAVE_CPR_CFG 592 +#define MSM_BUS_SLAVE_CPR_XPU_CFG 593 +#define MSM_BUS_SLAVE_MISC_CFG 594 +#define MSM_BUS_SLAVE_MISC_XPU_CFG 595 +#define MSM_BUS_SLAVE_VENUS_CFG 596 +#define MSM_BUS_SLAVE_MISC_VENUS_CFG 597 +#define MSM_BUS_SLAVE_GRAPHICS_3D_CFG 598 +#define MSM_BUS_SLAVE_MMSS_CLK_CFG 599 +#define MSM_BUS_SLAVE_MMSS_CLK_XPU_CFG 600 +#define MSM_BUS_SLAVE_MNOC_MPU_CFG 601 +#define MSM_BUS_SLAVE_ONOC_MPU_CFG 602 +#define MSM_BUS_SLAVE_SERVICE_MNOC 603 +#define MSM_BUS_SLAVE_OCMEM 604 +#define MSM_BUS_SLAVE_SERVICE_ONOC 605 +#define MSM_BUS_SLAVE_SDCC_1 606 +#define MSM_BUS_SLAVE_SDCC_3 607 +#define MSM_BUS_SLAVE_SDCC_2 608 +#define MSM_BUS_SLAVE_SDCC_4 609 +#define MSM_BUS_SLAVE_BAM_DMA 610 +#define MSM_BUS_SLAVE_BLSP_2 611 +#define MSM_BUS_SLAVE_USB_HSIC 612 +#define MSM_BUS_SLAVE_BLSP_1 613 +#define MSM_BUS_SLAVE_USB_HS 614 +#define MSM_BUS_SLAVE_PDM 615 +#define MSM_BUS_SLAVE_PERIPH_APU_CFG 616 +#define MSM_BUS_SLAVE_PNOC_MPU_CFG 617 +#define MSM_BUS_SLAVE_PRNG 618 +#define MSM_BUS_SLAVE_SERVICE_PNOC 619 +#define MSM_BUS_SLAVE_CLK_CTL 620 +#define MSM_BUS_SLAVE_CNOC_MSS 621 +#define MSM_BUS_SLAVE_SECURITY 622 +#define MSM_BUS_SLAVE_TCSR 623 +#define MSM_BUS_SLAVE_TLMM 624 +#define MSM_BUS_SLAVE_CRYPTO_0_CFG 625 +#define MSM_BUS_SLAVE_CRYPTO_1_CFG 626 +#define MSM_BUS_SLAVE_IMEM_CFG 627 +#define MSM_BUS_SLAVE_MESSAGE_RAM 628 +#define MSM_BUS_SLAVE_BIMC_CFG 629 +#define MSM_BUS_SLAVE_BOOT_ROM 630 +#define MSM_BUS_SLAVE_CNOC_MNOC_MMSS_CFG 631 +#define MSM_BUS_SLAVE_PMIC_ARB 632 +#define MSM_BUS_SLAVE_SPDM_WRAPPER 633 +#define MSM_BUS_SLAVE_DEHR_CFG 634 +#define MSM_BUS_SLAVE_QDSS_CFG 635 +#define MSM_BUS_SLAVE_RBCPR_CFG 636 +#define MSM_BUS_SLAVE_RBCPR_QDSS_APU_CFG 637 +#define MSM_BUS_SLAVE_SNOC_MPU_CFG 638 +#define MSM_BUS_SLAVE_CNOC_ONOC_CFG 639 +#define MSM_BUS_SLAVE_CNOC_MNOC_CFG 640 +#define MSM_BUS_SLAVE_PNOC_CFG 641 +#define MSM_BUS_SLAVE_SNOC_CFG 642 +#define MSM_BUS_SLAVE_EBI1_DLL_CFG 643 +#define MSM_BUS_SLAVE_PHY_APU_CFG 644 +#define MSM_BUS_SLAVE_EBI1_PHY_CFG 645 +#define MSM_BUS_SLAVE_SERVICE_CNOC 646 +#define MSM_BUS_SLAVE_IPS_CFG 647 +#define MSM_BUS_SLAVE_QPIC 648 +#define MSM_BUS_SLAVE_DSI_CFG 649 +#define MSM_BUS_SLAVE_UFS_CFG 650 +#define MSM_BUS_SLAVE_RBCPR_CX_CFG 651 +#define MSM_BUS_SLAVE_RBCPR_MX_CFG 652 +#define MSM_BUS_SLAVE_PCIE_CFG 653 +#define MSM_BUS_SLAVE_USB_PHYS_CFG 654 +#define MSM_BUS_SLAVE_VIDEO_CAP_CFG 655 +#define MSM_BUS_SLAVE_AVSYNC_CFG 656 +#define MSM_BUS_SLAVE_CRYPTO_2_CFG 657 +#define MSM_BUS_SLAVE_VPU_CFG 658 +#define MSM_BUS_SLAVE_BCAST_CFG 659 +#define MSM_BUS_SLAVE_KLM_CFG 660 +#define MSM_BUS_SLAVE_GENI_IR_CFG 661 +#define MSM_BUS_SLAVE_OCMEM_GFX 662 +#define MSM_BUS_SLAVE_CATS_128 663 +#define MSM_BUS_SLAVE_OCMEM_64 664 +#define MSM_BUS_SLAVE_PCIE_0 665 +#define MSM_BUS_SLAVE_PCIE_1 666 +#define MSM_BUS_SLAVE_PCIE_0_CFG 667 +#define MSM_BUS_SLAVE_PCIE_1_CFG 668 +#define MSM_BUS_SLAVE_SRVC_MNOC 669 +#define MSM_BUS_SLAVE_USB_HS2 670 +#define MSM_BUS_SLAVE_AUDIO 671 +#define MSM_BUS_SLAVE_TCU 672 +#define MSM_BUS_SLAVE_APPSS 673 +#define MSM_BUS_SLAVE_PCIE_PARF 674 +#define MSM_BUS_SLAVE_USB3_PHY_CFG 675 +#define MSM_BUS_SLAVE_IPA_CFG 676 +#define MSM_BUS_SLAVE_A0NOC_SNOC 677 +#define MSM_BUS_SLAVE_A1NOC_SNOC 678 +#define MSM_BUS_SLAVE_A2NOC_SNOC 679 +#define MSM_BUS_SLAVE_HMSS_L3 680 +#define MSM_BUS_SLAVE_PIMEM_CFG 681 +#define MSM_BUS_SLAVE_DCC_CFG 682 +#define MSM_BUS_SLAVE_QDSS_RBCPR_APU_CFG 683 +#define MSM_BUS_SLAVE_PCIE_2_CFG 684 +#define MSM_BUS_SLAVE_PCIE20_AHB2PHY 685 +#define MSM_BUS_SLAVE_A0NOC_CFG 686 +#define MSM_BUS_SLAVE_A1NOC_CFG 687 +#define MSM_BUS_SLAVE_A2NOC_CFG 688 +#define MSM_BUS_SLAVE_A1NOC_MPU_CFG 689 +#define MSM_BUS_SLAVE_A2NOC_MPU_CFG 690 +#define MSM_BUS_SLAVE_A0NOC_SMMU_CFG 691 +#define MSM_BUS_SLAVE_A1NOC_SMMU_CFG 692 +#define MSM_BUS_SLAVE_A2NOC_SMMU_CFG 693 +#define MSM_BUS_SLAVE_LPASS_SMMU_CFG 694 +#define MSM_BUS_SLAVE_MMAGIC_CFG 695 +#define MSM_BUS_SLAVE_VENUS_THROTTLE_CFG 696 +#define MSM_BUS_SLAVE_SSC_CFG 697 +#define MSM_BUS_SLAVE_DSA_CFG 698 +#define MSM_BUS_SLAVE_DSA_MPU_CFG 699 +#define MSM_BUS_SLAVE_DISPLAY_THROTTLE_CFG 700 +#define MSM_BUS_SLAVE_SMMU_CPP_CFG 701 +#define MSM_BUS_SLAVE_SMMU_JPEG_CFG 702 +#define MSM_BUS_SLAVE_SMMU_MDP_CFG 703 +#define MSM_BUS_SLAVE_SMMU_ROTATOR_CFG 704 +#define MSM_BUS_SLAVE_SMMU_VENUS_CFG 705 +#define MSM_BUS_SLAVE_SMMU_VFE_CFG 706 +#define MSM_BUS_SLAVE_A0NOC_MPU_CFG 707 +#define MSM_BUS_SLAVE_VMEM_CFG 708 +#define MSM_BUS_SLAVE_CAMERA_THROTTLE_CFG 709 +#define MSM_BUS_SLAVE_VMEM 710 +#define MSM_BUS_SLAVE_AHB2PHY 711 +#define MSM_BUS_SLAVE_PIMEM 712 +#define MSM_BUS_SLAVE_SNOC_VMEM 713 +#define MSM_BUS_SLAVE_PCIE_2 714 +#define MSM_BUS_SLAVE_RBCPR_MX 715 +#define MSM_BUS_SLAVE_RBCPR_CX 716 +#define MSM_BUS_SLAVE_BIMC_PCNOC 717 +#define MSM_BUS_SLAVE_PCNOC_BIMC_1 718 +#define MSM_BUS_SLAVE_SGMII 719 +#define MSM_BUS_SLAVE_SPMI_FETCHER 720 +#define MSM_BUS_PNOC_SLV_6 721 +#define MSM_BUS_SLAVE_MMSS_SMMU_CFG 722 +#define MSM_BUS_SLAVE_WLAN 723 +#define MSM_BUS_SLAVE_CRVIRT_A2NOC 724 +#define MSM_BUS_SLAVE_CNOC_A2NOC 725 +#define MSM_BUS_SLAVE_GLM 726 +#define MSM_BUS_SLAVE_GNOC_BIMC 727 +#define MSM_BUS_SLAVE_GNOC_SNOC 728 +#define MSM_BUS_SLAVE_QM_CFG 729 +#define MSM_BUS_SLAVE_TLMM_EAST 730 +#define MSM_BUS_SLAVE_TLMM_NORTH 731 +#define MSM_BUS_SLAVE_TLMM_WEST 732 +#define MSM_BUS_SLAVE_SKL 733 +#define MSM_BUS_SLAVE_LPASS_TCM 734 +#define MSM_BUS_SLAVE_TLMM_SOUTH 735 +#define MSM_BUS_SLAVE_TLMM_CENTER 736 +#define MSM_BUS_MSS_NAV_CE_MPU_CFG 737 +#define MSM_BUS_SLAVE_A2NOC_THROTTLE_CFG 738 +#define MSM_BUS_SLAVE_CDSP 739 +#define MSM_BUS_SLAVE_CDSP_SMMU_CFG 740 +#define MSM_BUS_SLAVE_LPASS_MPU_CFG 741 +#define MSM_BUS_SLAVE_CSI_PHY_CFG 742 +#define MSM_BUS_SLAVE_LAST 743 + +#define MSM_BUS_SYSTEM_FPB_SLAVE_SYSTEM MSM_BUS_SYSTEM_SLAVE_SYSTEM_FPB +#define MSM_BUS_CPSS_FPB_SLAVE_SYSTEM MSM_BUS_SYSTEM_SLAVE_CPSS_FPB + +/* + * ID's used in RPM messages + */ +#define ICBID_MASTER_APPSS_PROC 0 +#define ICBID_MASTER_MSS_PROC 1 +#define ICBID_MASTER_MNOC_BIMC 2 +#define ICBID_MASTER_SNOC_BIMC 3 +#define ICBID_MASTER_SNOC_BIMC_0 ICBID_MASTER_SNOC_BIMC +#define ICBID_MASTER_CNOC_MNOC_MMSS_CFG 4 +#define ICBID_MASTER_CNOC_MNOC_CFG 5 +#define ICBID_MASTER_GFX3D 6 +#define ICBID_MASTER_JPEG 7 +#define ICBID_MASTER_MDP 8 +#define ICBID_MASTER_MDP0 ICBID_MASTER_MDP +#define ICBID_MASTER_MDPS ICBID_MASTER_MDP +#define ICBID_MASTER_VIDEO 9 +#define ICBID_MASTER_VIDEO_P0 ICBID_MASTER_VIDEO +#define ICBID_MASTER_VIDEO_P1 10 +#define ICBID_MASTER_VFE 11 +#define ICBID_MASTER_VFE0 ICBID_MASTER_VFE +#define ICBID_MASTER_CNOC_ONOC_CFG 12 +#define ICBID_MASTER_JPEG_OCMEM 13 +#define ICBID_MASTER_MDP_OCMEM 14 +#define ICBID_MASTER_VIDEO_P0_OCMEM 15 +#define ICBID_MASTER_VIDEO_P1_OCMEM 16 +#define ICBID_MASTER_VFE_OCMEM 17 +#define ICBID_MASTER_LPASS_AHB 18 +#define ICBID_MASTER_QDSS_BAM 19 +#define ICBID_MASTER_SNOC_CFG 20 +#define ICBID_MASTER_BIMC_SNOC 21 +#define ICBID_MASTER_BIMC_SNOC_0 ICBID_MASTER_BIMC_SNOC +#define ICBID_MASTER_CNOC_SNOC 22 +#define ICBID_MASTER_CRYPTO 23 +#define ICBID_MASTER_CRYPTO_CORE0 ICBID_MASTER_CRYPTO +#define ICBID_MASTER_CRYPTO_CORE1 24 +#define ICBID_MASTER_LPASS_PROC 25 +#define ICBID_MASTER_MSS 26 +#define ICBID_MASTER_MSS_NAV 27 +#define ICBID_MASTER_OCMEM_DMA 28 +#define ICBID_MASTER_PNOC_SNOC 29 +#define ICBID_MASTER_WCSS 30 +#define ICBID_MASTER_QDSS_ETR 31 +#define ICBID_MASTER_USB3 32 +#define ICBID_MASTER_USB3_0 ICBID_MASTER_USB3 +#define ICBID_MASTER_SDCC_1 33 +#define ICBID_MASTER_SDCC_3 34 +#define ICBID_MASTER_SDCC_2 35 +#define ICBID_MASTER_SDCC_4 36 +#define ICBID_MASTER_TSIF 37 +#define ICBID_MASTER_BAM_DMA 38 +#define ICBID_MASTER_BLSP_2 39 +#define ICBID_MASTER_USB_HSIC 40 +#define ICBID_MASTER_BLSP_1 41 +#define ICBID_MASTER_USB_HS 42 +#define ICBID_MASTER_USB_HS1 ICBID_MASTER_USB_HS +#define ICBID_MASTER_PNOC_CFG 43 +#define ICBID_MASTER_SNOC_PNOC 44 +#define ICBID_MASTER_RPM_INST 45 +#define ICBID_MASTER_RPM_DATA 46 +#define ICBID_MASTER_RPM_SYS 47 +#define ICBID_MASTER_DEHR 48 +#define ICBID_MASTER_QDSS_DAP 49 +#define ICBID_MASTER_SPDM 50 +#define ICBID_MASTER_TIC 51 +#define ICBID_MASTER_SNOC_CNOC 52 +#define ICBID_MASTER_GFX3D_OCMEM 53 +#define ICBID_MASTER_GFX3D_GMEM ICBID_MASTER_GFX3D_OCMEM +#define ICBID_MASTER_OVIRT_SNOC 54 +#define ICBID_MASTER_SNOC_OVIRT 55 +#define ICBID_MASTER_SNOC_GVIRT ICBID_MASTER_SNOC_OVIRT +#define ICBID_MASTER_ONOC_OVIRT 56 +#define ICBID_MASTER_USB_HS2 57 +#define ICBID_MASTER_QPIC 58 +#define ICBID_MASTER_IPA 59 +#define ICBID_MASTER_DSI 60 +#define ICBID_MASTER_MDP1 61 +#define ICBID_MASTER_MDPE ICBID_MASTER_MDP1 +#define ICBID_MASTER_VPU_PROC 62 +#define ICBID_MASTER_VPU 63 +#define ICBID_MASTER_VPU0 ICBID_MASTER_VPU +#define ICBID_MASTER_CRYPTO_CORE2 64 +#define ICBID_MASTER_PCIE_0 65 +#define ICBID_MASTER_PCIE_1 66 +#define ICBID_MASTER_SATA 67 +#define ICBID_MASTER_UFS 68 +#define ICBID_MASTER_USB3_1 69 +#define ICBID_MASTER_VIDEO_OCMEM 70 +#define ICBID_MASTER_VPU1 71 +#define ICBID_MASTER_VCAP 72 +#define ICBID_MASTER_EMAC 73 +#define ICBID_MASTER_BCAST 74 +#define ICBID_MASTER_MMSS_PROC 75 +#define ICBID_MASTER_SNOC_BIMC_1 76 +#define ICBID_MASTER_SNOC_PCNOC 77 +#define ICBID_MASTER_AUDIO 78 +#define ICBID_MASTER_MM_INT_0 79 +#define ICBID_MASTER_MM_INT_1 80 +#define ICBID_MASTER_MM_INT_2 81 +#define ICBID_MASTER_MM_INT_BIMC 82 +#define ICBID_MASTER_MSS_INT 83 +#define ICBID_MASTER_PCNOC_CFG 84 +#define ICBID_MASTER_PCNOC_INT_0 85 +#define ICBID_MASTER_PCNOC_INT_1 86 +#define ICBID_MASTER_PCNOC_M_0 87 +#define ICBID_MASTER_PCNOC_M_1 88 +#define ICBID_MASTER_PCNOC_S_0 89 +#define ICBID_MASTER_PCNOC_S_1 90 +#define ICBID_MASTER_PCNOC_S_2 91 +#define ICBID_MASTER_PCNOC_S_3 92 +#define ICBID_MASTER_PCNOC_S_4 93 +#define ICBID_MASTER_PCNOC_S_6 94 +#define ICBID_MASTER_PCNOC_S_7 95 +#define ICBID_MASTER_PCNOC_S_8 96 +#define ICBID_MASTER_PCNOC_S_9 97 +#define ICBID_MASTER_QDSS_INT 98 +#define ICBID_MASTER_SNOC_INT_0 99 +#define ICBID_MASTER_SNOC_INT_1 100 +#define ICBID_MASTER_SNOC_INT_BIMC 101 +#define ICBID_MASTER_TCU_0 102 +#define ICBID_MASTER_TCU_1 103 +#define ICBID_MASTER_BIMC_INT_0 104 +#define ICBID_MASTER_BIMC_INT_1 105 +#define ICBID_MASTER_CAMERA 106 +#define ICBID_MASTER_RICA 107 +#define ICBID_MASTER_SNOC_BIMC_2 108 +#define ICBID_MASTER_BIMC_SNOC_1 109 +#define ICBID_MASTER_A0NOC_SNOC 110 +#define ICBID_MASTER_A1NOC_SNOC 111 +#define ICBID_MASTER_A2NOC_SNOC 112 +#define ICBID_MASTER_PIMEM 113 +#define ICBID_MASTER_SNOC_VMEM 114 +#define ICBID_MASTER_CPP 115 +#define ICBID_MASTER_CNOC_A1NOC 116 +#define ICBID_MASTER_PNOC_A1NOC 117 +#define ICBID_MASTER_HMSS 118 +#define ICBID_MASTER_PCIE_2 119 +#define ICBID_MASTER_ROTATOR 120 +#define ICBID_MASTER_VENUS_VMEM 121 +#define ICBID_MASTER_DCC 122 +#define ICBID_MASTER_MCDMA 123 +#define ICBID_MASTER_PCNOC_INT_2 124 +#define ICBID_MASTER_PCNOC_INT_3 125 +#define ICBID_MASTER_PCNOC_INT_4 126 +#define ICBID_MASTER_PCNOC_INT_5 127 +#define ICBID_MASTER_PCNOC_INT_6 128 +#define ICBID_MASTER_PCNOC_S_5 129 +#define ICBID_MASTER_SENSORS_AHB 130 +#define ICBID_MASTER_SENSORS_PROC 131 +#define ICBID_MASTER_QSPI 132 +#define ICBID_MASTER_VFE1 133 +#define ICBID_MASTER_SNOC_INT_2 134 +#define ICBID_MASTER_SMMNOC_BIMC 135 +#define ICBID_MASTER_CRVIRT_A1NOC 136 +#define ICBID_MASTER_XM_USB_HS1 137 +#define ICBID_MASTER_XI_USB_HS1 138 +#define ICBID_MASTER_PCNOC_BIMC_1 139 +#define ICBID_MASTER_BIMC_PCNOC 140 +#define ICBID_MASTER_XI_HSIC 141 +#define ICBID_MASTER_SGMII 142 +#define ICBID_MASTER_SPMI_FETCHER 143 +#define ICBID_MASTER_GNOC_BIMC 144 +#define ICBID_MASTER_CRVIRT_A2NOC 145 +#define ICBID_MASTER_CNOC_A2NOC 146 +#define ICBID_MASTER_WLAN 147 +#define ICBID_MASTER_MSS_CE 148 +#define ICBID_MASTER_CDSP_PROC 149 +#define ICBID_MASTER_GNOC_SNOC 150 + +#define ICBID_SLAVE_EBI1 0 +#define ICBID_SLAVE_APPSS_L2 1 +#define ICBID_SLAVE_BIMC_SNOC 2 +#define ICBID_SLAVE_BIMC_SNOC_0 ICBID_SLAVE_BIMC_SNOC +#define ICBID_SLAVE_CAMERA_CFG 3 +#define ICBID_SLAVE_DISPLAY_CFG 4 +#define ICBID_SLAVE_OCMEM_CFG 5 +#define ICBID_SLAVE_CPR_CFG 6 +#define ICBID_SLAVE_CPR_XPU_CFG 7 +#define ICBID_SLAVE_MISC_CFG 8 +#define ICBID_SLAVE_MISC_XPU_CFG 9 +#define ICBID_SLAVE_VENUS_CFG 10 +#define ICBID_SLAVE_GFX3D_CFG 11 +#define ICBID_SLAVE_MMSS_CLK_CFG 12 +#define ICBID_SLAVE_MMSS_CLK_XPU_CFG 13 +#define ICBID_SLAVE_MNOC_MPU_CFG 14 +#define ICBID_SLAVE_ONOC_MPU_CFG 15 +#define ICBID_SLAVE_MNOC_BIMC 16 +#define ICBID_SLAVE_SERVICE_MNOC 17 +#define ICBID_SLAVE_OCMEM 18 +#define ICBID_SLAVE_GMEM ICBID_SLAVE_OCMEM +#define ICBID_SLAVE_SERVICE_ONOC 19 +#define ICBID_SLAVE_APPSS 20 +#define ICBID_SLAVE_LPASS 21 +#define ICBID_SLAVE_USB3 22 +#define ICBID_SLAVE_USB3_0 ICBID_SLAVE_USB3 +#define ICBID_SLAVE_WCSS 23 +#define ICBID_SLAVE_SNOC_BIMC 24 +#define ICBID_SLAVE_SNOC_BIMC_0 ICBID_SLAVE_SNOC_BIMC +#define ICBID_SLAVE_SNOC_CNOC 25 +#define ICBID_SLAVE_IMEM 26 +#define ICBID_SLAVE_OCIMEM ICBID_SLAVE_IMEM +#define ICBID_SLAVE_SNOC_OVIRT 27 +#define ICBID_SLAVE_SNOC_GVIRT ICBID_SLAVE_SNOC_OVIRT +#define ICBID_SLAVE_SNOC_PNOC 28 +#define ICBID_SLAVE_SNOC_PCNOC ICBID_SLAVE_SNOC_PNOC +#define ICBID_SLAVE_SERVICE_SNOC 29 +#define ICBID_SLAVE_QDSS_STM 30 +#define ICBID_SLAVE_SDCC_1 31 +#define ICBID_SLAVE_SDCC_3 32 +#define ICBID_SLAVE_SDCC_2 33 +#define ICBID_SLAVE_SDCC_4 34 +#define ICBID_SLAVE_TSIF 35 +#define ICBID_SLAVE_BAM_DMA 36 +#define ICBID_SLAVE_BLSP_2 37 +#define ICBID_SLAVE_USB_HSIC 38 +#define ICBID_SLAVE_BLSP_1 39 +#define ICBID_SLAVE_USB_HS 40 +#define ICBID_SLAVE_USB_HS1 ICBID_SLAVE_USB_HS +#define ICBID_SLAVE_PDM 41 +#define ICBID_SLAVE_PERIPH_APU_CFG 42 +#define ICBID_SLAVE_PNOC_MPU_CFG 43 +#define ICBID_SLAVE_PRNG 44 +#define ICBID_SLAVE_PNOC_SNOC 45 +#define ICBID_SLAVE_PCNOC_SNOC ICBID_SLAVE_PNOC_SNOC +#define ICBID_SLAVE_SERVICE_PNOC 46 +#define ICBID_SLAVE_CLK_CTL 47 +#define ICBID_SLAVE_CNOC_MSS 48 +#define ICBID_SLAVE_PCNOC_MSS ICBID_SLAVE_CNOC_MSS +#define ICBID_SLAVE_SECURITY 49 +#define ICBID_SLAVE_TCSR 50 +#define ICBID_SLAVE_TLMM 51 +#define ICBID_SLAVE_CRYPTO_0_CFG 52 +#define ICBID_SLAVE_CRYPTO_1_CFG 53 +#define ICBID_SLAVE_IMEM_CFG 54 +#define ICBID_SLAVE_MESSAGE_RAM 55 +#define ICBID_SLAVE_BIMC_CFG 56 +#define ICBID_SLAVE_BOOT_ROM 57 +#define ICBID_SLAVE_CNOC_MNOC_MMSS_CFG 58 +#define ICBID_SLAVE_PMIC_ARB 59 +#define ICBID_SLAVE_SPDM_WRAPPER 60 +#define ICBID_SLAVE_DEHR_CFG 61 +#define ICBID_SLAVE_MPM 62 +#define ICBID_SLAVE_QDSS_CFG 63 +#define ICBID_SLAVE_RBCPR_CFG 64 +#define ICBID_SLAVE_RBCPR_CX_CFG ICBID_SLAVE_RBCPR_CFG +#define ICBID_SLAVE_RBCPR_QDSS_APU_CFG 65 +#define ICBID_SLAVE_CNOC_MNOC_CFG 66 +#define ICBID_SLAVE_SNOC_MPU_CFG 67 +#define ICBID_SLAVE_CNOC_ONOC_CFG 68 +#define ICBID_SLAVE_PNOC_CFG 69 +#define ICBID_SLAVE_SNOC_CFG 70 +#define ICBID_SLAVE_EBI1_DLL_CFG 71 +#define ICBID_SLAVE_PHY_APU_CFG 72 +#define ICBID_SLAVE_EBI1_PHY_CFG 73 +#define ICBID_SLAVE_RPM 74 +#define ICBID_SLAVE_CNOC_SNOC 75 +#define ICBID_SLAVE_SERVICE_CNOC 76 +#define ICBID_SLAVE_OVIRT_SNOC 77 +#define ICBID_SLAVE_OVIRT_OCMEM 78 +#define ICBID_SLAVE_USB_HS2 79 +#define ICBID_SLAVE_QPIC 80 +#define ICBID_SLAVE_IPS_CFG 81 +#define ICBID_SLAVE_DSI_CFG 82 +#define ICBID_SLAVE_USB3_1 83 +#define ICBID_SLAVE_PCIE_0 84 +#define ICBID_SLAVE_PCIE_1 85 +#define ICBID_SLAVE_PSS_SMMU_CFG 86 +#define ICBID_SLAVE_CRYPTO_2_CFG 87 +#define ICBID_SLAVE_PCIE_0_CFG 88 +#define ICBID_SLAVE_PCIE_1_CFG 89 +#define ICBID_SLAVE_SATA_CFG 90 +#define ICBID_SLAVE_SPSS_GENI_IR 91 +#define ICBID_SLAVE_UFS_CFG 92 +#define ICBID_SLAVE_AVSYNC_CFG 93 +#define ICBID_SLAVE_VPU_CFG 94 +#define ICBID_SLAVE_USB_PHY_CFG 95 +#define ICBID_SLAVE_RBCPR_MX_CFG 96 +#define ICBID_SLAVE_PCIE_PARF 97 +#define ICBID_SLAVE_VCAP_CFG 98 +#define ICBID_SLAVE_EMAC_CFG 99 +#define ICBID_SLAVE_BCAST_CFG 100 +#define ICBID_SLAVE_KLM_CFG 101 +#define ICBID_SLAVE_DISPLAY_PWM 102 +#define ICBID_SLAVE_GENI 103 +#define ICBID_SLAVE_SNOC_BIMC_1 104 +#define ICBID_SLAVE_AUDIO 105 +#define ICBID_SLAVE_CATS_0 106 +#define ICBID_SLAVE_CATS_1 107 +#define ICBID_SLAVE_MM_INT_0 108 +#define ICBID_SLAVE_MM_INT_1 109 +#define ICBID_SLAVE_MM_INT_2 110 +#define ICBID_SLAVE_MM_INT_BIMC 111 +#define ICBID_SLAVE_MMU_MODEM_XPU_CFG 112 +#define ICBID_SLAVE_MSS_INT 113 +#define ICBID_SLAVE_PCNOC_INT_0 114 +#define ICBID_SLAVE_PCNOC_INT_1 115 +#define ICBID_SLAVE_PCNOC_M_0 116 +#define ICBID_SLAVE_PCNOC_M_1 117 +#define ICBID_SLAVE_PCNOC_S_0 118 +#define ICBID_SLAVE_PCNOC_S_1 119 +#define ICBID_SLAVE_PCNOC_S_2 120 +#define ICBID_SLAVE_PCNOC_S_3 121 +#define ICBID_SLAVE_PCNOC_S_4 122 +#define ICBID_SLAVE_PCNOC_S_6 123 +#define ICBID_SLAVE_PCNOC_S_7 124 +#define ICBID_SLAVE_PCNOC_S_8 125 +#define ICBID_SLAVE_PCNOC_S_9 126 +#define ICBID_SLAVE_PRNG_XPU_CFG 127 +#define ICBID_SLAVE_QDSS_INT 128 +#define ICBID_SLAVE_RPM_XPU_CFG 129 +#define ICBID_SLAVE_SNOC_INT_0 130 +#define ICBID_SLAVE_SNOC_INT_1 131 +#define ICBID_SLAVE_SNOC_INT_BIMC 132 +#define ICBID_SLAVE_TCU 133 +#define ICBID_SLAVE_BIMC_INT_0 134 +#define ICBID_SLAVE_BIMC_INT_1 135 +#define ICBID_SLAVE_RICA_CFG 136 +#define ICBID_SLAVE_SNOC_BIMC_2 137 +#define ICBID_SLAVE_BIMC_SNOC_1 138 +#define ICBID_SLAVE_PNOC_A1NOC 139 +#define ICBID_SLAVE_SNOC_VMEM 140 +#define ICBID_SLAVE_A0NOC_SNOC 141 +#define ICBID_SLAVE_A1NOC_SNOC 142 +#define ICBID_SLAVE_A2NOC_SNOC 143 +#define ICBID_SLAVE_A0NOC_CFG 144 +#define ICBID_SLAVE_A0NOC_MPU_CFG 145 +#define ICBID_SLAVE_A0NOC_SMMU_CFG 146 +#define ICBID_SLAVE_A1NOC_CFG 147 +#define ICBID_SLAVE_A1NOC_MPU_CFG 148 +#define ICBID_SLAVE_A1NOC_SMMU_CFG 149 +#define ICBID_SLAVE_A2NOC_CFG 150 +#define ICBID_SLAVE_A2NOC_MPU_CFG 151 +#define ICBID_SLAVE_A2NOC_SMMU_CFG 152 +#define ICBID_SLAVE_AHB2PHY 153 +#define ICBID_SLAVE_CAMERA_THROTTLE_CFG 154 +#define ICBID_SLAVE_DCC_CFG 155 +#define ICBID_SLAVE_DISPLAY_THROTTLE_CFG 156 +#define ICBID_SLAVE_DSA_CFG 157 +#define ICBID_SLAVE_DSA_MPU_CFG 158 +#define ICBID_SLAVE_SSC_MPU_CFG 159 +#define ICBID_SLAVE_HMSS_L3 160 +#define ICBID_SLAVE_LPASS_SMMU_CFG 161 +#define ICBID_SLAVE_MMAGIC_CFG 162 +#define ICBID_SLAVE_PCIE20_AHB2PHY 163 +#define ICBID_SLAVE_PCIE_2 164 +#define ICBID_SLAVE_PCIE_2_CFG 165 +#define ICBID_SLAVE_PIMEM 166 +#define ICBID_SLAVE_PIMEM_CFG 167 +#define ICBID_SLAVE_QDSS_RBCPR_APU_CFG 168 +#define ICBID_SLAVE_RBCPR_CX 169 +#define ICBID_SLAVE_RBCPR_MX 170 +#define ICBID_SLAVE_SMMU_CPP_CFG 171 +#define ICBID_SLAVE_SMMU_JPEG_CFG 172 +#define ICBID_SLAVE_SMMU_MDP_CFG 173 +#define ICBID_SLAVE_SMMU_ROTATOR_CFG 174 +#define ICBID_SLAVE_SMMU_VENUS_CFG 175 +#define ICBID_SLAVE_SMMU_VFE_CFG 176 +#define ICBID_SLAVE_SSC_CFG 177 +#define ICBID_SLAVE_VENUS_THROTTLE_CFG 178 +#define ICBID_SLAVE_VMEM 179 +#define ICBID_SLAVE_VMEM_CFG 180 +#define ICBID_SLAVE_QDSS_MPU_CFG 181 +#define ICBID_SLAVE_USB3_PHY_CFG 182 +#define ICBID_SLAVE_IPA_CFG 183 +#define ICBID_SLAVE_PCNOC_INT_2 184 +#define ICBID_SLAVE_PCNOC_INT_3 185 +#define ICBID_SLAVE_PCNOC_INT_4 186 +#define ICBID_SLAVE_PCNOC_INT_5 187 +#define ICBID_SLAVE_PCNOC_INT_6 188 +#define ICBID_SLAVE_PCNOC_S_5 189 +#define ICBID_SLAVE_QSPI 190 +#define ICBID_SLAVE_A1NOC_MS_MPU_CFG 191 +#define ICBID_SLAVE_A2NOC_MS_MPU_CFG 192 +#define ICBID_SLAVE_MODEM_Q6_SMMU_CFG 193 +#define ICBID_SLAVE_MSS_MPU_CFG 194 +#define ICBID_SLAVE_MSS_PROC_MS_MPU_CFG 195 +#define ICBID_SLAVE_SKL 196 +#define ICBID_SLAVE_SNOC_INT_2 197 +#define ICBID_SLAVE_SMMNOC_BIMC 198 +#define ICBID_SLAVE_CRVIRT_A1NOC 199 +#define ICBID_SLAVE_SGMII 200 +#define ICBID_SLAVE_QHS4_APPS 201 +#define ICBID_SLAVE_BIMC_PCNOC 202 +#define ICBID_SLAVE_PCNOC_BIMC_1 203 +#define ICBID_SLAVE_SPMI_FETCHER 204 +#define ICBID_SLAVE_MMSS_SMMU_CFG 205 +#define ICBID_SLAVE_WLAN 206 +#define ICBID_SLAVE_CRVIRT_A2NOC 207 +#define ICBID_SLAVE_CNOC_A2NOC 208 +#define ICBID_SLAVE_GLM 209 +#define ICBID_SLAVE_GNOC_BIMC 210 +#define ICBID_SLAVE_GNOC_SNOC 211 +#define ICBID_SLAVE_QM_CFG 212 +#define ICBID_SLAVE_TLMM_EAST 213 +#define ICBID_SLAVE_TLMM_NORTH 214 +#define ICBID_SLAVE_TLMM_WEST 215 +#define ICBID_SLAVE_LPASS_TCM 216 +#define ICBID_SLAVE_TLMM_SOUTH 217 +#define ICBID_SLAVE_TLMM_CENTER 218 +#define ICBID_SLAVE_MSS_NAV_CE_MPU_CFG 219 +#define ICBID_SLAVE_A2NOC_THROTTLE_CFG 220 +#define ICBID_SLAVE_CDSP 221 +#define ICBID_SLAVE_CDSP_SMMU_CFG 222 +#define ICBID_SLAVE_LPASS_MPU_CFG 223 +#define ICBID_SLAVE_CSI_PHY_CFG 224 +#endif diff -Nruw linux-4.4.115-fbx/arch/metag/boot/dts/include/dt-bindings/msm./msm-bus-rule-ops.h linux-4.4.115-fbx/arch/metag/boot/dts/include/dt-bindings/msm/msm-bus-rule-ops.h --- linux-4.4.115-fbx/arch/metag/boot/dts/include/dt-bindings/msm./msm-bus-rule-ops.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-4.4.115-fbx/arch/metag/boot/dts/include/dt-bindings/msm/msm-bus-rule-ops.h 2019-01-22 16:16:28.179288750 +0100 @@ -0,0 +1,34 @@ +/* Copyright (c) 2014, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __MSM_BUS_RULE_OPS_H +#define __MSM_BUS_RULE_OPS_H + +#define FLD_IB 0 +#define FLD_AB 1 +#define FLD_CLK 2 + +#define OP_LE 0 +#define OP_LT 1 +#define OP_GE 2 +#define OP_GT 3 +#define OP_NOOP 4 + +#define RULE_STATE_NOT_APPLIED 0 +#define RULE_STATE_APPLIED 1 + +#define THROTTLE_ON 0 +#define THROTTLE_OFF 1 +#define THROTTLE_REG 2 + + +#endif diff -Nruw linux-4.4.115-fbx/arch/metag/boot/dts/include/dt-bindings/msm./pm.h linux-4.4.115-fbx/arch/metag/boot/dts/include/dt-bindings/msm/pm.h --- linux-4.4.115-fbx/arch/metag/boot/dts/include/dt-bindings/msm./pm.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-4.4.115-fbx/arch/metag/boot/dts/include/dt-bindings/msm/pm.h 2019-01-22 16:16:28.179288750 +0100 @@ -0,0 +1,25 @@ +/* Copyright (c) 2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __DT_MSM_PM_H__ +#define __DT_MSM_PM_H__ + +#define LPM_RESET_LVL_NONE 0 +#define LPM_RESET_LVL_RET 1 +#define LPM_RESET_LVL_GDHS 2 +#define LPM_RESET_LVL_PC 3 + +#define LPM_AFF_LVL_CPU 0 +#define LPM_AFF_LVL_L2 1 +#define LPM_AFF_LVL_CCI 2 + +#endif diff -Nruw linux-4.4.115-fbx/arch/metag/boot/dts/include/dt-bindings/msm./power-on.h linux-4.4.115-fbx/arch/metag/boot/dts/include/dt-bindings/msm/power-on.h --- linux-4.4.115-fbx/arch/metag/boot/dts/include/dt-bindings/msm./power-on.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-4.4.115-fbx/arch/metag/boot/dts/include/dt-bindings/msm/power-on.h 2019-01-22 16:16:28.179288750 +0100 @@ -0,0 +1,24 @@ +/* Copyright (c) 2015, 2017, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __MSM_POWER_ON_H__ +#define __MSM_POWER_ON_H__ + +#define PON_POWER_OFF_RESERVED 0x00 +#define PON_POWER_OFF_WARM_RESET 0x01 +#define PON_POWER_OFF_SHUTDOWN 0x04 +#define PON_POWER_OFF_DVDD_SHUTDOWN 0x05 +#define PON_POWER_OFF_HARD_RESET 0x07 +#define PON_POWER_OFF_DVDD_HARD_RESET 0x08 +#define PON_POWER_OFF_MAX_TYPE 0x10 + +#endif --- /dev/null 2019-10-24 16:47:25.704025805 +0200 +++ linux-4.4.115-fbx/arch/metag/boot/dts/include/dt-bindings/regulator/qcom,rpm-smd-regulator.h 2019-01-22 16:16:28.183288787 +0100 @@ -0,0 +1,28 @@ +/* Copyright (c) 2015, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __QCOM_RPM_SMD_REGULATOR_H +#define __QCOM_RPM_SMD_REGULATOR_H + +#define RPM_SMD_REGULATOR_LEVEL_NONE 0 +#define RPM_SMD_REGULATOR_LEVEL_RETENTION 16 +#define RPM_SMD_REGULATOR_LEVEL_RETENTION_PLUS 32 +#define RPM_SMD_REGULATOR_LEVEL_MIN_SVS 48 +#define RPM_SMD_REGULATOR_LEVEL_LOW_SVS 64 +#define RPM_SMD_REGULATOR_LEVEL_SVS 128 +#define RPM_SMD_REGULATOR_LEVEL_SVS_PLUS 192 +#define RPM_SMD_REGULATOR_LEVEL_NOM 256 +#define RPM_SMD_REGULATOR_LEVEL_NOM_PLUS 320 +#define RPM_SMD_REGULATOR_LEVEL_TURBO 384 +#define RPM_SMD_REGULATOR_LEVEL_BINNING 512 + +#endif --- /dev/null 2019-10-24 16:47:25.704025805 +0200 +++ linux-4.4.115-fbx/arch/mips/boot/dts/include/dt-bindings/clock/audio-ext-clk.h 2019-01-22 16:16:28.167288642 +0100 @@ -0,0 +1,30 @@ +/* Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __AUDIO_EXT_CLK_H +#define __AUDIO_EXT_CLK_H + +/* Audio External Clocks */ +#define AUDIO_PMI_CLK 0 +#define AUDIO_PMIC_LNBB_CLK 0 +#define AUDIO_AP_CLK 1 +#define AUDIO_AP_CLK2 2 +#define AUDIO_LPASS_MCLK 3 +#define AUDIO_LPASS_MCLK2 4 + +#define clk_audio_ap_clk 0x9b5727cb +#define clk_audio_pmi_clk 0xcbfe416d +#define clk_audio_ap_clk2 0x454d1e91 +#define clk_audio_lpass_mclk 0xf0f2a284 +#define clk_audio_pmi_lnbb_clk 0x57312343 + +#endif --- /dev/null 2019-10-24 16:47:25.704025805 +0200 +++ linux-4.4.115-fbx/arch/mips/boot/dts/include/dt-bindings/clock/msm-clocks-8996.h 2019-01-22 16:16:28.171288678 +0100 @@ -0,0 +1,574 @@ +/* Copyright (c) 2014-2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __MSM_CLOCKS_8996_H +#define __MSM_CLOCKS_8996_H + +#include "audio-ext-clk.h" + +/* clock_gcc controlled clocks */ +#define clk_cxo_clk_src 0x79e95308 +#define clk_pnoc_clk 0x4325d220 +#define clk_pnoc_a_clk 0x2808c12b +#define clk_bimc_clk 0x4b80bf00 +#define clk_bimc_a_clk 0x4b25668a +#define clk_cnoc_clk 0xd5ccb7f4 +#define clk_cnoc_a_clk 0xd8fe2ccc +#define clk_snoc_clk 0x2c341aa0 +#define clk_snoc_a_clk 0x8fcef2af +#define clk_bb_clk1 0xf5304268 +#define clk_bb_clk1_ao 0xfa113810 +#define clk_bb_clk1_pin 0x6dd0a779 +#define clk_bb_clk1_pin_ao 0x9b637772 +#define clk_bb_clk2 0xfe15cb87 +#define clk_bb_clk2_ao 0x59682706 +#define clk_bb_clk2_pin 0x498938e5 +#define clk_bb_clk2_pin_ao 0x52513787 +#define clk_bimc_msmbus_clk 0xd212feea +#define clk_bimc_msmbus_a_clk 0x71d1a499 +#define clk_ce1_a_clk 0x44a833fe +#define clk_cnoc_msmbus_clk 0x62228b5d +#define clk_cnoc_msmbus_a_clk 0x67442955 +#define clk_cxo_clk_src_ao 0x64eb6004 +#define clk_cxo_dwc3_clk 0xf79c19f6 +#define clk_cxo_lpm_clk 0x94adbf3d +#define clk_cxo_otg_clk 0x4eec0bb9 +#define clk_cxo_pil_lpass_clk 0xe17f0ff6 +#define clk_cxo_pil_ssc_clk 0x81832015 +#define clk_div_clk1 0xaa1157a6 +#define clk_div_clk1_ao 0x6b943d68 +#define clk_div_clk2 0xd454019f +#define clk_div_clk2_ao 0x53f9e788 +#define clk_div_clk3 0xa9a55a68 +#define clk_div_clk3_ao 0x3d6725a8 +#define clk_ipa_a_clk 0xeeec2919 +#define clk_ipa_clk 0xfa685cda +#define clk_ln_bb_clk 0x3ab0b36d +#define clk_ln_bb_a_clk 0xc7257ea8 +#define clk_ln_bb_clk_pin 0x1b1c476a +#define clk_ln_bb_a_clk_pin 0x9cbb5411 +#define clk_mcd_ce1_clk 0xbb615d26 +#define clk_pnoc_keepalive_a_clk 0xf8f91f0b +#define clk_pnoc_msmbus_clk 0x38b95c77 +#define clk_pnoc_msmbus_a_clk 0x8c9b4e93 +#define clk_pnoc_pm_clk 0xd6f7dfb9 +#define clk_pnoc_sps_clk 0xd482ecc7 +#define clk_qdss_a_clk 0xdd121669 +#define clk_qdss_clk 0x1492202a +#define clk_rf_clk1 0xaabeea5a +#define clk_rf_clk1_ao 0x72a10cb8 +#define clk_rf_clk1_pin 0x8f463562 +#define clk_rf_clk1_pin_ao 0x62549ff6 +#define clk_rf_clk2 0x24a30992 +#define clk_rf_clk2_ao 0x944d8bbd +#define clk_rf_clk2_pin 0xa7c5602a +#define clk_rf_clk2_pin_ao 0x2d75eb4d +#define clk_snoc_msmbus_clk 0xe6900bb6 +#define clk_snoc_msmbus_a_clk 0x5d4683bd +#define clk_mcd_ce1_clk 0xbb615d26 +#define clk_qcedev_ce1_clk 0x293f97b0 +#define clk_qcrypto_ce1_clk 0xa6ac14df +#define clk_qseecom_ce1_clk 0xaa858373 +#define clk_scm_ce1_clk 0xd8ebcc62 +#define clk_ce1_clk 0x42229c55 +#define clk_gcc_ce1_ahb_m_clk 0x2eb28c01 +#define clk_gcc_ce1_axi_m_clk 0xc174dfba +#define clk_measure_only_bimc_hmss_axi_clk 0xc1cc4f11 +#define clk_aggre1_noc_clk 0x049abba8 +#define clk_aggre1_noc_a_clk 0xc12e4220 +#define clk_aggre2_noc_clk 0xaa681404 +#define clk_aggre2_noc_a_clk 0xcab67089 +#define clk_mmssnoc_axi_rpm_clk 0x4d7f8cdc +#define clk_mmssnoc_axi_rpm_a_clk 0xfbea899b +#define clk_mmssnoc_axi_clk 0xdb4b31e6 +#define clk_mmssnoc_axi_a_clk 0xd4970614 +#define clk_mmssnoc_gds_clk 0x06a22afa + +#define clk_gpll0 0x1ebe3bc4 +#define clk_gpll0_ao 0xa1368304 +#define clk_gpll0_out_main 0xe9374de7 +#define clk_gpll4 0xb3b5d85b +#define clk_gpll4_out_main 0xa9a0ab9d +#define clk_ufs_axi_clk_src 0x297ca380 +#define clk_pcie_aux_clk_src 0xebc50566 +#define clk_usb30_master_clk_src 0xc6262f89 +#define clk_usb20_master_clk_src 0x5680ac83 +#define clk_ufs_ice_core_clk_src 0xda8e7119 +#define clk_blsp1_qup1_i2c_apps_clk_src 0x17f78f5e +#define clk_blsp1_qup1_spi_apps_clk_src 0xf534c4fa +#define clk_blsp1_qup2_i2c_apps_clk_src 0x8de71c79 +#define clk_blsp1_qup2_spi_apps_clk_src 0x33cf809a +#define clk_blsp1_qup3_i2c_apps_clk_src 0xf161b902 +#define clk_blsp1_qup3_spi_apps_clk_src 0x5e95683f +#define clk_blsp1_qup4_i2c_apps_clk_src 0xb2ecce68 +#define clk_blsp1_qup4_spi_apps_clk_src 0xddb5bbdb +#define clk_blsp1_qup5_i2c_apps_clk_src 0x71ea7804 +#define clk_blsp1_qup5_spi_apps_clk_src 0x9752f35f +#define clk_blsp1_qup6_i2c_apps_clk_src 0x28806803 +#define clk_blsp1_qup6_spi_apps_clk_src 0x44a1edc4 +#define clk_blsp1_uart1_apps_clk_src 0xf8146114 +#define clk_blsp1_uart2_apps_clk_src 0xfc9c2f73 +#define clk_blsp1_uart3_apps_clk_src 0x600497f2 +#define clk_blsp1_uart4_apps_clk_src 0x56bff15c +#define clk_blsp1_uart5_apps_clk_src 0x218ef697 +#define clk_blsp1_uart6_apps_clk_src 0x8fbdbe4c +#define clk_blsp2_qup1_i2c_apps_clk_src 0xd6d1e95d +#define clk_blsp2_qup1_spi_apps_clk_src 0xcc1b8365 +#define clk_blsp2_qup2_i2c_apps_clk_src 0x603b5c51 +#define clk_blsp2_qup2_spi_apps_clk_src 0xd577dc44 +#define clk_blsp2_qup3_i2c_apps_clk_src 0xea82959c +#define clk_blsp2_qup3_spi_apps_clk_src 0xd04b1e92 +#define clk_blsp2_qup4_i2c_apps_clk_src 0x73dc968c +#define clk_blsp2_qup4_spi_apps_clk_src 0x25d4a2b1 +#define clk_blsp2_qup5_i2c_apps_clk_src 0xcc3698bd +#define clk_blsp2_qup5_spi_apps_clk_src 0xfa0cf45e +#define clk_blsp2_qup6_i2c_apps_clk_src 0x2fa53151 +#define clk_blsp2_qup6_spi_apps_clk_src 0x5ca86755 +#define clk_blsp2_uart1_apps_clk_src 0x562c66dc +#define clk_blsp2_uart2_apps_clk_src 0xdd448080 +#define clk_blsp2_uart3_apps_clk_src 0x46b2e90f +#define clk_blsp2_uart4_apps_clk_src 0x23a093d2 +#define clk_blsp2_uart5_apps_clk_src 0xe067616a +#define clk_blsp2_uart6_apps_clk_src 0xe02d2829 +#define clk_gp1_clk_src 0xad85b97a +#define clk_gp2_clk_src 0xfb1f0065 +#define clk_gp3_clk_src 0x63b693d6 +#define clk_hmss_rbcpr_clk_src 0xedd9a474 +#define clk_pdm2_clk_src 0x31e494fd +#define clk_sdcc1_apps_clk_src 0xd4975db2 +#define clk_sdcc2_apps_clk_src 0xfc46c821 +#define clk_sdcc3_apps_clk_src 0xea34c7f4 +#define clk_sdcc4_apps_clk_src 0x7aaaaa0c +#define clk_tsif_ref_clk_src 0x4e9042d1 +#define clk_usb20_mock_utmi_clk_src 0xc3aaeecb +#define clk_usb30_mock_utmi_clk_src 0xa024a976 +#define clk_usb3_phy_aux_clk_src 0x15eec63c +#define clk_gcc_qusb2phy_prim_reset 0x07550fa1 +#define clk_gcc_qusb2phy_sec_reset 0x3f3a87d0 +#define clk_gcc_periph_noc_usb20_ahb_clk 0xfb9f26e9 +#define clk_gcc_mmss_gcc_dbg_clk 0xe89d461c +#define clk_cpu_dbg_clk 0x6550dfa9 +#define clk_gcc_blsp1_ahb_clk 0x8caa5b4f +#define clk_gcc_blsp1_qup1_i2c_apps_clk 0xc303fae9 +#define clk_gcc_blsp1_qup1_spi_apps_clk 0x759a76b0 +#define clk_gcc_blsp1_qup2_i2c_apps_clk 0x1076f220 +#define clk_gcc_blsp1_qup2_spi_apps_clk 0x3e77d48f +#define clk_gcc_blsp1_qup3_i2c_apps_clk 0x9e25ac82 +#define clk_gcc_blsp1_qup3_spi_apps_clk 0xfb978880 +#define clk_gcc_blsp1_qup4_i2c_apps_clk 0xd7f40f6f +#define clk_gcc_blsp1_qup4_spi_apps_clk 0x80f8722f +#define clk_gcc_blsp1_qup5_i2c_apps_clk 0xacae5604 +#define clk_gcc_blsp1_qup5_spi_apps_clk 0xbf3e15d7 +#define clk_gcc_blsp1_qup6_i2c_apps_clk 0x5c6ad820 +#define clk_gcc_blsp1_qup6_spi_apps_clk 0x780d9f85 +#define clk_gcc_blsp1_uart1_apps_clk 0xc7c62f90 +#define clk_gcc_blsp1_uart2_apps_clk 0xf8a61c96 +#define clk_gcc_blsp1_uart3_apps_clk 0xc3298bd7 +#define clk_gcc_blsp1_uart4_apps_clk 0x26be16c0 +#define clk_gcc_blsp1_uart5_apps_clk 0x28a6bc74 +#define clk_gcc_blsp1_uart6_apps_clk 0x28fd3466 +#define clk_gcc_blsp2_ahb_clk 0x8f283c1d +#define clk_gcc_blsp2_qup1_i2c_apps_clk 0x9ace11dd +#define clk_gcc_blsp2_qup1_spi_apps_clk 0xa32604cc +#define clk_gcc_blsp2_qup2_i2c_apps_clk 0x1bf9a57e +#define clk_gcc_blsp2_qup2_spi_apps_clk 0xbf54ca6d +#define clk_gcc_blsp2_qup3_i2c_apps_clk 0x336d4170 +#define clk_gcc_blsp2_qup3_spi_apps_clk 0xc68509d6 +#define clk_gcc_blsp2_qup4_i2c_apps_clk 0xbd22539d +#define clk_gcc_blsp2_qup4_spi_apps_clk 0x01a72b93 +#define clk_gcc_blsp2_qup5_i2c_apps_clk 0xe2b2ce1d +#define clk_gcc_blsp2_qup5_spi_apps_clk 0xf40999cd +#define clk_gcc_blsp2_qup6_i2c_apps_clk 0x894bcea4 +#define clk_gcc_blsp2_qup6_spi_apps_clk 0xfe1bd34a +#define clk_gcc_blsp2_uart1_apps_clk 0x8c3512ff +#define clk_gcc_blsp2_uart2_apps_clk 0x1e1965a3 +#define clk_gcc_blsp2_uart3_apps_clk 0x382415ab +#define clk_gcc_blsp2_uart4_apps_clk 0x87a44b42 +#define clk_gcc_blsp2_uart5_apps_clk 0x5cd30649 +#define clk_gcc_blsp2_uart6_apps_clk 0x8feee5ab +#define clk_gcc_boot_rom_ahb_clk 0xde2adeb1 +#define clk_gcc_gp1_clk 0x057f7b69 +#define clk_gcc_gp2_clk 0x9bf83ffd +#define clk_gcc_gp3_clk 0xec6539ee +#define clk_gcc_hmss_rbcpr_clk 0x699183be +#define clk_gcc_mmss_noc_cfg_ahb_clk 0xb41a9d99 +#define clk_gcc_pcie_0_aux_clk 0x3d2e3ece +#define clk_gcc_pcie_0_cfg_ahb_clk 0x4dd325c3 +#define clk_gcc_pcie_0_mstr_axi_clk 0x3f85285b +#define clk_gcc_pcie_0_slv_axi_clk 0xd69638a1 +#define clk_gcc_pcie_0_pipe_clk 0x4f37621e +#define clk_gcc_pcie_0_phy_reset 0xdc3201c1 +#define clk_gcc_pcie_1_aux_clk 0xc9bb962c +#define clk_gcc_pcie_1_cfg_ahb_clk 0xb6338658 +#define clk_gcc_pcie_1_mstr_axi_clk 0xc20f6269 +#define clk_gcc_pcie_1_slv_axi_clk 0xd54e40d6 +#define clk_gcc_pcie_1_pipe_clk 0xc1627422 +#define clk_gcc_pcie_1_phy_reset 0x674481bb +#define clk_gcc_pcie_2_aux_clk 0xa4dc7ae8 +#define clk_gcc_pcie_2_cfg_ahb_clk 0x4f1d3121 +#define clk_gcc_pcie_2_mstr_axi_clk 0x9e81724a +#define clk_gcc_pcie_2_slv_axi_clk 0x7990d8b2 +#define clk_gcc_pcie_2_pipe_clk 0xa757a834 +#define clk_gcc_pcie_2_phy_reset 0x82634880 +#define clk_gcc_pcie_phy_reset 0x9bc3c959 +#define clk_gcc_pcie_phy_com_reset 0x8bf513e6 +#define clk_gcc_pcie_phy_nocsr_com_phy_reset 0x0c16a2da +#define clk_gcc_pcie_phy_aux_clk 0x4746e74f +#define clk_gcc_pcie_phy_cfg_ahb_clk 0x8533671a +#define clk_gcc_pdm2_clk 0x99d55711 +#define clk_gcc_pdm_ahb_clk 0x365664f6 +#define clk_gcc_prng_ahb_clk 0x397e7eaa +#define clk_gcc_sdcc1_ahb_clk 0x691e0caa +#define clk_gcc_sdcc1_apps_clk 0x9ad6fb96 +#define clk_gcc_sdcc2_ahb_clk 0x23d5727f +#define clk_gcc_sdcc2_apps_clk 0x861b20ac +#define clk_gcc_sdcc3_ahb_clk 0x565b2c03 +#define clk_gcc_sdcc3_apps_clk 0x0b27aeac +#define clk_gcc_sdcc4_ahb_clk 0x64f3e6a8 +#define clk_gcc_sdcc4_apps_clk 0xbf7c4dc8 +#define clk_gcc_tsif_ahb_clk 0x88d2822c +#define clk_gcc_tsif_ref_clk 0x8f1ed2c2 +#define clk_gcc_ufs_ahb_clk 0x1914bb84 +#define clk_gcc_ufs_axi_clk 0x47c743a7 +#define clk_gcc_ufs_ice_core_clk 0x310b0710 +#define clk_gcc_ufs_rx_cfg_clk 0xa6747786 +#define clk_gcc_ufs_rx_symbol_0_clk 0x7f43251c +#define clk_gcc_ufs_rx_symbol_1_clk 0x03182fde +#define clk_gcc_ufs_tx_cfg_clk 0xba2cf8b5 +#define clk_gcc_ufs_tx_symbol_0_clk 0x6a9f747a +#define clk_gcc_ufs_unipro_core_clk 0x2daf7fd2 +#define clk_gcc_ufs_sys_clk_core_clk 0x360e5ac8 +#define clk_gcc_ufs_tx_symbol_clk_core_clk 0xf6fb0df7 +#define clk_gcc_usb20_master_clk 0x24c3b66a +#define clk_gcc_usb20_mock_utmi_clk 0xe8db8203 +#define clk_gcc_usb20_sleep_clk 0x6e8cb4b2 +#define clk_gcc_usb30_master_clk 0xb3b4e2cb +#define clk_gcc_usb30_mock_utmi_clk 0xa800b65a +#define clk_gcc_usb30_sleep_clk 0xd0b65c92 +#define clk_gcc_usb3_phy_aux_clk 0x0d9a36e0 +#define clk_gcc_usb3_phy_pipe_clk 0xf279aff2 +#define clk_gcc_usb_phy_cfg_ahb2phy_clk 0xd1231a0e +#define clk_gcc_aggre0_cnoc_ahb_clk 0x53a35559 +#define clk_gcc_aggre0_snoc_axi_clk 0x3c446400 +#define clk_gcc_aggre0_noc_qosgen_extref_clk 0x8c4356ba +#define clk_hlos1_vote_lpass_core_smmu_clk 0x3aaa1743 +#define clk_hlos1_vote_lpass_adsp_smmu_clk 0xc76f702f +#define clk_gcc_usb3_phy_reset 0x03d559f1 +#define clk_gcc_usb3phy_phy_reset 0xb1a4f885 +#define clk_gcc_usb3_clkref_clk 0xb6cc8f01 +#define clk_gcc_hdmi_clkref_clk 0x4d4eec04 +#define clk_gcc_edp_clkref_clk 0xa8685c3f +#define clk_gcc_ufs_clkref_clk 0x92aa126f +#define clk_gcc_pcie_clkref_clk 0xa2e247fa +#define clk_gcc_rx2_usb2_clkref_clk 0x27ec24ba +#define clk_gcc_rx1_usb2_clkref_clk 0x53351d25 +#define clk_gcc_smmu_aggre0_ahb_clk 0x47a06ce4 +#define clk_gcc_smmu_aggre0_axi_clk 0x3cac4a6c +#define clk_gcc_sys_noc_usb3_axi_clk 0x94d26800 +#define clk_gcc_sys_noc_ufs_axi_clk 0x19d38312 +#define clk_gcc_aggre2_usb3_axi_clk 0xd5822a8e +#define clk_gcc_aggre2_ufs_axi_clk 0xb31e5191 +#define clk_gcc_mmss_gpll0_div_clk 0xdd06848d +#define clk_gcc_mmss_bimc_gfx_clk 0xe4f28754 +#define clk_gcc_bimc_gfx_clk 0x3edd69ad +#define clk_gcc_qspi_ahb_clk 0x96969dc8 +#define clk_gcc_qspi_ser_clk 0xfaf1e266 +#define clk_qspi_ser_clk_src 0x426676ee +#define clk_sdcc1_ice_core_clk_src 0xfd6a4301 +#define clk_gcc_sdcc1_ice_core_clk 0x0fd5680a +#define clk_gcc_mss_cfg_ahb_clk 0x111cde81 +#define clk_gcc_mss_snoc_axi_clk 0x0e71de85 +#define clk_gcc_mss_q6_bimc_axi_clk 0x67544d62 +#define clk_gcc_mss_mnoc_bimc_axi_clk 0xf665d03f +#define clk_gpll0_out_msscc 0x7d794829 +#define clk_gcc_debug_mux_v2 0xf7e749f0 +#define clk_gcc_dcc_ahb_clk 0xfa14a88c +#define clk_gcc_aggre0_noc_mpu_cfg_ahb_clk 0x5c1bb8e2 + +/* clock_mmss controlled clocks */ +#define clk_mmsscc_xo 0x05e63704 +#define clk_mmsscc_gpll0 0xe900c515 +#define clk_mmsscc_gpll0_div 0x73892e05 +#define clk_mmsscc_mmssnoc_ahb 0x7b4bd6f7 +#define clk_mmpll0 0xdd83b751 +#define clk_mmpll0_out_main 0x2f996a31 +#define clk_mmpll1 0x6da7fb90 +#define clk_mmpll1_out_main 0xa0d3a7da +#define clk_mmpll4 0x22c063c1 +#define clk_mmpll4_out_main 0xfb21c2fd +#define clk_mmpll3 0x18c76899 +#define clk_mmpll3_out_main 0x6eb6328f +#define clk_ahb_clk_src 0x86f49203 +#define clk_mmpll2 0x1190e4d8 +#define clk_mmpll2_out_main 0x1e9e24a8 +#define clk_mmpll8 0xd06ad45e +#define clk_mmpll8_out_main 0x75b1f386 +#define clk_mmpll9 0x1c50684c +#define clk_mmpll9_out_main 0x16b74937 +#define clk_mmpll5 0xa41e1936 +#define clk_mmpll5_out_main 0xcc1897bf +#define clk_csi0_clk_src 0x227e65bc +#define clk_vfe0_clk_src 0xa0c2bd8f +#define clk_vfe1_clk_src 0x4e357366 +#define clk_csi1_clk_src 0x6a2a6c36 +#define clk_csi2_clk_src 0x4113589f +#define clk_csi3_clk_src 0xfd934012 +#define clk_maxi_clk_src 0x52c09777 +#define clk_cpp_clk_src 0x8382f56d +#define clk_jpeg0_clk_src 0x9a0a0ac3 +#define clk_jpeg2_clk_src 0x5ad927f3 +#define clk_jpeg_dma_clk_src 0xb68afcea +#define clk_mdp_clk_src 0x6dc1f8f1 +#define clk_video_core_clk_src 0x8be4c944 +#define clk_fd_core_clk_src 0xe4799ab7 +#define clk_cci_clk_src 0x822f3d97 +#define clk_csiphy0_3p_clk_src 0xd2474b12 +#define clk_csiphy1_3p_clk_src 0x46a02aff +#define clk_csiphy2_3p_clk_src 0x1447813f +#define clk_camss_gp0_clk_src 0x6b57cfe6 +#define clk_camss_gp1_clk_src 0xf735368a +#define clk_jpeg_dma_clk_src 0xb68afcea +#define clk_mclk0_clk_src 0x266b3853 +#define clk_mclk1_clk_src 0xa73cad0c +#define clk_mclk2_clk_src 0x42545468 +#define clk_mclk3_clk_src 0x2bfbb714 +#define clk_csi0phytimer_clk_src 0xc8a309be +#define clk_csi1phytimer_clk_src 0x7c0fe23a +#define clk_csi2phytimer_clk_src 0x62ffea9c +#define clk_rbbmtimer_clk_src 0x17649ecc +#define clk_esc0_clk_src 0xb41d7c38 +#define clk_esc1_clk_src 0x3b0afa42 +#define clk_hdmi_clk_src 0xb40aeea9 +#define clk_vsync_clk_src 0xecb43940 +#define clk_rbcpr_clk_src 0x2c2e9af2 +#define clk_video_subcore0_clk_src 0x88d79636 +#define clk_video_subcore1_clk_src 0x4966930c +#define clk_mmss_bto_ahb_clk 0xfdf8c361 +#define clk_camss_ahb_clk 0xc4ff91d4 +#define clk_camss_cci_ahb_clk 0x04c4441a +#define clk_camss_cci_clk 0xd6cb5eb9 +#define clk_camss_cpp_ahb_clk 0x12e9a87b +#define clk_camss_cpp_clk 0xb82f366b +#define clk_camss_cpp_axi_clk 0x5598c804 +#define clk_camss_cpp_vbif_ahb_clk 0xb5f31be4 +#define clk_camss_csi0_ahb_clk 0x6e29c972 +#define clk_camss_csi0_clk 0x30862ddb +#define clk_camss_csi0phy_clk 0x2cecfb84 +#define clk_camss_csi0pix_clk 0x6946f77b +#define clk_camss_csi0rdi_clk 0x83645ef5 +#define clk_camss_csi1_ahb_clk 0xccc15f06 +#define clk_camss_csi1_clk 0xb150f052 +#define clk_camss_csi1phy_clk 0xb989f06d +#define clk_camss_csi1pix_clk 0x58d19bf3 +#define clk_camss_csi1rdi_clk 0x4d2f3352 +#define clk_camss_csi2_ahb_clk 0x92d02d75 +#define clk_camss_csi2_clk 0x74fc92e8 +#define clk_camss_csi2phy_clk 0xda05d9d8 +#define clk_camss_csi2pix_clk 0xf8ed0731 +#define clk_camss_csi2rdi_clk 0xdc1b2081 +#define clk_camss_csi3_ahb_clk 0xee5e459c +#define clk_camss_csi3_clk 0x39488fdd +#define clk_camss_csi3phy_clk 0x8b6063b9 +#define clk_camss_csi3pix_clk 0xd82bd467 +#define clk_camss_csi3rdi_clk 0xb6750046 +#define clk_camss_csi_vfe0_clk 0x3023937a +#define clk_camss_csi_vfe1_clk 0xe66fa522 +#define clk_camss_csiphy0_3p_clk 0xf2a54f5a +#define clk_camss_csiphy1_3p_clk 0x8bf70cb2 +#define clk_camss_csiphy2_3p_clk 0x1c14c939 +#define clk_camss_gp0_clk 0xcee7e51d +#define clk_camss_gp1_clk 0x41f1c2e3 +#define clk_camss_ispif_ahb_clk 0x9a212c6d +#define clk_camss_jpeg0_clk 0x0b0e2db7 +#define clk_camss_jpeg2_clk 0xd7291c8d +#define clk_camss_jpeg_ahb_clk 0x1f47fd28 +#define clk_camss_jpeg_axi_clk 0x9e5545c8 +#define clk_camss_jpeg_dma_clk 0x2336e65d +#define clk_camss_mclk0_clk 0xcf0c61e0 +#define clk_camss_mclk1_clk 0xd1410ed4 +#define clk_camss_mclk2_clk 0x851286f2 +#define clk_camss_mclk3_clk 0x4db11c45 +#define clk_camss_micro_ahb_clk 0x33a23277 +#define clk_camss_csi0phytimer_clk 0xff93b3c8 +#define clk_camss_csi1phytimer_clk 0x6c399ab6 +#define clk_camss_csi2phytimer_clk 0x24f47f49 +#define clk_camss_top_ahb_clk 0x8f8b2d33 +#define clk_camss_vfe_ahb_clk 0x595197bc +#define clk_camss_vfe_axi_clk 0x273d4c31 +#define clk_camss_vfe0_ahb_clk 0x4652833c +#define clk_camss_vfe0_clk 0x1e9bb8c4 +#define clk_camss_vfe0_stream_clk 0x22835fa4 +#define clk_camss_vfe1_ahb_clk 0x6a56abd3 +#define clk_camss_vfe1_clk 0x5bffa69b +#define clk_camss_vfe1_stream_clk 0x92f849b9 +#define clk_fd_ahb_clk 0x868a2c5c +#define clk_fd_core_clk 0x3badcae4 +#define clk_fd_core_uar_clk 0x7e624e15 +#define clk_gpu_ahb_clk 0xf97f1d43 +#define clk_gpu_aon_isense_clk 0xa9e9b297 +#define clk_gpu_gx_gfx3d_clk 0xb7ece823 +#define clk_gpu_mx_clk 0xb80ccedf +#define clk_gpu_gx_rbbmtimer_clk 0xdeba634e +#define clk_mdss_ahb_clk 0x684ccb41 +#define clk_mdss_axi_clk 0xcc07d687 +#define clk_mdss_esc0_clk 0x28cafbe6 +#define clk_mdss_esc1_clk 0xc22c6883 +#define clk_mdss_hdmi_ahb_clk 0x01cef516 +#define clk_mdss_hdmi_clk 0x097a6de9 +#define clk_mdss_mdp_clk 0x618336ac +#define clk_mdss_vsync_clk 0x42a022d3 +#define clk_mmss_misc_ahb_clk 0xea30b0e7 +#define clk_mmss_misc_cxo_clk 0xe620cd80 +#define clk_mmagic_bimc_noc_cfg_ahb_clk 0x12d5ba72 +#define clk_mmagic_camss_axi_clk 0xa8b1c16b +#define clk_mmagic_camss_noc_cfg_ahb_clk 0x5182c819 +#define clk_mmss_mmagic_cfg_ahb_clk 0x5e94a822 +#define clk_mmagic_mdss_axi_clk 0xa0359d10 +#define clk_mmagic_mdss_noc_cfg_ahb_clk 0x9c6d5482 +#define clk_mmagic_video_axi_clk 0x7b9219c3 +#define clk_mmagic_video_noc_cfg_ahb_clk 0x5124d256 +#define clk_mmss_mmagic_ahb_clk 0x3d15f2b0 +#define clk_mmss_mmagic_maxi_clk 0xbdaf5af7 +#define clk_mmss_rbcpr_ahb_clk 0x623ba55f +#define clk_mmss_rbcpr_clk 0x69a23a6f +#define clk_mmss_spdm_cpp_clk 0xefe35cd2 +#define clk_mmss_spdm_jpeg_dma_clk 0xcb7bd5a0 +#define clk_smmu_cpp_ahb_clk 0x3ad82d84 +#define clk_smmu_cpp_axi_clk 0xa6bb2f4a +#define clk_smmu_jpeg_ahb_clk 0x10c436ec +#define clk_smmu_jpeg_axi_clk 0x41112f37 +#define clk_smmu_mdp_ahb_clk 0x04994cb2 +#define clk_smmu_mdp_axi_clk 0x7fd71687 +#define clk_smmu_rot_ahb_clk 0xa30772c9 +#define clk_smmu_rot_axi_clk 0xfed7c078 +#define clk_smmu_vfe_ahb_clk 0x4dabebe7 +#define clk_smmu_vfe_axi_clk 0xde483725 +#define clk_smmu_video_ahb_clk 0x2d738e2c +#define clk_smmu_video_axi_clk 0xe2b5b887 +#define clk_video_ahb_clk 0x90775cfb +#define clk_video_axi_clk 0xe6c16dba +#define clk_video_core_clk 0x7e876ec3 +#define clk_video_maxi_clk 0x97749db6 +#define clk_video_subcore0_clk 0xb6f63e6c +#define clk_video_subcore1_clk 0x26c29cb4 +#define clk_vmem_ahb_clk 0xab6223ff +#define clk_vmem_maxi_clk 0x15ef32db +#define clk_mmss_debug_mux 0xe646ffda +#define clk_mmss_gcc_dbg_clk 0xafa4d48a +#define clk_gfx3d_clk_src 0x917f76ef +#define clk_extpclk_clk_src 0xb2c31abd +#define clk_mdss_byte0_clk 0xf5a03f64 +#define clk_mdss_byte1_clk 0xb8c7067d +#define clk_mdss_extpclk_clk 0xfa5aadb0 +#define clk_mdss_pclk0_clk 0x3487234a +#define clk_mdss_pclk1_clk 0xd5804246 +#define clk_gpu_gcc_dbg_clk 0x0ccc42cd +#define clk_mdss_mdp_vote_clk 0x588460a4 +#define clk_mdss_rotator_vote_clk 0x5b1f675e +#define clk_mmpll2_postdiv_clk 0x4fdeaaba +#define clk_mmpll8_postdiv_clk 0xedf57882 +#define clk_mmpll9_postdiv_clk 0x3064b618 +#define clk_gfx3d_clk_src_v2 0x4210acb7 +#define clk_byte0_clk_src 0x75cc885b +#define clk_byte1_clk_src 0x63c2c955 +#define clk_pclk0_clk_src 0xccac1f35 +#define clk_pclk1_clk_src 0x090f68ac +#define clk_ext_byte0_clk_src 0xfb32f31e +#define clk_ext_byte1_clk_src 0x585ef6d4 +#define clk_ext_pclk0_clk_src 0x087c1612 +#define clk_ext_pclk1_clk_src 0x8067c5a3 + +/* clock_debug controlled clocks */ +#define clk_gcc_debug_mux 0x8121ac15 + +/* external multimedia clocks */ +#define clk_dsi0pll_pixel_clk_mux 0x792379e1 +#define clk_dsi0pll_byte_clk_mux 0x60e83f06 +#define clk_dsi0pll_byte_clk_src 0xbbaa30be +#define clk_dsi0pll_pixel_clk_src 0x45b3260f +#define clk_dsi0pll_n2_div_clk 0x1474c213 +#define clk_dsi0pll_post_n1_div_clk 0xdab8c389 +#define clk_dsi0pll_vco_clk 0x15940d40 +#define clk_dsi1pll_pixel_clk_mux 0x36458019 +#define clk_dsi1pll_byte_clk_mux 0xb5a42b7b +#define clk_dsi1pll_byte_clk_src 0x63930a8f +#define clk_dsi1pll_pixel_clk_src 0x0e4c9b56 +#define clk_dsi1pll_n2_div_clk 0x2c9d4007 +#define clk_dsi1pll_post_n1_div_clk 0x03020041 +#define clk_dsi1pll_vco_clk 0x99797b50 +#define clk_mdss_dsi1_vco_clk_src 0xfcd15658 +#define clk_hdmi_vco_clk 0x66003284 + +#define clk_dsi0pll_shadow_byte_clk_src 0x177c029c +#define clk_dsi0pll_shadow_pixel_clk_src 0x98ae3c92 +#define clk_dsi0pll_shadow_n2_div_clk 0xd5f0dad9 +#define clk_dsi0pll_shadow_post_n1_div_clk 0x1f7c8cf8 +#define clk_dsi0pll_shadow_vco_clk 0xb100ca83 +#define clk_dsi1pll_shadow_byte_clk_src 0xfc021ce5 +#define clk_dsi1pll_shadow_pixel_clk_src 0xdcca3ffc +#define clk_dsi1pll_shadow_n2_div_clk 0x189541bf +#define clk_dsi1pll_shadow_post_n1_div_clk 0x1637020e +#define clk_dsi1pll_shadow_vco_clk 0x68d8b6f7 + +/* CPU clocks */ +#define clk_pwrcl_clk 0xc554130e +#define clk_pwrcl_pll 0x25454ca1 +#define clk_pwrcl_alt_pll 0xc445471b +#define clk_pwrcl_pll_main 0x28948e22 +#define clk_pwrcl_alt_pll_main 0x25c8270e +#define clk_pwrcl_hf_mux 0x77706ae6 +#define clk_pwrcl_lf_mux 0xd99e334d +#define clk_perfcl_clk 0x58869997 +#define clk_perfcl_pll 0x97dcec1c +#define clk_perfcl_alt_pll 0xfe2eaea1 +#define clk_perfcl_pll_main 0x0dbf0c0b +#define clk_perfcl_alt_pll_main 0x0b892aab +#define clk_perfcl_hf_mux 0x9e8bbe59 +#define clk_perfcl_lf_mux 0x2f9c278d +#define clk_cbf_pll 0xfe2e96a3 +#define clk_cbf_pll_main 0x2b05cf95 +#define clk_cbf_hf_mux 0x71244f73 +#define clk_cbf_clk 0x48e9e16b +#define clk_xo_ao 0x428c856d +#define clk_sys_apcsaux_clk 0x0b0dd513 +#define clk_cpu_debug_mux 0xc7acaa31 + +/* GCC block resets */ +#define QUSB2PHY_PRIM_BCR 0 +#define QUSB2PHY_SEC_BCR 1 +#define BLSP1_BCR 2 +#define BLSP2_BCR 3 +#define BOOT_ROM_BCR 4 +#define PRNG_BCR 5 +#define UFS_BCR 6 +#define USB_20_BCR 7 +#define USB_30_BCR 8 +#define USB3_PHY_BCR 9 +#define USB3PHY_PHY_BCR 10 +#define PCIE_0_PHY_BCR 11 +#define PCIE_1_PHY_BCR 12 +#define PCIE_2_PHY_BCR 13 +#define PCIE_PHY_BCR 14 +#define PCIE_PHY_COM_BCR 15 +#define PCIE_PHY_NOCSR_COM_PHY_BCR 16 + +/* MMSS Block resets */ +#define VIDEO_BCR 0 +#define MDSS_BCR 1 +#define CAMSS_MICRO_BCR 2 +#define CAMSS_JPEG_BCR 3 +#define CAMSS_VFE0_BCR 4 +#define CAMSS_VFE1_BCR 5 +#define FD_BCR 6 +#define GPU_GX_BCR 7 + +#endif --- /dev/null 2019-10-24 16:47:25.704025805 +0200 +++ linux-4.4.115-fbx/arch/mips/boot/dts/include/dt-bindings/clock/msm-clocks-8998.h 2019-01-22 16:16:28.171288678 +0100 @@ -0,0 +1,534 @@ +/* Copyright (c) 2015-2017, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __MSM_CLOCKS_8998_H +#define __MSM_CLOCKS_8998_H + +#include "audio-ext-clk.h" + +/* clock_rpm controlled clocks */ +#define clk_ce1_clk 0x42229c55 +#define clk_ce1_a_clk 0x44a833fe +#define clk_cxo_clk_src 0x79e95308 +#define clk_bimc_clk 0x4b80bf00 +#define clk_bimc_a_clk 0x4b25668a +#define clk_cnoc_clk 0xd5ccb7f4 +#define clk_cnoc_a_clk 0xd8fe2ccc +#define clk_snoc_clk 0x2c341aa0 +#define clk_snoc_a_clk 0x8fcef2af +#define clk_cnoc_periph_clk 0xb11e9cf9 +#define clk_cnoc_periph_a_clk 0x1d7faa2e +#define clk_cnoc_periph_keepalive_a_clk 0x7287aef2 +#define clk_ln_bb_clk1 0xb867b147 +#define clk_ln_bb_clk1_ao 0x7f63a93a +#define clk_ln_bb_clk1_pin 0x6fc5653c +#define clk_ln_bb_clk1_pin_ao 0x25d625bf +#define clk_ln_bb_clk2 0xf83e6387 +#define clk_ln_bb_clk2_ao 0x96f09628 +#define clk_ln_bb_clk2_pin 0xa9ebe8d5 +#define clk_ln_bb_clk2_pin_ao 0x89a1226f +#define clk_ln_bb_clk3 0x4f52a39e +#define clk_ln_bb_clk3_ao 0xb15eba76 +#define clk_ln_bb_clk3_pin 0xc4de7dad +#define clk_ln_bb_clk3_pin_ao 0xc01022e8 +#define clk_bimc_msmbus_clk 0xd212feea +#define clk_bimc_msmbus_a_clk 0x71d1a499 +#define clk_cnoc_msmbus_clk 0x62228b5d +#define clk_cnoc_msmbus_a_clk 0x67442955 +#define clk_cxo_clk_src_ao 0x64eb6004 +#define clk_cxo_dwc3_clk 0xf79c19f6 +#define clk_cxo_lpm_clk 0x94adbf3d +#define clk_cxo_otg_clk 0x4eec0bb9 +#define clk_cxo_pil_lpass_clk 0xe17f0ff6 +#define clk_cxo_pil_ssc_clk 0x81832015 +#define clk_cxo_pil_spss_clk 0x5cd71a61 +#define clk_div_clk1 0xaa1157a6 +#define clk_div_clk1_ao 0x6b943d68 +#define clk_div_clk2 0xd454019f +#define clk_div_clk2_ao 0x53f9e788 +#define clk_div_clk3 0xa9a55a68 +#define clk_div_clk3_ao 0x3d6725a8 +#define clk_ipa_clk 0xfa685cda +#define clk_ipa_a_clk 0xeeec2919 +#define clk_mcd_ce1_clk 0xbb615d26 +#define clk_mmssnoc_axi_clk 0xdb4b31e6 +#define clk_mmssnoc_axi_a_clk 0xd4970614 +#define clk_qcedev_ce1_clk 0x293f97b0 +#define clk_qcrypto_ce1_clk 0xa6ac14df +#define clk_qdss_clk 0x1492202a +#define clk_qdss_a_clk 0xdd121669 +#define clk_qseecom_ce1_clk 0xaa858373 +#define clk_rf_clk1 0xaabeea5a +#define clk_rf_clk1_ao 0x72a10cb8 +#define clk_rf_clk1_pin 0x8f463562 +#define clk_rf_clk1_pin_ao 0x62549ff6 +#define clk_rf_clk2 0x24a30992 +#define clk_rf_clk2_ao 0x944d8bbd +#define clk_rf_clk2_pin 0xa7c5602a +#define clk_rf_clk2_pin_ao 0x2d75eb4d +#define clk_rf_clk3 0xb673936b +#define clk_rf_clk3_ao 0x038bb968 +#define clk_rf_clk3_pin 0x726f53f5 +#define clk_rf_clk3_pin_ao 0x76f9240f +#define clk_scm_ce1_clk 0xd8ebcc62 +#define clk_snoc_msmbus_clk 0xe6900bb6 +#define clk_snoc_msmbus_a_clk 0x5d4683bd +#define clk_gcc_ce1_ahb_m_clk 0x2eb28c01 +#define clk_gcc_ce1_axi_m_clk 0xc174dfba +#define clk_aggre1_noc_clk 0x049abba8 +#define clk_aggre1_noc_a_clk 0xc12e4220 +#define clk_aggre2_noc_clk 0xaa681404 +#define clk_aggre2_noc_a_clk 0xcab67089 +#define clk_measure_only_bimc_hmss_axi_clk 0xc1cc4f11 + +/* clock_gcc controlled clocks*/ +#define clk_debug_mmss_clk 0x977c99b6 +#define clk_debug_rpm_clk 0x8e2b07ca +#define clk_debug_cpu_clk 0x0e696b2b +#define clk_gpu_gcc_debug_clk 0x3eb88190 +#define clk_gfx_gcc_debug_clk 0xa3a64fec +#define clk_gpll0 0x1ebe3bc4 +#define clk_gpll0_out_main 0xe9374de7 +#define clk_gpll0_ao 0xa1368304 +#define clk_gcc_mmss_gpll0_clk 0x8050f008 +#define clk_gcc_mmss_gpll0_div_clk 0xdd06848d +#define clk_gcc_gpu_gpll0_clk 0xdad7a7a4 +#define clk_gcc_gpu_gpll0_div_clk 0x07d16c6a +#define clk_gpll4 0xb3b5d85b +#define clk_gpll4_out_main 0xa9a0ab9d +#define clk_usb30_master_clk_src 0xc6262f89 +#define clk_pcie_aux_clk_src 0xebc50566 +#define clk_ufs_axi_clk_src 0x297ca380 +#define clk_blsp1_qup1_i2c_apps_clk_src 0x17f78f5e +#define clk_blsp1_qup1_spi_apps_clk_src 0xf534c4fa +#define clk_blsp1_qup2_i2c_apps_clk_src 0x8de71c79 +#define clk_blsp1_qup2_spi_apps_clk_src 0x33cf809a +#define clk_blsp1_qup3_i2c_apps_clk_src 0xf161b902 +#define clk_blsp1_qup3_spi_apps_clk_src 0x5e95683f +#define clk_blsp1_qup4_i2c_apps_clk_src 0xb2ecce68 +#define clk_blsp1_qup4_spi_apps_clk_src 0xddb5bbdb +#define clk_blsp1_qup5_i2c_apps_clk_src 0x71ea7804 +#define clk_blsp1_qup5_spi_apps_clk_src 0x9752f35f +#define clk_blsp1_qup6_i2c_apps_clk_src 0x28806803 +#define clk_blsp1_qup6_spi_apps_clk_src 0x44a1edc4 +#define clk_blsp1_uart1_apps_clk_src 0xf8146114 +#define clk_blsp1_uart2_apps_clk_src 0xfc9c2f73 +#define clk_blsp1_uart3_apps_clk_src 0x600497f2 +#define clk_blsp2_qup1_i2c_apps_clk_src 0xd6d1e95d +#define clk_blsp2_qup1_spi_apps_clk_src 0xcc1b8365 +#define clk_blsp2_qup2_i2c_apps_clk_src 0x603b5c51 +#define clk_blsp2_qup2_spi_apps_clk_src 0xd577dc44 +#define clk_blsp2_qup3_i2c_apps_clk_src 0xea82959c +#define clk_blsp2_qup3_spi_apps_clk_src 0xd04b1e92 +#define clk_blsp2_qup4_i2c_apps_clk_src 0x73dc968c +#define clk_blsp2_qup4_spi_apps_clk_src 0x25d4a2b1 +#define clk_blsp2_qup5_i2c_apps_clk_src 0xcc3698bd +#define clk_blsp2_qup5_spi_apps_clk_src 0xfa0cf45e +#define clk_blsp2_qup6_i2c_apps_clk_src 0x2fa53151 +#define clk_blsp2_qup6_spi_apps_clk_src 0x5ca86755 +#define clk_blsp2_uart1_apps_clk_src 0x562c66dc +#define clk_blsp2_uart2_apps_clk_src 0xdd448080 +#define clk_blsp2_uart3_apps_clk_src 0x46b2e90f +#define clk_gp1_clk_src 0xad85b97a +#define clk_gp2_clk_src 0xfb1f0065 +#define clk_gp3_clk_src 0x63b693d6 +#define clk_hmss_rbcpr_clk_src 0xedd9a474 +#define clk_pdm2_clk_src 0x31e494fd +#define clk_sdcc2_apps_clk_src 0xfc46c821 +#define clk_sdcc4_apps_clk_src 0x7aaaaa0c +#define clk_tsif_ref_clk_src 0x4e9042d1 +#define clk_ufs_ice_core_clk_src 0xda8e7119 +#define clk_ufs_phy_aux_clk_src 0xc6bca085 +#define clk_ufs_unipro_core_clk_src 0x179e80a9 +#define clk_usb30_mock_utmi_clk_src 0xa024a976 +#define clk_usb3_phy_aux_clk_src 0x15eec63c +#define clk_qspi_ref_clk_src 0xfe6b8e11 +#define clk_gcc_pcie_phy_0_reset 0x6bb4df33 +#define clk_gcc_usb3_phy_reset 0x03d559f1 +#define clk_gcc_usb3phy_phy_reset 0xb1a4f885 +#define clk_gcc_aggre1_ufs_axi_clk 0x873459d8 +#define clk_gcc_aggre1_ufs_axi_hw_ctl_clk 0x117a6f39 +#define clk_gcc_aggre1_usb3_axi_clk 0xc5c3fbe8 +#define clk_gcc_bimc_mss_q6_axi_clk 0x7437988f +#define clk_gcc_blsp1_ahb_clk 0x8caa5b4f +#define clk_gcc_blsp1_qup1_i2c_apps_clk 0xc303fae9 +#define clk_gcc_blsp1_qup1_spi_apps_clk 0x759a76b0 +#define clk_gcc_blsp1_qup2_i2c_apps_clk 0x1076f220 +#define clk_gcc_blsp1_qup2_spi_apps_clk 0x3e77d48f +#define clk_gcc_blsp1_qup3_i2c_apps_clk 0x9e25ac82 +#define clk_gcc_blsp1_qup3_spi_apps_clk 0xfb978880 +#define clk_gcc_blsp1_qup4_i2c_apps_clk 0xd7f40f6f +#define clk_gcc_blsp1_qup4_spi_apps_clk 0x80f8722f +#define clk_gcc_blsp1_qup5_i2c_apps_clk 0xacae5604 +#define clk_gcc_blsp1_qup5_spi_apps_clk 0xbf3e15d7 +#define clk_gcc_blsp1_qup6_i2c_apps_clk 0x5c6ad820 +#define clk_gcc_blsp1_qup6_spi_apps_clk 0x780d9f85 +#define clk_gcc_blsp1_uart1_apps_clk 0xc7c62f90 +#define clk_gcc_blsp1_uart2_apps_clk 0xf8a61c96 +#define clk_gcc_blsp1_uart3_apps_clk 0xc3298bd7 +#define clk_gcc_blsp2_ahb_clk 0x8f283c1d +#define clk_gcc_blsp2_qup1_i2c_apps_clk 0x9ace11dd +#define clk_gcc_blsp2_qup1_spi_apps_clk 0xa32604cc +#define clk_gcc_blsp2_qup2_i2c_apps_clk 0x1bf9a57e +#define clk_gcc_blsp2_qup2_spi_apps_clk 0xbf54ca6d +#define clk_gcc_blsp2_qup3_i2c_apps_clk 0x336d4170 +#define clk_gcc_blsp2_qup3_spi_apps_clk 0xc68509d6 +#define clk_gcc_blsp2_qup4_i2c_apps_clk 0xbd22539d +#define clk_gcc_blsp2_qup4_spi_apps_clk 0x01a72b93 +#define clk_gcc_blsp2_qup5_i2c_apps_clk 0xe2b2ce1d +#define clk_gcc_blsp2_qup5_spi_apps_clk 0xf40999cd +#define clk_gcc_blsp2_qup6_i2c_apps_clk 0x894bcea4 +#define clk_gcc_blsp2_qup6_spi_apps_clk 0xfe1bd34a +#define clk_gcc_blsp2_uart1_apps_clk 0x8c3512ff +#define clk_gcc_blsp2_uart2_apps_clk 0x1e1965a3 +#define clk_gcc_blsp2_uart3_apps_clk 0x382415ab +#define clk_gcc_boot_rom_ahb_clk 0xde2adeb1 +#define clk_gcc_bimc_gfx_clk 0x3edd69ad +#define clk_gcc_cfg_noc_usb3_axi_clk 0x9ea4c2d9 +#define clk_gcc_gp1_clk 0x057f7b69 +#define clk_gcc_gp2_clk 0x9bf83ffd +#define clk_gcc_gp3_clk 0xec6539ee +#define clk_gcc_gpu_bimc_gfx_clk 0x3909459b +#define clk_gcc_gpu_cfg_ahb_clk 0x72f20a57 +#define clk_gcc_gpu_iref_clk 0xfd82abad +#define clk_gcc_hmss_dvm_bus_clk 0x17cc8b53 +#define clk_gcc_hmss_rbcpr_clk 0x699183be +#define clk_hmss_gpll0_clk_src 0x17eb05d0 +#define clk_hmss_gpll4_clk_src 0x20456cae +#define clk_gcc_mmss_sys_noc_axi_clk 0x4467b15b +#define clk_gcc_mss_at_clk 0x1692c5aa +#define clk_nav_gcc_dbg_clk 0x2221c544 +#define clk_gcc_pcie_0_aux_clk 0x3d2e3ece +#define clk_gcc_pcie_0_cfg_ahb_clk 0x4dd325c3 +#define clk_gcc_pcie_0_mstr_axi_clk 0x3f85285b +#define clk_gcc_pcie_0_pipe_clk 0x4f37621e +#define clk_gcc_pcie_0_slv_axi_clk 0xd69638a1 +#define clk_gcc_pcie_phy_aux_clk 0x4746e74f +#define clk_gcc_pdm2_clk 0x99d55711 +#define clk_gcc_pdm_ahb_clk 0x365664f6 +#define clk_gcc_prng_ahb_clk 0x397e7eaa +#define clk_gcc_sdcc2_ahb_clk 0x23d5727f +#define clk_gcc_sdcc2_apps_clk 0x861b20ac +#define clk_gcc_sdcc4_ahb_clk 0x64f3e6a8 +#define clk_gcc_sdcc4_apps_clk 0xbf7c4dc8 +#define clk_gcc_tsif_ahb_clk 0x88d2822c +#define clk_gcc_tsif_ref_clk 0x8f1ed2c2 +#define clk_gcc_ufs_ahb_clk 0x1914bb84 +#define clk_gcc_ufs_axi_clk 0x47c743a7 +#define clk_gcc_ufs_axi_hw_ctl_clk 0x69385b45 +#define clk_gcc_ufs_ice_core_clk 0x310b0710 +#define clk_gcc_ufs_ice_core_hw_ctl_clk 0x84e15a5b +#define clk_gcc_ufs_phy_aux_clk 0x17acc8fb +#define clk_gcc_ufs_phy_aux_hw_ctl_clk 0x7dbdb2e2 +#define clk_gcc_ufs_rx_symbol_0_clk 0x7f43251c +#define clk_gcc_ufs_rx_symbol_1_clk 0x03182fde +#define clk_gcc_ufs_tx_symbol_0_clk 0x6a9f747a +#define clk_ufs_tx_symbol_0_clk 0xb3fcd0f7 +#define clk_ufs_rx_symbol_0_clk 0x17a0f1cd +#define clk_gcc_ufs_unipro_core_clk 0x2daf7fd2 +#define clk_gcc_ufs_unipro_core_hw_ctl_clk 0x4a4e0f3d +#define clk_gcc_usb30_master_clk 0xb3b4e2cb +#define clk_gcc_usb30_mock_utmi_clk 0xa800b65a +#define clk_gcc_usb30_sleep_clk 0xd0b65c92 +#define clk_gcc_usb3_phy_aux_clk 0x0d9a36e0 +#define clk_gcc_usb3_phy_pipe_clk 0xf279aff2 +#define clk_gcc_usb3_clkref_clk 0xb6cc8f00 +#define clk_gcc_hdmi_clkref_clk 0x4d4eec04 +#define clk_gcc_edp_clkref_clk 0xa8685c3f +#define clk_gcc_ufs_clkref_clk 0x92aa126f +#define clk_gcc_pcie_clkref_clk 0xa2e247fa +#define clk_gcc_rx2_qlink_clkref_clk 0xd0ba986d +#define clk_gcc_rx1_usb2_clkref_clk 0x53351d25 +#define clk_gcc_pcie_phy_reset 0x9bc3c959 +#define clk_gcc_pcie_phy_com_reset 0x8bf513e6 +#define clk_gcc_pcie_phy_nocsr_com_phy_reset 0x0c16a2da +#define clk_gcc_qusb2phy_prim_reset 0x07550fa1 +#define clk_gcc_qusb2phy_sec_reset 0x3f3a87d0 +#define clk_gcc_mmss_noc_cfg_ahb_clk 0xb41a9d99 +#define clk_gcc_dcc_ahb_clk 0xfa14a88c +#define clk_hlos1_vote_lpass_core_smmu_clk 0x3aaa1743 +#define clk_hlos1_vote_lpass_adsp_smmu_clk 0xc76f702f +#define clk_gcc_mss_cfg_ahb_clk 0x111cde81 +#define clk_gcc_mss_q6_bimc_axi_clk 0x67544d62 +#define clk_gcc_mss_mnoc_bimc_axi_clk 0xf665d03f +#define clk_gpll0_out_msscc 0x7d794829 +#define clk_gcc_mss_snoc_axi_clk 0x0e71de85 +#define clk_gcc_qspi_ref_clk 0x766a0f7c +#define clk_gcc_qspi_ahb_clk 0x96969dc8 +#define clk_gcc_debug_mux 0x8121ac15 + +/* clock_mmss controlled clocks */ +#define clk_mmsscc_xo 0x05e63704 +#define clk_mmsscc_gpll0 0xe900c515 +#define clk_mmsscc_gpll0_div 0x73892e05 +#define clk_mmpll0_pll 0x361e3cfd +#define clk_mmpll1_pll 0x198e426b +#define clk_mmpll3_pll 0x18c76899 +#define clk_mmpll4_pll 0x22c063c1 +#define clk_mmpll5_pll 0xa41e1936 +#define clk_mmpll6_pll 0xc56fb440 +#define clk_mmpll7_pll 0x3ac216af +#define clk_mmpll10_pll 0x2561263b +#define clk_mmpll0_pll_out 0x1e9e24a8 +#define clk_mmpll1_pll_out 0x5fa32257 +#define clk_mmpll3_pll_out 0x6eb6328f +#define clk_mmpll4_pll_out 0xfb21c2fd +#define clk_mmpll5_pll_out 0xcc1897bf +#define clk_mmpll6_pll_out 0xfb1060bd +#define clk_mmpll7_pll_out 0x767758ed +#define clk_mmpll10_pll_out 0x3c5668f3 +#define clk_ahb_clk_src 0x86f49203 +#define clk_csi0_clk_src 0x227e65bc +#define clk_vfe0_clk_src 0xa0c2bd8f +#define clk_vfe1_clk_src 0x4e357366 +#define clk_mdp_clk_src 0x6dc1f8f1 +#define clk_maxi_clk_src 0x52c09777 +#define clk_cpp_clk_src 0x8382f56d +#define clk_jpeg0_clk_src 0x9a0a0ac3 +#define clk_rot_clk_src 0xce49b56c +#define clk_video_core_clk_src 0x8be4c944 +#define clk_csi1_clk_src 0x6a2a6c36 +#define clk_csi2_clk_src 0x4113589f +#define clk_csi3_clk_src 0xfd934012 +#define clk_fd_core_clk_src 0xe4799ab7 +#define clk_ext_dp_phy_pll_vco 0x441b576b +#define clk_ext_dp_phy_pll_link 0xea12644c +#define clk_dp_link_clk_src 0x370d0626 +#define clk_dp_crypto_clk_src 0xf8faa811 +#define clk_dp_pixel_clk_src 0xf5dfbabf +#define clk_ext_extpclk_clk_src 0xe5b273af +#define clk_ext_pclk0_clk_src 0x087c1612 +#define clk_ext_pclk1_clk_src 0x8067c5a3 +#define clk_pclk0_clk_src 0xccac1f35 +#define clk_pclk1_clk_src 0x090f68ac +#define clk_video_subcore0_clk_src 0x88d79636 +#define clk_video_subcore1_clk_src 0x4966930c +#define clk_cci_clk_src 0x822f3d97 +#define clk_camss_gp0_clk_src 0x43b063e9 +#define clk_camss_gp1_clk_src 0xa3315f1b +#define clk_mclk0_clk_src 0x266b3853 +#define clk_mclk1_clk_src 0xa73cad0c +#define clk_mclk2_clk_src 0x42545468 +#define clk_mclk3_clk_src 0x2bfbb714 +#define clk_csiphy_clk_src 0x8cceb70a +#define clk_csi0phytimer_clk_src 0xc8a309be +#define clk_csi1phytimer_clk_src 0x7c0fe23a +#define clk_csi2phytimer_clk_src 0x62ffea9c +#define clk_ext_byte0_clk_src 0xfb32f31e +#define clk_ext_byte1_clk_src 0x585ef6d4 +#define clk_byte0_clk_src 0x75cc885b +#define clk_byte1_clk_src 0x63c2c955 +#define clk_dp_aux_clk_src 0x2b6e972b +#define clk_dp_gtc_clk_src 0xc5a86a42 +#define clk_esc0_clk_src 0xb41d7c38 +#define clk_esc1_clk_src 0x3b0afa42 +#define clk_extpclk_clk_src 0xb2c31abd +#define clk_hdmi_clk_src 0xb40aeea9 +#define clk_vsync_clk_src 0xecb43940 +#define clk_mmss_bimc_smmu_ahb_clk 0x4825baf4 +#define clk_mmss_bimc_smmu_axi_clk 0xc365ac39 +#define clk_mmss_snoc_dvm_axi_clk 0x2c159a11 +#define clk_mmss_camss_ahb_clk 0xa51f2c1d +#define clk_mmss_camss_cci_ahb_clk 0xfda8bb6a +#define clk_mmss_camss_cci_clk 0x71bb5c97 +#define clk_mmss_camss_cpp_ahb_clk 0xd5554f15 +#define clk_mmss_camss_cpp_clk 0x8e99ef57 +#define clk_mmss_camss_cpp_axi_clk 0xd84e390b +#define clk_mmss_camss_cpp_vbif_ahb_clk 0x1b33a88e +#define clk_mmss_camss_cphy_csid0_clk 0x56114361 +#define clk_mmss_camss_csi0_ahb_clk 0x2b58d241 +#define clk_mmss_camss_csi0_clk 0xccfe39ef +#define clk_mmss_camss_csi0pix_clk 0x9e26509d +#define clk_mmss_camss_csi0rdi_clk 0x01d5bf83 +#define clk_mmss_camss_cphy_csid1_clk 0x79fbcd8a +#define clk_mmss_camss_csi1_ahb_clk 0x7073244b +#define clk_mmss_camss_csi1_clk 0x3eeeaac0 +#define clk_mmss_camss_csi1pix_clk 0xf1375139 +#define clk_mmss_camss_csi1rdi_clk 0x43185024 +#define clk_mmss_camss_cphy_csid2_clk 0xf295e3ef +#define clk_mmss_camss_csi2_ahb_clk 0x681c1479 +#define clk_mmss_camss_csi2_clk 0x94524569 +#define clk_mmss_camss_csi2pix_clk 0xf4de617d +#define clk_mmss_camss_csi2rdi_clk 0x4bf01dc5 +#define clk_mmss_camss_cphy_csid3_clk 0x100188e9 +#define clk_mmss_camss_csi3_ahb_clk 0xfae7c29b +#define clk_mmss_camss_csi3_clk 0x55e4bbae +#define clk_mmss_camss_csi3pix_clk 0xc166a015 +#define clk_mmss_camss_csi3rdi_clk 0x6983a4cd +#define clk_mmss_camss_csi_vfe0_clk 0x3b30b798 +#define clk_mmss_camss_csi_vfe1_clk 0xfe729af7 +#define clk_mmss_camss_csiphy0_clk 0x96c81af8 +#define clk_mmss_camss_csiphy1_clk 0xee9ac2bb +#define clk_mmss_camss_csiphy2_clk 0x3365e70e +#define clk_mmss_fd_ahb_clk 0x4ff1da4d +#define clk_mmss_fd_core_clk 0x749e7eb0 +#define clk_mmss_fd_core_uar_clk 0x8ea480c5 +#define clk_mmss_camss_gp0_clk 0x3f7f6c87 +#define clk_mmss_camss_gp1_clk 0xdccdd730 +#define clk_mmss_camss_ispif_ahb_clk 0xbda4f0e3 +#define clk_mmss_camss_jpeg0_clk 0x4cc73b07 +#define clk_mmss_camss_jpeg0_vote_clk 0xc9efa6ac +#define clk_mmss_camss_jpeg0_dma_vote_clk 0x371ec109 +#define clk_mmss_camss_jpeg_ahb_clk 0xde1fece3 +#define clk_mmss_camss_jpeg_axi_clk 0x7534616b +#define clk_mmss_camss_mclk0_clk 0x056293a7 +#define clk_mmss_camss_mclk1_clk 0x96c7b69b +#define clk_mmss_camss_mclk2_clk 0x8820556e +#define clk_mmss_camss_mclk3_clk 0xf90ffb67 +#define clk_mmss_camss_micro_ahb_clk 0x6c6fd3c7 +#define clk_mmss_camss_csi0phytimer_clk 0x7a78864e +#define clk_mmss_camss_csi1phytimer_clk 0x6e6c1de5 +#define clk_mmss_camss_csi2phytimer_clk 0x0235e2de +#define clk_mmss_camss_top_ahb_clk 0x120618d6 +#define clk_mmss_camss_vfe0_ahb_clk 0x137bd0bd +#define clk_mmss_camss_vfe0_clk 0xead28288 +#define clk_mmss_camss_vfe0_stream_clk 0xa0428287 +#define clk_mmss_camss_vfe1_ahb_clk 0xac0154c0 +#define clk_mmss_camss_vfe1_clk 0xc216b14d +#define clk_mmss_camss_vfe1_stream_clk 0x745af3b6 +#define clk_mmss_camss_vfe_vbif_ahb_clk 0x0109a9c6 +#define clk_mmss_camss_vfe_vbif_axi_clk 0xe626d8a1 +#define clk_mmss_mdss_ahb_clk 0x85d37ab5 +#define clk_mmss_mdss_axi_clk 0xdf04fc1d +#define clk_mmss_mdss_byte0_clk 0x38105d25 +#define clk_mmss_mdss_byte0_intf_clk 0x38e5aa79 +#define clk_mmss_mdss_byte0_intf_div_clk 0x8604f181 +#define clk_mmss_mdss_byte1_clk 0xe0c21354 +#define clk_mmss_mdss_byte1_intf_clk 0xcf654d8e +#define clk_mmss_mdss_byte1_intf_div_clk 0xcdf334c5 +#define clk_mmss_mdss_dp_aux_clk 0x23125eb6 +#define clk_mmss_mdss_dp_crypto_clk 0x9a072d4e +#define clk_mmss_mdss_dp_link_clk 0x8dd302d1 +#define clk_mmss_mdss_dp_link_intf_clk 0x70e386e6 +#define clk_mmss_mdss_dp_pixel_clk 0xb707b765 +#define clk_mmss_mdss_dp_gtc_clk 0xb59c151a +#define clk_mmss_mdss_esc0_clk 0x5721ff83 +#define clk_mmss_mdss_esc1_clk 0xc3d0376b +#define clk_mmss_mdss_extpclk_clk 0x74d5a954 +#define clk_mmss_mdss_hdmi_clk 0x28460a6d +#define clk_mmss_mdss_hdmi_dp_ahb_clk 0x5448519f +#define clk_mmss_mdss_mdp_clk 0x43539b0e +#define clk_mmss_mdss_mdp_lut_clk 0x00627b2b +#define clk_mmss_mdss_pclk0_clk 0xcc0e909d +#define clk_mmss_mdss_pclk1_clk 0x850d9146 +#define clk_mmss_mdss_rot_clk 0xbb7e71c4 +#define clk_mmss_mdss_vsync_clk 0x629b36dc +#define clk_mmss_misc_ahb_clk 0xea30b0e7 +#define clk_mmss_misc_cxo_clk 0xe620cd80 +#define clk_mmss_mnoc_ahb_clk 0x49a394f4 +#define clk_mmss_mnoc_maxi_clk 0xd8b7278f +#define clk_mmss_video_subcore0_clk 0x23fae359 +#define clk_mmss_video_subcore1_clk 0x5213a0c7 +#define clk_mmss_video_ahb_clk 0x94334ae9 +#define clk_mmss_video_axi_clk 0xf3178ba5 +#define clk_mmss_video_core_clk 0x78f14c85 +#define clk_mmss_video_maxi_clk 0x1785ef88 +#define clk_mmss_vmem_ahb_clk 0x4b18955b +#define clk_mmss_vmem_maxi_clk 0xb6067889 +#define clk_mmss_debug_mux 0xe646ffda + +/* external multimedia clocks */ +#define clk_dsi0pll_byteclk_mux 0xecf2c434 +#define clk_dsi0pll_byteclk_src 0x6f6f740f +#define clk_dsi0pll_pclk_mux 0x6c9da335 +#define clk_dsi0pll_pclk_src 0x5efd85d4 +#define clk_dsi0pll_pclk_src_mux 0x84b14663 +#define clk_dsi0pll_post_bit_div 0xf46dcf27 +#define clk_dsi0pll_pll_out_div1 0xeda5b7fe +#define clk_dsi0pll_pll_out_div2 0x97fa476d +#define clk_dsi0pll_pll_out_div4 0x90a98ce0 +#define clk_dsi0pll_pll_out_div8 0x9d9d85cf +#define clk_dsi0pll_pll_out_mux 0x179c27ca +#define clk_dsi0pll_post_vco_mux 0xfaf9bd1f +#define clk_dsi0pll_post_vco_div1 0xabb50b2a +#define clk_dsi0pll_post_vco_div4 0xbe51c091 +#define clk_dsi0pll_bitclk_src 0x36c3c437 +#define clk_dsi0pll_vco_clk 0x15940d40 + +#define clk_dsi1pll_byteclk_mux 0x14e2f38f +#define clk_dsi1pll_byteclk_src 0x4b65c298 +#define clk_dsi1pll_pclk_mux 0x4c0518b5 +#define clk_dsi1pll_pclk_src 0xeddcd80e +#define clk_dsi1pll_pclk_src_mux 0x3651feb3 +#define clk_dsi1pll_post_bit_div 0x712f0260 +#define clk_dsi1pll_pll_out_div8 0x87628ddb +#define clk_dsi1pll_pll_out_div4 0x0d9a384b +#define clk_dsi1pll_pll_out_div2 0x0c9b5748 +#define clk_dsi1pll_pll_out_div1 0x3193164e +#define clk_dsi1pll_pll_out_mux 0x171bf8fd +#define clk_dsi1pll_post_vco_mux 0xc6a90d20 +#define clk_dsi1pll_post_vco_div1 0x6f47ca7d +#define clk_dsi1pll_post_vco_div4 0x90628974 +#define clk_dsi1pll_bitclk_src 0x13ab045b +#define clk_dsi1pll_vco_clk 0x99797b50 + +#define clk_dp_vco_clk 0xfcaaeec7 +#define clk_dp_link_2x_clk_divsel_five 0xcfe3f5dd +#define clk_vco_divsel_four_clk_src 0xe0da19c0 +#define clk_vco_divsel_two_clk_src 0xb5cfc6a8 +#define clk_vco_divided_clk_src_mux 0x3f8197c2 +#define clk_hdmi_vco_clk 0xbb7dc20d + +/* clock_gpu controlled clocks*/ +#define clk_gpucc_xo 0xc4e1a890 +#define clk_gpucc_gpll0 0x0db0e37f +#define clk_gfx3d_clk_src 0x917f76ef +#define clk_rbbmtimer_clk_src 0x17649ecc +#define clk_gfx3d_isense_clk_src 0xecc3eafa +#define clk_rbcpr_clk_src 0x2c2e9af2 +#define clk_gpu_debug_div_clk 0x75d6f53f +#define clk_gpucc_gfx3d_clk 0x95f01bd5 +#define clk_gpucc_rbbmtimer_clk 0x58a0a7ca +#define clk_gpucc_gfx3d_isense_clk 0xb2678e80 +#define clk_gpucc_cxo_clk 0x6532dcae +#define clk_gpucc_rbcpr_clk 0x7bd750e8 +#define clk_gpu_pll0_pll 0x0e61ab4d +#define clk_gpu_pll0_pll_out_even 0xb0ed5009 +#define clk_gpu_pll0_pll_out_odd 0x08c5a8a5 +#define clk_gpu_pll0_postdiv_clk 0x76c19f3c +#define clk_gpucc_mx_clk 0x1edbb879 +#define clk_gpucc_gcc_dbg_clk 0x9ae8cd3c +#define clk_gfxcc_dbg_clk 0x3ed47625 + +/* CPU clocks */ +#define clk_pwrcl_clk 0xc554130e +#define clk_perfcl_clk 0x58869997 +#define clk_sys_apcsaux_clk_gcc 0xf905e862 +#define clk_xo_ao 0x428c856d +#define clk_osm_clk_src 0xaabe68c3 +#define clk_cpu_debug_mux 0x3ae8bcb2 + +/* Audio External Clocks */ +#define clk_audio_ap_clk 0x9b5727cb +#define clk_audio_pmi_clk 0xcbfe416d +#define clk_audio_ap_clk2 0x454d1e91 + +/* GCC block resets */ +#define QUSB2PHY_PRIM_BCR 0 +#define QUSB2PHY_SEC_BCR 1 +#define BLSP1_BCR 2 +#define BLSP2_BCR 3 +#define BOOT_ROM_BCR 4 +#define PRNG_BCR 5 +#define UFS_BCR 6 +#define USB_30_BCR 7 +#define USB3_PHY_BCR 8 +#define USB3PHY_PHY_BCR 9 +#define PCIE_0_PHY_BCR 10 +#define PCIE_PHY_BCR 11 +#define PCIE_PHY_COM_BCR 12 +#define PCIE_PHY_NOCSR_COM_PHY_BCR 13 + +/* MMSS block resets */ +#define CAMSS_MICRO_BCR 0 + +#endif --- /dev/null 2019-10-24 16:47:25.704025805 +0200 +++ linux-4.4.115-fbx/arch/mips/boot/dts/include/dt-bindings/clock/msm-clocks-hwio-8998.h 2019-01-22 16:16:28.171288678 +0100 @@ -0,0 +1,395 @@ +/* Copyright (c) 2015-2017, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define CLKFLAG_NO_RATE_CACHE 0x00004000 + +#define FMAX_LOWER 0 +#define FMAX_LOW 1 +#define FMAX_NOM 2 +#define FMAX_TURBO 3 + +#define HALT_CHECK_DELAY 5 + +#define RPM_MISC_CLK_TYPE 0x306b6c63 +#define RPM_BUS_CLK_TYPE 0x316b6c63 +#define RPM_MEM_CLK_TYPE 0x326b6c63 +#define RPM_IPA_CLK_TYPE 0x617069 +#define RPM_CE_CLK_TYPE 0x6563 +#define RPM_AGGR_CLK_TYPE 0x72676761 +#define RPM_SMD_KEY_ENABLE 0x62616E45 +#define RPM_MMAXI_CLK_TYPE 0x69786d6d + +#define CXO_CLK_SRC_ID 0x0 +#define QDSS_CLK_ID 0x1 +#define SNOC_CLK_ID 0x1 +#define CNOC_CLK_ID 0x2 +#define CNOC_PERIPH_CLK_ID 0x0 +#define BIMC_CLK_ID 0x0 +#define IPA_CLK_ID 0x0 +#define CE1_CLK_ID 0x0 +#define RF_CLK1_ID 0x4 +#define RF_CLK2_ID 0x5 +#define RF_CLK3_ID 0x6 +#define LN_BB_CLK1_ID 0x1 +#define LN_BB_CLK2_ID 0x2 +#define LN_BB_CLK3_ID 0x3 +#define DIV_CLK1_ID 0xb +#define DIV_CLK2_ID 0xc +#define DIV_CLK3_ID 0xd +#define RF_CLK1_PIN_ID 0x4 +#define RF_CLK2_PIN_ID 0x5 +#define RF_CLK3_PIN_ID 0x6 +#define LN_BB_CLK1_PIN_ID 0x1 +#define LN_BB_CLK2_PIN_ID 0x2 +#define LN_BB_CLK3_PIN_ID 0x3 +#define AGGR1_NOC_ID 0x1 +#define AGGR2_NOC_ID 0x2 +#define MMSSNOC_AXI_CLK_ID 0x0 + +#define APCS_COMMON_LMH_CMD_RCGR 0x0012C + +#define GCC_APCS_GPLL_ENA_VOTE 0x52000 +#define GCC_APCS_CLOCK_BRANCH_ENA_VOTE 0x52004 +#define GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1 0x5200C +#define PLLTEST_PAD_CFG 0x6200C +#define GCC_XO_DIV4_CBCR 0x43008 +#define CLOCK_FRQ_MEASURE_CTL 0x62004 +#define CLOCK_FRQ_MEASURE_STATUS 0x62008 +#define GCC_GPLL0_MODE 0x00000 +#define GCC_GPLL4_MODE 0x77000 +#define GCC_USB30_MASTER_CMD_RCGR 0x0F014 +#define GCC_PCIE_AUX_CMD_RCGR 0x6C000 +#define GCC_UFS_AXI_CMD_RCGR 0x75018 +#define GCC_BLSP1_QUP1_I2C_APPS_CMD_RCGR 0x19020 +#define GCC_BLSP1_QUP1_SPI_APPS_CMD_RCGR 0x1900C +#define GCC_BLSP1_QUP2_I2C_APPS_CMD_RCGR 0x1B020 +#define GCC_BLSP1_QUP2_SPI_APPS_CMD_RCGR 0x1B00C +#define GCC_BLSP1_QUP3_I2C_APPS_CMD_RCGR 0x1D020 +#define GCC_BLSP1_QUP3_SPI_APPS_CMD_RCGR 0x1D00C +#define GCC_BLSP1_QUP4_I2C_APPS_CMD_RCGR 0x1F020 +#define GCC_BLSP1_QUP4_SPI_APPS_CMD_RCGR 0x1F00C +#define GCC_BLSP1_QUP5_I2C_APPS_CMD_RCGR 0x21020 +#define GCC_BLSP1_QUP5_SPI_APPS_CMD_RCGR 0x2100C +#define GCC_BLSP1_QUP6_I2C_APPS_CMD_RCGR 0x23020 +#define GCC_BLSP1_QUP6_SPI_APPS_CMD_RCGR 0x2300C +#define GCC_BLSP1_UART1_APPS_CMD_RCGR 0x1A00C +#define GCC_BLSP1_UART2_APPS_CMD_RCGR 0x1C00C +#define GCC_BLSP1_UART3_APPS_CMD_RCGR 0x1E00C +#define GCC_BLSP2_QUP1_I2C_APPS_CMD_RCGR 0x26020 +#define GCC_BLSP2_QUP2_I2C_APPS_CMD_RCGR 0x28020 +#define GCC_BLSP2_QUP3_I2C_APPS_CMD_RCGR 0x2A020 +#define GCC_BLSP2_QUP4_I2C_APPS_CMD_RCGR 0x2C020 +#define GCC_BLSP2_QUP5_I2C_APPS_CMD_RCGR 0x2E020 +#define GCC_BLSP2_QUP6_I2C_APPS_CMD_RCGR 0x30020 +#define GCC_BLSP2_QUP1_SPI_APPS_CMD_RCGR 0x2600C +#define GCC_BLSP2_QUP2_SPI_APPS_CMD_RCGR 0x2800C +#define GCC_BLSP2_QUP3_SPI_APPS_CMD_RCGR 0x2A00C +#define GCC_BLSP2_QUP4_SPI_APPS_CMD_RCGR 0x2C00C +#define GCC_BLSP2_QUP5_SPI_APPS_CMD_RCGR 0x2E00C +#define GCC_BLSP2_QUP6_SPI_APPS_CMD_RCGR 0x3000C +#define GCC_BLSP2_UART1_APPS_CMD_RCGR 0x2700C +#define GCC_BLSP2_UART2_APPS_CMD_RCGR 0x2900C +#define GCC_BLSP2_UART3_APPS_CMD_RCGR 0x2B00C +#define GCC_GP1_CMD_RCGR 0x64004 +#define GCC_GP2_CMD_RCGR 0x65004 +#define GCC_GP3_CMD_RCGR 0x66004 +#define GCC_HMSS_RBCPR_CMD_RCGR 0x48044 +#define GCC_PDM2_CMD_RCGR 0x33010 +#define GCC_SDCC2_APPS_CMD_RCGR 0x14010 +#define GCC_SDCC4_APPS_CMD_RCGR 0x16010 +#define GCC_TSIF_REF_CMD_RCGR 0x36010 +#define GCC_UFS_ICE_CORE_CMD_RCGR 0x76010 +#define GCC_UFS_PHY_AUX_CMD_RCGR 0x76044 +#define GCC_UFS_UNIPRO_CORE_CMD_RCGR 0x76028 +#define GCC_USB30_MOCK_UTMI_CMD_RCGR 0x0F028 +#define GCC_USB3_PHY_AUX_CMD_RCGR 0x5000C +#define GCC_QSPI_REF_CMD_RCGR 0x9000C +#define GCC_PCIE_0_PHY_BCR 0x6C01C +#define GCC_HDMI_CLKREF_EN 0x88000 +#define GCC_UFS_CLKREF_EN 0x88004 +#define GCC_USB3_CLKREF_EN 0x88008 +#define GCC_PCIE_CLKREF_EN 0x8800C +#define GCC_RX1_USB2_CLKREF_EN 0x88014 +#define GCC_USB3_PHY_BCR 0x50020 +#define GCC_AGGRE1_NOC_XO_CBCR 0x8202C +#define GCC_AGGRE1_UFS_AXI_CBCR 0x82028 +#define GCC_AGGRE1_USB3_AXI_CBCR 0x82024 +#define GCC_BIMC_MSS_Q6_AXI_CBCR 0x4401C +#define GCC_BLSP1_AHB_CBCR 0x17004 +#define GCC_BLSP1_BCR 0x17000 +#define GCC_BLSP1_QUP1_SPI_APPS_CBCR 0x19004 +#define GCC_BLSP1_QUP1_I2C_APPS_CBCR 0x19008 +#define GCC_BLSP1_QUP2_SPI_APPS_CBCR 0x1B004 +#define GCC_BLSP1_QUP2_I2C_APPS_CBCR 0x1B008 +#define GCC_BLSP1_QUP3_SPI_APPS_CBCR 0x1D004 +#define GCC_BLSP1_QUP3_I2C_APPS_CBCR 0x1D008 +#define GCC_BLSP1_QUP4_SPI_APPS_CBCR 0x1F004 +#define GCC_BLSP1_QUP4_I2C_APPS_CBCR 0x1F008 +#define GCC_BLSP1_QUP5_SPI_APPS_CBCR 0x21004 +#define GCC_BLSP1_QUP5_I2C_APPS_CBCR 0x21008 +#define GCC_BLSP1_QUP6_SPI_APPS_CBCR 0x23004 +#define GCC_BLSP1_QUP6_I2C_APPS_CBCR 0x23008 +#define GCC_BLSP1_UART1_APPS_CBCR 0x1A004 +#define GCC_BLSP1_UART2_APPS_CBCR 0x1C004 +#define GCC_BLSP1_UART3_APPS_CBCR 0x1E004 +#define GCC_BLSP2_AHB_CBCR 0x25004 +#define GCC_BLSP2_BCR 0x25000 +#define GCC_BLSP2_QUP1_SPI_APPS_CBCR 0x26004 +#define GCC_BLSP2_QUP1_I2C_APPS_CBCR 0x26008 +#define GCC_BLSP2_QUP2_I2C_APPS_CBCR 0x28008 +#define GCC_BLSP2_QUP2_SPI_APPS_CBCR 0x28004 +#define GCC_BLSP2_QUP3_SPI_APPS_CBCR 0x2A004 +#define GCC_BLSP2_QUP3_I2C_APPS_CBCR 0x2A008 +#define GCC_BLSP2_QUP4_SPI_APPS_CBCR 0x2C004 +#define GCC_BLSP2_QUP4_I2C_APPS_CBCR 0x2C008 +#define GCC_BLSP2_QUP5_SPI_APPS_CBCR 0x2E004 +#define GCC_BLSP2_QUP5_I2C_APPS_CBCR 0x2E008 +#define GCC_BLSP2_QUP6_SPI_APPS_CBCR 0x30004 +#define GCC_BLSP2_QUP6_I2C_APPS_CBCR 0x30008 +#define GCC_BLSP2_UART1_APPS_CBCR 0x27004 +#define GCC_BLSP2_UART2_APPS_CBCR 0x29004 +#define GCC_BLSP2_UART3_APPS_CBCR 0x2B004 +#define GCC_BOOT_ROM_AHB_CBCR 0x38004 +#define GCC_BOOT_ROM_BCR 0x38000 +#define GCC_CFG_NOC_USB3_AXI_CBCR 0x05018 +#define GCC_BIMC_GFX_CBCR 0x46040 +#define GCC_GP1_CBCR 0x64000 +#define GCC_GP2_CBCR 0x65000 +#define GCC_GP3_CBCR 0x66000 +#define GCC_GPU_BIMC_GFX_CBCR 0x71010 +#define GCC_GPU_CFG_AHB_CBCR 0x71004 +#define GCC_GPU_IREF_EN 0x88010 +#define GCC_HMSS_DVM_BUS_CBCR 0x4808C +#define GCC_HMSS_RBCPR_CBCR 0x48008 +#define GCC_MMSS_SYS_NOC_AXI_CBCR 0x09000 +#define GCC_MMSS_NOC_CFG_AHB_CBCR 0x09004 +#define GCC_PCIE_0_SLV_AXI_CBCR 0x6B008 +#define GCC_PCIE_0_MSTR_AXI_CBCR 0x6B00C +#define GCC_PCIE_0_CFG_AHB_CBCR 0x6B010 +#define GCC_PCIE_0_AUX_CBCR 0x6B014 +#define GCC_PCIE_0_PIPE_CBCR 0x6B018 +#define GCC_PCIE_PHY_AUX_CBCR 0x6F004 +#define GCC_PCIE_PHY_BCR 0x6F000 +#define GCC_PCIE_PHY_COM_BCR 0x6F014 +#define GCC_PCIE_PHY_NOCSR_COM_PHY_BCR 0x6F00C +#define GCC_QUSB2PHY_PRIM_BCR 0x12000 +#define GCC_QUSB2PHY_SEC_BCR 0x12004 +#define GCC_PDM2_CBCR 0x3300C +#define GCC_PDM_AHB_CBCR 0x33004 +#define GCC_PRNG_AHB_CBCR 0x34004 +#define GCC_PRNG_BCR 0x34000 +#define GCC_SDCC2_APPS_CBCR 0x14004 +#define GCC_SDCC2_AHB_CBCR 0x14008 +#define GCC_SDCC4_APPS_CBCR 0x16004 +#define GCC_SDCC4_AHB_CBCR 0x16008 +#define GCC_TSIF_AHB_CBCR 0x36004 +#define GCC_TSIF_REF_CBCR 0x36008 +#define GCC_UFS_AXI_CBCR 0x75008 +#define GCC_UFS_BCR 0x75000 +#define GCC_UFS_AHB_CBCR 0x7500C +#define GCC_UFS_TX_SYMBOL_0_CBCR 0x75010 +#define GCC_UFS_RX_SYMBOL_0_CBCR 0x75014 +#define GCC_UFS_RX_SYMBOL_1_CBCR 0x7605C +#define GCC_UFS_UNIPRO_CORE_CBCR 0x76008 +#define GCC_UFS_ICE_CORE_CBCR 0x7600C +#define GCC_UFS_PHY_AUX_CBCR 0x76040 +#define GCC_USB30_MASTER_CBCR 0x0F008 +#define GCC_USB30_SLEEP_CBCR 0x0F00C +#define GCC_USB30_MOCK_UTMI_CBCR 0x0F010 +#define GCC_USB_30_BCR 0x0F000 +#define GCC_USB3_PHY_AUX_CBCR 0x50000 +#define GCC_USB3_PHY_PIPE_CBCR 0x50004 +#define GCC_USB3PHY_PHY_BCR 0x50024 +#define GCC_APCS_CLOCK_SLEEP_ENA_VOTE 0x52008 +#define GCC_MSS_CFG_AHB_CBCR 0x8A000 +#define GCC_MSS_Q6_BIMC_AXI_CBCR 0x8A040 +#define GCC_MSS_MNOC_BIMC_AXI_CBCR 0x8A004 +#define GCC_MSS_SNOC_AXI_CBCR 0x8A03C +#define GCC_HMSS_GPLL0_CMD_RCGR 0x4805C +#define GCC_MSS_CFG_AHB_CBCR 0x8A000 +#define GCC_MSS_Q6_BIMC_AXI_CBCR 0x8A040 +#define GCC_MSS_MNOC_BIMC_AXI_CBCR 0x8A004 +#define GCC_MSS_SNOC_AXI_CBCR 0x8A03C +#define GCC_DCC_AHB_CBCR 0x84004 +#define GCC_HLOS1_VOTE_LPASS_CORE_SMMU_CBCR 0x7D010 +#define GCC_HLOS1_VOTE_LPASS_ADSP_SMMU_CBCR 0x7D014 +#define GCC_QSPI_AHB_CBCR 0x90004 +#define GCC_QSPI_REF_CBCR 0x90008 +#define GCC_MMSS_MISC 0x0902C +#define GCC_GPU_MISC 0x71028 + +#define GPUCC_GPU_PLL0_PLL_MODE 0x00000 +#define GPUCC_GPU_PLL0_USER_CTL_MODE 0x0000C +#define GPUCC_GFX3D_CMD_RCGR 0x01070 +#define GPUCC_RBBMTIMER_CMD_RCGR 0x010B0 +#define GPUCC_GFX3D_ISENSE_CMD_RCGR 0x01100 +#define GPUCC_RBCPR_CMD_RCGR 0x01030 +#define GPUCC_GFX3D_CBCR 0x01098 +#define GPUCC_RBBMTIMER_CBCR 0x010D0 +#define GPUCC_GFX3D_ISENSE_CBCR 0x01124 +#define GPUCC_CXO_CBCR 0x01020 +#define GPUCC_RBCPR_CBCR 0x01054 +#define GPU_GX_BCR 0x01090 +#define GPUCC_GX_DOMAIN_MISC 0x00130 +#define GPUCC_GPU_DD_WRAP_CTRL 0x00430 +#define GPUCC_DEBUG_CLK_CTL 0x00120 + +#define MMSS_PLL_VOTE_APCS 0x001E0 +#define MMSS_MMPLL0_PLL_MODE 0x0C000 +#define MMSS_MMPLL1_PLL_MODE 0x0C050 +#define MMSS_MMPLL3_PLL_MODE 0x00000 +#define MMSS_MMPLL4_PLL_MODE 0x00050 +#define MMSS_MMPLL5_PLL_MODE 0x000A0 +#define MMSS_MMPLL6_PLL_MODE 0x000F0 +#define MMSS_MMPLL7_PLL_MODE 0x00140 +#define MMSS_MMPLL10_PLL_MODE 0x00190 +#define MMSS_AHB_CMD_RCGR 0x05000 +#define MMSS_CSI0_CMD_RCGR 0x03090 +#define MMSS_VFE0_CMD_RCGR 0x03600 +#define MMSS_VFE1_CMD_RCGR 0x03620 +#define MMSS_MDP_CMD_RCGR 0x02040 +#define MMSS_MAXI_CMD_RCGR 0x0F020 +#define MMSS_CPP_CMD_RCGR 0x03640 +#define MMSS_JPEG0_CMD_RCGR 0x03500 +#define MMSS_ROT_CMD_RCGR 0x021A0 +#define MMSS_VIDEO_CORE_CMD_RCGR 0x01000 +#define MMSS_CSI1_CMD_RCGR 0x03100 +#define MMSS_CSI2_CMD_RCGR 0x03160 +#define MMSS_CSI3_CMD_RCGR 0x031C0 +#define MMSS_FD_CORE_CMD_RCGR 0x03B00 +#define MMSS_BYTE0_CMD_RCGR 0x02120 +#define MMSS_BYTE1_CMD_RCGR 0x02140 +#define MMSS_PCLK0_CMD_RCGR 0x02000 +#define MMSS_PCLK1_CMD_RCGR 0x02020 +#define MMSS_VIDEO_SUBCORE0_CMD_RCGR 0x01060 +#define MMSS_VIDEO_SUBCORE1_CMD_RCGR 0x01080 +#define MMSS_CSIPHY_CMD_RCGR 0x03800 +#define MMSS_CCI_CMD_RCGR 0x03300 +#define MMSS_CAMSS_GP0_CMD_RCGR 0x03420 +#define MMSS_CAMSS_GP1_CMD_RCGR 0x03450 +#define MMSS_MCLK0_CMD_RCGR 0x03360 +#define MMSS_MCLK1_CMD_RCGR 0x03390 +#define MMSS_MCLK2_CMD_RCGR 0x033C0 +#define MMSS_MCLK3_CMD_RCGR 0x033F0 +#define MMSS_CAMSS_CSI2PHYTIMER_CBCR 0x03084 +#define MMSS_CSI0PHYTIMER_CMD_RCGR 0x03000 +#define MMSS_CSI1PHYTIMER_CMD_RCGR 0x03030 +#define MMSS_CSI2PHYTIMER_CMD_RCGR 0x03060 +#define MMSS_DP_GTC_CMD_RCGR 0x02280 +#define MMSS_ESC0_CMD_RCGR 0x02160 +#define MMSS_ESC1_CMD_RCGR 0x02180 +#define MMSS_EXTPCLK_CMD_RCGR 0x02060 +#define MMSS_HDMI_CMD_RCGR 0x02100 +#define MMSS_VSYNC_CMD_RCGR 0x02080 +#define MMSS_BIMC_SMMU_AHB_CBCR 0x0E004 +#define MMSS_BIMC_SMMU_AXI_CBCR 0x0E008 +#define MMSS_SNOC_DVM_AXI_CBCR 0x0E040 +#define MMSS_CAMSS_AHB_CBCR 0x0348C +#define MMSS_CAMSS_CCI_AHB_CBCR 0x03348 +#define MMSS_CAMSS_CCI_CBCR 0x03344 +#define MMSS_CAMSS_CPP_AHB_CBCR 0x036B4 +#define MMSS_CAMSS_CPP_CBCR 0x036B0 +#define MMSS_CAMSS_CPP_AXI_CBCR 0x036C4 +#define MMSS_CAMSS_CPP_VBIF_AHB_CBCR 0x036C8 +#define MMSS_CAMSS_CPHY_CSID0_CBCR 0x03730 +#define MMSS_CAMSS_CSI0_AHB_CBCR 0x030BC +#define MMSS_CAMSS_CSI0_CBCR 0x030B4 +#define MMSS_CAMSS_CSI0PIX_CBCR 0x030E4 +#define MMSS_CAMSS_CSI0RDI_CBCR 0x030D4 +#define MMSS_CAMSS_CPHY_CSID1_CBCR 0x03734 +#define MMSS_CAMSS_CSI1_AHB_CBCR 0x03128 +#define MMSS_CAMSS_CSI1_CBCR 0x03124 +#define MMSS_CAMSS_CSI1PIX_CBCR 0x03154 +#define MMSS_CAMSS_CSI1RDI_CBCR 0x03144 +#define MMSS_CAMSS_CPHY_CSID2_CBCR 0x03738 +#define MMSS_CAMSS_CSI2_AHB_CBCR 0x03188 +#define MMSS_CAMSS_CSI2_CBCR 0x03184 +#define MMSS_CAMSS_CSI2PIX_CBCR 0x031B4 +#define MMSS_CAMSS_CSI2RDI_CBCR 0x031A4 +#define MMSS_CAMSS_CPHY_CSID3_CBCR 0x0373C +#define MMSS_CAMSS_CSI3_AHB_CBCR 0x031E8 +#define MMSS_CAMSS_CSI3_CBCR 0x031E4 +#define MMSS_CAMSS_CSI3PIX_CBCR 0x03214 +#define MMSS_CAMSS_CSI3RDI_CBCR 0x03204 +#define MMSS_CAMSS_CSI_VFE0_CBCR 0x03704 +#define MMSS_CAMSS_CSI_VFE1_CBCR 0x03714 +#define MMSS_CAMSS_CSIPHY0_CBCR 0x03740 +#define MMSS_CAMSS_CSIPHY1_CBCR 0x03744 +#define MMSS_CAMSS_CSIPHY2_CBCR 0x03748 +#define MMSS_FD_AHB_CBCR 0x03B74 +#define MMSS_FD_CORE_CBCR 0x03B68 +#define MMSS_FD_CORE_UAR_CBCR 0x03B6C +#define MMSS_CAMSS_GP0_CBCR 0x03444 +#define MMSS_CAMSS_GP1_CBCR 0x03474 +#define MMSS_CAMSS_ISPIF_AHB_CBCR 0x03224 +#define MMSS_CAMSS_JPEG0_CBCR 0x035A8 +#define MMSS_CAMSS_JPEG_AHB_CBCR 0x035B4 +#define MMSS_CAMSS_JPEG_AXI_CBCR 0x035B8 +#define MMSS_CAMSS_MCLK0_CBCR 0x03384 +#define MMSS_CAMSS_MCLK1_CBCR 0x033B4 +#define MMSS_CAMSS_MCLK2_CBCR 0x033E4 +#define MMSS_CAMSS_MCLK3_CBCR 0x03414 +#define MMSS_CAMSS_MICRO_AHB_CBCR 0x03494 +#define MMSS_CAMSS_CSI0PHYTIMER_CBCR 0x03024 +#define MMSS_CAMSS_CSI1PHYTIMER_CBCR 0x03054 +#define MMSS_CSI2PHYTIMER_CMD_RCGR 0x03060 +#define MMSS_CAMSS_TOP_AHB_CBCR 0x03484 +#define MMSS_CAMSS_VFE0_AHB_CBCR 0x03668 +#define MMSS_CAMSS_VFE0_CBCR 0x036A8 +#define MMSS_CAMSS_VFE0_STREAM_CBCR 0x03720 +#define MMSS_CAMSS_VFE1_AHB_CBCR 0x03678 +#define MMSS_CAMSS_VFE1_CBCR 0x036AC +#define MMSS_CAMSS_VFE1_STREAM_CBCR 0x03724 +#define MMSS_CAMSS_VFE_VBIF_AHB_CBCR 0x036B8 +#define MMSS_CAMSS_VFE_VBIF_AXI_CBCR 0x036BC +#define MMSS_MDSS_AHB_CBCR 0x02308 +#define MMSS_MDSS_AXI_CBCR 0x02310 +#define MMSS_MDSS_BYTE0_CBCR 0x0233C +#define MMSS_MDSS_BYTE0_INTF_CBCR 0x02374 +#define MMSS_MDSS_BYTE0_INTF_DIV 0x0237C +#define MMSS_MDSS_BYTE1_CBCR 0x02340 +#define MMSS_MDSS_BYTE1_INTF_CBCR 0x02378 +#define MMSS_MDSS_BYTE1_INTF_DIV 0x02380 +#define MMSS_MDSS_DP_AUX_CBCR 0x02364 +#define MMSS_MDSS_DP_CRYPTO_CBCR 0x0235C +#define MMSS_MDSS_DP_GTC_CBCR 0x02368 +#define MMSS_MDSS_DP_LINK_CBCR 0x02354 +#define MMSS_MDSS_DP_LINK_INTF_CBCR 0x02358 +#define MMSS_MDSS_DP_PIXEL_CBCR 0x02360 +#define MMSS_MDSS_ESC0_CBCR 0x02344 +#define MMSS_MDSS_ESC1_CBCR 0x02348 +#define MMSS_MDSS_EXTPCLK_CBCR 0x02324 +#define MMSS_MDSS_HDMI_CBCR 0x02338 +#define MMSS_MDSS_HDMI_DP_AHB_CBCR 0x0230C +#define MMSS_MDSS_MDP_CBCR 0x0231C +#define MMSS_MDSS_MDP_LUT_CBCR 0x02320 +#define MMSS_MDSS_PCLK0_CBCR 0x02314 +#define MMSS_MDSS_PCLK1_CBCR 0x02318 +#define MMSS_MDSS_ROT_CBCR 0x02350 +#define MMSS_MDSS_VSYNC_CBCR 0x02328 +#define MMSS_MISC_AHB_CBCR 0x00328 +#define MMSS_MISC_CXO_CBCR 0x00324 +#define MMSS_MNOC_AHB_CBCR 0x05024 +#define MMSS_MNOC_MAXI_CBCR 0x0F004 +#define MMSS_VIDEO_SUBCORE0_CBCR 0x01048 +#define MMSS_VIDEO_SUBCORE1_CBCR 0x0104C +#define MMSS_VIDEO_AHB_CBCR 0x01030 +#define MMSS_VIDEO_AXI_CBCR 0x01034 +#define MMSS_VIDEO_CORE_CBCR 0x01028 +#define MMSS_VIDEO_MAXI_CBCR 0x01038 +#define MMSS_VMEM_AHB_CBCR 0x0F068 +#define MMSS_VMEM_MAXI_CBCR 0x0F064 +#define MMSS_DP_AUX_CMD_RCGR 0x02260 +#define MMSS_DP_CRYPTO_CMD_RCGR 0x02220 +#define MMSS_DP_LINK_CMD_RCGR 0x02200 +#define MMSS_DP_PIXEL_CMD_RCGR 0x02240 +#define MMSS_DEBUG_CLK_CTL 0x00900 diff -Nruw linux-4.4.115-fbx/arch/mips/boot/dts/include/dt-bindings/msm./msm-bus-ids.h linux-4.4.115-fbx/arch/mips/boot/dts/include/dt-bindings/msm/msm-bus-ids.h --- linux-4.4.115-fbx/arch/mips/boot/dts/include/dt-bindings/msm./msm-bus-ids.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-4.4.115-fbx/arch/mips/boot/dts/include/dt-bindings/msm/msm-bus-ids.h 2019-01-22 16:16:28.179288750 +0100 @@ -0,0 +1,887 @@ +/* Copyright (c) 2014-2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __MSM_BUS_IDS_H +#define __MSM_BUS_IDS_H + +/* Aggregation types */ +#define AGG_SCHEME_NONE 0 +#define AGG_SCHEME_LEG 1 +#define AGG_SCHEME_1 2 + +/* Topology related enums */ +#define MSM_BUS_FAB_DEFAULT 0 +#define MSM_BUS_FAB_APPSS 0 +#define MSM_BUS_FAB_SYSTEM 1024 +#define MSM_BUS_FAB_MMSS 2048 +#define MSM_BUS_FAB_SYSTEM_FPB 3072 +#define MSM_BUS_FAB_CPSS_FPB 4096 + +#define MSM_BUS_FAB_BIMC 0 +#define MSM_BUS_FAB_SYS_NOC 1024 +#define MSM_BUS_FAB_MMSS_NOC 2048 +#define MSM_BUS_FAB_OCMEM_NOC 3072 +#define MSM_BUS_FAB_PERIPH_NOC 4096 +#define MSM_BUS_FAB_CONFIG_NOC 5120 +#define MSM_BUS_FAB_OCMEM_VNOC 6144 +#define MSM_BUS_FAB_MMSS_AHB 2049 +#define MSM_BUS_FAB_A0_NOC 6145 +#define MSM_BUS_FAB_A1_NOC 6146 +#define MSM_BUS_FAB_A2_NOC 6147 +#define MSM_BUS_FAB_GNOC 6148 +#define MSM_BUS_FAB_CR_VIRT 6149 + +#define MSM_BUS_MASTER_FIRST 1 +#define MSM_BUS_MASTER_AMPSS_M0 1 +#define MSM_BUS_MASTER_AMPSS_M1 2 +#define MSM_BUS_APPSS_MASTER_FAB_MMSS 3 +#define MSM_BUS_APPSS_MASTER_FAB_SYSTEM 4 +#define MSM_BUS_SYSTEM_MASTER_FAB_APPSS 5 +#define MSM_BUS_MASTER_SPS 6 +#define MSM_BUS_MASTER_ADM_PORT0 7 +#define MSM_BUS_MASTER_ADM_PORT1 8 +#define MSM_BUS_SYSTEM_MASTER_ADM1_PORT0 9 +#define MSM_BUS_MASTER_ADM1_PORT1 10 +#define MSM_BUS_MASTER_LPASS_PROC 11 +#define MSM_BUS_MASTER_MSS_PROCI 12 +#define MSM_BUS_MASTER_MSS_PROCD 13 +#define MSM_BUS_MASTER_MSS_MDM_PORT0 14 +#define MSM_BUS_MASTER_LPASS 15 +#define MSM_BUS_SYSTEM_MASTER_CPSS_FPB 16 +#define MSM_BUS_SYSTEM_MASTER_SYSTEM_FPB 17 +#define MSM_BUS_SYSTEM_MASTER_MMSS_FPB 18 +#define MSM_BUS_MASTER_ADM1_CI 19 +#define MSM_BUS_MASTER_ADM0_CI 20 +#define MSM_BUS_MASTER_MSS_MDM_PORT1 21 +#define MSM_BUS_MASTER_MDP_PORT0 22 +#define MSM_BUS_MASTER_MDP_PORT1 23 +#define MSM_BUS_MMSS_MASTER_ADM1_PORT0 24 +#define MSM_BUS_MASTER_ROTATOR 25 +#define MSM_BUS_MASTER_GRAPHICS_3D 26 +#define MSM_BUS_MASTER_JPEG_DEC 27 +#define MSM_BUS_MASTER_GRAPHICS_2D_CORE0 28 +#define MSM_BUS_MASTER_VFE 29 +#define MSM_BUS_MASTER_VFE0 MSM_BUS_MASTER_VFE +#define MSM_BUS_MASTER_VPE 30 +#define MSM_BUS_MASTER_JPEG_ENC 31 +#define MSM_BUS_MASTER_GRAPHICS_2D_CORE1 32 +#define MSM_BUS_MMSS_MASTER_APPS_FAB 33 +#define MSM_BUS_MASTER_HD_CODEC_PORT0 34 +#define MSM_BUS_MASTER_HD_CODEC_PORT1 35 +#define MSM_BUS_MASTER_SPDM 36 +#define MSM_BUS_MASTER_RPM 37 +#define MSM_BUS_MASTER_MSS 38 +#define MSM_BUS_MASTER_RIVA 39 +#define MSM_BUS_MASTER_SNOC_VMEM 40 +#define MSM_BUS_MASTER_MSS_SW_PROC 41 +#define MSM_BUS_MASTER_MSS_FW_PROC 42 +#define MSM_BUS_MASTER_HMSS 43 +#define MSM_BUS_MASTER_GSS_NAV 44 +#define MSM_BUS_MASTER_PCIE 45 +#define MSM_BUS_MASTER_SATA 46 +#define MSM_BUS_MASTER_CRYPTO 47 +#define MSM_BUS_MASTER_VIDEO_CAP 48 +#define MSM_BUS_MASTER_GRAPHICS_3D_PORT1 49 +#define MSM_BUS_MASTER_VIDEO_ENC 50 +#define MSM_BUS_MASTER_VIDEO_DEC 51 +#define MSM_BUS_MASTER_LPASS_AHB 52 +#define MSM_BUS_MASTER_QDSS_BAM 53 +#define MSM_BUS_MASTER_SNOC_CFG 54 +#define MSM_BUS_MASTER_CRYPTO_CORE0 55 +#define MSM_BUS_MASTER_CRYPTO_CORE1 56 +#define MSM_BUS_MASTER_MSS_NAV 57 +#define MSM_BUS_MASTER_OCMEM_DMA 58 +#define MSM_BUS_MASTER_WCSS 59 +#define MSM_BUS_MASTER_QDSS_ETR 60 +#define MSM_BUS_MASTER_USB3 61 +#define MSM_BUS_MASTER_JPEG 62 +#define MSM_BUS_MASTER_VIDEO_P0 63 +#define MSM_BUS_MASTER_VIDEO_P1 64 +#define MSM_BUS_MASTER_MSS_PROC 65 +#define MSM_BUS_MASTER_JPEG_OCMEM 66 +#define MSM_BUS_MASTER_MDP_OCMEM 67 +#define MSM_BUS_MASTER_VIDEO_P0_OCMEM 68 +#define MSM_BUS_MASTER_VIDEO_P1_OCMEM 69 +#define MSM_BUS_MASTER_VFE_OCMEM 70 +#define MSM_BUS_MASTER_CNOC_ONOC_CFG 71 +#define MSM_BUS_MASTER_RPM_INST 72 +#define MSM_BUS_MASTER_RPM_DATA 73 +#define MSM_BUS_MASTER_RPM_SYS 74 +#define MSM_BUS_MASTER_DEHR 75 +#define MSM_BUS_MASTER_QDSS_DAP 76 +#define MSM_BUS_MASTER_TIC 77 +#define MSM_BUS_MASTER_SDCC_1 78 +#define MSM_BUS_MASTER_SDCC_3 79 +#define MSM_BUS_MASTER_SDCC_4 80 +#define MSM_BUS_MASTER_SDCC_2 81 +#define MSM_BUS_MASTER_TSIF 82 +#define MSM_BUS_MASTER_BAM_DMA 83 +#define MSM_BUS_MASTER_BLSP_2 84 +#define MSM_BUS_MASTER_USB_HSIC 85 +#define MSM_BUS_MASTER_BLSP_1 86 +#define MSM_BUS_MASTER_USB_HS 87 +#define MSM_BUS_MASTER_PNOC_CFG 88 +#define MSM_BUS_MASTER_V_OCMEM_GFX3D 89 +#define MSM_BUS_MASTER_IPA 90 +#define MSM_BUS_MASTER_QPIC 91 +#define MSM_BUS_MASTER_MDPE 92 +#define MSM_BUS_MASTER_USB_HS2 93 +#define MSM_BUS_MASTER_VPU 94 +#define MSM_BUS_MASTER_UFS 95 +#define MSM_BUS_MASTER_BCAST 96 +#define MSM_BUS_MASTER_CRYPTO_CORE2 97 +#define MSM_BUS_MASTER_EMAC 98 +#define MSM_BUS_MASTER_VPU_1 99 +#define MSM_BUS_MASTER_PCIE_1 100 +#define MSM_BUS_MASTER_USB3_1 101 +#define MSM_BUS_MASTER_CNOC_MNOC_MMSS_CFG 102 +#define MSM_BUS_MASTER_CNOC_MNOC_CFG 103 +#define MSM_BUS_MASTER_TCU_0 104 +#define MSM_BUS_MASTER_TCU_1 105 +#define MSM_BUS_MASTER_CPP 106 +#define MSM_BUS_MASTER_AUDIO 107 +#define MSM_BUS_MASTER_PCIE_2 108 +#define MSM_BUS_MASTER_VFE1 109 +#define MSM_BUS_MASTER_XM_USB_HS1 110 +#define MSM_BUS_MASTER_PCNOC_BIMC_1 111 +#define MSM_BUS_MASTER_BIMC_PCNOC 112 +#define MSM_BUS_MASTER_XI_USB_HSIC 113 +#define MSM_BUS_MASTER_SGMII 114 +#define MSM_BUS_SPMI_FETCHER 115 +#define MSM_BUS_MASTER_GNOC_BIMC 116 +#define MSM_BUS_MASTER_CRVIRT_A2NOC 117 +#define MSM_BUS_MASTER_CNOC_A2NOC 118 +#define MSM_BUS_MASTER_WLAN 119 +#define MSM_BUS_MASTER_MSS_CE 120 +#define MSM_BUS_MASTER_CDSP_PROC 121 +#define MSM_BUS_MASTER_GNOC_SNOC 122 +#define MSM_BUS_MASTER_PIMEM 123 +#define MSM_BUS_MASTER_MASTER_LAST 124 + +#define MSM_BUS_SYSTEM_FPB_MASTER_SYSTEM MSM_BUS_SYSTEM_MASTER_SYSTEM_FPB +#define MSM_BUS_CPSS_FPB_MASTER_SYSTEM MSM_BUS_SYSTEM_MASTER_CPSS_FPB + +#define MSM_BUS_SNOC_MM_INT_0 10000 +#define MSM_BUS_SNOC_MM_INT_1 10001 +#define MSM_BUS_SNOC_MM_INT_2 10002 +#define MSM_BUS_SNOC_MM_INT_BIMC 10003 +#define MSM_BUS_SNOC_INT_0 10004 +#define MSM_BUS_SNOC_INT_1 10005 +#define MSM_BUS_SNOC_INT_BIMC 10006 +#define MSM_BUS_SNOC_BIMC_0_MAS 10007 +#define MSM_BUS_SNOC_BIMC_1_MAS 10008 +#define MSM_BUS_SNOC_QDSS_INT 10009 +#define MSM_BUS_PNOC_SNOC_MAS 10010 +#define MSM_BUS_PNOC_SNOC_SLV 10011 +#define MSM_BUS_PNOC_INT_0 10012 +#define MSM_BUS_PNOC_INT_1 10013 +#define MSM_BUS_PNOC_M_0 10014 +#define MSM_BUS_PNOC_M_1 10015 +#define MSM_BUS_BIMC_SNOC_MAS 10016 +#define MSM_BUS_BIMC_SNOC_SLV 10017 +#define MSM_BUS_PNOC_SLV_0 10018 +#define MSM_BUS_PNOC_SLV_1 10019 +#define MSM_BUS_PNOC_SLV_2 10020 +#define MSM_BUS_PNOC_SLV_3 10021 +#define MSM_BUS_PNOC_SLV_4 10022 +#define MSM_BUS_PNOC_SLV_8 10023 +#define MSM_BUS_PNOC_SLV_9 10024 +#define MSM_BUS_SNOC_BIMC_0_SLV 10025 +#define MSM_BUS_SNOC_BIMC_1_SLV 10026 +#define MSM_BUS_MNOC_BIMC_MAS 10027 +#define MSM_BUS_MNOC_BIMC_SLV 10028 +#define MSM_BUS_BIMC_MNOC_MAS 10029 +#define MSM_BUS_BIMC_MNOC_SLV 10030 +#define MSM_BUS_SNOC_BIMC_MAS 10031 +#define MSM_BUS_SNOC_BIMC_SLV 10032 +#define MSM_BUS_CNOC_SNOC_MAS 10033 +#define MSM_BUS_CNOC_SNOC_SLV 10034 +#define MSM_BUS_SNOC_CNOC_MAS 10035 +#define MSM_BUS_SNOC_CNOC_SLV 10036 +#define MSM_BUS_OVNOC_SNOC_MAS 10037 +#define MSM_BUS_OVNOC_SNOC_SLV 10038 +#define MSM_BUS_SNOC_OVNOC_MAS 10039 +#define MSM_BUS_SNOC_OVNOC_SLV 10040 +#define MSM_BUS_SNOC_PNOC_MAS 10041 +#define MSM_BUS_SNOC_PNOC_SLV 10042 +#define MSM_BUS_BIMC_INT_APPS_EBI 10043 +#define MSM_BUS_BIMC_INT_APPS_SNOC 10044 +#define MSM_BUS_SNOC_BIMC_2_MAS 10045 +#define MSM_BUS_SNOC_BIMC_2_SLV 10046 +#define MSM_BUS_PNOC_SLV_5 10047 +#define MSM_BUS_PNOC_SLV_7 10048 +#define MSM_BUS_PNOC_INT_2 10049 +#define MSM_BUS_PNOC_INT_3 10050 +#define MSM_BUS_PNOC_INT_4 10051 +#define MSM_BUS_PNOC_INT_5 10052 +#define MSM_BUS_PNOC_INT_6 10053 +#define MSM_BUS_PNOC_INT_7 10054 +#define MSM_BUS_BIMC_SNOC_1_MAS 10055 +#define MSM_BUS_BIMC_SNOC_1_SLV 10056 +#define MSM_BUS_PNOC_A1NOC_MAS 10057 +#define MSM_BUS_PNOC_A1NOC_SLV 10058 +#define MSM_BUS_CNOC_A1NOC_MAS 10059 +#define MSM_BUS_A0NOC_SNOC_MAS 10060 +#define MSM_BUS_A0NOC_SNOC_SLV 10061 +#define MSM_BUS_A1NOC_SNOC_SLV 10062 +#define MSM_BUS_A1NOC_SNOC_MAS 10063 +#define MSM_BUS_A2NOC_SNOC_MAS 10064 +#define MSM_BUS_A2NOC_SNOC_SLV 10065 +#define MSM_BUS_SNOC_INT_2 10066 +#define MSM_BUS_A0NOC_QDSS_INT 10067 +#define MSM_BUS_INT_LAST 10068 + +#define MSM_BUS_INT_TEST_ID 20000 +#define MSM_BUS_INT_TEST_LAST 20050 + +#define MSM_BUS_SLAVE_FIRST 512 +#define MSM_BUS_SLAVE_EBI_CH0 512 +#define MSM_BUS_SLAVE_EBI_CH1 513 +#define MSM_BUS_SLAVE_AMPSS_L2 514 +#define MSM_BUS_APPSS_SLAVE_FAB_MMSS 515 +#define MSM_BUS_APPSS_SLAVE_FAB_SYSTEM 516 +#define MSM_BUS_SYSTEM_SLAVE_FAB_APPS 517 +#define MSM_BUS_SLAVE_SPS 518 +#define MSM_BUS_SLAVE_SYSTEM_IMEM 519 +#define MSM_BUS_SLAVE_AMPSS 520 +#define MSM_BUS_SLAVE_MSS 521 +#define MSM_BUS_SLAVE_LPASS 522 +#define MSM_BUS_SYSTEM_SLAVE_CPSS_FPB 523 +#define MSM_BUS_SYSTEM_SLAVE_SYSTEM_FPB 524 +#define MSM_BUS_SYSTEM_SLAVE_MMSS_FPB 525 +#define MSM_BUS_SLAVE_CORESIGHT 526 +#define MSM_BUS_SLAVE_RIVA 527 +#define MSM_BUS_SLAVE_SMI 528 +#define MSM_BUS_MMSS_SLAVE_FAB_APPS 529 +#define MSM_BUS_MMSS_SLAVE_FAB_APPS_1 530 +#define MSM_BUS_SLAVE_MM_IMEM 531 +#define MSM_BUS_SLAVE_CRYPTO 532 +#define MSM_BUS_SLAVE_SPDM 533 +#define MSM_BUS_SLAVE_RPM 534 +#define MSM_BUS_SLAVE_RPM_MSG_RAM 535 +#define MSM_BUS_SLAVE_MPM 536 +#define MSM_BUS_SLAVE_PMIC1_SSBI1_A 537 +#define MSM_BUS_SLAVE_PMIC1_SSBI1_B 538 +#define MSM_BUS_SLAVE_PMIC1_SSBI1_C 539 +#define MSM_BUS_SLAVE_PMIC2_SSBI2_A 540 +#define MSM_BUS_SLAVE_PMIC2_SSBI2_B 541 +#define MSM_BUS_SLAVE_GSBI1_UART 542 +#define MSM_BUS_SLAVE_GSBI2_UART 543 +#define MSM_BUS_SLAVE_GSBI3_UART 544 +#define MSM_BUS_SLAVE_GSBI4_UART 545 +#define MSM_BUS_SLAVE_GSBI5_UART 546 +#define MSM_BUS_SLAVE_GSBI6_UART 547 +#define MSM_BUS_SLAVE_GSBI7_UART 548 +#define MSM_BUS_SLAVE_GSBI8_UART 549 +#define MSM_BUS_SLAVE_GSBI9_UART 550 +#define MSM_BUS_SLAVE_GSBI10_UART 551 +#define MSM_BUS_SLAVE_GSBI11_UART 552 +#define MSM_BUS_SLAVE_GSBI12_UART 553 +#define MSM_BUS_SLAVE_GSBI1_QUP 554 +#define MSM_BUS_SLAVE_GSBI2_QUP 555 +#define MSM_BUS_SLAVE_GSBI3_QUP 556 +#define MSM_BUS_SLAVE_GSBI4_QUP 557 +#define MSM_BUS_SLAVE_GSBI5_QUP 558 +#define MSM_BUS_SLAVE_GSBI6_QUP 559 +#define MSM_BUS_SLAVE_GSBI7_QUP 560 +#define MSM_BUS_SLAVE_GSBI8_QUP 561 +#define MSM_BUS_SLAVE_GSBI9_QUP 562 +#define MSM_BUS_SLAVE_GSBI10_QUP 563 +#define MSM_BUS_SLAVE_GSBI11_QUP 564 +#define MSM_BUS_SLAVE_GSBI12_QUP 565 +#define MSM_BUS_SLAVE_EBI2_NAND 566 +#define MSM_BUS_SLAVE_EBI2_CS0 567 +#define MSM_BUS_SLAVE_EBI2_CS1 568 +#define MSM_BUS_SLAVE_EBI2_CS2 569 +#define MSM_BUS_SLAVE_EBI2_CS3 570 +#define MSM_BUS_SLAVE_EBI2_CS4 571 +#define MSM_BUS_SLAVE_EBI2_CS5 572 +#define MSM_BUS_SLAVE_USB_FS1 573 +#define MSM_BUS_SLAVE_USB_FS2 574 +#define MSM_BUS_SLAVE_TSIF 575 +#define MSM_BUS_SLAVE_MSM_TSSC 576 +#define MSM_BUS_SLAVE_MSM_PDM 577 +#define MSM_BUS_SLAVE_MSM_DIMEM 578 +#define MSM_BUS_SLAVE_MSM_TCSR 579 +#define MSM_BUS_SLAVE_MSM_PRNG 580 +#define MSM_BUS_SLAVE_GSS 581 +#define MSM_BUS_SLAVE_SATA 582 +#define MSM_BUS_SLAVE_USB3 583 +#define MSM_BUS_SLAVE_WCSS 584 +#define MSM_BUS_SLAVE_OCIMEM 585 +#define MSM_BUS_SLAVE_SNOC_OCMEM 586 +#define MSM_BUS_SLAVE_SERVICE_SNOC 587 +#define MSM_BUS_SLAVE_QDSS_STM 588 +#define MSM_BUS_SLAVE_CAMERA_CFG 589 +#define MSM_BUS_SLAVE_DISPLAY_CFG 590 +#define MSM_BUS_SLAVE_OCMEM_CFG 591 +#define MSM_BUS_SLAVE_CPR_CFG 592 +#define MSM_BUS_SLAVE_CPR_XPU_CFG 593 +#define MSM_BUS_SLAVE_MISC_CFG 594 +#define MSM_BUS_SLAVE_MISC_XPU_CFG 595 +#define MSM_BUS_SLAVE_VENUS_CFG 596 +#define MSM_BUS_SLAVE_MISC_VENUS_CFG 597 +#define MSM_BUS_SLAVE_GRAPHICS_3D_CFG 598 +#define MSM_BUS_SLAVE_MMSS_CLK_CFG 599 +#define MSM_BUS_SLAVE_MMSS_CLK_XPU_CFG 600 +#define MSM_BUS_SLAVE_MNOC_MPU_CFG 601 +#define MSM_BUS_SLAVE_ONOC_MPU_CFG 602 +#define MSM_BUS_SLAVE_SERVICE_MNOC 603 +#define MSM_BUS_SLAVE_OCMEM 604 +#define MSM_BUS_SLAVE_SERVICE_ONOC 605 +#define MSM_BUS_SLAVE_SDCC_1 606 +#define MSM_BUS_SLAVE_SDCC_3 607 +#define MSM_BUS_SLAVE_SDCC_2 608 +#define MSM_BUS_SLAVE_SDCC_4 609 +#define MSM_BUS_SLAVE_BAM_DMA 610 +#define MSM_BUS_SLAVE_BLSP_2 611 +#define MSM_BUS_SLAVE_USB_HSIC 612 +#define MSM_BUS_SLAVE_BLSP_1 613 +#define MSM_BUS_SLAVE_USB_HS 614 +#define MSM_BUS_SLAVE_PDM 615 +#define MSM_BUS_SLAVE_PERIPH_APU_CFG 616 +#define MSM_BUS_SLAVE_PNOC_MPU_CFG 617 +#define MSM_BUS_SLAVE_PRNG 618 +#define MSM_BUS_SLAVE_SERVICE_PNOC 619 +#define MSM_BUS_SLAVE_CLK_CTL 620 +#define MSM_BUS_SLAVE_CNOC_MSS 621 +#define MSM_BUS_SLAVE_SECURITY 622 +#define MSM_BUS_SLAVE_TCSR 623 +#define MSM_BUS_SLAVE_TLMM 624 +#define MSM_BUS_SLAVE_CRYPTO_0_CFG 625 +#define MSM_BUS_SLAVE_CRYPTO_1_CFG 626 +#define MSM_BUS_SLAVE_IMEM_CFG 627 +#define MSM_BUS_SLAVE_MESSAGE_RAM 628 +#define MSM_BUS_SLAVE_BIMC_CFG 629 +#define MSM_BUS_SLAVE_BOOT_ROM 630 +#define MSM_BUS_SLAVE_CNOC_MNOC_MMSS_CFG 631 +#define MSM_BUS_SLAVE_PMIC_ARB 632 +#define MSM_BUS_SLAVE_SPDM_WRAPPER 633 +#define MSM_BUS_SLAVE_DEHR_CFG 634 +#define MSM_BUS_SLAVE_QDSS_CFG 635 +#define MSM_BUS_SLAVE_RBCPR_CFG 636 +#define MSM_BUS_SLAVE_RBCPR_QDSS_APU_CFG 637 +#define MSM_BUS_SLAVE_SNOC_MPU_CFG 638 +#define MSM_BUS_SLAVE_CNOC_ONOC_CFG 639 +#define MSM_BUS_SLAVE_CNOC_MNOC_CFG 640 +#define MSM_BUS_SLAVE_PNOC_CFG 641 +#define MSM_BUS_SLAVE_SNOC_CFG 642 +#define MSM_BUS_SLAVE_EBI1_DLL_CFG 643 +#define MSM_BUS_SLAVE_PHY_APU_CFG 644 +#define MSM_BUS_SLAVE_EBI1_PHY_CFG 645 +#define MSM_BUS_SLAVE_SERVICE_CNOC 646 +#define MSM_BUS_SLAVE_IPS_CFG 647 +#define MSM_BUS_SLAVE_QPIC 648 +#define MSM_BUS_SLAVE_DSI_CFG 649 +#define MSM_BUS_SLAVE_UFS_CFG 650 +#define MSM_BUS_SLAVE_RBCPR_CX_CFG 651 +#define MSM_BUS_SLAVE_RBCPR_MX_CFG 652 +#define MSM_BUS_SLAVE_PCIE_CFG 653 +#define MSM_BUS_SLAVE_USB_PHYS_CFG 654 +#define MSM_BUS_SLAVE_VIDEO_CAP_CFG 655 +#define MSM_BUS_SLAVE_AVSYNC_CFG 656 +#define MSM_BUS_SLAVE_CRYPTO_2_CFG 657 +#define MSM_BUS_SLAVE_VPU_CFG 658 +#define MSM_BUS_SLAVE_BCAST_CFG 659 +#define MSM_BUS_SLAVE_KLM_CFG 660 +#define MSM_BUS_SLAVE_GENI_IR_CFG 661 +#define MSM_BUS_SLAVE_OCMEM_GFX 662 +#define MSM_BUS_SLAVE_CATS_128 663 +#define MSM_BUS_SLAVE_OCMEM_64 664 +#define MSM_BUS_SLAVE_PCIE_0 665 +#define MSM_BUS_SLAVE_PCIE_1 666 +#define MSM_BUS_SLAVE_PCIE_0_CFG 667 +#define MSM_BUS_SLAVE_PCIE_1_CFG 668 +#define MSM_BUS_SLAVE_SRVC_MNOC 669 +#define MSM_BUS_SLAVE_USB_HS2 670 +#define MSM_BUS_SLAVE_AUDIO 671 +#define MSM_BUS_SLAVE_TCU 672 +#define MSM_BUS_SLAVE_APPSS 673 +#define MSM_BUS_SLAVE_PCIE_PARF 674 +#define MSM_BUS_SLAVE_USB3_PHY_CFG 675 +#define MSM_BUS_SLAVE_IPA_CFG 676 +#define MSM_BUS_SLAVE_A0NOC_SNOC 677 +#define MSM_BUS_SLAVE_A1NOC_SNOC 678 +#define MSM_BUS_SLAVE_A2NOC_SNOC 679 +#define MSM_BUS_SLAVE_HMSS_L3 680 +#define MSM_BUS_SLAVE_PIMEM_CFG 681 +#define MSM_BUS_SLAVE_DCC_CFG 682 +#define MSM_BUS_SLAVE_QDSS_RBCPR_APU_CFG 683 +#define MSM_BUS_SLAVE_PCIE_2_CFG 684 +#define MSM_BUS_SLAVE_PCIE20_AHB2PHY 685 +#define MSM_BUS_SLAVE_A0NOC_CFG 686 +#define MSM_BUS_SLAVE_A1NOC_CFG 687 +#define MSM_BUS_SLAVE_A2NOC_CFG 688 +#define MSM_BUS_SLAVE_A1NOC_MPU_CFG 689 +#define MSM_BUS_SLAVE_A2NOC_MPU_CFG 690 +#define MSM_BUS_SLAVE_A0NOC_SMMU_CFG 691 +#define MSM_BUS_SLAVE_A1NOC_SMMU_CFG 692 +#define MSM_BUS_SLAVE_A2NOC_SMMU_CFG 693 +#define MSM_BUS_SLAVE_LPASS_SMMU_CFG 694 +#define MSM_BUS_SLAVE_MMAGIC_CFG 695 +#define MSM_BUS_SLAVE_VENUS_THROTTLE_CFG 696 +#define MSM_BUS_SLAVE_SSC_CFG 697 +#define MSM_BUS_SLAVE_DSA_CFG 698 +#define MSM_BUS_SLAVE_DSA_MPU_CFG 699 +#define MSM_BUS_SLAVE_DISPLAY_THROTTLE_CFG 700 +#define MSM_BUS_SLAVE_SMMU_CPP_CFG 701 +#define MSM_BUS_SLAVE_SMMU_JPEG_CFG 702 +#define MSM_BUS_SLAVE_SMMU_MDP_CFG 703 +#define MSM_BUS_SLAVE_SMMU_ROTATOR_CFG 704 +#define MSM_BUS_SLAVE_SMMU_VENUS_CFG 705 +#define MSM_BUS_SLAVE_SMMU_VFE_CFG 706 +#define MSM_BUS_SLAVE_A0NOC_MPU_CFG 707 +#define MSM_BUS_SLAVE_VMEM_CFG 708 +#define MSM_BUS_SLAVE_CAMERA_THROTTLE_CFG 709 +#define MSM_BUS_SLAVE_VMEM 710 +#define MSM_BUS_SLAVE_AHB2PHY 711 +#define MSM_BUS_SLAVE_PIMEM 712 +#define MSM_BUS_SLAVE_SNOC_VMEM 713 +#define MSM_BUS_SLAVE_PCIE_2 714 +#define MSM_BUS_SLAVE_RBCPR_MX 715 +#define MSM_BUS_SLAVE_RBCPR_CX 716 +#define MSM_BUS_SLAVE_BIMC_PCNOC 717 +#define MSM_BUS_SLAVE_PCNOC_BIMC_1 718 +#define MSM_BUS_SLAVE_SGMII 719 +#define MSM_BUS_SLAVE_SPMI_FETCHER 720 +#define MSM_BUS_PNOC_SLV_6 721 +#define MSM_BUS_SLAVE_MMSS_SMMU_CFG 722 +#define MSM_BUS_SLAVE_WLAN 723 +#define MSM_BUS_SLAVE_CRVIRT_A2NOC 724 +#define MSM_BUS_SLAVE_CNOC_A2NOC 725 +#define MSM_BUS_SLAVE_GLM 726 +#define MSM_BUS_SLAVE_GNOC_BIMC 727 +#define MSM_BUS_SLAVE_GNOC_SNOC 728 +#define MSM_BUS_SLAVE_QM_CFG 729 +#define MSM_BUS_SLAVE_TLMM_EAST 730 +#define MSM_BUS_SLAVE_TLMM_NORTH 731 +#define MSM_BUS_SLAVE_TLMM_WEST 732 +#define MSM_BUS_SLAVE_SKL 733 +#define MSM_BUS_SLAVE_LPASS_TCM 734 +#define MSM_BUS_SLAVE_TLMM_SOUTH 735 +#define MSM_BUS_SLAVE_TLMM_CENTER 736 +#define MSM_BUS_MSS_NAV_CE_MPU_CFG 737 +#define MSM_BUS_SLAVE_A2NOC_THROTTLE_CFG 738 +#define MSM_BUS_SLAVE_CDSP 739 +#define MSM_BUS_SLAVE_CDSP_SMMU_CFG 740 +#define MSM_BUS_SLAVE_LPASS_MPU_CFG 741 +#define MSM_BUS_SLAVE_CSI_PHY_CFG 742 +#define MSM_BUS_SLAVE_LAST 743 + +#define MSM_BUS_SYSTEM_FPB_SLAVE_SYSTEM MSM_BUS_SYSTEM_SLAVE_SYSTEM_FPB +#define MSM_BUS_CPSS_FPB_SLAVE_SYSTEM MSM_BUS_SYSTEM_SLAVE_CPSS_FPB + +/* + * ID's used in RPM messages + */ +#define ICBID_MASTER_APPSS_PROC 0 +#define ICBID_MASTER_MSS_PROC 1 +#define ICBID_MASTER_MNOC_BIMC 2 +#define ICBID_MASTER_SNOC_BIMC 3 +#define ICBID_MASTER_SNOC_BIMC_0 ICBID_MASTER_SNOC_BIMC +#define ICBID_MASTER_CNOC_MNOC_MMSS_CFG 4 +#define ICBID_MASTER_CNOC_MNOC_CFG 5 +#define ICBID_MASTER_GFX3D 6 +#define ICBID_MASTER_JPEG 7 +#define ICBID_MASTER_MDP 8 +#define ICBID_MASTER_MDP0 ICBID_MASTER_MDP +#define ICBID_MASTER_MDPS ICBID_MASTER_MDP +#define ICBID_MASTER_VIDEO 9 +#define ICBID_MASTER_VIDEO_P0 ICBID_MASTER_VIDEO +#define ICBID_MASTER_VIDEO_P1 10 +#define ICBID_MASTER_VFE 11 +#define ICBID_MASTER_VFE0 ICBID_MASTER_VFE +#define ICBID_MASTER_CNOC_ONOC_CFG 12 +#define ICBID_MASTER_JPEG_OCMEM 13 +#define ICBID_MASTER_MDP_OCMEM 14 +#define ICBID_MASTER_VIDEO_P0_OCMEM 15 +#define ICBID_MASTER_VIDEO_P1_OCMEM 16 +#define ICBID_MASTER_VFE_OCMEM 17 +#define ICBID_MASTER_LPASS_AHB 18 +#define ICBID_MASTER_QDSS_BAM 19 +#define ICBID_MASTER_SNOC_CFG 20 +#define ICBID_MASTER_BIMC_SNOC 21 +#define ICBID_MASTER_BIMC_SNOC_0 ICBID_MASTER_BIMC_SNOC +#define ICBID_MASTER_CNOC_SNOC 22 +#define ICBID_MASTER_CRYPTO 23 +#define ICBID_MASTER_CRYPTO_CORE0 ICBID_MASTER_CRYPTO +#define ICBID_MASTER_CRYPTO_CORE1 24 +#define ICBID_MASTER_LPASS_PROC 25 +#define ICBID_MASTER_MSS 26 +#define ICBID_MASTER_MSS_NAV 27 +#define ICBID_MASTER_OCMEM_DMA 28 +#define ICBID_MASTER_PNOC_SNOC 29 +#define ICBID_MASTER_WCSS 30 +#define ICBID_MASTER_QDSS_ETR 31 +#define ICBID_MASTER_USB3 32 +#define ICBID_MASTER_USB3_0 ICBID_MASTER_USB3 +#define ICBID_MASTER_SDCC_1 33 +#define ICBID_MASTER_SDCC_3 34 +#define ICBID_MASTER_SDCC_2 35 +#define ICBID_MASTER_SDCC_4 36 +#define ICBID_MASTER_TSIF 37 +#define ICBID_MASTER_BAM_DMA 38 +#define ICBID_MASTER_BLSP_2 39 +#define ICBID_MASTER_USB_HSIC 40 +#define ICBID_MASTER_BLSP_1 41 +#define ICBID_MASTER_USB_HS 42 +#define ICBID_MASTER_USB_HS1 ICBID_MASTER_USB_HS +#define ICBID_MASTER_PNOC_CFG 43 +#define ICBID_MASTER_SNOC_PNOC 44 +#define ICBID_MASTER_RPM_INST 45 +#define ICBID_MASTER_RPM_DATA 46 +#define ICBID_MASTER_RPM_SYS 47 +#define ICBID_MASTER_DEHR 48 +#define ICBID_MASTER_QDSS_DAP 49 +#define ICBID_MASTER_SPDM 50 +#define ICBID_MASTER_TIC 51 +#define ICBID_MASTER_SNOC_CNOC 52 +#define ICBID_MASTER_GFX3D_OCMEM 53 +#define ICBID_MASTER_GFX3D_GMEM ICBID_MASTER_GFX3D_OCMEM +#define ICBID_MASTER_OVIRT_SNOC 54 +#define ICBID_MASTER_SNOC_OVIRT 55 +#define ICBID_MASTER_SNOC_GVIRT ICBID_MASTER_SNOC_OVIRT +#define ICBID_MASTER_ONOC_OVIRT 56 +#define ICBID_MASTER_USB_HS2 57 +#define ICBID_MASTER_QPIC 58 +#define ICBID_MASTER_IPA 59 +#define ICBID_MASTER_DSI 60 +#define ICBID_MASTER_MDP1 61 +#define ICBID_MASTER_MDPE ICBID_MASTER_MDP1 +#define ICBID_MASTER_VPU_PROC 62 +#define ICBID_MASTER_VPU 63 +#define ICBID_MASTER_VPU0 ICBID_MASTER_VPU +#define ICBID_MASTER_CRYPTO_CORE2 64 +#define ICBID_MASTER_PCIE_0 65 +#define ICBID_MASTER_PCIE_1 66 +#define ICBID_MASTER_SATA 67 +#define ICBID_MASTER_UFS 68 +#define ICBID_MASTER_USB3_1 69 +#define ICBID_MASTER_VIDEO_OCMEM 70 +#define ICBID_MASTER_VPU1 71 +#define ICBID_MASTER_VCAP 72 +#define ICBID_MASTER_EMAC 73 +#define ICBID_MASTER_BCAST 74 +#define ICBID_MASTER_MMSS_PROC 75 +#define ICBID_MASTER_SNOC_BIMC_1 76 +#define ICBID_MASTER_SNOC_PCNOC 77 +#define ICBID_MASTER_AUDIO 78 +#define ICBID_MASTER_MM_INT_0 79 +#define ICBID_MASTER_MM_INT_1 80 +#define ICBID_MASTER_MM_INT_2 81 +#define ICBID_MASTER_MM_INT_BIMC 82 +#define ICBID_MASTER_MSS_INT 83 +#define ICBID_MASTER_PCNOC_CFG 84 +#define ICBID_MASTER_PCNOC_INT_0 85 +#define ICBID_MASTER_PCNOC_INT_1 86 +#define ICBID_MASTER_PCNOC_M_0 87 +#define ICBID_MASTER_PCNOC_M_1 88 +#define ICBID_MASTER_PCNOC_S_0 89 +#define ICBID_MASTER_PCNOC_S_1 90 +#define ICBID_MASTER_PCNOC_S_2 91 +#define ICBID_MASTER_PCNOC_S_3 92 +#define ICBID_MASTER_PCNOC_S_4 93 +#define ICBID_MASTER_PCNOC_S_6 94 +#define ICBID_MASTER_PCNOC_S_7 95 +#define ICBID_MASTER_PCNOC_S_8 96 +#define ICBID_MASTER_PCNOC_S_9 97 +#define ICBID_MASTER_QDSS_INT 98 +#define ICBID_MASTER_SNOC_INT_0 99 +#define ICBID_MASTER_SNOC_INT_1 100 +#define ICBID_MASTER_SNOC_INT_BIMC 101 +#define ICBID_MASTER_TCU_0 102 +#define ICBID_MASTER_TCU_1 103 +#define ICBID_MASTER_BIMC_INT_0 104 +#define ICBID_MASTER_BIMC_INT_1 105 +#define ICBID_MASTER_CAMERA 106 +#define ICBID_MASTER_RICA 107 +#define ICBID_MASTER_SNOC_BIMC_2 108 +#define ICBID_MASTER_BIMC_SNOC_1 109 +#define ICBID_MASTER_A0NOC_SNOC 110 +#define ICBID_MASTER_A1NOC_SNOC 111 +#define ICBID_MASTER_A2NOC_SNOC 112 +#define ICBID_MASTER_PIMEM 113 +#define ICBID_MASTER_SNOC_VMEM 114 +#define ICBID_MASTER_CPP 115 +#define ICBID_MASTER_CNOC_A1NOC 116 +#define ICBID_MASTER_PNOC_A1NOC 117 +#define ICBID_MASTER_HMSS 118 +#define ICBID_MASTER_PCIE_2 119 +#define ICBID_MASTER_ROTATOR 120 +#define ICBID_MASTER_VENUS_VMEM 121 +#define ICBID_MASTER_DCC 122 +#define ICBID_MASTER_MCDMA 123 +#define ICBID_MASTER_PCNOC_INT_2 124 +#define ICBID_MASTER_PCNOC_INT_3 125 +#define ICBID_MASTER_PCNOC_INT_4 126 +#define ICBID_MASTER_PCNOC_INT_5 127 +#define ICBID_MASTER_PCNOC_INT_6 128 +#define ICBID_MASTER_PCNOC_S_5 129 +#define ICBID_MASTER_SENSORS_AHB 130 +#define ICBID_MASTER_SENSORS_PROC 131 +#define ICBID_MASTER_QSPI 132 +#define ICBID_MASTER_VFE1 133 +#define ICBID_MASTER_SNOC_INT_2 134 +#define ICBID_MASTER_SMMNOC_BIMC 135 +#define ICBID_MASTER_CRVIRT_A1NOC 136 +#define ICBID_MASTER_XM_USB_HS1 137 +#define ICBID_MASTER_XI_USB_HS1 138 +#define ICBID_MASTER_PCNOC_BIMC_1 139 +#define ICBID_MASTER_BIMC_PCNOC 140 +#define ICBID_MASTER_XI_HSIC 141 +#define ICBID_MASTER_SGMII 142 +#define ICBID_MASTER_SPMI_FETCHER 143 +#define ICBID_MASTER_GNOC_BIMC 144 +#define ICBID_MASTER_CRVIRT_A2NOC 145 +#define ICBID_MASTER_CNOC_A2NOC 146 +#define ICBID_MASTER_WLAN 147 +#define ICBID_MASTER_MSS_CE 148 +#define ICBID_MASTER_CDSP_PROC 149 +#define ICBID_MASTER_GNOC_SNOC 150 + +#define ICBID_SLAVE_EBI1 0 +#define ICBID_SLAVE_APPSS_L2 1 +#define ICBID_SLAVE_BIMC_SNOC 2 +#define ICBID_SLAVE_BIMC_SNOC_0 ICBID_SLAVE_BIMC_SNOC +#define ICBID_SLAVE_CAMERA_CFG 3 +#define ICBID_SLAVE_DISPLAY_CFG 4 +#define ICBID_SLAVE_OCMEM_CFG 5 +#define ICBID_SLAVE_CPR_CFG 6 +#define ICBID_SLAVE_CPR_XPU_CFG 7 +#define ICBID_SLAVE_MISC_CFG 8 +#define ICBID_SLAVE_MISC_XPU_CFG 9 +#define ICBID_SLAVE_VENUS_CFG 10 +#define ICBID_SLAVE_GFX3D_CFG 11 +#define ICBID_SLAVE_MMSS_CLK_CFG 12 +#define ICBID_SLAVE_MMSS_CLK_XPU_CFG 13 +#define ICBID_SLAVE_MNOC_MPU_CFG 14 +#define ICBID_SLAVE_ONOC_MPU_CFG 15 +#define ICBID_SLAVE_MNOC_BIMC 16 +#define ICBID_SLAVE_SERVICE_MNOC 17 +#define ICBID_SLAVE_OCMEM 18 +#define ICBID_SLAVE_GMEM ICBID_SLAVE_OCMEM +#define ICBID_SLAVE_SERVICE_ONOC 19 +#define ICBID_SLAVE_APPSS 20 +#define ICBID_SLAVE_LPASS 21 +#define ICBID_SLAVE_USB3 22 +#define ICBID_SLAVE_USB3_0 ICBID_SLAVE_USB3 +#define ICBID_SLAVE_WCSS 23 +#define ICBID_SLAVE_SNOC_BIMC 24 +#define ICBID_SLAVE_SNOC_BIMC_0 ICBID_SLAVE_SNOC_BIMC +#define ICBID_SLAVE_SNOC_CNOC 25 +#define ICBID_SLAVE_IMEM 26 +#define ICBID_SLAVE_OCIMEM ICBID_SLAVE_IMEM +#define ICBID_SLAVE_SNOC_OVIRT 27 +#define ICBID_SLAVE_SNOC_GVIRT ICBID_SLAVE_SNOC_OVIRT +#define ICBID_SLAVE_SNOC_PNOC 28 +#define ICBID_SLAVE_SNOC_PCNOC ICBID_SLAVE_SNOC_PNOC +#define ICBID_SLAVE_SERVICE_SNOC 29 +#define ICBID_SLAVE_QDSS_STM 30 +#define ICBID_SLAVE_SDCC_1 31 +#define ICBID_SLAVE_SDCC_3 32 +#define ICBID_SLAVE_SDCC_2 33 +#define ICBID_SLAVE_SDCC_4 34 +#define ICBID_SLAVE_TSIF 35 +#define ICBID_SLAVE_BAM_DMA 36 +#define ICBID_SLAVE_BLSP_2 37 +#define ICBID_SLAVE_USB_HSIC 38 +#define ICBID_SLAVE_BLSP_1 39 +#define ICBID_SLAVE_USB_HS 40 +#define ICBID_SLAVE_USB_HS1 ICBID_SLAVE_USB_HS +#define ICBID_SLAVE_PDM 41 +#define ICBID_SLAVE_PERIPH_APU_CFG 42 +#define ICBID_SLAVE_PNOC_MPU_CFG 43 +#define ICBID_SLAVE_PRNG 44 +#define ICBID_SLAVE_PNOC_SNOC 45 +#define ICBID_SLAVE_PCNOC_SNOC ICBID_SLAVE_PNOC_SNOC +#define ICBID_SLAVE_SERVICE_PNOC 46 +#define ICBID_SLAVE_CLK_CTL 47 +#define ICBID_SLAVE_CNOC_MSS 48 +#define ICBID_SLAVE_PCNOC_MSS ICBID_SLAVE_CNOC_MSS +#define ICBID_SLAVE_SECURITY 49 +#define ICBID_SLAVE_TCSR 50 +#define ICBID_SLAVE_TLMM 51 +#define ICBID_SLAVE_CRYPTO_0_CFG 52 +#define ICBID_SLAVE_CRYPTO_1_CFG 53 +#define ICBID_SLAVE_IMEM_CFG 54 +#define ICBID_SLAVE_MESSAGE_RAM 55 +#define ICBID_SLAVE_BIMC_CFG 56 +#define ICBID_SLAVE_BOOT_ROM 57 +#define ICBID_SLAVE_CNOC_MNOC_MMSS_CFG 58 +#define ICBID_SLAVE_PMIC_ARB 59 +#define ICBID_SLAVE_SPDM_WRAPPER 60 +#define ICBID_SLAVE_DEHR_CFG 61 +#define ICBID_SLAVE_MPM 62 +#define ICBID_SLAVE_QDSS_CFG 63 +#define ICBID_SLAVE_RBCPR_CFG 64 +#define ICBID_SLAVE_RBCPR_CX_CFG ICBID_SLAVE_RBCPR_CFG +#define ICBID_SLAVE_RBCPR_QDSS_APU_CFG 65 +#define ICBID_SLAVE_CNOC_MNOC_CFG 66 +#define ICBID_SLAVE_SNOC_MPU_CFG 67 +#define ICBID_SLAVE_CNOC_ONOC_CFG 68 +#define ICBID_SLAVE_PNOC_CFG 69 +#define ICBID_SLAVE_SNOC_CFG 70 +#define ICBID_SLAVE_EBI1_DLL_CFG 71 +#define ICBID_SLAVE_PHY_APU_CFG 72 +#define ICBID_SLAVE_EBI1_PHY_CFG 73 +#define ICBID_SLAVE_RPM 74 +#define ICBID_SLAVE_CNOC_SNOC 75 +#define ICBID_SLAVE_SERVICE_CNOC 76 +#define ICBID_SLAVE_OVIRT_SNOC 77 +#define ICBID_SLAVE_OVIRT_OCMEM 78 +#define ICBID_SLAVE_USB_HS2 79 +#define ICBID_SLAVE_QPIC 80 +#define ICBID_SLAVE_IPS_CFG 81 +#define ICBID_SLAVE_DSI_CFG 82 +#define ICBID_SLAVE_USB3_1 83 +#define ICBID_SLAVE_PCIE_0 84 +#define ICBID_SLAVE_PCIE_1 85 +#define ICBID_SLAVE_PSS_SMMU_CFG 86 +#define ICBID_SLAVE_CRYPTO_2_CFG 87 +#define ICBID_SLAVE_PCIE_0_CFG 88 +#define ICBID_SLAVE_PCIE_1_CFG 89 +#define ICBID_SLAVE_SATA_CFG 90 +#define ICBID_SLAVE_SPSS_GENI_IR 91 +#define ICBID_SLAVE_UFS_CFG 92 +#define ICBID_SLAVE_AVSYNC_CFG 93 +#define ICBID_SLAVE_VPU_CFG 94 +#define ICBID_SLAVE_USB_PHY_CFG 95 +#define ICBID_SLAVE_RBCPR_MX_CFG 96 +#define ICBID_SLAVE_PCIE_PARF 97 +#define ICBID_SLAVE_VCAP_CFG 98 +#define ICBID_SLAVE_EMAC_CFG 99 +#define ICBID_SLAVE_BCAST_CFG 100 +#define ICBID_SLAVE_KLM_CFG 101 +#define ICBID_SLAVE_DISPLAY_PWM 102 +#define ICBID_SLAVE_GENI 103 +#define ICBID_SLAVE_SNOC_BIMC_1 104 +#define ICBID_SLAVE_AUDIO 105 +#define ICBID_SLAVE_CATS_0 106 +#define ICBID_SLAVE_CATS_1 107 +#define ICBID_SLAVE_MM_INT_0 108 +#define ICBID_SLAVE_MM_INT_1 109 +#define ICBID_SLAVE_MM_INT_2 110 +#define ICBID_SLAVE_MM_INT_BIMC 111 +#define ICBID_SLAVE_MMU_MODEM_XPU_CFG 112 +#define ICBID_SLAVE_MSS_INT 113 +#define ICBID_SLAVE_PCNOC_INT_0 114 +#define ICBID_SLAVE_PCNOC_INT_1 115 +#define ICBID_SLAVE_PCNOC_M_0 116 +#define ICBID_SLAVE_PCNOC_M_1 117 +#define ICBID_SLAVE_PCNOC_S_0 118 +#define ICBID_SLAVE_PCNOC_S_1 119 +#define ICBID_SLAVE_PCNOC_S_2 120 +#define ICBID_SLAVE_PCNOC_S_3 121 +#define ICBID_SLAVE_PCNOC_S_4 122 +#define ICBID_SLAVE_PCNOC_S_6 123 +#define ICBID_SLAVE_PCNOC_S_7 124 +#define ICBID_SLAVE_PCNOC_S_8 125 +#define ICBID_SLAVE_PCNOC_S_9 126 +#define ICBID_SLAVE_PRNG_XPU_CFG 127 +#define ICBID_SLAVE_QDSS_INT 128 +#define ICBID_SLAVE_RPM_XPU_CFG 129 +#define ICBID_SLAVE_SNOC_INT_0 130 +#define ICBID_SLAVE_SNOC_INT_1 131 +#define ICBID_SLAVE_SNOC_INT_BIMC 132 +#define ICBID_SLAVE_TCU 133 +#define ICBID_SLAVE_BIMC_INT_0 134 +#define ICBID_SLAVE_BIMC_INT_1 135 +#define ICBID_SLAVE_RICA_CFG 136 +#define ICBID_SLAVE_SNOC_BIMC_2 137 +#define ICBID_SLAVE_BIMC_SNOC_1 138 +#define ICBID_SLAVE_PNOC_A1NOC 139 +#define ICBID_SLAVE_SNOC_VMEM 140 +#define ICBID_SLAVE_A0NOC_SNOC 141 +#define ICBID_SLAVE_A1NOC_SNOC 142 +#define ICBID_SLAVE_A2NOC_SNOC 143 +#define ICBID_SLAVE_A0NOC_CFG 144 +#define ICBID_SLAVE_A0NOC_MPU_CFG 145 +#define ICBID_SLAVE_A0NOC_SMMU_CFG 146 +#define ICBID_SLAVE_A1NOC_CFG 147 +#define ICBID_SLAVE_A1NOC_MPU_CFG 148 +#define ICBID_SLAVE_A1NOC_SMMU_CFG 149 +#define ICBID_SLAVE_A2NOC_CFG 150 +#define ICBID_SLAVE_A2NOC_MPU_CFG 151 +#define ICBID_SLAVE_A2NOC_SMMU_CFG 152 +#define ICBID_SLAVE_AHB2PHY 153 +#define ICBID_SLAVE_CAMERA_THROTTLE_CFG 154 +#define ICBID_SLAVE_DCC_CFG 155 +#define ICBID_SLAVE_DISPLAY_THROTTLE_CFG 156 +#define ICBID_SLAVE_DSA_CFG 157 +#define ICBID_SLAVE_DSA_MPU_CFG 158 +#define ICBID_SLAVE_SSC_MPU_CFG 159 +#define ICBID_SLAVE_HMSS_L3 160 +#define ICBID_SLAVE_LPASS_SMMU_CFG 161 +#define ICBID_SLAVE_MMAGIC_CFG 162 +#define ICBID_SLAVE_PCIE20_AHB2PHY 163 +#define ICBID_SLAVE_PCIE_2 164 +#define ICBID_SLAVE_PCIE_2_CFG 165 +#define ICBID_SLAVE_PIMEM 166 +#define ICBID_SLAVE_PIMEM_CFG 167 +#define ICBID_SLAVE_QDSS_RBCPR_APU_CFG 168 +#define ICBID_SLAVE_RBCPR_CX 169 +#define ICBID_SLAVE_RBCPR_MX 170 +#define ICBID_SLAVE_SMMU_CPP_CFG 171 +#define ICBID_SLAVE_SMMU_JPEG_CFG 172 +#define ICBID_SLAVE_SMMU_MDP_CFG 173 +#define ICBID_SLAVE_SMMU_ROTATOR_CFG 174 +#define ICBID_SLAVE_SMMU_VENUS_CFG 175 +#define ICBID_SLAVE_SMMU_VFE_CFG 176 +#define ICBID_SLAVE_SSC_CFG 177 +#define ICBID_SLAVE_VENUS_THROTTLE_CFG 178 +#define ICBID_SLAVE_VMEM 179 +#define ICBID_SLAVE_VMEM_CFG 180 +#define ICBID_SLAVE_QDSS_MPU_CFG 181 +#define ICBID_SLAVE_USB3_PHY_CFG 182 +#define ICBID_SLAVE_IPA_CFG 183 +#define ICBID_SLAVE_PCNOC_INT_2 184 +#define ICBID_SLAVE_PCNOC_INT_3 185 +#define ICBID_SLAVE_PCNOC_INT_4 186 +#define ICBID_SLAVE_PCNOC_INT_5 187 +#define ICBID_SLAVE_PCNOC_INT_6 188 +#define ICBID_SLAVE_PCNOC_S_5 189 +#define ICBID_SLAVE_QSPI 190 +#define ICBID_SLAVE_A1NOC_MS_MPU_CFG 191 +#define ICBID_SLAVE_A2NOC_MS_MPU_CFG 192 +#define ICBID_SLAVE_MODEM_Q6_SMMU_CFG 193 +#define ICBID_SLAVE_MSS_MPU_CFG 194 +#define ICBID_SLAVE_MSS_PROC_MS_MPU_CFG 195 +#define ICBID_SLAVE_SKL 196 +#define ICBID_SLAVE_SNOC_INT_2 197 +#define ICBID_SLAVE_SMMNOC_BIMC 198 +#define ICBID_SLAVE_CRVIRT_A1NOC 199 +#define ICBID_SLAVE_SGMII 200 +#define ICBID_SLAVE_QHS4_APPS 201 +#define ICBID_SLAVE_BIMC_PCNOC 202 +#define ICBID_SLAVE_PCNOC_BIMC_1 203 +#define ICBID_SLAVE_SPMI_FETCHER 204 +#define ICBID_SLAVE_MMSS_SMMU_CFG 205 +#define ICBID_SLAVE_WLAN 206 +#define ICBID_SLAVE_CRVIRT_A2NOC 207 +#define ICBID_SLAVE_CNOC_A2NOC 208 +#define ICBID_SLAVE_GLM 209 +#define ICBID_SLAVE_GNOC_BIMC 210 +#define ICBID_SLAVE_GNOC_SNOC 211 +#define ICBID_SLAVE_QM_CFG 212 +#define ICBID_SLAVE_TLMM_EAST 213 +#define ICBID_SLAVE_TLMM_NORTH 214 +#define ICBID_SLAVE_TLMM_WEST 215 +#define ICBID_SLAVE_LPASS_TCM 216 +#define ICBID_SLAVE_TLMM_SOUTH 217 +#define ICBID_SLAVE_TLMM_CENTER 218 +#define ICBID_SLAVE_MSS_NAV_CE_MPU_CFG 219 +#define ICBID_SLAVE_A2NOC_THROTTLE_CFG 220 +#define ICBID_SLAVE_CDSP 221 +#define ICBID_SLAVE_CDSP_SMMU_CFG 222 +#define ICBID_SLAVE_LPASS_MPU_CFG 223 +#define ICBID_SLAVE_CSI_PHY_CFG 224 +#endif diff -Nruw linux-4.4.115-fbx/arch/mips/boot/dts/include/dt-bindings/msm./msm-bus-rule-ops.h linux-4.4.115-fbx/arch/mips/boot/dts/include/dt-bindings/msm/msm-bus-rule-ops.h --- linux-4.4.115-fbx/arch/mips/boot/dts/include/dt-bindings/msm./msm-bus-rule-ops.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-4.4.115-fbx/arch/mips/boot/dts/include/dt-bindings/msm/msm-bus-rule-ops.h 2019-01-22 16:16:28.179288750 +0100 @@ -0,0 +1,34 @@ +/* Copyright (c) 2014, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __MSM_BUS_RULE_OPS_H +#define __MSM_BUS_RULE_OPS_H + +#define FLD_IB 0 +#define FLD_AB 1 +#define FLD_CLK 2 + +#define OP_LE 0 +#define OP_LT 1 +#define OP_GE 2 +#define OP_GT 3 +#define OP_NOOP 4 + +#define RULE_STATE_NOT_APPLIED 0 +#define RULE_STATE_APPLIED 1 + +#define THROTTLE_ON 0 +#define THROTTLE_OFF 1 +#define THROTTLE_REG 2 + + +#endif diff -Nruw linux-4.4.115-fbx/arch/mips/boot/dts/include/dt-bindings/msm./pm.h linux-4.4.115-fbx/arch/mips/boot/dts/include/dt-bindings/msm/pm.h --- linux-4.4.115-fbx/arch/mips/boot/dts/include/dt-bindings/msm./pm.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-4.4.115-fbx/arch/mips/boot/dts/include/dt-bindings/msm/pm.h 2019-01-22 16:16:28.179288750 +0100 @@ -0,0 +1,25 @@ +/* Copyright (c) 2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __DT_MSM_PM_H__ +#define __DT_MSM_PM_H__ + +#define LPM_RESET_LVL_NONE 0 +#define LPM_RESET_LVL_RET 1 +#define LPM_RESET_LVL_GDHS 2 +#define LPM_RESET_LVL_PC 3 + +#define LPM_AFF_LVL_CPU 0 +#define LPM_AFF_LVL_L2 1 +#define LPM_AFF_LVL_CCI 2 + +#endif diff -Nruw linux-4.4.115-fbx/arch/mips/boot/dts/include/dt-bindings/msm./power-on.h linux-4.4.115-fbx/arch/mips/boot/dts/include/dt-bindings/msm/power-on.h --- linux-4.4.115-fbx/arch/mips/boot/dts/include/dt-bindings/msm./power-on.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-4.4.115-fbx/arch/mips/boot/dts/include/dt-bindings/msm/power-on.h 2019-01-22 16:16:28.179288750 +0100 @@ -0,0 +1,24 @@ +/* Copyright (c) 2015, 2017, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __MSM_POWER_ON_H__ +#define __MSM_POWER_ON_H__ + +#define PON_POWER_OFF_RESERVED 0x00 +#define PON_POWER_OFF_WARM_RESET 0x01 +#define PON_POWER_OFF_SHUTDOWN 0x04 +#define PON_POWER_OFF_DVDD_SHUTDOWN 0x05 +#define PON_POWER_OFF_HARD_RESET 0x07 +#define PON_POWER_OFF_DVDD_HARD_RESET 0x08 +#define PON_POWER_OFF_MAX_TYPE 0x10 + +#endif --- /dev/null 2019-10-24 16:47:25.704025805 +0200 +++ linux-4.4.115-fbx/arch/mips/boot/dts/include/dt-bindings/regulator/qcom,rpm-smd-regulator.h 2019-01-22 16:16:28.183288787 +0100 @@ -0,0 +1,28 @@ +/* Copyright (c) 2015, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __QCOM_RPM_SMD_REGULATOR_H +#define __QCOM_RPM_SMD_REGULATOR_H + +#define RPM_SMD_REGULATOR_LEVEL_NONE 0 +#define RPM_SMD_REGULATOR_LEVEL_RETENTION 16 +#define RPM_SMD_REGULATOR_LEVEL_RETENTION_PLUS 32 +#define RPM_SMD_REGULATOR_LEVEL_MIN_SVS 48 +#define RPM_SMD_REGULATOR_LEVEL_LOW_SVS 64 +#define RPM_SMD_REGULATOR_LEVEL_SVS 128 +#define RPM_SMD_REGULATOR_LEVEL_SVS_PLUS 192 +#define RPM_SMD_REGULATOR_LEVEL_NOM 256 +#define RPM_SMD_REGULATOR_LEVEL_NOM_PLUS 320 +#define RPM_SMD_REGULATOR_LEVEL_TURBO 384 +#define RPM_SMD_REGULATOR_LEVEL_BINNING 512 + +#endif --- /dev/null 2019-10-24 16:47:25.704025805 +0200 +++ linux-4.4.115-fbx/arch/powerpc/boot/dts/include/dt-bindings/clock/audio-ext-clk.h 2019-01-22 16:16:28.167288642 +0100 @@ -0,0 +1,30 @@ +/* Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __AUDIO_EXT_CLK_H +#define __AUDIO_EXT_CLK_H + +/* Audio External Clocks */ +#define AUDIO_PMI_CLK 0 +#define AUDIO_PMIC_LNBB_CLK 0 +#define AUDIO_AP_CLK 1 +#define AUDIO_AP_CLK2 2 +#define AUDIO_LPASS_MCLK 3 +#define AUDIO_LPASS_MCLK2 4 + +#define clk_audio_ap_clk 0x9b5727cb +#define clk_audio_pmi_clk 0xcbfe416d +#define clk_audio_ap_clk2 0x454d1e91 +#define clk_audio_lpass_mclk 0xf0f2a284 +#define clk_audio_pmi_lnbb_clk 0x57312343 + +#endif --- /dev/null 2019-10-24 16:47:25.704025805 +0200 +++ linux-4.4.115-fbx/arch/powerpc/boot/dts/include/dt-bindings/clock/msm-clocks-8996.h 2019-01-22 16:16:28.171288678 +0100 @@ -0,0 +1,574 @@ +/* Copyright (c) 2014-2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __MSM_CLOCKS_8996_H +#define __MSM_CLOCKS_8996_H + +#include "audio-ext-clk.h" + +/* clock_gcc controlled clocks */ +#define clk_cxo_clk_src 0x79e95308 +#define clk_pnoc_clk 0x4325d220 +#define clk_pnoc_a_clk 0x2808c12b +#define clk_bimc_clk 0x4b80bf00 +#define clk_bimc_a_clk 0x4b25668a +#define clk_cnoc_clk 0xd5ccb7f4 +#define clk_cnoc_a_clk 0xd8fe2ccc +#define clk_snoc_clk 0x2c341aa0 +#define clk_snoc_a_clk 0x8fcef2af +#define clk_bb_clk1 0xf5304268 +#define clk_bb_clk1_ao 0xfa113810 +#define clk_bb_clk1_pin 0x6dd0a779 +#define clk_bb_clk1_pin_ao 0x9b637772 +#define clk_bb_clk2 0xfe15cb87 +#define clk_bb_clk2_ao 0x59682706 +#define clk_bb_clk2_pin 0x498938e5 +#define clk_bb_clk2_pin_ao 0x52513787 +#define clk_bimc_msmbus_clk 0xd212feea +#define clk_bimc_msmbus_a_clk 0x71d1a499 +#define clk_ce1_a_clk 0x44a833fe +#define clk_cnoc_msmbus_clk 0x62228b5d +#define clk_cnoc_msmbus_a_clk 0x67442955 +#define clk_cxo_clk_src_ao 0x64eb6004 +#define clk_cxo_dwc3_clk 0xf79c19f6 +#define clk_cxo_lpm_clk 0x94adbf3d +#define clk_cxo_otg_clk 0x4eec0bb9 +#define clk_cxo_pil_lpass_clk 0xe17f0ff6 +#define clk_cxo_pil_ssc_clk 0x81832015 +#define clk_div_clk1 0xaa1157a6 +#define clk_div_clk1_ao 0x6b943d68 +#define clk_div_clk2 0xd454019f +#define clk_div_clk2_ao 0x53f9e788 +#define clk_div_clk3 0xa9a55a68 +#define clk_div_clk3_ao 0x3d6725a8 +#define clk_ipa_a_clk 0xeeec2919 +#define clk_ipa_clk 0xfa685cda +#define clk_ln_bb_clk 0x3ab0b36d +#define clk_ln_bb_a_clk 0xc7257ea8 +#define clk_ln_bb_clk_pin 0x1b1c476a +#define clk_ln_bb_a_clk_pin 0x9cbb5411 +#define clk_mcd_ce1_clk 0xbb615d26 +#define clk_pnoc_keepalive_a_clk 0xf8f91f0b +#define clk_pnoc_msmbus_clk 0x38b95c77 +#define clk_pnoc_msmbus_a_clk 0x8c9b4e93 +#define clk_pnoc_pm_clk 0xd6f7dfb9 +#define clk_pnoc_sps_clk 0xd482ecc7 +#define clk_qdss_a_clk 0xdd121669 +#define clk_qdss_clk 0x1492202a +#define clk_rf_clk1 0xaabeea5a +#define clk_rf_clk1_ao 0x72a10cb8 +#define clk_rf_clk1_pin 0x8f463562 +#define clk_rf_clk1_pin_ao 0x62549ff6 +#define clk_rf_clk2 0x24a30992 +#define clk_rf_clk2_ao 0x944d8bbd +#define clk_rf_clk2_pin 0xa7c5602a +#define clk_rf_clk2_pin_ao 0x2d75eb4d +#define clk_snoc_msmbus_clk 0xe6900bb6 +#define clk_snoc_msmbus_a_clk 0x5d4683bd +#define clk_mcd_ce1_clk 0xbb615d26 +#define clk_qcedev_ce1_clk 0x293f97b0 +#define clk_qcrypto_ce1_clk 0xa6ac14df +#define clk_qseecom_ce1_clk 0xaa858373 +#define clk_scm_ce1_clk 0xd8ebcc62 +#define clk_ce1_clk 0x42229c55 +#define clk_gcc_ce1_ahb_m_clk 0x2eb28c01 +#define clk_gcc_ce1_axi_m_clk 0xc174dfba +#define clk_measure_only_bimc_hmss_axi_clk 0xc1cc4f11 +#define clk_aggre1_noc_clk 0x049abba8 +#define clk_aggre1_noc_a_clk 0xc12e4220 +#define clk_aggre2_noc_clk 0xaa681404 +#define clk_aggre2_noc_a_clk 0xcab67089 +#define clk_mmssnoc_axi_rpm_clk 0x4d7f8cdc +#define clk_mmssnoc_axi_rpm_a_clk 0xfbea899b +#define clk_mmssnoc_axi_clk 0xdb4b31e6 +#define clk_mmssnoc_axi_a_clk 0xd4970614 +#define clk_mmssnoc_gds_clk 0x06a22afa + +#define clk_gpll0 0x1ebe3bc4 +#define clk_gpll0_ao 0xa1368304 +#define clk_gpll0_out_main 0xe9374de7 +#define clk_gpll4 0xb3b5d85b +#define clk_gpll4_out_main 0xa9a0ab9d +#define clk_ufs_axi_clk_src 0x297ca380 +#define clk_pcie_aux_clk_src 0xebc50566 +#define clk_usb30_master_clk_src 0xc6262f89 +#define clk_usb20_master_clk_src 0x5680ac83 +#define clk_ufs_ice_core_clk_src 0xda8e7119 +#define clk_blsp1_qup1_i2c_apps_clk_src 0x17f78f5e +#define clk_blsp1_qup1_spi_apps_clk_src 0xf534c4fa +#define clk_blsp1_qup2_i2c_apps_clk_src 0x8de71c79 +#define clk_blsp1_qup2_spi_apps_clk_src 0x33cf809a +#define clk_blsp1_qup3_i2c_apps_clk_src 0xf161b902 +#define clk_blsp1_qup3_spi_apps_clk_src 0x5e95683f +#define clk_blsp1_qup4_i2c_apps_clk_src 0xb2ecce68 +#define clk_blsp1_qup4_spi_apps_clk_src 0xddb5bbdb +#define clk_blsp1_qup5_i2c_apps_clk_src 0x71ea7804 +#define clk_blsp1_qup5_spi_apps_clk_src 0x9752f35f +#define clk_blsp1_qup6_i2c_apps_clk_src 0x28806803 +#define clk_blsp1_qup6_spi_apps_clk_src 0x44a1edc4 +#define clk_blsp1_uart1_apps_clk_src 0xf8146114 +#define clk_blsp1_uart2_apps_clk_src 0xfc9c2f73 +#define clk_blsp1_uart3_apps_clk_src 0x600497f2 +#define clk_blsp1_uart4_apps_clk_src 0x56bff15c +#define clk_blsp1_uart5_apps_clk_src 0x218ef697 +#define clk_blsp1_uart6_apps_clk_src 0x8fbdbe4c +#define clk_blsp2_qup1_i2c_apps_clk_src 0xd6d1e95d +#define clk_blsp2_qup1_spi_apps_clk_src 0xcc1b8365 +#define clk_blsp2_qup2_i2c_apps_clk_src 0x603b5c51 +#define clk_blsp2_qup2_spi_apps_clk_src 0xd577dc44 +#define clk_blsp2_qup3_i2c_apps_clk_src 0xea82959c +#define clk_blsp2_qup3_spi_apps_clk_src 0xd04b1e92 +#define clk_blsp2_qup4_i2c_apps_clk_src 0x73dc968c +#define clk_blsp2_qup4_spi_apps_clk_src 0x25d4a2b1 +#define clk_blsp2_qup5_i2c_apps_clk_src 0xcc3698bd +#define clk_blsp2_qup5_spi_apps_clk_src 0xfa0cf45e +#define clk_blsp2_qup6_i2c_apps_clk_src 0x2fa53151 +#define clk_blsp2_qup6_spi_apps_clk_src 0x5ca86755 +#define clk_blsp2_uart1_apps_clk_src 0x562c66dc +#define clk_blsp2_uart2_apps_clk_src 0xdd448080 +#define clk_blsp2_uart3_apps_clk_src 0x46b2e90f +#define clk_blsp2_uart4_apps_clk_src 0x23a093d2 +#define clk_blsp2_uart5_apps_clk_src 0xe067616a +#define clk_blsp2_uart6_apps_clk_src 0xe02d2829 +#define clk_gp1_clk_src 0xad85b97a +#define clk_gp2_clk_src 0xfb1f0065 +#define clk_gp3_clk_src 0x63b693d6 +#define clk_hmss_rbcpr_clk_src 0xedd9a474 +#define clk_pdm2_clk_src 0x31e494fd +#define clk_sdcc1_apps_clk_src 0xd4975db2 +#define clk_sdcc2_apps_clk_src 0xfc46c821 +#define clk_sdcc3_apps_clk_src 0xea34c7f4 +#define clk_sdcc4_apps_clk_src 0x7aaaaa0c +#define clk_tsif_ref_clk_src 0x4e9042d1 +#define clk_usb20_mock_utmi_clk_src 0xc3aaeecb +#define clk_usb30_mock_utmi_clk_src 0xa024a976 +#define clk_usb3_phy_aux_clk_src 0x15eec63c +#define clk_gcc_qusb2phy_prim_reset 0x07550fa1 +#define clk_gcc_qusb2phy_sec_reset 0x3f3a87d0 +#define clk_gcc_periph_noc_usb20_ahb_clk 0xfb9f26e9 +#define clk_gcc_mmss_gcc_dbg_clk 0xe89d461c +#define clk_cpu_dbg_clk 0x6550dfa9 +#define clk_gcc_blsp1_ahb_clk 0x8caa5b4f +#define clk_gcc_blsp1_qup1_i2c_apps_clk 0xc303fae9 +#define clk_gcc_blsp1_qup1_spi_apps_clk 0x759a76b0 +#define clk_gcc_blsp1_qup2_i2c_apps_clk 0x1076f220 +#define clk_gcc_blsp1_qup2_spi_apps_clk 0x3e77d48f +#define clk_gcc_blsp1_qup3_i2c_apps_clk 0x9e25ac82 +#define clk_gcc_blsp1_qup3_spi_apps_clk 0xfb978880 +#define clk_gcc_blsp1_qup4_i2c_apps_clk 0xd7f40f6f +#define clk_gcc_blsp1_qup4_spi_apps_clk 0x80f8722f +#define clk_gcc_blsp1_qup5_i2c_apps_clk 0xacae5604 +#define clk_gcc_blsp1_qup5_spi_apps_clk 0xbf3e15d7 +#define clk_gcc_blsp1_qup6_i2c_apps_clk 0x5c6ad820 +#define clk_gcc_blsp1_qup6_spi_apps_clk 0x780d9f85 +#define clk_gcc_blsp1_uart1_apps_clk 0xc7c62f90 +#define clk_gcc_blsp1_uart2_apps_clk 0xf8a61c96 +#define clk_gcc_blsp1_uart3_apps_clk 0xc3298bd7 +#define clk_gcc_blsp1_uart4_apps_clk 0x26be16c0 +#define clk_gcc_blsp1_uart5_apps_clk 0x28a6bc74 +#define clk_gcc_blsp1_uart6_apps_clk 0x28fd3466 +#define clk_gcc_blsp2_ahb_clk 0x8f283c1d +#define clk_gcc_blsp2_qup1_i2c_apps_clk 0x9ace11dd +#define clk_gcc_blsp2_qup1_spi_apps_clk 0xa32604cc +#define clk_gcc_blsp2_qup2_i2c_apps_clk 0x1bf9a57e +#define clk_gcc_blsp2_qup2_spi_apps_clk 0xbf54ca6d +#define clk_gcc_blsp2_qup3_i2c_apps_clk 0x336d4170 +#define clk_gcc_blsp2_qup3_spi_apps_clk 0xc68509d6 +#define clk_gcc_blsp2_qup4_i2c_apps_clk 0xbd22539d +#define clk_gcc_blsp2_qup4_spi_apps_clk 0x01a72b93 +#define clk_gcc_blsp2_qup5_i2c_apps_clk 0xe2b2ce1d +#define clk_gcc_blsp2_qup5_spi_apps_clk 0xf40999cd +#define clk_gcc_blsp2_qup6_i2c_apps_clk 0x894bcea4 +#define clk_gcc_blsp2_qup6_spi_apps_clk 0xfe1bd34a +#define clk_gcc_blsp2_uart1_apps_clk 0x8c3512ff +#define clk_gcc_blsp2_uart2_apps_clk 0x1e1965a3 +#define clk_gcc_blsp2_uart3_apps_clk 0x382415ab +#define clk_gcc_blsp2_uart4_apps_clk 0x87a44b42 +#define clk_gcc_blsp2_uart5_apps_clk 0x5cd30649 +#define clk_gcc_blsp2_uart6_apps_clk 0x8feee5ab +#define clk_gcc_boot_rom_ahb_clk 0xde2adeb1 +#define clk_gcc_gp1_clk 0x057f7b69 +#define clk_gcc_gp2_clk 0x9bf83ffd +#define clk_gcc_gp3_clk 0xec6539ee +#define clk_gcc_hmss_rbcpr_clk 0x699183be +#define clk_gcc_mmss_noc_cfg_ahb_clk 0xb41a9d99 +#define clk_gcc_pcie_0_aux_clk 0x3d2e3ece +#define clk_gcc_pcie_0_cfg_ahb_clk 0x4dd325c3 +#define clk_gcc_pcie_0_mstr_axi_clk 0x3f85285b +#define clk_gcc_pcie_0_slv_axi_clk 0xd69638a1 +#define clk_gcc_pcie_0_pipe_clk 0x4f37621e +#define clk_gcc_pcie_0_phy_reset 0xdc3201c1 +#define clk_gcc_pcie_1_aux_clk 0xc9bb962c +#define clk_gcc_pcie_1_cfg_ahb_clk 0xb6338658 +#define clk_gcc_pcie_1_mstr_axi_clk 0xc20f6269 +#define clk_gcc_pcie_1_slv_axi_clk 0xd54e40d6 +#define clk_gcc_pcie_1_pipe_clk 0xc1627422 +#define clk_gcc_pcie_1_phy_reset 0x674481bb +#define clk_gcc_pcie_2_aux_clk 0xa4dc7ae8 +#define clk_gcc_pcie_2_cfg_ahb_clk 0x4f1d3121 +#define clk_gcc_pcie_2_mstr_axi_clk 0x9e81724a +#define clk_gcc_pcie_2_slv_axi_clk 0x7990d8b2 +#define clk_gcc_pcie_2_pipe_clk 0xa757a834 +#define clk_gcc_pcie_2_phy_reset 0x82634880 +#define clk_gcc_pcie_phy_reset 0x9bc3c959 +#define clk_gcc_pcie_phy_com_reset 0x8bf513e6 +#define clk_gcc_pcie_phy_nocsr_com_phy_reset 0x0c16a2da +#define clk_gcc_pcie_phy_aux_clk 0x4746e74f +#define clk_gcc_pcie_phy_cfg_ahb_clk 0x8533671a +#define clk_gcc_pdm2_clk 0x99d55711 +#define clk_gcc_pdm_ahb_clk 0x365664f6 +#define clk_gcc_prng_ahb_clk 0x397e7eaa +#define clk_gcc_sdcc1_ahb_clk 0x691e0caa +#define clk_gcc_sdcc1_apps_clk 0x9ad6fb96 +#define clk_gcc_sdcc2_ahb_clk 0x23d5727f +#define clk_gcc_sdcc2_apps_clk 0x861b20ac +#define clk_gcc_sdcc3_ahb_clk 0x565b2c03 +#define clk_gcc_sdcc3_apps_clk 0x0b27aeac +#define clk_gcc_sdcc4_ahb_clk 0x64f3e6a8 +#define clk_gcc_sdcc4_apps_clk 0xbf7c4dc8 +#define clk_gcc_tsif_ahb_clk 0x88d2822c +#define clk_gcc_tsif_ref_clk 0x8f1ed2c2 +#define clk_gcc_ufs_ahb_clk 0x1914bb84 +#define clk_gcc_ufs_axi_clk 0x47c743a7 +#define clk_gcc_ufs_ice_core_clk 0x310b0710 +#define clk_gcc_ufs_rx_cfg_clk 0xa6747786 +#define clk_gcc_ufs_rx_symbol_0_clk 0x7f43251c +#define clk_gcc_ufs_rx_symbol_1_clk 0x03182fde +#define clk_gcc_ufs_tx_cfg_clk 0xba2cf8b5 +#define clk_gcc_ufs_tx_symbol_0_clk 0x6a9f747a +#define clk_gcc_ufs_unipro_core_clk 0x2daf7fd2 +#define clk_gcc_ufs_sys_clk_core_clk 0x360e5ac8 +#define clk_gcc_ufs_tx_symbol_clk_core_clk 0xf6fb0df7 +#define clk_gcc_usb20_master_clk 0x24c3b66a +#define clk_gcc_usb20_mock_utmi_clk 0xe8db8203 +#define clk_gcc_usb20_sleep_clk 0x6e8cb4b2 +#define clk_gcc_usb30_master_clk 0xb3b4e2cb +#define clk_gcc_usb30_mock_utmi_clk 0xa800b65a +#define clk_gcc_usb30_sleep_clk 0xd0b65c92 +#define clk_gcc_usb3_phy_aux_clk 0x0d9a36e0 +#define clk_gcc_usb3_phy_pipe_clk 0xf279aff2 +#define clk_gcc_usb_phy_cfg_ahb2phy_clk 0xd1231a0e +#define clk_gcc_aggre0_cnoc_ahb_clk 0x53a35559 +#define clk_gcc_aggre0_snoc_axi_clk 0x3c446400 +#define clk_gcc_aggre0_noc_qosgen_extref_clk 0x8c4356ba +#define clk_hlos1_vote_lpass_core_smmu_clk 0x3aaa1743 +#define clk_hlos1_vote_lpass_adsp_smmu_clk 0xc76f702f +#define clk_gcc_usb3_phy_reset 0x03d559f1 +#define clk_gcc_usb3phy_phy_reset 0xb1a4f885 +#define clk_gcc_usb3_clkref_clk 0xb6cc8f01 +#define clk_gcc_hdmi_clkref_clk 0x4d4eec04 +#define clk_gcc_edp_clkref_clk 0xa8685c3f +#define clk_gcc_ufs_clkref_clk 0x92aa126f +#define clk_gcc_pcie_clkref_clk 0xa2e247fa +#define clk_gcc_rx2_usb2_clkref_clk 0x27ec24ba +#define clk_gcc_rx1_usb2_clkref_clk 0x53351d25 +#define clk_gcc_smmu_aggre0_ahb_clk 0x47a06ce4 +#define clk_gcc_smmu_aggre0_axi_clk 0x3cac4a6c +#define clk_gcc_sys_noc_usb3_axi_clk 0x94d26800 +#define clk_gcc_sys_noc_ufs_axi_clk 0x19d38312 +#define clk_gcc_aggre2_usb3_axi_clk 0xd5822a8e +#define clk_gcc_aggre2_ufs_axi_clk 0xb31e5191 +#define clk_gcc_mmss_gpll0_div_clk 0xdd06848d +#define clk_gcc_mmss_bimc_gfx_clk 0xe4f28754 +#define clk_gcc_bimc_gfx_clk 0x3edd69ad +#define clk_gcc_qspi_ahb_clk 0x96969dc8 +#define clk_gcc_qspi_ser_clk 0xfaf1e266 +#define clk_qspi_ser_clk_src 0x426676ee +#define clk_sdcc1_ice_core_clk_src 0xfd6a4301 +#define clk_gcc_sdcc1_ice_core_clk 0x0fd5680a +#define clk_gcc_mss_cfg_ahb_clk 0x111cde81 +#define clk_gcc_mss_snoc_axi_clk 0x0e71de85 +#define clk_gcc_mss_q6_bimc_axi_clk 0x67544d62 +#define clk_gcc_mss_mnoc_bimc_axi_clk 0xf665d03f +#define clk_gpll0_out_msscc 0x7d794829 +#define clk_gcc_debug_mux_v2 0xf7e749f0 +#define clk_gcc_dcc_ahb_clk 0xfa14a88c +#define clk_gcc_aggre0_noc_mpu_cfg_ahb_clk 0x5c1bb8e2 + +/* clock_mmss controlled clocks */ +#define clk_mmsscc_xo 0x05e63704 +#define clk_mmsscc_gpll0 0xe900c515 +#define clk_mmsscc_gpll0_div 0x73892e05 +#define clk_mmsscc_mmssnoc_ahb 0x7b4bd6f7 +#define clk_mmpll0 0xdd83b751 +#define clk_mmpll0_out_main 0x2f996a31 +#define clk_mmpll1 0x6da7fb90 +#define clk_mmpll1_out_main 0xa0d3a7da +#define clk_mmpll4 0x22c063c1 +#define clk_mmpll4_out_main 0xfb21c2fd +#define clk_mmpll3 0x18c76899 +#define clk_mmpll3_out_main 0x6eb6328f +#define clk_ahb_clk_src 0x86f49203 +#define clk_mmpll2 0x1190e4d8 +#define clk_mmpll2_out_main 0x1e9e24a8 +#define clk_mmpll8 0xd06ad45e +#define clk_mmpll8_out_main 0x75b1f386 +#define clk_mmpll9 0x1c50684c +#define clk_mmpll9_out_main 0x16b74937 +#define clk_mmpll5 0xa41e1936 +#define clk_mmpll5_out_main 0xcc1897bf +#define clk_csi0_clk_src 0x227e65bc +#define clk_vfe0_clk_src 0xa0c2bd8f +#define clk_vfe1_clk_src 0x4e357366 +#define clk_csi1_clk_src 0x6a2a6c36 +#define clk_csi2_clk_src 0x4113589f +#define clk_csi3_clk_src 0xfd934012 +#define clk_maxi_clk_src 0x52c09777 +#define clk_cpp_clk_src 0x8382f56d +#define clk_jpeg0_clk_src 0x9a0a0ac3 +#define clk_jpeg2_clk_src 0x5ad927f3 +#define clk_jpeg_dma_clk_src 0xb68afcea +#define clk_mdp_clk_src 0x6dc1f8f1 +#define clk_video_core_clk_src 0x8be4c944 +#define clk_fd_core_clk_src 0xe4799ab7 +#define clk_cci_clk_src 0x822f3d97 +#define clk_csiphy0_3p_clk_src 0xd2474b12 +#define clk_csiphy1_3p_clk_src 0x46a02aff +#define clk_csiphy2_3p_clk_src 0x1447813f +#define clk_camss_gp0_clk_src 0x6b57cfe6 +#define clk_camss_gp1_clk_src 0xf735368a +#define clk_jpeg_dma_clk_src 0xb68afcea +#define clk_mclk0_clk_src 0x266b3853 +#define clk_mclk1_clk_src 0xa73cad0c +#define clk_mclk2_clk_src 0x42545468 +#define clk_mclk3_clk_src 0x2bfbb714 +#define clk_csi0phytimer_clk_src 0xc8a309be +#define clk_csi1phytimer_clk_src 0x7c0fe23a +#define clk_csi2phytimer_clk_src 0x62ffea9c +#define clk_rbbmtimer_clk_src 0x17649ecc +#define clk_esc0_clk_src 0xb41d7c38 +#define clk_esc1_clk_src 0x3b0afa42 +#define clk_hdmi_clk_src 0xb40aeea9 +#define clk_vsync_clk_src 0xecb43940 +#define clk_rbcpr_clk_src 0x2c2e9af2 +#define clk_video_subcore0_clk_src 0x88d79636 +#define clk_video_subcore1_clk_src 0x4966930c +#define clk_mmss_bto_ahb_clk 0xfdf8c361 +#define clk_camss_ahb_clk 0xc4ff91d4 +#define clk_camss_cci_ahb_clk 0x04c4441a +#define clk_camss_cci_clk 0xd6cb5eb9 +#define clk_camss_cpp_ahb_clk 0x12e9a87b +#define clk_camss_cpp_clk 0xb82f366b +#define clk_camss_cpp_axi_clk 0x5598c804 +#define clk_camss_cpp_vbif_ahb_clk 0xb5f31be4 +#define clk_camss_csi0_ahb_clk 0x6e29c972 +#define clk_camss_csi0_clk 0x30862ddb +#define clk_camss_csi0phy_clk 0x2cecfb84 +#define clk_camss_csi0pix_clk 0x6946f77b +#define clk_camss_csi0rdi_clk 0x83645ef5 +#define clk_camss_csi1_ahb_clk 0xccc15f06 +#define clk_camss_csi1_clk 0xb150f052 +#define clk_camss_csi1phy_clk 0xb989f06d +#define clk_camss_csi1pix_clk 0x58d19bf3 +#define clk_camss_csi1rdi_clk 0x4d2f3352 +#define clk_camss_csi2_ahb_clk 0x92d02d75 +#define clk_camss_csi2_clk 0x74fc92e8 +#define clk_camss_csi2phy_clk 0xda05d9d8 +#define clk_camss_csi2pix_clk 0xf8ed0731 +#define clk_camss_csi2rdi_clk 0xdc1b2081 +#define clk_camss_csi3_ahb_clk 0xee5e459c +#define clk_camss_csi3_clk 0x39488fdd +#define clk_camss_csi3phy_clk 0x8b6063b9 +#define clk_camss_csi3pix_clk 0xd82bd467 +#define clk_camss_csi3rdi_clk 0xb6750046 +#define clk_camss_csi_vfe0_clk 0x3023937a +#define clk_camss_csi_vfe1_clk 0xe66fa522 +#define clk_camss_csiphy0_3p_clk 0xf2a54f5a +#define clk_camss_csiphy1_3p_clk 0x8bf70cb2 +#define clk_camss_csiphy2_3p_clk 0x1c14c939 +#define clk_camss_gp0_clk 0xcee7e51d +#define clk_camss_gp1_clk 0x41f1c2e3 +#define clk_camss_ispif_ahb_clk 0x9a212c6d +#define clk_camss_jpeg0_clk 0x0b0e2db7 +#define clk_camss_jpeg2_clk 0xd7291c8d +#define clk_camss_jpeg_ahb_clk 0x1f47fd28 +#define clk_camss_jpeg_axi_clk 0x9e5545c8 +#define clk_camss_jpeg_dma_clk 0x2336e65d +#define clk_camss_mclk0_clk 0xcf0c61e0 +#define clk_camss_mclk1_clk 0xd1410ed4 +#define clk_camss_mclk2_clk 0x851286f2 +#define clk_camss_mclk3_clk 0x4db11c45 +#define clk_camss_micro_ahb_clk 0x33a23277 +#define clk_camss_csi0phytimer_clk 0xff93b3c8 +#define clk_camss_csi1phytimer_clk 0x6c399ab6 +#define clk_camss_csi2phytimer_clk 0x24f47f49 +#define clk_camss_top_ahb_clk 0x8f8b2d33 +#define clk_camss_vfe_ahb_clk 0x595197bc +#define clk_camss_vfe_axi_clk 0x273d4c31 +#define clk_camss_vfe0_ahb_clk 0x4652833c +#define clk_camss_vfe0_clk 0x1e9bb8c4 +#define clk_camss_vfe0_stream_clk 0x22835fa4 +#define clk_camss_vfe1_ahb_clk 0x6a56abd3 +#define clk_camss_vfe1_clk 0x5bffa69b +#define clk_camss_vfe1_stream_clk 0x92f849b9 +#define clk_fd_ahb_clk 0x868a2c5c +#define clk_fd_core_clk 0x3badcae4 +#define clk_fd_core_uar_clk 0x7e624e15 +#define clk_gpu_ahb_clk 0xf97f1d43 +#define clk_gpu_aon_isense_clk 0xa9e9b297 +#define clk_gpu_gx_gfx3d_clk 0xb7ece823 +#define clk_gpu_mx_clk 0xb80ccedf +#define clk_gpu_gx_rbbmtimer_clk 0xdeba634e +#define clk_mdss_ahb_clk 0x684ccb41 +#define clk_mdss_axi_clk 0xcc07d687 +#define clk_mdss_esc0_clk 0x28cafbe6 +#define clk_mdss_esc1_clk 0xc22c6883 +#define clk_mdss_hdmi_ahb_clk 0x01cef516 +#define clk_mdss_hdmi_clk 0x097a6de9 +#define clk_mdss_mdp_clk 0x618336ac +#define clk_mdss_vsync_clk 0x42a022d3 +#define clk_mmss_misc_ahb_clk 0xea30b0e7 +#define clk_mmss_misc_cxo_clk 0xe620cd80 +#define clk_mmagic_bimc_noc_cfg_ahb_clk 0x12d5ba72 +#define clk_mmagic_camss_axi_clk 0xa8b1c16b +#define clk_mmagic_camss_noc_cfg_ahb_clk 0x5182c819 +#define clk_mmss_mmagic_cfg_ahb_clk 0x5e94a822 +#define clk_mmagic_mdss_axi_clk 0xa0359d10 +#define clk_mmagic_mdss_noc_cfg_ahb_clk 0x9c6d5482 +#define clk_mmagic_video_axi_clk 0x7b9219c3 +#define clk_mmagic_video_noc_cfg_ahb_clk 0x5124d256 +#define clk_mmss_mmagic_ahb_clk 0x3d15f2b0 +#define clk_mmss_mmagic_maxi_clk 0xbdaf5af7 +#define clk_mmss_rbcpr_ahb_clk 0x623ba55f +#define clk_mmss_rbcpr_clk 0x69a23a6f +#define clk_mmss_spdm_cpp_clk 0xefe35cd2 +#define clk_mmss_spdm_jpeg_dma_clk 0xcb7bd5a0 +#define clk_smmu_cpp_ahb_clk 0x3ad82d84 +#define clk_smmu_cpp_axi_clk 0xa6bb2f4a +#define clk_smmu_jpeg_ahb_clk 0x10c436ec +#define clk_smmu_jpeg_axi_clk 0x41112f37 +#define clk_smmu_mdp_ahb_clk 0x04994cb2 +#define clk_smmu_mdp_axi_clk 0x7fd71687 +#define clk_smmu_rot_ahb_clk 0xa30772c9 +#define clk_smmu_rot_axi_clk 0xfed7c078 +#define clk_smmu_vfe_ahb_clk 0x4dabebe7 +#define clk_smmu_vfe_axi_clk 0xde483725 +#define clk_smmu_video_ahb_clk 0x2d738e2c +#define clk_smmu_video_axi_clk 0xe2b5b887 +#define clk_video_ahb_clk 0x90775cfb +#define clk_video_axi_clk 0xe6c16dba +#define clk_video_core_clk 0x7e876ec3 +#define clk_video_maxi_clk 0x97749db6 +#define clk_video_subcore0_clk 0xb6f63e6c +#define clk_video_subcore1_clk 0x26c29cb4 +#define clk_vmem_ahb_clk 0xab6223ff +#define clk_vmem_maxi_clk 0x15ef32db +#define clk_mmss_debug_mux 0xe646ffda +#define clk_mmss_gcc_dbg_clk 0xafa4d48a +#define clk_gfx3d_clk_src 0x917f76ef +#define clk_extpclk_clk_src 0xb2c31abd +#define clk_mdss_byte0_clk 0xf5a03f64 +#define clk_mdss_byte1_clk 0xb8c7067d +#define clk_mdss_extpclk_clk 0xfa5aadb0 +#define clk_mdss_pclk0_clk 0x3487234a +#define clk_mdss_pclk1_clk 0xd5804246 +#define clk_gpu_gcc_dbg_clk 0x0ccc42cd +#define clk_mdss_mdp_vote_clk 0x588460a4 +#define clk_mdss_rotator_vote_clk 0x5b1f675e +#define clk_mmpll2_postdiv_clk 0x4fdeaaba +#define clk_mmpll8_postdiv_clk 0xedf57882 +#define clk_mmpll9_postdiv_clk 0x3064b618 +#define clk_gfx3d_clk_src_v2 0x4210acb7 +#define clk_byte0_clk_src 0x75cc885b +#define clk_byte1_clk_src 0x63c2c955 +#define clk_pclk0_clk_src 0xccac1f35 +#define clk_pclk1_clk_src 0x090f68ac +#define clk_ext_byte0_clk_src 0xfb32f31e +#define clk_ext_byte1_clk_src 0x585ef6d4 +#define clk_ext_pclk0_clk_src 0x087c1612 +#define clk_ext_pclk1_clk_src 0x8067c5a3 + +/* clock_debug controlled clocks */ +#define clk_gcc_debug_mux 0x8121ac15 + +/* external multimedia clocks */ +#define clk_dsi0pll_pixel_clk_mux 0x792379e1 +#define clk_dsi0pll_byte_clk_mux 0x60e83f06 +#define clk_dsi0pll_byte_clk_src 0xbbaa30be +#define clk_dsi0pll_pixel_clk_src 0x45b3260f +#define clk_dsi0pll_n2_div_clk 0x1474c213 +#define clk_dsi0pll_post_n1_div_clk 0xdab8c389 +#define clk_dsi0pll_vco_clk 0x15940d40 +#define clk_dsi1pll_pixel_clk_mux 0x36458019 +#define clk_dsi1pll_byte_clk_mux 0xb5a42b7b +#define clk_dsi1pll_byte_clk_src 0x63930a8f +#define clk_dsi1pll_pixel_clk_src 0x0e4c9b56 +#define clk_dsi1pll_n2_div_clk 0x2c9d4007 +#define clk_dsi1pll_post_n1_div_clk 0x03020041 +#define clk_dsi1pll_vco_clk 0x99797b50 +#define clk_mdss_dsi1_vco_clk_src 0xfcd15658 +#define clk_hdmi_vco_clk 0x66003284 + +#define clk_dsi0pll_shadow_byte_clk_src 0x177c029c +#define clk_dsi0pll_shadow_pixel_clk_src 0x98ae3c92 +#define clk_dsi0pll_shadow_n2_div_clk 0xd5f0dad9 +#define clk_dsi0pll_shadow_post_n1_div_clk 0x1f7c8cf8 +#define clk_dsi0pll_shadow_vco_clk 0xb100ca83 +#define clk_dsi1pll_shadow_byte_clk_src 0xfc021ce5 +#define clk_dsi1pll_shadow_pixel_clk_src 0xdcca3ffc +#define clk_dsi1pll_shadow_n2_div_clk 0x189541bf +#define clk_dsi1pll_shadow_post_n1_div_clk 0x1637020e +#define clk_dsi1pll_shadow_vco_clk 0x68d8b6f7 + +/* CPU clocks */ +#define clk_pwrcl_clk 0xc554130e +#define clk_pwrcl_pll 0x25454ca1 +#define clk_pwrcl_alt_pll 0xc445471b +#define clk_pwrcl_pll_main 0x28948e22 +#define clk_pwrcl_alt_pll_main 0x25c8270e +#define clk_pwrcl_hf_mux 0x77706ae6 +#define clk_pwrcl_lf_mux 0xd99e334d +#define clk_perfcl_clk 0x58869997 +#define clk_perfcl_pll 0x97dcec1c +#define clk_perfcl_alt_pll 0xfe2eaea1 +#define clk_perfcl_pll_main 0x0dbf0c0b +#define clk_perfcl_alt_pll_main 0x0b892aab +#define clk_perfcl_hf_mux 0x9e8bbe59 +#define clk_perfcl_lf_mux 0x2f9c278d +#define clk_cbf_pll 0xfe2e96a3 +#define clk_cbf_pll_main 0x2b05cf95 +#define clk_cbf_hf_mux 0x71244f73 +#define clk_cbf_clk 0x48e9e16b +#define clk_xo_ao 0x428c856d +#define clk_sys_apcsaux_clk 0x0b0dd513 +#define clk_cpu_debug_mux 0xc7acaa31 + +/* GCC block resets */ +#define QUSB2PHY_PRIM_BCR 0 +#define QUSB2PHY_SEC_BCR 1 +#define BLSP1_BCR 2 +#define BLSP2_BCR 3 +#define BOOT_ROM_BCR 4 +#define PRNG_BCR 5 +#define UFS_BCR 6 +#define USB_20_BCR 7 +#define USB_30_BCR 8 +#define USB3_PHY_BCR 9 +#define USB3PHY_PHY_BCR 10 +#define PCIE_0_PHY_BCR 11 +#define PCIE_1_PHY_BCR 12 +#define PCIE_2_PHY_BCR 13 +#define PCIE_PHY_BCR 14 +#define PCIE_PHY_COM_BCR 15 +#define PCIE_PHY_NOCSR_COM_PHY_BCR 16 + +/* MMSS Block resets */ +#define VIDEO_BCR 0 +#define MDSS_BCR 1 +#define CAMSS_MICRO_BCR 2 +#define CAMSS_JPEG_BCR 3 +#define CAMSS_VFE0_BCR 4 +#define CAMSS_VFE1_BCR 5 +#define FD_BCR 6 +#define GPU_GX_BCR 7 + +#endif --- /dev/null 2019-10-24 16:47:25.704025805 +0200 +++ linux-4.4.115-fbx/arch/powerpc/boot/dts/include/dt-bindings/clock/msm-clocks-8998.h 2019-01-22 16:16:28.171288678 +0100 @@ -0,0 +1,534 @@ +/* Copyright (c) 2015-2017, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __MSM_CLOCKS_8998_H +#define __MSM_CLOCKS_8998_H + +#include "audio-ext-clk.h" + +/* clock_rpm controlled clocks */ +#define clk_ce1_clk 0x42229c55 +#define clk_ce1_a_clk 0x44a833fe +#define clk_cxo_clk_src 0x79e95308 +#define clk_bimc_clk 0x4b80bf00 +#define clk_bimc_a_clk 0x4b25668a +#define clk_cnoc_clk 0xd5ccb7f4 +#define clk_cnoc_a_clk 0xd8fe2ccc +#define clk_snoc_clk 0x2c341aa0 +#define clk_snoc_a_clk 0x8fcef2af +#define clk_cnoc_periph_clk 0xb11e9cf9 +#define clk_cnoc_periph_a_clk 0x1d7faa2e +#define clk_cnoc_periph_keepalive_a_clk 0x7287aef2 +#define clk_ln_bb_clk1 0xb867b147 +#define clk_ln_bb_clk1_ao 0x7f63a93a +#define clk_ln_bb_clk1_pin 0x6fc5653c +#define clk_ln_bb_clk1_pin_ao 0x25d625bf +#define clk_ln_bb_clk2 0xf83e6387 +#define clk_ln_bb_clk2_ao 0x96f09628 +#define clk_ln_bb_clk2_pin 0xa9ebe8d5 +#define clk_ln_bb_clk2_pin_ao 0x89a1226f +#define clk_ln_bb_clk3 0x4f52a39e +#define clk_ln_bb_clk3_ao 0xb15eba76 +#define clk_ln_bb_clk3_pin 0xc4de7dad +#define clk_ln_bb_clk3_pin_ao 0xc01022e8 +#define clk_bimc_msmbus_clk 0xd212feea +#define clk_bimc_msmbus_a_clk 0x71d1a499 +#define clk_cnoc_msmbus_clk 0x62228b5d +#define clk_cnoc_msmbus_a_clk 0x67442955 +#define clk_cxo_clk_src_ao 0x64eb6004 +#define clk_cxo_dwc3_clk 0xf79c19f6 +#define clk_cxo_lpm_clk 0x94adbf3d +#define clk_cxo_otg_clk 0x4eec0bb9 +#define clk_cxo_pil_lpass_clk 0xe17f0ff6 +#define clk_cxo_pil_ssc_clk 0x81832015 +#define clk_cxo_pil_spss_clk 0x5cd71a61 +#define clk_div_clk1 0xaa1157a6 +#define clk_div_clk1_ao 0x6b943d68 +#define clk_div_clk2 0xd454019f +#define clk_div_clk2_ao 0x53f9e788 +#define clk_div_clk3 0xa9a55a68 +#define clk_div_clk3_ao 0x3d6725a8 +#define clk_ipa_clk 0xfa685cda +#define clk_ipa_a_clk 0xeeec2919 +#define clk_mcd_ce1_clk 0xbb615d26 +#define clk_mmssnoc_axi_clk 0xdb4b31e6 +#define clk_mmssnoc_axi_a_clk 0xd4970614 +#define clk_qcedev_ce1_clk 0x293f97b0 +#define clk_qcrypto_ce1_clk 0xa6ac14df +#define clk_qdss_clk 0x1492202a +#define clk_qdss_a_clk 0xdd121669 +#define clk_qseecom_ce1_clk 0xaa858373 +#define clk_rf_clk1 0xaabeea5a +#define clk_rf_clk1_ao 0x72a10cb8 +#define clk_rf_clk1_pin 0x8f463562 +#define clk_rf_clk1_pin_ao 0x62549ff6 +#define clk_rf_clk2 0x24a30992 +#define clk_rf_clk2_ao 0x944d8bbd +#define clk_rf_clk2_pin 0xa7c5602a +#define clk_rf_clk2_pin_ao 0x2d75eb4d +#define clk_rf_clk3 0xb673936b +#define clk_rf_clk3_ao 0x038bb968 +#define clk_rf_clk3_pin 0x726f53f5 +#define clk_rf_clk3_pin_ao 0x76f9240f +#define clk_scm_ce1_clk 0xd8ebcc62 +#define clk_snoc_msmbus_clk 0xe6900bb6 +#define clk_snoc_msmbus_a_clk 0x5d4683bd +#define clk_gcc_ce1_ahb_m_clk 0x2eb28c01 +#define clk_gcc_ce1_axi_m_clk 0xc174dfba +#define clk_aggre1_noc_clk 0x049abba8 +#define clk_aggre1_noc_a_clk 0xc12e4220 +#define clk_aggre2_noc_clk 0xaa681404 +#define clk_aggre2_noc_a_clk 0xcab67089 +#define clk_measure_only_bimc_hmss_axi_clk 0xc1cc4f11 + +/* clock_gcc controlled clocks*/ +#define clk_debug_mmss_clk 0x977c99b6 +#define clk_debug_rpm_clk 0x8e2b07ca +#define clk_debug_cpu_clk 0x0e696b2b +#define clk_gpu_gcc_debug_clk 0x3eb88190 +#define clk_gfx_gcc_debug_clk 0xa3a64fec +#define clk_gpll0 0x1ebe3bc4 +#define clk_gpll0_out_main 0xe9374de7 +#define clk_gpll0_ao 0xa1368304 +#define clk_gcc_mmss_gpll0_clk 0x8050f008 +#define clk_gcc_mmss_gpll0_div_clk 0xdd06848d +#define clk_gcc_gpu_gpll0_clk 0xdad7a7a4 +#define clk_gcc_gpu_gpll0_div_clk 0x07d16c6a +#define clk_gpll4 0xb3b5d85b +#define clk_gpll4_out_main 0xa9a0ab9d +#define clk_usb30_master_clk_src 0xc6262f89 +#define clk_pcie_aux_clk_src 0xebc50566 +#define clk_ufs_axi_clk_src 0x297ca380 +#define clk_blsp1_qup1_i2c_apps_clk_src 0x17f78f5e +#define clk_blsp1_qup1_spi_apps_clk_src 0xf534c4fa +#define clk_blsp1_qup2_i2c_apps_clk_src 0x8de71c79 +#define clk_blsp1_qup2_spi_apps_clk_src 0x33cf809a +#define clk_blsp1_qup3_i2c_apps_clk_src 0xf161b902 +#define clk_blsp1_qup3_spi_apps_clk_src 0x5e95683f +#define clk_blsp1_qup4_i2c_apps_clk_src 0xb2ecce68 +#define clk_blsp1_qup4_spi_apps_clk_src 0xddb5bbdb +#define clk_blsp1_qup5_i2c_apps_clk_src 0x71ea7804 +#define clk_blsp1_qup5_spi_apps_clk_src 0x9752f35f +#define clk_blsp1_qup6_i2c_apps_clk_src 0x28806803 +#define clk_blsp1_qup6_spi_apps_clk_src 0x44a1edc4 +#define clk_blsp1_uart1_apps_clk_src 0xf8146114 +#define clk_blsp1_uart2_apps_clk_src 0xfc9c2f73 +#define clk_blsp1_uart3_apps_clk_src 0x600497f2 +#define clk_blsp2_qup1_i2c_apps_clk_src 0xd6d1e95d +#define clk_blsp2_qup1_spi_apps_clk_src 0xcc1b8365 +#define clk_blsp2_qup2_i2c_apps_clk_src 0x603b5c51 +#define clk_blsp2_qup2_spi_apps_clk_src 0xd577dc44 +#define clk_blsp2_qup3_i2c_apps_clk_src 0xea82959c +#define clk_blsp2_qup3_spi_apps_clk_src 0xd04b1e92 +#define clk_blsp2_qup4_i2c_apps_clk_src 0x73dc968c +#define clk_blsp2_qup4_spi_apps_clk_src 0x25d4a2b1 +#define clk_blsp2_qup5_i2c_apps_clk_src 0xcc3698bd +#define clk_blsp2_qup5_spi_apps_clk_src 0xfa0cf45e +#define clk_blsp2_qup6_i2c_apps_clk_src 0x2fa53151 +#define clk_blsp2_qup6_spi_apps_clk_src 0x5ca86755 +#define clk_blsp2_uart1_apps_clk_src 0x562c66dc +#define clk_blsp2_uart2_apps_clk_src 0xdd448080 +#define clk_blsp2_uart3_apps_clk_src 0x46b2e90f +#define clk_gp1_clk_src 0xad85b97a +#define clk_gp2_clk_src 0xfb1f0065 +#define clk_gp3_clk_src 0x63b693d6 +#define clk_hmss_rbcpr_clk_src 0xedd9a474 +#define clk_pdm2_clk_src 0x31e494fd +#define clk_sdcc2_apps_clk_src 0xfc46c821 +#define clk_sdcc4_apps_clk_src 0x7aaaaa0c +#define clk_tsif_ref_clk_src 0x4e9042d1 +#define clk_ufs_ice_core_clk_src 0xda8e7119 +#define clk_ufs_phy_aux_clk_src 0xc6bca085 +#define clk_ufs_unipro_core_clk_src 0x179e80a9 +#define clk_usb30_mock_utmi_clk_src 0xa024a976 +#define clk_usb3_phy_aux_clk_src 0x15eec63c +#define clk_qspi_ref_clk_src 0xfe6b8e11 +#define clk_gcc_pcie_phy_0_reset 0x6bb4df33 +#define clk_gcc_usb3_phy_reset 0x03d559f1 +#define clk_gcc_usb3phy_phy_reset 0xb1a4f885 +#define clk_gcc_aggre1_ufs_axi_clk 0x873459d8 +#define clk_gcc_aggre1_ufs_axi_hw_ctl_clk 0x117a6f39 +#define clk_gcc_aggre1_usb3_axi_clk 0xc5c3fbe8 +#define clk_gcc_bimc_mss_q6_axi_clk 0x7437988f +#define clk_gcc_blsp1_ahb_clk 0x8caa5b4f +#define clk_gcc_blsp1_qup1_i2c_apps_clk 0xc303fae9 +#define clk_gcc_blsp1_qup1_spi_apps_clk 0x759a76b0 +#define clk_gcc_blsp1_qup2_i2c_apps_clk 0x1076f220 +#define clk_gcc_blsp1_qup2_spi_apps_clk 0x3e77d48f +#define clk_gcc_blsp1_qup3_i2c_apps_clk 0x9e25ac82 +#define clk_gcc_blsp1_qup3_spi_apps_clk 0xfb978880 +#define clk_gcc_blsp1_qup4_i2c_apps_clk 0xd7f40f6f +#define clk_gcc_blsp1_qup4_spi_apps_clk 0x80f8722f +#define clk_gcc_blsp1_qup5_i2c_apps_clk 0xacae5604 +#define clk_gcc_blsp1_qup5_spi_apps_clk 0xbf3e15d7 +#define clk_gcc_blsp1_qup6_i2c_apps_clk 0x5c6ad820 +#define clk_gcc_blsp1_qup6_spi_apps_clk 0x780d9f85 +#define clk_gcc_blsp1_uart1_apps_clk 0xc7c62f90 +#define clk_gcc_blsp1_uart2_apps_clk 0xf8a61c96 +#define clk_gcc_blsp1_uart3_apps_clk 0xc3298bd7 +#define clk_gcc_blsp2_ahb_clk 0x8f283c1d +#define clk_gcc_blsp2_qup1_i2c_apps_clk 0x9ace11dd +#define clk_gcc_blsp2_qup1_spi_apps_clk 0xa32604cc +#define clk_gcc_blsp2_qup2_i2c_apps_clk 0x1bf9a57e +#define clk_gcc_blsp2_qup2_spi_apps_clk 0xbf54ca6d +#define clk_gcc_blsp2_qup3_i2c_apps_clk 0x336d4170 +#define clk_gcc_blsp2_qup3_spi_apps_clk 0xc68509d6 +#define clk_gcc_blsp2_qup4_i2c_apps_clk 0xbd22539d +#define clk_gcc_blsp2_qup4_spi_apps_clk 0x01a72b93 +#define clk_gcc_blsp2_qup5_i2c_apps_clk 0xe2b2ce1d +#define clk_gcc_blsp2_qup5_spi_apps_clk 0xf40999cd +#define clk_gcc_blsp2_qup6_i2c_apps_clk 0x894bcea4 +#define clk_gcc_blsp2_qup6_spi_apps_clk 0xfe1bd34a +#define clk_gcc_blsp2_uart1_apps_clk 0x8c3512ff +#define clk_gcc_blsp2_uart2_apps_clk 0x1e1965a3 +#define clk_gcc_blsp2_uart3_apps_clk 0x382415ab +#define clk_gcc_boot_rom_ahb_clk 0xde2adeb1 +#define clk_gcc_bimc_gfx_clk 0x3edd69ad +#define clk_gcc_cfg_noc_usb3_axi_clk 0x9ea4c2d9 +#define clk_gcc_gp1_clk 0x057f7b69 +#define clk_gcc_gp2_clk 0x9bf83ffd +#define clk_gcc_gp3_clk 0xec6539ee +#define clk_gcc_gpu_bimc_gfx_clk 0x3909459b +#define clk_gcc_gpu_cfg_ahb_clk 0x72f20a57 +#define clk_gcc_gpu_iref_clk 0xfd82abad +#define clk_gcc_hmss_dvm_bus_clk 0x17cc8b53 +#define clk_gcc_hmss_rbcpr_clk 0x699183be +#define clk_hmss_gpll0_clk_src 0x17eb05d0 +#define clk_hmss_gpll4_clk_src 0x20456cae +#define clk_gcc_mmss_sys_noc_axi_clk 0x4467b15b +#define clk_gcc_mss_at_clk 0x1692c5aa +#define clk_nav_gcc_dbg_clk 0x2221c544 +#define clk_gcc_pcie_0_aux_clk 0x3d2e3ece +#define clk_gcc_pcie_0_cfg_ahb_clk 0x4dd325c3 +#define clk_gcc_pcie_0_mstr_axi_clk 0x3f85285b +#define clk_gcc_pcie_0_pipe_clk 0x4f37621e +#define clk_gcc_pcie_0_slv_axi_clk 0xd69638a1 +#define clk_gcc_pcie_phy_aux_clk 0x4746e74f +#define clk_gcc_pdm2_clk 0x99d55711 +#define clk_gcc_pdm_ahb_clk 0x365664f6 +#define clk_gcc_prng_ahb_clk 0x397e7eaa +#define clk_gcc_sdcc2_ahb_clk 0x23d5727f +#define clk_gcc_sdcc2_apps_clk 0x861b20ac +#define clk_gcc_sdcc4_ahb_clk 0x64f3e6a8 +#define clk_gcc_sdcc4_apps_clk 0xbf7c4dc8 +#define clk_gcc_tsif_ahb_clk 0x88d2822c +#define clk_gcc_tsif_ref_clk 0x8f1ed2c2 +#define clk_gcc_ufs_ahb_clk 0x1914bb84 +#define clk_gcc_ufs_axi_clk 0x47c743a7 +#define clk_gcc_ufs_axi_hw_ctl_clk 0x69385b45 +#define clk_gcc_ufs_ice_core_clk 0x310b0710 +#define clk_gcc_ufs_ice_core_hw_ctl_clk 0x84e15a5b +#define clk_gcc_ufs_phy_aux_clk 0x17acc8fb +#define clk_gcc_ufs_phy_aux_hw_ctl_clk 0x7dbdb2e2 +#define clk_gcc_ufs_rx_symbol_0_clk 0x7f43251c +#define clk_gcc_ufs_rx_symbol_1_clk 0x03182fde +#define clk_gcc_ufs_tx_symbol_0_clk 0x6a9f747a +#define clk_ufs_tx_symbol_0_clk 0xb3fcd0f7 +#define clk_ufs_rx_symbol_0_clk 0x17a0f1cd +#define clk_gcc_ufs_unipro_core_clk 0x2daf7fd2 +#define clk_gcc_ufs_unipro_core_hw_ctl_clk 0x4a4e0f3d +#define clk_gcc_usb30_master_clk 0xb3b4e2cb +#define clk_gcc_usb30_mock_utmi_clk 0xa800b65a +#define clk_gcc_usb30_sleep_clk 0xd0b65c92 +#define clk_gcc_usb3_phy_aux_clk 0x0d9a36e0 +#define clk_gcc_usb3_phy_pipe_clk 0xf279aff2 +#define clk_gcc_usb3_clkref_clk 0xb6cc8f00 +#define clk_gcc_hdmi_clkref_clk 0x4d4eec04 +#define clk_gcc_edp_clkref_clk 0xa8685c3f +#define clk_gcc_ufs_clkref_clk 0x92aa126f +#define clk_gcc_pcie_clkref_clk 0xa2e247fa +#define clk_gcc_rx2_qlink_clkref_clk 0xd0ba986d +#define clk_gcc_rx1_usb2_clkref_clk 0x53351d25 +#define clk_gcc_pcie_phy_reset 0x9bc3c959 +#define clk_gcc_pcie_phy_com_reset 0x8bf513e6 +#define clk_gcc_pcie_phy_nocsr_com_phy_reset 0x0c16a2da +#define clk_gcc_qusb2phy_prim_reset 0x07550fa1 +#define clk_gcc_qusb2phy_sec_reset 0x3f3a87d0 +#define clk_gcc_mmss_noc_cfg_ahb_clk 0xb41a9d99 +#define clk_gcc_dcc_ahb_clk 0xfa14a88c +#define clk_hlos1_vote_lpass_core_smmu_clk 0x3aaa1743 +#define clk_hlos1_vote_lpass_adsp_smmu_clk 0xc76f702f +#define clk_gcc_mss_cfg_ahb_clk 0x111cde81 +#define clk_gcc_mss_q6_bimc_axi_clk 0x67544d62 +#define clk_gcc_mss_mnoc_bimc_axi_clk 0xf665d03f +#define clk_gpll0_out_msscc 0x7d794829 +#define clk_gcc_mss_snoc_axi_clk 0x0e71de85 +#define clk_gcc_qspi_ref_clk 0x766a0f7c +#define clk_gcc_qspi_ahb_clk 0x96969dc8 +#define clk_gcc_debug_mux 0x8121ac15 + +/* clock_mmss controlled clocks */ +#define clk_mmsscc_xo 0x05e63704 +#define clk_mmsscc_gpll0 0xe900c515 +#define clk_mmsscc_gpll0_div 0x73892e05 +#define clk_mmpll0_pll 0x361e3cfd +#define clk_mmpll1_pll 0x198e426b +#define clk_mmpll3_pll 0x18c76899 +#define clk_mmpll4_pll 0x22c063c1 +#define clk_mmpll5_pll 0xa41e1936 +#define clk_mmpll6_pll 0xc56fb440 +#define clk_mmpll7_pll 0x3ac216af +#define clk_mmpll10_pll 0x2561263b +#define clk_mmpll0_pll_out 0x1e9e24a8 +#define clk_mmpll1_pll_out 0x5fa32257 +#define clk_mmpll3_pll_out 0x6eb6328f +#define clk_mmpll4_pll_out 0xfb21c2fd +#define clk_mmpll5_pll_out 0xcc1897bf +#define clk_mmpll6_pll_out 0xfb1060bd +#define clk_mmpll7_pll_out 0x767758ed +#define clk_mmpll10_pll_out 0x3c5668f3 +#define clk_ahb_clk_src 0x86f49203 +#define clk_csi0_clk_src 0x227e65bc +#define clk_vfe0_clk_src 0xa0c2bd8f +#define clk_vfe1_clk_src 0x4e357366 +#define clk_mdp_clk_src 0x6dc1f8f1 +#define clk_maxi_clk_src 0x52c09777 +#define clk_cpp_clk_src 0x8382f56d +#define clk_jpeg0_clk_src 0x9a0a0ac3 +#define clk_rot_clk_src 0xce49b56c +#define clk_video_core_clk_src 0x8be4c944 +#define clk_csi1_clk_src 0x6a2a6c36 +#define clk_csi2_clk_src 0x4113589f +#define clk_csi3_clk_src 0xfd934012 +#define clk_fd_core_clk_src 0xe4799ab7 +#define clk_ext_dp_phy_pll_vco 0x441b576b +#define clk_ext_dp_phy_pll_link 0xea12644c +#define clk_dp_link_clk_src 0x370d0626 +#define clk_dp_crypto_clk_src 0xf8faa811 +#define clk_dp_pixel_clk_src 0xf5dfbabf +#define clk_ext_extpclk_clk_src 0xe5b273af +#define clk_ext_pclk0_clk_src 0x087c1612 +#define clk_ext_pclk1_clk_src 0x8067c5a3 +#define clk_pclk0_clk_src 0xccac1f35 +#define clk_pclk1_clk_src 0x090f68ac +#define clk_video_subcore0_clk_src 0x88d79636 +#define clk_video_subcore1_clk_src 0x4966930c +#define clk_cci_clk_src 0x822f3d97 +#define clk_camss_gp0_clk_src 0x43b063e9 +#define clk_camss_gp1_clk_src 0xa3315f1b +#define clk_mclk0_clk_src 0x266b3853 +#define clk_mclk1_clk_src 0xa73cad0c +#define clk_mclk2_clk_src 0x42545468 +#define clk_mclk3_clk_src 0x2bfbb714 +#define clk_csiphy_clk_src 0x8cceb70a +#define clk_csi0phytimer_clk_src 0xc8a309be +#define clk_csi1phytimer_clk_src 0x7c0fe23a +#define clk_csi2phytimer_clk_src 0x62ffea9c +#define clk_ext_byte0_clk_src 0xfb32f31e +#define clk_ext_byte1_clk_src 0x585ef6d4 +#define clk_byte0_clk_src 0x75cc885b +#define clk_byte1_clk_src 0x63c2c955 +#define clk_dp_aux_clk_src 0x2b6e972b +#define clk_dp_gtc_clk_src 0xc5a86a42 +#define clk_esc0_clk_src 0xb41d7c38 +#define clk_esc1_clk_src 0x3b0afa42 +#define clk_extpclk_clk_src 0xb2c31abd +#define clk_hdmi_clk_src 0xb40aeea9 +#define clk_vsync_clk_src 0xecb43940 +#define clk_mmss_bimc_smmu_ahb_clk 0x4825baf4 +#define clk_mmss_bimc_smmu_axi_clk 0xc365ac39 +#define clk_mmss_snoc_dvm_axi_clk 0x2c159a11 +#define clk_mmss_camss_ahb_clk 0xa51f2c1d +#define clk_mmss_camss_cci_ahb_clk 0xfda8bb6a +#define clk_mmss_camss_cci_clk 0x71bb5c97 +#define clk_mmss_camss_cpp_ahb_clk 0xd5554f15 +#define clk_mmss_camss_cpp_clk 0x8e99ef57 +#define clk_mmss_camss_cpp_axi_clk 0xd84e390b +#define clk_mmss_camss_cpp_vbif_ahb_clk 0x1b33a88e +#define clk_mmss_camss_cphy_csid0_clk 0x56114361 +#define clk_mmss_camss_csi0_ahb_clk 0x2b58d241 +#define clk_mmss_camss_csi0_clk 0xccfe39ef +#define clk_mmss_camss_csi0pix_clk 0x9e26509d +#define clk_mmss_camss_csi0rdi_clk 0x01d5bf83 +#define clk_mmss_camss_cphy_csid1_clk 0x79fbcd8a +#define clk_mmss_camss_csi1_ahb_clk 0x7073244b +#define clk_mmss_camss_csi1_clk 0x3eeeaac0 +#define clk_mmss_camss_csi1pix_clk 0xf1375139 +#define clk_mmss_camss_csi1rdi_clk 0x43185024 +#define clk_mmss_camss_cphy_csid2_clk 0xf295e3ef +#define clk_mmss_camss_csi2_ahb_clk 0x681c1479 +#define clk_mmss_camss_csi2_clk 0x94524569 +#define clk_mmss_camss_csi2pix_clk 0xf4de617d +#define clk_mmss_camss_csi2rdi_clk 0x4bf01dc5 +#define clk_mmss_camss_cphy_csid3_clk 0x100188e9 +#define clk_mmss_camss_csi3_ahb_clk 0xfae7c29b +#define clk_mmss_camss_csi3_clk 0x55e4bbae +#define clk_mmss_camss_csi3pix_clk 0xc166a015 +#define clk_mmss_camss_csi3rdi_clk 0x6983a4cd +#define clk_mmss_camss_csi_vfe0_clk 0x3b30b798 +#define clk_mmss_camss_csi_vfe1_clk 0xfe729af7 +#define clk_mmss_camss_csiphy0_clk 0x96c81af8 +#define clk_mmss_camss_csiphy1_clk 0xee9ac2bb +#define clk_mmss_camss_csiphy2_clk 0x3365e70e +#define clk_mmss_fd_ahb_clk 0x4ff1da4d +#define clk_mmss_fd_core_clk 0x749e7eb0 +#define clk_mmss_fd_core_uar_clk 0x8ea480c5 +#define clk_mmss_camss_gp0_clk 0x3f7f6c87 +#define clk_mmss_camss_gp1_clk 0xdccdd730 +#define clk_mmss_camss_ispif_ahb_clk 0xbda4f0e3 +#define clk_mmss_camss_jpeg0_clk 0x4cc73b07 +#define clk_mmss_camss_jpeg0_vote_clk 0xc9efa6ac +#define clk_mmss_camss_jpeg0_dma_vote_clk 0x371ec109 +#define clk_mmss_camss_jpeg_ahb_clk 0xde1fece3 +#define clk_mmss_camss_jpeg_axi_clk 0x7534616b +#define clk_mmss_camss_mclk0_clk 0x056293a7 +#define clk_mmss_camss_mclk1_clk 0x96c7b69b +#define clk_mmss_camss_mclk2_clk 0x8820556e +#define clk_mmss_camss_mclk3_clk 0xf90ffb67 +#define clk_mmss_camss_micro_ahb_clk 0x6c6fd3c7 +#define clk_mmss_camss_csi0phytimer_clk 0x7a78864e +#define clk_mmss_camss_csi1phytimer_clk 0x6e6c1de5 +#define clk_mmss_camss_csi2phytimer_clk 0x0235e2de +#define clk_mmss_camss_top_ahb_clk 0x120618d6 +#define clk_mmss_camss_vfe0_ahb_clk 0x137bd0bd +#define clk_mmss_camss_vfe0_clk 0xead28288 +#define clk_mmss_camss_vfe0_stream_clk 0xa0428287 +#define clk_mmss_camss_vfe1_ahb_clk 0xac0154c0 +#define clk_mmss_camss_vfe1_clk 0xc216b14d +#define clk_mmss_camss_vfe1_stream_clk 0x745af3b6 +#define clk_mmss_camss_vfe_vbif_ahb_clk 0x0109a9c6 +#define clk_mmss_camss_vfe_vbif_axi_clk 0xe626d8a1 +#define clk_mmss_mdss_ahb_clk 0x85d37ab5 +#define clk_mmss_mdss_axi_clk 0xdf04fc1d +#define clk_mmss_mdss_byte0_clk 0x38105d25 +#define clk_mmss_mdss_byte0_intf_clk 0x38e5aa79 +#define clk_mmss_mdss_byte0_intf_div_clk 0x8604f181 +#define clk_mmss_mdss_byte1_clk 0xe0c21354 +#define clk_mmss_mdss_byte1_intf_clk 0xcf654d8e +#define clk_mmss_mdss_byte1_intf_div_clk 0xcdf334c5 +#define clk_mmss_mdss_dp_aux_clk 0x23125eb6 +#define clk_mmss_mdss_dp_crypto_clk 0x9a072d4e +#define clk_mmss_mdss_dp_link_clk 0x8dd302d1 +#define clk_mmss_mdss_dp_link_intf_clk 0x70e386e6 +#define clk_mmss_mdss_dp_pixel_clk 0xb707b765 +#define clk_mmss_mdss_dp_gtc_clk 0xb59c151a +#define clk_mmss_mdss_esc0_clk 0x5721ff83 +#define clk_mmss_mdss_esc1_clk 0xc3d0376b +#define clk_mmss_mdss_extpclk_clk 0x74d5a954 +#define clk_mmss_mdss_hdmi_clk 0x28460a6d +#define clk_mmss_mdss_hdmi_dp_ahb_clk 0x5448519f +#define clk_mmss_mdss_mdp_clk 0x43539b0e +#define clk_mmss_mdss_mdp_lut_clk 0x00627b2b +#define clk_mmss_mdss_pclk0_clk 0xcc0e909d +#define clk_mmss_mdss_pclk1_clk 0x850d9146 +#define clk_mmss_mdss_rot_clk 0xbb7e71c4 +#define clk_mmss_mdss_vsync_clk 0x629b36dc +#define clk_mmss_misc_ahb_clk 0xea30b0e7 +#define clk_mmss_misc_cxo_clk 0xe620cd80 +#define clk_mmss_mnoc_ahb_clk 0x49a394f4 +#define clk_mmss_mnoc_maxi_clk 0xd8b7278f +#define clk_mmss_video_subcore0_clk 0x23fae359 +#define clk_mmss_video_subcore1_clk 0x5213a0c7 +#define clk_mmss_video_ahb_clk 0x94334ae9 +#define clk_mmss_video_axi_clk 0xf3178ba5 +#define clk_mmss_video_core_clk 0x78f14c85 +#define clk_mmss_video_maxi_clk 0x1785ef88 +#define clk_mmss_vmem_ahb_clk 0x4b18955b +#define clk_mmss_vmem_maxi_clk 0xb6067889 +#define clk_mmss_debug_mux 0xe646ffda + +/* external multimedia clocks */ +#define clk_dsi0pll_byteclk_mux 0xecf2c434 +#define clk_dsi0pll_byteclk_src 0x6f6f740f +#define clk_dsi0pll_pclk_mux 0x6c9da335 +#define clk_dsi0pll_pclk_src 0x5efd85d4 +#define clk_dsi0pll_pclk_src_mux 0x84b14663 +#define clk_dsi0pll_post_bit_div 0xf46dcf27 +#define clk_dsi0pll_pll_out_div1 0xeda5b7fe +#define clk_dsi0pll_pll_out_div2 0x97fa476d +#define clk_dsi0pll_pll_out_div4 0x90a98ce0 +#define clk_dsi0pll_pll_out_div8 0x9d9d85cf +#define clk_dsi0pll_pll_out_mux 0x179c27ca +#define clk_dsi0pll_post_vco_mux 0xfaf9bd1f +#define clk_dsi0pll_post_vco_div1 0xabb50b2a +#define clk_dsi0pll_post_vco_div4 0xbe51c091 +#define clk_dsi0pll_bitclk_src 0x36c3c437 +#define clk_dsi0pll_vco_clk 0x15940d40 + +#define clk_dsi1pll_byteclk_mux 0x14e2f38f +#define clk_dsi1pll_byteclk_src 0x4b65c298 +#define clk_dsi1pll_pclk_mux 0x4c0518b5 +#define clk_dsi1pll_pclk_src 0xeddcd80e +#define clk_dsi1pll_pclk_src_mux 0x3651feb3 +#define clk_dsi1pll_post_bit_div 0x712f0260 +#define clk_dsi1pll_pll_out_div8 0x87628ddb +#define clk_dsi1pll_pll_out_div4 0x0d9a384b +#define clk_dsi1pll_pll_out_div2 0x0c9b5748 +#define clk_dsi1pll_pll_out_div1 0x3193164e +#define clk_dsi1pll_pll_out_mux 0x171bf8fd +#define clk_dsi1pll_post_vco_mux 0xc6a90d20 +#define clk_dsi1pll_post_vco_div1 0x6f47ca7d +#define clk_dsi1pll_post_vco_div4 0x90628974 +#define clk_dsi1pll_bitclk_src 0x13ab045b +#define clk_dsi1pll_vco_clk 0x99797b50 + +#define clk_dp_vco_clk 0xfcaaeec7 +#define clk_dp_link_2x_clk_divsel_five 0xcfe3f5dd +#define clk_vco_divsel_four_clk_src 0xe0da19c0 +#define clk_vco_divsel_two_clk_src 0xb5cfc6a8 +#define clk_vco_divided_clk_src_mux 0x3f8197c2 +#define clk_hdmi_vco_clk 0xbb7dc20d + +/* clock_gpu controlled clocks*/ +#define clk_gpucc_xo 0xc4e1a890 +#define clk_gpucc_gpll0 0x0db0e37f +#define clk_gfx3d_clk_src 0x917f76ef +#define clk_rbbmtimer_clk_src 0x17649ecc +#define clk_gfx3d_isense_clk_src 0xecc3eafa +#define clk_rbcpr_clk_src 0x2c2e9af2 +#define clk_gpu_debug_div_clk 0x75d6f53f +#define clk_gpucc_gfx3d_clk 0x95f01bd5 +#define clk_gpucc_rbbmtimer_clk 0x58a0a7ca +#define clk_gpucc_gfx3d_isense_clk 0xb2678e80 +#define clk_gpucc_cxo_clk 0x6532dcae +#define clk_gpucc_rbcpr_clk 0x7bd750e8 +#define clk_gpu_pll0_pll 0x0e61ab4d +#define clk_gpu_pll0_pll_out_even 0xb0ed5009 +#define clk_gpu_pll0_pll_out_odd 0x08c5a8a5 +#define clk_gpu_pll0_postdiv_clk 0x76c19f3c +#define clk_gpucc_mx_clk 0x1edbb879 +#define clk_gpucc_gcc_dbg_clk 0x9ae8cd3c +#define clk_gfxcc_dbg_clk 0x3ed47625 + +/* CPU clocks */ +#define clk_pwrcl_clk 0xc554130e +#define clk_perfcl_clk 0x58869997 +#define clk_sys_apcsaux_clk_gcc 0xf905e862 +#define clk_xo_ao 0x428c856d +#define clk_osm_clk_src 0xaabe68c3 +#define clk_cpu_debug_mux 0x3ae8bcb2 + +/* Audio External Clocks */ +#define clk_audio_ap_clk 0x9b5727cb +#define clk_audio_pmi_clk 0xcbfe416d +#define clk_audio_ap_clk2 0x454d1e91 + +/* GCC block resets */ +#define QUSB2PHY_PRIM_BCR 0 +#define QUSB2PHY_SEC_BCR 1 +#define BLSP1_BCR 2 +#define BLSP2_BCR 3 +#define BOOT_ROM_BCR 4 +#define PRNG_BCR 5 +#define UFS_BCR 6 +#define USB_30_BCR 7 +#define USB3_PHY_BCR 8 +#define USB3PHY_PHY_BCR 9 +#define PCIE_0_PHY_BCR 10 +#define PCIE_PHY_BCR 11 +#define PCIE_PHY_COM_BCR 12 +#define PCIE_PHY_NOCSR_COM_PHY_BCR 13 + +/* MMSS block resets */ +#define CAMSS_MICRO_BCR 0 + +#endif --- /dev/null 2019-10-24 16:47:25.704025805 +0200 +++ linux-4.4.115-fbx/arch/powerpc/boot/dts/include/dt-bindings/clock/msm-clocks-hwio-8998.h 2019-01-22 16:16:28.171288678 +0100 @@ -0,0 +1,395 @@ +/* Copyright (c) 2015-2017, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define CLKFLAG_NO_RATE_CACHE 0x00004000 + +#define FMAX_LOWER 0 +#define FMAX_LOW 1 +#define FMAX_NOM 2 +#define FMAX_TURBO 3 + +#define HALT_CHECK_DELAY 5 + +#define RPM_MISC_CLK_TYPE 0x306b6c63 +#define RPM_BUS_CLK_TYPE 0x316b6c63 +#define RPM_MEM_CLK_TYPE 0x326b6c63 +#define RPM_IPA_CLK_TYPE 0x617069 +#define RPM_CE_CLK_TYPE 0x6563 +#define RPM_AGGR_CLK_TYPE 0x72676761 +#define RPM_SMD_KEY_ENABLE 0x62616E45 +#define RPM_MMAXI_CLK_TYPE 0x69786d6d + +#define CXO_CLK_SRC_ID 0x0 +#define QDSS_CLK_ID 0x1 +#define SNOC_CLK_ID 0x1 +#define CNOC_CLK_ID 0x2 +#define CNOC_PERIPH_CLK_ID 0x0 +#define BIMC_CLK_ID 0x0 +#define IPA_CLK_ID 0x0 +#define CE1_CLK_ID 0x0 +#define RF_CLK1_ID 0x4 +#define RF_CLK2_ID 0x5 +#define RF_CLK3_ID 0x6 +#define LN_BB_CLK1_ID 0x1 +#define LN_BB_CLK2_ID 0x2 +#define LN_BB_CLK3_ID 0x3 +#define DIV_CLK1_ID 0xb +#define DIV_CLK2_ID 0xc +#define DIV_CLK3_ID 0xd +#define RF_CLK1_PIN_ID 0x4 +#define RF_CLK2_PIN_ID 0x5 +#define RF_CLK3_PIN_ID 0x6 +#define LN_BB_CLK1_PIN_ID 0x1 +#define LN_BB_CLK2_PIN_ID 0x2 +#define LN_BB_CLK3_PIN_ID 0x3 +#define AGGR1_NOC_ID 0x1 +#define AGGR2_NOC_ID 0x2 +#define MMSSNOC_AXI_CLK_ID 0x0 + +#define APCS_COMMON_LMH_CMD_RCGR 0x0012C + +#define GCC_APCS_GPLL_ENA_VOTE 0x52000 +#define GCC_APCS_CLOCK_BRANCH_ENA_VOTE 0x52004 +#define GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1 0x5200C +#define PLLTEST_PAD_CFG 0x6200C +#define GCC_XO_DIV4_CBCR 0x43008 +#define CLOCK_FRQ_MEASURE_CTL 0x62004 +#define CLOCK_FRQ_MEASURE_STATUS 0x62008 +#define GCC_GPLL0_MODE 0x00000 +#define GCC_GPLL4_MODE 0x77000 +#define GCC_USB30_MASTER_CMD_RCGR 0x0F014 +#define GCC_PCIE_AUX_CMD_RCGR 0x6C000 +#define GCC_UFS_AXI_CMD_RCGR 0x75018 +#define GCC_BLSP1_QUP1_I2C_APPS_CMD_RCGR 0x19020 +#define GCC_BLSP1_QUP1_SPI_APPS_CMD_RCGR 0x1900C +#define GCC_BLSP1_QUP2_I2C_APPS_CMD_RCGR 0x1B020 +#define GCC_BLSP1_QUP2_SPI_APPS_CMD_RCGR 0x1B00C +#define GCC_BLSP1_QUP3_I2C_APPS_CMD_RCGR 0x1D020 +#define GCC_BLSP1_QUP3_SPI_APPS_CMD_RCGR 0x1D00C +#define GCC_BLSP1_QUP4_I2C_APPS_CMD_RCGR 0x1F020 +#define GCC_BLSP1_QUP4_SPI_APPS_CMD_RCGR 0x1F00C +#define GCC_BLSP1_QUP5_I2C_APPS_CMD_RCGR 0x21020 +#define GCC_BLSP1_QUP5_SPI_APPS_CMD_RCGR 0x2100C +#define GCC_BLSP1_QUP6_I2C_APPS_CMD_RCGR 0x23020 +#define GCC_BLSP1_QUP6_SPI_APPS_CMD_RCGR 0x2300C +#define GCC_BLSP1_UART1_APPS_CMD_RCGR 0x1A00C +#define GCC_BLSP1_UART2_APPS_CMD_RCGR 0x1C00C +#define GCC_BLSP1_UART3_APPS_CMD_RCGR 0x1E00C +#define GCC_BLSP2_QUP1_I2C_APPS_CMD_RCGR 0x26020 +#define GCC_BLSP2_QUP2_I2C_APPS_CMD_RCGR 0x28020 +#define GCC_BLSP2_QUP3_I2C_APPS_CMD_RCGR 0x2A020 +#define GCC_BLSP2_QUP4_I2C_APPS_CMD_RCGR 0x2C020 +#define GCC_BLSP2_QUP5_I2C_APPS_CMD_RCGR 0x2E020 +#define GCC_BLSP2_QUP6_I2C_APPS_CMD_RCGR 0x30020 +#define GCC_BLSP2_QUP1_SPI_APPS_CMD_RCGR 0x2600C +#define GCC_BLSP2_QUP2_SPI_APPS_CMD_RCGR 0x2800C +#define GCC_BLSP2_QUP3_SPI_APPS_CMD_RCGR 0x2A00C +#define GCC_BLSP2_QUP4_SPI_APPS_CMD_RCGR 0x2C00C +#define GCC_BLSP2_QUP5_SPI_APPS_CMD_RCGR 0x2E00C +#define GCC_BLSP2_QUP6_SPI_APPS_CMD_RCGR 0x3000C +#define GCC_BLSP2_UART1_APPS_CMD_RCGR 0x2700C +#define GCC_BLSP2_UART2_APPS_CMD_RCGR 0x2900C +#define GCC_BLSP2_UART3_APPS_CMD_RCGR 0x2B00C +#define GCC_GP1_CMD_RCGR 0x64004 +#define GCC_GP2_CMD_RCGR 0x65004 +#define GCC_GP3_CMD_RCGR 0x66004 +#define GCC_HMSS_RBCPR_CMD_RCGR 0x48044 +#define GCC_PDM2_CMD_RCGR 0x33010 +#define GCC_SDCC2_APPS_CMD_RCGR 0x14010 +#define GCC_SDCC4_APPS_CMD_RCGR 0x16010 +#define GCC_TSIF_REF_CMD_RCGR 0x36010 +#define GCC_UFS_ICE_CORE_CMD_RCGR 0x76010 +#define GCC_UFS_PHY_AUX_CMD_RCGR 0x76044 +#define GCC_UFS_UNIPRO_CORE_CMD_RCGR 0x76028 +#define GCC_USB30_MOCK_UTMI_CMD_RCGR 0x0F028 +#define GCC_USB3_PHY_AUX_CMD_RCGR 0x5000C +#define GCC_QSPI_REF_CMD_RCGR 0x9000C +#define GCC_PCIE_0_PHY_BCR 0x6C01C +#define GCC_HDMI_CLKREF_EN 0x88000 +#define GCC_UFS_CLKREF_EN 0x88004 +#define GCC_USB3_CLKREF_EN 0x88008 +#define GCC_PCIE_CLKREF_EN 0x8800C +#define GCC_RX1_USB2_CLKREF_EN 0x88014 +#define GCC_USB3_PHY_BCR 0x50020 +#define GCC_AGGRE1_NOC_XO_CBCR 0x8202C +#define GCC_AGGRE1_UFS_AXI_CBCR 0x82028 +#define GCC_AGGRE1_USB3_AXI_CBCR 0x82024 +#define GCC_BIMC_MSS_Q6_AXI_CBCR 0x4401C +#define GCC_BLSP1_AHB_CBCR 0x17004 +#define GCC_BLSP1_BCR 0x17000 +#define GCC_BLSP1_QUP1_SPI_APPS_CBCR 0x19004 +#define GCC_BLSP1_QUP1_I2C_APPS_CBCR 0x19008 +#define GCC_BLSP1_QUP2_SPI_APPS_CBCR 0x1B004 +#define GCC_BLSP1_QUP2_I2C_APPS_CBCR 0x1B008 +#define GCC_BLSP1_QUP3_SPI_APPS_CBCR 0x1D004 +#define GCC_BLSP1_QUP3_I2C_APPS_CBCR 0x1D008 +#define GCC_BLSP1_QUP4_SPI_APPS_CBCR 0x1F004 +#define GCC_BLSP1_QUP4_I2C_APPS_CBCR 0x1F008 +#define GCC_BLSP1_QUP5_SPI_APPS_CBCR 0x21004 +#define GCC_BLSP1_QUP5_I2C_APPS_CBCR 0x21008 +#define GCC_BLSP1_QUP6_SPI_APPS_CBCR 0x23004 +#define GCC_BLSP1_QUP6_I2C_APPS_CBCR 0x23008 +#define GCC_BLSP1_UART1_APPS_CBCR 0x1A004 +#define GCC_BLSP1_UART2_APPS_CBCR 0x1C004 +#define GCC_BLSP1_UART3_APPS_CBCR 0x1E004 +#define GCC_BLSP2_AHB_CBCR 0x25004 +#define GCC_BLSP2_BCR 0x25000 +#define GCC_BLSP2_QUP1_SPI_APPS_CBCR 0x26004 +#define GCC_BLSP2_QUP1_I2C_APPS_CBCR 0x26008 +#define GCC_BLSP2_QUP2_I2C_APPS_CBCR 0x28008 +#define GCC_BLSP2_QUP2_SPI_APPS_CBCR 0x28004 +#define GCC_BLSP2_QUP3_SPI_APPS_CBCR 0x2A004 +#define GCC_BLSP2_QUP3_I2C_APPS_CBCR 0x2A008 +#define GCC_BLSP2_QUP4_SPI_APPS_CBCR 0x2C004 +#define GCC_BLSP2_QUP4_I2C_APPS_CBCR 0x2C008 +#define GCC_BLSP2_QUP5_SPI_APPS_CBCR 0x2E004 +#define GCC_BLSP2_QUP5_I2C_APPS_CBCR 0x2E008 +#define GCC_BLSP2_QUP6_SPI_APPS_CBCR 0x30004 +#define GCC_BLSP2_QUP6_I2C_APPS_CBCR 0x30008 +#define GCC_BLSP2_UART1_APPS_CBCR 0x27004 +#define GCC_BLSP2_UART2_APPS_CBCR 0x29004 +#define GCC_BLSP2_UART3_APPS_CBCR 0x2B004 +#define GCC_BOOT_ROM_AHB_CBCR 0x38004 +#define GCC_BOOT_ROM_BCR 0x38000 +#define GCC_CFG_NOC_USB3_AXI_CBCR 0x05018 +#define GCC_BIMC_GFX_CBCR 0x46040 +#define GCC_GP1_CBCR 0x64000 +#define GCC_GP2_CBCR 0x65000 +#define GCC_GP3_CBCR 0x66000 +#define GCC_GPU_BIMC_GFX_CBCR 0x71010 +#define GCC_GPU_CFG_AHB_CBCR 0x71004 +#define GCC_GPU_IREF_EN 0x88010 +#define GCC_HMSS_DVM_BUS_CBCR 0x4808C +#define GCC_HMSS_RBCPR_CBCR 0x48008 +#define GCC_MMSS_SYS_NOC_AXI_CBCR 0x09000 +#define GCC_MMSS_NOC_CFG_AHB_CBCR 0x09004 +#define GCC_PCIE_0_SLV_AXI_CBCR 0x6B008 +#define GCC_PCIE_0_MSTR_AXI_CBCR 0x6B00C +#define GCC_PCIE_0_CFG_AHB_CBCR 0x6B010 +#define GCC_PCIE_0_AUX_CBCR 0x6B014 +#define GCC_PCIE_0_PIPE_CBCR 0x6B018 +#define GCC_PCIE_PHY_AUX_CBCR 0x6F004 +#define GCC_PCIE_PHY_BCR 0x6F000 +#define GCC_PCIE_PHY_COM_BCR 0x6F014 +#define GCC_PCIE_PHY_NOCSR_COM_PHY_BCR 0x6F00C +#define GCC_QUSB2PHY_PRIM_BCR 0x12000 +#define GCC_QUSB2PHY_SEC_BCR 0x12004 +#define GCC_PDM2_CBCR 0x3300C +#define GCC_PDM_AHB_CBCR 0x33004 +#define GCC_PRNG_AHB_CBCR 0x34004 +#define GCC_PRNG_BCR 0x34000 +#define GCC_SDCC2_APPS_CBCR 0x14004 +#define GCC_SDCC2_AHB_CBCR 0x14008 +#define GCC_SDCC4_APPS_CBCR 0x16004 +#define GCC_SDCC4_AHB_CBCR 0x16008 +#define GCC_TSIF_AHB_CBCR 0x36004 +#define GCC_TSIF_REF_CBCR 0x36008 +#define GCC_UFS_AXI_CBCR 0x75008 +#define GCC_UFS_BCR 0x75000 +#define GCC_UFS_AHB_CBCR 0x7500C +#define GCC_UFS_TX_SYMBOL_0_CBCR 0x75010 +#define GCC_UFS_RX_SYMBOL_0_CBCR 0x75014 +#define GCC_UFS_RX_SYMBOL_1_CBCR 0x7605C +#define GCC_UFS_UNIPRO_CORE_CBCR 0x76008 +#define GCC_UFS_ICE_CORE_CBCR 0x7600C +#define GCC_UFS_PHY_AUX_CBCR 0x76040 +#define GCC_USB30_MASTER_CBCR 0x0F008 +#define GCC_USB30_SLEEP_CBCR 0x0F00C +#define GCC_USB30_MOCK_UTMI_CBCR 0x0F010 +#define GCC_USB_30_BCR 0x0F000 +#define GCC_USB3_PHY_AUX_CBCR 0x50000 +#define GCC_USB3_PHY_PIPE_CBCR 0x50004 +#define GCC_USB3PHY_PHY_BCR 0x50024 +#define GCC_APCS_CLOCK_SLEEP_ENA_VOTE 0x52008 +#define GCC_MSS_CFG_AHB_CBCR 0x8A000 +#define GCC_MSS_Q6_BIMC_AXI_CBCR 0x8A040 +#define GCC_MSS_MNOC_BIMC_AXI_CBCR 0x8A004 +#define GCC_MSS_SNOC_AXI_CBCR 0x8A03C +#define GCC_HMSS_GPLL0_CMD_RCGR 0x4805C +#define GCC_MSS_CFG_AHB_CBCR 0x8A000 +#define GCC_MSS_Q6_BIMC_AXI_CBCR 0x8A040 +#define GCC_MSS_MNOC_BIMC_AXI_CBCR 0x8A004 +#define GCC_MSS_SNOC_AXI_CBCR 0x8A03C +#define GCC_DCC_AHB_CBCR 0x84004 +#define GCC_HLOS1_VOTE_LPASS_CORE_SMMU_CBCR 0x7D010 +#define GCC_HLOS1_VOTE_LPASS_ADSP_SMMU_CBCR 0x7D014 +#define GCC_QSPI_AHB_CBCR 0x90004 +#define GCC_QSPI_REF_CBCR 0x90008 +#define GCC_MMSS_MISC 0x0902C +#define GCC_GPU_MISC 0x71028 + +#define GPUCC_GPU_PLL0_PLL_MODE 0x00000 +#define GPUCC_GPU_PLL0_USER_CTL_MODE 0x0000C +#define GPUCC_GFX3D_CMD_RCGR 0x01070 +#define GPUCC_RBBMTIMER_CMD_RCGR 0x010B0 +#define GPUCC_GFX3D_ISENSE_CMD_RCGR 0x01100 +#define GPUCC_RBCPR_CMD_RCGR 0x01030 +#define GPUCC_GFX3D_CBCR 0x01098 +#define GPUCC_RBBMTIMER_CBCR 0x010D0 +#define GPUCC_GFX3D_ISENSE_CBCR 0x01124 +#define GPUCC_CXO_CBCR 0x01020 +#define GPUCC_RBCPR_CBCR 0x01054 +#define GPU_GX_BCR 0x01090 +#define GPUCC_GX_DOMAIN_MISC 0x00130 +#define GPUCC_GPU_DD_WRAP_CTRL 0x00430 +#define GPUCC_DEBUG_CLK_CTL 0x00120 + +#define MMSS_PLL_VOTE_APCS 0x001E0 +#define MMSS_MMPLL0_PLL_MODE 0x0C000 +#define MMSS_MMPLL1_PLL_MODE 0x0C050 +#define MMSS_MMPLL3_PLL_MODE 0x00000 +#define MMSS_MMPLL4_PLL_MODE 0x00050 +#define MMSS_MMPLL5_PLL_MODE 0x000A0 +#define MMSS_MMPLL6_PLL_MODE 0x000F0 +#define MMSS_MMPLL7_PLL_MODE 0x00140 +#define MMSS_MMPLL10_PLL_MODE 0x00190 +#define MMSS_AHB_CMD_RCGR 0x05000 +#define MMSS_CSI0_CMD_RCGR 0x03090 +#define MMSS_VFE0_CMD_RCGR 0x03600 +#define MMSS_VFE1_CMD_RCGR 0x03620 +#define MMSS_MDP_CMD_RCGR 0x02040 +#define MMSS_MAXI_CMD_RCGR 0x0F020 +#define MMSS_CPP_CMD_RCGR 0x03640 +#define MMSS_JPEG0_CMD_RCGR 0x03500 +#define MMSS_ROT_CMD_RCGR 0x021A0 +#define MMSS_VIDEO_CORE_CMD_RCGR 0x01000 +#define MMSS_CSI1_CMD_RCGR 0x03100 +#define MMSS_CSI2_CMD_RCGR 0x03160 +#define MMSS_CSI3_CMD_RCGR 0x031C0 +#define MMSS_FD_CORE_CMD_RCGR 0x03B00 +#define MMSS_BYTE0_CMD_RCGR 0x02120 +#define MMSS_BYTE1_CMD_RCGR 0x02140 +#define MMSS_PCLK0_CMD_RCGR 0x02000 +#define MMSS_PCLK1_CMD_RCGR 0x02020 +#define MMSS_VIDEO_SUBCORE0_CMD_RCGR 0x01060 +#define MMSS_VIDEO_SUBCORE1_CMD_RCGR 0x01080 +#define MMSS_CSIPHY_CMD_RCGR 0x03800 +#define MMSS_CCI_CMD_RCGR 0x03300 +#define MMSS_CAMSS_GP0_CMD_RCGR 0x03420 +#define MMSS_CAMSS_GP1_CMD_RCGR 0x03450 +#define MMSS_MCLK0_CMD_RCGR 0x03360 +#define MMSS_MCLK1_CMD_RCGR 0x03390 +#define MMSS_MCLK2_CMD_RCGR 0x033C0 +#define MMSS_MCLK3_CMD_RCGR 0x033F0 +#define MMSS_CAMSS_CSI2PHYTIMER_CBCR 0x03084 +#define MMSS_CSI0PHYTIMER_CMD_RCGR 0x03000 +#define MMSS_CSI1PHYTIMER_CMD_RCGR 0x03030 +#define MMSS_CSI2PHYTIMER_CMD_RCGR 0x03060 +#define MMSS_DP_GTC_CMD_RCGR 0x02280 +#define MMSS_ESC0_CMD_RCGR 0x02160 +#define MMSS_ESC1_CMD_RCGR 0x02180 +#define MMSS_EXTPCLK_CMD_RCGR 0x02060 +#define MMSS_HDMI_CMD_RCGR 0x02100 +#define MMSS_VSYNC_CMD_RCGR 0x02080 +#define MMSS_BIMC_SMMU_AHB_CBCR 0x0E004 +#define MMSS_BIMC_SMMU_AXI_CBCR 0x0E008 +#define MMSS_SNOC_DVM_AXI_CBCR 0x0E040 +#define MMSS_CAMSS_AHB_CBCR 0x0348C +#define MMSS_CAMSS_CCI_AHB_CBCR 0x03348 +#define MMSS_CAMSS_CCI_CBCR 0x03344 +#define MMSS_CAMSS_CPP_AHB_CBCR 0x036B4 +#define MMSS_CAMSS_CPP_CBCR 0x036B0 +#define MMSS_CAMSS_CPP_AXI_CBCR 0x036C4 +#define MMSS_CAMSS_CPP_VBIF_AHB_CBCR 0x036C8 +#define MMSS_CAMSS_CPHY_CSID0_CBCR 0x03730 +#define MMSS_CAMSS_CSI0_AHB_CBCR 0x030BC +#define MMSS_CAMSS_CSI0_CBCR 0x030B4 +#define MMSS_CAMSS_CSI0PIX_CBCR 0x030E4 +#define MMSS_CAMSS_CSI0RDI_CBCR 0x030D4 +#define MMSS_CAMSS_CPHY_CSID1_CBCR 0x03734 +#define MMSS_CAMSS_CSI1_AHB_CBCR 0x03128 +#define MMSS_CAMSS_CSI1_CBCR 0x03124 +#define MMSS_CAMSS_CSI1PIX_CBCR 0x03154 +#define MMSS_CAMSS_CSI1RDI_CBCR 0x03144 +#define MMSS_CAMSS_CPHY_CSID2_CBCR 0x03738 +#define MMSS_CAMSS_CSI2_AHB_CBCR 0x03188 +#define MMSS_CAMSS_CSI2_CBCR 0x03184 +#define MMSS_CAMSS_CSI2PIX_CBCR 0x031B4 +#define MMSS_CAMSS_CSI2RDI_CBCR 0x031A4 +#define MMSS_CAMSS_CPHY_CSID3_CBCR 0x0373C +#define MMSS_CAMSS_CSI3_AHB_CBCR 0x031E8 +#define MMSS_CAMSS_CSI3_CBCR 0x031E4 +#define MMSS_CAMSS_CSI3PIX_CBCR 0x03214 +#define MMSS_CAMSS_CSI3RDI_CBCR 0x03204 +#define MMSS_CAMSS_CSI_VFE0_CBCR 0x03704 +#define MMSS_CAMSS_CSI_VFE1_CBCR 0x03714 +#define MMSS_CAMSS_CSIPHY0_CBCR 0x03740 +#define MMSS_CAMSS_CSIPHY1_CBCR 0x03744 +#define MMSS_CAMSS_CSIPHY2_CBCR 0x03748 +#define MMSS_FD_AHB_CBCR 0x03B74 +#define MMSS_FD_CORE_CBCR 0x03B68 +#define MMSS_FD_CORE_UAR_CBCR 0x03B6C +#define MMSS_CAMSS_GP0_CBCR 0x03444 +#define MMSS_CAMSS_GP1_CBCR 0x03474 +#define MMSS_CAMSS_ISPIF_AHB_CBCR 0x03224 +#define MMSS_CAMSS_JPEG0_CBCR 0x035A8 +#define MMSS_CAMSS_JPEG_AHB_CBCR 0x035B4 +#define MMSS_CAMSS_JPEG_AXI_CBCR 0x035B8 +#define MMSS_CAMSS_MCLK0_CBCR 0x03384 +#define MMSS_CAMSS_MCLK1_CBCR 0x033B4 +#define MMSS_CAMSS_MCLK2_CBCR 0x033E4 +#define MMSS_CAMSS_MCLK3_CBCR 0x03414 +#define MMSS_CAMSS_MICRO_AHB_CBCR 0x03494 +#define MMSS_CAMSS_CSI0PHYTIMER_CBCR 0x03024 +#define MMSS_CAMSS_CSI1PHYTIMER_CBCR 0x03054 +#define MMSS_CSI2PHYTIMER_CMD_RCGR 0x03060 +#define MMSS_CAMSS_TOP_AHB_CBCR 0x03484 +#define MMSS_CAMSS_VFE0_AHB_CBCR 0x03668 +#define MMSS_CAMSS_VFE0_CBCR 0x036A8 +#define MMSS_CAMSS_VFE0_STREAM_CBCR 0x03720 +#define MMSS_CAMSS_VFE1_AHB_CBCR 0x03678 +#define MMSS_CAMSS_VFE1_CBCR 0x036AC +#define MMSS_CAMSS_VFE1_STREAM_CBCR 0x03724 +#define MMSS_CAMSS_VFE_VBIF_AHB_CBCR 0x036B8 +#define MMSS_CAMSS_VFE_VBIF_AXI_CBCR 0x036BC +#define MMSS_MDSS_AHB_CBCR 0x02308 +#define MMSS_MDSS_AXI_CBCR 0x02310 +#define MMSS_MDSS_BYTE0_CBCR 0x0233C +#define MMSS_MDSS_BYTE0_INTF_CBCR 0x02374 +#define MMSS_MDSS_BYTE0_INTF_DIV 0x0237C +#define MMSS_MDSS_BYTE1_CBCR 0x02340 +#define MMSS_MDSS_BYTE1_INTF_CBCR 0x02378 +#define MMSS_MDSS_BYTE1_INTF_DIV 0x02380 +#define MMSS_MDSS_DP_AUX_CBCR 0x02364 +#define MMSS_MDSS_DP_CRYPTO_CBCR 0x0235C +#define MMSS_MDSS_DP_GTC_CBCR 0x02368 +#define MMSS_MDSS_DP_LINK_CBCR 0x02354 +#define MMSS_MDSS_DP_LINK_INTF_CBCR 0x02358 +#define MMSS_MDSS_DP_PIXEL_CBCR 0x02360 +#define MMSS_MDSS_ESC0_CBCR 0x02344 +#define MMSS_MDSS_ESC1_CBCR 0x02348 +#define MMSS_MDSS_EXTPCLK_CBCR 0x02324 +#define MMSS_MDSS_HDMI_CBCR 0x02338 +#define MMSS_MDSS_HDMI_DP_AHB_CBCR 0x0230C +#define MMSS_MDSS_MDP_CBCR 0x0231C +#define MMSS_MDSS_MDP_LUT_CBCR 0x02320 +#define MMSS_MDSS_PCLK0_CBCR 0x02314 +#define MMSS_MDSS_PCLK1_CBCR 0x02318 +#define MMSS_MDSS_ROT_CBCR 0x02350 +#define MMSS_MDSS_VSYNC_CBCR 0x02328 +#define MMSS_MISC_AHB_CBCR 0x00328 +#define MMSS_MISC_CXO_CBCR 0x00324 +#define MMSS_MNOC_AHB_CBCR 0x05024 +#define MMSS_MNOC_MAXI_CBCR 0x0F004 +#define MMSS_VIDEO_SUBCORE0_CBCR 0x01048 +#define MMSS_VIDEO_SUBCORE1_CBCR 0x0104C +#define MMSS_VIDEO_AHB_CBCR 0x01030 +#define MMSS_VIDEO_AXI_CBCR 0x01034 +#define MMSS_VIDEO_CORE_CBCR 0x01028 +#define MMSS_VIDEO_MAXI_CBCR 0x01038 +#define MMSS_VMEM_AHB_CBCR 0x0F068 +#define MMSS_VMEM_MAXI_CBCR 0x0F064 +#define MMSS_DP_AUX_CMD_RCGR 0x02260 +#define MMSS_DP_CRYPTO_CMD_RCGR 0x02220 +#define MMSS_DP_LINK_CMD_RCGR 0x02200 +#define MMSS_DP_PIXEL_CMD_RCGR 0x02240 +#define MMSS_DEBUG_CLK_CTL 0x00900 diff -Nruw linux-4.4.115-fbx/arch/powerpc/boot/dts/include/dt-bindings/msm./msm-bus-ids.h linux-4.4.115-fbx/arch/powerpc/boot/dts/include/dt-bindings/msm/msm-bus-ids.h --- linux-4.4.115-fbx/arch/powerpc/boot/dts/include/dt-bindings/msm./msm-bus-ids.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-4.4.115-fbx/arch/powerpc/boot/dts/include/dt-bindings/msm/msm-bus-ids.h 2019-01-22 16:16:28.179288750 +0100 @@ -0,0 +1,887 @@ +/* Copyright (c) 2014-2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __MSM_BUS_IDS_H +#define __MSM_BUS_IDS_H + +/* Aggregation types */ +#define AGG_SCHEME_NONE 0 +#define AGG_SCHEME_LEG 1 +#define AGG_SCHEME_1 2 + +/* Topology related enums */ +#define MSM_BUS_FAB_DEFAULT 0 +#define MSM_BUS_FAB_APPSS 0 +#define MSM_BUS_FAB_SYSTEM 1024 +#define MSM_BUS_FAB_MMSS 2048 +#define MSM_BUS_FAB_SYSTEM_FPB 3072 +#define MSM_BUS_FAB_CPSS_FPB 4096 + +#define MSM_BUS_FAB_BIMC 0 +#define MSM_BUS_FAB_SYS_NOC 1024 +#define MSM_BUS_FAB_MMSS_NOC 2048 +#define MSM_BUS_FAB_OCMEM_NOC 3072 +#define MSM_BUS_FAB_PERIPH_NOC 4096 +#define MSM_BUS_FAB_CONFIG_NOC 5120 +#define MSM_BUS_FAB_OCMEM_VNOC 6144 +#define MSM_BUS_FAB_MMSS_AHB 2049 +#define MSM_BUS_FAB_A0_NOC 6145 +#define MSM_BUS_FAB_A1_NOC 6146 +#define MSM_BUS_FAB_A2_NOC 6147 +#define MSM_BUS_FAB_GNOC 6148 +#define MSM_BUS_FAB_CR_VIRT 6149 + +#define MSM_BUS_MASTER_FIRST 1 +#define MSM_BUS_MASTER_AMPSS_M0 1 +#define MSM_BUS_MASTER_AMPSS_M1 2 +#define MSM_BUS_APPSS_MASTER_FAB_MMSS 3 +#define MSM_BUS_APPSS_MASTER_FAB_SYSTEM 4 +#define MSM_BUS_SYSTEM_MASTER_FAB_APPSS 5 +#define MSM_BUS_MASTER_SPS 6 +#define MSM_BUS_MASTER_ADM_PORT0 7 +#define MSM_BUS_MASTER_ADM_PORT1 8 +#define MSM_BUS_SYSTEM_MASTER_ADM1_PORT0 9 +#define MSM_BUS_MASTER_ADM1_PORT1 10 +#define MSM_BUS_MASTER_LPASS_PROC 11 +#define MSM_BUS_MASTER_MSS_PROCI 12 +#define MSM_BUS_MASTER_MSS_PROCD 13 +#define MSM_BUS_MASTER_MSS_MDM_PORT0 14 +#define MSM_BUS_MASTER_LPASS 15 +#define MSM_BUS_SYSTEM_MASTER_CPSS_FPB 16 +#define MSM_BUS_SYSTEM_MASTER_SYSTEM_FPB 17 +#define MSM_BUS_SYSTEM_MASTER_MMSS_FPB 18 +#define MSM_BUS_MASTER_ADM1_CI 19 +#define MSM_BUS_MASTER_ADM0_CI 20 +#define MSM_BUS_MASTER_MSS_MDM_PORT1 21 +#define MSM_BUS_MASTER_MDP_PORT0 22 +#define MSM_BUS_MASTER_MDP_PORT1 23 +#define MSM_BUS_MMSS_MASTER_ADM1_PORT0 24 +#define MSM_BUS_MASTER_ROTATOR 25 +#define MSM_BUS_MASTER_GRAPHICS_3D 26 +#define MSM_BUS_MASTER_JPEG_DEC 27 +#define MSM_BUS_MASTER_GRAPHICS_2D_CORE0 28 +#define MSM_BUS_MASTER_VFE 29 +#define MSM_BUS_MASTER_VFE0 MSM_BUS_MASTER_VFE +#define MSM_BUS_MASTER_VPE 30 +#define MSM_BUS_MASTER_JPEG_ENC 31 +#define MSM_BUS_MASTER_GRAPHICS_2D_CORE1 32 +#define MSM_BUS_MMSS_MASTER_APPS_FAB 33 +#define MSM_BUS_MASTER_HD_CODEC_PORT0 34 +#define MSM_BUS_MASTER_HD_CODEC_PORT1 35 +#define MSM_BUS_MASTER_SPDM 36 +#define MSM_BUS_MASTER_RPM 37 +#define MSM_BUS_MASTER_MSS 38 +#define MSM_BUS_MASTER_RIVA 39 +#define MSM_BUS_MASTER_SNOC_VMEM 40 +#define MSM_BUS_MASTER_MSS_SW_PROC 41 +#define MSM_BUS_MASTER_MSS_FW_PROC 42 +#define MSM_BUS_MASTER_HMSS 43 +#define MSM_BUS_MASTER_GSS_NAV 44 +#define MSM_BUS_MASTER_PCIE 45 +#define MSM_BUS_MASTER_SATA 46 +#define MSM_BUS_MASTER_CRYPTO 47 +#define MSM_BUS_MASTER_VIDEO_CAP 48 +#define MSM_BUS_MASTER_GRAPHICS_3D_PORT1 49 +#define MSM_BUS_MASTER_VIDEO_ENC 50 +#define MSM_BUS_MASTER_VIDEO_DEC 51 +#define MSM_BUS_MASTER_LPASS_AHB 52 +#define MSM_BUS_MASTER_QDSS_BAM 53 +#define MSM_BUS_MASTER_SNOC_CFG 54 +#define MSM_BUS_MASTER_CRYPTO_CORE0 55 +#define MSM_BUS_MASTER_CRYPTO_CORE1 56 +#define MSM_BUS_MASTER_MSS_NAV 57 +#define MSM_BUS_MASTER_OCMEM_DMA 58 +#define MSM_BUS_MASTER_WCSS 59 +#define MSM_BUS_MASTER_QDSS_ETR 60 +#define MSM_BUS_MASTER_USB3 61 +#define MSM_BUS_MASTER_JPEG 62 +#define MSM_BUS_MASTER_VIDEO_P0 63 +#define MSM_BUS_MASTER_VIDEO_P1 64 +#define MSM_BUS_MASTER_MSS_PROC 65 +#define MSM_BUS_MASTER_JPEG_OCMEM 66 +#define MSM_BUS_MASTER_MDP_OCMEM 67 +#define MSM_BUS_MASTER_VIDEO_P0_OCMEM 68 +#define MSM_BUS_MASTER_VIDEO_P1_OCMEM 69 +#define MSM_BUS_MASTER_VFE_OCMEM 70 +#define MSM_BUS_MASTER_CNOC_ONOC_CFG 71 +#define MSM_BUS_MASTER_RPM_INST 72 +#define MSM_BUS_MASTER_RPM_DATA 73 +#define MSM_BUS_MASTER_RPM_SYS 74 +#define MSM_BUS_MASTER_DEHR 75 +#define MSM_BUS_MASTER_QDSS_DAP 76 +#define MSM_BUS_MASTER_TIC 77 +#define MSM_BUS_MASTER_SDCC_1 78 +#define MSM_BUS_MASTER_SDCC_3 79 +#define MSM_BUS_MASTER_SDCC_4 80 +#define MSM_BUS_MASTER_SDCC_2 81 +#define MSM_BUS_MASTER_TSIF 82 +#define MSM_BUS_MASTER_BAM_DMA 83 +#define MSM_BUS_MASTER_BLSP_2 84 +#define MSM_BUS_MASTER_USB_HSIC 85 +#define MSM_BUS_MASTER_BLSP_1 86 +#define MSM_BUS_MASTER_USB_HS 87 +#define MSM_BUS_MASTER_PNOC_CFG 88 +#define MSM_BUS_MASTER_V_OCMEM_GFX3D 89 +#define MSM_BUS_MASTER_IPA 90 +#define MSM_BUS_MASTER_QPIC 91 +#define MSM_BUS_MASTER_MDPE 92 +#define MSM_BUS_MASTER_USB_HS2 93 +#define MSM_BUS_MASTER_VPU 94 +#define MSM_BUS_MASTER_UFS 95 +#define MSM_BUS_MASTER_BCAST 96 +#define MSM_BUS_MASTER_CRYPTO_CORE2 97 +#define MSM_BUS_MASTER_EMAC 98 +#define MSM_BUS_MASTER_VPU_1 99 +#define MSM_BUS_MASTER_PCIE_1 100 +#define MSM_BUS_MASTER_USB3_1 101 +#define MSM_BUS_MASTER_CNOC_MNOC_MMSS_CFG 102 +#define MSM_BUS_MASTER_CNOC_MNOC_CFG 103 +#define MSM_BUS_MASTER_TCU_0 104 +#define MSM_BUS_MASTER_TCU_1 105 +#define MSM_BUS_MASTER_CPP 106 +#define MSM_BUS_MASTER_AUDIO 107 +#define MSM_BUS_MASTER_PCIE_2 108 +#define MSM_BUS_MASTER_VFE1 109 +#define MSM_BUS_MASTER_XM_USB_HS1 110 +#define MSM_BUS_MASTER_PCNOC_BIMC_1 111 +#define MSM_BUS_MASTER_BIMC_PCNOC 112 +#define MSM_BUS_MASTER_XI_USB_HSIC 113 +#define MSM_BUS_MASTER_SGMII 114 +#define MSM_BUS_SPMI_FETCHER 115 +#define MSM_BUS_MASTER_GNOC_BIMC 116 +#define MSM_BUS_MASTER_CRVIRT_A2NOC 117 +#define MSM_BUS_MASTER_CNOC_A2NOC 118 +#define MSM_BUS_MASTER_WLAN 119 +#define MSM_BUS_MASTER_MSS_CE 120 +#define MSM_BUS_MASTER_CDSP_PROC 121 +#define MSM_BUS_MASTER_GNOC_SNOC 122 +#define MSM_BUS_MASTER_PIMEM 123 +#define MSM_BUS_MASTER_MASTER_LAST 124 + +#define MSM_BUS_SYSTEM_FPB_MASTER_SYSTEM MSM_BUS_SYSTEM_MASTER_SYSTEM_FPB +#define MSM_BUS_CPSS_FPB_MASTER_SYSTEM MSM_BUS_SYSTEM_MASTER_CPSS_FPB + +#define MSM_BUS_SNOC_MM_INT_0 10000 +#define MSM_BUS_SNOC_MM_INT_1 10001 +#define MSM_BUS_SNOC_MM_INT_2 10002 +#define MSM_BUS_SNOC_MM_INT_BIMC 10003 +#define MSM_BUS_SNOC_INT_0 10004 +#define MSM_BUS_SNOC_INT_1 10005 +#define MSM_BUS_SNOC_INT_BIMC 10006 +#define MSM_BUS_SNOC_BIMC_0_MAS 10007 +#define MSM_BUS_SNOC_BIMC_1_MAS 10008 +#define MSM_BUS_SNOC_QDSS_INT 10009 +#define MSM_BUS_PNOC_SNOC_MAS 10010 +#define MSM_BUS_PNOC_SNOC_SLV 10011 +#define MSM_BUS_PNOC_INT_0 10012 +#define MSM_BUS_PNOC_INT_1 10013 +#define MSM_BUS_PNOC_M_0 10014 +#define MSM_BUS_PNOC_M_1 10015 +#define MSM_BUS_BIMC_SNOC_MAS 10016 +#define MSM_BUS_BIMC_SNOC_SLV 10017 +#define MSM_BUS_PNOC_SLV_0 10018 +#define MSM_BUS_PNOC_SLV_1 10019 +#define MSM_BUS_PNOC_SLV_2 10020 +#define MSM_BUS_PNOC_SLV_3 10021 +#define MSM_BUS_PNOC_SLV_4 10022 +#define MSM_BUS_PNOC_SLV_8 10023 +#define MSM_BUS_PNOC_SLV_9 10024 +#define MSM_BUS_SNOC_BIMC_0_SLV 10025 +#define MSM_BUS_SNOC_BIMC_1_SLV 10026 +#define MSM_BUS_MNOC_BIMC_MAS 10027 +#define MSM_BUS_MNOC_BIMC_SLV 10028 +#define MSM_BUS_BIMC_MNOC_MAS 10029 +#define MSM_BUS_BIMC_MNOC_SLV 10030 +#define MSM_BUS_SNOC_BIMC_MAS 10031 +#define MSM_BUS_SNOC_BIMC_SLV 10032 +#define MSM_BUS_CNOC_SNOC_MAS 10033 +#define MSM_BUS_CNOC_SNOC_SLV 10034 +#define MSM_BUS_SNOC_CNOC_MAS 10035 +#define MSM_BUS_SNOC_CNOC_SLV 10036 +#define MSM_BUS_OVNOC_SNOC_MAS 10037 +#define MSM_BUS_OVNOC_SNOC_SLV 10038 +#define MSM_BUS_SNOC_OVNOC_MAS 10039 +#define MSM_BUS_SNOC_OVNOC_SLV 10040 +#define MSM_BUS_SNOC_PNOC_MAS 10041 +#define MSM_BUS_SNOC_PNOC_SLV 10042 +#define MSM_BUS_BIMC_INT_APPS_EBI 10043 +#define MSM_BUS_BIMC_INT_APPS_SNOC 10044 +#define MSM_BUS_SNOC_BIMC_2_MAS 10045 +#define MSM_BUS_SNOC_BIMC_2_SLV 10046 +#define MSM_BUS_PNOC_SLV_5 10047 +#define MSM_BUS_PNOC_SLV_7 10048 +#define MSM_BUS_PNOC_INT_2 10049 +#define MSM_BUS_PNOC_INT_3 10050 +#define MSM_BUS_PNOC_INT_4 10051 +#define MSM_BUS_PNOC_INT_5 10052 +#define MSM_BUS_PNOC_INT_6 10053 +#define MSM_BUS_PNOC_INT_7 10054 +#define MSM_BUS_BIMC_SNOC_1_MAS 10055 +#define MSM_BUS_BIMC_SNOC_1_SLV 10056 +#define MSM_BUS_PNOC_A1NOC_MAS 10057 +#define MSM_BUS_PNOC_A1NOC_SLV 10058 +#define MSM_BUS_CNOC_A1NOC_MAS 10059 +#define MSM_BUS_A0NOC_SNOC_MAS 10060 +#define MSM_BUS_A0NOC_SNOC_SLV 10061 +#define MSM_BUS_A1NOC_SNOC_SLV 10062 +#define MSM_BUS_A1NOC_SNOC_MAS 10063 +#define MSM_BUS_A2NOC_SNOC_MAS 10064 +#define MSM_BUS_A2NOC_SNOC_SLV 10065 +#define MSM_BUS_SNOC_INT_2 10066 +#define MSM_BUS_A0NOC_QDSS_INT 10067 +#define MSM_BUS_INT_LAST 10068 + +#define MSM_BUS_INT_TEST_ID 20000 +#define MSM_BUS_INT_TEST_LAST 20050 + +#define MSM_BUS_SLAVE_FIRST 512 +#define MSM_BUS_SLAVE_EBI_CH0 512 +#define MSM_BUS_SLAVE_EBI_CH1 513 +#define MSM_BUS_SLAVE_AMPSS_L2 514 +#define MSM_BUS_APPSS_SLAVE_FAB_MMSS 515 +#define MSM_BUS_APPSS_SLAVE_FAB_SYSTEM 516 +#define MSM_BUS_SYSTEM_SLAVE_FAB_APPS 517 +#define MSM_BUS_SLAVE_SPS 518 +#define MSM_BUS_SLAVE_SYSTEM_IMEM 519 +#define MSM_BUS_SLAVE_AMPSS 520 +#define MSM_BUS_SLAVE_MSS 521 +#define MSM_BUS_SLAVE_LPASS 522 +#define MSM_BUS_SYSTEM_SLAVE_CPSS_FPB 523 +#define MSM_BUS_SYSTEM_SLAVE_SYSTEM_FPB 524 +#define MSM_BUS_SYSTEM_SLAVE_MMSS_FPB 525 +#define MSM_BUS_SLAVE_CORESIGHT 526 +#define MSM_BUS_SLAVE_RIVA 527 +#define MSM_BUS_SLAVE_SMI 528 +#define MSM_BUS_MMSS_SLAVE_FAB_APPS 529 +#define MSM_BUS_MMSS_SLAVE_FAB_APPS_1 530 +#define MSM_BUS_SLAVE_MM_IMEM 531 +#define MSM_BUS_SLAVE_CRYPTO 532 +#define MSM_BUS_SLAVE_SPDM 533 +#define MSM_BUS_SLAVE_RPM 534 +#define MSM_BUS_SLAVE_RPM_MSG_RAM 535 +#define MSM_BUS_SLAVE_MPM 536 +#define MSM_BUS_SLAVE_PMIC1_SSBI1_A 537 +#define MSM_BUS_SLAVE_PMIC1_SSBI1_B 538 +#define MSM_BUS_SLAVE_PMIC1_SSBI1_C 539 +#define MSM_BUS_SLAVE_PMIC2_SSBI2_A 540 +#define MSM_BUS_SLAVE_PMIC2_SSBI2_B 541 +#define MSM_BUS_SLAVE_GSBI1_UART 542 +#define MSM_BUS_SLAVE_GSBI2_UART 543 +#define MSM_BUS_SLAVE_GSBI3_UART 544 +#define MSM_BUS_SLAVE_GSBI4_UART 545 +#define MSM_BUS_SLAVE_GSBI5_UART 546 +#define MSM_BUS_SLAVE_GSBI6_UART 547 +#define MSM_BUS_SLAVE_GSBI7_UART 548 +#define MSM_BUS_SLAVE_GSBI8_UART 549 +#define MSM_BUS_SLAVE_GSBI9_UART 550 +#define MSM_BUS_SLAVE_GSBI10_UART 551 +#define MSM_BUS_SLAVE_GSBI11_UART 552 +#define MSM_BUS_SLAVE_GSBI12_UART 553 +#define MSM_BUS_SLAVE_GSBI1_QUP 554 +#define MSM_BUS_SLAVE_GSBI2_QUP 555 +#define MSM_BUS_SLAVE_GSBI3_QUP 556 +#define MSM_BUS_SLAVE_GSBI4_QUP 557 +#define MSM_BUS_SLAVE_GSBI5_QUP 558 +#define MSM_BUS_SLAVE_GSBI6_QUP 559 +#define MSM_BUS_SLAVE_GSBI7_QUP 560 +#define MSM_BUS_SLAVE_GSBI8_QUP 561 +#define MSM_BUS_SLAVE_GSBI9_QUP 562 +#define MSM_BUS_SLAVE_GSBI10_QUP 563 +#define MSM_BUS_SLAVE_GSBI11_QUP 564 +#define MSM_BUS_SLAVE_GSBI12_QUP 565 +#define MSM_BUS_SLAVE_EBI2_NAND 566 +#define MSM_BUS_SLAVE_EBI2_CS0 567 +#define MSM_BUS_SLAVE_EBI2_CS1 568 +#define MSM_BUS_SLAVE_EBI2_CS2 569 +#define MSM_BUS_SLAVE_EBI2_CS3 570 +#define MSM_BUS_SLAVE_EBI2_CS4 571 +#define MSM_BUS_SLAVE_EBI2_CS5 572 +#define MSM_BUS_SLAVE_USB_FS1 573 +#define MSM_BUS_SLAVE_USB_FS2 574 +#define MSM_BUS_SLAVE_TSIF 575 +#define MSM_BUS_SLAVE_MSM_TSSC 576 +#define MSM_BUS_SLAVE_MSM_PDM 577 +#define MSM_BUS_SLAVE_MSM_DIMEM 578 +#define MSM_BUS_SLAVE_MSM_TCSR 579 +#define MSM_BUS_SLAVE_MSM_PRNG 580 +#define MSM_BUS_SLAVE_GSS 581 +#define MSM_BUS_SLAVE_SATA 582 +#define MSM_BUS_SLAVE_USB3 583 +#define MSM_BUS_SLAVE_WCSS 584 +#define MSM_BUS_SLAVE_OCIMEM 585 +#define MSM_BUS_SLAVE_SNOC_OCMEM 586 +#define MSM_BUS_SLAVE_SERVICE_SNOC 587 +#define MSM_BUS_SLAVE_QDSS_STM 588 +#define MSM_BUS_SLAVE_CAMERA_CFG 589 +#define MSM_BUS_SLAVE_DISPLAY_CFG 590 +#define MSM_BUS_SLAVE_OCMEM_CFG 591 +#define MSM_BUS_SLAVE_CPR_CFG 592 +#define MSM_BUS_SLAVE_CPR_XPU_CFG 593 +#define MSM_BUS_SLAVE_MISC_CFG 594 +#define MSM_BUS_SLAVE_MISC_XPU_CFG 595 +#define MSM_BUS_SLAVE_VENUS_CFG 596 +#define MSM_BUS_SLAVE_MISC_VENUS_CFG 597 +#define MSM_BUS_SLAVE_GRAPHICS_3D_CFG 598 +#define MSM_BUS_SLAVE_MMSS_CLK_CFG 599 +#define MSM_BUS_SLAVE_MMSS_CLK_XPU_CFG 600 +#define MSM_BUS_SLAVE_MNOC_MPU_CFG 601 +#define MSM_BUS_SLAVE_ONOC_MPU_CFG 602 +#define MSM_BUS_SLAVE_SERVICE_MNOC 603 +#define MSM_BUS_SLAVE_OCMEM 604 +#define MSM_BUS_SLAVE_SERVICE_ONOC 605 +#define MSM_BUS_SLAVE_SDCC_1 606 +#define MSM_BUS_SLAVE_SDCC_3 607 +#define MSM_BUS_SLAVE_SDCC_2 608 +#define MSM_BUS_SLAVE_SDCC_4 609 +#define MSM_BUS_SLAVE_BAM_DMA 610 +#define MSM_BUS_SLAVE_BLSP_2 611 +#define MSM_BUS_SLAVE_USB_HSIC 612 +#define MSM_BUS_SLAVE_BLSP_1 613 +#define MSM_BUS_SLAVE_USB_HS 614 +#define MSM_BUS_SLAVE_PDM 615 +#define MSM_BUS_SLAVE_PERIPH_APU_CFG 616 +#define MSM_BUS_SLAVE_PNOC_MPU_CFG 617 +#define MSM_BUS_SLAVE_PRNG 618 +#define MSM_BUS_SLAVE_SERVICE_PNOC 619 +#define MSM_BUS_SLAVE_CLK_CTL 620 +#define MSM_BUS_SLAVE_CNOC_MSS 621 +#define MSM_BUS_SLAVE_SECURITY 622 +#define MSM_BUS_SLAVE_TCSR 623 +#define MSM_BUS_SLAVE_TLMM 624 +#define MSM_BUS_SLAVE_CRYPTO_0_CFG 625 +#define MSM_BUS_SLAVE_CRYPTO_1_CFG 626 +#define MSM_BUS_SLAVE_IMEM_CFG 627 +#define MSM_BUS_SLAVE_MESSAGE_RAM 628 +#define MSM_BUS_SLAVE_BIMC_CFG 629 +#define MSM_BUS_SLAVE_BOOT_ROM 630 +#define MSM_BUS_SLAVE_CNOC_MNOC_MMSS_CFG 631 +#define MSM_BUS_SLAVE_PMIC_ARB 632 +#define MSM_BUS_SLAVE_SPDM_WRAPPER 633 +#define MSM_BUS_SLAVE_DEHR_CFG 634 +#define MSM_BUS_SLAVE_QDSS_CFG 635 +#define MSM_BUS_SLAVE_RBCPR_CFG 636 +#define MSM_BUS_SLAVE_RBCPR_QDSS_APU_CFG 637 +#define MSM_BUS_SLAVE_SNOC_MPU_CFG 638 +#define MSM_BUS_SLAVE_CNOC_ONOC_CFG 639 +#define MSM_BUS_SLAVE_CNOC_MNOC_CFG 640 +#define MSM_BUS_SLAVE_PNOC_CFG 641 +#define MSM_BUS_SLAVE_SNOC_CFG 642 +#define MSM_BUS_SLAVE_EBI1_DLL_CFG 643 +#define MSM_BUS_SLAVE_PHY_APU_CFG 644 +#define MSM_BUS_SLAVE_EBI1_PHY_CFG 645 +#define MSM_BUS_SLAVE_SERVICE_CNOC 646 +#define MSM_BUS_SLAVE_IPS_CFG 647 +#define MSM_BUS_SLAVE_QPIC 648 +#define MSM_BUS_SLAVE_DSI_CFG 649 +#define MSM_BUS_SLAVE_UFS_CFG 650 +#define MSM_BUS_SLAVE_RBCPR_CX_CFG 651 +#define MSM_BUS_SLAVE_RBCPR_MX_CFG 652 +#define MSM_BUS_SLAVE_PCIE_CFG 653 +#define MSM_BUS_SLAVE_USB_PHYS_CFG 654 +#define MSM_BUS_SLAVE_VIDEO_CAP_CFG 655 +#define MSM_BUS_SLAVE_AVSYNC_CFG 656 +#define MSM_BUS_SLAVE_CRYPTO_2_CFG 657 +#define MSM_BUS_SLAVE_VPU_CFG 658 +#define MSM_BUS_SLAVE_BCAST_CFG 659 +#define MSM_BUS_SLAVE_KLM_CFG 660 +#define MSM_BUS_SLAVE_GENI_IR_CFG 661 +#define MSM_BUS_SLAVE_OCMEM_GFX 662 +#define MSM_BUS_SLAVE_CATS_128 663 +#define MSM_BUS_SLAVE_OCMEM_64 664 +#define MSM_BUS_SLAVE_PCIE_0 665 +#define MSM_BUS_SLAVE_PCIE_1 666 +#define MSM_BUS_SLAVE_PCIE_0_CFG 667 +#define MSM_BUS_SLAVE_PCIE_1_CFG 668 +#define MSM_BUS_SLAVE_SRVC_MNOC 669 +#define MSM_BUS_SLAVE_USB_HS2 670 +#define MSM_BUS_SLAVE_AUDIO 671 +#define MSM_BUS_SLAVE_TCU 672 +#define MSM_BUS_SLAVE_APPSS 673 +#define MSM_BUS_SLAVE_PCIE_PARF 674 +#define MSM_BUS_SLAVE_USB3_PHY_CFG 675 +#define MSM_BUS_SLAVE_IPA_CFG 676 +#define MSM_BUS_SLAVE_A0NOC_SNOC 677 +#define MSM_BUS_SLAVE_A1NOC_SNOC 678 +#define MSM_BUS_SLAVE_A2NOC_SNOC 679 +#define MSM_BUS_SLAVE_HMSS_L3 680 +#define MSM_BUS_SLAVE_PIMEM_CFG 681 +#define MSM_BUS_SLAVE_DCC_CFG 682 +#define MSM_BUS_SLAVE_QDSS_RBCPR_APU_CFG 683 +#define MSM_BUS_SLAVE_PCIE_2_CFG 684 +#define MSM_BUS_SLAVE_PCIE20_AHB2PHY 685 +#define MSM_BUS_SLAVE_A0NOC_CFG 686 +#define MSM_BUS_SLAVE_A1NOC_CFG 687 +#define MSM_BUS_SLAVE_A2NOC_CFG 688 +#define MSM_BUS_SLAVE_A1NOC_MPU_CFG 689 +#define MSM_BUS_SLAVE_A2NOC_MPU_CFG 690 +#define MSM_BUS_SLAVE_A0NOC_SMMU_CFG 691 +#define MSM_BUS_SLAVE_A1NOC_SMMU_CFG 692 +#define MSM_BUS_SLAVE_A2NOC_SMMU_CFG 693 +#define MSM_BUS_SLAVE_LPASS_SMMU_CFG 694 +#define MSM_BUS_SLAVE_MMAGIC_CFG 695 +#define MSM_BUS_SLAVE_VENUS_THROTTLE_CFG 696 +#define MSM_BUS_SLAVE_SSC_CFG 697 +#define MSM_BUS_SLAVE_DSA_CFG 698 +#define MSM_BUS_SLAVE_DSA_MPU_CFG 699 +#define MSM_BUS_SLAVE_DISPLAY_THROTTLE_CFG 700 +#define MSM_BUS_SLAVE_SMMU_CPP_CFG 701 +#define MSM_BUS_SLAVE_SMMU_JPEG_CFG 702 +#define MSM_BUS_SLAVE_SMMU_MDP_CFG 703 +#define MSM_BUS_SLAVE_SMMU_ROTATOR_CFG 704 +#define MSM_BUS_SLAVE_SMMU_VENUS_CFG 705 +#define MSM_BUS_SLAVE_SMMU_VFE_CFG 706 +#define MSM_BUS_SLAVE_A0NOC_MPU_CFG 707 +#define MSM_BUS_SLAVE_VMEM_CFG 708 +#define MSM_BUS_SLAVE_CAMERA_THROTTLE_CFG 709 +#define MSM_BUS_SLAVE_VMEM 710 +#define MSM_BUS_SLAVE_AHB2PHY 711 +#define MSM_BUS_SLAVE_PIMEM 712 +#define MSM_BUS_SLAVE_SNOC_VMEM 713 +#define MSM_BUS_SLAVE_PCIE_2 714 +#define MSM_BUS_SLAVE_RBCPR_MX 715 +#define MSM_BUS_SLAVE_RBCPR_CX 716 +#define MSM_BUS_SLAVE_BIMC_PCNOC 717 +#define MSM_BUS_SLAVE_PCNOC_BIMC_1 718 +#define MSM_BUS_SLAVE_SGMII 719 +#define MSM_BUS_SLAVE_SPMI_FETCHER 720 +#define MSM_BUS_PNOC_SLV_6 721 +#define MSM_BUS_SLAVE_MMSS_SMMU_CFG 722 +#define MSM_BUS_SLAVE_WLAN 723 +#define MSM_BUS_SLAVE_CRVIRT_A2NOC 724 +#define MSM_BUS_SLAVE_CNOC_A2NOC 725 +#define MSM_BUS_SLAVE_GLM 726 +#define MSM_BUS_SLAVE_GNOC_BIMC 727 +#define MSM_BUS_SLAVE_GNOC_SNOC 728 +#define MSM_BUS_SLAVE_QM_CFG 729 +#define MSM_BUS_SLAVE_TLMM_EAST 730 +#define MSM_BUS_SLAVE_TLMM_NORTH 731 +#define MSM_BUS_SLAVE_TLMM_WEST 732 +#define MSM_BUS_SLAVE_SKL 733 +#define MSM_BUS_SLAVE_LPASS_TCM 734 +#define MSM_BUS_SLAVE_TLMM_SOUTH 735 +#define MSM_BUS_SLAVE_TLMM_CENTER 736 +#define MSM_BUS_MSS_NAV_CE_MPU_CFG 737 +#define MSM_BUS_SLAVE_A2NOC_THROTTLE_CFG 738 +#define MSM_BUS_SLAVE_CDSP 739 +#define MSM_BUS_SLAVE_CDSP_SMMU_CFG 740 +#define MSM_BUS_SLAVE_LPASS_MPU_CFG 741 +#define MSM_BUS_SLAVE_CSI_PHY_CFG 742 +#define MSM_BUS_SLAVE_LAST 743 + +#define MSM_BUS_SYSTEM_FPB_SLAVE_SYSTEM MSM_BUS_SYSTEM_SLAVE_SYSTEM_FPB +#define MSM_BUS_CPSS_FPB_SLAVE_SYSTEM MSM_BUS_SYSTEM_SLAVE_CPSS_FPB + +/* + * ID's used in RPM messages + */ +#define ICBID_MASTER_APPSS_PROC 0 +#define ICBID_MASTER_MSS_PROC 1 +#define ICBID_MASTER_MNOC_BIMC 2 +#define ICBID_MASTER_SNOC_BIMC 3 +#define ICBID_MASTER_SNOC_BIMC_0 ICBID_MASTER_SNOC_BIMC +#define ICBID_MASTER_CNOC_MNOC_MMSS_CFG 4 +#define ICBID_MASTER_CNOC_MNOC_CFG 5 +#define ICBID_MASTER_GFX3D 6 +#define ICBID_MASTER_JPEG 7 +#define ICBID_MASTER_MDP 8 +#define ICBID_MASTER_MDP0 ICBID_MASTER_MDP +#define ICBID_MASTER_MDPS ICBID_MASTER_MDP +#define ICBID_MASTER_VIDEO 9 +#define ICBID_MASTER_VIDEO_P0 ICBID_MASTER_VIDEO +#define ICBID_MASTER_VIDEO_P1 10 +#define ICBID_MASTER_VFE 11 +#define ICBID_MASTER_VFE0 ICBID_MASTER_VFE +#define ICBID_MASTER_CNOC_ONOC_CFG 12 +#define ICBID_MASTER_JPEG_OCMEM 13 +#define ICBID_MASTER_MDP_OCMEM 14 +#define ICBID_MASTER_VIDEO_P0_OCMEM 15 +#define ICBID_MASTER_VIDEO_P1_OCMEM 16 +#define ICBID_MASTER_VFE_OCMEM 17 +#define ICBID_MASTER_LPASS_AHB 18 +#define ICBID_MASTER_QDSS_BAM 19 +#define ICBID_MASTER_SNOC_CFG 20 +#define ICBID_MASTER_BIMC_SNOC 21 +#define ICBID_MASTER_BIMC_SNOC_0 ICBID_MASTER_BIMC_SNOC +#define ICBID_MASTER_CNOC_SNOC 22 +#define ICBID_MASTER_CRYPTO 23 +#define ICBID_MASTER_CRYPTO_CORE0 ICBID_MASTER_CRYPTO +#define ICBID_MASTER_CRYPTO_CORE1 24 +#define ICBID_MASTER_LPASS_PROC 25 +#define ICBID_MASTER_MSS 26 +#define ICBID_MASTER_MSS_NAV 27 +#define ICBID_MASTER_OCMEM_DMA 28 +#define ICBID_MASTER_PNOC_SNOC 29 +#define ICBID_MASTER_WCSS 30 +#define ICBID_MASTER_QDSS_ETR 31 +#define ICBID_MASTER_USB3 32 +#define ICBID_MASTER_USB3_0 ICBID_MASTER_USB3 +#define ICBID_MASTER_SDCC_1 33 +#define ICBID_MASTER_SDCC_3 34 +#define ICBID_MASTER_SDCC_2 35 +#define ICBID_MASTER_SDCC_4 36 +#define ICBID_MASTER_TSIF 37 +#define ICBID_MASTER_BAM_DMA 38 +#define ICBID_MASTER_BLSP_2 39 +#define ICBID_MASTER_USB_HSIC 40 +#define ICBID_MASTER_BLSP_1 41 +#define ICBID_MASTER_USB_HS 42 +#define ICBID_MASTER_USB_HS1 ICBID_MASTER_USB_HS +#define ICBID_MASTER_PNOC_CFG 43 +#define ICBID_MASTER_SNOC_PNOC 44 +#define ICBID_MASTER_RPM_INST 45 +#define ICBID_MASTER_RPM_DATA 46 +#define ICBID_MASTER_RPM_SYS 47 +#define ICBID_MASTER_DEHR 48 +#define ICBID_MASTER_QDSS_DAP 49 +#define ICBID_MASTER_SPDM 50 +#define ICBID_MASTER_TIC 51 +#define ICBID_MASTER_SNOC_CNOC 52 +#define ICBID_MASTER_GFX3D_OCMEM 53 +#define ICBID_MASTER_GFX3D_GMEM ICBID_MASTER_GFX3D_OCMEM +#define ICBID_MASTER_OVIRT_SNOC 54 +#define ICBID_MASTER_SNOC_OVIRT 55 +#define ICBID_MASTER_SNOC_GVIRT ICBID_MASTER_SNOC_OVIRT +#define ICBID_MASTER_ONOC_OVIRT 56 +#define ICBID_MASTER_USB_HS2 57 +#define ICBID_MASTER_QPIC 58 +#define ICBID_MASTER_IPA 59 +#define ICBID_MASTER_DSI 60 +#define ICBID_MASTER_MDP1 61 +#define ICBID_MASTER_MDPE ICBID_MASTER_MDP1 +#define ICBID_MASTER_VPU_PROC 62 +#define ICBID_MASTER_VPU 63 +#define ICBID_MASTER_VPU0 ICBID_MASTER_VPU +#define ICBID_MASTER_CRYPTO_CORE2 64 +#define ICBID_MASTER_PCIE_0 65 +#define ICBID_MASTER_PCIE_1 66 +#define ICBID_MASTER_SATA 67 +#define ICBID_MASTER_UFS 68 +#define ICBID_MASTER_USB3_1 69 +#define ICBID_MASTER_VIDEO_OCMEM 70 +#define ICBID_MASTER_VPU1 71 +#define ICBID_MASTER_VCAP 72 +#define ICBID_MASTER_EMAC 73 +#define ICBID_MASTER_BCAST 74 +#define ICBID_MASTER_MMSS_PROC 75 +#define ICBID_MASTER_SNOC_BIMC_1 76 +#define ICBID_MASTER_SNOC_PCNOC 77 +#define ICBID_MASTER_AUDIO 78 +#define ICBID_MASTER_MM_INT_0 79 +#define ICBID_MASTER_MM_INT_1 80 +#define ICBID_MASTER_MM_INT_2 81 +#define ICBID_MASTER_MM_INT_BIMC 82 +#define ICBID_MASTER_MSS_INT 83 +#define ICBID_MASTER_PCNOC_CFG 84 +#define ICBID_MASTER_PCNOC_INT_0 85 +#define ICBID_MASTER_PCNOC_INT_1 86 +#define ICBID_MASTER_PCNOC_M_0 87 +#define ICBID_MASTER_PCNOC_M_1 88 +#define ICBID_MASTER_PCNOC_S_0 89 +#define ICBID_MASTER_PCNOC_S_1 90 +#define ICBID_MASTER_PCNOC_S_2 91 +#define ICBID_MASTER_PCNOC_S_3 92 +#define ICBID_MASTER_PCNOC_S_4 93 +#define ICBID_MASTER_PCNOC_S_6 94 +#define ICBID_MASTER_PCNOC_S_7 95 +#define ICBID_MASTER_PCNOC_S_8 96 +#define ICBID_MASTER_PCNOC_S_9 97 +#define ICBID_MASTER_QDSS_INT 98 +#define ICBID_MASTER_SNOC_INT_0 99 +#define ICBID_MASTER_SNOC_INT_1 100 +#define ICBID_MASTER_SNOC_INT_BIMC 101 +#define ICBID_MASTER_TCU_0 102 +#define ICBID_MASTER_TCU_1 103 +#define ICBID_MASTER_BIMC_INT_0 104 +#define ICBID_MASTER_BIMC_INT_1 105 +#define ICBID_MASTER_CAMERA 106 +#define ICBID_MASTER_RICA 107 +#define ICBID_MASTER_SNOC_BIMC_2 108 +#define ICBID_MASTER_BIMC_SNOC_1 109 +#define ICBID_MASTER_A0NOC_SNOC 110 +#define ICBID_MASTER_A1NOC_SNOC 111 +#define ICBID_MASTER_A2NOC_SNOC 112 +#define ICBID_MASTER_PIMEM 113 +#define ICBID_MASTER_SNOC_VMEM 114 +#define ICBID_MASTER_CPP 115 +#define ICBID_MASTER_CNOC_A1NOC 116 +#define ICBID_MASTER_PNOC_A1NOC 117 +#define ICBID_MASTER_HMSS 118 +#define ICBID_MASTER_PCIE_2 119 +#define ICBID_MASTER_ROTATOR 120 +#define ICBID_MASTER_VENUS_VMEM 121 +#define ICBID_MASTER_DCC 122 +#define ICBID_MASTER_MCDMA 123 +#define ICBID_MASTER_PCNOC_INT_2 124 +#define ICBID_MASTER_PCNOC_INT_3 125 +#define ICBID_MASTER_PCNOC_INT_4 126 +#define ICBID_MASTER_PCNOC_INT_5 127 +#define ICBID_MASTER_PCNOC_INT_6 128 +#define ICBID_MASTER_PCNOC_S_5 129 +#define ICBID_MASTER_SENSORS_AHB 130 +#define ICBID_MASTER_SENSORS_PROC 131 +#define ICBID_MASTER_QSPI 132 +#define ICBID_MASTER_VFE1 133 +#define ICBID_MASTER_SNOC_INT_2 134 +#define ICBID_MASTER_SMMNOC_BIMC 135 +#define ICBID_MASTER_CRVIRT_A1NOC 136 +#define ICBID_MASTER_XM_USB_HS1 137 +#define ICBID_MASTER_XI_USB_HS1 138 +#define ICBID_MASTER_PCNOC_BIMC_1 139 +#define ICBID_MASTER_BIMC_PCNOC 140 +#define ICBID_MASTER_XI_HSIC 141 +#define ICBID_MASTER_SGMII 142 +#define ICBID_MASTER_SPMI_FETCHER 143 +#define ICBID_MASTER_GNOC_BIMC 144 +#define ICBID_MASTER_CRVIRT_A2NOC 145 +#define ICBID_MASTER_CNOC_A2NOC 146 +#define ICBID_MASTER_WLAN 147 +#define ICBID_MASTER_MSS_CE 148 +#define ICBID_MASTER_CDSP_PROC 149 +#define ICBID_MASTER_GNOC_SNOC 150 + +#define ICBID_SLAVE_EBI1 0 +#define ICBID_SLAVE_APPSS_L2 1 +#define ICBID_SLAVE_BIMC_SNOC 2 +#define ICBID_SLAVE_BIMC_SNOC_0 ICBID_SLAVE_BIMC_SNOC +#define ICBID_SLAVE_CAMERA_CFG 3 +#define ICBID_SLAVE_DISPLAY_CFG 4 +#define ICBID_SLAVE_OCMEM_CFG 5 +#define ICBID_SLAVE_CPR_CFG 6 +#define ICBID_SLAVE_CPR_XPU_CFG 7 +#define ICBID_SLAVE_MISC_CFG 8 +#define ICBID_SLAVE_MISC_XPU_CFG 9 +#define ICBID_SLAVE_VENUS_CFG 10 +#define ICBID_SLAVE_GFX3D_CFG 11 +#define ICBID_SLAVE_MMSS_CLK_CFG 12 +#define ICBID_SLAVE_MMSS_CLK_XPU_CFG 13 +#define ICBID_SLAVE_MNOC_MPU_CFG 14 +#define ICBID_SLAVE_ONOC_MPU_CFG 15 +#define ICBID_SLAVE_MNOC_BIMC 16 +#define ICBID_SLAVE_SERVICE_MNOC 17 +#define ICBID_SLAVE_OCMEM 18 +#define ICBID_SLAVE_GMEM ICBID_SLAVE_OCMEM +#define ICBID_SLAVE_SERVICE_ONOC 19 +#define ICBID_SLAVE_APPSS 20 +#define ICBID_SLAVE_LPASS 21 +#define ICBID_SLAVE_USB3 22 +#define ICBID_SLAVE_USB3_0 ICBID_SLAVE_USB3 +#define ICBID_SLAVE_WCSS 23 +#define ICBID_SLAVE_SNOC_BIMC 24 +#define ICBID_SLAVE_SNOC_BIMC_0 ICBID_SLAVE_SNOC_BIMC +#define ICBID_SLAVE_SNOC_CNOC 25 +#define ICBID_SLAVE_IMEM 26 +#define ICBID_SLAVE_OCIMEM ICBID_SLAVE_IMEM +#define ICBID_SLAVE_SNOC_OVIRT 27 +#define ICBID_SLAVE_SNOC_GVIRT ICBID_SLAVE_SNOC_OVIRT +#define ICBID_SLAVE_SNOC_PNOC 28 +#define ICBID_SLAVE_SNOC_PCNOC ICBID_SLAVE_SNOC_PNOC +#define ICBID_SLAVE_SERVICE_SNOC 29 +#define ICBID_SLAVE_QDSS_STM 30 +#define ICBID_SLAVE_SDCC_1 31 +#define ICBID_SLAVE_SDCC_3 32 +#define ICBID_SLAVE_SDCC_2 33 +#define ICBID_SLAVE_SDCC_4 34 +#define ICBID_SLAVE_TSIF 35 +#define ICBID_SLAVE_BAM_DMA 36 +#define ICBID_SLAVE_BLSP_2 37 +#define ICBID_SLAVE_USB_HSIC 38 +#define ICBID_SLAVE_BLSP_1 39 +#define ICBID_SLAVE_USB_HS 40 +#define ICBID_SLAVE_USB_HS1 ICBID_SLAVE_USB_HS +#define ICBID_SLAVE_PDM 41 +#define ICBID_SLAVE_PERIPH_APU_CFG 42 +#define ICBID_SLAVE_PNOC_MPU_CFG 43 +#define ICBID_SLAVE_PRNG 44 +#define ICBID_SLAVE_PNOC_SNOC 45 +#define ICBID_SLAVE_PCNOC_SNOC ICBID_SLAVE_PNOC_SNOC +#define ICBID_SLAVE_SERVICE_PNOC 46 +#define ICBID_SLAVE_CLK_CTL 47 +#define ICBID_SLAVE_CNOC_MSS 48 +#define ICBID_SLAVE_PCNOC_MSS ICBID_SLAVE_CNOC_MSS +#define ICBID_SLAVE_SECURITY 49 +#define ICBID_SLAVE_TCSR 50 +#define ICBID_SLAVE_TLMM 51 +#define ICBID_SLAVE_CRYPTO_0_CFG 52 +#define ICBID_SLAVE_CRYPTO_1_CFG 53 +#define ICBID_SLAVE_IMEM_CFG 54 +#define ICBID_SLAVE_MESSAGE_RAM 55 +#define ICBID_SLAVE_BIMC_CFG 56 +#define ICBID_SLAVE_BOOT_ROM 57 +#define ICBID_SLAVE_CNOC_MNOC_MMSS_CFG 58 +#define ICBID_SLAVE_PMIC_ARB 59 +#define ICBID_SLAVE_SPDM_WRAPPER 60 +#define ICBID_SLAVE_DEHR_CFG 61 +#define ICBID_SLAVE_MPM 62 +#define ICBID_SLAVE_QDSS_CFG 63 +#define ICBID_SLAVE_RBCPR_CFG 64 +#define ICBID_SLAVE_RBCPR_CX_CFG ICBID_SLAVE_RBCPR_CFG +#define ICBID_SLAVE_RBCPR_QDSS_APU_CFG 65 +#define ICBID_SLAVE_CNOC_MNOC_CFG 66 +#define ICBID_SLAVE_SNOC_MPU_CFG 67 +#define ICBID_SLAVE_CNOC_ONOC_CFG 68 +#define ICBID_SLAVE_PNOC_CFG 69 +#define ICBID_SLAVE_SNOC_CFG 70 +#define ICBID_SLAVE_EBI1_DLL_CFG 71 +#define ICBID_SLAVE_PHY_APU_CFG 72 +#define ICBID_SLAVE_EBI1_PHY_CFG 73 +#define ICBID_SLAVE_RPM 74 +#define ICBID_SLAVE_CNOC_SNOC 75 +#define ICBID_SLAVE_SERVICE_CNOC 76 +#define ICBID_SLAVE_OVIRT_SNOC 77 +#define ICBID_SLAVE_OVIRT_OCMEM 78 +#define ICBID_SLAVE_USB_HS2 79 +#define ICBID_SLAVE_QPIC 80 +#define ICBID_SLAVE_IPS_CFG 81 +#define ICBID_SLAVE_DSI_CFG 82 +#define ICBID_SLAVE_USB3_1 83 +#define ICBID_SLAVE_PCIE_0 84 +#define ICBID_SLAVE_PCIE_1 85 +#define ICBID_SLAVE_PSS_SMMU_CFG 86 +#define ICBID_SLAVE_CRYPTO_2_CFG 87 +#define ICBID_SLAVE_PCIE_0_CFG 88 +#define ICBID_SLAVE_PCIE_1_CFG 89 +#define ICBID_SLAVE_SATA_CFG 90 +#define ICBID_SLAVE_SPSS_GENI_IR 91 +#define ICBID_SLAVE_UFS_CFG 92 +#define ICBID_SLAVE_AVSYNC_CFG 93 +#define ICBID_SLAVE_VPU_CFG 94 +#define ICBID_SLAVE_USB_PHY_CFG 95 +#define ICBID_SLAVE_RBCPR_MX_CFG 96 +#define ICBID_SLAVE_PCIE_PARF 97 +#define ICBID_SLAVE_VCAP_CFG 98 +#define ICBID_SLAVE_EMAC_CFG 99 +#define ICBID_SLAVE_BCAST_CFG 100 +#define ICBID_SLAVE_KLM_CFG 101 +#define ICBID_SLAVE_DISPLAY_PWM 102 +#define ICBID_SLAVE_GENI 103 +#define ICBID_SLAVE_SNOC_BIMC_1 104 +#define ICBID_SLAVE_AUDIO 105 +#define ICBID_SLAVE_CATS_0 106 +#define ICBID_SLAVE_CATS_1 107 +#define ICBID_SLAVE_MM_INT_0 108 +#define ICBID_SLAVE_MM_INT_1 109 +#define ICBID_SLAVE_MM_INT_2 110 +#define ICBID_SLAVE_MM_INT_BIMC 111 +#define ICBID_SLAVE_MMU_MODEM_XPU_CFG 112 +#define ICBID_SLAVE_MSS_INT 113 +#define ICBID_SLAVE_PCNOC_INT_0 114 +#define ICBID_SLAVE_PCNOC_INT_1 115 +#define ICBID_SLAVE_PCNOC_M_0 116 +#define ICBID_SLAVE_PCNOC_M_1 117 +#define ICBID_SLAVE_PCNOC_S_0 118 +#define ICBID_SLAVE_PCNOC_S_1 119 +#define ICBID_SLAVE_PCNOC_S_2 120 +#define ICBID_SLAVE_PCNOC_S_3 121 +#define ICBID_SLAVE_PCNOC_S_4 122 +#define ICBID_SLAVE_PCNOC_S_6 123 +#define ICBID_SLAVE_PCNOC_S_7 124 +#define ICBID_SLAVE_PCNOC_S_8 125 +#define ICBID_SLAVE_PCNOC_S_9 126 +#define ICBID_SLAVE_PRNG_XPU_CFG 127 +#define ICBID_SLAVE_QDSS_INT 128 +#define ICBID_SLAVE_RPM_XPU_CFG 129 +#define ICBID_SLAVE_SNOC_INT_0 130 +#define ICBID_SLAVE_SNOC_INT_1 131 +#define ICBID_SLAVE_SNOC_INT_BIMC 132 +#define ICBID_SLAVE_TCU 133 +#define ICBID_SLAVE_BIMC_INT_0 134 +#define ICBID_SLAVE_BIMC_INT_1 135 +#define ICBID_SLAVE_RICA_CFG 136 +#define ICBID_SLAVE_SNOC_BIMC_2 137 +#define ICBID_SLAVE_BIMC_SNOC_1 138 +#define ICBID_SLAVE_PNOC_A1NOC 139 +#define ICBID_SLAVE_SNOC_VMEM 140 +#define ICBID_SLAVE_A0NOC_SNOC 141 +#define ICBID_SLAVE_A1NOC_SNOC 142 +#define ICBID_SLAVE_A2NOC_SNOC 143 +#define ICBID_SLAVE_A0NOC_CFG 144 +#define ICBID_SLAVE_A0NOC_MPU_CFG 145 +#define ICBID_SLAVE_A0NOC_SMMU_CFG 146 +#define ICBID_SLAVE_A1NOC_CFG 147 +#define ICBID_SLAVE_A1NOC_MPU_CFG 148 +#define ICBID_SLAVE_A1NOC_SMMU_CFG 149 +#define ICBID_SLAVE_A2NOC_CFG 150 +#define ICBID_SLAVE_A2NOC_MPU_CFG 151 +#define ICBID_SLAVE_A2NOC_SMMU_CFG 152 +#define ICBID_SLAVE_AHB2PHY 153 +#define ICBID_SLAVE_CAMERA_THROTTLE_CFG 154 +#define ICBID_SLAVE_DCC_CFG 155 +#define ICBID_SLAVE_DISPLAY_THROTTLE_CFG 156 +#define ICBID_SLAVE_DSA_CFG 157 +#define ICBID_SLAVE_DSA_MPU_CFG 158 +#define ICBID_SLAVE_SSC_MPU_CFG 159 +#define ICBID_SLAVE_HMSS_L3 160 +#define ICBID_SLAVE_LPASS_SMMU_CFG 161 +#define ICBID_SLAVE_MMAGIC_CFG 162 +#define ICBID_SLAVE_PCIE20_AHB2PHY 163 +#define ICBID_SLAVE_PCIE_2 164 +#define ICBID_SLAVE_PCIE_2_CFG 165 +#define ICBID_SLAVE_PIMEM 166 +#define ICBID_SLAVE_PIMEM_CFG 167 +#define ICBID_SLAVE_QDSS_RBCPR_APU_CFG 168 +#define ICBID_SLAVE_RBCPR_CX 169 +#define ICBID_SLAVE_RBCPR_MX 170 +#define ICBID_SLAVE_SMMU_CPP_CFG 171 +#define ICBID_SLAVE_SMMU_JPEG_CFG 172 +#define ICBID_SLAVE_SMMU_MDP_CFG 173 +#define ICBID_SLAVE_SMMU_ROTATOR_CFG 174 +#define ICBID_SLAVE_SMMU_VENUS_CFG 175 +#define ICBID_SLAVE_SMMU_VFE_CFG 176 +#define ICBID_SLAVE_SSC_CFG 177 +#define ICBID_SLAVE_VENUS_THROTTLE_CFG 178 +#define ICBID_SLAVE_VMEM 179 +#define ICBID_SLAVE_VMEM_CFG 180 +#define ICBID_SLAVE_QDSS_MPU_CFG 181 +#define ICBID_SLAVE_USB3_PHY_CFG 182 +#define ICBID_SLAVE_IPA_CFG 183 +#define ICBID_SLAVE_PCNOC_INT_2 184 +#define ICBID_SLAVE_PCNOC_INT_3 185 +#define ICBID_SLAVE_PCNOC_INT_4 186 +#define ICBID_SLAVE_PCNOC_INT_5 187 +#define ICBID_SLAVE_PCNOC_INT_6 188 +#define ICBID_SLAVE_PCNOC_S_5 189 +#define ICBID_SLAVE_QSPI 190 +#define ICBID_SLAVE_A1NOC_MS_MPU_CFG 191 +#define ICBID_SLAVE_A2NOC_MS_MPU_CFG 192 +#define ICBID_SLAVE_MODEM_Q6_SMMU_CFG 193 +#define ICBID_SLAVE_MSS_MPU_CFG 194 +#define ICBID_SLAVE_MSS_PROC_MS_MPU_CFG 195 +#define ICBID_SLAVE_SKL 196 +#define ICBID_SLAVE_SNOC_INT_2 197 +#define ICBID_SLAVE_SMMNOC_BIMC 198 +#define ICBID_SLAVE_CRVIRT_A1NOC 199 +#define ICBID_SLAVE_SGMII 200 +#define ICBID_SLAVE_QHS4_APPS 201 +#define ICBID_SLAVE_BIMC_PCNOC 202 +#define ICBID_SLAVE_PCNOC_BIMC_1 203 +#define ICBID_SLAVE_SPMI_FETCHER 204 +#define ICBID_SLAVE_MMSS_SMMU_CFG 205 +#define ICBID_SLAVE_WLAN 206 +#define ICBID_SLAVE_CRVIRT_A2NOC 207 +#define ICBID_SLAVE_CNOC_A2NOC 208 +#define ICBID_SLAVE_GLM 209 +#define ICBID_SLAVE_GNOC_BIMC 210 +#define ICBID_SLAVE_GNOC_SNOC 211 +#define ICBID_SLAVE_QM_CFG 212 +#define ICBID_SLAVE_TLMM_EAST 213 +#define ICBID_SLAVE_TLMM_NORTH 214 +#define ICBID_SLAVE_TLMM_WEST 215 +#define ICBID_SLAVE_LPASS_TCM 216 +#define ICBID_SLAVE_TLMM_SOUTH 217 +#define ICBID_SLAVE_TLMM_CENTER 218 +#define ICBID_SLAVE_MSS_NAV_CE_MPU_CFG 219 +#define ICBID_SLAVE_A2NOC_THROTTLE_CFG 220 +#define ICBID_SLAVE_CDSP 221 +#define ICBID_SLAVE_CDSP_SMMU_CFG 222 +#define ICBID_SLAVE_LPASS_MPU_CFG 223 +#define ICBID_SLAVE_CSI_PHY_CFG 224 +#endif diff -Nruw linux-4.4.115-fbx/arch/powerpc/boot/dts/include/dt-bindings/msm./msm-bus-rule-ops.h linux-4.4.115-fbx/arch/powerpc/boot/dts/include/dt-bindings/msm/msm-bus-rule-ops.h --- linux-4.4.115-fbx/arch/powerpc/boot/dts/include/dt-bindings/msm./msm-bus-rule-ops.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-4.4.115-fbx/arch/powerpc/boot/dts/include/dt-bindings/msm/msm-bus-rule-ops.h 2019-01-22 16:16:28.179288750 +0100 @@ -0,0 +1,34 @@ +/* Copyright (c) 2014, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __MSM_BUS_RULE_OPS_H +#define __MSM_BUS_RULE_OPS_H + +#define FLD_IB 0 +#define FLD_AB 1 +#define FLD_CLK 2 + +#define OP_LE 0 +#define OP_LT 1 +#define OP_GE 2 +#define OP_GT 3 +#define OP_NOOP 4 + +#define RULE_STATE_NOT_APPLIED 0 +#define RULE_STATE_APPLIED 1 + +#define THROTTLE_ON 0 +#define THROTTLE_OFF 1 +#define THROTTLE_REG 2 + + +#endif diff -Nruw linux-4.4.115-fbx/arch/powerpc/boot/dts/include/dt-bindings/msm./pm.h linux-4.4.115-fbx/arch/powerpc/boot/dts/include/dt-bindings/msm/pm.h --- linux-4.4.115-fbx/arch/powerpc/boot/dts/include/dt-bindings/msm./pm.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-4.4.115-fbx/arch/powerpc/boot/dts/include/dt-bindings/msm/pm.h 2019-01-22 16:16:28.179288750 +0100 @@ -0,0 +1,25 @@ +/* Copyright (c) 2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __DT_MSM_PM_H__ +#define __DT_MSM_PM_H__ + +#define LPM_RESET_LVL_NONE 0 +#define LPM_RESET_LVL_RET 1 +#define LPM_RESET_LVL_GDHS 2 +#define LPM_RESET_LVL_PC 3 + +#define LPM_AFF_LVL_CPU 0 +#define LPM_AFF_LVL_L2 1 +#define LPM_AFF_LVL_CCI 2 + +#endif diff -Nruw linux-4.4.115-fbx/arch/powerpc/boot/dts/include/dt-bindings/msm./power-on.h linux-4.4.115-fbx/arch/powerpc/boot/dts/include/dt-bindings/msm/power-on.h --- linux-4.4.115-fbx/arch/powerpc/boot/dts/include/dt-bindings/msm./power-on.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-4.4.115-fbx/arch/powerpc/boot/dts/include/dt-bindings/msm/power-on.h 2019-01-22 16:16:28.179288750 +0100 @@ -0,0 +1,24 @@ +/* Copyright (c) 2015, 2017, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __MSM_POWER_ON_H__ +#define __MSM_POWER_ON_H__ + +#define PON_POWER_OFF_RESERVED 0x00 +#define PON_POWER_OFF_WARM_RESET 0x01 +#define PON_POWER_OFF_SHUTDOWN 0x04 +#define PON_POWER_OFF_DVDD_SHUTDOWN 0x05 +#define PON_POWER_OFF_HARD_RESET 0x07 +#define PON_POWER_OFF_DVDD_HARD_RESET 0x08 +#define PON_POWER_OFF_MAX_TYPE 0x10 + +#endif --- /dev/null 2019-10-24 16:47:25.704025805 +0200 +++ linux-4.4.115-fbx/arch/powerpc/boot/dts/include/dt-bindings/regulator/qcom,rpm-smd-regulator.h 2019-01-22 16:16:28.183288787 +0100 @@ -0,0 +1,28 @@ +/* Copyright (c) 2015, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __QCOM_RPM_SMD_REGULATOR_H +#define __QCOM_RPM_SMD_REGULATOR_H + +#define RPM_SMD_REGULATOR_LEVEL_NONE 0 +#define RPM_SMD_REGULATOR_LEVEL_RETENTION 16 +#define RPM_SMD_REGULATOR_LEVEL_RETENTION_PLUS 32 +#define RPM_SMD_REGULATOR_LEVEL_MIN_SVS 48 +#define RPM_SMD_REGULATOR_LEVEL_LOW_SVS 64 +#define RPM_SMD_REGULATOR_LEVEL_SVS 128 +#define RPM_SMD_REGULATOR_LEVEL_SVS_PLUS 192 +#define RPM_SMD_REGULATOR_LEVEL_NOM 256 +#define RPM_SMD_REGULATOR_LEVEL_NOM_PLUS 320 +#define RPM_SMD_REGULATOR_LEVEL_TURBO 384 +#define RPM_SMD_REGULATOR_LEVEL_BINNING 512 + +#endif --- /dev/null 2019-10-24 16:47:25.704025805 +0200 +++ linux-4.4.115-fbx/config 2019-10-29 09:38:15.536162274 +0100 @@ -0,0 +1,4992 @@ +# +# Automatically generated file; DO NOT EDIT. +# Linux/arm64 4.4.115 Kernel Configuration +# +CONFIG_ARM64=y +CONFIG_64BIT=y +CONFIG_ARCH_PHYS_ADDR_T_64BIT=y +CONFIG_MMU=y +CONFIG_ARCH_MMAP_RND_BITS_MIN=18 +CONFIG_ARCH_MMAP_RND_BITS_MAX=24 +CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11 +CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=16 +CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000 +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_RWSEM_XCHGADD_ALGORITHM=y +CONFIG_GENERIC_BUG=y +CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CSUM=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_ZONE_DMA=y +CONFIG_HAVE_GENERIC_RCU_GUP=y +CONFIG_ARCH_DMA_ADDR_T_64BIT=y +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_NEED_SG_DMA_LENGTH=y +CONFIG_SMP=y +CONFIG_ARM64_DMA_USE_IOMMU=y +CONFIG_ARM64_DMA_IOMMU_ALIGNMENT=9 +CONFIG_SWIOTLB=y +CONFIG_IOMMU_HELPER=y +CONFIG_KERNEL_MODE_NEON=y +CONFIG_FIX_EARLYCON_MEM=y +CONFIG_PGTABLE_LEVELS=3 +# CONFIG_MSM_GVM_QUIN is not set +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" +CONFIG_IRQ_WORK=y +CONFIG_BUILDTIME_EXTABLE_SORT=y +CONFIG_THREAD_INFO_IN_TASK=y + +# +# General setup +# +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_CROSS_COMPILE="/opt/toolchains/aarch64-glibc-2.25-gcc-6.3.0-binutils-2.28-gdb-7.12.1/bin/aarch64-linux-gnu-" +# CONFIG_COMPILE_TEST is not set +CONFIG_LOCALVERSION="" +# CONFIG_LOCALVERSION_AUTO is not set +CONFIG_DEFAULT_HOSTNAME="fbx7hd" +# CONFIG_SWAP is not set +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +CONFIG_POSIX_MQUEUE=y +CONFIG_POSIX_MQUEUE_SYSCTL=y +# CONFIG_CROSS_MEMORY_ATTACH is not set +# CONFIG_FHANDLE is not set +# CONFIG_USELIB is not set +CONFIG_AUDIT=y +CONFIG_HAVE_ARCH_AUDITSYSCALL=y +CONFIG_AUDITSYSCALL=y +CONFIG_AUDIT_WATCH=y +CONFIG_AUDIT_TREE=y + +# +# IRQ subsystem +# +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_GENERIC_IRQ_SHOW=y +CONFIG_GENERIC_IRQ_SHOW_LEVEL=y +CONFIG_GENERIC_IRQ_MIGRATION=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_IRQ_DOMAIN=y +CONFIG_IRQ_DOMAIN_HIERARCHY=y +CONFIG_GENERIC_MSI_IRQ=y +CONFIG_GENERIC_MSI_IRQ_DOMAIN=y +CONFIG_HANDLE_DOMAIN_IRQ=y +# CONFIG_IRQ_DOMAIN_DEBUG is not set +CONFIG_IRQ_FORCED_THREADING=y +CONFIG_SPARSE_IRQ=y +CONFIG_GENERIC_TIME_VSYSCALL=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_ARCH_HAS_TICK_BROADCAST=y +CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y + +# +# Timers subsystem +# +CONFIG_TICK_ONESHOT=y +CONFIG_NO_HZ_COMMON=y +# CONFIG_HZ_PERIODIC is not set +CONFIG_NO_HZ_IDLE=y +# CONFIG_NO_HZ_FULL is not set +# CONFIG_NO_HZ is not set +CONFIG_HIGH_RES_TIMERS=y + +# +# CPU/Task time and stats accounting +# +# CONFIG_TICK_CPU_ACCOUNTING is not set +# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set +CONFIG_IRQ_TIME_ACCOUNTING=y +# CONFIG_SCHED_WALT is not set +# CONFIG_BSD_PROCESS_ACCT is not set +CONFIG_TASKSTATS=y +CONFIG_TASK_DELAY_ACCT=y +CONFIG_TASK_XACCT=y +CONFIG_TASK_IO_ACCOUNTING=y + +# +# RCU Subsystem +# +CONFIG_PREEMPT_RCU=y +CONFIG_RCU_EXPERT=y +CONFIG_SRCU=y +# CONFIG_TASKS_RCU is not set +CONFIG_RCU_STALL_COMMON=y +CONFIG_RCU_FANOUT=64 +CONFIG_RCU_FANOUT_LEAF=16 +CONFIG_RCU_FAST_NO_HZ=y +# CONFIG_TREE_RCU_TRACE is not set +# CONFIG_RCU_BOOST is not set +CONFIG_RCU_KTHREAD_PRIO=0 +CONFIG_RCU_NOCB_CPU=y +# CONFIG_RCU_NOCB_CPU_NONE is not set +# CONFIG_RCU_NOCB_CPU_ZERO is not set +CONFIG_RCU_NOCB_CPU_ALL=y +# CONFIG_RCU_EXPEDITE_BOOT is not set +CONFIG_BUILD_BIN2C=y +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_LOG_BUF_SHIFT=17 +CONFIG_LOG_CPU_MAX_BUF_SHIFT=17 +# CONFIG_FBX_DECRYPT_INITRD is not set +CONFIG_GENERIC_SCHED_CLOCK=y +CONFIG_CGROUPS=y +# CONFIG_CGROUP_DEBUG is not set +CONFIG_CGROUP_FREEZER=y +# CONFIG_CGROUP_PIDS is not set +CONFIG_CGROUP_DEVICE=y +CONFIG_CPUSETS=y +CONFIG_PROC_PID_CPUSET=y +CONFIG_CGROUP_CPUACCT=y +CONFIG_CGROUP_SCHEDTUNE=y +# CONFIG_MEMCG is not set +# CONFIG_CGROUP_PERF is not set +CONFIG_CGROUP_SCHED=y +CONFIG_FAIR_GROUP_SCHED=y +# CONFIG_CFS_BANDWIDTH is not set +CONFIG_RT_GROUP_SCHED=y +# CONFIG_BLK_CGROUP is not set +CONFIG_SCHED_HMP=y +CONFIG_SCHED_HMP_CSTATE_AWARE=y +CONFIG_SCHED_CORE_CTL=y +# CONFIG_CHECKPOINT_RESTORE is not set +CONFIG_NAMESPACES=y +CONFIG_UTS_NS=y +CONFIG_IPC_NS=y +# CONFIG_USER_NS is not set +CONFIG_PID_NS=y +CONFIG_NET_NS=y +CONFIG_SCHED_AUTOGROUP=y +CONFIG_SCHED_TUNE=y +# CONFIG_DEFAULT_USE_ENERGY_AWARE is not set +# CONFIG_SYSFS_DEPRECATED is not set +CONFIG_RELAY=y +CONFIG_BLK_DEV_INITRD=y +CONFIG_INITRAMFS_SOURCE="" +# CONFIG_RD_GZIP is not set +# CONFIG_RD_BZIP2 is not set +# CONFIG_RD_LZMA is not set +# CONFIG_RD_XZ is not set +# CONFIG_RD_LZO is not set +# CONFIG_RD_LZ4 is not set +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_SYSCTL=y +CONFIG_ANON_INODES=y +CONFIG_HAVE_UID16=y +CONFIG_SYSCTL_EXCEPTION_TRACE=y +CONFIG_BPF=y +CONFIG_EXPERT=y +CONFIG_UID16=y +CONFIG_MULTIUSER=y +# CONFIG_SGETMASK_SYSCALL is not set +# CONFIG_SYSFS_SYSCALL is not set +# CONFIG_SYSCTL_SYSCALL is not set +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_ALL is not set +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +# CONFIG_BPF_SYSCALL is not set +CONFIG_SHMEM=y +# CONFIG_AIO is not set +CONFIG_ADVISE_SYSCALLS=y +# CONFIG_USERFAULTFD is not set +CONFIG_PCI_QUIRKS=y +# CONFIG_MEMBARRIER is not set +CONFIG_EMBEDDED=y +CONFIG_HAVE_PERF_EVENTS=y +CONFIG_PERF_USE_VMALLOC=y + +# +# Kernel Performance Events And Counters +# +CONFIG_PERF_EVENTS=y +# CONFIG_DEBUG_PERF_USE_VMALLOC is not set +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_SLUB_DEBUG=y +# CONFIG_COMPAT_BRK is not set +# CONFIG_SLAB is not set +CONFIG_SLUB=y +# CONFIG_SLOB is not set +CONFIG_SLUB_CPU_PARTIAL=y +# CONFIG_SYSTEM_DATA_VERIFICATION is not set +# CONFIG_PROFILING is not set +CONFIG_TRACEPOINTS=y +# CONFIG_KPROBES is not set +# CONFIG_JUMP_LABEL is not set +# CONFIG_UPROBES is not set +# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set +CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y +CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KRETPROBES=y +CONFIG_HAVE_ARCH_TRACEHOOK=y +CONFIG_HAVE_DMA_ATTRS=y +CONFIG_HAVE_DMA_CONTIGUOUS=y +CONFIG_GENERIC_SMP_IDLE_THREAD=y +CONFIG_GENERIC_IDLE_POLL_SETUP=y +CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y +CONFIG_HAVE_CLK=y +CONFIG_HAVE_DMA_API_DEBUG=y +CONFIG_HAVE_PERF_REGS=y +CONFIG_HAVE_PERF_USER_STACK_DUMP=y +CONFIG_HAVE_ARCH_JUMP_LABEL=y +CONFIG_HAVE_RCU_TABLE_FREE=y +CONFIG_HAVE_ALIGNED_STRUCT_PAGE=y +CONFIG_HAVE_CMPXCHG_LOCAL=y +CONFIG_HAVE_CMPXCHG_DOUBLE=y +CONFIG_ARCH_WANT_COMPAT_IPC_PARSE_VERSION=y +CONFIG_HAVE_ARCH_SECCOMP_FILTER=y +CONFIG_SECCOMP_FILTER=y +CONFIG_HAVE_CC_STACKPROTECTOR=y +CONFIG_CC_STACKPROTECTOR=y +# CONFIG_CC_STACKPROTECTOR_NONE is not set +CONFIG_CC_STACKPROTECTOR_REGULAR=y +# CONFIG_CC_STACKPROTECTOR_STRONG is not set +CONFIG_HAVE_CONTEXT_TRACKING=y +CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y +CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y +CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE=y +CONFIG_HAVE_ARCH_HUGE_VMAP=y +CONFIG_MODULES_USE_ELF_RELA=y +CONFIG_ARCH_HAS_ELF_RANDOMIZE=y +CONFIG_HAVE_ARCH_MMAP_RND_BITS=y +CONFIG_ARCH_MMAP_RND_BITS=18 +CONFIG_HAVE_ARCH_MMAP_RND_COMPAT_BITS=y +CONFIG_ARCH_MMAP_RND_COMPAT_BITS=16 +CONFIG_CLONE_BACKWARDS=y +CONFIG_OLD_SIGSUSPEND3=y +CONFIG_COMPAT_OLD_SIGACTION=y + +# +# GCOV-based kernel profiling +# +# CONFIG_GCOV_KERNEL is not set +CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y +CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_SLABINFO=y +CONFIG_RT_MUTEXES=y +CONFIG_BASE_SMALL=0 +CONFIG_MODULES=y +# CONFIG_MODULE_FORCE_LOAD is not set +CONFIG_MODULE_UNLOAD=y +CONFIG_MODULE_FORCE_UNLOAD=y +CONFIG_MODVERSIONS=y +# CONFIG_MODULE_SRCVERSION_ALL is not set +# CONFIG_MODULE_SIG is not set +# CONFIG_MODULE_COMPRESS is not set +CONFIG_MODULES_TREE_LOOKUP=y +CONFIG_BLOCK=y +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_BLK_DEV_BSGLIB is not set +# CONFIG_BLK_DEV_INTEGRITY is not set +# CONFIG_BLK_CMDLINE_PARSER is not set +# CONFIG_BLOCK_PERF_FRAMEWORK is not set + +# +# Partition Types +# +CONFIG_PARTITION_ADVANCED=y +# CONFIG_ACORN_PARTITION is not set +# CONFIG_AIX_PARTITION is not set +# CONFIG_OSF_PARTITION is not set +# CONFIG_AMIGA_PARTITION is not set +# CONFIG_ATARI_PARTITION is not set +# CONFIG_MAC_PARTITION is not set +CONFIG_MSDOS_PARTITION=y +# CONFIG_BSD_DISKLABEL is not set +# CONFIG_MINIX_SUBPARTITION is not set +# CONFIG_SOLARIS_X86_PARTITION is not set +# CONFIG_UNIXWARE_DISKLABEL is not set +# CONFIG_LDM_PARTITION is not set +# CONFIG_SGI_PARTITION is not set +# CONFIG_ULTRIX_PARTITION is not set +# CONFIG_SUN_PARTITION is not set +# CONFIG_KARMA_PARTITION is not set +CONFIG_EFI_PARTITION=y +# CONFIG_SYSV68_PARTITION is not set +# CONFIG_CMDLINE_PARTITION is not set +CONFIG_BLOCK_COMPAT=y + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +# CONFIG_IOSCHED_TEST is not set +CONFIG_IOSCHED_DEADLINE=y +CONFIG_IOSCHED_CFQ=y +# CONFIG_DEFAULT_DEADLINE is not set +CONFIG_DEFAULT_CFQ=y +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="cfq" +CONFIG_ASN1=y +CONFIG_UNINLINE_SPIN_UNLOCK=y +CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y +CONFIG_MUTEX_SPIN_ON_OWNER=y +CONFIG_RWSEM_SPIN_ON_OWNER=y +CONFIG_LOCK_SPIN_ON_OWNER=y +CONFIG_FREEZER=y + +# +# Platform selection +# +# CONFIG_ARCH_BCM_IPROC is not set +# CONFIG_ARCH_BERLIN is not set +# CONFIG_ARCH_EXYNOS7 is not set +# CONFIG_ARCH_LAYERSCAPE is not set +# CONFIG_ARCH_HISI is not set +# CONFIG_ARCH_MEDIATEK is not set +CONFIG_ARCH_QCOM=y +# CONFIG_ARCH_MSM8996 is not set +CONFIG_ARCH_MSM8998=y +# CONFIG_ARCH_MSMHAMSTER is not set +# CONFIG_ARCH_SDM660 is not set +# CONFIG_ARCH_SDM630 is not set +# CONFIG_ARCH_ROCKCHIP is not set +# CONFIG_ARCH_SEATTLE is not set +# CONFIG_ARCH_STRATIX10 is not set +# CONFIG_ARCH_TEGRA is not set +# CONFIG_ARCH_SPRD is not set +# CONFIG_ARCH_THUNDER is not set +# CONFIG_ARCH_VEXPRESS is not set +# CONFIG_ARCH_XGENE is not set +# CONFIG_ARCH_ZYNQMP is not set + +# +# Bus support +# +CONFIG_PCI=y +CONFIG_PCI_DOMAINS=y +CONFIG_PCI_DOMAINS_GENERIC=y +CONFIG_PCI_SYSCALL=y +CONFIG_PCI_BUS_ADDR_T_64BIT=y +CONFIG_PCI_MSI=y +CONFIG_PCI_MSI_IRQ_DOMAIN=y +# CONFIG_PCI_DEBUG is not set +# CONFIG_PCI_REALLOC_ENABLE_AUTO is not set +# CONFIG_PCI_STUB is not set +# CONFIG_PCI_IOV is not set +# CONFIG_PCI_PRI is not set +# CONFIG_PCI_PASID is not set +CONFIG_PCI_MSM=y +CONFIG_PCI_LABEL=y + +# +# PCI host controller drivers +# +# CONFIG_PCI_HOST_GENERIC is not set +# CONFIG_PCIE_IPROC is not set +# CONFIG_PCI_HISI is not set +# CONFIG_PCIEPORTBUS is not set +# CONFIG_HOTPLUG_PCI is not set + +# +# Kernel Features +# + +# +# ARM errata workarounds via the alternatives framework +# +CONFIG_ARM64_ERRATUM_826319=y +CONFIG_ARM64_ERRATUM_827319=y +CONFIG_ARM64_ERRATUM_824069=y +CONFIG_ARM64_ERRATUM_819472=y +CONFIG_ARM64_ERRATUM_832075=y +CONFIG_ARM64_ERRATUM_845719=y +CONFIG_ARM64_ERRATUM_843419=y +# CONFIG_CAVIUM_ERRATUM_22375 is not set +# CONFIG_CAVIUM_ERRATUM_23154 is not set +# CONFIG_CAVIUM_ERRATUM_27456 is not set +CONFIG_ARM64_4K_PAGES=y +# CONFIG_ARM64_16K_PAGES is not set +# CONFIG_ARM64_DCACHE_DISABLE is not set +# CONFIG_ARM64_ICACHE_DISABLE is not set +# CONFIG_ARM64_64K_PAGES is not set +CONFIG_ARM64_VA_BITS_39=y +# CONFIG_ARM64_VA_BITS_48 is not set +CONFIG_ARM64_VA_BITS=39 +# CONFIG_CPU_BIG_ENDIAN is not set +CONFIG_SCHED_MC=y +# CONFIG_SCHED_SMT is not set +CONFIG_NR_CPUS=8 +CONFIG_HOTPLUG_CPU=y +CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y +CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y +CONFIG_ARCH_NR_GPIO=1024 +CONFIG_QCOM_TLB_EL2_HANDLER=y +# CONFIG_PREEMPT_NONE is not set +# CONFIG_PREEMPT_VOLUNTARY is not set +CONFIG_PREEMPT=y +CONFIG_PREEMPT_COUNT=y +CONFIG_HZ_100=y +# CONFIG_HZ_250 is not set +# CONFIG_HZ_300 is not set +# CONFIG_HZ_1000 is not set +CONFIG_HZ=100 +CONFIG_SCHED_HRTICK=y +CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y +CONFIG_ARCH_HAS_HOLES_MEMORYMODEL=y +CONFIG_ARCH_SPARSEMEM_ENABLE=y +CONFIG_ARCH_SPARSEMEM_DEFAULT=y +CONFIG_ARCH_SELECT_MEMORY_MODEL=y +CONFIG_HAVE_ARCH_PFN_VALID=y +CONFIG_HW_PERF_EVENTS=y +CONFIG_ARM64_REG_REBALANCE_ON_CTX_SW=y +# CONFIG_PERF_EVENTS_USERMODE is not set +# CONFIG_PERF_EVENTS_RESET_PMU_DEBUGFS is not set +CONFIG_SYS_SUPPORTS_HUGETLBFS=y +CONFIG_ARCH_WANT_HUGE_PMD_SHARE=y +CONFIG_ARCH_HAS_CACHE_LINE_SIZE=y +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_SPARSEMEM_MANUAL=y +CONFIG_SPARSEMEM=y +CONFIG_HAVE_MEMORY_PRESENT=y +CONFIG_SPARSEMEM_EXTREME=y +CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y +CONFIG_SPARSEMEM_VMEMMAP=y +CONFIG_HAVE_MEMBLOCK=y +CONFIG_NO_BOOTMEM=y +CONFIG_MEMORY_ISOLATION=y +# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set +# CONFIG_MEMORY_HOTPLUG is not set +CONFIG_SPLIT_PTLOCK_CPUS=4 +CONFIG_COMPACTION=y +CONFIG_MIGRATION=y +CONFIG_PHYS_ADDR_T_64BIT=y +CONFIG_ZONE_DMA_FLAG=1 +CONFIG_BOUNCE=y +CONFIG_MMU_NOTIFIER=y +# CONFIG_KSM is not set +CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 +# CONFIG_TRANSPARENT_HUGEPAGE is not set +# CONFIG_CLEANCACHE is not set +CONFIG_CMA=y +# CONFIG_CMA_DEBUG is not set +CONFIG_CMA_DEBUGFS=y +CONFIG_CMA_AREAS=7 +# CONFIG_ZPOOL is not set +# CONFIG_ZBUD is not set +CONFIG_ZSMALLOC=y +# CONFIG_PGTABLE_MAPPING is not set +# CONFIG_ZSMALLOC_STAT is not set +CONFIG_GENERIC_EARLY_IOREMAP=y +CONFIG_KSWAPD_CPU_AFFINITY_MASK="" +# CONFIG_IDLE_PAGE_TRACKING is not set +# CONFIG_FORCE_ALLOC_FROM_DMA_ZONE is not set +# CONFIG_PROCESS_RECLAIM is not set +CONFIG_SECCOMP=y +# CONFIG_XEN is not set +CONFIG_FORCE_MAX_ZONEORDER=11 +CONFIG_UNMAP_KERNEL_AT_EL0=y +CONFIG_HARDEN_BRANCH_PREDICTOR=y +CONFIG_ARMV8_DEPRECATED=y +CONFIG_SWP_EMULATION=y +CONFIG_CP15_BARRIER_EMULATION=y +CONFIG_SETEND_EMULATION=y +# CONFIG_ARM64_SW_TTBR0_PAN is not set + +# +# ARMv8.1 architectural features +# +# CONFIG_ARM64_HW_AFDBM is not set +# CONFIG_ARM64_PAN is not set +# CONFIG_ARM64_LSE_ATOMICS is not set +# CONFIG_ARM64_UAO is not set +CONFIG_ARM64_MODULE_CMODEL_LARGE=y +# CONFIG_RANDOMIZE_BASE is not set + +# +# Boot options +# +# CONFIG_ARM64_ACPI_PARKING_PROTOCOL is not set +CONFIG_CMDLINE="ro earlyprintk earlycon=msm_serial_dm,0xc1b0000 console=ttyMSM0,115200,n8 androidboot.bootdevice=1da4000.ufshc rcupdate.rcu_expedited=1 root=/dev/nfs ip=:::::eth0.41:dhcp dhcpclass=linux-fbx7hd rootwait" +# CONFIG_CMDLINE_FROM_BOOTLOADER is not set +# CONFIG_CMDLINE_EXTEND is not set +CONFIG_CMDLINE_FORCE=y +# CONFIG_EFI is not set +# CONFIG_BUILD_ARM64_APPENDED_DTB_IMAGE is not set +# CONFIG_BUILD_ARM64_DT_OVERLAY is not set + +# +# Userspace binary formats +# +CONFIG_BINFMT_ELF=y +CONFIG_COMPAT_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +CONFIG_BINFMT_SCRIPT=y +# CONFIG_HAVE_AOUT is not set +# CONFIG_BINFMT_MISC is not set +CONFIG_COREDUMP=y +CONFIG_COMPAT=y +CONFIG_SYSVIPC_COMPAT=y + +# +# Power management options +# +CONFIG_SUSPEND=y +CONFIG_SUSPEND_FREEZER=y +# CONFIG_SUSPEND_SKIP_SYNC is not set +CONFIG_WAKELOCK=y +CONFIG_PM_SLEEP=y +CONFIG_PM_SLEEP_SMP=y +CONFIG_PM_AUTOSLEEP=y +CONFIG_PM_WAKELOCKS=y +CONFIG_PM_WAKELOCKS_LIMIT=0 +# CONFIG_PM_WAKELOCKS_GC is not set +CONFIG_PM=y +# CONFIG_PM_DEBUG is not set +CONFIG_PM_OPP=y +CONFIG_PM_CLK=y +# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set +CONFIG_CPU_PM=y +CONFIG_ARCH_HIBERNATION_POSSIBLE=y +CONFIG_ARCH_SUSPEND_POSSIBLE=y + +# +# CPU Power Management +# + +# +# CPU Idle +# +CONFIG_CPU_IDLE=y +CONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y +CONFIG_CPU_IDLE_GOV_LADDER=y +CONFIG_CPU_IDLE_GOV_MENU=y + +# +# ARM CPU Idle Drivers +# +# CONFIG_ARM_CPUIDLE is not set +# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set + +# +# CPU Frequency scaling +# +CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_GOV_COMMON=y +# CONFIG_CPU_FREQ_STAT is not set +CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y +# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_INTERACTIVE is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_SCHED is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL is not set +CONFIG_CPU_FREQ_GOV_PERFORMANCE=y +CONFIG_CPU_FREQ_GOV_POWERSAVE=y +CONFIG_CPU_FREQ_GOV_USERSPACE=y +CONFIG_CPU_FREQ_GOV_ONDEMAND=y +CONFIG_CPU_FREQ_GOV_INTERACTIVE=y +CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y +# CONFIG_CPU_BOOST is not set +# CONFIG_CPU_FREQ_GOV_SCHEDUTIL is not set + +# +# CPU frequency scaling drivers +# +# CONFIG_CPUFREQ_DT is not set +# CONFIG_ARM_BIG_LITTLE_CPUFREQ is not set +# CONFIG_ARM_KIRKWOOD_CPUFREQ is not set +# CONFIG_ACPI_CPPC_CPUFREQ is not set +CONFIG_CPU_FREQ_MSM=y +CONFIG_NET=y +CONFIG_COMPAT_NETLINK_MESSAGES=y +# CONFIG_DISABLE_NET_SKB_FRAG_CACHE is not set + +# +# Networking options +# +CONFIG_PACKET=y +# CONFIG_PACKET_DIAG is not set +CONFIG_UNIX=y +# CONFIG_UNIX_DIAG is not set +CONFIG_XFRM=y +CONFIG_XFRM_ALGO=y +CONFIG_XFRM_USER=y +# CONFIG_XFRM_SUB_POLICY is not set +# CONFIG_XFRM_MIGRATE is not set +# CONFIG_XFRM_STATISTICS is not set +CONFIG_NET_KEY=y +# CONFIG_NET_KEY_MIGRATE is not set +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +# CONFIG_IP_PNP_BOOTP is not set +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE_DEMUX is not set +# CONFIG_NET_IP_TUNNEL is not set +# CONFIG_IP_MROUTE is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_NET_IPVTI is not set +# CONFIG_NET_UDP_TUNNEL is not set +# CONFIG_NET_FOU is not set +CONFIG_INET_AH=y +CONFIG_INET_ESP=y +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_XFRM_TUNNEL is not set +# CONFIG_INET_TUNNEL is not set +CONFIG_INET_XFRM_MODE_TRANSPORT=y +CONFIG_INET_XFRM_MODE_TUNNEL=y +# CONFIG_INET_XFRM_MODE_BEET is not set +CONFIG_INET_LRO=y +# CONFIG_INET_DIAG is not set +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set +CONFIG_IPV6=y +# CONFIG_IPV6_ROUTER_PREF is not set +# CONFIG_IPV6_OPTIMISTIC_DAD is not set +# CONFIG_INET6_AH is not set +# CONFIG_INET6_ESP is not set +# CONFIG_INET6_IPCOMP is not set +# CONFIG_IPV6_MIP6 is not set +# CONFIG_IPV6_ILA is not set +# CONFIG_INET6_XFRM_TUNNEL is not set +# CONFIG_INET6_TUNNEL is not set +# CONFIG_INET6_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET6_XFRM_MODE_TUNNEL is not set +# CONFIG_INET6_XFRM_MODE_BEET is not set +# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set +# CONFIG_IPV6_SIT is not set +# CONFIG_IPV6_TUNNEL is not set +# CONFIG_IPV6_GRE is not set +# CONFIG_IPV6_MULTIPLE_TABLES is not set +# CONFIG_IPV6_MROUTE is not set +# CONFIG_ANDROID_PARANOID_NETWORK is not set +# CONFIG_NETWORK_SECMARK is not set +# CONFIG_NET_PTP_CLASSIFY is not set +# CONFIG_NETWORK_PHY_TIMESTAMPING is not set +CONFIG_NETFILTER=y +# CONFIG_NETFILTER_DEBUG is not set +CONFIG_NETFILTER_ADVANCED=y +# CONFIG_BRIDGE_NETFILTER is not set + +# +# Core Netfilter Configuration +# +# CONFIG_NETFILTER_INGRESS is not set +# CONFIG_NETFILTER_NETLINK_ACCT is not set +# CONFIG_NETFILTER_NETLINK_QUEUE is not set +# CONFIG_NETFILTER_NETLINK_LOG is not set +CONFIG_NF_CONNTRACK=y +CONFIG_NF_LOG_COMMON=y +# CONFIG_NF_CONNTRACK_MARK is not set +CONFIG_NF_CONNTRACK_PROCFS=y +# CONFIG_NF_CONNTRACK_EVENTS is not set +# CONFIG_NF_CONNTRACK_TIMEOUT is not set +# CONFIG_NF_CONNTRACK_TIMESTAMP is not set +# CONFIG_NF_CT_PROTO_DCCP is not set +# CONFIG_NF_CT_PROTO_SCTP is not set +# CONFIG_NF_CT_PROTO_UDPLITE is not set +# CONFIG_NF_CONNTRACK_AMANDA is not set +# CONFIG_NF_CONNTRACK_FTP is not set +# CONFIG_NF_CONNTRACK_H323 is not set +# CONFIG_NF_CONNTRACK_IRC is not set +# CONFIG_NF_CONNTRACK_NETBIOS_NS is not set +# CONFIG_NF_CONNTRACK_SNMP is not set +# CONFIG_NF_CONNTRACK_PPTP is not set +# CONFIG_NF_CONNTRACK_SANE is not set +# CONFIG_NF_CONNTRACK_SIP is not set +# CONFIG_NF_CONNTRACK_TFTP is not set +# CONFIG_NF_CT_NETLINK is not set +# CONFIG_NF_CT_NETLINK_TIMEOUT is not set +CONFIG_NF_NAT=y +CONFIG_NF_NAT_NEEDED=y +# CONFIG_NF_NAT_AMANDA is not set +# CONFIG_NF_NAT_FTP is not set +# CONFIG_NF_NAT_IRC is not set +# CONFIG_NF_NAT_SIP is not set +# CONFIG_NF_NAT_TFTP is not set +CONFIG_NF_NAT_REDIRECT=y +# CONFIG_NF_TABLES is not set +CONFIG_NETFILTER_XTABLES=y + +# +# Xtables combined modules +# +# CONFIG_NETFILTER_XT_MARK is not set +# CONFIG_NETFILTER_XT_CONNMARK is not set + +# +# Xtables targets +# +# CONFIG_NETFILTER_XT_TARGET_AUDIT is not set +# CONFIG_NETFILTER_XT_TARGET_CLASSIFY is not set +# CONFIG_NETFILTER_XT_TARGET_CONNMARK is not set +# CONFIG_NETFILTER_XT_TARGET_HMARK is not set +# CONFIG_NETFILTER_XT_TARGET_IDLETIMER is not set +# CONFIG_NETFILTER_XT_TARGET_HARDIDLETIMER is not set +# CONFIG_NETFILTER_XT_TARGET_LED is not set +CONFIG_NETFILTER_XT_TARGET_LOG=y +# CONFIG_NETFILTER_XT_TARGET_MARK is not set +CONFIG_NETFILTER_XT_NAT=y +# CONFIG_NETFILTER_XT_TARGET_NETMAP is not set +# CONFIG_NETFILTER_XT_TARGET_NFLOG is not set +# CONFIG_NETFILTER_XT_TARGET_NFQUEUE is not set +# CONFIG_NETFILTER_XT_TARGET_RATEEST is not set +CONFIG_NETFILTER_XT_TARGET_REDIRECT=y +# CONFIG_NETFILTER_XT_TARGET_TEE is not set +# CONFIG_NETFILTER_XT_TARGET_TCPMSS is not set + +# +# Xtables matches +# +# CONFIG_NETFILTER_XT_MATCH_ADDRTYPE is not set +# CONFIG_NETFILTER_XT_MATCH_BPF is not set +# CONFIG_NETFILTER_XT_MATCH_CGROUP is not set +# CONFIG_NETFILTER_XT_MATCH_CLUSTER is not set +# CONFIG_NETFILTER_XT_MATCH_COMMENT is not set +# CONFIG_NETFILTER_XT_MATCH_CONNBYTES is not set +# CONFIG_NETFILTER_XT_MATCH_CONNLABEL is not set +# CONFIG_NETFILTER_XT_MATCH_CONNLIMIT is not set +# CONFIG_NETFILTER_XT_MATCH_CONNMARK is not set +# CONFIG_NETFILTER_XT_MATCH_CONNTRACK is not set +# CONFIG_NETFILTER_XT_MATCH_CPU is not set +# CONFIG_NETFILTER_XT_MATCH_DCCP is not set +# CONFIG_NETFILTER_XT_MATCH_DEVGROUP is not set +# CONFIG_NETFILTER_XT_MATCH_DSCP is not set +# CONFIG_NETFILTER_XT_MATCH_ECN is not set +# CONFIG_NETFILTER_XT_MATCH_ESP is not set +# CONFIG_NETFILTER_XT_MATCH_HASHLIMIT is not set +# CONFIG_NETFILTER_XT_MATCH_HELPER is not set +# CONFIG_NETFILTER_XT_MATCH_HL is not set +# CONFIG_NETFILTER_XT_MATCH_IPCOMP is not set +# CONFIG_NETFILTER_XT_MATCH_IPRANGE is not set +# CONFIG_NETFILTER_XT_MATCH_L2TP is not set +# CONFIG_NETFILTER_XT_MATCH_LENGTH is not set +# CONFIG_NETFILTER_XT_MATCH_LIMIT is not set +# CONFIG_NETFILTER_XT_MATCH_MAC is not set +# CONFIG_NETFILTER_XT_MATCH_MARK is not set +# CONFIG_NETFILTER_XT_MATCH_MULTIPORT is not set +# CONFIG_NETFILTER_XT_MATCH_NFACCT is not set +CONFIG_NETFILTER_XT_MATCH_OWNER=y +# CONFIG_NETFILTER_XT_MATCH_POLICY is not set +CONFIG_NETFILTER_XT_MATCH_PKTTYPE=y +# CONFIG_NETFILTER_XT_MATCH_QUOTA is not set +# CONFIG_NETFILTER_XT_MATCH_QUOTA2 is not set +# CONFIG_NETFILTER_XT_MATCH_RATEEST is not set +# CONFIG_NETFILTER_XT_MATCH_REALM is not set +# CONFIG_NETFILTER_XT_MATCH_RECENT is not set +# CONFIG_NETFILTER_XT_MATCH_SCTP is not set +# CONFIG_NETFILTER_XT_MATCH_SOCKET is not set +CONFIG_NETFILTER_XT_MATCH_STATE=y +# CONFIG_NETFILTER_XT_MATCH_STATISTIC is not set +# CONFIG_NETFILTER_XT_MATCH_STRING is not set +# CONFIG_NETFILTER_XT_MATCH_TCPMSS is not set +# CONFIG_NETFILTER_XT_MATCH_TIME is not set +# CONFIG_NETFILTER_XT_MATCH_U32 is not set +# CONFIG_IP_SET is not set +# CONFIG_IP_VS is not set + +# +# IP: Netfilter Configuration +# +CONFIG_NF_DEFRAG_IPV4=y +CONFIG_NF_CONNTRACK_IPV4=y +CONFIG_NF_CONNTRACK_PROC_COMPAT=y +# CONFIG_NF_DUP_IPV4 is not set +# CONFIG_NF_LOG_ARP is not set +CONFIG_NF_LOG_IPV4=y +CONFIG_NF_REJECT_IPV4=y +CONFIG_NF_NAT_IPV4=y +# CONFIG_NF_NAT_MASQUERADE_IPV4 is not set +# CONFIG_NF_NAT_PPTP is not set +# CONFIG_NF_NAT_H323 is not set +CONFIG_IP_NF_IPTABLES=y +# CONFIG_IP_NF_MATCH_AH is not set +# CONFIG_IP_NF_MATCH_ECN is not set +# CONFIG_IP_NF_MATCH_TTL is not set +CONFIG_IP_NF_FILTER=y +CONFIG_IP_NF_TARGET_REJECT=y +# CONFIG_IP_NF_TARGET_SYNPROXY is not set +CONFIG_IP_NF_NAT=y +# CONFIG_IP_NF_TARGET_MASQUERADE is not set +# CONFIG_IP_NF_TARGET_NETMAP is not set +CONFIG_IP_NF_TARGET_REDIRECT=y +# CONFIG_IP_NF_MANGLE is not set +# CONFIG_IP_NF_RAW is not set +# CONFIG_IP_NF_ARPTABLES is not set + +# +# IPv6: Netfilter Configuration +# +CONFIG_NF_DEFRAG_IPV6=y +CONFIG_NF_CONNTRACK_IPV6=y +# CONFIG_NF_DUP_IPV6 is not set +CONFIG_NF_REJECT_IPV6=y +CONFIG_NF_LOG_IPV6=y +# CONFIG_NF_NAT_IPV6 is not set +CONFIG_IP6_NF_IPTABLES=y +# CONFIG_IP6_NF_IPTABLES_128 is not set +# CONFIG_IP6_NF_MATCH_AH is not set +# CONFIG_IP6_NF_MATCH_EUI64 is not set +# CONFIG_IP6_NF_MATCH_FRAG is not set +# CONFIG_IP6_NF_MATCH_OPTS is not set +# CONFIG_IP6_NF_MATCH_HL is not set +# CONFIG_IP6_NF_MATCH_IPV6HEADER is not set +# CONFIG_IP6_NF_MATCH_MH is not set +# CONFIG_IP6_NF_MATCH_RT is not set +CONFIG_IP6_NF_FILTER=y +CONFIG_IP6_NF_TARGET_REJECT=y +# CONFIG_IP6_NF_TARGET_SYNPROXY is not set +# CONFIG_IP6_NF_MANGLE is not set +# CONFIG_IP6_NF_RAW is not set +# CONFIG_IP6_NF_NAT is not set +# CONFIG_BRIDGE_NF_EBTABLES is not set +# CONFIG_IP_DCCP is not set +# CONFIG_IP_SCTP is not set +# CONFIG_RDS is not set +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +# CONFIG_L2TP is not set +CONFIG_STP=y +CONFIG_BRIDGE=y +# CONFIG_BRIDGE_IGMP_SNOOPING is not set +# CONFIG_BRIDGE_VLAN_FILTERING is not set +CONFIG_HAVE_NET_DSA=y +# CONFIG_NET_DSA is not set +CONFIG_VLAN_8021Q=y +# CONFIG_VLAN_8021Q_GVRP is not set +# CONFIG_VLAN_8021Q_MVRP is not set +# CONFIG_DECNET is not set +CONFIG_LLC=y +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_PHONET is not set +# CONFIG_6LOWPAN is not set +# CONFIG_IEEE802154 is not set +# CONFIG_NET_SCHED is not set +# CONFIG_DCB is not set +CONFIG_DNS_RESOLVER=y +# CONFIG_BATMAN_ADV is not set +# CONFIG_OPENVSWITCH is not set +# CONFIG_VSOCKETS is not set +# CONFIG_NETLINK_DIAG is not set +# CONFIG_MPLS is not set +# CONFIG_HSR is not set +# CONFIG_NET_SWITCHDEV is not set +# CONFIG_NET_L3_MASTER_DEV is not set +# CONFIG_RMNET_DATA is not set +CONFIG_RPS=y +CONFIG_RFS_ACCEL=y +CONFIG_XPS=y +# CONFIG_CGROUP_NET_PRIO is not set +# CONFIG_CGROUP_NET_CLASSID is not set +CONFIG_NET_RX_BUSY_POLL=y +CONFIG_BQL=y +CONFIG_BPF_JIT=y +CONFIG_NET_FLOW_LIMIT=y +# CONFIG_SOCKEV_NLMCAST is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_NET_DROP_MONITOR is not set +# CONFIG_HAMRADIO is not set +# CONFIG_CAN is not set +# CONFIG_IRDA is not set +CONFIG_BT=y +CONFIG_BT_BREDR=y +# CONFIG_BT_RFCOMM is not set +# CONFIG_BT_BNEP is not set +# CONFIG_BT_HIDP is not set +CONFIG_BT_HS=y +CONFIG_BT_LE=y +# CONFIG_BT_SELFTEST is not set +CONFIG_BT_DEBUGFS=y + +# +# Bluetooth device drivers +# +# CONFIG_BT_HCIBTUSB is not set +# CONFIG_BT_HCIBTSDIO is not set +CONFIG_BT_HCIUART=y +CONFIG_BT_HCIUART_H4=y +# CONFIG_BT_HCIUART_BCSP is not set +# CONFIG_BT_HCIUART_ATH3K is not set +# CONFIG_BT_HCIUART_LL is not set +# CONFIG_BT_HCIUART_3WIRE is not set +# CONFIG_BT_HCIUART_INTEL is not set +# CONFIG_BT_HCIUART_BCM is not set +# CONFIG_BT_HCIUART_QCA is not set +# CONFIG_BT_HCIBCM203X is not set +# CONFIG_BT_HCIBPA10X is not set +# CONFIG_BT_HCIBFUSB is not set +# CONFIG_BT_HCIVHCI is not set +# CONFIG_BT_MRVL is not set +CONFIG_MSM_BT_POWER=y +CONFIG_BTFM_SLIM=y +CONFIG_BTFM_SLIM_WCN3990=y +# CONFIG_AF_RXRPC is not set +CONFIG_WIRELESS=y +CONFIG_WIRELESS_EXT=y +CONFIG_WEXT_CORE=y +CONFIG_WEXT_PROC=y +CONFIG_WEXT_SPY=y +CONFIG_WEXT_PRIV=y +CONFIG_CFG80211=m +CONFIG_NL80211_TESTMODE=y +# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set +# CONFIG_CFG80211_REG_DEBUG is not set +CONFIG_CFG80211_CERTIFICATION_ONUS=y +# CONFIG_CFG80211_REG_CELLULAR_HINTS is not set +CONFIG_CFG80211_REG_RELAX_NO_IR=y +CONFIG_CFG80211_DEFAULT_PS=y +# CONFIG_CFG80211_DEBUGFS is not set +CONFIG_CFG80211_INTERNAL_REGDB=y +# CONFIG_CFG80211_CRDA_SUPPORT is not set +# CONFIG_CFG80211_WEXT is not set +# CONFIG_LIB80211 is not set +CONFIG_MAC80211=m +CONFIG_MAC80211_HAS_RC=y +CONFIG_MAC80211_RC_MINSTREL=y +CONFIG_MAC80211_RC_MINSTREL_HT=y +CONFIG_MAC80211_RC_MINSTREL_VHT=y +CONFIG_MAC80211_RC_DEFAULT_MINSTREL=y +CONFIG_MAC80211_RC_DEFAULT="minstrel_ht" +CONFIG_MAC80211_MESH=y +CONFIG_MAC80211_LEDS=y +# CONFIG_MAC80211_DEBUGFS is not set +# CONFIG_MAC80211_MESSAGE_TRACING is not set +# CONFIG_MAC80211_DEBUG_MENU is not set +CONFIG_MAC80211_STA_HASH_MAX_SIZE=0 +# CONFIG_WIMAX is not set +CONFIG_RFKILL=y +CONFIG_RFKILL_PM=y +CONFIG_RFKILL_LEDS=y +# CONFIG_RFKILL_INPUT is not set +# CONFIG_RFKILL_REGULATOR is not set +# CONFIG_RFKILL_GPIO is not set +# CONFIG_NET_9P is not set +# CONFIG_CAIF is not set +# CONFIG_CEPH_LIB is not set +# CONFIG_NFC is not set +CONFIG_NFC_NQ=y +# CONFIG_LWTUNNEL is not set +CONFIG_IPC_ROUTER=y +CONFIG_IPC_ROUTER_SECURITY=y +CONFIG_HAVE_BPF_JIT=y +CONFIG_HAVE_EBPF_JIT=y + +# +# Device Drivers +# +CONFIG_ARM_AMBA=y +# CONFIG_TEGRA_AHB is not set + +# +# Generic Driver Options +# +# CONFIG_UEVENT_HELPER is not set +CONFIG_DEVTMPFS=y +# CONFIG_DEVTMPFS_MOUNT is not set +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=y +CONFIG_FIRMWARE_IN_KERNEL=y +CONFIG_EXTRA_FIRMWARE="" +# CONFIG_FW_LOADER_USER_HELPER_FALLBACK is not set +CONFIG_ALLOW_DEV_COREDUMP=y +# CONFIG_DEBUG_DRIVER is not set +# CONFIG_DEBUG_DEVRES is not set +# CONFIG_SYS_HYPERVISOR is not set +# CONFIG_GENERIC_CPU_DEVICES is not set +CONFIG_GENERIC_CPU_AUTOPROBE=y +CONFIG_SOC_BUS=y +CONFIG_REGMAP=y +CONFIG_REGMAP_I2C=y +CONFIG_REGMAP_SPI=y +CONFIG_REGMAP_SPMI=y +CONFIG_REGMAP_MMIO=y +CONFIG_REGMAP_SWR=y +# CONFIG_REGMAP_ALLOW_WRITE_DEBUGFS is not set +CONFIG_DMA_SHARED_BUFFER=y +# CONFIG_FENCE_TRACE is not set +CONFIG_DMA_CMA=y + +# +# Default contiguous memory area size: +# +CONFIG_CMA_SIZE_MBYTES=16 +CONFIG_CMA_SIZE_SEL_MBYTES=y +# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set +# CONFIG_CMA_SIZE_SEL_MIN is not set +# CONFIG_CMA_SIZE_SEL_MAX is not set +CONFIG_CMA_ALIGNMENT=8 + +# +# Bus devices +# +# CONFIG_ARM_CCI400_PMU is not set +# CONFIG_ARM_CCI500_PMU is not set +# CONFIG_ARM_CCN is not set +# CONFIG_VEXPRESS_CONFIG is not set +# CONFIG_CONNECTOR is not set +CONFIG_FREEBOX_PROCFS=y +# CONFIG_MTD is not set +CONFIG_DTC=y +CONFIG_OF=y +# CONFIG_OF_UNITTEST is not set +CONFIG_OF_FLATTREE=y +CONFIG_OF_EARLY_FLATTREE=y +CONFIG_OF_ADDRESS=y +CONFIG_OF_ADDRESS_PCI=y +CONFIG_OF_IRQ=y +CONFIG_OF_NET=y +CONFIG_OF_MDIO=y +CONFIG_OF_PCI=y +CONFIG_OF_PCI_IRQ=y +CONFIG_OF_RESERVED_MEM=y +CONFIG_OF_SLIMBUS=y +# CONFIG_OF_OVERLAY is not set +CONFIG_OF_BATTERYDATA=y +# CONFIG_PARPORT is not set +CONFIG_PNP=y +# CONFIG_PNP_DEBUG_MESSAGES is not set + +# +# Protocols +# +CONFIG_PNPACPI=y +CONFIG_BLK_DEV=y +# CONFIG_BLK_DEV_NULL_BLK is not set +# CONFIG_BLK_DEV_PCIESSD_MTIP32XX is not set +# CONFIG_ZRAM is not set +# CONFIG_BLK_CPQ_CISS_DA is not set +# CONFIG_BLK_DEV_DAC960 is not set +# CONFIG_BLK_DEV_UMEM is not set +# CONFIG_BLK_DEV_COW_COMMON is not set +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_LOOP_MIN_COUNT=8 +# CONFIG_BLK_DEV_CRYPTOLOOP is not set +# CONFIG_BLK_DEV_DRBD is not set +# CONFIG_BLK_DEV_NBD is not set +# CONFIG_BLK_DEV_SKD is not set +# CONFIG_BLK_DEV_SX8 is not set +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=1 +CONFIG_BLK_DEV_RAM_SIZE=196608 +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_ATA_OVER_ETH is not set +# CONFIG_BLK_DEV_RBD is not set +# CONFIG_BLK_DEV_RSXX is not set +# CONFIG_BLK_DEV_NVME is not set + +# +# Misc devices +# +# CONFIG_SENSORS_LIS3LV02D is not set +# CONFIG_AD525X_DPOT is not set +# CONFIG_DUMMY_IRQ is not set +# CONFIG_PHANTOM is not set +# CONFIG_SGI_IOC4 is not set +# CONFIG_TIFM_CORE is not set +# CONFIG_ICS932S401 is not set +# CONFIG_ENCLOSURE_SERVICES is not set +# CONFIG_HP_ILO is not set +# CONFIG_QCOM_COINCELL is not set +# CONFIG_APDS9802ALS is not set +# CONFIG_ISL29003 is not set +# CONFIG_ISL29020 is not set +# CONFIG_SENSORS_TSL2550 is not set +# CONFIG_SENSORS_BH1780 is not set +# CONFIG_SENSORS_BH1770 is not set +# CONFIG_SENSORS_APDS990X is not set +# CONFIG_HMC6352 is not set +# CONFIG_DS1682 is not set +# CONFIG_TI_DAC7512 is not set +# CONFIG_BMP085_I2C is not set +# CONFIG_BMP085_SPI is not set +CONFIG_FBXSERIAL_OF=y +# CONFIG_USB_SWITCH_FSA9480 is not set +# CONFIG_LATTICE_ECP3_CONFIG is not set +# CONFIG_SRAM is not set +CONFIG_QSEECOM=y +CONFIG_HDCP_QSEECOM=y +# CONFIG_PROFILER is not set +CONFIG_QPNP_MISC=y +# CONFIG_C2PORT is not set + +# +# EEPROM support +# +CONFIG_EEPROM_AT24=y +# CONFIG_EEPROM_AT25 is not set +# CONFIG_EEPROM_LEGACY is not set +# CONFIG_EEPROM_MAX6875 is not set +# CONFIG_EEPROM_93CX6 is not set +# CONFIG_EEPROM_93XX46 is not set +# CONFIG_CB710_CORE is not set + +# +# Texas Instruments shared transport line discipline +# +# CONFIG_TI_ST is not set +# CONFIG_SENSORS_LIS3_I2C is not set + +# +# Altera FPGA firmware download module +# +# CONFIG_ALTERA_STAPL is not set +CONFIG_MSM_QDSP6V2_CODECS=y +CONFIG_MSM_ULTRASOUND=y + +# +# Intel MIC Bus Driver +# + +# +# SCIF Bus Driver +# + +# +# Intel MIC Host Driver +# + +# +# Intel MIC Card Driver +# + +# +# SCIF Driver +# + +# +# Intel MIC Coprocessor State Management (COSM) Drivers +# +# CONFIG_GENWQE is not set +# CONFIG_ECHO is not set +# CONFIG_CXL_BASE is not set +# CONFIG_CXL_KERNEL_API is not set +# CONFIG_CXL_EEH is not set +CONFIG_NET_RTL8367C_SPI=y +CONFIG_NET_RTL8367C_SPI_CONFIG=y + +# +# HDMI CEC support +# +CONFIG_HDMI_CEC=y + +# +# SCSI device support +# +CONFIG_SCSI_MOD=y +# CONFIG_RAID_ATTRS is not set +CONFIG_SCSI=y +CONFIG_SCSI_DMA=y +# CONFIG_SCSI_NETLINK is not set +# CONFIG_SCSI_MQ_DEFAULT is not set +CONFIG_SCSI_PROC_FS=y + +# +# SCSI support type (disk, tape, CD-ROM) +# +CONFIG_BLK_DEV_SD=y +# CONFIG_CHR_DEV_ST is not set +# CONFIG_CHR_DEV_OSST is not set +CONFIG_BLK_DEV_SR=y +# CONFIG_BLK_DEV_SR_VENDOR is not set +CONFIG_CHR_DEV_SG=y +CONFIG_CHR_DEV_SCH=y +CONFIG_SCSI_CONSTANTS=y +CONFIG_SCSI_LOGGING=y +CONFIG_SCSI_SCAN_ASYNC=y + +# +# SCSI Transports +# +# CONFIG_SCSI_SPI_ATTRS is not set +# CONFIG_SCSI_FC_ATTRS is not set +# CONFIG_SCSI_ISCSI_ATTRS is not set +# CONFIG_SCSI_SAS_ATTRS is not set +# CONFIG_SCSI_SAS_LIBSAS is not set +# CONFIG_SCSI_SRP_ATTRS is not set +CONFIG_SCSI_LOWLEVEL=y +# CONFIG_ISCSI_TCP is not set +# CONFIG_ISCSI_BOOT_SYSFS is not set +# CONFIG_SCSI_CXGB3_ISCSI is not set +# CONFIG_SCSI_CXGB4_ISCSI is not set +# CONFIG_SCSI_BNX2_ISCSI is not set +# CONFIG_BE2ISCSI is not set +# CONFIG_BLK_DEV_3W_XXXX_RAID is not set +# CONFIG_SCSI_HPSA is not set +# CONFIG_SCSI_3W_9XXX is not set +# CONFIG_SCSI_3W_SAS is not set +# CONFIG_SCSI_ACARD is not set +# CONFIG_SCSI_AACRAID is not set +# CONFIG_SCSI_AIC7XXX is not set +# CONFIG_SCSI_AIC79XX is not set +# CONFIG_SCSI_AIC94XX is not set +# CONFIG_SCSI_MVSAS is not set +# CONFIG_SCSI_MVUMI is not set +# CONFIG_SCSI_ADVANSYS is not set +# CONFIG_SCSI_ARCMSR is not set +# CONFIG_SCSI_ESAS2R is not set +# CONFIG_MEGARAID_NEWGEN is not set +# CONFIG_MEGARAID_LEGACY is not set +# CONFIG_MEGARAID_SAS is not set +# CONFIG_SCSI_MPT3SAS is not set +# CONFIG_SCSI_MPT2SAS is not set +CONFIG_SCSI_UFSHCD=y +# CONFIG_SCSI_UFSHCD_PCI is not set +CONFIG_SCSI_UFSHCD_PLATFORM=y +CONFIG_SCSI_UFS_QCOM=y +# CONFIG_SCSI_UFSHCD_CMD_LOGGING is not set +# CONFIG_SCSI_HPTIOP is not set +# CONFIG_SCSI_SNIC is not set +# CONFIG_SCSI_DMX3191D is not set +# CONFIG_SCSI_FUTURE_DOMAIN is not set +# CONFIG_SCSI_IPS is not set +# CONFIG_SCSI_INITIO is not set +# CONFIG_SCSI_INIA100 is not set +# CONFIG_SCSI_STEX is not set +# CONFIG_SCSI_SYM53C8XX_2 is not set +# CONFIG_SCSI_QLOGIC_1280 is not set +# CONFIG_SCSI_QLA_ISCSI is not set +# CONFIG_SCSI_DC395x is not set +# CONFIG_SCSI_AM53C974 is not set +# CONFIG_SCSI_WD719X is not set +# CONFIG_SCSI_DEBUG is not set +# CONFIG_SCSI_PMCRAID is not set +# CONFIG_SCSI_PM8001 is not set +# CONFIG_SCSI_LOWLEVEL_PCMCIA is not set +# CONFIG_SCSI_DH is not set +# CONFIG_SCSI_OSD_INITIATOR is not set +CONFIG_HAVE_PATA_PLATFORM=y +# CONFIG_ATA is not set +CONFIG_MD=y +# CONFIG_BLK_DEV_MD is not set +# CONFIG_BCACHE is not set +CONFIG_BLK_DEV_DM_BUILTIN=y +CONFIG_BLK_DEV_DM=y +# CONFIG_DM_MQ_DEFAULT is not set +# CONFIG_DM_DEBUG is not set +CONFIG_DM_BUFIO=y +CONFIG_DM_CRYPT=y +CONFIG_DM_REQ_CRYPT=y +# CONFIG_DM_SNAPSHOT is not set +# CONFIG_DM_THIN_PROVISIONING is not set +# CONFIG_DM_CACHE is not set +# CONFIG_DM_ERA is not set +# CONFIG_DM_MIRROR is not set +# CONFIG_DM_RAID is not set +# CONFIG_DM_ZERO is not set +# CONFIG_DM_MULTIPATH is not set +# CONFIG_DM_DELAY is not set +CONFIG_DM_UEVENT=y +# CONFIG_DM_FLAKEY is not set +CONFIG_DM_VERITY=y +# CONFIG_DM_VERITY_HASH_PREFETCH_MIN_SIZE_128 is not set +CONFIG_DM_VERITY_HASH_PREFETCH_MIN_SIZE=1 +CONFIG_DM_VERITY_FEC=y +# CONFIG_DM_SWITCH is not set +# CONFIG_DM_LOG_WRITES is not set +# CONFIG_DM_VERITY_AVB is not set +# CONFIG_TARGET_CORE is not set +# CONFIG_FUSION is not set + +# +# IEEE 1394 (FireWire) support +# +# CONFIG_FIREWIRE is not set +# CONFIG_FIREWIRE_NOSY is not set +CONFIG_NETDEVICES=y +CONFIG_NET_CORE=y +# CONFIG_BONDING is not set +# CONFIG_DUMMY is not set +# CONFIG_EQUALIZER is not set +# CONFIG_NET_FC is not set +# CONFIG_NET_TEAM is not set +# CONFIG_MACVLAN is not set +# CONFIG_IPVLAN is not set +# CONFIG_VXLAN is not set +# CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set +CONFIG_TUN=y +# CONFIG_TUN_VNET_CROSS_LE is not set +# CONFIG_VETH is not set +# CONFIG_NLMON is not set +# CONFIG_ARCNET is not set + +# +# CAIF transport drivers +# + +# +# Distributed Switch Architecture drivers +# +# CONFIG_NET_DSA_MV88E6XXX is not set +# CONFIG_NET_DSA_MV88E6XXX_NEED_PPU is not set +CONFIG_ETHERNET=y +CONFIG_MDIO=y +# CONFIG_NET_VENDOR_3COM is not set +# CONFIG_NET_VENDOR_ADAPTEC is not set +# CONFIG_NET_VENDOR_AGERE is not set +# CONFIG_NET_VENDOR_ALTEON is not set +# CONFIG_ALTERA_TSE is not set +# CONFIG_NET_VENDOR_AMD is not set +# CONFIG_NET_VENDOR_ARC is not set +CONFIG_NET_VENDOR_ATHEROS=y +# CONFIG_ATL2 is not set +# CONFIG_ATL1 is not set +# CONFIG_ATL1E is not set +# CONFIG_ATL1C is not set +# CONFIG_ALX is not set +CONFIG_ALX_PROP=y +# CONFIG_NET_VENDOR_AURORA is not set +# CONFIG_NET_CADENCE is not set +# CONFIG_NET_VENDOR_BROADCOM is not set +# CONFIG_NET_VENDOR_BROCADE is not set +# CONFIG_NET_VENDOR_CAVIUM is not set +# CONFIG_NET_VENDOR_CHELSIO is not set +# CONFIG_NET_VENDOR_CISCO is not set +# CONFIG_DNET is not set +# CONFIG_NET_VENDOR_DEC is not set +# CONFIG_NET_VENDOR_DLINK is not set +# CONFIG_NET_VENDOR_EMULEX is not set +# CONFIG_NET_VENDOR_EZCHIP is not set +# CONFIG_NET_VENDOR_EXAR is not set +# CONFIG_NET_VENDOR_HISILICON is not set +# CONFIG_NET_VENDOR_HP is not set +# CONFIG_NET_VENDOR_INTEL is not set +# CONFIG_JME is not set +# CONFIG_NET_VENDOR_MARVELL is not set +# CONFIG_NET_VENDOR_MELLANOX is not set +# CONFIG_NET_VENDOR_MICREL is not set +# CONFIG_NET_VENDOR_MICROCHIP is not set +# CONFIG_NET_VENDOR_MYRI is not set +# CONFIG_FEALNX is not set +# CONFIG_NET_VENDOR_NATSEMI is not set +# CONFIG_NET_VENDOR_NVIDIA is not set +# CONFIG_NET_VENDOR_OKI is not set +# CONFIG_ETHOC is not set +# CONFIG_NET_PACKET_ENGINE is not set +# CONFIG_NET_VENDOR_QLOGIC is not set +# CONFIG_NET_VENDOR_QUALCOMM is not set +# CONFIG_NET_VENDOR_REALTEK is not set +# CONFIG_NET_VENDOR_RENESAS is not set +# CONFIG_NET_VENDOR_RDC is not set +# CONFIG_NET_VENDOR_ROCKER is not set +# CONFIG_NET_VENDOR_SAMSUNG is not set +# CONFIG_NET_VENDOR_SEEQ is not set +# CONFIG_NET_VENDOR_SILAN is not set +# CONFIG_NET_VENDOR_SIS is not set +# CONFIG_SFC is not set +# CONFIG_NET_VENDOR_SMSC is not set +# CONFIG_NET_VENDOR_STMICRO is not set +# CONFIG_NET_VENDOR_SUN is not set +# CONFIG_NET_VENDOR_SYNOPSYS is not set +# CONFIG_NET_VENDOR_TEHUTI is not set +# CONFIG_NET_VENDOR_TI is not set +# CONFIG_NET_VENDOR_VIA is not set +# CONFIG_NET_VENDOR_WIZNET is not set +# CONFIG_FDDI is not set +# CONFIG_HIPPI is not set +# CONFIG_NET_SB1000 is not set +CONFIG_PHYLIB=y + +# +# MII PHY device drivers +# +# CONFIG_AQUANTIA_PHY is not set +# CONFIG_AT803X_PHY is not set +# CONFIG_AMD_PHY is not set +# CONFIG_MARVELL_PHY is not set +# CONFIG_DAVICOM_PHY is not set +# CONFIG_QSEMI_PHY is not set +# CONFIG_LXT_PHY is not set +# CONFIG_CICADA_PHY is not set +# CONFIG_VITESSE_PHY is not set +# CONFIG_TERANETICS_PHY is not set +# CONFIG_SMSC_PHY is not set +# CONFIG_BROADCOM_PHY is not set +# CONFIG_BCM7XXX_PHY is not set +# CONFIG_BCM87XX_PHY is not set +# CONFIG_ICPLUS_PHY is not set +# CONFIG_REALTEK_PHY is not set +# CONFIG_NATIONAL_PHY is not set +# CONFIG_STE10XP is not set +# CONFIG_LSI_ET1011C_PHY is not set +# CONFIG_MICREL_PHY is not set +# CONFIG_DP83848_PHY is not set +# CONFIG_DP83867_PHY is not set +# CONFIG_MICROCHIP_PHY is not set +# CONFIG_FIXED_PHY is not set +# CONFIG_MDIO_BITBANG is not set +# CONFIG_MDIO_OCTEON is not set +# CONFIG_MDIO_BUS_MUX_GPIO is not set +# CONFIG_MDIO_BUS_MUX_MMIOREG is not set +# CONFIG_MDIO_BCM_UNIMAC is not set +# CONFIG_MICREL_KS8995MA is not set +CONFIG_PPP=y +CONFIG_PPP_BSDCOMP=y +CONFIG_PPP_DEFLATE=y +# CONFIG_PPP_FILTER is not set +CONFIG_PPP_MPPE=y +# CONFIG_PPP_MULTILINK is not set +# CONFIG_PPPOE is not set +CONFIG_PPPOLAC=y +CONFIG_PPPOPNS=y +# CONFIG_PPP_ASYNC is not set +# CONFIG_PPP_SYNC_TTY is not set +# CONFIG_SLIP is not set +CONFIG_SLHC=y +# CONFIG_USB_NET_DRIVERS is not set +CONFIG_WLAN=y +# CONFIG_LIBERTAS_THINFIRM is not set +# CONFIG_ATMEL is not set +# CONFIG_AT76C50X_USB is not set +# CONFIG_PRISM54 is not set +# CONFIG_USB_ZD1201 is not set +# CONFIG_USB_NET_RNDIS_WLAN is not set +# CONFIG_ADM8211 is not set +# CONFIG_RTL8180 is not set +# CONFIG_RTL8187 is not set +# CONFIG_MAC80211_HWSIM is not set +# CONFIG_MWL8K is not set +# CONFIG_WIFI_CONTROL_FUNC is not set +# CONFIG_WCNSS_CORE is not set +CONFIG_WCNSS_MEM_PRE_ALLOC=y +# CONFIG_CNSS_CRYPTO is not set +# CONFIG_CNSS_QCA6290 is not set +CONFIG_ATH_COMMON=m +CONFIG_ATH_CARDS=m +# CONFIG_ATH_DEBUG is not set +# CONFIG_ATH_REG_DYNAMIC_USER_REG_HINTS is not set +# CONFIG_ATH5K is not set +# CONFIG_ATH5K_PCI is not set +# CONFIG_ATH9K is not set +# CONFIG_ATH9K_HTC is not set +# CONFIG_CARL9170 is not set +# CONFIG_ATH6KL is not set +# CONFIG_AR5523 is not set +# CONFIG_WIL6210 is not set +CONFIG_ATH10K=m +# CONFIG_ATH10K_PCI is not set +CONFIG_ATH10K_TARGET_SNOC=m +CONFIG_ATH10K_SNOC=y +CONFIG_ATH10K_DEBUG=y +# CONFIG_ATH10K_DEBUGFS is not set +# CONFIG_ATH10K_TRACING is not set +CONFIG_ATH10K_DFS_CERTIFIED=y +# CONFIG_WCN36XX is not set +# CONFIG_B43 is not set +# CONFIG_B43LEGACY is not set +# CONFIG_BRCMSMAC is not set +# CONFIG_BRCMFMAC is not set +# CONFIG_HOSTAP is not set +# CONFIG_IPW2100 is not set +# CONFIG_IPW2200 is not set +# CONFIG_IWLWIFI is not set +# CONFIG_IWL4965 is not set +# CONFIG_IWL3945 is not set +# CONFIG_LIBERTAS is not set +# CONFIG_HERMES is not set +# CONFIG_P54_COMMON is not set +# CONFIG_RT2X00 is not set +# CONFIG_WL_MEDIATEK is not set +# CONFIG_RTL_CARDS is not set +# CONFIG_RTL8XXXU is not set +# CONFIG_WL_TI is not set +# CONFIG_ZD1211RW is not set +# CONFIG_MWIFIEX is not set +# CONFIG_CW1200 is not set +# CONFIG_RSI_91X is not set +# CONFIG_CNSS is not set +# CONFIG_CLD_DEBUG is not set +# CONFIG_CLD_HL_SDIO_CORE is not set +CONFIG_CLD_LL_CORE=y +# CONFIG_CNSS2 is not set +# CONFIG_CNSS_GENL is not set +CONFIG_CNSS_UTILS=y + +# +# Enable WiMAX (Networking options) to see the WiMAX drivers +# +# CONFIG_WAN is not set +# CONFIG_VMXNET3 is not set +# CONFIG_FUJITSU_ES is not set +# CONFIG_RMNET is not set +# CONFIG_ISDN is not set +# CONFIG_NVM is not set + +# +# Input device support +# +CONFIG_INPUT=y +CONFIG_INPUT_LEDS=y +# CONFIG_INPUT_FF_MEMLESS is not set +# CONFIG_INPUT_POLLDEV is not set +# CONFIG_INPUT_SPARSEKMAP is not set +# CONFIG_INPUT_MATRIXKMAP is not set + +# +# Userland interfaces +# +# CONFIG_INPUT_MOUSEDEV is not set +# CONFIG_INPUT_JOYDEV is not set +CONFIG_INPUT_EVDEV=y +# CONFIG_INPUT_EVBUG is not set +CONFIG_INPUT_KEYRESET=y +CONFIG_INPUT_KEYCOMBO=y + +# +# Input Device Drivers +# +CONFIG_INPUT_KEYBOARD=y +# CONFIG_KEYBOARD_ADP5588 is not set +# CONFIG_KEYBOARD_ADP5589 is not set +# CONFIG_KEYBOARD_ATKBD is not set +# CONFIG_KEYBOARD_QT1070 is not set +# CONFIG_KEYBOARD_QT2160 is not set +# CONFIG_KEYBOARD_LKKBD is not set +CONFIG_KEYBOARD_GPIO=y +# CONFIG_KEYBOARD_GPIO_POLLED is not set +# CONFIG_KEYBOARD_TCA6416 is not set +# CONFIG_KEYBOARD_TCA8418 is not set +# CONFIG_KEYBOARD_MATRIX is not set +# CONFIG_KEYBOARD_LM8323 is not set +# CONFIG_KEYBOARD_LM8333 is not set +# CONFIG_KEYBOARD_MAX7359 is not set +# CONFIG_KEYBOARD_MCS is not set +# CONFIG_KEYBOARD_MPR121 is not set +# CONFIG_KEYBOARD_NEWTON is not set +# CONFIG_KEYBOARD_OPENCORES is not set +# CONFIG_KEYBOARD_SAMSUNG is not set +# CONFIG_KEYBOARD_STOWAWAY is not set +# CONFIG_KEYBOARD_SUNKBD is not set +# CONFIG_KEYBOARD_OMAP4 is not set +# CONFIG_KEYBOARD_XTKBD is not set +# CONFIG_KEYBOARD_CAP11XX is not set +# CONFIG_KEYBOARD_BCM is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +CONFIG_INPUT_MISC=y +# CONFIG_INPUT_AD714X is not set +# CONFIG_INPUT_BMA150 is not set +# CONFIG_INPUT_E3X0_BUTTON is not set +# CONFIG_INPUT_HBTP_INPUT is not set +# CONFIG_INPUT_PM8941_PWRKEY is not set +CONFIG_INPUT_QPNP_POWER_ON=y +# CONFIG_INPUT_MMA8450 is not set +# CONFIG_INPUT_MPU3050 is not set +# CONFIG_INPUT_GP2A is not set +# CONFIG_INPUT_GPIO_BEEPER is not set +# CONFIG_INPUT_GPIO_TILT_POLLED is not set +# CONFIG_INPUT_ATI_REMOTE2 is not set +# CONFIG_INPUT_KEYCHORD is not set +# CONFIG_INPUT_KEYSPAN_REMOTE is not set +# CONFIG_INPUT_KXTJ9 is not set +# CONFIG_INPUT_POWERMATE is not set +# CONFIG_INPUT_YEALINK is not set +# CONFIG_INPUT_CM109 is not set +# CONFIG_INPUT_REGULATOR_HAPTIC is not set +CONFIG_INPUT_UINPUT=y +CONFIG_INPUT_GPIO=y +# CONFIG_INPUT_PCF8574 is not set +# CONFIG_INPUT_PWM_BEEPER is not set +# CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set +# CONFIG_INPUT_ADXL34X is not set +# CONFIG_INPUT_IMS_PCU is not set +# CONFIG_INPUT_CMA3000 is not set +# CONFIG_INPUT_SOC_BUTTON_ARRAY is not set +# CONFIG_INPUT_DRV260X_HAPTICS is not set +# CONFIG_INPUT_DRV2665_HAPTICS is not set +# CONFIG_INPUT_DRV2667_HAPTICS is not set +# CONFIG_INPUT_PIXART_OTS_PAT9125_SWITCH is not set +# CONFIG_INPUT_STMVL53L0 is not set + +# +# Hardware I/O ports +# +# CONFIG_SERIO is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_TTY=y +CONFIG_VT=y +# CONFIG_CONSOLE_TRANSLATIONS is not set +# CONFIG_VT_CONSOLE is not set +CONFIG_HW_CONSOLE=y +# CONFIG_VT_HW_CONSOLE_BINDING is not set +CONFIG_UNIX98_PTYS=y +# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set +CONFIG_LEGACY_PTYS=y +CONFIG_LEGACY_PTY_COUNT=16 +# CONFIG_SERIAL_NONSTANDARD is not set +# CONFIG_NOZOMI is not set +# CONFIG_N_GSM is not set +# CONFIG_TRACE_SINK is not set +CONFIG_DEVMEM=y +# CONFIG_DEVKMEM is not set + +# +# Serial drivers +# +CONFIG_SERIAL_EARLYCON=y +# CONFIG_SERIAL_8250 is not set + +# +# Non-8250 serial port support +# +# CONFIG_SERIAL_AMBA_PL010 is not set +# CONFIG_SERIAL_AMBA_PL011 is not set +# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set +# CONFIG_SERIAL_MAX3100 is not set +# CONFIG_SERIAL_MAX310X is not set +# CONFIG_SERIAL_UARTLITE is not set +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_JSM is not set +CONFIG_SERIAL_MSM=y +CONFIG_SERIAL_MSM_CONSOLE=y +CONFIG_SERIAL_MSM_HS=y +# CONFIG_SERIAL_SCCNXP is not set +# CONFIG_SERIAL_SC16IS7XX is not set +# CONFIG_SERIAL_ALTERA_JTAGUART is not set +# CONFIG_SERIAL_ALTERA_UART is not set +# CONFIG_SERIAL_IFX6X60 is not set +CONFIG_SERIAL_MSM_SMD=y +# CONFIG_SERIAL_XILINX_PS_UART is not set +# CONFIG_SERIAL_ARC is not set +# CONFIG_SERIAL_RP2 is not set +# CONFIG_SERIAL_FSL_LPUART is not set +# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set + +# +# Diag Support +# +CONFIG_DIAG_CHAR=y + +# +# DIAG traffic over USB +# + +# +# HSIC/SMUX support for DIAG +# +# CONFIG_TTY_PRINTK is not set +# CONFIG_HVC_DCC is not set +# CONFIG_IPMI_HANDLER is not set +CONFIG_HW_RANDOM=y +# CONFIG_HW_RANDOM_TIMERIOMEM is not set +CONFIG_HW_RANDOM_MSM_LEGACY=y +# CONFIG_HW_RANDOM_MSM is not set +# CONFIG_R3964 is not set +# CONFIG_APPLICOM is not set + +# +# PCMCIA character devices +# +# CONFIG_RAW_DRIVER is not set +# CONFIG_HPET is not set +# CONFIG_TCG_TPM is not set +# CONFIG_DEVPORT is not set +# CONFIG_MSM_SMD_PKT is not set +# CONFIG_XILLYBUS is not set +CONFIG_MSM_ADSPRPC=y +CONFIG_MSM_RDBG=m + +# +# I2C support +# +CONFIG_I2C=y +CONFIG_ACPI_I2C_OPREGION=y +CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_COMPAT=y +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_MUX=y + +# +# Multiplexer I2C Chip support +# +# CONFIG_I2C_ARB_GPIO_CHALLENGE is not set +CONFIG_I2C_MUX_GPIO=y +# CONFIG_I2C_MUX_PCA9541 is not set +# CONFIG_I2C_MUX_PCA954x is not set +# CONFIG_I2C_MUX_PINCTRL is not set +# CONFIG_I2C_MUX_REG is not set +CONFIG_I2C_HELPER_AUTO=y +CONFIG_I2C_ALGOBIT=y + +# +# I2C Hardware Bus support +# + +# +# PC SMBus host controller drivers +# +# CONFIG_I2C_ALI1535 is not set +# CONFIG_I2C_ALI1563 is not set +# CONFIG_I2C_ALI15X3 is not set +# CONFIG_I2C_AMD756 is not set +# CONFIG_I2C_AMD8111 is not set +# CONFIG_I2C_I801 is not set +# CONFIG_I2C_ISCH is not set +# CONFIG_I2C_PIIX4 is not set +# CONFIG_I2C_NFORCE2 is not set +# CONFIG_I2C_SIS5595 is not set +# CONFIG_I2C_SIS630 is not set +# CONFIG_I2C_SIS96X is not set +# CONFIG_I2C_VIA is not set +# CONFIG_I2C_VIAPRO is not set + +# +# ACPI drivers +# +# CONFIG_I2C_SCMI is not set + +# +# I2C system bus drivers (mostly embedded / system-on-chip) +# +# CONFIG_I2C_CADENCE is not set +# CONFIG_I2C_CBUS_GPIO is not set +# CONFIG_I2C_DESIGNWARE_PCI is not set +# CONFIG_I2C_EMEV2 is not set +CONFIG_I2C_GPIO=y +# CONFIG_I2C_NOMADIK is not set +# CONFIG_I2C_OCORES is not set +# CONFIG_I2C_PCA_PLATFORM is not set +# CONFIG_I2C_PXA_PCI is not set +# CONFIG_I2C_QUP is not set +# CONFIG_I2C_SIMTEC is not set +# CONFIG_I2C_XILINX is not set + +# +# External I2C/SMBus adapter drivers +# +# CONFIG_I2C_DIOLAN_U2C is not set +# CONFIG_I2C_PARPORT_LIGHT is not set +# CONFIG_I2C_ROBOTFUZZ_OSIF is not set +# CONFIG_I2C_TAOS_EVM is not set +# CONFIG_I2C_TINY_USB is not set + +# +# Other I2C/SMBus bus drivers +# +CONFIG_I2C_MSM_V2=y +# CONFIG_I2C_STUB is not set +# CONFIG_I2C_SLAVE is not set +# CONFIG_I2C_DEBUG_CORE is not set +# CONFIG_I2C_DEBUG_ALGO is not set +# CONFIG_I2C_DEBUG_BUS is not set +CONFIG_SLIMBUS=y +# CONFIG_SLIMBUS_MSM_CTRL is not set +CONFIG_SLIMBUS_MSM_NGD=y +CONFIG_SOUNDWIRE=y +CONFIG_SOUNDWIRE_WCD_CTRL=y +CONFIG_SPI=y +# CONFIG_SPI_DEBUG is not set +CONFIG_SPI_MASTER=y + +# +# SPI Master Controller Drivers +# +# CONFIG_SPI_ALTERA is not set +# CONFIG_SPI_BITBANG is not set +# CONFIG_SPI_CADENCE is not set +# CONFIG_SPI_GPIO is not set +# CONFIG_SPI_FSL_SPI is not set +# CONFIG_SPI_OC_TINY is not set +# CONFIG_SPI_PL022 is not set +# CONFIG_SPI_PXA2XX is not set +# CONFIG_SPI_PXA2XX_PCI is not set +# CONFIG_SPI_ROCKCHIP is not set +CONFIG_SPI_QUP=y +# CONFIG_SPI_SC18IS602 is not set +# CONFIG_SPI_XCOMM is not set +# CONFIG_SPI_XILINX is not set +# CONFIG_SPI_ZYNQMP_GQSPI is not set +# CONFIG_SPI_DESIGNWARE is not set + +# +# SPI Protocol Masters +# +CONFIG_SPI_SPIDEV=y +# CONFIG_SPI_TLE62X0 is not set +# CONFIG_SPI_SLAVE is not set +CONFIG_SPMI=y +CONFIG_SPMI_MSM_PMIC_ARB=y +# CONFIG_HSI is not set + +# +# PPS support +# +# CONFIG_PPS is not set + +# +# PPS generators support +# + +# +# PTP clock support +# +# CONFIG_PTP_1588_CLOCK is not set + +# +# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. +# +CONFIG_PINCTRL=y + +# +# Pin controllers +# +CONFIG_PINMUX=y +CONFIG_PINCONF=y +CONFIG_GENERIC_PINCONF=y +# CONFIG_DEBUG_PINCTRL is not set +# CONFIG_PINCTRL_AMD is not set +# CONFIG_PINCTRL_SINGLE is not set +# CONFIG_PINCTRL_BAYTRAIL is not set +# CONFIG_PINCTRL_CHERRYVIEW is not set +# CONFIG_PINCTRL_BROXTON is not set +# CONFIG_PINCTRL_SUNRISEPOINT is not set +CONFIG_PINCTRL_MSM=y +# CONFIG_PINCTRL_APQ8064 is not set +# CONFIG_PINCTRL_APQ8084 is not set +# CONFIG_PINCTRL_IPQ8064 is not set +# CONFIG_PINCTRL_MSM8660 is not set +# CONFIG_PINCTRL_MSM8960 is not set +# CONFIG_PINCTRL_MSM8X74 is not set +# CONFIG_PINCTRL_MSM8916 is not set +# CONFIG_PINCTRL_QDF2XXX is not set +# CONFIG_PINCTRL_QCOM_SPMI_PMIC is not set +# CONFIG_PINCTRL_QCOM_SSBI_PMIC is not set +CONFIG_PINCTRL_MSM8998=y +# CONFIG_PINCTRL_MSM8996 is not set +# CONFIG_PINCTRL_SDM660 is not set +CONFIG_PINCTRL_WCD=y +# CONFIG_PINCTRL_LPI is not set +CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y +CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y +CONFIG_GPIOLIB=y +CONFIG_GPIO_DEVRES=y +CONFIG_OF_GPIO=y +CONFIG_GPIO_ACPI=y +CONFIG_GPIOLIB_IRQCHIP=y +# CONFIG_DEBUG_GPIO is not set +CONFIG_GPIO_SYSFS=y + +# +# Memory mapped GPIO drivers +# +# CONFIG_GPIO_74XX_MMIO is not set +# CONFIG_GPIO_ALTERA is not set +# CONFIG_GPIO_AMDPT is not set +# CONFIG_GPIO_DWAPB is not set +# CONFIG_GPIO_GENERIC_PLATFORM is not set +# CONFIG_GPIO_GRGPIO is not set +# CONFIG_GPIO_PL061 is not set +CONFIG_GPIO_QPNP_PIN=y +# CONFIG_GPIO_QPNP_PIN_DEBUG is not set +# CONFIG_GPIO_SYSCON is not set +# CONFIG_GPIO_VX855 is not set +# CONFIG_GPIO_XGENE is not set +# CONFIG_GPIO_XILINX is not set +# CONFIG_GPIO_ZX is not set + +# +# I2C GPIO expanders +# +# CONFIG_GPIO_ADP5588 is not set +# CONFIG_GPIO_ADNP is not set +# CONFIG_GPIO_MAX7300 is not set +# CONFIG_GPIO_MAX732X is not set +CONFIG_GPIO_PCA953X=y +CONFIG_GPIO_PCA953X_IRQ=y +# CONFIG_GPIO_PCF857X is not set +# CONFIG_GPIO_SX150X is not set + +# +# MFD GPIO expanders +# + +# +# PCI GPIO expanders +# +# CONFIG_GPIO_AMD8111 is not set +# CONFIG_GPIO_BT8XX is not set +# CONFIG_GPIO_ML_IOH is not set +# CONFIG_GPIO_RDC321X is not set + +# +# SPI GPIO expanders +# +# CONFIG_GPIO_74X164 is not set +# CONFIG_GPIO_MAX7301 is not set +# CONFIG_GPIO_MC33880 is not set + +# +# SPI or I2C GPIO expanders +# +# CONFIG_GPIO_MCP23S08 is not set + +# +# USB GPIO expanders +# +CONFIG_FREEBOX_GPIO=y +CONFIG_FREEBOX_GPIO_DT=y +# CONFIG_W1 is not set +CONFIG_POWER_SUPPLY=y +# CONFIG_POWER_SUPPLY_DEBUG is not set +# CONFIG_PDA_POWER is not set +# CONFIG_GENERIC_ADC_BATTERY is not set +# CONFIG_TEST_POWER is not set +# CONFIG_BATTERY_DS2780 is not set +# CONFIG_BATTERY_DS2781 is not set +# CONFIG_BATTERY_DS2782 is not set +# CONFIG_BATTERY_SBS is not set +# CONFIG_BATTERY_BQ27XXX is not set +# CONFIG_BATTERY_MAX17040 is not set +# CONFIG_BATTERY_MAX17042 is not set +# CONFIG_CHARGER_ISP1704 is not set +# CONFIG_CHARGER_MAX8903 is not set +# CONFIG_CHARGER_LP8727 is not set +# CONFIG_CHARGER_GPIO is not set +# CONFIG_CHARGER_MANAGER is not set +# CONFIG_CHARGER_QCOM_SMBB is not set +# CONFIG_CHARGER_BQ2415X is not set +# CONFIG_CHARGER_BQ24190 is not set +# CONFIG_CHARGER_BQ24257 is not set +# CONFIG_CHARGER_BQ24735 is not set +# CONFIG_CHARGER_BQ25890 is not set +# CONFIG_CHARGER_SMB347 is not set +# CONFIG_BATTERY_BQ28400 is not set +# CONFIG_BATTERY_GAUGE_LTC2941 is not set +# CONFIG_CHARGER_RT9455 is not set +CONFIG_POWER_RESET=y +# CONFIG_POWER_RESET_GPIO is not set +# CONFIG_POWER_RESET_GPIO_RESTART is not set +# CONFIG_POWER_RESET_LTC2952 is not set +CONFIG_POWER_RESET_QCOM=y +# CONFIG_QCOM_DLOAD_MODE is not set +# CONFIG_POWER_RESET_RESTART is not set +CONFIG_POWER_RESET_XGENE=y +CONFIG_POWER_RESET_SYSCON=y +# CONFIG_POWER_RESET_SYSCON_POWEROFF is not set +# CONFIG_SYSCON_REBOOT_MODE is not set + +# +# Qualcomm Technologies Inc Charger and Fuel Gauge support +# +# CONFIG_QPNP_SMBCHARGER is not set +# CONFIG_QPNP_FG is not set +CONFIG_QPNP_FG_GEN3=y +# CONFIG_SMB135X_CHARGER is not set +# CONFIG_SMB1351_USB_CHARGER is not set +CONFIG_MSM_BCL_CTL=y +CONFIG_MSM_BCL_PERIPHERAL_CTL=y +CONFIG_BATTERY_BCL=y +CONFIG_QPNP_SMB2=y +CONFIG_SMB138X_CHARGER=y +CONFIG_QPNP_QNOVO=y +# CONFIG_POWER_AVS is not set +CONFIG_MSM_PM=y +CONFIG_APSS_CORE_EA=y +CONFIG_MSM_APM=y +CONFIG_MSM_IDLE_STATS=y +CONFIG_MSM_IDLE_STATS_FIRST_BUCKET=62500 +CONFIG_MSM_IDLE_STATS_BUCKET_SHIFT=2 +CONFIG_MSM_IDLE_STATS_BUCKET_COUNT=10 +CONFIG_MSM_SUSPEND_STATS_FIRST_BUCKET=1000000000 +CONFIG_HWMON=y +# CONFIG_HWMON_VID is not set +# CONFIG_HWMON_DEBUG_CHIP is not set + +# +# Native drivers +# +# CONFIG_SENSORS_AD7314 is not set +# CONFIG_SENSORS_AD7414 is not set +# CONFIG_SENSORS_AD7418 is not set +# CONFIG_SENSORS_ADM1021 is not set +# CONFIG_SENSORS_ADM1025 is not set +# CONFIG_SENSORS_ADM1026 is not set +# CONFIG_SENSORS_ADM1029 is not set +# CONFIG_SENSORS_ADM1031 is not set +# CONFIG_SENSORS_ADM9240 is not set +# CONFIG_SENSORS_ADT7310 is not set +# CONFIG_SENSORS_ADT7410 is not set +# CONFIG_SENSORS_ADT7411 is not set +# CONFIG_SENSORS_ADT7462 is not set +# CONFIG_SENSORS_ADT7470 is not set +# CONFIG_SENSORS_ADT7475 is not set +# CONFIG_SENSORS_ASC7621 is not set +# CONFIG_SENSORS_ATXP1 is not set +# CONFIG_SENSORS_DS620 is not set +# CONFIG_SENSORS_DS1621 is not set +# CONFIG_SENSORS_I5K_AMB is not set +# CONFIG_SENSORS_F71805F is not set +# CONFIG_SENSORS_F71882FG is not set +# CONFIG_SENSORS_F75375S is not set +# CONFIG_SENSORS_GL518SM is not set +# CONFIG_SENSORS_GL520SM is not set +# CONFIG_SENSORS_G760A is not set +# CONFIG_SENSORS_G762 is not set +# CONFIG_SENSORS_GPIO_FAN is not set +# CONFIG_SENSORS_HIH6130 is not set +# CONFIG_SENSORS_IIO_HWMON is not set +# CONFIG_SENSORS_IT87 is not set +# CONFIG_SENSORS_JC42 is not set +# CONFIG_SENSORS_POWR1220 is not set +# CONFIG_SENSORS_LINEAGE is not set +# CONFIG_SENSORS_LTC2945 is not set +# CONFIG_SENSORS_LTC4151 is not set +# CONFIG_SENSORS_LTC4215 is not set +# CONFIG_SENSORS_LTC4222 is not set +# CONFIG_SENSORS_LTC4245 is not set +# CONFIG_SENSORS_LTC4260 is not set +# CONFIG_SENSORS_LTC4261 is not set +# CONFIG_SENSORS_MAX1111 is not set +# CONFIG_SENSORS_MAX16065 is not set +# CONFIG_SENSORS_MAX1619 is not set +# CONFIG_SENSORS_MAX1668 is not set +# CONFIG_SENSORS_MAX197 is not set +# CONFIG_SENSORS_MAX6639 is not set +# CONFIG_SENSORS_MAX6642 is not set +# CONFIG_SENSORS_MAX6650 is not set +# CONFIG_SENSORS_MAX6697 is not set +# CONFIG_SENSORS_MAX31790 is not set +# CONFIG_SENSORS_HTU21 is not set +# CONFIG_SENSORS_MCP3021 is not set +# CONFIG_SENSORS_ADCXX is not set +# CONFIG_SENSORS_LM63 is not set +# CONFIG_SENSORS_LM70 is not set +# CONFIG_SENSORS_LM73 is not set +CONFIG_SENSORS_LM75=y +# CONFIG_SENSORS_LM77 is not set +# CONFIG_SENSORS_LM78 is not set +# CONFIG_SENSORS_LM80 is not set +# CONFIG_SENSORS_LM83 is not set +# CONFIG_SENSORS_LM85 is not set +# CONFIG_SENSORS_LM87 is not set +# CONFIG_SENSORS_LM90 is not set +# CONFIG_SENSORS_LM92 is not set +# CONFIG_SENSORS_LM93 is not set +# CONFIG_SENSORS_LM95234 is not set +# CONFIG_SENSORS_LM95241 is not set +# CONFIG_SENSORS_LM95245 is not set +# CONFIG_SENSORS_PC87360 is not set +# CONFIG_SENSORS_PC87427 is not set +# CONFIG_SENSORS_NTC_THERMISTOR is not set +# CONFIG_SENSORS_NCT6683 is not set +# CONFIG_SENSORS_NCT6775 is not set +# CONFIG_SENSORS_NCT7802 is not set +# CONFIG_SENSORS_NCT7904 is not set +# CONFIG_SENSORS_PCF8591 is not set +# CONFIG_SENSORS_EPM_ADC is not set +CONFIG_SENSORS_QPNP_ADC_VOLTAGE=y +# CONFIG_SENSORS_QPNP_ADC_CURRENT is not set +# CONFIG_PMBUS is not set +# CONFIG_SENSORS_PWM_FAN is not set +# CONFIG_SENSORS_SHT15 is not set +# CONFIG_SENSORS_SHT21 is not set +# CONFIG_SENSORS_SHTC1 is not set +# CONFIG_SENSORS_SIS5595 is not set +# CONFIG_SENSORS_DME1737 is not set +# CONFIG_SENSORS_EMC1403 is not set +# CONFIG_SENSORS_EMC2103 is not set +# CONFIG_SENSORS_EMC6W201 is not set +# CONFIG_SENSORS_SMSC47M1 is not set +# CONFIG_SENSORS_SMSC47M192 is not set +# CONFIG_SENSORS_SMSC47B397 is not set +# CONFIG_SENSORS_SCH56XX_COMMON is not set +# CONFIG_SENSORS_SMM665 is not set +# CONFIG_SENSORS_ADC128D818 is not set +# CONFIG_SENSORS_ADS1015 is not set +# CONFIG_SENSORS_ADS7828 is not set +# CONFIG_SENSORS_ADS7871 is not set +# CONFIG_SENSORS_AMC6821 is not set +# CONFIG_SENSORS_INA209 is not set +# CONFIG_SENSORS_INA2XX is not set +# CONFIG_SENSORS_TC74 is not set +# CONFIG_SENSORS_THMC50 is not set +# CONFIG_SENSORS_TMP102 is not set +# CONFIG_SENSORS_TMP103 is not set +# CONFIG_SENSORS_TMP401 is not set +# CONFIG_SENSORS_TMP421 is not set +# CONFIG_SENSORS_VIA686A is not set +# CONFIG_SENSORS_VT1211 is not set +# CONFIG_SENSORS_VT8231 is not set +# CONFIG_SENSORS_W83781D is not set +# CONFIG_SENSORS_W83791D is not set +# CONFIG_SENSORS_W83792D is not set +# CONFIG_SENSORS_W83793 is not set +# CONFIG_SENSORS_W83795 is not set +# CONFIG_SENSORS_W83L785TS is not set +# CONFIG_SENSORS_W83L786NG is not set +# CONFIG_SENSORS_W83627HF is not set +# CONFIG_SENSORS_W83627EHF is not set + +# +# ACPI drivers +# +# CONFIG_SENSORS_ACPI_POWER is not set +CONFIG_THERMAL=y +CONFIG_THERMAL_HWMON=y +CONFIG_THERMAL_OF=y +CONFIG_THERMAL_WRITABLE_TRIPS=y +CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y +# CONFIG_THERMAL_DEFAULT_GOV_FAIR_SHARE is not set +# CONFIG_THERMAL_DEFAULT_GOV_USER_SPACE is not set +# CONFIG_THERMAL_DEFAULT_GOV_POWER_ALLOCATOR is not set +# CONFIG_THERMAL_GOV_FAIR_SHARE is not set +CONFIG_THERMAL_GOV_STEP_WISE=y +# CONFIG_THERMAL_GOV_BANG_BANG is not set +# CONFIG_THERMAL_GOV_USER_SPACE is not set +# CONFIG_THERMAL_GOV_POWER_ALLOCATOR is not set +CONFIG_CPU_THERMAL=y +CONFIG_DEVFREQ_THERMAL=y +# CONFIG_THERMAL_EMULATION is not set +CONFIG_LIMITS_MONITOR=y +CONFIG_LIMITS_LITE_HW=y +CONFIG_THERMAL_MONITOR=y +CONFIG_THERMAL_TSENS8974=y +# CONFIG_IMX_THERMAL is not set +CONFIG_THERMAL_QPNP=y +CONFIG_THERMAL_QPNP_ADC_TM=y +CONFIG_QCOM_THERMAL_LIMITS_DCVS=y +# CONFIG_QCOM_SPMI_TEMP_ALARM is not set +# CONFIG_WATCHDOG is not set +CONFIG_SSB_POSSIBLE=y + +# +# Sonics Silicon Backplane +# +# CONFIG_SSB is not set +CONFIG_BCMA_POSSIBLE=y + +# +# Broadcom specific AMBA +# +# CONFIG_BCMA is not set + +# +# Multifunction device drivers +# +CONFIG_MFD_CORE=y +# CONFIG_MFD_AS3711 is not set +# CONFIG_MFD_AS3722 is not set +# CONFIG_PMIC_ADP5520 is not set +# CONFIG_MFD_AAT2870_CORE is not set +# CONFIG_MFD_ATMEL_FLEXCOM is not set +# CONFIG_MFD_ATMEL_HLCDC is not set +# CONFIG_MFD_BCM590XX is not set +# CONFIG_MFD_AXP20X is not set +# CONFIG_PMIC_DA903X is not set +# CONFIG_MFD_DA9052_SPI is not set +# CONFIG_MFD_DA9052_I2C is not set +# CONFIG_MFD_DA9055 is not set +# CONFIG_MFD_DA9062 is not set +# CONFIG_MFD_DA9063 is not set +# CONFIG_MFD_DA9150 is not set +# CONFIG_MFD_DLN2 is not set +# CONFIG_MFD_MC13XXX_SPI is not set +# CONFIG_MFD_MC13XXX_I2C is not set +# CONFIG_MFD_HI6421_PMIC is not set +# CONFIG_HTC_PASIC3 is not set +# CONFIG_HTC_I2CPLD is not set +# CONFIG_LPC_ICH is not set +# CONFIG_LPC_SCH is not set +# CONFIG_INTEL_SOC_PMIC is not set +# CONFIG_MFD_JANZ_CMODIO is not set +# CONFIG_MFD_KEMPLD is not set +# CONFIG_MFD_88PM800 is not set +# CONFIG_MFD_88PM805 is not set +# CONFIG_MFD_88PM860X is not set +# CONFIG_MFD_MAX14577 is not set +# CONFIG_MFD_MAX77686 is not set +# CONFIG_MFD_MAX77693 is not set +# CONFIG_MFD_MAX77843 is not set +# CONFIG_MFD_MAX8907 is not set +# CONFIG_MFD_MAX8925 is not set +# CONFIG_MFD_MAX8997 is not set +# CONFIG_MFD_MAX8998 is not set +# CONFIG_MFD_MT6397 is not set +# CONFIG_MFD_MENF21BMC is not set +# CONFIG_EZX_PCAP is not set +# CONFIG_MFD_VIPERBOARD is not set +# CONFIG_MFD_RETU is not set +# CONFIG_MFD_PCF50633 is not set +# CONFIG_MFD_QCOM_RPM is not set +CONFIG_MFD_SPMI_PMIC=y +CONFIG_MFD_I2C_PMIC=y +# CONFIG_MFD_RDC321X is not set +# CONFIG_MFD_RTSX_PCI is not set +# CONFIG_MFD_RT5033 is not set +# CONFIG_MFD_RTSX_USB is not set +# CONFIG_MFD_RC5T583 is not set +# CONFIG_MFD_RK808 is not set +# CONFIG_MFD_RN5T618 is not set +# CONFIG_MFD_SEC_CORE is not set +# CONFIG_MFD_SI476X_CORE is not set +# CONFIG_MFD_SM501 is not set +# CONFIG_MFD_SKY81452 is not set +# CONFIG_MFD_SMSC is not set +# CONFIG_ABX500_CORE is not set +# CONFIG_MFD_STMPE is not set +CONFIG_MFD_SYSCON=y +# CONFIG_MFD_TI_AM335X_TSCADC is not set +# CONFIG_MFD_LP3943 is not set +# CONFIG_MFD_LP8788 is not set +# CONFIG_MFD_PALMAS is not set +# CONFIG_TPS6105X is not set +# CONFIG_TPS65010 is not set +# CONFIG_TPS6507X is not set +# CONFIG_MFD_TPS65090 is not set +# CONFIG_MFD_TPS65217 is not set +# CONFIG_MFD_TPS65218 is not set +# CONFIG_MFD_TPS6586X is not set +# CONFIG_MFD_TPS65910 is not set +# CONFIG_MFD_TPS65912 is not set +# CONFIG_MFD_TPS65912_I2C is not set +# CONFIG_MFD_TPS65912_SPI is not set +# CONFIG_MFD_TPS80031 is not set +# CONFIG_TWL4030_CORE is not set +# CONFIG_TWL6040_CORE is not set +# CONFIG_MFD_WL1273_CORE is not set +# CONFIG_MFD_LM3533 is not set +# CONFIG_MFD_TC3589X is not set +CONFIG_MFD_FBX7HD_TOP_PSOC=y +# CONFIG_MFD_TMIO is not set +# CONFIG_MFD_VX855 is not set +# CONFIG_MFD_ARIZONA_I2C is not set +# CONFIG_MFD_ARIZONA_SPI is not set +# CONFIG_MFD_WM8400 is not set +# CONFIG_MFD_WM831X_I2C is not set +# CONFIG_MFD_WM831X_SPI is not set +# CONFIG_MFD_WM8350_I2C is not set +# CONFIG_MFD_WM8994 is not set +CONFIG_MSM_CDC_PINCTRL=y +CONFIG_MSM_CDC_SUPPLY=y +CONFIG_WCD9XXX_CODEC_UTIL=y +# CONFIG_WCD9330_CODEC is not set +CONFIG_WCD9335_CODEC=y +CONFIG_WCD934X_CODEC=y +CONFIG_REGULATOR=y +# CONFIG_REGULATOR_DEBUG is not set +CONFIG_REGULATOR_FIXED_VOLTAGE=y +# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set +# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set +# CONFIG_REGULATOR_ACT8865 is not set +# CONFIG_REGULATOR_AD5398 is not set +# CONFIG_REGULATOR_ANATOP is not set +# CONFIG_REGULATOR_DA9210 is not set +# CONFIG_REGULATOR_DA9211 is not set +# CONFIG_REGULATOR_FAN53555 is not set +# CONFIG_REGULATOR_MSM_GFX_LDO is not set +# CONFIG_REGULATOR_GPIO is not set +# CONFIG_REGULATOR_ISL9305 is not set +# CONFIG_REGULATOR_ISL6271A is not set +# CONFIG_REGULATOR_LP3971 is not set +# CONFIG_REGULATOR_LP3972 is not set +# CONFIG_REGULATOR_LP872X is not set +# CONFIG_REGULATOR_LP8755 is not set +# CONFIG_REGULATOR_LTC3589 is not set +# CONFIG_REGULATOR_MAX1586 is not set +# CONFIG_REGULATOR_MAX20010 is not set +# CONFIG_REGULATOR_MAX8649 is not set +# CONFIG_REGULATOR_MAX8660 is not set +# CONFIG_REGULATOR_MAX8952 is not set +# CONFIG_REGULATOR_MAX8973 is not set +# CONFIG_REGULATOR_MT6311 is not set +# CONFIG_REGULATOR_ONSEMI_NCP6335D is not set +# CONFIG_REGULATOR_PFUZE100 is not set +# CONFIG_REGULATOR_PWM is not set +# CONFIG_REGULATOR_QCOM_SPMI is not set +# CONFIG_REGULATOR_TPS51632 is not set +# CONFIG_REGULATOR_TPS62360 is not set +# CONFIG_REGULATOR_TPS65023 is not set +# CONFIG_REGULATOR_TPS6507X is not set +# CONFIG_REGULATOR_TPS6524X is not set +CONFIG_REGULATOR_RPM_SMD=y +CONFIG_REGULATOR_QPNP=y +CONFIG_REGULATOR_QPNP_LABIBB=y +CONFIG_REGULATOR_QPNP_LCDB=y +# CONFIG_REGULATOR_QPNP_OLEDB is not set +CONFIG_REGULATOR_SPM=y +# CONFIG_REGULATOR_CPR is not set +# CONFIG_REGULATOR_CPR2_GFX is not set +CONFIG_REGULATOR_CPR3=y +CONFIG_REGULATOR_CPR3_HMSS=y +CONFIG_REGULATOR_CPR3_MMSS=y +# CONFIG_REGULATOR_CPR4_APSS is not set +CONFIG_REGULATOR_CPRH_KBSS=y +# CONFIG_REGULATOR_CPR4_MMSS_LDO is not set +# CONFIG_REGULATOR_KRYO is not set +CONFIG_REGULATOR_MEM_ACC=y +CONFIG_REGULATOR_PROXY_CONSUMER=y +CONFIG_REGULATOR_STUB=y +CONFIG_MEDIA_SUPPORT=y + +# +# Multimedia core support +# +CONFIG_MEDIA_CAMERA_SUPPORT=y +# CONFIG_MEDIA_ANALOG_TV_SUPPORT is not set +CONFIG_MEDIA_DIGITAL_TV_SUPPORT=y +CONFIG_MEDIA_RADIO_SUPPORT=y +# CONFIG_MEDIA_SDR_SUPPORT is not set +CONFIG_MEDIA_RC_SUPPORT=y +CONFIG_MEDIA_CEC_SUPPORT=y +CONFIG_MEDIA_CONTROLLER=y +CONFIG_VIDEO_DEV=y +CONFIG_VIDEO_V4L2_SUBDEV_API=y +CONFIG_VIDEO_V4L2=y +CONFIG_VIDEO_ADV_DEBUG=y +# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set +CONFIG_VIDEOBUF2_CORE=y +CONFIG_DVB_CORE=y +# CONFIG_DVB_NET is not set +# CONFIG_TTPCI_EEPROM is not set +CONFIG_DVB_MAX_ADAPTERS=8 +# CONFIG_DVB_DYNAMIC_MINORS is not set + +# +# Media drivers +# +CONFIG_RC_CORE=y +CONFIG_RC_MAP=y +CONFIG_RC_DECODERS=y +# CONFIG_LIRC is not set +# CONFIG_IR_NEC_DECODER is not set +# CONFIG_IR_RC5_DECODER is not set +CONFIG_IR_RC6_DECODER=y +# CONFIG_IR_JVC_DECODER is not set +# CONFIG_IR_SONY_DECODER is not set +# CONFIG_IR_SANYO_DECODER is not set +# CONFIG_IR_SHARP_DECODER is not set +CONFIG_IR_MCE_KBD_DECODER=y +# CONFIG_IR_XMP_DECODER is not set +CONFIG_RC_DEVICES=y +# CONFIG_RC_ATI_REMOTE is not set +# CONFIG_IR_ENE is not set +# CONFIG_IR_HIX5HD2 is not set +# CONFIG_IR_IMON is not set +CONFIG_IR_MCEUSB=y +# CONFIG_IR_ITE_CIR is not set +# CONFIG_IR_FINTEK is not set +# CONFIG_IR_NUVOTON is not set +# CONFIG_IR_REDRAT3 is not set +# CONFIG_IR_STREAMZAP is not set +# CONFIG_IR_IGORPLUGUSB is not set +# CONFIG_IR_IGUANA is not set +# CONFIG_IR_TTUSBIR is not set +# CONFIG_RC_LOOPBACK is not set +CONFIG_IR_GPIO_CIR=y +CONFIG_MEDIA_USB_SUPPORT=y + +# +# Webcam devices +# +# CONFIG_USB_VIDEO_CLASS is not set +# CONFIG_USB_GSPCA is not set +# CONFIG_USB_PWC is not set +# CONFIG_VIDEO_CPIA2 is not set +# CONFIG_USB_ZR364XX is not set +# CONFIG_USB_STKWEBCAM is not set +# CONFIG_USB_S2255 is not set +# CONFIG_VIDEO_USBTV is not set + +# +# Analog/digital TV USB devices +# +# CONFIG_VIDEO_AU0828 is not set +# CONFIG_VIDEO_CX231XX is not set +# CONFIG_VIDEO_TM6000 is not set + +# +# Digital TV USB devices +# +# CONFIG_DVB_USB is not set +# CONFIG_DVB_USB_V2 is not set +# CONFIG_DVB_TTUSB_BUDGET is not set +# CONFIG_DVB_TTUSB_DEC is not set +# CONFIG_SMS_USB_DRV is not set +# CONFIG_DVB_B2C2_FLEXCOP_USB is not set +# CONFIG_DVB_AS102 is not set + +# +# Webcam, TV (analog/digital) USB devices +# +# CONFIG_VIDEO_EM28XX is not set +# CONFIG_MEDIA_PCI_SUPPORT is not set +CONFIG_V4L_PLATFORM_DRIVERS=y +# CONFIG_VIDEO_CAFE_CCIC is not set +# CONFIG_SOC_CAMERA is not set +# CONFIG_VIDEO_XILINX is not set +# CONFIG_V4L_MEM2MEM_DRIVERS is not set +# CONFIG_V4L_TEST_DRIVERS is not set +# CONFIG_DVB_PLATFORM_DRIVERS is not set + +# +# QTI MSM Camera And Video & AIS +# +# CONFIG_MSM_CAMERA is not set +# CONFIG_MSMB_CAMERA is not set +CONFIG_MSM_VIDC_V4L2=y +CONFIG_MSM_VIDC_VMEM=y +CONFIG_MSM_VIDC_GOVERNORS=y +# CONFIG_MSM_SDE_ROTATOR is not set +CONFIG_MSM_SDE_HDMI_CEC=y +# CONFIG_MSM_AIS is not set +CONFIG_DVB_MSM_TSPP=m + +# +# Supported MMC/SDIO adapters +# +# CONFIG_SMS_SDIO_DRV is not set +CONFIG_RADIO_ADAPTERS=y +# CONFIG_RADIO_SI470X is not set +# CONFIG_RADIO_SI4713 is not set +# CONFIG_USB_MR800 is not set +# CONFIG_USB_DSBR is not set +# CONFIG_RADIO_MAXIRADIO is not set +# CONFIG_RADIO_SHARK is not set +# CONFIG_RADIO_SHARK2 is not set +# CONFIG_USB_KEENE is not set +# CONFIG_USB_RAREMONO is not set +# CONFIG_USB_MA901 is not set +# CONFIG_RADIO_TEA5764 is not set +# CONFIG_RADIO_SAA7706H is not set +# CONFIG_RADIO_TEF6862 is not set +# CONFIG_RADIO_WL1273 is not set + +# +# Texas Instruments WL128x FM driver (ST based) +# +# CONFIG_CYPRESS_FIRMWARE is not set + +# +# Media ancillary drivers (tuners, sensors, i2c, frontends) +# +# CONFIG_MEDIA_SUBDRV_AUTOSELECT is not set +CONFIG_MEDIA_ATTACH=y +# CONFIG_VIDEO_IR_I2C is not set + +# +# Encoders, decoders, sensors and other helper chips +# + +# +# Audio decoders, processors and mixers +# +# CONFIG_VIDEO_TVAUDIO is not set +# CONFIG_VIDEO_TDA7432 is not set +# CONFIG_VIDEO_TDA9840 is not set +# CONFIG_VIDEO_TEA6415C is not set +# CONFIG_VIDEO_TEA6420 is not set +# CONFIG_VIDEO_MSP3400 is not set +# CONFIG_VIDEO_CS5345 is not set +# CONFIG_VIDEO_CS53L32A is not set +# CONFIG_VIDEO_TLV320AIC23B is not set +# CONFIG_VIDEO_UDA1342 is not set +# CONFIG_VIDEO_WM8775 is not set +# CONFIG_VIDEO_WM8739 is not set +# CONFIG_VIDEO_VP27SMPX is not set +# CONFIG_VIDEO_SONY_BTF_MPX is not set + +# +# RDS decoders +# +# CONFIG_VIDEO_SAA6588 is not set + +# +# Video decoders +# +# CONFIG_VIDEO_ADV7180 is not set +# CONFIG_VIDEO_ADV7183 is not set +# CONFIG_VIDEO_ADV7604 is not set +# CONFIG_VIDEO_ADV7842 is not set +# CONFIG_VIDEO_ADV7481 is not set +# CONFIG_VIDEO_TVTUNER is not set +# CONFIG_VIDEO_BT819 is not set +# CONFIG_VIDEO_BT856 is not set +# CONFIG_VIDEO_BT866 is not set +# CONFIG_VIDEO_KS0127 is not set +# CONFIG_VIDEO_ML86V7667 is not set +# CONFIG_VIDEO_SAA7110 is not set +# CONFIG_VIDEO_SAA711X is not set +# CONFIG_VIDEO_TC358743 is not set +# CONFIG_VIDEO_TVP514X is not set +# CONFIG_VIDEO_TVP5150 is not set +# CONFIG_VIDEO_TVP7002 is not set +# CONFIG_VIDEO_TW2804 is not set +# CONFIG_VIDEO_TW9903 is not set +# CONFIG_VIDEO_TW9906 is not set +# CONFIG_VIDEO_VPX3220 is not set + +# +# Video and audio decoders +# +# CONFIG_VIDEO_SAA717X is not set +# CONFIG_VIDEO_CX25840 is not set + +# +# Video encoders +# +# CONFIG_VIDEO_SAA7127 is not set +# CONFIG_VIDEO_SAA7185 is not set +# CONFIG_VIDEO_ADV7170 is not set +# CONFIG_VIDEO_ADV7175 is not set +# CONFIG_VIDEO_ADV7343 is not set +# CONFIG_VIDEO_ADV7393 is not set +# CONFIG_VIDEO_ADV7511 is not set +# CONFIG_VIDEO_AD9389B is not set +# CONFIG_VIDEO_AK881X is not set +# CONFIG_VIDEO_THS8200 is not set + +# +# Camera sensor devices +# +# CONFIG_VIDEO_OV2659 is not set +# CONFIG_VIDEO_OV7640 is not set +# CONFIG_VIDEO_OV7670 is not set +# CONFIG_VIDEO_OV9650 is not set +# CONFIG_VIDEO_VS6624 is not set +# CONFIG_VIDEO_MT9M032 is not set +# CONFIG_VIDEO_MT9P031 is not set +# CONFIG_VIDEO_MT9T001 is not set +# CONFIG_VIDEO_MT9V011 is not set +# CONFIG_VIDEO_MT9V032 is not set +# CONFIG_VIDEO_SR030PC30 is not set +# CONFIG_VIDEO_NOON010PC30 is not set +# CONFIG_VIDEO_M5MOLS is not set +# CONFIG_VIDEO_S5K6AA is not set +# CONFIG_VIDEO_S5K6A3 is not set +# CONFIG_VIDEO_S5K4ECGX is not set +# CONFIG_VIDEO_S5K5BAF is not set +# CONFIG_VIDEO_SMIAPP is not set +# CONFIG_VIDEO_S5C73M3 is not set + +# +# Flash devices +# +# CONFIG_VIDEO_ADP1653 is not set +# CONFIG_VIDEO_AS3645A is not set +# CONFIG_VIDEO_LM3560 is not set +# CONFIG_VIDEO_LM3646 is not set + +# +# Video improvement chips +# +# CONFIG_VIDEO_UPD64031A is not set +# CONFIG_VIDEO_UPD64083 is not set + +# +# Audio/Video compression chips +# +# CONFIG_VIDEO_SAA6752HS is not set + +# +# Miscellaneous helper chips +# +# CONFIG_VIDEO_THS7303 is not set +# CONFIG_VIDEO_M52790 is not set + +# +# Sensors used on soc_camera driver +# +CONFIG_MEDIA_TUNER=y + +# +# Customize TV tuners +# +# CONFIG_MEDIA_TUNER_SIMPLE is not set +# CONFIG_MEDIA_TUNER_TDA8290 is not set +# CONFIG_MEDIA_TUNER_TDA827X is not set +# CONFIG_MEDIA_TUNER_TDA18271 is not set +# CONFIG_MEDIA_TUNER_TDA9887 is not set +# CONFIG_MEDIA_TUNER_TEA5761 is not set +# CONFIG_MEDIA_TUNER_TEA5767 is not set +# CONFIG_MEDIA_TUNER_MSI001 is not set +# CONFIG_MEDIA_TUNER_MT20XX is not set +# CONFIG_MEDIA_TUNER_MT2060 is not set +# CONFIG_MEDIA_TUNER_MT2063 is not set +# CONFIG_MEDIA_TUNER_MT2266 is not set +# CONFIG_MEDIA_TUNER_MT2131 is not set +# CONFIG_MEDIA_TUNER_QT1010 is not set +# CONFIG_MEDIA_TUNER_XC2028 is not set +# CONFIG_MEDIA_TUNER_XC5000 is not set +# CONFIG_MEDIA_TUNER_XC4000 is not set +# CONFIG_MEDIA_TUNER_MXL5005S is not set +# CONFIG_MEDIA_TUNER_MXL5007T is not set +# CONFIG_MEDIA_TUNER_MC44S803 is not set +# CONFIG_MEDIA_TUNER_MAX2165 is not set +# CONFIG_MEDIA_TUNER_TDA18218 is not set +# CONFIG_MEDIA_TUNER_FC0011 is not set +# CONFIG_MEDIA_TUNER_FC0012 is not set +# CONFIG_MEDIA_TUNER_FC0013 is not set +# CONFIG_MEDIA_TUNER_TDA18212 is not set +# CONFIG_MEDIA_TUNER_E4000 is not set +# CONFIG_MEDIA_TUNER_FC2580 is not set +# CONFIG_MEDIA_TUNER_M88RS6000T is not set +# CONFIG_MEDIA_TUNER_TUA9001 is not set +CONFIG_MEDIA_TUNER_SI2157=m +# CONFIG_MEDIA_TUNER_IT913X is not set +# CONFIG_MEDIA_TUNER_R820T is not set +# CONFIG_MEDIA_TUNER_MXL301RF is not set +# CONFIG_MEDIA_TUNER_QM1D1C0042 is not set + +# +# Customise DVB Frontends +# + +# +# Multistandard (satellite) frontends +# +# CONFIG_DVB_STB0899 is not set +# CONFIG_DVB_STB6100 is not set +# CONFIG_DVB_STV090x is not set +# CONFIG_DVB_STV6110x is not set +# CONFIG_DVB_M88DS3103 is not set + +# +# Multistandard (cable + terrestrial) frontends +# +# CONFIG_DVB_DRXK is not set +# CONFIG_DVB_TDA18271C2DD is not set +# CONFIG_DVB_SI2165 is not set + +# +# DVB-S (satellite) frontends +# +# CONFIG_DVB_CX24110 is not set +# CONFIG_DVB_CX24123 is not set +# CONFIG_DVB_MT312 is not set +# CONFIG_DVB_ZL10036 is not set +# CONFIG_DVB_ZL10039 is not set +# CONFIG_DVB_S5H1420 is not set +# CONFIG_DVB_STV0288 is not set +# CONFIG_DVB_STB6000 is not set +# CONFIG_DVB_STV0299 is not set +# CONFIG_DVB_STV6110 is not set +# CONFIG_DVB_STV0900 is not set +# CONFIG_DVB_TDA8083 is not set +# CONFIG_DVB_TDA10086 is not set +# CONFIG_DVB_TDA8261 is not set +# CONFIG_DVB_VES1X93 is not set +# CONFIG_DVB_TUNER_ITD1000 is not set +# CONFIG_DVB_TUNER_CX24113 is not set +# CONFIG_DVB_TDA826X is not set +# CONFIG_DVB_TUA6100 is not set +# CONFIG_DVB_CX24116 is not set +# CONFIG_DVB_CX24117 is not set +# CONFIG_DVB_CX24120 is not set +# CONFIG_DVB_SI21XX is not set +# CONFIG_DVB_TS2020 is not set +# CONFIG_DVB_DS3000 is not set +# CONFIG_DVB_MB86A16 is not set +# CONFIG_DVB_TDA10071 is not set + +# +# DVB-T (terrestrial) frontends +# +# CONFIG_DVB_SP8870 is not set +# CONFIG_DVB_SP887X is not set +# CONFIG_DVB_CX22700 is not set +# CONFIG_DVB_CX22702 is not set +# CONFIG_DVB_S5H1432 is not set +# CONFIG_DVB_DRXD is not set +# CONFIG_DVB_L64781 is not set +# CONFIG_DVB_TDA1004X is not set +# CONFIG_DVB_NXT6000 is not set +# CONFIG_DVB_MT352 is not set +# CONFIG_DVB_ZL10353 is not set +# CONFIG_DVB_DIB3000MB is not set +# CONFIG_DVB_DIB3000MC is not set +# CONFIG_DVB_DIB7000M is not set +# CONFIG_DVB_DIB7000P is not set +# CONFIG_DVB_DIB9000 is not set +# CONFIG_DVB_TDA10048 is not set +# CONFIG_DVB_AF9013 is not set +# CONFIG_DVB_EC100 is not set +# CONFIG_DVB_HD29L2 is not set +# CONFIG_DVB_STV0367 is not set +# CONFIG_DVB_CXD2820R is not set +# CONFIG_DVB_CXD2841ER is not set +# CONFIG_DVB_RTL2830 is not set +# CONFIG_DVB_RTL2832 is not set +CONFIG_DVB_SI2168=m +# CONFIG_DVB_AS102_FE is not set + +# +# DVB-C (cable) frontends +# +# CONFIG_DVB_VES1820 is not set +# CONFIG_DVB_TDA10021 is not set +# CONFIG_DVB_TDA10023 is not set +# CONFIG_DVB_STV0297 is not set + +# +# ATSC (North American/Korean Terrestrial/Cable DTV) frontends +# +# CONFIG_DVB_NXT200X is not set +# CONFIG_DVB_OR51211 is not set +# CONFIG_DVB_OR51132 is not set +# CONFIG_DVB_BCM3510 is not set +# CONFIG_DVB_LGDT330X is not set +# CONFIG_DVB_LGDT3305 is not set +# CONFIG_DVB_LGDT3306A is not set +# CONFIG_DVB_LG2160 is not set +# CONFIG_DVB_S5H1409 is not set +# CONFIG_DVB_AU8522_DTV is not set +# CONFIG_DVB_AU8522_V4L is not set +# CONFIG_DVB_S5H1411 is not set + +# +# ISDB-T (terrestrial) frontends +# +# CONFIG_DVB_S921 is not set +# CONFIG_DVB_DIB8000 is not set +# CONFIG_DVB_MB86A20S is not set + +# +# ISDB-S (satellite) & ISDB-T (terrestrial) frontends +# +# CONFIG_DVB_TC90522 is not set + +# +# Digital terrestrial only tuners/PLL +# +# CONFIG_DVB_PLL is not set +# CONFIG_DVB_TUNER_DIB0070 is not set +# CONFIG_DVB_TUNER_DIB0090 is not set + +# +# SEC control devices for DVB-S +# +# CONFIG_DVB_DRX39XYJ is not set +# CONFIG_DVB_LNBH25 is not set +# CONFIG_DVB_LNBP21 is not set +# CONFIG_DVB_LNBP22 is not set +# CONFIG_DVB_ISL6405 is not set +# CONFIG_DVB_ISL6421 is not set +# CONFIG_DVB_ISL6423 is not set +# CONFIG_DVB_A8293 is not set +# CONFIG_DVB_SP2 is not set +# CONFIG_DVB_LGS8GL5 is not set +# CONFIG_DVB_LGS8GXX is not set +# CONFIG_DVB_ATBM8830 is not set +# CONFIG_DVB_TDA665x is not set +# CONFIG_DVB_IX2505V is not set +# CONFIG_DVB_M88RS2000 is not set +# CONFIG_DVB_AF9033 is not set +# CONFIG_DVB_HORUS3A is not set +# CONFIG_DVB_ASCOT2E is not set + +# +# Tools to develop new frontends +# +# CONFIG_DVB_DUMMY_FE is not set + +# +# Graphics support +# +# CONFIG_VGA_ARB is not set +# CONFIG_QCOM_KGSL is not set +CONFIG_DRM=y +CONFIG_DRM_MIPI_DSI=y +CONFIG_DRM_KMS_HELPER=y +# CONFIG_DRM_FBDEV_EMULATION is not set +# CONFIG_DRM_LOAD_EDID_FIRMWARE is not set + +# +# I2C encoder or helper chips +# +# CONFIG_DRM_I2C_ADV7511 is not set +# CONFIG_DRM_I2C_CH7006 is not set +# CONFIG_DRM_I2C_SIL164 is not set +# CONFIG_DRM_I2C_NXP_TDA998X is not set +# CONFIG_DRM_TDFX is not set +# CONFIG_DRM_R128 is not set +# CONFIG_DRM_RADEON is not set +# CONFIG_DRM_AMDGPU is not set +# CONFIG_DRM_NOUVEAU is not set +# CONFIG_DRM_MGA is not set +# CONFIG_DRM_VIA is not set +# CONFIG_DRM_SAVAGE is not set +# CONFIG_DRM_VGEM is not set +# CONFIG_DRM_UDL is not set +# CONFIG_DRM_AST is not set +# CONFIG_DRM_MGAG200 is not set +# CONFIG_DRM_CIRRUS_QEMU is not set +# CONFIG_DRM_QXL is not set +# CONFIG_DRM_BOCHS is not set +CONFIG_DRM_MSM=y +# CONFIG_DRM_MSM_REGISTER_LOGGING is not set +CONFIG_DRM_MSM_DSI=y +CONFIG_DRM_MSM_DSI_STAGING=y +CONFIG_DRM_MSM_DSI_28NM_PHY=y +CONFIG_DRM_MSM_DSI_20NM_PHY=y +# CONFIG_DRM_MSM_MDP4 is not set +# CONFIG_DRM_MSM_HDCP is not set +CONFIG_DRM_SDE_WB=y +CONFIG_DRM_SDE_HDMI=y +# CONFIG_DRM_SDE_EVTLOG_DEBUG is not set +CONFIG_DRM_PANEL=y + +# +# Display Panels +# +# CONFIG_DRM_PANEL_SIMPLE is not set +# CONFIG_DRM_PANEL_SAMSUNG_LD9040 is not set +# CONFIG_DRM_PANEL_LG_LG4573 is not set +# CONFIG_DRM_PANEL_SAMSUNG_S6E8AA0 is not set +# CONFIG_DRM_PANEL_SHARP_LQ101R1SX01 is not set +CONFIG_DRM_BRIDGE=y + +# +# Display Interface Bridges +# +# CONFIG_DRM_NXP_PTN3460 is not set +# CONFIG_DRM_PARADE_PS8622 is not set +# CONFIG_MSM_BA_V4L2 is not set + +# +# Frame buffer Devices +# +CONFIG_FB=y +# CONFIG_FIRMWARE_EDID is not set +CONFIG_FB_CMDLINE=y +# CONFIG_FB_DDC is not set +# CONFIG_FB_BOOT_VESA_SUPPORT is not set +# CONFIG_FB_CFB_FILLRECT is not set +# CONFIG_FB_CFB_COPYAREA is not set +# CONFIG_FB_CFB_IMAGEBLIT is not set +# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set +# CONFIG_FB_SYS_FILLRECT is not set +# CONFIG_FB_SYS_COPYAREA is not set +# CONFIG_FB_SYS_IMAGEBLIT is not set +# CONFIG_FB_FOREIGN_ENDIAN is not set +# CONFIG_FB_SYS_FOPS is not set +# CONFIG_FB_SVGALIB is not set +# CONFIG_FB_MACMODES is not set +# CONFIG_FB_BACKLIGHT is not set +# CONFIG_FB_MODE_HELPERS is not set +# CONFIG_FB_TILEBLITTING is not set + +# +# Frame buffer hardware drivers +# +# CONFIG_FB_CIRRUS is not set +# CONFIG_FB_PM2 is not set +# CONFIG_FB_ARMCLCD is not set +# CONFIG_FB_CYBER2000 is not set +# CONFIG_FB_ASILIANT is not set +# CONFIG_FB_IMSTT is not set +# CONFIG_FB_OPENCORES is not set +# CONFIG_FB_S1D13XXX is not set +# CONFIG_FB_NVIDIA is not set +# CONFIG_FB_RIVA is not set +# CONFIG_FB_I740 is not set +# CONFIG_FB_MATROX is not set +# CONFIG_FB_RADEON is not set +# CONFIG_FB_ATY128 is not set +# CONFIG_FB_ATY is not set +# CONFIG_FB_S3 is not set +# CONFIG_FB_SAVAGE is not set +# CONFIG_FB_SIS is not set +# CONFIG_FB_NEOMAGIC is not set +# CONFIG_FB_KYRO is not set +# CONFIG_FB_3DFX is not set +# CONFIG_FB_VOODOO1 is not set +# CONFIG_FB_VT8623 is not set +# CONFIG_FB_TRIDENT is not set +# CONFIG_FB_ARK is not set +# CONFIG_FB_PM3 is not set +# CONFIG_FB_CARMINE is not set +# CONFIG_FB_SMSCUFX is not set +# CONFIG_FB_UDL is not set +# CONFIG_FB_IBM_GXT4500 is not set +# CONFIG_FB_VIRTUAL is not set +# CONFIG_FB_METRONOME is not set +# CONFIG_FB_MB862XX is not set +# CONFIG_FB_MSM is not set +# CONFIG_FB_BROADSHEET is not set +# CONFIG_FB_AUO_K190X is not set +# CONFIG_FB_SIMPLE is not set +# CONFIG_MSM_DBA is not set +# CONFIG_FB_SSD1307 is not set +# CONFIG_FB_SM712 is not set +CONFIG_BACKLIGHT_LCD_SUPPORT=y +# CONFIG_LCD_CLASS_DEVICE is not set +CONFIG_BACKLIGHT_CLASS_DEVICE=y +# CONFIG_BACKLIGHT_GENERIC is not set +# CONFIG_BACKLIGHT_PWM is not set +# CONFIG_BACKLIGHT_PM8941_WLED is not set +# CONFIG_BACKLIGHT_ADP8860 is not set +# CONFIG_BACKLIGHT_ADP8870 is not set +# CONFIG_BACKLIGHT_LM3630A is not set +# CONFIG_BACKLIGHT_LM3639 is not set +# CONFIG_BACKLIGHT_LP855X is not set +# CONFIG_BACKLIGHT_GPIO is not set +# CONFIG_BACKLIGHT_LV5207LP is not set +# CONFIG_BACKLIGHT_BD6107 is not set +# CONFIG_ADF is not set +# CONFIG_VGASTATE is not set +CONFIG_HDMI=y + +# +# Console display driver support +# +CONFIG_DUMMY_CONSOLE=y +CONFIG_DUMMY_CONSOLE_COLUMNS=80 +CONFIG_DUMMY_CONSOLE_ROWS=25 +# CONFIG_FRAMEBUFFER_CONSOLE is not set +# CONFIG_LOGO is not set +CONFIG_SOUND=y +# CONFIG_SOUND_OSS_CORE is not set +CONFIG_SND=y +CONFIG_SND_TIMER=y +CONFIG_SND_PCM=y +CONFIG_SND_HWDEP=y +CONFIG_SND_RAWMIDI=y +CONFIG_SND_COMPRESS_OFFLOAD=y +CONFIG_SND_JACK=y +# CONFIG_SND_SEQUENCER is not set +# CONFIG_SND_MIXER_OSS is not set +# CONFIG_SND_PCM_OSS is not set +CONFIG_SND_PCM_TIMER=y +# CONFIG_SND_HRTIMER is not set +CONFIG_SND_DYNAMIC_MINORS=y +CONFIG_SND_MAX_CARDS=32 +CONFIG_SND_SUPPORT_OLD_API=y +CONFIG_SND_PROC_FS=y +CONFIG_SND_VERBOSE_PROCFS=y +# CONFIG_SND_VERBOSE_PRINTK is not set +# CONFIG_SND_DEBUG is not set +# CONFIG_SND_RAWMIDI_SEQ is not set +# CONFIG_SND_OPL3_LIB_SEQ is not set +# CONFIG_SND_OPL4_LIB_SEQ is not set +# CONFIG_SND_SBAWE_SEQ is not set +# CONFIG_SND_EMU10K1_SEQ is not set +CONFIG_SND_DRIVERS=y +# CONFIG_SND_DUMMY is not set +# CONFIG_SND_ALOOP is not set +# CONFIG_SND_MTPAV is not set +# CONFIG_SND_SERIAL_U16550 is not set +# CONFIG_SND_MPU401 is not set +CONFIG_SND_PCI=y +# CONFIG_SND_AD1889 is not set +# CONFIG_SND_ALS300 is not set +# CONFIG_SND_ALI5451 is not set +# CONFIG_SND_ATIIXP is not set +# CONFIG_SND_ATIIXP_MODEM is not set +# CONFIG_SND_AU8810 is not set +# CONFIG_SND_AU8820 is not set +# CONFIG_SND_AU8830 is not set +# CONFIG_SND_AW2 is not set +# CONFIG_SND_AZT3328 is not set +# CONFIG_SND_BT87X is not set +# CONFIG_SND_CA0106 is not set +# CONFIG_SND_CMIPCI is not set +# CONFIG_SND_OXYGEN is not set +# CONFIG_SND_CS4281 is not set +# CONFIG_SND_CS46XX is not set +# CONFIG_SND_CTXFI is not set +# CONFIG_SND_DARLA20 is not set +# CONFIG_SND_GINA20 is not set +# CONFIG_SND_LAYLA20 is not set +# CONFIG_SND_DARLA24 is not set +# CONFIG_SND_GINA24 is not set +# CONFIG_SND_LAYLA24 is not set +# CONFIG_SND_MONA is not set +# CONFIG_SND_MIA is not set +# CONFIG_SND_ECHO3G is not set +# CONFIG_SND_INDIGO is not set +# CONFIG_SND_INDIGOIO is not set +# CONFIG_SND_INDIGODJ is not set +# CONFIG_SND_INDIGOIOX is not set +# CONFIG_SND_INDIGODJX is not set +# CONFIG_SND_EMU10K1 is not set +# CONFIG_SND_EMU10K1X is not set +# CONFIG_SND_ENS1370 is not set +# CONFIG_SND_ENS1371 is not set +# CONFIG_SND_ES1938 is not set +# CONFIG_SND_ES1968 is not set +# CONFIG_SND_FM801 is not set +# CONFIG_SND_HDSP is not set +# CONFIG_SND_HDSPM is not set +# CONFIG_SND_ICE1712 is not set +# CONFIG_SND_ICE1724 is not set +# CONFIG_SND_INTEL8X0 is not set +# CONFIG_SND_INTEL8X0M is not set +# CONFIG_SND_KORG1212 is not set +# CONFIG_SND_LOLA is not set +# CONFIG_SND_LX6464ES is not set +# CONFIG_SND_MAESTRO3 is not set +# CONFIG_SND_MIXART is not set +# CONFIG_SND_NM256 is not set +# CONFIG_SND_PCXHR is not set +# CONFIG_SND_RIPTIDE is not set +# CONFIG_SND_RME32 is not set +# CONFIG_SND_RME96 is not set +# CONFIG_SND_RME9652 is not set +# CONFIG_SND_SE6X is not set +# CONFIG_SND_SONICVIBES is not set +# CONFIG_SND_TRIDENT is not set +# CONFIG_SND_VIA82XX is not set +# CONFIG_SND_VIA82XX_MODEM is not set +# CONFIG_SND_VIRTUOSO is not set +# CONFIG_SND_VX222 is not set +# CONFIG_SND_YMFPCI is not set + +# +# HD-Audio +# +# CONFIG_SND_HDA_INTEL is not set +CONFIG_SND_HDA_PREALLOC_SIZE=64 +CONFIG_SND_SPI=y +CONFIG_SND_USB=y +CONFIG_SND_USB_AUDIO=y +# CONFIG_SND_USB_UA101 is not set +# CONFIG_SND_USB_CAIAQ is not set +# CONFIG_SND_USB_6FIRE is not set +# CONFIG_SND_USB_HIFACE is not set +# CONFIG_SND_BCD2000 is not set +# CONFIG_SND_USB_POD is not set +# CONFIG_SND_USB_PODHD is not set +# CONFIG_SND_USB_TONEPORT is not set +# CONFIG_SND_USB_VARIAX is not set +CONFIG_SND_USB_AUDIO_QMI=y +CONFIG_SND_SOC=y +CONFIG_SND_SOC_COMPRESS=y +# CONFIG_SND_ATMEL_SOC is not set +# CONFIG_SND_DESIGNWARE_I2S is not set + +# +# SoC Audio for Freescale CPUs +# + +# +# Common SoC Audio options for Freescale CPUs: +# +# CONFIG_SND_SOC_FSL_ASRC is not set +# CONFIG_SND_SOC_FSL_SAI is not set +# CONFIG_SND_SOC_FSL_SSI is not set +# CONFIG_SND_SOC_FSL_SPDIF is not set +# CONFIG_SND_SOC_FSL_ESAI is not set +# CONFIG_SND_SOC_IMX_AUDMUX is not set + +# +# MSM SoC Audio support +# +CONFIG_SND_SOC_MSM_HOSTLESS_PCM=y +CONFIG_SND_SOC_MSM_QDSP6V2_INTF=y +CONFIG_SND_SOC_QDSP6V2=y +# CONFIG_SND_SOC_QDSP_DEBUG is not set +# CONFIG_DOLBY_DS2 is not set +CONFIG_DOLBY_LICENSE=y +CONFIG_DTS_EAGLE=y +CONFIG_DTS_SRS_TM=y +CONFIG_QTI_PP=y +# CONFIG_QTI_PP_AUDIOSPHERE is not set +CONFIG_SND_SOC_CPE=y +# CONFIG_SND_SOC_INT_CODEC is not set +# CONFIG_SND_SOC_EXT_CODEC is not set +CONFIG_SND_SOC_MSM8998=y +# CONFIG_SND_SOC_QCOM is not set + +# +# Allwinner SoC Audio support +# +# CONFIG_SND_SUN4I_CODEC is not set +# CONFIG_SND_SOC_XTFPGA_I2S is not set +CONFIG_SND_SOC_I2C_AND_SPI=y + +# +# CODEC drivers +# +# CONFIG_SND_SOC_AC97_CODEC is not set +# CONFIG_SND_SOC_ADAU1701 is not set +# CONFIG_SND_SOC_AK4104 is not set +# CONFIG_SND_SOC_AK4554 is not set +# CONFIG_SND_SOC_AK4613 is not set +# CONFIG_SND_SOC_AK4642 is not set +# CONFIG_SND_SOC_AK5386 is not set +# CONFIG_SND_SOC_ALC5623 is not set +# CONFIG_SND_SOC_CS35L32 is not set +# CONFIG_SND_SOC_CS42L51_I2C is not set +# CONFIG_SND_SOC_CS42L52 is not set +# CONFIG_SND_SOC_CS42L56 is not set +# CONFIG_SND_SOC_CS42L73 is not set +# CONFIG_SND_SOC_CS4265 is not set +# CONFIG_SND_SOC_CS4270 is not set +# CONFIG_SND_SOC_CS4271_I2C is not set +# CONFIG_SND_SOC_CS4271_SPI is not set +# CONFIG_SND_SOC_CS42XX8_I2C is not set +# CONFIG_SND_SOC_CS4349 is not set +# CONFIG_SND_SOC_HDMI_CODEC is not set +# CONFIG_SND_SOC_ES8328 is not set +# CONFIG_SND_SOC_GTM601 is not set +# CONFIG_SND_SOC_PCM1681 is not set +# CONFIG_SND_SOC_PCM1792A is not set +# CONFIG_SND_SOC_PCM512x_I2C is not set +# CONFIG_SND_SOC_PCM512x_SPI is not set +# CONFIG_SND_SOC_RT5631 is not set +# CONFIG_SND_SOC_RT5677_SPI is not set +# CONFIG_SND_SOC_SGTL5000 is not set +CONFIG_SND_SOC_SIL9437=y +# CONFIG_SND_SOC_SIRF_AUDIO_CODEC is not set +# CONFIG_SND_SOC_SPDIF is not set +# CONFIG_SND_SOC_SSM2602_SPI is not set +# CONFIG_SND_SOC_SSM2602_I2C is not set +# CONFIG_SND_SOC_SSM4567 is not set +# CONFIG_SND_SOC_STA32X is not set +# CONFIG_SND_SOC_STA350 is not set +# CONFIG_SND_SOC_STI_SAS is not set +# CONFIG_SND_SOC_TAS2552 is not set +# CONFIG_SND_SOC_TAS5086 is not set +# CONFIG_SND_SOC_TAS571X is not set +CONFIG_SND_SOC_TAS5766=y +# CONFIG_SND_SOC_TFA9879 is not set +# CONFIG_SND_SOC_TLV320AIC23_I2C is not set +# CONFIG_SND_SOC_TLV320AIC23_SPI is not set +# CONFIG_SND_SOC_TLV320AIC31XX is not set +# CONFIG_SND_SOC_TLV320AIC3X is not set +# CONFIG_SND_SOC_TS3A227E is not set +CONFIG_SND_SOC_WCD934X_DSD=y +CONFIG_SND_SOC_WCD9335=y +CONFIG_SND_SOC_WCD934X=y +CONFIG_SND_SOC_WCD934X_MBHC=y +CONFIG_SND_SOC_WSA881X=y +CONFIG_SND_SOC_WCD9XXX=y +CONFIG_SND_SOC_WCD9XXX_V2=y +CONFIG_SND_SOC_WCD_CPE=y +CONFIG_AUDIO_EXT_CLK=y +CONFIG_SND_SOC_WCD_MBHC=y +CONFIG_SND_SOC_WCD_DSP_MGR=y +CONFIG_SND_SOC_WCD_SPI=y +# CONFIG_SND_SOC_WM8510 is not set +# CONFIG_SND_SOC_WM8523 is not set +# CONFIG_SND_SOC_WM8580 is not set +# CONFIG_SND_SOC_WM8711 is not set +# CONFIG_SND_SOC_WM8728 is not set +# CONFIG_SND_SOC_WM8731 is not set +# CONFIG_SND_SOC_WM8737 is not set +# CONFIG_SND_SOC_WM8741 is not set +# CONFIG_SND_SOC_WM8750 is not set +# CONFIG_SND_SOC_WM8753 is not set +# CONFIG_SND_SOC_WM8770 is not set +# CONFIG_SND_SOC_WM8776 is not set +CONFIG_SND_SOC_WM8804=y +CONFIG_SND_SOC_WM8804_I2C=y +# CONFIG_SND_SOC_WM8804_SPI is not set +# CONFIG_SND_SOC_WM8903 is not set +# CONFIG_SND_SOC_WM8962 is not set +# CONFIG_SND_SOC_WM8978 is not set +# CONFIG_SND_SOC_TPA6130A2 is not set +CONFIG_SND_SOC_MSM_STUB=y +CONFIG_SND_SOC_MSM_HDMI_CODEC_RX=y +# CONFIG_SND_SOC_SDM660_CDC is not set +# CONFIG_SND_SOC_MSM_SDW is not set +# CONFIG_SND_SIMPLE_CARD is not set +# CONFIG_SOUND_PRIME is not set + +# +# HID support +# +CONFIG_HID=y +# CONFIG_HID_BATTERY_STRENGTH is not set +CONFIG_HIDRAW=y +CONFIG_UHID=y +CONFIG_HID_GENERIC=y + +# +# Special HID drivers +# +# CONFIG_HID_A4TECH is not set +# CONFIG_HID_ACRUX is not set +CONFIG_HID_APPLE=y +# CONFIG_HID_APPLEIR is not set +# CONFIG_HID_AUREAL is not set +# CONFIG_HID_BELKIN is not set +# CONFIG_HID_BETOP_FF is not set +# CONFIG_HID_CHERRY is not set +# CONFIG_HID_CHICONY is not set +# CONFIG_HID_CORSAIR is not set +# CONFIG_HID_PRODIKEYS is not set +# CONFIG_HID_CP2112 is not set +# CONFIG_HID_CYPRESS is not set +# CONFIG_HID_DRAGONRISE is not set +# CONFIG_HID_EMS_FF is not set +# CONFIG_HID_ELECOM is not set +# CONFIG_HID_ELO is not set +# CONFIG_HID_EZKEY is not set +# CONFIG_HID_GEMBIRD is not set +# CONFIG_HID_GFRM is not set +# CONFIG_HID_HOLTEK is not set +# CONFIG_HID_GT683R is not set +# CONFIG_HID_KEYTOUCH is not set +# CONFIG_HID_KYE is not set +# CONFIG_HID_UCLOGIC is not set +# CONFIG_HID_WALTOP is not set +CONFIG_HID_FBX_REMOTE_AUDIO=y +# CONFIG_HID_GYRATION is not set +# CONFIG_HID_ICADE is not set +# CONFIG_HID_TWINHAN is not set +# CONFIG_HID_KENSINGTON is not set +# CONFIG_HID_LCPOWER is not set +# CONFIG_HID_LENOVO is not set +# CONFIG_HID_LOGITECH is not set +# CONFIG_HID_MAGICMOUSE is not set +CONFIG_HID_MICROSOFT=y +# CONFIG_HID_MONTEREY is not set +# CONFIG_HID_MULTITOUCH is not set +# CONFIG_HID_NTRIG is not set +# CONFIG_HID_ORTEK is not set +# CONFIG_HID_PANTHERLORD is not set +# CONFIG_HID_PENMOUNT is not set +# CONFIG_HID_PETALYNX is not set +# CONFIG_HID_PICOLCD is not set +# CONFIG_HID_PLANTRONICS is not set +# CONFIG_HID_PRIMAX is not set +# CONFIG_HID_ROCCAT is not set +# CONFIG_HID_SAITEK is not set +# CONFIG_HID_SAMSUNG is not set +# CONFIG_HID_SONY is not set +# CONFIG_HID_SPEEDLINK is not set +# CONFIG_HID_STEELSERIES is not set +# CONFIG_HID_SUNPLUS is not set +# CONFIG_HID_RMI is not set +# CONFIG_HID_GREENASIA is not set +# CONFIG_HID_SMARTJOYPLUS is not set +# CONFIG_HID_TIVO is not set +# CONFIG_HID_TOPSEED is not set +# CONFIG_HID_THINGM is not set +# CONFIG_HID_THRUSTMASTER is not set +# CONFIG_HID_WACOM is not set +# CONFIG_HID_WIIMOTE is not set +# CONFIG_HID_XINMO is not set +# CONFIG_HID_ZEROPLUS is not set +# CONFIG_HID_ZYDACRON is not set +# CONFIG_HID_SENSOR_HUB is not set + +# +# USB HID support +# +CONFIG_USB_HID=y +# CONFIG_HID_PID is not set +CONFIG_USB_HIDDEV=y + +# +# I2C HID support +# +# CONFIG_I2C_HID is not set +CONFIG_USB_OHCI_LITTLE_ENDIAN=y +CONFIG_USB_SUPPORT=y +CONFIG_USB_COMMON=y +CONFIG_USB_ARCH_HAS_HCD=y +CONFIG_USB=y +CONFIG_USB_ANNOUNCE_NEW_DEVICES=y + +# +# Miscellaneous USB options +# +CONFIG_USB_DEFAULT_PERSIST=y +# CONFIG_USB_DYNAMIC_MINORS is not set +# CONFIG_USB_OTG is not set +# CONFIG_USB_OTG_WHITELIST is not set +# CONFIG_USB_OTG_BLACKLIST_HUB is not set +# CONFIG_USB_ULPI_BUS is not set +# CONFIG_USB_MON is not set +# CONFIG_USB_WUSB_CBAF is not set + +# +# USB Host Controller Drivers +# +# CONFIG_USB_C67X00_HCD is not set +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_PCI=y +CONFIG_USB_XHCI_PLATFORM=y +# CONFIG_USB_EHCI_HCD is not set +# CONFIG_USB_OXU210HP_HCD is not set +# CONFIG_USB_ISP116X_HCD is not set +# CONFIG_USB_ISP1362_HCD is not set +# CONFIG_USB_FOTG210_HCD is not set +# CONFIG_USB_MAX3421_HCD is not set +# CONFIG_USB_OHCI_HCD is not set +# CONFIG_USB_UHCI_HCD is not set +# CONFIG_USB_SL811_HCD is not set +# CONFIG_USB_R8A66597_HCD is not set +# CONFIG_USB_HCD_TEST_MODE is not set + +# +# USB Device Class drivers +# +# CONFIG_USB_ACM is not set +# CONFIG_USB_PRINTER is not set +# CONFIG_USB_WDM is not set +# CONFIG_USB_TMC is not set + +# +# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may +# + +# +# also be needed; see USB_STORAGE Help for more info +# +CONFIG_USB_STORAGE=y +# CONFIG_USB_STORAGE_DEBUG is not set +# CONFIG_USB_STORAGE_REALTEK is not set +# CONFIG_USB_STORAGE_DATAFAB is not set +# CONFIG_USB_STORAGE_FREECOM is not set +# CONFIG_USB_STORAGE_ISD200 is not set +# CONFIG_USB_STORAGE_USBAT is not set +# CONFIG_USB_STORAGE_SDDR09 is not set +# CONFIG_USB_STORAGE_SDDR55 is not set +# CONFIG_USB_STORAGE_JUMPSHOT is not set +# CONFIG_USB_STORAGE_ALAUDA is not set +# CONFIG_USB_STORAGE_ONETOUCH is not set +# CONFIG_USB_STORAGE_KARMA is not set +# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set +# CONFIG_USB_STORAGE_ENE_UB6250 is not set +CONFIG_USB_UAS=y + +# +# USB Imaging devices +# +# CONFIG_USB_MDC800 is not set +# CONFIG_USB_MICROTEK is not set +# CONFIG_USBIP_CORE is not set +# CONFIG_USB_MUSB_HDRC is not set +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_HOST=y + +# +# Platform Glue Driver Support +# +CONFIG_USB_DWC3_PCI=y +CONFIG_USB_DWC3_QCOM=y +# CONFIG_USB_DWC2 is not set +# CONFIG_USB_ISP1760 is not set + +# +# USB Power Delivery +# +# CONFIG_USB_PD is not set +CONFIG_QPNP_USB_PDPHY=y + +# +# USB port drivers +# +# CONFIG_USB_SERIAL is not set + +# +# USB Miscellaneous drivers +# +# CONFIG_USB_EMI62 is not set +# CONFIG_USB_EMI26 is not set +# CONFIG_USB_ADUTUX is not set +# CONFIG_USB_SEVSEG is not set +# CONFIG_USB_RIO500 is not set +# CONFIG_USB_LEGOTOWER is not set +# CONFIG_USB_LCD is not set +# CONFIG_USB_LED is not set +# CONFIG_USB_CYPRESS_CY7C63 is not set +# CONFIG_USB_CYTHERM is not set +# CONFIG_USB_IDMOUSE is not set +# CONFIG_USB_FTDI_ELAN is not set +# CONFIG_USB_APPLEDISPLAY is not set +# CONFIG_USB_LD is not set +# CONFIG_USB_TRANCEVIBRATOR is not set +# CONFIG_USB_IOWARRIOR is not set +# CONFIG_USB_TEST is not set +# CONFIG_USB_EHSET_TEST_FIXTURE is not set +# CONFIG_USB_ISIGHTFW is not set +# CONFIG_USB_YUREX is not set +# CONFIG_USB_EZUSB_FX2 is not set +# CONFIG_USB_HSIC_USB3503 is not set +# CONFIG_USB_LINK_LAYER_TEST is not set +# CONFIG_USB_CHAOSKEY is not set +# CONFIG_USB_QTI_KS_BRIDGE is not set + +# +# USB Physical Layer drivers +# +CONFIG_USB_PHY=y +CONFIG_USB_OTG_WAKELOCK=y +CONFIG_NOP_USB_XCEIV=y +# CONFIG_USB_GPIO_VBUS is not set +# CONFIG_USB_ISP1301 is not set +# CONFIG_USB_MSM_OTG is not set +# CONFIG_USB_QCOM_8X16_PHY is not set +# CONFIG_USB_MSM_HSPHY is not set +# CONFIG_USB_MSM_SSPHY is not set +CONFIG_USB_MSM_SSPHY_QMP=y +CONFIG_MSM_QUSB_PHY=y +# CONFIG_USB_ULPI is not set +# CONFIG_DUAL_ROLE_USB_INTF is not set +# CONFIG_USB_GADGET is not set +# CONFIG_USB_LED_TRIG is not set +# CONFIG_UWB is not set +CONFIG_MMC=y +# CONFIG_MMC_DEBUG is not set +CONFIG_MMC_PERF_PROFILING=y +# CONFIG_MMC_RING_BUFFER is not set +# CONFIG_MMC_EMBEDDED_SDIO is not set +# CONFIG_MMC_PARANOID_SD_INIT is not set +CONFIG_MMC_CLKGATE=y + +# +# MMC/SD/SDIO Card Drivers +# +CONFIG_MMC_BLOCK=y +CONFIG_MMC_BLOCK_MINORS=32 +CONFIG_MMC_BLOCK_BOUNCE=y +# CONFIG_MMC_BLOCK_DEFERRED_RESUME is not set +# CONFIG_SDIO_UART is not set +# CONFIG_MMC_TEST is not set +# CONFIG_MMC_SIMULATE_MAX_SPEED is not set + +# +# MMC/SD/SDIO Host Controller Drivers +# +# CONFIG_MMC_ARMMMCI is not set +CONFIG_MMC_SDHCI=y +# CONFIG_MMC_SDHCI_PCI is not set +# CONFIG_MMC_SDHCI_ACPI is not set +CONFIG_MMC_SDHCI_PLTFM=y +# CONFIG_MMC_SDHCI_OF_ARASAN is not set +# CONFIG_MMC_SDHCI_OF_AT91 is not set +# CONFIG_MMC_SDHCI_F_SDH30 is not set +CONFIG_MMC_SDHCI_MSM=y +# CONFIG_MMC_TIFM_SD is not set +# CONFIG_MMC_SPI is not set +# CONFIG_MMC_CB710 is not set +# CONFIG_MMC_VIA_SDMMC is not set +# CONFIG_MMC_DW is not set +# CONFIG_MMC_VUB300 is not set +# CONFIG_MMC_USHC is not set +# CONFIG_MMC_USDHI6ROL0 is not set +# CONFIG_MMC_CQ_HCI is not set +# CONFIG_MMC_TOSHIBA_PCI is not set +# CONFIG_MMC_MTK is not set +# CONFIG_MEMSTICK is not set +CONFIG_NEW_LEDS=y +CONFIG_LEDS_CLASS=y +# CONFIG_LEDS_CLASS_FLASH is not set + +# +# LED drivers +# +# CONFIG_LEDS_BCM6328 is not set +# CONFIG_LEDS_BCM6358 is not set +# CONFIG_LEDS_LM3530 is not set +# CONFIG_LEDS_LM3642 is not set +# CONFIG_LEDS_PCA9532 is not set +# CONFIG_LEDS_GPIO is not set +# CONFIG_LEDS_LP3944 is not set +# CONFIG_LEDS_LP5521 is not set +# CONFIG_LEDS_LP5523 is not set +# CONFIG_LEDS_LP5562 is not set +# CONFIG_LEDS_LP8501 is not set +# CONFIG_LEDS_LP8860 is not set +# CONFIG_LEDS_PCA955X is not set +# CONFIG_LEDS_PCA963X is not set +# CONFIG_LEDS_DAC124S085 is not set +# CONFIG_LEDS_PWM is not set +# CONFIG_LEDS_REGULATOR is not set +# CONFIG_LEDS_BD2802 is not set +# CONFIG_LEDS_LT3593 is not set +# CONFIG_LEDS_TCA6507 is not set +# CONFIG_LEDS_TLC591XX is not set +# CONFIG_LEDS_LM355x is not set + +# +# LED driver for blink(1) USB RGB LED is under Special HID drivers (HID_THINGM) +# +# CONFIG_LEDS_BLINKM is not set +CONFIG_LEDS_QPNP=y +# CONFIG_LEDS_QPNP_FLASH is not set +CONFIG_LEDS_QPNP_FLASH_V2=y +CONFIG_LEDS_QPNP_WLED=y +CONFIG_LEDS_SYSCON=y + +# +# LED Triggers +# +CONFIG_LEDS_TRIGGERS=y +# CONFIG_LEDS_TRIGGER_TIMER is not set +# CONFIG_LEDS_TRIGGER_ONESHOT is not set +# CONFIG_LEDS_TRIGGER_HEARTBEAT is not set +# CONFIG_LEDS_TRIGGER_BACKLIGHT is not set +# CONFIG_LEDS_TRIGGER_CPU is not set +# CONFIG_LEDS_TRIGGER_GPIO is not set +# CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set + +# +# iptables trigger is under Netfilter config (LED target) +# +# CONFIG_LEDS_TRIGGER_TRANSIENT is not set +# CONFIG_LEDS_TRIGGER_CAMERA is not set +CONFIG_SWITCH=y +# CONFIG_SWITCH_GPIO is not set +# CONFIG_ACCESSIBILITY is not set +# CONFIG_INFINIBAND is not set +CONFIG_EDAC_SUPPORT=y +CONFIG_EDAC=y +# CONFIG_EDAC_LEGACY_SYSFS is not set +# CONFIG_EDAC_DEBUG is not set +CONFIG_EDAC_MM_EDAC=y +# CONFIG_EDAC_XGENE is not set +CONFIG_EDAC_CORTEX_ARM64=y +# CONFIG_EDAC_CORTEX_ARM64_PANIC_ON_CE is not set +# CONFIG_EDAC_CORTEX_ARM64_DBE_IRQ_ONLY is not set +CONFIG_EDAC_CORTEX_ARM64_PANIC_ON_UE=y +CONFIG_RTC_LIB=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_HCTOSYS=y +CONFIG_RTC_HCTOSYS_DEVICE="rtc0" +CONFIG_RTC_SYSTOHC=y +CONFIG_RTC_SYSTOHC_DEVICE="rtc0" +# CONFIG_RTC_DEBUG is not set + +# +# RTC interfaces +# +CONFIG_RTC_INTF_SYSFS=y +CONFIG_RTC_INTF_PROC=y +CONFIG_RTC_INTF_DEV=y +# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set +# CONFIG_RTC_DRV_TEST is not set + +# +# I2C RTC drivers +# +# CONFIG_RTC_DRV_ABB5ZES3 is not set +# CONFIG_RTC_DRV_ABX80X is not set +# CONFIG_RTC_DRV_DS1307 is not set +# CONFIG_RTC_DRV_DS1374 is not set +# CONFIG_RTC_DRV_DS1672 is not set +# CONFIG_RTC_DRV_DS3232 is not set +# CONFIG_RTC_DRV_HYM8563 is not set +# CONFIG_RTC_DRV_MAX6900 is not set +# CONFIG_RTC_DRV_RS5C372 is not set +# CONFIG_RTC_DRV_ISL1208 is not set +# CONFIG_RTC_DRV_ISL12022 is not set +# CONFIG_RTC_DRV_ISL12057 is not set +# CONFIG_RTC_DRV_X1205 is not set +# CONFIG_RTC_DRV_PCF2127 is not set +# CONFIG_RTC_DRV_PCF8523 is not set +# CONFIG_RTC_DRV_PCF8563 is not set +# CONFIG_RTC_DRV_PCF85063 is not set +# CONFIG_RTC_DRV_PCF8583 is not set +# CONFIG_RTC_DRV_M41T80 is not set +# CONFIG_RTC_DRV_BQ32K is not set +# CONFIG_RTC_DRV_S35390A is not set +# CONFIG_RTC_DRV_FM3130 is not set +# CONFIG_RTC_DRV_RX8581 is not set +# CONFIG_RTC_DRV_RX8025 is not set +# CONFIG_RTC_DRV_EM3027 is not set +# CONFIG_RTC_DRV_RV3029C2 is not set +# CONFIG_RTC_DRV_RV8803 is not set + +# +# SPI RTC drivers +# +# CONFIG_RTC_DRV_M41T93 is not set +# CONFIG_RTC_DRV_M41T94 is not set +# CONFIG_RTC_DRV_DS1305 is not set +# CONFIG_RTC_DRV_DS1343 is not set +# CONFIG_RTC_DRV_DS1347 is not set +# CONFIG_RTC_DRV_DS1390 is not set +# CONFIG_RTC_DRV_MAX6902 is not set +# CONFIG_RTC_DRV_R9701 is not set +# CONFIG_RTC_DRV_RS5C348 is not set +# CONFIG_RTC_DRV_DS3234 is not set +# CONFIG_RTC_DRV_PCF2123 is not set +# CONFIG_RTC_DRV_RX4581 is not set +# CONFIG_RTC_DRV_MCP795 is not set + +# +# Platform RTC drivers +# +# CONFIG_RTC_DRV_DS1286 is not set +# CONFIG_RTC_DRV_DS1511 is not set +# CONFIG_RTC_DRV_DS1553 is not set +# CONFIG_RTC_DRV_DS1685_FAMILY is not set +# CONFIG_RTC_DRV_DS1742 is not set +# CONFIG_RTC_DRV_DS2404 is not set +# CONFIG_RTC_DRV_STK17TA8 is not set +# CONFIG_RTC_DRV_M48T86 is not set +# CONFIG_RTC_DRV_M48T35 is not set +# CONFIG_RTC_DRV_M48T59 is not set +# CONFIG_RTC_DRV_MSM6242 is not set +# CONFIG_RTC_DRV_BQ4802 is not set +# CONFIG_RTC_DRV_RP5C01 is not set +# CONFIG_RTC_DRV_V3020 is not set +# CONFIG_RTC_DRV_ZYNQMP is not set + +# +# on-CPU RTC drivers +# +# CONFIG_RTC_DRV_PL030 is not set +# CONFIG_RTC_DRV_PL031 is not set +# CONFIG_RTC_DRV_PM8XXX is not set +# CONFIG_RTC_DRV_SNVS is not set +CONFIG_RTC_DRV_QPNP=y + +# +# HID Sensor RTC drivers +# +# CONFIG_RTC_DRV_HID_SENSOR_TIME is not set +# CONFIG_ESOC is not set +CONFIG_DMADEVICES=y +# CONFIG_DMADEVICES_DEBUG is not set + +# +# DMA Devices +# +CONFIG_DMA_ENGINE=y +CONFIG_DMA_ACPI=y +CONFIG_DMA_OF=y +# CONFIG_AMBA_PL08X is not set +# CONFIG_FSL_EDMA is not set +# CONFIG_INTEL_IDMA64 is not set +# CONFIG_PL330_DMA is not set +# CONFIG_QCOM_BAM_DMA is not set +CONFIG_QCOM_SPS_DMA=y +# CONFIG_DW_DMAC is not set +# CONFIG_DW_DMAC_PCI is not set + +# +# DMA Clients +# +# CONFIG_ASYNC_TX_DMA is not set +# CONFIG_DMATEST is not set +# CONFIG_AUXDISPLAY is not set +CONFIG_UIO=y +# CONFIG_UIO_CIF is not set +# CONFIG_UIO_PDRV_GENIRQ is not set +# CONFIG_UIO_DMEM_GENIRQ is not set +# CONFIG_UIO_AEC is not set +# CONFIG_UIO_SERCOS3 is not set +# CONFIG_UIO_PCI_GENERIC is not set +# CONFIG_UIO_NETX is not set +# CONFIG_UIO_PRUSS is not set +# CONFIG_UIO_MF624 is not set +CONFIG_UIO_MSM_SHAREDMEM=y +# CONFIG_VFIO is not set +# CONFIG_VIRT_DRIVERS is not set + +# +# Virtio drivers +# +# CONFIG_VIRTIO_PCI is not set +# CONFIG_VIRTIO_MMIO is not set + +# +# Microsoft Hyper-V guest support +# +CONFIG_STAGING=y +# CONFIG_PRISM2_USB is not set +# CONFIG_COMEDI is not set +# CONFIG_RTL8192U is not set +# CONFIG_RTLLIB is not set +# CONFIG_R8712U is not set +# CONFIG_R8188EU is not set +# CONFIG_R8723AU is not set +# CONFIG_RTS5208 is not set +# CONFIG_VT6655 is not set +# CONFIG_VT6656 is not set + +# +# IIO staging drivers +# + +# +# Accelerometers +# +# CONFIG_ADIS16201 is not set +# CONFIG_ADIS16203 is not set +# CONFIG_ADIS16204 is not set +# CONFIG_ADIS16209 is not set +# CONFIG_ADIS16220 is not set +# CONFIG_ADIS16240 is not set +# CONFIG_LIS3L02DQ is not set + +# +# Analog to digital converters +# +# CONFIG_AD7606 is not set +# CONFIG_AD7780 is not set +# CONFIG_AD7816 is not set +# CONFIG_AD7192 is not set +# CONFIG_AD7280 is not set + +# +# Analog digital bi-direction converters +# +# CONFIG_ADT7316 is not set + +# +# Capacitance to digital converters +# +# CONFIG_AD7150 is not set +# CONFIG_AD7152 is not set +# CONFIG_AD7746 is not set + +# +# Direct Digital Synthesis +# +# CONFIG_AD9832 is not set +# CONFIG_AD9834 is not set + +# +# Digital gyroscope sensors +# +# CONFIG_ADIS16060 is not set + +# +# Network Analyzer, Impedance Converters +# +# CONFIG_AD5933 is not set + +# +# Light sensors +# +# CONFIG_SENSORS_ISL29018 is not set +# CONFIG_SENSORS_ISL29028 is not set +# CONFIG_TSL2583 is not set +# CONFIG_TSL2x7x is not set + +# +# Magnetometer sensors +# +# CONFIG_SENSORS_HMC5843_I2C is not set +# CONFIG_SENSORS_HMC5843_SPI is not set + +# +# Active energy metering IC +# +# CONFIG_ADE7753 is not set +# CONFIG_ADE7754 is not set +# CONFIG_ADE7758 is not set +# CONFIG_ADE7759 is not set +# CONFIG_ADE7854 is not set + +# +# Resolver to digital converters +# +# CONFIG_AD2S90 is not set +# CONFIG_AD2S1200 is not set +# CONFIG_AD2S1210 is not set + +# +# Triggers - standalone +# +# CONFIG_IIO_SIMPLE_DUMMY is not set +# CONFIG_FB_SM750 is not set +# CONFIG_FB_XGI is not set + +# +# Speakup console speech +# +# CONFIG_SPEAKUP is not set +# CONFIG_TOUCHSCREEN_SYNAPTICS_I2C_RMI4 is not set +# CONFIG_STAGING_MEDIA is not set + +# +# Android +# +CONFIG_ASHMEM=y +CONFIG_ANDROID_TIMED_OUTPUT=y +CONFIG_ANDROID_TIMED_GPIO=y +CONFIG_ANDROID_LOW_MEMORY_KILLER=y +CONFIG_ANDROID_LOW_MEMORY_KILLER_AUTODETECT_OOM_ADJ_VALUES=y +CONFIG_SYNC=y +CONFIG_SW_SYNC=y +# CONFIG_SW_SYNC_USER is not set +# CONFIG_ONESHOT_SYNC is not set +# CONFIG_ONESHOT_SYNC_USER is not set +CONFIG_ION=y +# CONFIG_ION_TEST is not set +# CONFIG_ION_DUMMY is not set +CONFIG_ION_MSM=y +# CONFIG_ALLOC_BUFFERS_IN_4K_CHUNKS is not set +# CONFIG_FIQ_DEBUGGER is not set +# CONFIG_FIQ_WATCHDOG is not set +# CONFIG_STAGING_BOARD is not set +# CONFIG_WIMAX_GDM72XX is not set +# CONFIG_LTE_GDM724X is not set +# CONFIG_LUSTRE_FS is not set +# CONFIG_DGNC is not set +# CONFIG_DGAP is not set +# CONFIG_GS_FPGABOOT is not set +# CONFIG_FB_TFT is not set +# CONFIG_FSL_MC_BUS is not set +# CONFIG_WILC1000_DRIVER is not set +# CONFIG_MOST is not set +# CONFIG_GOLDFISH is not set +# CONFIG_CHROME_PLATFORMS is not set + +# +# Qualcomm MSM specific device drivers +# +CONFIG_QPNP_REVID=y +CONFIG_QPNP_COINCELL=y +CONFIG_SPS=y +# CONFIG_SPS_SUPPORT_BAMDMA is not set +CONFIG_SPS_SUPPORT_NDP_BAM=y +# CONFIG_EP_PCIE is not set +# CONFIG_IPA is not set +# CONFIG_GSI is not set +CONFIG_GPIO_USB_DETECT=y +# CONFIG_MSM_MHI is not set +# CONFIG_MSM_11AD is not set +CONFIG_SEEMP_CORE=y +CONFIG_MSM_EXT_DISPLAY=y +CONFIG_CLKDEV_LOOKUP=y +CONFIG_HAVE_CLK_PREPARE=y +CONFIG_COMMON_CLK_MSM=y +# CONFIG_MSM_CLK_CONTROLLER_V2 is not set +CONFIG_MSM_MDSS_PLL=y +CONFIG_HWSPINLOCK=y + +# +# Hardware Spinlock drivers +# +# CONFIG_HWSPINLOCK_QCOM is not set +CONFIG_REMOTE_SPINLOCK_MSM=y + +# +# Clock Source drivers +# +CONFIG_CLKSRC_OF=y +CONFIG_CLKSRC_ACPI=y +CONFIG_CLKSRC_PROBE=y +CONFIG_ARM_ARCH_TIMER=y +CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y +CONFIG_MSM_TIMER_LEAP=y +# CONFIG_ARM_ARCH_TIMER_VCT_ACCESS is not set +# CONFIG_ARM_TIMER_SP804 is not set +# CONFIG_ATMEL_PIT is not set +# CONFIG_SH_TIMER_CMT is not set +# CONFIG_SH_TIMER_MTU2 is not set +# CONFIG_SH_TIMER_TMU is not set +# CONFIG_EM_TIMER_STI is not set +# CONFIG_MAILBOX is not set +CONFIG_IOMMU_API=y +CONFIG_IOMMU_SUPPORT=y + +# +# Generic IOMMU Pagetable Support +# +CONFIG_IOMMU_IO_PGTABLE=y +CONFIG_IOMMU_IO_PGTABLE_LPAE=y +# CONFIG_IOMMU_IO_PGTABLE_LPAE_SELFTEST is not set +CONFIG_IOMMU_IO_PGTABLE_FAST=y +# CONFIG_IOMMU_IO_PGTABLE_FAST_SELFTEST is not set +# CONFIG_IOMMU_IO_PGTABLE_FAST_PROVE_TLB is not set +CONFIG_OF_IOMMU=y +CONFIG_ARM_SMMU=y +# CONFIG_ARM_SMMU_V3 is not set +CONFIG_IOMMU_DEBUG=y +CONFIG_IOMMU_DEBUG_TRACKING=y +# CONFIG_IOMMU_TESTS is not set + +# +# Remoteproc drivers +# +# CONFIG_STE_MODEM_RPROC is not set + +# +# Rpmsg drivers +# + +# +# SOC (System On Chip) specific Drivers +# +# CONFIG_MSM_HAB is not set +# CONFIG_MSM_INRUSH_CURRENT_MITIGATION is not set +# CONFIG_MSM_PFE_WA is not set +# CONFIG_QCOM_COMMON_LOG is not set +CONFIG_MSM_SMEM=y +CONFIG_QPNP_HAPTIC=y +# CONFIG_QPNP_PBS is not set +CONFIG_MSM_SMD=y +# CONFIG_MSM_SMD_DEBUG is not set +CONFIG_MSM_GLINK=y +CONFIG_MSM_GLINK_LOOPBACK_SERVER=y +CONFIG_MSM_GLINK_SMD_XPRT=y +CONFIG_MSM_GLINK_SMEM_NATIVE_XPRT=y +CONFIG_MSM_GLINK_SPI_XPRT=y +CONFIG_MSM_SPCOM=y +CONFIG_MSM_SPSS_UTILS=y +CONFIG_MSM_SMEM_LOGGING=y +CONFIG_MSM_SMP2P=y +CONFIG_MSM_SMP2P_TEST=y +CONFIG_MSM_QMI_INTERFACE=y +# CONFIG_MSM_L2_IA_DEBUG is not set +CONFIG_MSM_RPM_SMD=y +CONFIG_QCOM_BUS_SCALING=y +# CONFIG_QCOM_GSBI is not set +# CONFIG_QCOM_SMEM is not set +CONFIG_MSM_SERVICE_LOCATOR=y +# CONFIG_MSM_HVC is not set +CONFIG_QCOM_DCC=y +CONFIG_MSM_IPC_ROUTER_SMD_XPRT=y +CONFIG_MSM_SYSMON_GLINK_COMM=y +CONFIG_MSM_IPC_ROUTER_GLINK_XPRT=y +# CONFIG_MSM_SYSTEM_HEALTH_MONITOR is not set +CONFIG_MSM_GLINK_PKT=y +CONFIG_MSM_SPM=y +# CONFIG_MSM_L2_SPM is not set +CONFIG_QCOM_SCM=y +# CONFIG_QCOM_SCM_QCPE is not set +# CONFIG_QCOM_SCM_XPU is not set +# CONFIG_QCOM_SCM_ERRATA is not set +CONFIG_QCOM_WATCHDOG_V2=y +CONFIG_QCOM_IRQ_HELPER=y +# CONFIG_QCOM_MEMORY_DUMP is not set +# CONFIG_QCOM_MEMORY_DUMP_V2 is not set +CONFIG_ICNSS=y +# CONFIG_ICNSS_DEBUG is not set +CONFIG_MSM_SECURE_BUFFER=y +# CONFIG_MSM_GLADIATOR_ERP is not set +CONFIG_MSM_GLADIATOR_ERP_V2=y +CONFIG_PANIC_ON_GLADIATOR_ERROR_V2=y +# CONFIG_MSM_GLADIATOR_ERROR_V2_MAIN_LOGGER_ONLY is not set +CONFIG_MSM_GLADIATOR_HANG_DETECT=y +CONFIG_MSM_CORE_HANG_DETECT=y +CONFIG_MSM_RUN_QUEUE_STATS=y +CONFIG_MSM_JTAGV8=y +CONFIG_MSM_BOOT_STATS=y +# CONFIG_MSM_BOOT_TIME_MARKER is not set +# CONFIG_QCOM_CPUSS_DUMP is not set +# CONFIG_MSM_QDSP6_APRV2 is not set +# CONFIG_MSM_QDSP6_APRV3 is not set +CONFIG_MSM_QDSP6_APRV2_GLINK=y +# CONFIG_MSM_QDSP6_APRV3_GLINK is not set +CONFIG_MSM_QDSP6_SSR=y +CONFIG_MSM_QDSP6_PDR=y +CONFIG_MSM_QDSP6_NOTIFIER=y +CONFIG_MSM_ADSP_LOADER=y +# CONFIG_MSM_CDSP_LOADER is not set +CONFIG_MSM_PERFORMANCE=y +# CONFIG_MSM_PERFORMANCE_HOTPLUG_ON is not set +CONFIG_MSM_SUBSYSTEM_RESTART=y +# CONFIG_MSM_SYSMON_COMM is not set +CONFIG_MSM_PIL=y +CONFIG_MSM_PIL_SSR_GENERIC=y +CONFIG_MSM_PIL_MSS_QDSP6V5=y +CONFIG_TRACER_PKT=y +# CONFIG_QCOM_FORCE_WDOG_BITE_ON_PANIC is not set +CONFIG_MSM_MPM_OF=y +CONFIG_MSM_EVENT_TIMER=y +CONFIG_MSM_AVTIMER=y +# CONFIG_MSM_KERNEL_PROTECT is not set +CONFIG_QCOM_REMOTEQDSS=y +CONFIG_MSM_SERVICE_NOTIFIER=y +# CONFIG_MSM_QBT1000 is not set +CONFIG_MSM_RPM_RBCPR_STATS_V2_LOG=y +CONFIG_MSM_RPM_LOG=y +CONFIG_MSM_RPM_STATS_LOG=y +CONFIG_QSEE_IPC_IRQ_BRIDGE=y +CONFIG_WCD_DSP_GLINK=y +CONFIG_QCOM_SMCINVOKE=y +CONFIG_QCOM_EARLY_RANDOM=y +# CONFIG_QCOM_CX_IPEAK is not set +# CONFIG_MSM_CACHE_M4M_ERP64_PANIC_ON_CE is not set +# CONFIG_MSM_CACHE_M4M_ERP64_PANIC_ON_UE is not set +CONFIG_MEM_SHARE_QMI_SERVICE=y +# CONFIG_SUNXI_SRAM is not set +# CONFIG_SOC_TI is not set +CONFIG_PM_DEVFREQ=y + +# +# DEVFREQ Governors +# +CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y +CONFIG_DEVFREQ_GOV_PERFORMANCE=y +CONFIG_DEVFREQ_GOV_POWERSAVE=y +CONFIG_DEVFREQ_GOV_USERSPACE=y +CONFIG_DEVFREQ_GOV_CPUFREQ=y +CONFIG_QCOM_BIMC_BWMON=y +# CONFIG_ARMBW_HWMON is not set +CONFIG_ARM_MEMLAT_MON=y +# CONFIG_QCOMCCI_HWMON is not set +# CONFIG_QCOM_M4M_HWMON is not set +CONFIG_DEVFREQ_GOV_QCOM_BW_HWMON=y +# CONFIG_DEVFREQ_GOV_QCOM_CACHE_HWMON is not set +CONFIG_DEVFREQ_GOV_SPDM_HYP=y +CONFIG_DEVFREQ_GOV_MEMLAT=y + +# +# DEVFREQ Drivers +# +# CONFIG_DEVFREQ_SIMPLE_DEV is not set +CONFIG_QCOM_DEVFREQ_DEVBW=y +CONFIG_SPDM_SCM=y +CONFIG_DEVFREQ_SPDM=y +# CONFIG_PM_DEVFREQ_EVENT is not set +CONFIG_EXTCON=y + +# +# Extcon Device Drivers +# +# CONFIG_EXTCON_ADC_JACK is not set +# CONFIG_EXTCON_GPIO is not set +# CONFIG_EXTCON_RT8973A is not set +# CONFIG_EXTCON_SM5502 is not set +# CONFIG_EXTCON_USB_GPIO is not set +# CONFIG_MEMORY is not set +CONFIG_IIO=y +# CONFIG_IIO_BUFFER is not set +# CONFIG_IIO_TRIGGER is not set + +# +# Accelerometers +# +# CONFIG_BMA180 is not set +# CONFIG_BMC150_ACCEL is not set +# CONFIG_IIO_ST_ACCEL_3AXIS is not set +# CONFIG_KXSD9 is not set +# CONFIG_KXCJK1013 is not set +# CONFIG_MMA8452 is not set +# CONFIG_MMA9551 is not set +# CONFIG_MMA9553 is not set +# CONFIG_MXC4005 is not set +# CONFIG_STK8312 is not set + +# +# Analog to digital converters +# +# CONFIG_AD7266 is not set +# CONFIG_AD7291 is not set +# CONFIG_AD7298 is not set +# CONFIG_AD7476 is not set +# CONFIG_AD7791 is not set +# CONFIG_AD7793 is not set +# CONFIG_AD7887 is not set +# CONFIG_AD7923 is not set +# CONFIG_AD799X is not set +# CONFIG_CC10001_ADC is not set +# CONFIG_HI8435 is not set +# CONFIG_MAX1027 is not set +# CONFIG_MAX1363 is not set +# CONFIG_MCP320X is not set +# CONFIG_MCP3422 is not set +# CONFIG_NAU7802 is not set +# CONFIG_QCOM_SPMI_IADC is not set +# CONFIG_QCOM_SPMI_VADC is not set +CONFIG_QCOM_RRADC=y +CONFIG_QCOM_TADC=y +# CONFIG_TI_ADC081C is not set +# CONFIG_TI_ADC128S052 is not set +# CONFIG_VF610_ADC is not set + +# +# Amplifiers +# +# CONFIG_AD8366 is not set + +# +# Chemical Sensors +# +# CONFIG_VZ89X is not set + +# +# Hid Sensor IIO Common +# + +# +# SSP Sensor Common +# +# CONFIG_IIO_SSP_SENSORHUB is not set + +# +# Digital to analog converters +# +# CONFIG_AD5064 is not set +# CONFIG_AD5360 is not set +# CONFIG_AD5380 is not set +# CONFIG_AD5421 is not set +# CONFIG_AD5446 is not set +# CONFIG_AD5449 is not set +# CONFIG_AD5504 is not set +# CONFIG_AD5624R_SPI is not set +# CONFIG_AD5686 is not set +# CONFIG_AD5755 is not set +# CONFIG_AD5764 is not set +# CONFIG_AD5791 is not set +# CONFIG_AD7303 is not set +# CONFIG_M62332 is not set +# CONFIG_MAX517 is not set +# CONFIG_MAX5821 is not set +# CONFIG_MCP4725 is not set +# CONFIG_MCP4922 is not set + +# +# Frequency Synthesizers DDS/PLL +# + +# +# Clock Generator/Distribution +# +# CONFIG_AD9523 is not set + +# +# Phase-Locked Loop (PLL) frequency synthesizers +# +# CONFIG_ADF4350 is not set + +# +# Digital gyroscope sensors +# +# CONFIG_ADIS16080 is not set +# CONFIG_ADIS16130 is not set +# CONFIG_ADIS16136 is not set +# CONFIG_ADIS16260 is not set +# CONFIG_ADXRS450 is not set +# CONFIG_BMG160 is not set +# CONFIG_IIO_ST_GYRO_3AXIS is not set +# CONFIG_ITG3200 is not set + +# +# Humidity sensors +# +# CONFIG_DHT11 is not set +# CONFIG_HDC100X is not set +# CONFIG_HTU21 is not set +# CONFIG_SI7005 is not set +# CONFIG_SI7020 is not set + +# +# Inertial measurement units +# +# CONFIG_ADIS16400 is not set +# CONFIG_ADIS16480 is not set +# CONFIG_KMX61 is not set +# CONFIG_INV_MPU6050_IIO is not set + +# +# Light sensors +# +# CONFIG_ACPI_ALS is not set +# CONFIG_ADJD_S311 is not set +# CONFIG_AL3320A is not set +# CONFIG_APDS9300 is not set +# CONFIG_APDS9960 is not set +# CONFIG_BH1750 is not set +# CONFIG_CM32181 is not set +# CONFIG_CM3232 is not set +# CONFIG_CM3323 is not set +# CONFIG_CM36651 is not set +# CONFIG_GP2AP020A00F is not set +# CONFIG_ISL29125 is not set +# CONFIG_JSA1212 is not set +# CONFIG_RPR0521 is not set +# CONFIG_LTR501 is not set +# CONFIG_OPT3001 is not set +# CONFIG_PA12203001 is not set +# CONFIG_STK3310 is not set +# CONFIG_TCS3414 is not set +# CONFIG_TCS3472 is not set +# CONFIG_SENSORS_TSL2563 is not set +# CONFIG_TSL4531 is not set +# CONFIG_US5182D is not set +# CONFIG_VCNL4000 is not set + +# +# Magnetometer sensors +# +# CONFIG_AK8975 is not set +# CONFIG_AK09911 is not set +# CONFIG_BMC150_MAGN is not set +# CONFIG_MAG3110 is not set +# CONFIG_MMC35240 is not set +# CONFIG_IIO_ST_MAGN_3AXIS is not set + +# +# Inclinometer sensors +# + +# +# Digital potentiometers +# +# CONFIG_MCP4531 is not set + +# +# Pressure sensors +# +# CONFIG_BMP280 is not set +# CONFIG_MPL115 is not set +# CONFIG_MPL3115 is not set +# CONFIG_MS5611 is not set +# CONFIG_MS5637 is not set +# CONFIG_IIO_ST_PRESS is not set +# CONFIG_T5403 is not set + +# +# Lightning sensors +# +# CONFIG_AS3935 is not set + +# +# Proximity sensors +# +# CONFIG_LIDAR_LITE_V2 is not set +# CONFIG_SX9500 is not set + +# +# Temperature sensors +# +# CONFIG_MLX90614 is not set +# CONFIG_TMP006 is not set +# CONFIG_TSYS01 is not set +# CONFIG_TSYS02D is not set +# CONFIG_NTB is not set +# CONFIG_VME_BUS is not set +CONFIG_PWM=y +CONFIG_PWM_SYSFS=y +# CONFIG_PWM_FSL_FTM is not set +# CONFIG_PWM_PCA9685 is not set +CONFIG_PWM_QPNP=y +CONFIG_IRQCHIP=y +CONFIG_ARM_GIC=y +CONFIG_ARM_GIC_V2M=y +CONFIG_ARM_GIC_V3=y +CONFIG_ARM_GIC_V3_ITS=y +CONFIG_ARM_GIC_V3_ACL=y +# CONFIG_ARM_GIC_V3_NO_ACCESS_CONTROL is not set +CONFIG_QCOM_SHOW_RESUME_IRQ=y +CONFIG_MSM_IRQ=y +# CONFIG_IPACK_BUS is not set +CONFIG_ARCH_HAS_RESET_CONTROLLER=y +CONFIG_RESET_CONTROLLER=y +# CONFIG_FMC is not set + +# +# PHY Subsystem +# +CONFIG_GENERIC_PHY=y +# CONFIG_PHY_PXA_28NM_HSIC is not set +# CONFIG_PHY_PXA_28NM_USB2 is not set +# CONFIG_BCM_KONA_USB2_PHY is not set +# CONFIG_PHY_QCOM_APQ8064_SATA is not set +# CONFIG_PHY_QCOM_IPQ806X_SATA is not set +# CONFIG_PHY_XGENE is not set +CONFIG_PHY_QCOM_UFS=y +# CONFIG_POWERCAP is not set +# CONFIG_MCB is not set + +# +# Performance monitor support +# +CONFIG_ARM_PMU=y +CONFIG_RAS=y +# CONFIG_THUNDERBOLT is not set + +# +# Android +# +CONFIG_ANDROID=y +# CONFIG_ANDROID_BINDER_IPC is not set +# CONFIG_LIBNVDIMM is not set +# CONFIG_NVMEM is not set +# CONFIG_STM is not set +# CONFIG_INTEL_TH is not set + +# +# FPGA Configuration Support +# +# CONFIG_FPGA is not set + +# +# Firmware Drivers +# +CONFIG_ARM_PSCI_FW=y +# CONFIG_FIRMWARE_MEMMAP is not set +CONFIG_QCOM_SCM_64=y +CONFIG_HAVE_ARM_SMCCC=y +CONFIG_MSM_TZ_LOG=y +# CONFIG_BIF is not set +CONFIG_SENSORS_SSC=y +# CONFIG_TEE is not set + +# +# Firmware Drivers +# +CONFIG_ACPI=y +CONFIG_ACPI_GENERIC_GSI=y +CONFIG_ACPI_CCA_REQUIRED=y +# CONFIG_ACPI_DEBUGGER is not set +# CONFIG_ACPI_EC_DEBUGFS is not set +CONFIG_ACPI_BUTTON=y +CONFIG_ACPI_FAN=y +# CONFIG_ACPI_DOCK is not set +CONFIG_ACPI_PROCESSOR=y +CONFIG_ACPI_HOTPLUG_CPU=y +CONFIG_ACPI_THERMAL=y +# CONFIG_ACPI_CUSTOM_DSDT is not set +# CONFIG_ACPI_DEBUG is not set +# CONFIG_ACPI_PCI_SLOT is not set +CONFIG_ACPI_CONTAINER=y +# CONFIG_ACPI_HED is not set +# CONFIG_ACPI_CUSTOM_METHOD is not set +CONFIG_ACPI_REDUCED_HARDWARE_ONLY=y +# CONFIG_PMIC_OPREGION is not set + +# +# File systems +# +CONFIG_DCACHE_WORD_ACCESS=y +# CONFIG_EXT2_FS is not set +# CONFIG_EXT3_FS is not set +CONFIG_EXT4_FS=y +CONFIG_EXT4_USE_FOR_EXT2=y +# CONFIG_EXT4_FS_POSIX_ACL is not set +# CONFIG_EXT4_FS_SECURITY is not set +# CONFIG_EXT4_ENCRYPTION is not set +# CONFIG_EXT4_DEBUG is not set +CONFIG_JBD2=y +# CONFIG_JBD2_DEBUG is not set +CONFIG_FS_MBCACHE=y +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +CONFIG_XFS_FS=y +# CONFIG_XFS_QUOTA is not set +# CONFIG_XFS_POSIX_ACL is not set +# CONFIG_XFS_RT is not set +# CONFIG_XFS_WARN is not set +# CONFIG_XFS_DEBUG is not set +# CONFIG_GFS2_FS is not set +# CONFIG_OCFS2_FS is not set +# CONFIG_BTRFS_FS is not set +# CONFIG_NILFS2_FS is not set +# CONFIG_F2FS_FS is not set +# CONFIG_FS_DAX is not set +# CONFIG_FS_POSIX_ACL is not set +CONFIG_EXPORTFS=y +CONFIG_FILE_LOCKING=y +# CONFIG_FS_ENCRYPTION is not set +CONFIG_FSNOTIFY=y +CONFIG_DNOTIFY=y +CONFIG_INOTIFY_USER=y +CONFIG_FANOTIFY=y +# CONFIG_QUOTA is not set +# CONFIG_QUOTACTL is not set +# CONFIG_AUTOFS4_FS is not set +CONFIG_FUSE_FS=y +# CONFIG_CUSE is not set +# CONFIG_OVERLAY_FS is not set + +# +# Caches +# +# CONFIG_FSCACHE is not set + +# +# CD-ROM/DVD Filesystems +# +CONFIG_ISO9660_FS=y +CONFIG_JOLIET=y +CONFIG_ZISOFS=y +CONFIG_UDF_FS=y +CONFIG_UDF_NLS=y + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=y +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_FAT_DEFAULT_CODEPAGE=850 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +# CONFIG_NTFS_FS is not set +CONFIG_EXFAT_FS=y + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +# CONFIG_PROC_KCORE is not set +CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y +# CONFIG_PROC_CHILDREN is not set +CONFIG_KERNFS=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +# CONFIG_TMPFS_POSIX_ACL is not set +# CONFIG_TMPFS_XATTR is not set +# CONFIG_HUGETLBFS is not set +# CONFIG_HUGETLB_PAGE is not set +CONFIG_CONFIGFS_FS=y +CONFIG_MISC_FILESYSTEMS=y +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_ECRYPT_FS is not set +# CONFIG_SDCARD_FS is not set +CONFIG_HFS_FS=y +CONFIG_HFSPLUS_FS=y +# CONFIG_HFSPLUS_FS_POSIX_ACL is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +# CONFIG_LOGFS is not set +CONFIG_CRAMFS=y +CONFIG_SQUASHFS=y +# CONFIG_SQUASHFS_DECOMP_SINGLE is not set +# CONFIG_SQUASHFS_DECOMP_MULTI is not set +CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU=y +# CONFIG_SQUASHFS_XATTR is not set +# CONFIG_SQUASHFS_ZLIB is not set +# CONFIG_SQUASHFS_LZ4 is not set +# CONFIG_SQUASHFS_LZO is not set +CONFIG_SQUASHFS_XZ=y +# CONFIG_SQUASHFS_ZSTD is not set +# CONFIG_SQUASHFS_4K_DEVBLK_SIZE is not set +# CONFIG_SQUASHFS_EMBEDDED is not set +CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 +# CONFIG_VXFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_OMFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_QNX6FS_FS is not set +# CONFIG_ROMFS_FS is not set +CONFIG_PSTORE=y +# CONFIG_PSTORE_CONSOLE is not set +# CONFIG_PSTORE_PMSG is not set +CONFIG_PSTORE_RAM=y +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set +CONFIG_NETWORK_FILESYSTEMS=y +CONFIG_NFS_FS=y +CONFIG_NFS_V2=y +CONFIG_NFS_V3=y +# CONFIG_NFS_V3_ACL is not set +CONFIG_NFS_V4=y +# CONFIG_NFS_SWAP is not set +# CONFIG_NFS_V4_1 is not set +CONFIG_ROOT_NFS=y +# CONFIG_NFS_USE_LEGACY_DNS is not set +CONFIG_NFS_USE_KERNEL_DNS=y +# CONFIG_NFSD is not set +CONFIG_GRACE_PERIOD=y +CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=y +CONFIG_SUNRPC_GSS=y +# CONFIG_SUNRPC_DEBUG is not set +# CONFIG_CEPH_FS is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="iso8859-1" +# CONFIG_NLS_CODEPAGE_437 is not set +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +CONFIG_NLS_CODEPAGE_850=y +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +# CONFIG_NLS_CODEPAGE_932 is not set +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +# CONFIG_NLS_ASCII is not set +CONFIG_NLS_ISO8859_1=y +# CONFIG_NLS_ISO8859_2 is not set +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +# CONFIG_NLS_ISO8859_15 is not set +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +# CONFIG_NLS_MAC_ROMAN is not set +# CONFIG_NLS_MAC_CELTIC is not set +# CONFIG_NLS_MAC_CENTEURO is not set +# CONFIG_NLS_MAC_CROATIAN is not set +# CONFIG_NLS_MAC_CYRILLIC is not set +# CONFIG_NLS_MAC_GAELIC is not set +# CONFIG_NLS_MAC_GREEK is not set +# CONFIG_NLS_MAC_ICELAND is not set +# CONFIG_NLS_MAC_INUIT is not set +# CONFIG_NLS_MAC_ROMANIAN is not set +# CONFIG_NLS_MAC_TURKISH is not set +CONFIG_NLS_UTF8=y +# CONFIG_DLM is not set +# CONFIG_FILE_TABLE_DEBUG is not set +# CONFIG_VIRTUALIZATION is not set + +# +# Kernel hacking +# + +# +# printk and dmesg options +# +CONFIG_PRINTK_TIME=y +CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4 +# CONFIG_BOOT_PRINTK_DELAY is not set +CONFIG_DYNAMIC_DEBUG=y + +# +# Compile-time checks and compiler options +# +# CONFIG_DEBUG_INFO is not set +CONFIG_ENABLE_WARN_DEPRECATED=y +CONFIG_ENABLE_MUST_CHECK=y +CONFIG_FRAME_WARN=2048 +# CONFIG_STRIP_ASM_SYMS is not set +# CONFIG_READABLE_ASM is not set +# CONFIG_UNUSED_SYMBOLS is not set +CONFIG_PAGE_OWNER=y +CONFIG_PAGE_OWNER_ENABLE_DEFAULT=y +CONFIG_DEBUG_FS=y +# CONFIG_HEADERS_CHECK is not set +# CONFIG_DEBUG_SECTION_MISMATCH is not set +CONFIG_SECTION_MISMATCH_WARN_ONLY=y +CONFIG_ARCH_WANT_FRAME_POINTERS=y +CONFIG_FRAME_POINTER=y +# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set +CONFIG_MAGIC_SYSRQ=y +CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE=0x1 +CONFIG_DEBUG_KERNEL=y + +# +# Memory Debugging +# +CONFIG_PAGE_EXTENSION=y +# CONFIG_DEBUG_PAGEALLOC is not set +# CONFIG_SLUB_DEBUG_PANIC_ON is not set +# CONFIG_PAGE_POISONING is not set +# CONFIG_DEBUG_OBJECTS is not set +CONFIG_SLUB_DEBUG_ON=y +# CONFIG_SLUB_STATS is not set +CONFIG_HAVE_DEBUG_KMEMLEAK=y +# CONFIG_DEBUG_KMEMLEAK is not set +# CONFIG_DEBUG_STACK_USAGE is not set +# CONFIG_DEBUG_VM is not set +# CONFIG_DEBUG_MEMORY_INIT is not set +# CONFIG_DEBUG_PER_CPU_MAPS is not set +CONFIG_HAVE_ARCH_KASAN=y +# CONFIG_KASAN is not set +# CONFIG_DEBUG_REFCOUNT is not set +# CONFIG_DEBUG_SHIRQ is not set + +# +# Debug Lockups and Hangs +# +CONFIG_LOCKUP_DETECTOR=y +CONFIG_HARDLOCKUP_DETECTOR_OTHER_CPU=y +CONFIG_HARDLOCKUP_DETECTOR=y +# CONFIG_BOOTPARAM_HARDLOCKUP_PANIC is not set +CONFIG_BOOTPARAM_HARDLOCKUP_PANIC_VALUE=0 +CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC=y +CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=1 +CONFIG_DETECT_HUNG_TASK=y +CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=120 +# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set +CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0 +CONFIG_WQ_WATCHDOG=y +# CONFIG_PANIC_ON_OOPS is not set +CONFIG_PANIC_ON_OOPS_VALUE=0 +CONFIG_PANIC_TIMEOUT=5 +CONFIG_SCHED_DEBUG=y +CONFIG_SCHED_INFO=y +CONFIG_PANIC_ON_SCHED_BUG=y +CONFIG_PANIC_ON_RT_THROTTLING=y +CONFIG_SYSRQ_SCHED_DEBUG=y +CONFIG_SCHEDSTATS=y +# CONFIG_SCHED_STACK_END_CHECK is not set +# CONFIG_DEBUG_TIMEKEEPING is not set +# CONFIG_DEBUG_PREEMPT is not set + +# +# Lock Debugging (spinlocks, mutexes, etc...) +# +# CONFIG_DEBUG_RT_MUTEXES is not set +# CONFIG_DEBUG_SPINLOCK is not set +# CONFIG_DEBUG_MUTEXES is not set +# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set +# CONFIG_DEBUG_LOCK_ALLOC is not set +# CONFIG_PROVE_LOCKING is not set +# CONFIG_LOCK_STAT is not set +# CONFIG_DEBUG_ATOMIC_SLEEP is not set +# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set +# CONFIG_LOCK_TORTURE_TEST is not set +CONFIG_STACKTRACE=y +# CONFIG_DEBUG_KOBJECT is not set +CONFIG_HAVE_DEBUG_BUGVERBOSE=y +CONFIG_DEBUG_BUGVERBOSE=y +# CONFIG_DEBUG_LIST is not set +# CONFIG_DEBUG_PI_LIST is not set +# CONFIG_DEBUG_SG is not set +# CONFIG_DEBUG_NOTIFIERS is not set +# CONFIG_DEBUG_CREDENTIALS is not set + +# +# RCU Debugging +# +# CONFIG_PROVE_RCU is not set +# CONFIG_SPARSE_RCU_POINTER is not set +# CONFIG_TORTURE_TEST is not set +# CONFIG_RCU_TORTURE_TEST is not set +CONFIG_RCU_CPU_STALL_TIMEOUT=21 +# CONFIG_RCU_STALL_WATCHDOG_BITE is not set +# CONFIG_RCU_TRACE is not set +# CONFIG_RCU_EQS_DEBUG is not set +# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set +# CONFIG_NOTIFIER_ERROR_INJECTION is not set +# CONFIG_FAULT_INJECTION is not set +CONFIG_NOP_TRACER=y +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y +CONFIG_HAVE_DYNAMIC_FTRACE=y +CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y +CONFIG_HAVE_SYSCALL_TRACEPOINTS=y +CONFIG_HAVE_C_RECORDMCOUNT=y +CONFIG_TRACE_CLOCK=y +CONFIG_RING_BUFFER=y +CONFIG_EVENT_TRACING=y +CONFIG_CONTEXT_SWITCH_TRACER=y +CONFIG_IPC_LOGGING=y +# CONFIG_QCOM_RTB is not set +CONFIG_TRACING=y +CONFIG_GENERIC_TRACER=y +CONFIG_TRACING_SUPPORT=y +# CONFIG_FTRACE is not set + +# +# Runtime Testing +# +# CONFIG_LKDTM is not set +# CONFIG_TEST_LIST_SORT is not set +# CONFIG_BACKTRACE_SELF_TEST is not set +# CONFIG_RBTREE_TEST is not set +# CONFIG_INTERVAL_TREE_TEST is not set +# CONFIG_PERCPU_TEST is not set +# CONFIG_ATOMIC64_SELFTEST is not set +# CONFIG_TEST_HEXDUMP is not set +# CONFIG_TEST_STRING_HELPERS is not set +# CONFIG_TEST_KSTRTOX is not set +# CONFIG_TEST_PRINTF is not set +# CONFIG_TEST_RHASHTABLE is not set +# CONFIG_DMA_API_DEBUG is not set +# CONFIG_TEST_LKM is not set +# CONFIG_TEST_USER_COPY is not set +# CONFIG_TEST_BPF is not set +# CONFIG_TEST_FIRMWARE is not set +# CONFIG_TEST_UDELAY is not set +# CONFIG_MEMTEST is not set +# CONFIG_TEST_STATIC_KEYS is not set +CONFIG_PANIC_ON_DATA_CORRUPTION=y +# CONFIG_SAMPLES is not set +CONFIG_HAVE_ARCH_KGDB=y +# CONFIG_KGDB is not set +CONFIG_ARCH_HAS_UBSAN_SANITIZE_ALL=y +# CONFIG_UBSAN is not set +# CONFIG_ARM64_PTDUMP is not set +# CONFIG_STRICT_DEVMEM is not set +# CONFIG_PID_IN_CONTEXTIDR is not set +# CONFIG_ARM64_RANDOMIZE_TEXT_OFFSET is not set +# CONFIG_DEBUG_SET_MODULE_RONX is not set +CONFIG_DEBUG_RODATA=y +CONFIG_DEBUG_ALIGN_RODATA=y +# CONFIG_FORCE_PAGES is not set +# CONFIG_FREE_PAGES_RDONLY is not set +# CONFIG_ARM64_STRICT_BREAK_BEFORE_MAKE is not set +# CONFIG_CORESIGHT is not set + +# +# Security options +# +CONFIG_KEYS=y +CONFIG_KEYS_COMPAT=y +# CONFIG_PERSISTENT_KEYRINGS is not set +# CONFIG_BIG_KEYS is not set +# CONFIG_ENCRYPTED_KEYS is not set + +# +# Qualcomm Technologies, Inc Per File Encryption security device drivers +# +# CONFIG_SECURITY_DMESG_RESTRICT is not set +CONFIG_SECURITY_PERF_EVENTS_RESTRICT=y +# CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set +CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y +CONFIG_HAVE_ARCH_HARDENED_USERCOPY=y +# CONFIG_HARDENED_USERCOPY is not set +CONFIG_DEFAULT_SECURITY_DAC=y +CONFIG_DEFAULT_SECURITY="" +CONFIG_CRYPTO=y + +# +# Crypto core or helper +# +CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_ALGAPI2=y +CONFIG_CRYPTO_AEAD=y +CONFIG_CRYPTO_AEAD2=y +CONFIG_CRYPTO_BLKCIPHER=y +CONFIG_CRYPTO_BLKCIPHER2=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_HASH2=y +CONFIG_CRYPTO_RNG=y +CONFIG_CRYPTO_RNG2=y +CONFIG_CRYPTO_RNG_DEFAULT=y +CONFIG_CRYPTO_PCOMP2=y +CONFIG_CRYPTO_AKCIPHER2=y +CONFIG_CRYPTO_AKCIPHER=y +# CONFIG_CRYPTO_RSA is not set +CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_MANAGER2=y +# CONFIG_CRYPTO_USER is not set +CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y +CONFIG_CRYPTO_GF128MUL=y +CONFIG_CRYPTO_NULL=y +CONFIG_CRYPTO_NULL2=y +# CONFIG_CRYPTO_PCRYPT is not set +CONFIG_CRYPTO_WORKQUEUE=y +CONFIG_CRYPTO_CRYPTD=y +# CONFIG_CRYPTO_MCRYPTD is not set +CONFIG_CRYPTO_AUTHENC=y +# CONFIG_CRYPTO_TEST is not set +CONFIG_CRYPTO_ABLK_HELPER=y + +# +# Authenticated Encryption with Associated Data +# +CONFIG_CRYPTO_CCM=y +CONFIG_CRYPTO_GCM=y +# CONFIG_CRYPTO_CHACHA20POLY1305 is not set +CONFIG_CRYPTO_SEQIV=y +CONFIG_CRYPTO_ECHAINIV=y + +# +# Block modes +# +CONFIG_CRYPTO_CBC=y +# CONFIG_CRYPTO_HEH is not set +CONFIG_CRYPTO_CTR=y +# CONFIG_CRYPTO_CTS is not set +CONFIG_CRYPTO_ECB=y +# CONFIG_CRYPTO_LRW is not set +# CONFIG_CRYPTO_PCBC is not set +CONFIG_CRYPTO_XTS=y +# CONFIG_CRYPTO_KEYWRAP is not set + +# +# Hash modes +# +CONFIG_CRYPTO_CMAC=y +CONFIG_CRYPTO_HMAC=y +# CONFIG_CRYPTO_XCBC is not set +# CONFIG_CRYPTO_VMAC is not set + +# +# Digest +# +CONFIG_CRYPTO_CRC32C=y +# CONFIG_CRYPTO_CRC32 is not set +# CONFIG_CRYPTO_CRCT10DIF is not set +CONFIG_CRYPTO_GHASH=y +# CONFIG_CRYPTO_POLY1305 is not set +# CONFIG_CRYPTO_MD4 is not set +CONFIG_CRYPTO_MD5=y +# CONFIG_CRYPTO_MICHAEL_MIC is not set +# CONFIG_CRYPTO_RMD128 is not set +# CONFIG_CRYPTO_RMD160 is not set +# CONFIG_CRYPTO_RMD256 is not set +# CONFIG_CRYPTO_RMD320 is not set +CONFIG_CRYPTO_SHA1=y +CONFIG_CRYPTO_SHA256=y +CONFIG_CRYPTO_SHA512=y +# CONFIG_CRYPTO_TGR192 is not set +# CONFIG_CRYPTO_WP512 is not set + +# +# Ciphers +# +CONFIG_CRYPTO_AES=y +# CONFIG_CRYPTO_ANUBIS is not set +CONFIG_CRYPTO_ARC4=y +# CONFIG_CRYPTO_BLOWFISH is not set +# CONFIG_CRYPTO_CAMELLIA is not set +# CONFIG_CRYPTO_CAST5 is not set +# CONFIG_CRYPTO_CAST6 is not set +CONFIG_CRYPTO_DES=y +# CONFIG_CRYPTO_FCRYPT is not set +# CONFIG_CRYPTO_KHAZAD is not set +# CONFIG_CRYPTO_SALSA20 is not set +# CONFIG_CRYPTO_CHACHA20 is not set +# CONFIG_CRYPTO_SEED is not set +# CONFIG_CRYPTO_SERPENT is not set +# CONFIG_CRYPTO_TEA is not set +# CONFIG_CRYPTO_TWOFISH is not set + +# +# Compression +# +CONFIG_CRYPTO_DEFLATE=y +# CONFIG_CRYPTO_ZLIB is not set +# CONFIG_CRYPTO_LZO is not set +# CONFIG_CRYPTO_842 is not set +# CONFIG_CRYPTO_LZ4 is not set +# CONFIG_CRYPTO_LZ4HC is not set + +# +# Random Number Generation +# +CONFIG_CRYPTO_ANSI_CPRNG=y +CONFIG_CRYPTO_DRBG_MENU=y +CONFIG_CRYPTO_DRBG_HMAC=y +# CONFIG_CRYPTO_DRBG_HASH is not set +# CONFIG_CRYPTO_DRBG_CTR is not set +CONFIG_CRYPTO_DRBG=y +CONFIG_CRYPTO_JITTERENTROPY=y +# CONFIG_CRYPTO_USER_API_HASH is not set +# CONFIG_CRYPTO_USER_API_SKCIPHER is not set +# CONFIG_CRYPTO_USER_API_RNG is not set +# CONFIG_CRYPTO_USER_API_AEAD is not set +CONFIG_CRYPTO_HASH_INFO=y +CONFIG_CRYPTO_HW=y +CONFIG_CRYPTO_DEV_QCE50=y +# CONFIG_FIPS_ENABLE is not set +CONFIG_CRYPTO_DEV_QCRYPTO=y +CONFIG_CRYPTO_DEV_QCOM_MSM_QCE=y +CONFIG_CRYPTO_DEV_QCEDEV=y +CONFIG_CRYPTO_DEV_OTA_CRYPTO=y +# CONFIG_CRYPTO_DEV_CCP is not set +# CONFIG_CRYPTO_DEV_QCE is not set +CONFIG_ASYMMETRIC_KEY_TYPE=y +CONFIG_ASYMMETRIC_PUBLIC_KEY_SUBTYPE=y +CONFIG_PUBLIC_KEY_ALGO_RSA=y +CONFIG_X509_CERTIFICATE_PARSER=y +CONFIG_PKCS7_MESSAGE_PARSER=y +# CONFIG_PKCS7_TEST_KEY is not set +# CONFIG_SIGNED_PE_FILE_VERIFICATION is not set + +# +# Certificates for signature checking +# +CONFIG_SYSTEM_TRUSTED_KEYRING=y +CONFIG_SYSTEM_TRUSTED_KEYS="" +CONFIG_ARM64_CRYPTO=y +CONFIG_CRYPTO_SHA1_ARM64_CE=y +CONFIG_CRYPTO_SHA2_ARM64_CE=y +CONFIG_CRYPTO_GHASH_ARM64_CE=y +CONFIG_CRYPTO_POLY_HASH_ARM64_CE=y +CONFIG_CRYPTO_AES_ARM64_CE=y +CONFIG_CRYPTO_AES_ARM64_CE_CCM=y +CONFIG_CRYPTO_AES_ARM64_CE_BLK=y +CONFIG_CRYPTO_AES_ARM64_NEON_BLK=y +CONFIG_CRYPTO_CRC32_ARM64=y +CONFIG_BINARY_PRINTF=y + +# +# Library routines +# +CONFIG_BITREVERSE=y +CONFIG_HAVE_ARCH_BITREVERSE=y +CONFIG_RATIONAL=y +CONFIG_GENERIC_STRNCPY_FROM_USER=y +CONFIG_GENERIC_STRNLEN_USER=y +CONFIG_GENERIC_NET_UTILS=y +CONFIG_GENERIC_PCI_IOMAP=y +CONFIG_GENERIC_IO=y +CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y +CONFIG_CRC_CCITT=y +CONFIG_CRC16=y +# CONFIG_CRC_T10DIF is not set +CONFIG_CRC_ITU_T=y +CONFIG_CRC32=y +# CONFIG_CRC32_SELFTEST is not set +CONFIG_CRC32_SLICEBY8=y +# CONFIG_CRC32_SLICEBY4 is not set +# CONFIG_CRC32_SARWATE is not set +# CONFIG_CRC32_BIT is not set +# CONFIG_CRC7 is not set +CONFIG_LIBCRC32C=y +# CONFIG_CRC8 is not set +CONFIG_AUDIT_GENERIC=y +CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y +CONFIG_AUDIT_COMPAT_GENERIC=y +# CONFIG_RANDOM32_SELFTEST is not set +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=y +CONFIG_LZO_COMPRESS=y +CONFIG_LZO_DECOMPRESS=y +CONFIG_XZ_DEC=y +# CONFIG_XZ_DEC_X86 is not set +# CONFIG_XZ_DEC_POWERPC is not set +# CONFIG_XZ_DEC_IA64 is not set +# CONFIG_XZ_DEC_ARM is not set +# CONFIG_XZ_DEC_ARMTHUMB is not set +# CONFIG_XZ_DEC_SPARC is not set +# CONFIG_XZ_DEC_BCJ is not set +# CONFIG_XZ_DEC_TEST is not set +CONFIG_GENERIC_ALLOCATOR=y +CONFIG_REED_SOLOMON=y +CONFIG_REED_SOLOMON_ENC8=y +CONFIG_REED_SOLOMON_DEC8=y +CONFIG_INTERVAL_TREE=y +CONFIG_ASSOCIATIVE_ARRAY=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT_MAP=y +CONFIG_HAS_DMA=y +CONFIG_CPU_RMAP=y +CONFIG_DQL=y +CONFIG_NLATTR=y +CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y +CONFIG_CLZ_TAB=y +# CONFIG_CORDIC is not set +# CONFIG_DDR is not set +CONFIG_MPILIB=y +CONFIG_LIBFDT=y +CONFIG_OID_REGISTRY=y +# CONFIG_SG_SPLIT is not set +CONFIG_ARCH_HAS_SG_CHAIN=y +CONFIG_QMI_ENCDEC=y +# CONFIG_QMI_ENCDEC_DEBUG is not set +CONFIG_STACKDEPOT=y +CONFIG_ARCH_HAS_FBXSERIAL=y +CONFIG_FBXSERIAL=y --- /dev/null 2019-10-24 16:47:25.704025805 +0200 +++ linux-4.4.115-fbx/drivers/base/dma-removed.c 2019-10-29 09:26:23.409200888 +0100 @@ -0,0 +1,452 @@ +/* + * + * Copyright (c) 2013-2017, The Linux Foundation. All rights reserved. + * Copyright (C) 2000-2004 Russell King + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +struct removed_region { + phys_addr_t base; + int nr_pages; + unsigned long *bitmap; + int fixup; + struct mutex lock; +}; + +#define NO_KERNEL_MAPPING_DUMMY 0x2222 + +static int dma_init_removed_memory(phys_addr_t phys_addr, size_t size, + struct removed_region **mem) +{ + struct removed_region *dma_mem = NULL; + int pages = size >> PAGE_SHIFT; + int bitmap_size = BITS_TO_LONGS(pages) * sizeof(long); + + dma_mem = kzalloc(sizeof(struct removed_region), GFP_KERNEL); + if (!dma_mem) + goto out; + dma_mem->bitmap = kzalloc(bitmap_size, GFP_KERNEL); + if (!dma_mem->bitmap) + goto free1_out; + + dma_mem->base = phys_addr; + dma_mem->nr_pages = pages; + mutex_init(&dma_mem->lock); + + *mem = dma_mem; + + return 0; + +free1_out: + kfree(dma_mem); +out: + return -ENOMEM; +} + +static int dma_assign_removed_region(struct device *dev, + struct removed_region *mem) +{ + if (dev->removed_mem) + return -EBUSY; + + dev->removed_mem = mem; + return 0; +} + +static void adapt_iomem_resource(unsigned long base_pfn, unsigned long end_pfn) +{ + struct resource *res, *conflict; + resource_size_t cstart, cend; + + res = kzalloc(sizeof(*res), GFP_KERNEL); + if (!res) + return; + + res->name = "System RAM"; + res->start = __pfn_to_phys(base_pfn); + res->end = __pfn_to_phys(end_pfn) - 1; + res->flags = IORESOURCE_MEM | IORESOURCE_BUSY; + + conflict = request_resource_conflict(&iomem_resource, res); + if (!conflict) { + pr_err("Removed memory: no conflict resource found\n"); + kfree(res); + goto done; + } + + cstart = conflict->start; + cend = conflict->end; + if ((cstart == res->start) && (cend == res->end)) { + release_resource(conflict); + } else if ((res->start >= cstart) && (res->start <= cend)) { + if (res->start == cstart) { + adjust_resource(conflict, res->end + 1, + cend - res->end); + } else if (res->end == cend) { + adjust_resource(conflict, cstart, + res->start - cstart); + } else { + adjust_resource(conflict, cstart, + res->start - cstart); + res->start = res->end + 1; + res->end = cend; + request_resource(&iomem_resource, res); + goto done; + } + } else { + pr_err("Removed memory: incorrect resource conflict start=%llx end=%llx\n", + (unsigned long long) conflict->start, + (unsigned long long) conflict->end); + } + + kfree(res); +done: + return; +} + +#ifdef CONFIG_FLATMEM +static void free_memmap(unsigned long start_pfn, unsigned long end_pfn) +{ + struct page *start_pg, *end_pg; + unsigned long pg, pgend; + + start_pfn = ALIGN(start_pfn, pageblock_nr_pages); + end_pfn = round_down(end_pfn, pageblock_nr_pages); + /* + * Convert start_pfn/end_pfn to a struct page pointer. + */ + start_pg = pfn_to_page(start_pfn - 1) + 1; + end_pg = pfn_to_page(end_pfn - 1) + 1; + + /* + * Convert to physical addresses, and round start upwards and end + * downwards. + */ + pg = (unsigned long)PAGE_ALIGN(__pa(start_pg)); + pgend = (unsigned long)__pa(end_pg) & PAGE_MASK; + + /* + * If there are free pages between these, free the section of the + * memmap array. + */ + if (pg < pgend) + free_bootmem_late(pg, pgend - pg); +} +#else +static void free_memmap(unsigned long start_pfn, unsigned long end_pfn) +{ +} +#endif + +static int _clear_pte(pte_t *pte, pgtable_t token, unsigned long addr, + void *data) +{ + pte_clear(&init_mm, addr, pte); + return 0; +} + +static void clear_mapping(unsigned long addr, unsigned long size) +{ + apply_to_page_range(&init_mm, addr, size, _clear_pte, NULL); + /* ensure ptes are updated */ + mb(); + flush_tlb_kernel_range(addr, addr + size); +} + +static void removed_region_fixup(struct removed_region *dma_mem, int index) +{ + unsigned long fixup_size; + unsigned long base_pfn; + unsigned long flags; + + if (index > dma_mem->nr_pages) + return; + + /* carve-out */ + flags = memblock_region_resize_late_begin(); + memblock_free(dma_mem->base, dma_mem->nr_pages * PAGE_SIZE); + memblock_remove(dma_mem->base, index * PAGE_SIZE); + memblock_region_resize_late_end(flags); + + /* clear page-mappings */ + base_pfn = dma_mem->base >> PAGE_SHIFT; + if (!PageHighMem(pfn_to_page(base_pfn))) { + clear_mapping((unsigned long) phys_to_virt(dma_mem->base), + index * PAGE_SIZE); + } + + /* free page objects */ + free_memmap(base_pfn, base_pfn + index); + + /* return remaining area to system */ + fixup_size = (dma_mem->nr_pages - index) * PAGE_SIZE; + free_bootmem_late(dma_mem->base + index * PAGE_SIZE, fixup_size); + + /* + * release freed resource region so as to show up under iomem resource + * list + */ + adapt_iomem_resource(base_pfn, base_pfn + index); + + /* limit the fixup region */ + dma_mem->nr_pages = index; +} + +void *removed_alloc(struct device *dev, size_t size, dma_addr_t *handle, + gfp_t gfp, struct dma_attrs *attrs) +{ + bool no_kernel_mapping = dma_get_attr(DMA_ATTR_NO_KERNEL_MAPPING, + attrs); + bool skip_zeroing = dma_get_attr(DMA_ATTR_SKIP_ZEROING, attrs); + int pageno; + unsigned long order; + void *addr = NULL; + struct removed_region *dma_mem = dev->removed_mem; + int nbits; + unsigned int align; + + if (!gfpflags_allow_blocking(gfp)) + return NULL; + + size = PAGE_ALIGN(size); + nbits = size >> PAGE_SHIFT; + order = get_order(size); + + if (order > get_order(SZ_1M)) + order = get_order(SZ_1M); + + align = (1 << order) - 1; + + + mutex_lock(&dma_mem->lock); + pageno = bitmap_find_next_zero_area(dma_mem->bitmap, dma_mem->nr_pages, + 0, nbits, align); + + if (pageno < dma_mem->nr_pages) { + phys_addr_t base = dma_mem->base + pageno * PAGE_SIZE; + *handle = base; + + bitmap_set(dma_mem->bitmap, pageno, nbits); + + if (dma_mem->fixup) { + removed_region_fixup(dma_mem, pageno + nbits); + dma_mem->fixup = 0; + } + + if (no_kernel_mapping && skip_zeroing) { + addr = (void *)NO_KERNEL_MAPPING_DUMMY; + goto out; + } + + addr = ioremap(base, size); + if (WARN_ON(!addr)) { + bitmap_clear(dma_mem->bitmap, pageno, nbits); + } else { + if (!skip_zeroing) + memset_io(addr, 0, size); + if (no_kernel_mapping) { + iounmap(addr); + addr = (void *)NO_KERNEL_MAPPING_DUMMY; + } + *handle = base; + } + } + +out: + mutex_unlock(&dma_mem->lock); + return addr; +} + + +int removed_mmap(struct device *dev, struct vm_area_struct *vma, + void *cpu_addr, dma_addr_t dma_addr, size_t size, + struct dma_attrs *attrs) +{ + return -ENXIO; +} + +void removed_free(struct device *dev, size_t size, void *cpu_addr, + dma_addr_t handle, struct dma_attrs *attrs) +{ + bool no_kernel_mapping = dma_get_attr(DMA_ATTR_NO_KERNEL_MAPPING, + attrs); + struct removed_region *dma_mem = dev->removed_mem; + + size = PAGE_ALIGN(size); + if (!no_kernel_mapping) + iounmap(cpu_addr); + mutex_lock(&dma_mem->lock); + bitmap_clear(dma_mem->bitmap, (handle - dma_mem->base) >> PAGE_SHIFT, + size >> PAGE_SHIFT); + mutex_unlock(&dma_mem->lock); +} + +static dma_addr_t removed_map_page(struct device *dev, struct page *page, + unsigned long offset, size_t size, + enum dma_data_direction dir, + struct dma_attrs *attrs) +{ + return ~(dma_addr_t)0; +} + +static void removed_unmap_page(struct device *dev, dma_addr_t dma_handle, + size_t size, enum dma_data_direction dir, + struct dma_attrs *attrs) +{ + return; +} + +static int removed_map_sg(struct device *dev, struct scatterlist *sg, + int nents, enum dma_data_direction dir, + struct dma_attrs *attrs) +{ + return 0; +} + +static void removed_unmap_sg(struct device *dev, + struct scatterlist *sg, int nents, + enum dma_data_direction dir, + struct dma_attrs *attrs) +{ + return; +} + +static void removed_sync_single_for_cpu(struct device *dev, + dma_addr_t dma_handle, size_t size, + enum dma_data_direction dir) +{ + return; +} + +void removed_sync_single_for_device(struct device *dev, + dma_addr_t dma_handle, size_t size, + enum dma_data_direction dir) +{ + return; +} + +void removed_sync_sg_for_cpu(struct device *dev, + struct scatterlist *sg, int nents, + enum dma_data_direction dir) +{ + return; +} + +void removed_sync_sg_for_device(struct device *dev, + struct scatterlist *sg, int nents, + enum dma_data_direction dir) +{ + return; +} + +void *removed_remap(struct device *dev, void *cpu_addr, dma_addr_t handle, + size_t size, struct dma_attrs *attrs) +{ + return ioremap(handle, size); +} + +void removed_unremap(struct device *dev, void *remapped_address, size_t size) +{ + iounmap(remapped_address); +} + +struct dma_map_ops removed_dma_ops = { + .alloc = removed_alloc, + .free = removed_free, + .mmap = removed_mmap, + .map_page = removed_map_page, + .unmap_page = removed_unmap_page, + .map_sg = removed_map_sg, + .unmap_sg = removed_unmap_sg, + .sync_single_for_cpu = removed_sync_single_for_cpu, + .sync_single_for_device = removed_sync_single_for_device, + .sync_sg_for_cpu = removed_sync_sg_for_cpu, + .sync_sg_for_device = removed_sync_sg_for_device, + .remap = removed_remap, + .unremap = removed_unremap, +}; +EXPORT_SYMBOL(removed_dma_ops); + +#ifdef CONFIG_OF_RESERVED_MEM +#include +#include +#include + +static int rmem_dma_device_init(struct reserved_mem *rmem, struct device *dev) +{ + struct removed_region *mem = rmem->priv; + if (!mem && dma_init_removed_memory(rmem->base, rmem->size, &mem)) { + pr_info("Reserved memory: failed to init DMA memory pool at %pa, size %ld MiB\n", + &rmem->base, (unsigned long)rmem->size / SZ_1M); + return -EINVAL; + } + mem->fixup = rmem->fixup; + set_dma_ops(dev, &removed_dma_ops); + rmem->priv = mem; + dma_assign_removed_region(dev, mem); + return 0; +} + +static void rmem_dma_device_release(struct reserved_mem *rmem, + struct device *dev) +{ + dev->dma_mem = NULL; +} + +static const struct reserved_mem_ops removed_mem_ops = { + .device_init = rmem_dma_device_init, + .device_release = rmem_dma_device_release, +}; + +static int __init removed_dma_setup(struct reserved_mem *rmem) +{ + unsigned long node = rmem->fdt_node; + int nomap, fixup; + + nomap = of_get_flat_dt_prop(node, "no-map", NULL) != NULL; + fixup = of_get_flat_dt_prop(node, "no-map-fixup", NULL) != NULL; + + if (nomap && fixup) { + pr_err("Removed memory: nomap & nomap-fixup can't co-exist\n"); + return -EINVAL; + } + + rmem->fixup = fixup; + if (rmem->fixup) { + /* Architecture specific contiguous memory fixup only for + * no-map-fixup to split mappings + */ + dma_contiguous_early_fixup(rmem->base, rmem->size); + } + + rmem->ops = &removed_mem_ops; + pr_info("Removed memory: created DMA memory pool at %pa, size %ld MiB\n", + &rmem->base, (unsigned long)rmem->size / SZ_1M); + return 0; +} +RESERVEDMEM_OF_DECLARE(dma, "removed-dma-pool", removed_dma_setup); +#endif --- /dev/null 2019-10-24 16:47:25.704025805 +0200 +++ linux-4.4.115-fbx/drivers/base/power/opp/debugfs.c 2019-01-22 16:16:22.879240756 +0100 @@ -0,0 +1,218 @@ +/* + * Generic OPP debugfs interface + * + * Copyright (C) 2015-2016 Viresh Kumar + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt + +#include +#include +#include +#include +#include + +#include "opp.h" + +static struct dentry *rootdir; + +static void opp_set_dev_name(const struct device *dev, char *name) +{ + if (dev->parent) + snprintf(name, NAME_MAX, "%s-%s", dev_name(dev->parent), + dev_name(dev)); + else + snprintf(name, NAME_MAX, "%s", dev_name(dev)); +} + +void opp_debug_remove_one(struct dev_pm_opp *opp) +{ + debugfs_remove_recursive(opp->dentry); +} + +int opp_debug_create_one(struct dev_pm_opp *opp, struct opp_table *opp_table) +{ + struct dentry *pdentry = opp_table->dentry; + struct dentry *d; + char name[25]; /* 20 chars for 64 bit value + 5 (opp:\0) */ + + /* Rate is unique to each OPP, use it to give opp-name */ + snprintf(name, sizeof(name), "opp:%lu", opp->rate); + + /* Create per-opp directory */ + d = debugfs_create_dir(name, pdentry); + if (!d) + return -ENOMEM; + + if (!debugfs_create_bool("available", S_IRUGO, d, &opp->available)) + return -ENOMEM; + + if (!debugfs_create_bool("dynamic", S_IRUGO, d, &opp->dynamic)) + return -ENOMEM; + + if (!debugfs_create_bool("turbo", S_IRUGO, d, &opp->turbo)) + return -ENOMEM; + + if (!debugfs_create_bool("suspend", S_IRUGO, d, &opp->suspend)) + return -ENOMEM; + + if (!debugfs_create_ulong("rate_hz", S_IRUGO, d, &opp->rate)) + return -ENOMEM; + + if (!debugfs_create_ulong("u_volt_target", S_IRUGO, d, &opp->u_volt)) + return -ENOMEM; + + if (!debugfs_create_ulong("u_volt_min", S_IRUGO, d, &opp->u_volt_min)) + return -ENOMEM; + + if (!debugfs_create_ulong("u_volt_max", S_IRUGO, d, &opp->u_volt_max)) + return -ENOMEM; + + if (!debugfs_create_ulong("u_amp", S_IRUGO, d, &opp->u_amp)) + return -ENOMEM; + + if (!debugfs_create_ulong("clock_latency_ns", S_IRUGO, d, + &opp->clock_latency_ns)) + return -ENOMEM; + + opp->dentry = d; + return 0; +} + +static int opp_list_debug_create_dir(struct opp_device *opp_dev, + struct opp_table *opp_table) +{ + const struct device *dev = opp_dev->dev; + struct dentry *d; + + opp_set_dev_name(dev, opp_table->dentry_name); + + /* Create device specific directory */ + d = debugfs_create_dir(opp_table->dentry_name, rootdir); + if (!d) { + dev_err(dev, "%s: Failed to create debugfs dir\n", __func__); + return -ENOMEM; + } + + opp_dev->dentry = d; + opp_table->dentry = d; + + return 0; +} + +static int opp_list_debug_create_link(struct opp_device *opp_dev, + struct opp_table *opp_table) +{ + const struct device *dev = opp_dev->dev; + char name[NAME_MAX]; + struct dentry *d; + + opp_set_dev_name(opp_dev->dev, name); + + /* Create device specific directory link */ + d = debugfs_create_symlink(name, rootdir, opp_table->dentry_name); + if (!d) { + dev_err(dev, "%s: Failed to create link\n", __func__); + return -ENOMEM; + } + + opp_dev->dentry = d; + + return 0; +} + +/** + * opp_debug_register - add a device opp node to the debugfs 'opp' directory + * @opp_dev: opp-dev pointer for device + * @opp_table: the device-opp being added + * + * Dynamically adds device specific directory in debugfs 'opp' directory. If the + * device-opp is shared with other devices, then links will be created for all + * devices except the first. + * + * Return: 0 on success, otherwise negative error. + */ +int opp_debug_register(struct opp_device *opp_dev, struct opp_table *opp_table) +{ + if (!rootdir) { + pr_debug("%s: Uninitialized rootdir\n", __func__); + return -EINVAL; + } + + if (opp_table->dentry) + return opp_list_debug_create_link(opp_dev, opp_table); + + return opp_list_debug_create_dir(opp_dev, opp_table); +} + +static void opp_migrate_dentry(struct opp_device *opp_dev, + struct opp_table *opp_table) +{ + struct opp_device *new_dev; + const struct device *dev; + struct dentry *dentry; + + /* Look for next opp-dev */ + list_for_each_entry(new_dev, &opp_table->dev_list, node) + if (new_dev != opp_dev) + break; + + /* new_dev is guaranteed to be valid here */ + dev = new_dev->dev; + debugfs_remove_recursive(new_dev->dentry); + + opp_set_dev_name(dev, opp_table->dentry_name); + + dentry = debugfs_rename(rootdir, opp_dev->dentry, rootdir, + opp_table->dentry_name); + if (!dentry) { + dev_err(dev, "%s: Failed to rename link from: %s to %s\n", + __func__, dev_name(opp_dev->dev), dev_name(dev)); + return; + } + + new_dev->dentry = dentry; + opp_table->dentry = dentry; +} + +/** + * opp_debug_unregister - remove a device opp node from debugfs opp directory + * @opp_dev: opp-dev pointer for device + * @opp_table: the device-opp being removed + * + * Dynamically removes device specific directory from debugfs 'opp' directory. + */ +void opp_debug_unregister(struct opp_device *opp_dev, + struct opp_table *opp_table) +{ + if (opp_dev->dentry == opp_table->dentry) { + /* Move the real dentry object under another device */ + if (!list_is_singular(&opp_table->dev_list)) { + opp_migrate_dentry(opp_dev, opp_table); + goto out; + } + opp_table->dentry = NULL; + } + + debugfs_remove_recursive(opp_dev->dentry); + +out: + opp_dev->dentry = NULL; +} + +static int __init opp_debug_init(void) +{ + /* Create /sys/kernel/debug/opp directory */ + rootdir = debugfs_create_dir("opp", NULL); + if (!rootdir) { + pr_err("%s: Failed to create root directory\n", __func__); + return -ENOMEM; + } + + return 0; +} +core_initcall(opp_debug_init); --- /dev/null 2019-10-24 16:47:25.704025805 +0200 +++ linux-4.4.115-fbx/drivers/base/regmap/regmap-swr.c 2019-01-22 16:16:22.883240792 +0100 @@ -0,0 +1,216 @@ +/* + * Copyright (c) 2015-2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include + +#include "internal.h" + +static int regmap_swr_gather_write(void *context, + const void *reg, size_t reg_size, + const void *val, size_t val_len) +{ + struct device *dev = context; + struct swr_device *swr = to_swr_device(dev); + struct regmap *map = dev_get_regmap(dev, NULL); + size_t addr_bytes; + size_t val_bytes; + int i, ret = 0; + u16 reg_addr = 0; + + if (map == NULL) { + dev_err(dev, "%s: regmap is NULL\n", __func__); + return -EINVAL; + } + addr_bytes = map->format.reg_bytes; + if (swr == NULL) { + dev_err(dev, "%s: swr device is NULL\n", __func__); + return -EINVAL; + } + if (reg_size != addr_bytes) { + dev_err(dev, "%s: reg size %zd bytes not supported\n", + __func__, reg_size); + return -EINVAL; + } + reg_addr = *(u16 *)reg; + val_bytes = map->format.val_bytes; + /* val_len = val_bytes * val_count */ + for (i = 0; i < (val_len / val_bytes); i++) { + reg_addr = reg_addr + i; + val = (u8 *)val + (val_bytes * i); + ret = swr_write(swr, swr->dev_num, reg_addr, val); + if (ret < 0) { + dev_err(dev, "%s: write reg 0x%x failed, err %d\n", + __func__, reg_addr, ret); + break; + } + } + return ret; +} + +static int regmap_swr_raw_multi_reg_write(void *context, const void *data, + size_t count) +{ + struct device *dev = context; + struct swr_device *swr = to_swr_device(dev); + struct regmap *map = dev_get_regmap(dev, NULL); + size_t addr_bytes; + size_t val_bytes; + size_t pad_bytes; + size_t num_regs; + int i = 0; + int ret = 0; + u16 *reg; + u8 *val; + u8 *buf; + + if (swr == NULL) { + dev_err(dev, "%s: swr device is NULL\n", __func__); + return -EINVAL; + } + + if (map == NULL) { + dev_err(dev, "%s: regmap is NULL\n", __func__); + return -EINVAL; + } + + addr_bytes = map->format.reg_bytes; + val_bytes = map->format.val_bytes; + pad_bytes = map->format.pad_bytes; + + if (addr_bytes + val_bytes + pad_bytes == 0) { + dev_err(dev, "%s: sum of addr, value and pad is 0\n", __func__); + return -EINVAL; + } + num_regs = count / (addr_bytes + val_bytes + pad_bytes); + + reg = kcalloc(num_regs, sizeof(u16), GFP_KERNEL); + if (!reg) + return -ENOMEM; + + val = kcalloc(num_regs, sizeof(u8), GFP_KERNEL); + if (!val) { + ret = -ENOMEM; + goto mem_fail; + } + + buf = (u8 *)data; + for (i = 0; i < num_regs; i++) { + reg[i] = *(u16 *)buf; + buf += (map->format.reg_bytes + map->format.pad_bytes); + val[i] = *buf; + buf += map->format.val_bytes; + } + ret = swr_bulk_write(swr, swr->dev_num, reg, val, num_regs); + if (ret) + dev_err(dev, "%s: multi reg write failed\n", __func__); + + kfree(val); +mem_fail: + kfree(reg); + return ret; +} + +static int regmap_swr_write(void *context, const void *data, size_t count) +{ + struct device *dev = context; + struct regmap *map = dev_get_regmap(dev, NULL); + size_t addr_bytes; + size_t val_bytes; + size_t pad_bytes; + + if (map == NULL) { + dev_err(dev, "%s: regmap is NULL\n", __func__); + return -EINVAL; + } + addr_bytes = map->format.reg_bytes; + val_bytes = map->format.val_bytes; + pad_bytes = map->format.pad_bytes; + + WARN_ON(count < addr_bytes); + + if (count > (addr_bytes + val_bytes + pad_bytes)) + return regmap_swr_raw_multi_reg_write(context, data, count); + else + return regmap_swr_gather_write(context, data, addr_bytes, + (data + addr_bytes), + (count - addr_bytes)); +} + +static int regmap_swr_read(void *context, + const void *reg, size_t reg_size, + void *val, size_t val_size) +{ + struct device *dev = context; + struct swr_device *swr = to_swr_device(dev); + struct regmap *map = dev_get_regmap(dev, NULL); + size_t addr_bytes; + int ret = 0; + u16 reg_addr = 0; + + if (map == NULL) { + dev_err(dev, "%s: regmap is NULL\n", __func__); + return -EINVAL; + } + addr_bytes = map->format.reg_bytes; + if (swr == NULL) { + dev_err(dev, "%s: swr is NULL\n", __func__); + return -EINVAL; + } + if (reg_size != addr_bytes) { + dev_err(dev, "%s: register size %zd bytes not supported\n", + __func__, reg_size); + return -EINVAL; + } + reg_addr = *(u16 *)reg; + ret = swr_read(swr, swr->dev_num, reg_addr, val, val_size); + if (ret < 0) + dev_err(dev, "%s: codec reg 0x%x read failed %d\n", + __func__, reg_addr, ret); + return ret; +} + +static struct regmap_bus regmap_swr = { + .write = regmap_swr_write, + .gather_write = regmap_swr_gather_write, + .read = regmap_swr_read, + .reg_format_endian_default = REGMAP_ENDIAN_NATIVE, + .val_format_endian_default = REGMAP_ENDIAN_NATIVE, +}; + +struct regmap *__regmap_init_swr(struct swr_device *swr, + const struct regmap_config *config, + struct lock_class_key *lock_key, + const char *lock_name) +{ + return __regmap_init(&swr->dev, ®map_swr, &swr->dev, config, + lock_key, lock_name); +} +EXPORT_SYMBOL(__regmap_init_swr); + +struct regmap *__devm_regmap_init_swr(struct swr_device *swr, + const struct regmap_config *config, + struct lock_class_key *lock_key, + const char *lock_name) +{ + return __devm_regmap_init(&swr->dev, ®map_swr, &swr->dev, config, + lock_key, lock_name); +} +EXPORT_SYMBOL(__devm_regmap_init_swr); + +MODULE_LICENSE("GPL v2"); diff -Nruw linux-4.4.115-fbx/drivers/bif./Kconfig linux-4.4.115-fbx/drivers/bif/Kconfig --- linux-4.4.115-fbx/drivers/bif./Kconfig 1970-01-01 01:00:00.000000000 +0100 +++ linux-4.4.115-fbx/drivers/bif/Kconfig 2019-01-22 16:16:22.887240828 +0100 @@ -0,0 +1,25 @@ +# +# BIF framework and drivers +# +menuconfig BIF + bool "MIPI-BIF support" + select CRC_CCITT + select BITREVERSE + help + MIPI-BIF (battery interface) is a one-wire serial interface between a + host master device and one or more slave devices which are located in + a battery pack or also on the host. Enabling this option allows for + BIF consumer drivers to issue transactions via BIF controller drivers. + +if BIF +config BIF_QPNP + depends on SPMI + tristate "Qualcomm QPNP BIF support" + help + This driver supports the QPNP BSI peripheral found inside of Qualcomm + QPNP PMIC devices. The BSI peripheral is able to communicate using + the BIF protocol. The QPNP BSI driver hooks into the BIF framework. + Enable this option in order to provide support for BIF communication + on targets which have BSI PMIC peripherals. + +endif diff -Nruw linux-4.4.115-fbx/drivers/bif./Makefile linux-4.4.115-fbx/drivers/bif/Makefile --- linux-4.4.115-fbx/drivers/bif./Makefile 1970-01-01 01:00:00.000000000 +0100 +++ linux-4.4.115-fbx/drivers/bif/Makefile 2019-01-22 16:16:22.887240828 +0100 @@ -0,0 +1,5 @@ +# +# Makefile for kernel BIF framework. +# +obj-$(CONFIG_BIF) += bif-core.o +obj-$(CONFIG_BIF_QPNP) += qpnp-bsi.o --- /dev/null 2019-10-24 16:47:25.704025805 +0200 +++ linux-4.4.115-fbx/drivers/bluetooth/bluetooth-power.c 2019-01-22 16:16:22.927241190 +0100 @@ -0,0 +1,773 @@ +/* Copyright (c) 2009-2010, 2013-2017 The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +/* + * Bluetooth Power Switch Module + * controls power to external Bluetooth device + * with interface to power management device + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "btfm_slim.h" +#include + +#define BT_PWR_DBG(fmt, arg...) pr_debug("%s: " fmt "\n", __func__, ## arg) +#define BT_PWR_INFO(fmt, arg...) pr_info("%s: " fmt "\n", __func__, ## arg) +#define BT_PWR_ERR(fmt, arg...) pr_err("%s: " fmt "\n", __func__, ## arg) + + +static const struct of_device_id bt_power_match_table[] = { + { .compatible = "qca,ar3002" }, + { .compatible = "qca,qca6174" }, + { .compatible = "qca,wcn3990" }, + {} +}; + +static struct bluetooth_power_platform_data *bt_power_pdata; +static struct platform_device *btpdev; +static bool previous; +static int pwr_state; +struct class *bt_class; +static int bt_major; + +static int bt_vreg_init(struct bt_power_vreg_data *vreg) +{ + int rc = 0; + struct device *dev = &btpdev->dev; + + BT_PWR_DBG("vreg_get for : %s", vreg->name); + + /* Get the regulator handle */ + vreg->reg = regulator_get(dev, vreg->name); + if (IS_ERR(vreg->reg)) { + rc = PTR_ERR(vreg->reg); + pr_err("%s: regulator_get(%s) failed. rc=%d\n", + __func__, vreg->name, rc); + goto out; + } + + if ((regulator_count_voltages(vreg->reg) > 0) + && (vreg->low_vol_level) && (vreg->high_vol_level)) + vreg->set_voltage_sup = 1; + +out: + return rc; +} + +static int bt_vreg_enable(struct bt_power_vreg_data *vreg) +{ + int rc = 0; + + BT_PWR_DBG("vreg_en for : %s", vreg->name); + + if (!vreg->is_enabled) { + if (vreg->set_voltage_sup) { + rc = regulator_set_voltage(vreg->reg, + vreg->low_vol_level, + vreg->high_vol_level); + if (rc < 0) { + BT_PWR_ERR("vreg_set_vol(%s) failed rc=%d\n", + vreg->name, rc); + goto out; + } + } + + if (vreg->load_uA >= 0) { + rc = regulator_set_load(vreg->reg, + vreg->load_uA); + if (rc < 0) { + BT_PWR_ERR("vreg_set_mode(%s) failed rc=%d\n", + vreg->name, rc); + goto out; + } + } + + rc = regulator_enable(vreg->reg); + if (rc < 0) { + BT_PWR_ERR("regulator_enable(%s) failed. rc=%d\n", + vreg->name, rc); + goto out; + } + vreg->is_enabled = true; + } +out: + return rc; +} + +static int bt_vreg_disable(struct bt_power_vreg_data *vreg) +{ + int rc = 0; + + if (!vreg) + return rc; + + BT_PWR_DBG("vreg_disable for : %s", vreg->name); + + if (vreg->is_enabled) { + rc = regulator_disable(vreg->reg); + if (rc < 0) { + BT_PWR_ERR("regulator_disable(%s) failed. rc=%d\n", + vreg->name, rc); + goto out; + } + vreg->is_enabled = false; + + if (vreg->set_voltage_sup) { + /* Set the min voltage to 0 */ + rc = regulator_set_voltage(vreg->reg, 0, + vreg->high_vol_level); + if (rc < 0) { + BT_PWR_ERR("vreg_set_vol(%s) failed rc=%d\n", + vreg->name, rc); + goto out; + } + } + if (vreg->load_uA >= 0) { + rc = regulator_set_load(vreg->reg, 0); + if (rc < 0) { + BT_PWR_ERR("vreg_set_mode(%s) failed rc=%d\n", + vreg->name, rc); + } + } + } +out: + return rc; +} + +static int bt_configure_vreg(struct bt_power_vreg_data *vreg) +{ + int rc = 0; + + BT_PWR_DBG("config %s", vreg->name); + + /* Get the regulator handle for vreg */ + if (!(vreg->reg)) { + rc = bt_vreg_init(vreg); + if (rc < 0) + return rc; + } + rc = bt_vreg_enable(vreg); + + return rc; +} + +static int bt_clk_enable(struct bt_power_clk_data *clk) +{ + int rc = 0; + + BT_PWR_DBG("%s", clk->name); + + /* Get the clock handle for vreg */ + if (!clk->clk || clk->is_enabled) { + BT_PWR_ERR("error - node: %p, clk->is_enabled:%d", + clk->clk, clk->is_enabled); + return -EINVAL; + } + + rc = clk_prepare_enable(clk->clk); + if (rc) { + BT_PWR_ERR("failed to enable %s, rc(%d)\n", clk->name, rc); + return rc; + } + + clk->is_enabled = true; + return rc; +} + +static int bt_clk_disable(struct bt_power_clk_data *clk) +{ + int rc = 0; + + BT_PWR_DBG("%s", clk->name); + + /* Get the clock handle for vreg */ + if (!clk->clk || !clk->is_enabled) { + BT_PWR_ERR("error - node: %p, clk->is_enabled:%d", + clk->clk, clk->is_enabled); + return -EINVAL; + } + clk_disable_unprepare(clk->clk); + + clk->is_enabled = false; + return rc; +} + +static int bt_configure_gpios(int on) +{ + int rc = 0; + int bt_reset_gpio = bt_power_pdata->bt_gpio_sys_rst; + + BT_PWR_DBG("bt_gpio= %d on: %d", bt_reset_gpio, on); + + if (on) { + rc = gpio_request(bt_reset_gpio, "bt_sys_rst_n"); + if (rc) { + BT_PWR_ERR("unable to request gpio %d (%d)\n", + bt_reset_gpio, rc); + return rc; + } + + rc = gpio_direction_output(bt_reset_gpio, 0); + if (rc) { + BT_PWR_ERR("Unable to set direction\n"); + return rc; + } + msleep(50); + rc = gpio_direction_output(bt_reset_gpio, 1); + if (rc) { + BT_PWR_ERR("Unable to set direction\n"); + return rc; + } + msleep(50); + } else { + gpio_set_value(bt_reset_gpio, 0); + msleep(100); + } + return rc; +} + +static int bluetooth_power(int on) +{ + int rc = 0; + + BT_PWR_DBG("on: %d", on); + + if (on) { + if (bt_power_pdata->bt_vdd_io) { + rc = bt_configure_vreg(bt_power_pdata->bt_vdd_io); + if (rc < 0) { + BT_PWR_ERR("bt_power vddio config failed"); + goto out; + } + } + if (bt_power_pdata->bt_vdd_xtal) { + rc = bt_configure_vreg(bt_power_pdata->bt_vdd_xtal); + if (rc < 0) { + BT_PWR_ERR("bt_power vddxtal config failed"); + goto vdd_xtal_fail; + } + } + if (bt_power_pdata->bt_vdd_core) { + rc = bt_configure_vreg(bt_power_pdata->bt_vdd_core); + if (rc < 0) { + BT_PWR_ERR("bt_power vddcore config failed"); + goto vdd_core_fail; + } + } + if (bt_power_pdata->bt_vdd_pa) { + rc = bt_configure_vreg(bt_power_pdata->bt_vdd_pa); + if (rc < 0) { + BT_PWR_ERR("bt_power vddpa config failed"); + goto vdd_pa_fail; + } + } + if (bt_power_pdata->bt_vdd_ldo) { + rc = bt_configure_vreg(bt_power_pdata->bt_vdd_ldo); + if (rc < 0) { + BT_PWR_ERR("bt_power vddldo config failed"); + goto vdd_ldo_fail; + } + } + if (bt_power_pdata->bt_chip_pwd) { + rc = bt_configure_vreg(bt_power_pdata->bt_chip_pwd); + if (rc < 0) { + BT_PWR_ERR("bt_power chippwd config failed"); + goto chip_pwd_fail; + } + } + /* Parse dt_info and check if a target requires clock voting. + * Enable BT clock when BT is on and disable it when BT is off + */ + if (bt_power_pdata->bt_chip_clk) { + rc = bt_clk_enable(bt_power_pdata->bt_chip_clk); + if (rc < 0) { + BT_PWR_ERR("bt_power gpio config failed"); + goto clk_fail; + } + } + if (bt_power_pdata->bt_gpio_sys_rst > 0) { + rc = bt_configure_gpios(on); + if (rc < 0) { + BT_PWR_ERR("bt_power gpio config failed"); + goto gpio_fail; + } + } + } else { + if (bt_power_pdata->bt_gpio_sys_rst > 0) + bt_configure_gpios(on); +gpio_fail: + if (bt_power_pdata->bt_gpio_sys_rst > 0) + gpio_free(bt_power_pdata->bt_gpio_sys_rst); + if (bt_power_pdata->bt_chip_clk) + bt_clk_disable(bt_power_pdata->bt_chip_clk); +clk_fail: + if (bt_power_pdata->bt_chip_pwd) + bt_vreg_disable(bt_power_pdata->bt_chip_pwd); +chip_pwd_fail: + if (bt_power_pdata->bt_vdd_ldo) + bt_vreg_disable(bt_power_pdata->bt_vdd_ldo); +vdd_ldo_fail: + if (bt_power_pdata->bt_vdd_pa) + bt_vreg_disable(bt_power_pdata->bt_vdd_pa); +vdd_pa_fail: + if (bt_power_pdata->bt_vdd_core) + bt_vreg_disable(bt_power_pdata->bt_vdd_core); +vdd_core_fail: + if (bt_power_pdata->bt_vdd_xtal) + bt_vreg_disable(bt_power_pdata->bt_vdd_xtal); +vdd_xtal_fail: + if (bt_power_pdata->bt_vdd_io) + bt_vreg_disable(bt_power_pdata->bt_vdd_io); + } +out: + return rc; +} + +static int bluetooth_toggle_radio(void *data, bool blocked) +{ + int ret = 0; + int (*power_control)(int enable); + + power_control = + ((struct bluetooth_power_platform_data *)data)->bt_power_setup; + + if (previous != blocked) + ret = (*power_control)(!blocked); + if (!ret) + previous = blocked; + return ret; +} + +static const struct rfkill_ops bluetooth_power_rfkill_ops = { + .set_block = bluetooth_toggle_radio, +}; + +#if defined(CONFIG_CNSS) && defined(CONFIG_CLD_LL_CORE) +static ssize_t enable_extldo(struct device *dev, struct device_attribute *attr, + char *buf) +{ + int ret; + bool enable = false; + struct cnss_platform_cap cap; + + ret = cnss_get_platform_cap(&cap); + if (ret) { + BT_PWR_ERR("Platform capability info from CNSS not available!"); + enable = false; + } else if (!ret && (cap.cap_flag & CNSS_HAS_EXTERNAL_SWREG)) { + enable = true; + } + return snprintf(buf, 6, "%s", (enable ? "true" : "false")); +} +#else +static ssize_t enable_extldo(struct device *dev, struct device_attribute *attr, + char *buf) +{ + return snprintf(buf, 6, "%s", "false"); +} +#endif + +static DEVICE_ATTR(extldo, S_IRUGO, enable_extldo, NULL); + +static int bluetooth_power_rfkill_probe(struct platform_device *pdev) +{ + struct rfkill *rfkill; + int ret; + + rfkill = rfkill_alloc("bt_power", &pdev->dev, RFKILL_TYPE_BLUETOOTH, + &bluetooth_power_rfkill_ops, + pdev->dev.platform_data); + + if (!rfkill) { + dev_err(&pdev->dev, "rfkill allocate failed\n"); + return -ENOMEM; + } + + /* add file into rfkill0 to handle LDO27 */ + ret = device_create_file(&pdev->dev, &dev_attr_extldo); + if (ret < 0) + BT_PWR_ERR("device create file error!"); + + /* force Bluetooth off during init to allow for user control */ + rfkill_init_sw_state(rfkill, 1); + previous = 1; + + ret = rfkill_register(rfkill); + if (ret) { + dev_err(&pdev->dev, "rfkill register failed=%d\n", ret); + rfkill_destroy(rfkill); + return ret; + } + + platform_set_drvdata(pdev, rfkill); + + return 0; +} + +static void bluetooth_power_rfkill_remove(struct platform_device *pdev) +{ + struct rfkill *rfkill; + + dev_dbg(&pdev->dev, "%s\n", __func__); + + rfkill = platform_get_drvdata(pdev); + if (rfkill) + rfkill_unregister(rfkill); + rfkill_destroy(rfkill); + platform_set_drvdata(pdev, NULL); +} + +#define MAX_PROP_SIZE 32 +static int bt_dt_parse_vreg_info(struct device *dev, + struct bt_power_vreg_data **vreg_data, const char *vreg_name) +{ + int len, ret = 0; + const __be32 *prop; + char prop_name[MAX_PROP_SIZE]; + struct bt_power_vreg_data *vreg; + struct device_node *np = dev->of_node; + + BT_PWR_DBG("vreg dev tree parse for %s", vreg_name); + + *vreg_data = NULL; + snprintf(prop_name, MAX_PROP_SIZE, "%s-supply", vreg_name); + if (of_parse_phandle(np, prop_name, 0)) { + vreg = devm_kzalloc(dev, sizeof(*vreg), GFP_KERNEL); + if (!vreg) { + dev_err(dev, "No memory for vreg: %s\n", vreg_name); + ret = -ENOMEM; + goto err; + } + + vreg->name = vreg_name; + + /* Parse voltage-level from each node */ + snprintf(prop_name, MAX_PROP_SIZE, + "%s-voltage-level", vreg_name); + prop = of_get_property(np, prop_name, &len); + if (!prop || (len != (2 * sizeof(__be32)))) { + dev_warn(dev, "%s %s property\n", + prop ? "invalid format" : "no", prop_name); + } else { + vreg->low_vol_level = be32_to_cpup(&prop[0]); + vreg->high_vol_level = be32_to_cpup(&prop[1]); + } + + /* Parse current-level from each node */ + snprintf(prop_name, MAX_PROP_SIZE, + "%s-current-level", vreg_name); + ret = of_property_read_u32(np, prop_name, &vreg->load_uA); + if (ret < 0) { + BT_PWR_DBG("%s property is not valid\n", prop_name); + vreg->load_uA = -1; + ret = 0; + } + + *vreg_data = vreg; + BT_PWR_DBG("%s: vol=[%d %d]uV, current=[%d]uA\n", + vreg->name, vreg->low_vol_level, + vreg->high_vol_level, + vreg->load_uA); + } else + BT_PWR_INFO("%s: is not provided in device tree", vreg_name); + +err: + return ret; +} + +static int bt_dt_parse_clk_info(struct device *dev, + struct bt_power_clk_data **clk_data) +{ + int ret = -EINVAL; + struct bt_power_clk_data *clk = NULL; + struct device_node *np = dev->of_node; + + BT_PWR_DBG(""); + + *clk_data = NULL; + if (of_parse_phandle(np, "clocks", 0)) { + clk = devm_kzalloc(dev, sizeof(*clk), GFP_KERNEL); + if (!clk) { + BT_PWR_ERR("No memory for clocks"); + ret = -ENOMEM; + goto err; + } + + /* Allocated 20 bytes size buffer for clock name string */ + clk->name = devm_kzalloc(dev, 20, GFP_KERNEL); + + /* Parse clock name from node */ + ret = of_property_read_string_index(np, "clock-names", 0, + &(clk->name)); + if (ret < 0) { + BT_PWR_ERR("reading \"clock-names\" failed"); + return ret; + } + + clk->clk = devm_clk_get(dev, clk->name); + if (IS_ERR(clk->clk)) { + ret = PTR_ERR(clk->clk); + BT_PWR_ERR("failed to get %s, ret (%d)", + clk->name, ret); + clk->clk = NULL; + return ret; + } + + *clk_data = clk; + } else { + BT_PWR_ERR("clocks is not provided in device tree"); + } + +err: + return ret; +} + +static int bt_power_populate_dt_pinfo(struct platform_device *pdev) +{ + int rc; + + BT_PWR_DBG(""); + + if (!bt_power_pdata) + return -ENOMEM; + + if (pdev->dev.of_node) { + bt_power_pdata->bt_gpio_sys_rst = + of_get_named_gpio(pdev->dev.of_node, + "qca,bt-reset-gpio", 0); + if (bt_power_pdata->bt_gpio_sys_rst < 0) + BT_PWR_ERR("bt-reset-gpio not provided in device tree"); + + rc = bt_dt_parse_vreg_info(&pdev->dev, + &bt_power_pdata->bt_vdd_core, + "qca,bt-vdd-core"); + if (rc < 0) + BT_PWR_ERR("bt-vdd-core not provided in device tree"); + + rc = bt_dt_parse_vreg_info(&pdev->dev, + &bt_power_pdata->bt_vdd_io, + "qca,bt-vdd-io"); + if (rc < 0) + BT_PWR_ERR("bt-vdd-io not provided in device tree"); + + rc = bt_dt_parse_vreg_info(&pdev->dev, + &bt_power_pdata->bt_vdd_xtal, + "qca,bt-vdd-xtal"); + if (rc < 0) + BT_PWR_ERR("bt-vdd-xtal not provided in device tree"); + + rc = bt_dt_parse_vreg_info(&pdev->dev, + &bt_power_pdata->bt_vdd_pa, + "qca,bt-vdd-pa"); + if (rc < 0) + BT_PWR_ERR("bt-vdd-pa not provided in device tree"); + + rc = bt_dt_parse_vreg_info(&pdev->dev, + &bt_power_pdata->bt_vdd_ldo, + "qca,bt-vdd-ldo"); + if (rc < 0) + BT_PWR_ERR("bt-vdd-ldo not provided in device tree"); + + rc = bt_dt_parse_vreg_info(&pdev->dev, + &bt_power_pdata->bt_chip_pwd, + "qca,bt-chip-pwd"); + if (rc < 0) + BT_PWR_ERR("bt-chip-pwd not provided in device tree"); + + rc = bt_dt_parse_clk_info(&pdev->dev, + &bt_power_pdata->bt_chip_clk); + if (rc < 0) + BT_PWR_ERR("clock not provided in device tree"); + } + + bt_power_pdata->bt_power_setup = bluetooth_power; + + return 0; +} + +static int bt_power_probe(struct platform_device *pdev) +{ + int ret = 0; + + dev_dbg(&pdev->dev, "%s\n", __func__); + + bt_power_pdata = + kzalloc(sizeof(struct bluetooth_power_platform_data), + GFP_KERNEL); + + if (!bt_power_pdata) { + BT_PWR_ERR("Failed to allocate memory"); + return -ENOMEM; + } + + if (pdev->dev.of_node) { + ret = bt_power_populate_dt_pinfo(pdev); + if (ret < 0) { + BT_PWR_ERR("Failed to populate device tree info"); + goto free_pdata; + } + pdev->dev.platform_data = bt_power_pdata; + } else if (pdev->dev.platform_data) { + /* Optional data set to default if not provided */ + if (!((struct bluetooth_power_platform_data *) + (pdev->dev.platform_data))->bt_power_setup) + ((struct bluetooth_power_platform_data *) + (pdev->dev.platform_data))->bt_power_setup = + bluetooth_power; + + memcpy(bt_power_pdata, pdev->dev.platform_data, + sizeof(struct bluetooth_power_platform_data)); + pwr_state = 0; + } else { + BT_PWR_ERR("Failed to get platform data"); + goto free_pdata; + } + + if (bluetooth_power_rfkill_probe(pdev) < 0) + goto free_pdata; + + btpdev = pdev; + + return 0; + +free_pdata: + kfree(bt_power_pdata); + return ret; +} + +static int bt_power_remove(struct platform_device *pdev) +{ + dev_dbg(&pdev->dev, "%s\n", __func__); + + bluetooth_power_rfkill_remove(pdev); + + if (bt_power_pdata->bt_chip_pwd->reg) + regulator_put(bt_power_pdata->bt_chip_pwd->reg); + + kfree(bt_power_pdata); + + return 0; +} + +int bt_register_slimdev(struct device *dev) +{ + BT_PWR_DBG(""); + if (!bt_power_pdata || (dev == NULL)) { + BT_PWR_ERR("Failed to allocate memory"); + return -EINVAL; + } + bt_power_pdata->slim_dev = dev; + return 0; +} + +static long bt_ioctl(struct file *file, unsigned int cmd, unsigned long arg) +{ + int ret = 0, pwr_cntrl = 0; + + switch (cmd) { + case BT_CMD_SLIM_TEST: + if (!bt_power_pdata->slim_dev) { + BT_PWR_ERR("slim_dev is null\n"); + return -EINVAL; + } + ret = btfm_slim_hw_init( + bt_power_pdata->slim_dev->platform_data + ); + break; + case BT_CMD_PWR_CTRL: + pwr_cntrl = (int)arg; + BT_PWR_ERR("BT_CMD_PWR_CTRL pwr_cntrl:%d", pwr_cntrl); + if (pwr_state != pwr_cntrl) { + ret = bluetooth_power(pwr_cntrl); + if (!ret) + pwr_state = pwr_cntrl; + } else { + BT_PWR_ERR("BT chip state is already :%d no change d\n" + , pwr_state); + ret = 0; + } + break; + default: + return -EINVAL; + } + return ret; +} + +static struct platform_driver bt_power_driver = { + .probe = bt_power_probe, + .remove = bt_power_remove, + .driver = { + .name = "bt_power", + .owner = THIS_MODULE, + .of_match_table = bt_power_match_table, + }, +}; + +static const struct file_operations bt_dev_fops = { + .owner = THIS_MODULE, + .unlocked_ioctl = bt_ioctl, + .compat_ioctl = bt_ioctl, +}; + +static int __init bluetooth_power_init(void) +{ + int ret; + + ret = platform_driver_register(&bt_power_driver); + + bt_major = register_chrdev(0, "bt", &bt_dev_fops); + if (bt_major < 0) { + BTFMSLIM_ERR("failed to allocate char dev\n"); + goto chrdev_unreg; + } + + bt_class = class_create(THIS_MODULE, "bt-dev"); + if (IS_ERR(bt_class)) { + BTFMSLIM_ERR("coudn't create class"); + goto chrdev_unreg; + } + + + if (device_create(bt_class, NULL, MKDEV(bt_major, 0), + NULL, "btpower") == NULL) { + BTFMSLIM_ERR("failed to allocate char dev\n"); + goto chrdev_unreg; + } + return 0; + +chrdev_unreg: + unregister_chrdev(bt_major, "bt"); + class_destroy(bt_class); + return ret; +} + +static void __exit bluetooth_power_exit(void) +{ + platform_driver_unregister(&bt_power_driver); +} + +MODULE_LICENSE("GPL v2"); +MODULE_DESCRIPTION("MSM Bluetooth power control driver"); + +module_init(bluetooth_power_init); +module_exit(bluetooth_power_exit); --- /dev/null 2019-10-24 16:47:25.704025805 +0200 +++ linux-4.4.115-fbx/drivers/bluetooth/btfm_slim.c 2019-01-22 16:16:22.931241227 +0100 @@ -0,0 +1,565 @@ +/* Copyright (c) 2017, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "btfm_slim.h" +#include "btfm_slim_wcn3990.h" + +int btfm_slim_write(struct btfmslim *btfmslim, + uint16_t reg, int bytes, void *src, uint8_t pgd) +{ + int ret, i; + struct slim_ele_access msg; + int slim_write_tries = SLIM_SLAVE_RW_MAX_TRIES; + + BTFMSLIM_DBG("Write to %s", pgd?"PGD":"IFD"); + msg.start_offset = SLIM_SLAVE_REG_OFFSET + reg; + msg.num_bytes = bytes; + msg.comp = NULL; + + for ( ; slim_write_tries != 0; slim_write_tries--) { + mutex_lock(&btfmslim->xfer_lock); + ret = slim_change_val_element(pgd ? btfmslim->slim_pgd : + &btfmslim->slim_ifd, &msg, src, bytes); + mutex_unlock(&btfmslim->xfer_lock); + if (ret == 0) + break; + usleep_range(5000, 5100); + } + + if (ret) { + BTFMSLIM_ERR("failed (%d)", ret); + return ret; + } + + for (i = 0; i < bytes; i++) + BTFMSLIM_DBG("Write 0x%02x to reg 0x%x", ((uint8_t *)src)[i], + reg + i); + return 0; +} + +int btfm_slim_write_pgd(struct btfmslim *btfmslim, + uint16_t reg, int bytes, void *src) +{ + return btfm_slim_write(btfmslim, reg, bytes, src, PGD); +} + +int btfm_slim_write_inf(struct btfmslim *btfmslim, + uint16_t reg, int bytes, void *src) +{ + return btfm_slim_write(btfmslim, reg, bytes, src, IFD); +} + +int btfm_slim_read(struct btfmslim *btfmslim, unsigned short reg, + int bytes, void *dest, uint8_t pgd) +{ + int ret, i; + struct slim_ele_access msg; + int slim_read_tries = SLIM_SLAVE_RW_MAX_TRIES; + + BTFMSLIM_DBG("Read from %s", pgd?"PGD":"IFD"); + msg.start_offset = SLIM_SLAVE_REG_OFFSET + reg; + msg.num_bytes = bytes; + msg.comp = NULL; + + for ( ; slim_read_tries != 0; slim_read_tries--) { + mutex_lock(&btfmslim->xfer_lock); + ret = slim_request_val_element(pgd ? btfmslim->slim_pgd : + &btfmslim->slim_ifd, &msg, dest, bytes); + mutex_unlock(&btfmslim->xfer_lock); + if (ret == 0) + break; + usleep_range(5000, 5100); + } + + if (ret) + BTFMSLIM_ERR("failed (%d)", ret); + + for (i = 0; i < bytes; i++) + BTFMSLIM_DBG("Read 0x%02x from reg 0x%x", ((uint8_t *)dest)[i], + reg + i); + + return 0; +} + +int btfm_slim_read_pgd(struct btfmslim *btfmslim, + uint16_t reg, int bytes, void *dest) +{ + return btfm_slim_read(btfmslim, reg, bytes, dest, PGD); +} + +int btfm_slim_read_inf(struct btfmslim *btfmslim, + uint16_t reg, int bytes, void *dest) +{ + return btfm_slim_read(btfmslim, reg, bytes, dest, IFD); +} + +int btfm_slim_enable_ch(struct btfmslim *btfmslim, struct btfmslim_ch *ch, + uint8_t rxport, uint32_t rates, uint8_t grp, uint8_t nchan) +{ + int ret, i; + struct slim_ch prop; + struct btfmslim_ch *chan = ch; + uint16_t ch_h[2]; + + if (!btfmslim || !ch) + return -EINVAL; + + BTFMSLIM_DBG("port: %d ch: %d", ch->port, ch->ch); + + /* Define the channel with below parameters */ + prop.prot = SLIM_AUTO_ISO; + prop.baser = SLIM_RATE_4000HZ; + prop.dataf = (rates == 48000) ? SLIM_CH_DATAF_NOT_DEFINED + : SLIM_CH_DATAF_LPCM_AUDIO; + prop.auxf = SLIM_CH_AUXF_NOT_APPLICABLE; + prop.ratem = (rates/4000); + prop.sampleszbits = 16; + + ch_h[0] = ch->ch_hdl; + ch_h[1] = (grp) ? (ch+1)->ch_hdl : 0; + + ret = slim_define_ch(btfmslim->slim_pgd, &prop, ch_h, nchan, grp, + &ch->grph); + if (ret < 0) { + BTFMSLIM_ERR("slim_define_ch failed ret[%d]", ret); + goto error; + } + + for (i = 0; i < nchan; i++, ch++) { + /* Enable port through registration setting */ + if (btfmslim->vendor_port_en) { + ret = btfmslim->vendor_port_en(btfmslim, ch->port, + rxport, 1); + if (ret < 0) { + BTFMSLIM_ERR("vendor_port_en failed ret[%d]", + ret); + goto error; + } + } + + if (rxport) { + BTFMSLIM_INFO("slim_connect_sink(port: %d, ch: %d)", + ch->port, ch->ch); + /* Connect Port with channel given by Machine driver*/ + ret = slim_connect_sink(btfmslim->slim_pgd, + &ch->port_hdl, 1, ch->ch_hdl); + if (ret < 0) { + BTFMSLIM_ERR("slim_connect_sink failed ret[%d]", + ret); + goto remove_channel; + } + } else { + BTFMSLIM_INFO("slim_connect_src(port: %d, ch: %d)", + ch->port, ch->ch); + /* Connect Port with channel given by Machine driver*/ + ret = slim_connect_src(btfmslim->slim_pgd, ch->port_hdl, + ch->ch_hdl); + if (ret < 0) { + BTFMSLIM_ERR("slim_connect_src failed ret[%d]", + ret); + goto remove_channel; + } + } + } + + /* Activate the channel immediately */ + BTFMSLIM_INFO( + "port: %d, ch: %d, grp: %d, ch->grph: 0x%x, ch_hdl: 0x%x", + chan->port, chan->ch, grp, chan->grph, chan->ch_hdl); + + ret = slim_control_ch(btfmslim->slim_pgd, (grp ? chan->grph : + chan->ch_hdl), SLIM_CH_ACTIVATE, true); + if (ret < 0) { + BTFMSLIM_ERR("slim_control_ch failed ret[%d]", ret); + goto remove_channel; + } + +error: + return ret; + +remove_channel: + /* Remove the channel immediately*/ + ret = slim_control_ch(btfmslim->slim_pgd, (grp ? ch->grph : ch->ch_hdl), + SLIM_CH_REMOVE, true); + if (ret < 0) + BTFMSLIM_ERR("slim_control_ch failed ret[%d]", ret); + + return ret; +} + +int btfm_slim_disable_ch(struct btfmslim *btfmslim, struct btfmslim_ch *ch, + uint8_t rxport, uint8_t grp, uint8_t nchan) +{ + int ret, i; + + if (!btfmslim || !ch) + return -EINVAL; + + BTFMSLIM_INFO("port:%d, grp: %d, ch->grph:0x%x, ch->ch_hdl:0x%x ", + ch->port, grp, ch->grph, ch->ch_hdl); + + /* Remove the channel immediately*/ + ret = slim_control_ch(btfmslim->slim_pgd, (grp ? ch->grph : ch->ch_hdl), + SLIM_CH_REMOVE, true); + if (ret < 0) { + BTFMSLIM_ERR("slim_control_ch failed ret[%d]", ret); + ret = slim_disconnect_ports(btfmslim->slim_pgd, + &ch->port_hdl, 1); + if (ret < 0) { + BTFMSLIM_ERR("slim_disconnect_ports failed ret[%d]", + ret); + goto error; + } + } + /* Disable port through registration setting */ + for (i = 0; i < nchan; i++, ch++) { + if (btfmslim->vendor_port_en) { + ret = btfmslim->vendor_port_en(btfmslim, ch->port, + rxport, 0); + if (ret < 0) { + BTFMSLIM_ERR("vendor_port_en failed ret[%d]", + ret); + break; + } + } + } + +error: + return ret; +} + +static int btfm_slim_get_logical_addr(struct slim_device *slim) +{ + int ret = 0; + const unsigned long timeout = jiffies + + msecs_to_jiffies(SLIM_SLAVE_PRESENT_TIMEOUT); + + do { + ret = slim_get_logical_addr(slim, slim->e_addr, + ARRAY_SIZE(slim->e_addr), &slim->laddr); + if (!ret) { + BTFMSLIM_DBG("Assigned l-addr: 0x%x", slim->laddr); + break; + } + /* Give SLIMBUS time to report present and be ready. */ + usleep_range(1000, 1100); + BTFMSLIM_DBG("retyring get logical addr"); + } while (time_before(jiffies, timeout)); + + return ret; +} + +static int btfm_slim_alloc_port(struct btfmslim *btfmslim) +{ + int ret = -EINVAL, i; + struct btfmslim_ch *rx_chs; + struct btfmslim_ch *tx_chs; + + if (!btfmslim) + return ret; + + rx_chs = btfmslim->rx_chs; + tx_chs = btfmslim->tx_chs; + + if (!rx_chs || !tx_chs) + return ret; + + BTFMSLIM_DBG("Rx: id\tname\tport\thdl\tch\tch_hdl"); + for (i = 0 ; (rx_chs->port != BTFM_SLIM_PGD_PORT_LAST) && + (i < BTFM_SLIM_NUM_CODEC_DAIS); i++, rx_chs++) { + + /* Get Rx port handler from slimbus driver based + * on port number + */ + ret = slim_get_slaveport(btfmslim->slim_pgd->laddr, + rx_chs->port, &rx_chs->port_hdl, SLIM_SINK); + if (ret < 0) { + BTFMSLIM_ERR("slave port failure port#%d - ret[%d]", + rx_chs->port, SLIM_SINK); + return ret; + } + BTFMSLIM_DBG(" %d\t%s\t%d\t%x\t%d\t%x", rx_chs->id, + rx_chs->name, rx_chs->port, rx_chs->port_hdl, + rx_chs->ch, rx_chs->ch_hdl); + } + + BTFMSLIM_DBG("Tx: id\tname\tport\thdl\tch\tch_hdl"); + for (i = 0; (tx_chs->port != BTFM_SLIM_PGD_PORT_LAST) && + (i < BTFM_SLIM_NUM_CODEC_DAIS); i++, tx_chs++) { + + /* Get Tx port handler from slimbus driver based + * on port number + */ + ret = slim_get_slaveport(btfmslim->slim_pgd->laddr, + tx_chs->port, &tx_chs->port_hdl, SLIM_SRC); + if (ret < 0) { + BTFMSLIM_ERR("slave port failure port#%d - ret[%d]", + tx_chs->port, SLIM_SRC); + return ret; + } + BTFMSLIM_DBG(" %d\t%s\t%d\t%x\t%d\t%x", tx_chs->id, + tx_chs->name, tx_chs->port, tx_chs->port_hdl, + tx_chs->ch, tx_chs->ch_hdl); + } + return ret; +} + +int btfm_slim_hw_init(struct btfmslim *btfmslim) +{ + int ret; + + BTFMSLIM_DBG(""); + if (!btfmslim) + return -EINVAL; + + if (btfmslim->enabled) { + BTFMSLIM_DBG("Already enabled"); + return 0; + } + mutex_lock(&btfmslim->io_lock); + + /* Assign Logical Address for PGD (Ported Generic Device) + * enumeration address + */ + ret = btfm_slim_get_logical_addr(btfmslim->slim_pgd); + if (ret) { + BTFMSLIM_ERR("failed to get slimbus %s logical address: %d", + btfmslim->slim_pgd->name, ret); + goto error; + } + + /* Assign Logical Address for Ported Generic Device + * enumeration address + */ + ret = btfm_slim_get_logical_addr(&btfmslim->slim_ifd); + if (ret) { + BTFMSLIM_ERR("failed to get slimbus %s logical address: %d", + btfmslim->slim_ifd.name, ret); + goto error; + } + + /* Allocate ports with logical address to get port handler from + * slimbus driver + */ + ret = btfm_slim_alloc_port(btfmslim); + if (ret) + goto error; + + /* Start vendor specific initialization and get port information */ + if (btfmslim->vendor_init) + ret = btfmslim->vendor_init(btfmslim); + + /* Only when all registers read/write successfully, it set to + * enabled status + */ + btfmslim->enabled = 1; +error: + mutex_unlock(&btfmslim->io_lock); + return ret; +} + + +int btfm_slim_hw_deinit(struct btfmslim *btfmslim) +{ + int ret = 0; + + if (!btfmslim) + return -EINVAL; + + if (!btfmslim->enabled) { + BTFMSLIM_DBG("Already disabled"); + return 0; + } + mutex_lock(&btfmslim->io_lock); + btfmslim->enabled = 0; + mutex_unlock(&btfmslim->io_lock); + return ret; +} + +static int btfm_slim_get_dt_info(struct btfmslim *btfmslim) +{ + int ret = 0; + struct slim_device *slim = btfmslim->slim_pgd; + struct slim_device *slim_ifd = &btfmslim->slim_ifd; + struct property *prop; + + if (!slim || !slim_ifd) + return -EINVAL; + + if (slim->dev.of_node) { + BTFMSLIM_DBG("Platform data from device tree (%s)", + slim->name); + ret = of_property_read_string(slim->dev.of_node, + "qcom,btfm-slim-ifd", &slim_ifd->name); + if (ret) { + BTFMSLIM_ERR("Looking up %s property in node %s failed", + "qcom,btfm-slim-ifd", + slim->dev.of_node->full_name); + return -ENODEV; + } + BTFMSLIM_DBG("qcom,btfm-slim-ifd (%s)", slim_ifd->name); + + prop = of_find_property(slim->dev.of_node, + "qcom,btfm-slim-ifd-elemental-addr", NULL); + if (!prop) { + BTFMSLIM_ERR("Looking up %s property in node %s failed", + "qcom,btfm-slim-ifd-elemental-addr", + slim->dev.of_node->full_name); + return -ENODEV; + } else if (prop->length != 6) { + BTFMSLIM_ERR( + "invalid codec slim ifd addr. addr length= %d", + prop->length); + return -ENODEV; + } + memcpy(slim_ifd->e_addr, prop->value, 6); + BTFMSLIM_DBG( + "PGD Enum Addr: %.02x:%.02x:%.02x:%.02x:%.02x: %.02x", + slim->e_addr[0], slim->e_addr[1], slim->e_addr[2], + slim->e_addr[3], slim->e_addr[4], slim->e_addr[5]); + BTFMSLIM_DBG( + "IFD Enum Addr: %.02x:%.02x:%.02x:%.02x:%.02x: %.02x", + slim_ifd->e_addr[0], slim_ifd->e_addr[1], + slim_ifd->e_addr[2], slim_ifd->e_addr[3], + slim_ifd->e_addr[4], slim_ifd->e_addr[5]); + } else { + BTFMSLIM_ERR("Platform data is not valid"); + } + + return ret; +} + +static int btfm_slim_probe(struct slim_device *slim) +{ + int ret = 0; + struct btfmslim *btfm_slim; + + BTFMSLIM_DBG(""); + if (!slim->ctrl) + return -EINVAL; + + /* Allocation btfmslim data pointer */ + btfm_slim = kzalloc(sizeof(struct btfmslim), GFP_KERNEL); + if (btfm_slim == NULL) { + BTFMSLIM_ERR("error, allocation failed"); + return -ENOMEM; + } + /* BTFM Slimbus driver control data configuration */ + btfm_slim->slim_pgd = slim; + + /* Assign vendor specific function */ + btfm_slim->rx_chs = SLIM_SLAVE_RXPORT; + btfm_slim->tx_chs = SLIM_SLAVE_TXPORT; + btfm_slim->vendor_init = SLIM_SLAVE_INIT; + btfm_slim->vendor_port_en = SLIM_SLAVE_PORT_EN; + + /* Created Mutex for slimbus data transfer */ + mutex_init(&btfm_slim->io_lock); + mutex_init(&btfm_slim->xfer_lock); + + /* Get Device tree node for Interface Device enumeration address */ + ret = btfm_slim_get_dt_info(btfm_slim); + if (ret) + goto dealloc; + + /* Add Interface Device for slimbus driver */ + ret = slim_add_device(btfm_slim->slim_pgd->ctrl, &btfm_slim->slim_ifd); + if (ret) { + BTFMSLIM_ERR("error, adding SLIMBUS device failed"); + goto dealloc; + } + + /* Platform driver data allocation */ + slim->dev.platform_data = btfm_slim; + + /* Driver specific data allocation */ + btfm_slim->dev = &slim->dev; + ret = btfm_slim_register_codec(&slim->dev); + ret = bt_register_slimdev(&slim->dev); + return ret; + +dealloc: + mutex_destroy(&btfm_slim->io_lock); + mutex_destroy(&btfm_slim->xfer_lock); + kfree(btfm_slim); + return ret; +} +static int btfm_slim_remove(struct slim_device *slim) +{ + struct btfmslim *btfm_slim = slim->dev.platform_data; + + BTFMSLIM_DBG(""); + mutex_destroy(&btfm_slim->io_lock); + mutex_destroy(&btfm_slim->xfer_lock); + snd_soc_unregister_codec(&slim->dev); + + BTFMSLIM_DBG("slim_remove_device() - btfm_slim->slim_ifd"); + slim_remove_device(&btfm_slim->slim_ifd); + + BTFMSLIM_DBG("slim_remove_device() - btfm_slim->slim_pgd"); + slim_remove_device(slim); + + kfree(btfm_slim); + return 0; +} + +static const struct slim_device_id btfm_slim_id[] = { + {SLIM_SLAVE_COMPATIBLE_STR, 0}, + {} +}; + +static struct slim_driver btfm_slim_driver = { + .driver = { + .name = "btfmslim-driver", + .owner = THIS_MODULE, + }, + .probe = btfm_slim_probe, + .remove = btfm_slim_remove, + .id_table = btfm_slim_id +}; + +static int __init btfm_slim_init(void) +{ + int ret; + + BTFMSLIM_DBG(""); + ret = slim_driver_register(&btfm_slim_driver); + if (ret) + BTFMSLIM_ERR("Failed to register slimbus driver: %d", ret); + return ret; +} + +static void __exit btfm_slim_exit(void) +{ + BTFMSLIM_DBG(""); + slim_driver_unregister(&btfm_slim_driver); +} + +module_init(btfm_slim_init); +module_exit(btfm_slim_exit); + +MODULE_LICENSE("GPL v2"); +MODULE_DESCRIPTION("BTFM Slimbus Slave driver"); --- /dev/null 2019-10-24 16:47:25.704025805 +0200 +++ linux-4.4.115-fbx/drivers/bluetooth/btfm_slim_codec.c 2019-01-22 16:16:22.931241227 +0100 @@ -0,0 +1,434 @@ +/* Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "btfm_slim.h" + +static int bt_soc_enable_status; + + +static int btfm_slim_codec_write(struct snd_soc_codec *codec, unsigned int reg, + unsigned int value) +{ + return 0; +} + +static unsigned int btfm_slim_codec_read(struct snd_soc_codec *codec, + unsigned int reg) +{ + return 0; +} + +static int bt_soc_status_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + ucontrol->value.integer.value[0] = bt_soc_enable_status; + return 1; +} + +static int bt_soc_status_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + return 1; +} + +static const struct snd_kcontrol_new status_controls[] = { + SOC_SINGLE_EXT("BT SOC status", 0, 0, 1, 0, + bt_soc_status_get, + bt_soc_status_put) + +}; + + +static int btfm_slim_codec_probe(struct snd_soc_codec *codec) +{ + snd_soc_add_codec_controls(codec, status_controls, + ARRAY_SIZE(status_controls)); + return 0; +} + +static int btfm_slim_codec_remove(struct snd_soc_codec *codec) +{ + return 0; +} + +static int btfm_slim_dai_startup(struct snd_pcm_substream *substream, + struct snd_soc_dai *dai) +{ + int ret; + struct btfmslim *btfmslim = dai->dev->platform_data; + + BTFMSLIM_DBG("substream = %s stream = %d dai->name = %s", + substream->name, substream->stream, dai->name); + ret = btfm_slim_hw_init(btfmslim); + return ret; +} + +static void btfm_slim_dai_shutdown(struct snd_pcm_substream *substream, + struct snd_soc_dai *dai) +{ + int i; + struct btfmslim *btfmslim = dai->dev->platform_data; + struct btfmslim_ch *ch; + uint8_t rxport, grp = false, nchan = 1; + + BTFMSLIM_DBG("dai->name: %s, dai->id: %d, dai->rate: %d", dai->name, + dai->id, dai->rate); + + switch (dai->id) { + case BTFM_FM_SLIM_TX: + grp = true; nchan = 2; + ch = btfmslim->tx_chs; + rxport = 0; + break; + case BTFM_BT_SCO_SLIM_TX: + ch = btfmslim->tx_chs; + rxport = 0; + break; + case BTFM_BT_SCO_A2DP_SLIM_RX: + case BTFM_BT_SPLIT_A2DP_SLIM_RX: + ch = btfmslim->rx_chs; + rxport = 1; + break; + case BTFM_SLIM_NUM_CODEC_DAIS: + default: + BTFMSLIM_ERR("dai->id is invalid:%d", dai->id); + return; + } + + /* Search for dai->id matched port handler */ + for (i = 0; (i < BTFM_SLIM_NUM_CODEC_DAIS) && + (ch->id != BTFM_SLIM_NUM_CODEC_DAIS) && + (ch->id != dai->id); ch++, i++) + ; + + if ((ch->port == BTFM_SLIM_PGD_PORT_LAST) || + (ch->id == BTFM_SLIM_NUM_CODEC_DAIS)) { + BTFMSLIM_ERR("ch is invalid!!"); + return; + } + + btfm_slim_disable_ch(btfmslim, ch, rxport, grp, nchan); + btfm_slim_hw_deinit(btfmslim); +} + +static int btfm_slim_dai_hw_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params, + struct snd_soc_dai *dai) +{ + BTFMSLIM_DBG("dai->name = %s DAI-ID %x rate %d num_ch %d", + dai->name, dai->id, params_rate(params), + params_channels(params)); + + return 0; +} + +int btfm_slim_dai_prepare(struct snd_pcm_substream *substream, + struct snd_soc_dai *dai) +{ + int i, ret = -EINVAL; + struct btfmslim *btfmslim = dai->dev->platform_data; + struct btfmslim_ch *ch; + uint8_t rxport, grp = false, nchan = 1; + bt_soc_enable_status = 0; + + BTFMSLIM_DBG("dai->name: %s, dai->id: %d, dai->rate: %d", dai->name, + dai->id, dai->rate); + + /* save sample rate */ + btfmslim->sample_rate = dai->rate; + + switch (dai->id) { + case BTFM_FM_SLIM_TX: + grp = true; nchan = 2; + ch = btfmslim->tx_chs; + rxport = 0; + break; + case BTFM_BT_SCO_SLIM_TX: + ch = btfmslim->tx_chs; + rxport = 0; + break; + case BTFM_BT_SCO_A2DP_SLIM_RX: + case BTFM_BT_SPLIT_A2DP_SLIM_RX: + ch = btfmslim->rx_chs; + rxport = 1; + break; + case BTFM_SLIM_NUM_CODEC_DAIS: + default: + BTFMSLIM_ERR("dai->id is invalid:%d", dai->id); + return ret; + } + + /* Search for dai->id matched port handler */ + for (i = 0; (i < BTFM_SLIM_NUM_CODEC_DAIS) && + (ch->id != BTFM_SLIM_NUM_CODEC_DAIS) && + (ch->id != dai->id); ch++, i++) + ; + + if ((ch->port == BTFM_SLIM_PGD_PORT_LAST) || + (ch->id == BTFM_SLIM_NUM_CODEC_DAIS)) { + BTFMSLIM_ERR("ch is invalid!!"); + return ret; + } + + ret = btfm_slim_enable_ch(btfmslim, ch, rxport, dai->rate, grp, nchan); + + /* save the enable channel status */ + if (ret == 0) + bt_soc_enable_status = 1; + return ret; +} + +/* This function will be called once during boot up */ +static int btfm_slim_dai_set_channel_map(struct snd_soc_dai *dai, + unsigned int tx_num, unsigned int *tx_slot, + unsigned int rx_num, unsigned int *rx_slot) +{ + int ret = -EINVAL, i; + struct btfmslim *btfmslim = dai->dev->platform_data; + struct btfmslim_ch *rx_chs; + struct btfmslim_ch *tx_chs; + + BTFMSLIM_DBG(""); + + if (!btfmslim) + return ret; + + rx_chs = btfmslim->rx_chs; + tx_chs = btfmslim->tx_chs; + + if (!rx_chs || !tx_chs) + return ret; + + BTFMSLIM_DBG("Rx: id\tname\tport\thdl\tch\tch_hdl"); + for (i = 0; (rx_chs->port != BTFM_SLIM_PGD_PORT_LAST) && (i < rx_num); + i++, rx_chs++) { + /* Set Rx Channel number from machine driver and + * get channel handler from slimbus driver + */ + rx_chs->ch = *(uint8_t *)(rx_slot + i); + ret = slim_query_ch(btfmslim->slim_pgd, rx_chs->ch, + &rx_chs->ch_hdl); + if (ret < 0) { + BTFMSLIM_ERR("slim_query_ch failure ch#%d - ret[%d]", + rx_chs->ch, ret); + goto error; + } + BTFMSLIM_DBG(" %d\t%s\t%d\t%x\t%d\t%x", rx_chs->id, + rx_chs->name, rx_chs->port, rx_chs->port_hdl, + rx_chs->ch, rx_chs->ch_hdl); + } + + BTFMSLIM_DBG("Tx: id\tname\tport\thdl\tch\tch_hdl"); + for (i = 0; (tx_chs->port != BTFM_SLIM_PGD_PORT_LAST) && (i < tx_num); + i++, tx_chs++) { + /* Set Tx Channel number from machine driver and + * get channel handler from slimbus driver + */ + tx_chs->ch = *(uint8_t *)(tx_slot + i); + ret = slim_query_ch(btfmslim->slim_pgd, tx_chs->ch, + &tx_chs->ch_hdl); + if (ret < 0) { + BTFMSLIM_ERR("slim_query_ch failure ch#%d - ret[%d]", + tx_chs->ch, ret); + goto error; + } + BTFMSLIM_DBG(" %d\t%s\t%d\t%x\t%d\t%x", tx_chs->id, + tx_chs->name, tx_chs->port, tx_chs->port_hdl, + tx_chs->ch, tx_chs->ch_hdl); + } + +error: + return ret; +} + +static int btfm_slim_dai_get_channel_map(struct snd_soc_dai *dai, + unsigned int *tx_num, unsigned int *tx_slot, + unsigned int *rx_num, unsigned int *rx_slot) +{ + int i, ret = -EINVAL, *slot = NULL, j = 0, num = 1; + struct btfmslim *btfmslim = dai->dev->platform_data; + struct btfmslim_ch *ch = NULL; + + if (!btfmslim) + return ret; + + switch (dai->id) { + case BTFM_FM_SLIM_TX: + num = 2; + case BTFM_BT_SCO_SLIM_TX: + if (!tx_slot || !tx_num) { + BTFMSLIM_ERR("Invalid tx_slot %p or tx_num %p", + tx_slot, tx_num); + return -EINVAL; + } + ch = btfmslim->tx_chs; + if (!ch) + return -EINVAL; + slot = tx_slot; + *rx_slot = 0; + *tx_num = num; + *rx_num = 0; + break; + case BTFM_BT_SCO_A2DP_SLIM_RX: + case BTFM_BT_SPLIT_A2DP_SLIM_RX: + if (!rx_slot || !rx_num) { + BTFMSLIM_ERR("Invalid rx_slot %p or rx_num %p", + rx_slot, rx_num); + return -EINVAL; + } + ch = btfmslim->rx_chs; + if (!ch) + return -EINVAL; + slot = rx_slot; + *tx_slot = 0; + *tx_num = 0; + *rx_num = num; + break; + default: + BTFMSLIM_ERR("Unsupported DAI %d", dai->id); + return -EINVAL; + } + + do { + for (i = 0; (i < BTFM_SLIM_NUM_CODEC_DAIS) && (ch->id != + BTFM_SLIM_NUM_CODEC_DAIS) && (ch->id != dai->id); + ch++, i++) + ; + + if (ch->id == BTFM_SLIM_NUM_CODEC_DAIS || + i == BTFM_SLIM_NUM_CODEC_DAIS) { + BTFMSLIM_ERR( + "No channel has been allocated for dai (%d)", + dai->id); + return -EINVAL; + } + + *(slot + j) = ch->ch; + BTFMSLIM_DBG("id:%d, port:%d, ch:%d, slot: %d", ch->id, + ch->port, ch->ch, *(slot + j)); + + /* In case it has mulitiple channels */ + if (++j < num) + ch++; + } while (j < num); + + return 0; +} + +static struct snd_soc_dai_ops btfmslim_dai_ops = { + .startup = btfm_slim_dai_startup, + .shutdown = btfm_slim_dai_shutdown, + .hw_params = btfm_slim_dai_hw_params, + .prepare = btfm_slim_dai_prepare, + .set_channel_map = btfm_slim_dai_set_channel_map, + .get_channel_map = btfm_slim_dai_get_channel_map, +}; + +static struct snd_soc_dai_driver btfmslim_dai[] = { + { /* FM Audio data multiple channel : FM -> qdsp */ + .name = "btfm_fm_slim_tx", + .id = BTFM_FM_SLIM_TX, + .capture = { + .stream_name = "FM TX Capture", + .rates = SNDRV_PCM_RATE_48000, /* 48 KHz */ + .formats = SNDRV_PCM_FMTBIT_S16_LE, /* 16 bits */ + .rate_max = 48000, + .rate_min = 48000, + .channels_min = 1, + .channels_max = 2, + }, + .ops = &btfmslim_dai_ops, + }, + { /* Bluetooth SCO voice uplink: bt -> modem */ + .name = "btfm_bt_sco_slim_tx", + .id = BTFM_BT_SCO_SLIM_TX, + .capture = { + .stream_name = "SCO TX Capture", + /* 8 KHz or 16 KHz */ + .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000, + .formats = SNDRV_PCM_FMTBIT_S16_LE, /* 16 bits */ + .rate_max = 16000, + .rate_min = 8000, + .channels_min = 1, + .channels_max = 1, + }, + .ops = &btfmslim_dai_ops, + }, + { /* Bluetooth SCO voice downlink: modem -> bt or A2DP Playback */ + .name = "btfm_bt_sco_a2dp_slim_rx", + .id = BTFM_BT_SCO_A2DP_SLIM_RX, + .playback = { + .stream_name = "SCO A2DP RX Playback", + .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 + | SNDRV_PCM_RATE_48000, /* 8 or 16 or 48 Khz*/ + .formats = SNDRV_PCM_FMTBIT_S16_LE, /* 16 bits */ + .rate_max = 48000, + .rate_min = 8000, + .channels_min = 1, + .channels_max = 1, + }, + .ops = &btfmslim_dai_ops, + }, + { /* Bluetooth Split A2DP data: qdsp -> bt */ + .name = "btfm_bt_split_a2dp_slim_rx", + .id = BTFM_BT_SPLIT_A2DP_SLIM_RX, + .playback = { + .stream_name = "SPLIT A2DP Playback", + .rates = SNDRV_PCM_RATE_48000, /* 48 KHz */ + .formats = SNDRV_PCM_FMTBIT_S16_LE, /* 16 bits */ + .rate_max = 48000, + .rate_min = 48000, + .channels_min = 1, + .channels_max = 1, + }, + .ops = &btfmslim_dai_ops, + }, +}; + +static struct snd_soc_codec_driver btfmslim_codec = { + .probe = btfm_slim_codec_probe, + .remove = btfm_slim_codec_remove, + .read = btfm_slim_codec_read, + .write = btfm_slim_codec_write, +}; + +int btfm_slim_register_codec(struct device *dev) +{ + int ret = 0; + + BTFMSLIM_DBG(""); + /* Register Codec driver */ + ret = snd_soc_register_codec(dev, &btfmslim_codec, + btfmslim_dai, ARRAY_SIZE(btfmslim_dai)); + + if (ret) + BTFMSLIM_ERR("failed to register codec (%d)", ret); + + return ret; +} + +MODULE_DESCRIPTION("BTFM Slimbus Codec driver"); +MODULE_LICENSE("GPL v2"); --- /dev/null 2019-10-24 16:47:25.704025805 +0200 +++ linux-4.4.115-fbx/drivers/bluetooth/btfm_slim.h 2019-01-22 16:16:22.931241227 +0100 @@ -0,0 +1,165 @@ +/* Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#ifndef BTFM_SLIM_H +#define BTFM_SLIM_H +#include + +#define BTFMSLIM_DBG(fmt, arg...) pr_debug("%s: " fmt "\n", __func__, ## arg) +#define BTFMSLIM_INFO(fmt, arg...) pr_info("%s: " fmt "\n", __func__, ## arg) +#define BTFMSLIM_ERR(fmt, arg...) pr_err("%s: " fmt "\n", __func__, ## arg) + +/* Vendor specific defines + * This should redefines in slimbus slave specific header +*/ +#define SLIM_SLAVE_COMPATIBLE_STR "btfmslim_slave" +#define SLIM_SLAVE_REG_OFFSET 0x0000 +#define SLIM_SLAVE_RXPORT NULL +#define SLIM_SLAVE_TXPORT NULL +#define SLIM_SLAVE_INIT NULL +#define SLIM_SLAVE_PORT_EN NULL + +/* Misc defines */ +#define SLIM_SLAVE_RW_MAX_TRIES 3 +#define SLIM_SLAVE_PRESENT_TIMEOUT 100 + +#define PGD 1 +#define IFD 0 + + +/* Codec driver defines */ +enum { + BTFM_FM_SLIM_TX = 0, + BTFM_BT_SCO_SLIM_TX, + BTFM_BT_SCO_A2DP_SLIM_RX, + BTFM_BT_SPLIT_A2DP_SLIM_RX, + BTFM_SLIM_NUM_CODEC_DAIS +}; + +/* Slimbus Port defines - This should be redefined in specific device file */ +#define BTFM_SLIM_PGD_PORT_LAST 0xFF + +struct btfmslim_ch { + int id; + char *name; + uint32_t port_hdl; /* slimbus port handler */ + uint16_t port; /* slimbus port number */ + + uint8_t ch; /* slimbus channel number */ + uint16_t ch_hdl; /* slimbus channel handler */ + uint16_t grph; /* slimbus group channel handler */ +}; + +struct btfmslim { + struct device *dev; + struct slim_device *slim_pgd; + struct slim_device slim_ifd; + struct mutex io_lock; + struct mutex xfer_lock; + uint8_t enabled; + + uint32_t num_rx_port; + uint32_t num_tx_port; + uint32_t sample_rate; + + struct btfmslim_ch *rx_chs; + struct btfmslim_ch *tx_chs; + + int (*vendor_init)(struct btfmslim *btfmslim); + int (*vendor_port_en)(struct btfmslim *btfmslim, uint8_t port_num, + uint8_t rxport, uint8_t enable); +}; + +/** + * btfm_slim_hw_init: Initialize slimbus slave device + * Returns: + * 0: Success + * else: Fail + */ +int btfm_slim_hw_init(struct btfmslim *btfmslim); + +/** + * btfm_slim_hw_deinit: Deinitialize slimbus slave device + * Returns: + * 0: Success + * else: Fail + */ +int btfm_slim_hw_deinit(struct btfmslim *btfmslim); + +/** + * btfm_slim_write: write value to pgd or ifd device + * @btfmslim: slimbus slave device data pointer. + * @reg: slimbus slave register address + * @bytes: length of data + * @src: data pointer to write + * @pgd: selection for device: either PGD or IFD + * Returns: + * -EINVAL + * -ETIMEDOUT + * -ENOMEM + */ +int btfm_slim_write(struct btfmslim *btfmslim, + uint16_t reg, int bytes, void *src, uint8_t pgd); + + + +/** + * btfm_slim_read: read value from pgd or ifd device + * @btfmslim: slimbus slave device data pointer. + * @reg: slimbus slave register address + * @bytes: length of data + * @dest: data pointer to read + * @pgd: selection for device: either PGD or IFD + * Returns: + * -EINVAL + * -ETIMEDOUT + * -ENOMEM + */ +int btfm_slim_read(struct btfmslim *btfmslim, + uint16_t reg, int bytes, void *dest, uint8_t pgd); + + +/** + * btfm_slim_enable_ch: enable channel for slimbus slave port + * @btfmslim: slimbus slave device data pointer. + * @ch: slimbus slave channel pointer + * @rxport: rxport or txport + * Returns: + * -EINVAL + * -ETIMEDOUT + * -ENOMEM + */ +int btfm_slim_enable_ch(struct btfmslim *btfmslim, + struct btfmslim_ch *ch, uint8_t rxport, uint32_t rates, + uint8_t grp, uint8_t nchan); + +/** + * btfm_slim_disable_ch: disable channel for slimbus slave port + * @btfmslim: slimbus slave device data pointer. + * @ch: slimbus slave channel pointer + * @rxport: rxport or txport + * Returns: + * -EINVAL + * -ETIMEDOUT + * -ENOMEM + */ +int btfm_slim_disable_ch(struct btfmslim *btfmslim, + struct btfmslim_ch *ch, uint8_t rxport, uint8_t grp, uint8_t nchan); + +/** + * btfm_slim_register_codec: Register codec driver in slimbus device node + * @dev: device node + * Returns: + * -ENOMEM + * 0 +*/ +int btfm_slim_register_codec(struct device *dev); +#endif /* BTFM_SLIM_H */ --- /dev/null 2019-10-24 16:47:25.704025805 +0200 +++ linux-4.4.115-fbx/drivers/bluetooth/btfm_slim_wcn3990.c 2019-01-22 16:16:22.931241227 +0100 @@ -0,0 +1,176 @@ +/* Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include +#include "btfm_slim.h" +#include "btfm_slim_wcn3990.h" + +/* WCN3990 Port assignment */ +struct btfmslim_ch wcn3990_rxport[] = { + {.id = BTFM_BT_SCO_A2DP_SLIM_RX, .name = "SCO_A2P_Rx", + .port = CHRK_SB_PGD_PORT_RX_SCO}, + {.id = BTFM_BT_SPLIT_A2DP_SLIM_RX, .name = "A2P_Rx", + .port = CHRK_SB_PGD_PORT_RX_A2P}, + {.id = BTFM_SLIM_NUM_CODEC_DAIS, .name = "", + .port = BTFM_SLIM_PGD_PORT_LAST}, +}; + +struct btfmslim_ch wcn3990_txport[] = { + {.id = BTFM_FM_SLIM_TX, .name = "FM_Tx1", + .port = CHRK_SB_PGD_PORT_TX1_FM}, + {.id = BTFM_FM_SLIM_TX, .name = "FM_Tx2", + .port = CHRK_SB_PGD_PORT_TX2_FM}, + {.id = BTFM_BT_SCO_SLIM_TX, .name = "SCO_Tx", + .port = CHRK_SB_PGD_PORT_TX_SCO}, + {.id = BTFM_SLIM_NUM_CODEC_DAIS, .name = "", + .port = BTFM_SLIM_PGD_PORT_LAST}, +}; + +/* Function description */ +int btfm_slim_chrk_hw_init(struct btfmslim *btfmslim) +{ + int ret = 0; + uint8_t reg_val; + uint16_t reg; + + BTFMSLIM_DBG(""); + + if (!btfmslim) + return -EINVAL; + + /* Get SB_SLAVE_HW_REV_MSB value*/ + reg = CHRK_SB_SLAVE_HW_REV_MSB; + ret = btfm_slim_read(btfmslim, reg, 1, ®_val, IFD); + if (ret) { + BTFMSLIM_ERR("failed to read (%d) reg 0x%x", ret, reg); + goto error; + } + BTFMSLIM_DBG("Major Rev: 0x%x, Minor Rev: 0x%x", + (reg_val & 0xF0) >> 4, (reg_val & 0x0F)); + + /* Get SB_SLAVE_HW_REV_LSB value*/ + reg = CHRK_SB_SLAVE_HW_REV_LSB; + ret = btfm_slim_read(btfmslim, reg, 1, ®_val, IFD); + if (ret) { + BTFMSLIM_ERR("failed to read (%d) reg 0x%x", ret, reg); + goto error; + } + BTFMSLIM_DBG("Step Rev: 0x%x", reg_val); + +error: + return ret; +} + +static inline int is_fm_port(uint8_t port_num) +{ + if (port_num == CHRK_SB_PGD_PORT_TX1_FM || + port_num == CHRK_SB_PGD_PORT_TX2_FM) + return 1; + else + return 0; +} + +int btfm_slim_chrk_enable_port(struct btfmslim *btfmslim, uint8_t port_num, + uint8_t rxport, uint8_t enable) +{ + int ret = 0; + uint8_t reg_val = 0, en; + uint8_t port_bit = 0; + uint16_t reg; + + BTFMSLIM_DBG("port(%d) enable(%d)", port_num, enable); + + if (rxport) { + if (enable) { + /* For SCO Rx, A2DP Rx */ + reg_val = 0x1; + port_bit = port_num - 0x10; + reg = CHRK_SB_PGD_RX_PORTn_MULTI_CHNL_0(port_bit); + BTFMSLIM_DBG("writing reg_val (%d) to reg(%x)", + reg_val, reg); + ret = btfm_slim_write(btfmslim, reg, 1, ®_val, IFD); + if (ret) { + BTFMSLIM_ERR("failed to write (%d) reg 0x%x", + ret, reg); + goto error; + } + } + /* Port enable */ + reg = CHRK_SB_PGD_PORT_RX_CFGN(port_num - 0x10); + goto enable_disable_rxport; + } + if (!enable) + goto enable_disable_txport; + + /* txport */ + /* Multiple Channel Setting */ + if (is_fm_port(port_num)) { + reg_val = (0x1 << CHRK_SB_PGD_PORT_TX1_FM) | + (0x1 << CHRK_SB_PGD_PORT_TX2_FM); + reg = CHRK_SB_PGD_TX_PORTn_MULTI_CHNL_0(port_num); + ret = btfm_slim_write(btfmslim, reg, 1, ®_val, IFD); + if (ret) { + BTFMSLIM_ERR("failed to write (%d) reg 0x%x", + ret, reg); + goto error; + } + } else if (port_num == CHRK_SB_PGD_PORT_TX_SCO) { + /* SCO Tx */ + reg_val = 0x1 << CHRK_SB_PGD_PORT_TX_SCO; + reg = CHRK_SB_PGD_TX_PORTn_MULTI_CHNL_0(port_num); + BTFMSLIM_DBG("writing reg_val (%d) to reg(%x)", + reg_val, reg); + ret = btfm_slim_write(btfmslim, reg, 1, ®_val, IFD); + if (ret) { + BTFMSLIM_ERR("failed to write (%d) reg 0x%x", + ret, reg); + goto error; + } + } + + /* Enable Tx port hw auto recovery for underrun or overrun error */ + reg_val = (CHRK_ENABLE_OVERRUN_AUTO_RECOVERY | + CHRK_ENABLE_UNDERRUN_AUTO_RECOVERY); + reg = CHRK_SB_PGD_PORT_TX_OR_UR_CFGN(port_num); + ret = btfm_slim_write(btfmslim, reg, 1, ®_val, IFD); + if (ret) { + BTFMSLIM_ERR("failed to write (%d) reg 0x%x", ret, reg); + goto error; + } + +enable_disable_txport: + /* Port enable */ + reg = CHRK_SB_PGD_PORT_TX_CFGN(port_num); + +enable_disable_rxport: + if (enable) + en = CHRK_SB_PGD_PORT_ENABLE; + else + en = CHRK_SB_PGD_PORT_DISABLE; + + if (is_fm_port(port_num)) + reg_val = en | CHRK_SB_PGD_PORT_WM_L8; + else if (port_num == CHRK_SB_PGD_PORT_TX_SCO) + reg_val = enable ? en | CHRK_SB_PGD_PORT_WM_L1 : en; + else + reg_val = enable ? en | CHRK_SB_PGD_PORT_WM_LB : en; + + if (enable && port_num == CHRK_SB_PGD_PORT_TX_SCO) + BTFMSLIM_INFO("programming SCO Tx with reg_val %d to reg 0x%x", + reg_val, reg); + + ret = btfm_slim_write(btfmslim, reg, 1, ®_val, IFD); + if (ret) + BTFMSLIM_ERR("failed to write (%d) reg 0x%x", ret, reg); + +error: + return ret; +} --- /dev/null 2019-10-24 16:47:25.704025805 +0200 +++ linux-4.4.115-fbx/drivers/bluetooth/btfm_slim_wcn3990.h 2019-01-22 16:16:22.931241227 +0100 @@ -0,0 +1,141 @@ +/* Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#ifndef BTFM_SLIM_WCN3990_H +#define BTFM_SLIM_WCN3990_H +#ifdef CONFIG_BTFM_SLIM_WCN3990 +#include "btfm_slim.h" + +/* Registers Address */ +#define CHRK_SB_COMP_TEST 0x00000000 +#define CHRK_SB_SLAVE_HW_REV_MSB 0x00000001 +#define CHRK_SB_SLAVE_HW_REV_LSB 0x00000002 +#define CHRK_SB_DEBUG_FEATURES 0x00000005 +#define CHRK_SB_INTF_INT_EN 0x00000010 +#define CHRK_SB_INTF_INT_STATUS 0x00000011 +#define CHRK_SB_INTF_INT_CLR 0x00000012 +#define CHRK_SB_FRM_CFG 0x00000013 +#define CHRK_SB_FRM_STATUS 0x00000014 +#define CHRK_SB_FRM_INT_EN 0x00000015 +#define CHRK_SB_FRM_INT_STATUS 0x00000016 +#define CHRK_SB_FRM_INT_CLR 0x00000017 +#define CHRK_SB_FRM_WAKEUP 0x00000018 +#define CHRK_SB_FRM_CLKCTL_DONE 0x00000019 +#define CHRK_SB_FRM_IE_STATUS 0x0000001A +#define CHRK_SB_FRM_VE_STATUS 0x0000001B +#define CHRK_SB_PGD_TX_CFG_STATUS 0x00000020 +#define CHRK_SB_PGD_RX_CFG_STATUS 0x00000021 +#define CHRK_SB_PGD_DEV_INT_EN 0x00000022 +#define CHRK_SB_PGD_DEV_INT_STATUS 0x00000023 +#define CHRK_SB_PGD_DEV_INT_CLR 0x00000024 +#define CHRK_SB_PGD_PORT_INT_EN_RX_0 0x00000030 +#define CHRK_SB_PGD_PORT_INT_EN_RX_1 0x00000031 +#define CHRK_SB_PGD_PORT_INT_EN_TX_0 0x00000032 +#define CHRK_SB_PGD_PORT_INT_EN_TX_1 0x00000033 +#define CHRK_SB_PGD_PORT_INT_STATUS_RX_0 0x00000034 +#define CHRK_SB_PGD_PORT_INT_STATUS_RX_1 0x00000035 +#define CHRK_SB_PGD_PORT_INT_STATUS_TX_0 0x00000036 +#define CHRK_SB_PGD_PORT_INT_STATUS_TX_1 0x00000037 +#define CHRK_SB_PGD_PORT_INT_CLR_RX_0 0x00000038 +#define CHRK_SB_PGD_PORT_INT_CLR_RX_1 0x00000039 +#define CHRK_SB_PGD_PORT_INT_CLR_TX_0 0x0000003A +#define CHRK_SB_PGD_PORT_INT_CLR_TX_1 0x0000003B +#define CHRK_SB_PGD_PORT_RX_CFGN(n) (0x00000040 + n) +#define CHRK_SB_PGD_PORT_TX_CFGN(n) (0x00000050 + n) +#define CHRK_SB_PGD_PORT_INT_RX_SOURCEN(n) (0x00000060 + n) +#define CHRK_SB_PGD_PORT_INT_TX_SOURCEN(n) (0x00000070 + n) +#define CHRK_SB_PGD_PORT_RX_STATUSN(n) (0x00000080 + n) +#define CHRK_SB_PGD_PORT_TX_STATUSN(n) (0x00000090 + n) +#define CHRK_SB_PGD_TX_PORTn_MULTI_CHNL_0(n) (0x00000100 + 0x4*n) +#define CHRK_SB_PGD_TX_PORTn_MULTI_CHNL_1(n) (0x00000101 + 0x4*n) +#define CHRK_SB_PGD_RX_PORTn_MULTI_CHNL_0(n) (0x00000180 + 0x4*n) +#define CHRK_SB_PGD_RX_PORTn_MULTI_CHNL_1(n) (0x00000181 + 0x4*n) +#define CHRK_SB_PGD_PORT_TX_OR_UR_CFGN(n) (0x000001F0 + n) + +/* Register Bit Setting */ +#define CHRK_ENABLE_OVERRUN_AUTO_RECOVERY (0x1 << 1) +#define CHRK_ENABLE_UNDERRUN_AUTO_RECOVERY (0x1 << 0) +#define CHRK_SB_PGD_PORT_ENABLE (0x1 << 0) +#define CHRK_SB_PGD_PORT_DISABLE (0x0 << 0) +#define CHRK_SB_PGD_PORT_WM_L1 (0x1 << 1) +#define CHRK_SB_PGD_PORT_WM_L2 (0x2 << 1) +#define CHRK_SB_PGD_PORT_WM_L3 (0x3 << 1) +#define CHRK_SB_PGD_PORT_WM_L8 (0x8 << 1) +#define CHRK_SB_PGD_PORT_WM_LB (0xB << 1) + +#define CHRK_SB_PGD_PORT_RX_NUM 16 +#define CHRK_SB_PGD_PORT_TX_NUM 16 + +/* PGD Port Map */ +#define CHRK_SB_PGD_PORT_TX_SCO 0 +#define CHRK_SB_PGD_PORT_TX1_FM 1 +#define CHRK_SB_PGD_PORT_TX2_FM 2 +#define CHRK_SB_PGD_PORT_RX_SCO 16 +#define CHRK_SB_PGD_PORT_RX_A2P 17 + + +/* Function Prototype */ + +/* + * btfm_slim_chrk_hw_init: Initialize wcn3990 specific slimbus slave device + * @btfmslim: slimbus slave device data pointer. + * Returns: + * 0: Success + * else: Fail + */ +int btfm_slim_chrk_hw_init(struct btfmslim *btfmslim); + +/* + * btfm_slim_chrk_enable_rxport: Enable wcn3990 Rx port by given port number + * @btfmslim: slimbus slave device data pointer. + * @portNum: slimbus slave port number to enable + * @rxport: rxport or txport + * @enable: enable port or disable port + * Returns: + * 0: Success + * else: Fail + */ +int btfm_slim_chrk_enable_port(struct btfmslim *btfmslim, uint8_t portNum, + uint8_t rxport, uint8_t enable); + +/* Specific defines for wcn3990 slimbus device */ +#define WCN3990_SLIM_REG_OFFSET 0x0800 + +#ifdef SLIM_SLAVE_REG_OFFSET +#undef SLIM_SLAVE_REG_OFFSET +#define SLIM_SLAVE_REG_OFFSET WCN3990_SLIM_REG_OFFSET +#endif + +/* Assign vendor specific function */ +extern struct btfmslim_ch wcn3990_txport[]; +extern struct btfmslim_ch wcn3990_rxport[]; + +#ifdef SLIM_SLAVE_RXPORT +#undef SLIM_SLAVE_RXPORT +#define SLIM_SLAVE_RXPORT (&wcn3990_rxport[0]) +#endif + +#ifdef SLIM_SLAVE_TXPORT +#undef SLIM_SLAVE_TXPORT +#define SLIM_SLAVE_TXPORT (&wcn3990_txport[0]) +#endif + +#ifdef SLIM_SLAVE_INIT +#undef SLIM_SLAVE_INIT +#define SLIM_SLAVE_INIT btfm_slim_chrk_hw_init +#endif + +#ifdef SLIM_SLAVE_PORT_EN +#undef SLIM_SLAVE_PORT_EN +#define SLIM_SLAVE_PORT_EN btfm_slim_chrk_enable_port +#endif +#endif /* CONFIG_BTFM_WCN3990 */ +#endif /* BTFM_SLIM_WCN3990_H */ --- /dev/null 2019-10-24 16:47:25.704025805 +0200 +++ linux-4.4.115-fbx/drivers/char/adsprpc.c 2019-10-29 09:26:23.445201240 +0100 @@ -0,0 +1,3263 @@ +/* + * Copyright (c) 2012-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "adsprpc_compat.h" +#include "adsprpc_shared.h" +#include +#include + +#define TZ_PIL_PROTECT_MEM_SUBSYS_ID 0x0C +#define TZ_PIL_CLEAR_PROTECT_MEM_SUBSYS_ID 0x0D +#define TZ_PIL_AUTH_QDSP6_PROC 1 +#define ADSP_MMAP_HEAP_ADDR 4 +#define ADSP_MMAP_REMOTE_HEAP_ADDR 8 +#define FASTRPC_ENOSUCH 39 +#define VMID_SSC_Q6 38 +#define VMID_ADSP_Q6 6 +#define AC_VM_ADSP_HEAP_SHARED 33 +#define DEBUGFS_SIZE 1024 + +#define RPC_TIMEOUT (5 * HZ) +#define BALIGN 128 +#define NUM_CHANNELS 4 /* adsp,sdsp,mdsp,cdsp */ +#define NUM_SESSIONS 9 /*8 compute, 1 cpz*/ +#define FASTRPC_CTX_MAGIC (0xbeeddeed) +#define FASTRPC_CTX_MAX (256) +#define FASTRPC_CTXID_MASK (0xFF0) + +#define IS_CACHE_ALIGNED(x) (((x) & ((L1_CACHE_BYTES)-1)) == 0) + +#define FASTRPC_LINK_STATE_DOWN (0x0) +#define FASTRPC_LINK_STATE_UP (0x1) +#define FASTRPC_LINK_DISCONNECTED (0x0) +#define FASTRPC_LINK_CONNECTING (0x1) +#define FASTRPC_LINK_CONNECTED (0x3) +#define FASTRPC_LINK_DISCONNECTING (0x7) + +#define PERF_KEYS "count:flush:map:copy:glink:getargs:putargs:invalidate:invoke" +#define FASTRPC_STATIC_HANDLE_KERNEL (1) +#define FASTRPC_STATIC_HANDLE_LISTENER (3) +#define FASTRPC_STATIC_HANDLE_MAX (20) + +#define PERF_END (void)0 + +#define PERF(enb, cnt, ff) \ + {\ + struct timespec startT = {0};\ + if (enb) {\ + getnstimeofday(&startT);\ + } \ + ff ;\ + if (enb) {\ + cnt += getnstimediff(&startT);\ + } \ + } + +static int fastrpc_glink_open(int cid); +static void fastrpc_glink_close(void *chan, int cid); +static struct dentry *debugfs_root; +static struct dentry *debugfs_global_file; + +static inline uint64_t buf_page_start(uint64_t buf) +{ + uint64_t start = (uint64_t) buf & PAGE_MASK; + return start; +} + +static inline uint64_t buf_page_offset(uint64_t buf) +{ + uint64_t offset = (uint64_t) buf & (PAGE_SIZE - 1); + return offset; +} + +static inline uint64_t buf_num_pages(uint64_t buf, size_t len) +{ + uint64_t start = buf_page_start(buf) >> PAGE_SHIFT; + uint64_t end = (((uint64_t) buf + len - 1) & PAGE_MASK) >> PAGE_SHIFT; + uint64_t nPages = end - start + 1; + return nPages; +} + +static inline uint64_t buf_page_size(uint32_t size) +{ + uint64_t sz = (size + (PAGE_SIZE - 1)) & PAGE_MASK; + return sz > PAGE_SIZE ? sz : PAGE_SIZE; +} + +static inline void *uint64_to_ptr(uint64_t addr) +{ + void *ptr = (void *)((uintptr_t)addr); + return ptr; +} + +static inline uint64_t ptr_to_uint64(void *ptr) +{ + uint64_t addr = (uint64_t)((uintptr_t)ptr); + return addr; +} + +struct fastrpc_file; + +struct fastrpc_buf { + struct hlist_node hn; + struct fastrpc_file *fl; + void *virt; + uint64_t phys; + size_t size; +}; + +struct fastrpc_ctx_lst; + +struct overlap { + uintptr_t start; + uintptr_t end; + int raix; + uintptr_t mstart; + uintptr_t mend; + uintptr_t offset; +}; + +struct smq_invoke_ctx { + struct hlist_node hn; + struct completion work; + int retval; + int pid; + int tgid; + remote_arg_t *lpra; + remote_arg64_t *rpra; + int *fds; + unsigned *attrs; + struct fastrpc_mmap **maps; + struct fastrpc_buf *buf; + size_t used; + struct fastrpc_file *fl; + uint32_t sc; + struct overlap *overs; + struct overlap **overps; + struct smq_msg msg; + unsigned int magic; + uint64_t ctxid; +}; + +struct fastrpc_ctx_lst { + struct hlist_head pending; + struct hlist_head interrupted; +}; + +struct fastrpc_smmu { + struct device *dev; + struct dma_iommu_mapping *mapping; + int cb; + int enabled; + int faults; + int secure; + int coherent; +}; + +struct fastrpc_session_ctx { + struct device *dev; + struct fastrpc_smmu smmu; + int used; +}; + +struct fastrpc_glink_info { + int link_state; + int port_state; + struct glink_open_config cfg; + struct glink_link_info link_info; + void *link_notify_handle; +}; + +struct fastrpc_channel_ctx { + char *name; + char *subsys; + void *chan; + struct device *dev; + struct fastrpc_session_ctx session[NUM_SESSIONS]; + struct completion work; + struct completion workport; + struct notifier_block nb; + struct kref kref; + int channel; + int sesscount; + int ssrcount; + void *handle; + int prevssrcount; + int issubsystemup; + int vmid; + int heap_vmid; + int ramdumpenabled; + void *remoteheap_ramdump_dev; + struct fastrpc_glink_info link; +}; + +struct fastrpc_apps { + struct fastrpc_channel_ctx *channel; + struct cdev cdev; + struct class *class; + struct mutex smd_mutex; + struct smq_phy_page range; + struct hlist_head maps; + uint32_t staticpd_flags; + dev_t dev_no; + int compat; + struct hlist_head drivers; + spinlock_t hlock; + struct ion_client *client; + struct device *dev; + bool glink; + spinlock_t ctxlock; + struct smq_invoke_ctx *ctxtable[FASTRPC_CTX_MAX]; +}; + +struct fastrpc_mmap { + struct hlist_node hn; + struct fastrpc_file *fl; + struct fastrpc_apps *apps; + int fd; + uint32_t flags; + struct dma_buf *buf; + struct sg_table *table; + struct dma_buf_attachment *attach; + struct ion_handle *handle; + uint64_t phys; + size_t size; + uintptr_t va; + size_t len; + int refs; + uintptr_t raddr; + int uncached; + int secure; + uintptr_t attr; +}; + +struct fastrpc_perf { + int64_t count; + int64_t flush; + int64_t map; + int64_t copy; + int64_t link; + int64_t getargs; + int64_t putargs; + int64_t invargs; + int64_t invoke; +}; + +struct fastrpc_file { + struct hlist_node hn; + spinlock_t hlock; + struct hlist_head maps; + struct hlist_head bufs; + struct fastrpc_ctx_lst clst; + struct fastrpc_session_ctx *sctx; + struct fastrpc_session_ctx *secsctx; + uint32_t mode; + uint32_t profile; + int tgid; + int cid; + int ssrcount; + int pd; + int file_close; + struct fastrpc_apps *apps; + struct fastrpc_perf perf; + struct dentry *debugfs_file; + struct mutex map_mutex; +}; + +static struct fastrpc_apps gfa; + +static struct fastrpc_channel_ctx gcinfo[NUM_CHANNELS] = { + { + .name = "adsprpc-smd", + .subsys = "adsp", + .channel = SMD_APPS_QDSP, + .link.link_info.edge = "lpass", + .link.link_info.transport = "smem", + }, + { + .name = "mdsprpc-smd", + .subsys = "modem", + .channel = SMD_APPS_MODEM, + .link.link_info.edge = "mpss", + .link.link_info.transport = "smem", + }, + { + .name = "sdsprpc-smd", + .subsys = "slpi", + .channel = SMD_APPS_DSPS, + .link.link_info.edge = "dsps", + .link.link_info.transport = "smem", + .vmid = VMID_SSC_Q6, + }, + { + .name = "cdsprpc-smd", + .subsys = "cdsp", + .link.link_info.edge = "cdsp", + .link.link_info.transport = "smem", + }, +}; + +static inline int64_t getnstimediff(struct timespec *start) +{ + int64_t ns; + struct timespec ts, b; + + getnstimeofday(&ts); + b = timespec_sub(ts, *start); + ns = timespec_to_ns(&b); + return ns; +} + +static void fastrpc_buf_free(struct fastrpc_buf *buf, int cache) +{ + struct fastrpc_file *fl = buf == NULL ? NULL : buf->fl; + int vmid; + + if (!fl) + return; + if (cache) { + spin_lock(&fl->hlock); + hlist_add_head(&buf->hn, &fl->bufs); + spin_unlock(&fl->hlock); + return; + } + if (!IS_ERR_OR_NULL(buf->virt)) { + int destVM[1] = {VMID_HLOS}; + int destVMperm[1] = {PERM_READ | PERM_WRITE | PERM_EXEC}; + + if (fl->sctx->smmu.cb) + buf->phys &= ~((uint64_t)fl->sctx->smmu.cb << 32); + vmid = fl->apps->channel[fl->cid].vmid; + if (vmid) { + int srcVM[2] = {VMID_HLOS, vmid}; + + hyp_assign_phys(buf->phys, buf_page_size(buf->size), + srcVM, 2, destVM, destVMperm, 1); + } + dma_free_coherent(fl->sctx->smmu.dev, buf->size, buf->virt, + buf->phys); + } + kfree(buf); +} + +static void fastrpc_buf_list_free(struct fastrpc_file *fl) +{ + struct fastrpc_buf *buf, *free; + do { + struct hlist_node *n; + + free = NULL; + spin_lock(&fl->hlock); + hlist_for_each_entry_safe(buf, n, &fl->bufs, hn) { + hlist_del_init(&buf->hn); + free = buf; + break; + } + spin_unlock(&fl->hlock); + if (free) + fastrpc_buf_free(free, 0); + } while (free); +} + +static void fastrpc_mmap_add(struct fastrpc_mmap *map) +{ + if (map->flags == ADSP_MMAP_HEAP_ADDR || + map->flags == ADSP_MMAP_REMOTE_HEAP_ADDR) { + struct fastrpc_apps *me = &gfa; + + spin_lock(&me->hlock); + hlist_add_head(&map->hn, &me->maps); + spin_unlock(&me->hlock); + } else { + struct fastrpc_file *fl = map->fl; + + spin_lock(&fl->hlock); + hlist_add_head(&map->hn, &fl->maps); + spin_unlock(&fl->hlock); + } +} + +static int fastrpc_mmap_find(struct fastrpc_file *fl, int fd, uintptr_t va, + size_t len, int mflags, struct fastrpc_mmap **ppmap) +{ + struct fastrpc_apps *me = &gfa; + struct fastrpc_mmap *match = NULL, *map = NULL; + struct hlist_node *n; + + if ((va + len) < va) + return -EOVERFLOW; + if (mflags == ADSP_MMAP_HEAP_ADDR || + mflags == ADSP_MMAP_REMOTE_HEAP_ADDR) { + spin_lock(&me->hlock); + hlist_for_each_entry_safe(map, n, &me->maps, hn) { + if (va >= map->va && + va + len <= map->va + map->len && + map->fd == fd) { + map->refs++; + match = map; + break; + } + } + spin_unlock(&me->hlock); + } else { + spin_lock(&fl->hlock); + hlist_for_each_entry_safe(map, n, &fl->maps, hn) { + if (va >= map->va && + va + len <= map->va + map->len && + map->fd == fd) { + map->refs++; + match = map; + break; + } + } + spin_unlock(&fl->hlock); + } + if (match) { + *ppmap = match; + return 0; + } + return -ENOTTY; +} + +static int dma_alloc_memory(phys_addr_t *region_start, size_t size) +{ + struct fastrpc_apps *me = &gfa; + void *vaddr = NULL; + DEFINE_DMA_ATTRS(attrs); + + if (me->dev == NULL) { + pr_err("device adsprpc-mem is not initialized\n"); + return -ENODEV; + } + dma_set_attr(DMA_ATTR_SKIP_ZEROING, &attrs); + dma_set_attr(DMA_ATTR_NO_KERNEL_MAPPING, &attrs); + vaddr = dma_alloc_attrs(me->dev, size, region_start, GFP_KERNEL, + &attrs); + if (!vaddr) { + pr_err("ADSPRPC: Failed to allocate %x remote heap memory\n", + (unsigned int)size); + return -ENOMEM; + } + return 0; +} + +static int fastrpc_mmap_remove(struct fastrpc_file *fl, uintptr_t va, + size_t len, struct fastrpc_mmap **ppmap) +{ + struct fastrpc_mmap *match = NULL, *map; + struct hlist_node *n; + struct fastrpc_apps *me = &gfa; + + spin_lock(&me->hlock); + hlist_for_each_entry_safe(map, n, &me->maps, hn) { + if (map->raddr == va && + map->raddr + map->len == va + len && + map->refs == 1) { + match = map; + hlist_del_init(&map->hn); + break; + } + } + spin_unlock(&me->hlock); + if (match) { + *ppmap = match; + return 0; + } + spin_lock(&fl->hlock); + hlist_for_each_entry_safe(map, n, &fl->maps, hn) { + if (map->raddr == va && + map->raddr + map->len == va + len && + map->refs == 1) { + match = map; + hlist_del_init(&map->hn); + break; + } + } + spin_unlock(&fl->hlock); + if (match) { + *ppmap = match; + return 0; + } + return -ENOTTY; +} + +static void fastrpc_mmap_free(struct fastrpc_mmap *map) +{ + struct fastrpc_apps *me = &gfa; + struct fastrpc_file *fl; + int vmid; + struct fastrpc_session_ctx *sess; + + if (!map) + return; + fl = map->fl; + if (map->flags == ADSP_MMAP_HEAP_ADDR || + map->flags == ADSP_MMAP_REMOTE_HEAP_ADDR) { + spin_lock(&me->hlock); + map->refs--; + if (!map->refs) + hlist_del_init(&map->hn); + spin_unlock(&me->hlock); + } else { + spin_lock(&fl->hlock); + map->refs--; + if (!map->refs) + hlist_del_init(&map->hn); + spin_unlock(&fl->hlock); + } + if (map->refs > 0) + return; + if (map->flags == ADSP_MMAP_HEAP_ADDR || + map->flags == ADSP_MMAP_REMOTE_HEAP_ADDR) { + DEFINE_DMA_ATTRS(attrs); + + if (me->dev == NULL) { + pr_err("failed to free remote heap allocation\n"); + return; + } + if (map->phys) { + dma_set_attr(DMA_ATTR_SKIP_ZEROING, &attrs); + dma_set_attr(DMA_ATTR_NO_KERNEL_MAPPING, &attrs); + dma_free_attrs(me->dev, map->size, + &(map->va), map->phys, &attrs); + } + } else { + int destVM[1] = {VMID_HLOS}; + int destVMperm[1] = {PERM_READ | PERM_WRITE | PERM_EXEC}; + + if (map->secure) + sess = fl->secsctx; + else + sess = fl->sctx; + + if (!IS_ERR_OR_NULL(map->handle)) + ion_free(fl->apps->client, map->handle); + if (sess && sess->smmu.enabled) { + if (map->size || map->phys) + msm_dma_unmap_sg(sess->smmu.dev, + map->table->sgl, + map->table->nents, DMA_BIDIRECTIONAL, + map->buf); + } + vmid = fl->apps->channel[fl->cid].vmid; + if (vmid && map->phys) { + int srcVM[2] = {VMID_HLOS, vmid}; + + hyp_assign_phys(map->phys, buf_page_size(map->size), + srcVM, 2, destVM, destVMperm, 1); + } + + if (!IS_ERR_OR_NULL(map->table)) + dma_buf_unmap_attachment(map->attach, map->table, + DMA_BIDIRECTIONAL); + if (!IS_ERR_OR_NULL(map->attach)) + dma_buf_detach(map->buf, map->attach); + if (!IS_ERR_OR_NULL(map->buf)) + dma_buf_put(map->buf); + } + kfree(map); +} + +static int fastrpc_session_alloc(struct fastrpc_channel_ctx *chan, int secure, + struct fastrpc_session_ctx **session); + +static int fastrpc_mmap_create(struct fastrpc_file *fl, int fd, unsigned attr, + uintptr_t va, size_t len, int mflags, struct fastrpc_mmap **ppmap) +{ + struct fastrpc_apps *me = &gfa; + struct fastrpc_session_ctx *sess; + struct fastrpc_apps *apps = fl->apps; + int cid = fl->cid; + struct fastrpc_channel_ctx *chan = &apps->channel[cid]; + struct fastrpc_mmap *map = NULL; + struct dma_attrs attrs; + phys_addr_t region_start = 0; + unsigned long flags; + int err = 0, vmid; + + if (!fastrpc_mmap_find(fl, fd, va, len, mflags, ppmap)) + return 0; + map = kzalloc(sizeof(*map), GFP_KERNEL); + VERIFY(err, !IS_ERR_OR_NULL(map)); + if (err) + goto bail; + INIT_HLIST_NODE(&map->hn); + map->flags = mflags; + map->refs = 1; + map->fl = fl; + map->fd = fd; + map->attr = attr; + if (mflags == ADSP_MMAP_HEAP_ADDR || + mflags == ADSP_MMAP_REMOTE_HEAP_ADDR) { + map->apps = me; + map->fl = NULL; + VERIFY(err, !dma_alloc_memory(®ion_start, len)); + if (err) + goto bail; + map->phys = (uintptr_t)region_start; + map->size = len; + map->va = (uintptr_t)map->phys; + } else { + VERIFY(err, !IS_ERR_OR_NULL(map->handle = + ion_import_dma_buf(fl->apps->client, fd))); + if (err) + goto bail; + VERIFY(err, !ion_handle_get_flags(fl->apps->client, map->handle, + &flags)); + if (err) + goto bail; + + map->uncached = !ION_IS_CACHED(flags); + if (map->attr & FASTRPC_ATTR_NOVA) + map->uncached = 1; + + map->secure = flags & ION_FLAG_SECURE; + if (map->secure) { + if (!fl->secsctx) + err = fastrpc_session_alloc(chan, 1, + &fl->secsctx); + if (err) + goto bail; + } + if (map->secure) + sess = fl->secsctx; + else + sess = fl->sctx; + + VERIFY(err, !IS_ERR_OR_NULL(sess)); + if (err) + goto bail; + VERIFY(err, !IS_ERR_OR_NULL(map->buf = dma_buf_get(fd))); + if (err) + goto bail; + VERIFY(err, !IS_ERR_OR_NULL(map->attach = + dma_buf_attach(map->buf, sess->smmu.dev))); + if (err) + goto bail; + VERIFY(err, !IS_ERR_OR_NULL(map->table = + dma_buf_map_attachment(map->attach, + DMA_BIDIRECTIONAL))); + if (err) + goto bail; + if (sess->smmu.enabled) { + init_dma_attrs(&attrs); + dma_set_attr(DMA_ATTR_EXEC_MAPPING, &attrs); + + if ((map->attr & FASTRPC_ATTR_NON_COHERENT) || + (sess->smmu.coherent && map->uncached)) + dma_set_attr(DMA_ATTR_FORCE_NON_COHERENT, + &attrs); + else if (map->attr & FASTRPC_ATTR_COHERENT) + dma_set_attr(DMA_ATTR_FORCE_COHERENT, &attrs); + + VERIFY(err, map->table->nents == + msm_dma_map_sg_attrs(sess->smmu.dev, + map->table->sgl, map->table->nents, + DMA_BIDIRECTIONAL, map->buf, &attrs)); + if (err) + goto bail; + } else { + VERIFY(err, map->table->nents == 1); + if (err) + goto bail; + } + map->phys = sg_dma_address(map->table->sgl); + if (sess->smmu.cb) { + map->phys += ((uint64_t)sess->smmu.cb << 32); + map->size = sg_dma_len(map->table->sgl); + } else { + map->size = buf_page_size(len); + } + vmid = fl->apps->channel[fl->cid].vmid; + if (vmid) { + int srcVM[1] = {VMID_HLOS}; + int destVM[2] = {VMID_HLOS, vmid}; + int destVMperm[2] = {PERM_READ | PERM_WRITE | PERM_EXEC, + PERM_READ | PERM_WRITE | PERM_EXEC}; + + VERIFY(err, !hyp_assign_phys(map->phys, + buf_page_size(map->size), + srcVM, 1, destVM, destVMperm, 2)); + if (err) + goto bail; + } + map->va = va; + } + map->len = len; + + fastrpc_mmap_add(map); + *ppmap = map; + +bail: + if (err && map) + fastrpc_mmap_free(map); + return err; +} + +static int fastrpc_buf_alloc(struct fastrpc_file *fl, size_t size, + struct fastrpc_buf **obuf) +{ + int err = 0, vmid; + struct fastrpc_buf *buf = NULL, *fr = NULL; + struct hlist_node *n; + + VERIFY(err, size > 0); + if (err) + goto bail; + + /* find the smallest buffer that fits in the cache */ + spin_lock(&fl->hlock); + hlist_for_each_entry_safe(buf, n, &fl->bufs, hn) { + if (buf->size >= size && (!fr || fr->size > buf->size)) + fr = buf; + } + if (fr) + hlist_del_init(&fr->hn); + spin_unlock(&fl->hlock); + if (fr) { + *obuf = fr; + return 0; + } + buf = NULL; + VERIFY(err, NULL != (buf = kzalloc(sizeof(*buf), GFP_KERNEL))); + if (err) + goto bail; + INIT_HLIST_NODE(&buf->hn); + buf->fl = fl; + buf->virt = NULL; + buf->phys = 0; + buf->size = size; + buf->virt = dma_alloc_coherent(fl->sctx->smmu.dev, buf->size, + (void *)&buf->phys, GFP_KERNEL); + if (IS_ERR_OR_NULL(buf->virt)) { + /* free cache and retry */ + fastrpc_buf_list_free(fl); + buf->virt = dma_alloc_coherent(fl->sctx->smmu.dev, buf->size, + (void *)&buf->phys, GFP_KERNEL); + VERIFY(err, !IS_ERR_OR_NULL(buf->virt)); + } + if (err) + goto bail; + if (fl->sctx->smmu.cb) + buf->phys += ((uint64_t)fl->sctx->smmu.cb << 32); + vmid = fl->apps->channel[fl->cid].vmid; + if (vmid) { + int srcVM[1] = {VMID_HLOS}; + int destVM[2] = {VMID_HLOS, vmid}; + int destVMperm[2] = {PERM_READ | PERM_WRITE | PERM_EXEC, + PERM_READ | PERM_WRITE | PERM_EXEC}; + + VERIFY(err, !hyp_assign_phys(buf->phys, buf_page_size(size), + srcVM, 1, destVM, destVMperm, 2)); + if (err) + goto bail; + } + + *obuf = buf; + bail: + if (err && buf) + fastrpc_buf_free(buf, 0); + return err; +} + + +static int context_restore_interrupted(struct fastrpc_file *fl, + struct fastrpc_ioctl_invoke_attrs *inv, + struct smq_invoke_ctx **po) +{ + int err = 0; + struct smq_invoke_ctx *ctx = NULL, *ictx = NULL; + struct hlist_node *n; + struct fastrpc_ioctl_invoke *invoke = &inv->inv; + spin_lock(&fl->hlock); + hlist_for_each_entry_safe(ictx, n, &fl->clst.interrupted, hn) { + if (ictx->pid == current->pid) { + if (invoke->sc != ictx->sc || ictx->fl != fl) + err = -1; + else { + ctx = ictx; + hlist_del_init(&ctx->hn); + hlist_add_head(&ctx->hn, &fl->clst.pending); + } + break; + } + } + spin_unlock(&fl->hlock); + if (ctx) + *po = ctx; + return err; +} + +#define CMP(aa, bb) ((aa) == (bb) ? 0 : (aa) < (bb) ? -1 : 1) +static int overlap_ptr_cmp(const void *a, const void *b) +{ + struct overlap *pa = *((struct overlap **)a); + struct overlap *pb = *((struct overlap **)b); + /* sort with lowest starting buffer first */ + int st = CMP(pa->start, pb->start); + /* sort with highest ending buffer first */ + int ed = CMP(pb->end, pa->end); + return st == 0 ? ed : st; +} + +static int context_build_overlap(struct smq_invoke_ctx *ctx) +{ + int i, err = 0; + remote_arg_t *lpra = ctx->lpra; + int inbufs = REMOTE_SCALARS_INBUFS(ctx->sc); + int outbufs = REMOTE_SCALARS_OUTBUFS(ctx->sc); + int nbufs = inbufs + outbufs; + struct overlap max; + for (i = 0; i < nbufs; ++i) { + ctx->overs[i].start = (uintptr_t)lpra[i].buf.pv; + ctx->overs[i].end = ctx->overs[i].start + lpra[i].buf.len; + if (lpra[i].buf.len) { + VERIFY(err, ctx->overs[i].end > ctx->overs[i].start); + if (err) + goto bail; + } + ctx->overs[i].raix = i; + ctx->overps[i] = &ctx->overs[i]; + } + sort(ctx->overps, nbufs, sizeof(*ctx->overps), overlap_ptr_cmp, NULL); + max.start = 0; + max.end = 0; + for (i = 0; i < nbufs; ++i) { + if (ctx->overps[i]->start < max.end) { + ctx->overps[i]->mstart = max.end; + ctx->overps[i]->mend = ctx->overps[i]->end; + ctx->overps[i]->offset = max.end - + ctx->overps[i]->start; + if (ctx->overps[i]->end > max.end) { + max.end = ctx->overps[i]->end; + } else { + ctx->overps[i]->mend = 0; + ctx->overps[i]->mstart = 0; + } + } else { + ctx->overps[i]->mend = ctx->overps[i]->end; + ctx->overps[i]->mstart = ctx->overps[i]->start; + ctx->overps[i]->offset = 0; + max = *ctx->overps[i]; + } + } +bail: + return err; +} + +#define K_COPY_FROM_USER(err, kernel, dst, src, size) \ + do {\ + if (!(kernel))\ + VERIFY(err, 0 == copy_from_user((dst),\ + (void const __user *)(src),\ + (size)));\ + else\ + memmove((dst), (src), (size));\ + } while (0) + +#define K_COPY_TO_USER(err, kernel, dst, src, size) \ + do {\ + if (!(kernel))\ + VERIFY(err, 0 == copy_to_user((void __user *)(dst), \ + (src), (size)));\ + else\ + memmove((dst), (src), (size));\ + } while (0) + + +static void context_free(struct smq_invoke_ctx *ctx); + +static int context_alloc(struct fastrpc_file *fl, uint32_t kernel, + struct fastrpc_ioctl_invoke_attrs *invokefd, + struct smq_invoke_ctx **po) +{ + int err = 0, bufs, ii, size = 0; + struct fastrpc_apps *me = &gfa; + struct smq_invoke_ctx *ctx = NULL; + struct fastrpc_ctx_lst *clst = &fl->clst; + struct fastrpc_ioctl_invoke *invoke = &invokefd->inv; + + bufs = REMOTE_SCALARS_LENGTH(invoke->sc); + size = bufs * sizeof(*ctx->lpra) + bufs * sizeof(*ctx->maps) + + sizeof(*ctx->fds) * (bufs) + + sizeof(*ctx->attrs) * (bufs) + + sizeof(*ctx->overs) * (bufs) + + sizeof(*ctx->overps) * (bufs); + + VERIFY(err, NULL != (ctx = kzalloc(sizeof(*ctx) + size, GFP_KERNEL))); + if (err) + goto bail; + + INIT_HLIST_NODE(&ctx->hn); + hlist_add_fake(&ctx->hn); + ctx->fl = fl; + ctx->maps = (struct fastrpc_mmap **)(&ctx[1]); + ctx->lpra = (remote_arg_t *)(&ctx->maps[bufs]); + ctx->fds = (int *)(&ctx->lpra[bufs]); + ctx->attrs = (unsigned *)(&ctx->fds[bufs]); + ctx->overs = (struct overlap *)(&ctx->attrs[bufs]); + ctx->overps = (struct overlap **)(&ctx->overs[bufs]); + + K_COPY_FROM_USER(err, kernel, (void *)ctx->lpra, invoke->pra, + bufs * sizeof(*ctx->lpra)); + if (err) + goto bail; + + if (invokefd->fds) { + K_COPY_FROM_USER(err, kernel, ctx->fds, invokefd->fds, + bufs * sizeof(*ctx->fds)); + if (err) + goto bail; + } + if (invokefd->attrs) { + K_COPY_FROM_USER(err, kernel, ctx->attrs, invokefd->attrs, + bufs * sizeof(*ctx->attrs)); + if (err) + goto bail; + } + + ctx->sc = invoke->sc; + if (bufs) { + VERIFY(err, 0 == context_build_overlap(ctx)); + if (err) + goto bail; + } + ctx->retval = -1; + ctx->pid = current->pid; + ctx->tgid = current->tgid; + init_completion(&ctx->work); + ctx->magic = FASTRPC_CTX_MAGIC; + + spin_lock(&fl->hlock); + hlist_add_head(&ctx->hn, &clst->pending); + spin_unlock(&fl->hlock); + + spin_lock(&me->ctxlock); + for (ii = 0; ii < FASTRPC_CTX_MAX; ii++) { + if (!me->ctxtable[ii]) { + me->ctxtable[ii] = ctx; + ctx->ctxid = (ptr_to_uint64(ctx) & ~0xFFF)|(ii << 4); + break; + } + } + spin_unlock(&me->ctxlock); + VERIFY(err, ii < FASTRPC_CTX_MAX); + if (err) { + pr_err("adsprpc: out of context memory\n"); + goto bail; + } + + *po = ctx; +bail: + if (ctx && err) + context_free(ctx); + return err; +} + +static void context_save_interrupted(struct smq_invoke_ctx *ctx) +{ + struct fastrpc_ctx_lst *clst = &ctx->fl->clst; + spin_lock(&ctx->fl->hlock); + hlist_del_init(&ctx->hn); + hlist_add_head(&ctx->hn, &clst->interrupted); + spin_unlock(&ctx->fl->hlock); + /* free the cache on power collapse */ + fastrpc_buf_list_free(ctx->fl); +} + +static void context_free(struct smq_invoke_ctx *ctx) +{ + int i; + struct fastrpc_apps *me = &gfa; + int nbufs = REMOTE_SCALARS_INBUFS(ctx->sc) + + REMOTE_SCALARS_OUTBUFS(ctx->sc); + spin_lock(&ctx->fl->hlock); + hlist_del_init(&ctx->hn); + spin_unlock(&ctx->fl->hlock); + for (i = 0; i < nbufs; ++i) + fastrpc_mmap_free(ctx->maps[i]); + fastrpc_buf_free(ctx->buf, 1); + ctx->magic = 0; + ctx->ctxid = 0; + + spin_lock(&me->ctxlock); + for (i = 0; i < FASTRPC_CTX_MAX; i++) { + if (me->ctxtable[i] == ctx) { + me->ctxtable[i] = NULL; + break; + } + } + spin_unlock(&me->ctxlock); + + kfree(ctx); +} + +static void context_notify_user(struct smq_invoke_ctx *ctx, int retval) +{ + ctx->retval = retval; + complete(&ctx->work); +} + + +static void fastrpc_notify_users(struct fastrpc_file *me) +{ + struct smq_invoke_ctx *ictx; + struct hlist_node *n; + spin_lock(&me->hlock); + hlist_for_each_entry_safe(ictx, n, &me->clst.pending, hn) { + complete(&ictx->work); + } + hlist_for_each_entry_safe(ictx, n, &me->clst.interrupted, hn) { + complete(&ictx->work); + } + spin_unlock(&me->hlock); + +} + +static void fastrpc_notify_drivers(struct fastrpc_apps *me, int cid) +{ + struct fastrpc_file *fl; + struct hlist_node *n; + spin_lock(&me->hlock); + hlist_for_each_entry_safe(fl, n, &me->drivers, hn) { + if (fl->cid == cid) + fastrpc_notify_users(fl); + } + spin_unlock(&me->hlock); + +} +static void context_list_ctor(struct fastrpc_ctx_lst *me) +{ + INIT_HLIST_HEAD(&me->interrupted); + INIT_HLIST_HEAD(&me->pending); +} + +static void fastrpc_context_list_dtor(struct fastrpc_file *fl) +{ + struct fastrpc_ctx_lst *clst = &fl->clst; + struct smq_invoke_ctx *ictx = NULL, *ctxfree; + struct hlist_node *n; + do { + ctxfree = NULL; + spin_lock(&fl->hlock); + hlist_for_each_entry_safe(ictx, n, &clst->interrupted, hn) { + hlist_del_init(&ictx->hn); + ctxfree = ictx; + break; + } + spin_unlock(&fl->hlock); + if (ctxfree) + context_free(ctxfree); + } while (ctxfree); + do { + ctxfree = NULL; + spin_lock(&fl->hlock); + hlist_for_each_entry_safe(ictx, n, &clst->pending, hn) { + hlist_del_init(&ictx->hn); + ctxfree = ictx; + break; + } + spin_unlock(&fl->hlock); + if (ctxfree) + context_free(ctxfree); + } while (ctxfree); +} + +static int fastrpc_file_free(struct fastrpc_file *fl); +static void fastrpc_file_list_dtor(struct fastrpc_apps *me) +{ + struct fastrpc_file *fl, *free; + struct hlist_node *n; + do { + free = NULL; + spin_lock(&me->hlock); + hlist_for_each_entry_safe(fl, n, &me->drivers, hn) { + hlist_del_init(&fl->hn); + free = fl; + break; + } + spin_unlock(&me->hlock); + if (free) + fastrpc_file_free(free); + } while (free); +} + +static int get_args(uint32_t kernel, struct smq_invoke_ctx *ctx) +{ + remote_arg64_t *rpra; + remote_arg_t *lpra = ctx->lpra; + struct smq_invoke_buf *list; + struct smq_phy_page *pages, *ipage; + uint32_t sc = ctx->sc; + int inbufs = REMOTE_SCALARS_INBUFS(sc); + int outbufs = REMOTE_SCALARS_OUTBUFS(sc); + int bufs = inbufs + outbufs; + uintptr_t args; + size_t rlen = 0, copylen = 0, metalen = 0; + int i, inh, oix; + int err = 0; + int mflags = 0; + + /* calculate size of the metadata */ + rpra = NULL; + list = smq_invoke_buf_start(rpra, sc); + pages = smq_phy_page_start(sc, list); + ipage = pages; + + for (i = 0; i < bufs; ++i) { + uintptr_t buf = (uintptr_t)lpra[i].buf.pv; + size_t len = lpra[i].buf.len; + + if (ctx->fds[i] && (ctx->fds[i] != -1)) + fastrpc_mmap_create(ctx->fl, ctx->fds[i], + ctx->attrs[i], buf, len, + mflags, &ctx->maps[i]); + ipage += 1; + } + metalen = copylen = (size_t)&ipage[0]; + /* calculate len requreed for copying */ + for (oix = 0; oix < inbufs + outbufs; ++oix) { + int i = ctx->overps[oix]->raix; + uintptr_t mstart, mend; + size_t len = lpra[i].buf.len; + + if (!len) + continue; + if (ctx->maps[i]) + continue; + if (ctx->overps[oix]->offset == 0) + copylen = ALIGN(copylen, BALIGN); + mstart = ctx->overps[oix]->mstart; + mend = ctx->overps[oix]->mend; + VERIFY(err, (mend - mstart) <= LONG_MAX); + if (err) + goto bail; + copylen += mend - mstart; + VERIFY(err, copylen >= 0); + if (err) + goto bail; + } + ctx->used = copylen; + + /* allocate new buffer */ + if (copylen) { + VERIFY(err, !fastrpc_buf_alloc(ctx->fl, copylen, &ctx->buf)); + if (err) + goto bail; + } + VERIFY(err, ctx->buf->virt != NULL); + if (err) + goto bail; + if (metalen <= copylen) + memset(ctx->buf->virt, 0, metalen); + + /* copy metadata */ + rpra = ctx->buf->virt; + ctx->rpra = rpra; + list = smq_invoke_buf_start(rpra, sc); + pages = smq_phy_page_start(sc, list); + ipage = pages; + args = (uintptr_t)ctx->buf->virt + metalen; + for (i = 0; i < bufs; ++i) { + size_t len = lpra[i].buf.len; + list[i].num = 0; + list[i].pgidx = 0; + if (!len) + continue; + list[i].num = 1; + list[i].pgidx = ipage - pages; + ipage++; + } + /* map ion buffers */ + PERF(ctx->fl->profile, ctx->fl->perf.map, + for (i = 0; i < inbufs + outbufs; ++i) { + struct fastrpc_mmap *map = ctx->maps[i]; + uint64_t buf = ptr_to_uint64(lpra[i].buf.pv); + size_t len = lpra[i].buf.len; + rpra[i].buf.pv = 0; + rpra[i].buf.len = len; + if (!len) + continue; + if (map) { + struct vm_area_struct *vma; + uintptr_t offset; + uint64_t num = buf_num_pages(buf, len); + int idx = list[i].pgidx; + + if (map->attr & FASTRPC_ATTR_NOVA) { + offset = 0; + } else { + down_read(¤t->mm->mmap_sem); + VERIFY(err, NULL != (vma = find_vma(current->mm, + map->va))); + if (err) { + up_read(¤t->mm->mmap_sem); + goto bail; + } + offset = buf_page_start(buf) - vma->vm_start; + up_read(¤t->mm->mmap_sem); + VERIFY(err, offset < (uintptr_t)map->size); + if (err) + goto bail; + } + pages[idx].addr = map->phys + offset; + pages[idx].size = num << PAGE_SHIFT; + } + rpra[i].buf.pv = buf; + } + PERF_END); + + /* copy non ion buffers */ + PERF(ctx->fl->profile, ctx->fl->perf.copy, + rlen = copylen - metalen; + for (oix = 0; rpra && oix < inbufs + outbufs; ++oix) { + int i = ctx->overps[oix]->raix; + struct fastrpc_mmap *map = ctx->maps[i]; + size_t mlen; + uint64_t buf; + size_t len = lpra[i].buf.len; + + if (!len) + continue; + if (map) + continue; + if (ctx->overps[oix]->offset == 0) { + rlen -= ALIGN(args, BALIGN) - args; + args = ALIGN(args, BALIGN); + } + mlen = ctx->overps[oix]->mend - ctx->overps[oix]->mstart; + VERIFY(err, rlen >= mlen); + if (err) + goto bail; + rpra[i].buf.pv = (args - ctx->overps[oix]->offset); + pages[list[i].pgidx].addr = ctx->buf->phys - + ctx->overps[oix]->offset + + (copylen - rlen); + pages[list[i].pgidx].addr = + buf_page_start(pages[list[i].pgidx].addr); + buf = rpra[i].buf.pv; + pages[list[i].pgidx].size = buf_num_pages(buf, len) * PAGE_SIZE; + if (i < inbufs) { + K_COPY_FROM_USER(err, kernel, uint64_to_ptr(buf), + lpra[i].buf.pv, len); + if (err) + goto bail; + } + args = args + mlen; + rlen -= mlen; + } + PERF_END); + + PERF(ctx->fl->profile, ctx->fl->perf.flush, + for (oix = 0; oix < inbufs + outbufs; ++oix) { + int i = ctx->overps[oix]->raix; + struct fastrpc_mmap *map = ctx->maps[i]; + + if (map && map->uncached) + continue; + if (ctx->fl->sctx->smmu.coherent && + !(map && (map->attr & FASTRPC_ATTR_NON_COHERENT))) + continue; + if (map && (map->attr & FASTRPC_ATTR_COHERENT)) + continue; + + if (rpra && rpra[i].buf.len && ctx->overps[oix]->mstart) { + if (map && map->handle) + msm_ion_do_cache_op(ctx->fl->apps->client, + map->handle, + uint64_to_ptr(rpra[i].buf.pv), + rpra[i].buf.len, + ION_IOC_CLEAN_INV_CACHES); + else + dmac_flush_range(uint64_to_ptr(rpra[i].buf.pv), + uint64_to_ptr(rpra[i].buf.pv + + rpra[i].buf.len)); + } + } + PERF_END); + + inh = inbufs + outbufs; + for (i = 0; rpra && i < REMOTE_SCALARS_INHANDLES(sc); i++) { + rpra[inh + i].buf.pv = ptr_to_uint64(ctx->lpra[inh + i].buf.pv); + rpra[inh + i].buf.len = ctx->lpra[inh + i].buf.len; + rpra[inh + i].h = ctx->lpra[inh + i].h; + } + + bail: + return err; +} + +static int put_args(uint32_t kernel, struct smq_invoke_ctx *ctx, + remote_arg_t *upra) +{ + uint32_t sc = ctx->sc; + remote_arg64_t *rpra = ctx->rpra; + int i, inbufs, outbufs, outh, size; + int err = 0; + + inbufs = REMOTE_SCALARS_INBUFS(sc); + outbufs = REMOTE_SCALARS_OUTBUFS(sc); + for (i = inbufs; i < inbufs + outbufs; ++i) { + if (!ctx->maps[i]) { + K_COPY_TO_USER(err, kernel, + ctx->lpra[i].buf.pv, + uint64_to_ptr(rpra[i].buf.pv), + rpra[i].buf.len); + if (err) + goto bail; + } else { + fastrpc_mmap_free(ctx->maps[i]); + ctx->maps[i] = NULL; + } + } + size = sizeof(*rpra) * REMOTE_SCALARS_OUTHANDLES(sc); + if (size) { + outh = inbufs + outbufs + REMOTE_SCALARS_INHANDLES(sc); + K_COPY_TO_USER(err, kernel, &upra[outh], &rpra[outh], size); + if (err) + goto bail; + } + bail: + return err; +} + +static void inv_args_pre(struct smq_invoke_ctx *ctx) +{ + int i, inbufs, outbufs; + uint32_t sc = ctx->sc; + remote_arg64_t *rpra = ctx->rpra; + uintptr_t end; + + inbufs = REMOTE_SCALARS_INBUFS(sc); + outbufs = REMOTE_SCALARS_OUTBUFS(sc); + for (i = inbufs; i < inbufs + outbufs; ++i) { + struct fastrpc_mmap *map = ctx->maps[i]; + + if (map && map->uncached) + continue; + if (!rpra[i].buf.len) + continue; + if (ctx->fl->sctx->smmu.coherent && + !(map && (map->attr & FASTRPC_ATTR_NON_COHERENT))) + continue; + if (map && (map->attr & FASTRPC_ATTR_COHERENT)) + continue; + + if (buf_page_start(ptr_to_uint64((void *)rpra)) == + buf_page_start(rpra[i].buf.pv)) + continue; + if (!IS_CACHE_ALIGNED((uintptr_t) + uint64_to_ptr(rpra[i].buf.pv))) { + if (map && map->handle) + msm_ion_do_cache_op(ctx->fl->apps->client, + map->handle, + uint64_to_ptr(rpra[i].buf.pv), + sizeof(uintptr_t), + ION_IOC_CLEAN_INV_CACHES); + else + dmac_flush_range( + uint64_to_ptr(rpra[i].buf.pv), (char *) + uint64_to_ptr(rpra[i].buf.pv + 1)); + } + + end = (uintptr_t)uint64_to_ptr(rpra[i].buf.pv + + rpra[i].buf.len); + if (!IS_CACHE_ALIGNED(end)) { + if (map && map->handle) + msm_ion_do_cache_op(ctx->fl->apps->client, + map->handle, + uint64_to_ptr(end), + sizeof(uintptr_t), + ION_IOC_CLEAN_INV_CACHES); + else + dmac_flush_range((char *)end, + (char *)end + 1); + } + } +} + +static void inv_args(struct smq_invoke_ctx *ctx) +{ + int i, inbufs, outbufs; + uint32_t sc = ctx->sc; + remote_arg64_t *rpra = ctx->rpra; + int inv = 0; + + inbufs = REMOTE_SCALARS_INBUFS(sc); + outbufs = REMOTE_SCALARS_OUTBUFS(sc); + for (i = inbufs; i < inbufs + outbufs; ++i) { + struct fastrpc_mmap *map = ctx->maps[i]; + + if (map && map->uncached) + continue; + if (!rpra[i].buf.len) + continue; + if (ctx->fl->sctx->smmu.coherent && + !(map && (map->attr & FASTRPC_ATTR_NON_COHERENT))) + continue; + if (map && (map->attr & FASTRPC_ATTR_COHERENT)) + continue; + + if (buf_page_start(ptr_to_uint64((void *)rpra)) == + buf_page_start(rpra[i].buf.pv)) { + inv = 1; + continue; + } + if (map && map->handle) + msm_ion_do_cache_op(ctx->fl->apps->client, map->handle, + (char *)uint64_to_ptr(rpra[i].buf.pv), + rpra[i].buf.len, ION_IOC_INV_CACHES); + else + dmac_inv_range((char *)uint64_to_ptr(rpra[i].buf.pv), + (char *)uint64_to_ptr(rpra[i].buf.pv + + rpra[i].buf.len)); + } + +} + +static int fastrpc_invoke_send(struct smq_invoke_ctx *ctx, + uint32_t kernel, uint32_t handle) +{ + struct smq_msg *msg = &ctx->msg; + struct fastrpc_file *fl = ctx->fl; + struct fastrpc_channel_ctx *channel_ctx = &fl->apps->channel[fl->cid]; + int err = 0, len; + + VERIFY(err, NULL != channel_ctx->chan); + if (err) + goto bail; + msg->pid = current->tgid; + msg->tid = current->pid; + if (kernel) + msg->pid = 0; + msg->invoke.header.ctx = ctx->ctxid | fl->pd; + msg->invoke.header.handle = handle; + msg->invoke.header.sc = ctx->sc; + msg->invoke.page.addr = ctx->buf ? ctx->buf->phys : 0; + msg->invoke.page.size = buf_page_size(ctx->used); + + if (fl->apps->glink) { + if (fl->ssrcount != channel_ctx->ssrcount) { + err = -ECONNRESET; + goto bail; + } + VERIFY(err, channel_ctx->link.port_state == + FASTRPC_LINK_CONNECTED); + if (err) + goto bail; + err = glink_tx(channel_ctx->chan, + (void *)&fl->apps->channel[fl->cid], msg, sizeof(*msg), + GLINK_TX_REQ_INTENT); + } else { + spin_lock(&fl->apps->hlock); + len = smd_write((smd_channel_t *) + channel_ctx->chan, + msg, sizeof(*msg)); + spin_unlock(&fl->apps->hlock); + VERIFY(err, len == sizeof(*msg)); + } + bail: + return err; +} + +static void fastrpc_smd_read_handler(int cid) +{ + struct fastrpc_apps *me = &gfa; + struct smq_invoke_rsp rsp = {0}; + int ret = 0, err = 0; + uint32_t index; + + do { + ret = smd_read_from_cb(me->channel[cid].chan, &rsp, + sizeof(rsp)); + if (ret != sizeof(rsp)) + break; + index = (uint32_t)((rsp.ctx & FASTRPC_CTXID_MASK) >> 4); + VERIFY(err, index < FASTRPC_CTX_MAX); + if (err) + goto bail; + + VERIFY(err, !IS_ERR_OR_NULL(me->ctxtable[index])); + if (err) + goto bail; + + VERIFY(err, ((me->ctxtable[index]->ctxid == (rsp.ctx & ~1)) && + me->ctxtable[index]->magic == FASTRPC_CTX_MAGIC)); + if (err) + goto bail; + + context_notify_user(me->ctxtable[index], rsp.retval); + } while (ret == sizeof(rsp)); + +bail: + if (err) + pr_err("adsprpc: invalid response or context\n"); +} + +static void smd_event_handler(void *priv, unsigned event) +{ + struct fastrpc_apps *me = &gfa; + int cid = (int)(uintptr_t)priv; + + switch (event) { + case SMD_EVENT_OPEN: + complete(&me->channel[cid].workport); + break; + case SMD_EVENT_CLOSE: + fastrpc_notify_drivers(me, cid); + break; + case SMD_EVENT_DATA: + fastrpc_smd_read_handler(cid); + break; + } +} + +static void fastrpc_init(struct fastrpc_apps *me) +{ + int i; + INIT_HLIST_HEAD(&me->drivers); + INIT_HLIST_HEAD(&me->maps); + spin_lock_init(&me->hlock); + spin_lock_init(&me->ctxlock); + mutex_init(&me->smd_mutex); + me->channel = &gcinfo[0]; + for (i = 0; i < NUM_CHANNELS; i++) { + init_completion(&me->channel[i].work); + init_completion(&me->channel[i].workport); + me->channel[i].sesscount = 0; + } +} + +static int fastrpc_release_current_dsp_process(struct fastrpc_file *fl); + +static int fastrpc_internal_invoke(struct fastrpc_file *fl, uint32_t mode, + uint32_t kernel, + struct fastrpc_ioctl_invoke_attrs *inv) +{ + struct smq_invoke_ctx *ctx = NULL; + struct fastrpc_ioctl_invoke *invoke = &inv->inv; + int cid = fl->cid; + int interrupted = 0; + int err = 0; + struct timespec invoket = {0}; + + VERIFY(err, fl->sctx); + if (err) + goto bail; + VERIFY(err, fl->cid >= 0 && fl->cid < NUM_CHANNELS); + if (err) + goto bail; + if (fl->profile) + getnstimeofday(&invoket); + + if (!kernel) { + VERIFY(err, invoke->handle != FASTRPC_STATIC_HANDLE_KERNEL); + if (err) { + pr_err("adsprpc: ERROR: %s: user application %s trying to send a kernel RPC message to channel %d", + __func__, current->comm, cid); + goto bail; + } + } + + VERIFY(err, fl->sctx != NULL); + if (err) + goto bail; + VERIFY(err, fl->cid >= 0 && fl->cid < NUM_CHANNELS); + if (err) + goto bail; + if (!kernel) { + VERIFY(err, 0 == context_restore_interrupted(fl, inv, + &ctx)); + if (err) + goto bail; + if (fl->sctx->smmu.faults) + err = FASTRPC_ENOSUCH; + if (err) + goto bail; + if (ctx) + goto wait; + } + + VERIFY(err, 0 == context_alloc(fl, kernel, inv, &ctx)); + if (err) + goto bail; + + if (REMOTE_SCALARS_LENGTH(ctx->sc)) { + PERF(fl->profile, fl->perf.getargs, + VERIFY(err, 0 == get_args(kernel, ctx)); + PERF_END); + if (err) + goto bail; + } + + PERF(fl->profile, fl->perf.invargs, + inv_args_pre(ctx); + if (mode == FASTRPC_MODE_SERIAL) + inv_args(ctx); + PERF_END); + + PERF(fl->profile, fl->perf.link, + VERIFY(err, 0 == fastrpc_invoke_send(ctx, kernel, invoke->handle)); + PERF_END); + + if (err) + goto bail; + + PERF(fl->profile, fl->perf.invargs, + if (mode == FASTRPC_MODE_PARALLEL) + inv_args(ctx); + PERF_END); + wait: + if (kernel) + wait_for_completion(&ctx->work); + else { + interrupted = wait_for_completion_interruptible(&ctx->work); + VERIFY(err, 0 == (err = interrupted)); + if (err) + goto bail; + } + VERIFY(err, 0 == (err = ctx->retval)); + if (err) + goto bail; + + PERF(fl->profile, fl->perf.putargs, + VERIFY(err, 0 == put_args(kernel, ctx, invoke->pra)); + PERF_END); + if (err) + goto bail; + bail: + if (ctx && interrupted == -ERESTARTSYS) + context_save_interrupted(ctx); + else if (ctx) + context_free(ctx); + if (fl->ssrcount != fl->apps->channel[cid].ssrcount) + err = ECONNRESET; + + if (fl->profile && !interrupted) { + if (invoke->handle != FASTRPC_STATIC_HANDLE_LISTENER) + fl->perf.invoke += getnstimediff(&invoket); + if (!(invoke->handle >= 0 && + invoke->handle <= FASTRPC_STATIC_HANDLE_MAX)) + fl->perf.count++; + } + return err; +} + +static int fastrpc_channel_open(struct fastrpc_file *fl); +static int fastrpc_init_process(struct fastrpc_file *fl, + struct fastrpc_ioctl_init_attrs *uproc) +{ + int err = 0; + struct fastrpc_apps *me = &gfa; + struct fastrpc_ioctl_invoke_attrs ioctl; + struct fastrpc_ioctl_init *init = &uproc->init; + struct smq_phy_page pages[1]; + struct fastrpc_mmap *file = NULL, *mem = NULL; + char *proc_name = NULL; + int srcVM[1] = {VMID_HLOS}; + int destVM[1] = {gcinfo[0].heap_vmid}; + int destVMperm[1] = {PERM_READ | PERM_WRITE | PERM_EXEC}; + int hlosVMperm[1] = {PERM_READ | PERM_WRITE | PERM_EXEC}; + + VERIFY(err, 0 == (err = fastrpc_channel_open(fl))); + if (err) + goto bail; + if (init->flags == FASTRPC_INIT_ATTACH) { + remote_arg_t ra[1]; + int tgid = current->tgid; + ra[0].buf.pv = (void *)&tgid; + ra[0].buf.len = sizeof(tgid); + ioctl.inv.handle = FASTRPC_STATIC_HANDLE_KERNEL; + ioctl.inv.sc = REMOTE_SCALARS_MAKE(0, 1, 0); + ioctl.inv.pra = ra; + ioctl.fds = NULL; + ioctl.attrs = NULL; + fl->pd = 0; + VERIFY(err, !(err = fastrpc_internal_invoke(fl, + FASTRPC_MODE_PARALLEL, 1, &ioctl))); + if (err) + goto bail; + } else if (init->flags == FASTRPC_INIT_CREATE) { + remote_arg_t ra[6]; + int fds[6]; + int mflags = 0; + struct { + int pgid; + unsigned int namelen; + unsigned int filelen; + unsigned int pageslen; + int attrs; + int siglen; + } inbuf; + inbuf.pgid = current->tgid; + inbuf.namelen = strlen(current->comm) + 1; + inbuf.filelen = init->filelen; + fl->pd = 1; + + if (!access_ok(0, (void const __user *)init->file, + init->filelen)) + goto bail; + if (init->filelen) { + VERIFY(err, !fastrpc_mmap_create(fl, init->filefd, 0, + init->file, init->filelen, mflags, &file)); + if (err) + goto bail; + } + if (!access_ok(1, (void const __user *)init->mem, + init->memlen)) + goto bail; + inbuf.pageslen = 1; + VERIFY(err, !fastrpc_mmap_create(fl, init->memfd, 0, + init->mem, init->memlen, mflags, &mem)); + if (err) + goto bail; + inbuf.pageslen = 1; + ra[0].buf.pv = (void *)&inbuf; + ra[0].buf.len = sizeof(inbuf); + fds[0] = 0; + + ra[1].buf.pv = (void *)current->comm; + ra[1].buf.len = inbuf.namelen; + fds[1] = 0; + + ra[2].buf.pv = (void *)init->file; + ra[2].buf.len = inbuf.filelen; + fds[2] = init->filefd; + + pages[0].addr = mem->phys; + pages[0].size = mem->size; + ra[3].buf.pv = (void *)pages; + ra[3].buf.len = 1 * sizeof(*pages); + fds[3] = 0; + + inbuf.attrs = uproc->attrs; + ra[4].buf.pv = (void *)&(inbuf.attrs); + ra[4].buf.len = sizeof(inbuf.attrs); + fds[4] = 0; + + inbuf.siglen = uproc->siglen; + ra[5].buf.pv = (void *)&(inbuf.siglen); + ra[5].buf.len = sizeof(inbuf.siglen); + fds[5] = 0; + + ioctl.inv.handle = FASTRPC_STATIC_HANDLE_KERNEL; + ioctl.inv.sc = REMOTE_SCALARS_MAKE(6, 4, 0); + if (uproc->attrs) + ioctl.inv.sc = REMOTE_SCALARS_MAKE(7, 6, 0); + ioctl.inv.pra = ra; + ioctl.fds = fds; + ioctl.attrs = NULL; + VERIFY(err, !(err = fastrpc_internal_invoke(fl, + FASTRPC_MODE_PARALLEL, 1, &ioctl))); + if (err) + goto bail; + } else if (init->flags == FASTRPC_INIT_CREATE_STATIC) { + remote_arg_t ra[3]; + uint64_t phys = 0; + size_t size = 0; + int fds[3]; + struct { + int pgid; + unsigned int namelen; + unsigned int pageslen; + } inbuf; + + if (!init->filelen) + goto bail; + VERIFY(err, proc_name = kzalloc(init->filelen, GFP_KERNEL)); + if (err) + goto bail; + VERIFY(err, 0 == copy_from_user(proc_name, + (unsigned char *)init->file, init->filelen)); + if (err) + goto bail; + inbuf.pgid = current->tgid; + inbuf.namelen = init->filelen; + inbuf.pageslen = 0; + if (!me->staticpd_flags) { + inbuf.pageslen = 1; + VERIFY(err, !fastrpc_mmap_create(fl, -1, 0, init->mem, + init->memlen, ADSP_MMAP_REMOTE_HEAP_ADDR, + &mem)); + if (err) + goto bail; + phys = mem->phys; + size = mem->size; + VERIFY(err, !hyp_assign_phys(phys, (uint64_t)size, + srcVM, 1, destVM, destVMperm, 1)); + if (err) { + pr_err("ADSPRPC: hyp_assign_phys fail err %d", + err); + pr_err("map->phys %llx, map->size %d\n", + phys, (int)size); + goto bail; + } + me->staticpd_flags = 1; + } + + ra[0].buf.pv = (void *)&inbuf; + ra[0].buf.len = sizeof(inbuf); + fds[0] = 0; + + ra[1].buf.pv = (void *)proc_name; + ra[1].buf.len = inbuf.namelen; + fds[1] = 0; + + pages[0].addr = phys; + pages[0].size = size; + + ra[2].buf.pv = (void *)pages; + ra[2].buf.len = sizeof(*pages); + fds[2] = 0; + ioctl.inv.handle = FASTRPC_STATIC_HANDLE_KERNEL; + + ioctl.inv.sc = REMOTE_SCALARS_MAKE(8, 3, 0); + ioctl.inv.pra = ra; + ioctl.fds = NULL; + ioctl.attrs = NULL; + VERIFY(err, !(err = fastrpc_internal_invoke(fl, + FASTRPC_MODE_PARALLEL, 1, &ioctl))); + if (err) + goto bail; + } else { + err = -ENOTTY; + } +bail: + kfree(proc_name); + if (err && (init->flags == FASTRPC_INIT_CREATE_STATIC)) + me->staticpd_flags = 0; + if (mem && err) { + if (mem->flags == ADSP_MMAP_REMOTE_HEAP_ADDR) + hyp_assign_phys(mem->phys, (uint64_t)mem->size, + destVM, 1, srcVM, hlosVMperm, 1); + fastrpc_mmap_free(mem); + } + if (file) + fastrpc_mmap_free(file); + return err; +} + +static int fastrpc_release_current_dsp_process(struct fastrpc_file *fl) +{ + int err = 0; + struct fastrpc_ioctl_invoke_attrs ioctl; + remote_arg_t ra[1]; + int tgid = 0; + + VERIFY(err, fl->cid >= 0 && fl->cid < NUM_CHANNELS); + if (err) + goto bail; + VERIFY(err, fl->apps->channel[fl->cid].chan != NULL); + if (err) + goto bail; + tgid = fl->tgid; + ra[0].buf.pv = (void *)&tgid; + ra[0].buf.len = sizeof(tgid); + ioctl.inv.handle = FASTRPC_STATIC_HANDLE_KERNEL; + ioctl.inv.sc = REMOTE_SCALARS_MAKE(1, 1, 0); + ioctl.inv.pra = ra; + ioctl.fds = NULL; + ioctl.attrs = NULL; + VERIFY(err, 0 == (err = fastrpc_internal_invoke(fl, + FASTRPC_MODE_PARALLEL, 1, &ioctl))); +bail: + return err; +} + +static int fastrpc_mmap_on_dsp(struct fastrpc_file *fl, uint32_t flags, + struct fastrpc_mmap *map) +{ + struct fastrpc_ioctl_invoke_attrs ioctl; + struct smq_phy_page page; + int num = 1; + remote_arg_t ra[3]; + int err = 0; + struct { + int pid; + uint32_t flags; + uintptr_t vaddrin; + int num; + } inargs; + + struct { + uintptr_t vaddrout; + } routargs; + inargs.pid = current->tgid; + inargs.vaddrin = (uintptr_t)map->va; + inargs.flags = flags; + inargs.num = fl->apps->compat ? num * sizeof(page) : num; + ra[0].buf.pv = (void *)&inargs; + ra[0].buf.len = sizeof(inargs); + page.addr = map->phys; + page.size = map->size; + ra[1].buf.pv = (void *)&page; + ra[1].buf.len = num * sizeof(page); + + ra[2].buf.pv = (void *)&routargs; + ra[2].buf.len = sizeof(routargs); + + ioctl.inv.handle = FASTRPC_STATIC_HANDLE_KERNEL; + if (fl->apps->compat) + ioctl.inv.sc = REMOTE_SCALARS_MAKE(4, 2, 1); + else + ioctl.inv.sc = REMOTE_SCALARS_MAKE(2, 2, 1); + ioctl.inv.pra = ra; + ioctl.fds = NULL; + ioctl.attrs = NULL; + VERIFY(err, 0 == (err = fastrpc_internal_invoke(fl, + FASTRPC_MODE_PARALLEL, 1, &ioctl))); + map->raddr = (uintptr_t)routargs.vaddrout; + if (err) + goto bail; + if (flags == ADSP_MMAP_HEAP_ADDR) { + struct scm_desc desc = {0}; + + desc.args[0] = TZ_PIL_AUTH_QDSP6_PROC; + desc.args[1] = map->phys; + desc.args[2] = map->size; + desc.arginfo = SCM_ARGS(3); + err = scm_call2(SCM_SIP_FNID(SCM_SVC_PIL, + TZ_PIL_PROTECT_MEM_SUBSYS_ID), &desc); + } else if (flags == ADSP_MMAP_REMOTE_HEAP_ADDR) { + + int srcVM[1] = {VMID_HLOS}; + int destVM[1] = {gcinfo[0].heap_vmid}; + int destVMperm[1] = {PERM_READ | PERM_WRITE | PERM_EXEC}; + + VERIFY(err, !hyp_assign_phys(map->phys, (uint64_t)map->size, + srcVM, 1, destVM, destVMperm, 1)); + if (err) + goto bail; + } +bail: + return err; +} + +static int fastrpc_munmap_on_dsp_rh(struct fastrpc_file *fl, + struct fastrpc_mmap *map) +{ + int err = 0; + int srcVM[1] = {gcinfo[0].heap_vmid}; + int destVM[1] = {VMID_HLOS}; + int destVMperm[1] = {PERM_READ | PERM_WRITE | PERM_EXEC}; + + if (map->flags == ADSP_MMAP_HEAP_ADDR) { + struct fastrpc_ioctl_invoke_attrs ioctl; + struct scm_desc desc = {0}; + remote_arg_t ra[1]; + int err = 0; + struct { + uint8_t skey; + } routargs; + + ra[0].buf.pv = (void *)&routargs; + ra[0].buf.len = sizeof(routargs); + + ioctl.inv.handle = FASTRPC_STATIC_HANDLE_KERNEL; + ioctl.inv.sc = REMOTE_SCALARS_MAKE(7, 0, 1); + ioctl.inv.pra = ra; + ioctl.fds = NULL; + ioctl.attrs = NULL; + if (fl == NULL) + goto bail; + + VERIFY(err, 0 == (err = fastrpc_internal_invoke(fl, + FASTRPC_MODE_PARALLEL, 1, &ioctl))); + if (err) + goto bail; + desc.args[0] = TZ_PIL_AUTH_QDSP6_PROC; + desc.args[1] = map->phys; + desc.args[2] = map->size; + desc.args[3] = routargs.skey; + desc.arginfo = SCM_ARGS(4); + err = scm_call2(SCM_SIP_FNID(SCM_SVC_PIL, + TZ_PIL_CLEAR_PROTECT_MEM_SUBSYS_ID), &desc); + } else if (map->flags == ADSP_MMAP_REMOTE_HEAP_ADDR) { + VERIFY(err, !hyp_assign_phys(map->phys, (uint64_t)map->size, + srcVM, 1, destVM, destVMperm, 1)); + if (err) + goto bail; + } + +bail: + return err; +} + +static int fastrpc_munmap_on_dsp(struct fastrpc_file *fl, + struct fastrpc_mmap *map) +{ + struct fastrpc_ioctl_invoke_attrs ioctl; + remote_arg_t ra[1]; + int err = 0; + struct { + int pid; + uintptr_t vaddrout; + size_t size; + } inargs; + + inargs.pid = current->tgid; + inargs.size = map->size; + inargs.vaddrout = map->raddr; + ra[0].buf.pv = (void *)&inargs; + ra[0].buf.len = sizeof(inargs); + + ioctl.inv.handle = FASTRPC_STATIC_HANDLE_KERNEL; + if (fl->apps->compat) + ioctl.inv.sc = REMOTE_SCALARS_MAKE(5, 1, 0); + else + ioctl.inv.sc = REMOTE_SCALARS_MAKE(3, 1, 0); + ioctl.inv.pra = ra; + ioctl.fds = NULL; + ioctl.attrs = NULL; + VERIFY(err, 0 == (err = fastrpc_internal_invoke(fl, + FASTRPC_MODE_PARALLEL, 1, &ioctl))); + if (err) + goto bail; + if (map->flags == ADSP_MMAP_HEAP_ADDR || + map->flags == ADSP_MMAP_REMOTE_HEAP_ADDR) { + VERIFY(err, !fastrpc_munmap_on_dsp_rh(fl, map)); + if (err) + goto bail; + } +bail: + return err; +} + +static int fastrpc_mmap_remove_ssr(struct fastrpc_file *fl) +{ + struct fastrpc_mmap *match = NULL, *map = NULL; + struct hlist_node *n = NULL; + int err = 0, ret = 0; + struct fastrpc_apps *me = &gfa; + struct ramdump_segment *ramdump_segments_rh = NULL; + + do { + match = NULL; + spin_lock(&me->hlock); + hlist_for_each_entry_safe(map, n, &me->maps, hn) { + match = map; + hlist_del_init(&map->hn); + break; + } + spin_unlock(&me->hlock); + + if (match) { + VERIFY(err, !fastrpc_munmap_on_dsp_rh(fl, match)); + if (err) + goto bail; + if (me->channel[0].ramdumpenabled) { + ramdump_segments_rh = kcalloc(1, + sizeof(struct ramdump_segment), GFP_KERNEL); + if (ramdump_segments_rh) { + ramdump_segments_rh->address = + match->phys; + ramdump_segments_rh->size = match->size; + ret = do_elf_ramdump( + me->channel[0].remoteheap_ramdump_dev, + ramdump_segments_rh, 1); + if (ret < 0) + pr_err("ADSPRPC: unable to dump heap"); + kfree(ramdump_segments_rh); + } + } + fastrpc_mmap_free(match); + } + } while (match); +bail: + if (err && match) + fastrpc_mmap_add(match); + return err; +} + +static int fastrpc_mmap_remove(struct fastrpc_file *fl, uintptr_t va, + size_t len, struct fastrpc_mmap **ppmap); + +static void fastrpc_mmap_add(struct fastrpc_mmap *map); + +static int fastrpc_internal_munmap(struct fastrpc_file *fl, + struct fastrpc_ioctl_munmap *ud) +{ + int err = 0; + struct fastrpc_mmap *map = NULL; + + mutex_lock(&fl->map_mutex); + VERIFY(err, !fastrpc_mmap_remove(fl, ud->vaddrout, ud->size, &map)); + if (err) + goto bail; + VERIFY(err, !fastrpc_munmap_on_dsp(fl, map)); + if (err) + goto bail; + fastrpc_mmap_free(map); +bail: + if (err && map) + fastrpc_mmap_add(map); + mutex_unlock(&fl->map_mutex); + return err; +} + +static int fastrpc_internal_mmap(struct fastrpc_file *fl, + struct fastrpc_ioctl_mmap *ud) +{ + + struct fastrpc_mmap *map = NULL; + int err = 0; + + mutex_lock(&fl->map_mutex); + if (!fastrpc_mmap_find(fl, ud->fd, (uintptr_t)ud->vaddrin, ud->size, + ud->flags, &map)){ + mutex_unlock(&fl->map_mutex); + return 0; + } + VERIFY(err, !fastrpc_mmap_create(fl, ud->fd, 0, + (uintptr_t)ud->vaddrin, ud->size, ud->flags, &map)); + if (err) + goto bail; + VERIFY(err, 0 == fastrpc_mmap_on_dsp(fl, ud->flags, map)); + if (err) + goto bail; + ud->vaddrout = map->raddr; + bail: + if (err && map) + fastrpc_mmap_free(map); + mutex_unlock(&fl->map_mutex); + return err; +} + +static void fastrpc_channel_close(struct kref *kref) +{ + struct fastrpc_apps *me = &gfa; + struct fastrpc_channel_ctx *ctx; + int cid; + + ctx = container_of(kref, struct fastrpc_channel_ctx, kref); + cid = ctx - &gcinfo[0]; + if (!me->glink) + smd_close(ctx->chan); + else + fastrpc_glink_close(ctx->chan, cid); + + ctx->chan = NULL; + mutex_unlock(&me->smd_mutex); + pr_info("'closed /dev/%s c %d %d'\n", gcinfo[cid].name, + MAJOR(me->dev_no), cid); +} + +static void fastrpc_context_list_dtor(struct fastrpc_file *fl); + +static int fastrpc_session_alloc_locked(struct fastrpc_channel_ctx *chan, + int secure, struct fastrpc_session_ctx **session) +{ + struct fastrpc_apps *me = &gfa; + int idx = 0, err = 0; + + if (chan->sesscount) { + for (idx = 0; idx < chan->sesscount; ++idx) { + if (!chan->session[idx].used && + chan->session[idx].smmu.secure == secure) { + chan->session[idx].used = 1; + break; + } + } + VERIFY(err, idx < chan->sesscount); + if (err) + goto bail; + chan->session[idx].smmu.faults = 0; + } else { + VERIFY(err, me->dev != NULL); + if (err) + goto bail; + chan->session[0].dev = me->dev; + chan->session[0].smmu.dev = me->dev; + } + + *session = &chan->session[idx]; + bail: + return err; +} + +static bool fastrpc_glink_notify_rx_intent_req(void *h, const void *priv, + size_t size) +{ + if (glink_queue_rx_intent(h, NULL, size)) + return false; + return true; +} + +static void fastrpc_glink_notify_tx_done(void *handle, const void *priv, + const void *pkt_priv, const void *ptr) +{ +} + +static void fastrpc_glink_notify_rx(void *handle, const void *priv, + const void *pkt_priv, const void *ptr, size_t size) +{ + struct smq_invoke_rsp *rsp = (struct smq_invoke_rsp *)ptr; + struct fastrpc_apps *me = &gfa; + uint32_t index; + int err = 0; + + VERIFY(err, (rsp && size >= sizeof(*rsp))); + if (err) + goto bail; + + index = (uint32_t)((rsp->ctx & FASTRPC_CTXID_MASK) >> 4); + VERIFY(err, index < FASTRPC_CTX_MAX); + if (err) + goto bail; + + VERIFY(err, !IS_ERR_OR_NULL(me->ctxtable[index])); + if (err) + goto bail; + + VERIFY(err, ((me->ctxtable[index]->ctxid == (rsp->ctx & ~1)) && + me->ctxtable[index]->magic == FASTRPC_CTX_MAGIC)); + if (err) + goto bail; + + context_notify_user(me->ctxtable[index], rsp->retval); +bail: + if (err) + pr_err("adsprpc: invalid response or context\n"); + glink_rx_done(handle, ptr, true); +} + +static void fastrpc_glink_notify_state(void *handle, const void *priv, + unsigned int event) +{ + struct fastrpc_apps *me = &gfa; + int cid = (int)(uintptr_t)priv; + struct fastrpc_glink_info *link; + + if (cid < 0 || cid >= NUM_CHANNELS) + return; + link = &me->channel[cid].link; + switch (event) { + case GLINK_CONNECTED: + link->port_state = FASTRPC_LINK_CONNECTED; + complete(&me->channel[cid].workport); + break; + case GLINK_LOCAL_DISCONNECTED: + link->port_state = FASTRPC_LINK_DISCONNECTED; + break; + case GLINK_REMOTE_DISCONNECTED: + if (me->channel[cid].chan) { + fastrpc_glink_close(me->channel[cid].chan, cid); + me->channel[cid].chan = 0; + } + break; + default: + break; + } +} + +static int fastrpc_session_alloc(struct fastrpc_channel_ctx *chan, int secure, + struct fastrpc_session_ctx **session) +{ + int err = 0; + struct fastrpc_apps *me = &gfa; + + mutex_lock(&me->smd_mutex); + if (!*session) + err = fastrpc_session_alloc_locked(chan, secure, session); + mutex_unlock(&me->smd_mutex); + return err; +} + +static void fastrpc_session_free(struct fastrpc_channel_ctx *chan, + struct fastrpc_session_ctx *session) +{ + struct fastrpc_apps *me = &gfa; + + mutex_lock(&me->smd_mutex); + session->used = 0; + mutex_unlock(&me->smd_mutex); +} + +static int fastrpc_file_free(struct fastrpc_file *fl) +{ + struct hlist_node *n; + struct fastrpc_mmap *map = NULL; + int cid; + + if (!fl) + return 0; + cid = fl->cid; + + (void)fastrpc_release_current_dsp_process(fl); + + spin_lock(&fl->apps->hlock); + hlist_del_init(&fl->hn); + spin_unlock(&fl->apps->hlock); + + if (!fl->sctx) { + goto bail; + } + + spin_lock(&fl->hlock); + fl->file_close = 1; + spin_unlock(&fl->hlock); + fastrpc_context_list_dtor(fl); + fastrpc_buf_list_free(fl); + hlist_for_each_entry_safe(map, n, &fl->maps, hn) { + fastrpc_mmap_free(map); + } + if (fl->ssrcount == fl->apps->channel[cid].ssrcount) + kref_put_mutex(&fl->apps->channel[cid].kref, + fastrpc_channel_close, &fl->apps->smd_mutex); + if (fl->sctx) + fastrpc_session_free(&fl->apps->channel[cid], fl->sctx); + if (fl->secsctx) + fastrpc_session_free(&fl->apps->channel[cid], fl->secsctx); +bail: + mutex_destroy(&fl->map_mutex); + kfree(fl); + return 0; +} + +static int fastrpc_device_release(struct inode *inode, struct file *file) +{ + struct fastrpc_file *fl = (struct fastrpc_file *)file->private_data; + + if (fl) { + if (fl->debugfs_file != NULL) + debugfs_remove(fl->debugfs_file); + + fastrpc_file_free(fl); + file->private_data = NULL; + } + return 0; +} + +static void fastrpc_link_state_handler(struct glink_link_state_cb_info *cb_info, + void *priv) +{ + struct fastrpc_apps *me = &gfa; + int cid = (int)((uintptr_t)priv); + struct fastrpc_glink_info *link; + + if (cid < 0 || cid >= NUM_CHANNELS) + return; + + link = &me->channel[cid].link; + switch (cb_info->link_state) { + case GLINK_LINK_STATE_UP: + link->link_state = FASTRPC_LINK_STATE_UP; + complete(&me->channel[cid].work); + break; + case GLINK_LINK_STATE_DOWN: + link->link_state = FASTRPC_LINK_STATE_DOWN; + break; + default: + pr_err("adsprpc: unknown link state %d\n", cb_info->link_state); + break; + } +} + +static int fastrpc_glink_register(int cid, struct fastrpc_apps *me) +{ + int err = 0; + struct fastrpc_glink_info *link; + + VERIFY(err, (cid >= 0 && cid < NUM_CHANNELS)); + if (err) + goto bail; + + link = &me->channel[cid].link; + if (link->link_notify_handle != NULL) + goto bail; + + link->link_info.glink_link_state_notif_cb = fastrpc_link_state_handler; + link->link_notify_handle = glink_register_link_state_cb( + &link->link_info, + (void *)((uintptr_t)cid)); + VERIFY(err, !IS_ERR_OR_NULL(me->channel[cid].link.link_notify_handle)); + if (err) { + link->link_notify_handle = NULL; + goto bail; + } + VERIFY(err, wait_for_completion_timeout(&me->channel[cid].work, + RPC_TIMEOUT)); +bail: + return err; +} + +static void fastrpc_glink_close(void *chan, int cid) +{ + int err = 0; + struct fastrpc_glink_info *link; + + VERIFY(err, (cid >= 0 && cid < NUM_CHANNELS)); + if (err) + return; + link = &gfa.channel[cid].link; + + if (link->port_state == FASTRPC_LINK_CONNECTED) { + link->port_state = FASTRPC_LINK_DISCONNECTING; + glink_close(chan); + } +} + +static int fastrpc_glink_open(int cid) +{ + int err = 0; + void *handle = NULL; + struct fastrpc_apps *me = &gfa; + struct glink_open_config *cfg; + struct fastrpc_glink_info *link; + + VERIFY(err, (cid >= 0 && cid < NUM_CHANNELS)); + if (err) + goto bail; + link = &me->channel[cid].link; + cfg = &me->channel[cid].link.cfg; + VERIFY(err, (link->link_state == FASTRPC_LINK_STATE_UP)); + if (err) + goto bail; + + VERIFY(err, (link->port_state == FASTRPC_LINK_DISCONNECTED)); + if (err) + goto bail; + + link->port_state = FASTRPC_LINK_CONNECTING; + cfg->priv = (void *)(uintptr_t)cid; + cfg->edge = gcinfo[cid].link.link_info.edge; + cfg->transport = gcinfo[cid].link.link_info.transport; + cfg->name = FASTRPC_GLINK_GUID; + cfg->notify_rx = fastrpc_glink_notify_rx; + cfg->notify_tx_done = fastrpc_glink_notify_tx_done; + cfg->notify_state = fastrpc_glink_notify_state; + cfg->notify_rx_intent_req = fastrpc_glink_notify_rx_intent_req; + handle = glink_open(cfg); + VERIFY(err, !IS_ERR_OR_NULL(handle)); + if (err) + goto bail; + me->channel[cid].chan = handle; +bail: + return err; +} + +static int fastrpc_debugfs_open(struct inode *inode, struct file *filp) +{ + filp->private_data = inode->i_private; + return 0; +} + +static ssize_t fastrpc_debugfs_read(struct file *filp, char __user *buffer, + size_t count, loff_t *position) +{ + struct fastrpc_file *fl = filp->private_data; + struct hlist_node *n; + struct fastrpc_buf *buf = NULL; + struct fastrpc_mmap *map = NULL; + struct smq_invoke_ctx *ictx = NULL; + struct fastrpc_channel_ctx *chan; + struct fastrpc_session_ctx *sess; + unsigned int len = 0; + int i, j, ret = 0; + char *fileinfo = NULL; + + fileinfo = kzalloc(DEBUGFS_SIZE, GFP_KERNEL); + if (!fileinfo) + goto bail; + if (fl == NULL) { + for (i = 0; i < NUM_CHANNELS; i++) { + chan = &gcinfo[i]; + len += scnprintf(fileinfo + len, + DEBUGFS_SIZE - len, "%s\n\n", + chan->name); + len += scnprintf(fileinfo + len, + DEBUGFS_SIZE - len, "%s %d\n", + "sesscount:", chan->sesscount); + for (j = 0; j < chan->sesscount; j++) { + sess = &chan->session[j]; + len += scnprintf(fileinfo + len, + DEBUGFS_SIZE - len, + "%s%d\n\n", "SESSION", j); + len += scnprintf(fileinfo + len, + DEBUGFS_SIZE - len, + "%s %d\n", "sid:", + sess->smmu.cb); + len += scnprintf(fileinfo + len, + DEBUGFS_SIZE - len, + "%s %d\n", "SECURE:", + sess->smmu.secure); + } + } + } else { + len += scnprintf(fileinfo + len, DEBUGFS_SIZE - len, + "%s %d\n\n", + "PROCESS_ID:", fl->tgid); + len += scnprintf(fileinfo + len, DEBUGFS_SIZE - len, + "%s %d\n\n", + "CHANNEL_ID:", fl->cid); + len += scnprintf(fileinfo + len, DEBUGFS_SIZE - len, + "%s %d\n\n", + "SSRCOUNT:", fl->ssrcount); + len += scnprintf(fileinfo + len, DEBUGFS_SIZE - len, + "%s\n", + "LIST OF BUFS:"); + spin_lock(&fl->hlock); + hlist_for_each_entry_safe(buf, n, &fl->bufs, hn) { + len += scnprintf(fileinfo + len, DEBUGFS_SIZE - len, + "%s %pK %s %pK %s %llx\n", "buf:", + buf, "buf->virt:", buf->virt, + "buf->phys:", buf->phys); + } + len += scnprintf(fileinfo + len, DEBUGFS_SIZE - len, + "\n%s\n", + "LIST OF MAPS:"); + hlist_for_each_entry_safe(map, n, &fl->maps, hn) { + len += scnprintf(fileinfo + len, DEBUGFS_SIZE - len, + "%s %pK %s %lx %s %llx\n", + "map:", map, + "map->va:", map->va, + "map->phys:", map->phys); + } + len += scnprintf(fileinfo + len, DEBUGFS_SIZE - len, + "\n%s\n", + "LIST OF PENDING SMQCONTEXTS:"); + hlist_for_each_entry_safe(ictx, n, &fl->clst.pending, hn) { + len += scnprintf(fileinfo + len, DEBUGFS_SIZE - len, + "%s %pK %s %u %s %u %s %u\n", + "smqcontext:", ictx, + "sc:", ictx->sc, + "tid:", ictx->pid, + "handle", ictx->rpra->h); + } + len += scnprintf(fileinfo + len, DEBUGFS_SIZE - len, + "\n%s\n", + "LIST OF INTERRUPTED SMQCONTEXTS:"); + hlist_for_each_entry_safe(ictx, n, &fl->clst.interrupted, hn) { + len += scnprintf(fileinfo + len, DEBUGFS_SIZE - len, + "%s %pK %s %u %s %u %s %u\n", + "smqcontext:", ictx, + "sc:", ictx->sc, + "tid:", ictx->pid, + "handle", ictx->rpra->h); + } + spin_unlock(&fl->hlock); + } + if (len > DEBUGFS_SIZE) + len = DEBUGFS_SIZE; + ret = simple_read_from_buffer(buffer, count, position, fileinfo, len); + kfree(fileinfo); +bail: + return ret; +} + +static const struct file_operations debugfs_fops = { + .open = fastrpc_debugfs_open, + .read = fastrpc_debugfs_read, +}; +static int fastrpc_channel_open(struct fastrpc_file *fl) +{ + struct fastrpc_apps *me = &gfa; + int cid, err = 0; + + mutex_lock(&me->smd_mutex); + + VERIFY(err, fl && fl->sctx); + if (err) + goto bail; + cid = fl->cid; + VERIFY(err, cid >= 0 && cid < NUM_CHANNELS); + if (err) + goto bail; + if (me->channel[cid].ssrcount != + me->channel[cid].prevssrcount) { + if (!me->channel[cid].issubsystemup) { + VERIFY(err, 0); + if (err) + goto bail; + } + } + fl->ssrcount = me->channel[cid].ssrcount; + if ((kref_get_unless_zero(&me->channel[cid].kref) == 0) || + (me->channel[cid].chan == NULL)) { + if (me->glink) { + VERIFY(err, 0 == fastrpc_glink_register(cid, me)); + if (err) + goto bail; + VERIFY(err, 0 == fastrpc_glink_open(cid)); + } else { + VERIFY(err, !smd_named_open_on_edge(FASTRPC_SMD_GUID, + gcinfo[cid].channel, + (smd_channel_t **)&me->channel[cid].chan, + (void *)(uintptr_t)cid, + smd_event_handler)); + } + if (err) + goto bail; + + VERIFY(err, + wait_for_completion_timeout(&me->channel[cid].workport, + RPC_TIMEOUT)); + if (err) { + me->channel[cid].chan = NULL; + goto bail; + } + kref_init(&me->channel[cid].kref); + pr_info("'opened /dev/%s c %d %d'\n", gcinfo[cid].name, + MAJOR(me->dev_no), cid); + + if (me->glink) { + err = glink_queue_rx_intent(me->channel[cid].chan, + NULL, 16); + err |= glink_queue_rx_intent(me->channel[cid].chan, + NULL, 64); + if (err) + pr_warn("adsprpc: intent fail for %d err %d\n", + cid, err); + } + if (cid == 0 && me->channel[cid].ssrcount != + me->channel[cid].prevssrcount) { + if (fastrpc_mmap_remove_ssr(fl)) + pr_err("ADSPRPC: SSR: Failed to unmap remote heap\n"); + me->channel[cid].prevssrcount = + me->channel[cid].ssrcount; + } + } + +bail: + mutex_unlock(&me->smd_mutex); + return err; +} + +static int fastrpc_device_open(struct inode *inode, struct file *filp) +{ + int err = 0; + struct dentry *debugfs_file; + struct fastrpc_file *fl = NULL; + struct fastrpc_apps *me = &gfa; + + VERIFY(err, NULL != (fl = kzalloc(sizeof(*fl), GFP_KERNEL))); + if (err) + return err; + debugfs_file = debugfs_create_file(current->comm, 0644, debugfs_root, + fl, &debugfs_fops); + context_list_ctor(&fl->clst); + spin_lock_init(&fl->hlock); + INIT_HLIST_HEAD(&fl->maps); + INIT_HLIST_HEAD(&fl->bufs); + INIT_HLIST_NODE(&fl->hn); + fl->tgid = current->tgid; + fl->apps = me; + fl->mode = FASTRPC_MODE_SERIAL; + fl->cid = -1; + if (debugfs_file != NULL) + fl->debugfs_file = debugfs_file; + memset(&fl->perf, 0, sizeof(fl->perf)); + filp->private_data = fl; + mutex_init(&fl->map_mutex); + spin_lock(&me->hlock); + hlist_add_head(&fl->hn, &me->drivers); + spin_unlock(&me->hlock); + return 0; +} + +static int fastrpc_get_info(struct fastrpc_file *fl, uint32_t *info) +{ + int err = 0; + uint32_t cid; + + VERIFY(err, fl != NULL); + if (err) + goto bail; + if (fl->cid == -1) { + cid = *info; + VERIFY(err, cid < NUM_CHANNELS); + if (err) + goto bail; + fl->cid = cid; + fl->ssrcount = fl->apps->channel[cid].ssrcount; + VERIFY(err, !fastrpc_session_alloc_locked( + &fl->apps->channel[cid], 0, &fl->sctx)); + if (err) + goto bail; + } + if (fl->sctx) + *info = (fl->sctx->smmu.enabled ? 1 : 0); +bail: + return err; +} + +static long fastrpc_device_ioctl(struct file *file, unsigned int ioctl_num, + unsigned long ioctl_param) +{ + union { + struct fastrpc_ioctl_invoke_attrs inv; + struct fastrpc_ioctl_mmap mmap; + struct fastrpc_ioctl_munmap munmap; + struct fastrpc_ioctl_init_attrs init; + struct fastrpc_ioctl_perf perf; + } p; + void *param = (char *)ioctl_param; + struct fastrpc_file *fl = (struct fastrpc_file *)file->private_data; + int size = 0, err = 0; + uint32_t info; + + p.inv.fds = NULL; + p.inv.attrs = NULL; + spin_lock(&fl->hlock); + if (fl->file_close == 1) { + err = EBADF; + pr_warn("ADSPRPC: fastrpc_device_release is happening, So not sending any new requests to DSP"); + spin_unlock(&fl->hlock); + goto bail; + } + spin_unlock(&fl->hlock); + + switch (ioctl_num) { + case FASTRPC_IOCTL_INVOKE: + size = sizeof(struct fastrpc_ioctl_invoke); + case FASTRPC_IOCTL_INVOKE_FD: + if (!size) + size = sizeof(struct fastrpc_ioctl_invoke_fd); + /* fall through */ + case FASTRPC_IOCTL_INVOKE_ATTRS: + if (!size) + size = sizeof(struct fastrpc_ioctl_invoke_attrs); + K_COPY_FROM_USER(err, 0, &p.inv, param, size); + if (err) + goto bail; + VERIFY(err, 0 == (err = fastrpc_internal_invoke(fl, fl->mode, + 0, &p.inv))); + if (err) + goto bail; + break; + case FASTRPC_IOCTL_MMAP: + K_COPY_FROM_USER(err, 0, &p.mmap, param, + sizeof(p.mmap)); + if (err) + goto bail; + VERIFY(err, 0 == (err = fastrpc_internal_mmap(fl, &p.mmap))); + if (err) + goto bail; + K_COPY_TO_USER(err, 0, param, &p.mmap, sizeof(p.mmap)); + if (err) + goto bail; + break; + case FASTRPC_IOCTL_MUNMAP: + K_COPY_FROM_USER(err, 0, &p.munmap, param, + sizeof(p.munmap)); + if (err) + goto bail; + VERIFY(err, 0 == (err = fastrpc_internal_munmap(fl, + &p.munmap))); + if (err) + goto bail; + break; + case FASTRPC_IOCTL_SETMODE: + switch ((uint32_t)ioctl_param) { + case FASTRPC_MODE_PARALLEL: + case FASTRPC_MODE_SERIAL: + fl->mode = (uint32_t)ioctl_param; + break; + case FASTRPC_MODE_PROFILE: + fl->profile = (uint32_t)ioctl_param; + break; + default: + err = -ENOTTY; + break; + } + break; + case FASTRPC_IOCTL_GETPERF: + K_COPY_FROM_USER(err, 0, &p.perf, + param, sizeof(p.perf)); + if (err) + goto bail; + p.perf.numkeys = sizeof(struct fastrpc_perf)/sizeof(int64_t); + if (p.perf.keys) { + char *keys = PERF_KEYS; + + K_COPY_TO_USER(err, 0, (void *)p.perf.keys, + keys, strlen(keys)+1); + if (err) + goto bail; + } + if (p.perf.data) { + K_COPY_TO_USER(err, 0, (void *)p.perf.data, + &fl->perf, sizeof(fl->perf)); + } + K_COPY_TO_USER(err, 0, param, &p.perf, sizeof(p.perf)); + if (err) + goto bail; + break; + case FASTRPC_IOCTL_GETINFO: + K_COPY_FROM_USER(err, 0, &info, param, sizeof(info)); + if (err) + goto bail; + VERIFY(err, 0 == (err = fastrpc_get_info(fl, &info))); + if (err) + goto bail; + K_COPY_TO_USER(err, 0, param, &info, sizeof(info)); + if (err) + goto bail; + break; + case FASTRPC_IOCTL_INIT: + p.init.attrs = 0; + p.init.siglen = 0; + size = sizeof(struct fastrpc_ioctl_init); + /* fall through */ + case FASTRPC_IOCTL_INIT_ATTRS: + if (!size) + size = sizeof(struct fastrpc_ioctl_init_attrs); + K_COPY_FROM_USER(err, 0, &p.init, param, size); + if (err) + goto bail; + VERIFY(err, p.init.init.filelen >= 0 && + p.init.init.memlen >= 0); + if (err) + goto bail; + VERIFY(err, 0 == fastrpc_init_process(fl, &p.init)); + if (err) + goto bail; + break; + + default: + err = -ENOTTY; + pr_info("bad ioctl: %d\n", ioctl_num); + break; + } + bail: + return err; +} + +static int fastrpc_restart_notifier_cb(struct notifier_block *nb, + unsigned long code, + void *data) +{ + struct fastrpc_apps *me = &gfa; + struct fastrpc_channel_ctx *ctx; + struct notif_data *notifdata = data; + int cid; + + ctx = container_of(nb, struct fastrpc_channel_ctx, nb); + cid = ctx - &me->channel[0]; + if (code == SUBSYS_BEFORE_SHUTDOWN) { + mutex_lock(&me->smd_mutex); + ctx->ssrcount++; + ctx->issubsystemup = 0; + if (ctx->chan) { + if (me->glink) + fastrpc_glink_close(ctx->chan, cid); + else + smd_close(ctx->chan); + + ctx->chan = 0; + pr_info("'restart notifier: closed /dev/%s c %d %d'\n", + gcinfo[cid].name, MAJOR(me->dev_no), cid); + } + mutex_unlock(&me->smd_mutex); + if (cid == 0) + me->staticpd_flags = 0; + fastrpc_notify_drivers(me, cid); + } else if (code == SUBSYS_RAMDUMP_NOTIFICATION) { + if (me->channel[0].remoteheap_ramdump_dev && + notifdata->enable_ramdump) { + me->channel[0].ramdumpenabled = 1; + } + } else if (code == SUBSYS_AFTER_POWERUP) { + ctx->issubsystemup = 1; + } + + return NOTIFY_DONE; +} + +static int fastrpc_smmu_fault_handler(struct iommu_domain *domain, + struct device *dev, unsigned long iova, int flags, void *token) +{ + struct fastrpc_session_ctx *sess = (struct fastrpc_session_ctx *)token; + int err = 0; + + VERIFY(err, sess != NULL); + if (err) + return err; + sess->smmu.faults++; + dev_err(dev, "ADSPRPC context fault: iova=0x%08lx, cb = %d, faults=%d", + iova, sess->smmu.cb, sess->smmu.faults); + return 0; +} + +static const struct file_operations fops = { + .open = fastrpc_device_open, + .release = fastrpc_device_release, + .unlocked_ioctl = fastrpc_device_ioctl, + .compat_ioctl = compat_fastrpc_device_ioctl, +}; + +static struct of_device_id fastrpc_match_table[] = { + { .compatible = "qcom,msm-fastrpc-adsp", }, + { .compatible = "qcom,msm-fastrpc-compute-cb", }, + { .compatible = "qcom,msm-fastrpc-legacy-compute-cb", }, + { .compatible = "qcom,msm-adsprpc-mem-region", }, + {} +}; + +static int fastrpc_cb_probe(struct device *dev) +{ + struct fastrpc_channel_ctx *chan; + struct fastrpc_session_ctx *sess; + struct of_phandle_args iommuspec; + const char *name; + unsigned int start = 0x80000000; + int err = 0, i; + int secure_vmid = VMID_CP_PIXEL; + + VERIFY(err, NULL != (name = of_get_property(dev->of_node, + "label", NULL))); + if (err) + goto bail; + for (i = 0; i < NUM_CHANNELS; i++) { + if (!gcinfo[i].name) + continue; + if (!strcmp(name, gcinfo[i].name)) + break; + } + VERIFY(err, i < NUM_CHANNELS); + if (err) + goto bail; + chan = &gcinfo[i]; + VERIFY(err, chan->sesscount < NUM_SESSIONS); + if (err) + goto bail; + + VERIFY(err, !of_parse_phandle_with_args(dev->of_node, "iommus", + "#iommu-cells", 0, &iommuspec)); + if (err) + goto bail; + sess = &chan->session[chan->sesscount]; + sess->smmu.cb = iommuspec.args[0]; + sess->used = 0; + sess->smmu.coherent = of_property_read_bool(dev->of_node, + "dma-coherent"); + sess->smmu.secure = of_property_read_bool(dev->of_node, + "qcom,secure-context-bank"); + if (sess->smmu.secure) + start = 0x60000000; + VERIFY(err, !IS_ERR_OR_NULL(sess->smmu.mapping = + arm_iommu_create_mapping(&platform_bus_type, + start, 0x70000000))); + if (err) + goto bail; + iommu_set_fault_handler(sess->smmu.mapping->domain, + fastrpc_smmu_fault_handler, sess); + if (sess->smmu.secure) + iommu_domain_set_attr(sess->smmu.mapping->domain, + DOMAIN_ATTR_SECURE_VMID, + &secure_vmid); + + VERIFY(err, !arm_iommu_attach_device(dev, sess->smmu.mapping)); + if (err) + goto bail; + sess->smmu.dev = dev; + sess->smmu.enabled = 1; + chan->sesscount++; + debugfs_global_file = debugfs_create_file("global", 0644, debugfs_root, + NULL, &debugfs_fops); + +bail: + return err; +} + +static int fastrpc_cb_legacy_probe(struct device *dev) +{ + struct device_node *domains_child_node = NULL; + struct device_node *ctx_node = NULL; + struct fastrpc_channel_ctx *chan; + struct fastrpc_session_ctx *first_sess, *sess; + const char *name; + unsigned int *range = NULL, range_size = 0; + unsigned int *sids = NULL, sids_size = 0; + int err = 0, ret = 0, i; + + VERIFY(err, 0 != (domains_child_node = of_get_child_by_name( + dev->of_node, + "qcom,msm_fastrpc_compute_cb"))); + if (err) + goto bail; + VERIFY(err, 0 != (ctx_node = of_parse_phandle( + domains_child_node, + "qcom,adsp-shared-phandle", 0))); + if (err) + goto bail; + VERIFY(err, 0 != of_get_property(domains_child_node, + "qcom,adsp-shared-sids", &sids_size)); + if (err) + goto bail; + VERIFY(err, sids = kzalloc(sids_size, GFP_KERNEL)); + if (err) + goto bail; + ret = of_property_read_u32_array(domains_child_node, + "qcom,adsp-shared-sids", + sids, + sids_size/sizeof(unsigned int)); + if (ret) + goto bail; + VERIFY(err, 0 != (name = of_get_property(ctx_node, "label", NULL))); + if (err) + goto bail; + VERIFY(err, 0 != of_get_property(domains_child_node, + "qcom,virtual-addr-pool", &range_size)); + if (err) + goto bail; + VERIFY(err, range = kzalloc(range_size, GFP_KERNEL)); + if (err) + goto bail; + ret = of_property_read_u32_array(domains_child_node, + "qcom,virtual-addr-pool", + range, + range_size/sizeof(unsigned int)); + if (ret) + goto bail; + + chan = &gcinfo[0]; + VERIFY(err, chan->sesscount < NUM_SESSIONS); + if (err) + goto bail; + first_sess = &chan->session[chan->sesscount]; + first_sess->smmu.dev = msm_iommu_get_ctx(name); + VERIFY(err, !IS_ERR_OR_NULL(first_sess->smmu.mapping = + arm_iommu_create_mapping( + msm_iommu_get_bus(first_sess->smmu.dev), + range[0], range[1]))); + if (err) + goto bail; + VERIFY(err, !arm_iommu_attach_device(first_sess->dev, + first_sess->smmu.mapping)); + if (err) + goto bail; + for (i = 0; i < sids_size/sizeof(unsigned int); i++) { + VERIFY(err, chan->sesscount < NUM_SESSIONS); + if (err) + goto bail; + sess = &chan->session[chan->sesscount]; + sess->smmu.cb = sids[i]; + sess->smmu.dev = first_sess->smmu.dev; + sess->smmu.enabled = 1; + sess->smmu.mapping = first_sess->smmu.mapping; + chan->sesscount++; + } +bail: + kfree(sids); + kfree(range); + return err; +} + +static int fastrpc_probe(struct platform_device *pdev) +{ + int err = 0; + struct fastrpc_apps *me = &gfa; + struct device *dev = &pdev->dev; + + if (of_device_is_compatible(dev->of_node, + "qcom,msm-fastrpc-compute-cb")) + return fastrpc_cb_probe(dev); + + if (of_device_is_compatible(dev->of_node, + "qcom,msm-fastrpc-legacy-compute-cb")) + return fastrpc_cb_legacy_probe(dev); + + if (of_device_is_compatible(dev->of_node, + "qcom,msm-adsprpc-mem-region")) { + me->dev = dev; + me->channel[0].remoteheap_ramdump_dev = + create_ramdump_device("adsp_rh", dev); + if (IS_ERR_OR_NULL(me->channel[0].remoteheap_ramdump_dev)) { + pr_err("ADSPRPC: Unable to create adsp-remoteheap ramdump device.\n"); + me->channel[0].remoteheap_ramdump_dev = NULL; + } + return 0; + } + if (of_property_read_bool(dev->of_node, + "qcom,fastrpc-vmid-heap-shared")) + gcinfo[0].heap_vmid = AC_VM_ADSP_HEAP_SHARED; + else + gcinfo[0].heap_vmid = VMID_ADSP_Q6; + pr_info("ADSPRPC: gcinfo[0].heap_vmid %d\n", gcinfo[0].heap_vmid); + me->glink = of_property_read_bool(dev->of_node, "qcom,fastrpc-glink"); + VERIFY(err, !of_platform_populate(pdev->dev.of_node, + fastrpc_match_table, + NULL, &pdev->dev)); + if (err) + goto bail; +bail: + return err; +} + +static void fastrpc_deinit(void) +{ + struct fastrpc_apps *me = &gfa; + struct fastrpc_channel_ctx *chan = gcinfo; + int i, j; + + for (i = 0; i < NUM_CHANNELS; i++, chan++) { + if (chan->chan) { + kref_put_mutex(&chan->kref, + fastrpc_channel_close, &me->smd_mutex); + chan->chan = NULL; + } + for (j = 0; j < NUM_SESSIONS; j++) { + struct fastrpc_session_ctx *sess = &chan->session[j]; + if (sess->smmu.dev) { + arm_iommu_detach_device(sess->smmu.dev); + sess->smmu.dev = NULL; + } + if (sess->smmu.mapping) { + arm_iommu_release_mapping(sess->smmu.mapping); + sess->smmu.mapping = NULL; + } + } + } +} + +static struct platform_driver fastrpc_driver = { + .probe = fastrpc_probe, + .driver = { + .name = "fastrpc", + .owner = THIS_MODULE, + .of_match_table = fastrpc_match_table, + }, +}; + +static int __init fastrpc_device_init(void) +{ + struct fastrpc_apps *me = &gfa; + struct device *dev = NULL; + int err = 0, i; + + memset(me, 0, sizeof(*me)); + + fastrpc_init(me); + me->dev = NULL; + VERIFY(err, 0 == platform_driver_register(&fastrpc_driver)); + if (err) + goto register_bail; + VERIFY(err, 0 == alloc_chrdev_region(&me->dev_no, 0, NUM_CHANNELS, + DEVICE_NAME)); + if (err) + goto alloc_chrdev_bail; + cdev_init(&me->cdev, &fops); + me->cdev.owner = THIS_MODULE; + VERIFY(err, 0 == cdev_add(&me->cdev, MKDEV(MAJOR(me->dev_no), 0), + 1)); + if (err) + goto cdev_init_bail; + me->class = class_create(THIS_MODULE, "fastrpc"); + VERIFY(err, !IS_ERR(me->class)); + if (err) + goto class_create_bail; + me->compat = (NULL == fops.compat_ioctl) ? 0 : 1; + dev = device_create(me->class, NULL, + MKDEV(MAJOR(me->dev_no), 0), + NULL, gcinfo[0].name); + VERIFY(err, !IS_ERR_OR_NULL(dev)); + if (err) + goto device_create_bail; + for (i = 0; i < NUM_CHANNELS; i++) { + me->channel[i].dev = dev; + me->channel[i].ssrcount = 0; + me->channel[i].prevssrcount = 0; + me->channel[i].issubsystemup = 1; + me->channel[i].ramdumpenabled = 0; + me->channel[i].remoteheap_ramdump_dev = NULL; + me->channel[i].nb.notifier_call = fastrpc_restart_notifier_cb; + me->channel[i].handle = subsys_notif_register_notifier( + gcinfo[i].subsys, + &me->channel[i].nb); + } + + me->client = msm_ion_client_create(DEVICE_NAME); + VERIFY(err, !IS_ERR_OR_NULL(me->client)); + if (err) + goto device_create_bail; + debugfs_root = debugfs_create_dir("adsprpc", NULL); + return 0; +device_create_bail: + for (i = 0; i < NUM_CHANNELS; i++) { + if (me->channel[i].handle) + subsys_notif_unregister_notifier(me->channel[i].handle, + &me->channel[i].nb); + } + if (!IS_ERR_OR_NULL(dev)) + device_destroy(me->class, MKDEV(MAJOR(me->dev_no), 0)); + class_destroy(me->class); +class_create_bail: + cdev_del(&me->cdev); +cdev_init_bail: + unregister_chrdev_region(me->dev_no, NUM_CHANNELS); +alloc_chrdev_bail: +register_bail: + fastrpc_deinit(); + return err; +} + +static void __exit fastrpc_device_exit(void) +{ + struct fastrpc_apps *me = &gfa; + int i; + + fastrpc_file_list_dtor(me); + fastrpc_deinit(); + for (i = 0; i < NUM_CHANNELS; i++) { + if (!gcinfo[i].name) + continue; + device_destroy(me->class, MKDEV(MAJOR(me->dev_no), i)); + subsys_notif_unregister_notifier(me->channel[i].handle, + &me->channel[i].nb); + } + class_destroy(me->class); + cdev_del(&me->cdev); + unregister_chrdev_region(me->dev_no, NUM_CHANNELS); + ion_client_destroy(me->client); + debugfs_remove_recursive(debugfs_root); +} + +late_initcall(fastrpc_device_init); +module_exit(fastrpc_device_exit); + +MODULE_LICENSE("GPL v2"); --- /dev/null 2019-10-24 16:47:25.704025805 +0200 +++ linux-4.4.115-fbx/drivers/char/adsprpc_compat.c 2019-01-22 16:16:22.943241335 +0100 @@ -0,0 +1,436 @@ +/* + * Copyright (c) 2014-2017, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include +#include +#include +#include + +#include "adsprpc_compat.h" +#include "adsprpc_shared.h" + +#define COMPAT_FASTRPC_IOCTL_INVOKE \ + _IOWR('R', 1, struct compat_fastrpc_ioctl_invoke) +#define COMPAT_FASTRPC_IOCTL_MMAP \ + _IOWR('R', 2, struct compat_fastrpc_ioctl_mmap) +#define COMPAT_FASTRPC_IOCTL_MUNMAP \ + _IOWR('R', 3, struct compat_fastrpc_ioctl_munmap) +#define COMPAT_FASTRPC_IOCTL_INVOKE_FD \ + _IOWR('R', 4, struct compat_fastrpc_ioctl_invoke_fd) +#define COMPAT_FASTRPC_IOCTL_INIT \ + _IOWR('R', 6, struct compat_fastrpc_ioctl_init) +#define COMPAT_FASTRPC_IOCTL_INVOKE_ATTRS \ + _IOWR('R', 7, struct compat_fastrpc_ioctl_invoke_attrs) +#define COMPAT_FASTRPC_IOCTL_GETPERF \ + _IOWR('R', 9, struct compat_fastrpc_ioctl_perf) +#define COMPAT_FASTRPC_IOCTL_INIT_ATTRS \ + _IOWR('R', 10, struct compat_fastrpc_ioctl_init_attrs) + +struct compat_remote_buf { + compat_uptr_t pv; /* buffer pointer */ + compat_size_t len; /* length of buffer */ +}; + +union compat_remote_arg { + struct compat_remote_buf buf; + compat_uint_t h; +}; + +struct compat_fastrpc_ioctl_invoke { + compat_uint_t handle; /* remote handle */ + compat_uint_t sc; /* scalars describing the data */ + compat_uptr_t pra; /* remote arguments list */ +}; + +struct compat_fastrpc_ioctl_invoke_fd { + struct compat_fastrpc_ioctl_invoke inv; + compat_uptr_t fds; /* fd list */ +}; + +struct compat_fastrpc_ioctl_invoke_attrs { + struct compat_fastrpc_ioctl_invoke inv; + compat_uptr_t fds; /* fd list */ + compat_uptr_t attrs; /* attribute list */ +}; + +struct compat_fastrpc_ioctl_mmap { + compat_int_t fd; /* ion fd */ + compat_uint_t flags; /* flags for dsp to map with */ + compat_uptr_t vaddrin; /* optional virtual address */ + compat_size_t size; /* size */ + compat_uptr_t vaddrout; /* dsps virtual address */ +}; + +struct compat_fastrpc_ioctl_munmap { + compat_uptr_t vaddrout; /* address to unmap */ + compat_size_t size; /* size */ +}; + +struct compat_fastrpc_ioctl_init { + compat_uint_t flags; /* one of FASTRPC_INIT_* macros */ + compat_uptr_t file; /* pointer to elf file */ + compat_int_t filelen; /* elf file length */ + compat_int_t filefd; /* ION fd for the file */ + compat_uptr_t mem; /* mem for the PD */ + compat_int_t memlen; /* mem length */ + compat_int_t memfd; /* ION fd for the mem */ +}; + +struct compat_fastrpc_ioctl_init_attrs { + struct compat_fastrpc_ioctl_init init; + compat_int_t attrs; /* attributes to init process */ + compat_int_t siglen; /* test signature file length */ +}; + +struct compat_fastrpc_ioctl_perf { /* kernel performance data */ + compat_uptr_t data; + compat_int_t numkeys; + compat_uptr_t keys; +}; + +static int compat_get_fastrpc_ioctl_invoke( + struct compat_fastrpc_ioctl_invoke_attrs __user *inv32, + struct fastrpc_ioctl_invoke_attrs __user **inva, + unsigned int cmd) +{ + compat_uint_t u, sc; + compat_size_t s; + compat_uptr_t p; + struct fastrpc_ioctl_invoke_attrs *inv; + union compat_remote_arg *pra32; + union remote_arg *pra; + int err, len, num, j; + + err = get_user(sc, &inv32->inv.sc); + if (err) + return err; + + len = REMOTE_SCALARS_LENGTH(sc); + VERIFY(err, NULL != (inv = compat_alloc_user_space( + sizeof(*inv) + len * sizeof(*pra)))); + if (err) + return -EFAULT; + + pra = (union remote_arg *)(inv + 1); + err = put_user(pra, &inv->inv.pra); + err |= put_user(sc, &inv->inv.sc); + err |= get_user(u, &inv32->inv.handle); + err |= put_user(u, &inv->inv.handle); + err |= get_user(p, &inv32->inv.pra); + if (err) + return err; + + pra32 = compat_ptr(p); + pra = (union remote_arg *)(inv + 1); + num = REMOTE_SCALARS_INBUFS(sc) + REMOTE_SCALARS_OUTBUFS(sc); + for (j = 0; j < num; j++) { + err |= get_user(p, &pra32[j].buf.pv); + err |= put_user(p, (uintptr_t *)&pra[j].buf.pv); + err |= get_user(s, &pra32[j].buf.len); + err |= put_user(s, &pra[j].buf.len); + } + for (j = 0; j < REMOTE_SCALARS_INHANDLES(sc); j++) { + err |= get_user(u, &pra32[num + j].h); + err |= put_user(u, &pra[num + j].h); + } + + err |= put_user(NULL, &inv->fds); + if (cmd != COMPAT_FASTRPC_IOCTL_INVOKE) { + err |= get_user(p, &inv32->fds); + err |= put_user(p, (compat_uptr_t *)&inv->fds); + } + err |= put_user(NULL, &inv->attrs); + if (cmd == COMPAT_FASTRPC_IOCTL_INVOKE_ATTRS) { + err |= get_user(p, &inv32->attrs); + err |= put_user(p, (compat_uptr_t *)&inv->attrs); + } + + *inva = inv; + return err; +} + +static int compat_put_fastrpc_ioctl_invoke( + struct compat_fastrpc_ioctl_invoke_attrs __user *inv32, + struct fastrpc_ioctl_invoke_attrs __user *inv) +{ + compat_uptr_t p; + compat_uint_t u, h; + union compat_remote_arg *pra32; + union remote_arg *pra; + int err, i, num; + + err = get_user(u, &inv32->inv.sc); + err |= get_user(p, &inv32->inv.pra); + if (err) + return err; + + pra32 = compat_ptr(p); + pra = (union remote_arg *)(inv + 1); + num = REMOTE_SCALARS_INBUFS(u) + REMOTE_SCALARS_OUTBUFS(u) + + REMOTE_SCALARS_INHANDLES(u); + for (i = 0; i < REMOTE_SCALARS_OUTHANDLES(u); i++) { + err |= get_user(h, &pra[num + i].h); + err |= put_user(h, &pra32[num + i].h); + } + + return err; +} + +static int compat_get_fastrpc_ioctl_mmap( + struct compat_fastrpc_ioctl_mmap __user *map32, + struct fastrpc_ioctl_mmap __user *map) +{ + compat_uint_t u; + compat_int_t i; + compat_size_t s; + compat_uptr_t p; + int err; + + err = get_user(i, &map32->fd); + err |= put_user(i, &map->fd); + err |= get_user(u, &map32->flags); + err |= put_user(u, &map->flags); + err |= get_user(p, &map32->vaddrin); + err |= put_user(p, (uintptr_t *)&map->vaddrin); + err |= get_user(s, &map32->size); + err |= put_user(s, &map->size); + + return err; +} + +static int compat_put_fastrpc_ioctl_mmap( + struct compat_fastrpc_ioctl_mmap __user *map32, + struct fastrpc_ioctl_mmap __user *map) +{ + compat_uptr_t p; + int err; + + err = get_user(p, &map->vaddrout); + err |= put_user(p, &map32->vaddrout); + + return err; +} + +static int compat_get_fastrpc_ioctl_munmap( + struct compat_fastrpc_ioctl_munmap __user *unmap32, + struct fastrpc_ioctl_munmap __user *unmap) +{ + compat_uptr_t p; + compat_size_t s; + int err; + + err = get_user(p, &unmap32->vaddrout); + err |= put_user(p, &unmap->vaddrout); + err |= get_user(s, &unmap32->size); + err |= put_user(s, &unmap->size); + + return err; +} + +static int compat_get_fastrpc_ioctl_perf( + struct compat_fastrpc_ioctl_perf __user *perf32, + struct fastrpc_ioctl_perf __user *perf) +{ + compat_uptr_t p; + int err; + + err = get_user(p, &perf32->data); + err |= put_user(p, &perf->data); + err |= get_user(p, &perf32->keys); + err |= put_user(p, &perf->keys); + + return err; +} + +static int compat_get_fastrpc_ioctl_init( + struct compat_fastrpc_ioctl_init_attrs __user *init32, + struct fastrpc_ioctl_init_attrs __user *init, + unsigned int cmd) +{ + compat_uint_t u; + compat_uptr_t p; + compat_int_t i; + int err; + + err = get_user(u, &init32->init.flags); + err |= put_user(u, &init->init.flags); + err |= get_user(p, &init32->init.file); + err |= put_user(p, &init->init.file); + err |= get_user(i, &init32->init.filelen); + err |= put_user(i, &init->init.filelen); + err |= get_user(i, &init32->init.filefd); + err |= put_user(i, &init->init.filefd); + err |= get_user(p, &init32->init.mem); + err |= put_user(p, &init->init.mem); + err |= get_user(i, &init32->init.memlen); + err |= put_user(i, &init->init.memlen); + err |= get_user(i, &init32->init.memfd); + err |= put_user(i, &init->init.memfd); + + err |= put_user(0, &init->attrs); + if (cmd == COMPAT_FASTRPC_IOCTL_INIT_ATTRS) { + err |= get_user(i, &init32->attrs); + err |= put_user(i, (compat_uptr_t *)&init->attrs); + } + + err |= put_user(0, &init->siglen); + if (cmd == COMPAT_FASTRPC_IOCTL_INIT_ATTRS) { + err |= get_user(i, &init32->siglen); + err |= put_user(i, (compat_uptr_t *)&init->siglen); + } + + return err; +} + +long compat_fastrpc_device_ioctl(struct file *filp, unsigned int cmd, + unsigned long arg) +{ + int err = 0; + + if (!filp->f_op || !filp->f_op->unlocked_ioctl) + return -ENOTTY; + + switch (cmd) { + case COMPAT_FASTRPC_IOCTL_INVOKE: + case COMPAT_FASTRPC_IOCTL_INVOKE_FD: + case COMPAT_FASTRPC_IOCTL_INVOKE_ATTRS: + { + struct compat_fastrpc_ioctl_invoke_attrs __user *inv32; + struct fastrpc_ioctl_invoke_attrs __user *inv; + long ret; + + inv32 = compat_ptr(arg); + VERIFY(err, 0 == compat_get_fastrpc_ioctl_invoke(inv32, + &inv, cmd)); + if (err) + return err; + ret = filp->f_op->unlocked_ioctl(filp, + FASTRPC_IOCTL_INVOKE_ATTRS, (unsigned long)inv); + if (ret) + return ret; + VERIFY(err, 0 == compat_put_fastrpc_ioctl_invoke(inv32, inv)); + return err; + } + case COMPAT_FASTRPC_IOCTL_MMAP: + { + struct compat_fastrpc_ioctl_mmap __user *map32; + struct fastrpc_ioctl_mmap __user *map; + long ret; + + map32 = compat_ptr(arg); + VERIFY(err, NULL != (map = compat_alloc_user_space( + sizeof(*map)))); + if (err) + return -EFAULT; + VERIFY(err, 0 == compat_get_fastrpc_ioctl_mmap(map32, map)); + if (err) + return err; + ret = filp->f_op->unlocked_ioctl(filp, FASTRPC_IOCTL_MMAP, + (unsigned long)map); + if (ret) + return ret; + VERIFY(err, 0 == compat_put_fastrpc_ioctl_mmap(map32, map)); + return err; + } + case COMPAT_FASTRPC_IOCTL_MUNMAP: + { + struct compat_fastrpc_ioctl_munmap __user *unmap32; + struct fastrpc_ioctl_munmap __user *unmap; + + unmap32 = compat_ptr(arg); + VERIFY(err, NULL != (unmap = compat_alloc_user_space( + sizeof(*unmap)))); + if (err) + return -EFAULT; + VERIFY(err, 0 == compat_get_fastrpc_ioctl_munmap(unmap32, + unmap)); + if (err) + return err; + return filp->f_op->unlocked_ioctl(filp, FASTRPC_IOCTL_MUNMAP, + (unsigned long)unmap); + } + case COMPAT_FASTRPC_IOCTL_INIT: + /* fall through */ + case COMPAT_FASTRPC_IOCTL_INIT_ATTRS: + { + struct compat_fastrpc_ioctl_init_attrs __user *init32; + struct fastrpc_ioctl_init_attrs __user *init; + + init32 = compat_ptr(arg); + VERIFY(err, NULL != (init = compat_alloc_user_space( + sizeof(*init)))); + if (err) + return -EFAULT; + VERIFY(err, 0 == compat_get_fastrpc_ioctl_init(init32, + init, cmd)); + if (err) + return err; + return filp->f_op->unlocked_ioctl(filp, + FASTRPC_IOCTL_INIT_ATTRS, (unsigned long)init); + } + case FASTRPC_IOCTL_GETINFO: + { + compat_uptr_t __user *info32; + uint32_t __user *info; + compat_uint_t u; + long ret; + + info32 = compat_ptr(arg); + VERIFY(err, NULL != (info = compat_alloc_user_space( + sizeof(*info)))); + if (err) + return -EFAULT; + err = get_user(u, info32); + err |= put_user(u, info); + if (err) + return err; + ret = filp->f_op->unlocked_ioctl(filp, FASTRPC_IOCTL_GETINFO, + (unsigned long)info); + if (ret) + return ret; + err = get_user(u, info); + err |= put_user(u, info32); + return err; + } + case FASTRPC_IOCTL_SETMODE: + return filp->f_op->unlocked_ioctl(filp, cmd, + (unsigned long)compat_ptr(arg)); + case COMPAT_FASTRPC_IOCTL_GETPERF: + { + struct compat_fastrpc_ioctl_perf __user *perf32; + struct fastrpc_ioctl_perf *perf; + compat_uint_t u; + long ret; + + perf32 = compat_ptr(arg); + VERIFY(err, NULL != (perf = compat_alloc_user_space( + sizeof(*perf)))); + if (err) + return -EFAULT; + VERIFY(err, 0 == compat_get_fastrpc_ioctl_perf(perf32, + perf)); + if (err) + return err; + ret = filp->f_op->unlocked_ioctl(filp, FASTRPC_IOCTL_GETPERF, + (unsigned long)perf); + if (ret) + return ret; + err = get_user(u, &perf->numkeys); + err |= put_user(u, &perf32->numkeys); + return err; + } + default: + return -ENOIOCTLCMD; + } +} --- /dev/null 2019-10-24 16:47:25.704025805 +0200 +++ linux-4.4.115-fbx/drivers/char/adsprpc_compat.h 2019-01-22 16:16:22.943241335 +0100 @@ -0,0 +1,26 @@ +/* + * Copyright (c) 2014 The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ +#ifndef ADSPRPC_COMPAT_H +#define ADSPRPC_COMPAT_H + +#ifdef CONFIG_COMPAT + +long compat_fastrpc_device_ioctl(struct file *filp, unsigned int cmd, + unsigned long arg); +#else + +#define compat_fastrpc_device_ioctl NULL + +#endif /* CONFIG_COMPAT */ +#endif /* ADSPRPC_COMPAT_H */ --- /dev/null 2019-10-24 16:47:25.704025805 +0200 +++ linux-4.4.115-fbx/drivers/char/adsprpc_shared.h 2019-01-22 16:16:22.943241335 +0100 @@ -0,0 +1,235 @@ +/* + * Copyright (c) 2012-2017, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ +#ifndef ADSPRPC_SHARED_H +#define ADSPRPC_SHARED_H + +#include + +#define FASTRPC_IOCTL_INVOKE _IOWR('R', 1, struct fastrpc_ioctl_invoke) +#define FASTRPC_IOCTL_MMAP _IOWR('R', 2, struct fastrpc_ioctl_mmap) +#define FASTRPC_IOCTL_MUNMAP _IOWR('R', 3, struct fastrpc_ioctl_munmap) +#define FASTRPC_IOCTL_INVOKE_FD _IOWR('R', 4, struct fastrpc_ioctl_invoke_fd) +#define FASTRPC_IOCTL_SETMODE _IOWR('R', 5, uint32_t) +#define FASTRPC_IOCTL_INIT _IOWR('R', 6, struct fastrpc_ioctl_init) +#define FASTRPC_IOCTL_INVOKE_ATTRS \ + _IOWR('R', 7, struct fastrpc_ioctl_invoke_attrs) +#define FASTRPC_IOCTL_GETINFO _IOWR('R', 8, uint32_t) +#define FASTRPC_IOCTL_GETPERF _IOWR('R', 9, struct fastrpc_ioctl_perf) +#define FASTRPC_IOCTL_INIT_ATTRS _IOWR('R', 10, struct fastrpc_ioctl_init_attrs) + +#define FASTRPC_GLINK_GUID "fastrpcglink-apps-dsp" +#define FASTRPC_SMD_GUID "fastrpcsmd-apps-dsp" +#define DEVICE_NAME "adsprpc-smd" + +/* Set for buffers that have no virtual mapping in userspace */ +#define FASTRPC_ATTR_NOVA 0x1 + +/* Set for buffers that are NOT dma coherent */ +#define FASTRPC_ATTR_NON_COHERENT 0x2 + +/* Set for buffers that are dma coherent */ +#define FASTRPC_ATTR_COHERENT 0x4 + +/* Driver should operate in parallel with the co-processor */ +#define FASTRPC_MODE_PARALLEL 0 + +/* Driver should operate in serial mode with the co-processor */ +#define FASTRPC_MODE_SERIAL 1 + +/* Driver should operate in profile mode with the co-processor */ +#define FASTRPC_MODE_PROFILE 2 + +/* INIT a new process or attach to guestos */ +#define FASTRPC_INIT_ATTACH 0 +#define FASTRPC_INIT_CREATE 1 +#define FASTRPC_INIT_CREATE_STATIC 2 + +/* Retrives number of input buffers from the scalars parameter */ +#define REMOTE_SCALARS_INBUFS(sc) (((sc) >> 16) & 0x0ff) + +/* Retrives number of output buffers from the scalars parameter */ +#define REMOTE_SCALARS_OUTBUFS(sc) (((sc) >> 8) & 0x0ff) + +/* Retrives number of input handles from the scalars parameter */ +#define REMOTE_SCALARS_INHANDLES(sc) (((sc) >> 4) & 0x0f) + +/* Retrives number of output handles from the scalars parameter */ +#define REMOTE_SCALARS_OUTHANDLES(sc) ((sc) & 0x0f) + +#define REMOTE_SCALARS_LENGTH(sc) (REMOTE_SCALARS_INBUFS(sc) +\ + REMOTE_SCALARS_OUTBUFS(sc) +\ + REMOTE_SCALARS_INHANDLES(sc) +\ + REMOTE_SCALARS_OUTHANDLES(sc)) + +#define REMOTE_SCALARS_MAKEX(attr, method, in, out, oin, oout) \ + ((((uint32_t) (attr) & 0x7) << 29) | \ + (((uint32_t) (method) & 0x1f) << 24) | \ + (((uint32_t) (in) & 0xff) << 16) | \ + (((uint32_t) (out) & 0xff) << 8) | \ + (((uint32_t) (oin) & 0x0f) << 4) | \ + ((uint32_t) (oout) & 0x0f)) + +#define REMOTE_SCALARS_MAKE(method, in, out) \ + REMOTE_SCALARS_MAKEX(0, method, in, out, 0, 0) + + +#ifndef VERIFY_PRINT_ERROR +#define VERIFY_EPRINTF(format, args) (void)0 +#endif + +#ifndef VERIFY_PRINT_INFO +#define VERIFY_IPRINTF(args) (void)0 +#endif + +#ifndef VERIFY +#define __STR__(x) #x ":" +#define __TOSTR__(x) __STR__(x) +#define __FILE_LINE__ __FILE__ ":" __TOSTR__(__LINE__) + +#define VERIFY(err, val) \ +do {\ + VERIFY_IPRINTF(__FILE_LINE__"info: calling: " #val "\n");\ + if (0 == (val)) {\ + (err) = (err) == 0 ? -1 : (err);\ + VERIFY_EPRINTF(__FILE_LINE__"error: %d: " #val "\n", (err));\ + } else {\ + VERIFY_IPRINTF(__FILE_LINE__"info: passed: " #val "\n");\ + } \ +} while (0) +#endif + +#define remote_arg64_t union remote_arg64 + +struct remote_buf64 { + uint64_t pv; + uint64_t len; +}; + +union remote_arg64 { + struct remote_buf64 buf; + uint32_t h; +}; + +#define remote_arg_t union remote_arg + +struct remote_buf { + void *pv; /* buffer pointer */ + size_t len; /* length of buffer */ +}; + +union remote_arg { + struct remote_buf buf; /* buffer info */ + uint32_t h; /* remote handle */ +}; + +struct fastrpc_ioctl_invoke { + uint32_t handle; /* remote handle */ + uint32_t sc; /* scalars describing the data */ + remote_arg_t *pra; /* remote arguments list */ +}; + +struct fastrpc_ioctl_invoke_fd { + struct fastrpc_ioctl_invoke inv; + int *fds; /* fd list */ +}; + +struct fastrpc_ioctl_invoke_attrs { + struct fastrpc_ioctl_invoke inv; + int *fds; /* fd list */ + unsigned *attrs; /* attribute list */ +}; + +struct fastrpc_ioctl_init { + uint32_t flags; /* one of FASTRPC_INIT_* macros */ + uintptr_t file; /* pointer to elf file */ + uint32_t filelen; /* elf file length */ + int32_t filefd; /* ION fd for the file */ + uintptr_t mem; /* mem for the PD */ + uint32_t memlen; /* mem length */ + int32_t memfd; /* ION fd for the mem */ +}; + +struct fastrpc_ioctl_init_attrs { + struct fastrpc_ioctl_init init; + int attrs; + unsigned int siglen; +}; + +struct fastrpc_ioctl_munmap { + uintptr_t vaddrout; /* address to unmap */ + size_t size; /* size */ +}; + +struct fastrpc_ioctl_mmap { + int fd; /* ion fd */ + uint32_t flags; /* flags for dsp to map with */ + uintptr_t vaddrin; /* optional virtual address */ + size_t size; /* size */ + uintptr_t vaddrout; /* dsps virtual address */ +}; + +struct fastrpc_ioctl_perf { /* kernel performance data */ + uintptr_t data; + uint32_t numkeys; + uintptr_t keys; +}; + +struct smq_null_invoke { + uint64_t ctx; /* invoke caller context */ + uint32_t handle; /* handle to invoke */ + uint32_t sc; /* scalars structure describing the data */ +}; + +struct smq_phy_page { + uint64_t addr; /* physical address */ + uint64_t size; /* size of contiguous region */ +}; + +struct smq_invoke_buf { + int num; /* number of contiguous regions */ + int pgidx; /* index to start of contiguous region */ +}; + +struct smq_invoke { + struct smq_null_invoke header; + struct smq_phy_page page; /* remote arg and list of pages address */ +}; + +struct smq_msg { + uint32_t pid; /* process group id */ + uint32_t tid; /* thread id */ + struct smq_invoke invoke; +}; + +struct smq_invoke_rsp { + uint64_t ctx; /* invoke caller context */ + int retval; /* invoke return value */ +}; + +static inline struct smq_invoke_buf *smq_invoke_buf_start(remote_arg64_t *pra, + uint32_t sc) +{ + unsigned int len = REMOTE_SCALARS_LENGTH(sc); + + return (struct smq_invoke_buf *)(&pra[len]); +} + +static inline struct smq_phy_page *smq_phy_page_start(uint32_t sc, + struct smq_invoke_buf *buf) +{ + uint64_t nTotal = REMOTE_SCALARS_INBUFS(sc)+REMOTE_SCALARS_OUTBUFS(sc); + return (struct smq_phy_page *)(&buf[nTotal]); +} + +#endif diff -Nruw linux-4.4.115-fbx/drivers/char/diag./diagchar_core.c linux-4.4.115-fbx/drivers/char/diag/diagchar_core.c --- linux-4.4.115-fbx/drivers/char/diag./diagchar_core.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-4.4.115-fbx/drivers/char/diag/diagchar_core.c 2019-10-29 09:26:23.449201280 +0100 @@ -0,0 +1,3890 @@ +/* Copyright (c) 2008-2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#ifdef CONFIG_DIAG_OVER_USB +#include +#endif +#include +#include "diagchar_hdlc.h" +#include "diagmem.h" +#include "diagchar.h" +#include "diagfwd.h" +#include "diagfwd_cntl.h" +#include "diag_dci.h" +#include "diag_debugfs.h" +#include "diag_masks.h" +#include "diagfwd_bridge.h" +#include "diag_usb.h" +#include "diag_memorydevice.h" +#include "diag_mux.h" +#include "diag_ipc_logging.h" +#include "diagfwd_peripheral.h" + +#include +#include +#ifdef CONFIG_COMPAT +#include +#endif + +MODULE_DESCRIPTION("Diag Char Driver"); +MODULE_LICENSE("GPL v2"); +MODULE_VERSION("1.0"); + +#define MIN_SIZ_ALLOW 4 +#define INIT 1 +#define EXIT -1 +struct diagchar_dev *driver; +struct diagchar_priv { + int pid; +}; + +#define USER_SPACE_RAW_DATA 0 +#define USER_SPACE_HDLC_DATA 1 + +/* Memory pool variables */ +/* Used for copying any incoming packet from user space clients. */ +static unsigned int poolsize = 12; +module_param(poolsize, uint, 0); + +/* + * Used for HDLC encoding packets coming from the user + * space. + */ +static unsigned int poolsize_hdlc = 10; +module_param(poolsize_hdlc, uint, 0); + +/* + * This is used for incoming DCI requests from the user space clients. + * Don't expose itemsize as it is internal. + */ +static unsigned int poolsize_user = 8; +module_param(poolsize_user, uint, 0); + +/* + * USB structures allocated for writing Diag data generated on the Apps to USB. + * Don't expose itemsize as it is constant. + */ +static unsigned int itemsize_usb_apps = sizeof(struct diag_request); +static unsigned int poolsize_usb_apps = 10; +module_param(poolsize_usb_apps, uint, 0); + +/* Used for DCI client buffers. Don't expose itemsize as it is constant. */ +static unsigned int poolsize_dci = 10; +module_param(poolsize_dci, uint, 0); + +#ifdef CONFIG_DIAGFWD_BRIDGE_CODE +/* Used for reading data from the remote device. */ +static unsigned int itemsize_mdm = DIAG_MDM_BUF_SIZE; +static unsigned int poolsize_mdm = 18; +module_param(itemsize_mdm, uint, 0); +module_param(poolsize_mdm, uint, 0); + +/* + * Used for reading DCI data from the remote device. + * Don't expose poolsize for DCI data. There is only one read buffer + */ +static unsigned int itemsize_mdm_dci = DIAG_MDM_BUF_SIZE; +static unsigned int poolsize_mdm_dci = 1; +module_param(itemsize_mdm_dci, uint, 0); + +/* + * Used for USB structues associated with a remote device. + * Don't expose the itemsize since it is constant. + */ +static unsigned int itemsize_mdm_usb = sizeof(struct diag_request); +static unsigned int poolsize_mdm_usb = 18; +module_param(poolsize_mdm_usb, uint, 0); + +/* + * Used for writing read DCI data to remote peripherals. Don't + * expose poolsize for DCI data. There is only one read + * buffer. Add 6 bytes for DCI header information: Start (1), + * Version (1), Length (2), Tag (2) + */ +static unsigned int itemsize_mdm_dci_write = DIAG_MDM_DCI_BUF_SIZE; +static unsigned int poolsize_mdm_dci_write = 1; +module_param(itemsize_mdm_dci_write, uint, 0); + +/* + * Used for USB structures associated with a remote SMUX + * device Don't expose the itemsize since it is constant + */ +static unsigned int itemsize_qsc_usb = sizeof(struct diag_request); +static unsigned int poolsize_qsc_usb = 8; +module_param(poolsize_qsc_usb, uint, 0); +#endif + +/* This is the max number of user-space clients supported at initialization*/ +static unsigned int max_clients = 15; +module_param(max_clients, uint, 0); + +/* Timer variables */ +static struct timer_list drain_timer; +static int timer_in_progress; + +/* + * Diag Mask clear variable + * Used for clearing masks upon + * USB disconnection and stopping ODL + */ +static int diag_mask_clear_param = 1; +module_param(diag_mask_clear_param, int, 0644); + +struct diag_apps_data_t { + void *buf; + uint32_t len; + int ctxt; +}; + +static struct diag_apps_data_t hdlc_data; +static struct diag_apps_data_t non_hdlc_data; +static struct mutex apps_data_mutex; + +#define DIAGPKT_MAX_DELAYED_RSP 0xFFFF + +#ifdef DIAG_DEBUG +uint16_t diag_debug_mask; +void *diag_ipc_log; +#endif + +static void diag_md_session_close(int pid); + +/* + * Returns the next delayed rsp id. If wrapping is enabled, + * wraps the delayed rsp id to DIAGPKT_MAX_DELAYED_RSP. + */ +static uint16_t diag_get_next_delayed_rsp_id(void) +{ + uint16_t rsp_id = 0; + + mutex_lock(&driver->delayed_rsp_mutex); + rsp_id = driver->delayed_rsp_id; + if (rsp_id < DIAGPKT_MAX_DELAYED_RSP) + rsp_id++; + else { + if (wrap_enabled) { + rsp_id = 1; + wrap_count++; + } else + rsp_id = DIAGPKT_MAX_DELAYED_RSP; + } + driver->delayed_rsp_id = rsp_id; + mutex_unlock(&driver->delayed_rsp_mutex); + + return rsp_id; +} + +static int diag_switch_logging(struct diag_logging_mode_param_t *param); + +#define COPY_USER_SPACE_OR_EXIT(buf, data, length) \ +do { \ + if ((count < ret+length) || (copy_to_user(buf, \ + (void *)&data, length))) { \ + ret = -EFAULT; \ + goto exit; \ + } \ + ret += length; \ +} while (0) + +#define COPY_USER_SPACE_OR_ERR(buf, data, length) \ +do { \ + if ((count < ret+length) || (copy_to_user(buf, \ + (void *)&data, length))) { \ + ret = -EFAULT; \ + break; \ + } \ + ret += length; \ +} while (0) + +static void drain_timer_func(unsigned long data) +{ + queue_work(driver->diag_wq , &(driver->diag_drain_work)); +} + +static void diag_drain_apps_data(struct diag_apps_data_t *data) +{ + int err = 0; + + if (!data || !data->buf) + return; + + err = diag_mux_write(DIAG_LOCAL_PROC, data->buf, data->len, + data->ctxt); + if (err) + diagmem_free(driver, data->buf, POOL_TYPE_HDLC); + + data->buf = NULL; + data->len = 0; +} + +void diag_update_user_client_work_fn(struct work_struct *work) +{ + diag_update_userspace_clients(HDLC_SUPPORT_TYPE); +} + +static void diag_update_md_client_work_fn(struct work_struct *work) +{ + diag_update_md_clients(HDLC_SUPPORT_TYPE); +} + +void diag_drain_work_fn(struct work_struct *work) +{ + struct diag_md_session_t *session_info = NULL; + uint8_t hdlc_disabled = 0; + + timer_in_progress = 0; + mutex_lock(&apps_data_mutex); + mutex_lock(&driver->md_session_lock); + session_info = diag_md_session_get_peripheral(APPS_DATA); + if (session_info) + hdlc_disabled = session_info->hdlc_disabled; + else + hdlc_disabled = driver->hdlc_disabled; + mutex_unlock(&driver->md_session_lock); + if (!hdlc_disabled) + diag_drain_apps_data(&hdlc_data); + else + diag_drain_apps_data(&non_hdlc_data); + mutex_unlock(&apps_data_mutex); +} + +void check_drain_timer(void) +{ + int ret = 0; + + if (!timer_in_progress) { + timer_in_progress = 1; + ret = mod_timer(&drain_timer, jiffies + msecs_to_jiffies(200)); + } +} + +void diag_add_client(int i, struct file *file) +{ + struct diagchar_priv *diagpriv_data; + + driver->client_map[i].pid = current->tgid; + diagpriv_data = kmalloc(sizeof(struct diagchar_priv), + GFP_KERNEL); + if (diagpriv_data) + diagpriv_data->pid = current->tgid; + file->private_data = diagpriv_data; + strlcpy(driver->client_map[i].name, current->comm, 20); + driver->client_map[i].name[19] = '\0'; +} + +static void diag_mempool_init(void) +{ + uint32_t itemsize = DIAG_MAX_REQ_SIZE; + uint32_t itemsize_hdlc = DIAG_MAX_HDLC_BUF_SIZE + APF_DIAG_PADDING; + uint32_t itemsize_dci = IN_BUF_SIZE; + uint32_t itemsize_user = DCI_REQ_BUF_SIZE; + + itemsize += ((DCI_HDR_SIZE > CALLBACK_HDR_SIZE) ? DCI_HDR_SIZE : + CALLBACK_HDR_SIZE); + diagmem_setsize(POOL_TYPE_COPY, itemsize, poolsize); + diagmem_setsize(POOL_TYPE_HDLC, itemsize_hdlc, poolsize_hdlc); + diagmem_setsize(POOL_TYPE_DCI, itemsize_dci, poolsize_dci); + diagmem_setsize(POOL_TYPE_USER, itemsize_user, poolsize_user); + + diagmem_init(driver, POOL_TYPE_COPY); + diagmem_init(driver, POOL_TYPE_HDLC); + diagmem_init(driver, POOL_TYPE_USER); + diagmem_init(driver, POOL_TYPE_DCI); +} + +static void diag_mempool_exit(void) +{ + diagmem_exit(driver, POOL_TYPE_COPY); + diagmem_exit(driver, POOL_TYPE_HDLC); + diagmem_exit(driver, POOL_TYPE_USER); + diagmem_exit(driver, POOL_TYPE_DCI); +} + +static int diagchar_open(struct inode *inode, struct file *file) +{ + int i = 0; + void *temp; + + if (driver) { + mutex_lock(&driver->diagchar_mutex); + + for (i = 0; i < driver->num_clients; i++) + if (driver->client_map[i].pid == 0) + break; + + if (i < driver->num_clients) { + diag_add_client(i, file); + } else { + if (i < THRESHOLD_CLIENT_LIMIT) { + driver->num_clients++; + temp = krealloc(driver->client_map + , (driver->num_clients) * sizeof(struct + diag_client_map), GFP_KERNEL); + if (!temp) + goto fail; + else + driver->client_map = temp; + temp = krealloc(driver->data_ready + , (driver->num_clients) * sizeof(int), + GFP_KERNEL); + if (!temp) + goto fail; + else + driver->data_ready = temp; + diag_add_client(i, file); + } else { + mutex_unlock(&driver->diagchar_mutex); + pr_err_ratelimited("diag: Max client limit for DIAG reached\n"); + pr_err_ratelimited("diag: Cannot open handle %s" + " %d", current->comm, current->tgid); + for (i = 0; i < driver->num_clients; i++) + pr_debug("%d) %s PID=%d", i, driver-> + client_map[i].name, + driver->client_map[i].pid); + return -ENOMEM; + } + } + driver->data_ready[i] = 0x0; + atomic_set(&driver->data_ready_notif[i], 0); + driver->data_ready[i] |= MSG_MASKS_TYPE; + atomic_inc(&driver->data_ready_notif[i]); + driver->data_ready[i] |= EVENT_MASKS_TYPE; + atomic_inc(&driver->data_ready_notif[i]); + driver->data_ready[i] |= LOG_MASKS_TYPE; + atomic_inc(&driver->data_ready_notif[i]); + driver->data_ready[i] |= DCI_LOG_MASKS_TYPE; + atomic_inc(&driver->data_ready_notif[i]); + driver->data_ready[i] |= DCI_EVENT_MASKS_TYPE; + atomic_inc(&driver->data_ready_notif[i]); + + if (driver->ref_count == 0) + diag_mempool_init(); + driver->ref_count++; + mutex_unlock(&driver->diagchar_mutex); + return 0; + } + return -ENOMEM; + +fail: + driver->num_clients--; + mutex_unlock(&driver->diagchar_mutex); + pr_err_ratelimited("diag: Insufficient memory for new client"); + return -ENOMEM; +} + +static uint32_t diag_translate_kernel_to_user_mask(uint32_t peripheral_mask) +{ + uint32_t ret = 0; + + if (peripheral_mask & MD_PERIPHERAL_MASK(APPS_DATA)) + ret |= DIAG_CON_APSS; + if (peripheral_mask & MD_PERIPHERAL_MASK(PERIPHERAL_MODEM)) + ret |= DIAG_CON_MPSS; + if (peripheral_mask & MD_PERIPHERAL_MASK(PERIPHERAL_LPASS)) + ret |= DIAG_CON_LPASS; + if (peripheral_mask & MD_PERIPHERAL_MASK(PERIPHERAL_WCNSS)) + ret |= DIAG_CON_WCNSS; + if (peripheral_mask & MD_PERIPHERAL_MASK(PERIPHERAL_SENSORS)) + ret |= DIAG_CON_SENSORS; + if (peripheral_mask & MD_PERIPHERAL_MASK(PERIPHERAL_WDSP)) + ret |= DIAG_CON_WDSP; + if (peripheral_mask & MD_PERIPHERAL_MASK(PERIPHERAL_CDSP)) + ret |= DIAG_CON_CDSP; + if (peripheral_mask & MD_PERIPHERAL_MASK(UPD_WLAN)) + ret |= DIAG_CON_UPD_WLAN; + if (peripheral_mask & MD_PERIPHERAL_MASK(UPD_AUDIO)) + ret |= DIAG_CON_UPD_AUDIO; + if (peripheral_mask & MD_PERIPHERAL_MASK(UPD_SENSORS)) + ret |= DIAG_CON_UPD_SENSORS; + return ret; +} + +uint8_t diag_mask_to_pd_value(uint32_t peripheral_mask) +{ + uint8_t upd = 0; + uint32_t pd_mask = 0; + + pd_mask = diag_translate_kernel_to_user_mask(peripheral_mask); + switch (pd_mask) { + case DIAG_CON_UPD_WLAN: + upd = UPD_WLAN; + break; + case DIAG_CON_UPD_AUDIO: + upd = UPD_AUDIO; + break; + case DIAG_CON_UPD_SENSORS: + upd = UPD_SENSORS; + break; + default: + DIAG_LOG(DIAG_DEBUG_MASKS, + "asking for mask update with no pd mask set\n"); + } + return upd; +} + +int diag_mask_param(void) +{ + return diag_mask_clear_param; +} +void diag_clear_masks(int pid) +{ + int ret; + char cmd_disable_log_mask[] = { 0x73, 0, 0, 0, 0, 0, 0, 0}; + char cmd_disable_msg_mask[] = { 0x7D, 0x05, 0, 0, 0, 0, 0, 0}; + char cmd_disable_event_mask[] = { 0x60, 0}; + + DIAG_LOG(DIAG_DEBUG_PERIPHERALS, + "diag: %s: masks clear request upon %s\n", __func__, + ((pid) ? "ODL exit" : "USB Disconnection")); + + ret = diag_process_apps_masks(cmd_disable_log_mask, + sizeof(cmd_disable_log_mask), pid); + ret = diag_process_apps_masks(cmd_disable_msg_mask, + sizeof(cmd_disable_msg_mask), pid); + ret = diag_process_apps_masks(cmd_disable_event_mask, + sizeof(cmd_disable_event_mask), pid); + DIAG_LOG(DIAG_DEBUG_PERIPHERALS, + "diag:%s: masks cleared successfully\n", __func__); +} + +static void diag_close_logging_process(const int pid) +{ + int i, j; + int session_mask; + uint32_t p_mask; + struct diag_md_session_t *session_info = NULL; + struct diag_logging_mode_param_t params; + + mutex_lock(&driver->md_session_lock); + session_info = diag_md_session_get_pid(pid); + if (!session_info) { + mutex_unlock(&driver->md_session_lock); + return; + } + session_mask = session_info->peripheral_mask; + mutex_unlock(&driver->md_session_lock); + + if (diag_mask_clear_param) + diag_clear_masks(pid); + + mutex_lock(&driver->diag_maskclear_mutex); + driver->mask_clear = 1; + mutex_unlock(&driver->diag_maskclear_mutex); + + mutex_lock(&driver->diagchar_mutex); + + p_mask = + diag_translate_kernel_to_user_mask(session_mask); + + for (i = 0; i < NUM_MD_SESSIONS; i++) + if (MD_PERIPHERAL_MASK(i) & session_mask) + diag_mux_close_peripheral(DIAG_LOCAL_PROC, i); + + params.req_mode = USB_MODE; + params.mode_param = 0; + params.pd_mask = 0; + params.peripheral_mask = p_mask; + + if (driver->num_pd_session > 0) { + for (i = UPD_WLAN; (i < NUM_MD_SESSIONS); i++) { + if (session_mask & MD_PERIPHERAL_MASK(i)) { + j = i - UPD_WLAN; + driver->pd_session_clear[j] = 1; + driver->pd_logging_mode[j] = 0; + driver->num_pd_session -= 1; + params.pd_mask = p_mask; + } + } + } + mutex_lock(&driver->md_session_lock); + diag_md_session_close(pid); + mutex_unlock(&driver->md_session_lock); + diag_switch_logging(¶ms); + + mutex_unlock(&driver->diagchar_mutex); +} + +static int diag_remove_client_entry(struct file *file) +{ + int i = -1; + struct diagchar_priv *diagpriv_data = NULL; + struct diag_dci_client_tbl *dci_entry = NULL; + + if (!driver) + return -ENOMEM; + + mutex_lock(&driver->diag_file_mutex); + if (!file) { + DIAG_LOG(DIAG_DEBUG_USERSPACE, "Invalid file pointer\n"); + mutex_unlock(&driver->diag_file_mutex); + return -ENOENT; + } + if (!(file->private_data)) { + DIAG_LOG(DIAG_DEBUG_USERSPACE, "Invalid private data\n"); + mutex_unlock(&driver->diag_file_mutex); + return -EINVAL; + } + + diagpriv_data = file->private_data; + + /* + * clean up any DCI registrations, if this is a DCI client + * This will specially help in case of ungraceful exit of any DCI client + * This call will remove any pending registrations of such client + */ + mutex_lock(&driver->dci_mutex); + dci_entry = dci_lookup_client_entry_pid(current->tgid); + if (dci_entry) + diag_dci_deinit_client(dci_entry); + mutex_unlock(&driver->dci_mutex); + + diag_close_logging_process(current->tgid); + + /* Delete the pkt response table entry for the exiting process */ + diag_cmd_remove_reg_by_pid(current->tgid); + + mutex_lock(&driver->diagchar_mutex); + driver->ref_count--; + if (driver->ref_count == 0) + diag_mempool_exit(); + + for (i = 0; i < driver->num_clients; i++) { + if (NULL != diagpriv_data && diagpriv_data->pid == + driver->client_map[i].pid) { + driver->client_map[i].pid = 0; + kfree(diagpriv_data); + diagpriv_data = NULL; + file->private_data = 0; + break; + } + } + mutex_unlock(&driver->diagchar_mutex); + mutex_unlock(&driver->diag_file_mutex); + return 0; +} +static int diagchar_close(struct inode *inode, struct file *file) +{ + int ret; + DIAG_LOG(DIAG_DEBUG_USERSPACE, "diag: process exit %s\n", + current->comm); + ret = diag_remove_client_entry(file); + mutex_lock(&driver->diag_maskclear_mutex); + driver->mask_clear = 0; + mutex_unlock(&driver->diag_maskclear_mutex); + return ret; +} + +void diag_record_stats(int type, int flag) +{ + struct diag_pkt_stats_t *pkt_stats = NULL; + + switch (type) { + case DATA_TYPE_EVENT: + pkt_stats = &driver->event_stats; + break; + case DATA_TYPE_F3: + pkt_stats = &driver->msg_stats; + break; + case DATA_TYPE_LOG: + pkt_stats = &driver->log_stats; + break; + case DATA_TYPE_RESPONSE: + if (flag != PKT_DROP) + return; + pr_err_ratelimited("diag: In %s, dropping response. This shouldn't happen\n", + __func__); + return; + case DATA_TYPE_DELAYED_RESPONSE: + /* No counters to increase for Delayed responses */ + return; + default: + pr_err_ratelimited("diag: In %s, invalid pkt_type: %d\n", + __func__, type); + return; + } + + switch (flag) { + case PKT_ALLOC: + atomic_add(1, (atomic_t *)&pkt_stats->alloc_count); + break; + case PKT_DROP: + atomic_add(1, (atomic_t *)&pkt_stats->drop_count); + break; + case PKT_RESET: + atomic_set((atomic_t *)&pkt_stats->alloc_count, 0); + atomic_set((atomic_t *)&pkt_stats->drop_count, 0); + break; + default: + pr_err_ratelimited("diag: In %s, invalid flag: %d\n", + __func__, flag); + return; + } +} + +void diag_get_timestamp(char *time_str) +{ + struct timeval t; + struct tm broken_tm; + do_gettimeofday(&t); + if (!time_str) + return; + time_to_tm(t.tv_sec, 0, &broken_tm); + scnprintf(time_str, DIAG_TS_SIZE, "%d:%d:%d:%ld", broken_tm.tm_hour, + broken_tm.tm_min, broken_tm.tm_sec, t.tv_usec); +} + +int diag_get_remote(int remote_info) +{ + int val = (remote_info < 0) ? -remote_info : remote_info; + int remote_val; + + switch (val) { + case MDM: + case MDM2: + case QSC: + remote_val = -remote_info; + break; + default: + remote_val = 0; + break; + } + + return remote_val; +} + +int diag_cmd_chk_polling(struct diag_cmd_reg_entry_t *entry) +{ + int polling = DIAG_CMD_NOT_POLLING; + + if (!entry) + return -EIO; + + if (entry->cmd_code == DIAG_CMD_NO_SUBSYS) { + if (entry->subsys_id == DIAG_CMD_NO_SUBSYS && + entry->cmd_code_hi >= DIAG_CMD_STATUS && + entry->cmd_code_lo <= DIAG_CMD_STATUS) + polling = DIAG_CMD_POLLING; + else if (entry->subsys_id == DIAG_SS_WCDMA && + entry->cmd_code_hi >= DIAG_CMD_QUERY_CALL && + entry->cmd_code_lo <= DIAG_CMD_QUERY_CALL) + polling = DIAG_CMD_POLLING; + else if (entry->subsys_id == DIAG_SS_GSM && + entry->cmd_code_hi >= DIAG_CMD_QUERY_TMC && + entry->cmd_code_lo <= DIAG_CMD_QUERY_TMC) + polling = DIAG_CMD_POLLING; + else if (entry->subsys_id == DIAG_SS_PARAMS && + entry->cmd_code_hi >= DIAG_DIAG_POLL && + entry->cmd_code_lo <= DIAG_DIAG_POLL) + polling = DIAG_CMD_POLLING; + else if (entry->subsys_id == DIAG_SS_TDSCDMA && + entry->cmd_code_hi >= DIAG_CMD_TDSCDMA_STATUS && + entry->cmd_code_lo <= DIAG_CMD_TDSCDMA_STATUS) + polling = DIAG_CMD_POLLING; + } + + return polling; +} + +static void diag_cmd_invalidate_polling(int change_flag) +{ + int polling = DIAG_CMD_NOT_POLLING; + struct list_head *start; + struct list_head *temp; + struct diag_cmd_reg_t *item = NULL; + + if (change_flag == DIAG_CMD_ADD) { + if (driver->polling_reg_flag) + return; + } + + driver->polling_reg_flag = 0; + list_for_each_safe(start, temp, &driver->cmd_reg_list) { + item = list_entry(start, struct diag_cmd_reg_t, link); + if (&item->entry == NULL) { + pr_err("diag: In %s, unable to search command\n", + __func__); + return; + } + polling = diag_cmd_chk_polling(&item->entry); + if (polling == DIAG_CMD_POLLING) { + driver->polling_reg_flag = 1; + break; + } + } +} + +int diag_cmd_add_reg(struct diag_cmd_reg_entry_t *new_entry, uint8_t proc, + int pid) +{ + struct diag_cmd_reg_t *new_item = NULL; + + if (!new_entry) { + pr_err("diag: In %s, invalid new entry\n", __func__); + return -EINVAL; + } + + if (proc > APPS_DATA) { + pr_err("diag: In %s, invalid peripheral %d\n", __func__, proc); + return -EINVAL; + } + + if (proc != APPS_DATA) + pid = INVALID_PID; + + new_item = kzalloc(sizeof(struct diag_cmd_reg_t), GFP_KERNEL); + if (!new_item) { + pr_err("diag: In %s, unable to create memory for new command registration\n", + __func__); + return -ENOMEM; + } + kmemleak_not_leak(new_item); + + new_item->pid = pid; + new_item->proc = proc; + memcpy(&new_item->entry, new_entry, + sizeof(struct diag_cmd_reg_entry_t)); + INIT_LIST_HEAD(&new_item->link); + + mutex_lock(&driver->cmd_reg_mutex); + list_add_tail(&new_item->link, &driver->cmd_reg_list); + driver->cmd_reg_count++; + diag_cmd_invalidate_polling(DIAG_CMD_ADD); + mutex_unlock(&driver->cmd_reg_mutex); + + return 0; +} + +struct diag_cmd_reg_entry_t *diag_cmd_search( + struct diag_cmd_reg_entry_t *entry, int proc) +{ + struct list_head *start; + struct list_head *temp; + struct diag_cmd_reg_t *item = NULL; + struct diag_cmd_reg_entry_t *temp_entry = NULL; + + if (!entry) { + pr_err("diag: In %s, invalid entry\n", __func__); + return NULL; + } + + list_for_each_safe(start, temp, &driver->cmd_reg_list) { + item = list_entry(start, struct diag_cmd_reg_t, link); + if (&item->entry == NULL) { + pr_err("diag: In %s, unable to search command\n", + __func__); + return NULL; + } + temp_entry = &item->entry; + if (temp_entry->cmd_code == entry->cmd_code && + temp_entry->subsys_id == entry->subsys_id && + temp_entry->cmd_code_hi >= entry->cmd_code_hi && + temp_entry->cmd_code_lo <= entry->cmd_code_lo && + (proc == item->proc || proc == ALL_PROC)) { + return &item->entry; + } else if (temp_entry->cmd_code == DIAG_CMD_NO_SUBSYS && + entry->cmd_code == DIAG_CMD_DIAG_SUBSYS) { + if (temp_entry->subsys_id == entry->subsys_id && + temp_entry->cmd_code_hi >= entry->cmd_code_hi && + temp_entry->cmd_code_lo <= entry->cmd_code_lo && + (proc == item->proc || proc == ALL_PROC)) { + return &item->entry; + } + } else if (temp_entry->cmd_code == DIAG_CMD_NO_SUBSYS && + temp_entry->subsys_id == DIAG_CMD_NO_SUBSYS) { + if ((temp_entry->cmd_code_hi >= entry->cmd_code) && + (temp_entry->cmd_code_lo <= entry->cmd_code) && + (proc == item->proc || proc == ALL_PROC)) { + if (entry->cmd_code == MODE_CMD) { + if (entry->subsys_id == RESET_ID && + item->proc != APPS_DATA) { + continue; + } + if (entry->subsys_id != RESET_ID && + item->proc == APPS_DATA) { + continue; + } + } + return &item->entry; + } + } + } + + return NULL; +} + +void diag_cmd_remove_reg(struct diag_cmd_reg_entry_t *entry, uint8_t proc) +{ + struct diag_cmd_reg_t *item = NULL; + struct diag_cmd_reg_entry_t *temp_entry; + if (!entry) { + pr_err("diag: In %s, invalid entry\n", __func__); + return; + } + + mutex_lock(&driver->cmd_reg_mutex); + temp_entry = diag_cmd_search(entry, proc); + if (temp_entry) { + item = container_of(temp_entry, struct diag_cmd_reg_t, entry); + if (!item) { + mutex_unlock(&driver->cmd_reg_mutex); + return; + } + list_del(&item->link); + kfree(item); + driver->cmd_reg_count--; + } + diag_cmd_invalidate_polling(DIAG_CMD_REMOVE); + mutex_unlock(&driver->cmd_reg_mutex); +} + +void diag_cmd_remove_reg_by_pid(int pid) +{ + struct list_head *start; + struct list_head *temp; + struct diag_cmd_reg_t *item = NULL; + + mutex_lock(&driver->cmd_reg_mutex); + list_for_each_safe(start, temp, &driver->cmd_reg_list) { + item = list_entry(start, struct diag_cmd_reg_t, link); + if (&item->entry == NULL) { + pr_err("diag: In %s, unable to search command\n", + __func__); + mutex_unlock(&driver->cmd_reg_mutex); + return; + } + if (item->pid == pid) { + list_del(&item->link); + kfree(item); + driver->cmd_reg_count--; + } + } + mutex_unlock(&driver->cmd_reg_mutex); +} + +void diag_cmd_remove_reg_by_proc(int proc) +{ + struct list_head *start; + struct list_head *temp; + struct diag_cmd_reg_t *item = NULL; + + mutex_lock(&driver->cmd_reg_mutex); + list_for_each_safe(start, temp, &driver->cmd_reg_list) { + item = list_entry(start, struct diag_cmd_reg_t, link); + if (&item->entry == NULL) { + pr_err("diag: In %s, unable to search command\n", + __func__); + mutex_unlock(&driver->cmd_reg_mutex); + return; + } + if (item->proc == proc) { + list_del(&item->link); + kfree(item); + driver->cmd_reg_count--; + } + } + diag_cmd_invalidate_polling(DIAG_CMD_REMOVE); + mutex_unlock(&driver->cmd_reg_mutex); +} + +static int diag_copy_dci(char __user *buf, size_t count, + struct diag_dci_client_tbl *entry, int *pret) +{ + int total_data_len = 0; + int ret = 0; + int exit_stat = 1; + uint8_t drain_again = 0; + struct diag_dci_buffer_t *buf_entry, *temp; + + if (!buf || !entry || !pret) + return exit_stat; + + ret = *pret; + + ret += sizeof(int); + if (ret >= count) { + pr_err("diag: In %s, invalid value for ret: %d, count: %zu\n", + __func__, ret, count); + return -EINVAL; + } + + mutex_lock(&entry->write_buf_mutex); + list_for_each_entry_safe(buf_entry, temp, &entry->list_write_buf, + buf_track) { + + if ((ret + buf_entry->data_len) > count) { + drain_again = 1; + break; + } + + list_del(&buf_entry->buf_track); + mutex_lock(&buf_entry->data_mutex); + if ((buf_entry->data_len > 0) && + (buf_entry->in_busy) && + (buf_entry->data)) { + if (copy_to_user(buf+ret, (void *)buf_entry->data, + buf_entry->data_len)) + goto drop; + ret += buf_entry->data_len; + total_data_len += buf_entry->data_len; + diag_ws_on_copy(DIAG_WS_DCI); +drop: + buf_entry->in_busy = 0; + buf_entry->data_len = 0; + buf_entry->in_list = 0; + if (buf_entry->buf_type == DCI_BUF_CMD) { + mutex_unlock(&buf_entry->data_mutex); + continue; + } else if (buf_entry->buf_type == DCI_BUF_SECONDARY) { + diagmem_free(driver, buf_entry->data, + POOL_TYPE_DCI); + buf_entry->data = NULL; + mutex_unlock(&buf_entry->data_mutex); + kfree(buf_entry); + continue; + } + + } + mutex_unlock(&buf_entry->data_mutex); + } + + if (total_data_len > 0) { + /* Copy the total data length */ + COPY_USER_SPACE_OR_EXIT(buf+8, total_data_len, 4); + ret -= 4; + } else { + pr_debug("diag: In %s, Trying to copy ZERO bytes, total_data_len: %d\n", + __func__, total_data_len); + } + + exit_stat = 0; +exit: + entry->in_service = 0; + mutex_unlock(&entry->write_buf_mutex); + *pret = ret; + if (drain_again) + dci_drain_data(0); + + return exit_stat; +} + +#ifdef CONFIG_DIAGFWD_BRIDGE_CODE +static int diag_remote_init(void) +{ + diagmem_setsize(POOL_TYPE_MDM, itemsize_mdm, poolsize_mdm); + diagmem_setsize(POOL_TYPE_MDM2, itemsize_mdm, poolsize_mdm); + diagmem_setsize(POOL_TYPE_MDM_DCI, itemsize_mdm_dci, poolsize_mdm_dci); + diagmem_setsize(POOL_TYPE_MDM2_DCI, itemsize_mdm_dci, + poolsize_mdm_dci); + diagmem_setsize(POOL_TYPE_MDM_MUX, itemsize_mdm_usb, poolsize_mdm_usb); + diagmem_setsize(POOL_TYPE_MDM2_MUX, itemsize_mdm_usb, poolsize_mdm_usb); + diagmem_setsize(POOL_TYPE_MDM_DCI_WRITE, itemsize_mdm_dci_write, + poolsize_mdm_dci_write); + diagmem_setsize(POOL_TYPE_MDM2_DCI_WRITE, itemsize_mdm_dci_write, + poolsize_mdm_dci_write); + diagmem_setsize(POOL_TYPE_QSC_MUX, itemsize_qsc_usb, + poolsize_qsc_usb); + driver->hdlc_encode_buf = kzalloc(DIAG_MAX_HDLC_BUF_SIZE, GFP_KERNEL); + if (!driver->hdlc_encode_buf) + return -ENOMEM; + driver->hdlc_encode_buf_len = 0; + return 0; +} + +static void diag_remote_exit(void) +{ + kfree(driver->hdlc_encode_buf); +} + +static int diag_send_raw_data_remote(int proc, void *buf, int len, + uint8_t hdlc_flag) +{ + int err = 0; + int max_len = 0; + uint8_t retry_count = 0; + uint8_t max_retries = 3; + uint16_t payload = 0; + struct diag_send_desc_type send = { NULL, NULL, DIAG_STATE_START, 0 }; + struct diag_hdlc_dest_type enc = { NULL, NULL, 0 }; + int bridge_index = proc - 1; + struct diag_md_session_t *session_info = NULL; + uint8_t hdlc_disabled = 0; + + if (!buf) + return -EINVAL; + + if (len <= 0) { + pr_err("diag: In %s, invalid len: %d", __func__, len); + return -EBADMSG; + } + + if (bridge_index < 0 || bridge_index > NUM_REMOTE_DEV) { + pr_err("diag: In %s, invalid bridge index: %d\n", __func__, + bridge_index); + return -EINVAL; + } + + do { + if (driver->hdlc_encode_buf_len == 0) + break; + usleep_range(10000, 10100); + retry_count++; + } while (retry_count < max_retries); + + if (driver->hdlc_encode_buf_len != 0) + return -EAGAIN; + mutex_lock(&driver->md_session_lock); + session_info = diag_md_session_get_peripheral(APPS_DATA); + if (session_info) + hdlc_disabled = session_info->hdlc_disabled; + else + hdlc_disabled = driver->hdlc_disabled; + mutex_unlock(&driver->md_session_lock); + if (hdlc_disabled) { + if (len < 4) { + pr_err("diag: In %s, invalid len: %d of non_hdlc pkt", + __func__, len); + return -EBADMSG; + } + payload = *(uint16_t *)(buf + 2); + if (payload > DIAG_MAX_HDLC_BUF_SIZE) { + pr_err("diag: Dropping packet, payload size is %d\n", + payload); + return -EBADMSG; + } + driver->hdlc_encode_buf_len = payload; + /* + * Adding 5 bytes for start (1 byte), version (1 byte), + * payload (2 bytes) and end (1 byte) + */ + if (len == (payload + 5)) { + /* + * Adding 4 bytes for start (1 byte), version (1 byte) + * and payload (2 bytes) + */ + memcpy(driver->hdlc_encode_buf, buf + 4, payload); + goto send_data; + } else { + pr_err("diag: In %s, invalid len: %d of non_hdlc pkt", + __func__, len); + return -EBADMSG; + } + } + + if (hdlc_flag) { + if (DIAG_MAX_HDLC_BUF_SIZE < len) { + pr_err("diag: Dropping packet, HDLC encoded packet payload size crosses buffer limit. Current payload size %d\n", + len); + return -EBADMSG; + } + driver->hdlc_encode_buf_len = len; + memcpy(driver->hdlc_encode_buf, buf, len); + goto send_data; + } + + /* + * The worst case length will be twice as the incoming packet length. + * Add 3 bytes for CRC bytes (2 bytes) and delimiter (1 byte) + */ + max_len = (2 * len) + 3; + if (DIAG_MAX_HDLC_BUF_SIZE < max_len) { + pr_err("diag: Dropping packet, HDLC encoded packet payload size crosses buffer limit. Current payload size %d\n", + max_len); + return -EBADMSG; + } + + /* Perform HDLC encoding on incoming data */ + send.state = DIAG_STATE_START; + send.pkt = (void *)(buf); + send.last = (void *)(buf + len - 1); + send.terminate = 1; + + enc.dest = driver->hdlc_encode_buf; + enc.dest_last = (void *)(driver->hdlc_encode_buf + max_len - 1); + diag_hdlc_encode(&send, &enc); + driver->hdlc_encode_buf_len = (int)(enc.dest - + (void *)driver->hdlc_encode_buf); + +send_data: + err = diagfwd_bridge_write(bridge_index, driver->hdlc_encode_buf, + driver->hdlc_encode_buf_len); + if (err) { + pr_err_ratelimited("diag: Error writing Callback packet to proc: %d, err: %d\n", + proc, err); + driver->hdlc_encode_buf_len = 0; + } + + return err; +} + +static int diag_process_userspace_remote(int proc, void *buf, int len) +{ + int bridge_index = proc - 1; + + if (!buf || len < 0) { + pr_err("diag: Invalid input in %s, buf: %pK, len: %d\n", + __func__, buf, len); + return -EINVAL; + } + + if (bridge_index < 0 || bridge_index > NUM_REMOTE_DEV) { + pr_err("diag: In %s, invalid bridge index: %d\n", __func__, + bridge_index); + return -EINVAL; + } + + driver->user_space_data_busy = 1; + return diagfwd_bridge_write(bridge_index, buf, len); +} +#else +static int diag_remote_init(void) +{ + return 0; +} + +static void diag_remote_exit(void) +{ + return; +} + +int diagfwd_bridge_init(void) +{ + return 0; +} + +void diagfwd_bridge_exit(void) +{ + return; +} + +uint16_t diag_get_remote_device_mask(void) +{ + return 0; +} + +static int diag_send_raw_data_remote(int proc, void *buf, int len, + uint8_t hdlc_flag) +{ + return -EINVAL; +} + +static int diag_process_userspace_remote(int proc, void *buf, int len) +{ + return 0; +} +#endif + +static int mask_request_validate(unsigned char mask_buf[]) +{ + uint8_t packet_id; + uint8_t subsys_id; + uint16_t ss_cmd; + + packet_id = mask_buf[0]; + + if (packet_id == DIAG_CMD_DIAG_SUBSYS_DELAY) { + subsys_id = mask_buf[1]; + ss_cmd = *(uint16_t *)(mask_buf + 2); + switch (subsys_id) { + case DIAG_SS_DIAG: + if ((ss_cmd == DIAG_SS_FILE_READ_MODEM) || + (ss_cmd == DIAG_SS_FILE_READ_ADSP) || + (ss_cmd == DIAG_SS_FILE_READ_WCNSS) || + (ss_cmd == DIAG_SS_FILE_READ_SLPI) || + (ss_cmd == DIAG_SS_FILE_READ_APPS)) + return 1; + break; + default: + return 0; + } + } else if (packet_id == 0x4B) { + subsys_id = mask_buf[1]; + ss_cmd = *(uint16_t *)(mask_buf + 2); + /* Packets with SSID which are allowed */ + switch (subsys_id) { + case 0x04: /* DIAG_SUBSYS_WCDMA */ + if ((ss_cmd == 0) || (ss_cmd == 0xF)) + return 1; + break; + case 0x08: /* DIAG_SUBSYS_GSM */ + if ((ss_cmd == 0) || (ss_cmd == 0x1)) + return 1; + break; + case 0x09: /* DIAG_SUBSYS_UMTS */ + case 0x0F: /* DIAG_SUBSYS_CM */ + if (ss_cmd == 0) + return 1; + break; + case 0x0C: /* DIAG_SUBSYS_OS */ + if ((ss_cmd == 2) || (ss_cmd == 0x100)) + return 1; /* MPU and APU */ + break; + case 0x12: /* DIAG_SUBSYS_DIAG_SERV */ + if ((ss_cmd == 0) || (ss_cmd == 0x6) || (ss_cmd == 0x7)) + return 1; + else if (ss_cmd == 0x218) /* HDLC Disabled Command*/ + return 0; + else if (ss_cmd == DIAG_GET_TIME_API) + return 1; + else if (ss_cmd == DIAG_SET_TIME_API) + return 1; + else if (ss_cmd == DIAG_SWITCH_COMMAND) + return 1; + else if (ss_cmd == DIAG_BUFFERING_MODE) + return 1; + break; + case 0x13: /* DIAG_SUBSYS_FS */ + if ((ss_cmd == 0) || (ss_cmd == 0x1)) + return 1; + break; + default: + return 0; + break; + } + } else { + switch (packet_id) { + case 0x00: /* Version Number */ + case 0x0C: /* CDMA status packet */ + case 0x1C: /* Diag Version */ + case 0x1D: /* Time Stamp */ + case 0x60: /* Event Report Control */ + case 0x63: /* Status snapshot */ + case 0x73: /* Logging Configuration */ + case 0x7C: /* Extended build ID */ + case 0x7D: /* Extended Message configuration */ + case 0x81: /* Event get mask */ + case 0x82: /* Set the event mask */ + return 1; + break; + default: + return 0; + break; + } + } + return 0; +} + +static void diag_md_session_init(void) +{ + int i; + + mutex_init(&driver->md_session_lock); + driver->md_session_mask = 0; + driver->md_session_mode = DIAG_MD_NONE; + for (i = 0; i < NUM_MD_SESSIONS; i++) + driver->md_session_map[i] = NULL; +} + +static void diag_md_session_exit(void) +{ + int i; + struct diag_md_session_t *session_info = NULL; + + for (i = 0; i < NUM_MD_SESSIONS; i++) { + if (driver->md_session_map[i]) { + session_info = driver->md_session_map[i]; + diag_log_mask_free(session_info->log_mask); + kfree(session_info->log_mask); + session_info->log_mask = NULL; + diag_msg_mask_free(session_info->msg_mask, + session_info); + kfree(session_info->msg_mask); + session_info->msg_mask = NULL; + diag_event_mask_free(session_info->event_mask); + kfree(session_info->event_mask); + session_info->event_mask = NULL; + kfree(session_info); + session_info = NULL; + driver->md_session_map[i] = NULL; + } + } + mutex_destroy(&driver->md_session_lock); + driver->md_session_mask = 0; + driver->md_session_mode = DIAG_MD_NONE; +} + +int diag_md_session_create(int mode, int peripheral_mask, int proc) +{ + int i; + int err = 0; + struct diag_md_session_t *new_session = NULL; + + /* + * If a session is running with a peripheral mask and a new session + * request comes in with same peripheral mask value then return + * invalid param + */ + if (driver->md_session_mode == DIAG_MD_PERIPHERAL && + (driver->md_session_mask & peripheral_mask) != 0) + return -EINVAL; + + mutex_lock(&driver->md_session_lock); + new_session = kzalloc(sizeof(struct diag_md_session_t), GFP_KERNEL); + if (!new_session) { + mutex_unlock(&driver->md_session_lock); + return -ENOMEM; + } + new_session->peripheral_mask = 0; + new_session->pid = current->tgid; + new_session->task = current; + new_session->md_client_thread_info = current_thread_info(); + new_session->log_mask = kzalloc(sizeof(struct diag_mask_info), + GFP_KERNEL); + if (!new_session->log_mask) { + err = -ENOMEM; + goto fail_peripheral; + } + new_session->event_mask = kzalloc(sizeof(struct diag_mask_info), + GFP_KERNEL); + if (!new_session->event_mask) { + err = -ENOMEM; + goto fail_peripheral; + } + new_session->msg_mask = kzalloc(sizeof(struct diag_mask_info), + GFP_KERNEL); + if (!new_session->msg_mask) { + err = -ENOMEM; + goto fail_peripheral; + } + + err = diag_log_mask_copy(new_session->log_mask, &log_mask); + if (err) { + DIAG_LOG(DIAG_DEBUG_USERSPACE, + "return value of log copy. err %d\n", err); + goto fail_peripheral; + } + err = diag_event_mask_copy(new_session->event_mask, &event_mask); + if (err) { + DIAG_LOG(DIAG_DEBUG_USERSPACE, + "return value of event copy. err %d\n", err); + goto fail_peripheral; + } + new_session->msg_mask_tbl_count = 0; + err = diag_msg_mask_copy(new_session, new_session->msg_mask, + &msg_mask); + if (err) { + DIAG_LOG(DIAG_DEBUG_USERSPACE, + "return value of msg copy. err %d\n", err); + goto fail_peripheral; + } + for (i = 0; i < NUM_MD_SESSIONS; i++) { + if ((MD_PERIPHERAL_MASK(i) & peripheral_mask) == 0) + continue; + if (driver->md_session_map[i] != NULL) { + DIAG_LOG(DIAG_DEBUG_USERSPACE, + "another instance present for %d\n", i); + err = -EEXIST; + goto fail_peripheral; + } + new_session->peripheral_mask |= MD_PERIPHERAL_MASK(i); + driver->md_session_map[i] = new_session; + driver->md_session_mask |= MD_PERIPHERAL_MASK(i); + } + setup_timer(&new_session->hdlc_reset_timer, + diag_md_hdlc_reset_timer_func, + new_session->pid); + + driver->md_session_mode = DIAG_MD_PERIPHERAL; + mutex_unlock(&driver->md_session_lock); + DIAG_LOG(DIAG_DEBUG_USERSPACE, + "created session in peripheral mode\n"); + return 0; + +fail_peripheral: + diag_log_mask_free(new_session->log_mask); + kfree(new_session->log_mask); + new_session->log_mask = NULL; + diag_event_mask_free(new_session->event_mask); + kfree(new_session->event_mask); + new_session->event_mask = NULL; + diag_msg_mask_free(new_session->msg_mask, + new_session); + kfree(new_session->msg_mask); + new_session->msg_mask = NULL; + kfree(new_session); + new_session = NULL; + mutex_unlock(&driver->md_session_lock); + return err; +} + +static void diag_md_session_close(int pid) +{ + int i; + uint8_t found = 0; + struct diag_md_session_t *session_info = NULL; + + session_info = diag_md_session_get_pid(pid); + if (!session_info) + return; + + for (i = 0; i < NUM_MD_SESSIONS; i++) { + if (driver->md_session_map[i] != session_info) + continue; + driver->md_session_map[i] = NULL; + driver->md_session_mask &= ~session_info->peripheral_mask; + } + diag_log_mask_free(session_info->log_mask); + kfree(session_info->log_mask); + session_info->log_mask = NULL; + diag_msg_mask_free(session_info->msg_mask, + session_info); + kfree(session_info->msg_mask); + session_info->msg_mask = NULL; + diag_event_mask_free(session_info->event_mask); + kfree(session_info->event_mask); + session_info->event_mask = NULL; + del_timer(&session_info->hdlc_reset_timer); + + for (i = 0; i < NUM_MD_SESSIONS && !found; i++) { + if (driver->md_session_map[i] != NULL) + found = 1; + } + + driver->md_session_mode = (found) ? DIAG_MD_PERIPHERAL : DIAG_MD_NONE; + kfree(session_info); + session_info = NULL; + DIAG_LOG(DIAG_DEBUG_USERSPACE, "cleared up session\n"); +} + +struct diag_md_session_t *diag_md_session_get_pid(int pid) +{ + int i; + if (pid <= 0) + return NULL; + for (i = 0; i < NUM_MD_SESSIONS; i++) { + if (driver->md_session_map[i] && + driver->md_session_map[i]->pid == pid) + return driver->md_session_map[i]; + } + return NULL; +} + +struct diag_md_session_t *diag_md_session_get_peripheral(uint8_t peripheral) +{ + if (peripheral >= NUM_MD_SESSIONS) + return NULL; + return driver->md_session_map[peripheral]; +} + +static int diag_md_peripheral_switch(int pid, + int peripheral_mask, int req_mode) { + int i, bit = 0; + struct diag_md_session_t *session_info = NULL; + + session_info = diag_md_session_get_pid(pid); + if (!session_info) + return -EINVAL; + if (req_mode != DIAG_USB_MODE || req_mode != DIAG_MEMORY_DEVICE_MODE) + return -EINVAL; + + /* + * check that md_session_map for i == session_info, + * if not then race condition occurred and bail + */ + for (i = 0; i < NUM_MD_SESSIONS; i++) { + bit = MD_PERIPHERAL_MASK(i) & peripheral_mask; + if (!bit) + continue; + if (req_mode == DIAG_USB_MODE) { + if (driver->md_session_map[i] != session_info) + return -EINVAL; + driver->md_session_map[i] = NULL; + driver->md_session_mask &= ~bit; + session_info->peripheral_mask &= ~bit; + + } else { + if (driver->md_session_map[i] != NULL) + return -EINVAL; + driver->md_session_map[i] = session_info; + driver->md_session_mask |= bit; + session_info->peripheral_mask |= bit; + + } + } + + driver->md_session_mode = DIAG_MD_PERIPHERAL; + DIAG_LOG(DIAG_DEBUG_USERSPACE, "Changed Peripherals:0x%x to mode:%d\n", + peripheral_mask, req_mode); +} + +static int diag_md_session_check(int curr_mode, int req_mode, + const struct diag_logging_mode_param_t *param, + uint8_t *change_mode) +{ + int i, bit = 0, err = 0, peripheral_mask = 0; + int change_mask = 0; + struct diag_md_session_t *session_info = NULL; + + if (!param || !change_mode) + return -EIO; + + *change_mode = 0; + + switch (curr_mode) { + case DIAG_USB_MODE: + case DIAG_MEMORY_DEVICE_MODE: + case DIAG_MULTI_MODE: + break; + default: + return -EINVAL; + } + + if (req_mode != DIAG_USB_MODE && req_mode != DIAG_MEMORY_DEVICE_MODE) + return -EINVAL; + + if (req_mode == DIAG_USB_MODE) { + if (curr_mode == DIAG_USB_MODE) + return 0; + mutex_lock(&driver->md_session_lock); + if (driver->md_session_mode == DIAG_MD_NONE + && driver->md_session_mask == 0 && driver->logging_mask) { + *change_mode = 1; + mutex_unlock(&driver->md_session_lock); + return 0; + } + /* + * curr_mode is either DIAG_MULTI_MODE or DIAG_MD_MODE + * Check if requested peripherals are already in usb mode + */ + for (i = 0; i < NUM_MD_SESSIONS; i++) { + bit = MD_PERIPHERAL_MASK(i) & param->peripheral_mask; + if (!bit) + continue; + if (bit & driver->logging_mask) + change_mask |= bit; + } + if (!change_mask) { + mutex_unlock(&driver->md_session_lock); + return 0; + } + + /* + * Change is needed. Check if this md_session has set all the + * requested peripherals. If another md session set a requested + * peripheral then we cannot switch that peripheral to USB. + * If this session owns all the requested peripherals, then + * call function to switch the modes/masks for the md_session + */ + session_info = diag_md_session_get_pid(current->tgid); + if (!session_info) { + *change_mode = 1; + mutex_unlock(&driver->md_session_lock); + return 0; + } + peripheral_mask = session_info->peripheral_mask; + if ((change_mask & peripheral_mask) + != change_mask) { + DIAG_LOG(DIAG_DEBUG_USERSPACE, + "Another MD Session owns a requested peripheral\n"); + mutex_unlock(&driver->md_session_lock); + return -EINVAL; + } + *change_mode = 1; + + /* If all peripherals are being set to USB Mode, call close */ + if (~change_mask & peripheral_mask) { + err = diag_md_peripheral_switch(current->tgid, + change_mask, DIAG_USB_MODE); + } else + diag_md_session_close(current->tgid); + mutex_unlock(&driver->md_session_lock); + return err; + + } else if (req_mode == DIAG_MEMORY_DEVICE_MODE) { + /* + * Get bit mask that represents what peripherals already have + * been set. Check that requested peripherals already set are + * owned by this md session + */ + mutex_lock(&driver->md_session_lock); + change_mask = driver->md_session_mask & param->peripheral_mask; + session_info = diag_md_session_get_pid(current->tgid); + + if (session_info) { + if ((session_info->peripheral_mask & change_mask) + != change_mask) { + DIAG_LOG(DIAG_DEBUG_USERSPACE, + "Another MD Session owns a requested peripheral\n"); + mutex_unlock(&driver->md_session_lock); + return -EINVAL; + } + err = diag_md_peripheral_switch(current->tgid, + change_mask, DIAG_USB_MODE); + mutex_unlock(&driver->md_session_lock); + } else { + mutex_unlock(&driver->md_session_lock); + if (change_mask) { + DIAG_LOG(DIAG_DEBUG_USERSPACE, + "Another MD Session owns a requested peripheral\n"); + return -EINVAL; + } + err = diag_md_session_create(DIAG_MD_PERIPHERAL, + param->peripheral_mask, DIAG_LOCAL_PROC); + } + *change_mode = 1; + return err; + } + return -EINVAL; +} + +static uint32_t diag_translate_mask(uint32_t peripheral_mask) +{ + uint32_t ret = 0; + + if (peripheral_mask & DIAG_CON_APSS) + ret |= (1 << APPS_DATA); + if (peripheral_mask & DIAG_CON_MPSS) + ret |= (1 << PERIPHERAL_MODEM); + if (peripheral_mask & DIAG_CON_LPASS) + ret |= (1 << PERIPHERAL_LPASS); + if (peripheral_mask & DIAG_CON_WCNSS) + ret |= (1 << PERIPHERAL_WCNSS); + if (peripheral_mask & DIAG_CON_SENSORS) + ret |= (1 << PERIPHERAL_SENSORS); + if (peripheral_mask & DIAG_CON_WDSP) + ret |= (1 << PERIPHERAL_WDSP); + if (peripheral_mask & DIAG_CON_CDSP) + ret |= (1 << PERIPHERAL_CDSP); + if (peripheral_mask & DIAG_CON_UPD_WLAN) + ret |= (1 << UPD_WLAN); + if (peripheral_mask & DIAG_CON_UPD_AUDIO) + ret |= (1 << UPD_AUDIO); + if (peripheral_mask & DIAG_CON_UPD_SENSORS) + ret |= (1 << UPD_SENSORS); + + return ret; +} + +static int diag_switch_logging(struct diag_logging_mode_param_t *param) +{ + int new_mode, i = 0; + int curr_mode; + int err = 0; + uint8_t do_switch = 1; + uint32_t peripheral_mask = 0; + uint8_t peripheral, upd; + + if (!param) + return -EINVAL; + + if (!param->peripheral_mask) { + DIAG_LOG(DIAG_DEBUG_USERSPACE, + "asking for mode switch with no peripheral mask set\n"); + return -EINVAL; + } + + if (param->pd_mask) { + switch (param->pd_mask) { + case DIAG_CON_UPD_WLAN: + peripheral = PERIPHERAL_MODEM; + upd = UPD_WLAN; + break; + case DIAG_CON_UPD_AUDIO: + peripheral = PERIPHERAL_LPASS; + upd = UPD_AUDIO; + break; + case DIAG_CON_UPD_SENSORS: + peripheral = PERIPHERAL_LPASS; + upd = UPD_SENSORS; + break; + default: + DIAG_LOG(DIAG_DEBUG_USERSPACE, + "asking for mode switch with no pd mask set\n"); + return -EINVAL; + } + + mutex_lock(&driver->md_session_lock); + if (driver->md_session_map[peripheral] && + (MD_PERIPHERAL_MASK(peripheral) & + diag_mux->mux_mask)) { + DIAG_LOG(DIAG_DEBUG_USERSPACE, + "diag_fr: User PD is already logging onto active peripheral logging\n"); + i = upd - UPD_WLAN; + mutex_unlock(&driver->md_session_lock); + driver->pd_session_clear[i] = 0; + return -EINVAL; + } + mutex_unlock(&driver->md_session_lock); + peripheral_mask = + diag_translate_mask(param->pd_mask); + param->peripheral_mask = peripheral_mask; + i = upd - UPD_WLAN; + if (!driver->pd_session_clear[i]) { + driver->pd_logging_mode[i] = 1; + driver->num_pd_session += 1; + } + driver->pd_session_clear[i] = 0; + } else { + peripheral_mask = + diag_translate_mask(param->peripheral_mask); + param->peripheral_mask = peripheral_mask; + } + + switch (param->req_mode) { + case CALLBACK_MODE: + case UART_MODE: + case SOCKET_MODE: + case MEMORY_DEVICE_MODE: + new_mode = DIAG_MEMORY_DEVICE_MODE; + break; + case USB_MODE: + new_mode = DIAG_USB_MODE; + break; + default: + pr_err("diag: In %s, request to switch to invalid mode: %d\n", + __func__, param->req_mode); + return -EINVAL; + } + + curr_mode = driver->logging_mode; + DIAG_LOG(DIAG_DEBUG_USERSPACE, + "request to switch logging from %d mask:%0x to new_mode %d mask:%0x\n", + curr_mode, driver->md_session_mask, new_mode, peripheral_mask); + + err = diag_md_session_check(curr_mode, new_mode, param, &do_switch); + if (err) { + DIAG_LOG(DIAG_DEBUG_USERSPACE, + "err from diag_md_session_check, err: %d\n", err); + return err; + } + + if (do_switch == 0) { + DIAG_LOG(DIAG_DEBUG_USERSPACE, + "not switching modes c: %d n: %d\n", + curr_mode, new_mode); + return 0; + } + + diag_ws_reset(DIAG_WS_MUX); + err = diag_mux_switch_logging(&new_mode, &peripheral_mask); + if (err) { + pr_err("diag: In %s, unable to switch mode from %d to %d, err: %d\n", + __func__, curr_mode, new_mode, err); + driver->logging_mode = curr_mode; + goto fail; + } + driver->logging_mode = new_mode; + driver->logging_mask = peripheral_mask; + DIAG_LOG(DIAG_DEBUG_USERSPACE, + "Switch logging to %d mask:%0x\n", new_mode, peripheral_mask); + + /* Update to take peripheral_mask */ + if (new_mode != DIAG_MEMORY_DEVICE_MODE) { + diag_update_real_time_vote(DIAG_PROC_MEMORY_DEVICE, + MODE_REALTIME, ALL_PROC); + } else { + diag_update_proc_vote(DIAG_PROC_MEMORY_DEVICE, VOTE_UP, + ALL_PROC); + } + + if (!(new_mode == DIAG_MEMORY_DEVICE_MODE && + curr_mode == DIAG_USB_MODE)) { + queue_work(driver->diag_real_time_wq, + &driver->diag_real_time_work); + } + + return 0; +fail: + return err; +} + +static int diag_ioctl_dci_reg(unsigned long ioarg) +{ + int result = -EINVAL; + struct diag_dci_reg_tbl_t dci_reg_params; + + if (copy_from_user(&dci_reg_params, (void __user *)ioarg, + sizeof(struct diag_dci_reg_tbl_t))) + return -EFAULT; + + result = diag_dci_register_client(&dci_reg_params); + + return result; +} + +static int diag_ioctl_dci_health_stats(unsigned long ioarg) +{ + int result = -EINVAL; + struct diag_dci_health_stats_proc stats; + + if (copy_from_user(&stats, (void __user *)ioarg, + sizeof(struct diag_dci_health_stats_proc))) + return -EFAULT; + + result = diag_dci_copy_health_stats(&stats); + if (result == DIAG_DCI_NO_ERROR) { + if (copy_to_user((void __user *)ioarg, &stats, + sizeof(struct diag_dci_health_stats_proc))) + return -EFAULT; + } + + return result; +} + +static int diag_ioctl_dci_log_status(unsigned long ioarg) +{ + struct diag_log_event_stats le_stats; + struct diag_dci_client_tbl *dci_client = NULL; + + if (copy_from_user(&le_stats, (void __user *)ioarg, + sizeof(struct diag_log_event_stats))) + return -EFAULT; + + dci_client = diag_dci_get_client_entry(le_stats.client_id); + if (!dci_client) + return DIAG_DCI_NOT_SUPPORTED; + le_stats.is_set = diag_dci_query_log_mask(dci_client, le_stats.code); + if (copy_to_user((void __user *)ioarg, &le_stats, + sizeof(struct diag_log_event_stats))) + return -EFAULT; + + return DIAG_DCI_NO_ERROR; +} + +static int diag_ioctl_dci_event_status(unsigned long ioarg) +{ + struct diag_log_event_stats le_stats; + struct diag_dci_client_tbl *dci_client = NULL; + + if (copy_from_user(&le_stats, (void __user *)ioarg, + sizeof(struct diag_log_event_stats))) + return -EFAULT; + + dci_client = diag_dci_get_client_entry(le_stats.client_id); + if (!dci_client) + return DIAG_DCI_NOT_SUPPORTED; + + le_stats.is_set = diag_dci_query_event_mask(dci_client, le_stats.code); + if (copy_to_user((void __user *)ioarg, &le_stats, + sizeof(struct diag_log_event_stats))) + return -EFAULT; + + return DIAG_DCI_NO_ERROR; +} + +static int diag_ioctl_lsm_deinit(void) +{ + int i; + + mutex_lock(&driver->diagchar_mutex); + for (i = 0; i < driver->num_clients; i++) + if (driver->client_map[i].pid == current->tgid) + break; + + if (i == driver->num_clients) { + mutex_unlock(&driver->diagchar_mutex); + return -EINVAL; + } + if (!(driver->data_ready[i] & DEINIT_TYPE)) { + driver->data_ready[i] |= DEINIT_TYPE; + atomic_inc(&driver->data_ready_notif[i]); + } + mutex_unlock(&driver->diagchar_mutex); + wake_up_interruptible(&driver->wait_q); + + return 1; +} + +static int diag_ioctl_vote_real_time(unsigned long ioarg) +{ + int real_time = 0; + int temp_proc = ALL_PROC; + struct real_time_vote_t vote; + struct diag_dci_client_tbl *dci_client = NULL; + + if (copy_from_user(&vote, (void __user *)ioarg, + sizeof(struct real_time_vote_t))) + return -EFAULT; + + if (vote.proc > DIAG_PROC_MEMORY_DEVICE || + vote.real_time_vote > MODE_UNKNOWN || + vote.client_id < 0) { + pr_err("diag: %s, invalid params, proc: %d, vote: %d, client_id: %d\n", + __func__, vote.proc, vote.real_time_vote, + vote.client_id); + return -EINVAL; + } + + driver->real_time_update_busy++; + if (vote.proc == DIAG_PROC_DCI) { + dci_client = diag_dci_get_client_entry(vote.client_id); + if (!dci_client) { + driver->real_time_update_busy--; + return DIAG_DCI_NOT_SUPPORTED; + } + diag_dci_set_real_time(dci_client, vote.real_time_vote); + real_time = diag_dci_get_cumulative_real_time( + dci_client->client_info.token); + diag_update_real_time_vote(vote.proc, real_time, + dci_client->client_info.token); + } else { + real_time = vote.real_time_vote; + temp_proc = vote.client_id; + diag_update_real_time_vote(vote.proc, real_time, + temp_proc); + } + queue_work(driver->diag_real_time_wq, &driver->diag_real_time_work); + return 0; +} + +static int diag_ioctl_get_real_time(unsigned long ioarg) +{ + int i; + int retry_count = 0; + int timer = 0; + struct real_time_query_t rt_query; + + if (copy_from_user(&rt_query, (void __user *)ioarg, + sizeof(struct real_time_query_t))) + return -EFAULT; + while (retry_count < 3) { + if (driver->real_time_update_busy > 0) { + retry_count++; + /* + * The value 10000 was chosen empirically as an + * optimum value in order to give the work in + * diag_real_time_wq to complete processing. + */ + for (timer = 0; timer < 5; timer++) + usleep_range(10000, 10100); + } else { + break; + } + } + + if (driver->real_time_update_busy > 0) + return -EAGAIN; + + if (rt_query.proc < 0 || rt_query.proc >= DIAG_NUM_PROC) { + pr_err("diag: Invalid proc %d in %s\n", rt_query.proc, + __func__); + return -EINVAL; + } + rt_query.real_time = driver->real_time_mode[rt_query.proc]; + /* + * For the local processor, if any of the peripherals is in buffering + * mode, overwrite the value of real time with UNKNOWN_MODE + */ + if (rt_query.proc == DIAG_LOCAL_PROC) { + for (i = 0; i < NUM_PERIPHERALS; i++) { + if (!driver->feature[i].peripheral_buffering) + continue; + switch (driver->buffering_mode[i].mode) { + case DIAG_BUFFERING_MODE_CIRCULAR: + case DIAG_BUFFERING_MODE_THRESHOLD: + rt_query.real_time = MODE_UNKNOWN; + break; + } + } + } + + if (copy_to_user((void __user *)ioarg, &rt_query, + sizeof(struct real_time_query_t))) + return -EFAULT; + + return 0; +} + +static int diag_ioctl_set_buffering_mode(unsigned long ioarg) +{ + struct diag_buffering_mode_t params; + int peripheral = 0; + uint8_t diag_id = 0; + + if (copy_from_user(¶ms, (void __user *)ioarg, sizeof(params))) + return -EFAULT; + + diag_map_pd_to_diagid(params.peripheral, &diag_id, &peripheral); + + if ((peripheral < 0) || + peripheral >= NUM_PERIPHERALS) { + pr_err("diag: In %s, invalid peripheral %d\n", __func__, + peripheral); + return -EIO; + } + + if (params.peripheral > NUM_PERIPHERALS && + !driver->feature[peripheral].pd_buffering) { + pr_err("diag: In %s, pd buffering not supported for peripheral:%d\n", + __func__, peripheral); + return -EIO; + } + + if (!driver->feature[peripheral].peripheral_buffering) { + pr_err("diag: In %s, peripheral %d doesn't support buffering\n", + __func__, peripheral); + return -EIO; + } + + mutex_lock(&driver->mode_lock); + driver->buffering_flag[params.peripheral] = 1; + mutex_unlock(&driver->mode_lock); + + return diag_send_peripheral_buffering_mode(¶ms); +} + +static int diag_ioctl_peripheral_drain_immediate(unsigned long ioarg) +{ + uint8_t pd, diag_id = 0; + int peripheral = 0; + + if (copy_from_user(&pd, (void __user *)ioarg, sizeof(uint8_t))) + return -EFAULT; + + diag_map_pd_to_diagid(pd, &diag_id, &peripheral); + + if ((peripheral < 0) || + peripheral >= NUM_PERIPHERALS) { + pr_err("diag: In %s, invalid peripheral %d\n", __func__, + peripheral); + return -EINVAL; + } + + if (pd > NUM_PERIPHERALS && + !driver->feature[peripheral].pd_buffering) { + pr_err("diag: In %s, pd buffering not supported for peripheral:%d\n", + __func__, peripheral); + return -EIO; + } + + return diag_send_peripheral_drain_immediate(pd, diag_id, peripheral); +} + +static int diag_ioctl_dci_support(unsigned long ioarg) +{ + struct diag_dci_peripherals_t dci_support; + int result = -EINVAL; + + if (copy_from_user(&dci_support, (void __user *)ioarg, + sizeof(struct diag_dci_peripherals_t))) + return -EFAULT; + + result = diag_dci_get_support_list(&dci_support); + if (result == DIAG_DCI_NO_ERROR) + if (copy_to_user((void __user *)ioarg, &dci_support, + sizeof(struct diag_dci_peripherals_t))) + return -EFAULT; + + return result; +} + +static int diag_ioctl_hdlc_toggle(unsigned long ioarg) +{ + uint8_t hdlc_support; + struct diag_md_session_t *session_info = NULL; + if (copy_from_user(&hdlc_support, (void __user *)ioarg, + sizeof(uint8_t))) + return -EFAULT; + mutex_lock(&driver->hdlc_disable_mutex); + mutex_lock(&driver->md_session_lock); + session_info = diag_md_session_get_pid(current->tgid); + if (session_info) + session_info->hdlc_disabled = hdlc_support; + else + driver->hdlc_disabled = hdlc_support; + mutex_unlock(&driver->md_session_lock); + mutex_unlock(&driver->hdlc_disable_mutex); + diag_update_md_clients(HDLC_SUPPORT_TYPE); + + return 0; +} + +static int diag_ioctl_query_pd_logging(struct diag_logging_mode_param_t *param) +{ + int ret = -EINVAL; + int peripheral; + char *p_str = NULL; + + if (!param) + return -EINVAL; + + if (!param->pd_mask) { + DIAG_LOG(DIAG_DEBUG_USERSPACE, + "query with no pd mask set, returning error\n"); + return -EINVAL; + } + + switch (param->pd_mask) { + case DIAG_CON_UPD_WLAN: + peripheral = PERIPHERAL_MODEM; + p_str = "MODEM"; + break; + case DIAG_CON_UPD_AUDIO: + case DIAG_CON_UPD_SENSORS: + peripheral = PERIPHERAL_LPASS; + p_str = "LPASS"; + break; + default: + DIAG_LOG(DIAG_DEBUG_USERSPACE, + "Invalid pd mask, returning EINVAL\n"); + return -EINVAL; + } + + DIAG_LOG(DIAG_DEBUG_USERSPACE, + "diag: %s: Untagging support on APPS is %s\n", __func__, + ((driver->supports_apps_header_untagging) ? + "present" : "absent")); + + DIAG_LOG(DIAG_DEBUG_USERSPACE, + "diag: %s: Tagging support on %s is %s\n", + __func__, p_str, + (driver->feature[peripheral].untag_header ? + "present" : "absent")); + + if (driver->supports_apps_header_untagging && + driver->feature[peripheral].untag_header) + ret = 0; + + return ret; +} + +static int diag_ioctl_register_callback(unsigned long ioarg) +{ + int err = 0; + struct diag_callback_reg_t reg; + + if (copy_from_user(®, (void __user *)ioarg, + sizeof(struct diag_callback_reg_t))) { + return -EFAULT; + } + + if (reg.proc < 0 || reg.proc >= DIAG_NUM_PROC) { + pr_err("diag: In %s, invalid proc %d for callback registration\n", + __func__, reg.proc); + return -EINVAL; + } + + if (driver->md_session_mode == DIAG_MD_PERIPHERAL) + return -EIO; + + return err; +} + +static int diag_cmd_register_tbl(struct diag_cmd_reg_tbl_t *reg_tbl) +{ + int i; + int err = 0; + uint32_t count = 0; + struct diag_cmd_reg_entry_t *entries = NULL; + const uint16_t entry_len = sizeof(struct diag_cmd_reg_entry_t); + + + if (!reg_tbl) { + pr_err("diag: In %s, invalid registration table\n", __func__); + return -EINVAL; + } + + count = reg_tbl->count; + if ((UINT_MAX / entry_len) < count) { + pr_warn("diag: In %s, possbile integer overflow.\n", __func__); + return -EFAULT; + } + + entries = kzalloc(count * entry_len, GFP_KERNEL); + if (!entries) { + pr_err("diag: In %s, unable to create memory for registration table entries\n", + __func__); + return -ENOMEM; + } + + err = copy_from_user(entries, reg_tbl->entries, count * entry_len); + if (err) { + pr_err("diag: In %s, error copying data from userspace, err: %d\n", + __func__, err); + kfree(entries); + return -EFAULT; + } + + for (i = 0; i < count; i++) { + err = diag_cmd_add_reg(&entries[i], APPS_DATA, current->tgid); + if (err) { + pr_err("diag: In %s, unable to register command, err: %d\n", + __func__, err); + break; + } + } + + kfree(entries); + return err; +} + +static int diag_ioctl_cmd_reg(unsigned long ioarg) +{ + struct diag_cmd_reg_tbl_t reg_tbl; + + if (copy_from_user(®_tbl, (void __user *)ioarg, + sizeof(struct diag_cmd_reg_tbl_t))) { + return -EFAULT; + } + + return diag_cmd_register_tbl(®_tbl); +} + +static int diag_ioctl_cmd_dereg(void) +{ + diag_cmd_remove_reg_by_pid(current->tgid); + return 0; +} + +#ifdef CONFIG_COMPAT +/* + * @sync_obj_name: name of the synchronization object associated with this proc + * @count: number of entries in the bind + * @params: the actual packet registrations + */ +struct diag_cmd_reg_tbl_compat_t { + char sync_obj_name[MAX_SYNC_OBJ_NAME_SIZE]; + uint32_t count; + compat_uptr_t entries; +}; + +static int diag_ioctl_cmd_reg_compat(unsigned long ioarg) +{ + struct diag_cmd_reg_tbl_compat_t reg_tbl_compat; + struct diag_cmd_reg_tbl_t reg_tbl; + + if (copy_from_user(®_tbl_compat, (void __user *)ioarg, + sizeof(struct diag_cmd_reg_tbl_compat_t))) { + return -EFAULT; + } + + strlcpy(reg_tbl.sync_obj_name, reg_tbl_compat.sync_obj_name, + MAX_SYNC_OBJ_NAME_SIZE); + reg_tbl.count = reg_tbl_compat.count; + reg_tbl.entries = (struct diag_cmd_reg_entry_t *) + (uintptr_t)reg_tbl_compat.entries; + + return diag_cmd_register_tbl(®_tbl); +} + +long diagchar_compat_ioctl(struct file *filp, + unsigned int iocmd, unsigned long ioarg) +{ + int result = -EINVAL; + int client_id = 0; + uint16_t delayed_rsp_id = 0; + uint16_t remote_dev; + struct diag_dci_client_tbl *dci_client = NULL; + struct diag_logging_mode_param_t mode_param; + + switch (iocmd) { + case DIAG_IOCTL_COMMAND_REG: + result = diag_ioctl_cmd_reg_compat(ioarg); + break; + case DIAG_IOCTL_COMMAND_DEREG: + result = diag_ioctl_cmd_dereg(); + break; + case DIAG_IOCTL_GET_DELAYED_RSP_ID: + delayed_rsp_id = diag_get_next_delayed_rsp_id(); + if (copy_to_user((void __user *)ioarg, &delayed_rsp_id, + sizeof(uint16_t))) + result = -EFAULT; + else + result = 0; + break; + case DIAG_IOCTL_DCI_REG: + result = diag_ioctl_dci_reg(ioarg); + break; + case DIAG_IOCTL_DCI_DEINIT: + mutex_lock(&driver->dci_mutex); + if (copy_from_user((void *)&client_id, (void __user *)ioarg, + sizeof(int))) { + mutex_unlock(&driver->dci_mutex); + return -EFAULT; + } + dci_client = diag_dci_get_client_entry(client_id); + if (!dci_client) { + mutex_unlock(&driver->dci_mutex); + return DIAG_DCI_NOT_SUPPORTED; + } + result = diag_dci_deinit_client(dci_client); + mutex_unlock(&driver->dci_mutex); + break; + case DIAG_IOCTL_DCI_SUPPORT: + result = diag_ioctl_dci_support(ioarg); + break; + case DIAG_IOCTL_DCI_HEALTH_STATS: + mutex_lock(&driver->dci_mutex); + result = diag_ioctl_dci_health_stats(ioarg); + mutex_unlock(&driver->dci_mutex); + break; + case DIAG_IOCTL_DCI_LOG_STATUS: + mutex_lock(&driver->dci_mutex); + result = diag_ioctl_dci_log_status(ioarg); + mutex_unlock(&driver->dci_mutex); + break; + case DIAG_IOCTL_DCI_EVENT_STATUS: + mutex_lock(&driver->dci_mutex); + result = diag_ioctl_dci_event_status(ioarg); + mutex_unlock(&driver->dci_mutex); + break; + case DIAG_IOCTL_DCI_CLEAR_LOGS: + mutex_lock(&driver->dci_mutex); + if (copy_from_user((void *)&client_id, (void __user *)ioarg, + sizeof(int))) { + mutex_unlock(&driver->dci_mutex); + return -EFAULT; + } + result = diag_dci_clear_log_mask(client_id); + mutex_unlock(&driver->dci_mutex); + break; + case DIAG_IOCTL_DCI_CLEAR_EVENTS: + mutex_lock(&driver->dci_mutex); + if (copy_from_user(&client_id, (void __user *)ioarg, + sizeof(int))) { + mutex_unlock(&driver->dci_mutex); + return -EFAULT; + } + result = diag_dci_clear_event_mask(client_id); + mutex_unlock(&driver->dci_mutex); + break; + case DIAG_IOCTL_LSM_DEINIT: + result = diag_ioctl_lsm_deinit(); + break; + case DIAG_IOCTL_SWITCH_LOGGING: + if (copy_from_user((void *)&mode_param, (void __user *)ioarg, + sizeof(mode_param))) + return -EFAULT; + mutex_lock(&driver->diagchar_mutex); + result = diag_switch_logging(&mode_param); + mutex_unlock(&driver->diagchar_mutex); + break; + case DIAG_IOCTL_REMOTE_DEV: + remote_dev = diag_get_remote_device_mask(); + if (copy_to_user((void __user *)ioarg, &remote_dev, + sizeof(uint16_t))) + result = -EFAULT; + else + result = 1; + break; + case DIAG_IOCTL_VOTE_REAL_TIME: + mutex_lock(&driver->dci_mutex); + result = diag_ioctl_vote_real_time(ioarg); + mutex_unlock(&driver->dci_mutex); + break; + case DIAG_IOCTL_GET_REAL_TIME: + result = diag_ioctl_get_real_time(ioarg); + break; + case DIAG_IOCTL_PERIPHERAL_BUF_CONFIG: + result = diag_ioctl_set_buffering_mode(ioarg); + break; + case DIAG_IOCTL_PERIPHERAL_BUF_DRAIN: + result = diag_ioctl_peripheral_drain_immediate(ioarg); + break; + case DIAG_IOCTL_REGISTER_CALLBACK: + result = diag_ioctl_register_callback(ioarg); + break; + case DIAG_IOCTL_HDLC_TOGGLE: + result = diag_ioctl_hdlc_toggle(ioarg); + break; + case DIAG_IOCTL_QUERY_PD_LOGGING: + if (copy_from_user((void *)&mode_param, (void __user *)ioarg, + sizeof(mode_param))) + return -EFAULT; + result = diag_ioctl_query_pd_logging(&mode_param); + break; + } + return result; +} +#endif + +long diagchar_ioctl(struct file *filp, + unsigned int iocmd, unsigned long ioarg) +{ + int result = -EINVAL; + int client_id = 0; + uint16_t delayed_rsp_id; + uint16_t remote_dev; + struct diag_dci_client_tbl *dci_client = NULL; + struct diag_logging_mode_param_t mode_param; + + switch (iocmd) { + case DIAG_IOCTL_COMMAND_REG: + result = diag_ioctl_cmd_reg(ioarg); + break; + case DIAG_IOCTL_COMMAND_DEREG: + result = diag_ioctl_cmd_dereg(); + break; + case DIAG_IOCTL_GET_DELAYED_RSP_ID: + delayed_rsp_id = diag_get_next_delayed_rsp_id(); + if (copy_to_user((void __user *)ioarg, &delayed_rsp_id, + sizeof(uint16_t))) + result = -EFAULT; + else + result = 0; + break; + case DIAG_IOCTL_DCI_REG: + result = diag_ioctl_dci_reg(ioarg); + break; + case DIAG_IOCTL_DCI_DEINIT: + mutex_lock(&driver->dci_mutex); + if (copy_from_user((void *)&client_id, (void __user *)ioarg, + sizeof(int))) { + mutex_unlock(&driver->dci_mutex); + return -EFAULT; + } + dci_client = diag_dci_get_client_entry(client_id); + if (!dci_client) { + mutex_unlock(&driver->dci_mutex); + return DIAG_DCI_NOT_SUPPORTED; + } + result = diag_dci_deinit_client(dci_client); + mutex_unlock(&driver->dci_mutex); + break; + case DIAG_IOCTL_DCI_SUPPORT: + result = diag_ioctl_dci_support(ioarg); + break; + case DIAG_IOCTL_DCI_HEALTH_STATS: + mutex_lock(&driver->dci_mutex); + result = diag_ioctl_dci_health_stats(ioarg); + mutex_unlock(&driver->dci_mutex); + break; + case DIAG_IOCTL_DCI_LOG_STATUS: + mutex_lock(&driver->dci_mutex); + result = diag_ioctl_dci_log_status(ioarg); + mutex_unlock(&driver->dci_mutex); + break; + case DIAG_IOCTL_DCI_EVENT_STATUS: + mutex_lock(&driver->dci_mutex); + result = diag_ioctl_dci_event_status(ioarg); + mutex_unlock(&driver->dci_mutex); + break; + case DIAG_IOCTL_DCI_CLEAR_LOGS: + mutex_lock(&driver->dci_mutex); + if (copy_from_user((void *)&client_id, (void __user *)ioarg, + sizeof(int))) { + mutex_unlock(&driver->dci_mutex); + return -EFAULT; + } + result = diag_dci_clear_log_mask(client_id); + mutex_unlock(&driver->dci_mutex); + break; + case DIAG_IOCTL_DCI_CLEAR_EVENTS: + mutex_lock(&driver->dci_mutex); + if (copy_from_user(&client_id, (void __user *)ioarg, + sizeof(int))) { + mutex_unlock(&driver->dci_mutex); + return -EFAULT; + } + result = diag_dci_clear_event_mask(client_id); + mutex_unlock(&driver->dci_mutex); + break; + case DIAG_IOCTL_LSM_DEINIT: + result = diag_ioctl_lsm_deinit(); + break; + case DIAG_IOCTL_SWITCH_LOGGING: + if (copy_from_user((void *)&mode_param, (void __user *)ioarg, + sizeof(mode_param))) + return -EFAULT; + mutex_lock(&driver->diagchar_mutex); + result = diag_switch_logging(&mode_param); + mutex_unlock(&driver->diagchar_mutex); + break; + case DIAG_IOCTL_REMOTE_DEV: + remote_dev = diag_get_remote_device_mask(); + if (copy_to_user((void __user *)ioarg, &remote_dev, + sizeof(uint16_t))) + result = -EFAULT; + else + result = 1; + break; + case DIAG_IOCTL_VOTE_REAL_TIME: + mutex_lock(&driver->dci_mutex); + result = diag_ioctl_vote_real_time(ioarg); + mutex_unlock(&driver->dci_mutex); + break; + case DIAG_IOCTL_GET_REAL_TIME: + result = diag_ioctl_get_real_time(ioarg); + break; + case DIAG_IOCTL_PERIPHERAL_BUF_CONFIG: + result = diag_ioctl_set_buffering_mode(ioarg); + break; + case DIAG_IOCTL_PERIPHERAL_BUF_DRAIN: + result = diag_ioctl_peripheral_drain_immediate(ioarg); + break; + case DIAG_IOCTL_REGISTER_CALLBACK: + result = diag_ioctl_register_callback(ioarg); + break; + case DIAG_IOCTL_HDLC_TOGGLE: + result = diag_ioctl_hdlc_toggle(ioarg); + break; + case DIAG_IOCTL_QUERY_PD_LOGGING: + if (copy_from_user((void *)&mode_param, (void __user *)ioarg, + sizeof(mode_param))) + return -EFAULT; + result = diag_ioctl_query_pd_logging(&mode_param); + break; + } + return result; +} + +static int diag_process_apps_data_hdlc(unsigned char *buf, int len, + int pkt_type) +{ + int err = 0; + int ret = PKT_DROP; + struct diag_apps_data_t *data = &hdlc_data; + struct diag_send_desc_type send = { NULL, NULL, DIAG_STATE_START, 0 }; + struct diag_hdlc_dest_type enc = { NULL, NULL, 0 }; + /* + * The maximum encoded size of the buffer can be atmost twice the length + * of the packet. Add three bytes foe footer - 16 bit CRC (2 bytes) + + * delimiter (1 byte). + */ + const uint32_t max_encoded_size = ((2 * len) + 3); + + if (!buf || len <= 0) { + pr_err("diag: In %s, invalid buf: %pK len: %d\n", + __func__, buf, len); + return -EIO; + } + + if (DIAG_MAX_HDLC_BUF_SIZE < max_encoded_size) { + pr_err_ratelimited("diag: In %s, encoded data is larger %d than the buffer size %d\n", + __func__, max_encoded_size, DIAG_MAX_HDLC_BUF_SIZE); + return -EBADMSG; + } + + send.state = DIAG_STATE_START; + send.pkt = buf; + send.last = (void *)(buf + len - 1); + send.terminate = 1; + + if (!data->buf) + data->buf = diagmem_alloc(driver, DIAG_MAX_HDLC_BUF_SIZE + + APF_DIAG_PADDING, + POOL_TYPE_HDLC); + if (!data->buf) { + ret = PKT_DROP; + goto fail_ret; + } + + if ((DIAG_MAX_HDLC_BUF_SIZE - data->len) <= max_encoded_size) { + err = diag_mux_write(DIAG_LOCAL_PROC, data->buf, data->len, + data->ctxt); + if (err) { + ret = -EIO; + goto fail_free_buf; + } + data->buf = NULL; + data->len = 0; + data->buf = diagmem_alloc(driver, DIAG_MAX_HDLC_BUF_SIZE + + APF_DIAG_PADDING, + POOL_TYPE_HDLC); + if (!data->buf) { + ret = PKT_DROP; + goto fail_ret; + } + } + + enc.dest = data->buf + data->len; + enc.dest_last = (void *)(data->buf + data->len + max_encoded_size); + diag_hdlc_encode(&send, &enc); + + /* + * This is to check if after HDLC encoding, we are still within + * the limits of aggregation buffer. If not, we write out the + * current buffer and start aggregation in a newly allocated + * buffer. + */ + if ((uintptr_t)enc.dest >= (uintptr_t)(data->buf + + DIAG_MAX_HDLC_BUF_SIZE)) { + err = diag_mux_write(DIAG_LOCAL_PROC, data->buf, data->len, + data->ctxt); + if (err) { + ret = -EIO; + goto fail_free_buf; + } + data->buf = NULL; + data->len = 0; + data->buf = diagmem_alloc(driver, DIAG_MAX_HDLC_BUF_SIZE + + APF_DIAG_PADDING, + POOL_TYPE_HDLC); + if (!data->buf) { + ret = PKT_DROP; + goto fail_ret; + } + + enc.dest = data->buf + data->len; + enc.dest_last = (void *)(data->buf + data->len + + max_encoded_size); + diag_hdlc_encode(&send, &enc); + } + + data->len = (((uintptr_t)enc.dest - (uintptr_t)data->buf) < + DIAG_MAX_HDLC_BUF_SIZE) ? + ((uintptr_t)enc.dest - (uintptr_t)data->buf) : + DIAG_MAX_HDLC_BUF_SIZE; + + if (pkt_type == DATA_TYPE_RESPONSE) { + err = diag_mux_write(DIAG_LOCAL_PROC, data->buf, data->len, + data->ctxt); + if (err) { + ret = -EIO; + goto fail_free_buf; + } + data->buf = NULL; + data->len = 0; + } + + return PKT_ALLOC; + +fail_free_buf: + diagmem_free(driver, data->buf, POOL_TYPE_HDLC); + data->buf = NULL; + data->len = 0; + +fail_ret: + return ret; +} + +static int diag_process_apps_data_non_hdlc(unsigned char *buf, int len, + int pkt_type) +{ + int err = 0; + int ret = PKT_DROP; + struct diag_pkt_frame_t header; + struct diag_apps_data_t *data = &non_hdlc_data; + /* + * The maximum packet size, when the data is non hdlc encoded is equal + * to the size of the packet frame header and the length. Add 1 for the + * delimiter 0x7E at the end. + */ + const uint32_t max_pkt_size = sizeof(header) + len + 1; + + if (!buf || len <= 0) { + pr_err("diag: In %s, invalid buf: %pK len: %d\n", + __func__, buf, len); + return -EIO; + } + + if (!data->buf) { + data->buf = diagmem_alloc(driver, DIAG_MAX_HDLC_BUF_SIZE + + APF_DIAG_PADDING, + POOL_TYPE_HDLC); + if (!data->buf) { + ret = PKT_DROP; + goto fail_ret; + } + } + + if ((DIAG_MAX_HDLC_BUF_SIZE - data->len) <= max_pkt_size) { + err = diag_mux_write(DIAG_LOCAL_PROC, data->buf, data->len, + data->ctxt); + if (err) { + ret = -EIO; + goto fail_free_buf; + } + data->buf = NULL; + data->len = 0; + data->buf = diagmem_alloc(driver, DIAG_MAX_HDLC_BUF_SIZE + + APF_DIAG_PADDING, + POOL_TYPE_HDLC); + if (!data->buf) { + ret = PKT_DROP; + goto fail_ret; + } + } + + header.start = CONTROL_CHAR; + header.version = 1; + header.length = len; + memcpy(data->buf + data->len, &header, sizeof(header)); + data->len += sizeof(header); + memcpy(data->buf + data->len, buf, len); + data->len += len; + *(uint8_t *)(data->buf + data->len) = CONTROL_CHAR; + data->len += sizeof(uint8_t); + if (pkt_type == DATA_TYPE_RESPONSE) { + err = diag_mux_write(DIAG_LOCAL_PROC, data->buf, data->len, + data->ctxt); + if (err) { + ret = -EIO; + goto fail_free_buf; + } + data->buf = NULL; + data->len = 0; + } + + return PKT_ALLOC; + +fail_free_buf: + diagmem_free(driver, data->buf, POOL_TYPE_HDLC); + data->buf = NULL; + data->len = 0; + +fail_ret: + return ret; +} + +static int diag_user_process_dci_data(const char __user *buf, int len) +{ + int err = 0; + const int mempool = POOL_TYPE_USER; + unsigned char *user_space_data = NULL; + + if (!buf || len <= 0 || len > diag_mempools[mempool].itemsize) { + pr_err_ratelimited("diag: In %s, invalid buf %pK len: %d\n", + __func__, buf, len); + return -EBADMSG; + } + + user_space_data = diagmem_alloc(driver, len, mempool); + if (!user_space_data) + return -ENOMEM; + + err = copy_from_user(user_space_data, buf, len); + if (err) { + pr_err_ratelimited("diag: In %s, unable to copy data from userspace, err: %d\n", + __func__, err); + err = DIAG_DCI_SEND_DATA_FAIL; + goto fail; + } + + err = diag_process_dci_transaction(user_space_data, len); +fail: + diagmem_free(driver, user_space_data, mempool); + user_space_data = NULL; + return err; +} + +static int diag_user_process_dci_apps_data(const char __user *buf, int len, + int pkt_type) +{ + int err = 0; + const int mempool = POOL_TYPE_COPY; + unsigned char *user_space_data = NULL; + + if (!buf || len <= 0 || len > diag_mempools[mempool].itemsize) { + pr_err_ratelimited("diag: In %s, invalid buf %pK len: %d\n", + __func__, buf, len); + return -EBADMSG; + } + + pkt_type &= (DCI_PKT_TYPE | DATA_TYPE_DCI_LOG | DATA_TYPE_DCI_EVENT); + if (!pkt_type) { + pr_err_ratelimited("diag: In %s, invalid pkt_type: %d\n", + __func__, pkt_type); + return -EBADMSG; + } + + user_space_data = diagmem_alloc(driver, len, mempool); + if (!user_space_data) + return -ENOMEM; + + err = copy_from_user(user_space_data, buf, len); + if (err) { + pr_alert("diag: In %s, unable to copy data from userspace, err: %d\n", + __func__, err); + goto fail; + } + + diag_process_apps_dci_read_data(pkt_type, user_space_data, len); +fail: + diagmem_free(driver, user_space_data, mempool); + user_space_data = NULL; + return err; +} + +static int diag_user_process_raw_data(const char __user *buf, int len) +{ + int err = 0; + int ret = 0; + int token_offset = 0; + int remote_proc = 0; + const int mempool = POOL_TYPE_COPY; + unsigned char *user_space_data = NULL; + + if (!buf || len <= 0 || len > CALLBACK_BUF_SIZE) { + pr_err_ratelimited("diag: In %s, invalid buf %pK len: %d\n", + __func__, buf, len); + return -EBADMSG; + } + + user_space_data = diagmem_alloc(driver, len, mempool); + if (!user_space_data) + return -ENOMEM; + + err = copy_from_user(user_space_data, buf, len); + if (err) { + pr_err("diag: copy failed for user space data\n"); + goto fail; + } + + /* Check for proc_type */ + remote_proc = diag_get_remote(*(int *)user_space_data); + if (remote_proc) { + token_offset = sizeof(int); + if (len <= MIN_SIZ_ALLOW) { + pr_err("diag: In %s, possible integer underflow, payload size: %d\n", + __func__, len); + diagmem_free(driver, user_space_data, mempool); + user_space_data = NULL; + return -EBADMSG; + } + len -= sizeof(int); + } + if (driver->mask_check) { + if (!mask_request_validate(user_space_data + + token_offset)) { + pr_alert("diag: mask request Invalid\n"); + diagmem_free(driver, user_space_data, mempool); + user_space_data = NULL; + return -EFAULT; + } + } + if (remote_proc) { + ret = diag_send_raw_data_remote(remote_proc, + (void *)(user_space_data + token_offset), + len, USER_SPACE_RAW_DATA); + if (ret) { + pr_err("diag: Error sending data to remote proc %d, err: %d\n", + remote_proc, ret); + } + } else { + wait_event_interruptible(driver->wait_q, + (driver->in_busy_pktdata == 0)); + ret = diag_process_apps_pkt(user_space_data, len, + current->tgid); + if (ret == 1) + diag_send_error_rsp((void *)(user_space_data), len, + current->tgid); + } +fail: + diagmem_free(driver, user_space_data, mempool); + user_space_data = NULL; + return ret; +} + +static int diag_user_process_userspace_data(const char __user *buf, int len) +{ + int err = 0; + int max_retries = 3; + int retry_count = 0; + int remote_proc = 0; + int token_offset = 0; + struct diag_md_session_t *session_info = NULL; + uint8_t hdlc_disabled; + + if (!buf || len <= 0 || len > USER_SPACE_DATA) { + pr_err_ratelimited("diag: In %s, invalid buf %pK len: %d\n", + __func__, buf, len); + return -EBADMSG; + } + + do { + if (!driver->user_space_data_busy) + break; + retry_count++; + usleep_range(10000, 10100); + } while (retry_count < max_retries); + + if (driver->user_space_data_busy) + return -EAGAIN; + + err = copy_from_user(driver->user_space_data_buf, buf, len); + if (err) { + pr_err("diag: In %s, failed to copy data from userspace, err: %d\n", + __func__, err); + return -EIO; + } + + /* Check for proc_type */ + remote_proc = diag_get_remote(*(int *)driver->user_space_data_buf); + if (remote_proc) { + if (len <= MIN_SIZ_ALLOW) { + pr_err("diag: Integer underflow in %s, payload size: %d", + __func__, len); + return -EBADMSG; + } + token_offset = sizeof(int); + len -= sizeof(int); + } + + /* Check masks for On-Device logging */ + if (driver->mask_check) { + if (!mask_request_validate(driver->user_space_data_buf + + token_offset)) { + pr_alert("diag: mask request Invalid\n"); + return -EFAULT; + } + } + + /* send masks to local processor now */ + if (!remote_proc) { + mutex_lock(&driver->md_session_lock); + session_info = diag_md_session_get_pid(current->tgid); + if (!session_info) { + pr_err("diag:In %s request came from invalid md session pid:%d", + __func__, current->tgid); + mutex_unlock(&driver->md_session_lock); + return -EINVAL; + } + if (session_info) + hdlc_disabled = session_info->hdlc_disabled; + else + hdlc_disabled = driver->hdlc_disabled; + mutex_unlock(&driver->md_session_lock); + if (!hdlc_disabled) + diag_process_hdlc_pkt((void *) + (driver->user_space_data_buf), + len, current->tgid); + else + diag_process_non_hdlc_pkt((char *) + (driver->user_space_data_buf), + len, current->tgid); + return 0; + } + + err = diag_process_userspace_remote(remote_proc, + driver->user_space_data_buf + + token_offset, len); + if (err) { + driver->user_space_data_busy = 0; + pr_err("diag: Error sending mask to remote proc %d, err: %d\n", + remote_proc, err); + } + + return err; +} + +static int diag_user_process_apps_data(const char __user *buf, int len, + int pkt_type) +{ + int ret = 0; + int stm_size = 0; + const int mempool = POOL_TYPE_COPY; + unsigned char *user_space_data = NULL; + struct diag_md_session_t *session_info = NULL; + uint8_t hdlc_disabled; + + if (!buf || len <= 0 || len > DIAG_MAX_RSP_SIZE) { + pr_err_ratelimited("diag: In %s, invalid buf %pK len: %d\n", + __func__, buf, len); + return -EBADMSG; + } + + switch (pkt_type) { + case DATA_TYPE_EVENT: + case DATA_TYPE_F3: + case DATA_TYPE_LOG: + case DATA_TYPE_RESPONSE: + case DATA_TYPE_DELAYED_RESPONSE: + break; + default: + pr_err_ratelimited("diag: In %s, invalid pkt_type: %d\n", + __func__, pkt_type); + return -EBADMSG; + } + + user_space_data = diagmem_alloc(driver, len, mempool); + if (!user_space_data) { + diag_record_stats(pkt_type, PKT_DROP); + return -ENOMEM; + } + + ret = copy_from_user(user_space_data, buf, len); + if (ret) { + pr_alert("diag: In %s, unable to copy data from userspace, err: %d\n", + __func__, ret); + diagmem_free(driver, user_space_data, mempool); + user_space_data = NULL; + diag_record_stats(pkt_type, PKT_DROP); + return -EBADMSG; + } + + if (driver->stm_state[APPS_DATA] && + (pkt_type >= DATA_TYPE_EVENT) && (pkt_type <= DATA_TYPE_LOG)) { + stm_size = stm_log_inv_ts(OST_ENTITY_DIAG, 0, user_space_data, + len); + if (stm_size == 0) { + pr_debug("diag: In %s, stm_log_inv_ts returned size of 0\n", + __func__); + } + diagmem_free(driver, user_space_data, mempool); + user_space_data = NULL; + + return 0; + } + + mutex_lock(&apps_data_mutex); + mutex_lock(&driver->hdlc_disable_mutex); + mutex_lock(&driver->md_session_lock); + session_info = diag_md_session_get_peripheral(APPS_DATA); + if (session_info) + hdlc_disabled = session_info->hdlc_disabled; + else + hdlc_disabled = driver->hdlc_disabled; + mutex_unlock(&driver->md_session_lock); + if (hdlc_disabled) + ret = diag_process_apps_data_non_hdlc(user_space_data, len, + pkt_type); + else + ret = diag_process_apps_data_hdlc(user_space_data, len, + pkt_type); + mutex_unlock(&driver->hdlc_disable_mutex); + mutex_unlock(&apps_data_mutex); + + diagmem_free(driver, user_space_data, mempool); + user_space_data = NULL; + + check_drain_timer(); + + if (ret == PKT_DROP) + diag_record_stats(pkt_type, PKT_DROP); + else if (ret == PKT_ALLOC) + diag_record_stats(pkt_type, PKT_ALLOC); + else + return ret; + + return 0; +} + +static ssize_t diagchar_read(struct file *file, char __user *buf, size_t count, + loff_t *ppos) +{ + struct diag_dci_client_tbl *entry; + struct list_head *start, *temp; + int index = -1, i = 0, ret = 0; + int data_type; + int copy_dci_data = 0; + int exit_stat = 0; + int write_len = 0; + struct diag_md_session_t *session_info = NULL; + + mutex_lock(&driver->diagchar_mutex); + for (i = 0; i < driver->num_clients; i++) + if (driver->client_map[i].pid == current->tgid) + index = i; + mutex_unlock(&driver->diagchar_mutex); + + if (index == -1) { + pr_err("diag: Client PID not found in table"); + return -EINVAL; + } + if (!buf) { + pr_err("diag: bad address from user side\n"); + return -EFAULT; + } + wait_event_interruptible(driver->wait_q, + atomic_read(&driver->data_ready_notif[index]) > 0); + + mutex_lock(&driver->diagchar_mutex); + + if ((driver->data_ready[index] & USER_SPACE_DATA_TYPE) && + (driver->logging_mode == DIAG_MEMORY_DEVICE_MODE || + driver->logging_mode == DIAG_MULTI_MODE)) { + pr_debug("diag: process woken up\n"); + /*Copy the type of data being passed*/ + data_type = driver->data_ready[index] & USER_SPACE_DATA_TYPE; + driver->data_ready[index] ^= USER_SPACE_DATA_TYPE; + atomic_dec(&driver->data_ready_notif[index]); + COPY_USER_SPACE_OR_EXIT(buf, data_type, sizeof(int)); + /* place holder for number of data field */ + ret += sizeof(int); + mutex_lock(&driver->md_session_lock); + session_info = diag_md_session_get_pid(current->tgid); + exit_stat = diag_md_copy_to_user(buf, &ret, count, + session_info); + mutex_unlock(&driver->md_session_lock); + goto exit; + } else if (driver->data_ready[index] & USER_SPACE_DATA_TYPE) { + /* In case, the thread wakes up and the logging mode is + not memory device any more, the condition needs to be cleared */ + driver->data_ready[index] ^= USER_SPACE_DATA_TYPE; + atomic_dec(&driver->data_ready_notif[index]); + } + + if (driver->data_ready[index] & HDLC_SUPPORT_TYPE) { + data_type = driver->data_ready[index] & HDLC_SUPPORT_TYPE; + driver->data_ready[index] ^= HDLC_SUPPORT_TYPE; + atomic_dec(&driver->data_ready_notif[index]); + COPY_USER_SPACE_OR_EXIT(buf, data_type, sizeof(int)); + mutex_lock(&driver->md_session_lock); + session_info = diag_md_session_get_pid(current->tgid); + if (session_info) { + COPY_USER_SPACE_OR_ERR(buf+4, + session_info->hdlc_disabled, + sizeof(uint8_t)); + if (ret == -EFAULT) { + mutex_unlock(&driver->md_session_lock); + goto exit; + } + } + mutex_unlock(&driver->md_session_lock); + goto exit; + } + + if (driver->data_ready[index] & DEINIT_TYPE) { + /*Copy the type of data being passed*/ + data_type = driver->data_ready[index] & DEINIT_TYPE; + COPY_USER_SPACE_OR_EXIT(buf, data_type, 4); + driver->data_ready[index] ^= DEINIT_TYPE; + atomic_dec(&driver->data_ready_notif[index]); + mutex_unlock(&driver->diagchar_mutex); + diag_remove_client_entry(file); + return ret; + } + + if (driver->data_ready[index] & MSG_MASKS_TYPE) { + /*Copy the type of data being passed*/ + data_type = driver->data_ready[index] & MSG_MASKS_TYPE; + mutex_lock(&driver->md_session_lock); + session_info = diag_md_session_get_peripheral(APPS_DATA); + COPY_USER_SPACE_OR_ERR(buf, data_type, sizeof(int)); + if (ret == -EFAULT) { + mutex_unlock(&driver->md_session_lock); + goto exit; + } + write_len = diag_copy_to_user_msg_mask(buf + ret, count, + session_info); + mutex_unlock(&driver->md_session_lock); + if (write_len > 0) + ret += write_len; + driver->data_ready[index] ^= MSG_MASKS_TYPE; + atomic_dec(&driver->data_ready_notif[index]); + goto exit; + } + + if (driver->data_ready[index] & EVENT_MASKS_TYPE) { + /*Copy the type of data being passed*/ + data_type = driver->data_ready[index] & EVENT_MASKS_TYPE; + mutex_lock(&driver->md_session_lock); + session_info = diag_md_session_get_peripheral(APPS_DATA); + COPY_USER_SPACE_OR_ERR(buf, data_type, 4); + if (ret == -EFAULT) { + mutex_unlock(&driver->md_session_lock); + goto exit; + } + if (session_info && session_info->event_mask && + session_info->event_mask->ptr) { + COPY_USER_SPACE_OR_ERR(buf + sizeof(int), + *(session_info->event_mask->ptr), + session_info->event_mask->mask_len); + if (ret == -EFAULT) { + mutex_unlock(&driver->md_session_lock); + goto exit; + } + } else { + COPY_USER_SPACE_OR_ERR(buf + sizeof(int), + *(event_mask.ptr), + event_mask.mask_len); + if (ret == -EFAULT) { + mutex_unlock(&driver->md_session_lock); + goto exit; + } + } + mutex_unlock(&driver->md_session_lock); + driver->data_ready[index] ^= EVENT_MASKS_TYPE; + atomic_dec(&driver->data_ready_notif[index]); + goto exit; + } + + if (driver->data_ready[index] & LOG_MASKS_TYPE) { + /*Copy the type of data being passed*/ + data_type = driver->data_ready[index] & LOG_MASKS_TYPE; + mutex_lock(&driver->md_session_lock); + session_info = diag_md_session_get_peripheral(APPS_DATA); + COPY_USER_SPACE_OR_ERR(buf, data_type, sizeof(int)); + if (ret == -EFAULT) { + mutex_unlock(&driver->md_session_lock); + goto exit; + } + write_len = diag_copy_to_user_log_mask(buf + ret, count, + session_info); + mutex_unlock(&driver->md_session_lock); + if (write_len > 0) + ret += write_len; + driver->data_ready[index] ^= LOG_MASKS_TYPE; + atomic_dec(&driver->data_ready_notif[index]); + goto exit; + } + + if (driver->data_ready[index] & PKT_TYPE) { + /*Copy the type of data being passed*/ + data_type = driver->data_ready[index] & PKT_TYPE; + COPY_USER_SPACE_OR_EXIT(buf, data_type, sizeof(data_type)); + COPY_USER_SPACE_OR_EXIT(buf + sizeof(data_type), + *(driver->apps_req_buf), + driver->apps_req_buf_len); + driver->data_ready[index] ^= PKT_TYPE; + atomic_dec(&driver->data_ready_notif[index]); + driver->in_busy_pktdata = 0; + goto exit; + } + + if (driver->data_ready[index] & DCI_PKT_TYPE) { + /* Copy the type of data being passed */ + data_type = driver->data_ready[index] & DCI_PKT_TYPE; + COPY_USER_SPACE_OR_EXIT(buf, data_type, 4); + COPY_USER_SPACE_OR_EXIT(buf+4, *(driver->dci_pkt_buf), + driver->dci_pkt_length); + driver->data_ready[index] ^= DCI_PKT_TYPE; + atomic_dec(&driver->data_ready_notif[index]); + driver->in_busy_dcipktdata = 0; + goto exit; + } + + if (driver->data_ready[index] & DCI_EVENT_MASKS_TYPE) { + /*Copy the type of data being passed*/ + data_type = driver->data_ready[index] & DCI_EVENT_MASKS_TYPE; + COPY_USER_SPACE_OR_EXIT(buf, data_type, 4); + COPY_USER_SPACE_OR_EXIT(buf+4, driver->num_dci_client, 4); + COPY_USER_SPACE_OR_EXIT(buf + 8, (dci_ops_tbl[DCI_LOCAL_PROC]. + event_mask_composite), DCI_EVENT_MASK_SIZE); + driver->data_ready[index] ^= DCI_EVENT_MASKS_TYPE; + atomic_dec(&driver->data_ready_notif[index]); + goto exit; + } + + if (driver->data_ready[index] & DCI_LOG_MASKS_TYPE) { + /*Copy the type of data being passed*/ + data_type = driver->data_ready[index] & DCI_LOG_MASKS_TYPE; + COPY_USER_SPACE_OR_EXIT(buf, data_type, 4); + COPY_USER_SPACE_OR_EXIT(buf+4, driver->num_dci_client, 4); + COPY_USER_SPACE_OR_EXIT(buf+8, (dci_ops_tbl[DCI_LOCAL_PROC]. + log_mask_composite), DCI_LOG_MASK_SIZE); + driver->data_ready[index] ^= DCI_LOG_MASKS_TYPE; + atomic_dec(&driver->data_ready_notif[index]); + goto exit; + } + +exit: + if (driver->data_ready[index] & DCI_DATA_TYPE) { + data_type = driver->data_ready[index] & DCI_DATA_TYPE; + mutex_unlock(&driver->diagchar_mutex); + /* Copy the type of data being passed */ + mutex_lock(&driver->dci_mutex); + list_for_each_safe(start, temp, &driver->dci_client_list) { + entry = list_entry(start, struct diag_dci_client_tbl, + track); + if (entry->client->tgid != current->tgid) + continue; + if (!entry->in_service) + continue; + if (copy_to_user(buf + ret, &data_type, sizeof(int))) { + mutex_unlock(&driver->dci_mutex); + goto end; + } + ret += sizeof(int); + if (copy_to_user(buf + ret, &entry->client_info.token, + sizeof(int))) { + mutex_unlock(&driver->dci_mutex); + goto end; + } + ret += sizeof(int); + copy_dci_data = 1; + exit_stat = diag_copy_dci(buf, count, entry, &ret); + mutex_lock(&driver->diagchar_mutex); + driver->data_ready[index] ^= DCI_DATA_TYPE; + atomic_dec(&driver->data_ready_notif[index]); + mutex_unlock(&driver->diagchar_mutex); + if (exit_stat == 1) { + mutex_unlock(&driver->dci_mutex); + goto end; + } + } + mutex_unlock(&driver->dci_mutex); + goto end; + } + mutex_unlock(&driver->diagchar_mutex); +end: + /* + * Flush any read that is currently pending on DCI data and + * command channnels. This will ensure that the next read is not + * missed. + */ + if (copy_dci_data) { + diag_ws_on_copy_complete(DIAG_WS_DCI); + flush_workqueue(driver->diag_dci_wq); + } + return ret; +} + +static ssize_t diagchar_write(struct file *file, const char __user *buf, + size_t count, loff_t *ppos) +{ + int err = 0; + int pkt_type = 0; + int payload_len = 0; + const char __user *payload_buf = NULL; + + /* + * The data coming from the user sapce should at least have the + * packet type heeader. + */ + if (count < sizeof(int)) { + pr_err("diag: In %s, client is sending short data, len: %d\n", + __func__, (int)count); + return -EBADMSG; + } + + err = copy_from_user((&pkt_type), buf, sizeof(int)); + if (err) { + pr_err_ratelimited("diag: In %s, unable to copy pkt_type from userspace, err: %d\n", + __func__, err); + return -EIO; + } + +#ifdef CONFIG_DIAG_OVER_USB + if (driver->logging_mode == DIAG_USB_MODE && !driver->usb_connected) { + if (!((pkt_type == DCI_DATA_TYPE) || + (pkt_type == DCI_PKT_TYPE) || + (pkt_type & DATA_TYPE_DCI_LOG) || + (pkt_type & DATA_TYPE_DCI_EVENT))) { + pr_debug("diag: In %s, Dropping non DCI packet type\n", + __func__); + return -EIO; + } + } +#endif + + payload_buf = buf + sizeof(int); + payload_len = count - sizeof(int); + + if (pkt_type == DCI_PKT_TYPE) + return diag_user_process_dci_apps_data(payload_buf, + payload_len, + pkt_type); + else if (pkt_type == DCI_DATA_TYPE) + return diag_user_process_dci_data(payload_buf, payload_len); + else if (pkt_type == USER_SPACE_RAW_DATA_TYPE) + return diag_user_process_raw_data(payload_buf, + payload_len); + else if (pkt_type == USER_SPACE_DATA_TYPE) + return diag_user_process_userspace_data(payload_buf, + payload_len); + if (pkt_type & (DATA_TYPE_DCI_LOG | DATA_TYPE_DCI_EVENT)) { + err = diag_user_process_dci_apps_data(payload_buf, payload_len, + pkt_type); + if (pkt_type & DATA_TYPE_DCI_LOG) + pkt_type ^= DATA_TYPE_DCI_LOG; + if (pkt_type & DATA_TYPE_DCI_EVENT) + pkt_type ^= DATA_TYPE_DCI_EVENT; +#ifdef CONFIG_DIAG_OVER_USB + /* + * Check if the log or event is selected even on the regular + * stream. If USB is not connected and we are not in memory + * device mode, we should not process these logs/events. + */ + if (pkt_type && driver->logging_mode == DIAG_USB_MODE && + !driver->usb_connected) + return err; +#endif + } + + switch (pkt_type) { + case DATA_TYPE_EVENT: + case DATA_TYPE_F3: + case DATA_TYPE_LOG: + case DATA_TYPE_DELAYED_RESPONSE: + case DATA_TYPE_RESPONSE: + return diag_user_process_apps_data(payload_buf, payload_len, + pkt_type); + default: + pr_err_ratelimited("diag: In %s, invalid pkt_type: %d\n", + __func__, pkt_type); + return -EINVAL; + } + + return err; +} + +void diag_ws_init() +{ + driver->dci_ws.ref_count = 0; + driver->dci_ws.copy_count = 0; + spin_lock_init(&driver->dci_ws.lock); + + driver->md_ws.ref_count = 0; + driver->md_ws.copy_count = 0; + spin_lock_init(&driver->md_ws.lock); +} + +static void diag_stats_init(void) +{ + if (!driver) + return; + + driver->msg_stats.alloc_count = 0; + driver->msg_stats.drop_count = 0; + + driver->log_stats.alloc_count = 0; + driver->log_stats.drop_count = 0; + + driver->event_stats.alloc_count = 0; + driver->event_stats.drop_count = 0; +} + +void diag_ws_on_notify() +{ + /* + * Do not deal with reference count here as there can be spurious + * interrupts. + */ + pm_stay_awake(driver->diag_dev); +} + +void diag_ws_on_read(int type, int pkt_len) +{ + unsigned long flags; + struct diag_ws_ref_t *ws_ref = NULL; + + switch (type) { + case DIAG_WS_DCI: + ws_ref = &driver->dci_ws; + break; + case DIAG_WS_MUX: + ws_ref = &driver->md_ws; + break; + default: + pr_err_ratelimited("diag: In %s, invalid type: %d\n", + __func__, type); + return; + } + + spin_lock_irqsave(&ws_ref->lock, flags); + if (pkt_len > 0) { + ws_ref->ref_count++; + } else { + if (ws_ref->ref_count < 1) { + ws_ref->ref_count = 0; + ws_ref->copy_count = 0; + } + diag_ws_release(); + } + spin_unlock_irqrestore(&ws_ref->lock, flags); +} + + +void diag_ws_on_copy(int type) +{ + unsigned long flags; + struct diag_ws_ref_t *ws_ref = NULL; + + switch (type) { + case DIAG_WS_DCI: + ws_ref = &driver->dci_ws; + break; + case DIAG_WS_MUX: + ws_ref = &driver->md_ws; + break; + default: + pr_err_ratelimited("diag: In %s, invalid type: %d\n", + __func__, type); + return; + } + + spin_lock_irqsave(&ws_ref->lock, flags); + ws_ref->copy_count++; + spin_unlock_irqrestore(&ws_ref->lock, flags); +} + +void diag_ws_on_copy_fail(int type) +{ + unsigned long flags; + struct diag_ws_ref_t *ws_ref = NULL; + + switch (type) { + case DIAG_WS_DCI: + ws_ref = &driver->dci_ws; + break; + case DIAG_WS_MUX: + ws_ref = &driver->md_ws; + break; + default: + pr_err_ratelimited("diag: In %s, invalid type: %d\n", + __func__, type); + return; + } + + spin_lock_irqsave(&ws_ref->lock, flags); + ws_ref->ref_count--; + spin_unlock_irqrestore(&ws_ref->lock, flags); + + diag_ws_release(); +} + +void diag_ws_on_copy_complete(int type) +{ + unsigned long flags; + struct diag_ws_ref_t *ws_ref = NULL; + + switch (type) { + case DIAG_WS_DCI: + ws_ref = &driver->dci_ws; + break; + case DIAG_WS_MUX: + ws_ref = &driver->md_ws; + break; + default: + pr_err_ratelimited("diag: In %s, invalid type: %d\n", + __func__, type); + return; + } + + spin_lock_irqsave(&ws_ref->lock, flags); + ws_ref->ref_count -= ws_ref->copy_count; + if (ws_ref->ref_count < 1) + ws_ref->ref_count = 0; + ws_ref->copy_count = 0; + spin_unlock_irqrestore(&ws_ref->lock, flags); + + diag_ws_release(); +} + +void diag_ws_reset(int type) +{ + unsigned long flags; + struct diag_ws_ref_t *ws_ref = NULL; + + switch (type) { + case DIAG_WS_DCI: + ws_ref = &driver->dci_ws; + break; + case DIAG_WS_MUX: + ws_ref = &driver->md_ws; + break; + default: + pr_err_ratelimited("diag: In %s, invalid type: %d\n", + __func__, type); + return; + } + + spin_lock_irqsave(&ws_ref->lock, flags); + ws_ref->ref_count = 0; + ws_ref->copy_count = 0; + spin_unlock_irqrestore(&ws_ref->lock, flags); + + diag_ws_release(); +} + +void diag_ws_release() +{ + if (driver->dci_ws.ref_count == 0 && driver->md_ws.ref_count == 0) + pm_relax(driver->diag_dev); +} + +#ifdef DIAG_DEBUG +static void diag_debug_init(void) +{ + diag_ipc_log = ipc_log_context_create(DIAG_IPC_LOG_PAGES, "diag", 0); + if (!diag_ipc_log) + pr_err("diag: Failed to create IPC logging context\n"); + /* + * Set the bit mask here as per diag_ipc_logging.h to enable debug logs + * to be logged to IPC + */ + diag_debug_mask = DIAG_DEBUG_PERIPHERALS | DIAG_DEBUG_DCI | + DIAG_DEBUG_USERSPACE | DIAG_DEBUG_BRIDGE; +} +#else +static void diag_debug_init(void) +{ + +} +#endif + +static int diag_real_time_info_init(void) +{ + int i; + if (!driver) + return -EIO; + for (i = 0; i < DIAG_NUM_PROC; i++) { + driver->real_time_mode[i] = 1; + driver->proc_rt_vote_mask[i] |= DIAG_PROC_DCI; + driver->proc_rt_vote_mask[i] |= DIAG_PROC_MEMORY_DEVICE; + } + driver->real_time_update_busy = 0; + driver->proc_active_mask = 0; + driver->diag_real_time_wq = create_singlethread_workqueue( + "diag_real_time_wq"); + if (!driver->diag_real_time_wq) + return -ENOMEM; + INIT_WORK(&(driver->diag_real_time_work), diag_real_time_work_fn); + mutex_init(&driver->real_time_mutex); + return 0; +} + +static const struct file_operations diagcharfops = { + .owner = THIS_MODULE, + .read = diagchar_read, + .write = diagchar_write, +#ifdef CONFIG_COMPAT + .compat_ioctl = diagchar_compat_ioctl, +#endif + .unlocked_ioctl = diagchar_ioctl, + .open = diagchar_open, + .release = diagchar_close +}; + +static int diagchar_setup_cdev(dev_t devno) +{ + + int err; + + cdev_init(driver->cdev, &diagcharfops); + + driver->cdev->owner = THIS_MODULE; + driver->cdev->ops = &diagcharfops; + + err = cdev_add(driver->cdev, devno, 1); + + if (err) { + printk(KERN_INFO "diagchar cdev registration failed !\n\n"); + return -1; + } + + driver->diagchar_class = class_create(THIS_MODULE, "diag"); + + if (IS_ERR(driver->diagchar_class)) { + printk(KERN_ERR "Error creating diagchar class.\n"); + return -1; + } + + driver->diag_dev = device_create(driver->diagchar_class, NULL, devno, + (void *)driver, "diag"); + + if (!driver->diag_dev) + return -EIO; + + driver->diag_dev->power.wakeup = wakeup_source_register("DIAG_WS"); + return 0; + +} + +static int diagchar_cleanup(void) +{ + if (driver) { + if (driver->cdev) { + /* TODO - Check if device exists before deleting */ + device_destroy(driver->diagchar_class, + MKDEV(driver->major, + driver->minor_start)); + cdev_del(driver->cdev); + } + if (!IS_ERR(driver->diagchar_class)) + class_destroy(driver->diagchar_class); + kfree(driver); + } + return 0; +} + +static int diag_mhi_probe(struct platform_device *pdev) +{ + int ret; + + if (!mhi_is_device_ready(&pdev->dev, "qcom,mhi")) + return -EPROBE_DEFER; + driver->pdev = pdev; + ret = diag_remote_init(); + if (ret) { + diag_remote_exit(); + return ret; + } + ret = diagfwd_bridge_init(); + if (ret) { + diagfwd_bridge_exit(); + return ret; + } + pr_debug("diag: mhi device is ready\n"); + return 0; +} + +static const struct of_device_id diag_mhi_table[] = { + {.compatible = "qcom,diag-mhi"}, + {}, +}; + +static struct platform_driver diag_mhi_driver = { + .probe = diag_mhi_probe, + .driver = { + .name = "DIAG MHI Platform", + .owner = THIS_MODULE, + .of_match_table = diag_mhi_table, + }, +}; + +static int __init diagchar_init(void) +{ + dev_t dev; + int error, ret, i; + + pr_debug("diagfwd initializing ..\n"); + ret = 0; + driver = kzalloc(sizeof(struct diagchar_dev) + 5, GFP_KERNEL); + if (!driver) + return -ENOMEM; + kmemleak_not_leak(driver); + + timer_in_progress = 0; + driver->delayed_rsp_id = 0; + driver->hdlc_disabled = 0; + driver->dci_state = DIAG_DCI_NO_ERROR; + setup_timer(&drain_timer, drain_timer_func, 1234); + driver->supports_sockets = 1; + driver->time_sync_enabled = 0; + driver->uses_time_api = 0; + driver->poolsize = poolsize; + driver->poolsize_hdlc = poolsize_hdlc; + driver->poolsize_dci = poolsize_dci; + driver->poolsize_user = poolsize_user; + /* + * POOL_TYPE_MUX_APPS is for the buffers in the Diag MUX layer. + * The number of buffers encompasses Diag data generated on + * the Apss processor + 1 for the responses generated exclusively on + * the Apps processor + data from data channels (4 channels per + * peripheral) + data from command channels (2) + */ + diagmem_setsize(POOL_TYPE_MUX_APPS, itemsize_usb_apps, + poolsize_usb_apps + 1 + (NUM_PERIPHERALS * 6)); + driver->num_clients = max_clients; + driver->logging_mode = DIAG_USB_MODE; + for (i = 0; i < NUM_UPD; i++) { + driver->pd_logging_mode[i] = 0; + driver->pd_session_clear[i] = 0; + } + driver->num_pd_session = 0; + driver->mask_check = 0; + driver->in_busy_pktdata = 0; + driver->in_busy_dcipktdata = 0; + driver->rsp_buf_ctxt = SET_BUF_CTXT(APPS_DATA, TYPE_CMD, 1); + hdlc_data.ctxt = SET_BUF_CTXT(APPS_DATA, TYPE_DATA, 1); + hdlc_data.len = 0; + non_hdlc_data.ctxt = SET_BUF_CTXT(APPS_DATA, TYPE_DATA, 1); + non_hdlc_data.len = 0; + mutex_init(&driver->hdlc_disable_mutex); + mutex_init(&driver->diagchar_mutex); + mutex_init(&driver->diag_maskclear_mutex); + mutex_init(&driver->diag_notifier_mutex); + mutex_init(&driver->diag_file_mutex); + mutex_init(&driver->delayed_rsp_mutex); + mutex_init(&apps_data_mutex); + mutex_init(&driver->msg_mask_lock); + mutex_init(&driver->hdlc_recovery_mutex); + for (i = 0; i < NUM_PERIPHERALS; i++) + mutex_init(&driver->diagfwd_channel_mutex[i]); + init_waitqueue_head(&driver->wait_q); + INIT_WORK(&(driver->diag_drain_work), diag_drain_work_fn); + INIT_WORK(&(driver->update_user_clients), + diag_update_user_client_work_fn); + INIT_WORK(&(driver->update_md_clients), + diag_update_md_client_work_fn); + diag_ws_init(); + diag_stats_init(); + diag_debug_init(); + diag_md_session_init(); + + driver->incoming_pkt.capacity = DIAG_MAX_REQ_SIZE; + driver->incoming_pkt.data = kzalloc(DIAG_MAX_REQ_SIZE, GFP_KERNEL); + if (!driver->incoming_pkt.data) + goto fail; + kmemleak_not_leak(driver->incoming_pkt.data); + driver->incoming_pkt.processing = 0; + driver->incoming_pkt.read_len = 0; + driver->incoming_pkt.remaining = 0; + driver->incoming_pkt.total_len = 0; + + ret = diag_real_time_info_init(); + if (ret) + goto fail; + ret = diag_debugfs_init(); + if (ret) + goto fail; + ret = diag_masks_init(); + if (ret) + goto fail; + ret = diag_mux_init(); + if (ret) + goto fail; + ret = diagfwd_init(); + if (ret) + goto fail; + ret = diagfwd_cntl_init(); + if (ret) + goto fail; + driver->dci_state = diag_dci_init(); + ret = diagfwd_peripheral_init(); + if (ret) + goto fail; + diagfwd_cntl_channel_init(); + if (driver->dci_state == DIAG_DCI_NO_ERROR) + diag_dci_channel_init(); + pr_debug("diagchar initializing ..\n"); + driver->num = 1; + driver->name = ((void *)driver) + sizeof(struct diagchar_dev); + strlcpy(driver->name, "diag", 4); + /* Get major number from kernel and initialize */ + error = alloc_chrdev_region(&dev, driver->minor_start, + driver->num, driver->name); + if (!error) { + driver->major = MAJOR(dev); + driver->minor_start = MINOR(dev); + } else { + pr_err("diag: Major number not allocated\n"); + goto fail; + } + driver->cdev = cdev_alloc(); + error = diagchar_setup_cdev(dev); + if (error) + goto fail; + + pr_debug("diagchar initialized now"); + platform_driver_register(&diag_mhi_driver); + return 0; + +fail: + pr_err("diagchar is not initialized, ret: %d\n", ret); + diag_debugfs_cleanup(); + diagchar_cleanup(); + diag_mux_exit(); + diagfwd_peripheral_exit(); + diagfwd_bridge_exit(); + diagfwd_exit(); + diagfwd_cntl_exit(); + diag_dci_exit(); + diag_masks_exit(); + return -1; +} + +static void diagchar_exit(void) +{ + printk(KERN_INFO "diagchar exiting ..\n"); + diag_mempool_exit(); + diag_mux_exit(); + diagfwd_peripheral_exit(); + diagfwd_exit(); + diagfwd_cntl_exit(); + diag_dci_exit(); + diag_masks_exit(); + diag_md_session_exit(); + diag_remote_exit(); + diag_debugfs_cleanup(); + diagchar_cleanup(); + printk(KERN_INFO "done diagchar exit\n"); +} + +module_init(diagchar_init); +module_exit(diagchar_exit); diff -Nruw linux-4.4.115-fbx/drivers/char/diag./diagchar.h linux-4.4.115-fbx/drivers/char/diag/diagchar.h --- linux-4.4.115-fbx/drivers/char/diag./diagchar.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-4.4.115-fbx/drivers/char/diag/diagchar.h 2019-10-29 09:26:23.449201280 +0100 @@ -0,0 +1,688 @@ +/* Copyright (c) 2008-2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef DIAGCHAR_H +#define DIAGCHAR_H + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "diagfwd_bridge.h" + +#define THRESHOLD_CLIENT_LIMIT 50 + +/* Size of the USB buffers used for read and write*/ +#define USB_MAX_OUT_BUF 4096 +#define APPS_BUF_SIZE 4096 +#define IN_BUF_SIZE 16384 +#define MAX_SYNC_OBJ_NAME_SIZE 32 + +#define DIAG_MAX_REQ_SIZE (16 * 1024) +#define DIAG_MAX_RSP_SIZE (16 * 1024) +#define APF_DIAG_PADDING 0 +/* + * In the worst case, the HDLC buffer can be atmost twice the size of the + * original packet. Add 3 bytes for 16 bit CRC (2 bytes) and a delimiter + * (1 byte) + */ +#define DIAG_MAX_HDLC_BUF_SIZE ((DIAG_MAX_REQ_SIZE * 2) + 3) + +/* The header of callback data type has remote processor token (of type int) */ +#define CALLBACK_HDR_SIZE (sizeof(int)) +#define CALLBACK_BUF_SIZE (DIAG_MAX_REQ_SIZE + CALLBACK_HDR_SIZE) + +#define MAX_SSID_PER_RANGE 200 + +#define ALL_PROC -1 + +#define REMOTE_DATA 4 + +#define USER_SPACE_DATA 16384 + +#define DIAG_CTRL_MSG_LOG_MASK 9 +#define DIAG_CTRL_MSG_EVENT_MASK 10 +#define DIAG_CTRL_MSG_F3_MASK 11 +#define CONTROL_CHAR 0x7E + +#define DIAG_CON_APSS (0x0001) /* Bit mask for APSS */ +#define DIAG_CON_MPSS (0x0002) /* Bit mask for MPSS */ +#define DIAG_CON_LPASS (0x0004) /* Bit mask for LPASS */ +#define DIAG_CON_WCNSS (0x0008) /* Bit mask for WCNSS */ +#define DIAG_CON_SENSORS (0x0010) /* Bit mask for Sensors */ +#define DIAG_CON_WDSP (0x0020) /* Bit mask for WDSP */ +#define DIAG_CON_CDSP (0x0040) /* Bit mask for CDSP */ + +#define DIAG_CON_UPD_WLAN (0x1000) /*Bit mask for WLAN PD*/ +#define DIAG_CON_UPD_AUDIO (0x2000) /*Bit mask for AUDIO PD*/ +#define DIAG_CON_UPD_SENSORS (0x4000) /*Bit mask for SENSORS PD*/ + +#define DIAG_CON_NONE (0x0000) /* Bit mask for No SS*/ +#define DIAG_CON_ALL (DIAG_CON_APSS | DIAG_CON_MPSS \ + | DIAG_CON_LPASS | DIAG_CON_WCNSS \ + | DIAG_CON_SENSORS | DIAG_CON_WDSP \ + | DIAG_CON_CDSP) +#define DIAG_CON_UPD_ALL (DIAG_CON_UPD_WLAN \ + | DIAG_CON_UPD_AUDIO \ + | DIAG_CON_UPD_SENSORS) + +#define DIAG_STM_MODEM 0x01 +#define DIAG_STM_LPASS 0x02 +#define DIAG_STM_WCNSS 0x04 +#define DIAG_STM_APPS 0x08 +#define DIAG_STM_SENSORS 0x10 +#define DIAG_STM_WDSP 0x20 +#define DIAG_STM_CDSP 0x40 + +#define INVALID_PID -1 +#define DIAG_CMD_FOUND 1 +#define DIAG_CMD_NOT_FOUND 0 +#define DIAG_CMD_POLLING 1 +#define DIAG_CMD_NOT_POLLING 0 +#define DIAG_CMD_ADD 1 +#define DIAG_CMD_REMOVE 0 + +#define DIAG_CMD_VERSION 0 +#define DIAG_CMD_ERROR 0x13 +#define DIAG_CMD_DOWNLOAD 0x3A +#define DIAG_CMD_DIAG_SUBSYS 0x4B +#define DIAG_CMD_LOG_CONFIG 0x73 +#define DIAG_CMD_LOG_ON_DMND 0x78 +#define DIAG_CMD_EXT_BUILD 0x7c +#define DIAG_CMD_MSG_CONFIG 0x7D +#define DIAG_CMD_GET_EVENT_MASK 0x81 +#define DIAG_CMD_SET_EVENT_MASK 0x82 +#define DIAG_CMD_EVENT_TOGGLE 0x60 +#define DIAG_CMD_NO_SUBSYS 0xFF +#define DIAG_CMD_STATUS 0x0C +#define DIAG_SS_WCDMA 0x04 +#define DIAG_CMD_QUERY_CALL 0x0E +#define DIAG_SS_GSM 0x08 +#define DIAG_CMD_QUERY_TMC 0x02 +#define DIAG_SS_TDSCDMA 0x57 +#define DIAG_CMD_TDSCDMA_STATUS 0x0E +#define DIAG_CMD_DIAG_SUBSYS_DELAY 0x80 + +#define DIAG_SS_DIAG 0x12 +#define DIAG_SS_PARAMS 0x32 +#define DIAG_SS_FILE_READ_MODEM 0x0816 +#define DIAG_SS_FILE_READ_ADSP 0x0E10 +#define DIAG_SS_FILE_READ_WCNSS 0x141F +#define DIAG_SS_FILE_READ_SLPI 0x01A18 +#define DIAG_SS_FILE_READ_APPS 0x020F + +#define DIAG_DIAG_MAX_PKT_SZ 0x55 +#define DIAG_DIAG_STM 0x214 +#define DIAG_DIAG_POLL 0x03 +#define DIAG_DEL_RSP_WRAP 0x04 +#define DIAG_DEL_RSP_WRAP_CNT 0x05 +#define DIAG_EXT_MOBILE_ID 0x06 +#define DIAG_GET_TIME_API 0x21B +#define DIAG_SET_TIME_API 0x21C +#define DIAG_SWITCH_COMMAND 0x081B +#define DIAG_BUFFERING_MODE 0x080C + +#define DIAG_CMD_OP_LOG_DISABLE 0 +#define DIAG_CMD_OP_GET_LOG_RANGE 1 +#define DIAG_CMD_OP_SET_LOG_MASK 3 +#define DIAG_CMD_OP_GET_LOG_MASK 4 + +#define DIAG_CMD_OP_GET_SSID_RANGE 1 +#define DIAG_CMD_OP_GET_BUILD_MASK 2 +#define DIAG_CMD_OP_GET_MSG_MASK 3 +#define DIAG_CMD_OP_SET_MSG_MASK 4 +#define DIAG_CMD_OP_SET_ALL_MSG_MASK 5 + +#define DIAG_CMD_OP_GET_MSG_ALLOC 0x33 +#define DIAG_CMD_OP_GET_MSG_DROP 0x30 +#define DIAG_CMD_OP_RESET_MSG_STATS 0x2F +#define DIAG_CMD_OP_GET_LOG_ALLOC 0x31 +#define DIAG_CMD_OP_GET_LOG_DROP 0x2C +#define DIAG_CMD_OP_RESET_LOG_STATS 0x2B +#define DIAG_CMD_OP_GET_EVENT_ALLOC 0x32 +#define DIAG_CMD_OP_GET_EVENT_DROP 0x2E +#define DIAG_CMD_OP_RESET_EVENT_STATS 0x2D + +#define DIAG_CMD_OP_HDLC_DISABLE 0x218 + +#define BAD_PARAM_RESPONSE_MESSAGE 20 + +#define PERSIST_TIME_SUCCESS 0 +#define PERSIST_TIME_FAILURE 1 +#define PERSIST_TIME_NOT_SUPPORTED 2 + +#define MODE_CMD 41 +#define RESET_ID 2 + +#define PKT_DROP 0 +#define PKT_ALLOC 1 +#define PKT_RESET 2 + +#define FEATURE_MASK_LEN 4 + +#define DIAG_MD_NONE 0 +#define DIAG_MD_PERIPHERAL 1 + +/* + * The status bit masks when received in a signal handler are to be + * used in conjunction with the peripheral list bit mask to determine the + * status for a peripheral. For instance, 0x00010002 would denote an open + * status on the MPSS + */ +#define DIAG_STATUS_OPEN (0x00010000) /* DCI channel open status mask */ +#define DIAG_STATUS_CLOSED (0x00020000) /* DCI channel closed status mask */ + +#define MODE_NONREALTIME 0 +#define MODE_REALTIME 1 +#define MODE_UNKNOWN 2 + +#define DIAG_BUFFERING_MODE_STREAMING 0 +#define DIAG_BUFFERING_MODE_THRESHOLD 1 +#define DIAG_BUFFERING_MODE_CIRCULAR 2 + +#define DIAG_MIN_WM_VAL 0 +#define DIAG_MAX_WM_VAL 100 + +#define DEFAULT_LOW_WM_VAL 15 +#define DEFAULT_HIGH_WM_VAL 85 + +#define TYPE_DATA 0 +#define TYPE_CNTL 1 +#define TYPE_DCI 2 +#define TYPE_CMD 3 +#define TYPE_DCI_CMD 4 +#define NUM_TYPES 5 + +#define PERIPHERAL_MODEM 0 +#define PERIPHERAL_LPASS 1 +#define PERIPHERAL_WCNSS 2 +#define PERIPHERAL_SENSORS 3 +#define PERIPHERAL_WDSP 4 +#define PERIPHERAL_CDSP 5 +#define NUM_PERIPHERALS 6 +#define APPS_DATA (NUM_PERIPHERALS) + +#define UPD_WLAN 7 +#define UPD_AUDIO 8 +#define UPD_SENSORS 9 +#define NUM_UPD 3 + +#define DIAG_ID_APPS 1 +#define DIAG_ID_MPSS 2 +#define DIAG_ID_WLAN 3 +#define DIAG_ID_LPASS 4 +#define DIAG_ID_CDSP 5 +#define DIAG_ID_AUDIO 6 +#define DIAG_ID_SENSORS 7 + +/* Number of sessions possible in Memory Device Mode. +1 for Apps data */ +#define NUM_MD_SESSIONS (NUM_PERIPHERALS \ + + NUM_UPD + 1) + +#define MD_PERIPHERAL_MASK(x) (1 << x) + +#define MD_PERIPHERAL_PD_MASK(x) \ + ((x == PERIPHERAL_MODEM) ? (1 << UPD_WLAN) : \ + ((x == PERIPHERAL_LPASS) ? (1 << UPD_AUDIO | 1 << UPD_SENSORS) : 0))\ + +/* + * Number of stm processors includes all the peripherals and + * apps.Added 1 below to indicate apps + */ +#define NUM_STM_PROCESSORS (NUM_PERIPHERALS + 1) +/* + * Indicates number of peripherals that can support DCI and Apps + * processor. This doesn't mean that a peripheral has the + * feature. + */ +#define NUM_DCI_PERIPHERALS (NUM_PERIPHERALS + 1) + +#define DIAG_PROC_DCI 1 +#define DIAG_PROC_MEMORY_DEVICE 2 + +/* Flags to vote the DCI or Memory device process up or down + when it becomes active or inactive */ +#define VOTE_DOWN 0 +#define VOTE_UP 1 + +#define DIAG_TS_SIZE 50 + +#define DIAG_MDM_BUF_SIZE 2048 +/* The Maximum request size is 2k + DCI header + footer (6 bytes) */ +#define DIAG_MDM_DCI_BUF_SIZE (2048 + 6) + +#define DIAG_LOCAL_PROC 0 + +#ifndef CONFIG_DIAGFWD_BRIDGE_CODE +/* Local Processor only */ +#define DIAG_NUM_PROC 1 +#else +/* Local Processor + Remote Devices */ +#define DIAG_NUM_PROC (1 + NUM_REMOTE_DEV) +#endif + +#define DIAG_WS_DCI 0 +#define DIAG_WS_MUX 1 + +#define DIAG_DATA_TYPE 1 +#define DIAG_CNTL_TYPE 2 +#define DIAG_DCI_TYPE 3 + +/* List of remote processor supported */ +enum remote_procs { + MDM = 1, + MDM2 = 2, + QSC = 5, +}; + +struct diag_pkt_header_t { + uint8_t cmd_code; + uint8_t subsys_id; + uint16_t subsys_cmd_code; +} __packed; + +struct diag_cmd_ext_mobile_rsp_t { + struct diag_pkt_header_t header; + uint8_t version; + uint8_t padding[3]; + uint32_t family; + uint32_t chip_id; +} __packed; + +struct diag_cmd_time_sync_query_req_t { + struct diag_pkt_header_t header; + uint8_t version; +}; + +struct diag_cmd_time_sync_query_rsp_t { + struct diag_pkt_header_t header; + uint8_t version; + uint8_t time_api; +}; + +struct diag_cmd_time_sync_switch_req_t { + struct diag_pkt_header_t header; + uint8_t version; + uint8_t time_api; + uint8_t persist_time; +}; + +struct diag_cmd_time_sync_switch_rsp_t { + struct diag_pkt_header_t header; + uint8_t version; + uint8_t time_api; + uint8_t time_api_status; + uint8_t persist_time_status; +}; + +struct diag_cmd_reg_entry_t { + uint16_t cmd_code; + uint16_t subsys_id; + uint16_t cmd_code_lo; + uint16_t cmd_code_hi; +} __packed; + +struct diag_cmd_reg_t { + struct list_head link; + struct diag_cmd_reg_entry_t entry; + uint8_t proc; + int pid; +}; + +/* + * @sync_obj_name: name of the synchronization object associated with this proc + * @count: number of entries in the bind + * @entries: the actual packet registrations + */ +struct diag_cmd_reg_tbl_t { + char sync_obj_name[MAX_SYNC_OBJ_NAME_SIZE]; + uint32_t count; + struct diag_cmd_reg_entry_t *entries; +}; + +struct diag_client_map { + char name[20]; + int pid; +}; + +struct real_time_vote_t { + int client_id; + uint16_t proc; + uint8_t real_time_vote; +} __packed; + +struct real_time_query_t { + int real_time; + int proc; +} __packed; + +struct diag_buffering_mode_t { + uint8_t peripheral; + uint8_t mode; + uint8_t high_wm_val; + uint8_t low_wm_val; +} __packed; + +struct diag_callback_reg_t { + int proc; +} __packed; + +struct diag_ws_ref_t { + int ref_count; + int copy_count; + spinlock_t lock; +}; + +/* This structure is defined in USB header file */ +#ifndef CONFIG_DIAG_OVER_USB +struct diag_request { + char *buf; + int length; + int actual; + int status; + void *context; +}; +#endif + +struct diag_pkt_stats_t { + uint32_t alloc_count; + uint32_t drop_count; +}; + +struct diag_cmd_stats_rsp_t { + struct diag_pkt_header_t header; + uint32_t payload; +}; + +struct diag_cmd_hdlc_disable_rsp_t { + struct diag_pkt_header_t header; + uint8_t framing_version; + uint8_t result; +}; + +struct diag_pkt_frame_t { + uint8_t start; + uint8_t version; + uint16_t length; +}; + +struct diag_partial_pkt_t { + uint32_t total_len; + uint32_t read_len; + uint32_t remaining; + uint32_t capacity; + uint8_t processing; + unsigned char *data; +} __packed; + +struct diag_logging_mode_param_t { + uint32_t req_mode; + uint32_t peripheral_mask; + uint32_t pd_mask; + uint8_t mode_param; +} __packed; + +struct diag_md_session_t { + int pid; + int peripheral_mask; + uint8_t hdlc_disabled; + uint8_t msg_mask_tbl_count; + struct timer_list hdlc_reset_timer; + struct diag_mask_info *msg_mask; + struct diag_mask_info *log_mask; + struct diag_mask_info *event_mask; + struct thread_info *md_client_thread_info; + struct task_struct *task; +}; + +/* + * High level structure for storing Diag masks. + * + * @ptr: Pointer to the buffer that stores the masks + * @mask_len: Length of the buffer pointed by ptr + * @update_buf: Buffer for performing mask updates to peripherals + * @update_buf_len: Length of the buffer pointed by buf + * @status: status of the mask - all enable, disabled, valid + * @lock: To protect access to the mask variables + */ +struct diag_mask_info { + uint8_t *ptr; + int mask_len; + uint8_t *update_buf; + int update_buf_len; + uint8_t status; + struct mutex lock; +}; + +struct diag_md_proc_info { + int pid; + struct task_struct *socket_process; + struct task_struct *callback_process; + struct task_struct *mdlog_process; +}; + +struct diag_feature_t { + uint8_t feature_mask[FEATURE_MASK_LEN]; + uint8_t rcvd_feature_mask; + uint8_t log_on_demand; + uint8_t separate_cmd_rsp; + uint8_t encode_hdlc; + uint8_t untag_header; + uint8_t peripheral_buffering; + uint8_t pd_buffering; + uint8_t mask_centralization; + uint8_t stm_support; + uint8_t sockets_enabled; + uint8_t sent_feature_mask; +}; + +struct diagchar_dev { + + /* State for the char driver */ + unsigned int major; + unsigned int minor_start; + int num; + struct cdev *cdev; + char *name; + struct class *diagchar_class; + struct device *diag_dev; + int ref_count; + int mask_clear; + struct mutex diag_maskclear_mutex; + struct mutex diag_notifier_mutex; + struct mutex diagchar_mutex; + struct mutex diag_file_mutex; + wait_queue_head_t wait_q; + struct diag_client_map *client_map; + int *data_ready; + atomic_t data_ready_notif[THRESHOLD_CLIENT_LIMIT]; + int num_clients; + int polling_reg_flag; + int use_device_tree; + int supports_separate_cmdrsp; + int supports_apps_hdlc_encoding; + int supports_apps_header_untagging; + int supports_pd_buffering; + int peripheral_untag[NUM_PERIPHERALS]; + int supports_sockets; + /* The state requested in the STM command */ + int stm_state_requested[NUM_STM_PROCESSORS]; + /* The current STM state */ + int stm_state[NUM_STM_PROCESSORS]; + uint16_t stm_peripheral; + struct work_struct stm_update_work; + uint16_t mask_update; + struct work_struct mask_update_work; + uint16_t close_transport; + struct work_struct close_transport_work; + struct workqueue_struct *cntl_wq; + struct mutex cntl_lock; + /* Whether or not the peripheral supports STM */ + /* Delayed response Variables */ + uint16_t delayed_rsp_id; + struct mutex delayed_rsp_mutex; + /* DCI related variables */ + struct list_head dci_req_list; + struct list_head dci_client_list; + int dci_tag; + int dci_client_id; + struct mutex dci_mutex; + int num_dci_client; + unsigned char *apps_dci_buf; + int dci_state; + struct workqueue_struct *diag_dci_wq; + struct list_head cmd_reg_list; + struct mutex cmd_reg_mutex; + uint32_t cmd_reg_count; + struct mutex diagfwd_channel_mutex[NUM_PERIPHERALS]; + /* Sizes that reflect memory pool sizes */ + unsigned int poolsize; + unsigned int poolsize_hdlc; + unsigned int poolsize_dci; + unsigned int poolsize_user; + /* Buffers for masks */ + struct mutex diag_cntl_mutex; + /* Members for Sending response */ + unsigned char *encoded_rsp_buf; + int encoded_rsp_len; + uint8_t rsp_buf_busy; + spinlock_t rsp_buf_busy_lock; + int rsp_buf_ctxt; + struct diagfwd_info *diagfwd_data[NUM_PERIPHERALS]; + struct diagfwd_info *diagfwd_cntl[NUM_PERIPHERALS]; + struct diagfwd_info *diagfwd_dci[NUM_PERIPHERALS]; + struct diagfwd_info *diagfwd_cmd[NUM_PERIPHERALS]; + struct diagfwd_info *diagfwd_dci_cmd[NUM_PERIPHERALS]; + struct diag_feature_t feature[NUM_PERIPHERALS]; + struct diag_buffering_mode_t buffering_mode[NUM_MD_SESSIONS]; + uint8_t buffering_flag[NUM_MD_SESSIONS]; + struct mutex mode_lock; + unsigned char *user_space_data_buf; + uint8_t user_space_data_busy; + struct diag_pkt_stats_t msg_stats; + struct diag_pkt_stats_t log_stats; + struct diag_pkt_stats_t event_stats; + /* buffer for updating mask to peripherals */ + unsigned char *buf_feature_mask_update; + uint8_t hdlc_disabled; + struct mutex hdlc_disable_mutex; + struct mutex hdlc_recovery_mutex; + struct timer_list hdlc_reset_timer; + struct mutex diag_hdlc_mutex; + unsigned char *hdlc_buf; + uint32_t hdlc_buf_len; + unsigned char *apps_rsp_buf; + struct diag_partial_pkt_t incoming_pkt; + int in_busy_pktdata; + /* Variables for non real time mode */ + int real_time_mode[DIAG_NUM_PROC]; + int real_time_update_busy; + uint16_t proc_active_mask; + uint16_t proc_rt_vote_mask[DIAG_NUM_PROC]; + struct mutex real_time_mutex; + struct work_struct diag_real_time_work; + struct workqueue_struct *diag_real_time_wq; +#ifdef CONFIG_DIAG_OVER_USB + int usb_connected; +#endif + struct workqueue_struct *diag_wq; + struct work_struct diag_drain_work; + struct work_struct update_user_clients; + struct work_struct update_md_clients; + struct workqueue_struct *diag_cntl_wq; + uint8_t log_on_demand_support; + uint8_t *apps_req_buf; + uint32_t apps_req_buf_len; + uint8_t *dci_pkt_buf; /* For Apps DCI packets */ + uint32_t dci_pkt_length; + int in_busy_dcipktdata; + int logging_mode; + int logging_mask; + int pd_logging_mode[NUM_UPD]; + int pd_session_clear[NUM_UPD]; + int num_pd_session; + int mask_check; + uint32_t md_session_mask; + uint8_t md_session_mode; + struct diag_md_session_t *md_session_map[NUM_MD_SESSIONS]; + struct mutex md_session_lock; + /* Power related variables */ + struct diag_ws_ref_t dci_ws; + struct diag_ws_ref_t md_ws; + /* Pointers to Diag Masks */ + struct diag_mask_info *msg_mask; + struct diag_mask_info *log_mask; + struct diag_mask_info *event_mask; + struct diag_mask_info *build_time_mask; + uint8_t msg_mask_tbl_count; + uint8_t bt_msg_mask_tbl_count; + uint16_t event_mask_size; + uint16_t last_event_id; + struct mutex msg_mask_lock; + /* Variables for Mask Centralization */ + uint16_t num_event_id[NUM_PERIPHERALS]; + uint32_t num_equip_id[NUM_PERIPHERALS]; + uint32_t max_ssid_count[NUM_PERIPHERALS]; +#ifdef CONFIG_DIAGFWD_BRIDGE_CODE + /* For sending command requests in callback mode */ + unsigned char *hdlc_encode_buf; + int hdlc_encode_buf_len; +#endif + int time_sync_enabled; + uint8_t uses_time_api; + struct platform_device *pdev; +}; + +extern struct diagchar_dev *driver; + +extern int wrap_enabled; +extern uint16_t wrap_count; + +void diag_get_timestamp(char *time_str); +void check_drain_timer(void); +int diag_get_remote(int remote_info); + +void diag_ws_init(void); +void diag_ws_on_notify(void); +void diag_ws_on_read(int type, int pkt_len); +void diag_ws_on_copy(int type); +void diag_ws_on_copy_fail(int type); +void diag_ws_on_copy_complete(int type); +void diag_ws_reset(int type); +void diag_ws_release(void); +void chk_logging_wakeup(void); +int diag_cmd_add_reg(struct diag_cmd_reg_entry_t *new_entry, uint8_t proc, + int pid); +struct diag_cmd_reg_entry_t *diag_cmd_search( + struct diag_cmd_reg_entry_t *entry, + int proc); +void diag_cmd_remove_reg(struct diag_cmd_reg_entry_t *entry, uint8_t proc); +void diag_cmd_remove_reg_by_pid(int pid); +void diag_cmd_remove_reg_by_proc(int proc); +int diag_cmd_chk_polling(struct diag_cmd_reg_entry_t *entry); +int diag_mask_param(void); +void diag_clear_masks(int pid); +uint8_t diag_mask_to_pd_value(uint32_t peripheral_mask); + +void diag_record_stats(int type, int flag); + +struct diag_md_session_t *diag_md_session_get_pid(int pid); +struct diag_md_session_t *diag_md_session_get_peripheral(uint8_t peripheral); + +#endif diff -Nruw linux-4.4.115-fbx/drivers/char/diag./diagchar_hdlc.c linux-4.4.115-fbx/drivers/char/diag/diagchar_hdlc.c --- linux-4.4.115-fbx/drivers/char/diag./diagchar_hdlc.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-4.4.115-fbx/drivers/char/diag/diagchar_hdlc.c 2019-01-22 16:16:22.959241480 +0100 @@ -0,0 +1,267 @@ +/* Copyright (c) 2008-2009, 2012-2014, The Linux Foundation. + * All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include "diagchar_hdlc.h" +#include "diagchar.h" + + +MODULE_LICENSE("GPL v2"); + +#define CRC_16_L_SEED 0xFFFF + +#define CRC_16_L_STEP(xx_crc, xx_c) \ + crc_ccitt_byte(xx_crc, xx_c) + +void diag_hdlc_encode(struct diag_send_desc_type *src_desc, + struct diag_hdlc_dest_type *enc) +{ + uint8_t *dest; + uint8_t *dest_last; + const uint8_t *src; + const uint8_t *src_last; + uint16_t crc; + unsigned char src_byte = 0; + enum diag_send_state_enum_type state; + unsigned int used = 0; + + if (src_desc && enc) { + + /* Copy parts to local variables. */ + src = src_desc->pkt; + src_last = src_desc->last; + state = src_desc->state; + dest = enc->dest; + dest_last = enc->dest_last; + + if (state == DIAG_STATE_START) { + crc = CRC_16_L_SEED; + state++; + } else { + /* Get a local copy of the CRC */ + crc = enc->crc; + } + + /* dest or dest_last may be NULL to trigger a + state transition only */ + if (dest && dest_last) { + /* This condition needs to include the possibility + of 2 dest bytes for an escaped byte */ + while (src <= src_last && dest <= dest_last) { + + src_byte = *src++; + + if ((src_byte == CONTROL_CHAR) || + (src_byte == ESC_CHAR)) { + + /* If the escape character is not the + last byte */ + if (dest != dest_last) { + crc = CRC_16_L_STEP(crc, + src_byte); + + *dest++ = ESC_CHAR; + used++; + + *dest++ = src_byte + ^ ESC_MASK; + used++; + } else { + + src--; + break; + } + + } else { + crc = CRC_16_L_STEP(crc, src_byte); + *dest++ = src_byte; + used++; + } + } + + if (src > src_last) { + + if (state == DIAG_STATE_BUSY) { + if (src_desc->terminate) { + crc = ~crc; + state++; + } else { + /* Done with fragment */ + state = DIAG_STATE_COMPLETE; + } + } + + while (dest <= dest_last && + state >= DIAG_STATE_CRC1 && + state < DIAG_STATE_TERM) { + /* Encode a byte of the CRC next */ + src_byte = crc & 0xFF; + + if ((src_byte == CONTROL_CHAR) + || (src_byte == ESC_CHAR)) { + + if (dest != dest_last) { + + *dest++ = ESC_CHAR; + used++; + *dest++ = src_byte ^ + ESC_MASK; + used++; + + crc >>= 8; + } else { + + break; + } + } else { + + crc >>= 8; + *dest++ = src_byte; + used++; + } + + state++; + } + + if (state == DIAG_STATE_TERM) { + if (dest_last >= dest) { + *dest++ = CONTROL_CHAR; + used++; + state++; /* Complete */ + } + } + } + } + /* Copy local variables back into the encode structure. */ + + enc->dest = dest; + enc->dest_last = dest_last; + enc->crc = crc; + src_desc->pkt = src; + src_desc->last = src_last; + src_desc->state = state; + } + + return; +} + + +int diag_hdlc_decode(struct diag_hdlc_decode_type *hdlc) +{ + uint8_t *src_ptr = NULL, *dest_ptr = NULL; + unsigned int src_length = 0, dest_length = 0; + + unsigned int len = 0; + unsigned int i; + uint8_t src_byte; + + int pkt_bnd = HDLC_INCOMPLETE; + int msg_start; + + if (hdlc && hdlc->src_ptr && hdlc->dest_ptr && + (hdlc->src_size > hdlc->src_idx) && + (hdlc->dest_size > hdlc->dest_idx)) { + + msg_start = (hdlc->src_idx == 0) ? 1 : 0; + + src_ptr = hdlc->src_ptr; + src_ptr = &src_ptr[hdlc->src_idx]; + src_length = hdlc->src_size - hdlc->src_idx; + + dest_ptr = hdlc->dest_ptr; + dest_ptr = &dest_ptr[hdlc->dest_idx]; + dest_length = hdlc->dest_size - hdlc->dest_idx; + + for (i = 0; i < src_length; i++) { + + src_byte = src_ptr[i]; + + if (hdlc->escaping) { + dest_ptr[len++] = src_byte ^ ESC_MASK; + hdlc->escaping = 0; + } else if (src_byte == ESC_CHAR) { + if (i == (src_length - 1)) { + hdlc->escaping = 1; + i++; + break; + } else { + dest_ptr[len++] = src_ptr[++i] + ^ ESC_MASK; + } + } else if (src_byte == CONTROL_CHAR) { + if (msg_start && i == 0 && src_length > 1) + continue; + /* Byte 0x7E will be considered + as end of packet */ + dest_ptr[len++] = src_byte; + i++; + pkt_bnd = HDLC_COMPLETE; + break; + } else { + dest_ptr[len++] = src_byte; + } + + if (len >= dest_length) { + i++; + break; + } + } + + hdlc->src_idx += i; + hdlc->dest_idx += len; + } + + return pkt_bnd; +} + +int crc_check(uint8_t *buf, uint16_t len) +{ + uint16_t crc = CRC_16_L_SEED; + uint8_t sent_crc[2] = {0, 0}; + + /* + * The minimum length of a valid incoming packet is 4. 1 byte + * of data and 3 bytes for CRC + */ + if (!buf || len < 4) { + pr_err_ratelimited("diag: In %s, invalid packet or length, buf: 0x%p, len: %d", + __func__, buf, len); + return -EIO; + } + + /* + * Run CRC check for the original input. Skip the last 3 CRC + * bytes + */ + crc = crc_ccitt(crc, buf, len-3); + crc ^= CRC_16_L_SEED; + + /* Check the computed CRC against the original CRC bytes. */ + sent_crc[0] = buf[len-3]; + sent_crc[1] = buf[len-2]; + if (crc != *((uint16_t *)sent_crc)) { + pr_debug("diag: In %s, crc mismatch. expected: %x, sent %x.\n", + __func__, crc, *((uint16_t *)sent_crc)); + return -EIO; + } + + return 0; +} diff -Nruw linux-4.4.115-fbx/drivers/char/diag./diagchar_hdlc.h linux-4.4.115-fbx/drivers/char/diag/diagchar_hdlc.h --- linux-4.4.115-fbx/drivers/char/diag./diagchar_hdlc.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-4.4.115-fbx/drivers/char/diag/diagchar_hdlc.h 2019-01-22 16:16:22.959241480 +0100 @@ -0,0 +1,66 @@ +/* Copyright (c) 2008-2009, 2012-2014, The Linux Foundation. + * All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef DIAGCHAR_HDLC +#define DIAGCHAR_HDLC + +enum diag_send_state_enum_type { + DIAG_STATE_START, + DIAG_STATE_BUSY, + DIAG_STATE_CRC1, + DIAG_STATE_CRC2, + DIAG_STATE_TERM, + DIAG_STATE_COMPLETE +}; + +struct diag_send_desc_type { + const void *pkt; + const void *last; /* Address of last byte to send. */ + enum diag_send_state_enum_type state; + unsigned char terminate; /* True if this fragment + terminates the packet */ +}; + +struct diag_hdlc_dest_type { + void *dest; + void *dest_last; + /* Below: internal use only */ + uint16_t crc; +}; + +struct diag_hdlc_decode_type { + uint8_t *src_ptr; + unsigned int src_idx; + unsigned int src_size; + uint8_t *dest_ptr; + unsigned int dest_idx; + unsigned int dest_size; + int escaping; + +}; + +void diag_hdlc_encode(struct diag_send_desc_type *src_desc, + struct diag_hdlc_dest_type *enc); + +int diag_hdlc_decode(struct diag_hdlc_decode_type *hdlc); + +int crc_check(uint8_t *buf, uint16_t len); + +#define ESC_CHAR 0x7D +#define ESC_MASK 0x20 + +#define HDLC_INCOMPLETE 0 +#define HDLC_COMPLETE 1 + +#define HDLC_FOOTER_LEN 3 +#endif diff -Nruw linux-4.4.115-fbx/drivers/char/diag./diag_dci.c linux-4.4.115-fbx/drivers/char/diag/diag_dci.c --- linux-4.4.115-fbx/drivers/char/diag./diag_dci.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-4.4.115-fbx/drivers/char/diag/diag_dci.c 2019-10-29 09:26:23.445201240 +0100 @@ -0,0 +1,3312 @@ +/* Copyright (c) 2012-2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#ifdef CONFIG_DIAG_OVER_USB +#include +#endif +#include "diagchar_hdlc.h" +#include "diagmem.h" +#include "diagchar.h" +#include "diagfwd.h" +#include "diagfwd_cntl.h" +#include "diag_dci.h" +#include "diag_masks.h" +#include "diagfwd_bridge.h" +#include "diagfwd_peripheral.h" +#include "diag_ipc_logging.h" + +static struct timer_list dci_drain_timer; +static int dci_timer_in_progress; +static struct work_struct dci_data_drain_work; + +struct diag_dci_partial_pkt_t partial_pkt; + +unsigned int dci_max_reg = 100; +unsigned int dci_max_clients = 10; +struct mutex dci_log_mask_mutex; +struct mutex dci_event_mask_mutex; + +/* + * DCI_HANDSHAKE_RETRY_TIME: Time to wait (in microseconds) before checking the + * connection status again. + * + * DCI_HANDSHAKE_WAIT_TIME: Timeout (in milliseconds) to check for dci + * connection status + */ +#define DCI_HANDSHAKE_RETRY_TIME 500000 +#define DCI_HANDSHAKE_WAIT_TIME 200 + +spinlock_t ws_lock; +unsigned long ws_lock_flags; + +struct dci_ops_tbl_t dci_ops_tbl[NUM_DCI_PROC] = { + { + .ctx = 0, + .send_log_mask = diag_send_dci_log_mask, + .send_event_mask = diag_send_dci_event_mask, + .peripheral_status = 0, + .mempool = 0, + }, +#ifdef CONFIG_DIAGFWD_BRIDGE_CODE + { + .ctx = DIAGFWD_MDM_DCI, + .send_log_mask = diag_send_dci_log_mask_remote, + .send_event_mask = diag_send_dci_event_mask_remote, + .peripheral_status = 0, + .mempool = POOL_TYPE_MDM_DCI_WRITE, + } +#endif +}; + +struct dci_channel_status_t dci_channel_status[NUM_DCI_PROC] = { + { + .id = 0, + .open = 0, + .retry_count = 0 + }, +#ifdef CONFIG_DIAGFWD_BRIDGE_CODE + { + .id = DIAGFWD_MDM_DCI, + .open = 0, + .retry_count = 0 + } +#endif +}; + +/* Number of milliseconds anticipated to process the DCI data */ +#define DCI_WAKEUP_TIMEOUT 1 + +#define DCI_CAN_ADD_BUF_TO_LIST(buf) \ + (buf && buf->data && !buf->in_busy && buf->data_len > 0) \ + +#ifdef CONFIG_DEBUG_FS +struct diag_dci_data_info *dci_traffic; +struct mutex dci_stat_mutex; +void diag_dci_record_traffic(int read_bytes, uint8_t ch_type, + uint8_t peripheral, uint8_t proc) +{ + static int curr_dci_data; + static unsigned long iteration; + struct diag_dci_data_info *temp_data = dci_traffic; + if (!temp_data) + return; + mutex_lock(&dci_stat_mutex); + if (curr_dci_data == DIAG_DCI_DEBUG_CNT) + curr_dci_data = 0; + temp_data += curr_dci_data; + temp_data->iteration = iteration + 1; + temp_data->data_size = read_bytes; + temp_data->peripheral = peripheral; + temp_data->ch_type = ch_type; + temp_data->proc = proc; + diag_get_timestamp(temp_data->time_stamp); + curr_dci_data++; + iteration++; + mutex_unlock(&dci_stat_mutex); +} +#else +void diag_dci_record_traffic(int read_bytes, uint8_t ch_type, + uint8_t peripheral, uint8_t proc) { } +#endif + +static int check_peripheral_dci_support(int peripheral_id, int dci_proc_id) +{ + int dci_peripheral_list = 0; + + if (dci_proc_id < 0 || dci_proc_id >= NUM_DCI_PROC) { + pr_err("diag:In %s,not a supported DCI proc id\n", __func__); + return 0; + } + if (peripheral_id < 0 || peripheral_id >= NUM_PERIPHERALS) { + pr_err("diag:In %s,not a valid peripheral id\n", __func__); + return 0; + } + dci_peripheral_list = dci_ops_tbl[dci_proc_id].peripheral_status; + + if (dci_peripheral_list <= 0 || dci_peripheral_list > DIAG_CON_ALL) { + pr_err("diag:In %s,not a valid dci peripheral mask\n", + __func__); + return 0; + } + /* Remove APSS bit mask information */ + dci_peripheral_list = dci_peripheral_list >> 1; + + if ((1 << peripheral_id) & (dci_peripheral_list)) + return 1; + else + return 0; +} + +static void create_dci_log_mask_tbl(unsigned char *mask, uint8_t dirty) +{ + unsigned char *temp = mask; + uint8_t i; + + if (!mask) + return; + + /* create hard coded table for log mask with 16 categories */ + for (i = 0; i < DCI_MAX_LOG_CODES; i++) { + *temp = i; + temp++; + *temp = dirty ? 1 : 0; + temp++; + memset(temp, 0, DCI_MAX_ITEMS_PER_LOG_CODE); + temp += DCI_MAX_ITEMS_PER_LOG_CODE; + } +} + +static void create_dci_event_mask_tbl(unsigned char *tbl_buf) +{ + if (tbl_buf) + memset(tbl_buf, 0, DCI_EVENT_MASK_SIZE); +} + +void dci_drain_data(unsigned long data) +{ + queue_work(driver->diag_dci_wq, &dci_data_drain_work); +} + +static void dci_check_drain_timer(void) +{ + if (!dci_timer_in_progress) { + dci_timer_in_progress = 1; + mod_timer(&dci_drain_timer, jiffies + msecs_to_jiffies(200)); + } +} + +#ifdef CONFIG_DIAGFWD_BRIDGE_CODE +static void dci_handshake_work_fn(struct work_struct *work) +{ + int err = 0; + int max_retries = 5; + + struct dci_channel_status_t *status = container_of(work, + struct dci_channel_status_t, + handshake_work); + + if (status->open) { + pr_debug("diag: In %s, remote dci channel is open, index: %d\n", + __func__, status->id); + return; + } + + if (status->retry_count == max_retries) { + status->retry_count = 0; + pr_info("diag: dci channel connection handshake timed out, id: %d\n", + status->id); + err = diagfwd_bridge_close(TOKEN_TO_BRIDGE(status->id)); + if (err) { + pr_err("diag: In %s, unable to close dci channel id: %d, err: %d\n", + __func__, status->id, err); + } + return; + } + status->retry_count++; + /* + * Sleep for sometime to check for the connection status again. The + * value should be optimum to include a roundabout time for a small + * packet to the remote processor. + */ + usleep_range(DCI_HANDSHAKE_RETRY_TIME, DCI_HANDSHAKE_RETRY_TIME + 100); + mod_timer(&status->wait_time, + jiffies + msecs_to_jiffies(DCI_HANDSHAKE_WAIT_TIME)); +} + +static void dci_chk_handshake(unsigned long data) +{ + int index = (int)data; + + if (index < 0 || index >= NUM_DCI_PROC) + return; + + queue_work(driver->diag_dci_wq, + &dci_channel_status[index].handshake_work); +} +#endif + +static int diag_dci_init_buffer(struct diag_dci_buffer_t *buffer, int type) +{ + if (!buffer || buffer->data) + return -EINVAL; + + switch (type) { + case DCI_BUF_PRIMARY: + buffer->capacity = IN_BUF_SIZE; + buffer->data = vzalloc(buffer->capacity); + if (!buffer->data) + return -ENOMEM; + break; + case DCI_BUF_SECONDARY: + buffer->data = NULL; + buffer->capacity = IN_BUF_SIZE; + break; + case DCI_BUF_CMD: + buffer->capacity = DIAG_MAX_REQ_SIZE + DCI_BUF_SIZE; + buffer->data = vzalloc(buffer->capacity); + if (!buffer->data) + return -ENOMEM; + break; + default: + pr_err("diag: In %s, unknown type %d", __func__, type); + return -EINVAL; + } + + buffer->data_len = 0; + buffer->in_busy = 0; + buffer->buf_type = type; + mutex_init(&buffer->data_mutex); + + return 0; +} + +static inline int diag_dci_check_buffer(struct diag_dci_buffer_t *buf, int len) +{ + if (!buf) + return -EINVAL; + + /* Return 1 if the buffer is not busy and can hold new data */ + if ((buf->data_len + len < buf->capacity) && !buf->in_busy) + return 1; + + return 0; +} + +static void dci_add_buffer_to_list(struct diag_dci_client_tbl *client, + struct diag_dci_buffer_t *buf) +{ + if (!buf || !client || !buf->data) + return; + + if (buf->in_list || buf->data_len == 0) + return; + + mutex_lock(&client->write_buf_mutex); + list_add_tail(&buf->buf_track, &client->list_write_buf); + /* + * In the case of DCI, there can be multiple packets in one read. To + * calculate the wakeup source reference count, we must account for each + * packet in a single read. + */ + diag_ws_on_read(DIAG_WS_DCI, buf->data_len); + mutex_lock(&buf->data_mutex); + buf->in_busy = 1; + buf->in_list = 1; + mutex_unlock(&buf->data_mutex); + mutex_unlock(&client->write_buf_mutex); +} + +static int diag_dci_get_buffer(struct diag_dci_client_tbl *client, + int data_source, int len) +{ + struct diag_dci_buffer_t *buf_primary = NULL; + struct diag_dci_buffer_t *buf_temp = NULL; + struct diag_dci_buffer_t *curr = NULL; + + if (!client) + return -EINVAL; + if (len < 0 || len > IN_BUF_SIZE) + return -EINVAL; + + curr = client->buffers[data_source].buf_curr; + buf_primary = client->buffers[data_source].buf_primary; + + if (curr && diag_dci_check_buffer(curr, len) == 1) + return 0; + + dci_add_buffer_to_list(client, curr); + client->buffers[data_source].buf_curr = NULL; + + if (diag_dci_check_buffer(buf_primary, len) == 1) { + client->buffers[data_source].buf_curr = buf_primary; + return 0; + } + + buf_temp = kzalloc(sizeof(struct diag_dci_buffer_t), GFP_KERNEL); + if (!buf_temp) + return -EIO; + + if (!diag_dci_init_buffer(buf_temp, DCI_BUF_SECONDARY)) { + buf_temp->data = diagmem_alloc(driver, IN_BUF_SIZE, + POOL_TYPE_DCI); + if (!buf_temp->data) { + kfree(buf_temp); + buf_temp = NULL; + return -ENOMEM; + } + client->buffers[data_source].buf_curr = buf_temp; + return 0; + } + + kfree(buf_temp); + buf_temp = NULL; + return -EIO; +} + +void diag_dci_wakeup_clients() +{ + struct list_head *start, *temp; + struct diag_dci_client_tbl *entry = NULL; + + mutex_lock(&driver->dci_mutex); + list_for_each_safe(start, temp, &driver->dci_client_list) { + entry = list_entry(start, struct diag_dci_client_tbl, track); + + /* + * Don't wake up the client when there is no pending buffer to + * write or when it is writing to user space + */ + if (!list_empty(&entry->list_write_buf) && !entry->in_service) { + mutex_lock(&entry->write_buf_mutex); + entry->in_service = 1; + mutex_unlock(&entry->write_buf_mutex); + diag_update_sleeping_process(entry->client->tgid, + DCI_DATA_TYPE); + } + } + mutex_unlock(&driver->dci_mutex); +} + +void dci_data_drain_work_fn(struct work_struct *work) +{ + int i; + struct list_head *start, *temp; + struct diag_dci_client_tbl *entry = NULL; + struct diag_dci_buf_peripheral_t *proc_buf = NULL; + struct diag_dci_buffer_t *buf_temp = NULL; + + mutex_lock(&driver->dci_mutex); + list_for_each_safe(start, temp, &driver->dci_client_list) { + entry = list_entry(start, struct diag_dci_client_tbl, track); + for (i = 0; i < entry->num_buffers; i++) { + proc_buf = &entry->buffers[i]; + + mutex_lock(&proc_buf->buf_mutex); + buf_temp = proc_buf->buf_primary; + if (DCI_CAN_ADD_BUF_TO_LIST(buf_temp)) + dci_add_buffer_to_list(entry, buf_temp); + + buf_temp = proc_buf->buf_cmd; + if (DCI_CAN_ADD_BUF_TO_LIST(buf_temp)) + dci_add_buffer_to_list(entry, buf_temp); + + buf_temp = proc_buf->buf_curr; + if (DCI_CAN_ADD_BUF_TO_LIST(buf_temp)) { + dci_add_buffer_to_list(entry, buf_temp); + proc_buf->buf_curr = NULL; + } + mutex_unlock(&proc_buf->buf_mutex); + } + if (!list_empty(&entry->list_write_buf) && !entry->in_service) { + mutex_lock(&entry->write_buf_mutex); + entry->in_service = 1; + mutex_unlock(&entry->write_buf_mutex); + diag_update_sleeping_process(entry->client->tgid, + DCI_DATA_TYPE); + } + } + mutex_unlock(&driver->dci_mutex); + dci_timer_in_progress = 0; +} + +static int diag_process_single_dci_pkt(unsigned char *buf, int len, + int data_source, int token) +{ + uint8_t cmd_code = 0; + + if (!buf || len < 0) { + pr_err("diag: Invalid input in %s, buf: %pK, len: %d\n", + __func__, buf, len); + return -EIO; + } + + cmd_code = *(uint8_t *)buf; + + switch (cmd_code) { + case LOG_CMD_CODE: + extract_dci_log(buf, len, data_source, token, NULL); + break; + case EVENT_CMD_CODE: + extract_dci_events(buf, len, data_source, token, NULL); + break; + case EXT_HDR_CMD_CODE: + extract_dci_ext_pkt(buf, len, data_source, token); + break; + case DCI_PKT_RSP_CODE: + case DCI_DELAYED_RSP_CODE: + extract_dci_pkt_rsp(buf, len, data_source, token); + break; + case DCI_CONTROL_PKT_CODE: + extract_dci_ctrl_pkt(buf, len, token); + break; + default: + pr_err("diag: Unable to process single DCI packet, cmd_code: %d, data_source: %d", + cmd_code, data_source); + return -EINVAL; + } + + return 0; +} + +/* Process the data read from apps userspace client */ +void diag_process_apps_dci_read_data(int data_type, void *buf, int recd_bytes) +{ + int err = 0; + + if (!buf) { + pr_err_ratelimited("diag: In %s, Null buf pointer\n", __func__); + return; + } + + if (data_type != DATA_TYPE_DCI_LOG && data_type != DATA_TYPE_DCI_EVENT + && data_type != DCI_PKT_TYPE) { + pr_err("diag: In %s, unsupported data_type: 0x%x\n", + __func__, (unsigned int)data_type); + return; + } + + err = diag_process_single_dci_pkt(buf, recd_bytes, APPS_DATA, + DCI_LOCAL_PROC); + if (err) + return; + + /* wake up all sleeping DCI clients which have some data */ + diag_dci_wakeup_clients(); + dci_check_drain_timer(); +} + +void diag_process_remote_dci_read_data(int index, void *buf, int recd_bytes) +{ + int read_bytes = 0, err = 0; + uint16_t dci_pkt_len; + struct diag_dci_header_t *header = NULL; + int header_len = sizeof(struct diag_dci_header_t); + int token = BRIDGE_TO_TOKEN(index); + + if (!buf) + return; + + diag_dci_record_traffic(recd_bytes, 0, 0, token); + + if (!partial_pkt.processing) + goto start; + + if (partial_pkt.remaining > recd_bytes) { + if ((partial_pkt.read_len + recd_bytes) > + (MAX_DCI_PACKET_SZ)) { + pr_err("diag: Invalid length %d, %d received in %s\n", + partial_pkt.read_len, recd_bytes, __func__); + goto end; + } + memcpy(partial_pkt.data + partial_pkt.read_len, buf, + recd_bytes); + read_bytes += recd_bytes; + buf += read_bytes; + partial_pkt.read_len += recd_bytes; + partial_pkt.remaining -= recd_bytes; + } else { + if ((partial_pkt.read_len + partial_pkt.remaining) > + (MAX_DCI_PACKET_SZ)) { + pr_err("diag: Invalid length during partial read %d, %d received in %s\n", + partial_pkt.read_len, + partial_pkt.remaining, __func__); + goto end; + } + memcpy(partial_pkt.data + partial_pkt.read_len, buf, + partial_pkt.remaining); + read_bytes += partial_pkt.remaining; + buf += read_bytes; + partial_pkt.read_len += partial_pkt.remaining; + partial_pkt.remaining = 0; + } + + if (partial_pkt.remaining == 0) { + /* + * Retrieve from the DCI control packet after the header = start + * (1 byte) + version (1 byte) + length (2 bytes) + */ + diag_process_single_dci_pkt(partial_pkt.data + 4, + partial_pkt.read_len - header_len, + DCI_REMOTE_DATA, token); + partial_pkt.read_len = 0; + partial_pkt.total_len = 0; + partial_pkt.processing = 0; + goto start; + } + goto end; + +start: + while (read_bytes < recd_bytes) { + header = (struct diag_dci_header_t *)buf; + dci_pkt_len = header->length; + + if (header->cmd_code != DCI_CONTROL_PKT_CODE && + driver->num_dci_client == 0) { + read_bytes += header_len + dci_pkt_len; + buf += header_len + dci_pkt_len; + continue; + } + + if (dci_pkt_len + header_len > MAX_DCI_PACKET_SZ) { + pr_err("diag: Invalid length in the dci packet field %d\n", + dci_pkt_len); + break; + } + + if ((dci_pkt_len + header_len) > (recd_bytes - read_bytes)) { + partial_pkt.read_len = recd_bytes - read_bytes; + partial_pkt.total_len = dci_pkt_len + header_len; + partial_pkt.remaining = partial_pkt.total_len - + partial_pkt.read_len; + partial_pkt.processing = 1; + memcpy(partial_pkt.data, buf, partial_pkt.read_len); + break; + } + /* + * Retrieve from the DCI control packet after the header = start + * (1 byte) + version (1 byte) + length (2 bytes) + */ + err = diag_process_single_dci_pkt(buf + 4, dci_pkt_len, + DCI_REMOTE_DATA, DCI_MDM_PROC); + if (err) + break; + read_bytes += header_len + dci_pkt_len; + buf += header_len + dci_pkt_len; /* advance to next DCI pkt */ + } +end: + if (err) + return; + /* wake up all sleeping DCI clients which have some data */ + diag_dci_wakeup_clients(); + dci_check_drain_timer(); + return; +} + +/* Process the data read from the peripheral dci channels */ +void diag_dci_process_peripheral_data(struct diagfwd_info *p_info, void *buf, + int recd_bytes) +{ + int read_bytes = 0, err = 0; + uint16_t dci_pkt_len; + struct diag_dci_pkt_header_t *header = NULL; + uint8_t recv_pkt_cmd_code; + + if (!buf || !p_info) + return; + + /* + * Release wakeup source when there are no more clients to + * process DCI data + */ + if (driver->num_dci_client == 0) { + diag_ws_reset(DIAG_WS_DCI); + return; + } + + diag_dci_record_traffic(recd_bytes, p_info->type, p_info->peripheral, + DCI_LOCAL_PROC); + while (read_bytes < recd_bytes) { + header = (struct diag_dci_pkt_header_t *)buf; + recv_pkt_cmd_code = header->pkt_code; + dci_pkt_len = header->len; + + /* + * Check if the length of the current packet is lesser than the + * remaining bytes in the received buffer. This includes space + * for the Start byte (1), Version byte (1), length bytes (2) + * and End byte (1) + */ + if ((dci_pkt_len + 5) > (recd_bytes - read_bytes)) { + pr_err("diag: Invalid length in %s, len: %d, dci_pkt_len: %d", + __func__, recd_bytes, dci_pkt_len); + diag_ws_release(); + return; + } + /* + * Retrieve from the DCI control packet after the header = start + * (1 byte) + version (1 byte) + length (2 bytes) + */ + err = diag_process_single_dci_pkt(buf + 4, dci_pkt_len, + (int)p_info->peripheral, + DCI_LOCAL_PROC); + if (err) { + diag_ws_release(); + break; + } + read_bytes += 5 + dci_pkt_len; + buf += 5 + dci_pkt_len; /* advance to next DCI pkt */ + } + + if (err) + return; + /* wake up all sleeping DCI clients which have some data */ + diag_dci_wakeup_clients(); + dci_check_drain_timer(); + return; +} + +int diag_dci_query_log_mask(struct diag_dci_client_tbl *entry, + uint16_t log_code) +{ + uint16_t item_num; + uint8_t equip_id, *log_mask_ptr, byte_mask; + int byte_index, offset; + + if (!entry) { + pr_err("diag: In %s, invalid client entry\n", __func__); + return 0; + } + + equip_id = LOG_GET_EQUIP_ID(log_code); + item_num = LOG_GET_ITEM_NUM(log_code); + byte_index = item_num/8 + 2; + byte_mask = 0x01 << (item_num % 8); + offset = equip_id * 514; + + if (offset + byte_index >= DCI_LOG_MASK_SIZE) { + pr_err("diag: In %s, invalid offset: %d, log_code: %d, byte_index: %d\n", + __func__, offset, log_code, byte_index); + return 0; + } + + log_mask_ptr = entry->dci_log_mask; + log_mask_ptr = log_mask_ptr + offset + byte_index; + return ((*log_mask_ptr & byte_mask) == byte_mask) ? 1 : 0; + +} + +int diag_dci_query_event_mask(struct diag_dci_client_tbl *entry, + uint16_t event_id) +{ + uint8_t *event_mask_ptr, byte_mask; + int byte_index, bit_index; + + if (!entry) { + pr_err("diag: In %s, invalid client entry\n", __func__); + return 0; + } + + byte_index = event_id/8; + bit_index = event_id % 8; + byte_mask = 0x1 << bit_index; + + if (byte_index >= DCI_EVENT_MASK_SIZE) { + pr_err("diag: In %s, invalid, event_id: %d, byte_index: %d\n", + __func__, event_id, byte_index); + return 0; + } + + event_mask_ptr = entry->dci_event_mask; + event_mask_ptr = event_mask_ptr + byte_index; + return ((*event_mask_ptr & byte_mask) == byte_mask) ? 1 : 0; +} + +static int diag_dci_filter_commands(struct diag_pkt_header_t *header) +{ + if (!header) + return -ENOMEM; + + switch (header->cmd_code) { + case 0x7d: /* Msg Mask Configuration */ + case 0x73: /* Log Mask Configuration */ + case 0x81: /* Event Mask Configuration */ + case 0x82: /* Event Mask Change */ + case 0x60: /* Event Mask Toggle */ + return 1; + } + + if (header->cmd_code == 0x4b && header->subsys_id == 0x12) { + switch (header->subsys_cmd_code) { + case 0x60: /* Extended Event Mask Config */ + case 0x61: /* Extended Msg Mask Config */ + case 0x62: /* Extended Log Mask Config */ + case 0x20C: /* Set current Preset ID */ + case 0x20D: /* Get current Preset ID */ + case 0x218: /* HDLC Disabled Command */ + return 1; + } + } + + return 0; +} + +static struct dci_pkt_req_entry_t *diag_register_dci_transaction(int uid, + int client_id) +{ + struct dci_pkt_req_entry_t *entry = NULL; + entry = kzalloc(sizeof(struct dci_pkt_req_entry_t), GFP_KERNEL); + if (!entry) + return NULL; + + driver->dci_tag++; + entry->client_id = client_id; + entry->uid = uid; + entry->tag = driver->dci_tag; + pr_debug("diag: Registering DCI cmd req, client_id: %d, uid: %d, tag:%d\n", + entry->client_id, entry->uid, entry->tag); + list_add_tail(&entry->track, &driver->dci_req_list); + + return entry; +} + +static struct dci_pkt_req_entry_t *diag_dci_get_request_entry(int tag) +{ + struct list_head *start, *temp; + struct dci_pkt_req_entry_t *entry = NULL; + list_for_each_safe(start, temp, &driver->dci_req_list) { + entry = list_entry(start, struct dci_pkt_req_entry_t, track); + if (entry->tag == tag) + return entry; + } + return NULL; +} + +static int diag_dci_remove_req_entry(unsigned char *buf, int len, + struct dci_pkt_req_entry_t *entry) +{ + uint16_t rsp_count = 0, delayed_rsp_id = 0; + if (!buf || len <= 0 || !entry) { + pr_err("diag: In %s, invalid input buf: %pK, len: %d, entry: %pK\n", + __func__, buf, len, entry); + return -EIO; + } + + /* It is an immediate response, delete it from the table */ + if (*buf != 0x80) { + list_del(&entry->track); + kfree(entry); + entry = NULL; + return 1; + } + + /* It is a delayed response. Check if the length is valid */ + if (len < MIN_DELAYED_RSP_LEN) { + pr_err("diag: Invalid delayed rsp packet length %d\n", len); + return -EINVAL; + } + + /* + * If the delayed response id field (uint16_t at byte 8) is 0 then + * there is only one response and we can remove the request entry. + */ + delayed_rsp_id = *(uint16_t *)(buf + 8); + if (delayed_rsp_id == 0) { + list_del(&entry->track); + kfree(entry); + entry = NULL; + return 1; + } + + /* + * Check the response count field (uint16 at byte 10). The request + * entry can be deleted it it is the last response in the sequence. + * It is the last response in the sequence if the response count + * is 1 or if the signed bit gets dropped. + */ + rsp_count = *(uint16_t *)(buf + 10); + if (rsp_count > 0 && rsp_count < 0x1000) { + list_del(&entry->track); + kfree(entry); + entry = NULL; + return 1; + } + + return 0; +} + +static void dci_process_ctrl_status(unsigned char *buf, int len, int token) +{ + struct diag_ctrl_dci_status *header = NULL; + unsigned char *temp = buf; + uint32_t read_len = 0; + uint8_t i; + int peripheral_mask, status; + + if (!buf || (len < sizeof(struct diag_ctrl_dci_status))) { + pr_err("diag: In %s, invalid buf %pK or length: %d\n", + __func__, buf, len); + return; + } + + if (!VALID_DCI_TOKEN(token)) { + pr_err("diag: In %s, invalid DCI token %d\n", __func__, token); + return; + } + + header = (struct diag_ctrl_dci_status *)temp; + temp += sizeof(struct diag_ctrl_dci_status); + read_len += sizeof(struct diag_ctrl_dci_status); + + for (i = 0; i < header->count; i++) { + if (read_len > (len - 2)) { + pr_err("diag: In %s, Invalid length len: %d\n", + __func__, len); + return; + } + + switch (*(uint8_t *)temp) { + case PERIPHERAL_MODEM: + peripheral_mask = DIAG_CON_MPSS; + break; + case PERIPHERAL_LPASS: + peripheral_mask = DIAG_CON_LPASS; + break; + case PERIPHERAL_WCNSS: + peripheral_mask = DIAG_CON_WCNSS; + break; + case PERIPHERAL_SENSORS: + peripheral_mask = DIAG_CON_SENSORS; + break; + default: + pr_err("diag: In %s, unknown peripheral, peripheral: %d\n", + __func__, *(uint8_t *)temp); + return; + } + temp += sizeof(uint8_t); + read_len += sizeof(uint8_t); + + status = (*(uint8_t *)temp) ? DIAG_STATUS_OPEN : + DIAG_STATUS_CLOSED; + temp += sizeof(uint8_t); + read_len += sizeof(uint8_t); + diag_dci_notify_client(peripheral_mask, status, token); + } +} + +static void dci_process_ctrl_handshake_pkt(unsigned char *buf, int len, + int token) +{ + struct diag_ctrl_dci_handshake_pkt *header = NULL; + unsigned char *temp = buf; + int err = 0; + + if (!buf || (len < sizeof(struct diag_ctrl_dci_handshake_pkt))) + return; + + if (!VALID_DCI_TOKEN(token)) + return; + + header = (struct diag_ctrl_dci_handshake_pkt *)temp; + if (header->magic == DCI_MAGIC) { + dci_channel_status[token].open = 1; + err = dci_ops_tbl[token].send_log_mask(token); + if (err) { + pr_err("diag: In %s, unable to send log mask to token: %d, err: %d\n", + __func__, token, err); + } + err = dci_ops_tbl[token].send_event_mask(token); + if (err) { + pr_err("diag: In %s, unable to send event mask to token: %d, err: %d\n", + __func__, token, err); + } + } +} + +void extract_dci_ctrl_pkt(unsigned char *buf, int len, int token) +{ + unsigned char *temp = buf; + uint32_t ctrl_pkt_id; + + diag_ws_on_read(DIAG_WS_DCI, len); + if (!buf) { + pr_err("diag: Invalid buffer in %s\n", __func__); + goto err; + } + + if (len < (sizeof(uint8_t) + sizeof(uint32_t))) { + pr_err("diag: In %s, invalid length %d\n", __func__, len); + goto err; + } + + /* Skip the Control packet command code */ + temp += sizeof(uint8_t); + len -= sizeof(uint8_t); + ctrl_pkt_id = *(uint32_t *)temp; + switch (ctrl_pkt_id) { + case DIAG_CTRL_MSG_DCI_CONNECTION_STATUS: + dci_process_ctrl_status(temp, len, token); + break; + case DIAG_CTRL_MSG_DCI_HANDSHAKE_PKT: + dci_process_ctrl_handshake_pkt(temp, len, token); + break; + default: + pr_debug("diag: In %s, unknown control pkt %d\n", + __func__, ctrl_pkt_id); + break; + } + +err: + /* + * DCI control packets are not consumed by the clients. Mimic client + * consumption by setting and clearing the wakeup source copy_count + * explicitly. + */ + diag_ws_on_copy_fail(DIAG_WS_DCI); +} + +void extract_dci_pkt_rsp(unsigned char *buf, int len, int data_source, + int token) +{ + int tag; + struct diag_dci_client_tbl *entry = NULL; + void *temp_buf = NULL; + uint8_t dci_cmd_code, cmd_code_len, delete_flag = 0; + uint32_t rsp_len = 0; + struct diag_dci_buffer_t *rsp_buf = NULL; + struct dci_pkt_req_entry_t *req_entry = NULL; + unsigned char *temp = buf; + int save_req_uid = 0; + struct diag_dci_pkt_rsp_header_t pkt_rsp_header; + + if (!buf) { + pr_err("diag: Invalid pointer in %s\n", __func__); + return; + } + dci_cmd_code = *(uint8_t *)(temp); + if (dci_cmd_code == DCI_PKT_RSP_CODE) { + cmd_code_len = sizeof(uint8_t); + } else if (dci_cmd_code == DCI_DELAYED_RSP_CODE) { + cmd_code_len = sizeof(uint32_t); + } else { + pr_err("diag: In %s, invalid command code %d\n", __func__, + dci_cmd_code); + return; + } + temp += cmd_code_len; + tag = *(int *)temp; + temp += sizeof(int); + + /* + * The size of the response is (total length) - (length of the command + * code, the tag (int) + */ + rsp_len = len - (cmd_code_len + sizeof(int)); + if ((rsp_len == 0) || (rsp_len > (len - 5))) { + pr_err("diag: Invalid length in %s, len: %d, rsp_len: %d", + __func__, len, rsp_len); + return; + } + + mutex_lock(&driver->dci_mutex); + req_entry = diag_dci_get_request_entry(tag); + if (!req_entry) { + pr_err_ratelimited("diag: No matching client for DCI data\n"); + mutex_unlock(&driver->dci_mutex); + return; + } + + entry = diag_dci_get_client_entry(req_entry->client_id); + if (!entry) { + pr_err("diag: In %s, couldn't find client entry, id:%d\n", + __func__, req_entry->client_id); + mutex_unlock(&driver->dci_mutex); + return; + } + + save_req_uid = req_entry->uid; + /* Remove the headers and send only the response to this function */ + delete_flag = diag_dci_remove_req_entry(temp, rsp_len, req_entry); + if (delete_flag < 0) { + mutex_unlock(&driver->dci_mutex); + return; + } + + mutex_lock(&entry->buffers[data_source].buf_mutex); + rsp_buf = entry->buffers[data_source].buf_cmd; + + mutex_lock(&rsp_buf->data_mutex); + /* + * Check if we can fit the data in the rsp buffer. The total length of + * the rsp is the rsp length (write_len) + DCI_PKT_RSP_TYPE header (int) + * + field for length (int) + delete_flag (uint8_t) + */ + if ((rsp_buf->data_len + 9 + rsp_len) > rsp_buf->capacity) { + pr_alert("diag: create capacity for pkt rsp\n"); + rsp_buf->capacity += 9 + rsp_len; + temp_buf = krealloc(rsp_buf->data, rsp_buf->capacity, + GFP_KERNEL); + if (!temp_buf) { + pr_err("diag: DCI realloc failed\n"); + mutex_unlock(&rsp_buf->data_mutex); + mutex_unlock(&entry->buffers[data_source].buf_mutex); + mutex_unlock(&driver->dci_mutex); + return; + } else { + rsp_buf->data = temp_buf; + } + } + + /* Fill in packet response header information */ + pkt_rsp_header.type = DCI_PKT_RSP_TYPE; + /* Packet Length = Response Length + Length of uid field (int) */ + pkt_rsp_header.length = rsp_len + sizeof(int); + pkt_rsp_header.delete_flag = delete_flag; + pkt_rsp_header.uid = save_req_uid; + memcpy(rsp_buf->data + rsp_buf->data_len, &pkt_rsp_header, + sizeof(struct diag_dci_pkt_rsp_header_t)); + rsp_buf->data_len += sizeof(struct diag_dci_pkt_rsp_header_t); + memcpy(rsp_buf->data + rsp_buf->data_len, temp, rsp_len); + rsp_buf->data_len += rsp_len; + rsp_buf->data_source = data_source; + + mutex_unlock(&rsp_buf->data_mutex); + + /* + * Add directly to the list for writing responses to the + * userspace as these shouldn't be buffered and shouldn't wait + * for log and event buffers to be full + */ + dci_add_buffer_to_list(entry, rsp_buf); + mutex_unlock(&entry->buffers[data_source].buf_mutex); + mutex_unlock(&driver->dci_mutex); +} + +static void copy_ext_hdr(struct diag_dci_buffer_t *data_buffer, void *ext_hdr) +{ + if (!data_buffer) { + pr_err("diag: In %s, data buffer is NULL", __func__); + return; + } + + *(int *)(data_buffer->data + data_buffer->data_len) = + DCI_EXT_HDR_TYPE; + data_buffer->data_len += sizeof(int); + memcpy(data_buffer->data + data_buffer->data_len, ext_hdr, + EXT_HDR_LEN); + data_buffer->data_len += EXT_HDR_LEN; +} + +static void copy_dci_event(unsigned char *buf, int len, + struct diag_dci_client_tbl *client, int data_source, + void *ext_hdr) +{ + struct diag_dci_buffer_t *data_buffer = NULL; + struct diag_dci_buf_peripheral_t *proc_buf = NULL; + int err = 0, total_len = 0; + + if (!buf || !client) { + pr_err("diag: Invalid pointers in %s", __func__); + return; + } + + total_len = sizeof(int) + len; + if (ext_hdr) + total_len += sizeof(int) + EXT_HDR_LEN; + + proc_buf = &client->buffers[data_source]; + mutex_lock(&proc_buf->buf_mutex); + mutex_lock(&proc_buf->health_mutex); + err = diag_dci_get_buffer(client, data_source, total_len); + if (err) { + if (err == -ENOMEM) + proc_buf->health.dropped_events++; + else + pr_err("diag: In %s, invalid packet\n", __func__); + mutex_unlock(&proc_buf->health_mutex); + mutex_unlock(&proc_buf->buf_mutex); + return; + } + + data_buffer = proc_buf->buf_curr; + + proc_buf->health.received_events++; + mutex_unlock(&proc_buf->health_mutex); + mutex_unlock(&proc_buf->buf_mutex); + + mutex_lock(&data_buffer->data_mutex); + if (ext_hdr) + copy_ext_hdr(data_buffer, ext_hdr); + + *(int *)(data_buffer->data + data_buffer->data_len) = DCI_EVENT_TYPE; + data_buffer->data_len += sizeof(int); + memcpy(data_buffer->data + data_buffer->data_len, buf, len); + data_buffer->data_len += len; + data_buffer->data_source = data_source; + mutex_unlock(&data_buffer->data_mutex); + +} + +void extract_dci_events(unsigned char *buf, int len, int data_source, + int token, void *ext_hdr) +{ + uint16_t event_id, event_id_packet, length, temp_len; + uint8_t payload_len, payload_len_field; + uint8_t timestamp[8] = {0}, timestamp_len; + unsigned char event_data[MAX_EVENT_SIZE]; + unsigned int total_event_len; + struct list_head *start, *temp; + struct diag_dci_client_tbl *entry = NULL; + + if (!buf) { + pr_err("diag: In %s buffer is NULL\n", __func__); + return; + } + /* + * 1 byte for event code and 2 bytes for the length field. + * The length field indicates the total length removing the cmd_code + * and the lenght field. The event parsing in that case should happen + * till the end. + */ + if (len < 3) { + pr_err("diag: In %s invalid len: %d\n", __func__, len); + return; + } + length = *(uint16_t *)(buf + 1); /* total length of event series */ + if ((length == 0) || (len != (length + 3))) { + pr_err("diag: Incoming dci event length: %d is invalid\n", + length); + return; + } + /* + * Move directly to the start of the event series. + * The event parsing should happen from start of event + * series till the end. + */ + temp_len = 3; + while (temp_len < length) { + event_id_packet = *(uint16_t *)(buf + temp_len); + event_id = event_id_packet & 0x0FFF; /* extract 12 bits */ + if (event_id_packet & 0x8000) { + /* The packet has the two smallest byte of the + * timestamp + */ + timestamp_len = 2; + } else { + /* The packet has the full timestamp. The first event + * will always have full timestamp. Save it in the + * timestamp buffer and use it for subsequent events if + * necessary. + */ + timestamp_len = 8; + if ((temp_len + timestamp_len + 2) <= len) + memcpy(timestamp, buf + temp_len + 2, + timestamp_len); + else { + pr_err("diag: Invalid length in %s, len: %d, temp_len: %d", + __func__, len, temp_len); + return; + } + } + /* 13th and 14th bit represent the payload length */ + if (((event_id_packet & 0x6000) >> 13) == 3) { + payload_len_field = 1; + if ((temp_len + timestamp_len + 3) <= len) { + payload_len = *(uint8_t *) + (buf + temp_len + 2 + timestamp_len); + } else { + pr_err("diag: Invalid length in %s, len: %d, temp_len: %d", + __func__, len, temp_len); + return; + } + if ((payload_len < (MAX_EVENT_SIZE - 13)) && + ((temp_len + timestamp_len + payload_len + 3) <= len)) { + /* + * Copy the payload length and the payload + * after skipping temp_len bytes for already + * parsed packet, timestamp_len for timestamp + * buffer, 2 bytes for event_id_packet. + */ + memcpy(event_data + 12, buf + temp_len + 2 + + timestamp_len, 1); + memcpy(event_data + 13, buf + temp_len + 2 + + timestamp_len + 1, payload_len); + } else { + pr_err("diag: event > %d, payload_len = %d, temp_len = %d\n", + (MAX_EVENT_SIZE - 13), payload_len, temp_len); + return; + } + } else { + payload_len_field = 0; + payload_len = (event_id_packet & 0x6000) >> 13; + /* + * Copy the payload after skipping temp_len bytes + * for already parsed packet, timestamp_len for + * timestamp buffer, 2 bytes for event_id_packet. + */ + if ((payload_len < (MAX_EVENT_SIZE - 12)) && + ((temp_len + timestamp_len + payload_len + 2) <= len)) + memcpy(event_data + 12, buf + temp_len + 2 + + timestamp_len, payload_len); + else { + pr_err("diag: event > %d, payload_len = %d, temp_len = %d\n", + (MAX_EVENT_SIZE - 12), payload_len, temp_len); + return; + } + } + + /* Before copying the data to userspace, check if we are still + * within the buffer limit. This is an error case, don't count + * it towards the health statistics. + * + * Here, the offset of 2 bytes(uint16_t) is for the + * event_id_packet length + */ + temp_len += sizeof(uint16_t) + timestamp_len + + payload_len_field + payload_len; + if (temp_len > len) { + pr_err("diag: Invalid length in %s, len: %d, read: %d", + __func__, len, temp_len); + return; + } + + /* 2 bytes for the event id & timestamp len is hard coded to 8, + as individual events have full timestamp */ + *(uint16_t *)(event_data) = 10 + + payload_len_field + payload_len; + *(uint16_t *)(event_data + 2) = event_id_packet & 0x7FFF; + memcpy(event_data + 4, timestamp, 8); + /* 2 bytes for the event length field which is added to + the event data */ + total_event_len = 2 + 10 + payload_len_field + payload_len; + /* parse through event mask tbl of each client and check mask */ + mutex_lock(&driver->dci_mutex); + list_for_each_safe(start, temp, &driver->dci_client_list) { + entry = list_entry(start, struct diag_dci_client_tbl, + track); + if (entry->client_info.token != token) + continue; + if (diag_dci_query_event_mask(entry, event_id)) { + /* copy to client buffer */ + copy_dci_event(event_data, total_event_len, + entry, data_source, ext_hdr); + } + } + mutex_unlock(&driver->dci_mutex); + } +} + +static void copy_dci_log(unsigned char *buf, int len, + struct diag_dci_client_tbl *client, int data_source, + void *ext_hdr) +{ + uint16_t log_length = 0; + struct diag_dci_buffer_t *data_buffer = NULL; + struct diag_dci_buf_peripheral_t *proc_buf = NULL; + int err = 0, total_len = 0; + + if (!buf || !client) { + pr_err("diag: Invalid pointers in %s", __func__); + return; + } + + log_length = *(uint16_t *)(buf + 2); + if (log_length > USHRT_MAX - 4) { + pr_err("diag: Integer overflow in %s, log_len: %d", + __func__, log_length); + return; + } + total_len = sizeof(int) + log_length; + if (ext_hdr) + total_len += sizeof(int) + EXT_HDR_LEN; + + /* Check if we are within the len. The check should include the + * first 4 bytes for the Log code(2) and the length bytes (2) + */ + if ((log_length + sizeof(uint16_t) + 2) > len) { + pr_err("diag: Invalid length in %s, log_len: %d, len: %d", + __func__, log_length, len); + return; + } + + proc_buf = &client->buffers[data_source]; + mutex_lock(&proc_buf->buf_mutex); + mutex_lock(&proc_buf->health_mutex); + err = diag_dci_get_buffer(client, data_source, total_len); + if (err) { + if (err == -ENOMEM) + proc_buf->health.dropped_logs++; + else + pr_err("diag: In %s, invalid packet\n", __func__); + mutex_unlock(&proc_buf->health_mutex); + mutex_unlock(&proc_buf->buf_mutex); + return; + } + + data_buffer = proc_buf->buf_curr; + proc_buf->health.received_logs++; + mutex_unlock(&proc_buf->health_mutex); + mutex_unlock(&proc_buf->buf_mutex); + + mutex_lock(&data_buffer->data_mutex); + if (!data_buffer->data) { + mutex_unlock(&data_buffer->data_mutex); + return; + } + if (ext_hdr) + copy_ext_hdr(data_buffer, ext_hdr); + + *(int *)(data_buffer->data + data_buffer->data_len) = DCI_LOG_TYPE; + data_buffer->data_len += sizeof(int); + memcpy(data_buffer->data + data_buffer->data_len, buf + sizeof(int), + log_length); + data_buffer->data_len += log_length; + data_buffer->data_source = data_source; + mutex_unlock(&data_buffer->data_mutex); +} + +void extract_dci_log(unsigned char *buf, int len, int data_source, int token, + void *ext_hdr) +{ + uint16_t log_code, read_bytes = 0; + struct list_head *start, *temp; + struct diag_dci_client_tbl *entry = NULL; + + if (!buf) { + pr_err("diag: In %s buffer is NULL\n", __func__); + return; + } + /* + * The first eight bytes for the incoming log packet contains + * Command code (2), the length of the packet (2), the length + * of the log (2) and log code (2) + */ + if (len < 8) { + pr_err("diag: In %s invalid len: %d\n", __func__, len); + return; + } + + log_code = *(uint16_t *)(buf + 6); + read_bytes += sizeof(uint16_t) + 6; + + /* parse through log mask table of each client and check mask */ + mutex_lock(&driver->dci_mutex); + list_for_each_safe(start, temp, &driver->dci_client_list) { + entry = list_entry(start, struct diag_dci_client_tbl, track); + if (entry->client_info.token != token) + continue; + if (diag_dci_query_log_mask(entry, log_code)) { + pr_debug("\t log code %x needed by client %d", + log_code, entry->client->tgid); + /* copy to client buffer */ + copy_dci_log(buf, len, entry, data_source, ext_hdr); + } + } + mutex_unlock(&driver->dci_mutex); +} + +void extract_dci_ext_pkt(unsigned char *buf, int len, int data_source, + int token) +{ + uint8_t version, pkt_cmd_code = 0; + unsigned char *pkt = NULL; + + if (!buf) { + pr_err("diag: In %s buffer is NULL\n", __func__); + return; + } + if (len < (EXT_HDR_LEN + sizeof(uint8_t))) { + pr_err("diag: In %s invalid len: %d\n", __func__, len); + return; + } + + version = *(uint8_t *)buf + 1; + if (version < EXT_HDR_VERSION) { + pr_err("diag: %s, Extended header with invalid version: %d\n", + __func__, version); + return; + } + + pkt = buf + EXT_HDR_LEN; + pkt_cmd_code = *(uint8_t *)pkt; + len -= EXT_HDR_LEN; + + switch (pkt_cmd_code) { + case LOG_CMD_CODE: + extract_dci_log(pkt, len, data_source, token, buf); + break; + case EVENT_CMD_CODE: + extract_dci_events(pkt, len, data_source, token, buf); + break; + default: + pr_err("diag: %s unsupported cmd_code: %d, data_source: %d\n", + __func__, pkt_cmd_code, data_source); + return; + } +} + +void diag_dci_channel_open_work(struct work_struct *work) +{ + int i, j; + char dirty_bits[16]; + uint8_t *client_log_mask_ptr; + uint8_t *log_mask_ptr; + int ret; + struct list_head *start, *temp; + struct diag_dci_client_tbl *entry = NULL; + + /* Update apps and peripheral(s) with the dci log and event masks */ + memset(dirty_bits, 0, 16 * sizeof(uint8_t)); + + /* + * From each log entry used by each client, determine + * which log entries in the cumulative logs that need + * to be updated on the peripheral. + */ + mutex_lock(&driver->dci_mutex); + list_for_each_safe(start, temp, &driver->dci_client_list) { + entry = list_entry(start, struct diag_dci_client_tbl, track); + if (entry->client_info.token != DCI_LOCAL_PROC) + continue; + client_log_mask_ptr = entry->dci_log_mask; + for (j = 0; j < 16; j++) { + if (*(client_log_mask_ptr+1)) + dirty_bits[j] = 1; + client_log_mask_ptr += 514; + } + } + mutex_unlock(&driver->dci_mutex); + + mutex_lock(&dci_log_mask_mutex); + /* Update the appropriate dirty bits in the cumulative mask */ + log_mask_ptr = dci_ops_tbl[DCI_LOCAL_PROC].log_mask_composite; + for (i = 0; i < 16; i++) { + if (dirty_bits[i]) + *(log_mask_ptr+1) = dirty_bits[i]; + + log_mask_ptr += 514; + } + mutex_unlock(&dci_log_mask_mutex); + + /* Send updated mask to userspace clients */ + diag_update_userspace_clients(DCI_LOG_MASKS_TYPE); + /* Send updated log mask to peripherals */ + ret = dci_ops_tbl[DCI_LOCAL_PROC].send_log_mask(DCI_LOCAL_PROC); + + /* Send updated event mask to userspace clients */ + diag_update_userspace_clients(DCI_EVENT_MASKS_TYPE); + /* Send updated event mask to peripheral */ + ret = dci_ops_tbl[DCI_LOCAL_PROC].send_event_mask(DCI_LOCAL_PROC); +} + +void diag_dci_notify_client(int peripheral_mask, int data, int proc) +{ + int stat = 0; + struct siginfo info; + struct list_head *start, *temp; + struct diag_dci_client_tbl *entry = NULL; + struct pid *pid_struct = NULL; + struct task_struct *dci_task = NULL; + + memset(&info, 0, sizeof(struct siginfo)); + info.si_code = SI_QUEUE; + info.si_int = (peripheral_mask | data); + if (data == DIAG_STATUS_OPEN) + dci_ops_tbl[proc].peripheral_status |= peripheral_mask; + else + dci_ops_tbl[proc].peripheral_status &= ~peripheral_mask; + + /* Notify the DCI process that the peripheral DCI Channel is up */ + mutex_lock(&driver->dci_mutex); + list_for_each_safe(start, temp, &driver->dci_client_list) { + entry = list_entry(start, struct diag_dci_client_tbl, track); + if (entry->client_info.token != proc) + continue; + if (entry->client_info.notification_list & peripheral_mask) { + info.si_signo = entry->client_info.signal_type; + pid_struct = find_get_pid(entry->tgid); + if (pid_struct) { + dci_task = get_pid_task(pid_struct, + PIDTYPE_PID); + if (!dci_task) { + DIAG_LOG(DIAG_DEBUG_PERIPHERALS, + "diag: dci client with pid = %d Exited..\n", + entry->tgid); + mutex_unlock(&driver->dci_mutex); + return; + } + if (entry->client && + entry->tgid == dci_task->tgid) { + DIAG_LOG(DIAG_DEBUG_DCI, + "entry tgid = %d, dci client tgid = %d\n", + entry->tgid, dci_task->tgid); + stat = send_sig_info( + entry->client_info.signal_type, + &info, dci_task); + if (stat) + pr_err("diag: Err sending dci signal to client, signal data: 0x%x, stat: %d\n", + info.si_int, stat); + } else + pr_err("diag: client data is corrupted, signal data: 0x%x, stat: %d\n", + info.si_int, stat); + } + } + } + mutex_unlock(&driver->dci_mutex); +} + +static int diag_send_dci_pkt(struct diag_cmd_reg_t *entry, + unsigned char *buf, int len, int tag) +{ + int i, status = DIAG_DCI_NO_ERROR; + uint32_t write_len = 0; + struct diag_dci_pkt_header_t header; + + if (!entry) + return -EIO; + + if (len < 1 || len > DIAG_MAX_REQ_SIZE) { + pr_err("diag: dci: In %s, invalid length %d, max_length: %d\n", + __func__, len, (int)(DCI_REQ_BUF_SIZE - sizeof(header))); + return -EIO; + } + + if ((len + sizeof(header) + sizeof(uint8_t)) > DCI_BUF_SIZE) { + pr_err("diag: dci: In %s, invalid length %d for apps_dci_buf, max_length: %d\n", + __func__, len, DIAG_MAX_REQ_SIZE); + return -EIO; + } + + mutex_lock(&driver->dci_mutex); + /* prepare DCI packet */ + header.start = CONTROL_CHAR; + header.version = 1; + header.len = len + sizeof(int) + sizeof(uint8_t); + header.pkt_code = DCI_PKT_RSP_CODE; + header.tag = tag; + memcpy(driver->apps_dci_buf, &header, sizeof(header)); + write_len += sizeof(header); + memcpy(driver->apps_dci_buf + write_len , buf, len); + write_len += len; + *(uint8_t *)(driver->apps_dci_buf + write_len) = CONTROL_CHAR; + write_len += sizeof(uint8_t); + + /* This command is registered locally on the Apps */ + if (entry->proc == APPS_DATA) { + diag_update_pkt_buffer(driver->apps_dci_buf, write_len, + DCI_PKT_TYPE); + diag_update_sleeping_process(entry->pid, DCI_PKT_TYPE); + mutex_unlock(&driver->dci_mutex); + return DIAG_DCI_NO_ERROR; + } + + for (i = 0; i < NUM_PERIPHERALS; i++) + if (entry->proc == i) { + status = 1; + break; + } + + if (status) { + status = diag_dci_write_proc(entry->proc, + DIAG_DATA_TYPE, + driver->apps_dci_buf, + write_len); + } else { + pr_err("diag: Cannot send packet to peripheral %d", + entry->proc); + status = DIAG_DCI_SEND_DATA_FAIL; + } + mutex_unlock(&driver->dci_mutex); + return status; +} + +#ifdef CONFIG_DIAGFWD_BRIDGE_CODE +unsigned char *dci_get_buffer_from_bridge(int token) +{ + uint8_t retries = 0, max_retries = 3; + unsigned char *buf = NULL; + + do { + buf = diagmem_alloc(driver, DIAG_MDM_BUF_SIZE, + dci_ops_tbl[token].mempool); + if (!buf) { + usleep_range(5000, 5100); + retries++; + } else + break; + } while (retries < max_retries); + + return buf; +} + +int diag_dci_write_bridge(int token, unsigned char *buf, int len) +{ + return diagfwd_bridge_write(TOKEN_TO_BRIDGE(token), buf, len); +} + +int diag_dci_write_done_bridge(int index, unsigned char *buf, int len) +{ + int token = BRIDGE_TO_TOKEN(index); + if (!VALID_DCI_TOKEN(token)) { + pr_err("diag: Invalid DCI token %d in %s\n", token, __func__); + return -EINVAL; + } + diagmem_free(driver, buf, dci_ops_tbl[token].mempool); + return 0; +} +#endif + +#ifdef CONFIG_DIAGFWD_BRIDGE_CODE +static int diag_send_dci_pkt_remote(unsigned char *data, int len, int tag, + int token) +{ + unsigned char *buf = NULL; + struct diag_dci_header_t dci_header; + int dci_header_size = sizeof(struct diag_dci_header_t); + int ret = DIAG_DCI_NO_ERROR; + uint32_t write_len = 0; + + if (!data) + return -EIO; + + buf = dci_get_buffer_from_bridge(token); + if (!buf) { + pr_err("diag: In %s, unable to get dci buffers to write data\n", + __func__); + return -EAGAIN; + } + + dci_header.start = CONTROL_CHAR; + dci_header.version = 1; + /* + * The Length of the DCI packet = length of the command + tag (int) + + * the command code size (uint8_t) + */ + dci_header.length = len + sizeof(int) + sizeof(uint8_t); + dci_header.cmd_code = DCI_PKT_RSP_CODE; + + memcpy(buf + write_len, &dci_header, dci_header_size); + write_len += dci_header_size; + *(int *)(buf + write_len) = tag; + write_len += sizeof(int); + memcpy(buf + write_len, data, len); + write_len += len; + *(buf + write_len) = CONTROL_CHAR; /* End Terminator */ + write_len += sizeof(uint8_t); + + ret = diag_dci_write_bridge(token, buf, write_len); + if (ret) { + pr_err("diag: error writing dci pkt to remote proc, token: %d, err: %d\n", + token, ret); + diagmem_free(driver, buf, dci_ops_tbl[token].mempool); + } else { + ret = DIAG_DCI_NO_ERROR; + } + + return ret; +} +#else +static int diag_send_dci_pkt_remote(unsigned char *data, int len, int tag, + int token) +{ + return DIAG_DCI_NO_ERROR; +} +#endif + +#ifdef CONFIG_DIAGFWD_BRIDGE_CODE +int diag_dci_send_handshake_pkt(int index) +{ + int err = 0; + int token = BRIDGE_TO_TOKEN(index); + int write_len = 0; + struct diag_ctrl_dci_handshake_pkt ctrl_pkt; + unsigned char *buf = NULL; + struct diag_dci_header_t dci_header; + + if (!VALID_DCI_TOKEN(token)) { + pr_err("diag: In %s, invalid DCI token %d\n", __func__, token); + return -EINVAL; + } + + buf = dci_get_buffer_from_bridge(token); + if (!buf) { + pr_err("diag: In %s, unable to get dci buffers to write data\n", + __func__); + return -EAGAIN; + } + + dci_header.start = CONTROL_CHAR; + dci_header.version = 1; + /* Include the cmd code (uint8_t) in the length */ + dci_header.length = sizeof(ctrl_pkt) + sizeof(uint8_t); + dci_header.cmd_code = DCI_CONTROL_PKT_CODE; + memcpy(buf, &dci_header, sizeof(dci_header)); + write_len += sizeof(dci_header); + + ctrl_pkt.ctrl_pkt_id = DIAG_CTRL_MSG_DCI_HANDSHAKE_PKT; + /* + * The control packet data length accounts for the version (uint32_t) + * of the packet and the magic number (uint32_t). + */ + ctrl_pkt.ctrl_pkt_data_len = 2 * sizeof(uint32_t); + ctrl_pkt.version = 1; + ctrl_pkt.magic = DCI_MAGIC; + memcpy(buf + write_len, &ctrl_pkt, sizeof(ctrl_pkt)); + write_len += sizeof(ctrl_pkt); + + *(uint8_t *)(buf + write_len) = CONTROL_CHAR; + write_len += sizeof(uint8_t); + + err = diag_dci_write_bridge(token, buf, write_len); + if (err) { + pr_err("diag: error writing ack packet to remote proc, token: %d, err: %d\n", + token, err); + diagmem_free(driver, buf, dci_ops_tbl[token].mempool); + return err; + } + + mod_timer(&(dci_channel_status[token].wait_time), + jiffies + msecs_to_jiffies(DCI_HANDSHAKE_WAIT_TIME)); + + return 0; +} +#else +int diag_dci_send_handshake_pkt(int index) +{ + return 0; +} +#endif + +static int diag_dci_process_apps_pkt(struct diag_pkt_header_t *pkt_header, + unsigned char *req_buf, int req_len, + int tag) +{ + uint8_t cmd_code, subsys_id, i, goto_download = 0; + uint8_t header_len = sizeof(struct diag_dci_pkt_header_t); + uint16_t ss_cmd_code; + uint32_t write_len = 0; + unsigned char *dest_buf = driver->apps_dci_buf; + unsigned char *payload_ptr = driver->apps_dci_buf + header_len; + struct diag_dci_pkt_header_t dci_header; + + if (!pkt_header || !req_buf || req_len <= 0 || tag < 0) + return -EIO; + + cmd_code = pkt_header->cmd_code; + subsys_id = pkt_header->subsys_id; + ss_cmd_code = pkt_header->subsys_cmd_code; + + if (cmd_code == DIAG_CMD_DOWNLOAD) { + *payload_ptr = DIAG_CMD_DOWNLOAD; + write_len = sizeof(uint8_t); + goto_download = 1; + goto fill_buffer; + } else if (cmd_code == DIAG_CMD_VERSION) { + if (chk_polling_response()) { + for (i = 0; i < 55; i++, write_len++, payload_ptr++) + *(payload_ptr) = 0; + goto fill_buffer; + } + } else if (cmd_code == DIAG_CMD_EXT_BUILD) { + if (chk_polling_response()) { + *payload_ptr = DIAG_CMD_EXT_BUILD; + write_len = sizeof(uint8_t); + payload_ptr += sizeof(uint8_t); + for (i = 0; i < 8; i++, write_len++, payload_ptr++) + *(payload_ptr) = 0; + *(int *)(payload_ptr) = chk_config_get_id(); + write_len += sizeof(int); + goto fill_buffer; + } + } else if (cmd_code == DIAG_CMD_LOG_ON_DMND) { + write_len = diag_cmd_log_on_demand(req_buf, req_len, + payload_ptr, + APPS_BUF_SIZE - header_len); + goto fill_buffer; + } else if (cmd_code != DIAG_CMD_DIAG_SUBSYS) { + return DIAG_DCI_TABLE_ERR; + } + + if (subsys_id == DIAG_SS_DIAG) { + if (ss_cmd_code == DIAG_DIAG_MAX_PKT_SZ) { + memcpy(payload_ptr, pkt_header, + sizeof(struct diag_pkt_header_t)); + write_len = sizeof(struct diag_pkt_header_t); + *(uint32_t *)(payload_ptr + write_len) = + DIAG_MAX_REQ_SIZE; + write_len += sizeof(uint32_t); + } else if (ss_cmd_code == DIAG_DIAG_STM) { + write_len = diag_process_stm_cmd(req_buf, payload_ptr); + } + } else if (subsys_id == DIAG_SS_PARAMS) { + if (ss_cmd_code == DIAG_DIAG_POLL) { + if (chk_polling_response()) { + memcpy(payload_ptr, pkt_header, + sizeof(struct diag_pkt_header_t)); + write_len = sizeof(struct diag_pkt_header_t); + payload_ptr += write_len; + for (i = 0; i < 12; i++, write_len++) { + *(payload_ptr) = 0; + payload_ptr++; + } + } + } else if (ss_cmd_code == DIAG_DEL_RSP_WRAP) { + memcpy(payload_ptr, pkt_header, + sizeof(struct diag_pkt_header_t)); + write_len = sizeof(struct diag_pkt_header_t); + *(int *)(payload_ptr + write_len) = wrap_enabled; + write_len += sizeof(int); + } else if (ss_cmd_code == DIAG_DEL_RSP_WRAP_CNT) { + wrap_enabled = true; + memcpy(payload_ptr, pkt_header, + sizeof(struct diag_pkt_header_t)); + write_len = sizeof(struct diag_pkt_header_t); + *(uint16_t *)(payload_ptr + write_len) = wrap_count; + write_len += sizeof(uint16_t); + } else if (ss_cmd_code == DIAG_EXT_MOBILE_ID) { + write_len = diag_cmd_get_mobile_id(req_buf, req_len, + payload_ptr, + APPS_BUF_SIZE - header_len); + } + } + +fill_buffer: + if (write_len > 0) { + /* Check if we are within the range of the buffer*/ + if (write_len + header_len > DIAG_MAX_REQ_SIZE) { + pr_err("diag: In %s, invalid length %d\n", __func__, + write_len + header_len); + return -ENOMEM; + } + dci_header.start = CONTROL_CHAR; + dci_header.version = 1; + /* + * Length of the rsp pkt = actual data len + pkt rsp code + * (uint8_t) + tag (int) + */ + dci_header.len = write_len + sizeof(uint8_t) + sizeof(int); + dci_header.pkt_code = DCI_PKT_RSP_CODE; + dci_header.tag = tag; + driver->in_busy_dcipktdata = 1; + memcpy(dest_buf, &dci_header, header_len); + diag_process_apps_dci_read_data(DCI_PKT_TYPE, dest_buf + 4, + dci_header.len); + driver->in_busy_dcipktdata = 0; + + if (goto_download) { + /* + * Sleep for sometime so that the response reaches the + * client. The value 5000 empirically as an optimum + * time for the response to reach the client. + */ + usleep_range(5000, 5100); + /* call download API */ + msm_set_restart_mode(RESTART_DLOAD); + pr_alert("diag: download mode set, Rebooting SoC..\n"); + kernel_restart(NULL); + } + return DIAG_DCI_NO_ERROR; + } + + return DIAG_DCI_TABLE_ERR; +} + +static int diag_process_dci_pkt_rsp(unsigned char *buf, int len) +{ + int ret = DIAG_DCI_TABLE_ERR; + int common_cmd = 0; + struct diag_pkt_header_t *header = NULL; + unsigned char *temp = buf; + unsigned char *req_buf = NULL; + uint8_t retry_count = 0, max_retries = 3; + uint32_t read_len = 0, req_len = len; + struct dci_pkt_req_entry_t *req_entry = NULL; + struct diag_dci_client_tbl *dci_entry = NULL; + struct dci_pkt_req_t req_hdr; + struct diag_cmd_reg_t *reg_item; + struct diag_cmd_reg_entry_t reg_entry; + struct diag_cmd_reg_entry_t *temp_entry; + + if (!buf) + return -EIO; + + if (len <= sizeof(struct dci_pkt_req_t) || len > DCI_REQ_BUF_SIZE) { + pr_err("diag: dci: Invalid length %d len in %s", len, __func__); + return -EIO; + } + + req_hdr = *(struct dci_pkt_req_t *)temp; + temp += sizeof(struct dci_pkt_req_t); + read_len += sizeof(struct dci_pkt_req_t); + req_len -= sizeof(struct dci_pkt_req_t); + req_buf = temp; /* Start of the Request */ + header = (struct diag_pkt_header_t *)temp; + temp += sizeof(struct diag_pkt_header_t); + read_len += sizeof(struct diag_pkt_header_t); + if (read_len >= DCI_REQ_BUF_SIZE) { + pr_err("diag: dci: In %s, invalid read_len: %d\n", __func__, + read_len); + return -EIO; + } + + mutex_lock(&driver->dci_mutex); + dci_entry = diag_dci_get_client_entry(req_hdr.client_id); + if (!dci_entry) { + pr_err("diag: Invalid client %d in %s\n", + req_hdr.client_id, __func__); + mutex_unlock(&driver->dci_mutex); + return DIAG_DCI_NO_REG; + } + + /* Check if the command is allowed on DCI */ + if (diag_dci_filter_commands(header)) { + pr_debug("diag: command not supported %d %d %d", + header->cmd_code, header->subsys_id, + header->subsys_cmd_code); + mutex_unlock(&driver->dci_mutex); + return DIAG_DCI_SEND_DATA_FAIL; + } + + common_cmd = diag_check_common_cmd(header); + if (common_cmd < 0) { + pr_debug("diag: error in checking common command, %d\n", + common_cmd); + mutex_unlock(&driver->dci_mutex); + return DIAG_DCI_SEND_DATA_FAIL; + } + + /* + * Previous packet is yet to be consumed by the client. Wait + * till the buffer is free. + */ + while (retry_count < max_retries) { + retry_count++; + if (driver->in_busy_dcipktdata) + usleep_range(10000, 10100); + else + break; + } + /* The buffer is still busy */ + if (driver->in_busy_dcipktdata) { + pr_err("diag: In %s, apps dci buffer is still busy. Dropping packet\n", + __func__); + mutex_unlock(&driver->dci_mutex); + return -EAGAIN; + } + + /* Register this new DCI packet */ + req_entry = diag_register_dci_transaction(req_hdr.uid, + req_hdr.client_id); + if (!req_entry) { + pr_alert("diag: registering new DCI transaction failed\n"); + mutex_unlock(&driver->dci_mutex); + return DIAG_DCI_NO_REG; + } + mutex_unlock(&driver->dci_mutex); + + /* + * If the client has registered for remote data, route the packet to the + * remote processor + */ + if (dci_entry->client_info.token > 0) { + ret = diag_send_dci_pkt_remote(req_buf, req_len, req_entry->tag, + dci_entry->client_info.token); + return ret; + } + + /* Check if it is a dedicated Apps command */ + ret = diag_dci_process_apps_pkt(header, req_buf, req_len, + req_entry->tag); + if ((ret == DIAG_DCI_NO_ERROR && !common_cmd) || ret < 0) + return ret; + + reg_entry.cmd_code = header->cmd_code; + reg_entry.subsys_id = header->subsys_id; + reg_entry.cmd_code_hi = header->subsys_cmd_code; + reg_entry.cmd_code_lo = header->subsys_cmd_code; + + mutex_lock(&driver->cmd_reg_mutex); + temp_entry = diag_cmd_search(®_entry, ALL_PROC); + if (temp_entry) { + reg_item = container_of(temp_entry, struct diag_cmd_reg_t, + entry); + ret = diag_send_dci_pkt(reg_item, req_buf, req_len, + req_entry->tag); + } else { + DIAG_LOG(DIAG_DEBUG_DCI, "Command not found: %02x %02x %02x\n", + reg_entry.cmd_code, reg_entry.subsys_id, + reg_entry.cmd_code_hi); + } + mutex_unlock(&driver->cmd_reg_mutex); + + return ret; +} + +int diag_process_dci_transaction(unsigned char *buf, int len) +{ + unsigned char *temp = buf; + uint16_t log_code, item_num; + int ret = -1, found = 0, client_id = 0, client_token = 0; + int count, set_mask, num_codes, bit_index, event_id, offset = 0; + unsigned int byte_index, read_len = 0; + uint8_t equip_id, *log_mask_ptr, *head_log_mask_ptr, byte_mask; + uint8_t *event_mask_ptr; + struct diag_dci_client_tbl *dci_entry = NULL; + + if (!temp) { + pr_err("diag: Invalid buffer in %s\n", __func__); + return -ENOMEM; + } + + /* This is Pkt request/response transaction */ + if (*(int *)temp > 0) { + return diag_process_dci_pkt_rsp(buf, len); + } else if (*(int *)temp == DCI_LOG_TYPE) { + /* Minimum length of a log mask config is 12 + 2 bytes for + atleast one log code to be set or reset */ + if (len < DCI_LOG_CON_MIN_LEN || len > USER_SPACE_DATA) { + pr_err("diag: dci: Invalid length in %s\n", __func__); + return -EIO; + } + + /* Extract each log code and put in client table */ + temp += sizeof(int); + read_len += sizeof(int); + client_id = *(int *)temp; + temp += sizeof(int); + read_len += sizeof(int); + set_mask = *(int *)temp; + temp += sizeof(int); + read_len += sizeof(int); + num_codes = *(int *)temp; + temp += sizeof(int); + read_len += sizeof(int); + + /* find client table entry */ + mutex_lock(&driver->dci_mutex); + dci_entry = diag_dci_get_client_entry(client_id); + if (!dci_entry) { + pr_err("diag: In %s, invalid client\n", __func__); + mutex_unlock(&driver->dci_mutex); + return ret; + } + client_token = dci_entry->client_info.token; + + if (num_codes == 0 || (num_codes >= (USER_SPACE_DATA - 8)/2)) { + pr_err("diag: dci: Invalid number of log codes %d\n", + num_codes); + mutex_unlock(&driver->dci_mutex); + return -EIO; + } + + head_log_mask_ptr = dci_entry->dci_log_mask; + if (!head_log_mask_ptr) { + pr_err("diag: dci: Invalid Log mask pointer in %s\n", + __func__); + mutex_unlock(&driver->dci_mutex); + return -ENOMEM; + } + pr_debug("diag: head of dci log mask %pK\n", head_log_mask_ptr); + count = 0; /* iterator for extracting log codes */ + + while (count < num_codes) { + if (read_len >= USER_SPACE_DATA) { + pr_err("diag: dci: Invalid length for log type in %s", + __func__); + mutex_unlock(&driver->dci_mutex); + return -EIO; + } + log_code = *(uint16_t *)temp; + equip_id = LOG_GET_EQUIP_ID(log_code); + item_num = LOG_GET_ITEM_NUM(log_code); + byte_index = item_num/8 + 2; + if (byte_index >= (DCI_MAX_ITEMS_PER_LOG_CODE+2)) { + pr_err("diag: dci: Log type, invalid byte index\n"); + mutex_unlock(&driver->dci_mutex); + return ret; + } + byte_mask = 0x01 << (item_num % 8); + /* + * Parse through log mask table and find + * relevant range + */ + log_mask_ptr = head_log_mask_ptr; + found = 0; + offset = 0; + while (log_mask_ptr && (offset < DCI_LOG_MASK_SIZE)) { + if (*log_mask_ptr == equip_id) { + found = 1; + pr_debug("diag: find equip id = %x at %pK\n", + equip_id, log_mask_ptr); + break; + } else { + pr_debug("diag: did not find equip id = %x at %d\n", + equip_id, *log_mask_ptr); + log_mask_ptr += 514; + offset += 514; + } + } + if (!found) { + pr_err("diag: dci equip id not found\n"); + mutex_unlock(&driver->dci_mutex); + return ret; + } + *(log_mask_ptr+1) = 1; /* set the dirty byte */ + log_mask_ptr = log_mask_ptr + byte_index; + if (set_mask) + *log_mask_ptr |= byte_mask; + else + *log_mask_ptr &= ~byte_mask; + /* add to cumulative mask */ + update_dci_cumulative_log_mask( + offset, byte_index, + byte_mask, client_token); + temp += 2; + read_len += 2; + count++; + ret = DIAG_DCI_NO_ERROR; + } + /* send updated mask to userspace clients */ + if (client_token == DCI_LOCAL_PROC) + diag_update_userspace_clients(DCI_LOG_MASKS_TYPE); + /* send updated mask to peripherals */ + ret = dci_ops_tbl[client_token].send_log_mask(client_token); + mutex_unlock(&driver->dci_mutex); + } else if (*(int *)temp == DCI_EVENT_TYPE) { + /* Minimum length of a event mask config is 12 + 4 bytes for + atleast one event id to be set or reset. */ + if (len < DCI_EVENT_CON_MIN_LEN || len > USER_SPACE_DATA) { + pr_err("diag: dci: Invalid length in %s\n", __func__); + return -EIO; + } + + /* Extract each event id and put in client table */ + temp += sizeof(int); + read_len += sizeof(int); + client_id = *(int *)temp; + temp += sizeof(int); + read_len += sizeof(int); + set_mask = *(int *)temp; + temp += sizeof(int); + read_len += sizeof(int); + num_codes = *(int *)temp; + temp += sizeof(int); + read_len += sizeof(int); + + /* find client table entry */ + mutex_lock(&driver->dci_mutex); + dci_entry = diag_dci_get_client_entry(client_id); + if (!dci_entry) { + pr_err("diag: In %s, invalid client\n", __func__); + mutex_unlock(&driver->dci_mutex); + return ret; + } + client_token = dci_entry->client_info.token; + + /* Check for positive number of event ids. Also, the number of + event ids should fit in the buffer along with set_mask and + num_codes which are 4 bytes each */ + if (num_codes == 0 || (num_codes >= (USER_SPACE_DATA - 8)/2)) { + pr_err("diag: dci: Invalid number of event ids %d\n", + num_codes); + mutex_unlock(&driver->dci_mutex); + return -EIO; + } + + event_mask_ptr = dci_entry->dci_event_mask; + if (!event_mask_ptr) { + pr_err("diag: dci: Invalid event mask pointer in %s\n", + __func__); + mutex_unlock(&driver->dci_mutex); + return -ENOMEM; + } + pr_debug("diag: head of dci event mask %pK\n", event_mask_ptr); + count = 0; /* iterator for extracting log codes */ + while (count < num_codes) { + if (read_len >= USER_SPACE_DATA) { + pr_err("diag: dci: Invalid length for event type in %s", + __func__); + mutex_unlock(&driver->dci_mutex); + return -EIO; + } + event_id = *(int *)temp; + byte_index = event_id/8; + if (byte_index >= DCI_EVENT_MASK_SIZE) { + pr_err("diag: dci: Event type, invalid byte index\n"); + mutex_unlock(&driver->dci_mutex); + return ret; + } + bit_index = event_id % 8; + byte_mask = 0x1 << bit_index; + /* + * Parse through event mask table and set + * relevant byte & bit combination + */ + if (set_mask) + *(event_mask_ptr + byte_index) |= byte_mask; + else + *(event_mask_ptr + byte_index) &= ~byte_mask; + /* add to cumulative mask */ + update_dci_cumulative_event_mask(byte_index, byte_mask, + client_token); + temp += sizeof(int); + read_len += sizeof(int); + count++; + ret = DIAG_DCI_NO_ERROR; + } + /* send updated mask to userspace clients */ + if (dci_entry->client_info.token == DCI_LOCAL_PROC) + diag_update_userspace_clients(DCI_EVENT_MASKS_TYPE); + /* send updated mask to peripherals */ + ret = dci_ops_tbl[client_token].send_event_mask(client_token); + mutex_unlock(&driver->dci_mutex); + } else { + pr_alert("diag: Incorrect DCI transaction\n"); + } + return ret; +} + + +struct diag_dci_client_tbl *diag_dci_get_client_entry(int client_id) +{ + struct list_head *start, *temp; + struct diag_dci_client_tbl *entry = NULL; + list_for_each_safe(start, temp, &driver->dci_client_list) { + entry = list_entry(start, struct diag_dci_client_tbl, track); + if (entry->client_info.client_id == client_id) + return entry; + } + return NULL; +} + +struct diag_dci_client_tbl *dci_lookup_client_entry_pid(int tgid) +{ + struct list_head *start, *temp; + struct diag_dci_client_tbl *entry = NULL; + struct pid *pid_struct = NULL; + struct task_struct *task_s = NULL; + + list_for_each_safe(start, temp, &driver->dci_client_list) { + entry = list_entry(start, struct diag_dci_client_tbl, track); + pid_struct = find_get_pid(entry->tgid); + if (!pid_struct) { + DIAG_LOG(DIAG_DEBUG_DCI, + "diag: valid pid doesn't exist for pid = %d\n", + entry->tgid); + continue; + } + task_s = get_pid_task(pid_struct, PIDTYPE_PID); + if (!task_s) { + DIAG_LOG(DIAG_DEBUG_DCI, + "diag: valid task doesn't exist for pid = %d\n", + entry->tgid); + continue; + } + if (task_s == entry->client) + if (entry->client->tgid == tgid) + return entry; + } + return NULL; +} + +void update_dci_cumulative_event_mask(int offset, uint8_t byte_mask, int token) +{ + uint8_t *event_mask_ptr, *update_ptr = NULL; + struct list_head *start, *temp; + struct diag_dci_client_tbl *entry = NULL; + bool is_set = false; + + mutex_lock(&dci_event_mask_mutex); + update_ptr = dci_ops_tbl[token].event_mask_composite; + if (!update_ptr) { + mutex_unlock(&dci_event_mask_mutex); + return; + } + update_ptr += offset; + list_for_each_safe(start, temp, &driver->dci_client_list) { + entry = list_entry(start, struct diag_dci_client_tbl, track); + if (entry->client_info.token != token) + continue; + event_mask_ptr = entry->dci_event_mask; + event_mask_ptr += offset; + if ((*event_mask_ptr & byte_mask) == byte_mask) { + is_set = true; + /* break even if one client has the event mask set */ + break; + } + } + if (is_set == false) + *update_ptr &= ~byte_mask; + else + *update_ptr |= byte_mask; + mutex_unlock(&dci_event_mask_mutex); +} + +void diag_dci_invalidate_cumulative_event_mask(int token) +{ + int i = 0; + struct list_head *start, *temp; + struct diag_dci_client_tbl *entry = NULL; + uint8_t *event_mask_ptr, *update_ptr = NULL; + + mutex_lock(&dci_event_mask_mutex); + update_ptr = dci_ops_tbl[token].event_mask_composite; + if (!update_ptr) { + mutex_unlock(&dci_event_mask_mutex); + return; + } + + create_dci_event_mask_tbl(update_ptr); + list_for_each_safe(start, temp, &driver->dci_client_list) { + entry = list_entry(start, struct diag_dci_client_tbl, track); + if (entry->client_info.token != token) + continue; + event_mask_ptr = entry->dci_event_mask; + for (i = 0; i < DCI_EVENT_MASK_SIZE; i++) + *(update_ptr+i) |= *(event_mask_ptr+i); + } + mutex_unlock(&dci_event_mask_mutex); +} + +#ifdef CONFIG_DIAGFWD_BRIDGE_CODE +int diag_send_dci_event_mask_remote(int token) +{ + unsigned char *buf = NULL; + struct diag_dci_header_t dci_header; + struct diag_ctrl_event_mask event_mask; + int dci_header_size = sizeof(struct diag_dci_header_t); + int event_header_size = sizeof(struct diag_ctrl_event_mask); + int i, ret = DIAG_DCI_NO_ERROR, err = DIAG_DCI_NO_ERROR; + unsigned char *event_mask_ptr = NULL; + uint32_t write_len = 0; + + mutex_lock(&dci_event_mask_mutex); + event_mask_ptr = dci_ops_tbl[token].event_mask_composite; + if (!event_mask_ptr) { + mutex_unlock(&dci_event_mask_mutex); + return -EINVAL; + } + buf = dci_get_buffer_from_bridge(token); + if (!buf) { + pr_err("diag: In %s, unable to get dci buffers to write data\n", + __func__); + mutex_unlock(&dci_event_mask_mutex); + return -EAGAIN; + } + + /* Frame the DCI header */ + dci_header.start = CONTROL_CHAR; + dci_header.version = 1; + dci_header.length = event_header_size + DCI_EVENT_MASK_SIZE + 1; + dci_header.cmd_code = DCI_CONTROL_PKT_CODE; + + event_mask.cmd_type = DIAG_CTRL_MSG_EVENT_MASK; + event_mask.data_len = EVENT_MASK_CTRL_HEADER_LEN + DCI_EVENT_MASK_SIZE; + event_mask.stream_id = DCI_MASK_STREAM; + event_mask.status = DIAG_CTRL_MASK_VALID; + event_mask.event_config = 0; /* event config */ + event_mask.event_mask_size = DCI_EVENT_MASK_SIZE; + for (i = 0; i < DCI_EVENT_MASK_SIZE; i++) { + if (event_mask_ptr[i] != 0) { + event_mask.event_config = 1; + break; + } + } + memcpy(buf + write_len, &dci_header, dci_header_size); + write_len += dci_header_size; + memcpy(buf + write_len, &event_mask, event_header_size); + write_len += event_header_size; + memcpy(buf + write_len, event_mask_ptr, DCI_EVENT_MASK_SIZE); + write_len += DCI_EVENT_MASK_SIZE; + *(buf + write_len) = CONTROL_CHAR; /* End Terminator */ + write_len += sizeof(uint8_t); + err = diag_dci_write_bridge(token, buf, write_len); + if (err) { + pr_err("diag: error writing event mask to remote proc, token: %d, err: %d\n", + token, err); + diagmem_free(driver, buf, dci_ops_tbl[token].mempool); + ret = err; + } else { + ret = DIAG_DCI_NO_ERROR; + } + mutex_unlock(&dci_event_mask_mutex); + return ret; +} +#endif + +int diag_send_dci_event_mask(int token) +{ + void *buf = event_mask.update_buf; + struct diag_ctrl_event_mask header; + int header_size = sizeof(struct diag_ctrl_event_mask); + int ret = DIAG_DCI_NO_ERROR, err = DIAG_DCI_NO_ERROR, i; + unsigned char *event_mask_ptr = NULL; + + mutex_lock(&dci_event_mask_mutex); + event_mask_ptr = dci_ops_tbl[DCI_LOCAL_PROC].event_mask_composite; + if (!event_mask_ptr) { + mutex_unlock(&dci_event_mask_mutex); + return -EINVAL; + } + + mutex_lock(&event_mask.lock); + /* send event mask update */ + header.cmd_type = DIAG_CTRL_MSG_EVENT_MASK; + header.data_len = EVENT_MASK_CTRL_HEADER_LEN + DCI_EVENT_MASK_SIZE; + header.stream_id = DCI_MASK_STREAM; + header.status = DIAG_CTRL_MASK_VALID; + header.event_config = 0; /* event config */ + header.event_mask_size = DCI_EVENT_MASK_SIZE; + for (i = 0; i < DCI_EVENT_MASK_SIZE; i++) { + if (event_mask_ptr[i] != 0) { + header.event_config = 1; + break; + } + } + memcpy(buf, &header, header_size); + memcpy(buf+header_size, event_mask_ptr, DCI_EVENT_MASK_SIZE); + for (i = 0; i < NUM_PERIPHERALS; i++) { + /* + * Don't send to peripheral if its regular channel + * is down. It may also mean that the peripheral doesn't + * support DCI. + */ + if (check_peripheral_dci_support(i, DCI_LOCAL_PROC)) { + err = diag_dci_write_proc(i, DIAG_CNTL_TYPE, buf, + header_size + DCI_EVENT_MASK_SIZE); + if (err != DIAG_DCI_NO_ERROR) + ret = DIAG_DCI_SEND_DATA_FAIL; + } + } + + mutex_unlock(&event_mask.lock); + mutex_unlock(&dci_event_mask_mutex); + + return ret; +} + +void update_dci_cumulative_log_mask(int offset, unsigned int byte_index, + uint8_t byte_mask, int token) +{ + uint8_t *log_mask_ptr, *update_ptr = NULL; + bool is_set = false; + struct list_head *start, *temp; + struct diag_dci_client_tbl *entry = NULL; + + mutex_lock(&dci_log_mask_mutex); + update_ptr = dci_ops_tbl[token].log_mask_composite; + if (!update_ptr) { + mutex_unlock(&dci_log_mask_mutex); + return; + } + + update_ptr += offset; + /* update the dirty bit */ + *(update_ptr+1) = 1; + update_ptr = update_ptr + byte_index; + list_for_each_safe(start, temp, &driver->dci_client_list) { + entry = list_entry(start, struct diag_dci_client_tbl, track); + if (entry->client_info.token != token) + continue; + log_mask_ptr = entry->dci_log_mask; + log_mask_ptr = log_mask_ptr + offset + byte_index; + if ((*log_mask_ptr & byte_mask) == byte_mask) { + is_set = true; + /* break even if one client has the log mask set */ + break; + } + } + + if (is_set == false) + *update_ptr &= ~byte_mask; + else + *update_ptr |= byte_mask; + mutex_unlock(&dci_log_mask_mutex); +} + +void diag_dci_invalidate_cumulative_log_mask(int token) +{ + int i = 0; + struct list_head *start, *temp; + struct diag_dci_client_tbl *entry = NULL; + uint8_t *log_mask_ptr, *update_ptr = NULL; + + /* Clear the composite mask and redo all the masks */ + mutex_lock(&dci_log_mask_mutex); + update_ptr = dci_ops_tbl[token].log_mask_composite; + if (!update_ptr) { + mutex_unlock(&dci_log_mask_mutex); + return; + } + + create_dci_log_mask_tbl(update_ptr, DCI_LOG_MASK_DIRTY); + list_for_each_safe(start, temp, &driver->dci_client_list) { + entry = list_entry(start, struct diag_dci_client_tbl, track); + if (entry->client_info.token != token) + continue; + log_mask_ptr = entry->dci_log_mask; + for (i = 0; i < DCI_LOG_MASK_SIZE; i++) + *(update_ptr+i) |= *(log_mask_ptr+i); + } + mutex_unlock(&dci_log_mask_mutex); +} + +static int dci_fill_log_mask(unsigned char *dest_ptr, unsigned char *src_ptr) +{ + struct diag_ctrl_log_mask header; + int header_len = sizeof(struct diag_ctrl_log_mask); + + header.cmd_type = DIAG_CTRL_MSG_LOG_MASK; + header.num_items = DCI_MAX_ITEMS_PER_LOG_CODE; + header.data_len = 11 + DCI_MAX_ITEMS_PER_LOG_CODE; + header.stream_id = DCI_MASK_STREAM; + header.status = 3; + header.equip_id = *src_ptr; + header.log_mask_size = DCI_MAX_ITEMS_PER_LOG_CODE; + memcpy(dest_ptr, &header, header_len); + memcpy(dest_ptr + header_len, src_ptr + 2, DCI_MAX_ITEMS_PER_LOG_CODE); + + return header_len + DCI_MAX_ITEMS_PER_LOG_CODE; +} + +#ifdef CONFIG_DIAGFWD_BRIDGE_CODE +int diag_send_dci_log_mask_remote(int token) +{ + + unsigned char *buf = NULL; + struct diag_dci_header_t dci_header; + int dci_header_size = sizeof(struct diag_dci_header_t); + int log_header_size = sizeof(struct diag_ctrl_log_mask); + uint8_t *log_mask_ptr = NULL; + int i, ret = DIAG_DCI_NO_ERROR, err = DIAG_DCI_NO_ERROR; + int updated; + uint32_t write_len = 0; + + mutex_lock(&dci_log_mask_mutex); + log_mask_ptr = dci_ops_tbl[token].log_mask_composite; + if (!log_mask_ptr) { + mutex_unlock(&dci_log_mask_mutex); + return -EINVAL; + } + + /* DCI header is common to all equipment IDs */ + dci_header.start = CONTROL_CHAR; + dci_header.version = 1; + dci_header.length = log_header_size + DCI_MAX_ITEMS_PER_LOG_CODE + 1; + dci_header.cmd_code = DCI_CONTROL_PKT_CODE; + + for (i = 0; i < DCI_MAX_LOG_CODES; i++) { + updated = 1; + write_len = 0; + if (!*(log_mask_ptr + 1)) { + log_mask_ptr += 514; + continue; + } + + buf = dci_get_buffer_from_bridge(token); + if (!buf) { + pr_err("diag: In %s, unable to get dci buffers to write data\n", + __func__); + mutex_unlock(&dci_log_mask_mutex); + return -EAGAIN; + } + + memcpy(buf + write_len, &dci_header, dci_header_size); + write_len += dci_header_size; + write_len += dci_fill_log_mask(buf + write_len, log_mask_ptr); + *(buf + write_len) = CONTROL_CHAR; /* End Terminator */ + write_len += sizeof(uint8_t); + err = diag_dci_write_bridge(token, buf, write_len); + if (err) { + pr_err("diag: error writing log mask to remote processor, equip_id: %d, token: %d, err: %d\n", + i, token, err); + diagmem_free(driver, buf, dci_ops_tbl[token].mempool); + updated = 0; + } + if (updated) + *(log_mask_ptr + 1) = 0; /* clear dirty byte */ + log_mask_ptr += 514; + } + mutex_unlock(&dci_log_mask_mutex); + return ret; +} +#endif + +int diag_send_dci_log_mask(int token) +{ + void *buf = log_mask.update_buf; + int write_len = 0; + uint8_t *log_mask_ptr = NULL; + int i, j, ret = DIAG_DCI_NO_ERROR, err = DIAG_DCI_NO_ERROR; + int updated; + + + mutex_lock(&dci_log_mask_mutex); + log_mask_ptr = dci_ops_tbl[DCI_LOCAL_PROC].log_mask_composite; + if (!log_mask_ptr) { + mutex_unlock(&dci_log_mask_mutex); + return -EINVAL; + } + + mutex_lock(&log_mask.lock); + for (i = 0; i < 16; i++) { + updated = 1; + /* Dirty bit is set don't update the mask for this equip id */ + if (!(*(log_mask_ptr + 1))) { + log_mask_ptr += 514; + continue; + } + write_len = dci_fill_log_mask(buf, log_mask_ptr); + for (j = 0; j < NUM_PERIPHERALS && write_len; j++) { + if (check_peripheral_dci_support(j, DCI_LOCAL_PROC)) { + err = diag_dci_write_proc(j, DIAG_CNTL_TYPE, + buf, write_len); + if (err != DIAG_DCI_NO_ERROR) { + updated = 0; + ret = DIAG_DCI_SEND_DATA_FAIL; + } + } + } + if (updated) + *(log_mask_ptr+1) = 0; /* clear dirty byte */ + log_mask_ptr += 514; + } + mutex_unlock(&log_mask.lock); + mutex_unlock(&dci_log_mask_mutex); + return ret; +} + +static int diag_dci_init_local(void) +{ + struct dci_ops_tbl_t *temp = &dci_ops_tbl[DCI_LOCAL_PROC]; + + create_dci_log_mask_tbl(temp->log_mask_composite, DCI_LOG_MASK_CLEAN); + create_dci_event_mask_tbl(temp->event_mask_composite); + temp->peripheral_status |= DIAG_CON_APSS; + + return 0; +} + +#ifdef CONFIG_DIAGFWD_BRIDGE_CODE +static void diag_dci_init_handshake_remote(void) +{ + int i; + struct dci_channel_status_t *temp = NULL; + + for (i = DCI_REMOTE_BASE; i < NUM_DCI_PROC; i++) { + temp = &dci_channel_status[i]; + temp->id = i; + setup_timer(&temp->wait_time, dci_chk_handshake, i); + INIT_WORK(&temp->handshake_work, dci_handshake_work_fn); + } +} + +static int diag_dci_init_remote(void) +{ + int i; + struct dci_ops_tbl_t *temp = NULL; + + diagmem_init(driver, POOL_TYPE_MDM_DCI_WRITE); + + for (i = DCI_REMOTE_BASE; i < DCI_REMOTE_LAST; i++) { + temp = &dci_ops_tbl[i]; + create_dci_log_mask_tbl(temp->log_mask_composite, + DCI_LOG_MASK_CLEAN); + create_dci_event_mask_tbl(temp->event_mask_composite); + } + + partial_pkt.data = vzalloc(MAX_DCI_PACKET_SZ); + if (!partial_pkt.data) { + pr_err("diag: Unable to create partial pkt data\n"); + return -ENOMEM; + } + + partial_pkt.total_len = 0; + partial_pkt.read_len = 0; + partial_pkt.remaining = 0; + partial_pkt.processing = 0; + + diag_dci_init_handshake_remote(); + + return 0; +} +#else +static int diag_dci_init_remote(void) +{ + return 0; +} +#endif + +static int diag_dci_init_ops_tbl(void) +{ + int err = 0; + + err = diag_dci_init_local(); + if (err) + goto err; + err = diag_dci_init_remote(); + if (err) + goto err; + + return 0; + +err: + return -ENOMEM; +} + +int diag_dci_init(void) +{ + int ret = 0; + + driver->dci_tag = 0; + driver->dci_client_id = 0; + driver->num_dci_client = 0; + mutex_init(&driver->dci_mutex); + mutex_init(&dci_log_mask_mutex); + mutex_init(&dci_event_mask_mutex); + spin_lock_init(&ws_lock); + + ret = diag_dci_init_ops_tbl(); + if (ret) + goto err; + + if (driver->apps_dci_buf == NULL) { + driver->apps_dci_buf = vzalloc(DCI_BUF_SIZE); + if (driver->apps_dci_buf == NULL) + goto err; + } + INIT_LIST_HEAD(&driver->dci_client_list); + INIT_LIST_HEAD(&driver->dci_req_list); + + driver->diag_dci_wq = create_singlethread_workqueue("diag_dci_wq"); + if (!driver->diag_dci_wq) + goto err; + + INIT_WORK(&dci_data_drain_work, dci_data_drain_work_fn); + + setup_timer(&dci_drain_timer, dci_drain_data, 0); + return DIAG_DCI_NO_ERROR; +err: + pr_err("diag: Could not initialize diag DCI buffers"); + vfree(driver->apps_dci_buf); + driver->apps_dci_buf = NULL; + + if (driver->diag_dci_wq) + destroy_workqueue(driver->diag_dci_wq); + vfree(partial_pkt.data); + partial_pkt.data = NULL; + mutex_destroy(&driver->dci_mutex); + mutex_destroy(&dci_log_mask_mutex); + mutex_destroy(&dci_event_mask_mutex); + return DIAG_DCI_NO_REG; +} + +void diag_dci_channel_init(void) +{ + uint8_t peripheral; + + for (peripheral = 0; peripheral < NUM_PERIPHERALS; peripheral++) { + diagfwd_open(peripheral, TYPE_DCI); + diagfwd_open(peripheral, TYPE_DCI_CMD); + } +} + +void diag_dci_exit(void) +{ + vfree(partial_pkt.data); + partial_pkt.data = NULL; + vfree(driver->apps_dci_buf); + driver->apps_dci_buf = NULL; + mutex_destroy(&driver->dci_mutex); + mutex_destroy(&dci_log_mask_mutex); + mutex_destroy(&dci_event_mask_mutex); + destroy_workqueue(driver->diag_dci_wq); +} + +int diag_dci_clear_log_mask(int client_id) +{ + int err = DIAG_DCI_NO_ERROR, token = DCI_LOCAL_PROC; + uint8_t *update_ptr; + struct diag_dci_client_tbl *entry = NULL; + + entry = diag_dci_get_client_entry(client_id); + if (!entry) { + pr_err("diag: In %s, invalid client entry\n", __func__); + return DIAG_DCI_TABLE_ERR; + } + token = entry->client_info.token; + update_ptr = dci_ops_tbl[token].log_mask_composite; + + create_dci_log_mask_tbl(entry->dci_log_mask, DCI_LOG_MASK_CLEAN); + diag_dci_invalidate_cumulative_log_mask(token); + + /* + * Send updated mask to userspace clients only if the client + * is registered on the local processor + */ + if (token == DCI_LOCAL_PROC) + diag_update_userspace_clients(DCI_LOG_MASKS_TYPE); + /* Send updated mask to peripherals */ + err = dci_ops_tbl[token].send_log_mask(token); + return err; +} + +int diag_dci_clear_event_mask(int client_id) +{ + int err = DIAG_DCI_NO_ERROR, token = DCI_LOCAL_PROC; + uint8_t *update_ptr; + struct diag_dci_client_tbl *entry = NULL; + + entry = diag_dci_get_client_entry(client_id); + if (!entry) { + pr_err("diag: In %s, invalid client entry\n", __func__); + return DIAG_DCI_TABLE_ERR; + } + token = entry->client_info.token; + update_ptr = dci_ops_tbl[token].event_mask_composite; + + create_dci_event_mask_tbl(entry->dci_event_mask); + diag_dci_invalidate_cumulative_event_mask(token); + + /* + * Send updated mask to userspace clients only if the client is + * registerted on the local processor + */ + if (token == DCI_LOCAL_PROC) + diag_update_userspace_clients(DCI_EVENT_MASKS_TYPE); + /* Send updated mask to peripherals */ + err = dci_ops_tbl[token].send_event_mask(token); + return err; +} + +uint8_t diag_dci_get_cumulative_real_time(int token) +{ + uint8_t real_time = MODE_NONREALTIME; + struct list_head *start, *temp; + struct diag_dci_client_tbl *entry = NULL; + + list_for_each_safe(start, temp, &driver->dci_client_list) { + entry = list_entry(start, struct diag_dci_client_tbl, track); + if (entry->real_time == MODE_REALTIME && + entry->client_info.token == token) { + real_time = 1; + break; + } + } + return real_time; +} + +int diag_dci_set_real_time(struct diag_dci_client_tbl *entry, uint8_t real_time) +{ + if (!entry) { + pr_err("diag: In %s, invalid client entry\n", __func__); + return 0; + } + entry->real_time = real_time; + return 1; +} + +int diag_dci_register_client(struct diag_dci_reg_tbl_t *reg_entry) +{ + int i, err = 0; + struct diag_dci_client_tbl *new_entry = NULL; + struct diag_dci_buf_peripheral_t *proc_buf = NULL; + + if (!reg_entry) + return DIAG_DCI_NO_REG; + if (!VALID_DCI_TOKEN(reg_entry->token)) { + pr_alert("diag: Invalid DCI client token, %d\n", + reg_entry->token); + return DIAG_DCI_NO_REG; + } + + if (driver->dci_state == DIAG_DCI_NO_REG) + return DIAG_DCI_NO_REG; + + if (driver->num_dci_client >= MAX_DCI_CLIENTS) + return DIAG_DCI_NO_REG; + + new_entry = kzalloc(sizeof(struct diag_dci_client_tbl), GFP_KERNEL); + if (new_entry == NULL) { + pr_err("diag: unable to alloc memory\n"); + return DIAG_DCI_NO_REG; + } + + mutex_lock(&driver->dci_mutex); + + new_entry->client = current; + new_entry->tgid = current->tgid; + new_entry->client_info.notification_list = + reg_entry->notification_list; + new_entry->client_info.signal_type = + reg_entry->signal_type; + new_entry->client_info.token = reg_entry->token; + switch (reg_entry->token) { + case DCI_LOCAL_PROC: + new_entry->num_buffers = NUM_DCI_PERIPHERALS; + break; + case DCI_MDM_PROC: + new_entry->num_buffers = 1; + break; + } + + new_entry->buffers = NULL; + new_entry->real_time = MODE_REALTIME; + new_entry->in_service = 0; + INIT_LIST_HEAD(&new_entry->list_write_buf); + mutex_init(&new_entry->write_buf_mutex); + new_entry->dci_log_mask = vzalloc(DCI_LOG_MASK_SIZE); + if (!new_entry->dci_log_mask) { + pr_err("diag: Unable to create log mask for client, %d", + driver->dci_client_id); + goto fail_alloc; + } + create_dci_log_mask_tbl(new_entry->dci_log_mask, DCI_LOG_MASK_CLEAN); + + new_entry->dci_event_mask = vzalloc(DCI_EVENT_MASK_SIZE); + if (!new_entry->dci_event_mask) { + pr_err("diag: Unable to create event mask for client, %d", + driver->dci_client_id); + goto fail_alloc; + } + create_dci_event_mask_tbl(new_entry->dci_event_mask); + + new_entry->buffers = kzalloc(new_entry->num_buffers * + sizeof(struct diag_dci_buf_peripheral_t), + GFP_KERNEL); + if (!new_entry->buffers) { + pr_err("diag: Unable to allocate buffers for peripherals in %s\n", + __func__); + goto fail_alloc; + } + + for (i = 0; i < new_entry->num_buffers; i++) { + proc_buf = &new_entry->buffers[i]; + if (!proc_buf) + goto fail_alloc; + + mutex_init(&proc_buf->health_mutex); + mutex_init(&proc_buf->buf_mutex); + proc_buf->health.dropped_events = 0; + proc_buf->health.dropped_logs = 0; + proc_buf->health.received_events = 0; + proc_buf->health.received_logs = 0; + proc_buf->buf_primary = kzalloc( + sizeof(struct diag_dci_buffer_t), + GFP_KERNEL); + if (!proc_buf->buf_primary) + goto fail_alloc; + proc_buf->buf_cmd = kzalloc(sizeof(struct diag_dci_buffer_t), + GFP_KERNEL); + if (!proc_buf->buf_cmd) + goto fail_alloc; + err = diag_dci_init_buffer(proc_buf->buf_primary, + DCI_BUF_PRIMARY); + if (err) + goto fail_alloc; + err = diag_dci_init_buffer(proc_buf->buf_cmd, DCI_BUF_CMD); + if (err) + goto fail_alloc; + proc_buf->buf_curr = proc_buf->buf_primary; + } + + list_add_tail(&new_entry->track, &driver->dci_client_list); + driver->dci_client_id++; + new_entry->client_info.client_id = driver->dci_client_id; + reg_entry->client_id = driver->dci_client_id; + driver->num_dci_client++; + if (driver->num_dci_client == 1) + diag_update_proc_vote(DIAG_PROC_DCI, VOTE_UP, reg_entry->token); + queue_work(driver->diag_real_time_wq, &driver->diag_real_time_work); + mutex_unlock(&driver->dci_mutex); + + return driver->dci_client_id; + +fail_alloc: + if (new_entry) { + for (i = 0; ((i < new_entry->num_buffers) && + new_entry->buffers); i++) { + proc_buf = &new_entry->buffers[i]; + if (proc_buf) { + mutex_destroy(&proc_buf->health_mutex); + if (proc_buf->buf_primary) { + vfree(proc_buf->buf_primary->data); + proc_buf->buf_primary->data = NULL; + mutex_destroy( + &proc_buf->buf_primary->data_mutex); + } + kfree(proc_buf->buf_primary); + proc_buf->buf_primary = NULL; + if (proc_buf->buf_cmd) { + vfree(proc_buf->buf_cmd->data); + proc_buf->buf_cmd->data = NULL; + mutex_destroy( + &proc_buf->buf_cmd->data_mutex); + } + kfree(proc_buf->buf_cmd); + proc_buf->buf_cmd = NULL; + } + } + vfree(new_entry->dci_event_mask); + new_entry->dci_event_mask = NULL; + vfree(new_entry->dci_log_mask); + new_entry->dci_log_mask = NULL; + kfree(new_entry->buffers); + new_entry->buffers = NULL; + kfree(new_entry); + new_entry = NULL; + } + mutex_unlock(&driver->dci_mutex); + return DIAG_DCI_NO_REG; +} + +int diag_dci_deinit_client(struct diag_dci_client_tbl *entry) +{ + int ret = DIAG_DCI_NO_ERROR, real_time = MODE_REALTIME, i, peripheral; + struct diag_dci_buf_peripheral_t *proc_buf = NULL; + struct diag_dci_buffer_t *buf_entry, *temp; + struct list_head *start, *req_temp; + struct dci_pkt_req_entry_t *req_entry = NULL; + int token = DCI_LOCAL_PROC; + + if (!entry) + return DIAG_DCI_NOT_SUPPORTED; + + token = entry->client_info.token; + /* + * Remove the entry from the list before freeing the buffers + * to ensure that we don't have any invalid access. + */ + if (!list_empty(&entry->track)) + list_del(&entry->track); + driver->num_dci_client--; + /* + * Clear the client's log and event masks, update the cumulative + * masks and send the masks to peripherals + */ + vfree(entry->dci_log_mask); + entry->dci_log_mask = NULL; + diag_dci_invalidate_cumulative_log_mask(token); + if (token == DCI_LOCAL_PROC) + diag_update_userspace_clients(DCI_LOG_MASKS_TYPE); + ret = dci_ops_tbl[token].send_log_mask(token); + if (ret != DIAG_DCI_NO_ERROR) { + return ret; + } + vfree(entry->dci_event_mask); + entry->dci_event_mask = NULL; + diag_dci_invalidate_cumulative_event_mask(token); + if (token == DCI_LOCAL_PROC) + diag_update_userspace_clients(DCI_EVENT_MASKS_TYPE); + ret = dci_ops_tbl[token].send_event_mask(token); + if (ret != DIAG_DCI_NO_ERROR) { + return ret; + } + + list_for_each_safe(start, req_temp, &driver->dci_req_list) { + req_entry = list_entry(start, struct dci_pkt_req_entry_t, + track); + if (req_entry->client_id == entry->client_info.client_id) { + if (!list_empty(&req_entry->track)) + list_del(&req_entry->track); + kfree(req_entry); + req_entry = NULL; + } + } + + /* Clean up any buffer that is pending write */ + mutex_lock(&entry->write_buf_mutex); + list_for_each_entry_safe(buf_entry, temp, &entry->list_write_buf, + buf_track) { + if (!list_empty(&buf_entry->buf_track)) + list_del(&buf_entry->buf_track); + if (buf_entry->buf_type == DCI_BUF_SECONDARY) { + mutex_lock(&buf_entry->data_mutex); + diagmem_free(driver, buf_entry->data, POOL_TYPE_DCI); + buf_entry->data = NULL; + mutex_unlock(&buf_entry->data_mutex); + kfree(buf_entry); + buf_entry = NULL; + } else if (buf_entry->buf_type == DCI_BUF_CMD) { + peripheral = buf_entry->data_source; + if (peripheral == APPS_DATA) + continue; + } + /* + * These are buffers that can't be written to the client which + * means that the copy cannot be completed. Make sure that we + * remove those references in DCI wakeup source. + */ + diag_ws_on_copy_fail(DIAG_WS_DCI); + } + mutex_unlock(&entry->write_buf_mutex); + + for (i = 0; i < entry->num_buffers; i++) { + proc_buf = &entry->buffers[i]; + buf_entry = proc_buf->buf_curr; + mutex_lock(&proc_buf->buf_mutex); + /* Clean up secondary buffer from mempool that is active */ + if (buf_entry && buf_entry->buf_type == DCI_BUF_SECONDARY) { + mutex_lock(&buf_entry->data_mutex); + diagmem_free(driver, buf_entry->data, POOL_TYPE_DCI); + buf_entry->data = NULL; + mutex_unlock(&buf_entry->data_mutex); + mutex_destroy(&buf_entry->data_mutex); + kfree(buf_entry); + buf_entry = NULL; + } + + mutex_lock(&proc_buf->buf_primary->data_mutex); + vfree(proc_buf->buf_primary->data); + proc_buf->buf_primary->data = NULL; + mutex_unlock(&proc_buf->buf_primary->data_mutex); + + mutex_lock(&proc_buf->buf_cmd->data_mutex); + vfree(proc_buf->buf_cmd->data); + proc_buf->buf_cmd->data = NULL; + mutex_unlock(&proc_buf->buf_cmd->data_mutex); + + mutex_destroy(&proc_buf->health_mutex); + mutex_destroy(&proc_buf->buf_primary->data_mutex); + mutex_destroy(&proc_buf->buf_cmd->data_mutex); + + kfree(proc_buf->buf_primary); + proc_buf->buf_primary = NULL; + kfree(proc_buf->buf_cmd); + proc_buf->buf_cmd = NULL; + mutex_unlock(&proc_buf->buf_mutex); + } + mutex_destroy(&entry->write_buf_mutex); + + kfree(entry->buffers); + entry->buffers = NULL; + kfree(entry); + entry = NULL; + + if (driver->num_dci_client == 0) { + diag_update_proc_vote(DIAG_PROC_DCI, VOTE_DOWN, token); + } else { + real_time = diag_dci_get_cumulative_real_time(token); + diag_update_real_time_vote(DIAG_PROC_DCI, real_time, token); + } + queue_work(driver->diag_real_time_wq, &driver->diag_real_time_work); + + return DIAG_DCI_NO_ERROR; +} + +int diag_dci_write_proc(uint8_t peripheral, int pkt_type, char *buf, int len) +{ + uint8_t dest_channel = TYPE_DATA; + int err = 0; + + if (!buf || peripheral >= NUM_PERIPHERALS || len < 0 || + !(driver->feature[PERIPHERAL_MODEM].rcvd_feature_mask)) { + DIAG_LOG(DIAG_DEBUG_DCI, + "buf: 0x%pK, p: %d, len: %d, f_mask: %d\n", + buf, peripheral, len, + driver->feature[PERIPHERAL_MODEM].rcvd_feature_mask); + return -EINVAL; + } + + if (pkt_type == DIAG_DATA_TYPE) { + dest_channel = TYPE_DCI_CMD; + } else if (pkt_type == DIAG_CNTL_TYPE) { + dest_channel = TYPE_CNTL; + } else { + pr_err("diag: Invalid DCI pkt type in %s", __func__); + return -EINVAL; + } + + err = diagfwd_write(peripheral, dest_channel, buf, len); + if (err && err != -ENODEV) { + pr_err("diag: In %s, unable to write to peripheral: %d, type: %d, len: %d, err: %d\n", + __func__, peripheral, dest_channel, len, err); + } else { + err = DIAG_DCI_NO_ERROR; + } + + return err; +} + +int diag_dci_copy_health_stats(struct diag_dci_health_stats_proc *stats_proc) +{ + struct diag_dci_client_tbl *entry = NULL; + struct diag_dci_health_t *health = NULL; + struct diag_dci_health_stats *stats = NULL; + int i, proc; + + if (!stats_proc) + return -EINVAL; + + stats = &stats_proc->health; + proc = stats_proc->proc; + if (proc < ALL_PROC || proc > APPS_DATA) + return -EINVAL; + + entry = diag_dci_get_client_entry(stats_proc->client_id); + if (!entry) + return DIAG_DCI_NOT_SUPPORTED; + + /* + * If the client has registered for remote processor, the + * proc field doesn't have any effect as they have only one buffer. + */ + if (entry->client_info.token) + proc = 0; + + stats->stats.dropped_logs = 0; + stats->stats.dropped_events = 0; + stats->stats.received_logs = 0; + stats->stats.received_events = 0; + + if (proc != ALL_PROC) { + health = &entry->buffers[proc].health; + stats->stats.dropped_logs = health->dropped_logs; + stats->stats.dropped_events = health->dropped_events; + stats->stats.received_logs = health->received_logs; + stats->stats.received_events = health->received_events; + if (stats->reset_status) { + mutex_lock(&entry->buffers[proc].health_mutex); + health->dropped_logs = 0; + health->dropped_events = 0; + health->received_logs = 0; + health->received_events = 0; + mutex_unlock(&entry->buffers[proc].health_mutex); + } + return DIAG_DCI_NO_ERROR; + } + + for (i = 0; i < entry->num_buffers; i++) { + health = &entry->buffers[i].health; + stats->stats.dropped_logs += health->dropped_logs; + stats->stats.dropped_events += health->dropped_events; + stats->stats.received_logs += health->received_logs; + stats->stats.received_events += health->received_events; + if (stats->reset_status) { + mutex_lock(&entry->buffers[i].health_mutex); + health->dropped_logs = 0; + health->dropped_events = 0; + health->received_logs = 0; + health->received_events = 0; + mutex_unlock(&entry->buffers[i].health_mutex); + } + } + return DIAG_DCI_NO_ERROR; +} + +int diag_dci_get_support_list(struct diag_dci_peripherals_t *support_list) +{ + if (!support_list) + return -ENOMEM; + + if (!VALID_DCI_TOKEN(support_list->proc)) + return -EIO; + + support_list->list = dci_ops_tbl[support_list->proc].peripheral_status; + return DIAG_DCI_NO_ERROR; +} diff -Nruw linux-4.4.115-fbx/drivers/char/diag./diag_dci.h linux-4.4.115-fbx/drivers/char/diag/diag_dci.h --- linux-4.4.115-fbx/drivers/char/diag./diag_dci.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-4.4.115-fbx/drivers/char/diag/diag_dci.h 2019-10-29 09:26:23.449201280 +0100 @@ -0,0 +1,329 @@ +/* Copyright (c) 2012-2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#ifndef DIAG_DCI_H +#define DIAG_DCI_H + +#define MAX_DCI_CLIENTS 10 +#define DCI_PKT_RSP_CODE 0x93 +#define DCI_DELAYED_RSP_CODE 0x94 +#define DCI_CONTROL_PKT_CODE 0x9A +#define EXT_HDR_CMD_CODE 0x98 +#define LOG_CMD_CODE 0x10 +#define EVENT_CMD_CODE 0x60 +#define DCI_PKT_RSP_TYPE 0 +#define DCI_LOG_TYPE -1 +#define DCI_EVENT_TYPE -2 +#define DCI_EXT_HDR_TYPE -3 +#define SET_LOG_MASK 1 +#define DISABLE_LOG_MASK 0 +#define MAX_EVENT_SIZE 512 +#define DCI_CLIENT_INDEX_INVALID -1 +#define DCI_LOG_CON_MIN_LEN 14 +#define DCI_EVENT_CON_MIN_LEN 16 + +#define EXT_HDR_LEN 8 +#define EXT_HDR_VERSION 1 + +#define DCI_BUF_PRIMARY 1 +#define DCI_BUF_SECONDARY 2 +#define DCI_BUF_CMD 3 + +#ifdef CONFIG_DEBUG_FS +#define DIAG_DCI_DEBUG_CNT 100 +#define DIAG_DCI_DEBUG_LEN 100 +#endif + +/* 16 log code categories, each has: + * 1 bytes equip id + 1 dirty byte + 512 byte max log mask + */ +#define DCI_LOG_MASK_SIZE (16*514) +#define DCI_EVENT_MASK_SIZE 512 +#define DCI_MASK_STREAM 2 +#define DCI_MAX_LOG_CODES 16 +#define DCI_MAX_ITEMS_PER_LOG_CODE 512 + +#define DCI_LOG_MASK_CLEAN 0 +#define DCI_LOG_MASK_DIRTY 1 + +#define MIN_DELAYED_RSP_LEN 12 +/* + * Maximum data size that peripherals send = 8.5K log + + * DCI header + footer (6 bytes) + */ +#define MAX_DCI_PACKET_SZ 8710 + +extern unsigned int dci_max_reg; +extern unsigned int dci_max_clients; + +#define DCI_LOCAL_PROC 0 +#define DCI_REMOTE_BASE 1 +#define DCI_MDM_PROC DCI_REMOTE_BASE +#define DCI_REMOTE_LAST (DCI_REMOTE_BASE + 1) + +#ifndef CONFIG_DIAGFWD_BRIDGE_CODE +#define NUM_DCI_PROC 1 +#else +#define NUM_DCI_PROC DCI_REMOTE_LAST +#endif + +#define DCI_REMOTE_DATA 0 + +#define VALID_DCI_TOKEN(x) ((x >= 0 && x < NUM_DCI_PROC) ? 1 : 0) +#define BRIDGE_TO_TOKEN(x) (x - DIAGFWD_MDM_DCI + DCI_REMOTE_BASE) +#define TOKEN_TO_BRIDGE(x) (dci_ops_tbl[x].ctx) + +#define DCI_MAGIC (0xAABB1122) + +struct dci_pkt_req_t { + int uid; + int client_id; +} __packed; + +struct dci_stream_req_t { + int type; + int client_id; + int set_flag; + int count; +} __packed; + +struct dci_pkt_req_entry_t { + int client_id; + int uid; + int tag; + struct list_head track; +} __packed; + +struct diag_dci_reg_tbl_t { + int client_id; + uint16_t notification_list; + int signal_type; + int token; +} __packed; + +struct diag_dci_health_t { + int dropped_logs; + int dropped_events; + int received_logs; + int received_events; +}; + +struct diag_dci_partial_pkt_t { + unsigned char *data; + uint32_t total_len; + uint32_t read_len; + uint32_t remaining; + uint8_t processing; +} __packed; + +struct diag_dci_buffer_t { + unsigned char *data; + unsigned int data_len; + struct mutex data_mutex; + uint8_t in_busy; + uint8_t buf_type; + int data_source; + int capacity; + uint8_t in_list; + struct list_head buf_track; +}; + +struct diag_dci_buf_peripheral_t { + struct diag_dci_buffer_t *buf_curr; + struct diag_dci_buffer_t *buf_primary; + struct diag_dci_buffer_t *buf_cmd; + struct diag_dci_health_t health; + struct mutex health_mutex; + struct mutex buf_mutex; +}; + +struct diag_dci_client_tbl { + int tgid; + struct diag_dci_reg_tbl_t client_info; + struct task_struct *client; + unsigned char *dci_log_mask; + unsigned char *dci_event_mask; + uint8_t real_time; + struct list_head track; + struct diag_dci_buf_peripheral_t *buffers; + uint8_t num_buffers; + uint8_t in_service; + struct list_head list_write_buf; + struct mutex write_buf_mutex; +}; + +struct diag_dci_health_stats { + struct diag_dci_health_t stats; + int reset_status; +}; + +struct diag_dci_health_stats_proc { + int client_id; + struct diag_dci_health_stats health; + int proc; +} __packed; + +struct diag_dci_peripherals_t { + int proc; + uint16_t list; +} __packed; + +/* This is used for querying DCI Log + or Event Mask */ +struct diag_log_event_stats { + int client_id; + uint16_t code; + int is_set; +} __packed; + +struct diag_dci_pkt_rsp_header_t { + int type; + int length; + uint8_t delete_flag; + int uid; +} __packed; + +struct diag_dci_pkt_header_t { + uint8_t start; + uint8_t version; + uint16_t len; + uint8_t pkt_code; + int tag; +} __packed; + +struct diag_dci_header_t { + uint8_t start; + uint8_t version; + uint16_t length; + uint8_t cmd_code; +} __packed; + +struct dci_ops_tbl_t { + int ctx; + int mempool; + unsigned char log_mask_composite[DCI_LOG_MASK_SIZE]; + unsigned char event_mask_composite[DCI_EVENT_MASK_SIZE]; + int (*send_log_mask)(int token); + int (*send_event_mask)(int token); + uint16_t peripheral_status; +} __packed; + +struct dci_channel_status_t { + int id; + int open; + int retry_count; + struct timer_list wait_time; + struct work_struct handshake_work; +} __packed; + +extern struct dci_ops_tbl_t dci_ops_tbl[NUM_DCI_PROC]; + +enum { + DIAG_DCI_NO_ERROR = 1001, /* No error */ + DIAG_DCI_NO_REG, /* Could not register */ + DIAG_DCI_NO_MEM, /* Failed memory allocation */ + DIAG_DCI_NOT_SUPPORTED, /* This particular client is not supported */ + DIAG_DCI_HUGE_PACKET, /* Request/Response Packet too huge */ + DIAG_DCI_SEND_DATA_FAIL,/* writing to kernel or peripheral fails */ + DIAG_DCI_TABLE_ERR /* Error dealing with registration tables */ +}; + +#define DCI_HDR_SIZE \ + ((sizeof(struct diag_dci_pkt_header_t) > \ + sizeof(struct diag_dci_header_t)) ? \ + (sizeof(struct diag_dci_pkt_header_t) + 1) : \ + (sizeof(struct diag_dci_header_t) + 1)) \ + +#define DCI_BUF_SIZE (uint32_t)(DIAG_MAX_REQ_SIZE + DCI_HDR_SIZE) + +#define DCI_REQ_HDR_SIZE \ + ((sizeof(struct dci_pkt_req_t) > \ + sizeof(struct dci_stream_req_t)) ? \ + (sizeof(struct dci_pkt_req_t)) : \ + (sizeof(struct dci_stream_req_t))) \ + +#define DCI_REQ_BUF_SIZE (uint32_t)(DIAG_MAX_REQ_SIZE + DCI_REQ_HDR_SIZE) + +#ifdef CONFIG_DEBUG_FS +/* To collect debug information during each smd read */ +struct diag_dci_data_info { + unsigned long iteration; + int data_size; + char time_stamp[DIAG_TS_SIZE]; + uint8_t peripheral; + uint8_t ch_type; + uint8_t proc; +}; + +extern struct diag_dci_data_info *dci_traffic; +extern struct mutex dci_stat_mutex; +#endif + +int diag_dci_init(void); +void diag_dci_channel_init(void); +void diag_dci_exit(void); +int diag_dci_register_client(struct diag_dci_reg_tbl_t *reg_entry); +int diag_dci_deinit_client(struct diag_dci_client_tbl *entry); +void diag_dci_channel_open_work(struct work_struct *); +void diag_dci_notify_client(int peripheral_mask, int data, int proc); +void diag_dci_wakeup_clients(void); +void diag_process_apps_dci_read_data(int data_type, void *buf, int recd_bytes); +void diag_dci_process_peripheral_data(struct diagfwd_info *p_info, void *buf, + int recd_bytes); +int diag_process_dci_transaction(unsigned char *buf, int len); +void extract_dci_pkt_rsp(unsigned char *buf, int len, int data_source, + int token); +void extract_dci_ctrl_pkt(unsigned char *buf, int len, int token); +struct diag_dci_client_tbl *diag_dci_get_client_entry(int client_id); +struct diag_dci_client_tbl *dci_lookup_client_entry_pid(int tgid); +void diag_process_remote_dci_read_data(int index, void *buf, int recd_bytes); +int diag_dci_get_support_list(struct diag_dci_peripherals_t *support_list); +/* DCI Log streaming functions */ +void update_dci_cumulative_log_mask(int offset, unsigned int byte_index, + uint8_t byte_mask, int token); +void diag_dci_invalidate_cumulative_log_mask(int token); +int diag_send_dci_log_mask(int token); +void extract_dci_log(unsigned char *buf, int len, int data_source, int token, + void *ext_hdr); +int diag_dci_clear_log_mask(int client_id); +int diag_dci_query_log_mask(struct diag_dci_client_tbl *entry, + uint16_t log_code); +/* DCI event streaming functions */ +void update_dci_cumulative_event_mask(int offset, uint8_t byte_mask, int token); +void diag_dci_invalidate_cumulative_event_mask(int token); +int diag_send_dci_event_mask(int token); +void extract_dci_events(unsigned char *buf, int len, int data_source, + int token, void *ext_hdr); +/* DCI extended header handling functions */ +void extract_dci_ext_pkt(unsigned char *buf, int len, int data_source, + int token); +int diag_dci_clear_event_mask(int client_id); +int diag_dci_query_event_mask(struct diag_dci_client_tbl *entry, + uint16_t event_id); +void diag_dci_record_traffic(int read_bytes, uint8_t ch_type, + uint8_t peripheral, uint8_t proc); +uint8_t diag_dci_get_cumulative_real_time(int token); +int diag_dci_set_real_time(struct diag_dci_client_tbl *entry, + uint8_t real_time); +int diag_dci_copy_health_stats(struct diag_dci_health_stats_proc *stats_proc); +int diag_dci_write_proc(uint8_t peripheral, int pkt_type, char *buf, int len); +void dci_drain_data(unsigned long data); + +#ifdef CONFIG_DIAGFWD_BRIDGE_CODE +int diag_send_dci_log_mask_remote(int token); +int diag_send_dci_event_mask_remote(int token); +unsigned char *dci_get_buffer_from_bridge(int token); +int diag_dci_write_bridge(int token, unsigned char *buf, int len); +int diag_dci_write_done_bridge(int index, unsigned char *buf, int len); +int diag_dci_send_handshake_pkt(int index); +#endif + +#endif diff -Nruw linux-4.4.115-fbx/drivers/char/diag./diag_debugfs.c linux-4.4.115-fbx/drivers/char/diag/diag_debugfs.c --- linux-4.4.115-fbx/drivers/char/diag./diag_debugfs.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-4.4.115-fbx/drivers/char/diag/diag_debugfs.c 2019-10-29 09:26:23.449201280 +0100 @@ -0,0 +1,1216 @@ +/* Copyright (c) 2011-2017, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifdef CONFIG_DEBUG_FS + +#include +#include +#include +#include +#include "diagchar.h" +#include "diagfwd.h" +#ifdef CONFIG_DIAGFWD_BRIDGE_CODE +#include "diagfwd_bridge.h" +#endif +#ifdef CONFIG_USB_QCOM_DIAG_BRIDGE +#include "diagfwd_hsic.h" +#include "diagfwd_smux.h" +#endif +#ifdef CONFIG_MSM_MHI +#include "diagfwd_mhi.h" +#endif +#include "diagmem.h" +#include "diag_dci.h" +#include "diag_usb.h" +#include "diagfwd_peripheral.h" +#include "diagfwd_smd.h" +#include "diagfwd_socket.h" +#include "diagfwd_glink.h" +#include "diag_debugfs.h" +#include "diag_ipc_logging.h" + +#define DEBUG_BUF_SIZE 4096 +static struct dentry *diag_dbgfs_dent; +static int diag_dbgfs_table_index; +static int diag_dbgfs_mempool_index; +static int diag_dbgfs_usbinfo_index; +static int diag_dbgfs_smdinfo_index; +static int diag_dbgfs_socketinfo_index; +static int diag_dbgfs_glinkinfo_index; +static int diag_dbgfs_hsicinfo_index; +static int diag_dbgfs_mhiinfo_index; +static int diag_dbgfs_bridgeinfo_index; +static int diag_dbgfs_finished; +static int diag_dbgfs_dci_data_index; +static int diag_dbgfs_dci_finished; +static struct mutex diag_dci_dbgfs_mutex; +static ssize_t diag_dbgfs_read_status(struct file *file, char __user *ubuf, + size_t count, loff_t *ppos) +{ + char *buf; + int ret, i; + unsigned int buf_size; + buf = kzalloc(sizeof(char) * DEBUG_BUF_SIZE, GFP_KERNEL); + if (!buf) { + pr_err("diag: %s, Error allocating memory\n", __func__); + return -ENOMEM; + } + buf_size = ksize(buf); + ret = scnprintf(buf, buf_size, + "CPU Tools ID: %d\n" + "Check Polling Response: %d\n" + "Polling Registered: %d\n" + "Uses Device Tree: %d\n" + "Apps Supports Separate CMDRSP: %d\n" + "Apps Supports HDLC Encoding: %d\n" + "Apps Supports Header Untagging: %d\n" + "Apps Supports Sockets: %d\n" + "Logging Mode: %d\n" + "RSP Buffer is Busy: %d\n" + "HDLC Disabled: %d\n" + "Time Sync Enabled: %d\n" + "MD session mode: %d\n" + "MD session mask: %d\n" + "Uses Time API: %d\n" + "Supports PD buffering: %d\n", + chk_config_get_id(), + chk_polling_response(), + driver->polling_reg_flag, + driver->use_device_tree, + driver->supports_separate_cmdrsp, + driver->supports_apps_hdlc_encoding, + driver->supports_apps_header_untagging, + driver->supports_sockets, + driver->logging_mode, + driver->rsp_buf_busy, + driver->hdlc_disabled, + driver->time_sync_enabled, + driver->md_session_mode, + driver->md_session_mask, + driver->uses_time_api, + driver->supports_pd_buffering); + + for (i = 0; i < NUM_PERIPHERALS; i++) { + ret += scnprintf(buf+ret, buf_size-ret, + "p: %s Feature: %02x %02x |%c%c%c%c%c%c%c%c%c%c|\n", + PERIPHERAL_STRING(i), + driver->feature[i].feature_mask[0], + driver->feature[i].feature_mask[1], + driver->feature[i].rcvd_feature_mask ? 'F':'f', + driver->feature[i].peripheral_buffering ? 'B':'b', + driver->feature[i].separate_cmd_rsp ? 'C':'c', + driver->feature[i].encode_hdlc ? 'H':'h', + driver->feature[i].mask_centralization ? 'M':'m', + driver->feature[i].pd_buffering ? 'P':'p', + driver->feature[i].stm_support ? 'Q':'q', + driver->feature[i].sockets_enabled ? 'S':'s', + driver->feature[i].sent_feature_mask ? 'T':'t', + driver->feature[i].untag_header ? 'U':'u'); + } + +#ifdef CONFIG_DIAG_OVER_USB + ret += scnprintf(buf+ret, buf_size-ret, + "USB Connected: %d\n", + driver->usb_connected); +#endif + + for (i = 0; i < DIAG_NUM_PROC; i++) { + ret += scnprintf(buf+ret, buf_size-ret, + "Real Time Mode: %d: %d\n", i, + driver->real_time_mode[i]); + } + + ret = simple_read_from_buffer(ubuf, count, ppos, buf, ret); + + kfree(buf); + return ret; +} + +static ssize_t diag_dbgfs_read_dcistats(struct file *file, + char __user *ubuf, size_t count, loff_t *ppos) +{ + char *buf = NULL; + unsigned int bytes_remaining, bytes_written = 0; + unsigned int bytes_in_buf = 0, i = 0; + struct diag_dci_data_info *temp_data = dci_traffic; + unsigned int buf_size; + buf_size = (DEBUG_BUF_SIZE < count) ? DEBUG_BUF_SIZE : count; + + if (diag_dbgfs_dci_finished) { + diag_dbgfs_dci_finished = 0; + return 0; + } + + buf = kzalloc(sizeof(char) * buf_size, GFP_KERNEL); + if (ZERO_OR_NULL_PTR(buf)) { + pr_err("diag: %s, Error allocating memory\n", __func__); + return -ENOMEM; + } + + buf_size = ksize(buf); + bytes_remaining = buf_size; + + mutex_lock(&diag_dci_dbgfs_mutex); + if (diag_dbgfs_dci_data_index == 0) { + bytes_written = + scnprintf(buf, buf_size, + "number of clients: %d\n" + "dci proc active: %d\n" + "dci real time vote: %d\n", + driver->num_dci_client, + (driver->proc_active_mask & DIAG_PROC_DCI) ? 1 : 0, + (driver->proc_rt_vote_mask[DIAG_LOCAL_PROC] & + DIAG_PROC_DCI) ? 1 : 0); + bytes_in_buf += bytes_written; + bytes_remaining -= bytes_written; +#ifdef CONFIG_DIAG_OVER_USB + bytes_written = scnprintf(buf+bytes_in_buf, bytes_remaining, + "usb_connected: %d\n", + driver->usb_connected); + bytes_in_buf += bytes_written; + bytes_remaining -= bytes_written; +#endif + bytes_written = scnprintf(buf+bytes_in_buf, + bytes_remaining, + "dci power: active, relax: %lu, %lu\n", + driver->diag_dev->power.wakeup-> + active_count, + driver->diag_dev-> + power.wakeup->relax_count); + bytes_in_buf += bytes_written; + bytes_remaining -= bytes_written; + + } + temp_data += diag_dbgfs_dci_data_index; + for (i = diag_dbgfs_dci_data_index; i < DIAG_DCI_DEBUG_CNT; i++) { + if (temp_data->iteration != 0) { + bytes_written = scnprintf( + buf + bytes_in_buf, bytes_remaining, + "i %-5ld\t" + "s %-5d\t" + "p %-5d\t" + "r %-5d\t" + "c %-5d\t" + "t %-15s\n", + temp_data->iteration, + temp_data->data_size, + temp_data->peripheral, + temp_data->proc, + temp_data->ch_type, + temp_data->time_stamp); + bytes_in_buf += bytes_written; + bytes_remaining -= bytes_written; + /* Check if there is room for another entry */ + if (bytes_remaining < bytes_written) + break; + } + temp_data++; + } + diag_dbgfs_dci_data_index = (i >= DIAG_DCI_DEBUG_CNT) ? 0 : i + 1; + mutex_unlock(&diag_dci_dbgfs_mutex); + bytes_written = simple_read_from_buffer(ubuf, count, ppos, buf, + bytes_in_buf); + kfree(buf); + diag_dbgfs_dci_finished = 1; + return bytes_written; +} + +static ssize_t diag_dbgfs_read_power(struct file *file, char __user *ubuf, + size_t count, loff_t *ppos) +{ + char *buf; + int ret; + unsigned int buf_size; + + buf = kzalloc(sizeof(char) * DEBUG_BUF_SIZE, GFP_KERNEL); + if (!buf) { + pr_err("diag: %s, Error allocating memory\n", __func__); + return -ENOMEM; + } + + buf_size = ksize(buf); + ret = scnprintf(buf, buf_size, + "DCI reference count: %d\n" + "DCI copy count: %d\n" + "DCI Client Count: %d\n\n" + "Memory Device reference count: %d\n" + "Memory Device copy count: %d\n" + "Logging mode: %d\n\n" + "Wakeup source active count: %lu\n" + "Wakeup source relax count: %lu\n\n", + driver->dci_ws.ref_count, + driver->dci_ws.copy_count, + driver->num_dci_client, + driver->md_ws.ref_count, + driver->md_ws.copy_count, + driver->logging_mode, + driver->diag_dev->power.wakeup->active_count, + driver->diag_dev->power.wakeup->relax_count); + + ret = simple_read_from_buffer(ubuf, count, ppos, buf, ret); + + kfree(buf); + return ret; +} + +static ssize_t diag_dbgfs_read_table(struct file *file, char __user *ubuf, + size_t count, loff_t *ppos) +{ + char *buf; + int ret = 0; + int i = 0; + int is_polling = 0; + unsigned int bytes_remaining; + unsigned int bytes_in_buffer = 0; + unsigned int bytes_written; + unsigned int buf_size; + struct list_head *start; + struct list_head *temp; + struct diag_cmd_reg_t *item = NULL; + + mutex_lock(&driver->cmd_reg_mutex); + if (diag_dbgfs_table_index == driver->cmd_reg_count) { + diag_dbgfs_table_index = 0; + mutex_unlock(&driver->cmd_reg_mutex); + return 0; + } + + buf_size = (DEBUG_BUF_SIZE < count) ? DEBUG_BUF_SIZE : count; + + buf = kzalloc(sizeof(char) * buf_size, GFP_KERNEL); + if (ZERO_OR_NULL_PTR(buf)) { + pr_err("diag: %s, Error allocating memory\n", __func__); + mutex_unlock(&driver->cmd_reg_mutex); + return -ENOMEM; + } + buf_size = ksize(buf); + bytes_remaining = buf_size; + + if (diag_dbgfs_table_index == 0) { + bytes_written = scnprintf(buf+bytes_in_buffer, bytes_remaining, + "Client ids: Modem: %d, LPASS: %d, WCNSS: %d, SLPI: %d, APPS: %d\n", + PERIPHERAL_MODEM, PERIPHERAL_LPASS, + PERIPHERAL_WCNSS, PERIPHERAL_SENSORS, + APPS_DATA); + bytes_in_buffer += bytes_written; + bytes_remaining -= bytes_written; + } + + list_for_each_safe(start, temp, &driver->cmd_reg_list) { + item = list_entry(start, struct diag_cmd_reg_t, link); + if (i < diag_dbgfs_table_index) { + i++; + continue; + } + + is_polling = diag_cmd_chk_polling(&item->entry); + bytes_written = scnprintf(buf+bytes_in_buffer, bytes_remaining, + "i: %3d, cmd_code: %4x, subsys_id: %4x, cmd_code_lo: %4x, cmd_code_hi: %4x, proc: %d, process_id: %5d %s\n", + i++, + item->entry.cmd_code, + item->entry.subsys_id, + item->entry.cmd_code_lo, + item->entry.cmd_code_hi, + item->proc, + item->pid, + (is_polling == DIAG_CMD_POLLING) ? + "<-- Polling Cmd" : ""); + + bytes_in_buffer += bytes_written; + + /* Check if there is room to add another table entry */ + bytes_remaining = buf_size - bytes_in_buffer; + + if (bytes_remaining < bytes_written) + break; + } + diag_dbgfs_table_index = i; + mutex_unlock(&driver->cmd_reg_mutex); + + *ppos = 0; + ret = simple_read_from_buffer(ubuf, count, ppos, buf, bytes_in_buffer); + + kfree(buf); + return ret; +} + +static ssize_t diag_dbgfs_read_mempool(struct file *file, char __user *ubuf, + size_t count, loff_t *ppos) +{ + char *buf = NULL; + int ret = 0; + int i = 0; + unsigned int buf_size; + unsigned int bytes_remaining = 0; + unsigned int bytes_written = 0; + unsigned int bytes_in_buffer = 0; + struct diag_mempool_t *mempool = NULL; + + if (diag_dbgfs_mempool_index >= NUM_MEMORY_POOLS) { + /* Done. Reset to prepare for future requests */ + diag_dbgfs_mempool_index = 0; + return 0; + } + + buf = kzalloc(sizeof(char) * DEBUG_BUF_SIZE, GFP_KERNEL); + if (ZERO_OR_NULL_PTR(buf)) { + pr_err("diag: %s, Error allocating memory\n", __func__); + return -ENOMEM; + } + + buf_size = ksize(buf); + bytes_remaining = buf_size; + bytes_written = scnprintf(buf+bytes_in_buffer, bytes_remaining, + "%-24s\t" + "%-10s\t" + "%-5s\t" + "%-5s\t" + "%-5s\n", + "POOL", "HANDLE", "COUNT", "SIZE", "ITEMSIZE"); + bytes_in_buffer += bytes_written; + bytes_remaining = buf_size - bytes_in_buffer; + + for (i = diag_dbgfs_mempool_index; i < NUM_MEMORY_POOLS; i++) { + mempool = &diag_mempools[i]; + bytes_written = scnprintf(buf+bytes_in_buffer, bytes_remaining, + "%-24s\t" + "%-10p\t" + "%-5d\t" + "%-5d\t" + "%-5d\n", + mempool->name, + mempool->pool, + mempool->count, + mempool->poolsize, + mempool->itemsize); + bytes_in_buffer += bytes_written; + + /* Check if there is room to add another table entry */ + bytes_remaining = buf_size - bytes_in_buffer; + + if (bytes_remaining < bytes_written) + break; + } + diag_dbgfs_mempool_index = i+1; + *ppos = 0; + ret = simple_read_from_buffer(ubuf, count, ppos, buf, bytes_in_buffer); + + kfree(buf); + return ret; +} + +#ifdef CONFIG_DIAG_OVER_USB +static ssize_t diag_dbgfs_read_usbinfo(struct file *file, char __user *ubuf, + size_t count, loff_t *ppos) +{ + char *buf = NULL; + int ret = 0; + int i = 0; + unsigned int buf_size; + unsigned int bytes_remaining = 0; + unsigned int bytes_written = 0; + unsigned int bytes_in_buffer = 0; + struct diag_usb_info *usb_info = NULL; + + if (diag_dbgfs_usbinfo_index >= NUM_DIAG_USB_DEV) { + /* Done. Reset to prepare for future requests */ + diag_dbgfs_usbinfo_index = 0; + return 0; + } + + buf = kzalloc(sizeof(char) * DEBUG_BUF_SIZE, GFP_KERNEL); + if (ZERO_OR_NULL_PTR(buf)) { + pr_err("diag: %s, Error allocating memory\n", __func__); + return -ENOMEM; + } + + buf_size = ksize(buf); + bytes_remaining = buf_size; + for (i = diag_dbgfs_usbinfo_index; i < NUM_DIAG_USB_DEV; i++) { + usb_info = &diag_usb[i]; + if (!usb_info->enabled) + continue; + bytes_written = scnprintf(buf+bytes_in_buffer, bytes_remaining, + "id: %d\n" + "name: %s\n" + "hdl: %pK\n" + "connected: %d\n" + "diag state: %d\n" + "enabled: %d\n" + "mempool: %s\n" + "read pending: %d\n" + "read count: %lu\n" + "write count: %lu\n" + "read work pending: %d\n" + "read done work pending: %d\n" + "connect work pending: %d\n" + "disconnect work pending: %d\n" + "max size supported: %d\n\n", + usb_info->id, + usb_info->name, + usb_info->hdl, + atomic_read(&usb_info->connected), + atomic_read(&usb_info->diag_state), + usb_info->enabled, + DIAG_MEMPOOL_GET_NAME(usb_info->mempool), + atomic_read(&usb_info->read_pending), + usb_info->read_cnt, + usb_info->write_cnt, + work_pending(&usb_info->read_work), + work_pending(&usb_info->read_done_work), + work_pending(&usb_info->connect_work), + work_pending(&usb_info->disconnect_work), + usb_info->max_size); + bytes_in_buffer += bytes_written; + + /* Check if there is room to add another table entry */ + bytes_remaining = buf_size - bytes_in_buffer; + + if (bytes_remaining < bytes_written) + break; + } + diag_dbgfs_usbinfo_index = i+1; + *ppos = 0; + ret = simple_read_from_buffer(ubuf, count, ppos, buf, bytes_in_buffer); + + kfree(buf); + return ret; +} + +const struct file_operations diag_dbgfs_usbinfo_ops = { + .read = diag_dbgfs_read_usbinfo, +}; +#endif + +static ssize_t diag_dbgfs_read_smdinfo(struct file *file, char __user *ubuf, + size_t count, loff_t *ppos) +{ + char *buf = NULL; + int ret = 0; + int i = 0; + int j = 0; + unsigned int buf_size; + unsigned int bytes_remaining = 0; + unsigned int bytes_written = 0; + unsigned int bytes_in_buffer = 0; + struct diag_smd_info *smd_info = NULL; + struct diagfwd_info *fwd_ctxt = NULL; + + if (diag_dbgfs_smdinfo_index >= NUM_PERIPHERALS) { + /* Done. Reset to prepare for future requests */ + diag_dbgfs_smdinfo_index = 0; + return 0; + } + + buf = kzalloc(sizeof(char) * DEBUG_BUF_SIZE, GFP_KERNEL); + if (ZERO_OR_NULL_PTR(buf)) { + pr_err("diag: %s, Error allocating memory\n", __func__); + return -ENOMEM; + } + + buf_size = ksize(buf); + bytes_remaining = buf_size; + for (i = 0; i < NUM_TYPES; i++) { + for (j = 0; j < NUM_PERIPHERALS; j++) { + switch (i) { + case TYPE_DATA: + smd_info = &smd_data[j]; + break; + case TYPE_CNTL: + smd_info = &smd_cntl[j]; + break; + case TYPE_DCI: + smd_info = &smd_dci[j]; + break; + case TYPE_CMD: + smd_info = &smd_cmd[j]; + break; + case TYPE_DCI_CMD: + smd_info = &smd_dci_cmd[j]; + break; + default: + return -EINVAL; + } + + fwd_ctxt = (struct diagfwd_info *)(smd_info->fwd_ctxt); + + bytes_written = scnprintf(buf+bytes_in_buffer, + bytes_remaining, + "name\t\t:\t%s\n" + "hdl\t\t:\t%pK\n" + "inited\t\t:\t%d\n" + "opened\t\t:\t%d\n" + "diag_state\t:\t%d\n" + "fifo size\t:\t%d\n" + "open pending\t:\t%d\n" + "close pending\t:\t%d\n" + "read pending\t:\t%d\n" + "buf_1 busy\t:\t%d\n" + "buf_2 busy\t:\t%d\n" + "bytes read\t:\t%lu\n" + "bytes written\t:\t%lu\n" + "fwd inited\t:\t%d\n" + "fwd opened\t:\t%d\n" + "fwd ch_open\t:\t%d\n\n", + smd_info->name, + smd_info->hdl, + smd_info->inited, + atomic_read(&smd_info->opened), + atomic_read(&smd_info->diag_state), + smd_info->fifo_size, + work_pending(&smd_info->open_work), + work_pending(&smd_info->close_work), + work_pending(&smd_info->read_work), + (fwd_ctxt && fwd_ctxt->buf_1) ? + atomic_read(&fwd_ctxt->buf_1->in_busy) : -1, + (fwd_ctxt && fwd_ctxt->buf_2) ? + atomic_read(&fwd_ctxt->buf_2->in_busy) : -1, + (fwd_ctxt) ? fwd_ctxt->read_bytes : 0, + (fwd_ctxt) ? fwd_ctxt->write_bytes : 0, + (fwd_ctxt) ? fwd_ctxt->inited : -1, + (fwd_ctxt) ? + atomic_read(&fwd_ctxt->opened) : -1, + (fwd_ctxt) ? fwd_ctxt->ch_open : -1); + bytes_in_buffer += bytes_written; + + /* Check if there is room to add another table entry */ + bytes_remaining = buf_size - bytes_in_buffer; + + if (bytes_remaining < bytes_written) + break; + } + } + diag_dbgfs_smdinfo_index = i+1; + *ppos = 0; + ret = simple_read_from_buffer(ubuf, count, ppos, buf, bytes_in_buffer); + + kfree(buf); + return ret; +} + +static ssize_t diag_dbgfs_read_socketinfo(struct file *file, char __user *ubuf, + size_t count, loff_t *ppos) +{ + char *buf = NULL; + int ret = 0; + int i = 0; + int j = 0; + unsigned int buf_size; + unsigned int bytes_remaining = 0; + unsigned int bytes_written = 0; + unsigned int bytes_in_buffer = 0; + struct diag_socket_info *info = NULL; + struct diagfwd_info *fwd_ctxt = NULL; + + if (diag_dbgfs_socketinfo_index >= NUM_PERIPHERALS) { + /* Done. Reset to prepare for future requests */ + diag_dbgfs_socketinfo_index = 0; + return 0; + } + + buf = kzalloc(sizeof(char) * DEBUG_BUF_SIZE, GFP_KERNEL); + if (ZERO_OR_NULL_PTR(buf)) { + pr_err("diag: %s, Error allocating memory\n", __func__); + return -ENOMEM; + } + + buf_size = ksize(buf); + bytes_remaining = buf_size; + for (i = 0; i < NUM_TYPES; i++) { + for (j = 0; j < NUM_PERIPHERALS; j++) { + switch (i) { + case TYPE_DATA: + info = &socket_data[j]; + break; + case TYPE_CNTL: + info = &socket_cntl[j]; + break; + case TYPE_DCI: + info = &socket_dci[j]; + break; + case TYPE_CMD: + info = &socket_cmd[j]; + break; + case TYPE_DCI_CMD: + info = &socket_dci_cmd[j]; + break; + default: + return -EINVAL; + } + + fwd_ctxt = (struct diagfwd_info *)(info->fwd_ctxt); + + bytes_written = scnprintf(buf+bytes_in_buffer, + bytes_remaining, + "name\t\t:\t%s\n" + "hdl\t\t:\t%pK\n" + "inited\t\t:\t%d\n" + "opened\t\t:\t%d\n" + "diag_state\t:\t%d\n" + "buf_1 busy\t:\t%d\n" + "buf_2 busy\t:\t%d\n" + "flow ctrl count\t:\t%d\n" + "data_ready\t:\t%d\n" + "init pending\t:\t%d\n" + "read pending\t:\t%d\n" + "bytes read\t:\t%lu\n" + "bytes written\t:\t%lu\n" + "fwd inited\t:\t%d\n" + "fwd opened\t:\t%d\n" + "fwd ch_open\t:\t%d\n\n", + info->name, + info->hdl, + info->inited, + atomic_read(&info->opened), + atomic_read(&info->diag_state), + (fwd_ctxt && fwd_ctxt->buf_1) ? + atomic_read(&fwd_ctxt->buf_1->in_busy) : -1, + (fwd_ctxt && fwd_ctxt->buf_2) ? + atomic_read(&fwd_ctxt->buf_2->in_busy) : -1, + atomic_read(&info->flow_cnt), + info->data_ready, + work_pending(&info->init_work), + work_pending(&info->read_work), + (fwd_ctxt) ? fwd_ctxt->read_bytes : 0, + (fwd_ctxt) ? fwd_ctxt->write_bytes : 0, + (fwd_ctxt) ? fwd_ctxt->inited : -1, + (fwd_ctxt) ? + atomic_read(&fwd_ctxt->opened) : -1, + (fwd_ctxt) ? fwd_ctxt->ch_open : -1); + bytes_in_buffer += bytes_written; + + /* Check if there is room to add another table entry */ + bytes_remaining = buf_size - bytes_in_buffer; + + if (bytes_remaining < bytes_written) + break; + } + } + diag_dbgfs_socketinfo_index = i+1; + *ppos = 0; + ret = simple_read_from_buffer(ubuf, count, ppos, buf, bytes_in_buffer); + + kfree(buf); + return ret; +} + +static ssize_t diag_dbgfs_read_glinkinfo(struct file *file, char __user *ubuf, + size_t count, loff_t *ppos) +{ + char *buf = NULL; + int ret = 0; + int i = 0; + int j = 0; + unsigned int buf_size; + unsigned int bytes_remaining = 0; + unsigned int bytes_written = 0; + unsigned int bytes_in_buffer = 0; + struct diag_glink_info *info = NULL; + struct diagfwd_info *fwd_ctxt = NULL; + + if (diag_dbgfs_glinkinfo_index >= NUM_PERIPHERALS) { + /* Done. Reset to prepare for future requests */ + diag_dbgfs_socketinfo_index = 0; + return 0; + } + + buf = kzalloc(sizeof(char) * DEBUG_BUF_SIZE, GFP_KERNEL); + if (!buf) + return -ENOMEM; + + buf_size = ksize(buf); + bytes_remaining = buf_size; + for (i = 0; i < NUM_TYPES; i++) { + for (j = 0; j < NUM_PERIPHERALS; j++) { + switch (i) { + case TYPE_DATA: + info = &glink_data[j]; + break; + case TYPE_CNTL: + info = &glink_cntl[j]; + break; + case TYPE_DCI: + info = &glink_dci[j]; + break; + case TYPE_CMD: + info = &glink_cmd[j]; + break; + case TYPE_DCI_CMD: + info = &glink_dci_cmd[j]; + break; + default: + return -EINVAL; + } + + fwd_ctxt = (struct diagfwd_info *)(info->fwd_ctxt); + + bytes_written = scnprintf(buf+bytes_in_buffer, + bytes_remaining, + "name\t\t:\t%s\n" + "hdl\t\t:\t%pK\n" + "inited\t\t:\t%d\n" + "opened\t\t:\t%d\n" + "diag_state\t:\t%d\n" + "buf_1 busy\t:\t%d\n" + "buf_2 busy\t:\t%d\n" + "tx_intent_ready\t:\t%d\n" + "open pending\t:\t%d\n" + "close pending\t:\t%d\n" + "read pending\t:\t%d\n" + "bytes read\t:\t%lu\n" + "bytes written\t:\t%lu\n" + "fwd inited\t:\t%d\n" + "fwd opened\t:\t%d\n" + "fwd ch_open\t:\t%d\n\n", + info->name, + info->hdl, + info->inited, + atomic_read(&info->opened), + atomic_read(&info->diag_state), + (fwd_ctxt && fwd_ctxt->buf_1) ? + atomic_read(&fwd_ctxt->buf_1->in_busy) : -1, + (fwd_ctxt && fwd_ctxt->buf_2) ? + atomic_read(&fwd_ctxt->buf_2->in_busy) : -1, + atomic_read(&info->tx_intent_ready), + work_pending(&info->open_work), + work_pending(&info->close_work), + work_pending(&info->read_work), + (fwd_ctxt) ? fwd_ctxt->read_bytes : 0, + (fwd_ctxt) ? fwd_ctxt->write_bytes : 0, + (fwd_ctxt) ? fwd_ctxt->inited : -1, + (fwd_ctxt) ? + atomic_read(&fwd_ctxt->opened) : -1, + (fwd_ctxt) ? fwd_ctxt->ch_open : -1); + bytes_in_buffer += bytes_written; + + /* Check if there is room to add another table entry */ + bytes_remaining = buf_size - bytes_in_buffer; + + if (bytes_remaining < bytes_written) + break; + } + } + diag_dbgfs_glinkinfo_index = i+1; + *ppos = 0; + ret = simple_read_from_buffer(ubuf, count, ppos, buf, bytes_in_buffer); + + kfree(buf); + return ret; +} + +static ssize_t diag_dbgfs_write_debug(struct file *fp, const char __user *buf, + size_t count, loff_t *ppos) +{ + const int size = 10; + unsigned char cmd[size]; + long value = 0; + int len = 0; + + if (count < 1) + return -EINVAL; + + len = (count < (size - 1)) ? count : size - 1; + if (copy_from_user(cmd, buf, len)) + return -EFAULT; + + cmd[len] = 0; + if (cmd[len-1] == '\n') { + cmd[len-1] = 0; + len--; + } + + if (kstrtol(cmd, 10, &value)) + return -EINVAL; + + if (value < 0) + return -EINVAL; + + diag_debug_mask = (uint16_t)value; + return count; +} + +#ifdef CONFIG_DIAGFWD_BRIDGE_CODE +#ifdef CONFIG_USB_QCOM_DIAG_BRIDGE +static ssize_t diag_dbgfs_read_hsicinfo(struct file *file, char __user *ubuf, + size_t count, loff_t *ppos) +{ + char *buf = NULL; + int ret = 0; + int i = 0; + unsigned int buf_size; + unsigned int bytes_remaining = 0; + unsigned int bytes_written = 0; + unsigned int bytes_in_buffer = 0; + struct diag_hsic_info *hsic_info = NULL; + + if (diag_dbgfs_hsicinfo_index >= NUM_DIAG_USB_DEV) { + /* Done. Reset to prepare for future requests */ + diag_dbgfs_hsicinfo_index = 0; + return 0; + } + + buf = kzalloc(sizeof(char) * DEBUG_BUF_SIZE, GFP_KERNEL); + if (ZERO_OR_NULL_PTR(buf)) { + pr_err("diag: %s, Error allocating memory\n", __func__); + return -ENOMEM; + } + + buf_size = ksize(buf); + bytes_remaining = buf_size; + for (i = diag_dbgfs_hsicinfo_index; i < NUM_HSIC_DEV; i++) { + hsic_info = &diag_hsic[i]; + if (!hsic_info->enabled) + continue; + bytes_written = scnprintf(buf+bytes_in_buffer, bytes_remaining, + "id: %d\n" + "name: %s\n" + "bridge index: %s\n" + "opened: %d\n" + "enabled: %d\n" + "suspended: %d\n" + "mempool: %s\n" + "read work pending: %d\n" + "open work pending: %d\n" + "close work pending: %d\n\n", + hsic_info->id, + hsic_info->name, + DIAG_BRIDGE_GET_NAME(hsic_info->dev_id), + hsic_info->opened, + hsic_info->enabled, + hsic_info->suspended, + DIAG_MEMPOOL_GET_NAME(hsic_info->mempool), + work_pending(&hsic_info->read_work), + work_pending(&hsic_info->open_work), + work_pending(&hsic_info->close_work)); + bytes_in_buffer += bytes_written; + + /* Check if there is room to add another table entry */ + bytes_remaining = buf_size - bytes_in_buffer; + + if (bytes_remaining < bytes_written) + break; + } + diag_dbgfs_hsicinfo_index = i+1; + *ppos = 0; + ret = simple_read_from_buffer(ubuf, count, ppos, buf, bytes_in_buffer); + + kfree(buf); + return ret; +} + +const struct file_operations diag_dbgfs_hsicinfo_ops = { + .read = diag_dbgfs_read_hsicinfo, +}; +#endif +#ifdef CONFIG_MSM_MHI +static ssize_t diag_dbgfs_read_mhiinfo(struct file *file, char __user *ubuf, + size_t count, loff_t *ppos) +{ + char *buf = NULL; + int ret = 0; + int i = 0; + unsigned int buf_size; + unsigned int bytes_remaining = 0; + unsigned int bytes_written = 0; + unsigned int bytes_in_buffer = 0; + struct diag_mhi_info *mhi_info = NULL; + + if (diag_dbgfs_mhiinfo_index >= NUM_MHI_DEV) { + /* Done. Reset to prepare for future requests */ + diag_dbgfs_mhiinfo_index = 0; + return 0; + } + + buf = kzalloc(sizeof(char) * DEBUG_BUF_SIZE, GFP_KERNEL); + if (ZERO_OR_NULL_PTR(buf)) { + pr_err("diag: %s, Error allocating memory\n", __func__); + return -ENOMEM; + } + + buf_size = ksize(buf); + bytes_remaining = buf_size; + for (i = diag_dbgfs_mhiinfo_index; i < NUM_MHI_DEV; i++) { + mhi_info = &diag_mhi[i]; + bytes_written = scnprintf(buf+bytes_in_buffer, bytes_remaining, + "id: %d\n" + "name: %s\n" + "bridge index: %s\n" + "mempool: %s\n" + "read ch opened: %d\n" + "read ch hdl: %pK\n" + "write ch opened: %d\n" + "write ch hdl: %pK\n" + "read work pending: %d\n" + "read done work pending: %d\n" + "open work pending: %d\n" + "close work pending: %d\n\n", + mhi_info->id, + mhi_info->name, + DIAG_BRIDGE_GET_NAME(mhi_info->dev_id), + DIAG_MEMPOOL_GET_NAME(mhi_info->mempool), + atomic_read(&mhi_info->read_ch.opened), + mhi_info->read_ch.hdl, + atomic_read(&mhi_info->write_ch.opened), + mhi_info->write_ch.hdl, + work_pending(&mhi_info->read_work), + work_pending(&mhi_info->read_done_work), + work_pending(&mhi_info->open_work), + work_pending(&mhi_info->close_work)); + bytes_in_buffer += bytes_written; + + /* Check if there is room to add another table entry */ + bytes_remaining = buf_size - bytes_in_buffer; + + if (bytes_remaining < bytes_written) + break; + } + diag_dbgfs_mhiinfo_index = i+1; + *ppos = 0; + ret = simple_read_from_buffer(ubuf, count, ppos, buf, bytes_in_buffer); + + kfree(buf); + return ret; +} + + +const struct file_operations diag_dbgfs_mhiinfo_ops = { + .read = diag_dbgfs_read_mhiinfo, +}; + +#endif +static ssize_t diag_dbgfs_read_bridge(struct file *file, char __user *ubuf, + size_t count, loff_t *ppos) +{ + char *buf = NULL; + int ret = 0; + int i = 0; + unsigned int buf_size; + unsigned int bytes_remaining = 0; + unsigned int bytes_written = 0; + unsigned int bytes_in_buffer = 0; + struct diagfwd_bridge_info *info = NULL; + + if (diag_dbgfs_bridgeinfo_index >= NUM_DIAG_USB_DEV) { + /* Done. Reset to prepare for future requests */ + diag_dbgfs_bridgeinfo_index = 0; + return 0; + } + + buf = kzalloc(sizeof(char) * DEBUG_BUF_SIZE, GFP_KERNEL); + if (ZERO_OR_NULL_PTR(buf)) { + pr_err("diag: %s, Error allocating memory\n", __func__); + return -ENOMEM; + } + + buf_size = ksize(buf); + bytes_remaining = buf_size; + for (i = diag_dbgfs_bridgeinfo_index; i < NUM_REMOTE_DEV; i++) { + info = &bridge_info[i]; + if (!info->inited) + continue; + bytes_written = scnprintf(buf+bytes_in_buffer, bytes_remaining, + "id: %d\n" + "name: %s\n" + "type: %d\n" + "inited: %d\n" + "ctxt: %d\n" + "dev_ops: %pK\n" + "dci_read_buf: %pK\n" + "dci_read_ptr: %pK\n" + "dci_read_len: %d\n\n", + info->id, + info->name, + info->type, + info->inited, + info->ctxt, + info->dev_ops, + info->dci_read_buf, + info->dci_read_ptr, + info->dci_read_len); + bytes_in_buffer += bytes_written; + + /* Check if there is room to add another table entry */ + bytes_remaining = buf_size - bytes_in_buffer; + + if (bytes_remaining < bytes_written) + break; + } + diag_dbgfs_bridgeinfo_index = i+1; + *ppos = 0; + ret = simple_read_from_buffer(ubuf, count, ppos, buf, bytes_in_buffer); + + kfree(buf); + return ret; +} + +const struct file_operations diag_dbgfs_bridge_ops = { + .read = diag_dbgfs_read_bridge, +}; + +#endif + +const struct file_operations diag_dbgfs_status_ops = { + .read = diag_dbgfs_read_status, +}; + +const struct file_operations diag_dbgfs_smdinfo_ops = { + .read = diag_dbgfs_read_smdinfo, +}; + +const struct file_operations diag_dbgfs_socketinfo_ops = { + .read = diag_dbgfs_read_socketinfo, +}; + +const struct file_operations diag_dbgfs_glinkinfo_ops = { + .read = diag_dbgfs_read_glinkinfo, +}; + +const struct file_operations diag_dbgfs_table_ops = { + .read = diag_dbgfs_read_table, +}; + +const struct file_operations diag_dbgfs_mempool_ops = { + .read = diag_dbgfs_read_mempool, +}; + +const struct file_operations diag_dbgfs_dcistats_ops = { + .read = diag_dbgfs_read_dcistats, +}; + +const struct file_operations diag_dbgfs_power_ops = { + .read = diag_dbgfs_read_power, +}; + +const struct file_operations diag_dbgfs_debug_ops = { + .write = diag_dbgfs_write_debug +}; + +int diag_debugfs_init(void) +{ + struct dentry *entry = NULL; + + diag_dbgfs_dent = debugfs_create_dir("diag", 0); + if (IS_ERR(diag_dbgfs_dent)) + return -ENOMEM; + + entry = debugfs_create_file("status", 0444, diag_dbgfs_dent, 0, + &diag_dbgfs_status_ops); + if (!entry) + goto err; + + entry = debugfs_create_file("smdinfo", 0444, diag_dbgfs_dent, 0, + &diag_dbgfs_smdinfo_ops); + if (!entry) + goto err; + + entry = debugfs_create_file("socketinfo", 0444, diag_dbgfs_dent, 0, + &diag_dbgfs_socketinfo_ops); + if (!entry) + goto err; + + entry = debugfs_create_file("glinkinfo", 0444, diag_dbgfs_dent, 0, + &diag_dbgfs_glinkinfo_ops); + if (!entry) + goto err; + + entry = debugfs_create_file("table", 0444, diag_dbgfs_dent, 0, + &diag_dbgfs_table_ops); + if (!entry) + goto err; + + entry = debugfs_create_file("mempool", 0444, diag_dbgfs_dent, 0, + &diag_dbgfs_mempool_ops); + if (!entry) + goto err; + +#ifdef CONFIG_DIAG_OVER_USB + entry = debugfs_create_file("usbinfo", 0444, diag_dbgfs_dent, 0, + &diag_dbgfs_usbinfo_ops); + if (!entry) + goto err; +#endif + + entry = debugfs_create_file("dci_stats", 0444, diag_dbgfs_dent, 0, + &diag_dbgfs_dcistats_ops); + if (!entry) + goto err; + + entry = debugfs_create_file("power", 0444, diag_dbgfs_dent, 0, + &diag_dbgfs_power_ops); + if (!entry) + goto err; + + entry = debugfs_create_file("debug", 0444, diag_dbgfs_dent, 0, + &diag_dbgfs_debug_ops); + if (!entry) + goto err; + +#ifdef CONFIG_DIAGFWD_BRIDGE_CODE + entry = debugfs_create_file("bridge", 0444, diag_dbgfs_dent, 0, + &diag_dbgfs_bridge_ops); + if (!entry) + goto err; +#ifdef CONFIG_USB_QCOM_DIAG_BRIDGE + entry = debugfs_create_file("hsicinfo", 0444, diag_dbgfs_dent, 0, + &diag_dbgfs_hsicinfo_ops); + if (!entry) + goto err; +#endif +#ifdef CONFIG_MSM_MHI + entry = debugfs_create_file("mhiinfo", 0444, diag_dbgfs_dent, 0, + &diag_dbgfs_mhiinfo_ops); + if (!entry) + goto err; +#endif +#endif + diag_dbgfs_table_index = 0; + diag_dbgfs_mempool_index = 0; + diag_dbgfs_usbinfo_index = 0; + diag_dbgfs_smdinfo_index = 0; + diag_dbgfs_socketinfo_index = 0; + diag_dbgfs_hsicinfo_index = 0; + diag_dbgfs_bridgeinfo_index = 0; + diag_dbgfs_mhiinfo_index = 0; + diag_dbgfs_finished = 0; + diag_dbgfs_dci_data_index = 0; + diag_dbgfs_dci_finished = 0; + + /* DCI related structures */ + dci_traffic = kzalloc(sizeof(struct diag_dci_data_info) * + DIAG_DCI_DEBUG_CNT, GFP_KERNEL); + if (ZERO_OR_NULL_PTR(dci_traffic)) + pr_warn("diag: could not allocate memory for dci debug info\n"); + + mutex_init(&dci_stat_mutex); + mutex_init(&diag_dci_dbgfs_mutex); + return 0; +err: + kfree(dci_traffic); + debugfs_remove_recursive(diag_dbgfs_dent); + return -ENOMEM; +} + +void diag_debugfs_cleanup(void) +{ + if (diag_dbgfs_dent) { + debugfs_remove_recursive(diag_dbgfs_dent); + diag_dbgfs_dent = NULL; + } + + kfree(dci_traffic); + mutex_destroy(&dci_stat_mutex); + mutex_destroy(&diag_dci_dbgfs_mutex); +} +#else +int diag_debugfs_init(void) { return 0; } +void diag_debugfs_cleanup(void) { } +#endif diff -Nruw linux-4.4.115-fbx/drivers/char/diag./diag_debugfs.h linux-4.4.115-fbx/drivers/char/diag/diag_debugfs.h --- linux-4.4.115-fbx/drivers/char/diag./diag_debugfs.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-4.4.115-fbx/drivers/char/diag/diag_debugfs.h 2019-01-22 16:16:22.955241444 +0100 @@ -0,0 +1,19 @@ +/* Copyright (c) 2012, 2014, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef DIAG_DEBUGFS_H +#define DIAG_DEBUGFS_H + +int diag_debugfs_init(void); +void diag_debugfs_cleanup(void); + +#endif diff -Nruw linux-4.4.115-fbx/drivers/char/diag./diagfwd_bridge.h linux-4.4.115-fbx/drivers/char/diag/diagfwd_bridge.h --- linux-4.4.115-fbx/drivers/char/diag./diagfwd_bridge.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-4.4.115-fbx/drivers/char/diag/diagfwd_bridge.h 2019-10-29 09:26:23.453201319 +0100 @@ -0,0 +1,67 @@ +/* Copyright (c) 2012-2014, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef DIAGFWD_BRIDGE_H +#define DIAGFWD_BRIDGE_H + +/* + * Add Data channels at the top half and the DCI channels at the + * bottom half of this list. + */ +#define DIAGFWD_MDM 0 +#define DIAGFWD_SMUX 1 +#define NUM_REMOTE_DATA_DEV 2 +#define DIAGFWD_MDM_DCI NUM_REMOTE_DATA_DEV +#define NUM_REMOTE_DCI_DEV (DIAGFWD_MDM_DCI - NUM_REMOTE_DATA_DEV + 1) +#define NUM_REMOTE_DEV (NUM_REMOTE_DATA_DEV + NUM_REMOTE_DCI_DEV) + +#define DIAG_BRIDGE_NAME_SZ 24 +#define DIAG_BRIDGE_GET_NAME(x) (bridge_info[x].name) + +struct diag_remote_dev_ops { + int (*open)(int id); + int (*close)(int id); + int (*queue_read)(int id); + int (*write)(int id, unsigned char *buf, int len, int ctxt); + int (*fwd_complete)(int id, unsigned char *buf, int len, int ctxt); +}; + +struct diagfwd_bridge_info { + int id; + int type; + int inited; + int ctxt; + char name[DIAG_BRIDGE_NAME_SZ]; + struct diag_remote_dev_ops *dev_ops; + /* DCI related variables. These would be NULL for data channels */ + void *dci_read_ptr; + unsigned char *dci_read_buf; + int dci_read_len; + struct workqueue_struct *dci_wq; + struct work_struct dci_read_work; +}; + +extern struct diagfwd_bridge_info bridge_info[NUM_REMOTE_DEV]; +int diagfwd_bridge_init(void); +void diagfwd_bridge_exit(void); +int diagfwd_bridge_close(int id); +int diagfwd_bridge_write(int id, unsigned char *buf, int len); +uint16_t diag_get_remote_device_mask(void); + +/* The following functions must be called by Diag remote devices only. */ +int diagfwd_bridge_register(int id, int ctxt, struct diag_remote_dev_ops *ops); +int diag_remote_dev_open(int id); +void diag_remote_dev_close(int id); +int diag_remote_dev_read_done(int id, unsigned char *buf, int len); +int diag_remote_dev_write_done(int id, unsigned char *buf, int len, int ctxt); + +#endif diff -Nruw linux-4.4.115-fbx/drivers/char/diag./diagfwd.c linux-4.4.115-fbx/drivers/char/diag/diagfwd.c --- linux-4.4.115-fbx/drivers/char/diag./diagfwd.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-4.4.115-fbx/drivers/char/diag/diagfwd.c 2019-10-29 09:26:23.453201319 +0100 @@ -0,0 +1,1816 @@ +/* Copyright (c) 2008-2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#ifdef CONFIG_DIAG_OVER_USB +#include +#endif +#include +#include +#include "diagmem.h" +#include "diagchar.h" +#include "diagfwd.h" +#include "diagfwd_peripheral.h" +#include "diagfwd_cntl.h" +#include "diagchar_hdlc.h" +#include "diag_dci.h" +#include "diag_masks.h" +#include "diag_usb.h" +#include "diag_mux.h" +#include "diag_ipc_logging.h" + +#define STM_CMD_VERSION_OFFSET 4 +#define STM_CMD_MASK_OFFSET 5 +#define STM_CMD_DATA_OFFSET 6 +#define STM_CMD_NUM_BYTES 7 + +#define STM_RSP_SUPPORTED_INDEX 7 +#define STM_RSP_STATUS_INDEX 8 +#define STM_RSP_NUM_BYTES 9 +#define RETRY_MAX_COUNT 1000 + +static int timestamp_switch; +module_param(timestamp_switch, int, 0644); + +int wrap_enabled; +uint16_t wrap_count; +static struct diag_hdlc_decode_type *hdlc_decode; + +#define DIAG_NUM_COMMON_CMD 1 +static uint8_t common_cmds[DIAG_NUM_COMMON_CMD] = { + DIAG_CMD_LOG_ON_DMND +}; + +static uint8_t hdlc_timer_in_progress; + +/* Determine if this device uses a device tree */ +#ifdef CONFIG_OF +static int has_device_tree(void) +{ + struct device_node *node; + + node = of_find_node_by_path("/"); + if (node) { + of_node_put(node); + return 1; + } + return 0; +} +#else +static int has_device_tree(void) +{ + return 0; +} +#endif + +int chk_config_get_id(void) +{ + switch (socinfo_get_msm_cpu()) { + case MSM_CPU_8X60: + return APQ8060_TOOLS_ID; + case MSM_CPU_8960: + case MSM_CPU_8960AB: + return AO8960_TOOLS_ID; + case MSM_CPU_8064: + case MSM_CPU_8064AB: + case MSM_CPU_8064AA: + return APQ8064_TOOLS_ID; + case MSM_CPU_8930: + case MSM_CPU_8930AA: + case MSM_CPU_8930AB: + return MSM8930_TOOLS_ID; + case MSM_CPU_8974: + return MSM8974_TOOLS_ID; + case MSM_CPU_8625: + return MSM8625_TOOLS_ID; + case MSM_CPU_8084: + return APQ8084_TOOLS_ID; + case MSM_CPU_8916: + return MSM8916_TOOLS_ID; + case MSM_CPU_8939: + return MSM8939_TOOLS_ID; + case MSM_CPU_8994: + return MSM8994_TOOLS_ID; + case MSM_CPU_8226: + return APQ8026_TOOLS_ID; + case MSM_CPU_8909: + return MSM8909_TOOLS_ID; + case MSM_CPU_8992: + return MSM8992_TOOLS_ID; + case MSM_CPU_8996: + return MSM_8996_TOOLS_ID; + default: + if (driver->use_device_tree) { + if (machine_is_msm8974()) + return MSM8974_TOOLS_ID; + else if (machine_is_apq8074()) + return APQ8074_TOOLS_ID; + else + return 0; + } else { + return 0; + } + } +} + +/* + * This will return TRUE for targets which support apps only mode and hence SSR. + * This applies to 8960 and newer targets. + */ +int chk_apps_only(void) +{ + if (driver->use_device_tree) + return 1; + + switch (socinfo_get_msm_cpu()) { + case MSM_CPU_8960: + case MSM_CPU_8960AB: + case MSM_CPU_8064: + case MSM_CPU_8064AB: + case MSM_CPU_8064AA: + case MSM_CPU_8930: + case MSM_CPU_8930AA: + case MSM_CPU_8930AB: + case MSM_CPU_8627: + case MSM_CPU_9615: + case MSM_CPU_8974: + return 1; + default: + return 0; + } +} + +/* + * This will return TRUE for targets which support apps as master. + * Thus, SW DLOAD and Mode Reset are supported on apps processor. + * This applies to 8960 and newer targets. + */ +int chk_apps_master(void) +{ + if (driver->use_device_tree) + return 1; + else + return 0; +} + +int chk_polling_response(void) +{ + if (!(driver->polling_reg_flag) && chk_apps_master()) + /* + * If the apps processor is master and no other processor + * has registered to respond for polling + */ + return 1; + else if (!(driver->diagfwd_cntl[PERIPHERAL_MODEM] && + driver->diagfwd_cntl[PERIPHERAL_MODEM]->ch_open) && + (driver->feature[PERIPHERAL_MODEM].rcvd_feature_mask)) + /* + * If the apps processor is not the master and the modem + * is not up or we did not receive the feature masks from Modem + */ + return 1; + else + return 0; +} + +/* + * This function should be called if you feel that the logging process may + * need to be woken up. For instance, if the logging mode is MEMORY_DEVICE MODE + * and while trying to read data from data channel there are no buffers + * available to read the data into, then this function should be called to + * determine if the logging process needs to be woken up. + */ +void chk_logging_wakeup(void) +{ + int i; + int j; + int pid = 0; + + for (j = 0; j < NUM_MD_SESSIONS; j++) { + if (!driver->md_session_map[j]) + continue; + pid = driver->md_session_map[j]->pid; + + /* Find the index of the logging process */ + for (i = 0; i < driver->num_clients; i++) { + if (driver->client_map[i].pid != pid) + continue; + if (driver->data_ready[i] & USER_SPACE_DATA_TYPE) + continue; + /* + * At very high logging rates a race condition can + * occur where the buffers containing the data from + * a channel are all in use, but the data_ready flag + * is cleared. In this case, the buffers never have + * their data read/logged. Detect and remedy this + * situation. + */ + driver->data_ready[i] |= USER_SPACE_DATA_TYPE; + atomic_inc(&driver->data_ready_notif[i]); + pr_debug("diag: Force wakeup of logging process\n"); + wake_up_interruptible(&driver->wait_q); + break; + } + /* + * Diag Memory Device is in normal. Check only for the first + * index as all the indices point to the same session + * structure. + */ + if ((driver->md_session_mask == DIAG_CON_ALL) && (j == 0)) + break; + } +} + +static void pack_rsp_and_send(unsigned char *buf, int len, + int pid) +{ + int err; + int retry_count = 0, i, rsp_ctxt; + uint32_t write_len = 0; + unsigned long flags; + unsigned char *rsp_ptr = driver->encoded_rsp_buf; + struct diag_pkt_frame_t header; + struct diag_md_session_t *session_info = NULL, *info = NULL; + + if (!rsp_ptr || !buf) + return; + + if (len > DIAG_MAX_RSP_SIZE || len < 0) { + pr_err("diag: In %s, invalid len %d, permissible len %d\n", + __func__, len, DIAG_MAX_RSP_SIZE); + return; + } + + mutex_lock(&driver->md_session_lock); + session_info = diag_md_session_get_pid(pid); + info = (session_info) ? session_info : + diag_md_session_get_peripheral(APPS_DATA); + + if (info && info->peripheral_mask) { + for (i = 0; i < NUM_MD_SESSIONS; i++) { + if (info->peripheral_mask & (1 << i)) + break; + } + rsp_ctxt = SET_BUF_CTXT(i, TYPE_CMD, TYPE_CMD); + } else + rsp_ctxt = driver->rsp_buf_ctxt; + mutex_unlock(&driver->md_session_lock); + + /* + * Keep trying till we get the buffer back. It should probably + * take one or two iterations. When this loops till RETRY_MAX_COUNT, it + * means we did not get a write complete for the previous + * response. + */ + while (retry_count < RETRY_MAX_COUNT) { + if (!driver->rsp_buf_busy) + break; + /* + * Wait for sometime and try again. The value 10000 was chosen + * empirically as an optimum value for USB to complete a write + */ + usleep_range(10000, 10100); + retry_count++; + + /* + * There can be a race conditon that clears the data ready flag + * for responses. Make sure we don't miss previous wakeups for + * draining responses when we are in Memory Device Mode. + */ + if (driver->logging_mode == DIAG_MEMORY_DEVICE_MODE || + driver->logging_mode == DIAG_MULTI_MODE) { + mutex_lock(&driver->md_session_lock); + chk_logging_wakeup(); + mutex_unlock(&driver->md_session_lock); + } + } + if (driver->rsp_buf_busy) { + pr_err("diag: unable to get hold of response buffer\n"); + return; + } + + driver->rsp_buf_busy = 1; + header.start = CONTROL_CHAR; + header.version = 1; + header.length = len; + memcpy(rsp_ptr, &header, sizeof(header)); + write_len += sizeof(header); + memcpy(rsp_ptr + write_len, buf, len); + write_len += len; + *(uint8_t *)(rsp_ptr + write_len) = CONTROL_CHAR; + write_len += sizeof(uint8_t); + + err = diag_mux_write(DIAG_LOCAL_PROC, rsp_ptr, write_len, rsp_ctxt); + if (err) { + pr_err("diag: In %s, unable to write to mux, err: %d\n", + __func__, err); + spin_lock_irqsave(&driver->rsp_buf_busy_lock, flags); + driver->rsp_buf_busy = 0; + spin_unlock_irqrestore(&driver->rsp_buf_busy_lock, flags); + } +} + +static void encode_rsp_and_send(unsigned char *buf, int len, + int pid) +{ + struct diag_send_desc_type send = { NULL, NULL, DIAG_STATE_START, 0 }; + struct diag_hdlc_dest_type enc = { NULL, NULL, 0 }; + unsigned char *rsp_ptr = driver->encoded_rsp_buf; + int err, i, rsp_ctxt, retry_count = 0; + unsigned long flags; + struct diag_md_session_t *session_info = NULL, *info = NULL; + + if (!rsp_ptr || !buf) + return; + + if (len > DIAG_MAX_RSP_SIZE || len < 0) { + pr_err("diag: In %s, invalid len %d, permissible len %d\n", + __func__, len, DIAG_MAX_RSP_SIZE); + return; + } + + mutex_lock(&driver->md_session_lock); + session_info = diag_md_session_get_pid(pid); + info = (session_info) ? session_info : + diag_md_session_get_peripheral(APPS_DATA); + + if (info && info->peripheral_mask) { + for (i = 0; i < NUM_MD_SESSIONS; i++) { + if (info->peripheral_mask & (1 << i)) + break; + } + rsp_ctxt = SET_BUF_CTXT(i, TYPE_CMD, TYPE_CMD); + } else + rsp_ctxt = driver->rsp_buf_ctxt; + mutex_unlock(&driver->md_session_lock); + /* + * Keep trying till we get the buffer back. It should probably + * take one or two iterations. When this loops till RETRY_MAX_COUNT, it + * means we did not get a write complete for the previous + * response. + */ + while (retry_count < RETRY_MAX_COUNT) { + if (!driver->rsp_buf_busy) + break; + /* + * Wait for sometime and try again. The value 10000 was chosen + * empirically as an optimum value for USB to complete a write + */ + usleep_range(10000, 10100); + retry_count++; + + /* + * There can be a race conditon that clears the data ready flag + * for responses. Make sure we don't miss previous wakeups for + * draining responses when we are in Memory Device Mode. + */ + if (driver->logging_mode == DIAG_MEMORY_DEVICE_MODE || + driver->logging_mode == DIAG_MULTI_MODE) { + mutex_lock(&driver->md_session_lock); + chk_logging_wakeup(); + mutex_unlock(&driver->md_session_lock); + } + } + + if (driver->rsp_buf_busy) { + pr_err("diag: unable to get hold of response buffer\n"); + return; + } + + spin_lock_irqsave(&driver->rsp_buf_busy_lock, flags); + driver->rsp_buf_busy = 1; + spin_unlock_irqrestore(&driver->rsp_buf_busy_lock, flags); + send.state = DIAG_STATE_START; + send.pkt = buf; + send.last = (void *)(buf + len - 1); + send.terminate = 1; + enc.dest = rsp_ptr; + enc.dest_last = (void *)(rsp_ptr + DIAG_MAX_HDLC_BUF_SIZE - 1); + diag_hdlc_encode(&send, &enc); + driver->encoded_rsp_len = (int)(enc.dest - (void *)rsp_ptr); + err = diag_mux_write(DIAG_LOCAL_PROC, rsp_ptr, driver->encoded_rsp_len, + rsp_ctxt); + if (err) { + pr_err("diag: In %s, Unable to write to device, err: %d\n", + __func__, err); + spin_lock_irqsave(&driver->rsp_buf_busy_lock, flags); + driver->rsp_buf_busy = 0; + spin_unlock_irqrestore(&driver->rsp_buf_busy_lock, flags); + } + memset(buf, '\0', DIAG_MAX_RSP_SIZE); +} + +static void diag_send_rsp(unsigned char *buf, int len, int pid) +{ + struct diag_md_session_t *session_info = NULL, *info = NULL; + uint8_t hdlc_disabled; + mutex_lock(&driver->md_session_lock); + info = diag_md_session_get_pid(pid); + session_info = (info) ? info : + diag_md_session_get_peripheral(APPS_DATA); + if (session_info) + hdlc_disabled = session_info->hdlc_disabled; + else + hdlc_disabled = driver->hdlc_disabled; + mutex_unlock(&driver->md_session_lock); + if (hdlc_disabled) + pack_rsp_and_send(buf, len, pid); + else + encode_rsp_and_send(buf, len, pid); +} + +void diag_update_pkt_buffer(unsigned char *buf, uint32_t len, int type) +{ + unsigned char *ptr = NULL; + unsigned char *temp = buf; + int *in_busy = NULL; + uint32_t *length = NULL; + uint32_t max_len = 0; + + if (!buf || len == 0) { + pr_err("diag: In %s, Invalid ptr %pK and length %d\n", + __func__, buf, len); + return; + } + + switch (type) { + case PKT_TYPE: + ptr = driver->apps_req_buf; + length = &driver->apps_req_buf_len; + max_len = DIAG_MAX_REQ_SIZE; + in_busy = &driver->in_busy_pktdata; + break; + case DCI_PKT_TYPE: + ptr = driver->dci_pkt_buf; + length = &driver->dci_pkt_length; + max_len = DCI_BUF_SIZE; + in_busy = &driver->in_busy_dcipktdata; + break; + default: + pr_err("diag: Invalid type %d in %s\n", type, __func__); + return; + } + + mutex_lock(&driver->diagchar_mutex); + if (CHK_OVERFLOW(ptr, ptr, ptr + max_len, len)) { + memcpy(ptr, temp , len); + *length = len; + *in_busy = 1; + } else { + pr_alert("diag: In %s, no space for response packet, len: %d, type: %d\n", + __func__, len, type); + } + mutex_unlock(&driver->diagchar_mutex); +} + +void diag_update_userspace_clients(unsigned int type) +{ + int i; + + mutex_lock(&driver->diagchar_mutex); + for (i = 0; i < driver->num_clients; i++) + if (driver->client_map[i].pid != 0 && + !(driver->data_ready[i] & type)) { + driver->data_ready[i] |= type; + atomic_inc(&driver->data_ready_notif[i]); + } + wake_up_interruptible(&driver->wait_q); + mutex_unlock(&driver->diagchar_mutex); +} + +void diag_update_md_clients(unsigned int type) +{ + int i, j; + + mutex_lock(&driver->diagchar_mutex); + mutex_lock(&driver->md_session_lock); + for (i = 0; i < NUM_MD_SESSIONS; i++) { + if (driver->md_session_map[i] != NULL) + for (j = 0; j < driver->num_clients; j++) { + if (driver->client_map[j].pid != 0 && + driver->client_map[j].pid == + driver->md_session_map[i]->pid) { + if (!(driver->data_ready[j] & type)) { + driver->data_ready[j] |= type; + atomic_inc( + &driver->data_ready_notif[j]); + } + break; + } + } + } + mutex_unlock(&driver->md_session_lock); + wake_up_interruptible(&driver->wait_q); + mutex_unlock(&driver->diagchar_mutex); +} +void diag_update_sleeping_process(int process_id, int data_type) +{ + int i; + + mutex_lock(&driver->diagchar_mutex); + for (i = 0; i < driver->num_clients; i++) + if (driver->client_map[i].pid == process_id) { + if (!(driver->data_ready[i] & data_type)) { + driver->data_ready[i] |= data_type; + atomic_inc(&driver->data_ready_notif[i]); + } + break; + } + wake_up_interruptible(&driver->wait_q); + mutex_unlock(&driver->diagchar_mutex); +} + +static int diag_send_data(struct diag_cmd_reg_t *entry, unsigned char *buf, + int len) +{ + if (!entry) + return -EIO; + + if (entry->proc == APPS_DATA) { + diag_update_pkt_buffer(buf, len, PKT_TYPE); + diag_update_sleeping_process(entry->pid, PKT_TYPE); + return 0; + } + + return diagfwd_write(entry->proc, TYPE_CMD, buf, len); +} + +void diag_process_stm_mask(uint8_t cmd, uint8_t data_mask, int data_type) +{ + int status = 0; + if (data_type >= PERIPHERAL_MODEM && data_type <= PERIPHERAL_SENSORS) { + if (driver->feature[data_type].stm_support) { + status = diag_send_stm_state(data_type, cmd); + if (status == 0) + driver->stm_state[data_type] = cmd; + } + driver->stm_state_requested[data_type] = cmd; + } else if (data_type == APPS_DATA) { + driver->stm_state[data_type] = cmd; + driver->stm_state_requested[data_type] = cmd; + } +} + +int diag_process_stm_cmd(unsigned char *buf, unsigned char *dest_buf) +{ + uint8_t version, mask, cmd; + uint8_t rsp_supported = 0; + uint8_t rsp_status = 0; + int i; + + if (!buf || !dest_buf) { + pr_err("diag: Invalid pointers buf: %pK, dest_buf %pK in %s\n", + buf, dest_buf, __func__); + return -EIO; + } + + version = *(buf + STM_CMD_VERSION_OFFSET); + mask = *(buf + STM_CMD_MASK_OFFSET); + cmd = *(buf + STM_CMD_DATA_OFFSET); + + /* + * Check if command is valid. If the command is asking for + * status, then the processor mask field is to be ignored. + */ + if ((version != 2) || (cmd > STATUS_STM) || + ((cmd != STATUS_STM) && ((mask == 0) || (0 != (mask >> 4))))) { + /* Command is invalid. Send bad param message response */ + dest_buf[0] = BAD_PARAM_RESPONSE_MESSAGE; + for (i = 0; i < STM_CMD_NUM_BYTES; i++) + dest_buf[i+1] = *(buf + i); + return STM_CMD_NUM_BYTES+1; + } else if (cmd != STATUS_STM) { + if (mask & DIAG_STM_MODEM) + diag_process_stm_mask(cmd, DIAG_STM_MODEM, + PERIPHERAL_MODEM); + + if (mask & DIAG_STM_LPASS) + diag_process_stm_mask(cmd, DIAG_STM_LPASS, + PERIPHERAL_LPASS); + + if (mask & DIAG_STM_WCNSS) + diag_process_stm_mask(cmd, DIAG_STM_WCNSS, + PERIPHERAL_WCNSS); + + if (mask & DIAG_STM_SENSORS) + diag_process_stm_mask(cmd, DIAG_STM_SENSORS, + PERIPHERAL_SENSORS); + if (mask & DIAG_STM_WDSP) + diag_process_stm_mask(cmd, DIAG_STM_WDSP, + PERIPHERAL_WDSP); + + if (mask & DIAG_STM_APPS) + diag_process_stm_mask(cmd, DIAG_STM_APPS, APPS_DATA); + } + + for (i = 0; i < STM_CMD_NUM_BYTES; i++) + dest_buf[i] = *(buf + i); + + /* Set mask denoting which peripherals support STM */ + if (driver->feature[PERIPHERAL_MODEM].stm_support) + rsp_supported |= DIAG_STM_MODEM; + + if (driver->feature[PERIPHERAL_LPASS].stm_support) + rsp_supported |= DIAG_STM_LPASS; + + if (driver->feature[PERIPHERAL_WCNSS].stm_support) + rsp_supported |= DIAG_STM_WCNSS; + + if (driver->feature[PERIPHERAL_SENSORS].stm_support) + rsp_supported |= DIAG_STM_SENSORS; + + if (driver->feature[PERIPHERAL_WDSP].stm_support) + rsp_supported |= DIAG_STM_WDSP; + + rsp_supported |= DIAG_STM_APPS; + + /* Set mask denoting STM state/status for each peripheral/APSS */ + if (driver->stm_state[PERIPHERAL_MODEM]) + rsp_status |= DIAG_STM_MODEM; + + if (driver->stm_state[PERIPHERAL_LPASS]) + rsp_status |= DIAG_STM_LPASS; + + if (driver->stm_state[PERIPHERAL_WCNSS]) + rsp_status |= DIAG_STM_WCNSS; + + if (driver->stm_state[PERIPHERAL_SENSORS]) + rsp_status |= DIAG_STM_SENSORS; + + if (driver->stm_state[PERIPHERAL_WDSP]) + rsp_status |= DIAG_STM_WDSP; + + if (driver->stm_state[APPS_DATA]) + rsp_status |= DIAG_STM_APPS; + + dest_buf[STM_RSP_SUPPORTED_INDEX] = rsp_supported; + dest_buf[STM_RSP_STATUS_INDEX] = rsp_status; + + return STM_RSP_NUM_BYTES; +} + +int diag_process_time_sync_query_cmd(unsigned char *src_buf, int src_len, + unsigned char *dest_buf, int dest_len) +{ + int write_len = 0; + struct diag_cmd_time_sync_query_req_t *req = NULL; + struct diag_cmd_time_sync_query_rsp_t rsp; + + if (!src_buf || !dest_buf || src_len <= 0 || dest_len <= 0) { + pr_err("diag: Invalid input in %s, src_buf: %pK, src_len: %d, dest_buf: %pK, dest_len: %d", + __func__, src_buf, src_len, dest_buf, dest_len); + return -EINVAL; + } + + req = (struct diag_cmd_time_sync_query_req_t *)src_buf; + rsp.header.cmd_code = req->header.cmd_code; + rsp.header.subsys_id = req->header.subsys_id; + rsp.header.subsys_cmd_code = req->header.subsys_cmd_code; + rsp.version = req->version; + rsp.time_api = driver->uses_time_api; + memcpy(dest_buf, &rsp, sizeof(rsp)); + write_len = sizeof(rsp); + return write_len; +} + +int diag_process_time_sync_switch_cmd(unsigned char *src_buf, int src_len, + unsigned char *dest_buf, int dest_len) +{ + uint8_t peripheral, status = 0; + struct diag_cmd_time_sync_switch_req_t *req = NULL; + struct diag_cmd_time_sync_switch_rsp_t rsp; + struct diag_ctrl_msg_time_sync time_sync_msg; + int msg_size = sizeof(struct diag_ctrl_msg_time_sync); + int err = 0, write_len = 0; + + if (!src_buf || !dest_buf || src_len <= 0 || dest_len <= 0) { + pr_err("diag: Invalid input in %s, src_buf: %pK, src_len: %d, dest_buf: %pK, dest_len: %d", + __func__, src_buf, src_len, dest_buf, dest_len); + return -EINVAL; + } + + req = (struct diag_cmd_time_sync_switch_req_t *)src_buf; + rsp.header.cmd_code = req->header.cmd_code; + rsp.header.subsys_id = req->header.subsys_id; + rsp.header.subsys_cmd_code = req->header.subsys_cmd_code; + rsp.version = req->version; + rsp.time_api = req->time_api; + if ((req->version > 1) || (req->time_api > 1) || + (req->persist_time > 0)) { + dest_buf[0] = BAD_PARAM_RESPONSE_MESSAGE; + rsp.time_api_status = 0; + rsp.persist_time_status = PERSIST_TIME_NOT_SUPPORTED; + memcpy(dest_buf + 1, &rsp, sizeof(rsp)); + write_len = sizeof(rsp) + 1; + timestamp_switch = 0; + return write_len; + } + + time_sync_msg.ctrl_pkt_id = DIAG_CTRL_MSG_TIME_SYNC_PKT; + time_sync_msg.ctrl_pkt_data_len = 5; + time_sync_msg.version = 1; + time_sync_msg.time_api = req->time_api; + + for (peripheral = 0; peripheral < NUM_PERIPHERALS; peripheral++) { + err = diagfwd_write(peripheral, TYPE_CNTL, &time_sync_msg, + msg_size); + if (err && err != -ENODEV) { + pr_err("diag: In %s, unable to write to peripheral: %d, type: %d, len: %d, err: %d\n", + __func__, peripheral, TYPE_CNTL, + msg_size, err); + status |= (1 << peripheral); + } + } + + driver->time_sync_enabled = 1; + driver->uses_time_api = req->time_api; + + switch (req->time_api) { + case 0: + timestamp_switch = 0; + break; + case 1: + timestamp_switch = 1; + break; + default: + timestamp_switch = 0; + break; + } + + rsp.time_api_status = status; + rsp.persist_time_status = PERSIST_TIME_NOT_SUPPORTED; + memcpy(dest_buf, &rsp, sizeof(rsp)); + write_len = sizeof(rsp); + return write_len; +} + +int diag_cmd_log_on_demand(unsigned char *src_buf, int src_len, + unsigned char *dest_buf, int dest_len) +{ + int write_len = 0; + struct diag_log_on_demand_rsp_t header; + + if (!driver->diagfwd_cntl[PERIPHERAL_MODEM] || + !driver->diagfwd_cntl[PERIPHERAL_MODEM]->ch_open || + !driver->log_on_demand_support) + return 0; + + if (!src_buf || !dest_buf || src_len <= 0 || dest_len <= 0) { + pr_err("diag: Invalid input in %s, src_buf: %pK, src_len: %d, dest_buf: %pK, dest_len: %d", + __func__, src_buf, src_len, dest_buf, dest_len); + return -EINVAL; + } + + header.cmd_code = DIAG_CMD_LOG_ON_DMND; + header.log_code = *(uint16_t *)(src_buf + 1); + header.status = 1; + memcpy(dest_buf, &header, sizeof(struct diag_log_on_demand_rsp_t)); + write_len += sizeof(struct diag_log_on_demand_rsp_t); + + return write_len; +} + +int diag_cmd_get_mobile_id(unsigned char *src_buf, int src_len, + unsigned char *dest_buf, int dest_len) +{ + int write_len = 0; + struct diag_pkt_header_t *header = NULL; + struct diag_cmd_ext_mobile_rsp_t rsp; + + if (!src_buf || src_len != sizeof(*header) || !dest_buf || + dest_len < sizeof(rsp)) + return -EIO; + + header = (struct diag_pkt_header_t *)src_buf; + rsp.header.cmd_code = header->cmd_code; + rsp.header.subsys_id = header->subsys_id; + rsp.header.subsys_cmd_code = header->subsys_cmd_code; + rsp.version = 2; + rsp.padding[0] = 0; + rsp.padding[1] = 0; + rsp.padding[2] = 0; + rsp.family = 0; + rsp.chip_id = (uint32_t)socinfo_get_id(); + + memcpy(dest_buf, &rsp, sizeof(rsp)); + write_len += sizeof(rsp); + + return write_len; +} + +int diag_check_common_cmd(struct diag_pkt_header_t *header) +{ + int i; + + if (!header) + return -EIO; + + for (i = 0; i < DIAG_NUM_COMMON_CMD; i++) { + if (header->cmd_code == common_cmds[i]) + return 1; + } + + return 0; +} + +#ifdef CONFIG_DIAG_OVER_USB +static int diag_cmd_chk_stats(unsigned char *src_buf, int src_len, + unsigned char *dest_buf, int dest_len) +{ + int payload = 0; + int write_len = 0; + struct diag_pkt_header_t *header = NULL; + struct diag_cmd_stats_rsp_t rsp; + + if (!src_buf || src_len < sizeof(struct diag_pkt_header_t) || + !dest_buf || dest_len < sizeof(rsp)) + return -EINVAL; + + header = (struct diag_pkt_header_t *)src_buf; + + if (header->cmd_code != DIAG_CMD_DIAG_SUBSYS || + header->subsys_id != DIAG_SS_DIAG) + return -EINVAL; + + switch (header->subsys_cmd_code) { + case DIAG_CMD_OP_GET_MSG_ALLOC: + payload = driver->msg_stats.alloc_count; + break; + case DIAG_CMD_OP_GET_MSG_DROP: + payload = driver->msg_stats.drop_count; + break; + case DIAG_CMD_OP_RESET_MSG_STATS: + diag_record_stats(DATA_TYPE_F3, PKT_RESET); + break; + case DIAG_CMD_OP_GET_LOG_ALLOC: + payload = driver->log_stats.alloc_count; + break; + case DIAG_CMD_OP_GET_LOG_DROP: + payload = driver->log_stats.drop_count; + break; + case DIAG_CMD_OP_RESET_LOG_STATS: + diag_record_stats(DATA_TYPE_LOG, PKT_RESET); + break; + case DIAG_CMD_OP_GET_EVENT_ALLOC: + payload = driver->event_stats.alloc_count; + break; + case DIAG_CMD_OP_GET_EVENT_DROP: + payload = driver->event_stats.drop_count; + break; + case DIAG_CMD_OP_RESET_EVENT_STATS: + diag_record_stats(DATA_TYPE_EVENT, PKT_RESET); + break; + default: + return -EINVAL; + } + + memcpy(&rsp.header, header, sizeof(struct diag_pkt_header_t)); + rsp.payload = payload; + write_len = sizeof(rsp); + memcpy(dest_buf, &rsp, sizeof(rsp)); + + return write_len; +} + +static int diag_cmd_disable_hdlc(unsigned char *src_buf, int src_len, + unsigned char *dest_buf, int dest_len) +{ + struct diag_pkt_header_t *header = NULL; + struct diag_cmd_hdlc_disable_rsp_t rsp; + int write_len = 0; + + if (!src_buf || src_len < sizeof(*header) || + !dest_buf || dest_len < sizeof(rsp)) { + return -EIO; + } + + header = (struct diag_pkt_header_t *)src_buf; + if (header->cmd_code != DIAG_CMD_DIAG_SUBSYS || + header->subsys_id != DIAG_SS_DIAG || + header->subsys_cmd_code != DIAG_CMD_OP_HDLC_DISABLE) { + return -EINVAL; + } + + memcpy(&rsp.header, header, sizeof(struct diag_pkt_header_t)); + rsp.framing_version = 1; + rsp.result = 0; + write_len = sizeof(rsp); + memcpy(dest_buf, &rsp, sizeof(rsp)); + + return write_len; +} +#endif + +void diag_send_error_rsp(unsigned char *buf, int len, + int pid) +{ + /* -1 to accomodate the first byte 0x13 */ + if (len > (DIAG_MAX_RSP_SIZE - 1)) { + pr_err("diag: cannot send err rsp, huge length: %d\n", len); + return; + } + + *(uint8_t *)driver->apps_rsp_buf = DIAG_CMD_ERROR; + memcpy((driver->apps_rsp_buf + sizeof(uint8_t)), buf, len); + diag_send_rsp(driver->apps_rsp_buf, len + 1, pid); +} + +int diag_process_apps_pkt(unsigned char *buf, int len, int pid) +{ + int p_mask = 0; + int mask_ret; + int write_len = 0; + unsigned char *temp = NULL; + struct diag_cmd_reg_entry_t entry; + struct diag_cmd_reg_entry_t *temp_entry = NULL; + struct diag_cmd_reg_t *reg_item = NULL; + struct diag_md_session_t *info = NULL; + + if (!buf) + return -EIO; + + /* Check if the command is a supported mask command */ + mask_ret = diag_process_apps_masks(buf, len, pid); + if (mask_ret > 0) { + diag_send_rsp(driver->apps_rsp_buf, mask_ret, pid); + return 0; + } + + temp = buf; + entry.cmd_code = (uint16_t)(*(uint8_t *)temp); + temp += sizeof(uint8_t); + entry.subsys_id = (uint16_t)(*(uint8_t *)temp); + temp += sizeof(uint8_t); + entry.cmd_code_hi = (uint16_t)(*(uint16_t *)temp); + entry.cmd_code_lo = (uint16_t)(*(uint16_t *)temp); + temp += sizeof(uint16_t); + + pr_debug("diag: In %s, received cmd %02x %02x %02x\n", + __func__, entry.cmd_code, entry.subsys_id, entry.cmd_code_hi); + + if (*buf == DIAG_CMD_LOG_ON_DMND && driver->log_on_demand_support && + driver->feature[PERIPHERAL_MODEM].rcvd_feature_mask) { + write_len = diag_cmd_log_on_demand(buf, len, + driver->apps_rsp_buf, + DIAG_MAX_RSP_SIZE); + if (write_len > 0) + diag_send_rsp(driver->apps_rsp_buf, write_len, pid); + return 0; + } + + mutex_lock(&driver->cmd_reg_mutex); + temp_entry = diag_cmd_search(&entry, ALL_PROC); + if (temp_entry) { + reg_item = container_of(temp_entry, struct diag_cmd_reg_t, + entry); + mutex_lock(&driver->md_session_lock); + info = diag_md_session_get_pid(pid); + if (info) { + p_mask = info->peripheral_mask; + mutex_unlock(&driver->md_session_lock); + if (MD_PERIPHERAL_MASK(reg_item->proc) & p_mask) + write_len = diag_send_data(reg_item, buf, len); + } else { + mutex_unlock(&driver->md_session_lock); + if (MD_PERIPHERAL_MASK(reg_item->proc) & + driver->logging_mask) + diag_send_error_rsp(buf, len, pid); + else + write_len = diag_send_data(reg_item, buf, len); + } + mutex_unlock(&driver->cmd_reg_mutex); + return write_len; + } + mutex_unlock(&driver->cmd_reg_mutex); + +#if defined(CONFIG_DIAG_OVER_USB) + /* Check for the command/respond msg for the maximum packet length */ + if ((*buf == 0x4b) && (*(buf+1) == 0x12) && + (*(uint16_t *)(buf+2) == 0x0055)) { + int i; + for (i = 0; i < 4; i++) + *(driver->apps_rsp_buf+i) = *(buf+i); + *(uint32_t *)(driver->apps_rsp_buf+4) = DIAG_MAX_REQ_SIZE; + diag_send_rsp(driver->apps_rsp_buf, 8, pid); + return 0; + } else if ((*buf == 0x4b) && (*(buf+1) == 0x12) && + (*(uint16_t *)(buf+2) == DIAG_DIAG_STM)) { + len = diag_process_stm_cmd(buf, driver->apps_rsp_buf); + if (len > 0) { + diag_send_rsp(driver->apps_rsp_buf, len, pid); + return 0; + } + return len; + } + /* Check for time sync query command */ + else if ((*buf == DIAG_CMD_DIAG_SUBSYS) && + (*(buf+1) == DIAG_SS_DIAG) && + (*(uint16_t *)(buf+2) == DIAG_GET_TIME_API)) { + write_len = diag_process_time_sync_query_cmd(buf, len, + driver->apps_rsp_buf, + DIAG_MAX_RSP_SIZE); + if (write_len > 0) + diag_send_rsp(driver->apps_rsp_buf, write_len, pid); + return 0; + } + /* Check for time sync switch command */ + else if ((*buf == DIAG_CMD_DIAG_SUBSYS) && + (*(buf+1) == DIAG_SS_DIAG) && + (*(uint16_t *)(buf+2) == DIAG_SET_TIME_API)) { + write_len = diag_process_time_sync_switch_cmd(buf, len, + driver->apps_rsp_buf, + DIAG_MAX_RSP_SIZE); + if (write_len > 0) + diag_send_rsp(driver->apps_rsp_buf, write_len, pid); + return 0; + } + /* Check for download command */ + else if ((chk_apps_master()) && (*buf == 0x3A)) { + /* send response back */ + driver->apps_rsp_buf[0] = *buf; + diag_send_rsp(driver->apps_rsp_buf, 1, pid); + msleep(5000); + /* call download API */ + msm_set_restart_mode(RESTART_DLOAD); + printk(KERN_CRIT "diag: download mode set, Rebooting SoC..\n"); + kernel_restart(NULL); + /* Not required, represents that command isnt sent to modem */ + return 0; + } + /* Check for polling for Apps only DIAG */ + else if ((*buf == 0x4b) && (*(buf+1) == 0x32) && + (*(buf+2) == 0x03)) { + /* If no one has registered for polling */ + if (chk_polling_response()) { + int i; + /* Respond to polling for Apps only DIAG */ + for (i = 0; i < 3; i++) + driver->apps_rsp_buf[i] = *(buf+i); + for (i = 0; i < 13; i++) + driver->apps_rsp_buf[i+3] = 0; + + diag_send_rsp(driver->apps_rsp_buf, 16, pid); + return 0; + } + } + /* Return the Delayed Response Wrap Status */ + else if ((*buf == 0x4b) && (*(buf+1) == 0x32) && + (*(buf+2) == 0x04) && (*(buf+3) == 0x0)) { + memcpy(driver->apps_rsp_buf, buf, 4); + driver->apps_rsp_buf[4] = wrap_enabled; + diag_send_rsp(driver->apps_rsp_buf, 5, pid); + return 0; + } + /* Wrap the Delayed Rsp ID */ + else if ((*buf == 0x4b) && (*(buf+1) == 0x32) && + (*(buf+2) == 0x05) && (*(buf+3) == 0x0)) { + wrap_enabled = true; + memcpy(driver->apps_rsp_buf, buf, 4); + driver->apps_rsp_buf[4] = wrap_count; + diag_send_rsp(driver->apps_rsp_buf, 6, pid); + return 0; + } + /* Mobile ID Rsp */ + else if ((*buf == DIAG_CMD_DIAG_SUBSYS) && + (*(buf+1) == DIAG_SS_PARAMS) && + (*(buf+2) == DIAG_EXT_MOBILE_ID) && (*(buf+3) == 0x0)) { + write_len = diag_cmd_get_mobile_id(buf, len, + driver->apps_rsp_buf, + DIAG_MAX_RSP_SIZE); + if (write_len > 0) { + diag_send_rsp(driver->apps_rsp_buf, write_len, pid); + return 0; + } + } + /* + * If the apps processor is master and no other + * processor has registered for polling command. + * If modem is not up and we have not received feature + * mask update from modem, in that case APPS should + * respond for 0X7C command + */ + else if (chk_apps_master() && + !(driver->polling_reg_flag) && + !(driver->diagfwd_cntl[PERIPHERAL_MODEM]->ch_open) && + !(driver->feature[PERIPHERAL_MODEM].rcvd_feature_mask)) { + int i; + /* respond to 0x0 command */ + if (*buf == 0x00) { + for (i = 0; i < 55; i++) + driver->apps_rsp_buf[i] = 0; + + diag_send_rsp(driver->apps_rsp_buf, 55, pid); + return 0; + } + /* respond to 0x7c command */ + else if (*buf == 0x7c) { + driver->apps_rsp_buf[0] = 0x7c; + for (i = 1; i < 8; i++) + driver->apps_rsp_buf[i] = 0; + /* Tools ID for APQ 8060 */ + *(int *)(driver->apps_rsp_buf + 8) = + chk_config_get_id(); + *(unsigned char *)(driver->apps_rsp_buf + 12) = '\0'; + *(unsigned char *)(driver->apps_rsp_buf + 13) = '\0'; + diag_send_rsp(driver->apps_rsp_buf, 14, pid); + return 0; + } + } + write_len = diag_cmd_chk_stats(buf, len, driver->apps_rsp_buf, + DIAG_MAX_RSP_SIZE); + if (write_len > 0) { + diag_send_rsp(driver->apps_rsp_buf, write_len, pid); + return 0; + } + write_len = diag_cmd_disable_hdlc(buf, len, driver->apps_rsp_buf, + DIAG_MAX_RSP_SIZE); + if (write_len > 0) { + /* + * This mutex lock is necessary since we need to drain all the + * pending buffers from peripherals which may be HDLC encoded + * before disabling HDLC encoding on Apps processor. + */ + mutex_lock(&driver->hdlc_disable_mutex); + diag_send_rsp(driver->apps_rsp_buf, write_len, pid); + /* + * Set the value of hdlc_disabled after sending the response to + * the tools. This is required since the tools is expecting a + * HDLC encoded reponse for this request. + */ + pr_debug("diag: In %s, disabling HDLC encoding\n", + __func__); + mutex_lock(&driver->md_session_lock); + info = diag_md_session_get_pid(pid); + if (info) + info->hdlc_disabled = 1; + else + driver->hdlc_disabled = 1; + mutex_unlock(&driver->md_session_lock); + diag_update_md_clients(HDLC_SUPPORT_TYPE); + mutex_unlock(&driver->hdlc_disable_mutex); + return 0; + } +#endif + + /* We have now come to the end of the function. */ + if (chk_apps_only()) + diag_send_error_rsp(buf, len, pid); + + return 0; +} + +void diag_process_hdlc_pkt(void *data, unsigned int len, int pid) +{ + int err = 0; + int ret = 0; + + if (len > DIAG_MAX_HDLC_BUF_SIZE) { + pr_err("diag: In %s, invalid length: %d\n", __func__, len); + return; + } + + mutex_lock(&driver->diag_hdlc_mutex); + pr_debug("diag: In %s, received packet of length: %d, req_buf_len: %d\n", + __func__, len, driver->hdlc_buf_len); + + if (driver->hdlc_buf_len >= DIAG_MAX_REQ_SIZE) { + pr_err("diag: In %s, request length is more than supported len. Dropping packet.\n", + __func__); + goto fail; + } + + hdlc_decode->dest_ptr = driver->hdlc_buf + driver->hdlc_buf_len; + hdlc_decode->dest_size = DIAG_MAX_HDLC_BUF_SIZE - driver->hdlc_buf_len; + hdlc_decode->src_ptr = data; + hdlc_decode->src_size = len; + hdlc_decode->src_idx = 0; + hdlc_decode->dest_idx = 0; + + ret = diag_hdlc_decode(hdlc_decode); + /* + * driver->hdlc_buf is of size DIAG_MAX_HDLC_BUF_SIZE. But the decoded + * packet should be within DIAG_MAX_REQ_SIZE. + */ + if (driver->hdlc_buf_len + hdlc_decode->dest_idx <= DIAG_MAX_REQ_SIZE) { + driver->hdlc_buf_len += hdlc_decode->dest_idx; + } else { + pr_err_ratelimited("diag: In %s, Dropping packet. pkt_size: %d, max: %d\n", + __func__, + driver->hdlc_buf_len + hdlc_decode->dest_idx, + DIAG_MAX_REQ_SIZE); + goto fail; + } + + if (ret == HDLC_COMPLETE) { + err = crc_check(driver->hdlc_buf, driver->hdlc_buf_len); + if (err) { + /* CRC check failed. */ + pr_err_ratelimited("diag: In %s, bad CRC. Dropping packet\n", + __func__); + goto fail; + } + driver->hdlc_buf_len -= HDLC_FOOTER_LEN; + + if (driver->hdlc_buf_len < 1) { + pr_err_ratelimited("diag: In %s, message is too short, len: %d, dest len: %d\n", + __func__, driver->hdlc_buf_len, + hdlc_decode->dest_idx); + goto fail; + } + + err = diag_process_apps_pkt(driver->hdlc_buf, + driver->hdlc_buf_len, pid); + if (err < 0) + goto fail; + } else { + goto end; + } + + driver->hdlc_buf_len = 0; + mutex_unlock(&driver->diag_hdlc_mutex); + return; + +fail: + /* + * Tools needs to get a response in order to start its + * recovery algorithm. Send an error response if the + * packet is not in expected format. + */ + diag_send_error_rsp(driver->hdlc_buf, driver->hdlc_buf_len, pid); + driver->hdlc_buf_len = 0; +end: + mutex_unlock(&driver->diag_hdlc_mutex); +} + +static int diagfwd_mux_open(int id, int mode) +{ + uint8_t i; + unsigned long flags; + + switch (mode) { +#ifdef CONFIG_DIAG_OVER_USB + case DIAG_USB_MODE: + driver->usb_connected = 1; + break; +#endif + case DIAG_MEMORY_DEVICE_MODE: + break; + default: + return -EINVAL; + } + + if (driver->rsp_buf_busy) { + /* + * When a client switches from callback mode to USB mode + * explicitly, there can be a situation when the last response + * is not drained to the user space application. Reset the + * in_busy flag in this case. + */ + spin_lock_irqsave(&driver->rsp_buf_busy_lock, flags); + driver->rsp_buf_busy = 0; + spin_unlock_irqrestore(&driver->rsp_buf_busy_lock, flags); + } + for (i = 0; i < NUM_PERIPHERALS; i++) { + diagfwd_open(i, TYPE_DATA); + diagfwd_open(i, TYPE_CMD); + } + queue_work(driver->diag_real_time_wq, &driver->diag_real_time_work); + return 0; +} + +static int diagfwd_mux_close(int id, int mode) +{ + uint8_t i; + + switch (mode) { +#ifdef CONFIG_DIAG_OVER_USB + case DIAG_USB_MODE: + driver->usb_connected = 0; + break; +#endif + case DIAG_MEMORY_DEVICE_MODE: + break; + default: + return -EINVAL; + } + + if ((driver->logging_mode == DIAG_MULTI_MODE && + driver->md_session_mode == DIAG_MD_NONE) || + (driver->md_session_mode == DIAG_MD_PERIPHERAL)) { + /* + * This case indicates that the USB is removed + * but there is a client running in background + * with Memory Device mode. + */ + } else { + /* + * With sysfs parameter to clear masks set, + * peripheral masks are cleared on ODL exit and + * USB disconnection and buffers are not marked busy. + * This enables read and drop of stale packets. + * + * With sysfs parameter to clear masks cleared, + * masks are not cleared and buffers are to be marked + * busy to ensure traffic generated by peripheral + * are not read + */ + if (!(diag_mask_param())) { + for (i = 0; i < NUM_PERIPHERALS; i++) { + diagfwd_close(i, TYPE_DATA); + diagfwd_close(i, TYPE_CMD); + } + } + /* Re enable HDLC encoding */ + pr_debug("diag: In %s, re-enabling HDLC encoding\n", + __func__); + mutex_lock(&driver->hdlc_disable_mutex); + if (driver->md_session_mode == DIAG_MD_NONE) + driver->hdlc_disabled = 0; + mutex_unlock(&driver->hdlc_disable_mutex); + queue_work(driver->diag_wq, + &(driver->update_user_clients)); + } + queue_work(driver->diag_real_time_wq, + &driver->diag_real_time_work); + return 0; +} + +static uint8_t hdlc_reset; + +static void hdlc_reset_timer_start(int pid) +{ + struct diag_md_session_t *info = NULL; + mutex_lock(&driver->md_session_lock); + info = diag_md_session_get_pid(pid); + if (!hdlc_timer_in_progress) { + hdlc_timer_in_progress = 1; + if (info) + mod_timer(&info->hdlc_reset_timer, + jiffies + msecs_to_jiffies(200)); + else + mod_timer(&driver->hdlc_reset_timer, + jiffies + msecs_to_jiffies(200)); + } + mutex_unlock(&driver->md_session_lock); +} + +static void hdlc_reset_timer_func(unsigned long data) +{ + pr_debug("diag: In %s, re-enabling HDLC encoding\n", + __func__); + if (hdlc_reset) { + driver->hdlc_disabled = 0; + queue_work(driver->diag_wq, + &(driver->update_user_clients)); + } + hdlc_timer_in_progress = 0; +} + +void diag_md_hdlc_reset_timer_func(unsigned long pid) +{ + struct diag_md_session_t *session_info = NULL; + + pr_debug("diag: In %s, re-enabling HDLC encoding\n", + __func__); + if (hdlc_reset) { + session_info = diag_md_session_get_pid(pid); + if (session_info) + session_info->hdlc_disabled = 0; + queue_work(driver->diag_wq, + &(driver->update_md_clients)); + } + hdlc_timer_in_progress = 0; +} + +static void diag_hdlc_start_recovery(unsigned char *buf, int len, + int pid) +{ + int i; + static uint32_t bad_byte_counter; + unsigned char *start_ptr = NULL; + struct diag_pkt_frame_t *actual_pkt = NULL; + struct diag_md_session_t *info = NULL; + + hdlc_reset = 1; + hdlc_reset_timer_start(pid); + + actual_pkt = (struct diag_pkt_frame_t *)buf; + for (i = 0; i < len; i++) { + if (actual_pkt->start == CONTROL_CHAR && + actual_pkt->version == 1 && + actual_pkt->length < len && + (*(uint8_t *)(buf + sizeof(struct diag_pkt_frame_t) + + actual_pkt->length) == CONTROL_CHAR)) { + start_ptr = &buf[i]; + break; + } + bad_byte_counter++; + if (bad_byte_counter > (DIAG_MAX_REQ_SIZE + + sizeof(struct diag_pkt_frame_t) + 1)) { + bad_byte_counter = 0; + pr_err("diag: In %s, re-enabling HDLC encoding\n", + __func__); + mutex_lock(&driver->hdlc_disable_mutex); + mutex_lock(&driver->md_session_lock); + info = diag_md_session_get_pid(pid); + if (info) + info->hdlc_disabled = 0; + else + driver->hdlc_disabled = 0; + mutex_unlock(&driver->md_session_lock); + mutex_unlock(&driver->hdlc_disable_mutex); + diag_update_md_clients(HDLC_SUPPORT_TYPE); + + return; + } + } + + if (start_ptr) { + /* Discard any partial packet reads */ + mutex_lock(&driver->hdlc_recovery_mutex); + driver->incoming_pkt.processing = 0; + mutex_unlock(&driver->hdlc_recovery_mutex); + diag_process_non_hdlc_pkt(start_ptr, len - i, pid); + } +} + +void diag_process_non_hdlc_pkt(unsigned char *buf, int len, int pid) +{ + int err = 0; + uint16_t pkt_len = 0; + uint32_t read_bytes = 0; + const uint32_t header_len = sizeof(struct diag_pkt_frame_t); + struct diag_pkt_frame_t *actual_pkt = NULL; + unsigned char *data_ptr = NULL; + struct diag_partial_pkt_t *partial_pkt = NULL; + + mutex_lock(&driver->hdlc_recovery_mutex); + if (!buf || len <= 0) { + mutex_unlock(&driver->hdlc_recovery_mutex); + return; + } + partial_pkt = &driver->incoming_pkt; + if (!partial_pkt->processing) { + mutex_unlock(&driver->hdlc_recovery_mutex); + goto start; + } + + if (partial_pkt->remaining > len) { + if ((partial_pkt->read_len + len) > partial_pkt->capacity) { + pr_err("diag: Invalid length %d, %d received in %s\n", + partial_pkt->read_len, len, __func__); + mutex_unlock(&driver->hdlc_recovery_mutex); + goto end; + } + memcpy(partial_pkt->data + partial_pkt->read_len, buf, len); + read_bytes += len; + buf += read_bytes; + partial_pkt->read_len += len; + partial_pkt->remaining -= len; + } else { + if ((partial_pkt->read_len + partial_pkt->remaining) > + partial_pkt->capacity) { + pr_err("diag: Invalid length during partial read %d, %d received in %s\n", + partial_pkt->read_len, + partial_pkt->remaining, __func__); + mutex_unlock(&driver->hdlc_recovery_mutex); + goto end; + } + memcpy(partial_pkt->data + partial_pkt->read_len, buf, + partial_pkt->remaining); + read_bytes += partial_pkt->remaining; + buf += read_bytes; + partial_pkt->read_len += partial_pkt->remaining; + partial_pkt->remaining = 0; + } + + if (partial_pkt->remaining == 0) { + actual_pkt = (struct diag_pkt_frame_t *)(partial_pkt->data); + data_ptr = partial_pkt->data + header_len; + if (*(uint8_t *)(data_ptr + actual_pkt->length) != + CONTROL_CHAR) { + mutex_unlock(&driver->hdlc_recovery_mutex); + diag_hdlc_start_recovery(buf, len, pid); + mutex_lock(&driver->hdlc_recovery_mutex); + } + err = diag_process_apps_pkt(data_ptr, + actual_pkt->length, pid); + if (err) { + pr_err("diag: In %s, unable to process incoming data packet, err: %d\n", + __func__, err); + mutex_unlock(&driver->hdlc_recovery_mutex); + goto end; + } + partial_pkt->read_len = 0; + partial_pkt->total_len = 0; + partial_pkt->processing = 0; + mutex_unlock(&driver->hdlc_recovery_mutex); + goto start; + } + mutex_unlock(&driver->hdlc_recovery_mutex); + goto end; + +start: + while (read_bytes < len) { + actual_pkt = (struct diag_pkt_frame_t *)buf; + pkt_len = actual_pkt->length; + + if (actual_pkt->start != CONTROL_CHAR) { + diag_hdlc_start_recovery(buf, len, pid); + diag_send_error_rsp(buf, len, pid); + goto end; + } + mutex_lock(&driver->hdlc_recovery_mutex); + if (pkt_len + header_len > partial_pkt->capacity) { + pr_err("diag: In %s, incoming data is too large for the request buffer %d\n", + __func__, pkt_len); + mutex_unlock(&driver->hdlc_recovery_mutex); + diag_hdlc_start_recovery(buf, len, pid); + break; + } + if ((pkt_len + header_len) > (len - read_bytes)) { + partial_pkt->read_len = len - read_bytes; + partial_pkt->total_len = pkt_len + header_len; + partial_pkt->remaining = partial_pkt->total_len - + partial_pkt->read_len; + partial_pkt->processing = 1; + memcpy(partial_pkt->data, buf, partial_pkt->read_len); + mutex_unlock(&driver->hdlc_recovery_mutex); + break; + } + data_ptr = buf + header_len; + if (*(uint8_t *)(data_ptr + actual_pkt->length) != + CONTROL_CHAR) { + mutex_unlock(&driver->hdlc_recovery_mutex); + diag_hdlc_start_recovery(buf, len, pid); + mutex_lock(&driver->hdlc_recovery_mutex); + } + else + hdlc_reset = 0; + err = diag_process_apps_pkt(data_ptr, + actual_pkt->length, pid); + if (err) { + mutex_unlock(&driver->hdlc_recovery_mutex); + break; + } + read_bytes += header_len + pkt_len + 1; + buf += header_len + pkt_len + 1; /* advance to next pkt */ + mutex_unlock(&driver->hdlc_recovery_mutex); + } +end: + return; +} + +static int diagfwd_mux_read_done(unsigned char *buf, int len, int ctxt) +{ + if (!buf || len <= 0) + return -EINVAL; + + if (!driver->hdlc_disabled) + diag_process_hdlc_pkt(buf, len, 0); + else + diag_process_non_hdlc_pkt(buf, len, 0); + + diag_mux_queue_read(ctxt); + return 0; +} + +static int diagfwd_mux_write_done(unsigned char *buf, int len, int buf_ctxt, + int ctxt) +{ + unsigned long flags; + int peripheral = -1; + int type = -1; + int num = -1; + + if (!buf || len < 0) + return -EINVAL; + + peripheral = GET_BUF_PERIPHERAL(buf_ctxt); + type = GET_BUF_TYPE(buf_ctxt); + num = GET_BUF_NUM(buf_ctxt); + + switch (type) { + case TYPE_DATA: + if (peripheral >= 0 && peripheral < NUM_PERIPHERALS) { + DIAG_LOG(DIAG_DEBUG_PERIPHERALS, + "Marking buffer as free after write done p: %d, t: %d, buf_num: %d\n", + peripheral, type, num); + diagfwd_write_done(peripheral, type, num); + diag_ws_on_copy(DIAG_WS_MUX); + } else if (peripheral == APPS_DATA) { + diagmem_free(driver, (unsigned char *)buf, + POOL_TYPE_HDLC); + buf = NULL; + } else { + pr_err_ratelimited("diag: Invalid peripheral %d in %s, type: %d\n", + peripheral, __func__, type); + } + break; + case TYPE_CMD: + if (peripheral >= 0 && peripheral < NUM_PERIPHERALS && + num != TYPE_CMD) { + DIAG_LOG(DIAG_DEBUG_PERIPHERALS, + "Marking buffer as free after write done p: %d, t: %d, buf_num: %d\n", + peripheral, type, num); + diagfwd_write_done(peripheral, type, num); + } else if (peripheral == APPS_DATA || + (peripheral >= 0 && peripheral < NUM_PERIPHERALS && + num == TYPE_CMD)) { + DIAG_LOG(DIAG_DEBUG_PERIPHERALS, + "Marking APPS response buffer free after write done for p: %d, t: %d, buf_num: %d\n", + peripheral, type, num); + spin_lock_irqsave(&driver->rsp_buf_busy_lock, flags); + driver->rsp_buf_busy = 0; + driver->encoded_rsp_len = 0; + spin_unlock_irqrestore(&driver->rsp_buf_busy_lock, + flags); + } + break; + default: + pr_err_ratelimited("diag: Incorrect data type %d, buf_ctxt: %d in %s\n", + type, buf_ctxt, __func__); + break; + } + + return 0; +} + +static struct diag_mux_ops diagfwd_mux_ops = { + .open = diagfwd_mux_open, + .close = diagfwd_mux_close, + .read_done = diagfwd_mux_read_done, + .write_done = diagfwd_mux_write_done +}; + +int diagfwd_init(void) +{ + int ret; + int i; + + wrap_enabled = 0; + wrap_count = 0; + driver->use_device_tree = has_device_tree(); + for (i = 0; i < DIAG_NUM_PROC; i++) + driver->real_time_mode[i] = 1; + driver->supports_separate_cmdrsp = 1; + driver->supports_apps_hdlc_encoding = 1; + driver->supports_apps_header_untagging = 1; + driver->supports_pd_buffering = 1; + for (i = 0; i < NUM_PERIPHERALS; i++) + driver->peripheral_untag[i] = 0; + mutex_init(&driver->diag_hdlc_mutex); + mutex_init(&driver->diag_cntl_mutex); + mutex_init(&driver->mode_lock); + driver->encoded_rsp_buf = kzalloc(DIAG_MAX_HDLC_BUF_SIZE + + APF_DIAG_PADDING, GFP_KERNEL); + if (!driver->encoded_rsp_buf) + goto err; + kmemleak_not_leak(driver->encoded_rsp_buf); + hdlc_decode = kzalloc(sizeof(struct diag_hdlc_decode_type), + GFP_KERNEL); + if (!hdlc_decode) + goto err; + setup_timer(&driver->hdlc_reset_timer, hdlc_reset_timer_func, 0); + kmemleak_not_leak(hdlc_decode); + driver->encoded_rsp_len = 0; + driver->rsp_buf_busy = 0; + spin_lock_init(&driver->rsp_buf_busy_lock); + driver->user_space_data_busy = 0; + driver->hdlc_buf_len = 0; + INIT_LIST_HEAD(&driver->cmd_reg_list); + driver->cmd_reg_count = 0; + mutex_init(&driver->cmd_reg_mutex); + + for (i = 0; i < NUM_PERIPHERALS; i++) { + driver->feature[i].separate_cmd_rsp = 0; + driver->feature[i].stm_support = DISABLE_STM; + driver->feature[i].rcvd_feature_mask = 0; + driver->feature[i].peripheral_buffering = 0; + driver->feature[i].pd_buffering = 0; + driver->feature[i].encode_hdlc = 0; + driver->feature[i].untag_header = + DISABLE_PKT_HEADER_UNTAGGING; + driver->feature[i].mask_centralization = 0; + driver->feature[i].log_on_demand = 0; + driver->feature[i].sent_feature_mask = 0; + } + + for (i = 0; i < NUM_MD_SESSIONS; i++) { + driver->buffering_mode[i].peripheral = i; + driver->buffering_mode[i].mode = DIAG_BUFFERING_MODE_STREAMING; + driver->buffering_mode[i].high_wm_val = DEFAULT_HIGH_WM_VAL; + driver->buffering_mode[i].low_wm_val = DEFAULT_LOW_WM_VAL; + } + + for (i = 0; i < NUM_STM_PROCESSORS; i++) { + driver->stm_state_requested[i] = DISABLE_STM; + driver->stm_state[i] = DISABLE_STM; + } + + if (driver->hdlc_buf == NULL) { + driver->hdlc_buf = kzalloc(DIAG_MAX_HDLC_BUF_SIZE, GFP_KERNEL); + if (!driver->hdlc_buf) + goto err; + kmemleak_not_leak(driver->hdlc_buf); + } + if (driver->user_space_data_buf == NULL) + driver->user_space_data_buf = kzalloc(USER_SPACE_DATA, + GFP_KERNEL); + if (driver->user_space_data_buf == NULL) + goto err; + kmemleak_not_leak(driver->user_space_data_buf); + if (driver->client_map == NULL && + (driver->client_map = kzalloc + ((driver->num_clients) * sizeof(struct diag_client_map), + GFP_KERNEL)) == NULL) + goto err; + kmemleak_not_leak(driver->client_map); + if (driver->data_ready == NULL && + (driver->data_ready = kzalloc(driver->num_clients * sizeof(int) + , GFP_KERNEL)) == NULL) + goto err; + kmemleak_not_leak(driver->data_ready); + for (i = 0; i < THRESHOLD_CLIENT_LIMIT; i++) + atomic_set(&driver->data_ready_notif[i], 0); + if (driver->apps_req_buf == NULL) { + driver->apps_req_buf = kzalloc(DIAG_MAX_REQ_SIZE, GFP_KERNEL); + if (!driver->apps_req_buf) + goto err; + kmemleak_not_leak(driver->apps_req_buf); + } + if (driver->dci_pkt_buf == NULL) { + driver->dci_pkt_buf = kzalloc(DCI_BUF_SIZE, GFP_KERNEL); + if (!driver->dci_pkt_buf) + goto err; + kmemleak_not_leak(driver->dci_pkt_buf); + } + if (driver->apps_rsp_buf == NULL) { + driver->apps_rsp_buf = kzalloc(DIAG_MAX_RSP_SIZE, GFP_KERNEL); + if (driver->apps_rsp_buf == NULL) + goto err; + kmemleak_not_leak(driver->apps_rsp_buf); + } + driver->diag_wq = create_singlethread_workqueue("diag_wq"); + if (!driver->diag_wq) + goto err; + ret = diag_mux_register(DIAG_LOCAL_PROC, DIAG_LOCAL_PROC, + &diagfwd_mux_ops); + if (ret) { + pr_err("diag: Unable to register with USB, err: %d\n", ret); + goto err; + } + + return 0; +err: + pr_err("diag: In %s, couldn't initialize diag\n", __func__); + + diag_usb_exit(DIAG_USB_LOCAL); + kfree(driver->encoded_rsp_buf); + kfree(driver->hdlc_buf); + kfree(driver->client_map); + kfree(driver->data_ready); + kfree(driver->apps_req_buf); + kfree(driver->dci_pkt_buf); + kfree(driver->apps_rsp_buf); + kfree(hdlc_decode); + kfree(driver->user_space_data_buf); + if (driver->diag_wq) + destroy_workqueue(driver->diag_wq); + return -ENOMEM; +} + +void diagfwd_exit(void) +{ + kfree(driver->encoded_rsp_buf); + kfree(driver->hdlc_buf); + kfree(hdlc_decode); + kfree(driver->client_map); + kfree(driver->data_ready); + kfree(driver->apps_req_buf); + kfree(driver->dci_pkt_buf); + kfree(driver->apps_rsp_buf); + kfree(driver->user_space_data_buf); + destroy_workqueue(driver->diag_wq); +} diff -Nruw linux-4.4.115-fbx/drivers/char/diag./diagfwd_cntl.c linux-4.4.115-fbx/drivers/char/diag/diagfwd_cntl.c --- linux-4.4.115-fbx/drivers/char/diag./diagfwd_cntl.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-4.4.115-fbx/drivers/char/diag/diagfwd_cntl.c 2019-10-29 09:26:23.453201319 +0100 @@ -0,0 +1,1566 @@ +/* Copyright (c) 2011-2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include "diagchar.h" +#include "diagfwd.h" +#include "diagfwd_cntl.h" +#include "diagfwd_peripheral.h" +#include "diagfwd_bridge.h" +#include "diag_dci.h" +#include "diagmem.h" +#include "diag_masks.h" +#include "diag_ipc_logging.h" +#include "diag_mux.h" + +#define FEATURE_SUPPORTED(x) ((feature_mask << (i * 8)) & (1 << x)) + +/* tracks which peripheral is undergoing SSR */ +static uint16_t reg_dirty; +static void diag_notify_md_client(uint8_t peripheral, int data); + +static void diag_mask_update_work_fn(struct work_struct *work) +{ + uint8_t peripheral; + + for (peripheral = 0; peripheral <= NUM_PERIPHERALS; peripheral++) { + if (!(driver->mask_update & PERIPHERAL_MASK(peripheral))) + continue; + mutex_lock(&driver->cntl_lock); + driver->mask_update ^= PERIPHERAL_MASK(peripheral); + mutex_unlock(&driver->cntl_lock); + diag_send_updates_peripheral(peripheral); + } +} + +void diag_cntl_channel_open(struct diagfwd_info *p_info) +{ + if (!p_info) + return; + driver->mask_update |= PERIPHERAL_MASK(p_info->peripheral); + queue_work(driver->cntl_wq, &driver->mask_update_work); + diag_notify_md_client(p_info->peripheral, DIAG_STATUS_OPEN); +} + +void diag_cntl_channel_close(struct diagfwd_info *p_info) +{ + uint8_t peripheral; + + if (!p_info) + return; + + peripheral = p_info->peripheral; + if (peripheral >= NUM_PERIPHERALS) + return; + + driver->feature[peripheral].sent_feature_mask = 0; + driver->feature[peripheral].rcvd_feature_mask = 0; + reg_dirty |= PERIPHERAL_MASK(peripheral); + diag_cmd_remove_reg_by_proc(peripheral); + driver->feature[peripheral].stm_support = DISABLE_STM; + driver->feature[peripheral].log_on_demand = 0; + driver->stm_state[peripheral] = DISABLE_STM; + driver->stm_state_requested[peripheral] = DISABLE_STM; + reg_dirty ^= PERIPHERAL_MASK(peripheral); + diag_notify_md_client(peripheral, DIAG_STATUS_CLOSED); +} + +static void diag_stm_update_work_fn(struct work_struct *work) +{ + uint8_t i; + uint16_t peripheral_mask = 0; + int err = 0; + + mutex_lock(&driver->cntl_lock); + peripheral_mask = driver->stm_peripheral; + driver->stm_peripheral = 0; + mutex_unlock(&driver->cntl_lock); + + if (peripheral_mask == 0) + return; + + for (i = 0; i < NUM_PERIPHERALS; i++) { + if (!driver->feature[i].stm_support) + continue; + if (peripheral_mask & PERIPHERAL_MASK(i)) { + err = diag_send_stm_state(i, + (uint8_t)(driver->stm_state_requested[i])); + if (!err) { + driver->stm_state[i] = + driver->stm_state_requested[i]; + } + } + } +} + +void diag_notify_md_client(uint8_t peripheral, int data) +{ + int stat = 0; + struct siginfo info; + struct pid *pid_struct; + struct task_struct *result; + + if (peripheral > NUM_PERIPHERALS) + return; + + if (driver->logging_mode != DIAG_MEMORY_DEVICE_MODE) + return; + + mutex_lock(&driver->md_session_lock); + memset(&info, 0, sizeof(struct siginfo)); + info.si_code = SI_QUEUE; + info.si_int = (PERIPHERAL_MASK(peripheral) | data); + info.si_signo = SIGCONT; + + if (!driver->md_session_map[peripheral] || + driver->md_session_map[peripheral]->pid <= 0) { + pr_err("diag: md_session_map[%d] is invalid\n", peripheral); + mutex_unlock(&driver->md_session_lock); + return; + } + + pid_struct = find_get_pid( + driver->md_session_map[peripheral]->pid); + DIAG_LOG(DIAG_DEBUG_PERIPHERALS, + "md_session_map[%d] pid = %d task = %pK\n", + peripheral, + driver->md_session_map[peripheral]->pid, + driver->md_session_map[peripheral]->task); + + if (pid_struct) { + result = get_pid_task(pid_struct, PIDTYPE_PID); + + if (!result) { + DIAG_LOG(DIAG_DEBUG_PERIPHERALS, + "diag: md_session_map[%d] with pid = %d Exited..\n", + peripheral, + driver->md_session_map[peripheral]->pid); + mutex_unlock(&driver->md_session_lock); + return; + } + + if (driver->md_session_map[peripheral] && + driver->md_session_map[peripheral]->task == result) { + stat = send_sig_info(info.si_signo, + &info, result); + if (stat) + pr_err("diag: Err sending signal to memory device client, signal data: 0x%x, stat: %d\n", + info.si_int, stat); + } else + pr_err("diag: md_session_map[%d] data is corrupted, signal data: 0x%x, stat: %d\n", + peripheral, info.si_int, stat); + } + mutex_unlock(&driver->md_session_lock); +} + +static void process_pd_status(uint8_t *buf, uint32_t len, + uint8_t peripheral) +{ + struct diag_ctrl_msg_pd_status *pd_msg = NULL; + uint32_t pd; + int status = DIAG_STATUS_CLOSED; + + if (!buf || peripheral >= NUM_PERIPHERALS || len < sizeof(*pd_msg)) + return; + + pd_msg = (struct diag_ctrl_msg_pd_status *)buf; + pd = pd_msg->pd_id; + status = (pd_msg->status == 0) ? DIAG_STATUS_OPEN : DIAG_STATUS_CLOSED; + diag_notify_md_client(peripheral, status); +} + +static void enable_stm_feature(uint8_t peripheral) +{ + if (peripheral >= NUM_PERIPHERALS) + return; + + mutex_lock(&driver->cntl_lock); + driver->feature[peripheral].stm_support = ENABLE_STM; + driver->stm_peripheral |= PERIPHERAL_MASK(peripheral); + mutex_unlock(&driver->cntl_lock); + + queue_work(driver->cntl_wq, &(driver->stm_update_work)); +} + +static void enable_socket_feature(uint8_t peripheral) +{ + if (peripheral >= NUM_PERIPHERALS) + return; + + if (driver->supports_sockets) + driver->feature[peripheral].sockets_enabled = 1; + else + driver->feature[peripheral].sockets_enabled = 0; +} + +static void process_hdlc_encoding_feature(uint8_t peripheral) +{ + if (peripheral >= NUM_PERIPHERALS) + return; + + if (driver->supports_apps_hdlc_encoding) { + driver->feature[peripheral].encode_hdlc = + ENABLE_APPS_HDLC_ENCODING; + } else { + driver->feature[peripheral].encode_hdlc = + DISABLE_APPS_HDLC_ENCODING; + } +} + +static void process_upd_header_untagging_feature(uint8_t peripheral) +{ + if (peripheral >= NUM_PERIPHERALS) + return; + + if (driver->supports_apps_header_untagging) { + driver->feature[peripheral].untag_header = + ENABLE_PKT_HEADER_UNTAGGING; + } else { + driver->feature[peripheral].untag_header = + DISABLE_PKT_HEADER_UNTAGGING; + } +} + +static void process_command_deregistration(uint8_t *buf, uint32_t len, + uint8_t peripheral) +{ + uint8_t *ptr = buf; + int i; + int header_len = sizeof(struct diag_ctrl_cmd_dereg); + int read_len = 0; + struct diag_ctrl_cmd_dereg *dereg = NULL; + struct cmd_code_range *range = NULL; + struct diag_cmd_reg_entry_t del_entry; + + /* + * Perform Basic sanity. The len field is the size of the data payload. + * This doesn't include the header size. + */ + if (!buf || peripheral >= NUM_PERIPHERALS || len == 0) + return; + + dereg = (struct diag_ctrl_cmd_dereg *)ptr; + ptr += header_len; + /* Don't account for pkt_id and length */ + read_len += header_len - (2 * sizeof(uint32_t)); + + if (dereg->count_entries == 0) { + pr_debug("diag: In %s, received reg tbl with no entries\n", + __func__); + return; + } + + for (i = 0; i < dereg->count_entries && read_len < len; i++) { + range = (struct cmd_code_range *)ptr; + ptr += sizeof(struct cmd_code_range) - sizeof(uint32_t); + read_len += sizeof(struct cmd_code_range) - sizeof(uint32_t); + del_entry.cmd_code = dereg->cmd_code; + del_entry.subsys_id = dereg->subsysid; + del_entry.cmd_code_hi = range->cmd_code_hi; + del_entry.cmd_code_lo = range->cmd_code_lo; + diag_cmd_remove_reg(&del_entry, peripheral); + } + + if (i != dereg->count_entries) { + pr_err("diag: In %s, reading less than available, read_len: %d, len: %d count: %d\n", + __func__, read_len, len, dereg->count_entries); + } +} +static void process_command_registration(uint8_t *buf, uint32_t len, + uint8_t peripheral) +{ + uint8_t *ptr = buf; + int i; + int header_len = sizeof(struct diag_ctrl_cmd_reg); + int read_len = 0; + struct diag_ctrl_cmd_reg *reg = NULL; + struct cmd_code_range *range = NULL; + struct diag_cmd_reg_entry_t new_entry; + + /* + * Perform Basic sanity. The len field is the size of the data payload. + * This doesn't include the header size. + */ + if (!buf || peripheral >= NUM_PERIPHERALS || len == 0) + return; + + reg = (struct diag_ctrl_cmd_reg *)ptr; + ptr += header_len; + /* Don't account for pkt_id and length */ + read_len += header_len - (2 * sizeof(uint32_t)); + + if (reg->count_entries == 0) { + pr_debug("diag: In %s, received reg tbl with no entries\n", + __func__); + return; + } + + for (i = 0; i < reg->count_entries && read_len < len; i++) { + range = (struct cmd_code_range *)ptr; + ptr += sizeof(struct cmd_code_range); + read_len += sizeof(struct cmd_code_range); + new_entry.cmd_code = reg->cmd_code; + new_entry.subsys_id = reg->subsysid; + new_entry.cmd_code_hi = range->cmd_code_hi; + new_entry.cmd_code_lo = range->cmd_code_lo; + diag_cmd_add_reg(&new_entry, peripheral, INVALID_PID); + } + + if (i != reg->count_entries) { + pr_err("diag: In %s, reading less than available, read_len: %d, len: %d count: %d\n", + __func__, read_len, len, reg->count_entries); + } +} + +static void diag_close_transport_work_fn(struct work_struct *work) +{ + uint8_t transport; + uint8_t peripheral; + + mutex_lock(&driver->cntl_lock); + for (peripheral = 0; peripheral <= NUM_PERIPHERALS; peripheral++) { + if (!(driver->close_transport & PERIPHERAL_MASK(peripheral))) + continue; + driver->close_transport ^= PERIPHERAL_MASK(peripheral); + transport = driver->feature[peripheral].sockets_enabled ? + TRANSPORT_SMD : TRANSPORT_SOCKET; + diagfwd_close_transport(transport, peripheral); + } + mutex_unlock(&driver->cntl_lock); +} + +static void process_socket_feature(uint8_t peripheral) +{ + if (peripheral >= NUM_PERIPHERALS) + return; + + mutex_lock(&driver->cntl_lock); + driver->close_transport |= PERIPHERAL_MASK(peripheral); + queue_work(driver->cntl_wq, &driver->close_transport_work); + mutex_unlock(&driver->cntl_lock); +} + +static void process_log_on_demand_feature(uint8_t peripheral) +{ + /* Log On Demand command is registered only on Modem */ + if (peripheral != PERIPHERAL_MODEM) + return; + + if (driver->feature[PERIPHERAL_MODEM].log_on_demand) + driver->log_on_demand_support = 1; + else + driver->log_on_demand_support = 0; +} + +static void process_incoming_feature_mask(uint8_t *buf, uint32_t len, + uint8_t peripheral) +{ + int i; + int header_len = sizeof(struct diag_ctrl_feature_mask); + int read_len = 0; + struct diag_ctrl_feature_mask *header = NULL; + uint32_t feature_mask_len = 0; + uint32_t feature_mask = 0; + uint8_t *ptr = buf; + + if (!buf || peripheral >= NUM_PERIPHERALS || len == 0) + return; + + header = (struct diag_ctrl_feature_mask *)ptr; + ptr += header_len; + feature_mask_len = header->feature_mask_len; + + if (feature_mask_len == 0) { + pr_debug("diag: In %s, received invalid feature mask from peripheral %d\n", + __func__, peripheral); + return; + } + + if (feature_mask_len > FEATURE_MASK_LEN) { + pr_alert("diag: Receiving feature mask length more than Apps support\n"); + feature_mask_len = FEATURE_MASK_LEN; + } + + diag_cmd_remove_reg_by_proc(peripheral); + + driver->feature[peripheral].rcvd_feature_mask = 1; + + for (i = 0; i < feature_mask_len && read_len < len; i++) { + feature_mask = *(uint8_t *)ptr; + driver->feature[peripheral].feature_mask[i] = feature_mask; + ptr += sizeof(uint8_t); + read_len += sizeof(uint8_t); + + if (FEATURE_SUPPORTED(F_DIAG_LOG_ON_DEMAND_APPS)) + driver->feature[peripheral].log_on_demand = 1; + if (FEATURE_SUPPORTED(F_DIAG_REQ_RSP_SUPPORT)) + driver->feature[peripheral].separate_cmd_rsp = 1; + if (FEATURE_SUPPORTED(F_DIAG_APPS_HDLC_ENCODE)) + process_hdlc_encoding_feature(peripheral); + if (FEATURE_SUPPORTED(F_DIAG_PKT_HEADER_UNTAG)) + process_upd_header_untagging_feature(peripheral); + if (FEATURE_SUPPORTED(F_DIAG_STM)) + enable_stm_feature(peripheral); + if (FEATURE_SUPPORTED(F_DIAG_MASK_CENTRALIZATION)) + driver->feature[peripheral].mask_centralization = 1; + if (FEATURE_SUPPORTED(F_DIAG_PERIPHERAL_BUFFERING)) + driver->feature[peripheral].peripheral_buffering = 1; + if (FEATURE_SUPPORTED(F_DIAG_PD_BUFFERING)) + driver->feature[peripheral].pd_buffering = 1; + if (FEATURE_SUPPORTED(F_DIAG_SOCKETS_ENABLED)) + enable_socket_feature(peripheral); + } + + process_socket_feature(peripheral); + process_log_on_demand_feature(peripheral); +} + +static void process_last_event_report(uint8_t *buf, uint32_t len, + uint8_t peripheral) +{ + struct diag_ctrl_last_event_report *header = NULL; + uint8_t *ptr = buf; + uint8_t *temp = NULL; + uint32_t pkt_len = sizeof(uint32_t) + sizeof(uint16_t); + uint16_t event_size = 0; + + if (!buf || peripheral >= NUM_PERIPHERALS || len != pkt_len) + return; + + mutex_lock(&event_mask.lock); + header = (struct diag_ctrl_last_event_report *)ptr; + event_size = ((header->event_last_id / 8) + 1); + if (event_size >= driver->event_mask_size) { + DIAG_LOG(DIAG_DEBUG_MASKS, + "diag: receiving event mask size more that Apps can handle\n"); + temp = krealloc(driver->event_mask->ptr, event_size, + GFP_KERNEL); + if (!temp) { + pr_err("diag: In %s, unable to reallocate event mask to support events from %d\n", + __func__, peripheral); + goto err; + } + driver->event_mask->ptr = temp; + driver->event_mask_size = event_size; + } + + driver->num_event_id[peripheral] = header->event_last_id; + if (header->event_last_id > driver->last_event_id) + driver->last_event_id = header->event_last_id; +err: + mutex_unlock(&event_mask.lock); +} + +static void process_log_range_report(uint8_t *buf, uint32_t len, + uint8_t peripheral) +{ + int i; + int read_len = 0; + int header_len = sizeof(struct diag_ctrl_log_range_report); + uint8_t *ptr = buf; + struct diag_ctrl_log_range_report *header = NULL; + struct diag_ctrl_log_range *log_range = NULL; + struct diag_log_mask_t *mask_ptr = NULL; + + if (!buf || peripheral >= NUM_PERIPHERALS || len < 0) + return; + + header = (struct diag_ctrl_log_range_report *)ptr; + ptr += header_len; + /* Don't account for pkt_id and length */ + read_len += header_len - (2 * sizeof(uint32_t)); + + driver->num_equip_id[peripheral] = header->num_ranges; + for (i = 0; i < header->num_ranges && read_len < len; i++) { + log_range = (struct diag_ctrl_log_range *)ptr; + ptr += sizeof(struct diag_ctrl_log_range); + read_len += sizeof(struct diag_ctrl_log_range); + + if (log_range->equip_id >= MAX_EQUIP_ID) { + pr_err("diag: receiving log equip id %d more than supported equip id: %d from peripheral: %d\n", + log_range->equip_id, MAX_EQUIP_ID, peripheral); + continue; + } + mask_ptr = (struct diag_log_mask_t *)log_mask.ptr; + mask_ptr = &mask_ptr[log_range->equip_id]; + + mutex_lock(&(mask_ptr->lock)); + mask_ptr->num_items = log_range->num_items; + mask_ptr->range = LOG_ITEMS_TO_SIZE(log_range->num_items); + mutex_unlock(&(mask_ptr->lock)); + } +} + +static int update_msg_mask_tbl_entry(struct diag_msg_mask_t *mask, + struct diag_ssid_range_t *range) +{ + uint32_t temp_range; + + if (!mask || !range) + return -EIO; + if (range->ssid_last < range->ssid_first) { + pr_err("diag: In %s, invalid ssid range, first: %d, last: %d\n", + __func__, range->ssid_first, range->ssid_last); + return -EINVAL; + } + if (range->ssid_last >= mask->ssid_last) { + temp_range = range->ssid_last - mask->ssid_first + 1; + if (temp_range > MAX_SSID_PER_RANGE) { + temp_range = MAX_SSID_PER_RANGE; + mask->ssid_last = mask->ssid_first + temp_range - 1; + } else + mask->ssid_last = range->ssid_last; + mask->ssid_last_tools = mask->ssid_last; + mask->range = temp_range; + } + + return 0; +} + +static void process_ssid_range_report(uint8_t *buf, uint32_t len, + uint8_t peripheral) +{ + int i; + int j; + int read_len = 0; + int found = 0; + int new_size = 0; + int err = 0; + struct diag_ctrl_ssid_range_report *header = NULL; + struct diag_ssid_range_t *ssid_range = NULL; + int header_len = sizeof(struct diag_ctrl_ssid_range_report); + struct diag_msg_mask_t *mask_ptr = NULL; + uint8_t *ptr = buf; + uint8_t *temp = NULL; + uint32_t min_len = header_len - sizeof(struct diag_ctrl_pkt_header_t); + + if (!buf || peripheral >= NUM_PERIPHERALS || len < min_len) + return; + + header = (struct diag_ctrl_ssid_range_report *)ptr; + ptr += header_len; + /* Don't account for pkt_id and length */ + read_len += header_len - (2 * sizeof(uint32_t)); + + mutex_lock(&driver->msg_mask_lock); + driver->max_ssid_count[peripheral] = header->count; + for (i = 0; i < header->count && read_len < len; i++) { + ssid_range = (struct diag_ssid_range_t *)ptr; + ptr += sizeof(struct diag_ssid_range_t); + read_len += sizeof(struct diag_ssid_range_t); + mask_ptr = (struct diag_msg_mask_t *)msg_mask.ptr; + found = 0; + for (j = 0; j < driver->msg_mask_tbl_count; j++, mask_ptr++) { + if (!mask_ptr->ptr || !ssid_range) { + found = 1; + break; + } + if (mask_ptr->ssid_first != ssid_range->ssid_first) + continue; + mutex_lock(&mask_ptr->lock); + err = update_msg_mask_tbl_entry(mask_ptr, ssid_range); + mutex_unlock(&mask_ptr->lock); + if (err == -ENOMEM) { + pr_err("diag: In %s, unable to increase the msg mask table range\n", + __func__); + } + found = 1; + break; + } + + if (found) + continue; + + new_size = (driver->msg_mask_tbl_count + 1) * + sizeof(struct diag_msg_mask_t); + DIAG_LOG(DIAG_DEBUG_MASKS, + "diag: receiving msg mask size more that Apps can handle\n"); + temp = krealloc(msg_mask.ptr, new_size, GFP_KERNEL); + if (!temp) { + pr_err("diag: In %s, Unable to add new ssid table to msg mask, ssid first: %d, last: %d\n", + __func__, ssid_range->ssid_first, + ssid_range->ssid_last); + continue; + } + msg_mask.ptr = temp; + mask_ptr = (struct diag_msg_mask_t *)msg_mask.ptr; + err = diag_create_msg_mask_table_entry(mask_ptr, ssid_range); + if (err) { + pr_err("diag: In %s, Unable to create a new msg mask table entry, first: %d last: %d err: %d\n", + __func__, ssid_range->ssid_first, + ssid_range->ssid_last, err); + continue; + } + driver->msg_mask_tbl_count += 1; + } + mutex_unlock(&driver->msg_mask_lock); +} + +static void diag_build_time_mask_update(uint8_t *buf, + struct diag_ssid_range_t *range) +{ + int i; + int j; + int num_items = 0; + int err = 0; + int found = 0; + int new_size = 0; + uint8_t *temp = NULL; + uint32_t *mask_ptr = (uint32_t *)buf; + uint32_t *dest_ptr = NULL; + struct diag_msg_mask_t *build_mask = NULL; + + if (!range || !buf) + return; + + if (range->ssid_last < range->ssid_first) { + pr_err("diag: In %s, invalid ssid range, first: %d, last: %d\n", + __func__, range->ssid_first, range->ssid_last); + return; + } + mutex_lock(&driver->msg_mask_lock); + build_mask = (struct diag_msg_mask_t *)(driver->build_time_mask->ptr); + num_items = range->ssid_last - range->ssid_first + 1; + + for (i = 0; i < driver->bt_msg_mask_tbl_count; i++, build_mask++) { + if (!build_mask->ptr) { + found = 1; + break; + } + if (build_mask->ssid_first != range->ssid_first) + continue; + found = 1; + mutex_lock(&build_mask->lock); + err = update_msg_mask_tbl_entry(build_mask, range); + if (err == -ENOMEM) { + pr_err("diag: In %s, unable to increase the msg build mask table range\n", + __func__); + } + dest_ptr = build_mask->ptr; + for (j = 0; (j < build_mask->range) && mask_ptr && dest_ptr; + j++, mask_ptr++, dest_ptr++) + *(uint32_t *)dest_ptr |= *mask_ptr; + mutex_unlock(&build_mask->lock); + break; + } + + if (found) + goto end; + + new_size = (driver->bt_msg_mask_tbl_count + 1) * + sizeof(struct diag_msg_mask_t); + DIAG_LOG(DIAG_DEBUG_MASKS, + "diag: receiving build time mask size more that Apps can handle\n"); + + temp = krealloc(driver->build_time_mask->ptr, new_size, GFP_KERNEL); + if (!temp) { + pr_err("diag: In %s, unable to create a new entry for build time mask\n", + __func__); + goto end; + } + driver->build_time_mask->ptr = temp; + build_mask = (struct diag_msg_mask_t *)driver->build_time_mask->ptr; + err = diag_create_msg_mask_table_entry(build_mask, range); + if (err) { + pr_err("diag: In %s, Unable to create a new msg mask table entry, err: %d\n", + __func__, err); + goto end; + } + driver->bt_msg_mask_tbl_count += 1; +end: + mutex_unlock(&driver->msg_mask_lock); + return; +} + +static void process_build_mask_report(uint8_t *buf, uint32_t len, + uint8_t peripheral) +{ + int i; + int read_len = 0; + int num_items = 0; + int header_len = sizeof(struct diag_ctrl_build_mask_report); + uint8_t *ptr = buf; + struct diag_ctrl_build_mask_report *header = NULL; + struct diag_ssid_range_t *range = NULL; + + if (!buf || peripheral >= NUM_PERIPHERALS || len < header_len) + return; + + header = (struct diag_ctrl_build_mask_report *)ptr; + ptr += header_len; + /* Don't account for pkt_id and length */ + read_len += header_len - (2 * sizeof(uint32_t)); + + for (i = 0; i < header->count && read_len < len; i++) { + range = (struct diag_ssid_range_t *)ptr; + ptr += sizeof(struct diag_ssid_range_t); + read_len += sizeof(struct diag_ssid_range_t); + num_items = range->ssid_last - range->ssid_first + 1; + diag_build_time_mask_update(ptr, range); + ptr += num_items * sizeof(uint32_t); + read_len += num_items * sizeof(uint32_t); + } +} + +void diag_cntl_process_read_data(struct diagfwd_info *p_info, void *buf, + int len) +{ + uint32_t read_len = 0; + uint32_t header_len = sizeof(struct diag_ctrl_pkt_header_t); + uint8_t *ptr = buf; + struct diag_ctrl_pkt_header_t *ctrl_pkt = NULL; + + if (!buf || len <= 0 || !p_info) + return; + + if (reg_dirty & PERIPHERAL_MASK(p_info->peripheral)) { + pr_err_ratelimited("diag: dropping command registration from peripheral %d\n", + p_info->peripheral); + return; + } + + while (read_len + header_len < len) { + ctrl_pkt = (struct diag_ctrl_pkt_header_t *)ptr; + switch (ctrl_pkt->pkt_id) { + case DIAG_CTRL_MSG_REG: + process_command_registration(ptr, ctrl_pkt->len, + p_info->peripheral); + break; + case DIAG_CTRL_MSG_DEREG: + process_command_deregistration(ptr, ctrl_pkt->len, + p_info->peripheral); + break; + case DIAG_CTRL_MSG_FEATURE: + process_incoming_feature_mask(ptr, ctrl_pkt->len, + p_info->peripheral); + break; + case DIAG_CTRL_MSG_LAST_EVENT_REPORT: + process_last_event_report(ptr, ctrl_pkt->len, + p_info->peripheral); + break; + case DIAG_CTRL_MSG_LOG_RANGE_REPORT: + process_log_range_report(ptr, ctrl_pkt->len, + p_info->peripheral); + break; + case DIAG_CTRL_MSG_SSID_RANGE_REPORT: + process_ssid_range_report(ptr, ctrl_pkt->len, + p_info->peripheral); + break; + case DIAG_CTRL_MSG_BUILD_MASK_REPORT: + process_build_mask_report(ptr, ctrl_pkt->len, + p_info->peripheral); + break; + case DIAG_CTRL_MSG_PD_STATUS: + process_pd_status(ptr, ctrl_pkt->len, + p_info->peripheral); + break; + default: + pr_debug("diag: Control packet %d not supported\n", + ctrl_pkt->pkt_id); + } + ptr += header_len + ctrl_pkt->len; + read_len += header_len + ctrl_pkt->len; + } + + return; +} + +#ifdef CONFIG_DIAG_OVER_USB +static int diag_compute_real_time(int idx) +{ + int real_time = MODE_REALTIME; + if (driver->proc_active_mask == 0) { + /* + * There are no DCI or Memory Device processes. Diag should + * be in Real Time mode irrespective of USB connection + */ + real_time = MODE_REALTIME; + } else if (driver->proc_rt_vote_mask[idx] & driver->proc_active_mask) { + /* + * Atleast one process is alive and is voting for Real Time + * data - Diag should be in real time mode irrespective of USB + * connection. + */ + real_time = MODE_REALTIME; + } else if (driver->usb_connected) { + /* + * If USB is connected, check individual process. If Memory + * Device Mode is active, set the mode requested by Memory + * Device process. Set to realtime mode otherwise. + */ + if ((driver->proc_rt_vote_mask[idx] & + DIAG_PROC_MEMORY_DEVICE) == 0) + real_time = MODE_NONREALTIME; + else + real_time = MODE_REALTIME; + } else { + /* + * We come here if USB is not connected and the active + * processes are voting for Non realtime mode. + */ + real_time = MODE_NONREALTIME; + } + return real_time; +} +#endif + +static void diag_create_diag_mode_ctrl_pkt(unsigned char *dest_buf, + uint8_t diag_id, int real_time) +{ + struct diag_ctrl_msg_diagmode diagmode; + struct diag_ctrl_msg_diagmode_v2 diagmode_v2; + int msg_size = sizeof(struct diag_ctrl_msg_diagmode); + int msg_size_2 = sizeof(struct diag_ctrl_msg_diagmode_v2); + + if (!dest_buf) + return; + + if (diag_id) { + diagmode_v2.ctrl_pkt_id = DIAG_CTRL_MSG_DIAGMODE; + diagmode_v2.ctrl_pkt_data_len = DIAG_MODE_PKT_LEN_V2; + diagmode_v2.version = 2; + diagmode_v2.sleep_vote = real_time ? 1 : 0; + /* + * 0 - Disables real-time logging (to prevent + * frequent APPS wake-ups, etc.). + * 1 - Enable real-time logging + */ + diagmode_v2.real_time = real_time; + diagmode_v2.use_nrt_values = 0; + diagmode_v2.commit_threshold = 0; + diagmode_v2.sleep_threshold = 0; + diagmode_v2.sleep_time = 0; + diagmode_v2.drain_timer_val = 0; + diagmode_v2.event_stale_timer_val = 0; + diagmode_v2.diag_id = diag_id; + memcpy(dest_buf, &diagmode_v2, msg_size_2); + } else { + diagmode.ctrl_pkt_id = DIAG_CTRL_MSG_DIAGMODE; + diagmode.ctrl_pkt_data_len = DIAG_MODE_PKT_LEN; + diagmode.version = 1; + diagmode.sleep_vote = real_time ? 1 : 0; + /* + * 0 - Disables real-time logging (to prevent + * frequent APPS wake-ups, etc.). + * 1 - Enable real-time logging + */ + diagmode.real_time = real_time; + diagmode.use_nrt_values = 0; + diagmode.commit_threshold = 0; + diagmode.sleep_threshold = 0; + diagmode.sleep_time = 0; + diagmode.drain_timer_val = 0; + diagmode.event_stale_timer_val = 0; + memcpy(dest_buf, &diagmode, msg_size); + } +} + +void diag_update_proc_vote(uint16_t proc, uint8_t vote, int index) +{ + int i; + + mutex_lock(&driver->real_time_mutex); + if (vote) + driver->proc_active_mask |= proc; + else { + driver->proc_active_mask &= ~proc; + if (index == ALL_PROC) { + for (i = 0; i < DIAG_NUM_PROC; i++) + driver->proc_rt_vote_mask[i] |= proc; + } else { + driver->proc_rt_vote_mask[index] |= proc; + } + } + mutex_unlock(&driver->real_time_mutex); +} + +void diag_update_real_time_vote(uint16_t proc, uint8_t real_time, int index) +{ + int i; + + if (index >= DIAG_NUM_PROC) { + pr_err("diag: In %s, invalid index %d\n", __func__, index); + return; + } + + mutex_lock(&driver->real_time_mutex); + if (index == ALL_PROC) { + for (i = 0; i < DIAG_NUM_PROC; i++) { + if (real_time) + driver->proc_rt_vote_mask[i] |= proc; + else + driver->proc_rt_vote_mask[i] &= ~proc; + } + } else { + if (real_time) + driver->proc_rt_vote_mask[index] |= proc; + else + driver->proc_rt_vote_mask[index] &= ~proc; + } + mutex_unlock(&driver->real_time_mutex); +} + + +#ifdef CONFIG_DIAGFWD_BRIDGE_CODE +static void diag_send_diag_mode_update_remote(int token, int real_time) +{ + unsigned char *buf = NULL; + int err = 0; + struct diag_dci_header_t dci_header; + int dci_header_size = sizeof(struct diag_dci_header_t); + int msg_size = sizeof(struct diag_ctrl_msg_diagmode); + uint32_t write_len = 0; + + if (token < 0 || token >= NUM_DCI_PROC) { + pr_err("diag: Invalid remote device channel in %s, token: %d\n", + __func__, token); + return; + } + + if (real_time != MODE_REALTIME && real_time != MODE_NONREALTIME) { + pr_err("diag: Invalid real time value in %s, type: %d\n", + __func__, real_time); + return; + } + + buf = dci_get_buffer_from_bridge(token); + if (!buf) { + pr_err("diag: In %s, unable to get dci buffers to write data\n", + __func__); + return; + } + /* Frame the DCI header */ + dci_header.start = CONTROL_CHAR; + dci_header.version = 1; + dci_header.length = msg_size + 1; + dci_header.cmd_code = DCI_CONTROL_PKT_CODE; + + memcpy(buf + write_len, &dci_header, dci_header_size); + write_len += dci_header_size; + diag_create_diag_mode_ctrl_pkt(buf + write_len, 0, real_time); + write_len += msg_size; + *(buf + write_len) = CONTROL_CHAR; /* End Terminator */ + write_len += sizeof(uint8_t); + err = diagfwd_bridge_write(TOKEN_TO_BRIDGE(token), buf, write_len); + if (err != write_len) { + pr_err("diag: cannot send nrt mode ctrl pkt, err: %d\n", err); + diagmem_free(driver, buf, dci_ops_tbl[token].mempool); + } else { + driver->real_time_mode[token + 1] = real_time; + } +} +#else +static inline void diag_send_diag_mode_update_remote(int token, int real_time) +{ +} +#endif + +#ifdef CONFIG_DIAG_OVER_USB +void diag_real_time_work_fn(struct work_struct *work) +{ + int temp_real_time = MODE_REALTIME, i, j; + uint8_t send_update = 1; + + /* + * If any peripheral in the local processor is in either threshold or + * circular buffering mode, don't send the real time mode control + * packet. + */ + for (i = 0; i < NUM_PERIPHERALS; i++) { + if (!driver->feature[i].peripheral_buffering) + continue; + switch (driver->buffering_mode[i].mode) { + case DIAG_BUFFERING_MODE_THRESHOLD: + case DIAG_BUFFERING_MODE_CIRCULAR: + send_update = 0; + break; + } + } + + mutex_lock(&driver->mode_lock); + for (i = 0; i < DIAG_NUM_PROC; i++) { + temp_real_time = diag_compute_real_time(i); + if (temp_real_time == driver->real_time_mode[i]) { + pr_debug("diag: did not update real time mode on proc %d, already in the req mode %d", + i, temp_real_time); + continue; + } + + if (i == DIAG_LOCAL_PROC) { + if (!send_update) { + pr_debug("diag: In %s, cannot send real time mode pkt since one of the periperhal is in buffering mode\n", + __func__); + break; + } + for (j = 0; j < NUM_PERIPHERALS; j++) + diag_send_real_time_update(j, + temp_real_time); + } else { + diag_send_diag_mode_update_remote(i - 1, + temp_real_time); + } + } + mutex_unlock(&driver->mode_lock); + + if (driver->real_time_update_busy > 0) + driver->real_time_update_busy--; +} +#else +void diag_real_time_work_fn(struct work_struct *work) +{ + int temp_real_time = MODE_REALTIME, i, j; + + for (i = 0; i < DIAG_NUM_PROC; i++) { + if (driver->proc_active_mask == 0) { + /* + * There are no DCI or Memory Device processes. + * Diag should be in Real Time mode. + */ + temp_real_time = MODE_REALTIME; + } else if (!(driver->proc_rt_vote_mask[i] & + driver->proc_active_mask)) { + /* No active process is voting for real time mode */ + temp_real_time = MODE_NONREALTIME; + } + if (temp_real_time == driver->real_time_mode[i]) { + pr_debug("diag: did not update real time mode on proc %d, already in the req mode %d", + i, temp_real_time); + continue; + } + + if (i == DIAG_LOCAL_PROC) { + for (j = 0; j < NUM_PERIPHERALS; j++) + diag_send_real_time_update( + j, temp_real_time); + } else { + diag_send_diag_mode_update_remote(i - 1, + temp_real_time); + } + } + + if (driver->real_time_update_busy > 0) + driver->real_time_update_busy--; +} +#endif + +static int __diag_send_real_time_update(uint8_t peripheral, int real_time, + uint8_t diag_id) +{ + char buf[sizeof(struct diag_ctrl_msg_diagmode_v2)]; + int msg_size = 0; + int err = 0; + + if (peripheral >= NUM_PERIPHERALS) { + pr_err("diag: In %s, invalid peripheral %d\n", __func__, + peripheral); + return -EINVAL; + } + + if (!driver->diagfwd_cntl[peripheral] || + !driver->diagfwd_cntl[peripheral]->ch_open) { + pr_debug("diag: In %s, control channel is not open, p: %d\n", + __func__, peripheral); + return err; + } + + if (real_time != MODE_NONREALTIME && real_time != MODE_REALTIME) { + pr_err("diag: In %s, invalid real time mode %d, peripheral: %d\n", + __func__, real_time, peripheral); + return -EINVAL; + } + + msg_size = (diag_id ? sizeof(struct diag_ctrl_msg_diagmode_v2) : + sizeof(struct diag_ctrl_msg_diagmode)); + + diag_create_diag_mode_ctrl_pkt(buf, diag_id, real_time); + + mutex_lock(&driver->diag_cntl_mutex); + + err = diagfwd_write(peripheral, TYPE_CNTL, buf, msg_size); + + if (err && err != -ENODEV) { + pr_err("diag: In %s, unable to write, peripheral: %d, type: %d, len: %d, err: %d\n", + __func__, peripheral, TYPE_CNTL, + msg_size, err); + } else { + driver->real_time_mode[DIAG_LOCAL_PROC] = real_time; + } + + mutex_unlock(&driver->diag_cntl_mutex); + + return err; +} + +int diag_send_real_time_update(uint8_t peripheral, int real_time) +{ + int i; + + for (i = 0; i < NUM_PERIPHERALS; i++) { + if (!driver->buffering_flag[i]) + continue; + /* + * One of the peripherals is in buffering mode. Don't set + * the RT value. + */ + return -EINVAL; + } + + return __diag_send_real_time_update(peripheral, real_time, 0); +} + +void diag_map_pd_to_diagid(uint8_t pd, uint8_t *diag_id, int *peripheral) +{ + switch (pd) { + case UPD_WLAN: + *diag_id = DIAG_ID_WLAN; + *peripheral = PERIPHERAL_MODEM; + break; + case UPD_AUDIO: + *diag_id = DIAG_ID_AUDIO; + *peripheral = PERIPHERAL_LPASS; + break; + case UPD_SENSORS: + *diag_id = DIAG_ID_SENSORS; + *peripheral = PERIPHERAL_LPASS; + break; + case PERIPHERAL_MODEM: + *diag_id = DIAG_ID_MPSS; + *peripheral = PERIPHERAL_MODEM; + break; + case PERIPHERAL_LPASS: + *diag_id = DIAG_ID_LPASS; + *peripheral = PERIPHERAL_LPASS; + break; + case PERIPHERAL_WCNSS: + *diag_id = 0; + *peripheral = PERIPHERAL_WCNSS; + break; + case PERIPHERAL_SENSORS: + *diag_id = 0; + *peripheral = PERIPHERAL_SENSORS; + break; + case PERIPHERAL_WDSP: + *diag_id = 0; + *peripheral = PERIPHERAL_WDSP; + break; + case PERIPHERAL_CDSP: + *diag_id = DIAG_ID_CDSP; + *peripheral = PERIPHERAL_CDSP; + break; + default: + pr_err("diag: In %s, invalid peripheral %d\n", __func__, + pd); + *peripheral = -EINVAL; + break; + } + + if (*peripheral > 0) + if (!driver->feature[*peripheral].pd_buffering) + *diag_id = 0; +} + +int diag_send_peripheral_buffering_mode(struct diag_buffering_mode_t *params) +{ + int err = 0; + int mode = MODE_REALTIME; + int peripheral = 0; + uint8_t diag_id = 0; + + if (!params) + return -EIO; + + diag_map_pd_to_diagid(params->peripheral, + &diag_id, &peripheral); + + if ((peripheral < 0) || + peripheral >= NUM_PERIPHERALS) { + pr_err("diag: In %s, invalid peripheral %d\n", __func__, + peripheral); + return -EINVAL; + } + + if (!driver->buffering_flag[params->peripheral]) { + pr_err("diag: In %s, buffering flag not set for %d\n", __func__, + params->peripheral); + return -EINVAL; + } + + if (!driver->feature[peripheral].peripheral_buffering) { + pr_err("diag: In %s, peripheral %d doesn't support buffering\n", + __func__, peripheral); + return -EIO; + } + + switch (params->mode) { + case DIAG_BUFFERING_MODE_STREAMING: + mode = MODE_REALTIME; + break; + case DIAG_BUFFERING_MODE_THRESHOLD: + case DIAG_BUFFERING_MODE_CIRCULAR: + mode = MODE_NONREALTIME; + break; + default: + pr_err("diag: In %s, invalid tx mode %d\n", __func__, + params->mode); + return -EINVAL; + } + + if (!driver->feature[peripheral].peripheral_buffering) { + pr_debug("diag: In %s, peripheral %d doesn't support buffering\n", + __func__, peripheral); + driver->buffering_flag[params->peripheral] = 0; + return -EIO; + } + + /* + * Perform sanity on watermark values. These values must be + * checked irrespective of the buffering mode. + */ + if (((params->high_wm_val > DIAG_MAX_WM_VAL) || + (params->low_wm_val > DIAG_MAX_WM_VAL)) || + (params->low_wm_val > params->high_wm_val) || + ((params->low_wm_val == params->high_wm_val) && + (params->low_wm_val != DIAG_MIN_WM_VAL))) { + pr_err("diag: In %s, invalid watermark values, high: %d, low: %d, peripheral: %d\n", + __func__, params->high_wm_val, params->low_wm_val, + params->peripheral); + return -EINVAL; + } + + mutex_lock(&driver->mode_lock); + err = diag_send_buffering_tx_mode_pkt(peripheral, diag_id, params); + if (err) { + pr_err("diag: In %s, unable to send buffering mode packet to peripheral %d, err: %d\n", + __func__, peripheral, err); + goto fail; + } + err = diag_send_buffering_wm_values(peripheral, diag_id, params); + if (err) { + pr_err("diag: In %s, unable to send buffering wm value packet to peripheral %d, err: %d\n", + __func__, peripheral, err); + goto fail; + } + err = __diag_send_real_time_update(peripheral, mode, diag_id); + if (err) { + pr_err("diag: In %s, unable to send mode update to peripheral %d, mode: %d, err: %d\n", + __func__, peripheral, mode, err); + goto fail; + } + driver->buffering_mode[params->peripheral].peripheral = + params->peripheral; + driver->buffering_mode[params->peripheral].mode = + params->mode; + driver->buffering_mode[params->peripheral].low_wm_val = + params->low_wm_val; + driver->buffering_mode[params->peripheral].high_wm_val = + params->high_wm_val; + if (params->mode == DIAG_BUFFERING_MODE_STREAMING) + driver->buffering_flag[params->peripheral] = 0; +fail: + mutex_unlock(&driver->mode_lock); + return err; +} + +int diag_send_stm_state(uint8_t peripheral, uint8_t stm_control_data) +{ + struct diag_ctrl_msg_stm stm_msg; + int msg_size = sizeof(struct diag_ctrl_msg_stm); + int err = 0; + + if (peripheral >= NUM_PERIPHERALS) + return -EIO; + + if (!driver->diagfwd_cntl[peripheral] || + !driver->diagfwd_cntl[peripheral]->ch_open) { + pr_debug("diag: In %s, control channel is not open, p: %d\n", + __func__, peripheral); + return -ENODEV; + } + + if (driver->feature[peripheral].stm_support == DISABLE_STM) + return -EINVAL; + + stm_msg.ctrl_pkt_id = 21; + stm_msg.ctrl_pkt_data_len = 5; + stm_msg.version = 1; + stm_msg.control_data = stm_control_data; + err = diagfwd_write(peripheral, TYPE_CNTL, &stm_msg, msg_size); + if (err && err != -ENODEV) { + pr_err("diag: In %s, unable to write to smd, peripheral: %d, type: %d, len: %d, err: %d\n", + __func__, peripheral, TYPE_CNTL, + msg_size, err); + } + + return err; +} + +int diag_send_peripheral_drain_immediate(uint8_t pd, + uint8_t diag_id, int peripheral) +{ + int err = 0; + struct diag_ctrl_drain_immediate ctrl_pkt; + struct diag_ctrl_drain_immediate_v2 ctrl_pkt_v2; + + if (!driver->feature[peripheral].peripheral_buffering) { + pr_debug("diag: In %s, peripheral %d doesn't support buffering\n", + __func__, peripheral); + return -EINVAL; + } + + if (!driver->diagfwd_cntl[peripheral] || + !driver->diagfwd_cntl[peripheral]->ch_open) { + pr_debug("diag: In %s, control channel is not open, p: %d\n", + __func__, peripheral); + return -ENODEV; + } + + if (diag_id && driver->feature[peripheral].pd_buffering) { + ctrl_pkt_v2.pkt_id = DIAG_CTRL_MSG_PERIPHERAL_BUF_DRAIN_IMM; + /* + * The length of the ctrl pkt is size of version, + * diag_id and stream id + */ + ctrl_pkt_v2.len = sizeof(uint32_t) + (2 * sizeof(uint8_t)); + ctrl_pkt_v2.version = 2; + ctrl_pkt_v2.diag_id = diag_id; + ctrl_pkt_v2.stream_id = 1; + err = diagfwd_write(peripheral, TYPE_CNTL, &ctrl_pkt_v2, + sizeof(ctrl_pkt_v2)); + if (err && err != -ENODEV) { + pr_err("diag: Unable to send drain immediate ctrl packet to peripheral %d, err: %d\n", + peripheral, err); + } + } else { + ctrl_pkt.pkt_id = DIAG_CTRL_MSG_PERIPHERAL_BUF_DRAIN_IMM; + /* + * The length of the ctrl pkt is + * size of version and stream id + */ + ctrl_pkt.len = sizeof(uint32_t) + sizeof(uint8_t); + ctrl_pkt.version = 1; + ctrl_pkt.stream_id = 1; + err = diagfwd_write(peripheral, TYPE_CNTL, &ctrl_pkt, + sizeof(ctrl_pkt)); + if (err && err != -ENODEV) { + pr_err("diag: Unable to send drain immediate ctrl packet to peripheral %d, err: %d\n", + peripheral, err); + } + } + + return err; +} + +int diag_send_buffering_tx_mode_pkt(uint8_t peripheral, + uint8_t diag_id, struct diag_buffering_mode_t *params) +{ + int err = 0; + struct diag_ctrl_peripheral_tx_mode ctrl_pkt; + struct diag_ctrl_peripheral_tx_mode_v2 ctrl_pkt_v2; + + if (!params) + return -EIO; + + if (peripheral >= NUM_PERIPHERALS) { + pr_err("diag: In %s, invalid peripheral %d\n", __func__, + peripheral); + return -EINVAL; + } + + if (!driver->feature[peripheral].peripheral_buffering) { + pr_debug("diag: In %s, peripheral %d doesn't support buffering\n", + __func__, peripheral); + return -EINVAL; + } + + switch (params->mode) { + case DIAG_BUFFERING_MODE_STREAMING: + case DIAG_BUFFERING_MODE_THRESHOLD: + case DIAG_BUFFERING_MODE_CIRCULAR: + break; + default: + pr_err("diag: In %s, invalid tx mode: %d\n", __func__, + params->mode); + return -EINVAL; + } + + if (diag_id && + driver->feature[peripheral].pd_buffering) { + + ctrl_pkt_v2.pkt_id = DIAG_CTRL_MSG_CONFIG_PERIPHERAL_TX_MODE; + /* + * Control packet length is size of version, diag_id, + * stream_id and tx_mode + */ + ctrl_pkt_v2.len = sizeof(uint32_t) + (3 * sizeof(uint8_t)); + ctrl_pkt_v2.version = 2; + ctrl_pkt_v2.diag_id = diag_id; + ctrl_pkt_v2.stream_id = 1; + ctrl_pkt_v2.tx_mode = params->mode; + + err = diagfwd_write(peripheral, TYPE_CNTL, &ctrl_pkt_v2, + sizeof(ctrl_pkt_v2)); + if (err && err != -ENODEV) { + pr_err("diag: Unable to send tx_mode ctrl packet to peripheral %d, err: %d\n", + peripheral, err); + goto fail; + } + } else { + ctrl_pkt.pkt_id = DIAG_CTRL_MSG_CONFIG_PERIPHERAL_TX_MODE; + /* + * Control packet length is size of version, + * stream_id and tx_mode + */ + ctrl_pkt.len = sizeof(uint32_t) + (2 * sizeof(uint8_t)); + ctrl_pkt.version = 1; + ctrl_pkt.stream_id = 1; + ctrl_pkt.tx_mode = params->mode; + + err = diagfwd_write(peripheral, TYPE_CNTL, &ctrl_pkt, + sizeof(ctrl_pkt)); + if (err && err != -ENODEV) { + pr_err("diag: Unable to send tx_mode ctrl packet to peripheral %d, err: %d\n", + peripheral, err); + goto fail; + } + } + driver->buffering_mode[params->peripheral].mode = params->mode; + +fail: + return err; +} + +int diag_send_buffering_wm_values(uint8_t peripheral, + uint8_t diag_id, struct diag_buffering_mode_t *params) +{ + int err = 0; + struct diag_ctrl_set_wq_val ctrl_pkt; + struct diag_ctrl_set_wq_val_v2 ctrl_pkt_v2; + + if (!params) + return -EIO; + + if (peripheral >= NUM_PERIPHERALS) { + pr_err("diag: In %s, invalid peripheral %d\n", __func__, + peripheral); + return -EINVAL; + } + + if (!driver->feature[peripheral].peripheral_buffering) { + pr_debug("diag: In %s, peripheral %d doesn't support buffering\n", + __func__, peripheral); + return -EINVAL; + } + + if (!driver->diagfwd_cntl[peripheral] || + !driver->diagfwd_cntl[peripheral]->ch_open) { + pr_debug("diag: In %s, control channel is not open, p: %d\n", + __func__, peripheral); + return -ENODEV; + } + + switch (params->mode) { + case DIAG_BUFFERING_MODE_STREAMING: + case DIAG_BUFFERING_MODE_THRESHOLD: + case DIAG_BUFFERING_MODE_CIRCULAR: + break; + default: + pr_err("diag: In %s, invalid tx mode: %d\n", __func__, + params->mode); + return -EINVAL; + } + + if (diag_id && + driver->feature[peripheral].pd_buffering) { + ctrl_pkt_v2.pkt_id = DIAG_CTRL_MSG_CONFIG_PERIPHERAL_WMQ_VAL; + /* + * Control packet length is size of version, diag_id, + * stream_id and wmq values + */ + ctrl_pkt_v2.len = sizeof(uint32_t) + (4 * sizeof(uint8_t)); + ctrl_pkt_v2.version = 2; + ctrl_pkt_v2.diag_id = diag_id; + ctrl_pkt_v2.stream_id = 1; + ctrl_pkt_v2.high_wm_val = params->high_wm_val; + ctrl_pkt_v2.low_wm_val = params->low_wm_val; + + err = diagfwd_write(peripheral, TYPE_CNTL, &ctrl_pkt_v2, + sizeof(ctrl_pkt_v2)); + if (err && err != -ENODEV) { + pr_err("diag: Unable to send watermark values to peripheral %d, err: %d\n", + peripheral, err); + } + } else { + ctrl_pkt.pkt_id = DIAG_CTRL_MSG_CONFIG_PERIPHERAL_WMQ_VAL; + /* + * Control packet length is size of version, + * stream_id and wmq values + */ + ctrl_pkt.len = sizeof(uint32_t) + (3 * sizeof(uint8_t)); + ctrl_pkt.version = 1; + ctrl_pkt.stream_id = 1; + ctrl_pkt.high_wm_val = params->high_wm_val; + ctrl_pkt.low_wm_val = params->low_wm_val; + + err = diagfwd_write(peripheral, TYPE_CNTL, &ctrl_pkt, + sizeof(ctrl_pkt)); + if (err && err != -ENODEV) { + pr_err("diag: Unable to send watermark values to peripheral %d, err: %d\n", + peripheral, err); + } + } + return err; +} + +int diagfwd_cntl_init(void) +{ + uint8_t peripheral = 0; + + reg_dirty = 0; + driver->polling_reg_flag = 0; + driver->log_on_demand_support = 1; + driver->stm_peripheral = 0; + driver->close_transport = 0; + for (peripheral = 0; peripheral < NUM_PERIPHERALS; peripheral++) + driver->buffering_flag[peripheral] = 0; + + mutex_init(&driver->cntl_lock); + INIT_WORK(&(driver->stm_update_work), diag_stm_update_work_fn); + INIT_WORK(&(driver->mask_update_work), diag_mask_update_work_fn); + INIT_WORK(&(driver->close_transport_work), + diag_close_transport_work_fn); + + driver->cntl_wq = create_singlethread_workqueue("diag_cntl_wq"); + if (!driver->cntl_wq) + return -ENOMEM; + + return 0; +} + +void diagfwd_cntl_channel_init(void) +{ + uint8_t peripheral; + + for (peripheral = 0; peripheral < NUM_PERIPHERALS; peripheral++) { + diagfwd_early_open(peripheral); + diagfwd_open(peripheral, TYPE_CNTL); + } +} + +void diagfwd_cntl_exit(void) +{ + if (driver->cntl_wq) + destroy_workqueue(driver->cntl_wq); + return; +} diff -Nruw linux-4.4.115-fbx/drivers/char/diag./diagfwd_cntl.h linux-4.4.115-fbx/drivers/char/diag/diagfwd_cntl.h --- linux-4.4.115-fbx/drivers/char/diag./diagfwd_cntl.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-4.4.115-fbx/drivers/char/diag/diagfwd_cntl.h 2019-01-22 16:16:22.959241480 +0100 @@ -0,0 +1,332 @@ +/* Copyright (c) 2011-2017, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef DIAGFWD_CNTL_H +#define DIAGFWD_CNTL_H + +/* Message registration commands */ +#define DIAG_CTRL_MSG_REG 1 +/* Message passing for DTR events */ +#define DIAG_CTRL_MSG_DTR 2 +/* Control Diag sleep vote, buffering etc */ +#define DIAG_CTRL_MSG_DIAGMODE 3 +/* Diag data based on "light" diag mask */ +#define DIAG_CTRL_MSG_DIAGDATA 4 +/* Send diag internal feature mask 'diag_int_feature_mask' */ +#define DIAG_CTRL_MSG_FEATURE 8 +/* Send Diag log mask for a particular equip id */ +#define DIAG_CTRL_MSG_EQUIP_LOG_MASK 9 +/* Send Diag event mask */ +#define DIAG_CTRL_MSG_EVENT_MASK_V2 10 +/* Send Diag F3 mask */ +#define DIAG_CTRL_MSG_F3_MASK_V2 11 +#define DIAG_CTRL_MSG_NUM_PRESETS 12 +#define DIAG_CTRL_MSG_SET_PRESET_ID 13 +#define DIAG_CTRL_MSG_LOG_MASK_WITH_PRESET_ID 14 +#define DIAG_CTRL_MSG_EVENT_MASK_WITH_PRESET_ID 15 +#define DIAG_CTRL_MSG_F3_MASK_WITH_PRESET_ID 16 +#define DIAG_CTRL_MSG_CONFIG_PERIPHERAL_TX_MODE 17 +#define DIAG_CTRL_MSG_PERIPHERAL_BUF_DRAIN_IMM 18 +#define DIAG_CTRL_MSG_CONFIG_PERIPHERAL_WMQ_VAL 19 +#define DIAG_CTRL_MSG_DCI_CONNECTION_STATUS 20 +#define DIAG_CTRL_MSG_LAST_EVENT_REPORT 22 +#define DIAG_CTRL_MSG_LOG_RANGE_REPORT 23 +#define DIAG_CTRL_MSG_SSID_RANGE_REPORT 24 +#define DIAG_CTRL_MSG_BUILD_MASK_REPORT 25 +#define DIAG_CTRL_MSG_DEREG 27 +#define DIAG_CTRL_MSG_DCI_HANDSHAKE_PKT 29 +#define DIAG_CTRL_MSG_PD_STATUS 30 +#define DIAG_CTRL_MSG_TIME_SYNC_PKT 31 + +/* + * Feature Mask Definitions: Feature mask is used to sepcify Diag features + * supported by the Apps processor + * + * F_DIAG_FEATURE_MASK_SUPPORT - Denotes we support sending and receiving + * feature masks + * F_DIAG_LOG_ON_DEMAND_APPS - Apps responds to Log on Demand request + * F_DIAG_REQ_RSP_SUPPORT - Apps supported dedicated request response Channel + * F_DIAG_APPS_HDLC_ENCODE - HDLC encoding is done on the forward channel + * F_DIAG_STM - Denotes Apps supports Diag over STM + */ +#define F_DIAG_FEATURE_MASK_SUPPORT 0 +#define F_DIAG_LOG_ON_DEMAND_APPS 2 +#define F_DIAG_REQ_RSP_SUPPORT 4 +#define F_DIAG_APPS_HDLC_ENCODE 6 +#define F_DIAG_STM 9 +#define F_DIAG_PERIPHERAL_BUFFERING 10 +#define F_DIAG_MASK_CENTRALIZATION 11 +#define F_DIAG_SOCKETS_ENABLED 13 +#define F_DIAG_DCI_EXTENDED_HEADER_SUPPORT 14 +#define F_DIAG_PKT_HEADER_UNTAG 16 +#define F_DIAG_PD_BUFFERING 17 + +#define ENABLE_SEPARATE_CMDRSP 1 +#define DISABLE_SEPARATE_CMDRSP 0 + +#define DISABLE_STM 0 +#define ENABLE_STM 1 +#define STATUS_STM 2 + +#define UPDATE_PERIPHERAL_STM_STATE 1 +#define CLEAR_PERIPHERAL_STM_STATE 2 + +#define ENABLE_APPS_HDLC_ENCODING 1 +#define DISABLE_APPS_HDLC_ENCODING 0 + +#define ENABLE_PKT_HEADER_UNTAGGING 1 +#define DISABLE_PKT_HEADER_UNTAGGING 0 + +#define DIAG_MODE_PKT_LEN 36 +#define DIAG_MODE_PKT_LEN_V2 37 + +struct diag_ctrl_pkt_header_t { + uint32_t pkt_id; + uint32_t len; +}; + +struct cmd_code_range { + uint16_t cmd_code_lo; + uint16_t cmd_code_hi; + uint32_t data; +}; + +struct diag_ctrl_cmd_reg { + uint32_t pkt_id; + uint32_t len; + uint32_t version; + uint16_t cmd_code; + uint16_t subsysid; + uint16_t count_entries; + uint16_t port; +}; + +struct diag_ctrl_cmd_dereg { + uint32_t pkt_id; + uint32_t len; + uint32_t version; + uint16_t cmd_code; + uint16_t subsysid; + uint16_t count_entries; +} __packed; + +struct diag_ctrl_event_mask { + uint32_t cmd_type; + uint32_t data_len; + uint8_t stream_id; + uint8_t status; + uint8_t event_config; + uint32_t event_mask_size; + /* Copy event mask here */ +} __packed; + +struct diag_ctrl_log_mask { + uint32_t cmd_type; + uint32_t data_len; + uint8_t stream_id; + uint8_t status; + uint8_t equip_id; + uint32_t num_items; /* Last log code for this equip_id */ + uint32_t log_mask_size; /* Size of log mask stored in log_mask[] */ + /* Copy log mask here */ +} __packed; + +struct diag_ctrl_msg_mask { + uint32_t cmd_type; + uint32_t data_len; + uint8_t stream_id; + uint8_t status; + uint8_t msg_mode; + uint16_t ssid_first; /* Start of range of supported SSIDs */ + uint16_t ssid_last; /* Last SSID in range */ + uint32_t msg_mask_size; /* ssid_last - ssid_first + 1 */ + /* Copy msg mask here */ +} __packed; + +struct diag_ctrl_feature_mask { + uint32_t ctrl_pkt_id; + uint32_t ctrl_pkt_data_len; + uint32_t feature_mask_len; + /* Copy feature mask here */ +} __packed; + +struct diag_ctrl_msg_diagmode { + uint32_t ctrl_pkt_id; + uint32_t ctrl_pkt_data_len; + uint32_t version; + uint32_t sleep_vote; + uint32_t real_time; + uint32_t use_nrt_values; + uint32_t commit_threshold; + uint32_t sleep_threshold; + uint32_t sleep_time; + uint32_t drain_timer_val; + uint32_t event_stale_timer_val; +} __packed; + +struct diag_ctrl_msg_diagmode_v2 { + uint32_t ctrl_pkt_id; + uint32_t ctrl_pkt_data_len; + uint32_t version; + uint32_t sleep_vote; + uint32_t real_time; + uint32_t use_nrt_values; + uint32_t commit_threshold; + uint32_t sleep_threshold; + uint32_t sleep_time; + uint32_t drain_timer_val; + uint32_t event_stale_timer_val; + uint8_t diag_id; +} __packed; + +struct diag_ctrl_msg_stm { + uint32_t ctrl_pkt_id; + uint32_t ctrl_pkt_data_len; + uint32_t version; + uint8_t control_data; +} __packed; + +struct diag_ctrl_msg_time_sync { + uint32_t ctrl_pkt_id; + uint32_t ctrl_pkt_data_len; + uint32_t version; + uint8_t time_api; +} __packed; + +struct diag_ctrl_dci_status { + uint32_t ctrl_pkt_id; + uint32_t ctrl_pkt_data_len; + uint32_t version; + uint8_t count; +} __packed; + +struct diag_ctrl_dci_handshake_pkt { + uint32_t ctrl_pkt_id; + uint32_t ctrl_pkt_data_len; + uint32_t version; + uint32_t magic; +} __packed; + +struct diag_ctrl_msg_pd_status { + uint32_t ctrl_pkt_id; + uint32_t ctrl_pkt_data_len; + uint32_t version; + uint32_t pd_id; + uint8_t status; +} __packed; + +struct diag_ctrl_last_event_report { + uint32_t pkt_id; + uint32_t len; + uint32_t version; + uint16_t event_last_id; +} __packed; + +struct diag_ctrl_log_range_report { + uint32_t pkt_id; + uint32_t len; + uint32_t version; + uint32_t last_equip_id; + uint32_t num_ranges; +} __packed; + +struct diag_ctrl_log_range { + uint32_t equip_id; + uint32_t num_items; +} __packed; + +struct diag_ctrl_ssid_range_report { + uint32_t pkt_id; + uint32_t len; + uint32_t version; + uint32_t count; +} __packed; + +struct diag_ctrl_build_mask_report { + uint32_t pkt_id; + uint32_t len; + uint32_t version; + uint32_t count; +} __packed; + +struct diag_ctrl_peripheral_tx_mode { + uint32_t pkt_id; + uint32_t len; + uint32_t version; + uint8_t stream_id; + uint8_t tx_mode; +} __packed; + +struct diag_ctrl_peripheral_tx_mode_v2 { + uint32_t pkt_id; + uint32_t len; + uint32_t version; + uint8_t diag_id; + uint8_t stream_id; + uint8_t tx_mode; +} __packed; + +struct diag_ctrl_drain_immediate { + uint32_t pkt_id; + uint32_t len; + uint32_t version; + uint8_t stream_id; +} __packed; + +struct diag_ctrl_drain_immediate_v2 { + uint32_t pkt_id; + uint32_t len; + uint32_t version; + uint8_t diag_id; + uint8_t stream_id; +} __packed; + +struct diag_ctrl_set_wq_val { + uint32_t pkt_id; + uint32_t len; + uint32_t version; + uint8_t stream_id; + uint8_t high_wm_val; + uint8_t low_wm_val; +} __packed; + +struct diag_ctrl_set_wq_val_v2 { + uint32_t pkt_id; + uint32_t len; + uint32_t version; + uint8_t diag_id; + uint8_t stream_id; + uint8_t high_wm_val; + uint8_t low_wm_val; +} __packed; + +int diagfwd_cntl_init(void); +void diagfwd_cntl_channel_init(void); +void diagfwd_cntl_exit(void); +void diag_cntl_channel_open(struct diagfwd_info *p_info); +void diag_cntl_channel_close(struct diagfwd_info *p_info); +void diag_cntl_process_read_data(struct diagfwd_info *p_info, void *buf, + int len); +int diag_send_real_time_update(uint8_t peripheral, int real_time); +void diag_map_pd_to_diagid(uint8_t pd, uint8_t *diag_id, int *peripheral); +int diag_send_peripheral_buffering_mode(struct diag_buffering_mode_t *params); +void diag_update_proc_vote(uint16_t proc, uint8_t vote, int index); +void diag_update_real_time_vote(uint16_t proc, uint8_t real_time, int index); +void diag_real_time_work_fn(struct work_struct *work); +int diag_send_stm_state(uint8_t peripheral, uint8_t stm_control_data); +int diag_send_peripheral_drain_immediate(uint8_t pd, + uint8_t diag_id, int peripheral); +int diag_send_buffering_tx_mode_pkt(uint8_t peripheral, + uint8_t diag_id, struct diag_buffering_mode_t *params); +int diag_send_buffering_wm_values(uint8_t peripheral, + uint8_t diag_id, struct diag_buffering_mode_t *params); +#endif diff -Nruw linux-4.4.115-fbx/drivers/char/diag./diagfwd_glink.c linux-4.4.115-fbx/drivers/char/diag/diagfwd_glink.c --- linux-4.4.115-fbx/drivers/char/diag./diagfwd_glink.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-4.4.115-fbx/drivers/char/diag/diagfwd_glink.c 2019-01-22 16:16:22.959241480 +0100 @@ -0,0 +1,830 @@ +/* Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "diagchar.h" +#include "diagfwd.h" +#include "diagfwd_peripheral.h" +#include "diagfwd_glink.h" +#include "diag_ipc_logging.h" + +struct diag_glink_info glink_data[NUM_PERIPHERALS] = { + { + .peripheral = PERIPHERAL_MODEM, + .type = TYPE_DATA, + .edge = "mpss", + .name = "DIAG_DATA", + .hdl = NULL + }, + { + .peripheral = PERIPHERAL_LPASS, + .type = TYPE_DATA, + .edge = "lpass", + .name = "DIAG_DATA", + .hdl = NULL + }, + { + .peripheral = PERIPHERAL_WCNSS, + .type = TYPE_DATA, + .edge = "wcnss", + .name = "DIAG_DATA", + .hdl = NULL + }, + { + .peripheral = PERIPHERAL_SENSORS, + .type = TYPE_DATA, + .edge = "dsps", + .name = "DIAG_DATA", + .hdl = NULL + }, + { + .peripheral = PERIPHERAL_WDSP, + .type = TYPE_DATA, + .edge = "wdsp", + .name = "DIAG_DATA", + .hdl = NULL + }, + { + .peripheral = PERIPHERAL_CDSP, + .type = TYPE_DATA, + .edge = "cdsp", + .name = "DIAG_DATA", + .hdl = NULL + } +}; + +struct diag_glink_info glink_cntl[NUM_PERIPHERALS] = { + { + .peripheral = PERIPHERAL_MODEM, + .type = TYPE_CNTL, + .edge = "mpss", + .name = "DIAG_CTRL", + .hdl = NULL + }, + { + .peripheral = PERIPHERAL_LPASS, + .type = TYPE_CNTL, + .edge = "lpass", + .name = "DIAG_CTRL", + .hdl = NULL + }, + { + .peripheral = PERIPHERAL_WCNSS, + .type = TYPE_CNTL, + .edge = "wcnss", + .name = "DIAG_CTRL", + .hdl = NULL + }, + { + .peripheral = PERIPHERAL_SENSORS, + .type = TYPE_CNTL, + .edge = "dsps", + .name = "DIAG_CTRL", + .hdl = NULL + }, + { + .peripheral = PERIPHERAL_WDSP, + .type = TYPE_CNTL, + .edge = "wdsp", + .name = "DIAG_CTRL", + .hdl = NULL + }, + { + .peripheral = PERIPHERAL_CDSP, + .type = TYPE_CNTL, + .edge = "cdsp", + .name = "DIAG_CTRL", + .hdl = NULL + } +}; + +struct diag_glink_info glink_dci[NUM_PERIPHERALS] = { + { + .peripheral = PERIPHERAL_MODEM, + .type = TYPE_DCI, + .edge = "mpss", + .name = "DIAG_DCI_DATA", + .hdl = NULL + }, + { + .peripheral = PERIPHERAL_LPASS, + .type = TYPE_DCI, + .edge = "lpass", + .name = "DIAG_DCI_DATA", + .hdl = NULL + }, + { + .peripheral = PERIPHERAL_WCNSS, + .type = TYPE_DCI, + .edge = "wcnss", + .name = "DIAG_DCI_DATA", + .hdl = NULL + }, + { + .peripheral = PERIPHERAL_SENSORS, + .type = TYPE_DCI, + .edge = "dsps", + .name = "DIAG_DCI_DATA", + .hdl = NULL + }, + { + .peripheral = PERIPHERAL_WDSP, + .type = TYPE_DCI, + .edge = "wdsp", + .name = "DIAG_DCI_DATA", + .hdl = NULL + }, + { + .peripheral = PERIPHERAL_CDSP, + .type = TYPE_DCI, + .edge = "cdsp", + .name = "DIAG_DCI_DATA", + .hdl = NULL + } +}; + +struct diag_glink_info glink_cmd[NUM_PERIPHERALS] = { + { + .peripheral = PERIPHERAL_MODEM, + .type = TYPE_CMD, + .edge = "mpss", + .name = "DIAG_CMD", + .hdl = NULL + }, + { + .peripheral = PERIPHERAL_LPASS, + .type = TYPE_CMD, + .edge = "lpass", + .name = "DIAG_CMD", + .hdl = NULL + }, + { + .peripheral = PERIPHERAL_WCNSS, + .type = TYPE_CMD, + .edge = "wcnss", + .name = "DIAG_CMD", + .hdl = NULL + }, + { + .peripheral = PERIPHERAL_SENSORS, + .type = TYPE_CMD, + .edge = "dsps", + .name = "DIAG_CMD", + .hdl = NULL + }, + { + .peripheral = PERIPHERAL_WDSP, + .type = TYPE_CMD, + .edge = "wdsp", + .name = "DIAG_CMD", + .hdl = NULL + }, + { + .peripheral = PERIPHERAL_CDSP, + .type = TYPE_CMD, + .edge = "cdsp", + .name = "DIAG_CMD", + .hdl = NULL + } +}; + +struct diag_glink_info glink_dci_cmd[NUM_PERIPHERALS] = { + { + .peripheral = PERIPHERAL_MODEM, + .type = TYPE_DCI_CMD, + .edge = "mpss", + .name = "DIAG_DCI_CMD", + .hdl = NULL + }, + { + .peripheral = PERIPHERAL_LPASS, + .type = TYPE_DCI_CMD, + .edge = "lpass", + .name = "DIAG_DCI_CMD", + .hdl = NULL + }, + { + .peripheral = PERIPHERAL_WCNSS, + .type = TYPE_DCI_CMD, + .edge = "wcnss", + .name = "DIAG_DCI_CMD", + .hdl = NULL + }, + { + .peripheral = PERIPHERAL_SENSORS, + .type = TYPE_DCI_CMD, + .edge = "dsps", + .name = "DIAG_DCI_CMD", + .hdl = NULL + }, + { + .peripheral = PERIPHERAL_WDSP, + .type = TYPE_DCI_CMD, + .edge = "wdsp", + .name = "DIAG_DCI_CMD", + .hdl = NULL + }, + { + .peripheral = PERIPHERAL_CDSP, + .type = TYPE_DCI_CMD, + .edge = "cdsp", + .name = "DIAG_DCI_CMD", + .hdl = NULL + } +}; + +static void diag_state_open_glink(void *ctxt); +static void diag_state_close_glink(void *ctxt); +static int diag_glink_write(void *ctxt, unsigned char *buf, int len); +static int diag_glink_read(void *ctxt, unsigned char *buf, int buf_len); +static void diag_glink_queue_read(void *ctxt); + +static struct diag_peripheral_ops glink_ops = { + .open = diag_state_open_glink, + .close = diag_state_close_glink, + .write = diag_glink_write, + .read = diag_glink_read, + .queue_read = diag_glink_queue_read +}; + +static void diag_state_open_glink(void *ctxt) +{ + struct diag_glink_info *glink_info = NULL; + + if (!ctxt) + return; + + glink_info = (struct diag_glink_info *)(ctxt); + atomic_set(&glink_info->diag_state, 1); + DIAG_LOG(DIAG_DEBUG_PERIPHERALS, + "%s setting diag state to 1", glink_info->name); +} + +static void diag_glink_queue_read(void *ctxt) +{ + struct diag_glink_info *glink_info = NULL; + + if (!ctxt) + return; + + glink_info = (struct diag_glink_info *)ctxt; + if (glink_info->hdl && glink_info->wq && + atomic_read(&glink_info->opened)) + queue_work(glink_info->wq, &(glink_info->read_work)); +} + +static void diag_state_close_glink(void *ctxt) +{ + struct diag_glink_info *glink_info = NULL; + + if (!ctxt) + return; + + glink_info = (struct diag_glink_info *)(ctxt); + atomic_set(&glink_info->diag_state, 0); + DIAG_LOG(DIAG_DEBUG_PERIPHERALS, + "%s setting diag state to 0", glink_info->name); + wake_up_interruptible(&glink_info->read_wait_q); + flush_workqueue(glink_info->wq); +} + +int diag_glink_check_state(void *ctxt) +{ + struct diag_glink_info *info = NULL; + + if (!ctxt) + return 0; + + info = (struct diag_glink_info *)ctxt; + return (int)(atomic_read(&info->diag_state)); +} + +static int diag_glink_read(void *ctxt, unsigned char *buf, int buf_len) +{ + struct diag_glink_info *glink_info = NULL; + int ret_val = 0; + + if (!ctxt || !buf || buf_len <= 0) + return -EIO; + + glink_info = (struct diag_glink_info *)ctxt; + if (!glink_info || !atomic_read(&glink_info->opened) || + !glink_info->hdl || !glink_info->inited) { + DIAG_LOG(DIAG_DEBUG_PERIPHERALS, + "diag:Glink channel not opened"); + return -EIO; + } + + ret_val = glink_queue_rx_intent(glink_info->hdl, buf, buf_len); + if (ret_val == 0) + DIAG_LOG(DIAG_DEBUG_PERIPHERALS, + "diag: queued an rx intent ch:%s perip:%d buf:%pK of len:%d\n", + glink_info->name, glink_info->peripheral, buf, buf_len); + + return ret_val; +} + +static void diag_glink_read_work_fn(struct work_struct *work) +{ + struct diag_glink_info *glink_info = container_of(work, + struct diag_glink_info, + read_work); + + if (!glink_info || !atomic_read(&glink_info->opened)) + return; + + if (!glink_info->inited) { + diag_ws_release(); + return; + } + + diagfwd_channel_read(glink_info->fwd_ctxt); +} +struct diag_glink_read_work { + struct diag_glink_info *glink_info; + const void *ptr_read_done; + const void *ptr_rx_done; + size_t ptr_read_size; + struct work_struct work; +}; + +static void diag_glink_notify_rx_work_fn(struct work_struct *work) +{ + struct diag_glink_read_work *read_work = container_of(work, + struct diag_glink_read_work, work); + struct diag_glink_info *glink_info = read_work->glink_info; + + if (!glink_info || !glink_info->hdl) { + kfree(read_work); + return; + } + + diagfwd_channel_read_done(glink_info->fwd_ctxt, + (unsigned char *)(read_work->ptr_read_done), + read_work->ptr_read_size); + + glink_rx_done(glink_info->hdl, read_work->ptr_rx_done, false); + + DIAG_LOG(DIAG_DEBUG_PERIPHERALS, + "diag: Rx done for packet %pK of len: %d periph: %d ch: %d\n", + read_work->ptr_rx_done, (int)read_work->ptr_read_size, + glink_info->peripheral, glink_info->type); + kfree(read_work); +} + +static void diag_glink_notify_rx(void *hdl, const void *priv, + const void *pkt_priv, const void *ptr, + size_t size) +{ + struct diag_glink_info *glink_info = (struct diag_glink_info *)priv; + struct diag_glink_read_work *read_work; + + if (!glink_info || !glink_info->hdl || !ptr || !pkt_priv || !hdl) + return; + + if (size <= 0) + return; + + DIAG_LOG(DIAG_DEBUG_PERIPHERALS, + "diag: received a packet %pK of len:%d from periph:%d ch:%d\n", + ptr, (int)size, glink_info->peripheral, glink_info->type); + + read_work = kmalloc(sizeof(*read_work), GFP_ATOMIC); + if (!read_work) { + DIAG_LOG(DIAG_DEBUG_PERIPHERALS, + "diag: Could not allocate read_work\n"); + glink_rx_done(glink_info->hdl, ptr, true); + return; + } + + memcpy((void *)pkt_priv, ptr, size); + + read_work->glink_info = glink_info; + read_work->ptr_read_done = pkt_priv; + read_work->ptr_rx_done = ptr; + read_work->ptr_read_size = size; + INIT_WORK(&read_work->work, diag_glink_notify_rx_work_fn); + queue_work(glink_info->wq, &read_work->work); + + DIAG_LOG(DIAG_DEBUG_PERIPHERALS, + "diag: Rx queued for packet %pK of len: %d periph: %d ch: %d\n", + ptr, (int)size, glink_info->peripheral, glink_info->type); +} + +static void diag_glink_notify_remote_rx_intent(void *hdl, const void *priv, + size_t size) +{ + struct diag_glink_info *glink_info = (struct diag_glink_info *)priv; + + if (!glink_info) + return; + + atomic_inc(&glink_info->tx_intent_ready); + wake_up_interruptible(&glink_info->wait_q); + DIAG_LOG(DIAG_DEBUG_PERIPHERALS, + "diag:received remote rx intent for %d type %d\n", + glink_info->peripheral, glink_info->type); +} + +static void diag_glink_notify_tx_done(void *hdl, const void *priv, + const void *pkt_priv, + const void *ptr) +{ + struct diag_glink_info *glink_info = NULL; + struct diagfwd_info *fwd_info = NULL; + int found = 0; + + glink_info = (struct diag_glink_info *)priv; + if (!glink_info) + return; + + fwd_info = glink_info->fwd_ctxt; + DIAG_LOG(DIAG_DEBUG_PERIPHERALS, + "diag: Received glink tx done notify for ptr%pK pkt_priv %pK\n", + ptr, pkt_priv); + found = diagfwd_write_buffer_done(fwd_info, ptr); + if (!found) + DIAG_LOG(DIAG_DEBUG_PERIPHERALS, + "Received Tx done on invalid buffer ptr %pK\n", ptr); +} + +static int diag_glink_write(void *ctxt, unsigned char *buf, int len) +{ + struct diag_glink_info *glink_info = NULL; + int err = 0; + uint32_t tx_flags = GLINK_TX_REQ_INTENT; + + if (!ctxt || !buf) + return -EIO; + + glink_info = (struct diag_glink_info *)ctxt; + if (!glink_info || len <= 0) { + pr_err_ratelimited("diag: In %s, invalid params, glink_info: %pK, buf: %pK, len: %d\n", + __func__, glink_info, buf, len); + return -EINVAL; + } + + if (!glink_info->inited || !glink_info->hdl || + !atomic_read(&glink_info->opened)) { + pr_err_ratelimited("diag: In %s, glink not inited, glink_info: %pK, buf: %pK, len: %d\n", + __func__, glink_info, buf, len); + return -ENODEV; + } + + if (atomic_read(&glink_info->tx_intent_ready)) { + atomic_dec(&glink_info->tx_intent_ready); + err = glink_tx(glink_info->hdl, glink_info, buf, len, tx_flags); + if (!err) { + DIAG_LOG(DIAG_DEBUG_PERIPHERALS, + "%s wrote to glink, len: %d\n", + glink_info->name, len); + } + } else + err = -ENOMEM; + + return err; + +} + +static void diag_glink_connect_work_fn(struct work_struct *work) +{ + struct diag_glink_info *glink_info = container_of(work, + struct diag_glink_info, + connect_work); + if (!glink_info || !glink_info->hdl) + return; + atomic_set(&glink_info->opened, 1); + diagfwd_channel_open(glink_info->fwd_ctxt); + diagfwd_late_open(glink_info->fwd_ctxt); + DIAG_LOG(DIAG_DEBUG_PERIPHERALS, "glink channel open: p: %d t: %d\n", + glink_info->peripheral, glink_info->type); +} + +static void diag_glink_remote_disconnect_work_fn(struct work_struct *work) +{ + struct diag_glink_info *glink_info = container_of(work, + struct diag_glink_info, + remote_disconnect_work); + if (!glink_info || !glink_info->hdl) + return; + atomic_set(&glink_info->opened, 0); + diagfwd_channel_close(glink_info->fwd_ctxt); + atomic_set(&glink_info->tx_intent_ready, 0); +} + +static void diag_glink_late_init_work_fn(struct work_struct *work) +{ + struct diag_glink_info *glink_info = container_of(work, + struct diag_glink_info, + late_init_work); + if (!glink_info || !glink_info->hdl) + return; + diagfwd_channel_open(glink_info->fwd_ctxt); + DIAG_LOG(DIAG_DEBUG_PERIPHERALS, "glink late init p: %d t: %d\n", + glink_info->peripheral, glink_info->type); +} + +static void diag_glink_transport_notify_state(void *handle, const void *priv, + unsigned event) +{ + struct diag_glink_info *glink_info = (struct diag_glink_info *)priv; + + if (!glink_info) + return; + + switch (event) { + case GLINK_CONNECTED: + DIAG_LOG(DIAG_DEBUG_PERIPHERALS, + "%s received channel connect for periph:%d\n", + glink_info->name, glink_info->peripheral); + queue_work(glink_info->wq, &glink_info->connect_work); + break; + case GLINK_LOCAL_DISCONNECTED: + DIAG_LOG(DIAG_DEBUG_PERIPHERALS, + "%s received channel disconnect for periph:%d\n", + glink_info->name, glink_info->peripheral); + + break; + case GLINK_REMOTE_DISCONNECTED: + DIAG_LOG(DIAG_DEBUG_PERIPHERALS, + "%s received channel remote disconnect for periph:%d\n", + glink_info->name, glink_info->peripheral); + queue_work(glink_info->wq, &glink_info->remote_disconnect_work); + break; + default: + DIAG_LOG(DIAG_DEBUG_PERIPHERALS, + "%s received invalid notification\n", + glink_info->name); + break; + } + +} +static void diag_glink_open_work_fn(struct work_struct *work) +{ + struct diag_glink_info *glink_info = container_of(work, + struct diag_glink_info, + open_work); + struct glink_open_config open_cfg; + void *handle = NULL; + + if (!glink_info || glink_info->hdl) + return; + + memset(&open_cfg, 0, sizeof(struct glink_open_config)); + open_cfg.priv = glink_info; + open_cfg.edge = glink_info->edge; + open_cfg.name = glink_info->name; + open_cfg.notify_rx = diag_glink_notify_rx; + open_cfg.notify_tx_done = diag_glink_notify_tx_done; + open_cfg.notify_state = diag_glink_transport_notify_state; + open_cfg.notify_remote_rx_intent = diag_glink_notify_remote_rx_intent; + handle = glink_open(&open_cfg); + if (IS_ERR_OR_NULL(handle)) { + DIAG_LOG(DIAG_DEBUG_PERIPHERALS, "error opening channel %s", + glink_info->name); + } else + glink_info->hdl = handle; +} + +static void diag_glink_close_work_fn(struct work_struct *work) +{ + struct diag_glink_info *glink_info = container_of(work, + struct diag_glink_info, + close_work); + if (!glink_info || !glink_info->inited || !glink_info->hdl) + return; + + glink_close(glink_info->hdl); + atomic_set(&glink_info->opened, 0); + atomic_set(&glink_info->tx_intent_ready, 0); + glink_info->hdl = NULL; + diagfwd_channel_close(glink_info->fwd_ctxt); +} + +static void diag_glink_notify_cb(struct glink_link_state_cb_info *cb_info, + void *priv) +{ + struct diag_glink_info *glink_info = NULL; + + glink_info = (struct diag_glink_info *)priv; + if (!glink_info) + return; + if (!cb_info) + return; + + switch (cb_info->link_state) { + case GLINK_LINK_STATE_UP: + DIAG_LOG(DIAG_DEBUG_PERIPHERALS, + "%s channel opened for periph:%d\n", + glink_info->name, glink_info->peripheral); + queue_work(glink_info->wq, &glink_info->open_work); + break; + case GLINK_LINK_STATE_DOWN: + DIAG_LOG(DIAG_DEBUG_PERIPHERALS, + "%s channel closed for periph:%d\n", + glink_info->name, glink_info->peripheral); + queue_work(glink_info->wq, &glink_info->close_work); + break; + default: + DIAG_LOG(DIAG_DEBUG_PERIPHERALS, + "Invalid link state notification for ch:%s\n", + glink_info->name); + break; + + } +} + +static void glink_late_init(struct diag_glink_info *glink_info) +{ + struct diagfwd_info *fwd_info = NULL; + + if (!glink_info) + return; + + DIAG_LOG(DIAG_DEBUG_PERIPHERALS, "%s entering\n", + glink_info->name); + + diagfwd_register(TRANSPORT_GLINK, glink_info->peripheral, + glink_info->type, (void *)glink_info, + &glink_ops, &glink_info->fwd_ctxt); + fwd_info = glink_info->fwd_ctxt; + if (!fwd_info) + return; + + glink_info->inited = 1; + + if (atomic_read(&glink_info->opened)) + queue_work(glink_info->wq, &(glink_info->late_init_work)); + + DIAG_LOG(DIAG_DEBUG_PERIPHERALS, "%s exiting\n", + glink_info->name); +} + +int diag_glink_init_peripheral(uint8_t peripheral) +{ + if (peripheral >= NUM_PERIPHERALS) { + pr_err("diag: In %s, invalid peripheral %d\n", + __func__, peripheral); + return -EINVAL; + } + + glink_late_init(&glink_data[peripheral]); + glink_late_init(&glink_dci[peripheral]); + glink_late_init(&glink_cmd[peripheral]); + glink_late_init(&glink_dci_cmd[peripheral]); + + return 0; +} + +static void __diag_glink_init(struct diag_glink_info *glink_info) +{ + char wq_name[DIAG_GLINK_NAME_SZ + 12]; + struct glink_link_info link_info; + void *link_state_handle = NULL; + + if (!glink_info) + return; + + init_waitqueue_head(&glink_info->wait_q); + init_waitqueue_head(&glink_info->read_wait_q); + mutex_init(&glink_info->lock); + strlcpy(wq_name, "DIAG_GLINK_", 12); + strlcat(wq_name, glink_info->name, sizeof(glink_info->name)); + glink_info->wq = create_singlethread_workqueue(wq_name); + if (!glink_info->wq) { + pr_err("diag: In %s, unable to create workqueue for glink ch:%s\n", + __func__, glink_info->name); + return; + } + INIT_WORK(&(glink_info->open_work), diag_glink_open_work_fn); + INIT_WORK(&(glink_info->close_work), diag_glink_close_work_fn); + INIT_WORK(&(glink_info->read_work), diag_glink_read_work_fn); + INIT_WORK(&(glink_info->connect_work), diag_glink_connect_work_fn); + INIT_WORK(&(glink_info->remote_disconnect_work), + diag_glink_remote_disconnect_work_fn); + INIT_WORK(&(glink_info->late_init_work), diag_glink_late_init_work_fn); + link_info.glink_link_state_notif_cb = diag_glink_notify_cb; + link_info.transport = NULL; + link_info.edge = glink_info->edge; + glink_info->link_state_handle = NULL; + link_state_handle = glink_register_link_state_cb(&link_info, + (void *)glink_info); + if (IS_ERR_OR_NULL(link_state_handle)) { + pr_err("diag: In %s, unable to register for glink channel %s\n", + __func__, glink_info->name); + destroy_workqueue(glink_info->wq); + return; + } + glink_info->link_state_handle = link_state_handle; + glink_info->fwd_ctxt = NULL; + atomic_set(&glink_info->tx_intent_ready, 0); + atomic_set(&glink_info->opened, 0); + atomic_set(&glink_info->diag_state, 0); + DIAG_LOG(DIAG_DEBUG_PERIPHERALS, + "%s initialized fwd_ctxt: %pK hdl: %pK\n", + glink_info->name, glink_info->fwd_ctxt, + glink_info->link_state_handle); +} + +void diag_glink_invalidate(void *ctxt, struct diagfwd_info *fwd_ctxt) +{ + struct diag_glink_info *info = NULL; + + if (!ctxt || !fwd_ctxt) + return; + + info = (struct diag_glink_info *)ctxt; + info->fwd_ctxt = fwd_ctxt; +} + +int diag_glink_init(void) +{ + uint8_t peripheral; + struct diag_glink_info *glink_info = NULL; + + for (peripheral = 0; peripheral < NUM_PERIPHERALS; peripheral++) { + if (peripheral != PERIPHERAL_WDSP) + continue; + glink_info = &glink_cntl[peripheral]; + __diag_glink_init(glink_info); + diagfwd_cntl_register(TRANSPORT_GLINK, glink_info->peripheral, + (void *)glink_info, &glink_ops, + &(glink_info->fwd_ctxt)); + glink_info->inited = 1; + __diag_glink_init(&glink_data[peripheral]); + __diag_glink_init(&glink_cmd[peripheral]); + __diag_glink_init(&glink_dci[peripheral]); + __diag_glink_init(&glink_dci_cmd[peripheral]); + } + return 0; +} + +static void __diag_glink_exit(struct diag_glink_info *glink_info) +{ + if (!glink_info) + return; + + DIAG_LOG(DIAG_DEBUG_PERIPHERALS, "%s entering\n", + glink_info->name); + + diagfwd_deregister(glink_info->peripheral, glink_info->type, + (void *)glink_info); + glink_info->fwd_ctxt = NULL; + glink_info->hdl = NULL; + if (glink_info->wq) + destroy_workqueue(glink_info->wq); + + DIAG_LOG(DIAG_DEBUG_PERIPHERALS, "%s exiting\n", + glink_info->name); +} + +void diag_glink_early_exit(void) +{ + int peripheral = 0; + + for (peripheral = 0; peripheral < NUM_PERIPHERALS; peripheral++) { + if (peripheral != PERIPHERAL_WDSP) + continue; + __diag_glink_exit(&glink_cntl[peripheral]); + glink_unregister_link_state_cb(&glink_cntl[peripheral].hdl); + } +} + +void diag_glink_exit(void) +{ + int peripheral = 0; + + for (peripheral = 0; peripheral < NUM_PERIPHERALS; peripheral++) { + if (peripheral != PERIPHERAL_WDSP) + continue; + __diag_glink_exit(&glink_data[peripheral]); + __diag_glink_exit(&glink_cmd[peripheral]); + __diag_glink_exit(&glink_dci[peripheral]); + __diag_glink_exit(&glink_dci_cmd[peripheral]); + glink_unregister_link_state_cb(&glink_data[peripheral].hdl); + glink_unregister_link_state_cb(&glink_cmd[peripheral].hdl); + glink_unregister_link_state_cb(&glink_dci[peripheral].hdl); + glink_unregister_link_state_cb(&glink_dci_cmd[peripheral].hdl); + } +} diff -Nruw linux-4.4.115-fbx/drivers/char/diag./diagfwd_glink.h linux-4.4.115-fbx/drivers/char/diag/diagfwd_glink.h --- linux-4.4.115-fbx/drivers/char/diag./diagfwd_glink.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-4.4.115-fbx/drivers/char/diag/diagfwd_glink.h 2019-01-22 16:16:22.963241516 +0100 @@ -0,0 +1,57 @@ +/* Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef DIAGFWD_GLINK_H +#define DIAGFWD_GLINK_H + +#define DIAG_GLINK_NAME_SZ 24 +#define GLINK_DRAIN_BUF_SIZE 4096 + +struct diag_glink_info { + uint8_t peripheral; + uint8_t type; + uint8_t inited; + atomic_t opened; + atomic_t diag_state; + uint32_t fifo_size; + atomic_t tx_intent_ready; + void *hdl; + void *link_state_handle; + char edge[DIAG_GLINK_NAME_SZ]; + char name[DIAG_GLINK_NAME_SZ]; + struct mutex lock; + wait_queue_head_t read_wait_q; + wait_queue_head_t wait_q; + struct workqueue_struct *wq; + struct work_struct open_work; + struct work_struct close_work; + struct work_struct read_work; + struct work_struct connect_work; + struct work_struct remote_disconnect_work; + struct work_struct late_init_work; + struct diagfwd_info *fwd_ctxt; +}; + +extern struct diag_glink_info glink_data[NUM_PERIPHERALS]; +extern struct diag_glink_info glink_cntl[NUM_PERIPHERALS]; +extern struct diag_glink_info glink_cmd[NUM_PERIPHERALS]; +extern struct diag_glink_info glink_dci_cmd[NUM_PERIPHERALS]; +extern struct diag_glink_info glink_dci[NUM_PERIPHERALS]; + +int diag_glink_init_peripheral(uint8_t peripheral); +void diag_glink_exit(void); +int diag_glink_init(void); +void diag_glink_early_exit(void); +void diag_glink_invalidate(void *ctxt, struct diagfwd_info *fwd_ctxt); +int diag_glink_check_state(void *ctxt); + +#endif diff -Nruw linux-4.4.115-fbx/drivers/char/diag./diagfwd.h linux-4.4.115-fbx/drivers/char/diag/diagfwd.h --- linux-4.4.115-fbx/drivers/char/diag./diagfwd.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-4.4.115-fbx/drivers/char/diag/diagfwd.h 2019-01-22 16:16:22.959241480 +0100 @@ -0,0 +1,52 @@ +/* Copyright (c) 2008-2015, 2017 The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef DIAGFWD_H +#define DIAGFWD_H + +/* + * The context applies to Diag SMD data buffers. It is used to identify the + * buffer once these buffers are writtent to USB. + */ +#define SET_BUF_CTXT(p, d, n) \ + (((p & 0xFF) << 16) | ((d & 0xFF) << 8) | (n & 0xFF)) +#define SET_PD_CTXT(u) ((u & 0xFF) << 24) +#define GET_BUF_PERIPHERAL(p) ((p & 0xFF0000) >> 16) +#define GET_BUF_TYPE(d) ((d & 0x00FF00) >> 8) +#define GET_BUF_NUM(n) ((n & 0x0000FF)) +#define GET_PD_CTXT(u) ((u & 0xFF000000) >> 24) + +#define CHK_OVERFLOW(bufStart, start, end, length) \ + ((((bufStart) <= (start)) && ((end) - (start) >= (length))) ? 1 : 0) + +int diagfwd_init(void); +void diagfwd_exit(void); +void diag_process_hdlc_pkt(void *data, unsigned int len, int pid); +void diag_process_non_hdlc_pkt(unsigned char *data, int len, int pid); +int chk_config_get_id(void); +int chk_apps_only(void); +int chk_apps_master(void); +int chk_polling_response(void); +int diag_cmd_log_on_demand(unsigned char *src_buf, int src_len, + unsigned char *dest_buf, int dest_len); +int diag_cmd_get_mobile_id(unsigned char *src_buf, int src_len, + unsigned char *dest_buf, int dest_len); +int diag_check_common_cmd(struct diag_pkt_header_t *header); +void diag_update_userspace_clients(unsigned int type); +void diag_update_sleeping_process(int process_id, int data_type); +int diag_process_apps_pkt(unsigned char *buf, int len, int pid); +void diag_send_error_rsp(unsigned char *buf, int len, int pid); +void diag_update_pkt_buffer(unsigned char *buf, uint32_t len, int type); +int diag_process_stm_cmd(unsigned char *buf, unsigned char *dest_buf); +void diag_md_hdlc_reset_timer_func(unsigned long pid); +void diag_update_md_clients(unsigned int type); +#endif diff -Nruw linux-4.4.115-fbx/drivers/char/diag./diagfwd_peripheral.c linux-4.4.115-fbx/drivers/char/diag/diagfwd_peripheral.c --- linux-4.4.115-fbx/drivers/char/diag./diagfwd_peripheral.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-4.4.115-fbx/drivers/char/diag/diagfwd_peripheral.c 2019-10-29 09:26:23.453201319 +0100 @@ -0,0 +1,2074 @@ +/* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "diagchar.h" +#include "diagchar_hdlc.h" +#include "diagfwd_peripheral.h" +#include "diagfwd_cntl.h" +#include "diag_masks.h" +#include "diag_dci.h" +#include "diagfwd.h" +#include "diagfwd_smd.h" +#include "diagfwd_socket.h" +#include "diag_mux.h" +#include "diag_ipc_logging.h" +#include "diagfwd_glink.h" +#include "diag_memorydevice.h" + +struct data_header { + uint8_t control_char; + uint8_t version; + uint16_t length; +}; + +static struct diagfwd_info *early_init_info[NUM_TRANSPORT]; + +static void diagfwd_queue_read(struct diagfwd_info *fwd_info); +static void diagfwd_buffers_exit(struct diagfwd_info *fwd_info); +static void diagfwd_cntl_open(struct diagfwd_info *fwd_info); +static void diagfwd_cntl_close(struct diagfwd_info *fwd_info); +static void diagfwd_dci_open(struct diagfwd_info *fwd_info); +static void diagfwd_dci_close(struct diagfwd_info *fwd_info); +static void diagfwd_data_read_untag_done(struct diagfwd_info *fwd_info, + unsigned char *buf, int len); +static void diagfwd_data_read_done(struct diagfwd_info *fwd_info, + unsigned char *buf, int len); +static void diagfwd_cntl_read_done(struct diagfwd_info *fwd_info, + unsigned char *buf, int len); +static void diagfwd_dci_read_done(struct diagfwd_info *fwd_info, + unsigned char *buf, int len); +static void diagfwd_write_buffers_init(struct diagfwd_info *fwd_info); +static void diagfwd_write_buffers_exit(struct diagfwd_info *fwd_info); +struct diagfwd_info peripheral_info[NUM_TYPES][NUM_PERIPHERALS]; + +static struct diag_channel_ops data_ch_ops = { + .open = NULL, + .close = NULL, + .read_done = diagfwd_data_read_untag_done +}; + +static struct diag_channel_ops cntl_ch_ops = { + .open = diagfwd_cntl_open, + .close = diagfwd_cntl_close, + .read_done = diagfwd_cntl_read_done +}; + +static struct diag_channel_ops dci_ch_ops = { + .open = diagfwd_dci_open, + .close = diagfwd_dci_close, + .read_done = diagfwd_dci_read_done +}; + +static void diagfwd_cntl_open(struct diagfwd_info *fwd_info) +{ + if (!fwd_info) + return; + diag_cntl_channel_open(fwd_info); +} + +static void diagfwd_cntl_close(struct diagfwd_info *fwd_info) +{ + if (!fwd_info) + return; + diag_cntl_channel_close(fwd_info); +} + +static void diagfwd_dci_open(struct diagfwd_info *fwd_info) +{ + if (!fwd_info) + return; + + diag_dci_notify_client(PERIPHERAL_MASK(fwd_info->peripheral), + DIAG_STATUS_OPEN, DCI_LOCAL_PROC); +} + +static void diagfwd_dci_close(struct diagfwd_info *fwd_info) +{ + if (!fwd_info) + return; + + diag_dci_notify_client(PERIPHERAL_MASK(fwd_info->peripheral), + DIAG_STATUS_CLOSED, DCI_LOCAL_PROC); +} + +static int diag_add_hdlc_encoding(unsigned char *dest_buf, int *dest_len, + unsigned char *buf, int len) +{ + struct diag_send_desc_type send = { NULL, NULL, DIAG_STATE_START, 0 }; + struct diag_hdlc_dest_type enc = { NULL, NULL, 0 }; + struct data_header *header; + int header_size = sizeof(struct data_header); + uint8_t *end_control_char = NULL; + uint8_t *payload = NULL; + uint8_t *temp_buf = NULL; + uint8_t *temp_encode_buf = NULL; + int src_pkt_len; + int encoded_pkt_length; + int max_size; + int total_processed = 0; + int bytes_remaining; + int err = 0; + uint8_t loop_count = 0; + + if (!dest_buf || !dest_len || !buf) + return -EIO; + + temp_buf = buf; + temp_encode_buf = dest_buf; + bytes_remaining = *dest_len; + + while (total_processed < len) { + loop_count++; + header = (struct data_header *)temp_buf; + /* Perform initial error checking */ + if (header->control_char != CONTROL_CHAR || + header->version != 1) { + err = -EINVAL; + break; + } + + if (header->length >= bytes_remaining) + break; + + payload = temp_buf + header_size; + end_control_char = payload + header->length; + if (*end_control_char != CONTROL_CHAR) { + err = -EINVAL; + break; + } + + max_size = 2 * header->length + 3; + if (bytes_remaining < max_size) { + err = -EINVAL; + break; + } + + /* Prepare for encoding the data */ + send.state = DIAG_STATE_START; + send.pkt = payload; + send.last = (void *)(payload + header->length - 1); + send.terminate = 1; + + enc.dest = temp_encode_buf; + enc.dest_last = (void *)(temp_encode_buf + max_size); + enc.crc = 0; + diag_hdlc_encode(&send, &enc); + + /* Prepare for next packet */ + src_pkt_len = (header_size + header->length + 1); + total_processed += src_pkt_len; + temp_buf += src_pkt_len; + + encoded_pkt_length = (uint8_t *)enc.dest - temp_encode_buf; + bytes_remaining -= encoded_pkt_length; + temp_encode_buf = enc.dest; + } + + *dest_len = (int)(temp_encode_buf - dest_buf); + + return err; +} + +static int check_bufsize_for_encoding(struct diagfwd_buf_t *buf, uint32_t len) +{ + int i, ctx = 0; + uint32_t max_size = 0; + unsigned char *temp_buf = NULL; + struct diag_md_info *ch = NULL; + + if (!buf || len == 0) + return -EINVAL; + + max_size = (2 * len) + 3; + if (max_size > PERIPHERAL_BUF_SZ) { + if (max_size > MAX_PERIPHERAL_HDLC_BUF_SZ) { + pr_err("diag: In %s, max_size is going beyond limit %d\n", + __func__, max_size); + max_size = MAX_PERIPHERAL_HDLC_BUF_SZ; + } + + if (buf->len < max_size) { + if (driver->logging_mode == DIAG_MEMORY_DEVICE_MODE) { + ch = &diag_md[DIAG_LOCAL_PROC]; + for (i = 0; ch != NULL && + i < ch->num_tbl_entries; i++) { + if (ch->tbl[i].buf == buf->data) { + ctx = ch->tbl[i].ctx; + ch->tbl[i].buf = NULL; + ch->tbl[i].len = 0; + ch->tbl[i].ctx = 0; + DIAG_LOG(DIAG_DEBUG_PERIPHERALS, + "Flushed mdlog table entries before reallocating data buffer, p:%d, t:%d\n", + GET_BUF_PERIPHERAL(ctx), + GET_BUF_TYPE(ctx)); + break; + } + } + } + temp_buf = krealloc(buf->data, max_size + + APF_DIAG_PADDING, + GFP_KERNEL); + if (!temp_buf) + return -ENOMEM; + DIAG_LOG(DIAG_DEBUG_PERIPHERALS, + "Reallocated data buffer: %pK with size: %d\n", + temp_buf, max_size); + buf->data = temp_buf; + buf->len = max_size; + } + } + + return buf->len; +} + +int diag_md_get_peripheral(int ctxt) +{ + int peripheral; + + if (driver->num_pd_session) { + peripheral = GET_PD_CTXT(ctxt); + switch (peripheral) { + case UPD_WLAN: + if (!driver->pd_logging_mode[0]) + peripheral = PERIPHERAL_MODEM; + break; + case UPD_AUDIO: + if (!driver->pd_logging_mode[1]) + peripheral = PERIPHERAL_LPASS; + break; + case UPD_SENSORS: + if (!driver->pd_logging_mode[2]) + peripheral = PERIPHERAL_LPASS; + break; + case DIAG_ID_MPSS: + case DIAG_ID_LPASS: + case DIAG_ID_CDSP: + default: + peripheral = + GET_BUF_PERIPHERAL(ctxt); + if (peripheral > NUM_PERIPHERALS) + peripheral = -EINVAL; + break; + } + } else { + /* Account for Apps data as well */ + peripheral = GET_BUF_PERIPHERAL(ctxt); + if (peripheral > NUM_PERIPHERALS) + peripheral = -EINVAL; + } + + return peripheral; +} + +static void diagfwd_data_process_done(struct diagfwd_info *fwd_info, + struct diagfwd_buf_t *buf, int len) +{ + int err = 0; + int write_len = 0, peripheral = 0; + unsigned char *write_buf = NULL; + struct diag_md_session_t *session_info = NULL; + uint8_t hdlc_disabled = 0; + + if (!fwd_info || !buf || len <= 0) { + diag_ws_release(); + return; + } + + switch (fwd_info->type) { + case TYPE_DATA: + case TYPE_CMD: + break; + default: + pr_err_ratelimited("diag: In %s, invalid type %d for peripheral %d\n", + __func__, fwd_info->type, + fwd_info->peripheral); + diag_ws_release(); + return; + } + + mutex_lock(&driver->hdlc_disable_mutex); + mutex_lock(&fwd_info->data_mutex); + + peripheral = diag_md_get_peripheral(buf->ctxt); + if (peripheral < 0) { + pr_err("diag:%s:%d invalid peripheral = %d\n", + __func__, __LINE__, peripheral); + mutex_unlock(&fwd_info->data_mutex); + mutex_unlock(&driver->hdlc_disable_mutex); + diag_ws_release(); + return; + } + mutex_lock(&driver->md_session_lock); + session_info = diag_md_session_get_peripheral(peripheral); + if (session_info) + hdlc_disabled = session_info->hdlc_disabled; + else + hdlc_disabled = driver->hdlc_disabled; + mutex_unlock(&driver->md_session_lock); + if (hdlc_disabled) { + /* The data is raw and and on APPS side HDLC is disabled */ + if (!buf) { + pr_err("diag: In %s, no match for non encode buffer %pK, peripheral %d, type: %d\n", + __func__, buf, fwd_info->peripheral, + fwd_info->type); + goto end; + } + if (len > PERIPHERAL_BUF_SZ) { + pr_err("diag: In %s, Incoming buffer too large %d, peripheral %d, type: %d\n", + __func__, len, fwd_info->peripheral, + fwd_info->type); + goto end; + } + write_len = len; + if (write_len <= 0) + goto end; + write_buf = buf->data_raw; + } else { + if (!buf) { + pr_err("diag: In %s, no match for non encode buffer %pK, peripheral %d, type: %d\n", + __func__, buf, fwd_info->peripheral, + fwd_info->type); + goto end; + } + + write_len = check_bufsize_for_encoding(buf, len); + if (write_len <= 0) { + pr_err("diag: error in checking buf for encoding\n"); + goto end; + } + write_buf = buf->data; + err = diag_add_hdlc_encoding(write_buf, &write_len, + buf->data_raw, len); + if (err) { + pr_err("diag: error in adding hdlc encoding\n"); + goto end; + } + } + mutex_unlock(&fwd_info->data_mutex); + mutex_unlock(&driver->hdlc_disable_mutex); + + if (write_len > 0) { + err = diag_mux_write(DIAG_LOCAL_PROC, write_buf, write_len, + buf->ctxt); + if (err) { + pr_err_ratelimited("diag: In %s, unable to write to mux error: %d\n", + __func__, err); + goto end_write; + } + } + + diagfwd_queue_read(fwd_info); + return; + +end: + mutex_unlock(&fwd_info->data_mutex); + mutex_unlock(&driver->hdlc_disable_mutex); +end_write: + diag_ws_release(); + if (buf) { + DIAG_LOG(DIAG_DEBUG_PERIPHERALS, + "Marking buffer as free p: %d, t: %d, buf_num: %d\n", + fwd_info->peripheral, fwd_info->type, + GET_BUF_NUM(buf->ctxt)); + diagfwd_write_done(fwd_info->peripheral, fwd_info->type, + GET_BUF_NUM(buf->ctxt)); + } + diagfwd_queue_read(fwd_info); +} + +static void diagfwd_data_read_untag_done(struct diagfwd_info *fwd_info, + unsigned char *buf, int len) +{ + int len_cpd = 0; + int len_upd_1 = 0, len_upd_2 = 0; + int ctxt_cpd = 0; + int ctxt_upd_1 = 0, ctxt_upd_2 = 0; + int buf_len = 0, processed = 0; + unsigned char *temp_buf_main = NULL; + unsigned char *temp_buf_cpd = NULL; + unsigned char *temp_buf_upd_1 = NULL; + unsigned char *temp_buf_upd_2 = NULL; + struct diagfwd_buf_t *temp_ptr_upd = NULL; + struct diagfwd_buf_t *temp_ptr_cpd = NULL; + int flag_buf_1 = 0, flag_buf_2 = 0; + uint8_t peripheral; + + if (!fwd_info || !buf || len <= 0) { + diag_ws_release(); + return; + } + + switch (fwd_info->type) { + case TYPE_DATA: + case TYPE_CMD: + break; + default: + pr_err_ratelimited("diag: In %s, invalid type %d for peripheral %d\n", + __func__, fwd_info->type, + fwd_info->peripheral); + diag_ws_release(); + return; + } + peripheral = fwd_info->peripheral; + + if (driver->feature[peripheral].encode_hdlc && + driver->feature[peripheral].untag_header && + driver->peripheral_untag[peripheral]) { + temp_buf_cpd = buf; + temp_buf_main = buf; + if (fwd_info->buf_1 && + fwd_info->buf_1->data_raw == buf) { + flag_buf_1 = 1; + temp_ptr_cpd = fwd_info->buf_1; + if (fwd_info->type == TYPE_DATA) { + temp_buf_upd_1 = + fwd_info->buf_upd_1_a->data_raw; + if (peripheral == + PERIPHERAL_LPASS) + temp_buf_upd_2 = + fwd_info->buf_upd_2_a->data_raw; + } + } else if (fwd_info->buf_2 && + fwd_info->buf_2->data_raw == buf) { + flag_buf_2 = 1; + temp_ptr_cpd = fwd_info->buf_2; + if (fwd_info->type == TYPE_DATA) { + temp_buf_upd_1 = + fwd_info->buf_upd_1_b->data_raw; + if (peripheral == + PERIPHERAL_LPASS) + temp_buf_upd_2 = + fwd_info->buf_upd_2_b->data_raw; + } + } else { + pr_err("diag: In %s, no match for buffer %pK, peripheral %d, type: %d\n", + __func__, buf, peripheral, + fwd_info->type); + goto end; + } + while (processed < len) { + buf_len = + *(uint16_t *) (temp_buf_main + 2); + switch ((*temp_buf_main)) { + case DIAG_ID_MPSS: + ctxt_cpd = DIAG_ID_MPSS; + len_cpd += buf_len; + if (temp_buf_cpd) { + memcpy(temp_buf_cpd, + (temp_buf_main + 4), buf_len); + temp_buf_cpd += buf_len; + } + break; + case DIAG_ID_WLAN: + ctxt_upd_1 = UPD_WLAN; + len_upd_1 += buf_len; + if (temp_buf_upd_1) { + memcpy(temp_buf_upd_1, + (temp_buf_main + 4), buf_len); + temp_buf_upd_1 += buf_len; + } + break; + case DIAG_ID_LPASS: + ctxt_cpd = DIAG_ID_LPASS; + len_cpd += buf_len; + if (temp_buf_cpd) { + memcpy(temp_buf_cpd, + (temp_buf_main + 4), buf_len); + temp_buf_cpd += buf_len; + } + break; + case DIAG_ID_AUDIO: + ctxt_upd_1 = UPD_AUDIO; + len_upd_1 += buf_len; + if (temp_buf_upd_1) { + memcpy(temp_buf_upd_1, + (temp_buf_main + 4), buf_len); + temp_buf_upd_1 += buf_len; + } + break; + case DIAG_ID_SENSORS: + ctxt_upd_2 = UPD_SENSORS; + len_upd_2 += buf_len; + if (temp_buf_upd_2) { + memcpy(temp_buf_upd_2, + (temp_buf_main + 4), buf_len); + temp_buf_upd_2 += buf_len; + } + break; + case DIAG_ID_CDSP: + ctxt_cpd = DIAG_ID_CDSP; + len_cpd += buf_len; + if (temp_buf_cpd) { + memcpy(temp_buf_cpd, + (temp_buf_main + 4), buf_len); + temp_buf_cpd += buf_len; + } + break; + default: + goto end; + } + len = len - 4; + temp_buf_main += (buf_len + 4); + processed += buf_len; + } + + if (flag_buf_1) { + fwd_info->cpd_len_1 = len_cpd; + if (fwd_info->type == TYPE_DATA) + fwd_info->upd_len_1_a = len_upd_1; + if (peripheral == PERIPHERAL_LPASS && + fwd_info->type == TYPE_DATA) + fwd_info->upd_len_2_a = len_upd_2; + } else if (flag_buf_2) { + fwd_info->cpd_len_2 = len_cpd; + if (fwd_info->type == TYPE_DATA) + fwd_info->upd_len_1_b = len_upd_1; + if (peripheral == PERIPHERAL_LPASS && + fwd_info->type == TYPE_DATA) + fwd_info->upd_len_2_b = len_upd_2; + } + + if (peripheral == PERIPHERAL_LPASS && + fwd_info->type == TYPE_DATA && len_upd_2) { + if (flag_buf_1) + temp_ptr_upd = fwd_info->buf_upd_2_a; + else + temp_ptr_upd = fwd_info->buf_upd_2_b; + temp_ptr_upd->ctxt &= 0x00FFFFFF; + temp_ptr_upd->ctxt |= + (SET_PD_CTXT(ctxt_upd_2)); + atomic_set(&temp_ptr_upd->in_busy, 1); + diagfwd_data_process_done(fwd_info, + temp_ptr_upd, len_upd_2); + } else { + if (flag_buf_1) + fwd_info->upd_len_2_a = 0; + if (flag_buf_2) + fwd_info->upd_len_2_b = 0; + } + if (fwd_info->type == TYPE_DATA && len_upd_1) { + if (flag_buf_1) + temp_ptr_upd = fwd_info->buf_upd_1_a; + else + temp_ptr_upd = fwd_info->buf_upd_1_b; + temp_ptr_upd->ctxt &= 0x00FFFFFF; + temp_ptr_upd->ctxt |= + (SET_PD_CTXT(ctxt_upd_1)); + atomic_set(&temp_ptr_upd->in_busy, 1); + diagfwd_data_process_done(fwd_info, + temp_ptr_upd, len_upd_1); + } else { + if (flag_buf_1) + fwd_info->upd_len_1_a = 0; + if (flag_buf_2) + fwd_info->upd_len_1_b = 0; + } + if (len_cpd) { + temp_ptr_cpd->ctxt &= 0x00FFFFFF; + temp_ptr_cpd->ctxt |= + (SET_PD_CTXT(ctxt_cpd)); + diagfwd_data_process_done(fwd_info, + temp_ptr_cpd, len_cpd); + } else { + if (flag_buf_1) + fwd_info->cpd_len_1 = 0; + if (flag_buf_2) + fwd_info->cpd_len_2 = 0; + } + return; + } else { + diagfwd_data_read_done(fwd_info, buf, len); + return; + } +end: + diag_ws_release(); + if (temp_ptr_cpd) { + DIAG_LOG(DIAG_DEBUG_PERIPHERALS, + "Marking buffer as free p: %d, t: %d, buf_num: %d\n", + fwd_info->peripheral, fwd_info->type, + GET_BUF_NUM(temp_ptr_cpd->ctxt)); + diagfwd_write_done(fwd_info->peripheral, fwd_info->type, + GET_BUF_NUM(temp_ptr_cpd->ctxt)); + } + diagfwd_queue_read(fwd_info); +} + +static void diagfwd_data_read_done(struct diagfwd_info *fwd_info, + unsigned char *buf, int len) +{ + int err = 0; + int write_len = 0; + unsigned char *write_buf = NULL; + struct diagfwd_buf_t *temp_buf = NULL; + struct diag_md_session_t *session_info = NULL; + uint8_t hdlc_disabled = 0; + + if (!fwd_info || !buf || len <= 0) { + diag_ws_release(); + return; + } + + switch (fwd_info->type) { + case TYPE_DATA: + case TYPE_CMD: + break; + default: + pr_err_ratelimited("diag: In %s, invalid type %d for peripheral %d\n", + __func__, fwd_info->type, + fwd_info->peripheral); + diag_ws_release(); + return; + } + + mutex_lock(&driver->hdlc_disable_mutex); + mutex_lock(&fwd_info->data_mutex); + mutex_lock(&driver->md_session_lock); + session_info = diag_md_session_get_peripheral(fwd_info->peripheral); + if (session_info) + hdlc_disabled = session_info->hdlc_disabled; + else + hdlc_disabled = driver->hdlc_disabled; + mutex_unlock(&driver->md_session_lock); + if (!driver->feature[fwd_info->peripheral].encode_hdlc) { + if (fwd_info->buf_1 && fwd_info->buf_1->data == buf) { + temp_buf = fwd_info->buf_1; + write_buf = fwd_info->buf_1->data; + } else if (fwd_info->buf_2 && fwd_info->buf_2->data == buf) { + temp_buf = fwd_info->buf_2; + write_buf = fwd_info->buf_2->data; + } else { + pr_err("diag: In %s, no match for buffer %pK, peripheral %d, type: %d\n", + __func__, buf, fwd_info->peripheral, + fwd_info->type); + goto end; + } + write_len = len; + } else if (hdlc_disabled) { + /* The data is raw and and on APPS side HDLC is disabled */ + if (fwd_info->buf_1 && fwd_info->buf_1->data_raw == buf) { + temp_buf = fwd_info->buf_1; + } else if (fwd_info->buf_2 && + fwd_info->buf_2->data_raw == buf) { + temp_buf = fwd_info->buf_2; + } else { + pr_err("diag: In %s, no match for non encode buffer %pK, peripheral %d, type: %d\n", + __func__, buf, fwd_info->peripheral, + fwd_info->type); + goto end; + } + if (len > PERIPHERAL_BUF_SZ) { + pr_err("diag: In %s, Incoming buffer too large %d, peripheral %d, type: %d\n", + __func__, len, fwd_info->peripheral, + fwd_info->type); + goto end; + } + write_len = len; + write_buf = buf; + } else { + if (fwd_info->buf_1 && fwd_info->buf_1->data_raw == buf) { + temp_buf = fwd_info->buf_1; + } else if (fwd_info->buf_2 && + fwd_info->buf_2->data_raw == buf) { + temp_buf = fwd_info->buf_2; + } else { + pr_err("diag: In %s, no match for non encode buffer %pK, peripheral %d, type: %d\n", + __func__, buf, fwd_info->peripheral, + fwd_info->type); + goto end; + } + write_len = check_bufsize_for_encoding(temp_buf, len); + if (write_len <= 0) { + pr_err("diag: error in checking buf for encoding\n"); + goto end; + } + write_buf = temp_buf->data; + err = diag_add_hdlc_encoding(write_buf, &write_len, buf, len); + if (err) { + pr_err("diag: error in adding hdlc encoding\n"); + goto end; + } + } + + mutex_unlock(&fwd_info->data_mutex); + mutex_unlock(&driver->hdlc_disable_mutex); + + if (write_len > 0) { + err = diag_mux_write(DIAG_LOCAL_PROC, write_buf, write_len, + temp_buf->ctxt); + if (err) { + pr_err_ratelimited("diag: In %s, unable to write to mux error: %d\n", + __func__, err); + goto end_write; + } + } + diagfwd_queue_read(fwd_info); + return; + +end: + mutex_unlock(&fwd_info->data_mutex); + mutex_unlock(&driver->hdlc_disable_mutex); +end_write: + diag_ws_release(); + if (temp_buf) { + DIAG_LOG(DIAG_DEBUG_PERIPHERALS, + "Marking buffer as free p: %d, t: %d, buf_num: %d\n", + fwd_info->peripheral, fwd_info->type, + GET_BUF_NUM(temp_buf->ctxt)); + diagfwd_write_done(fwd_info->peripheral, fwd_info->type, + GET_BUF_NUM(temp_buf->ctxt)); + } + diagfwd_queue_read(fwd_info); + return; +} + +static void diagfwd_cntl_read_done(struct diagfwd_info *fwd_info, + unsigned char *buf, int len) +{ + if (!fwd_info) { + diag_ws_release(); + return; + } + + if (fwd_info->type != TYPE_CNTL) { + pr_err("diag: In %s, invalid type %d for peripheral %d\n", + __func__, fwd_info->type, fwd_info->peripheral); + diag_ws_release(); + return; + } + + diag_ws_on_read(DIAG_WS_MUX, len); + diag_cntl_process_read_data(fwd_info, buf, len); + /* + * Control packets are not consumed by the clients. Mimic + * consumption by setting and clearing the wakeup source copy_count + * explicitly. + */ + diag_ws_on_copy_fail(DIAG_WS_MUX); + /* Reset the buffer in_busy value after processing the data */ + if (fwd_info->buf_1) + atomic_set(&fwd_info->buf_1->in_busy, 0); + + diagfwd_queue_read(fwd_info); + diagfwd_queue_read(&peripheral_info[TYPE_DATA][fwd_info->peripheral]); + diagfwd_queue_read(&peripheral_info[TYPE_CMD][fwd_info->peripheral]); +} + +static void diagfwd_dci_read_done(struct diagfwd_info *fwd_info, + unsigned char *buf, int len) +{ + if (!fwd_info) + return; + + switch (fwd_info->type) { + case TYPE_DCI: + case TYPE_DCI_CMD: + break; + default: + pr_err("diag: In %s, invalid type %d for peripheral %d\n", + __func__, fwd_info->type, fwd_info->peripheral); + return; + } + + diag_dci_process_peripheral_data(fwd_info, (void *)buf, len); + /* Reset the buffer in_busy value after processing the data */ + if (fwd_info->buf_1) + atomic_set(&fwd_info->buf_1->in_busy, 0); + + diagfwd_queue_read(fwd_info); +} + +static void diagfwd_reset_buffers(struct diagfwd_info *fwd_info, + unsigned char *buf) +{ + if (!fwd_info || !buf) + return; + + if (!driver->feature[fwd_info->peripheral].encode_hdlc) { + if (fwd_info->buf_1 && fwd_info->buf_1->data == buf) + atomic_set(&fwd_info->buf_1->in_busy, 0); + else if (fwd_info->buf_2 && fwd_info->buf_2->data == buf) + atomic_set(&fwd_info->buf_2->in_busy, 0); + } else { + if (fwd_info->buf_1 && fwd_info->buf_1->data_raw == buf) + atomic_set(&fwd_info->buf_1->in_busy, 0); + else if (fwd_info->buf_2 && fwd_info->buf_2->data_raw == buf) + atomic_set(&fwd_info->buf_2->in_busy, 0); + } + if (fwd_info->buf_1 && !atomic_read(&(fwd_info->buf_1->in_busy))) { + DIAG_LOG(DIAG_DEBUG_PERIPHERALS, + "Buffer 1 for core PD is marked free, p: %d, t: %d\n", + fwd_info->peripheral, fwd_info->type); + } + if (fwd_info->buf_2 && !atomic_read(&(fwd_info->buf_2->in_busy))) { + DIAG_LOG(DIAG_DEBUG_PERIPHERALS, + "Buffer 2 for core PD is marked free, p: %d, t: %d\n", + fwd_info->peripheral, fwd_info->type); + } +} + +int diagfwd_peripheral_init(void) +{ + uint8_t peripheral; + uint8_t transport; + uint8_t type; + struct diagfwd_info *fwd_info = NULL; + + for (transport = 0; transport < NUM_TRANSPORT; transport++) { + early_init_info[transport] = kzalloc( + sizeof(struct diagfwd_info) * NUM_PERIPHERALS, + GFP_KERNEL); + if (!early_init_info[transport]) + return -ENOMEM; + kmemleak_not_leak(early_init_info[transport]); + } + + for (peripheral = 0; peripheral < NUM_PERIPHERALS; peripheral++) { + for (transport = 0; transport < NUM_TRANSPORT; transport++) { + fwd_info = &early_init_info[transport][peripheral]; + fwd_info->peripheral = peripheral; + fwd_info->type = TYPE_CNTL; + fwd_info->transport = transport; + fwd_info->ctxt = NULL; + fwd_info->p_ops = NULL; + fwd_info->ch_open = 0; + fwd_info->inited = 1; + fwd_info->read_bytes = 0; + fwd_info->write_bytes = 0; + fwd_info->cpd_len_1 = 0; + fwd_info->cpd_len_2 = 0; + fwd_info->upd_len_1_a = 0; + fwd_info->upd_len_1_b = 0; + fwd_info->upd_len_2_a = 0; + fwd_info->upd_len_2_a = 0; + mutex_init(&fwd_info->buf_mutex); + mutex_init(&fwd_info->data_mutex); + spin_lock_init(&fwd_info->write_buf_lock); + } + } + + for (peripheral = 0; peripheral < NUM_PERIPHERALS; peripheral++) { + for (type = 0; type < NUM_TYPES; type++) { + fwd_info = &peripheral_info[type][peripheral]; + fwd_info->peripheral = peripheral; + fwd_info->type = type; + fwd_info->ctxt = NULL; + fwd_info->p_ops = NULL; + fwd_info->ch_open = 0; + fwd_info->read_bytes = 0; + fwd_info->write_bytes = 0; + fwd_info->cpd_len_1 = 0; + fwd_info->cpd_len_2 = 0; + fwd_info->upd_len_1_a = 0; + fwd_info->upd_len_1_b = 0; + fwd_info->upd_len_2_a = 0; + fwd_info->upd_len_2_a = 0; + spin_lock_init(&fwd_info->write_buf_lock); + mutex_init(&fwd_info->buf_mutex); + mutex_init(&fwd_info->data_mutex); + /* + * This state shouldn't be set for Control channels + * during initialization. This is set when the feature + * mask is received for the first time. + */ + if (type != TYPE_CNTL) + fwd_info->inited = 1; + } + driver->diagfwd_data[peripheral] = + &peripheral_info[TYPE_DATA][peripheral]; + driver->diagfwd_cntl[peripheral] = + &peripheral_info[TYPE_CNTL][peripheral]; + driver->diagfwd_dci[peripheral] = + &peripheral_info[TYPE_DCI][peripheral]; + driver->diagfwd_cmd[peripheral] = + &peripheral_info[TYPE_CMD][peripheral]; + driver->diagfwd_dci_cmd[peripheral] = + &peripheral_info[TYPE_DCI_CMD][peripheral]; + } + + diag_smd_init(); + if (driver->supports_sockets) + diag_socket_init(); + diag_glink_init(); + + return 0; +} + +void diagfwd_peripheral_exit(void) +{ + uint8_t peripheral; + uint8_t type; + struct diagfwd_info *fwd_info = NULL; + int transport = 0; + + diag_smd_exit(); + diag_socket_exit(); + + for (peripheral = 0; peripheral < NUM_PERIPHERALS; peripheral++) { + for (type = 0; type < NUM_TYPES; type++) { + fwd_info = &peripheral_info[type][peripheral]; + fwd_info->ctxt = NULL; + fwd_info->p_ops = NULL; + fwd_info->ch_open = 0; + diagfwd_buffers_exit(fwd_info); + } + } + + for (peripheral = 0; peripheral < NUM_PERIPHERALS; peripheral++) { + driver->diagfwd_data[peripheral] = NULL; + driver->diagfwd_cntl[peripheral] = NULL; + driver->diagfwd_dci[peripheral] = NULL; + driver->diagfwd_cmd[peripheral] = NULL; + driver->diagfwd_dci_cmd[peripheral] = NULL; + } + + for (transport = 0; transport < NUM_TRANSPORT; transport++) { + kfree(early_init_info[transport]); + early_init_info[transport] = NULL; + } +} + +int diagfwd_cntl_register(uint8_t transport, uint8_t peripheral, void *ctxt, + struct diag_peripheral_ops *ops, + struct diagfwd_info **fwd_ctxt) +{ + struct diagfwd_info *fwd_info = NULL; + + if (!ctxt || !ops) + return -EIO; + + if (transport >= NUM_TRANSPORT || peripheral >= NUM_PERIPHERALS) + return -EINVAL; + + fwd_info = &early_init_info[transport][peripheral]; + *fwd_ctxt = &early_init_info[transport][peripheral]; + fwd_info->ctxt = ctxt; + fwd_info->p_ops = ops; + fwd_info->c_ops = &cntl_ch_ops; + + return 0; +} + +int diagfwd_register(uint8_t transport, uint8_t peripheral, uint8_t type, + void *ctxt, struct diag_peripheral_ops *ops, + struct diagfwd_info **fwd_ctxt) +{ + struct diagfwd_info *fwd_info = NULL; + + if (peripheral >= NUM_PERIPHERALS || type >= NUM_TYPES || + !ctxt || !ops || transport >= NUM_TRANSPORT) { + pr_err("diag: In %s, returning error\n", __func__); + return -EIO; + } + + fwd_info = &peripheral_info[type][peripheral]; + *fwd_ctxt = &peripheral_info[type][peripheral]; + fwd_info->ctxt = ctxt; + fwd_info->p_ops = ops; + fwd_info->transport = transport; + fwd_info->ch_open = 0; + + switch (type) { + case TYPE_DATA: + case TYPE_CMD: + fwd_info->c_ops = &data_ch_ops; + break; + case TYPE_DCI: + case TYPE_DCI_CMD: + fwd_info->c_ops = &dci_ch_ops; + break; + default: + pr_err("diag: In %s, invalid type: %d\n", __func__, type); + return -EINVAL; + } + + if (atomic_read(&fwd_info->opened) && + fwd_info->p_ops && fwd_info->p_ops->open) { + /* + * The registration can happen late, like in the case of + * sockets. fwd_info->opened reflects diag_state. Propogate the + * state to the peipherals. + */ + fwd_info->p_ops->open(fwd_info->ctxt); + } + + return 0; +} + +void diagfwd_deregister(uint8_t peripheral, uint8_t type, void *ctxt) +{ + struct diagfwd_info *fwd_info = NULL; + + if (peripheral >= NUM_PERIPHERALS || type >= NUM_TYPES || !ctxt) + return; + + fwd_info = &peripheral_info[type][peripheral]; + if (fwd_info->ctxt != ctxt) { + pr_err("diag: In %s, unable to find a match for p: %d t: %d\n", + __func__, peripheral, type); + return; + } + fwd_info->ctxt = NULL; + fwd_info->p_ops = NULL; + fwd_info->ch_open = 0; + diagfwd_buffers_exit(fwd_info); + + switch (type) { + case TYPE_DATA: + driver->diagfwd_data[peripheral] = NULL; + break; + case TYPE_CNTL: + driver->diagfwd_cntl[peripheral] = NULL; + break; + case TYPE_DCI: + driver->diagfwd_dci[peripheral] = NULL; + break; + case TYPE_CMD: + driver->diagfwd_cmd[peripheral] = NULL; + break; + case TYPE_DCI_CMD: + driver->diagfwd_dci_cmd[peripheral] = NULL; + break; + } +} + +void diagfwd_close_transport(uint8_t transport, uint8_t peripheral) +{ + struct diagfwd_info *fwd_info = NULL; + struct diagfwd_info *dest_info = NULL; + int (*init_fn)(uint8_t) = NULL; + void (*invalidate_fn)(void *, struct diagfwd_info *) = NULL; + int (*check_channel_state)(void *) = NULL; + uint8_t transport_open = 0; + int i = 0; + + if (peripheral >= NUM_PERIPHERALS) + return; + + switch (transport) { + case TRANSPORT_SMD: + transport_open = TRANSPORT_SOCKET; + init_fn = diag_socket_init_peripheral; + invalidate_fn = diag_socket_invalidate; + check_channel_state = diag_socket_check_state; + break; + case TRANSPORT_SOCKET: + if (peripheral == PERIPHERAL_WDSP) { + transport_open = TRANSPORT_GLINK; + init_fn = diag_glink_init_peripheral; + invalidate_fn = diag_glink_invalidate; + check_channel_state = diag_glink_check_state; + } else { + transport_open = TRANSPORT_SMD; + init_fn = diag_smd_init_peripheral; + invalidate_fn = diag_smd_invalidate; + check_channel_state = diag_smd_check_state; + } + break; + default: + return; + } + + mutex_lock(&driver->diagfwd_channel_mutex[peripheral]); + fwd_info = &early_init_info[transport][peripheral]; + if (fwd_info->p_ops && fwd_info->p_ops->close) + fwd_info->p_ops->close(fwd_info->ctxt); + fwd_info = &early_init_info[transport_open][peripheral]; + dest_info = &peripheral_info[TYPE_CNTL][peripheral]; + dest_info->inited = 1; + dest_info->ctxt = fwd_info->ctxt; + dest_info->p_ops = fwd_info->p_ops; + dest_info->c_ops = fwd_info->c_ops; + dest_info->ch_open = fwd_info->ch_open; + dest_info->read_bytes = fwd_info->read_bytes; + dest_info->write_bytes = fwd_info->write_bytes; + dest_info->inited = fwd_info->inited; + dest_info->buf_1 = fwd_info->buf_1; + dest_info->buf_2 = fwd_info->buf_2; + dest_info->transport = fwd_info->transport; + invalidate_fn(dest_info->ctxt, dest_info); + for (i = 0; i < NUM_WRITE_BUFFERS; i++) + dest_info->buf_ptr[i] = fwd_info->buf_ptr[i]; + if (!check_channel_state(dest_info->ctxt)) + diagfwd_late_open(dest_info); + diagfwd_cntl_open(dest_info); + init_fn(peripheral); + mutex_unlock(&driver->diagfwd_channel_mutex[peripheral]); + diagfwd_queue_read(&peripheral_info[TYPE_DATA][peripheral]); + diagfwd_queue_read(&peripheral_info[TYPE_CMD][peripheral]); +} + +void *diagfwd_request_write_buf(struct diagfwd_info *fwd_info) +{ + void *buf = NULL; + int index; + unsigned long flags; + + spin_lock_irqsave(&fwd_info->write_buf_lock, flags); + for (index = 0 ; index < NUM_WRITE_BUFFERS; index++) { + if (!atomic_read(&(fwd_info->buf_ptr[index]->in_busy))) { + atomic_set(&(fwd_info->buf_ptr[index]->in_busy), 1); + buf = fwd_info->buf_ptr[index]->data; + if (!buf) + return NULL; + break; + } + } + spin_unlock_irqrestore(&fwd_info->write_buf_lock, flags); + return buf; +} + +int diagfwd_write(uint8_t peripheral, uint8_t type, void *buf, int len) +{ + struct diagfwd_info *fwd_info = NULL; + int err = 0; + uint8_t retry_count = 0; + uint8_t max_retries = 3; + void *buf_ptr = NULL; + if (peripheral >= NUM_PERIPHERALS || type >= NUM_TYPES) + return -EINVAL; + + if (type == TYPE_CMD || type == TYPE_DCI_CMD) { + if (!driver->feature[peripheral].rcvd_feature_mask || + !driver->feature[peripheral].sent_feature_mask) { + pr_debug_ratelimited("diag: In %s, feature mask for peripheral: %d not received or sent yet\n", + __func__, peripheral); + return 0; + } + if (!driver->feature[peripheral].separate_cmd_rsp) + type = (type == TYPE_CMD) ? TYPE_DATA : TYPE_DCI; + } + + fwd_info = &peripheral_info[type][peripheral]; + if (!fwd_info->inited || !atomic_read(&fwd_info->opened)) + return -ENODEV; + + if (!(fwd_info->p_ops && fwd_info->p_ops->write && fwd_info->ctxt)) + return -EIO; + + if (fwd_info->transport == TRANSPORT_GLINK) { + buf_ptr = diagfwd_request_write_buf(fwd_info); + if (buf_ptr) + memcpy(buf_ptr, buf, len); + else { + DIAG_LOG(DIAG_DEBUG_PERIPHERALS, + "diag: buffer not found for writing\n"); + return -EIO; + } + } else + buf_ptr = buf; + + while (retry_count < max_retries) { + err = 0; + err = fwd_info->p_ops->write(fwd_info->ctxt, buf_ptr, len); + if (err && err != -ENODEV) { + usleep_range(100000, 101000); + retry_count++; + continue; + } + break; + } + + if (!err) + fwd_info->write_bytes += len; + else + if (fwd_info->transport == TRANSPORT_GLINK) + diagfwd_write_buffer_done(fwd_info, buf_ptr); + return err; +} + +static void __diag_fwd_open(struct diagfwd_info *fwd_info) +{ + bool set_busy = true; + + if (!fwd_info) + return; + + atomic_set(&fwd_info->opened, 1); + if (!fwd_info->inited) + return; + + /* + * Logging mode here is reflecting previous mode + * status and will be updated to new mode later. + * + * Keeping the buffers busy for Memory Device Mode. + */ + +#ifdef CONFIG_DIAG_OVER_USB + set_busy = (driver->logging_mode != DIAG_USB_MODE) || + driver->usb_connected; +#endif + if (set_busy) { + if (fwd_info->buf_1) { + atomic_set(&fwd_info->buf_1->in_busy, 0); + DIAG_LOG(DIAG_DEBUG_PERIPHERALS, + "Buffer 1 for core PD is marked free, p: %d, t: %d\n", + fwd_info->peripheral, fwd_info->type); + } + if (fwd_info->buf_2) { + atomic_set(&fwd_info->buf_2->in_busy, 0); + DIAG_LOG(DIAG_DEBUG_PERIPHERALS, + "Buffer 2 for core PD is marked free, p: %d, t: %d\n", + fwd_info->peripheral, fwd_info->type); + } + } + + if (fwd_info->p_ops && fwd_info->p_ops->open) + fwd_info->p_ops->open(fwd_info->ctxt); + + diagfwd_queue_read(fwd_info); +} + +void diagfwd_early_open(uint8_t peripheral) +{ + uint8_t transport = 0; + struct diagfwd_info *fwd_info = NULL; + + if (peripheral >= NUM_PERIPHERALS) + return; + + for (transport = 0; transport < NUM_TRANSPORT; transport++) { + fwd_info = &early_init_info[transport][peripheral]; + __diag_fwd_open(fwd_info); + } +} + +void diagfwd_open(uint8_t peripheral, uint8_t type) +{ + struct diagfwd_info *fwd_info = NULL; + + if (peripheral >= NUM_PERIPHERALS || type >= NUM_TYPES) + return; + + fwd_info = &peripheral_info[type][peripheral]; + __diag_fwd_open(fwd_info); +} + +void diagfwd_late_open(struct diagfwd_info *fwd_info) +{ + __diag_fwd_open(fwd_info); +} + +void diagfwd_close(uint8_t peripheral, uint8_t type) +{ + struct diagfwd_info *fwd_info = NULL; + + if (peripheral >= NUM_PERIPHERALS || type >= NUM_TYPES) + return; + + fwd_info = &peripheral_info[type][peripheral]; + atomic_set(&fwd_info->opened, 0); + if (!fwd_info->inited) + return; + + if (fwd_info->p_ops && fwd_info->p_ops->close) + fwd_info->p_ops->close(fwd_info->ctxt); + + if (fwd_info->buf_1) + atomic_set(&fwd_info->buf_1->in_busy, 1); + /* + * Only Data channels have two buffers. Set both the buffers + * to busy on close. + */ + if (fwd_info->buf_2) + atomic_set(&fwd_info->buf_2->in_busy, 1); +} + +int diagfwd_channel_open(struct diagfwd_info *fwd_info) +{ + int i; + if (!fwd_info) + return -EIO; + + if (!fwd_info->inited) { + pr_debug("diag: In %s, channel is not inited, p: %d, t: %d\n", + __func__, fwd_info->peripheral, fwd_info->type); + return -EINVAL; + } + + if (fwd_info->ch_open) { + pr_debug("diag: In %s, channel is already open, p: %d, t: %d\n", + __func__, fwd_info->peripheral, fwd_info->type); + return 0; + } + mutex_lock(&driver->diagfwd_channel_mutex[fwd_info->peripheral]); + fwd_info->ch_open = 1; + diagfwd_buffers_init(fwd_info); + + /* + * Initialize buffers for glink supported + * peripherals only. + */ + if (fwd_info->transport == TRANSPORT_GLINK) + diagfwd_write_buffers_init(fwd_info); + + if (fwd_info && fwd_info->c_ops && fwd_info->c_ops->open) + fwd_info->c_ops->open(fwd_info); + for (i = 0; i < NUM_WRITE_BUFFERS; i++) { + if (fwd_info->buf_ptr[i]) + atomic_set(&fwd_info->buf_ptr[i]->in_busy, 0); + } + diagfwd_queue_read(fwd_info); + DIAG_LOG(DIAG_DEBUG_PERIPHERALS, "p: %d t: %d considered opened\n", + fwd_info->peripheral, fwd_info->type); + + if (atomic_read(&fwd_info->opened)) { + if (fwd_info->p_ops && fwd_info->p_ops->open) + fwd_info->p_ops->open(fwd_info->ctxt); + } + mutex_unlock(&driver->diagfwd_channel_mutex[fwd_info->peripheral]); + return 0; +} + +int diagfwd_channel_close(struct diagfwd_info *fwd_info) +{ + int i; + if (!fwd_info) + return -EIO; + + if (fwd_info->type == TYPE_CNTL) + flush_workqueue(driver->cntl_wq); + + mutex_lock(&driver->diagfwd_channel_mutex[fwd_info->peripheral]); + fwd_info->ch_open = 0; + if (fwd_info && fwd_info->c_ops && fwd_info->c_ops->close) + fwd_info->c_ops->close(fwd_info); + + if (fwd_info->buf_1 && fwd_info->buf_1->data) { + atomic_set(&fwd_info->buf_1->in_busy, 0); + DIAG_LOG(DIAG_DEBUG_PERIPHERALS, + "Buffer 1 for core PD is marked free, p: %d, t: %d\n", + fwd_info->peripheral, fwd_info->type); + } + if (fwd_info->buf_2 && fwd_info->buf_2->data) { + atomic_set(&fwd_info->buf_2->in_busy, 0); + DIAG_LOG(DIAG_DEBUG_PERIPHERALS, + "Buffer 2 for core PD is marked free, p: %d, t: %d\n", + fwd_info->peripheral, fwd_info->type); + } + + for (i = 0; i < NUM_WRITE_BUFFERS; i++) { + if (fwd_info->buf_ptr[i]) + atomic_set(&fwd_info->buf_ptr[i]->in_busy, 1); + } + DIAG_LOG(DIAG_DEBUG_PERIPHERALS, "p: %d t: %d considered closed\n", + fwd_info->peripheral, fwd_info->type); + mutex_unlock(&driver->diagfwd_channel_mutex[fwd_info->peripheral]); + return 0; +} + +int diagfwd_channel_read_done(struct diagfwd_info *fwd_info, + unsigned char *buf, uint32_t len) +{ + if (!fwd_info) { + diag_ws_release(); + return -EIO; + } + + /* + * Diag peripheral layers should send len as 0 if there is any error + * in reading data from the transport. Use this information to reset the + * in_busy flags. No need to queue read in this case. + */ + if (len == 0) { + DIAG_LOG(DIAG_DEBUG_PERIPHERALS, + "Read Length is 0, resetting the diag buffers p: %d, t: %d\n", + fwd_info->peripheral, fwd_info->type); + diagfwd_reset_buffers(fwd_info, buf); + diag_ws_release(); + return 0; + } + + if (fwd_info && fwd_info->c_ops && fwd_info->c_ops->read_done) + fwd_info->c_ops->read_done(fwd_info, buf, len); + fwd_info->read_bytes += len; + + return 0; +} + +void diagfwd_write_done(uint8_t peripheral, uint8_t type, int buf_num) +{ + struct diagfwd_info *fwd_info = NULL; + + if (peripheral >= NUM_PERIPHERALS || type >= NUM_TYPES) + return; + + fwd_info = &peripheral_info[type][peripheral]; + if (!fwd_info) + return; + + if (buf_num == 1 && fwd_info->buf_1) { + /* Buffer 1 for core PD is freed */ + fwd_info->cpd_len_1 = 0; + + if (peripheral == PERIPHERAL_LPASS) { + if (!fwd_info->upd_len_1_a && + !fwd_info->upd_len_2_a) + atomic_set(&fwd_info->buf_1->in_busy, 0); + } else if (peripheral == PERIPHERAL_MODEM) { + if (!fwd_info->upd_len_1_a) + atomic_set(&fwd_info->buf_1->in_busy, 0); + } else { + atomic_set(&fwd_info->buf_1->in_busy, 0); + } + if (!atomic_read(&(fwd_info->buf_1->in_busy))) { + DIAG_LOG(DIAG_DEBUG_PERIPHERALS, + "Buffer 1 for core PD is marked free, p: %d, t: %d, buf_num: %d\n", + fwd_info->peripheral, fwd_info->type, buf_num); + } + } else if (buf_num == 2 && fwd_info->buf_2) { + /* Buffer 2 for core PD is freed */ + fwd_info->cpd_len_2 = 0; + + if (peripheral == PERIPHERAL_LPASS) { + if (!fwd_info->upd_len_1_b && + !fwd_info->upd_len_2_b) + atomic_set(&fwd_info->buf_2->in_busy, 0); + } else if (peripheral == PERIPHERAL_MODEM) { + if (!fwd_info->upd_len_1_b) + atomic_set(&fwd_info->buf_2->in_busy, 0); + } else { + atomic_set(&fwd_info->buf_2->in_busy, 0); + } + if (!atomic_read(&(fwd_info->buf_2->in_busy))) { + DIAG_LOG(DIAG_DEBUG_PERIPHERALS, + "Buffer 2 for core PD is marked free, p: %d, t: %d, buf_num: %d\n", + fwd_info->peripheral, fwd_info->type, buf_num); + } + } else if (buf_num == 3 && fwd_info->buf_upd_1_a && fwd_info->buf_1) { + /* Buffer 1 for user pd 1 is freed */ + atomic_set(&fwd_info->buf_upd_1_a->in_busy, 0); + + if (peripheral == PERIPHERAL_LPASS) { + /* if not data in cpd and other user pd + * free the core pd buffer for LPASS + */ + if (!fwd_info->cpd_len_1 && + !fwd_info->upd_len_2_a) + atomic_set(&fwd_info->buf_1->in_busy, 0); + } else { + /* if not data in cpd + * free the core pd buffer for MPSS + */ + if (!fwd_info->cpd_len_1) + atomic_set(&fwd_info->buf_1->in_busy, 0); + } + if (!atomic_read(&(fwd_info->buf_1->in_busy))) { + DIAG_LOG(DIAG_DEBUG_PERIPHERALS, + "Buffer 1 for core PD is marked free, p: %d, t: %d, buf_num: %d\n", + fwd_info->peripheral, fwd_info->type, buf_num); + } + fwd_info->upd_len_1_a = 0; + + } else if (buf_num == 4 && fwd_info->buf_upd_1_b && fwd_info->buf_2) { + /* Buffer 2 for user pd 1 is freed */ + atomic_set(&fwd_info->buf_upd_1_b->in_busy, 0); + if (peripheral == PERIPHERAL_LPASS) { + /* if not data in cpd and other user pd + * free the core pd buffer for LPASS + */ + if (!fwd_info->cpd_len_2 && + !fwd_info->upd_len_2_b) + atomic_set(&fwd_info->buf_2->in_busy, 0); + } else { + /* if not data in cpd + * free the core pd buffer for MPSS + */ + if (!fwd_info->cpd_len_2) + atomic_set(&fwd_info->buf_2->in_busy, 0); + } + if (!atomic_read(&(fwd_info->buf_2->in_busy))) { + DIAG_LOG(DIAG_DEBUG_PERIPHERALS, + "Buffer 2 for core PD is marked free, p: %d, t: %d, buf_num: %d\n", + fwd_info->peripheral, fwd_info->type, buf_num); + } + fwd_info->upd_len_1_b = 0; + + } else if (buf_num == 5 && fwd_info->buf_upd_2_a && fwd_info->buf_1) { + /* Buffer 1 for user pd 2 is freed */ + atomic_set(&fwd_info->buf_upd_2_a->in_busy, 0); + /* if not data in cpd and other user pd + * free the core pd buffer for LPASS + */ + if (!fwd_info->cpd_len_1 && + !fwd_info->upd_len_1_a) { + atomic_set(&fwd_info->buf_1->in_busy, 0); + DIAG_LOG(DIAG_DEBUG_PERIPHERALS, + "Buffer 1 for core PD is marked free, p: %d, t: %d, buf_num: %d\n", + fwd_info->peripheral, fwd_info->type, buf_num); + } + + fwd_info->upd_len_2_a = 0; + + } else if (buf_num == 6 && fwd_info->buf_upd_2_b && fwd_info->buf_2) { + /* Buffer 2 for user pd 2 is freed */ + atomic_set(&fwd_info->buf_upd_2_b->in_busy, 0); + /* if not data in cpd and other user pd + * free the core pd buffer for LPASS + */ + if (!fwd_info->cpd_len_2 && + !fwd_info->upd_len_1_b) { + atomic_set(&fwd_info->buf_2->in_busy, 0); + DIAG_LOG(DIAG_DEBUG_PERIPHERALS, + "Buffer 2 for core PD is marked free, p: %d, t: %d, buf_num: %d\n", + fwd_info->peripheral, fwd_info->type, buf_num); + } + fwd_info->upd_len_2_b = 0; + + } else + pr_err("diag: In %s, invalid buf_num: %d\n", __func__, buf_num); + + diagfwd_queue_read(fwd_info); +} + +int diagfwd_write_buffer_done(struct diagfwd_info *fwd_info, const void *ptr) +{ + + int found = 0; + int index = 0; + unsigned long flags; + + if (!fwd_info || !ptr) + return found; + spin_lock_irqsave(&fwd_info->write_buf_lock, flags); + for (index = 0; index < NUM_WRITE_BUFFERS; index++) { + if (fwd_info->buf_ptr[index]->data == ptr) { + atomic_set(&fwd_info->buf_ptr[index]->in_busy, 0); + found = 1; + break; + } + } + spin_unlock_irqrestore(&fwd_info->write_buf_lock, flags); + return found; +} + +void diagfwd_channel_read(struct diagfwd_info *fwd_info) +{ + int err = 0; + uint32_t read_len = 0; + unsigned char *read_buf = NULL; + struct diagfwd_buf_t *temp_buf = NULL; + + if (!fwd_info) { + diag_ws_release(); + return; + } + + if (!fwd_info->inited || !atomic_read(&fwd_info->opened)) { + pr_debug("diag: In %s, p: %d, t: %d, inited: %d, opened: %d ch_open: %d\n", + __func__, fwd_info->peripheral, fwd_info->type, + fwd_info->inited, atomic_read(&fwd_info->opened), + fwd_info->ch_open); + diag_ws_release(); + return; + } + + if (fwd_info->buf_1 && !atomic_read(&fwd_info->buf_1->in_busy)) { + if (driver->feature[fwd_info->peripheral].encode_hdlc && + (fwd_info->type == TYPE_DATA || + fwd_info->type == TYPE_CMD)) { + read_buf = fwd_info->buf_1->data_raw; + read_len = fwd_info->buf_1->len_raw; + } else { + read_buf = fwd_info->buf_1->data; + read_len = fwd_info->buf_1->len; + } + if (read_buf) { + temp_buf = fwd_info->buf_1; + atomic_set(&temp_buf->in_busy, 1); + } + } else if (fwd_info->buf_2 && !atomic_read(&fwd_info->buf_2->in_busy)) { + if (driver->feature[fwd_info->peripheral].encode_hdlc && + (fwd_info->type == TYPE_DATA || + fwd_info->type == TYPE_CMD)) { + read_buf = fwd_info->buf_2->data_raw; + read_len = fwd_info->buf_2->len_raw; + } else { + read_buf = fwd_info->buf_2->data; + read_len = fwd_info->buf_2->len; + } + if (read_buf) { + temp_buf = fwd_info->buf_2; + atomic_set(&temp_buf->in_busy, 1); + } + } else { + pr_debug("diag: In %s, both buffers are empty for p: %d, t: %d\n", + __func__, fwd_info->peripheral, fwd_info->type); + } + + if (!read_buf) { + diag_ws_release(); + return; + } + + if (!(fwd_info->p_ops && fwd_info->p_ops->read && fwd_info->ctxt)) + goto fail_return; + + DIAG_LOG(DIAG_DEBUG_PERIPHERALS, "issued a read p: %d t: %d buf: %pK\n", + fwd_info->peripheral, fwd_info->type, read_buf); + err = fwd_info->p_ops->read(fwd_info->ctxt, read_buf, read_len); + if (err) + goto fail_return; + + return; + +fail_return: + diag_ws_release(); + atomic_set(&temp_buf->in_busy, 0); + return; +} + +static void diagfwd_queue_read(struct diagfwd_info *fwd_info) +{ + if (!fwd_info) + return; + + if (!fwd_info->inited || !atomic_read(&fwd_info->opened)) { + pr_debug("diag: In %s, p: %d, t: %d, inited: %d, opened: %d ch_open: %d\n", + __func__, fwd_info->peripheral, fwd_info->type, + fwd_info->inited, atomic_read(&fwd_info->opened), + fwd_info->ch_open); + return; + } + + /* + * Don't queue a read on the data and command channels before receiving + * the feature mask from the peripheral. We won't know which buffer to + * use - HDLC or non HDLC buffer for reading. + */ + if ((!driver->feature[fwd_info->peripheral].rcvd_feature_mask) && + (fwd_info->type != TYPE_CNTL)) { + return; + } + + if (fwd_info->p_ops && fwd_info->p_ops->queue_read && fwd_info->ctxt) + fwd_info->p_ops->queue_read(fwd_info->ctxt); +} + +void diagfwd_buffers_init(struct diagfwd_info *fwd_info) +{ + struct diagfwd_buf_t *temp_fwd_buf; + unsigned char *temp_char_buf; + + if (!fwd_info) + return; + + if (!fwd_info->inited) { + pr_err("diag: In %s, channel not inited, p: %d, t: %d\n", + __func__, fwd_info->peripheral, fwd_info->type); + return; + } + + mutex_lock(&fwd_info->buf_mutex); + + if (!fwd_info->buf_1) { + fwd_info->buf_1 = kzalloc(sizeof(struct diagfwd_buf_t), + GFP_KERNEL); + if (ZERO_OR_NULL_PTR(fwd_info->buf_1)) + goto err; + kmemleak_not_leak(fwd_info->buf_1); + } + + if (!fwd_info->buf_1->data) { + fwd_info->buf_1->data = kzalloc(PERIPHERAL_BUF_SZ + + APF_DIAG_PADDING, + GFP_KERNEL); + if (ZERO_OR_NULL_PTR(fwd_info->buf_1->data)) + goto err; + fwd_info->buf_1->len = PERIPHERAL_BUF_SZ; + kmemleak_not_leak(fwd_info->buf_1->data); + fwd_info->buf_1->ctxt = SET_BUF_CTXT(fwd_info->peripheral, + fwd_info->type, 1); + } + + if (fwd_info->type == TYPE_DATA) { + if (!fwd_info->buf_2) { + fwd_info->buf_2 = kzalloc(sizeof(struct diagfwd_buf_t), + GFP_KERNEL); + if (ZERO_OR_NULL_PTR(fwd_info->buf_2)) + goto err; + kmemleak_not_leak(fwd_info->buf_2); + } + + if (!fwd_info->buf_2->data) { + fwd_info->buf_2->data = kzalloc(PERIPHERAL_BUF_SZ + + APF_DIAG_PADDING, + GFP_KERNEL); + if (ZERO_OR_NULL_PTR(fwd_info->buf_2->data)) + goto err; + fwd_info->buf_2->len = PERIPHERAL_BUF_SZ; + kmemleak_not_leak(fwd_info->buf_2->data); + fwd_info->buf_2->ctxt = SET_BUF_CTXT( + fwd_info->peripheral, + fwd_info->type, 2); + } + + if (driver->feature[fwd_info->peripheral].untag_header) { + if (!fwd_info->buf_upd_1_a) { + fwd_info->buf_upd_1_a = + kzalloc(sizeof(struct diagfwd_buf_t), + GFP_KERNEL); + if (ZERO_OR_NULL_PTR(fwd_info->buf_upd_1_a)) + goto err; + kmemleak_not_leak(fwd_info->buf_upd_1_a); + } + + if (fwd_info->buf_upd_1_a && + !fwd_info->buf_upd_1_a->data) { + fwd_info->buf_upd_1_a->data = + kzalloc(PERIPHERAL_BUF_SZ + + APF_DIAG_PADDING, + GFP_KERNEL); + temp_char_buf = fwd_info->buf_upd_1_a->data; + if (ZERO_OR_NULL_PTR(temp_char_buf)) + goto err; + fwd_info->buf_upd_1_a->len = PERIPHERAL_BUF_SZ; + kmemleak_not_leak(temp_char_buf); + fwd_info->buf_upd_1_a->ctxt = SET_BUF_CTXT( + fwd_info->peripheral, + fwd_info->type, 3); + } + + if (!fwd_info->buf_upd_1_b) { + fwd_info->buf_upd_1_b = + kzalloc(sizeof(struct diagfwd_buf_t), + GFP_KERNEL); + if (ZERO_OR_NULL_PTR(fwd_info->buf_upd_1_b)) + goto err; + kmemleak_not_leak(fwd_info->buf_upd_1_b); + } + + if (fwd_info->buf_upd_1_b && + !fwd_info->buf_upd_1_b->data) { + fwd_info->buf_upd_1_b->data = + kzalloc(PERIPHERAL_BUF_SZ + + APF_DIAG_PADDING, + GFP_KERNEL); + temp_char_buf = + fwd_info->buf_upd_1_b->data; + if (ZERO_OR_NULL_PTR(temp_char_buf)) + goto err; + fwd_info->buf_upd_1_b->len = + PERIPHERAL_BUF_SZ; + kmemleak_not_leak(temp_char_buf); + fwd_info->buf_upd_1_b->ctxt = SET_BUF_CTXT( + fwd_info->peripheral, + fwd_info->type, 4); + } + if (fwd_info->peripheral == + PERIPHERAL_LPASS) { + if (!fwd_info->buf_upd_2_a) { + fwd_info->buf_upd_2_a = + kzalloc(sizeof(struct diagfwd_buf_t), + GFP_KERNEL); + temp_fwd_buf = + fwd_info->buf_upd_2_a; + if (ZERO_OR_NULL_PTR(temp_fwd_buf)) + goto err; + kmemleak_not_leak(temp_fwd_buf); + } + + if (!fwd_info->buf_upd_2_a->data) { + fwd_info->buf_upd_2_a->data = + kzalloc(PERIPHERAL_BUF_SZ + + APF_DIAG_PADDING, + GFP_KERNEL); + temp_char_buf = + fwd_info->buf_upd_2_a->data; + if (ZERO_OR_NULL_PTR(temp_char_buf)) + goto err; + fwd_info->buf_upd_2_a->len = + PERIPHERAL_BUF_SZ; + kmemleak_not_leak(temp_char_buf); + fwd_info->buf_upd_2_a->ctxt = + SET_BUF_CTXT( + fwd_info->peripheral, + fwd_info->type, 5); + } + if (!fwd_info->buf_upd_2_b) { + fwd_info->buf_upd_2_b = + kzalloc(sizeof(struct diagfwd_buf_t), + GFP_KERNEL); + temp_fwd_buf = + fwd_info->buf_upd_2_b; + if (ZERO_OR_NULL_PTR(temp_fwd_buf)) + goto err; + kmemleak_not_leak(temp_fwd_buf); + } + + if (!fwd_info->buf_upd_2_b->data) { + fwd_info->buf_upd_2_b->data = + kzalloc(PERIPHERAL_BUF_SZ + + APF_DIAG_PADDING, + GFP_KERNEL); + temp_char_buf = + fwd_info->buf_upd_2_b->data; + if (ZERO_OR_NULL_PTR(temp_char_buf)) + goto err; + fwd_info->buf_upd_2_b->len = + PERIPHERAL_BUF_SZ; + kmemleak_not_leak(temp_char_buf); + fwd_info->buf_upd_2_b->ctxt = + SET_BUF_CTXT( + fwd_info->peripheral, + fwd_info->type, 6); + } + } + } + + if (driver->supports_apps_hdlc_encoding) { + /* In support of hdlc encoding */ + if (!fwd_info->buf_1->data_raw) { + fwd_info->buf_1->data_raw = + kzalloc(PERIPHERAL_BUF_SZ + + APF_DIAG_PADDING, + GFP_KERNEL); + temp_char_buf = + fwd_info->buf_1->data_raw; + if (ZERO_OR_NULL_PTR(temp_char_buf)) + goto err; + fwd_info->buf_1->len_raw = + PERIPHERAL_BUF_SZ; + kmemleak_not_leak(temp_char_buf); + } + + if (!fwd_info->buf_2->data_raw) { + fwd_info->buf_2->data_raw = + kzalloc(PERIPHERAL_BUF_SZ + + APF_DIAG_PADDING, + GFP_KERNEL); + temp_char_buf = + fwd_info->buf_2->data_raw; + if (ZERO_OR_NULL_PTR(temp_char_buf)) + goto err; + fwd_info->buf_2->len_raw = + PERIPHERAL_BUF_SZ; + kmemleak_not_leak(temp_char_buf); + } + + if (driver->feature[fwd_info->peripheral]. + untag_header) { + if (fwd_info->buf_upd_1_a && + !fwd_info->buf_upd_1_a->data_raw) { + fwd_info->buf_upd_1_a->data_raw = + kzalloc(PERIPHERAL_BUF_SZ + + APF_DIAG_PADDING, + GFP_KERNEL); + temp_char_buf = + fwd_info->buf_upd_1_a->data_raw; + if (ZERO_OR_NULL_PTR(temp_char_buf)) + goto err; + fwd_info->buf_upd_1_a->len_raw = + PERIPHERAL_BUF_SZ; + kmemleak_not_leak(temp_char_buf); + } + + if (fwd_info->buf_upd_1_b && + !fwd_info->buf_upd_1_b->data_raw) { + fwd_info->buf_upd_1_b->data_raw = + kzalloc(PERIPHERAL_BUF_SZ + + APF_DIAG_PADDING, + GFP_KERNEL); + temp_char_buf = + fwd_info->buf_upd_1_b->data_raw; + if (ZERO_OR_NULL_PTR(temp_char_buf)) + goto err; + fwd_info->buf_upd_1_b->len_raw = + PERIPHERAL_BUF_SZ; + kmemleak_not_leak(temp_char_buf); + } + if (fwd_info->peripheral == PERIPHERAL_LPASS + && !fwd_info->buf_upd_2_a->data_raw) { + fwd_info->buf_upd_2_a->data_raw = + kzalloc(PERIPHERAL_BUF_SZ + + APF_DIAG_PADDING, + GFP_KERNEL); + temp_char_buf = + fwd_info->buf_upd_2_a->data_raw; + if (ZERO_OR_NULL_PTR(temp_char_buf)) + goto err; + fwd_info->buf_upd_2_a->len_raw = + PERIPHERAL_BUF_SZ; + kmemleak_not_leak(temp_char_buf); + } + if (fwd_info->peripheral == PERIPHERAL_LPASS + && !fwd_info->buf_upd_2_b->data_raw) { + fwd_info->buf_upd_2_b->data_raw = + kzalloc(PERIPHERAL_BUF_SZ + + APF_DIAG_PADDING, + GFP_KERNEL); + temp_char_buf = + fwd_info->buf_upd_2_b->data_raw; + if (ZERO_OR_NULL_PTR(temp_char_buf)) + goto err; + fwd_info->buf_upd_2_b->len_raw = + PERIPHERAL_BUF_SZ; + kmemleak_not_leak(temp_char_buf); + } + } + } + } + + if (fwd_info->type == TYPE_CMD && + driver->supports_apps_hdlc_encoding) { + /* In support of hdlc encoding */ + if (!fwd_info->buf_1->data_raw) { + fwd_info->buf_1->data_raw = kzalloc(PERIPHERAL_BUF_SZ + + APF_DIAG_PADDING, + GFP_KERNEL); + temp_char_buf = + fwd_info->buf_1->data_raw; + if (ZERO_OR_NULL_PTR(temp_char_buf)) + goto err; + fwd_info->buf_1->len_raw = PERIPHERAL_BUF_SZ; + kmemleak_not_leak(temp_char_buf); + } + } + + mutex_unlock(&fwd_info->buf_mutex); + return; + +err: + mutex_unlock(&fwd_info->buf_mutex); + diagfwd_buffers_exit(fwd_info); + + return; +} + +static void diagfwd_buffers_exit(struct diagfwd_info *fwd_info) +{ + + if (!fwd_info) + return; + + mutex_lock(&fwd_info->buf_mutex); + if (fwd_info->buf_1) { + kfree(fwd_info->buf_1->data); + fwd_info->buf_1->data = NULL; + kfree(fwd_info->buf_1->data_raw); + fwd_info->buf_1->data_raw = NULL; + kfree(fwd_info->buf_1); + fwd_info->buf_1 = NULL; + } + if (fwd_info->buf_2) { + kfree(fwd_info->buf_2->data); + fwd_info->buf_2->data = NULL; + kfree(fwd_info->buf_2->data_raw); + fwd_info->buf_2->data_raw = NULL; + kfree(fwd_info->buf_2); + fwd_info->buf_2 = NULL; + } + if (fwd_info->buf_upd_1_a) { + kfree(fwd_info->buf_upd_1_a->data); + fwd_info->buf_upd_1_a->data = NULL; + kfree(fwd_info->buf_upd_1_a->data_raw); + fwd_info->buf_upd_1_a->data_raw = NULL; + kfree(fwd_info->buf_upd_1_a); + fwd_info->buf_upd_1_a = NULL; + } + if (fwd_info->buf_upd_1_b) { + kfree(fwd_info->buf_upd_1_b->data); + fwd_info->buf_upd_1_b->data = NULL; + kfree(fwd_info->buf_upd_1_b->data_raw); + fwd_info->buf_upd_1_b->data_raw = NULL; + kfree(fwd_info->buf_upd_1_b); + fwd_info->buf_upd_1_b = NULL; + } + if (fwd_info->buf_upd_2_a) { + kfree(fwd_info->buf_upd_2_a->data); + fwd_info->buf_upd_2_a->data = NULL; + kfree(fwd_info->buf_upd_2_a->data_raw); + fwd_info->buf_upd_2_a->data_raw = NULL; + kfree(fwd_info->buf_upd_2_a); + fwd_info->buf_upd_2_a = NULL; + } + if (fwd_info->buf_upd_2_b) { + kfree(fwd_info->buf_upd_2_b->data); + fwd_info->buf_upd_2_b->data = NULL; + kfree(fwd_info->buf_upd_2_b->data_raw); + fwd_info->buf_upd_2_b->data_raw = NULL; + kfree(fwd_info->buf_upd_2_b); + fwd_info->buf_upd_2_b = NULL; + } + mutex_unlock(&fwd_info->buf_mutex); +} + +void diagfwd_write_buffers_init(struct diagfwd_info *fwd_info) +{ + unsigned long flags; + int i; + + if (!fwd_info) + return; + + if (!fwd_info->inited) { + pr_err("diag: In %s, channel not inited, p: %d, t: %d\n", + __func__, fwd_info->peripheral, fwd_info->type); + return; + } + + spin_lock_irqsave(&fwd_info->write_buf_lock, flags); + for (i = 0; i < NUM_WRITE_BUFFERS; i++) { + if (!fwd_info->buf_ptr[i]) + fwd_info->buf_ptr[i] = + kzalloc(sizeof(struct diagfwd_buf_t), + GFP_ATOMIC); + if (!fwd_info->buf_ptr[i]) + goto err; + kmemleak_not_leak(fwd_info->buf_ptr[i]); + if (!fwd_info->buf_ptr[i]->data) { + fwd_info->buf_ptr[i]->data = kzalloc(PERIPHERAL_BUF_SZ, + GFP_ATOMIC); + if (!fwd_info->buf_ptr[i]->data) + goto err; + fwd_info->buf_ptr[i]->len = PERIPHERAL_BUF_SZ; + kmemleak_not_leak(fwd_info->buf_ptr[i]->data); + } + } + spin_unlock_irqrestore(&fwd_info->write_buf_lock, flags); + return; + +err: + spin_unlock_irqrestore(&fwd_info->write_buf_lock, flags); + pr_err("diag:unable to allocate write buffers\n"); + diagfwd_write_buffers_exit(fwd_info); + +} + +static void diagfwd_write_buffers_exit(struct diagfwd_info *fwd_info) +{ + unsigned long flags; + int i; + + if (!fwd_info) + return; + + spin_lock_irqsave(&fwd_info->write_buf_lock, flags); + for (i = 0; i < NUM_WRITE_BUFFERS; i++) { + if (fwd_info->buf_ptr[i]) { + kfree(fwd_info->buf_ptr[i]->data); + fwd_info->buf_ptr[i]->data = NULL; + kfree(fwd_info->buf_ptr[i]); + fwd_info->buf_ptr[i] = NULL; + } + } + spin_unlock_irqrestore(&fwd_info->write_buf_lock, flags); +} diff -Nruw linux-4.4.115-fbx/drivers/char/diag./diagfwd_peripheral.h linux-4.4.115-fbx/drivers/char/diag/diagfwd_peripheral.h --- linux-4.4.115-fbx/drivers/char/diag./diagfwd_peripheral.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-4.4.115-fbx/drivers/char/diag/diagfwd_peripheral.h 2019-01-22 16:16:22.963241516 +0100 @@ -0,0 +1,133 @@ +/* Copyright (c) 2015-2017, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef DIAGFWD_PERIPHERAL_H +#define DIAGFWD_PERIPHERAL_H + +#define PERIPHERAL_BUF_SZ 16384 +#define MAX_PERIPHERAL_BUF_SZ 32768 +#define MAX_PERIPHERAL_HDLC_BUF_SZ 65539 + +#define TRANSPORT_UNKNOWN -1 +#define TRANSPORT_SMD 0 +#define TRANSPORT_SOCKET 1 +#define TRANSPORT_GLINK 2 +#define NUM_TRANSPORT 3 +#define NUM_WRITE_BUFFERS 2 +#define PERIPHERAL_MASK(x) \ + ((x == PERIPHERAL_MODEM) ? DIAG_CON_MPSS : \ + ((x == PERIPHERAL_LPASS) ? DIAG_CON_LPASS : \ + ((x == PERIPHERAL_WCNSS) ? DIAG_CON_WCNSS : \ + ((x == PERIPHERAL_SENSORS) ? DIAG_CON_SENSORS : \ + ((x == PERIPHERAL_WDSP) ? DIAG_CON_WDSP : \ + ((x == PERIPHERAL_CDSP) ? DIAG_CON_CDSP : 0)))))) \ + +#define PERIPHERAL_STRING(x) \ + ((x == PERIPHERAL_MODEM) ? "MODEM" : \ + ((x == PERIPHERAL_LPASS) ? "LPASS" : \ + ((x == PERIPHERAL_WCNSS) ? "WCNSS" : \ + ((x == PERIPHERAL_SENSORS) ? "SENSORS" : \ + ((x == PERIPHERAL_WDSP) ? "WDSP" : \ + ((x == PERIPHERAL_CDSP) ? "CDSP" : "UNKNOWN")))))) \ + +struct diagfwd_buf_t { + unsigned char *data; + unsigned char *data_raw; + uint32_t len; + uint32_t len_raw; + atomic_t in_busy; + int ctxt; +}; + +struct diag_channel_ops { + void (*open)(struct diagfwd_info *fwd_info); + void (*close)(struct diagfwd_info *fwd_info); + void (*read_done)(struct diagfwd_info *fwd_info, + unsigned char *buf, int len); +}; + +struct diag_peripheral_ops { + void (*open)(void *ctxt); + void (*close)(void *ctxt); + int (*write)(void *ctxt, unsigned char *buf, int len); + int (*read)(void *ctxt, unsigned char *buf, int len); + void (*queue_read)(void *ctxt); +}; + +struct diagfwd_info { + uint8_t peripheral; + uint8_t type; + uint8_t transport; + uint8_t inited; + uint8_t ch_open; + atomic_t opened; + unsigned long read_bytes; + unsigned long write_bytes; + spinlock_t write_buf_lock; + struct mutex buf_mutex; + struct mutex data_mutex; + void *ctxt; + struct diagfwd_buf_t *buf_1; + struct diagfwd_buf_t *buf_2; + struct diagfwd_buf_t *buf_upd_1_a; + struct diagfwd_buf_t *buf_upd_1_b; + struct diagfwd_buf_t *buf_upd_2_a; + struct diagfwd_buf_t *buf_upd_2_b; + struct diagfwd_buf_t *buf_ptr[NUM_WRITE_BUFFERS]; + int cpd_len_1; + int cpd_len_2; + int upd_len_1_a; + int upd_len_1_b; + int upd_len_2_a; + int upd_len_2_b; + struct diag_peripheral_ops *p_ops; + struct diag_channel_ops *c_ops; +}; + +extern struct diagfwd_info peripheral_info[NUM_TYPES][NUM_PERIPHERALS]; + +int diagfwd_peripheral_init(void); +void diagfwd_peripheral_exit(void); + +void diagfwd_close_transport(uint8_t transport, uint8_t peripheral); + +void diagfwd_open(uint8_t peripheral, uint8_t type); +void diagfwd_early_open(uint8_t peripheral); + +void diagfwd_late_open(struct diagfwd_info *fwd_info); +void diagfwd_close(uint8_t peripheral, uint8_t type); + +int diag_md_get_peripheral(int ctxt); + +int diagfwd_register(uint8_t transport, uint8_t peripheral, uint8_t type, + void *ctxt, struct diag_peripheral_ops *ops, + struct diagfwd_info **fwd_ctxt); +int diagfwd_cntl_register(uint8_t transport, uint8_t peripheral, void *ctxt, + struct diag_peripheral_ops *ops, + struct diagfwd_info **fwd_ctxt); +void diagfwd_deregister(uint8_t peripheral, uint8_t type, void *ctxt); + +int diagfwd_write(uint8_t peripheral, uint8_t type, void *buf, int len); +void diagfwd_write_done(uint8_t peripheral, uint8_t type, int buf_num); +void diagfwd_buffers_init(struct diagfwd_info *fwd_info); + +/* + * The following functions are called by the channels + */ +int diagfwd_channel_open(struct diagfwd_info *fwd_info); +int diagfwd_channel_close(struct diagfwd_info *fwd_info); +void diagfwd_channel_read(struct diagfwd_info *fwd_info); +int diagfwd_channel_read_done(struct diagfwd_info *fwd_info, + unsigned char *buf, uint32_t len); +int diagfwd_write_buffer_done(struct diagfwd_info *fwd_info, const void *ptr); + +#endif diff -Nruw linux-4.4.115-fbx/drivers/char/diag./diagfwd_smd.c linux-4.4.115-fbx/drivers/char/diag/diagfwd_smd.c --- linux-4.4.115-fbx/drivers/char/diag./diagfwd_smd.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-4.4.115-fbx/drivers/char/diag/diagfwd_smd.c 2019-01-22 16:16:22.963241516 +0100 @@ -0,0 +1,898 @@ +/* Copyright (c) 2015-2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "diagchar.h" +#include "diagfwd.h" +#include "diagfwd_peripheral.h" +#include "diagfwd_smd.h" +#include "diag_ipc_logging.h" + +struct diag_smd_info smd_data[NUM_PERIPHERALS] = { + { + .peripheral = PERIPHERAL_MODEM, + .type = TYPE_DATA, + .name = "MODEM_DATA" + }, + { + .peripheral = PERIPHERAL_LPASS, + .type = TYPE_DATA, + .name = "LPASS_DATA" + }, + { + .peripheral = PERIPHERAL_WCNSS, + .type = TYPE_DATA, + .name = "WCNSS_DATA" + }, + { + .peripheral = PERIPHERAL_SENSORS, + .type = TYPE_DATA, + .name = "SENSORS_DATA" + }, + { + .peripheral = PERIPHERAL_WDSP, + .type = TYPE_DATA, + .name = "DIAG_DATA" + }, + { + .peripheral = PERIPHERAL_CDSP, + .type = TYPE_DATA, + .name = "CDSP_DATA" + } +}; + +struct diag_smd_info smd_cntl[NUM_PERIPHERALS] = { + { + .peripheral = PERIPHERAL_MODEM, + .type = TYPE_CNTL, + .name = "MODEM_CNTL" + }, + { + .peripheral = PERIPHERAL_LPASS, + .type = TYPE_CNTL, + .name = "LPASS_CNTL" + }, + { + .peripheral = PERIPHERAL_WCNSS, + .type = TYPE_CNTL, + .name = "WCNSS_CNTL" + }, + { + .peripheral = PERIPHERAL_SENSORS, + .type = TYPE_CNTL, + .name = "SENSORS_CNTL" + }, + { + .peripheral = PERIPHERAL_WDSP, + .type = TYPE_CNTL, + .name = "DIAG_CTRL" + }, + { + .peripheral = PERIPHERAL_CDSP, + .type = TYPE_CNTL, + .name = "CDSP_CNTL" + } +}; + +struct diag_smd_info smd_dci[NUM_PERIPHERALS] = { + { + .peripheral = PERIPHERAL_MODEM, + .type = TYPE_DCI, + .name = "MODEM_DCI" + }, + { + .peripheral = PERIPHERAL_LPASS, + .type = TYPE_DCI, + .name = "LPASS_DCI" + }, + { + .peripheral = PERIPHERAL_WCNSS, + .type = TYPE_DCI, + .name = "WCNSS_DCI" + }, + { + .peripheral = PERIPHERAL_SENSORS, + .type = TYPE_DCI, + .name = "SENSORS_DCI" + }, + { + .peripheral = PERIPHERAL_WDSP, + .type = TYPE_DCI, + .name = "DIAG_DCI_DATA" + }, + { + .peripheral = PERIPHERAL_CDSP, + .type = TYPE_DCI, + .name = "CDSP_DCI" + } +}; + +struct diag_smd_info smd_cmd[NUM_PERIPHERALS] = { + { + .peripheral = PERIPHERAL_MODEM, + .type = TYPE_CMD, + .name = "MODEM_CMD" + }, + { + .peripheral = PERIPHERAL_LPASS, + .type = TYPE_CMD, + .name = "LPASS_CMD" + }, + { + .peripheral = PERIPHERAL_WCNSS, + .type = TYPE_CMD, + .name = "WCNSS_CMD" + }, + { + .peripheral = PERIPHERAL_SENSORS, + .type = TYPE_CMD, + .name = "SENSORS_CMD" + }, + { + .peripheral = PERIPHERAL_WDSP, + .type = TYPE_CMD, + .name = "DIAG_CMD" + }, + { + .peripheral = PERIPHERAL_CDSP, + .type = TYPE_CMD, + .name = "CDSP_CMD" + } +}; + +struct diag_smd_info smd_dci_cmd[NUM_PERIPHERALS] = { + { + .peripheral = PERIPHERAL_MODEM, + .type = TYPE_DCI_CMD, + .name = "MODEM_DCI_CMD" + }, + { + .peripheral = PERIPHERAL_LPASS, + .type = TYPE_DCI_CMD, + .name = "LPASS_DCI_CMD" + }, + { + .peripheral = PERIPHERAL_WCNSS, + .type = TYPE_DCI_CMD, + .name = "WCNSS_DCI_CMD" + }, + { + .peripheral = PERIPHERAL_SENSORS, + .type = TYPE_DCI_CMD, + .name = "SENSORS_DCI_CMD" + }, + { + .peripheral = PERIPHERAL_WDSP, + .type = TYPE_DCI_CMD, + .name = "DIAG_DCI_CMD" + }, + { + .peripheral = PERIPHERAL_CDSP, + .type = TYPE_DCI_CMD, + .name = "CDSP_DCI_CMD" + } +}; + +static void diag_state_open_smd(void *ctxt); +static void diag_state_close_smd(void *ctxt); +static void smd_notify(void *ctxt, unsigned event); +static int diag_smd_write(void *ctxt, unsigned char *buf, int len); +static int diag_smd_read(void *ctxt, unsigned char *buf, int buf_len); +static void diag_smd_queue_read(void *ctxt); + +static struct diag_peripheral_ops smd_ops = { + .open = diag_state_open_smd, + .close = diag_state_close_smd, + .write = diag_smd_write, + .read = diag_smd_read, + .queue_read = diag_smd_queue_read +}; + +static void diag_state_open_smd(void *ctxt) +{ + struct diag_smd_info *smd_info = NULL; + + if (!ctxt) + return; + + smd_info = (struct diag_smd_info *)(ctxt); + atomic_set(&smd_info->diag_state, 1); + DIAG_LOG(DIAG_DEBUG_PERIPHERALS, + "%s setting diag state to 1", smd_info->name); +} + +static void diag_state_close_smd(void *ctxt) +{ + struct diag_smd_info *smd_info = NULL; + + if (!ctxt) + return; + + smd_info = (struct diag_smd_info *)(ctxt); + atomic_set(&smd_info->diag_state, 0); + DIAG_LOG(DIAG_DEBUG_PERIPHERALS, + "%s setting diag state to 0", smd_info->name); + wake_up_interruptible(&smd_info->read_wait_q); + flush_workqueue(smd_info->wq); +} + +static int smd_channel_probe(struct platform_device *pdev, uint8_t type) +{ + int r = 0; + int index = -1; + const char *channel_name = NULL; + struct diag_smd_info *smd_info = NULL; + + switch (pdev->id) { + case SMD_APPS_MODEM: + index = PERIPHERAL_MODEM; + break; + case SMD_APPS_QDSP: + index = PERIPHERAL_LPASS; + break; + case SMD_APPS_WCNSS: + index = PERIPHERAL_WCNSS; + break; + case SMD_APPS_DSPS: + index = PERIPHERAL_SENSORS; + break; + default: + pr_debug("diag: In %s Received probe for invalid index %d", + __func__, pdev->id); + return -EINVAL; + } + + switch (type) { + case TYPE_DATA: + smd_info = &smd_data[index]; + channel_name = "DIAG"; + break; + case TYPE_CNTL: + smd_info = &smd_cntl[index]; + channel_name = "DIAG_CNTL"; + break; + case TYPE_CMD: + smd_info = &smd_cmd[index]; + channel_name = "DIAG_CMD"; + break; + case TYPE_DCI: + smd_info = &smd_dci[index]; + channel_name = "DIAG_2"; + break; + case TYPE_DCI_CMD: + smd_info = &smd_dci_cmd[index]; + channel_name = "DIAG_2_CMD"; + break; + default: + return -EINVAL; + } + + if (index == PERIPHERAL_WCNSS && type == TYPE_DATA) + channel_name = "APPS_RIVA_DATA"; + else if (index == PERIPHERAL_WCNSS && type == TYPE_CNTL) + channel_name = "APPS_RIVA_CTRL"; + + if (!channel_name || !smd_info) + return -EIO; + + r = smd_named_open_on_edge(channel_name, pdev->id, &smd_info->hdl, + smd_info, smd_notify); + + pm_runtime_set_active(&pdev->dev); + pm_runtime_enable(&pdev->dev); + pr_debug("diag: In %s, SMD port probed %s, id = %d, r = %d\n", + __func__, smd_info->name, pdev->id, r); + + return 0; +} + +static int smd_data_probe(struct platform_device *pdev) +{ + return smd_channel_probe(pdev, TYPE_DATA); +} + +static int smd_cntl_probe(struct platform_device *pdev) +{ + return smd_channel_probe(pdev, TYPE_CNTL); +} + +static int smd_cmd_probe(struct platform_device *pdev) +{ + return smd_channel_probe(pdev, TYPE_CMD); +} + +static int smd_dci_probe(struct platform_device *pdev) +{ + return smd_channel_probe(pdev, TYPE_DCI); +} + +static int smd_dci_cmd_probe(struct platform_device *pdev) +{ + return smd_channel_probe(pdev, TYPE_DCI_CMD); +} + +static int smd_runtime_suspend(struct device *dev) +{ + dev_dbg(dev, "pm_runtime: suspending...\n"); + return 0; +} + +static int smd_runtime_resume(struct device *dev) +{ + dev_dbg(dev, "pm_runtime: resuming...\n"); + return 0; +} + +static const struct dev_pm_ops smd_dev_pm_ops = { + .runtime_suspend = smd_runtime_suspend, + .runtime_resume = smd_runtime_resume, +}; + +static struct platform_driver diag_smd_ch_driver = { + .probe = smd_data_probe, + .driver = { + .name = "DIAG", + .owner = THIS_MODULE, + .pm = &smd_dev_pm_ops, + }, +}; + +static struct platform_driver diag_smd_lite_driver = { + .probe = smd_data_probe, + .driver = { + .name = "APPS_RIVA_DATA", + .owner = THIS_MODULE, + .pm = &smd_dev_pm_ops, + }, +}; + +static struct platform_driver diag_smd_cntl_driver = { + .probe = smd_cntl_probe, + .driver = { + .name = "DIAG_CNTL", + .owner = THIS_MODULE, + .pm = &smd_dev_pm_ops, + }, +}; + +static struct platform_driver diag_smd_lite_cntl_driver = { + .probe = smd_cntl_probe, + .driver = { + .name = "APPS_RIVA_CTRL", + .owner = THIS_MODULE, + .pm = &smd_dev_pm_ops, + }, +}; + +static struct platform_driver diag_smd_lite_cmd_driver = { + .probe = smd_cmd_probe, + .driver = { + .name = "DIAG_CMD", + .owner = THIS_MODULE, + .pm = &smd_dev_pm_ops, + } +}; + +static struct platform_driver diag_smd_dci_driver = { + .probe = smd_dci_probe, + .driver = { + .name = "DIAG_2", + .owner = THIS_MODULE, + .pm = &smd_dev_pm_ops, + }, +}; + +static struct platform_driver diag_smd_dci_cmd_driver = { + .probe = smd_dci_cmd_probe, + .driver = { + .name = "DIAG_2_CMD", + .owner = THIS_MODULE, + .pm = &smd_dev_pm_ops, + }, +}; + +static void smd_open_work_fn(struct work_struct *work) +{ + struct diag_smd_info *smd_info = container_of(work, + struct diag_smd_info, + open_work); + if (!smd_info->inited) + return; + + diagfwd_channel_open(smd_info->fwd_ctxt); + diagfwd_late_open(smd_info->fwd_ctxt); + DIAG_LOG(DIAG_DEBUG_PERIPHERALS, "%s exiting\n", + smd_info->name); +} + +static void smd_close_work_fn(struct work_struct *work) +{ + struct diag_smd_info *smd_info = container_of(work, + struct diag_smd_info, + close_work); + if (!smd_info->inited) + return; + + diagfwd_channel_close(smd_info->fwd_ctxt); + wake_up_interruptible(&smd_info->read_wait_q); + DIAG_LOG(DIAG_DEBUG_PERIPHERALS, "%s exiting\n", + smd_info->name); +} + +static void smd_read_work_fn(struct work_struct *work) +{ + struct diag_smd_info *smd_info = container_of(work, + struct diag_smd_info, + read_work); + if (!smd_info->inited) { + diag_ws_release(); + return; + } + + diagfwd_channel_read(smd_info->fwd_ctxt); +} + +static void diag_smd_queue_read(void *ctxt) +{ + struct diag_smd_info *smd_info = NULL; + + if (!ctxt) + return; + + smd_info = (struct diag_smd_info *)ctxt; + if (smd_info->inited && atomic_read(&smd_info->opened) && + smd_info->hdl) { + wake_up_interruptible(&smd_info->read_wait_q); + queue_work(smd_info->wq, &(smd_info->read_work)); + } +} +int diag_smd_check_state(void *ctxt) +{ + struct diag_smd_info *info = NULL; + + if (!ctxt) + return 0; + + info = (struct diag_smd_info *)ctxt; + return (int)(atomic_read(&info->diag_state)); +} +void diag_smd_invalidate(void *ctxt, struct diagfwd_info *fwd_ctxt) +{ + struct diag_smd_info *smd_info = NULL; + void *prev = NULL; + + if (!ctxt || !fwd_ctxt) + return; + + smd_info = (struct diag_smd_info *)ctxt; + prev = smd_info->fwd_ctxt; + smd_info->fwd_ctxt = fwd_ctxt; + DIAG_LOG(DIAG_DEBUG_PERIPHERALS, "%s prev: %pK fwd_ctxt: %pK\n", + smd_info->name, prev, smd_info->fwd_ctxt); +} + +static void __diag_smd_init(struct diag_smd_info *smd_info) +{ + char wq_name[DIAG_SMD_NAME_SZ + 10]; + if (!smd_info) + return; + + init_waitqueue_head(&smd_info->read_wait_q); + mutex_init(&smd_info->lock); + strlcpy(wq_name, "DIAG_SMD_", 10); + strlcat(wq_name, smd_info->name, sizeof(smd_info->name)); + smd_info->wq = create_singlethread_workqueue(wq_name); + if (!smd_info->wq) { + pr_err("diag: In %s, unable to create workqueue for smd channel %s\n", + __func__, smd_info->name); + return; + } + INIT_WORK(&(smd_info->open_work), smd_open_work_fn); + INIT_WORK(&(smd_info->close_work), smd_close_work_fn); + INIT_WORK(&(smd_info->read_work), smd_read_work_fn); + smd_info->fifo_size = 0; + smd_info->hdl = NULL; + smd_info->fwd_ctxt = NULL; + atomic_set(&smd_info->opened, 0); + atomic_set(&smd_info->diag_state, 0); + + DIAG_LOG(DIAG_DEBUG_PERIPHERALS, "%s initialized fwd_ctxt: %pK\n", + smd_info->name, smd_info->fwd_ctxt); +} + +int diag_smd_init(void) +{ + uint8_t peripheral; + struct diag_smd_info *smd_info = NULL; + + for (peripheral = 0; peripheral < NUM_PERIPHERALS; peripheral++) { + smd_info = &smd_cntl[peripheral]; + __diag_smd_init(smd_info); + diagfwd_cntl_register(TRANSPORT_SMD, smd_info->peripheral, + (void *)smd_info, &smd_ops, + &smd_info->fwd_ctxt); + smd_info->inited = 1; + __diag_smd_init(&smd_data[peripheral]); + __diag_smd_init(&smd_cmd[peripheral]); + __diag_smd_init(&smd_dci[peripheral]); + __diag_smd_init(&smd_dci_cmd[peripheral]); + } + + platform_driver_register(&diag_smd_cntl_driver); + platform_driver_register(&diag_smd_lite_cntl_driver); + platform_driver_register(&diag_smd_ch_driver); + platform_driver_register(&diag_smd_lite_driver); + platform_driver_register(&diag_smd_lite_cmd_driver); + platform_driver_register(&diag_smd_dci_driver); + platform_driver_register(&diag_smd_dci_cmd_driver); + + return 0; +} + +static void smd_late_init(struct diag_smd_info *smd_info) +{ + struct diagfwd_info *fwd_info = NULL; + if (!smd_info) + return; + + DIAG_LOG(DIAG_DEBUG_PERIPHERALS, "%s entering\n", + smd_info->name); + + diagfwd_register(TRANSPORT_SMD, smd_info->peripheral, smd_info->type, + (void *)smd_info, &smd_ops, &smd_info->fwd_ctxt); + fwd_info = smd_info->fwd_ctxt; + smd_info->inited = 1; + /* + * The channel is already open by the probe call as a result of other + * peripheral. Inform the diag fwd layer that the channel is open. + */ + if (atomic_read(&smd_info->opened)) + diagfwd_channel_open(smd_info->fwd_ctxt); + + DIAG_LOG(DIAG_DEBUG_PERIPHERALS, "%s exiting\n", + smd_info->name); +} + +int diag_smd_init_peripheral(uint8_t peripheral) +{ + if (peripheral >= NUM_PERIPHERALS) { + pr_err("diag: In %s, invalid peripheral %d\n", + __func__, peripheral); + return -EINVAL; + } + + smd_late_init(&smd_data[peripheral]); + smd_late_init(&smd_dci[peripheral]); + smd_late_init(&smd_cmd[peripheral]); + smd_late_init(&smd_dci_cmd[peripheral]); + + return 0; +} + +static void __diag_smd_exit(struct diag_smd_info *smd_info) +{ + if (!smd_info) + return; + + DIAG_LOG(DIAG_DEBUG_PERIPHERALS, "%s entering\n", + smd_info->name); + + diagfwd_deregister(smd_info->peripheral, smd_info->type, + (void *)smd_info); + smd_info->fwd_ctxt = NULL; + smd_info->hdl = NULL; + if (smd_info->wq) + destroy_workqueue(smd_info->wq); + + DIAG_LOG(DIAG_DEBUG_PERIPHERALS, "%s exiting\n", + smd_info->name); +} + +void diag_smd_early_exit(void) +{ + int i = 0; + + for (i = 0; i < NUM_PERIPHERALS; i++) + __diag_smd_exit(&smd_cntl[i]); + + platform_driver_unregister(&diag_smd_cntl_driver); + platform_driver_unregister(&diag_smd_lite_cntl_driver); +} + +void diag_smd_exit(void) +{ + int i = 0; + + for (i = 0; i < NUM_PERIPHERALS; i++) { + __diag_smd_exit(&smd_data[i]); + __diag_smd_exit(&smd_cmd[i]); + __diag_smd_exit(&smd_dci[i]); + __diag_smd_exit(&smd_dci_cmd[i]); + } + + platform_driver_unregister(&diag_smd_ch_driver); + platform_driver_unregister(&diag_smd_lite_driver); + platform_driver_unregister(&diag_smd_lite_cmd_driver); + platform_driver_unregister(&diag_smd_dci_driver); + platform_driver_unregister(&diag_smd_dci_cmd_driver); +} + +static int diag_smd_write_ext(struct diag_smd_info *smd_info, + unsigned char *buf, int len) +{ + int err = 0; + int offset = 0; + int write_len = 0; + int retry_count = 0; + int max_retries = 3; + uint8_t avail = 0; + + if (!smd_info || !buf || len <= 0) { + pr_err_ratelimited("diag: In %s, invalid params, smd_info: %pK, buf: %pK, len: %d\n", + __func__, smd_info, buf, len); + return -EINVAL; + } + + if (!smd_info->inited || !smd_info->hdl || + !atomic_read(&smd_info->opened)) + return -ENODEV; + + mutex_lock(&smd_info->lock); + err = smd_write_start(smd_info->hdl, len); + if (err) { + pr_err_ratelimited("diag: In %s, error calling smd_write_start, peripheral: %d, err: %d\n", + __func__, smd_info->peripheral, err); + goto fail; + } + + while (offset < len) { + retry_count = 0; + do { + if (smd_write_segment_avail(smd_info->hdl)) { + avail = 1; + break; + } + /* + * The channel maybe busy - the FIFO can be full. Retry + * after sometime. The value of 10000 was chosen + * emprically as the optimal value for the peripherals + * to read data from the SMD channel. + */ + usleep_range(10000, 10100); + retry_count++; + } while (retry_count < max_retries); + + if (!avail) { + err = -EAGAIN; + goto fail; + } + + write_len = smd_write_segment(smd_info->hdl, buf + offset, + (len - offset)); + offset += write_len; + write_len = 0; + } + + err = smd_write_end(smd_info->hdl); + if (err) { + pr_err_ratelimited("diag: In %s, error calling smd_write_end, peripheral: %d, err: %d\n", + __func__, smd_info->peripheral, err); + goto fail; + } + +fail: + mutex_unlock(&smd_info->lock); + DIAG_LOG(DIAG_DEBUG_PERIPHERALS, + "%s wrote to channel, write_len: %d, err: %d\n", + smd_info->name, offset, err); + return err; +} + +static int diag_smd_write(void *ctxt, unsigned char *buf, int len) +{ + int write_len = 0; + int retry_count = 0; + int max_retries = 3; + struct diag_smd_info *smd_info = NULL; + + if (!ctxt || !buf) + return -EIO; + + smd_info = (struct diag_smd_info *)ctxt; + if (!smd_info || !buf || len <= 0) { + pr_err_ratelimited("diag: In %s, invalid params, smd_info: %pK, buf: %pK, len: %d\n", + __func__, smd_info, buf, len); + return -EINVAL; + } + + if (!smd_info->inited || !smd_info->hdl || + !atomic_read(&smd_info->opened)) + return -ENODEV; + + if (len > smd_info->fifo_size) + return diag_smd_write_ext(smd_info, buf, len); + + do { + mutex_lock(&smd_info->lock); + write_len = smd_write(smd_info->hdl, buf, len); + mutex_unlock(&smd_info->lock); + if (write_len == len) + break; + /* + * The channel maybe busy - the FIFO can be full. Retry after + * sometime. The value of 10000 was chosen emprically as the + * optimal value for the peripherals to read data from the SMD + * channel. + */ + usleep_range(10000, 10100); + retry_count++; + } while (retry_count < max_retries); + + DIAG_LOG(DIAG_DEBUG_PERIPHERALS, "%s wrote to channel, write_len: %d\n", + smd_info->name, write_len); + + if (write_len != len) + return -ENOMEM; + + return 0; +} + +static int diag_smd_read(void *ctxt, unsigned char *buf, int buf_len) +{ + int pkt_len = 0; + int err = 0; + int total_recd_partial = 0; + int total_recd = 0; + uint8_t buf_full = 0; + unsigned char *temp_buf = NULL; + uint32_t read_len = 0; + struct diag_smd_info *smd_info = NULL; + + if (!ctxt || !buf || buf_len <= 0) + return -EIO; + + smd_info = (struct diag_smd_info *)ctxt; + if (!smd_info->hdl || !smd_info->inited || + !atomic_read(&smd_info->opened)) + return -EIO; + + /* + * Always try to read the data if notification is received from smd + * In case if packet size is 0 release the wake source hold earlier + */ + err = wait_event_interruptible(smd_info->read_wait_q, + (smd_info->hdl != NULL) && + (atomic_read(&smd_info->opened) == 1)); + if (err) { + diagfwd_channel_read_done(smd_info->fwd_ctxt, buf, 0); + return -ERESTARTSYS; + } + + /* + * Reset the buffers. Also release the wake source hold earlier. + */ + if (atomic_read(&smd_info->diag_state) == 0) { + DIAG_LOG(DIAG_DEBUG_PERIPHERALS, + "%s closing read thread. diag state is closed\n", + smd_info->name); + diagfwd_channel_read_done(smd_info->fwd_ctxt, buf, 0); + return 0; + } + + if (!smd_info->hdl || !atomic_read(&smd_info->opened)) { + DIAG_LOG(DIAG_DEBUG_PERIPHERALS, + "%s stopping read, hdl: %pK, opened: %d\n", + smd_info->name, smd_info->hdl, + atomic_read(&smd_info->opened)); + goto fail_return; + } + + do { + total_recd_partial = 0; + temp_buf = buf + total_recd; + pkt_len = smd_cur_packet_size(smd_info->hdl); + if (pkt_len <= 0) + break; + + if (total_recd + pkt_len > buf_len) { + buf_full = 1; + break; + } + + while (total_recd_partial < pkt_len) { + read_len = smd_read_avail(smd_info->hdl); + if (!read_len) { + wait_event_interruptible(smd_info->read_wait_q, + ((atomic_read(&smd_info->opened)) && + smd_read_avail(smd_info->hdl))); + + if (!smd_info->hdl || + !atomic_read(&smd_info->opened)) { + DIAG_LOG(DIAG_DEBUG_PERIPHERALS, + "%s exiting from wait", + smd_info->name); + goto fail_return; + } + } + + if (pkt_len < read_len) + goto fail_return; + + smd_read(smd_info->hdl, temp_buf, read_len); + total_recd_partial += read_len; + total_recd += read_len; + temp_buf += read_len; + } + } while (pkt_len > 0); + + if ((smd_info->type == TYPE_DATA && pkt_len) || buf_full) + err = queue_work(smd_info->wq, &(smd_info->read_work)); + + if (total_recd > 0) { + DIAG_LOG(DIAG_DEBUG_PERIPHERALS, "%s read total bytes: %d\n", + smd_info->name, total_recd); + diagfwd_channel_read_done(smd_info->fwd_ctxt, buf, total_recd); + } else { + DIAG_LOG(DIAG_DEBUG_PERIPHERALS, "%s error in read, err: %d\n", + smd_info->name, total_recd); + goto fail_return; + } + return 0; + +fail_return: + diagfwd_channel_read_done(smd_info->fwd_ctxt, buf, 0); + return -EINVAL; +} + +static void smd_notify(void *ctxt, unsigned event) +{ + struct diag_smd_info *smd_info = NULL; + + smd_info = (struct diag_smd_info *)ctxt; + if (!smd_info) + return; + + switch (event) { + case SMD_EVENT_OPEN: + atomic_set(&smd_info->opened, 1); + smd_info->fifo_size = smd_write_avail(smd_info->hdl); + DIAG_LOG(DIAG_DEBUG_PERIPHERALS, "%s channel opened\n", + smd_info->name); + queue_work(smd_info->wq, &(smd_info->open_work)); + break; + case SMD_EVENT_CLOSE: + atomic_set(&smd_info->opened, 0); + DIAG_LOG(DIAG_DEBUG_PERIPHERALS, "%s channel closed\n", + smd_info->name); + queue_work(smd_info->wq, &(smd_info->close_work)); + break; + case SMD_EVENT_DATA: + diag_ws_on_notify(); + queue_work(smd_info->wq, &(smd_info->read_work)); + break; + } + + wake_up_interruptible(&smd_info->read_wait_q); +} + diff -Nruw linux-4.4.115-fbx/drivers/char/diag./diagfwd_smd.h linux-4.4.115-fbx/drivers/char/diag/diagfwd_smd.h --- linux-4.4.115-fbx/drivers/char/diag./diagfwd_smd.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-4.4.115-fbx/drivers/char/diag/diagfwd_smd.h 2019-01-22 16:16:22.963241516 +0100 @@ -0,0 +1,50 @@ +/* Copyright (c) 2015, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef DIAGFWD_SMD_H +#define DIAGFWD_SMD_H + +#define DIAG_SMD_NAME_SZ 24 +#define SMD_DRAIN_BUF_SIZE 4096 + +struct diag_smd_info { + uint8_t peripheral; + uint8_t type; + uint8_t inited; + atomic_t opened; + atomic_t diag_state; + uint32_t fifo_size; + smd_channel_t *hdl; + char name[DIAG_SMD_NAME_SZ]; + struct mutex lock; + wait_queue_head_t read_wait_q; + struct workqueue_struct *wq; + struct work_struct open_work; + struct work_struct close_work; + struct work_struct read_work; + struct diagfwd_info *fwd_ctxt; +}; + +extern struct diag_smd_info smd_data[NUM_PERIPHERALS]; +extern struct diag_smd_info smd_cntl[NUM_PERIPHERALS]; +extern struct diag_smd_info smd_dci[NUM_PERIPHERALS]; +extern struct diag_smd_info smd_cmd[NUM_PERIPHERALS]; +extern struct diag_smd_info smd_dci_cmd[NUM_PERIPHERALS]; + +int diag_smd_init_peripheral(uint8_t peripheral); +void diag_smd_exit(void); +int diag_smd_init(void); +void diag_smd_early_exit(void); +void diag_smd_invalidate(void *ctxt, struct diagfwd_info *fwd_ctxt); +int diag_smd_check_state(void *ctxt); + +#endif diff -Nruw linux-4.4.115-fbx/drivers/char/diag./diagfwd_socket.c linux-4.4.115-fbx/drivers/char/diag/diagfwd_socket.c --- linux-4.4.115-fbx/drivers/char/diag./diagfwd_socket.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-4.4.115-fbx/drivers/char/diag/diagfwd_socket.c 2019-01-22 16:16:22.963241516 +0100 @@ -0,0 +1,1238 @@ +/* Copyright (c) 2015-2017, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "diagchar.h" +#include "diagfwd.h" +#include "diagfwd_peripheral.h" +#include "diagfwd_socket.h" +#include "diag_ipc_logging.h" + +#include +#include + +#define DIAG_SVC_ID 0x1001 + +#define MODEM_INST_BASE 0 +#define LPASS_INST_BASE 64 +#define WCNSS_INST_BASE 128 +#define SENSORS_INST_BASE 192 +#define CDSP_INST_BASE 256 +#define WDSP_INST_BASE 320 + +#define INST_ID_CNTL 0 +#define INST_ID_CMD 1 +#define INST_ID_DATA 2 +#define INST_ID_DCI_CMD 3 +#define INST_ID_DCI 4 + +struct diag_cntl_socket_info *cntl_socket; +static uint64_t bootup_req[NUM_SOCKET_SUBSYSTEMS]; + +struct diag_socket_info socket_data[NUM_PERIPHERALS] = { + { + .peripheral = PERIPHERAL_MODEM, + .type = TYPE_DATA, + .name = "MODEM_DATA" + }, + { + .peripheral = PERIPHERAL_LPASS, + .type = TYPE_DATA, + .name = "LPASS_DATA" + }, + { + .peripheral = PERIPHERAL_WCNSS, + .type = TYPE_DATA, + .name = "WCNSS_DATA" + }, + { + .peripheral = PERIPHERAL_SENSORS, + .type = TYPE_DATA, + .name = "SENSORS_DATA" + }, + { + .peripheral = PERIPHERAL_WDSP, + .type = TYPE_DATA, + .name = "DIAG_DATA" + }, + { + .peripheral = PERIPHERAL_CDSP, + .type = TYPE_DATA, + .name = "CDSP_DATA" + } +}; + +struct diag_socket_info socket_cntl[NUM_PERIPHERALS] = { + { + .peripheral = PERIPHERAL_MODEM, + .type = TYPE_CNTL, + .name = "MODEM_CNTL" + }, + { + .peripheral = PERIPHERAL_LPASS, + .type = TYPE_CNTL, + .name = "LPASS_CNTL" + }, + { + .peripheral = PERIPHERAL_WCNSS, + .type = TYPE_CNTL, + .name = "WCNSS_CNTL" + }, + { + .peripheral = PERIPHERAL_SENSORS, + .type = TYPE_CNTL, + .name = "SENSORS_CNTL" + }, + { + .peripheral = PERIPHERAL_WDSP, + .type = TYPE_CNTL, + .name = "DIAG_CTRL" + }, + { + .peripheral = PERIPHERAL_CDSP, + .type = TYPE_CNTL, + .name = "CDSP_CNTL" + } +}; + +struct diag_socket_info socket_dci[NUM_PERIPHERALS] = { + { + .peripheral = PERIPHERAL_MODEM, + .type = TYPE_DCI, + .name = "MODEM_DCI" + }, + { + .peripheral = PERIPHERAL_LPASS, + .type = TYPE_DCI, + .name = "LPASS_DCI" + }, + { + .peripheral = PERIPHERAL_WCNSS, + .type = TYPE_DCI, + .name = "WCNSS_DCI" + }, + { + .peripheral = PERIPHERAL_SENSORS, + .type = TYPE_DCI, + .name = "SENSORS_DCI" + }, + { + .peripheral = PERIPHERAL_WDSP, + .type = TYPE_DCI, + .name = "DIAG_DCI_DATA" + }, + { + .peripheral = PERIPHERAL_CDSP, + .type = TYPE_DCI, + .name = "CDSP_DCI" + } +}; + +struct diag_socket_info socket_cmd[NUM_PERIPHERALS] = { + { + .peripheral = PERIPHERAL_MODEM, + .type = TYPE_CMD, + .name = "MODEM_CMD" + }, + { + .peripheral = PERIPHERAL_LPASS, + .type = TYPE_CMD, + .name = "LPASS_CMD" + }, + { + .peripheral = PERIPHERAL_WCNSS, + .type = TYPE_CMD, + .name = "WCNSS_CMD" + }, + { + .peripheral = PERIPHERAL_SENSORS, + .type = TYPE_CMD, + .name = "SENSORS_CMD" + }, + { + .peripheral = PERIPHERAL_WDSP, + .type = TYPE_CMD, + .name = "DIAG_CMD" + }, + { + .peripheral = PERIPHERAL_CDSP, + .type = TYPE_CMD, + .name = "CDSP_CMD" + } + +}; + +struct diag_socket_info socket_dci_cmd[NUM_PERIPHERALS] = { + { + .peripheral = PERIPHERAL_MODEM, + .type = TYPE_DCI_CMD, + .name = "MODEM_DCI_CMD" + }, + { + .peripheral = PERIPHERAL_LPASS, + .type = TYPE_DCI_CMD, + .name = "LPASS_DCI_CMD" + }, + { + .peripheral = PERIPHERAL_WCNSS, + .type = TYPE_DCI_CMD, + .name = "WCNSS_DCI_CMD" + }, + { + .peripheral = PERIPHERAL_SENSORS, + .type = TYPE_DCI_CMD, + .name = "SENSORS_DCI_CMD" + }, + { + .peripheral = PERIPHERAL_WDSP, + .type = TYPE_DCI_CMD, + .name = "DIAG_DCI_CMD" + }, + { + .peripheral = PERIPHERAL_CDSP, + .type = TYPE_DCI_CMD, + .name = "CDSP_DCI_CMD" + }, +}; + +static void diag_state_open_socket(void *ctxt); +static void diag_state_close_socket(void *ctxt); +static int diag_socket_write(void *ctxt, unsigned char *buf, int len); +static int diag_socket_read(void *ctxt, unsigned char *buf, int buf_len); +static void diag_socket_queue_read(void *ctxt); +static void socket_init_work_fn(struct work_struct *work); +static int socket_ready_notify(struct notifier_block *nb, + unsigned long action, void *data); + +static struct diag_peripheral_ops socket_ops = { + .open = diag_state_open_socket, + .close = diag_state_close_socket, + .write = diag_socket_write, + .read = diag_socket_read, + .queue_read = diag_socket_queue_read +}; + +static struct notifier_block socket_notify = { + .notifier_call = socket_ready_notify, +}; + +static void diag_state_open_socket(void *ctxt) +{ + struct diag_socket_info *info = NULL; + + if (!ctxt) + return; + + info = (struct diag_socket_info *)(ctxt); + atomic_set(&info->diag_state, 1); + DIAG_LOG(DIAG_DEBUG_PERIPHERALS, + "%s setting diag state to 1", info->name); +} + +static void diag_state_close_socket(void *ctxt) +{ + struct diag_socket_info *info = NULL; + + if (!ctxt) + return; + + info = (struct diag_socket_info *)(ctxt); + atomic_set(&info->diag_state, 0); + DIAG_LOG(DIAG_DEBUG_PERIPHERALS, + "%s setting diag state to 0", info->name); + wake_up_interruptible(&info->read_wait_q); + flush_workqueue(info->wq); +} + +static void socket_data_ready(struct sock *sk_ptr) +{ + unsigned long flags; + struct diag_socket_info *info = NULL; + + if (!sk_ptr) { + pr_err_ratelimited("diag: In %s, invalid sk_ptr", __func__); + return; + } + + info = (struct diag_socket_info *)(sk_ptr->sk_user_data); + if (!info) { + pr_err_ratelimited("diag: In %s, invalid info\n", __func__); + return; + } + + spin_lock_irqsave(&info->lock, flags); + info->data_ready++; + spin_unlock_irqrestore(&info->lock, flags); + diag_ws_on_notify(); + + queue_work(info->wq, &(info->read_work)); + wake_up_interruptible(&info->read_wait_q); + return; +} + +static void cntl_socket_data_ready(struct sock *sk_ptr) +{ + if (!sk_ptr || !cntl_socket) { + pr_err_ratelimited("diag: In %s, invalid ptrs. sk_ptr: %pK cntl_socket: %pK\n", + __func__, sk_ptr, cntl_socket); + return; + } + + atomic_inc(&cntl_socket->data_ready); + wake_up_interruptible(&cntl_socket->read_wait_q); + queue_work(cntl_socket->wq, &(cntl_socket->read_work)); +} + +static void socket_flow_cntl(struct sock *sk_ptr) +{ + struct diag_socket_info *info = NULL; + + if (!sk_ptr) + return; + + info = (struct diag_socket_info *)(sk_ptr->sk_user_data); + if (!info) { + pr_err_ratelimited("diag: In %s, invalid info\n", __func__); + return; + } + + atomic_inc(&info->flow_cnt); + DIAG_LOG(DIAG_DEBUG_PERIPHERALS, "%s flow controlled\n", info->name); + pr_debug("diag: In %s, channel %s flow controlled\n", + __func__, info->name); +} + +static int lookup_server(struct diag_socket_info *info) +{ + int ret = 0; + struct server_lookup_args *args = NULL; + struct sockaddr_msm_ipc *srv_addr = NULL; + + if (!info) + return -EINVAL; + + args = kzalloc((sizeof(struct server_lookup_args) + + sizeof(struct msm_ipc_server_info)), GFP_KERNEL); + if (!args) + return -ENOMEM; + kmemleak_not_leak(args); + + args->lookup_mask = 0xFFFFFFFF; + args->port_name.service = info->svc_id; + args->port_name.instance = info->ins_id; + args->num_entries_in_array = 1; + args->num_entries_found = 0; + + ret = kernel_sock_ioctl(info->hdl, IPC_ROUTER_IOCTL_LOOKUP_SERVER, + (unsigned long)args); + if (ret < 0) { + pr_err("diag: In %s, cannot find service for %s\n", __func__, + info->name); + kfree(args); + return -EFAULT; + } + + srv_addr = &info->remote_addr; + srv_addr->family = AF_MSM_IPC; + srv_addr->address.addrtype = MSM_IPC_ADDR_ID; + srv_addr->address.addr.port_addr.node_id = args->srv_info[0].node_id; + srv_addr->address.addr.port_addr.port_id = args->srv_info[0].port_id; + ret = args->num_entries_found; + kfree(args); + if (ret < 1) + return -EIO; + DIAG_LOG(DIAG_DEBUG_PERIPHERALS, "%s found server node: %d port: %d", + info->name, srv_addr->address.addr.port_addr.node_id, + srv_addr->address.addr.port_addr.port_id); + return 0; +} + +static void __socket_open_channel(struct diag_socket_info *info) +{ + if (!info) + return; + + if (!info->inited) { + pr_debug("diag: In %s, socket %s is not initialized\n", + __func__, info->name); + return; + } + + if (atomic_read(&info->opened)) { + pr_debug("diag: In %s, socket %s already opened\n", + __func__, info->name); + return; + } + + atomic_set(&info->opened, 1); + diagfwd_channel_open(info->fwd_ctxt); +} + +static void socket_open_client(struct diag_socket_info *info) +{ + int ret = 0; + + if (!info || info->port_type != PORT_TYPE_CLIENT) + return; + + ret = sock_create(AF_MSM_IPC, SOCK_DGRAM, 0, &info->hdl); + if (ret < 0 || !info->hdl) { + pr_err("diag: In %s, socket not initialized for %s\n", __func__, + info->name); + return; + } + + write_lock_bh(&info->hdl->sk->sk_callback_lock); + info->hdl->sk->sk_user_data = (void *)(info); + info->hdl->sk->sk_data_ready = socket_data_ready; + info->hdl->sk->sk_write_space = socket_flow_cntl; + write_unlock_bh(&info->hdl->sk->sk_callback_lock); + ret = lookup_server(info); + if (ret) { + pr_err("diag: In %s, failed to lookup server, ret: %d\n", + __func__, ret); + return; + } + __socket_open_channel(info); + DIAG_LOG(DIAG_DEBUG_PERIPHERALS, "%s opened client\n", info->name); +} + +static void socket_open_server(struct diag_socket_info *info) +{ + int ret = 0; + struct sockaddr_msm_ipc srv_addr = { 0 }; + + if (!info) + return; + + ret = sock_create(AF_MSM_IPC, SOCK_DGRAM, 0, &info->hdl); + if (ret < 0 || !info->hdl) { + pr_err("diag: In %s, socket not initialized for %s\n", __func__, + info->name); + return; + } + + write_lock_bh(&info->hdl->sk->sk_callback_lock); + info->hdl->sk->sk_user_data = (void *)(info); + info->hdl->sk->sk_data_ready = socket_data_ready; + info->hdl->sk->sk_write_space = socket_flow_cntl; + write_unlock_bh(&info->hdl->sk->sk_callback_lock); + + srv_addr.family = AF_MSM_IPC; + srv_addr.address.addrtype = MSM_IPC_ADDR_NAME; + srv_addr.address.addr.port_name.service = info->svc_id; + srv_addr.address.addr.port_name.instance = info->ins_id; + + ret = kernel_bind(info->hdl, (struct sockaddr *)&srv_addr, + sizeof(srv_addr)); + if (ret) { + pr_err("diag: In %s, failed to bind, ch: %s, svc_id: %d ins_id: %d, err: %d\n", + __func__, info->name, info->svc_id, info->ins_id, ret); + return; + } + DIAG_LOG(DIAG_DEBUG_PERIPHERALS, "%s opened server svc: %d ins: %d", + info->name, info->svc_id, info->ins_id); +} + +static void socket_init_work_fn(struct work_struct *work) +{ + struct diag_socket_info *info = container_of(work, + struct diag_socket_info, + init_work); + if (!info) + return; + + if (!info->inited) { + pr_debug("diag: In %s, socket %s is not initialized\n", + __func__, info->name); + return; + } + + switch (info->port_type) { + case PORT_TYPE_SERVER: + socket_open_server(info); + break; + case PORT_TYPE_CLIENT: + socket_open_client(info); + break; + default: + pr_err("diag: In %s, unknown type %d\n", __func__, + info->port_type); + break; + } +} + +static void __socket_close_channel(struct diag_socket_info *info) +{ + if (!info || !info->hdl) + return; + + if (!atomic_read(&info->opened)) + return; + + if (bootup_req[info->peripheral] == PEPIPHERAL_SSR_UP) { + DIAG_LOG(DIAG_DEBUG_PERIPHERALS, + "diag: %s is up, stopping cleanup: bootup_req = %d\n", + info->name, (int)bootup_req[info->peripheral]); + return; + } + + memset(&info->remote_addr, 0, sizeof(struct sockaddr_msm_ipc)); + diagfwd_channel_close(info->fwd_ctxt); + + atomic_set(&info->opened, 0); + + /* Don't close the server. Server should always remain open */ + if (info->port_type != PORT_TYPE_SERVER) { + write_lock_bh(&info->hdl->sk->sk_callback_lock); + info->hdl->sk->sk_user_data = NULL; + info->hdl->sk->sk_data_ready = NULL; + write_unlock_bh(&info->hdl->sk->sk_callback_lock); + sock_release(info->hdl); + info->hdl = NULL; + wake_up_interruptible(&info->read_wait_q); + } + DIAG_LOG(DIAG_DEBUG_PERIPHERALS, "%s exiting\n", info->name); + + return; +} + +static void socket_close_channel(struct diag_socket_info *info) +{ + if (!info) + return; + + __socket_close_channel(info); + + DIAG_LOG(DIAG_DEBUG_PERIPHERALS, "%s exiting\n", info->name); +} + +static int cntl_socket_process_msg_server(uint32_t cmd, uint32_t svc_id, + uint32_t ins_id) +{ + uint8_t peripheral; + uint8_t found = 0; + struct diag_socket_info *info = NULL; + + for (peripheral = 0; peripheral < NUM_PERIPHERALS; peripheral++) { + info = &socket_cmd[peripheral]; + if ((svc_id == info->svc_id) && + (ins_id == info->ins_id)) { + found = 1; + break; + } + + info = &socket_dci_cmd[peripheral]; + if ((svc_id == info->svc_id) && + (ins_id == info->ins_id)) { + found = 1; + break; + } + } + + if (!found) + return -EIO; + + switch (cmd) { + case CNTL_CMD_NEW_SERVER: + DIAG_LOG(DIAG_DEBUG_PERIPHERALS, "%s received new server\n", + info->name); + diagfwd_register(TRANSPORT_SOCKET, info->peripheral, + info->type, (void *)info, &socket_ops, + &info->fwd_ctxt); + queue_work(info->wq, &(info->init_work)); + break; + case CNTL_CMD_REMOVE_SERVER: + DIAG_LOG(DIAG_DEBUG_PERIPHERALS, "%s received remove server\n", + info->name); + socket_close_channel(info); + break; + default: + return -EINVAL; + } + + return 0; +} + +static int cntl_socket_process_msg_client(uint32_t cmd, uint32_t node_id, + uint32_t port_id) +{ + uint8_t peripheral; + uint8_t found = 0; + struct diag_socket_info *info = NULL; + struct msm_ipc_port_addr remote_port = {0}; + + for (peripheral = 0; peripheral < NUM_PERIPHERALS; peripheral++) { + info = &socket_data[peripheral]; + remote_port = info->remote_addr.address.addr.port_addr; + if ((remote_port.node_id == node_id) && + (remote_port.port_id == port_id)) { + found = 1; + break; + } + + info = &socket_cntl[peripheral]; + remote_port = info->remote_addr.address.addr.port_addr; + if ((remote_port.node_id == node_id) && + (remote_port.port_id == port_id)) { + found = 1; + break; + } + + info = &socket_dci[peripheral]; + remote_port = info->remote_addr.address.addr.port_addr; + if ((remote_port.node_id == node_id) && + (remote_port.port_id == port_id)) { + found = 1; + break; + } + } + + if (!found) + return -EIO; + + switch (cmd) { + case CNTL_CMD_REMOVE_CLIENT: + DIAG_LOG(DIAG_DEBUG_PERIPHERALS, "%s received remove client\n", + info->name); + mutex_lock(&driver->diag_notifier_mutex); + socket_close_channel(info); + mutex_unlock(&driver->diag_notifier_mutex); + break; + default: + return -EINVAL; + } + + return 0; +} + +static int restart_notifier_cb(struct notifier_block *this, + unsigned long code, + void *data); + +struct restart_notifier_block { + unsigned processor; + char *name; + struct notifier_block nb; +}; + +static struct restart_notifier_block restart_notifiers[] = { + {SOCKET_MODEM, "modem", .nb.notifier_call = restart_notifier_cb}, + {SOCKET_ADSP, "adsp", .nb.notifier_call = restart_notifier_cb}, + {SOCKET_WCNSS, "wcnss", .nb.notifier_call = restart_notifier_cb}, + {SOCKET_SLPI, "slpi", .nb.notifier_call = restart_notifier_cb}, + {SOCKET_CDSP, "cdsp", .nb.notifier_call = restart_notifier_cb}, +}; + + +static void cntl_socket_read_work_fn(struct work_struct *work) +{ + union cntl_port_msg msg; + int ret = 0; + struct kvec iov = { 0 }; + struct msghdr read_msg = { 0 }; + + if (!cntl_socket) + return; + + ret = wait_event_interruptible(cntl_socket->read_wait_q, + (atomic_read(&cntl_socket->data_ready) > 0)); + if (ret) + return; + + do { + iov.iov_base = &msg; + iov.iov_len = sizeof(msg); + read_msg.msg_name = NULL; + read_msg.msg_namelen = 0; + ret = kernel_recvmsg(cntl_socket->hdl, &read_msg, &iov, 1, + sizeof(msg), MSG_DONTWAIT); + if (ret < 0) { + pr_debug("diag: In %s, Error recving data %d\n", + __func__, ret); + break; + } + + atomic_dec(&cntl_socket->data_ready); + + switch (msg.srv.cmd) { + case CNTL_CMD_NEW_SERVER: + case CNTL_CMD_REMOVE_SERVER: + cntl_socket_process_msg_server(msg.srv.cmd, + msg.srv.service, + msg.srv.instance); + break; + case CNTL_CMD_REMOVE_CLIENT: + cntl_socket_process_msg_client(msg.cli.cmd, + msg.cli.node_id, + msg.cli.port_id); + break; + } + } while (atomic_read(&cntl_socket->data_ready) > 0); +} + +static void socket_read_work_fn(struct work_struct *work) +{ + struct diag_socket_info *info = container_of(work, + struct diag_socket_info, + read_work); + + if (!info) + return; + + if (!atomic_read(&info->opened) && info->port_type == PORT_TYPE_SERVER) + diagfwd_buffers_init(info->fwd_ctxt); + + diagfwd_channel_read(info->fwd_ctxt); +} + +static void diag_socket_queue_read(void *ctxt) +{ + struct diag_socket_info *info = NULL; + + if (!ctxt) + return; + + info = (struct diag_socket_info *)ctxt; + if (info->hdl && info->wq) + queue_work(info->wq, &(info->read_work)); +} + +void diag_socket_invalidate(void *ctxt, struct diagfwd_info *fwd_ctxt) +{ + struct diag_socket_info *info = NULL; + + if (!ctxt || !fwd_ctxt) + return; + + info = (struct diag_socket_info *)ctxt; + info->fwd_ctxt = fwd_ctxt; +} + +int diag_socket_check_state(void *ctxt) +{ + struct diag_socket_info *info = NULL; + + if (!ctxt) + return 0; + + info = (struct diag_socket_info *)ctxt; + return (int)(atomic_read(&info->diag_state)); +} + +static void __diag_socket_init(struct diag_socket_info *info) +{ + uint16_t ins_base = 0; + uint16_t ins_offset = 0; + + char wq_name[DIAG_SOCKET_NAME_SZ + 10]; + if (!info) + return; + + init_waitqueue_head(&info->wait_q); + info->inited = 0; + atomic_set(&info->opened, 0); + atomic_set(&info->diag_state, 0); + info->pkt_len = 0; + info->pkt_read = 0; + info->hdl = NULL; + info->fwd_ctxt = NULL; + info->data_ready = 0; + atomic_set(&info->flow_cnt, 0); + spin_lock_init(&info->lock); + strlcpy(wq_name, "DIAG_SOCKET_", 10); + strlcat(wq_name, info->name, sizeof(info->name)); + init_waitqueue_head(&info->read_wait_q); + info->wq = create_singlethread_workqueue(wq_name); + if (!info->wq) { + pr_err("diag: In %s, unable to create workqueue for socket channel %s\n", + __func__, info->name); + return; + } + INIT_WORK(&(info->init_work), socket_init_work_fn); + INIT_WORK(&(info->read_work), socket_read_work_fn); + + switch (info->peripheral) { + case PERIPHERAL_MODEM: + ins_base = MODEM_INST_BASE; + break; + case PERIPHERAL_LPASS: + ins_base = LPASS_INST_BASE; + break; + case PERIPHERAL_WCNSS: + ins_base = WCNSS_INST_BASE; + break; + case PERIPHERAL_SENSORS: + ins_base = SENSORS_INST_BASE; + break; + case PERIPHERAL_WDSP: + ins_base = WDSP_INST_BASE; + break; + case PERIPHERAL_CDSP: + ins_base = CDSP_INST_BASE; + break; + } + + switch (info->type) { + case TYPE_DATA: + ins_offset = INST_ID_DATA; + info->port_type = PORT_TYPE_SERVER; + break; + case TYPE_CNTL: + ins_offset = INST_ID_CNTL; + info->port_type = PORT_TYPE_SERVER; + break; + case TYPE_DCI: + ins_offset = INST_ID_DCI; + info->port_type = PORT_TYPE_SERVER; + break; + case TYPE_CMD: + ins_offset = INST_ID_CMD; + info->port_type = PORT_TYPE_CLIENT; + break; + case TYPE_DCI_CMD: + ins_offset = INST_ID_DCI_CMD; + info->port_type = PORT_TYPE_CLIENT; + break; + } + + info->svc_id = DIAG_SVC_ID; + info->ins_id = ins_base + ins_offset; + info->inited = 1; +} + +static void cntl_socket_init_work_fn(struct work_struct *work) +{ + int ret = 0; + + if (!cntl_socket) + return; + + ret = sock_create(AF_MSM_IPC, SOCK_DGRAM, 0, &cntl_socket->hdl); + if (ret < 0 || !cntl_socket->hdl) { + pr_err("diag: In %s, cntl socket is not initialized, ret: %d\n", + __func__, ret); + return; + } + + write_lock_bh(&cntl_socket->hdl->sk->sk_callback_lock); + cntl_socket->hdl->sk->sk_user_data = (void *)cntl_socket; + cntl_socket->hdl->sk->sk_data_ready = cntl_socket_data_ready; + write_unlock_bh(&cntl_socket->hdl->sk->sk_callback_lock); + + ret = kernel_sock_ioctl(cntl_socket->hdl, + IPC_ROUTER_IOCTL_BIND_CONTROL_PORT, 0); + if (ret < 0) { + pr_err("diag: In %s Could not bind as control port, ret: %d\n", + __func__, ret); + } + + DIAG_LOG(DIAG_DEBUG_PERIPHERALS, "Initialized control sockets"); +} + +static int __diag_cntl_socket_init(void) +{ + cntl_socket = kzalloc(sizeof(struct diag_cntl_socket_info), GFP_KERNEL); + if (!cntl_socket) + return -ENOMEM; + + cntl_socket->svc_id = DIAG_SVC_ID; + cntl_socket->ins_id = 1; + atomic_set(&cntl_socket->data_ready, 0); + init_waitqueue_head(&cntl_socket->read_wait_q); + cntl_socket->wq = create_singlethread_workqueue("DIAG_CNTL_SOCKET"); + INIT_WORK(&(cntl_socket->read_work), cntl_socket_read_work_fn); + INIT_WORK(&(cntl_socket->init_work), cntl_socket_init_work_fn); + + return 0; +} + +int diag_socket_init(void) +{ + int err = 0; + int i; + int peripheral = 0; + void *handle; + struct diag_socket_info *info = NULL; + struct restart_notifier_block *nb; + + for (peripheral = 0; peripheral < NUM_PERIPHERALS; peripheral++) { + info = &socket_cntl[peripheral]; + __diag_socket_init(&socket_cntl[peripheral]); + + diagfwd_cntl_register(TRANSPORT_SOCKET, peripheral, + (void *)info, &socket_ops, &(info->fwd_ctxt)); + + __diag_socket_init(&socket_data[peripheral]); + __diag_socket_init(&socket_cmd[peripheral]); + __diag_socket_init(&socket_dci[peripheral]); + __diag_socket_init(&socket_dci_cmd[peripheral]); + } + + err = __diag_cntl_socket_init(); + if (err) { + pr_err("diag: Unable to open control sockets, err: %d\n", err); + goto fail; + } + + for (i = 0; i < ARRAY_SIZE(restart_notifiers); i++) { + nb = &restart_notifiers[i]; + if (nb) { + handle = subsys_notif_register_notifier(nb->name, + &nb->nb); + DIAG_LOG(DIAG_DEBUG_PERIPHERALS, + "%s: registering notifier for '%s', handle=%p\n", + __func__, nb->name, handle); + } + } + + register_ipcrtr_af_init_notifier(&socket_notify); +fail: + return err; +} + +static int socket_ready_notify(struct notifier_block *nb, + unsigned long action, void *data) +{ + uint8_t peripheral; + struct diag_socket_info *info = NULL; + + DIAG_LOG(DIAG_DEBUG_PERIPHERALS, "received notification from IPCR"); + + if (action != IPCRTR_AF_INIT) { + DIAG_LOG(DIAG_DEBUG_PERIPHERALS, + "action not recognized by diag %lu\n", action); + return 0; + } + + /* Initialize only the servers */ + for (peripheral = 0; peripheral < NUM_PERIPHERALS; peripheral++) { + info = &socket_cntl[peripheral]; + queue_work(info->wq, &(info->init_work)); + info = &socket_data[peripheral]; + queue_work(info->wq, &(info->init_work)); + info = &socket_dci[peripheral]; + queue_work(info->wq, &(info->init_work)); + } + DIAG_LOG(DIAG_DEBUG_PERIPHERALS, "Initialized all servers"); + + queue_work(cntl_socket->wq, &(cntl_socket->init_work)); + + return 0; +} + +static int restart_notifier_cb(struct notifier_block *this, unsigned long code, + void *_cmd) +{ + struct restart_notifier_block *notifier; + + notifier = container_of(this, + struct restart_notifier_block, nb); + if (!notifier) { + DIAG_LOG(DIAG_DEBUG_PERIPHERALS, + "diag: %s: invalid notifier block\n", __func__); + return NOTIFY_DONE; + } + + mutex_lock(&driver->diag_notifier_mutex); + DIAG_LOG(DIAG_DEBUG_PERIPHERALS, + "%s: ssr for processor %d ('%s')\n", + __func__, notifier->processor, notifier->name); + + switch (code) { + + case SUBSYS_BEFORE_SHUTDOWN: + DIAG_LOG(DIAG_DEBUG_PERIPHERALS, + "diag: %s: SUBSYS_BEFORE_SHUTDOWN\n", __func__); + bootup_req[notifier->processor] = PEPIPHERAL_SSR_DOWN; + break; + + case SUBSYS_AFTER_SHUTDOWN: + DIAG_LOG(DIAG_DEBUG_PERIPHERALS, + "diag: %s: SUBSYS_AFTER_SHUTDOWN\n", __func__); + break; + + case SUBSYS_BEFORE_POWERUP: + DIAG_LOG(DIAG_DEBUG_PERIPHERALS, + "diag: %s: SUBSYS_BEFORE_POWERUP\n", __func__); + break; + + case SUBSYS_AFTER_POWERUP: + DIAG_LOG(DIAG_DEBUG_PERIPHERALS, + "diag: %s: SUBSYS_AFTER_POWERUP\n", __func__); + if (!bootup_req[notifier->processor]) { + bootup_req[notifier->processor] = PEPIPHERAL_SSR_DOWN; + break; + } + bootup_req[notifier->processor] = PEPIPHERAL_SSR_UP; + break; + + default: + DIAG_LOG(DIAG_DEBUG_PERIPHERALS, + "diag: code: %lu\n", code); + break; + } + mutex_unlock(&driver->diag_notifier_mutex); + DIAG_LOG(DIAG_DEBUG_PERIPHERALS, + "diag: bootup_req[%s] = %d\n", + notifier->name, (int)bootup_req[notifier->processor]); + + return NOTIFY_DONE; +} + +int diag_socket_init_peripheral(uint8_t peripheral) +{ + struct diag_socket_info *info = NULL; + + if (peripheral >= NUM_PERIPHERALS) + return -EINVAL; + + info = &socket_data[peripheral]; + diagfwd_register(TRANSPORT_SOCKET, info->peripheral, + info->type, (void *)info, &socket_ops, + &info->fwd_ctxt); + + info = &socket_dci[peripheral]; + diagfwd_register(TRANSPORT_SOCKET, info->peripheral, + info->type, (void *)info, &socket_ops, + &info->fwd_ctxt); + return 0; +} + +static void __diag_socket_exit(struct diag_socket_info *info) +{ + if (!info) + return; + + diagfwd_deregister(info->peripheral, info->type, (void *)info); + info->fwd_ctxt = NULL; + info->hdl = NULL; + if (info->wq) + destroy_workqueue(info->wq); + +} + +void diag_socket_early_exit(void) +{ + int i = 0; + + for (i = 0; i < NUM_PERIPHERALS; i++) + __diag_socket_exit(&socket_cntl[i]); +} + +void diag_socket_exit(void) +{ + int i = 0; + + for (i = 0; i < NUM_PERIPHERALS; i++) { + __diag_socket_exit(&socket_data[i]); + __diag_socket_exit(&socket_cmd[i]); + __diag_socket_exit(&socket_dci[i]); + __diag_socket_exit(&socket_dci_cmd[i]); + } +} + +static int diag_socket_read(void *ctxt, unsigned char *buf, int buf_len) +{ + int err = 0; + int pkt_len = 0; + int read_len = 0; + int bytes_remaining = 0; + int total_recd = 0; + int loop_count = 0; + uint8_t buf_full = 0; + unsigned char *temp = NULL; + struct kvec iov = {0}; + struct msghdr read_msg = {0}; + struct sockaddr_msm_ipc src_addr = {0}; + struct diag_socket_info *info = NULL; + unsigned long flags; + + info = (struct diag_socket_info *)(ctxt); + if (!info) + return -ENODEV; + + if (!buf || !ctxt || buf_len <= 0) + return -EINVAL; + + temp = buf; + bytes_remaining = buf_len; + + err = wait_event_interruptible(info->read_wait_q, + (info->data_ready > 0) || (!info->hdl) || + (atomic_read(&info->diag_state) == 0)); + if (err) { + mutex_lock(&driver->diagfwd_channel_mutex[info->peripheral]); + diagfwd_channel_read_done(info->fwd_ctxt, buf, 0); + mutex_unlock(&driver->diagfwd_channel_mutex[info->peripheral]); + return -ERESTARTSYS; + } + + /* + * There is no need to continue reading over peripheral in this case. + * Release the wake source hold earlier. + */ + if (atomic_read(&info->diag_state) == 0) { + DIAG_LOG(DIAG_DEBUG_PERIPHERALS, + "%s closing read thread. diag state is closed\n", + info->name); + mutex_lock(&driver->diagfwd_channel_mutex[info->peripheral]); + diagfwd_channel_read_done(info->fwd_ctxt, buf, 0); + mutex_unlock(&driver->diagfwd_channel_mutex[info->peripheral]); + return 0; + } + + if (!info->hdl) { + DIAG_LOG(DIAG_DEBUG_PERIPHERALS, "%s closing read thread\n", + info->name); + goto fail; + } + + do { + loop_count++; + iov.iov_base = temp; + iov.iov_len = bytes_remaining; + read_msg.msg_name = &src_addr; + read_msg.msg_namelen = sizeof(src_addr); + + pkt_len = kernel_recvmsg(info->hdl, &read_msg, &iov, 1, 0, + MSG_PEEK); + if (pkt_len <= 0) + break; + + if (pkt_len > bytes_remaining) { + buf_full = 1; + break; + } + + spin_lock_irqsave(&info->lock, flags); + info->data_ready--; + spin_unlock_irqrestore(&info->lock, flags); + + read_len = kernel_recvmsg(info->hdl, &read_msg, &iov, 1, + pkt_len, 0); + if (read_len <= 0) + goto fail; + + if (!atomic_read(&info->opened) && + info->port_type == PORT_TYPE_SERVER) { + /* + * This is the first packet from the client. Copy its + * address to the connection object. Consider this + * channel open for communication. + */ + memcpy(&info->remote_addr, &src_addr, sizeof(src_addr)); + if (info->ins_id == INST_ID_DCI) + atomic_set(&info->opened, 1); + else + __socket_open_channel(info); + } + + if (read_len < 0) { + pr_err_ratelimited("diag: In %s, error receiving data, err: %d\n", + __func__, pkt_len); + err = read_len; + goto fail; + } + temp += read_len; + total_recd += read_len; + bytes_remaining -= read_len; + } while (info->data_ready > 0); + + if (buf_full || (info->type == TYPE_DATA && pkt_len)) + err = queue_work(info->wq, &(info->read_work)); + + if (total_recd > 0) { + DIAG_LOG(DIAG_DEBUG_PERIPHERALS, "%s read total bytes: %d\n", + info->name, total_recd); + mutex_lock(&driver->diagfwd_channel_mutex[info->peripheral]); + err = diagfwd_channel_read_done(info->fwd_ctxt, + buf, total_recd); + mutex_unlock(&driver->diagfwd_channel_mutex[info->peripheral]); + if (err) + goto fail; + } else { + DIAG_LOG(DIAG_DEBUG_PERIPHERALS, "%s error in read, err: %d\n", + info->name, total_recd); + goto fail; + } + + diag_socket_queue_read(info); + return 0; + +fail: + mutex_lock(&driver->diagfwd_channel_mutex[info->peripheral]); + diagfwd_channel_read_done(info->fwd_ctxt, buf, 0); + mutex_unlock(&driver->diagfwd_channel_mutex[info->peripheral]); + return -EIO; +} + +static int diag_socket_write(void *ctxt, unsigned char *buf, int len) +{ + int err = 0; + int write_len = 0; + struct kvec iov = {0}; + struct msghdr write_msg = {0}; + struct diag_socket_info *info = NULL; + + if (!ctxt || !buf || len <= 0) + return -EIO; + + info = (struct diag_socket_info *)(ctxt); + if (!atomic_read(&info->opened) || !info->hdl) + return -ENODEV; + + iov.iov_base = buf; + iov.iov_len = len; + write_msg.msg_name = &info->remote_addr; + write_msg.msg_namelen = sizeof(info->remote_addr); + write_msg.msg_flags |= MSG_DONTWAIT; + write_len = kernel_sendmsg(info->hdl, &write_msg, &iov, 1, len); + if (write_len < 0) { + err = write_len; + /* + * -EAGAIN means that the number of packets in flight is at + * max capactity and the peripheral hasn't read the data. + */ + if (err != -EAGAIN) { + pr_err_ratelimited("diag: In %s, error sending data, err: %d, ch: %s\n", + __func__, err, info->name); + } + } else if (write_len != len) { + err = write_len; + pr_err_ratelimited("diag: In %s, wrote partial packet to %s, len: %d, wrote: %d\n", + __func__, info->name, len, write_len); + } + + DIAG_LOG(DIAG_DEBUG_PERIPHERALS, "%s wrote to socket, len: %d\n", + info->name, write_len); + + return err; +} + diff -Nruw linux-4.4.115-fbx/drivers/char/diag./diagfwd_socket.h linux-4.4.115-fbx/drivers/char/diag/diagfwd_socket.h --- linux-4.4.115-fbx/drivers/char/diag./diagfwd_socket.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-4.4.115-fbx/drivers/char/diag/diagfwd_socket.h 2019-01-22 16:16:22.963241516 +0100 @@ -0,0 +1,110 @@ +/* Copyright (c) 2015-2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef DIAGFWD_SOCKET_H +#define DIAGFWD_SOCKET_H + +#include +#include + +#define DIAG_SOCKET_NAME_SZ 24 + +#define DIAG_SOCK_MODEM_SVC_ID 64 +#define DIAG_SOCK_MODEM_INS_ID 3 + +#define PORT_TYPE_SERVER 0 +#define PORT_TYPE_CLIENT 1 + +#define PEPIPHERAL_AFTER_BOOT 0 +#define PEPIPHERAL_SSR_DOWN 1 +#define PEPIPHERAL_SSR_UP 2 + +#define CNTL_CMD_NEW_SERVER 4 +#define CNTL_CMD_REMOVE_SERVER 5 +#define CNTL_CMD_REMOVE_CLIENT 6 + +enum { + SOCKET_MODEM, + SOCKET_ADSP, + SOCKET_WCNSS, + SOCKET_SLPI, + SOCKET_CDSP, + SOCKET_APPS, + NUM_SOCKET_SUBSYSTEMS, +}; + +struct diag_socket_info { + uint8_t peripheral; + uint8_t type; + uint8_t port_type; + uint8_t inited; + atomic_t opened; + atomic_t diag_state; + uint32_t pkt_len; + uint32_t pkt_read; + uint32_t svc_id; + uint32_t ins_id; + uint32_t data_ready; + atomic_t flow_cnt; + char name[DIAG_SOCKET_NAME_SZ]; + spinlock_t lock; + wait_queue_head_t wait_q; + struct sockaddr_msm_ipc remote_addr; + struct socket *hdl; + struct workqueue_struct *wq; + struct work_struct init_work; + struct work_struct read_work; + struct diagfwd_info *fwd_ctxt; + wait_queue_head_t read_wait_q; +}; + +union cntl_port_msg { + struct { + uint32_t cmd; + uint32_t service; + uint32_t instance; + uint32_t node_id; + uint32_t port_id; + } srv; + struct { + uint32_t cmd; + uint32_t node_id; + uint32_t port_id; + } cli; +}; + +struct diag_cntl_socket_info { + uint32_t svc_id; + uint32_t ins_id; + atomic_t data_ready; + struct workqueue_struct *wq; + struct work_struct read_work; + struct work_struct init_work; + wait_queue_head_t read_wait_q; + struct socket *hdl; +}; + +extern struct diag_socket_info socket_data[NUM_PERIPHERALS]; +extern struct diag_socket_info socket_cntl[NUM_PERIPHERALS]; +extern struct diag_socket_info socket_dci[NUM_PERIPHERALS]; +extern struct diag_socket_info socket_cmd[NUM_PERIPHERALS]; +extern struct diag_socket_info socket_dci_cmd[NUM_PERIPHERALS]; + +extern struct diag_cntl_socket_info *cntl_socket; + +int diag_socket_init(void); +int diag_socket_init_peripheral(uint8_t peripheral); +void diag_socket_exit(void); +void diag_socket_early_exit(void); +void diag_socket_invalidate(void *ctxt, struct diagfwd_info *fwd_ctxt); +int diag_socket_check_state(void *ctxt); +#endif diff -Nruw linux-4.4.115-fbx/drivers/char/diag./diag_ipc_logging.h linux-4.4.115-fbx/drivers/char/diag/diag_ipc_logging.h --- linux-4.4.115-fbx/drivers/char/diag./diag_ipc_logging.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-4.4.115-fbx/drivers/char/diag/diag_ipc_logging.h 2019-10-29 09:26:23.449201280 +0100 @@ -0,0 +1,45 @@ +/* Copyright (c) 2015, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef DIAGIPCLOG_H +#define DIAGIPCLOG_H + +#include + +#define DIAG_IPC_LOG_PAGES 50 + +#define DIAG_DEBUG_USERSPACE 0x0001 +#define DIAG_DEBUG_MUX 0x0002 +#define DIAG_DEBUG_DCI 0x0004 +#define DIAG_DEBUG_PERIPHERALS 0x0008 +#define DIAG_DEBUG_MASKS 0x0010 +#define DIAG_DEBUG_POWER 0x0020 +#define DIAG_DEBUG_BRIDGE 0x0040 + +#define DIAG_DEBUG + +#ifdef DIAG_DEBUG +extern uint16_t diag_debug_mask; +extern void *diag_ipc_log; + +#define DIAG_LOG(log_lvl, msg, ...) \ + do { \ + if (diag_ipc_log && (log_lvl & diag_debug_mask)) { \ + ipc_log_string(diag_ipc_log, \ + "[%s] " msg, __func__, ##__VA_ARGS__); \ + } \ + } while (0) +#else +#define DIAG_LOG(log_lvl, msg, ...) +#endif + +#endif diff -Nruw linux-4.4.115-fbx/drivers/char/diag./diag_masks.c linux-4.4.115-fbx/drivers/char/diag/diag_masks.c --- linux-4.4.115-fbx/drivers/char/diag./diag_masks.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-4.4.115-fbx/drivers/char/diag/diag_masks.c 2019-10-29 09:26:23.449201280 +0100 @@ -0,0 +1,2351 @@ +/* Copyright (c) 2008-2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include "diagchar.h" +#include "diagfwd_cntl.h" +#include "diag_masks.h" +#include "diagfwd_peripheral.h" +#include "diag_ipc_logging.h" + +#define ALL_EQUIP_ID 100 +#define ALL_SSID -1 + +#define DIAG_SET_FEATURE_MASK(x) (feature_bytes[(x)/8] |= (1 << (x & 0x7))) + +#define diag_check_update(x) \ + (!info || (info && (info->peripheral_mask & MD_PERIPHERAL_MASK(x))) \ + || (info && (info->peripheral_mask & MD_PERIPHERAL_PD_MASK(x)))) \ + +struct diag_mask_info msg_mask; +struct diag_mask_info msg_bt_mask; +struct diag_mask_info log_mask; +struct diag_mask_info event_mask; + +static const struct diag_ssid_range_t msg_mask_tbl[] = { + { .ssid_first = MSG_SSID_0, .ssid_last = MSG_SSID_0_LAST }, + { .ssid_first = MSG_SSID_1, .ssid_last = MSG_SSID_1_LAST }, + { .ssid_first = MSG_SSID_2, .ssid_last = MSG_SSID_2_LAST }, + { .ssid_first = MSG_SSID_3, .ssid_last = MSG_SSID_3_LAST }, + { .ssid_first = MSG_SSID_4, .ssid_last = MSG_SSID_4_LAST }, + { .ssid_first = MSG_SSID_5, .ssid_last = MSG_SSID_5_LAST }, + { .ssid_first = MSG_SSID_6, .ssid_last = MSG_SSID_6_LAST }, + { .ssid_first = MSG_SSID_7, .ssid_last = MSG_SSID_7_LAST }, + { .ssid_first = MSG_SSID_8, .ssid_last = MSG_SSID_8_LAST }, + { .ssid_first = MSG_SSID_9, .ssid_last = MSG_SSID_9_LAST }, + { .ssid_first = MSG_SSID_10, .ssid_last = MSG_SSID_10_LAST }, + { .ssid_first = MSG_SSID_11, .ssid_last = MSG_SSID_11_LAST }, + { .ssid_first = MSG_SSID_12, .ssid_last = MSG_SSID_12_LAST }, + { .ssid_first = MSG_SSID_13, .ssid_last = MSG_SSID_13_LAST }, + { .ssid_first = MSG_SSID_14, .ssid_last = MSG_SSID_14_LAST }, + { .ssid_first = MSG_SSID_15, .ssid_last = MSG_SSID_15_LAST }, + { .ssid_first = MSG_SSID_16, .ssid_last = MSG_SSID_16_LAST }, + { .ssid_first = MSG_SSID_17, .ssid_last = MSG_SSID_17_LAST }, + { .ssid_first = MSG_SSID_18, .ssid_last = MSG_SSID_18_LAST }, + { .ssid_first = MSG_SSID_19, .ssid_last = MSG_SSID_19_LAST }, + { .ssid_first = MSG_SSID_20, .ssid_last = MSG_SSID_20_LAST }, + { .ssid_first = MSG_SSID_21, .ssid_last = MSG_SSID_21_LAST }, + { .ssid_first = MSG_SSID_22, .ssid_last = MSG_SSID_22_LAST }, + { .ssid_first = MSG_SSID_23, .ssid_last = MSG_SSID_23_LAST }, + { .ssid_first = MSG_SSID_24, .ssid_last = MSG_SSID_24_LAST }, + { .ssid_first = MSG_SSID_25, .ssid_last = MSG_SSID_25_LAST } +}; + +static int diag_apps_responds(void) +{ + /* + * Apps processor should respond to mask commands only if the + * Modem channel is up, the feature mask is received from Modem + * and if Modem supports Mask Centralization. + */ + if (!chk_apps_only()) + return 0; + + if (driver->diagfwd_cntl[PERIPHERAL_MODEM] && + driver->diagfwd_cntl[PERIPHERAL_MODEM]->ch_open && + driver->feature[PERIPHERAL_MODEM].rcvd_feature_mask) { + if (driver->feature[PERIPHERAL_MODEM].mask_centralization) + return 1; + return 0; + } + return 1; +} + +static void diag_send_log_mask_update(uint8_t peripheral, int equip_id) +{ + int i; + int err = 0; + int send_once = 0; + int header_len = sizeof(struct diag_ctrl_log_mask); + uint8_t *buf = NULL, upd = 0; + uint8_t *temp = NULL; + uint32_t mask_size = 0; + struct diag_ctrl_log_mask ctrl_pkt; + struct diag_mask_info *mask_info = NULL; + struct diag_log_mask_t *mask = NULL; + + if (peripheral >= NUM_PERIPHERALS) + return; + + if (!driver->diagfwd_cntl[peripheral] || + !driver->diagfwd_cntl[peripheral]->ch_open) { + pr_debug("diag: In %s, control channel is not open, p: %d\n", + __func__, peripheral); + return; + } + + if (driver->md_session_mask != 0) { + if (driver->md_session_mask & MD_PERIPHERAL_MASK(peripheral)) { + if (driver->md_session_map[peripheral]) + mask_info = + driver->md_session_map[peripheral]->log_mask; + } else if (driver->md_session_mask & + MD_PERIPHERAL_PD_MASK(peripheral)) { + upd = diag_mask_to_pd_value(driver->md_session_mask); + if (upd && driver->md_session_map[upd]) + mask_info = + driver->md_session_map[upd]->log_mask; + } else { + DIAG_LOG(DIAG_DEBUG_MASKS, + "asking for mask update with unknown session mask\n"); + return; + } + } else { + mask_info = &log_mask; + } + + if (!mask_info || !mask_info->ptr || !mask_info->update_buf) + return; + + mask = (struct diag_log_mask_t *)mask_info->ptr; + if (!mask->ptr) + return; + buf = mask_info->update_buf; + + switch (mask_info->status) { + case DIAG_CTRL_MASK_ALL_DISABLED: + ctrl_pkt.equip_id = 0; + ctrl_pkt.num_items = 0; + ctrl_pkt.log_mask_size = 0; + send_once = 1; + break; + case DIAG_CTRL_MASK_ALL_ENABLED: + ctrl_pkt.equip_id = 0; + ctrl_pkt.num_items = 0; + ctrl_pkt.log_mask_size = 0; + send_once = 1; + break; + case DIAG_CTRL_MASK_VALID: + send_once = 0; + break; + default: + pr_debug("diag: In %s, invalid log_mask status\n", __func__); + return; + } + + mutex_lock(&mask_info->lock); + for (i = 0; i < MAX_EQUIP_ID; i++, mask++) { + if (!mask->ptr) + continue; + + if (equip_id != i && equip_id != ALL_EQUIP_ID) + continue; + + mutex_lock(&mask->lock); + ctrl_pkt.cmd_type = DIAG_CTRL_MSG_LOG_MASK; + ctrl_pkt.stream_id = 1; + ctrl_pkt.status = mask_info->status; + if (mask_info->status == DIAG_CTRL_MASK_VALID) { + mask_size = LOG_ITEMS_TO_SIZE(mask->num_items_tools); + ctrl_pkt.equip_id = i; + ctrl_pkt.num_items = mask->num_items_tools; + ctrl_pkt.log_mask_size = mask_size; + } + ctrl_pkt.data_len = LOG_MASK_CTRL_HEADER_LEN + mask_size; + + if (header_len + mask_size > mask_info->update_buf_len) { + temp = krealloc(buf, header_len + mask_size, + GFP_KERNEL); + if (!temp) { + pr_err_ratelimited("diag: Unable to realloc log update buffer, new size: %d, equip_id: %d\n", + header_len + mask_size, equip_id); + mutex_unlock(&mask->lock); + break; + } + mask_info->update_buf = temp; + mask_info->update_buf_len = header_len + mask_size; + buf = temp; + } + + memcpy(buf, &ctrl_pkt, header_len); + if (mask_size > 0 && mask_size <= LOG_MASK_SIZE) + memcpy(buf + header_len, mask->ptr, mask_size); + mutex_unlock(&mask->lock); + + DIAG_LOG(DIAG_DEBUG_MASKS, + "sending ctrl pkt to %d, e %d num_items %d size %d\n", + peripheral, i, ctrl_pkt.num_items, + ctrl_pkt.log_mask_size); + + err = diagfwd_write(peripheral, TYPE_CNTL, + buf, header_len + mask_size); + if (err && err != -ENODEV) + pr_err_ratelimited("diag: Unable to send log masks to peripheral %d, equip_id: %d, err: %d\n", + peripheral, i, err); + if (send_once || equip_id != ALL_EQUIP_ID) + break; + + } + mutex_unlock(&mask_info->lock); +} + +static void diag_send_event_mask_update(uint8_t peripheral) +{ + uint8_t *buf = NULL, upd = 0; + uint8_t *temp = NULL; + struct diag_ctrl_event_mask header; + struct diag_mask_info *mask_info = NULL; + int num_bytes = EVENT_COUNT_TO_BYTES(driver->last_event_id); + int write_len = 0; + int err = 0; + int temp_len = 0; + + if (num_bytes <= 0 || num_bytes > driver->event_mask_size) { + pr_debug("diag: In %s, invalid event mask length %d\n", + __func__, num_bytes); + return; + } + + if (peripheral >= NUM_PERIPHERALS) + return; + + if (!driver->diagfwd_cntl[peripheral] || + !driver->diagfwd_cntl[peripheral]->ch_open) { + pr_debug("diag: In %s, control channel is not open, p: %d\n", + __func__, peripheral); + return; + } + + if (driver->md_session_mask != 0) { + if (driver->md_session_mask & MD_PERIPHERAL_MASK(peripheral)) { + if (driver->md_session_map[peripheral]) + mask_info = + driver->md_session_map[peripheral]->event_mask; + } else if (driver->md_session_mask & + MD_PERIPHERAL_PD_MASK(peripheral)) { + upd = diag_mask_to_pd_value(driver->md_session_mask); + if (upd && driver->md_session_map[upd]) + mask_info = + driver->md_session_map[upd]->event_mask; + } else { + DIAG_LOG(DIAG_DEBUG_MASKS, + "asking for mask update with unknown session mask\n"); + return; + } + } else { + mask_info = &event_mask; + } + + if (!mask_info || !mask_info->ptr || !mask_info->update_buf) + return; + + buf = mask_info->update_buf; + mutex_lock(&mask_info->lock); + header.cmd_type = DIAG_CTRL_MSG_EVENT_MASK; + header.stream_id = 1; + header.status = mask_info->status; + + switch (mask_info->status) { + case DIAG_CTRL_MASK_ALL_DISABLED: + header.event_config = 0; + header.event_mask_size = 0; + break; + case DIAG_CTRL_MASK_ALL_ENABLED: + header.event_config = 1; + header.event_mask_size = 0; + break; + case DIAG_CTRL_MASK_VALID: + header.event_config = 1; + header.event_mask_size = num_bytes; + if (num_bytes + sizeof(header) > mask_info->update_buf_len) { + temp_len = num_bytes + sizeof(header); + temp = krealloc(buf, temp_len, GFP_KERNEL); + if (!temp) { + pr_err("diag: Unable to realloc event mask update buffer\n"); + goto err; + } else { + mask_info->update_buf = temp; + mask_info->update_buf_len = temp_len; + buf = temp; + } + } + if (num_bytes > 0 && num_bytes < mask_info->mask_len) + memcpy(buf + sizeof(header), mask_info->ptr, num_bytes); + else { + pr_err("diag: num_bytes(%d) is not satisfying length condition\n", + num_bytes); + goto err; + } + write_len += num_bytes; + break; + default: + pr_debug("diag: In %s, invalid status %d\n", __func__, + mask_info->status); + goto err; + } + header.data_len = EVENT_MASK_CTRL_HEADER_LEN + header.event_mask_size; + memcpy(buf, &header, sizeof(header)); + write_len += sizeof(header); + + err = diagfwd_write(peripheral, TYPE_CNTL, buf, write_len); + if (err && err != -ENODEV) + pr_err_ratelimited("diag: Unable to send event masks to peripheral %d\n", + peripheral); +err: + mutex_unlock(&mask_info->lock); +} + +static void diag_send_msg_mask_update(uint8_t peripheral, int first, int last) +{ + int i; + int err = 0; + int header_len = sizeof(struct diag_ctrl_msg_mask); + int temp_len = 0; + uint8_t *buf = NULL, *temp = NULL; + uint8_t upd = 0; + uint8_t msg_mask_tbl_count_local = 0; + uint32_t mask_size = 0; + struct diag_mask_info *mask_info = NULL; + struct diag_msg_mask_t *mask = NULL; + struct diag_ctrl_msg_mask header; + struct diag_md_session_t *md_session_info = NULL; + + if (peripheral >= NUM_PERIPHERALS) + return; + + if (!driver->diagfwd_cntl[peripheral] || + !driver->diagfwd_cntl[peripheral]->ch_open) { + pr_debug("diag: In %s, control channel is not open, p: %d\n", + __func__, peripheral); + return; + } + + if (driver->md_session_mask != 0) { + if (driver->md_session_mask & MD_PERIPHERAL_MASK(peripheral)) { + if (driver->md_session_map[peripheral]) { + mask_info = + driver->md_session_map[peripheral]->msg_mask; + md_session_info = + driver->md_session_map[peripheral]; + } + } else if (driver->md_session_mask & + MD_PERIPHERAL_PD_MASK(peripheral)) { + upd = diag_mask_to_pd_value(driver->md_session_mask); + if (upd && driver->md_session_map[upd]) { + mask_info = + driver->md_session_map[upd]->msg_mask; + md_session_info = + driver->md_session_map[upd]; + } + } else { + DIAG_LOG(DIAG_DEBUG_MASKS, + "asking for mask update with unknown session mask\n"); + return; + } + } else { + mask_info = &msg_mask; + } + + if (!mask_info || !mask_info->ptr || !mask_info->update_buf) + return; + mutex_lock(&driver->msg_mask_lock); + mask = (struct diag_msg_mask_t *)mask_info->ptr; + if (!mask->ptr) { + mutex_unlock(&driver->msg_mask_lock); + return; + } + buf = mask_info->update_buf; + if (md_session_info) + msg_mask_tbl_count_local = md_session_info->msg_mask_tbl_count; + else + msg_mask_tbl_count_local = driver->msg_mask_tbl_count; + mutex_unlock(&driver->msg_mask_lock); + mutex_lock(&mask_info->lock); + switch (mask_info->status) { + case DIAG_CTRL_MASK_ALL_DISABLED: + mask_size = 0; + break; + case DIAG_CTRL_MASK_ALL_ENABLED: + mask_size = 1; + break; + case DIAG_CTRL_MASK_VALID: + break; + default: + pr_debug("diag: In %s, invalid status: %d\n", __func__, + mask_info->status); + goto err; + } + + for (i = 0; i < msg_mask_tbl_count_local; i++, mask++) { + if (!mask->ptr) + continue; + mutex_lock(&driver->msg_mask_lock); + if (((mask->ssid_first > first) || + (mask->ssid_last_tools < last)) && first != ALL_SSID) { + mutex_unlock(&driver->msg_mask_lock); + continue; + } + + mutex_lock(&mask->lock); + if (mask_info->status == DIAG_CTRL_MASK_VALID) { + mask_size = + mask->ssid_last_tools - mask->ssid_first + 1; + temp_len = mask_size * sizeof(uint32_t); + if (temp_len + header_len <= mask_info->update_buf_len) + goto proceed; + temp = krealloc(mask_info->update_buf, temp_len, + GFP_KERNEL); + if (!temp) { + pr_err("diag: In %s, unable to realloc msg_mask update buffer\n", + __func__); + mask_size = (mask_info->update_buf_len - + header_len) / sizeof(uint32_t); + } else { + mask_info->update_buf = temp; + mask_info->update_buf_len = temp_len; + buf = temp; + pr_debug("diag: In %s, successfully reallocated msg_mask update buffer to len: %d\n", + __func__, mask_info->update_buf_len); + } + } else if (mask_info->status == DIAG_CTRL_MASK_ALL_ENABLED) { + mask_size = 1; + } +proceed: + header.cmd_type = DIAG_CTRL_MSG_F3_MASK; + header.status = mask_info->status; + header.stream_id = 1; + header.msg_mode = 0; + header.ssid_first = mask->ssid_first; + header.ssid_last = mask->ssid_last_tools; + header.msg_mask_size = mask_size; + mask_size *= sizeof(uint32_t); + header.data_len = MSG_MASK_CTRL_HEADER_LEN + mask_size; + memcpy(buf, &header, header_len); + if (mask_size > 0) + memcpy(buf + header_len, mask->ptr, mask_size); + mutex_unlock(&mask->lock); + mutex_unlock(&driver->msg_mask_lock); + + err = diagfwd_write(peripheral, TYPE_CNTL, buf, + header_len + mask_size); + if (err && err != -ENODEV) + pr_err_ratelimited("diag: Unable to send msg masks to peripheral %d, error = %d\n", + peripheral, err); + + if (first != ALL_SSID) + break; + } +err: + mutex_unlock(&mask_info->lock); +} + +static void diag_send_time_sync_update(uint8_t peripheral) +{ + struct diag_ctrl_msg_time_sync time_sync_msg; + int msg_size = sizeof(struct diag_ctrl_msg_time_sync); + int err = 0; + + if (peripheral >= NUM_PERIPHERALS) { + pr_err("diag: In %s, Invalid peripheral, %d\n", + __func__, peripheral); + return; + } + + if (!driver->diagfwd_cntl[peripheral] || + !driver->diagfwd_cntl[peripheral]->ch_open) { + pr_err("diag: In %s, control channel is not open, p: %d, %pK\n", + __func__, peripheral, driver->diagfwd_cntl[peripheral]); + return; + } + + mutex_lock(&driver->diag_cntl_mutex); + time_sync_msg.ctrl_pkt_id = DIAG_CTRL_MSG_TIME_SYNC_PKT; + time_sync_msg.ctrl_pkt_data_len = 5; + time_sync_msg.version = 1; + time_sync_msg.time_api = driver->uses_time_api; + + err = diagfwd_write(peripheral, TYPE_CNTL, &time_sync_msg, msg_size); + if (err) + pr_err("diag: In %s, unable to write to peripheral: %d, type: %d, len: %d, err: %d\n", + __func__, peripheral, TYPE_CNTL, + msg_size, err); + mutex_unlock(&driver->diag_cntl_mutex); +} + +static void diag_send_feature_mask_update(uint8_t peripheral) +{ + void *buf = driver->buf_feature_mask_update; + int header_size = sizeof(struct diag_ctrl_feature_mask); + uint8_t feature_bytes[FEATURE_MASK_LEN] = {0, 0}; + struct diag_ctrl_feature_mask feature_mask; + int total_len = 0; + int err = 0; + + if (peripheral >= NUM_PERIPHERALS) { + pr_err("diag: In %s, Invalid peripheral, %d\n", + __func__, peripheral); + return; + } + + if (!driver->diagfwd_cntl[peripheral] || + !driver->diagfwd_cntl[peripheral]->ch_open) { + pr_err("diag: In %s, control channel is not open, p: %d, %pK\n", + __func__, peripheral, driver->diagfwd_cntl[peripheral]); + return; + } + + mutex_lock(&driver->diag_cntl_mutex); + /* send feature mask update */ + feature_mask.ctrl_pkt_id = DIAG_CTRL_MSG_FEATURE; + feature_mask.ctrl_pkt_data_len = sizeof(uint32_t) + FEATURE_MASK_LEN; + feature_mask.feature_mask_len = FEATURE_MASK_LEN; + memcpy(buf, &feature_mask, header_size); + DIAG_SET_FEATURE_MASK(F_DIAG_FEATURE_MASK_SUPPORT); + DIAG_SET_FEATURE_MASK(F_DIAG_LOG_ON_DEMAND_APPS); + DIAG_SET_FEATURE_MASK(F_DIAG_STM); + DIAG_SET_FEATURE_MASK(F_DIAG_DCI_EXTENDED_HEADER_SUPPORT); + if (driver->supports_separate_cmdrsp) + DIAG_SET_FEATURE_MASK(F_DIAG_REQ_RSP_SUPPORT); + if (driver->supports_apps_hdlc_encoding) + DIAG_SET_FEATURE_MASK(F_DIAG_APPS_HDLC_ENCODE); + if (driver->supports_apps_header_untagging) { + if (peripheral == PERIPHERAL_MODEM || + peripheral == PERIPHERAL_LPASS || + peripheral == PERIPHERAL_CDSP) { + DIAG_SET_FEATURE_MASK(F_DIAG_PKT_HEADER_UNTAG); + driver->peripheral_untag[peripheral] = + ENABLE_PKT_HEADER_UNTAGGING; + } + } + DIAG_SET_FEATURE_MASK(F_DIAG_MASK_CENTRALIZATION); + if (driver->supports_sockets) + DIAG_SET_FEATURE_MASK(F_DIAG_SOCKETS_ENABLED); + + memcpy(buf + header_size, &feature_bytes, FEATURE_MASK_LEN); + total_len = header_size + FEATURE_MASK_LEN; + + err = diagfwd_write(peripheral, TYPE_CNTL, buf, total_len); + if (err) { + pr_err_ratelimited("diag: In %s, unable to write feature mask to peripheral: %d, type: %d, len: %d, err: %d\n", + __func__, peripheral, TYPE_CNTL, + total_len, err); + mutex_unlock(&driver->diag_cntl_mutex); + return; + } + driver->feature[peripheral].sent_feature_mask = 1; + mutex_unlock(&driver->diag_cntl_mutex); +} + +static int diag_cmd_get_ssid_range(unsigned char *src_buf, int src_len, + unsigned char *dest_buf, int dest_len, int pid) +{ + int i; + int write_len = 0; + uint8_t msg_mask_tbl_count = 0; + struct diag_msg_mask_t *mask_ptr = NULL; + struct diag_msg_ssid_query_t rsp; + struct diag_ssid_range_t ssid_range; + struct diag_mask_info *mask_info = NULL; + struct diag_md_session_t *info = NULL; + + mutex_lock(&driver->md_session_lock); + info = diag_md_session_get_pid(pid); + mask_info = (!info) ? &msg_mask : info->msg_mask; + if (!src_buf || !dest_buf || src_len <= 0 || dest_len <= 0 || + !mask_info) { + pr_err("diag: Invalid input in %s, src_buf: %pK, src_len: %d, dest_buf: %pK, dest_len: %d, mask_info: %pK\n", + __func__, src_buf, src_len, dest_buf, dest_len, + mask_info); + mutex_unlock(&driver->md_session_lock); + return -EINVAL; + } + if (!mask_info->ptr) { + pr_err("diag: In %s, invalid input mask_info->ptr: %pK\n", + __func__, mask_info->ptr); + mutex_unlock(&driver->md_session_lock); + return -EINVAL; + } + + if (!diag_apps_responds()) { + mutex_unlock(&driver->md_session_lock); + return 0; + } + mutex_lock(&driver->msg_mask_lock); + msg_mask_tbl_count = (info) ? info->msg_mask_tbl_count : + driver->msg_mask_tbl_count; + rsp.cmd_code = DIAG_CMD_MSG_CONFIG; + rsp.sub_cmd = DIAG_CMD_OP_GET_SSID_RANGE; + rsp.status = MSG_STATUS_SUCCESS; + rsp.padding = 0; + rsp.count = msg_mask_tbl_count; + memcpy(dest_buf, &rsp, sizeof(rsp)); + write_len += sizeof(rsp); + mask_ptr = (struct diag_msg_mask_t *)mask_info->ptr; + for (i = 0; i < msg_mask_tbl_count; i++, mask_ptr++) { + if (write_len + sizeof(ssid_range) > dest_len) { + pr_err("diag: In %s, Truncating response due to size limitations of rsp buffer\n", + __func__); + break; + } + ssid_range.ssid_first = mask_ptr->ssid_first; + ssid_range.ssid_last = mask_ptr->ssid_last_tools; + memcpy(dest_buf + write_len, &ssid_range, sizeof(ssid_range)); + write_len += sizeof(ssid_range); + } + mutex_unlock(&driver->msg_mask_lock); + mutex_unlock(&driver->md_session_lock); + return write_len; +} + +static int diag_cmd_get_build_mask(unsigned char *src_buf, int src_len, + unsigned char *dest_buf, int dest_len, int pid) +{ + int i = 0; + int write_len = 0; + int num_entries = 0; + int copy_len = 0; + struct diag_msg_mask_t *build_mask = NULL; + struct diag_build_mask_req_t *req = NULL; + struct diag_msg_build_mask_t rsp; + + if (!src_buf || !dest_buf || src_len <= 0 || dest_len <= 0) { + pr_err("diag: Invalid input in %s, src_buf: %pK, src_len: %d, dest_buf: %pK, dest_len: %d\n", + __func__, src_buf, src_len, dest_buf, dest_len); + return -EINVAL; + } + + if (!diag_apps_responds()) + return 0; + mutex_lock(&driver->msg_mask_lock); + req = (struct diag_build_mask_req_t *)src_buf; + rsp.cmd_code = DIAG_CMD_MSG_CONFIG; + rsp.sub_cmd = DIAG_CMD_OP_GET_BUILD_MASK; + rsp.ssid_first = req->ssid_first; + rsp.ssid_last = req->ssid_last; + rsp.status = MSG_STATUS_FAIL; + rsp.padding = 0; + build_mask = (struct diag_msg_mask_t *)msg_bt_mask.ptr; + for (i = 0; i < driver->bt_msg_mask_tbl_count; i++, build_mask++) { + if (!build_mask->ptr) + continue; + if (build_mask->ssid_first != req->ssid_first) + continue; + num_entries = req->ssid_last - req->ssid_first + 1; + if (num_entries > build_mask->range) { + pr_warn("diag: In %s, truncating ssid range for ssid_first: %d ssid_last %d\n", + __func__, req->ssid_first, req->ssid_last); + num_entries = build_mask->range; + req->ssid_last = req->ssid_first + build_mask->range; + } + copy_len = num_entries * sizeof(uint32_t); + if (copy_len + sizeof(rsp) > dest_len) + copy_len = dest_len - sizeof(rsp); + memcpy(dest_buf + sizeof(rsp), build_mask->ptr, copy_len); + write_len += copy_len; + rsp.ssid_last = build_mask->ssid_last; + rsp.status = MSG_STATUS_SUCCESS; + break; + } + memcpy(dest_buf, &rsp, sizeof(rsp)); + write_len += sizeof(rsp); + mutex_unlock(&driver->msg_mask_lock); + return write_len; +} + +static int diag_cmd_get_msg_mask(unsigned char *src_buf, int src_len, + unsigned char *dest_buf, int dest_len, int pid) +{ + int i; + int write_len = 0; + uint32_t mask_size = 0; + uint8_t msg_mask_tbl_count = 0; + struct diag_msg_mask_t *mask = NULL; + struct diag_build_mask_req_t *req = NULL; + struct diag_msg_build_mask_t rsp; + struct diag_mask_info *mask_info = NULL; + struct diag_md_session_t *info = NULL; + + mutex_lock(&driver->md_session_lock); + info = diag_md_session_get_pid(pid); + + mask_info = (!info) ? &msg_mask : info->msg_mask; + if (!src_buf || !dest_buf || src_len <= 0 || dest_len <= 0 || + !mask_info) { + pr_err("diag: Invalid input in %s, src_buf: %pK, src_len: %d, dest_buf: %pK, dest_len: %d, mask_info: %pK\n", + __func__, src_buf, src_len, dest_buf, dest_len, + mask_info); + mutex_unlock(&driver->md_session_lock); + return -EINVAL; + } + if (!mask_info->ptr) { + pr_err("diag: In %s, invalid input mask_info->ptr: %pK\n", + __func__, mask_info->ptr); + mutex_unlock(&driver->md_session_lock); + return -EINVAL; + } + if (!diag_apps_responds()) { + mutex_unlock(&driver->md_session_lock); + return 0; + } + + mutex_lock(&driver->msg_mask_lock); + msg_mask_tbl_count = (info) ? info->msg_mask_tbl_count : + driver->msg_mask_tbl_count; + req = (struct diag_build_mask_req_t *)src_buf; + rsp.cmd_code = DIAG_CMD_MSG_CONFIG; + rsp.sub_cmd = DIAG_CMD_OP_GET_MSG_MASK; + rsp.ssid_first = req->ssid_first; + rsp.ssid_last = req->ssid_last; + rsp.status = MSG_STATUS_FAIL; + rsp.padding = 0; + mask = (struct diag_msg_mask_t *)mask_info->ptr; + if (!mask->ptr) { + pr_err("diag: Invalid input in %s, mask->ptr: %pK\n", + __func__, mask->ptr); + mutex_unlock(&driver->msg_mask_lock); + mutex_unlock(&driver->md_session_lock); + return -EINVAL; + } + for (i = 0; i < msg_mask_tbl_count; i++, mask++) { + if (!mask->ptr) + continue; + if ((req->ssid_first < mask->ssid_first) || + (req->ssid_first > mask->ssid_last_tools)) { + continue; + } + mask_size = mask->range * sizeof(uint32_t); + /* Copy msg mask only till the end of the rsp buffer */ + if (mask_size + sizeof(rsp) > dest_len) + mask_size = dest_len - sizeof(rsp); + memcpy(dest_buf + sizeof(rsp), mask->ptr, mask_size); + write_len += mask_size; + rsp.status = MSG_STATUS_SUCCESS; + break; + } + memcpy(dest_buf, &rsp, sizeof(rsp)); + write_len += sizeof(rsp); + mutex_unlock(&driver->msg_mask_lock); + mutex_unlock(&driver->md_session_lock); + return write_len; +} + +static int diag_cmd_set_msg_mask(unsigned char *src_buf, int src_len, + unsigned char *dest_buf, int dest_len, int pid) +{ + int i; + int write_len = 0; + int header_len = sizeof(struct diag_msg_build_mask_t); + int found = 0; + uint32_t mask_size = 0; + uint32_t offset = 0; + struct diag_msg_mask_t *mask = NULL; + struct diag_msg_build_mask_t *req = NULL; + struct diag_msg_build_mask_t rsp; + struct diag_mask_info *mask_info = NULL; + struct diag_msg_mask_t *mask_next = NULL; + uint32_t *temp = NULL; + struct diag_md_session_t *info = NULL; + uint8_t msg_mask_tbl_count = 0; + + mutex_lock(&driver->md_session_lock); + info = diag_md_session_get_pid(pid); + + mask_info = (!info) ? &msg_mask : info->msg_mask; + if (!src_buf || !dest_buf || src_len <= 0 || dest_len <= 0 || + !mask_info) { + pr_err("diag: Invalid input in %s, src_buf: %pK, src_len: %d, dest_buf: %pK, dest_len: %d, mask_info: %pK\n", + __func__, src_buf, src_len, dest_buf, dest_len, + mask_info); + mutex_unlock(&driver->md_session_lock); + return -EINVAL; + } + if (!mask_info->ptr) { + pr_err("diag: In %s, invalid input mask_info->ptr: %pK\n", + __func__, mask_info->ptr); + mutex_unlock(&driver->md_session_lock); + return -EINVAL; + } + + req = (struct diag_msg_build_mask_t *)src_buf; + mutex_lock(&mask_info->lock); + mutex_lock(&driver->msg_mask_lock); + mask = (struct diag_msg_mask_t *)mask_info->ptr; + if (!mask->ptr) { + pr_err("diag: Invalid input in %s, mask->ptr: %pK\n", + __func__, mask->ptr); + mutex_unlock(&driver->msg_mask_lock); + mutex_unlock(&mask_info->lock); + mutex_unlock(&driver->md_session_lock); + return -EINVAL; + } + msg_mask_tbl_count = (info) ? info->msg_mask_tbl_count : + driver->msg_mask_tbl_count; + for (i = 0; i < msg_mask_tbl_count; i++, mask++) { + if (!mask->ptr) + continue; + if (i < (msg_mask_tbl_count - 1)) { + mask_next = mask; + mask_next++; + } else + mask_next = NULL; + + if ((req->ssid_first < mask->ssid_first) || + (req->ssid_first > mask->ssid_first + MAX_SSID_PER_RANGE) || + (mask_next && (req->ssid_first >= mask_next->ssid_first))) { + continue; + } + mask_next = NULL; + found = 1; + mutex_lock(&mask->lock); + mask_size = req->ssid_last - req->ssid_first + 1; + if (mask_size > MAX_SSID_PER_RANGE) { + pr_warn("diag: In %s, truncating ssid range, %d-%d to max allowed: %d\n", + __func__, mask->ssid_first, mask->ssid_last, + MAX_SSID_PER_RANGE); + mask_size = MAX_SSID_PER_RANGE; + mask->range_tools = MAX_SSID_PER_RANGE; + mask->ssid_last_tools = + mask->ssid_first + mask->range_tools; + } + if (req->ssid_last > mask->ssid_last_tools) { + pr_debug("diag: Msg SSID range mismatch\n"); + if (mask_size != MAX_SSID_PER_RANGE) + mask->ssid_last_tools = req->ssid_last; + mask->range_tools = + mask->ssid_last_tools - mask->ssid_first + 1; + temp = krealloc(mask->ptr, + mask->range_tools * sizeof(uint32_t), + GFP_KERNEL); + if (!temp) { + pr_err_ratelimited("diag: In %s, unable to allocate memory for msg mask ptr, mask_size: %d\n", + __func__, mask_size); + mutex_unlock(&mask->lock); + mutex_unlock(&driver->msg_mask_lock); + mutex_unlock(&mask_info->lock); + mutex_unlock(&driver->md_session_lock); + return -ENOMEM; + } + mask->ptr = temp; + } + + offset = req->ssid_first - mask->ssid_first; + if (offset + mask_size > mask->range_tools) { + pr_err("diag: In %s, Not in msg mask range, mask_size: %d, offset: %d\n", + __func__, mask_size, offset); + mutex_unlock(&mask->lock); + break; + } + mask_size = mask_size * sizeof(uint32_t); + memcpy(mask->ptr + offset, src_buf + header_len, mask_size); + mutex_unlock(&mask->lock); + mask_info->status = DIAG_CTRL_MASK_VALID; + break; + } + mutex_unlock(&driver->msg_mask_lock); + mutex_unlock(&mask_info->lock); + mutex_unlock(&driver->md_session_lock); + if (diag_check_update(APPS_DATA)) + diag_update_userspace_clients(MSG_MASKS_TYPE); + + /* + * Apps processor must send the response to this command. Frame the + * response. + */ + rsp.cmd_code = DIAG_CMD_MSG_CONFIG; + rsp.sub_cmd = DIAG_CMD_OP_SET_MSG_MASK; + rsp.ssid_first = req->ssid_first; + rsp.ssid_last = req->ssid_last; + rsp.status = found; + rsp.padding = 0; + memcpy(dest_buf, &rsp, header_len); + write_len += header_len; + if (!found) + goto end; + if (mask_size + write_len > dest_len) + mask_size = dest_len - write_len; + memcpy(dest_buf + write_len, src_buf + header_len, mask_size); + write_len += mask_size; + for (i = 0; i < NUM_PERIPHERALS; i++) { + if (!diag_check_update(i)) + continue; + mutex_lock(&driver->md_session_lock); + diag_send_msg_mask_update(i, req->ssid_first, req->ssid_last); + mutex_unlock(&driver->md_session_lock); + } +end: + return write_len; +} + +static int diag_cmd_set_all_msg_mask(unsigned char *src_buf, int src_len, + unsigned char *dest_buf, int dest_len, int pid) +{ + int i; + int write_len = 0; + int header_len = sizeof(struct diag_msg_config_rsp_t); + struct diag_msg_config_rsp_t rsp; + struct diag_msg_config_rsp_t *req = NULL; + struct diag_msg_mask_t *mask = NULL; + struct diag_mask_info *mask_info = NULL; + struct diag_md_session_t *info = NULL; + uint8_t msg_mask_tbl_count = 0; + + mutex_lock(&driver->md_session_lock); + info = diag_md_session_get_pid(pid); + + mask_info = (!info) ? &msg_mask : info->msg_mask; + if (!src_buf || !dest_buf || src_len <= 0 || dest_len <= 0 || + !mask_info) { + pr_err("diag: Invalid input in %s, src_buf: %pK, src_len: %d, dest_buf: %pK, dest_len: %d, mask_info: %pK\n", + __func__, src_buf, src_len, dest_buf, dest_len, + mask_info); + mutex_unlock(&driver->md_session_lock); + return -EINVAL; + } + if (!mask_info->ptr) { + pr_err("diag: In %s, invalid input mask_info->ptr: %pK\n", + __func__, mask_info->ptr); + mutex_unlock(&driver->md_session_lock); + return -EINVAL; + } + + req = (struct diag_msg_config_rsp_t *)src_buf; + + mutex_lock(&mask_info->lock); + mutex_lock(&driver->msg_mask_lock); + + mask = (struct diag_msg_mask_t *)mask_info->ptr; + if (!mask->ptr) { + pr_err("diag: Invalid input in %s, mask->ptr: %pK\n", + __func__, mask->ptr); + mutex_unlock(&driver->msg_mask_lock); + mutex_unlock(&mask_info->lock); + mutex_unlock(&driver->md_session_lock); + return -EINVAL; + } + msg_mask_tbl_count = (info) ? info->msg_mask_tbl_count : + driver->msg_mask_tbl_count; + mask_info->status = (req->rt_mask) ? DIAG_CTRL_MASK_ALL_ENABLED : + DIAG_CTRL_MASK_ALL_DISABLED; + for (i = 0; i < msg_mask_tbl_count; i++, mask++) { + if (mask && mask->ptr) { + mutex_lock(&mask->lock); + memset(mask->ptr, req->rt_mask, + mask->range * sizeof(uint32_t)); + mutex_unlock(&mask->lock); + } + } + mutex_unlock(&driver->msg_mask_lock); + mutex_unlock(&mask_info->lock); + mutex_unlock(&driver->md_session_lock); + if (diag_check_update(APPS_DATA)) + diag_update_userspace_clients(MSG_MASKS_TYPE); + + /* + * Apps processor must send the response to this command. Frame the + * response. + */ + rsp.cmd_code = DIAG_CMD_MSG_CONFIG; + rsp.sub_cmd = DIAG_CMD_OP_SET_ALL_MSG_MASK; + rsp.status = MSG_STATUS_SUCCESS; + rsp.padding = 0; + rsp.rt_mask = req->rt_mask; + memcpy(dest_buf, &rsp, header_len); + write_len += header_len; + + for (i = 0; i < NUM_PERIPHERALS; i++) { + if (!diag_check_update(i)) + continue; + mutex_lock(&driver->md_session_lock); + diag_send_msg_mask_update(i, ALL_SSID, ALL_SSID); + mutex_unlock(&driver->md_session_lock); + } + + return write_len; +} + +static int diag_cmd_get_event_mask(unsigned char *src_buf, int src_len, + unsigned char *dest_buf, int dest_len, int pid) +{ + int write_len = 0; + uint32_t mask_size; + struct diag_event_mask_config_t rsp; + + if (!src_buf || !dest_buf || src_len <= 0 || dest_len <= 0) { + pr_err("diag: Invalid input in %s, src_buf: %pK, src_len: %d, dest_buf: %pK, dest_len: %d\n", + __func__, src_buf, src_len, dest_buf, dest_len); + return -EINVAL; + } + + if (!diag_apps_responds()) + return 0; + + mask_size = EVENT_COUNT_TO_BYTES(driver->last_event_id); + if (mask_size + sizeof(rsp) > dest_len) { + pr_err("diag: In %s, invalid mask size: %d\n", __func__, + mask_size); + return -ENOMEM; + } + + rsp.cmd_code = DIAG_CMD_GET_EVENT_MASK; + rsp.status = EVENT_STATUS_SUCCESS; + rsp.padding = 0; + rsp.num_bits = driver->last_event_id + 1; + memcpy(dest_buf, &rsp, sizeof(rsp)); + write_len += sizeof(rsp); + memcpy(dest_buf + write_len, event_mask.ptr, mask_size); + write_len += mask_size; + + return write_len; +} + +static int diag_cmd_update_event_mask(unsigned char *src_buf, int src_len, + unsigned char *dest_buf, int dest_len, int pid) +{ + int i; + int write_len = 0; + int mask_len = 0; + int header_len = sizeof(struct diag_event_mask_config_t); + struct diag_event_mask_config_t rsp; + struct diag_event_mask_config_t *req; + struct diag_mask_info *mask_info = NULL; + struct diag_md_session_t *info = NULL; + + mutex_lock(&driver->md_session_lock); + info = diag_md_session_get_pid(pid); + mask_info = (!info) ? &event_mask : info->event_mask; + if (!src_buf || !dest_buf || src_len <= 0 || dest_len <= 0 || + !mask_info) { + pr_err("diag: Invalid input in %s, src_buf: %pK, src_len: %d, dest_buf: %pK, dest_len: %d, mask_info: %pK\n", + __func__, src_buf, src_len, dest_buf, dest_len, + mask_info); + mutex_unlock(&driver->md_session_lock); + return -EINVAL; + } + if (!mask_info->ptr) { + pr_err("diag: In %s, invalid input mask_info->ptr: %pK\n", + __func__, mask_info->ptr); + mutex_unlock(&driver->md_session_lock); + return -EINVAL; + } + req = (struct diag_event_mask_config_t *)src_buf; + mask_len = EVENT_COUNT_TO_BYTES(req->num_bits); + if (mask_len <= 0 || mask_len > event_mask.mask_len) { + pr_err("diag: In %s, invalid event mask len: %d\n", __func__, + mask_len); + mutex_unlock(&driver->md_session_lock); + return -EIO; + } + + mutex_lock(&mask_info->lock); + memcpy(mask_info->ptr, src_buf + header_len, mask_len); + mask_info->status = DIAG_CTRL_MASK_VALID; + mutex_unlock(&mask_info->lock); + mutex_unlock(&driver->md_session_lock); + if (diag_check_update(APPS_DATA)) + diag_update_userspace_clients(EVENT_MASKS_TYPE); + + /* + * Apps processor must send the response to this command. Frame the + * response. + */ + rsp.cmd_code = DIAG_CMD_SET_EVENT_MASK; + rsp.status = EVENT_STATUS_SUCCESS; + rsp.padding = 0; + rsp.num_bits = driver->last_event_id + 1; + memcpy(dest_buf, &rsp, header_len); + write_len += header_len; + memcpy(dest_buf + write_len, mask_info->ptr, mask_len); + write_len += mask_len; + + for (i = 0; i < NUM_PERIPHERALS; i++) { + if (!diag_check_update(i)) + continue; + mutex_lock(&driver->md_session_lock); + diag_send_event_mask_update(i); + mutex_unlock(&driver->md_session_lock); + } + + return write_len; +} + +static int diag_cmd_toggle_events(unsigned char *src_buf, int src_len, + unsigned char *dest_buf, int dest_len, int pid) +{ + int i; + int write_len = 0; + uint8_t toggle = 0; + struct diag_event_report_t header; + struct diag_mask_info *mask_info = NULL; + struct diag_md_session_t *info = NULL; + + mutex_lock(&driver->md_session_lock); + info = diag_md_session_get_pid(pid); + mask_info = (!info) ? &event_mask : info->event_mask; + if (!src_buf || !dest_buf || src_len <= 0 || dest_len <= 0 || + !mask_info) { + pr_err("diag: Invalid input in %s, src_buf: %pK, src_len: %d, dest_buf: %pK, dest_len: %d, mask_info: %pK\n", + __func__, src_buf, src_len, dest_buf, dest_len, + mask_info); + mutex_unlock(&driver->md_session_lock); + return -EINVAL; + } + if (!mask_info->ptr) { + pr_err("diag: In %s, invalid input mask_info->ptr: %pK\n", + __func__, mask_info->ptr); + mutex_unlock(&driver->md_session_lock); + return -EINVAL; + } + + toggle = *(src_buf + 1); + mutex_lock(&mask_info->lock); + if (toggle) { + mask_info->status = DIAG_CTRL_MASK_ALL_ENABLED; + memset(mask_info->ptr, 0xFF, mask_info->mask_len); + } else { + mask_info->status = DIAG_CTRL_MASK_ALL_DISABLED; + memset(mask_info->ptr, 0, mask_info->mask_len); + } + mutex_unlock(&mask_info->lock); + mutex_unlock(&driver->md_session_lock); + if (diag_check_update(APPS_DATA)) + diag_update_userspace_clients(EVENT_MASKS_TYPE); + + /* + * Apps processor must send the response to this command. Frame the + * response. + */ + header.cmd_code = DIAG_CMD_EVENT_TOGGLE; + header.padding = 0; + for (i = 0; i < NUM_PERIPHERALS; i++) { + if (!diag_check_update(i)) + continue; + mutex_lock(&driver->md_session_lock); + diag_send_event_mask_update(i); + mutex_unlock(&driver->md_session_lock); + } + memcpy(dest_buf, &header, sizeof(header)); + write_len += sizeof(header); + + return write_len; +} + +static int diag_cmd_get_log_mask(unsigned char *src_buf, int src_len, + unsigned char *dest_buf, int dest_len, int pid) +{ + int i; + int status = LOG_STATUS_INVALID; + int write_len = 0; + int read_len = 0; + int req_header_len = sizeof(struct diag_log_config_req_t); + int rsp_header_len = sizeof(struct diag_log_config_rsp_t); + uint32_t mask_size = 0; + struct diag_log_mask_t *log_item = NULL; + struct diag_log_config_req_t *req; + struct diag_log_config_rsp_t rsp; + struct diag_mask_info *mask_info = NULL; + struct diag_md_session_t *info = NULL; + + mutex_lock(&driver->md_session_lock); + info = diag_md_session_get_pid(pid); + + mask_info = (!info) ? &log_mask : info->log_mask; + if (!src_buf || !dest_buf || src_len <= 0 || dest_len <= 0 || + !mask_info) { + pr_err("diag: Invalid input in %s, src_buf: %pK, src_len: %d, dest_buf: %pK, dest_len: %d, mask_info: %pK\n", + __func__, src_buf, src_len, dest_buf, dest_len, + mask_info); + mutex_unlock(&driver->md_session_lock); + return -EINVAL; + } + if (!mask_info->ptr) { + pr_err("diag: In %s, invalid input mask_info->ptr: %pK\n", + __func__, mask_info->ptr); + mutex_unlock(&driver->md_session_lock); + return -EINVAL; + } + + if (!diag_apps_responds()) { + mutex_unlock(&driver->md_session_lock); + return 0; + } + + req = (struct diag_log_config_req_t *)src_buf; + read_len += req_header_len; + + rsp.cmd_code = DIAG_CMD_LOG_CONFIG; + rsp.padding[0] = 0; + rsp.padding[1] = 0; + rsp.padding[2] = 0; + rsp.sub_cmd = DIAG_CMD_OP_GET_LOG_MASK; + /* + * Don't copy the response header now. Copy at the end after + * calculating the status field value + */ + write_len += rsp_header_len; + + log_item = (struct diag_log_mask_t *)mask_info->ptr; + if (!log_item->ptr) { + pr_err("diag: Invalid input in %s, mask: %pK\n", + __func__, log_item); + mutex_unlock(&driver->md_session_lock); + return -EINVAL; + } + for (i = 0; i < MAX_EQUIP_ID; i++, log_item++) { + if (log_item->equip_id != req->equip_id) + continue; + mutex_lock(&log_item->lock); + mask_size = LOG_ITEMS_TO_SIZE(log_item->num_items_tools); + /* + * Make sure we have space to fill the response in the buffer. + * Destination buffer should atleast be able to hold equip_id + * (uint32_t), num_items(uint32_t), mask (mask_size) and the + * response header. + */ + if ((mask_size + (2 * sizeof(uint32_t)) + rsp_header_len) > + dest_len) { + pr_err("diag: In %s, invalid length: %d, max rsp_len: %d\n", + __func__, mask_size, dest_len); + status = LOG_STATUS_FAIL; + mutex_unlock(&log_item->lock); + break; + } + *(uint32_t *)(dest_buf + write_len) = log_item->equip_id; + write_len += sizeof(uint32_t); + *(uint32_t *)(dest_buf + write_len) = log_item->num_items_tools; + write_len += sizeof(uint32_t); + if (mask_size > 0) { + memcpy(dest_buf + write_len, log_item->ptr, mask_size); + write_len += mask_size; + } + DIAG_LOG(DIAG_DEBUG_MASKS, + "sending log e %d num_items %d size %d\n", + log_item->equip_id, log_item->num_items_tools, + log_item->range_tools); + mutex_unlock(&log_item->lock); + status = LOG_STATUS_SUCCESS; + break; + } + + rsp.status = status; + memcpy(dest_buf, &rsp, rsp_header_len); + + mutex_unlock(&driver->md_session_lock); + return write_len; +} + +static int diag_cmd_get_log_range(unsigned char *src_buf, int src_len, + unsigned char *dest_buf, int dest_len, int pid) +{ + int i; + int write_len = 0; + struct diag_log_config_rsp_t rsp; + struct diag_log_mask_t *mask = (struct diag_log_mask_t *)log_mask.ptr; + + if (!mask) + return -EINVAL; + + if (!diag_apps_responds()) + return 0; + + if (!src_buf || !dest_buf || src_len <= 0 || dest_len <= 0) { + pr_err("diag: Invalid input in %s, src_buf: %pK, src_len: %d, dest_buf: %pK, dest_len: %d\n", + __func__, src_buf, src_len, dest_buf, dest_len); + return -EINVAL; + } + + rsp.cmd_code = DIAG_CMD_LOG_CONFIG; + rsp.padding[0] = 0; + rsp.padding[1] = 0; + rsp.padding[2] = 0; + rsp.sub_cmd = DIAG_CMD_OP_GET_LOG_RANGE; + rsp.status = LOG_STATUS_SUCCESS; + memcpy(dest_buf, &rsp, sizeof(rsp)); + write_len += sizeof(rsp); + + for (i = 0; i < MAX_EQUIP_ID && write_len < dest_len; i++, mask++) { + *(uint32_t *)(dest_buf + write_len) = mask->num_items_tools; + write_len += sizeof(uint32_t); + } + + return write_len; +} + +static int diag_cmd_set_log_mask(unsigned char *src_buf, int src_len, + unsigned char *dest_buf, int dest_len, + int pid) +{ + int i; + int write_len = 0; + int status = LOG_STATUS_SUCCESS; + int read_len = 0; + int payload_len = 0; + int req_header_len = sizeof(struct diag_log_config_req_t); + int rsp_header_len = sizeof(struct diag_log_config_set_rsp_t); + uint32_t mask_size = 0; + struct diag_log_config_req_t *req; + struct diag_log_config_set_rsp_t rsp; + struct diag_log_mask_t *mask = NULL; + unsigned char *temp_buf = NULL; + struct diag_mask_info *mask_info = NULL; + struct diag_md_session_t *info = NULL; + + mutex_lock(&driver->md_session_lock); + info = diag_md_session_get_pid(pid); + + mask_info = (!info) ? &log_mask : info->log_mask; + if (!src_buf || !dest_buf || src_len <= 0 || dest_len <= 0 || + !mask_info) { + pr_err("diag: Invalid input in %s, src_buf: %pK, src_len: %d, dest_buf: %pK, dest_len: %d, mask_info: %pK\n", + __func__, src_buf, src_len, dest_buf, dest_len, + mask_info); + mutex_unlock(&driver->md_session_lock); + return -EINVAL; + } + if (!mask_info->ptr) { + pr_err("diag: In %s, invalid input mask_info->ptr: %pK\n", + __func__, mask_info->ptr); + mutex_unlock(&driver->md_session_lock); + return -EINVAL; + } + + req = (struct diag_log_config_req_t *)src_buf; + read_len += req_header_len; + mask = (struct diag_log_mask_t *)mask_info->ptr; + if (!mask->ptr) { + pr_err("diag: Invalid input in %s, mask->ptr: %pK\n", + __func__, mask->ptr); + mutex_unlock(&driver->md_session_lock); + return -EINVAL; + } + if (req->equip_id >= MAX_EQUIP_ID) { + pr_err("diag: In %s, Invalid logging mask request, equip_id: %d\n", + __func__, req->equip_id); + status = LOG_STATUS_INVALID; + } + + if (req->num_items == 0) { + pr_err("diag: In %s, Invalid number of items in log mask request, equip_id: %d\n", + __func__, req->equip_id); + status = LOG_STATUS_INVALID; + } + + mutex_lock(&mask_info->lock); + for (i = 0; i < MAX_EQUIP_ID && !status; i++, mask++) { + if (!mask || !mask->ptr) + continue; + if (mask->equip_id != req->equip_id) + continue; + mutex_lock(&mask->lock); + + DIAG_LOG(DIAG_DEBUG_MASKS, "e: %d current: %d %d new: %d %d", + mask->equip_id, mask->num_items_tools, + mask->range_tools, req->num_items, + LOG_ITEMS_TO_SIZE(req->num_items)); + /* + * If the size of the log mask cannot fit into our + * buffer, trim till we have space left in the buffer. + * num_items should then reflect the items that we have + * in our buffer. + */ + mask->num_items_tools = (req->num_items > MAX_ITEMS_ALLOWED) ? + MAX_ITEMS_ALLOWED : req->num_items; + mask_size = LOG_ITEMS_TO_SIZE(mask->num_items_tools); + memset(mask->ptr, 0, mask->range_tools); + if (mask_size > mask->range_tools) { + DIAG_LOG(DIAG_DEBUG_MASKS, + "log range mismatch, e: %d old: %d new: %d\n", + req->equip_id, mask->range_tools, + LOG_ITEMS_TO_SIZE(mask->num_items_tools)); + /* Change in the mask reported by tools */ + temp_buf = krealloc(mask->ptr, mask_size, GFP_KERNEL); + if (!temp_buf) { + mask_info->status = DIAG_CTRL_MASK_INVALID; + mutex_unlock(&mask->lock); + break; + } + mask->ptr = temp_buf; + memset(mask->ptr, 0, mask_size); + mask->range_tools = mask_size; + } + req->num_items = mask->num_items_tools; + if (mask_size > 0) + memcpy(mask->ptr, src_buf + read_len, mask_size); + DIAG_LOG(DIAG_DEBUG_MASKS, + "copying log mask, e %d num %d range %d size %d\n", + req->equip_id, mask->num_items_tools, + mask->range_tools, mask_size); + mutex_unlock(&mask->lock); + mask_info->status = DIAG_CTRL_MASK_VALID; + break; + } + mutex_unlock(&mask_info->lock); + mutex_unlock(&driver->md_session_lock); + if (diag_check_update(APPS_DATA)) + diag_update_userspace_clients(LOG_MASKS_TYPE); + + /* + * Apps processor must send the response to this command. Frame the + * response. + */ + payload_len = LOG_ITEMS_TO_SIZE(req->num_items); + if ((payload_len + rsp_header_len > dest_len) || (payload_len == 0)) { + pr_err("diag: In %s, invalid length, payload_len: %d, header_len: %d, dest_len: %d\n", + __func__, payload_len, rsp_header_len , dest_len); + status = LOG_STATUS_FAIL; + } + rsp.cmd_code = DIAG_CMD_LOG_CONFIG; + rsp.padding[0] = 0; + rsp.padding[1] = 0; + rsp.padding[2] = 0; + rsp.sub_cmd = DIAG_CMD_OP_SET_LOG_MASK; + rsp.status = status; + rsp.equip_id = req->equip_id; + rsp.num_items = req->num_items; + memcpy(dest_buf, &rsp, rsp_header_len); + write_len += rsp_header_len; + if (status != LOG_STATUS_SUCCESS) + goto end; + memcpy(dest_buf + write_len, src_buf + read_len, payload_len); + write_len += payload_len; + + for (i = 0; i < NUM_PERIPHERALS; i++) { + if (!diag_check_update(i)) + continue; + mutex_lock(&driver->md_session_lock); + diag_send_log_mask_update(i, req->equip_id); + mutex_unlock(&driver->md_session_lock); + } +end: + return write_len; +} + +static int diag_cmd_disable_log_mask(unsigned char *src_buf, int src_len, + unsigned char *dest_buf, int dest_len, int pid) +{ + struct diag_mask_info *mask_info = NULL; + struct diag_log_mask_t *mask = NULL; + struct diag_log_config_rsp_t header; + int write_len = 0, i; + struct diag_md_session_t *info = NULL; + + mutex_lock(&driver->md_session_lock); + info = diag_md_session_get_pid(pid); + + mask_info = (!info) ? &log_mask : info->log_mask; + if (!src_buf || !dest_buf || src_len <= 0 || dest_len <= 0 || + !mask_info) { + pr_err("diag: Invalid input in %s, src_buf: %pK, src_len: %d, dest_buf: %pK, dest_len: %d, mask_info: %pK\n", + __func__, src_buf, src_len, dest_buf, dest_len, + mask_info); + mutex_unlock(&driver->md_session_lock); + return -EINVAL; + } + if (!mask_info->ptr) { + pr_err("diag: In %s, invalid input mask_info->ptr: %pK\n", + __func__, mask_info->ptr); + mutex_unlock(&driver->md_session_lock); + return -EINVAL; + } + mask = (struct diag_log_mask_t *)mask_info->ptr; + if (!mask->ptr) { + pr_err("diag: Invalid input in %s, mask->ptr: %pK\n", + __func__, mask->ptr); + mutex_unlock(&driver->md_session_lock); + return -EINVAL; + } + for (i = 0; i < MAX_EQUIP_ID; i++, mask++) { + if (mask && mask->ptr) { + mutex_lock(&mask->lock); + memset(mask->ptr, 0, mask->range); + mutex_unlock(&mask->lock); + } + } + mask_info->status = DIAG_CTRL_MASK_ALL_DISABLED; + mutex_unlock(&driver->md_session_lock); + if (diag_check_update(APPS_DATA)) + diag_update_userspace_clients(LOG_MASKS_TYPE); + + /* + * Apps processor must send the response to this command. Frame the + * response. + */ + header.cmd_code = DIAG_CMD_LOG_CONFIG; + header.padding[0] = 0; + header.padding[1] = 0; + header.padding[2] = 0; + header.sub_cmd = DIAG_CMD_OP_LOG_DISABLE; + header.status = LOG_STATUS_SUCCESS; + memcpy(dest_buf, &header, sizeof(struct diag_log_config_rsp_t)); + write_len += sizeof(struct diag_log_config_rsp_t); + for (i = 0; i < NUM_PERIPHERALS; i++) { + if (!diag_check_update(i)) + continue; + mutex_lock(&driver->md_session_lock); + diag_send_log_mask_update(i, ALL_EQUIP_ID); + mutex_unlock(&driver->md_session_lock); + } + + return write_len; +} + +int diag_create_msg_mask_table_entry(struct diag_msg_mask_t *msg_mask, + struct diag_ssid_range_t *range) +{ + if (!msg_mask || !range) + return -EIO; + if (range->ssid_last < range->ssid_first) + return -EINVAL; + msg_mask->ssid_first = range->ssid_first; + msg_mask->ssid_last = range->ssid_last; + msg_mask->ssid_last_tools = range->ssid_last; + msg_mask->range = msg_mask->ssid_last - msg_mask->ssid_first + 1; + if (msg_mask->range < MAX_SSID_PER_RANGE) + msg_mask->range = MAX_SSID_PER_RANGE; + msg_mask->range_tools = msg_mask->range; + mutex_init(&msg_mask->lock); + if (msg_mask->range > 0) { + msg_mask->ptr = kzalloc(msg_mask->range * sizeof(uint32_t), + GFP_KERNEL); + if (!msg_mask->ptr) + return -ENOMEM; + kmemleak_not_leak(msg_mask->ptr); + } + return 0; +} + +static int diag_create_msg_mask_table(void) +{ + int i; + int err = 0; + struct diag_msg_mask_t *mask = (struct diag_msg_mask_t *)msg_mask.ptr; + struct diag_ssid_range_t range; + + mutex_lock(&msg_mask.lock); + mutex_lock(&driver->msg_mask_lock); + driver->msg_mask_tbl_count = MSG_MASK_TBL_CNT; + for (i = 0; (i < driver->msg_mask_tbl_count) && mask; + i++, mask++) { + range.ssid_first = msg_mask_tbl[i].ssid_first; + range.ssid_last = msg_mask_tbl[i].ssid_last; + err = diag_create_msg_mask_table_entry(mask, &range); + if (err) + break; + } + mutex_unlock(&driver->msg_mask_lock); + mutex_unlock(&msg_mask.lock); + return err; +} + +static int diag_create_build_time_mask(void) +{ + int i; + int err = 0; + const uint32_t *tbl = NULL; + uint32_t tbl_size = 0; + struct diag_msg_mask_t *build_mask = NULL; + struct diag_ssid_range_t range; + + mutex_lock(&msg_bt_mask.lock); + mutex_lock(&driver->msg_mask_lock); + driver->bt_msg_mask_tbl_count = MSG_MASK_TBL_CNT; + build_mask = (struct diag_msg_mask_t *)msg_bt_mask.ptr; + for (i = 0; (i < driver->bt_msg_mask_tbl_count) && build_mask; + i++, build_mask++) { + range.ssid_first = msg_mask_tbl[i].ssid_first; + range.ssid_last = msg_mask_tbl[i].ssid_last; + err = diag_create_msg_mask_table_entry(build_mask, &range); + if (err) + break; + switch (build_mask->ssid_first) { + case MSG_SSID_0: + tbl = msg_bld_masks_0; + tbl_size = sizeof(msg_bld_masks_0); + break; + case MSG_SSID_1: + tbl = msg_bld_masks_1; + tbl_size = sizeof(msg_bld_masks_1); + break; + case MSG_SSID_2: + tbl = msg_bld_masks_2; + tbl_size = sizeof(msg_bld_masks_2); + break; + case MSG_SSID_3: + tbl = msg_bld_masks_3; + tbl_size = sizeof(msg_bld_masks_3); + break; + case MSG_SSID_4: + tbl = msg_bld_masks_4; + tbl_size = sizeof(msg_bld_masks_4); + break; + case MSG_SSID_5: + tbl = msg_bld_masks_5; + tbl_size = sizeof(msg_bld_masks_5); + break; + case MSG_SSID_6: + tbl = msg_bld_masks_6; + tbl_size = sizeof(msg_bld_masks_6); + break; + case MSG_SSID_7: + tbl = msg_bld_masks_7; + tbl_size = sizeof(msg_bld_masks_7); + break; + case MSG_SSID_8: + tbl = msg_bld_masks_8; + tbl_size = sizeof(msg_bld_masks_8); + break; + case MSG_SSID_9: + tbl = msg_bld_masks_9; + tbl_size = sizeof(msg_bld_masks_9); + break; + case MSG_SSID_10: + tbl = msg_bld_masks_10; + tbl_size = sizeof(msg_bld_masks_10); + break; + case MSG_SSID_11: + tbl = msg_bld_masks_11; + tbl_size = sizeof(msg_bld_masks_11); + break; + case MSG_SSID_12: + tbl = msg_bld_masks_12; + tbl_size = sizeof(msg_bld_masks_12); + break; + case MSG_SSID_13: + tbl = msg_bld_masks_13; + tbl_size = sizeof(msg_bld_masks_13); + break; + case MSG_SSID_14: + tbl = msg_bld_masks_14; + tbl_size = sizeof(msg_bld_masks_14); + break; + case MSG_SSID_15: + tbl = msg_bld_masks_15; + tbl_size = sizeof(msg_bld_masks_15); + break; + case MSG_SSID_16: + tbl = msg_bld_masks_16; + tbl_size = sizeof(msg_bld_masks_16); + break; + case MSG_SSID_17: + tbl = msg_bld_masks_17; + tbl_size = sizeof(msg_bld_masks_17); + break; + case MSG_SSID_18: + tbl = msg_bld_masks_18; + tbl_size = sizeof(msg_bld_masks_18); + break; + case MSG_SSID_19: + tbl = msg_bld_masks_19; + tbl_size = sizeof(msg_bld_masks_19); + break; + case MSG_SSID_20: + tbl = msg_bld_masks_20; + tbl_size = sizeof(msg_bld_masks_20); + break; + case MSG_SSID_21: + tbl = msg_bld_masks_21; + tbl_size = sizeof(msg_bld_masks_21); + break; + case MSG_SSID_22: + tbl = msg_bld_masks_22; + tbl_size = sizeof(msg_bld_masks_22); + break; + } + if (!tbl) + continue; + if (tbl_size > build_mask->range * sizeof(uint32_t)) { + pr_warn("diag: In %s, table %d has more ssid than max, ssid_first: %d, ssid_last: %d\n", + __func__, i, build_mask->ssid_first, + build_mask->ssid_last); + tbl_size = build_mask->range * sizeof(uint32_t); + } + memcpy(build_mask->ptr, tbl, tbl_size); + } + mutex_unlock(&driver->msg_mask_lock); + mutex_unlock(&msg_bt_mask.lock); + return err; +} + +static int diag_create_log_mask_table(void) +{ + struct diag_log_mask_t *mask = NULL; + uint8_t i; + int err = 0; + + mutex_lock(&log_mask.lock); + mask = (struct diag_log_mask_t *)(log_mask.ptr); + for (i = 0; (i < MAX_EQUIP_ID) && mask; i++, mask++) { + mask->equip_id = i; + mask->num_items = LOG_GET_ITEM_NUM(log_code_last_tbl[i]); + mask->num_items_tools = mask->num_items; + mutex_init(&mask->lock); + if (LOG_ITEMS_TO_SIZE(mask->num_items) > MAX_ITEMS_PER_EQUIP_ID) + mask->range = LOG_ITEMS_TO_SIZE(mask->num_items); + else + mask->range = MAX_ITEMS_PER_EQUIP_ID; + mask->range_tools = mask->range; + mask->ptr = kzalloc(mask->range, GFP_KERNEL); + if (!mask->ptr) { + err = -ENOMEM; + break; + } + kmemleak_not_leak(mask->ptr); + } + mutex_unlock(&log_mask.lock); + return err; +} + +static int __diag_mask_init(struct diag_mask_info *mask_info, int mask_len, + int update_buf_len) +{ + if (!mask_info || mask_len < 0 || update_buf_len < 0) + return -EINVAL; + + mask_info->status = DIAG_CTRL_MASK_INVALID; + mask_info->mask_len = mask_len; + mask_info->update_buf_len = update_buf_len; + if (mask_len > 0) { + mask_info->ptr = kzalloc(mask_len, GFP_KERNEL); + if (!mask_info->ptr) + return -ENOMEM; + kmemleak_not_leak(mask_info->ptr); + } + if (update_buf_len > 0) { + mask_info->update_buf = kzalloc(update_buf_len, GFP_KERNEL); + if (!mask_info->update_buf) { + kfree(mask_info->ptr); + return -ENOMEM; + } + kmemleak_not_leak(mask_info->update_buf); + } + return 0; +} + +static void __diag_mask_exit(struct diag_mask_info *mask_info) +{ + if (!mask_info || !mask_info->ptr) + return; + + mutex_lock(&mask_info->lock); + kfree(mask_info->ptr); + mask_info->ptr = NULL; + kfree(mask_info->update_buf); + mask_info->update_buf = NULL; + mutex_unlock(&mask_info->lock); +} + +int diag_log_mask_copy(struct diag_mask_info *dest, struct diag_mask_info *src) +{ + int i; + int err = 0; + struct diag_log_mask_t *src_mask = NULL; + struct diag_log_mask_t *dest_mask = NULL; + + if (!src || !dest) + return -EINVAL; + + mutex_init(&dest->lock); + err = __diag_mask_init(dest, LOG_MASK_SIZE, APPS_BUF_SIZE); + if (err) + return err; + + mutex_lock(&dest->lock); + src_mask = (struct diag_log_mask_t *)(src->ptr); + dest_mask = (struct diag_log_mask_t *)(dest->ptr); + + dest->mask_len = src->mask_len; + dest->status = src->status; + + for (i = 0; i < MAX_EQUIP_ID; i++, src_mask++, dest_mask++) { + dest_mask->equip_id = src_mask->equip_id; + dest_mask->num_items = src_mask->num_items; + dest_mask->num_items_tools = src_mask->num_items_tools; + mutex_init(&dest_mask->lock); + dest_mask->range = src_mask->range; + dest_mask->range_tools = src_mask->range_tools; + dest_mask->ptr = kzalloc(dest_mask->range_tools, GFP_KERNEL); + if (!dest_mask->ptr) { + err = -ENOMEM; + break; + } + kmemleak_not_leak(dest_mask->ptr); + memcpy(dest_mask->ptr, src_mask->ptr, dest_mask->range_tools); + } + mutex_unlock(&dest->lock); + + return err; +} + +void diag_log_mask_free(struct diag_mask_info *mask_info) +{ + int i; + struct diag_log_mask_t *mask = NULL; + + if (!mask_info || !mask_info->ptr) + return; + + mutex_lock(&mask_info->lock); + mask = (struct diag_log_mask_t *)mask_info->ptr; + if (!mask->ptr) { + pr_err("diag: Invalid input in %s, mask->ptr: %pK\n", + __func__, mask->ptr); + mutex_unlock(&mask_info->lock); + return; + } + for (i = 0; i < MAX_EQUIP_ID; i++, mask++) { + kfree(mask->ptr); + mask->ptr = NULL; + } + mutex_unlock(&mask_info->lock); + + __diag_mask_exit(mask_info); + +} + +static int diag_msg_mask_init(void) +{ + int err = 0; + int i; + + mutex_init(&msg_mask.lock); + err = __diag_mask_init(&msg_mask, MSG_MASK_SIZE, APPS_BUF_SIZE); + if (err) + return err; + + err = diag_create_msg_mask_table(); + if (err) { + pr_err("diag: Unable to create msg masks, err: %d\n", err); + return err; + } + mutex_lock(&driver->msg_mask_lock); + driver->msg_mask = &msg_mask; + for (i = 0; i < NUM_PERIPHERALS; i++) + driver->max_ssid_count[i] = 0; + mutex_unlock(&driver->msg_mask_lock); + + return 0; +} + +int diag_msg_mask_copy(struct diag_md_session_t *new_session, + struct diag_mask_info *dest, struct diag_mask_info *src) +{ + int i; + int err = 0; + struct diag_msg_mask_t *src_mask = NULL; + struct diag_msg_mask_t *dest_mask = NULL; + struct diag_ssid_range_t range; + + if (!src || !dest) + return -EINVAL; + + mutex_init(&dest->lock); + mutex_lock(&dest->lock); + mutex_lock(&driver->msg_mask_lock); + new_session->msg_mask_tbl_count = + driver->msg_mask_tbl_count; + err = __diag_mask_init(dest, + (new_session->msg_mask_tbl_count * + sizeof(struct diag_msg_mask_t)), APPS_BUF_SIZE); + if (err) { + mutex_unlock(&driver->msg_mask_lock); + mutex_unlock(&dest->lock); + return err; + } + src_mask = (struct diag_msg_mask_t *)src->ptr; + dest_mask = (struct diag_msg_mask_t *)dest->ptr; + + dest->mask_len = src->mask_len; + dest->status = src->status; + for (i = 0; i < new_session->msg_mask_tbl_count; i++) { + range.ssid_first = src_mask->ssid_first; + range.ssid_last = src_mask->ssid_last; + err = diag_create_msg_mask_table_entry(dest_mask, &range); + if (err) + break; + memcpy(dest_mask->ptr, src_mask->ptr, + dest_mask->range * sizeof(uint32_t)); + src_mask++; + dest_mask++; + } + mutex_unlock(&driver->msg_mask_lock); + mutex_unlock(&dest->lock); + return err; +} + +void diag_msg_mask_free(struct diag_mask_info *mask_info, + struct diag_md_session_t *session_info) +{ + int i; + struct diag_msg_mask_t *mask = NULL; + uint8_t msg_mask_tbl_count = 0; + + if (!mask_info || !mask_info->ptr) + return; + mutex_lock(&mask_info->lock); + mutex_lock(&driver->msg_mask_lock); + mask = (struct diag_msg_mask_t *)mask_info->ptr; + if (!mask->ptr) { + pr_err("diag: Invalid input in %s, mask->ptr: %pK\n", + __func__, mask->ptr); + mutex_unlock(&driver->msg_mask_lock); + mutex_unlock(&mask_info->lock); + return; + } + msg_mask_tbl_count = (session_info) ? + session_info->msg_mask_tbl_count : + driver->msg_mask_tbl_count; + for (i = 0; i < msg_mask_tbl_count; i++, mask++) { + kfree(mask->ptr); + mask->ptr = NULL; + } + mutex_unlock(&driver->msg_mask_lock); + mutex_unlock(&mask_info->lock); + __diag_mask_exit(mask_info); +} + +static void diag_msg_mask_exit(void) +{ + int i; + struct diag_msg_mask_t *mask = NULL; + mutex_lock(&driver->msg_mask_lock); + mask = (struct diag_msg_mask_t *)(msg_mask.ptr); + if (mask) { + for (i = 0; i < driver->msg_mask_tbl_count; i++, mask++) + kfree(mask->ptr); + kfree(msg_mask.ptr); + msg_mask.ptr = NULL; + } + kfree(msg_mask.update_buf); + msg_mask.update_buf = NULL; + mutex_unlock(&driver->msg_mask_lock); +} + +static int diag_build_time_mask_init(void) +{ + int err = 0; + + /* There is no need for update buffer for Build Time masks */ + mutex_init(&msg_bt_mask.lock); + err = __diag_mask_init(&msg_bt_mask, MSG_MASK_SIZE, 0); + if (err) + return err; + err = diag_create_build_time_mask(); + if (err) { + pr_err("diag: Unable to create msg build time masks, err: %d\n", + err); + return err; + } + driver->build_time_mask = &msg_bt_mask; + return 0; +} + +static void diag_build_time_mask_exit(void) +{ + int i; + struct diag_msg_mask_t *mask = NULL; + mutex_lock(&driver->msg_mask_lock); + mask = (struct diag_msg_mask_t *)(msg_bt_mask.ptr); + if (mask) { + for (i = 0; i < driver->bt_msg_mask_tbl_count; i++, mask++) + kfree(mask->ptr); + kfree(msg_bt_mask.ptr); + msg_bt_mask.ptr = NULL; + } + mutex_unlock(&driver->msg_mask_lock); +} + +static int diag_log_mask_init(void) +{ + int err = 0; + int i; + + mutex_init(&log_mask.lock); + err = __diag_mask_init(&log_mask, LOG_MASK_SIZE, APPS_BUF_SIZE); + if (err) + return err; + err = diag_create_log_mask_table(); + if (err) + return err; + driver->log_mask = &log_mask; + + for (i = 0; i < NUM_PERIPHERALS; i++) + driver->num_equip_id[i] = 0; + + return 0; +} + +static void diag_log_mask_exit(void) +{ + int i; + struct diag_log_mask_t *mask = NULL; + + mask = (struct diag_log_mask_t *)(log_mask.ptr); + if (mask) { + for (i = 0; i < MAX_EQUIP_ID; i++, mask++) + kfree(mask->ptr); + kfree(log_mask.ptr); + } + + kfree(log_mask.update_buf); +} + +static int diag_event_mask_init(void) +{ + int err = 0; + int i; + + mutex_init(&event_mask.lock); + err = __diag_mask_init(&event_mask, EVENT_MASK_SIZE, APPS_BUF_SIZE); + if (err) + return err; + driver->event_mask_size = EVENT_MASK_SIZE; + driver->last_event_id = APPS_EVENT_LAST_ID; + driver->event_mask = &event_mask; + + for (i = 0; i < NUM_PERIPHERALS; i++) + driver->num_event_id[i] = 0; + + return 0; +} + +int diag_event_mask_copy(struct diag_mask_info *dest, + struct diag_mask_info *src) +{ + int err = 0; + + if (!src || !dest) + return -EINVAL; + + mutex_init(&dest->lock); + err = __diag_mask_init(dest, EVENT_MASK_SIZE, APPS_BUF_SIZE); + if (err) + return err; + + mutex_lock(&dest->lock); + dest->mask_len = src->mask_len; + dest->status = src->status; + memcpy(dest->ptr, src->ptr, dest->mask_len); + mutex_unlock(&dest->lock); + + return err; +} + +void diag_event_mask_free(struct diag_mask_info *mask_info) +{ + if (!mask_info) + return; + + __diag_mask_exit(mask_info); +} + +static void diag_event_mask_exit(void) +{ + kfree(event_mask.ptr); + kfree(event_mask.update_buf); +} + +int diag_copy_to_user_msg_mask(char __user *buf, size_t count, + struct diag_md_session_t *info) +{ + int i; + int err = 0; + int len = 0; + int copy_len = 0; + int total_len = 0; + struct diag_msg_mask_userspace_t header; + struct diag_mask_info *mask_info = NULL; + struct diag_msg_mask_t *mask = NULL; + unsigned char *ptr = NULL; + uint8_t msg_mask_tbl_count = 0; + + if (!buf || count == 0) + return -EINVAL; + + mask_info = (!info) ? &msg_mask : info->msg_mask; + if (!mask_info) + return -EIO; + + if (!mask_info->ptr || !mask_info->update_buf) { + pr_err("diag: In %s, invalid input mask_info->ptr: %pK, mask_info->update_buf: %pK\n", + __func__, mask_info->ptr, mask_info->update_buf); + return -EINVAL; + } + mutex_lock(&driver->diag_maskclear_mutex); + if (driver->mask_clear) { + DIAG_LOG(DIAG_DEBUG_PERIPHERALS, + "diag:%s: count = %zu\n", __func__, count); + mutex_unlock(&driver->diag_maskclear_mutex); + return -EIO; + } + mutex_unlock(&driver->diag_maskclear_mutex); + mutex_lock(&mask_info->lock); + mutex_lock(&driver->msg_mask_lock); + + mask = (struct diag_msg_mask_t *)(mask_info->ptr); + if (!mask->ptr) { + pr_err("diag: Invalid input in %s, mask->ptr: %pK\n", + __func__, mask->ptr); + mutex_unlock(&driver->msg_mask_lock); + mutex_unlock(&mask_info->lock); + return -EINVAL; + } + msg_mask_tbl_count = (info) ? info->msg_mask_tbl_count : + driver->msg_mask_tbl_count; + for (i = 0; i < msg_mask_tbl_count; i++, mask++) { + if (!mask->ptr) + continue; + ptr = mask_info->update_buf; + len = 0; + mutex_lock(&mask->lock); + header.ssid_first = mask->ssid_first; + header.ssid_last = mask->ssid_last_tools; + header.range = mask->range_tools; + memcpy(ptr, &header, sizeof(header)); + len += sizeof(header); + copy_len = (sizeof(uint32_t) * mask->range_tools); + if ((len + copy_len) > mask_info->update_buf_len) { + pr_err("diag: In %s, no space to update msg mask, first: %d, last: %d\n", + __func__, mask->ssid_first, + mask->ssid_last_tools); + mutex_unlock(&mask->lock); + continue; + } + memcpy(ptr + len, mask->ptr, copy_len); + len += copy_len; + mutex_unlock(&mask->lock); + /* + sizeof(int) to account for data_type already in buf */ + if (total_len + sizeof(int) + len > count) { + pr_err("diag: In %s, unable to send msg masks to user space, total_len: %d, count: %zu\n", + __func__, total_len, count); + err = -ENOMEM; + break; + } + err = copy_to_user(buf + total_len, (void *)ptr, len); + if (err) { + pr_err("diag: In %s Unable to send msg masks to user space clients, err: %d\n", + __func__, err); + break; + } + total_len += len; + } + mutex_unlock(&driver->msg_mask_lock); + mutex_unlock(&mask_info->lock); + return err ? err : total_len; +} + +int diag_copy_to_user_log_mask(char __user *buf, size_t count, + struct diag_md_session_t *info) +{ + int i; + int err = 0; + int len = 0; + int copy_len = 0; + int total_len = 0; + struct diag_log_mask_userspace_t header; + struct diag_log_mask_t *mask = NULL; + struct diag_mask_info *mask_info = NULL; + unsigned char *ptr = NULL; + + if (!buf || count == 0) + return -EINVAL; + + mask_info = (!info) ? &log_mask : info->log_mask; + if (!mask_info) + return -EIO; + + if (!mask_info->ptr || !mask_info->update_buf) { + pr_err("diag: In %s, invalid input mask_info->ptr: %pK, mask_info->update_buf: %pK\n", + __func__, mask_info->ptr, mask_info->update_buf); + return -EINVAL; + } + + mutex_lock(&mask_info->lock); + mask = (struct diag_log_mask_t *)(mask_info->ptr); + if (!mask->ptr) { + pr_err("diag: Invalid input in %s, mask->ptr: %pK\n", + __func__, mask->ptr); + mutex_unlock(&mask_info->lock); + return -EINVAL; + } + for (i = 0; i < MAX_EQUIP_ID; i++, mask++) { + if (!mask->ptr) + continue; + ptr = mask_info->update_buf; + len = 0; + mutex_lock(&mask->lock); + header.equip_id = mask->equip_id; + header.num_items = mask->num_items_tools; + memcpy(ptr, &header, sizeof(header)); + len += sizeof(header); + copy_len = LOG_ITEMS_TO_SIZE(header.num_items); + if ((len + copy_len) > mask_info->update_buf_len) { + pr_err("diag: In %s, no space to update log mask, equip_id: %d\n", + __func__, mask->equip_id); + mutex_unlock(&mask->lock); + continue; + } + memcpy(ptr + len, mask->ptr, copy_len); + len += copy_len; + mutex_unlock(&mask->lock); + /* + sizeof(int) to account for data_type already in buf */ + if (total_len + sizeof(int) + len > count) { + pr_err("diag: In %s, unable to send log masks to user space, total_len: %d, count: %zu\n", + __func__, total_len, count); + err = -ENOMEM; + break; + } + err = copy_to_user(buf + total_len, (void *)ptr, len); + if (err) { + pr_err("diag: In %s Unable to send log masks to user space clients, err: %d\n", + __func__, err); + break; + } + total_len += len; + } + mutex_unlock(&mask_info->lock); + + return err ? err : total_len; +} + +void diag_send_updates_peripheral(uint8_t peripheral) +{ + diag_send_feature_mask_update(peripheral); + if (driver->time_sync_enabled) + diag_send_time_sync_update(peripheral); + mutex_lock(&driver->md_session_lock); + diag_send_msg_mask_update(peripheral, ALL_SSID, ALL_SSID); + diag_send_log_mask_update(peripheral, ALL_EQUIP_ID); + diag_send_event_mask_update(peripheral); + mutex_unlock(&driver->md_session_lock); + diag_send_real_time_update(peripheral, + driver->real_time_mode[DIAG_LOCAL_PROC]); + diag_send_peripheral_buffering_mode( + &driver->buffering_mode[peripheral]); +} + +int diag_process_apps_masks(unsigned char *buf, int len, int pid) +{ + int size = 0; + int sub_cmd = 0; + int (*hdlr)(unsigned char *src_buf, int src_len, + unsigned char *dest_buf, int dest_len, int pid) = NULL; + + if (!buf || len <= 0) + return -EINVAL; + + if (*buf == DIAG_CMD_LOG_CONFIG) { + sub_cmd = *(int *)(buf + sizeof(int)); + switch (sub_cmd) { + case DIAG_CMD_OP_LOG_DISABLE: + hdlr = diag_cmd_disable_log_mask; + break; + case DIAG_CMD_OP_GET_LOG_RANGE: + hdlr = diag_cmd_get_log_range; + break; + case DIAG_CMD_OP_SET_LOG_MASK: + hdlr = diag_cmd_set_log_mask; + break; + case DIAG_CMD_OP_GET_LOG_MASK: + hdlr = diag_cmd_get_log_mask; + break; + } + } else if (*buf == DIAG_CMD_MSG_CONFIG) { + sub_cmd = *(uint8_t *)(buf + sizeof(uint8_t)); + switch (sub_cmd) { + case DIAG_CMD_OP_GET_SSID_RANGE: + hdlr = diag_cmd_get_ssid_range; + break; + case DIAG_CMD_OP_GET_BUILD_MASK: + hdlr = diag_cmd_get_build_mask; + break; + case DIAG_CMD_OP_GET_MSG_MASK: + hdlr = diag_cmd_get_msg_mask; + break; + case DIAG_CMD_OP_SET_MSG_MASK: + hdlr = diag_cmd_set_msg_mask; + break; + case DIAG_CMD_OP_SET_ALL_MSG_MASK: + hdlr = diag_cmd_set_all_msg_mask; + break; + } + } else if (*buf == DIAG_CMD_GET_EVENT_MASK) { + hdlr = diag_cmd_get_event_mask; + } else if (*buf == DIAG_CMD_SET_EVENT_MASK) { + hdlr = diag_cmd_update_event_mask; + } else if (*buf == DIAG_CMD_EVENT_TOGGLE) { + hdlr = diag_cmd_toggle_events; + } + + if (hdlr) + size = hdlr(buf, len, driver->apps_rsp_buf, + DIAG_MAX_RSP_SIZE, pid); + + return (size > 0) ? size : 0; +} + +int diag_masks_init(void) +{ + int err = 0; + err = diag_msg_mask_init(); + if (err) + goto fail; + + err = diag_build_time_mask_init(); + if (err) + goto fail; + + err = diag_log_mask_init(); + if (err) + goto fail; + + err = diag_event_mask_init(); + if (err) + goto fail; + + if (driver->buf_feature_mask_update == NULL) { + driver->buf_feature_mask_update = kzalloc(sizeof( + struct diag_ctrl_feature_mask) + + FEATURE_MASK_LEN, GFP_KERNEL); + if (driver->buf_feature_mask_update == NULL) + goto fail; + kmemleak_not_leak(driver->buf_feature_mask_update); + } + + return 0; +fail: + pr_err("diag: Could not initialize diag mask buffers\n"); + diag_masks_exit(); + return -ENOMEM; +} + +void diag_masks_exit(void) +{ + diag_msg_mask_exit(); + diag_build_time_mask_exit(); + diag_log_mask_exit(); + diag_event_mask_exit(); + kfree(driver->buf_feature_mask_update); +} diff -Nruw linux-4.4.115-fbx/drivers/char/diag./diag_masks.h linux-4.4.115-fbx/drivers/char/diag/diag_masks.h --- linux-4.4.115-fbx/drivers/char/diag./diag_masks.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-4.4.115-fbx/drivers/char/diag/diag_masks.h 2019-10-29 09:26:23.449201280 +0100 @@ -0,0 +1,180 @@ +/* Copyright (c) 2013-2015, 2018 The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef DIAG_MASKS_H +#define DIAG_MASKS_H + +#include "diagfwd.h" + +struct diag_log_mask_t { + uint8_t equip_id; + uint32_t num_items; + uint32_t num_items_tools; + uint32_t range; + uint32_t range_tools; + struct mutex lock; + uint8_t *ptr; +}; + +struct diag_ssid_range_t { + uint16_t ssid_first; + uint16_t ssid_last; +} __packed; + +struct diag_msg_mask_t { + uint32_t ssid_first; + uint32_t ssid_last; + uint32_t ssid_last_tools; + uint32_t range; + uint32_t range_tools; + struct mutex lock; + uint32_t *ptr; +}; + +struct diag_log_config_req_t { + uint8_t cmd_code; + uint8_t padding[3]; + uint32_t sub_cmd; + uint32_t equip_id; + uint32_t num_items; +} __packed; + +struct diag_log_config_rsp_t { + uint8_t cmd_code; + uint8_t padding[3]; + uint32_t sub_cmd; + uint32_t status; +} __packed; + +struct diag_log_config_set_rsp_t { + uint8_t cmd_code; + uint8_t padding[3]; + uint32_t sub_cmd; + uint32_t status; + uint32_t equip_id; + uint32_t num_items; +} __packed; + +struct diag_log_on_demand_rsp_t { + uint8_t cmd_code; + uint16_t log_code; + uint8_t status; +} __packed; + +struct diag_event_report_t { + uint8_t cmd_code; + uint16_t padding; +} __packed; + +struct diag_event_mask_config_t { + uint8_t cmd_code; + uint8_t status; + uint16_t padding; + uint16_t num_bits; +} __packed; + +struct diag_msg_config_rsp_t { + uint8_t cmd_code; + uint8_t sub_cmd; + uint8_t status; + uint8_t padding; + uint32_t rt_mask; +} __packed; + +struct diag_msg_ssid_query_t { + uint8_t cmd_code; + uint8_t sub_cmd; + uint8_t status; + uint8_t padding; + uint32_t count; +} __packed; + +struct diag_build_mask_req_t { + uint8_t cmd_code; + uint8_t sub_cmd; + uint16_t ssid_first; + uint16_t ssid_last; +} __packed; + +struct diag_msg_build_mask_t { + uint8_t cmd_code; + uint8_t sub_cmd; + uint16_t ssid_first; + uint16_t ssid_last; + uint8_t status; + uint8_t padding; +} __packed; + +struct diag_msg_mask_userspace_t { + uint32_t ssid_first; + uint32_t ssid_last; + uint32_t range; +} __packed; + +struct diag_log_mask_userspace_t { + uint8_t equip_id; + uint32_t num_items; +} __packed; + +#define MAX_EQUIP_ID 16 +#define MSG_MASK_SIZE (MSG_MASK_TBL_CNT * sizeof(struct diag_msg_mask_t)) +#define LOG_MASK_SIZE (MAX_EQUIP_ID * sizeof(struct diag_log_mask_t)) +#define EVENT_MASK_SIZE 513 +#define MAX_ITEMS_PER_EQUIP_ID 512 +#define MAX_ITEMS_ALLOWED 0xFFF + +#define LOG_MASK_CTRL_HEADER_LEN 11 +#define MSG_MASK_CTRL_HEADER_LEN 11 +#define EVENT_MASK_CTRL_HEADER_LEN 7 + +#define LOG_STATUS_SUCCESS 0 +#define LOG_STATUS_INVALID 1 +#define LOG_STATUS_FAIL 2 + +#define MSG_STATUS_FAIL 0 +#define MSG_STATUS_SUCCESS 1 + +#define EVENT_STATUS_SUCCESS 0 +#define EVENT_STATUS_FAIL 1 + +#define DIAG_CTRL_MASK_INVALID 0 +#define DIAG_CTRL_MASK_ALL_DISABLED 1 +#define DIAG_CTRL_MASK_ALL_ENABLED 2 +#define DIAG_CTRL_MASK_VALID 3 + +extern struct diag_mask_info msg_mask; +extern struct diag_mask_info msg_bt_mask; +extern struct diag_mask_info log_mask; +extern struct diag_mask_info event_mask; + +int diag_masks_init(void); +void diag_masks_exit(void); +int diag_log_mask_copy(struct diag_mask_info *dest, + struct diag_mask_info *src); +int diag_msg_mask_copy(struct diag_md_session_t *new_session, + struct diag_mask_info *dest, struct diag_mask_info *src); +int diag_event_mask_copy(struct diag_mask_info *dest, + struct diag_mask_info *src); +void diag_log_mask_free(struct diag_mask_info *mask_info); +void diag_msg_mask_free(struct diag_mask_info *mask_info, + struct diag_md_session_t *session_info); +void diag_event_mask_free(struct diag_mask_info *mask_info); +int diag_process_apps_masks(unsigned char *buf, int len, int pid); +void diag_send_updates_peripheral(uint8_t peripheral); + +extern int diag_create_msg_mask_table_entry(struct diag_msg_mask_t *msg_mask, + struct diag_ssid_range_t *range); +extern int diag_copy_to_user_msg_mask(char __user *buf, size_t count, + struct diag_md_session_t *info); +extern int diag_copy_to_user_log_mask(char __user *buf, size_t count, + struct diag_md_session_t *info); +#endif diff -Nruw linux-4.4.115-fbx/drivers/char/diag./diagmem.c linux-4.4.115-fbx/drivers/char/diag/diagmem.c --- linux-4.4.115-fbx/drivers/char/diag./diagmem.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-4.4.115-fbx/drivers/char/diag/diagmem.c 2019-01-22 16:16:22.963241516 +0100 @@ -0,0 +1,294 @@ +/* Copyright (c) 2008-2014, 2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "diagchar.h" +#include "diagmem.h" + +struct diag_mempool_t diag_mempools[NUM_MEMORY_POOLS] = { + { + .id = POOL_TYPE_COPY, + .name = "POOL_COPY", + .pool = NULL, + .itemsize = 0, + .poolsize = 0, + .count = 0 + }, + { + .id = POOL_TYPE_HDLC, + .name = "POOL_HDLC", + .pool = NULL, + .itemsize = 0, + .poolsize = 0, + .count = 0 + }, + { + .id = POOL_TYPE_USER, + .name = "POOL_USER", + .pool = NULL, + .itemsize = 0, + .poolsize = 0, + .count = 0 + }, + { + .id = POOL_TYPE_MUX_APPS, + .name = "POOL_MUX_APPS", + .pool = NULL, + .itemsize = 0, + .poolsize = 0, + .count = 0 + }, + { + .id = POOL_TYPE_DCI, + .name = "POOL_DCI", + .pool = NULL, + .itemsize = 0, + .poolsize = 0, + .count = 0 + }, +#ifdef CONFIG_DIAGFWD_BRIDGE_CODE + { + .id = POOL_TYPE_MDM, + .name = "POOL_MDM", + .pool = NULL, + .itemsize = 0, + .poolsize = 0, + .count = 0 + }, + { + .id = POOL_TYPE_MDM2, + .name = "POOL_MDM2", + .pool = NULL, + .itemsize = 0, + .poolsize = 0, + .count = 0 + }, + { + .id = POOL_TYPE_MDM_DCI, + .name = "POOL_MDM_DCI", + .pool = NULL, + .itemsize = 0, + .poolsize = 0, + .count = 0 + }, + { + .id = POOL_TYPE_MDM2_DCI, + .name = "POOL_MDM2_DCI", + .pool = NULL, + .itemsize = 0, + .poolsize = 0, + .count = 0 + }, + { + .id = POOL_TYPE_MDM_MUX, + .name = "POOL_MDM_MUX", + .pool = NULL, + .itemsize = 0, + .poolsize = 0, + .count = 0 + }, + { + .id = POOL_TYPE_MDM2_MUX, + .name = "POOL_MDM2_MUX", + .pool = NULL, + .itemsize = 0, + .poolsize = 0, + .count = 0 + }, + { + .id = POOL_TYPE_MDM_DCI_WRITE, + .name = "POOL_MDM_DCI_WRITE", + .pool = NULL, + .itemsize = 0, + .poolsize = 0, + .count = 0 + }, + { + .id = POOL_TYPE_MDM2_DCI_WRITE, + .name = "POOL_MDM2_DCI_WRITE", + .pool = NULL, + .itemsize = 0, + .poolsize = 0, + .count = 0 + }, + { + .id = POOL_TYPE_QSC_MUX, + .name = "POOL_QSC_MUX", + .pool = NULL, + .itemsize = 0, + .poolsize = 0, + .count = 0 + } +#endif +}; + +void diagmem_setsize(int pool_idx, int itemsize, int poolsize) +{ + if (pool_idx < 0 || pool_idx >= NUM_MEMORY_POOLS) { + pr_err("diag: Invalid pool index %d in %s\n", pool_idx, + __func__); + return; + } + + diag_mempools[pool_idx].itemsize = itemsize; + diag_mempools[pool_idx].poolsize = poolsize; + pr_debug("diag: Mempool %s sizes: itemsize %d poolsize %d\n", + diag_mempools[pool_idx].name, diag_mempools[pool_idx].itemsize, + diag_mempools[pool_idx].poolsize); +} + +void *diagmem_alloc(struct diagchar_dev *driver, int size, int pool_type) +{ + void *buf = NULL; + int i = 0; + unsigned long flags; + struct diag_mempool_t *mempool = NULL; + + if (!driver) + return NULL; + + for (i = 0; i < NUM_MEMORY_POOLS; i++) { + mempool = &diag_mempools[i]; + if (pool_type != mempool->id) + continue; + if (!mempool->pool) { + pr_err_ratelimited("diag: %s mempool is not initialized yet\n", + mempool->name); + break; + } + if (size == 0 || size > mempool->itemsize) { + pr_err_ratelimited("diag: cannot alloc from mempool %s, invalid size: %d\n", + mempool->name, size); + break; + } + spin_lock_irqsave(&mempool->lock, flags); + if (mempool->count < mempool->poolsize) { + atomic_add(1, (atomic_t *)&mempool->count); + buf = mempool_alloc(mempool->pool, GFP_ATOMIC); + kmemleak_not_leak(buf); + } + spin_unlock_irqrestore(&mempool->lock, flags); + if (!buf) { + pr_debug_ratelimited("diag: Unable to allocate buffer from memory pool %s, size: %d/%d count: %d/%d\n", + mempool->name, + size, mempool->itemsize, + mempool->count, + mempool->poolsize); + } + break; + } + + return buf; +} + +void diagmem_free(struct diagchar_dev *driver, void *buf, int pool_type) +{ + int i = 0; + unsigned long flags; + struct diag_mempool_t *mempool = NULL; + + if (!driver || !buf) + return; + + for (i = 0; i < NUM_MEMORY_POOLS; i++) { + mempool = &diag_mempools[i]; + if (pool_type != mempool->id) + continue; + if (!mempool->pool) { + pr_err_ratelimited("diag: %s mempool is not initialized yet\n", + mempool->name); + break; + } + spin_lock_irqsave(&mempool->lock, flags); + if (mempool->count > 0) { + mempool_free(buf, mempool->pool); + atomic_add(-1, (atomic_t *)&mempool->count); + } else { + pr_err_ratelimited("diag: Attempting to free items from %s mempool which is already empty\n", + mempool->name); + } + spin_unlock_irqrestore(&mempool->lock, flags); + break; + } +} + +void diagmem_init(struct diagchar_dev *driver, int index) +{ + struct diag_mempool_t *mempool = NULL; + if (!driver) + return; + + if (index < 0 || index >= NUM_MEMORY_POOLS) { + pr_err("diag: In %s, Invalid index %d\n", __func__, index); + return; + } + + mempool = &diag_mempools[index]; + if (mempool->pool) { + pr_debug("diag: mempool %s is already initialized\n", + mempool->name); + return; + } + if (mempool->itemsize <= 0 || mempool->poolsize <= 0) { + pr_err("diag: Unable to initialize %s mempool, itemsize: %d poolsize: %d\n", + mempool->name, mempool->itemsize, + mempool->poolsize); + return; + } + + mempool->pool = mempool_create_kmalloc_pool(mempool->poolsize, + mempool->itemsize); + if (!mempool->pool) + pr_err("diag: cannot allocate %s mempool\n", mempool->name); + else + kmemleak_not_leak(mempool->pool); + + spin_lock_init(&mempool->lock); +} + +void diagmem_exit(struct diagchar_dev *driver, int index) +{ + unsigned long flags; + struct diag_mempool_t *mempool = NULL; + + if (!driver) + return; + + if (index < 0 || index >= NUM_MEMORY_POOLS) { + pr_err("diag: In %s, Invalid index %d\n", __func__, index); + return; + } + + mempool = &diag_mempools[index]; + spin_lock_irqsave(&mempool->lock, flags); + if (mempool->count == 0 && mempool->pool != NULL) { + mempool_destroy(mempool->pool); + mempool->pool = NULL; + } else { + pr_err("diag: Unable to destory %s pool, count: %d\n", + mempool->name, mempool->count); + } + spin_unlock_irqrestore(&mempool->lock, flags); +} + diff -Nruw linux-4.4.115-fbx/drivers/char/diag./diagmem.h linux-4.4.115-fbx/drivers/char/diag/diagmem.h --- linux-4.4.115-fbx/drivers/char/diag./diagmem.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-4.4.115-fbx/drivers/char/diag/diagmem.h 2019-01-22 16:16:22.963241516 +0100 @@ -0,0 +1,63 @@ +/* Copyright (c) 2008-2014, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef DIAGMEM_H +#define DIAGMEM_H +#include "diagchar.h" + +#define POOL_TYPE_COPY 0 +#define POOL_TYPE_HDLC 1 +#define POOL_TYPE_USER 2 +#define POOL_TYPE_MUX_APPS 3 +#define POOL_TYPE_DCI 4 +#define POOL_TYPE_LOCAL_LAST 5 + +#define POOL_TYPE_REMOTE_BASE POOL_TYPE_LOCAL_LAST +#define POOL_TYPE_MDM POOL_TYPE_REMOTE_BASE +#define POOL_TYPE_MDM2 (POOL_TYPE_REMOTE_BASE + 1) +#define POOL_TYPE_MDM_DCI (POOL_TYPE_REMOTE_BASE + 2) +#define POOL_TYPE_MDM2_DCI (POOL_TYPE_REMOTE_BASE + 3) +#define POOL_TYPE_MDM_MUX (POOL_TYPE_REMOTE_BASE + 4) +#define POOL_TYPE_MDM2_MUX (POOL_TYPE_REMOTE_BASE + 5) +#define POOL_TYPE_MDM_DCI_WRITE (POOL_TYPE_REMOTE_BASE + 6) +#define POOL_TYPE_MDM2_DCI_WRITE (POOL_TYPE_REMOTE_BASE + 7) +#define POOL_TYPE_QSC_MUX (POOL_TYPE_REMOTE_BASE + 8) +#define POOL_TYPE_REMOTE_LAST (POOL_TYPE_REMOTE_BASE + 9) + +#ifdef CONFIG_DIAGFWD_BRIDGE_CODE +#define NUM_MEMORY_POOLS POOL_TYPE_REMOTE_LAST +#else +#define NUM_MEMORY_POOLS POOL_TYPE_LOCAL_LAST +#endif + +#define DIAG_MEMPOOL_NAME_SZ 24 +#define DIAG_MEMPOOL_GET_NAME(x) (diag_mempools[x].name) + +struct diag_mempool_t { + int id; + char name[DIAG_MEMPOOL_NAME_SZ]; + mempool_t *pool; + unsigned int itemsize; + unsigned int poolsize; + int count; + spinlock_t lock; +} __packed; + +extern struct diag_mempool_t diag_mempools[NUM_MEMORY_POOLS]; + +void diagmem_setsize(int pool_idx, int itemsize, int poolsize); +void *diagmem_alloc(struct diagchar_dev *driver, int size, int pool_type); +void diagmem_free(struct diagchar_dev *driver, void *buf, int pool_type); +void diagmem_init(struct diagchar_dev *driver, int type); +void diagmem_exit(struct diagchar_dev *driver, int type); + +#endif diff -Nruw linux-4.4.115-fbx/drivers/char/diag./diag_memorydevice.c linux-4.4.115-fbx/drivers/char/diag/diag_memorydevice.c --- linux-4.4.115-fbx/drivers/char/diag./diag_memorydevice.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-4.4.115-fbx/drivers/char/diag/diag_memorydevice.c 2019-10-29 09:26:23.449201280 +0100 @@ -0,0 +1,430 @@ +/* Copyright (c) 2014-2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "diagchar.h" +#include "diag_memorydevice.h" +#include "diagfwd_bridge.h" +#include "diag_mux.h" +#include "diagmem.h" +#include "diagfwd.h" +#include "diagfwd_peripheral.h" +#include "diag_ipc_logging.h" + +struct diag_md_info diag_md[NUM_DIAG_MD_DEV] = { + { + .id = DIAG_MD_LOCAL, + .ctx = 0, + .mempool = POOL_TYPE_MUX_APPS, + .num_tbl_entries = 0, + .tbl = NULL, + .ops = NULL, + }, +#ifdef CONFIG_DIAGFWD_BRIDGE_CODE + { + .id = DIAG_MD_MDM, + .ctx = 0, + .mempool = POOL_TYPE_MDM_MUX, + .num_tbl_entries = 0, + .tbl = NULL, + .ops = NULL, + }, + { + .id = DIAG_MD_MDM2, + .ctx = 0, + .mempool = POOL_TYPE_MDM2_MUX, + .num_tbl_entries = 0, + .tbl = NULL, + .ops = NULL, + }, + { + .id = DIAG_MD_SMUX, + .ctx = 0, + .mempool = POOL_TYPE_QSC_MUX, + .num_tbl_entries = 0, + .tbl = NULL, + .ops = NULL, + } +#endif +}; + +int diag_md_register(int id, int ctx, struct diag_mux_ops *ops) +{ + if (id < 0 || id >= NUM_DIAG_MD_DEV || !ops) + return -EINVAL; + + diag_md[id].ops = ops; + diag_md[id].ctx = ctx; + return 0; +} + +void diag_md_open_all() +{ + int i; + struct diag_md_info *ch = NULL; + + for (i = 0; i < NUM_DIAG_MD_DEV; i++) { + ch = &diag_md[i]; + if (ch->ops && ch->ops->open) + ch->ops->open(ch->ctx, DIAG_MEMORY_DEVICE_MODE); + } + + return; +} + +void diag_md_close_all() +{ + int i, j; + unsigned long flags; + struct diag_md_info *ch = NULL; + struct diag_buf_tbl_t *entry = NULL; + + for (i = 0; i < NUM_DIAG_MD_DEV; i++) { + ch = &diag_md[i]; + + if (ch->ops && ch->ops->close) + ch->ops->close(ch->ctx, DIAG_MEMORY_DEVICE_MODE); + + /* + * When we close the Memory device mode, make sure we flush the + * internal buffers in the table so that there are no stale + * entries. + */ + spin_lock_irqsave(&ch->lock, flags); + for (j = 0; j < ch->num_tbl_entries; j++) { + entry = &ch->tbl[j]; + if (entry->len <= 0) + continue; + if (ch->ops && ch->ops->write_done) + ch->ops->write_done(entry->buf, entry->len, + entry->ctx, + DIAG_MEMORY_DEVICE_MODE); + entry->buf = NULL; + entry->len = 0; + entry->ctx = 0; + } + spin_unlock_irqrestore(&ch->lock, flags); + } + + diag_ws_reset(DIAG_WS_MUX); +} + +int diag_md_write(int id, unsigned char *buf, int len, int ctx) +{ + int i, pid = 0; + uint8_t found = 0; + unsigned long flags; + struct diag_md_info *ch = NULL; + uint8_t peripheral; + struct diag_md_session_t *session_info = NULL; + + if (id < 0 || id >= NUM_DIAG_MD_DEV || id >= DIAG_NUM_PROC) + return -EINVAL; + + if (!buf || len < 0) + return -EINVAL; + + peripheral = + diag_md_get_peripheral(ctx); + if (peripheral < 0) + return -EINVAL; + + mutex_lock(&driver->md_session_lock); + session_info = diag_md_session_get_peripheral(peripheral); + if (!session_info) { + mutex_unlock(&driver->md_session_lock); + return -EIO; + } + pid = session_info->pid; + mutex_unlock(&driver->md_session_lock); + + ch = &diag_md[id]; + if (!ch) + return -EINVAL; + + spin_lock_irqsave(&ch->lock, flags); + for (i = 0; i < ch->num_tbl_entries && !found; i++) { + if (ch->tbl[i].buf != buf) + continue; + found = 1; + pr_err_ratelimited("diag: trying to write the same buffer buf: %pK, len: %d, back to the table for p: %d, t: %d, buf_num: %d, proc: %d, i: %d\n", + buf, ch->tbl[i].len, GET_BUF_PERIPHERAL(ctx), + GET_BUF_TYPE(ctx), GET_BUF_NUM(ctx), id, i); + ch->tbl[i].buf = NULL; + ch->tbl[i].len = 0; + ch->tbl[i].ctx = 0; + } + spin_unlock_irqrestore(&ch->lock, flags); + + if (found) + return -ENOMEM; + + spin_lock_irqsave(&ch->lock, flags); + for (i = 0; i < ch->num_tbl_entries && !found; i++) { + if (ch->tbl[i].len == 0) { + ch->tbl[i].buf = buf; + ch->tbl[i].len = len; + ch->tbl[i].ctx = ctx; + found = 1; + diag_ws_on_read(DIAG_WS_MUX, len); + } + } + spin_unlock_irqrestore(&ch->lock, flags); + + if (!found) { + pr_err_ratelimited("diag: Unable to find an empty space in table, please reduce logging rate, proc: %d\n", + id); + return -ENOMEM; + } + + found = 0; + mutex_lock(&driver->diagchar_mutex); + for (i = 0; i < driver->num_clients && !found; i++) { + if ((driver->client_map[i].pid != pid) || + (driver->client_map[i].pid == 0)) + continue; + + found = 1; + if (!(driver->data_ready[i] & USER_SPACE_DATA_TYPE)) { + driver->data_ready[i] |= USER_SPACE_DATA_TYPE; + atomic_inc(&driver->data_ready_notif[i]); + } + pr_debug("diag: wake up logging process\n"); + wake_up_interruptible(&driver->wait_q); + } + mutex_unlock(&driver->diagchar_mutex); + + if (!found) + return -EINVAL; + + return 0; +} + +int diag_md_copy_to_user(char __user *buf, int *pret, size_t buf_size, + struct diag_md_session_t *info) +{ + int i, j; + int err = 0; + int ret = *pret; + int num_data = 0; + int remote_token; + unsigned long flags; + struct diag_md_info *ch = NULL; + struct diag_buf_tbl_t *entry = NULL; + uint8_t drain_again = 0; + uint8_t peripheral = 0; + struct diag_md_session_t *session_info = NULL; + struct pid *pid_struct = NULL; + + for (i = 0; i < NUM_DIAG_MD_DEV && !err; i++) { + ch = &diag_md[i]; + for (j = 0; j < ch->num_tbl_entries && !err; j++) { + entry = &ch->tbl[j]; + if (entry->len <= 0 || entry->buf == NULL) + continue; + + peripheral = diag_md_get_peripheral(entry->ctx); + if (peripheral < 0) + goto drop_data; + + session_info = + diag_md_session_get_peripheral(peripheral); + if (!session_info) { + goto drop_data; + } + + if (session_info && info && + (session_info->pid != info->pid)) + continue; + if ((info && (info->peripheral_mask & + MD_PERIPHERAL_MASK(peripheral)) == 0)) + goto drop_data; + pid_struct = find_get_pid(session_info->pid); + if (!pid_struct) { + err = -ESRCH; + DIAG_LOG(DIAG_DEBUG_PERIPHERALS, + "diag: No such md_session_map[%d] with pid = %d err=%d exists..\n", + peripheral, session_info->pid, err); + goto drop_data; + } + /* + * If the data is from remote processor, copy the remote + * token first + */ + if (i > 0) { + if ((ret + (3 * sizeof(int)) + entry->len) >= + buf_size) { + drain_again = 1; + break; + } + } else { + if ((ret + (2 * sizeof(int)) + entry->len) >= + buf_size) { + drain_again = 1; + break; + } + } + if (i > 0) { + remote_token = diag_get_remote(i); + if (get_pid_task(pid_struct, PIDTYPE_PID)) { + err = copy_to_user(buf + ret, + &remote_token, + sizeof(int)); + if (err) + goto drop_data; + ret += sizeof(int); + } + } + + /* Copy the length of data being passed */ + if (get_pid_task(pid_struct, PIDTYPE_PID)) { + err = copy_to_user(buf + ret, + (void *)&(entry->len), + sizeof(int)); + if (err) + goto drop_data; + ret += sizeof(int); + } + + /* Copy the actual data being passed */ + if (get_pid_task(pid_struct, PIDTYPE_PID)) { + err = copy_to_user(buf + ret, + (void *)entry->buf, + entry->len); + if (err) + goto drop_data; + ret += entry->len; + } + /* + * The data is now copied to the user space client, + * Notify that the write is complete and delete its + * entry from the table + */ + num_data++; +drop_data: + spin_lock_irqsave(&ch->lock, flags); + if (ch->ops && ch->ops->write_done) + ch->ops->write_done(entry->buf, entry->len, + entry->ctx, + DIAG_MEMORY_DEVICE_MODE); + diag_ws_on_copy(DIAG_WS_MUX); + entry->buf = NULL; + entry->len = 0; + entry->ctx = 0; + spin_unlock_irqrestore(&ch->lock, flags); + } + } + + *pret = ret; + if (pid_struct && get_pid_task(pid_struct, PIDTYPE_PID)) { + err = copy_to_user(buf + sizeof(int), + (void *)&num_data, + sizeof(int)); + } + diag_ws_on_copy_complete(DIAG_WS_MUX); + if (drain_again) + chk_logging_wakeup(); + + return err; +} + +int diag_md_close_peripheral(int id, uint8_t peripheral) +{ + int i; + uint8_t found = 0; + unsigned long flags; + struct diag_md_info *ch = NULL; + struct diag_buf_tbl_t *entry = NULL; + + if (id < 0 || id >= NUM_DIAG_MD_DEV || id >= DIAG_NUM_PROC) + return -EINVAL; + + ch = &diag_md[id]; + + spin_lock_irqsave(&ch->lock, flags); + for (i = 0; i < ch->num_tbl_entries && !found; i++) { + entry = &ch->tbl[i]; + + if (peripheral > NUM_PERIPHERALS) { + if (GET_PD_CTXT(entry->ctx) != peripheral) + continue; + } else { + if (GET_BUF_PERIPHERAL(entry->ctx) != + peripheral) + continue; + } + found = 1; + if (ch->ops && ch->ops->write_done) { + ch->ops->write_done(entry->buf, entry->len, + entry->ctx, + DIAG_MEMORY_DEVICE_MODE); + entry->buf = NULL; + entry->len = 0; + entry->ctx = 0; + } + } + spin_unlock_irqrestore(&ch->lock, flags); + return 0; +} + +int diag_md_init() +{ + int i, j; + struct diag_md_info *ch = NULL; + + for (i = 0; i < NUM_DIAG_MD_DEV; i++) { + ch = &diag_md[i]; + ch->num_tbl_entries = diag_mempools[ch->mempool].poolsize; + ch->tbl = kzalloc(ch->num_tbl_entries * + sizeof(struct diag_buf_tbl_t), + GFP_KERNEL); + if (!ch->tbl) + goto fail; + + for (j = 0; j < ch->num_tbl_entries; j++) { + ch->tbl[j].buf = NULL; + ch->tbl[j].len = 0; + ch->tbl[j].ctx = 0; + } + spin_lock_init(&(ch->lock)); + } + + return 0; + +fail: + diag_md_exit(); + return -ENOMEM; +} + +void diag_md_exit() +{ + int i; + struct diag_md_info *ch = NULL; + + for (i = 0; i < NUM_DIAG_MD_DEV; i++) { + ch = &diag_md[i]; + kfree(ch->tbl); + ch->num_tbl_entries = 0; + ch->ops = NULL; + } +} diff -Nruw linux-4.4.115-fbx/drivers/char/diag./diag_memorydevice.h linux-4.4.115-fbx/drivers/char/diag/diag_memorydevice.h --- linux-4.4.115-fbx/drivers/char/diag./diag_memorydevice.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-4.4.115-fbx/drivers/char/diag/diag_memorydevice.h 2019-10-29 09:26:23.449201280 +0100 @@ -0,0 +1,57 @@ +/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef DIAG_MEMORYDEVICE_H +#define DIAG_MEMORYDEVICE_H + +#define DIAG_MD_LOCAL 0 +#define DIAG_MD_LOCAL_LAST 1 +#define DIAG_MD_BRIDGE_BASE DIAG_MD_LOCAL_LAST +#define DIAG_MD_MDM (DIAG_MD_BRIDGE_BASE) +#define DIAG_MD_MDM2 (DIAG_MD_BRIDGE_BASE + 1) +#define DIAG_MD_SMUX (DIAG_MD_BRIDGE_BASE + 2) +#define DIAG_MD_BRIDGE_LAST (DIAG_MD_BRIDGE_BASE + 3) + +#ifndef CONFIG_DIAGFWD_BRIDGE_CODE +#define NUM_DIAG_MD_DEV DIAG_MD_LOCAL_LAST +#else +#define NUM_DIAG_MD_DEV DIAG_MD_BRIDGE_LAST +#endif + +struct diag_buf_tbl_t { + unsigned char *buf; + int len; + int ctx; +}; + +struct diag_md_info { + int id; + int ctx; + int mempool; + int num_tbl_entries; + spinlock_t lock; + struct diag_buf_tbl_t *tbl; + struct diag_mux_ops *ops; +}; + +extern struct diag_md_info diag_md[NUM_DIAG_MD_DEV]; + +int diag_md_init(void); +void diag_md_exit(void); +void diag_md_open_all(void); +void diag_md_close_all(void); +int diag_md_register(int id, int ctx, struct diag_mux_ops *ops); +int diag_md_close_peripheral(int id, uint8_t peripheral); +int diag_md_write(int id, unsigned char *buf, int len, int ctx); +int diag_md_copy_to_user(char __user *buf, int *pret, size_t buf_size, + struct diag_md_session_t *info); +#endif diff -Nruw linux-4.4.115-fbx/drivers/char/diag./diag_mux.c linux-4.4.115-fbx/drivers/char/diag/diag_mux.c --- linux-4.4.115-fbx/drivers/char/diag./diag_mux.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-4.4.115-fbx/drivers/char/diag/diag_mux.c 2019-10-29 09:26:23.449201280 +0100 @@ -0,0 +1,288 @@ +/* Copyright (c) 2014-2017, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "diagchar.h" +#include "diagfwd.h" +#include "diag_mux.h" +#include "diag_usb.h" +#include "diag_memorydevice.h" +#include "diag_ipc_logging.h" + +struct diag_mux_state_t *diag_mux; +static struct diag_logger_t usb_logger; +static struct diag_logger_t md_logger; + +static struct diag_logger_ops usb_log_ops = { + .open = diag_usb_connect_all, + .close = diag_usb_disconnect_all, + .queue_read = diag_usb_queue_read, + .write = diag_usb_write, + .close_peripheral = NULL +}; + +static struct diag_logger_ops md_log_ops = { + .open = diag_md_open_all, + .close = diag_md_close_all, + .queue_read = NULL, + .write = diag_md_write, + .close_peripheral = diag_md_close_peripheral, +}; + +int diag_mux_init() +{ + diag_mux = kzalloc(sizeof(struct diag_mux_state_t), + GFP_KERNEL); + if (!diag_mux) + return -ENOMEM; + kmemleak_not_leak(diag_mux); + + usb_logger.mode = DIAG_USB_MODE; + usb_logger.log_ops = &usb_log_ops; + + md_logger.mode = DIAG_MEMORY_DEVICE_MODE; + md_logger.log_ops = &md_log_ops; + diag_md_init(); + + /* + * Set USB logging as the default logger. This is the mode + * Diag should be in when it initializes. + */ + diag_mux->usb_ptr = &usb_logger; + diag_mux->md_ptr = &md_logger; + diag_mux->logger = &usb_logger; + diag_mux->mux_mask = 0; + diag_mux->mode = DIAG_USB_MODE; + return 0; +} + +void diag_mux_exit() +{ + kfree(diag_mux); +} + +int diag_mux_register(int proc, int ctx, struct diag_mux_ops *ops) +{ + int err = 0; + if (!ops) + return -EINVAL; + + if (proc < 0 || proc >= NUM_MUX_PROC) + return 0; + + /* Register with USB logger */ + usb_logger.ops[proc] = ops; + err = diag_usb_register(proc, ctx, ops); + if (err) { + pr_err("diag: MUX: unable to register usb operations for proc: %d, err: %d\n", + proc, err); + return err; + } + + md_logger.ops[proc] = ops; + err = diag_md_register(proc, ctx, ops); + if (err) { + pr_err("diag: MUX: unable to register md operations for proc: %d, err: %d\n", + proc, err); + return err; + } + + return 0; +} + +int diag_mux_queue_read(int proc) +{ + struct diag_logger_t *logger = NULL; + + if (proc < 0 || proc >= NUM_MUX_PROC) + return -EINVAL; + if (!diag_mux) + return -EIO; + + if (diag_mux->mode == DIAG_MULTI_MODE) + logger = diag_mux->usb_ptr; + else + logger = diag_mux->logger; + + if (logger && logger->log_ops && logger->log_ops->queue_read) + return logger->log_ops->queue_read(proc); + + return 0; +} + +int diag_mux_write(int proc, unsigned char *buf, int len, int ctx) +{ + struct diag_logger_t *logger = NULL; + int peripheral, upd; + + if (proc < 0 || proc >= NUM_MUX_PROC) + return -EINVAL; + if (!diag_mux) + return -EIO; + + upd = GET_PD_CTXT(ctx); + if (upd) { + switch (upd) { + case DIAG_ID_MPSS: + upd = PERIPHERAL_MODEM; + break; + case DIAG_ID_LPASS: + upd = PERIPHERAL_LPASS; + break; + case DIAG_ID_CDSP: + upd = PERIPHERAL_CDSP; + break; + case UPD_WLAN: + if (!driver->pd_logging_mode[0]) + upd = PERIPHERAL_MODEM; + break; + case UPD_AUDIO: + if (!driver->pd_logging_mode[1]) + upd = PERIPHERAL_LPASS; + break; + case UPD_SENSORS: + if (!driver->pd_logging_mode[2]) + upd = PERIPHERAL_LPASS; + break; + default: + pr_err("diag: invalid pd ctxt= %d\n", upd); + return -EINVAL; + } + if (((MD_PERIPHERAL_MASK(upd)) & + (diag_mux->mux_mask)) && + driver->md_session_map[upd]) + logger = diag_mux->md_ptr; + else + logger = diag_mux->usb_ptr; + } else { + + peripheral = GET_BUF_PERIPHERAL(ctx); + if (peripheral > NUM_PERIPHERALS) + return -EINVAL; + + if (MD_PERIPHERAL_MASK(peripheral) & + diag_mux->mux_mask) + logger = diag_mux->md_ptr; + else + logger = diag_mux->usb_ptr; + } + + if (logger && logger->log_ops && logger->log_ops->write) + return logger->log_ops->write(proc, buf, len, ctx); + return 0; +} + +int diag_mux_close_peripheral(int proc, uint8_t peripheral) +{ + struct diag_logger_t *logger = NULL; + if (proc < 0 || proc >= NUM_MUX_PROC) + return -EINVAL; + + /* Peripheral should account for Apps data as well */ + if (peripheral > NUM_PERIPHERALS) { + if (driver->num_pd_session) { + if (peripheral > NUM_MD_SESSIONS) + return -EINVAL; + } else { + return -EINVAL; + } + } + + if (!diag_mux) + return -EIO; + + if (MD_PERIPHERAL_MASK(peripheral) & diag_mux->mux_mask) + logger = diag_mux->md_ptr; + else + logger = diag_mux->logger; + + if (logger && logger->log_ops && logger->log_ops->close_peripheral) + return logger->log_ops->close_peripheral(proc, peripheral); + return 0; +} + +int diag_mux_switch_logging(int *req_mode, int *peripheral_mask) +{ + unsigned int new_mask = 0; + + if (!req_mode) + return -EINVAL; + + if (*peripheral_mask <= 0 || + (*peripheral_mask > (DIAG_CON_ALL | DIAG_CON_UPD_ALL))) { + pr_err("diag: mask %d in %s\n", *peripheral_mask, __func__); + return -EINVAL; + } + + switch (*req_mode) { + case DIAG_USB_MODE: + new_mask = ~(*peripheral_mask) & diag_mux->mux_mask; + if (new_mask != DIAG_CON_NONE) + *req_mode = DIAG_MULTI_MODE; + break; + case DIAG_MEMORY_DEVICE_MODE: + new_mask = (*peripheral_mask) | diag_mux->mux_mask; + if (new_mask != DIAG_CON_ALL) + *req_mode = DIAG_MULTI_MODE; + break; + default: + pr_err("diag: Invalid mode %d in %s\n", *req_mode, __func__); + return -EINVAL; + } + + switch (diag_mux->mode) { + case DIAG_USB_MODE: + if (*req_mode == DIAG_MEMORY_DEVICE_MODE) { + diag_mux->usb_ptr->log_ops->close(); + diag_mux->logger = diag_mux->md_ptr; + diag_mux->md_ptr->log_ops->open(); + } else if (*req_mode == DIAG_MULTI_MODE) { + diag_mux->md_ptr->log_ops->open(); + diag_mux->logger = NULL; + } + break; + case DIAG_MEMORY_DEVICE_MODE: + if (*req_mode == DIAG_USB_MODE) { + diag_mux->md_ptr->log_ops->close(); + diag_mux->logger = diag_mux->usb_ptr; + diag_mux->usb_ptr->log_ops->open(); + } else if (*req_mode == DIAG_MULTI_MODE) { + diag_mux->usb_ptr->log_ops->open(); + diag_mux->logger = NULL; + } + break; + case DIAG_MULTI_MODE: + if (*req_mode == DIAG_USB_MODE) { + diag_mux->md_ptr->log_ops->close(); + diag_mux->logger = diag_mux->usb_ptr; + } else if (*req_mode == DIAG_MEMORY_DEVICE_MODE) { + diag_mux->usb_ptr->log_ops->close(); + diag_mux->logger = diag_mux->md_ptr; + } + break; + } + diag_mux->mode = *req_mode; + diag_mux->mux_mask = new_mask; + *peripheral_mask = new_mask; + return 0; +} diff -Nruw linux-4.4.115-fbx/drivers/char/diag./diag_mux.h linux-4.4.115-fbx/drivers/char/diag/diag_mux.h --- linux-4.4.115-fbx/drivers/char/diag./diag_mux.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-4.4.115-fbx/drivers/char/diag/diag_mux.h 2019-01-22 16:16:22.955241444 +0100 @@ -0,0 +1,76 @@ +/* Copyright (c) 2014-2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#ifndef DIAG_MUX_H +#define DIAG_MUX_H +#include "diagchar.h" + +struct diag_mux_state_t { + struct diag_logger_t *logger; + struct diag_logger_t *usb_ptr; + struct diag_logger_t *md_ptr; + unsigned int mux_mask; + unsigned int mode; +}; + +struct diag_mux_ops { + int (*open)(int id, int mode); + int (*close)(int id, int mode); + int (*read_done)(unsigned char *buf, int len, int id); + int (*write_done)(unsigned char *buf, int len, int buf_ctx, + int id); +}; + +#define DIAG_USB_MODE 0 +#define DIAG_MEMORY_DEVICE_MODE 1 +#define DIAG_NO_LOGGING_MODE 2 +#define DIAG_MULTI_MODE 3 + +#define DIAG_MUX_LOCAL 0 +#define DIAG_MUX_LOCAL_LAST 1 +#define DIAG_MUX_BRIDGE_BASE DIAG_MUX_LOCAL_LAST +#define DIAG_MUX_MDM (DIAG_MUX_BRIDGE_BASE) +#define DIAG_MUX_MDM2 (DIAG_MUX_BRIDGE_BASE + 1) +#define DIAG_MUX_SMUX (DIAG_MUX_BRIDGE_BASE + 2) +#define DIAG_MUX_BRIDGE_LAST (DIAG_MUX_BRIDGE_BASE + 3) + +#ifndef CONFIG_DIAGFWD_BRIDGE_CODE +#define NUM_MUX_PROC DIAG_MUX_LOCAL_LAST +#else +#define NUM_MUX_PROC DIAG_MUX_BRIDGE_LAST +#endif + +struct diag_logger_ops { + void (*open)(void); + void (*close)(void); + int (*queue_read)(int id); + int (*write)(int id, unsigned char *buf, int len, int ctx); + int (*close_peripheral)(int id, uint8_t peripheral); +}; + +struct diag_logger_t { + int mode; + struct diag_mux_ops *ops[NUM_MUX_PROC]; + struct diag_logger_ops *log_ops; +}; + +extern struct diag_mux_state_t *diag_mux; + +int diag_mux_init(void); +void diag_mux_exit(void); +int diag_mux_register(int proc, int ctx, struct diag_mux_ops *ops); +int diag_mux_queue_read(int proc); +int diag_mux_write(int proc, unsigned char *buf, int len, int ctx); +int diag_mux_close_peripheral(int proc, uint8_t peripheral); +int diag_mux_open_all(struct diag_logger_t *logger); +int diag_mux_close_all(void); +int diag_mux_switch_logging(int *new_mode, int *peripheral_mask); +#endif diff -Nruw linux-4.4.115-fbx/drivers/char/diag./diag_usb.h linux-4.4.115-fbx/drivers/char/diag/diag_usb.h --- linux-4.4.115-fbx/drivers/char/diag./diag_usb.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-4.4.115-fbx/drivers/char/diag/diag_usb.h 2019-01-22 16:16:22.955241444 +0100 @@ -0,0 +1,110 @@ +/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef DIAGUSB_H +#define DIAGUSB_H + +#ifdef CONFIG_DIAG_OVER_USB +#include +#endif +#include "diagchar.h" +#include "diag_mux.h" + +#define DIAG_USB_LOCAL 0 +#define DIAG_USB_LOCAL_LAST 1 +#define DIAG_USB_BRIDGE_BASE DIAG_USB_LOCAL_LAST +#define DIAG_USB_MDM (DIAG_USB_BRIDGE_BASE) +#define DIAG_USB_MDM2 (DIAG_USB_BRIDGE_BASE + 1) +#define DIAG_USB_QSC (DIAG_USB_BRIDGE_BASE + 2) +#define DIAG_USB_BRIDGE_LAST (DIAG_USB_BRIDGE_BASE + 3) + +#ifndef CONFIG_DIAGFWD_BRIDGE_CODE +#define NUM_DIAG_USB_DEV DIAG_USB_LOCAL_LAST +#else +#define NUM_DIAG_USB_DEV DIAG_USB_BRIDGE_LAST +#endif + +#define DIAG_USB_NAME_SZ 24 +#define DIAG_USB_GET_NAME(x) (diag_usb[x].name) + +#define DIAG_USB_MODE 0 + +struct diag_usb_buf_tbl_t { + struct list_head track; + unsigned char *buf; + uint32_t len; + atomic_t ref_count; + int ctxt; +}; + +struct diag_usb_info { + int id; + int ctxt; + char name[DIAG_USB_NAME_SZ]; + atomic_t connected; + atomic_t diag_state; + atomic_t read_pending; + int enabled; + int mempool; + int max_size; + struct list_head buf_tbl; + unsigned long read_cnt; + unsigned long write_cnt; + spinlock_t lock; + spinlock_t write_lock; + struct usb_diag_ch *hdl; + struct diag_mux_ops *ops; + unsigned char *read_buf; + struct diag_request *read_ptr; + struct work_struct read_work; + struct work_struct read_done_work; + struct work_struct connect_work; + struct work_struct disconnect_work; + struct workqueue_struct *usb_wq; +}; + +#ifdef CONFIG_DIAG_OVER_USB +extern struct diag_usb_info diag_usb[NUM_DIAG_USB_DEV]; +int diag_usb_register(int id, int ctxt, struct diag_mux_ops *ops); +int diag_usb_queue_read(int id); +int diag_usb_write(int id, unsigned char *buf, int len, int ctxt); +void diag_usb_connect_all(void); +void diag_usb_disconnect_all(void); +void diag_usb_exit(int id); +#else +static inline int diag_usb_register(int id, int ctxt, struct diag_mux_ops *ops) +{ + return 0; +} +static inline int diag_usb_queue_read(int id) +{ + return 0; +} +static inline int diag_usb_write(int id, unsigned char *buf, int len, int ctxt) +{ + return 0; +} +static inline void diag_usb_connect_all(void) +{ + return; +} +static inline void diag_usb_disconnect_all(void) +{ + return; +} +static inline void diag_usb_exit(int id) +{ + return; +} +#endif + +#endif diff -Nruw linux-4.4.115-fbx/drivers/char/diag./Kconfig linux-4.4.115-fbx/drivers/char/diag/Kconfig --- linux-4.4.115-fbx/drivers/char/diag./Kconfig 1970-01-01 01:00:00.000000000 +0100 +++ linux-4.4.115-fbx/drivers/char/diag/Kconfig 2019-10-29 09:26:23.445201240 +0100 @@ -0,0 +1,33 @@ +menu "Diag Support" + +config DIAG_CHAR + tristate "char driver interface and diag forwarding to/from modem" + default m + depends on ARCH_QCOM + depends on POWER_RESET_QCOM + select CRC_CCITT + help + Char driver interface for diag user space and diag-forwarding to modem ARM and back. + This enables diagchar for maemo usb gadget or android usb gadget based on config selected. +endmenu + +menu "DIAG traffic over USB" + +config DIAG_OVER_USB + bool "Enable DIAG traffic to go over USB" + depends on USB_CONFIGFS_F_DIAG || USB_FUNCTION_DIAG || USB_QCOM_MAEMO + depends on ARCH_QCOM + default y + help + This feature helps segregate code required for DIAG traffic to go over USB. +endmenu + +menu "HSIC/SMUX support for DIAG" + +config DIAGFWD_BRIDGE_CODE + depends on USB_QCOM_DIAG_BRIDGE || MSM_MHI + default y + bool "Enable QSC/9K DIAG traffic over SMUX/HSIC" + help + SMUX/HSIC Transport Layer for DIAG Router +endmenu diff -Nruw linux-4.4.115-fbx/drivers/char/diag./Makefile linux-4.4.115-fbx/drivers/char/diag/Makefile --- linux-4.4.115-fbx/drivers/char/diag./Makefile 1970-01-01 01:00:00.000000000 +0100 +++ linux-4.4.115-fbx/drivers/char/diag/Makefile 2019-10-29 09:26:23.445201240 +0100 @@ -0,0 +1,7 @@ +obj-$(CONFIG_DIAG_CHAR) := diagchar.o +obj-$(CONFIG_DIAGFWD_BRIDGE_CODE) += diagfwd_bridge.o +obj-$(CONFIG_USB_QCOM_DIAG_BRIDGE) += diagfwd_hsic.o +obj-$(CONFIG_USB_QCOM_DIAG_BRIDGE) += diagfwd_smux.o +obj-$(CONFIG_MSM_MHI) += diagfwd_mhi.o +obj-$(CONFIG_DIAG_OVER_USB) += diag_usb.o +diagchar-objs := diagchar_core.o diagchar_hdlc.o diagfwd.o diagfwd_glink.o diagfwd_peripheral.o diagfwd_smd.o diagfwd_socket.o diag_mux.o diag_memorydevice.o diagmem.o diagfwd_cntl.o diag_dci.o diag_masks.o diag_debugfs.o --- /dev/null 2019-10-24 16:47:25.704025805 +0200 +++ linux-4.4.115-fbx/drivers/char/hw_random/msm_rng.c 2019-01-22 16:16:22.967241553 +0100 @@ -0,0 +1,482 @@ +/* + * Copyright (c) 2011-2013, 2015, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + + + +#define DRIVER_NAME "msm_rng" + +/* Device specific register offsets */ +#define PRNG_DATA_OUT_OFFSET 0x0000 +#define PRNG_STATUS_OFFSET 0x0004 +#define PRNG_LFSR_CFG_OFFSET 0x0100 +#define PRNG_CONFIG_OFFSET 0x0104 + +/* Device specific register masks and config values */ +#define PRNG_LFSR_CFG_MASK 0xFFFF0000 +#define PRNG_LFSR_CFG_CLOCKS 0x0000DDDD +#define PRNG_CONFIG_MASK 0xFFFFFFFD +#define PRNG_HW_ENABLE 0x00000002 + +#define MAX_HW_FIFO_DEPTH 16 /* FIFO is 16 words deep */ +#define MAX_HW_FIFO_SIZE (MAX_HW_FIFO_DEPTH * 4) /* FIFO is 32 bits wide */ + +struct msm_rng_device { + struct platform_device *pdev; + void __iomem *base; + struct clk *prng_clk; + uint32_t qrng_perf_client; + struct mutex rng_lock; +}; + +struct msm_rng_device msm_rng_device_info; +static struct msm_rng_device *msm_rng_dev_cached; +struct mutex cached_rng_lock; +static long msm_rng_ioctl(struct file *filp, unsigned int cmd, + unsigned long arg) +{ + long ret = 0; + + switch (cmd) { + case QRNG_IOCTL_RESET_BUS_BANDWIDTH: + pr_info("calling msm_rng_bus_scale(LOW)\n"); + ret = msm_bus_scale_client_update_request( + msm_rng_device_info.qrng_perf_client, 0); + if (ret) + pr_err("failed qrng_reset_bus_bw, ret = %ld\n", ret); + break; + default: + pr_err("Unsupported IOCTL call"); + break; + } + return ret; +} + +/* + * + * This function calls hardware random bit generator directory and retuns it + * back to caller + * + */ +static int msm_rng_direct_read(struct msm_rng_device *msm_rng_dev, + void *data, size_t max) +{ + struct platform_device *pdev; + void __iomem *base; + size_t currsize = 0; + u32 val; + u32 *retdata = data; + int ret; + int failed = 0; + + pdev = msm_rng_dev->pdev; + base = msm_rng_dev->base; + + /* no room for word data */ + if (max < 4) + return 0; + + mutex_lock(&msm_rng_dev->rng_lock); + + if (msm_rng_dev->qrng_perf_client) { + ret = msm_bus_scale_client_update_request( + msm_rng_dev->qrng_perf_client, 1); + if (ret) + pr_err("bus_scale_client_update_req failed!\n"); + } + /* enable PRNG clock */ + ret = clk_prepare_enable(msm_rng_dev->prng_clk); + if (ret) { + dev_err(&pdev->dev, "failed to enable clock in callback\n"); + goto err; + } + /* read random data from h/w */ + do { + /* check status bit if data is available */ + while (!(readl_relaxed(base + PRNG_STATUS_OFFSET) + & 0x00000001)) { + if (failed == 10) { + pr_err("Data not available after retry\n"); + break; + } + pr_err("msm_rng:Data not available!\n"); + msleep_interruptible(10); + failed++; + } + + /* read FIFO */ + val = readl_relaxed(base + PRNG_DATA_OUT_OFFSET); + if (!val) + break; /* no data to read so just bail */ + + /* write data back to callers pointer */ + *(retdata++) = val; + currsize += 4; + /* make sure we stay on 32bit boundary */ + if ((max - currsize) < 4) + break; + + } while (currsize < max); + + /* vote to turn off clock */ + clk_disable_unprepare(msm_rng_dev->prng_clk); +err: + if (msm_rng_dev->qrng_perf_client) { + ret = msm_bus_scale_client_update_request( + msm_rng_dev->qrng_perf_client, 0); + if (ret) + pr_err("bus_scale_client_update_req failed!\n"); + } + mutex_unlock(&msm_rng_dev->rng_lock); + + val = 0L; + return currsize; +} +static int msm_rng_read(struct hwrng *rng, void *data, size_t max, bool wait) +{ + struct msm_rng_device *msm_rng_dev; + int rv = 0; + + msm_rng_dev = (struct msm_rng_device *)rng->priv; + rv = msm_rng_direct_read(msm_rng_dev, data, max); + + return rv; +} + + +static struct hwrng msm_rng = { + .name = DRIVER_NAME, + .read = msm_rng_read, + .quality = 700, +}; + +static int msm_rng_enable_hw(struct msm_rng_device *msm_rng_dev) +{ + unsigned long val = 0; + unsigned long reg_val = 0; + int ret = 0; + + if (msm_rng_dev->qrng_perf_client) { + ret = msm_bus_scale_client_update_request( + msm_rng_dev->qrng_perf_client, 1); + if (ret) + pr_err("bus_scale_client_update_req failed!\n"); + } + /* Enable the PRNG CLK */ + ret = clk_prepare_enable(msm_rng_dev->prng_clk); + if (ret) { + dev_err(&(msm_rng_dev->pdev)->dev, + "failed to enable clock in probe\n"); + return -EPERM; + } + + /* Enable PRNG h/w only if it is NOT ON */ + val = readl_relaxed(msm_rng_dev->base + PRNG_CONFIG_OFFSET) & + PRNG_HW_ENABLE; + /* PRNG H/W is not ON */ + if (val != PRNG_HW_ENABLE) { + val = readl_relaxed(msm_rng_dev->base + PRNG_LFSR_CFG_OFFSET); + val &= PRNG_LFSR_CFG_MASK; + val |= PRNG_LFSR_CFG_CLOCKS; + writel_relaxed(val, msm_rng_dev->base + PRNG_LFSR_CFG_OFFSET); + + /* The PRNG CONFIG register should be first written */ + mb(); + + reg_val = readl_relaxed(msm_rng_dev->base + PRNG_CONFIG_OFFSET) + & PRNG_CONFIG_MASK; + reg_val |= PRNG_HW_ENABLE; + writel_relaxed(reg_val, msm_rng_dev->base + PRNG_CONFIG_OFFSET); + + /* The PRNG clk should be disabled only after we enable the + * PRNG h/w by writing to the PRNG CONFIG register. + */ + mb(); + } + clk_disable_unprepare(msm_rng_dev->prng_clk); + + if (msm_rng_dev->qrng_perf_client) { + ret = msm_bus_scale_client_update_request( + msm_rng_dev->qrng_perf_client, 0); + if (ret) + pr_err("bus_scale_client_update_req failed!\n"); + } + + return 0; +} + +static const struct file_operations msm_rng_fops = { + .unlocked_ioctl = msm_rng_ioctl, +}; +static struct class *msm_rng_class; +static struct cdev msm_rng_cdev; + +static int msm_rng_probe(struct platform_device *pdev) +{ + struct resource *res; + struct msm_rng_device *msm_rng_dev = NULL; + void __iomem *base = NULL; + bool configure_qrng = true; + int error = 0; + int ret = 0; + struct device *dev; + + struct msm_bus_scale_pdata *qrng_platform_support = NULL; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (res == NULL) { + dev_err(&pdev->dev, "invalid address\n"); + error = -EFAULT; + goto err_exit; + } + + msm_rng_dev = kzalloc(sizeof(struct msm_rng_device), GFP_KERNEL); + if (!msm_rng_dev) { + dev_err(&pdev->dev, "cannot allocate memory\n"); + error = -ENOMEM; + goto err_exit; + } + + base = ioremap(res->start, resource_size(res)); + if (!base) { + dev_err(&pdev->dev, "ioremap failed\n"); + error = -ENOMEM; + goto err_iomap; + } + msm_rng_dev->base = base; + + /* create a handle for clock control */ + if ((pdev->dev.of_node) && (of_property_read_bool(pdev->dev.of_node, + "qcom,msm-rng-iface-clk"))) + msm_rng_dev->prng_clk = clk_get(&pdev->dev, + "iface_clk"); + else + msm_rng_dev->prng_clk = clk_get(&pdev->dev, "core_clk"); + if (IS_ERR(msm_rng_dev->prng_clk)) { + dev_err(&pdev->dev, "failed to register clock source\n"); + error = -EPERM; + goto err_clk_get; + } + + /* save away pdev and register driver data */ + msm_rng_dev->pdev = pdev; + platform_set_drvdata(pdev, msm_rng_dev); + + if (pdev->dev.of_node) { + /* Register bus client */ + qrng_platform_support = msm_bus_cl_get_pdata(pdev); + msm_rng_dev->qrng_perf_client = msm_bus_scale_register_client( + qrng_platform_support); + msm_rng_device_info.qrng_perf_client = + msm_rng_dev->qrng_perf_client; + if (!msm_rng_dev->qrng_perf_client) + pr_err("Unable to register bus client\n"); + } + + /* Enable rng h/w for the targets which can access the entire + * address space of PRNG. + */ + if ((pdev->dev.of_node) && (of_property_read_bool(pdev->dev.of_node, + "qcom,no-qrng-config"))) + configure_qrng = false; + if (configure_qrng) { + error = msm_rng_enable_hw(msm_rng_dev); + if (error) + goto rollback_clk; + } + + mutex_init(&msm_rng_dev->rng_lock); + mutex_init(&cached_rng_lock); + + /* register with hwrng framework */ + msm_rng.priv = (unsigned long) msm_rng_dev; + error = hwrng_register(&msm_rng); + if (error) { + dev_err(&pdev->dev, "failed to register hwrng\n"); + error = -EPERM; + goto rollback_clk; + } + ret = register_chrdev(QRNG_IOC_MAGIC, DRIVER_NAME, &msm_rng_fops); + + msm_rng_class = class_create(THIS_MODULE, "msm-rng"); + if (IS_ERR(msm_rng_class)) { + pr_err("class_create failed\n"); + return PTR_ERR(msm_rng_class); + } + + dev = device_create(msm_rng_class, NULL, MKDEV(QRNG_IOC_MAGIC, 0), + NULL, "msm-rng"); + if (IS_ERR(dev)) { + pr_err("Device create failed\n"); + error = PTR_ERR(dev); + goto unregister_chrdev; + } + cdev_init(&msm_rng_cdev, &msm_rng_fops); + msm_rng_dev_cached = msm_rng_dev; + return error; + +unregister_chrdev: + unregister_chrdev(QRNG_IOC_MAGIC, DRIVER_NAME); +rollback_clk: + clk_put(msm_rng_dev->prng_clk); +err_clk_get: + iounmap(msm_rng_dev->base); +err_iomap: + kzfree(msm_rng_dev); +err_exit: + return error; +} + +static int msm_rng_remove(struct platform_device *pdev) +{ + struct msm_rng_device *msm_rng_dev = platform_get_drvdata(pdev); + + unregister_chrdev(QRNG_IOC_MAGIC, DRIVER_NAME); + hwrng_unregister(&msm_rng); + clk_put(msm_rng_dev->prng_clk); + iounmap(msm_rng_dev->base); + platform_set_drvdata(pdev, NULL); + if (msm_rng_dev->qrng_perf_client) + msm_bus_scale_unregister_client(msm_rng_dev->qrng_perf_client); + + kzfree(msm_rng_dev); + msm_rng_dev_cached = NULL; + return 0; +} + +static int qrng_get_random(struct crypto_rng *tfm, const u8 *src, + unsigned int slen, u8 *rdata, + unsigned int dlen) +{ + int sizeread = 0; + int rv = -EFAULT; + + if (!msm_rng_dev_cached) { + pr_err("%s: msm_rng_dev is not initialized.\n", __func__); + rv = -ENODEV; + goto err_exit; + } + + if (!rdata) { + pr_err("%s: data buffer is null!\n", __func__); + rv = -EINVAL; + goto err_exit; + } + + if (signal_pending(current) || + mutex_lock_interruptible(&cached_rng_lock)) { + pr_err("%s: mutex lock interrupted!\n", __func__); + rv = -ERESTARTSYS; + goto err_exit; + } + sizeread = msm_rng_direct_read(msm_rng_dev_cached, rdata, dlen); + + if (sizeread == dlen) + rv = 0; + + mutex_unlock(&cached_rng_lock); +err_exit: + return rv; + +} + +static int qrng_reset(struct crypto_rng *tfm, const u8 *seed, unsigned int slen) +{ + return 0; +} + +static struct rng_alg rng_algs[] = { { + .generate = qrng_get_random, + .seed = qrng_reset, + .seedsize = 0, + .base = { + .cra_name = "qrng", + .cra_driver_name = "fips_hw_qrng", + .cra_priority = 300, + .cra_ctxsize = 0, + .cra_module = THIS_MODULE, + } +} }; + +static struct of_device_id qrng_match[] = { + { .compatible = "qcom,msm-rng", + }, + {} +}; + +static struct platform_driver rng_driver = { + .probe = msm_rng_probe, + .remove = msm_rng_remove, + .driver = { + .name = DRIVER_NAME, + .owner = THIS_MODULE, + .of_match_table = qrng_match, + } +}; + +static int __init msm_rng_init(void) +{ + int ret; + + msm_rng_dev_cached = NULL; + ret = platform_driver_register(&rng_driver); + if (ret) { + pr_err("%s: platform_driver_register error:%d\n", + __func__, ret); + goto err_exit; + } + ret = crypto_register_rngs(rng_algs, ARRAY_SIZE(rng_algs)); + if (ret) { + pr_err("%s: crypto_register_algs error:%d\n", + __func__, ret); + goto err_exit; + } + +err_exit: + return ret; +} + +module_init(msm_rng_init); + +static void __exit msm_rng_exit(void) +{ + crypto_unregister_rngs(rng_algs, ARRAY_SIZE(rng_algs)); + platform_driver_unregister(&rng_driver); +} + +module_exit(msm_rng_exit); + +MODULE_AUTHOR("The Linux Foundation"); +MODULE_DESCRIPTION("Qualcomm MSM Random Number Driver"); +MODULE_LICENSE("GPL v2"); --- /dev/null 2019-10-24 16:47:25.704025805 +0200 +++ linux-4.4.115-fbx/drivers/char/rdbg.c 2019-01-22 16:16:22.983241698 +0100 @@ -0,0 +1,1173 @@ +/* + * Copyright (c) 2013-2017, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define SMP2P_NUM_PROCS 16 +#define MAX_RETRIES 20 + +#define SM_VERSION 1 +#define SM_BLOCKSIZE 128 + +#define SMQ_MAGIC_INIT 0xFF00FF00 +#define SMQ_MAGIC_PRODUCER (SMQ_MAGIC_INIT | 0x1) +#define SMQ_MAGIC_CONSUMER (SMQ_MAGIC_INIT | 0x2) + +enum SMQ_STATUS { + SMQ_SUCCESS = 0, + SMQ_ENOMEMORY = -1, + SMQ_EBADPARM = -2, + SMQ_UNDERFLOW = -3, + SMQ_OVERFLOW = -4 +}; + +enum smq_type { + PRODUCER = 1, + CONSUMER = 2, + INVALID = 3 +}; + +struct smq_block_map { + uint32_t index_read; + uint32_t num_blocks; + uint8_t *map; +}; + +struct smq_node { + uint16_t index_block; + uint16_t num_blocks; +} __attribute__ ((__packed__)); + +struct smq_hdr { + uint8_t producer_version; + uint8_t consumer_version; +} __attribute__ ((__packed__)); + +struct smq_out_state { + uint32_t init; + uint32_t index_check_queue_for_reset; + uint32_t index_sent_write; + uint32_t index_free_read; +} __attribute__ ((__packed__)); + +struct smq_out { + struct smq_out_state s; + struct smq_node sent[1]; +}; + +struct smq_in_state { + uint32_t init; + uint32_t index_check_queue_for_reset_ack; + uint32_t index_sent_read; + uint32_t index_free_write; +} __attribute__ ((__packed__)); + +struct smq_in { + struct smq_in_state s; + struct smq_node free[1]; +}; + +struct smq { + struct smq_hdr *hdr; + struct smq_out *out; + struct smq_in *in; + uint8_t *blocks; + uint32_t num_blocks; + struct mutex *lock; + uint32_t initialized; + struct smq_block_map block_map; + enum smq_type type; +}; + +struct gpio_info { + int gpio_base_id; + int irq_base_id; +}; + +struct rdbg_data { + struct device *device; + struct completion work; + struct gpio_info in; + struct gpio_info out; + bool device_initialized; + int gpio_out_offset; + bool device_opened; + void *smem_addr; + size_t smem_size; + struct smq producer_smrb; + struct smq consumer_smrb; + struct mutex write_mutex; +}; + +struct rdbg_device { + struct cdev cdev; + struct class *class; + dev_t dev_no; + int num_devices; + struct rdbg_data *rdbg_data; +}; + +static struct rdbg_device g_rdbg_instance = { + { {0} }, + NULL, + 0, + SMP2P_NUM_PROCS, + NULL +}; + +struct processor_specific_info { + char *name; + unsigned int smem_buffer_addr; + size_t smem_buffer_size; +}; + +static struct processor_specific_info proc_info[SMP2P_NUM_PROCS] = { + {0}, /*APPS*/ + {"rdbg_modem", 0, 0}, /*MODEM*/ + {"rdbg_adsp", SMEM_LC_DEBUGGER, 16*1024}, /*ADSP*/ + {0}, /*SMP2P_RESERVED_PROC_1*/ + {"rdbg_wcnss", 0, 0}, /*WCNSS*/ + {"rdbg_cdsp", SMEM_LC_DEBUGGER, 16*1024}, /*CDSP*/ + {NULL}, /*SMP2P_POWER_PROC*/ + {NULL}, /*SMP2P_TZ_PROC*/ + {NULL}, /*EMPTY*/ + {NULL}, /*EMPTY*/ + {NULL}, /*EMPTY*/ + {NULL}, /*EMPTY*/ + {NULL}, /*EMPTY*/ + {NULL}, /*EMPTY*/ + {NULL}, /*EMPTY*/ + {NULL} /*SMP2P_REMOTE_MOCK_PROC*/ +}; + +static int smq_blockmap_get(struct smq_block_map *block_map, + uint32_t *block_index, uint32_t n) +{ + uint32_t start; + uint32_t mark = 0; + uint32_t found = 0; + uint32_t i = 0; + + start = block_map->index_read; + + if (n == 1) { + do { + if (!block_map->map[block_map->index_read]) { + *block_index = block_map->index_read; + block_map->map[block_map->index_read] = 1; + block_map->index_read++; + block_map->index_read %= block_map->num_blocks; + return SMQ_SUCCESS; + } + block_map->index_read++; + } while (start != (block_map->index_read %= + block_map->num_blocks)); + } else { + mark = block_map->num_blocks; + + do { + if (!block_map->map[block_map->index_read]) { + if (mark > block_map->index_read) { + mark = block_map->index_read; + start = block_map->index_read; + found = 0; + } + + found++; + if (found == n) { + *block_index = mark; + for (i = 0; i < n; i++) + block_map->map[mark + i] = + (uint8_t)(n - i); + block_map->index_read += block_map->map + [block_map->index_read] - 1; + return SMQ_SUCCESS; + } + } else { + found = 0; + block_map->index_read += block_map->map + [block_map->index_read] - 1; + mark = block_map->num_blocks; + } + block_map->index_read++; + } while (start != (block_map->index_read %= + block_map->num_blocks)); + } + + return SMQ_ENOMEMORY; +} + +static void smq_blockmap_put(struct smq_block_map *block_map, uint32_t i) +{ + uint32_t num_blocks = block_map->map[i]; + + while (num_blocks--) { + block_map->map[i] = 0; + i++; + } +} + +static int smq_blockmap_reset(struct smq_block_map *block_map) +{ + if (!block_map->map) + return SMQ_ENOMEMORY; + memset(block_map->map, 0, block_map->num_blocks + 1); + block_map->index_read = 0; + + return SMQ_SUCCESS; +} + +static int smq_blockmap_ctor(struct smq_block_map *block_map, + uint32_t num_blocks) +{ + if (num_blocks <= 1) + return SMQ_ENOMEMORY; + + block_map->map = kcalloc(num_blocks, sizeof(uint8_t), GFP_KERNEL); + if (!block_map->map) + return SMQ_ENOMEMORY; + + block_map->num_blocks = num_blocks - 1; + smq_blockmap_reset(block_map); + + return SMQ_SUCCESS; +} + +static void smq_blockmap_dtor(struct smq_block_map *block_map) +{ + kfree(block_map->map); + block_map->map = NULL; +} + +static int smq_free(struct smq *smq, void *data) +{ + struct smq_node node; + uint32_t index_block; + int err = SMQ_SUCCESS; + + if (smq->lock) + mutex_lock(smq->lock); + + if ((smq->hdr->producer_version != SM_VERSION) && + (smq->out->s.init != SMQ_MAGIC_PRODUCER)) { + err = SMQ_UNDERFLOW; + goto bail; + } + + index_block = ((uint8_t *)data - smq->blocks) / SM_BLOCKSIZE; + if (index_block >= smq->num_blocks) { + err = SMQ_EBADPARM; + goto bail; + } + + node.index_block = (uint16_t)index_block; + node.num_blocks = 0; + *((struct smq_node *)(smq->in->free + smq->in-> + s.index_free_write)) = node; + + smq->in->s.index_free_write = (smq->in->s.index_free_write + 1) + % smq->num_blocks; + +bail: + if (smq->lock) + mutex_unlock(smq->lock); + return err; +} + +static int smq_receive(struct smq *smq, void **pp, int *pnsize, int *pbmore) +{ + struct smq_node *node; + int err = SMQ_SUCCESS; + int more = 0; + + if ((smq->hdr->producer_version != SM_VERSION) && + (smq->out->s.init != SMQ_MAGIC_PRODUCER)) + return SMQ_UNDERFLOW; + + if (smq->in->s.index_sent_read == smq->out->s.index_sent_write) { + err = SMQ_UNDERFLOW; + goto bail; + } + + node = (struct smq_node *)(smq->out->sent + smq->in->s.index_sent_read); + if (node->index_block >= smq->num_blocks) { + err = SMQ_EBADPARM; + goto bail; + } + + smq->in->s.index_sent_read = (smq->in->s.index_sent_read + 1) + % smq->num_blocks; + + *pp = smq->blocks + (node->index_block * SM_BLOCKSIZE); + *pnsize = SM_BLOCKSIZE * node->num_blocks; + + /* Ensure that the reads and writes are updated in the memory + * when they are done and not cached. Also, ensure that the reads + * and writes are not reordered as they are shared between two cores. + */ + rmb(); + if (smq->in->s.index_sent_read != smq->out->s.index_sent_write) + more = 1; + +bail: + *pbmore = more; + return err; +} + +static int smq_alloc_send(struct smq *smq, const uint8_t *pcb, int nsize) +{ + void *pv = 0; + int num_blocks; + uint32_t index_block = 0; + int err = SMQ_SUCCESS; + struct smq_node *node = NULL; + + mutex_lock(smq->lock); + + if ((smq->in->s.init == SMQ_MAGIC_CONSUMER) && + (smq->hdr->consumer_version == SM_VERSION)) { + if (smq->out->s.index_check_queue_for_reset == + smq->in->s.index_check_queue_for_reset_ack) { + while (smq->out->s.index_free_read != + smq->in->s.index_free_write) { + node = (struct smq_node *)( + smq->in->free + + smq->out->s.index_free_read); + if (node->index_block >= smq->num_blocks) { + err = SMQ_EBADPARM; + goto bail; + } + + smq->out->s.index_free_read = + (smq->out->s.index_free_read + 1) + % smq->num_blocks; + + smq_blockmap_put(&smq->block_map, + node->index_block); + /* Ensure that the reads and writes are + * updated in the memory when they are done + * and not cached. Also, ensure that the reads + * and writes are not reordered as they are + * shared between two cores. + */ + rmb(); + } + } + } + + num_blocks = ALIGN(nsize, SM_BLOCKSIZE)/SM_BLOCKSIZE; + err = smq_blockmap_get(&smq->block_map, &index_block, num_blocks); + if (err != SMQ_SUCCESS) + goto bail; + + pv = smq->blocks + (SM_BLOCKSIZE * index_block); + + err = copy_from_user((void *)pv, (void *)pcb, nsize); + if (err != 0) + goto bail; + + ((struct smq_node *)(smq->out->sent + + smq->out->s.index_sent_write))->index_block + = (uint16_t)index_block; + ((struct smq_node *)(smq->out->sent + + smq->out->s.index_sent_write))->num_blocks + = (uint16_t)num_blocks; + + smq->out->s.index_sent_write = (smq->out->s.index_sent_write + 1) + % smq->num_blocks; + +bail: + if (err != SMQ_SUCCESS) { + if (pv) + smq_blockmap_put(&smq->block_map, index_block); + } + mutex_unlock(smq->lock); + return err; +} + +static int smq_reset_producer_queue_internal(struct smq *smq, + uint32_t reset_num) +{ + int retval = 0; + uint32_t i; + + if (smq->type != PRODUCER) + goto bail; + + mutex_lock(smq->lock); + if (smq->out->s.index_check_queue_for_reset != reset_num) { + smq->out->s.index_check_queue_for_reset = reset_num; + for (i = 0; i < smq->num_blocks; i++) + (smq->out->sent + i)->index_block = 0xFFFF; + + smq_blockmap_reset(&smq->block_map); + smq->out->s.index_sent_write = 0; + smq->out->s.index_free_read = 0; + retval = 1; + } + mutex_unlock(smq->lock); + +bail: + return retval; +} + +static int smq_check_queue_reset(struct smq *p_cons, struct smq *p_prod) +{ + int retval = 0; + uint32_t reset_num, i; + + if ((p_cons->type != CONSUMER) || + (p_cons->out->s.init != SMQ_MAGIC_PRODUCER) || + (p_cons->hdr->producer_version != SM_VERSION)) + goto bail; + + reset_num = p_cons->out->s.index_check_queue_for_reset; + if (p_cons->in->s.index_check_queue_for_reset_ack != reset_num) { + p_cons->in->s.index_check_queue_for_reset_ack = reset_num; + for (i = 0; i < p_cons->num_blocks; i++) + (p_cons->in->free + i)->index_block = 0xFFFF; + + p_cons->in->s.index_sent_read = 0; + p_cons->in->s.index_free_write = 0; + + retval = smq_reset_producer_queue_internal(p_prod, reset_num); + } + +bail: + return retval; +} + +static int check_subsystem_debug_enabled(void *base_addr, int size) +{ + int num_blocks; + uint8_t *pb_orig; + uint8_t *pb; + struct smq smq; + int err = 0; + + pb = pb_orig = (uint8_t *)base_addr; + pb += sizeof(struct smq_hdr); + pb = PTR_ALIGN(pb, 8); + size -= pb - (uint8_t *)pb_orig; + num_blocks = (int)((size - sizeof(struct smq_out_state) - + sizeof(struct smq_in_state))/(SM_BLOCKSIZE + + sizeof(struct smq_node) * 2)); + if (num_blocks <= 0) { + err = SMQ_EBADPARM; + goto bail; + } + + pb += num_blocks * SM_BLOCKSIZE; + smq.out = (struct smq_out *)pb; + pb += sizeof(struct smq_out_state) + (num_blocks * + sizeof(struct smq_node)); + smq.in = (struct smq_in *)pb; + + if (smq.in->s.init != SMQ_MAGIC_CONSUMER) { + pr_err("%s, smq in consumer not initialized", __func__); + err = -ECOMM; + } + +bail: + return err; +} + +static void smq_dtor(struct smq *smq) +{ + if (smq->initialized == SMQ_MAGIC_INIT) { + switch (smq->type) { + case PRODUCER: + smq->out->s.init = 0; + smq_blockmap_dtor(&smq->block_map); + break; + case CONSUMER: + smq->in->s.init = 0; + break; + default: + case INVALID: + break; + } + + smq->initialized = 0; + } +} + +/* + * The shared memory is used as a circular ring buffer in each direction. + * Thus we have a bi-directional shared memory channel between the AP + * and a subsystem. We call this SMQ. Each memory channel contains a header, + * data and a control mechanism that is used to synchronize read and write + * of data between the AP and the remote subsystem. + * + * Overall SMQ memory view: + * + * +------------------------------------------------+ + * | SMEM buffer | + * |-----------------------+------------------------| + * |Producer: LA | Producer: Remote | + * |Consumer: Remote | subsystem | + * | subsystem | Consumer: LA | + * | | | + * | Producer| Consumer| + * +-----------------------+------------------------+ + * | | + * | | + * | +--------------------------------------+ + * | | + * | | + * v v + * +--------------------------------------------------------------+ + * | Header | Data | Control | + * +-----------+---+---+---+-----+----+--+--+-----+---+--+--+-----+ + * | | b | b | b | | S |n |n | | S |n |n | | + * | Producer | l | l | l | | M |o |o | | M |o |o | | + * | Ver | o | o | o | | Q |d |d | | Q |d |d | | + * |-----------| c | c | c | ... | |e |e | ... | |e |e | ... | + * | | k | k | k | | O | | | | I | | | | + * | Consumer | | | | | u |0 |1 | | n |0 |1 | | + * | Ver | 0 | 1 | 2 | | t | | | | | | | | + * +-----------+---+---+---+-----+----+--+--+-----+---+--+--+-----+ + * | | + * + | + * | + * +------------------------+ + * | + * v + * +----+----+----+----+ + * | SMQ Nodes | + * |----|----|----|----| + * Node # | 0 | 1 | 2 | ...| + * |----|----|----|----| + * Starting Block Index # | 0 | 3 | 8 | ...| + * |----|----|----|----| + * # of blocks | 3 | 5 | 1 | ...| + * +----+----+----+----+ + * + * Header: Contains version numbers for software compatibility to ensure + * that both producers and consumers on the AP and subsystems know how to + * read from and write to the queue. + * Both the producer and consumer versions are 1. + * +---------+-------------------+ + * | Size | Field | + * +---------+-------------------+ + * | 1 byte | Producer Version | + * +---------+-------------------+ + * | 1 byte | Consumer Version | + * +---------+-------------------+ + * + * Data: The data portion contains multiple blocks [0..N] of a fixed size. + * The block size SM_BLOCKSIZE is fixed to 128 bytes for header version #1. + * Payload sent from the debug agent app is split (if necessary) and placed + * in these blocks. The first data block is placed at the next 8 byte aligned + * address after the header. + * + * The number of blocks for a given SMEM allocation is derived as follows: + * Number of Blocks = ((Total Size - Alignment - Size of Header + * - Size of SMQIn - Size of SMQOut)/(SM_BLOCKSIZE)) + * + * The producer maintains a private block map of each of these blocks to + * determine which of these blocks in the queue is available and which are free. + * + * Control: + * The control portion contains a list of nodes [0..N] where N is number + * of available data blocks. Each node identifies the data + * block indexes that contain a particular debug message to be transferred, + * and the number of blocks it took to hold the contents of the message. + * + * Each node has the following structure: + * +---------+-------------------+ + * | Size | Field | + * +---------+-------------------+ + * | 2 bytes |Staring Block Index| + * +---------+-------------------+ + * | 2 bytes |Number of Blocks | + * +---------+-------------------+ + * + * The producer and the consumer update different parts of the control channel + * (SMQOut / SMQIn) respectively. Each of these control data structures contains + * information about the last node that was written / read, and the actual nodes + * that were written/read. + * + * SMQOut Structure (R/W by producer, R by consumer): + * +---------+-------------------+ + * | Size | Field | + * +---------+-------------------+ + * | 4 bytes | Magic Init Number | + * +---------+-------------------+ + * | 4 bytes | Reset | + * +---------+-------------------+ + * | 4 bytes | Last Sent Index | + * +---------+-------------------+ + * | 4 bytes | Index Free Read | + * +---------+-------------------+ + * + * SMQIn Structure (R/W by consumer, R by producer): + * +---------+-------------------+ + * | Size | Field | + * +---------+-------------------+ + * | 4 bytes | Magic Init Number | + * +---------+-------------------+ + * | 4 bytes | Reset ACK | + * +---------+-------------------+ + * | 4 bytes | Last Read Index | + * +---------+-------------------+ + * | 4 bytes | Index Free Write | + * +---------+-------------------+ + * + * Magic Init Number: + * Both SMQ Out and SMQ In initialize this field with a predefined magic + * number so as to make sure that both the consumer and producer blocks + * have fully initialized and have valid data in the shared memory control area. + * Producer Magic #: 0xFF00FF01 + * Consumer Magic #: 0xFF00FF02 + */ +static int smq_ctor(struct smq *smq, void *base_addr, int size, + enum smq_type type, struct mutex *lock_ptr) +{ + int num_blocks; + uint8_t *pb_orig; + uint8_t *pb; + uint32_t i; + int err; + + if (smq->initialized == SMQ_MAGIC_INIT) { + err = SMQ_EBADPARM; + goto bail; + } + + if (!base_addr || !size) { + err = SMQ_EBADPARM; + goto bail; + } + + if (type == PRODUCER) + smq->lock = lock_ptr; + + pb_orig = (uint8_t *)base_addr; + smq->hdr = (struct smq_hdr *)pb_orig; + pb = pb_orig; + pb += sizeof(struct smq_hdr); + pb = PTR_ALIGN(pb, 8); + size -= pb - (uint8_t *)pb_orig; + num_blocks = (int)((size - sizeof(struct smq_out_state) - + sizeof(struct smq_in_state))/(SM_BLOCKSIZE + + sizeof(struct smq_node) * 2)); + if (num_blocks <= 0) { + err = SMQ_ENOMEMORY; + goto bail; + } + + smq->blocks = pb; + smq->num_blocks = num_blocks; + pb += num_blocks * SM_BLOCKSIZE; + smq->out = (struct smq_out *)pb; + pb += sizeof(struct smq_out_state) + (num_blocks * + sizeof(struct smq_node)); + smq->in = (struct smq_in *)pb; + smq->type = type; + if (type == PRODUCER) { + smq->hdr->producer_version = SM_VERSION; + for (i = 0; i < smq->num_blocks; i++) + (smq->out->sent + i)->index_block = 0xFFFF; + + err = smq_blockmap_ctor(&smq->block_map, smq->num_blocks); + if (err != SMQ_SUCCESS) + goto bail; + + smq->out->s.index_sent_write = 0; + smq->out->s.index_free_read = 0; + if (smq->out->s.init == SMQ_MAGIC_PRODUCER) { + smq->out->s.index_check_queue_for_reset += 1; + } else { + smq->out->s.index_check_queue_for_reset = 1; + smq->out->s.init = SMQ_MAGIC_PRODUCER; + } + } else { + smq->hdr->consumer_version = SM_VERSION; + for (i = 0; i < smq->num_blocks; i++) + (smq->in->free + i)->index_block = 0xFFFF; + + smq->in->s.index_sent_read = 0; + smq->in->s.index_free_write = 0; + if (smq->out->s.init == SMQ_MAGIC_PRODUCER) { + smq->in->s.index_check_queue_for_reset_ack = + smq->out->s.index_check_queue_for_reset; + } else { + smq->in->s.index_check_queue_for_reset_ack = 0; + } + + smq->in->s.init = SMQ_MAGIC_CONSUMER; + } + smq->initialized = SMQ_MAGIC_INIT; + err = SMQ_SUCCESS; + +bail: + return err; +} + +static void send_interrupt_to_subsystem(struct rdbg_data *rdbgdata) +{ + int offset = rdbgdata->gpio_out_offset; + int val = 1 ^ gpio_get_value(rdbgdata->out.gpio_base_id + offset); + + gpio_set_value(rdbgdata->out.gpio_base_id + offset, val); + rdbgdata->gpio_out_offset = (offset + 1) % 32; + + dev_dbg(rdbgdata->device, "%s: sent interrupt %d to subsystem", + __func__, val); +} + +static irqreturn_t on_interrupt_from(int irq, void *ptr) +{ + struct rdbg_data *rdbgdata = (struct rdbg_data *) ptr; + + dev_dbg(rdbgdata->device, "%s: Received interrupt %d from subsystem", + __func__, irq); + + complete(&(rdbgdata->work)); + return IRQ_HANDLED; +} + +static int initialize_smq(struct rdbg_data *rdbgdata) +{ + int err = 0; + unsigned char *smem_consumer_buffer = rdbgdata->smem_addr; + + smem_consumer_buffer += (rdbgdata->smem_size/2); + + if (smq_ctor(&(rdbgdata->producer_smrb), (void *)(rdbgdata->smem_addr), + ((rdbgdata->smem_size)/2), PRODUCER, &rdbgdata->write_mutex)) { + dev_err(rdbgdata->device, "%s: smq producer allocation failed", + __func__); + err = -ENOMEM; + goto bail; + } + + if (smq_ctor(&(rdbgdata->consumer_smrb), (void *)smem_consumer_buffer, + ((rdbgdata->smem_size)/2), CONSUMER, NULL)) { + dev_err(rdbgdata->device, "%s: smq conmsumer allocation failed", + __func__); + err = -ENOMEM; + } + +bail: + return err; + +} + +static int rdbg_open(struct inode *inode, struct file *filp) +{ + int device_id = -1; + struct rdbg_device *device = &g_rdbg_instance; + struct rdbg_data *rdbgdata = NULL; + int err = 0; + + if (!inode || !device->rdbg_data) { + pr_err("Memory not allocated yet"); + err = -ENODEV; + goto bail; + } + + device_id = MINOR(inode->i_rdev); + rdbgdata = &device->rdbg_data[device_id]; + + if (rdbgdata->device_opened) { + dev_err(rdbgdata->device, "%s: Device already opened", + __func__); + err = -EEXIST; + goto bail; + } + + rdbgdata->smem_size = proc_info[device_id].smem_buffer_size; + if (!rdbgdata->smem_size) { + dev_err(rdbgdata->device, "%s: smem not initialized", __func__); + err = -ENOMEM; + goto bail; + } + + rdbgdata->smem_addr = smem_find(proc_info[device_id].smem_buffer_addr, + rdbgdata->smem_size, 0, SMEM_ANY_HOST_FLAG); + if (!rdbgdata->smem_addr) { + dev_err(rdbgdata->device, "%s: Could not allocate smem memory", + __func__); + err = -ENOMEM; + goto bail; + } + dev_dbg(rdbgdata->device, "%s: SMEM address=0x%lx smem_size=%d", + __func__, (unsigned long)rdbgdata->smem_addr, + (unsigned int)rdbgdata->smem_size); + + if (check_subsystem_debug_enabled(rdbgdata->smem_addr, + rdbgdata->smem_size/2)) { + dev_err(rdbgdata->device, "%s: Subsystem %s is not debug enabled", + __func__, proc_info[device_id].name); + err = -ECOMM; + goto bail; + } + + init_completion(&rdbgdata->work); + + err = request_irq(rdbgdata->in.irq_base_id, on_interrupt_from, + IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING, + proc_info[device_id].name, + (void *)&device->rdbg_data[device_id]); + if (err) { + dev_err(rdbgdata->device, + "%s: Failed to register interrupt.Err=%d,irqid=%d.", + __func__, err, rdbgdata->in.irq_base_id); + goto irq_bail; + } + + err = enable_irq_wake(rdbgdata->in.irq_base_id); + if (err < 0) { + dev_dbg(rdbgdata->device, "enable_irq_wake() failed with err=%d", + err); + err = 0; + } + + mutex_init(&rdbgdata->write_mutex); + + err = initialize_smq(rdbgdata); + if (err) { + dev_err(rdbgdata->device, "Error initializing smq. Err=%d", + err); + goto smq_bail; + } + + rdbgdata->device_opened = 1; + + filp->private_data = (void *)rdbgdata; + + return 0; + +smq_bail: + smq_dtor(&(rdbgdata->producer_smrb)); + smq_dtor(&(rdbgdata->consumer_smrb)); + mutex_destroy(&rdbgdata->write_mutex); +irq_bail: + free_irq(rdbgdata->in.irq_base_id, (void *) + &device->rdbg_data[device_id]); +bail: + return err; +} + +static int rdbg_release(struct inode *inode, struct file *filp) +{ + int device_id = -1; + struct rdbg_device *rdbgdevice = &g_rdbg_instance; + struct rdbg_data *rdbgdata = NULL; + int err = 0; + + if (!inode || !rdbgdevice->rdbg_data) { + pr_err("Memory not allocated yet"); + err = -ENODEV; + goto bail; + } + + device_id = MINOR(inode->i_rdev); + rdbgdata = &rdbgdevice->rdbg_data[device_id]; + + if (rdbgdata->device_opened == 1) { + dev_dbg(rdbgdata->device, "%s: Destroying %s.", __func__, + proc_info[device_id].name); + rdbgdata->device_opened = 0; + complete(&(rdbgdata->work)); + free_irq(rdbgdata->in.irq_base_id, (void *) + &rdbgdevice->rdbg_data[device_id]); + if (rdbgdevice->rdbg_data[device_id].producer_smrb.initialized) + smq_dtor(&(rdbgdevice->rdbg_data[device_id]. + producer_smrb)); + if (rdbgdevice->rdbg_data[device_id].consumer_smrb.initialized) + smq_dtor(&(rdbgdevice->rdbg_data[device_id]. + consumer_smrb)); + mutex_destroy(&rdbgdata->write_mutex); + } + + filp->private_data = NULL; + +bail: + return err; +} + +static ssize_t rdbg_read(struct file *filp, char __user *buf, size_t size, + loff_t *offset) +{ + int err = 0; + struct rdbg_data *rdbgdata = filp->private_data; + void *p_sent_buffer = NULL; + int nsize = 0; + int more = 0; + + if (!rdbgdata) { + pr_err("Invalid argument"); + err = -EINVAL; + goto bail; + } + + dev_dbg(rdbgdata->device, "%s: In receive", __func__); + err = wait_for_completion_interruptible(&(rdbgdata->work)); + if (err) { + dev_err(rdbgdata->device, "%s: Error in wait", __func__); + goto bail; + } + + smq_check_queue_reset(&(rdbgdata->consumer_smrb), + &(rdbgdata->producer_smrb)); + if (smq_receive(&(rdbgdata->consumer_smrb), &p_sent_buffer, + &nsize, &more) != SMQ_SUCCESS) { + dev_err(rdbgdata->device, "%s: Error in smq_recv(). Err code = %d", + __func__, err); + err = -ENODATA; + goto bail; + } + + size = ((size < nsize) ? size : nsize); + err = copy_to_user(buf, p_sent_buffer, size); + if (err != 0) { + dev_err(rdbgdata->device, "%s: Error in copy_to_user(). Err code = %d", + __func__, err); + err = -ENODATA; + goto bail; + } + + smq_free(&(rdbgdata->consumer_smrb), p_sent_buffer); + err = size; + dev_dbg(rdbgdata->device, "%s: Read data to buffer with address 0x%lx", + __func__, (unsigned long) buf); + +bail: + return err; +} + +static ssize_t rdbg_write(struct file *filp, const char __user *buf, + size_t size, loff_t *offset) +{ + int err = 0; + int num_retries = 0; + struct rdbg_data *rdbgdata = filp->private_data; + + if (!rdbgdata) { + pr_err("Invalid argument"); + err = -EINVAL; + goto bail; + } + + do { + err = smq_alloc_send(&(rdbgdata->producer_smrb), buf, size); + dev_dbg(rdbgdata->device, "%s, smq_alloc_send returned %d.", + __func__, err); + } while (err != 0 && num_retries++ < MAX_RETRIES); + + if (err != 0) { + err = -ECOMM; + goto bail; + } + + send_interrupt_to_subsystem(rdbgdata); + + err = size; + +bail: + return err; +} + + +static const struct file_operations rdbg_fops = { + .open = rdbg_open, + .read = rdbg_read, + .write = rdbg_write, + .release = rdbg_release, +}; + +static int register_smp2p(char *node_name, struct gpio_info *gpio_info_ptr) +{ + struct device_node *node = NULL; + int cnt = 0; + int id = 0; + + node = of_find_compatible_node(NULL, NULL, node_name); + if (node) { + cnt = of_gpio_count(node); + if (cnt && gpio_info_ptr) { + id = of_get_gpio(node, 0); + gpio_info_ptr->gpio_base_id = id; + gpio_info_ptr->irq_base_id = gpio_to_irq(id); + return 0; + } + } + return -EINVAL; +} + +static int __init rdbg_init(void) +{ + int err = 0; + struct rdbg_device *rdbgdevice = &g_rdbg_instance; + int minor = 0; + int major = 0; + int minor_nodes_created = 0; + + char *rdbg_compatible_string = "qcom,smp2pgpio_client_rdbg_"; + int max_len = strlen(rdbg_compatible_string) + strlen("xx_out"); + + char *node_name = kcalloc(max_len, sizeof(char), GFP_KERNEL); + + if (!node_name) { + err = -ENOMEM; + goto bail; + } + + if (rdbgdevice->num_devices < 1 || + rdbgdevice->num_devices > SMP2P_NUM_PROCS) { + pr_err("rgdb: invalid num_devices"); + err = -EDOM; + goto name_bail; + } + + rdbgdevice->rdbg_data = kcalloc(rdbgdevice->num_devices, + sizeof(struct rdbg_data), GFP_KERNEL); + if (!rdbgdevice->rdbg_data) { + err = -ENOMEM; + goto name_bail; + } + + err = alloc_chrdev_region(&rdbgdevice->dev_no, 0, + rdbgdevice->num_devices, "rdbgctl"); + if (err) { + pr_err("Error in alloc_chrdev_region."); + goto data_bail; + } + major = MAJOR(rdbgdevice->dev_no); + + cdev_init(&rdbgdevice->cdev, &rdbg_fops); + rdbgdevice->cdev.owner = THIS_MODULE; + err = cdev_add(&rdbgdevice->cdev, MKDEV(major, 0), + rdbgdevice->num_devices); + if (err) { + pr_err("Error in cdev_add"); + goto chrdev_bail; + } + + rdbgdevice->class = class_create(THIS_MODULE, "rdbg"); + if (IS_ERR(rdbgdevice->class)) { + err = PTR_ERR(rdbgdevice->class); + pr_err("Error in class_create"); + goto cdev_bail; + } + + for (minor = 0; minor < rdbgdevice->num_devices; minor++) { + if (!proc_info[minor].name) + continue; + + if (snprintf(node_name, max_len, "%s%d_in", + rdbg_compatible_string, minor) <= 0) { + pr_err("Error in snprintf"); + err = -ENOMEM; + goto device_bail; + } + + if (register_smp2p(node_name, + &rdbgdevice->rdbg_data[minor].in)) { + pr_debug("No incoming device tree entry found for %s", + proc_info[minor].name); + continue; + } + + if (snprintf(node_name, max_len, "%s%d_out", + rdbg_compatible_string, minor) <= 0) { + pr_err("Error in snprintf"); + err = -ENOMEM; + goto device_bail; + } + + if (register_smp2p(node_name, + &rdbgdevice->rdbg_data[minor].out)) { + pr_err("No outgoing device tree entry found for %s", + proc_info[minor].name); + err = -EINVAL; + goto device_bail; + } + + rdbgdevice->rdbg_data[minor].device = device_create( + rdbgdevice->class, NULL, MKDEV(major, minor), + NULL, "%s", proc_info[minor].name); + if (IS_ERR(rdbgdevice->rdbg_data[minor].device)) { + err = PTR_ERR(rdbgdevice->rdbg_data[minor].device); + pr_err("Error in device_create"); + goto device_bail; + } + rdbgdevice->rdbg_data[minor].device_initialized = 1; + minor_nodes_created++; + dev_dbg(rdbgdevice->rdbg_data[minor].device, + "%s: created /dev/%s c %d %d'", __func__, + proc_info[minor].name, major, minor); + } + + if (!minor_nodes_created) { + pr_err("No device tree entries found"); + err = -EINVAL; + goto class_bail; + } + + goto name_bail; + +device_bail: + for (--minor; minor >= 0; minor--) { + if (rdbgdevice->rdbg_data[minor].device_initialized) + device_destroy(rdbgdevice->class, + MKDEV(MAJOR(rdbgdevice->dev_no), minor)); + } +class_bail: + class_destroy(rdbgdevice->class); +cdev_bail: + cdev_del(&rdbgdevice->cdev); +chrdev_bail: + unregister_chrdev_region(rdbgdevice->dev_no, rdbgdevice->num_devices); +data_bail: + kfree(rdbgdevice->rdbg_data); +name_bail: + kfree(node_name); +bail: + return err; +} + +static void __exit rdbg_exit(void) +{ + struct rdbg_device *rdbgdevice = &g_rdbg_instance; + int minor; + + for (minor = 0; minor < rdbgdevice->num_devices; minor++) { + if (rdbgdevice->rdbg_data[minor].device_initialized) { + device_destroy(rdbgdevice->class, + MKDEV(MAJOR(rdbgdevice->dev_no), minor)); + } + } + class_destroy(rdbgdevice->class); + cdev_del(&rdbgdevice->cdev); + unregister_chrdev_region(rdbgdevice->dev_no, 1); + kfree(rdbgdevice->rdbg_data); +} + +module_init(rdbg_init); +module_exit(rdbg_exit); + +MODULE_DESCRIPTION("rdbg module"); +MODULE_LICENSE("GPL v2"); diff -Nruw linux-4.4.115-fbx/drivers/clk/msm./clock-alpha-pll.c linux-4.4.115-fbx/drivers/clk/msm/clock-alpha-pll.c --- linux-4.4.115-fbx/drivers/clk/msm./clock-alpha-pll.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-4.4.115-fbx/drivers/clk/msm/clock-alpha-pll.c 2019-01-22 16:16:23.015241987 +0100 @@ -0,0 +1,1255 @@ +/* + * Copyright (c) 2012-2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#define pr_fmt(fmt) "%s: " fmt, __func__ + +#include +#include +#include +#include +#include +#include +#include + +#include "clock.h" + +#define WAIT_MAX_LOOPS 100 + +#define MODE_REG(pll) (*pll->base + pll->offset + 0x0) +#define LOCK_REG(pll) (*pll->base + pll->offset + 0x0) +#define ACTIVE_REG(pll) (*pll->base + pll->offset + 0x0) +#define UPDATE_REG(pll) (*pll->base + pll->offset + 0x0) +#define L_REG(pll) (*pll->base + pll->offset + 0x4) +#define A_REG(pll) (*pll->base + pll->offset + 0x8) +#define VCO_REG(pll) (*pll->base + pll->offset + 0x10) +#define ALPHA_EN_REG(pll) (*pll->base + pll->offset + 0x10) +#define OUTPUT_REG(pll) (*pll->base + pll->offset + 0x10) +#define VOTE_REG(pll) (*pll->base + pll->fsm_reg_offset) +#define USER_CTL_LO_REG(pll) (*pll->base + pll->offset + 0x10) +#define USER_CTL_HI_REG(pll) (*pll->base + pll->offset + 0x14) +#define CONFIG_CTL_REG(pll) (*pll->base + pll->offset + 0x18) +#define TEST_CTL_LO_REG(pll) (*pll->base + pll->offset + 0x1c) +#define TEST_CTL_HI_REG(pll) (*pll->base + pll->offset + 0x20) + +#define PLL_BYPASSNL 0x2 +#define PLL_RESET_N 0x4 +#define PLL_OUTCTRL 0x1 +#define PLL_LATCH_INTERFACE BIT(11) + +#define FABIA_CONFIG_CTL_REG(pll) (*pll->base + pll->offset + 0x14) +#define FABIA_USER_CTL_LO_REG(pll) (*pll->base + pll->offset + 0xc) +#define FABIA_USER_CTL_HI_REG(pll) (*pll->base + pll->offset + 0x10) +#define FABIA_TEST_CTL_LO_REG(pll) (*pll->base + pll->offset + 0x1c) +#define FABIA_TEST_CTL_HI_REG(pll) (*pll->base + pll->offset + 0x20) +#define FABIA_L_REG(pll) (*pll->base + pll->offset + 0x4) +#define FABIA_CAL_L_VAL(pll) (*pll->base + pll->offset + 0x8) +#define FABIA_FRAC_REG(pll) (*pll->base + pll->offset + 0x38) +#define FABIA_PLL_OPMODE(pll) (*pll->base + pll->offset + 0x2c) + +#define FABIA_PLL_STANDBY 0x0 +#define FABIA_PLL_RUN 0x1 +#define FABIA_PLL_OUT_MAIN 0x7 +#define FABIA_RATE_MARGIN 500 +#define ALPHA_PLL_ACK_LATCH BIT(29) +#define ALPHA_PLL_HW_UPDATE_LOGIC_BYPASS BIT(23) + +/* + * Even though 40 bits are present, use only 32 for ease of calculation. + */ +#define ALPHA_REG_BITWIDTH 40 +#define ALPHA_BITWIDTH 32 +#define FABIA_ALPHA_BITWIDTH 16 + +/* + * Enable/disable registers could be shared among PLLs when FSM voting + * is used. This lock protects against potential race when multiple + * PLLs are being enabled/disabled together. + */ +static DEFINE_SPINLOCK(alpha_pll_reg_lock); + +static unsigned long compute_rate(struct alpha_pll_clk *pll, + u32 l_val, u32 a_val) +{ + u64 rate, parent_rate; + int alpha_bw = ALPHA_BITWIDTH; + + if (pll->is_fabia) + alpha_bw = FABIA_ALPHA_BITWIDTH; + + parent_rate = clk_get_rate(pll->c.parent); + rate = parent_rate * l_val; + rate += (parent_rate * a_val) >> alpha_bw; + return rate; +} + +static bool is_locked(struct alpha_pll_clk *pll) +{ + u32 reg = readl_relaxed(LOCK_REG(pll)); + u32 mask = pll->masks->lock_mask; + return (reg & mask) == mask; +} + +static bool is_active(struct alpha_pll_clk *pll) +{ + u32 reg = readl_relaxed(ACTIVE_REG(pll)); + u32 mask = pll->masks->active_mask; + return (reg & mask) == mask; +} + +/* + * Check active_flag if PLL is in FSM mode, otherwise check lock_det + * bit. This function assumes PLLs are already configured to the + * right mode. + */ +static bool update_finish(struct alpha_pll_clk *pll) +{ + if (pll->fsm_en_mask) + return is_active(pll); + else + return is_locked(pll); +} + +static int wait_for_update(struct alpha_pll_clk *pll) +{ + int count; + + for (count = WAIT_MAX_LOOPS; count > 0; count--) { + if (update_finish(pll)) + break; + udelay(1); + } + + if (!count) { + pr_err("%s didn't lock after enabling it!\n", pll->c.dbg_name); + return -EINVAL; + } + + return 0; +} + +static int __alpha_pll_vote_enable(struct alpha_pll_clk *pll) +{ + u32 ena; + + ena = readl_relaxed(VOTE_REG(pll)); + ena |= pll->fsm_en_mask; + writel_relaxed(ena, VOTE_REG(pll)); + mb(); + + return wait_for_update(pll); +} + +static int __alpha_pll_enable(struct alpha_pll_clk *pll, int enable_output) +{ + int rc; + u32 mode; + + mode = readl_relaxed(MODE_REG(pll)); + mode |= PLL_BYPASSNL; + writel_relaxed(mode, MODE_REG(pll)); + + /* + * H/W requires a 5us delay between disabling the bypass and + * de-asserting the reset. + */ + mb(); + udelay(5); + + mode |= PLL_RESET_N; + writel_relaxed(mode, MODE_REG(pll)); + + rc = wait_for_update(pll); + if (rc < 0) + return rc; + + /* Enable PLL output. */ + if (enable_output) { + mode |= PLL_OUTCTRL; + writel_relaxed(mode, MODE_REG(pll)); + } + + /* Ensure that the write above goes through before returning. */ + mb(); + return 0; +} + +static void setup_alpha_pll_values(u64 a_val, u32 l_val, u32 vco_val, + struct alpha_pll_clk *pll) +{ + struct alpha_pll_masks *masks = pll->masks; + u32 regval; + + a_val = a_val << (ALPHA_REG_BITWIDTH - ALPHA_BITWIDTH); + + writel_relaxed(l_val, L_REG(pll)); + __iowrite32_copy(A_REG(pll), &a_val, 2); + + if (vco_val != UINT_MAX) { + regval = readl_relaxed(VCO_REG(pll)); + regval &= ~(masks->vco_mask << masks->vco_shift); + regval |= vco_val << masks->vco_shift; + writel_relaxed(regval, VCO_REG(pll)); + } + + regval = readl_relaxed(ALPHA_EN_REG(pll)); + regval |= masks->alpha_en_mask; + writel_relaxed(regval, ALPHA_EN_REG(pll)); +} + +static int alpha_pll_enable(struct clk *c) +{ + struct alpha_pll_clk *pll = to_alpha_pll_clk(c); + unsigned long flags; + int rc; + + if (unlikely(!pll->inited)) + __init_alpha_pll(c); + + spin_lock_irqsave(&alpha_pll_reg_lock, flags); + if (pll->fsm_en_mask) + rc = __alpha_pll_vote_enable(pll); + else + rc = __alpha_pll_enable(pll, true); + spin_unlock_irqrestore(&alpha_pll_reg_lock, flags); + + return rc; +} + +static int __calibrate_alpha_pll(struct alpha_pll_clk *pll); +static int dyna_alpha_pll_enable(struct clk *c) +{ + struct alpha_pll_clk *pll = to_alpha_pll_clk(c); + unsigned long flags; + int rc; + + if (unlikely(!pll->inited)) + __init_alpha_pll(c); + + spin_lock_irqsave(&alpha_pll_reg_lock, flags); + + if (pll->slew) + __calibrate_alpha_pll(pll); + + if (pll->fsm_en_mask) + rc = __alpha_pll_vote_enable(pll); + else + rc = __alpha_pll_enable(pll, true); + spin_unlock_irqrestore(&alpha_pll_reg_lock, flags); + + return rc; +} + +#define PLL_OFFLINE_REQ_BIT BIT(7) +#define PLL_FSM_ENA_BIT BIT(20) +#define PLL_OFFLINE_ACK_BIT BIT(28) +#define PLL_ACTIVE_FLAG BIT(30) + +static int alpha_pll_enable_hwfsm(struct clk *c) +{ + u32 mode; + struct alpha_pll_clk *pll = to_alpha_pll_clk(c); + + /* Re-enable HW FSM mode, clear OFFLINE request */ + mode = readl_relaxed(MODE_REG(pll)); + mode |= PLL_FSM_ENA_BIT; + mode &= ~PLL_OFFLINE_REQ_BIT; + writel_relaxed(mode, MODE_REG(pll)); + + /* Make sure enable request goes through before waiting for update */ + mb(); + + if (wait_for_update(pll) < 0) + panic("PLL %s failed to lock", c->dbg_name); + + return 0; +} + +static void alpha_pll_disable_hwfsm(struct clk *c) +{ + u32 mode; + struct alpha_pll_clk *pll = to_alpha_pll_clk(c); + + /* Request PLL_OFFLINE and wait for ack */ + mode = readl_relaxed(MODE_REG(pll)); + writel_relaxed(mode | PLL_OFFLINE_REQ_BIT, MODE_REG(pll)); + while (!(readl_relaxed(MODE_REG(pll)) & PLL_OFFLINE_ACK_BIT)) + ; + + /* Disable HW FSM */ + mode = readl_relaxed(MODE_REG(pll)); + mode &= ~PLL_FSM_ENA_BIT; + if (pll->offline_bit_workaround) + mode &= ~PLL_OFFLINE_REQ_BIT; + writel_relaxed(mode, MODE_REG(pll)); + + while (readl_relaxed(MODE_REG(pll)) & PLL_ACTIVE_FLAG) + ; +} + +static void __alpha_pll_vote_disable(struct alpha_pll_clk *pll) +{ + u32 ena; + + ena = readl_relaxed(VOTE_REG(pll)); + ena &= ~pll->fsm_en_mask; + writel_relaxed(ena, VOTE_REG(pll)); +} + +static void __alpha_pll_disable(struct alpha_pll_clk *pll) +{ + u32 mode; + + mode = readl_relaxed(MODE_REG(pll)); + mode &= ~PLL_OUTCTRL; + writel_relaxed(mode, MODE_REG(pll)); + + /* Delay of 2 output clock ticks required until output is disabled */ + mb(); + udelay(1); + + mode &= ~(PLL_BYPASSNL | PLL_RESET_N); + writel_relaxed(mode, MODE_REG(pll)); +} + +static void alpha_pll_disable(struct clk *c) +{ + struct alpha_pll_clk *pll = to_alpha_pll_clk(c); + unsigned long flags; + + spin_lock_irqsave(&alpha_pll_reg_lock, flags); + if (pll->fsm_en_mask) + __alpha_pll_vote_disable(pll); + else + __alpha_pll_disable(pll); + spin_unlock_irqrestore(&alpha_pll_reg_lock, flags); +} + +static void dyna_alpha_pll_disable(struct clk *c) +{ + struct alpha_pll_clk *pll = to_alpha_pll_clk(c); + unsigned long flags; + + spin_lock_irqsave(&alpha_pll_reg_lock, flags); + if (pll->fsm_en_mask) + __alpha_pll_vote_disable(pll); + else + __alpha_pll_disable(pll); + + spin_unlock_irqrestore(&alpha_pll_reg_lock, flags); +} + +static u32 find_vco(struct alpha_pll_clk *pll, unsigned long rate) +{ + unsigned long i; + struct alpha_pll_vco_tbl *v = pll->vco_tbl; + + for (i = 0; i < pll->num_vco; i++) { + if (rate >= v[i].min_freq && rate <= v[i].max_freq) + return v[i].vco_val; + } + + return -EINVAL; +} + +static unsigned long __calc_values(struct alpha_pll_clk *pll, + unsigned long rate, int *l_val, u64 *a_val, bool round_up) +{ + u32 parent_rate; + u64 remainder; + u64 quotient; + unsigned long freq_hz; + int alpha_bw = ALPHA_BITWIDTH; + + parent_rate = clk_get_rate(pll->c.parent); + quotient = rate; + remainder = do_div(quotient, parent_rate); + *l_val = quotient; + + if (!remainder) { + *a_val = 0; + return rate; + } + + if (pll->is_fabia) + alpha_bw = FABIA_ALPHA_BITWIDTH; + + /* Upper ALPHA_BITWIDTH bits of Alpha */ + quotient = remainder << alpha_bw; + remainder = do_div(quotient, parent_rate); + + if (remainder && round_up) + quotient++; + + *a_val = quotient; + freq_hz = compute_rate(pll, *l_val, *a_val); + return freq_hz; +} + +static unsigned long round_rate_down(struct alpha_pll_clk *pll, + unsigned long rate, int *l_val, u64 *a_val) +{ + return __calc_values(pll, rate, l_val, a_val, false); +} + +static unsigned long round_rate_up(struct alpha_pll_clk *pll, + unsigned long rate, int *l_val, u64 *a_val) +{ + return __calc_values(pll, rate, l_val, a_val, true); +} + +static bool dynamic_update_finish(struct alpha_pll_clk *pll) +{ + u32 reg = readl_relaxed(UPDATE_REG(pll)); + u32 mask = pll->masks->update_mask; + + return (reg & mask) == 0; +} + +static int wait_for_dynamic_update(struct alpha_pll_clk *pll) +{ + int count; + + for (count = WAIT_MAX_LOOPS; count > 0; count--) { + if (dynamic_update_finish(pll)) + break; + udelay(1); + } + + if (!count) { + pr_err("%s didn't latch after updating it!\n", pll->c.dbg_name); + return -EINVAL; + } + + return 0; +} + +static int dyna_alpha_pll_dynamic_update(struct alpha_pll_clk *pll) +{ + struct alpha_pll_masks *masks = pll->masks; + u32 regval; + int rc; + + regval = readl_relaxed(UPDATE_REG(pll)); + regval |= masks->update_mask; + writel_relaxed(regval, UPDATE_REG(pll)); + + rc = wait_for_dynamic_update(pll); + if (rc < 0) + return rc; + + /* + * HPG mandates a wait of at least 570ns before polling the LOCK + * detect bit. Have a delay of 1us just to be safe. + */ + mb(); + udelay(1); + + rc = wait_for_update(pll); + if (rc < 0) + return rc; + + return 0; +} + +static int alpha_pll_set_rate(struct clk *c, unsigned long rate); +static int dyna_alpha_pll_set_rate(struct clk *c, unsigned long rate) +{ + struct alpha_pll_clk *pll = to_alpha_pll_clk(c); + unsigned long freq_hz, flags; + u32 l_val, vco_val; + u64 a_val; + int ret; + + freq_hz = round_rate_up(pll, rate, &l_val, &a_val); + if (freq_hz != rate) { + pr_err("alpha_pll: Call clk_set_rate with rounded rates!\n"); + return -EINVAL; + } + + vco_val = find_vco(pll, freq_hz); + + /* + * Dynamic pll update will not support switching frequencies across + * vco ranges. In those cases fall back to normal alpha set rate. + */ + if (pll->current_vco_val != vco_val) { + ret = alpha_pll_set_rate(c, rate); + if (!ret) + pll->current_vco_val = vco_val; + else + return ret; + return 0; + } + + spin_lock_irqsave(&c->lock, flags); + + a_val = a_val << (ALPHA_REG_BITWIDTH - ALPHA_BITWIDTH); + + writel_relaxed(l_val, L_REG(pll)); + __iowrite32_copy(A_REG(pll), &a_val, 2); + + /* Ensure that the write above goes through before proceeding. */ + mb(); + + if (c->count) + dyna_alpha_pll_dynamic_update(pll); + + spin_unlock_irqrestore(&c->lock, flags); + return 0; +} + +/* + * Slewing plls should be bought up at frequency which is in the middle of the + * desired VCO range. So after bringing up the pll at calibration freq, set it + * back to desired frequency(that was set by previous clk_set_rate). + */ +static int __calibrate_alpha_pll(struct alpha_pll_clk *pll) +{ + unsigned long calibration_freq, freq_hz; + struct alpha_pll_vco_tbl *vco_tbl = pll->vco_tbl; + u64 a_val; + u32 l_val, vco_val; + int rc; + + vco_val = find_vco(pll, pll->c.rate); + if (IS_ERR_VALUE(vco_val)) { + pr_err("alpha pll: not in a valid vco range\n"); + return -EINVAL; + } + /* + * As during slewing plls vco_sel won't be allowed to change, vco table + * should have only one entry table, i.e. index = 0, find the + * calibration frequency. + */ + calibration_freq = (vco_tbl[0].min_freq + + vco_tbl[0].max_freq)/2; + + freq_hz = round_rate_up(pll, calibration_freq, &l_val, &a_val); + if (freq_hz != calibration_freq) { + pr_err("alpha_pll: call clk_set_rate with rounded rates!\n"); + return -EINVAL; + } + + setup_alpha_pll_values(a_val, l_val, vco_tbl->vco_val, pll); + + /* Bringup the pll at calibration frequency */ + rc = __alpha_pll_enable(pll, false); + if (rc) { + pr_err("alpha pll calibration failed\n"); + return rc; + } + + /* + * PLL is already running at calibration frequency. + * So slew pll to the previously set frequency. + */ + pr_debug("pll %s: setting back to required rate %lu\n", pll->c.dbg_name, + pll->c.rate); + freq_hz = round_rate_up(pll, pll->c.rate, &l_val, &a_val); + setup_alpha_pll_values(a_val, l_val, UINT_MAX, pll); + dyna_alpha_pll_dynamic_update(pll); + + return 0; +} + +static int alpha_pll_dynamic_update(struct alpha_pll_clk *pll) +{ + u32 regval; + + /* Latch the input to the PLL */ + regval = readl_relaxed(MODE_REG(pll)); + regval |= pll->masks->update_mask; + writel_relaxed(regval, MODE_REG(pll)); + + /* Wait for 2 reference cycle before checking ACK bit */ + udelay(1); + if (!(readl_relaxed(MODE_REG(pll)) & ALPHA_PLL_ACK_LATCH)) { + WARN(1, "%s: PLL latch failed. Output may be unstable!\n", + pll->c.dbg_name); + return -EINVAL; + } + + /* Return latch input to 0 */ + regval = readl_relaxed(MODE_REG(pll)); + regval &= ~pll->masks->update_mask; + writel_relaxed(regval, MODE_REG(pll)); + + /* Wait for PLL output to stabilize */ + udelay(100); + + return 0; +} + +static int alpha_pll_set_rate(struct clk *c, unsigned long rate) +{ + struct alpha_pll_clk *pll = to_alpha_pll_clk(c); + struct alpha_pll_masks *masks = pll->masks; + unsigned long flags, freq_hz; + u32 regval, l_val; + int vco_val; + u64 a_val; + + freq_hz = round_rate_up(pll, rate, &l_val, &a_val); + if (freq_hz != rate) { + pr_err("alpha_pll: Call clk_set_rate with rounded rates!\n"); + return -EINVAL; + } + + vco_val = find_vco(pll, freq_hz); + if (IS_ERR_VALUE(vco_val)) { + pr_err("alpha pll: not in a valid vco range\n"); + return -EINVAL; + } + + if (pll->no_irq_dis) + spin_lock(&c->lock); + else + spin_lock_irqsave(&c->lock, flags); + + /* + * For PLLs that do not support dynamic programming (dynamic_update + * is not set), ensure PLL is off before changing rate. For + * optimization reasons, assume no downstream clock is actively + * using it. + */ + if (c->count && !pll->dynamic_update) + c->ops->disable(c); + + a_val = a_val << (ALPHA_REG_BITWIDTH - ALPHA_BITWIDTH); + + writel_relaxed(l_val, L_REG(pll)); + __iowrite32_copy(A_REG(pll), &a_val, 2); + + if (masks->vco_mask) { + regval = readl_relaxed(VCO_REG(pll)); + regval &= ~(masks->vco_mask << masks->vco_shift); + regval |= vco_val << masks->vco_shift; + writel_relaxed(regval, VCO_REG(pll)); + } + + regval = readl_relaxed(ALPHA_EN_REG(pll)); + regval |= masks->alpha_en_mask; + writel_relaxed(regval, ALPHA_EN_REG(pll)); + + if (c->count && pll->dynamic_update) + alpha_pll_dynamic_update(pll); + + if (c->count && !pll->dynamic_update) + c->ops->enable(c); + + if (pll->no_irq_dis) + spin_unlock(&c->lock); + else + spin_unlock_irqrestore(&c->lock, flags); + return 0; +} + +static long alpha_pll_round_rate(struct clk *c, unsigned long rate) +{ + struct alpha_pll_clk *pll = to_alpha_pll_clk(c); + struct alpha_pll_vco_tbl *v = pll->vco_tbl; + int ret; + u32 l_val; + unsigned long freq_hz; + u64 a_val; + int i; + + if (pll->no_prepared_reconfig && c->prepare_count) + return -EINVAL; + + freq_hz = round_rate_up(pll, rate, &l_val, &a_val); + if (rate < pll->min_supported_freq) + return pll->min_supported_freq; + if (pll->is_fabia) + return freq_hz; + + ret = find_vco(pll, freq_hz); + if (!IS_ERR_VALUE(ret)) + return freq_hz; + + freq_hz = 0; + for (i = 0; i < pll->num_vco; i++) { + if (is_better_rate(rate, freq_hz, v[i].min_freq)) + freq_hz = v[i].min_freq; + if (is_better_rate(rate, freq_hz, v[i].max_freq)) + freq_hz = v[i].max_freq; + } + if (!freq_hz) + return -EINVAL; + return freq_hz; +} + +static void update_vco_tbl(struct alpha_pll_clk *pll) +{ + int i, l_val; + u64 a_val; + unsigned long hz; + + /* Round vco limits to valid rates */ + for (i = 0; i < pll->num_vco; i++) { + hz = round_rate_up(pll, pll->vco_tbl[i].min_freq, &l_val, + &a_val); + pll->vco_tbl[i].min_freq = hz; + + hz = round_rate_down(pll, pll->vco_tbl[i].max_freq, &l_val, + &a_val); + pll->vco_tbl[i].max_freq = hz; + } +} + +/* + * Program bias count to be 0x6 (corresponds to 5us), and lock count + * bits to 0 (check lock_det for locking). + */ +static void __set_fsm_mode(void __iomem *mode_reg) +{ + u32 regval = readl_relaxed(mode_reg); + + /* De-assert reset to FSM */ + regval &= ~BIT(21); + writel_relaxed(regval, mode_reg); + + /* Program bias count */ + regval &= ~BM(19, 14); + regval |= BVAL(19, 14, 0x6); + writel_relaxed(regval, mode_reg); + + /* Program lock count */ + regval &= ~BM(13, 8); + regval |= BVAL(13, 8, 0x0); + writel_relaxed(regval, mode_reg); + + /* Enable PLL FSM voting */ + regval |= BIT(20); + writel_relaxed(regval, mode_reg); +} + +static bool is_fsm_mode(void __iomem *mode_reg) +{ + return !!(readl_relaxed(mode_reg) & BIT(20)); +} + +void __init_alpha_pll(struct clk *c) +{ + struct alpha_pll_clk *pll = to_alpha_pll_clk(c); + struct alpha_pll_masks *masks = pll->masks; + u32 regval; + + if (pll->config_ctl_val) + writel_relaxed(pll->config_ctl_val, CONFIG_CTL_REG(pll)); + + if (masks->output_mask && pll->enable_config) { + regval = readl_relaxed(OUTPUT_REG(pll)); + regval &= ~masks->output_mask; + regval |= pll->enable_config; + writel_relaxed(regval, OUTPUT_REG(pll)); + } + + if (masks->post_div_mask) { + regval = readl_relaxed(USER_CTL_LO_REG(pll)); + regval &= ~masks->post_div_mask; + regval |= pll->post_div_config; + writel_relaxed(regval, USER_CTL_LO_REG(pll)); + } + + if (pll->slew) { + regval = readl_relaxed(USER_CTL_HI_REG(pll)); + regval &= ~PLL_LATCH_INTERFACE; + writel_relaxed(regval, USER_CTL_HI_REG(pll)); + } + + if (masks->test_ctl_lo_mask) { + regval = readl_relaxed(TEST_CTL_LO_REG(pll)); + regval &= ~masks->test_ctl_lo_mask; + regval |= pll->test_ctl_lo_val; + writel_relaxed(regval, TEST_CTL_LO_REG(pll)); + } + + if (masks->test_ctl_hi_mask) { + regval = readl_relaxed(TEST_CTL_HI_REG(pll)); + regval &= ~masks->test_ctl_hi_mask; + regval |= pll->test_ctl_hi_val; + writel_relaxed(regval, TEST_CTL_HI_REG(pll)); + } + + if (pll->fsm_en_mask) + __set_fsm_mode(MODE_REG(pll)); + + pll->inited = true; +} + +static enum handoff alpha_pll_handoff(struct clk *c) +{ + struct alpha_pll_clk *pll = to_alpha_pll_clk(c); + struct alpha_pll_masks *masks = pll->masks; + u64 a_val; + u32 alpha_en, l_val, regval; + + /* Set the PLL_HW_UPDATE_LOGIC_BYPASS bit before continuing */ + if (pll->dynamic_update) { + regval = readl_relaxed(MODE_REG(pll)); + regval |= ALPHA_PLL_HW_UPDATE_LOGIC_BYPASS; + writel_relaxed(regval, MODE_REG(pll)); + } + + update_vco_tbl(pll); + + if (!is_locked(pll)) { + if (c->rate && alpha_pll_set_rate(c, c->rate)) + WARN(1, "%s: Failed to configure rate\n", c->dbg_name); + __init_alpha_pll(c); + return HANDOFF_DISABLED_CLK; + } else if (pll->fsm_en_mask && !is_fsm_mode(MODE_REG(pll))) { + WARN(1, "%s should be in FSM mode but is not\n", c->dbg_name); + } + + l_val = readl_relaxed(L_REG(pll)); + /* read u64 in two steps to satisfy alignment constraint */ + a_val = readl_relaxed(A_REG(pll) + 0x4); + a_val = a_val << 32 | readl_relaxed(A_REG(pll)); + /* get upper 32 bits */ + a_val = a_val >> (ALPHA_REG_BITWIDTH - ALPHA_BITWIDTH); + + alpha_en = readl_relaxed(ALPHA_EN_REG(pll)); + alpha_en &= masks->alpha_en_mask; + if (!alpha_en) + a_val = 0; + + c->rate = compute_rate(pll, l_val, a_val); + + /* + * Unconditionally vote for the PLL; it might be on because of + * another master's vote. + */ + if (pll->fsm_en_mask) + __alpha_pll_vote_enable(pll); + + return HANDOFF_ENABLED_CLK; +} + +static void __iomem *alpha_pll_list_registers(struct clk *clk, int n, + struct clk_register_data **regs, u32 *size) +{ + struct alpha_pll_clk *pll = to_alpha_pll_clk(clk); + static struct clk_register_data data[] = { + {"PLL_MODE", 0x0}, + {"PLL_L_VAL", 0x4}, + {"PLL_ALPHA_VAL", 0x8}, + {"PLL_ALPHA_VAL_U", 0xC}, + {"PLL_USER_CTL", 0x10}, + {"PLL_CONFIG_CTL", 0x18}, + }; + + if (n) + return ERR_PTR(-EINVAL); + + *regs = data; + *size = ARRAY_SIZE(data); + return MODE_REG(pll); +} + +static int __fabia_alpha_pll_enable(struct alpha_pll_clk *pll) +{ + int rc; + u32 mode; + + /* Disable PLL output */ + mode = readl_relaxed(MODE_REG(pll)); + mode &= ~PLL_OUTCTRL; + writel_relaxed(mode, MODE_REG(pll)); + + /* Set operation mode to STANDBY */ + writel_relaxed(FABIA_PLL_STANDBY, FABIA_PLL_OPMODE(pll)); + + /* PLL should be in STANDBY mode before continuing */ + mb(); + + /* Bring PLL out of reset */ + mode = readl_relaxed(MODE_REG(pll)); + mode |= PLL_RESET_N; + writel_relaxed(mode, MODE_REG(pll)); + + /* Set operation mode to RUN */ + writel_relaxed(FABIA_PLL_RUN, FABIA_PLL_OPMODE(pll)); + + rc = wait_for_update(pll); + if (rc < 0) + return rc; + + /* Enable the main PLL output */ + mode = readl_relaxed(FABIA_USER_CTL_LO_REG(pll)); + mode |= FABIA_PLL_OUT_MAIN; + writel_relaxed(mode, FABIA_USER_CTL_LO_REG(pll)); + + /* Enable PLL outputs */ + mode = readl_relaxed(MODE_REG(pll)); + mode |= PLL_OUTCTRL; + writel_relaxed(mode, MODE_REG(pll)); + + /* Ensure that the write above goes through before returning. */ + mb(); + return 0; +} + +static int fabia_alpha_pll_enable(struct clk *c) +{ + struct alpha_pll_clk *pll = to_alpha_pll_clk(c); + unsigned long flags; + int rc; + + spin_lock_irqsave(&alpha_pll_reg_lock, flags); + if (pll->fsm_en_mask) + rc = __alpha_pll_vote_enable(pll); + else + rc = __fabia_alpha_pll_enable(pll); + spin_unlock_irqrestore(&alpha_pll_reg_lock, flags); + + return rc; +} + +static void __fabia_alpha_pll_disable(struct alpha_pll_clk *pll) +{ + u32 mode; + + /* Disable PLL outputs */ + mode = readl_relaxed(MODE_REG(pll)); + mode &= ~PLL_OUTCTRL; + writel_relaxed(mode, MODE_REG(pll)); + + /* Disable the main PLL output */ + mode = readl_relaxed(FABIA_USER_CTL_LO_REG(pll)); + mode &= ~FABIA_PLL_OUT_MAIN; + writel_relaxed(mode, FABIA_USER_CTL_LO_REG(pll)); + + /* Place the PLL mode in STANDBY */ + writel_relaxed(FABIA_PLL_STANDBY, FABIA_PLL_OPMODE(pll)); +} + +static void fabia_alpha_pll_disable(struct clk *c) +{ + struct alpha_pll_clk *pll = to_alpha_pll_clk(c); + unsigned long flags; + + spin_lock_irqsave(&alpha_pll_reg_lock, flags); + if (pll->fsm_en_mask) + __alpha_pll_vote_disable(pll); + else + __fabia_alpha_pll_disable(pll); + spin_unlock_irqrestore(&alpha_pll_reg_lock, flags); +} + +static int fabia_alpha_pll_set_rate(struct clk *c, unsigned long rate) +{ + struct alpha_pll_clk *pll = to_alpha_pll_clk(c); + unsigned long flags, freq_hz; + u32 l_val; + u64 a_val; + + freq_hz = round_rate_up(pll, rate, &l_val, &a_val); + if (freq_hz > rate + FABIA_RATE_MARGIN || freq_hz < rate) { + pr_err("%s: Call clk_set_rate with rounded rates!\n", + c->dbg_name); + return -EINVAL; + } + + spin_lock_irqsave(&c->lock, flags); + /* Set the new L value */ + writel_relaxed(l_val, FABIA_L_REG(pll)); + /* + * pll_cal_l_val is set to pll_l_val on MOST targets. Set it + * explicitly here for PLL out-of-reset calibration to work + * without a glitch on all of them. + */ + writel_relaxed(l_val, FABIA_CAL_L_VAL(pll)); + writel_relaxed(a_val, FABIA_FRAC_REG(pll)); + + alpha_pll_dynamic_update(pll); + + spin_unlock_irqrestore(&c->lock, flags); + return 0; +} + +void __init_fabia_alpha_pll(struct clk *c) +{ + struct alpha_pll_clk *pll = to_alpha_pll_clk(c); + struct alpha_pll_masks *masks = pll->masks; + u32 regval; + + if (pll->config_ctl_val) + writel_relaxed(pll->config_ctl_val, FABIA_CONFIG_CTL_REG(pll)); + + if (masks->output_mask && pll->enable_config) { + regval = readl_relaxed(FABIA_USER_CTL_LO_REG(pll)); + regval &= ~masks->output_mask; + regval |= pll->enable_config; + writel_relaxed(regval, FABIA_USER_CTL_LO_REG(pll)); + } + + if (masks->post_div_mask) { + regval = readl_relaxed(FABIA_USER_CTL_LO_REG(pll)); + regval &= ~masks->post_div_mask; + regval |= pll->post_div_config; + writel_relaxed(regval, FABIA_USER_CTL_LO_REG(pll)); + } + + if (pll->slew) { + regval = readl_relaxed(FABIA_USER_CTL_HI_REG(pll)); + regval &= ~PLL_LATCH_INTERFACE; + writel_relaxed(regval, FABIA_USER_CTL_HI_REG(pll)); + } + + if (masks->test_ctl_lo_mask) { + regval = readl_relaxed(FABIA_TEST_CTL_LO_REG(pll)); + regval &= ~masks->test_ctl_lo_mask; + regval |= pll->test_ctl_lo_val; + writel_relaxed(regval, FABIA_TEST_CTL_LO_REG(pll)); + } + + if (masks->test_ctl_hi_mask) { + regval = readl_relaxed(FABIA_TEST_CTL_HI_REG(pll)); + regval &= ~masks->test_ctl_hi_mask; + regval |= pll->test_ctl_hi_val; + writel_relaxed(regval, FABIA_TEST_CTL_HI_REG(pll)); + } + + if (pll->fsm_en_mask) + __set_fsm_mode(MODE_REG(pll)); + + pll->inited = true; +} + +static enum handoff fabia_alpha_pll_handoff(struct clk *c) +{ + struct alpha_pll_clk *pll = to_alpha_pll_clk(c); + u64 a_val; + u32 l_val, regval; + + /* Set the PLL_HW_UPDATE_LOGIC_BYPASS bit before continuing */ + regval = readl_relaxed(MODE_REG(pll)); + regval |= ALPHA_PLL_HW_UPDATE_LOGIC_BYPASS; + writel_relaxed(regval, MODE_REG(pll)); + + /* Set the PLL_RESET_N bit to place the PLL in STANDBY from OFF */ + regval |= PLL_RESET_N; + writel_relaxed(regval, MODE_REG(pll)); + + if (!is_locked(pll)) { + if (c->rate && fabia_alpha_pll_set_rate(c, c->rate)) + WARN(1, "%s: Failed to configure rate\n", c->dbg_name); + __init_fabia_alpha_pll(c); + return HANDOFF_DISABLED_CLK; + } else if (pll->fsm_en_mask && !is_fsm_mode(MODE_REG(pll))) { + WARN(1, "%s should be in FSM mode but is not\n", c->dbg_name); + } + + l_val = readl_relaxed(FABIA_L_REG(pll)); + a_val = readl_relaxed(FABIA_FRAC_REG(pll)); + + c->rate = compute_rate(pll, l_val, a_val); + + /* + * Unconditionally vote for the PLL; it might be on because of + * another master's vote. + */ + if (pll->fsm_en_mask) + __alpha_pll_vote_enable(pll); + + return HANDOFF_ENABLED_CLK; +} + +struct clk_ops clk_ops_alpha_pll = { + .enable = alpha_pll_enable, + .disable = alpha_pll_disable, + .round_rate = alpha_pll_round_rate, + .set_rate = alpha_pll_set_rate, + .handoff = alpha_pll_handoff, + .list_registers = alpha_pll_list_registers, +}; + +struct clk_ops clk_ops_alpha_pll_hwfsm = { + .enable = alpha_pll_enable_hwfsm, + .disable = alpha_pll_disable_hwfsm, + .round_rate = alpha_pll_round_rate, + .set_rate = alpha_pll_set_rate, + .handoff = alpha_pll_handoff, + .list_registers = alpha_pll_list_registers, +}; + +struct clk_ops clk_ops_fixed_alpha_pll = { + .enable = alpha_pll_enable, + .disable = alpha_pll_disable, + .handoff = alpha_pll_handoff, + .list_registers = alpha_pll_list_registers, +}; + +struct clk_ops clk_ops_fixed_fabia_alpha_pll = { + .enable = fabia_alpha_pll_enable, + .disable = fabia_alpha_pll_disable, + .handoff = fabia_alpha_pll_handoff, +}; + +struct clk_ops clk_ops_fabia_alpha_pll = { + .enable = fabia_alpha_pll_enable, + .disable = fabia_alpha_pll_disable, + .round_rate = alpha_pll_round_rate, + .set_rate = fabia_alpha_pll_set_rate, + .handoff = fabia_alpha_pll_handoff, +}; + +struct clk_ops clk_ops_dyna_alpha_pll = { + .enable = dyna_alpha_pll_enable, + .disable = dyna_alpha_pll_disable, + .round_rate = alpha_pll_round_rate, + .set_rate = dyna_alpha_pll_set_rate, + .handoff = alpha_pll_handoff, + .list_registers = alpha_pll_list_registers, +}; + +static struct alpha_pll_masks masks_20nm_p = { + .lock_mask = BIT(31), + .active_mask = BIT(30), + .vco_mask = BM(21, 20) >> 20, + .vco_shift = 20, + .alpha_en_mask = BIT(24), + .output_mask = 0xF, + .post_div_mask = 0xF00, +}; + +static struct alpha_pll_vco_tbl vco_20nm_p[] = { + VCO(3, 250000000, 500000000), + VCO(2, 500000000, 1000000000), + VCO(1, 1000000000, 1500000000), + VCO(0, 1500000000, 2000000000), +}; + +static struct alpha_pll_masks masks_20nm_t = { + .lock_mask = BIT(31), + .alpha_en_mask = BIT(24), + .output_mask = 0xf, +}; + +static struct alpha_pll_vco_tbl vco_20nm_t[] = { + VCO(0, 500000000, 1250000000), +}; + +static struct alpha_pll_clk *alpha_pll_dt_parser(struct device *dev, + struct device_node *np) +{ + struct alpha_pll_clk *pll; + struct msmclk_data *drv; + + pll = devm_kzalloc(dev, sizeof(*pll), GFP_KERNEL); + if (!pll) { + dt_err(np, "memory alloc failure\n"); + return ERR_PTR(-ENOMEM); + } + + if (of_property_read_u32(np, "qcom,base-offset", &pll->offset)) { + dt_err(np, "missing qcom,base-offset\n"); + return ERR_PTR(-EINVAL); + } + + /* Optional property */ + of_property_read_u32(np, "qcom,post-div-config", + &pll->post_div_config); + + pll->masks = devm_kzalloc(dev, sizeof(*pll->masks), GFP_KERNEL); + if (!pll->masks) { + dt_err(np, "memory alloc failure\n"); + return ERR_PTR(-ENOMEM); + } + + if (of_device_is_compatible(np, "qcom,fixed-alpha-pll-20p") || + of_device_is_compatible(np, "qcom,alpha-pll-20p")) { + *pll->masks = masks_20nm_p; + pll->vco_tbl = vco_20nm_p; + pll->num_vco = ARRAY_SIZE(vco_20nm_p); + } else if (of_device_is_compatible(np, "qcom,fixed-alpha-pll-20t") || + of_device_is_compatible(np, "qcom,alpha-pll-20t")) { + *pll->masks = masks_20nm_t; + pll->vco_tbl = vco_20nm_t; + pll->num_vco = ARRAY_SIZE(vco_20nm_t); + } else { + dt_err(np, "unexpected compatible string\n"); + return ERR_PTR(-EINVAL); + } + + drv = msmclk_parse_phandle(dev, np->parent->phandle); + if (IS_ERR_OR_NULL(drv)) + return ERR_CAST(drv); + pll->base = &drv->base; + return pll; +} + +static void *variable_rate_alpha_pll_dt_parser(struct device *dev, + struct device_node *np) +{ + struct alpha_pll_clk *pll; + + pll = alpha_pll_dt_parser(dev, np); + if (IS_ERR(pll)) + return pll; + + /* Optional Property */ + of_property_read_u32(np, "qcom,output-enable", &pll->enable_config); + + pll->c.ops = &clk_ops_alpha_pll; + return msmclk_generic_clk_init(dev, np, &pll->c); +} + +static void *fixed_rate_alpha_pll_dt_parser(struct device *dev, + struct device_node *np) +{ + struct alpha_pll_clk *pll; + int rc; + u32 val; + + pll = alpha_pll_dt_parser(dev, np); + if (IS_ERR(pll)) + return pll; + + rc = of_property_read_u32(np, "qcom,pll-config-rate", &val); + if (rc) { + dt_err(np, "missing qcom,pll-config-rate\n"); + return ERR_PTR(-EINVAL); + } + pll->c.rate = val; + + rc = of_property_read_u32(np, "qcom,output-enable", + &pll->enable_config); + if (rc) { + dt_err(np, "missing qcom,output-enable\n"); + return ERR_PTR(-EINVAL); + } + + /* Optional Property */ + rc = of_property_read_u32(np, "qcom,fsm-en-bit", &val); + if (!rc) { + rc = of_property_read_u32(np, "qcom,fsm-en-offset", + &pll->fsm_reg_offset); + if (rc) { + dt_err(np, "missing qcom,fsm-en-offset\n"); + return ERR_PTR(-EINVAL); + } + pll->fsm_en_mask = BIT(val); + } + + pll->c.ops = &clk_ops_fixed_alpha_pll; + return msmclk_generic_clk_init(dev, np, &pll->c); +} + +MSMCLK_PARSER(fixed_rate_alpha_pll_dt_parser, "qcom,fixed-alpha-pll-20p", 0); +MSMCLK_PARSER(fixed_rate_alpha_pll_dt_parser, "qcom,fixed-alpha-pll-20t", 1); +MSMCLK_PARSER(variable_rate_alpha_pll_dt_parser, "qcom,alpha-pll-20p", 0); +MSMCLK_PARSER(variable_rate_alpha_pll_dt_parser, "qcom,alpha-pll-20t", 1); diff -Nruw linux-4.4.115-fbx/drivers/clk/msm./clock.c linux-4.4.115-fbx/drivers/clk/msm/clock.c --- linux-4.4.115-fbx/drivers/clk/msm./clock.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-4.4.115-fbx/drivers/clk/msm/clock.c 2019-01-22 16:16:23.019242024 +0100 @@ -0,0 +1,1389 @@ +/* arch/arm/mach-msm/clock.c + * + * Copyright (C) 2007 Google, Inc. + * Copyright (c) 2007-2015, The Linux Foundation. All rights reserved. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include "clock.h" + +struct handoff_clk { + struct list_head list; + struct clk *clk; +}; +static LIST_HEAD(handoff_list); + +struct handoff_vdd { + struct list_head list; + struct clk_vdd_class *vdd_class; +}; +static LIST_HEAD(handoff_vdd_list); + +static DEFINE_MUTEX(msm_clock_init_lock); +LIST_HEAD(orphan_clk_list); +static LIST_HEAD(clk_notifier_list); + +/* Find the voltage level required for a given rate. */ +int find_vdd_level(struct clk *clk, unsigned long rate) +{ + int level; + + for (level = 0; level < clk->num_fmax; level++) + if (rate <= clk->fmax[level]) + break; + + if (level == clk->num_fmax) { + pr_err("Rate %lu for %s is greater than highest Fmax\n", rate, + clk->dbg_name); + return -EINVAL; + } + + return level; +} + +/* Update voltage level given the current votes. */ +static int update_vdd(struct clk_vdd_class *vdd_class) +{ + int level, rc = 0, i, ignore; + struct regulator **r = vdd_class->regulator; + int *uv = vdd_class->vdd_uv; + int *ua = vdd_class->vdd_ua; + int n_reg = vdd_class->num_regulators; + int cur_lvl = vdd_class->cur_level; + int max_lvl = vdd_class->num_levels - 1; + int cur_base = cur_lvl * n_reg; + int new_base; + + /* aggregate votes */ + for (level = max_lvl; level > 0; level--) + if (vdd_class->level_votes[level]) + break; + + if (level == cur_lvl) + return 0; + + max_lvl = max_lvl * n_reg; + new_base = level * n_reg; + for (i = 0; i < vdd_class->num_regulators; i++) { + rc = regulator_set_voltage(r[i], uv[new_base + i], + vdd_class->use_max_uV ? INT_MAX : uv[max_lvl + i]); + if (rc) + goto set_voltage_fail; + + if (ua) { + rc = regulator_set_load(r[i], ua[new_base + i]); + rc = rc > 0 ? 0 : rc; + if (rc) + goto set_mode_fail; + } + if (cur_lvl == 0 || cur_lvl == vdd_class->num_levels) + rc = regulator_enable(r[i]); + else if (level == 0) + rc = regulator_disable(r[i]); + if (rc) + goto enable_disable_fail; + } + if (vdd_class->set_vdd && !vdd_class->num_regulators) + rc = vdd_class->set_vdd(vdd_class, level); + + if (!rc) + vdd_class->cur_level = level; + + return rc; + +enable_disable_fail: + /* + * set_optimum_mode could use voltage to derive mode. Restore + * previous voltage setting for r[i] first. + */ + if (ua) { + regulator_set_voltage(r[i], uv[cur_base + i], + vdd_class->use_max_uV ? INT_MAX : uv[max_lvl + i]); + regulator_set_load(r[i], ua[cur_base + i]); + } + +set_mode_fail: + regulator_set_voltage(r[i], uv[cur_base + i], + vdd_class->use_max_uV ? INT_MAX : uv[max_lvl + i]); + +set_voltage_fail: + for (i--; i >= 0; i--) { + regulator_set_voltage(r[i], uv[cur_base + i], + vdd_class->use_max_uV ? INT_MAX : uv[max_lvl + i]); + if (ua) + regulator_set_load(r[i], ua[cur_base + i]); + if (cur_lvl == 0 || cur_lvl == vdd_class->num_levels) + regulator_disable(r[i]); + else if (level == 0) + ignore = regulator_enable(r[i]); + } + return rc; +} + +/* Vote for a voltage level. */ +int vote_vdd_level(struct clk_vdd_class *vdd_class, int level) +{ + int rc; + + if (level >= vdd_class->num_levels) + return -EINVAL; + + mutex_lock(&vdd_class->lock); + vdd_class->level_votes[level]++; + rc = update_vdd(vdd_class); + if (rc) + vdd_class->level_votes[level]--; + mutex_unlock(&vdd_class->lock); + + return rc; +} + +/* Remove vote for a voltage level. */ +int unvote_vdd_level(struct clk_vdd_class *vdd_class, int level) +{ + int rc = 0; + + if (level >= vdd_class->num_levels) + return -EINVAL; + + mutex_lock(&vdd_class->lock); + if (WARN(!vdd_class->level_votes[level], + "Reference counts are incorrect for %s level %d\n", + vdd_class->class_name, level)) + goto out; + vdd_class->level_votes[level]--; + rc = update_vdd(vdd_class); + if (rc) + vdd_class->level_votes[level]++; +out: + mutex_unlock(&vdd_class->lock); + return rc; +} + +/* Vote for a voltage level corresponding to a clock's rate. */ +static int vote_rate_vdd(struct clk *clk, unsigned long rate) +{ + int level; + + if (!clk->vdd_class) + return 0; + + level = find_vdd_level(clk, rate); + if (level < 0) + return level; + + return vote_vdd_level(clk->vdd_class, level); +} + +/* Remove vote for a voltage level corresponding to a clock's rate. */ +static void unvote_rate_vdd(struct clk *clk, unsigned long rate) +{ + int level; + + if (!clk->vdd_class) + return; + + level = find_vdd_level(clk, rate); + if (level < 0) + return; + + unvote_vdd_level(clk->vdd_class, level); +} + +/* Check if the rate is within the voltage limits of the clock. */ +bool is_rate_valid(struct clk *clk, unsigned long rate) +{ + int level; + + if (!clk->vdd_class) + return true; + + level = find_vdd_level(clk, rate); + return level >= 0; +} + +/** + * __clk_pre_reparent() - Set up the new parent before switching to it and + * prevent the enable state of the child clock from changing. + * @c: The child clock that's going to switch parents + * @new: The new parent that the child clock is going to switch to + * @flags: Pointer to scratch space to save spinlock flags + * + * Cannot be called from atomic context. + * + * Use this API to set up the @new parent clock to be able to support the + * current prepare and enable state of the child clock @c. Once the parent is + * set up, the child clock can safely switch to it. + * + * The caller shall grab the prepare_lock of clock @c before calling this API + * and only release it after calling __clk_post_reparent() for clock @c (or + * if this API fails). This is necessary to prevent the prepare state of the + * child clock @c from changing while the reparenting is in progress. Since + * this API takes care of grabbing the enable lock of @c, only atomic + * operation are allowed between calls to __clk_pre_reparent and + * __clk_post_reparent() + * + * The scratch space pointed to by @flags should not be altered before + * calling __clk_post_reparent() for clock @c. + * + * See also: __clk_post_reparent() + */ +int __clk_pre_reparent(struct clk *c, struct clk *new, unsigned long *flags) +{ + int rc; + + if (c->prepare_count) { + rc = clk_prepare(new); + if (rc) + return rc; + } + + spin_lock_irqsave(&c->lock, *flags); + if (c->count) { + rc = clk_enable(new); + if (rc) { + spin_unlock_irqrestore(&c->lock, *flags); + clk_unprepare(new); + return rc; + } + } + return 0; +} + +/** + * __clk_post_reparent() - Release requirements on old parent after switching + * away from it and allow changes to the child clock's enable state. + * @c: The child clock that switched parents + * @old: The old parent that the child clock switched away from or the new + * parent of a failed reparent attempt. + * @flags: Pointer to scratch space where spinlock flags were saved + * + * Cannot be called from atomic context. + * + * This API works in tandem with __clk_pre_reparent. Use this API to + * - Remove prepare and enable requirements from the @old parent after + * switching away from it + * - Or, undo the effects of __clk_pre_reparent() after a failed attempt to + * change parents + * + * The caller shall release the prepare_lock of @c that was grabbed before + * calling __clk_pre_reparent() only after this API is called (or if + * __clk_pre_reparent() fails). This is necessary to prevent the prepare + * state of the child clock @c from changing while the reparenting is in + * progress. Since this API releases the enable lock of @c, the limit to + * atomic operations set by __clk_pre_reparent() is no longer present. + * + * The scratch space pointed to by @flags shall not be altered since the call + * to __clk_pre_reparent() for clock @c. + * + * See also: __clk_pre_reparent() + */ +void __clk_post_reparent(struct clk *c, struct clk *old, unsigned long *flags) +{ + if (c->count) + clk_disable(old); + spin_unlock_irqrestore(&c->lock, *flags); + + if (c->prepare_count) + clk_unprepare(old); +} + +int clk_prepare(struct clk *clk) +{ + int ret = 0; + struct clk *parent; + + if (!clk) + return 0; + if (IS_ERR(clk)) + return -EINVAL; + + mutex_lock(&clk->prepare_lock); + if (clk->prepare_count == 0) { + parent = clk->parent; + + ret = clk_prepare(parent); + if (ret) + goto out; + ret = clk_prepare(clk->depends); + if (ret) + goto err_prepare_depends; + + ret = vote_rate_vdd(clk, clk->rate); + if (ret) + goto err_vote_vdd; + if (clk->ops->prepare) + ret = clk->ops->prepare(clk); + if (ret) + goto err_prepare_clock; + } + clk->prepare_count++; +out: + mutex_unlock(&clk->prepare_lock); + return ret; +err_prepare_clock: + unvote_rate_vdd(clk, clk->rate); +err_vote_vdd: + clk_unprepare(clk->depends); +err_prepare_depends: + clk_unprepare(parent); + goto out; +} +EXPORT_SYMBOL(clk_prepare); + +/* + * Standard clock functions defined in include/linux/clk.h + */ +int clk_enable(struct clk *clk) +{ + int ret = 0; + unsigned long flags; + struct clk *parent; + const char *name; + + if (!clk) + return 0; + if (IS_ERR(clk)) + return -EINVAL; + name = clk->dbg_name; + + spin_lock_irqsave(&clk->lock, flags); + WARN(!clk->prepare_count, + "%s: Don't call enable on unprepared clocks\n", name); + if (clk->count == 0) { + parent = clk->parent; + + ret = clk_enable(parent); + if (ret) + goto err_enable_parent; + ret = clk_enable(clk->depends); + if (ret) + goto err_enable_depends; + + trace_clock_enable(name, 1, smp_processor_id()); + if (clk->ops->enable) + ret = clk->ops->enable(clk); + if (ret) + goto err_enable_clock; + } + clk->count++; + spin_unlock_irqrestore(&clk->lock, flags); + + return 0; + +err_enable_clock: + clk_disable(clk->depends); +err_enable_depends: + clk_disable(parent); +err_enable_parent: + spin_unlock_irqrestore(&clk->lock, flags); + return ret; +} +EXPORT_SYMBOL(clk_enable); + +void clk_disable(struct clk *clk) +{ + const char *name; + unsigned long flags; + + if (IS_ERR_OR_NULL(clk)) + return; + name = clk->dbg_name; + + spin_lock_irqsave(&clk->lock, flags); + WARN(!clk->prepare_count, + "%s: Never called prepare or calling disable after unprepare\n", + name); + if (WARN(clk->count == 0, "%s is unbalanced", name)) + goto out; + if (clk->count == 1) { + struct clk *parent = clk->parent; + + trace_clock_disable(name, 0, smp_processor_id()); + if (clk->ops->disable) + clk->ops->disable(clk); + clk_disable(clk->depends); + clk_disable(parent); + } + clk->count--; +out: + spin_unlock_irqrestore(&clk->lock, flags); +} +EXPORT_SYMBOL(clk_disable); + +void clk_unprepare(struct clk *clk) +{ + const char *name; + + if (IS_ERR_OR_NULL(clk)) + return; + name = clk->dbg_name; + + mutex_lock(&clk->prepare_lock); + if (WARN(!clk->prepare_count, "%s is unbalanced (prepare)", name)) + goto out; + if (clk->prepare_count == 1) { + struct clk *parent = clk->parent; + + WARN(clk->count, + "%s: Don't call unprepare when the clock is enabled\n", + name); + + if (clk->ops->unprepare) + clk->ops->unprepare(clk); + unvote_rate_vdd(clk, clk->rate); + clk_unprepare(clk->depends); + clk_unprepare(parent); + } + clk->prepare_count--; +out: + mutex_unlock(&clk->prepare_lock); +} +EXPORT_SYMBOL(clk_unprepare); + +int clk_reset(struct clk *clk, enum clk_reset_action action) +{ + if (IS_ERR_OR_NULL(clk)) + return -EINVAL; + + if (!clk->ops->reset) + return -ENOSYS; + + return clk->ops->reset(clk, action); +} +EXPORT_SYMBOL(clk_reset); + +/** + * __clk_notify - call clk notifier chain + * @clk: struct clk * that is changing rate + * @msg: clk notifier type (see include/linux/clk.h) + * @old_rate: old clk rate + * @new_rate: new clk rate + * + * Triggers a notifier call chain on the clk rate-change notification + * for 'clk'. Passes a pointer to the struct clk and the previous + * and current rates to the notifier callback. Intended to be called by + * internal clock code only. Returns NOTIFY_DONE from the last driver + * called if all went well, or NOTIFY_STOP or NOTIFY_BAD immediately if + * a driver returns that. + */ +static int __clk_notify(struct clk *clk, unsigned long msg, + unsigned long old_rate, unsigned long new_rate) +{ + struct msm_clk_notifier *cn; + struct msm_clk_notifier_data cnd; + int ret = NOTIFY_DONE; + + cnd.clk = clk; + cnd.old_rate = old_rate; + cnd.new_rate = new_rate; + + list_for_each_entry(cn, &clk_notifier_list, node) { + if (cn->clk == clk) { + ret = srcu_notifier_call_chain(&cn->notifier_head, msg, + &cnd); + break; + } + } + + return ret; +} + +/* + * clk rate change notifiers + * + * Note - The following notifier functionality is a verbatim copy + * of the implementation in the common clock framework, copied here + * until MSM switches to the common clock framework. + */ + +/** + * msm_clk_notif_register - add a clk rate change notifier + * @clk: struct clk * to watch + * @nb: struct notifier_block * with callback info + * + * Request notification when clk's rate changes. This uses an SRCU + * notifier because we want it to block and notifier unregistrations are + * uncommon. The callbacks associated with the notifier must not + * re-enter into the clk framework by calling any top-level clk APIs; + * this will cause a nested prepare_lock mutex. + * + * Pre-change notifier callbacks will be passed the current, pre-change + * rate of the clk via struct msm_clk_notifier_data.old_rate. The new, + * post-change rate of the clk is passed via struct + * msm_clk_notifier_data.new_rate. + * + * Post-change notifiers will pass the now-current, post-change rate of + * the clk in both struct msm_clk_notifier_data.old_rate and struct + * msm_clk_notifier_data.new_rate. + * + * Abort-change notifiers are effectively the opposite of pre-change + * notifiers: the original pre-change clk rate is passed in via struct + * msm_clk_notifier_data.new_rate and the failed post-change rate is passed + * in via struct msm_clk_notifier_data.old_rate. + * + * msm_clk_notif_register() must be called from non-atomic context. + * Returns -EINVAL if called with null arguments, -ENOMEM upon + * allocation failure; otherwise, passes along the return value of + * srcu_notifier_chain_register(). + */ +int msm_clk_notif_register(struct clk *clk, struct notifier_block *nb) +{ + struct msm_clk_notifier *cn; + int ret = -ENOMEM; + + if (!clk || !nb) + return -EINVAL; + + mutex_lock(&clk->prepare_lock); + + /* search the list of notifiers for this clk */ + list_for_each_entry(cn, &clk_notifier_list, node) + if (cn->clk == clk) + break; + + /* if clk wasn't in the notifier list, allocate new clk_notifier */ + if (cn->clk != clk) { + cn = kzalloc(sizeof(struct msm_clk_notifier), GFP_KERNEL); + if (!cn) + goto out; + + cn->clk = clk; + srcu_init_notifier_head(&cn->notifier_head); + + list_add(&cn->node, &clk_notifier_list); + } + + ret = srcu_notifier_chain_register(&cn->notifier_head, nb); + + clk->notifier_count++; + +out: + mutex_unlock(&clk->prepare_lock); + + return ret; +} + +/** + * msm_clk_notif_unregister - remove a clk rate change notifier + * @clk: struct clk * + * @nb: struct notifier_block * with callback info + * + * Request no further notification for changes to 'clk' and frees memory + * allocated in msm_clk_notifier_register. + * + * Returns -EINVAL if called with null arguments; otherwise, passes + * along the return value of srcu_notifier_chain_unregister(). + */ +int msm_clk_notif_unregister(struct clk *clk, struct notifier_block *nb) +{ + struct msm_clk_notifier *cn = NULL; + int ret = -EINVAL; + + if (!clk || !nb) + return -EINVAL; + + mutex_lock(&clk->prepare_lock); + + list_for_each_entry(cn, &clk_notifier_list, node) + if (cn->clk == clk) + break; + + if (cn->clk == clk) { + ret = srcu_notifier_chain_unregister(&cn->notifier_head, nb); + + clk->notifier_count--; + + /* XXX the notifier code should handle this better */ + if (!cn->notifier_head.head) { + srcu_cleanup_notifier_head(&cn->notifier_head); + list_del(&cn->node); + kfree(cn); + } + + } else { + ret = -ENOENT; + } + + mutex_unlock(&clk->prepare_lock); + + return ret; +} + +unsigned long clk_get_rate(struct clk *clk) +{ + if (IS_ERR_OR_NULL(clk)) + return 0; + + if (!clk->ops->get_rate) + return clk->rate; + + return clk->ops->get_rate(clk); +} +EXPORT_SYMBOL(clk_get_rate); + +int clk_set_rate(struct clk *clk, unsigned long rate) +{ + unsigned long start_rate; + int rc = 0; + const char *name; + + if (IS_ERR_OR_NULL(clk)) + return -EINVAL; + name = clk->dbg_name; + + if (!is_rate_valid(clk, rate)) + return -EINVAL; + + mutex_lock(&clk->prepare_lock); + + /* Return early if the rate isn't going to change */ + if (clk->rate == rate && !(clk->flags & CLKFLAG_NO_RATE_CACHE)) + goto out; + + if (!clk->ops->set_rate) { + rc = -ENOSYS; + goto out; + } + + trace_clock_set_rate(name, rate, raw_smp_processor_id()); + + start_rate = clk->rate; + + if (clk->notifier_count) + __clk_notify(clk, PRE_RATE_CHANGE, clk->rate, rate); + + if (clk->ops->pre_set_rate) { + rc = clk->ops->pre_set_rate(clk, rate); + if (rc) + goto abort_set_rate; + } + + /* Enforce vdd requirements for target frequency. */ + if (clk->prepare_count) { + rc = vote_rate_vdd(clk, rate); + if (rc) + goto err_vote_vdd; + } + + rc = clk->ops->set_rate(clk, rate); + if (rc) + goto err_set_rate; + clk->rate = rate; + + /* Release vdd requirements for starting frequency. */ + if (clk->prepare_count) + unvote_rate_vdd(clk, start_rate); + + if (clk->ops->post_set_rate) + clk->ops->post_set_rate(clk, start_rate); + + if (clk->notifier_count) + __clk_notify(clk, POST_RATE_CHANGE, start_rate, clk->rate); + + trace_clock_set_rate_complete(name, clk->rate, raw_smp_processor_id()); +out: + mutex_unlock(&clk->prepare_lock); + return rc; + +abort_set_rate: + __clk_notify(clk, ABORT_RATE_CHANGE, clk->rate, rate); +err_set_rate: + if (clk->prepare_count) + unvote_rate_vdd(clk, rate); +err_vote_vdd: + /* clk->rate is still the old rate. So, pass the new rate instead. */ + if (clk->ops->post_set_rate) + clk->ops->post_set_rate(clk, rate); + goto out; +} +EXPORT_SYMBOL(clk_set_rate); + +long clk_round_rate(struct clk *clk, unsigned long rate) +{ + long rrate; + unsigned long fmax = 0, i; + + if (IS_ERR_OR_NULL(clk)) + return -EINVAL; + + for (i = 0; i < clk->num_fmax; i++) + fmax = max(fmax, clk->fmax[i]); + if (!fmax) + fmax = ULONG_MAX; + rate = min(rate, fmax); + + if (clk->ops->round_rate) + rrate = clk->ops->round_rate(clk, rate); + else if (clk->rate) + rrate = clk->rate; + else + return -ENOSYS; + + if (rrate > fmax) + return -EINVAL; + return rrate; +} +EXPORT_SYMBOL(clk_round_rate); + +int clk_set_max_rate(struct clk *clk, unsigned long rate) +{ + if (IS_ERR_OR_NULL(clk)) + return -EINVAL; + + if (!clk->ops->set_max_rate) + return -ENOSYS; + + return clk->ops->set_max_rate(clk, rate); +} +EXPORT_SYMBOL(clk_set_max_rate); + +int parent_to_src_sel(struct clk_src *parents, int num_parents, struct clk *p) +{ + int i; + + for (i = 0; i < num_parents; i++) { + if (parents[i].src == p) + return parents[i].sel; + } + + return -EINVAL; +} +EXPORT_SYMBOL(parent_to_src_sel); + +int clk_get_parent_sel(struct clk *c, struct clk *parent) +{ + return parent_to_src_sel(c->parents, c->num_parents, parent); +} +EXPORT_SYMBOL(clk_get_parent_sel); + +int clk_set_parent(struct clk *clk, struct clk *parent) +{ + int rc = 0; + if (IS_ERR_OR_NULL(clk)) + return -EINVAL; + + if (!clk->ops->set_parent && clk->parent == parent) + return 0; + + if (!clk->ops->set_parent) + return -ENOSYS; + + mutex_lock(&clk->prepare_lock); + if (clk->parent == parent && !(clk->flags & CLKFLAG_NO_RATE_CACHE)) + goto out; + rc = clk->ops->set_parent(clk, parent); +out: + mutex_unlock(&clk->prepare_lock); + + return rc; +} +EXPORT_SYMBOL(clk_set_parent); + +struct clk *clk_get_parent(struct clk *clk) +{ + if (IS_ERR_OR_NULL(clk)) + return NULL; + + return clk->parent; +} +EXPORT_SYMBOL(clk_get_parent); + +int clk_set_flags(struct clk *clk, unsigned long flags) +{ + if (IS_ERR_OR_NULL(clk)) + return -EINVAL; + if (!clk->ops->set_flags) + return -ENOSYS; + + return clk->ops->set_flags(clk, flags); +} +EXPORT_SYMBOL(clk_set_flags); + +static LIST_HEAD(initdata_list); + +static void init_sibling_lists(struct clk_lookup *clock_tbl, size_t num_clocks) +{ + struct clk *clk, *parent; + unsigned n; + + for (n = 0; n < num_clocks; n++) { + clk = clock_tbl[n].clk; + parent = clk->parent; + if (parent && list_empty(&clk->siblings)) + list_add(&clk->siblings, &parent->children); + } +} + +static void vdd_class_init(struct clk_vdd_class *vdd) +{ + struct handoff_vdd *v; + + if (!vdd) + return; + + if (vdd->skip_handoff) + return; + + list_for_each_entry(v, &handoff_vdd_list, list) { + if (v->vdd_class == vdd) + return; + } + + pr_debug("voting for vdd_class %s\n", vdd->class_name); + if (vote_vdd_level(vdd, vdd->num_levels - 1)) + pr_err("failed to vote for %s\n", vdd->class_name); + + v = kmalloc(sizeof(*v), GFP_KERNEL); + if (!v) { + pr_err("Unable to kmalloc. %s will be stuck at max.\n", + vdd->class_name); + return; + } + + v->vdd_class = vdd; + list_add_tail(&v->list, &handoff_vdd_list); +} + +static int __handoff_clk(struct clk *clk) +{ + enum handoff state = HANDOFF_DISABLED_CLK; + struct handoff_clk *h = NULL; + int rc, i; + + if (clk == NULL || clk->flags & CLKFLAG_INIT_DONE || + clk->flags & CLKFLAG_SKIP_HANDOFF) + return 0; + + if (clk->flags & CLKFLAG_INIT_ERR) + return -ENXIO; + + if (clk->flags & CLKFLAG_EPROBE_DEFER) + return -EPROBE_DEFER; + + /* Handoff any 'depends' clock first. */ + rc = __handoff_clk(clk->depends); + if (rc) + goto err; + + /* + * Handoff functions for the parent must be called before the + * children can be handed off. Without handing off the parents and + * knowing their rate and state (on/off), it's impossible to figure + * out the rate and state of the children. + */ + if (clk->ops->get_parent) + clk->parent = clk->ops->get_parent(clk); + + if (IS_ERR(clk->parent)) { + rc = PTR_ERR(clk->parent); + goto err; + } + + rc = __handoff_clk(clk->parent); + if (rc) + goto err; + + for (i = 0; i < clk->num_parents; i++) { + rc = __handoff_clk(clk->parents[i].src); + if (rc) + goto err; + } + + if (clk->ops->handoff) + state = clk->ops->handoff(clk); + + if (state == HANDOFF_ENABLED_CLK) { + + h = kmalloc(sizeof(*h), GFP_KERNEL); + if (!h) { + rc = -ENOMEM; + goto err; + } + + rc = clk_prepare_enable(clk->parent); + if (rc) + goto err; + + rc = clk_prepare_enable(clk->depends); + if (rc) + goto err_depends; + + rc = vote_rate_vdd(clk, clk->rate); + WARN(rc, "%s unable to vote for voltage!\n", clk->dbg_name); + + clk->count = 1; + clk->prepare_count = 1; + h->clk = clk; + list_add_tail(&h->list, &handoff_list); + + pr_debug("Handed off %s rate=%lu\n", clk->dbg_name, clk->rate); + } + + if (clk->init_rate && clk_set_rate(clk, clk->init_rate)) + pr_err("failed to set an init rate of %lu on %s\n", + clk->init_rate, clk->dbg_name); + if (clk->always_on && clk_prepare_enable(clk)) + pr_err("failed to enable always-on clock %s\n", + clk->dbg_name); + + clk->flags |= CLKFLAG_INIT_DONE; + /* if the clk is on orphan list, remove it */ + list_del_init(&clk->list); + clock_debug_register(clk); + + return 0; + +err_depends: + clk_disable_unprepare(clk->parent); +err: + kfree(h); + if (rc == -EPROBE_DEFER) { + clk->flags |= CLKFLAG_EPROBE_DEFER; + if (list_empty(&clk->list)) + list_add_tail(&clk->list, &orphan_clk_list); + } else { + pr_err("%s handoff failed (%d)\n", clk->dbg_name, rc); + clk->flags |= CLKFLAG_INIT_ERR; + } + return rc; +} + +/** + * msm_clock_register() - Register additional clock tables + * @table: Table of clocks + * @size: Size of @table + * + * Upon return, clock APIs may be used to control clocks registered using this + * function. + */ +int msm_clock_register(struct clk_lookup *table, size_t size) +{ + int n = 0, rc; + struct clk *c, *safe; + bool found_more_clks; + + mutex_lock(&msm_clock_init_lock); + + init_sibling_lists(table, size); + + /* + * Enable regulators and temporarily set them up at maximum voltage. + * Once all the clocks have made their respective vote, remove this + * temporary vote. The removing of the temporary vote is done at + * late_init, by which time we assume all the clocks would have been + * handed off. + */ + for (n = 0; n < size; n++) + vdd_class_init(table[n].clk->vdd_class); + + /* + * Detect and preserve initial clock state until clock_late_init() or + * a driver explicitly changes it, whichever is first. + */ + + for (n = 0; n < size; n++) + __handoff_clk(table[n].clk); + + /* maintain backwards compatibility */ + if (table[0].con_id || table[0].dev_id) + clkdev_add_table(table, size); + + do { + found_more_clks = false; + /* clear cached __handoff_clk return values */ + list_for_each_entry_safe(c, safe, &orphan_clk_list, list) + c->flags &= ~CLKFLAG_EPROBE_DEFER; + + list_for_each_entry_safe(c, safe, &orphan_clk_list, list) { + rc = __handoff_clk(c); + if (!rc) + found_more_clks = true; + } + } while (found_more_clks); + + mutex_unlock(&msm_clock_init_lock); + + return 0; +} +EXPORT_SYMBOL(msm_clock_register); + +struct of_msm_provider_data { + struct clk_lookup *table; + size_t size; +}; + +static struct clk *of_clk_src_get(struct of_phandle_args *clkspec, + void *data) +{ + struct of_msm_provider_data *ofdata = data; + int n; + + for (n = 0; n < ofdata->size; n++) { + if (clkspec->args[0] == ofdata->table[n].of_idx) + return ofdata->table[n].clk; + } + return ERR_PTR(-ENOENT); +} + +#define MAX_LEN_OPP_HANDLE 50 +#define LEN_OPP_HANDLE 16 +#define LEN_OPP_VCORNER_HANDLE 22 + +static struct device **derive_device_list(struct clk *clk, + struct device_node *np, + char *clk_handle_name, int len) +{ + int j, count, cpu; + struct platform_device *pdev; + struct device_node *dev_node; + struct device **device_list; + + count = len/sizeof(u32); + device_list = kmalloc_array(count, sizeof(struct device *), + GFP_KERNEL); + if (!device_list) + return ERR_PTR(-ENOMEM); + + for (j = 0; j < count; j++) { + device_list[j] = NULL; + dev_node = of_parse_phandle(np, clk_handle_name, j); + if (!dev_node) { + pr_err("Unable to get device_node pointer for %s opp-handle (%s)\n", + clk->dbg_name, clk_handle_name); + goto err_parse_phandle; + } + + for_each_possible_cpu(cpu) { + if (of_get_cpu_node(cpu, NULL) == dev_node) { + device_list[j] = get_cpu_device(cpu); + } + } + + if (device_list[j]) + continue; + + pdev = of_find_device_by_node(dev_node); + if (!pdev) { + pr_err("Unable to find platform_device node for %s opp-handle\n", + clk->dbg_name); + goto err_parse_phandle; + } + device_list[j] = &pdev->dev; + } + return device_list; +err_parse_phandle: + kfree(device_list); + return ERR_PTR(-EINVAL); +} + +static int get_voltage(struct clk *clk, unsigned long rate, + int store_vcorner, int n) +{ + struct clk_vdd_class *vdd; + int uv, level, corner; + + /* + * Use the first regulator in the vdd class + * for the OPP table. + */ + vdd = clk->vdd_class; + if (vdd->num_regulators > 1) { + corner = vdd->vdd_uv[vdd->num_regulators * n]; + } else { + level = find_vdd_level(clk, rate); + if (level < 0) { + pr_err("Could not find vdd level\n"); + return -EINVAL; + } + corner = vdd->vdd_uv[level]; + } + + if (!corner) { + pr_err("%s: Unable to find vdd level for rate %lu\n", + clk->dbg_name, rate); + return -EINVAL; + } + + if (store_vcorner) { + uv = corner; + return uv; + } + + uv = regulator_list_corner_voltage(vdd->regulator[0], corner); + if (uv < 0) { + pr_err("%s: no uv for corner %d - err: %d\n", + clk->dbg_name, corner, uv); + return uv; + } + return uv; +} + +static int add_and_print_opp(struct clk *clk, struct device **device_list, + int count, unsigned long rate, int uv, int n) +{ + int j, ret = 0; + + for (j = 0; j < count; j++) { + ret = dev_pm_opp_add(device_list[j], rate, uv); + if (ret) { + pr_err("%s: couldn't add OPP for %lu - err: %d\n", + clk->dbg_name, rate, ret); + return ret; + } + if (n == 1 || n == clk->num_fmax - 1 || + rate == clk_round_rate(clk, INT_MAX)) + pr_info("%s: set OPP pair(%lu Hz: %u uV) on %s\n", + clk->dbg_name, rate, uv, + dev_name(device_list[j])); + } + return ret; +} + +static void populate_clock_opp_table(struct device_node *np, + struct clk_lookup *table, size_t size) +{ + struct device **device_list; + struct clk *clk; + char clk_handle_name[MAX_LEN_OPP_HANDLE]; + char clk_store_volt_corner[MAX_LEN_OPP_HANDLE]; + size_t i; + int n, len, count, uv = 0; + unsigned long rate, ret = 0; + bool store_vcorner; + + /* Iterate across all clocks in the clock controller */ + for (i = 0; i < size; i++) { + n = 1; + rate = 0; + + store_vcorner = false; + clk = table[i].clk; + if (!clk || !clk->num_fmax || clk->opp_table_populated) + continue; + + if (strlen(clk->dbg_name) + LEN_OPP_HANDLE + < MAX_LEN_OPP_HANDLE) { + ret = snprintf(clk_handle_name, + ARRAY_SIZE(clk_handle_name), + "qcom,%s-opp-handle", clk->dbg_name); + if (ret < strlen(clk->dbg_name) + LEN_OPP_HANDLE) { + pr_err("Failed to hold clk_handle_name\n"); + continue; + } + } else { + pr_err("clk name (%s) too large to fit in clk_handle_name\n", + clk->dbg_name); + continue; + } + + if (strlen(clk->dbg_name) + LEN_OPP_VCORNER_HANDLE + < MAX_LEN_OPP_HANDLE) { + ret = snprintf(clk_store_volt_corner, + ARRAY_SIZE(clk_store_volt_corner), + "qcom,%s-opp-store-vcorner", clk->dbg_name); + if (ret < strlen(clk->dbg_name) + + LEN_OPP_VCORNER_HANDLE) { + pr_err("Failed to hold clk_store_volt_corner\n"); + continue; + } + } else { + pr_err("clk name (%s) too large to fit in clk_store_volt_corner\n", + clk->dbg_name); + continue; + } + + if (!of_find_property(np, clk_handle_name, &len)) { + pr_debug("Unable to find %s\n", clk_handle_name); + if (!of_find_property(np, clk_store_volt_corner, + &len)) { + pr_debug("Unable to find %s\n", + clk_store_volt_corner); + continue; + } else { + store_vcorner = true; + device_list = derive_device_list(clk, np, + clk_store_volt_corner, len); + } + } else + device_list = derive_device_list(clk, np, + clk_handle_name, len); + if (IS_ERR_OR_NULL(device_list)) { + pr_err("Failed to fill device_list\n"); + continue; + } + + count = len/sizeof(u32); + while (1) { + /* + * Calling clk_round_rate will not work for all clocks + * (eg. mux_div). Use their fmax values instead to get + * list of all available frequencies. + */ + if (clk->ops->list_rate) { + ret = clk_round_rate(clk, rate + 1); + if (ret < 0) { + pr_err("clk_round_rate failed for %s\n", + clk->dbg_name); + goto err_round_rate; + } + /* + * If clk_round_rate give the same value on + * consecutive iterations, exit loop since + * we're at the maximum clock frequency. + */ + if (rate == ret) + break; + rate = ret; + } else { + if (n < clk->num_fmax) + rate = clk->fmax[n]; + else + break; + } + + uv = get_voltage(clk, rate, store_vcorner, n); + if (uv < 0) + goto err_round_rate; + + ret = add_and_print_opp(clk, device_list, count, + rate, uv , n); + if (ret) + goto err_round_rate; + + n++; + } +err_round_rate: + /* If OPP table population was successful, set the flag */ + if (uv >= 0 && ret >= 0) + clk->opp_table_populated = true; + kfree(device_list); + } +} + +/** + * of_msm_clock_register() - Register clock tables with clkdev and with the + * clock DT framework + * @table: Table of clocks + * @size: Size of @table + * @np: Device pointer corresponding to the clock-provider device + * + * Upon return, clock APIs may be used to control clocks registered using this + * function. + */ +int of_msm_clock_register(struct device_node *np, struct clk_lookup *table, + size_t size) +{ + int ret = 0; + struct of_msm_provider_data *data; + + data = kzalloc(sizeof(*data), GFP_KERNEL); + if (!data) + return -ENOMEM; + + data->table = table; + data->size = size; + + ret = of_clk_add_provider(np, of_clk_src_get, data); + if (ret) { + kfree(data); + return -ENOMEM; + } + + populate_clock_opp_table(np, table, size); + return msm_clock_register(table, size); +} +EXPORT_SYMBOL(of_msm_clock_register); + +/** + * msm_clock_init() - Register and initialize a clock driver + * @data: Driver-specific clock initialization data + * + * Upon return from this call, clock APIs may be used to control + * clocks registered with this API. + */ +int __init msm_clock_init(struct clock_init_data *data) +{ + if (!data) + return -EINVAL; + + if (data->pre_init) + data->pre_init(); + + mutex_lock(&msm_clock_init_lock); + if (data->late_init) + list_add(&data->list, &initdata_list); + mutex_unlock(&msm_clock_init_lock); + + msm_clock_register(data->table, data->size); + + if (data->post_init) + data->post_init(); + + return 0; +} + +static int __init clock_late_init(void) +{ + struct handoff_clk *h, *h_temp; + struct handoff_vdd *v, *v_temp; + struct clock_init_data *initdata, *initdata_temp; + int ret = 0; + + pr_info("%s: Removing enables held for handed-off clocks\n", __func__); + + mutex_lock(&msm_clock_init_lock); + + list_for_each_entry_safe(initdata, initdata_temp, + &initdata_list, list) { + ret = initdata->late_init(); + if (ret) + pr_err("%s: %pS failed late_init.\n", __func__, + initdata); + } + + list_for_each_entry_safe(h, h_temp, &handoff_list, list) { + clk_disable_unprepare(h->clk); + list_del(&h->list); + kfree(h); + } + + list_for_each_entry_safe(v, v_temp, &handoff_vdd_list, list) { + unvote_vdd_level(v->vdd_class, v->vdd_class->num_levels - 1); + list_del(&v->list); + kfree(v); + } + + mutex_unlock(&msm_clock_init_lock); + + return ret; +} +/* clock_late_init should run only after all deferred probing + * (excluding DLKM probes) has completed. + */ +late_initcall_sync(clock_late_init); diff -Nruw linux-4.4.115-fbx/drivers/clk/msm./clock-debug.c linux-4.4.115-fbx/drivers/clk/msm/clock-debug.c --- linux-4.4.115-fbx/drivers/clk/msm./clock-debug.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-4.4.115-fbx/drivers/clk/msm/clock-debug.c 2019-01-22 16:16:23.015241987 +0100 @@ -0,0 +1,683 @@ +/* + * Copyright (C) 2007 Google, Inc. + * Copyright (c) 2007-2014, 2016-2017, The Linux Foundation. All rights + * reserved. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + + +#include "clock.h" + +static LIST_HEAD(clk_list); +static DEFINE_MUTEX(clk_list_lock); + +static struct dentry *debugfs_base; +static u32 debug_suspend; + +static int clock_debug_rate_set(void *data, u64 val) +{ + struct clk *clock = data; + int ret; + + /* Only increases to max rate will succeed, but that's actually good + * for debugging purposes so we don't check for error. */ + if (clock->flags & CLKFLAG_MAX) + clk_set_max_rate(clock, val); + ret = clk_set_rate(clock, val); + if (ret) + pr_err("clk_set_rate(%s, %lu) failed (%d)\n", clock->dbg_name, + (unsigned long)val, ret); + + return ret; +} + +static int clock_debug_rate_get(void *data, u64 *val) +{ + struct clk *clock = data; + *val = clk_get_rate(clock); + return 0; +} + +DEFINE_SIMPLE_ATTRIBUTE(clock_rate_fops, clock_debug_rate_get, + clock_debug_rate_set, "%llu\n"); + +static struct clk *measure; + +static int clock_debug_measure_get(void *data, u64 *val) +{ + struct clk *clock = data, *par; + int ret, is_hw_gated; + unsigned long meas_rate, sw_rate; + + /* Check to see if the clock is in hardware gating mode */ + if (clock->ops->in_hwcg_mode) + is_hw_gated = clock->ops->in_hwcg_mode(clock); + else + is_hw_gated = 0; + + mutex_lock(&clock->prepare_lock); + ret = clk_set_parent(measure, clock); + if (!ret) { + /* + * Disable hw gating to get accurate rate measurements. Only do + * this if the clock is explictly enabled by software. This + * allows us to detect errors where clocks are on even though + * software is not requesting them to be on due to broken + * hardware gating signals. + */ + if (is_hw_gated && clock->count) + clock->ops->disable_hwcg(clock); + par = measure; + while (par && par != clock) { + if (par->ops->enable) + par->ops->enable(par); + par = par->parent; + } + *val = clk_get_rate(measure); + /* Reenable hwgating if it was disabled */ + if (is_hw_gated && clock->count) + clock->ops->enable_hwcg(clock); + } + + /* + * If there's a divider on the path from the clock output to the + * measurement circuitry, account for it by dividing the original clock + * rate with the rate set on the parent of the measure clock. + */ + meas_rate = clk_get_rate(clock); + sw_rate = clk_get_rate(measure->parent); + mutex_unlock(&clock->prepare_lock); + if (sw_rate && meas_rate >= (sw_rate * 2)) + *val *= DIV_ROUND_CLOSEST(meas_rate, sw_rate); + + return ret; +} + +DEFINE_SIMPLE_ATTRIBUTE(clock_measure_fops, clock_debug_measure_get, + NULL, "%lld\n"); + +static int clock_debug_enable_set(void *data, u64 val) +{ + struct clk *clock = data; + int rc = 0; + + if (val) + rc = clk_prepare_enable(clock); + else + clk_disable_unprepare(clock); + + return rc; +} + +static int clock_debug_enable_get(void *data, u64 *val) +{ + struct clk *clock = data; + int enabled; + + if (clock->ops->is_enabled) + enabled = clock->ops->is_enabled(clock); + else + enabled = !!(clock->count); + + *val = enabled; + return 0; +} + +DEFINE_SIMPLE_ATTRIBUTE(clock_enable_fops, clock_debug_enable_get, + clock_debug_enable_set, "%lld\n"); + +static int clock_debug_local_get(void *data, u64 *val) +{ + struct clk *clock = data; + + if (!clock->ops->is_local) + *val = true; + else + *val = clock->ops->is_local(clock); + + return 0; +} + +DEFINE_SIMPLE_ATTRIBUTE(clock_local_fops, clock_debug_local_get, + NULL, "%llu\n"); + +static int clock_debug_hwcg_get(void *data, u64 *val) +{ + struct clk *clock = data; + if (clock->ops->in_hwcg_mode) + *val = !!clock->ops->in_hwcg_mode(clock); + else + *val = 0; + return 0; +} + +DEFINE_SIMPLE_ATTRIBUTE(clock_hwcg_fops, clock_debug_hwcg_get, + NULL, "%llu\n"); + +static void clock_print_fmax_by_level(struct seq_file *m, int level) +{ + struct clk *clock = m->private; + struct clk_vdd_class *vdd_class = clock->vdd_class; + int off, i, vdd_level, nregs = vdd_class->num_regulators; + + vdd_level = find_vdd_level(clock, clock->rate); + + seq_printf(m, "%2s%10lu", vdd_level == level ? "[" : "", + clock->fmax[level]); + for (i = 0; i < nregs; i++) { + off = nregs*level + i; + if (vdd_class->vdd_uv) + seq_printf(m, "%10u", vdd_class->vdd_uv[off]); + if (vdd_class->vdd_ua) + seq_printf(m, "%10u", vdd_class->vdd_ua[off]); + } + + if (vdd_level == level) + seq_puts(m, "]"); + seq_puts(m, "\n"); +} + +static int fmax_rates_show(struct seq_file *m, void *unused) +{ + struct clk *clock = m->private; + struct clk_vdd_class *vdd_class = clock->vdd_class; + int level = 0, i, nregs = vdd_class->num_regulators; + char reg_name[10]; + + int vdd_level = find_vdd_level(clock, clock->rate); + if (vdd_level < 0) { + seq_printf(m, "could not find_vdd_level for %s, %ld\n", + clock->dbg_name, clock->rate); + return 0; + } + + seq_printf(m, "%12s", ""); + for (i = 0; i < nregs; i++) { + snprintf(reg_name, ARRAY_SIZE(reg_name), "reg %d", i); + seq_printf(m, "%10s", reg_name); + if (vdd_class->vdd_ua) + seq_printf(m, "%10s", ""); + } + + seq_printf(m, "\n%12s", "freq"); + for (i = 0; i < nregs; i++) { + seq_printf(m, "%10s", "uV"); + if (vdd_class->vdd_ua) + seq_printf(m, "%10s", "uA"); + } + seq_printf(m, "\n"); + + for (level = 0; level < clock->num_fmax; level++) + clock_print_fmax_by_level(m, level); + + return 0; +} + +static int fmax_rates_open(struct inode *inode, struct file *file) +{ + return single_open(file, fmax_rates_show, inode->i_private); +} + +static const struct file_operations fmax_rates_fops = { + .open = fmax_rates_open, + .read = seq_read, + .llseek = seq_lseek, + .release = seq_release, +}; + +static int orphan_list_show(struct seq_file *m, void *unused) +{ + struct clk *c, *safe; + + list_for_each_entry_safe(c, safe, &orphan_clk_list, list) + seq_printf(m, "%s\n", c->dbg_name); + + return 0; +} + +static int orphan_list_open(struct inode *inode, struct file *file) +{ + return single_open(file, orphan_list_show, inode->i_private); +} + +static const struct file_operations orphan_list_fops = { + .open = orphan_list_open, + .read = seq_read, + .llseek = seq_lseek, + .release = seq_release, +}; + +#define clock_debug_output(m, c, fmt, ...) \ +do { \ + if (m) \ + seq_printf(m, fmt, ##__VA_ARGS__); \ + else if (c) \ + pr_cont(fmt, ##__VA_ARGS__); \ + else \ + pr_info(fmt, ##__VA_ARGS__); \ +} while (0) + +static int clock_debug_print_clock(struct clk *c, struct seq_file *m) +{ + char *start = ""; + + if (!c || !c->prepare_count) + return 0; + + clock_debug_output(m, 0, "\t"); + do { + if (c->vdd_class) + clock_debug_output(m, 1, "%s%s:%u:%u [%ld, %d]", start, + c->dbg_name, c->prepare_count, c->count, + c->rate, find_vdd_level(c, c->rate)); + else + clock_debug_output(m, 1, "%s%s:%u:%u [%ld]", start, + c->dbg_name, c->prepare_count, c->count, + c->rate); + start = " -> "; + } while ((c = clk_get_parent(c))); + + clock_debug_output(m, 1, "\n"); + + return 1; +} + +/** + * clock_debug_print_enabled_clocks() - Print names of enabled clocks + * + */ +static void clock_debug_print_enabled_clocks(struct seq_file *m) +{ + struct clk *c; + int cnt = 0; + + if (!mutex_trylock(&clk_list_lock)) { + pr_err("clock-debug: Clocks are being registered. Cannot print clock state now.\n"); + return; + } + clock_debug_output(m, 0, "Enabled clocks:\n"); + list_for_each_entry(c, &clk_list, list) { + cnt += clock_debug_print_clock(c, m); + } + mutex_unlock(&clk_list_lock); + + if (cnt) + clock_debug_output(m, 0, "Enabled clock count: %d\n", cnt); + else + clock_debug_output(m, 0, "No clocks enabled.\n"); +} + +static int enabled_clocks_show(struct seq_file *m, void *unused) +{ + clock_debug_print_enabled_clocks(m); + return 0; +} + +static int enabled_clocks_open(struct inode *inode, struct file *file) +{ + return single_open(file, enabled_clocks_show, inode->i_private); +} + +static const struct file_operations enabled_clocks_fops = { + .open = enabled_clocks_open, + .read = seq_read, + .llseek = seq_lseek, + .release = seq_release, +}; + +static int trace_clocks_show(struct seq_file *m, void *unused) +{ + struct clk *c; + int total_cnt = 0; + + if (!mutex_trylock(&clk_list_lock)) { + pr_err("trace_clocks: Clocks are being registered. Cannot trace clock state now.\n"); + return 1; + } + list_for_each_entry(c, &clk_list, list) { + int vlevel = 0; + + if (c->num_fmax) + vlevel = find_vdd_level(c, c->rate); + trace_clock_state(c->dbg_name, c->prepare_count, c->count, + c->rate, vlevel); + total_cnt++; + } + mutex_unlock(&clk_list_lock); + clock_debug_output(m, 0, "Total clock count: %d\n", total_cnt); + + return 0; +} + +static int trace_clocks_open(struct inode *inode, struct file *file) +{ + return single_open(file, trace_clocks_show, inode->i_private); +} +static const struct file_operations trace_clocks_fops = { + .open = trace_clocks_open, + .read = seq_read, + .llseek = seq_lseek, + .release = seq_release, +}; + +static int list_rates_show(struct seq_file *m, void *unused) +{ + struct clk *clock = m->private; + int level, i = 0; + unsigned long rate, fmax = 0; + + /* Find max frequency supported within voltage constraints. */ + if (!clock->vdd_class) { + fmax = ULONG_MAX; + } else { + for (level = 0; level < clock->num_fmax; level++) + if (clock->fmax[level]) + fmax = clock->fmax[level]; + } + + /* + * List supported frequencies <= fmax. Higher frequencies may appear in + * the frequency table, but are not valid and should not be listed. + */ + while (!IS_ERR_VALUE(rate = clock->ops->list_rate(clock, i++))) { + if (rate <= fmax) + seq_printf(m, "%lu\n", rate); + } + + return 0; +} + +static int list_rates_open(struct inode *inode, struct file *file) +{ + return single_open(file, list_rates_show, inode->i_private); +} + +static const struct file_operations list_rates_fops = { + .open = list_rates_open, + .read = seq_read, + .llseek = seq_lseek, + .release = seq_release, +}; + +static ssize_t clock_parent_read(struct file *filp, char __user *ubuf, + size_t cnt, loff_t *ppos) +{ + struct clk *clock = filp->private_data; + struct clk *p = clock->parent; + char name[256] = {0}; + + snprintf(name, sizeof(name), "%s\n", p ? p->dbg_name : "None\n"); + + return simple_read_from_buffer(ubuf, cnt, ppos, name, strlen(name)); +} + + +static ssize_t clock_parent_write(struct file *filp, + const char __user *ubuf, size_t cnt, loff_t *ppos) +{ + struct clk *clock = filp->private_data; + char buf[256]; + char *cmp; + int ret; + struct clk *parent = NULL; + + cnt = min(cnt, sizeof(buf) - 1); + if (copy_from_user(&buf, ubuf, cnt)) + return -EFAULT; + buf[cnt] = '\0'; + cmp = strstrip(buf); + + mutex_lock(&clk_list_lock); + list_for_each_entry(parent, &clk_list, list) { + if (!strcmp(cmp, parent->dbg_name)) + break; + } + + if (&parent->list == &clk_list) { + ret = -EINVAL; + goto err; + } + + mutex_unlock(&clk_list_lock); + ret = clk_set_parent(clock, parent); + if (ret) + return ret; + + return cnt; +err: + mutex_unlock(&clk_list_lock); + return ret; +} + + +static const struct file_operations clock_parent_fops = { + .open = simple_open, + .read = clock_parent_read, + .write = clock_parent_write, +}; + +void clk_debug_print_hw(struct clk *clk, struct seq_file *f) +{ + void __iomem *base; + struct clk_register_data *regs; + u32 i, j, size; + + if (IS_ERR_OR_NULL(clk)) + return; + + clk_debug_print_hw(clk->parent, f); + + clock_debug_output(f, false, "%s\n", clk->dbg_name); + + if (!clk->ops->list_registers) + return; + + j = 0; + base = clk->ops->list_registers(clk, j, ®s, &size); + while (!IS_ERR(base)) { + for (i = 0; i < size; i++) { + u32 val = readl_relaxed(base + regs[i].offset); + clock_debug_output(f, false, "%20s: 0x%.8x\n", + regs[i].name, val); + } + j++; + base = clk->ops->list_registers(clk, j, ®s, &size); + } +} + +static int print_hw_show(struct seq_file *m, void *unused) +{ + struct clk *c = m->private; + clk_debug_print_hw(c, m); + + return 0; +} + +static int print_hw_open(struct inode *inode, struct file *file) +{ + return single_open(file, print_hw_show, inode->i_private); +} + +static const struct file_operations clock_print_hw_fops = { + .open = print_hw_open, + .read = seq_read, + .llseek = seq_lseek, + .release = seq_release, +}; + + +static void clock_measure_add(struct clk *clock) +{ + if (IS_ERR_OR_NULL(measure)) + return; + + if (clk_set_parent(measure, clock)) + return; + + debugfs_create_file("measure", S_IRUGO, clock->clk_dir, clock, + &clock_measure_fops); +} + +static int clock_debug_add(struct clk *clock) +{ + char temp[50], *ptr; + struct dentry *clk_dir; + + if (!debugfs_base) + return -ENOMEM; + + strlcpy(temp, clock->dbg_name, ARRAY_SIZE(temp)); + for (ptr = temp; *ptr; ptr++) + *ptr = tolower(*ptr); + + clk_dir = debugfs_create_dir(temp, debugfs_base); + if (!clk_dir) + return -ENOMEM; + + clock->clk_dir = clk_dir; + + if (!debugfs_create_file("rate", S_IRUGO | S_IWUSR, clk_dir, + clock, &clock_rate_fops)) + goto error; + + if (!debugfs_create_file("enable", S_IRUGO | S_IWUSR, clk_dir, + clock, &clock_enable_fops)) + goto error; + + if (!debugfs_create_file("is_local", S_IRUGO, clk_dir, clock, + &clock_local_fops)) + goto error; + + if (!debugfs_create_file("has_hw_gating", S_IRUGO, clk_dir, clock, + &clock_hwcg_fops)) + goto error; + + if (clock->ops->list_rate) + if (!debugfs_create_file("list_rates", + S_IRUGO, clk_dir, clock, &list_rates_fops)) + goto error; + + if (clock->vdd_class && !debugfs_create_file("fmax_rates", + S_IRUGO, clk_dir, clock, &fmax_rates_fops)) + goto error; + + if (!debugfs_create_file("parent", S_IRUGO, clk_dir, clock, + &clock_parent_fops)) + goto error; + + if (!debugfs_create_file("print", S_IRUGO, clk_dir, clock, + &clock_print_hw_fops)) + goto error; + + clock_measure_add(clock); + + return 0; +error: + debugfs_remove_recursive(clk_dir); + return -ENOMEM; +} +static DEFINE_MUTEX(clk_debug_lock); +static int clk_debug_init_once; + +/** + * clock_debug_init() - Initialize clock debugfs + * Lock clk_debug_lock before invoking this function. + */ +static int clock_debug_init(void) +{ + if (clk_debug_init_once) + return 0; + + clk_debug_init_once = 1; + + debugfs_base = debugfs_create_dir("clk", NULL); + if (!debugfs_base) + return -ENOMEM; + + if (!debugfs_create_u32("debug_suspend", S_IRUGO | S_IWUSR, + debugfs_base, &debug_suspend)) { + debugfs_remove_recursive(debugfs_base); + return -ENOMEM; + } + + if (!debugfs_create_file("enabled_clocks", S_IRUGO, debugfs_base, NULL, + &enabled_clocks_fops)) + return -ENOMEM; + + if (!debugfs_create_file("orphan_list", S_IRUGO, debugfs_base, NULL, + &orphan_list_fops)) + return -ENOMEM; + + if (!debugfs_create_file("trace_clocks", S_IRUGO, debugfs_base, NULL, + &trace_clocks_fops)) + return -ENOMEM; + + return 0; +} + +/** + * clock_debug_register() - Add additional clocks to clock debugfs hierarchy + * @list: List of clocks to create debugfs nodes for + */ +int clock_debug_register(struct clk *clk) +{ + int ret = 0; + struct clk *c; + + mutex_lock(&clk_list_lock); + if (!list_empty(&clk->list)) + goto out; + + ret = clock_debug_init(); + if (ret) + goto out; + + if (IS_ERR_OR_NULL(measure)) { + if (clk->flags & CLKFLAG_MEASURE) + measure = clk; + if (!IS_ERR_OR_NULL(measure)) { + list_for_each_entry(c, &clk_list, list) + clock_measure_add(c); + } + } + + list_add_tail(&clk->list, &clk_list); + clock_debug_add(clk); +out: + mutex_unlock(&clk_list_lock); + return ret; +} + +/* + * Print the names of enabled clocks and their parents if debug_suspend is set + */ +void clock_debug_print_enabled(void) +{ + if (likely(!debug_suspend)) + return; + + clock_debug_print_enabled_clocks(NULL); +} diff -Nruw linux-4.4.115-fbx/drivers/clk/msm./clock-dummy.c linux-4.4.115-fbx/drivers/clk/msm/clock-dummy.c --- linux-4.4.115-fbx/drivers/clk/msm./clock-dummy.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-4.4.115-fbx/drivers/clk/msm/clock-dummy.c 2019-10-29 09:26:23.473201514 +0100 @@ -0,0 +1,121 @@ +/* Copyright (c) 2011,2013-2014 The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include + +static int dummy_clk_reset(struct clk *clk, enum clk_reset_action action) +{ + return 0; +} + +static int dummy_clk_set_rate(struct clk *clk, unsigned long rate) +{ + clk->rate = rate; + return 0; +} + +static int dummy_clk_set_max_rate(struct clk *clk, unsigned long rate) +{ + return 0; +} + +static int dummy_clk_set_flags(struct clk *clk, unsigned flags) +{ + return 0; +} + +static unsigned long dummy_clk_get_rate(struct clk *clk) +{ + return clk->rate; +} + +static long dummy_clk_round_rate(struct clk *clk, unsigned long rate) +{ + return rate; +} + +struct clk_ops clk_ops_dummy = { + .reset = dummy_clk_reset, + .set_rate = dummy_clk_set_rate, + .set_max_rate = dummy_clk_set_max_rate, + .set_flags = dummy_clk_set_flags, + .get_rate = dummy_clk_get_rate, + .round_rate = dummy_clk_round_rate, +}; + +struct clk dummy_clk = { + .dbg_name = "dummy_clk", + .ops = &clk_ops_dummy, + CLK_INIT(dummy_clk), +}; + +static void *dummy_clk_dt_parser(struct device *dev, struct device_node *np) +{ + struct clk *c; + + c = devm_kzalloc(dev, sizeof(*c), GFP_KERNEL); + if (!c) { + dev_err(dev, "failed to map memory for %s\n", np->name); + return ERR_PTR(-ENOMEM); + } + c->ops = &clk_ops_dummy; + + return msmclk_generic_clk_init(dev, np, c); +} +MSMCLK_PARSER(dummy_clk_dt_parser, "qcom,dummy-clk", 0); + +static struct clk *of_dummy_get(struct of_phandle_args *clkspec, + void *data) +{ + u32 rate; + + if (!of_property_read_u32(clkspec->np, "clock-frequency", &rate)) + dummy_clk.rate = rate; + + return &dummy_clk; +} + +static struct of_device_id msm_clock_dummy_match_table[] = { + { .compatible = "qcom,dummycc" }, + { .compatible = "fixed-clock" }, + {} +}; + +static int msm_clock_dummy_probe(struct platform_device *pdev) +{ + int ret; + + ret = of_clk_add_provider(pdev->dev.of_node, of_dummy_get, NULL); + if (ret) + return -ENOMEM; + + dev_info(&pdev->dev, "Registered DUMMY provider.\n"); + return ret; +} + +static struct platform_driver msm_clock_dummy_driver = { + .probe = msm_clock_dummy_probe, + .driver = { + .name = "clock-dummy", + .of_match_table = msm_clock_dummy_match_table, + .owner = THIS_MODULE, + }, +}; + +int __init msm_dummy_clk_init(void) +{ + return platform_driver_register(&msm_clock_dummy_driver); +} +arch_initcall(msm_dummy_clk_init); diff -Nruw linux-4.4.115-fbx/drivers/clk/msm./clock-gcc-8998.c linux-4.4.115-fbx/drivers/clk/msm/clock-gcc-8998.c --- linux-4.4.115-fbx/drivers/clk/msm./clock-gcc-8998.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-4.4.115-fbx/drivers/clk/msm/clock-gcc-8998.c 2019-01-22 16:16:23.015241987 +0100 @@ -0,0 +1,2877 @@ +/* Copyright (c) 2015-2017, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +#include +#include + +#include "vdd-level-8998.h" +#include "reset.h" + +static void __iomem *virt_base; +static void __iomem *virt_dbgbase; + +#define cxo_clk_src_source_val 0 +#define cxo_clk_src_ao_source_val 0 +#define gpll0_out_main_source_val 1 +#define gpll0_ao_source_val 1 +#define gpll4_out_main_source_val 5 +#define gpll0_early_div_source_val 6 + +#define FIXDIV(div) (div ? (2 * (div) - 1) : (0)) + +#define F(f, s, div, m, n) \ + { \ + .freq_hz = (f), \ + .src_clk = &s.c, \ + .m_val = (m), \ + .n_val = ~((n)-(m)) * !!(n), \ + .d_val = ~(n),\ + .div_src_val = BVAL(4, 0, (int)FIXDIV(div)) \ + | BVAL(10, 8, s##_source_val), \ + } + +static DEFINE_VDD_REGULATORS(vdd_dig, VDD_DIG_NUM, 1, vdd_corner, NULL); +static DEFINE_VDD_REGULATORS(vdd_dig_ao, VDD_DIG_NUM, 1, vdd_corner, NULL); + +DEFINE_CLK_RPM_SMD_BRANCH(cxo_clk_src, cxo_clk_src_ao, RPM_MISC_CLK_TYPE, + CXO_CLK_SRC_ID, 19200000); +DEFINE_CLK_RPM_SMD(bimc_clk, bimc_a_clk, RPM_MEM_CLK_TYPE, BIMC_CLK_ID, NULL); +DEFINE_CLK_RPM_SMD(cnoc_clk, cnoc_a_clk, RPM_BUS_CLK_TYPE, CNOC_CLK_ID, NULL); +DEFINE_CLK_RPM_SMD(snoc_clk, snoc_a_clk, RPM_BUS_CLK_TYPE, SNOC_CLK_ID, NULL); +DEFINE_CLK_RPM_SMD(cnoc_periph_clk, cnoc_periph_a_clk, RPM_BUS_CLK_TYPE, + CNOC_PERIPH_CLK_ID, NULL); +static DEFINE_CLK_VOTER(cnoc_periph_keepalive_a_clk, &cnoc_periph_a_clk.c, + LONG_MAX); +static DEFINE_CLK_VOTER(bimc_msmbus_clk, &bimc_clk.c, LONG_MAX); +static DEFINE_CLK_VOTER(bimc_msmbus_a_clk, &bimc_a_clk.c, LONG_MAX); +static DEFINE_CLK_VOTER(cnoc_msmbus_clk, &cnoc_clk.c, LONG_MAX); +static DEFINE_CLK_VOTER(cnoc_msmbus_a_clk, &cnoc_a_clk.c, LONG_MAX); +static DEFINE_CLK_BRANCH_VOTER(cxo_dwc3_clk, &cxo_clk_src.c); +static DEFINE_CLK_BRANCH_VOTER(cxo_lpm_clk, &cxo_clk_src.c); +static DEFINE_CLK_BRANCH_VOTER(cxo_otg_clk, &cxo_clk_src.c); +static DEFINE_CLK_BRANCH_VOTER(cxo_pil_lpass_clk, &cxo_clk_src.c); +static DEFINE_CLK_BRANCH_VOTER(cxo_pil_ssc_clk, &cxo_clk_src.c); +static DEFINE_CLK_BRANCH_VOTER(cxo_pil_spss_clk, &cxo_clk_src.c); +DEFINE_CLK_RPM_SMD_XO_BUFFER(div_clk1, div_clk1_ao, DIV_CLK1_ID); +DEFINE_CLK_RPM_SMD_XO_BUFFER(div_clk2, div_clk2_ao, DIV_CLK2_ID); +DEFINE_CLK_RPM_SMD_XO_BUFFER(div_clk3, div_clk3_ao, DIV_CLK3_ID); +DEFINE_CLK_RPM_SMD(ipa_clk, ipa_a_clk, RPM_IPA_CLK_TYPE, + IPA_CLK_ID, NULL); +DEFINE_CLK_RPM_SMD(ce1_clk, ce1_a_clk, RPM_CE_CLK_TYPE, + CE1_CLK_ID, NULL); +DEFINE_CLK_RPM_SMD_XO_BUFFER(ln_bb_clk1, ln_bb_clk1_ao, LN_BB_CLK1_ID); +DEFINE_CLK_RPM_SMD_XO_BUFFER_PINCTRL(ln_bb_clk1_pin, ln_bb_clk1_pin_ao, + LN_BB_CLK1_PIN_ID); +DEFINE_CLK_RPM_SMD_XO_BUFFER(ln_bb_clk2, ln_bb_clk2_ao, LN_BB_CLK2_ID); +DEFINE_CLK_RPM_SMD_XO_BUFFER_PINCTRL(ln_bb_clk2_pin, ln_bb_clk2_pin_ao, + LN_BB_CLK2_PIN_ID); +DEFINE_CLK_RPM_SMD_XO_BUFFER(ln_bb_clk3, ln_bb_clk3_ao, LN_BB_CLK3_ID); +DEFINE_CLK_RPM_SMD_XO_BUFFER_PINCTRL(ln_bb_clk3_pin, ln_bb_clk3_pin_ao, + LN_BB_CLK3_PIN_ID); +static DEFINE_CLK_VOTER(mcd_ce1_clk, &ce1_clk.c, 85710000); +DEFINE_CLK_DUMMY(measure_only_bimc_hmss_axi_clk, 0); +DEFINE_CLK_RPM_SMD(mmssnoc_axi_clk, mmssnoc_axi_a_clk, + RPM_MMAXI_CLK_TYPE, MMSSNOC_AXI_CLK_ID, NULL); +DEFINE_CLK_RPM_SMD(aggre1_noc_clk, aggre1_noc_a_clk, RPM_AGGR_CLK_TYPE, + AGGR1_NOC_ID, NULL); +DEFINE_CLK_RPM_SMD(aggre2_noc_clk, aggre2_noc_a_clk, RPM_AGGR_CLK_TYPE, + AGGR2_NOC_ID, NULL); +static DEFINE_CLK_VOTER(qcedev_ce1_clk, &ce1_clk.c, 85710000); +static DEFINE_CLK_VOTER(qcrypto_ce1_clk, &ce1_clk.c, 85710000); +DEFINE_CLK_RPM_SMD_QDSS(qdss_clk, qdss_a_clk, RPM_MISC_CLK_TYPE, + QDSS_CLK_ID); +static DEFINE_CLK_VOTER(qseecom_ce1_clk, &ce1_clk.c, 85710000); +DEFINE_CLK_RPM_SMD_XO_BUFFER(rf_clk1, rf_clk1_ao, RF_CLK1_ID); +DEFINE_CLK_RPM_SMD_XO_BUFFER_PINCTRL(rf_clk1_pin, rf_clk1_pin_ao, + RF_CLK1_PIN_ID); +DEFINE_CLK_RPM_SMD_XO_BUFFER(rf_clk2, rf_clk2_ao, RF_CLK2_ID); +DEFINE_CLK_RPM_SMD_XO_BUFFER_PINCTRL(rf_clk2_pin, rf_clk2_pin_ao, + RF_CLK2_PIN_ID); +DEFINE_CLK_RPM_SMD_XO_BUFFER(rf_clk3, rf_clk3_ao, RF_CLK3_ID); +DEFINE_CLK_RPM_SMD_XO_BUFFER_PINCTRL(rf_clk3_pin, rf_clk3_pin_ao, + RF_CLK3_PIN_ID); +static DEFINE_CLK_VOTER(scm_ce1_clk, &ce1_clk.c, 85710000); +static DEFINE_CLK_VOTER(snoc_msmbus_clk, &snoc_clk.c, LONG_MAX); +static DEFINE_CLK_VOTER(snoc_msmbus_a_clk, &snoc_a_clk.c, LONG_MAX); +DEFINE_CLK_DUMMY(gcc_ce1_ahb_m_clk, 0); +DEFINE_CLK_DUMMY(gcc_ce1_axi_m_clk, 0); + +DEFINE_EXT_CLK(debug_mmss_clk, NULL); +DEFINE_EXT_CLK(gpu_gcc_debug_clk, NULL); +DEFINE_EXT_CLK(gfx_gcc_debug_clk, NULL); +DEFINE_EXT_CLK(debug_cpu_clk, NULL); + +static unsigned int soft_vote_gpll0; + +static struct pll_vote_clk gpll0 = { + .en_reg = (void __iomem *)GCC_APCS_GPLL_ENA_VOTE, + .en_mask = BIT(0), + .status_reg = (void __iomem *)GCC_GPLL0_MODE, + .status_mask = BIT(31), + .soft_vote = &soft_vote_gpll0, + .soft_vote_mask = PLL_SOFT_VOTE_PRIMARY, + .base = &virt_base, + .c = { + .rate = 600000000, + .parent = &cxo_clk_src.c, + .dbg_name = "gpll0", + .ops = &clk_ops_pll_acpu_vote, + CLK_INIT(gpll0.c), + }, +}; + +static struct pll_vote_clk gpll0_ao = { + .en_reg = (void __iomem *)GCC_APCS_GPLL_ENA_VOTE, + .en_mask = BIT(0), + .status_reg = (void __iomem *)GCC_GPLL0_MODE, + .status_mask = BIT(31), + .soft_vote = &soft_vote_gpll0, + .soft_vote_mask = PLL_SOFT_VOTE_ACPU, + .base = &virt_base, + .c = { + .rate = 600000000, + .parent = &cxo_clk_src_ao.c, + .dbg_name = "gpll0_ao", + .ops = &clk_ops_pll_acpu_vote, + CLK_INIT(gpll0_ao.c), + }, +}; + +DEFINE_EXT_CLK(gpll0_out_main, &gpll0.c); +DEFINE_EXT_CLK(gpll0_early_div, &gpll0.c); + +static struct local_vote_clk gcc_mmss_gpll0_clk = { + .cbcr_reg = GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1, + .vote_reg = GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1, + .en_mask = BIT(1), + .base = &virt_base, + .halt_check = DELAY, + .c = { + .dbg_name = "gcc_mmss_gpll0_clk", + .parent = &gpll0.c, + .ops = &clk_ops_vote, + CLK_INIT(gcc_mmss_gpll0_clk.c), + }, +}; + +static struct local_vote_clk gcc_mmss_gpll0_div_clk = { + .cbcr_reg = GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1, + .vote_reg = GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1, + .en_mask = BIT(0), + .base = &virt_base, + .halt_check = DELAY, + .c = { + .dbg_name = "gcc_mmss_gpll0_div_clk", + .parent = &gpll0.c, + .ops = &clk_ops_vote, + CLK_INIT(gcc_mmss_gpll0_div_clk.c), + }, +}; + +static struct local_vote_clk gcc_gpu_gpll0_clk = { + .cbcr_reg = GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1, + .vote_reg = GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1, + .en_mask = BIT(4), + .base = &virt_base, + .halt_check = DELAY, + .c = { + .dbg_name = "gcc_gpu_gpll0_clk", + .parent = &gpll0.c, + .ops = &clk_ops_vote, + CLK_INIT(gcc_gpu_gpll0_clk.c), + }, +}; + +static struct local_vote_clk gcc_gpu_gpll0_div_clk = { + .cbcr_reg = GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1, + .vote_reg = GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1, + .en_mask = BIT(3), + .base = &virt_base, + .halt_check = DELAY, + .c = { + .dbg_name = "gcc_gpu_gpll0_div_clk", + .parent = &gpll0.c, + .ops = &clk_ops_vote, + CLK_INIT(gcc_gpu_gpll0_div_clk.c), + }, +}; + +static struct pll_vote_clk gpll4 = { + .en_reg = (void __iomem *)GCC_APCS_GPLL_ENA_VOTE, + .en_mask = BIT(4), + .status_reg = (void __iomem *)GCC_GPLL4_MODE, + .status_mask = BIT(31), + .base = &virt_base, + .c = { + .rate = 384000000, + .parent = &cxo_clk_src.c, + .dbg_name = "gpll4", + .ops = &clk_ops_pll_vote, + VDD_DIG_FMAX_MAP3(LOWER, 400000000, LOW, 800000000, + NOMINAL, 1600000000), + CLK_INIT(gpll4.c), + }, +}; +DEFINE_EXT_CLK(gpll4_out_main, &gpll4.c); + +static struct clk_freq_tbl ftbl_usb30_master_clk_src[] = { + F( 19200000, cxo_clk_src, 1, 0, 0), + F( 60000000, gpll0_out_main, 10, 0, 0), + F( 120000000, gpll0_out_main, 5, 0, 0), + F( 150000000, gpll0_out_main, 4, 0, 0), + F_END +}; + +static struct rcg_clk usb30_master_clk_src = { + .cmd_rcgr_reg = GCC_USB30_MASTER_CMD_RCGR, + .set_rate = set_rate_mnd, + .freq_tbl = ftbl_usb30_master_clk_src, + .current_freq = &rcg_dummy_freq, + .base = &virt_base, + .c = { + .dbg_name = "usb30_master_clk_src", + .ops = &clk_ops_rcg_mnd, + VDD_DIG_FMAX_MAP4(LOWER, 66670000, LOW, 133330000, + NOMINAL, 200000000, HIGH, 240000000), + CLK_INIT(usb30_master_clk_src.c), + }, +}; + +static struct clk_freq_tbl ftbl_pcie_aux_clk_src[] = { + F( 19200000, cxo_clk_src, 1, 0, 0), + F_END +}; + +static struct rcg_clk pcie_aux_clk_src = { + .cmd_rcgr_reg = GCC_PCIE_AUX_CMD_RCGR, + .set_rate = set_rate_mnd, + .freq_tbl = ftbl_pcie_aux_clk_src, + .current_freq = &rcg_dummy_freq, + .base = &virt_base, + .c = { + .dbg_name = "pcie_aux_clk_src", + .ops = &clk_ops_rcg_mnd, + VDD_DIG_FMAX_MAP2(LOWER, 9600000, LOW, 19200000), + CLK_INIT(pcie_aux_clk_src.c), + }, +}; + +static struct clk_freq_tbl ftbl_ufs_axi_clk_src[] = { + F( 50000000, gpll0_out_main, 12, 0, 0), + F( 100000000, gpll0_out_main, 6, 0, 0), + F( 200000000, gpll0_out_main, 3, 0, 0), + F( 240000000, gpll0_out_main, 2.5, 0, 0), + F_END +}; + +static struct rcg_clk ufs_axi_clk_src = { + .cmd_rcgr_reg = GCC_UFS_AXI_CMD_RCGR, + .set_rate = set_rate_mnd, + .freq_tbl = ftbl_ufs_axi_clk_src, + .current_freq = &rcg_dummy_freq, + .base = &virt_base, + .c = { + .dbg_name = "ufs_axi_clk_src", + .ops = &clk_ops_rcg_mnd, + VDD_DIG_FMAX_MAP4(LOWER, 50000000, LOW, 100000000, + NOMINAL, 200000000, HIGH, 240000000), + CLK_INIT(ufs_axi_clk_src.c), + }, +}; + +static struct clk_freq_tbl ftbl_blsp_i2c_apps_clk_src[] = { + F( 19200000, cxo_clk_src, 1, 0, 0), + F( 50000000, gpll0_out_main, 12, 0, 0), + F_END +}; + +static struct rcg_clk blsp1_qup1_i2c_apps_clk_src = { + .cmd_rcgr_reg = GCC_BLSP1_QUP1_I2C_APPS_CMD_RCGR, + .set_rate = set_rate_hid, + .freq_tbl = ftbl_blsp_i2c_apps_clk_src, + .current_freq = &rcg_dummy_freq, + .base = &virt_base, + .c = { + .dbg_name = "blsp1_qup1_i2c_apps_clk_src", + .ops = &clk_ops_rcg, + VDD_DIG_FMAX_MAP2(LOWER, 19200000, LOW, 50000000), + CLK_INIT(blsp1_qup1_i2c_apps_clk_src.c), + }, +}; + +static struct clk_freq_tbl ftbl_blsp_qup_spi_apps_clk_src[] = { + F( 960000, cxo_clk_src, 10, 1, 2), + F( 4800000, cxo_clk_src, 4, 0, 0), + F( 9600000, cxo_clk_src, 2, 0, 0), + F( 15000000, gpll0_early_div, 5, 1, 4), + F( 19200000, cxo_clk_src, 1, 0, 0), + F( 25000000, gpll0_out_main, 12, 1, 2), + F( 50000000, gpll0_out_main, 12, 0, 0), + F_END +}; + +static struct rcg_clk blsp1_qup1_spi_apps_clk_src = { + .cmd_rcgr_reg = GCC_BLSP1_QUP1_SPI_APPS_CMD_RCGR, + .set_rate = set_rate_mnd, + .freq_tbl = ftbl_blsp_qup_spi_apps_clk_src, + .current_freq = &rcg_dummy_freq, + .base = &virt_base, + .c = { + .dbg_name = "blsp1_qup1_spi_apps_clk_src", + .ops = &clk_ops_rcg_mnd, + VDD_DIG_FMAX_MAP3(LOWER, 19200000, LOW, 25000000, + NOMINAL, 50000000), + CLK_INIT(blsp1_qup1_spi_apps_clk_src.c), + }, +}; + +static struct rcg_clk blsp1_qup2_i2c_apps_clk_src = { + .cmd_rcgr_reg = GCC_BLSP1_QUP2_I2C_APPS_CMD_RCGR, + .set_rate = set_rate_hid, + .freq_tbl = ftbl_blsp_i2c_apps_clk_src, + .current_freq = &rcg_dummy_freq, + .base = &virt_base, + .c = { + .dbg_name = "blsp1_qup2_i2c_apps_clk_src", + .ops = &clk_ops_rcg, + VDD_DIG_FMAX_MAP2(LOWER, 19200000, LOW, 50000000), + CLK_INIT(blsp1_qup2_i2c_apps_clk_src.c), + }, +}; + +static struct rcg_clk blsp1_qup2_spi_apps_clk_src = { + .cmd_rcgr_reg = GCC_BLSP1_QUP2_SPI_APPS_CMD_RCGR, + .set_rate = set_rate_mnd, + .freq_tbl = ftbl_blsp_qup_spi_apps_clk_src, + .current_freq = &rcg_dummy_freq, + .base = &virt_base, + .c = { + .dbg_name = "blsp1_qup2_spi_apps_clk_src", + .ops = &clk_ops_rcg_mnd, + VDD_DIG_FMAX_MAP3(LOWER, 19200000, LOW, 25000000, + NOMINAL, 50000000), + CLK_INIT(blsp1_qup2_spi_apps_clk_src.c), + }, +}; + +static struct rcg_clk blsp1_qup3_i2c_apps_clk_src = { + .cmd_rcgr_reg = GCC_BLSP1_QUP3_I2C_APPS_CMD_RCGR, + .set_rate = set_rate_hid, + .freq_tbl = ftbl_blsp_i2c_apps_clk_src, + .current_freq = &rcg_dummy_freq, + .base = &virt_base, + .c = { + .dbg_name = "blsp1_qup3_i2c_apps_clk_src", + .ops = &clk_ops_rcg, + VDD_DIG_FMAX_MAP2(LOWER, 19200000, LOW, 50000000), + CLK_INIT(blsp1_qup3_i2c_apps_clk_src.c), + }, +}; + +static struct rcg_clk blsp1_qup3_spi_apps_clk_src = { + .cmd_rcgr_reg = GCC_BLSP1_QUP3_SPI_APPS_CMD_RCGR, + .set_rate = set_rate_mnd, + .freq_tbl = ftbl_blsp_qup_spi_apps_clk_src, + .current_freq = &rcg_dummy_freq, + .base = &virt_base, + .c = { + .dbg_name = "blsp1_qup3_spi_apps_clk_src", + .ops = &clk_ops_rcg_mnd, + VDD_DIG_FMAX_MAP3(LOWER, 19200000, LOW, 25000000, + NOMINAL, 50000000), + CLK_INIT(blsp1_qup3_spi_apps_clk_src.c), + }, +}; + +static struct rcg_clk blsp1_qup4_i2c_apps_clk_src = { + .cmd_rcgr_reg = GCC_BLSP1_QUP4_I2C_APPS_CMD_RCGR, + .set_rate = set_rate_hid, + .freq_tbl = ftbl_blsp_i2c_apps_clk_src, + .current_freq = &rcg_dummy_freq, + .base = &virt_base, + .c = { + .dbg_name = "blsp1_qup4_i2c_apps_clk_src", + .ops = &clk_ops_rcg, + VDD_DIG_FMAX_MAP2(LOWER, 19200000, LOW, 50000000), + CLK_INIT(blsp1_qup4_i2c_apps_clk_src.c), + }, +}; + +static struct rcg_clk blsp1_qup4_spi_apps_clk_src = { + .cmd_rcgr_reg = GCC_BLSP1_QUP4_SPI_APPS_CMD_RCGR, + .set_rate = set_rate_mnd, + .freq_tbl = ftbl_blsp_qup_spi_apps_clk_src, + .current_freq = &rcg_dummy_freq, + .base = &virt_base, + .c = { + .dbg_name = "blsp1_qup4_spi_apps_clk_src", + .ops = &clk_ops_rcg_mnd, + VDD_DIG_FMAX_MAP3(LOWER, 19200000, LOW, 25000000, + NOMINAL, 50000000), + CLK_INIT(blsp1_qup4_spi_apps_clk_src.c), + }, +}; + +static struct rcg_clk blsp1_qup5_i2c_apps_clk_src = { + .cmd_rcgr_reg = GCC_BLSP1_QUP5_I2C_APPS_CMD_RCGR, + .set_rate = set_rate_hid, + .freq_tbl = ftbl_blsp_i2c_apps_clk_src, + .current_freq = &rcg_dummy_freq, + .base = &virt_base, + .c = { + .dbg_name = "blsp1_qup5_i2c_apps_clk_src", + .ops = &clk_ops_rcg, + VDD_DIG_FMAX_MAP2(LOWER, 19200000, LOW, 50000000), + CLK_INIT(blsp1_qup5_i2c_apps_clk_src.c), + }, +}; + +static struct rcg_clk blsp1_qup5_spi_apps_clk_src = { + .cmd_rcgr_reg = GCC_BLSP1_QUP5_SPI_APPS_CMD_RCGR, + .set_rate = set_rate_mnd, + .freq_tbl = ftbl_blsp_qup_spi_apps_clk_src, + .current_freq = &rcg_dummy_freq, + .base = &virt_base, + .c = { + .dbg_name = "blsp1_qup5_spi_apps_clk_src", + .ops = &clk_ops_rcg_mnd, + VDD_DIG_FMAX_MAP3(LOWER, 19200000, LOW, 25000000, + NOMINAL, 50000000), + CLK_INIT(blsp1_qup5_spi_apps_clk_src.c), + }, +}; + +static struct rcg_clk blsp1_qup6_i2c_apps_clk_src = { + .cmd_rcgr_reg = GCC_BLSP1_QUP6_I2C_APPS_CMD_RCGR, + .set_rate = set_rate_hid, + .freq_tbl = ftbl_blsp_i2c_apps_clk_src, + .current_freq = &rcg_dummy_freq, + .base = &virt_base, + .c = { + .dbg_name = "blsp1_qup6_i2c_apps_clk_src", + .ops = &clk_ops_rcg, + VDD_DIG_FMAX_MAP2(LOWER, 19200000, LOW, 50000000), + CLK_INIT(blsp1_qup6_i2c_apps_clk_src.c), + }, +}; + +static struct rcg_clk blsp1_qup6_spi_apps_clk_src = { + .cmd_rcgr_reg = GCC_BLSP1_QUP6_SPI_APPS_CMD_RCGR, + .set_rate = set_rate_mnd, + .freq_tbl = ftbl_blsp_qup_spi_apps_clk_src, + .current_freq = &rcg_dummy_freq, + .base = &virt_base, + .c = { + .dbg_name = "blsp1_qup6_spi_apps_clk_src", + .ops = &clk_ops_rcg_mnd, + VDD_DIG_FMAX_MAP3(LOWER, 19200000, LOW, 25000000, + NOMINAL, 50000000), + CLK_INIT(blsp1_qup6_spi_apps_clk_src.c), + }, +}; + +static struct clk_freq_tbl ftbl_blsp_uart_apps_clk_src[] = { + F( 3686400, gpll0_early_div, 1, 192, 15625), + F( 7372800, gpll0_early_div, 1, 384, 15625), + F( 14745600, gpll0_early_div, 1, 768, 15625), + F( 16000000, gpll0_early_div, 1, 4, 75), + F( 19200000, cxo_clk_src, 1, 0, 0), + F( 24000000, gpll0_out_main, 5, 1, 5), + F( 32000000, gpll0_out_main, 1, 4, 75), + F( 40000000, gpll0_out_main, 15, 0, 0), + F( 46400000, gpll0_out_main, 1, 29, 375), + F( 48000000, gpll0_out_main, 12.5, 0, 0), + F( 51200000, gpll0_out_main, 1, 32, 375), + F( 56000000, gpll0_out_main, 1, 7, 75), + F( 58982400, gpll0_out_main, 1, 1536, 15625), + F( 60000000, gpll0_out_main, 10, 0, 0), + F( 63157895, gpll0_out_main, 9.5, 0, 0), + F_END +}; + +static struct rcg_clk blsp1_uart1_apps_clk_src = { + .cmd_rcgr_reg = GCC_BLSP1_UART1_APPS_CMD_RCGR, + .set_rate = set_rate_mnd, + .freq_tbl = ftbl_blsp_uart_apps_clk_src, + .current_freq = &rcg_dummy_freq, + .base = &virt_base, + .c = { + .dbg_name = "blsp1_uart1_apps_clk_src", + .ops = &clk_ops_rcg_mnd, + VDD_DIG_FMAX_MAP3(LOWER, 19200000, LOW, 31580000, + NOMINAL, 63160000), + CLK_INIT(blsp1_uart1_apps_clk_src.c), + }, +}; + +static struct rcg_clk blsp1_uart2_apps_clk_src = { + .cmd_rcgr_reg = GCC_BLSP1_UART2_APPS_CMD_RCGR, + .set_rate = set_rate_mnd, + .freq_tbl = ftbl_blsp_uart_apps_clk_src, + .current_freq = &rcg_dummy_freq, + .base = &virt_base, + .c = { + .dbg_name = "blsp1_uart2_apps_clk_src", + .ops = &clk_ops_rcg_mnd, + VDD_DIG_FMAX_MAP3(LOWER, 19200000, LOW, 31580000, + NOMINAL, 63160000), + CLK_INIT(blsp1_uart2_apps_clk_src.c), + }, +}; + +static struct rcg_clk blsp1_uart3_apps_clk_src = { + .cmd_rcgr_reg = GCC_BLSP1_UART3_APPS_CMD_RCGR, + .set_rate = set_rate_mnd, + .freq_tbl = ftbl_blsp_uart_apps_clk_src, + .current_freq = &rcg_dummy_freq, + .base = &virt_base, + .c = { + .dbg_name = "blsp1_uart3_apps_clk_src", + .ops = &clk_ops_rcg_mnd, + VDD_DIG_FMAX_MAP3(LOWER, 19200000, LOW, 31580000, + NOMINAL, 63160000), + CLK_INIT(blsp1_uart3_apps_clk_src.c), + }, +}; + +static struct rcg_clk blsp2_qup1_i2c_apps_clk_src = { + .cmd_rcgr_reg = GCC_BLSP2_QUP1_I2C_APPS_CMD_RCGR, + .set_rate = set_rate_hid, + .freq_tbl = ftbl_blsp_i2c_apps_clk_src, + .current_freq = &rcg_dummy_freq, + .base = &virt_base, + .c = { + .dbg_name = "blsp2_qup1_i2c_apps_clk_src", + .ops = &clk_ops_rcg, + VDD_DIG_FMAX_MAP2(LOWER, 19200000, LOW, 50000000), + CLK_INIT(blsp2_qup1_i2c_apps_clk_src.c), + }, +}; + +static struct rcg_clk blsp2_qup1_spi_apps_clk_src = { + .cmd_rcgr_reg = GCC_BLSP2_QUP1_SPI_APPS_CMD_RCGR, + .set_rate = set_rate_mnd, + .freq_tbl = ftbl_blsp_qup_spi_apps_clk_src, + .current_freq = &rcg_dummy_freq, + .base = &virt_base, + .c = { + .dbg_name = "blsp2_qup1_spi_apps_clk_src", + .ops = &clk_ops_rcg_mnd, + VDD_DIG_FMAX_MAP3(LOWER, 19200000, LOW, 25000000, + NOMINAL, 50000000), + CLK_INIT(blsp2_qup1_spi_apps_clk_src.c), + }, +}; + +static struct rcg_clk blsp2_qup2_i2c_apps_clk_src = { + .cmd_rcgr_reg = GCC_BLSP2_QUP2_I2C_APPS_CMD_RCGR, + .set_rate = set_rate_hid, + .freq_tbl = ftbl_blsp_i2c_apps_clk_src, + .current_freq = &rcg_dummy_freq, + .base = &virt_base, + .c = { + .dbg_name = "blsp2_qup2_i2c_apps_clk_src", + .ops = &clk_ops_rcg, + VDD_DIG_FMAX_MAP2(LOWER, 19200000, LOW, 50000000), + CLK_INIT(blsp2_qup2_i2c_apps_clk_src.c), + }, +}; + +static struct rcg_clk blsp2_qup2_spi_apps_clk_src = { + .cmd_rcgr_reg = GCC_BLSP2_QUP2_SPI_APPS_CMD_RCGR, + .set_rate = set_rate_mnd, + .freq_tbl = ftbl_blsp_qup_spi_apps_clk_src, + .current_freq = &rcg_dummy_freq, + .base = &virt_base, + .c = { + .dbg_name = "blsp2_qup2_spi_apps_clk_src", + .ops = &clk_ops_rcg_mnd, + VDD_DIG_FMAX_MAP3(LOWER, 19200000, LOW, 25000000, + NOMINAL, 50000000), + CLK_INIT(blsp2_qup2_spi_apps_clk_src.c), + }, +}; + +static struct rcg_clk blsp2_qup3_i2c_apps_clk_src = { + .cmd_rcgr_reg = GCC_BLSP2_QUP3_I2C_APPS_CMD_RCGR, + .set_rate = set_rate_hid, + .freq_tbl = ftbl_blsp_i2c_apps_clk_src, + .current_freq = &rcg_dummy_freq, + .base = &virt_base, + .c = { + .dbg_name = "blsp2_qup3_i2c_apps_clk_src", + .ops = &clk_ops_rcg, + VDD_DIG_FMAX_MAP2(LOWER, 19200000, LOW, 50000000), + CLK_INIT(blsp2_qup3_i2c_apps_clk_src.c), + }, +}; + +static struct rcg_clk blsp2_qup3_spi_apps_clk_src = { + .cmd_rcgr_reg = GCC_BLSP2_QUP3_SPI_APPS_CMD_RCGR, + .set_rate = set_rate_mnd, + .freq_tbl = ftbl_blsp_qup_spi_apps_clk_src, + .current_freq = &rcg_dummy_freq, + .base = &virt_base, + .c = { + .dbg_name = "blsp2_qup3_spi_apps_clk_src", + .ops = &clk_ops_rcg_mnd, + VDD_DIG_FMAX_MAP3(LOWER, 19200000, LOW, 25000000, + NOMINAL, 50000000), + CLK_INIT(blsp2_qup3_spi_apps_clk_src.c), + }, +}; + +static struct rcg_clk blsp2_qup4_i2c_apps_clk_src = { + .cmd_rcgr_reg = GCC_BLSP2_QUP4_I2C_APPS_CMD_RCGR, + .set_rate = set_rate_hid, + .freq_tbl = ftbl_blsp_i2c_apps_clk_src, + .current_freq = &rcg_dummy_freq, + .base = &virt_base, + .c = { + .dbg_name = "blsp2_qup4_i2c_apps_clk_src", + .ops = &clk_ops_rcg, + VDD_DIG_FMAX_MAP2(LOWER, 19200000, LOW, 50000000), + CLK_INIT(blsp2_qup4_i2c_apps_clk_src.c), + }, +}; + +static struct rcg_clk blsp2_qup4_spi_apps_clk_src = { + .cmd_rcgr_reg = GCC_BLSP2_QUP4_SPI_APPS_CMD_RCGR, + .set_rate = set_rate_mnd, + .freq_tbl = ftbl_blsp_qup_spi_apps_clk_src, + .current_freq = &rcg_dummy_freq, + .base = &virt_base, + .c = { + .dbg_name = "blsp2_qup4_spi_apps_clk_src", + .ops = &clk_ops_rcg_mnd, + VDD_DIG_FMAX_MAP3(LOWER, 19200000, LOW, 25000000, + NOMINAL, 50000000), + CLK_INIT(blsp2_qup4_spi_apps_clk_src.c), + }, +}; + +static struct rcg_clk blsp2_qup5_i2c_apps_clk_src = { + .cmd_rcgr_reg = GCC_BLSP2_QUP5_I2C_APPS_CMD_RCGR, + .set_rate = set_rate_hid, + .freq_tbl = ftbl_blsp_i2c_apps_clk_src, + .current_freq = &rcg_dummy_freq, + .base = &virt_base, + .c = { + .dbg_name = "blsp2_qup5_i2c_apps_clk_src", + .ops = &clk_ops_rcg, + VDD_DIG_FMAX_MAP2(LOWER, 19200000, LOW, 50000000), + CLK_INIT(blsp2_qup5_i2c_apps_clk_src.c), + }, +}; + +static struct rcg_clk blsp2_qup5_spi_apps_clk_src = { + .cmd_rcgr_reg = GCC_BLSP2_QUP5_SPI_APPS_CMD_RCGR, + .set_rate = set_rate_mnd, + .freq_tbl = ftbl_blsp_qup_spi_apps_clk_src, + .current_freq = &rcg_dummy_freq, + .base = &virt_base, + .c = { + .dbg_name = "blsp2_qup5_spi_apps_clk_src", + .ops = &clk_ops_rcg_mnd, + VDD_DIG_FMAX_MAP3(LOWER, 19200000, LOW, 25000000, + NOMINAL, 50000000), + CLK_INIT(blsp2_qup5_spi_apps_clk_src.c), + }, +}; + +static struct rcg_clk blsp2_qup6_i2c_apps_clk_src = { + .cmd_rcgr_reg = GCC_BLSP2_QUP6_I2C_APPS_CMD_RCGR, + .set_rate = set_rate_hid, + .freq_tbl = ftbl_blsp_i2c_apps_clk_src, + .current_freq = &rcg_dummy_freq, + .base = &virt_base, + .c = { + .dbg_name = "blsp2_qup6_i2c_apps_clk_src", + .ops = &clk_ops_rcg, + VDD_DIG_FMAX_MAP2(LOWER, 19200000, LOW, 50000000), + CLK_INIT(blsp2_qup6_i2c_apps_clk_src.c), + }, +}; + +static struct rcg_clk blsp2_qup6_spi_apps_clk_src = { + .cmd_rcgr_reg = GCC_BLSP2_QUP6_SPI_APPS_CMD_RCGR, + .set_rate = set_rate_mnd, + .freq_tbl = ftbl_blsp_qup_spi_apps_clk_src, + .current_freq = &rcg_dummy_freq, + .base = &virt_base, + .c = { + .dbg_name = "blsp2_qup6_spi_apps_clk_src", + .ops = &clk_ops_rcg_mnd, + VDD_DIG_FMAX_MAP3(LOWER, 19200000, LOW, 25000000, + NOMINAL, 50000000), + CLK_INIT(blsp2_qup6_spi_apps_clk_src.c), + }, +}; + +static struct rcg_clk blsp2_uart1_apps_clk_src = { + .cmd_rcgr_reg = GCC_BLSP2_UART1_APPS_CMD_RCGR, + .set_rate = set_rate_mnd, + .freq_tbl = ftbl_blsp_uart_apps_clk_src, + .current_freq = &rcg_dummy_freq, + .base = &virt_base, + .c = { + .dbg_name = "blsp2_uart1_apps_clk_src", + .ops = &clk_ops_rcg_mnd, + VDD_DIG_FMAX_MAP3(LOWER, 19200000, LOW, 31580000, + NOMINAL, 63160000), + CLK_INIT(blsp2_uart1_apps_clk_src.c), + }, +}; + +static struct rcg_clk blsp2_uart2_apps_clk_src = { + .cmd_rcgr_reg = GCC_BLSP2_UART2_APPS_CMD_RCGR, + .set_rate = set_rate_mnd, + .freq_tbl = ftbl_blsp_uart_apps_clk_src, + .current_freq = &rcg_dummy_freq, + .base = &virt_base, + .c = { + .dbg_name = "blsp2_uart2_apps_clk_src", + .ops = &clk_ops_rcg_mnd, + VDD_DIG_FMAX_MAP3(LOWER, 19200000, LOW, 31580000, + NOMINAL, 63160000), + CLK_INIT(blsp2_uart2_apps_clk_src.c), + }, +}; + +static struct rcg_clk blsp2_uart3_apps_clk_src = { + .cmd_rcgr_reg = GCC_BLSP2_UART3_APPS_CMD_RCGR, + .set_rate = set_rate_mnd, + .freq_tbl = ftbl_blsp_uart_apps_clk_src, + .current_freq = &rcg_dummy_freq, + .base = &virt_base, + .c = { + .dbg_name = "blsp2_uart3_apps_clk_src", + .ops = &clk_ops_rcg_mnd, + VDD_DIG_FMAX_MAP3(LOWER, 19200000, LOW, 31580000, + NOMINAL, 63160000), + CLK_INIT(blsp2_uart3_apps_clk_src.c), + }, +}; + +static struct clk_freq_tbl ftbl_gp_clk_src[] = { + F( 19200000, cxo_clk_src, 1, 0, 0), + F( 100000000, gpll0_out_main, 6, 0, 0), + F( 200000000, gpll0_out_main, 3, 0, 0), + F_END +}; + +static struct rcg_clk gp1_clk_src = { + .cmd_rcgr_reg = GCC_GP1_CMD_RCGR, + .set_rate = set_rate_mnd, + .freq_tbl = ftbl_gp_clk_src, + .current_freq = &rcg_dummy_freq, + .base = &virt_base, + .c = { + .dbg_name = "gp1_clk_src", + .ops = &clk_ops_rcg_mnd, + VDD_DIG_FMAX_MAP3(LOWER, 50000000, LOW, 100000000, + NOMINAL, 200000000), + CLK_INIT(gp1_clk_src.c), + }, +}; + +static struct rcg_clk gp2_clk_src = { + .cmd_rcgr_reg = GCC_GP2_CMD_RCGR, + .set_rate = set_rate_mnd, + .freq_tbl = ftbl_gp_clk_src, + .current_freq = &rcg_dummy_freq, + .base = &virt_base, + .c = { + .dbg_name = "gp2_clk_src", + .ops = &clk_ops_rcg_mnd, + VDD_DIG_FMAX_MAP3(LOWER, 50000000, LOW, 100000000, + NOMINAL, 200000000), + CLK_INIT(gp2_clk_src.c), + }, +}; + +static struct rcg_clk gp3_clk_src = { + .cmd_rcgr_reg = GCC_GP3_CMD_RCGR, + .set_rate = set_rate_mnd, + .freq_tbl = ftbl_gp_clk_src, + .current_freq = &rcg_dummy_freq, + .base = &virt_base, + .c = { + .dbg_name = "gp3_clk_src", + .ops = &clk_ops_rcg_mnd, + VDD_DIG_FMAX_MAP3(LOWER, 50000000, LOW, 100000000, + NOMINAL, 200000000), + CLK_INIT(gp3_clk_src.c), + }, +}; + +static struct clk_freq_tbl ftbl_hmss_rbcpr_clk_src[] = { + F( 19200000, cxo_clk_src_ao, 1, 0, 0), + F_END +}; + +static struct rcg_clk hmss_rbcpr_clk_src = { + .cmd_rcgr_reg = GCC_HMSS_RBCPR_CMD_RCGR, + .set_rate = set_rate_hid, + .freq_tbl = ftbl_hmss_rbcpr_clk_src, + .current_freq = &rcg_dummy_freq, + .base = &virt_base, + .c = { + .dbg_name = "hmss_rbcpr_clk_src", + .ops = &clk_ops_rcg, + CLK_INIT(hmss_rbcpr_clk_src.c), + }, +}; + +static struct clk_freq_tbl ftbl_pdm2_clk_src[] = { + F( 60000000, gpll0_out_main, 10, 0, 0), + F_END +}; + +static struct rcg_clk pdm2_clk_src = { + .cmd_rcgr_reg = GCC_PDM2_CMD_RCGR, + .set_rate = set_rate_hid, + .freq_tbl = ftbl_pdm2_clk_src, + .current_freq = &rcg_dummy_freq, + .base = &virt_base, + .c = { + .dbg_name = "pdm2_clk_src", + .ops = &clk_ops_rcg, + VDD_DIG_FMAX_MAP2(LOWER, 19200000, LOW, 60000000), + CLK_INIT(pdm2_clk_src.c), + }, +}; + +static struct clk_freq_tbl ftbl_sdcc2_apps_clk_src[] = { + F( 144000, cxo_clk_src, 16, 3, 25), + F( 400000, cxo_clk_src, 12, 1, 4), + F( 20000000, gpll0_out_main, 15, 1, 2), + F( 25000000, gpll0_out_main, 12, 1, 2), + F( 50000000, gpll0_out_main, 12, 0, 0), + F( 100000000, gpll0_out_main, 6, 0, 0), + F( 200000000, gpll0_out_main, 3, 0, 0), + F_END +}; + +static struct rcg_clk sdcc2_apps_clk_src = { + .cmd_rcgr_reg = GCC_SDCC2_APPS_CMD_RCGR, + .set_rate = set_rate_mnd, + .freq_tbl = ftbl_sdcc2_apps_clk_src, + .current_freq = &rcg_dummy_freq, + .base = &virt_base, + .c = { + .dbg_name = "sdcc2_apps_clk_src", + .ops = &clk_ops_rcg_mnd, + VDD_DIG_FMAX_MAP3(LOWER, 19200000, LOW, 100000000, + NOMINAL, 200000000), + CLK_INIT(sdcc2_apps_clk_src.c), + }, +}; + +static struct clk_freq_tbl ftbl_sdcc4_apps_clk_src[] = { + F( 144000, cxo_clk_src, 16, 3, 25), + F( 400000, cxo_clk_src, 12, 1, 4), + F( 20000000, gpll0_out_main, 15, 1, 2), + F( 25000000, gpll0_out_main, 12, 1, 2), + F( 50000000, gpll0_out_main, 12, 0, 0), + F( 100000000, gpll0_out_main, 6, 0, 0), + F_END +}; + +static struct rcg_clk sdcc4_apps_clk_src = { + .cmd_rcgr_reg = GCC_SDCC4_APPS_CMD_RCGR, + .set_rate = set_rate_mnd, + .freq_tbl = ftbl_sdcc4_apps_clk_src, + .current_freq = &rcg_dummy_freq, + .base = &virt_base, + .c = { + .dbg_name = "sdcc4_apps_clk_src", + .ops = &clk_ops_rcg_mnd, + VDD_DIG_FMAX_MAP3(LOWER, 19200000, LOW, 50000000, + NOMINAL, 100000000), + CLK_INIT(sdcc4_apps_clk_src.c), + }, +}; + +static struct clk_freq_tbl ftbl_tsif_ref_clk_src[] = { + F( 105495, cxo_clk_src, 1, 1, 182), + F_END +}; + +static struct rcg_clk tsif_ref_clk_src = { + .cmd_rcgr_reg = GCC_TSIF_REF_CMD_RCGR, + .set_rate = set_rate_mnd, + .freq_tbl = ftbl_tsif_ref_clk_src, + .current_freq = &rcg_dummy_freq, + .base = &virt_base, + .c = { + .dbg_name = "tsif_ref_clk_src", + .ops = &clk_ops_rcg_mnd, + VDD_DIG_FMAX_MAP1(LOWER, 105500), + CLK_INIT(tsif_ref_clk_src.c), + }, +}; + +static struct clk_freq_tbl ftbl_ufs_ice_core_clk_src[] = { + F( 75000000, gpll0_out_main, 8, 0, 0), + F( 150000000, gpll0_out_main, 4, 0, 0), + F( 300000000, gpll0_out_main, 2, 0, 0), + F_END +}; + +static struct rcg_clk ufs_ice_core_clk_src = { + .cmd_rcgr_reg = GCC_UFS_ICE_CORE_CMD_RCGR, + .set_rate = set_rate_hid, + .freq_tbl = ftbl_ufs_ice_core_clk_src, + .current_freq = &rcg_dummy_freq, + .base = &virt_base, + .c = { + .dbg_name = "ufs_ice_core_clk_src", + .ops = &clk_ops_rcg, + VDD_DIG_FMAX_MAP3(LOWER, 75000000, LOW, 150000000, + NOMINAL, 300000000), + CLK_INIT(ufs_ice_core_clk_src.c), + }, +}; + +static struct clk_freq_tbl ftbl_ufs_phy_aux_clk_src[] = { + F( 19200000, cxo_clk_src, 1, 0, 0), + F_END +}; + +static struct rcg_clk ufs_phy_aux_clk_src = { + .cmd_rcgr_reg = GCC_UFS_PHY_AUX_CMD_RCGR, + .set_rate = set_rate_hid, + .freq_tbl = ftbl_ufs_phy_aux_clk_src, + .current_freq = &rcg_dummy_freq, + .base = &virt_base, + .c = { + .dbg_name = "ufs_phy_aux_clk_src", + .ops = &clk_ops_rcg, + VDD_DIG_FMAX_MAP1(LOWER, 19200000), + CLK_INIT(ufs_phy_aux_clk_src.c), + }, +}; + +static struct clk_freq_tbl ftbl_ufs_unipro_core_clk_src[] = { + F( 37500000, gpll0_out_main, 16, 0, 0), + F( 75000000, gpll0_out_main, 8, 0, 0), + F( 150000000, gpll0_out_main, 4, 0, 0), + F_END +}; + +static struct rcg_clk ufs_unipro_core_clk_src = { + .cmd_rcgr_reg = GCC_UFS_UNIPRO_CORE_CMD_RCGR, + .set_rate = set_rate_hid, + .freq_tbl = ftbl_ufs_unipro_core_clk_src, + .current_freq = &rcg_dummy_freq, + .base = &virt_base, + .c = { + .dbg_name = "ufs_unipro_core_clk_src", + .ops = &clk_ops_rcg, + VDD_DIG_FMAX_MAP3(LOWER, 37500000, LOW, 75000000, + NOMINAL, 150000000), + CLK_INIT(ufs_unipro_core_clk_src.c), + }, +}; + +static struct clk_freq_tbl ftbl_usb30_mock_utmi_clk_src[] = { + F( 19200000, cxo_clk_src, 1, 0, 0), + F_END +}; + +static struct rcg_clk usb30_mock_utmi_clk_src = { + .cmd_rcgr_reg = GCC_USB30_MOCK_UTMI_CMD_RCGR, + .set_rate = set_rate_hid, + .freq_tbl = ftbl_usb30_mock_utmi_clk_src, + .current_freq = &rcg_dummy_freq, + .base = &virt_base, + .c = { + .dbg_name = "usb30_mock_utmi_clk_src", + .ops = &clk_ops_rcg, + VDD_DIG_FMAX_MAP2(LOWER, 40000000, LOW, 60000000), + CLK_INIT(usb30_mock_utmi_clk_src.c), + }, +}; + +static struct clk_freq_tbl ftbl_usb3_phy_aux_clk_src[] = { + F( 1200000, cxo_clk_src, 16, 0, 0), + F_END +}; + +static struct rcg_clk usb3_phy_aux_clk_src = { + .cmd_rcgr_reg = GCC_USB3_PHY_AUX_CMD_RCGR, + .set_rate = set_rate_hid, + .freq_tbl = ftbl_usb3_phy_aux_clk_src, + .current_freq = &rcg_dummy_freq, + .base = &virt_base, + .c = { + .dbg_name = "usb3_phy_aux_clk_src", + .ops = &clk_ops_rcg, + VDD_DIG_FMAX_MAP1(LOWER, 19200000), + CLK_INIT(usb3_phy_aux_clk_src.c), + }, +}; + +static struct clk_freq_tbl ftbl_hmss_gpll0_clk_src[] = { + F( 300000000, gpll0_ao, 2, 0, 0), + F_END +}; + +static struct rcg_clk hmss_gpll0_clk_src = { + .cmd_rcgr_reg = GCC_HMSS_GPLL0_CMD_RCGR, + .set_rate = set_rate_hid, + .freq_tbl = ftbl_hmss_gpll0_clk_src, + .current_freq = &rcg_dummy_freq, + .base = &virt_base, + .c = { + .dbg_name = "hmss_gpll0_clk_src", + .ops = &clk_ops_rcg, + VDD_DIG_FMAX_MAP1_AO(LOWER, 600000000), + CLK_INIT(hmss_gpll0_clk_src.c), + }, +}; + +static struct clk_freq_tbl ftbl_qspi_ref_clk_src[] = { + F( 75000000, gpll0_out_main, 8, 0, 0), + F( 150000000, gpll0_out_main, 4, 0, 0), + F( 256000000, gpll4_out_main, 1.5, 0, 0), + F( 300000000, gpll0_out_main, 2, 0, 0), + F_END +}; + +static struct rcg_clk qspi_ref_clk_src = { + .cmd_rcgr_reg = GCC_QSPI_REF_CMD_RCGR, + .set_rate = set_rate_hid, + .freq_tbl = ftbl_qspi_ref_clk_src, + .current_freq = &rcg_dummy_freq, + .base = &virt_base, + .c = { + .dbg_name = "qspi_ref_clk_src", + .ops = &clk_ops_rcg, + VDD_DIG_FMAX_MAP3(LOWER, 40000000, LOW, 160400000, + NOMINAL, 320800000), + CLK_INIT(qspi_ref_clk_src.c), + }, +}; + +static struct branch_clk gcc_hdmi_clkref_clk = { + .cbcr_reg = GCC_HDMI_CLKREF_EN, + .has_sibling = 1, + .base = &virt_base, + .c = { + .dbg_name = "gcc_hdmi_clkref_clk", + .ops = &clk_ops_branch, + CLK_INIT(gcc_hdmi_clkref_clk.c), + }, +}; + +static struct branch_clk gcc_pcie_clkref_clk = { + .cbcr_reg = GCC_PCIE_CLKREF_EN, + .has_sibling = 1, + .base = &virt_base, + .c = { + .dbg_name = "gcc_pcie_clkref_clk", + .ops = &clk_ops_branch, + CLK_INIT(gcc_pcie_clkref_clk.c), + }, +}; + +static struct branch_clk gcc_rx1_usb2_clkref_clk = { + .cbcr_reg = GCC_RX1_USB2_CLKREF_EN, + .has_sibling = 1, + .base = &virt_base, + .c = { + .dbg_name = "gcc_rx1_usb2_clkref_clk", + .ops = &clk_ops_branch, + CLK_INIT(gcc_rx1_usb2_clkref_clk.c), + }, +}; + +static struct branch_clk gcc_ufs_clkref_clk = { + .cbcr_reg = GCC_UFS_CLKREF_EN, + .has_sibling = 1, + .base = &virt_base, + .c = { + .dbg_name = "gcc_ufs_clkref_clk", + .ops = &clk_ops_branch, + CLK_INIT(gcc_ufs_clkref_clk.c), + }, +}; + +static struct branch_clk gcc_usb3_clkref_clk = { + .cbcr_reg = GCC_USB3_CLKREF_EN, + .has_sibling = 1, + .base = &virt_base, + .c = { + .dbg_name = "gcc_usb3_clkref_clk", + .ops = &clk_ops_branch, + CLK_INIT(gcc_usb3_clkref_clk.c), + }, +}; + +static struct reset_clk gcc_usb3_phy_reset = { + .reset_reg = GCC_USB3_PHY_BCR, + .base = &virt_base, + .c = { + .dbg_name = "gcc_usb3_phy_reset", + .ops = &clk_ops_rst, + CLK_INIT(gcc_usb3_phy_reset.c), + }, +}; + +static struct reset_clk gcc_usb3phy_phy_reset = { + .reset_reg = GCC_USB3PHY_PHY_BCR, + .base = &virt_base, + .c = { + .dbg_name = "gcc_usb3phy_phy_reset", + .ops = &clk_ops_rst, + CLK_INIT(gcc_usb3phy_phy_reset.c), + }, +}; + +static struct gate_clk gpll0_out_msscc = { + .en_reg = GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1, + .en_mask = BIT(2), + .delay_us = 1, + .base = &virt_base, + .c = { + .dbg_name = "gpll0_out_msscc", + .ops = &clk_ops_gate, + CLK_INIT(gpll0_out_msscc.c), + }, +}; + +static struct branch_clk gcc_aggre1_ufs_axi_clk = { + .cbcr_reg = GCC_AGGRE1_UFS_AXI_CBCR, + .has_sibling = 1, + .base = &virt_base, + .c = { + .dbg_name = "gcc_aggre1_ufs_axi_clk", + .parent = &ufs_axi_clk_src.c, + .ops = &clk_ops_branch, + CLK_INIT(gcc_aggre1_ufs_axi_clk.c), + }, +}; + +static struct hw_ctl_clk gcc_aggre1_ufs_axi_hw_ctl_clk = { + .cbcr_reg = GCC_AGGRE1_UFS_AXI_CBCR, + .base = &virt_base, + .c = { + .dbg_name = "gcc_aggre1_ufs_axi_hw_ctl_clk", + .parent = &gcc_aggre1_ufs_axi_clk.c, + .ops = &clk_ops_branch_hw_ctl, + CLK_INIT(gcc_aggre1_ufs_axi_hw_ctl_clk.c), + }, +}; + +static struct branch_clk gcc_aggre1_usb3_axi_clk = { + .cbcr_reg = GCC_AGGRE1_USB3_AXI_CBCR, + .has_sibling = 1, + .base = &virt_base, + .c = { + .dbg_name = "gcc_aggre1_usb3_axi_clk", + .parent = &usb30_master_clk_src.c, + .ops = &clk_ops_branch, + CLK_INIT(gcc_aggre1_usb3_axi_clk.c), + }, +}; + +static struct branch_clk gcc_bimc_mss_q6_axi_clk = { + .cbcr_reg = GCC_BIMC_MSS_Q6_AXI_CBCR, + .has_sibling = 1, + .base = &virt_base, + .c = { + .dbg_name = "gcc_bimc_mss_q6_axi_clk", + .ops = &clk_ops_branch, + CLK_INIT(gcc_bimc_mss_q6_axi_clk.c), + }, +}; + +static struct local_vote_clk gcc_blsp1_ahb_clk = { + .cbcr_reg = GCC_BLSP1_AHB_CBCR, + .bcr_reg = GCC_BLSP1_BCR, + .vote_reg = GCC_APCS_CLOCK_BRANCH_ENA_VOTE, + .en_mask = BIT(17), + .base = &virt_base, + .c = { + .dbg_name = "gcc_blsp1_ahb_clk", + .ops = &clk_ops_vote, + CLK_INIT(gcc_blsp1_ahb_clk.c), + }, +}; + +static struct branch_clk gcc_blsp1_qup1_i2c_apps_clk = { + .cbcr_reg = GCC_BLSP1_QUP1_I2C_APPS_CBCR, + .has_sibling = 0, + .base = &virt_base, + .c = { + .dbg_name = "gcc_blsp1_qup1_i2c_apps_clk", + .parent = &blsp1_qup1_i2c_apps_clk_src.c, + .ops = &clk_ops_branch, + CLK_INIT(gcc_blsp1_qup1_i2c_apps_clk.c), + }, +}; + +static struct branch_clk gcc_blsp1_qup1_spi_apps_clk = { + .cbcr_reg = GCC_BLSP1_QUP1_SPI_APPS_CBCR, + .has_sibling = 0, + .base = &virt_base, + .c = { + .dbg_name = "gcc_blsp1_qup1_spi_apps_clk", + .parent = &blsp1_qup1_spi_apps_clk_src.c, + .ops = &clk_ops_branch, + CLK_INIT(gcc_blsp1_qup1_spi_apps_clk.c), + }, +}; + +static struct branch_clk gcc_blsp1_qup2_i2c_apps_clk = { + .cbcr_reg = GCC_BLSP1_QUP2_I2C_APPS_CBCR, + .has_sibling = 0, + .base = &virt_base, + .c = { + .dbg_name = "gcc_blsp1_qup2_i2c_apps_clk", + .parent = &blsp1_qup2_i2c_apps_clk_src.c, + .ops = &clk_ops_branch, + CLK_INIT(gcc_blsp1_qup2_i2c_apps_clk.c), + }, +}; + +static struct branch_clk gcc_blsp1_qup2_spi_apps_clk = { + .cbcr_reg = GCC_BLSP1_QUP2_SPI_APPS_CBCR, + .has_sibling = 0, + .base = &virt_base, + .c = { + .dbg_name = "gcc_blsp1_qup2_spi_apps_clk", + .parent = &blsp1_qup2_spi_apps_clk_src.c, + .ops = &clk_ops_branch, + CLK_INIT(gcc_blsp1_qup2_spi_apps_clk.c), + }, +}; + +static struct branch_clk gcc_blsp1_qup3_i2c_apps_clk = { + .cbcr_reg = GCC_BLSP1_QUP3_I2C_APPS_CBCR, + .has_sibling = 0, + .base = &virt_base, + .c = { + .dbg_name = "gcc_blsp1_qup3_i2c_apps_clk", + .parent = &blsp1_qup3_i2c_apps_clk_src.c, + .ops = &clk_ops_branch, + CLK_INIT(gcc_blsp1_qup3_i2c_apps_clk.c), + }, +}; + +static struct branch_clk gcc_blsp1_qup3_spi_apps_clk = { + .cbcr_reg = GCC_BLSP1_QUP3_SPI_APPS_CBCR, + .has_sibling = 0, + .base = &virt_base, + .c = { + .dbg_name = "gcc_blsp1_qup3_spi_apps_clk", + .parent = &blsp1_qup3_spi_apps_clk_src.c, + .ops = &clk_ops_branch, + CLK_INIT(gcc_blsp1_qup3_spi_apps_clk.c), + }, +}; + +static struct branch_clk gcc_blsp1_qup4_i2c_apps_clk = { + .cbcr_reg = GCC_BLSP1_QUP4_I2C_APPS_CBCR, + .has_sibling = 0, + .base = &virt_base, + .c = { + .dbg_name = "gcc_blsp1_qup4_i2c_apps_clk", + .parent = &blsp1_qup4_i2c_apps_clk_src.c, + .ops = &clk_ops_branch, + CLK_INIT(gcc_blsp1_qup4_i2c_apps_clk.c), + }, +}; + +static struct branch_clk gcc_blsp1_qup4_spi_apps_clk = { + .cbcr_reg = GCC_BLSP1_QUP4_SPI_APPS_CBCR, + .has_sibling = 0, + .base = &virt_base, + .c = { + .dbg_name = "gcc_blsp1_qup4_spi_apps_clk", + .parent = &blsp1_qup4_spi_apps_clk_src.c, + .ops = &clk_ops_branch, + CLK_INIT(gcc_blsp1_qup4_spi_apps_clk.c), + }, +}; + +static struct branch_clk gcc_blsp1_qup5_i2c_apps_clk = { + .cbcr_reg = GCC_BLSP1_QUP5_I2C_APPS_CBCR, + .has_sibling = 0, + .base = &virt_base, + .c = { + .dbg_name = "gcc_blsp1_qup5_i2c_apps_clk", + .parent = &blsp1_qup5_i2c_apps_clk_src.c, + .ops = &clk_ops_branch, + CLK_INIT(gcc_blsp1_qup5_i2c_apps_clk.c), + }, +}; + +static struct branch_clk gcc_blsp1_qup5_spi_apps_clk = { + .cbcr_reg = GCC_BLSP1_QUP5_SPI_APPS_CBCR, + .has_sibling = 0, + .base = &virt_base, + .c = { + .dbg_name = "gcc_blsp1_qup5_spi_apps_clk", + .parent = &blsp1_qup5_spi_apps_clk_src.c, + .ops = &clk_ops_branch, + CLK_INIT(gcc_blsp1_qup5_spi_apps_clk.c), + }, +}; + +static struct branch_clk gcc_blsp1_qup6_i2c_apps_clk = { + .cbcr_reg = GCC_BLSP1_QUP6_I2C_APPS_CBCR, + .has_sibling = 0, + .base = &virt_base, + .c = { + .dbg_name = "gcc_blsp1_qup6_i2c_apps_clk", + .parent = &blsp1_qup6_i2c_apps_clk_src.c, + .ops = &clk_ops_branch, + CLK_INIT(gcc_blsp1_qup6_i2c_apps_clk.c), + }, +}; + +static struct branch_clk gcc_blsp1_qup6_spi_apps_clk = { + .cbcr_reg = GCC_BLSP1_QUP6_SPI_APPS_CBCR, + .has_sibling = 0, + .base = &virt_base, + .c = { + .dbg_name = "gcc_blsp1_qup6_spi_apps_clk", + .parent = &blsp1_qup6_spi_apps_clk_src.c, + .ops = &clk_ops_branch, + CLK_INIT(gcc_blsp1_qup6_spi_apps_clk.c), + }, +}; + +static struct branch_clk gcc_blsp1_uart1_apps_clk = { + .cbcr_reg = GCC_BLSP1_UART1_APPS_CBCR, + .has_sibling = 0, + .base = &virt_base, + .c = { + .dbg_name = "gcc_blsp1_uart1_apps_clk", + .parent = &blsp1_uart1_apps_clk_src.c, + .ops = &clk_ops_branch, + CLK_INIT(gcc_blsp1_uart1_apps_clk.c), + }, +}; + +static struct branch_clk gcc_blsp1_uart2_apps_clk = { + .cbcr_reg = GCC_BLSP1_UART2_APPS_CBCR, + .has_sibling = 0, + .base = &virt_base, + .c = { + .dbg_name = "gcc_blsp1_uart2_apps_clk", + .parent = &blsp1_uart2_apps_clk_src.c, + .ops = &clk_ops_branch, + CLK_INIT(gcc_blsp1_uart2_apps_clk.c), + }, +}; + +static struct branch_clk gcc_blsp1_uart3_apps_clk = { + .cbcr_reg = GCC_BLSP1_UART3_APPS_CBCR, + .has_sibling = 0, + .base = &virt_base, + .c = { + .dbg_name = "gcc_blsp1_uart3_apps_clk", + .parent = &blsp1_uart3_apps_clk_src.c, + .ops = &clk_ops_branch, + CLK_INIT(gcc_blsp1_uart3_apps_clk.c), + }, +}; + +static struct local_vote_clk gcc_blsp2_ahb_clk = { + .cbcr_reg = GCC_BLSP2_AHB_CBCR, + .bcr_reg = GCC_BLSP2_BCR, + .vote_reg = GCC_APCS_CLOCK_BRANCH_ENA_VOTE, + .en_mask = BIT(15), + .base = &virt_base, + .c = { + .dbg_name = "gcc_blsp2_ahb_clk", + .ops = &clk_ops_vote, + CLK_INIT(gcc_blsp2_ahb_clk.c), + }, +}; + +static struct branch_clk gcc_blsp2_qup1_i2c_apps_clk = { + .cbcr_reg = GCC_BLSP2_QUP1_I2C_APPS_CBCR, + .has_sibling = 0, + .base = &virt_base, + .c = { + .dbg_name = "gcc_blsp2_qup1_i2c_apps_clk", + .parent = &blsp2_qup1_i2c_apps_clk_src.c, + .ops = &clk_ops_branch, + CLK_INIT(gcc_blsp2_qup1_i2c_apps_clk.c), + }, +}; + +static struct branch_clk gcc_blsp2_qup1_spi_apps_clk = { + .cbcr_reg = GCC_BLSP2_QUP1_SPI_APPS_CBCR, + .has_sibling = 0, + .base = &virt_base, + .c = { + .dbg_name = "gcc_blsp2_qup1_spi_apps_clk", + .parent = &blsp2_qup1_spi_apps_clk_src.c, + .ops = &clk_ops_branch, + CLK_INIT(gcc_blsp2_qup1_spi_apps_clk.c), + }, +}; + +static struct branch_clk gcc_blsp2_qup2_i2c_apps_clk = { + .cbcr_reg = GCC_BLSP2_QUP2_I2C_APPS_CBCR, + .has_sibling = 0, + .base = &virt_base, + .c = { + .dbg_name = "gcc_blsp2_qup2_i2c_apps_clk", + .parent = &blsp2_qup2_i2c_apps_clk_src.c, + .ops = &clk_ops_branch, + CLK_INIT(gcc_blsp2_qup2_i2c_apps_clk.c), + }, +}; + +static struct branch_clk gcc_blsp2_qup2_spi_apps_clk = { + .cbcr_reg = GCC_BLSP2_QUP2_SPI_APPS_CBCR, + .has_sibling = 0, + .base = &virt_base, + .c = { + .dbg_name = "gcc_blsp2_qup2_spi_apps_clk", + .parent = &blsp2_qup2_spi_apps_clk_src.c, + .ops = &clk_ops_branch, + CLK_INIT(gcc_blsp2_qup2_spi_apps_clk.c), + }, +}; + +static struct branch_clk gcc_blsp2_qup3_i2c_apps_clk = { + .cbcr_reg = GCC_BLSP2_QUP3_I2C_APPS_CBCR, + .has_sibling = 0, + .base = &virt_base, + .c = { + .dbg_name = "gcc_blsp2_qup3_i2c_apps_clk", + .parent = &blsp2_qup3_i2c_apps_clk_src.c, + .ops = &clk_ops_branch, + CLK_INIT(gcc_blsp2_qup3_i2c_apps_clk.c), + }, +}; + +static struct branch_clk gcc_blsp2_qup3_spi_apps_clk = { + .cbcr_reg = GCC_BLSP2_QUP3_SPI_APPS_CBCR, + .has_sibling = 0, + .base = &virt_base, + .c = { + .dbg_name = "gcc_blsp2_qup3_spi_apps_clk", + .parent = &blsp2_qup3_spi_apps_clk_src.c, + .ops = &clk_ops_branch, + CLK_INIT(gcc_blsp2_qup3_spi_apps_clk.c), + }, +}; + +static struct branch_clk gcc_blsp2_qup4_i2c_apps_clk = { + .cbcr_reg = GCC_BLSP2_QUP4_I2C_APPS_CBCR, + .has_sibling = 0, + .base = &virt_base, + .c = { + .dbg_name = "gcc_blsp2_qup4_i2c_apps_clk", + .parent = &blsp2_qup4_i2c_apps_clk_src.c, + .ops = &clk_ops_branch, + CLK_INIT(gcc_blsp2_qup4_i2c_apps_clk.c), + }, +}; + +static struct branch_clk gcc_blsp2_qup4_spi_apps_clk = { + .cbcr_reg = GCC_BLSP2_QUP4_SPI_APPS_CBCR, + .has_sibling = 0, + .base = &virt_base, + .c = { + .dbg_name = "gcc_blsp2_qup4_spi_apps_clk", + .parent = &blsp2_qup4_spi_apps_clk_src.c, + .ops = &clk_ops_branch, + CLK_INIT(gcc_blsp2_qup4_spi_apps_clk.c), + }, +}; + +static struct branch_clk gcc_blsp2_qup5_i2c_apps_clk = { + .cbcr_reg = GCC_BLSP2_QUP5_I2C_APPS_CBCR, + .has_sibling = 0, + .base = &virt_base, + .c = { + .dbg_name = "gcc_blsp2_qup5_i2c_apps_clk", + .parent = &blsp2_qup5_i2c_apps_clk_src.c, + .ops = &clk_ops_branch, + CLK_INIT(gcc_blsp2_qup5_i2c_apps_clk.c), + }, +}; + +static struct branch_clk gcc_blsp2_qup5_spi_apps_clk = { + .cbcr_reg = GCC_BLSP2_QUP5_SPI_APPS_CBCR, + .has_sibling = 0, + .base = &virt_base, + .c = { + .dbg_name = "gcc_blsp2_qup5_spi_apps_clk", + .parent = &blsp2_qup5_spi_apps_clk_src.c, + .ops = &clk_ops_branch, + CLK_INIT(gcc_blsp2_qup5_spi_apps_clk.c), + }, +}; + +static struct branch_clk gcc_blsp2_qup6_i2c_apps_clk = { + .cbcr_reg = GCC_BLSP2_QUP6_I2C_APPS_CBCR, + .has_sibling = 0, + .base = &virt_base, + .c = { + .dbg_name = "gcc_blsp2_qup6_i2c_apps_clk", + .parent = &blsp2_qup6_i2c_apps_clk_src.c, + .ops = &clk_ops_branch, + CLK_INIT(gcc_blsp2_qup6_i2c_apps_clk.c), + }, +}; + +static struct branch_clk gcc_blsp2_qup6_spi_apps_clk = { + .cbcr_reg = GCC_BLSP2_QUP6_SPI_APPS_CBCR, + .has_sibling = 0, + .base = &virt_base, + .c = { + .dbg_name = "gcc_blsp2_qup6_spi_apps_clk", + .parent = &blsp2_qup6_spi_apps_clk_src.c, + .ops = &clk_ops_branch, + CLK_INIT(gcc_blsp2_qup6_spi_apps_clk.c), + }, +}; + +static struct branch_clk gcc_blsp2_uart1_apps_clk = { + .cbcr_reg = GCC_BLSP2_UART1_APPS_CBCR, + .has_sibling = 0, + .base = &virt_base, + .c = { + .dbg_name = "gcc_blsp2_uart1_apps_clk", + .parent = &blsp2_uart1_apps_clk_src.c, + .ops = &clk_ops_branch, + CLK_INIT(gcc_blsp2_uart1_apps_clk.c), + }, +}; + +static struct branch_clk gcc_blsp2_uart2_apps_clk = { + .cbcr_reg = GCC_BLSP2_UART2_APPS_CBCR, + .has_sibling = 0, + .base = &virt_base, + .c = { + .dbg_name = "gcc_blsp2_uart2_apps_clk", + .parent = &blsp2_uart2_apps_clk_src.c, + .ops = &clk_ops_branch, + CLK_INIT(gcc_blsp2_uart2_apps_clk.c), + }, +}; + +static struct branch_clk gcc_blsp2_uart3_apps_clk = { + .cbcr_reg = GCC_BLSP2_UART3_APPS_CBCR, + .has_sibling = 0, + .base = &virt_base, + .c = { + .dbg_name = "gcc_blsp2_uart3_apps_clk", + .parent = &blsp2_uart3_apps_clk_src.c, + .ops = &clk_ops_branch, + CLK_INIT(gcc_blsp2_uart3_apps_clk.c), + }, +}; + +static struct local_vote_clk gcc_boot_rom_ahb_clk = { + .cbcr_reg = GCC_BOOT_ROM_AHB_CBCR, + .bcr_reg = GCC_BOOT_ROM_BCR, + .vote_reg = GCC_APCS_CLOCK_BRANCH_ENA_VOTE, + .en_mask = BIT(10), + .base = &virt_base, + .c = { + .dbg_name = "gcc_boot_rom_ahb_clk", + .ops = &clk_ops_vote, + CLK_INIT(gcc_boot_rom_ahb_clk.c), + }, +}; + +static struct branch_clk gcc_cfg_noc_usb3_axi_clk = { + .cbcr_reg = GCC_CFG_NOC_USB3_AXI_CBCR, + .has_sibling = 1, + .base = &virt_base, + .c = { + .dbg_name = "gcc_cfg_noc_usb3_axi_clk", + .parent = &usb30_master_clk_src.c, + .ops = &clk_ops_branch, + CLK_INIT(gcc_cfg_noc_usb3_axi_clk.c), + }, +}; + +static struct branch_clk gcc_bimc_gfx_clk = { + .cbcr_reg = GCC_BIMC_GFX_CBCR, + .has_sibling = 1, + .check_enable_bit = true, + .no_halt_check_on_disable = true, + .base = &virt_base, + .c = { + .dbg_name = "gcc_bimc_gfx_clk", + .ops = &clk_ops_branch, + CLK_INIT(gcc_bimc_gfx_clk.c), + }, +}; + +static struct branch_clk gcc_gp1_clk = { + .cbcr_reg = GCC_GP1_CBCR, + .has_sibling = 0, + .base = &virt_base, + .c = { + .dbg_name = "gcc_gp1_clk", + .parent = &gp1_clk_src.c, + .ops = &clk_ops_branch, + CLK_INIT(gcc_gp1_clk.c), + }, +}; + +static struct branch_clk gcc_gp2_clk = { + .cbcr_reg = GCC_GP2_CBCR, + .has_sibling = 0, + .base = &virt_base, + .c = { + .dbg_name = "gcc_gp2_clk", + .parent = &gp2_clk_src.c, + .ops = &clk_ops_branch, + CLK_INIT(gcc_gp2_clk.c), + }, +}; + +static struct branch_clk gcc_gp3_clk = { + .cbcr_reg = GCC_GP3_CBCR, + .has_sibling = 0, + .base = &virt_base, + .c = { + .dbg_name = "gcc_gp3_clk", + .parent = &gp3_clk_src.c, + .ops = &clk_ops_branch, + CLK_INIT(gcc_gp3_clk.c), + }, +}; + +static struct branch_clk gcc_gpu_bimc_gfx_clk = { + .cbcr_reg = GCC_GPU_BIMC_GFX_CBCR, + .has_sibling = 1, + .check_enable_bit = true, + .no_halt_check_on_disable = true, + .base = &virt_base, + .c = { + .dbg_name = "gcc_gpu_bimc_gfx_clk", + .ops = &clk_ops_branch, + CLK_INIT(gcc_gpu_bimc_gfx_clk.c), + }, +}; + +static struct branch_clk gcc_gpu_cfg_ahb_clk = { + .cbcr_reg = GCC_GPU_CFG_AHB_CBCR, + .has_sibling = 1, + .check_enable_bit = true, + .no_halt_check_on_disable = true, + .base = &virt_base, + .c = { + .dbg_name = "gcc_gpu_cfg_ahb_clk", + .ops = &clk_ops_branch, + CLK_INIT(gcc_gpu_cfg_ahb_clk.c), + }, +}; + +static struct branch_clk gcc_gpu_iref_clk = { + .cbcr_reg = GCC_GPU_IREF_EN, + .has_sibling = 1, + .base = &virt_base, + .c = { + .dbg_name = "gcc_gpu_iref_clk", + .ops = &clk_ops_branch, + CLK_INIT(gcc_gpu_iref_clk.c), + }, +}; + +static struct branch_clk gcc_hmss_dvm_bus_clk = { + .cbcr_reg = GCC_HMSS_DVM_BUS_CBCR, + .has_sibling = 1, + .base = &virt_base, + .c = { + .dbg_name = "gcc_hmss_dvm_bus_clk", + .always_on = true, + .ops = &clk_ops_branch, + CLK_INIT(gcc_hmss_dvm_bus_clk.c), + }, +}; + +static struct branch_clk gcc_hmss_rbcpr_clk = { + .cbcr_reg = GCC_HMSS_RBCPR_CBCR, + .has_sibling = 0, + .base = &virt_base, + .c = { + .dbg_name = "gcc_hmss_rbcpr_clk", + .parent = &hmss_rbcpr_clk_src.c, + .ops = &clk_ops_branch, + CLK_INIT(gcc_hmss_rbcpr_clk.c), + }, +}; + +static struct branch_clk gcc_mmss_noc_cfg_ahb_clk = { + .cbcr_reg = GCC_MMSS_NOC_CFG_AHB_CBCR, + .has_sibling = 1, + .base = &virt_base, + .c = { + .dbg_name = "gcc_mmss_noc_cfg_ahb_clk", + .ops = &clk_ops_branch, + CLK_INIT(gcc_mmss_noc_cfg_ahb_clk.c), + }, +}; + +static struct branch_clk gcc_mmss_sys_noc_axi_clk = { + .cbcr_reg = GCC_MMSS_SYS_NOC_AXI_CBCR, + .has_sibling = 1, + .base = &virt_base, + .c = { + .dbg_name = "gcc_mmss_sys_noc_axi_clk", + .ops = &clk_ops_branch, + CLK_INIT(gcc_mmss_sys_noc_axi_clk.c), + }, +}; + +static struct branch_clk gcc_pcie_0_aux_clk = { + .cbcr_reg = GCC_PCIE_0_AUX_CBCR, + .has_sibling = 0, + .base = &virt_base, + .c = { + .dbg_name = "gcc_pcie_0_aux_clk", + .parent = &pcie_aux_clk_src.c, + .ops = &clk_ops_branch, + CLK_INIT(gcc_pcie_0_aux_clk.c), + }, +}; + +static struct branch_clk gcc_pcie_0_cfg_ahb_clk = { + .cbcr_reg = GCC_PCIE_0_CFG_AHB_CBCR, + .has_sibling = 1, + .base = &virt_base, + .c = { + .dbg_name = "gcc_pcie_0_cfg_ahb_clk", + .ops = &clk_ops_branch, + CLK_INIT(gcc_pcie_0_cfg_ahb_clk.c), + }, +}; + +static struct branch_clk gcc_pcie_0_mstr_axi_clk = { + .cbcr_reg = GCC_PCIE_0_MSTR_AXI_CBCR, + .has_sibling = 1, + .base = &virt_base, + .c = { + .dbg_name = "gcc_pcie_0_mstr_axi_clk", + .ops = &clk_ops_branch, + CLK_INIT(gcc_pcie_0_mstr_axi_clk.c), + }, +}; + +static struct branch_clk gcc_pcie_0_pipe_clk = { + .cbcr_reg = GCC_PCIE_0_PIPE_CBCR, + .bcr_reg = GCC_PCIE_0_PHY_BCR, + .has_sibling = 1, + .halt_check = DELAY, + .base = &virt_base, + .c = { + .dbg_name = "gcc_pcie_0_pipe_clk", + .ops = &clk_ops_branch, + CLK_INIT(gcc_pcie_0_pipe_clk.c), + }, +}; + +static struct branch_clk gcc_pcie_0_slv_axi_clk = { + .cbcr_reg = GCC_PCIE_0_SLV_AXI_CBCR, + .has_sibling = 1, + .base = &virt_base, + .c = { + .dbg_name = "gcc_pcie_0_slv_axi_clk", + .ops = &clk_ops_branch, + CLK_INIT(gcc_pcie_0_slv_axi_clk.c), + }, +}; + +static struct branch_clk gcc_pcie_phy_aux_clk = { + .cbcr_reg = GCC_PCIE_PHY_AUX_CBCR, + .has_sibling = 1, + .base = &virt_base, + .c = { + .dbg_name = "gcc_pcie_phy_aux_clk", + .parent = &pcie_aux_clk_src.c, + .ops = &clk_ops_branch, + CLK_INIT(gcc_pcie_phy_aux_clk.c), + }, +}; + +static struct reset_clk gcc_pcie_phy_reset = { + .reset_reg = GCC_PCIE_PHY_BCR, + .base = &virt_base, + .c = { + .dbg_name = "gcc_pcie_phy_reset", + .ops = &clk_ops_rst, + CLK_INIT(gcc_pcie_phy_reset.c), + }, +}; + +static struct reset_clk gcc_pcie_phy_com_reset = { + .reset_reg = GCC_PCIE_PHY_COM_BCR, + .base = &virt_base, + .c = { + .dbg_name = "gcc_pcie_phy_com_reset", + .ops = &clk_ops_rst, + CLK_INIT(gcc_pcie_phy_com_reset.c), + }, +}; + +static struct reset_clk gcc_pcie_phy_nocsr_com_phy_reset = { + .reset_reg = GCC_PCIE_PHY_NOCSR_COM_PHY_BCR, + .base = &virt_base, + .c = { + .dbg_name = "gcc_pcie_phy_nocsr_com_phy_reset", + .ops = &clk_ops_rst, + CLK_INIT(gcc_pcie_phy_nocsr_com_phy_reset.c), + }, +}; + +static struct branch_clk gcc_pdm2_clk = { + .cbcr_reg = GCC_PDM2_CBCR, + .has_sibling = 0, + .base = &virt_base, + .c = { + .dbg_name = "gcc_pdm2_clk", + .parent = &pdm2_clk_src.c, + .ops = &clk_ops_branch, + CLK_INIT(gcc_pdm2_clk.c), + }, +}; + +static struct branch_clk gcc_pdm_ahb_clk = { + .cbcr_reg = GCC_PDM_AHB_CBCR, + .has_sibling = 1, + .base = &virt_base, + .c = { + .dbg_name = "gcc_pdm_ahb_clk", + .ops = &clk_ops_branch, + CLK_INIT(gcc_pdm_ahb_clk.c), + }, +}; + +static struct local_vote_clk gcc_prng_ahb_clk = { + .cbcr_reg = GCC_PRNG_AHB_CBCR, + .bcr_reg = GCC_PRNG_BCR, + .vote_reg = GCC_APCS_CLOCK_BRANCH_ENA_VOTE, + .en_mask = BIT(13), + .base = &virt_base, + .c = { + .dbg_name = "gcc_prng_ahb_clk", + .ops = &clk_ops_vote, + CLK_INIT(gcc_prng_ahb_clk.c), + }, +}; + +static struct branch_clk gcc_sdcc2_ahb_clk = { + .cbcr_reg = GCC_SDCC2_AHB_CBCR, + .has_sibling = 1, + .base = &virt_base, + .c = { + .dbg_name = "gcc_sdcc2_ahb_clk", + .ops = &clk_ops_branch, + CLK_INIT(gcc_sdcc2_ahb_clk.c), + }, +}; + +static struct branch_clk gcc_sdcc2_apps_clk = { + .cbcr_reg = GCC_SDCC2_APPS_CBCR, + .has_sibling = 0, + .base = &virt_base, + .c = { + .dbg_name = "gcc_sdcc2_apps_clk", + .parent = &sdcc2_apps_clk_src.c, + .ops = &clk_ops_branch, + CLK_INIT(gcc_sdcc2_apps_clk.c), + }, +}; + +static struct branch_clk gcc_sdcc4_ahb_clk = { + .cbcr_reg = GCC_SDCC4_AHB_CBCR, + .has_sibling = 1, + .base = &virt_base, + .c = { + .dbg_name = "gcc_sdcc4_ahb_clk", + .ops = &clk_ops_branch, + CLK_INIT(gcc_sdcc4_ahb_clk.c), + }, +}; + +static struct branch_clk gcc_sdcc4_apps_clk = { + .cbcr_reg = GCC_SDCC4_APPS_CBCR, + .has_sibling = 0, + .base = &virt_base, + .c = { + .dbg_name = "gcc_sdcc4_apps_clk", + .parent = &sdcc4_apps_clk_src.c, + .ops = &clk_ops_branch, + CLK_INIT(gcc_sdcc4_apps_clk.c), + }, +}; + +static struct branch_clk gcc_tsif_ahb_clk = { + .cbcr_reg = GCC_TSIF_AHB_CBCR, + .has_sibling = 1, + .base = &virt_base, + .c = { + .dbg_name = "gcc_tsif_ahb_clk", + .ops = &clk_ops_branch, + CLK_INIT(gcc_tsif_ahb_clk.c), + }, +}; + +static struct branch_clk gcc_tsif_ref_clk = { + .cbcr_reg = GCC_TSIF_REF_CBCR, + .has_sibling = 0, + .base = &virt_base, + .c = { + .dbg_name = "gcc_tsif_ref_clk", + .parent = &tsif_ref_clk_src.c, + .ops = &clk_ops_branch, + CLK_INIT(gcc_tsif_ref_clk.c), + }, +}; + +static struct branch_clk gcc_ufs_ahb_clk = { + .cbcr_reg = GCC_UFS_AHB_CBCR, + .has_sibling = 1, + .base = &virt_base, + .c = { + .dbg_name = "gcc_ufs_ahb_clk", + .ops = &clk_ops_branch, + CLK_INIT(gcc_ufs_ahb_clk.c), + }, +}; + +static struct branch_clk gcc_ufs_axi_clk = { + .cbcr_reg = GCC_UFS_AXI_CBCR, + .bcr_reg = GCC_UFS_BCR, + .has_sibling = 0, + .base = &virt_base, + .c = { + .dbg_name = "gcc_ufs_axi_clk", + .parent = &ufs_axi_clk_src.c, + .ops = &clk_ops_branch, + CLK_INIT(gcc_ufs_axi_clk.c), + }, +}; + +static struct hw_ctl_clk gcc_ufs_axi_hw_ctl_clk = { + .cbcr_reg = GCC_UFS_AXI_CBCR, + .base = &virt_base, + .c = { + .dbg_name = "gcc_ufs_axi_hw_ctl_clk", + .parent = &gcc_ufs_axi_clk.c, + .ops = &clk_ops_branch_hw_ctl, + CLK_INIT(gcc_ufs_axi_hw_ctl_clk.c), + }, +}; + +static struct branch_clk gcc_ufs_ice_core_clk = { + .cbcr_reg = GCC_UFS_ICE_CORE_CBCR, + .has_sibling = 0, + .base = &virt_base, + .c = { + .dbg_name = "gcc_ufs_ice_core_clk", + .parent = &ufs_ice_core_clk_src.c, + .ops = &clk_ops_branch, + CLK_INIT(gcc_ufs_ice_core_clk.c), + }, +}; + +static struct hw_ctl_clk gcc_ufs_ice_core_hw_ctl_clk = { + .cbcr_reg = GCC_UFS_ICE_CORE_CBCR, + .base = &virt_base, + .c = { + .dbg_name = "gcc_ufs_ice_core_hw_ctl_clk", + .parent = &gcc_ufs_ice_core_clk.c, + .ops = &clk_ops_branch_hw_ctl, + CLK_INIT(gcc_ufs_ice_core_hw_ctl_clk.c), + }, +}; + +static struct branch_clk gcc_ufs_phy_aux_clk = { + .cbcr_reg = GCC_UFS_PHY_AUX_CBCR, + .has_sibling = 0, + .base = &virt_base, + .c = { + .dbg_name = "gcc_ufs_phy_aux_clk", + .parent = &ufs_phy_aux_clk_src.c, + .ops = &clk_ops_branch, + CLK_INIT(gcc_ufs_phy_aux_clk.c), + }, +}; + +static struct hw_ctl_clk gcc_ufs_phy_aux_hw_ctl_clk = { + .cbcr_reg = GCC_UFS_PHY_AUX_CBCR, + .base = &virt_base, + .c = { + .dbg_name = "gcc_ufs_phy_aux_hw_ctl_clk", + .parent = &gcc_ufs_phy_aux_clk.c, + .ops = &clk_ops_branch_hw_ctl, + CLK_INIT(gcc_ufs_phy_aux_hw_ctl_clk.c), + }, +}; + +static struct gate_clk gcc_ufs_rx_symbol_0_clk = { + .en_reg = GCC_UFS_RX_SYMBOL_0_CBCR, + .en_mask = BIT(0), + .delay_us = 500, + .base = &virt_base, + .c = { + .dbg_name = "gcc_ufs_rx_symbol_0_clk", + .ops = &clk_ops_gate, + CLK_INIT(gcc_ufs_rx_symbol_0_clk.c), + }, +}; + +static struct gate_clk gcc_ufs_rx_symbol_1_clk = { + .en_reg = GCC_UFS_RX_SYMBOL_1_CBCR, + .en_mask = BIT(0), + .delay_us = 500, + .base = &virt_base, + .c = { + .dbg_name = "gcc_ufs_rx_symbol_1_clk", + .ops = &clk_ops_gate, + CLK_INIT(gcc_ufs_rx_symbol_1_clk.c), + }, +}; + +static struct gate_clk gcc_ufs_tx_symbol_0_clk = { + .en_reg = GCC_UFS_TX_SYMBOL_0_CBCR, + .en_mask = BIT(0), + .delay_us = 500, + .base = &virt_base, + .c = { + .dbg_name = "gcc_ufs_tx_symbol_0_clk", + .ops = &clk_ops_gate, + CLK_INIT(gcc_ufs_tx_symbol_0_clk.c), + }, +}; + +static struct branch_clk gcc_ufs_unipro_core_clk = { + .cbcr_reg = GCC_UFS_UNIPRO_CORE_CBCR, + .has_sibling = 0, + .base = &virt_base, + .c = { + .dbg_name = "gcc_ufs_unipro_core_clk", + .parent = &ufs_unipro_core_clk_src.c, + .ops = &clk_ops_branch, + CLK_INIT(gcc_ufs_unipro_core_clk.c), + }, +}; + +static struct hw_ctl_clk gcc_ufs_unipro_core_hw_ctl_clk = { + .cbcr_reg = GCC_UFS_UNIPRO_CORE_CBCR, + .base = &virt_base, + .c = { + .dbg_name = "gcc_ufs_unipro_core_hw_ctl_clk", + .parent = &gcc_ufs_unipro_core_clk.c, + .ops = &clk_ops_branch_hw_ctl, + CLK_INIT(gcc_ufs_unipro_core_hw_ctl_clk.c), + }, +}; + +static struct branch_clk gcc_usb30_master_clk = { + .cbcr_reg = GCC_USB30_MASTER_CBCR, + .bcr_reg = GCC_USB_30_BCR, + .has_sibling = 0, + .base = &virt_base, + .c = { + .dbg_name = "gcc_usb30_master_clk", + .parent = &usb30_master_clk_src.c, + .ops = &clk_ops_branch, + CLK_INIT(gcc_usb30_master_clk.c), + .depends = &gcc_cfg_noc_usb3_axi_clk.c, + }, +}; + +static struct branch_clk gcc_usb30_mock_utmi_clk = { + .cbcr_reg = GCC_USB30_MOCK_UTMI_CBCR, + .has_sibling = 0, + .base = &virt_base, + .c = { + .dbg_name = "gcc_usb30_mock_utmi_clk", + .parent = &usb30_mock_utmi_clk_src.c, + .ops = &clk_ops_branch, + CLK_INIT(gcc_usb30_mock_utmi_clk.c), + }, +}; + +static struct branch_clk gcc_usb30_sleep_clk = { + .cbcr_reg = GCC_USB30_SLEEP_CBCR, + .has_sibling = 1, + .base = &virt_base, + .c = { + .dbg_name = "gcc_usb30_sleep_clk", + .ops = &clk_ops_branch, + CLK_INIT(gcc_usb30_sleep_clk.c), + }, +}; + +static struct branch_clk gcc_usb3_phy_aux_clk = { + .cbcr_reg = GCC_USB3_PHY_AUX_CBCR, + .has_sibling = 0, + .base = &virt_base, + .c = { + .dbg_name = "gcc_usb3_phy_aux_clk", + .parent = &usb3_phy_aux_clk_src.c, + .ops = &clk_ops_branch, + CLK_INIT(gcc_usb3_phy_aux_clk.c), + }, +}; + +static struct gate_clk gcc_usb3_phy_pipe_clk = { + .en_reg = GCC_USB3_PHY_PIPE_CBCR, + .en_mask = BIT(0), + .delay_us = 50, + .base = &virt_base, + .c = { + .dbg_name = "gcc_usb3_phy_pipe_clk", + .ops = &clk_ops_gate, + CLK_INIT(gcc_usb3_phy_pipe_clk.c), + }, +}; + +static struct reset_clk gcc_qusb2phy_prim_reset = { + .reset_reg = GCC_QUSB2PHY_PRIM_BCR, + .base = &virt_base, + .c = { + .dbg_name = "gcc_qusb2phy_prim_reset", + .ops = &clk_ops_rst, + CLK_INIT(gcc_qusb2phy_prim_reset.c), + }, +}; + +static struct reset_clk gcc_qusb2phy_sec_reset = { + .reset_reg = GCC_QUSB2PHY_SEC_BCR, + .base = &virt_base, + .c = { + .dbg_name = "gcc_qusb2phy_sec_reset", + .ops = &clk_ops_rst, + CLK_INIT(gcc_qusb2phy_sec_reset.c), + }, +}; + +static struct branch_clk gcc_mss_cfg_ahb_clk = { + .cbcr_reg = GCC_MSS_CFG_AHB_CBCR, + .has_sibling = 1, + .base = &virt_base, + .c = { + .dbg_name = "gcc_mss_cfg_ahb_clk", + .ops = &clk_ops_branch, + CLK_INIT(gcc_mss_cfg_ahb_clk.c), + }, +}; + +static struct branch_clk gcc_mss_q6_bimc_axi_clk = { + .cbcr_reg = GCC_MSS_Q6_BIMC_AXI_CBCR, + .has_sibling = 1, + .base = &virt_base, + .c = { + .dbg_name = "gcc_mss_q6_bimc_axi_clk", + .always_on = true, + .ops = &clk_ops_branch, + CLK_INIT(gcc_mss_q6_bimc_axi_clk.c), + }, +}; + +static struct branch_clk gcc_mss_mnoc_bimc_axi_clk = { + .cbcr_reg = GCC_MSS_MNOC_BIMC_AXI_CBCR, + .has_sibling = 1, + .base = &virt_base, + .c = { + .dbg_name = "gcc_mss_mnoc_bimc_axi_clk", + .ops = &clk_ops_branch, + CLK_INIT(gcc_mss_mnoc_bimc_axi_clk.c), + }, +}; + +static struct branch_clk gcc_mss_snoc_axi_clk = { + .cbcr_reg = GCC_MSS_SNOC_AXI_CBCR, + .has_sibling = 1, + .base = &virt_base, + .c = { + .dbg_name = "gcc_mss_snoc_axi_clk", + .ops = &clk_ops_branch, + CLK_INIT(gcc_mss_snoc_axi_clk.c), + }, +}; + +static struct branch_clk gcc_dcc_ahb_clk = { + .cbcr_reg = GCC_DCC_AHB_CBCR, + .has_sibling = 1, + .base = &virt_base, + .c = { + .dbg_name = "gcc_dcc_ahb_clk", + .ops = &clk_ops_branch, + CLK_INIT(gcc_dcc_ahb_clk.c), + }, +}; + +static struct branch_clk hlos1_vote_lpass_core_smmu_clk = { + .cbcr_reg = GCC_HLOS1_VOTE_LPASS_CORE_SMMU_CBCR, + .has_sibling = 0, + .base = &virt_base, + .no_halt_check_on_disable = true, + .c = { + .dbg_name = "hlos1_vote_lpass_core_smmu_clk", + .ops = &clk_ops_branch, + CLK_INIT(hlos1_vote_lpass_core_smmu_clk.c), + }, +}; + +static struct branch_clk hlos1_vote_lpass_adsp_smmu_clk = { + .cbcr_reg = GCC_HLOS1_VOTE_LPASS_ADSP_SMMU_CBCR, + .has_sibling = 0, + .base = &virt_base, + .no_halt_check_on_disable = true, + .c = { + .dbg_name = "hlos1_vote_lpass_adsp_smmu_clk", + .ops = &clk_ops_branch, + CLK_INIT(hlos1_vote_lpass_adsp_smmu_clk.c), + }, +}; + +static struct branch_clk gcc_qspi_ahb_clk = { + .cbcr_reg = GCC_QSPI_AHB_CBCR, + .has_sibling = 1, + .base = &virt_base, + .c = { + .dbg_name = "gcc_qspi_ahb_clk", + .ops = &clk_ops_branch, + CLK_INIT(gcc_qspi_ahb_clk.c), + }, +}; + +static struct branch_clk gcc_qspi_ref_clk = { + .cbcr_reg = GCC_QSPI_REF_CBCR, + .has_sibling = 0, + .base = &virt_base, + .c = { + .dbg_name = "gcc_qspi_ref_clk", + .parent = &qspi_ref_clk_src.c, + .ops = &clk_ops_branch, + CLK_INIT(gcc_qspi_ref_clk.c), + }, +}; + +static struct mux_clk gcc_debug_mux; +static struct clk_ops clk_ops_debug_mux; + +static struct measure_clk_data debug_mux_priv = { + .cxo = &cxo_clk_src.c, + .plltest_reg = PLLTEST_PAD_CFG, + .plltest_val = 0x51A00, + .xo_div4_cbcr = GCC_XO_DIV4_CBCR, + .ctl_reg = CLOCK_FRQ_MEASURE_CTL, + .status_reg = CLOCK_FRQ_MEASURE_STATUS, + .base = &virt_base, +}; + +static struct mux_clk gcc_debug_mux = { + .priv = &debug_mux_priv, + .ops = &mux_reg_ops, + .en_mask = BIT(16), + .mask = 0x3FF, + .base = &virt_dbgbase, + MUX_REC_SRC_LIST( + &gpu_gcc_debug_clk.c, + &gfx_gcc_debug_clk.c, + &debug_mmss_clk.c, + &debug_cpu_clk.c, + ), + MUX_SRC_LIST( + { &gpu_gcc_debug_clk.c, 0x013d }, + { &gfx_gcc_debug_clk.c, 0x013d }, + { &debug_mmss_clk.c, 0x0022 }, + { &debug_cpu_clk.c, 0x00c0 }, + { &snoc_clk.c, 0x0000 }, + { &cnoc_clk.c, 0x000e }, + { &bimc_clk.c, 0x014e }, + { &gcc_mmss_sys_noc_axi_clk.c, 0x001f }, + { &gcc_mmss_noc_cfg_ahb_clk.c, 0x0020 }, + { &gcc_usb30_master_clk.c, 0x003e }, + { &gcc_usb30_sleep_clk.c, 0x003f }, + { &gcc_usb30_mock_utmi_clk.c, 0x0040 }, + { &gcc_usb3_phy_aux_clk.c, 0x0041 }, + { &gcc_usb3_phy_pipe_clk.c, 0x0042 }, + { &gcc_sdcc2_apps_clk.c, 0x0046 }, + { &gcc_sdcc2_ahb_clk.c, 0x0047 }, + { &gcc_sdcc4_apps_clk.c, 0x0048 }, + { &gcc_sdcc4_ahb_clk.c, 0x0049 }, + { &gcc_blsp1_ahb_clk.c, 0x004a }, + { &gcc_blsp1_qup1_spi_apps_clk.c, 0x004c }, + { &gcc_blsp1_qup1_i2c_apps_clk.c, 0x004d }, + { &gcc_blsp1_uart1_apps_clk.c, 0x004e }, + { &gcc_blsp1_qup2_spi_apps_clk.c, 0x0050 }, + { &gcc_blsp1_qup2_i2c_apps_clk.c, 0x0051 }, + { &gcc_blsp1_uart2_apps_clk.c, 0x0052 }, + { &gcc_blsp1_qup3_spi_apps_clk.c, 0x0054 }, + { &gcc_blsp1_qup3_i2c_apps_clk.c, 0x0055 }, + { &gcc_blsp1_uart3_apps_clk.c, 0x0056 }, + { &gcc_blsp1_qup4_spi_apps_clk.c, 0x0058 }, + { &gcc_blsp1_qup4_i2c_apps_clk.c, 0x0059 }, + { &gcc_blsp1_qup5_spi_apps_clk.c, 0x005a }, + { &gcc_blsp1_qup5_i2c_apps_clk.c, 0x005b }, + { &gcc_blsp1_qup6_spi_apps_clk.c, 0x005c }, + { &gcc_blsp1_qup6_i2c_apps_clk.c, 0x005d }, + { &gcc_blsp2_ahb_clk.c, 0x005e }, + { &gcc_blsp2_qup1_spi_apps_clk.c, 0x0060 }, + { &gcc_blsp2_qup1_i2c_apps_clk.c, 0x0061 }, + { &gcc_blsp2_uart1_apps_clk.c, 0x0062 }, + { &gcc_blsp2_qup2_spi_apps_clk.c, 0x0064 }, + { &gcc_blsp2_qup2_i2c_apps_clk.c, 0x0065 }, + { &gcc_blsp2_uart2_apps_clk.c, 0x0066 }, + { &gcc_blsp2_qup3_spi_apps_clk.c, 0x0068 }, + { &gcc_blsp2_qup3_i2c_apps_clk.c, 0x0069 }, + { &gcc_blsp2_uart3_apps_clk.c, 0x006a }, + { &gcc_blsp2_qup4_spi_apps_clk.c, 0x006c }, + { &gcc_blsp2_qup4_i2c_apps_clk.c, 0x006d }, + { &gcc_blsp2_qup5_spi_apps_clk.c, 0x006e }, + { &gcc_blsp2_qup5_i2c_apps_clk.c, 0x006f }, + { &gcc_blsp2_qup6_spi_apps_clk.c, 0x0070 }, + { &gcc_blsp2_qup6_i2c_apps_clk.c, 0x0071 }, + { &gcc_pdm_ahb_clk.c, 0x0072 }, + { &gcc_pdm2_clk.c, 0x0074}, + { &gcc_prng_ahb_clk.c, 0x0075 }, + { &gcc_tsif_ahb_clk.c, 0x0076 }, + { &gcc_tsif_ref_clk.c, 0x0077 }, + { &gcc_boot_rom_ahb_clk.c, 0x007a }, + { &ce1_clk.c, 0x0097 }, + { &gcc_ce1_axi_m_clk.c, 0x0098 }, + { &gcc_ce1_ahb_m_clk.c, 0x0099 }, + { &measure_only_bimc_hmss_axi_clk.c, 0x00bb }, + { &gcc_bimc_gfx_clk.c, 0x00ac }, + { &gcc_hmss_rbcpr_clk.c, 0x00bc }, + { &gcc_gp1_clk.c, 0x00df }, + { &gcc_gp2_clk.c, 0x00e0 }, + { &gcc_gp3_clk.c, 0x00e1 }, + { &gcc_pcie_0_slv_axi_clk.c, 0x00e2 }, + { &gcc_pcie_0_mstr_axi_clk.c, 0x00e3 }, + { &gcc_pcie_0_cfg_ahb_clk.c, 0x00e4 }, + { &gcc_pcie_0_aux_clk.c, 0x00e5 }, + { &gcc_pcie_0_pipe_clk.c, 0x00e6 }, + { &gcc_pcie_phy_aux_clk.c, 0x00e8 }, + { &gcc_ufs_axi_clk.c, 0x00ea }, + { &gcc_ufs_ahb_clk.c, 0x00eb }, + { &gcc_ufs_tx_symbol_0_clk.c, 0x00ec }, + { &gcc_ufs_rx_symbol_0_clk.c, 0x00ed }, + { &gcc_ufs_rx_symbol_1_clk.c, 0x0162 }, + { &gcc_ufs_unipro_core_clk.c, 0x00f0 }, + { &gcc_ufs_ice_core_clk.c, 0x00f1 }, + { &gcc_dcc_ahb_clk.c, 0x0119 }, + { &ipa_clk.c, 0x011b }, + { &gcc_mss_cfg_ahb_clk.c, 0x011f }, + { &gcc_mss_q6_bimc_axi_clk.c, 0x0124 }, + { &gcc_mss_mnoc_bimc_axi_clk.c, 0x0120 }, + { &gcc_mss_snoc_axi_clk.c, 0x0123 }, + { &gcc_gpu_cfg_ahb_clk.c, 0x013b }, + { &gcc_gpu_bimc_gfx_clk.c, 0x013f }, + { &gcc_qspi_ahb_clk.c, 0x0156 }, + { &gcc_qspi_ref_clk.c, 0x0157 }, + ), + .c = { + .dbg_name = "gcc_debug_mux", + .ops = &clk_ops_debug_mux, + .flags = CLKFLAG_NO_RATE_CACHE | CLKFLAG_MEASURE, + CLK_INIT(gcc_debug_mux.c), + }, +}; + +static struct clk_lookup msm_clocks_rpm_8998[] = { + CLK_LIST(cxo_clk_src), + CLK_LIST(bimc_clk), + CLK_LIST(bimc_a_clk), + CLK_LIST(cnoc_clk), + CLK_LIST(cnoc_a_clk), + CLK_LIST(snoc_clk), + CLK_LIST(snoc_a_clk), + CLK_LIST(cnoc_periph_clk), + CLK_LIST(cnoc_periph_a_clk), + CLK_LIST(cnoc_periph_keepalive_a_clk), + CLK_LIST(bimc_msmbus_clk), + CLK_LIST(bimc_msmbus_a_clk), + CLK_LIST(ce1_clk), + CLK_LIST(ce1_a_clk), + CLK_LIST(cnoc_msmbus_clk), + CLK_LIST(cnoc_msmbus_a_clk), + CLK_LIST(cxo_clk_src_ao), + CLK_LIST(cxo_dwc3_clk), + CLK_LIST(cxo_lpm_clk), + CLK_LIST(cxo_otg_clk), + CLK_LIST(cxo_pil_lpass_clk), + CLK_LIST(cxo_pil_ssc_clk), + CLK_LIST(cxo_pil_spss_clk), + CLK_LIST(div_clk1), + CLK_LIST(div_clk1_ao), + CLK_LIST(div_clk2), + CLK_LIST(div_clk2_ao), + CLK_LIST(div_clk3), + CLK_LIST(div_clk3_ao), + CLK_LIST(ipa_clk), + CLK_LIST(ipa_a_clk), + CLK_LIST(ln_bb_clk1), + CLK_LIST(ln_bb_clk1_ao), + CLK_LIST(ln_bb_clk1_pin), + CLK_LIST(ln_bb_clk1_pin_ao), + CLK_LIST(ln_bb_clk2), + CLK_LIST(ln_bb_clk2_ao), + CLK_LIST(ln_bb_clk2_pin), + CLK_LIST(ln_bb_clk2_pin_ao), + CLK_LIST(ln_bb_clk3), + CLK_LIST(ln_bb_clk3_ao), + CLK_LIST(ln_bb_clk3_pin), + CLK_LIST(ln_bb_clk3_pin_ao), + CLK_LIST(mcd_ce1_clk), + CLK_LIST(measure_only_bimc_hmss_axi_clk), + CLK_LIST(mmssnoc_axi_clk), + CLK_LIST(mmssnoc_axi_a_clk), + CLK_LIST(aggre1_noc_clk), + CLK_LIST(aggre1_noc_a_clk), + CLK_LIST(aggre2_noc_clk), + CLK_LIST(aggre2_noc_a_clk), + CLK_LIST(qcedev_ce1_clk), + CLK_LIST(qcrypto_ce1_clk), + CLK_LIST(qdss_clk), + CLK_LIST(qdss_a_clk), + CLK_LIST(qseecom_ce1_clk), + CLK_LIST(rf_clk1), + CLK_LIST(rf_clk1_ao), + CLK_LIST(rf_clk1_pin), + CLK_LIST(rf_clk1_pin_ao), + CLK_LIST(rf_clk2), + CLK_LIST(rf_clk2_ao), + CLK_LIST(rf_clk2_pin), + CLK_LIST(rf_clk2_pin_ao), + CLK_LIST(rf_clk3), + CLK_LIST(rf_clk3_ao), + CLK_LIST(rf_clk3_pin), + CLK_LIST(rf_clk3_pin_ao), + CLK_LIST(scm_ce1_clk), + CLK_LIST(snoc_msmbus_clk), + CLK_LIST(snoc_msmbus_a_clk), + CLK_LIST(gcc_ce1_ahb_m_clk), + CLK_LIST(gcc_ce1_axi_m_clk), +}; + +static struct clk_lookup msm_clocks_gcc_8998[] = { + CLK_LIST(gpll0), + CLK_LIST(gpll0_ao), + CLK_LIST(gpll0_out_main), + CLK_LIST(gcc_mmss_gpll0_clk), + CLK_LIST(gcc_mmss_gpll0_div_clk), + CLK_LIST(gcc_gpu_gpll0_clk), + CLK_LIST(gcc_gpu_gpll0_div_clk), + CLK_LIST(gpll4), + CLK_LIST(gpll4_out_main), + CLK_LIST(usb30_master_clk_src), + CLK_LIST(pcie_aux_clk_src), + CLK_LIST(ufs_axi_clk_src), + CLK_LIST(blsp1_qup1_i2c_apps_clk_src), + CLK_LIST(blsp1_qup1_spi_apps_clk_src), + CLK_LIST(blsp1_qup2_i2c_apps_clk_src), + CLK_LIST(blsp1_qup2_spi_apps_clk_src), + CLK_LIST(blsp1_qup3_i2c_apps_clk_src), + CLK_LIST(blsp1_qup3_spi_apps_clk_src), + CLK_LIST(blsp1_qup4_i2c_apps_clk_src), + CLK_LIST(blsp1_qup4_spi_apps_clk_src), + CLK_LIST(blsp1_qup5_i2c_apps_clk_src), + CLK_LIST(blsp1_qup5_spi_apps_clk_src), + CLK_LIST(blsp1_qup6_i2c_apps_clk_src), + CLK_LIST(blsp1_qup6_spi_apps_clk_src), + CLK_LIST(blsp1_uart1_apps_clk_src), + CLK_LIST(blsp1_uart2_apps_clk_src), + CLK_LIST(blsp1_uart3_apps_clk_src), + CLK_LIST(blsp2_qup1_i2c_apps_clk_src), + CLK_LIST(blsp2_qup1_spi_apps_clk_src), + CLK_LIST(blsp2_qup2_i2c_apps_clk_src), + CLK_LIST(blsp2_qup2_spi_apps_clk_src), + CLK_LIST(blsp2_qup3_i2c_apps_clk_src), + CLK_LIST(blsp2_qup3_spi_apps_clk_src), + CLK_LIST(blsp2_qup4_i2c_apps_clk_src), + CLK_LIST(blsp2_qup4_spi_apps_clk_src), + CLK_LIST(blsp2_qup5_i2c_apps_clk_src), + CLK_LIST(blsp2_qup5_spi_apps_clk_src), + CLK_LIST(blsp2_qup6_i2c_apps_clk_src), + CLK_LIST(blsp2_qup6_spi_apps_clk_src), + CLK_LIST(blsp2_uart1_apps_clk_src), + CLK_LIST(blsp2_uart2_apps_clk_src), + CLK_LIST(blsp2_uart3_apps_clk_src), + CLK_LIST(gp1_clk_src), + CLK_LIST(gp2_clk_src), + CLK_LIST(gp3_clk_src), + CLK_LIST(hmss_rbcpr_clk_src), + CLK_LIST(pdm2_clk_src), + CLK_LIST(sdcc2_apps_clk_src), + CLK_LIST(sdcc4_apps_clk_src), + CLK_LIST(tsif_ref_clk_src), + CLK_LIST(ufs_ice_core_clk_src), + CLK_LIST(ufs_phy_aux_clk_src), + CLK_LIST(ufs_unipro_core_clk_src), + CLK_LIST(usb30_mock_utmi_clk_src), + CLK_LIST(usb3_phy_aux_clk_src), + CLK_LIST(hmss_gpll0_clk_src), + CLK_LIST(qspi_ref_clk_src), + CLK_LIST(gcc_usb3_phy_reset), + CLK_LIST(gcc_usb3phy_phy_reset), + CLK_LIST(gcc_qusb2phy_prim_reset), + CLK_LIST(gcc_qusb2phy_sec_reset), + CLK_LIST(gpll0_out_msscc), + CLK_LIST(gcc_aggre1_ufs_axi_clk), + CLK_LIST(gcc_aggre1_ufs_axi_hw_ctl_clk), + CLK_LIST(gcc_aggre1_usb3_axi_clk), + CLK_LIST(gcc_bimc_mss_q6_axi_clk), + CLK_LIST(gcc_blsp1_ahb_clk), + CLK_LIST(gcc_blsp1_qup1_i2c_apps_clk), + CLK_LIST(gcc_blsp1_qup1_spi_apps_clk), + CLK_LIST(gcc_blsp1_qup2_i2c_apps_clk), + CLK_LIST(gcc_blsp1_qup2_spi_apps_clk), + CLK_LIST(gcc_blsp1_qup3_i2c_apps_clk), + CLK_LIST(gcc_blsp1_qup3_spi_apps_clk), + CLK_LIST(gcc_blsp1_qup4_i2c_apps_clk), + CLK_LIST(gcc_blsp1_qup4_spi_apps_clk), + CLK_LIST(gcc_blsp1_qup5_i2c_apps_clk), + CLK_LIST(gcc_blsp1_qup5_spi_apps_clk), + CLK_LIST(gcc_blsp1_qup6_i2c_apps_clk), + CLK_LIST(gcc_blsp1_qup6_spi_apps_clk), + CLK_LIST(gcc_blsp1_uart1_apps_clk), + CLK_LIST(gcc_blsp1_uart2_apps_clk), + CLK_LIST(gcc_blsp1_uart3_apps_clk), + CLK_LIST(gcc_blsp2_ahb_clk), + CLK_LIST(gcc_blsp2_qup1_i2c_apps_clk), + CLK_LIST(gcc_blsp2_qup1_spi_apps_clk), + CLK_LIST(gcc_blsp2_qup2_i2c_apps_clk), + CLK_LIST(gcc_blsp2_qup2_spi_apps_clk), + CLK_LIST(gcc_blsp2_qup3_i2c_apps_clk), + CLK_LIST(gcc_blsp2_qup3_spi_apps_clk), + CLK_LIST(gcc_blsp2_qup4_i2c_apps_clk), + CLK_LIST(gcc_blsp2_qup4_spi_apps_clk), + CLK_LIST(gcc_blsp2_qup5_i2c_apps_clk), + CLK_LIST(gcc_blsp2_qup5_spi_apps_clk), + CLK_LIST(gcc_blsp2_qup6_i2c_apps_clk), + CLK_LIST(gcc_blsp2_qup6_spi_apps_clk), + CLK_LIST(gcc_blsp2_uart1_apps_clk), + CLK_LIST(gcc_blsp2_uart2_apps_clk), + CLK_LIST(gcc_blsp2_uart3_apps_clk), + CLK_LIST(gcc_cfg_noc_usb3_axi_clk), + CLK_LIST(gcc_bimc_gfx_clk), + CLK_LIST(gcc_gp1_clk), + CLK_LIST(gcc_gp2_clk), + CLK_LIST(gcc_gp3_clk), + CLK_LIST(gcc_gpu_bimc_gfx_clk), + CLK_LIST(gcc_gpu_cfg_ahb_clk), + CLK_LIST(gcc_gpu_iref_clk), + CLK_LIST(gcc_hmss_dvm_bus_clk), + CLK_LIST(gcc_hmss_rbcpr_clk), + CLK_LIST(gcc_mmss_noc_cfg_ahb_clk), + CLK_LIST(gcc_mmss_sys_noc_axi_clk), + CLK_LIST(gcc_pcie_0_aux_clk), + CLK_LIST(gcc_pcie_0_cfg_ahb_clk), + CLK_LIST(gcc_pcie_0_mstr_axi_clk), + CLK_LIST(gcc_pcie_0_pipe_clk), + CLK_LIST(gcc_pcie_0_slv_axi_clk), + CLK_LIST(gcc_pcie_phy_aux_clk), + CLK_LIST(gcc_pcie_phy_reset), + CLK_LIST(gcc_pcie_phy_com_reset), + CLK_LIST(gcc_pcie_phy_nocsr_com_phy_reset), + CLK_LIST(gcc_pdm2_clk), + CLK_LIST(gcc_pdm_ahb_clk), + CLK_LIST(gcc_sdcc2_ahb_clk), + CLK_LIST(gcc_sdcc2_apps_clk), + CLK_LIST(gcc_sdcc4_ahb_clk), + CLK_LIST(gcc_sdcc4_apps_clk), + CLK_LIST(gcc_tsif_ahb_clk), + CLK_LIST(gcc_tsif_ref_clk), + CLK_LIST(gcc_ufs_ahb_clk), + CLK_LIST(gcc_ufs_axi_clk), + CLK_LIST(gcc_ufs_axi_hw_ctl_clk), + CLK_LIST(gcc_ufs_ice_core_clk), + CLK_LIST(gcc_ufs_ice_core_hw_ctl_clk), + CLK_LIST(gcc_ufs_phy_aux_clk), + CLK_LIST(gcc_ufs_phy_aux_hw_ctl_clk), + CLK_LIST(gcc_ufs_rx_symbol_0_clk), + CLK_LIST(gcc_ufs_rx_symbol_1_clk), + CLK_LIST(gcc_ufs_tx_symbol_0_clk), + CLK_LIST(gcc_ufs_unipro_core_clk), + CLK_LIST(gcc_ufs_unipro_core_hw_ctl_clk), + CLK_LIST(gcc_usb30_master_clk), + CLK_LIST(gcc_usb30_mock_utmi_clk), + CLK_LIST(gcc_usb30_sleep_clk), + CLK_LIST(gcc_usb3_phy_aux_clk), + CLK_LIST(gcc_usb3_phy_pipe_clk), + CLK_LIST(gcc_prng_ahb_clk), + CLK_LIST(gcc_boot_rom_ahb_clk), + CLK_LIST(gcc_mss_cfg_ahb_clk), + CLK_LIST(gcc_mss_q6_bimc_axi_clk), + CLK_LIST(gcc_mss_mnoc_bimc_axi_clk), + CLK_LIST(gcc_mss_snoc_axi_clk), + CLK_LIST(gcc_hdmi_clkref_clk), + CLK_LIST(gcc_pcie_clkref_clk), + CLK_LIST(gcc_rx1_usb2_clkref_clk), + CLK_LIST(gcc_ufs_clkref_clk), + CLK_LIST(gcc_usb3_clkref_clk), + CLK_LIST(gcc_dcc_ahb_clk), + CLK_LIST(hlos1_vote_lpass_core_smmu_clk), + CLK_LIST(hlos1_vote_lpass_adsp_smmu_clk), + CLK_LIST(gcc_qspi_ahb_clk), + CLK_LIST(gcc_qspi_ref_clk), +}; + +static const struct msm_reset_map gcc_8998_resets[] = { + [QUSB2PHY_PRIM_BCR] = { 0x12000 }, + [QUSB2PHY_SEC_BCR] = { 0x12004 }, + [BLSP1_BCR] = { 0x17000 }, + [BLSP2_BCR] = { 0x25000 }, + [BOOT_ROM_BCR] = { 0x38000 }, + [PRNG_BCR] = { 0x34000 }, + [UFS_BCR] = { 0x75000 }, + [USB_30_BCR] = { 0x0f000 }, + [USB3_PHY_BCR] = { 0x50020 }, + [USB3PHY_PHY_BCR] = { 0x50024 }, + [PCIE_0_PHY_BCR] = { 0x6c01c }, + [PCIE_PHY_BCR] = { 0x6f000 }, + [PCIE_PHY_NOCSR_COM_PHY_BCR] = { 0x6f00C }, + [PCIE_PHY_COM_BCR] = { 0x6f014 }, +}; + +static void msm_gcc_8998_v1_fixup(void) +{ + gcc_ufs_rx_symbol_1_clk.c.ops = &clk_ops_dummy; + qspi_ref_clk_src.c.ops = &clk_ops_dummy; + gcc_qspi_ref_clk.c.ops = &clk_ops_dummy; + gcc_qspi_ahb_clk.c.ops = &clk_ops_dummy; +} + +static void msm_gcc_8998_v2_fixup(void) +{ + qspi_ref_clk_src.c.ops = &clk_ops_dummy; + gcc_qspi_ref_clk.c.ops = &clk_ops_dummy; + gcc_qspi_ahb_clk.c.ops = &clk_ops_dummy; +} + +static int msm_gcc_8998_probe(struct platform_device *pdev) +{ + struct resource *res; + u32 regval; + int ret; + bool is_v1 = 0, is_v2 = 0; + + ret = vote_bimc(&bimc_clk, INT_MAX); + if (ret < 0) + return ret; + + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cc_base"); + if (!res) { + dev_err(&pdev->dev, "Failed to get CC base\n"); + return -EINVAL; + } + + virt_base = devm_ioremap(&pdev->dev, res->start, resource_size(res)); + if (!virt_base) { + dev_err(&pdev->dev, "Failed to map in CC registers\n"); + return -ENOMEM; + } + + /* + * Clear the HMSS_AHB_CLK_ENA bit to allow the gcc_hmss_ahb_clk clock + * to be gated by RPM during VDD_MIN. + */ + regval = readl_relaxed(virt_base + GCC_APCS_CLOCK_BRANCH_ENA_VOTE); + regval &= ~BIT(21); + writel_relaxed(regval, virt_base + GCC_APCS_CLOCK_BRANCH_ENA_VOTE); + + vdd_dig.regulator[0] = devm_regulator_get(&pdev->dev, "vdd_dig"); + if (IS_ERR(vdd_dig.regulator[0])) { + if (!(PTR_ERR(vdd_dig.regulator[0]) == -EPROBE_DEFER)) + dev_err(&pdev->dev, + "Unable to get vdd_dig regulator\n"); + return PTR_ERR(vdd_dig.regulator[0]); + } + + vdd_dig_ao.regulator[0] = devm_regulator_get(&pdev->dev, "vdd_dig_ao"); + if (IS_ERR(vdd_dig_ao.regulator[0])) { + if (!(PTR_ERR(vdd_dig_ao.regulator[0]) == -EPROBE_DEFER)) + dev_err(&pdev->dev, + "Unable to get vdd_dig_ao regulator\n"); + return PTR_ERR(vdd_dig_ao.regulator[0]); + } + + bimc_clk.c.parent = &cxo_clk_src.c; + ret = of_msm_clock_register(pdev->dev.of_node, msm_clocks_rpm_8998, + ARRAY_SIZE(msm_clocks_rpm_8998)); + if (ret) + return ret; + + gpll0_early_div.c.rate = 300000000; + + ret = enable_rpm_scaling(); + if (ret < 0) + return ret; + + is_v1 = of_device_is_compatible(pdev->dev.of_node, "qcom,gcc-8998"); + if (is_v1) + msm_gcc_8998_v1_fixup(); + + is_v2 = of_device_is_compatible(pdev->dev.of_node, + "qcom,gcc-8998-v2"); + if (is_v2) + msm_gcc_8998_v2_fixup(); + + ret = of_msm_clock_register(pdev->dev.of_node, msm_clocks_gcc_8998, + ARRAY_SIZE(msm_clocks_gcc_8998)); + if (ret) + return ret; + + /* Disable the GPLL0 active input to MMSS and GPU via MISC registers */ + writel_relaxed(0x10003, virt_base + GCC_MMSS_MISC); + writel_relaxed(0x10003, virt_base + GCC_GPU_MISC); + + /* Hold an active set vote for the cnoc_periph resource */ + clk_set_rate(&cnoc_periph_keepalive_a_clk.c, 19200000); + clk_prepare_enable(&cnoc_periph_keepalive_a_clk.c); + + /* This clock is used for all MMSSCC register access */ + clk_prepare_enable(&gcc_mmss_noc_cfg_ahb_clk.c); + + /* Keep bimc gfx clock port on all the time */ + clk_prepare_enable(&gcc_bimc_gfx_clk.c); + + /* This clock is used for all GPUCC register access */ + clk_prepare_enable(&gcc_gpu_cfg_ahb_clk.c); + + /* Keep an active vote on CXO in case no other driver votes for it */ + clk_prepare_enable(&cxo_clk_src_ao.c); + + clk_set_flags(&gcc_gpu_bimc_gfx_clk.c, CLKFLAG_RETAIN_MEM); + + /* Register block resets */ + msm_reset_controller_register(pdev, gcc_8998_resets, + ARRAY_SIZE(gcc_8998_resets), virt_base); + + dev_info(&pdev->dev, "Registered GCC clocks\n"); + return 0; +} + +static struct of_device_id msm_clock_gcc_match_table[] = { + { .compatible = "qcom,gcc-8998" }, + { .compatible = "qcom,gcc-8998-v2" }, + { .compatible = "qcom,gcc-hamster" }, + {} +}; + +static struct platform_driver msm_clock_gcc_driver = { + .probe = msm_gcc_8998_probe, + .driver = { + .name = "qcom,gcc-8998", + .of_match_table = msm_clock_gcc_match_table, + .owner = THIS_MODULE, + }, +}; + +int __init msm_gcc_8998_init(void) +{ + return platform_driver_register(&msm_clock_gcc_driver); +} +arch_initcall(msm_gcc_8998_init); + +/* ======== Clock Debug Controller ======== */ +static struct clk_lookup msm_clocks_measure_8998[] = { + CLK_LIST(gpu_gcc_debug_clk), + CLK_LIST(gfx_gcc_debug_clk), + CLK_LIST(debug_mmss_clk), + CLK_LIST(debug_cpu_clk), + CLK_LOOKUP_OF("measure", gcc_debug_mux, "debug"), +}; + +static struct of_device_id msm_clock_debug_match_table[] = { + { .compatible = "qcom,cc-debug-8998" }, + {} +}; + +static int msm_clock_debug_8998_probe(struct platform_device *pdev) +{ + struct resource *res; + int ret; + + clk_ops_debug_mux = clk_ops_gen_mux; + clk_ops_debug_mux.get_rate = measure_get_rate; + + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cc_base"); + if (!res) { + dev_err(&pdev->dev, "Failed to get CC base\n"); + return -EINVAL; + } + virt_dbgbase = devm_ioremap(&pdev->dev, res->start, resource_size(res)); + if (!virt_dbgbase) { + dev_err(&pdev->dev, "Failed to map in CC registers\n"); + return -ENOMEM; + } + + gpu_gcc_debug_clk.dev = &pdev->dev; + gpu_gcc_debug_clk.clk_id = "debug_gpu_clk"; + + gfx_gcc_debug_clk.dev = &pdev->dev; + gfx_gcc_debug_clk.clk_id = "debug_gfx_clk"; + + debug_mmss_clk.dev = &pdev->dev; + debug_mmss_clk.clk_id = "debug_mmss_clk"; + + debug_cpu_clk.dev = &pdev->dev; + debug_cpu_clk.clk_id = "debug_cpu_clk"; + + ret = of_msm_clock_register(pdev->dev.of_node, + msm_clocks_measure_8998, + ARRAY_SIZE(msm_clocks_measure_8998)); + if (ret) + return ret; + + dev_info(&pdev->dev, "Registered debug mux\n"); + return ret; +} + +static struct platform_driver msm_clock_debug_driver = { + .probe = msm_clock_debug_8998_probe, + .driver = { + .name = "qcom,cc-debug-8998", + .of_match_table = msm_clock_debug_match_table, + .owner = THIS_MODULE, + }, +}; + +int __init msm_clock_debug_8998_init(void) +{ + return platform_driver_register(&msm_clock_debug_driver); +} +late_initcall(msm_clock_debug_8998_init); diff -Nruw linux-4.4.115-fbx/drivers/clk/msm./clock-generic.c linux-4.4.115-fbx/drivers/clk/msm/clock-generic.c --- linux-4.4.115-fbx/drivers/clk/msm./clock-generic.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-4.4.115-fbx/drivers/clk/msm/clock-generic.c 2019-01-22 16:16:23.015241987 +0100 @@ -0,0 +1,927 @@ +/* + * Copyright (c) 2013-2017, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +/* ==================== Mux clock ==================== */ + +static int mux_parent_to_src_sel(struct mux_clk *mux, struct clk *p) +{ + return parent_to_src_sel(mux->parents, mux->num_parents, p); +} + +static int mux_set_parent(struct clk *c, struct clk *p) +{ + struct mux_clk *mux = to_mux_clk(c); + int sel = mux_parent_to_src_sel(mux, p); + struct clk *old_parent; + int rc = 0, i; + unsigned long flags; + + if (sel < 0 && mux->rec_parents) { + for (i = 0; i < mux->num_rec_parents; i++) { + rc = clk_set_parent(mux->rec_parents[i], p); + if (!rc) { + /* + * This is necessary to ensure prepare/enable + * counts get propagated correctly. + */ + p = mux->rec_parents[i]; + sel = mux_parent_to_src_sel(mux, p); + break; + } + } + } + + if (sel < 0) + return sel; + + rc = __clk_pre_reparent(c, p, &flags); + if (rc) + goto out; + + rc = mux->ops->set_mux_sel(mux, sel); + if (rc) + goto set_fail; + + old_parent = c->parent; + c->parent = p; + c->rate = clk_get_rate(p); + __clk_post_reparent(c, old_parent, &flags); + + return 0; + +set_fail: + __clk_post_reparent(c, p, &flags); +out: + return rc; +} + +static long mux_round_rate(struct clk *c, unsigned long rate) +{ + struct mux_clk *mux = to_mux_clk(c); + int i; + unsigned long prate, rrate = 0; + + for (i = 0; i < mux->num_parents; i++) { + prate = clk_round_rate(mux->parents[i].src, rate); + if (is_better_rate(rate, rrate, prate)) + rrate = prate; + } + if (!rrate) + return -EINVAL; + + return rrate; +} + +static int mux_set_rate(struct clk *c, unsigned long rate) +{ + struct mux_clk *mux = to_mux_clk(c); + struct clk *new_parent = NULL; + int rc = 0, i; + unsigned long new_par_curr_rate; + unsigned long flags; + + /* + * Check if one of the possible parents is already at the requested + * rate. + */ + for (i = 0; i < mux->num_parents && mux->try_get_rate; i++) { + struct clk *p = mux->parents[i].src; + if (p->rate == rate && clk_round_rate(p, rate) == rate) { + new_parent = mux->parents[i].src; + break; + } + } + + for (i = 0; i < mux->num_parents && !(!i && new_parent); i++) { + if (clk_round_rate(mux->parents[i].src, rate) == rate) { + new_parent = mux->parents[i].src; + if (!mux->try_new_parent) + break; + if (mux->try_new_parent && new_parent != c->parent) + break; + } + } + + if (new_parent == NULL) + return -EINVAL; + + /* + * Switch to safe parent since the old and new parent might be the + * same and the parent might temporarily turn off while switching + * rates. If the mux can switch between distinct sources safely + * (indicated by try_new_parent), and the new source is not the current + * parent, do not switch to the safe parent. + */ + if (mux->safe_sel >= 0 && + !(mux->try_new_parent && (new_parent != c->parent))) { + /* + * The safe parent might be a clock with multiple sources; + * to select the "safe" source, set a safe frequency. + */ + if (mux->safe_freq) { + rc = clk_set_rate(mux->safe_parent, mux->safe_freq); + if (rc) { + pr_err("Failed to set safe rate on %s\n", + clk_name(mux->safe_parent)); + return rc; + } + } + + /* + * Some mux implementations might switch to/from a low power + * parent as part of their disable/enable ops. Grab the + * enable lock to avoid racing with these implementations. + */ + spin_lock_irqsave(&c->lock, flags); + rc = mux->ops->set_mux_sel(mux, mux->safe_sel); + spin_unlock_irqrestore(&c->lock, flags); + if (rc) + return rc; + + } + + new_par_curr_rate = clk_get_rate(new_parent); + rc = clk_set_rate(new_parent, rate); + if (rc) + goto set_rate_fail; + + rc = mux_set_parent(c, new_parent); + if (rc) + goto set_par_fail; + + return 0; + +set_par_fail: + clk_set_rate(new_parent, new_par_curr_rate); +set_rate_fail: + WARN(mux->ops->set_mux_sel(mux, + mux_parent_to_src_sel(mux, c->parent)), + "Set rate failed for %s. Also in bad state!\n", c->dbg_name); + return rc; +} + +static int mux_enable(struct clk *c) +{ + struct mux_clk *mux = to_mux_clk(c); + if (mux->ops->enable) + return mux->ops->enable(mux); + return 0; +} + +static void mux_disable(struct clk *c) +{ + struct mux_clk *mux = to_mux_clk(c); + if (mux->ops->disable) + return mux->ops->disable(mux); +} + +static struct clk *mux_get_parent(struct clk *c) +{ + struct mux_clk *mux = to_mux_clk(c); + int sel = mux->ops->get_mux_sel(mux); + int i; + + for (i = 0; i < mux->num_parents; i++) { + if (mux->parents[i].sel == sel) + return mux->parents[i].src; + } + + /* Unfamiliar parent. */ + return NULL; +} + +static enum handoff mux_handoff(struct clk *c) +{ + struct mux_clk *mux = to_mux_clk(c); + + c->rate = clk_get_rate(c->parent); + mux->safe_sel = mux_parent_to_src_sel(mux, mux->safe_parent); + + if (mux->en_mask && mux->ops && mux->ops->is_enabled) + return mux->ops->is_enabled(mux) + ? HANDOFF_ENABLED_CLK + : HANDOFF_DISABLED_CLK; + + /* + * If this function returns 'enabled' even when the clock downstream + * of this clock is disabled, then handoff code will unnecessarily + * enable the current parent of this clock. If this function always + * returns 'disabled' and a clock downstream is on, the clock handoff + * code will bump up the ref count for this clock and its current + * parent as necessary. So, clocks without an actual HW gate can + * always return disabled. + */ + return HANDOFF_DISABLED_CLK; +} + +static void __iomem *mux_clk_list_registers(struct clk *c, int n, + struct clk_register_data **regs, u32 *size) +{ + struct mux_clk *mux = to_mux_clk(c); + + if (mux->ops && mux->ops->list_registers) + return mux->ops->list_registers(mux, n, regs, size); + + return ERR_PTR(-EINVAL); +} + +struct clk_ops clk_ops_gen_mux = { + .enable = mux_enable, + .disable = mux_disable, + .set_parent = mux_set_parent, + .round_rate = mux_round_rate, + .set_rate = mux_set_rate, + .handoff = mux_handoff, + .get_parent = mux_get_parent, + .list_registers = mux_clk_list_registers, +}; + +/* ==================== Divider clock ==================== */ + +static long __div_round_rate(struct div_data *data, unsigned long rate, + struct clk *parent, unsigned int *best_div, unsigned long *best_prate) +{ + unsigned int div, min_div, max_div, _best_div = 1; + unsigned long prate, _best_prate = 0, rrate = 0, req_prate, actual_rate; + unsigned int numer; + + rate = max(rate, 1UL); + + min_div = max(data->min_div, 1U); + max_div = min(data->max_div, (unsigned int) (ULONG_MAX)); + + /* + * div values are doubled for half dividers. + * Adjust for that by picking a numer of 2. + */ + numer = data->is_half_divider ? 2 : 1; + + for (div = min_div; div <= max_div; div++) { + if (data->skip_odd_div && (div & 1)) + if (!(data->allow_div_one && (div == 1))) + continue; + if (data->skip_even_div && !(div & 1)) + continue; + req_prate = mult_frac(rate, div, numer); + prate = clk_round_rate(parent, req_prate); + if (IS_ERR_VALUE(prate)) + break; + + actual_rate = mult_frac(prate, numer, div); + if (is_better_rate(rate, rrate, actual_rate)) { + rrate = actual_rate; + _best_div = div; + _best_prate = prate; + } + + /* + * Trying higher dividers is only going to ask the parent for + * a higher rate. If it can't even output a rate higher than + * the one we request for this divider, the parent is not + * going to be able to output an even higher rate required + * for a higher divider. So, stop trying higher dividers. + */ + if (actual_rate < rate) + break; + + if (rrate <= rate + data->rate_margin) + break; + } + + if (!rrate) + return -EINVAL; + if (best_div) + *best_div = _best_div; + if (best_prate) + *best_prate = _best_prate; + + return rrate; +} + +static long div_round_rate(struct clk *c, unsigned long rate) +{ + struct div_clk *d = to_div_clk(c); + + return __div_round_rate(&d->data, rate, c->parent, NULL, NULL); +} + +static int _find_safe_div(struct clk *c, unsigned long rate) +{ + struct div_clk *d = to_div_clk(c); + struct div_data *data = &d->data; + unsigned long fast = max(rate, c->rate); + unsigned int numer = data->is_half_divider ? 2 : 1; + int i, safe_div = 0; + + if (!d->safe_freq) + return 0; + + /* Find the max safe freq that is lesser than fast */ + for (i = data->max_div; i >= data->min_div; i--) + if (mult_frac(d->safe_freq, numer, i) <= fast) + safe_div = i; + + return safe_div ?: -EINVAL; +} + +static int div_set_rate(struct clk *c, unsigned long rate) +{ + struct div_clk *d = to_div_clk(c); + int safe_div, div, rc = 0; + long rrate, old_prate, new_prate; + struct div_data *data = &d->data; + + rrate = __div_round_rate(data, rate, c->parent, &div, &new_prate); + if (rrate < rate || rrate > rate + data->rate_margin) + return -EINVAL; + + /* + * For fixed divider clock we don't want to return an error if the + * requested rate matches the achievable rate. So, don't check for + * !d->ops and return an error. __div_round_rate() ensures div == + * d->div if !d->ops. + */ + + safe_div = _find_safe_div(c, rate); + if (d->safe_freq && safe_div < 0) { + pr_err("No safe div on %s for transitioning from %lu to %lu\n", + c->dbg_name, c->rate, rate); + return -EINVAL; + } + + safe_div = max(safe_div, div); + + if (safe_div > data->div) { + rc = d->ops->set_div(d, safe_div); + if (rc) { + pr_err("Failed to set div %d on %s\n", safe_div, + c->dbg_name); + return rc; + } + } + + old_prate = clk_get_rate(c->parent); + rc = clk_set_rate(c->parent, new_prate); + if (rc) + goto set_rate_fail; + + if (div < data->div) + rc = d->ops->set_div(d, div); + else if (div < safe_div) + rc = d->ops->set_div(d, div); + if (rc) + goto div_dec_fail; + + data->div = div; + + return 0; + +div_dec_fail: + WARN(clk_set_rate(c->parent, old_prate), + "Set rate failed for %s. Also in bad state!\n", c->dbg_name); +set_rate_fail: + if (safe_div > data->div) + WARN(d->ops->set_div(d, data->div), + "Set rate failed for %s. Also in bad state!\n", + c->dbg_name); + return rc; +} + +static int div_enable(struct clk *c) +{ + struct div_clk *d = to_div_clk(c); + if (d->ops && d->ops->enable) + return d->ops->enable(d); + return 0; +} + +static void div_disable(struct clk *c) +{ + struct div_clk *d = to_div_clk(c); + if (d->ops && d->ops->disable) + return d->ops->disable(d); +} + +static enum handoff div_handoff(struct clk *c) +{ + struct div_clk *d = to_div_clk(c); + unsigned int div = d->data.div; + + if (d->ops && d->ops->get_div) + div = max(d->ops->get_div(d), 1); + div = max(div, 1U); + c->rate = clk_get_rate(c->parent) / div; + + if (!d->ops || !d->ops->set_div) + d->data.min_div = d->data.max_div = div; + d->data.div = div; + + if (d->en_mask && d->ops && d->ops->is_enabled) + return d->ops->is_enabled(d) + ? HANDOFF_ENABLED_CLK + : HANDOFF_DISABLED_CLK; + + /* + * If this function returns 'enabled' even when the clock downstream + * of this clock is disabled, then handoff code will unnecessarily + * enable the current parent of this clock. If this function always + * returns 'disabled' and a clock downstream is on, the clock handoff + * code will bump up the ref count for this clock and its current + * parent as necessary. So, clocks without an actual HW gate can + * always return disabled. + */ + return HANDOFF_DISABLED_CLK; +} + +static void __iomem *div_clk_list_registers(struct clk *c, int n, + struct clk_register_data **regs, u32 *size) +{ + struct div_clk *d = to_div_clk(c); + + if (d->ops && d->ops->list_registers) + return d->ops->list_registers(d, n, regs, size); + + return ERR_PTR(-EINVAL); +} + +struct clk_ops clk_ops_div = { + .enable = div_enable, + .disable = div_disable, + .round_rate = div_round_rate, + .set_rate = div_set_rate, + .handoff = div_handoff, + .list_registers = div_clk_list_registers, +}; + +static long __slave_div_round_rate(struct clk *c, unsigned long rate, + int *best_div) +{ + struct div_clk *d = to_div_clk(c); + unsigned int div, min_div, max_div; + long p_rate; + + rate = max(rate, 1UL); + + min_div = d->data.min_div; + max_div = d->data.max_div; + + p_rate = clk_get_rate(c->parent); + div = DIV_ROUND_CLOSEST(p_rate, rate); + div = max(div, min_div); + div = min(div, max_div); + if (best_div) + *best_div = div; + + if (d->data.is_half_divider) + p_rate *= 2; + + return p_rate / div; +} + +static long slave_div_round_rate(struct clk *c, unsigned long rate) +{ + return __slave_div_round_rate(c, rate, NULL); +} + +static int slave_div_set_rate(struct clk *c, unsigned long rate) +{ + struct div_clk *d = to_div_clk(c); + int div, rc = 0; + long rrate; + + rrate = __slave_div_round_rate(c, rate, &div); + if (rrate != rate) + return -EINVAL; + + if (div == d->data.div) + return 0; + + /* + * For fixed divider clock we don't want to return an error if the + * requested rate matches the achievable rate. So, don't check for + * !d->ops and return an error. __slave_div_round_rate() ensures + * div == d->data.div if !d->ops. + */ + rc = d->ops->set_div(d, div); + if (rc) + return rc; + + d->data.div = div; + + return 0; +} + +static unsigned long slave_div_get_rate(struct clk *c) +{ + struct div_clk *d = to_div_clk(c); + unsigned long rate; + + if (!d->data.div) + return 0; + + rate = clk_get_rate(c->parent) / d->data.div; + if (d->data.is_half_divider) + rate *= 2; + + return rate; +} + +struct clk_ops clk_ops_slave_div = { + .enable = div_enable, + .disable = div_disable, + .round_rate = slave_div_round_rate, + .set_rate = slave_div_set_rate, + .get_rate = slave_div_get_rate, + .handoff = div_handoff, + .list_registers = div_clk_list_registers, +}; + + +/** + * External clock + * Some clock controllers have input clock signal that come from outside the + * clock controller. That input clock signal might then be used as a source for + * several clocks inside the clock controller. This external clock + * implementation models this input clock signal by just passing on the requests + * to the clock's parent, the original external clock source. The driver for the + * clock controller should clk_get() the original external clock in the probe + * function and set is as a parent to this external clock.. + */ + +long parent_round_rate(struct clk *c, unsigned long rate) +{ + return clk_round_rate(c->parent, rate); +} + +int parent_set_rate(struct clk *c, unsigned long rate) +{ + return clk_set_rate(c->parent, rate); +} + +unsigned long parent_get_rate(struct clk *c) +{ + return clk_get_rate(c->parent); +} + +static int ext_set_parent(struct clk *c, struct clk *p) +{ + return clk_set_parent(c->parent, p); +} + +static struct clk *ext_get_parent(struct clk *c) +{ + struct ext_clk *ext = to_ext_clk(c); + + if (!IS_ERR_OR_NULL(c->parent)) + return c->parent; + return clk_get(ext->dev, ext->clk_id); +} + +static enum handoff ext_handoff(struct clk *c) +{ + c->rate = clk_get_rate(c->parent); + /* Similar reasoning applied in div_handoff, see comment there. */ + return HANDOFF_DISABLED_CLK; +} + +struct clk_ops clk_ops_ext = { + .handoff = ext_handoff, + .round_rate = parent_round_rate, + .set_rate = parent_set_rate, + .get_rate = parent_get_rate, + .set_parent = ext_set_parent, + .get_parent = ext_get_parent, +}; + +static void *ext_clk_dt_parser(struct device *dev, struct device_node *np) +{ + struct ext_clk *ext; + const char *str; + int rc; + + ext = devm_kzalloc(dev, sizeof(*ext), GFP_KERNEL); + if (!ext) { + dev_err(dev, "memory allocation failure\n"); + return ERR_PTR(-ENOMEM); + } + + ext->dev = dev; + rc = of_property_read_string(np, "qcom,clock-names", &str); + if (!rc) + ext->clk_id = (void *)str; + + ext->c.ops = &clk_ops_ext; + return msmclk_generic_clk_init(dev, np, &ext->c); +} +MSMCLK_PARSER(ext_clk_dt_parser, "qcom,ext-clk", 0); + +/* ==================== Mux_div clock ==================== */ + +static int mux_div_clk_enable(struct clk *c) +{ + struct mux_div_clk *md = to_mux_div_clk(c); + + if (md->ops->enable) + return md->ops->enable(md); + return 0; +} + +static void mux_div_clk_disable(struct clk *c) +{ + struct mux_div_clk *md = to_mux_div_clk(c); + + if (md->ops->disable) + return md->ops->disable(md); +} + +static long __mux_div_round_rate(struct clk *c, unsigned long rate, + struct clk **best_parent, int *best_div, unsigned long *best_prate) +{ + struct mux_div_clk *md = to_mux_div_clk(c); + unsigned int i; + unsigned long rrate, best = 0, _best_div = 0, _best_prate = 0; + struct clk *_best_parent = 0; + + if (md->try_get_rate) { + for (i = 0; i < md->num_parents; i++) { + int divider; + unsigned long p_rate; + + rrate = __div_round_rate(&md->data, rate, + md->parents[i].src, + ÷r, &p_rate); + /* + * Check if one of the possible parents is already at + * the requested rate. + */ + if (p_rate == clk_get_rate(md->parents[i].src) + && rrate == rate) { + best = rrate; + _best_div = divider; + _best_prate = p_rate; + _best_parent = md->parents[i].src; + goto end; + } + } + } + + for (i = 0; i < md->num_parents; i++) { + int div; + unsigned long prate; + + rrate = __div_round_rate(&md->data, rate, md->parents[i].src, + &div, &prate); + + if (is_better_rate(rate, best, rrate)) { + best = rrate; + _best_div = div; + _best_prate = prate; + _best_parent = md->parents[i].src; + } + + if (rate <= rrate && rrate <= rate + md->data.rate_margin) + break; + } +end: + if (best_div) + *best_div = _best_div; + if (best_prate) + *best_prate = _best_prate; + if (best_parent) + *best_parent = _best_parent; + + if (best) + return best; + return -EINVAL; +} + +static long mux_div_clk_round_rate(struct clk *c, unsigned long rate) +{ + return __mux_div_round_rate(c, rate, NULL, NULL, NULL); +} + +/* requires enable lock to be held */ +static int __set_src_div(struct mux_div_clk *md, struct clk *parent, u32 div) +{ + u32 rc = 0, src_sel; + + src_sel = parent_to_src_sel(md->parents, md->num_parents, parent); + /* + * If the clock is disabled, don't change to the new settings until + * the clock is reenabled + */ + if (md->c.count) + rc = md->ops->set_src_div(md, src_sel, div); + if (!rc) { + md->data.div = div; + md->src_sel = src_sel; + } + + return rc; +} + +static int set_src_div(struct mux_div_clk *md, struct clk *parent, u32 div) +{ + unsigned long flags; + u32 rc; + + spin_lock_irqsave(&md->c.lock, flags); + rc = __set_src_div(md, parent, div); + spin_unlock_irqrestore(&md->c.lock, flags); + + return rc; +} + +/* Must be called after handoff to ensure parent clock rates are initialized */ +static int safe_parent_init_once(struct clk *c) +{ + unsigned long rrate; + u32 best_div; + struct clk *best_parent; + struct mux_div_clk *md = to_mux_div_clk(c); + + if (IS_ERR(md->safe_parent)) + return -EINVAL; + if (!md->safe_freq || md->safe_parent) + return 0; + + rrate = __mux_div_round_rate(c, md->safe_freq, &best_parent, + &best_div, NULL); + + if (rrate == md->safe_freq) { + md->safe_div = best_div; + md->safe_parent = best_parent; + } else { + md->safe_parent = ERR_PTR(-EINVAL); + return -EINVAL; + } + return 0; +} + +static int mux_div_clk_set_rate(struct clk *c, unsigned long rate) +{ + struct mux_div_clk *md = to_mux_div_clk(c); + unsigned long flags, rrate; + unsigned long new_prate, new_parent_orig_rate; + struct clk *old_parent, *new_parent; + u32 new_div, old_div; + int rc; + + rc = safe_parent_init_once(c); + if (rc) + return rc; + + rrate = __mux_div_round_rate(c, rate, &new_parent, &new_div, + &new_prate); + if (rrate < rate || rrate > rate + md->data.rate_margin) + return -EINVAL; + + old_parent = c->parent; + old_div = md->data.div; + + /* Refer to the description of safe_freq in clock-generic.h */ + if (md->safe_freq) + rc = set_src_div(md, md->safe_parent, md->safe_div); + + else if (new_parent == old_parent && new_div >= old_div) { + /* + * If both the parent_rate and divider changes, there may be an + * intermediate frequency generated. Ensure this intermediate + * frequency is less than both the new rate and previous rate. + */ + rc = set_src_div(md, old_parent, new_div); + } + if (rc) + return rc; + + new_parent_orig_rate = clk_get_rate(new_parent); + rc = clk_set_rate(new_parent, new_prate); + if (rc) { + pr_err("failed to set %s to %ld\n", + clk_name(new_parent), new_prate); + goto err_set_rate; + } + + rc = __clk_pre_reparent(c, new_parent, &flags); + if (rc) + goto err_pre_reparent; + + /* Set divider and mux src atomically */ + rc = __set_src_div(md, new_parent, new_div); + if (rc) + goto err_set_src_div; + + c->parent = new_parent; + + __clk_post_reparent(c, old_parent, &flags); + return 0; + +err_set_src_div: + /* Not switching to new_parent, so disable it */ + __clk_post_reparent(c, new_parent, &flags); +err_pre_reparent: + rc = clk_set_rate(new_parent, new_parent_orig_rate); + WARN(rc, "%s: error changing new_parent (%s) rate back to %ld\n", + clk_name(c), clk_name(new_parent), new_parent_orig_rate); +err_set_rate: + rc = set_src_div(md, old_parent, old_div); + WARN(rc, "%s: error changing back to original div (%d) and parent (%s)\n", + clk_name(c), old_div, clk_name(old_parent)); + + return rc; +} + +static struct clk *mux_div_clk_get_parent(struct clk *c) +{ + struct mux_div_clk *md = to_mux_div_clk(c); + u32 i, div, src_sel; + + md->ops->get_src_div(md, &src_sel, &div); + + md->data.div = div; + md->src_sel = src_sel; + + for (i = 0; i < md->num_parents; i++) { + if (md->parents[i].sel == src_sel) + return md->parents[i].src; + } + + return NULL; +} + +static enum handoff mux_div_clk_handoff(struct clk *c) +{ + struct mux_div_clk *md = to_mux_div_clk(c); + unsigned long parent_rate; + unsigned int numer; + + parent_rate = clk_get_rate(c->parent); + /* + * div values are doubled for half dividers. + * Adjust for that by picking a numer of 2. + */ + numer = md->data.is_half_divider ? 2 : 1; + + if (md->data.div) { + c->rate = mult_frac(parent_rate, numer, md->data.div); + } else { + c->rate = 0; + return HANDOFF_DISABLED_CLK; + } + + if (md->en_mask && md->ops && md->ops->is_enabled) + return md->ops->is_enabled(md) + ? HANDOFF_ENABLED_CLK + : HANDOFF_DISABLED_CLK; + + /* + * If this function returns 'enabled' even when the clock downstream + * of this clock is disabled, then handoff code will unnecessarily + * enable the current parent of this clock. If this function always + * returns 'disabled' and a clock downstream is on, the clock handoff + * code will bump up the ref count for this clock and its current + * parent as necessary. So, clocks without an actual HW gate can + * always return disabled. + */ + return HANDOFF_DISABLED_CLK; +} + +static void __iomem *mux_div_clk_list_registers(struct clk *c, int n, + struct clk_register_data **regs, u32 *size) +{ + struct mux_div_clk *md = to_mux_div_clk(c); + + if (md->ops && md->ops->list_registers) + return md->ops->list_registers(md, n , regs, size); + + return ERR_PTR(-EINVAL); +} + +struct clk_ops clk_ops_mux_div_clk = { + .enable = mux_div_clk_enable, + .disable = mux_div_clk_disable, + .set_rate = mux_div_clk_set_rate, + .round_rate = mux_div_clk_round_rate, + .get_parent = mux_div_clk_get_parent, + .handoff = mux_div_clk_handoff, + .list_registers = mux_div_clk_list_registers, +}; diff -Nruw linux-4.4.115-fbx/drivers/clk/msm./clock-gpu-8998.c linux-4.4.115-fbx/drivers/clk/msm/clock-gpu-8998.c --- linux-4.4.115-fbx/drivers/clk/msm./clock-gpu-8998.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-4.4.115-fbx/drivers/clk/msm/clock-gpu-8998.c 2019-01-22 16:16:23.015241987 +0100 @@ -0,0 +1,734 @@ +/* Copyright (c) 2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include +#include + +#include "vdd-level-8998.h" + +static void __iomem *virt_base; +static void __iomem *virt_base_gfx; + +#define gpucc_cxo_clk_source_val 0 +#define gpucc_gpll0_source_val 5 +#define gpu_pll0_pll_out_even_source_val 1 +#define gpu_pll0_pll_out_odd_source_val 2 + +#define SW_COLLAPSE_MASK BIT(0) +#define GPU_CX_GDSCR_OFFSET 0x1004 +#define GPU_GX_GDSCR_OFFSET 0x1094 +#define CRC_SID_FSM_OFFSET 0x10A0 +#define CRC_MND_CFG_OFFSET 0x10A4 + +#define F(f, s, div, m, n) \ + { \ + .freq_hz = (f), \ + .src_clk = &s.c, \ + .m_val = (m), \ + .n_val = ~((n)-(m)) * !!(n), \ + .d_val = ~(n),\ + .div_src_val = BVAL(4, 0, (int)(2*(div) - 1)) \ + | BVAL(10, 8, s##_source_val), \ + } + +#define F_SLEW(f, s_f, s, div, m, n) \ + { \ + .freq_hz = (f), \ + .src_freq = (s_f), \ + .src_clk = &s.c, \ + .m_val = (m), \ + .n_val = ~((n)-(m)) * !!(n), \ + .d_val = ~(n),\ + .div_src_val = BVAL(4, 0, (int)(2*(div) - 1)) \ + | BVAL(10, 8, s##_source_val), \ + } + +static struct alpha_pll_masks pll_masks_p = { + .lock_mask = BIT(31), + .active_mask = BIT(30), + .update_mask = BIT(22), + .output_mask = 0xf, + .post_div_mask = BM(15, 8), +}; + +static DEFINE_VDD_REGULATORS(vdd_dig, VDD_DIG_NUM, 1, vdd_corner, NULL); +DEFINE_VDD_REGS_INIT(vdd_gpucc, 2); +DEFINE_VDD_REGS_INIT(vdd_gpucc_mx, 1); + +DEFINE_EXT_CLK(gpucc_xo, NULL); +DEFINE_EXT_CLK(gpucc_gpll0, NULL); + +static struct branch_clk gpucc_cxo_clk = { + .cbcr_reg = GPUCC_CXO_CBCR, + .has_sibling = 1, + .base = &virt_base, + .c = { + .dbg_name = "gpucc_cxo_clk", + .parent = &gpucc_xo.c, + .ops = &clk_ops_branch, + CLK_INIT(gpucc_cxo_clk.c), + }, +}; + +static struct alpha_pll_clk gpu_pll0_pll = { + .masks = &pll_masks_p, + .base = &virt_base_gfx, + .offset = GPUCC_GPU_PLL0_PLL_MODE, + .enable_config = 0x1, + .is_fabia = true, + .c = { + .rate = 0, + .parent = &gpucc_xo.c, + .dbg_name = "gpu_pll0_pll", + .ops = &clk_ops_fabia_alpha_pll, + VDD_GPU_PLL_FMAX_MAP1(MIN, 1300000500), + CLK_INIT(gpu_pll0_pll.c), + }, +}; + +static struct div_clk gpu_pll0_pll_out_even = { + .base = &virt_base_gfx, + .offset = GPUCC_GPU_PLL0_USER_CTL_MODE, + .mask = 0xf, + .shift = 8, + .data = { + .max_div = 8, + .min_div = 1, + .skip_odd_div = true, + .allow_div_one = true, + .rate_margin = 500, + }, + .ops = &postdiv_reg_ops, + .c = { + .parent = &gpu_pll0_pll.c, + .dbg_name = "gpu_pll0_pll_out_even", + .ops = &clk_ops_div, + .flags = CLKFLAG_NO_RATE_CACHE, + CLK_INIT(gpu_pll0_pll_out_even.c), + }, +}; + +static struct div_clk gpu_pll0_pll_out_odd = { + .base = &virt_base_gfx, + .offset = GPUCC_GPU_PLL0_USER_CTL_MODE, + .mask = 0xf, + .shift = 12, + .data = { + .max_div = 7, + .min_div = 3, + .skip_even_div = true, + .rate_margin = 500, + }, + .ops = &postdiv_reg_ops, + .c = { + .parent = &gpu_pll0_pll.c, + .dbg_name = "gpu_pll0_pll_out_odd", + .ops = &clk_ops_div, + .flags = CLKFLAG_NO_RATE_CACHE, + CLK_INIT(gpu_pll0_pll_out_odd.c), + }, +}; + +static struct clk_freq_tbl ftbl_gfx3d_clk_src[] = { + F_SLEW( 171000000, 342000000, gpu_pll0_pll_out_even, 1, 0, 0), + F_SLEW( 251000000, 502000000, gpu_pll0_pll_out_even, 1, 0, 0), + F_SLEW( 332000000, 664000000, gpu_pll0_pll_out_even, 1, 0, 0), + F_SLEW( 403000000, 806000000, gpu_pll0_pll_out_even, 1, 0, 0), + F_SLEW( 504000000, 1008000000, gpu_pll0_pll_out_even, 1, 0, 0), + F_SLEW( 650000000, 1300000000, gpu_pll0_pll_out_even, 1, 0, 0), + F_END +}; + +static struct clk_freq_tbl ftbl_gfx3d_clk_src_v2[] = { + F_SLEW( 180000000, 360000000, gpu_pll0_pll_out_even, 1, 0, 0), + F_SLEW( 257000000, 514000000, gpu_pll0_pll_out_even, 1, 0, 0), + F_SLEW( 342000000, 684000000, gpu_pll0_pll_out_even, 1, 0, 0), + F_SLEW( 414000000, 828000000, gpu_pll0_pll_out_even, 1, 0, 0), + F_SLEW( 515000000, 1030000000, gpu_pll0_pll_out_even, 1, 0, 0), + F_SLEW( 596000000, 1192000000, gpu_pll0_pll_out_even, 1, 0, 0), + F_SLEW( 670000000, 1340000000, gpu_pll0_pll_out_even, 1, 0, 0), + F_SLEW( 710000000, 1420000000, gpu_pll0_pll_out_even, 1, 0, 0), + F_END +}; + +static struct clk_freq_tbl ftbl_gfx3d_clk_src_vq[] = { + F_SLEW( 180000000, 360000000, gpu_pll0_pll_out_even, 1, 0, 0), + F_SLEW( 265000000, 530000000, gpu_pll0_pll_out_even, 1, 0, 0), + F_SLEW( 358000000, 716000000, gpu_pll0_pll_out_even, 1, 0, 0), + F_SLEW( 434000000, 868000000, gpu_pll0_pll_out_even, 1, 0, 0), + F_SLEW( 542000000, 1084000000, gpu_pll0_pll_out_even, 1, 0, 0), + F_SLEW( 630000000, 1260000000, gpu_pll0_pll_out_even, 1, 0, 0), + F_SLEW( 700000000, 1400000000, gpu_pll0_pll_out_even, 1, 0, 0), + F_SLEW( 750000000, 1500000000, gpu_pll0_pll_out_even, 1, 0, 0), + F_END +}; + +static struct rcg_clk gfx3d_clk_src = { + .cmd_rcgr_reg = GPUCC_GFX3D_CMD_RCGR, + .set_rate = set_rate_hid, + .freq_tbl = ftbl_gfx3d_clk_src, + .current_freq = &rcg_dummy_freq, + .force_enable_rcgr = true, + .base = &virt_base_gfx, + .c = { + .dbg_name = "gfx3d_clk_src", + .ops = &clk_ops_rcg, + .vdd_class = &vdd_gpucc, + CLK_INIT(gfx3d_clk_src.c), + }, +}; + +static struct clk_freq_tbl ftbl_rbbmtimer_clk_src[] = { + F( 19200000, gpucc_cxo_clk, 1, 0, 0), + F_END +}; + +static struct rcg_clk rbbmtimer_clk_src = { + .cmd_rcgr_reg = GPUCC_RBBMTIMER_CMD_RCGR, + .set_rate = set_rate_hid, + .freq_tbl = ftbl_rbbmtimer_clk_src, + .current_freq = &rcg_dummy_freq, + .base = &virt_base, + .c = { + .dbg_name = "rbbmtimer_clk_src", + .ops = &clk_ops_rcg, + VDD_DIG_FMAX_MAP1(MIN, 19200000), + CLK_INIT(rbbmtimer_clk_src.c), + }, +}; + +static struct clk_freq_tbl ftbl_gfx3d_isense_clk_src[] = { + F( 19200000, gpucc_cxo_clk, 1, 0, 0), + F( 40000000, gpucc_gpll0, 15, 0, 0), + F( 200000000, gpucc_gpll0, 3, 0, 0), + F( 300000000, gpucc_gpll0, 2, 0, 0), + F_END +}; + +static struct rcg_clk gfx3d_isense_clk_src = { + .cmd_rcgr_reg = GPUCC_GFX3D_ISENSE_CMD_RCGR, + .set_rate = set_rate_hid, + .freq_tbl = ftbl_gfx3d_isense_clk_src, + .current_freq = &rcg_dummy_freq, + .base = &virt_base, + .c = { + .dbg_name = "gfx3d_isense_clk_src", + .ops = &clk_ops_rcg, + VDD_DIG_FMAX_MAP4(MIN, 19200000, LOWER, 40000000, + LOW, 200000000, HIGH, 300000000), + CLK_INIT(gfx3d_isense_clk_src.c), + }, +}; + +static struct clk_freq_tbl ftbl_rbcpr_clk_src[] = { + F( 19200000, gpucc_cxo_clk, 1, 0, 0), + F( 50000000, gpucc_gpll0, 12, 0, 0), + F_END +}; + +static struct rcg_clk rbcpr_clk_src = { + .cmd_rcgr_reg = GPUCC_RBCPR_CMD_RCGR, + .set_rate = set_rate_hid, + .freq_tbl = ftbl_rbcpr_clk_src, + .current_freq = &rcg_dummy_freq, + .base = &virt_base, + .c = { + .dbg_name = "rbcpr_clk_src", + .ops = &clk_ops_rcg, + VDD_DIG_FMAX_MAP2(MIN, 19200000, NOMINAL, 50000000), + CLK_INIT(rbcpr_clk_src.c), + }, +}; + +static struct branch_clk gpucc_gfx3d_clk = { + .cbcr_reg = GPUCC_GFX3D_CBCR, + .has_sibling = 0, + .base = &virt_base_gfx, + .c = { + .dbg_name = "gpucc_gfx3d_clk", + .parent = &gfx3d_clk_src.c, + .ops = &clk_ops_branch, + CLK_INIT(gpucc_gfx3d_clk.c), + }, +}; + +static struct branch_clk gpucc_rbbmtimer_clk = { + .cbcr_reg = GPUCC_RBBMTIMER_CBCR, + .has_sibling = 0, + .base = &virt_base, + .c = { + .dbg_name = "gpucc_rbbmtimer_clk", + .parent = &rbbmtimer_clk_src.c, + .ops = &clk_ops_branch, + CLK_INIT(gpucc_rbbmtimer_clk.c), + }, +}; + +static struct branch_clk gpucc_gfx3d_isense_clk = { + .cbcr_reg = GPUCC_GFX3D_ISENSE_CBCR, + .has_sibling = 0, + .base = &virt_base, + .c = { + .dbg_name = "gpucc_gfx3d_isense_clk", + .parent = &gfx3d_isense_clk_src.c, + .ops = &clk_ops_branch, + CLK_INIT(gpucc_gfx3d_isense_clk.c), + }, +}; + +static struct branch_clk gpucc_rbcpr_clk = { + .cbcr_reg = GPUCC_RBCPR_CBCR, + .has_sibling = 0, + .base = &virt_base, + .c = { + .dbg_name = "gpucc_rbcpr_clk", + .parent = &rbcpr_clk_src.c, + .ops = &clk_ops_branch, + CLK_INIT(gpucc_rbcpr_clk.c), + }, +}; + +static struct fixed_clk gpucc_mx_clk = { + .c = { + .dbg_name = "gpucc_mx_clk", + .vdd_class = &vdd_gpucc_mx, + .ops = &clk_ops_dummy, + CLK_INIT(gpucc_mx_clk.c), + }, +}; + +static int of_get_fmax_vdd_class(struct platform_device *pdev, struct clk *c, + char *prop_name) +{ + struct device_node *of = pdev->dev.of_node; + int prop_len, i, j; + struct clk_vdd_class *vdd = c->vdd_class; + int num = vdd->num_regulators + 1; + u32 *array; + + if (!of_find_property(of, prop_name, &prop_len)) { + dev_err(&pdev->dev, "missing %s\n", prop_name); + return -EINVAL; + } + + prop_len /= sizeof(u32); + if (prop_len % num) { + dev_err(&pdev->dev, "bad length %d\n", prop_len); + return -EINVAL; + } + + prop_len /= num; + vdd->level_votes = devm_kzalloc(&pdev->dev, prop_len * sizeof(int), + GFP_KERNEL); + if (!vdd->level_votes) + return -ENOMEM; + + vdd->vdd_uv = devm_kzalloc(&pdev->dev, + prop_len * sizeof(int) * (num - 1), GFP_KERNEL); + if (!vdd->vdd_uv) + return -ENOMEM; + + c->fmax = devm_kzalloc(&pdev->dev, prop_len * sizeof(unsigned long), + GFP_KERNEL); + if (!c->fmax) + return -ENOMEM; + + array = devm_kzalloc(&pdev->dev, + prop_len * sizeof(u32) * num, GFP_KERNEL); + if (!array) + return -ENOMEM; + + of_property_read_u32_array(of, prop_name, array, prop_len * num); + for (i = 0; i < prop_len; i++) { + c->fmax[i] = array[num * i]; + for (j = 1; j < num; j++) { + vdd->vdd_uv[(num - 1) * i + (j - 1)] = + array[num * i + j]; + } + } + + devm_kfree(&pdev->dev, array); + vdd->num_levels = prop_len; + vdd->cur_level = prop_len; + c->num_fmax = prop_len; + return 0; +} + +static struct mux_clk gpucc_gcc_dbg_clk = { + .ops = &mux_reg_ops, + .en_mask = BIT(16), + .mask = 0x3FF, + .offset = GPUCC_DEBUG_CLK_CTL, + .en_offset = GPUCC_DEBUG_CLK_CTL, + .base = &virt_base, + MUX_SRC_LIST( + { &gpucc_rbcpr_clk.c, 0x0003 }, + { &gpucc_rbbmtimer_clk.c, 0x0005 }, + { &gpucc_gfx3d_isense_clk.c, 0x000a }, + ), + .c = { + .dbg_name = "gpucc_gcc_dbg_clk", + .ops = &clk_ops_gen_mux, + .flags = CLKFLAG_NO_RATE_CACHE, + CLK_INIT(gpucc_gcc_dbg_clk.c), + }, +}; + +static void enable_gfx_crc(void) +{ + u32 regval; + + /* Set graphics clock at a safe frequency */ + clk_set_rate(&gpucc_gfx3d_clk.c, gfx3d_clk_src.c.fmax[2]); + /* Turn on the GPU_CX GDSC */ + regval = readl_relaxed(virt_base_gfx + GPU_CX_GDSCR_OFFSET); + regval &= ~SW_COLLAPSE_MASK; + writel_relaxed(regval, virt_base_gfx + GPU_CX_GDSCR_OFFSET); + /* Wait for 10usecs to let the GDSC turn ON */ + mb(); + udelay(10); + /* Turn on the Graphics rail */ + if (regulator_enable(vdd_gpucc.regulator[0])) + pr_warn("Enabling the graphics rail during CRC sequence failed!\n"); + /* Turn on the GPU_GX GDSC */ + writel_relaxed(0x1, virt_base_gfx + GPU_GX_BCR); + /* + * BLK_ARES should be kept asserted for 1us before being de-asserted. + */ + wmb(); + udelay(1); + writel_relaxed(0x0, virt_base_gfx + GPU_GX_BCR); + regval = readl_relaxed(virt_base_gfx + GPUCC_GX_DOMAIN_MISC); + regval |= BIT(4); + writel_relaxed(regval, virt_base_gfx + GPUCC_GX_DOMAIN_MISC); + /* Keep reset asserted for at-least 1us before continuing. */ + wmb(); + udelay(1); + regval &= ~BIT(4); + writel_relaxed(regval, virt_base_gfx + GPUCC_GX_DOMAIN_MISC); + /* Make sure GMEM_RESET is de-asserted before continuing. */ + wmb(); + regval &= ~BIT(0); + writel_relaxed(regval, virt_base_gfx + GPUCC_GX_DOMAIN_MISC); + /* All previous writes should be done at this point */ + wmb(); + regval = readl_relaxed(virt_base_gfx + GPU_GX_GDSCR_OFFSET); + regval &= ~SW_COLLAPSE_MASK; + writel_relaxed(regval, virt_base_gfx + GPU_GX_GDSCR_OFFSET); + /* Wait for 10usecs to let the GDSC turn ON */ + mb(); + udelay(10); + /* Enable the graphics clock */ + clk_prepare_enable(&gpucc_gfx3d_clk.c); + /* Enabling MND RC in Bypass mode */ + writel_relaxed(0x00015010, virt_base_gfx + CRC_MND_CFG_OFFSET); + writel_relaxed(0x00800000, virt_base_gfx + CRC_SID_FSM_OFFSET); + /* Wait for 16 cycles before continuing */ + udelay(1); + clk_set_rate(&gpucc_gfx3d_clk.c, + gfx3d_clk_src.c.fmax[gfx3d_clk_src.c.num_fmax - 1]); + /* Disable the graphics clock */ + clk_disable_unprepare(&gpucc_gfx3d_clk.c); + /* Turn off the gpu_cx and gpu_gx GDSCs */ + regval = readl_relaxed(virt_base_gfx + GPU_GX_GDSCR_OFFSET); + regval |= SW_COLLAPSE_MASK; + writel_relaxed(regval, virt_base_gfx + GPU_GX_GDSCR_OFFSET); + /* Write to disable GX GDSC should go through before continuing */ + wmb(); + regval = readl_relaxed(virt_base_gfx + GPUCC_GX_DOMAIN_MISC); + regval |= BIT(0); + writel_relaxed(regval, virt_base_gfx + GPUCC_GX_DOMAIN_MISC); + /* Make sure GMEM_CLAMP_IO is asserted before continuing. */ + wmb(); + regulator_disable(vdd_gpucc.regulator[0]); + regval = readl_relaxed(virt_base_gfx + GPU_CX_GDSCR_OFFSET); + regval |= SW_COLLAPSE_MASK; + writel_relaxed(regval, virt_base_gfx + GPU_CX_GDSCR_OFFSET); +} + +static struct mux_clk gfxcc_dbg_clk = { + .ops = &mux_reg_ops, + .en_mask = BIT(16), + .mask = 0x3FF, + .offset = GPUCC_DEBUG_CLK_CTL, + .en_offset = GPUCC_DEBUG_CLK_CTL, + .base = &virt_base_gfx, + MUX_SRC_LIST( + { &gpucc_gfx3d_clk.c, 0x0008 }, + ), + .c = { + .dbg_name = "gfxcc_dbg_clk", + .ops = &clk_ops_gen_mux, + .flags = CLKFLAG_NO_RATE_CACHE, + CLK_INIT(gfxcc_dbg_clk.c), + }, +}; + +static struct clk_lookup msm_clocks_gpucc_8998[] = { + CLK_LIST(gpucc_xo), + CLK_LIST(gpucc_gpll0), + CLK_LIST(gpucc_cxo_clk), + CLK_LIST(rbbmtimer_clk_src), + CLK_LIST(gfx3d_isense_clk_src), + CLK_LIST(rbcpr_clk_src), + CLK_LIST(gpucc_rbbmtimer_clk), + CLK_LIST(gpucc_gfx3d_isense_clk), + CLK_LIST(gpucc_rbcpr_clk), + CLK_LIST(gpucc_gcc_dbg_clk), +}; + +static void msm_gpucc_hamster_fixup(void) +{ + gfx3d_isense_clk_src.c.ops = &clk_ops_dummy; + gpucc_gfx3d_isense_clk.c.ops = &clk_ops_dummy; +} + +static struct platform_driver msm_clock_gfxcc_driver; +int msm_gpucc_8998_probe(struct platform_device *pdev) +{ + struct resource *res; + struct device_node *of_node = pdev->dev.of_node; + int rc; + struct regulator *reg; + u32 regval; + struct clk *tmp; + bool is_vq = 0; + + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cc_base"); + if (!res) { + dev_err(&pdev->dev, "Unable to retrieve register base\n"); + return -ENOMEM; + } + + virt_base = devm_ioremap(&pdev->dev, res->start, resource_size(res)); + if (!virt_base) { + dev_err(&pdev->dev, "Failed to map CC registers\n"); + return -ENOMEM; + } + + reg = vdd_dig.regulator[0] = devm_regulator_get(&pdev->dev, "vdd_dig"); + if (IS_ERR(reg)) { + if (PTR_ERR(reg) != -EPROBE_DEFER) + dev_err(&pdev->dev, "Unable to get vdd_dig regulator\n"); + return PTR_ERR(reg); + } + + tmp = gpucc_xo.c.parent = devm_clk_get(&pdev->dev, "xo_ao"); + if (IS_ERR(tmp)) { + if (PTR_ERR(tmp) != -EPROBE_DEFER) + dev_err(&pdev->dev, "Unable to get xo_ao clock\n"); + return PTR_ERR(tmp); + } + + tmp = gpucc_gpll0.c.parent = devm_clk_get(&pdev->dev, "gpll0"); + if (IS_ERR(tmp)) { + if (PTR_ERR(tmp) != -EPROBE_DEFER) + dev_err(&pdev->dev, "Unable to get gpll0 clock\n"); + return PTR_ERR(tmp); + } + + /* Clear the DBG_CLK_DIV bits of the GPU debug register */ + regval = readl_relaxed(virt_base + gpucc_gcc_dbg_clk.offset); + regval &= ~BM(18, 17); + writel_relaxed(regval, virt_base + gpucc_gcc_dbg_clk.offset); + + is_vq = of_device_is_compatible(pdev->dev.of_node, + "qcom,gpucc-hamster"); + if (is_vq) + msm_gpucc_hamster_fixup(); + + rc = of_msm_clock_register(of_node, msm_clocks_gpucc_8998, + ARRAY_SIZE(msm_clocks_gpucc_8998)); + if (rc) + return rc; + + /* + * gpucc_cxo_clk works as the root clock for all GPUCC RCGs and GDSCs. + * Keep it enabled always. + */ + clk_prepare_enable(&gpucc_cxo_clk.c); + + dev_info(&pdev->dev, "Registered GPU clocks (barring gfx3d clocks)\n"); + return platform_driver_register(&msm_clock_gfxcc_driver); +} + +static const struct of_device_id msm_clock_gpucc_match_table[] = { + { .compatible = "qcom,gpucc-8998" }, + { .compatible = "qcom,gpucc-8998-v2" }, + { .compatible = "qcom,gpucc-hamster" }, + {}, +}; + +static struct platform_driver msm_clock_gpucc_driver = { + .probe = msm_gpucc_8998_probe, + .driver = { + .name = "qcom,gpucc-8998", + .of_match_table = msm_clock_gpucc_match_table, + .owner = THIS_MODULE, + }, +}; + +static struct clk_lookup msm_clocks_gfxcc_8998[] = { + CLK_LIST(gpu_pll0_pll), + CLK_LIST(gpu_pll0_pll_out_even), + CLK_LIST(gpu_pll0_pll_out_odd), + CLK_LIST(gfx3d_clk_src), + CLK_LIST(gpucc_gfx3d_clk), + CLK_LIST(gpucc_mx_clk), + CLK_LIST(gfxcc_dbg_clk), +}; + +static void msm_gfxcc_hamster_fixup(void) +{ + gpu_pll0_pll.c.fmax[VDD_DIG_MIN] = 1420000500; + gfx3d_clk_src.freq_tbl = ftbl_gfx3d_clk_src_vq; +} + +static void msm_gfxcc_8998_v2_fixup(void) +{ + gpu_pll0_pll.c.fmax[VDD_DIG_MIN] = 1420000500; + gfx3d_clk_src.freq_tbl = ftbl_gfx3d_clk_src_v2; +} + +int msm_gfxcc_8998_probe(struct platform_device *pdev) +{ + struct resource *res; + struct device_node *of_node = pdev->dev.of_node; + int rc; + struct regulator *reg; + u32 regval; + bool is_v2 = 0, is_vq = 0; + + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cc_base"); + if (!res) { + dev_err(&pdev->dev, "Unable to retrieve register base\n"); + return -ENOMEM; + } + + virt_base_gfx = devm_ioremap(&pdev->dev, res->start, + resource_size(res)); + if (!virt_base_gfx) { + dev_err(&pdev->dev, "Failed to map CC registers\n"); + return -ENOMEM; + } + + reg = vdd_gpucc.regulator[0] = devm_regulator_get(&pdev->dev, + "vdd_gpucc"); + if (IS_ERR(reg)) { + if (PTR_ERR(reg) != -EPROBE_DEFER) + dev_err(&pdev->dev, "Unable to get vdd_gpucc regulator\n"); + return PTR_ERR(reg); + } + + reg = vdd_gpucc.regulator[1] = devm_regulator_get(&pdev->dev, "vdd_mx"); + if (IS_ERR(reg)) { + if (PTR_ERR(reg) != -EPROBE_DEFER) + dev_err(&pdev->dev, "Unable to get vdd_mx regulator\n"); + return PTR_ERR(reg); + } + + reg = vdd_gpucc_mx.regulator[0] = devm_regulator_get(&pdev->dev, + "vdd_gpu_mx"); + if (IS_ERR(reg)) { + if (PTR_ERR(reg) != -EPROBE_DEFER) + dev_err(&pdev->dev, "Unable to get vdd_gpu_mx regulator\n"); + return PTR_ERR(reg); + } + + rc = of_get_fmax_vdd_class(pdev, &gfx3d_clk_src.c, + "qcom,gfxfreq-speedbin0"); + if (rc) { + dev_err(&pdev->dev, "Can't get freq-corner mapping for gfx3d_clk_src\n"); + return rc; + } + + rc = of_get_fmax_vdd_class(pdev, &gpucc_mx_clk.c, + "qcom,gfxfreq-mx-speedbin0"); + if (rc) { + dev_err(&pdev->dev, "Can't get freq-corner mapping for gpucc_mx_clk\n"); + return rc; + } + + is_v2 = of_device_is_compatible(pdev->dev.of_node, + "qcom,gfxcc-8998-v2"); + if (is_v2) + msm_gfxcc_8998_v2_fixup(); + + is_vq = of_device_is_compatible(pdev->dev.of_node, + "qcom,gfxcc-hamster"); + if (is_vq) + msm_gfxcc_hamster_fixup(); + + rc = of_msm_clock_register(of_node, msm_clocks_gfxcc_8998, + ARRAY_SIZE(msm_clocks_gfxcc_8998)); + if (rc) + return rc; + + enable_gfx_crc(); + + /* + * Force periph logic to be ON since after NAP, the value of the perf + * counter might be corrupted frequently. + */ + clk_set_flags(&gpucc_gfx3d_clk.c, CLKFLAG_RETAIN_PERIPH); + + /* + * Program the droop detector's gfx_pdn to 1'b1 in order to reduce + * leakage between the graphics and CX rails. + */ + regval = readl_relaxed(virt_base_gfx + GPUCC_GPU_DD_WRAP_CTRL); + regval |= BIT(0); + writel_relaxed(regval, virt_base_gfx + GPUCC_GPU_DD_WRAP_CTRL); + + dev_info(&pdev->dev, "Completed registering all GPU clocks\n"); + + return 0; +} + +static const struct of_device_id msm_clock_gfxcc_match_table[] = { + { .compatible = "qcom,gfxcc-8998" }, + { .compatible = "qcom,gfxcc-8998-v2" }, + { .compatible = "qcom,gfxcc-hamster" }, + {}, +}; + +static struct platform_driver msm_clock_gfxcc_driver = { + .probe = msm_gfxcc_8998_probe, + .driver = { + .name = "qcom,gfxcc-8998", + .of_match_table = msm_clock_gfxcc_match_table, + .owner = THIS_MODULE, + }, +}; + +int __init msm_gpucc_8998_init(void) +{ + return platform_driver_register(&msm_clock_gpucc_driver); +} +arch_initcall(msm_gpucc_8998_init); diff -Nruw linux-4.4.115-fbx/drivers/clk/msm./clock.h linux-4.4.115-fbx/drivers/clk/msm/clock.h --- linux-4.4.115-fbx/drivers/clk/msm./clock.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-4.4.115-fbx/drivers/clk/msm/clock.h 2019-01-22 16:16:23.019242024 +0100 @@ -0,0 +1,54 @@ +/* + * Copyright (c) 2013-2014, 2016, The Linux Foundation. All rights reserved. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef __DRIVERS_CLK_MSM_CLOCK_H +#define __DRIVERS_CLK_MSM_CLOCK_H + +#include + +/** + * struct clock_init_data - SoC specific clock initialization data + * @table: table of lookups to add + * @size: size of @table + * @pre_init: called before initializing the clock driver. + * @post_init: called after registering @table. clock APIs can be called inside. + * @late_init: called during late init + */ +struct clock_init_data { + struct list_head list; + struct clk_lookup *table; + size_t size; + void (*pre_init)(void); + void (*post_init)(void); + int (*late_init)(void); +}; + +int msm_clock_init(struct clock_init_data *data); +int find_vdd_level(struct clk *clk, unsigned long rate); +extern struct list_head orphan_clk_list; + +#if defined(CONFIG_DEBUG_FS) && defined(CONFIG_COMMON_CLK_MSM) +int clock_debug_register(struct clk *clk); +void clock_debug_print_enabled(void); +#elif defined(CONFIG_DEBUG_FS) && defined(CONFIG_COMMON_CLK_QCOM) +void clock_debug_print_enabled(void); +#else +static inline int clock_debug_register(struct clk *unused) +{ + return 0; +} +static inline void clock_debug_print_enabled(void) { return; } +#endif + +#endif diff -Nruw linux-4.4.115-fbx/drivers/clk/msm./clock-local2.c linux-4.4.115-fbx/drivers/clk/msm/clock-local2.c --- linux-4.4.115-fbx/drivers/clk/msm./clock-local2.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-4.4.115-fbx/drivers/clk/msm/clock-local2.c 2019-01-22 16:16:23.015241987 +0100 @@ -0,0 +1,3010 @@ +/* Copyright (c) 2012-2017, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#define pr_fmt(fmt) "%s: " fmt, __func__ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* + * When enabling/disabling a clock, check the halt bit up to this number + * number of times (with a 1 us delay in between) before continuing. + */ +#define HALT_CHECK_MAX_LOOPS 500 +/* For clock without halt checking, wait this long after enables/disables. */ +#define HALT_CHECK_DELAY_US 500 + +#define RCG_FORCE_DISABLE_DELAY_US 100 + +/* + * When updating an RCG configuration, check the update bit up to this number + * number of times (with a 1 us delay in between) before continuing. + */ +#define UPDATE_CHECK_MAX_LOOPS 500 + +DEFINE_SPINLOCK(local_clock_reg_lock); +struct clk_freq_tbl rcg_dummy_freq = F_END; + +#define CMD_RCGR_REG(x) (*(x)->base + (x)->cmd_rcgr_reg) +#define CFG_RCGR_REG(x) (*(x)->base + (x)->cmd_rcgr_reg + 0x4) +#define M_REG(x) (*(x)->base + (x)->cmd_rcgr_reg + 0x8) +#define N_REG(x) (*(x)->base + (x)->cmd_rcgr_reg + 0xC) +#define D_REG(x) (*(x)->base + (x)->cmd_rcgr_reg + 0x10) +#define CBCR_REG(x) (*(x)->base + (x)->cbcr_reg) +#define BCR_REG(x) (*(x)->base + (x)->bcr_reg) +#define RST_REG(x) (*(x)->base + (x)->reset_reg) +#define VOTE_REG(x) (*(x)->base + (x)->vote_reg) +#define GATE_EN_REG(x) (*(x)->base + (x)->en_reg) +#define DIV_REG(x) (*(x)->base + (x)->offset) +#define MUX_REG(x) (*(x)->base + (x)->offset) + +/* + * Important clock bit positions and masks + */ +#define CMD_RCGR_ROOT_ENABLE_BIT BIT(1) +#define CBCR_BRANCH_ENABLE_BIT BIT(0) +#define CBCR_BRANCH_OFF_BIT BIT(31) +#define CMD_RCGR_CONFIG_UPDATE_BIT BIT(0) +#define CMD_RCGR_ROOT_STATUS_BIT BIT(31) +#define BCR_BLK_ARES_BIT BIT(0) +#define CBCR_HW_CTL_BIT BIT(1) +#define CFG_RCGR_DIV_MASK BM(4, 0) +#define CFG_RCGR_SRC_SEL_MASK BM(10, 8) +#define MND_MODE_MASK BM(13, 12) +#define MND_DUAL_EDGE_MODE_BVAL BVAL(13, 12, 0x2) +#define CMD_RCGR_CONFIG_DIRTY_MASK BM(7, 4) +#define CBCR_CDIV_LSB 16 +#define CBCR_CDIV_MSB 19 + +enum branch_state { + BRANCH_ON, + BRANCH_OFF, +}; + +static struct clk_freq_tbl cxo_f = { + .freq_hz = 19200000, + .m_val = 0, + .n_val = 0, + .d_val = 0, + .div_src_val = 0, +}; + +struct div_map { + u32 mask; + int div; +}; + +/* + * RCG functions + */ + +/* + * Update an RCG with a new configuration. This may include a new M, N, or D + * value, source selection or pre-divider value. + * + */ +static void rcg_update_config(struct rcg_clk *rcg) +{ + u32 cmd_rcgr_regval; + int count = UPDATE_CHECK_MAX_LOOPS; + + if (rcg->non_local_control_timeout) + count = rcg->non_local_control_timeout; + + cmd_rcgr_regval = readl_relaxed(CMD_RCGR_REG(rcg)); + cmd_rcgr_regval |= CMD_RCGR_CONFIG_UPDATE_BIT; + writel_relaxed(cmd_rcgr_regval, CMD_RCGR_REG(rcg)); + + /* Wait for update to take effect */ + for (; count > 0; count--) { + if (!(readl_relaxed(CMD_RCGR_REG(rcg)) & + CMD_RCGR_CONFIG_UPDATE_BIT)) + return; + udelay(1); + } + + CLK_WARN(&rcg->c, count == 0, "rcg didn't update its configuration."); +} + +static void rcg_on_check(struct rcg_clk *rcg) +{ + int count = UPDATE_CHECK_MAX_LOOPS; + + if (rcg->non_local_control_timeout) + count = rcg->non_local_control_timeout; + + /* Wait for RCG to turn on */ + for (; count > 0; count--) { + if (!(readl_relaxed(CMD_RCGR_REG(rcg)) & + CMD_RCGR_ROOT_STATUS_BIT)) + return; + udelay(1); + } + CLK_WARN(&rcg->c, count == 0, "rcg didn't turn on."); +} + +/* RCG set rate function for clocks with Half Integer Dividers. */ +static void __set_rate_hid(struct rcg_clk *rcg, struct clk_freq_tbl *nf) +{ + u32 cfg_regval; + + cfg_regval = readl_relaxed(CFG_RCGR_REG(rcg)); + cfg_regval &= ~(CFG_RCGR_DIV_MASK | CFG_RCGR_SRC_SEL_MASK); + cfg_regval |= nf->div_src_val; + writel_relaxed(cfg_regval, CFG_RCGR_REG(rcg)); + + rcg_update_config(rcg); +} + +void set_rate_hid(struct rcg_clk *rcg, struct clk_freq_tbl *nf) +{ + unsigned long flags; + spin_lock_irqsave(&local_clock_reg_lock, flags); + __set_rate_hid(rcg, nf); + spin_unlock_irqrestore(&local_clock_reg_lock, flags); +} + +/* RCG set rate function for clocks with MND & Half Integer Dividers. */ +static void __set_rate_mnd(struct rcg_clk *rcg, struct clk_freq_tbl *nf) +{ + u32 cfg_regval; + + cfg_regval = readl_relaxed(CFG_RCGR_REG(rcg)); + writel_relaxed(nf->m_val, M_REG(rcg)); + writel_relaxed(nf->n_val, N_REG(rcg)); + writel_relaxed(nf->d_val, D_REG(rcg)); + + cfg_regval = readl_relaxed(CFG_RCGR_REG(rcg)); + cfg_regval &= ~(CFG_RCGR_DIV_MASK | CFG_RCGR_SRC_SEL_MASK); + cfg_regval |= nf->div_src_val; + + /* Activate or disable the M/N:D divider as necessary */ + cfg_regval &= ~MND_MODE_MASK; + if (nf->n_val != 0) + cfg_regval |= MND_DUAL_EDGE_MODE_BVAL; + writel_relaxed(cfg_regval, CFG_RCGR_REG(rcg)); + + rcg_update_config(rcg); +} + +void set_rate_mnd(struct rcg_clk *rcg, struct clk_freq_tbl *nf) +{ + unsigned long flags; + spin_lock_irqsave(&local_clock_reg_lock, flags); + __set_rate_mnd(rcg, nf); + spin_unlock_irqrestore(&local_clock_reg_lock, flags); +} + +static void rcg_set_force_enable(struct rcg_clk *rcg) +{ + u32 cmd_rcgr_regval; + unsigned long flags; + + spin_lock_irqsave(&local_clock_reg_lock, flags); + cmd_rcgr_regval = readl_relaxed(CMD_RCGR_REG(rcg)); + cmd_rcgr_regval |= CMD_RCGR_ROOT_ENABLE_BIT; + writel_relaxed(cmd_rcgr_regval, CMD_RCGR_REG(rcg)); + rcg_on_check(rcg); + spin_unlock_irqrestore(&local_clock_reg_lock, flags); +} + +static void rcg_clear_force_enable(struct rcg_clk *rcg) +{ + u32 cmd_rcgr_regval; + unsigned long flags; + + spin_lock_irqsave(&local_clock_reg_lock, flags); + cmd_rcgr_regval = readl_relaxed(CMD_RCGR_REG(rcg)); + cmd_rcgr_regval &= ~CMD_RCGR_ROOT_ENABLE_BIT; + writel_relaxed(cmd_rcgr_regval, CMD_RCGR_REG(rcg)); + spin_unlock_irqrestore(&local_clock_reg_lock, flags); + /* Add a delay of 100usecs to let the RCG disable */ + udelay(RCG_FORCE_DISABLE_DELAY_US); +} + +static int rcg_clk_enable(struct clk *c) +{ + struct rcg_clk *rcg = to_rcg_clk(c); + + WARN(rcg->current_freq == &rcg_dummy_freq, + "Attempting to prepare %s before setting its rate. " + "Set the rate first!\n", rcg->c.dbg_name); + + if (rcg->force_enable_rcgr) { + rcg_set_force_enable(rcg); + return 0; + } + + if (!rcg->non_local_children || rcg->current_freq == &rcg_dummy_freq) + return 0; + /* + * Switch from CXO to saved mux value. Force enable/disable while + * switching. The current parent is already prepared and enabled + * at this point, and the CXO source is always-on. Therefore the + * RCG can safely execute a dynamic switch. + */ + rcg_set_force_enable(rcg); + rcg->set_rate(rcg, rcg->current_freq); + rcg_clear_force_enable(rcg); + + return 0; +} + +static void rcg_clk_disable(struct clk *c) +{ + struct rcg_clk *rcg = to_rcg_clk(c); + + if (rcg->force_enable_rcgr) { + rcg_clear_force_enable(rcg); + return; + } + + if (!rcg->non_local_children) + return; + + /* + * Save mux select and switch to CXO. Force enable/disable while + * switching. The current parent is still prepared and enabled at this + * point, and the CXO source is always-on. Therefore the RCG can safely + * execute a dynamic switch. + */ + rcg_set_force_enable(rcg); + rcg->set_rate(rcg, &cxo_f); + rcg_clear_force_enable(rcg); +} + +static int prepare_enable_rcg_srcs(struct clk *c, struct clk *curr, + struct clk *new, unsigned long *flags) +{ + int rc; + + rc = clk_prepare(curr); + if (rc) + return rc; + + if (c->prepare_count) { + rc = clk_prepare(new); + if (rc) + goto err_new_src_prepare; + } + + rc = clk_prepare(new); + if (rc) + goto err_new_src_prepare2; + + spin_lock_irqsave(&c->lock, *flags); + rc = clk_enable(curr); + if (rc) { + spin_unlock_irqrestore(&c->lock, *flags); + goto err_curr_src_enable; + } + + if (c->count) { + rc = clk_enable(new); + if (rc) { + spin_unlock_irqrestore(&c->lock, *flags); + goto err_new_src_enable; + } + } + + rc = clk_enable(new); + if (rc) { + spin_unlock_irqrestore(&c->lock, *flags); + goto err_new_src_enable2; + } + return 0; + +err_new_src_enable2: + if (c->count) + clk_disable(new); +err_new_src_enable: + clk_disable(curr); +err_curr_src_enable: + clk_unprepare(new); +err_new_src_prepare2: + if (c->prepare_count) + clk_unprepare(new); +err_new_src_prepare: + clk_unprepare(curr); + return rc; +} + +static void disable_unprepare_rcg_srcs(struct clk *c, struct clk *curr, + struct clk *new, unsigned long *flags) +{ + clk_disable(new); + clk_disable(curr); + if (c->count) + clk_disable(curr); + spin_unlock_irqrestore(&c->lock, *flags); + + clk_unprepare(new); + clk_unprepare(curr); + if (c->prepare_count) + clk_unprepare(curr); +} + +static int rcg_clk_set_rate(struct clk *c, unsigned long rate) +{ + struct clk_freq_tbl *cf, *nf; + struct rcg_clk *rcg = to_rcg_clk(c); + int rc; + unsigned long flags; + + for (nf = rcg->freq_tbl; nf->freq_hz != FREQ_END + && nf->freq_hz != rate; nf++) + ; + + if (nf->freq_hz == FREQ_END) + return -EINVAL; + + cf = rcg->current_freq; + if (nf->src_freq != FIXED_CLK_SRC) { + rc = clk_set_rate(nf->src_clk, nf->src_freq); + if (rc) + return rc; + } + + if (rcg->non_local_control_timeout) { + /* + * __clk_pre_reparent only enables the RCG source if the SW + * count for the RCG is non-zero. We need to make sure that + * both PLL sources are ON before force turning on the RCG. + */ + rc = prepare_enable_rcg_srcs(c, cf->src_clk, nf->src_clk, + &flags); + } else + rc = __clk_pre_reparent(c, nf->src_clk, &flags); + + if (rc) + return rc; + + BUG_ON(!rcg->set_rate); + + /* Perform clock-specific frequency switch operations. */ + if ((rcg->non_local_children && c->count) || + rcg->non_local_control_timeout) { + /* + * Force enable the RCG before updating the RCG configuration + * since the downstream clock/s can be disabled at around the + * same time causing the feedback from the CBCR to turn off + * the RCG. + */ + rcg_set_force_enable(rcg); + rcg->set_rate(rcg, nf); + rcg_clear_force_enable(rcg); + } else if (!rcg->non_local_children) { + rcg->set_rate(rcg, nf); + } + + /* + * If non_local_children is set and the RCG is not enabled, + * the following operations switch parent in software and cache + * the frequency. The mux switch will occur when the RCG is enabled. + */ + rcg->current_freq = nf; + c->parent = nf->src_clk; + + if (rcg->non_local_control_timeout) + disable_unprepare_rcg_srcs(c, cf->src_clk, nf->src_clk, + &flags); + else + __clk_post_reparent(c, cf->src_clk, &flags); + + return 0; +} + +/* + * Return a supported rate that's at least the specified rate or + * the max supported rate if the specified rate is larger than the + * max supported rate. + */ +static long rcg_clk_round_rate(struct clk *c, unsigned long rate) +{ + struct rcg_clk *rcg = to_rcg_clk(c); + struct clk_freq_tbl *f; + + for (f = rcg->freq_tbl; f->freq_hz != FREQ_END; f++) + if (f->freq_hz >= rate) + return f->freq_hz; + + f--; + return f->freq_hz; +} + +/* Return the nth supported frequency for a given clock. */ +static long rcg_clk_list_rate(struct clk *c, unsigned n) +{ + struct rcg_clk *rcg = to_rcg_clk(c); + + if (!rcg->freq_tbl || rcg->freq_tbl->freq_hz == FREQ_END) + return -ENXIO; + + return (rcg->freq_tbl + n)->freq_hz; +} + +static struct clk *_rcg_clk_get_parent(struct rcg_clk *rcg, bool has_mnd, + bool match_rate) +{ + u32 n_regval = 0, m_regval = 0, d_regval = 0; + u32 cfg_regval, div, div_regval; + struct clk_freq_tbl *freq; + u32 cmd_rcgr_regval; + + if (!rcg->freq_tbl) { + WARN(1, "No frequency table present for rcg %s\n", + rcg->c.dbg_name); + return NULL; + } + + /* Is there a pending configuration? */ + cmd_rcgr_regval = readl_relaxed(CMD_RCGR_REG(rcg)); + if (cmd_rcgr_regval & CMD_RCGR_CONFIG_DIRTY_MASK) { + WARN(1, "Pending transaction for rcg %s\n", rcg->c.dbg_name); + return NULL; + } + + /* Get values of m, n, d, div and src_sel registers. */ + if (has_mnd) { + m_regval = readl_relaxed(M_REG(rcg)); + n_regval = readl_relaxed(N_REG(rcg)); + d_regval = readl_relaxed(D_REG(rcg)); + + /* + * The n and d values stored in the frequency tables are sign + * extended to 32 bits. The n and d values in the registers are + * sign extended to 8 or 16 bits. Sign extend the values read + * from the registers so that they can be compared to the + * values in the frequency tables. + */ + n_regval |= (n_regval >> 8) ? BM(31, 16) : BM(31, 8); + d_regval |= (d_regval >> 8) ? BM(31, 16) : BM(31, 8); + } + + cfg_regval = readl_relaxed(CFG_RCGR_REG(rcg)); + cfg_regval &= CFG_RCGR_SRC_SEL_MASK | CFG_RCGR_DIV_MASK + | MND_MODE_MASK; + + /* If mnd counter is present, check if it's in use. */ + has_mnd = (has_mnd) && + ((cfg_regval & MND_MODE_MASK) == MND_DUAL_EDGE_MODE_BVAL); + + /* + * Clear out the mn counter mode bits since we now want to compare only + * the source mux selection and pre-divider values in the registers. + */ + cfg_regval &= ~MND_MODE_MASK; + + /* Figure out what rate the rcg is running at */ + for (freq = rcg->freq_tbl; freq->freq_hz != FREQ_END; freq++) { + /* source select does not match */ + if ((freq->div_src_val & CFG_RCGR_SRC_SEL_MASK) + != (cfg_regval & CFG_RCGR_SRC_SEL_MASK)) + continue; + /* + * Stop if we found the required parent in the frequency table + * and only care if the source matches but dont care if the + * frequency matches + */ + if (!match_rate) + break; + /* divider does not match */ + div = freq->div_src_val & CFG_RCGR_DIV_MASK; + div_regval = cfg_regval & CFG_RCGR_DIV_MASK; + if (div != div_regval && (div > 1 || div_regval > 1)) + continue; + + if (has_mnd) { + if (freq->m_val != m_regval) + continue; + if (freq->n_val != n_regval) + continue; + if (freq->d_val != d_regval) + continue; + } else if (freq->n_val) { + continue; + } + break; + } + + /* No known frequency found */ + if (freq->freq_hz == FREQ_END) { + /* + * If we can't recognize the frequency and non_local_children is + * set, switch to safe frequency. It is assumed the current + * parent has been turned on by the bootchain if the RCG is on. + */ + if (rcg->non_local_children) { + rcg->set_rate(rcg, &cxo_f); + WARN(1, "don't recognize rcg frequency for %s\n", + rcg->c.dbg_name); + } + return NULL; + } + + rcg->current_freq = freq; + return freq->src_clk; +} + +static enum handoff _rcg_clk_handoff(struct rcg_clk *rcg) +{ + u32 cmd_rcgr_regval; + + if (rcg->current_freq && rcg->current_freq->freq_hz != FREQ_END) + rcg->c.rate = rcg->current_freq->freq_hz; + + /* Is the root enabled? */ + cmd_rcgr_regval = readl_relaxed(CMD_RCGR_REG(rcg)); + if ((cmd_rcgr_regval & CMD_RCGR_ROOT_STATUS_BIT)) + return HANDOFF_DISABLED_CLK; + + return HANDOFF_ENABLED_CLK; +} + +static struct clk *display_clk_get_parent(struct clk *c) +{ + return _rcg_clk_get_parent(to_rcg_clk(c), false, false); +} + +static struct clk *rcg_mnd_clk_get_parent(struct clk *c) +{ + return _rcg_clk_get_parent(to_rcg_clk(c), true, true); +} + +static struct clk *rcg_clk_get_parent(struct clk *c) +{ + return _rcg_clk_get_parent(to_rcg_clk(c), false, true); +} + +static enum handoff rcg_mnd_clk_handoff(struct clk *c) +{ + return _rcg_clk_handoff(to_rcg_clk(c)); +} + +static enum handoff rcg_clk_handoff(struct clk *c) +{ + return _rcg_clk_handoff(to_rcg_clk(c)); +} + +static void __iomem *rcg_hid_clk_list_registers(struct clk *c, int n, + struct clk_register_data **regs, u32 *size) +{ + struct rcg_clk *rcg = to_rcg_clk(c); + static struct clk_register_data data[] = { + {"CMD_RCGR", 0x0}, + {"CFG_RCGR", 0x4}, + }; + if (n) + return ERR_PTR(-EINVAL); + + *regs = data; + *size = ARRAY_SIZE(data); + return CMD_RCGR_REG(rcg); +} + +static void __iomem *rcg_mnd_clk_list_registers(struct clk *c, int n, + struct clk_register_data **regs, u32 *size) +{ + struct rcg_clk *rcg = to_rcg_clk(c); + static struct clk_register_data data[] = { + {"CMD_RCGR", 0x0}, + {"CFG_RCGR", 0x4}, + {"M_VAL", 0x8}, + {"N_VAL", 0xC}, + {"D_VAL", 0x10}, + }; + if (n) + return ERR_PTR(-EINVAL); + + *regs = data; + *size = ARRAY_SIZE(data); + return CMD_RCGR_REG(rcg); +} + +#define BRANCH_CHECK_MASK BM(31, 28) +#define BRANCH_ON_VAL BVAL(31, 28, 0x0) +#define BRANCH_OFF_VAL BVAL(31, 28, 0x8) +#define BRANCH_NOC_FSM_ON_VAL BVAL(31, 28, 0x2) + +/* + * Branch clock functions + */ +static int branch_clk_halt_check(struct clk *c, u32 halt_check, + void __iomem *cbcr_reg, enum branch_state br_status) +{ + char *status_str = (br_status == BRANCH_ON) ? "off" : "on"; + + /* + * Use a memory barrier since some halt status registers are + * not within the same 1K segment as the branch/root enable + * registers. It's also needed in the udelay() case to ensure + * the delay starts after the branch disable. + */ + mb(); + + if (halt_check == DELAY || halt_check == HALT_VOTED) { + udelay(HALT_CHECK_DELAY_US); + } else if (halt_check == HALT) { + int count; + u32 val; + for (count = HALT_CHECK_MAX_LOOPS; count > 0; count--) { + val = readl_relaxed(cbcr_reg); + val &= BRANCH_CHECK_MASK; + switch (br_status) { + case BRANCH_ON: + if (val == BRANCH_ON_VAL + || val == BRANCH_NOC_FSM_ON_VAL) + return 0; + break; + + case BRANCH_OFF: + if (val == BRANCH_OFF_VAL) + return 0; + break; + }; + udelay(1); + } + CLK_WARN(c, count == 0, "status stuck %s", status_str); + if (!count) + return -ETIMEDOUT; + } else { + pr_err("Invalid halt_check flag - %u\n", halt_check); + return -EINVAL; + } + + return 0; +} + +static unsigned long branch_clk_aggregate_rate(const struct clk *parent) +{ + struct clk *clk; + unsigned long rate = 0; + + list_for_each_entry(clk, &parent->children, siblings) { + struct branch_clk *v = to_branch_clk(clk); + + if (v->is_prepared) + rate = max(clk->rate, rate); + } + return rate; +} + +static int cbcr_set_flags(void * __iomem regaddr, unsigned flags) +{ + u32 cbcr_val; + unsigned long irq_flags; + int delay_us = 0, ret = 0; + + spin_lock_irqsave(&local_clock_reg_lock, irq_flags); + cbcr_val = readl_relaxed(regaddr); + switch (flags) { + case CLKFLAG_PERIPH_OFF_SET: + cbcr_val |= BIT(12); + delay_us = 1; + break; + case CLKFLAG_PERIPH_OFF_CLEAR: + cbcr_val &= ~BIT(12); + break; + case CLKFLAG_RETAIN_PERIPH: + cbcr_val |= BIT(13); + delay_us = 1; + break; + case CLKFLAG_NORETAIN_PERIPH: + cbcr_val &= ~BIT(13); + break; + case CLKFLAG_RETAIN_MEM: + cbcr_val |= BIT(14); + delay_us = 1; + break; + case CLKFLAG_NORETAIN_MEM: + cbcr_val &= ~BIT(14); + break; + default: + ret = -EINVAL; + } + writel_relaxed(cbcr_val, regaddr); + /* Make sure power is enabled before returning. */ + mb(); + udelay(delay_us); + + spin_unlock_irqrestore(&local_clock_reg_lock, irq_flags); + + return ret; +} + +static int branch_clk_set_flags(struct clk *c, unsigned flags) +{ + return cbcr_set_flags(CBCR_REG(to_branch_clk(c)), flags); +} + +static DEFINE_MUTEX(branch_clk_lock); + +static void branch_clk_unprepare(struct clk *c) +{ + struct branch_clk *branch = to_branch_clk(c); + unsigned long curr_rate, new_rate; + + if (!branch->aggr_sibling_rates) + return; + + mutex_lock(&branch_clk_lock); + branch->is_prepared = false; + new_rate = branch_clk_aggregate_rate(c->parent); + curr_rate = max(new_rate, c->rate); + if (new_rate < curr_rate) + clk_set_rate(c->parent, new_rate); + mutex_unlock(&branch_clk_lock); +} + +static int branch_clk_prepare(struct clk *c) +{ + struct branch_clk *branch = to_branch_clk(c); + unsigned long curr_rate; + int ret = 0; + + if (!branch->aggr_sibling_rates) + return ret; + + mutex_lock(&branch_clk_lock); + branch->is_prepared = false; + curr_rate = branch_clk_aggregate_rate(c->parent); + if (c->rate > curr_rate) { + ret = clk_set_rate(c->parent, c->rate); + if (ret) + goto exit; + } + branch->is_prepared = true; +exit: + mutex_unlock(&branch_clk_lock); + return ret; +} + +static void branch_clk_disable(struct clk *c) +{ + unsigned long flags; + struct branch_clk *branch = to_branch_clk(c); + u32 reg_val; + + spin_lock_irqsave(&local_clock_reg_lock, flags); + reg_val = readl_relaxed(CBCR_REG(branch)); + reg_val &= ~CBCR_BRANCH_ENABLE_BIT; + writel_relaxed(reg_val, CBCR_REG(branch)); + spin_unlock_irqrestore(&local_clock_reg_lock, flags); + + /* + * Wait for clock to disable before continuing. If disable times out, + * it is not handled explicitly since it is considered as non-fatal. + */ + if (!branch->no_halt_check_on_disable) + branch_clk_halt_check(c, branch->halt_check, CBCR_REG(branch), + BRANCH_OFF); + + if (branch->toggle_memory) { + branch_clk_set_flags(c, CLKFLAG_NORETAIN_MEM); + branch_clk_set_flags(c, CLKFLAG_NORETAIN_PERIPH); + } +} + +static int branch_clk_enable(struct clk *c) +{ + unsigned long flags; + u32 cbcr_val; + struct branch_clk *branch = to_branch_clk(c); + int ret = 0; + + if (branch->toggle_memory) { + branch_clk_set_flags(c, CLKFLAG_RETAIN_MEM); + branch_clk_set_flags(c, CLKFLAG_RETAIN_PERIPH); + } + spin_lock_irqsave(&local_clock_reg_lock, flags); + cbcr_val = readl_relaxed(CBCR_REG(branch)); + cbcr_val |= CBCR_BRANCH_ENABLE_BIT; + writel_relaxed(cbcr_val, CBCR_REG(branch)); + spin_unlock_irqrestore(&local_clock_reg_lock, flags); + + /* + * For clocks controlled by other masters via voting registers, + * delay polling for the status bit to allow previous clk_disable + * by the GDS controller to go through. + */ + if (branch->no_halt_check_on_disable) + udelay(5); + + /* Wait for clock to enable before continuing. */ + ret = branch_clk_halt_check(c, branch->halt_check, CBCR_REG(branch), + BRANCH_ON); + if (ret) + branch_clk_disable(c); + + return ret; +} + +static int branch_cdiv_set_rate(struct branch_clk *branch, unsigned long rate) +{ + unsigned long flags; + u32 regval; + + if (rate > branch->max_div) + return -EINVAL; + + spin_lock_irqsave(&local_clock_reg_lock, flags); + regval = readl_relaxed(CBCR_REG(branch)); + regval &= ~BM(CBCR_CDIV_MSB, CBCR_CDIV_LSB); + regval |= BVAL(CBCR_CDIV_MSB, CBCR_CDIV_LSB, rate); + writel_relaxed(regval, CBCR_REG(branch)); + spin_unlock_irqrestore(&local_clock_reg_lock, flags); + + return 0; +} + +static int branch_clk_set_rate(struct clk *c, unsigned long rate) +{ + struct branch_clk *clkh, *branch = to_branch_clk(c); + struct clk *clkp, *parent = c->parent; + unsigned long flags, curr_rate, new_rate, other_rate = 0; + int ret = 0; + + spin_lock_irqsave(&local_clock_reg_lock, flags); + if (readl_relaxed(CBCR_REG(branch)) & CBCR_HW_CTL_BIT) { + pr_err("Cannot scale %s clock while HW gating is enabled. Use corresponding hw_ctl_clk to scale it\n", + c->dbg_name); + spin_unlock_irqrestore(&local_clock_reg_lock, flags); + return -EINVAL; + } + spin_unlock_irqrestore(&local_clock_reg_lock, flags); + + if (branch->max_div) + return branch_cdiv_set_rate(branch, rate); + + if (branch->has_sibling) + return -EPERM; + + if (!branch->aggr_sibling_rates) + return clk_set_rate(c->parent, rate); + + mutex_lock(&branch_clk_lock); + if (!branch->is_prepared) { + c->rate = rate; + goto exit; + } + /* + * Get the aggregate rate without this clock's vote and update + * if the new rate is different than the current rate. + */ + list_for_each_entry(clkp, &parent->children, siblings) { + clkh = to_branch_clk(clkp); + if (clkh->is_prepared && clkh != branch) + other_rate = max(clkp->rate, other_rate); + } + curr_rate = max(other_rate, c->rate); + new_rate = max(other_rate, rate); + if (new_rate != curr_rate) { + ret = clk_set_rate(parent, new_rate); + if (!ret) + c->rate = rate; + } +exit: + mutex_unlock(&branch_clk_lock); + return ret; +} + +static long branch_clk_round_rate(struct clk *c, unsigned long rate) +{ + struct branch_clk *branch = to_branch_clk(c); + + if (branch->max_div) + return rate <= (branch->max_div) ? rate : -EPERM; + + if (!branch->has_sibling) + return clk_round_rate(c->parent, rate); + + return -EPERM; +} + +static unsigned long branch_clk_get_rate(struct clk *c) +{ + struct branch_clk *branch = to_branch_clk(c); + + if (branch->max_div || + (branch->aggr_sibling_rates && !branch->is_prepared)) + return branch->c.rate; + + return clk_get_rate(c->parent); +} + +static long branch_clk_list_rate(struct clk *c, unsigned n) +{ + int level; + unsigned long fmax = 0, rate; + struct branch_clk *branch = to_branch_clk(c); + struct clk *parent = c->parent; + + if (branch->has_sibling == 1) + return -ENXIO; + + if (!parent || !parent->ops->list_rate) + return -ENXIO; + + /* Find max frequency supported within voltage constraints. */ + if (!parent->vdd_class) { + fmax = ULONG_MAX; + } else { + for (level = 0; level < parent->num_fmax; level++) + if (parent->fmax[level]) + fmax = parent->fmax[level]; + } + + rate = parent->ops->list_rate(parent, n); + if (rate <= fmax) + return rate; + else + return -ENXIO; +} + +static enum handoff branch_clk_handoff(struct clk *c) +{ + struct branch_clk *branch = to_branch_clk(c); + u32 cbcr_regval; + + cbcr_regval = readl_relaxed(CBCR_REG(branch)); + + /* Set the cdiv to c->rate for fixed divider branch clock */ + if (c->rate && (c->rate < branch->max_div)) { + cbcr_regval &= ~BM(CBCR_CDIV_MSB, CBCR_CDIV_LSB); + cbcr_regval |= BVAL(CBCR_CDIV_MSB, CBCR_CDIV_LSB, c->rate); + writel_relaxed(cbcr_regval, CBCR_REG(branch)); + } + + if ((cbcr_regval & CBCR_BRANCH_OFF_BIT)) + return HANDOFF_DISABLED_CLK; + + if (!(cbcr_regval & CBCR_BRANCH_ENABLE_BIT)) { + if (!branch->check_enable_bit) + pr_warn("%s clock is enabled in HW even though ENABLE_BIT is not set\n", + c->dbg_name); + return HANDOFF_DISABLED_CLK; + } + + if (branch->max_div) { + cbcr_regval &= BM(CBCR_CDIV_MSB, CBCR_CDIV_LSB); + cbcr_regval >>= CBCR_CDIV_LSB; + c->rate = cbcr_regval; + } else if (!branch->has_sibling) { + c->rate = clk_get_rate(c->parent); + } + + return HANDOFF_ENABLED_CLK; +} + +static int __branch_clk_reset(void __iomem *bcr_reg, + enum clk_reset_action action) +{ + int ret = 0; + unsigned long flags; + u32 reg_val; + + spin_lock_irqsave(&local_clock_reg_lock, flags); + reg_val = readl_relaxed(bcr_reg); + switch (action) { + case CLK_RESET_ASSERT: + reg_val |= BCR_BLK_ARES_BIT; + break; + case CLK_RESET_DEASSERT: + reg_val &= ~BCR_BLK_ARES_BIT; + break; + default: + ret = -EINVAL; + } + writel_relaxed(reg_val, bcr_reg); + spin_unlock_irqrestore(&local_clock_reg_lock, flags); + + /* Make sure write is issued before returning. */ + mb(); + + return ret; +} + +static int branch_clk_reset(struct clk *c, enum clk_reset_action action) +{ + struct branch_clk *branch = to_branch_clk(c); + + if (!branch->bcr_reg) + return -EPERM; + return __branch_clk_reset(BCR_REG(branch), action); +} + +static void __iomem *branch_clk_list_registers(struct clk *c, int n, + struct clk_register_data **regs, u32 *size) +{ + struct branch_clk *branch = to_branch_clk(c); + static struct clk_register_data data[] = { + {"CBCR", 0x0}, + }; + if (n) + return ERR_PTR(-EINVAL); + + *regs = data; + *size = ARRAY_SIZE(data); + return CBCR_REG(branch); +} + +static void _hw_ctl_clk_enable(struct hw_ctl_clk *hwctl_clk) +{ + unsigned long flags; + u32 cbcr_val; + + spin_lock_irqsave(&local_clock_reg_lock, flags); + cbcr_val = readl_relaxed(CBCR_REG(hwctl_clk)); + cbcr_val |= CBCR_HW_CTL_BIT; + writel_relaxed(cbcr_val, CBCR_REG(hwctl_clk)); + spin_unlock_irqrestore(&local_clock_reg_lock, flags); +} + +static int hw_ctl_clk_enable(struct clk *c) +{ + struct hw_ctl_clk *hwctl_clk = to_hw_ctl_clk(c); + struct clk *parent = c->parent; + + /* The parent branch clock should have been prepared prior to this. */ + if (!parent || (parent && !parent->prepare_count)) + return -EINVAL; + + _hw_ctl_clk_enable(hwctl_clk); + return 0; +} + +static void _hw_ctl_clk_disable(struct hw_ctl_clk *hwctl_clk) +{ + unsigned long flags; + u32 cbcr_val; + + spin_lock_irqsave(&local_clock_reg_lock, flags); + cbcr_val = readl_relaxed(CBCR_REG(hwctl_clk)); + cbcr_val &= ~CBCR_HW_CTL_BIT; + writel_relaxed(cbcr_val, CBCR_REG(hwctl_clk)); + spin_unlock_irqrestore(&local_clock_reg_lock, flags); +} + +static void hw_ctl_clk_disable(struct clk *c) +{ + struct hw_ctl_clk *hwctl_clk = to_hw_ctl_clk(c); + + if (!c->parent) + return; + + _hw_ctl_clk_disable(hwctl_clk); +} + +static int hw_ctl_clk_set_rate(struct clk *c, unsigned long rate) +{ + struct hw_ctl_clk *hwctl_clk = to_hw_ctl_clk(c); + struct clk *parent = c->parent; + int ret = 0; + + if (!parent) + return -EINVAL; + /* + * Switch back to SW control while doing a frequency change to avoid + * having the downstream clock being gated at the same time that the + * RCG rate switch happens. + */ + _hw_ctl_clk_disable(hwctl_clk); + ret = clk_set_rate(parent, rate); + if (ret) + return ret; + _hw_ctl_clk_enable(hwctl_clk); + + return 0; +} + +static long hw_ctl_clk_round_rate(struct clk *c, unsigned long rate) +{ + return clk_round_rate(c->parent, rate); +} + +static unsigned long hw_ctl_clk_get_rate(struct clk *c) +{ + return clk_get_rate(c->parent); +} + +/* + * Voteable clock functions + */ +static int local_vote_clk_reset(struct clk *c, enum clk_reset_action action) +{ + struct local_vote_clk *vclk = to_local_vote_clk(c); + + if (!vclk->bcr_reg) { + WARN("clk_reset called on an unsupported clock (%s)\n", + c->dbg_name); + return -EPERM; + } + return __branch_clk_reset(BCR_REG(vclk), action); +} + +static void local_vote_clk_disable(struct clk *c) +{ + unsigned long flags; + u32 ena; + struct local_vote_clk *vclk = to_local_vote_clk(c); + + spin_lock_irqsave(&local_clock_reg_lock, flags); + ena = readl_relaxed(VOTE_REG(vclk)); + ena &= ~vclk->en_mask; + writel_relaxed(ena, VOTE_REG(vclk)); + spin_unlock_irqrestore(&local_clock_reg_lock, flags); +} + +static int local_vote_clk_enable(struct clk *c) +{ + unsigned long flags; + u32 ena; + struct local_vote_clk *vclk = to_local_vote_clk(c); + int ret = 0; + + spin_lock_irqsave(&local_clock_reg_lock, flags); + ena = readl_relaxed(VOTE_REG(vclk)); + ena |= vclk->en_mask; + writel_relaxed(ena, VOTE_REG(vclk)); + spin_unlock_irqrestore(&local_clock_reg_lock, flags); + + ret = branch_clk_halt_check(c, vclk->halt_check, CBCR_REG(vclk), + BRANCH_ON); + if (ret) + local_vote_clk_disable(c); + + return ret; +} + +static enum handoff local_vote_clk_handoff(struct clk *c) +{ + struct local_vote_clk *vclk = to_local_vote_clk(c); + u32 vote_regval; + + /* Is the branch voted on by apps? */ + vote_regval = readl_relaxed(VOTE_REG(vclk)); + if (!(vote_regval & vclk->en_mask)) + return HANDOFF_DISABLED_CLK; + + return HANDOFF_ENABLED_CLK; +} + +/* Sample clock for 'ticks' reference clock ticks. */ +static u32 run_measurement(unsigned ticks, void __iomem *ctl_reg, + void __iomem *status_reg) +{ + /* Stop counters and set the XO4 counter start value. */ + writel_relaxed(ticks, ctl_reg); + + /* Wait for timer to become ready. */ + while ((readl_relaxed(status_reg) & BIT(25)) != 0) + cpu_relax(); + + /* Run measurement and wait for completion. */ + writel_relaxed(BIT(20)|ticks, ctl_reg); + while ((readl_relaxed(status_reg) & BIT(25)) == 0) + cpu_relax(); + + /* Return measured ticks. */ + return readl_relaxed(status_reg) & BM(24, 0); +} + +/* + * Perform a hardware rate measurement for a given clock. + * FOR DEBUG USE ONLY: Measurements take ~15 ms! + */ +unsigned long measure_get_rate(struct clk *c) +{ + unsigned long flags; + u32 gcc_xo4_reg, regval; + u64 raw_count_short, raw_count_full; + unsigned ret; + u32 sample_ticks = 0x10000; + u32 multiplier = to_mux_clk(c)->post_div + 1; + struct measure_clk_data *data = to_mux_clk(c)->priv; + + regval = readl_relaxed(MUX_REG(to_mux_clk(c))); + /* clear and set post divider bits */ + regval &= ~BM(15, 12); + regval |= BVAL(15, 12, to_mux_clk(c)->post_div); + writel_relaxed(regval, MUX_REG(to_mux_clk(c))); + + ret = clk_prepare_enable(data->cxo); + if (ret) { + pr_warn("CXO clock failed to enable. Can't measure\n"); + ret = 0; + goto fail; + } + + spin_lock_irqsave(&local_clock_reg_lock, flags); + + /* Enable CXO/4 and RINGOSC branch. */ + gcc_xo4_reg = readl_relaxed(*data->base + data->xo_div4_cbcr); + gcc_xo4_reg |= CBCR_BRANCH_ENABLE_BIT; + writel_relaxed(gcc_xo4_reg, *data->base + data->xo_div4_cbcr); + + /* + * The ring oscillator counter will not reset if the measured clock + * is not running. To detect this, run a short measurement before + * the full measurement. If the raw results of the two are the same + * then the clock must be off. + */ + + /* Run a short measurement. (~1 ms) */ + raw_count_short = run_measurement(0x1000, *data->base + data->ctl_reg, + *data->base + data->status_reg); + /* Run a full measurement. (~14 ms) */ + raw_count_full = run_measurement(sample_ticks, + *data->base + data->ctl_reg, + *data->base + data->status_reg); + + gcc_xo4_reg &= ~CBCR_BRANCH_ENABLE_BIT; + writel_relaxed(gcc_xo4_reg, *data->base + data->xo_div4_cbcr); + + /* Return 0 if the clock is off. */ + if (raw_count_full == raw_count_short) { + ret = 0; + } else { + /* Compute rate in Hz. */ + raw_count_full = ((raw_count_full * 10) + 15) * 4800000; + do_div(raw_count_full, ((sample_ticks * 10) + 35)); + ret = (raw_count_full * multiplier); + } + writel_relaxed(data->plltest_val, *data->base + data->plltest_reg); + spin_unlock_irqrestore(&local_clock_reg_lock, flags); + + clk_disable_unprepare(data->cxo); + +fail: + regval = readl_relaxed(MUX_REG(to_mux_clk(c))); + /* clear post divider bits */ + regval &= ~BM(15, 12); + writel_relaxed(regval, MUX_REG(to_mux_clk(c))); + + return ret; +} + +struct frac_entry { + int num; + int den; +}; + +static void __iomem *local_vote_clk_list_registers(struct clk *c, int n, + struct clk_register_data **regs, u32 *size) +{ + struct local_vote_clk *vclk = to_local_vote_clk(c); + static struct clk_register_data data1[] = { + {"CBCR", 0x0}, + }; + static struct clk_register_data data2[] = { + {"APPS_VOTE", 0x0}, + {"APPS_SLEEP_VOTE", 0x4}, + }; + switch (n) { + case 0: + *regs = data1; + *size = ARRAY_SIZE(data1); + return CBCR_REG(vclk); + case 1: + *regs = data2; + *size = ARRAY_SIZE(data2); + return VOTE_REG(vclk); + default: + return ERR_PTR(-EINVAL); + } +} + +static struct frac_entry frac_table_675m[] = { /* link rate of 270M */ + {52, 295}, /* 119 M */ + {11, 57}, /* 130.25 M */ + {63, 307}, /* 138.50 M */ + {11, 50}, /* 148.50 M */ + {47, 206}, /* 154 M */ + {31, 100}, /* 205.25 M */ + {107, 269}, /* 268.50 M */ + {0, 0}, +}; + +static struct frac_entry frac_table_810m[] = { /* Link rate of 162M */ + {31, 211}, /* 119 M */ + {32, 199}, /* 130.25 M */ + {63, 307}, /* 138.50 M */ + {11, 60}, /* 148.50 M */ + {50, 263}, /* 154 M */ + {31, 120}, /* 205.25 M */ + {119, 359}, /* 268.50 M */ + {0, 0}, +}; + +static int set_rate_edp_pixel(struct clk *clk, unsigned long rate) +{ + struct rcg_clk *rcg = to_rcg_clk(clk); + struct clk_freq_tbl *pixel_freq = rcg->current_freq; + struct frac_entry *frac; + int delta = 100000; + s64 request; + s64 src_rate; + unsigned long flags; + + src_rate = clk_get_rate(clk->parent); + + if (src_rate == 810000000) + frac = frac_table_810m; + else + frac = frac_table_675m; + + while (frac->num) { + request = rate; + request *= frac->den; + request = div_s64(request, frac->num); + if ((src_rate < (request - delta)) || + (src_rate > (request + delta))) { + frac++; + continue; + } + + pixel_freq->div_src_val &= ~BM(4, 0); + if (frac->den == frac->num) { + pixel_freq->m_val = 0; + pixel_freq->n_val = 0; + } else { + pixel_freq->m_val = frac->num; + pixel_freq->n_val = ~(frac->den - frac->num); + pixel_freq->d_val = ~frac->den; + } + spin_lock_irqsave(&local_clock_reg_lock, flags); + __set_rate_mnd(rcg, pixel_freq); + spin_unlock_irqrestore(&local_clock_reg_lock, flags); + return 0; + } + return -EINVAL; +} + +enum handoff byte_rcg_handoff(struct clk *clk) +{ + struct rcg_clk *rcg = to_rcg_clk(clk); + u32 div_val; + unsigned long pre_div_rate, parent_rate = clk_get_rate(clk->parent); + + /* If the pre-divider is used, find the rate after the division */ + div_val = readl_relaxed(CFG_RCGR_REG(rcg)) & CFG_RCGR_DIV_MASK; + if (div_val > 1) + pre_div_rate = parent_rate / ((div_val + 1) >> 1); + else + pre_div_rate = parent_rate; + + clk->rate = pre_div_rate; + + if (readl_relaxed(CMD_RCGR_REG(rcg)) & CMD_RCGR_ROOT_STATUS_BIT) + return HANDOFF_DISABLED_CLK; + + return HANDOFF_ENABLED_CLK; +} + +static int set_rate_byte(struct clk *clk, unsigned long rate) +{ + struct rcg_clk *rcg = to_rcg_clk(clk); + struct clk *pll = clk->parent; + unsigned long source_rate, div, flags; + struct clk_freq_tbl *byte_freq = rcg->current_freq; + int rc; + + if (rate == 0) + return -EINVAL; + + rc = clk_set_rate(pll, rate); + if (rc) + return rc; + + source_rate = clk_round_rate(pll, rate); + if ((2 * source_rate) % rate) + return -EINVAL; + + div = ((2 * source_rate)/rate) - 1; + if (div > CFG_RCGR_DIV_MASK) + return -EINVAL; + + /* + * Both 0 and 1 represent same divider value in HW. + * Always use 0 to simplify comparison. + */ + div = (div == 1) ? 0 : div; + + byte_freq->div_src_val &= ~CFG_RCGR_DIV_MASK; + byte_freq->div_src_val |= BVAL(4, 0, div); + + spin_lock_irqsave(&local_clock_reg_lock, flags); + __set_rate_hid(rcg, byte_freq); + spin_unlock_irqrestore(&local_clock_reg_lock, flags); + + return 0; +} + +enum handoff pixel_rcg_handoff(struct clk *clk) +{ + struct rcg_clk *rcg = to_rcg_clk(clk); + u32 div_val = 0, mval = 0, nval = 0, cfg_regval; + unsigned long pre_div_rate, parent_rate = clk_get_rate(clk->parent); + + cfg_regval = readl_relaxed(CFG_RCGR_REG(rcg)); + + /* If the pre-divider is used, find the rate after the division */ + div_val = cfg_regval & CFG_RCGR_DIV_MASK; + if (div_val > 1) + pre_div_rate = parent_rate / ((div_val + 1) >> 1); + else + pre_div_rate = parent_rate; + + clk->rate = pre_div_rate; + + /* + * Pixel clocks have one frequency entry in their frequency table. + * Update that entry. + */ + if (rcg->current_freq) { + rcg->current_freq->div_src_val &= ~CFG_RCGR_DIV_MASK; + rcg->current_freq->div_src_val |= div_val; + } + + /* If MND is used, find the rate after the MND division */ + if ((cfg_regval & MND_MODE_MASK) == MND_DUAL_EDGE_MODE_BVAL) { + mval = readl_relaxed(M_REG(rcg)); + nval = readl_relaxed(N_REG(rcg)); + if (!nval) + return HANDOFF_DISABLED_CLK; + nval = (~nval) + mval; + if (rcg->current_freq) { + rcg->current_freq->n_val = ~(nval - mval); + rcg->current_freq->m_val = mval; + rcg->current_freq->d_val = ~nval; + } + clk->rate = (pre_div_rate * mval) / nval; + } + + if (readl_relaxed(CMD_RCGR_REG(rcg)) & CMD_RCGR_ROOT_STATUS_BIT) + return HANDOFF_DISABLED_CLK; + + return HANDOFF_ENABLED_CLK; +} + +static long round_rate_pixel(struct clk *clk, unsigned long rate) +{ + int frac_num[] = {3, 2, 4, 1}; + int frac_den[] = {8, 9, 9, 1}; + int delta = 100000; + int i; + + for (i = 0; i < ARRAY_SIZE(frac_num); i++) { + unsigned long request = (rate * frac_den[i]) / frac_num[i]; + unsigned long src_rate; + + src_rate = clk_round_rate(clk->parent, request); + if ((src_rate < (request - delta)) || + (src_rate > (request + delta))) + continue; + + return (src_rate * frac_num[i]) / frac_den[i]; + } + + return -EINVAL; +} + + +static int set_rate_pixel(struct clk *clk, unsigned long rate) +{ + struct rcg_clk *rcg = to_rcg_clk(clk); + struct clk_freq_tbl *pixel_freq = rcg->current_freq; + int frac_num[] = {1, 2, 4, 3, 2}; + int frac_den[] = {1, 3, 9, 8, 9}; + int delta = 100000; + int i, rc; + + for (i = 0; i < ARRAY_SIZE(frac_num); i++) { + unsigned long request = (rate * frac_den[i]) / frac_num[i]; + unsigned long src_rate; + + src_rate = clk_round_rate(clk->parent, request); + if ((src_rate < (request - delta)) || + (src_rate > (request + delta))) + continue; + + rc = clk_set_rate(clk->parent, src_rate); + if (rc) + return rc; + + pixel_freq->div_src_val &= ~BM(4, 0); + if (frac_den[i] == frac_num[i]) { + pixel_freq->m_val = 0; + pixel_freq->n_val = 0; + } else { + pixel_freq->m_val = frac_num[i]; + pixel_freq->n_val = ~(frac_den[i] - frac_num[i]); + pixel_freq->d_val = ~frac_den[i]; + } + set_rate_mnd(rcg, pixel_freq); + return 0; + } + return -EINVAL; +} + +static int rcg_clk_set_parent(struct clk *clk, struct clk *parent_clk) +{ + struct rcg_clk *rcg = to_rcg_clk(clk); + struct clk *old_parent = clk->parent; + struct clk_freq_tbl *nf; + unsigned long flags; + int rc = 0; + unsigned int parent_rate, rate; + u32 m_val, n_val, d_val, div_val; + u32 cfg_regval; + + /* Find the source clock freq tbl for the requested parent */ + if (!rcg->freq_tbl) + return -ENXIO; + + for (nf = rcg->freq_tbl; parent_clk != nf->src_clk; nf++) { + if (nf->freq_hz == FREQ_END) + return -ENXIO; + } + + /* This implementation recommends that the RCG be unprepared + * when switching RCG source since the divider configuration + * remains unchanged. + */ + WARN(clk->prepare_count, + "Trying to switch RCG source while it is prepared!\n"); + + parent_rate = clk_get_rate(parent_clk); + + div_val = (rcg->current_freq->div_src_val & CFG_RCGR_DIV_MASK); + if (div_val) + parent_rate /= ((div_val + 1) >> 1); + + /* Update divisor. Source select bits should already be as expected */ + nf->div_src_val &= ~CFG_RCGR_DIV_MASK; + nf->div_src_val |= div_val; + + cfg_regval = readl_relaxed(CFG_RCGR_REG(rcg)); + + if ((cfg_regval & MND_MODE_MASK) == MND_DUAL_EDGE_MODE_BVAL) { + nf->m_val = m_val = readl_relaxed(M_REG(rcg)); + n_val = readl_relaxed(N_REG(rcg)); + d_val = readl_relaxed(D_REG(rcg)); + + /* Sign extend the n and d values as those in registers are not + * sign extended. + */ + n_val |= (n_val >> 8) ? BM(31, 16) : BM(31, 8); + d_val |= (d_val >> 8) ? BM(31, 16) : BM(31, 8); + + nf->n_val = n_val; + nf->d_val = d_val; + + n_val = ~(n_val) + m_val; + rate = parent_rate * m_val; + if (n_val) + rate /= n_val; + else + WARN(1, "n_val was 0!!"); + } else + rate = parent_rate; + + /* Warn if switching to the new parent with the current m, n ,d values + * violates the voltage constraints for the RCG. + */ + WARN(!is_rate_valid(clk, rate) && clk->prepare_count, + "Switch to new RCG parent violates voltage requirement!\n"); + + rc = __clk_pre_reparent(clk, nf->src_clk, &flags); + if (rc) + return rc; + + /* Switch RCG source */ + rcg->set_rate(rcg, nf); + + rcg->current_freq = nf; + clk->parent = parent_clk; + clk->rate = rate; + + __clk_post_reparent(clk, old_parent, &flags); + + return 0; +} + +/* + * Unlike other clocks, the HDMI rate is adjusted through PLL + * re-programming. It is also routed through an HID divider. + */ +static int rcg_clk_set_rate_hdmi(struct clk *c, unsigned long rate) +{ + struct rcg_clk *rcg = to_rcg_clk(c); + struct clk_freq_tbl *nf = rcg->freq_tbl; + int rc; + + rc = clk_set_rate(nf->src_clk, rate); + if (rc < 0) + goto out; + set_rate_hid(rcg, nf); + + rcg->current_freq = nf; +out: + return rc; +} + +static struct clk *rcg_hdmi_clk_get_parent(struct clk *c) +{ + struct rcg_clk *rcg = to_rcg_clk(c); + struct clk_freq_tbl *freq = rcg->freq_tbl; + u32 cmd_rcgr_regval; + + /* Is there a pending configuration? */ + cmd_rcgr_regval = readl_relaxed(CMD_RCGR_REG(rcg)); + if (cmd_rcgr_regval & CMD_RCGR_CONFIG_DIRTY_MASK) + return NULL; + + rcg->current_freq->freq_hz = clk_get_rate(c->parent); + + return freq->src_clk; +} + +static int rcg_clk_set_rate_edp(struct clk *c, unsigned long rate) +{ + struct clk_freq_tbl *nf; + struct rcg_clk *rcg = to_rcg_clk(c); + int rc; + + for (nf = rcg->freq_tbl; nf->freq_hz != rate; nf++) + if (nf->freq_hz == FREQ_END) { + rc = -EINVAL; + goto out; + } + + rc = clk_set_rate(nf->src_clk, rate); + if (rc < 0) + goto out; + set_rate_hid(rcg, nf); + + rcg->current_freq = nf; + c->parent = nf->src_clk; +out: + return rc; +} + +static struct clk *edp_clk_get_parent(struct clk *c) +{ + struct rcg_clk *rcg = to_rcg_clk(c); + struct clk *clk; + struct clk_freq_tbl *freq; + unsigned long rate; + u32 cmd_rcgr_regval; + + /* Is there a pending configuration? */ + cmd_rcgr_regval = readl_relaxed(CMD_RCGR_REG(rcg)); + if (cmd_rcgr_regval & CMD_RCGR_CONFIG_DIRTY_MASK) + return NULL; + + /* Figure out what rate the rcg is running at */ + for (freq = rcg->freq_tbl; freq->freq_hz != FREQ_END; freq++) { + clk = freq->src_clk; + if (clk && clk->ops->get_rate) { + rate = clk->ops->get_rate(clk); + if (rate == freq->freq_hz) + break; + } + } + + /* No known frequency found */ + if (freq->freq_hz == FREQ_END) + return NULL; + + rcg->current_freq = freq; + return freq->src_clk; +} + +static int rcg_clk_set_rate_dp(struct clk *clk, unsigned long rate) +{ + struct rcg_clk *rcg = to_rcg_clk(clk); + struct clk_freq_tbl *freq_tbl = rcg->current_freq; + unsigned long src_rate; + unsigned long num, den, flags; + + src_rate = clk_get_rate(clk->parent); + if (src_rate <= 0) { + pr_err("Invalid RCG parent rate\n"); + return -EINVAL; + } + + rational_best_approximation(src_rate, rate, + (unsigned long)(1 << 16) - 1, + (unsigned long)(1 << 16) - 1, &den, &num); + + if (!num || !den) { + pr_err("Invalid MN values derived for requested rate %lu\n", + rate); + return -EINVAL; + } + + freq_tbl->div_src_val &= ~BM(4, 0); + if (num == den) { + freq_tbl->m_val = 0; + freq_tbl->n_val = 0; + } else { + freq_tbl->m_val = num; + freq_tbl->n_val = ~(den - num); + freq_tbl->d_val = ~den; + } + + spin_lock_irqsave(&local_clock_reg_lock, flags); + __set_rate_mnd(rcg, freq_tbl); + spin_unlock_irqrestore(&local_clock_reg_lock, flags); + return 0; +} + +static int gate_clk_enable(struct clk *c) +{ + unsigned long flags; + u32 regval; + struct gate_clk *g = to_gate_clk(c); + + spin_lock_irqsave(&local_clock_reg_lock, flags); + regval = readl_relaxed(GATE_EN_REG(g)); + regval |= g->en_mask; + writel_relaxed(regval, GATE_EN_REG(g)); + spin_unlock_irqrestore(&local_clock_reg_lock, flags); + if (g->delay_us) + udelay(g->delay_us); + + return 0; +} + +static void gate_clk_disable(struct clk *c) +{ + unsigned long flags; + u32 regval; + struct gate_clk *g = to_gate_clk(c); + + spin_lock_irqsave(&local_clock_reg_lock, flags); + regval = readl_relaxed(GATE_EN_REG(g)); + regval &= ~(g->en_mask); + writel_relaxed(regval, GATE_EN_REG(g)); + spin_unlock_irqrestore(&local_clock_reg_lock, flags); + if (g->delay_us) + udelay(g->delay_us); +} + +static void __iomem *gate_clk_list_registers(struct clk *c, int n, + struct clk_register_data **regs, u32 *size) +{ + struct gate_clk *g = to_gate_clk(c); + static struct clk_register_data data[] = { + {"EN_REG", 0x0}, + }; + if (n) + return ERR_PTR(-EINVAL); + + *regs = data; + *size = ARRAY_SIZE(data); + return GATE_EN_REG(g); +} + +static enum handoff gate_clk_handoff(struct clk *c) +{ + struct gate_clk *g = to_gate_clk(c); + u32 regval; + + regval = readl_relaxed(GATE_EN_REG(g)); + if (regval & g->en_mask) + return HANDOFF_ENABLED_CLK; + + return HANDOFF_DISABLED_CLK; +} + +static int gate_clk_set_flags(struct clk *c, unsigned flags) +{ + return cbcr_set_flags(GATE_EN_REG(to_gate_clk(c)), flags); +} + + +static int reset_clk_rst(struct clk *c, enum clk_reset_action action) +{ + struct reset_clk *rst = to_reset_clk(c); + + if (!rst->reset_reg) + return -EPERM; + + return __branch_clk_reset(RST_REG(rst), action); +} + +static void __iomem *reset_clk_list_registers(struct clk *clk, int n, + struct clk_register_data **regs, u32 *size) +{ + struct reset_clk *rst = to_reset_clk(clk); + static struct clk_register_data data[] = { + {"BCR", 0x0}, + }; + + if (n) + return ERR_PTR(-EINVAL); + + *regs = data; + *size = ARRAY_SIZE(data); + return RST_REG(rst); +} + +static DEFINE_SPINLOCK(mux_reg_lock); + +static int mux_reg_enable(struct mux_clk *clk) +{ + u32 regval; + unsigned long flags; + + if (!clk->en_mask) + return 0; + + spin_lock_irqsave(&mux_reg_lock, flags); + regval = readl_relaxed(*clk->base + clk->en_offset); + regval |= clk->en_mask; + writel_relaxed(regval, *clk->base + clk->en_offset); + /* Ensure enable request goes through before returning */ + mb(); + spin_unlock_irqrestore(&mux_reg_lock, flags); + + return 0; +} + +static void mux_reg_disable(struct mux_clk *clk) +{ + u32 regval; + unsigned long flags; + + if (!clk->en_mask) + return; + + spin_lock_irqsave(&mux_reg_lock, flags); + regval = readl_relaxed(*clk->base + clk->en_offset); + regval &= ~clk->en_mask; + writel_relaxed(regval, *clk->base + clk->en_offset); + spin_unlock_irqrestore(&mux_reg_lock, flags); +} + +static int mux_reg_set_mux_sel(struct mux_clk *clk, int sel) +{ + u32 regval; + unsigned long flags; + + spin_lock_irqsave(&mux_reg_lock, flags); + regval = readl_relaxed(MUX_REG(clk)); + regval &= ~(clk->mask << clk->shift); + regval |= (sel & clk->mask) << clk->shift; + writel_relaxed(regval, MUX_REG(clk)); + /* Ensure switch request goes through before returning */ + mb(); + spin_unlock_irqrestore(&mux_reg_lock, flags); + + return 0; +} + +static int mux_reg_get_mux_sel(struct mux_clk *clk) +{ + u32 regval = readl_relaxed(MUX_REG(clk)); + return (regval >> clk->shift) & clk->mask; +} + +static bool mux_reg_is_enabled(struct mux_clk *clk) +{ + u32 regval = readl_relaxed(MUX_REG(clk)); + return !!(regval & clk->en_mask); +} + +static void __iomem *mux_clk_list_registers(struct mux_clk *clk, int n, + struct clk_register_data **regs, u32 *size) +{ + static struct clk_register_data data[] = { + {"DEBUG_CLK_CTL", 0x0}, + }; + + if (n) + return ERR_PTR(-EINVAL); + + *regs = data; + *size = ARRAY_SIZE(data); + return *clk->base + clk->offset; +} + +/* PLL post-divider setting for each divider value */ +static struct div_map postdiv_map[] = { + { 0x0, 1 }, + { 0x1, 2 }, + { 0x3, 3 }, + { 0x3, 4 }, + { 0x5, 5 }, + { 0x7, 7 }, + { 0x7, 8 }, + { 0xF, 16 }, +}; + +static int postdiv_reg_set_div(struct div_clk *clk, int div) +{ + struct clk *parent = NULL; + u32 regval; + unsigned long flags; + unsigned int mask = -1; + int i, ret = 0; + + /* Divider is not configurable */ + if (!clk->mask) + return 0; + + for (i = 0; i < ARRAY_SIZE(postdiv_map); i++) { + if (postdiv_map[i].div == div) { + mask = postdiv_map[i].mask; + break; + } + } + + if (mask < 0) + return -EINVAL; + + spin_lock_irqsave(&clk->c.lock, flags); + parent = clk->c.parent; + if (parent->count && parent->ops->disable) + parent->ops->disable(parent); + + regval = readl_relaxed(DIV_REG(clk)); + regval &= ~(clk->mask << clk->shift); + regval |= (mask & clk->mask) << clk->shift; + writel_relaxed(regval, DIV_REG(clk)); + /* Ensure switch request goes through before returning */ + mb(); + + if (parent->count && parent->ops->enable) { + ret = parent->ops->enable(parent); + if (ret) + pr_err("Failed to force enable div parent!\n"); + } + + spin_unlock_irqrestore(&clk->c.lock, flags); + return ret; +} + +static int postdiv_reg_get_div(struct div_clk *clk) +{ + u32 regval; + int i, div = 0; + + /* Divider is not configurable */ + if (!clk->mask) + return clk->data.div; + + regval = readl_relaxed(DIV_REG(clk)); + regval = (regval >> clk->shift) & clk->mask; + for (i = 0; i < ARRAY_SIZE(postdiv_map); i++) { + if (postdiv_map[i].mask == regval) { + div = postdiv_map[i].div; + break; + } + } + if (!div) + return -EINVAL; + + return div; +} + +static int div_reg_set_div(struct div_clk *clk, int div) +{ + u32 regval; + unsigned long flags; + + /* Divider is not configurable */ + if (!clk->mask) + return 0; + + spin_lock_irqsave(&local_clock_reg_lock, flags); + regval = readl_relaxed(*clk->base + clk->offset); + regval &= ~(clk->mask << clk->shift); + regval |= (div & clk->mask) << clk->shift; + /* Ensure switch request goes through before returning */ + mb(); + spin_unlock_irqrestore(&local_clock_reg_lock, flags); + + return 0; +} + +static int div_reg_get_div(struct div_clk *clk) +{ + u32 regval; + /* Divider is not configurable */ + if (!clk->mask) + return clk->data.div; + + regval = readl_relaxed(*clk->base + clk->offset); + return (regval >> clk->shift) & clk->mask; +} + +/* =================Half-integer RCG without MN counter================= */ +#define RCGR_CMD_REG(x) ((x)->base + (x)->div_offset) +#define RCGR_DIV_REG(x) ((x)->base + (x)->div_offset + 4) +#define RCGR_SRC_REG(x) ((x)->base + (x)->div_offset + 4) + +static int rcg_mux_div_update_config(struct mux_div_clk *md) +{ + u32 regval, count; + + regval = readl_relaxed(RCGR_CMD_REG(md)); + regval |= CMD_RCGR_CONFIG_UPDATE_BIT; + writel_relaxed(regval, RCGR_CMD_REG(md)); + + /* Wait for update to take effect */ + for (count = UPDATE_CHECK_MAX_LOOPS; count > 0; count--) { + if (!(readl_relaxed(RCGR_CMD_REG(md)) & + CMD_RCGR_CONFIG_UPDATE_BIT)) + return 0; + udelay(1); + } + + CLK_WARN(&md->c, true, "didn't update its configuration."); + + return -EBUSY; +} + +static void rcg_get_src_div(struct mux_div_clk *md, u32 *src_sel, u32 *div) +{ + u32 regval; + unsigned long flags; + + spin_lock_irqsave(&local_clock_reg_lock, flags); + /* Is there a pending configuration? */ + regval = readl_relaxed(RCGR_CMD_REG(md)); + if (regval & CMD_RCGR_CONFIG_DIRTY_MASK) { + CLK_WARN(&md->c, true, "it's a pending configuration."); + spin_unlock_irqrestore(&local_clock_reg_lock, flags); + return; + } + + regval = readl_relaxed(RCGR_DIV_REG(md)); + regval &= (md->div_mask << md->div_shift); + *div = regval >> md->div_shift; + + /* bypass */ + if (*div == 0) + *div = 1; + /* the div is doubled here*/ + *div += 1; + + regval = readl_relaxed(RCGR_SRC_REG(md)); + regval &= (md->src_mask << md->src_shift); + *src_sel = regval >> md->src_shift; + spin_unlock_irqrestore(&local_clock_reg_lock, flags); +} + +static void mux_div_set_force_enable(struct mux_div_clk *md) +{ + u32 regval; + unsigned long flags; + int count; + + spin_lock_irqsave(&local_clock_reg_lock, flags); + regval = readl_relaxed(RCGR_CMD_REG(md)); + regval |= CMD_RCGR_ROOT_ENABLE_BIT; + writel_relaxed(regval, RCGR_CMD_REG(md)); + + /* Wait for RCG to turn ON */ + for (count = UPDATE_CHECK_MAX_LOOPS; count > 0; count--) { + if (!(readl_relaxed(RCGR_CMD_REG(md)) & + CMD_RCGR_CONFIG_UPDATE_BIT)) + goto exit; + udelay(1); + } + CLK_WARN(&md->c, count == 0, "rcg didn't turn on."); +exit: + spin_unlock_irqrestore(&local_clock_reg_lock, flags); +} + +static void mux_div_clear_force_enable(struct mux_div_clk *md) +{ + u32 regval; + unsigned long flags; + + spin_lock_irqsave(&local_clock_reg_lock, flags); + regval = readl_relaxed(RCGR_CMD_REG(md)); + regval &= ~CMD_RCGR_ROOT_ENABLE_BIT; + writel_relaxed(regval, RCGR_CMD_REG(md)); + spin_unlock_irqrestore(&local_clock_reg_lock, flags); +} + +static int rcg_set_src_div(struct mux_div_clk *md, u32 src_sel, u32 div) +{ + u32 regval; + unsigned long flags; + int ret; + + /* for half-integer divider, div here is doubled */ + if (div) + div -= 1; + + spin_lock_irqsave(&local_clock_reg_lock, flags); + regval = readl_relaxed(RCGR_DIV_REG(md)); + regval &= ~(md->div_mask << md->div_shift); + regval |= div << md->div_shift; + writel_relaxed(regval, RCGR_DIV_REG(md)); + + regval = readl_relaxed(RCGR_SRC_REG(md)); + regval &= ~(md->src_mask << md->src_shift); + regval |= src_sel << md->src_shift; + writel_relaxed(regval, RCGR_SRC_REG(md)); + + ret = rcg_mux_div_update_config(md); + spin_unlock_irqrestore(&local_clock_reg_lock, flags); + return ret; +} + +static int rcg_enable(struct mux_div_clk *md) +{ + if (md->force_enable_md) + mux_div_set_force_enable(md); + + return rcg_set_src_div(md, md->src_sel, md->data.div); +} + +static void rcg_disable(struct mux_div_clk *md) +{ + u32 src_sel; + + if (md->force_enable_md) + mux_div_clear_force_enable(md); + + if (!md->safe_freq) + return; + + src_sel = parent_to_src_sel(md->parents, md->num_parents, + md->safe_parent); + + rcg_set_src_div(md, src_sel, md->safe_div); +} + +static bool rcg_is_enabled(struct mux_div_clk *md) +{ + u32 regval; + + regval = readl_relaxed(RCGR_CMD_REG(md)); + if (regval & CMD_RCGR_ROOT_STATUS_BIT) + return false; + else + return true; +} + +static void __iomem *rcg_list_registers(struct mux_div_clk *md, int n, + struct clk_register_data **regs, u32 *size) +{ + static struct clk_register_data data[] = { + {"CMD_RCGR", 0x0}, + {"CFG_RCGR", 0x4}, + }; + + if (n) + return ERR_PTR(-EINVAL); + + *regs = data; + *size = ARRAY_SIZE(data); + return RCGR_CMD_REG(md); +} + +struct clk_ops clk_ops_empty; + +struct clk_ops clk_ops_rst = { + .reset = reset_clk_rst, + .list_registers = reset_clk_list_registers, +}; + +struct clk_ops clk_ops_rcg = { + .enable = rcg_clk_enable, + .disable = rcg_clk_disable, + .set_rate = rcg_clk_set_rate, + .list_rate = rcg_clk_list_rate, + .round_rate = rcg_clk_round_rate, + .handoff = rcg_clk_handoff, + .get_parent = rcg_clk_get_parent, + .set_parent = rcg_clk_set_parent, + .list_registers = rcg_hid_clk_list_registers, +}; + +struct clk_ops clk_ops_rcg_mnd = { + .enable = rcg_clk_enable, + .disable = rcg_clk_disable, + .set_rate = rcg_clk_set_rate, + .list_rate = rcg_clk_list_rate, + .round_rate = rcg_clk_round_rate, + .handoff = rcg_mnd_clk_handoff, + .get_parent = rcg_mnd_clk_get_parent, + .set_parent = rcg_clk_set_parent, + .list_registers = rcg_mnd_clk_list_registers, +}; + +struct clk_ops clk_ops_pixel = { + .enable = rcg_clk_enable, + .disable = rcg_clk_disable, + .set_rate = set_rate_pixel, + .list_rate = rcg_clk_list_rate, + .round_rate = round_rate_pixel, + .handoff = pixel_rcg_handoff, + .list_registers = rcg_mnd_clk_list_registers, +}; + +struct clk_ops clk_ops_pixel_multiparent = { + .enable = rcg_clk_enable, + .disable = rcg_clk_disable, + .set_rate = set_rate_pixel, + .list_rate = rcg_clk_list_rate, + .round_rate = round_rate_pixel, + .handoff = pixel_rcg_handoff, + .list_registers = rcg_mnd_clk_list_registers, + .get_parent = display_clk_get_parent, + .set_parent = rcg_clk_set_parent, +}; + +struct clk_ops clk_ops_edppixel = { + .enable = rcg_clk_enable, + .disable = rcg_clk_disable, + .set_rate = set_rate_edp_pixel, + .list_rate = rcg_clk_list_rate, + .round_rate = rcg_clk_round_rate, + .handoff = pixel_rcg_handoff, + .list_registers = rcg_mnd_clk_list_registers, +}; + +struct clk_ops clk_ops_byte = { + .enable = rcg_clk_enable, + .disable = rcg_clk_disable, + .set_rate = set_rate_byte, + .list_rate = rcg_clk_list_rate, + .round_rate = rcg_clk_round_rate, + .handoff = byte_rcg_handoff, + .list_registers = rcg_hid_clk_list_registers, +}; + +struct clk_ops clk_ops_byte_multiparent = { + .enable = rcg_clk_enable, + .disable = rcg_clk_disable, + .set_rate = set_rate_byte, + .list_rate = rcg_clk_list_rate, + .round_rate = rcg_clk_round_rate, + .handoff = byte_rcg_handoff, + .list_registers = rcg_hid_clk_list_registers, + .get_parent = display_clk_get_parent, + .set_parent = rcg_clk_set_parent, +}; + +struct clk_ops clk_ops_rcg_hdmi = { + .enable = rcg_clk_enable, + .disable = rcg_clk_disable, + .set_rate = rcg_clk_set_rate_hdmi, + .list_rate = rcg_clk_list_rate, + .round_rate = rcg_clk_round_rate, + .handoff = rcg_clk_handoff, + .get_parent = rcg_hdmi_clk_get_parent, + .list_registers = rcg_hid_clk_list_registers, +}; + +struct clk_ops clk_ops_rcg_edp = { + .enable = rcg_clk_enable, + .disable = rcg_clk_disable, + .set_rate = rcg_clk_set_rate_edp, + .list_rate = rcg_clk_list_rate, + .round_rate = rcg_clk_round_rate, + .handoff = rcg_clk_handoff, + .get_parent = edp_clk_get_parent, + .list_registers = rcg_hid_clk_list_registers, +}; + +struct clk_ops clk_ops_rcg_dp = { + .enable = rcg_clk_enable, + .disable = rcg_clk_disable, + .set_rate = rcg_clk_set_rate_dp, + .list_rate = rcg_clk_list_rate, + .handoff = pixel_rcg_handoff, + .list_registers = rcg_mnd_clk_list_registers, +}; + +struct clk_ops clk_ops_branch = { + .enable = branch_clk_enable, + .prepare = branch_clk_prepare, + .disable = branch_clk_disable, + .unprepare = branch_clk_unprepare, + .set_rate = branch_clk_set_rate, + .get_rate = branch_clk_get_rate, + .list_rate = branch_clk_list_rate, + .round_rate = branch_clk_round_rate, + .reset = branch_clk_reset, + .set_flags = branch_clk_set_flags, + .handoff = branch_clk_handoff, + .list_registers = branch_clk_list_registers, +}; + +struct clk_ops clk_ops_branch_hw_ctl = { + .enable = hw_ctl_clk_enable, + .disable = hw_ctl_clk_disable, + .set_rate = hw_ctl_clk_set_rate, + .get_rate = hw_ctl_clk_get_rate, + .round_rate = hw_ctl_clk_round_rate, +}; + +struct clk_ops clk_ops_vote = { + .enable = local_vote_clk_enable, + .disable = local_vote_clk_disable, + .reset = local_vote_clk_reset, + .handoff = local_vote_clk_handoff, + .list_registers = local_vote_clk_list_registers, +}; + +struct clk_ops clk_ops_gate = { + .enable = gate_clk_enable, + .disable = gate_clk_disable, + .set_rate = parent_set_rate, + .get_rate = parent_get_rate, + .round_rate = parent_round_rate, + .set_flags = gate_clk_set_flags, + .handoff = gate_clk_handoff, + .list_registers = gate_clk_list_registers, +}; + +struct clk_mux_ops mux_reg_ops = { + .enable = mux_reg_enable, + .disable = mux_reg_disable, + .set_mux_sel = mux_reg_set_mux_sel, + .get_mux_sel = mux_reg_get_mux_sel, + .is_enabled = mux_reg_is_enabled, + .list_registers = mux_clk_list_registers, +}; + +struct clk_div_ops div_reg_ops = { + .set_div = div_reg_set_div, + .get_div = div_reg_get_div, +}; + +struct clk_div_ops postdiv_reg_ops = { + .set_div = postdiv_reg_set_div, + .get_div = postdiv_reg_get_div, +}; + +struct mux_div_ops rcg_mux_div_ops = { + .enable = rcg_enable, + .disable = rcg_disable, + .set_src_div = rcg_set_src_div, + .get_src_div = rcg_get_src_div, + .is_enabled = rcg_is_enabled, + .list_registers = rcg_list_registers, +}; + +static void *cbc_dt_parser(struct device *dev, struct device_node *np) +{ + struct msmclk_data *drv; + struct branch_clk *branch_clk; + u32 rc; + + branch_clk = devm_kzalloc(dev, sizeof(*branch_clk), GFP_KERNEL); + if (!branch_clk) { + dt_err(np, "memory alloc failure\n"); + return ERR_PTR(-ENOMEM); + } + + drv = msmclk_parse_phandle(dev, np->parent->phandle); + if (IS_ERR_OR_NULL(drv)) + return ERR_CAST(drv); + branch_clk->base = &drv->base; + + rc = of_property_read_u32(np, "qcom,base-offset", + &branch_clk->cbcr_reg); + if (rc) { + dt_err(np, "missing/incorrect qcom,base-offset dt property\n"); + return ERR_PTR(rc); + } + + /* Optional property */ + of_property_read_u32(np, "qcom,bcr-offset", &branch_clk->bcr_reg); + + branch_clk->has_sibling = of_property_read_bool(np, + "qcom,has-sibling"); + + branch_clk->c.ops = &clk_ops_branch; + + return msmclk_generic_clk_init(dev, np, &branch_clk->c); +} +MSMCLK_PARSER(cbc_dt_parser, "qcom,cbc", 0); + +static void *local_vote_clk_dt_parser(struct device *dev, + struct device_node *np) +{ + struct local_vote_clk *vote_clk; + struct msmclk_data *drv; + int rc, val; + + vote_clk = devm_kzalloc(dev, sizeof(*vote_clk), GFP_KERNEL); + if (!vote_clk) { + dt_err(np, "failed to alloc memory\n"); + return ERR_PTR(-ENOMEM); + } + + drv = msmclk_parse_phandle(dev, np->parent->phandle); + if (IS_ERR_OR_NULL(drv)) + return ERR_CAST(drv); + vote_clk->base = &drv->base; + + rc = of_property_read_u32(np, "qcom,base-offset", + &vote_clk->cbcr_reg); + if (rc) { + dt_err(np, "missing/incorrect qcom,base-offset dt property\n"); + return ERR_PTR(-EINVAL); + } + + rc = of_property_read_u32(np, "qcom,en-offset", &vote_clk->vote_reg); + if (rc) { + dt_err(np, "missing/incorrect qcom,en-offset dt property\n"); + return ERR_PTR(-EINVAL); + } + + rc = of_property_read_u32(np, "qcom,en-bit", &val); + if (rc) { + dt_err(np, "missing/incorrect qcom,en-bit dt property\n"); + return ERR_PTR(-EINVAL); + } + vote_clk->en_mask = BIT(val); + + vote_clk->c.ops = &clk_ops_vote; + + /* Optional property */ + of_property_read_u32(np, "qcom,bcr-offset", &vote_clk->bcr_reg); + + return msmclk_generic_clk_init(dev, np, &vote_clk->c); +} +MSMCLK_PARSER(local_vote_clk_dt_parser, "qcom,local-vote-clk", 0); + +static void *gate_clk_dt_parser(struct device *dev, struct device_node *np) +{ + struct gate_clk *gate_clk; + struct msmclk_data *drv; + u32 en_bit, rc; + + gate_clk = devm_kzalloc(dev, sizeof(*gate_clk), GFP_KERNEL); + if (!gate_clk) { + dt_err(np, "memory alloc failure\n"); + return ERR_PTR(-ENOMEM); + } + + drv = msmclk_parse_phandle(dev, np->parent->phandle); + if (IS_ERR_OR_NULL(drv)) + return ERR_CAST(drv); + gate_clk->base = &drv->base; + + rc = of_property_read_u32(np, "qcom,en-offset", &gate_clk->en_reg); + if (rc) { + dt_err(np, "missing qcom,en-offset dt property\n"); + return ERR_PTR(-EINVAL); + } + + rc = of_property_read_u32(np, "qcom,en-bit", &en_bit); + if (rc) { + dt_err(np, "missing qcom,en-bit dt property\n"); + return ERR_PTR(-EINVAL); + } + gate_clk->en_mask = BIT(en_bit); + + /* Optional Property */ + rc = of_property_read_u32(np, "qcom,delay", &gate_clk->delay_us); + if (rc) + gate_clk->delay_us = 0; + + gate_clk->c.ops = &clk_ops_gate; + return msmclk_generic_clk_init(dev, np, &gate_clk->c); +} +MSMCLK_PARSER(gate_clk_dt_parser, "qcom,gate-clk", 0); + + +static inline u32 rcg_calc_m(u32 m, u32 n) +{ + return m; +} + +static inline u32 rcg_calc_n(u32 m, u32 n) +{ + n = n > 1 ? n : 0; + return ~((n)-(m)) * !!(n); +} + +static inline u32 rcg_calc_duty_cycle(u32 m, u32 n) +{ + return ~n; +} + +static inline u32 rcg_calc_div_src(u32 div_int, u32 div_frac, u32 src_sel) +{ + int div = 2 * div_int + (div_frac ? 1 : 0) - 1; + /* set bypass mode instead of a divider of 1 */ + div = (div != 1) ? div : 0; + return BVAL(4, 0, max(div, 0)) + | BVAL(10, 8, src_sel); +} + +struct clk_src *msmclk_parse_clk_src(struct device *dev, + struct device_node *np, int *array_size) +{ + struct clk_src *clks; + const void *prop; + int num_parents, len, i, prop_len, rc; + char *name = "qcom,parents"; + + if (!array_size) { + dt_err(np, "array_size must be a valid pointer\n"); + return ERR_PTR(-EINVAL); + } + + prop = of_get_property(np, name, &prop_len); + if (!prop) { + dt_prop_err(np, name, "missing dt property\n"); + return ERR_PTR(-EINVAL); + } + + len = sizeof(phandle) + sizeof(u32); + if (prop_len % len) { + dt_prop_err(np, name, "invalid property length\n"); + return ERR_PTR(-EINVAL); + } + num_parents = prop_len / len; + + clks = devm_kzalloc(dev, sizeof(*clks) * num_parents, GFP_KERNEL); + if (!clks) { + dt_err(np, "memory alloc failure\n"); + return ERR_PTR(-ENOMEM); + } + + /* Assume that u32 and phandle have the same size */ + for (i = 0; i < num_parents; i++) { + phandle p; + struct clk_src *a = &clks[i]; + + rc = of_property_read_u32_index(np, name, 2 * i, &a->sel); + rc |= of_property_read_phandle_index(np, name, 2 * i + 1, &p); + + if (rc) { + dt_prop_err(np, name, + "unable to read parent clock or mux index\n"); + return ERR_PTR(-EINVAL); + } + + a->src = msmclk_parse_phandle(dev, p); + if (IS_ERR(a->src)) { + dt_prop_err(np, name, "hashtable lookup failed\n"); + return ERR_CAST(a->src); + } + } + + *array_size = num_parents; + + return clks; +} + +static int rcg_parse_freq_tbl(struct device *dev, + struct device_node *np, struct rcg_clk *rcg) +{ + const void *prop; + u32 prop_len, num_rows, i, j = 0; + struct clk_freq_tbl *tbl; + int rc; + char *name = "qcom,freq-tbl"; + + prop = of_get_property(np, name, &prop_len); + if (!prop) { + dt_prop_err(np, name, "missing dt property\n"); + return -EINVAL; + } + + prop_len /= sizeof(u32); + if (prop_len % 6) { + dt_prop_err(np, name, "bad length\n"); + return -EINVAL; + } + + num_rows = prop_len / 6; + /* Array is null terminated. */ + rcg->freq_tbl = devm_kzalloc(dev, + sizeof(*rcg->freq_tbl) * (num_rows + 1), + GFP_KERNEL); + + if (!rcg->freq_tbl) { + dt_err(np, "memory alloc failure\n"); + return -ENOMEM; + } + + tbl = rcg->freq_tbl; + for (i = 0; i < num_rows; i++, tbl++) { + phandle p; + u32 div_int, div_frac, m, n, src_sel, freq_hz; + + rc = of_property_read_u32_index(np, name, j++, &freq_hz); + rc |= of_property_read_u32_index(np, name, j++, &div_int); + rc |= of_property_read_u32_index(np, name, j++, &div_frac); + rc |= of_property_read_u32_index(np, name, j++, &m); + rc |= of_property_read_u32_index(np, name, j++, &n); + rc |= of_property_read_u32_index(np, name, j++, &p); + + if (rc) { + dt_prop_err(np, name, "unable to read u32\n"); + return -EINVAL; + } + + tbl->freq_hz = (unsigned long)freq_hz; + tbl->src_clk = msmclk_parse_phandle(dev, p); + if (IS_ERR_OR_NULL(tbl->src_clk)) { + dt_prop_err(np, name, "hashtable lookup failure\n"); + return PTR_ERR(tbl->src_clk); + } + + tbl->m_val = rcg_calc_m(m, n); + tbl->n_val = rcg_calc_n(m, n); + tbl->d_val = rcg_calc_duty_cycle(m, n); + + src_sel = parent_to_src_sel(rcg->c.parents, + rcg->c.num_parents, tbl->src_clk); + tbl->div_src_val = rcg_calc_div_src(div_int, div_frac, + src_sel); + } + /* End table with special value */ + tbl->freq_hz = FREQ_END; + return 0; +} + +static void *rcg_clk_dt_parser(struct device *dev, struct device_node *np) +{ + struct rcg_clk *rcg; + struct msmclk_data *drv; + int rc; + + rcg = devm_kzalloc(dev, sizeof(*rcg), GFP_KERNEL); + if (!rcg) { + dt_err(np, "memory alloc failure\n"); + return ERR_PTR(-ENOMEM); + } + + drv = msmclk_parse_phandle(dev, np->parent->phandle); + if (IS_ERR_OR_NULL(drv)) + return drv; + rcg->base = &drv->base; + + rcg->c.parents = msmclk_parse_clk_src(dev, np, &rcg->c.num_parents); + if (IS_ERR(rcg->c.parents)) { + dt_err(np, "unable to read parents\n"); + return ERR_CAST(rcg->c.parents); + } + + rc = of_property_read_u32(np, "qcom,base-offset", &rcg->cmd_rcgr_reg); + if (rc) { + dt_err(np, "missing qcom,base-offset dt property\n"); + return ERR_PTR(rc); + } + + rc = rcg_parse_freq_tbl(dev, np, rcg); + if (rc) { + dt_err(np, "unable to read freq_tbl\n"); + return ERR_PTR(rc); + } + rcg->current_freq = &rcg_dummy_freq; + + if (of_device_is_compatible(np, "qcom,rcg-hid")) { + rcg->c.ops = &clk_ops_rcg; + rcg->set_rate = set_rate_hid; + } else if (of_device_is_compatible(np, "qcom,rcg-mn")) { + rcg->c.ops = &clk_ops_rcg_mnd; + rcg->set_rate = set_rate_mnd; + } else { + dt_err(np, "unexpected compatible string\n"); + return ERR_PTR(-EINVAL); + } + + return msmclk_generic_clk_init(dev, np, &rcg->c); +} +MSMCLK_PARSER(rcg_clk_dt_parser, "qcom,rcg-hid", 0); +MSMCLK_PARSER(rcg_clk_dt_parser, "qcom,rcg-mn", 1); + +static int parse_rec_parents(struct device *dev, + struct device_node *np, struct mux_clk *mux) +{ + int i, rc; + char *name = "qcom,recursive-parents"; + phandle p; + + mux->num_rec_parents = of_property_count_phandles(np, name); + if (mux->num_rec_parents <= 0) + return 0; + + mux->rec_parents = devm_kzalloc(dev, + sizeof(*mux->rec_parents) * mux->num_rec_parents, + GFP_KERNEL); + + if (!mux->rec_parents) { + dt_err(np, "memory alloc failure\n"); + return -ENOMEM; + } + + for (i = 0; i < mux->num_rec_parents; i++) { + rc = of_property_read_phandle_index(np, name, i, &p); + if (rc) { + dt_prop_err(np, name, "unable to read u32\n"); + return rc; + } + + mux->rec_parents[i] = msmclk_parse_phandle(dev, p); + if (IS_ERR(mux->rec_parents[i])) { + dt_prop_err(np, name, "hashtable lookup failure\n"); + return PTR_ERR(mux->rec_parents[i]); + } + } + + return 0; +} + +static void *mux_reg_clk_dt_parser(struct device *dev, struct device_node *np) +{ + struct mux_clk *mux; + struct msmclk_data *drv; + int rc; + + mux = devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL); + if (!mux) { + dt_err(np, "memory alloc failure\n"); + return ERR_PTR(-ENOMEM); + } + + mux->parents = msmclk_parse_clk_src(dev, np, &mux->num_parents); + if (IS_ERR(mux->parents)) + return mux->parents; + + mux->c.parents = mux->parents; + mux->c.num_parents = mux->num_parents; + + drv = msmclk_parse_phandle(dev, np->parent->phandle); + if (IS_ERR_OR_NULL(drv)) + return drv; + mux->base = &drv->base; + + rc = parse_rec_parents(dev, np, mux); + if (rc) { + dt_err(np, "Incorrect qcom,recursive-parents dt property\n"); + return ERR_PTR(rc); + } + + rc = of_property_read_u32(np, "qcom,offset", &mux->offset); + if (rc) { + dt_err(np, "missing qcom,offset dt property\n"); + return ERR_PTR(-EINVAL); + } + + rc = of_property_read_u32(np, "qcom,mask", &mux->mask); + if (rc) { + dt_err(np, "missing qcom,mask dt property\n"); + return ERR_PTR(-EINVAL); + } + + rc = of_property_read_u32(np, "qcom,shift", &mux->shift); + if (rc) { + dt_err(np, "missing qcom,shift dt property\n"); + return ERR_PTR(-EINVAL); + } + + mux->c.ops = &clk_ops_gen_mux; + mux->ops = &mux_reg_ops; + + /* Optional Properties */ + of_property_read_u32(np, "qcom,en-offset", &mux->en_offset); + of_property_read_u32(np, "qcom,en-mask", &mux->en_mask); + + return msmclk_generic_clk_init(dev, np, &mux->c); +}; +MSMCLK_PARSER(mux_reg_clk_dt_parser, "qcom,mux-reg", 0); + +static void *measure_clk_dt_parser(struct device *dev, + struct device_node *np) +{ + struct mux_clk *mux; + struct clk *c; + struct measure_clk_data *p; + struct clk_ops *clk_ops_measure_mux; + phandle cxo; + int rc; + + c = mux_reg_clk_dt_parser(dev, np); + if (IS_ERR(c)) + return c; + + mux = to_mux_clk(c); + + p = devm_kzalloc(dev, sizeof(*p), GFP_KERNEL); + if (!p) { + dt_err(np, "memory alloc failure\n"); + return ERR_PTR(-ENOMEM); + } + + rc = of_property_read_phandle_index(np, "qcom,cxo", 0, &cxo); + if (rc) { + dt_err(np, "missing qcom,cxo\n"); + return ERR_PTR(-EINVAL); + } + p->cxo = msmclk_parse_phandle(dev, cxo); + if (IS_ERR_OR_NULL(p->cxo)) { + dt_prop_err(np, "qcom,cxo", "hashtable lookup failure\n"); + return p->cxo; + } + + rc = of_property_read_u32(np, "qcom,xo-div4-cbcr", &p->xo_div4_cbcr); + if (rc) { + dt_err(np, "missing qcom,xo-div4-cbcr dt property\n"); + return ERR_PTR(-EINVAL); + } + + rc = of_property_read_u32(np, "qcom,test-pad-config", &p->plltest_val); + if (rc) { + dt_err(np, "missing qcom,test-pad-config dt property\n"); + return ERR_PTR(-EINVAL); + } + + p->base = mux->base; + p->ctl_reg = mux->offset + 0x4; + p->status_reg = mux->offset + 0x8; + p->plltest_reg = mux->offset + 0xC; + mux->priv = p; + + clk_ops_measure_mux = devm_kzalloc(dev, sizeof(*clk_ops_measure_mux), + GFP_KERNEL); + if (!clk_ops_measure_mux) { + dt_err(np, "memory alloc failure\n"); + return ERR_PTR(-ENOMEM); + } + + *clk_ops_measure_mux = clk_ops_gen_mux; + clk_ops_measure_mux->get_rate = measure_get_rate; + + mux->c.ops = clk_ops_measure_mux; + + /* Already did generic clk init */ + return &mux->c; +}; +MSMCLK_PARSER(measure_clk_dt_parser, "qcom,measure-mux", 0); + +static void *div_clk_dt_parser(struct device *dev, + struct device_node *np) +{ + struct div_clk *div_clk; + struct msmclk_data *drv; + int rc; + + div_clk = devm_kzalloc(dev, sizeof(*div_clk), GFP_KERNEL); + if (!div_clk) { + dt_err(np, "memory alloc failed\n"); + return ERR_PTR(-ENOMEM); + } + + rc = of_property_read_u32(np, "qcom,max-div", &div_clk->data.max_div); + if (rc) { + dt_err(np, "missing qcom,max-div\n"); + return ERR_PTR(-EINVAL); + } + + rc = of_property_read_u32(np, "qcom,min-div", &div_clk->data.min_div); + if (rc) { + dt_err(np, "missing qcom,min-div\n"); + return ERR_PTR(-EINVAL); + } + + rc = of_property_read_u32(np, "qcom,base-offset", &div_clk->offset); + if (rc) { + dt_err(np, "missing qcom,base-offset\n"); + return ERR_PTR(-EINVAL); + } + + rc = of_property_read_u32(np, "qcom,mask", &div_clk->mask); + if (rc) { + dt_err(np, "missing qcom,mask\n"); + return ERR_PTR(-EINVAL); + } + + rc = of_property_read_u32(np, "qcom,shift", &div_clk->shift); + if (rc) { + dt_err(np, "missing qcom,shift\n"); + return ERR_PTR(-EINVAL); + } + + if (of_property_read_bool(np, "qcom,slave-div")) + div_clk->c.ops = &clk_ops_slave_div; + else + div_clk->c.ops = &clk_ops_div; + div_clk->ops = &div_reg_ops; + + drv = msmclk_parse_phandle(dev, np->parent->phandle); + if (IS_ERR_OR_NULL(drv)) + return ERR_CAST(drv); + div_clk->base = &drv->base; + + return msmclk_generic_clk_init(dev, np, &div_clk->c); +}; +MSMCLK_PARSER(div_clk_dt_parser, "qcom,div-clk", 0); + +static void *fixed_div_clk_dt_parser(struct device *dev, + struct device_node *np) +{ + struct div_clk *div_clk; + int rc; + + div_clk = devm_kzalloc(dev, sizeof(*div_clk), GFP_KERNEL); + if (!div_clk) { + dt_err(np, "memory alloc failed\n"); + return ERR_PTR(-ENOMEM); + } + + rc = of_property_read_u32(np, "qcom,div", &div_clk->data.div); + if (rc) { + dt_err(np, "missing qcom,div\n"); + return ERR_PTR(-EINVAL); + } + div_clk->data.min_div = div_clk->data.div; + div_clk->data.max_div = div_clk->data.div; + + if (of_property_read_bool(np, "qcom,slave-div")) + div_clk->c.ops = &clk_ops_slave_div; + else + div_clk->c.ops = &clk_ops_div; + div_clk->ops = &div_reg_ops; + + return msmclk_generic_clk_init(dev, np, &div_clk->c); +} +MSMCLK_PARSER(fixed_div_clk_dt_parser, "qcom,fixed-div-clk", 0); + +static void *reset_clk_dt_parser(struct device *dev, + struct device_node *np) +{ + struct reset_clk *reset_clk; + struct msmclk_data *drv; + int rc; + + reset_clk = devm_kzalloc(dev, sizeof(*reset_clk), GFP_KERNEL); + if (!reset_clk) { + dt_err(np, "memory alloc failed\n"); + return ERR_PTR(-ENOMEM); + } + + rc = of_property_read_u32(np, "qcom,base-offset", + &reset_clk->reset_reg); + if (rc) { + dt_err(np, "missing qcom,base-offset\n"); + return ERR_PTR(-EINVAL); + } + + drv = msmclk_parse_phandle(dev, np->parent->phandle); + if (IS_ERR_OR_NULL(drv)) + return ERR_CAST(drv); + reset_clk->base = &drv->base; + + reset_clk->c.ops = &clk_ops_rst; + return msmclk_generic_clk_init(dev, np, &reset_clk->c); +}; +MSMCLK_PARSER(reset_clk_dt_parser, "qcom,reset-clk", 0); diff -Nruw linux-4.4.115-fbx/drivers/clk/msm./clock-mmss-8998.c linux-4.4.115-fbx/drivers/clk/msm/clock-mmss-8998.c --- linux-4.4.115-fbx/drivers/clk/msm./clock-mmss-8998.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-4.4.115-fbx/drivers/clk/msm/clock-mmss-8998.c 2019-01-22 16:16:23.019242024 +0100 @@ -0,0 +1,2954 @@ +/* Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include +#include + +#include "vdd-level-8998.h" +#include "reset.h" + +static void __iomem *virt_base; + +#define mmsscc_xo_mm_source_val 0 +#define mmsscc_gpll0_mm_source_val 5 +#define mmsscc_gpll0_div_mm_source_val 6 +#define mmpll0_pll_out_mm_source_val 1 +#define mmpll1_pll_out_mm_source_val 2 +#define mmpll3_pll_out_mm_source_val 3 +#define mmpll4_pll_out_mm_source_val 2 +#define mmpll5_pll_out_mm_source_val 2 +#define mmpll6_pll_out_mm_source_val 4 +#define mmpll7_pll_out_mm_source_val 3 +#define mmpll10_pll_out_mm_source_val 4 +#define dsi0phypll_mm_source_val 1 +#define dsi1phypll_mm_source_val 2 +#define hdmiphypll_mm_source_val 1 +#define ext_dp_phy_pll_link_mm_source_val 1 +#define ext_dp_phy_pll_vco_mm_source_val 2 + +#define FIXDIV(div) (div ? (2 * (div) - 1) : (0)) + +#define F_MM(f, s, div, m, n) \ + { \ + .freq_hz = (f), \ + .src_clk = &s.c, \ + .m_val = (m), \ + .n_val = ~((n)-(m)) * !!(n), \ + .d_val = ~(n),\ + .div_src_val = BVAL(4, 0, (int)FIXDIV(div)) \ + | BVAL(10, 8, s##_mm_source_val), \ + } + +#define F_SLEW(f, s_f, s, div, m, n) \ + { \ + .freq_hz = (f), \ + .src_freq = (s_f), \ + .src_clk = &s.c, \ + .m_val = (m), \ + .n_val = ~((n)-(m)) * !!(n), \ + .d_val = ~(n),\ + .div_src_val = BVAL(4, 0, (int)(2*(div) - 1)) \ + | BVAL(10, 8, s##_mm_source_val), \ + } + +DEFINE_EXT_CLK(mmsscc_xo, NULL); +DEFINE_EXT_CLK(mmsscc_gpll0, NULL); +DEFINE_EXT_CLK(mmsscc_gpll0_div, NULL); +DEFINE_EXT_CLK(ext_dp_phy_pll_vco, NULL); +DEFINE_EXT_CLK(ext_dp_phy_pll_link, NULL); + +static DEFINE_VDD_REGULATORS(vdd_dig, VDD_DIG_NUM, 1, vdd_corner, NULL); +static DEFINE_VDD_REGULATORS(vdd_mmsscc_mx, VDD_DIG_NUM, 1, vdd_corner, NULL); + +static struct alpha_pll_masks pll_masks_p = { + .lock_mask = BIT(31), + .active_mask = BIT(30), + .update_mask = BIT(22), + .output_mask = 0xf, +}; + +static struct pll_vote_clk mmpll0_pll = { + .en_reg = (void __iomem *)MMSS_PLL_VOTE_APCS, + .en_mask = BIT(0), + .status_reg = (void __iomem *)MMSS_MMPLL0_PLL_MODE, + .status_mask = BIT(31), + .base = &virt_base, + .c = { + .rate = 808000000, + .parent = &mmsscc_xo.c, + .dbg_name = "mmpll0", + .ops = &clk_ops_pll_vote, + VDD_MM_PLL_FMAX_MAP2(LOWER, 404000000, NOMINAL, 808000000), + CLK_INIT(mmpll0_pll.c), + }, +}; +DEFINE_EXT_CLK(mmpll0_pll_out, &mmpll0_pll.c); + +static struct pll_vote_clk mmpll1_pll = { + .en_reg = (void __iomem *)MMSS_PLL_VOTE_APCS, + .en_mask = BIT(1), + .status_reg = (void __iomem *)MMSS_MMPLL1_PLL_MODE, + .status_mask = BIT(31), + .base = &virt_base, + .c = { + .rate = 812000000, + .parent = &mmsscc_xo.c, + .dbg_name = "mmpll1_pll", + .ops = &clk_ops_pll_vote, + VDD_MM_PLL_FMAX_MAP2(LOWER, 406000000, NOMINAL, 812000000), + CLK_INIT(mmpll1_pll.c), + }, +}; +DEFINE_EXT_CLK(mmpll1_pll_out, &mmpll1_pll.c); + +static struct alpha_pll_clk mmpll3_pll = { + .offset = MMSS_MMPLL3_PLL_MODE, + .masks = &pll_masks_p, + .enable_config = 0x1, + .base = &virt_base, + .is_fabia = true, + .c = { + .rate = 930000000, + .parent = &mmsscc_xo.c, + .dbg_name = "mmpll3_pll", + .ops = &clk_ops_fixed_fabia_alpha_pll, + VDD_MM_PLL_FMAX_MAP2(LOWER, 465000000, LOW, 930000000), + CLK_INIT(mmpll3_pll.c), + }, +}; +DEFINE_EXT_CLK(mmpll3_pll_out, &mmpll3_pll.c); + +static struct alpha_pll_clk mmpll4_pll = { + .offset = MMSS_MMPLL4_PLL_MODE, + .masks = &pll_masks_p, + .enable_config = 0x1, + .base = &virt_base, + .is_fabia = true, + .c = { + .rate = 768000000, + .parent = &mmsscc_xo.c, + .dbg_name = "mmpll4_pll", + .ops = &clk_ops_fixed_fabia_alpha_pll, + VDD_MM_PLL_FMAX_MAP2(LOWER, 384000000, LOW, 768000000), + CLK_INIT(mmpll4_pll.c), + }, +}; +DEFINE_EXT_CLK(mmpll4_pll_out, &mmpll4_pll.c); + +static struct alpha_pll_clk mmpll5_pll = { + .offset = MMSS_MMPLL5_PLL_MODE, + .masks = &pll_masks_p, + .enable_config = 0x1, + .base = &virt_base, + .is_fabia = true, + .c = { + .rate = 825000000, + .parent = &mmsscc_xo.c, + .dbg_name = "mmpll5_pll", + .ops = &clk_ops_fixed_fabia_alpha_pll, + VDD_MM_PLL_FMAX_MAP2(LOWER, 412500000, LOW, 825000000), + CLK_INIT(mmpll5_pll.c), + }, +}; +DEFINE_EXT_CLK(mmpll5_pll_out, &mmpll5_pll.c); + +static struct alpha_pll_clk mmpll6_pll = { + .offset = MMSS_MMPLL6_PLL_MODE, + .masks = &pll_masks_p, + .enable_config = 0x1, + .base = &virt_base, + .is_fabia = true, + .c = { + .rate = 720000000, + .parent = &mmsscc_xo.c, + .dbg_name = "mmpll6_pll", + .ops = &clk_ops_fixed_fabia_alpha_pll, + VDD_MM_PLL_FMAX_MAP2(LOWER, 360000000, NOMINAL, 720000000), + CLK_INIT(mmpll6_pll.c), + }, +}; +DEFINE_EXT_CLK(mmpll6_pll_out, &mmpll6_pll.c); + +static struct alpha_pll_clk mmpll7_pll = { + .offset = MMSS_MMPLL7_PLL_MODE, + .masks = &pll_masks_p, + .enable_config = 0x1, + .base = &virt_base, + .is_fabia = true, + .c = { + .rate = 960000000, + .parent = &mmsscc_xo.c, + .dbg_name = "mmpll7_pll", + .ops = &clk_ops_fixed_fabia_alpha_pll, + VDD_MM_PLL_FMAX_MAP1(LOW, 960000000), + CLK_INIT(mmpll7_pll.c), + }, +}; +DEFINE_EXT_CLK(mmpll7_pll_out, &mmpll7_pll.c); + +static struct alpha_pll_clk mmpll10_pll = { + .offset = MMSS_MMPLL10_PLL_MODE, + .masks = &pll_masks_p, + .enable_config = 0x1, + .base = &virt_base, + .is_fabia = true, + .c = { + .rate = 576000000, + .parent = &mmsscc_xo.c, + .dbg_name = "mmpll10_pll", + .ops = &clk_ops_fixed_fabia_alpha_pll, + VDD_MM_PLL_FMAX_MAP2(LOWER, 288000000, NOMINAL, 576000000), + CLK_INIT(mmpll10_pll.c), + }, +}; +DEFINE_EXT_CLK(mmpll10_pll_out, &mmpll10_pll.c); + +static struct clk_freq_tbl ftbl_ahb_clk_src[] = { + F_MM( 19200000, mmsscc_xo, 1, 0, 0), + F_MM( 40000000, mmsscc_gpll0, 15, 0, 0), + F_MM( 80800000, mmpll0_pll_out, 10, 0, 0), + F_END +}; + +static struct rcg_clk ahb_clk_src = { + .cmd_rcgr_reg = MMSS_AHB_CMD_RCGR, + .set_rate = set_rate_hid, + .freq_tbl = ftbl_ahb_clk_src, + .current_freq = &rcg_dummy_freq, + .non_local_children = true, + .base = &virt_base, + .c = { + .dbg_name = "ahb_clk_src", + .ops = &clk_ops_rcg, + .flags = CLKFLAG_NO_RATE_CACHE, + VDD_DIG_FMAX_MAP3(LOWER, 19200000, LOW, 40000000, + NOMINAL, 80800000), + CLK_INIT(ahb_clk_src.c), + }, +}; + +static struct clk_freq_tbl ftbl_csi_clk_src[] = { + F_MM( 164571429, mmpll10_pll_out, 3.5, 0, 0), + F_MM( 256000000, mmpll4_pll_out, 3, 0, 0), + F_MM( 384000000, mmpll4_pll_out, 2, 0, 0), + F_MM( 576000000, mmpll10_pll_out, 1, 0, 0), + F_END +}; + +static struct clk_freq_tbl ftbl_csi_clk_src_vq[] = { + F_MM( 164571429, mmpll10_pll_out, 3.5, 0, 0), + F_MM( 256000000, mmpll4_pll_out, 3, 0, 0), + F_MM( 274290000, mmpll7_pll_out, 3.5, 0, 0), + F_MM( 300000000, mmsscc_gpll0, 2, 0, 0), + F_MM( 384000000, mmpll4_pll_out, 2, 0, 0), + F_MM( 576000000, mmpll10_pll_out, 1, 0, 0), + F_END +}; + +static struct rcg_clk csi0_clk_src = { + .cmd_rcgr_reg = MMSS_CSI0_CMD_RCGR, + .set_rate = set_rate_hid, + .freq_tbl = ftbl_csi_clk_src, + .current_freq = &rcg_dummy_freq, + .base = &virt_base, + .c = { + .dbg_name = "csi0_clk_src", + .ops = &clk_ops_rcg, + .flags = CLKFLAG_NO_RATE_CACHE, + VDD_DIG_FMAX_MAP4(LOWER, 164571429, LOW, 256000000, + NOMINAL, 384000000, HIGH, 576000000), + CLK_INIT(csi0_clk_src.c), + }, +}; + +static struct clk_freq_tbl ftbl_vfe_clk_src[] = { + F_MM( 200000000, mmsscc_gpll0, 3, 0, 0), + F_MM( 300000000, mmsscc_gpll0, 2, 0, 0), + F_MM( 320000000, mmpll7_pll_out, 3, 0, 0), + F_MM( 384000000, mmpll4_pll_out, 2, 0, 0), + F_MM( 576000000, mmpll10_pll_out, 1, 0, 0), + F_MM( 600000000, mmsscc_gpll0, 1, 0, 0), + F_END +}; + +static struct clk_freq_tbl ftbl_vfe_clk_src_vq[] = { + F_MM( 200000000, mmsscc_gpll0, 3, 0, 0), + F_MM( 300000000, mmsscc_gpll0, 2, 0, 0), + F_MM( 320000000, mmpll7_pll_out, 3, 0, 0), + F_MM( 384000000, mmpll4_pll_out, 2, 0, 0), + F_MM( 404000000, mmpll0_pll_out, 2, 0, 0), + F_MM( 480000000, mmpll7_pll_out, 2, 0, 0), + F_MM( 576000000, mmpll10_pll_out, 1, 0, 0), + F_MM( 600000000, mmsscc_gpll0, 1, 0, 0), + F_END +}; + + +static struct rcg_clk vfe0_clk_src = { + .cmd_rcgr_reg = MMSS_VFE0_CMD_RCGR, + .set_rate = set_rate_hid, + .freq_tbl = ftbl_vfe_clk_src, + .current_freq = &rcg_dummy_freq, + .base = &virt_base, + .c = { + .dbg_name = "vfe0_clk_src", + .ops = &clk_ops_rcg, + .flags = CLKFLAG_NO_RATE_CACHE, + VDD_DIG_FMAX_MAP4(LOWER, 200000000, LOW, 384000000, + NOMINAL, 576000000, HIGH, 600000000), + CLK_INIT(vfe0_clk_src.c), + }, +}; + +static struct rcg_clk vfe1_clk_src = { + .cmd_rcgr_reg = MMSS_VFE1_CMD_RCGR, + .set_rate = set_rate_hid, + .freq_tbl = ftbl_vfe_clk_src, + .current_freq = &rcg_dummy_freq, + .base = &virt_base, + .c = { + .dbg_name = "vfe1_clk_src", + .ops = &clk_ops_rcg, + .flags = CLKFLAG_NO_RATE_CACHE, + VDD_DIG_FMAX_MAP4(LOWER, 200000000, LOW, 384000000, + NOMINAL, 576000000, HIGH, 600000000), + CLK_INIT(vfe1_clk_src.c), + }, +}; + +static struct clk_freq_tbl ftbl_mdp_clk_src[] = { + F_MM( 85714286, mmsscc_gpll0, 7, 0, 0), + F_MM( 100000000, mmsscc_gpll0, 6, 0, 0), + F_MM( 150000000, mmsscc_gpll0, 4, 0, 0), + F_MM( 171428571, mmsscc_gpll0, 3.5, 0, 0), + F_MM( 200000000, mmsscc_gpll0, 3, 0, 0), + F_MM( 275000000, mmpll5_pll_out, 3, 0, 0), + F_MM( 300000000, mmsscc_gpll0, 2, 0, 0), + F_MM( 330000000, mmpll5_pll_out, 2.5, 0, 0), + F_MM( 412500000, mmpll5_pll_out, 2, 0, 0), + F_END +}; + +static struct rcg_clk mdp_clk_src = { + .cmd_rcgr_reg = MMSS_MDP_CMD_RCGR, + .set_rate = set_rate_hid, + .freq_tbl = ftbl_mdp_clk_src, + .current_freq = &rcg_dummy_freq, + .non_local_children = true, + .base = &virt_base, + .c = { + .dbg_name = "mdp_clk_src", + .ops = &clk_ops_rcg, + .flags = CLKFLAG_NO_RATE_CACHE, + VDD_DIG_FMAX_MAP4(LOWER, 171430000, LOW, 275000000, + NOMINAL, 330000000, HIGH, 412500000), + CLK_INIT(mdp_clk_src.c), + }, +}; + +static struct clk_freq_tbl ftbl_maxi_clk_src[] = { + F_MM( 19200000, mmsscc_xo, 1, 0, 0), + F_MM( 75000000, mmsscc_gpll0_div, 4, 0, 0), + F_MM( 171428571, mmsscc_gpll0, 3.5, 0, 0), + F_MM( 323200000, mmpll0_pll_out, 2.5, 0, 0), + F_MM( 406000000, mmpll1_pll_out, 2, 0, 0), + F_END +}; + +static struct rcg_clk maxi_clk_src = { + .cmd_rcgr_reg = MMSS_MAXI_CMD_RCGR, + .set_rate = set_rate_hid, + .freq_tbl = ftbl_maxi_clk_src, + .current_freq = &rcg_dummy_freq, + .base = &virt_base, + .c = { + .dbg_name = "maxi_clk_src", + .ops = &clk_ops_rcg, + .flags = CLKFLAG_NO_RATE_CACHE, + VDD_DIG_FMAX_MAP4(LOWER, 75000000, LOW, 171428571, + NOMINAL, 323200000, HIGH, 406000000), + CLK_INIT(maxi_clk_src.c), + }, +}; + +static struct clk_freq_tbl ftbl_cpp_clk_src[] = { + F_MM( 100000000, mmsscc_gpll0, 6, 0, 0), + F_MM( 200000000, mmsscc_gpll0, 3, 0, 0), + F_MM( 576000000, mmpll10_pll_out, 1, 0, 0), + F_MM( 600000000, mmsscc_gpll0, 1, 0, 0), + F_END +}; + +static struct clk_freq_tbl ftbl_cpp_clk_src_vq[] = { + F_MM( 100000000, mmsscc_gpll0, 6, 0, 0), + F_MM( 200000000, mmsscc_gpll0, 3, 0, 0), + F_MM( 384000000, mmpll4_pll_out, 2, 0, 0), + F_MM( 404000000, mmpll0_pll_out, 2, 0, 0), + F_MM( 480000000, mmpll7_pll_out, 2, 0, 0), + F_MM( 576000000, mmpll10_pll_out, 1, 0, 0), + F_MM( 600000000, mmsscc_gpll0, 1, 0, 0), + F_END +}; + +static struct rcg_clk cpp_clk_src = { + .cmd_rcgr_reg = MMSS_CPP_CMD_RCGR, + .set_rate = set_rate_hid, + .freq_tbl = ftbl_cpp_clk_src, + .current_freq = &rcg_dummy_freq, + .base = &virt_base, + .c = { + .dbg_name = "cpp_clk_src", + .ops = &clk_ops_rcg, + .flags = CLKFLAG_NO_RATE_CACHE, + VDD_DIG_FMAX_MAP4(LOWER, 100000000, LOW, 200000000, + NOMINAL, 576000000, HIGH, 600000000), + CLK_INIT(cpp_clk_src.c), + }, +}; + +static struct clk_freq_tbl ftbl_jpeg0_clk_src[] = { + F_MM( 75000000, mmsscc_gpll0, 8, 0, 0), + F_MM( 150000000, mmsscc_gpll0, 4, 0, 0), + F_MM( 480000000, mmpll7_pll_out, 2, 0, 0), + F_END +}; + +static struct clk_freq_tbl ftbl_jpeg0_clk_src_vq[] = { + F_MM( 75000000, mmsscc_gpll0, 8, 0, 0), + F_MM( 150000000, mmsscc_gpll0, 4, 0, 0), + F_MM( 320000000, mmpll7_pll_out, 3, 0, 0), + F_MM( 480000000, mmpll7_pll_out, 2, 0, 0), + F_END +}; + +static struct rcg_clk jpeg0_clk_src = { + .cmd_rcgr_reg = MMSS_JPEG0_CMD_RCGR, + .set_rate = set_rate_hid, + .freq_tbl = ftbl_jpeg0_clk_src, + .current_freq = &rcg_dummy_freq, + .base = &virt_base, + .c = { + .dbg_name = "jpeg0_clk_src", + .ops = &clk_ops_rcg, + .flags = CLKFLAG_NO_RATE_CACHE, + VDD_DIG_FMAX_MAP3(LOWER, 75000000, LOW, 150000000, + NOMINAL, 480000000), + CLK_INIT(jpeg0_clk_src.c), + }, +}; + +static struct clk_freq_tbl ftbl_rot_clk_src[] = { + F_MM( 171428571, mmsscc_gpll0, 3.5, 0, 0), + F_MM( 275000000, mmpll5_pll_out, 3, 0, 0), + F_MM( 330000000, mmpll5_pll_out, 2.5, 0, 0), + F_MM( 412500000, mmpll5_pll_out, 2, 0, 0), + F_END +}; + +static struct rcg_clk rot_clk_src = { + .cmd_rcgr_reg = MMSS_ROT_CMD_RCGR, + .set_rate = set_rate_hid, + .freq_tbl = ftbl_rot_clk_src, + .current_freq = &rcg_dummy_freq, + .base = &virt_base, + .c = { + .dbg_name = "rot_clk_src", + .ops = &clk_ops_rcg, + .flags = CLKFLAG_NO_RATE_CACHE, + VDD_DIG_FMAX_MAP4(LOWER, 171430000, LOW, 275000000, + NOMINAL, 330000000, HIGH, 412500000), + CLK_INIT(rot_clk_src.c), + }, +}; + +static struct clk_freq_tbl ftbl_video_core_clk_src[] = { + F_MM( 100000000, mmsscc_gpll0, 6, 0, 0), + F_MM( 186000000, mmpll3_pll_out, 5, 0, 0), + F_MM( 360000000, mmpll6_pll_out, 2, 0, 0), + F_MM( 465000000, mmpll3_pll_out, 2, 0, 0), + F_END +}; + +static struct clk_freq_tbl ftbl_video_core_clk_src_vq[] = { + F_MM( 200000000, mmsscc_gpll0, 3, 0, 0), + F_MM( 269330000, mmpll0_pll_out, 3, 0, 0), + F_MM( 355200000, mmpll6_pll_out, 2.5, 0, 0), + F_MM( 444000000, mmpll6_pll_out, 2, 0, 0), + F_MM( 533000000, mmpll3_pll_out, 2, 0, 0), + F_END +}; + +static struct rcg_clk video_core_clk_src = { + .cmd_rcgr_reg = MMSS_VIDEO_CORE_CMD_RCGR, + .set_rate = set_rate_hid, + .freq_tbl = ftbl_video_core_clk_src, + .current_freq = &rcg_dummy_freq, + .base = &virt_base, + .c = { + .dbg_name = "video_core_clk_src", + .ops = &clk_ops_rcg, + .flags = CLKFLAG_NO_RATE_CACHE, + VDD_DIG_FMAX_MAP4(LOWER, 100000000, LOW, 186000000, + NOMINAL, 360000000, HIGH, 465000000), + CLK_INIT(video_core_clk_src.c), + }, +}; + +static struct clk_freq_tbl ftbl_csiphy_clk_src[] = { + F_MM( 164570000, mmpll10_pll_out, 3.5, 0, 0), + F_MM( 256000000, mmpll4_pll_out, 3, 0, 0), + F_MM( 384000000, mmpll4_pll_out, 2, 0, 0), + F_END +}; + +static struct clk_freq_tbl ftbl_csiphy_clk_src_vq[] = { + F_MM( 164570000, mmpll10_pll_out, 3.5, 0, 0), + F_MM( 256000000, mmpll4_pll_out, 3, 0, 0), + F_MM( 274290000, mmpll7_pll_out, 3.5, 0, 0), + F_MM( 300000000, mmsscc_gpll0, 2, 0, 0), + F_MM( 384000000, mmpll4_pll_out, 2, 0, 0), + F_END +}; + +static struct rcg_clk csiphy_clk_src = { + .cmd_rcgr_reg = MMSS_CSIPHY_CMD_RCGR, + .set_rate = set_rate_hid, + .freq_tbl = ftbl_csiphy_clk_src, + .current_freq = &rcg_dummy_freq, + .base = &virt_base, + .c = { + .dbg_name = "csiphy_clk_src", + .ops = &clk_ops_rcg, + .flags = CLKFLAG_NO_RATE_CACHE, + VDD_DIG_FMAX_MAP3(LOWER, 164570000, LOW, 256000000, + NOMINAL, 384000000), + CLK_INIT(csiphy_clk_src.c), + }, +}; + +static struct rcg_clk csi1_clk_src = { + .cmd_rcgr_reg = MMSS_CSI1_CMD_RCGR, + .set_rate = set_rate_hid, + .freq_tbl = ftbl_csi_clk_src, + .current_freq = &rcg_dummy_freq, + .base = &virt_base, + .c = { + .dbg_name = "csi1_clk_src", + .ops = &clk_ops_rcg, + .flags = CLKFLAG_NO_RATE_CACHE, + VDD_DIG_FMAX_MAP4(LOWER, 164570000, LOW, 256000000, + NOMINAL, 384000000, HIGH, 576000000), + CLK_INIT(csi1_clk_src.c), + }, +}; + +static struct rcg_clk csi2_clk_src = { + .cmd_rcgr_reg = MMSS_CSI2_CMD_RCGR, + .set_rate = set_rate_hid, + .freq_tbl = ftbl_csi_clk_src, + .current_freq = &rcg_dummy_freq, + .base = &virt_base, + .c = { + .dbg_name = "csi2_clk_src", + .ops = &clk_ops_rcg, + .flags = CLKFLAG_NO_RATE_CACHE, + VDD_DIG_FMAX_MAP4(LOWER, 164570000, LOW, 256000000, + NOMINAL, 384000000, HIGH, 576000000), + CLK_INIT(csi2_clk_src.c), + }, +}; + +static struct rcg_clk csi3_clk_src = { + .cmd_rcgr_reg = MMSS_CSI3_CMD_RCGR, + .set_rate = set_rate_hid, + .freq_tbl = ftbl_csi_clk_src, + .current_freq = &rcg_dummy_freq, + .base = &virt_base, + .c = { + .dbg_name = "csi3_clk_src", + .ops = &clk_ops_rcg, + .flags = CLKFLAG_NO_RATE_CACHE, + VDD_DIG_FMAX_MAP4(LOWER, 164570000, LOW, 256000000, + NOMINAL, 384000000, HIGH, 576000000), + CLK_INIT(csi3_clk_src.c), + }, +}; + +static struct clk_freq_tbl ftbl_fd_core_clk_src[] = { + F_MM( 100000000, mmsscc_gpll0, 6, 0, 0), + F_MM( 200000000, mmsscc_gpll0, 3, 0, 0), + F_MM( 576000000, mmpll10_pll_out, 1, 0, 0), + F_END +}; + +static struct clk_freq_tbl ftbl_fd_core_clk_src_vq[] = { + F_MM( 100000000, mmsscc_gpll0, 6, 0, 0), + F_MM( 200000000, mmsscc_gpll0, 3, 0, 0), + F_MM( 404000000, mmpll0_pll_out, 2, 0, 0), + F_MM( 480000000, mmpll7_pll_out, 2, 0, 0), + F_MM( 576000000, mmpll10_pll_out, 1, 0, 0), + F_END +}; + +static struct rcg_clk fd_core_clk_src = { + .cmd_rcgr_reg = MMSS_FD_CORE_CMD_RCGR, + .set_rate = set_rate_hid, + .freq_tbl = ftbl_fd_core_clk_src, + .current_freq = &rcg_dummy_freq, + .base = &virt_base, + .c = { + .dbg_name = "fd_core_clk_src", + .ops = &clk_ops_rcg, + .flags = CLKFLAG_NO_RATE_CACHE, + VDD_DIG_FMAX_MAP3(LOWER, 100000000, LOW, 200000000, + NOMINAL, 576000000), + CLK_INIT(fd_core_clk_src.c), + }, +}; + +DEFINE_EXT_CLK(ext_byte0_clk_src, NULL); +DEFINE_EXT_CLK(ext_byte1_clk_src, NULL); +static struct clk_freq_tbl ftbl_byte_clk_src[] = { + { + .div_src_val = BVAL(10, 8, mmsscc_xo_mm_source_val) + | BVAL(4, 0, 0), + .src_clk = &mmsscc_xo.c, + .freq_hz = 0, + }, + { + .div_src_val = BVAL(10, 8, dsi0phypll_mm_source_val), + .src_clk = &ext_byte0_clk_src.c, + .freq_hz = 0, + }, + { + .div_src_val = BVAL(10, 8, dsi1phypll_mm_source_val) + | BVAL(4, 0, 0), + .src_clk = &ext_byte1_clk_src.c, + .freq_hz = 0, + }, + F_END +}; + +static struct rcg_clk byte0_clk_src = { + .cmd_rcgr_reg = MMSS_BYTE0_CMD_RCGR, + .set_rate = set_rate_hid, + .current_freq = ftbl_byte_clk_src, + .freq_tbl = ftbl_byte_clk_src, + .base = &virt_base, + .c = { + .dbg_name = "byte0_clk_src", + .parent = &ext_byte0_clk_src.c, + .ops = &clk_ops_byte_multiparent, + .flags = CLKFLAG_NO_RATE_CACHE, + VDD_DIG_FMAX_MAP3(LOWER, 131250000, LOW, 210000000, + NOMINAL, 312500000), + CLK_INIT(byte0_clk_src.c), + }, +}; + +static struct rcg_clk byte1_clk_src = { + .cmd_rcgr_reg = MMSS_BYTE1_CMD_RCGR, + .set_rate = set_rate_hid, + .current_freq = ftbl_byte_clk_src, + .freq_tbl = ftbl_byte_clk_src, + .base = &virt_base, + .c = { + .dbg_name = "byte1_clk_src", + .parent = &ext_byte1_clk_src.c, + .ops = &clk_ops_byte_multiparent, + .flags = CLKFLAG_NO_RATE_CACHE, + VDD_DIG_FMAX_MAP3(LOWER, 131250000, LOW, 210000000, + NOMINAL, 312500000), + CLK_INIT(byte1_clk_src.c), + }, +}; + +DEFINE_EXT_CLK(ext_pclk0_clk_src, NULL); +DEFINE_EXT_CLK(ext_pclk1_clk_src, NULL); +static struct clk_freq_tbl ftbl_pclk_clk_src[] = { + { + .div_src_val = BVAL(10, 8, mmsscc_xo_mm_source_val) + | BVAL(4, 0, 0), + .src_clk = &mmsscc_xo.c, + .freq_hz = 0, + }, + { + .div_src_val = BVAL(10, 8, dsi0phypll_mm_source_val) + | BVAL(4, 0, 0), + .src_clk = &ext_pclk0_clk_src.c, + .freq_hz = 0, + }, + { + .div_src_val = BVAL(10, 8, dsi1phypll_mm_source_val) + | BVAL(4, 0, 0), + .src_clk = &ext_pclk1_clk_src.c, + .freq_hz = 0, + }, + F_END +}; + +static struct rcg_clk pclk0_clk_src = { + .cmd_rcgr_reg = MMSS_PCLK0_CMD_RCGR, + .set_rate = set_rate_mnd, + .current_freq = ftbl_pclk_clk_src, + .freq_tbl = ftbl_pclk_clk_src, + .base = &virt_base, + .c = { + .dbg_name = "pclk0_clk_src", + .parent = &ext_pclk0_clk_src.c, + .ops = &clk_ops_pixel_multiparent, + .flags = CLKFLAG_NO_RATE_CACHE, + VDD_DIG_FMAX_MAP3(LOWER, 175000000, LOW, 280000000, + NOMINAL, 416670000), + CLK_INIT(pclk0_clk_src.c), + }, +}; + +static struct rcg_clk pclk1_clk_src = { + .cmd_rcgr_reg = MMSS_PCLK1_CMD_RCGR, + .set_rate = set_rate_mnd, + .current_freq = ftbl_pclk_clk_src, + .freq_tbl = ftbl_pclk_clk_src, + .base = &virt_base, + .c = { + .dbg_name = "pclk1_clk_src", + .parent = &ext_pclk1_clk_src.c, + .ops = &clk_ops_pixel_multiparent, + .flags = CLKFLAG_NO_RATE_CACHE, + VDD_DIG_FMAX_MAP3(LOWER, 175000000, LOW, 280000000, + NOMINAL, 416670000), + CLK_INIT(pclk1_clk_src.c), + }, +}; + +static struct clk_freq_tbl ftbl_video_subcore_clk_src[] = { + F_MM( 100000000, mmsscc_gpll0, 6, 0, 0), + F_MM( 186000000, mmpll3_pll_out, 5, 0, 0), + F_MM( 360000000, mmpll6_pll_out, 2, 0, 0), + F_MM( 465000000, mmpll3_pll_out, 2, 0, 0), + F_END +}; + +static struct clk_freq_tbl ftbl_video_subcore_clk_src_vq[] = { + F_MM( 200000000, mmsscc_gpll0, 3, 0, 0), + F_MM( 269330000, mmpll0_pll_out, 3, 0, 0), + F_MM( 355200000, mmpll6_pll_out, 2.5, 0, 0), + F_MM( 444000000, mmpll6_pll_out, 2, 0, 0), + F_MM( 533000000, mmpll3_pll_out, 2, 0, 0), + F_END +}; + +static struct rcg_clk video_subcore0_clk_src = { + .cmd_rcgr_reg = MMSS_VIDEO_SUBCORE0_CMD_RCGR, + .set_rate = set_rate_hid, + .freq_tbl = ftbl_video_subcore_clk_src, + .current_freq = &rcg_dummy_freq, + .non_local_control_timeout = 1000, + .base = &virt_base, + .c = { + .dbg_name = "video_subcore0_clk_src", + .ops = &clk_ops_rcg, + .flags = CLKFLAG_NO_RATE_CACHE, + VDD_DIG_FMAX_MAP4(LOWER, 100000000, LOW, 186000000, + NOMINAL, 360000000, HIGH, 465000000), + CLK_INIT(video_subcore0_clk_src.c), + }, +}; + +static struct rcg_clk video_subcore1_clk_src = { + .cmd_rcgr_reg = MMSS_VIDEO_SUBCORE1_CMD_RCGR, + .set_rate = set_rate_hid, + .freq_tbl = ftbl_video_subcore_clk_src, + .current_freq = &rcg_dummy_freq, + .non_local_control_timeout = 1000, + .base = &virt_base, + .c = { + .dbg_name = "video_subcore1_clk_src", + .ops = &clk_ops_rcg, + .flags = CLKFLAG_NO_RATE_CACHE, + VDD_DIG_FMAX_MAP4(LOWER, 100000000, LOW, 186000000, + NOMINAL, 360000000, HIGH, 465000000), + CLK_INIT(video_subcore1_clk_src.c), + }, +}; + +static struct clk_freq_tbl ftbl_cci_clk_src[] = { + F_MM( 37500000, mmsscc_gpll0, 16, 0, 0), + F_MM( 50000000, mmsscc_gpll0, 12, 0, 0), + F_MM( 100000000, mmsscc_gpll0, 6, 0, 0), + F_END +}; + +static struct rcg_clk cci_clk_src = { + .cmd_rcgr_reg = MMSS_CCI_CMD_RCGR, + .set_rate = set_rate_mnd, + .freq_tbl = ftbl_cci_clk_src, + .current_freq = &rcg_dummy_freq, + .base = &virt_base, + .c = { + .dbg_name = "cci_clk_src", + .ops = &clk_ops_rcg_mnd, + .flags = CLKFLAG_NO_RATE_CACHE, + VDD_DIG_FMAX_MAP3(LOWER, 37500000, LOW, 50000000, + NOMINAL, 100000000), + CLK_INIT(cci_clk_src.c), + }, +}; + +static struct clk_freq_tbl ftbl_camss_gp_clk_src[] = { + F_MM( 10000, mmsscc_xo, 16, 1, 120), + F_MM( 24000, mmsscc_xo, 16, 1, 50), + F_MM( 6000000, mmsscc_gpll0, 10, 1, 10), + F_MM( 12000000, mmsscc_gpll0, 10, 1, 5), + F_MM( 13000000, mmsscc_gpll0, 4, 13, 150), + F_MM( 24000000, mmsscc_gpll0, 5, 1, 5), + F_END +}; + +static struct rcg_clk camss_gp0_clk_src = { + .cmd_rcgr_reg = MMSS_CAMSS_GP0_CMD_RCGR, + .set_rate = set_rate_mnd, + .freq_tbl = ftbl_camss_gp_clk_src, + .current_freq = &rcg_dummy_freq, + .base = &virt_base, + .c = { + .dbg_name = "camss_gp0_clk_src", + .ops = &clk_ops_rcg_mnd, + .flags = CLKFLAG_NO_RATE_CACHE, + VDD_DIG_FMAX_MAP3(LOWER, 50000000, LOW, 100000000, + NOMINAL, 200000000), + CLK_INIT(camss_gp0_clk_src.c), + }, +}; + +static struct rcg_clk camss_gp1_clk_src = { + .cmd_rcgr_reg = MMSS_CAMSS_GP1_CMD_RCGR, + .set_rate = set_rate_mnd, + .freq_tbl = ftbl_camss_gp_clk_src, + .current_freq = &rcg_dummy_freq, + .base = &virt_base, + .c = { + .dbg_name = "camss_gp1_clk_src", + .ops = &clk_ops_rcg_mnd, + .flags = CLKFLAG_NO_RATE_CACHE, + VDD_DIG_FMAX_MAP3(LOWER, 50000000, LOW, 100000000, + NOMINAL, 200000000), + CLK_INIT(camss_gp1_clk_src.c), + }, +}; + +static struct clk_freq_tbl ftbl_mclk_clk_src[] = { + F_MM( 4800000, mmsscc_xo, 4, 0, 0), + F_MM( 6000000, mmsscc_gpll0_div, 10, 1, 5), + F_MM( 8000000, mmsscc_gpll0_div, 1, 2, 75), + F_MM( 9600000, mmsscc_xo, 2, 0, 0), + F_MM( 16666667, mmsscc_gpll0_div, 2, 1, 9), + F_MM( 19200000, mmsscc_xo, 1, 0, 0), + F_MM( 24000000, mmsscc_gpll0_div, 1, 2, 25), + F_MM( 33333333, mmsscc_gpll0_div, 1, 1, 9), + F_MM( 48000000, mmsscc_gpll0, 1, 2, 25), + F_MM( 66666667, mmsscc_gpll0, 1, 1, 9), + F_END +}; + +static struct rcg_clk mclk0_clk_src = { + .cmd_rcgr_reg = MMSS_MCLK0_CMD_RCGR, + .set_rate = set_rate_mnd, + .freq_tbl = ftbl_mclk_clk_src, + .current_freq = &rcg_dummy_freq, + .base = &virt_base, + .c = { + .dbg_name = "mclk0_clk_src", + .ops = &clk_ops_rcg_mnd, + .flags = CLKFLAG_NO_RATE_CACHE, + VDD_DIG_FMAX_MAP3(LOWER, 33333333, LOW, 66666667, + NOMINAL, 68571429), + CLK_INIT(mclk0_clk_src.c), + }, +}; + +static struct rcg_clk mclk1_clk_src = { + .cmd_rcgr_reg = MMSS_MCLK1_CMD_RCGR, + .set_rate = set_rate_mnd, + .freq_tbl = ftbl_mclk_clk_src, + .current_freq = &rcg_dummy_freq, + .base = &virt_base, + .c = { + .dbg_name = "mclk1_clk_src", + .ops = &clk_ops_rcg_mnd, + .flags = CLKFLAG_NO_RATE_CACHE, + VDD_DIG_FMAX_MAP3(LOWER, 33333333, LOW, 66666667, + NOMINAL, 68571429), + CLK_INIT(mclk1_clk_src.c), + }, +}; + +static struct rcg_clk mclk2_clk_src = { + .cmd_rcgr_reg = MMSS_MCLK2_CMD_RCGR, + .set_rate = set_rate_mnd, + .freq_tbl = ftbl_mclk_clk_src, + .current_freq = &rcg_dummy_freq, + .base = &virt_base, + .c = { + .dbg_name = "mclk2_clk_src", + .ops = &clk_ops_rcg_mnd, + .flags = CLKFLAG_NO_RATE_CACHE, + VDD_DIG_FMAX_MAP3(LOWER, 33333333, LOW, 66666667, + NOMINAL, 68571429), + CLK_INIT(mclk2_clk_src.c), + }, +}; + +static struct rcg_clk mclk3_clk_src = { + .cmd_rcgr_reg = MMSS_MCLK3_CMD_RCGR, + .set_rate = set_rate_mnd, + .freq_tbl = ftbl_mclk_clk_src, + .current_freq = &rcg_dummy_freq, + .base = &virt_base, + .c = { + .dbg_name = "mclk3_clk_src", + .ops = &clk_ops_rcg_mnd, + .flags = CLKFLAG_NO_RATE_CACHE, + VDD_DIG_FMAX_MAP3(LOWER, 33333333, LOW, 66666667, + NOMINAL, 68571429), + CLK_INIT(mclk3_clk_src.c), + }, +}; + +static struct clk_freq_tbl ftbl_csiphytimer_clk_src[] = { + F_MM( 200000000, mmsscc_gpll0, 3, 0, 0), + F_MM( 269333333, mmpll0_pll_out, 3, 0, 0), + F_END +}; + +static struct rcg_clk csi0phytimer_clk_src = { + .cmd_rcgr_reg = MMSS_CSI0PHYTIMER_CMD_RCGR, + .set_rate = set_rate_hid, + .freq_tbl = ftbl_csiphytimer_clk_src, + .current_freq = &rcg_dummy_freq, + .base = &virt_base, + .c = { + .dbg_name = "csi0phytimer_clk_src", + .ops = &clk_ops_rcg, + .flags = CLKFLAG_NO_RATE_CACHE, + VDD_DIG_FMAX_MAP3(LOWER, 100000000, LOW, 200000000, + NOMINAL, 269333333), + CLK_INIT(csi0phytimer_clk_src.c), + }, +}; + +static struct rcg_clk csi1phytimer_clk_src = { + .cmd_rcgr_reg = MMSS_CSI1PHYTIMER_CMD_RCGR, + .set_rate = set_rate_hid, + .freq_tbl = ftbl_csiphytimer_clk_src, + .current_freq = &rcg_dummy_freq, + .base = &virt_base, + .c = { + .dbg_name = "csi1phytimer_clk_src", + .ops = &clk_ops_rcg, + .flags = CLKFLAG_NO_RATE_CACHE, + VDD_DIG_FMAX_MAP3(LOWER, 100000000, LOW, 200000000, + NOMINAL, 269333333), + CLK_INIT(csi1phytimer_clk_src.c), + }, +}; + +static struct rcg_clk csi2phytimer_clk_src = { + .cmd_rcgr_reg = MMSS_CSI2PHYTIMER_CMD_RCGR, + .set_rate = set_rate_hid, + .freq_tbl = ftbl_csiphytimer_clk_src, + .current_freq = &rcg_dummy_freq, + .base = &virt_base, + .c = { + .dbg_name = "csi2phytimer_clk_src", + .ops = &clk_ops_rcg, + .flags = CLKFLAG_NO_RATE_CACHE, + VDD_DIG_FMAX_MAP3(LOWER, 100000000, LOW, 200000000, + NOMINAL, 269333333), + CLK_INIT(csi2phytimer_clk_src.c), + }, +}; + +static struct clk_freq_tbl ftbl_dp_gtc_clk_src[] = { + F_MM( 300000000, mmsscc_gpll0, 2, 0, 0), + F_END +}; + +static struct rcg_clk dp_gtc_clk_src = { + .cmd_rcgr_reg = MMSS_DP_GTC_CMD_RCGR, + .set_rate = set_rate_hid, + .freq_tbl = ftbl_dp_gtc_clk_src, + .current_freq = &rcg_dummy_freq, + .base = &virt_base, + .c = { + .dbg_name = "dp_gtc_clk_src", + .ops = &clk_ops_rcg, + .flags = CLKFLAG_NO_RATE_CACHE, + VDD_DIG_FMAX_MAP2(LOWER, 40000000, LOW, 300000000), + CLK_INIT(dp_gtc_clk_src.c), + }, +}; + +static struct clk_freq_tbl ftbl_esc_clk_src[] = { + F_MM( 19200000, mmsscc_xo, 1, 0, 0), + F_END +}; + +static struct rcg_clk esc0_clk_src = { + .cmd_rcgr_reg = MMSS_ESC0_CMD_RCGR, + .set_rate = set_rate_hid, + .freq_tbl = ftbl_esc_clk_src, + .current_freq = &rcg_dummy_freq, + .base = &virt_base, + .c = { + .dbg_name = "esc0_clk_src", + .ops = &clk_ops_rcg, + .flags = CLKFLAG_NO_RATE_CACHE, + VDD_DIG_FMAX_MAP2(LOWER, 19200000, NOMINAL, 19200000), + CLK_INIT(esc0_clk_src.c), + }, +}; + +static struct rcg_clk esc1_clk_src = { + .cmd_rcgr_reg = MMSS_ESC1_CMD_RCGR, + .set_rate = set_rate_hid, + .freq_tbl = ftbl_esc_clk_src, + .current_freq = &rcg_dummy_freq, + .base = &virt_base, + .c = { + .dbg_name = "esc1_clk_src", + .ops = &clk_ops_rcg, + .flags = CLKFLAG_NO_RATE_CACHE, + VDD_DIG_FMAX_MAP2(LOWER, 19200000, NOMINAL, 19200000), + CLK_INIT(esc1_clk_src.c), + }, +}; + +DEFINE_EXT_CLK(ext_extpclk_clk_src, NULL); +static struct clk_freq_tbl ftbl_extpclk_clk_src[] = { + { + .div_src_val = BVAL(10, 8, hdmiphypll_mm_source_val), + .src_clk = &ext_extpclk_clk_src.c, + }, + F_END +}; + +static struct rcg_clk extpclk_clk_src = { + .cmd_rcgr_reg = MMSS_EXTPCLK_CMD_RCGR, + .current_freq = ftbl_extpclk_clk_src, + .base = &virt_base, + .c = { + .dbg_name = "extpclk_clk_src", + .parent = &ext_extpclk_clk_src.c, + .ops = &clk_ops_byte, + .flags = CLKFLAG_NO_RATE_CACHE, + VDD_DIG_FMAX_MAP3(LOWER, 150000000, LOW, 300000000, + NOMINAL, 600000000), + CLK_INIT(extpclk_clk_src.c), + }, +}; + +static struct clk_freq_tbl ftbl_hdmi_clk_src[] = { + F_MM( 19200000, mmsscc_xo, 1, 0, 0), + F_END +}; + +static struct rcg_clk hdmi_clk_src = { + .cmd_rcgr_reg = MMSS_HDMI_CMD_RCGR, + .set_rate = set_rate_hid, + .freq_tbl = ftbl_hdmi_clk_src, + .current_freq = &rcg_dummy_freq, + .base = &virt_base, + .c = { + .dbg_name = "hdmi_clk_src", + .ops = &clk_ops_rcg, + .flags = CLKFLAG_NO_RATE_CACHE, + VDD_DIG_FMAX_MAP2(LOWER, 19200000, NOMINAL, 19200000), + CLK_INIT(hdmi_clk_src.c), + }, +}; + +static struct clk_freq_tbl ftbl_vsync_clk_src[] = { + F_MM( 19200000, mmsscc_xo, 1, 0, 0), + F_END +}; + +static struct rcg_clk vsync_clk_src = { + .cmd_rcgr_reg = MMSS_VSYNC_CMD_RCGR, + .set_rate = set_rate_hid, + .freq_tbl = ftbl_vsync_clk_src, + .current_freq = &rcg_dummy_freq, + .base = &virt_base, + .c = { + .dbg_name = "vsync_clk_src", + .ops = &clk_ops_rcg, + .flags = CLKFLAG_NO_RATE_CACHE, + VDD_DIG_FMAX_MAP2(LOWER, 19200000, NOMINAL, 19200000), + CLK_INIT(vsync_clk_src.c), + }, +}; + +static struct clk_freq_tbl ftbl_dp_aux_clk_src[] = { + F_MM( 19200000, mmsscc_xo, 1, 0, 0), + F_END +}; + +static struct rcg_clk dp_aux_clk_src = { + .cmd_rcgr_reg = MMSS_DP_AUX_CMD_RCGR, + .set_rate = set_rate_hid, + .freq_tbl = ftbl_dp_aux_clk_src, + .current_freq = &rcg_dummy_freq, + .base = &virt_base, + .c = { + .dbg_name = "dp_aux_clk_src", + .ops = &clk_ops_rcg, + .flags = CLKFLAG_NO_RATE_CACHE, + VDD_DIG_FMAX_MAP2(LOWER, 19200000, NOMINAL, 19200000), + CLK_INIT(dp_aux_clk_src.c), + }, +}; + +static struct clk_freq_tbl ftbl_dp_pixel_clk_src[] = { + { + .div_src_val = BVAL(10, 8, ext_dp_phy_pll_vco_mm_source_val), + .src_clk = &ext_dp_phy_pll_vco.c, + }, + F_END +}; + +static struct rcg_clk dp_pixel_clk_src = { + .cmd_rcgr_reg = MMSS_DP_PIXEL_CMD_RCGR, + .set_rate = set_rate_mnd, + .current_freq = ftbl_dp_pixel_clk_src, + .base = &virt_base, + .c = { + .dbg_name = "dp_pixel_clk_src", + .parent = &ext_dp_phy_pll_vco.c, + .ops = &clk_ops_rcg_dp, + .flags = CLKFLAG_NO_RATE_CACHE, + VDD_DIG_FMAX_MAP3(LOWER, 154000000, LOW, 337500000, + NOMINAL, 675000000), + CLK_INIT(dp_pixel_clk_src.c), + }, +}; + +static struct clk_freq_tbl ftbl_dp_link_clk_src[] = { + F_SLEW( 162000, 324000, ext_dp_phy_pll_link, 2, 0, 0), + F_SLEW( 270000, 540000, ext_dp_phy_pll_link, 2, 0, 0), + F_SLEW( 540000, 1080000, ext_dp_phy_pll_link, 2, 0, 0), + F_END +}; + +static struct rcg_clk dp_link_clk_src = { + .cmd_rcgr_reg = MMSS_DP_LINK_CMD_RCGR, + .set_rate = set_rate_hid, + .freq_tbl = ftbl_dp_link_clk_src, + .current_freq = ftbl_dp_link_clk_src, + .base = &virt_base, + .c = { + .dbg_name = "dp_link_clk_src", + .ops = &clk_ops_rcg, + .flags = CLKFLAG_NO_RATE_CACHE, + VDD_DIG_FMAX_MAP3(LOWER, 162000, LOW, 270000, + NOMINAL, 540000), + CLK_INIT(dp_link_clk_src.c), + }, +}; + +/* + * Current understanding is that the DP PLL is going to be configured by using + * the set_rate ops for the dp_link_clk_src and dp_pixel_clk_src. When set_rate + * is called on this RCG, the rate call never makes it to the external DP + * clocks. + */ +static struct clk_freq_tbl ftbl_dp_crypto_clk_src[] = { + F_MM( 101250, ext_dp_phy_pll_link, 1, 5, 16), + F_MM( 168750, ext_dp_phy_pll_link, 1, 5, 16), + F_MM( 337500, ext_dp_phy_pll_link, 1, 5, 16), + F_END +}; + +static struct rcg_clk dp_crypto_clk_src = { + .cmd_rcgr_reg = MMSS_DP_CRYPTO_CMD_RCGR, + .set_rate = set_rate_mnd, + .freq_tbl = ftbl_dp_crypto_clk_src, + .current_freq = ftbl_dp_crypto_clk_src, + .base = &virt_base, + .c = { + .dbg_name = "dp_crypto_clk_src", + .ops = &clk_ops_rcg_mnd, + .flags = CLKFLAG_NO_RATE_CACHE, + VDD_DIG_FMAX_MAP3(LOWER, 101250, LOW, 168750, + NOMINAL, 337500), + CLK_INIT(dp_crypto_clk_src.c), + }, +}; + +static struct branch_clk mmss_bimc_smmu_ahb_clk = { + .cbcr_reg = MMSS_BIMC_SMMU_AHB_CBCR, + .has_sibling = 1, + .check_enable_bit = true, + .no_halt_check_on_disable = true, + .base = &virt_base, + .c = { + .dbg_name = "mmss_bimc_smmu_ahb_clk", + .ops = &clk_ops_branch, + CLK_INIT(mmss_bimc_smmu_ahb_clk.c), + }, +}; + +static struct branch_clk mmss_bimc_smmu_axi_clk = { + .cbcr_reg = MMSS_BIMC_SMMU_AXI_CBCR, + .has_sibling = 1, + .check_enable_bit = true, + .no_halt_check_on_disable = true, + .base = &virt_base, + .c = { + .dbg_name = "mmss_bimc_smmu_axi_clk", + .ops = &clk_ops_branch, + CLK_INIT(mmss_bimc_smmu_axi_clk.c), + }, +}; + +static struct branch_clk mmss_snoc_dvm_axi_clk = { + .cbcr_reg = MMSS_SNOC_DVM_AXI_CBCR, + .has_sibling = 1, + .base = &virt_base, + .c = { + .dbg_name = "mmss_snoc_dvm_axi_clk", + .ops = &clk_ops_branch, + CLK_INIT(mmss_snoc_dvm_axi_clk.c), + }, +}; + +static struct branch_clk mmss_camss_ahb_clk = { + .cbcr_reg = MMSS_CAMSS_AHB_CBCR, + .has_sibling = 1, + .base = &virt_base, + .c = { + .dbg_name = "mmss_camss_ahb_clk", + .ops = &clk_ops_branch, + CLK_INIT(mmss_camss_ahb_clk.c), + }, +}; + +static struct branch_clk mmss_camss_cci_ahb_clk = { + .cbcr_reg = MMSS_CAMSS_CCI_AHB_CBCR, + .has_sibling = 1, + .base = &virt_base, + .c = { + .dbg_name = "mmss_camss_cci_ahb_clk", + .ops = &clk_ops_branch, + CLK_INIT(mmss_camss_cci_ahb_clk.c), + }, +}; + +static struct branch_clk mmss_camss_cci_clk = { + .cbcr_reg = MMSS_CAMSS_CCI_CBCR, + .has_sibling = 0, + .base = &virt_base, + .c = { + .dbg_name = "mmss_camss_cci_clk", + .parent = &cci_clk_src.c, + .flags = CLKFLAG_NO_RATE_CACHE, + .ops = &clk_ops_branch, + CLK_INIT(mmss_camss_cci_clk.c), + }, +}; + +static struct branch_clk mmss_camss_cpp_ahb_clk = { + .cbcr_reg = MMSS_CAMSS_CPP_AHB_CBCR, + .has_sibling = 1, + .base = &virt_base, + .c = { + .dbg_name = "mmss_camss_cpp_ahb_clk", + .ops = &clk_ops_branch, + CLK_INIT(mmss_camss_cpp_ahb_clk.c), + }, +}; + +static struct branch_clk mmss_camss_cpp_clk = { + .cbcr_reg = MMSS_CAMSS_CPP_CBCR, + .has_sibling = 0, + .base = &virt_base, + .c = { + .dbg_name = "mmss_camss_cpp_clk", + .parent = &cpp_clk_src.c, + .flags = CLKFLAG_NO_RATE_CACHE, + .ops = &clk_ops_branch, + CLK_INIT(mmss_camss_cpp_clk.c), + }, +}; + +static struct branch_clk mmss_camss_cpp_axi_clk = { + .cbcr_reg = MMSS_CAMSS_CPP_AXI_CBCR, + .has_sibling = 1, + .base = &virt_base, + .c = { + .dbg_name = "mmss_camss_cpp_axi_clk", + .ops = &clk_ops_branch, + CLK_INIT(mmss_camss_cpp_axi_clk.c), + }, +}; + +static struct branch_clk mmss_camss_cpp_vbif_ahb_clk = { + .cbcr_reg = MMSS_CAMSS_CPP_VBIF_AHB_CBCR, + .has_sibling = 1, + .base = &virt_base, + .c = { + .dbg_name = "mmss_camss_cpp_vbif_ahb_clk", + .ops = &clk_ops_branch, + CLK_INIT(mmss_camss_cpp_vbif_ahb_clk.c), + }, +}; + +static struct branch_clk mmss_camss_cphy_csid0_clk = { + .cbcr_reg = MMSS_CAMSS_CPHY_CSID0_CBCR, + .has_sibling = 1, + .base = &virt_base, + .c = { + .dbg_name = "mmss_camss_cphy_csid0_clk", + .parent = &csiphy_clk_src.c, + .ops = &clk_ops_branch, + CLK_INIT(mmss_camss_cphy_csid0_clk.c), + }, +}; + +static struct branch_clk mmss_camss_csi0_ahb_clk = { + .cbcr_reg = MMSS_CAMSS_CSI0_AHB_CBCR, + .has_sibling = 1, + .base = &virt_base, + .c = { + .dbg_name = "mmss_camss_csi0_ahb_clk", + .ops = &clk_ops_branch, + CLK_INIT(mmss_camss_csi0_ahb_clk.c), + }, +}; + +static struct branch_clk mmss_camss_csi0_clk = { + .cbcr_reg = MMSS_CAMSS_CSI0_CBCR, + .has_sibling = 0, + .base = &virt_base, + .c = { + .dbg_name = "mmss_camss_csi0_clk", + .parent = &csi0_clk_src.c, + .flags = CLKFLAG_NO_RATE_CACHE, + .ops = &clk_ops_branch, + CLK_INIT(mmss_camss_csi0_clk.c), + }, +}; + +static struct branch_clk mmss_camss_csi0pix_clk = { + .cbcr_reg = MMSS_CAMSS_CSI0PIX_CBCR, + .has_sibling = 1, + .base = &virt_base, + .c = { + .dbg_name = "mmss_camss_csi0pix_clk", + .parent = &csi0_clk_src.c, + .ops = &clk_ops_branch, + CLK_INIT(mmss_camss_csi0pix_clk.c), + }, +}; + +static struct branch_clk mmss_camss_csi0rdi_clk = { + .cbcr_reg = MMSS_CAMSS_CSI0RDI_CBCR, + .has_sibling = 1, + .base = &virt_base, + .c = { + .dbg_name = "mmss_camss_csi0rdi_clk", + .parent = &csi0_clk_src.c, + .ops = &clk_ops_branch, + CLK_INIT(mmss_camss_csi0rdi_clk.c), + }, +}; + +static struct branch_clk mmss_camss_cphy_csid1_clk = { + .cbcr_reg = MMSS_CAMSS_CPHY_CSID1_CBCR, + .has_sibling = 1, + .base = &virt_base, + .c = { + .dbg_name = "mmss_camss_cphy_csid1_clk", + .parent = &csiphy_clk_src.c, + .ops = &clk_ops_branch, + CLK_INIT(mmss_camss_cphy_csid1_clk.c), + }, +}; + +static struct branch_clk mmss_camss_csi1_ahb_clk = { + .cbcr_reg = MMSS_CAMSS_CSI1_AHB_CBCR, + .has_sibling = 1, + .base = &virt_base, + .c = { + .dbg_name = "mmss_camss_csi1_ahb_clk", + .ops = &clk_ops_branch, + CLK_INIT(mmss_camss_csi1_ahb_clk.c), + }, +}; + +static struct branch_clk mmss_camss_csi1_clk = { + .cbcr_reg = MMSS_CAMSS_CSI1_CBCR, + .has_sibling = 0, + .base = &virt_base, + .c = { + .dbg_name = "mmss_camss_csi1_clk", + .parent = &csi1_clk_src.c, + .flags = CLKFLAG_NO_RATE_CACHE, + .ops = &clk_ops_branch, + CLK_INIT(mmss_camss_csi1_clk.c), + }, +}; + +static struct branch_clk mmss_camss_csi1pix_clk = { + .cbcr_reg = MMSS_CAMSS_CSI1PIX_CBCR, + .has_sibling = 1, + .base = &virt_base, + .c = { + .dbg_name = "mmss_camss_csi1pix_clk", + .parent = &csi1_clk_src.c, + .ops = &clk_ops_branch, + CLK_INIT(mmss_camss_csi1pix_clk.c), + }, +}; + +static struct branch_clk mmss_camss_csi1rdi_clk = { + .cbcr_reg = MMSS_CAMSS_CSI1RDI_CBCR, + .has_sibling = 1, + .base = &virt_base, + .c = { + .dbg_name = "mmss_camss_csi1rdi_clk", + .parent = &csi1_clk_src.c, + .ops = &clk_ops_branch, + CLK_INIT(mmss_camss_csi1rdi_clk.c), + }, +}; + +static struct branch_clk mmss_camss_cphy_csid2_clk = { + .cbcr_reg = MMSS_CAMSS_CPHY_CSID2_CBCR, + .has_sibling = 1, + .base = &virt_base, + .c = { + .dbg_name = "mmss_camss_cphy_csid2_clk", + .parent = &csiphy_clk_src.c, + .ops = &clk_ops_branch, + CLK_INIT(mmss_camss_cphy_csid2_clk.c), + }, +}; + +static struct branch_clk mmss_camss_csi2_ahb_clk = { + .cbcr_reg = MMSS_CAMSS_CSI2_AHB_CBCR, + .has_sibling = 1, + .base = &virt_base, + .c = { + .dbg_name = "mmss_camss_csi2_ahb_clk", + .ops = &clk_ops_branch, + CLK_INIT(mmss_camss_csi2_ahb_clk.c), + }, +}; + +static struct branch_clk mmss_camss_csi2_clk = { + .cbcr_reg = MMSS_CAMSS_CSI2_CBCR, + .has_sibling = 0, + .base = &virt_base, + .c = { + .dbg_name = "mmss_camss_csi2_clk", + .parent = &csi2_clk_src.c, + .flags = CLKFLAG_NO_RATE_CACHE, + .ops = &clk_ops_branch, + CLK_INIT(mmss_camss_csi2_clk.c), + }, +}; + +static struct branch_clk mmss_camss_csi2pix_clk = { + .cbcr_reg = MMSS_CAMSS_CSI2PIX_CBCR, + .has_sibling = 1, + .base = &virt_base, + .c = { + .dbg_name = "mmss_camss_csi2pix_clk", + .parent = &csi2_clk_src.c, + .ops = &clk_ops_branch, + CLK_INIT(mmss_camss_csi2pix_clk.c), + }, +}; + +static struct branch_clk mmss_camss_csi2rdi_clk = { + .cbcr_reg = MMSS_CAMSS_CSI2RDI_CBCR, + .has_sibling = 1, + .base = &virt_base, + .c = { + .dbg_name = "mmss_camss_csi2rdi_clk", + .parent = &csi2_clk_src.c, + .ops = &clk_ops_branch, + CLK_INIT(mmss_camss_csi2rdi_clk.c), + }, +}; + +static struct branch_clk mmss_camss_cphy_csid3_clk = { + .cbcr_reg = MMSS_CAMSS_CPHY_CSID3_CBCR, + .has_sibling = 1, + .base = &virt_base, + .c = { + .dbg_name = "mmss_camss_cphy_csid3_clk", + .parent = &csiphy_clk_src.c, + .ops = &clk_ops_branch, + CLK_INIT(mmss_camss_cphy_csid3_clk.c), + }, +}; + +static struct branch_clk mmss_camss_csi3_ahb_clk = { + .cbcr_reg = MMSS_CAMSS_CSI3_AHB_CBCR, + .has_sibling = 1, + .base = &virt_base, + .c = { + .dbg_name = "mmss_camss_csi3_ahb_clk", + .ops = &clk_ops_branch, + CLK_INIT(mmss_camss_csi3_ahb_clk.c), + }, +}; + +static struct branch_clk mmss_camss_csi3_clk = { + .cbcr_reg = MMSS_CAMSS_CSI3_CBCR, + .has_sibling = 0, + .base = &virt_base, + .c = { + .dbg_name = "mmss_camss_csi3_clk", + .parent = &csi3_clk_src.c, + .flags = CLKFLAG_NO_RATE_CACHE, + .ops = &clk_ops_branch, + CLK_INIT(mmss_camss_csi3_clk.c), + }, +}; + +static struct branch_clk mmss_camss_csi3pix_clk = { + .cbcr_reg = MMSS_CAMSS_CSI3PIX_CBCR, + .has_sibling = 1, + .base = &virt_base, + .c = { + .dbg_name = "mmss_camss_csi3pix_clk", + .parent = &csi3_clk_src.c, + .ops = &clk_ops_branch, + CLK_INIT(mmss_camss_csi3pix_clk.c), + }, +}; + +static struct branch_clk mmss_camss_csi3rdi_clk = { + .cbcr_reg = MMSS_CAMSS_CSI3RDI_CBCR, + .has_sibling = 1, + .base = &virt_base, + .c = { + .dbg_name = "mmss_camss_csi3rdi_clk", + .parent = &csi3_clk_src.c, + .ops = &clk_ops_branch, + CLK_INIT(mmss_camss_csi3rdi_clk.c), + }, +}; + +static struct branch_clk mmss_camss_csi_vfe0_clk = { + .cbcr_reg = MMSS_CAMSS_CSI_VFE0_CBCR, + .has_sibling = 1, + .base = &virt_base, + .c = { + .dbg_name = "mmss_camss_csi_vfe0_clk", + .parent = &vfe0_clk_src.c, + .ops = &clk_ops_branch, + CLK_INIT(mmss_camss_csi_vfe0_clk.c), + }, +}; + +static struct branch_clk mmss_camss_csi_vfe1_clk = { + .cbcr_reg = MMSS_CAMSS_CSI_VFE1_CBCR, + .has_sibling = 1, + .base = &virt_base, + .c = { + .dbg_name = "mmss_camss_csi_vfe1_clk", + .parent = &vfe1_clk_src.c, + .ops = &clk_ops_branch, + CLK_INIT(mmss_camss_csi_vfe1_clk.c), + }, +}; + +static struct branch_clk mmss_camss_csiphy0_clk = { + .cbcr_reg = MMSS_CAMSS_CSIPHY0_CBCR, + .has_sibling = 0, + .aggr_sibling_rates = true, + .base = &virt_base, + .c = { + .dbg_name = "mmss_camss_csiphy0_clk", + .parent = &csiphy_clk_src.c, + .flags = CLKFLAG_NO_RATE_CACHE, + .ops = &clk_ops_branch, + CLK_INIT(mmss_camss_csiphy0_clk.c), + }, +}; + +static struct branch_clk mmss_camss_csiphy1_clk = { + .cbcr_reg = MMSS_CAMSS_CSIPHY1_CBCR, + .has_sibling = 0, + .aggr_sibling_rates = true, + .base = &virt_base, + .c = { + .dbg_name = "mmss_camss_csiphy1_clk", + .parent = &csiphy_clk_src.c, + .flags = CLKFLAG_NO_RATE_CACHE, + .ops = &clk_ops_branch, + CLK_INIT(mmss_camss_csiphy1_clk.c), + }, +}; + +static struct branch_clk mmss_camss_csiphy2_clk = { + .cbcr_reg = MMSS_CAMSS_CSIPHY2_CBCR, + .has_sibling = 0, + .aggr_sibling_rates = true, + .base = &virt_base, + .c = { + .dbg_name = "mmss_camss_csiphy2_clk", + .parent = &csiphy_clk_src.c, + .flags = CLKFLAG_NO_RATE_CACHE, + .ops = &clk_ops_branch, + CLK_INIT(mmss_camss_csiphy2_clk.c), + }, +}; + +static struct branch_clk mmss_fd_ahb_clk = { + .cbcr_reg = MMSS_FD_AHB_CBCR, + .has_sibling = 1, + .base = &virt_base, + .c = { + .dbg_name = "mmss_fd_ahb_clk", + .ops = &clk_ops_branch, + CLK_INIT(mmss_fd_ahb_clk.c), + }, +}; + +static struct branch_clk mmss_fd_core_clk = { + .cbcr_reg = MMSS_FD_CORE_CBCR, + .has_sibling = 0, + .base = &virt_base, + .c = { + .dbg_name = "mmss_fd_core_clk", + .parent = &fd_core_clk_src.c, + .flags = CLKFLAG_NO_RATE_CACHE, + .ops = &clk_ops_branch, + CLK_INIT(mmss_fd_core_clk.c), + }, +}; + +static struct branch_clk mmss_fd_core_uar_clk = { + .cbcr_reg = MMSS_FD_CORE_UAR_CBCR, + .has_sibling = 1, + .base = &virt_base, + .c = { + .dbg_name = "mmss_fd_core_uar_clk", + .parent = &fd_core_clk_src.c, + .ops = &clk_ops_branch, + CLK_INIT(mmss_fd_core_uar_clk.c), + }, +}; + +static struct branch_clk mmss_camss_gp0_clk = { + .cbcr_reg = MMSS_CAMSS_GP0_CBCR, + .has_sibling = 0, + .base = &virt_base, + .c = { + .dbg_name = "mmss_camss_gp0_clk", + .parent = &camss_gp0_clk_src.c, + .flags = CLKFLAG_NO_RATE_CACHE, + .ops = &clk_ops_branch, + CLK_INIT(mmss_camss_gp0_clk.c), + }, +}; + +static struct branch_clk mmss_camss_gp1_clk = { + .cbcr_reg = MMSS_CAMSS_GP1_CBCR, + .has_sibling = 0, + .base = &virt_base, + .c = { + .dbg_name = "mmss_camss_gp1_clk", + .parent = &camss_gp1_clk_src.c, + .flags = CLKFLAG_NO_RATE_CACHE, + .ops = &clk_ops_branch, + CLK_INIT(mmss_camss_gp1_clk.c), + }, +}; + +static struct branch_clk mmss_camss_ispif_ahb_clk = { + .cbcr_reg = MMSS_CAMSS_ISPIF_AHB_CBCR, + .has_sibling = 1, + .base = &virt_base, + .c = { + .dbg_name = "mmss_camss_ispif_ahb_clk", + .ops = &clk_ops_branch, + CLK_INIT(mmss_camss_ispif_ahb_clk.c), + }, +}; + +static struct branch_clk mmss_camss_jpeg0_clk = { + .cbcr_reg = MMSS_CAMSS_JPEG0_CBCR, + .has_sibling = 0, + .base = &virt_base, + .c = { + .dbg_name = "mmss_camss_jpeg0_clk", + .parent = &jpeg0_clk_src.c, + .flags = CLKFLAG_NO_RATE_CACHE, + .ops = &clk_ops_branch, + CLK_INIT(mmss_camss_jpeg0_clk.c), + }, +}; + +static DEFINE_CLK_VOTER(mmss_camss_jpeg0_vote_clk, &mmss_camss_jpeg0_clk.c, 0); +static DEFINE_CLK_VOTER(mmss_camss_jpeg0_dma_vote_clk, + &mmss_camss_jpeg0_clk.c, 0); + +static struct branch_clk mmss_camss_jpeg_ahb_clk = { + .cbcr_reg = MMSS_CAMSS_JPEG_AHB_CBCR, + .has_sibling = 1, + .base = &virt_base, + .c = { + .dbg_name = "mmss_camss_jpeg_ahb_clk", + .ops = &clk_ops_branch, + CLK_INIT(mmss_camss_jpeg_ahb_clk.c), + }, +}; + +static struct branch_clk mmss_camss_jpeg_axi_clk = { + .cbcr_reg = MMSS_CAMSS_JPEG_AXI_CBCR, + .has_sibling = 1, + .base = &virt_base, + .c = { + .dbg_name = "mmss_camss_jpeg_axi_clk", + .ops = &clk_ops_branch, + CLK_INIT(mmss_camss_jpeg_axi_clk.c), + }, +}; + +static struct branch_clk mmss_camss_mclk0_clk = { + .cbcr_reg = MMSS_CAMSS_MCLK0_CBCR, + .has_sibling = 0, + .base = &virt_base, + .c = { + .dbg_name = "mmss_camss_mclk0_clk", + .parent = &mclk0_clk_src.c, + .flags = CLKFLAG_NO_RATE_CACHE, + .ops = &clk_ops_branch, + CLK_INIT(mmss_camss_mclk0_clk.c), + }, +}; + +static struct branch_clk mmss_camss_mclk1_clk = { + .cbcr_reg = MMSS_CAMSS_MCLK1_CBCR, + .has_sibling = 0, + .base = &virt_base, + .c = { + .dbg_name = "mmss_camss_mclk1_clk", + .parent = &mclk1_clk_src.c, + .flags = CLKFLAG_NO_RATE_CACHE, + .ops = &clk_ops_branch, + CLK_INIT(mmss_camss_mclk1_clk.c), + }, +}; + +static struct branch_clk mmss_camss_mclk2_clk = { + .cbcr_reg = MMSS_CAMSS_MCLK2_CBCR, + .has_sibling = 0, + .base = &virt_base, + .c = { + .dbg_name = "mmss_camss_mclk2_clk", + .parent = &mclk2_clk_src.c, + .flags = CLKFLAG_NO_RATE_CACHE, + .ops = &clk_ops_branch, + CLK_INIT(mmss_camss_mclk2_clk.c), + }, +}; + +static struct branch_clk mmss_camss_mclk3_clk = { + .cbcr_reg = MMSS_CAMSS_MCLK3_CBCR, + .has_sibling = 0, + .base = &virt_base, + .c = { + .dbg_name = "mmss_camss_mclk3_clk", + .parent = &mclk3_clk_src.c, + .flags = CLKFLAG_NO_RATE_CACHE, + .ops = &clk_ops_branch, + CLK_INIT(mmss_camss_mclk3_clk.c), + }, +}; + +static struct branch_clk mmss_camss_micro_ahb_clk = { + .cbcr_reg = MMSS_CAMSS_MICRO_AHB_CBCR, + .has_sibling = 1, + .base = &virt_base, + .c = { + .dbg_name = "mmss_camss_micro_ahb_clk", + .ops = &clk_ops_branch, + CLK_INIT(mmss_camss_micro_ahb_clk.c), + }, +}; + +static struct branch_clk mmss_camss_csi0phytimer_clk = { + .cbcr_reg = MMSS_CAMSS_CSI0PHYTIMER_CBCR, + .has_sibling = 0, + .base = &virt_base, + .c = { + .dbg_name = "mmss_camss_csi0phytimer_clk", + .parent = &csi0phytimer_clk_src.c, + .flags = CLKFLAG_NO_RATE_CACHE, + .ops = &clk_ops_branch, + CLK_INIT(mmss_camss_csi0phytimer_clk.c), + }, +}; + +static struct branch_clk mmss_camss_csi1phytimer_clk = { + .cbcr_reg = MMSS_CAMSS_CSI1PHYTIMER_CBCR, + .has_sibling = 0, + .base = &virt_base, + .c = { + .dbg_name = "mmss_camss_csi1phytimer_clk", + .parent = &csi1phytimer_clk_src.c, + .flags = CLKFLAG_NO_RATE_CACHE, + .ops = &clk_ops_branch, + CLK_INIT(mmss_camss_csi1phytimer_clk.c), + }, +}; + +static struct branch_clk mmss_camss_csi2phytimer_clk = { + .cbcr_reg = MMSS_CAMSS_CSI2PHYTIMER_CBCR, + .has_sibling = 0, + .base = &virt_base, + .c = { + .dbg_name = "mmss_camss_csi2phytimer_clk", + .parent = &csi2phytimer_clk_src.c, + .flags = CLKFLAG_NO_RATE_CACHE, + .ops = &clk_ops_branch, + CLK_INIT(mmss_camss_csi2phytimer_clk.c), + }, +}; + +static struct branch_clk mmss_camss_top_ahb_clk = { + .cbcr_reg = MMSS_CAMSS_TOP_AHB_CBCR, + .has_sibling = 1, + .base = &virt_base, + .c = { + .dbg_name = "mmss_camss_top_ahb_clk", + .ops = &clk_ops_branch, + CLK_INIT(mmss_camss_top_ahb_clk.c), + }, +}; + +static struct branch_clk mmss_camss_vfe0_ahb_clk = { + .cbcr_reg = MMSS_CAMSS_VFE0_AHB_CBCR, + .has_sibling = 1, + .base = &virt_base, + .c = { + .dbg_name = "mmss_camss_vfe0_ahb_clk", + .ops = &clk_ops_branch, + CLK_INIT(mmss_camss_vfe0_ahb_clk.c), + }, +}; + +static struct branch_clk mmss_camss_vfe0_clk = { + .cbcr_reg = MMSS_CAMSS_VFE0_CBCR, + .has_sibling = 0, + .base = &virt_base, + .c = { + .dbg_name = "mmss_camss_vfe0_clk", + .parent = &vfe0_clk_src.c, + .flags = CLKFLAG_NO_RATE_CACHE, + .ops = &clk_ops_branch, + CLK_INIT(mmss_camss_vfe0_clk.c), + }, +}; + +static struct branch_clk mmss_camss_vfe0_stream_clk = { + .cbcr_reg = MMSS_CAMSS_VFE0_STREAM_CBCR, + .has_sibling = 1, + .base = &virt_base, + .c = { + .dbg_name = "mmss_camss_vfe0_stream_clk", + .parent = &vfe0_clk_src.c, + .ops = &clk_ops_branch, + CLK_INIT(mmss_camss_vfe0_stream_clk.c), + }, +}; + +static struct branch_clk mmss_camss_vfe1_ahb_clk = { + .cbcr_reg = MMSS_CAMSS_VFE1_AHB_CBCR, + .has_sibling = 1, + .base = &virt_base, + .c = { + .dbg_name = "mmss_camss_vfe1_ahb_clk", + .ops = &clk_ops_branch, + CLK_INIT(mmss_camss_vfe1_ahb_clk.c), + }, +}; + +static struct branch_clk mmss_camss_vfe1_clk = { + .cbcr_reg = MMSS_CAMSS_VFE1_CBCR, + .has_sibling = 0, + .base = &virt_base, + .c = { + .dbg_name = "mmss_camss_vfe1_clk", + .parent = &vfe1_clk_src.c, + .flags = CLKFLAG_NO_RATE_CACHE, + .ops = &clk_ops_branch, + CLK_INIT(mmss_camss_vfe1_clk.c), + }, +}; + +static struct branch_clk mmss_camss_vfe1_stream_clk = { + .cbcr_reg = MMSS_CAMSS_VFE1_STREAM_CBCR, + .has_sibling = 1, + .base = &virt_base, + .c = { + .dbg_name = "mmss_camss_vfe1_stream_clk", + .parent = &vfe1_clk_src.c, + .ops = &clk_ops_branch, + CLK_INIT(mmss_camss_vfe1_stream_clk.c), + }, +}; + +static struct branch_clk mmss_camss_vfe_vbif_ahb_clk = { + .cbcr_reg = MMSS_CAMSS_VFE_VBIF_AHB_CBCR, + .has_sibling = 1, + .base = &virt_base, + .c = { + .dbg_name = "mmss_camss_vfe_vbif_ahb_clk", + .ops = &clk_ops_branch, + CLK_INIT(mmss_camss_vfe_vbif_ahb_clk.c), + }, +}; + +static struct branch_clk mmss_camss_vfe_vbif_axi_clk = { + .cbcr_reg = MMSS_CAMSS_VFE_VBIF_AXI_CBCR, + .has_sibling = 1, + .base = &virt_base, + .c = { + .dbg_name = "mmss_camss_vfe_vbif_axi_clk", + .ops = &clk_ops_branch, + CLK_INIT(mmss_camss_vfe_vbif_axi_clk.c), + }, +}; + +static struct branch_clk mmss_mdss_ahb_clk = { + .cbcr_reg = MMSS_MDSS_AHB_CBCR, + .has_sibling = 1, + .base = &virt_base, + .c = { + .dbg_name = "mmss_mdss_ahb_clk", + .ops = &clk_ops_branch, + CLK_INIT(mmss_mdss_ahb_clk.c), + }, +}; + +static struct branch_clk mmss_mdss_axi_clk = { + .cbcr_reg = MMSS_MDSS_AXI_CBCR, + .has_sibling = 1, + .base = &virt_base, + .c = { + .dbg_name = "mmss_mdss_axi_clk", + .ops = &clk_ops_branch, + CLK_INIT(mmss_mdss_axi_clk.c), + }, +}; + +static struct branch_clk mmss_mdss_byte0_clk = { + .cbcr_reg = MMSS_MDSS_BYTE0_CBCR, + .has_sibling = 0, + .base = &virt_base, + .c = { + .dbg_name = "mmss_mdss_byte0_clk", + .parent = &byte0_clk_src.c, + .flags = CLKFLAG_NO_RATE_CACHE, + .ops = &clk_ops_branch, + CLK_INIT(mmss_mdss_byte0_clk.c), + }, +}; + +static struct div_clk mmss_mdss_byte0_intf_div_clk = { + .offset = MMSS_MDSS_BYTE0_INTF_DIV, + .mask = 0x3, + .shift = 0, + .data = { + .min_div = 1, + .max_div = 4, + }, + .base = &virt_base, + /* + * NOTE: Op does not work for div-3. Current assumption is that div-3 + * is not a recommended setting for this divider. + */ + .ops = &postdiv_reg_ops, + .c = { + .dbg_name = "mmss_mdss_byte0_intf_div_clk", + .parent = &byte0_clk_src.c, + .ops = &clk_ops_slave_div, + .flags = CLKFLAG_NO_RATE_CACHE, + CLK_INIT(mmss_mdss_byte0_intf_div_clk.c), + }, +}; + +static struct branch_clk mmss_mdss_byte0_intf_clk = { + .cbcr_reg = MMSS_MDSS_BYTE0_INTF_CBCR, + .has_sibling = 0, + .base = &virt_base, + .c = { + .dbg_name = "mmss_mdss_byte0_intf_clk", + .parent = &mmss_mdss_byte0_intf_div_clk.c, + .flags = CLKFLAG_NO_RATE_CACHE, + .ops = &clk_ops_branch, + CLK_INIT(mmss_mdss_byte0_intf_clk.c), + }, +}; + +static struct branch_clk mmss_mdss_byte1_clk = { + .cbcr_reg = MMSS_MDSS_BYTE1_CBCR, + .has_sibling = 0, + .base = &virt_base, + .c = { + .dbg_name = "mmss_mdss_byte1_clk", + .parent = &byte1_clk_src.c, + .flags = CLKFLAG_NO_RATE_CACHE, + .ops = &clk_ops_branch, + CLK_INIT(mmss_mdss_byte1_clk.c), + }, +}; + +static struct div_clk mmss_mdss_byte1_intf_div_clk = { + .offset = MMSS_MDSS_BYTE1_INTF_DIV, + .mask = 0x3, + .shift = 0, + .data = { + .min_div = 1, + .max_div = 4, + }, + .base = &virt_base, + /* + * NOTE: Op does not work for div-3. Current assumption is that div-3 + * is not a recommended setting for this divider. + */ + .ops = &postdiv_reg_ops, + .c = { + .dbg_name = "mmss_mdss_byte1_intf_div_clk", + .parent = &byte1_clk_src.c, + .ops = &clk_ops_slave_div, + .flags = CLKFLAG_NO_RATE_CACHE, + CLK_INIT(mmss_mdss_byte1_intf_div_clk.c), + }, +}; + +static struct branch_clk mmss_mdss_byte1_intf_clk = { + .cbcr_reg = MMSS_MDSS_BYTE1_INTF_CBCR, + .has_sibling = 0, + .base = &virt_base, + .c = { + .dbg_name = "mmss_mdss_byte1_intf_clk", + .parent = &mmss_mdss_byte1_intf_div_clk.c, + .flags = CLKFLAG_NO_RATE_CACHE, + .ops = &clk_ops_branch, + CLK_INIT(mmss_mdss_byte1_intf_clk.c), + }, +}; + +static struct branch_clk mmss_mdss_dp_aux_clk = { + .cbcr_reg = MMSS_MDSS_DP_AUX_CBCR, + .has_sibling = 0, + .base = &virt_base, + .c = { + .dbg_name = "mmss_mdss_dp_aux_clk", + .parent = &dp_aux_clk_src.c, + .flags = CLKFLAG_NO_RATE_CACHE, + .ops = &clk_ops_branch, + CLK_INIT(mmss_mdss_dp_aux_clk.c), + }, +}; + +static struct branch_clk mmss_mdss_dp_pixel_clk = { + .cbcr_reg = MMSS_MDSS_DP_PIXEL_CBCR, + .has_sibling = 0, + .base = &virt_base, + .c = { + .dbg_name = "mmss_mdss_dp_pixel_clk", + .parent = &dp_pixel_clk_src.c, + .flags = CLKFLAG_NO_RATE_CACHE, + .ops = &clk_ops_branch, + CLK_INIT(mmss_mdss_dp_pixel_clk.c), + }, +}; + +static struct branch_clk mmss_mdss_dp_link_clk = { + .cbcr_reg = MMSS_MDSS_DP_LINK_CBCR, + .has_sibling = 0, + .base = &virt_base, + .c = { + .dbg_name = "mmss_mdss_dp_link_clk", + .parent = &dp_link_clk_src.c, + .flags = CLKFLAG_NO_RATE_CACHE, + .ops = &clk_ops_branch, + CLK_INIT(mmss_mdss_dp_link_clk.c), + }, +}; + +/* Reset state of MMSS_MDSS_DP_LINK_INTF_DIV is 0x3 (div-4) */ +static struct branch_clk mmss_mdss_dp_link_intf_clk = { + .cbcr_reg = MMSS_MDSS_DP_LINK_INTF_CBCR, + .has_sibling = 1, + .base = &virt_base, + .c = { + .dbg_name = "mmss_mdss_dp_link_intf_clk", + .parent = &dp_link_clk_src.c, + .ops = &clk_ops_branch, + CLK_INIT(mmss_mdss_dp_link_intf_clk.c), + }, +}; + +static struct branch_clk mmss_mdss_dp_crypto_clk = { + .cbcr_reg = MMSS_MDSS_DP_CRYPTO_CBCR, + .has_sibling = 0, + .base = &virt_base, + .c = { + .dbg_name = "mmss_mdss_dp_crypto_clk", + .parent = &dp_crypto_clk_src.c, + .flags = CLKFLAG_NO_RATE_CACHE, + .ops = &clk_ops_branch, + CLK_INIT(mmss_mdss_dp_crypto_clk.c), + }, +}; + +static struct branch_clk mmss_mdss_dp_gtc_clk = { + .cbcr_reg = MMSS_MDSS_DP_GTC_CBCR, + .has_sibling = 0, + .base = &virt_base, + .c = { + .dbg_name = "mmss_mdss_dp_gtc_clk", + .parent = &dp_gtc_clk_src.c, + .flags = CLKFLAG_NO_RATE_CACHE, + .ops = &clk_ops_branch, + CLK_INIT(mmss_mdss_dp_gtc_clk.c), + }, +}; + +static struct branch_clk mmss_mdss_esc0_clk = { + .cbcr_reg = MMSS_MDSS_ESC0_CBCR, + .has_sibling = 0, + .base = &virt_base, + .c = { + .dbg_name = "mmss_mdss_esc0_clk", + .parent = &esc0_clk_src.c, + .flags = CLKFLAG_NO_RATE_CACHE, + .ops = &clk_ops_branch, + CLK_INIT(mmss_mdss_esc0_clk.c), + }, +}; + +static struct branch_clk mmss_mdss_esc1_clk = { + .cbcr_reg = MMSS_MDSS_ESC1_CBCR, + .has_sibling = 0, + .base = &virt_base, + .c = { + .dbg_name = "mmss_mdss_esc1_clk", + .parent = &esc1_clk_src.c, + .flags = CLKFLAG_NO_RATE_CACHE, + .ops = &clk_ops_branch, + CLK_INIT(mmss_mdss_esc1_clk.c), + }, +}; + +static struct branch_clk mmss_mdss_extpclk_clk = { + .cbcr_reg = MMSS_MDSS_EXTPCLK_CBCR, + .has_sibling = 0, + .base = &virt_base, + .c = { + .dbg_name = "mmss_mdss_extpclk_clk", + .parent = &extpclk_clk_src.c, + .flags = CLKFLAG_NO_RATE_CACHE, + .ops = &clk_ops_branch, + CLK_INIT(mmss_mdss_extpclk_clk.c), + }, +}; + +static struct branch_clk mmss_mdss_hdmi_clk = { + .cbcr_reg = MMSS_MDSS_HDMI_CBCR, + .has_sibling = 0, + .base = &virt_base, + .c = { + .dbg_name = "mmss_mdss_hdmi_clk", + .parent = &hdmi_clk_src.c, + .flags = CLKFLAG_NO_RATE_CACHE, + .ops = &clk_ops_branch, + CLK_INIT(mmss_mdss_hdmi_clk.c), + }, +}; + +static struct branch_clk mmss_mdss_hdmi_dp_ahb_clk = { + .cbcr_reg = MMSS_MDSS_HDMI_DP_AHB_CBCR, + .has_sibling = 1, + .base = &virt_base, + .c = { + .dbg_name = "mmss_mdss_hdmi_dp_ahb_clk", + .ops = &clk_ops_branch, + CLK_INIT(mmss_mdss_hdmi_dp_ahb_clk.c), + }, +}; + +static struct branch_clk mmss_mdss_mdp_clk = { + .cbcr_reg = MMSS_MDSS_MDP_CBCR, + .has_sibling = 0, + .base = &virt_base, + .c = { + .dbg_name = "mmss_mdss_mdp_clk", + .parent = &mdp_clk_src.c, + .flags = CLKFLAG_NO_RATE_CACHE, + .ops = &clk_ops_branch, + CLK_INIT(mmss_mdss_mdp_clk.c), + }, +}; + +static struct branch_clk mmss_mdss_mdp_lut_clk = { + .cbcr_reg = MMSS_MDSS_MDP_LUT_CBCR, + .has_sibling = 1, + .check_enable_bit = true, + .halt_check = DELAY, + .base = &virt_base, + .c = { + .dbg_name = "mmss_mdss_mdp_lut_clk", + .parent = &mdp_clk_src.c, + .ops = &clk_ops_branch, + CLK_INIT(mmss_mdss_mdp_lut_clk.c), + }, +}; + +static struct branch_clk mmss_mdss_pclk0_clk = { + .cbcr_reg = MMSS_MDSS_PCLK0_CBCR, + .has_sibling = 0, + .base = &virt_base, + .c = { + .dbg_name = "mmss_mdss_pclk0_clk", + .parent = &pclk0_clk_src.c, + .flags = CLKFLAG_NO_RATE_CACHE, + .ops = &clk_ops_branch, + CLK_INIT(mmss_mdss_pclk0_clk.c), + }, +}; + +static struct branch_clk mmss_mdss_pclk1_clk = { + .cbcr_reg = MMSS_MDSS_PCLK1_CBCR, + .has_sibling = 0, + .base = &virt_base, + .c = { + .dbg_name = "mmss_mdss_pclk1_clk", + .parent = &pclk1_clk_src.c, + .flags = CLKFLAG_NO_RATE_CACHE, + .ops = &clk_ops_branch, + CLK_INIT(mmss_mdss_pclk1_clk.c), + }, +}; + +static struct branch_clk mmss_mdss_rot_clk = { + .cbcr_reg = MMSS_MDSS_ROT_CBCR, + .has_sibling = 0, + .base = &virt_base, + .c = { + .dbg_name = "mmss_mdss_rot_clk", + .parent = &rot_clk_src.c, + .flags = CLKFLAG_NO_RATE_CACHE, + .ops = &clk_ops_branch, + CLK_INIT(mmss_mdss_rot_clk.c), + }, +}; + +static struct branch_clk mmss_mdss_vsync_clk = { + .cbcr_reg = MMSS_MDSS_VSYNC_CBCR, + .has_sibling = 0, + .base = &virt_base, + .c = { + .dbg_name = "mmss_mdss_vsync_clk", + .parent = &vsync_clk_src.c, + .flags = CLKFLAG_NO_RATE_CACHE, + .ops = &clk_ops_branch, + CLK_INIT(mmss_mdss_vsync_clk.c), + }, +}; + +static struct branch_clk mmss_mnoc_ahb_clk = { + .cbcr_reg = MMSS_MNOC_AHB_CBCR, + .has_sibling = 0, + .check_enable_bit = true, + .no_halt_check_on_disable = true, + .base = &virt_base, + .c = { + .dbg_name = "mmss_mnoc_ahb_clk", + .parent = &ahb_clk_src.c, + .flags = CLKFLAG_NO_RATE_CACHE, + .ops = &clk_ops_branch, + CLK_INIT(mmss_mnoc_ahb_clk.c), + }, +}; + +static struct branch_clk mmss_misc_ahb_clk = { + .cbcr_reg = MMSS_MISC_AHB_CBCR, + .has_sibling = 1, + .base = &virt_base, + .c = { + .dbg_name = "mmss_misc_ahb_clk", + .ops = &clk_ops_branch, + .depends = &mmss_mnoc_ahb_clk.c, + CLK_INIT(mmss_misc_ahb_clk.c), + }, +}; + +static struct branch_clk mmss_misc_cxo_clk = { + .cbcr_reg = MMSS_MISC_CXO_CBCR, + .has_sibling = 1, + .base = &virt_base, + .c = { + .dbg_name = "mmss_misc_cxo_clk", + .ops = &clk_ops_branch, + CLK_INIT(mmss_misc_cxo_clk.c), + }, +}; + +static struct branch_clk mmss_mnoc_maxi_clk = { + .cbcr_reg = MMSS_MNOC_MAXI_CBCR, + .has_sibling = 0, + .base = &virt_base, + .c = { + .dbg_name = "mmss_mnoc_maxi_clk", + .parent = &maxi_clk_src.c, + .flags = CLKFLAG_NO_RATE_CACHE, + .ops = &clk_ops_branch, + CLK_INIT(mmss_mnoc_maxi_clk.c), + }, +}; + +static struct branch_clk mmss_video_subcore0_clk = { + .cbcr_reg = MMSS_VIDEO_SUBCORE0_CBCR, + .has_sibling = 0, + .base = &virt_base, + .c = { + .dbg_name = "mmss_video_subcore0_clk", + .parent = &video_subcore0_clk_src.c, + .flags = CLKFLAG_NO_RATE_CACHE, + .ops = &clk_ops_branch, + CLK_INIT(mmss_video_subcore0_clk.c), + }, +}; + +static struct branch_clk mmss_video_subcore1_clk = { + .cbcr_reg = MMSS_VIDEO_SUBCORE1_CBCR, + .has_sibling = 0, + .base = &virt_base, + .c = { + .dbg_name = "mmss_video_subcore1_clk", + .parent = &video_subcore1_clk_src.c, + .flags = CLKFLAG_NO_RATE_CACHE, + .ops = &clk_ops_branch, + CLK_INIT(mmss_video_subcore1_clk.c), + }, +}; + +static struct branch_clk mmss_video_ahb_clk = { + .cbcr_reg = MMSS_VIDEO_AHB_CBCR, + .has_sibling = 1, + .base = &virt_base, + .c = { + .dbg_name = "mmss_video_ahb_clk", + .ops = &clk_ops_branch, + CLK_INIT(mmss_video_ahb_clk.c), + }, +}; + +static struct branch_clk mmss_video_axi_clk = { + .cbcr_reg = MMSS_VIDEO_AXI_CBCR, + .has_sibling = 1, + .base = &virt_base, + .c = { + .dbg_name = "mmss_video_axi_clk", + .ops = &clk_ops_branch, + CLK_INIT(mmss_video_axi_clk.c), + }, +}; + +static struct branch_clk mmss_video_core_clk = { + .cbcr_reg = MMSS_VIDEO_CORE_CBCR, + .has_sibling = 0, + .base = &virt_base, + .c = { + .dbg_name = "mmss_video_core_clk", + .parent = &video_core_clk_src.c, + .flags = CLKFLAG_NO_RATE_CACHE, + .ops = &clk_ops_branch, + CLK_INIT(mmss_video_core_clk.c), + }, +}; + +static struct branch_clk mmss_video_maxi_clk = { + .cbcr_reg = MMSS_VIDEO_MAXI_CBCR, + .has_sibling = 1, + .base = &virt_base, + .c = { + .dbg_name = "mmss_video_maxi_clk", + .parent = &maxi_clk_src.c, + .ops = &clk_ops_branch, + CLK_INIT(mmss_video_maxi_clk.c), + }, +}; + +static struct branch_clk mmss_vmem_ahb_clk = { + .cbcr_reg = MMSS_VMEM_AHB_CBCR, + .has_sibling = 1, + .base = &virt_base, + .c = { + .dbg_name = "mmss_vmem_ahb_clk", + .ops = &clk_ops_branch, + CLK_INIT(mmss_vmem_ahb_clk.c), + }, +}; + +static struct branch_clk mmss_vmem_maxi_clk = { + .cbcr_reg = MMSS_VMEM_MAXI_CBCR, + .has_sibling = 1, + .base = &virt_base, + .c = { + .dbg_name = "mmss_vmem_maxi_clk", + .parent = &maxi_clk_src.c, + .ops = &clk_ops_branch, + CLK_INIT(mmss_vmem_maxi_clk.c), + }, +}; + +static struct mux_clk mmss_debug_mux = { + .ops = &mux_reg_ops, + .en_mask = BIT(16), + .mask = 0x3FF, + .offset = MMSS_DEBUG_CLK_CTL, + .en_offset = MMSS_DEBUG_CLK_CTL, + .base = &virt_base, + MUX_SRC_LIST( + { &mmss_mnoc_ahb_clk.c, 0x0001 }, + { &mmss_misc_ahb_clk.c, 0x0003 }, + { &mmss_vmem_maxi_clk.c, 0x0009 }, + { &mmss_vmem_ahb_clk.c, 0x000a }, + { &mmss_bimc_smmu_ahb_clk.c, 0x000c }, + { &mmss_bimc_smmu_axi_clk.c, 0x000d }, + { &mmss_video_core_clk.c, 0x000e }, + { &mmss_video_axi_clk.c, 0x000f }, + { &mmss_video_maxi_clk.c, 0x0010 }, + { &mmss_video_ahb_clk.c, 0x0011 }, + { &mmss_mdss_rot_clk.c, 0x0012 }, + { &mmss_snoc_dvm_axi_clk.c, 0x0013 }, + { &mmss_mdss_mdp_clk.c, 0x0014 }, + { &mmss_mdss_mdp_lut_clk.c, 0x0015 }, + { &mmss_mdss_pclk0_clk.c, 0x0016 }, + { &mmss_mdss_pclk1_clk.c, 0x0017 }, + { &mmss_mdss_extpclk_clk.c, 0x0018 }, + { &mmss_video_subcore0_clk.c, 0x001a }, + { &mmss_video_subcore1_clk.c, 0x001b }, + { &mmss_mdss_vsync_clk.c, 0x001c }, + { &mmss_mdss_hdmi_clk.c, 0x001d }, + { &mmss_mdss_byte0_clk.c, 0x001e }, + { &mmss_mdss_byte1_clk.c, 0x001f }, + { &mmss_mdss_esc0_clk.c, 0x0020 }, + { &mmss_mdss_esc1_clk.c, 0x0021 }, + { &mmss_mdss_ahb_clk.c, 0x0022 }, + { &mmss_mdss_hdmi_dp_ahb_clk.c, 0x0023 }, + { &mmss_mdss_axi_clk.c, 0x0024 }, + { &mmss_camss_top_ahb_clk.c, 0x0025 }, + { &mmss_camss_micro_ahb_clk.c, 0x0026 }, + { &mmss_camss_gp0_clk.c, 0x0027 }, + { &mmss_camss_gp1_clk.c, 0x0028 }, + { &mmss_camss_mclk0_clk.c, 0x0029 }, + { &mmss_camss_mclk1_clk.c, 0x002a }, + { &mmss_camss_mclk2_clk.c, 0x002b }, + { &mmss_camss_mclk3_clk.c, 0x002c }, + { &mmss_camss_cci_clk.c, 0x002d }, + { &mmss_camss_cci_ahb_clk.c, 0x002e }, + { &mmss_camss_csi0phytimer_clk.c, 0x002f }, + { &mmss_camss_csi1phytimer_clk.c, 0x0030 }, + { &mmss_camss_csi2phytimer_clk.c, 0x0031 }, + { &mmss_camss_jpeg0_clk.c, 0x0032 }, + { &mmss_camss_ispif_ahb_clk.c, 0x0033 }, + { &mmss_camss_jpeg_ahb_clk.c, 0x0035 }, + { &mmss_camss_jpeg_axi_clk.c, 0x0036 }, + { &mmss_camss_ahb_clk.c, 0x0037 }, + { &mmss_camss_vfe0_clk.c, 0x0038 }, + { &mmss_camss_vfe1_clk.c, 0x0039 }, + { &mmss_camss_cpp_clk.c, 0x003a }, + { &mmss_camss_cpp_ahb_clk.c, 0x003b }, + { &mmss_camss_csi_vfe0_clk.c, 0x003f }, + { &mmss_camss_csi_vfe1_clk.c, 0x0040 }, + { &mmss_camss_csi0_clk.c, 0x0041 }, + { &mmss_camss_csi0_ahb_clk.c, 0x0042 }, + { &mmss_camss_csiphy0_clk.c, 0x0043 }, + { &mmss_camss_csi0rdi_clk.c, 0x0044 }, + { &mmss_camss_csi0pix_clk.c, 0x0045 }, + { &mmss_camss_csi1_clk.c, 0x0046 }, + { &mmss_camss_csi1_ahb_clk.c, 0x0047 }, + { &mmss_camss_csi1rdi_clk.c, 0x0049 }, + { &mmss_camss_csi1pix_clk.c, 0x004a }, + { &mmss_camss_csi2_clk.c, 0x004b }, + { &mmss_camss_csi2_ahb_clk.c, 0x004c }, + { &mmss_camss_csi2rdi_clk.c, 0x004e }, + { &mmss_camss_csi2pix_clk.c, 0x004f }, + { &mmss_camss_csi3_clk.c, 0x0050 }, + { &mmss_camss_csi3_ahb_clk.c, 0x0051 }, + { &mmss_camss_csi3rdi_clk.c, 0x0053 }, + { &mmss_camss_csi3pix_clk.c, 0x0054 }, + { &mmss_mnoc_maxi_clk.c, 0x0070 }, + { &mmss_camss_vfe0_stream_clk.c, 0x0071 }, + { &mmss_camss_vfe1_stream_clk.c, 0x0072 }, + { &mmss_camss_cpp_vbif_ahb_clk.c, 0x0073 }, + { &mmss_misc_cxo_clk.c, 0x0077 }, + { &mmss_camss_cpp_axi_clk.c, 0x007a }, + { &mmss_camss_csiphy1_clk.c, 0x0085 }, + { &mmss_camss_vfe0_ahb_clk.c, 0x0086 }, + { &mmss_camss_vfe1_ahb_clk.c, 0x0087 }, + { &mmss_camss_csiphy2_clk.c, 0x0088 }, + { &mmss_fd_core_clk.c, 0x0089 }, + { &mmss_fd_core_uar_clk.c, 0x008a }, + { &mmss_fd_ahb_clk.c, 0x008c }, + { &mmss_camss_cphy_csid0_clk.c, 0x008d }, + { &mmss_camss_cphy_csid1_clk.c, 0x008e }, + { &mmss_camss_cphy_csid2_clk.c, 0x008f }, + { &mmss_camss_cphy_csid3_clk.c, 0x0090 }, + { &mmss_mdss_dp_link_clk.c, 0x0098 }, + { &mmss_mdss_dp_link_intf_clk.c, 0x0099 }, + { &mmss_mdss_dp_crypto_clk.c, 0x009a }, + { &mmss_mdss_dp_pixel_clk.c, 0x009b }, + { &mmss_mdss_dp_aux_clk.c, 0x009c }, + { &mmss_mdss_dp_gtc_clk.c, 0x009d }, + { &mmss_mdss_byte0_intf_clk.c, 0x00ad }, + { &mmss_mdss_byte1_intf_clk.c, 0x00ae }, + ), + .c = { + .dbg_name = "mmss_debug_mux", + .ops = &clk_ops_gen_mux, + .flags = CLKFLAG_NO_RATE_CACHE, + CLK_INIT(mmss_debug_mux.c), + }, +}; + +static struct clk_lookup msm_clocks_mmss_8998[] = { + CLK_LIST(mmsscc_xo), + CLK_LIST(mmsscc_gpll0), + CLK_LIST(mmsscc_gpll0_div), + CLK_LIST(mmpll0_pll), + CLK_LIST(mmpll0_pll_out), + CLK_LIST(mmpll1_pll), + CLK_LIST(mmpll1_pll_out), + CLK_LIST(mmpll3_pll), + CLK_LIST(mmpll3_pll_out), + CLK_LIST(mmpll4_pll), + CLK_LIST(mmpll4_pll_out), + CLK_LIST(mmpll5_pll), + CLK_LIST(mmpll5_pll_out), + CLK_LIST(mmpll6_pll), + CLK_LIST(mmpll6_pll_out), + CLK_LIST(mmpll7_pll), + CLK_LIST(mmpll7_pll_out), + CLK_LIST(mmpll10_pll), + CLK_LIST(mmpll10_pll_out), + CLK_LIST(ahb_clk_src), + CLK_LIST(csi0_clk_src), + CLK_LIST(vfe0_clk_src), + CLK_LIST(vfe1_clk_src), + CLK_LIST(mdp_clk_src), + CLK_LIST(maxi_clk_src), + CLK_LIST(cpp_clk_src), + CLK_LIST(jpeg0_clk_src), + CLK_LIST(rot_clk_src), + CLK_LIST(video_core_clk_src), + CLK_LIST(csi1_clk_src), + CLK_LIST(csi2_clk_src), + CLK_LIST(csi3_clk_src), + CLK_LIST(fd_core_clk_src), + CLK_LIST(video_subcore0_clk_src), + CLK_LIST(video_subcore1_clk_src), + CLK_LIST(cci_clk_src), + CLK_LIST(csiphy_clk_src), + CLK_LIST(camss_gp0_clk_src), + CLK_LIST(camss_gp1_clk_src), + CLK_LIST(mclk0_clk_src), + CLK_LIST(mclk1_clk_src), + CLK_LIST(mclk2_clk_src), + CLK_LIST(mclk3_clk_src), + CLK_LIST(ext_byte0_clk_src), + CLK_LIST(ext_byte1_clk_src), + CLK_LIST(byte0_clk_src), + CLK_LIST(byte1_clk_src), + CLK_LIST(ext_pclk0_clk_src), + CLK_LIST(ext_pclk1_clk_src), + CLK_LIST(pclk0_clk_src), + CLK_LIST(pclk1_clk_src), + CLK_LIST(ext_extpclk_clk_src), + CLK_LIST(extpclk_clk_src), + CLK_LIST(ext_dp_phy_pll_vco), + CLK_LIST(ext_dp_phy_pll_link), + CLK_LIST(dp_pixel_clk_src), + CLK_LIST(dp_link_clk_src), + CLK_LIST(dp_crypto_clk_src), + CLK_LIST(csi0phytimer_clk_src), + CLK_LIST(csi1phytimer_clk_src), + CLK_LIST(csi2phytimer_clk_src), + CLK_LIST(dp_aux_clk_src), + CLK_LIST(dp_gtc_clk_src), + CLK_LIST(esc0_clk_src), + CLK_LIST(esc1_clk_src), + CLK_LIST(hdmi_clk_src), + CLK_LIST(vsync_clk_src), + CLK_LIST(mmss_bimc_smmu_ahb_clk), + CLK_LIST(mmss_bimc_smmu_axi_clk), + CLK_LIST(mmss_snoc_dvm_axi_clk), + CLK_LIST(mmss_camss_ahb_clk), + CLK_LIST(mmss_camss_cci_ahb_clk), + CLK_LIST(mmss_camss_cci_clk), + CLK_LIST(mmss_camss_cpp_ahb_clk), + CLK_LIST(mmss_camss_cpp_clk), + CLK_LIST(mmss_camss_cpp_axi_clk), + CLK_LIST(mmss_camss_cpp_vbif_ahb_clk), + CLK_LIST(mmss_camss_cphy_csid0_clk), + CLK_LIST(mmss_camss_csi0_ahb_clk), + CLK_LIST(mmss_camss_csi0_clk), + CLK_LIST(mmss_camss_csi0pix_clk), + CLK_LIST(mmss_camss_csi0rdi_clk), + CLK_LIST(mmss_camss_cphy_csid1_clk), + CLK_LIST(mmss_camss_csi1_ahb_clk), + CLK_LIST(mmss_camss_csi1_clk), + CLK_LIST(mmss_camss_csi1pix_clk), + CLK_LIST(mmss_camss_csi1rdi_clk), + CLK_LIST(mmss_camss_cphy_csid2_clk), + CLK_LIST(mmss_camss_csi2_ahb_clk), + CLK_LIST(mmss_camss_csi2_clk), + CLK_LIST(mmss_camss_csi2pix_clk), + CLK_LIST(mmss_camss_csi2rdi_clk), + CLK_LIST(mmss_camss_cphy_csid3_clk), + CLK_LIST(mmss_camss_csi3_ahb_clk), + CLK_LIST(mmss_camss_csi3_clk), + CLK_LIST(mmss_camss_csi3pix_clk), + CLK_LIST(mmss_camss_csi3rdi_clk), + CLK_LIST(mmss_camss_csi_vfe0_clk), + CLK_LIST(mmss_camss_csi_vfe1_clk), + CLK_LIST(mmss_camss_csiphy0_clk), + CLK_LIST(mmss_camss_csiphy1_clk), + CLK_LIST(mmss_camss_csiphy2_clk), + CLK_LIST(mmss_fd_ahb_clk), + CLK_LIST(mmss_fd_core_clk), + CLK_LIST(mmss_fd_core_uar_clk), + CLK_LIST(mmss_camss_gp0_clk), + CLK_LIST(mmss_camss_gp1_clk), + CLK_LIST(mmss_camss_ispif_ahb_clk), + CLK_LIST(mmss_camss_jpeg0_clk), + CLK_LIST(mmss_camss_jpeg0_vote_clk), + CLK_LIST(mmss_camss_jpeg0_dma_vote_clk), + CLK_LIST(mmss_camss_jpeg_ahb_clk), + CLK_LIST(mmss_camss_jpeg_axi_clk), + CLK_LIST(mmss_camss_mclk0_clk), + CLK_LIST(mmss_camss_mclk1_clk), + CLK_LIST(mmss_camss_mclk2_clk), + CLK_LIST(mmss_camss_mclk3_clk), + CLK_LIST(mmss_camss_micro_ahb_clk), + CLK_LIST(mmss_camss_csi0phytimer_clk), + CLK_LIST(mmss_camss_csi1phytimer_clk), + CLK_LIST(mmss_camss_csi2phytimer_clk), + CLK_LIST(mmss_camss_top_ahb_clk), + CLK_LIST(mmss_camss_vfe0_ahb_clk), + CLK_LIST(mmss_camss_vfe0_clk), + CLK_LIST(mmss_camss_vfe0_stream_clk), + CLK_LIST(mmss_camss_vfe1_ahb_clk), + CLK_LIST(mmss_camss_vfe1_clk), + CLK_LIST(mmss_camss_vfe1_stream_clk), + CLK_LIST(mmss_camss_vfe_vbif_ahb_clk), + CLK_LIST(mmss_camss_vfe_vbif_axi_clk), + CLK_LIST(mmss_mdss_ahb_clk), + CLK_LIST(mmss_mdss_axi_clk), + CLK_LIST(mmss_mdss_byte0_clk), + CLK_LIST(mmss_mdss_byte0_intf_div_clk), + CLK_LIST(mmss_mdss_byte0_intf_clk), + CLK_LIST(mmss_mdss_byte1_clk), + CLK_LIST(mmss_mdss_byte0_intf_div_clk), + CLK_LIST(mmss_mdss_byte1_intf_clk), + CLK_LIST(mmss_mdss_dp_aux_clk), + CLK_LIST(mmss_mdss_dp_crypto_clk), + CLK_LIST(mmss_mdss_dp_pixel_clk), + CLK_LIST(mmss_mdss_dp_link_clk), + CLK_LIST(mmss_mdss_dp_link_intf_clk), + CLK_LIST(mmss_mdss_dp_gtc_clk), + CLK_LIST(mmss_mdss_esc0_clk), + CLK_LIST(mmss_mdss_esc1_clk), + CLK_LIST(mmss_mdss_extpclk_clk), + CLK_LIST(mmss_mdss_hdmi_clk), + CLK_LIST(mmss_mdss_hdmi_dp_ahb_clk), + CLK_LIST(mmss_mdss_mdp_clk), + CLK_LIST(mmss_mdss_mdp_lut_clk), + CLK_LIST(mmss_mdss_pclk0_clk), + CLK_LIST(mmss_mdss_pclk1_clk), + CLK_LIST(mmss_mdss_rot_clk), + CLK_LIST(mmss_mdss_vsync_clk), + CLK_LIST(mmss_misc_ahb_clk), + CLK_LIST(mmss_misc_cxo_clk), + CLK_LIST(mmss_mnoc_ahb_clk), + CLK_LIST(mmss_video_subcore0_clk), + CLK_LIST(mmss_video_subcore1_clk), + CLK_LIST(mmss_video_ahb_clk), + CLK_LIST(mmss_video_axi_clk), + CLK_LIST(mmss_video_core_clk), + CLK_LIST(mmss_video_maxi_clk), + CLK_LIST(mmss_vmem_ahb_clk), + CLK_LIST(mmss_vmem_maxi_clk), + CLK_LIST(mmss_mnoc_maxi_clk), + CLK_LIST(mmss_debug_mux), +}; + +static const struct msm_reset_map mmss_8998_resets[] = { + [CAMSS_MICRO_BCR] = { 0x3490 }, +}; + +static void msm_mmsscc_hamster_fixup(void) +{ + mmpll3_pll.c.rate = 1066000000; + mmpll3_pll.c.fmax[VDD_DIG_LOWER] = 533000000; + mmpll3_pll.c.fmax[VDD_DIG_LOW] = 533000000; + mmpll3_pll.c.fmax[VDD_DIG_LOW_L1] = 533000000; + mmpll3_pll.c.fmax[VDD_DIG_NOMINAL] = 1066000000; + mmpll3_pll.c.fmax[VDD_DIG_HIGH] = 1066000000; + + mmpll4_pll.c.fmax[VDD_DIG_LOW] = 384000000; + mmpll4_pll.c.fmax[VDD_DIG_LOW_L1] = 384000000; + mmpll4_pll.c.fmax[VDD_DIG_NOMINAL] = 768000000; + + mmpll5_pll.c.fmax[VDD_DIG_LOW] = 412500000; + mmpll5_pll.c.fmax[VDD_DIG_LOW_L1] = 412500000; + mmpll5_pll.c.fmax[VDD_DIG_NOMINAL] = 825000000; + + mmpll6_pll.c.rate = 888000000; + mmpll6_pll.c.fmax[VDD_DIG_LOWER] = 444000000; + mmpll6_pll.c.fmax[VDD_DIG_LOW] = 444000000; + mmpll6_pll.c.fmax[VDD_DIG_LOW_L1] = 444000000; + mmpll6_pll.c.fmax[VDD_DIG_NOMINAL] = 888000000; + mmpll6_pll.c.fmax[VDD_DIG_HIGH] = 888000000; + + vfe0_clk_src.freq_tbl = ftbl_vfe_clk_src_vq; + vfe0_clk_src.c.fmax[VDD_DIG_LOW] = 404000000; + vfe0_clk_src.c.fmax[VDD_DIG_LOW_L1] = 480000000; + vfe1_clk_src.freq_tbl = ftbl_vfe_clk_src_vq; + vfe1_clk_src.c.fmax[VDD_DIG_LOW] = 404000000; + vfe1_clk_src.c.fmax[VDD_DIG_LOW_L1] = 480000000; + + csi0_clk_src.freq_tbl = ftbl_csi_clk_src_vq; + csi0_clk_src.c.fmax[VDD_DIG_LOW] = 274290000; + csi0_clk_src.c.fmax[VDD_DIG_LOW_L1] = 320000000; + csi1_clk_src.freq_tbl = ftbl_csi_clk_src_vq; + csi1_clk_src.c.fmax[VDD_DIG_LOW] = 274290000; + csi1_clk_src.c.fmax[VDD_DIG_LOW_L1] = 320000000; + csi2_clk_src.freq_tbl = ftbl_csi_clk_src_vq; + csi2_clk_src.c.fmax[VDD_DIG_LOW] = 274290000; + csi2_clk_src.c.fmax[VDD_DIG_LOW_L1] = 320000000; + csi3_clk_src.freq_tbl = ftbl_csi_clk_src_vq; + csi3_clk_src.c.fmax[VDD_DIG_LOW] = 274290000; + csi3_clk_src.c.fmax[VDD_DIG_LOW_L1] = 320000000; + + cpp_clk_src.freq_tbl = ftbl_cpp_clk_src_vq; + cpp_clk_src.c.fmax[VDD_DIG_LOW] = 384000000; + cpp_clk_src.c.fmax[VDD_DIG_LOW_L1] = 404000000; + jpeg0_clk_src.freq_tbl = ftbl_jpeg0_clk_src_vq; + jpeg0_clk_src.c.fmax[VDD_DIG_LOW_L1] = 320000000; + csiphy_clk_src.freq_tbl = ftbl_csiphy_clk_src_vq; + csiphy_clk_src.c.fmax[VDD_DIG_LOW] = 274290000; + csiphy_clk_src.c.fmax[VDD_DIG_LOW_L1] = 300000000; + fd_core_clk_src.freq_tbl = ftbl_fd_core_clk_src_vq; + fd_core_clk_src.c.fmax[VDD_DIG_LOW] = 404000000; + fd_core_clk_src.c.fmax[VDD_DIG_LOW_L1] = 480000000; + + csi0phytimer_clk_src.c.fmax[VDD_DIG_LOW_L1] = 269333333; + csi1phytimer_clk_src.c.fmax[VDD_DIG_LOW_L1] = 269333333; + csi2phytimer_clk_src.c.fmax[VDD_DIG_LOW_L1] = 269333333; + + mdp_clk_src.c.fmax[VDD_DIG_LOW_L1] = 330000000; + extpclk_clk_src.c.fmax[VDD_DIG_LOW] = 312500000; + extpclk_clk_src.c.fmax[VDD_DIG_LOW_L1] = 375000000; + rot_clk_src.c.fmax[VDD_DIG_LOW_L1] = 330000000; + + video_core_clk_src.freq_tbl = ftbl_video_core_clk_src_vq; + video_core_clk_src.c.fmax[VDD_DIG_LOWER] = 200000000; + video_core_clk_src.c.fmax[VDD_DIG_LOW] = 269330000; + video_core_clk_src.c.fmax[VDD_DIG_LOW_L1] = 355200000; + video_core_clk_src.c.fmax[VDD_DIG_NOMINAL] = 444000000; + video_core_clk_src.c.fmax[VDD_DIG_HIGH] = 533000000; + + video_subcore0_clk_src.freq_tbl = ftbl_video_subcore_clk_src_vq; + video_subcore0_clk_src.c.fmax[VDD_DIG_LOWER] = 200000000; + video_subcore0_clk_src.c.fmax[VDD_DIG_LOW] = 269330000; + video_subcore0_clk_src.c.fmax[VDD_DIG_LOW_L1] = 355200000; + video_subcore0_clk_src.c.fmax[VDD_DIG_NOMINAL] = 444000000; + video_subcore0_clk_src.c.fmax[VDD_DIG_HIGH] = 533000000; + + video_subcore1_clk_src.freq_tbl = ftbl_video_subcore_clk_src_vq; + video_subcore1_clk_src.c.fmax[VDD_DIG_LOWER] = 200000000; + video_subcore1_clk_src.c.fmax[VDD_DIG_LOW] = 269330000; + video_subcore1_clk_src.c.fmax[VDD_DIG_LOW_L1] = 355200000; + video_subcore1_clk_src.c.fmax[VDD_DIG_NOMINAL] = 444000000; + video_subcore1_clk_src.c.fmax[VDD_DIG_HIGH] = 533000000; +}; + +static void msm_mmsscc_v2_fixup(void) +{ + csi0_clk_src.c.fmax[VDD_DIG_NOMINAL] = 480000000; + csi1_clk_src.c.fmax[VDD_DIG_NOMINAL] = 480000000; + csi2_clk_src.c.fmax[VDD_DIG_NOMINAL] = 480000000; + csi3_clk_src.c.fmax[VDD_DIG_NOMINAL] = 480000000; +} + +int msm_mmsscc_8998_probe(struct platform_device *pdev) +{ + struct resource *res; + int rc; + struct clk *tmp; + struct regulator *reg; + u32 regval; + bool is_v2 = 0, is_vq = 0; + + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cc_base"); + if (!res) { + dev_err(&pdev->dev, "Unable to retrieve register base.\n"); + return -ENOMEM; + } + virt_base = devm_ioremap(&pdev->dev, res->start, resource_size(res)); + if (!virt_base) { + dev_err(&pdev->dev, "Failed to map CC registers\n"); + return -ENOMEM; + } + + /* Clear the DBG_CLK_DIV bits of the MMSS debug register */ + regval = readl_relaxed(virt_base + mmss_debug_mux.offset); + regval &= ~BM(18, 17); + writel_relaxed(regval, virt_base + mmss_debug_mux.offset); + + reg = vdd_dig.regulator[0] = devm_regulator_get(&pdev->dev, "vdd_dig"); + if (IS_ERR(reg)) { + if (PTR_ERR(reg) != -EPROBE_DEFER) + dev_err(&pdev->dev, "Unable to get vdd_dig regulator!"); + return PTR_ERR(reg); + } + + reg = vdd_mmsscc_mx.regulator[0] = devm_regulator_get(&pdev->dev, + "vdd_mmsscc_mx"); + if (IS_ERR(reg)) { + if (PTR_ERR(reg) != -EPROBE_DEFER) + dev_err(&pdev->dev, "Unable to get vdd_mmsscc_mx regulator!"); + return PTR_ERR(reg); + } + + tmp = mmsscc_xo.c.parent = devm_clk_get(&pdev->dev, "xo"); + if (IS_ERR(tmp)) { + if (PTR_ERR(tmp) != -EPROBE_DEFER) + dev_err(&pdev->dev, "Unable to get xo clock!\n"); + return PTR_ERR(tmp); + } + + tmp = mmsscc_gpll0.c.parent = devm_clk_get(&pdev->dev, "gpll0"); + if (IS_ERR(tmp)) { + if (PTR_ERR(tmp) != -EPROBE_DEFER) + dev_err(&pdev->dev, "Unable to get gpll0 clock!\n"); + return PTR_ERR(tmp); + } + + tmp = mmsscc_gpll0_div.c.parent = devm_clk_get(&pdev->dev, "gpll0_div"); + if (IS_ERR(tmp)) { + if (PTR_ERR(tmp) != -EPROBE_DEFER) + dev_err(&pdev->dev, "Unable to get gpll0_div clock!\n"); + return PTR_ERR(tmp); + } + + ext_pclk0_clk_src.dev = &pdev->dev; + ext_pclk0_clk_src.clk_id = "pclk0_src"; + ext_pclk0_clk_src.c.flags = CLKFLAG_NO_RATE_CACHE; + ext_pclk1_clk_src.dev = &pdev->dev; + ext_pclk1_clk_src.clk_id = "pclk1_src"; + ext_pclk1_clk_src.c.flags = CLKFLAG_NO_RATE_CACHE; + ext_byte0_clk_src.dev = &pdev->dev; + ext_byte0_clk_src.clk_id = "byte0_src"; + ext_byte0_clk_src.c.flags = CLKFLAG_NO_RATE_CACHE; + ext_byte1_clk_src.dev = &pdev->dev; + ext_byte1_clk_src.clk_id = "byte1_src"; + ext_byte1_clk_src.c.flags = CLKFLAG_NO_RATE_CACHE; + ext_extpclk_clk_src.dev = &pdev->dev; + ext_extpclk_clk_src.clk_id = "extpclk_src"; + + ext_dp_phy_pll_link.dev = &pdev->dev; + ext_dp_phy_pll_link.clk_id = "dp_link_src"; + ext_dp_phy_pll_link.c.flags = CLKFLAG_NO_RATE_CACHE; + ext_dp_phy_pll_vco.dev = &pdev->dev; + ext_dp_phy_pll_vco.clk_id = "dp_vco_div"; + ext_dp_phy_pll_vco.c.flags = CLKFLAG_NO_RATE_CACHE; + + mmss_camss_jpeg0_vote_clk.c.flags = CLKFLAG_NO_RATE_CACHE; + mmss_camss_jpeg0_dma_vote_clk.c.flags = CLKFLAG_NO_RATE_CACHE; + + is_vq = of_device_is_compatible(pdev->dev.of_node, + "qcom,mmsscc-hamster"); + if (is_vq) + msm_mmsscc_hamster_fixup(); + + is_v2 = of_device_is_compatible(pdev->dev.of_node, + "qcom,mmsscc-8998-v2"); + if (is_v2) { + msm_mmsscc_hamster_fixup(); + msm_mmsscc_v2_fixup(); + } + + rc = of_msm_clock_register(pdev->dev.of_node, msm_clocks_mmss_8998, + ARRAY_SIZE(msm_clocks_mmss_8998)); + if (rc) + return rc; + + /* Register block resets */ + msm_reset_controller_register(pdev, mmss_8998_resets, + ARRAY_SIZE(mmss_8998_resets), virt_base); + + dev_info(&pdev->dev, "Registered MMSS clocks.\n"); + return 0; +} + +static struct of_device_id msm_clock_mmss_match_table[] = { + { .compatible = "qcom,mmsscc-8998" }, + { .compatible = "qcom,mmsscc-8998-v2" }, + { .compatible = "qcom,mmsscc-hamster" }, + {}, +}; + +static struct platform_driver msm_clock_mmss_driver = { + .probe = msm_mmsscc_8998_probe, + .driver = { + .name = "qcom,mmsscc-8998", + .of_match_table = msm_clock_mmss_match_table, + .owner = THIS_MODULE, + }, +}; + +int __init msm_mmsscc_8998_init(void) +{ + return platform_driver_register(&msm_clock_mmss_driver); +} +arch_initcall(msm_mmsscc_8998_init); diff -Nruw linux-4.4.115-fbx/drivers/clk/msm./clock-osm.c linux-4.4.115-fbx/drivers/clk/msm/clock-osm.c --- linux-4.4.115-fbx/drivers/clk/msm./clock-osm.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-4.4.115-fbx/drivers/clk/msm/clock-osm.c 2019-01-22 16:16:23.019242024 +0100 @@ -0,0 +1,3535 @@ +/* + * Copyright (c) 2016-2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define pr_fmt(fmt) "%s: " fmt, __func__ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include +#include + +#include "clock.h" + +enum clk_osm_bases { + OSM_BASE, + PLL_BASE, + EFUSE_BASE, + ACD_BASE, + NUM_BASES, +}; + +enum clk_osm_lut_data { + FREQ, + FREQ_DATA, + PLL_OVERRIDES, + SPARE_DATA, + VIRTUAL_CORNER, + NUM_FIELDS, +}; + +enum clk_osm_trace_method { + XOR_PACKET, + PERIODIC_PACKET, +}; + +enum clk_osm_trace_packet_id { + TRACE_PACKET0, + TRACE_PACKET1, + TRACE_PACKET2, + TRACE_PACKET3, +}; + +#define SEQ_REG(n) (0x300 + (n) * 4) +#define MEM_ACC_SEQ_REG_CFG_START(n) (SEQ_REG(12 + (n))) +#define MEM_ACC_SEQ_CONST(n) (n) +#define MEM_ACC_INSTR_COMP(n) (0x67 + ((n) * 0x40)) +#define MEM_ACC_SEQ_REG_VAL_START(n) (SEQ_REG(60 + (n))) +#define SEQ_REG1_MSM8998_V2 0x1048 +#define VERSION_REG 0x0 + +#define OSM_TABLE_SIZE 40 +#define MAX_VIRTUAL_CORNER (OSM_TABLE_SIZE - 1) +#define MAX_CLUSTER_CNT 2 +#define CORE_COUNT_VAL(val) ((val & GENMASK(18, 16)) >> 16) +#define SINGLE_CORE 1 +#define MAX_CORE_COUNT 4 +#define LLM_SW_OVERRIDE_CNT 3 +#define OSM_SEQ_MINUS_ONE 0xff + +#define ENABLE_REG 0x1004 +#define INDEX_REG 0x1150 +#define FREQ_REG 0x1154 +#define VOLT_REG 0x1158 +#define OVERRIDE_REG 0x115C +#define SPARE_REG 0x1164 + +#define OSM_CYCLE_COUNTER_CTRL_REG 0x1F00 +#define OSM_CYCLE_COUNTER_STATUS_REG 0x1F04 +#define DCVS_PERF_STATE_DESIRED_REG 0x1F10 +#define DCVS_PERF_STATE_DEVIATION_INTR_STAT 0x1F14 +#define DCVS_PERF_STATE_DEVIATION_INTR_EN 0x1F18 +#define DCVS_PERF_STATE_DEVIATION_INTR_CLEAR 0x1F1C +#define DCVS_PERF_STATE_DEVIATION_CORRECTED_INTR_STAT 0x1F20 +#define DCVS_PERF_STATE_DEVIATION_CORRECTED_INTR_EN 0x1F24 +#define DCVS_PERF_STATE_DEVIATION_CORRECTED_INTR_CLEAR 0x1F28 +#define DCVS_PERF_STATE_MET_INTR_STAT 0x1F2C +#define DCVS_PERF_STATE_MET_INTR_EN 0x1F30 +#define DCVS_PERF_STATE_MET_INTR_CLR 0x1F34 +#define OSM_CORE_TABLE_SIZE 8192 +#define OSM_REG_SIZE 32 + +#define WDOG_DOMAIN_PSTATE_STATUS 0x1c00 +#define WDOG_PROGRAM_COUNTER 0x1c74 + +#define OSM_CYCLE_COUNTER_USE_XO_EDGE_EN BIT(8) +#define PLL_MODE 0x0 +#define PLL_L_VAL 0x4 +#define PLL_USER_CTRL 0xC +#define PLL_CONFIG_CTL_LO 0x10 +#define PLL_TEST_CTL_HI 0x1C +#define PLL_STATUS 0x2C +#define PLL_LOCK_DET_MASK BIT(16) +#define PLL_WAIT_LOCK_TIME_US 10 +#define PLL_WAIT_LOCK_TIME_NS (PLL_WAIT_LOCK_TIME_US * 1000) +#define PLL_MIN_LVAL 43 +#define L_VAL(freq_data) ((freq_data) & GENMASK(7, 0)) + +#define CC_ZERO_BEHAV_CTRL 0x100C +#define SPM_CC_DCVS_DISABLE 0x1020 +#define SPM_CC_CTRL 0x1028 +#define SPM_CC_HYSTERESIS 0x101C +#define SPM_CORE_RET_MAPPING 0x1024 +#define CFG_DELAY_VAL_3 0x12C + +#define LLM_FREQ_VOTE_HYSTERESIS 0x102C +#define LLM_VOLT_VOTE_HYSTERESIS 0x1030 +#define LLM_INTF_DCVS_DISABLE 0x1034 + +#define ENABLE_OVERRIDE BIT(0) + +#define ITM_CL0_DISABLE_CL1_ENABLED 0x2 +#define ITM_CL0_ENABLED_CL1_DISABLE 0x1 + +#define APM_MX_MODE 0 +#define APM_APC_MODE BIT(1) +#define APM_MODE_SWITCH_MASK (BVAL(4, 2, 7) | BVAL(1, 0, 3)) +#define APM_MX_MODE_VAL 0 +#define APM_APC_MODE_VAL 0x3 + +#define GPLL_SEL 0x400 +#define PLL_EARLY_SEL 0x500 +#define PLL_MAIN_SEL 0x300 +#define RCG_UPDATE 0x3 +#define RCG_UPDATE_SUCCESS 0x2 +#define PLL_POST_DIV1 0x1F +#define PLL_POST_DIV2 0x11F + +#define LLM_SW_OVERRIDE_REG 0x1038 +#define VMIN_REDUC_ENABLE_REG 0x103C +#define VMIN_REDUC_TIMER_REG 0x1040 +#define PDN_FSM_CTRL_REG 0x1070 +#define CC_BOOST_TIMER_REG0 0x1074 +#define CC_BOOST_TIMER_REG1 0x1078 +#define CC_BOOST_TIMER_REG2 0x107C +#define CC_BOOST_EN_MASK BIT(0) +#define PS_BOOST_EN_MASK BIT(1) +#define DCVS_BOOST_EN_MASK BIT(2) +#define PC_RET_EXIT_DROOP_EN_MASK BIT(3) +#define WFX_DROOP_EN_MASK BIT(4) +#define DCVS_DROOP_EN_MASK BIT(5) +#define LMH_PS_EN_MASK BIT(6) +#define IGNORE_PLL_LOCK_MASK BIT(15) +#define SAFE_FREQ_WAIT_NS 5000 +#define DEXT_DECREMENT_WAIT_NS 1000 +#define DCVS_BOOST_TIMER_REG0 0x1084 +#define DCVS_BOOST_TIMER_REG1 0x1088 +#define DCVS_BOOST_TIMER_REG2 0x108C +#define PS_BOOST_TIMER_REG0 0x1094 +#define PS_BOOST_TIMER_REG1 0x1098 +#define PS_BOOST_TIMER_REG2 0x109C +#define BOOST_PROG_SYNC_DELAY_REG 0x10A0 +#define DROOP_CTRL_REG 0x10A4 +#define DROOP_RELEASE_TIMER_CTRL 0x10A8 +#define DROOP_PROG_SYNC_DELAY_REG 0x10BC +#define DROOP_UNSTALL_TIMER_CTRL_REG 0x10AC +#define DROOP_WAIT_TO_RELEASE_TIMER_CTRL0_REG 0x10B0 +#define DROOP_WAIT_TO_RELEASE_TIMER_CTRL1_REG 0x10B4 +#define OSM_PLL_SW_OVERRIDE_EN 0x10C0 + +#define PLL_SW_OVERRIDE_DROOP_EN BIT(0) +#define DCVS_DROOP_TIMER_CTRL 0x10B8 +#define SEQ_MEM_ADDR 0x500 +#define SEQ_CFG_BR_ADDR 0x170 +#define MAX_INSTRUCTIONS 256 +#define MAX_BR_INSTRUCTIONS 49 + +#define MAX_MEM_ACC_LEVELS 3 +#define MAX_MEM_ACC_VAL_PER_LEVEL 3 +#define MAX_MEM_ACC_VALUES (MAX_MEM_ACC_LEVELS * \ + MAX_MEM_ACC_VAL_PER_LEVEL) +#define MEM_ACC_APM_READ_MASK 0xff + +#define TRACE_CTRL 0x1F38 +#define TRACE_CTRL_EN_MASK BIT(0) +#define TRACE_CTRL_ENABLE 1 +#define TRACE_CTRL_DISABLE 0 +#define TRACE_CTRL_ENABLE_WDOG_STATUS BIT(30) +#define TRACE_CTRL_PACKET_TYPE_MASK BVAL(2, 1, 3) +#define TRACE_CTRL_PACKET_TYPE_SHIFT 1 +#define TRACE_CTRL_PERIODIC_TRACE_EN_MASK BIT(3) +#define TRACE_CTRL_PERIODIC_TRACE_ENABLE BIT(3) +#define PERIODIC_TRACE_TIMER_CTRL 0x1F3C +#define PERIODIC_TRACE_MIN_NS 1000 +#define PERIODIC_TRACE_MAX_NS 21474836475 +#define PERIODIC_TRACE_DEFAULT_NS 1000000 + +#define PLL_DD_USER_CTL_LO_ENABLE 0x0f04c408 +#define PLL_DD_USER_CTL_LO_DISABLE 0x1f04c41f +#define PLL_DD_D0_USER_CTL_LO 0x17916208 +#define PLL_DD_D1_USER_CTL_LO 0x17816208 + +#define PWRCL_EFUSE_SHIFT 0 +#define PWRCL_EFUSE_MASK 0 +#define PERFCL_EFUSE_SHIFT 29 +#define PERFCL_EFUSE_MASK 0x7 + +#define MSM8998V1_PWRCL_BOOT_RATE 1478400000 +#define MSM8998V1_PERFCL_BOOT_RATE 1536000000 +#define MSM8998V2_PWRCL_BOOT_RATE 1555200000 +#define MSM8998V2_PERFCL_BOOT_RATE 1728000000 + +#define DEBUG_REG_NUM 3 + +/* ACD registers */ +#define ACD_HW_VERSION 0x0 +#define ACDCR 0x4 +#define ACDTD 0x8 +#define ACDSSCR 0x28 +#define ACD_EXTINT_CFG 0x30 +#define ACD_DCVS_SW 0x34 +#define ACD_GFMUX_CFG 0x3c +#define ACD_READOUT_CFG 0x48 +#define ACD_AUTOXFER_CFG 0x80 +#define ACD_AUTOXFER 0x84 +#define ACD_AUTOXFER_CTL 0x88 +#define ACD_AUTOXFER_STATUS 0x8c +#define ACD_WRITE_CTL 0x90 +#define ACD_WRITE_STATUS 0x94 +#define ACD_READOUT 0x98 + +#define ACD_MASTER_ONLY_REG_ADDR 0x80 +#define ACD_WRITE_CTL_UPDATE_EN BIT(0) +#define ACD_WRITE_CTL_SELECT_SHIFT 1 +#define ACD_GFMUX_CFG_SELECT BIT(0) +#define ACD_AUTOXFER_START_CLEAR 0 +#define ACD_AUTOXFER_START_SET BIT(0) +#define AUTO_XFER_DONE_MASK BIT(0) +#define ACD_DCVS_SW_DCVS_IN_PRGR_SET BIT(0) +#define ACD_DCVS_SW_DCVS_IN_PRGR_CLEAR 0 +#define ACD_LOCAL_TRANSFER_TIMEOUT_NS 500 + +static void __iomem *virt_base; +static void __iomem *debug_base; + +#define lmh_lite_clk_src_source_val 1 + +#define ACD_REG_RELATIVE_ADDR(addr) (addr / 4) +#define ACD_REG_RELATIVE_ADDR_BITMASK(addr) \ + (1 << (ACD_REG_RELATIVE_ADDR(addr))) + +#define FIXDIV(div) (div ? (2 * (div) - 1) : (0)) + +#define F(f, s, div, m, n) \ + { \ + .freq_hz = (f), \ + .src_clk = &s.c, \ + .m_val = (m), \ + .n_val = ~((n)-(m)) * !!(n), \ + .d_val = ~(n),\ + .div_src_val = BVAL(4, 0, (int)FIXDIV(div)) \ + | BVAL(10, 8, s##_source_val), \ + } + +static u32 seq_instr[] = { + 0xc2005000, 0x2c9e3b21, 0xc0ab2cdc, 0xc2882525, 0x359dc491, + 0x700a500b, 0x5001aefc, 0xaefd7000, 0x390938c8, 0xcb44c833, + 0xce56cd54, 0x341336e0, 0xa4baadba, 0xb480a493, 0x10004000, + 0x70005001, 0x1000500c, 0xc792c5a1, 0x501625e1, 0x3da335a2, + 0x50170006, 0x50150006, 0x1000c633, 0x1000acb3, 0xc422acb4, + 0xaefc1000, 0x700a500b, 0x70005001, 0x5010aefd, 0x5012700b, + 0xad41700c, 0x84e5adb9, 0xb3808566, 0x239b0003, 0x856484e3, + 0xb9800007, 0x2bad0003, 0xac3aa20b, 0x0003181b, 0x0003bb40, + 0xa30d239b, 0x500c181b, 0x5011500f, 0x181b3413, 0x853984b9, + 0x0003bd80, 0xa0012ba4, 0x72050803, 0x500e1000, 0x500c1000, + 0x1c011c0a, 0x3b181c06, 0x1c073b43, 0x1c061000, 0x1c073983, + 0x1c02500c, 0x10001c0a, 0x70015002, 0x81031000, 0x70025003, + 0x70035004, 0x3b441000, 0x81553985, 0x70025003, 0x50054003, + 0xa1467009, 0x0003b1c0, 0x4005238b, 0x835a1000, 0x855c84db, + 0x1000a51f, 0x84de835d, 0xa52c855c, 0x50061000, 0x39cd3a4c, + 0x3ad03a8f, 0x10004006, 0x70065007, 0xa00f2c12, 0x08034007, + 0xaefc7205, 0xaefd700d, 0xa9641000, 0x40071c1a, 0x700daefc, + 0x1000aefd, 0x70065007, 0x50101c16, 0x40075012, 0x700daefc, + 0x2411aefd, 0xa8211000, 0x0803a00f, 0x500c7005, 0x1c1591e0, + 0x500f5014, 0x10005011, 0x500c2bd4, 0x0803a00f, 0x10007205, + 0xa00fa9d1, 0x0803a821, 0xa9d07005, 0x91e0500c, 0x500f1c15, + 0x10005011, 0x1c162bce, 0x50125010, 0xa022a82a, 0x70050803, + 0x1c1591df, 0x5011500f, 0x5014500c, 0x0803a00f, 0x10007205, + 0x501391a4, 0x22172217, 0x70075008, 0xa9634008, 0x1c1a0006, + 0x70085009, 0x10004009, 0x00008ed9, 0x3e05c8dd, 0x1c033604, + 0xabaf1000, 0x856284e1, 0x0003bb80, 0x1000239f, 0x0803a037, + 0x10007205, 0x8dc61000, 0x38a71c2a, 0x1c2a8dc4, 0x100038a6, + 0x1c2a8dc5, 0x8dc73867, 0x38681c2a, 0x8c491000, 0x8d4b8cca, + 0x10001c00, 0x8ccd8c4c, 0x1c008d4e, 0x8c4f1000, 0x8d518cd0, + 0x10001c00, 0xa759a79a, 0x1000a718, 0xbf80af9b, 0x00001000, +}; + +static u32 seq_br_instr[] = { + 0x248, 0x20e, 0x21c, 0xf6, 0x112, + 0x11c, 0xe4, 0xea, 0xc6, 0xd6, + 0x126, 0x108, 0x184, 0x1a8, 0x1b0, + 0x134, 0x158, 0x16e, 0x14a, 0xc2, + 0x190, 0x1d2, 0x1cc, 0x1d4, 0x1e8, + 0x0, 0x1f6, 0x32, 0x66, 0xb0, + 0xa6, 0x1fc, 0x3c, 0x44, 0x5c, + 0x60, 0x204, 0x30, 0x22a, 0x234, + 0x23e, 0x0, 0x250, 0x0, 0x0, 0x9a, + 0x20c, +}; + +DEFINE_EXT_CLK(xo_ao, NULL); +DEFINE_EXT_CLK(sys_apcsaux_clk_gcc, NULL); +DEFINE_EXT_CLK(lmh_lite_clk_src, NULL); + +struct osm_entry { + u16 virtual_corner; + u16 open_loop_volt; + u32 freq_data; + u32 override_data; + u32 spare_data; + long frequency; +}; + +const char *clk_panic_reg_names[] = {"WDOG_DOMAIN_PSTATE_STATUS", + "WDOG_PROGRAM_COUNTER", + "APM_STATUS"}; +const int clk_panic_reg_offsets[] = {WDOG_DOMAIN_PSTATE_STATUS, + WDOG_PROGRAM_COUNTER}; + +static struct dentry *osm_debugfs_base; + +struct clk_osm { + struct clk c; + struct osm_entry osm_table[OSM_TABLE_SIZE]; + struct dentry *debugfs; + struct regulator *vdd_reg; + struct platform_device *vdd_dev; + void *vbases[NUM_BASES]; + unsigned long pbases[NUM_BASES]; + void __iomem *debug_regs[DEBUG_REG_NUM]; + spinlock_t lock; + + u32 cpu_reg_mask; + u32 num_entries; + u32 cluster_num; + u32 irq; + u32 apm_crossover_vc; + u32 apm_threshold_pre_vc; + u32 apm_threshold_vc; + u32 mem_acc_crossover_vc; + u32 mem_acc_threshold_pre_vc; + u32 mem_acc_threshold_vc; + u32 cycle_counter_reads; + u32 cycle_counter_delay; + u32 cycle_counter_factor; + u64 total_cycle_counter; + u32 prev_cycle_counter; + u32 l_val_base; + u32 apcs_itm_present; + u32 apcs_cfg_rcgr; + u32 apcs_cmd_rcgr; + u32 apcs_pll_user_ctl; + u32 apcs_mem_acc_cfg[MAX_MEM_ACC_VAL_PER_LEVEL]; + u32 apcs_mem_acc_val[MAX_MEM_ACC_VALUES]; + u32 llm_sw_overr[LLM_SW_OVERRIDE_CNT]; + u32 apm_mode_ctl; + u32 apm_ctrl_status; + u32 osm_clk_rate; + u32 xo_clk_rate; + u32 acd_td; + u32 acd_cr; + u32 acd_sscr; + u32 acd_extint0_cfg; + u32 acd_extint1_cfg; + u32 acd_autoxfer_ctl; + u32 acd_debugfs_addr; + u32 acd_debugfs_addr_size; + bool acd_init; + bool secure_init; + bool red_fsm_en; + bool boost_fsm_en; + bool safe_fsm_en; + bool ps_fsm_en; + bool droop_fsm_en; + bool wfx_fsm_en; + bool pc_fsm_en; + + enum clk_osm_trace_method trace_method; + enum clk_osm_trace_packet_id trace_id; + struct notifier_block panic_notifier; + u32 trace_periodic_timer; + bool trace_en; + bool wdog_trace_en; +}; + +static bool msm8998_v1; +static bool msm8998_v2; + +static inline void clk_osm_masked_write_reg(struct clk_osm *c, u32 val, + u32 offset, u32 mask) +{ + u32 val2, orig_val; + + val2 = orig_val = readl_relaxed((char *)c->vbases[OSM_BASE] + offset); + val2 &= ~mask; + val2 |= val & mask; + + if (val2 != orig_val) + writel_relaxed(val2, (char *)c->vbases[OSM_BASE] + offset); +} + +static inline void clk_osm_write_reg(struct clk_osm *c, u32 val, u32 offset) +{ + writel_relaxed(val, (char *)c->vbases[OSM_BASE] + offset); +} + +static inline int clk_osm_read_reg(struct clk_osm *c, u32 offset) +{ + return readl_relaxed((char *)c->vbases[OSM_BASE] + offset); +} + +static inline int clk_osm_read_reg_no_log(struct clk_osm *c, u32 offset) +{ + return readl_relaxed_no_log((char *)c->vbases[OSM_BASE] + offset); +} + +static inline int clk_osm_mb(struct clk_osm *c, int base) +{ + return readl_relaxed_no_log((char *)c->vbases[base] + VERSION_REG); +} + +static inline int clk_osm_acd_mb(struct clk_osm *c) +{ + return readl_relaxed_no_log((char *)c->vbases[ACD_BASE] + + ACD_HW_VERSION); +} + +static inline void clk_osm_acd_master_write_reg(struct clk_osm *c, + u32 val, u32 offset) +{ + writel_relaxed(val, (char *)c->vbases[ACD_BASE] + offset); +} + +static int clk_osm_acd_local_read_reg(struct clk_osm *c, u32 offset) +{ + u32 reg = 0; + int timeout; + + if (offset >= ACD_MASTER_ONLY_REG_ADDR) { + pr_err("ACD register at offset=0x%x not locally readable\n", + offset); + return -EINVAL; + } + + /* Set select field in read control register */ + writel_relaxed(ACD_REG_RELATIVE_ADDR(offset), + (char *)c->vbases[ACD_BASE] + ACD_READOUT_CFG); + + /* Clear write control register */ + writel_relaxed(reg, (char *)c->vbases[ACD_BASE] + ACD_WRITE_CTL); + + /* Set select and update_en fields in write control register */ + reg = (ACD_REG_RELATIVE_ADDR(ACD_READOUT_CFG) + << ACD_WRITE_CTL_SELECT_SHIFT) + | ACD_WRITE_CTL_UPDATE_EN; + writel_relaxed(reg, (char *)c->vbases[ACD_BASE] + ACD_WRITE_CTL); + + /* Ensure writes complete before polling */ + clk_osm_acd_mb(c); + + /* Poll write status register */ + for (timeout = ACD_LOCAL_TRANSFER_TIMEOUT_NS; timeout > 0; + timeout -= 100) { + reg = readl_relaxed((char *)c->vbases[ACD_BASE] + + ACD_WRITE_STATUS); + if ((reg & (ACD_REG_RELATIVE_ADDR_BITMASK(ACD_READOUT_CFG)))) + break; + ndelay(100); + } + + if (!timeout) { + pr_err("local read timed out, offset=0x%x status=0x%x\n", + offset, reg); + return -ETIMEDOUT; + } + + reg = readl_relaxed((char *)c->vbases[ACD_BASE] + + ACD_READOUT); + return reg; +} + +static int clk_osm_acd_local_write_reg(struct clk_osm *c, u32 val, u32 offset) +{ + u32 reg = 0; + int timeout; + + if (offset >= ACD_MASTER_ONLY_REG_ADDR) { + pr_err("ACD register at offset=0x%x not transferrable\n", + offset); + return -EINVAL; + } + + /* Clear write control register */ + writel_relaxed(reg, (char *)c->vbases[ACD_BASE] + ACD_WRITE_CTL); + + /* Set select and update_en fields in write control register */ + reg = (ACD_REG_RELATIVE_ADDR(offset) << ACD_WRITE_CTL_SELECT_SHIFT) + | ACD_WRITE_CTL_UPDATE_EN; + writel_relaxed(reg, (char *)c->vbases[ACD_BASE] + ACD_WRITE_CTL); + + /* Ensure writes complete before polling */ + clk_osm_acd_mb(c); + + /* Poll write status register */ + for (timeout = ACD_LOCAL_TRANSFER_TIMEOUT_NS; timeout > 0; + timeout -= 100) { + reg = readl_relaxed((char *)c->vbases[ACD_BASE] + + ACD_WRITE_STATUS); + if ((reg & (ACD_REG_RELATIVE_ADDR_BITMASK(offset)))) + break; + ndelay(100); + } + + if (!timeout) { + pr_err("local write timed out, offset=0x%x val=0x%x status=0x%x\n", + offset, val, reg); + return -ETIMEDOUT; + } + + return 0; +} + +static int clk_osm_acd_master_write_through_reg(struct clk_osm *c, + u32 val, u32 offset) +{ + writel_relaxed(val, (char *)c->vbases[ACD_BASE] + offset); + + /* Ensure writes complete before transfer to local copy */ + clk_osm_acd_mb(c); + + return clk_osm_acd_local_write_reg(c, val, offset); +} + +static int clk_osm_acd_auto_local_write_reg(struct clk_osm *c, u32 mask) +{ + u32 numregs, bitmask = mask; + u32 reg = 0; + int timeout; + + /* count number of bits set in register mask */ + for (numregs = 0; bitmask; numregs++) + bitmask &= bitmask - 1; + + /* Program auto-transfter mask */ + writel_relaxed(mask, (char *)c->vbases[ACD_BASE] + ACD_AUTOXFER_CFG); + + /* Clear start field in auto-transfer register */ + writel_relaxed(ACD_AUTOXFER_START_CLEAR, + (char *)c->vbases[ACD_BASE] + ACD_AUTOXFER); + + /* Set start field in auto-transfer register */ + writel_relaxed(ACD_AUTOXFER_START_SET, + (char *)c->vbases[ACD_BASE] + ACD_AUTOXFER); + + /* Ensure writes complete before polling */ + clk_osm_acd_mb(c); + + /* Poll auto-transfer status register */ + for (timeout = ACD_LOCAL_TRANSFER_TIMEOUT_NS * numregs; + timeout > 0; timeout -= 100) { + reg = readl_relaxed((char *)c->vbases[ACD_BASE] + + ACD_AUTOXFER_STATUS); + if (reg & AUTO_XFER_DONE_MASK) + break; + ndelay(100); + } + + if (!timeout) { + pr_err("local register auto-transfer timed out, mask=0x%x registers=%d status=0x%x\n", + mask, numregs, reg); + return -ETIMEDOUT; + } + + return 0; +} + +static int clk_osm_acd_init(struct clk_osm *c) +{ + + int rc = 0; + u32 auto_xfer_mask = 0; + + if (!c->acd_init) + return 0; + + c->acd_debugfs_addr = ACD_HW_VERSION; + + /* Program ACD tunable-length delay register */ + clk_osm_acd_master_write_reg(c, c->acd_td, ACDTD); + auto_xfer_mask |= ACD_REG_RELATIVE_ADDR_BITMASK(ACDTD); + + /* Program ACD control register */ + clk_osm_acd_master_write_reg(c, c->acd_cr, ACDCR); + auto_xfer_mask |= ACD_REG_RELATIVE_ADDR_BITMASK(ACDCR); + + /* Program ACD soft start control register */ + clk_osm_acd_master_write_reg(c, c->acd_sscr, ACDSSCR); + auto_xfer_mask |= ACD_REG_RELATIVE_ADDR_BITMASK(ACDSSCR); + + /* Program initial ACD external interface configuration register */ + clk_osm_acd_master_write_reg(c, c->acd_extint0_cfg, ACD_EXTINT_CFG); + auto_xfer_mask |= ACD_REG_RELATIVE_ADDR_BITMASK(ACD_EXTINT_CFG); + + /* Program ACD auto-register transfer control register */ + clk_osm_acd_master_write_reg(c, c->acd_autoxfer_ctl, ACD_AUTOXFER_CTL); + + /* Ensure writes complete before transfers to local copy */ + clk_osm_acd_mb(c); + + /* Transfer master copies */ + rc = clk_osm_acd_auto_local_write_reg(c, auto_xfer_mask); + if (rc) + return rc; + + /* Switch CPUSS clock source to ACD clock */ + rc = clk_osm_acd_master_write_through_reg(c, ACD_GFMUX_CFG_SELECT, + ACD_GFMUX_CFG); + if (rc) + return rc; + + /* Program ACD_DCVS_SW */ + rc = clk_osm_acd_master_write_through_reg(c, + ACD_DCVS_SW_DCVS_IN_PRGR_SET, + ACD_DCVS_SW); + if (rc) + return rc; + + rc = clk_osm_acd_master_write_through_reg(c, + ACD_DCVS_SW_DCVS_IN_PRGR_CLEAR, + ACD_DCVS_SW); + if (rc) + return rc; + + udelay(1); + + /* Program final ACD external interface configuration register */ + rc = clk_osm_acd_master_write_through_reg(c, c->acd_extint1_cfg, + ACD_EXTINT_CFG); + if (rc) + return rc; + + /* + * ACDCR, ACDTD, ACDSSCR, ACD_EXTINT_CFG, ACD_GFMUX_CFG + * must be copied from master to local copy on PC exit. + */ + auto_xfer_mask |= ACD_REG_RELATIVE_ADDR_BITMASK(ACD_GFMUX_CFG); + clk_osm_acd_master_write_reg(c, auto_xfer_mask, ACD_AUTOXFER_CFG); + + /* ACD has been initialized and enabled for this cluster */ + c->acd_init = false; + return 0; +} + +static inline int clk_osm_count_ns(struct clk_osm *c, u64 nsec) +{ + u64 temp; + + temp = (u64)c->osm_clk_rate * nsec; + do_div(temp, 1000000000); + + return temp; +} + +static inline struct clk_osm *to_clk_osm(struct clk *c) +{ + return container_of(c, struct clk_osm, c); +} + +static enum handoff clk_osm_handoff(struct clk *c) +{ + return HANDOFF_DISABLED_CLK; +} + +static long clk_osm_list_rate(struct clk *c, unsigned n) +{ + if (n >= c->num_fmax) + return -ENXIO; + return c->fmax[n]; +} + +static long clk_osm_round_rate(struct clk *c, unsigned long rate) +{ + int i; + unsigned long rrate = 0; + + /* + * If the rate passed in is 0, return the first frequency in + * the FMAX table. + */ + if (!rate) + return c->fmax[0]; + + for (i = 0; i < c->num_fmax; i++) { + if (is_better_rate(rate, rrate, c->fmax[i])) { + rrate = c->fmax[i]; + if (rrate == rate) + break; + } + } + + return rrate; +} + +static int clk_osm_search_table(struct osm_entry *table, int entries, long rate) +{ + int quad_core_index, single_core_index = 0; + int core_count; + + for (quad_core_index = 0; quad_core_index < entries; + quad_core_index++) { + core_count = + CORE_COUNT_VAL(table[quad_core_index].freq_data); + if (rate == table[quad_core_index].frequency && + core_count == SINGLE_CORE) { + single_core_index = quad_core_index; + continue; + } + if (rate == table[quad_core_index].frequency && + core_count == MAX_CORE_COUNT) + return quad_core_index; + } + if (single_core_index) + return single_core_index; + + return -EINVAL; +} + +static int clk_osm_set_rate(struct clk *c, unsigned long rate) +{ + struct clk_osm *cpuclk = to_clk_osm(c); + int index = 0; + unsigned long r_rate; + + r_rate = clk_osm_round_rate(c, rate); + + if (rate != r_rate) { + pr_err("invalid rate requested rate=%ld\n", rate); + return -EINVAL; + } + + /* Convert rate to table index */ + index = clk_osm_search_table(cpuclk->osm_table, + cpuclk->num_entries, r_rate); + if (index < 0) { + pr_err("cannot set cluster %u to %lu\n", + cpuclk->cluster_num, rate); + return -EINVAL; + } + pr_debug("rate: %lu --> index %d\n", rate, index); + + if (cpuclk->llm_sw_overr[0]) { + clk_osm_write_reg(cpuclk, cpuclk->llm_sw_overr[0], + LLM_SW_OVERRIDE_REG); + clk_osm_write_reg(cpuclk, cpuclk->llm_sw_overr[1], + LLM_SW_OVERRIDE_REG); + udelay(1); + } + + /* Choose index and send request to OSM hardware */ + clk_osm_write_reg(cpuclk, index, DCVS_PERF_STATE_DESIRED_REG); + + if (cpuclk->llm_sw_overr[0]) { + udelay(1); + clk_osm_write_reg(cpuclk, cpuclk->llm_sw_overr[2], + LLM_SW_OVERRIDE_REG); + } + + /* Make sure the write goes through before proceeding */ + clk_osm_mb(cpuclk, OSM_BASE); + + return 0; +} + +static int clk_osm_enable(struct clk *c) +{ + struct clk_osm *cpuclk = to_clk_osm(c); + int rc; + + rc = clk_osm_acd_init(cpuclk); + if (rc) { + pr_err("Failed to initialize ACD for cluster %d, rc=%d\n", + cpuclk->cluster_num, rc); + return rc; + } + + /* Wait for 5 usecs before enabling OSM */ + udelay(5); + + clk_osm_write_reg(cpuclk, 1, ENABLE_REG); + + /* Make sure the write goes through before proceeding */ + clk_osm_mb(cpuclk, OSM_BASE); + + /* Wait for 5us for OSM hardware to enable */ + udelay(5); + + pr_debug("OSM clk enabled for cluster=%d\n", cpuclk->cluster_num); + + return 0; +} + +static struct clk_ops clk_ops_cpu_osm = { + .enable = clk_osm_enable, + .set_rate = clk_osm_set_rate, + .round_rate = clk_osm_round_rate, + .list_rate = clk_osm_list_rate, + .handoff = clk_osm_handoff, +}; + +static struct regulator *vdd_pwrcl; +static struct regulator *vdd_perfcl; + +static struct clk_freq_tbl ftbl_osm_clk_src[] = { + F( 200000000, lmh_lite_clk_src, 1.5, 0, 0), + F_END +}; + +static struct rcg_clk osm_clk_src = { + .cmd_rcgr_reg = APCS_COMMON_LMH_CMD_RCGR, + .set_rate = set_rate_hid, + .freq_tbl = ftbl_osm_clk_src, + .current_freq = &rcg_dummy_freq, + .base = &virt_base, + .c = { + .dbg_name = "osm_clk_src", + .ops = &clk_ops_rcg, + CLK_INIT(osm_clk_src.c), + }, +}; + +static struct clk_osm pwrcl_clk = { + .cluster_num = 0, + .cpu_reg_mask = 0x3, + .c = { + .dbg_name = "pwrcl_clk", + .ops = &clk_ops_cpu_osm, + .parent = &xo_ao.c, + CLK_INIT(pwrcl_clk.c), + }, +}; + +static struct clk_osm perfcl_clk = { + .cluster_num = 1, + .cpu_reg_mask = 0x103, + .c = { + .dbg_name = "perfcl_clk", + .ops = &clk_ops_cpu_osm, + .parent = &xo_ao.c, + CLK_INIT(perfcl_clk.c), + }, +}; + +static struct clk_ops clk_ops_cpu_dbg_mux; + +static struct mux_clk cpu_debug_mux = { + .offset = 0x0, + .mask = 0x3, + .shift = 8, + .ops = &mux_reg_ops, + MUX_SRC_LIST( + { &pwrcl_clk.c, 0x00 }, + { &perfcl_clk.c, 0x01 }, + ), + .base = &debug_base, + .c = { + .dbg_name = "cpu_debug_mux", + .ops = &clk_ops_cpu_dbg_mux, + .flags = CLKFLAG_NO_RATE_CACHE, + CLK_INIT(cpu_debug_mux.c), + }, +}; + +static struct clk_lookup cpu_clocks_osm[] = { + CLK_LIST(pwrcl_clk), + CLK_LIST(perfcl_clk), + CLK_LIST(sys_apcsaux_clk_gcc), + CLK_LIST(xo_ao), + CLK_LIST(osm_clk_src), + CLK_LIST(cpu_debug_mux), +}; + +static unsigned long cpu_dbg_mux_get_rate(struct clk *clk) +{ + /* Account for the divider between the clock and the debug mux */ + if (!strcmp(clk->parent->dbg_name, "pwrcl_clk")) + return clk->rate/4; + else if (!strcmp(clk->parent->dbg_name, "perfcl_clk")) + return clk->rate/8; + return clk->rate; +} + +static void clk_osm_print_osm_table(struct clk_osm *c) +{ + int i; + struct osm_entry *table = c->osm_table; + u32 pll_src, pll_div, lval, core_count; + + pr_debug("Index, Frequency, VC, OLV (mv), Core Count, PLL Src, PLL Div, L-Val, ACC Level\n"); + for (i = 0; i < c->num_entries; i++) { + pll_src = (table[i].freq_data & GENMASK(27, 26)) >> 26; + pll_div = (table[i].freq_data & GENMASK(25, 24)) >> 24; + lval = L_VAL(table[i].freq_data); + core_count = (table[i].freq_data & GENMASK(18, 16)) >> 16; + + pr_debug("%3d, %11lu, %2u, %5u, %2u, %6u, %8u, %7u, %5u\n", + i, + table[i].frequency, + table[i].virtual_corner, + table[i].open_loop_volt, + core_count, + pll_src, + pll_div, + lval, + table[i].spare_data); + } + pr_debug("APM threshold corner=%d, crossover corner=%d\n", + c->apm_threshold_vc, c->apm_crossover_vc); + pr_debug("MEM-ACC threshold corner=%d, crossover corner=%d\n", + c->mem_acc_threshold_vc, c->mem_acc_crossover_vc); +} + +static int clk_osm_get_lut(struct platform_device *pdev, + struct clk_osm *c, char *prop_name) +{ + struct clk *clk = &c->c; + struct device_node *of = pdev->dev.of_node; + int prop_len, total_elems, num_rows, i, j, k; + int rc = 0; + u32 *array; + u32 *fmax_temp; + u32 data; + bool last_entry = false; + unsigned long abs_fmax = 0; + + if (!of_find_property(of, prop_name, &prop_len)) { + dev_err(&pdev->dev, "missing %s\n", prop_name); + return -EINVAL; + } + + total_elems = prop_len / sizeof(u32); + if (total_elems % NUM_FIELDS) { + dev_err(&pdev->dev, "bad length %d\n", prop_len); + return -EINVAL; + } + + num_rows = total_elems / NUM_FIELDS; + + fmax_temp = devm_kzalloc(&pdev->dev, num_rows * sizeof(unsigned long), + GFP_KERNEL); + if (!fmax_temp) + return -ENOMEM; + + array = devm_kzalloc(&pdev->dev, prop_len, GFP_KERNEL); + if (!array) + return -ENOMEM; + + rc = of_property_read_u32_array(of, prop_name, array, total_elems); + if (rc) { + dev_err(&pdev->dev, "Unable to parse OSM table, rc=%d\n", rc); + goto exit; + } + + pr_debug("%s: Entries in Table: %d\n", __func__, num_rows); + c->num_entries = num_rows; + if (c->num_entries > OSM_TABLE_SIZE) { + pr_err("LUT entries %d exceed maximum size %d\n", + c->num_entries, OSM_TABLE_SIZE); + return -EINVAL; + } + + for (i = 0, j = 0, k = 0; j < OSM_TABLE_SIZE; j++) { + c->osm_table[j].frequency = array[i + FREQ]; + c->osm_table[j].freq_data = array[i + FREQ_DATA]; + c->osm_table[j].override_data = array[i + PLL_OVERRIDES]; + c->osm_table[j].spare_data = array[i + SPARE_DATA]; + /* Voltage corners are 0 based in the OSM LUT */ + c->osm_table[j].virtual_corner = array[i + VIRTUAL_CORNER] - 1; + pr_debug("index=%d freq=%ld virtual_corner=%d freq_data=0x%x override_data=0x%x spare_data=0x%x\n", + j, c->osm_table[j].frequency, + c->osm_table[j].virtual_corner, + c->osm_table[j].freq_data, + c->osm_table[j].override_data, + c->osm_table[j].spare_data); + + data = (array[i + FREQ_DATA] & GENMASK(18, 16)) >> 16; + if (!last_entry && data == MAX_CORE_COUNT) { + fmax_temp[k] = array[i]; + k++; + } + + if (i < total_elems - NUM_FIELDS) + i += NUM_FIELDS; + else { + abs_fmax = array[i]; + last_entry = true; + } + } + + fmax_temp[k++] = abs_fmax; + clk->fmax = devm_kzalloc(&pdev->dev, k * sizeof(unsigned long), + GFP_KERNEL); + if (!clk->fmax) { + rc = -ENOMEM; + goto exit; + } + + for (i = 0; i < k; i++) + clk->fmax[i] = fmax_temp[i]; + + clk->num_fmax = k; +exit: + devm_kfree(&pdev->dev, fmax_temp); + devm_kfree(&pdev->dev, array); + return rc; +} + +static int clk_osm_parse_dt_configs(struct platform_device *pdev) +{ + struct device_node *of = pdev->dev.of_node; + u32 *array; + int i, rc = 0; + + array = devm_kzalloc(&pdev->dev, MAX_CLUSTER_CNT * sizeof(u32), + GFP_KERNEL); + if (!array) + return -ENOMEM; + + rc = of_property_read_u32_array(of, "qcom,l-val-base", + array, MAX_CLUSTER_CNT); + if (rc) { + dev_err(&pdev->dev, "unable to find qcom,l-val-base property, rc=%d\n", + rc); + return -EINVAL; + } + + pwrcl_clk.l_val_base = array[pwrcl_clk.cluster_num]; + perfcl_clk.l_val_base = array[perfcl_clk.cluster_num]; + + rc = of_property_read_u32_array(of, "qcom,apcs-itm-present", + array, MAX_CLUSTER_CNT); + if (rc) { + dev_err(&pdev->dev, "unable to find qcom,apcs-itm-present property, rc=%d\n", + rc); + return -EINVAL; + } + + pwrcl_clk.apcs_itm_present = array[pwrcl_clk.cluster_num]; + perfcl_clk.apcs_itm_present = array[perfcl_clk.cluster_num]; + + rc = of_property_read_u32_array(of, "qcom,apcs-cfg-rcgr", + array, MAX_CLUSTER_CNT); + if (rc) { + dev_err(&pdev->dev, "unable to find qcom,apcs-cfg-rcgr property, rc=%d\n", + rc); + return -EINVAL; + } + + pwrcl_clk.apcs_cfg_rcgr = array[pwrcl_clk.cluster_num]; + perfcl_clk.apcs_cfg_rcgr = array[perfcl_clk.cluster_num]; + + rc = of_property_read_u32_array(of, "qcom,apcs-cmd-rcgr", + array, MAX_CLUSTER_CNT); + if (rc) { + dev_err(&pdev->dev, "unable to find qcom,apcs-cmd-rcgr property, rc=%d\n", + rc); + return -EINVAL; + } + + pwrcl_clk.apcs_cmd_rcgr = array[pwrcl_clk.cluster_num]; + perfcl_clk.apcs_cmd_rcgr = array[perfcl_clk.cluster_num]; + + rc = of_property_read_u32_array(of, "qcom,apcs-pll-user-ctl", + array, MAX_CLUSTER_CNT); + if (rc) { + dev_err(&pdev->dev, "unable to find qcom,apcs-pll-user-ctl property, rc=%d\n", + rc); + return -EINVAL; + } + + pwrcl_clk.apcs_pll_user_ctl = array[pwrcl_clk.cluster_num]; + perfcl_clk.apcs_pll_user_ctl = array[perfcl_clk.cluster_num]; + + rc = of_property_read_u32_array(of, "qcom,apm-mode-ctl", + array, MAX_CLUSTER_CNT); + if (rc) { + dev_err(&pdev->dev, "unable to find qcom,apm-mode-ctl property, rc=%d\n", + rc); + return -EINVAL; + } + + pwrcl_clk.apm_mode_ctl = array[pwrcl_clk.cluster_num]; + perfcl_clk.apm_mode_ctl = array[perfcl_clk.cluster_num]; + + rc = of_property_read_u32_array(of, "qcom,apm-ctrl-status", + array, MAX_CLUSTER_CNT); + if (rc) { + dev_err(&pdev->dev, "unable to find qcom,apm-ctrl-status property, rc=%d\n", + rc); + return -EINVAL; + } + + pwrcl_clk.apm_ctrl_status = array[pwrcl_clk.cluster_num]; + perfcl_clk.apm_ctrl_status = array[perfcl_clk.cluster_num]; + + for (i = 0; i < LLM_SW_OVERRIDE_CNT; i++) + of_property_read_u32_index(of, "qcom,llm-sw-overr", + pwrcl_clk.cluster_num * + LLM_SW_OVERRIDE_CNT + i, + &pwrcl_clk.llm_sw_overr[i]); + + for (i = 0; i < LLM_SW_OVERRIDE_CNT; i++) + of_property_read_u32_index(of, "qcom,llm-sw-overr", + perfcl_clk.cluster_num * + LLM_SW_OVERRIDE_CNT + i, + &perfcl_clk.llm_sw_overr[i]); + + if (pwrcl_clk.acd_init || perfcl_clk.acd_init) { + rc = of_property_read_u32_array(of, "qcom,acdtd-val", + array, MAX_CLUSTER_CNT); + if (rc) { + dev_err(&pdev->dev, "unable to find qcom,acdtd-val property, rc=%d\n", + rc); + return -EINVAL; + } + + pwrcl_clk.acd_td = array[pwrcl_clk.cluster_num]; + perfcl_clk.acd_td = array[perfcl_clk.cluster_num]; + + rc = of_property_read_u32_array(of, "qcom,acdcr-val", + array, MAX_CLUSTER_CNT); + if (rc) { + dev_err(&pdev->dev, "unable to find qcom,acdcr-val property, rc=%d\n", + rc); + return -EINVAL; + } + + pwrcl_clk.acd_cr = array[pwrcl_clk.cluster_num]; + perfcl_clk.acd_cr = array[perfcl_clk.cluster_num]; + + rc = of_property_read_u32_array(of, "qcom,acdsscr-val", + array, MAX_CLUSTER_CNT); + if (rc) { + dev_err(&pdev->dev, "unable to find qcom,acdsscr-val property, rc=%d\n", + rc); + return -EINVAL; + } + + pwrcl_clk.acd_sscr = array[pwrcl_clk.cluster_num]; + perfcl_clk.acd_sscr = array[perfcl_clk.cluster_num]; + + rc = of_property_read_u32_array(of, "qcom,acdextint0-val", + array, MAX_CLUSTER_CNT); + if (rc) { + dev_err(&pdev->dev, "unable to find qcom,acdextint0-val property, rc=%d\n", + rc); + return -EINVAL; + } + + pwrcl_clk.acd_extint0_cfg = array[pwrcl_clk.cluster_num]; + perfcl_clk.acd_extint0_cfg = array[perfcl_clk.cluster_num]; + + rc = of_property_read_u32_array(of, "qcom,acdextint1-val", + array, MAX_CLUSTER_CNT); + if (rc) { + dev_err(&pdev->dev, "unable to find qcom,acdextint1-val property, rc=%d\n", + rc); + return -EINVAL; + } + + pwrcl_clk.acd_extint1_cfg = array[pwrcl_clk.cluster_num]; + perfcl_clk.acd_extint1_cfg = array[perfcl_clk.cluster_num]; + + rc = of_property_read_u32_array(of, "qcom,acdautoxfer-val", + array, MAX_CLUSTER_CNT); + if (rc) { + dev_err(&pdev->dev, "unable to find qcom,acdautoxfer-val property, rc=%d\n", + rc); + return -EINVAL; + } + + pwrcl_clk.acd_autoxfer_ctl = array[pwrcl_clk.cluster_num]; + perfcl_clk.acd_autoxfer_ctl = array[perfcl_clk.cluster_num]; + } + + rc = of_property_read_u32(of, "qcom,xo-clk-rate", + &pwrcl_clk.xo_clk_rate); + if (rc) { + dev_err(&pdev->dev, "unable to find qcom,xo-clk-rate property, rc=%d\n", + rc); + return -EINVAL; + } + + perfcl_clk.xo_clk_rate = pwrcl_clk.xo_clk_rate; + + rc = of_property_read_u32(of, "qcom,osm-clk-rate", + &pwrcl_clk.osm_clk_rate); + if (rc) { + dev_err(&pdev->dev, "unable to find qcom,osm-clk-rate property, rc=%d\n", + rc); + return -EINVAL; + } + perfcl_clk.osm_clk_rate = pwrcl_clk.osm_clk_rate; + + rc = of_property_read_u32(of, "qcom,cc-reads", + &pwrcl_clk.cycle_counter_reads); + if (rc) { + dev_err(&pdev->dev, "unable to find qcom,cc-reads property, rc=%d\n", + rc); + return -EINVAL; + } + perfcl_clk.cycle_counter_reads = pwrcl_clk.cycle_counter_reads; + + rc = of_property_read_u32(of, "qcom,cc-delay", + &pwrcl_clk.cycle_counter_delay); + if (rc) + dev_dbg(&pdev->dev, "no delays between cycle counter reads\n"); + else + perfcl_clk.cycle_counter_delay = pwrcl_clk.cycle_counter_delay; + + rc = of_property_read_u32(of, "qcom,cc-factor", + &pwrcl_clk.cycle_counter_factor); + if (rc) + dev_dbg(&pdev->dev, "no factor specified for cycle counter estimation\n"); + else + perfcl_clk.cycle_counter_factor = + pwrcl_clk.cycle_counter_factor; + + perfcl_clk.red_fsm_en = pwrcl_clk.red_fsm_en = + of_property_read_bool(of, "qcom,red-fsm-en"); + + perfcl_clk.boost_fsm_en = pwrcl_clk.boost_fsm_en = + of_property_read_bool(of, "qcom,boost-fsm-en"); + + perfcl_clk.safe_fsm_en = pwrcl_clk.safe_fsm_en = + of_property_read_bool(of, "qcom,safe-fsm-en"); + + perfcl_clk.ps_fsm_en = pwrcl_clk.ps_fsm_en = + of_property_read_bool(of, "qcom,ps-fsm-en"); + + perfcl_clk.droop_fsm_en = pwrcl_clk.droop_fsm_en = + of_property_read_bool(of, "qcom,droop-fsm-en"); + + perfcl_clk.wfx_fsm_en = pwrcl_clk.wfx_fsm_en = + of_property_read_bool(of, "qcom,wfx-fsm-en"); + + perfcl_clk.pc_fsm_en = pwrcl_clk.pc_fsm_en = + of_property_read_bool(of, "qcom,pc-fsm-en"); + + devm_kfree(&pdev->dev, array); + + perfcl_clk.secure_init = pwrcl_clk.secure_init = + of_property_read_bool(pdev->dev.of_node, "qcom,osm-no-tz"); + + if (!pwrcl_clk.secure_init) + return rc; + + rc = of_property_read_u32_array(of, "qcom,pwrcl-apcs-mem-acc-cfg", + pwrcl_clk.apcs_mem_acc_cfg, + MAX_MEM_ACC_VAL_PER_LEVEL); + if (rc) { + dev_err(&pdev->dev, "unable to find qcom,pwrcl-apcs-mem-acc-cfg property, rc=%d\n", + rc); + return -EINVAL; + } + + of_property_read_u32_array(of, "qcom,perfcl-apcs-mem-acc-cfg", + perfcl_clk.apcs_mem_acc_cfg, + MAX_MEM_ACC_VAL_PER_LEVEL); + if (rc) { + dev_err(&pdev->dev, "unable to find qcom,perfcl-apcs-mem-acc-cfg property, rc=%d\n", + rc); + return -EINVAL; + } + + rc = of_property_read_u32_array(of, "qcom,pwrcl-apcs-mem-acc-val", + pwrcl_clk.apcs_mem_acc_val, + MAX_MEM_ACC_VALUES); + if (rc) { + dev_err(&pdev->dev, "unable to find qcom,pwrcl-apcs-mem-acc-val property, rc=%d\n", + rc); + return -EINVAL; + } + + rc = of_property_read_u32_array(of, "qcom,perfcl-apcs-mem-acc-val", + perfcl_clk.apcs_mem_acc_val, + MAX_MEM_ACC_VALUES); + if (rc) { + dev_err(&pdev->dev, "unable to find qcom,perfcl-apcs-mem-acc-val property, rc=%d\n", + rc); + return -EINVAL; + } + + return rc; +} + +static int clk_osm_resources_init(struct platform_device *pdev) +{ + struct device_node *node; + struct resource *res; + struct clk *c; + unsigned long pbase; + int i, rc = 0; + void *vbase; + + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "osm"); + if (!res) { + dev_err(&pdev->dev, + "Unable to get platform resource for osm"); + return -ENOMEM; + } + + pwrcl_clk.pbases[OSM_BASE] = (unsigned long)res->start; + pwrcl_clk.vbases[OSM_BASE] = devm_ioremap(&pdev->dev, res->start, + resource_size(res)); + if (!pwrcl_clk.vbases[OSM_BASE]) { + dev_err(&pdev->dev, "Unable to map in osm base\n"); + return -ENOMEM; + } + + perfcl_clk.pbases[OSM_BASE] = pwrcl_clk.pbases[OSM_BASE] + + perfcl_clk.cluster_num * OSM_CORE_TABLE_SIZE; + perfcl_clk.vbases[OSM_BASE] = pwrcl_clk.vbases[OSM_BASE] + + perfcl_clk.cluster_num * OSM_CORE_TABLE_SIZE; + + for (i = 0; i < MAX_CLUSTER_CNT; i++) { + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, + i == pwrcl_clk.cluster_num ? + "pwrcl_pll" : "perfcl_pll"); + if (!res) { + dev_err(&pdev->dev, + "Unable to get platform resource\n"); + return -ENOMEM; + } + pbase = (unsigned long)res->start; + vbase = devm_ioremap(&pdev->dev, res->start, + resource_size(res)); + + if (!vbase) { + dev_err(&pdev->dev, "Unable to map in base\n"); + return -ENOMEM; + } + + if (i == pwrcl_clk.cluster_num) { + pwrcl_clk.pbases[PLL_BASE] = pbase; + pwrcl_clk.vbases[PLL_BASE] = vbase; + } else { + perfcl_clk.pbases[PLL_BASE] = pbase; + perfcl_clk.vbases[PLL_BASE] = vbase; + } + } + + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "debug"); + if (!res) { + dev_err(&pdev->dev, "Failed to get debug mux base\n"); + return -EINVAL; + } + + debug_base = devm_ioremap(&pdev->dev, res->start, + resource_size(res)); + if (!debug_base) { + dev_err(&pdev->dev, "Unable to map in debug mux base\n"); + return -ENOMEM; + } + + clk_ops_cpu_dbg_mux = clk_ops_gen_mux; + clk_ops_cpu_dbg_mux.get_rate = cpu_dbg_mux_get_rate; + + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "apcs_common"); + if (!res) { + dev_err(&pdev->dev, "Failed to get apcs common base\n"); + return -EINVAL; + } + + virt_base = devm_ioremap(&pdev->dev, res->start, resource_size(res)); + if (!virt_base) { + dev_err(&pdev->dev, "Failed to map apcs common registers\n"); + return -ENOMEM; + } + + /* efuse speed bin fuses are optional */ + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, + "pwrcl_efuse"); + if (res) { + pbase = (unsigned long)res->start; + vbase = devm_ioremap(&pdev->dev, res->start, + resource_size(res)); + if (!vbase) { + dev_err(&pdev->dev, "Unable to map in pwrcl_efuse base\n"); + return -ENOMEM; + } + pwrcl_clk.pbases[EFUSE_BASE] = pbase; + pwrcl_clk.vbases[EFUSE_BASE] = vbase; + } + + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, + "perfcl_efuse"); + if (res) { + pbase = (unsigned long)res->start; + vbase = devm_ioremap(&pdev->dev, res->start, + resource_size(res)); + if (!vbase) { + dev_err(&pdev->dev, "Unable to map in perfcl_efuse base\n"); + return -ENOMEM; + } + perfcl_clk.pbases[EFUSE_BASE] = pbase; + perfcl_clk.vbases[EFUSE_BASE] = vbase; + } + + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, + "pwrcl_acd"); + if (res) { + pbase = (unsigned long)res->start; + vbase = devm_ioremap(&pdev->dev, res->start, + resource_size(res)); + if (!vbase) { + dev_err(&pdev->dev, "Unable to map in pwrcl_acd base\n"); + return -ENOMEM; + } + pwrcl_clk.pbases[ACD_BASE] = pbase; + pwrcl_clk.acd_debugfs_addr_size = resource_size(res); + pwrcl_clk.vbases[ACD_BASE] = vbase; + pwrcl_clk.acd_init = true; + } else { + pwrcl_clk.acd_init = false; + } + + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, + "perfcl_acd"); + if (res) { + pbase = (unsigned long)res->start; + vbase = devm_ioremap(&pdev->dev, res->start, + resource_size(res)); + if (!vbase) { + dev_err(&pdev->dev, "Unable to map in perfcl_acd base\n"); + return -ENOMEM; + } + perfcl_clk.pbases[ACD_BASE] = pbase; + perfcl_clk.acd_debugfs_addr_size = resource_size(res); + perfcl_clk.vbases[ACD_BASE] = vbase; + perfcl_clk.acd_init = true; + } else { + perfcl_clk.acd_init = false; + } + + pwrcl_clk.debug_regs[0] = devm_ioremap(&pdev->dev, + pwrcl_clk.pbases[OSM_BASE] + + clk_panic_reg_offsets[0], + 0x4); + if (!pwrcl_clk.debug_regs[0]) { + dev_err(&pdev->dev, "Failed to map %s debug register\n", + clk_panic_reg_names[0]); + return -ENOMEM; + } + + pwrcl_clk.debug_regs[1] = devm_ioremap(&pdev->dev, + pwrcl_clk.pbases[OSM_BASE] + + clk_panic_reg_offsets[1], + 0x4); + if (!pwrcl_clk.debug_regs[1]) { + dev_err(&pdev->dev, "Failed to map %s debug register\n", + clk_panic_reg_names[1]); + return -ENOMEM; + } + + pwrcl_clk.debug_regs[2] = devm_ioremap(&pdev->dev, + pwrcl_clk.apm_ctrl_status, + 0x4); + if (!pwrcl_clk.debug_regs[2]) { + dev_err(&pdev->dev, "Failed to map %s debug register\n", + clk_panic_reg_names[2]); + return -ENOMEM; + } + + perfcl_clk.debug_regs[0] = devm_ioremap(&pdev->dev, + perfcl_clk.pbases[OSM_BASE] + + clk_panic_reg_offsets[0], + 0x4); + if (!perfcl_clk.debug_regs[0]) { + dev_err(&pdev->dev, "Failed to map %s debug register\n", + clk_panic_reg_names[0]); + return -ENOMEM; + } + + perfcl_clk.debug_regs[1] = devm_ioremap(&pdev->dev, + perfcl_clk.pbases[OSM_BASE] + + clk_panic_reg_offsets[1], + 0x4); + if (!perfcl_clk.debug_regs[1]) { + dev_err(&pdev->dev, "Failed to map %s debug register\n", + clk_panic_reg_names[1]); + return -ENOMEM; + } + + perfcl_clk.debug_regs[2] = devm_ioremap(&pdev->dev, + perfcl_clk.apm_ctrl_status, + 0x4); + if (!perfcl_clk.debug_regs[2]) { + dev_err(&pdev->dev, "Failed to map %s debug register\n", + clk_panic_reg_names[2]); + return -ENOMEM; + } + + vdd_pwrcl = devm_regulator_get(&pdev->dev, "vdd-pwrcl"); + if (IS_ERR(vdd_pwrcl)) { + rc = PTR_ERR(vdd_pwrcl); + if (rc != -EPROBE_DEFER) + dev_err(&pdev->dev, "Unable to get the pwrcl vreg, rc=%d\n", + rc); + return rc; + } + + vdd_perfcl = devm_regulator_get(&pdev->dev, "vdd-perfcl"); + if (IS_ERR(vdd_perfcl)) { + rc = PTR_ERR(vdd_perfcl); + if (rc != -EPROBE_DEFER) + dev_err(&pdev->dev, "Unable to get the perfcl vreg, rc=%d\n", + rc); + return rc; + } + + pwrcl_clk.vdd_reg = vdd_pwrcl; + perfcl_clk.vdd_reg = vdd_perfcl; + + node = of_parse_phandle(pdev->dev.of_node, "vdd-pwrcl-supply", 0); + if (!node) { + pr_err("Unable to find vdd-pwrcl-supply\n"); + return -EINVAL; + } + + pwrcl_clk.vdd_dev = of_find_device_by_node(node->parent->parent); + if (!pwrcl_clk.vdd_dev) { + pr_err("Unable to find device for vdd-pwrcl-supply node\n"); + return -EINVAL; + } + + node = of_parse_phandle(pdev->dev.of_node, + "vdd-perfcl-supply", 0); + if (!node) { + pr_err("Unable to find vdd-perfcl-supply\n"); + return -EINVAL; + } + + perfcl_clk.vdd_dev = of_find_device_by_node(node->parent->parent); + if (!perfcl_clk.vdd_dev) { + pr_err("Unable to find device for vdd-perfcl-supply\n"); + return -EINVAL; + } + + c = devm_clk_get(&pdev->dev, "aux_clk"); + if (IS_ERR(c)) { + rc = PTR_ERR(c); + if (rc != -EPROBE_DEFER) + dev_err(&pdev->dev, "Unable to get aux_clk, rc=%d\n", + rc); + return rc; + } + sys_apcsaux_clk_gcc.c.parent = c; + + c = devm_clk_get(&pdev->dev, "xo_ao"); + if (IS_ERR(c)) { + rc = PTR_ERR(c); + if (rc != -EPROBE_DEFER) + dev_err(&pdev->dev, "Unable to get xo_ao clk, rc=%d\n", + rc); + return rc; + } + xo_ao.c.parent = c; + + return 0; +} + +static void clk_osm_setup_cluster_pll(struct clk_osm *c) +{ + writel_relaxed(0x0, c->vbases[PLL_BASE] + PLL_MODE); + writel_relaxed(0x20, c->vbases[PLL_BASE] + PLL_L_VAL); + writel_relaxed(0x01000008, c->vbases[PLL_BASE] + + PLL_USER_CTRL); + writel_relaxed(0x20004AA8, c->vbases[PLL_BASE] + + PLL_CONFIG_CTL_LO); + writel_relaxed(0x2, c->vbases[PLL_BASE] + + PLL_MODE); + + /* Ensure writes complete before delaying */ + clk_osm_mb(c, PLL_BASE); + + udelay(PLL_WAIT_LOCK_TIME_US); + + writel_relaxed(0x6, c->vbases[PLL_BASE] + PLL_MODE); + + /* Ensure write completes before delaying */ + clk_osm_mb(c, PLL_BASE); + + usleep_range(50, 75); + + writel_relaxed(0x7, c->vbases[PLL_BASE] + PLL_MODE); +} + +static int clk_osm_setup_hw_table(struct clk_osm *c) +{ + struct osm_entry *entry = c->osm_table; + int i; + u32 freq_val = 0, volt_val = 0, override_val = 0, spare_val = 0; + u32 table_entry_offset = 0, last_spare = 0, last_virtual_corner = 0; + + for (i = 0; i < OSM_TABLE_SIZE; i++) { + if (i < c->num_entries) { + freq_val = entry[i].freq_data; + volt_val = BVAL(21, 16, entry[i].virtual_corner) + | BVAL(11, 0, entry[i].open_loop_volt); + override_val = entry[i].override_data; + spare_val = entry[i].spare_data; + + if (last_virtual_corner && last_virtual_corner == + entry[i].virtual_corner && last_spare != + entry[i].spare_data) { + pr_err("invalid LUT entry at row=%d virtual_corner=%d, spare_data=%d\n", + i, entry[i].virtual_corner, + entry[i].spare_data); + return -EINVAL; + } + last_virtual_corner = entry[i].virtual_corner; + last_spare = entry[i].spare_data; + } + + table_entry_offset = i * OSM_REG_SIZE; + clk_osm_write_reg(c, i, INDEX_REG + table_entry_offset); + clk_osm_write_reg(c, freq_val, FREQ_REG + table_entry_offset); + clk_osm_write_reg(c, volt_val, VOLT_REG + table_entry_offset); + clk_osm_write_reg(c, override_val, OVERRIDE_REG + + table_entry_offset); + clk_osm_write_reg(c, spare_val, SPARE_REG + + table_entry_offset); + } + + /* Make sure all writes go through */ + clk_osm_mb(c, OSM_BASE); + + return 0; +} + +static int clk_osm_resolve_open_loop_voltages(struct clk_osm *c) +{ + struct regulator *regulator = c->vdd_reg; + u32 vc, mv; + int i; + + for (i = 0; i < OSM_TABLE_SIZE; i++) { + vc = c->osm_table[i].virtual_corner + 1; + /* Voltage is in uv. Convert to mv */ + mv = regulator_list_corner_voltage(regulator, vc) / 1000; + c->osm_table[i].open_loop_volt = mv; + } + + return 0; +} + +static int clk_osm_resolve_crossover_corners(struct clk_osm *c, + struct platform_device *pdev, + const char *mem_acc_prop) +{ + struct regulator *regulator = c->vdd_reg; + int count, vc, i, apm_threshold; + int mem_acc_threshold = 0; + int rc = 0; + u32 corner_volt; + + rc = of_property_read_u32(pdev->dev.of_node, + "qcom,apm-threshold-voltage", + &apm_threshold); + if (rc) { + pr_info("qcom,apm-threshold-voltage property not specified\n"); + return rc; + } + + if (mem_acc_prop) + of_property_read_u32(pdev->dev.of_node, mem_acc_prop, + &mem_acc_threshold); + + /* Determine crossover virtual corner */ + count = regulator_count_voltages(regulator); + if (count < 0) { + pr_err("Failed to get the number of virtual corners supported\n"); + return count; + } + + /* + * CPRh corners (in hardware) are ordered: + * 0 - n-1 - for n functional corners + * APM crossover - required for OSM + * [MEM ACC crossover] - optional + * + * 'count' corresponds to the total number of corners including n + * functional corners, the APM crossover corner, and potentially the + * MEM ACC cross over corner. + */ + if (mem_acc_threshold) { + c->apm_crossover_vc = count - 2; + c->mem_acc_crossover_vc = count - 1; + } else { + c->apm_crossover_vc = count - 1; + } + + /* Determine APM threshold virtual corner */ + for (i = 0; i < OSM_TABLE_SIZE; i++) { + vc = c->osm_table[i].virtual_corner + 1; + corner_volt = regulator_list_corner_voltage(regulator, vc); + + if (corner_volt >= apm_threshold) { + c->apm_threshold_vc = c->osm_table[i].virtual_corner; + /* + * Handle case where VC 0 has open-loop + * greater than or equal to APM threshold voltage. + */ + c->apm_threshold_pre_vc = c->apm_threshold_vc ? + c->apm_threshold_vc - 1 : OSM_SEQ_MINUS_ONE; + break; + } + } + + /* + * This assumes the OSM table uses corners + * 0 to MAX_VIRTUAL_CORNER - 1. + */ + if (!c->apm_threshold_vc && + c->apm_threshold_pre_vc != OSM_SEQ_MINUS_ONE) { + c->apm_threshold_vc = MAX_VIRTUAL_CORNER; + c->apm_threshold_pre_vc = c->apm_threshold_vc - 1; + } + + /* Determine MEM ACC threshold virtual corner */ + if (mem_acc_threshold) { + for (i = 0; i < OSM_TABLE_SIZE; i++) { + vc = c->osm_table[i].virtual_corner + 1; + corner_volt + = regulator_list_corner_voltage(regulator, vc); + + if (corner_volt >= mem_acc_threshold) { + c->mem_acc_threshold_vc + = c->osm_table[i].virtual_corner; + /* + * Handle case where VC 0 has open-loop + * greater than or equal to MEM-ACC threshold + * voltage. + */ + c->mem_acc_threshold_pre_vc = + c->mem_acc_threshold_vc ? + c->mem_acc_threshold_vc - 1 : + OSM_SEQ_MINUS_ONE; + break; + } + } + + /* + * This assumes the OSM table uses corners + * 0 to MAX_VIRTUAL_CORNER - 1. + */ + if (!c->mem_acc_threshold_vc && c->mem_acc_threshold_pre_vc + != OSM_SEQ_MINUS_ONE) { + c->mem_acc_threshold_vc = + MAX_VIRTUAL_CORNER; + c->mem_acc_threshold_pre_vc = + c->mem_acc_threshold_vc - 1; + } + } + + return 0; +} + +static int clk_osm_set_cc_policy(struct platform_device *pdev) +{ + int rc = 0, val; + u32 *array; + struct device_node *of = pdev->dev.of_node; + + array = devm_kzalloc(&pdev->dev, MAX_CLUSTER_CNT * sizeof(u32), + GFP_KERNEL); + if (!array) + return -ENOMEM; + + rc = of_property_read_u32_array(of, "qcom,up-timer", array, + MAX_CLUSTER_CNT); + if (rc) { + dev_dbg(&pdev->dev, "No up timer value, rc=%d\n", + rc); + } else { + val = clk_osm_read_reg(&pwrcl_clk, SPM_CC_HYSTERESIS) + | BVAL(31, 16, clk_osm_count_ns(&pwrcl_clk, + array[pwrcl_clk.cluster_num])); + clk_osm_write_reg(&pwrcl_clk, val, SPM_CC_HYSTERESIS); + val = clk_osm_read_reg(&perfcl_clk, SPM_CC_HYSTERESIS) + | BVAL(31, 16, clk_osm_count_ns(&perfcl_clk, + array[perfcl_clk.cluster_num])); + clk_osm_write_reg(&perfcl_clk, val, SPM_CC_HYSTERESIS); + } + + rc = of_property_read_u32_array(of, "qcom,down-timer", + array, MAX_CLUSTER_CNT); + if (rc) { + dev_dbg(&pdev->dev, "No down timer value, rc=%d\n", rc); + } else { + val = clk_osm_read_reg(&pwrcl_clk, SPM_CC_HYSTERESIS) + | BVAL(15, 0, clk_osm_count_ns(&pwrcl_clk, + array[pwrcl_clk.cluster_num])); + clk_osm_write_reg(&pwrcl_clk, val, SPM_CC_HYSTERESIS); + val = clk_osm_read_reg(&perfcl_clk, SPM_CC_HYSTERESIS) + | BVAL(15, 0, clk_osm_count_ns(&perfcl_clk, + array[perfcl_clk.cluster_num])); + clk_osm_write_reg(&perfcl_clk, val, SPM_CC_HYSTERESIS); + } + + /* OSM index override for cluster PC */ + rc = of_property_read_u32_array(of, "qcom,pc-override-index", + array, MAX_CLUSTER_CNT); + if (rc) { + dev_dbg(&pdev->dev, "No PC override index value, rc=%d\n", + rc); + clk_osm_write_reg(&pwrcl_clk, 0, CC_ZERO_BEHAV_CTRL); + clk_osm_write_reg(&perfcl_clk, 0, CC_ZERO_BEHAV_CTRL); + } else { + val = BVAL(6, 1, array[pwrcl_clk.cluster_num]) + | ENABLE_OVERRIDE; + clk_osm_write_reg(&pwrcl_clk, val, CC_ZERO_BEHAV_CTRL); + val = BVAL(6, 1, array[perfcl_clk.cluster_num]) + | ENABLE_OVERRIDE; + clk_osm_write_reg(&perfcl_clk, val, CC_ZERO_BEHAV_CTRL); + } + + /* Wait for the writes to complete */ + clk_osm_mb(&perfcl_clk, OSM_BASE); + + rc = of_property_read_bool(pdev->dev.of_node, "qcom,set-ret-inactive"); + if (rc) { + dev_dbg(&pdev->dev, "Treat cores in retention as active\n"); + val = 0; + } else { + dev_dbg(&pdev->dev, "Treat cores in retention as inactive\n"); + val = 1; + } + + clk_osm_write_reg(&pwrcl_clk, val, SPM_CORE_RET_MAPPING); + clk_osm_write_reg(&perfcl_clk, val, SPM_CORE_RET_MAPPING); + + rc = of_property_read_bool(pdev->dev.of_node, "qcom,disable-cc-dvcs"); + if (rc) { + dev_dbg(&pdev->dev, "Disabling CC based DCVS\n"); + val = 1; + } else + val = 0; + + clk_osm_write_reg(&pwrcl_clk, val, SPM_CC_DCVS_DISABLE); + clk_osm_write_reg(&perfcl_clk, val, SPM_CC_DCVS_DISABLE); + + /* Wait for the writes to complete */ + clk_osm_mb(&perfcl_clk, OSM_BASE); + + devm_kfree(&pdev->dev, array); + return 0; +} + +static void clk_osm_setup_itm_to_osm_handoff(void) +{ + /* Program address of ITM_PRESENT of CPUSS */ + clk_osm_write_reg(&pwrcl_clk, pwrcl_clk.apcs_itm_present, + SEQ_REG(37)); + clk_osm_write_reg(&pwrcl_clk, 0, SEQ_REG(38)); + clk_osm_write_reg(&perfcl_clk, perfcl_clk.apcs_itm_present, + SEQ_REG(37)); + clk_osm_write_reg(&perfcl_clk, 0, SEQ_REG(38)); + + /* + * Program data to write to ITM_PRESENT assuming ITM for other domain + * is enabled and the ITM for this domain is to be disabled. + */ + clk_osm_write_reg(&pwrcl_clk, ITM_CL0_DISABLE_CL1_ENABLED, + SEQ_REG(39)); + clk_osm_write_reg(&perfcl_clk, ITM_CL0_ENABLED_CL1_DISABLE, + SEQ_REG(39)); +} + +static int clk_osm_set_llm_freq_policy(struct platform_device *pdev) +{ + struct device_node *of = pdev->dev.of_node; + u32 *array; + int rc = 0, val, regval; + + array = devm_kzalloc(&pdev->dev, MAX_CLUSTER_CNT * sizeof(u32), + GFP_KERNEL); + if (!array) + return -ENOMEM; + + /* + * Setup Timer to control how long OSM should wait before performing + * DCVS when a LLM up frequency request is received. + * Time is specified in us. + */ + rc = of_property_read_u32_array(of, "qcom,llm-freq-up-timer", array, + MAX_CLUSTER_CNT); + if (rc) { + dev_dbg(&pdev->dev, "Unable to get CC up timer value: %d\n", + rc); + } else { + val = clk_osm_read_reg(&pwrcl_clk, LLM_FREQ_VOTE_HYSTERESIS) + | BVAL(31, 16, clk_osm_count_ns(&pwrcl_clk, + array[pwrcl_clk.cluster_num])); + clk_osm_write_reg(&pwrcl_clk, val, LLM_FREQ_VOTE_HYSTERESIS); + val = clk_osm_read_reg(&perfcl_clk, LLM_FREQ_VOTE_HYSTERESIS) + | BVAL(31, 16, clk_osm_count_ns(&perfcl_clk, + array[perfcl_clk.cluster_num])); + clk_osm_write_reg(&perfcl_clk, val, LLM_FREQ_VOTE_HYSTERESIS); + } + + /* + * Setup Timer to control how long OSM should wait before performing + * DCVS when a LLM down frequency request is received. + * Time is specified in us. + */ + rc = of_property_read_u32_array(of, "qcom,llm-freq-down-timer", + array, MAX_CLUSTER_CNT); + if (rc) { + dev_dbg(&pdev->dev, "No LLM Frequency down timer value: %d\n", + rc); + } else { + val = clk_osm_read_reg(&pwrcl_clk, LLM_FREQ_VOTE_HYSTERESIS) + | BVAL(15, 0, clk_osm_count_ns(&pwrcl_clk, + array[pwrcl_clk.cluster_num])); + clk_osm_write_reg(&pwrcl_clk, val, LLM_FREQ_VOTE_HYSTERESIS); + val = clk_osm_read_reg(&perfcl_clk, LLM_FREQ_VOTE_HYSTERESIS) + | BVAL(15, 0, clk_osm_count_ns(&perfcl_clk, + array[perfcl_clk.cluster_num])); + clk_osm_write_reg(&perfcl_clk, val, LLM_FREQ_VOTE_HYSTERESIS); + } + + /* Enable or disable honoring of LLM frequency requests */ + rc = of_property_read_bool(pdev->dev.of_node, + "qcom,enable-llm-freq-vote"); + if (rc) { + dev_dbg(&pdev->dev, "Honoring LLM Frequency requests\n"); + val = 0; + } else + val = 1; + + /* Enable or disable LLM FREQ DVCS */ + regval = val | clk_osm_read_reg(&pwrcl_clk, LLM_INTF_DCVS_DISABLE); + clk_osm_write_reg(&pwrcl_clk, regval, LLM_INTF_DCVS_DISABLE); + regval = val | clk_osm_read_reg(&perfcl_clk, LLM_INTF_DCVS_DISABLE); + clk_osm_write_reg(&perfcl_clk, regval, LLM_INTF_DCVS_DISABLE); + + /* Wait for the write to complete */ + clk_osm_mb(&perfcl_clk, OSM_BASE); + + devm_kfree(&pdev->dev, array); + return 0; +} + +static int clk_osm_set_llm_volt_policy(struct platform_device *pdev) +{ + struct device_node *of = pdev->dev.of_node; + u32 *array; + int rc = 0, val, regval; + + array = devm_kzalloc(&pdev->dev, MAX_CLUSTER_CNT * sizeof(u32), + GFP_KERNEL); + if (!array) + return -ENOMEM; + + /* + * Setup Timer to control how long OSM should wait before performing + * DCVS when a LLM up voltage request is received. + * Time is specified in us. + */ + rc = of_property_read_u32_array(of, "qcom,llm-volt-up-timer", + array, MAX_CLUSTER_CNT); + if (rc) { + dev_dbg(&pdev->dev, "No LLM voltage up timer value, rc=%d\n", + rc); + } else { + val = clk_osm_read_reg(&pwrcl_clk, LLM_VOLT_VOTE_HYSTERESIS) + | BVAL(31, 16, clk_osm_count_ns(&pwrcl_clk, + array[pwrcl_clk.cluster_num])); + clk_osm_write_reg(&pwrcl_clk, val, LLM_VOLT_VOTE_HYSTERESIS); + val = clk_osm_read_reg(&perfcl_clk, LLM_VOLT_VOTE_HYSTERESIS) + | BVAL(31, 16, clk_osm_count_ns(&perfcl_clk, + array[perfcl_clk.cluster_num])); + clk_osm_write_reg(&perfcl_clk, val, LLM_VOLT_VOTE_HYSTERESIS); + } + + /* + * Setup Timer to control how long OSM should wait before performing + * DCVS when a LLM down voltage request is received. + * Time is specified in us. + */ + rc = of_property_read_u32_array(of, "qcom,llm-volt-down-timer", + array, MAX_CLUSTER_CNT); + if (rc) { + dev_dbg(&pdev->dev, "No LLM Voltage down timer value: %d\n", + rc); + } else { + val = clk_osm_read_reg(&pwrcl_clk, LLM_VOLT_VOTE_HYSTERESIS) + | BVAL(15, 0, clk_osm_count_ns(&pwrcl_clk, + array[pwrcl_clk.cluster_num])); + clk_osm_write_reg(&pwrcl_clk, val, LLM_VOLT_VOTE_HYSTERESIS); + val = clk_osm_read_reg(&perfcl_clk, LLM_VOLT_VOTE_HYSTERESIS) + | BVAL(15, 0, clk_osm_count_ns(&perfcl_clk, + array[perfcl_clk.cluster_num])); + clk_osm_write_reg(&perfcl_clk, val, LLM_VOLT_VOTE_HYSTERESIS); + } + + /* Enable or disable honoring of LLM Voltage requests */ + rc = of_property_read_bool(pdev->dev.of_node, + "qcom,enable-llm-volt-vote"); + if (rc) { + dev_dbg(&pdev->dev, "Honoring LLM Voltage requests\n"); + val = 0; + } else + val = BIT(1); + + /* Enable or disable LLM VOLT DVCS */ + regval = val | clk_osm_read_reg(&pwrcl_clk, LLM_INTF_DCVS_DISABLE); + clk_osm_write_reg(&pwrcl_clk, regval, LLM_INTF_DCVS_DISABLE); + regval = val | clk_osm_read_reg(&perfcl_clk, LLM_INTF_DCVS_DISABLE); + clk_osm_write_reg(&perfcl_clk, regval, LLM_INTF_DCVS_DISABLE); + + /* Wait for the writes to complete */ + clk_osm_mb(&perfcl_clk, OSM_BASE); + + devm_kfree(&pdev->dev, array); + return 0; +} + +static void clk_osm_program_apm_regs(struct clk_osm *c) +{ + /* + * Program address of the control register used to configure + * the Array Power Mux controller + */ + clk_osm_write_reg(c, c->apm_mode_ctl, SEQ_REG(2)); + + /* Program address of controller status register */ + clk_osm_write_reg(c, c->apm_ctrl_status, SEQ_REG(3)); + + /* Program mode value to switch APM from VDD_APCC to VDD_MX */ + clk_osm_write_reg(c, APM_MX_MODE, SEQ_REG(77)); + + /* Program value used to determine current APM power supply is VDD_MX */ + clk_osm_write_reg(c, APM_MX_MODE_VAL, SEQ_REG(78)); + + /* Program mask used to determine status of APM power supply switch */ + clk_osm_write_reg(c, APM_MODE_SWITCH_MASK, SEQ_REG(79)); + + /* Program mode value to switch APM from VDD_MX to VDD_APCC */ + clk_osm_write_reg(c, APM_APC_MODE, SEQ_REG(80)); + + /* + * Program value used to determine current APM power supply + * is VDD_APCC + */ + clk_osm_write_reg(c, APM_APC_MODE_VAL, SEQ_REG(81)); +} + +static void clk_osm_program_mem_acc_regs(struct clk_osm *c) +{ + struct osm_entry *table = c->osm_table; + int i, curr_level, j = 0; + int mem_acc_level_map[MAX_MEM_ACC_LEVELS] = {0, 0, 0}; + int threshold_vc[4]; + + curr_level = c->osm_table[0].spare_data; + for (i = 0; i < c->num_entries; i++) { + if (curr_level == MAX_MEM_ACC_LEVELS) + break; + + if (c->osm_table[i].spare_data != curr_level) { + mem_acc_level_map[j++] + = c->osm_table[i].virtual_corner - 1; + curr_level = c->osm_table[i].spare_data; + } + } + + if (c->secure_init) { + clk_osm_write_reg(c, MEM_ACC_SEQ_CONST(1), SEQ_REG(51)); + clk_osm_write_reg(c, MEM_ACC_SEQ_CONST(2), SEQ_REG(52)); + clk_osm_write_reg(c, MEM_ACC_SEQ_CONST(3), SEQ_REG(53)); + clk_osm_write_reg(c, MEM_ACC_SEQ_CONST(4), SEQ_REG(54)); + clk_osm_write_reg(c, MEM_ACC_APM_READ_MASK, SEQ_REG(59)); + clk_osm_write_reg(c, mem_acc_level_map[0], SEQ_REG(55)); + clk_osm_write_reg(c, mem_acc_level_map[0] + 1, SEQ_REG(56)); + clk_osm_write_reg(c, mem_acc_level_map[1], SEQ_REG(57)); + clk_osm_write_reg(c, mem_acc_level_map[1] + 1, SEQ_REG(58)); + clk_osm_write_reg(c, c->pbases[OSM_BASE] + SEQ_REG(28), + SEQ_REG(49)); + + for (i = 0; i < MAX_MEM_ACC_VALUES; i++) + clk_osm_write_reg(c, c->apcs_mem_acc_val[i], + MEM_ACC_SEQ_REG_VAL_START(i)); + + for (i = 0; i < MAX_MEM_ACC_VAL_PER_LEVEL; i++) + clk_osm_write_reg(c, c->apcs_mem_acc_cfg[i], + MEM_ACC_SEQ_REG_CFG_START(i)); + } else { + if (c->mem_acc_crossover_vc) + scm_io_write(c->pbases[OSM_BASE] + SEQ_REG(88), + c->mem_acc_crossover_vc); + + threshold_vc[0] = mem_acc_level_map[0]; + threshold_vc[1] = mem_acc_level_map[0] + 1; + threshold_vc[2] = mem_acc_level_map[1]; + threshold_vc[3] = mem_acc_level_map[1] + 1; + + /* + * Use dynamic MEM ACC threshold voltage based value for the + * highest MEM ACC threshold if it is specified instead of the + * fixed mapping in the LUT. + */ + if (c->mem_acc_threshold_vc || c->mem_acc_threshold_pre_vc + == OSM_SEQ_MINUS_ONE) { + threshold_vc[2] = c->mem_acc_threshold_pre_vc; + threshold_vc[3] = c->mem_acc_threshold_vc; + + if (c->mem_acc_threshold_pre_vc == OSM_SEQ_MINUS_ONE) { + threshold_vc[1] = threshold_vc[0] = + c->mem_acc_threshold_pre_vc; + } else { + if (threshold_vc[1] >= threshold_vc[2]) + threshold_vc[1] = threshold_vc[2] - 1; + if (threshold_vc[0] >= threshold_vc[1]) + threshold_vc[0] = threshold_vc[1] - 1; + } + } + + scm_io_write(c->pbases[OSM_BASE] + SEQ_REG(55), + threshold_vc[0]); + scm_io_write(c->pbases[OSM_BASE] + SEQ_REG(56), + threshold_vc[1]); + scm_io_write(c->pbases[OSM_BASE] + SEQ_REG(57), + threshold_vc[2]); + scm_io_write(c->pbases[OSM_BASE] + SEQ_REG(58), + threshold_vc[3]); + /* SEQ_REG(49) = SEQ_REG(28) init by TZ */ + } + + /* + * Program L_VAL corresponding to the first virtual + * corner with MEM ACC level 3. + */ + if (c->mem_acc_threshold_vc || + c->mem_acc_threshold_pre_vc == OSM_SEQ_MINUS_ONE) + for (i = 0; i < c->num_entries; i++) + if (c->mem_acc_threshold_vc == table[i].virtual_corner) + scm_io_write(c->pbases[OSM_BASE] + SEQ_REG(32), + L_VAL(table[i].freq_data)); + + return; +} + +void clk_osm_setup_sequencer(struct clk_osm *c) +{ + u32 i; + + pr_debug("Setting up sequencer for cluster=%d\n", c->cluster_num); + for (i = 0; i < ARRAY_SIZE(seq_instr); i++) { + clk_osm_write_reg(c, seq_instr[i], + (long)(SEQ_MEM_ADDR + i * 4)); + } + + pr_debug("Setting up sequencer branch instructions for cluster=%d\n", + c->cluster_num); + for (i = 0; i < ARRAY_SIZE(seq_br_instr); i++) { + clk_osm_write_reg(c, seq_br_instr[i], + (long)(SEQ_CFG_BR_ADDR + i * 4)); + } +} + +static void clk_osm_setup_cycle_counters(struct clk_osm *c) +{ + u32 ratio = c->osm_clk_rate; + u32 val = 0; + + /* Enable cycle counter */ + val |= BIT(0); + /* Setup OSM clock to XO ratio */ + do_div(ratio, c->xo_clk_rate); + val |= BVAL(5, 1, ratio - 1) | OSM_CYCLE_COUNTER_USE_XO_EDGE_EN; + clk_osm_write_reg(c, val, OSM_CYCLE_COUNTER_CTRL_REG); + c->total_cycle_counter = 0; + c->prev_cycle_counter = 0; + pr_debug("OSM to XO clock ratio: %d\n", ratio); +} + +static void clk_osm_setup_osm_was(struct clk_osm *c) +{ + u32 cc_hyst; + u32 val; + + if (msm8998_v2) + return; + + val = clk_osm_read_reg(c, PDN_FSM_CTRL_REG); + val |= IGNORE_PLL_LOCK_MASK; + cc_hyst = clk_osm_read_reg(c, SPM_CC_HYSTERESIS); + + if (c->secure_init) { + clk_osm_write_reg(c, val, SEQ_REG(47)); + val &= ~IGNORE_PLL_LOCK_MASK; + clk_osm_write_reg(c, val, SEQ_REG(48)); + + clk_osm_write_reg(c, c->pbases[OSM_BASE] + SEQ_REG(42), + SEQ_REG(40)); + clk_osm_write_reg(c, c->pbases[OSM_BASE] + SEQ_REG(43), + SEQ_REG(41)); + clk_osm_write_reg(c, 0x1, SEQ_REG(44)); + clk_osm_write_reg(c, 0x0, SEQ_REG(45)); + clk_osm_write_reg(c, c->pbases[OSM_BASE] + PDN_FSM_CTRL_REG, + SEQ_REG(46)); + + /* C2D/C3 + D2D workaround */ + clk_osm_write_reg(c, c->pbases[OSM_BASE] + SPM_CC_HYSTERESIS, + SEQ_REG(6)); + clk_osm_write_reg(c, cc_hyst, SEQ_REG(7)); + + /* Droop detector PLL lock detect workaround */ + clk_osm_write_reg(c, PLL_DD_USER_CTL_LO_ENABLE, SEQ_REG(4)); + clk_osm_write_reg(c, PLL_DD_USER_CTL_LO_DISABLE, SEQ_REG(5)); + clk_osm_write_reg(c, c->cluster_num == 0 ? PLL_DD_D0_USER_CTL_LO + : PLL_DD_D1_USER_CTL_LO, SEQ_REG(21)); + + /* PLL lock detect and HMSS AHB clock workaround */ + clk_osm_write_reg(c, 0x640, CFG_DELAY_VAL_3); + + /* DxFSM workaround */ + clk_osm_write_reg(c, c->cluster_num == 0 ? 0x17911200 : + 0x17811200, SEQ_REG(22)); + clk_osm_write_reg(c, 0x80800, SEQ_REG(23)); + clk_osm_write_reg(c, 0x179D1100, SEQ_REG(24)); + clk_osm_write_reg(c, 0x11f, SEQ_REG(25)); + clk_osm_write_reg(c, c->cluster_num == 0 ? 0x17912000 : + 0x17811290, SEQ_REG(26)); + clk_osm_write_reg(c, c->cluster_num == 0 ? 0x17911290 : + 0x17811290, SEQ_REG(20)); + clk_osm_write_reg(c, c->cluster_num == 0 ? 0x17811290 : + 0x17911290, SEQ_REG(32)); + clk_osm_write_reg(c, 0x179D4020, SEQ_REG(35)); + clk_osm_write_reg(c, 0x11f, SEQ_REG(25)); + clk_osm_write_reg(c, 0xa, SEQ_REG(86)); + clk_osm_write_reg(c, 0xe, SEQ_REG(87)); + clk_osm_write_reg(c, 0x00400000, SEQ_REG(88)); + clk_osm_write_reg(c, 0x00700000, SEQ_REG(89)); + } else { + scm_io_write(c->pbases[OSM_BASE] + SEQ_REG(47), val); + val &= ~IGNORE_PLL_LOCK_MASK; + scm_io_write(c->pbases[OSM_BASE] + SEQ_REG(48), val); + + /* C2D/C3 + D2D workaround */ + scm_io_write(c->pbases[OSM_BASE] + SEQ_REG(7), + cc_hyst); + + /* Droop detector PLL lock detect workaround */ + scm_io_write(c->pbases[OSM_BASE] + SEQ_REG(4), + PLL_DD_USER_CTL_LO_ENABLE); + } + + if (c->cluster_num == 0) { + val = readl_relaxed(c->vbases[PLL_BASE] + PLL_TEST_CTL_HI) + | BIT(13); + writel_relaxed(val, c->vbases[PLL_BASE] + + PLL_TEST_CTL_HI); + } + + /* Ensure writes complete before returning */ + clk_osm_mb(c, OSM_BASE); +} + +static void clk_osm_setup_fsms(struct clk_osm *c) +{ + u32 val; + + /* Reduction FSM */ + if (c->red_fsm_en) { + val = clk_osm_read_reg(c, VMIN_REDUC_ENABLE_REG) | BIT(0); + clk_osm_write_reg(c, val, VMIN_REDUC_ENABLE_REG); + clk_osm_write_reg(c, BVAL(15, 0, clk_osm_count_ns(c, 10000)), + VMIN_REDUC_TIMER_REG); + } + + /* Boost FSM */ + if (c->boost_fsm_en) { + val = clk_osm_read_reg(c, PDN_FSM_CTRL_REG); + clk_osm_write_reg(c, val | CC_BOOST_EN_MASK, PDN_FSM_CTRL_REG); + + val = clk_osm_read_reg(c, CC_BOOST_TIMER_REG0); + val |= BVAL(15, 0, clk_osm_count_ns(c, PLL_WAIT_LOCK_TIME_NS)); + val |= BVAL(31, 16, clk_osm_count_ns(c, SAFE_FREQ_WAIT_NS)); + clk_osm_write_reg(c, val, CC_BOOST_TIMER_REG0); + + val = clk_osm_read_reg(c, CC_BOOST_TIMER_REG1); + val |= BVAL(15, 0, clk_osm_count_ns(c, PLL_WAIT_LOCK_TIME_NS)); + val |= BVAL(31, 16, clk_osm_count_ns(c, PLL_WAIT_LOCK_TIME_NS)); + clk_osm_write_reg(c, val, CC_BOOST_TIMER_REG1); + + val = clk_osm_read_reg(c, CC_BOOST_TIMER_REG2); + val |= BVAL(15, 0, clk_osm_count_ns(c, DEXT_DECREMENT_WAIT_NS)); + clk_osm_write_reg(c, val, CC_BOOST_TIMER_REG2); + } + + /* Safe Freq FSM */ + if (c->safe_fsm_en) { + val = clk_osm_read_reg(c, PDN_FSM_CTRL_REG); + clk_osm_write_reg(c, val | DCVS_BOOST_EN_MASK, + PDN_FSM_CTRL_REG); + + val = clk_osm_read_reg(c, DCVS_BOOST_TIMER_REG0); + val |= BVAL(15, 0, clk_osm_count_ns(c, PLL_WAIT_LOCK_TIME_NS)); + val |= BVAL(31, 16, clk_osm_count_ns(c, SAFE_FREQ_WAIT_NS)); + clk_osm_write_reg(c, val, DCVS_BOOST_TIMER_REG0); + + val = clk_osm_read_reg(c, DCVS_BOOST_TIMER_REG1); + val |= BVAL(15, 0, clk_osm_count_ns(c, PLL_WAIT_LOCK_TIME_NS)); + val |= BVAL(31, 16, clk_osm_count_ns(c, PLL_WAIT_LOCK_TIME_NS)); + clk_osm_write_reg(c, val, DCVS_BOOST_TIMER_REG1); + + val = clk_osm_read_reg(c, DCVS_BOOST_TIMER_REG2); + val |= BVAL(15, 0, clk_osm_count_ns(c, DEXT_DECREMENT_WAIT_NS)); + clk_osm_write_reg(c, val, DCVS_BOOST_TIMER_REG2); + + } + + /* PS FSM */ + if (c->ps_fsm_en) { + val = clk_osm_read_reg(c, PDN_FSM_CTRL_REG); + clk_osm_write_reg(c, val | PS_BOOST_EN_MASK, PDN_FSM_CTRL_REG); + + val = clk_osm_read_reg(c, PS_BOOST_TIMER_REG0); + val |= BVAL(15, 0, clk_osm_count_ns(c, PLL_WAIT_LOCK_TIME_NS)); + val |= BVAL(31, 16, clk_osm_count_ns(c, SAFE_FREQ_WAIT_NS)); + clk_osm_write_reg(c, val, PS_BOOST_TIMER_REG0); + + val = clk_osm_read_reg(c, PS_BOOST_TIMER_REG1); + val |= BVAL(15, 0, clk_osm_count_ns(c, PLL_WAIT_LOCK_TIME_NS)); + val |= BVAL(31, 16, clk_osm_count_ns(c, PLL_WAIT_LOCK_TIME_NS)); + clk_osm_write_reg(c, val, PS_BOOST_TIMER_REG1); + + val = clk_osm_read_reg(c, PS_BOOST_TIMER_REG2); + val |= BVAL(15, 0, clk_osm_count_ns(c, DEXT_DECREMENT_WAIT_NS)); + clk_osm_write_reg(c, val, PS_BOOST_TIMER_REG2); + } + + /* PLL signal timing control */ + if (c->boost_fsm_en || c->safe_fsm_en || c->ps_fsm_en) + clk_osm_write_reg(c, 0x5, BOOST_PROG_SYNC_DELAY_REG); + + /* Droop FSM */ + if (c->wfx_fsm_en) { + /* WFx FSM */ + val = clk_osm_read_reg(c, PDN_FSM_CTRL_REG); + clk_osm_write_reg(c, val | WFX_DROOP_EN_MASK, PDN_FSM_CTRL_REG); + + val = clk_osm_read_reg(c, DROOP_UNSTALL_TIMER_CTRL_REG); + val |= BVAL(31, 16, clk_osm_count_ns(c, 500)); + clk_osm_write_reg(c, val, DROOP_UNSTALL_TIMER_CTRL_REG); + + val = clk_osm_read_reg(c, + DROOP_WAIT_TO_RELEASE_TIMER_CTRL0_REG); + val |= BVAL(31, 16, clk_osm_count_ns(c, 250)); + clk_osm_write_reg(c, val, + DROOP_WAIT_TO_RELEASE_TIMER_CTRL0_REG); + } + + /* PC/RET FSM */ + if (c->pc_fsm_en) { + val = clk_osm_read_reg(c, PDN_FSM_CTRL_REG); + clk_osm_write_reg(c, val | PC_RET_EXIT_DROOP_EN_MASK, + PDN_FSM_CTRL_REG); + + val = clk_osm_read_reg(c, DROOP_UNSTALL_TIMER_CTRL_REG); + val |= BVAL(15, 0, clk_osm_count_ns(c, 500)); + clk_osm_write_reg(c, val, DROOP_UNSTALL_TIMER_CTRL_REG); + + val = clk_osm_read_reg(c, + DROOP_WAIT_TO_RELEASE_TIMER_CTRL0_REG); + val |= BVAL(15, 0, clk_osm_count_ns(c, 250)); + clk_osm_write_reg(c, val, + DROOP_WAIT_TO_RELEASE_TIMER_CTRL0_REG); + } + + /* DCVS droop FSM - only if RCGwRC is not used for di/dt control */ + if (c->droop_fsm_en) { + val = clk_osm_read_reg(c, PDN_FSM_CTRL_REG); + clk_osm_write_reg(c, val | DCVS_DROOP_EN_MASK, + PDN_FSM_CTRL_REG); + } + + if (c->wfx_fsm_en || c->ps_fsm_en || c->droop_fsm_en) { + clk_osm_write_reg(c, 0x1, DROOP_PROG_SYNC_DELAY_REG); + clk_osm_write_reg(c, clk_osm_count_ns(c, 5), + DROOP_RELEASE_TIMER_CTRL); + clk_osm_write_reg(c, clk_osm_count_ns(c, 500), + DCVS_DROOP_TIMER_CTRL); + val = clk_osm_read_reg(c, DROOP_CTRL_REG); + val |= BIT(31) | BVAL(22, 16, 0x2) | + BVAL(6, 0, 0x8); + clk_osm_write_reg(c, val, DROOP_CTRL_REG); + } + + /* Enable the PLL Droop Override */ + val = clk_osm_read_reg(c, OSM_PLL_SW_OVERRIDE_EN); + val |= PLL_SW_OVERRIDE_DROOP_EN; + clk_osm_write_reg(c, val, OSM_PLL_SW_OVERRIDE_EN); +} + +static void clk_osm_do_additional_setup(struct clk_osm *c, + struct platform_device *pdev) +{ + if (!c->secure_init) + return; + + dev_info(&pdev->dev, "Performing additional OSM setup due to lack of TZ for cluster=%d\n", + c->cluster_num); + + clk_osm_write_reg(c, BVAL(23, 16, 0xF), SPM_CC_CTRL); + + /* PLL LVAL programming */ + clk_osm_write_reg(c, c->l_val_base, SEQ_REG(0)); + clk_osm_write_reg(c, PLL_MIN_LVAL, SEQ_REG(21)); + + /* PLL post-div programming */ + clk_osm_write_reg(c, c->apcs_pll_user_ctl, SEQ_REG(18)); + clk_osm_write_reg(c, PLL_POST_DIV2, SEQ_REG(19)); + clk_osm_write_reg(c, PLL_POST_DIV1, SEQ_REG(29)); + + /* APM Programming */ + clk_osm_program_apm_regs(c); + + /* GFMUX Programming */ + clk_osm_write_reg(c, c->apcs_cfg_rcgr, SEQ_REG(16)); + clk_osm_write_reg(c, c->apcs_cmd_rcgr, SEQ_REG(33)); + clk_osm_write_reg(c, RCG_UPDATE, SEQ_REG(34)); + clk_osm_write_reg(c, GPLL_SEL, SEQ_REG(17)); + clk_osm_write_reg(c, PLL_EARLY_SEL, SEQ_REG(82)); + clk_osm_write_reg(c, PLL_MAIN_SEL, SEQ_REG(83)); + clk_osm_write_reg(c, RCG_UPDATE_SUCCESS, SEQ_REG(84)); + clk_osm_write_reg(c, RCG_UPDATE, SEQ_REG(85)); + + /* ITM to OSM handoff */ + clk_osm_setup_itm_to_osm_handoff(); + + pr_debug("seq_size: %lu, seqbr_size: %lu\n", ARRAY_SIZE(seq_instr), + ARRAY_SIZE(seq_br_instr)); + clk_osm_setup_sequencer(&pwrcl_clk); + clk_osm_setup_sequencer(&perfcl_clk); +} + +static void clk_osm_apm_vc_setup(struct clk_osm *c) +{ + /* + * APM crossover virtual corner corresponds to switching + * voltage during APM transition. APM threshold virtual + * corner is the first corner which requires switch + * sequence of APM from MX to APC. + */ + if (c->secure_init) { + clk_osm_write_reg(c, c->apm_threshold_vc, SEQ_REG(1)); + clk_osm_write_reg(c, c->apm_crossover_vc, SEQ_REG(72)); + clk_osm_write_reg(c, c->pbases[OSM_BASE] + SEQ_REG(1), + SEQ_REG(8)); + clk_osm_write_reg(c, c->apm_threshold_vc, + SEQ_REG(15)); + clk_osm_write_reg(c, c->apm_threshold_pre_vc, + SEQ_REG(31)); + clk_osm_write_reg(c, 0x3b | c->apm_threshold_vc << 6, + SEQ_REG(73)); + clk_osm_write_reg(c, 0x39 | c->apm_threshold_vc << 6, + SEQ_REG(76)); + + /* Ensure writes complete before returning */ + clk_osm_mb(c, OSM_BASE); + } else { + if (msm8998_v1) { + scm_io_write(c->pbases[OSM_BASE] + SEQ_REG(1), + c->apm_threshold_vc); + scm_io_write(c->pbases[OSM_BASE] + SEQ_REG(73), + 0x3b | c->apm_threshold_vc << 6); + } else if (msm8998_v2) { + clk_osm_write_reg(c, c->apm_threshold_vc, + SEQ_REG1_MSM8998_V2); + } + scm_io_write(c->pbases[OSM_BASE] + SEQ_REG(72), + c->apm_crossover_vc); + scm_io_write(c->pbases[OSM_BASE] + SEQ_REG(15), + c->apm_threshold_vc); + scm_io_write(c->pbases[OSM_BASE] + SEQ_REG(31), + c->apm_threshold_pre_vc); + scm_io_write(c->pbases[OSM_BASE] + SEQ_REG(76), + 0x39 | c->apm_threshold_vc << 6); + } +} + +static irqreturn_t clk_osm_debug_irq_cb(int irq, void *data) +{ + struct clk_osm *c = data; + unsigned long first, second, total_delta = 0; + u32 val, factor; + int i; + + val = clk_osm_read_reg(c, DCVS_PERF_STATE_DEVIATION_INTR_STAT); + if (val & BIT(0)) { + pr_info("OS DCVS performance state deviated\n"); + clk_osm_write_reg(c, BIT(0), + DCVS_PERF_STATE_DEVIATION_INTR_CLEAR); + } + + val = clk_osm_read_reg(c, + DCVS_PERF_STATE_DEVIATION_CORRECTED_INTR_STAT); + if (val & BIT(0)) { + pr_info("OS DCVS performance state corrected\n"); + clk_osm_write_reg(c, BIT(0), + DCVS_PERF_STATE_DEVIATION_CORRECTED_INTR_CLEAR); + } + + val = clk_osm_read_reg(c, DCVS_PERF_STATE_MET_INTR_STAT); + if (val & BIT(0)) { + pr_info("OS DCVS performance state desired reached\n"); + clk_osm_write_reg(c, BIT(0), DCVS_PERF_STATE_MET_INTR_CLR); + } + + factor = c->cycle_counter_factor ? c->cycle_counter_factor : 1; + + for (i = 0; i < c->cycle_counter_reads; i++) { + first = clk_osm_read_reg(c, OSM_CYCLE_COUNTER_STATUS_REG); + + if (c->cycle_counter_delay) + udelay(c->cycle_counter_delay); + + second = clk_osm_read_reg(c, OSM_CYCLE_COUNTER_STATUS_REG); + total_delta = total_delta + ((second - first) / factor); + } + + pr_info("cluster=%d, L_VAL (estimated)=%lu\n", + c->cluster_num, total_delta / c->cycle_counter_factor); + + return IRQ_HANDLED; +} + +static int clk_osm_setup_irq(struct platform_device *pdev, struct clk_osm *c, + char *irq_name) +{ + int rc = 0; + + rc = c->irq = platform_get_irq_byname(pdev, irq_name); + if (rc < 0) { + dev_err(&pdev->dev, "%s irq not specified\n", irq_name); + return rc; + } + + rc = devm_request_irq(&pdev->dev, c->irq, + clk_osm_debug_irq_cb, + IRQF_TRIGGER_RISING | IRQF_SHARED, + "OSM IRQ", c); + if (rc) + dev_err(&pdev->dev, "Request IRQ failed for OSM IRQ\n"); + + return rc; +} + +static u32 find_voltage(struct clk_osm *c, unsigned long rate) +{ + struct osm_entry *table = c->osm_table; + int entries = c->num_entries, i; + + for (i = 0; i < entries; i++) { + if (rate == table[i].frequency) { + /* OPP table voltages have units of mV */ + return table[i].open_loop_volt * 1000; + } + } + + return -EINVAL; +} + +static int add_opp(struct clk_osm *c, struct device *dev) +{ + unsigned long rate = 0; + u32 uv; + long rc; + int j = 0; + unsigned long min_rate = c->c.fmax[0]; + unsigned long max_rate = c->c.fmax[c->c.num_fmax - 1]; + + while (1) { + rate = c->c.fmax[j++]; + uv = find_voltage(c, rate); + if (uv <= 0) { + pr_warn("No voltage for %lu.\n", rate); + return -EINVAL; + } + + rc = dev_pm_opp_add(dev, rate, uv); + if (rc) { + pr_warn("failed to add OPP for %lu\n", rate); + return rc; + } + + /* + * Print the OPP pair for the lowest and highest frequency for + * each device that we're populating. This is important since + * this information will be used by thermal mitigation and the + * scheduler. + */ + if (rate == min_rate) + pr_info("Set OPP pair (%lu Hz, %d uv) on %s\n", + rate, uv, dev_name(dev)); + + if (rate == max_rate && max_rate != min_rate) { + pr_info("Set OPP pair (%lu Hz, %d uv) on %s\n", + rate, uv, dev_name(dev)); + break; + } + + if (min_rate == max_rate) + break; + } + + return 0; +} + +static struct clk *logical_cpu_to_clk(int cpu) +{ + struct device_node *cpu_node; + const u32 *cell; + u64 hwid; + static struct clk *cpu_clk_map[NR_CPUS]; + + if (cpu_clk_map[cpu]) + return cpu_clk_map[cpu]; + + cpu_node = of_get_cpu_node(cpu, NULL); + if (!cpu_node) + goto fail; + + cell = of_get_property(cpu_node, "reg", NULL); + if (!cell) { + pr_err("%s: missing reg property\n", cpu_node->full_name); + goto fail; + } + + hwid = of_read_number(cell, of_n_addr_cells(cpu_node)); + if ((hwid | pwrcl_clk.cpu_reg_mask) == pwrcl_clk.cpu_reg_mask) { + cpu_clk_map[cpu] = &pwrcl_clk.c; + return &pwrcl_clk.c; + } + if ((hwid | perfcl_clk.cpu_reg_mask) == perfcl_clk.cpu_reg_mask) { + cpu_clk_map[cpu] = &perfcl_clk.c; + return &perfcl_clk.c; + } + +fail: + return NULL; +} + +static u64 clk_osm_get_cpu_cycle_counter(int cpu) +{ + struct clk_osm *c; + u32 val; + unsigned long flags; + + if (logical_cpu_to_clk(cpu) == &pwrcl_clk.c) + c = &pwrcl_clk; + else if (logical_cpu_to_clk(cpu) == &perfcl_clk.c) + c = &perfcl_clk; + else { + pr_err("no clock device for CPU=%d\n", cpu); + return 0; + } + + spin_lock_irqsave(&c->lock, flags); + val = clk_osm_read_reg_no_log(c, OSM_CYCLE_COUNTER_STATUS_REG); + + if (val < c->prev_cycle_counter) { + /* Handle counter overflow */ + c->total_cycle_counter += UINT_MAX - + c->prev_cycle_counter + val; + c->prev_cycle_counter = val; + } else { + c->total_cycle_counter += val - c->prev_cycle_counter; + c->prev_cycle_counter = val; + } + spin_unlock_irqrestore(&c->lock, flags); + + return c->total_cycle_counter; +} + +static void populate_opp_table(struct platform_device *pdev) +{ + int cpu; + + for_each_possible_cpu(cpu) { + if (logical_cpu_to_clk(cpu) == &pwrcl_clk.c) { + WARN(add_opp(&pwrcl_clk, get_cpu_device(cpu)), + "Failed to add OPP levels for power cluster\n"); + } + if (logical_cpu_to_clk(cpu) == &perfcl_clk.c) { + WARN(add_opp(&perfcl_clk, get_cpu_device(cpu)), + "Failed to add OPP levels for perf cluster\n"); + } + } +} + +static int debugfs_get_trace_enable(void *data, u64 *val) +{ + struct clk_osm *c = data; + + *val = c->trace_en; + return 0; +} + +static int debugfs_set_trace_enable(void *data, u64 val) +{ + struct clk_osm *c = data; + + clk_osm_masked_write_reg(c, val ? TRACE_CTRL_ENABLE : + TRACE_CTRL_DISABLE, + TRACE_CTRL, TRACE_CTRL_EN_MASK); + c->trace_en = val ? true : false; + return 0; +} +DEFINE_SIMPLE_ATTRIBUTE(debugfs_trace_enable_fops, + debugfs_get_trace_enable, + debugfs_set_trace_enable, + "%llu\n"); + +static int debugfs_get_wdog_trace(void *data, u64 *val) +{ + struct clk_osm *c = data; + + *val = c->wdog_trace_en; + return 0; +} + +static int debugfs_set_wdog_trace(void *data, u64 val) +{ + struct clk_osm *c = data; + int regval; + + if (msm8998_v2) { + regval = clk_osm_read_reg(c, TRACE_CTRL); + regval = val ? regval | TRACE_CTRL_ENABLE_WDOG_STATUS : + regval & ~TRACE_CTRL_ENABLE_WDOG_STATUS; + clk_osm_write_reg(c, regval, TRACE_CTRL); + c->wdog_trace_en = val ? true : false; + } else { + pr_info("wdog status registers enabled by default\n"); + } + + return 0; +} +DEFINE_SIMPLE_ATTRIBUTE(debugfs_trace_wdog_enable_fops, + debugfs_get_wdog_trace, + debugfs_set_wdog_trace, + "%llu\n"); + +#define MAX_DEBUG_BUF_LEN 15 + +static DEFINE_MUTEX(debug_buf_mutex); +static char debug_buf[MAX_DEBUG_BUF_LEN]; + +static ssize_t debugfs_trace_method_set(struct file *file, + const char __user *buf, + size_t count, loff_t *ppos) +{ + struct clk_osm *c = file->private_data; + u32 val; + + if (IS_ERR(file) || file == NULL) { + pr_err("input error %ld\n", PTR_ERR(file)); + return -EINVAL; + } + + if (!c) { + pr_err("invalid clk_osm handle\n"); + return -EINVAL; + } + + if (count < MAX_DEBUG_BUF_LEN) { + mutex_lock(&debug_buf_mutex); + + if (copy_from_user(debug_buf, (void __user *) buf, count)) { + mutex_unlock(&debug_buf_mutex); + return -EFAULT; + } + debug_buf[count] = '\0'; + mutex_unlock(&debug_buf_mutex); + + /* check that user entered a supported packet type */ + if (strcmp(debug_buf, "periodic\n") == 0) { + clk_osm_write_reg(c, clk_osm_count_ns(c, + PERIODIC_TRACE_DEFAULT_NS), + PERIODIC_TRACE_TIMER_CTRL); + clk_osm_masked_write_reg(c, + TRACE_CTRL_PERIODIC_TRACE_ENABLE, + TRACE_CTRL, TRACE_CTRL_PERIODIC_TRACE_EN_MASK); + c->trace_method = PERIODIC_PACKET; + c->trace_periodic_timer = PERIODIC_TRACE_DEFAULT_NS; + return count; + } else if (strcmp(debug_buf, "xor\n") == 0) { + val = clk_osm_read_reg(c, TRACE_CTRL); + val &= ~TRACE_CTRL_PERIODIC_TRACE_ENABLE; + clk_osm_write_reg(c, val, TRACE_CTRL); + c->trace_method = XOR_PACKET; + return count; + } + } + + pr_err("error, supported trace mode types: 'periodic' or 'xor'\n"); + return -EINVAL; +} + +static ssize_t debugfs_trace_method_get(struct file *file, char __user *buf, + size_t count, loff_t *ppos) +{ + struct clk_osm *c = file->private_data; + int len = 0, rc; + + if (IS_ERR(file) || file == NULL) { + pr_err("input error %ld\n", PTR_ERR(file)); + return -EINVAL; + } + + if (!c) { + pr_err("invalid clk_osm handle\n"); + return -EINVAL; + } + + mutex_lock(&debug_buf_mutex); + + if (c->trace_method == PERIODIC_PACKET) + len = snprintf(debug_buf, sizeof(debug_buf), "periodic\n"); + else if (c->trace_method == XOR_PACKET) + len = snprintf(debug_buf, sizeof(debug_buf), "xor\n"); + + rc = simple_read_from_buffer((void __user *) buf, count, ppos, + (void *) debug_buf, len); + + mutex_unlock(&debug_buf_mutex); + + return rc; +} + +static int debugfs_trace_method_open(struct inode *inode, struct file *file) +{ + if (IS_ERR(file) || file == NULL) { + pr_err("input error %ld\n", PTR_ERR(file)); + return -EINVAL; + } + + file->private_data = inode->i_private; + return 0; +} + +static const struct file_operations debugfs_trace_method_fops = { + .write = debugfs_trace_method_set, + .open = debugfs_trace_method_open, + .read = debugfs_trace_method_get, +}; + +static int debugfs_get_trace_packet_id(void *data, u64 *val) +{ + struct clk_osm *c = data; + + *val = c->trace_id; + return 0; +} + +static int debugfs_set_trace_packet_id(void *data, u64 val) +{ + struct clk_osm *c = data; + + if (val < TRACE_PACKET0 || val > TRACE_PACKET3) { + pr_err("supported trace IDs=%d-%d\n", + TRACE_PACKET0, TRACE_PACKET3); + return 0; + } + + clk_osm_masked_write_reg(c, val << TRACE_CTRL_PACKET_TYPE_SHIFT, + TRACE_CTRL, TRACE_CTRL_PACKET_TYPE_MASK); + c->trace_id = val; + return 0; +} +DEFINE_SIMPLE_ATTRIBUTE(debugfs_trace_packet_id_fops, + debugfs_get_trace_packet_id, + debugfs_set_trace_packet_id, + "%llu\n"); + +static int debugfs_get_trace_periodic_timer(void *data, u64 *val) +{ + struct clk_osm *c = data; + + *val = c->trace_periodic_timer; + return 0; +} + +static int debugfs_set_trace_periodic_timer(void *data, u64 val) +{ + struct clk_osm *c = data; + + if (val < PERIODIC_TRACE_MIN_NS || val > PERIODIC_TRACE_MAX_NS) { + pr_err("supported periodic trace periods=%d-%ld ns\n", + PERIODIC_TRACE_MIN_NS, PERIODIC_TRACE_MAX_NS); + return 0; + } + + clk_osm_write_reg(c, clk_osm_count_ns(c, val), + PERIODIC_TRACE_TIMER_CTRL); + c->trace_periodic_timer = val; + return 0; +} +DEFINE_SIMPLE_ATTRIBUTE(debugfs_trace_periodic_timer_fops, + debugfs_get_trace_periodic_timer, + debugfs_set_trace_periodic_timer, + "%llu\n"); + +static int debugfs_get_perf_state_met_irq(void *data, u64 *val) +{ + struct clk_osm *c = data; + + *val = clk_osm_read_reg(c, DCVS_PERF_STATE_MET_INTR_EN); + return 0; +} + +static int debugfs_set_perf_state_met_irq(void *data, u64 val) +{ + struct clk_osm *c = data; + + clk_osm_write_reg(c, val ? 1 : 0, + DCVS_PERF_STATE_MET_INTR_EN); + return 0; +} +DEFINE_SIMPLE_ATTRIBUTE(debugfs_perf_state_met_irq_fops, + debugfs_get_perf_state_met_irq, + debugfs_set_perf_state_met_irq, + "%llu\n"); + +static int debugfs_get_perf_state_deviation_irq(void *data, u64 *val) +{ + struct clk_osm *c = data; + + *val = clk_osm_read_reg(c, + DCVS_PERF_STATE_DEVIATION_INTR_EN); + return 0; +} + +static int debugfs_set_perf_state_deviation_irq(void *data, u64 val) +{ + struct clk_osm *c = data; + + clk_osm_write_reg(c, val ? 1 : 0, + DCVS_PERF_STATE_DEVIATION_INTR_EN); + return 0; +} +DEFINE_SIMPLE_ATTRIBUTE(debugfs_perf_state_deviation_irq_fops, + debugfs_get_perf_state_deviation_irq, + debugfs_set_perf_state_deviation_irq, + "%llu\n"); + +static int debugfs_get_perf_state_deviation_corrected_irq(void *data, u64 *val) +{ + struct clk_osm *c = data; + + *val = clk_osm_read_reg(c, + DCVS_PERF_STATE_DEVIATION_CORRECTED_INTR_EN); + return 0; +} + +static int debugfs_set_perf_state_deviation_corrected_irq(void *data, u64 val) +{ + struct clk_osm *c = data; + + clk_osm_write_reg(c, val ? 1 : 0, + DCVS_PERF_STATE_DEVIATION_CORRECTED_INTR_EN); + return 0; +} +DEFINE_SIMPLE_ATTRIBUTE(debugfs_perf_state_deviation_corrected_irq_fops, + debugfs_get_perf_state_deviation_corrected_irq, + debugfs_set_perf_state_deviation_corrected_irq, + "%llu\n"); + +static int debugfs_get_debug_reg(void *data, u64 *val) +{ + struct clk_osm *c = data; + + if (!c->pbases[ACD_BASE]) { + pr_err("ACD base start not defined\n"); + return -EINVAL; + } + + if (c->acd_debugfs_addr >= ACD_MASTER_ONLY_REG_ADDR) + *val = readl_relaxed((char *)c->vbases[ACD_BASE] + + c->acd_debugfs_addr); + else + *val = clk_osm_acd_local_read_reg(c, c->acd_debugfs_addr); + return 0; +} + +static int debugfs_set_debug_reg(void *data, u64 val) +{ + struct clk_osm *c = data; + + if (!c->pbases[ACD_BASE]) { + pr_err("ACD base start not defined\n"); + return -EINVAL; + } + + if (c->acd_debugfs_addr >= ACD_MASTER_ONLY_REG_ADDR) + clk_osm_acd_master_write_reg(c, val, c->acd_debugfs_addr); + else + clk_osm_acd_master_write_through_reg(c, val, + c->acd_debugfs_addr); + + return 0; +} +DEFINE_SIMPLE_ATTRIBUTE(debugfs_acd_debug_reg_fops, + debugfs_get_debug_reg, + debugfs_set_debug_reg, + "0x%llx\n"); + +static int debugfs_get_debug_reg_addr(void *data, u64 *val) +{ + struct clk_osm *c = data; + + if (!c->pbases[ACD_BASE]) { + pr_err("ACD base start not defined\n"); + return -EINVAL; + } + + *val = c->acd_debugfs_addr; + + return 0; +} + +static int debugfs_set_debug_reg_addr(void *data, u64 val) +{ + struct clk_osm *c = data; + + if (!c->pbases[ACD_BASE]) { + pr_err("ACD base start not defined\n"); + return -EINVAL; + } + + if (val >= c->acd_debugfs_addr_size) + return -EINVAL; + + c->acd_debugfs_addr = val; + + return 0; +} +DEFINE_SIMPLE_ATTRIBUTE(debugfs_acd_debug_reg_addr_fops, + debugfs_get_debug_reg_addr, + debugfs_set_debug_reg_addr, + "%llu\n"); + +static void populate_debugfs_dir(struct clk_osm *c) +{ + struct dentry *temp; + + if (osm_debugfs_base == NULL) { + osm_debugfs_base = debugfs_create_dir("osm", NULL); + if (IS_ERR_OR_NULL(osm_debugfs_base)) { + pr_err("osm debugfs base directory creation failed\n"); + osm_debugfs_base = NULL; + return; + } + } + + c->debugfs = debugfs_create_dir(c->c.dbg_name, osm_debugfs_base); + if (IS_ERR_OR_NULL(c->debugfs)) { + pr_err("osm debugfs directory creation failed\n"); + return; + } + + temp = debugfs_create_file("perf_state_met_irq_enable", + S_IRUGO | S_IWUSR, + c->debugfs, c, + &debugfs_perf_state_met_irq_fops); + if (IS_ERR_OR_NULL(temp)) { + pr_err("perf_state_met_irq_enable debugfs file creation failed\n"); + goto exit; + } + + temp = debugfs_create_file("perf_state_deviation_irq_enable", + S_IRUGO | S_IWUSR, + c->debugfs, c, + &debugfs_perf_state_deviation_irq_fops); + if (IS_ERR_OR_NULL(temp)) { + pr_err("perf_state_deviation_irq_enable debugfs file creation failed\n"); + goto exit; + } + + temp = debugfs_create_file("perf_state_deviation_corrected_irq_enable", + S_IRUGO | S_IWUSR, + c->debugfs, c, + &debugfs_perf_state_deviation_corrected_irq_fops); + if (IS_ERR_OR_NULL(temp)) { + pr_err("debugfs_perf_state_deviation_corrected_irq_fops debugfs file creation failed\n"); + goto exit; + } + + temp = debugfs_create_file("wdog_trace_enable", + S_IRUGO | S_IWUSR, + c->debugfs, c, + &debugfs_trace_wdog_enable_fops); + if (IS_ERR_OR_NULL(temp)) { + pr_err("debugfs_trace_wdog_enable_fops debugfs file creation failed\n"); + goto exit; + } + + temp = debugfs_create_file("trace_enable", + S_IRUGO | S_IWUSR, + c->debugfs, c, + &debugfs_trace_enable_fops); + if (IS_ERR_OR_NULL(temp)) { + pr_err("debugfs_trace_enable_fops debugfs file creation failed\n"); + goto exit; + } + + temp = debugfs_create_file("trace_method", + S_IRUGO | S_IWUSR, + c->debugfs, c, + &debugfs_trace_method_fops); + if (IS_ERR_OR_NULL(temp)) { + pr_err("debugfs_trace_method_fops debugfs file creation failed\n"); + goto exit; + } + + temp = debugfs_create_file("trace_packet_id", + S_IRUGO | S_IWUSR, + c->debugfs, c, + &debugfs_trace_packet_id_fops); + if (IS_ERR_OR_NULL(temp)) { + pr_err("debugfs_trace_packet_id_fops debugfs file creation failed\n"); + goto exit; + } + + temp = debugfs_create_file("trace_periodic_timer", + S_IRUGO | S_IWUSR, + c->debugfs, c, + &debugfs_trace_periodic_timer_fops); + if (IS_ERR_OR_NULL(temp)) { + pr_err("debugfs_trace_periodic_timer_fops debugfs file creation failed\n"); + goto exit; + } + + temp = debugfs_create_file("acd_debug_reg", + S_IRUGO | S_IWUSR, + c->debugfs, c, + &debugfs_acd_debug_reg_fops); + if (IS_ERR_OR_NULL(temp)) { + pr_err("debugfs_acd_debug_reg_fops debugfs file creation failed\n"); + goto exit; + } + + temp = debugfs_create_file("acd_debug_reg_addr", + S_IRUGO | S_IWUSR, + c->debugfs, c, + &debugfs_acd_debug_reg_addr_fops); + if (IS_ERR_OR_NULL(temp)) { + pr_err("debugfs_acd_debug_reg_addr_fops debugfs file creation failed\n"); + goto exit; + } + +exit: + if (IS_ERR_OR_NULL(temp)) + debugfs_remove_recursive(c->debugfs); +} + +static int clk_osm_panic_callback(struct notifier_block *nfb, + unsigned long event, + void *data) +{ + int i; + u32 value; + struct clk_osm *c = container_of(nfb, + struct clk_osm, + panic_notifier); + + for (i = 0; i < DEBUG_REG_NUM; i++) { + value = readl_relaxed(c->debug_regs[i]); + pr_debug("%s_%d=0x%08x\n", clk_panic_reg_names[i], + c->cluster_num, value); + } + + return NOTIFY_OK; +} + +static unsigned long init_rate = 300000000; +static unsigned long osm_clk_init_rate = 200000000; + +static int cpu_clock_osm_driver_probe(struct platform_device *pdev) +{ + int rc, cpu; + int speedbin = 0, pvs_ver = 0; + u32 pte_efuse; + char pwrclspeedbinstr[] = "qcom,pwrcl-speedbin0-v0"; + char perfclspeedbinstr[] = "qcom,perfcl-speedbin0-v0"; + struct cpu_cycle_counter_cb cb = { + .get_cpu_cycle_counter = clk_osm_get_cpu_cycle_counter, + }; + + if (of_find_compatible_node(NULL, NULL, + "qcom,cpu-clock-osm-msm8998-v1")) { + msm8998_v1 = true; + } else if (of_find_compatible_node(NULL, NULL, + "qcom,cpu-clock-osm-msm8998-v2")) { + msm8998_v2 = true; + } + + rc = clk_osm_parse_dt_configs(pdev); + if (rc) { + dev_err(&pdev->dev, "Unable to parse device tree configurations\n"); + return rc; + } + + rc = clk_osm_resources_init(pdev); + if (rc) { + if (rc != -EPROBE_DEFER) + dev_err(&pdev->dev, "resources init failed, rc=%d\n", + rc); + return rc; + } + + if ((pwrcl_clk.secure_init || perfcl_clk.secure_init) && + msm8998_v2) { + pr_err("unsupported configuration for msm8998 v2\n"); + return -EINVAL; + } + + if (pwrcl_clk.vbases[EFUSE_BASE]) { + /* Multiple speed-bins are supported */ + pte_efuse = readl_relaxed(pwrcl_clk.vbases[EFUSE_BASE]); + speedbin = ((pte_efuse >> PWRCL_EFUSE_SHIFT) & + PWRCL_EFUSE_MASK); + snprintf(pwrclspeedbinstr, ARRAY_SIZE(pwrclspeedbinstr), + "qcom,pwrcl-speedbin%d-v%d", speedbin, pvs_ver); + } + + dev_info(&pdev->dev, "using pwrcl speed bin %u and pvs_ver %d\n", + speedbin, pvs_ver); + + rc = clk_osm_get_lut(pdev, &pwrcl_clk, + pwrclspeedbinstr); + if (rc) { + dev_err(&pdev->dev, "Unable to get OSM LUT for power cluster, rc=%d\n", + rc); + return rc; + } + + if (perfcl_clk.vbases[EFUSE_BASE]) { + /* Multiple speed-bins are supported */ + pte_efuse = readl_relaxed(perfcl_clk.vbases[EFUSE_BASE]); + speedbin = ((pte_efuse >> PERFCL_EFUSE_SHIFT) & + PERFCL_EFUSE_MASK); + snprintf(perfclspeedbinstr, ARRAY_SIZE(perfclspeedbinstr), + "qcom,perfcl-speedbin%d-v%d", speedbin, pvs_ver); + } + + dev_info(&pdev->dev, "using perfcl speed bin %u and pvs_ver %d\n", + speedbin, pvs_ver); + + rc = clk_osm_get_lut(pdev, &perfcl_clk, perfclspeedbinstr); + if (rc) { + dev_err(&pdev->dev, "Unable to get OSM LUT for perf cluster, rc=%d\n", + rc); + return rc; + } + + rc = clk_osm_resolve_open_loop_voltages(&pwrcl_clk); + if (rc) { + if (rc == -EPROBE_DEFER) + return rc; + dev_err(&pdev->dev, "Unable to determine open-loop voltages for power cluster, rc=%d\n", + rc); + return rc; + } + + rc = clk_osm_resolve_open_loop_voltages(&perfcl_clk); + if (rc) { + if (rc == -EPROBE_DEFER) + return rc; + dev_err(&pdev->dev, "Unable to determine open-loop voltages for perf cluster, rc=%d\n", + rc); + return rc; + } + + rc = clk_osm_resolve_crossover_corners(&pwrcl_clk, pdev, + "qcom,pwrcl-apcs-mem-acc-threshold-voltage"); + if (rc) + dev_info(&pdev->dev, "No MEM-ACC crossover corner programmed\n"); + + rc = clk_osm_resolve_crossover_corners(&perfcl_clk, pdev, + "qcom,perfcl-apcs-mem-acc-threshold-voltage"); + if (rc) + dev_info(&pdev->dev, "No MEM-ACC crossover corner programmed\n"); + + clk_osm_setup_cycle_counters(&pwrcl_clk); + clk_osm_setup_cycle_counters(&perfcl_clk); + + clk_osm_print_osm_table(&pwrcl_clk); + clk_osm_print_osm_table(&perfcl_clk); + + rc = clk_osm_setup_hw_table(&pwrcl_clk); + if (rc) { + dev_err(&pdev->dev, "failed to setup power cluster hardware table\n"); + goto exit; + } + rc = clk_osm_setup_hw_table(&perfcl_clk); + if (rc) { + dev_err(&pdev->dev, "failed to setup perf cluster hardware table\n"); + goto exit; + } + + /* Policy tuning */ + rc = clk_osm_set_cc_policy(pdev); + if (rc < 0) { + dev_err(&pdev->dev, "cc policy setup failed"); + goto exit; + } + + /* LLM Freq Policy Tuning */ + rc = clk_osm_set_llm_freq_policy(pdev); + if (rc < 0) { + dev_err(&pdev->dev, "LLM Frequency Policy setup failed"); + goto exit; + } + + /* LLM Voltage Policy Tuning */ + rc = clk_osm_set_llm_volt_policy(pdev); + if (rc < 0) { + dev_err(&pdev->dev, "Failed to set LLM voltage Policy"); + goto exit; + } + + clk_osm_setup_fsms(&pwrcl_clk); + clk_osm_setup_fsms(&perfcl_clk); + + /* + * Perform typical secure-world HW initialization + * as necessary. + */ + clk_osm_do_additional_setup(&pwrcl_clk, pdev); + clk_osm_do_additional_setup(&perfcl_clk, pdev); + + /* MEM-ACC Programming */ + clk_osm_program_mem_acc_regs(&pwrcl_clk); + clk_osm_program_mem_acc_regs(&perfcl_clk); + + /* Program APM crossover corners */ + clk_osm_apm_vc_setup(&pwrcl_clk); + clk_osm_apm_vc_setup(&perfcl_clk); + + rc = clk_osm_setup_irq(pdev, &pwrcl_clk, "pwrcl-irq"); + if (rc) + pr_err("Debug IRQ not set for pwrcl\n"); + + rc = clk_osm_setup_irq(pdev, &perfcl_clk, "perfcl-irq"); + if (rc) + pr_err("Debug IRQ not set for perfcl\n"); + + clk_osm_setup_osm_was(&pwrcl_clk); + clk_osm_setup_osm_was(&perfcl_clk); + + if (of_property_read_bool(pdev->dev.of_node, + "qcom,osm-pll-setup")) { + clk_osm_setup_cluster_pll(&pwrcl_clk); + clk_osm_setup_cluster_pll(&perfcl_clk); + } + + spin_lock_init(&pwrcl_clk.lock); + spin_lock_init(&perfcl_clk.lock); + + pwrcl_clk.panic_notifier.notifier_call = clk_osm_panic_callback; + atomic_notifier_chain_register(&panic_notifier_list, + &pwrcl_clk.panic_notifier); + perfcl_clk.panic_notifier.notifier_call = clk_osm_panic_callback; + atomic_notifier_chain_register(&panic_notifier_list, + &perfcl_clk.panic_notifier); + + rc = of_msm_clock_register(pdev->dev.of_node, cpu_clocks_osm, + ARRAY_SIZE(cpu_clocks_osm)); + if (rc) { + dev_err(&pdev->dev, "Unable to register CPU clocks, rc=%d\n", + rc); + return rc; + } + + /* + * The hmss_gpll0 clock runs at 300 MHz. Ensure it is at the correct + * frequency before enabling OSM. LUT index 0 is always sourced from + * this clock. + */ + rc = clk_set_rate(&sys_apcsaux_clk_gcc.c, init_rate); + if (rc) { + dev_err(&pdev->dev, "Unable to set init rate on hmss_gpll0, rc=%d\n", + rc); + return rc; + } + clk_prepare_enable(&sys_apcsaux_clk_gcc.c); + + rc = clk_set_rate(&osm_clk_src.c, osm_clk_init_rate); + if (rc) { + dev_err(&pdev->dev, "Unable to set init rate on osm_clk, rc=%d\n", + rc); + goto exit2; + } + + /* Make sure index zero is selected */ + rc = clk_set_rate(&pwrcl_clk.c, init_rate); + if (rc) { + dev_err(&pdev->dev, "Unable to set init rate on pwr cluster, rc=%d\n", + rc); + goto exit2; + } + + rc = clk_set_rate(&perfcl_clk.c, init_rate); + if (rc) { + dev_err(&pdev->dev, "Unable to set init rate on perf cluster, rc=%d\n", + rc); + goto exit2; + } + + get_online_cpus(); + + /* Enable OSM */ + for_each_online_cpu(cpu) { + WARN(clk_prepare_enable(logical_cpu_to_clk(cpu)), + "Failed to enable clock for cpu %d\n", cpu); + } + + /* Set final boot rate */ + rc = clk_set_rate(&pwrcl_clk.c, msm8998_v1 ? + MSM8998V1_PWRCL_BOOT_RATE : + MSM8998V2_PWRCL_BOOT_RATE); + if (rc) { + dev_err(&pdev->dev, "Unable to set boot rate on pwr cluster, rc=%d\n", + rc); + goto exit2; + } + + rc = clk_set_rate(&perfcl_clk.c, msm8998_v1 ? + MSM8998V1_PERFCL_BOOT_RATE : + MSM8998V2_PERFCL_BOOT_RATE); + if (rc) { + dev_err(&pdev->dev, "Unable to set boot rate on perf cluster, rc=%d\n", + rc); + goto exit2; + } + + populate_opp_table(pdev); + populate_debugfs_dir(&pwrcl_clk); + populate_debugfs_dir(&perfcl_clk); + + of_platform_populate(pdev->dev.of_node, NULL, NULL, &pdev->dev); + + register_cpu_cycle_counter_cb(&cb); + + pr_info("OSM driver inited\n"); + put_online_cpus(); + + return 0; + +exit2: + clk_disable_unprepare(&sys_apcsaux_clk_gcc.c); +exit: + dev_err(&pdev->dev, "OSM driver failed to initialize, rc=%d\n", + rc); + panic("Unable to Setup OSM"); +} + +static struct of_device_id match_table[] = { + { .compatible = "qcom,cpu-clock-osm-msm8998-v1" }, + { .compatible = "qcom,cpu-clock-osm-msm8998-v2" }, + {} +}; + +static struct platform_driver cpu_clock_osm_driver = { + .probe = cpu_clock_osm_driver_probe, + .driver = { + .name = "cpu-clock-osm", + .of_match_table = match_table, + .owner = THIS_MODULE, + }, +}; + +static int __init cpu_clock_osm_init(void) +{ + return platform_driver_register(&cpu_clock_osm_driver); +} +arch_initcall(cpu_clock_osm_init); + +static void __exit cpu_clock_osm_exit(void) +{ + platform_driver_unregister(&cpu_clock_osm_driver); +} +module_exit(cpu_clock_osm_exit); + +MODULE_DESCRIPTION("CPU clock driver for OSM"); +MODULE_LICENSE("GPL v2"); diff -Nruw linux-4.4.115-fbx/drivers/clk/msm./clock-pll.c linux-4.4.115-fbx/drivers/clk/msm/clock-pll.c --- linux-4.4.115-fbx/drivers/clk/msm./clock-pll.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-4.4.115-fbx/drivers/clk/msm/clock-pll.c 2019-01-22 16:16:23.019242024 +0100 @@ -0,0 +1,1206 @@ +/* + * Copyright (c) 2012-2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#define pr_fmt(fmt) "%s: " fmt, __func__ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "clock.h" + +#define PLL_OUTCTRL BIT(0) +#define PLL_BYPASSNL BIT(1) +#define PLL_RESET_N BIT(2) +#define PLL_MODE_MASK BM(3, 0) + +#define PLL_EN_REG(x) (*(x)->base + (unsigned long) (x)->en_reg) +#define PLL_STATUS_REG(x) (*(x)->base + (unsigned long) (x)->status_reg) +#define PLL_ALT_STATUS_REG(x) (*(x)->base + (unsigned long) \ + (x)->alt_status_reg) +#define PLL_MODE_REG(x) (*(x)->base + (unsigned long) (x)->mode_reg) +#define PLL_L_REG(x) (*(x)->base + (unsigned long) (x)->l_reg) +#define PLL_M_REG(x) (*(x)->base + (unsigned long) (x)->m_reg) +#define PLL_N_REG(x) (*(x)->base + (unsigned long) (x)->n_reg) +#define PLL_CONFIG_REG(x) (*(x)->base + (unsigned long) (x)->config_reg) +#define PLL_ALPHA_REG(x) (*(x)->base + (unsigned long) (x)->alpha_reg) +#define PLL_CFG_ALT_REG(x) (*(x)->base + (unsigned long) \ + (x)->config_alt_reg) +#define PLL_CFG_CTL_REG(x) (*(x)->base + (unsigned long) \ + (x)->config_ctl_reg) +#define PLL_CFG_CTL_HI_REG(x) (*(x)->base + (unsigned long) \ + (x)->config_ctl_hi_reg) +#define PLL_TEST_CTL_LO_REG(x) (*(x)->base + (unsigned long) \ + (x)->test_ctl_lo_reg) +#define PLL_TEST_CTL_HI_REG(x) (*(x)->base + (unsigned long) \ + (x)->test_ctl_hi_reg) +static DEFINE_SPINLOCK(pll_reg_lock); + +#define ENABLE_WAIT_MAX_LOOPS 200 +#define PLL_LOCKED_BIT BIT(16) + +#define SPM_FORCE_EVENT 0x4 + +static int pll_vote_clk_enable(struct clk *c) +{ + u32 ena, count; + unsigned long flags; + struct pll_vote_clk *pllv = to_pll_vote_clk(c); + + spin_lock_irqsave(&pll_reg_lock, flags); + ena = readl_relaxed(PLL_EN_REG(pllv)); + ena |= pllv->en_mask; + writel_relaxed(ena, PLL_EN_REG(pllv)); + spin_unlock_irqrestore(&pll_reg_lock, flags); + + /* + * Use a memory barrier since some PLL status registers are + * not within the same 1K segment as the voting registers. + */ + mb(); + + /* Wait for pll to enable. */ + for (count = ENABLE_WAIT_MAX_LOOPS; count > 0; count--) { + if (readl_relaxed(PLL_STATUS_REG(pllv)) & pllv->status_mask) + return 0; + udelay(1); + } + + WARN("PLL %s didn't enable after voting for it!\n", c->dbg_name); + + return -ETIMEDOUT; +} + +static void pll_vote_clk_disable(struct clk *c) +{ + u32 ena; + unsigned long flags; + struct pll_vote_clk *pllv = to_pll_vote_clk(c); + + spin_lock_irqsave(&pll_reg_lock, flags); + ena = readl_relaxed(PLL_EN_REG(pllv)); + ena &= ~(pllv->en_mask); + writel_relaxed(ena, PLL_EN_REG(pllv)); + spin_unlock_irqrestore(&pll_reg_lock, flags); +} + +static int pll_vote_clk_is_enabled(struct clk *c) +{ + struct pll_vote_clk *pllv = to_pll_vote_clk(c); + return !!(readl_relaxed(PLL_STATUS_REG(pllv)) & pllv->status_mask); +} + +static enum handoff pll_vote_clk_handoff(struct clk *c) +{ + struct pll_vote_clk *pllv = to_pll_vote_clk(c); + if (readl_relaxed(PLL_EN_REG(pllv)) & pllv->en_mask) + return HANDOFF_ENABLED_CLK; + + return HANDOFF_DISABLED_CLK; +} + +static void __iomem *pll_vote_clk_list_registers(struct clk *c, int n, + struct clk_register_data **regs, u32 *size) +{ + struct pll_vote_clk *pllv = to_pll_vote_clk(c); + static struct clk_register_data data1[] = { + {"APPS_VOTE", 0x0}, + }; + + if (n) + return ERR_PTR(-EINVAL); + + *regs = data1; + *size = ARRAY_SIZE(data1); + return PLL_EN_REG(pllv); +} + +struct clk_ops clk_ops_pll_vote = { + .enable = pll_vote_clk_enable, + .disable = pll_vote_clk_disable, + .is_enabled = pll_vote_clk_is_enabled, + .handoff = pll_vote_clk_handoff, + .list_registers = pll_vote_clk_list_registers, +}; + +/* + * spm_event() -- Set/Clear SPM events + * PLL off sequence -- enable (1) + * Set L2_SPM_FORCE_EVENT_EN[bit] register to 1 + * Set L2_SPM_FORCE_EVENT[bit] register to 1 + * PLL on sequence -- enable (0) + * Clear L2_SPM_FORCE_EVENT[bit] register to 0 + * Clear L2_SPM_FORCE_EVENT_EN[bit] register to 0 + */ +static void spm_event(void __iomem *base, u32 offset, u32 bit, + bool enable) +{ + uint32_t val; + + if (!base) + return; + + if (enable) { + /* L2_SPM_FORCE_EVENT_EN */ + val = readl_relaxed(base + offset); + val |= BIT(bit); + writel_relaxed(val, (base + offset)); + /* Ensure that the write above goes through. */ + mb(); + + /* L2_SPM_FORCE_EVENT */ + val = readl_relaxed(base + offset + SPM_FORCE_EVENT); + val |= BIT(bit); + writel_relaxed(val, (base + offset + SPM_FORCE_EVENT)); + /* Ensure that the write above goes through. */ + mb(); + } else { + /* L2_SPM_FORCE_EVENT */ + val = readl_relaxed(base + offset + SPM_FORCE_EVENT); + val &= ~BIT(bit); + writel_relaxed(val, (base + offset + SPM_FORCE_EVENT)); + /* Ensure that the write above goes through. */ + mb(); + + /* L2_SPM_FORCE_EVENT_EN */ + val = readl_relaxed(base + offset); + val &= ~BIT(bit); + writel_relaxed(val, (base + offset)); + /* Ensure that the write above goes through. */ + mb(); + } +} + +static void __pll_config_reg(void __iomem *pll_config, struct pll_freq_tbl *f, + struct pll_config_masks *masks) +{ + u32 regval; + + regval = readl_relaxed(pll_config); + + /* Enable the MN counter if used */ + if (f->m_val) + regval |= masks->mn_en_mask; + + /* Set pre-divider and post-divider values */ + regval &= ~masks->pre_div_mask; + regval |= f->pre_div_val; + regval &= ~masks->post_div_mask; + regval |= f->post_div_val; + + /* Select VCO setting */ + regval &= ~masks->vco_mask; + regval |= f->vco_val; + + /* Enable main output if it has not been enabled */ + if (masks->main_output_mask && !(regval & masks->main_output_mask)) + regval |= masks->main_output_mask; + + writel_relaxed(regval, pll_config); +} + +static int sr2_pll_clk_enable(struct clk *c) +{ + unsigned long flags; + struct pll_clk *pll = to_pll_clk(c); + int ret = 0, count; + u32 mode = readl_relaxed(PLL_MODE_REG(pll)); + u32 lockmask = pll->masks.lock_mask ?: PLL_LOCKED_BIT; + + spin_lock_irqsave(&pll_reg_lock, flags); + + spm_event(pll->spm_ctrl.spm_base, pll->spm_ctrl.offset, + pll->spm_ctrl.event_bit, false); + + /* Disable PLL bypass mode. */ + mode |= PLL_BYPASSNL; + writel_relaxed(mode, PLL_MODE_REG(pll)); + + /* + * H/W requires a 5us delay between disabling the bypass and + * de-asserting the reset. Delay 10us just to be safe. + */ + mb(); + udelay(10); + + /* De-assert active-low PLL reset. */ + mode |= PLL_RESET_N; + writel_relaxed(mode, PLL_MODE_REG(pll)); + + /* Wait for pll to lock. */ + for (count = ENABLE_WAIT_MAX_LOOPS; count > 0; count--) { + if (readl_relaxed(PLL_STATUS_REG(pll)) & lockmask) + break; + udelay(1); + } + + if (!(readl_relaxed(PLL_STATUS_REG(pll)) & lockmask)) + pr_err("PLL %s didn't lock after enabling it!\n", c->dbg_name); + + /* Enable PLL output. */ + mode |= PLL_OUTCTRL; + writel_relaxed(mode, PLL_MODE_REG(pll)); + + /* Ensure that the write above goes through before returning. */ + mb(); + + spin_unlock_irqrestore(&pll_reg_lock, flags); + return ret; +} + +void __variable_rate_pll_init(struct clk *c) +{ + struct pll_clk *pll = to_pll_clk(c); + u32 regval; + + regval = readl_relaxed(PLL_CONFIG_REG(pll)); + + if (pll->masks.post_div_mask) { + regval &= ~pll->masks.post_div_mask; + regval |= pll->vals.post_div_masked; + } + + if (pll->masks.pre_div_mask) { + regval &= ~pll->masks.pre_div_mask; + regval |= pll->vals.pre_div_masked; + } + + if (pll->masks.main_output_mask) + regval |= pll->masks.main_output_mask; + + if (pll->masks.early_output_mask) + regval |= pll->masks.early_output_mask; + + if (pll->vals.enable_mn) + regval |= pll->masks.mn_en_mask; + else + regval &= ~pll->masks.mn_en_mask; + + writel_relaxed(regval, PLL_CONFIG_REG(pll)); + + regval = readl_relaxed(PLL_MODE_REG(pll)); + if (pll->masks.apc_pdn_mask) + regval &= ~pll->masks.apc_pdn_mask; + writel_relaxed(regval, PLL_MODE_REG(pll)); + + writel_relaxed(pll->vals.alpha_val, PLL_ALPHA_REG(pll)); + writel_relaxed(pll->vals.config_ctl_val, PLL_CFG_CTL_REG(pll)); + if (pll->vals.config_ctl_hi_val) + writel_relaxed(pll->vals.config_ctl_hi_val, + PLL_CFG_CTL_HI_REG(pll)); + if (pll->init_test_ctl) { + writel_relaxed(pll->vals.test_ctl_lo_val, + PLL_TEST_CTL_LO_REG(pll)); + writel_relaxed(pll->vals.test_ctl_hi_val, + PLL_TEST_CTL_HI_REG(pll)); + } + + pll->inited = true; +} + +static int variable_rate_pll_clk_enable(struct clk *c) +{ + unsigned long flags; + struct pll_clk *pll = to_pll_clk(c); + int ret = 0, count; + u32 mode, testlo; + u32 lockmask = pll->masks.lock_mask ?: PLL_LOCKED_BIT; + u32 mode_lock; + u64 time; + bool early_lock = false; + + spin_lock_irqsave(&pll_reg_lock, flags); + + if (unlikely(!to_pll_clk(c)->inited)) + __variable_rate_pll_init(c); + + mode = readl_relaxed(PLL_MODE_REG(pll)); + + /* Set test control bits as required by HW doc */ + if (pll->test_ctl_lo_reg && pll->vals.test_ctl_lo_val && + pll->pgm_test_ctl_enable) + writel_relaxed(pll->vals.test_ctl_lo_val, + PLL_TEST_CTL_LO_REG(pll)); + + if (!pll->test_ctl_dbg) { + /* Enable test_ctl debug */ + mode |= BIT(3); + writel_relaxed(mode, PLL_MODE_REG(pll)); + + testlo = readl_relaxed(PLL_TEST_CTL_LO_REG(pll)); + testlo &= ~BM(7, 6); + testlo |= 0xC0; + writel_relaxed(testlo, PLL_TEST_CTL_LO_REG(pll)); + /* Wait for the write to complete */ + mb(); + } + + /* Disable PLL bypass mode. */ + mode |= PLL_BYPASSNL; + writel_relaxed(mode, PLL_MODE_REG(pll)); + + /* + * H/W requires a 5us delay between disabling the bypass and + * de-asserting the reset. Use 10us to be sure. + */ + mb(); + udelay(10); + + /* De-assert active-low PLL reset. */ + mode |= PLL_RESET_N; + writel_relaxed(mode, PLL_MODE_REG(pll)); + + /* + * 5us delay mandated by HPG. However, put in a 200us delay here. + * This is to address possible locking issues with the PLL exhibit + * early "transient" locks about 16us from this point. With this + * higher delay, we avoid running into those transients. + */ + mb(); + udelay(200); + + /* Clear test control bits */ + if (pll->test_ctl_lo_reg && pll->vals.test_ctl_lo_val && + pll->pgm_test_ctl_enable) + writel_relaxed(0x0, PLL_TEST_CTL_LO_REG(pll)); + + + time = sched_clock(); + /* Wait for pll to lock. */ + for (count = ENABLE_WAIT_MAX_LOOPS; count > 0; count--) { + if (readl_relaxed(PLL_STATUS_REG(pll)) & lockmask) { + udelay(1); + /* + * Check again to be sure. This is to avoid + * breaking too early if there is a "transient" + * lock. + */ + if ((readl_relaxed(PLL_STATUS_REG(pll)) & lockmask)) + break; + else + early_lock = true; + } + udelay(1); + } + time = sched_clock() - time; + + mode_lock = readl_relaxed(PLL_STATUS_REG(pll)); + + if (!(mode_lock & lockmask)) { + pr_err("PLL lock bit detection total wait time: %lld ns", time); + pr_err("PLL %s didn't lock after enabling for L value 0x%x!\n", + c->dbg_name, readl_relaxed(PLL_L_REG(pll))); + pr_err("mode register is 0x%x\n", + readl_relaxed(PLL_STATUS_REG(pll))); + pr_err("user control register is 0x%x\n", + readl_relaxed(PLL_CONFIG_REG(pll))); + pr_err("config control register is 0x%x\n", + readl_relaxed(PLL_CFG_CTL_REG(pll))); + pr_err("test control high register is 0x%x\n", + readl_relaxed(PLL_TEST_CTL_HI_REG(pll))); + pr_err("test control low register is 0x%x\n", + readl_relaxed(PLL_TEST_CTL_LO_REG(pll))); + pr_err("early lock? %s\n", early_lock ? "yes" : "no"); + + testlo = readl_relaxed(PLL_TEST_CTL_LO_REG(pll)); + testlo &= ~BM(7, 6); + writel_relaxed(testlo, PLL_TEST_CTL_LO_REG(pll)); + /* Wait for the write to complete */ + mb(); + + pr_err("test_ctl_lo = 0x%x, pll status is: 0x%x\n", + readl_relaxed(PLL_TEST_CTL_LO_REG(pll)), + readl_relaxed(PLL_ALT_STATUS_REG(pll))); + + testlo = readl_relaxed(PLL_TEST_CTL_LO_REG(pll)); + testlo &= ~BM(7, 6); + testlo |= 0x40; + writel_relaxed(testlo, PLL_TEST_CTL_LO_REG(pll)); + /* Wait for the write to complete */ + mb(); + pr_err("test_ctl_lo = 0x%x, pll status is: 0x%x\n", + readl_relaxed(PLL_TEST_CTL_LO_REG(pll)), + readl_relaxed(PLL_ALT_STATUS_REG(pll))); + + testlo = readl_relaxed(PLL_TEST_CTL_LO_REG(pll)); + testlo &= ~BM(7, 6); + testlo |= 0x80; + writel_relaxed(testlo, PLL_TEST_CTL_LO_REG(pll)); + /* Wait for the write to complete */ + mb(); + + pr_err("test_ctl_lo = 0x%x, pll status is: 0x%x\n", + readl_relaxed(PLL_TEST_CTL_LO_REG(pll)), + readl_relaxed(PLL_ALT_STATUS_REG(pll))); + + testlo = readl_relaxed(PLL_TEST_CTL_LO_REG(pll)); + testlo &= ~BM(7, 6); + testlo |= 0xC0; + writel_relaxed(testlo, PLL_TEST_CTL_LO_REG(pll)); + /* Wait for the write to complete */ + mb(); + + pr_err("test_ctl_lo = 0x%x, pll status is: 0x%x\n", + readl_relaxed(PLL_TEST_CTL_LO_REG(pll)), + readl_relaxed(PLL_ALT_STATUS_REG(pll))); + panic("failed to lock %s PLL\n", c->dbg_name); + } + + /* Enable PLL output. */ + mode |= PLL_OUTCTRL; + writel_relaxed(mode, PLL_MODE_REG(pll)); + + /* Ensure that the write above goes through before returning. */ + mb(); + + spin_unlock_irqrestore(&pll_reg_lock, flags); + + return ret; +} + +static void variable_rate_pll_clk_disable_hwfsm(struct clk *c) +{ + struct pll_clk *pll = to_pll_clk(c); + u32 regval; + + /* Set test control bit to stay-in-CFA if necessary */ + if (pll->test_ctl_lo_reg && pll->pgm_test_ctl_enable) { + regval = readl_relaxed(PLL_TEST_CTL_LO_REG(pll)); + writel_relaxed(regval | BIT(16), + PLL_TEST_CTL_LO_REG(pll)); + } + + /* 8 reference clock cycle delay mandated by the HPG */ + udelay(1); +} + +static int variable_rate_pll_clk_enable_hwfsm(struct clk *c) +{ + struct pll_clk *pll = to_pll_clk(c); + int count; + u32 lockmask = pll->masks.lock_mask ?: PLL_LOCKED_BIT; + unsigned long flags; + u32 regval; + + spin_lock_irqsave(&pll_reg_lock, flags); + + /* Clear test control bit if necessary */ + if (pll->test_ctl_lo_reg && pll->pgm_test_ctl_enable) { + regval = readl_relaxed(PLL_TEST_CTL_LO_REG(pll)); + regval &= ~BIT(16); + writel_relaxed(regval, PLL_TEST_CTL_LO_REG(pll)); + } + + /* Wait for 50us explicitly to avoid transient locks */ + udelay(50); + + for (count = ENABLE_WAIT_MAX_LOOPS; count > 0; count--) { + if (readl_relaxed(PLL_STATUS_REG(pll)) & lockmask) + break; + udelay(1); + } + + if (!(readl_relaxed(PLL_STATUS_REG(pll)) & lockmask)) + pr_err("PLL %s didn't lock after enabling it!\n", c->dbg_name); + + spin_unlock_irqrestore(&pll_reg_lock, flags); + + return 0; +} + +static void __pll_clk_enable_reg(void __iomem *mode_reg) +{ + u32 mode = readl_relaxed(mode_reg); + /* Disable PLL bypass mode. */ + mode |= PLL_BYPASSNL; + writel_relaxed(mode, mode_reg); + + /* + * H/W requires a 5us delay between disabling the bypass and + * de-asserting the reset. Delay 10us just to be safe. + */ + mb(); + udelay(10); + + /* De-assert active-low PLL reset. */ + mode |= PLL_RESET_N; + writel_relaxed(mode, mode_reg); + + /* Wait until PLL is locked. */ + mb(); + udelay(50); + + /* Enable PLL output. */ + mode |= PLL_OUTCTRL; + writel_relaxed(mode, mode_reg); + + /* Ensure that the write above goes through before returning. */ + mb(); +} + +static int local_pll_clk_enable(struct clk *c) +{ + unsigned long flags; + struct pll_clk *pll = to_pll_clk(c); + + spin_lock_irqsave(&pll_reg_lock, flags); + __pll_clk_enable_reg(PLL_MODE_REG(pll)); + spin_unlock_irqrestore(&pll_reg_lock, flags); + + return 0; +} + +static void __pll_clk_disable_reg(void __iomem *mode_reg) +{ + u32 mode = readl_relaxed(mode_reg); + mode &= ~PLL_MODE_MASK; + writel_relaxed(mode, mode_reg); +} + +static void local_pll_clk_disable(struct clk *c) +{ + unsigned long flags; + struct pll_clk *pll = to_pll_clk(c); + + /* + * Disable the PLL output, disable test mode, enable + * the bypass mode, and assert the reset. + */ + spin_lock_irqsave(&pll_reg_lock, flags); + spm_event(pll->spm_ctrl.spm_base, pll->spm_ctrl.offset, + pll->spm_ctrl.event_bit, true); + __pll_clk_disable_reg(PLL_MODE_REG(pll)); + spin_unlock_irqrestore(&pll_reg_lock, flags); +} + +static enum handoff local_pll_clk_handoff(struct clk *c) +{ + struct pll_clk *pll = to_pll_clk(c); + u32 mode = readl_relaxed(PLL_MODE_REG(pll)); + u32 mask = PLL_BYPASSNL | PLL_RESET_N | PLL_OUTCTRL; + unsigned long parent_rate; + u32 lval, mval, nval, userval; + + if ((mode & mask) != mask) + return HANDOFF_DISABLED_CLK; + + /* Assume bootloaders configure PLL to c->rate */ + if (c->rate) + return HANDOFF_ENABLED_CLK; + + parent_rate = clk_get_rate(c->parent); + lval = readl_relaxed(PLL_L_REG(pll)); + mval = readl_relaxed(PLL_M_REG(pll)); + nval = readl_relaxed(PLL_N_REG(pll)); + userval = readl_relaxed(PLL_CONFIG_REG(pll)); + + c->rate = parent_rate * lval; + + if (pll->masks.mn_en_mask && userval) { + if (!nval) + nval = 1; + c->rate += (parent_rate * mval) / nval; + } + + return HANDOFF_ENABLED_CLK; +} + +static long local_pll_clk_round_rate(struct clk *c, unsigned long rate) +{ + struct pll_freq_tbl *nf; + struct pll_clk *pll = to_pll_clk(c); + + if (!pll->freq_tbl) + return -EINVAL; + + for (nf = pll->freq_tbl; nf->freq_hz != PLL_FREQ_END; nf++) + if (nf->freq_hz >= rate) + return nf->freq_hz; + + nf--; + return nf->freq_hz; +} + +static int local_pll_clk_set_rate(struct clk *c, unsigned long rate) +{ + struct pll_freq_tbl *nf; + struct pll_clk *pll = to_pll_clk(c); + unsigned long flags; + + for (nf = pll->freq_tbl; nf->freq_hz != PLL_FREQ_END + && nf->freq_hz != rate; nf++) + ; + + if (nf->freq_hz == PLL_FREQ_END) + return -EINVAL; + + /* + * Ensure PLL is off before changing rate. For optimization reasons, + * assume no downstream clock is using actively using it. + */ + spin_lock_irqsave(&c->lock, flags); + if (c->count) + c->ops->disable(c); + + writel_relaxed(nf->l_val, PLL_L_REG(pll)); + writel_relaxed(nf->m_val, PLL_M_REG(pll)); + writel_relaxed(nf->n_val, PLL_N_REG(pll)); + + __pll_config_reg(PLL_CONFIG_REG(pll), nf, &pll->masks); + + if (c->count) + c->ops->enable(c); + + spin_unlock_irqrestore(&c->lock, flags); + return 0; +} + +static enum handoff variable_rate_pll_handoff(struct clk *c) +{ + struct pll_clk *pll = to_pll_clk(c); + u32 mode = readl_relaxed(PLL_MODE_REG(pll)); + u32 mask = PLL_BYPASSNL | PLL_RESET_N | PLL_OUTCTRL; + u32 lval; + + pll->src_rate = clk_get_rate(c->parent); + + lval = readl_relaxed(PLL_L_REG(pll)); + if (!lval) + return HANDOFF_DISABLED_CLK; + + c->rate = pll->src_rate * lval; + + if (c->rate > pll->max_rate || c->rate < pll->min_rate) { + WARN(1, "%s: Out of spec PLL", c->dbg_name); + return HANDOFF_DISABLED_CLK; + } + + if ((mode & mask) != mask) + return HANDOFF_DISABLED_CLK; + + return HANDOFF_ENABLED_CLK; +} + +static long variable_rate_pll_round_rate(struct clk *c, unsigned long rate) +{ + struct pll_clk *pll = to_pll_clk(c); + + if (!pll->src_rate) + return 0; + + if (pll->no_prepared_reconfig && c->prepare_count && c->rate != rate) + return -EINVAL; + + if (rate < pll->min_rate) + rate = pll->min_rate; + if (rate > pll->max_rate) + rate = pll->max_rate; + + return min(pll->max_rate, + DIV_ROUND_UP(rate, pll->src_rate) * pll->src_rate); +} + +/* + * For optimization reasons, assumes no downstream clocks are actively using + * it. + */ +static int variable_rate_pll_set_rate(struct clk *c, unsigned long rate) +{ + struct pll_clk *pll = to_pll_clk(c); + unsigned long flags; + u32 l_val; + + if (rate != variable_rate_pll_round_rate(c, rate)) + return -EINVAL; + + l_val = rate / pll->src_rate; + + spin_lock_irqsave(&c->lock, flags); + + if (c->count && c->ops->disable) + c->ops->disable(c); + + writel_relaxed(l_val, PLL_L_REG(pll)); + + if (c->count && c->ops->enable) + c->ops->enable(c); + + spin_unlock_irqrestore(&c->lock, flags); + + return 0; +} + +int sr_pll_clk_enable(struct clk *c) +{ + u32 mode; + unsigned long flags; + struct pll_clk *pll = to_pll_clk(c); + + spin_lock_irqsave(&pll_reg_lock, flags); + mode = readl_relaxed(PLL_MODE_REG(pll)); + /* De-assert active-low PLL reset. */ + mode |= PLL_RESET_N; + writel_relaxed(mode, PLL_MODE_REG(pll)); + + /* + * H/W requires a 5us delay between disabling the bypass and + * de-asserting the reset. Delay 10us just to be safe. + */ + mb(); + udelay(10); + + /* Disable PLL bypass mode. */ + mode |= PLL_BYPASSNL; + writel_relaxed(mode, PLL_MODE_REG(pll)); + + /* Wait until PLL is locked. */ + mb(); + udelay(60); + + /* Enable PLL output. */ + mode |= PLL_OUTCTRL; + writel_relaxed(mode, PLL_MODE_REG(pll)); + + /* Ensure that the write above goes through before returning. */ + mb(); + + spin_unlock_irqrestore(&pll_reg_lock, flags); + + return 0; +} + +int sr_hpm_lp_pll_clk_enable(struct clk *c) +{ + unsigned long flags; + struct pll_clk *pll = to_pll_clk(c); + u32 count, mode; + int ret = 0; + + spin_lock_irqsave(&pll_reg_lock, flags); + + /* Disable PLL bypass mode and de-assert reset. */ + mode = PLL_BYPASSNL | PLL_RESET_N; + writel_relaxed(mode, PLL_MODE_REG(pll)); + + /* Wait for pll to lock. */ + for (count = ENABLE_WAIT_MAX_LOOPS; count > 0; count--) { + if (readl_relaxed(PLL_STATUS_REG(pll)) & PLL_LOCKED_BIT) + break; + udelay(1); + } + + if (!(readl_relaxed(PLL_STATUS_REG(pll)) & PLL_LOCKED_BIT)) { + WARN("PLL %s didn't lock after enabling it!\n", c->dbg_name); + ret = -ETIMEDOUT; + goto out; + } + + /* Enable PLL output. */ + mode |= PLL_OUTCTRL; + writel_relaxed(mode, PLL_MODE_REG(pll)); + + /* Ensure the write above goes through before returning. */ + mb(); + +out: + spin_unlock_irqrestore(&pll_reg_lock, flags); + return ret; +} + + +static void __iomem *variable_rate_pll_list_registers(struct clk *c, int n, + struct clk_register_data **regs, u32 *size) +{ + struct pll_clk *pll = to_pll_clk(c); + static struct clk_register_data data[] = { + {"MODE", 0x0}, + {"L", 0x4}, + {"ALPHA", 0x8}, + {"USER_CTL", 0x10}, + {"CONFIG_CTL", 0x14}, + {"STATUS", 0x1C}, + }; + if (n) + return ERR_PTR(-EINVAL); + + *regs = data; + *size = ARRAY_SIZE(data); + return PLL_MODE_REG(pll); +} + +static void __iomem *local_pll_clk_list_registers(struct clk *c, int n, + struct clk_register_data **regs, u32 *size) +{ + /* Not compatible with 8960 & friends */ + struct pll_clk *pll = to_pll_clk(c); + static struct clk_register_data data[] = { + {"MODE", 0x0}, + {"L", 0x4}, + {"M", 0x8}, + {"N", 0xC}, + {"USER", 0x10}, + {"CONFIG", 0x14}, + {"STATUS", 0x1C}, + }; + if (n) + return ERR_PTR(-EINVAL); + + *regs = data; + *size = ARRAY_SIZE(data); + return PLL_MODE_REG(pll); +} + + +struct clk_ops clk_ops_local_pll = { + .enable = local_pll_clk_enable, + .disable = local_pll_clk_disable, + .set_rate = local_pll_clk_set_rate, + .handoff = local_pll_clk_handoff, + .list_registers = local_pll_clk_list_registers, +}; + +struct clk_ops clk_ops_sr2_pll = { + .enable = sr2_pll_clk_enable, + .disable = local_pll_clk_disable, + .set_rate = local_pll_clk_set_rate, + .round_rate = local_pll_clk_round_rate, + .handoff = local_pll_clk_handoff, + .list_registers = local_pll_clk_list_registers, +}; + +struct clk_ops clk_ops_variable_rate_pll_hwfsm = { + .enable = variable_rate_pll_clk_enable_hwfsm, + .disable = variable_rate_pll_clk_disable_hwfsm, + .set_rate = variable_rate_pll_set_rate, + .round_rate = variable_rate_pll_round_rate, + .handoff = variable_rate_pll_handoff, +}; + +struct clk_ops clk_ops_variable_rate_pll = { + .enable = variable_rate_pll_clk_enable, + .disable = local_pll_clk_disable, + .set_rate = variable_rate_pll_set_rate, + .round_rate = variable_rate_pll_round_rate, + .handoff = variable_rate_pll_handoff, + .list_registers = variable_rate_pll_list_registers, +}; + +static DEFINE_SPINLOCK(soft_vote_lock); + +static int pll_acpu_vote_clk_enable(struct clk *c) +{ + int ret = 0; + unsigned long flags; + struct pll_vote_clk *pllv = to_pll_vote_clk(c); + + spin_lock_irqsave(&soft_vote_lock, flags); + + if (!*pllv->soft_vote) + ret = pll_vote_clk_enable(c); + if (ret == 0) + *pllv->soft_vote |= (pllv->soft_vote_mask); + + spin_unlock_irqrestore(&soft_vote_lock, flags); + return ret; +} + +static void pll_acpu_vote_clk_disable(struct clk *c) +{ + unsigned long flags; + struct pll_vote_clk *pllv = to_pll_vote_clk(c); + + spin_lock_irqsave(&soft_vote_lock, flags); + + *pllv->soft_vote &= ~(pllv->soft_vote_mask); + if (!*pllv->soft_vote) + pll_vote_clk_disable(c); + + spin_unlock_irqrestore(&soft_vote_lock, flags); +} + +static enum handoff pll_acpu_vote_clk_handoff(struct clk *c) +{ + if (pll_vote_clk_handoff(c) == HANDOFF_DISABLED_CLK) + return HANDOFF_DISABLED_CLK; + + if (pll_acpu_vote_clk_enable(c)) + return HANDOFF_DISABLED_CLK; + + return HANDOFF_ENABLED_CLK; +} + +struct clk_ops clk_ops_pll_acpu_vote = { + .enable = pll_acpu_vote_clk_enable, + .disable = pll_acpu_vote_clk_disable, + .is_enabled = pll_vote_clk_is_enabled, + .handoff = pll_acpu_vote_clk_handoff, + .list_registers = pll_vote_clk_list_registers, +}; + + +static int pll_sleep_clk_enable(struct clk *c) +{ + u32 ena; + unsigned long flags; + struct pll_vote_clk *pllv = to_pll_vote_clk(c); + + spin_lock_irqsave(&pll_reg_lock, flags); + ena = readl_relaxed(PLL_EN_REG(pllv)); + ena &= ~(pllv->en_mask); + writel_relaxed(ena, PLL_EN_REG(pllv)); + spin_unlock_irqrestore(&pll_reg_lock, flags); + return 0; +} + +static void pll_sleep_clk_disable(struct clk *c) +{ + u32 ena; + unsigned long flags; + struct pll_vote_clk *pllv = to_pll_vote_clk(c); + + spin_lock_irqsave(&pll_reg_lock, flags); + ena = readl_relaxed(PLL_EN_REG(pllv)); + ena |= pllv->en_mask; + writel_relaxed(ena, PLL_EN_REG(pllv)); + spin_unlock_irqrestore(&pll_reg_lock, flags); +} + +static enum handoff pll_sleep_clk_handoff(struct clk *c) +{ + struct pll_vote_clk *pllv = to_pll_vote_clk(c); + + if (!(readl_relaxed(PLL_EN_REG(pllv)) & pllv->en_mask)) + return HANDOFF_ENABLED_CLK; + + return HANDOFF_DISABLED_CLK; +} + +/* + * This .ops is meant to be used by gpll0_sleep_clk_src. The aim is to utilise + * the h/w feature of sleep enable bit to denote if the PLL can be turned OFF + * once APPS goes to PC. gpll0_sleep_clk_src will be enabled only if there is a + * peripheral client using it and disabled if there is none. The current + * implementation of enable .ops clears the h/w bit of sleep enable while the + * disable .ops asserts it. + */ + +struct clk_ops clk_ops_pll_sleep_vote = { + .enable = pll_sleep_clk_enable, + .disable = pll_sleep_clk_disable, + .handoff = pll_sleep_clk_handoff, + .list_registers = pll_vote_clk_list_registers, +}; + +static void __set_fsm_mode(void __iomem *mode_reg, + u32 bias_count, u32 lock_count) +{ + u32 regval = readl_relaxed(mode_reg); + + /* De-assert reset to FSM */ + regval &= ~BIT(21); + writel_relaxed(regval, mode_reg); + + /* Program bias count */ + regval &= ~BM(19, 14); + regval |= BVAL(19, 14, bias_count); + writel_relaxed(regval, mode_reg); + + /* Program lock count */ + regval &= ~BM(13, 8); + regval |= BVAL(13, 8, lock_count); + writel_relaxed(regval, mode_reg); + + /* Enable PLL FSM voting */ + regval |= BIT(20); + writel_relaxed(regval, mode_reg); +} + +static void __configure_alt_config(struct pll_alt_config config, + struct pll_config_regs *regs) +{ + u32 regval; + + regval = readl_relaxed(PLL_CFG_ALT_REG(regs)); + + if (config.mask) { + regval &= ~config.mask; + regval |= config.val; + } + + writel_relaxed(regval, PLL_CFG_ALT_REG(regs)); +} + +void __configure_pll(struct pll_config *config, + struct pll_config_regs *regs, u32 ena_fsm_mode) +{ + u32 regval; + + writel_relaxed(config->l, PLL_L_REG(regs)); + writel_relaxed(config->m, PLL_M_REG(regs)); + writel_relaxed(config->n, PLL_N_REG(regs)); + + regval = readl_relaxed(PLL_CONFIG_REG(regs)); + + /* Enable the MN accumulator */ + if (config->mn_ena_mask) { + regval &= ~config->mn_ena_mask; + regval |= config->mn_ena_val; + } + + /* Enable the main output */ + if (config->main_output_mask) { + regval &= ~config->main_output_mask; + regval |= config->main_output_val; + } + + /* Enable the aux output */ + if (config->aux_output_mask) { + regval &= ~config->aux_output_mask; + regval |= config->aux_output_val; + } + + /* Set pre-divider and post-divider values */ + regval &= ~config->pre_div_mask; + regval |= config->pre_div_val; + regval &= ~config->post_div_mask; + regval |= config->post_div_val; + + /* Select VCO setting */ + regval &= ~config->vco_mask; + regval |= config->vco_val; + + if (config->add_factor_mask) { + regval &= ~config->add_factor_mask; + regval |= config->add_factor_val; + } + + writel_relaxed(regval, PLL_CONFIG_REG(regs)); + + if (regs->config_alt_reg) + __configure_alt_config(config->alt_cfg, regs); + + if (regs->config_ctl_reg) + writel_relaxed(config->cfg_ctl_val, PLL_CFG_CTL_REG(regs)); +} + +void configure_sr_pll(struct pll_config *config, + struct pll_config_regs *regs, u32 ena_fsm_mode) +{ + __configure_pll(config, regs, ena_fsm_mode); + if (ena_fsm_mode) + __set_fsm_mode(PLL_MODE_REG(regs), 0x1, 0x8); +} + +void configure_sr_hpm_lp_pll(struct pll_config *config, + struct pll_config_regs *regs, u32 ena_fsm_mode) +{ + __configure_pll(config, regs, ena_fsm_mode); + if (ena_fsm_mode) + __set_fsm_mode(PLL_MODE_REG(regs), 0x1, 0x0); +} + +static void *votable_pll_clk_dt_parser(struct device *dev, + struct device_node *np) +{ + struct pll_vote_clk *v, *peer; + struct clk *c; + u32 val, rc; + phandle p; + struct msmclk_data *drv; + + v = devm_kzalloc(dev, sizeof(*v), GFP_KERNEL); + if (!v) { + dt_err(np, "memory alloc failure\n"); + return ERR_PTR(-ENOMEM); + } + + drv = msmclk_parse_phandle(dev, np->parent->phandle); + if (IS_ERR_OR_NULL(drv)) + return ERR_CAST(drv); + v->base = &drv->base; + + rc = of_property_read_u32(np, "qcom,en-offset", (u32 *)&v->en_reg); + if (rc) { + dt_err(np, "missing qcom,en-offset dt property\n"); + return ERR_PTR(-EINVAL); + } + + rc = of_property_read_u32(np, "qcom,en-bit", &val); + if (rc) { + dt_err(np, "missing qcom,en-bit dt property\n"); + return ERR_PTR(-EINVAL); + } + v->en_mask = BIT(val); + + rc = of_property_read_u32(np, "qcom,status-offset", + (u32 *)&v->status_reg); + if (rc) { + dt_err(np, "missing qcom,status-offset dt property\n"); + return ERR_PTR(-EINVAL); + } + + rc = of_property_read_u32(np, "qcom,status-bit", &val); + if (rc) { + dt_err(np, "missing qcom,status-bit dt property\n"); + return ERR_PTR(-EINVAL); + } + v->status_mask = BIT(val); + + rc = of_property_read_u32(np, "qcom,pll-config-rate", &val); + if (rc) { + dt_err(np, "missing qcom,pll-config-rate dt property\n"); + return ERR_PTR(-EINVAL); + } + v->c.rate = val; + + if (of_device_is_compatible(np, "qcom,active-only-pll")) + v->soft_vote_mask = PLL_SOFT_VOTE_ACPU; + else if (of_device_is_compatible(np, "qcom,sleep-active-pll")) + v->soft_vote_mask = PLL_SOFT_VOTE_PRIMARY; + + if (of_device_is_compatible(np, "qcom,votable-pll")) { + v->c.ops = &clk_ops_pll_vote; + return msmclk_generic_clk_init(dev, np, &v->c); + } + + rc = of_property_read_phandle_index(np, "qcom,peer", 0, &p); + if (rc) { + dt_err(np, "missing qcom,peer dt property\n"); + return ERR_PTR(-EINVAL); + } + + c = msmclk_lookup_phandle(dev, p); + if (!IS_ERR_OR_NULL(c)) { + v->soft_vote = devm_kzalloc(dev, sizeof(*v->soft_vote), + GFP_KERNEL); + if (!v->soft_vote) { + dt_err(np, "memory alloc failure\n"); + return ERR_PTR(-ENOMEM); + } + + peer = to_pll_vote_clk(c); + peer->soft_vote = v->soft_vote; + } + + v->c.ops = &clk_ops_pll_acpu_vote; + return msmclk_generic_clk_init(dev, np, &v->c); +} +MSMCLK_PARSER(votable_pll_clk_dt_parser, "qcom,active-only-pll", 0); +MSMCLK_PARSER(votable_pll_clk_dt_parser, "qcom,sleep-active-pll", 1); +MSMCLK_PARSER(votable_pll_clk_dt_parser, "qcom,votable-pll", 2); diff -Nruw linux-4.4.115-fbx/drivers/clk/msm./clock-rpm.c linux-4.4.115-fbx/drivers/clk/msm/clock-rpm.c --- linux-4.4.115-fbx/drivers/clk/msm./clock-rpm.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-4.4.115-fbx/drivers/clk/msm/clock-rpm.c 2019-01-22 16:16:23.019242024 +0100 @@ -0,0 +1,472 @@ +/* Copyright (c) 2010-2015, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#define pr_fmt(fmt) "%s: " fmt, __func__ + +#include +#include +#include +#include +#include + +#define __clk_rpmrs_set_rate(r, value, ctx) \ + ((r)->rpmrs_data->set_rate_fn((r), (value), (ctx))) + +#define clk_rpmrs_set_rate_sleep(r, value) \ + __clk_rpmrs_set_rate((r), (value), (r)->rpmrs_data->ctx_sleep_id) + +#define clk_rpmrs_set_rate_active(r, value) \ + __clk_rpmrs_set_rate((r), (value), (r)->rpmrs_data->ctx_active_id) + +static int clk_rpmrs_set_rate_smd(struct rpm_clk *r, uint32_t value, + uint32_t context) +{ + int ret; + + struct msm_rpm_kvp kvp = { + .key = r->rpm_key, + .data = (void *)&value, + .length = sizeof(value), + }; + + switch (context) { + case MSM_RPM_CTX_ACTIVE_SET: + if (*r->last_active_set_vote == value) + return 0; + break; + case MSM_RPM_CTX_SLEEP_SET: + if (*r->last_sleep_set_vote == value) + return 0; + break; + default: + return -EINVAL; + }; + + ret = msm_rpm_send_message(context, r->rpm_res_type, r->rpm_clk_id, + &kvp, 1); + if (ret) + return ret; + + switch (context) { + case MSM_RPM_CTX_ACTIVE_SET: + *r->last_active_set_vote = value; + break; + case MSM_RPM_CTX_SLEEP_SET: + *r->last_sleep_set_vote = value; + break; + } + + return 0; +} + +static int clk_rpmrs_handoff_smd(struct rpm_clk *r) +{ + if (!r->branch) + r->c.rate = INT_MAX; + + return 0; +} + +static int clk_rpmrs_is_enabled_smd(struct rpm_clk *r) +{ + return !!r->c.prepare_count; +} + +struct clk_rpmrs_data { + int (*set_rate_fn)(struct rpm_clk *r, uint32_t value, uint32_t context); + int (*get_rate_fn)(struct rpm_clk *r); + int (*handoff_fn)(struct rpm_clk *r); + int (*is_enabled)(struct rpm_clk *r); + int ctx_active_id; + int ctx_sleep_id; +}; + +struct clk_rpmrs_data clk_rpmrs_data_smd = { + .set_rate_fn = clk_rpmrs_set_rate_smd, + .handoff_fn = clk_rpmrs_handoff_smd, + .is_enabled = clk_rpmrs_is_enabled_smd, + .ctx_active_id = MSM_RPM_CTX_ACTIVE_SET, + .ctx_sleep_id = MSM_RPM_CTX_SLEEP_SET, +}; + +static DEFINE_RT_MUTEX(rpm_clock_lock); + +static void to_active_sleep_khz(struct rpm_clk *r, unsigned long rate, + unsigned long *active_khz, unsigned long *sleep_khz) +{ + /* Convert the rate (hz) to khz */ + *active_khz = DIV_ROUND_UP(rate, 1000); + + /* + * Active-only clocks don't care what the rate is during sleep. So, + * they vote for zero. + */ + if (r->active_only) + *sleep_khz = 0; + else + *sleep_khz = *active_khz; +} + +static int rpm_clk_prepare(struct clk *clk) +{ + struct rpm_clk *r = to_rpm_clk(clk); + uint32_t value; + int rc = 0; + unsigned long this_khz, this_sleep_khz; + unsigned long peer_khz = 0, peer_sleep_khz = 0; + struct rpm_clk *peer = r->peer; + + rt_mutex_lock(&rpm_clock_lock); + + to_active_sleep_khz(r, r->c.rate, &this_khz, &this_sleep_khz); + + /* Don't send requests to the RPM if the rate has not been set. */ + if (this_khz == 0) + goto out; + + /* Take peer clock's rate into account only if it's enabled. */ + if (peer->enabled) + to_active_sleep_khz(peer, peer->c.rate, + &peer_khz, &peer_sleep_khz); + + value = max(this_khz, peer_khz); + if (r->branch) + value = !!value; + + rc = clk_rpmrs_set_rate_active(r, value); + if (rc) + goto out; + + value = max(this_sleep_khz, peer_sleep_khz); + if (r->branch) + value = !!value; + + rc = clk_rpmrs_set_rate_sleep(r, value); + if (rc) { + /* Undo the active set vote and restore it to peer_khz */ + value = peer_khz; + rc = clk_rpmrs_set_rate_active(r, value); + } + +out: + if (!rc) + r->enabled = true; + + rt_mutex_unlock(&rpm_clock_lock); + + return rc; +} + +static void rpm_clk_unprepare(struct clk *clk) +{ + struct rpm_clk *r = to_rpm_clk(clk); + + rt_mutex_lock(&rpm_clock_lock); + + if (r->c.rate) { + uint32_t value; + struct rpm_clk *peer = r->peer; + unsigned long peer_khz = 0, peer_sleep_khz = 0; + int rc; + + /* Take peer clock's rate into account only if it's enabled. */ + if (peer->enabled) + to_active_sleep_khz(peer, peer->c.rate, + &peer_khz, &peer_sleep_khz); + + value = r->branch ? !!peer_khz : peer_khz; + rc = clk_rpmrs_set_rate_active(r, value); + if (rc) + goto out; + + value = r->branch ? !!peer_sleep_khz : peer_sleep_khz; + rc = clk_rpmrs_set_rate_sleep(r, value); + } + r->enabled = false; +out: + rt_mutex_unlock(&rpm_clock_lock); + + return; +} + +static int rpm_clk_set_rate(struct clk *clk, unsigned long rate) +{ + struct rpm_clk *r = to_rpm_clk(clk); + unsigned long this_khz, this_sleep_khz; + int rc = 0; + + rt_mutex_lock(&rpm_clock_lock); + + if (r->enabled) { + uint32_t value; + struct rpm_clk *peer = r->peer; + unsigned long peer_khz = 0, peer_sleep_khz = 0; + + to_active_sleep_khz(r, rate, &this_khz, &this_sleep_khz); + + /* Take peer clock's rate into account only if it's enabled. */ + if (peer->enabled) + to_active_sleep_khz(peer, peer->c.rate, + &peer_khz, &peer_sleep_khz); + + value = max(this_khz, peer_khz); + rc = clk_rpmrs_set_rate_active(r, value); + if (rc) + goto out; + + value = max(this_sleep_khz, peer_sleep_khz); + rc = clk_rpmrs_set_rate_sleep(r, value); + } + +out: + rt_mutex_unlock(&rpm_clock_lock); + + return rc; +} + +static unsigned long rpm_clk_get_rate(struct clk *clk) +{ + struct rpm_clk *r = to_rpm_clk(clk); + if (r->rpmrs_data->get_rate_fn) + return r->rpmrs_data->get_rate_fn(r); + else + return clk->rate; +} + +static int rpm_clk_is_enabled(struct clk *clk) +{ + struct rpm_clk *r = to_rpm_clk(clk); + return r->rpmrs_data->is_enabled(r); +} + +static long rpm_clk_round_rate(struct clk *clk, unsigned long rate) +{ + /* Not supported. */ + return rate; +} + +static bool rpm_clk_is_local(struct clk *clk) +{ + return false; +} + +static enum handoff rpm_clk_handoff(struct clk *clk) +{ + struct rpm_clk *r = to_rpm_clk(clk); + int rc; + + /* + * Querying an RPM clock's status will return 0 unless the clock's + * rate has previously been set through the RPM. When handing off, + * assume these clocks are enabled (unless the RPM call fails) so + * child clocks of these RPM clocks can still be handed off. + */ + rc = r->rpmrs_data->handoff_fn(r); + if (rc < 0) + return HANDOFF_DISABLED_CLK; + + /* + * Since RPM handoff code may update the software rate of the clock by + * querying the RPM, we need to make sure our request to RPM now + * matches the software rate of the clock. When we send the request + * to RPM, we also need to update any other state info we would + * normally update. So, call the appropriate clock function instead + * of directly using the RPM driver APIs. + */ + rc = rpm_clk_prepare(clk); + if (rc < 0) + return HANDOFF_DISABLED_CLK; + + return HANDOFF_ENABLED_CLK; +} + +#define RPM_MISC_CLK_TYPE 0x306b6c63 +#define RPM_SCALING_ENABLE_ID 0x2 + +int enable_rpm_scaling(void) +{ + int rc, value = 0x1; + static int is_inited; + + struct msm_rpm_kvp kvp = { + .key = RPM_SMD_KEY_ENABLE, + .data = (void *)&value, + .length = sizeof(value), + }; + + if (is_inited) + return 0; + + rc = msm_rpm_send_message_noirq(MSM_RPM_CTX_SLEEP_SET, + RPM_MISC_CLK_TYPE, RPM_SCALING_ENABLE_ID, &kvp, 1); + if (rc < 0) { + if (rc != -EPROBE_DEFER) + WARN(1, "RPM clock scaling (sleep set) did not enable!\n"); + return rc; + } + + rc = msm_rpm_send_message_noirq(MSM_RPM_CTX_ACTIVE_SET, + RPM_MISC_CLK_TYPE, RPM_SCALING_ENABLE_ID, &kvp, 1); + if (rc < 0) { + if (rc != -EPROBE_DEFER) + WARN(1, "RPM clock scaling (active set) did not enable!\n"); + return rc; + } + + is_inited++; + return 0; +} + +int vote_bimc(struct rpm_clk *r, uint32_t value) +{ + int rc; + + struct msm_rpm_kvp kvp = { + .key = r->rpm_key, + .data = (void *)&value, + .length = sizeof(value), + }; + + rc = msm_rpm_send_message_noirq(MSM_RPM_CTX_ACTIVE_SET, + r->rpm_res_type, r->rpmrs_data->ctx_active_id, + &kvp, 1); + if (rc < 0) { + if (rc != -EPROBE_DEFER) + WARN(1, "BIMC vote not sent!\n"); + return rc; + } + + return rc; +} + +struct clk_ops clk_ops_rpm = { + .prepare = rpm_clk_prepare, + .unprepare = rpm_clk_unprepare, + .set_rate = rpm_clk_set_rate, + .get_rate = rpm_clk_get_rate, + .is_enabled = rpm_clk_is_enabled, + .round_rate = rpm_clk_round_rate, + .is_local = rpm_clk_is_local, + .handoff = rpm_clk_handoff, +}; + +struct clk_ops clk_ops_rpm_branch = { + .prepare = rpm_clk_prepare, + .unprepare = rpm_clk_unprepare, + .is_local = rpm_clk_is_local, + .handoff = rpm_clk_handoff, +}; + +static struct rpm_clk *rpm_clk_dt_parser_common(struct device *dev, + struct device_node *np) +{ + struct rpm_clk *rpm, *peer; + struct clk *c; + int rc = 0; + phandle p; + const char *str; + + rpm = devm_kzalloc(dev, sizeof(*rpm), GFP_KERNEL); + if (!rpm) { + dt_err(np, "memory alloc failure\n"); + return ERR_PTR(-ENOMEM); + } + + rc = of_property_read_phandle_index(np, "qcom,rpm-peer", 0, &p); + if (rc) { + dt_err(np, "missing qcom,rpm-peer dt property\n"); + return ERR_PTR(rc); + } + + /* Rely on whoever's called last to setup the circular ref */ + c = msmclk_lookup_phandle(dev, p); + if (!IS_ERR(c)) { + uint32_t *sleep = devm_kzalloc(dev, sizeof(uint32_t), + GFP_KERNEL); + uint32_t *active = + devm_kzalloc(dev, sizeof(uint32_t), + GFP_KERNEL); + + if (!sleep || !active) + return ERR_PTR(-ENOMEM); + peer = to_rpm_clk(c); + peer->peer = rpm; + rpm->peer = peer; + rpm->last_active_set_vote = active; + peer->last_active_set_vote = active; + rpm->last_sleep_set_vote = sleep; + peer->last_sleep_set_vote = sleep; + } + + rpm->rpmrs_data = &clk_rpmrs_data_smd; + rpm->active_only = of_device_is_compatible(np, "qcom,rpm-a-clk") || + of_device_is_compatible(np, "qcom,rpm-branch-a-clk"); + + rc = of_property_read_string(np, "qcom,res-type", &str); + if (rc) { + dt_err(np, "missing qcom,res-type dt property\n"); + return ERR_PTR(rc); + } + if (sscanf(str, "%4c", (char *) &rpm->rpm_res_type) <= 0) + return ERR_PTR(-EINVAL); + + rc = of_property_read_u32(np, "qcom,res-id", &rpm->rpm_clk_id); + if (rc) { + dt_err(np, "missing qcom,res-id dt property\n"); + return ERR_PTR(rc); + } + + rc = of_property_read_string(np, "qcom,key", &str); + if (rc) { + dt_err(np, "missing qcom,key dt property\n"); + return ERR_PTR(rc); + } + if (sscanf(str, "%4c", (char *) &rpm->rpm_key) <= 0) + return ERR_PTR(-EINVAL); + return rpm; +} + +static void *rpm_clk_dt_parser(struct device *dev, struct device_node *np) +{ + struct rpm_clk *rpm; + rpm = rpm_clk_dt_parser_common(dev, np); + if (IS_ERR(rpm)) + return rpm; + + rpm->c.ops = &clk_ops_rpm; + return msmclk_generic_clk_init(dev, np, &rpm->c); +} + +static void *rpm_branch_clk_dt_parser(struct device *dev, + struct device_node *np) +{ + struct rpm_clk *rpm; + u32 rate; + int rc; + rpm = rpm_clk_dt_parser_common(dev, np); + if (IS_ERR(rpm)) + return rpm; + + rpm->c.ops = &clk_ops_rpm_branch; + rpm->branch = true; + + rc = of_property_read_u32(np, "qcom,rcg-init-rate", &rate); + if (!rc) + rpm->c.rate = rate; + + return msmclk_generic_clk_init(dev, np, &rpm->c); +} +MSMCLK_PARSER(rpm_clk_dt_parser, "qcom,rpm-clk", 0); +MSMCLK_PARSER(rpm_clk_dt_parser, "qcom,rpm-a-clk", 1); +MSMCLK_PARSER(rpm_branch_clk_dt_parser, "qcom,rpm-branch-clk", 0); +MSMCLK_PARSER(rpm_branch_clk_dt_parser, "qcom,rpm-branch-a-clk", 1); diff -Nruw linux-4.4.115-fbx/drivers/clk/msm./clock-voter.c linux-4.4.115-fbx/drivers/clk/msm/clock-voter.c --- linux-4.4.115-fbx/drivers/clk/msm./clock-voter.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-4.4.115-fbx/drivers/clk/msm/clock-voter.c 2019-01-22 16:16:23.019242024 +0100 @@ -0,0 +1,202 @@ +/* Copyright (c) 2010-2015, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define pr_fmt(fmt) "%s: " fmt, __func__ + +#include +#include +#include +#include +#include +#include + +static DEFINE_RT_MUTEX(voter_clk_lock); + +/* Aggregate the rate of clocks that are currently on. */ +static unsigned long voter_clk_aggregate_rate(const struct clk *parent) +{ + struct clk *clk; + unsigned long rate = 0; + + list_for_each_entry(clk, &parent->children, siblings) { + struct clk_voter *v = to_clk_voter(clk); + if (v->enabled) + rate = max(clk->rate, rate); + } + return rate; +} + +static int voter_clk_set_rate(struct clk *clk, unsigned long rate) +{ + int ret = 0; + struct clk *clkp; + struct clk_voter *clkh, *v = to_clk_voter(clk); + unsigned long cur_rate, new_rate, other_rate = 0; + + if (v->is_branch) + return 0; + + rt_mutex_lock(&voter_clk_lock); + + if (v->enabled) { + struct clk *parent = clk->parent; + + /* + * Get the aggregate rate without this clock's vote and update + * if the new rate is different than the current rate + */ + list_for_each_entry(clkp, &parent->children, siblings) { + clkh = to_clk_voter(clkp); + if (clkh->enabled && clkh != v) + other_rate = max(clkp->rate, other_rate); + } + + cur_rate = max(other_rate, clk->rate); + new_rate = max(other_rate, rate); + + if (new_rate != cur_rate) { + ret = clk_set_rate(parent, new_rate); + if (ret) + goto unlock; + } + } + clk->rate = rate; +unlock: + rt_mutex_unlock(&voter_clk_lock); + + return ret; +} + +static int voter_clk_prepare(struct clk *clk) +{ + int ret = 0; + unsigned long cur_rate; + struct clk *parent; + struct clk_voter *v = to_clk_voter(clk); + + rt_mutex_lock(&voter_clk_lock); + parent = clk->parent; + + if (v->is_branch) { + v->enabled = true; + goto out; + } + + /* + * Increase the rate if this clock is voting for a higher rate + * than the current rate. + */ + cur_rate = voter_clk_aggregate_rate(parent); + if (clk->rate > cur_rate) { + ret = clk_set_rate(parent, clk->rate); + if (ret) + goto out; + } + v->enabled = true; +out: + rt_mutex_unlock(&voter_clk_lock); + + return ret; +} + +static void voter_clk_unprepare(struct clk *clk) +{ + unsigned long cur_rate, new_rate; + struct clk *parent; + struct clk_voter *v = to_clk_voter(clk); + + + rt_mutex_lock(&voter_clk_lock); + parent = clk->parent; + + /* + * Decrease the rate if this clock was the only one voting for + * the highest rate. + */ + v->enabled = false; + if (v->is_branch) + goto out; + + new_rate = voter_clk_aggregate_rate(parent); + cur_rate = max(new_rate, clk->rate); + + if (new_rate < cur_rate) + clk_set_rate(parent, new_rate); + +out: + rt_mutex_unlock(&voter_clk_lock); +} + +static int voter_clk_is_enabled(struct clk *clk) +{ + struct clk_voter *v = to_clk_voter(clk); + return v->enabled; +} + +static long voter_clk_round_rate(struct clk *clk, unsigned long rate) +{ + return clk_round_rate(clk->parent, rate); +} + +static bool voter_clk_is_local(struct clk *clk) +{ + return true; +} + +static enum handoff voter_clk_handoff(struct clk *clk) +{ + if (!clk->rate) + return HANDOFF_DISABLED_CLK; + + /* + * Send the default rate to the parent if necessary and update the + * software state of the voter clock. + */ + if (voter_clk_prepare(clk) < 0) + return HANDOFF_DISABLED_CLK; + + return HANDOFF_ENABLED_CLK; +} + +struct clk_ops clk_ops_voter = { + .prepare = voter_clk_prepare, + .unprepare = voter_clk_unprepare, + .set_rate = voter_clk_set_rate, + .is_enabled = voter_clk_is_enabled, + .round_rate = voter_clk_round_rate, + .is_local = voter_clk_is_local, + .handoff = voter_clk_handoff, +}; + +static void *sw_vote_clk_dt_parser(struct device *dev, + struct device_node *np) +{ + struct clk_voter *v; + int rc; + u32 temp; + + v = devm_kzalloc(dev, sizeof(*v), GFP_KERNEL); + if (!v) { + dt_err(np, "failed to alloc memory\n"); + return ERR_PTR(-ENOMEM); + } + + rc = of_property_read_u32(np, "qcom,config-rate", &temp); + if (rc) { + dt_prop_err(np, "qcom,config-rate", "is missing"); + return ERR_PTR(rc); + } + + v->c.ops = &clk_ops_voter; + return msmclk_generic_clk_init(dev, np, &v->c); +} +MSMCLK_PARSER(sw_vote_clk_dt_parser, "qcom,sw-vote-clk", 0); diff -Nruw linux-4.4.115-fbx/drivers/clk/msm./gdsc.c linux-4.4.115-fbx/drivers/clk/msm/gdsc.c --- linux-4.4.115-fbx/drivers/clk/msm./gdsc.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-4.4.115-fbx/drivers/clk/msm/gdsc.c 2019-01-22 16:16:23.019242024 +0100 @@ -0,0 +1,718 @@ +/* + * Copyright (c) 2012-2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define PWR_ON_MASK BIT(31) +#define EN_REST_WAIT_MASK (0xF << 20) +#define EN_FEW_WAIT_MASK (0xF << 16) +#define CLK_DIS_WAIT_MASK (0xF << 12) +#define SW_OVERRIDE_MASK BIT(2) +#define HW_CONTROL_MASK BIT(1) +#define SW_COLLAPSE_MASK BIT(0) +#define GMEM_CLAMP_IO_MASK BIT(0) +#define GMEM_RESET_MASK BIT(4) +#define BCR_BLK_ARES_BIT BIT(0) + +/* Wait 2^n CXO cycles between all states. Here, n=2 (4 cycles). */ +#define EN_REST_WAIT_VAL (0x2 << 20) +#define EN_FEW_WAIT_VAL (0x8 << 16) +#define CLK_DIS_WAIT_VAL (0x2 << 12) + +#define TIMEOUT_US 100 + +struct gdsc { + struct regulator_dev *rdev; + struct regulator_desc rdesc; + void __iomem *gdscr; + struct clk **clocks; + struct reset_control **reset_clocks; + int clock_count; + int reset_count; + bool toggle_mem; + bool toggle_periph; + bool toggle_logic; + bool resets_asserted; + bool root_en; + bool force_root_en; + int root_clk_idx; + bool no_status_check_on_disable; + bool is_gdsc_enabled; + bool allow_clear; + bool reset_aon; + void __iomem *domain_addr; + void __iomem *hw_ctrl_addr; + void __iomem *sw_reset_addr; + u32 gds_timeout; +}; + +enum gdscr_status { + ENABLED, + DISABLED, +}; + +static DEFINE_MUTEX(gdsc_seq_lock); + +void gdsc_allow_clear_retention(struct regulator *regulator) +{ + struct gdsc *sc = regulator_get_drvdata(regulator); + + if (sc) + sc->allow_clear = true; +} + +static int poll_gdsc_status(struct gdsc *sc, enum gdscr_status status) +{ + void __iomem *gdscr; + int count = sc->gds_timeout; + u32 val; + + if (sc->hw_ctrl_addr) + gdscr = sc->hw_ctrl_addr; + else + gdscr = sc->gdscr; + + for (; count > 0; count--) { + val = readl_relaxed(gdscr); + val &= PWR_ON_MASK; + switch (status) { + case ENABLED: + if (val) + return 0; + break; + case DISABLED: + if (!val) + return 0; + break; + } + /* + * There is no guarantee about the delay needed for the enable + * bit in the GDSCR to be set or reset after the GDSC state + * changes. Hence, keep on checking for a reasonable number + * of times until the bit is set with the least possible delay + * between succeessive tries. + */ + udelay(1); + } + return -ETIMEDOUT; +} + +static int gdsc_is_enabled(struct regulator_dev *rdev) +{ + struct gdsc *sc = rdev_get_drvdata(rdev); + uint32_t regval; + + if (!sc->toggle_logic) + return !sc->resets_asserted; + + regval = readl_relaxed(sc->gdscr); + if (regval & PWR_ON_MASK) { + /* + * The GDSC might be turned on due to TZ/HYP vote on the + * votable GDS registers. Check the SW_COLLAPSE_MASK to + * determine if HLOS has voted for it. + */ + if (!(regval & SW_COLLAPSE_MASK)) + return true; + } + return false; +} + +static int gdsc_enable(struct regulator_dev *rdev) +{ + struct gdsc *sc = rdev_get_drvdata(rdev); + uint32_t regval, hw_ctrl_regval = 0x0; + int i, ret = 0; + + mutex_lock(&gdsc_seq_lock); + + if (sc->root_en || sc->force_root_en) + clk_prepare_enable(sc->clocks[sc->root_clk_idx]); + + if (sc->toggle_logic) { + if (sc->sw_reset_addr) { + regval = readl_relaxed(sc->sw_reset_addr); + regval |= BCR_BLK_ARES_BIT; + writel_relaxed(regval, sc->sw_reset_addr); + /* + * BLK_ARES should be kept asserted for 1us before + * being de-asserted. + */ + wmb(); + udelay(1); + + regval &= ~BCR_BLK_ARES_BIT; + writel_relaxed(regval, sc->sw_reset_addr); + + /* Make sure de-assert goes through before continuing */ + wmb(); + } + + if (sc->domain_addr) { + if (sc->reset_aon) { + regval = readl_relaxed(sc->domain_addr); + regval |= GMEM_RESET_MASK; + writel_relaxed(regval, sc->domain_addr); + /* + * Keep reset asserted for at-least 1us before + * continuing. + */ + wmb(); + udelay(1); + + regval &= ~GMEM_RESET_MASK; + writel_relaxed(regval, sc->domain_addr); + /* + * Make sure GMEM_RESET is de-asserted before + * continuing. + */ + wmb(); + } + + regval = readl_relaxed(sc->domain_addr); + regval &= ~GMEM_CLAMP_IO_MASK; + writel_relaxed(regval, sc->domain_addr); + /* + * Make sure CLAMP_IO is de-asserted before continuing. + */ + wmb(); + } + + regval = readl_relaxed(sc->gdscr); + if (regval & HW_CONTROL_MASK) { + dev_warn(&rdev->dev, "Invalid enable while %s is under HW control\n", + sc->rdesc.name); + mutex_unlock(&gdsc_seq_lock); + return -EBUSY; + } + + regval &= ~SW_COLLAPSE_MASK; + writel_relaxed(regval, sc->gdscr); + + /* Wait for 8 XO cycles before polling the status bit. */ + mb(); + udelay(1); + + ret = poll_gdsc_status(sc, ENABLED); + if (ret) { + regval = readl_relaxed(sc->gdscr); + if (sc->hw_ctrl_addr) { + hw_ctrl_regval = + readl_relaxed(sc->hw_ctrl_addr); + dev_warn(&rdev->dev, "%s state (after %d us timeout): 0x%x, GDS_HW_CTRL: 0x%x. Re-polling.\n", + sc->rdesc.name, sc->gds_timeout, + regval, hw_ctrl_regval); + + ret = poll_gdsc_status(sc, ENABLED); + if (ret) { + dev_err(&rdev->dev, "%s final state (after additional %d us timeout): 0x%x, GDS_HW_CTRL: 0x%x\n", + sc->rdesc.name, sc->gds_timeout, + readl_relaxed(sc->gdscr), + readl_relaxed(sc->hw_ctrl_addr)); + + mutex_unlock(&gdsc_seq_lock); + return ret; + } + } else { + dev_err(&rdev->dev, "%s enable timed out: 0x%x\n", + sc->rdesc.name, + regval); + udelay(sc->gds_timeout); + regval = readl_relaxed(sc->gdscr); + dev_err(&rdev->dev, "%s final state: 0x%x (%d us after timeout)\n", + sc->rdesc.name, regval, + sc->gds_timeout); + mutex_unlock(&gdsc_seq_lock); + return ret; + } + } + } else { + for (i = 0; i < sc->reset_count; i++) + reset_control_deassert(sc->reset_clocks[i]); + sc->resets_asserted = false; + } + + for (i = 0; i < sc->clock_count; i++) { + if (unlikely(i == sc->root_clk_idx)) + continue; + if (sc->toggle_mem) + clk_set_flags(sc->clocks[i], CLKFLAG_RETAIN_MEM); + if (sc->toggle_periph) + clk_set_flags(sc->clocks[i], CLKFLAG_RETAIN_PERIPH); + } + + /* + * If clocks to this power domain were already on, they will take an + * additional 4 clock cycles to re-enable after the rail is enabled. + * Delay to account for this. A delay is also needed to ensure clocks + * are not enabled within 400ns of enabling power to the memories. + */ + udelay(1); + + /* Delay to account for staggered memory powerup. */ + udelay(1); + + if (sc->force_root_en) + clk_disable_unprepare(sc->clocks[sc->root_clk_idx]); + sc->is_gdsc_enabled = true; + + mutex_unlock(&gdsc_seq_lock); + + return ret; +} + +static int gdsc_disable(struct regulator_dev *rdev) +{ + struct gdsc *sc = rdev_get_drvdata(rdev); + uint32_t regval; + int i, ret = 0; + + mutex_lock(&gdsc_seq_lock); + + if (sc->force_root_en) + clk_prepare_enable(sc->clocks[sc->root_clk_idx]); + + for (i = sc->clock_count-1; i >= 0; i--) { + if (unlikely(i == sc->root_clk_idx)) + continue; + if (sc->toggle_mem && sc->allow_clear) + clk_set_flags(sc->clocks[i], CLKFLAG_NORETAIN_MEM); + if (sc->toggle_periph && sc->allow_clear) + clk_set_flags(sc->clocks[i], CLKFLAG_NORETAIN_PERIPH); + } + + /* Delay to account for staggered memory powerdown. */ + udelay(1); + + if (sc->toggle_logic) { + regval = readl_relaxed(sc->gdscr); + if (regval & HW_CONTROL_MASK) { + dev_warn(&rdev->dev, "Invalid disable while %s is under HW control\n", + sc->rdesc.name); + mutex_unlock(&gdsc_seq_lock); + return -EBUSY; + } + + regval |= SW_COLLAPSE_MASK; + writel_relaxed(regval, sc->gdscr); + /* Wait for 8 XO cycles before polling the status bit. */ + mb(); + udelay(1); + + if (sc->no_status_check_on_disable) { + /* + * Add a short delay here to ensure that gdsc_enable + * right after it was disabled does not put it in a + * wierd state. + */ + udelay(TIMEOUT_US); + } else { + ret = poll_gdsc_status(sc, DISABLED); + if (ret) + dev_err(&rdev->dev, "%s disable timed out: 0x%x\n", + sc->rdesc.name, regval); + } + + if (sc->domain_addr) { + regval = readl_relaxed(sc->domain_addr); + regval |= GMEM_CLAMP_IO_MASK; + writel_relaxed(regval, sc->domain_addr); + /* Make sure CLAMP_IO is asserted before continuing. */ + wmb(); + } + } else { + for (i = sc->reset_count-1; i >= 0; i--) + reset_control_assert(sc->reset_clocks[i]); + sc->resets_asserted = true; + } + + /* + * Check if gdsc_enable was called for this GDSC. If not, the root + * clock will not have been enabled prior to this. + */ + if ((sc->is_gdsc_enabled && sc->root_en) || sc->force_root_en) + clk_disable_unprepare(sc->clocks[sc->root_clk_idx]); + sc->is_gdsc_enabled = false; + + mutex_unlock(&gdsc_seq_lock); + + return ret; +} + +static unsigned int gdsc_get_mode(struct regulator_dev *rdev) +{ + struct gdsc *sc = rdev_get_drvdata(rdev); + uint32_t regval; + + mutex_lock(&gdsc_seq_lock); + regval = readl_relaxed(sc->gdscr); + mutex_unlock(&gdsc_seq_lock); + if (regval & HW_CONTROL_MASK) + return REGULATOR_MODE_FAST; + return REGULATOR_MODE_NORMAL; +} + +static int gdsc_set_mode(struct regulator_dev *rdev, unsigned int mode) +{ + struct gdsc *sc = rdev_get_drvdata(rdev); + uint32_t regval; + int ret = 0; + + mutex_lock(&gdsc_seq_lock); + + regval = readl_relaxed(sc->gdscr); + + /* + * HW control can only be enable/disabled when SW_COLLAPSE + * indicates on. + */ + if (regval & SW_COLLAPSE_MASK) { + dev_err(&rdev->dev, "can't enable hw collapse now\n"); + mutex_unlock(&gdsc_seq_lock); + return -EBUSY; + } + + switch (mode) { + case REGULATOR_MODE_FAST: + /* Turn on HW trigger mode */ + regval |= HW_CONTROL_MASK; + writel_relaxed(regval, sc->gdscr); + /* + * There may be a race with internal HW trigger signal, + * that will result in GDSC going through a power down and + * up cycle. In case HW trigger signal is controlled by + * firmware that also poll same status bits as we do, FW + * might read an 'on' status before the GDSC can finish + * power cycle. We wait 1us before returning to ensure + * FW can't immediately poll the status bit. + */ + mb(); + udelay(1); + break; + + case REGULATOR_MODE_NORMAL: + /* Turn off HW trigger mode */ + regval &= ~HW_CONTROL_MASK; + writel_relaxed(regval, sc->gdscr); + /* + * There may be a race with internal HW trigger signal, + * that will result in GDSC going through a power down and + * up cycle. If we poll too early, status bit will + * indicate 'on' before the GDSC can finish the power cycle. + * Account for this case by waiting 1us before polling. + */ + mb(); + udelay(1); + + ret = poll_gdsc_status(sc, ENABLED); + if (ret) + dev_err(&rdev->dev, "%s set_mode timed out: 0x%x\n", + sc->rdesc.name, regval); + break; + default: + ret = -EINVAL; + break; + } + + mutex_unlock(&gdsc_seq_lock); + + return ret; +} + +static struct regulator_ops gdsc_ops = { + .is_enabled = gdsc_is_enabled, + .enable = gdsc_enable, + .disable = gdsc_disable, + .set_mode = gdsc_set_mode, + .get_mode = gdsc_get_mode, +}; + +static int gdsc_probe(struct platform_device *pdev) +{ + static atomic_t gdsc_count = ATOMIC_INIT(-1); + struct regulator_config reg_config = {}; + struct regulator_init_data *init_data; + struct resource *res; + struct gdsc *sc; + uint32_t regval, clk_dis_wait_val = CLK_DIS_WAIT_VAL; + bool retain_mem, retain_periph, support_hw_trigger; + int i, ret; + u32 timeout; + + sc = devm_kzalloc(&pdev->dev, sizeof(struct gdsc), GFP_KERNEL); + if (sc == NULL) + return -ENOMEM; + + init_data = of_get_regulator_init_data(&pdev->dev, pdev->dev.of_node, + &sc->rdesc); + if (init_data == NULL) + return -ENOMEM; + + if (of_get_property(pdev->dev.of_node, "parent-supply", NULL)) + init_data->supply_regulator = "parent"; + + ret = of_property_read_string(pdev->dev.of_node, "regulator-name", + &sc->rdesc.name); + if (ret) + return ret; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (res == NULL) + return -EINVAL; + sc->gdscr = devm_ioremap(&pdev->dev, res->start, resource_size(res)); + if (sc->gdscr == NULL) + return -ENOMEM; + + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, + "domain_addr"); + if (res) { + sc->domain_addr = devm_ioremap(&pdev->dev, res->start, + resource_size(res)); + if (sc->domain_addr == NULL) + return -ENOMEM; + } + + sc->reset_aon = of_property_read_bool(pdev->dev.of_node, + "qcom,reset-aon-logic"); + + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, + "sw_reset"); + if (res) { + sc->sw_reset_addr = devm_ioremap(&pdev->dev, res->start, + resource_size(res)); + if (sc->sw_reset_addr == NULL) + return -ENOMEM; + } + + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, + "hw_ctrl_addr"); + if (res) { + sc->hw_ctrl_addr = devm_ioremap(&pdev->dev, res->start, + resource_size(res)); + if (sc->hw_ctrl_addr == NULL) + return -ENOMEM; + } + + sc->gds_timeout = TIMEOUT_US; + ret = of_property_read_u32(pdev->dev.of_node, "qcom,gds-timeout", + &timeout); + if (!ret) + sc->gds_timeout = timeout; + + sc->clock_count = of_property_count_strings(pdev->dev.of_node, + "clock-names"); + if (sc->clock_count == -EINVAL) { + sc->clock_count = 0; + } else if (IS_ERR_VALUE(sc->clock_count)) { + dev_err(&pdev->dev, "Failed to get clock names\n"); + return -EINVAL; + } + + sc->clocks = devm_kzalloc(&pdev->dev, + sizeof(struct clk *) * sc->clock_count, GFP_KERNEL); + if (!sc->clocks) + return -ENOMEM; + + sc->root_clk_idx = -1; + + sc->root_en = of_property_read_bool(pdev->dev.of_node, + "qcom,enable-root-clk"); + sc->force_root_en = of_property_read_bool(pdev->dev.of_node, + "qcom,force-enable-root-clk"); + for (i = 0; i < sc->clock_count; i++) { + const char *clock_name; + of_property_read_string_index(pdev->dev.of_node, "clock-names", + i, &clock_name); + sc->clocks[i] = devm_clk_get(&pdev->dev, clock_name); + if (IS_ERR(sc->clocks[i])) { + int rc = PTR_ERR(sc->clocks[i]); + if (rc != -EPROBE_DEFER) + dev_err(&pdev->dev, "Failed to get %s\n", + clock_name); + return rc; + } + + if (!strcmp(clock_name, "core_root_clk")) + sc->root_clk_idx = i; + } + + if ((sc->root_en || sc->force_root_en) && (sc->root_clk_idx == -1)) { + dev_err(&pdev->dev, "Failed to get root clock name\n"); + return -EINVAL; + } + + sc->rdesc.id = atomic_inc_return(&gdsc_count); + sc->rdesc.ops = &gdsc_ops; + sc->rdesc.type = REGULATOR_VOLTAGE; + sc->rdesc.owner = THIS_MODULE; + platform_set_drvdata(pdev, sc); + + /* + * Disable HW trigger: collapse/restore occur based on registers writes. + * Disable SW override: Use hardware state-machine for sequencing. + */ + regval = readl_relaxed(sc->gdscr); + regval &= ~(HW_CONTROL_MASK | SW_OVERRIDE_MASK); + + if (!of_property_read_u32(pdev->dev.of_node, "qcom,clk-dis-wait-val", + &clk_dis_wait_val)) + clk_dis_wait_val = clk_dis_wait_val << 12; + + /* Configure wait time between states. */ + regval &= ~(EN_REST_WAIT_MASK | EN_FEW_WAIT_MASK | CLK_DIS_WAIT_MASK); + regval |= EN_REST_WAIT_VAL | EN_FEW_WAIT_VAL | clk_dis_wait_val; + writel_relaxed(regval, sc->gdscr); + + sc->no_status_check_on_disable = + of_property_read_bool(pdev->dev.of_node, + "qcom,no-status-check-on-disable"); + retain_mem = of_property_read_bool(pdev->dev.of_node, + "qcom,retain-mem"); + sc->toggle_mem = !retain_mem; + retain_periph = of_property_read_bool(pdev->dev.of_node, + "qcom,retain-periph"); + sc->toggle_periph = !retain_periph; + sc->toggle_logic = !of_property_read_bool(pdev->dev.of_node, + "qcom,skip-logic-collapse"); + support_hw_trigger = of_property_read_bool(pdev->dev.of_node, + "qcom,support-hw-trigger"); + if (support_hw_trigger) { + init_data->constraints.valid_ops_mask |= REGULATOR_CHANGE_MODE; + init_data->constraints.valid_modes_mask |= + REGULATOR_MODE_NORMAL | REGULATOR_MODE_FAST; + } + + if (!sc->toggle_logic) { + sc->reset_count = of_property_count_strings(pdev->dev.of_node, + "reset-names"); + if (sc->reset_count == -EINVAL) { + sc->reset_count = 0; + } else if (IS_ERR_VALUE(sc->reset_count)) { + dev_err(&pdev->dev, "Failed to get reset reset names\n"); + return -EINVAL; + } + + sc->reset_clocks = devm_kzalloc(&pdev->dev, + sizeof(struct reset_control *) * + sc->reset_count, + GFP_KERNEL); + if (!sc->reset_clocks) + return -ENOMEM; + + for (i = 0; i < sc->reset_count; i++) { + const char *reset_name; + + of_property_read_string_index(pdev->dev.of_node, + "reset-names", i, &reset_name); + sc->reset_clocks[i] = devm_reset_control_get(&pdev->dev, + reset_name); + if (IS_ERR(sc->reset_clocks[i])) { + int rc = PTR_ERR(sc->reset_clocks[i]); + + if (rc != -EPROBE_DEFER) + dev_err(&pdev->dev, "Failed to get %s\n", + reset_name); + return rc; + } + } + + regval &= ~SW_COLLAPSE_MASK; + writel_relaxed(regval, sc->gdscr); + + ret = poll_gdsc_status(sc, ENABLED); + if (ret) { + dev_err(&pdev->dev, "%s enable timed out: 0x%x\n", + sc->rdesc.name, regval); + return ret; + } + } + + sc->allow_clear = of_property_read_bool(pdev->dev.of_node, + "qcom,disallow-clear"); + sc->allow_clear = !sc->allow_clear; + + for (i = 0; i < sc->clock_count; i++) { + if (retain_mem || (regval & PWR_ON_MASK) || !sc->allow_clear) + clk_set_flags(sc->clocks[i], CLKFLAG_RETAIN_MEM); + else + clk_set_flags(sc->clocks[i], CLKFLAG_NORETAIN_MEM); + + if (retain_periph || (regval & PWR_ON_MASK) || !sc->allow_clear) + clk_set_flags(sc->clocks[i], CLKFLAG_RETAIN_PERIPH); + else + clk_set_flags(sc->clocks[i], CLKFLAG_NORETAIN_PERIPH); + } + + reg_config.dev = &pdev->dev; + reg_config.init_data = init_data; + reg_config.driver_data = sc; + reg_config.of_node = pdev->dev.of_node; + sc->rdev = regulator_register(&sc->rdesc, ®_config); + if (IS_ERR(sc->rdev)) { + dev_err(&pdev->dev, "regulator_register(\"%s\") failed.\n", + sc->rdesc.name); + return PTR_ERR(sc->rdev); + } + + return 0; +} + +static int gdsc_remove(struct platform_device *pdev) +{ + struct gdsc *sc = platform_get_drvdata(pdev); + regulator_unregister(sc->rdev); + return 0; +} + +static struct of_device_id gdsc_match_table[] = { + { .compatible = "qcom,gdsc" }, + {} +}; + +static struct platform_driver gdsc_driver = { + .probe = gdsc_probe, + .remove = gdsc_remove, + .driver = { + .name = "gdsc", + .of_match_table = gdsc_match_table, + .owner = THIS_MODULE, + }, +}; + +static int __init gdsc_init(void) +{ + return platform_driver_register(&gdsc_driver); +} +subsys_initcall(gdsc_init); + +static void __exit gdsc_exit(void) +{ + platform_driver_unregister(&gdsc_driver); +} +module_exit(gdsc_exit); + +MODULE_LICENSE("GPL v2"); +MODULE_DESCRIPTION("MSM8974 GDSC power rail regulator driver"); diff -Nruw linux-4.4.115-fbx/drivers/clk/msm./Kconfig linux-4.4.115-fbx/drivers/clk/msm/Kconfig --- linux-4.4.115-fbx/drivers/clk/msm./Kconfig 1970-01-01 01:00:00.000000000 +0100 +++ linux-4.4.115-fbx/drivers/clk/msm/Kconfig 2019-01-22 16:16:23.015241987 +0100 @@ -0,0 +1,30 @@ +config COMMON_CLK_MSM + tristate "Support for MSM clock controllers" + depends on OF + depends on ARCH_QCOM + select RATIONAL + help + This support clock controller used by MSM devices which support + global, mmss and gpu clock controller. + Say Y if you want to support the clocks exposed by the MSM on + platforms such as msm8996, msm8998 etc. + +config MSM_CLK_CONTROLLER_V2 + bool "QTI clock driver" + depends on COMMON_CLK_MSM + ---help--- + Generate clock data structures from definitions found in + device tree. + +config MSM_VIRTCLK_FRONTEND + bool + +config MSM_VIRTCLK_FRONTEND_8996 + tristate "QTI msm8996 virtual clock frontend driver" + depends on COMMON_CLK_MSM && MSM_HAB + select MSM_VIRTCLK_FRONTEND + ---help--- + This is the virtual clock frontend driver for the QTI msm8996 + virtual platform. + +source "drivers/clk/msm/mdss/Kconfig" diff -Nruw linux-4.4.115-fbx/drivers/clk/msm./Makefile linux-4.4.115-fbx/drivers/clk/msm/Makefile --- linux-4.4.115-fbx/drivers/clk/msm./Makefile 1970-01-01 01:00:00.000000000 +0100 +++ linux-4.4.115-fbx/drivers/clk/msm/Makefile 2019-01-22 16:16:23.015241987 +0100 @@ -0,0 +1,35 @@ +obj-$(CONFIG_COMMON_CLK_MSM) += clock.o +obj-$(CONFIG_COMMON_CLK_MSM) += clock-dummy.o +obj-$(CONFIG_COMMON_CLK_MSM) += clock-generic.o +obj-$(CONFIG_COMMON_CLK_MSM) += clock-local2.o +obj-$(CONFIG_COMMON_CLK_MSM) += clock-pll.o +obj-$(CONFIG_COMMON_CLK_MSM) += clock-alpha-pll.o +obj-$(CONFIG_COMMON_CLK_MSM) += clock-rpm.o +obj-$(CONFIG_COMMON_CLK_MSM) += clock-voter.o +obj-$(CONFIG_COMMON_CLK_MSM) += reset.o + +obj-$(CONFIG_MSM_CLK_CONTROLLER_V2) += msm-clock-controller.o + +obj-$(CONFIG_COMMON_CLK_MSM) += clock-debug.o + +# MSM 8996 +ifeq ($(CONFIG_COMMON_CLK_MSM), y) + obj-$(CONFIG_ARCH_MSM8996) += clock-gcc-8996.o + obj-$(CONFIG_ARCH_MSM8996) += clock-mmss-8996.o + obj-$(CONFIG_ARCH_MSM8996) += clock-cpu-8996.o +endif + +# MSM 8998 +ifeq ($(CONFIG_COMMON_CLK_MSM), y) + obj-$(CONFIG_ARCH_MSM8998) += clock-gcc-8998.o + obj-$(CONFIG_ARCH_MSM8998) += clock-gpu-8998.o + obj-$(CONFIG_ARCH_MSM8998) += clock-mmss-8998.o + obj-$(CONFIG_ARCH_MSM8998) += clock-osm.o +endif + +obj-$(CONFIG_COMMON_CLK_MSM) += gdsc.o +obj-$(CONFIG_COMMON_CLK_MSM) += mdss/ + +obj-$(CONFIG_MSM_VIRTCLK_FRONTEND) += virtclk-front.o +obj-$(CONFIG_MSM_VIRTCLK_FRONTEND) += virt-reset-front.o +obj-$(CONFIG_MSM_VIRTCLK_FRONTEND_8996) += virtclk-front-8996.o diff -Nruw linux-4.4.115-fbx/drivers/clk/msm./mdss/Kconfig linux-4.4.115-fbx/drivers/clk/msm/mdss/Kconfig --- linux-4.4.115-fbx/drivers/clk/msm./mdss/Kconfig 1970-01-01 01:00:00.000000000 +0100 +++ linux-4.4.115-fbx/drivers/clk/msm/mdss/Kconfig 2019-01-22 16:16:23.019242024 +0100 @@ -0,0 +1,7 @@ +config MSM_MDSS_PLL + bool "MDSS pll programming" + depends on COMMON_CLK_MSM + ---help--- + It provides support for DSI, eDP and HDMI interface pll programming on MDSS + hardware. It also handles the pll specific resources and turn them on/off when + mdss pll client tries to enable/disable pll clocks. diff -Nruw linux-4.4.115-fbx/drivers/clk/msm./mdss/Makefile linux-4.4.115-fbx/drivers/clk/msm/mdss/Makefile --- linux-4.4.115-fbx/drivers/clk/msm./mdss/Makefile 1970-01-01 01:00:00.000000000 +0100 +++ linux-4.4.115-fbx/drivers/clk/msm/mdss/Makefile 2019-01-22 16:16:23.019242024 +0100 @@ -0,0 +1,9 @@ +obj-$(CONFIG_MSM_MDSS_PLL) += mdss-pll-util.o +obj-$(CONFIG_MSM_MDSS_PLL) += mdss-pll.o +obj-$(CONFIG_MSM_MDSS_PLL) += mdss-dsi-pll-8996.o +obj-$(CONFIG_MSM_MDSS_PLL) += mdss-dsi-pll-8996-util.o +obj-$(CONFIG_MSM_MDSS_PLL) += mdss-dsi-pll-8998.o +obj-$(CONFIG_MSM_MDSS_PLL) += mdss-dp-pll-8998.o +obj-$(CONFIG_MSM_MDSS_PLL) += mdss-dp-pll-8998-util.o +obj-$(CONFIG_MSM_MDSS_PLL) += mdss-hdmi-pll-8996.o +obj-$(CONFIG_MSM_MDSS_PLL) += mdss-hdmi-pll-8998.o diff -Nruw linux-4.4.115-fbx/drivers/clk/msm./mdss/mdss-dp-pll-8998.c linux-4.4.115-fbx/drivers/clk/msm/mdss/mdss-dp-pll-8998.c --- linux-4.4.115-fbx/drivers/clk/msm./mdss/mdss-dp-pll-8998.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-4.4.115-fbx/drivers/clk/msm/mdss/mdss-dp-pll-8998.c 2019-01-22 16:16:23.019242024 +0100 @@ -0,0 +1,224 @@ +/* Copyright (c) 2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +/* +*************************************************************************** +******** Display Port PLL driver block diagram for branch clocks ********** +*************************************************************************** + + +--------------------------+ + | DP_VCO_CLK | + | | + | +-------------------+ | + | | (DP PLL/VCO) | | + | +---------+---------+ | + | v | + | +----------+-----------+ | + | | hsclk_divsel_clk_src | | + | +----------+-----------+ | + +--------------------------+ + | + v + +------------<------------|------------>-------------+ + | | | ++----------v----------+ +----------v----------+ +----------v----------+ +| dp_link_2x_clk | | vco_divided_clk_src | | vco_divided_clk_src | +| divsel_five | | | | | +v----------+----------v | divsel_two | | divsel_four | + | +----------+----------+ +----------+----------+ + | | | + v v v + | +---------------------+ | + Input to MMSSCC block | | (aux_clk_ops) | | + for link clk, crypto clk +--> vco_divided_clk <-+ + and interface clock | _src_mux | + +----------+----------+ + | + v + Input to MMSSCC block + for DP pixel clock + +****************************************************************************** +*/ + +#define pr_fmt(fmt) "%s: " fmt, __func__ + +#include +#include +#include +#include +#include +#include +#include + +#include "mdss-pll.h" +#include "mdss-dp-pll.h" +#include "mdss-dp-pll-8998.h" + +static struct clk_ops clk_ops_vco_divided_clk_src_c; +static struct clk_ops clk_ops_link_2x_clk_div_c; +static struct clk_ops clk_ops_gen_mux_dp; + +static struct clk_div_ops link2xclk_divsel_ops = { + .set_div = link2xclk_divsel_set_div, + .get_div = link2xclk_divsel_get_div, +}; + +static struct clk_div_ops vco_divided_clk_ops = { + .set_div = vco_divided_clk_set_div, + .get_div = vco_divided_clk_get_div, +}; + +static struct clk_ops dp_8998_vco_clk_ops = { + .set_rate = dp_vco_set_rate, + .round_rate = dp_vco_round_rate, + .prepare = dp_vco_prepare, + .unprepare = dp_vco_unprepare, + .handoff = dp_vco_handoff, +}; + +static struct clk_mux_ops mdss_mux_ops = { + .set_mux_sel = mdss_set_mux_sel, + .get_mux_sel = mdss_get_mux_sel, +}; + +static struct dp_pll_vco_clk dp_vco_clk = { + .min_rate = DP_VCO_HSCLK_RATE_1620MHZDIV1000, + .max_rate = DP_VCO_HSCLK_RATE_5400MHZDIV1000, + .c = { + .dbg_name = "dp_vco_clk", + .ops = &dp_8998_vco_clk_ops, + .flags = CLKFLAG_NO_RATE_CACHE, + CLK_INIT(dp_vco_clk.c), + }, +}; + +static struct div_clk dp_link_2x_clk_divsel_five = { + .data = { + .div = 5, + .min_div = 5, + .max_div = 5, + }, + .ops = &link2xclk_divsel_ops, + .c = { + .parent = &dp_vco_clk.c, + .dbg_name = "dp_link_2x_clk_divsel_five", + .ops = &clk_ops_link_2x_clk_div_c, + .flags = CLKFLAG_NO_RATE_CACHE, + CLK_INIT(dp_link_2x_clk_divsel_five.c), + }, +}; + +static struct div_clk vco_divsel_four_clk_src = { + .data = { + .div = 4, + .min_div = 4, + .max_div = 4, + }, + .ops = &vco_divided_clk_ops, + .c = { + .parent = &dp_vco_clk.c, + .dbg_name = "vco_divsel_four_clk_src", + .ops = &clk_ops_vco_divided_clk_src_c, + .flags = CLKFLAG_NO_RATE_CACHE, + CLK_INIT(vco_divsel_four_clk_src.c), + }, +}; + +static struct div_clk vco_divsel_two_clk_src = { + .data = { + .div = 2, + .min_div = 2, + .max_div = 2, + }, + .ops = &vco_divided_clk_ops, + .c = { + .parent = &dp_vco_clk.c, + .dbg_name = "vco_divsel_two_clk_src", + .ops = &clk_ops_vco_divided_clk_src_c, + .flags = CLKFLAG_NO_RATE_CACHE, + CLK_INIT(vco_divsel_two_clk_src.c), + }, +}; + +static struct mux_clk vco_divided_clk_src_mux = { + .num_parents = 2, + .parents = (struct clk_src[]) { + {&vco_divsel_two_clk_src.c, 0}, + {&vco_divsel_four_clk_src.c, 1}, + }, + .ops = &mdss_mux_ops, + .c = { + .parent = &vco_divsel_two_clk_src.c, + .dbg_name = "vco_divided_clk_src_mux", + .ops = &clk_ops_gen_mux_dp, + .flags = CLKFLAG_NO_RATE_CACHE, + CLK_INIT(vco_divided_clk_src_mux.c), + } +}; + +static struct clk_lookup dp_pllcc_8998[] = { + CLK_LIST(dp_vco_clk), + CLK_LIST(dp_link_2x_clk_divsel_five), + CLK_LIST(vco_divsel_four_clk_src), + CLK_LIST(vco_divsel_two_clk_src), + CLK_LIST(vco_divided_clk_src_mux), +}; + +int dp_pll_clock_register_8998(struct platform_device *pdev, + struct mdss_pll_resources *pll_res) +{ + int rc = -ENOTSUPP; + + if (!pll_res || !pll_res->pll_base || !pll_res->phy_base) { + DEV_ERR("%s: Invalid input parameters\n", __func__); + return -EINVAL; + } + + /* Set client data for vco, mux and div clocks */ + dp_vco_clk.priv = pll_res; + vco_divided_clk_src_mux.priv = pll_res; + vco_divsel_two_clk_src.priv = pll_res; + vco_divsel_four_clk_src.priv = pll_res; + dp_link_2x_clk_divsel_five.priv = pll_res; + + clk_ops_link_2x_clk_div_c = clk_ops_div; + clk_ops_link_2x_clk_div_c.prepare = mdss_pll_div_prepare; + + /* + * Set the ops for the divider in the pixel clock tree to the + * slave_div to ensure that a set rate on this divider clock will not + * be propagated to it's parent. This is needed ensure that when we set + * the rate for pixel clock, the vco is not reconfigured + */ + clk_ops_vco_divided_clk_src_c = clk_ops_slave_div; + clk_ops_vco_divided_clk_src_c.prepare = mdss_pll_div_prepare; + clk_ops_vco_divided_clk_src_c.handoff = vco_divided_clk_handoff; + + clk_ops_gen_mux_dp = clk_ops_gen_mux; + clk_ops_gen_mux_dp.get_rate = parent_get_rate; + + /* We can select different clock ops for future versions */ + dp_vco_clk.c.ops = &dp_8998_vco_clk_ops; + + rc = of_msm_clock_register(pdev->dev.of_node, dp_pllcc_8998, + ARRAY_SIZE(dp_pllcc_8998)); + if (rc) { + DEV_ERR("%s: Clock register failed rc=%d\n", __func__, rc); + rc = -EPROBE_DEFER; + } else { + DEV_DBG("%s SUCCESS\n", __func__); + } + + return rc; +} diff -Nruw linux-4.4.115-fbx/drivers/clk/msm./mdss/mdss-dp-pll-8998.h linux-4.4.115-fbx/drivers/clk/msm/mdss/mdss-dp-pll-8998.h --- linux-4.4.115-fbx/drivers/clk/msm./mdss/mdss-dp-pll-8998.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-4.4.115-fbx/drivers/clk/msm/mdss/mdss-dp-pll-8998.h 2019-01-22 16:16:23.019242024 +0100 @@ -0,0 +1,180 @@ +/* Copyright (c) 2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef __MDSS_DP_PLL_8998_H +#define __MDSS_DP_PLL_8998_H + +#define DP_PHY_REVISION_ID0 0x0000 +#define DP_PHY_REVISION_ID1 0x0004 +#define DP_PHY_REVISION_ID2 0x0008 +#define DP_PHY_REVISION_ID3 0x000C + +#define DP_PHY_CFG 0x0010 +#define DP_PHY_PD_CTL 0x0014 +#define DP_PHY_MODE 0x0018 + +#define DP_PHY_AUX_CFG0 0x001C +#define DP_PHY_AUX_CFG1 0x0020 +#define DP_PHY_AUX_CFG2 0x0024 +#define DP_PHY_AUX_CFG3 0x0028 +#define DP_PHY_AUX_CFG4 0x002C +#define DP_PHY_AUX_CFG5 0x0030 +#define DP_PHY_AUX_CFG6 0x0034 +#define DP_PHY_AUX_CFG7 0x0038 +#define DP_PHY_AUX_CFG8 0x003C +#define DP_PHY_AUX_CFG9 0x0040 +#define DP_PHY_AUX_INTERRUPT_MASK 0x0044 +#define DP_PHY_AUX_INTERRUPT_CLEAR 0x0048 +#define DP_PHY_AUX_BIST_CFG 0x004C + +#define DP_PHY_VCO_DIV 0x0064 +#define DP_PHY_TX0_TX1_LANE_CTL 0x0068 + +#define DP_PHY_TX2_TX3_LANE_CTL 0x0084 +#define DP_PHY_SPARE0 0x00A8 +#define DP_PHY_STATUS 0x00BC + +/* Tx registers */ +#define QSERDES_TX0_OFFSET 0x0400 +#define QSERDES_TX1_OFFSET 0x0800 + +#define TXn_BIST_MODE_LANENO 0x0000 +#define TXn_CLKBUF_ENABLE 0x0008 +#define TXn_TX_EMP_POST1_LVL 0x000C + +#define TXn_TX_DRV_LVL 0x001C + +#define TXn_RESET_TSYNC_EN 0x0024 +#define TXn_PRE_STALL_LDO_BOOST_EN 0x0028 +#define TXn_TX_BAND 0x002C +#define TXn_SLEW_CNTL 0x0030 +#define TXn_INTERFACE_SELECT 0x0034 + +#define TXn_RES_CODE_LANE_TX 0x003C +#define TXn_RES_CODE_LANE_RX 0x0040 +#define TXn_RES_CODE_LANE_OFFSET_TX 0x0044 +#define TXn_RES_CODE_LANE_OFFSET_RX 0x0048 + +#define TXn_DEBUG_BUS_SEL 0x0058 +#define TXn_TRANSCEIVER_BIAS_EN 0x005C +#define TXn_HIGHZ_DRVR_EN 0x0060 +#define TXn_TX_POL_INV 0x0064 +#define TXn_PARRATE_REC_DETECT_IDLE_EN 0x0068 + +#define TXn_LANE_MODE_1 0x008C + +#define TXn_TRAN_DRVR_EMP_EN 0x00C0 +#define TXn_TX_INTERFACE_MODE 0x00C4 + +#define TXn_VMODE_CTRL1 0x00F0 + + +/* PLL register offset */ +#define QSERDES_COM_ATB_SEL1 0x0000 +#define QSERDES_COM_ATB_SEL2 0x0004 +#define QSERDES_COM_FREQ_UPDATE 0x0008 +#define QSERDES_COM_BG_TIMER 0x000C +#define QSERDES_COM_SSC_EN_CENTER 0x0010 +#define QSERDES_COM_SSC_ADJ_PER1 0x0014 +#define QSERDES_COM_SSC_ADJ_PER2 0x0018 +#define QSERDES_COM_SSC_PER1 0x001C +#define QSERDES_COM_SSC_PER2 0x0020 +#define QSERDES_COM_SSC_STEP_SIZE1 0x0024 +#define QSERDES_COM_SSC_STEP_SIZE2 0x0028 +#define QSERDES_COM_POST_DIV 0x002C +#define QSERDES_COM_POST_DIV_MUX 0x0030 +#define QSERDES_COM_BIAS_EN_CLKBUFLR_EN 0x0034 +#define QSERDES_COM_CLK_ENABLE1 0x0038 +#define QSERDES_COM_SYS_CLK_CTRL 0x003C +#define QSERDES_COM_SYSCLK_BUF_ENABLE 0x0040 +#define QSERDES_COM_PLL_EN 0x0044 +#define QSERDES_COM_PLL_IVCO 0x0048 +#define QSERDES_COM_CMN_IETRIM 0x004C +#define QSERDES_COM_CMN_IPTRIM 0x0050 + +#define QSERDES_COM_CP_CTRL_MODE0 0x0060 +#define QSERDES_COM_CP_CTRL_MODE1 0x0064 +#define QSERDES_COM_PLL_RCTRL_MODE0 0x0068 +#define QSERDES_COM_PLL_RCTRL_MODE1 0x006C +#define QSERDES_COM_PLL_CCTRL_MODE0 0x0070 +#define QSERDES_COM_PLL_CCTRL_MODE1 0x0074 +#define QSERDES_COM_PLL_CNTRL 0x0078 +#define QSERDES_COM_BIAS_EN_CTRL_BY_PSM 0x007C +#define QSERDES_COM_SYSCLK_EN_SEL 0x0080 +#define QSERDES_COM_CML_SYSCLK_SEL 0x0084 +#define QSERDES_COM_RESETSM_CNTRL 0x0088 +#define QSERDES_COM_RESETSM_CNTRL2 0x008C +#define QSERDES_COM_LOCK_CMP_EN 0x0090 +#define QSERDES_COM_LOCK_CMP_CFG 0x0094 +#define QSERDES_COM_LOCK_CMP1_MODE0 0x0098 +#define QSERDES_COM_LOCK_CMP2_MODE0 0x009C +#define QSERDES_COM_LOCK_CMP3_MODE0 0x00A0 + +#define QSERDES_COM_DEC_START_MODE0 0x00B0 +#define QSERDES_COM_DEC_START_MODE1 0x00B4 +#define QSERDES_COM_DIV_FRAC_START1_MODE0 0x00B8 +#define QSERDES_COM_DIV_FRAC_START2_MODE0 0x00BC +#define QSERDES_COM_DIV_FRAC_START3_MODE0 0x00C0 +#define QSERDES_COM_DIV_FRAC_START1_MODE1 0x00C4 +#define QSERDES_COM_DIV_FRAC_START2_MODE1 0x00C8 +#define QSERDES_COM_DIV_FRAC_START3_MODE1 0x00CC +#define QSERDES_COM_INTEGLOOP_INITVAL 0x00D0 +#define QSERDES_COM_INTEGLOOP_EN 0x00D4 +#define QSERDES_COM_INTEGLOOP_GAIN0_MODE0 0x00D8 +#define QSERDES_COM_INTEGLOOP_GAIN1_MODE0 0x00DC +#define QSERDES_COM_INTEGLOOP_GAIN0_MODE1 0x00E0 +#define QSERDES_COM_INTEGLOOP_GAIN1_MODE1 0x00E4 +#define QSERDES_COM_VCOCAL_DEADMAN_CTRL 0x00E8 +#define QSERDES_COM_VCO_TUNE_CTRL 0x00EC +#define QSERDES_COM_VCO_TUNE_MAP 0x00F0 + +#define QSERDES_COM_CMN_STATUS 0x0124 +#define QSERDES_COM_RESET_SM_STATUS 0x0128 + +#define QSERDES_COM_CLK_SEL 0x0138 +#define QSERDES_COM_HSCLK_SEL 0x013C + +#define QSERDES_COM_CORECLK_DIV_MODE0 0x0148 + +#define QSERDES_COM_SW_RESET 0x0150 +#define QSERDES_COM_CORE_CLK_EN 0x0154 +#define QSERDES_COM_C_READY_STATUS 0x0158 +#define QSERDES_COM_CMN_CONFIG 0x015C + +#define QSERDES_COM_SVS_MODE_CLK_SEL 0x0164 + +#define DP_PLL_POLL_SLEEP_US 500 +#define DP_PLL_POLL_TIMEOUT_US 10000 + +#define DP_VCO_RATE_8100MHZDIV1000 8100000UL +#define DP_VCO_RATE_10800MHZDIV1000 10800000UL + +#define DP_VCO_HSCLK_RATE_1620MHZDIV1000 1620000UL +#define DP_VCO_HSCLK_RATE_2700MHZDIV1000 2700000UL +#define DP_VCO_HSCLK_RATE_5400MHZDIV1000 5400000UL + +int dp_vco_set_rate(struct clk *c, unsigned long rate); +unsigned long dp_vco_get_rate(struct clk *c); +long dp_vco_round_rate(struct clk *c, unsigned long rate); +enum handoff dp_vco_handoff(struct clk *c); +enum handoff vco_divided_clk_handoff(struct clk *c); +int dp_vco_prepare(struct clk *c); +void dp_vco_unprepare(struct clk *c); +int hsclk_divsel_set_div(struct div_clk *clk, int div); +int hsclk_divsel_get_div(struct div_clk *clk); +int link2xclk_divsel_set_div(struct div_clk *clk, int div); +int link2xclk_divsel_get_div(struct div_clk *clk); +int vco_divided_clk_set_div(struct div_clk *clk, int div); +int vco_divided_clk_get_div(struct div_clk *clk); + +#endif /* __MDSS_DP_PLL_8998_H */ diff -Nruw linux-4.4.115-fbx/drivers/clk/msm./mdss/mdss-dp-pll-8998-util.c linux-4.4.115-fbx/drivers/clk/msm/mdss/mdss-dp-pll-8998-util.c --- linux-4.4.115-fbx/drivers/clk/msm./mdss/mdss-dp-pll-8998-util.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-4.4.115-fbx/drivers/clk/msm/mdss/mdss-dp-pll-8998-util.c 2019-01-22 16:16:23.019242024 +0100 @@ -0,0 +1,846 @@ +/* Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#define pr_fmt(fmt) "%s: " fmt, __func__ + +#include +#include +#include +#include +#include +#include + +#include "mdss-pll.h" +#include "mdss-dp-pll.h" +#include "mdss-dp-pll-8998.h" + +int link2xclk_divsel_set_div(struct div_clk *clk, int div) +{ + int rc; + u32 link2xclk_div_tx0, link2xclk_div_tx1; + u32 phy_mode; + u8 orientation; + u32 spare_value; + struct mdss_pll_resources *dp_res = clk->priv; + + rc = mdss_pll_resource_enable(dp_res, true); + if (rc) { + pr_err("Failed to enable mdss DP PLL resources\n"); + return rc; + } + + spare_value = MDSS_PLL_REG_R(dp_res->phy_base, DP_PHY_SPARE0); + orientation = (spare_value & 0xF0) >> 4; + pr_debug("spare_value=0x%x, orientation=0x%x\n", spare_value, + orientation); + + link2xclk_div_tx0 = MDSS_PLL_REG_R(dp_res->phy_base, + QSERDES_TX0_OFFSET + TXn_TX_BAND); + link2xclk_div_tx1 = MDSS_PLL_REG_R(dp_res->phy_base, + QSERDES_TX1_OFFSET + TXn_TX_BAND); + + link2xclk_div_tx0 &= ~0x07; /* bits 0 to 2 */ + link2xclk_div_tx1 &= ~0x07; /* bits 0 to 2 */ + + /* Configure TX band Mux */ + link2xclk_div_tx0 |= 0x4; + link2xclk_div_tx1 |= 0x4; + + /* Configure DP PHY MODE depending on the plug orientation */ + if (orientation == ORIENTATION_CC2) + phy_mode = 0x48; + else + phy_mode = 0x58; + + + MDSS_PLL_REG_W(dp_res->phy_base, + QSERDES_TX0_OFFSET + TXn_TX_BAND, + link2xclk_div_tx0); + MDSS_PLL_REG_W(dp_res->phy_base, + QSERDES_TX1_OFFSET + TXn_TX_BAND, + link2xclk_div_tx1); + MDSS_PLL_REG_W(dp_res->phy_base, + DP_PHY_MODE, phy_mode); + /* Make sure the PHY register writes are done */ + wmb(); + + pr_debug("%s: div=%d link2xclk_div_tx0=%x, link2xclk_div_tx1=%x\n", + __func__, div, link2xclk_div_tx0, link2xclk_div_tx1); + + mdss_pll_resource_enable(dp_res, false); + + return rc; +} + +int link2xclk_divsel_get_div(struct div_clk *clk) +{ + int rc; + u32 div = 0, phy_mode; + struct mdss_pll_resources *dp_res = clk->priv; + + rc = mdss_pll_resource_enable(dp_res, true); + if (rc) { + pr_err("Failed to enable dp_res resources\n"); + return rc; + } + + phy_mode = MDSS_PLL_REG_R(dp_res->phy_base, DP_PHY_MODE); + + if (phy_mode & 0x48) + pr_err("%s: DP PAR Rate not correct\n", __func__); + + if ((phy_mode & 0x3) == 1) + div = 10; + else if ((phy_mode & 0x3) == 0) + div = 5; + else + pr_err("%s: unsupported div: %d\n", __func__, phy_mode); + + mdss_pll_resource_enable(dp_res, false); + pr_debug("%s: phy_mode=%d, div=%d\n", __func__, + phy_mode, div); + + return div; +} + +int vco_divided_clk_set_div(struct div_clk *clk, int div) +{ + int rc; + u32 auxclk_div; + struct mdss_pll_resources *dp_res = clk->priv; + + rc = mdss_pll_resource_enable(dp_res, true); + if (rc) { + pr_err("Failed to enable mdss DP PLL resources\n"); + return rc; + } + + auxclk_div = MDSS_PLL_REG_R(dp_res->phy_base, DP_PHY_VCO_DIV); + auxclk_div &= ~0x03; /* bits 0 to 1 */ + + if (div == 4) + auxclk_div |= 2; + else + auxclk_div |= 1; /* Default divider */ + + MDSS_PLL_REG_W(dp_res->phy_base, + DP_PHY_VCO_DIV, auxclk_div); + /* Make sure the PHY registers writes are done */ + wmb(); + pr_debug("%s: div=%d auxclk_div=%x\n", __func__, div, auxclk_div); + + mdss_pll_resource_enable(dp_res, false); + + return rc; +} + + +enum handoff vco_divided_clk_handoff(struct clk *c) +{ + /* + * Since cont-splash is not enabled, disable handoff + * for vco_divider_clk. + */ + return HANDOFF_DISABLED_CLK; +} + +int vco_divided_clk_get_div(struct div_clk *clk) +{ + int rc; + u32 div, auxclk_div; + struct mdss_pll_resources *dp_res = clk->priv; + + rc = mdss_pll_resource_enable(dp_res, true); + if (rc) { + pr_err("Failed to enable dp_res resources\n"); + return rc; + } + + auxclk_div = MDSS_PLL_REG_R(dp_res->phy_base, DP_PHY_VCO_DIV); + auxclk_div &= 0x03; + + div = 2; /* Default divider */ + if (auxclk_div == 2) + div = 4; + + mdss_pll_resource_enable(dp_res, false); + + pr_debug("%s: auxclk_div=%d, div=%d\n", __func__, auxclk_div, div); + + return div; +} + +int dp_config_vco_rate(struct dp_pll_vco_clk *vco, unsigned long rate) +{ + u32 res = 0; + struct mdss_pll_resources *dp_res = vco->priv; + u8 orientation, ln_cnt; + u32 spare_value; + + spare_value = MDSS_PLL_REG_R(dp_res->phy_base, DP_PHY_SPARE0); + ln_cnt = spare_value & 0x0F; + orientation = (spare_value & 0xF0) >> 4; + pr_debug("%s: spare_value=0x%x, ln_cnt=0x%x, orientation=0x%x\n", + __func__, spare_value, ln_cnt, orientation); + + if (ln_cnt != 4) { + if (orientation == ORIENTATION_CC2) + MDSS_PLL_REG_W(dp_res->phy_base, + DP_PHY_PD_CTL, 0x2d); + else + MDSS_PLL_REG_W(dp_res->phy_base, + DP_PHY_PD_CTL, 0x35); + } else { + MDSS_PLL_REG_W(dp_res->phy_base, + DP_PHY_PD_CTL, 0x3d); + } + + /* Make sure the PHY register writes are done */ + wmb(); + MDSS_PLL_REG_W(dp_res->pll_base, + QSERDES_COM_SVS_MODE_CLK_SEL, 0x01); + MDSS_PLL_REG_W(dp_res->pll_base, + QSERDES_COM_SYSCLK_EN_SEL, 0x37); + + MDSS_PLL_REG_W(dp_res->pll_base, + QSERDES_COM_CLK_ENABLE1, 0x0e); + MDSS_PLL_REG_W(dp_res->pll_base, + QSERDES_COM_SYSCLK_BUF_ENABLE, 0x06); + MDSS_PLL_REG_W(dp_res->pll_base, + QSERDES_COM_CLK_SEL, 0x30); + + /* Different for each clock rates */ + if (rate == DP_VCO_HSCLK_RATE_1620MHZDIV1000) { + pr_debug("%s: VCO rate: %ld\n", __func__, + DP_VCO_RATE_8100MHZDIV1000); + MDSS_PLL_REG_W(dp_res->pll_base, + QSERDES_COM_SYS_CLK_CTRL, 0x02); + MDSS_PLL_REG_W(dp_res->pll_base, + QSERDES_COM_HSCLK_SEL, 0x2c); + MDSS_PLL_REG_W(dp_res->pll_base, + QSERDES_COM_LOCK_CMP_EN, 0x04); + MDSS_PLL_REG_W(dp_res->pll_base, + QSERDES_COM_DEC_START_MODE0, 0x69); + MDSS_PLL_REG_W(dp_res->pll_base, + QSERDES_COM_DIV_FRAC_START1_MODE0, 0x00); + MDSS_PLL_REG_W(dp_res->pll_base, + QSERDES_COM_DIV_FRAC_START2_MODE0, 0x80); + MDSS_PLL_REG_W(dp_res->pll_base, + QSERDES_COM_DIV_FRAC_START3_MODE0, 0x07); + MDSS_PLL_REG_W(dp_res->pll_base, + QSERDES_COM_CMN_CONFIG, 0x42); + MDSS_PLL_REG_W(dp_res->pll_base, + QSERDES_COM_LOCK_CMP1_MODE0, 0xbf); + MDSS_PLL_REG_W(dp_res->pll_base, + QSERDES_COM_LOCK_CMP2_MODE0, 0x21); + MDSS_PLL_REG_W(dp_res->pll_base, + QSERDES_COM_LOCK_CMP3_MODE0, 0x00); + } else if (rate == DP_VCO_HSCLK_RATE_2700MHZDIV1000) { + pr_debug("%s: VCO rate: %ld\n", __func__, + DP_VCO_RATE_8100MHZDIV1000); + MDSS_PLL_REG_W(dp_res->pll_base, + QSERDES_COM_SYS_CLK_CTRL, 0x06); + MDSS_PLL_REG_W(dp_res->pll_base, + QSERDES_COM_HSCLK_SEL, 0x84); + MDSS_PLL_REG_W(dp_res->pll_base, + QSERDES_COM_LOCK_CMP_EN, 0x08); + MDSS_PLL_REG_W(dp_res->pll_base, + QSERDES_COM_DEC_START_MODE0, 0x69); + MDSS_PLL_REG_W(dp_res->pll_base, + QSERDES_COM_DIV_FRAC_START1_MODE0, 0x00); + MDSS_PLL_REG_W(dp_res->pll_base, + QSERDES_COM_DIV_FRAC_START2_MODE0, 0x80); + MDSS_PLL_REG_W(dp_res->pll_base, + QSERDES_COM_DIV_FRAC_START3_MODE0, 0x07); + MDSS_PLL_REG_W(dp_res->pll_base, + QSERDES_COM_CMN_CONFIG, 0x02); + MDSS_PLL_REG_W(dp_res->pll_base, + QSERDES_COM_LOCK_CMP1_MODE0, 0x3f); + MDSS_PLL_REG_W(dp_res->pll_base, + QSERDES_COM_LOCK_CMP2_MODE0, 0x38); + MDSS_PLL_REG_W(dp_res->pll_base, + QSERDES_COM_LOCK_CMP3_MODE0, 0x00); + } else if (rate == DP_VCO_HSCLK_RATE_5400MHZDIV1000) { + pr_debug("%s: VCO rate: %ld\n", __func__, + DP_VCO_RATE_10800MHZDIV1000); + MDSS_PLL_REG_W(dp_res->pll_base, + QSERDES_COM_SYS_CLK_CTRL, 0x06); + MDSS_PLL_REG_W(dp_res->pll_base, + QSERDES_COM_HSCLK_SEL, 0x80); + MDSS_PLL_REG_W(dp_res->pll_base, + QSERDES_COM_LOCK_CMP_EN, 0x08); + MDSS_PLL_REG_W(dp_res->pll_base, + QSERDES_COM_DEC_START_MODE0, 0x8c); + MDSS_PLL_REG_W(dp_res->pll_base, + QSERDES_COM_DIV_FRAC_START1_MODE0, 0x00); + MDSS_PLL_REG_W(dp_res->pll_base, + QSERDES_COM_DIV_FRAC_START2_MODE0, 0x00); + MDSS_PLL_REG_W(dp_res->pll_base, + QSERDES_COM_DIV_FRAC_START3_MODE0, 0x0a); + MDSS_PLL_REG_W(dp_res->pll_base, + QSERDES_COM_CMN_CONFIG, 0x12); + MDSS_PLL_REG_W(dp_res->pll_base, + QSERDES_COM_LOCK_CMP1_MODE0, 0x7f); + MDSS_PLL_REG_W(dp_res->pll_base, + QSERDES_COM_LOCK_CMP2_MODE0, 0x70); + MDSS_PLL_REG_W(dp_res->pll_base, + QSERDES_COM_LOCK_CMP3_MODE0, 0x00); + } else { + pr_err("%s: unsupported rate: %ld\n", __func__, rate); + return -EINVAL; + } + /* Make sure the PLL register writes are done */ + wmb(); + + if ((rate == DP_VCO_HSCLK_RATE_1620MHZDIV1000) + || (rate == DP_VCO_HSCLK_RATE_2700MHZDIV1000)) { + MDSS_PLL_REG_W(dp_res->phy_base, + DP_PHY_VCO_DIV, 0x1); + } else { + MDSS_PLL_REG_W(dp_res->phy_base, + DP_PHY_VCO_DIV, 0x2); + } + /* Make sure the PHY register writes are done */ + wmb(); + + MDSS_PLL_REG_W(dp_res->pll_base, + QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x3f); + MDSS_PLL_REG_W(dp_res->pll_base, + QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00); + MDSS_PLL_REG_W(dp_res->pll_base, + QSERDES_COM_VCO_TUNE_MAP, 0x00); + + MDSS_PLL_REG_W(dp_res->pll_base, + QSERDES_COM_BG_TIMER, 0x00); + MDSS_PLL_REG_W(dp_res->pll_base, + QSERDES_COM_BG_TIMER, 0x0a); + MDSS_PLL_REG_W(dp_res->pll_base, + QSERDES_COM_CORECLK_DIV_MODE0, 0x05); + MDSS_PLL_REG_W(dp_res->pll_base, + QSERDES_COM_VCO_TUNE_CTRL, 0x00); + MDSS_PLL_REG_W(dp_res->pll_base, + QSERDES_COM_CP_CTRL_MODE0, 0x06); + MDSS_PLL_REG_W(dp_res->pll_base, + QSERDES_COM_PLL_CCTRL_MODE0, 0x36); + MDSS_PLL_REG_W(dp_res->pll_base, + QSERDES_COM_PLL_RCTRL_MODE0, 0x16); + MDSS_PLL_REG_W(dp_res->pll_base, + QSERDES_COM_PLL_IVCO, 0x07); + MDSS_PLL_REG_W(dp_res->pll_base, + QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x37); + MDSS_PLL_REG_W(dp_res->pll_base, + QSERDES_COM_CORE_CLK_EN, 0x0f); + + /* Make sure the PLL register writes are done */ + wmb(); + + if (orientation == ORIENTATION_CC2) + MDSS_PLL_REG_W(dp_res->phy_base, DP_PHY_MODE, 0x48); + else + MDSS_PLL_REG_W(dp_res->phy_base, DP_PHY_MODE, 0x58); + + MDSS_PLL_REG_W(dp_res->phy_base, + DP_PHY_TX0_TX1_LANE_CTL, 0x05); + MDSS_PLL_REG_W(dp_res->phy_base, + DP_PHY_TX2_TX3_LANE_CTL, 0x05); + + MDSS_PLL_REG_W(dp_res->phy_base, + QSERDES_TX0_OFFSET + TXn_TRANSCEIVER_BIAS_EN, + 0x1a); + MDSS_PLL_REG_W(dp_res->phy_base, + QSERDES_TX1_OFFSET + TXn_TRANSCEIVER_BIAS_EN, + 0x1a); + + MDSS_PLL_REG_W(dp_res->phy_base, + QSERDES_TX0_OFFSET + TXn_VMODE_CTRL1, + 0x40); + MDSS_PLL_REG_W(dp_res->phy_base, + QSERDES_TX1_OFFSET + TXn_VMODE_CTRL1, + 0x40); + + MDSS_PLL_REG_W(dp_res->phy_base, + QSERDES_TX0_OFFSET + TXn_PRE_STALL_LDO_BOOST_EN, + 0x30); + MDSS_PLL_REG_W(dp_res->phy_base, + QSERDES_TX1_OFFSET + TXn_PRE_STALL_LDO_BOOST_EN, + 0x30); + MDSS_PLL_REG_W(dp_res->phy_base, + QSERDES_TX0_OFFSET + TXn_INTERFACE_SELECT, + 0x3d); + MDSS_PLL_REG_W(dp_res->phy_base, + QSERDES_TX1_OFFSET + TXn_INTERFACE_SELECT, + 0x3d); + MDSS_PLL_REG_W(dp_res->phy_base, + QSERDES_TX0_OFFSET + TXn_CLKBUF_ENABLE, + 0x0f); + MDSS_PLL_REG_W(dp_res->phy_base, + QSERDES_TX1_OFFSET + TXn_CLKBUF_ENABLE, + 0x0f); + MDSS_PLL_REG_W(dp_res->phy_base, + QSERDES_TX0_OFFSET + TXn_RESET_TSYNC_EN, + 0x03); + MDSS_PLL_REG_W(dp_res->phy_base, + QSERDES_TX1_OFFSET + TXn_RESET_TSYNC_EN, + 0x03); + MDSS_PLL_REG_W(dp_res->phy_base, + QSERDES_TX0_OFFSET + TXn_TRAN_DRVR_EMP_EN, + 0x03); + MDSS_PLL_REG_W(dp_res->phy_base, + QSERDES_TX1_OFFSET + TXn_TRAN_DRVR_EMP_EN, + 0x03); + MDSS_PLL_REG_W(dp_res->phy_base, + QSERDES_TX0_OFFSET + TXn_PARRATE_REC_DETECT_IDLE_EN, + 0x00); + MDSS_PLL_REG_W(dp_res->phy_base, + QSERDES_TX1_OFFSET + TXn_PARRATE_REC_DETECT_IDLE_EN, + 0x00); + MDSS_PLL_REG_W(dp_res->phy_base, + QSERDES_TX0_OFFSET + TXn_TX_INTERFACE_MODE, + 0x00); + MDSS_PLL_REG_W(dp_res->phy_base, + QSERDES_TX1_OFFSET + TXn_TX_INTERFACE_MODE, + 0x00); + + MDSS_PLL_REG_W(dp_res->phy_base, + QSERDES_TX0_OFFSET + TXn_TX_BAND, + 0x4); + MDSS_PLL_REG_W(dp_res->phy_base, + QSERDES_TX1_OFFSET + TXn_TX_BAND, + 0x4); + /* Make sure the PHY register writes are done */ + wmb(); + return res; +} + +static bool dp_pll_lock_status(struct mdss_pll_resources *dp_res) +{ + u32 status; + bool pll_locked; + + /* poll for PLL ready status */ + if (readl_poll_timeout_atomic((dp_res->pll_base + + QSERDES_COM_C_READY_STATUS), + status, + ((status & BIT(0)) > 0), + DP_PLL_POLL_SLEEP_US, + DP_PLL_POLL_TIMEOUT_US)) { + pr_err("%s: C_READY status is not high. Status=%x\n", + __func__, status); + pll_locked = false; + } else if (readl_poll_timeout_atomic((dp_res->pll_base + + DP_PHY_STATUS), + status, + ((status & BIT(1)) > 0), + DP_PLL_POLL_SLEEP_US, + DP_PLL_POLL_TIMEOUT_US)) { + pr_err("%s: Phy_ready is not high. Status=%x\n", + __func__, status); + pll_locked = false; + } else { + pll_locked = true; + } + + return pll_locked; +} + + +static int dp_pll_enable(struct clk *c) +{ + int rc = 0; + u32 status; + struct dp_pll_vco_clk *vco = mdss_dp_to_vco_clk(c); + struct mdss_pll_resources *dp_res = vco->priv; + u8 orientation, ln_cnt; + u32 spare_value, bias_en, drvr_en, lane_mode; + + spare_value = MDSS_PLL_REG_R(dp_res->phy_base, DP_PHY_SPARE0); + ln_cnt = spare_value & 0x0F; + orientation = (spare_value & 0xF0) >> 4; + + MDSS_PLL_REG_W(dp_res->phy_base, + DP_PHY_CFG, 0x01); + MDSS_PLL_REG_W(dp_res->phy_base, + DP_PHY_CFG, 0x05); + MDSS_PLL_REG_W(dp_res->phy_base, + DP_PHY_CFG, 0x01); + MDSS_PLL_REG_W(dp_res->phy_base, + DP_PHY_CFG, 0x09); + /* Make sure the PHY register writes are done */ + wmb(); + MDSS_PLL_REG_W(dp_res->pll_base, + QSERDES_COM_RESETSM_CNTRL, 0x20); + /* Make sure the PLL register writes are done */ + wmb(); + /* poll for PLL ready status */ + if (readl_poll_timeout_atomic((dp_res->pll_base + + QSERDES_COM_C_READY_STATUS), + status, + ((status & BIT(0)) > 0), + DP_PLL_POLL_SLEEP_US, + DP_PLL_POLL_TIMEOUT_US)) { + pr_err("%s: C_READY status is not high. Status=%x\n", + __func__, status); + rc = -EINVAL; + goto lock_err; + } + + MDSS_PLL_REG_W(dp_res->phy_base, + DP_PHY_CFG, 0x19); + /* Make sure the PHY register writes are done */ + wmb(); + /* poll for PHY ready status */ + if (readl_poll_timeout_atomic((dp_res->phy_base + + DP_PHY_STATUS), + status, + ((status & BIT(1)) > 0), + DP_PLL_POLL_SLEEP_US, + DP_PLL_POLL_TIMEOUT_US)) { + pr_err("%s: Phy_ready is not high. Status=%x\n", + __func__, status); + rc = -EINVAL; + goto lock_err; + } + + pr_debug("%s: PLL is locked\n", __func__); + + if (ln_cnt == 1) { + bias_en = 0x3e; + drvr_en = 0x13; + } else { + bias_en = 0x3f; + drvr_en = 0x10; + } + + if (ln_cnt != 4) { + if (orientation == ORIENTATION_CC1) { + MDSS_PLL_REG_W(dp_res->phy_base, + QSERDES_TX1_OFFSET + TXn_TRANSCEIVER_BIAS_EN, + bias_en); + MDSS_PLL_REG_W(dp_res->phy_base, + QSERDES_TX1_OFFSET + TXn_HIGHZ_DRVR_EN, + drvr_en); + } else { + MDSS_PLL_REG_W(dp_res->phy_base, + QSERDES_TX0_OFFSET + TXn_TRANSCEIVER_BIAS_EN, + bias_en); + MDSS_PLL_REG_W(dp_res->phy_base, + QSERDES_TX0_OFFSET + TXn_HIGHZ_DRVR_EN, + drvr_en); + } + } else { + MDSS_PLL_REG_W(dp_res->phy_base, + QSERDES_TX0_OFFSET + TXn_TRANSCEIVER_BIAS_EN, + bias_en); + MDSS_PLL_REG_W(dp_res->phy_base, + QSERDES_TX0_OFFSET + TXn_HIGHZ_DRVR_EN, + drvr_en); + MDSS_PLL_REG_W(dp_res->phy_base, + QSERDES_TX1_OFFSET + TXn_TRANSCEIVER_BIAS_EN, + bias_en); + MDSS_PLL_REG_W(dp_res->phy_base, + QSERDES_TX1_OFFSET + TXn_HIGHZ_DRVR_EN, + drvr_en); + } + + MDSS_PLL_REG_W(dp_res->phy_base, + QSERDES_TX0_OFFSET + TXn_TX_POL_INV, + 0x0a); + MDSS_PLL_REG_W(dp_res->phy_base, + QSERDES_TX1_OFFSET + TXn_TX_POL_INV, + 0x0a); + MDSS_PLL_REG_W(dp_res->phy_base, + DP_PHY_CFG, 0x18); + udelay(2000); + + MDSS_PLL_REG_W(dp_res->phy_base, + DP_PHY_CFG, 0x19); + + /* + * Make sure all the register writes are completed before + * doing any other operation + */ + wmb(); + + if (vco->rate == DP_VCO_HSCLK_RATE_2700MHZDIV1000) + lane_mode = 0xc6; + else + lane_mode = 0xf6; + + MDSS_PLL_REG_W(dp_res->phy_base, + QSERDES_TX0_OFFSET + TXn_LANE_MODE_1, + lane_mode); + MDSS_PLL_REG_W(dp_res->phy_base, + QSERDES_TX1_OFFSET + TXn_LANE_MODE_1, + lane_mode); + + MDSS_PLL_REG_W(dp_res->phy_base, + QSERDES_TX0_OFFSET + TXn_CLKBUF_ENABLE, + 0x1f); + MDSS_PLL_REG_W(dp_res->phy_base, + QSERDES_TX1_OFFSET + TXn_CLKBUF_ENABLE, + 0x1f); + MDSS_PLL_REG_W(dp_res->phy_base, + QSERDES_TX0_OFFSET + TXn_CLKBUF_ENABLE, + 0x0f); + MDSS_PLL_REG_W(dp_res->phy_base, + QSERDES_TX1_OFFSET + TXn_CLKBUF_ENABLE, + 0x0f); + /* + * Make sure all the register writes are completed before + * doing any other operation + */ + wmb(); + + MDSS_PLL_REG_W(dp_res->phy_base, + DP_PHY_CFG, 0x09); + udelay(2000); + + MDSS_PLL_REG_W(dp_res->phy_base, + DP_PHY_CFG, 0x19); + udelay(2000); + /* poll for PHY ready status */ + if (readl_poll_timeout_atomic((dp_res->phy_base + + DP_PHY_STATUS), + status, + ((status & BIT(1)) > 0), + DP_PLL_POLL_SLEEP_US, + DP_PLL_POLL_TIMEOUT_US)) { + pr_err("%s: Lane_mode: Phy_ready is not high. Status=%x\n", + __func__, status); + rc = -EINVAL; + goto lock_err; + } + + MDSS_PLL_REG_W(dp_res->phy_base, + QSERDES_TX0_OFFSET + TXn_TX_DRV_LVL, + 0x2a); + MDSS_PLL_REG_W(dp_res->phy_base, + QSERDES_TX1_OFFSET + TXn_TX_DRV_LVL, + 0x2a); + MDSS_PLL_REG_W(dp_res->phy_base, + QSERDES_TX0_OFFSET + TXn_TX_EMP_POST1_LVL, + 0x20); + MDSS_PLL_REG_W(dp_res->phy_base, + QSERDES_TX1_OFFSET + TXn_TX_EMP_POST1_LVL, + 0x20); + MDSS_PLL_REG_W(dp_res->phy_base, + QSERDES_TX0_OFFSET + TXn_RES_CODE_LANE_OFFSET_TX, + 0x11); + MDSS_PLL_REG_W(dp_res->phy_base, + QSERDES_TX1_OFFSET + TXn_RES_CODE_LANE_OFFSET_TX, + 0x11); + MDSS_PLL_REG_W(dp_res->phy_base, + QSERDES_TX0_OFFSET + TXn_RES_CODE_LANE_OFFSET_RX, + 0x11); + MDSS_PLL_REG_W(dp_res->phy_base, + QSERDES_TX1_OFFSET + TXn_RES_CODE_LANE_OFFSET_RX, + 0x11); + /* Make sure the PHY register writes are done */ + wmb(); + +lock_err: + return rc; +} + +static int dp_pll_disable(struct clk *c) +{ + int rc = 0; + struct dp_pll_vco_clk *vco = mdss_dp_to_vco_clk(c); + struct mdss_pll_resources *dp_res = vco->priv; + + /* Assert DP PHY power down */ + MDSS_PLL_REG_W(dp_res->phy_base, + DP_PHY_PD_CTL, 0x2); + /* + * Make sure all the register writes to disable PLL are + * completed before doing any other operation + */ + wmb(); + + return rc; +} + + +int dp_vco_prepare(struct clk *c) +{ + int rc = 0; + struct dp_pll_vco_clk *vco = mdss_dp_to_vco_clk(c); + struct mdss_pll_resources *dp_pll_res = vco->priv; + + DEV_DBG("rate=%ld\n", vco->rate); + rc = mdss_pll_resource_enable(dp_pll_res, true); + if (rc) { + pr_err("Failed to enable mdss DP pll resources\n"); + goto error; + } + + rc = dp_pll_enable(c); + if (rc) { + mdss_pll_resource_enable(dp_pll_res, false); + pr_err("ndx=%d failed to enable dp pll\n", + dp_pll_res->index); + goto error; + } + + mdss_pll_resource_enable(dp_pll_res, false); +error: + return rc; +} + +void dp_vco_unprepare(struct clk *c) +{ + struct dp_pll_vco_clk *vco = mdss_dp_to_vco_clk(c); + struct mdss_pll_resources *io = vco->priv; + + if (!io) { + DEV_ERR("Invalid input parameter\n"); + return; + } + + if (!io->pll_on && + mdss_pll_resource_enable(io, true)) { + DEV_ERR("pll resource can't be enabled\n"); + return; + } + dp_pll_disable(c); + + io->handoff_resources = false; + mdss_pll_resource_enable(io, false); + io->pll_on = false; +} + +int dp_vco_set_rate(struct clk *c, unsigned long rate) +{ + struct dp_pll_vco_clk *vco = mdss_dp_to_vco_clk(c); + struct mdss_pll_resources *io = vco->priv; + int rc; + + rc = mdss_pll_resource_enable(io, true); + if (rc) { + DEV_ERR("pll resource can't be enabled\n"); + return rc; + } + + DEV_DBG("DP lane CLK rate=%ld\n", rate); + + rc = dp_config_vco_rate(vco, rate); + if (rc) + DEV_ERR("%s: Failed to set clk rate\n", __func__); + + mdss_pll_resource_enable(io, false); + + vco->rate = rate; + + return 0; +} + +unsigned long dp_vco_get_rate(struct clk *c) +{ + struct dp_pll_vco_clk *vco = mdss_dp_to_vco_clk(c); + int rc; + u32 div, hsclk_div, link2xclk_div = 0; + u64 vco_rate; + struct mdss_pll_resources *pll = vco->priv; + + rc = mdss_pll_resource_enable(pll, true); + if (rc) { + pr_err("Failed to enable mdss DP pll=%d\n", pll->index); + return rc; + } + + div = MDSS_PLL_REG_R(pll->pll_base, QSERDES_COM_HSCLK_SEL); + div &= 0x0f; + + if (div == 12) + hsclk_div = 5; /* Default */ + else if (div == 4) + hsclk_div = 3; + else if (div == 0) + hsclk_div = 2; + else { + pr_debug("unknown divider. forcing to default\n"); + hsclk_div = 5; + } + + div = MDSS_PLL_REG_R(pll->phy_base, DP_PHY_MODE); + + if (div & 0x58) + pr_err("%s: DP PAR Rate not correct\n", __func__); + + if ((div & 0x3) == 1) + link2xclk_div = 10; + else if ((div & 0x3) == 0) + link2xclk_div = 5; + else + pr_err("%s: unsupported div. Phy_mode: %d\n", __func__, div); + + if (link2xclk_div == 10) { + vco_rate = DP_VCO_HSCLK_RATE_2700MHZDIV1000; + } else { + if (hsclk_div == 5) + vco_rate = DP_VCO_HSCLK_RATE_1620MHZDIV1000; + else if (hsclk_div == 3) + vco_rate = DP_VCO_HSCLK_RATE_2700MHZDIV1000; + else + vco_rate = DP_VCO_HSCLK_RATE_5400MHZDIV1000; + } + + pr_debug("returning vco rate = %lu\n", (unsigned long)vco_rate); + + mdss_pll_resource_enable(pll, false); + + return (unsigned long)vco_rate; +} + +long dp_vco_round_rate(struct clk *c, unsigned long rate) +{ + unsigned long rrate = rate; + struct dp_pll_vco_clk *vco = mdss_dp_to_vco_clk(c); + + if (rate <= vco->min_rate) + rrate = vco->min_rate; + else if (rate <= DP_VCO_HSCLK_RATE_2700MHZDIV1000) + rrate = DP_VCO_HSCLK_RATE_2700MHZDIV1000; + else + rrate = vco->max_rate; + + pr_debug("%s: rrate=%ld\n", __func__, rrate); + + return rrate; +} + +enum handoff dp_vco_handoff(struct clk *c) +{ + enum handoff ret = HANDOFF_DISABLED_CLK; + struct dp_pll_vco_clk *vco = mdss_dp_to_vco_clk(c); + struct mdss_pll_resources *io = vco->priv; + + if (mdss_pll_resource_enable(io, true)) { + DEV_ERR("pll resource can't be enabled\n"); + return ret; + } + + if (dp_pll_lock_status(io)) { + io->pll_on = true; + c->rate = dp_vco_get_rate(c); + io->handoff_resources = true; + ret = HANDOFF_ENABLED_CLK; + } else { + mdss_pll_resource_enable(io, false); + ret = HANDOFF_DISABLED_CLK; + DEV_DBG("%s: PLL not locked\n", __func__); + } + + DEV_DBG("done, ret=%d\n", ret); + return ret; +} diff -Nruw linux-4.4.115-fbx/drivers/clk/msm./mdss/mdss-dp-pll.h linux-4.4.115-fbx/drivers/clk/msm/mdss/mdss-dp-pll.h --- linux-4.4.115-fbx/drivers/clk/msm./mdss/mdss-dp-pll.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-4.4.115-fbx/drivers/clk/msm/mdss/mdss-dp-pll.h 2019-01-22 16:16:23.019242024 +0100 @@ -0,0 +1,36 @@ +/* Copyright (c) 2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef __MDSS_DP_PLL_H +#define __MDSS_DP_PLL_H + +struct dp_pll_vco_clk { + unsigned long rate; /* current vco rate */ + u64 min_rate; /* min vco rate */ + u64 max_rate; /* max vco rate */ + void *priv; + + struct clk c; +}; + +static inline struct dp_pll_vco_clk *mdss_dp_to_vco_clk(struct clk *clk) +{ + return container_of(clk, struct dp_pll_vco_clk, c); +} + +int dp_pll_clock_register_8998(struct platform_device *pdev, + struct mdss_pll_resources *pll_res); + + +#endif /* __MDSS_DP_PLL_H */ + diff -Nruw linux-4.4.115-fbx/drivers/clk/msm./mdss/mdss-dsi-pll-8996.c linux-4.4.115-fbx/drivers/clk/msm/mdss/mdss-dsi-pll-8996.c --- linux-4.4.115-fbx/drivers/clk/msm./mdss/mdss-dsi-pll-8996.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-4.4.115-fbx/drivers/clk/msm/mdss/mdss-dsi-pll-8996.c 2019-01-22 16:16:23.019242024 +0100 @@ -0,0 +1,566 @@ +/* Copyright (c) 2015-2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#define pr_fmt(fmt) "%s: " fmt, __func__ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "mdss-pll.h" +#include "mdss-dsi-pll.h" +#include "mdss-dsi-pll-8996.h" + +#define VCO_DELAY_USEC 1 + +static struct dsi_pll_db pll_db[DSI_PLL_NUM]; + +static struct clk_ops n2_clk_src_ops; +static struct clk_ops shadow_n2_clk_src_ops; +static struct clk_ops byte_clk_src_ops; +static struct clk_ops post_n1_div_clk_src_ops; +static struct clk_ops shadow_post_n1_div_clk_src_ops; + +static struct clk_ops clk_ops_gen_mux_dsi; + +/* Op structures */ +static struct clk_ops clk_ops_dsi_vco = { + .set_rate = pll_vco_set_rate_8996, + .round_rate = pll_vco_round_rate_8996, + .handoff = pll_vco_handoff_8996, + .prepare = pll_vco_prepare_8996, + .unprepare = pll_vco_unprepare_8996, +}; + +static struct clk_div_ops post_n1_div_ops = { + .set_div = post_n1_div_set_div, + .get_div = post_n1_div_get_div, +}; + +static struct clk_div_ops n2_div_ops = { /* hr_oclk3 */ + .set_div = n2_div_set_div, + .get_div = n2_div_get_div, +}; + +static struct clk_mux_ops mdss_byte_mux_ops = { + .set_mux_sel = set_mdss_byte_mux_sel_8996, + .get_mux_sel = get_mdss_byte_mux_sel_8996, +}; + +static struct clk_mux_ops mdss_pixel_mux_ops = { + .set_mux_sel = set_mdss_pixel_mux_sel_8996, + .get_mux_sel = get_mdss_pixel_mux_sel_8996, +}; + +/* Shadow ops for dynamic refresh */ +static struct clk_ops clk_ops_shadow_dsi_vco = { + .set_rate = shadow_pll_vco_set_rate_8996, + .round_rate = pll_vco_round_rate_8996, + .handoff = shadow_pll_vco_handoff_8996, +}; + +static struct clk_div_ops shadow_post_n1_div_ops = { + .set_div = post_n1_div_set_div, +}; + +static struct clk_div_ops shadow_n2_div_ops = { + .set_div = shadow_n2_div_set_div, +}; + +static struct dsi_pll_vco_clk dsi0pll_vco_clk = { + .ref_clk_rate = 19200000UL, + .min_rate = 1300000000UL, + .max_rate = 2600000000UL, + .pll_en_seq_cnt = 1, + .pll_enable_seqs[0] = dsi_pll_enable_seq_8996, + .c = { + .dbg_name = "dsi0pll_vco_clk_8996", + .ops = &clk_ops_dsi_vco, + CLK_INIT(dsi0pll_vco_clk.c), + }, +}; + +static struct dsi_pll_vco_clk dsi0pll_shadow_vco_clk = { + .ref_clk_rate = 19200000u, + .min_rate = 1300000000u, + .max_rate = 2600000000u, + .c = { + .dbg_name = "dsi0pll_shadow_vco_clk", + .ops = &clk_ops_shadow_dsi_vco, + CLK_INIT(dsi0pll_shadow_vco_clk.c), + }, +}; + +static struct dsi_pll_vco_clk dsi1pll_vco_clk = { + .ref_clk_rate = 19200000UL, + .min_rate = 1300000000UL, + .max_rate = 2600000000UL, + .pll_en_seq_cnt = 1, + .pll_enable_seqs[0] = dsi_pll_enable_seq_8996, + .c = { + .dbg_name = "dsi1pll_vco_clk_8996", + .ops = &clk_ops_dsi_vco, + CLK_INIT(dsi1pll_vco_clk.c), + }, +}; + +static struct dsi_pll_vco_clk dsi1pll_shadow_vco_clk = { + .ref_clk_rate = 19200000u, + .min_rate = 1300000000u, + .max_rate = 2600000000u, + .pll_en_seq_cnt = 1, + .pll_enable_seqs[0] = dsi_pll_enable_seq_8996, + .c = { + .dbg_name = "dsi1pll_shadow_vco_clk", + .ops = &clk_ops_shadow_dsi_vco, + CLK_INIT(dsi1pll_shadow_vco_clk.c), + }, +}; + +static struct div_clk dsi0pll_post_n1_div_clk = { + .data = { + .max_div = 15, + .min_div = 1, + }, + .ops = &post_n1_div_ops, + .c = { + .parent = &dsi0pll_vco_clk.c, + .dbg_name = "dsi0pll_post_n1_div_clk", + .ops = &post_n1_div_clk_src_ops, + .flags = CLKFLAG_NO_RATE_CACHE, + CLK_INIT(dsi0pll_post_n1_div_clk.c), + }, +}; + +static struct div_clk dsi0pll_shadow_post_n1_div_clk = { + .data = { + .max_div = 15, + .min_div = 1, + }, + .ops = &shadow_post_n1_div_ops, + .c = { + .parent = &dsi0pll_shadow_vco_clk.c, + .dbg_name = "dsi0pll_shadow_post_n1_div_clk", + .ops = &shadow_post_n1_div_clk_src_ops, + .flags = CLKFLAG_NO_RATE_CACHE, + CLK_INIT(dsi0pll_shadow_post_n1_div_clk.c), + }, +}; + +static struct div_clk dsi1pll_post_n1_div_clk = { + .data = { + .max_div = 15, + .min_div = 1, + }, + .ops = &post_n1_div_ops, + .c = { + .parent = &dsi1pll_vco_clk.c, + .dbg_name = "dsi1pll_post_n1_div_clk", + .ops = &post_n1_div_clk_src_ops, + .flags = CLKFLAG_NO_RATE_CACHE, + CLK_INIT(dsi1pll_post_n1_div_clk.c), + }, +}; + +static struct div_clk dsi1pll_shadow_post_n1_div_clk = { + .data = { + .max_div = 15, + .min_div = 1, + }, + .ops = &shadow_post_n1_div_ops, + .c = { + .parent = &dsi1pll_shadow_vco_clk.c, + .dbg_name = "dsi1pll_shadow_post_n1_div_clk", + .ops = &shadow_post_n1_div_clk_src_ops, + .flags = CLKFLAG_NO_RATE_CACHE, + CLK_INIT(dsi1pll_shadow_post_n1_div_clk.c), + }, +}; + +static struct div_clk dsi0pll_n2_div_clk = { + .data = { + .max_div = 15, + .min_div = 1, + }, + .ops = &n2_div_ops, + .c = { + .parent = &dsi0pll_post_n1_div_clk.c, + .dbg_name = "dsi0pll_n2_div_clk", + .ops = &n2_clk_src_ops, + .flags = CLKFLAG_NO_RATE_CACHE, + CLK_INIT(dsi0pll_n2_div_clk.c), + }, +}; + +static struct div_clk dsi0pll_shadow_n2_div_clk = { + .data = { + .max_div = 15, + .min_div = 1, + }, + .ops = &shadow_n2_div_ops, + .c = { + .parent = &dsi0pll_shadow_post_n1_div_clk.c, + .dbg_name = "dsi0pll_shadow_n2_div_clk", + .ops = &shadow_n2_clk_src_ops, + .flags = CLKFLAG_NO_RATE_CACHE, + CLK_INIT(dsi0pll_shadow_n2_div_clk.c), + }, +}; + +static struct div_clk dsi1pll_n2_div_clk = { + .data = { + .max_div = 15, + .min_div = 1, + }, + .ops = &n2_div_ops, + .c = { + .parent = &dsi1pll_post_n1_div_clk.c, + .dbg_name = "dsi1pll_n2_div_clk", + .ops = &n2_clk_src_ops, + .flags = CLKFLAG_NO_RATE_CACHE, + CLK_INIT(dsi1pll_n2_div_clk.c), + }, +}; + +static struct div_clk dsi1pll_shadow_n2_div_clk = { + .data = { + .max_div = 15, + .min_div = 1, + }, + .ops = &shadow_n2_div_ops, + .c = { + .parent = &dsi1pll_shadow_post_n1_div_clk.c, + .dbg_name = "dsi1pll_shadow_n2_div_clk", + .ops = &shadow_n2_clk_src_ops, + .flags = CLKFLAG_NO_RATE_CACHE, + CLK_INIT(dsi1pll_shadow_n2_div_clk.c), + }, +}; + +static struct div_clk dsi0pll_pixel_clk_src = { + .data = { + .div = 2, + .min_div = 2, + .max_div = 2, + }, + .c = { + .parent = &dsi0pll_n2_div_clk.c, + .dbg_name = "dsi0pll_pixel_clk_src", + .ops = &clk_ops_div, + .flags = CLKFLAG_NO_RATE_CACHE, + CLK_INIT(dsi0pll_pixel_clk_src.c), + }, +}; + +static struct div_clk dsi0pll_shadow_pixel_clk_src = { + .data = { + .div = 2, + .min_div = 2, + .max_div = 2, + }, + .c = { + .parent = &dsi0pll_shadow_n2_div_clk.c, + .dbg_name = "dsi0pll_shadow_pixel_clk_src", + .ops = &clk_ops_div, + .flags = CLKFLAG_NO_RATE_CACHE, + CLK_INIT(dsi0pll_shadow_pixel_clk_src.c), + }, +}; + +static struct div_clk dsi1pll_pixel_clk_src = { + .data = { + .div = 2, + .min_div = 2, + .max_div = 2, + }, + .c = { + .parent = &dsi1pll_n2_div_clk.c, + .dbg_name = "dsi1pll_pixel_clk_src", + .ops = &clk_ops_div, + .flags = CLKFLAG_NO_RATE_CACHE, + CLK_INIT(dsi1pll_pixel_clk_src.c), + }, +}; + +static struct div_clk dsi1pll_shadow_pixel_clk_src = { + .data = { + .div = 2, + .min_div = 2, + .max_div = 2, + }, + .c = { + .parent = &dsi1pll_shadow_n2_div_clk.c, + .dbg_name = "dsi1pll_shadow_pixel_clk_src", + .ops = &clk_ops_div, + .flags = CLKFLAG_NO_RATE_CACHE, + CLK_INIT(dsi1pll_shadow_pixel_clk_src.c), + }, +}; + +static struct mux_clk dsi0pll_pixel_clk_mux = { + .num_parents = 2, + .parents = (struct clk_src[]) { + {&dsi0pll_pixel_clk_src.c, 0}, + {&dsi0pll_shadow_pixel_clk_src.c, 1}, + }, + .ops = &mdss_pixel_mux_ops, + .c = { + .parent = &dsi0pll_pixel_clk_src.c, + .dbg_name = "dsi0pll_pixel_clk_mux", + .ops = &clk_ops_gen_mux_dsi, + .flags = CLKFLAG_NO_RATE_CACHE, + CLK_INIT(dsi0pll_pixel_clk_mux.c), + } +}; + +static struct mux_clk dsi1pll_pixel_clk_mux = { + .num_parents = 2, + .parents = (struct clk_src[]) { + {&dsi1pll_pixel_clk_src.c, 0}, + {&dsi1pll_shadow_pixel_clk_src.c, 1}, + }, + .ops = &mdss_pixel_mux_ops, + .c = { + .parent = &dsi1pll_pixel_clk_src.c, + .dbg_name = "dsi1pll_pixel_clk_mux", + .ops = &clk_ops_gen_mux_dsi, + .flags = CLKFLAG_NO_RATE_CACHE, + CLK_INIT(dsi1pll_pixel_clk_mux.c), + } +}; + +static struct div_clk dsi0pll_byte_clk_src = { + .data = { + .div = 8, + .min_div = 8, + .max_div = 8, + }, + .c = { + .parent = &dsi0pll_post_n1_div_clk.c, + .dbg_name = "dsi0pll_byte_clk_src", + .ops = &clk_ops_div, + CLK_INIT(dsi0pll_byte_clk_src.c), + }, +}; + +static struct div_clk dsi0pll_shadow_byte_clk_src = { + .data = { + .div = 8, + .min_div = 8, + .max_div = 8, + }, + .c = { + .parent = &dsi0pll_shadow_post_n1_div_clk.c, + .dbg_name = "dsi0pll_shadow_byte_clk_src", + .ops = &clk_ops_div, + CLK_INIT(dsi0pll_shadow_byte_clk_src.c), + }, +}; + +static struct div_clk dsi1pll_byte_clk_src = { + .data = { + .div = 8, + .min_div = 8, + .max_div = 8, + }, + .c = { + .parent = &dsi1pll_post_n1_div_clk.c, + .dbg_name = "dsi1pll_byte_clk_src", + .ops = &clk_ops_div, + CLK_INIT(dsi1pll_byte_clk_src.c), + }, +}; + +static struct div_clk dsi1pll_shadow_byte_clk_src = { + .data = { + .div = 8, + .min_div = 8, + .max_div = 8, + }, + .c = { + .parent = &dsi1pll_shadow_post_n1_div_clk.c, + .dbg_name = "dsi1pll_shadow_byte_clk_src", + .ops = &clk_ops_div, + CLK_INIT(dsi1pll_shadow_byte_clk_src.c), + }, +}; + +static struct mux_clk dsi0pll_byte_clk_mux = { + .num_parents = 2, + .parents = (struct clk_src[]) { + {&dsi0pll_byte_clk_src.c, 0}, + {&dsi0pll_shadow_byte_clk_src.c, 1}, + }, + .ops = &mdss_byte_mux_ops, + .c = { + .parent = &dsi0pll_byte_clk_src.c, + .dbg_name = "dsi0pll_byte_clk_mux", + .ops = &clk_ops_gen_mux_dsi, + .flags = CLKFLAG_NO_RATE_CACHE, + CLK_INIT(dsi0pll_byte_clk_mux.c), + } +}; +static struct mux_clk dsi1pll_byte_clk_mux = { + .num_parents = 2, + .parents = (struct clk_src[]) { + {&dsi1pll_byte_clk_src.c, 0}, + {&dsi1pll_shadow_byte_clk_src.c, 1}, + }, + .ops = &mdss_byte_mux_ops, + .c = { + .parent = &dsi1pll_byte_clk_src.c, + .dbg_name = "dsi1pll_byte_clk_mux", + .ops = &clk_ops_gen_mux_dsi, + .flags = CLKFLAG_NO_RATE_CACHE, + CLK_INIT(dsi1pll_byte_clk_mux.c), + } +}; + +static struct clk_lookup mdss_dsi_pllcc_8996[] = { + CLK_LIST(dsi0pll_byte_clk_mux), + CLK_LIST(dsi0pll_byte_clk_src), + CLK_LIST(dsi0pll_pixel_clk_mux), + CLK_LIST(dsi0pll_pixel_clk_src), + CLK_LIST(dsi0pll_n2_div_clk), + CLK_LIST(dsi0pll_post_n1_div_clk), + CLK_LIST(dsi0pll_vco_clk), + CLK_LIST(dsi0pll_shadow_byte_clk_src), + CLK_LIST(dsi0pll_shadow_pixel_clk_src), + CLK_LIST(dsi0pll_shadow_n2_div_clk), + CLK_LIST(dsi0pll_shadow_post_n1_div_clk), + CLK_LIST(dsi0pll_shadow_vco_clk), +}; + +static struct clk_lookup mdss_dsi_pllcc_8996_1[] = { + CLK_LIST(dsi1pll_byte_clk_mux), + CLK_LIST(dsi1pll_byte_clk_src), + CLK_LIST(dsi1pll_pixel_clk_mux), + CLK_LIST(dsi1pll_pixel_clk_src), + CLK_LIST(dsi1pll_n2_div_clk), + CLK_LIST(dsi1pll_post_n1_div_clk), + CLK_LIST(dsi1pll_vco_clk), + CLK_LIST(dsi1pll_shadow_byte_clk_src), + CLK_LIST(dsi1pll_shadow_pixel_clk_src), + CLK_LIST(dsi1pll_shadow_n2_div_clk), + CLK_LIST(dsi1pll_shadow_post_n1_div_clk), + CLK_LIST(dsi1pll_shadow_vco_clk), +}; + +int dsi_pll_clock_register_8996(struct platform_device *pdev, + struct mdss_pll_resources *pll_res) +{ + int rc = 0, ndx; + int const ssc_freq_default = 31500; /* default h/w recommended value */ + int const ssc_ppm_default = 5000; /* default h/w recommended value */ + struct dsi_pll_db *pdb; + + if (!pdev || !pdev->dev.of_node) { + pr_err("Invalid input parameters\n"); + return -EINVAL; + } + + if (!pll_res || !pll_res->pll_base) { + pr_err("Invalid PLL resources\n"); + return -EPROBE_DEFER; + } + + if (pll_res->index >= DSI_PLL_NUM) { + pr_err("pll ndx=%d is NOT supported\n", pll_res->index); + return -EINVAL; + } + + ndx = pll_res->index; + pdb = &pll_db[ndx]; + pll_res->priv = pdb; + pdb->pll = pll_res; + ndx++; + ndx %= DSI_PLL_NUM; + pdb->next = &pll_db[ndx]; + + /* Set clock source operations */ + + /* hr_oclk3, pixel */ + n2_clk_src_ops = clk_ops_slave_div; + n2_clk_src_ops.prepare = mdss_pll_div_prepare; + + shadow_n2_clk_src_ops = clk_ops_slave_div; + + /* hr_ockl2, byte, vco pll */ + post_n1_div_clk_src_ops = clk_ops_div; + post_n1_div_clk_src_ops.prepare = mdss_pll_div_prepare; + + shadow_post_n1_div_clk_src_ops = clk_ops_div; + + byte_clk_src_ops = clk_ops_div; + byte_clk_src_ops.prepare = mdss_pll_div_prepare; + + clk_ops_gen_mux_dsi = clk_ops_gen_mux; + clk_ops_gen_mux_dsi.round_rate = parent_round_rate; + clk_ops_gen_mux_dsi.set_rate = parent_set_rate; + + if (pll_res->ssc_en) { + if (!pll_res->ssc_freq) + pll_res->ssc_freq = ssc_freq_default; + if (!pll_res->ssc_ppm) + pll_res->ssc_ppm = ssc_ppm_default; + } + + /* Set client data to mux, div and vco clocks. */ + if (pll_res->index == DSI_PLL_1) { + dsi1pll_byte_clk_src.priv = pll_res; + dsi1pll_pixel_clk_src.priv = pll_res; + dsi1pll_post_n1_div_clk.priv = pll_res; + dsi1pll_n2_div_clk.priv = pll_res; + dsi1pll_vco_clk.priv = pll_res; + + dsi1pll_shadow_byte_clk_src.priv = pll_res; + dsi1pll_shadow_pixel_clk_src.priv = pll_res; + dsi1pll_shadow_post_n1_div_clk.priv = pll_res; + dsi1pll_shadow_n2_div_clk.priv = pll_res; + dsi1pll_shadow_vco_clk.priv = pll_res; + + pll_res->vco_delay = VCO_DELAY_USEC; + rc = of_msm_clock_register(pdev->dev.of_node, + mdss_dsi_pllcc_8996_1, + ARRAY_SIZE(mdss_dsi_pllcc_8996_1)); + } else { + dsi0pll_byte_clk_src.priv = pll_res; + dsi0pll_pixel_clk_src.priv = pll_res; + dsi0pll_post_n1_div_clk.priv = pll_res; + dsi0pll_n2_div_clk.priv = pll_res; + dsi0pll_vco_clk.priv = pll_res; + + dsi0pll_shadow_byte_clk_src.priv = pll_res; + dsi0pll_shadow_pixel_clk_src.priv = pll_res; + dsi0pll_shadow_post_n1_div_clk.priv = pll_res; + dsi0pll_shadow_n2_div_clk.priv = pll_res; + dsi0pll_shadow_vco_clk.priv = pll_res; + + pll_res->vco_delay = VCO_DELAY_USEC; + rc = of_msm_clock_register(pdev->dev.of_node, + mdss_dsi_pllcc_8996, + ARRAY_SIZE(mdss_dsi_pllcc_8996)); + } + + if (!rc) { + pr_info("Registered DSI PLL ndx=%d clocks successfully\n", + pll_res->index); + } + + return rc; +} diff -Nruw linux-4.4.115-fbx/drivers/clk/msm./mdss/mdss-dsi-pll-8996.h linux-4.4.115-fbx/drivers/clk/msm/mdss/mdss-dsi-pll-8996.h --- linux-4.4.115-fbx/drivers/clk/msm./mdss/mdss-dsi-pll-8996.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-4.4.115-fbx/drivers/clk/msm/mdss/mdss-dsi-pll-8996.h 2019-01-22 16:16:23.019242024 +0100 @@ -0,0 +1,221 @@ +/* Copyright (c) 2015-2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef MDSS_DSI_PLL_8996_H +#define MDSS_DSI_PLL_8996_H + +#define DSIPHY_CMN_CLK_CFG0 0x0010 +#define DSIPHY_CMN_CLK_CFG1 0x0014 +#define DSIPHY_CMN_GLBL_TEST_CTRL 0x0018 + +#define DSIPHY_CMN_PLL_CNTRL 0x0048 +#define DSIPHY_CMN_CTRL_0 0x001c +#define DSIPHY_CMN_CTRL_1 0x0020 + +#define DSIPHY_CMN_LDO_CNTRL 0x004c + +#define DSIPHY_PLL_IE_TRIM 0x0400 +#define DSIPHY_PLL_IP_TRIM 0x0404 + +#define DSIPHY_PLL_IPTAT_TRIM 0x0410 + +#define DSIPHY_PLL_CLKBUFLR_EN 0x041c + +#define DSIPHY_PLL_SYSCLK_EN_RESET 0x0428 +#define DSIPHY_PLL_RESETSM_CNTRL 0x042c +#define DSIPHY_PLL_RESETSM_CNTRL2 0x0430 +#define DSIPHY_PLL_RESETSM_CNTRL3 0x0434 +#define DSIPHY_PLL_RESETSM_CNTRL4 0x0438 +#define DSIPHY_PLL_RESETSM_CNTRL5 0x043c +#define DSIPHY_PLL_KVCO_DIV_REF1 0x0440 +#define DSIPHY_PLL_KVCO_DIV_REF2 0x0444 +#define DSIPHY_PLL_KVCO_COUNT1 0x0448 +#define DSIPHY_PLL_KVCO_COUNT2 0x044c +#define DSIPHY_PLL_VREF_CFG1 0x045c + +#define DSIPHY_PLL_KVCO_CODE 0x0458 + +#define DSIPHY_PLL_VCO_DIV_REF1 0x046c +#define DSIPHY_PLL_VCO_DIV_REF2 0x0470 +#define DSIPHY_PLL_VCO_COUNT1 0x0474 +#define DSIPHY_PLL_VCO_COUNT2 0x0478 +#define DSIPHY_PLL_PLLLOCK_CMP1 0x047c +#define DSIPHY_PLL_PLLLOCK_CMP2 0x0480 +#define DSIPHY_PLL_PLLLOCK_CMP3 0x0484 +#define DSIPHY_PLL_PLLLOCK_CMP_EN 0x0488 +#define DSIPHY_PLL_PLL_VCO_TUNE 0x048C +#define DSIPHY_PLL_DEC_START 0x0490 +#define DSIPHY_PLL_SSC_EN_CENTER 0x0494 +#define DSIPHY_PLL_SSC_ADJ_PER1 0x0498 +#define DSIPHY_PLL_SSC_ADJ_PER2 0x049c +#define DSIPHY_PLL_SSC_PER1 0x04a0 +#define DSIPHY_PLL_SSC_PER2 0x04a4 +#define DSIPHY_PLL_SSC_STEP_SIZE1 0x04a8 +#define DSIPHY_PLL_SSC_STEP_SIZE2 0x04ac +#define DSIPHY_PLL_DIV_FRAC_START1 0x04b4 +#define DSIPHY_PLL_DIV_FRAC_START2 0x04b8 +#define DSIPHY_PLL_DIV_FRAC_START3 0x04bc +#define DSIPHY_PLL_TXCLK_EN 0x04c0 +#define DSIPHY_PLL_PLL_CRCTRL 0x04c4 + +#define DSIPHY_PLL_RESET_SM_READY_STATUS 0x04cc + +#define DSIPHY_PLL_PLL_MISC1 0x04e8 + +#define DSIPHY_PLL_CP_SET_CUR 0x04f0 +#define DSIPHY_PLL_PLL_ICPMSET 0x04f4 +#define DSIPHY_PLL_PLL_ICPCSET 0x04f8 +#define DSIPHY_PLL_PLL_ICP_SET 0x04fc +#define DSIPHY_PLL_PLL_LPF1 0x0500 +#define DSIPHY_PLL_PLL_LPF2_POSTDIV 0x0504 +#define DSIPHY_PLL_PLL_BANDGAP 0x0508 + +#define DSI_DYNAMIC_REFRESH_PLL_CTRL15 0x050 +#define DSI_DYNAMIC_REFRESH_PLL_CTRL19 0x060 +#define DSI_DYNAMIC_REFRESH_PLL_CTRL20 0x064 +#define DSI_DYNAMIC_REFRESH_PLL_CTRL21 0x068 +#define DSI_DYNAMIC_REFRESH_PLL_CTRL22 0x06C +#define DSI_DYNAMIC_REFRESH_PLL_CTRL23 0x070 +#define DSI_DYNAMIC_REFRESH_PLL_CTRL24 0x074 +#define DSI_DYNAMIC_REFRESH_PLL_CTRL25 0x078 +#define DSI_DYNAMIC_REFRESH_PLL_CTRL26 0x07C +#define DSI_DYNAMIC_REFRESH_PLL_CTRL27 0x080 +#define DSI_DYNAMIC_REFRESH_PLL_CTRL28 0x084 +#define DSI_DYNAMIC_REFRESH_PLL_CTRL29 0x088 +#define DSI_DYNAMIC_REFRESH_PLL_UPPER_ADDR 0x094 +#define DSI_DYNAMIC_REFRESH_PLL_UPPER_ADDR2 0x098 + +struct dsi_pll_input { + u32 fref; /* 19.2 Mhz, reference clk */ + u32 fdata; /* bit clock rate */ + u32 dsiclk_sel; /* 1, reg: 0x0014 */ + u32 n2div; /* 1, reg: 0x0010, bit 4-7 */ + u32 ssc_en; /* 1, reg: 0x0494, bit 0 */ + u32 ldo_en; /* 0, reg: 0x004c, bit 0 */ + + /* fixed */ + u32 refclk_dbler_en; /* 0, reg: 0x04c0, bit 1 */ + u32 vco_measure_time; /* 5, unknown */ + u32 kvco_measure_time; /* 5, unknown */ + u32 bandgap_timer; /* 4, reg: 0x0430, bit 3 - 5 */ + u32 pll_wakeup_timer; /* 5, reg: 0x043c, bit 0 - 2 */ + u32 plllock_cnt; /* 1, reg: 0x0488, bit 1 - 2 */ + u32 plllock_rng; /* 1, reg: 0x0488, bit 3 - 4 */ + u32 ssc_center; /* 0, reg: 0x0494, bit 1 */ + u32 ssc_adj_period; /* 37, reg: 0x498, bit 0 - 9 */ + u32 ssc_spread; /* 0.005 */ + u32 ssc_freq; /* unknown */ + u32 pll_ie_trim; /* 4, reg: 0x0400 */ + u32 pll_ip_trim; /* 4, reg: 0x0404 */ + u32 pll_iptat_trim; /* reg: 0x0410 */ + u32 pll_cpcset_cur; /* 1, reg: 0x04f0, bit 0 - 2 */ + u32 pll_cpmset_cur; /* 1, reg: 0x04f0, bit 3 - 5 */ + + u32 pll_icpmset; /* 4, reg: 0x04fc, bit 3 - 5 */ + u32 pll_icpcset; /* 4, reg: 0x04fc, bit 0 - 2 */ + + u32 pll_icpmset_p; /* 0, reg: 0x04f4, bit 0 - 2 */ + u32 pll_icpmset_m; /* 0, reg: 0x04f4, bit 3 - 5 */ + + u32 pll_icpcset_p; /* 0, reg: 0x04f8, bit 0 - 2 */ + u32 pll_icpcset_m; /* 0, reg: 0x04f8, bit 3 - 5 */ + + u32 pll_lpf_res1; /* 3, reg: 0x0504, bit 0 - 3 */ + u32 pll_lpf_cap1; /* 11, reg: 0x0500, bit 0 - 3 */ + u32 pll_lpf_cap2; /* 1, reg: 0x0500, bit 4 - 7 */ + u32 pll_c3ctrl; /* 2, reg: 0x04c4 */ + u32 pll_r3ctrl; /* 1, reg: 0x04c4 */ +}; + +struct dsi_pll_output { + u32 pll_txclk_en; /* reg: 0x04c0 */ + u32 dec_start; /* reg: 0x0490 */ + u32 div_frac_start; /* reg: 0x04b4, 0x4b8, 0x04bc */ + u32 ssc_period; /* reg: 0x04a0, 0x04a4 */ + u32 ssc_step_size; /* reg: 0x04a8, 0x04ac */ + u32 plllock_cmp; /* reg: 0x047c, 0x0480, 0x0484 */ + u32 pll_vco_div_ref; /* reg: 0x046c, 0x0470 */ + u32 pll_vco_count; /* reg: 0x0474, 0x0478 */ + u32 pll_kvco_div_ref; /* reg: 0x0440, 0x0444 */ + u32 pll_kvco_count; /* reg: 0x0448, 0x044c */ + u32 pll_misc1; /* reg: 0x04e8 */ + u32 pll_lpf2_postdiv; /* reg: 0x0504 */ + u32 pll_resetsm_cntrl; /* reg: 0x042c */ + u32 pll_resetsm_cntrl2; /* reg: 0x0430 */ + u32 pll_resetsm_cntrl5; /* reg: 0x043c */ + u32 pll_kvco_code; /* reg: 0x0458 */ + + u32 cmn_clk_cfg0; /* reg: 0x0010 */ + u32 cmn_clk_cfg1; /* reg: 0x0014 */ + u32 cmn_ldo_cntrl; /* reg: 0x004c */ + + u32 pll_postdiv; /* vco */ + u32 pll_n1div; /* vco */ + u32 pll_n2div; /* hr_oclk3, pixel */ + u32 fcvo; +}; + +enum { + DSI_PLL_0, + DSI_PLL_1, + DSI_PLL_NUM +}; + +struct dsi_pll_db { + struct dsi_pll_db *next; + struct mdss_pll_resources *pll; + struct dsi_pll_input in; + struct dsi_pll_output out; + int source_setup_done; +}; + +enum { + PLL_OUTPUT_NONE, + PLL_OUTPUT_RIGHT, + PLL_OUTPUT_LEFT, + PLL_OUTPUT_BOTH +}; + +enum { + PLL_SOURCE_FROM_LEFT, + PLL_SOURCE_FROM_RIGHT +}; + +enum { + PLL_UNKNOWN, + PLL_STANDALONE, + PLL_SLAVE, + PLL_MASTER +}; + +int pll_vco_set_rate_8996(struct clk *c, unsigned long rate); +long pll_vco_round_rate_8996(struct clk *c, unsigned long rate); +enum handoff pll_vco_handoff_8996(struct clk *c); +enum handoff shadow_pll_vco_handoff_8996(struct clk *c); +int shadow_post_n1_div_set_div(struct div_clk *clk, int div); +int shadow_post_n1_div_get_div(struct div_clk *clk); +int shadow_n2_div_set_div(struct div_clk *clk, int div); +int shadow_n2_div_get_div(struct div_clk *clk); +int shadow_pll_vco_set_rate_8996(struct clk *c, unsigned long rate); +int pll_vco_prepare_8996(struct clk *c); +void pll_vco_unprepare_8996(struct clk *c); +int set_mdss_byte_mux_sel_8996(struct mux_clk *clk, int sel); +int get_mdss_byte_mux_sel_8996(struct mux_clk *clk); +int set_mdss_pixel_mux_sel_8996(struct mux_clk *clk, int sel); +int get_mdss_pixel_mux_sel_8996(struct mux_clk *clk); +int post_n1_div_set_div(struct div_clk *clk, int div); +int post_n1_div_get_div(struct div_clk *clk); +int n2_div_set_div(struct div_clk *clk, int div); +int n2_div_get_div(struct div_clk *clk); +int dsi_pll_enable_seq_8996(struct mdss_pll_resources *pll); + +#endif /* MDSS_DSI_PLL_8996_H */ diff -Nruw linux-4.4.115-fbx/drivers/clk/msm./mdss/mdss-dsi-pll-8996-util.c linux-4.4.115-fbx/drivers/clk/msm/mdss/mdss-dsi-pll-8996-util.c --- linux-4.4.115-fbx/drivers/clk/msm./mdss/mdss-dsi-pll-8996-util.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-4.4.115-fbx/drivers/clk/msm/mdss/mdss-dsi-pll-8996-util.c 2019-10-29 09:26:23.473201514 +0100 @@ -0,0 +1,1142 @@ +/* Copyright (c) 2015-2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define pr_fmt(fmt) "%s: " fmt, __func__ + +#include +#include +#include +#include +#include + +#include "mdss-pll.h" +#include "mdss-dsi-pll.h" +#include "mdss-dsi-pll-8996.h" + +#define DSI_PLL_POLL_MAX_READS 15 +#define DSI_PLL_POLL_TIMEOUT_US 1000 +#define MSM8996_DSI_PLL_REVISION_2 2 + +#define CEIL(x, y) (((x) + ((y)-1)) / (y)) + +int set_mdss_byte_mux_sel_8996(struct mux_clk *clk, int sel) +{ + return 0; +} + +int get_mdss_byte_mux_sel_8996(struct mux_clk *clk) +{ + return 0; +} + +int set_mdss_pixel_mux_sel_8996(struct mux_clk *clk, int sel) +{ + return 0; +} + +int get_mdss_pixel_mux_sel_8996(struct mux_clk *clk) +{ + return 0; +} + +static int mdss_pll_read_stored_trim_codes( + struct mdss_pll_resources *dsi_pll_res, s64 vco_clk_rate) +{ + int i; + int rc = 0; + bool found = false; + + if (!dsi_pll_res->dfps) { + rc = -EINVAL; + goto end_read; + } + + for (i = 0; i < dsi_pll_res->dfps->panel_dfps.frame_rate_cnt; i++) { + struct dfps_codes_info *codes_info = + &dsi_pll_res->dfps->codes_dfps[i]; + + pr_debug("valid=%d frame_rate=%d, vco_rate=%d, code %d %d\n", + codes_info->is_valid, codes_info->frame_rate, + codes_info->clk_rate, codes_info->pll_codes.pll_codes_1, + codes_info->pll_codes.pll_codes_2); + + if (vco_clk_rate != codes_info->clk_rate && + codes_info->is_valid) + continue; + + dsi_pll_res->cache_pll_trim_codes[0] = + codes_info->pll_codes.pll_codes_1; + dsi_pll_res->cache_pll_trim_codes[1] = + codes_info->pll_codes.pll_codes_2; + found = true; + break; + } + + if (!found) { + rc = -EINVAL; + goto end_read; + } + + pr_debug("core_kvco_code=0x%x core_vco_tune=0x%x\n", + dsi_pll_res->cache_pll_trim_codes[0], + dsi_pll_res->cache_pll_trim_codes[1]); + +end_read: + return rc; +} + +int post_n1_div_set_div(struct div_clk *clk, int div) +{ + struct mdss_pll_resources *pll = clk->priv; + struct dsi_pll_db *pdb; + struct dsi_pll_output *pout; + int rc; + u32 n1div = 0; + + rc = mdss_pll_resource_enable(pll, true); + if (rc) { + pr_err("Failed to enable mdss dsi pll resources\n"); + return rc; + } + + pdb = (struct dsi_pll_db *)pll->priv; + pout = &pdb->out; + + /* + * vco rate = bit_clk * postdiv * n1div + * vco range from 1300 to 2600 Mhz + * postdiv = 1 + * n1div = 1 to 15 + * n1div = roundup(1300Mhz / bit_clk) + * support bit_clk above 86.67Mhz + */ + + /* this is for vco/bit clock */ + pout->pll_postdiv = 1; /* fixed, divided by 1 */ + pout->pll_n1div = div; + + n1div = MDSS_PLL_REG_R(pll->pll_base, DSIPHY_CMN_CLK_CFG0); + n1div &= ~0xf; + n1div |= (div & 0xf); + MDSS_PLL_REG_W(pll->pll_base, DSIPHY_CMN_CLK_CFG0, n1div); + /* ensure n1 divider is programed */ + wmb(); + pr_debug("ndx=%d div=%d postdiv=%x n1div=%x\n", + pll->index, div, pout->pll_postdiv, pout->pll_n1div); + + mdss_pll_resource_enable(pll, false); + + return 0; +} + +int post_n1_div_get_div(struct div_clk *clk) +{ + u32 div; + int rc; + struct mdss_pll_resources *pll = clk->priv; + + if (is_gdsc_disabled(pll)) + return 0; + + rc = mdss_pll_resource_enable(pll, true); + if (rc) { + pr_err("Failed to enable mdss dsi pll resources\n"); + return rc; + } + + /* + * postdiv = 1/2/4/8 + * n1div = 1 - 15 + * fot the time being, assume postdiv = 1 + */ + + div = MDSS_PLL_REG_R(pll->pll_base, DSIPHY_CMN_CLK_CFG0); + div &= 0xF; + pr_debug("n1 div = %d\n", div); + + mdss_pll_resource_enable(pll, false); + + return div; +} + +int n2_div_set_div(struct div_clk *clk, int div) +{ + int rc; + u32 n2div; + struct mdss_pll_resources *pll = clk->priv; + struct dsi_pll_db *pdb; + struct dsi_pll_output *pout; + struct mdss_pll_resources *slave; + + rc = mdss_pll_resource_enable(pll, true); + if (rc) { + pr_err("Failed to enable mdss dsi pll resources\n"); + return rc; + } + + pdb = (struct dsi_pll_db *)pll->priv; + pout = &pdb->out; + + /* this is for pixel clock */ + n2div = MDSS_PLL_REG_R(pll->pll_base, DSIPHY_CMN_CLK_CFG0); + n2div &= ~0xf0; /* bits 4 to 7 */ + n2div |= (div << 4); + MDSS_PLL_REG_W(pll->pll_base, DSIPHY_CMN_CLK_CFG0, n2div); + + /* commit slave if split display is enabled */ + slave = pll->slave; + if (slave) + MDSS_PLL_REG_W(slave->pll_base, DSIPHY_CMN_CLK_CFG0, n2div); + + pout->pll_n2div = div; + + /* set dsiclk_sel=1 so that n2div *= 2 */ + MDSS_PLL_REG_W(pll->pll_base, DSIPHY_CMN_CLK_CFG1, 1); + pr_debug("ndx=%d div=%d n2div=%x\n", pll->index, div, n2div); + + mdss_pll_resource_enable(pll, false); + + return rc; +} + +int shadow_n2_div_set_div(struct div_clk *clk, int div) +{ + struct mdss_pll_resources *pll = clk->priv; + struct dsi_pll_db *pdb; + struct dsi_pll_output *pout; + u32 data; + + pdb = pll->priv; + pout = &pdb->out; + + pout->pll_n2div = div; + + data = (pout->pll_n1div | (pout->pll_n2div << 4)); + MDSS_DYN_PLL_REG_W(pll->dyn_pll_base, + DSI_DYNAMIC_REFRESH_PLL_CTRL19, + DSIPHY_CMN_CLK_CFG0, DSIPHY_CMN_CLK_CFG1, + data, 1); + return 0; +} + +int n2_div_get_div(struct div_clk *clk) +{ + int rc; + u32 n2div; + struct mdss_pll_resources *pll = clk->priv; + + if (is_gdsc_disabled(pll)) + return 0; + + rc = mdss_pll_resource_enable(pll, true); + if (rc) { + pr_err("Failed to enable mdss dsi pll=%d resources\n", + pll->index); + return rc; + } + + n2div = MDSS_PLL_REG_R(pll->pll_base, DSIPHY_CMN_CLK_CFG0); + n2div >>= 4; + n2div &= 0x0f; + + mdss_pll_resource_enable(pll, false); + + pr_debug("ndx=%d div=%d\n", pll->index, n2div); + + return n2div; +} + +static bool pll_is_pll_locked_8996(struct mdss_pll_resources *pll) +{ + u32 status; + bool pll_locked; + + /* poll for PLL ready status */ + if (readl_poll_timeout_atomic((pll->pll_base + + DSIPHY_PLL_RESET_SM_READY_STATUS), + status, + ((status & BIT(5)) > 0), + DSI_PLL_POLL_MAX_READS, + DSI_PLL_POLL_TIMEOUT_US)) { + pr_err("DSI PLL ndx=%d status=%x failed to Lock\n", + pll->index, status); + pll_locked = false; + } else if (readl_poll_timeout_atomic((pll->pll_base + + DSIPHY_PLL_RESET_SM_READY_STATUS), + status, + ((status & BIT(0)) > 0), + DSI_PLL_POLL_MAX_READS, + DSI_PLL_POLL_TIMEOUT_US)) { + pr_err("DSI PLL ndx=%d status=%x PLl not ready\n", + pll->index, status); + pll_locked = false; + } else { + pll_locked = true; + } + + return pll_locked; +} + +static void dsi_pll_start_8996(void __iomem *pll_base) +{ + pr_debug("start PLL at base=%p\n", pll_base); + + MDSS_PLL_REG_W(pll_base, DSIPHY_PLL_VREF_CFG1, 0x10); + MDSS_PLL_REG_W(pll_base, DSIPHY_CMN_PLL_CNTRL, 1); +} + +static void dsi_pll_stop_8996(void __iomem *pll_base) +{ + pr_debug("stop PLL at base=%p\n", pll_base); + + MDSS_PLL_REG_W(pll_base, DSIPHY_CMN_PLL_CNTRL, 0); +} + +int dsi_pll_enable_seq_8996(struct mdss_pll_resources *pll) +{ + int rc = 0; + + if (!pll) { + pr_err("Invalid PLL resources\n"); + return -EINVAL; + } + + dsi_pll_start_8996(pll->pll_base); + + /* + * both DSIPHY_PLL_CLKBUFLR_EN and DSIPHY_CMN_GLBL_TEST_CTRL + * enabled at mdss_dsi_8996_phy_config() + */ + + if (!pll_is_pll_locked_8996(pll)) { + pr_err("DSI PLL ndx=%d lock failed\n", pll->index); + rc = -EINVAL; + goto init_lock_err; + } + + pr_debug("DSI PLL ndx=%d Lock success\n", pll->index); + +init_lock_err: + return rc; +} + +static int dsi_pll_enable(struct clk *c) +{ + int i, rc = 0; + struct dsi_pll_vco_clk *vco = to_vco_clk(c); + struct mdss_pll_resources *pll = vco->priv; + + /* Try all enable sequences until one succeeds */ + for (i = 0; i < vco->pll_en_seq_cnt; i++) { + rc = vco->pll_enable_seqs[i](pll); + pr_debug("DSI PLL %s after sequence #%d\n", + rc ? "unlocked" : "locked", i + 1); + if (!rc) + break; + } + + if (rc) + pr_err("ndx=%d DSI PLL failed to lock\n", pll->index); + else + pll->pll_on = true; + + return rc; +} + +static void dsi_pll_disable(struct clk *c) +{ + struct dsi_pll_vco_clk *vco = to_vco_clk(c); + struct mdss_pll_resources *pll = vco->priv; + struct mdss_pll_resources *slave; + + if (!pll->pll_on && + mdss_pll_resource_enable(pll, true)) { + pr_err("Failed to enable mdss dsi pll=%d\n", pll->index); + return; + } + + pll->handoff_resources = false; + slave = pll->slave; + + dsi_pll_stop_8996(pll->pll_base); + + mdss_pll_resource_enable(pll, false); + + pll->pll_on = false; + + pr_debug("DSI PLL ndx=%d Disabled\n", pll->index); + return; +} + +static void mdss_dsi_pll_8996_input_init(struct mdss_pll_resources *pll, + struct dsi_pll_db *pdb) +{ + pdb->in.fref = 19200000; /* 19.2 Mhz*/ + pdb->in.fdata = 0; /* bit clock rate */ + pdb->in.dsiclk_sel = 1; /* 1, reg: 0x0014 */ + pdb->in.ssc_en = pll->ssc_en; /* 1, reg: 0x0494, bit 0 */ + pdb->in.ldo_en = 0; /* 0, reg: 0x004c, bit 0 */ + + /* fixed input */ + pdb->in.refclk_dbler_en = 0; /* 0, reg: 0x04c0, bit 1 */ + pdb->in.vco_measure_time = 5; /* 5, unknown */ + pdb->in.kvco_measure_time = 5; /* 5, unknown */ + pdb->in.bandgap_timer = 4; /* 4, reg: 0x0430, bit 3 - 5 */ + pdb->in.pll_wakeup_timer = 5; /* 5, reg: 0x043c, bit 0 - 2 */ + pdb->in.plllock_cnt = 1; /* 1, reg: 0x0488, bit 1 - 2 */ + pdb->in.plllock_rng = 0; /* 0, reg: 0x0488, bit 3 - 4 */ + pdb->in.ssc_center = pll->ssc_center;/* 0, reg: 0x0494, bit 1 */ + pdb->in.ssc_adj_period = 37; /* 37, reg: 0x498, bit 0 - 9 */ + pdb->in.ssc_spread = pll->ssc_ppm / 1000; + pdb->in.ssc_freq = pll->ssc_freq; + + pdb->in.pll_ie_trim = 4; /* 4, reg: 0x0400 */ + pdb->in.pll_ip_trim = 4; /* 4, reg: 0x0404 */ + pdb->in.pll_cpcset_cur = 1; /* 1, reg: 0x04f0, bit 0 - 2 */ + pdb->in.pll_cpmset_cur = 1; /* 1, reg: 0x04f0, bit 3 - 5 */ + pdb->in.pll_icpmset = 4; /* 4, reg: 0x04fc, bit 3 - 5 */ + pdb->in.pll_icpcset = 4; /* 4, reg: 0x04fc, bit 0 - 2 */ + pdb->in.pll_icpmset_p = 0; /* 0, reg: 0x04f4, bit 0 - 2 */ + pdb->in.pll_icpmset_m = 0; /* 0, reg: 0x04f4, bit 3 - 5 */ + pdb->in.pll_icpcset_p = 0; /* 0, reg: 0x04f8, bit 0 - 2 */ + pdb->in.pll_icpcset_m = 0; /* 0, reg: 0x04f8, bit 3 - 5 */ + pdb->in.pll_lpf_res1 = 3; /* 3, reg: 0x0504, bit 0 - 3 */ + pdb->in.pll_lpf_cap1 = 11; /* 11, reg: 0x0500, bit 0 - 3 */ + pdb->in.pll_lpf_cap2 = 1; /* 1, reg: 0x0500, bit 4 - 7 */ + pdb->in.pll_iptat_trim = 7; + pdb->in.pll_c3ctrl = 2; /* 2 */ + pdb->in.pll_r3ctrl = 1; /* 1 */ +} + +static void pll_8996_ssc_calc(struct mdss_pll_resources *pll, + struct dsi_pll_db *pdb) +{ + u32 period, ssc_period; + u32 ref, rem; + s64 step_size; + + pr_debug("%s: vco=%lld ref=%lld\n", __func__, + pll->vco_current_rate, pll->vco_ref_clk_rate); + + ssc_period = pdb->in.ssc_freq / 500; + period = (unsigned long)pll->vco_ref_clk_rate / 1000; + ssc_period = CEIL(period, ssc_period); + ssc_period -= 1; + pdb->out.ssc_period = ssc_period; + + pr_debug("%s: ssc, freq=%d spread=%d period=%d\n", __func__, + pdb->in.ssc_freq, pdb->in.ssc_spread, pdb->out.ssc_period); + + step_size = (u32)pll->vco_current_rate; + ref = pll->vco_ref_clk_rate; + ref /= 1000; + step_size = div_s64(step_size, ref); + step_size <<= 20; + step_size = div_s64(step_size, 1000); + step_size *= pdb->in.ssc_spread; + step_size = div_s64(step_size, 1000); + step_size *= (pdb->in.ssc_adj_period + 1); + + rem = 0; + step_size = div_s64_rem(step_size, ssc_period + 1, &rem); + if (rem) + step_size++; + + pr_debug("%s: step_size=%lld\n", __func__, step_size); + + step_size &= 0x0ffff; /* take lower 16 bits */ + + pdb->out.ssc_step_size = step_size; +} + +static void pll_8996_dec_frac_calc(struct mdss_pll_resources *pll, + struct dsi_pll_db *pdb) +{ + struct dsi_pll_input *pin = &pdb->in; + struct dsi_pll_output *pout = &pdb->out; + s64 multiplier = BIT(20); + s64 dec_start_multiple, dec_start, pll_comp_val; + s32 duration, div_frac_start; + s64 vco_clk_rate = pll->vco_current_rate; + s64 fref = pll->vco_ref_clk_rate; + + pr_debug("vco_clk_rate=%lld ref_clk_rate=%lld\n", + vco_clk_rate, fref); + + dec_start_multiple = div_s64(vco_clk_rate * multiplier, fref); + div_s64_rem(dec_start_multiple, multiplier, &div_frac_start); + + dec_start = div_s64(dec_start_multiple, multiplier); + + pout->dec_start = (u32)dec_start; + pout->div_frac_start = div_frac_start; + + if (pin->plllock_cnt == 0) + duration = 1024; + else if (pin->plllock_cnt == 1) + duration = 256; + else if (pin->plllock_cnt == 2) + duration = 128; + else + duration = 32; + + pll_comp_val = duration * dec_start_multiple; + pll_comp_val = div_s64(pll_comp_val, multiplier); + do_div(pll_comp_val, 10); + + pout->plllock_cmp = (u32)pll_comp_val; + + pout->pll_txclk_en = 1; + if (pll->revision == MSM8996_DSI_PLL_REVISION_2) + pout->cmn_ldo_cntrl = 0x3c; + else + pout->cmn_ldo_cntrl = 0x1c; +} + +static u32 pll_8996_kvco_slop(u32 vrate) +{ + u32 slop = 0; + + if (vrate > 1300000000UL && vrate <= 1800000000UL) + slop = 600; + else if (vrate > 1800000000UL && vrate < 2300000000UL) + slop = 400; + else if (vrate > 2300000000UL && vrate < 2600000000UL) + slop = 280; + + return slop; +} + +static void pll_8996_calc_vco_count(struct dsi_pll_db *pdb, + s64 vco_clk_rate, s64 fref) +{ + struct dsi_pll_input *pin = &pdb->in; + struct dsi_pll_output *pout = &pdb->out; + s64 data; + u32 cnt; + + data = fref * pin->vco_measure_time; + do_div(data, 1000000); + data &= 0x03ff; /* 10 bits */ + data -= 2; + pout->pll_vco_div_ref = data; + + data = (unsigned long)vco_clk_rate / 1000000; /* unit is Mhz */ + data *= pin->vco_measure_time; + do_div(data, 10); + pout->pll_vco_count = data; /* reg: 0x0474, 0x0478 */ + + data = fref * pin->kvco_measure_time; + do_div(data, 1000000); + data &= 0x03ff; /* 10 bits */ + data -= 1; + pout->pll_kvco_div_ref = data; + + cnt = pll_8996_kvco_slop(vco_clk_rate); + cnt *= 2; + do_div(cnt, 100); + cnt *= pin->kvco_measure_time; + pout->pll_kvco_count = cnt; + + pout->pll_misc1 = 16; + pout->pll_resetsm_cntrl = 48; + pout->pll_resetsm_cntrl2 = pin->bandgap_timer << 3; + pout->pll_resetsm_cntrl5 = pin->pll_wakeup_timer; + pout->pll_kvco_code = 0; +} + +static void pll_db_commit_ssc(struct mdss_pll_resources *pll, + struct dsi_pll_db *pdb) +{ + void __iomem *pll_base = pll->pll_base; + struct dsi_pll_input *pin = &pdb->in; + struct dsi_pll_output *pout = &pdb->out; + char data; + + data = pin->ssc_adj_period; + data &= 0x0ff; + MDSS_PLL_REG_W(pll_base, DSIPHY_PLL_SSC_ADJ_PER1, data); + data = (pin->ssc_adj_period >> 8); + data &= 0x03; + MDSS_PLL_REG_W(pll_base, DSIPHY_PLL_SSC_ADJ_PER2, data); + + data = pout->ssc_period; + data &= 0x0ff; + MDSS_PLL_REG_W(pll_base, DSIPHY_PLL_SSC_PER1, data); + data = (pout->ssc_period >> 8); + data &= 0x0ff; + MDSS_PLL_REG_W(pll_base, DSIPHY_PLL_SSC_PER2, data); + + data = pout->ssc_step_size; + data &= 0x0ff; + MDSS_PLL_REG_W(pll_base, DSIPHY_PLL_SSC_STEP_SIZE1, data); + data = (pout->ssc_step_size >> 8); + data &= 0x0ff; + MDSS_PLL_REG_W(pll_base, DSIPHY_PLL_SSC_STEP_SIZE2, data); + + data = (pin->ssc_center & 0x01); + data <<= 1; + data |= 0x01; /* enable */ + MDSS_PLL_REG_W(pll_base, DSIPHY_PLL_SSC_EN_CENTER, data); + + wmb(); /* make sure register committed */ +} + +static void pll_db_commit_common(struct mdss_pll_resources *pll, + struct dsi_pll_db *pdb) +{ + void __iomem *pll_base = pll->pll_base; + struct dsi_pll_input *pin = &pdb->in; + struct dsi_pll_output *pout = &pdb->out; + char data; + + /* confgiure the non frequency dependent pll registers */ + data = 0; + MDSS_PLL_REG_W(pll_base, DSIPHY_PLL_SYSCLK_EN_RESET, data); + + /* DSIPHY_PLL_CLKBUFLR_EN updated at dsi phy */ + + data = pout->pll_txclk_en; + MDSS_PLL_REG_W(pll_base, DSIPHY_PLL_TXCLK_EN, data); + + data = pout->pll_resetsm_cntrl; + MDSS_PLL_REG_W(pll_base, DSIPHY_PLL_RESETSM_CNTRL, data); + data = pout->pll_resetsm_cntrl2; + MDSS_PLL_REG_W(pll_base, DSIPHY_PLL_RESETSM_CNTRL2, data); + data = pout->pll_resetsm_cntrl5; + MDSS_PLL_REG_W(pll_base, DSIPHY_PLL_RESETSM_CNTRL5, data); + + data = pout->pll_vco_div_ref; + data &= 0x0ff; + MDSS_PLL_REG_W(pll_base, DSIPHY_PLL_VCO_DIV_REF1, data); + data = (pout->pll_vco_div_ref >> 8); + data &= 0x03; + MDSS_PLL_REG_W(pll_base, DSIPHY_PLL_VCO_DIV_REF2, data); + + data = pout->pll_kvco_div_ref; + data &= 0x0ff; + MDSS_PLL_REG_W(pll_base, DSIPHY_PLL_KVCO_DIV_REF1, data); + data = (pout->pll_kvco_div_ref >> 8); + data &= 0x03; + MDSS_PLL_REG_W(pll_base, DSIPHY_PLL_KVCO_DIV_REF2, data); + + data = pout->pll_misc1; + MDSS_PLL_REG_W(pll_base, DSIPHY_PLL_PLL_MISC1, data); + + data = pin->pll_ie_trim; + MDSS_PLL_REG_W(pll_base, DSIPHY_PLL_IE_TRIM, data); + + data = pin->pll_ip_trim; + MDSS_PLL_REG_W(pll_base, DSIPHY_PLL_IP_TRIM, data); + + data = ((pin->pll_cpmset_cur << 3) | pin->pll_cpcset_cur); + MDSS_PLL_REG_W(pll_base, DSIPHY_PLL_CP_SET_CUR, data); + + data = ((pin->pll_icpcset_p << 3) | pin->pll_icpcset_m); + MDSS_PLL_REG_W(pll_base, DSIPHY_PLL_PLL_ICPCSET, data); + + data = ((pin->pll_icpmset_p << 3) | pin->pll_icpcset_m); + MDSS_PLL_REG_W(pll_base, DSIPHY_PLL_PLL_ICPMSET, data); + + data = ((pin->pll_icpmset << 3) | pin->pll_icpcset); + MDSS_PLL_REG_W(pll_base, DSIPHY_PLL_PLL_ICP_SET, data); + + data = ((pdb->in.pll_lpf_cap2 << 4) | pdb->in.pll_lpf_cap1); + MDSS_PLL_REG_W(pll_base, DSIPHY_PLL_PLL_LPF1, data); + + data = pin->pll_iptat_trim; + MDSS_PLL_REG_W(pll_base, DSIPHY_PLL_IPTAT_TRIM, data); + + data = (pdb->in.pll_c3ctrl | (pdb->in.pll_r3ctrl << 4)); + MDSS_PLL_REG_W(pll_base, DSIPHY_PLL_PLL_CRCTRL, data); +} + +static void pll_db_commit_8996(struct mdss_pll_resources *pll, + struct dsi_pll_db *pdb) +{ + void __iomem *pll_base = pll->pll_base; + struct dsi_pll_input *pin = &pdb->in; + struct dsi_pll_output *pout = &pdb->out; + char data; + + data = pout->cmn_ldo_cntrl; + MDSS_PLL_REG_W(pll_base, DSIPHY_CMN_LDO_CNTRL, data); + + pll_db_commit_common(pll, pdb); + + /* de assert pll start and apply pll sw reset */ + /* stop pll */ + MDSS_PLL_REG_W(pll_base, DSIPHY_CMN_PLL_CNTRL, 0); + + /* pll sw reset */ + MDSS_PLL_REG_W(pll_base, DSIPHY_CMN_CTRL_1, 0x20); + wmb(); /* make sure register committed */ + udelay(10); + + MDSS_PLL_REG_W(pll_base, DSIPHY_CMN_CTRL_1, 0); + wmb(); /* make sure register committed */ + + MDSS_PLL_REG_W(pll_base, DSIPHY_PLL_PLL_VCO_TUNE, 0); + MDSS_PLL_REG_W(pll_base, DSIPHY_PLL_KVCO_CODE, 0); + wmb(); /* make sure register committed */ + + data = pdb->in.dsiclk_sel; /* set dsiclk_sel = 1 */ + MDSS_PLL_REG_W(pll_base, DSIPHY_CMN_CLK_CFG1, data); + + data = 0xff; /* data, clk, pll normal operation */ + MDSS_PLL_REG_W(pll_base, DSIPHY_CMN_CTRL_0, data); + + /* confgiure the frequency dependent pll registers */ + data = pout->dec_start; + MDSS_PLL_REG_W(pll_base, DSIPHY_PLL_DEC_START, data); + + data = pout->div_frac_start; + data &= 0x0ff; + MDSS_PLL_REG_W(pll_base, DSIPHY_PLL_DIV_FRAC_START1, data); + data = (pout->div_frac_start >> 8); + data &= 0x0ff; + MDSS_PLL_REG_W(pll_base, DSIPHY_PLL_DIV_FRAC_START2, data); + data = (pout->div_frac_start >> 16); + data &= 0x0f; + MDSS_PLL_REG_W(pll_base, DSIPHY_PLL_DIV_FRAC_START3, data); + + data = pout->plllock_cmp; + data &= 0x0ff; + MDSS_PLL_REG_W(pll_base, DSIPHY_PLL_PLLLOCK_CMP1, data); + data = (pout->plllock_cmp >> 8); + data &= 0x0ff; + MDSS_PLL_REG_W(pll_base, DSIPHY_PLL_PLLLOCK_CMP2, data); + data = (pout->plllock_cmp >> 16); + data &= 0x03; + MDSS_PLL_REG_W(pll_base, DSIPHY_PLL_PLLLOCK_CMP3, data); + + data = ((pin->plllock_cnt << 1) | (pin->plllock_rng << 3)); + MDSS_PLL_REG_W(pll_base, DSIPHY_PLL_PLLLOCK_CMP_EN, data); + + data = pout->pll_vco_count; + data &= 0x0ff; + MDSS_PLL_REG_W(pll_base, DSIPHY_PLL_VCO_COUNT1, data); + data = (pout->pll_vco_count >> 8); + data &= 0x0ff; + MDSS_PLL_REG_W(pll_base, DSIPHY_PLL_VCO_COUNT2, data); + + data = pout->pll_kvco_count; + data &= 0x0ff; + MDSS_PLL_REG_W(pll_base, DSIPHY_PLL_KVCO_COUNT1, data); + data = (pout->pll_kvco_count >> 8); + data &= 0x03; + MDSS_PLL_REG_W(pll_base, DSIPHY_PLL_KVCO_COUNT2, data); + + /* + * tx_band = pll_postdiv + * 0: divided by 1 <== for now + * 1: divided by 2 + * 2: divided by 4 + * 3: divided by 8 + */ + data = (((pout->pll_postdiv - 1) << 4) | pdb->in.pll_lpf_res1); + MDSS_PLL_REG_W(pll_base, DSIPHY_PLL_PLL_LPF2_POSTDIV, data); + + data = (pout->pll_n1div | (pout->pll_n2div << 4)); + MDSS_PLL_REG_W(pll_base, DSIPHY_CMN_CLK_CFG0, data); + + if (pll->ssc_en) + pll_db_commit_ssc(pll, pdb); + + wmb(); /* make sure register committed */ +} + +/* + * pll_source_finding: + * Both GLBL_TEST_CTRL and CLKBUFLR_EN are configured + * at mdss_dsi_8996_phy_config() + */ +static int pll_source_finding(struct mdss_pll_resources *pll) +{ + u32 clk_buf_en; + u32 glbl_test_ctrl; + + glbl_test_ctrl = MDSS_PLL_REG_R(pll->pll_base, + DSIPHY_CMN_GLBL_TEST_CTRL); + clk_buf_en = MDSS_PLL_REG_R(pll->pll_base, + DSIPHY_PLL_CLKBUFLR_EN); + + glbl_test_ctrl &= BIT(2); + glbl_test_ctrl >>= 2; + + pr_debug("%s: pll=%d clk_buf_en=%x glbl_test_ctrl=%x\n", + __func__, pll->index, clk_buf_en, glbl_test_ctrl); + + clk_buf_en &= (PLL_OUTPUT_RIGHT | PLL_OUTPUT_LEFT); + + if ((glbl_test_ctrl == PLL_SOURCE_FROM_LEFT) && + (clk_buf_en == PLL_OUTPUT_BOTH)) + return PLL_MASTER; + + if ((glbl_test_ctrl == PLL_SOURCE_FROM_RIGHT) && + (clk_buf_en == PLL_OUTPUT_NONE)) + return PLL_SLAVE; + + if ((glbl_test_ctrl == PLL_SOURCE_FROM_LEFT) && + (clk_buf_en == PLL_OUTPUT_RIGHT)) + return PLL_STANDALONE; + + pr_debug("%s: Error pll setup, clk_buf_en=%x glbl_test_ctrl=%x\n", + __func__, clk_buf_en, glbl_test_ctrl); + + return PLL_UNKNOWN; +} + +static void pll_source_setup(struct mdss_pll_resources *pll) +{ + int status; + struct dsi_pll_db *pdb = (struct dsi_pll_db *)pll->priv; + struct mdss_pll_resources *other; + + if (pdb->source_setup_done) + return; + + pdb->source_setup_done++; + + status = pll_source_finding(pll); + + if (status == PLL_STANDALONE || status == PLL_UNKNOWN) + return; + + other = pdb->next->pll; + if (!other) + return; + + pr_debug("%s: status=%d pll=%d other=%d\n", __func__, + status, pll->index, other->index); + + if (status == PLL_MASTER) + pll->slave = other; + else + other->slave = pll; +} + +int pll_vco_set_rate_8996(struct clk *c, unsigned long rate) +{ + int rc; + struct dsi_pll_vco_clk *vco = to_vco_clk(c); + struct mdss_pll_resources *pll = vco->priv; + struct mdss_pll_resources *slave; + struct dsi_pll_db *pdb; + + pdb = (struct dsi_pll_db *)pll->priv; + if (!pdb) { + pr_err("No prov found\n"); + return -EINVAL; + } + + rc = mdss_pll_resource_enable(pll, true); + if (rc) { + pr_err("Failed to enable mdss dsi plla=%d\n", pll->index); + return rc; + } + + pll_source_setup(pll); + + pr_debug("%s: ndx=%d base=%p rate=%lu slave=%p\n", __func__, + pll->index, pll->pll_base, rate, pll->slave); + + pll->vco_current_rate = rate; + pll->vco_ref_clk_rate = vco->ref_clk_rate; + + mdss_dsi_pll_8996_input_init(pll, pdb); + + pll_8996_dec_frac_calc(pll, pdb); + + if (pll->ssc_en) + pll_8996_ssc_calc(pll, pdb); + + pll_8996_calc_vco_count(pdb, pll->vco_current_rate, + pll->vco_ref_clk_rate); + + /* commit slave if split display is enabled */ + slave = pll->slave; + if (slave) + pll_db_commit_8996(slave, pdb); + + /* commit master itself */ + pll_db_commit_8996(pll, pdb); + + mdss_pll_resource_enable(pll, false); + + return rc; +} + +static void shadow_pll_dynamic_refresh_8996(struct mdss_pll_resources *pll, + struct dsi_pll_db *pdb) +{ + struct dsi_pll_output *pout = &pdb->out; + + MDSS_DYN_PLL_REG_W(pll->dyn_pll_base, + DSI_DYNAMIC_REFRESH_PLL_CTRL20, + DSIPHY_CMN_CTRL_0, DSIPHY_PLL_SYSCLK_EN_RESET, + 0xFF, 0x0); + MDSS_DYN_PLL_REG_W(pll->dyn_pll_base, + DSI_DYNAMIC_REFRESH_PLL_CTRL21, + DSIPHY_PLL_DEC_START, DSIPHY_PLL_DIV_FRAC_START1, + pout->dec_start, (pout->div_frac_start & 0x0FF)); + MDSS_DYN_PLL_REG_W(pll->dyn_pll_base, + DSI_DYNAMIC_REFRESH_PLL_CTRL22, + DSIPHY_PLL_DIV_FRAC_START2, DSIPHY_PLL_DIV_FRAC_START3, + ((pout->div_frac_start >> 8) & 0x0FF), + ((pout->div_frac_start >> 16) & 0x0F)); + MDSS_DYN_PLL_REG_W(pll->dyn_pll_base, + DSI_DYNAMIC_REFRESH_PLL_CTRL23, + DSIPHY_PLL_PLLLOCK_CMP1, DSIPHY_PLL_PLLLOCK_CMP2, + (pout->plllock_cmp & 0x0FF), + ((pout->plllock_cmp >> 8) & 0x0FF)); + MDSS_DYN_PLL_REG_W(pll->dyn_pll_base, + DSI_DYNAMIC_REFRESH_PLL_CTRL24, + DSIPHY_PLL_PLLLOCK_CMP3, DSIPHY_PLL_PLL_VCO_TUNE, + ((pout->plllock_cmp >> 16) & 0x03), + (pll->cache_pll_trim_codes[1] | BIT(7))); /* VCO tune*/ + MDSS_DYN_PLL_REG_W(pll->dyn_pll_base, + DSI_DYNAMIC_REFRESH_PLL_CTRL25, + DSIPHY_PLL_KVCO_CODE, DSIPHY_PLL_RESETSM_CNTRL, + (pll->cache_pll_trim_codes[0] | BIT(5)), 0x38); + MDSS_DYN_PLL_REG_W(pll->dyn_pll_base, + DSI_DYNAMIC_REFRESH_PLL_CTRL26, + DSIPHY_PLL_PLL_LPF2_POSTDIV, DSIPHY_CMN_PLL_CNTRL, + (((pout->pll_postdiv - 1) << 4) | pdb->in.pll_lpf_res1), 0x01); + MDSS_DYN_PLL_REG_W(pll->dyn_pll_base, + DSI_DYNAMIC_REFRESH_PLL_CTRL27, + DSIPHY_CMN_PLL_CNTRL, DSIPHY_CMN_PLL_CNTRL, + 0x01, 0x01); + MDSS_DYN_PLL_REG_W(pll->dyn_pll_base, + DSI_DYNAMIC_REFRESH_PLL_CTRL28, + DSIPHY_CMN_PLL_CNTRL, DSIPHY_CMN_PLL_CNTRL, + 0x01, 0x01); + MDSS_DYN_PLL_REG_W(pll->dyn_pll_base, + DSI_DYNAMIC_REFRESH_PLL_CTRL29, + DSIPHY_CMN_PLL_CNTRL, DSIPHY_CMN_PLL_CNTRL, + 0x01, 0x01); + MDSS_PLL_REG_W(pll->dyn_pll_base, + DSI_DYNAMIC_REFRESH_PLL_UPPER_ADDR, 0x0000001E); + MDSS_PLL_REG_W(pll->dyn_pll_base, + DSI_DYNAMIC_REFRESH_PLL_UPPER_ADDR2, 0x001FFE00); + + /* + * Ensure all the dynamic refresh registers are written before + * dynamic refresh to change the fps is triggered + */ + wmb(); +} + +int shadow_pll_vco_set_rate_8996(struct clk *c, unsigned long rate) +{ + int rc; + struct dsi_pll_vco_clk *vco = to_vco_clk(c); + struct mdss_pll_resources *pll = vco->priv; + struct dsi_pll_db *pdb; + s64 vco_clk_rate = (s64)rate; + + if (!pll) { + pr_err("PLL data not found\n"); + return -EINVAL; + } + + pdb = pll->priv; + if (!pdb) { + pr_err("No priv data found\n"); + return -EINVAL; + } + + rc = mdss_pll_read_stored_trim_codes(pll, vco_clk_rate); + if (rc) { + pr_err("cannot find pll codes rate=%lld\n", vco_clk_rate); + return -EINVAL; + } + + rc = mdss_pll_resource_enable(pll, true); + if (rc) { + pr_err("Failed to enable mdss dsi plla=%d\n", pll->index); + return rc; + } + + pr_debug("%s: ndx=%d base=%p rate=%lu\n", __func__, + pll->index, pll->pll_base, rate); + + pll->vco_current_rate = rate; + pll->vco_ref_clk_rate = vco->ref_clk_rate; + + mdss_dsi_pll_8996_input_init(pll, pdb); + + pll_8996_dec_frac_calc(pll, pdb); + + pll_8996_calc_vco_count(pdb, pll->vco_current_rate, + pll->vco_ref_clk_rate); + + shadow_pll_dynamic_refresh_8996(pll, pdb); + + rc = mdss_pll_resource_enable(pll, false); + if (rc) { + pr_err("Failed to enable mdss dsi plla=%d\n", pll->index); + return rc; + } + + return rc; +} + +unsigned long pll_vco_get_rate_8996(struct clk *c) +{ + u64 vco_rate, multiplier = BIT(20); + s32 div_frac_start; + u32 dec_start; + struct dsi_pll_vco_clk *vco = to_vco_clk(c); + u64 ref_clk = vco->ref_clk_rate; + int rc; + struct mdss_pll_resources *pll = vco->priv; + + if (is_gdsc_disabled(pll)) + return 0; + + rc = mdss_pll_resource_enable(pll, true); + if (rc) { + pr_err("Failed to enable mdss dsi pll=%d\n", pll->index); + return rc; + } + + dec_start = MDSS_PLL_REG_R(pll->pll_base, + DSIPHY_PLL_DEC_START); + dec_start &= 0x0ff; + pr_debug("dec_start = 0x%x\n", dec_start); + + div_frac_start = (MDSS_PLL_REG_R(pll->pll_base, + DSIPHY_PLL_DIV_FRAC_START3) & 0x0f) << 16; + div_frac_start |= (MDSS_PLL_REG_R(pll->pll_base, + DSIPHY_PLL_DIV_FRAC_START2) & 0x0ff) << 8; + div_frac_start |= MDSS_PLL_REG_R(pll->pll_base, + DSIPHY_PLL_DIV_FRAC_START1) & 0x0ff; + pr_debug("div_frac_start = 0x%x\n", div_frac_start); + + vco_rate = ref_clk * dec_start; + vco_rate += ((ref_clk * div_frac_start) / multiplier); + + pr_debug("returning vco rate = %lu\n", (unsigned long)vco_rate); + + mdss_pll_resource_enable(pll, false); + + return (unsigned long)vco_rate; +} + +long pll_vco_round_rate_8996(struct clk *c, unsigned long rate) +{ + unsigned long rrate = rate; + u32 div; + struct dsi_pll_vco_clk *vco = to_vco_clk(c); + + div = vco->min_rate / rate; + if (div > 15) { + /* rate < 86.67 Mhz */ + pr_err("rate=%lu NOT supportted\n", rate); + return -EINVAL; + } + + if (rate < vco->min_rate) + rrate = vco->min_rate; + if (rate > vco->max_rate) + rrate = vco->max_rate; + + return rrate; +} + +enum handoff pll_vco_handoff_8996(struct clk *c) +{ + int rc; + enum handoff ret = HANDOFF_DISABLED_CLK; + struct dsi_pll_vco_clk *vco = to_vco_clk(c); + struct mdss_pll_resources *pll = vco->priv; + + if (is_gdsc_disabled(pll)) + return HANDOFF_DISABLED_CLK; + + rc = mdss_pll_resource_enable(pll, true); + if (rc) { + pr_err("Failed to enable mdss dsi pll=%d\n", pll->index); + return ret; + } + + if (pll_is_pll_locked_8996(pll)) { + pll->handoff_resources = true; + pll->pll_on = true; + c->rate = pll_vco_get_rate_8996(c); + ret = HANDOFF_ENABLED_CLK; + } else { + mdss_pll_resource_enable(pll, false); + } + + return ret; +} + +enum handoff shadow_pll_vco_handoff_8996(struct clk *c) +{ + return HANDOFF_DISABLED_CLK; +} + +int pll_vco_prepare_8996(struct clk *c) +{ + int rc = 0; + struct dsi_pll_vco_clk *vco = to_vco_clk(c); + struct mdss_pll_resources *pll = vco->priv; + + if (!pll) { + pr_err("Dsi pll resources are not available\n"); + return -EINVAL; + } + + rc = mdss_pll_resource_enable(pll, true); + if (rc) { + pr_err("ndx=%d Failed to enable mdss dsi pll resources\n", + pll->index); + return rc; + } + + if ((pll->vco_cached_rate != 0) + && (pll->vco_cached_rate == c->rate)) { + rc = c->ops->set_rate(c, pll->vco_cached_rate); + if (rc) { + pr_err("index=%d vco_set_rate failed. rc=%d\n", + rc, pll->index); + mdss_pll_resource_enable(pll, false); + goto error; + } + } + + rc = dsi_pll_enable(c); + + if (rc) { + mdss_pll_resource_enable(pll, false); + pr_err("ndx=%d failed to enable dsi pll\n", pll->index); + } + +error: + return rc; +} + +void pll_vco_unprepare_8996(struct clk *c) +{ + struct dsi_pll_vco_clk *vco = to_vco_clk(c); + struct mdss_pll_resources *pll = vco->priv; + + if (!pll) { + pr_err("Dsi pll resources are not available\n"); + return; + } + + pll->vco_cached_rate = c->rate; + dsi_pll_disable(c); +} diff -Nruw linux-4.4.115-fbx/drivers/clk/msm./mdss/mdss-dsi-pll-8998.c linux-4.4.115-fbx/drivers/clk/msm/mdss/mdss-dsi-pll-8998.c --- linux-4.4.115-fbx/drivers/clk/msm./mdss/mdss-dsi-pll-8998.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-4.4.115-fbx/drivers/clk/msm/mdss/mdss-dsi-pll-8998.c 2019-01-22 16:16:23.019242024 +0100 @@ -0,0 +1,1814 @@ +/* + * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define pr_fmt(fmt) "%s: " fmt, __func__ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "mdss-pll.h" +#include "mdss-dsi-pll.h" +#include "mdss-pll.h" + +#define VCO_DELAY_USEC 1 + +#define MHZ_250 250000000UL +#define MHZ_500 500000000UL +#define MHZ_1000 1000000000UL +#define MHZ_1100 1100000000UL +#define MHZ_1900 1900000000UL +#define MHZ_3000 3000000000UL + +/* Register Offsets from PLL base address */ +#define PLL_ANALOG_CONTROLS_ONE 0x000 +#define PLL_ANALOG_CONTROLS_TWO 0x004 +#define PLL_INT_LOOP_SETTINGS 0x008 +#define PLL_INT_LOOP_SETTINGS_TWO 0x00c +#define PLL_ANALOG_CONTROLS_THREE 0x010 +#define PLL_ANALOG_CONTROLS_FOUR 0x014 +#define PLL_INT_LOOP_CONTROLS 0x018 +#define PLL_DSM_DIVIDER 0x01c +#define PLL_FEEDBACK_DIVIDER 0x020 +#define PLL_SYSTEM_MUXES 0x024 +#define PLL_FREQ_UPDATE_CONTROL_OVERRIDES 0x028 +#define PLL_CMODE 0x02c +#define PLL_CALIBRATION_SETTINGS 0x030 +#define PLL_BAND_SEL_CAL_TIMER_LOW 0x034 +#define PLL_BAND_SEL_CAL_TIMER_HIGH 0x038 +#define PLL_BAND_SEL_CAL_SETTINGS 0x03c +#define PLL_BAND_SEL_MIN 0x040 +#define PLL_BAND_SEL_MAX 0x044 +#define PLL_BAND_SEL_PFILT 0x048 +#define PLL_BAND_SEL_IFILT 0x04c +#define PLL_BAND_SEL_CAL_SETTINGS_TWO 0x050 +#define PLL_BAND_SEL_CAL_SETTINGS_THREE 0x054 +#define PLL_BAND_SEL_CAL_SETTINGS_FOUR 0x058 +#define PLL_BAND_SEL_ICODE_HIGH 0x05c +#define PLL_BAND_SEL_ICODE_LOW 0x060 +#define PLL_FREQ_DETECT_SETTINGS_ONE 0x064 +#define PLL_PFILT 0x07c +#define PLL_IFILT 0x080 +#define PLL_GAIN 0x084 +#define PLL_ICODE_LOW 0x088 +#define PLL_ICODE_HIGH 0x08c +#define PLL_LOCKDET 0x090 +#define PLL_OUTDIV 0x094 +#define PLL_FASTLOCK_CONTROL 0x098 +#define PLL_PASS_OUT_OVERRIDE_ONE 0x09c +#define PLL_PASS_OUT_OVERRIDE_TWO 0x0a0 +#define PLL_CORE_OVERRIDE 0x0a4 +#define PLL_CORE_INPUT_OVERRIDE 0x0a8 +#define PLL_RATE_CHANGE 0x0ac +#define PLL_PLL_DIGITAL_TIMERS 0x0b0 +#define PLL_PLL_DIGITAL_TIMERS_TWO 0x0b4 +#define PLL_DEC_FRAC_MUXES 0x0c8 +#define PLL_DECIMAL_DIV_START_1 0x0cc +#define PLL_FRAC_DIV_START_LOW_1 0x0d0 +#define PLL_FRAC_DIV_START_MID_1 0x0d4 +#define PLL_FRAC_DIV_START_HIGH_1 0x0d8 +#define PLL_MASH_CONTROL 0x0ec +#define PLL_SSC_MUX_CONTROL 0x108 +#define PLL_SSC_STEPSIZE_LOW_1 0x10c +#define PLL_SSC_STEPSIZE_HIGH_1 0x110 +#define PLL_SSC_DIV_PER_LOW_1 0x114 +#define PLL_SSC_DIV_PER_HIGH_1 0x118 +#define PLL_SSC_DIV_ADJPER_LOW_1 0x11c +#define PLL_SSC_DIV_ADJPER_HIGH_1 0x120 +#define PLL_SSC_CONTROL 0x13c +#define PLL_PLL_OUTDIV_RATE 0x140 +#define PLL_PLL_LOCKDET_RATE_1 0x144 +#define PLL_PLL_PROP_GAIN_RATE_1 0x14c +#define PLL_PLL_BAND_SET_RATE_1 0x154 +#define PLL_PLL_INT_GAIN_IFILT_BAND_1 0x15c +#define PLL_PLL_FL_INT_GAIN_PFILT_BAND_1 0x164 +#define PLL_FASTLOCK_EN_BAND 0x16c +#define PLL_FREQ_TUNE_ACCUM_INIT_MUX 0x17c +#define PLL_PLL_LOCK_OVERRIDE 0x180 +#define PLL_PLL_LOCK_DELAY 0x184 +#define PLL_PLL_LOCK_MIN_DELAY 0x188 +#define PLL_CLOCK_INVERTERS 0x18c +#define PLL_SPARE_AND_JPC_OVERRIDES 0x190 +#define PLL_BIAS_CONTROL_1 0x194 +#define PLL_BIAS_CONTROL_2 0x198 +#define PLL_ALOG_OBSV_BUS_CTRL_1 0x19c +#define PLL_COMMON_STATUS_ONE 0x1a0 + +/* Register Offsets from PHY base address */ +#define PHY_CMN_CLK_CFG0 0x010 +#define PHY_CMN_CLK_CFG1 0x014 +#define PHY_CMN_RBUF_CTRL 0x01c +#define PHY_CMN_PLL_CNTRL 0x038 +#define PHY_CMN_CTRL_0 0x024 + +/* Bit definition of SSC control registers */ +#define SSC_CENTER BIT(0) +#define SSC_EN BIT(1) +#define SSC_FREQ_UPDATE BIT(2) +#define SSC_FREQ_UPDATE_MUX BIT(3) +#define SSC_UPDATE_SSC BIT(4) +#define SSC_UPDATE_SSC_MUX BIT(5) +#define SSC_START BIT(6) +#define SSC_START_MUX BIT(7) + +enum { + DSI_PLL_0, + DSI_PLL_1, + DSI_PLL_MAX +}; + +struct dsi_pll_regs { + u32 pll_prop_gain_rate; + u32 pll_outdiv_rate; + u32 pll_lockdet_rate; + u32 decimal_div_start; + u32 frac_div_start_low; + u32 frac_div_start_mid; + u32 frac_div_start_high; + u32 pll_clock_inverters; + u32 ssc_stepsize_low; + u32 ssc_stepsize_high; + u32 ssc_div_per_low; + u32 ssc_div_per_high; + u32 ssc_adjper_low; + u32 ssc_adjper_high; + u32 ssc_control; +}; + +struct dsi_pll_config { + u32 ref_freq; + bool ignore_frac; + bool disable_prescaler; + bool enable_ssc; + bool ssc_center; + u32 dec_bits; + u32 frac_bits; + u32 lock_timer; + u32 ssc_freq; + u32 ssc_offset; + u32 ssc_adj_per; + u32 thresh_cycles; + u32 refclk_cycles; +}; + +struct dsi_pll_8998 { + struct mdss_pll_resources *rsc; + struct dsi_pll_config pll_configuration; + struct dsi_pll_regs reg_setup; +}; + +static struct mdss_pll_resources *pll_rsc_db[DSI_PLL_MAX]; +static struct dsi_pll_8998 plls[DSI_PLL_MAX]; + +static void dsi_pll_config_slave(struct mdss_pll_resources *rsc) +{ + u32 reg; + struct mdss_pll_resources *orsc = pll_rsc_db[DSI_PLL_1]; + + if (!rsc) + return; + + /* Only DSI PLL0 can act as a master */ + if (rsc->index != DSI_PLL_0) + return; + + /* default configuration: source is either internal or ref clock */ + rsc->slave = NULL; + + if (!orsc) { + pr_warn("slave PLL unavilable, assuming standalone config\n"); + return; + } + + /* check to see if the source of DSI1 PLL bitclk is set to external */ + reg = MDSS_PLL_REG_R(orsc->phy_base, PHY_CMN_CLK_CFG1); + reg &= (BIT(2) | BIT(3)); + if (reg == 0x04) + rsc->slave = pll_rsc_db[DSI_PLL_1]; /* external source */ + + pr_debug("Slave PLL %s\n", rsc->slave ? "configured" : "absent"); +} + +static void dsi_pll_setup_config(struct dsi_pll_8998 *pll, + struct mdss_pll_resources *rsc) +{ + struct dsi_pll_config *config = &pll->pll_configuration; + + config->ref_freq = 19200000; + config->dec_bits = 8; + config->frac_bits = 18; + config->lock_timer = 64; + config->ssc_freq = 31500; + config->ssc_offset = 5000; + config->ssc_adj_per = 2; + config->thresh_cycles = 32; + config->refclk_cycles = 256; + + config->ignore_frac = false; + config->disable_prescaler = false; + config->enable_ssc = rsc->ssc_en; + config->ssc_center = rsc->ssc_center; + + if (config->enable_ssc) { + if (rsc->ssc_freq) + config->ssc_freq = rsc->ssc_freq; + if (rsc->ssc_ppm) + config->ssc_offset = rsc->ssc_ppm; + } + + dsi_pll_config_slave(rsc); +} + +static void dsi_pll_calc_dec_frac(struct dsi_pll_8998 *pll, + struct mdss_pll_resources *rsc) +{ + struct dsi_pll_config *config = &pll->pll_configuration; + struct dsi_pll_regs *regs = &pll->reg_setup; + u64 fref = rsc->vco_ref_clk_rate; + u64 pll_freq; + u64 divider; + u64 dec, dec_multiple; + u32 frac; + u64 multiplier; + + pll_freq = rsc->vco_current_rate; + + if (config->disable_prescaler) + divider = fref; + else + divider = fref * 2; + + multiplier = 1 << config->frac_bits; + dec_multiple = div_u64(pll_freq * multiplier, divider); + div_u64_rem(dec_multiple, multiplier, &frac); + + dec = div_u64(dec_multiple, multiplier); + + if (pll_freq <= MHZ_1900) + regs->pll_prop_gain_rate = 8; + else if (pll_freq <= MHZ_3000) + regs->pll_prop_gain_rate = 10; + else + regs->pll_prop_gain_rate = 12; + + if (pll_freq < MHZ_1100) + regs->pll_clock_inverters = 8; + else + regs->pll_clock_inverters = 0; + + regs->pll_lockdet_rate = config->lock_timer; + regs->decimal_div_start = dec; + regs->frac_div_start_low = (frac & 0xff); + regs->frac_div_start_mid = (frac & 0xff00) >> 8; + regs->frac_div_start_high = (frac & 0x30000) >> 16; +} + +static void dsi_pll_calc_ssc(struct dsi_pll_8998 *pll, + struct mdss_pll_resources *rsc) +{ + struct dsi_pll_config *config = &pll->pll_configuration; + struct dsi_pll_regs *regs = &pll->reg_setup; + u32 ssc_per; + u32 ssc_mod; + u64 ssc_step_size; + u64 frac; + + if (!config->enable_ssc) { + pr_debug("SSC not enabled\n"); + return; + } + + ssc_per = DIV_ROUND_CLOSEST(config->ref_freq, config->ssc_freq) / 2 - 1; + ssc_mod = (ssc_per + 1) % (config->ssc_adj_per + 1); + ssc_per -= ssc_mod; + + frac = regs->frac_div_start_low | + (regs->frac_div_start_mid << 8) | + (regs->frac_div_start_high << 16); + ssc_step_size = regs->decimal_div_start; + ssc_step_size *= (1 << config->frac_bits); + ssc_step_size += frac; + ssc_step_size *= config->ssc_offset; + ssc_step_size *= (config->ssc_adj_per + 1); + ssc_step_size = div_u64(ssc_step_size, (ssc_per + 1)); + ssc_step_size = DIV_ROUND_CLOSEST_ULL(ssc_step_size, 1000000); + + regs->ssc_div_per_low = ssc_per & 0xFF; + regs->ssc_div_per_high = (ssc_per & 0xFF00) >> 8; + regs->ssc_stepsize_low = (u32)(ssc_step_size & 0xFF); + regs->ssc_stepsize_high = (u32)((ssc_step_size & 0xFF00) >> 8); + regs->ssc_adjper_low = config->ssc_adj_per & 0xFF; + regs->ssc_adjper_high = (config->ssc_adj_per & 0xFF00) >> 8; + + regs->ssc_control = config->ssc_center ? SSC_CENTER : 0; + + pr_debug("SCC: Dec:%d, frac:%llu, frac_bits:%d\n", + regs->decimal_div_start, frac, config->frac_bits); + pr_debug("SSC: div_per:0x%X, stepsize:0x%X, adjper:0x%X\n", + ssc_per, (u32)ssc_step_size, config->ssc_adj_per); +} + +static void dsi_pll_ssc_commit(struct dsi_pll_8998 *pll, + struct mdss_pll_resources *rsc) +{ + void __iomem *pll_base = rsc->pll_base; + struct dsi_pll_regs *regs = &pll->reg_setup; + + if (pll->pll_configuration.enable_ssc) { + pr_debug("SSC is enabled\n"); + + MDSS_PLL_REG_W(pll_base, PLL_SSC_STEPSIZE_LOW_1, + regs->ssc_stepsize_low); + MDSS_PLL_REG_W(pll_base, PLL_SSC_STEPSIZE_HIGH_1, + regs->ssc_stepsize_high); + MDSS_PLL_REG_W(pll_base, PLL_SSC_DIV_PER_LOW_1, + regs->ssc_div_per_low); + MDSS_PLL_REG_W(pll_base, PLL_SSC_DIV_PER_HIGH_1, + regs->ssc_div_per_high); + MDSS_PLL_REG_W(pll_base, PLL_SSC_DIV_ADJPER_LOW_1, + regs->ssc_adjper_low); + MDSS_PLL_REG_W(pll_base, PLL_SSC_DIV_ADJPER_HIGH_1, + regs->ssc_adjper_high); + MDSS_PLL_REG_W(pll_base, PLL_SSC_CONTROL, + SSC_EN | regs->ssc_control); + } +} + +static void dsi_pll_config_hzindep_reg(struct dsi_pll_8998 *pll, + struct mdss_pll_resources *rsc) +{ + void __iomem *pll_base = rsc->pll_base; + + MDSS_PLL_REG_W(pll_base, PLL_ANALOG_CONTROLS_ONE, 0x80); + MDSS_PLL_REG_W(pll_base, PLL_ANALOG_CONTROLS_TWO, 0x03); + MDSS_PLL_REG_W(pll_base, PLL_ANALOG_CONTROLS_THREE, 0x00); + MDSS_PLL_REG_W(pll_base, PLL_DSM_DIVIDER, 0x00); + MDSS_PLL_REG_W(pll_base, PLL_FEEDBACK_DIVIDER, 0x4e); + MDSS_PLL_REG_W(pll_base, PLL_CALIBRATION_SETTINGS, 0x40); + MDSS_PLL_REG_W(pll_base, PLL_BAND_SEL_CAL_SETTINGS_THREE, 0xba); + MDSS_PLL_REG_W(pll_base, PLL_FREQ_DETECT_SETTINGS_ONE, 0x0c); + MDSS_PLL_REG_W(pll_base, PLL_OUTDIV, 0x00); + MDSS_PLL_REG_W(pll_base, PLL_CORE_OVERRIDE, 0x00); + MDSS_PLL_REG_W(pll_base, PLL_PLL_DIGITAL_TIMERS_TWO, 0x08); + MDSS_PLL_REG_W(pll_base, PLL_PLL_PROP_GAIN_RATE_1, 0x08); + MDSS_PLL_REG_W(pll_base, PLL_PLL_BAND_SET_RATE_1, 0xc0); + MDSS_PLL_REG_W(pll_base, PLL_PLL_INT_GAIN_IFILT_BAND_1, 0x82); + MDSS_PLL_REG_W(pll_base, PLL_PLL_FL_INT_GAIN_PFILT_BAND_1, 0x4c); + MDSS_PLL_REG_W(pll_base, PLL_PLL_LOCK_OVERRIDE, 0x80); + MDSS_PLL_REG_W(pll_base, PLL_PFILT, 0x29); + MDSS_PLL_REG_W(pll_base, PLL_IFILT, 0x3f); +} + +static void dsi_pll_init_val(struct mdss_pll_resources *rsc) +{ + void __iomem *pll_base = rsc->pll_base; + + MDSS_PLL_REG_W(pll_base, PLL_CORE_INPUT_OVERRIDE, 0x10); + MDSS_PLL_REG_W(pll_base, PLL_INT_LOOP_SETTINGS, 0x3f); + MDSS_PLL_REG_W(pll_base, PLL_INT_LOOP_SETTINGS_TWO, 0x0); + MDSS_PLL_REG_W(pll_base, PLL_ANALOG_CONTROLS_FOUR, 0x0); + MDSS_PLL_REG_W(pll_base, PLL_INT_LOOP_CONTROLS, 0x80); + MDSS_PLL_REG_W(pll_base, PLL_FREQ_UPDATE_CONTROL_OVERRIDES, 0x0); + MDSS_PLL_REG_W(pll_base, PLL_BAND_SEL_CAL_TIMER_LOW, 0x0); + MDSS_PLL_REG_W(pll_base, PLL_BAND_SEL_CAL_TIMER_HIGH, 0x02); + MDSS_PLL_REG_W(pll_base, PLL_BAND_SEL_CAL_SETTINGS, 0x82); + MDSS_PLL_REG_W(pll_base, PLL_BAND_SEL_MIN, 0x00); + MDSS_PLL_REG_W(pll_base, PLL_BAND_SEL_MAX, 0xff); + MDSS_PLL_REG_W(pll_base, PLL_BAND_SEL_PFILT, 0x00); + MDSS_PLL_REG_W(pll_base, PLL_BAND_SEL_IFILT, 0x00); + MDSS_PLL_REG_W(pll_base, PLL_BAND_SEL_CAL_SETTINGS_TWO, 0x25); + MDSS_PLL_REG_W(pll_base, PLL_BAND_SEL_CAL_SETTINGS_FOUR, 0x4f); + MDSS_PLL_REG_W(pll_base, PLL_BAND_SEL_ICODE_HIGH, 0x0a); + MDSS_PLL_REG_W(pll_base, PLL_BAND_SEL_ICODE_LOW, 0x0); + MDSS_PLL_REG_W(pll_base, PLL_GAIN, 0x42); + MDSS_PLL_REG_W(pll_base, PLL_ICODE_LOW, 0x00); + MDSS_PLL_REG_W(pll_base, PLL_ICODE_HIGH, 0x00); + MDSS_PLL_REG_W(pll_base, PLL_LOCKDET, 0x30); + MDSS_PLL_REG_W(pll_base, PLL_FASTLOCK_CONTROL, 0x04); + MDSS_PLL_REG_W(pll_base, PLL_PASS_OUT_OVERRIDE_ONE, 0x00); + MDSS_PLL_REG_W(pll_base, PLL_PASS_OUT_OVERRIDE_TWO, 0x00); + MDSS_PLL_REG_W(pll_base, PLL_RATE_CHANGE, 0x01); + MDSS_PLL_REG_W(pll_base, PLL_PLL_DIGITAL_TIMERS, 0x08); + MDSS_PLL_REG_W(pll_base, PLL_DEC_FRAC_MUXES, 0x00); + MDSS_PLL_REG_W(pll_base, PLL_MASH_CONTROL, 0x03); + MDSS_PLL_REG_W(pll_base, PLL_SSC_MUX_CONTROL, 0x0); + MDSS_PLL_REG_W(pll_base, PLL_SSC_CONTROL, 0x0); + MDSS_PLL_REG_W(pll_base, PLL_FASTLOCK_EN_BAND, 0x03); + MDSS_PLL_REG_W(pll_base, PLL_FREQ_TUNE_ACCUM_INIT_MUX, 0x0); + MDSS_PLL_REG_W(pll_base, PLL_PLL_LOCK_MIN_DELAY, 0x19); + MDSS_PLL_REG_W(pll_base, PLL_SPARE_AND_JPC_OVERRIDES, 0x0); + MDSS_PLL_REG_W(pll_base, PLL_BIAS_CONTROL_1, 0x40); + MDSS_PLL_REG_W(pll_base, PLL_BIAS_CONTROL_2, 0x20); + MDSS_PLL_REG_W(pll_base, PLL_ALOG_OBSV_BUS_CTRL_1, 0x0); +} + +static void dsi_pll_commit(struct dsi_pll_8998 *pll, + struct mdss_pll_resources *rsc) +{ + void __iomem *pll_base = rsc->pll_base; + struct dsi_pll_regs *reg = &pll->reg_setup; + + MDSS_PLL_REG_W(pll_base, PLL_CORE_INPUT_OVERRIDE, 0x12); + MDSS_PLL_REG_W(pll_base, PLL_DECIMAL_DIV_START_1, + reg->decimal_div_start); + MDSS_PLL_REG_W(pll_base, PLL_FRAC_DIV_START_LOW_1, + reg->frac_div_start_low); + MDSS_PLL_REG_W(pll_base, PLL_FRAC_DIV_START_MID_1, + reg->frac_div_start_mid); + MDSS_PLL_REG_W(pll_base, PLL_FRAC_DIV_START_HIGH_1, + reg->frac_div_start_high); + MDSS_PLL_REG_W(pll_base, PLL_PLL_LOCKDET_RATE_1, 0x40); + MDSS_PLL_REG_W(pll_base, PLL_PLL_LOCK_DELAY, 0x06); + MDSS_PLL_REG_W(pll_base, PLL_CMODE, 0x10); + MDSS_PLL_REG_W(pll_base, PLL_CLOCK_INVERTERS, reg->pll_clock_inverters); + +} + +static int vco_8998_set_rate(struct clk *c, unsigned long rate) +{ + int rc; + struct dsi_pll_vco_clk *vco = to_vco_clk(c); + struct mdss_pll_resources *rsc = vco->priv; + struct dsi_pll_8998 *pll; + + if (!rsc) { + pr_err("pll resource not found\n"); + return -EINVAL; + } + + if (rsc->pll_on) + return 0; + + pll = rsc->priv; + if (!pll) { + pr_err("pll configuration not found\n"); + return -EINVAL; + } + + pr_debug("ndx=%d, rate=%lu\n", rsc->index, rate); + + rsc->vco_current_rate = rate; + rsc->vco_ref_clk_rate = vco->ref_clk_rate; + + rc = mdss_pll_resource_enable(rsc, true); + if (rc) { + pr_err("failed to enable mdss dsi pll(%d), rc=%d\n", + rsc->index, rc); + return rc; + } + + dsi_pll_init_val(rsc); + + dsi_pll_setup_config(pll, rsc); + + dsi_pll_calc_dec_frac(pll, rsc); + + dsi_pll_calc_ssc(pll, rsc); + + dsi_pll_commit(pll, rsc); + + dsi_pll_config_hzindep_reg(pll, rsc); + + dsi_pll_ssc_commit(pll, rsc); + + /* flush, ensure all register writes are done*/ + wmb(); + + mdss_pll_resource_enable(rsc, false); + + return 0; +} + +static int dsi_pll_8998_lock_status(struct mdss_pll_resources *pll) +{ + int rc; + u32 status; + u32 const delay_us = 100; + u32 const timeout_us = 5000; + + rc = readl_poll_timeout_atomic(pll->pll_base + PLL_COMMON_STATUS_ONE, + status, + ((status & BIT(0)) > 0), + delay_us, + timeout_us); + if (rc) + pr_err("DSI PLL(%d) lock failed, status=0x%08x\n", + pll->index, status); + + return rc; +} + +static void dsi_pll_disable_pll_bias(struct mdss_pll_resources *rsc) +{ + u32 data = MDSS_PLL_REG_R(rsc->phy_base, PHY_CMN_CTRL_0); + + MDSS_PLL_REG_W(rsc->pll_base, PLL_SYSTEM_MUXES, 0); + MDSS_PLL_REG_W(rsc->phy_base, PHY_CMN_CTRL_0, data & ~BIT(5)); + ndelay(250); +} + +static void dsi_pll_enable_pll_bias(struct mdss_pll_resources *rsc) +{ + u32 data = MDSS_PLL_REG_R(rsc->phy_base, PHY_CMN_CTRL_0); + + MDSS_PLL_REG_W(rsc->phy_base, PHY_CMN_CTRL_0, data | BIT(5)); + MDSS_PLL_REG_W(rsc->pll_base, PLL_SYSTEM_MUXES, 0xc0); + ndelay(250); +} + +static void dsi_pll_disable_global_clk(struct mdss_pll_resources *rsc) +{ + u32 data; + + data = MDSS_PLL_REG_R(rsc->phy_base, PHY_CMN_CLK_CFG1); + MDSS_PLL_REG_W(rsc->phy_base, PHY_CMN_CLK_CFG1, (data & ~BIT(5))); +} + +static void dsi_pll_enable_global_clk(struct mdss_pll_resources *rsc) +{ + u32 data; + + data = MDSS_PLL_REG_R(rsc->phy_base, PHY_CMN_CLK_CFG1); + MDSS_PLL_REG_W(rsc->phy_base, PHY_CMN_CLK_CFG1, (data | BIT(5))); +} + +static int dsi_pll_enable(struct dsi_pll_vco_clk *vco) +{ + int rc; + struct mdss_pll_resources *rsc = vco->priv; + struct dsi_pll_8998 *pll = rsc->priv; + struct dsi_pll_regs *regs = &pll->reg_setup; + + dsi_pll_enable_pll_bias(rsc); + if (rsc->slave) + dsi_pll_enable_pll_bias(rsc->slave); + + /* + * The PLL out dividers are fixed divider clocks and hence the + * set_div is not called during set_rate cycle of the tree. + * The outdiv rate is therefore set in the pll out mux's set_sel + * callback. But that will be called only after vco's set rate. + * Hence PLL out div value is set here before locking the PLL. + */ + MDSS_PLL_REG_W(rsc->pll_base, PLL_PLL_OUTDIV_RATE, + regs->pll_outdiv_rate); + + /* Start PLL */ + MDSS_PLL_REG_W(rsc->phy_base, PHY_CMN_PLL_CNTRL, 0x01); + + /* + * ensure all PLL configurations are written prior to checking + * for PLL lock. + */ + wmb(); + + /* Check for PLL lock */ + rc = dsi_pll_8998_lock_status(rsc); + if (rc) { + pr_err("PLL(%d) lock failed\n", rsc->index); + goto error; + } + + rsc->pll_on = true; + + dsi_pll_enable_global_clk(rsc); + if (rsc->slave) + dsi_pll_enable_global_clk(rsc->slave); + + MDSS_PLL_REG_W(rsc->phy_base, PHY_CMN_RBUF_CTRL, 0x01); + if (rsc->slave) + MDSS_PLL_REG_W(rsc->slave->phy_base, PHY_CMN_RBUF_CTRL, 0x01); + +error: + return rc; +} + +static void dsi_pll_disable_sub(struct mdss_pll_resources *rsc) +{ + MDSS_PLL_REG_W(rsc->phy_base, PHY_CMN_RBUF_CTRL, 0); + dsi_pll_disable_pll_bias(rsc); +} + +static void dsi_pll_disable(struct dsi_pll_vco_clk *vco) +{ + struct mdss_pll_resources *rsc = vco->priv; + + if (!rsc->pll_on && + mdss_pll_resource_enable(rsc, true)) { + pr_err("failed to enable pll (%d) resources\n", rsc->index); + return; + } + + rsc->handoff_resources = false; + + pr_debug("stop PLL (%d)\n", rsc->index); + + /* + * To avoid any stray glitches while + * abruptly powering down the PLL + * make sure to gate the clock using + * the clock enable bit before powering + * down the PLL + **/ + dsi_pll_disable_global_clk(rsc); + MDSS_PLL_REG_W(rsc->phy_base, PHY_CMN_PLL_CNTRL, 0); + dsi_pll_disable_sub(rsc); + if (rsc->slave) { + dsi_pll_disable_global_clk(rsc->slave); + dsi_pll_disable_sub(rsc->slave); + } + /* flush, ensure all register writes are done*/ + wmb(); + rsc->pll_on = false; +} + +static void vco_8998_unprepare(struct clk *c) +{ + struct dsi_pll_vco_clk *vco = to_vco_clk(c); + struct mdss_pll_resources *pll = vco->priv; + + if (!pll) { + pr_err("dsi pll resources not available\n"); + return; + } + + pll->vco_cached_rate = c->rate; + dsi_pll_disable(vco); + mdss_pll_resource_enable(pll, false); +} + +static int vco_8998_prepare(struct clk *c) +{ + int rc = 0; + struct dsi_pll_vco_clk *vco = to_vco_clk(c); + struct mdss_pll_resources *pll = vco->priv; + + if (!pll) { + pr_err("dsi pll resources are not available\n"); + return -EINVAL; + } + + rc = mdss_pll_resource_enable(pll, true); + if (rc) { + pr_err("failed to enable pll (%d) resource, rc=%d\n", + pll->index, rc); + return rc; + } + + if ((pll->vco_cached_rate != 0) && + (pll->vco_cached_rate == c->rate)) { + rc = c->ops->set_rate(c, pll->vco_cached_rate); + if (rc) { + pr_err("pll(%d) set_rate failed, rc=%d\n", + pll->index, rc); + mdss_pll_resource_enable(pll, false); + return rc; + } + } + + rc = dsi_pll_enable(vco); + if (rc) { + mdss_pll_resource_enable(pll, false); + pr_err("pll(%d) enable failed, rc=%d\n", pll->index, rc); + return rc; + } + + return rc; +} + +static unsigned long dsi_pll_get_vco_rate(struct clk *c) +{ + struct dsi_pll_vco_clk *vco = to_vco_clk(c); + struct mdss_pll_resources *rsc = vco->priv; + struct dsi_pll_8998 *pll = rsc->priv; + struct dsi_pll_regs *regs = &pll->reg_setup; + int rc; + u64 ref_clk = vco->ref_clk_rate; + u64 vco_rate; + u64 multiplier; + u32 frac; + u32 dec; + u32 outdiv; + u64 pll_freq, tmp64; + + rc = mdss_pll_resource_enable(rsc, true); + if (rc) { + pr_err("failed to enable pll(%d) resource, rc=%d\n", + rsc->index, rc); + return 0; + } + + dec = MDSS_PLL_REG_R(rsc->pll_base, PLL_DECIMAL_DIV_START_1); + dec &= 0xFF; + + frac = MDSS_PLL_REG_R(rsc->pll_base, PLL_FRAC_DIV_START_LOW_1); + frac |= ((MDSS_PLL_REG_R(rsc->pll_base, PLL_FRAC_DIV_START_MID_1) & + 0xFF) << + 8); + frac |= ((MDSS_PLL_REG_R(rsc->pll_base, PLL_FRAC_DIV_START_HIGH_1) & + 0x3) << + 16); + + /* OUTDIV_1:0 field is (log(outdiv, 2)) */ + outdiv = MDSS_PLL_REG_R(rsc->pll_base, PLL_PLL_OUTDIV_RATE); + outdiv &= 0x3; + + regs->pll_outdiv_rate = outdiv; + + outdiv = 1 << outdiv; + + /* + * TODO: + * 1. Assumes prescaler is disabled + * 2. Multiplier is 2^18. it should be 2^(num_of_frac_bits) + **/ + multiplier = 1 << 18; + pll_freq = dec * (ref_clk * 2); + tmp64 = (ref_clk * 2 * frac); + pll_freq += div_u64(tmp64, multiplier); + + vco_rate = div_u64(pll_freq, outdiv); + + pr_debug("dec=0x%x, frac=0x%x, outdiv=%d, vco=%llu\n", + dec, frac, outdiv, vco_rate); + + (void)mdss_pll_resource_enable(rsc, false); + + return (unsigned long)vco_rate; +} + +enum handoff vco_8998_handoff(struct clk *c) +{ + enum handoff ret = HANDOFF_DISABLED_CLK; + int rc; + struct dsi_pll_vco_clk *vco = to_vco_clk(c); + struct mdss_pll_resources *pll = vco->priv; + u32 status; + + if (!pll) { + pr_err("Unable to find pll resource\n"); + return HANDOFF_DISABLED_CLK; + } + + rc = mdss_pll_resource_enable(pll, true); + if (rc) { + pr_err("failed to enable pll(%d) resources, rc=%d\n", + pll->index, rc); + return ret; + } + + status = MDSS_PLL_REG_R(pll->pll_base, PLL_COMMON_STATUS_ONE); + if (status & BIT(0)) { + pll->handoff_resources = true; + pll->pll_on = true; + c->rate = dsi_pll_get_vco_rate(c); + ret = HANDOFF_ENABLED_CLK; + } else { + (void)mdss_pll_resource_enable(pll, false); + ret = HANDOFF_DISABLED_CLK; + } + + return ret; +} + +static int pixel_clk_get_div(struct div_clk *clk) +{ + int rc; + struct mdss_pll_resources *pll = clk->priv; + u32 reg_val; + int div; + + rc = mdss_pll_resource_enable(pll, true); + if (rc) { + pr_err("Failed to enable dsi pll resources, rc=%d\n", rc); + return rc; + } + + reg_val = MDSS_PLL_REG_R(pll->phy_base, PHY_CMN_CLK_CFG0); + div = (reg_val & 0xF0) >> 4; + + (void)mdss_pll_resource_enable(pll, false); + + return div; +} + +static void pixel_clk_set_div_sub(struct mdss_pll_resources *pll, int div) +{ + u32 reg_val; + + reg_val = MDSS_PLL_REG_R(pll->phy_base, PHY_CMN_CLK_CFG0); + reg_val &= ~0xF0; + reg_val |= (div << 4); + MDSS_PLL_REG_W(pll->phy_base, PHY_CMN_CLK_CFG0, reg_val); +} + +static int pixel_clk_set_div(struct div_clk *clk, int div) +{ + int rc; + struct mdss_pll_resources *pll = clk->priv; + + rc = mdss_pll_resource_enable(pll, true); + if (rc) { + pr_err("Failed to enable dsi pll resources, rc=%d\n", rc); + return rc; + } + + pixel_clk_set_div_sub(pll, div); + if (pll->slave) + pixel_clk_set_div_sub(pll->slave, div); + + (void)mdss_pll_resource_enable(pll, false); + + return 0; +} + +static int bit_clk_get_div(struct div_clk *clk) +{ + int rc; + struct mdss_pll_resources *pll = clk->priv; + u32 reg_val; + int div; + + rc = mdss_pll_resource_enable(pll, true); + if (rc) { + pr_err("Failed to enable dsi pll resources, rc=%d\n", rc); + return rc; + } + + reg_val = MDSS_PLL_REG_R(pll->phy_base, PHY_CMN_CLK_CFG0); + div = (reg_val & 0x0F); + + (void)mdss_pll_resource_enable(pll, false); + + return div; +} + +static void bit_clk_set_div_sub(struct mdss_pll_resources *rsc, int div) +{ + u32 reg_val; + + reg_val = MDSS_PLL_REG_R(rsc->phy_base, PHY_CMN_CLK_CFG0); + reg_val &= ~0x0F; + reg_val |= div; + MDSS_PLL_REG_W(rsc->phy_base, PHY_CMN_CLK_CFG0, reg_val); +} + +static int bit_clk_set_div(struct div_clk *clk, int div) +{ + int rc; + struct mdss_pll_resources *rsc = clk->priv; + struct dsi_pll_8998 *pll; + + if (!rsc) { + pr_err("pll resource not found\n"); + return -EINVAL; + } + + pll = rsc->priv; + if (!pll) { + pr_err("pll configuration not found\n"); + return -EINVAL; + } + + rc = mdss_pll_resource_enable(rsc, true); + if (rc) { + pr_err("Failed to enable dsi pll resources, rc=%d\n", rc); + return rc; + } + + bit_clk_set_div_sub(rsc, div); + /* For slave PLL, this divider always should be set to 1 */ + if (rsc->slave) + bit_clk_set_div_sub(rsc->slave, 1); + + (void)mdss_pll_resource_enable(rsc, false); + + return rc; +} + +static int dsi_pll_out_set_mux_sel(struct mux_clk *clk, int sel) +{ + struct mdss_pll_resources *rsc = clk->priv; + struct dsi_pll_8998 *pll = rsc->priv; + struct dsi_pll_regs *regs = &pll->reg_setup; + + regs->pll_outdiv_rate = sel; + + return 0; +} + +static int dsi_pll_out_get_mux_sel(struct mux_clk *clk) +{ + struct mdss_pll_resources *rsc = clk->priv; + struct dsi_pll_8998 *pll = rsc->priv; + struct dsi_pll_regs *regs = &pll->reg_setup; + + return regs->pll_outdiv_rate; +} + +static int post_vco_clk_get_div(struct div_clk *clk) +{ + int rc; + struct mdss_pll_resources *pll = clk->priv; + u32 reg_val; + int div; + + rc = mdss_pll_resource_enable(pll, true); + if (rc) { + pr_err("Failed to enable dsi pll resources, rc=%d\n", rc); + return rc; + } + + reg_val = MDSS_PLL_REG_R(pll->phy_base, PHY_CMN_CLK_CFG1); + reg_val &= 0x3; + + if (reg_val == 2) + div = 1; + else if (reg_val == 3) + div = 4; + else + div = 1; + + (void)mdss_pll_resource_enable(pll, false); + + return div; +} + +static int post_vco_clk_set_div_sub(struct mdss_pll_resources *pll, int div) +{ + u32 reg_val; + int rc = 0; + + reg_val = MDSS_PLL_REG_R(pll->phy_base, PHY_CMN_CLK_CFG1); + reg_val &= ~0x03; + if (div == 1) { + reg_val |= 0x2; + } else if (div == 4) { + reg_val |= 0x3; + } else { + rc = -EINVAL; + pr_err("unsupported divider %d\n", div); + goto error; + } + + MDSS_PLL_REG_W(pll->phy_base, PHY_CMN_CLK_CFG1, reg_val); + +error: + return rc; +} + +static int post_vco_clk_set_div(struct div_clk *clk, int div) +{ + int rc = 0; + struct mdss_pll_resources *pll = clk->priv; + + rc = mdss_pll_resource_enable(pll, true); + if (rc) { + pr_err("Failed to enable dsi pll resources, rc=%d\n", rc); + return rc; + } + + rc = post_vco_clk_set_div_sub(pll, div); + if (!rc && pll->slave) + rc = post_vco_clk_set_div_sub(pll->slave, div); + + (void)mdss_pll_resource_enable(pll, false); + + return rc; +} + +static int post_bit_clk_get_div(struct div_clk *clk) +{ + int rc; + struct mdss_pll_resources *pll = clk->priv; + u32 reg_val; + int div; + + rc = mdss_pll_resource_enable(pll, true); + if (rc) { + pr_err("Failed to enable dsi pll resources, rc=%d\n", rc); + return rc; + } + + reg_val = MDSS_PLL_REG_R(pll->phy_base, PHY_CMN_CLK_CFG1); + reg_val &= 0x3; + + if (reg_val == 0) + div = 1; + else if (reg_val == 1) + div = 2; + else + div = 1; + + (void)mdss_pll_resource_enable(pll, false); + + return div; +} + +static int post_bit_clk_set_div_sub(struct mdss_pll_resources *pll, int div) +{ + int rc = 0; + u32 reg_val; + + reg_val = MDSS_PLL_REG_R(pll->phy_base, PHY_CMN_CLK_CFG1); + reg_val &= ~0x03; + if (div == 1) { + reg_val |= 0x0; + } else if (div == 2) { + reg_val |= 0x1; + } else { + rc = -EINVAL; + pr_err("unsupported divider %d\n", div); + goto error; + } + + MDSS_PLL_REG_W(pll->phy_base, PHY_CMN_CLK_CFG1, reg_val); + +error: + return rc; +} + +static int post_bit_clk_set_div(struct div_clk *clk, int div) +{ + int rc = 0; + struct mdss_pll_resources *pll = clk->priv; + + rc = mdss_pll_resource_enable(pll, true); + if (rc) { + pr_err("Failed to enable dsi pll resources, rc=%d\n", rc); + return rc; + } + + rc = post_bit_clk_set_div_sub(pll, div); + if (!rc && pll->slave) + rc = post_bit_clk_set_div_sub(pll->slave, div); + + (void)mdss_pll_resource_enable(pll, false); + + return rc; +} + +long vco_8998_round_rate(struct clk *c, unsigned long rate) +{ + unsigned long rrate = rate; + struct dsi_pll_vco_clk *vco = to_vco_clk(c); + + if (rate < vco->min_rate) + rrate = vco->min_rate; + if (rate > vco->max_rate) + rrate = vco->max_rate; + + return rrate; +} + +/* clk ops that require runtime fixup */ +static struct clk_ops clk_ops_gen_mux_dsi; +static struct clk_ops clk_ops_bitclk_src_c; +static struct clk_ops clk_ops_post_vco_div_c; +static struct clk_ops clk_ops_post_bit_div_c; +static struct clk_ops clk_ops_pclk_src_c; + +static struct clk_div_ops clk_post_vco_div_ops = { + .set_div = post_vco_clk_set_div, + .get_div = post_vco_clk_get_div, +}; + +static struct clk_div_ops clk_post_bit_div_ops = { + .set_div = post_bit_clk_set_div, + .get_div = post_bit_clk_get_div, +}; + +static struct clk_div_ops pixel_clk_div_ops = { + .set_div = pixel_clk_set_div, + .get_div = pixel_clk_get_div, +}; + +static struct clk_div_ops clk_bitclk_src_ops = { + .set_div = bit_clk_set_div, + .get_div = bit_clk_get_div, +}; + +static struct clk_ops clk_ops_vco_8998 = { + .set_rate = vco_8998_set_rate, + .round_rate = vco_8998_round_rate, + .handoff = vco_8998_handoff, + .prepare = vco_8998_prepare, + .unprepare = vco_8998_unprepare, +}; + +static struct clk_mux_ops mdss_mux_ops = { + .set_mux_sel = mdss_set_mux_sel, + .get_mux_sel = mdss_get_mux_sel, +}; + +static struct clk_mux_ops mdss_pll_out_mux_ops = { + .set_mux_sel = dsi_pll_out_set_mux_sel, + .get_mux_sel = dsi_pll_out_get_mux_sel, +}; + +/* + * Clock tree for generating DSI byte and pixel clocks. + * + * +---------------+ + * | vco_clk | + * | | + * +-------+-------+ + * | + * | + * +-------+--------+------------------+-----------------+ + * | | | | + * +------v-------+ +------v-------+ +-------v------+ +------v-------+ + * | pll_out_div1 | | pll_out_div2 | | pll_out_div4 | | pll_out_div8 | + * | DIV(1) | | DIV(2) | | DIV(4) | | DIV(8) | + * +------+-------+ +------+-------+ +-------+------+ +------+-------+ + * | | | | + * +------------+ | +--------------+ | + * | | | +---------------------------+ + * | | | | + * +--v---v---v----v--+ + * \ pll_out_mux / + * \ / + * +------+-----+ + * | + * +---------------+-----------------+ + * | | | + * +------v-----+ +-------v-------+ +-------v-------+ + * | bitclk_src | | post_vco_div1 | | post_vco_div4 | + * | DIV(1..15) | + DIV(1) | | DIV(4) | + * +------+-----+ +-------+-------+ +-------+-------+ + * | | | + * Shadow | | +---------------------+ + * Path | +-----------------------------+ | + * + | | | + * | +---------------------------------+ | | + * | | | | | + * | +------v------=+ +------v-------+ +-v---------v----+ + * | | byteclk_src | | post_bit_div | \ post_vco_mux / + * | | DIV(8) | | DIV(1,2) | \ / + * | +------+-------+ +------+-------+ +---+------+ + * | | | | + * | | | +----------+ + * | | | | + * | | +----v-----v------+ + * +-v--------v---------+ \ pclk_src_mux / + * \ byteclk_mux / \ / + * \ / +-----+-----+ + * +------+-------+ | Shadow + * | | Path + * v +-----v------+ + + * dsi_byte_clk | pclk_src | | + * | DIV(1..15) | | + * +-----+------+ | + * | | + * +------+ | + * | | + * +---v----v----+ + * \ pclk_mux / + * \ / + * +---+---+ + * | + * | + * v + * dsi_pclk + * + */ + +static struct dsi_pll_vco_clk dsi0pll_vco_clk = { + .ref_clk_rate = 19200000UL, + .min_rate = 1000000000UL, + .max_rate = 3500000000UL, + .c = { + .dbg_name = "dsi0pll_vco_clk", + .ops = &clk_ops_vco_8998, + .flags = CLKFLAG_NO_RATE_CACHE, + CLK_INIT(dsi0pll_vco_clk.c), + }, +}; + +static struct div_clk dsi0pll_pll_out_div1 = { + .data = { + .div = 1, + .min_div = 1, + .max_div = 1, + }, + .c = { + .parent = &dsi0pll_vco_clk.c, + .dbg_name = "dsi0pll_pll_out_div1", + .ops = &clk_ops_div, + .flags = CLKFLAG_NO_RATE_CACHE, + CLK_INIT(dsi0pll_pll_out_div1.c), + } +}; + +static struct div_clk dsi0pll_pll_out_div2 = { + .data = { + .div = 2, + .min_div = 2, + .max_div = 2, + }, + .c = { + .parent = &dsi0pll_vco_clk.c, + .dbg_name = "dsi0pll_pll_out_div2", + .ops = &clk_ops_div, + .flags = CLKFLAG_NO_RATE_CACHE, + CLK_INIT(dsi0pll_pll_out_div2.c), + } +}; + +static struct div_clk dsi0pll_pll_out_div4 = { + .data = { + .div = 4, + .min_div = 4, + .max_div = 4, + }, + .c = { + .parent = &dsi0pll_vco_clk.c, + .dbg_name = "dsi0pll_pll_out_div4", + .ops = &clk_ops_div, + .flags = CLKFLAG_NO_RATE_CACHE, + CLK_INIT(dsi0pll_pll_out_div4.c), + } +}; + +static struct div_clk dsi0pll_pll_out_div8 = { + .data = { + .div = 8, + .min_div = 8, + .max_div = 8, + }, + .c = { + .parent = &dsi0pll_vco_clk.c, + .dbg_name = "dsi0pll_pll_out_div8", + .ops = &clk_ops_div, + .flags = CLKFLAG_NO_RATE_CACHE, + CLK_INIT(dsi0pll_pll_out_div8.c), + } +}; + +static struct mux_clk dsi0pll_pll_out_mux = { + .num_parents = 4, + .parents = (struct clk_src[]) { + {&dsi0pll_pll_out_div1.c, 0}, + {&dsi0pll_pll_out_div2.c, 1}, + {&dsi0pll_pll_out_div4.c, 2}, + {&dsi0pll_pll_out_div8.c, 3}, + }, + .ops = &mdss_pll_out_mux_ops, + .c = { + .parent = &dsi0pll_pll_out_div1.c, + .dbg_name = "dsi0pll_pll_out_mux", + .ops = &clk_ops_gen_mux, + .flags = CLKFLAG_NO_RATE_CACHE, + CLK_INIT(dsi0pll_pll_out_mux.c), + } +}; +static struct div_clk dsi0pll_bitclk_src = { + .data = { + .div = 1, + .min_div = 1, + .max_div = 15, + }, + .ops = &clk_bitclk_src_ops, + .c = { + .parent = &dsi0pll_pll_out_mux.c, + .dbg_name = "dsi0pll_bitclk_src", + .ops = &clk_ops_bitclk_src_c, + .flags = CLKFLAG_NO_RATE_CACHE, + CLK_INIT(dsi0pll_bitclk_src.c), + } +}; + +static struct div_clk dsi0pll_post_vco_div1 = { + .data = { + .div = 1, + .min_div = 1, + .max_div = 1, + }, + .ops = &clk_post_vco_div_ops, + .c = { + .parent = &dsi0pll_pll_out_mux.c, + .dbg_name = "dsi0pll_post_vco_div1", + .ops = &clk_ops_post_vco_div_c, + .flags = CLKFLAG_NO_RATE_CACHE, + CLK_INIT(dsi0pll_post_vco_div1.c), + } +}; + +static struct div_clk dsi0pll_post_vco_div4 = { + .data = { + .div = 4, + .min_div = 4, + .max_div = 4, + }, + .ops = &clk_post_vco_div_ops, + .c = { + .parent = &dsi0pll_pll_out_mux.c, + .dbg_name = "dsi0pll_post_vco_div4", + .ops = &clk_ops_post_vco_div_c, + .flags = CLKFLAG_NO_RATE_CACHE, + CLK_INIT(dsi0pll_post_vco_div4.c), + } +}; + +static struct mux_clk dsi0pll_post_vco_mux = { + .num_parents = 2, + .parents = (struct clk_src[]) { + {&dsi0pll_post_vco_div1.c, 0}, + {&dsi0pll_post_vco_div4.c, 1}, + }, + .ops = &mdss_mux_ops, + .c = { + .parent = &dsi0pll_post_vco_div1.c, + .dbg_name = "dsi0pll_post_vco_mux", + .ops = &clk_ops_gen_mux, + .flags = CLKFLAG_NO_RATE_CACHE, + CLK_INIT(dsi0pll_post_vco_mux.c), + } +}; + +static struct div_clk dsi0pll_post_bit_div = { + .data = { + .div = 1, + .min_div = 1, + .max_div = 2, + }, + .ops = &clk_post_bit_div_ops, + .c = { + .parent = &dsi0pll_bitclk_src.c, + .dbg_name = "dsi0pll_post_bit_div", + .ops = &clk_ops_post_bit_div_c, + .flags = CLKFLAG_NO_RATE_CACHE, + CLK_INIT(dsi0pll_post_bit_div.c), + } +}; + +static struct mux_clk dsi0pll_pclk_src_mux = { + .num_parents = 2, + .parents = (struct clk_src[]) { + {&dsi0pll_post_bit_div.c, 0}, + {&dsi0pll_post_vco_mux.c, 1}, + }, + .ops = &mdss_mux_ops, + .c = { + .parent = &dsi0pll_post_bit_div.c, + .dbg_name = "dsi0pll_pclk_src_mux", + .ops = &clk_ops_gen_mux, + .flags = CLKFLAG_NO_RATE_CACHE, + CLK_INIT(dsi0pll_pclk_src_mux.c), + } +}; + +static struct div_clk dsi0pll_pclk_src = { + .data = { + .div = 1, + .min_div = 1, + .max_div = 15, + }, + .ops = &pixel_clk_div_ops, + .c = { + .parent = &dsi0pll_pclk_src_mux.c, + .dbg_name = "dsi0pll_pclk_src", + .ops = &clk_ops_pclk_src_c, + .flags = CLKFLAG_NO_RATE_CACHE, + CLK_INIT(dsi0pll_pclk_src.c), + }, +}; + +static struct mux_clk dsi0pll_pclk_mux = { + .num_parents = 1, + .parents = (struct clk_src[]) { + {&dsi0pll_pclk_src.c, 0}, + }, + .ops = &mdss_mux_ops, + .c = { + .parent = &dsi0pll_pclk_src.c, + .dbg_name = "dsi0pll_pclk_mux", + .ops = &clk_ops_gen_mux_dsi, + .flags = CLKFLAG_NO_RATE_CACHE, + CLK_INIT(dsi0pll_pclk_mux.c), + } +}; + +static struct div_clk dsi0pll_byteclk_src = { + .data = { + .div = 8, + .min_div = 8, + .max_div = 8, + }, + .c = { + .parent = &dsi0pll_bitclk_src.c, + .dbg_name = "dsi0pll_byteclk_src", + .ops = &clk_ops_div, + .flags = CLKFLAG_NO_RATE_CACHE, + CLK_INIT(dsi0pll_byteclk_src.c), + }, +}; + +static struct mux_clk dsi0pll_byteclk_mux = { + .num_parents = 1, + .parents = (struct clk_src[]) { + {&dsi0pll_byteclk_src.c, 0}, + }, + .ops = &mdss_mux_ops, + .c = { + .parent = &dsi0pll_byteclk_src.c, + .dbg_name = "dsi0pll_byteclk_mux", + .ops = &clk_ops_gen_mux_dsi, + .flags = CLKFLAG_NO_RATE_CACHE, + CLK_INIT(dsi0pll_byteclk_mux.c), + } +}; + +static struct dsi_pll_vco_clk dsi1pll_vco_clk = { + .ref_clk_rate = 19200000UL, + .min_rate = 1000000000UL, + .max_rate = 3500000000UL, + .c = { + .dbg_name = "dsi1pll_vco_clk", + .ops = &clk_ops_vco_8998, + .flags = CLKFLAG_NO_RATE_CACHE, + CLK_INIT(dsi1pll_vco_clk.c), + }, +}; + +static struct div_clk dsi1pll_pll_out_div1 = { + .data = { + .div = 1, + .min_div = 1, + .max_div = 1, + }, + .c = { + .parent = &dsi1pll_vco_clk.c, + .dbg_name = "dsi1pll_pll_out_div1", + .ops = &clk_ops_div, + .flags = CLKFLAG_NO_RATE_CACHE, + CLK_INIT(dsi1pll_pll_out_div1.c), + } +}; + +static struct div_clk dsi1pll_pll_out_div2 = { + .data = { + .div = 2, + .min_div = 2, + .max_div = 2, + }, + .c = { + .parent = &dsi1pll_vco_clk.c, + .dbg_name = "dsi1pll_pll_out_div2", + .ops = &clk_ops_div, + .flags = CLKFLAG_NO_RATE_CACHE, + CLK_INIT(dsi1pll_pll_out_div2.c), + } +}; + +static struct div_clk dsi1pll_pll_out_div4 = { + .data = { + .div = 4, + .min_div = 4, + .max_div = 4, + }, + .c = { + .parent = &dsi1pll_vco_clk.c, + .dbg_name = "dsi1pll_pll_out_div4", + .ops = &clk_ops_div, + .flags = CLKFLAG_NO_RATE_CACHE, + CLK_INIT(dsi1pll_pll_out_div4.c), + } +}; + +static struct div_clk dsi1pll_pll_out_div8 = { + .data = { + .div = 8, + .min_div = 8, + .max_div = 8, + }, + .c = { + .parent = &dsi1pll_vco_clk.c, + .dbg_name = "dsi1pll_pll_out_div8", + .ops = &clk_ops_div, + .flags = CLKFLAG_NO_RATE_CACHE, + CLK_INIT(dsi1pll_pll_out_div8.c), + } +}; + +static struct mux_clk dsi1pll_pll_out_mux = { + .num_parents = 4, + .parents = (struct clk_src[]) { + {&dsi1pll_pll_out_div1.c, 0}, + {&dsi1pll_pll_out_div2.c, 1}, + {&dsi1pll_pll_out_div4.c, 2}, + {&dsi1pll_pll_out_div8.c, 3}, + }, + .ops = &mdss_pll_out_mux_ops, + .c = { + .parent = &dsi1pll_pll_out_div1.c, + .dbg_name = "dsi1pll_pll_out_mux", + .ops = &clk_ops_gen_mux, + .flags = CLKFLAG_NO_RATE_CACHE, + CLK_INIT(dsi1pll_pll_out_mux.c), + } +}; + +static struct div_clk dsi1pll_bitclk_src = { + .data = { + .div = 1, + .min_div = 1, + .max_div = 15, + }, + .ops = &clk_bitclk_src_ops, + .c = { + .parent = &dsi1pll_pll_out_mux.c, + .dbg_name = "dsi1pll_bitclk_src", + .ops = &clk_ops_bitclk_src_c, + .flags = CLKFLAG_NO_RATE_CACHE, + CLK_INIT(dsi1pll_bitclk_src.c), + } +}; + +static struct div_clk dsi1pll_post_vco_div1 = { + .data = { + .div = 1, + .min_div = 1, + .max_div = 1, + }, + .ops = &clk_post_vco_div_ops, + .c = { + .parent = &dsi1pll_pll_out_mux.c, + .dbg_name = "dsi1pll_post_vco_div1", + .ops = &clk_ops_post_vco_div_c, + .flags = CLKFLAG_NO_RATE_CACHE, + CLK_INIT(dsi1pll_post_vco_div1.c), + } +}; + +static struct div_clk dsi1pll_post_vco_div4 = { + .data = { + .div = 4, + .min_div = 4, + .max_div = 4, + }, + .ops = &clk_post_vco_div_ops, + .c = { + .parent = &dsi1pll_pll_out_mux.c, + .dbg_name = "dsi1pll_post_vco_div4", + .ops = &clk_ops_post_vco_div_c, + .flags = CLKFLAG_NO_RATE_CACHE, + CLK_INIT(dsi1pll_post_vco_div4.c), + } +}; + +static struct mux_clk dsi1pll_post_vco_mux = { + .num_parents = 2, + .parents = (struct clk_src[]) { + {&dsi1pll_post_vco_div1.c, 0}, + {&dsi1pll_post_vco_div4.c, 1}, + }, + .ops = &mdss_mux_ops, + .c = { + .parent = &dsi1pll_post_vco_div1.c, + .dbg_name = "dsi1pll_post_vco_mux", + .ops = &clk_ops_gen_mux, + .flags = CLKFLAG_NO_RATE_CACHE, + CLK_INIT(dsi1pll_post_vco_mux.c), + } +}; + +static struct div_clk dsi1pll_post_bit_div = { + .data = { + .div = 1, + .min_div = 1, + .max_div = 2, + }, + .ops = &clk_post_bit_div_ops, + .c = { + .parent = &dsi1pll_bitclk_src.c, + .dbg_name = "dsi1pll_post_bit_div", + .ops = &clk_ops_post_bit_div_c, + .flags = CLKFLAG_NO_RATE_CACHE, + CLK_INIT(dsi1pll_post_bit_div.c), + } +}; + +static struct mux_clk dsi1pll_pclk_src_mux = { + .num_parents = 2, + .parents = (struct clk_src[]) { + {&dsi1pll_post_bit_div.c, 0}, + {&dsi1pll_post_vco_mux.c, 1}, + }, + .ops = &mdss_mux_ops, + .c = { + .parent = &dsi1pll_post_bit_div.c, + .dbg_name = "dsi1pll_pclk_src_mux", + .ops = &clk_ops_gen_mux, + .flags = CLKFLAG_NO_RATE_CACHE, + CLK_INIT(dsi1pll_pclk_src_mux.c), + } +}; + +static struct div_clk dsi1pll_pclk_src = { + .data = { + .div = 1, + .min_div = 1, + .max_div = 15, + }, + .ops = &pixel_clk_div_ops, + .c = { + .parent = &dsi1pll_pclk_src_mux.c, + .dbg_name = "dsi1pll_pclk_src", + .ops = &clk_ops_pclk_src_c, + .flags = CLKFLAG_NO_RATE_CACHE, + CLK_INIT(dsi1pll_pclk_src.c), + }, +}; + +static struct mux_clk dsi1pll_pclk_mux = { + .num_parents = 1, + .parents = (struct clk_src[]) { + {&dsi1pll_pclk_src.c, 0}, + }, + .ops = &mdss_mux_ops, + .c = { + .parent = &dsi1pll_pclk_src.c, + .dbg_name = "dsi1pll_pclk_mux", + .ops = &clk_ops_gen_mux_dsi, + .flags = CLKFLAG_NO_RATE_CACHE, + CLK_INIT(dsi1pll_pclk_mux.c), + } +}; + +static struct div_clk dsi1pll_byteclk_src = { + .data = { + .div = 8, + .min_div = 8, + .max_div = 8, + }, + .c = { + .parent = &dsi1pll_bitclk_src.c, + .dbg_name = "dsi1pll_byteclk_src", + .ops = &clk_ops_div, + .flags = CLKFLAG_NO_RATE_CACHE, + CLK_INIT(dsi1pll_byteclk_src.c), + }, +}; + +static struct mux_clk dsi1pll_byteclk_mux = { + .num_parents = 1, + .parents = (struct clk_src[]) { + {&dsi1pll_byteclk_src.c, 0}, + }, + .ops = &mdss_mux_ops, + .c = { + .parent = &dsi1pll_byteclk_src.c, + .dbg_name = "dsi1pll_byteclk_mux", + .ops = &clk_ops_gen_mux_dsi, + .flags = CLKFLAG_NO_RATE_CACHE, + CLK_INIT(dsi1pll_byteclk_mux.c), + } +}; + +static struct clk_lookup mdss_dsi_pll0cc_8998[] = { + CLK_LIST(dsi0pll_byteclk_mux), + CLK_LIST(dsi0pll_byteclk_src), + CLK_LIST(dsi0pll_pclk_mux), + CLK_LIST(dsi0pll_pclk_src), + CLK_LIST(dsi0pll_pclk_src_mux), + CLK_LIST(dsi0pll_post_bit_div), + CLK_LIST(dsi0pll_post_vco_mux), + CLK_LIST(dsi0pll_post_vco_div1), + CLK_LIST(dsi0pll_post_vco_div4), + CLK_LIST(dsi0pll_bitclk_src), + CLK_LIST(dsi0pll_pll_out_mux), + CLK_LIST(dsi0pll_pll_out_div8), + CLK_LIST(dsi0pll_pll_out_div4), + CLK_LIST(dsi0pll_pll_out_div2), + CLK_LIST(dsi0pll_pll_out_div1), + CLK_LIST(dsi0pll_vco_clk), +}; +static struct clk_lookup mdss_dsi_pll1cc_8998[] = { + CLK_LIST(dsi1pll_byteclk_mux), + CLK_LIST(dsi1pll_byteclk_src), + CLK_LIST(dsi1pll_pclk_mux), + CLK_LIST(dsi1pll_pclk_src), + CLK_LIST(dsi1pll_pclk_src_mux), + CLK_LIST(dsi1pll_post_bit_div), + CLK_LIST(dsi1pll_post_vco_mux), + CLK_LIST(dsi1pll_post_vco_div1), + CLK_LIST(dsi1pll_post_vco_div4), + CLK_LIST(dsi1pll_bitclk_src), + CLK_LIST(dsi1pll_pll_out_mux), + CLK_LIST(dsi1pll_pll_out_div8), + CLK_LIST(dsi1pll_pll_out_div4), + CLK_LIST(dsi1pll_pll_out_div2), + CLK_LIST(dsi1pll_pll_out_div1), + CLK_LIST(dsi1pll_vco_clk), +}; + +int dsi_pll_clock_register_8998(struct platform_device *pdev, + struct mdss_pll_resources *pll_res) +{ + int rc = 0, ndx; + + if (!pdev || !pdev->dev.of_node || + !pll_res || !pll_res->pll_base || !pll_res->phy_base) { + pr_err("Invalid params\n"); + return -EINVAL; + } + + ndx = pll_res->index; + + if (ndx >= DSI_PLL_MAX) { + pr_err("pll index(%d) NOT supported\n", ndx); + return -EINVAL; + } + + pll_rsc_db[ndx] = pll_res; + pll_res->priv = &plls[ndx]; + plls[ndx].rsc = pll_res; + + /* runtime fixup of all div and mux clock ops */ + clk_ops_gen_mux_dsi = clk_ops_gen_mux; + clk_ops_gen_mux_dsi.round_rate = parent_round_rate; + clk_ops_gen_mux_dsi.set_rate = parent_set_rate; + + clk_ops_bitclk_src_c = clk_ops_div; + clk_ops_bitclk_src_c.prepare = mdss_pll_div_prepare; + + /* + * Set the ops for the two dividers in the pixel clock tree to the + * slave_div to ensure that a set rate on this divider clock will not + * be propagated to it's parent. This is needed ensure that when we set + * the rate for pixel clock, the vco is not reconfigured + */ + clk_ops_post_vco_div_c = clk_ops_slave_div; + clk_ops_post_vco_div_c.prepare = mdss_pll_div_prepare; + + clk_ops_post_bit_div_c = clk_ops_slave_div; + clk_ops_post_bit_div_c.prepare = mdss_pll_div_prepare; + + clk_ops_pclk_src_c = clk_ops_div; + clk_ops_pclk_src_c.prepare = mdss_pll_div_prepare; + + pll_res->vco_delay = VCO_DELAY_USEC; + if (ndx == 0) { + dsi0pll_byteclk_mux.priv = pll_res; + dsi0pll_byteclk_src.priv = pll_res; + dsi0pll_pclk_mux.priv = pll_res; + dsi0pll_pclk_src.priv = pll_res; + dsi0pll_pclk_src_mux.priv = pll_res; + dsi0pll_post_bit_div.priv = pll_res; + dsi0pll_post_vco_mux.priv = pll_res; + dsi0pll_post_vco_div1.priv = pll_res; + dsi0pll_post_vco_div4.priv = pll_res; + dsi0pll_bitclk_src.priv = pll_res; + dsi0pll_pll_out_div1.priv = pll_res; + dsi0pll_pll_out_div2.priv = pll_res; + dsi0pll_pll_out_div4.priv = pll_res; + dsi0pll_pll_out_div8.priv = pll_res; + dsi0pll_pll_out_mux.priv = pll_res; + dsi0pll_vco_clk.priv = pll_res; + + rc = of_msm_clock_register(pdev->dev.of_node, + mdss_dsi_pll0cc_8998, + ARRAY_SIZE(mdss_dsi_pll0cc_8998)); + } else { + dsi1pll_byteclk_mux.priv = pll_res; + dsi1pll_byteclk_src.priv = pll_res; + dsi1pll_pclk_mux.priv = pll_res; + dsi1pll_pclk_src.priv = pll_res; + dsi1pll_pclk_src_mux.priv = pll_res; + dsi1pll_post_bit_div.priv = pll_res; + dsi1pll_post_vco_mux.priv = pll_res; + dsi1pll_post_vco_div1.priv = pll_res; + dsi1pll_post_vco_div4.priv = pll_res; + dsi1pll_bitclk_src.priv = pll_res; + dsi1pll_pll_out_div1.priv = pll_res; + dsi1pll_pll_out_div2.priv = pll_res; + dsi1pll_pll_out_div4.priv = pll_res; + dsi1pll_pll_out_div8.priv = pll_res; + dsi1pll_pll_out_mux.priv = pll_res; + dsi1pll_vco_clk.priv = pll_res; + + rc = of_msm_clock_register(pdev->dev.of_node, + mdss_dsi_pll1cc_8998, + ARRAY_SIZE(mdss_dsi_pll1cc_8998)); + } + if (rc) + pr_err("dsi%dpll clock register failed, rc=%d\n", ndx, rc); + + return rc; +} diff -Nruw linux-4.4.115-fbx/drivers/clk/msm./mdss/mdss-dsi-pll.h linux-4.4.115-fbx/drivers/clk/msm/mdss/mdss-dsi-pll.h --- linux-4.4.115-fbx/drivers/clk/msm./mdss/mdss-dsi-pll.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-4.4.115-fbx/drivers/clk/msm/mdss/mdss-dsi-pll.h 2019-01-22 16:16:23.019242024 +0100 @@ -0,0 +1,110 @@ +/* Copyright (c) 2012-2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __MDSS_DSI_PLL_H +#define __MDSS_DSI_PLL_H + +#define MAX_DSI_PLL_EN_SEQS 10 + +#define DSI_PHY_PLL_UNIPHY_PLL_GLB_CFG (0x0020) +#define DSI_PHY_PLL_UNIPHY_PLL_LKDET_CFG2 (0x0064) +#define DSI_PHY_PLL_UNIPHY_PLL_TEST_CFG (0x0068) +#define DSI_PHY_PLL_UNIPHY_PLL_CAL_CFG1 (0x0070) + +/* Register offsets for 20nm PHY PLL */ +#define MMSS_DSI_PHY_PLL_PLL_CNTRL (0x0014) +#define MMSS_DSI_PHY_PLL_PLL_BKG_KVCO_CAL_EN (0x002C) +#define MMSS_DSI_PHY_PLL_PLLLOCK_CMP_EN (0x009C) + +struct lpfr_cfg { + unsigned long vco_rate; + u32 r; +}; + +struct dsi_pll_vco_clk { + unsigned long ref_clk_rate; + unsigned long min_rate; + unsigned long max_rate; + u32 pll_en_seq_cnt; + struct lpfr_cfg *lpfr_lut; + u32 lpfr_lut_size; + void *priv; + + struct clk c; + + int (*pll_enable_seqs[MAX_DSI_PLL_EN_SEQS]) + (struct mdss_pll_resources *dsi_pll_Res); +}; + +static inline struct dsi_pll_vco_clk *to_vco_clk(struct clk *clk) +{ + return container_of(clk, struct dsi_pll_vco_clk, c); +} + +int dsi_pll_clock_register_hpm(struct platform_device *pdev, + struct mdss_pll_resources *pll_res); +int dsi_pll_clock_register_20nm(struct platform_device *pdev, + struct mdss_pll_resources *pll_res); +int dsi_pll_clock_register_lpm(struct platform_device *pdev, + struct mdss_pll_resources *pll_res); +int dsi_pll_clock_register_8996(struct platform_device *pdev, + struct mdss_pll_resources *pll_res); +int dsi_pll_clock_register_8998(struct platform_device *pdev, + struct mdss_pll_resources *pll_res); + +int set_byte_mux_sel(struct mux_clk *clk, int sel); +int get_byte_mux_sel(struct mux_clk *clk); +int dsi_pll_mux_prepare(struct clk *c); +int fixed_4div_set_div(struct div_clk *clk, int div); +int fixed_4div_get_div(struct div_clk *clk); +int digital_set_div(struct div_clk *clk, int div); +int digital_get_div(struct div_clk *clk); +int analog_set_div(struct div_clk *clk, int div); +int analog_get_div(struct div_clk *clk); +int dsi_pll_lock_status(struct mdss_pll_resources *dsi_pll_res); +int vco_set_rate(struct dsi_pll_vco_clk *vco, unsigned long rate); +unsigned long vco_get_rate(struct clk *c); +long vco_round_rate(struct clk *c, unsigned long rate); +enum handoff vco_handoff(struct clk *c); +int vco_prepare(struct clk *c); +void vco_unprepare(struct clk *c); + +/* APIs for 20nm PHY PLL */ +int pll_20nm_vco_set_rate(struct dsi_pll_vco_clk *vco, unsigned long rate); +int shadow_pll_20nm_vco_set_rate(struct dsi_pll_vco_clk *vco, + unsigned long rate); +long pll_20nm_vco_round_rate(struct clk *c, unsigned long rate); +enum handoff pll_20nm_vco_handoff(struct clk *c); +int pll_20nm_vco_prepare(struct clk *c); +void pll_20nm_vco_unprepare(struct clk *c); +int pll_20nm_vco_enable_seq(struct mdss_pll_resources *dsi_pll_res); + +int set_bypass_lp_div_mux_sel(struct mux_clk *clk, int sel); +int set_shadow_bypass_lp_div_mux_sel(struct mux_clk *clk, int sel); +int get_bypass_lp_div_mux_sel(struct mux_clk *clk); +int fixed_hr_oclk2_set_div(struct div_clk *clk, int div); +int shadow_fixed_hr_oclk2_set_div(struct div_clk *clk, int div); +int fixed_hr_oclk2_get_div(struct div_clk *clk); +int hr_oclk3_set_div(struct div_clk *clk, int div); +int shadow_hr_oclk3_set_div(struct div_clk *clk, int div); +int hr_oclk3_get_div(struct div_clk *clk); +int ndiv_set_div(struct div_clk *clk, int div); +int shadow_ndiv_set_div(struct div_clk *clk, int div); +int ndiv_get_div(struct div_clk *clk); +void __dsi_pll_disable(void __iomem *pll_base); + +int set_mdss_pixel_mux_sel(struct mux_clk *clk, int sel); +int get_mdss_pixel_mux_sel(struct mux_clk *clk); +int set_mdss_byte_mux_sel(struct mux_clk *clk, int sel); +int get_mdss_byte_mux_sel(struct mux_clk *clk); + +#endif diff -Nruw linux-4.4.115-fbx/drivers/clk/msm./mdss/mdss-hdmi-pll-8996.c linux-4.4.115-fbx/drivers/clk/msm/mdss/mdss-hdmi-pll-8996.c --- linux-4.4.115-fbx/drivers/clk/msm./mdss/mdss-hdmi-pll-8996.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-4.4.115-fbx/drivers/clk/msm/mdss/mdss-hdmi-pll-8996.c 2019-01-22 16:16:23.023242060 +0100 @@ -0,0 +1,2683 @@ +/* Copyright (c) 2014-2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "mdss-pll.h" +#include "mdss-hdmi-pll.h" + +/* CONSTANTS */ +#define HDMI_BIT_CLK_TO_PIX_CLK_RATIO 10 +#define HDMI_HIGH_FREQ_BIT_CLK_THRESHOLD 3400000000UL +#define HDMI_DIG_FREQ_BIT_CLK_THRESHOLD 1500000000UL +#define HDMI_MID_FREQ_BIT_CLK_THRESHOLD 750000000 +#define HDMI_CLKS_PLL_DIVSEL 0 +#define HDMI_CORECLK_DIV 5 +#define HDMI_REF_CLOCK 19200000 +#define HDMI_64B_ERR_VAL 0xFFFFFFFFFFFFFFFF +#define HDMI_VERSION_8996_V1 1 +#define HDMI_VERSION_8996_V2 2 +#define HDMI_VERSION_8996_V3 3 +#define HDMI_VERSION_8996_V3_1_8 4 + +#define HDMI_VCO_MAX_FREQ 12000000000 +#define HDMI_VCO_MIN_FREQ 8000000000 +#define HDMI_2400MHZ_BIT_CLK_HZ 2400000000UL +#define HDMI_2250MHZ_BIT_CLK_HZ 2250000000UL +#define HDMI_2000MHZ_BIT_CLK_HZ 2000000000UL +#define HDMI_1700MHZ_BIT_CLK_HZ 1700000000UL +#define HDMI_1200MHZ_BIT_CLK_HZ 1200000000UL +#define HDMI_1334MHZ_BIT_CLK_HZ 1334000000UL +#define HDMI_1000MHZ_BIT_CLK_HZ 1000000000UL +#define HDMI_850MHZ_BIT_CLK_HZ 850000000 +#define HDMI_667MHZ_BIT_CLK_HZ 667000000 +#define HDMI_600MHZ_BIT_CLK_HZ 600000000 +#define HDMI_500MHZ_BIT_CLK_HZ 500000000 +#define HDMI_450MHZ_BIT_CLK_HZ 450000000 +#define HDMI_334MHZ_BIT_CLK_HZ 334000000 +#define HDMI_300MHZ_BIT_CLK_HZ 300000000 +#define HDMI_282MHZ_BIT_CLK_HZ 282000000 +#define HDMI_250MHZ_BIT_CLK_HZ 250000000 +#define HDMI_KHZ_TO_HZ 1000 + +/* PLL REGISTERS */ +#define QSERDES_COM_ATB_SEL1 (0x000) +#define QSERDES_COM_ATB_SEL2 (0x004) +#define QSERDES_COM_FREQ_UPDATE (0x008) +#define QSERDES_COM_BG_TIMER (0x00C) +#define QSERDES_COM_SSC_EN_CENTER (0x010) +#define QSERDES_COM_SSC_ADJ_PER1 (0x014) +#define QSERDES_COM_SSC_ADJ_PER2 (0x018) +#define QSERDES_COM_SSC_PER1 (0x01C) +#define QSERDES_COM_SSC_PER2 (0x020) +#define QSERDES_COM_SSC_STEP_SIZE1 (0x024) +#define QSERDES_COM_SSC_STEP_SIZE2 (0x028) +#define QSERDES_COM_POST_DIV (0x02C) +#define QSERDES_COM_POST_DIV_MUX (0x030) +#define QSERDES_COM_BIAS_EN_CLKBUFLR_EN (0x034) +#define QSERDES_COM_CLK_ENABLE1 (0x038) +#define QSERDES_COM_SYS_CLK_CTRL (0x03C) +#define QSERDES_COM_SYSCLK_BUF_ENABLE (0x040) +#define QSERDES_COM_PLL_EN (0x044) +#define QSERDES_COM_PLL_IVCO (0x048) +#define QSERDES_COM_LOCK_CMP1_MODE0 (0x04C) +#define QSERDES_COM_LOCK_CMP2_MODE0 (0x050) +#define QSERDES_COM_LOCK_CMP3_MODE0 (0x054) +#define QSERDES_COM_LOCK_CMP1_MODE1 (0x058) +#define QSERDES_COM_LOCK_CMP2_MODE1 (0x05C) +#define QSERDES_COM_LOCK_CMP3_MODE1 (0x060) +#define QSERDES_COM_LOCK_CMP1_MODE2 (0x064) +#define QSERDES_COM_CMN_RSVD0 (0x064) +#define QSERDES_COM_LOCK_CMP2_MODE2 (0x068) +#define QSERDES_COM_EP_CLOCK_DETECT_CTRL (0x068) +#define QSERDES_COM_LOCK_CMP3_MODE2 (0x06C) +#define QSERDES_COM_SYSCLK_DET_COMP_STATUS (0x06C) +#define QSERDES_COM_BG_TRIM (0x070) +#define QSERDES_COM_CLK_EP_DIV (0x074) +#define QSERDES_COM_CP_CTRL_MODE0 (0x078) +#define QSERDES_COM_CP_CTRL_MODE1 (0x07C) +#define QSERDES_COM_CP_CTRL_MODE2 (0x080) +#define QSERDES_COM_CMN_RSVD1 (0x080) +#define QSERDES_COM_PLL_RCTRL_MODE0 (0x084) +#define QSERDES_COM_PLL_RCTRL_MODE1 (0x088) +#define QSERDES_COM_PLL_RCTRL_MODE2 (0x08C) +#define QSERDES_COM_CMN_RSVD2 (0x08C) +#define QSERDES_COM_PLL_CCTRL_MODE0 (0x090) +#define QSERDES_COM_PLL_CCTRL_MODE1 (0x094) +#define QSERDES_COM_PLL_CCTRL_MODE2 (0x098) +#define QSERDES_COM_CMN_RSVD3 (0x098) +#define QSERDES_COM_PLL_CNTRL (0x09C) +#define QSERDES_COM_PHASE_SEL_CTRL (0x0A0) +#define QSERDES_COM_PHASE_SEL_DC (0x0A4) +#define QSERDES_COM_CORE_CLK_IN_SYNC_SEL (0x0A8) +#define QSERDES_COM_BIAS_EN_CTRL_BY_PSM (0x0A8) +#define QSERDES_COM_SYSCLK_EN_SEL (0x0AC) +#define QSERDES_COM_CML_SYSCLK_SEL (0x0B0) +#define QSERDES_COM_RESETSM_CNTRL (0x0B4) +#define QSERDES_COM_RESETSM_CNTRL2 (0x0B8) +#define QSERDES_COM_RESTRIM_CTRL (0x0BC) +#define QSERDES_COM_RESTRIM_CTRL2 (0x0C0) +#define QSERDES_COM_RESCODE_DIV_NUM (0x0C4) +#define QSERDES_COM_LOCK_CMP_EN (0x0C8) +#define QSERDES_COM_LOCK_CMP_CFG (0x0CC) +#define QSERDES_COM_DEC_START_MODE0 (0x0D0) +#define QSERDES_COM_DEC_START_MODE1 (0x0D4) +#define QSERDES_COM_DEC_START_MODE2 (0x0D8) +#define QSERDES_COM_VCOCAL_DEADMAN_CTRL (0x0D8) +#define QSERDES_COM_DIV_FRAC_START1_MODE0 (0x0DC) +#define QSERDES_COM_DIV_FRAC_START2_MODE0 (0x0E0) +#define QSERDES_COM_DIV_FRAC_START3_MODE0 (0x0E4) +#define QSERDES_COM_DIV_FRAC_START1_MODE1 (0x0E8) +#define QSERDES_COM_DIV_FRAC_START2_MODE1 (0x0EC) +#define QSERDES_COM_DIV_FRAC_START3_MODE1 (0x0F0) +#define QSERDES_COM_DIV_FRAC_START1_MODE2 (0x0F4) +#define QSERDES_COM_VCO_TUNE_MINVAL1 (0x0F4) +#define QSERDES_COM_DIV_FRAC_START2_MODE2 (0x0F8) +#define QSERDES_COM_VCO_TUNE_MINVAL2 (0x0F8) +#define QSERDES_COM_DIV_FRAC_START3_MODE2 (0x0FC) +#define QSERDES_COM_CMN_RSVD4 (0x0FC) +#define QSERDES_COM_INTEGLOOP_INITVAL (0x100) +#define QSERDES_COM_INTEGLOOP_EN (0x104) +#define QSERDES_COM_INTEGLOOP_GAIN0_MODE0 (0x108) +#define QSERDES_COM_INTEGLOOP_GAIN1_MODE0 (0x10C) +#define QSERDES_COM_INTEGLOOP_GAIN0_MODE1 (0x110) +#define QSERDES_COM_INTEGLOOP_GAIN1_MODE1 (0x114) +#define QSERDES_COM_INTEGLOOP_GAIN0_MODE2 (0x118) +#define QSERDES_COM_VCO_TUNE_MAXVAL1 (0x118) +#define QSERDES_COM_INTEGLOOP_GAIN1_MODE2 (0x11C) +#define QSERDES_COM_VCO_TUNE_MAXVAL2 (0x11C) +#define QSERDES_COM_RES_TRIM_CONTROL2 (0x120) +#define QSERDES_COM_VCO_TUNE_CTRL (0x124) +#define QSERDES_COM_VCO_TUNE_MAP (0x128) +#define QSERDES_COM_VCO_TUNE1_MODE0 (0x12C) +#define QSERDES_COM_VCO_TUNE2_MODE0 (0x130) +#define QSERDES_COM_VCO_TUNE1_MODE1 (0x134) +#define QSERDES_COM_VCO_TUNE2_MODE1 (0x138) +#define QSERDES_COM_VCO_TUNE1_MODE2 (0x13C) +#define QSERDES_COM_VCO_TUNE_INITVAL1 (0x13C) +#define QSERDES_COM_VCO_TUNE2_MODE2 (0x140) +#define QSERDES_COM_VCO_TUNE_INITVAL2 (0x140) +#define QSERDES_COM_VCO_TUNE_TIMER1 (0x144) +#define QSERDES_COM_VCO_TUNE_TIMER2 (0x148) +#define QSERDES_COM_SAR (0x14C) +#define QSERDES_COM_SAR_CLK (0x150) +#define QSERDES_COM_SAR_CODE_OUT_STATUS (0x154) +#define QSERDES_COM_SAR_CODE_READY_STATUS (0x158) +#define QSERDES_COM_CMN_STATUS (0x15C) +#define QSERDES_COM_RESET_SM_STATUS (0x160) +#define QSERDES_COM_RESTRIM_CODE_STATUS (0x164) +#define QSERDES_COM_PLLCAL_CODE1_STATUS (0x168) +#define QSERDES_COM_PLLCAL_CODE2_STATUS (0x16C) +#define QSERDES_COM_BG_CTRL (0x170) +#define QSERDES_COM_CLK_SELECT (0x174) +#define QSERDES_COM_HSCLK_SEL (0x178) +#define QSERDES_COM_INTEGLOOP_BINCODE_STATUS (0x17C) +#define QSERDES_COM_PLL_ANALOG (0x180) +#define QSERDES_COM_CORECLK_DIV (0x184) +#define QSERDES_COM_SW_RESET (0x188) +#define QSERDES_COM_CORE_CLK_EN (0x18C) +#define QSERDES_COM_C_READY_STATUS (0x190) +#define QSERDES_COM_CMN_CONFIG (0x194) +#define QSERDES_COM_CMN_RATE_OVERRIDE (0x198) +#define QSERDES_COM_SVS_MODE_CLK_SEL (0x19C) +#define QSERDES_COM_DEBUG_BUS0 (0x1A0) +#define QSERDES_COM_DEBUG_BUS1 (0x1A4) +#define QSERDES_COM_DEBUG_BUS2 (0x1A8) +#define QSERDES_COM_DEBUG_BUS3 (0x1AC) +#define QSERDES_COM_DEBUG_BUS_SEL (0x1B0) +#define QSERDES_COM_CMN_MISC1 (0x1B4) +#define QSERDES_COM_CMN_MISC2 (0x1B8) +#define QSERDES_COM_CORECLK_DIV_MODE1 (0x1BC) +#define QSERDES_COM_CORECLK_DIV_MODE2 (0x1C0) +#define QSERDES_COM_CMN_RSVD5 (0x1C0) + +/* Tx Channel base addresses */ +#define HDMI_TX_L0_BASE_OFFSET (0x400) +#define HDMI_TX_L1_BASE_OFFSET (0x600) +#define HDMI_TX_L2_BASE_OFFSET (0x800) +#define HDMI_TX_L3_BASE_OFFSET (0xA00) + +/* Tx Channel PHY registers */ +#define QSERDES_TX_L0_BIST_MODE_LANENO (0x000) +#define QSERDES_TX_L0_BIST_INVERT (0x004) +#define QSERDES_TX_L0_CLKBUF_ENABLE (0x008) +#define QSERDES_TX_L0_CMN_CONTROL_ONE (0x00C) +#define QSERDES_TX_L0_CMN_CONTROL_TWO (0x010) +#define QSERDES_TX_L0_CMN_CONTROL_THREE (0x014) +#define QSERDES_TX_L0_TX_EMP_POST1_LVL (0x018) +#define QSERDES_TX_L0_TX_POST2_EMPH (0x01C) +#define QSERDES_TX_L0_TX_BOOST_LVL_UP_DN (0x020) +#define QSERDES_TX_L0_HP_PD_ENABLES (0x024) +#define QSERDES_TX_L0_TX_IDLE_LVL_LARGE_AMP (0x028) +#define QSERDES_TX_L0_TX_DRV_LVL (0x02C) +#define QSERDES_TX_L0_TX_DRV_LVL_OFFSET (0x030) +#define QSERDES_TX_L0_RESET_TSYNC_EN (0x034) +#define QSERDES_TX_L0_PRE_STALL_LDO_BOOST_EN (0x038) +#define QSERDES_TX_L0_TX_BAND (0x03C) +#define QSERDES_TX_L0_SLEW_CNTL (0x040) +#define QSERDES_TX_L0_INTERFACE_SELECT (0x044) +#define QSERDES_TX_L0_LPB_EN (0x048) +#define QSERDES_TX_L0_RES_CODE_LANE_TX (0x04C) +#define QSERDES_TX_L0_RES_CODE_LANE_RX (0x050) +#define QSERDES_TX_L0_RES_CODE_LANE_OFFSET (0x054) +#define QSERDES_TX_L0_PERL_LENGTH1 (0x058) +#define QSERDES_TX_L0_PERL_LENGTH2 (0x05C) +#define QSERDES_TX_L0_SERDES_BYP_EN_OUT (0x060) +#define QSERDES_TX_L0_DEBUG_BUS_SEL (0x064) +#define QSERDES_TX_L0_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN (0x068) +#define QSERDES_TX_L0_TX_POL_INV (0x06C) +#define QSERDES_TX_L0_PARRATE_REC_DETECT_IDLE_EN (0x070) +#define QSERDES_TX_L0_BIST_PATTERN1 (0x074) +#define QSERDES_TX_L0_BIST_PATTERN2 (0x078) +#define QSERDES_TX_L0_BIST_PATTERN3 (0x07C) +#define QSERDES_TX_L0_BIST_PATTERN4 (0x080) +#define QSERDES_TX_L0_BIST_PATTERN5 (0x084) +#define QSERDES_TX_L0_BIST_PATTERN6 (0x088) +#define QSERDES_TX_L0_BIST_PATTERN7 (0x08C) +#define QSERDES_TX_L0_BIST_PATTERN8 (0x090) +#define QSERDES_TX_L0_LANE_MODE (0x094) +#define QSERDES_TX_L0_IDAC_CAL_LANE_MODE (0x098) +#define QSERDES_TX_L0_IDAC_CAL_LANE_MODE_CONFIGURATION (0x09C) +#define QSERDES_TX_L0_ATB_SEL1 (0x0A0) +#define QSERDES_TX_L0_ATB_SEL2 (0x0A4) +#define QSERDES_TX_L0_RCV_DETECT_LVL (0x0A8) +#define QSERDES_TX_L0_RCV_DETECT_LVL_2 (0x0AC) +#define QSERDES_TX_L0_PRBS_SEED1 (0x0B0) +#define QSERDES_TX_L0_PRBS_SEED2 (0x0B4) +#define QSERDES_TX_L0_PRBS_SEED3 (0x0B8) +#define QSERDES_TX_L0_PRBS_SEED4 (0x0BC) +#define QSERDES_TX_L0_RESET_GEN (0x0C0) +#define QSERDES_TX_L0_RESET_GEN_MUXES (0x0C4) +#define QSERDES_TX_L0_TRAN_DRVR_EMP_EN (0x0C8) +#define QSERDES_TX_L0_TX_INTERFACE_MODE (0x0CC) +#define QSERDES_TX_L0_PWM_CTRL (0x0D0) +#define QSERDES_TX_L0_PWM_ENCODED_OR_DATA (0x0D4) +#define QSERDES_TX_L0_PWM_GEAR_1_DIVIDER_BAND2 (0x0D8) +#define QSERDES_TX_L0_PWM_GEAR_2_DIVIDER_BAND2 (0x0DC) +#define QSERDES_TX_L0_PWM_GEAR_3_DIVIDER_BAND2 (0x0E0) +#define QSERDES_TX_L0_PWM_GEAR_4_DIVIDER_BAND2 (0x0E4) +#define QSERDES_TX_L0_PWM_GEAR_1_DIVIDER_BAND0_1 (0x0E8) +#define QSERDES_TX_L0_PWM_GEAR_2_DIVIDER_BAND0_1 (0x0EC) +#define QSERDES_TX_L0_PWM_GEAR_3_DIVIDER_BAND0_1 (0x0F0) +#define QSERDES_TX_L0_PWM_GEAR_4_DIVIDER_BAND0_1 (0x0F4) +#define QSERDES_TX_L0_VMODE_CTRL1 (0x0F8) +#define QSERDES_TX_L0_VMODE_CTRL2 (0x0FC) +#define QSERDES_TX_L0_TX_ALOG_INTF_OBSV_CNTL (0x100) +#define QSERDES_TX_L0_BIST_STATUS (0x104) +#define QSERDES_TX_L0_BIST_ERROR_COUNT1 (0x108) +#define QSERDES_TX_L0_BIST_ERROR_COUNT2 (0x10C) +#define QSERDES_TX_L0_TX_ALOG_INTF_OBSV (0x110) + +/* HDMI PHY REGISTERS */ +#define HDMI_PHY_BASE_OFFSET (0xC00) + +#define HDMI_PHY_CFG (0x00) +#define HDMI_PHY_PD_CTL (0x04) +#define HDMI_PHY_MODE (0x08) +#define HDMI_PHY_MISR_CLEAR (0x0C) +#define HDMI_PHY_TX0_TX1_BIST_CFG0 (0x10) +#define HDMI_PHY_TX0_TX1_BIST_CFG1 (0x14) +#define HDMI_PHY_TX0_TX1_PRBS_SEED_BYTE0 (0x18) +#define HDMI_PHY_TX0_TX1_PRBS_SEED_BYTE1 (0x1C) +#define HDMI_PHY_TX0_TX1_BIST_PATTERN0 (0x20) +#define HDMI_PHY_TX0_TX1_BIST_PATTERN1 (0x24) +#define HDMI_PHY_TX2_TX3_BIST_CFG0 (0x28) +#define HDMI_PHY_TX2_TX3_BIST_CFG1 (0x2C) +#define HDMI_PHY_TX2_TX3_PRBS_SEED_BYTE0 (0x30) +#define HDMI_PHY_TX2_TX3_PRBS_SEED_BYTE1 (0x34) +#define HDMI_PHY_TX2_TX3_BIST_PATTERN0 (0x38) +#define HDMI_PHY_TX2_TX3_BIST_PATTERN1 (0x3C) +#define HDMI_PHY_DEBUG_BUS_SEL (0x40) +#define HDMI_PHY_TXCAL_CFG0 (0x44) +#define HDMI_PHY_TXCAL_CFG1 (0x48) +#define HDMI_PHY_TX0_TX1_LANE_CTL (0x4C) +#define HDMI_PHY_TX2_TX3_LANE_CTL (0x50) +#define HDMI_PHY_LANE_BIST_CONFIG (0x54) +#define HDMI_PHY_CLOCK (0x58) +#define HDMI_PHY_MISC1 (0x5C) +#define HDMI_PHY_MISC2 (0x60) +#define HDMI_PHY_TX0_TX1_BIST_STATUS0 (0x64) +#define HDMI_PHY_TX0_TX1_BIST_STATUS1 (0x68) +#define HDMI_PHY_TX0_TX1_BIST_STATUS2 (0x6C) +#define HDMI_PHY_TX2_TX3_BIST_STATUS0 (0x70) +#define HDMI_PHY_TX2_TX3_BIST_STATUS1 (0x74) +#define HDMI_PHY_TX2_TX3_BIST_STATUS2 (0x78) +#define HDMI_PHY_PRE_MISR_STATUS0 (0x7C) +#define HDMI_PHY_PRE_MISR_STATUS1 (0x80) +#define HDMI_PHY_PRE_MISR_STATUS2 (0x84) +#define HDMI_PHY_PRE_MISR_STATUS3 (0x88) +#define HDMI_PHY_POST_MISR_STATUS0 (0x8C) +#define HDMI_PHY_POST_MISR_STATUS1 (0x90) +#define HDMI_PHY_POST_MISR_STATUS2 (0x94) +#define HDMI_PHY_POST_MISR_STATUS3 (0x98) +#define HDMI_PHY_STATUS (0x9C) +#define HDMI_PHY_MISC3_STATUS (0xA0) +#define HDMI_PHY_MISC4_STATUS (0xA4) +#define HDMI_PHY_DEBUG_BUS0 (0xA8) +#define HDMI_PHY_DEBUG_BUS1 (0xAC) +#define HDMI_PHY_DEBUG_BUS2 (0xB0) +#define HDMI_PHY_DEBUG_BUS3 (0xB4) +#define HDMI_PHY_PHY_REVISION_ID0 (0xB8) +#define HDMI_PHY_PHY_REVISION_ID1 (0xBC) +#define HDMI_PHY_PHY_REVISION_ID2 (0xC0) +#define HDMI_PHY_PHY_REVISION_ID3 (0xC4) + +#define HDMI_PLL_POLL_MAX_READS 100 +#define HDMI_PLL_POLL_TIMEOUT_US 1500 + +enum hdmi_pll_freqs { + HDMI_PCLK_25200_KHZ, + HDMI_PCLK_27027_KHZ, + HDMI_PCLK_27000_KHZ, + HDMI_PCLK_74250_KHZ, + HDMI_PCLK_148500_KHZ, + HDMI_PCLK_154000_KHZ, + HDMI_PCLK_268500_KHZ, + HDMI_PCLK_297000_KHZ, + HDMI_PCLK_594000_KHZ, + HDMI_PCLK_MAX +}; + +struct hdmi_8996_phy_pll_reg_cfg { + u32 tx_l0_lane_mode; + u32 tx_l2_lane_mode; + u32 tx_l0_tx_band; + u32 tx_l1_tx_band; + u32 tx_l2_tx_band; + u32 tx_l3_tx_band; + u32 com_svs_mode_clk_sel; + u32 com_hsclk_sel; + u32 com_pll_cctrl_mode0; + u32 com_pll_rctrl_mode0; + u32 com_cp_ctrl_mode0; + u32 com_dec_start_mode0; + u32 com_div_frac_start1_mode0; + u32 com_div_frac_start2_mode0; + u32 com_div_frac_start3_mode0; + u32 com_integloop_gain0_mode0; + u32 com_integloop_gain1_mode0; + u32 com_lock_cmp_en; + u32 com_lock_cmp1_mode0; + u32 com_lock_cmp2_mode0; + u32 com_lock_cmp3_mode0; + u32 com_core_clk_en; + u32 com_coreclk_div; + u32 com_restrim_ctrl; + u32 com_vco_tune_ctrl; + + u32 tx_l0_tx_drv_lvl; + u32 tx_l0_tx_emp_post1_lvl; + u32 tx_l1_tx_drv_lvl; + u32 tx_l1_tx_emp_post1_lvl; + u32 tx_l2_tx_drv_lvl; + u32 tx_l2_tx_emp_post1_lvl; + u32 tx_l3_tx_drv_lvl; + u32 tx_l3_tx_emp_post1_lvl; + u32 tx_l0_vmode_ctrl1; + u32 tx_l0_vmode_ctrl2; + u32 tx_l1_vmode_ctrl1; + u32 tx_l1_vmode_ctrl2; + u32 tx_l2_vmode_ctrl1; + u32 tx_l2_vmode_ctrl2; + u32 tx_l3_vmode_ctrl1; + u32 tx_l3_vmode_ctrl2; + u32 tx_l0_res_code_lane_tx; + u32 tx_l1_res_code_lane_tx; + u32 tx_l2_res_code_lane_tx; + u32 tx_l3_res_code_lane_tx; + + u32 phy_mode; +}; + +struct hdmi_8996_v3_post_divider { + u64 vco_freq; + u64 hsclk_divsel; + u64 vco_ratio; + u64 tx_band_sel; + u64 half_rate_mode; +}; + +static inline struct hdmi_pll_vco_clk *to_hdmi_8996_vco_clk(struct clk *clk) +{ + return container_of(clk, struct hdmi_pll_vco_clk, c); +} + +static inline u64 hdmi_8996_v1_get_post_div_lt_2g(u64 bclk) +{ + if (bclk >= HDMI_2400MHZ_BIT_CLK_HZ) + return 2; + else if (bclk >= HDMI_1700MHZ_BIT_CLK_HZ) + return 3; + else if (bclk >= HDMI_1200MHZ_BIT_CLK_HZ) + return 4; + else if (bclk >= HDMI_850MHZ_BIT_CLK_HZ) + return 3; + else if (bclk >= HDMI_600MHZ_BIT_CLK_HZ) + return 4; + else if (bclk >= HDMI_450MHZ_BIT_CLK_HZ) + return 3; + else if (bclk >= HDMI_300MHZ_BIT_CLK_HZ) + return 4; + + return HDMI_64B_ERR_VAL; +} + +static inline u64 hdmi_8996_v2_get_post_div_lt_2g(u64 bclk, u64 vco_range) +{ + u64 hdmi_8ghz = vco_range; + u64 tmp_calc; + + hdmi_8ghz <<= 2; + tmp_calc = hdmi_8ghz; + do_div(tmp_calc, 6U); + + if (bclk >= vco_range) + return 2; + else if (bclk >= tmp_calc) + return 3; + else if (bclk >= vco_range >> 1) + return 4; + + tmp_calc = hdmi_8ghz; + do_div(tmp_calc, 12U); + if (bclk >= tmp_calc) + return 3; + else if (bclk >= vco_range >> 2) + return 4; + + tmp_calc = hdmi_8ghz; + do_div(tmp_calc, 24U); + if (bclk >= tmp_calc) + return 3; + else if (bclk >= vco_range >> 3) + return 4; + + return HDMI_64B_ERR_VAL; +} + +static inline u64 hdmi_8996_v2_get_post_div_gt_2g(u64 hsclk) +{ + if (hsclk >= 0 && hsclk <= 3) + return hsclk + 1; + + return HDMI_64B_ERR_VAL; +} + +static inline u64 hdmi_8996_get_coreclk_div_lt_2g(u64 bclk) +{ + if (bclk >= HDMI_1334MHZ_BIT_CLK_HZ) + return 1; + else if (bclk >= HDMI_1000MHZ_BIT_CLK_HZ) + return 1; + else if (bclk >= HDMI_667MHZ_BIT_CLK_HZ) + return 2; + else if (bclk >= HDMI_500MHZ_BIT_CLK_HZ) + return 2; + else if (bclk >= HDMI_334MHZ_BIT_CLK_HZ) + return 3; + else if (bclk >= HDMI_250MHZ_BIT_CLK_HZ) + return 3; + + return HDMI_64B_ERR_VAL; +} + +static inline u64 hdmi_8996_get_coreclk_div_ratio(u64 clks_pll_divsel, + u64 coreclk_div) +{ + if (clks_pll_divsel == 0) + return coreclk_div*2; + else if (clks_pll_divsel == 1) + return coreclk_div*4; + + return HDMI_64B_ERR_VAL; +} + +static inline u64 hdmi_8996_v1_get_tx_band(u64 bclk) +{ + if (bclk >= 2400000000UL) + return 0; + if (bclk >= 1200000000UL) + return 1; + if (bclk >= 600000000UL) + return 2; + if (bclk >= 300000000UL) + return 3; + + return HDMI_64B_ERR_VAL; +} + +static inline u64 hdmi_8996_v2_get_tx_band(u64 bclk, u64 vco_range) +{ + if (bclk >= vco_range) + return 0; + else if (bclk >= vco_range >> 1) + return 1; + else if (bclk >= vco_range >> 2) + return 2; + else if (bclk >= vco_range >> 3) + return 3; + + return HDMI_64B_ERR_VAL; +} + +static inline u64 hdmi_8996_v1_get_hsclk(u64 fdata) +{ + if (fdata >= 9600000000UL) + return 0; + else if (fdata >= 4800000000UL) + return 1; + else if (fdata >= 3200000000UL) + return 2; + else if (fdata >= 2400000000UL) + return 3; + + return HDMI_64B_ERR_VAL; +} + +static inline u64 hdmi_8996_v2_get_hsclk(u64 fdata, u64 vco_range) +{ + u64 tmp_calc = vco_range; + tmp_calc <<= 2; + do_div(tmp_calc, 3U); + if (fdata >= (vco_range << 2)) + return 0; + else if (fdata >= (vco_range << 1)) + return 1; + else if (fdata >= tmp_calc) + return 2; + else if (fdata >= vco_range) + return 3; + + return HDMI_64B_ERR_VAL; + +} + +static inline u64 hdmi_8996_v2_get_vco_freq(u64 bclk, u64 vco_range) +{ + u64 tx_band_div_ratio = 1U << hdmi_8996_v2_get_tx_band(bclk, vco_range); + u64 pll_post_div_ratio; + + if (bclk >= vco_range) { + u64 hsclk = hdmi_8996_v2_get_hsclk(bclk, vco_range); + pll_post_div_ratio = hdmi_8996_v2_get_post_div_gt_2g(hsclk); + } else { + pll_post_div_ratio = hdmi_8996_v2_get_post_div_lt_2g(bclk, + vco_range); + } + + return bclk * (pll_post_div_ratio * tx_band_div_ratio); +} + +static inline u64 hdmi_8996_v2_get_fdata(u64 bclk, u64 vco_range) +{ + if (bclk >= vco_range) { + return bclk; + } else { + u64 tmp_calc = hdmi_8996_v2_get_vco_freq(bclk, vco_range); + u64 pll_post_div_ratio_lt_2g = hdmi_8996_v2_get_post_div_lt_2g( + bclk, vco_range); + if (pll_post_div_ratio_lt_2g == HDMI_64B_ERR_VAL) + return HDMI_64B_ERR_VAL; + + do_div(tmp_calc, pll_post_div_ratio_lt_2g); + return tmp_calc; + } +} + +static inline u64 hdmi_8996_get_cpctrl(u64 frac_start, bool gen_ssc) +{ + if ((frac_start != 0) || + (gen_ssc == true)) + /* + * This should be ROUND(11/(19.2/20))). + * Since ref clock does not change, hardcoding to 11 + */ + return 0xB; + + return 0x23; +} + +static inline u64 hdmi_8996_get_rctrl(u64 frac_start, bool gen_ssc) +{ + if ((frac_start != 0) || (gen_ssc == true)) + return 0x16; + + return 0x10; +} + +static inline u64 hdmi_8996_get_cctrl(u64 frac_start, bool gen_ssc) +{ + if ((frac_start != 0) || (gen_ssc == true)) + return 0x28; + + return 0x1; +} + +static inline u64 hdmi_8996_get_integloop_gain(u64 frac_start, bool gen_ssc) +{ + if ((frac_start != 0) || (gen_ssc == true)) + return 0x80; + + return 0xC4; +} + +static inline u64 hdmi_8996_v3_get_integloop_gain(u64 frac_start, u64 bclk, + bool gen_ssc) +{ + u64 digclk_divsel = bclk >= HDMI_DIG_FREQ_BIT_CLK_THRESHOLD ? 1 : 2; + u64 base = ((frac_start != 0) || (gen_ssc == true)) ? 0x40 : 0xC4; + + base <<= digclk_divsel; + + return (base <= 2046 ? base : 0x7FE); +} + +static inline u64 hdmi_8996_get_vco_tune(u64 fdata, u64 div) +{ + u64 vco_tune; + + vco_tune = fdata * div; + do_div(vco_tune, 1000000); + vco_tune = 13000 - vco_tune - 256; + do_div(vco_tune, 5); + + return vco_tune; +} + +static inline u64 hdmi_8996_get_pll_cmp(u64 pll_cmp_cnt, u64 core_clk) +{ + u64 pll_cmp; + u64 rem; + pll_cmp = pll_cmp_cnt * core_clk; + rem = do_div(pll_cmp, HDMI_REF_CLOCK); + if (rem > (HDMI_REF_CLOCK >> 1)) + pll_cmp++; + pll_cmp -= 1; + + return pll_cmp; +} + +static inline u64 hdmi_8996_v3_get_pll_cmp(u64 pll_cmp_cnt, u64 fdata) +{ + u64 dividend = pll_cmp_cnt * fdata; + u64 divisor = HDMI_REF_CLOCK * 10; + u64 rem; + + rem = do_div(dividend, divisor); + if (rem > (divisor >> 1)) + dividend++; + + return dividend - 1; +} + +static int hdmi_8996_v3_get_post_div(struct hdmi_8996_v3_post_divider *pd, + u64 bclk) +{ + u32 ratio[] = {2, 3, 4, 5, 6, 9, 10, 12, 14, 15, 20, 21, 25, 28, 35}; + u32 tx_band_sel[] = {0, 1, 2, 3}; + u64 vco_freq[60]; + u64 vco, vco_optimal, half_rate_mode = 0; + int vco_optimal_index, vco_freq_index; + int i, j, k, x; + + for (i = 0; i <= 1; i++) { + vco_optimal = HDMI_VCO_MAX_FREQ; + vco_optimal_index = -1; + vco_freq_index = 0; + for (j = 0; j < 15; j++) { + for (k = 0; k < 4; k++) { + u64 ratio_mult = ratio[j] << tx_band_sel[k]; + + vco = bclk >> half_rate_mode; + vco *= ratio_mult; + vco_freq[vco_freq_index++] = vco; + } + } + + for (x = 0; x < 60; x++) { + u64 vco_tmp = vco_freq[x]; + + if ((vco_tmp >= HDMI_VCO_MIN_FREQ) && + (vco_tmp <= vco_optimal)) { + vco_optimal = vco_tmp; + vco_optimal_index = x; + } + } + + if (vco_optimal_index == -1) { + if (!half_rate_mode) + half_rate_mode++; + else + return -EINVAL; + } else { + pd->vco_freq = vco_optimal; + pd->tx_band_sel = tx_band_sel[vco_optimal_index % 4]; + pd->vco_ratio = ratio[vco_optimal_index / 4]; + break; + } + } + + switch (pd->vco_ratio) { + case 2: + pd->hsclk_divsel = 0; + break; + case 3: + pd->hsclk_divsel = 4; + break; + case 4: + pd->hsclk_divsel = 8; + break; + case 5: + pd->hsclk_divsel = 12; + break; + case 6: + pd->hsclk_divsel = 1; + break; + case 9: + pd->hsclk_divsel = 5; + break; + case 10: + pd->hsclk_divsel = 2; + break; + case 12: + pd->hsclk_divsel = 9; + break; + case 14: + pd->hsclk_divsel = 3; + break; + case 15: + pd->hsclk_divsel = 13; + break; + case 20: + pd->hsclk_divsel = 10; + break; + case 21: + pd->hsclk_divsel = 7; + break; + case 25: + pd->hsclk_divsel = 14; + break; + case 28: + pd->hsclk_divsel = 11; + break; + case 35: + pd->hsclk_divsel = 15; + break; + }; + + return 0; +} + +static int hdmi_8996_v1_calculate(u32 pix_clk, + struct hdmi_8996_phy_pll_reg_cfg *cfg) +{ + int rc = -EINVAL; + u64 fdata, clk_divtx, tmds_clk; + u64 bclk; + u64 post_div_gt_2g; + u64 post_div_lt_2g; + u64 coreclk_div1_lt_2g; + u64 core_clk_div_ratio; + u64 core_clk; + u64 pll_cmp; + u64 tx_band; + u64 tx_band_div_ratio; + u64 hsclk; + u64 dec_start; + u64 frac_start; + u64 pll_divisor = 4 * HDMI_REF_CLOCK; + u64 cpctrl; + u64 rctrl; + u64 cctrl; + u64 integloop_gain; + u64 vco_tune; + u64 vco_freq; + u64 rem; + + /* FDATA, CLK_DIVTX, PIXEL_CLK, TMDS_CLK */ + bclk = ((u64)pix_clk) * HDMI_BIT_CLK_TO_PIX_CLK_RATIO; + + if (bclk > HDMI_HIGH_FREQ_BIT_CLK_THRESHOLD) + tmds_clk = bclk/4; + else + tmds_clk = bclk; + + post_div_lt_2g = hdmi_8996_v1_get_post_div_lt_2g(bclk); + if (post_div_lt_2g == HDMI_64B_ERR_VAL) + goto fail; + + coreclk_div1_lt_2g = hdmi_8996_get_coreclk_div_lt_2g(bclk); + + core_clk_div_ratio = hdmi_8996_get_coreclk_div_ratio( + HDMI_CLKS_PLL_DIVSEL, HDMI_CORECLK_DIV); + + tx_band = hdmi_8996_v1_get_tx_band(bclk); + if (tx_band == HDMI_64B_ERR_VAL) + goto fail; + + tx_band_div_ratio = 1 << tx_band; + + if (bclk >= HDMI_2400MHZ_BIT_CLK_HZ) { + fdata = bclk; + hsclk = hdmi_8996_v1_get_hsclk(fdata); + if (hsclk == HDMI_64B_ERR_VAL) + goto fail; + + post_div_gt_2g = (hsclk <= 3) ? (hsclk + 1) : HDMI_64B_ERR_VAL; + if (post_div_gt_2g == HDMI_64B_ERR_VAL) + goto fail; + + vco_freq = bclk * (post_div_gt_2g * tx_band_div_ratio); + clk_divtx = vco_freq; + do_div(clk_divtx, post_div_gt_2g); + } else { + vco_freq = bclk * (post_div_lt_2g * tx_band_div_ratio); + fdata = vco_freq; + do_div(fdata, post_div_lt_2g); + hsclk = hdmi_8996_v1_get_hsclk(fdata); + if (hsclk == HDMI_64B_ERR_VAL) + goto fail; + + clk_divtx = vco_freq; + do_div(clk_divtx, post_div_lt_2g); + post_div_gt_2g = (hsclk <= 3) ? (hsclk + 1) : HDMI_64B_ERR_VAL; + if (post_div_gt_2g == HDMI_64B_ERR_VAL) + goto fail; + } + + /* Decimal and fraction values */ + dec_start = fdata * post_div_gt_2g; + do_div(dec_start, pll_divisor); + frac_start = ((pll_divisor - (((dec_start + 1) * pll_divisor) - + (fdata * post_div_gt_2g))) * (1 << 20)); + rem = do_div(frac_start, pll_divisor); + /* Round off frac_start to closest integer */ + if (rem >= (pll_divisor >> 1)) + frac_start++; + + cpctrl = hdmi_8996_get_cpctrl(frac_start, false); + rctrl = hdmi_8996_get_rctrl(frac_start, false); + cctrl = hdmi_8996_get_cctrl(frac_start, false); + integloop_gain = hdmi_8996_get_integloop_gain(frac_start, false); + vco_tune = hdmi_8996_get_vco_tune(fdata, post_div_gt_2g); + + core_clk = clk_divtx; + do_div(core_clk, core_clk_div_ratio); + pll_cmp = hdmi_8996_get_pll_cmp(1024, core_clk); + + /* Debug dump */ + DEV_DBG("%s: VCO freq: %llu\n", __func__, vco_freq); + DEV_DBG("%s: fdata: %llu\n", __func__, fdata); + DEV_DBG("%s: CLK_DIVTX: %llu\n", __func__, clk_divtx); + DEV_DBG("%s: pix_clk: %d\n", __func__, pix_clk); + DEV_DBG("%s: tmds clk: %llu\n", __func__, tmds_clk); + DEV_DBG("%s: HSCLK_SEL: %llu\n", __func__, hsclk); + DEV_DBG("%s: DEC_START: %llu\n", __func__, dec_start); + DEV_DBG("%s: DIV_FRAC_START: %llu\n", __func__, frac_start); + DEV_DBG("%s: PLL_CPCTRL: %llu\n", __func__, cpctrl); + DEV_DBG("%s: PLL_RCTRL: %llu\n", __func__, rctrl); + DEV_DBG("%s: PLL_CCTRL: %llu\n", __func__, cctrl); + DEV_DBG("%s: INTEGLOOP_GAIN: %llu\n", __func__, integloop_gain); + DEV_DBG("%s: VCO_TUNE: %llu\n", __func__, vco_tune); + DEV_DBG("%s: TX_BAND: %llu\n", __func__, tx_band); + DEV_DBG("%s: PLL_CMP: %llu\n", __func__, pll_cmp); + + /* Convert these values to register specific values */ + cfg->tx_l0_lane_mode = 0x3; + cfg->tx_l2_lane_mode = 0x3; + cfg->tx_l0_tx_band = tx_band + 4; + cfg->tx_l1_tx_band = tx_band + 4; + cfg->tx_l2_tx_band = tx_band + 4; + cfg->tx_l3_tx_band = tx_band + 4; + cfg->tx_l0_res_code_lane_tx = 0x33; + cfg->tx_l1_res_code_lane_tx = 0x33; + cfg->tx_l2_res_code_lane_tx = 0x33; + cfg->tx_l3_res_code_lane_tx = 0x33; + cfg->com_restrim_ctrl = 0x0; + cfg->com_vco_tune_ctrl = 0x1C; + + cfg->com_svs_mode_clk_sel = + (bclk >= HDMI_DIG_FREQ_BIT_CLK_THRESHOLD ? 1 : 2); + cfg->com_hsclk_sel = (0x28 | hsclk); + cfg->com_pll_cctrl_mode0 = cctrl; + cfg->com_pll_rctrl_mode0 = rctrl; + cfg->com_cp_ctrl_mode0 = cpctrl; + cfg->com_dec_start_mode0 = dec_start; + cfg->com_div_frac_start1_mode0 = (frac_start & 0xFF); + cfg->com_div_frac_start2_mode0 = ((frac_start & 0xFF00) >> 8); + cfg->com_div_frac_start3_mode0 = ((frac_start & 0xF0000) >> 16); + cfg->com_integloop_gain0_mode0 = (integloop_gain & 0xFF); + cfg->com_integloop_gain1_mode0 = ((integloop_gain & 0xF00) >> 8); + cfg->com_lock_cmp1_mode0 = (pll_cmp & 0xFF); + cfg->com_lock_cmp2_mode0 = ((pll_cmp & 0xFF00) >> 8); + cfg->com_lock_cmp3_mode0 = ((pll_cmp & 0x30000) >> 16); + cfg->com_core_clk_en = (0x6C | (HDMI_CLKS_PLL_DIVSEL << 4)); + cfg->com_coreclk_div = HDMI_CORECLK_DIV; + + if (bclk > HDMI_HIGH_FREQ_BIT_CLK_THRESHOLD) { + cfg->tx_l0_tx_drv_lvl = 0x25; + cfg->tx_l0_tx_emp_post1_lvl = 0x23; + cfg->tx_l1_tx_drv_lvl = 0x25; + cfg->tx_l1_tx_emp_post1_lvl = 0x23; + cfg->tx_l2_tx_drv_lvl = 0x25; + cfg->tx_l2_tx_emp_post1_lvl = 0x23; + cfg->tx_l3_tx_drv_lvl = 0x22; + cfg->tx_l3_tx_emp_post1_lvl = 0x27; + cfg->tx_l0_vmode_ctrl1 = 0x00; + cfg->tx_l0_vmode_ctrl2 = 0x0D; + cfg->tx_l1_vmode_ctrl1 = 0x00; + cfg->tx_l1_vmode_ctrl2 = 0x0D; + cfg->tx_l2_vmode_ctrl1 = 0x00; + cfg->tx_l2_vmode_ctrl2 = 0x0D; + cfg->tx_l3_vmode_ctrl1 = 0x00; + cfg->tx_l3_vmode_ctrl2 = 0x00; + cfg->com_restrim_ctrl = 0x0; + } else if (bclk > HDMI_MID_FREQ_BIT_CLK_THRESHOLD) { + cfg->tx_l0_tx_drv_lvl = 0x25; + cfg->tx_l0_tx_emp_post1_lvl = 0x23; + cfg->tx_l1_tx_drv_lvl = 0x25; + cfg->tx_l1_tx_emp_post1_lvl = 0x23; + cfg->tx_l2_tx_drv_lvl = 0x25; + cfg->tx_l2_tx_emp_post1_lvl = 0x23; + cfg->tx_l3_tx_drv_lvl = 0x25; + cfg->tx_l3_tx_emp_post1_lvl = 0x23; + cfg->tx_l0_vmode_ctrl1 = 0x00; + cfg->tx_l0_vmode_ctrl2 = 0x0D; + cfg->tx_l1_vmode_ctrl1 = 0x00; + cfg->tx_l1_vmode_ctrl2 = 0x0D; + cfg->tx_l2_vmode_ctrl1 = 0x00; + cfg->tx_l2_vmode_ctrl2 = 0x0D; + cfg->tx_l3_vmode_ctrl1 = 0x00; + cfg->tx_l3_vmode_ctrl2 = 0x00; + cfg->com_restrim_ctrl = 0x0; + } else { + cfg->tx_l0_tx_drv_lvl = 0x20; + cfg->tx_l0_tx_emp_post1_lvl = 0x20; + cfg->tx_l1_tx_drv_lvl = 0x20; + cfg->tx_l1_tx_emp_post1_lvl = 0x20; + cfg->tx_l2_tx_drv_lvl = 0x20; + cfg->tx_l2_tx_emp_post1_lvl = 0x20; + cfg->tx_l3_tx_drv_lvl = 0x20; + cfg->tx_l3_tx_emp_post1_lvl = 0x20; + cfg->tx_l0_vmode_ctrl1 = 0x00; + cfg->tx_l0_vmode_ctrl2 = 0x0E; + cfg->tx_l1_vmode_ctrl1 = 0x00; + cfg->tx_l1_vmode_ctrl2 = 0x0E; + cfg->tx_l2_vmode_ctrl1 = 0x00; + cfg->tx_l2_vmode_ctrl2 = 0x0E; + cfg->tx_l3_vmode_ctrl1 = 0x00; + cfg->tx_l3_vmode_ctrl2 = 0x0E; + cfg->com_restrim_ctrl = 0xD8; + } + + cfg->phy_mode = (bclk > HDMI_HIGH_FREQ_BIT_CLK_THRESHOLD) ? 0x10 : 0x0; + DEV_DBG("HDMI 8996 PLL: PLL Settings\n"); + DEV_DBG("PLL PARAM: tx_l0_lane_mode = 0x%x\n", cfg->tx_l0_lane_mode); + DEV_DBG("PLL PARAM: tx_l2_lane_mode = 0x%x\n", cfg->tx_l2_lane_mode); + DEV_DBG("PLL PARAM: tx_l0_tx_band = 0x%x\n", cfg->tx_l0_tx_band); + DEV_DBG("PLL PARAM: tx_l1_tx_band = 0x%x\n", cfg->tx_l1_tx_band); + DEV_DBG("PLL PARAM: tx_l2_tx_band = 0x%x\n", cfg->tx_l2_tx_band); + DEV_DBG("PLL PARAM: tx_l3_tx_band = 0x%x\n", cfg->tx_l3_tx_band); + DEV_DBG("PLL PARAM: com_svs_mode_clk_sel = 0x%x\n", + cfg->com_svs_mode_clk_sel); + DEV_DBG("PLL PARAM: com_hsclk_sel = 0x%x\n", cfg->com_hsclk_sel); + DEV_DBG("PLL PARAM: com_pll_cctrl_mode0 = 0x%x\n", + cfg->com_pll_cctrl_mode0); + DEV_DBG("PLL PARAM: com_pll_rctrl_mode0 = 0x%x\n", + cfg->com_pll_rctrl_mode0); + DEV_DBG("PLL PARAM: com_cp_ctrl_mode0 = 0x%x\n", + cfg->com_cp_ctrl_mode0); + DEV_DBG("PLL PARAM: com_dec_start_mode0 = 0x%x\n", + cfg->com_dec_start_mode0); + DEV_DBG("PLL PARAM: com_div_frac_start1_mode0 = 0x%x\n", + cfg->com_div_frac_start1_mode0); + DEV_DBG("PLL PARAM: com_div_frac_start2_mode0 = 0x%x\n", + cfg->com_div_frac_start2_mode0); + DEV_DBG("PLL PARAM: com_div_frac_start3_mode0 = 0x%x\n", + cfg->com_div_frac_start3_mode0); + DEV_DBG("PLL PARAM: com_integloop_gain0_mode0 = 0x%x\n", + cfg->com_integloop_gain0_mode0); + DEV_DBG("PLL PARAM: com_integloop_gain1_mode0 = 0x%x\n", + cfg->com_integloop_gain1_mode0); + DEV_DBG("PLL PARAM: com_lock_cmp1_mode0 = 0x%x\n", + cfg->com_lock_cmp1_mode0); + DEV_DBG("PLL PARAM: com_lock_cmp2_mode0 = 0x%x\n", + cfg->com_lock_cmp2_mode0); + DEV_DBG("PLL PARAM: com_lock_cmp3_mode0 = 0x%x\n", + cfg->com_lock_cmp3_mode0); + DEV_DBG("PLL PARAM: com_core_clk_en = 0x%x\n", cfg->com_core_clk_en); + DEV_DBG("PLL PARAM: com_coreclk_div = 0x%x\n", cfg->com_coreclk_div); + DEV_DBG("PLL PARAM: com_restrim_ctrl = 0x%x\n", cfg->com_restrim_ctrl); + + DEV_DBG("PLL PARAM: l0_tx_drv_lvl = 0x%x\n", cfg->tx_l0_tx_drv_lvl); + DEV_DBG("PLL PARAM: l0_tx_emp_post1_lvl = 0x%x\n", + cfg->tx_l0_tx_emp_post1_lvl); + DEV_DBG("PLL PARAM: l1_tx_drv_lvl = 0x%x\n", cfg->tx_l1_tx_drv_lvl); + DEV_DBG("PLL PARAM: l1_tx_emp_post1_lvl = 0x%x\n", + cfg->tx_l1_tx_emp_post1_lvl); + DEV_DBG("PLL PARAM: l2_tx_drv_lvl = 0x%x\n", cfg->tx_l2_tx_drv_lvl); + DEV_DBG("PLL PARAM: l2_tx_emp_post1_lvl = 0x%x\n", + cfg->tx_l2_tx_emp_post1_lvl); + DEV_DBG("PLL PARAM: l3_tx_drv_lvl = 0x%x\n", cfg->tx_l3_tx_drv_lvl); + DEV_DBG("PLL PARAM: l3_tx_emp_post1_lvl = 0x%x\n", + cfg->tx_l3_tx_emp_post1_lvl); + + DEV_DBG("PLL PARAM: l0_vmode_ctrl1 = 0x%x\n", cfg->tx_l0_vmode_ctrl1); + DEV_DBG("PLL PARAM: l0_vmode_ctrl2 = 0x%x\n", cfg->tx_l0_vmode_ctrl2); + DEV_DBG("PLL PARAM: l1_vmode_ctrl1 = 0x%x\n", cfg->tx_l1_vmode_ctrl1); + DEV_DBG("PLL PARAM: l1_vmode_ctrl2 = 0x%x\n", cfg->tx_l1_vmode_ctrl2); + DEV_DBG("PLL PARAM: l2_vmode_ctrl1 = 0x%x\n", cfg->tx_l2_vmode_ctrl1); + DEV_DBG("PLL PARAM: l2_vmode_ctrl2 = 0x%x\n", cfg->tx_l2_vmode_ctrl2); + DEV_DBG("PLL PARAM: l3_vmode_ctrl1 = 0x%x\n", cfg->tx_l3_vmode_ctrl1); + DEV_DBG("PLL PARAM: l3_vmode_ctrl2 = 0x%x\n", cfg->tx_l3_vmode_ctrl2); + DEV_DBG("PLL PARAM: tx_l0_res_code_lane_tx = 0x%x\n", + cfg->tx_l0_res_code_lane_tx); + DEV_DBG("PLL PARAM: tx_l1_res_code_lane_tx = 0x%x\n", + cfg->tx_l1_res_code_lane_tx); + DEV_DBG("PLL PARAM: tx_l2_res_code_lane_tx = 0x%x\n", + cfg->tx_l2_res_code_lane_tx); + DEV_DBG("PLL PARAM: tx_l3_res_code_lane_tx = 0x%x\n", + cfg->tx_l3_res_code_lane_tx); + + DEV_DBG("PLL PARAM: phy_mode = 0x%x\n", cfg->phy_mode); + rc = 0; +fail: + return rc; +} + +static int hdmi_8996_v2_calculate(u32 pix_clk, + struct hdmi_8996_phy_pll_reg_cfg *cfg) +{ + int rc = -EINVAL; + u64 fdata, clk_divtx, tmds_clk; + u64 bclk; + u64 post_div; + u64 core_clk_div; + u64 core_clk_div_ratio; + u64 core_clk; + u64 pll_cmp; + u64 tx_band; + u64 tx_band_div_ratio; + u64 hsclk; + u64 dec_start; + u64 frac_start; + u64 pll_divisor = 4 * HDMI_REF_CLOCK; + u64 cpctrl; + u64 rctrl; + u64 cctrl; + u64 integloop_gain; + u64 vco_tune; + u64 vco_freq; + u64 vco_range; + u64 rem; + + /* FDATA, CLK_DIVTX, PIXEL_CLK, TMDS_CLK */ + bclk = ((u64)pix_clk) * HDMI_BIT_CLK_TO_PIX_CLK_RATIO; + + if (bclk > HDMI_HIGH_FREQ_BIT_CLK_THRESHOLD) + tmds_clk = pix_clk >> 2; + else + tmds_clk = pix_clk; + + vco_range = bclk < HDMI_282MHZ_BIT_CLK_HZ ? HDMI_2000MHZ_BIT_CLK_HZ : + HDMI_2250MHZ_BIT_CLK_HZ; + + fdata = hdmi_8996_v2_get_fdata(bclk, vco_range); + if (fdata == HDMI_64B_ERR_VAL) + goto fail; + + hsclk = hdmi_8996_v2_get_hsclk(fdata, vco_range); + if (hsclk == HDMI_64B_ERR_VAL) + goto fail; + + if (bclk >= vco_range) + post_div = hdmi_8996_v2_get_post_div_gt_2g(hsclk); + else + post_div = hdmi_8996_v2_get_post_div_lt_2g(bclk, vco_range); + + if (post_div == HDMI_64B_ERR_VAL) + goto fail; + + core_clk_div = 5; + core_clk_div_ratio = core_clk_div * 2; + + tx_band = hdmi_8996_v2_get_tx_band(bclk, vco_range); + if (tx_band == HDMI_64B_ERR_VAL) + goto fail; + + tx_band_div_ratio = 1 << tx_band; + + vco_freq = hdmi_8996_v2_get_vco_freq(bclk, vco_range); + clk_divtx = vco_freq; + do_div(clk_divtx, post_div); + + /* Decimal and fraction values */ + dec_start = fdata * post_div; + do_div(dec_start, pll_divisor); + frac_start = ((pll_divisor - (((dec_start + 1) * pll_divisor) - + (fdata * post_div))) * (1 << 20)); + rem = do_div(frac_start, pll_divisor); + /* Round off frac_start to closest integer */ + if (rem >= (pll_divisor >> 1)) + frac_start++; + + cpctrl = hdmi_8996_get_cpctrl(frac_start, false); + rctrl = hdmi_8996_get_rctrl(frac_start, false); + cctrl = hdmi_8996_get_cctrl(frac_start, false); + integloop_gain = hdmi_8996_get_integloop_gain(frac_start, false); + vco_tune = hdmi_8996_get_vco_tune(fdata, post_div); + + core_clk = clk_divtx; + do_div(core_clk, core_clk_div_ratio); + pll_cmp = hdmi_8996_get_pll_cmp(1024, core_clk); + + /* Debug dump */ + DEV_DBG("%s: VCO freq: %llu\n", __func__, vco_freq); + DEV_DBG("%s: fdata: %llu\n", __func__, fdata); + DEV_DBG("%s: CLK_DIVTX: %llu\n", __func__, clk_divtx); + DEV_DBG("%s: pix_clk: %d\n", __func__, pix_clk); + DEV_DBG("%s: tmds clk: %llu\n", __func__, tmds_clk); + DEV_DBG("%s: HSCLK_SEL: %llu\n", __func__, hsclk); + DEV_DBG("%s: DEC_START: %llu\n", __func__, dec_start); + DEV_DBG("%s: DIV_FRAC_START: %llu\n", __func__, frac_start); + DEV_DBG("%s: PLL_CPCTRL: %llu\n", __func__, cpctrl); + DEV_DBG("%s: PLL_RCTRL: %llu\n", __func__, rctrl); + DEV_DBG("%s: PLL_CCTRL: %llu\n", __func__, cctrl); + DEV_DBG("%s: INTEGLOOP_GAIN: %llu\n", __func__, integloop_gain); + DEV_DBG("%s: VCO_TUNE: %llu\n", __func__, vco_tune); + DEV_DBG("%s: TX_BAND: %llu\n", __func__, tx_band); + DEV_DBG("%s: PLL_CMP: %llu\n", __func__, pll_cmp); + + /* Convert these values to register specific values */ + cfg->tx_l0_lane_mode = 0x3; + cfg->tx_l2_lane_mode = 0x3; + cfg->tx_l0_tx_band = tx_band + 4; + cfg->tx_l1_tx_band = tx_band + 4; + cfg->tx_l2_tx_band = tx_band + 4; + cfg->tx_l3_tx_band = tx_band + 4; + + if (bclk > HDMI_DIG_FREQ_BIT_CLK_THRESHOLD) + cfg->com_svs_mode_clk_sel = 1; + else + cfg->com_svs_mode_clk_sel = 2; + + cfg->com_hsclk_sel = (0x28 | hsclk); + cfg->com_pll_cctrl_mode0 = cctrl; + cfg->com_pll_rctrl_mode0 = rctrl; + cfg->com_cp_ctrl_mode0 = cpctrl; + cfg->com_dec_start_mode0 = dec_start; + cfg->com_div_frac_start1_mode0 = (frac_start & 0xFF); + cfg->com_div_frac_start2_mode0 = ((frac_start & 0xFF00) >> 8); + cfg->com_div_frac_start3_mode0 = ((frac_start & 0xF0000) >> 16); + cfg->com_integloop_gain0_mode0 = (integloop_gain & 0xFF); + cfg->com_integloop_gain1_mode0 = ((integloop_gain & 0xF00) >> 8); + cfg->com_lock_cmp1_mode0 = (pll_cmp & 0xFF); + cfg->com_lock_cmp2_mode0 = ((pll_cmp & 0xFF00) >> 8); + cfg->com_lock_cmp3_mode0 = ((pll_cmp & 0x30000) >> 16); + cfg->com_core_clk_en = (0x6C | (HDMI_CLKS_PLL_DIVSEL << 4)); + cfg->com_coreclk_div = HDMI_CORECLK_DIV; + cfg->com_vco_tune_ctrl = 0x0; + + if (bclk > HDMI_HIGH_FREQ_BIT_CLK_THRESHOLD) { + cfg->tx_l0_tx_drv_lvl = 0x25; + cfg->tx_l0_tx_emp_post1_lvl = 0x23; + cfg->tx_l1_tx_drv_lvl = 0x25; + cfg->tx_l1_tx_emp_post1_lvl = 0x23; + cfg->tx_l2_tx_drv_lvl = 0x25; + cfg->tx_l2_tx_emp_post1_lvl = 0x23; + cfg->tx_l3_tx_drv_lvl = 0x22; + cfg->tx_l3_tx_emp_post1_lvl = 0x27; + cfg->tx_l0_vmode_ctrl1 = 0x00; + cfg->tx_l0_vmode_ctrl2 = 0x0D; + cfg->tx_l1_vmode_ctrl1 = 0x00; + cfg->tx_l1_vmode_ctrl2 = 0x0D; + cfg->tx_l2_vmode_ctrl1 = 0x00; + cfg->tx_l2_vmode_ctrl2 = 0x0D; + cfg->tx_l3_vmode_ctrl1 = 0x00; + cfg->tx_l3_vmode_ctrl2 = 0x00; + cfg->tx_l0_res_code_lane_tx = 0x3F; + cfg->tx_l1_res_code_lane_tx = 0x3F; + cfg->tx_l2_res_code_lane_tx = 0x3F; + cfg->tx_l3_res_code_lane_tx = 0x3F; + cfg->com_restrim_ctrl = 0x0; + } else if (bclk > HDMI_MID_FREQ_BIT_CLK_THRESHOLD) { + cfg->tx_l0_tx_drv_lvl = 0x25; + cfg->tx_l0_tx_emp_post1_lvl = 0x23; + cfg->tx_l1_tx_drv_lvl = 0x25; + cfg->tx_l1_tx_emp_post1_lvl = 0x23; + cfg->tx_l2_tx_drv_lvl = 0x25; + cfg->tx_l2_tx_emp_post1_lvl = 0x23; + cfg->tx_l3_tx_drv_lvl = 0x25; + cfg->tx_l3_tx_emp_post1_lvl = 0x23; + cfg->tx_l0_vmode_ctrl1 = 0x00; + cfg->tx_l0_vmode_ctrl2 = 0x0D; + cfg->tx_l1_vmode_ctrl1 = 0x00; + cfg->tx_l1_vmode_ctrl2 = 0x0D; + cfg->tx_l2_vmode_ctrl1 = 0x00; + cfg->tx_l2_vmode_ctrl2 = 0x0D; + cfg->tx_l3_vmode_ctrl1 = 0x00; + cfg->tx_l3_vmode_ctrl2 = 0x00; + cfg->tx_l0_res_code_lane_tx = 0x39; + cfg->tx_l1_res_code_lane_tx = 0x39; + cfg->tx_l2_res_code_lane_tx = 0x39; + cfg->tx_l3_res_code_lane_tx = 0x39; + cfg->com_restrim_ctrl = 0x0; + } else { + cfg->tx_l0_tx_drv_lvl = 0x20; + cfg->tx_l0_tx_emp_post1_lvl = 0x20; + cfg->tx_l1_tx_drv_lvl = 0x20; + cfg->tx_l1_tx_emp_post1_lvl = 0x20; + cfg->tx_l2_tx_drv_lvl = 0x20; + cfg->tx_l2_tx_emp_post1_lvl = 0x20; + cfg->tx_l3_tx_drv_lvl = 0x20; + cfg->tx_l3_tx_emp_post1_lvl = 0x20; + cfg->tx_l0_vmode_ctrl1 = 0x00; + cfg->tx_l0_vmode_ctrl2 = 0x0E; + cfg->tx_l1_vmode_ctrl1 = 0x00; + cfg->tx_l1_vmode_ctrl2 = 0x0E; + cfg->tx_l2_vmode_ctrl1 = 0x00; + cfg->tx_l2_vmode_ctrl2 = 0x0E; + cfg->tx_l3_vmode_ctrl1 = 0x00; + cfg->tx_l3_vmode_ctrl2 = 0x0E; + cfg->tx_l0_res_code_lane_tx = 0x3F; + cfg->tx_l1_res_code_lane_tx = 0x3F; + cfg->tx_l2_res_code_lane_tx = 0x3F; + cfg->tx_l3_res_code_lane_tx = 0x3F; + cfg->com_restrim_ctrl = 0xD8; + } + + cfg->phy_mode = (bclk > HDMI_HIGH_FREQ_BIT_CLK_THRESHOLD) ? 0x10 : 0x0; + DEV_DBG("HDMI 8996 PLL: PLL Settings\n"); + DEV_DBG("PLL PARAM: tx_l0_lane_mode = 0x%x\n", cfg->tx_l0_lane_mode); + DEV_DBG("PLL PARAM: tx_l2_lane_mode = 0x%x\n", cfg->tx_l2_lane_mode); + DEV_DBG("PLL PARAM: tx_l0_tx_band = 0x%x\n", cfg->tx_l0_tx_band); + DEV_DBG("PLL PARAM: tx_l1_tx_band = 0x%x\n", cfg->tx_l1_tx_band); + DEV_DBG("PLL PARAM: tx_l2_tx_band = 0x%x\n", cfg->tx_l2_tx_band); + DEV_DBG("PLL PARAM: tx_l3_tx_band = 0x%x\n", cfg->tx_l3_tx_band); + DEV_DBG("PLL PARAM: com_svs_mode_clk_sel = 0x%x\n", + cfg->com_svs_mode_clk_sel); + DEV_DBG("PLL PARAM: com_vco_tune_ctrl = 0x%x\n", + cfg->com_vco_tune_ctrl); + DEV_DBG("PLL PARAM: com_hsclk_sel = 0x%x\n", cfg->com_hsclk_sel); + DEV_DBG("PLL PARAM: com_lock_cmp_en = 0x%x\n", cfg->com_lock_cmp_en); + DEV_DBG("PLL PARAM: com_pll_cctrl_mode0 = 0x%x\n", + cfg->com_pll_cctrl_mode0); + DEV_DBG("PLL PARAM: com_pll_rctrl_mode0 = 0x%x\n", + cfg->com_pll_rctrl_mode0); + DEV_DBG("PLL PARAM: com_cp_ctrl_mode0 = 0x%x\n", + cfg->com_cp_ctrl_mode0); + DEV_DBG("PLL PARAM: com_dec_start_mode0 = 0x%x\n", + cfg->com_dec_start_mode0); + DEV_DBG("PLL PARAM: com_div_frac_start1_mode0 = 0x%x\n", + cfg->com_div_frac_start1_mode0); + DEV_DBG("PLL PARAM: com_div_frac_start2_mode0 = 0x%x\n", + cfg->com_div_frac_start2_mode0); + DEV_DBG("PLL PARAM: com_div_frac_start3_mode0 = 0x%x\n", + cfg->com_div_frac_start3_mode0); + DEV_DBG("PLL PARAM: com_integloop_gain0_mode0 = 0x%x\n", + cfg->com_integloop_gain0_mode0); + DEV_DBG("PLL PARAM: com_integloop_gain1_mode0 = 0x%x\n", + cfg->com_integloop_gain1_mode0); + DEV_DBG("PLL PARAM: com_lock_cmp1_mode0 = 0x%x\n", + cfg->com_lock_cmp1_mode0); + DEV_DBG("PLL PARAM: com_lock_cmp2_mode0 = 0x%x\n", + cfg->com_lock_cmp2_mode0); + DEV_DBG("PLL PARAM: com_lock_cmp3_mode0 = 0x%x\n", + cfg->com_lock_cmp3_mode0); + DEV_DBG("PLL PARAM: com_core_clk_en = 0x%x\n", cfg->com_core_clk_en); + DEV_DBG("PLL PARAM: com_coreclk_div = 0x%x\n", cfg->com_coreclk_div); + + DEV_DBG("PLL PARAM: l0_tx_drv_lvl = 0x%x\n", cfg->tx_l0_tx_drv_lvl); + DEV_DBG("PLL PARAM: l0_tx_emp_post1_lvl = 0x%x\n", + cfg->tx_l0_tx_emp_post1_lvl); + DEV_DBG("PLL PARAM: l1_tx_drv_lvl = 0x%x\n", cfg->tx_l1_tx_drv_lvl); + DEV_DBG("PLL PARAM: l1_tx_emp_post1_lvl = 0x%x\n", + cfg->tx_l1_tx_emp_post1_lvl); + DEV_DBG("PLL PARAM: l2_tx_drv_lvl = 0x%x\n", cfg->tx_l2_tx_drv_lvl); + DEV_DBG("PLL PARAM: l2_tx_emp_post1_lvl = 0x%x\n", + cfg->tx_l2_tx_emp_post1_lvl); + DEV_DBG("PLL PARAM: l3_tx_drv_lvl = 0x%x\n", cfg->tx_l3_tx_drv_lvl); + DEV_DBG("PLL PARAM: l3_tx_emp_post1_lvl = 0x%x\n", + cfg->tx_l3_tx_emp_post1_lvl); + + DEV_DBG("PLL PARAM: l0_vmode_ctrl1 = 0x%x\n", cfg->tx_l0_vmode_ctrl1); + DEV_DBG("PLL PARAM: l0_vmode_ctrl2 = 0x%x\n", cfg->tx_l0_vmode_ctrl2); + DEV_DBG("PLL PARAM: l1_vmode_ctrl1 = 0x%x\n", cfg->tx_l1_vmode_ctrl1); + DEV_DBG("PLL PARAM: l1_vmode_ctrl2 = 0x%x\n", cfg->tx_l1_vmode_ctrl2); + DEV_DBG("PLL PARAM: l2_vmode_ctrl1 = 0x%x\n", cfg->tx_l2_vmode_ctrl1); + DEV_DBG("PLL PARAM: l2_vmode_ctrl2 = 0x%x\n", cfg->tx_l2_vmode_ctrl2); + DEV_DBG("PLL PARAM: l3_vmode_ctrl1 = 0x%x\n", cfg->tx_l3_vmode_ctrl1); + DEV_DBG("PLL PARAM: l3_vmode_ctrl2 = 0x%x\n", cfg->tx_l3_vmode_ctrl2); + DEV_DBG("PLL PARAM: tx_l0_res_code_lane_tx = 0x%x\n", + cfg->tx_l0_res_code_lane_tx); + DEV_DBG("PLL PARAM: tx_l1_res_code_lane_tx = 0x%x\n", + cfg->tx_l1_res_code_lane_tx); + DEV_DBG("PLL PARAM: tx_l2_res_code_lane_tx = 0x%x\n", + cfg->tx_l2_res_code_lane_tx); + DEV_DBG("PLL PARAM: tx_l3_res_code_lane_tx = 0x%x\n", + cfg->tx_l3_res_code_lane_tx); + DEV_DBG("PLL PARAM: com_restrim_ctrl = 0x%x\n", cfg->com_restrim_ctrl); + + DEV_DBG("PLL PARAM: phy_mode = 0x%x\n", cfg->phy_mode); + rc = 0; +fail: + return rc; +} + +static int hdmi_8996_v3_calculate(u32 pix_clk, + struct hdmi_8996_phy_pll_reg_cfg *cfg) +{ + int rc = -EINVAL; + struct hdmi_8996_v3_post_divider pd; + u64 fdata, tmds_clk; + u64 bclk; + u64 pll_cmp; + u64 tx_band; + u64 hsclk; + u64 dec_start; + u64 frac_start; + u64 pll_divisor = 4 * HDMI_REF_CLOCK; + u64 cpctrl; + u64 rctrl; + u64 cctrl; + u64 integloop_gain; + u64 vco_freq; + u64 rem; + + /* FDATA, HSCLK, PIXEL_CLK, TMDS_CLK */ + bclk = ((u64)pix_clk) * HDMI_BIT_CLK_TO_PIX_CLK_RATIO; + + if (bclk > HDMI_HIGH_FREQ_BIT_CLK_THRESHOLD) + tmds_clk = pix_clk >> 2; + else + tmds_clk = pix_clk; + + if (hdmi_8996_v3_get_post_div(&pd, bclk) || pd.vco_ratio <= 0 || + pd.vco_freq <= 0) + goto fail; + + vco_freq = pd.vco_freq; + fdata = pd.vco_freq; + do_div(fdata, pd.vco_ratio); + + hsclk = pd.hsclk_divsel; + dec_start = vco_freq; + do_div(dec_start, pll_divisor); + + frac_start = vco_freq * (1 << 20); + rem = do_div(frac_start, pll_divisor); + frac_start -= dec_start * (1 << 20); + if (rem > (pll_divisor >> 1)) + frac_start++; + + cpctrl = hdmi_8996_get_cpctrl(frac_start, false); + rctrl = hdmi_8996_get_rctrl(frac_start, false); + cctrl = hdmi_8996_get_cctrl(frac_start, false); + integloop_gain = hdmi_8996_v3_get_integloop_gain(frac_start, bclk, + false); + pll_cmp = hdmi_8996_v3_get_pll_cmp(1024, fdata); + tx_band = pd.tx_band_sel; + + /* Debug dump */ + DEV_DBG("%s: VCO freq: %llu\n", __func__, vco_freq); + DEV_DBG("%s: fdata: %llu\n", __func__, fdata); + DEV_DBG("%s: pix_clk: %d\n", __func__, pix_clk); + DEV_DBG("%s: tmds clk: %llu\n", __func__, tmds_clk); + DEV_DBG("%s: HSCLK_SEL: %llu\n", __func__, hsclk); + DEV_DBG("%s: DEC_START: %llu\n", __func__, dec_start); + DEV_DBG("%s: DIV_FRAC_START: %llu\n", __func__, frac_start); + DEV_DBG("%s: PLL_CPCTRL: %llu\n", __func__, cpctrl); + DEV_DBG("%s: PLL_RCTRL: %llu\n", __func__, rctrl); + DEV_DBG("%s: PLL_CCTRL: %llu\n", __func__, cctrl); + DEV_DBG("%s: INTEGLOOP_GAIN: %llu\n", __func__, integloop_gain); + DEV_DBG("%s: TX_BAND: %llu\n", __func__, tx_band); + DEV_DBG("%s: PLL_CMP: %llu\n", __func__, pll_cmp); + + /* Convert these values to register specific values */ + cfg->tx_l0_tx_band = tx_band + 4; + cfg->tx_l1_tx_band = tx_band + 4; + cfg->tx_l2_tx_band = tx_band + 4; + cfg->tx_l3_tx_band = tx_band + 4; + + if (bclk > HDMI_DIG_FREQ_BIT_CLK_THRESHOLD) + cfg->com_svs_mode_clk_sel = 1; + else + cfg->com_svs_mode_clk_sel = 2; + + cfg->com_hsclk_sel = (0x20 | hsclk); + cfg->com_pll_cctrl_mode0 = cctrl; + cfg->com_pll_rctrl_mode0 = rctrl; + cfg->com_cp_ctrl_mode0 = cpctrl; + cfg->com_dec_start_mode0 = dec_start; + cfg->com_div_frac_start1_mode0 = (frac_start & 0xFF); + cfg->com_div_frac_start2_mode0 = ((frac_start & 0xFF00) >> 8); + cfg->com_div_frac_start3_mode0 = ((frac_start & 0xF0000) >> 16); + cfg->com_integloop_gain0_mode0 = (integloop_gain & 0xFF); + cfg->com_integloop_gain1_mode0 = ((integloop_gain & 0xF00) >> 8); + cfg->com_lock_cmp1_mode0 = (pll_cmp & 0xFF); + cfg->com_lock_cmp2_mode0 = ((pll_cmp & 0xFF00) >> 8); + cfg->com_lock_cmp3_mode0 = ((pll_cmp & 0x30000) >> 16); + cfg->com_lock_cmp_en = 0x04; + cfg->com_core_clk_en = 0x2C; + cfg->com_coreclk_div = HDMI_CORECLK_DIV; + cfg->phy_mode = (bclk > HDMI_HIGH_FREQ_BIT_CLK_THRESHOLD) ? 0x10 : 0x0; + cfg->com_vco_tune_ctrl = 0x0; + + cfg->tx_l0_lane_mode = 0x43; + cfg->tx_l2_lane_mode = 0x43; + + if (bclk > HDMI_HIGH_FREQ_BIT_CLK_THRESHOLD) { + cfg->tx_l0_tx_drv_lvl = 0x25; + cfg->tx_l0_tx_emp_post1_lvl = 0x23; + cfg->tx_l1_tx_drv_lvl = 0x25; + cfg->tx_l1_tx_emp_post1_lvl = 0x23; + cfg->tx_l2_tx_drv_lvl = 0x25; + cfg->tx_l2_tx_emp_post1_lvl = 0x23; + cfg->tx_l3_tx_drv_lvl = 0x22; + cfg->tx_l3_tx_emp_post1_lvl = 0x27; + cfg->tx_l0_vmode_ctrl1 = 0x00; + cfg->tx_l0_vmode_ctrl2 = 0x0D; + cfg->tx_l1_vmode_ctrl1 = 0x00; + cfg->tx_l1_vmode_ctrl2 = 0x0D; + cfg->tx_l2_vmode_ctrl1 = 0x00; + cfg->tx_l2_vmode_ctrl2 = 0x0D; + cfg->tx_l3_vmode_ctrl1 = 0x00; + cfg->tx_l3_vmode_ctrl2 = 0x00; + } else if (bclk > HDMI_MID_FREQ_BIT_CLK_THRESHOLD) { + cfg->tx_l0_tx_drv_lvl = 0x25; + cfg->tx_l0_tx_emp_post1_lvl = 0x23; + cfg->tx_l1_tx_drv_lvl = 0x25; + cfg->tx_l1_tx_emp_post1_lvl = 0x23; + cfg->tx_l2_tx_drv_lvl = 0x25; + cfg->tx_l2_tx_emp_post1_lvl = 0x23; + cfg->tx_l3_tx_drv_lvl = 0x25; + cfg->tx_l3_tx_emp_post1_lvl = 0x23; + cfg->tx_l0_vmode_ctrl1 = 0x00; + cfg->tx_l0_vmode_ctrl2 = 0x0D; + cfg->tx_l1_vmode_ctrl1 = 0x00; + cfg->tx_l1_vmode_ctrl2 = 0x0D; + cfg->tx_l2_vmode_ctrl1 = 0x00; + cfg->tx_l2_vmode_ctrl2 = 0x0D; + cfg->tx_l3_vmode_ctrl1 = 0x00; + cfg->tx_l3_vmode_ctrl2 = 0x00; + } else { + cfg->tx_l0_tx_drv_lvl = 0x20; + cfg->tx_l0_tx_emp_post1_lvl = 0x20; + cfg->tx_l1_tx_drv_lvl = 0x20; + cfg->tx_l1_tx_emp_post1_lvl = 0x20; + cfg->tx_l2_tx_drv_lvl = 0x20; + cfg->tx_l2_tx_emp_post1_lvl = 0x20; + cfg->tx_l3_tx_drv_lvl = 0x20; + cfg->tx_l3_tx_emp_post1_lvl = 0x20; + cfg->tx_l0_vmode_ctrl1 = 0x00; + cfg->tx_l0_vmode_ctrl2 = 0x0E; + cfg->tx_l1_vmode_ctrl1 = 0x00; + cfg->tx_l1_vmode_ctrl2 = 0x0E; + cfg->tx_l2_vmode_ctrl1 = 0x00; + cfg->tx_l2_vmode_ctrl2 = 0x0E; + cfg->tx_l3_vmode_ctrl1 = 0x00; + cfg->tx_l3_vmode_ctrl2 = 0x0E; + } + + DEV_DBG("HDMI 8996 PLL: PLL Settings\n"); + DEV_DBG("PLL PARAM: tx_l0_tx_band = 0x%x\n", cfg->tx_l0_tx_band); + DEV_DBG("PLL PARAM: tx_l1_tx_band = 0x%x\n", cfg->tx_l1_tx_band); + DEV_DBG("PLL PARAM: tx_l2_tx_band = 0x%x\n", cfg->tx_l2_tx_band); + DEV_DBG("PLL PARAM: tx_l3_tx_band = 0x%x\n", cfg->tx_l3_tx_band); + DEV_DBG("PLL PARAM: com_svs_mode_clk_sel = 0x%x\n", + cfg->com_svs_mode_clk_sel); + DEV_DBG("PLL PARAM: com_hsclk_sel = 0x%x\n", cfg->com_hsclk_sel); + DEV_DBG("PLL PARAM: com_lock_cmp_en = 0x%x\n", cfg->com_lock_cmp_en); + DEV_DBG("PLL PARAM: com_pll_cctrl_mode0 = 0x%x\n", + cfg->com_pll_cctrl_mode0); + DEV_DBG("PLL PARAM: com_pll_rctrl_mode0 = 0x%x\n", + cfg->com_pll_rctrl_mode0); + DEV_DBG("PLL PARAM: com_cp_ctrl_mode0 = 0x%x\n", + cfg->com_cp_ctrl_mode0); + DEV_DBG("PLL PARAM: com_dec_start_mode0 = 0x%x\n", + cfg->com_dec_start_mode0); + DEV_DBG("PLL PARAM: com_div_frac_start1_mode0 = 0x%x\n", + cfg->com_div_frac_start1_mode0); + DEV_DBG("PLL PARAM: com_div_frac_start2_mode0 = 0x%x\n", + cfg->com_div_frac_start2_mode0); + DEV_DBG("PLL PARAM: com_div_frac_start3_mode0 = 0x%x\n", + cfg->com_div_frac_start3_mode0); + DEV_DBG("PLL PARAM: com_integloop_gain0_mode0 = 0x%x\n", + cfg->com_integloop_gain0_mode0); + DEV_DBG("PLL PARAM: com_integloop_gain1_mode0 = 0x%x\n", + cfg->com_integloop_gain1_mode0); + DEV_DBG("PLL PARAM: com_lock_cmp1_mode0 = 0x%x\n", + cfg->com_lock_cmp1_mode0); + DEV_DBG("PLL PARAM: com_lock_cmp2_mode0 = 0x%x\n", + cfg->com_lock_cmp2_mode0); + DEV_DBG("PLL PARAM: com_lock_cmp3_mode0 = 0x%x\n", + cfg->com_lock_cmp3_mode0); + DEV_DBG("PLL PARAM: com_core_clk_en = 0x%x\n", cfg->com_core_clk_en); + DEV_DBG("PLL PARAM: com_coreclk_div = 0x%x\n", cfg->com_coreclk_div); + DEV_DBG("PLL PARAM: phy_mode = 0x%x\n", cfg->phy_mode); + + DEV_DBG("PLL PARAM: tx_l0_lane_mode = 0x%x\n", cfg->tx_l0_lane_mode); + DEV_DBG("PLL PARAM: tx_l2_lane_mode = 0x%x\n", cfg->tx_l2_lane_mode); + DEV_DBG("PLL PARAM: l0_tx_drv_lvl = 0x%x\n", cfg->tx_l0_tx_drv_lvl); + DEV_DBG("PLL PARAM: l0_tx_emp_post1_lvl = 0x%x\n", + cfg->tx_l0_tx_emp_post1_lvl); + DEV_DBG("PLL PARAM: l1_tx_drv_lvl = 0x%x\n", cfg->tx_l1_tx_drv_lvl); + DEV_DBG("PLL PARAM: l1_tx_emp_post1_lvl = 0x%x\n", + cfg->tx_l1_tx_emp_post1_lvl); + DEV_DBG("PLL PARAM: l2_tx_drv_lvl = 0x%x\n", cfg->tx_l2_tx_drv_lvl); + DEV_DBG("PLL PARAM: l2_tx_emp_post1_lvl = 0x%x\n", + cfg->tx_l2_tx_emp_post1_lvl); + DEV_DBG("PLL PARAM: l3_tx_drv_lvl = 0x%x\n", cfg->tx_l3_tx_drv_lvl); + DEV_DBG("PLL PARAM: l3_tx_emp_post1_lvl = 0x%x\n", + cfg->tx_l3_tx_emp_post1_lvl); + + DEV_DBG("PLL PARAM: l0_vmode_ctrl1 = 0x%x\n", cfg->tx_l0_vmode_ctrl1); + DEV_DBG("PLL PARAM: l0_vmode_ctrl2 = 0x%x\n", cfg->tx_l0_vmode_ctrl2); + DEV_DBG("PLL PARAM: l1_vmode_ctrl1 = 0x%x\n", cfg->tx_l1_vmode_ctrl1); + DEV_DBG("PLL PARAM: l1_vmode_ctrl2 = 0x%x\n", cfg->tx_l1_vmode_ctrl2); + DEV_DBG("PLL PARAM: l2_vmode_ctrl1 = 0x%x\n", cfg->tx_l2_vmode_ctrl1); + DEV_DBG("PLL PARAM: l2_vmode_ctrl2 = 0x%x\n", cfg->tx_l2_vmode_ctrl2); + DEV_DBG("PLL PARAM: l3_vmode_ctrl1 = 0x%x\n", cfg->tx_l3_vmode_ctrl1); + DEV_DBG("PLL PARAM: l3_vmode_ctrl2 = 0x%x\n", cfg->tx_l3_vmode_ctrl2); + rc = 0; +fail: + return rc; +} + +static int hdmi_8996_calculate(u32 pix_clk, + struct hdmi_8996_phy_pll_reg_cfg *cfg, u32 ver) +{ + switch (ver) { + case HDMI_VERSION_8996_V3: + case HDMI_VERSION_8996_V3_1_8: + return hdmi_8996_v3_calculate(pix_clk, cfg); + case HDMI_VERSION_8996_V2: + return hdmi_8996_v2_calculate(pix_clk, cfg); + default: + return hdmi_8996_v1_calculate(pix_clk, cfg); + } +} + +static int hdmi_8996_phy_pll_set_clk_rate(struct clk *c, u32 tmds_clk, u32 ver) +{ + int rc = 0; + struct hdmi_pll_vco_clk *vco = to_hdmi_8996_vco_clk(c); + struct mdss_pll_resources *io = vco->priv; + struct hdmi_8996_phy_pll_reg_cfg cfg = {0}; + + rc = hdmi_8996_calculate(tmds_clk, &cfg, ver); + if (rc) { + DEV_ERR("%s: PLL calculation failed\n", __func__); + return rc; + } + + /* Initially shut down PHY */ + DEV_DBG("%s: Disabling PHY\n", __func__); + MDSS_PLL_REG_W(io->phy_base, HDMI_PHY_PD_CTL, 0x0); + udelay(500); + + /* Power up sequence */ + switch (ver) { + case HDMI_VERSION_8996_V2: + case HDMI_VERSION_8996_V3: + case HDMI_VERSION_8996_V3_1_8: + MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_BG_CTRL, 0x04); + break; + }; + + MDSS_PLL_REG_W(io->phy_base, HDMI_PHY_PD_CTL, 0x1); + MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_RESETSM_CNTRL, 0x20); + MDSS_PLL_REG_W(io->phy_base, HDMI_PHY_TX0_TX1_LANE_CTL, 0x0F); + MDSS_PLL_REG_W(io->phy_base, HDMI_PHY_TX2_TX3_LANE_CTL, 0x0F); + MDSS_PLL_REG_W(io->pll_base + HDMI_TX_L0_BASE_OFFSET, + QSERDES_TX_L0_CLKBUF_ENABLE, 0x03); + MDSS_PLL_REG_W(io->pll_base + HDMI_TX_L1_BASE_OFFSET, + QSERDES_TX_L0_CLKBUF_ENABLE, 0x03); + MDSS_PLL_REG_W(io->pll_base + HDMI_TX_L2_BASE_OFFSET, + QSERDES_TX_L0_CLKBUF_ENABLE, 0x03); + MDSS_PLL_REG_W(io->pll_base + HDMI_TX_L3_BASE_OFFSET, + QSERDES_TX_L0_CLKBUF_ENABLE, 0x03); + + MDSS_PLL_REG_W(io->pll_base + HDMI_TX_L0_BASE_OFFSET, + QSERDES_TX_L0_LANE_MODE, cfg.tx_l0_lane_mode); + MDSS_PLL_REG_W(io->pll_base + HDMI_TX_L2_BASE_OFFSET, + QSERDES_TX_L0_LANE_MODE, cfg.tx_l2_lane_mode); + + MDSS_PLL_REG_W(io->pll_base + HDMI_TX_L0_BASE_OFFSET, + QSERDES_TX_L0_TX_BAND, cfg.tx_l0_tx_band); + MDSS_PLL_REG_W(io->pll_base + HDMI_TX_L1_BASE_OFFSET, + QSERDES_TX_L0_TX_BAND, cfg.tx_l1_tx_band); + MDSS_PLL_REG_W(io->pll_base + HDMI_TX_L2_BASE_OFFSET, + QSERDES_TX_L0_TX_BAND, cfg.tx_l2_tx_band); + MDSS_PLL_REG_W(io->pll_base + HDMI_TX_L3_BASE_OFFSET, + QSERDES_TX_L0_TX_BAND, cfg.tx_l3_tx_band); + + MDSS_PLL_REG_W(io->pll_base + HDMI_TX_L0_BASE_OFFSET, + QSERDES_TX_L0_RESET_TSYNC_EN, 0x03); + MDSS_PLL_REG_W(io->pll_base + HDMI_TX_L1_BASE_OFFSET, + QSERDES_TX_L0_RESET_TSYNC_EN, 0x03); + MDSS_PLL_REG_W(io->pll_base + HDMI_TX_L2_BASE_OFFSET, + QSERDES_TX_L0_RESET_TSYNC_EN, 0x03); + MDSS_PLL_REG_W(io->pll_base + HDMI_TX_L3_BASE_OFFSET, + QSERDES_TX_L0_RESET_TSYNC_EN, 0x03); + + MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_SYSCLK_BUF_ENABLE, 0x1E); + MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x07); + MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_SYSCLK_EN_SEL, 0x37); + MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_SYS_CLK_CTRL, 0x02); + MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_CLK_ENABLE1, 0x0E); + if (ver == HDMI_VERSION_8996_V1) + MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_BG_CTRL, 0x06); + + /* Bypass VCO calibration */ + MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_SVS_MODE_CLK_SEL, + cfg.com_svs_mode_clk_sel); + + MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_BG_TRIM, 0x0F); + MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_PLL_IVCO, 0x0F); + MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_VCO_TUNE_CTRL, + cfg.com_vco_tune_ctrl); + + switch (ver) { + case HDMI_VERSION_8996_V1: + MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_SVS_MODE_CLK_SEL, + cfg.com_svs_mode_clk_sel); + break; + default: + MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_BG_CTRL, 0x06); + } + + MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_CLK_SELECT, 0x30); + MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_HSCLK_SEL, + cfg.com_hsclk_sel); + MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_LOCK_CMP_EN, + cfg.com_lock_cmp_en); + + MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_PLL_CCTRL_MODE0, + cfg.com_pll_cctrl_mode0); + MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_PLL_RCTRL_MODE0, + cfg.com_pll_rctrl_mode0); + MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_CP_CTRL_MODE0, + cfg.com_cp_ctrl_mode0); + MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_DEC_START_MODE0, + cfg.com_dec_start_mode0); + MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_DIV_FRAC_START1_MODE0, + cfg.com_div_frac_start1_mode0); + MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_DIV_FRAC_START2_MODE0, + cfg.com_div_frac_start2_mode0); + MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_DIV_FRAC_START3_MODE0, + cfg.com_div_frac_start3_mode0); + + MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_INTEGLOOP_GAIN0_MODE0, + cfg.com_integloop_gain0_mode0); + MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_INTEGLOOP_GAIN1_MODE0, + cfg.com_integloop_gain1_mode0); + + MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_LOCK_CMP1_MODE0, + cfg.com_lock_cmp1_mode0); + MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_LOCK_CMP2_MODE0, + cfg.com_lock_cmp2_mode0); + MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_LOCK_CMP3_MODE0, + cfg.com_lock_cmp3_mode0); + + MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_VCO_TUNE_MAP, 0x00); + MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_CORE_CLK_EN, + cfg.com_core_clk_en); + MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_CORECLK_DIV, + cfg.com_coreclk_div); + MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_CMN_CONFIG, 0x02); + + if (ver == HDMI_VERSION_8996_V3 || ver == HDMI_VERSION_8996_V3_1_8) + MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_RESCODE_DIV_NUM, 0x15); + + /* TX lanes setup (TX 0/1/2/3) */ + if (ver == HDMI_VERSION_8996_V3_1_8) { + MDSS_PLL_REG_W(io->pll_base + HDMI_TX_L0_BASE_OFFSET, + QSERDES_TX_L0_TX_DRV_LVL, + 0x00000023); + } else { + MDSS_PLL_REG_W(io->pll_base + HDMI_TX_L0_BASE_OFFSET, + QSERDES_TX_L0_TX_DRV_LVL, + cfg.tx_l0_tx_drv_lvl); + } + MDSS_PLL_REG_W(io->pll_base + HDMI_TX_L0_BASE_OFFSET, + QSERDES_TX_L0_TX_EMP_POST1_LVL, + cfg.tx_l0_tx_emp_post1_lvl); + + if (ver == HDMI_VERSION_8996_V3_1_8) { + MDSS_PLL_REG_W(io->pll_base + HDMI_TX_L1_BASE_OFFSET, + QSERDES_TX_L0_TX_DRV_LVL, + 0x00000023); + } else { + MDSS_PLL_REG_W(io->pll_base + HDMI_TX_L1_BASE_OFFSET, + QSERDES_TX_L0_TX_DRV_LVL, + cfg.tx_l1_tx_drv_lvl); + } + MDSS_PLL_REG_W(io->pll_base + HDMI_TX_L1_BASE_OFFSET, + QSERDES_TX_L0_TX_EMP_POST1_LVL, + cfg.tx_l1_tx_emp_post1_lvl); + + if (ver == HDMI_VERSION_8996_V3_1_8) { + MDSS_PLL_REG_W(io->pll_base + HDMI_TX_L2_BASE_OFFSET, + QSERDES_TX_L0_TX_DRV_LVL, + 0x00000023); + } else { + MDSS_PLL_REG_W(io->pll_base + HDMI_TX_L2_BASE_OFFSET, + QSERDES_TX_L0_TX_DRV_LVL, + cfg.tx_l2_tx_drv_lvl); + } + MDSS_PLL_REG_W(io->pll_base + HDMI_TX_L2_BASE_OFFSET, + QSERDES_TX_L0_TX_EMP_POST1_LVL, + cfg.tx_l2_tx_emp_post1_lvl); + + if (ver == HDMI_VERSION_8996_V3_1_8) { + MDSS_PLL_REG_W(io->pll_base + HDMI_TX_L3_BASE_OFFSET, + QSERDES_TX_L0_TX_DRV_LVL, + 0x00000020); + } else { + MDSS_PLL_REG_W(io->pll_base + HDMI_TX_L3_BASE_OFFSET, + QSERDES_TX_L0_TX_DRV_LVL, + cfg.tx_l3_tx_drv_lvl); + } + MDSS_PLL_REG_W(io->pll_base + HDMI_TX_L3_BASE_OFFSET, + QSERDES_TX_L0_TX_EMP_POST1_LVL, + cfg.tx_l3_tx_emp_post1_lvl); + + MDSS_PLL_REG_W(io->pll_base + HDMI_TX_L0_BASE_OFFSET, + QSERDES_TX_L0_VMODE_CTRL1, + cfg.tx_l0_vmode_ctrl1); + MDSS_PLL_REG_W(io->pll_base + HDMI_TX_L0_BASE_OFFSET, + QSERDES_TX_L0_VMODE_CTRL2, + cfg.tx_l0_vmode_ctrl2); + + MDSS_PLL_REG_W(io->pll_base + HDMI_TX_L1_BASE_OFFSET, + QSERDES_TX_L0_VMODE_CTRL1, + cfg.tx_l1_vmode_ctrl1); + MDSS_PLL_REG_W(io->pll_base + HDMI_TX_L1_BASE_OFFSET, + QSERDES_TX_L0_VMODE_CTRL2, + cfg.tx_l1_vmode_ctrl2); + + MDSS_PLL_REG_W(io->pll_base + HDMI_TX_L2_BASE_OFFSET, + QSERDES_TX_L0_VMODE_CTRL1, + cfg.tx_l2_vmode_ctrl1); + MDSS_PLL_REG_W(io->pll_base + HDMI_TX_L2_BASE_OFFSET, + QSERDES_TX_L0_VMODE_CTRL2, + cfg.tx_l2_vmode_ctrl2); + + MDSS_PLL_REG_W(io->pll_base + HDMI_TX_L3_BASE_OFFSET, + QSERDES_TX_L0_VMODE_CTRL1, + cfg.tx_l3_vmode_ctrl1); + if (ver == HDMI_VERSION_8996_V3_1_8) { + MDSS_PLL_REG_W(io->pll_base + HDMI_TX_L3_BASE_OFFSET, + QSERDES_TX_L0_VMODE_CTRL2, + 0x0000000D); + } else { + MDSS_PLL_REG_W(io->pll_base + HDMI_TX_L3_BASE_OFFSET, + QSERDES_TX_L0_VMODE_CTRL2, + cfg.tx_l3_vmode_ctrl2); + } + + MDSS_PLL_REG_W(io->pll_base + HDMI_TX_L0_BASE_OFFSET, + QSERDES_TX_L0_TX_DRV_LVL_OFFSET, 0x00); + MDSS_PLL_REG_W(io->pll_base + HDMI_TX_L1_BASE_OFFSET, + QSERDES_TX_L0_TX_DRV_LVL_OFFSET, 0x00); + MDSS_PLL_REG_W(io->pll_base + HDMI_TX_L2_BASE_OFFSET, + QSERDES_TX_L0_TX_DRV_LVL_OFFSET, 0x00); + MDSS_PLL_REG_W(io->pll_base + HDMI_TX_L3_BASE_OFFSET, + QSERDES_TX_L0_TX_DRV_LVL_OFFSET, 0x00); + + MDSS_PLL_REG_W(io->pll_base + HDMI_TX_L0_BASE_OFFSET, + QSERDES_TX_L0_RES_CODE_LANE_OFFSET, 0x00); + MDSS_PLL_REG_W(io->pll_base + HDMI_TX_L1_BASE_OFFSET, + QSERDES_TX_L0_RES_CODE_LANE_OFFSET, 0x00); + MDSS_PLL_REG_W(io->pll_base + HDMI_TX_L2_BASE_OFFSET, + QSERDES_TX_L0_RES_CODE_LANE_OFFSET, 0x00); + MDSS_PLL_REG_W(io->pll_base + HDMI_TX_L3_BASE_OFFSET, + QSERDES_TX_L0_RES_CODE_LANE_OFFSET, 0x00); + + if (ver < HDMI_VERSION_8996_V3) { + MDSS_PLL_REG_W(io->pll_base + HDMI_TX_L0_BASE_OFFSET, + QSERDES_TX_L0_RES_CODE_LANE_TX, + cfg.tx_l0_res_code_lane_tx); + MDSS_PLL_REG_W(io->pll_base + HDMI_TX_L1_BASE_OFFSET, + QSERDES_TX_L0_RES_CODE_LANE_TX, + cfg.tx_l1_res_code_lane_tx); + MDSS_PLL_REG_W(io->pll_base + HDMI_TX_L2_BASE_OFFSET, + QSERDES_TX_L0_RES_CODE_LANE_TX, + cfg.tx_l2_res_code_lane_tx); + MDSS_PLL_REG_W(io->pll_base + HDMI_TX_L3_BASE_OFFSET, + QSERDES_TX_L0_RES_CODE_LANE_TX, + cfg.tx_l3_res_code_lane_tx); + MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_RESTRIM_CTRL, + cfg.com_restrim_ctrl); + + MDSS_PLL_REG_W(io->phy_base, HDMI_PHY_TXCAL_CFG0, 0x00); + MDSS_PLL_REG_W(io->phy_base, HDMI_PHY_TXCAL_CFG1, 0x05); + } + + MDSS_PLL_REG_W(io->phy_base, HDMI_PHY_MODE, cfg.phy_mode); + MDSS_PLL_REG_W(io->phy_base, HDMI_PHY_PD_CTL, 0x1F); + + MDSS_PLL_REG_W(io->pll_base + HDMI_TX_L0_BASE_OFFSET, + QSERDES_TX_L0_TRAN_DRVR_EMP_EN, 0x03); + MDSS_PLL_REG_W(io->pll_base + HDMI_TX_L1_BASE_OFFSET, + QSERDES_TX_L0_TRAN_DRVR_EMP_EN, 0x03); + MDSS_PLL_REG_W(io->pll_base + HDMI_TX_L2_BASE_OFFSET, + QSERDES_TX_L0_TRAN_DRVR_EMP_EN, 0x03); + MDSS_PLL_REG_W(io->pll_base + HDMI_TX_L3_BASE_OFFSET, + QSERDES_TX_L0_TRAN_DRVR_EMP_EN, 0x03); + + MDSS_PLL_REG_W(io->pll_base + HDMI_TX_L0_BASE_OFFSET, + QSERDES_TX_L0_PARRATE_REC_DETECT_IDLE_EN, 0x40); + MDSS_PLL_REG_W(io->pll_base + HDMI_TX_L1_BASE_OFFSET, + QSERDES_TX_L0_PARRATE_REC_DETECT_IDLE_EN, 0x40); + MDSS_PLL_REG_W(io->pll_base + HDMI_TX_L2_BASE_OFFSET, + QSERDES_TX_L0_PARRATE_REC_DETECT_IDLE_EN, 0x40); + MDSS_PLL_REG_W(io->pll_base + HDMI_TX_L3_BASE_OFFSET, + QSERDES_TX_L0_PARRATE_REC_DETECT_IDLE_EN, 0x40); + + MDSS_PLL_REG_W(io->pll_base + HDMI_TX_L0_BASE_OFFSET, + QSERDES_TX_L0_HP_PD_ENABLES, 0x0C); + MDSS_PLL_REG_W(io->pll_base + HDMI_TX_L1_BASE_OFFSET, + QSERDES_TX_L0_HP_PD_ENABLES, 0x0C); + MDSS_PLL_REG_W(io->pll_base + HDMI_TX_L2_BASE_OFFSET, + QSERDES_TX_L0_HP_PD_ENABLES, 0x0C); + MDSS_PLL_REG_W(io->pll_base + HDMI_TX_L3_BASE_OFFSET, + QSERDES_TX_L0_HP_PD_ENABLES, 0x03); + + if (ver == HDMI_VERSION_8996_V2) { + MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_ATB_SEL1, 0x01); + MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_ATB_SEL2, 0x01); + } + /* + * Ensure that vco configuration gets flushed to hardware before + * enabling the PLL + */ + wmb(); + return 0; +} + +static int hdmi_8996_phy_ready_status(struct mdss_pll_resources *io) +{ + u32 status = 0; + int phy_ready = 0; + int rc; + u32 read_count = 0; + + rc = mdss_pll_resource_enable(io, true); + if (rc) { + DEV_ERR("%s: pll resource can't be enabled\n", __func__); + return rc; + } + + DEV_DBG("%s: Waiting for PHY Ready\n", __func__); + + /* Poll for PHY read status */ + while (read_count < HDMI_PLL_POLL_MAX_READS) { + status = MDSS_PLL_REG_R(io->phy_base, HDMI_PHY_STATUS); + if ((status & BIT(0)) == 1) { + phy_ready = 1; + DEV_DBG("%s: PHY READY\n", __func__); + break; + } + udelay(HDMI_PLL_POLL_TIMEOUT_US); + read_count++; + } + + if (read_count == HDMI_PLL_POLL_MAX_READS) { + phy_ready = 0; + DEV_DBG("%s: PHY READY TIMEOUT\n", __func__); + } + + mdss_pll_resource_enable(io, false); + + return phy_ready; +} + +static int hdmi_8996_pll_lock_status(struct mdss_pll_resources *io) +{ + u32 status; + int pll_locked = 0; + int rc; + u32 read_count = 0; + + rc = mdss_pll_resource_enable(io, true); + if (rc) { + DEV_ERR("%s: pll resource can't be enabled\n", __func__); + return rc; + } + + DEV_DBG("%s: Waiting for PLL lock\n", __func__); + + while (read_count < HDMI_PLL_POLL_MAX_READS) { + status = MDSS_PLL_REG_R(io->pll_base, + QSERDES_COM_C_READY_STATUS); + if ((status & BIT(0)) == 1) { + pll_locked = 1; + DEV_DBG("%s: C READY\n", __func__); + break; + } + udelay(HDMI_PLL_POLL_TIMEOUT_US); + read_count++; + } + + if (read_count == HDMI_PLL_POLL_MAX_READS) { + pll_locked = 0; + DEV_DBG("%s: C READY TIMEOUT\n", __func__); + } + + mdss_pll_resource_enable(io, false); + + return pll_locked; +} + +static int hdmi_8996_v1_perform_sw_calibration(struct clk *c) +{ + int rc = 0; + struct hdmi_pll_vco_clk *vco = to_hdmi_8996_vco_clk(c); + struct mdss_pll_resources *io = vco->priv; + + u32 max_code = 0x190; + u32 min_code = 0x0; + u32 max_cnt = 0; + u32 min_cnt = 0; + u32 expected_counter_value = 0; + u32 step = 0; + u32 dbus_all = 0; + u32 dbus_sel = 0; + u32 vco_code = 0; + u32 val = 0; + + vco_code = 0xC8; + + DEV_DBG("%s: Starting SW calibration with vco_code = %d\n", __func__, + vco_code); + + expected_counter_value = + (MDSS_PLL_REG_R(io->pll_base, QSERDES_COM_LOCK_CMP3_MODE0) << 16) | + (MDSS_PLL_REG_R(io->pll_base, QSERDES_COM_LOCK_CMP2_MODE0) << 8) | + (MDSS_PLL_REG_R(io->pll_base, QSERDES_COM_LOCK_CMP1_MODE0)); + + DEV_DBG("%s: expected_counter_value = %d\n", __func__, + expected_counter_value); + + val = MDSS_PLL_REG_R(io->pll_base, QSERDES_COM_CMN_MISC1); + val |= BIT(4); + MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_CMN_MISC1, val); + + val = MDSS_PLL_REG_R(io->pll_base, QSERDES_COM_CMN_MISC1); + val |= BIT(3); + MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_CMN_MISC1, val); + + MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_DEBUG_BUS_SEL, 0x4); + + val = MDSS_PLL_REG_R(io->pll_base, QSERDES_COM_LOCK_CMP_CFG); + val |= BIT(1); + MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_LOCK_CMP_CFG, val); + + udelay(60); + + while (1) { + MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_VCO_TUNE1_MODE0, + vco_code & 0xFF); + MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_VCO_TUNE2_MODE0, + (vco_code >> 8) & 0x3); + + udelay(20); + + val = MDSS_PLL_REG_R(io->pll_base, QSERDES_COM_LOCK_CMP_CFG); + val &= ~BIT(1); + MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_LOCK_CMP_CFG, val); + + udelay(60); + + val = MDSS_PLL_REG_R(io->pll_base, QSERDES_COM_LOCK_CMP_CFG); + val |= BIT(1); + MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_LOCK_CMP_CFG, val); + + udelay(60); + + dbus_all = + (MDSS_PLL_REG_R(io->pll_base, QSERDES_COM_DEBUG_BUS3) << 24) | + (MDSS_PLL_REG_R(io->pll_base, QSERDES_COM_DEBUG_BUS2) << 16) | + (MDSS_PLL_REG_R(io->pll_base, QSERDES_COM_DEBUG_BUS1) << 8) | + (MDSS_PLL_REG_R(io->pll_base, QSERDES_COM_DEBUG_BUS0)); + + dbus_sel = (dbus_all >> 9) & 0x3FFFF; + DEV_DBG("%s: loop[%d], dbus_all = 0x%x, dbus_sel = 0x%x\n", + __func__, step, dbus_all, dbus_sel); + if (dbus_sel == 0) + DEV_ERR("%s: CHECK HDMI REF CLK\n", __func__); + + if (dbus_sel == expected_counter_value) { + max_code = vco_code; + max_cnt = dbus_sel; + min_code = vco_code; + min_cnt = dbus_sel; + } else if (dbus_sel == 0) { + max_code = vco_code; + max_cnt = dbus_sel; + vco_code = (max_code + min_code)/2; + } else if (dbus_sel > expected_counter_value) { + min_code = vco_code; + min_cnt = dbus_sel; + vco_code = (max_code + min_code)/2; + } else if (dbus_sel < expected_counter_value) { + max_code = vco_code; + max_cnt = dbus_sel; + vco_code = (max_code + min_code)/2; + } + + step++; + + if ((vco_code == 0) || (vco_code == 0x3FF) || (step > 0x3FF)) { + DEV_ERR("%s: VCO tune code search failed\n", __func__); + rc = -ENOTSUPP; + break; + } + if ((max_code - min_code) <= 1) { + if ((max_code - min_code) == 1) { + if (abs((int)(max_cnt - expected_counter_value)) + < abs((int)(min_cnt - expected_counter_value + ))) { + vco_code = max_code; + } else { + vco_code = min_code; + } + } + break; + } + DEV_DBG("%s: loop[%d], new vco_code = %d\n", __func__, step, + vco_code); + } + + DEV_DBG("%s: CALIB done. vco_code = %d\n", __func__, vco_code); + MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_VCO_TUNE1_MODE0, + vco_code & 0xFF); + MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_VCO_TUNE2_MODE0, + (vco_code >> 8) & 0x3); + val = MDSS_PLL_REG_R(io->pll_base, QSERDES_COM_LOCK_CMP_CFG); + val &= ~BIT(1); + MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_LOCK_CMP_CFG, val); + + val = MDSS_PLL_REG_R(io->pll_base, QSERDES_COM_CMN_MISC1); + val |= BIT(4); + MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_CMN_MISC1, val); + + val = MDSS_PLL_REG_R(io->pll_base, QSERDES_COM_CMN_MISC1); + val &= ~BIT(3); + MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_CMN_MISC1, val); + + return rc; +} + +static int hdmi_8996_v2_perform_sw_calibration(struct clk *c) +{ + int rc = 0; + struct hdmi_pll_vco_clk *vco = to_hdmi_8996_vco_clk(c); + struct mdss_pll_resources *io = vco->priv; + u32 vco_code1, vco_code2, integral_loop, ready_poll; + u32 read_count = 0; + + while (read_count < (HDMI_PLL_POLL_MAX_READS << 1)) { + ready_poll = MDSS_PLL_REG_R(io->pll_base, + QSERDES_COM_C_READY_STATUS); + if ((ready_poll & BIT(0)) == 1) { + ready_poll = 1; + DEV_DBG("%s: C READY\n", __func__); + break; + } + udelay(HDMI_PLL_POLL_TIMEOUT_US); + read_count++; + } + + if (read_count == (HDMI_PLL_POLL_MAX_READS << 1)) { + ready_poll = 0; + DEV_DBG("%s: C READY TIMEOUT, TRYING SW CALIBRATION\n", + __func__); + } + + vco_code1 = MDSS_PLL_REG_R(io->pll_base, + QSERDES_COM_PLLCAL_CODE1_STATUS); + vco_code2 = MDSS_PLL_REG_R(io->pll_base, + QSERDES_COM_PLLCAL_CODE2_STATUS); + MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_DEBUG_BUS_SEL, 0x5); + integral_loop = MDSS_PLL_REG_R(io->pll_base, + QSERDES_COM_DEBUG_BUS0); + + if (((ready_poll & 0x1) == 0) || (((ready_poll & 1) == 1) && + (vco_code1 == 0xFF) && ((vco_code2 & 0x3) == 0x1) && + (integral_loop > 0xC0))) { + MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_ATB_SEL1, 0x04); + MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_ATB_SEL2, 0x00); + MDSS_PLL_REG_W(io->phy_base, HDMI_PHY_CFG, 0x17); + udelay(100); + + MDSS_PLL_REG_W(io->phy_base, HDMI_PHY_CFG, 0x11); + udelay(100); + + MDSS_PLL_REG_W(io->phy_base, HDMI_PHY_CFG, 0x19); + } + return rc; +} + +static int hdmi_8996_perform_sw_calibration(struct clk *c, u32 ver) +{ + switch (ver) { + case HDMI_VERSION_8996_V1: + return hdmi_8996_v1_perform_sw_calibration(c); + case HDMI_VERSION_8996_V2: + return hdmi_8996_v2_perform_sw_calibration(c); + } + return 0; +} + +static int hdmi_8996_vco_enable(struct clk *c, u32 ver) +{ + int rc = 0; + struct hdmi_pll_vco_clk *vco = to_hdmi_8996_vco_clk(c); + struct mdss_pll_resources *io = vco->priv; + + MDSS_PLL_REG_W(io->phy_base, HDMI_PHY_CFG, 0x1); + udelay(100); + + MDSS_PLL_REG_W(io->phy_base, HDMI_PHY_CFG, 0x19); + udelay(100); + + rc = hdmi_8996_perform_sw_calibration(c, ver); + if (rc) { + DEV_ERR("%s: software calibration failed\n", __func__); + return rc; + } + + rc = hdmi_8996_pll_lock_status(io); + if (!rc) { + DEV_ERR("%s: PLL not locked\n", __func__); + return rc; + } + + MDSS_PLL_REG_W(io->pll_base + HDMI_TX_L0_BASE_OFFSET, + QSERDES_TX_L0_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, + 0x6F); + MDSS_PLL_REG_W(io->pll_base + HDMI_TX_L1_BASE_OFFSET, + QSERDES_TX_L0_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, + 0x6F); + MDSS_PLL_REG_W(io->pll_base + HDMI_TX_L2_BASE_OFFSET, + QSERDES_TX_L0_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, + 0x6F); + MDSS_PLL_REG_W(io->pll_base + HDMI_TX_L3_BASE_OFFSET, + QSERDES_TX_L0_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, + 0x6F); + + /* Disable SSC */ + MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_SSC_PER1, 0x0); + MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_SSC_PER2, 0x0); + MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_SSC_STEP_SIZE1, 0x0); + MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_SSC_STEP_SIZE2, 0x0); + MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_SSC_EN_CENTER, 0x2); + + rc = hdmi_8996_phy_ready_status(io); + if (!rc) { + DEV_ERR("%s: PHY not READY\n", __func__); + return rc; + } + + /* Restart the retiming buffer */ + MDSS_PLL_REG_W(io->phy_base, HDMI_PHY_CFG, 0x18); + udelay(1); + MDSS_PLL_REG_W(io->phy_base, HDMI_PHY_CFG, 0x19); + + io->pll_on = true; + return 0; +} + +static int hdmi_8996_v1_vco_enable(struct clk *c) +{ + return hdmi_8996_vco_enable(c, HDMI_VERSION_8996_V1); +} + +static int hdmi_8996_v2_vco_enable(struct clk *c) +{ + return hdmi_8996_vco_enable(c, HDMI_VERSION_8996_V2); +} + +static int hdmi_8996_v3_vco_enable(struct clk *c) +{ + return hdmi_8996_vco_enable(c, HDMI_VERSION_8996_V3); +} + +static int hdmi_8996_v3_1p8_vco_enable(struct clk *c) +{ + return hdmi_8996_vco_enable(c, HDMI_VERSION_8996_V3_1_8); +} + +static int hdmi_8996_vco_get_lock_range(struct clk *c, unsigned long pixel_clk) +{ + u32 rng = 64, cmp_cnt = 1024; + u32 coreclk_div = 5, clks_pll_divsel = 2; + u32 vco_freq, vco_ratio, ppm_range; + u64 bclk; + struct hdmi_8996_v3_post_divider pd; + + bclk = ((u64)pixel_clk) * HDMI_BIT_CLK_TO_PIX_CLK_RATIO; + + DEV_DBG("%s: rate=%ld\n", __func__, pixel_clk); + + if (hdmi_8996_v3_get_post_div(&pd, bclk) || + pd.vco_ratio <= 0 || pd.vco_freq <= 0) { + DEV_ERR("%s: couldn't get post div\n", __func__); + return -EINVAL; + } + + do_div(pd.vco_freq, HDMI_KHZ_TO_HZ * HDMI_KHZ_TO_HZ); + + vco_freq = (u32) pd.vco_freq; + vco_ratio = (u32) pd.vco_ratio; + + DEV_DBG("%s: freq %d, ratio %d\n", __func__, + vco_freq, vco_ratio); + + ppm_range = (rng * HDMI_REF_CLOCK) / cmp_cnt; + ppm_range /= vco_freq / vco_ratio; + ppm_range *= coreclk_div * clks_pll_divsel; + + DEV_DBG("%s: ppm range: %d\n", __func__, ppm_range); + + return ppm_range; +} + +static int hdmi_8996_vco_rate_atomic_update(struct clk *c, + unsigned long rate, u32 ver) +{ + struct hdmi_pll_vco_clk *vco = to_hdmi_8996_vco_clk(c); + struct mdss_pll_resources *io = vco->priv; + void __iomem *pll; + struct hdmi_8996_phy_pll_reg_cfg cfg = {0}; + int rc = 0; + + rc = hdmi_8996_calculate(rate, &cfg, ver); + if (rc) { + DEV_ERR("%s: PLL calculation failed\n", __func__); + goto end; + } + + pll = io->pll_base; + + MDSS_PLL_REG_W(pll, QSERDES_COM_DEC_START_MODE0, + cfg.com_dec_start_mode0); + MDSS_PLL_REG_W(pll, QSERDES_COM_DIV_FRAC_START1_MODE0, + cfg.com_div_frac_start1_mode0); + MDSS_PLL_REG_W(pll, QSERDES_COM_DIV_FRAC_START2_MODE0, + cfg.com_div_frac_start2_mode0); + MDSS_PLL_REG_W(pll, QSERDES_COM_DIV_FRAC_START3_MODE0, + cfg.com_div_frac_start3_mode0); + + MDSS_PLL_REG_W(pll, QSERDES_COM_FREQ_UPDATE, 0x01); + MDSS_PLL_REG_W(pll, QSERDES_COM_FREQ_UPDATE, 0x00); + + DEV_DBG("%s: updated to rate %ld\n", __func__, rate); +end: + return rc; +} + +static int hdmi_8996_vco_set_rate(struct clk *c, unsigned long rate, u32 ver) +{ + struct hdmi_pll_vco_clk *vco = to_hdmi_8996_vco_clk(c); + struct mdss_pll_resources *io = vco->priv; + unsigned int set_power_dwn = 0; + bool atomic_update = false; + int rc, pll_lock_range; + + rc = mdss_pll_resource_enable(io, true); + if (rc) { + DEV_ERR("pll resource can't be enabled\n"); + return rc; + } + + DEV_DBG("%s: rate %ld\n", __func__, rate); + + if (MDSS_PLL_REG_R(io->pll_base, QSERDES_COM_C_READY_STATUS) & BIT(0) && + MDSS_PLL_REG_R(io->phy_base, HDMI_PHY_STATUS) & BIT(0)) { + pll_lock_range = hdmi_8996_vco_get_lock_range(c, vco->rate); + + if (pll_lock_range > 0 && vco->rate) { + u32 range_limit; + + range_limit = vco->rate * + (pll_lock_range / HDMI_KHZ_TO_HZ); + range_limit /= HDMI_KHZ_TO_HZ; + + DEV_DBG("%s: range limit %d\n", __func__, range_limit); + + if (abs(rate - vco->rate) < range_limit) + atomic_update = true; + } + } + + if (io->pll_on && !atomic_update) + set_power_dwn = 1; + + if (atomic_update) { + hdmi_8996_vco_rate_atomic_update(c, rate, ver); + } else { + rc = hdmi_8996_phy_pll_set_clk_rate(c, rate, ver); + if (rc) + DEV_ERR("%s: Failed to set clk rate\n", __func__); + } + + mdss_pll_resource_enable(io, false); + + if (set_power_dwn) + hdmi_8996_vco_enable(c, ver); + + vco->rate = rate; + vco->rate_set = true; + + return 0; +} + +static int hdmi_8996_v1_vco_set_rate(struct clk *c, unsigned long rate) +{ + return hdmi_8996_vco_set_rate(c, rate, HDMI_VERSION_8996_V1); +} + +static int hdmi_8996_v2_vco_set_rate(struct clk *c, unsigned long rate) +{ + return hdmi_8996_vco_set_rate(c, rate, HDMI_VERSION_8996_V2); +} + +static int hdmi_8996_v3_vco_set_rate(struct clk *c, unsigned long rate) +{ + return hdmi_8996_vco_set_rate(c, rate, HDMI_VERSION_8996_V3); +} + +static int hdmi_8996_v3_1p8_vco_set_rate(struct clk *c, unsigned long rate) +{ + return hdmi_8996_vco_set_rate(c, rate, HDMI_VERSION_8996_V3_1_8); +} + +static unsigned long hdmi_get_hsclk_sel_divisor(unsigned long hsclk_sel) +{ + unsigned long divisor; + + switch (hsclk_sel) { + case 0: + divisor = 2; + break; + case 1: + divisor = 6; + break; + case 2: + divisor = 10; + break; + case 3: + divisor = 14; + break; + case 4: + divisor = 3; + break; + case 5: + divisor = 9; + break; + case 6: + case 13: + divisor = 15; + break; + case 7: + divisor = 21; + break; + case 8: + divisor = 4; + break; + case 9: + divisor = 12; + break; + case 10: + divisor = 20; + break; + case 11: + divisor = 28; + break; + case 12: + divisor = 5; + break; + case 14: + divisor = 25; + break; + case 15: + divisor = 35; + break; + default: + divisor = 1; + DEV_ERR("%s: invalid hsclk_sel value = %lu", + __func__, hsclk_sel); + break; + } + + return divisor; +} + +static unsigned long hdmi_8996_vco_get_rate(struct clk *c) +{ + unsigned long freq = 0, hsclk_sel = 0, tx_band = 0, dec_start = 0, + div_frac_start = 0, vco_clock_freq = 0; + struct hdmi_pll_vco_clk *vco = to_hdmi_8996_vco_clk(c); + struct mdss_pll_resources *io = vco->priv; + + if (mdss_pll_resource_enable(io, true)) { + DEV_ERR("%s: pll resource can't be enabled\n", __func__); + return freq; + } + + dec_start = MDSS_PLL_REG_R(io->pll_base, QSERDES_COM_DEC_START_MODE0); + + div_frac_start = + MDSS_PLL_REG_R(io->pll_base, + QSERDES_COM_DIV_FRAC_START1_MODE0) | + MDSS_PLL_REG_R(io->pll_base, + QSERDES_COM_DIV_FRAC_START2_MODE0) << 8 | + MDSS_PLL_REG_R(io->pll_base, + QSERDES_COM_DIV_FRAC_START3_MODE0) << 16; + + vco_clock_freq = (dec_start + (div_frac_start / (1 << 20))) + * 4 * (HDMI_REF_CLOCK); + + hsclk_sel = MDSS_PLL_REG_R(io->pll_base, QSERDES_COM_HSCLK_SEL) & 0x15; + hsclk_sel = hdmi_get_hsclk_sel_divisor(hsclk_sel); + tx_band = MDSS_PLL_REG_R(io->pll_base + HDMI_TX_L0_BASE_OFFSET, + QSERDES_TX_L0_TX_BAND) & 0x3; + + freq = vco_clock_freq / (10 * hsclk_sel * (1 << tx_band)); + + mdss_pll_resource_enable(io, false); + + DEV_DBG("%s: freq = %lu\n", __func__, freq); + + return freq; +} + +static long hdmi_8996_vco_round_rate(struct clk *c, unsigned long rate) +{ + unsigned long rrate = rate; + + DEV_DBG("rrate=%ld\n", rrate); + + return rrate; +} + +static int hdmi_8996_vco_prepare(struct clk *c, u32 ver) +{ + struct hdmi_pll_vco_clk *vco = to_hdmi_8996_vco_clk(c); + struct mdss_pll_resources *io = vco->priv; + int ret = 0; + + DEV_DBG("rate=%ld\n", vco->rate); + + if (!vco->rate_set && vco->rate) + ret = hdmi_8996_vco_set_rate(c, vco->rate, ver); + + if (!ret) { + ret = mdss_pll_resource_enable(io, true); + if (ret) + DEV_ERR("pll resource can't be enabled\n"); + } + + return ret; +} + +static int hdmi_8996_v1_vco_prepare(struct clk *c) +{ + return hdmi_8996_vco_prepare(c, HDMI_VERSION_8996_V1); +} + +static int hdmi_8996_v2_vco_prepare(struct clk *c) +{ + return hdmi_8996_vco_prepare(c, HDMI_VERSION_8996_V2); +} + +static int hdmi_8996_v3_vco_prepare(struct clk *c) +{ + return hdmi_8996_vco_prepare(c, HDMI_VERSION_8996_V3); +} + +static int hdmi_8996_v3_1p8_vco_prepare(struct clk *c) +{ + return hdmi_8996_vco_prepare(c, HDMI_VERSION_8996_V3_1_8); +} + +static void hdmi_8996_vco_unprepare(struct clk *c) +{ + struct hdmi_pll_vco_clk *vco = to_hdmi_8996_vco_clk(c); + struct mdss_pll_resources *io = vco->priv; + + vco->rate_set = false; + + if (!io) { + DEV_ERR("Invalid input parameter\n"); + return; + } + + if (!io->pll_on && + mdss_pll_resource_enable(io, true)) { + DEV_ERR("pll resource can't be enabled\n"); + return; + } + + io->handoff_resources = false; + mdss_pll_resource_enable(io, false); + io->pll_on = false; +} + +static enum handoff hdmi_8996_vco_handoff(struct clk *c) +{ + enum handoff ret = HANDOFF_DISABLED_CLK; + struct hdmi_pll_vco_clk *vco = to_hdmi_8996_vco_clk(c); + struct mdss_pll_resources *io = vco->priv; + + if (is_gdsc_disabled(io)) + return HANDOFF_DISABLED_CLK; + + if (mdss_pll_resource_enable(io, true)) { + DEV_ERR("pll resource can't be enabled\n"); + return ret; + } + + io->handoff_resources = true; + + if (MDSS_PLL_REG_R(io->pll_base, QSERDES_COM_C_READY_STATUS) & BIT(0)) { + if (MDSS_PLL_REG_R(io->phy_base, HDMI_PHY_STATUS) & BIT(0)) { + io->pll_on = true; + c->rate = hdmi_8996_vco_get_rate(c); + vco->rate = c->rate; + ret = HANDOFF_ENABLED_CLK; + } else { + io->handoff_resources = false; + mdss_pll_resource_enable(io, false); + DEV_DBG("%s: PHY not ready\n", __func__); + } + } else { + io->handoff_resources = false; + mdss_pll_resource_enable(io, false); + DEV_DBG("%s: PLL not locked\n", __func__); + } + + DEV_DBG("done, ret=%d\n", ret); + return ret; +} + +static struct clk_ops hdmi_8996_v1_vco_clk_ops = { + .enable = hdmi_8996_v1_vco_enable, + .set_rate = hdmi_8996_v1_vco_set_rate, + .get_rate = hdmi_8996_vco_get_rate, + .round_rate = hdmi_8996_vco_round_rate, + .prepare = hdmi_8996_v1_vco_prepare, + .unprepare = hdmi_8996_vco_unprepare, + .handoff = hdmi_8996_vco_handoff, +}; + +static struct clk_ops hdmi_8996_v2_vco_clk_ops = { + .enable = hdmi_8996_v2_vco_enable, + .set_rate = hdmi_8996_v2_vco_set_rate, + .get_rate = hdmi_8996_vco_get_rate, + .round_rate = hdmi_8996_vco_round_rate, + .prepare = hdmi_8996_v2_vco_prepare, + .unprepare = hdmi_8996_vco_unprepare, + .handoff = hdmi_8996_vco_handoff, +}; + +static struct clk_ops hdmi_8996_v3_vco_clk_ops = { + .enable = hdmi_8996_v3_vco_enable, + .set_rate = hdmi_8996_v3_vco_set_rate, + .get_rate = hdmi_8996_vco_get_rate, + .round_rate = hdmi_8996_vco_round_rate, + .prepare = hdmi_8996_v3_vco_prepare, + .unprepare = hdmi_8996_vco_unprepare, + .handoff = hdmi_8996_vco_handoff, +}; + +static struct clk_ops hdmi_8996_v3_1p8_vco_clk_ops = { + .enable = hdmi_8996_v3_1p8_vco_enable, + .set_rate = hdmi_8996_v3_1p8_vco_set_rate, + .get_rate = hdmi_8996_vco_get_rate, + .round_rate = hdmi_8996_vco_round_rate, + .prepare = hdmi_8996_v3_1p8_vco_prepare, + .unprepare = hdmi_8996_vco_unprepare, + .handoff = hdmi_8996_vco_handoff, +}; + + +static struct hdmi_pll_vco_clk hdmi_vco_clk = { + .c = { + .dbg_name = "hdmi_8996_vco_clk", + .ops = &hdmi_8996_v1_vco_clk_ops, + CLK_INIT(hdmi_vco_clk.c), + }, +}; + +static struct clk_lookup hdmipllcc_8996[] = { + CLK_LIST(hdmi_vco_clk), +}; + +int hdmi_8996_pll_clock_register(struct platform_device *pdev, + struct mdss_pll_resources *pll_res, u32 ver) +{ + int rc = -ENOTSUPP; + if (!pll_res || !pll_res->phy_base || !pll_res->pll_base) { + DEV_ERR("%s: Invalid input parameters\n", __func__); + return -EPROBE_DEFER; + } + + /* Set client data for vco, mux and div clocks */ + hdmi_vco_clk.priv = pll_res; + + switch (ver) { + case HDMI_VERSION_8996_V2: + hdmi_vco_clk.c.ops = &hdmi_8996_v2_vco_clk_ops; + break; + case HDMI_VERSION_8996_V3: + hdmi_vco_clk.c.ops = &hdmi_8996_v3_vco_clk_ops; + break; + case HDMI_VERSION_8996_V3_1_8: + hdmi_vco_clk.c.ops = &hdmi_8996_v3_1p8_vco_clk_ops; + break; + default: + hdmi_vco_clk.c.ops = &hdmi_8996_v1_vco_clk_ops; + break; + }; + + rc = of_msm_clock_register(pdev->dev.of_node, hdmipllcc_8996, + ARRAY_SIZE(hdmipllcc_8996)); + if (rc) { + DEV_ERR("%s: Clock register failed rc=%d\n", __func__, rc); + rc = -EPROBE_DEFER; + } else { + DEV_DBG("%s SUCCESS\n", __func__); + } + + return rc; +} + +int hdmi_8996_v1_pll_clock_register(struct platform_device *pdev, + struct mdss_pll_resources *pll_res) +{ + return hdmi_8996_pll_clock_register(pdev, pll_res, + HDMI_VERSION_8996_V1); +} + +int hdmi_8996_v2_pll_clock_register(struct platform_device *pdev, + struct mdss_pll_resources *pll_res) +{ + return hdmi_8996_pll_clock_register(pdev, pll_res, + HDMI_VERSION_8996_V2); +} + +int hdmi_8996_v3_pll_clock_register(struct platform_device *pdev, + struct mdss_pll_resources *pll_res) +{ + return hdmi_8996_pll_clock_register(pdev, pll_res, + HDMI_VERSION_8996_V3); +} + +int hdmi_8996_v3_1p8_pll_clock_register(struct platform_device *pdev, + struct mdss_pll_resources *pll_res) +{ + return hdmi_8996_pll_clock_register(pdev, pll_res, + HDMI_VERSION_8996_V3_1_8); +} diff -Nruw linux-4.4.115-fbx/drivers/clk/msm./mdss/mdss-hdmi-pll-8998.c linux-4.4.115-fbx/drivers/clk/msm/mdss/mdss-hdmi-pll-8998.c --- linux-4.4.115-fbx/drivers/clk/msm./mdss/mdss-hdmi-pll-8998.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-4.4.115-fbx/drivers/clk/msm/mdss/mdss-hdmi-pll-8998.c 2019-01-22 16:16:23.023242060 +0100 @@ -0,0 +1,1054 @@ +/* Copyright (c) 2016-2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#define pr_fmt(fmt) "%s: " fmt, __func__ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "mdss-pll.h" +#include "mdss-hdmi-pll.h" + +#define _W(x, y, z) MDSS_PLL_REG_W(x, y, z) +#define _R(x, y) MDSS_PLL_REG_R(x, y) + +/* CONSTANTS */ +#define HDMI_VERSION_8998_3_3 1 +#define HDMI_VERSION_8998_1_8 2 + +/* PLL REGISTERS */ +#define FREQ_UPDATE (0x008) +#define BIAS_EN_CLKBUFLR_EN (0x034) +#define CLK_ENABLE1 (0x038) +#define SYS_CLK_CTRL (0x03C) +#define SYSCLK_BUF_ENABLE (0x040) +#define PLL_IVCO (0x048) +#define CP_CTRL_MODE0 (0x060) +#define PLL_RCTRL_MODE0 (0x068) +#define PLL_CCTRL_MODE0 (0x070) +#define SYSCLK_EN_SEL (0x080) +#define RESETSM_CNTRL (0x088) +#define LOCK_CMP_EN (0x090) +#define LOCK_CMP1_MODE0 (0x098) +#define LOCK_CMP2_MODE0 (0x09C) +#define LOCK_CMP3_MODE0 (0x0A0) +#define DEC_START_MODE0 (0x0B0) +#define DIV_FRAC_START1_MODE0 (0x0B8) +#define DIV_FRAC_START2_MODE0 (0x0BC) +#define DIV_FRAC_START3_MODE0 (0x0C0) +#define INTEGLOOP_GAIN0_MODE0 (0x0D8) +#define INTEGLOOP_GAIN1_MODE0 (0x0DC) +#define VCO_TUNE_CTRL (0x0EC) +#define VCO_TUNE_MAP (0x0F0) +#define CLK_SELECT (0x138) +#define HSCLK_SEL (0x13C) +#define CORECLK_DIV_MODE0 (0x148) +#define CORE_CLK_EN (0x154) +#define C_READY_STATUS (0x158) +#define SVS_MODE_CLK_SEL (0x164) + +/* Tx Channel PHY registers */ +#define PHY_TX_EMP_POST1_LVL(n) ((((n) * 0x200) + 0x400) + 0x000) +#define PHY_TX_INTERFACE_SELECT_TX_BAND(n) ((((n) * 0x200) + 0x400) + 0x008) +#define PHY_TX_CLKBUF_TERM_ENABLE(n) ((((n) * 0x200) + 0x400) + 0x00C) +#define PHY_TX_DRV_LVL_RES_CODE_OFFSET(n) ((((n) * 0x200) + 0x400) + 0x014) +#define PHY_TX_DRV_LVL(n) ((((n) * 0x200) + 0x400) + 0x018) +#define PHY_TX_LANE_CONFIG(n) ((((n) * 0x200) + 0x400) + 0x01C) +#define PHY_TX_PRE_DRIVER_1(n) ((((n) * 0x200) + 0x400) + 0x024) +#define PHY_TX_PRE_DRIVER_2(n) ((((n) * 0x200) + 0x400) + 0x028) +#define PHY_TX_LANE_MODE(n) ((((n) * 0x200) + 0x400) + 0x02C) + +/* HDMI PHY registers */ +#define PHY_CFG (0x00) +#define PHY_PD_CTL (0x04) +#define PHY_MODE (0x10) +#define PHY_CLOCK (0x5C) +#define PHY_CMN_CTRL (0x68) +#define PHY_STATUS (0xB4) + +#define HDMI_VCO_MAX_FREQ 12000000000 +#define HDMI_VCO_MIN_FREQ 8000000000 +#define HDMI_BIT_CLK_TO_PIX_CLK_RATIO 10 +#define HDMI_MHZ_TO_HZ 1000000 +#define HDMI_HZ_TO_MHZ 1000000 +#define HDMI_KHZ_TO_HZ 1000 +#define HDMI_REF_CLOCK_MHZ 19.2 +#define HDMI_REF_CLOCK_HZ (HDMI_REF_CLOCK_MHZ * 1000000) +#define HDMI_VCO_MIN_RATE_HZ 25000000 +#define HDMI_VCO_MAX_RATE_HZ 600000000 + +struct hdmi_8998_reg_cfg { + u32 tx_band; + u32 svs_mode_clk_sel; + u32 hsclk_sel; + u32 lock_cmp_en; + u32 cctrl_mode0; + u32 rctrl_mode0; + u32 cpctrl_mode0; + u32 dec_start_mode0; + u32 div_frac_start1_mode0; + u32 div_frac_start2_mode0; + u32 div_frac_start3_mode0; + u32 integloop_gain0_mode0; + u32 integloop_gain1_mode0; + u32 lock_cmp1_mode0; + u32 lock_cmp2_mode0; + u32 lock_cmp3_mode0; + u32 ssc_per1; + u32 ssc_per2; + u32 ssc_step_size1; + u32 ssc_step_size2; + u32 core_clk_en; + u32 coreclk_div_mode0; + u32 phy_mode; + u64 vco_freq; + u32 hsclk_divsel; + u32 vco_ratio; + u32 ssc_en_center; + + u32 l0_tx_drv_lvl; + u32 l0_tx_emp_post1_lvl; + u32 l1_tx_drv_lvl; + u32 l1_tx_emp_post1_lvl; + u32 l2_tx_drv_lvl; + u32 l2_tx_emp_post1_lvl; + u32 l3_tx_drv_lvl; + u32 l3_tx_emp_post1_lvl; + + u32 l0_pre_driver_1; + u32 l0_pre_driver_2; + u32 l1_pre_driver_1; + u32 l1_pre_driver_2; + u32 l2_pre_driver_1; + u32 l2_pre_driver_2; + u32 l3_pre_driver_1; + u32 l3_pre_driver_2; + + u32 l0_res_code_offset; + u32 l1_res_code_offset; + u32 l2_res_code_offset; + u32 l3_res_code_offset; + + bool debug; +}; + +static void hdmi_8998_get_div(struct hdmi_8998_reg_cfg *cfg, unsigned long pclk) +{ + u32 const ratio_list[] = {1, 2, 3, 4, 5, 6, + 9, 10, 12, 15, 25}; + u32 const band_list[] = {0, 1, 2, 3}; + u32 const sz_ratio = ARRAY_SIZE(ratio_list); + u32 const sz_band = ARRAY_SIZE(band_list); + u32 const cmp_cnt = 1024; + u32 const th_min = 500, th_max = 1000; + u32 half_rate_mode = 0; + u32 list_elements; + int optimal_index; + u32 i, j, k; + u32 found_hsclk_divsel = 0, found_vco_ratio; + u32 found_tx_band_sel; + u64 const min_freq = HDMI_VCO_MIN_FREQ, max_freq = HDMI_VCO_MAX_FREQ; + u64 const bit_clk = ((u64)pclk) * HDMI_BIT_CLK_TO_PIX_CLK_RATIO; + u64 freq_list[sz_ratio * sz_band]; + u64 found_vco_freq; + u64 freq_optimal; + +find_optimal_index: + freq_optimal = max_freq; + optimal_index = -1; + list_elements = 0; + + for (i = 0; i < sz_ratio; i++) { + for (j = 0; j < sz_band; j++) { + u64 freq = div_u64(bit_clk, (1 << half_rate_mode)); + + freq *= (ratio_list[i] * (1 << band_list[j])); + freq_list[list_elements++] = freq; + } + } + + for (k = 0; k < ARRAY_SIZE(freq_list); k++) { + u32 const clks_pll_div = 2, core_clk_div = 5; + u32 const rng1 = 16, rng2 = 8; + u32 th1, th2; + u64 core_clk, rvar1, rem; + + core_clk = (((freq_list[k] / + ratio_list[k / sz_band]) / + clks_pll_div) / core_clk_div); + + rvar1 = HDMI_REF_CLOCK_HZ * rng1 * HDMI_MHZ_TO_HZ; + rvar1 = div64_u64_rem(rvar1, (cmp_cnt * core_clk), &rem); + if (rem > ((cmp_cnt * core_clk) >> 1)) + rvar1++; + th1 = rvar1; + + rvar1 = HDMI_REF_CLOCK_HZ * rng2 * HDMI_MHZ_TO_HZ; + rvar1 = div64_u64_rem(rvar1, (cmp_cnt * core_clk), &rem); + if (rem > ((cmp_cnt * core_clk) >> 1)) + rvar1++; + th2 = rvar1; + + if (freq_list[k] >= min_freq && + freq_list[k] <= max_freq) { + if ((th1 >= th_min && th1 <= th_max) || + (th2 >= th_min && th2 <= th_max)) { + if (freq_list[k] <= freq_optimal) { + freq_optimal = freq_list[k]; + optimal_index = k; + } + } + } + } + + if (optimal_index == -1) { + if (!half_rate_mode) { + half_rate_mode = 1; + goto find_optimal_index; + } else { + /* set to default values */ + found_vco_freq = max_freq; + found_hsclk_divsel = 0; + found_vco_ratio = 2; + found_tx_band_sel = 0; + pr_err("Config error for pclk %ld\n", pclk); + } + } else { + found_vco_ratio = ratio_list[optimal_index / sz_band]; + found_tx_band_sel = band_list[optimal_index % sz_band]; + found_vco_freq = freq_optimal; + } + + switch (found_vco_ratio) { + case 1: + found_hsclk_divsel = 15; + break; + case 2: + found_hsclk_divsel = 0; + break; + case 3: + found_hsclk_divsel = 4; + break; + case 4: + found_hsclk_divsel = 8; + break; + case 5: + found_hsclk_divsel = 12; + break; + case 6: + found_hsclk_divsel = 1; + break; + case 9: + found_hsclk_divsel = 5; + break; + case 10: + found_hsclk_divsel = 2; + break; + case 12: + found_hsclk_divsel = 9; + break; + case 15: + found_hsclk_divsel = 13; + break; + case 25: + found_hsclk_divsel = 14; + break; + }; + + pr_debug("found_vco_freq=%llu\n", found_vco_freq); + pr_debug("found_hsclk_divsel=%d\n", found_hsclk_divsel); + pr_debug("found_vco_ratio=%d\n", found_vco_ratio); + pr_debug("found_tx_band_sel=%d\n", found_tx_band_sel); + pr_debug("half_rate_mode=%d\n", half_rate_mode); + pr_debug("optimal_index=%d\n", optimal_index); + + cfg->vco_freq = found_vco_freq; + cfg->hsclk_divsel = found_hsclk_divsel; + cfg->vco_ratio = found_vco_ratio; + cfg->tx_band = found_tx_band_sel; +} + +static int hdmi_8998_config_phy(unsigned long rate, + struct hdmi_8998_reg_cfg *cfg, u32 ver) +{ + u64 const high_freq_bit_clk_threshold = 3400000000UL; + u64 const dig_freq_bit_clk_threshold = 1500000000UL; + u64 const mid_freq_bit_clk_threshold = 750000000; + int rc = 0; + u64 fdata, tmds_clk; + u32 pll_div = 4 * HDMI_REF_CLOCK_HZ; + u64 bclk; + u64 vco_freq; + u64 hsclk_sel, dec_start, div_frac_start; + u64 rem; + u64 cpctrl, rctrl, cctrl; + u64 integloop_gain; + u32 digclk_divsel; + u32 tmds_bclk_ratio; + u64 cmp_rng, cmp_cnt = 1024, pll_cmp; + bool gen_ssc = false; + + bclk = rate * HDMI_BIT_CLK_TO_PIX_CLK_RATIO; + + if (bclk > high_freq_bit_clk_threshold) { + tmds_clk = rate / 4; + tmds_bclk_ratio = 1; + } else { + tmds_clk = rate; + tmds_bclk_ratio = 0; + } + + hdmi_8998_get_div(cfg, rate); + + vco_freq = cfg->vco_freq; + fdata = cfg->vco_freq; + do_div(fdata, cfg->vco_ratio); + + hsclk_sel = cfg->hsclk_divsel; + dec_start = vco_freq; + do_div(dec_start, pll_div); + + div_frac_start = vco_freq * (1 << 20); + rem = do_div(div_frac_start, pll_div); + div_frac_start -= (dec_start * (1 << 20)); + if (rem > (pll_div >> 1)) + div_frac_start++; + + if ((div_frac_start != 0) || (gen_ssc == true)) { + cpctrl = 0x8; + rctrl = 0x16; + cctrl = 0x34; + } else { + cpctrl = 0x30; + rctrl = 0x18; + cctrl = 0x2; + } + + digclk_divsel = (bclk > dig_freq_bit_clk_threshold) ? 0x1 : 0x2; + + integloop_gain = ((div_frac_start != 0) || + (gen_ssc == true)) ? 0x3F : 0xC4; + integloop_gain <<= (digclk_divsel == 2 ? 1 : 0); + integloop_gain = (integloop_gain <= 2046 ? integloop_gain : 0x7FE); + + cmp_rng = gen_ssc ? 0x40 : 0x10; + + pll_cmp = cmp_cnt * fdata; + rem = do_div(pll_cmp, (u32)(HDMI_REF_CLOCK_HZ * 10)); + if (rem > ((u64)(HDMI_REF_CLOCK_HZ * 10) >> 1)) + pll_cmp++; + + pll_cmp = pll_cmp - 1; + + pr_debug("VCO_FREQ = %llu\n", cfg->vco_freq); + pr_debug("FDATA = %llu\n", fdata); + pr_debug("DEC_START = %llu\n", dec_start); + pr_debug("DIV_FRAC_START = %llu\n", div_frac_start); + pr_debug("CPCTRL = %llu\n", cpctrl); + pr_debug("RCTRL = %llu\n", rctrl); + pr_debug("CCTRL = %llu\n", cctrl); + pr_debug("DIGCLK_DIVSEL = %u\n", digclk_divsel); + pr_debug("INTEGLOOP_GAIN = %llu\n", integloop_gain); + pr_debug("CMP_RNG = %llu\n", cmp_rng); + pr_debug("PLL_CMP = %llu\n", pll_cmp); + pr_debug("VER=%d\n", ver); + + cfg->svs_mode_clk_sel = (digclk_divsel & 0xFF); + cfg->hsclk_sel = (0x20 | hsclk_sel); + cfg->lock_cmp_en = (gen_ssc ? 0x4 : 0x0); + cfg->cctrl_mode0 = (cctrl & 0xFF); + cfg->rctrl_mode0 = (rctrl & 0xFF); + cfg->cpctrl_mode0 = (cpctrl & 0xFF); + cfg->dec_start_mode0 = (dec_start & 0xFF); + cfg->div_frac_start1_mode0 = (div_frac_start & 0xFF); + cfg->div_frac_start2_mode0 = ((div_frac_start & 0xFF00) >> 8); + cfg->div_frac_start3_mode0 = ((div_frac_start & 0xF0000) >> 16); + cfg->integloop_gain0_mode0 = (integloop_gain & 0xFF); + cfg->integloop_gain1_mode0 = (integloop_gain & 0xF00) >> 8; + cfg->lock_cmp1_mode0 = (pll_cmp & 0xFF); + cfg->lock_cmp2_mode0 = ((pll_cmp & 0xFF00) >> 8); + cfg->lock_cmp3_mode0 = ((pll_cmp & 0x30000) >> 16); + cfg->ssc_per1 = 0; + cfg->ssc_per2 = 0; + cfg->ssc_step_size1 = 0; + cfg->ssc_step_size2 = 0; + cfg->core_clk_en = 0x2C; + cfg->coreclk_div_mode0 = 0x5; + cfg->phy_mode = (tmds_bclk_ratio ? 0x5 : 0x4); + /* V1P8_SEL */ + if (ver == HDMI_VERSION_8998_1_8) + cfg->phy_mode |= 1 << 4; + cfg->ssc_en_center = 0x0; + + if (ver == HDMI_VERSION_8998_3_3) { + if (bclk > high_freq_bit_clk_threshold) { + cfg->l0_tx_drv_lvl = 0xf; + cfg->l0_tx_emp_post1_lvl = 0x3; + cfg->l1_tx_drv_lvl = 0xf; + cfg->l1_tx_emp_post1_lvl = 0x2; + cfg->l2_tx_drv_lvl = 0xf; + cfg->l2_tx_emp_post1_lvl = 0x3; + cfg->l3_tx_drv_lvl = 0xf; + cfg->l3_tx_emp_post1_lvl = 0x0; + cfg->l0_pre_driver_1 = 0x0; + cfg->l0_pre_driver_2 = 0x1C; + cfg->l1_pre_driver_1 = 0x0; + cfg->l1_pre_driver_2 = 0x1C; + cfg->l2_pre_driver_1 = 0x0; + cfg->l2_pre_driver_2 = 0x1C; + cfg->l3_pre_driver_1 = 0x0; + cfg->l3_pre_driver_2 = 0x0; + cfg->l0_res_code_offset = 0x3; + cfg->l1_res_code_offset = 0x0; + cfg->l2_res_code_offset = 0x0; + cfg->l3_res_code_offset = 0x3; + } else if (bclk > dig_freq_bit_clk_threshold) { + cfg->l0_tx_drv_lvl = 0xf; + cfg->l0_tx_emp_post1_lvl = 0x3; + cfg->l1_tx_drv_lvl = 0xf; + cfg->l1_tx_emp_post1_lvl = 0x3; + cfg->l2_tx_drv_lvl = 0xf; + cfg->l2_tx_emp_post1_lvl = 0x3; + cfg->l3_tx_drv_lvl = 0xf; + cfg->l3_tx_emp_post1_lvl = 0x0; + cfg->l0_pre_driver_1 = 0x0; + cfg->l0_pre_driver_2 = 0x16; + cfg->l1_pre_driver_1 = 0x0; + cfg->l1_pre_driver_2 = 0x16; + cfg->l2_pre_driver_1 = 0x0; + cfg->l2_pre_driver_2 = 0x16; + cfg->l3_pre_driver_1 = 0x0; + cfg->l3_pre_driver_2 = 0x18; + cfg->l0_res_code_offset = 0x3; + cfg->l1_res_code_offset = 0x0; + cfg->l2_res_code_offset = 0x0; + cfg->l3_res_code_offset = 0x0; + } else if (bclk > mid_freq_bit_clk_threshold) { + cfg->l0_tx_drv_lvl = 0xf; + cfg->l0_tx_emp_post1_lvl = 0x5; + cfg->l1_tx_drv_lvl = 0xf; + cfg->l1_tx_emp_post1_lvl = 0x5; + cfg->l2_tx_drv_lvl = 0xf; + cfg->l2_tx_emp_post1_lvl = 0x5; + cfg->l3_tx_drv_lvl = 0xf; + cfg->l3_tx_emp_post1_lvl = 0x0; + cfg->l0_pre_driver_1 = 0x0; + cfg->l0_pre_driver_2 = 0x0E; + cfg->l1_pre_driver_1 = 0x0; + cfg->l1_pre_driver_2 = 0x0E; + cfg->l2_pre_driver_1 = 0x0; + cfg->l2_pre_driver_2 = 0x0E; + cfg->l3_pre_driver_1 = 0x0; + cfg->l3_pre_driver_2 = 0x0E; + cfg->l0_res_code_offset = 0x0; + cfg->l1_res_code_offset = 0x0; + cfg->l2_res_code_offset = 0x0; + cfg->l3_res_code_offset = 0x0; + } else { + cfg->l0_tx_drv_lvl = 0x1; + cfg->l0_tx_emp_post1_lvl = 0x0; + cfg->l1_tx_drv_lvl = 0x1; + cfg->l1_tx_emp_post1_lvl = 0x0; + cfg->l2_tx_drv_lvl = 0x1; + cfg->l2_tx_emp_post1_lvl = 0x0; + cfg->l3_tx_drv_lvl = 0x0; + cfg->l3_tx_emp_post1_lvl = 0x0; + cfg->l0_pre_driver_1 = 0x0; + cfg->l0_pre_driver_2 = 0x16; + cfg->l1_pre_driver_1 = 0x0; + cfg->l1_pre_driver_2 = 0x16; + cfg->l2_pre_driver_1 = 0x0; + cfg->l2_pre_driver_2 = 0x16; + cfg->l3_pre_driver_1 = 0x0; + cfg->l3_pre_driver_2 = 0x18; + cfg->l0_res_code_offset = 0x0; + cfg->l1_res_code_offset = 0x0; + cfg->l2_res_code_offset = 0x0; + cfg->l3_res_code_offset = 0x0; + } + } else { + cfg->l0_tx_drv_lvl = 0xF; + cfg->l0_tx_emp_post1_lvl = 0x5; + cfg->l1_tx_drv_lvl = 0xF; + cfg->l1_tx_emp_post1_lvl = 0x2; + cfg->l2_tx_drv_lvl = 0xF; + cfg->l2_tx_emp_post1_lvl = 0x2; + cfg->l3_tx_drv_lvl = 0xF; + cfg->l3_tx_emp_post1_lvl = 0x0; + cfg->l0_pre_driver_1 = 0x0; + cfg->l0_pre_driver_2 = 0x1E; + cfg->l1_pre_driver_1 = 0x0; + cfg->l1_pre_driver_2 = 0x1E; + cfg->l2_pre_driver_1 = 0x0; + cfg->l2_pre_driver_2 = 0x1E; + cfg->l3_pre_driver_1 = 0x0; + cfg->l3_pre_driver_2 = 0x10; + cfg->l0_res_code_offset = 0x3; + cfg->l1_res_code_offset = 0x0; + cfg->l2_res_code_offset = 0x0; + cfg->l3_res_code_offset = 0x3; + } + + return rc; +} + +static int hdmi_8998_pll_set_clk_rate(struct clk *c, unsigned long rate, + u32 ver) +{ + int rc = 0; + struct hdmi_pll_vco_clk *vco = to_hdmi_vco_clk(c); + struct mdss_pll_resources *io = vco->priv; + struct hdmi_8998_reg_cfg cfg = {0}; + void __iomem *phy = io->phy_base, *pll = io->pll_base; + + rc = hdmi_8998_config_phy(rate, &cfg, ver); + if (rc) { + pr_err("rate calculation failed\n, rc=%d", rc); + return rc; + } + + _W(phy, PHY_PD_CTL, 0x0); + udelay(500); + + _W(phy, PHY_PD_CTL, 0x1); + _W(pll, RESETSM_CNTRL, 0x20); + _W(phy, PHY_CMN_CTRL, 0x6); + _W(pll, PHY_TX_INTERFACE_SELECT_TX_BAND(0), cfg.tx_band); + _W(pll, PHY_TX_INTERFACE_SELECT_TX_BAND(1), cfg.tx_band); + _W(pll, PHY_TX_INTERFACE_SELECT_TX_BAND(2), cfg.tx_band); + _W(pll, PHY_TX_INTERFACE_SELECT_TX_BAND(3), cfg.tx_band); + _W(pll, PHY_TX_CLKBUF_TERM_ENABLE(0), 0x1); + _W(pll, PHY_TX_LANE_MODE(0), 0x20); + _W(pll, PHY_TX_LANE_MODE(1), 0x20); + _W(pll, PHY_TX_LANE_MODE(2), 0x20); + _W(pll, PHY_TX_LANE_MODE(3), 0x20); + _W(pll, PHY_TX_CLKBUF_TERM_ENABLE(1), 0x1); + _W(pll, PHY_TX_CLKBUF_TERM_ENABLE(2), 0x1); + _W(pll, PHY_TX_CLKBUF_TERM_ENABLE(3), 0x1); + _W(pll, SYSCLK_BUF_ENABLE, 0x2); + _W(pll, BIAS_EN_CLKBUFLR_EN, 0xB); + _W(pll, SYSCLK_EN_SEL, 0x37); + _W(pll, SYS_CLK_CTRL, 0x2); + _W(pll, CLK_ENABLE1, 0xE); + _W(pll, PLL_IVCO, 0x7); + _W(pll, VCO_TUNE_CTRL, 0x0); + _W(pll, SVS_MODE_CLK_SEL, cfg.svs_mode_clk_sel); + _W(pll, CLK_SELECT, 0x30); + _W(pll, HSCLK_SEL, cfg.hsclk_sel); + _W(pll, LOCK_CMP_EN, cfg.lock_cmp_en); + _W(pll, PLL_CCTRL_MODE0, cfg.cctrl_mode0); + _W(pll, PLL_RCTRL_MODE0, cfg.rctrl_mode0); + _W(pll, CP_CTRL_MODE0, cfg.cpctrl_mode0); + _W(pll, DEC_START_MODE0, cfg.dec_start_mode0); + _W(pll, DIV_FRAC_START1_MODE0, cfg.div_frac_start1_mode0); + _W(pll, DIV_FRAC_START2_MODE0, cfg.div_frac_start2_mode0); + _W(pll, DIV_FRAC_START3_MODE0, cfg.div_frac_start3_mode0); + _W(pll, INTEGLOOP_GAIN0_MODE0, cfg.integloop_gain0_mode0); + _W(pll, INTEGLOOP_GAIN1_MODE0, cfg.integloop_gain1_mode0); + _W(pll, LOCK_CMP1_MODE0, cfg.lock_cmp1_mode0); + _W(pll, LOCK_CMP2_MODE0, cfg.lock_cmp2_mode0); + _W(pll, LOCK_CMP3_MODE0, cfg.lock_cmp3_mode0); + _W(pll, VCO_TUNE_MAP, 0x0); + _W(pll, CORE_CLK_EN, cfg.core_clk_en); + _W(pll, CORECLK_DIV_MODE0, cfg.coreclk_div_mode0); + + _W(pll, PHY_TX_DRV_LVL(0), cfg.l0_tx_drv_lvl); + _W(pll, PHY_TX_DRV_LVL(1), cfg.l1_tx_drv_lvl); + _W(pll, PHY_TX_DRV_LVL(2), cfg.l2_tx_drv_lvl); + _W(pll, PHY_TX_DRV_LVL(3), cfg.l3_tx_drv_lvl); + + _W(pll, PHY_TX_EMP_POST1_LVL(0), cfg.l0_tx_emp_post1_lvl); + _W(pll, PHY_TX_EMP_POST1_LVL(1), cfg.l1_tx_emp_post1_lvl); + _W(pll, PHY_TX_EMP_POST1_LVL(2), cfg.l2_tx_emp_post1_lvl); + _W(pll, PHY_TX_EMP_POST1_LVL(3), cfg.l3_tx_emp_post1_lvl); + + _W(pll, PHY_TX_PRE_DRIVER_1(0), cfg.l0_pre_driver_1); + _W(pll, PHY_TX_PRE_DRIVER_1(1), cfg.l1_pre_driver_1); + _W(pll, PHY_TX_PRE_DRIVER_1(2), cfg.l2_pre_driver_1); + _W(pll, PHY_TX_PRE_DRIVER_1(3), cfg.l3_pre_driver_1); + + _W(pll, PHY_TX_PRE_DRIVER_2(0), cfg.l0_pre_driver_2); + _W(pll, PHY_TX_PRE_DRIVER_2(1), cfg.l1_pre_driver_2); + _W(pll, PHY_TX_PRE_DRIVER_2(2), cfg.l2_pre_driver_2); + _W(pll, PHY_TX_PRE_DRIVER_2(3), cfg.l3_pre_driver_2); + + _W(pll, PHY_TX_DRV_LVL_RES_CODE_OFFSET(0), cfg.l0_res_code_offset); + _W(pll, PHY_TX_DRV_LVL_RES_CODE_OFFSET(1), cfg.l1_res_code_offset); + _W(pll, PHY_TX_DRV_LVL_RES_CODE_OFFSET(2), cfg.l2_res_code_offset); + _W(pll, PHY_TX_DRV_LVL_RES_CODE_OFFSET(3), cfg.l3_res_code_offset); + + _W(phy, PHY_MODE, cfg.phy_mode); + + _W(pll, PHY_TX_LANE_CONFIG(0), 0x10); + _W(pll, PHY_TX_LANE_CONFIG(1), 0x10); + _W(pll, PHY_TX_LANE_CONFIG(2), 0x10); + _W(pll, PHY_TX_LANE_CONFIG(3), 0x10); + + /* Ensure all registers are flushed to hardware */ + wmb(); + + return 0; +} + +static int hdmi_8998_pll_lock_status(struct mdss_pll_resources *io) +{ + u32 const delay_us = 100; + u32 const timeout_us = 5000; + u32 status; + int rc = 0; + void __iomem *pll = io->pll_base; + + rc = mdss_pll_resource_enable(io, true); + if (rc) { + pr_err("pll resource can't be enabled\n"); + return rc; + } + rc = readl_poll_timeout_atomic(pll + C_READY_STATUS, + status, + ((status & BIT(0)) > 0), + delay_us, + timeout_us); + if (rc) + pr_err("HDMI PLL(%d) lock failed, status=0x%08x\n", + io->index, status); + else + pr_debug("HDMI PLL(%d) lock passed, status=0x%08x\n", + io->index, status); + + mdss_pll_resource_enable(io, false); + + return rc; +} + +static int hdmi_8998_phy_ready_status(struct mdss_pll_resources *io) +{ + u32 const delay_us = 100; + u32 const timeout_us = 5000; + u32 status; + int rc = 0; + void __iomem *phy = io->phy_base; + + rc = mdss_pll_resource_enable(io, true); + if (rc) { + pr_err("pll resource can't be enabled\n"); + return rc; + } + + rc = readl_poll_timeout_atomic(phy + PHY_STATUS, + status, + ((status & BIT(0)) > 0), + delay_us, + timeout_us); + if (rc) + pr_err("HDMI PHY(%d) not ready, status=0x%08x\n", + io->index, status); + else + pr_debug("HDMI PHY(%d) ready, status=0x%08x\n", + io->index, status); + + mdss_pll_resource_enable(io, false); + + return rc; +} + +static int hdmi_8998_pll_enable(struct clk *c) +{ + int rc = 0; + struct hdmi_pll_vco_clk *vco = to_hdmi_vco_clk(c); + struct mdss_pll_resources *io = vco->priv; + void __iomem *phy = io->phy_base, *pll = io->pll_base; + + _W(phy, PHY_CFG, 0x1); + udelay(100); + _W(phy, PHY_CFG, 0x59); + udelay(100); + + /* Ensure all registers are flushed to hardware */ + wmb(); + + rc = hdmi_8998_pll_lock_status(io); + if (rc) { + pr_err("PLL not locked, rc=%d\n", rc); + return rc; + } + + _W(pll, PHY_TX_LANE_CONFIG(0), 0x1F); + _W(pll, PHY_TX_LANE_CONFIG(1), 0x1F); + _W(pll, PHY_TX_LANE_CONFIG(2), 0x1F); + _W(pll, PHY_TX_LANE_CONFIG(3), 0x1F); + + /* Ensure all registers are flushed to hardware */ + wmb(); + + rc = hdmi_8998_phy_ready_status(io); + if (rc) { + pr_err("PHY NOT READY, rc=%d\n", rc); + return rc; + } + + _W(phy, PHY_CFG, 0x58); + udelay(1); + _W(phy, PHY_CFG, 0x59); + + /* Ensure all registers are flushed to hardware */ + wmb(); + + io->pll_on = true; + return rc; +} + +/* + * Get the clock range allowed in atomic update. If clock rate + * goes beyond this range, a full tear down is required to set + * the new pixel clock. + */ +static int hdmi_8998_vco_get_lock_range(struct clk *c, + unsigned long pixel_clk) +{ + const u32 rng = 64, cmp_cnt = 1024; + const u32 coreclk_div = 5, clks_pll_divsel = 2; + u32 vco_freq, vco_ratio, ppm_range; + struct hdmi_8998_reg_cfg cfg = {0}; + + pr_debug("rate=%ld\n", pixel_clk); + + hdmi_8998_get_div(&cfg, pixel_clk); + if (cfg.vco_ratio <= 0 || cfg.vco_freq <= 0) { + pr_err("couldn't get post div\n"); + return -EINVAL; + } + + do_div(cfg.vco_freq, HDMI_KHZ_TO_HZ * HDMI_KHZ_TO_HZ); + + vco_freq = (u32) cfg.vco_freq; + vco_ratio = (u32) cfg.vco_ratio; + + pr_debug("freq %d, ratio %d\n", vco_freq, vco_ratio); + + ppm_range = (rng * HDMI_REF_CLOCK_HZ) / cmp_cnt; + ppm_range /= vco_freq / vco_ratio; + ppm_range *= coreclk_div * clks_pll_divsel; + + pr_debug("ppm range: %d\n", ppm_range); + + return ppm_range; +} + +static int hdmi_8998_vco_rate_atomic_update(struct clk *c, + unsigned long rate, u32 ver) +{ + struct hdmi_pll_vco_clk *vco = to_hdmi_vco_clk(c); + struct mdss_pll_resources *io = vco->priv; + void __iomem *pll; + struct hdmi_8998_reg_cfg cfg = {0}; + int rc = 0; + + rc = hdmi_8998_config_phy(rate, &cfg, ver); + if (rc) { + pr_err("rate calculation failed\n, rc=%d", rc); + goto end; + } + + pll = io->pll_base; + + _W(pll, DEC_START_MODE0, cfg.dec_start_mode0); + _W(pll, DIV_FRAC_START1_MODE0, cfg.div_frac_start1_mode0); + _W(pll, DIV_FRAC_START2_MODE0, cfg.div_frac_start2_mode0); + _W(pll, DIV_FRAC_START3_MODE0, cfg.div_frac_start3_mode0); + + _W(pll, FREQ_UPDATE, 0x01); + _W(pll, FREQ_UPDATE, 0x00); + + pr_debug("updated to rate %ld\n", rate); +end: + return rc; +} + +static int hdmi_8998_vco_set_rate(struct clk *c, unsigned long rate, u32 ver) +{ + struct hdmi_pll_vco_clk *vco = to_hdmi_vco_clk(c); + struct mdss_pll_resources *io = vco->priv; + unsigned int set_power_dwn = 0; + bool atomic_update = false; + int pll_lock_range = 0; + int rc = 0; + + rc = mdss_pll_resource_enable(io, true); + if (rc) { + pr_err("pll resource enable failed, rc=%d\n", rc); + return rc; + } + + pr_debug("rate %ld, vco_rate %ld\n", rate, vco->rate); + + if (_R(io->pll_base, C_READY_STATUS) & BIT(0) && + _R(io->phy_base, PHY_STATUS) & BIT(0)) { + pll_lock_range = hdmi_8998_vco_get_lock_range(c, vco->rate); + + if (pll_lock_range > 0 && vco->rate) { + u32 range_limit; + + range_limit = pll_lock_range * + (vco->rate / HDMI_KHZ_TO_HZ); + range_limit /= HDMI_KHZ_TO_HZ; + + pr_debug("range limit %d\n", range_limit); + + if (abs(rate - vco->rate) < range_limit) + atomic_update = true; + } + } + + if (io->pll_on && !atomic_update) + set_power_dwn = 1; + + if (atomic_update) + rc = hdmi_8998_vco_rate_atomic_update(c, rate, ver); + else + rc = hdmi_8998_pll_set_clk_rate(c, rate, ver); + + if (rc) { + pr_err("failed to set clk rate\n"); + goto error; + } + + if (set_power_dwn) { + rc = hdmi_8998_pll_enable(c); + if (rc) { + pr_err("failed to enable pll, rc=%d\n", rc); + goto error; + } + } + + vco->rate = rate; + vco->rate_set = true; + +error: + (void)mdss_pll_resource_enable(io, false); + + return rc; +} + +static long hdmi_8998_vco_round_rate(struct clk *c, unsigned long rate) +{ + unsigned long rrate = rate; + struct hdmi_pll_vco_clk *vco = to_hdmi_vco_clk(c); + + if (rate < vco->min_rate) + rrate = vco->min_rate; + if (rate > vco->max_rate) + rrate = vco->max_rate; + + return rrate; +} + +static int hdmi_8998_vco_prepare(struct clk *c, u32 ver) +{ + struct hdmi_pll_vco_clk *vco = to_hdmi_vco_clk(c); + struct mdss_pll_resources *io = vco->priv; + int rc = 0; + + if (!io) { + pr_err("hdmi pll resources are not available\n"); + return -EINVAL; + } + + rc = mdss_pll_resource_enable(io, true); + if (rc) { + pr_err("pll resource enable failed, rc=%d\n", rc); + return rc; + } + + if (!vco->rate_set && vco->rate) { + rc = hdmi_8998_pll_set_clk_rate(c, vco->rate, ver); + if (rc) { + pr_err("set rate failed, rc=%d\n", rc); + goto error; + } + } + + rc = hdmi_8998_pll_enable(c); + if (rc) + pr_err("pll enabled failed, rc=%d\n", rc); + +error: + if (rc) + mdss_pll_resource_enable(io, false); + + return rc; +} + +static void hdmi_8998_pll_disable(struct hdmi_pll_vco_clk *vco) +{ + struct mdss_pll_resources *io = vco->priv; + void __iomem *phy = io->phy_base; + + if (!io->pll_on) + return; + + _W(phy, PHY_PD_CTL, 0x0); + + /* Ensure all registers are flushed to hardware */ + wmb(); + + vco->rate_set = false; + io->handoff_resources = false; + io->pll_on = false; +} + +static void hdmi_8998_vco_unprepare(struct clk *c) +{ + struct hdmi_pll_vco_clk *vco = to_hdmi_vco_clk(c); + struct mdss_pll_resources *io = vco->priv; + + if (!io) { + pr_err("HDMI pll resources not available\n"); + return; + } + + hdmi_8998_pll_disable(vco); + mdss_pll_resource_enable(io, false); +} + +static enum handoff hdmi_8998_vco_handoff(struct clk *c) +{ + enum handoff ret = HANDOFF_DISABLED_CLK; + struct hdmi_pll_vco_clk *vco = to_hdmi_vco_clk(c); + struct mdss_pll_resources *io = vco->priv; + + if (mdss_pll_resource_enable(io, true)) { + pr_err("pll resource can't be enabled\n"); + return ret; + } + + io->handoff_resources = true; + + if (_R(io->pll_base, C_READY_STATUS) & BIT(0) && + _R(io->phy_base, PHY_STATUS) & BIT(0)) { + io->pll_on = true; + /* TODO: calculate rate based on the phy/pll register values. */ + ret = HANDOFF_ENABLED_CLK; + } else { + io->handoff_resources = false; + mdss_pll_resource_enable(io, false); + pr_debug("%s: PHY/PLL not ready\n", __func__); + } + + pr_debug("done, ret=%d\n", ret); + return ret; +} + +static int hdmi_8998_3p3_vco_set_rate(struct clk *c, unsigned long rate) +{ + return hdmi_8998_vco_set_rate(c, rate, HDMI_VERSION_8998_3_3); +} + +static int hdmi_8998_1p8_vco_set_rate(struct clk *c, unsigned long rate) +{ + return hdmi_8998_vco_set_rate(c, rate, HDMI_VERSION_8998_1_8); +} + +static int hdmi_8998_3p3_vco_prepare(struct clk *c) +{ + return hdmi_8998_vco_prepare(c, HDMI_VERSION_8998_3_3); +} + +static int hdmi_8998_1p8_vco_prepare(struct clk *c) +{ + return hdmi_8998_vco_prepare(c, HDMI_VERSION_8998_1_8); +} + +static struct clk_ops hdmi_8998_3p3_vco_clk_ops = { + .set_rate = hdmi_8998_3p3_vco_set_rate, + .round_rate = hdmi_8998_vco_round_rate, + .prepare = hdmi_8998_3p3_vco_prepare, + .unprepare = hdmi_8998_vco_unprepare, + .handoff = hdmi_8998_vco_handoff, +}; + +static struct clk_ops hdmi_8998_1p8_vco_clk_ops = { + .set_rate = hdmi_8998_1p8_vco_set_rate, + .round_rate = hdmi_8998_vco_round_rate, + .prepare = hdmi_8998_1p8_vco_prepare, + .unprepare = hdmi_8998_vco_unprepare, + .handoff = hdmi_8998_vco_handoff, +}; + +static struct hdmi_pll_vco_clk hdmi_vco_clk = { + .min_rate = HDMI_VCO_MIN_RATE_HZ, + .max_rate = HDMI_VCO_MAX_RATE_HZ, + .c = { + .dbg_name = "hdmi_8998_vco_clk", + .ops = &hdmi_8998_3p3_vco_clk_ops, + CLK_INIT(hdmi_vco_clk.c), + }, +}; + +static struct clk_lookup hdmipllcc_8998[] = { + CLK_LIST(hdmi_vco_clk), +}; + +int hdmi_8998_pll_clock_register(struct platform_device *pdev, + struct mdss_pll_resources *pll_res, u32 ver) +{ + int rc = 0; + + if (!pdev || !pll_res) { + pr_err("invalid input parameters\n"); + return -EINVAL; + } + + hdmi_vco_clk.priv = pll_res; + + switch (ver) { + case HDMI_VERSION_8998_3_3: + hdmi_vco_clk.c.ops = &hdmi_8998_3p3_vco_clk_ops; + break; + case HDMI_VERSION_8998_1_8: + hdmi_vco_clk.c.ops = &hdmi_8998_1p8_vco_clk_ops; + break; + default: + hdmi_vco_clk.c.ops = &hdmi_8998_3p3_vco_clk_ops; + break; + }; + + rc = of_msm_clock_register(pdev->dev.of_node, hdmipllcc_8998, + ARRAY_SIZE(hdmipllcc_8998)); + if (rc) { + pr_err("clock register failed, rc=%d\n", rc); + return rc; + } + + return rc; +} + +int hdmi_8998_3p3_pll_clock_register(struct platform_device *pdev, + struct mdss_pll_resources *pll_res) +{ + return hdmi_8998_pll_clock_register(pdev, pll_res, + HDMI_VERSION_8998_3_3); +} + +int hdmi_8998_1p8_pll_clock_register(struct platform_device *pdev, + struct mdss_pll_resources *pll_res) +{ + return hdmi_8998_pll_clock_register(pdev, pll_res, + HDMI_VERSION_8998_1_8); +} diff -Nruw linux-4.4.115-fbx/drivers/clk/msm./mdss/mdss-hdmi-pll.h linux-4.4.115-fbx/drivers/clk/msm/mdss/mdss-hdmi-pll.h --- linux-4.4.115-fbx/drivers/clk/msm./mdss/mdss-hdmi-pll.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-4.4.115-fbx/drivers/clk/msm/mdss/mdss-hdmi-pll.h 2019-01-22 16:16:23.023242060 +0100 @@ -0,0 +1,63 @@ +/* Copyright (c) 2012-2017, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __MDSS_HDMI_PLL_H +#define __MDSS_HDMI_PLL_H + +struct hdmi_pll_cfg { + unsigned long vco_rate; + u32 reg; +}; + +struct hdmi_pll_vco_clk { + unsigned long rate; /* current vco rate */ + unsigned long min_rate; /* min vco rate */ + unsigned long max_rate; /* max vco rate */ + bool rate_set; + struct hdmi_pll_cfg *ip_seti; + struct hdmi_pll_cfg *cp_seti; + struct hdmi_pll_cfg *ip_setp; + struct hdmi_pll_cfg *cp_setp; + struct hdmi_pll_cfg *crctrl; + void *priv; + + struct clk c; +}; + +static inline struct hdmi_pll_vco_clk *to_hdmi_vco_clk(struct clk *clk) +{ + return container_of(clk, struct hdmi_pll_vco_clk, c); +} + +int hdmi_pll_clock_register(struct platform_device *pdev, + struct mdss_pll_resources *pll_res); + +int hdmi_20nm_pll_clock_register(struct platform_device *pdev, + struct mdss_pll_resources *pll_res); + +int hdmi_8996_v1_pll_clock_register(struct platform_device *pdev, + struct mdss_pll_resources *pll_res); + +int hdmi_8996_v2_pll_clock_register(struct platform_device *pdev, + struct mdss_pll_resources *pll_res); + +int hdmi_8996_v3_pll_clock_register(struct platform_device *pdev, + struct mdss_pll_resources *pll_res); + +int hdmi_8996_v3_1p8_pll_clock_register(struct platform_device *pdev, + struct mdss_pll_resources *pll_res); + +int hdmi_8998_3p3_pll_clock_register(struct platform_device *pdev, + struct mdss_pll_resources *pll_res); +int hdmi_8998_1p8_pll_clock_register(struct platform_device *pdev, + struct mdss_pll_resources *pll_res); +#endif diff -Nruw linux-4.4.115-fbx/drivers/clk/msm./mdss/mdss-pll.c linux-4.4.115-fbx/drivers/clk/msm/mdss/mdss-pll.c --- linux-4.4.115-fbx/drivers/clk/msm./mdss/mdss-pll.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-4.4.115-fbx/drivers/clk/msm/mdss/mdss-pll.c 2019-01-22 16:16:23.023242060 +0100 @@ -0,0 +1,443 @@ +/* Copyright (c) 2013-2017, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#define pr_fmt(fmt) "%s: " fmt, __func__ + +#include +#include +#include +#include +#include +#include +#include + +#include "mdss-pll.h" +#include "mdss-dsi-pll.h" +#include "mdss-hdmi-pll.h" +#include "mdss-dp-pll.h" + +int mdss_pll_resource_enable(struct mdss_pll_resources *pll_res, bool enable) +{ + int rc = 0; + int changed = 0; + if (!pll_res) { + pr_err("Invalid input parameters\n"); + return -EINVAL; + } + + /* + * Don't turn off resources during handoff or add more than + * 1 refcount. + */ + if (pll_res->handoff_resources && + (!enable || (enable & pll_res->resource_enable))) { + pr_debug("Do not turn on/off pll resources during handoff case\n"); + return rc; + } + + if (enable) { + if (pll_res->resource_ref_cnt == 0) + changed++; + pll_res->resource_ref_cnt++; + } else { + if (pll_res->resource_ref_cnt) { + pll_res->resource_ref_cnt--; + if (pll_res->resource_ref_cnt == 0) + changed++; + } else { + pr_err("PLL Resources already OFF\n"); + } + } + + if (changed) { + rc = mdss_pll_util_resource_enable(pll_res, enable); + if (rc) + pr_err("Resource update failed rc=%d\n", rc); + else + pll_res->resource_enable = enable; + } + + return rc; +} + +static int mdss_pll_resource_init(struct platform_device *pdev, + struct mdss_pll_resources *pll_res) +{ + if (!pdev || !pll_res) { + pr_err("Invalid input parameters\n"); + return -EINVAL; + } + + return mdss_pll_util_resource_init(pdev, pll_res); +} + +static void mdss_pll_resource_deinit(struct platform_device *pdev, + struct mdss_pll_resources *pll_res) +{ + if (!pdev || !pll_res) { + pr_err("Invalid input parameters\n"); + return; + } + + mdss_pll_util_resource_deinit(pdev, pll_res); +} + +static void mdss_pll_resource_release(struct platform_device *pdev, + struct mdss_pll_resources *pll_res) +{ + if (!pdev || !pll_res) { + pr_err("Invalid input parameters\n"); + return; + } + + mdss_pll_util_resource_release(pdev, pll_res); +} + +static int mdss_pll_resource_parse(struct platform_device *pdev, + struct mdss_pll_resources *pll_res) +{ + int rc = 0; + const char *compatible_stream; + + if (!pdev || !pll_res) { + pr_err("Invalid input parameters\n"); + return -EINVAL; + } + + rc = mdss_pll_util_resource_parse(pdev, pll_res); + if (rc) { + pr_err("Failed to parse the resources rc=%d\n", rc); + goto end; + } + + compatible_stream = of_get_property(pdev->dev.of_node, + "compatible", NULL); + if (!compatible_stream) { + pr_err("Failed to parse the compatible stream\n"); + goto err; + } + + if (!strcmp(compatible_stream, "qcom,mdss_dsi_pll_8996")) { + pll_res->pll_interface_type = MDSS_DSI_PLL_8996; + pll_res->target_id = MDSS_PLL_TARGET_8996; + pll_res->revision = 1; + } else if (!strcmp(compatible_stream, "qcom,mdss_dsi_pll_8996_v2")) { + pll_res->pll_interface_type = MDSS_DSI_PLL_8996; + pll_res->target_id = MDSS_PLL_TARGET_8996; + pll_res->revision = 2; + } else if (!strcmp(compatible_stream, "qcom,mdss_dsi_pll_8998")) { + pll_res->pll_interface_type = MDSS_DSI_PLL_8998; + } else if (!strcmp(compatible_stream, "qcom,mdss_dp_pll_8998")) { + pll_res->pll_interface_type = MDSS_DP_PLL_8998; + } else if (!strcmp(compatible_stream, "qcom,mdss_hdmi_pll_8996")) { + pll_res->pll_interface_type = MDSS_HDMI_PLL_8996; + } else if (!strcmp(compatible_stream, "qcom,mdss_hdmi_pll_8996_v2")) { + pll_res->pll_interface_type = MDSS_HDMI_PLL_8996_V2; + } else if (!strcmp(compatible_stream, "qcom,mdss_hdmi_pll_8996_v3")) { + pll_res->pll_interface_type = MDSS_HDMI_PLL_8996_V3; + } else if (!strcmp(compatible_stream, + "qcom,mdss_hdmi_pll_8996_v3_1p8")) { + pll_res->pll_interface_type = MDSS_HDMI_PLL_8996_V3_1_8; + } else if (!strcmp(compatible_stream, "qcom,mdss_hdmi_pll_8998")) { + pll_res->pll_interface_type = MDSS_HDMI_PLL_8998_3_3; + } else if (!strcmp(compatible_stream, "qcom,mdss_hdmi_pll_8998_1p8")) { + pll_res->pll_interface_type = MDSS_HDMI_PLL_8998_1_8; + } else { + goto err; + } + + return rc; + +err: + mdss_pll_resource_release(pdev, pll_res); +end: + return rc; +} + +static int mdss_pll_clock_register(struct platform_device *pdev, + struct mdss_pll_resources *pll_res) +{ + int rc; + + if (!pdev || !pll_res) { + pr_err("Invalid input parameters\n"); + return -EINVAL; + } + + switch (pll_res->pll_interface_type) { + case MDSS_DSI_PLL_8996: + rc = dsi_pll_clock_register_8996(pdev, pll_res); + break; + case MDSS_DSI_PLL_8998: + rc = dsi_pll_clock_register_8998(pdev, pll_res); + case MDSS_DP_PLL_8998: + rc = dp_pll_clock_register_8998(pdev, pll_res); + break; + case MDSS_HDMI_PLL_8996: + rc = hdmi_8996_v1_pll_clock_register(pdev, pll_res); + break; + case MDSS_HDMI_PLL_8996_V2: + rc = hdmi_8996_v2_pll_clock_register(pdev, pll_res); + break; + case MDSS_HDMI_PLL_8996_V3: + rc = hdmi_8996_v3_pll_clock_register(pdev, pll_res); + break; + case MDSS_HDMI_PLL_8996_V3_1_8: + rc = hdmi_8996_v3_1p8_pll_clock_register(pdev, pll_res); + break; + case MDSS_HDMI_PLL_8998_3_3: + rc = hdmi_8998_3p3_pll_clock_register(pdev, pll_res); + break; + case MDSS_HDMI_PLL_8998_1_8: + rc = hdmi_8998_1p8_pll_clock_register(pdev, pll_res); + break; + case MDSS_UNKNOWN_PLL: + default: + rc = -EINVAL; + break; + } + + if (rc) { + pr_err("Pll ndx=%d clock register failed rc=%d\n", + pll_res->index, rc); + } + + return rc; +} + +static int mdss_pll_probe(struct platform_device *pdev) +{ + int rc = 0; + const char *label; + struct resource *pll_base_reg; + struct resource *phy_base_reg; + struct resource *dynamic_pll_base_reg; + struct resource *gdsc_base_reg; + struct mdss_pll_resources *pll_res; + + if (!pdev->dev.of_node) { + pr_err("MDSS pll driver only supports device tree probe\n"); + rc = -ENOTSUPP; + goto error; + } + + label = of_get_property(pdev->dev.of_node, "label", NULL); + if (!label) + pr_info("%d: MDSS pll label not specified\n", __LINE__); + else + pr_info("MDSS pll label = %s\n", label); + + pll_res = devm_kzalloc(&pdev->dev, sizeof(struct mdss_pll_resources), + GFP_KERNEL); + if (!pll_res) { + pr_err("Failed to allocate the clock pll\n"); + rc = -ENOMEM; + goto error; + } + platform_set_drvdata(pdev, pll_res); + + rc = of_property_read_u32(pdev->dev.of_node, "cell-index", + &pll_res->index); + if (rc) { + pr_err("Unable to get the cell-index rc=%d\n", rc); + pll_res->index = 0; + } + + pll_res->ssc_en = of_property_read_bool(pdev->dev.of_node, + "qcom,dsi-pll-ssc-en"); + + if (pll_res->ssc_en) { + pr_info("%s: label=%s PLL SSC enabled\n", __func__, label); + + rc = of_property_read_u32(pdev->dev.of_node, + "qcom,ssc-frequency-hz", &pll_res->ssc_freq); + + rc = of_property_read_u32(pdev->dev.of_node, + "qcom,ssc-ppm", &pll_res->ssc_ppm); + + pll_res->ssc_center = false; + + label = of_get_property(pdev->dev.of_node, + "qcom,dsi-pll-ssc-mode", NULL); + + if (label && !strcmp(label, "center-spread")) + pll_res->ssc_center = true; + } + + pll_base_reg = platform_get_resource_byname(pdev, + IORESOURCE_MEM, "pll_base"); + if (!pll_base_reg) { + pr_err("Unable to get the pll base resources\n"); + rc = -ENOMEM; + goto io_error; + } + + pll_res->pll_base = ioremap(pll_base_reg->start, + resource_size(pll_base_reg)); + if (!pll_res->pll_base) { + pr_err("Unable to remap pll base resources\n"); + rc = -ENOMEM; + goto io_error; + } + + pr_debug("%s: ndx=%d base=%p\n", __func__, + pll_res->index, pll_res->pll_base); + + rc = mdss_pll_resource_parse(pdev, pll_res); + if (rc) { + pr_err("Pll resource parsing from dt failed rc=%d\n", rc); + goto res_parse_error; + } + + phy_base_reg = platform_get_resource_byname(pdev, + IORESOURCE_MEM, "phy_base"); + if (phy_base_reg) { + pll_res->phy_base = ioremap(phy_base_reg->start, + resource_size(phy_base_reg)); + if (!pll_res->phy_base) { + pr_err("Unable to remap pll phy base resources\n"); + rc = -ENOMEM; + goto phy_io_error; + } + } + + dynamic_pll_base_reg = platform_get_resource_byname(pdev, + IORESOURCE_MEM, "dynamic_pll_base"); + if (dynamic_pll_base_reg) { + pll_res->dyn_pll_base = ioremap(dynamic_pll_base_reg->start, + resource_size(dynamic_pll_base_reg)); + if (!pll_res->dyn_pll_base) { + pr_err("Unable to remap dynamic pll base resources\n"); + rc = -ENOMEM; + goto dyn_pll_io_error; + } + } + + gdsc_base_reg = platform_get_resource_byname(pdev, + IORESOURCE_MEM, "gdsc_base"); + if (!gdsc_base_reg) { + pr_err("Unable to get the gdsc base resource\n"); + rc = -ENOMEM; + goto gdsc_io_error; + } + pll_res->gdsc_base = ioremap(gdsc_base_reg->start, + resource_size(gdsc_base_reg)); + if (!pll_res->gdsc_base) { + pr_err("Unable to remap gdsc base resources\n"); + rc = -ENOMEM; + goto gdsc_io_error; + } + + rc = mdss_pll_resource_init(pdev, pll_res); + if (rc) { + pr_err("Pll ndx=%d resource init failed rc=%d\n", + pll_res->index, rc); + goto res_init_error; + } + + rc = mdss_pll_clock_register(pdev, pll_res); + if (rc) { + pr_err("Pll ndx=%d clock register failed rc=%d\n", + pll_res->index, rc); + goto clock_register_error; + } + + return rc; + +clock_register_error: + mdss_pll_resource_deinit(pdev, pll_res); +res_init_error: + if (pll_res->gdsc_base) + iounmap(pll_res->gdsc_base); +gdsc_io_error: + if (pll_res->dyn_pll_base) + iounmap(pll_res->dyn_pll_base); +dyn_pll_io_error: + if (pll_res->phy_base) + iounmap(pll_res->phy_base); +phy_io_error: + mdss_pll_resource_release(pdev, pll_res); +res_parse_error: + iounmap(pll_res->pll_base); +io_error: + devm_kfree(&pdev->dev, pll_res); +error: + return rc; +} + +static int mdss_pll_remove(struct platform_device *pdev) +{ + struct mdss_pll_resources *pll_res; + + pll_res = platform_get_drvdata(pdev); + if (!pll_res) { + pr_err("Invalid PLL resource data"); + return 0; + } + + mdss_pll_resource_deinit(pdev, pll_res); + if (pll_res->phy_base) + iounmap(pll_res->phy_base); + if (pll_res->gdsc_base) + iounmap(pll_res->gdsc_base); + mdss_pll_resource_release(pdev, pll_res); + iounmap(pll_res->pll_base); + devm_kfree(&pdev->dev, pll_res); + return 0; +} + +static const struct of_device_id mdss_pll_dt_match[] = { + {.compatible = "qcom,mdss_dsi_pll_8996"}, + {.compatible = "qcom,mdss_dsi_pll_8996_v2"}, + {.compatible = "qcom,mdss_dsi_pll_8998"}, + {.compatible = "qcom,mdss_hdmi_pll_8996"}, + {.compatible = "qcom,mdss_hdmi_pll_8996_v2"}, + {.compatible = "qcom,mdss_hdmi_pll_8996_v3"}, + {.compatible = "qcom,mdss_hdmi_pll_8996_v3_1p8"}, + {.compatible = "qcom,mdss_dp_pll_8998"}, + {.compatible = "qcom,mdss_hdmi_pll_8998"}, + {.compatible = "qcom,mdss_hdmi_pll_8998_1p8"}, + {} +}; + +MODULE_DEVICE_TABLE(of, mdss_clock_dt_match); + +static struct platform_driver mdss_pll_driver = { + .probe = mdss_pll_probe, + .remove = mdss_pll_remove, + .driver = { + .name = "mdss_pll", + .of_match_table = mdss_pll_dt_match, + }, +}; + +static int __init mdss_pll_driver_init(void) +{ + int rc; + + rc = platform_driver_register(&mdss_pll_driver); + if (rc) + pr_err("mdss_register_pll_driver() failed!\n"); + + return rc; +} +subsys_initcall(mdss_pll_driver_init); + +static void __exit mdss_pll_driver_deinit(void) +{ + platform_driver_unregister(&mdss_pll_driver); +} +module_exit(mdss_pll_driver_deinit); + +MODULE_LICENSE("GPL v2"); +MODULE_DESCRIPTION("mdss pll driver"); diff -Nruw linux-4.4.115-fbx/drivers/clk/msm./mdss/mdss-pll.h linux-4.4.115-fbx/drivers/clk/msm/mdss/mdss-pll.h --- linux-4.4.115-fbx/drivers/clk/msm./mdss/mdss-pll.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-4.4.115-fbx/drivers/clk/msm/mdss/mdss-pll.h 2019-01-22 16:16:23.023242060 +0100 @@ -0,0 +1,235 @@ +/* Copyright (c) 2013-2017, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __MDSS_PLL_H +#define __MDSS_PLL_H + +#include +#include +#include + +#define MDSS_PLL_REG_W(base, offset, data) \ + writel_relaxed((data), (base) + (offset)) +#define MDSS_PLL_REG_R(base, offset) readl_relaxed((base) + (offset)) + +#define PLL_CALC_DATA(addr0, addr1, data0, data1) \ + (((data1) << 24) | ((((addr1) / 4) & 0xFF) << 16) | \ + ((data0) << 8) | (((addr0) / 4) & 0xFF)) + +#define MDSS_DYN_PLL_REG_W(base, offset, addr0, addr1, data0, data1) \ + writel_relaxed(PLL_CALC_DATA(addr0, addr1, data0, data1), \ + (base) + (offset)) + +enum { + MDSS_DSI_PLL_8996, + MDSS_DSI_PLL_8998, + MDSS_DP_PLL_8998, + MDSS_HDMI_PLL_8996, + MDSS_HDMI_PLL_8996_V2, + MDSS_HDMI_PLL_8996_V3, + MDSS_HDMI_PLL_8996_V3_1_8, + MDSS_HDMI_PLL_8998_3_3, + MDSS_HDMI_PLL_8998_1_8, + MDSS_UNKNOWN_PLL, +}; + +enum { + MDSS_PLL_TARGET_8996, +}; + +#define DFPS_MAX_NUM_OF_FRAME_RATES 20 + +struct dfps_panel_info { + uint32_t enabled; + uint32_t frame_rate_cnt; + uint32_t frame_rate[DFPS_MAX_NUM_OF_FRAME_RATES]; /* hz */ +}; + +struct dfps_pll_codes { + uint32_t pll_codes_1; + uint32_t pll_codes_2; +}; + +struct dfps_codes_info { + uint32_t is_valid; + uint32_t frame_rate; /* hz */ + uint32_t clk_rate; /* hz */ + struct dfps_pll_codes pll_codes; +}; + +struct dfps_info { + struct dfps_panel_info panel_dfps; + struct dfps_codes_info codes_dfps[DFPS_MAX_NUM_OF_FRAME_RATES]; + void *dfps_fb_base; + uint32_t chip_serial; +}; + +struct mdss_pll_resources { + + /* Pll specific resources like GPIO, power supply, clocks, etc*/ + struct dss_module_power mp; + + /* + * dsi/edp/hmdi plls' base register, phy, gdsc and dynamic refresh + * register mapping + */ + void __iomem *pll_base; + void __iomem *phy_base; + void __iomem *gdsc_base; + void __iomem *dyn_pll_base; + + bool is_init_locked; + s64 vco_current_rate; + s64 vco_locking_rate; + s64 vco_ref_clk_rate; + + /* + * Certain pll's needs to update the same vco rate after resume in + * suspend/resume scenario. Cached the vco rate for such plls. + */ + unsigned long vco_cached_rate; + + /* dsi/edp/hmdi pll interface type */ + u32 pll_interface_type; + + /* + * Target ID. Used in pll_register API for valid target check before + * registering the PLL clocks. + */ + u32 target_id; + + /* HW recommended delay during configuration of vco clock rate */ + u32 vco_delay; + + /* Ref-count of the PLL resources */ + u32 resource_ref_cnt; + + /* + * Keep track to resource status to avoid updating same status for the + * pll from different paths + */ + bool resource_enable; + + /* + * Certain plls' do not allow vco rate update if it is on. Keep track of + * status for them to turn on/off after set rate success. + */ + bool pll_on; + + /* + * handoff_status is true of pll is already enabled by bootloader with + * continuous splash enable case. Clock API will call the handoff API + * to enable the status. It is disabled if continuous splash + * feature is disabled. + */ + bool handoff_resources; + + /* + * caching the pll trim codes in the case of dynamic refresh + */ + int cache_pll_trim_codes[2]; + + /* + * for maintaining the status of saving trim codes + */ + bool reg_upd; + + /* + * Notifier callback for MDSS gdsc regulator events + */ + struct notifier_block gdsc_cb; + + /* + * Worker function to call PLL off event + */ + struct work_struct pll_off; + + /* + * PLL index if multiple index are available. Eg. in case of + * DSI we have 2 plls. + */ + uint32_t index; + + bool ssc_en; /* share pll with master */ + bool ssc_center; /* default is down spread */ + u32 ssc_freq; + u32 ssc_ppm; + + struct mdss_pll_resources *slave; + + /* + * target pll revision information + */ + int revision; + + void *priv; + + /* + * dynamic refresh pll codes stored in this structure + */ + struct dfps_info *dfps; + +}; + +struct mdss_pll_vco_calc { + s32 div_frac_start1; + s32 div_frac_start2; + s32 div_frac_start3; + s64 dec_start1; + s64 dec_start2; + s64 pll_plllock_cmp1; + s64 pll_plllock_cmp2; + s64 pll_plllock_cmp3; +}; + +static inline bool is_gdsc_disabled(struct mdss_pll_resources *pll_res) +{ + if (!pll_res->gdsc_base) { + WARN(1, "gdsc_base register is not defined\n"); + return true; + } + + return ((readl_relaxed(pll_res->gdsc_base + 0x4) & BIT(31)) && + (!(readl_relaxed(pll_res->gdsc_base) & BIT(0)))) ? false : true; +} + +static inline int mdss_pll_div_prepare(struct clk *c) +{ + struct div_clk *div = to_div_clk(c); + /* Restore the divider's value */ + return div->ops->set_div(div, div->data.div); +} + +static inline int mdss_set_mux_sel(struct mux_clk *clk, int sel) +{ + return 0; +} + +static inline int mdss_get_mux_sel(struct mux_clk *clk) +{ + return 0; +} + +int mdss_pll_resource_enable(struct mdss_pll_resources *pll_res, bool enable); +int mdss_pll_util_resource_init(struct platform_device *pdev, + struct mdss_pll_resources *pll_res); +void mdss_pll_util_resource_deinit(struct platform_device *pdev, + struct mdss_pll_resources *pll_res); +void mdss_pll_util_resource_release(struct platform_device *pdev, + struct mdss_pll_resources *pll_res); +int mdss_pll_util_resource_enable(struct mdss_pll_resources *pll_res, + bool enable); +int mdss_pll_util_resource_parse(struct platform_device *pdev, + struct mdss_pll_resources *pll_res); +struct dss_vreg *mdss_pll_get_mp_by_reg_name(struct mdss_pll_resources *pll_res + , char *name); +#endif diff -Nruw linux-4.4.115-fbx/drivers/clk/msm./mdss/mdss-pll-util.c linux-4.4.115-fbx/drivers/clk/msm/mdss/mdss-pll-util.c --- linux-4.4.115-fbx/drivers/clk/msm./mdss/mdss-pll-util.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-4.4.115-fbx/drivers/clk/msm/mdss/mdss-pll-util.c 2019-01-22 16:16:23.023242060 +0100 @@ -0,0 +1,441 @@ +/* Copyright (c) 2013-2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#define pr_fmt(fmt) "%s: " fmt, __func__ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "mdss-pll.h" + +int mdss_pll_util_resource_init(struct platform_device *pdev, + struct mdss_pll_resources *pll_res) +{ + int rc = 0; + struct dss_module_power *mp = &pll_res->mp; + + rc = msm_dss_config_vreg(&pdev->dev, + mp->vreg_config, mp->num_vreg, 1); + if (rc) { + pr_err("Vreg config failed rc=%d\n", rc); + goto vreg_err; + } + + rc = msm_dss_get_clk(&pdev->dev, mp->clk_config, mp->num_clk); + if (rc) { + pr_err("Clock get failed rc=%d\n", rc); + goto clk_err; + } + + return rc; + +clk_err: + msm_dss_config_vreg(&pdev->dev, mp->vreg_config, mp->num_vreg, 0); +vreg_err: + return rc; +} + +/** + * mdss_pll_get_mp_by_reg_name() -- Find power module by regulator name + *@pll_res: Pointer to the PLL resource + *@name: Regulator name as specified in the pll dtsi + * + * This is a helper function to retrieve the regulator information + * for each pll resource. + */ +struct dss_vreg *mdss_pll_get_mp_by_reg_name(struct mdss_pll_resources *pll_res + , char *name) +{ + + struct dss_vreg *regulator = NULL; + int i; + + if ((pll_res == NULL) || (pll_res->mp.vreg_config == NULL)) { + pr_err("%s Invalid PLL resource\n", __func__); + goto error; + } + + regulator = pll_res->mp.vreg_config; + + for (i = 0; i < pll_res->mp.num_vreg; i++) { + if (!strcmp(name, regulator->vreg_name)) { + pr_debug("Found regulator match for %s\n", name); + break; + } + regulator++; + } + +error: + return regulator; +} + +void mdss_pll_util_resource_deinit(struct platform_device *pdev, + struct mdss_pll_resources *pll_res) +{ + struct dss_module_power *mp = &pll_res->mp; + + msm_dss_put_clk(mp->clk_config, mp->num_clk); + + msm_dss_config_vreg(&pdev->dev, mp->vreg_config, mp->num_vreg, 0); +} + +void mdss_pll_util_resource_release(struct platform_device *pdev, + struct mdss_pll_resources *pll_res) +{ + struct dss_module_power *mp = &pll_res->mp; + + devm_kfree(&pdev->dev, mp->clk_config); + devm_kfree(&pdev->dev, mp->vreg_config); + mp->num_vreg = 0; + mp->num_clk = 0; +} + +int mdss_pll_util_resource_enable(struct mdss_pll_resources *pll_res, + bool enable) +{ + int rc = 0; + struct dss_module_power *mp = &pll_res->mp; + + if (enable) { + rc = msm_dss_enable_vreg(mp->vreg_config, mp->num_vreg, enable); + if (rc) { + pr_err("Failed to enable vregs rc=%d\n", rc); + goto vreg_err; + } + + rc = msm_dss_clk_set_rate(mp->clk_config, mp->num_clk); + if (rc) { + pr_err("Failed to set clock rate rc=%d\n", rc); + goto clk_err; + } + + rc = msm_dss_enable_clk(mp->clk_config, mp->num_clk, enable); + if (rc) { + pr_err("clock enable failed rc:%d\n", rc); + goto clk_err; + } + } else { + msm_dss_enable_clk(mp->clk_config, mp->num_clk, enable); + + msm_dss_enable_vreg(mp->vreg_config, mp->num_vreg, enable); + } + + return rc; + +clk_err: + msm_dss_enable_vreg(mp->vreg_config, mp->num_vreg, 0); +vreg_err: + return rc; +} + +static int mdss_pll_util_parse_dt_supply(struct platform_device *pdev, + struct mdss_pll_resources *pll_res) +{ + int i = 0, rc = 0; + u32 tmp = 0; + struct device_node *of_node = NULL, *supply_root_node = NULL; + struct device_node *supply_node = NULL; + struct dss_module_power *mp = &pll_res->mp; + + of_node = pdev->dev.of_node; + + mp->num_vreg = 0; + supply_root_node = of_get_child_by_name(of_node, + "qcom,platform-supply-entries"); + if (!supply_root_node) { + pr_err("no supply entry present\n"); + return rc; + } + + for_each_child_of_node(supply_root_node, supply_node) { + mp->num_vreg++; + } + + if (mp->num_vreg == 0) { + pr_debug("no vreg\n"); + return rc; + } else { + pr_debug("vreg found. count=%d\n", mp->num_vreg); + } + + mp->vreg_config = devm_kzalloc(&pdev->dev, sizeof(struct dss_vreg) * + mp->num_vreg, GFP_KERNEL); + if (!mp->vreg_config) { + pr_err("can't alloc vreg mem\n"); + rc = -ENOMEM; + return rc; + } + + for_each_child_of_node(supply_root_node, supply_node) { + + const char *st = NULL; + + rc = of_property_read_string(supply_node, + "qcom,supply-name", &st); + if (rc) { + pr_err(":error reading name. rc=%d\n", rc); + goto error; + } + + strlcpy(mp->vreg_config[i].vreg_name, st, + sizeof(mp->vreg_config[i].vreg_name)); + + rc = of_property_read_u32(supply_node, + "qcom,supply-min-voltage", &tmp); + if (rc) { + pr_err(": error reading min volt. rc=%d\n", rc); + goto error; + } + mp->vreg_config[i].min_voltage = tmp; + + rc = of_property_read_u32(supply_node, + "qcom,supply-max-voltage", &tmp); + if (rc) { + pr_err(": error reading max volt. rc=%d\n", rc); + goto error; + } + mp->vreg_config[i].max_voltage = tmp; + + rc = of_property_read_u32(supply_node, + "qcom,supply-enable-load", &tmp); + if (rc) { + pr_err(": error reading enable load. rc=%d\n", rc); + goto error; + } + mp->vreg_config[i].enable_load = tmp; + + rc = of_property_read_u32(supply_node, + "qcom,supply-disable-load", &tmp); + if (rc) { + pr_err(": error reading disable load. rc=%d\n", rc); + goto error; + } + mp->vreg_config[i].disable_load = tmp; + + rc = of_property_read_u32(supply_node, + "qcom,supply-pre-on-sleep", &tmp); + if (rc) + pr_debug("error reading supply pre sleep value. rc=%d\n", + rc); + + mp->vreg_config[i].pre_on_sleep = (!rc ? tmp : 0); + + rc = of_property_read_u32(supply_node, + "qcom,supply-pre-off-sleep", &tmp); + if (rc) + pr_debug("error reading supply pre sleep value. rc=%d\n", + rc); + + mp->vreg_config[i].pre_off_sleep = (!rc ? tmp : 0); + + rc = of_property_read_u32(supply_node, + "qcom,supply-post-on-sleep", &tmp); + if (rc) + pr_debug("error reading supply post sleep value. rc=%d\n", + rc); + + mp->vreg_config[i].post_on_sleep = (!rc ? tmp : 0); + + rc = of_property_read_u32(supply_node, + "qcom,supply-post-off-sleep", &tmp); + if (rc) + pr_debug("error reading supply post sleep value. rc=%d\n", + rc); + + mp->vreg_config[i].post_off_sleep = (!rc ? tmp : 0); + + pr_debug("%s min=%d, max=%d, enable=%d, disable=%d, preonsleep=%d, postonsleep=%d, preoffsleep=%d, postoffsleep=%d\n", + mp->vreg_config[i].vreg_name, + mp->vreg_config[i].min_voltage, + mp->vreg_config[i].max_voltage, + mp->vreg_config[i].enable_load, + mp->vreg_config[i].disable_load, + mp->vreg_config[i].pre_on_sleep, + mp->vreg_config[i].post_on_sleep, + mp->vreg_config[i].pre_off_sleep, + mp->vreg_config[i].post_off_sleep); + ++i; + + rc = 0; + } + + return rc; + +error: + if (mp->vreg_config) { + devm_kfree(&pdev->dev, mp->vreg_config); + mp->vreg_config = NULL; + mp->num_vreg = 0; + } + + return rc; +} + +static int mdss_pll_util_parse_dt_clock(struct platform_device *pdev, + struct mdss_pll_resources *pll_res) +{ + u32 i = 0, rc = 0; + struct dss_module_power *mp = &pll_res->mp; + const char *clock_name; + u32 clock_rate; + + mp->num_clk = of_property_count_strings(pdev->dev.of_node, + "clock-names"); + if (mp->num_clk <= 0) { + pr_err("clocks are not defined\n"); + goto clk_err; + } + + mp->clk_config = devm_kzalloc(&pdev->dev, + sizeof(struct dss_clk) * mp->num_clk, GFP_KERNEL); + if (!mp->clk_config) { + pr_err("clock configuration allocation failed\n"); + rc = -ENOMEM; + mp->num_clk = 0; + goto clk_err; + } + + for (i = 0; i < mp->num_clk; i++) { + of_property_read_string_index(pdev->dev.of_node, "clock-names", + i, &clock_name); + strlcpy(mp->clk_config[i].clk_name, clock_name, + sizeof(mp->clk_config[i].clk_name)); + + of_property_read_u32_index(pdev->dev.of_node, "clock-rate", + i, &clock_rate); + mp->clk_config[i].rate = clock_rate; + + if (!clock_rate) + mp->clk_config[i].type = DSS_CLK_AHB; + else + mp->clk_config[i].type = DSS_CLK_PCLK; + } + +clk_err: + return rc; +} + +static void mdss_pll_free_bootmem(u32 mem_addr, u32 size) +{ + unsigned long pfn_start, pfn_end, pfn_idx; + + pfn_start = mem_addr >> PAGE_SHIFT; + pfn_end = (mem_addr + size) >> PAGE_SHIFT; + for (pfn_idx = pfn_start; pfn_idx < pfn_end; pfn_idx++) + free_reserved_page(pfn_to_page(pfn_idx)); +} + +static int mdss_pll_util_parse_dt_dfps(struct platform_device *pdev, + struct mdss_pll_resources *pll_res) +{ + int rc = 0; + struct device_node *pnode; + const u32 *addr; + struct vm_struct *area; + u64 size; + u32 offsets[2]; + unsigned long virt_add; + + pnode = of_parse_phandle(pdev->dev.of_node, "memory-region", 0); + if (IS_ERR_OR_NULL(pnode)) { + rc = PTR_ERR(pnode); + goto pnode_err; + } + + addr = of_get_address(pnode, 0, &size, NULL); + if (!addr) { + pr_err("failed to parse the dfps memory address\n"); + rc = -EINVAL; + goto pnode_err; + } + /* maintain compatibility for 32/64 bit */ + offsets[0] = (u32) of_read_ulong(addr, 2); + offsets[1] = (u32) size; + + area = get_vm_area(offsets[1], VM_IOREMAP); + if (!area) { + rc = -ENOMEM; + goto dfps_mem_err; + } + + virt_add = (unsigned long)area->addr; + rc = ioremap_page_range(virt_add, (virt_add + offsets[1]), + offsets[0], PAGE_KERNEL); + if (rc) { + rc = -ENOMEM; + goto ioremap_err; + } + + pll_res->dfps = kzalloc(sizeof(struct dfps_info), GFP_KERNEL); + if (IS_ERR_OR_NULL(pll_res->dfps)) { + rc = PTR_ERR(pll_res->dfps); + pr_err("couldn't allocate dfps kernel memory\n"); + goto addr_err; + } + + /* memcopy complete dfps structure from kernel virtual memory */ + memcpy_fromio(pll_res->dfps, area->addr, sizeof(struct dfps_info)); + +addr_err: + if (virt_add) + unmap_kernel_range(virt_add, (unsigned long) size); +ioremap_err: + if (area) + vfree(area->addr); +dfps_mem_err: + /* free the dfps memory here */ + memblock_free(offsets[0], offsets[1]); + mdss_pll_free_bootmem(offsets[0], offsets[1]); +pnode_err: + if (pnode) + of_node_put(pnode); + + dma_release_declared_memory(&pdev->dev); + return rc; +} + +int mdss_pll_util_resource_parse(struct platform_device *pdev, + struct mdss_pll_resources *pll_res) +{ + int rc = 0; + struct dss_module_power *mp = &pll_res->mp; + + rc = mdss_pll_util_parse_dt_supply(pdev, pll_res); + if (rc) { + pr_err("vreg parsing failed rc=%d\n", rc); + goto end; + } + + rc = mdss_pll_util_parse_dt_clock(pdev, pll_res); + if (rc) { + pr_err("clock name parsing failed rc=%d", rc); + goto clk_err; + } + + if (mdss_pll_util_parse_dt_dfps(pdev, pll_res)) + pr_err("dfps not enabled!\n"); + + return rc; + +clk_err: + devm_kfree(&pdev->dev, mp->vreg_config); + mp->num_vreg = 0; +end: + return rc; +} diff -Nruw linux-4.4.115-fbx/drivers/clk/msm./reset.c linux-4.4.115-fbx/drivers/clk/msm/reset.c --- linux-4.4.115-fbx/drivers/clk/msm./reset.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-4.4.115-fbx/drivers/clk/msm/reset.c 2019-01-22 16:16:23.023242060 +0100 @@ -0,0 +1,100 @@ +/* + * Copyright (c) 2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include + +#include "reset.h" + +static int msm_reset(struct reset_controller_dev *rcdev, unsigned long id) +{ + rcdev->ops->assert(rcdev, id); + udelay(1); + rcdev->ops->deassert(rcdev, id); + return 0; +} + +static int +msm_reset_assert(struct reset_controller_dev *rcdev, unsigned long id) +{ + struct msm_reset_controller *rst; + const struct msm_reset_map *map; + u32 regval; + + rst = to_msm_reset_controller(rcdev); + map = &rst->reset_map[id]; + + regval = readl_relaxed(rst->base + map->reg); + regval |= BIT(map->bit); + writel_relaxed(regval, rst->base + map->reg); + + /* Make sure the reset is asserted */ + mb(); + + return 0; +} + +static int +msm_reset_deassert(struct reset_controller_dev *rcdev, unsigned long id) +{ + struct msm_reset_controller *rst; + const struct msm_reset_map *map; + u32 regval; + + rst = to_msm_reset_controller(rcdev); + map = &rst->reset_map[id]; + + regval = readl_relaxed(rst->base + map->reg); + regval &= ~BIT(map->bit); + writel_relaxed(regval, rst->base + map->reg); + + /* Make sure the reset is de-asserted */ + mb(); + + return 0; +} + +struct reset_control_ops msm_reset_ops = { + .reset = msm_reset, + .assert = msm_reset_assert, + .deassert = msm_reset_deassert, +}; +EXPORT_SYMBOL_GPL(msm_reset_ops); + +int msm_reset_controller_register(struct platform_device *pdev, + const struct msm_reset_map *map, unsigned int num_resets, + void __iomem *virt_base) +{ + struct msm_reset_controller *reset; + int ret = 0; + + reset = devm_kzalloc(&pdev->dev, sizeof(*reset), GFP_KERNEL); + if (!reset) + return -ENOMEM; + + reset->rcdev.of_node = pdev->dev.of_node; + reset->rcdev.ops = &msm_reset_ops; + reset->rcdev.owner = pdev->dev.driver->owner; + reset->rcdev.nr_resets = num_resets; + reset->reset_map = map; + reset->base = virt_base; + + ret = reset_controller_register(&reset->rcdev); + if (ret) + dev_err(&pdev->dev, "Failed to register with reset controller\n"); + + return ret; +} +EXPORT_SYMBOL_GPL(msm_reset_controller_register); diff -Nruw linux-4.4.115-fbx/drivers/clk/msm./reset.h linux-4.4.115-fbx/drivers/clk/msm/reset.h --- linux-4.4.115-fbx/drivers/clk/msm./reset.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-4.4.115-fbx/drivers/clk/msm/reset.h 2019-01-22 16:16:23.023242060 +0100 @@ -0,0 +1,39 @@ +/* + * Copyright (c) 2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __DRIVERS_CLK_RESET_H +#define __DRIVERS_CLK_RESET_H + +#include +#include + +struct msm_reset_map { + unsigned int reg; + u8 bit; +}; + +struct msm_reset_controller { + const struct msm_reset_map *reset_map; + struct reset_controller_dev rcdev; + void __iomem *base; +}; + +#define to_msm_reset_controller(r) \ + container_of(r, struct msm_reset_controller, rcdev) + +extern struct reset_control_ops msm_reset_ops; + +int msm_reset_controller_register(struct platform_device *pdev, + const struct msm_reset_map *map, unsigned int nr_resets, + void __iomem *virt_base); +#endif diff -Nruw linux-4.4.115-fbx/drivers/clk/msm./vdd-level-8998.h linux-4.4.115-fbx/drivers/clk/msm/vdd-level-8998.h --- linux-4.4.115-fbx/drivers/clk/msm./vdd-level-8998.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-4.4.115-fbx/drivers/clk/msm/vdd-level-8998.h 2019-01-22 16:16:23.023242060 +0100 @@ -0,0 +1,124 @@ +/* + * Copyright (c) 2015-2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __DRIVERS_CLK_QCOM_VDD_LEVEL_8998_H +#define __DRIVERS_CLK_QCOM_VDD_LEVEL_8998_H + +#include +#include +#include + +#define VDD_DIG_FMAX_MAP1(l1, f1) \ + .vdd_class = &vdd_dig, \ + .fmax = (unsigned long[VDD_DIG_NUM]) { \ + [VDD_DIG_##l1] = (f1), \ + }, \ + .num_fmax = VDD_DIG_NUM + +#define VDD_DIG_FMAX_MAP2(l1, f1, l2, f2) \ + .vdd_class = &vdd_dig, \ + .fmax = (unsigned long[VDD_DIG_NUM]) { \ + [VDD_DIG_##l1] = (f1), \ + [VDD_DIG_##l2] = (f2), \ + }, \ + .num_fmax = VDD_DIG_NUM + +#define VDD_DIG_FMAX_MAP3(l1, f1, l2, f2, l3, f3) \ + .vdd_class = &vdd_dig, \ + .fmax = (unsigned long[VDD_DIG_NUM]) { \ + [VDD_DIG_##l1] = (f1), \ + [VDD_DIG_##l2] = (f2), \ + [VDD_DIG_##l3] = (f3), \ + }, \ + .num_fmax = VDD_DIG_NUM + +#define VDD_DIG_FMAX_MAP4(l1, f1, l2, f2, l3, f3, l4, f4) \ + .vdd_class = &vdd_dig, \ + .fmax = (unsigned long[VDD_DIG_NUM]) { \ + [VDD_DIG_##l1] = (f1), \ + [VDD_DIG_##l2] = (f2), \ + [VDD_DIG_##l3] = (f3), \ + [VDD_DIG_##l4] = (f4), \ + }, \ + .num_fmax = VDD_DIG_NUM + +#define VDD_DIG_FMAX_MAP1_AO(l1, f1) \ + .vdd_class = &vdd_dig_ao, \ + .fmax = (unsigned long[VDD_DIG_NUM]) { \ + [VDD_DIG_##l1] = (f1), \ + }, \ + .num_fmax = VDD_DIG_NUM + +#define VDD_DIG_FMAX_MAP3_AO(l1, f1, l2, f2, l3, f3) \ + .vdd_class = &vdd_dig_ao, \ + .fmax = (unsigned long[VDD_DIG_NUM]) { \ + [VDD_DIG_##l1] = (f1), \ + [VDD_DIG_##l2] = (f2), \ + [VDD_DIG_##l3] = (f3), \ + }, \ + .num_fmax = VDD_DIG_NUM + +#define VDD_MM_PLL_FMAX_MAP1(l1, f1) \ + .vdd_class = &vdd_mmsscc_mx, \ + .fmax = (unsigned long[VDD_DIG_NUM]) { \ + [VDD_DIG_##l1] = (f1), \ + }, \ + .num_fmax = VDD_DIG_NUM + +#define VDD_MM_PLL_FMAX_MAP2(l1, f1, l2, f2) \ + .vdd_class = &vdd_mmsscc_mx, \ + .fmax = (unsigned long[VDD_DIG_NUM]) { \ + [VDD_DIG_##l1] = (f1), \ + [VDD_DIG_##l2] = (f2), \ + }, \ + .num_fmax = VDD_DIG_NUM + + +#define VDD_GPU_PLL_FMAX_MAP1(l1, f1) \ + .vdd_class = &vdd_gpucc_mx, \ + .fmax = (unsigned long[VDD_DIG_NUM]) { \ + [VDD_DIG_##l1] = (f1), \ + }, \ + .num_fmax = VDD_DIG_NUM + +#define VDD_GPU_PLL_FMAX_MAP3(l1, f1, l2, f2, l3, f3) \ + .vdd_class = &vdd_gpucc_mx, \ + .fmax = (unsigned long[VDD_DIG_NUM]) { \ + [VDD_DIG_##l1] = (f1), \ + [VDD_DIG_##l2] = (f2), \ + [VDD_DIG_##l3] = (f3), \ + }, \ + .num_fmax = VDD_DIG_NUM + +enum vdd_dig_levels { + VDD_DIG_NONE, + VDD_DIG_MIN, /* MIN SVS */ + VDD_DIG_LOWER, /* SVS2 */ + VDD_DIG_LOW, /* SVS */ + VDD_DIG_LOW_L1, /* SVSL1 */ + VDD_DIG_NOMINAL, /* NOM */ + VDD_DIG_HIGH, /* TURBO */ + VDD_DIG_NUM +}; + +static int vdd_corner[] = { + RPM_REGULATOR_LEVEL_NONE, /* VDD_DIG_NONE */ + RPM_REGULATOR_LEVEL_MIN_SVS, /* VDD_DIG_MIN */ + RPM_REGULATOR_LEVEL_LOW_SVS, /* VDD_DIG_LOWER */ + RPM_REGULATOR_LEVEL_SVS, /* VDD_DIG_LOW */ + RPM_REGULATOR_LEVEL_SVS_PLUS, /* VDD_DIG_LOW_L1 */ + RPM_REGULATOR_LEVEL_NOM, /* VDD_DIG_NOMINAL */ + RPM_REGULATOR_LEVEL_TURBO, /* VDD_DIG_HIGH */ +}; + +#endif diff -Nruw linux-4.4.115-fbx/drivers/clk/qcom/mdss./Kconfig linux-4.4.115-fbx/drivers/clk/qcom/mdss/Kconfig --- linux-4.4.115-fbx/drivers/clk/qcom/mdss./Kconfig 1970-01-01 01:00:00.000000000 +0100 +++ linux-4.4.115-fbx/drivers/clk/qcom/mdss/Kconfig 2019-01-22 16:16:23.039242205 +0100 @@ -0,0 +1,7 @@ +config QCOM_MDSS_PLL + bool "MDSS pll programming" + depends on COMMON_CLK_QCOM + ---help--- + It provides support for DSI, eDP and HDMI interface pll programming on MDSS + hardware. It also handles the pll specific resources and turn them on/off when + mdss pll client tries to enable/disable pll clocks. diff -Nruw linux-4.4.115-fbx/drivers/clk/qcom/mdss./Makefile linux-4.4.115-fbx/drivers/clk/qcom/mdss/Makefile --- linux-4.4.115-fbx/drivers/clk/qcom/mdss./Makefile 1970-01-01 01:00:00.000000000 +0100 +++ linux-4.4.115-fbx/drivers/clk/qcom/mdss/Makefile 2019-01-22 16:16:23.039242205 +0100 @@ -0,0 +1,6 @@ +obj-$(CONFIG_QCOM_MDSS_PLL) += mdss-pll-util.o +obj-$(CONFIG_QCOM_MDSS_PLL) += mdss-pll.o +obj-$(CONFIG_QCOM_MDSS_PLL) += mdss-dsi-pll-14nm.o +obj-$(CONFIG_QCOM_MDSS_PLL) += mdss-dsi-pll-14nm-util.o +obj-$(CONFIG_QCOM_MDSS_PLL) += mdss-dp-pll-14nm.o +obj-$(CONFIG_QCOM_MDSS_PLL) += mdss-dp-pll-14nm-util.o --- /dev/null 2019-10-24 16:47:25.704025805 +0200 +++ linux-4.4.115-fbx/drivers/cpufreq/cpufreq_governor_attr_set.c 2019-01-22 16:16:23.079242567 +0100 @@ -0,0 +1,84 @@ +/* + * Abstract code for CPUFreq governor tunable sysfs attributes. + * + * Copyright (C) 2016, Intel Corporation + * Author: Rafael J. Wysocki + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "cpufreq_governor.h" + +static inline struct gov_attr_set *to_gov_attr_set(struct kobject *kobj) +{ + return container_of(kobj, struct gov_attr_set, kobj); +} + +static inline struct governor_attr *to_gov_attr(struct attribute *attr) +{ + return container_of(attr, struct governor_attr, attr); +} + +static ssize_t governor_show(struct kobject *kobj, struct attribute *attr, + char *buf) +{ + struct governor_attr *gattr = to_gov_attr(attr); + + return gattr->show(to_gov_attr_set(kobj), buf); +} + +static ssize_t governor_store(struct kobject *kobj, struct attribute *attr, + const char *buf, size_t count) +{ + struct gov_attr_set *attr_set = to_gov_attr_set(kobj); + struct governor_attr *gattr = to_gov_attr(attr); + int ret; + + mutex_lock(&attr_set->update_lock); + ret = attr_set->usage_count ? gattr->store(attr_set, buf, count) : -EBUSY; + mutex_unlock(&attr_set->update_lock); + return ret; +} + +const struct sysfs_ops governor_sysfs_ops = { + .show = governor_show, + .store = governor_store, +}; +EXPORT_SYMBOL_GPL(governor_sysfs_ops); + +void gov_attr_set_init(struct gov_attr_set *attr_set, struct list_head *list_node) +{ + INIT_LIST_HEAD(&attr_set->policy_list); + mutex_init(&attr_set->update_lock); + attr_set->usage_count = 1; + list_add(list_node, &attr_set->policy_list); +} +EXPORT_SYMBOL_GPL(gov_attr_set_init); + +void gov_attr_set_get(struct gov_attr_set *attr_set, struct list_head *list_node) +{ + mutex_lock(&attr_set->update_lock); + attr_set->usage_count++; + list_add(list_node, &attr_set->policy_list); + mutex_unlock(&attr_set->update_lock); +} +EXPORT_SYMBOL_GPL(gov_attr_set_get); + +unsigned int gov_attr_set_put(struct gov_attr_set *attr_set, struct list_head *list_node) +{ + unsigned int count; + + mutex_lock(&attr_set->update_lock); + list_del(list_node); + count = --attr_set->usage_count; + mutex_unlock(&attr_set->update_lock); + if (count) + return count; + + kobject_put(&attr_set->kobj); + mutex_destroy(&attr_set->update_lock); + return 0; +} +EXPORT_SYMBOL_GPL(gov_attr_set_put); --- /dev/null 2019-10-24 16:47:25.704025805 +0200 +++ linux-4.4.115-fbx/drivers/cpufreq/cpufreq_interactive.c 2019-10-29 09:26:23.493201710 +0100 @@ -0,0 +1,1876 @@ +/* + * drivers/cpufreq/cpufreq_interactive.c + * + * Copyright (C) 2010 Google, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Author: Mike Chan (mike@android.com) + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define CREATE_TRACE_POINTS +#include + +struct cpufreq_interactive_policyinfo { + struct timer_list policy_timer; + struct timer_list policy_slack_timer; + struct hrtimer notif_timer; + spinlock_t load_lock; /* protects load tracking stat */ + u64 last_evaluated_jiffy; + struct cpufreq_policy *policy; + struct cpufreq_policy p_nolim; /* policy copy with no limits */ + struct cpufreq_frequency_table *freq_table; + spinlock_t target_freq_lock; /*protects target freq */ + unsigned int target_freq; + unsigned int floor_freq; + unsigned int min_freq; + u64 floor_validate_time; + u64 hispeed_validate_time; + u64 max_freq_hyst_start_time; + struct rw_semaphore enable_sem; + bool reject_notification; + bool notif_pending; + unsigned long notif_cpu; + int governor_enabled; + struct cpufreq_interactive_tunables *cached_tunables; + struct sched_load *sl; +}; + +/* Protected by per-policy load_lock */ +struct cpufreq_interactive_cpuinfo { + u64 time_in_idle; + u64 time_in_idle_timestamp; + u64 cputime_speedadj; + u64 cputime_speedadj_timestamp; + unsigned int loadadjfreq; +}; + +static DEFINE_PER_CPU(struct cpufreq_interactive_policyinfo *, polinfo); +static DEFINE_PER_CPU(struct cpufreq_interactive_cpuinfo, cpuinfo); + +/* realtime thread handles frequency scaling */ +static struct task_struct *speedchange_task; +static cpumask_t speedchange_cpumask; +static spinlock_t speedchange_cpumask_lock; +static struct mutex gov_lock; + +static int set_window_count; +static int migration_register_count; +static struct mutex sched_lock; +static cpumask_t controlled_cpus; + +/* Target load. Lower values result in higher CPU speeds. */ +#define DEFAULT_TARGET_LOAD 90 +static unsigned int default_target_loads[] = {DEFAULT_TARGET_LOAD}; + +#define DEFAULT_TIMER_RATE (20 * USEC_PER_MSEC) +#define DEFAULT_ABOVE_HISPEED_DELAY DEFAULT_TIMER_RATE +static unsigned int default_above_hispeed_delay[] = { + DEFAULT_ABOVE_HISPEED_DELAY }; + +struct cpufreq_interactive_tunables { + int usage_count; + /* Hi speed to bump to from lo speed when load burst (default max) */ + unsigned int hispeed_freq; + /* Go to hi speed when CPU load at or above this value. */ +#define DEFAULT_GO_HISPEED_LOAD 99 + unsigned long go_hispeed_load; + /* Target load. Lower values result in higher CPU speeds. */ + spinlock_t target_loads_lock; + unsigned int *target_loads; + int ntarget_loads; + /* + * The minimum amount of time to spend at a frequency before we can ramp + * down. + */ +#define DEFAULT_MIN_SAMPLE_TIME (80 * USEC_PER_MSEC) + unsigned long min_sample_time; + /* + * The sample rate of the timer used to increase frequency + */ + unsigned long timer_rate; + /* + * Wait this long before raising speed above hispeed, by default a + * single timer interval. + */ + spinlock_t above_hispeed_delay_lock; + unsigned int *above_hispeed_delay; + int nabove_hispeed_delay; + /* Non-zero means indefinite speed boost active */ + int boost_val; + /* Duration of a boot pulse in usecs */ + int boostpulse_duration_val; + /* End time of boost pulse in ktime converted to usecs */ + u64 boostpulse_endtime; + bool boosted; + /* + * Max additional time to wait in idle, beyond timer_rate, at speeds + * above minimum before wakeup to reduce speed, or -1 if unnecessary. + */ +#define DEFAULT_TIMER_SLACK (4 * DEFAULT_TIMER_RATE) + int timer_slack_val; + bool io_is_busy; + + /* scheduler input related flags */ + bool use_sched_load; + bool use_migration_notif; + + /* + * Whether to align timer windows across all CPUs. When + * use_sched_load is true, this flag is ignored and windows + * will always be aligned. + */ + bool align_windows; + + /* + * Stay at max freq for at least max_freq_hysteresis before dropping + * frequency. + */ + unsigned int max_freq_hysteresis; + + /* Ignore hispeed_freq and above_hispeed_delay for notification */ + bool ignore_hispeed_on_notif; + + /* Ignore min_sample_time for notification */ + bool fast_ramp_down; + + /* Whether to enable prediction or not */ + bool enable_prediction; +}; + +/* For cases where we have single governor instance for system */ +static struct cpufreq_interactive_tunables *common_tunables; +static struct cpufreq_interactive_tunables *cached_common_tunables; + +static struct attribute_group *get_sysfs_attr(void); + +/* Round to starting jiffy of next evaluation window */ +static u64 round_to_nw_start(u64 jif, + struct cpufreq_interactive_tunables *tunables) +{ + unsigned long step = usecs_to_jiffies(tunables->timer_rate); + u64 ret; + + if (tunables->use_sched_load || tunables->align_windows) { + do_div(jif, step); + ret = (jif + 1) * step; + } else { + ret = jiffies + usecs_to_jiffies(tunables->timer_rate); + } + + return ret; +} + +static inline int set_window_helper( + struct cpufreq_interactive_tunables *tunables) +{ + return sched_set_window(round_to_nw_start(get_jiffies_64(), tunables), + usecs_to_jiffies(tunables->timer_rate)); +} + +static void cpufreq_interactive_timer_resched(unsigned long cpu, + bool slack_only) +{ + struct cpufreq_interactive_policyinfo *ppol = per_cpu(polinfo, cpu); + struct cpufreq_interactive_cpuinfo *pcpu; + struct cpufreq_interactive_tunables *tunables = + ppol->policy->governor_data; + u64 expires; + unsigned long flags; + int i; + + spin_lock_irqsave(&ppol->load_lock, flags); + expires = round_to_nw_start(ppol->last_evaluated_jiffy, tunables); + if (!slack_only) { + for_each_cpu(i, ppol->policy->cpus) { + pcpu = &per_cpu(cpuinfo, i); + pcpu->time_in_idle = get_cpu_idle_time(i, + &pcpu->time_in_idle_timestamp, + tunables->io_is_busy); + pcpu->cputime_speedadj = 0; + pcpu->cputime_speedadj_timestamp = + pcpu->time_in_idle_timestamp; + } + del_timer(&ppol->policy_timer); + ppol->policy_timer.expires = expires; + add_timer(&ppol->policy_timer); + } + + if (tunables->timer_slack_val >= 0 && + ppol->target_freq > ppol->policy->min) { + expires += usecs_to_jiffies(tunables->timer_slack_val); + del_timer(&ppol->policy_slack_timer); + ppol->policy_slack_timer.expires = expires; + add_timer(&ppol->policy_slack_timer); + } + + spin_unlock_irqrestore(&ppol->load_lock, flags); +} + +/* The caller shall take enable_sem write semaphore to avoid any timer race. + * The policy_timer and policy_slack_timer must be deactivated when calling + * this function. + */ +static void cpufreq_interactive_timer_start( + struct cpufreq_interactive_tunables *tunables, int cpu) +{ + struct cpufreq_interactive_policyinfo *ppol = per_cpu(polinfo, cpu); + struct cpufreq_interactive_cpuinfo *pcpu; + u64 expires = round_to_nw_start(ppol->last_evaluated_jiffy, tunables); + unsigned long flags; + int i; + + spin_lock_irqsave(&ppol->load_lock, flags); + ppol->policy_timer.expires = expires; + add_timer(&ppol->policy_timer); + if (tunables->timer_slack_val >= 0 && + ppol->target_freq > ppol->policy->min) { + expires += usecs_to_jiffies(tunables->timer_slack_val); + ppol->policy_slack_timer.expires = expires; + add_timer(&ppol->policy_slack_timer); + } + + for_each_cpu(i, ppol->policy->cpus) { + pcpu = &per_cpu(cpuinfo, i); + pcpu->time_in_idle = + get_cpu_idle_time(i, &pcpu->time_in_idle_timestamp, + tunables->io_is_busy); + pcpu->cputime_speedadj = 0; + pcpu->cputime_speedadj_timestamp = pcpu->time_in_idle_timestamp; + } + spin_unlock_irqrestore(&ppol->load_lock, flags); +} + +static unsigned int freq_to_above_hispeed_delay( + struct cpufreq_interactive_tunables *tunables, + unsigned int freq) +{ + int i; + unsigned int ret; + unsigned long flags; + + spin_lock_irqsave(&tunables->above_hispeed_delay_lock, flags); + + for (i = 0; i < tunables->nabove_hispeed_delay - 1 && + freq >= tunables->above_hispeed_delay[i+1]; i += 2) + ; + + ret = tunables->above_hispeed_delay[i]; + spin_unlock_irqrestore(&tunables->above_hispeed_delay_lock, flags); + return ret; +} + +static unsigned int freq_to_targetload( + struct cpufreq_interactive_tunables *tunables, unsigned int freq) +{ + int i; + unsigned int ret; + unsigned long flags; + + spin_lock_irqsave(&tunables->target_loads_lock, flags); + + for (i = 0; i < tunables->ntarget_loads - 1 && + freq >= tunables->target_loads[i+1]; i += 2) + ; + + ret = tunables->target_loads[i]; + spin_unlock_irqrestore(&tunables->target_loads_lock, flags); + return ret; +} + +#define DEFAULT_MAX_LOAD 100 +u32 get_freq_max_load(int cpu, unsigned int freq) +{ + struct cpufreq_interactive_policyinfo *ppol = per_cpu(polinfo, cpu); + + if (!cpumask_test_cpu(cpu, &controlled_cpus)) + return DEFAULT_MAX_LOAD; + + if (have_governor_per_policy()) { + if (!ppol || !ppol->cached_tunables) + return DEFAULT_MAX_LOAD; + return freq_to_targetload(ppol->cached_tunables, freq); + } + + if (!cached_common_tunables) + return DEFAULT_MAX_LOAD; + return freq_to_targetload(cached_common_tunables, freq); +} + +/* + * If increasing frequencies never map to a lower target load then + * choose_freq() will find the minimum frequency that does not exceed its + * target load given the current load. + */ +static unsigned int choose_freq(struct cpufreq_interactive_policyinfo *pcpu, + unsigned int loadadjfreq) +{ + unsigned int freq = pcpu->policy->cur; + unsigned int prevfreq, freqmin, freqmax; + unsigned int tl; + int index; + + freqmin = 0; + freqmax = UINT_MAX; + + do { + prevfreq = freq; + tl = freq_to_targetload(pcpu->policy->governor_data, freq); + + /* + * Find the lowest frequency where the computed load is less + * than or equal to the target load. + */ + + if (cpufreq_frequency_table_target( + &pcpu->p_nolim, pcpu->freq_table, loadadjfreq / tl, + CPUFREQ_RELATION_L, &index)) + break; + freq = pcpu->freq_table[index].frequency; + + if (freq > prevfreq) { + /* The previous frequency is too low. */ + freqmin = prevfreq; + + if (freq >= freqmax) { + /* + * Find the highest frequency that is less + * than freqmax. + */ + if (cpufreq_frequency_table_target( + &pcpu->p_nolim, pcpu->freq_table, + freqmax - 1, CPUFREQ_RELATION_H, + &index)) + break; + freq = pcpu->freq_table[index].frequency; + + if (freq == freqmin) { + /* + * The first frequency below freqmax + * has already been found to be too + * low. freqmax is the lowest speed + * we found that is fast enough. + */ + freq = freqmax; + break; + } + } + } else if (freq < prevfreq) { + /* The previous frequency is high enough. */ + freqmax = prevfreq; + + if (freq <= freqmin) { + /* + * Find the lowest frequency that is higher + * than freqmin. + */ + if (cpufreq_frequency_table_target( + &pcpu->p_nolim, pcpu->freq_table, + freqmin + 1, CPUFREQ_RELATION_L, + &index)) + break; + freq = pcpu->freq_table[index].frequency; + + /* + * If freqmax is the first frequency above + * freqmin then we have already found that + * this speed is fast enough. + */ + if (freq == freqmax) + break; + } + } + + /* If same frequency chosen as previous then done. */ + } while (freq != prevfreq); + + return freq; +} + +static u64 update_load(int cpu) +{ + struct cpufreq_interactive_policyinfo *ppol = per_cpu(polinfo, cpu); + struct cpufreq_interactive_cpuinfo *pcpu = &per_cpu(cpuinfo, cpu); + struct cpufreq_interactive_tunables *tunables = + ppol->policy->governor_data; + u64 now; + u64 now_idle; + u64 delta_idle; + u64 delta_time; + u64 active_time; + + now_idle = get_cpu_idle_time(cpu, &now, tunables->io_is_busy); + delta_idle = (now_idle - pcpu->time_in_idle); + delta_time = (now - pcpu->time_in_idle_timestamp); + + if (delta_time <= delta_idle) + active_time = 0; + else + active_time = delta_time - delta_idle; + + pcpu->cputime_speedadj += active_time * ppol->policy->cur; + + pcpu->time_in_idle = now_idle; + pcpu->time_in_idle_timestamp = now; + return now; +} + +static unsigned int sl_busy_to_laf(struct cpufreq_interactive_policyinfo *ppol, + unsigned long busy) +{ + int prev_load; + struct cpufreq_interactive_tunables *tunables = + ppol->policy->governor_data; + + prev_load = mult_frac(ppol->policy->cpuinfo.max_freq * 100, + busy, tunables->timer_rate); + return prev_load; +} + +#define NEW_TASK_RATIO 75 +#define PRED_TOLERANCE_PCT 10 +static void cpufreq_interactive_timer(unsigned long data) +{ + s64 now; + unsigned int delta_time; + u64 cputime_speedadj; + int cpu_load; + int pol_load = 0; + struct cpufreq_interactive_policyinfo *ppol = per_cpu(polinfo, data); + struct cpufreq_interactive_tunables *tunables = + ppol->policy->governor_data; + struct sched_load *sl = ppol->sl; + struct cpufreq_interactive_cpuinfo *pcpu; + unsigned int new_freq; + unsigned int prev_laf = 0, t_prevlaf; + unsigned int pred_laf = 0, t_predlaf = 0; + unsigned int prev_chfreq, pred_chfreq, chosen_freq; + unsigned int index; + unsigned long flags; + unsigned long max_cpu; + int cpu, i; + int new_load_pct = 0; + int prev_l, pred_l = 0; + struct cpufreq_govinfo govinfo; + bool skip_hispeed_logic, skip_min_sample_time; + bool jump_to_max_no_ts = false; + bool jump_to_max = false; + bool start_hyst = true; + + if (!down_read_trylock(&ppol->enable_sem)) + return; + if (!ppol->governor_enabled) + goto exit; + + now = ktime_to_us(ktime_get()); + + spin_lock_irqsave(&ppol->target_freq_lock, flags); + spin_lock(&ppol->load_lock); + + skip_hispeed_logic = + tunables->ignore_hispeed_on_notif && ppol->notif_pending; + skip_min_sample_time = tunables->fast_ramp_down && ppol->notif_pending; + ppol->notif_pending = false; + now = ktime_to_us(ktime_get()); + ppol->last_evaluated_jiffy = get_jiffies_64(); + + if (tunables->use_sched_load) + sched_get_cpus_busy(sl, ppol->policy->cpus); + max_cpu = cpumask_first(ppol->policy->cpus); + i = 0; + for_each_cpu(cpu, ppol->policy->cpus) { + pcpu = &per_cpu(cpuinfo, cpu); + if (tunables->use_sched_load) { + t_prevlaf = sl_busy_to_laf(ppol, sl[i].prev_load); + prev_l = t_prevlaf / ppol->target_freq; + if (tunables->enable_prediction) { + t_predlaf = sl_busy_to_laf(ppol, + sl[i].predicted_load); + pred_l = t_predlaf / ppol->target_freq; + } + if (sl[i].prev_load) + new_load_pct = sl[i].new_task_load * 100 / + sl[i].prev_load; + else + new_load_pct = 0; + } else { + now = update_load(cpu); + delta_time = (unsigned int) + (now - pcpu->cputime_speedadj_timestamp); + if (WARN_ON_ONCE(!delta_time)) + continue; + cputime_speedadj = pcpu->cputime_speedadj; + do_div(cputime_speedadj, delta_time); + t_prevlaf = (unsigned int)cputime_speedadj * 100; + prev_l = t_prevlaf / ppol->target_freq; + } + + /* find max of loadadjfreq inside policy */ + if (t_prevlaf > prev_laf) { + prev_laf = t_prevlaf; + max_cpu = cpu; + } + pred_laf = max(t_predlaf, pred_laf); + + cpu_load = max(prev_l, pred_l); + pol_load = max(pol_load, cpu_load); + trace_cpufreq_interactive_cpuload(cpu, cpu_load, new_load_pct, + prev_l, pred_l); + + /* save loadadjfreq for notification */ + pcpu->loadadjfreq = max(t_prevlaf, t_predlaf); + + /* detect heavy new task and jump to policy->max */ + if (prev_l >= tunables->go_hispeed_load && + new_load_pct >= NEW_TASK_RATIO) { + skip_hispeed_logic = true; + jump_to_max = true; + } + i++; + } + spin_unlock(&ppol->load_lock); + + tunables->boosted = tunables->boost_val || now < tunables->boostpulse_endtime; + + prev_chfreq = choose_freq(ppol, prev_laf); + pred_chfreq = choose_freq(ppol, pred_laf); + chosen_freq = max(prev_chfreq, pred_chfreq); + + if (prev_chfreq < ppol->policy->max && pred_chfreq >= ppol->policy->max) + if (!jump_to_max) + jump_to_max_no_ts = true; + + if (now - ppol->max_freq_hyst_start_time < + tunables->max_freq_hysteresis && + pol_load >= tunables->go_hispeed_load && + ppol->target_freq < ppol->policy->max) { + skip_hispeed_logic = true; + skip_min_sample_time = true; + if (!jump_to_max) + jump_to_max_no_ts = true; + } + + new_freq = chosen_freq; + if (jump_to_max_no_ts || jump_to_max) { + new_freq = ppol->policy->cpuinfo.max_freq; + } else if (!skip_hispeed_logic) { + if (pol_load >= tunables->go_hispeed_load || + tunables->boosted) { + if (ppol->target_freq < tunables->hispeed_freq) + new_freq = tunables->hispeed_freq; + else + new_freq = max(new_freq, + tunables->hispeed_freq); + } + } + + if (now - ppol->max_freq_hyst_start_time < + tunables->max_freq_hysteresis) { + if (new_freq < ppol->policy->max && + ppol->policy->max <= tunables->hispeed_freq) + start_hyst = false; + new_freq = max(tunables->hispeed_freq, new_freq); + } + + if (!skip_hispeed_logic && + ppol->target_freq >= tunables->hispeed_freq && + new_freq > ppol->target_freq && + now - ppol->hispeed_validate_time < + freq_to_above_hispeed_delay(tunables, ppol->target_freq)) { + trace_cpufreq_interactive_notyet( + max_cpu, pol_load, ppol->target_freq, + ppol->policy->cur, new_freq); + spin_unlock_irqrestore(&ppol->target_freq_lock, flags); + goto rearm; + } + + ppol->hispeed_validate_time = now; + + if (cpufreq_frequency_table_target(&ppol->p_nolim, ppol->freq_table, + new_freq, CPUFREQ_RELATION_L, + &index)) { + spin_unlock_irqrestore(&ppol->target_freq_lock, flags); + goto rearm; + } + + new_freq = ppol->freq_table[index].frequency; + + /* + * Do not scale below floor_freq unless we have been at or above the + * floor frequency for the minimum sample time since last validated. + */ + if (!skip_min_sample_time && new_freq < ppol->floor_freq) { + if (now - ppol->floor_validate_time < + tunables->min_sample_time) { + trace_cpufreq_interactive_notyet( + max_cpu, pol_load, ppol->target_freq, + ppol->policy->cur, new_freq); + spin_unlock_irqrestore(&ppol->target_freq_lock, flags); + goto rearm; + } + } + + /* + * Update the timestamp for checking whether speed has been held at + * or above the selected frequency for a minimum of min_sample_time, + * if not boosted to hispeed_freq. If boosted to hispeed_freq then we + * allow the speed to drop as soon as the boostpulse duration expires + * (or the indefinite boost is turned off). If policy->max is restored + * for max_freq_hysteresis, don't extend the timestamp. Otherwise, it + * could incorrectly extended the duration of max_freq_hysteresis by + * min_sample_time. + */ + + if ((!tunables->boosted || new_freq > tunables->hispeed_freq) + && !jump_to_max_no_ts) { + ppol->floor_freq = new_freq; + ppol->floor_validate_time = now; + } + + if (start_hyst && new_freq >= ppol->policy->max && !jump_to_max_no_ts) + ppol->max_freq_hyst_start_time = now; + + if (ppol->target_freq == new_freq && + ppol->target_freq <= ppol->policy->cur) { + trace_cpufreq_interactive_already( + max_cpu, pol_load, ppol->target_freq, + ppol->policy->cur, new_freq); + spin_unlock_irqrestore(&ppol->target_freq_lock, flags); + goto rearm; + } + + trace_cpufreq_interactive_target(max_cpu, pol_load, ppol->target_freq, + ppol->policy->cur, new_freq); + + ppol->target_freq = new_freq; + spin_unlock_irqrestore(&ppol->target_freq_lock, flags); + spin_lock_irqsave(&speedchange_cpumask_lock, flags); + cpumask_set_cpu(max_cpu, &speedchange_cpumask); + spin_unlock_irqrestore(&speedchange_cpumask_lock, flags); + wake_up_process_no_notif(speedchange_task); + +rearm: + if (!timer_pending(&ppol->policy_timer)) + cpufreq_interactive_timer_resched(data, false); + + /* + * Send govinfo notification. + * Govinfo notification could potentially wake up another thread + * managed by its clients. Thread wakeups might trigger a load + * change callback that executes this function again. Therefore + * no spinlock could be held when sending the notification. + */ + for_each_cpu(i, ppol->policy->cpus) { + pcpu = &per_cpu(cpuinfo, i); + govinfo.cpu = i; + govinfo.load = pcpu->loadadjfreq / ppol->policy->max; + govinfo.sampling_rate_us = tunables->timer_rate; + atomic_notifier_call_chain(&cpufreq_govinfo_notifier_list, + CPUFREQ_LOAD_CHANGE, &govinfo); + } + +exit: + up_read(&ppol->enable_sem); + return; +} + +static int cpufreq_interactive_speedchange_task(void *data) +{ + unsigned int cpu; + cpumask_t tmp_mask; + unsigned long flags; + struct cpufreq_interactive_policyinfo *ppol; + + while (1) { + set_current_state(TASK_INTERRUPTIBLE); + spin_lock_irqsave(&speedchange_cpumask_lock, flags); + + if (cpumask_empty(&speedchange_cpumask)) { + spin_unlock_irqrestore(&speedchange_cpumask_lock, + flags); + schedule(); + + if (kthread_should_stop()) + break; + + spin_lock_irqsave(&speedchange_cpumask_lock, flags); + } + + set_current_state(TASK_RUNNING); + tmp_mask = speedchange_cpumask; + cpumask_clear(&speedchange_cpumask); + spin_unlock_irqrestore(&speedchange_cpumask_lock, flags); + + for_each_cpu(cpu, &tmp_mask) { + ppol = per_cpu(polinfo, cpu); + if (!down_read_trylock(&ppol->enable_sem)) + continue; + if (!ppol->governor_enabled) { + up_read(&ppol->enable_sem); + continue; + } + + if (ppol->target_freq != ppol->policy->cur) + __cpufreq_driver_target(ppol->policy, + ppol->target_freq, + CPUFREQ_RELATION_H); + trace_cpufreq_interactive_setspeed(cpu, + ppol->target_freq, + ppol->policy->cur); + up_read(&ppol->enable_sem); + } + } + + return 0; +} + +static void cpufreq_interactive_boost(struct cpufreq_interactive_tunables *tunables) +{ + int i; + int anyboost = 0; + unsigned long flags[2]; + struct cpufreq_interactive_policyinfo *ppol; + + tunables->boosted = true; + + spin_lock_irqsave(&speedchange_cpumask_lock, flags[0]); + + for_each_online_cpu(i) { + ppol = per_cpu(polinfo, i); + if (!ppol || tunables != ppol->policy->governor_data) + continue; + + spin_lock_irqsave(&ppol->target_freq_lock, flags[1]); + if (ppol->target_freq < tunables->hispeed_freq) { + ppol->target_freq = tunables->hispeed_freq; + cpumask_set_cpu(i, &speedchange_cpumask); + ppol->hispeed_validate_time = + ktime_to_us(ktime_get()); + anyboost = 1; + } + + /* + * Set floor freq and (re)start timer for when last + * validated. + */ + + ppol->floor_freq = tunables->hispeed_freq; + ppol->floor_validate_time = ktime_to_us(ktime_get()); + spin_unlock_irqrestore(&ppol->target_freq_lock, flags[1]); + break; + } + + spin_unlock_irqrestore(&speedchange_cpumask_lock, flags[0]); + + if (anyboost) + wake_up_process_no_notif(speedchange_task); +} + +static int load_change_callback(struct notifier_block *nb, unsigned long val, + void *data) +{ + unsigned long cpu = (unsigned long) data; + struct cpufreq_interactive_policyinfo *ppol = per_cpu(polinfo, cpu); + struct cpufreq_interactive_tunables *tunables; + unsigned long flags; + + if (!ppol || ppol->reject_notification) + return 0; + + if (!down_read_trylock(&ppol->enable_sem)) + return 0; + if (!ppol->governor_enabled) + goto exit; + + tunables = ppol->policy->governor_data; + if (!tunables->use_sched_load || !tunables->use_migration_notif) + goto exit; + + spin_lock_irqsave(&ppol->target_freq_lock, flags); + ppol->notif_pending = true; + ppol->notif_cpu = cpu; + spin_unlock_irqrestore(&ppol->target_freq_lock, flags); + + if (!hrtimer_is_queued(&ppol->notif_timer)) + hrtimer_start(&ppol->notif_timer, ms_to_ktime(1), + HRTIMER_MODE_REL); +exit: + up_read(&ppol->enable_sem); + return 0; +} + +static enum hrtimer_restart cpufreq_interactive_hrtimer(struct hrtimer *timer) +{ + struct cpufreq_interactive_policyinfo *ppol = container_of(timer, + struct cpufreq_interactive_policyinfo, notif_timer); + int cpu; + + if (!down_read_trylock(&ppol->enable_sem)) + return 0; + if (!ppol->governor_enabled) { + up_read(&ppol->enable_sem); + return 0; + } + cpu = ppol->notif_cpu; + trace_cpufreq_interactive_load_change(cpu); + del_timer(&ppol->policy_timer); + del_timer(&ppol->policy_slack_timer); + cpufreq_interactive_timer(cpu); + + up_read(&ppol->enable_sem); + return HRTIMER_NORESTART; +} + +static struct notifier_block load_notifier_block = { + .notifier_call = load_change_callback, +}; + +static int cpufreq_interactive_notifier( + struct notifier_block *nb, unsigned long val, void *data) +{ + struct cpufreq_freqs *freq = data; + struct cpufreq_interactive_policyinfo *ppol; + int cpu; + unsigned long flags; + + if (val == CPUFREQ_POSTCHANGE) { + ppol = per_cpu(polinfo, freq->cpu); + if (!ppol) + return 0; + if (!down_read_trylock(&ppol->enable_sem)) + return 0; + if (!ppol->governor_enabled) { + up_read(&ppol->enable_sem); + return 0; + } + + if (cpumask_first(ppol->policy->cpus) != freq->cpu) { + up_read(&ppol->enable_sem); + return 0; + } + spin_lock_irqsave(&ppol->load_lock, flags); + for_each_cpu(cpu, ppol->policy->cpus) + update_load(cpu); + spin_unlock_irqrestore(&ppol->load_lock, flags); + + up_read(&ppol->enable_sem); + } + return 0; +} + +static struct notifier_block cpufreq_notifier_block = { + .notifier_call = cpufreq_interactive_notifier, +}; + +static unsigned int *get_tokenized_data(const char *buf, int *num_tokens) +{ + const char *cp; + int i; + int ntokens = 1; + unsigned int *tokenized_data; + int err = -EINVAL; + + cp = buf; + while ((cp = strpbrk(cp + 1, " :"))) + ntokens++; + + if (!(ntokens & 0x1)) + goto err; + + tokenized_data = kmalloc(ntokens * sizeof(unsigned int), GFP_KERNEL); + if (!tokenized_data) { + err = -ENOMEM; + goto err; + } + + cp = buf; + i = 0; + while (i < ntokens) { + if (sscanf(cp, "%u", &tokenized_data[i++]) != 1) + goto err_kfree; + + cp = strpbrk(cp, " :"); + if (!cp) + break; + cp++; + } + + if (i != ntokens) + goto err_kfree; + + *num_tokens = ntokens; + return tokenized_data; + +err_kfree: + kfree(tokenized_data); +err: + return ERR_PTR(err); +} + +static ssize_t show_target_loads( + struct cpufreq_interactive_tunables *tunables, + char *buf) +{ + int i; + ssize_t ret = 0; + unsigned long flags; + + spin_lock_irqsave(&tunables->target_loads_lock, flags); + + for (i = 0; i < tunables->ntarget_loads; i++) + ret += sprintf(buf + ret, "%u%s", tunables->target_loads[i], + i & 0x1 ? ":" : " "); + + sprintf(buf + ret - 1, "\n"); + spin_unlock_irqrestore(&tunables->target_loads_lock, flags); + return ret; +} + +static ssize_t store_target_loads( + struct cpufreq_interactive_tunables *tunables, + const char *buf, size_t count) +{ + int ntokens; + unsigned int *new_target_loads = NULL; + unsigned long flags; + + new_target_loads = get_tokenized_data(buf, &ntokens); + if (IS_ERR(new_target_loads)) + return PTR_RET(new_target_loads); + + spin_lock_irqsave(&tunables->target_loads_lock, flags); + if (tunables->target_loads != default_target_loads) + kfree(tunables->target_loads); + tunables->target_loads = new_target_loads; + tunables->ntarget_loads = ntokens; + spin_unlock_irqrestore(&tunables->target_loads_lock, flags); + + sched_update_freq_max_load(&controlled_cpus); + + return count; +} + +static ssize_t show_above_hispeed_delay( + struct cpufreq_interactive_tunables *tunables, char *buf) +{ + int i; + ssize_t ret = 0; + unsigned long flags; + + spin_lock_irqsave(&tunables->above_hispeed_delay_lock, flags); + + for (i = 0; i < tunables->nabove_hispeed_delay; i++) + ret += sprintf(buf + ret, "%u%s", + tunables->above_hispeed_delay[i], + i & 0x1 ? ":" : " "); + + sprintf(buf + ret - 1, "\n"); + spin_unlock_irqrestore(&tunables->above_hispeed_delay_lock, flags); + return ret; +} + +static ssize_t store_above_hispeed_delay( + struct cpufreq_interactive_tunables *tunables, + const char *buf, size_t count) +{ + int ntokens; + unsigned int *new_above_hispeed_delay = NULL; + unsigned long flags; + + new_above_hispeed_delay = get_tokenized_data(buf, &ntokens); + if (IS_ERR(new_above_hispeed_delay)) + return PTR_RET(new_above_hispeed_delay); + + spin_lock_irqsave(&tunables->above_hispeed_delay_lock, flags); + if (tunables->above_hispeed_delay != default_above_hispeed_delay) + kfree(tunables->above_hispeed_delay); + tunables->above_hispeed_delay = new_above_hispeed_delay; + tunables->nabove_hispeed_delay = ntokens; + spin_unlock_irqrestore(&tunables->above_hispeed_delay_lock, flags); + return count; + +} + +static ssize_t show_hispeed_freq(struct cpufreq_interactive_tunables *tunables, + char *buf) +{ + return sprintf(buf, "%u\n", tunables->hispeed_freq); +} + +static ssize_t store_hispeed_freq(struct cpufreq_interactive_tunables *tunables, + const char *buf, size_t count) +{ + int ret; + long unsigned int val; + + ret = kstrtoul(buf, 0, &val); + if (ret < 0) + return ret; + tunables->hispeed_freq = val; + return count; +} + +#define show_store_one(file_name) \ +static ssize_t show_##file_name( \ + struct cpufreq_interactive_tunables *tunables, char *buf) \ +{ \ + return snprintf(buf, PAGE_SIZE, "%u\n", tunables->file_name); \ +} \ +static ssize_t store_##file_name( \ + struct cpufreq_interactive_tunables *tunables, \ + const char *buf, size_t count) \ +{ \ + int ret; \ + unsigned long int val; \ + \ + ret = kstrtoul(buf, 0, &val); \ + if (ret < 0) \ + return ret; \ + tunables->file_name = val; \ + return count; \ +} +show_store_one(max_freq_hysteresis); +show_store_one(align_windows); +show_store_one(ignore_hispeed_on_notif); +show_store_one(fast_ramp_down); +show_store_one(enable_prediction); + +static ssize_t show_go_hispeed_load(struct cpufreq_interactive_tunables + *tunables, char *buf) +{ + return sprintf(buf, "%lu\n", tunables->go_hispeed_load); +} + +static ssize_t store_go_hispeed_load(struct cpufreq_interactive_tunables + *tunables, const char *buf, size_t count) +{ + int ret; + unsigned long val; + + ret = kstrtoul(buf, 0, &val); + if (ret < 0) + return ret; + tunables->go_hispeed_load = val; + return count; +} + +static ssize_t show_min_sample_time(struct cpufreq_interactive_tunables + *tunables, char *buf) +{ + return sprintf(buf, "%lu\n", tunables->min_sample_time); +} + +static ssize_t store_min_sample_time(struct cpufreq_interactive_tunables + *tunables, const char *buf, size_t count) +{ + int ret; + unsigned long val; + + ret = kstrtoul(buf, 0, &val); + if (ret < 0) + return ret; + tunables->min_sample_time = val; + return count; +} + +static ssize_t show_timer_rate(struct cpufreq_interactive_tunables *tunables, + char *buf) +{ + return sprintf(buf, "%lu\n", tunables->timer_rate); +} + +static ssize_t store_timer_rate(struct cpufreq_interactive_tunables *tunables, + const char *buf, size_t count) +{ + int ret; + unsigned long val, val_round; + struct cpufreq_interactive_tunables *t; + int cpu; + + ret = kstrtoul(buf, 0, &val); + if (ret < 0) + return ret; + + val_round = jiffies_to_usecs(usecs_to_jiffies(val)); + if (val != val_round) + pr_warn("timer_rate not aligned to jiffy. Rounded up to %lu\n", + val_round); + tunables->timer_rate = val_round; + + if (!tunables->use_sched_load) + return count; + + for_each_possible_cpu(cpu) { + if (!per_cpu(polinfo, cpu)) + continue; + t = per_cpu(polinfo, cpu)->cached_tunables; + if (t && t->use_sched_load) + t->timer_rate = val_round; + } + set_window_helper(tunables); + + return count; +} + +static ssize_t show_timer_slack(struct cpufreq_interactive_tunables *tunables, + char *buf) +{ + return sprintf(buf, "%d\n", tunables->timer_slack_val); +} + +static ssize_t store_timer_slack(struct cpufreq_interactive_tunables *tunables, + const char *buf, size_t count) +{ + int ret; + unsigned long val; + + ret = kstrtol(buf, 10, &val); + if (ret < 0) + return ret; + + tunables->timer_slack_val = val; + return count; +} + +static ssize_t show_boost(struct cpufreq_interactive_tunables *tunables, + char *buf) +{ + return sprintf(buf, "%d\n", tunables->boost_val); +} + +static ssize_t store_boost(struct cpufreq_interactive_tunables *tunables, + const char *buf, size_t count) +{ + int ret; + unsigned long val; + + ret = kstrtoul(buf, 0, &val); + if (ret < 0) + return ret; + + tunables->boost_val = val; + + if (tunables->boost_val) { + trace_cpufreq_interactive_boost("on"); + if (!tunables->boosted) + cpufreq_interactive_boost(tunables); + } else { + tunables->boostpulse_endtime = ktime_to_us(ktime_get()); + trace_cpufreq_interactive_unboost("off"); + } + + return count; +} + +static ssize_t store_boostpulse(struct cpufreq_interactive_tunables *tunables, + const char *buf, size_t count) +{ + int ret; + unsigned long val; + + ret = kstrtoul(buf, 0, &val); + if (ret < 0) + return ret; + + tunables->boostpulse_endtime = ktime_to_us(ktime_get()) + + tunables->boostpulse_duration_val; + trace_cpufreq_interactive_boost("pulse"); + if (!tunables->boosted) + cpufreq_interactive_boost(tunables); + return count; +} + +static ssize_t show_boostpulse_duration(struct cpufreq_interactive_tunables + *tunables, char *buf) +{ + return sprintf(buf, "%d\n", tunables->boostpulse_duration_val); +} + +static ssize_t store_boostpulse_duration(struct cpufreq_interactive_tunables + *tunables, const char *buf, size_t count) +{ + int ret; + unsigned long val; + + ret = kstrtoul(buf, 0, &val); + if (ret < 0) + return ret; + + tunables->boostpulse_duration_val = val; + return count; +} + +static ssize_t show_io_is_busy(struct cpufreq_interactive_tunables *tunables, + char *buf) +{ + return sprintf(buf, "%u\n", tunables->io_is_busy); +} + +static ssize_t store_io_is_busy(struct cpufreq_interactive_tunables *tunables, + const char *buf, size_t count) +{ + int ret; + unsigned long val; + struct cpufreq_interactive_tunables *t; + int cpu; + + ret = kstrtoul(buf, 0, &val); + if (ret < 0) + return ret; + tunables->io_is_busy = val; + + if (!tunables->use_sched_load) + return count; + + for_each_possible_cpu(cpu) { + if (!per_cpu(polinfo, cpu)) + continue; + t = per_cpu(polinfo, cpu)->cached_tunables; + if (t && t->use_sched_load) + t->io_is_busy = val; + } + sched_set_io_is_busy(val); + + return count; +} + +static int cpufreq_interactive_enable_sched_input( + struct cpufreq_interactive_tunables *tunables) +{ + int rc = 0, j; + struct cpufreq_interactive_tunables *t; + + mutex_lock(&sched_lock); + + set_window_count++; + if (set_window_count > 1) { + for_each_possible_cpu(j) { + if (!per_cpu(polinfo, j)) + continue; + t = per_cpu(polinfo, j)->cached_tunables; + if (t && t->use_sched_load) { + tunables->timer_rate = t->timer_rate; + tunables->io_is_busy = t->io_is_busy; + break; + } + } + } else { + rc = set_window_helper(tunables); + if (rc) { + pr_err("%s: Failed to set sched window\n", __func__); + set_window_count--; + goto out; + } + sched_set_io_is_busy(tunables->io_is_busy); + } + + if (!tunables->use_migration_notif) + goto out; + + migration_register_count++; + if (migration_register_count > 1) + goto out; + else + atomic_notifier_chain_register(&load_alert_notifier_head, + &load_notifier_block); +out: + mutex_unlock(&sched_lock); + return rc; +} + +static int cpufreq_interactive_disable_sched_input( + struct cpufreq_interactive_tunables *tunables) +{ + mutex_lock(&sched_lock); + + if (tunables->use_migration_notif) { + migration_register_count--; + if (migration_register_count < 1) + atomic_notifier_chain_unregister( + &load_alert_notifier_head, + &load_notifier_block); + } + set_window_count--; + + mutex_unlock(&sched_lock); + return 0; +} + +static ssize_t show_use_sched_load( + struct cpufreq_interactive_tunables *tunables, char *buf) +{ + return snprintf(buf, PAGE_SIZE, "%d\n", tunables->use_sched_load); +} + +static ssize_t store_use_sched_load( + struct cpufreq_interactive_tunables *tunables, + const char *buf, size_t count) +{ + int ret; + unsigned long val; + + ret = kstrtoul(buf, 0, &val); + if (ret < 0) + return ret; + + if (tunables->use_sched_load == (bool) val) + return count; + + tunables->use_sched_load = val; + + if (val) + ret = cpufreq_interactive_enable_sched_input(tunables); + else + ret = cpufreq_interactive_disable_sched_input(tunables); + + if (ret) { + tunables->use_sched_load = !val; + return ret; + } + + return count; +} + +static ssize_t show_use_migration_notif( + struct cpufreq_interactive_tunables *tunables, char *buf) +{ + return snprintf(buf, PAGE_SIZE, "%d\n", + tunables->use_migration_notif); +} + +static ssize_t store_use_migration_notif( + struct cpufreq_interactive_tunables *tunables, + const char *buf, size_t count) +{ + int ret; + unsigned long val; + + ret = kstrtoul(buf, 0, &val); + if (ret < 0) + return ret; + + if (tunables->use_migration_notif == (bool) val) + return count; + tunables->use_migration_notif = val; + + if (!tunables->use_sched_load) + return count; + + mutex_lock(&sched_lock); + if (val) { + migration_register_count++; + if (migration_register_count == 1) + atomic_notifier_chain_register( + &load_alert_notifier_head, + &load_notifier_block); + } else { + migration_register_count--; + if (!migration_register_count) + atomic_notifier_chain_unregister( + &load_alert_notifier_head, + &load_notifier_block); + } + mutex_unlock(&sched_lock); + + return count; +} + +/* + * Create show/store routines + * - sys: One governor instance for complete SYSTEM + * - pol: One governor instance per struct cpufreq_policy + */ +#define show_gov_pol_sys(file_name) \ +static ssize_t show_##file_name##_gov_sys \ +(struct kobject *kobj, struct attribute *attr, char *buf) \ +{ \ + return show_##file_name(common_tunables, buf); \ +} \ + \ +static ssize_t show_##file_name##_gov_pol \ +(struct cpufreq_policy *policy, char *buf) \ +{ \ + return show_##file_name(policy->governor_data, buf); \ +} + +#define store_gov_pol_sys(file_name) \ +static ssize_t store_##file_name##_gov_sys \ +(struct kobject *kobj, struct attribute *attr, const char *buf, \ + size_t count) \ +{ \ + return store_##file_name(common_tunables, buf, count); \ +} \ + \ +static ssize_t store_##file_name##_gov_pol \ +(struct cpufreq_policy *policy, const char *buf, size_t count) \ +{ \ + return store_##file_name(policy->governor_data, buf, count); \ +} + +#define show_store_gov_pol_sys(file_name) \ +show_gov_pol_sys(file_name); \ +store_gov_pol_sys(file_name) + +show_store_gov_pol_sys(target_loads); +show_store_gov_pol_sys(above_hispeed_delay); +show_store_gov_pol_sys(hispeed_freq); +show_store_gov_pol_sys(go_hispeed_load); +show_store_gov_pol_sys(min_sample_time); +show_store_gov_pol_sys(timer_rate); +show_store_gov_pol_sys(timer_slack); +show_store_gov_pol_sys(boost); +store_gov_pol_sys(boostpulse); +show_store_gov_pol_sys(boostpulse_duration); +show_store_gov_pol_sys(io_is_busy); +show_store_gov_pol_sys(use_sched_load); +show_store_gov_pol_sys(use_migration_notif); +show_store_gov_pol_sys(max_freq_hysteresis); +show_store_gov_pol_sys(align_windows); +show_store_gov_pol_sys(ignore_hispeed_on_notif); +show_store_gov_pol_sys(fast_ramp_down); +show_store_gov_pol_sys(enable_prediction); + +#define gov_sys_attr_rw(_name) \ +static struct global_attr _name##_gov_sys = \ +__ATTR(_name, 0644, show_##_name##_gov_sys, store_##_name##_gov_sys) + +#define gov_pol_attr_rw(_name) \ +static struct freq_attr _name##_gov_pol = \ +__ATTR(_name, 0644, show_##_name##_gov_pol, store_##_name##_gov_pol) + +#define gov_sys_pol_attr_rw(_name) \ + gov_sys_attr_rw(_name); \ + gov_pol_attr_rw(_name) + +gov_sys_pol_attr_rw(target_loads); +gov_sys_pol_attr_rw(above_hispeed_delay); +gov_sys_pol_attr_rw(hispeed_freq); +gov_sys_pol_attr_rw(go_hispeed_load); +gov_sys_pol_attr_rw(min_sample_time); +gov_sys_pol_attr_rw(timer_rate); +gov_sys_pol_attr_rw(timer_slack); +gov_sys_pol_attr_rw(boost); +gov_sys_pol_attr_rw(boostpulse_duration); +gov_sys_pol_attr_rw(io_is_busy); +gov_sys_pol_attr_rw(use_sched_load); +gov_sys_pol_attr_rw(use_migration_notif); +gov_sys_pol_attr_rw(max_freq_hysteresis); +gov_sys_pol_attr_rw(align_windows); +gov_sys_pol_attr_rw(ignore_hispeed_on_notif); +gov_sys_pol_attr_rw(fast_ramp_down); +gov_sys_pol_attr_rw(enable_prediction); + +static struct global_attr boostpulse_gov_sys = + __ATTR(boostpulse, 0200, NULL, store_boostpulse_gov_sys); + +static struct freq_attr boostpulse_gov_pol = + __ATTR(boostpulse, 0200, NULL, store_boostpulse_gov_pol); + +/* One Governor instance for entire system */ +static struct attribute *interactive_attributes_gov_sys[] = { + &target_loads_gov_sys.attr, + &above_hispeed_delay_gov_sys.attr, + &hispeed_freq_gov_sys.attr, + &go_hispeed_load_gov_sys.attr, + &min_sample_time_gov_sys.attr, + &timer_rate_gov_sys.attr, + &timer_slack_gov_sys.attr, + &boost_gov_sys.attr, + &boostpulse_gov_sys.attr, + &boostpulse_duration_gov_sys.attr, + &io_is_busy_gov_sys.attr, + &use_sched_load_gov_sys.attr, + &use_migration_notif_gov_sys.attr, + &max_freq_hysteresis_gov_sys.attr, + &align_windows_gov_sys.attr, + &ignore_hispeed_on_notif_gov_sys.attr, + &fast_ramp_down_gov_sys.attr, + &enable_prediction_gov_sys.attr, + NULL, +}; + +static struct attribute_group interactive_attr_group_gov_sys = { + .attrs = interactive_attributes_gov_sys, + .name = "interactive", +}; + +/* Per policy governor instance */ +static struct attribute *interactive_attributes_gov_pol[] = { + &target_loads_gov_pol.attr, + &above_hispeed_delay_gov_pol.attr, + &hispeed_freq_gov_pol.attr, + &go_hispeed_load_gov_pol.attr, + &min_sample_time_gov_pol.attr, + &timer_rate_gov_pol.attr, + &timer_slack_gov_pol.attr, + &boost_gov_pol.attr, + &boostpulse_gov_pol.attr, + &boostpulse_duration_gov_pol.attr, + &io_is_busy_gov_pol.attr, + &use_sched_load_gov_pol.attr, + &use_migration_notif_gov_pol.attr, + &max_freq_hysteresis_gov_pol.attr, + &align_windows_gov_pol.attr, + &ignore_hispeed_on_notif_gov_pol.attr, + &fast_ramp_down_gov_pol.attr, + &enable_prediction_gov_pol.attr, + NULL, +}; + +static struct attribute_group interactive_attr_group_gov_pol = { + .attrs = interactive_attributes_gov_pol, + .name = "interactive", +}; + +static struct attribute_group *get_sysfs_attr(void) +{ + if (have_governor_per_policy()) + return &interactive_attr_group_gov_pol; + else + return &interactive_attr_group_gov_sys; +} + +static void cpufreq_interactive_nop_timer(unsigned long data) +{ +} + +static struct cpufreq_interactive_tunables *alloc_tunable( + struct cpufreq_policy *policy) +{ + struct cpufreq_interactive_tunables *tunables; + + tunables = kzalloc(sizeof(*tunables), GFP_KERNEL); + if (!tunables) + return ERR_PTR(-ENOMEM); + + tunables->above_hispeed_delay = default_above_hispeed_delay; + tunables->nabove_hispeed_delay = + ARRAY_SIZE(default_above_hispeed_delay); + tunables->go_hispeed_load = DEFAULT_GO_HISPEED_LOAD; + tunables->target_loads = default_target_loads; + tunables->ntarget_loads = ARRAY_SIZE(default_target_loads); + tunables->min_sample_time = DEFAULT_MIN_SAMPLE_TIME; + tunables->timer_rate = DEFAULT_TIMER_RATE; + tunables->boostpulse_duration_val = DEFAULT_MIN_SAMPLE_TIME; + tunables->timer_slack_val = DEFAULT_TIMER_SLACK; + + spin_lock_init(&tunables->target_loads_lock); + spin_lock_init(&tunables->above_hispeed_delay_lock); + + return tunables; +} + +static struct cpufreq_interactive_policyinfo *get_policyinfo( + struct cpufreq_policy *policy) +{ + struct cpufreq_interactive_policyinfo *ppol = + per_cpu(polinfo, policy->cpu); + int i; + struct sched_load *sl; + + /* polinfo already allocated for policy, return */ + if (ppol) + return ppol; + + ppol = kzalloc(sizeof(*ppol), GFP_KERNEL); + if (!ppol) + return ERR_PTR(-ENOMEM); + + sl = kcalloc(cpumask_weight(policy->related_cpus), sizeof(*sl), + GFP_KERNEL); + if (!sl) { + kfree(ppol); + return ERR_PTR(-ENOMEM); + } + ppol->sl = sl; + + init_timer_deferrable(&ppol->policy_timer); + ppol->policy_timer.function = cpufreq_interactive_timer; + init_timer(&ppol->policy_slack_timer); + ppol->policy_slack_timer.function = cpufreq_interactive_nop_timer; + hrtimer_init(&ppol->notif_timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL); + ppol->notif_timer.function = cpufreq_interactive_hrtimer; + spin_lock_init(&ppol->load_lock); + spin_lock_init(&ppol->target_freq_lock); + init_rwsem(&ppol->enable_sem); + + for_each_cpu(i, policy->related_cpus) + per_cpu(polinfo, i) = ppol; + return ppol; +} + +/* This function is not multithread-safe. */ +static void free_policyinfo(int cpu) +{ + struct cpufreq_interactive_policyinfo *ppol = per_cpu(polinfo, cpu); + int j; + + if (!ppol) + return; + + for_each_possible_cpu(j) + if (per_cpu(polinfo, j) == ppol) + per_cpu(polinfo, cpu) = NULL; + kfree(ppol->cached_tunables); + kfree(ppol->sl); + kfree(ppol); +} + +static struct cpufreq_interactive_tunables *get_tunables( + struct cpufreq_interactive_policyinfo *ppol) +{ + if (have_governor_per_policy()) + return ppol->cached_tunables; + else + return cached_common_tunables; +} + +static int cpufreq_governor_interactive(struct cpufreq_policy *policy, + unsigned int event) +{ + int rc; + struct cpufreq_interactive_policyinfo *ppol; + struct cpufreq_frequency_table *freq_table; + struct cpufreq_interactive_tunables *tunables; + + if (have_governor_per_policy()) + tunables = policy->governor_data; + else + tunables = common_tunables; + + BUG_ON(!tunables && (event != CPUFREQ_GOV_POLICY_INIT)); + + switch (event) { + case CPUFREQ_GOV_POLICY_INIT: + ppol = get_policyinfo(policy); + if (IS_ERR(ppol)) + return PTR_ERR(ppol); + + if (have_governor_per_policy()) { + WARN_ON(tunables); + } else if (tunables) { + tunables->usage_count++; + cpumask_or(&controlled_cpus, &controlled_cpus, + policy->related_cpus); + sched_update_freq_max_load(policy->related_cpus); + policy->governor_data = tunables; + return 0; + } + + tunables = get_tunables(ppol); + if (!tunables) { + tunables = alloc_tunable(policy); + if (IS_ERR(tunables)) + return PTR_ERR(tunables); + } + + tunables->usage_count = 1; + policy->governor_data = tunables; + if (!have_governor_per_policy()) + common_tunables = tunables; + + rc = sysfs_create_group(get_governor_parent_kobj(policy), + get_sysfs_attr()); + if (rc) { + kfree(tunables); + policy->governor_data = NULL; + if (!have_governor_per_policy()) + common_tunables = NULL; + return rc; + } + + if (!policy->governor->initialized) + cpufreq_register_notifier(&cpufreq_notifier_block, + CPUFREQ_TRANSITION_NOTIFIER); + + if (tunables->use_sched_load) + cpufreq_interactive_enable_sched_input(tunables); + + cpumask_or(&controlled_cpus, &controlled_cpus, + policy->related_cpus); + sched_update_freq_max_load(policy->related_cpus); + + if (have_governor_per_policy()) + ppol->cached_tunables = tunables; + else + cached_common_tunables = tunables; + + break; + + case CPUFREQ_GOV_POLICY_EXIT: + cpumask_andnot(&controlled_cpus, &controlled_cpus, + policy->related_cpus); + sched_update_freq_max_load(cpu_possible_mask); + if (!--tunables->usage_count) { + if (policy->governor->initialized == 1) + cpufreq_unregister_notifier(&cpufreq_notifier_block, + CPUFREQ_TRANSITION_NOTIFIER); + + sysfs_remove_group(get_governor_parent_kobj(policy), + get_sysfs_attr()); + + common_tunables = NULL; + } + + policy->governor_data = NULL; + + if (tunables->use_sched_load) + cpufreq_interactive_disable_sched_input(tunables); + + break; + + case CPUFREQ_GOV_START: + mutex_lock(&gov_lock); + + freq_table = cpufreq_frequency_get_table(policy->cpu); + if (!tunables->hispeed_freq) + tunables->hispeed_freq = policy->max; + + ppol = per_cpu(polinfo, policy->cpu); + ppol->policy = policy; + ppol->target_freq = policy->cur; + ppol->freq_table = freq_table; + ppol->p_nolim = *policy; + ppol->p_nolim.min = policy->cpuinfo.min_freq; + ppol->p_nolim.max = policy->cpuinfo.max_freq; + ppol->floor_freq = ppol->target_freq; + ppol->floor_validate_time = ktime_to_us(ktime_get()); + ppol->hispeed_validate_time = ppol->floor_validate_time; + ppol->min_freq = policy->min; + ppol->reject_notification = true; + ppol->notif_pending = false; + down_write(&ppol->enable_sem); + del_timer_sync(&ppol->policy_timer); + del_timer_sync(&ppol->policy_slack_timer); + ppol->policy_timer.data = policy->cpu; + ppol->last_evaluated_jiffy = get_jiffies_64(); + cpufreq_interactive_timer_start(tunables, policy->cpu); + ppol->governor_enabled = 1; + up_write(&ppol->enable_sem); + ppol->reject_notification = false; + + mutex_unlock(&gov_lock); + break; + + case CPUFREQ_GOV_STOP: + mutex_lock(&gov_lock); + + ppol = per_cpu(polinfo, policy->cpu); + ppol->reject_notification = true; + down_write(&ppol->enable_sem); + ppol->governor_enabled = 0; + ppol->target_freq = 0; + del_timer_sync(&ppol->policy_timer); + del_timer_sync(&ppol->policy_slack_timer); + up_write(&ppol->enable_sem); + ppol->reject_notification = false; + + mutex_unlock(&gov_lock); + break; + + case CPUFREQ_GOV_LIMITS: + ppol = per_cpu(polinfo, policy->cpu); + + __cpufreq_driver_target(policy, + ppol->target_freq, CPUFREQ_RELATION_L); + + down_read(&ppol->enable_sem); + if (ppol->governor_enabled) { + if (policy->min < ppol->min_freq) + cpufreq_interactive_timer_resched(policy->cpu, + true); + ppol->min_freq = policy->min; + } + up_read(&ppol->enable_sem); + + break; + } + return 0; +} + +#ifndef CONFIG_CPU_FREQ_DEFAULT_GOV_INTERACTIVE +static +#endif +struct cpufreq_governor cpufreq_gov_interactive = { + .name = "interactive", + .governor = cpufreq_governor_interactive, + .max_transition_latency = 10000000, + .owner = THIS_MODULE, +}; + +static int __init cpufreq_interactive_init(void) +{ + struct sched_param param = { .sched_priority = MAX_RT_PRIO-1 }; + int ret = 0; + + spin_lock_init(&speedchange_cpumask_lock); + mutex_init(&gov_lock); + mutex_init(&sched_lock); + speedchange_task = + kthread_create(cpufreq_interactive_speedchange_task, NULL, + "cfinteractive"); + if (IS_ERR(speedchange_task)) + return PTR_ERR(speedchange_task); + + sched_setscheduler_nocheck(speedchange_task, SCHED_FIFO, ¶m); + get_task_struct(speedchange_task); + + /* NB: wake up so the thread does not look hung to the freezer */ + wake_up_process_no_notif(speedchange_task); + + ret = cpufreq_register_governor(&cpufreq_gov_interactive); + if (ret) { + kthread_stop(speedchange_task); + put_task_struct(speedchange_task); + } + return ret; +} + +#ifdef CONFIG_CPU_FREQ_DEFAULT_GOV_INTERACTIVE +fs_initcall(cpufreq_interactive_init); +#else +module_init(cpufreq_interactive_init); +#endif + +static void __exit cpufreq_interactive_exit(void) +{ + int cpu; + + cpufreq_unregister_governor(&cpufreq_gov_interactive); + kthread_stop(speedchange_task); + put_task_struct(speedchange_task); + + for_each_possible_cpu(cpu) + free_policyinfo(cpu); +} + +module_exit(cpufreq_interactive_exit); + +MODULE_AUTHOR("Mike Chan "); +MODULE_DESCRIPTION("'cpufreq_interactive' - A cpufreq governor for " + "Latency sensitive workloads"); +MODULE_LICENSE("GPL"); --- /dev/null 2019-10-24 16:47:25.704025805 +0200 +++ linux-4.4.115-fbx/drivers/cpufreq/qcom-cpufreq.c 2019-01-22 16:16:23.087242639 +0100 @@ -0,0 +1,496 @@ +/* drivers/cpufreq/qcom-cpufreq.c + * + * MSM architecture cpufreq driver + * + * Copyright (C) 2007 Google, Inc. + * Copyright (c) 2007-2017, The Linux Foundation. All rights reserved. + * Author: Mike A. Chan + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static DEFINE_MUTEX(l2bw_lock); + +static struct clk *cpu_clk[NR_CPUS]; +static struct clk *l2_clk; +static DEFINE_PER_CPU(struct cpufreq_frequency_table *, freq_table); +static bool hotplug_ready; + +struct cpufreq_suspend_t { + struct mutex suspend_mutex; + int device_suspended; +}; + +static DEFINE_PER_CPU(struct cpufreq_suspend_t, suspend_data); + +static int set_cpu_freq(struct cpufreq_policy *policy, unsigned int new_freq, + unsigned int index) +{ + int ret = 0; + struct cpufreq_freqs freqs; + unsigned long rate; + + freqs.old = policy->cur; + freqs.new = new_freq; + freqs.cpu = policy->cpu; + + trace_cpu_frequency_switch_start(freqs.old, freqs.new, policy->cpu); + cpufreq_freq_transition_begin(policy, &freqs); + + rate = new_freq * 1000; + rate = clk_round_rate(cpu_clk[policy->cpu], rate); + ret = clk_set_rate(cpu_clk[policy->cpu], rate); + cpufreq_freq_transition_end(policy, &freqs, ret); + if (!ret) + trace_cpu_frequency_switch_end(policy->cpu); + + return ret; +} + +static int msm_cpufreq_target(struct cpufreq_policy *policy, + unsigned int target_freq, + unsigned int relation) +{ + int ret = 0; + int index; + struct cpufreq_frequency_table *table; + + mutex_lock(&per_cpu(suspend_data, policy->cpu).suspend_mutex); + + if (target_freq == policy->cur) + goto done; + + if (per_cpu(suspend_data, policy->cpu).device_suspended) { + pr_debug("cpufreq: cpu%d scheduling frequency change " + "in suspend.\n", policy->cpu); + ret = -EFAULT; + goto done; + } + + table = cpufreq_frequency_get_table(policy->cpu); + if (!table) { + pr_err("cpufreq: Failed to get frequency table for CPU%u\n", + policy->cpu); + ret = -ENODEV; + goto done; + } + if (cpufreq_frequency_table_target(policy, table, target_freq, relation, + &index)) { + pr_err("cpufreq: invalid target_freq: %d\n", target_freq); + ret = -EINVAL; + goto done; + } + + pr_debug("CPU[%d] target %d relation %d (%d-%d) selected %d\n", + policy->cpu, target_freq, relation, + policy->min, policy->max, table[index].frequency); + + ret = set_cpu_freq(policy, table[index].frequency, + table[index].driver_data); +done: + mutex_unlock(&per_cpu(suspend_data, policy->cpu).suspend_mutex); + return ret; +} + +static int msm_cpufreq_verify(struct cpufreq_policy *policy) +{ + cpufreq_verify_within_limits(policy, policy->cpuinfo.min_freq, + policy->cpuinfo.max_freq); + return 0; +} + +static unsigned int msm_cpufreq_get_freq(unsigned int cpu) +{ + return clk_get_rate(cpu_clk[cpu]) / 1000; +} + +static int msm_cpufreq_init(struct cpufreq_policy *policy) +{ + int cur_freq; + int index; + int ret = 0; + struct cpufreq_frequency_table *table = + per_cpu(freq_table, policy->cpu); + int cpu; + + /* + * In some SoC, some cores are clocked by same source, and their + * frequencies can not be changed independently. Find all other + * CPUs that share same clock, and mark them as controlled by + * same policy. + */ + for_each_possible_cpu(cpu) + if (cpu_clk[cpu] == cpu_clk[policy->cpu]) + cpumask_set_cpu(cpu, policy->cpus); + + ret = cpufreq_table_validate_and_show(policy, table); + if (ret) { + pr_err("cpufreq: failed to get policy min/max\n"); + return ret; + } + + cur_freq = clk_get_rate(cpu_clk[policy->cpu])/1000; + + if (cpufreq_frequency_table_target(policy, table, cur_freq, + CPUFREQ_RELATION_H, &index) && + cpufreq_frequency_table_target(policy, table, cur_freq, + CPUFREQ_RELATION_L, &index)) { + pr_info("cpufreq: cpu%d at invalid freq: %d\n", + policy->cpu, cur_freq); + return -EINVAL; + } + /* + * Call set_cpu_freq unconditionally so that when cpu is set to + * online, frequency limit will always be updated. + */ + ret = set_cpu_freq(policy, table[index].frequency, + table[index].driver_data); + if (ret) + return ret; + pr_debug("cpufreq: cpu%d init at %d switching to %d\n", + policy->cpu, cur_freq, table[index].frequency); + policy->cur = table[index].frequency; + + return 0; +} + +static int msm_cpufreq_cpu_callback(struct notifier_block *nfb, + unsigned long action, void *hcpu) +{ + unsigned int cpu = (unsigned long)hcpu; + int rc; + + /* Fail hotplug until this driver can get CPU clocks */ + if (!hotplug_ready) + return NOTIFY_BAD; + + switch (action & ~CPU_TASKS_FROZEN) { + + case CPU_DYING: + clk_disable(cpu_clk[cpu]); + clk_disable(l2_clk); + break; + /* + * Scale down clock/power of CPU that is dead and scale it back up + * before the CPU is brought up. + */ + case CPU_DEAD: + clk_unprepare(cpu_clk[cpu]); + clk_unprepare(l2_clk); + break; + case CPU_UP_CANCELED: + clk_unprepare(cpu_clk[cpu]); + clk_unprepare(l2_clk); + break; + case CPU_UP_PREPARE: + rc = clk_prepare(l2_clk); + if (rc < 0) + return NOTIFY_BAD; + rc = clk_prepare(cpu_clk[cpu]); + if (rc < 0) { + clk_unprepare(l2_clk); + return NOTIFY_BAD; + } + break; + + case CPU_STARTING: + rc = clk_enable(l2_clk); + if (rc < 0) + return NOTIFY_BAD; + rc = clk_enable(cpu_clk[cpu]); + if (rc) { + clk_disable(l2_clk); + return NOTIFY_BAD; + } + break; + + default: + break; + } + + return NOTIFY_OK; +} + +static struct notifier_block __refdata msm_cpufreq_cpu_notifier = { + .notifier_call = msm_cpufreq_cpu_callback, +}; + +static int msm_cpufreq_suspend(void) +{ + int cpu; + + for_each_possible_cpu(cpu) { + mutex_lock(&per_cpu(suspend_data, cpu).suspend_mutex); + per_cpu(suspend_data, cpu).device_suspended = 1; + mutex_unlock(&per_cpu(suspend_data, cpu).suspend_mutex); + } + + return NOTIFY_DONE; +} + +static int msm_cpufreq_resume(void) +{ + int cpu, ret; + struct cpufreq_policy policy; + + for_each_possible_cpu(cpu) { + per_cpu(suspend_data, cpu).device_suspended = 0; + } + + /* + * Freq request might be rejected during suspend, resulting + * in policy->cur violating min/max constraint. + * Correct the frequency as soon as possible. + */ + get_online_cpus(); + for_each_online_cpu(cpu) { + ret = cpufreq_get_policy(&policy, cpu); + if (ret) + continue; + if (policy.cur <= policy.max && policy.cur >= policy.min) + continue; + ret = cpufreq_update_policy(cpu); + if (ret) + pr_info("cpufreq: Current frequency violates policy min/max for CPU%d\n", + cpu); + else + pr_info("cpufreq: Frequency violation fixed for CPU%d\n", + cpu); + } + put_online_cpus(); + + return NOTIFY_DONE; +} + +static int msm_cpufreq_pm_event(struct notifier_block *this, + unsigned long event, void *ptr) +{ + switch (event) { + case PM_POST_HIBERNATION: + case PM_POST_SUSPEND: + return msm_cpufreq_resume(); + case PM_HIBERNATION_PREPARE: + case PM_SUSPEND_PREPARE: + return msm_cpufreq_suspend(); + default: + return NOTIFY_DONE; + } +} + +static struct notifier_block msm_cpufreq_pm_notifier = { + .notifier_call = msm_cpufreq_pm_event, +}; + +static struct freq_attr *msm_freq_attr[] = { + &cpufreq_freq_attr_scaling_available_freqs, + NULL, +}; + +static struct cpufreq_driver msm_cpufreq_driver = { + /* lps calculations are handled here. */ + .flags = CPUFREQ_STICKY | CPUFREQ_CONST_LOOPS, + .init = msm_cpufreq_init, + .verify = msm_cpufreq_verify, + .target = msm_cpufreq_target, + .get = msm_cpufreq_get_freq, + .name = "msm", + .attr = msm_freq_attr, +}; + +static struct cpufreq_frequency_table *cpufreq_parse_dt(struct device *dev, + char *tbl_name, int cpu) +{ + int ret, nf, i, j; + u32 *data; + struct cpufreq_frequency_table *ftbl; + + /* Parse list of usable CPU frequencies. */ + if (!of_find_property(dev->of_node, tbl_name, &nf)) + return ERR_PTR(-EINVAL); + nf /= sizeof(*data); + + if (nf == 0) + return ERR_PTR(-EINVAL); + + data = devm_kzalloc(dev, nf * sizeof(*data), GFP_KERNEL); + if (!data) + return ERR_PTR(-ENOMEM); + + ret = of_property_read_u32_array(dev->of_node, tbl_name, data, nf); + if (ret) + return ERR_PTR(ret); + + ftbl = devm_kzalloc(dev, (nf + 1) * sizeof(*ftbl), GFP_KERNEL); + if (!ftbl) + return ERR_PTR(-ENOMEM); + + j = 0; + for (i = 0; i < nf; i++) { + unsigned long f; + + f = clk_round_rate(cpu_clk[cpu], data[i] * 1000); + if (IS_ERR_VALUE(f)) + break; + f /= 1000; + + /* + * Don't repeat frequencies if they round up to the same clock + * frequency. + * + */ + if (j > 0 && f <= ftbl[j - 1].frequency) + continue; + + ftbl[j].driver_data = j; + ftbl[j].frequency = f; + j++; + } + + ftbl[j].driver_data = j; + ftbl[j].frequency = CPUFREQ_TABLE_END; + + devm_kfree(dev, data); + + return ftbl; +} + +static int __init msm_cpufreq_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + char clk_name[] = "cpu??_clk"; + char tbl_name[] = "qcom,cpufreq-table-??"; + struct clk *c; + int cpu; + struct cpufreq_frequency_table *ftbl; + + l2_clk = devm_clk_get(dev, "l2_clk"); + if (IS_ERR(l2_clk)) + l2_clk = NULL; + + for_each_possible_cpu(cpu) { + snprintf(clk_name, sizeof(clk_name), "cpu%d_clk", cpu); + c = devm_clk_get(dev, clk_name); + if (cpu == 0 && IS_ERR(c)) + return PTR_ERR(c); + else if (IS_ERR(c)) + c = cpu_clk[cpu-1]; + cpu_clk[cpu] = c; + } + hotplug_ready = true; + + /* Use per-policy governor tunable for some targets */ + if (of_property_read_bool(dev->of_node, "qcom,governor-per-policy")) + msm_cpufreq_driver.flags |= CPUFREQ_HAVE_GOVERNOR_PER_POLICY; + + /* Parse commong cpufreq table for all CPUs */ + ftbl = cpufreq_parse_dt(dev, "qcom,cpufreq-table", 0); + if (!IS_ERR(ftbl)) { + for_each_possible_cpu(cpu) + per_cpu(freq_table, cpu) = ftbl; + return 0; + } + + /* + * No common table. Parse individual tables for each unique + * CPU clock. + */ + for_each_possible_cpu(cpu) { + snprintf(tbl_name, sizeof(tbl_name), + "qcom,cpufreq-table-%d", cpu); + ftbl = cpufreq_parse_dt(dev, tbl_name, cpu); + + /* CPU0 must contain freq table */ + if (cpu == 0 && IS_ERR(ftbl)) { + dev_err(dev, "Failed to parse CPU0's freq table\n"); + return PTR_ERR(ftbl); + } + if (cpu == 0) { + per_cpu(freq_table, cpu) = ftbl; + continue; + } + + if (cpu_clk[cpu] != cpu_clk[cpu - 1] && IS_ERR(ftbl)) { + dev_err(dev, "Failed to parse CPU%d's freq table\n", + cpu); + return PTR_ERR(ftbl); + } + + /* Use previous CPU's table if it shares same clock */ + if (cpu_clk[cpu] == cpu_clk[cpu - 1]) { + if (!IS_ERR(ftbl)) { + dev_warn(dev, "Conflicting tables for CPU%d\n", + cpu); + devm_kfree(dev, ftbl); + } + ftbl = per_cpu(freq_table, cpu - 1); + } + per_cpu(freq_table, cpu) = ftbl; + } + + return 0; +} + +static struct of_device_id match_table[] = { + { .compatible = "qcom,msm-cpufreq" }, + {} +}; + +static struct platform_driver msm_cpufreq_plat_driver = { + .driver = { + .name = "msm-cpufreq", + .of_match_table = match_table, + .owner = THIS_MODULE, + }, +}; + +static int __init msm_cpufreq_register(void) +{ + int cpu, rc; + + for_each_possible_cpu(cpu) { + mutex_init(&(per_cpu(suspend_data, cpu).suspend_mutex)); + per_cpu(suspend_data, cpu).device_suspended = 0; + } + + rc = platform_driver_probe(&msm_cpufreq_plat_driver, + msm_cpufreq_probe); + if (rc < 0) { + /* Unblock hotplug if msm-cpufreq probe fails */ + unregister_hotcpu_notifier(&msm_cpufreq_cpu_notifier); + for_each_possible_cpu(cpu) + mutex_destroy(&(per_cpu(suspend_data, cpu). + suspend_mutex)); + return rc; + } + + register_pm_notifier(&msm_cpufreq_pm_notifier); + return cpufreq_register_driver(&msm_cpufreq_driver); +} + +subsys_initcall(msm_cpufreq_register); + +static int __init msm_cpufreq_early_register(void) +{ + return register_hotcpu_notifier(&msm_cpufreq_cpu_notifier); +} +core_initcall(msm_cpufreq_early_register); --- /dev/null 2019-10-24 16:47:25.704025805 +0200 +++ linux-4.4.115-fbx/drivers/cpuidle/lpm-levels.c 2019-01-22 16:16:23.095242712 +0100 @@ -0,0 +1,2041 @@ +/* Copyright (c) 2012-2017, The Linux Foundation. All rights reserved. + * Copyright (C) 2006-2007 Adam Belay + * Copyright (C) 2009 Intel Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "lpm-levels.h" +#include "lpm-workarounds.h" +#include +#define CREATE_TRACE_POINTS +#include +#include "../../drivers/clk/msm/clock.h" + +#define SCLK_HZ (32768) +#define SCM_HANDOFF_LOCK_ID "S:7" +#define PSCI_POWER_STATE(reset) (reset << 30) +#define PSCI_AFFINITY_LEVEL(lvl) ((lvl & 0x3) << 24) +static remote_spinlock_t scm_handoff_lock; + +enum { + MSM_LPM_LVL_DBG_SUSPEND_LIMITS = BIT(0), + MSM_LPM_LVL_DBG_IDLE_LIMITS = BIT(1), +}; + +enum debug_event { + CPU_ENTER, + CPU_EXIT, + CLUSTER_ENTER, + CLUSTER_EXIT, + PRE_PC_CB, + CPU_HP_STARTING, + CPU_HP_DYING, +}; + +struct lpm_debug { + cycle_t time; + enum debug_event evt; + int cpu; + uint32_t arg1; + uint32_t arg2; + uint32_t arg3; + uint32_t arg4; +}; + +struct lpm_cluster *lpm_root_node; + +#define MAXSAMPLES 5 + +static bool lpm_prediction = true; +module_param_named(lpm_prediction, + lpm_prediction, bool, S_IRUGO | S_IWUSR | S_IWGRP); + +static uint32_t ref_stddev = 100; +module_param_named( + ref_stddev, ref_stddev, uint, S_IRUGO | S_IWUSR | S_IWGRP +); + +static uint32_t tmr_add = 100; +module_param_named( + tmr_add, tmr_add, uint, S_IRUGO | S_IWUSR | S_IWGRP +); + +struct lpm_history { + uint32_t resi[MAXSAMPLES]; + int mode[MAXSAMPLES]; + int nsamp; + uint32_t hptr; + uint32_t hinvalid; + uint32_t htmr_wkup; + int64_t stime; +}; + +static DEFINE_PER_CPU(struct lpm_history, hist); + +static DEFINE_PER_CPU(struct lpm_cluster*, cpu_cluster); +static bool suspend_in_progress; +static struct hrtimer lpm_hrtimer; +static struct hrtimer histtimer; +static struct lpm_debug *lpm_debug; +static phys_addr_t lpm_debug_phys; +static const int num_dbg_elements = 0x100; +static int lpm_cpu_callback(struct notifier_block *cpu_nb, + unsigned long action, void *hcpu); + +static void cluster_unprepare(struct lpm_cluster *cluster, + const struct cpumask *cpu, int child_idx, bool from_idle, + int64_t time); +static void cluster_prepare(struct lpm_cluster *cluster, + const struct cpumask *cpu, int child_idx, bool from_idle, + int64_t time); + +static struct notifier_block __refdata lpm_cpu_nblk = { + .notifier_call = lpm_cpu_callback, +}; + +static bool menu_select; +module_param_named( + menu_select, menu_select, bool, S_IRUGO | S_IWUSR | S_IWGRP +); + +static int msm_pm_sleep_time_override; +module_param_named(sleep_time_override, + msm_pm_sleep_time_override, int, S_IRUGO | S_IWUSR | S_IWGRP); +static uint64_t suspend_wake_time; + +static bool print_parsed_dt; +module_param_named( + print_parsed_dt, print_parsed_dt, bool, S_IRUGO | S_IWUSR | S_IWGRP +); + +static bool sleep_disabled = true; +module_param_named(sleep_disabled, + sleep_disabled, bool, S_IRUGO | S_IWUSR | S_IWGRP); + +s32 msm_cpuidle_get_deep_idle_latency(void) +{ + return 10; +} + +void lpm_suspend_wake_time(uint64_t wakeup_time) +{ + if (wakeup_time <= 0) { + suspend_wake_time = msm_pm_sleep_time_override * MSEC_PER_SEC; + return; + } + + if (msm_pm_sleep_time_override && + (msm_pm_sleep_time_override < wakeup_time)) + suspend_wake_time = msm_pm_sleep_time_override * MSEC_PER_SEC; + else + suspend_wake_time = wakeup_time; +} +EXPORT_SYMBOL(lpm_suspend_wake_time); + +static uint32_t least_cluster_latency(struct lpm_cluster *cluster, + struct latency_level *lat_level) +{ + struct list_head *list; + struct lpm_cluster_level *level; + struct lpm_cluster *n; + struct power_params *pwr_params; + uint32_t latency = 0; + int i; + + if (!cluster->list.next) { + for (i = 0; i < cluster->nlevels; i++) { + level = &cluster->levels[i]; + pwr_params = &level->pwr; + if (lat_level->reset_level == level->reset_level) { + if ((latency > pwr_params->latency_us) + || (!latency)) + latency = pwr_params->latency_us; + break; + } + } + } else { + list_for_each(list, &cluster->parent->child) { + n = list_entry(list, typeof(*n), list); + if (lat_level->level_name) { + if (strcmp(lat_level->level_name, + n->cluster_name)) + continue; + } + for (i = 0; i < n->nlevels; i++) { + level = &n->levels[i]; + pwr_params = &level->pwr; + if (lat_level->reset_level == + level->reset_level) { + if ((latency > pwr_params->latency_us) + || (!latency)) + latency = + pwr_params->latency_us; + break; + } + } + } + } + return latency; +} + +static uint32_t least_cpu_latency(struct list_head *child, + struct latency_level *lat_level) +{ + struct list_head *list; + struct lpm_cpu_level *level; + struct power_params *pwr_params; + struct lpm_cpu *cpu; + struct lpm_cluster *n; + uint32_t latency = 0; + int i; + + list_for_each(list, child) { + n = list_entry(list, typeof(*n), list); + if (lat_level->level_name) { + if (strcmp(lat_level->level_name, n->cluster_name)) + continue; + } + cpu = n->cpu; + for (i = 0; i < cpu->nlevels; i++) { + level = &cpu->levels[i]; + pwr_params = &level->pwr; + if (lat_level->reset_level == level->reset_level) { + if ((latency > pwr_params->latency_us) + || (!latency)) + latency = pwr_params->latency_us; + break; + } + } + } + return latency; +} + +static struct lpm_cluster *cluster_aff_match(struct lpm_cluster *cluster, + int affinity_level) +{ + struct lpm_cluster *n; + + if ((cluster->aff_level == affinity_level) + || ((cluster->cpu) && (affinity_level == 0))) + return cluster; + else if (!cluster->cpu) { + n = list_entry(cluster->child.next, typeof(*n), list); + return cluster_aff_match(n, affinity_level); + } else + return NULL; +} + +int lpm_get_latency(struct latency_level *level, uint32_t *latency) +{ + struct lpm_cluster *cluster; + uint32_t val; + + if (!lpm_root_node) { + pr_err("%s: lpm_probe not completed\n", __func__); + return -EAGAIN; + } + + if ((level->affinity_level < 0) + || (level->affinity_level > lpm_root_node->aff_level) + || (level->reset_level < LPM_RESET_LVL_RET) + || (level->reset_level > LPM_RESET_LVL_PC) + || !latency) + return -EINVAL; + + cluster = cluster_aff_match(lpm_root_node, level->affinity_level); + if (!cluster) { + pr_err("%s:No matching cluster found for affinity_level:%d\n", + __func__, level->affinity_level); + return -EINVAL; + } + + if (level->affinity_level == 0) + val = least_cpu_latency(&cluster->parent->child, level); + else + val = least_cluster_latency(cluster, level); + + if (!val) { + pr_err("%s:No mode with affinity_level:%d reset_level:%d\n", + __func__, level->affinity_level, level->reset_level); + return -EINVAL; + } + + *latency = val; + + return 0; +} +EXPORT_SYMBOL(lpm_get_latency); + +static void update_debug_pc_event(enum debug_event event, uint32_t arg1, + uint32_t arg2, uint32_t arg3, uint32_t arg4) +{ + struct lpm_debug *dbg; + int idx; + static DEFINE_SPINLOCK(debug_lock); + static int pc_event_index; + + if (!lpm_debug) + return; + + spin_lock(&debug_lock); + idx = pc_event_index++; + dbg = &lpm_debug[idx & (num_dbg_elements - 1)]; + + dbg->evt = event; + dbg->time = arch_counter_get_cntvct(); + dbg->cpu = raw_smp_processor_id(); + dbg->arg1 = arg1; + dbg->arg2 = arg2; + dbg->arg3 = arg3; + dbg->arg4 = arg4; + spin_unlock(&debug_lock); +} + +static int lpm_cpu_callback(struct notifier_block *cpu_nb, + unsigned long action, void *hcpu) +{ + unsigned long cpu = (unsigned long) hcpu; + struct lpm_cluster *cluster = per_cpu(cpu_cluster, (unsigned int) cpu); + + switch (action & ~CPU_TASKS_FROZEN) { + case CPU_DYING: + update_debug_pc_event(CPU_HP_DYING, cpu, + cluster->num_children_in_sync.bits[0], + cluster->child_cpus.bits[0], false); + cluster_prepare(cluster, get_cpu_mask((unsigned int) cpu), + NR_LPM_LEVELS, false, 0); + break; + case CPU_STARTING: + update_debug_pc_event(CPU_HP_STARTING, cpu, + cluster->num_children_in_sync.bits[0], + cluster->child_cpus.bits[0], false); + cluster_unprepare(cluster, get_cpu_mask((unsigned int) cpu), + NR_LPM_LEVELS, false, 0); + break; + default: + break; + } + return NOTIFY_OK; +} + +#ifdef CONFIG_ARM_PSCI + +static int __init set_cpuidle_ops(void) +{ + int ret = 0, cpu; + + for_each_possible_cpu(cpu) { + ret = arm_cpuidle_init(cpu); + if (ret) + goto exit; + } + +exit: + return ret; +} + +#endif + +static enum hrtimer_restart lpm_hrtimer_cb(struct hrtimer *h) +{ + return HRTIMER_NORESTART; +} + +static void histtimer_cancel(void) +{ + hrtimer_try_to_cancel(&histtimer); +} + +static enum hrtimer_restart histtimer_fn(struct hrtimer *h) +{ + int cpu = raw_smp_processor_id(); + struct lpm_history *history = &per_cpu(hist, cpu); + + history->hinvalid = 1; + return HRTIMER_NORESTART; +} + +static void histtimer_start(uint32_t time_us) +{ + uint64_t time_ns = time_us * NSEC_PER_USEC; + ktime_t hist_ktime = ns_to_ktime(time_ns); + + histtimer.function = histtimer_fn; + hrtimer_start(&histtimer, hist_ktime, HRTIMER_MODE_REL_PINNED); +} + +static void cluster_timer_init(struct lpm_cluster *cluster) +{ + struct list_head *list; + + if (!cluster) + return; + + hrtimer_init(&cluster->histtimer, CLOCK_MONOTONIC, HRTIMER_MODE_REL); + + list_for_each(list, &cluster->child) { + struct lpm_cluster *n; + + n = list_entry(list, typeof(*n), list); + cluster_timer_init(n); + } +} + +static void clusttimer_cancel(void) +{ + int cpu = raw_smp_processor_id(); + struct lpm_cluster *cluster = per_cpu(cpu_cluster, cpu); + + hrtimer_try_to_cancel(&cluster->histtimer); + hrtimer_try_to_cancel(&cluster->parent->histtimer); +} + +static enum hrtimer_restart clusttimer_fn(struct hrtimer *h) +{ + struct lpm_cluster *cluster = container_of(h, + struct lpm_cluster, histtimer); + + cluster->history.hinvalid = 1; + return HRTIMER_NORESTART; +} + +static void clusttimer_start(struct lpm_cluster *cluster, uint32_t time_us) +{ + uint64_t time_ns = time_us * NSEC_PER_USEC; + ktime_t clust_ktime = ns_to_ktime(time_ns); + + cluster->histtimer.function = clusttimer_fn; + hrtimer_start(&cluster->histtimer, clust_ktime, + HRTIMER_MODE_REL_PINNED); +} + +static void msm_pm_set_timer(uint32_t modified_time_us) +{ + u64 modified_time_ns = modified_time_us * NSEC_PER_USEC; + ktime_t modified_ktime = ns_to_ktime(modified_time_ns); + + lpm_hrtimer.function = lpm_hrtimer_cb; + hrtimer_start(&lpm_hrtimer, modified_ktime, HRTIMER_MODE_REL_PINNED); +} + +int set_l2_mode(struct low_power_ops *ops, int mode, bool notify_rpm) +{ + int lpm = mode; + int rc = 0; + struct low_power_ops *cpu_ops = per_cpu(cpu_cluster, + smp_processor_id())->lpm_dev; + + if (cpu_ops->tz_flag & MSM_SCM_L2_OFF || + cpu_ops->tz_flag & MSM_SCM_L2_GDHS) + coresight_cti_ctx_restore(); + + switch (mode) { + case MSM_SPM_MODE_STANDALONE_POWER_COLLAPSE: + case MSM_SPM_MODE_POWER_COLLAPSE: + case MSM_SPM_MODE_FASTPC: + cpu_ops->tz_flag = MSM_SCM_L2_OFF; + coresight_cti_ctx_save(); + break; + case MSM_SPM_MODE_GDHS: + cpu_ops->tz_flag = MSM_SCM_L2_GDHS; + coresight_cti_ctx_save(); + break; + case MSM_SPM_MODE_CLOCK_GATING: + case MSM_SPM_MODE_RETENTION: + case MSM_SPM_MODE_DISABLED: + cpu_ops->tz_flag = MSM_SCM_L2_ON; + break; + default: + cpu_ops->tz_flag = MSM_SCM_L2_ON; + lpm = MSM_SPM_MODE_DISABLED; + break; + } + rc = msm_spm_config_low_power_mode(ops->spm, lpm, notify_rpm); + + if (rc) + pr_err("%s: Failed to set L2 low power mode %d, ERR %d", + __func__, lpm, rc); + + return rc; +} + +int set_l3_mode(struct low_power_ops *ops, int mode, bool notify_rpm) +{ + struct low_power_ops *cpu_ops = per_cpu(cpu_cluster, + smp_processor_id())->lpm_dev; + + switch (mode) { + case MSM_SPM_MODE_STANDALONE_POWER_COLLAPSE: + case MSM_SPM_MODE_POWER_COLLAPSE: + case MSM_SPM_MODE_FASTPC: + cpu_ops->tz_flag |= MSM_SCM_L3_PC_OFF; + break; + default: + break; + } + return msm_spm_config_low_power_mode(ops->spm, mode, notify_rpm); +} + + +int set_system_mode(struct low_power_ops *ops, int mode, bool notify_rpm) +{ + return msm_spm_config_low_power_mode(ops->spm, mode, notify_rpm); +} + +static int set_device_mode(struct lpm_cluster *cluster, int ndevice, + struct lpm_cluster_level *level) +{ + struct low_power_ops *ops; + + if (use_psci) + return 0; + + ops = &cluster->lpm_dev[ndevice]; + if (ops && ops->set_mode) + return ops->set_mode(ops, level->mode[ndevice], + level->notify_rpm); + else + return -EINVAL; +} + +static uint64_t lpm_cpuidle_predict(struct cpuidle_device *dev, + struct lpm_cpu *cpu, int *idx_restrict, + uint32_t *idx_restrict_time) +{ + int i, j, divisor; + uint64_t max, avg, stddev; + int64_t thresh = LLONG_MAX; + struct lpm_history *history = &per_cpu(hist, dev->cpu); + uint32_t *min_residency = get_per_cpu_min_residency(dev->cpu); + + if (!lpm_prediction) + return 0; + + /* + * Samples are marked invalid when woken-up due to timer, + * so donot predict. + */ + if (history->hinvalid) { + history->hinvalid = 0; + history->htmr_wkup = 1; + history->stime = 0; + return 0; + } + + /* + * Predict only when all the samples are collected. + */ + if (history->nsamp < MAXSAMPLES) { + history->stime = 0; + return 0; + } + + /* + * Check if the samples are not much deviated, if so use the + * average of those as predicted sleep time. Else if any + * specific mode has more premature exits return the index of + * that mode. + */ + +again: + max = avg = divisor = stddev = 0; + for (i = 0; i < MAXSAMPLES; i++) { + int64_t value = history->resi[i]; + + if (value <= thresh) { + avg += value; + divisor++; + if (value > max) + max = value; + } + } + do_div(avg, divisor); + + for (i = 0; i < MAXSAMPLES; i++) { + int64_t value = history->resi[i]; + + if (value <= thresh) { + int64_t diff = value - avg; + + stddev += diff * diff; + } + } + do_div(stddev, divisor); + stddev = int_sqrt(stddev); + + /* + * If the deviation is less, return the average, else + * ignore one maximum sample and retry + */ + if (((avg > stddev * 6) && (divisor >= (MAXSAMPLES - 1))) + || stddev <= ref_stddev) { + history->stime = ktime_to_us(ktime_get()) + avg; + return avg; + } else if (divisor > (MAXSAMPLES - 1)) { + thresh = max - 1; + goto again; + } + + /* + * Find the number of premature exits for each of the mode, + * excluding clockgating mode, and they are more than fifty + * percent restrict that and deeper modes. + */ + if (history->htmr_wkup != 1) { + for (j = 1; j < cpu->nlevels; j++) { + uint32_t failed = 0; + uint64_t total = 0; + + for (i = 0; i < MAXSAMPLES; i++) { + if ((history->mode[i] == j) && + (history->resi[i] < min_residency[j])) { + failed++; + total += history->resi[i]; + } + } + if (failed > (MAXSAMPLES/2)) { + *idx_restrict = j; + do_div(total, failed); + *idx_restrict_time = total; + history->stime = ktime_to_us(ktime_get()) + + *idx_restrict_time; + break; + } + } + } + return 0; +} + +static inline void invalidate_predict_history(struct cpuidle_device *dev) +{ + struct lpm_history *history = &per_cpu(hist, dev->cpu); + + if (!lpm_prediction) + return; + + if (history->hinvalid) { + history->hinvalid = 0; + history->htmr_wkup = 1; + history->stime = 0; + } +} + +static void clear_predict_history(void) +{ + struct lpm_history *history; + int i; + unsigned int cpu; + + if (!lpm_prediction) + return; + + for_each_possible_cpu(cpu) { + history = &per_cpu(hist, cpu); + for (i = 0; i < MAXSAMPLES; i++) { + history->resi[i] = 0; + history->mode[i] = -1; + history->hptr = 0; + history->nsamp = 0; + history->stime = 0; + } + } +} + +static void update_history(struct cpuidle_device *dev, int idx); + +static int cpu_power_select(struct cpuidle_device *dev, + struct lpm_cpu *cpu) +{ + int best_level = -1; + uint32_t latency_us = pm_qos_request_for_cpu(PM_QOS_CPU_DMA_LATENCY, + dev->cpu); + s64 sleep_us = ktime_to_us(tick_nohz_get_sleep_length()); + uint32_t modified_time_us = 0; + uint32_t next_event_us = 0; + int i, idx_restrict; + uint32_t lvl_latency_us = 0; + uint64_t predicted = 0; + uint32_t htime = 0, idx_restrict_time = 0; + uint32_t next_wakeup_us = (uint32_t)sleep_us; + uint32_t *min_residency = get_per_cpu_min_residency(dev->cpu); + uint32_t *max_residency = get_per_cpu_max_residency(dev->cpu); + + if (!cpu) + return -EINVAL; + + if ((sleep_disabled && !cpu_isolated(dev->cpu)) || sleep_us < 0) + return 0; + + idx_restrict = cpu->nlevels + 1; + + next_event_us = (uint32_t)(ktime_to_us(get_next_event_time(dev->cpu))); + + for (i = 0; i < cpu->nlevels; i++) { + struct lpm_cpu_level *level = &cpu->levels[i]; + struct power_params *pwr_params = &level->pwr; + enum msm_pm_sleep_mode mode = level->mode; + bool allow; + + allow = lpm_cpu_mode_allow(dev->cpu, i, true); + + if (!allow) + continue; + + lvl_latency_us = pwr_params->latency_us; + + if (latency_us < lvl_latency_us) + break; + + if (next_event_us) { + if (next_event_us < lvl_latency_us) + break; + + if (((next_event_us - lvl_latency_us) < sleep_us) || + (next_event_us < sleep_us)) + next_wakeup_us = next_event_us - lvl_latency_us; + } + + if (!i) { + /* + * If the next_wake_us itself is not sufficient for + * deeper low power modes than clock gating do not + * call prediction. + */ + if (next_wakeup_us > max_residency[i]) { + predicted = lpm_cpuidle_predict(dev, cpu, + &idx_restrict, &idx_restrict_time); + if (predicted && (predicted < min_residency[i])) + predicted = min_residency[i]; + } else + invalidate_predict_history(dev); + } + + if (i >= idx_restrict) + break; + + best_level = i; + + if (next_event_us && next_event_us < sleep_us && + (mode != MSM_PM_SLEEP_MODE_WAIT_FOR_INTERRUPT)) + modified_time_us + = next_event_us - lvl_latency_us; + else + modified_time_us = 0; + + if (predicted ? (predicted <= max_residency[i]) + : (next_wakeup_us <= max_residency[i])) + break; + } + + if (modified_time_us) + msm_pm_set_timer(modified_time_us); + + /* + * Start timer to avoid staying in shallower mode forever + * incase of misprediciton + */ + if ((predicted || (idx_restrict != (cpu->nlevels + 1))) + && ((best_level >= 0) + && (best_level < (cpu->nlevels-1)))) { + htime = predicted + tmr_add; + if (htime == tmr_add) + htime = idx_restrict_time; + else if (htime > max_residency[best_level]) + htime = max_residency[best_level]; + + if ((next_wakeup_us > htime) && + ((next_wakeup_us - htime) > max_residency[best_level])) + histtimer_start(htime); + } + + trace_cpu_power_select(best_level, sleep_us, latency_us, next_event_us); + + trace_cpu_pred_select(idx_restrict_time ? 2 : (predicted ? 1 : 0), + predicted, htime); + + return best_level; +} + +static uint64_t get_cluster_sleep_time(struct lpm_cluster *cluster, + struct cpumask *mask, bool from_idle, uint32_t *pred_time) +{ + int cpu; + int next_cpu = raw_smp_processor_id(); + ktime_t next_event; + struct cpumask online_cpus_in_cluster; + struct lpm_history *history; + int64_t prediction = LONG_MAX; + + next_event.tv64 = KTIME_MAX; + if (!suspend_wake_time) + suspend_wake_time = msm_pm_sleep_time_override; + if (!from_idle) { + if (mask) + cpumask_copy(mask, cpumask_of(raw_smp_processor_id())); + if (!suspend_wake_time) + return ~0ULL; + else + return USEC_PER_MSEC * suspend_wake_time; + } + + cpumask_and(&online_cpus_in_cluster, + &cluster->num_children_in_sync, cpu_online_mask); + + for_each_cpu(cpu, &online_cpus_in_cluster) { + ktime_t *next_event_c; + + next_event_c = get_next_event_cpu(cpu); + if (next_event_c->tv64 < next_event.tv64) { + next_event.tv64 = next_event_c->tv64; + next_cpu = cpu; + } + + if (from_idle && lpm_prediction) { + history = &per_cpu(hist, cpu); + if (history->stime && (history->stime < prediction)) + prediction = history->stime; + } + } + + if (mask) + cpumask_copy(mask, cpumask_of(next_cpu)); + + if (from_idle && lpm_prediction) { + if (prediction > ktime_to_us(ktime_get())) + *pred_time = prediction - ktime_to_us(ktime_get()); + } + + if (ktime_to_us(next_event) > ktime_to_us(ktime_get())) + return ktime_to_us(ktime_sub(next_event, ktime_get())); + else + return 0; +} + +static int cluster_predict(struct lpm_cluster *cluster, + uint32_t *pred_us) +{ + int i, j; + int ret = 0; + struct cluster_history *history = &cluster->history; + int64_t cur_time = ktime_to_us(ktime_get()); + + if (!lpm_prediction) + return 0; + + if (history->hinvalid) { + history->hinvalid = 0; + history->htmr_wkup = 1; + history->flag = 0; + return ret; + } + + if (history->nsamp == MAXSAMPLES) { + for (i = 0; i < MAXSAMPLES; i++) { + if ((cur_time - history->stime[i]) + > CLUST_SMPL_INVLD_TIME) + history->nsamp--; + } + } + + if (history->nsamp < MAXSAMPLES) { + history->flag = 0; + return ret; + } + + if (history->flag == 2) + history->flag = 0; + + if (history->htmr_wkup != 1) { + uint64_t total = 0; + + if (history->flag == 1) { + for (i = 0; i < MAXSAMPLES; i++) + total += history->resi[i]; + do_div(total, MAXSAMPLES); + *pred_us = total; + return 2; + } + + for (j = 1; j < cluster->nlevels; j++) { + uint32_t failed = 0; + + total = 0; + for (i = 0; i < MAXSAMPLES; i++) { + if ((history->mode[i] == j) && (history->resi[i] + < cluster->levels[j].pwr.min_residency)) { + failed++; + total += history->resi[i]; + } + } + + if (failed > (MAXSAMPLES-2)) { + do_div(total, failed); + *pred_us = total; + history->flag = 1; + return 1; + } + } + } + + return ret; +} + +static void update_cluster_history_time(struct cluster_history *history, + int idx, uint64_t start) +{ + history->entry_idx = idx; + history->entry_time = start; +} + +static void update_cluster_history(struct cluster_history *history, int idx) +{ + uint32_t tmr = 0; + uint32_t residency = 0; + struct lpm_cluster *cluster = + container_of(history, struct lpm_cluster, history); + + if (!lpm_prediction) + return; + + if ((history->entry_idx == -1) || (history->entry_idx == idx)) { + residency = ktime_to_us(ktime_get()) - history->entry_time; + history->stime[history->hptr] = history->entry_time; + } else + return; + + if (history->htmr_wkup) { + if (!history->hptr) + history->hptr = MAXSAMPLES-1; + else + history->hptr--; + + history->resi[history->hptr] += residency; + + history->htmr_wkup = 0; + tmr = 1; + } else { + history->resi[history->hptr] = residency; + } + + history->mode[history->hptr] = idx; + + history->entry_idx = INT_MIN; + history->entry_time = 0; + + if (history->nsamp < MAXSAMPLES) + history->nsamp++; + + trace_cluster_pred_hist(cluster->cluster_name, + history->mode[history->hptr], history->resi[history->hptr], + history->hptr, tmr); + + (history->hptr)++; + + if (history->hptr >= MAXSAMPLES) + history->hptr = 0; +} + +static void clear_cl_history_each(struct cluster_history *history) +{ + int i; + + for (i = 0; i < MAXSAMPLES; i++) { + history->resi[i] = 0; + history->mode[i] = -1; + history->stime[i] = 0; + } + history->hptr = 0; + history->nsamp = 0; + history->flag = 0; + history->hinvalid = 0; + history->htmr_wkup = 0; +} + +static void clear_cl_predict_history(void) +{ + struct lpm_cluster *cluster = lpm_root_node; + struct list_head *list; + + if (!lpm_prediction) + return; + + clear_cl_history_each(&cluster->history); + + list_for_each(list, &cluster->child) { + struct lpm_cluster *n; + + n = list_entry(list, typeof(*n), list); + clear_cl_history_each(&n->history); + } +} + +static int cluster_select(struct lpm_cluster *cluster, bool from_idle, + int *ispred) +{ + int best_level = -1; + int i; + struct cpumask mask; + uint32_t latency_us = ~0U; + uint32_t sleep_us; + uint32_t cpupred_us = 0, pred_us = 0; + int pred_mode = 0, predicted = 0; + + if (!cluster) + return -EINVAL; + + sleep_us = (uint32_t)get_cluster_sleep_time(cluster, NULL, + from_idle, &cpupred_us); + + if (from_idle) { + pred_mode = cluster_predict(cluster, &pred_us); + + if (cpupred_us && pred_mode && (cpupred_us < pred_us)) + pred_us = cpupred_us; + + if (pred_us && pred_mode && (pred_us < sleep_us)) + predicted = 1; + + if (predicted && (pred_us == cpupred_us)) + predicted = 2; + } + + if (cpumask_and(&mask, cpu_online_mask, &cluster->child_cpus)) + latency_us = pm_qos_request_for_cpumask(PM_QOS_CPU_DMA_LATENCY, + &mask); + + /* + * If atleast one of the core in the cluster is online, the cluster + * low power modes should be determined by the idle characteristics + * even if the last core enters the low power mode as a part of + * hotplug. + */ + + if (!from_idle && num_online_cpus() > 1 && + cpumask_intersects(&cluster->child_cpus, cpu_online_mask)) + from_idle = true; + + for (i = 0; i < cluster->nlevels; i++) { + struct lpm_cluster_level *level = &cluster->levels[i]; + struct power_params *pwr_params = &level->pwr; + + if (!lpm_cluster_mode_allow(cluster, i, from_idle)) + continue; + + if (level->last_core_only && + cpumask_weight(cpu_online_mask) > 1) + continue; + + if (!cpumask_equal(&cluster->num_children_in_sync, + &level->num_cpu_votes)) + continue; + + if (from_idle && latency_us < pwr_params->latency_us) + break; + + if (sleep_us < pwr_params->time_overhead_us) + break; + + if (suspend_in_progress && from_idle && level->notify_rpm) + continue; + + if (level->notify_rpm && msm_rpm_waiting_for_ack()) + continue; + + best_level = i; + + if (from_idle && + (predicted ? (pred_us <= pwr_params->max_residency) + : (sleep_us <= pwr_params->max_residency))) + break; + } + + if ((best_level == (cluster->nlevels - 1)) && (pred_mode == 2)) + cluster->history.flag = 2; + + *ispred = predicted; + + trace_cluster_pred_select(cluster->cluster_name, best_level, sleep_us, + latency_us, predicted, pred_us); + + return best_level; +} + +static void cluster_notify(struct lpm_cluster *cluster, + struct lpm_cluster_level *level, bool enter) +{ + if (level->is_reset && enter) + cpu_cluster_pm_enter(cluster->aff_level); + else if (level->is_reset && !enter) + cpu_cluster_pm_exit(cluster->aff_level); +} + +static int cluster_configure(struct lpm_cluster *cluster, int idx, + bool from_idle, int predicted) +{ + struct lpm_cluster_level *level = &cluster->levels[idx]; + struct cpumask online_cpus; + int ret, i; + + cpumask_and(&online_cpus, &cluster->num_children_in_sync, + cpu_online_mask); + + if (!cpumask_equal(&cluster->num_children_in_sync, &cluster->child_cpus) + || is_IPI_pending(&online_cpus)) { + return -EPERM; + } + + if (idx != cluster->default_level) { + update_debug_pc_event(CLUSTER_ENTER, idx, + cluster->num_children_in_sync.bits[0], + cluster->child_cpus.bits[0], from_idle); + trace_cluster_enter(cluster->cluster_name, idx, + cluster->num_children_in_sync.bits[0], + cluster->child_cpus.bits[0], from_idle); + lpm_stats_cluster_enter(cluster->stats, idx); + + if (from_idle && lpm_prediction) + update_cluster_history_time(&cluster->history, idx, + ktime_to_us(ktime_get())); + } + + for (i = 0; i < cluster->ndevices; i++) { + ret = set_device_mode(cluster, i, level); + if (ret) + goto failed_set_mode; + } + + if (level->notify_rpm) { + struct cpumask nextcpu, *cpumask; + uint64_t us; + uint32_t pred_us; + uint64_t sec; + uint64_t nsec; + + us = get_cluster_sleep_time(cluster, &nextcpu, + from_idle, &pred_us); + cpumask = level->disable_dynamic_routing ? NULL : &nextcpu; + + ret = msm_rpm_enter_sleep(0, cpumask); + if (ret) { + pr_info("Failed msm_rpm_enter_sleep() rc = %d\n", ret); + goto failed_set_mode; + } + + clear_predict_history(); + clear_cl_predict_history(); + + us = us + 1; + sec = us; + do_div(sec, USEC_PER_SEC); + nsec = us - sec * USEC_PER_SEC; + + sec = sec * SCLK_HZ; + if (nsec > 0) { + nsec = nsec * NSEC_PER_USEC; + do_div(nsec, NSEC_PER_SEC/SCLK_HZ); + } + us = sec + nsec; + msm_mpm_enter_sleep(us, from_idle, cpumask); + } + + /* Notify cluster enter event after successfully config completion */ + cluster_notify(cluster, level, true); + + sched_set_cluster_dstate(&cluster->child_cpus, idx, 0, 0); + + cluster->last_level = idx; + + if (predicted && (idx < (cluster->nlevels - 1))) { + struct power_params *pwr_params = &cluster->levels[idx].pwr; + + tick_broadcast_exit(); + clusttimer_start(cluster, pwr_params->max_residency + tmr_add); + tick_broadcast_enter(); + } + + return 0; + +failed_set_mode: + + for (i = 0; i < cluster->ndevices; i++) { + int rc = 0; + level = &cluster->levels[cluster->default_level]; + rc = set_device_mode(cluster, i, level); + BUG_ON(rc); + } + return ret; +} + +static void cluster_prepare(struct lpm_cluster *cluster, + const struct cpumask *cpu, int child_idx, bool from_idle, + int64_t start_time) +{ + int i; + int predicted = 0; + + if (!cluster) + return; + + if (cluster->min_child_level > child_idx) + return; + + spin_lock(&cluster->sync_lock); + cpumask_or(&cluster->num_children_in_sync, cpu, + &cluster->num_children_in_sync); + + for (i = 0; i < cluster->nlevels; i++) { + struct lpm_cluster_level *lvl = &cluster->levels[i]; + + if (child_idx >= lvl->min_child_level) + cpumask_or(&lvl->num_cpu_votes, cpu, + &lvl->num_cpu_votes); + } + + /* + * cluster_select() does not make any configuration changes. So its ok + * to release the lock here. If a core wakes up for a rude request, + * it need not wait for another to finish its cluster selection and + * configuration process + */ + + if (!cpumask_equal(&cluster->num_children_in_sync, + &cluster->child_cpus)) + goto failed; + + i = cluster_select(cluster, from_idle, &predicted); + + if (((i < 0) || (i == cluster->default_level)) + && predicted && from_idle) { + update_cluster_history_time(&cluster->history, + -1, ktime_to_us(ktime_get())); + + if (i < 0) { + struct power_params *pwr_params = + &cluster->levels[0].pwr; + + tick_broadcast_exit(); + clusttimer_start(cluster, + pwr_params->max_residency + tmr_add); + tick_broadcast_enter(); + } + } + + if (i < 0) + goto failed; + + if (cluster_configure(cluster, i, from_idle, predicted)) + goto failed; + + cluster->stats->sleep_time = start_time; + cluster_prepare(cluster->parent, &cluster->num_children_in_sync, i, + from_idle, start_time); + + spin_unlock(&cluster->sync_lock); + return; +failed: + spin_unlock(&cluster->sync_lock); + cluster->stats->sleep_time = 0; + return; +} + +static void cluster_unprepare(struct lpm_cluster *cluster, + const struct cpumask *cpu, int child_idx, bool from_idle, + int64_t end_time) +{ + struct lpm_cluster_level *level; + bool first_cpu; + int last_level, i, ret; + + if (!cluster) + return; + + if (cluster->min_child_level > child_idx) + return; + + spin_lock(&cluster->sync_lock); + last_level = cluster->default_level; + first_cpu = cpumask_equal(&cluster->num_children_in_sync, + &cluster->child_cpus); + cpumask_andnot(&cluster->num_children_in_sync, + &cluster->num_children_in_sync, cpu); + + for (i = 0; i < cluster->nlevels; i++) { + struct lpm_cluster_level *lvl = &cluster->levels[i]; + + if (child_idx >= lvl->min_child_level) + cpumask_andnot(&lvl->num_cpu_votes, + &lvl->num_cpu_votes, cpu); + } + + if (from_idle && first_cpu && + (cluster->last_level == cluster->default_level)) + update_cluster_history(&cluster->history, cluster->last_level); + + if (!first_cpu || cluster->last_level == cluster->default_level) + goto unlock_return; + + if (cluster->stats->sleep_time) + cluster->stats->sleep_time = end_time - + cluster->stats->sleep_time; + lpm_stats_cluster_exit(cluster->stats, cluster->last_level, true); + + level = &cluster->levels[cluster->last_level]; + if (level->notify_rpm) { + msm_rpm_exit_sleep(); + + /* If RPM bumps up CX to turbo, unvote CX turbo vote + * during exit of rpm assisted power collapse to + * reduce the power impact + */ + + lpm_wa_cx_unvote_send(); + msm_mpm_exit_sleep(from_idle); + } + + update_debug_pc_event(CLUSTER_EXIT, cluster->last_level, + cluster->num_children_in_sync.bits[0], + cluster->child_cpus.bits[0], from_idle); + trace_cluster_exit(cluster->cluster_name, cluster->last_level, + cluster->num_children_in_sync.bits[0], + cluster->child_cpus.bits[0], from_idle); + + last_level = cluster->last_level; + cluster->last_level = cluster->default_level; + + for (i = 0; i < cluster->ndevices; i++) { + level = &cluster->levels[cluster->default_level]; + ret = set_device_mode(cluster, i, level); + + BUG_ON(ret); + + } + sched_set_cluster_dstate(&cluster->child_cpus, 0, 0, 0); + + cluster_notify(cluster, &cluster->levels[last_level], false); + + if (from_idle) + update_cluster_history(&cluster->history, last_level); + + cluster_unprepare(cluster->parent, &cluster->child_cpus, + last_level, from_idle, end_time); +unlock_return: + spin_unlock(&cluster->sync_lock); +} + +static inline void cpu_prepare(struct lpm_cluster *cluster, int cpu_index, + bool from_idle) +{ + struct lpm_cpu_level *cpu_level = &cluster->cpu->levels[cpu_index]; + bool jtag_save_restore = + cluster->cpu->levels[cpu_index].jtag_save_restore; + + /* Use broadcast timer for aggregating sleep mode within a cluster. + * A broadcast timer could be used in the following scenarios + * 1) The architected timer HW gets reset during certain low power + * modes and the core relies on a external(broadcast) timer to wake up + * from sleep. This information is passed through device tree. + * 2) The CPU low power mode could trigger a system low power mode. + * The low power module relies on Broadcast timer to aggregate the + * next wakeup within a cluster, in which case, CPU switches over to + * use broadcast timer. + */ + if (from_idle && (cpu_level->use_bc_timer || + (cpu_index >= cluster->min_child_level))) + tick_broadcast_enter(); + + if (from_idle && ((cpu_level->mode == MSM_PM_SLEEP_MODE_POWER_COLLAPSE) + || (cpu_level->mode == + MSM_PM_SLEEP_MODE_POWER_COLLAPSE_STANDALONE) + || (cpu_level->is_reset))) + cpu_pm_enter(); + + /* + * Save JTAG registers for 8996v1.0 & 8996v2.x in C4 LPM + */ + if (jtag_save_restore) + msm_jtag_save_state(); +} + +static inline void cpu_unprepare(struct lpm_cluster *cluster, int cpu_index, + bool from_idle) +{ + struct lpm_cpu_level *cpu_level = &cluster->cpu->levels[cpu_index]; + bool jtag_save_restore = + cluster->cpu->levels[cpu_index].jtag_save_restore; + + if (from_idle && (cpu_level->use_bc_timer || + (cpu_index >= cluster->min_child_level))) + tick_broadcast_exit(); + + if (from_idle && ((cpu_level->mode == MSM_PM_SLEEP_MODE_POWER_COLLAPSE) + || (cpu_level->mode == + MSM_PM_SLEEP_MODE_POWER_COLLAPSE_STANDALONE) + || cpu_level->is_reset)) + cpu_pm_exit(); + + /* + * Restore JTAG registers for 8996v1.0 & 8996v2.x in C4 LPM + */ + if (jtag_save_restore) + msm_jtag_restore_state(); +} + +int get_cluster_id(struct lpm_cluster *cluster, int *aff_lvl) +{ + int state_id = 0; + + if (!cluster) + return 0; + + spin_lock(&cluster->sync_lock); + + if (!cpumask_equal(&cluster->num_children_in_sync, + &cluster->child_cpus)) + goto unlock_and_return; + + state_id |= get_cluster_id(cluster->parent, aff_lvl); + + if (cluster->last_level != cluster->default_level) { + struct lpm_cluster_level *level + = &cluster->levels[cluster->last_level]; + + state_id |= (level->psci_id & cluster->psci_mode_mask) + << cluster->psci_mode_shift; + (*aff_lvl)++; + } +unlock_and_return: + spin_unlock(&cluster->sync_lock); + return state_id; +} + +#if !defined(CONFIG_CPU_V7) +bool psci_enter_sleep(struct lpm_cluster *cluster, int idx, bool from_idle) +{ + /* + * idx = 0 is the default LPM state + */ + if (!idx) { + stop_critical_timings(); + wfi(); + start_critical_timings(); + return 1; + } else { + int affinity_level = 0; + int state_id = get_cluster_id(cluster, &affinity_level); + int power_state = + PSCI_POWER_STATE(cluster->cpu->levels[idx].is_reset); + bool success = false; + + if (cluster->cpu->levels[idx].hyp_psci) { + stop_critical_timings(); + __invoke_psci_fn_smc(0xC4000021, 0, 0, 0); + start_critical_timings(); + return 1; + } + + affinity_level = PSCI_AFFINITY_LEVEL(affinity_level); + state_id |= (power_state | affinity_level + | cluster->cpu->levels[idx].psci_id); + + update_debug_pc_event(CPU_ENTER, state_id, + 0xdeaffeed, 0xdeaffeed, true); + stop_critical_timings(); + success = !arm_cpuidle_suspend(state_id); + start_critical_timings(); + update_debug_pc_event(CPU_EXIT, state_id, + success, 0xdeaffeed, true); + return success; + } +} +#elif defined(CONFIG_ARM_PSCI) +bool psci_enter_sleep(struct lpm_cluster *cluster, int idx, bool from_idle) +{ + if (!idx) { + stop_critical_timings(); + wfi(); + start_critical_timings(); + return 1; + } else { + int affinity_level = 0; + int state_id = get_cluster_id(cluster, &affinity_level); + int power_state = + PSCI_POWER_STATE(cluster->cpu->levels[idx].is_reset); + bool success = false; + + affinity_level = PSCI_AFFINITY_LEVEL(affinity_level); + state_id |= (power_state | affinity_level + | cluster->cpu->levels[idx].psci_id); + + update_debug_pc_event(CPU_ENTER, state_id, + 0xdeaffeed, 0xdeaffeed, true); + stop_critical_timings(); + success = !arm_cpuidle_suspend(state_id); + start_critical_timings(); + update_debug_pc_event(CPU_EXIT, state_id, + success, 0xdeaffeed, true); + return success; + } +} +#else +bool psci_enter_sleep(struct lpm_cluster *cluster, int idx, bool from_idle) +{ + WARN_ONCE(true, "PSCI cpu_suspend ops not supported\n"); + return false; +} +#endif + +static int lpm_cpuidle_select(struct cpuidle_driver *drv, + struct cpuidle_device *dev) +{ + struct lpm_cluster *cluster = per_cpu(cpu_cluster, dev->cpu); + int idx; + + if (!cluster) + return 0; + + idx = cpu_power_select(dev, cluster->cpu); + + if (idx < 0) + return -EPERM; + + return idx; +} + +static void update_history(struct cpuidle_device *dev, int idx) +{ + struct lpm_history *history = &per_cpu(hist, dev->cpu); + uint32_t tmr = 0; + + if (!lpm_prediction) + return; + + if (history->htmr_wkup) { + if (!history->hptr) + history->hptr = MAXSAMPLES-1; + else + history->hptr--; + + history->resi[history->hptr] += dev->last_residency; + history->htmr_wkup = 0; + tmr = 1; + } else + history->resi[history->hptr] = dev->last_residency; + + history->mode[history->hptr] = idx; + + trace_cpu_pred_hist(history->mode[history->hptr], + history->resi[history->hptr], history->hptr, tmr); + + if (history->nsamp < MAXSAMPLES) + history->nsamp++; + + (history->hptr)++; + if (history->hptr >= MAXSAMPLES) + history->hptr = 0; +} + +static int lpm_cpuidle_enter(struct cpuidle_device *dev, + struct cpuidle_driver *drv, int idx) +{ + struct lpm_cluster *cluster = per_cpu(cpu_cluster, dev->cpu); + bool success = false; + const struct cpumask *cpumask = get_cpu_mask(dev->cpu); + int64_t start_time = ktime_to_ns(ktime_get()), end_time; + struct power_params *pwr_params; + + if (idx < 0) + return -EINVAL; + + pwr_params = &cluster->cpu->levels[idx].pwr; + sched_set_cpu_cstate(smp_processor_id(), idx + 1, + pwr_params->energy_overhead, pwr_params->latency_us); + + pwr_params = &cluster->cpu->levels[idx].pwr; + + cpu_prepare(cluster, idx, true); + cluster_prepare(cluster, cpumask, idx, true, ktime_to_ns(ktime_get())); + + trace_cpu_idle_enter(idx); + lpm_stats_cpu_enter(idx, start_time); + + if (need_resched()) + goto exit; + + BUG_ON(!use_psci); + success = psci_enter_sleep(cluster, idx, true); + +exit: + end_time = ktime_to_ns(ktime_get()); + lpm_stats_cpu_exit(idx, end_time, success); + + cluster_unprepare(cluster, cpumask, idx, true, end_time); + cpu_unprepare(cluster, idx, true); + sched_set_cpu_cstate(smp_processor_id(), 0, 0, 0); + end_time = ktime_to_ns(ktime_get()) - start_time; + do_div(end_time, 1000); + dev->last_residency = end_time; + update_history(dev, idx); + trace_cpu_idle_exit(idx, success); + local_irq_enable(); + if (lpm_prediction) { + histtimer_cancel(); + clusttimer_cancel(); + } + return idx; +} + +#ifdef CONFIG_CPU_IDLE_MULTIPLE_DRIVERS +static int cpuidle_register_cpu(struct cpuidle_driver *drv, + struct cpumask *mask) +{ + struct cpuidle_device *device; + int cpu, ret; + + + if (!mask || !drv) + return -EINVAL; + + drv->cpumask = mask; + ret = cpuidle_register_driver(drv); + if (ret) { + pr_err("Failed to register cpuidle driver %d\n", ret); + goto failed_driver_register; + } + + for_each_cpu(cpu, mask) { + device = &per_cpu(cpuidle_dev, cpu); + device->cpu = cpu; + + ret = cpuidle_register_device(device); + if (ret) { + pr_err("Failed to register cpuidle driver for cpu:%u\n", + cpu); + goto failed_driver_register; + } + } + return ret; +failed_driver_register: + for_each_cpu(cpu, mask) + cpuidle_unregister_driver(drv); + return ret; +} +#else +static int cpuidle_register_cpu(struct cpuidle_driver *drv, + struct cpumask *mask) +{ + return cpuidle_register(drv, NULL); +} +#endif + +static struct cpuidle_governor lpm_governor = { + .name = "qcom", + .rating = 30, + .select = lpm_cpuidle_select, + .owner = THIS_MODULE, +}; + +static int cluster_cpuidle_register(struct lpm_cluster *cl) +{ + int i = 0, ret = 0; + unsigned cpu; + struct lpm_cluster *p = NULL; + + if (!cl->cpu) { + struct lpm_cluster *n; + + list_for_each_entry(n, &cl->child, list) { + ret = cluster_cpuidle_register(n); + if (ret) + break; + } + return ret; + } + + cl->drv = kzalloc(sizeof(*cl->drv), GFP_KERNEL); + if (!cl->drv) + return -ENOMEM; + + cl->drv->name = "msm_idle"; + + for (i = 0; i < cl->cpu->nlevels; i++) { + struct cpuidle_state *st = &cl->drv->states[i]; + struct lpm_cpu_level *cpu_level = &cl->cpu->levels[i]; + snprintf(st->name, CPUIDLE_NAME_LEN, "C%u\n", i); + snprintf(st->desc, CPUIDLE_DESC_LEN, "%s", + cpu_level->name); + st->flags = 0; + st->exit_latency = cpu_level->pwr.latency_us; + st->power_usage = cpu_level->pwr.ss_power; + st->target_residency = 0; + st->enter = lpm_cpuidle_enter; + } + + cl->drv->state_count = cl->cpu->nlevels; + cl->drv->safe_state_index = 0; + for_each_cpu(cpu, &cl->child_cpus) + per_cpu(cpu_cluster, cpu) = cl; + + for_each_possible_cpu(cpu) { + if (cpu_online(cpu)) + continue; + p = per_cpu(cpu_cluster, cpu); + while (p) { + int j; + spin_lock(&p->sync_lock); + cpumask_set_cpu(cpu, &p->num_children_in_sync); + for (j = 0; j < p->nlevels; j++) + cpumask_copy(&p->levels[j].num_cpu_votes, + &p->num_children_in_sync); + spin_unlock(&p->sync_lock); + p = p->parent; + } + } + ret = cpuidle_register_cpu(cl->drv, &cl->child_cpus); + + if (ret) { + kfree(cl->drv); + return -ENOMEM; + } + return 0; +} + +/** + * init_lpm - initializes the governor + */ +static int __init init_lpm(void) +{ + return cpuidle_register_governor(&lpm_governor); +} + +postcore_initcall(init_lpm); + +static void register_cpu_lpm_stats(struct lpm_cpu *cpu, + struct lpm_cluster *parent) +{ + const char **level_name; + int i; + + level_name = kzalloc(cpu->nlevels * sizeof(*level_name), GFP_KERNEL); + + if (!level_name) + return; + + for (i = 0; i < cpu->nlevels; i++) + level_name[i] = cpu->levels[i].name; + + lpm_stats_config_level("cpu", level_name, cpu->nlevels, + parent->stats, &parent->child_cpus); + + kfree(level_name); +} + +static void register_cluster_lpm_stats(struct lpm_cluster *cl, + struct lpm_cluster *parent) +{ + const char **level_name; + int i; + struct lpm_cluster *child; + + if (!cl) + return; + + level_name = kzalloc(cl->nlevels * sizeof(*level_name), GFP_KERNEL); + + if (!level_name) + return; + + for (i = 0; i < cl->nlevels; i++) + level_name[i] = cl->levels[i].level_name; + + cl->stats = lpm_stats_config_level(cl->cluster_name, level_name, + cl->nlevels, parent ? parent->stats : NULL, NULL); + + kfree(level_name); + + if (cl->cpu) { + register_cpu_lpm_stats(cl->cpu, cl); + return; + } + + list_for_each_entry(child, &cl->child, list) + register_cluster_lpm_stats(child, cl); +} + +static int lpm_suspend_prepare(void) +{ + suspend_in_progress = true; + msm_mpm_suspend_prepare(); + lpm_stats_suspend_enter(); + + return 0; +} + +static void lpm_suspend_wake(void) +{ + suspend_in_progress = false; + msm_mpm_suspend_wake(); + lpm_stats_suspend_exit(); +} + +static int lpm_suspend_enter(suspend_state_t state) +{ + int cpu = raw_smp_processor_id(); + struct lpm_cluster *cluster = per_cpu(cpu_cluster, cpu); + struct lpm_cpu *lpm_cpu = cluster->cpu; + const struct cpumask *cpumask = get_cpu_mask(cpu); + int idx; + + for (idx = lpm_cpu->nlevels - 1; idx >= 0; idx--) { + + if (lpm_cpu_mode_allow(cpu, idx, false)) + break; + } + if (idx < 0) { + pr_err("Failed suspend\n"); + return 0; + } + cpu_prepare(cluster, idx, false); + cluster_prepare(cluster, cpumask, idx, false, 0); + if (idx > 0) + update_debug_pc_event(CPU_ENTER, idx, 0xdeaffeed, + 0xdeaffeed, false); + + /* + * Print the clocks which are enabled during system suspend + * This debug information is useful to know which are the + * clocks that are enabled and preventing the system level + * LPMs(XO and Vmin). + */ + clock_debug_print_enabled(); + + BUG_ON(!use_psci); + psci_enter_sleep(cluster, idx, true); + + if (idx > 0) + update_debug_pc_event(CPU_EXIT, idx, true, 0xdeaffeed, + false); + + cluster_unprepare(cluster, cpumask, idx, false, 0); + cpu_unprepare(cluster, idx, false); + return 0; +} + +static const struct platform_suspend_ops lpm_suspend_ops = { + .enter = lpm_suspend_enter, + .valid = suspend_valid_only_mem, + .prepare_late = lpm_suspend_prepare, + .wake = lpm_suspend_wake, +}; + +static int lpm_probe(struct platform_device *pdev) +{ + int ret; + int size; + struct kobject *module_kobj = NULL; + struct md_region md_entry; + + get_online_cpus(); + lpm_root_node = lpm_of_parse_cluster(pdev); + + if (IS_ERR_OR_NULL(lpm_root_node)) { + pr_err("%s(): Failed to probe low power modes\n", __func__); + put_online_cpus(); + return PTR_ERR(lpm_root_node); + } + + if (print_parsed_dt) + cluster_dt_walkthrough(lpm_root_node); + + /* + * Register hotplug notifier before broadcast time to ensure there + * to prevent race where a broadcast timer might not be setup on for a + * core. BUG in existing code but no known issues possibly because of + * how late lpm_levels gets initialized. + */ + suspend_set_ops(&lpm_suspend_ops); + hrtimer_init(&lpm_hrtimer, CLOCK_MONOTONIC, HRTIMER_MODE_REL); + hrtimer_init(&histtimer, CLOCK_MONOTONIC, HRTIMER_MODE_REL); + cluster_timer_init(lpm_root_node); + + ret = remote_spin_lock_init(&scm_handoff_lock, SCM_HANDOFF_LOCK_ID); + if (ret) { + pr_err("%s: Failed initializing scm_handoff_lock (%d)\n", + __func__, ret); + put_online_cpus(); + return ret; + } + + size = num_dbg_elements * sizeof(struct lpm_debug); + lpm_debug = dma_alloc_coherent(&pdev->dev, size, + &lpm_debug_phys, GFP_KERNEL); + register_cluster_lpm_stats(lpm_root_node, NULL); + + ret = cluster_cpuidle_register(lpm_root_node); + put_online_cpus(); + if (ret) { + pr_err("%s()Failed to register with cpuidle framework\n", + __func__); + goto failed; + } + register_hotcpu_notifier(&lpm_cpu_nblk); + module_kobj = kset_find_obj(module_kset, KBUILD_MODNAME); + if (!module_kobj) { + pr_err("%s: cannot find kobject for module %s\n", + __func__, KBUILD_MODNAME); + ret = -ENOENT; + goto failed; + } + + ret = create_cluster_lvl_nodes(lpm_root_node, module_kobj); + if (ret) { + pr_err("%s(): Failed to create cluster level nodes\n", + __func__); + goto failed; + } + + /* Add lpm_debug to Minidump*/ + strlcpy(md_entry.name, "KLPMDEBUG", sizeof(md_entry.name)); + md_entry.virt_addr = (uintptr_t)lpm_debug; + md_entry.phys_addr = lpm_debug_phys; + md_entry.size = size; + if (msm_minidump_add_region(&md_entry)) + pr_info("Failed to add lpm_debug in Minidump\n"); + + return 0; +failed: + free_cluster_node(lpm_root_node); + lpm_root_node = NULL; + return ret; +} + +static struct of_device_id lpm_mtch_tbl[] = { + {.compatible = "qcom,lpm-levels"}, + {}, +}; + +static struct platform_driver lpm_driver = { + .probe = lpm_probe, + .driver = { + .name = "lpm-levels", + .owner = THIS_MODULE, + .of_match_table = lpm_mtch_tbl, + }, +}; + +static int __init lpm_levels_module_init(void) +{ + int rc; + rc = platform_driver_register(&lpm_driver); + if (rc) { + pr_info("Error registering %s\n", lpm_driver.driver.name); + goto fail; + } + +#ifdef CONFIG_ARM_PSCI + rc = set_cpuidle_ops(); + if (rc) { + pr_err("%s(): Failed to set cpuidle ops\n", __func__); + goto fail; + } +#endif + +fail: + return rc; +} +late_initcall(lpm_levels_module_init); + +enum msm_pm_l2_scm_flag lpm_cpu_pre_pc_cb(unsigned int cpu) +{ + struct lpm_cluster *cluster = per_cpu(cpu_cluster, cpu); + enum msm_pm_l2_scm_flag retflag = MSM_SCM_L2_ON; + + /* + * No need to acquire the lock if probe isn't completed yet + * In the event of the hotplug happening before lpm probe, we want to + * flush the cache to make sure that L2 is flushed. In particular, this + * could cause incoherencies for a cluster architecture. This wouldn't + * affect the idle case as the idle driver wouldn't be registered + * before the probe function + */ + if (!cluster) + return MSM_SCM_L2_OFF; + + /* + * Assumes L2 only. What/How parameters gets passed into TZ will + * determine how this function reports this info back in msm-pm.c + */ + spin_lock(&cluster->sync_lock); + + if (!cluster->lpm_dev) { + retflag = MSM_SCM_L2_OFF; + goto unlock_and_return; + } + + if (!cpumask_equal(&cluster->num_children_in_sync, + &cluster->child_cpus)) + goto unlock_and_return; + + if (cluster->lpm_dev) + retflag = cluster->lpm_dev->tz_flag; + /* + * The scm_handoff_lock will be release by the secure monitor. + * It is used to serialize power-collapses from this point on, + * so that both Linux and the secure context have a consistent + * view regarding the number of running cpus (cpu_count). + * + * It must be acquired before releasing the cluster lock. + */ +unlock_and_return: + update_debug_pc_event(PRE_PC_CB, retflag, 0xdeadbeef, 0xdeadbeef, + 0xdeadbeef); + trace_pre_pc_cb(retflag); + remote_spin_lock_rlock_id(&scm_handoff_lock, + REMOTE_SPINLOCK_TID_START + cpu); + spin_unlock(&cluster->sync_lock); + return retflag; +} --- /dev/null 2019-10-24 16:47:25.704025805 +0200 +++ linux-4.4.115-fbx/drivers/cpuidle/lpm-levels.h 2019-01-22 16:16:23.095242712 +0100 @@ -0,0 +1,166 @@ +/* Copyright (c) 2014-2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include + +#define NR_LPM_LEVELS 8 +#define MAXSAMPLES 5 +#define CLUST_SMPL_INVLD_TIME 40000 + +extern bool use_psci; + +struct lpm_lookup_table { + uint32_t modes; + const char *mode_name; +}; + +struct power_params { + uint32_t latency_us; /* Enter + Exit latency */ + uint32_t ss_power; /* Steady state power */ + uint32_t energy_overhead; /* Enter + exit over head */ + uint32_t time_overhead_us; /* Enter + exit overhead */ + uint32_t residencies[NR_LPM_LEVELS]; + uint32_t min_residency; + uint32_t max_residency; +}; + +struct lpm_cpu_level { + const char *name; + enum msm_pm_sleep_mode mode; + bool use_bc_timer; + struct power_params pwr; + unsigned int psci_id; + bool is_reset; + bool jtag_save_restore; + bool hyp_psci; + int reset_level; +}; + +struct lpm_cpu { + struct lpm_cpu_level levels[NR_LPM_LEVELS]; + int nlevels; + unsigned int psci_mode_shift; + unsigned int psci_mode_mask; + struct lpm_cluster *parent; +}; + +struct lpm_level_avail { + bool idle_enabled; + bool suspend_enabled; + struct kobject *kobj; + struct kobj_attribute idle_enabled_attr; + struct kobj_attribute suspend_enabled_attr; + void *data; + int idx; + bool cpu_node; +}; + +struct lpm_cluster_level { + const char *level_name; + int *mode; /* SPM mode to enter */ + int min_child_level; + struct cpumask num_cpu_votes; + struct power_params pwr; + bool notify_rpm; + bool disable_dynamic_routing; + bool sync_level; + bool last_core_only; + struct lpm_level_avail available; + unsigned int psci_id; + bool is_reset; + int reset_level; +}; + +struct low_power_ops { + struct msm_spm_device *spm; + int (*set_mode)(struct low_power_ops *ops, int mode, bool notify_rpm); + enum msm_pm_l2_scm_flag tz_flag; +}; + +struct cluster_history { + uint32_t resi[MAXSAMPLES]; + int mode[MAXSAMPLES]; + int64_t stime[MAXSAMPLES]; + uint32_t hptr; + uint32_t hinvalid; + uint32_t htmr_wkup; + uint64_t entry_time; + int entry_idx; + int nsamp; + int flag; +}; + +struct lpm_cluster { + struct list_head list; + struct list_head child; + const char *cluster_name; + const char **name; + unsigned long aff_level; /* Affinity level of the node */ + struct low_power_ops *lpm_dev; + int ndevices; + struct lpm_cluster_level levels[NR_LPM_LEVELS]; + int nlevels; + enum msm_pm_l2_scm_flag l2_flag; + int min_child_level; + int default_level; + int last_level; + struct lpm_cpu *cpu; + struct cpuidle_driver *drv; + spinlock_t sync_lock; + struct cpumask child_cpus; + struct cpumask num_children_in_sync; + struct lpm_cluster *parent; + struct lpm_stats *stats; + unsigned int psci_mode_shift; + unsigned int psci_mode_mask; + bool no_saw_devices; + struct cluster_history history; + struct hrtimer histtimer; +}; + +int set_l2_mode(struct low_power_ops *ops, int mode, bool notify_rpm); +int set_system_mode(struct low_power_ops *ops, int mode, bool notify_rpm); +int set_l3_mode(struct low_power_ops *ops, int mode, bool notify_rpm); +void lpm_suspend_wake_time(uint64_t wakeup_time); + +struct lpm_cluster *lpm_of_parse_cluster(struct platform_device *pdev); +void free_cluster_node(struct lpm_cluster *cluster); +void cluster_dt_walkthrough(struct lpm_cluster *cluster); + +int create_cluster_lvl_nodes(struct lpm_cluster *p, struct kobject *kobj); +bool lpm_cpu_mode_allow(unsigned int cpu, + unsigned int mode, bool from_idle); +bool lpm_cluster_mode_allow(struct lpm_cluster *cluster, + unsigned int mode, bool from_idle); +uint32_t *get_per_cpu_max_residency(int cpu); +uint32_t *get_per_cpu_min_residency(int cpu); +extern struct lpm_cluster *lpm_root_node; + +#ifdef CONFIG_SMP +extern DEFINE_PER_CPU(bool, pending_ipi); +static inline bool is_IPI_pending(const struct cpumask *mask) +{ + unsigned int cpu; + + for_each_cpu(cpu, mask) { + if per_cpu(pending_ipi, cpu) + return true; + } + return false; +} +#else +static inline bool is_IPI_pending(const struct cpumask *mask) +{ + return false; +} +#endif --- /dev/null 2019-10-24 16:47:25.704025805 +0200 +++ linux-4.4.115-fbx/drivers/cpuidle/lpm-levels-of.c 2019-01-22 16:16:23.095242712 +0100 @@ -0,0 +1,1022 @@ +/* Copyright (c) 2014-2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "lpm-levels.h" + +bool use_psci; +enum lpm_type { + IDLE = 0, + SUSPEND, + LPM_TYPE_NR +}; + +struct lpm_type_str { + enum lpm_type type; + char *str; +}; + +static const struct lpm_type_str lpm_types[] = { + {IDLE, "idle_enabled"}, + {SUSPEND, "suspend_enabled"}, +}; + +static DEFINE_PER_CPU(uint32_t *, max_residency); +static DEFINE_PER_CPU(uint32_t *, min_residency); +static struct lpm_level_avail *cpu_level_available[NR_CPUS]; +static struct platform_device *lpm_pdev; + +static void *get_enabled_ptr(struct kobj_attribute *attr, + struct lpm_level_avail *avail) +{ + void *arg = NULL; + + if (!strcmp(attr->attr.name, lpm_types[IDLE].str)) + arg = (void *) &avail->idle_enabled; + else if (!strcmp(attr->attr.name, lpm_types[SUSPEND].str)) + arg = (void *) &avail->suspend_enabled; + + return arg; +} + +static struct lpm_level_avail *get_avail_ptr(struct kobject *kobj, + struct kobj_attribute *attr) +{ + struct lpm_level_avail *avail = NULL; + + if (!strcmp(attr->attr.name, lpm_types[IDLE].str)) + avail = container_of(attr, struct lpm_level_avail, + idle_enabled_attr); + else if (!strcmp(attr->attr.name, lpm_types[SUSPEND].str)) + avail = container_of(attr, struct lpm_level_avail, + suspend_enabled_attr); + + return avail; +} + +static void set_optimum_cpu_residency(struct lpm_cpu *cpu, int cpu_id, + bool probe_time) +{ + int i, j; + bool mode_avail; + uint32_t *maximum_residency = per_cpu(max_residency, cpu_id); + uint32_t *minimum_residency = per_cpu(min_residency, cpu_id); + + for (i = 0; i < cpu->nlevels; i++) { + struct power_params *pwr = &cpu->levels[i].pwr; + + mode_avail = probe_time || + lpm_cpu_mode_allow(cpu_id, i, true); + + if (!mode_avail) { + maximum_residency[i] = 0; + minimum_residency[i] = 0; + continue; + } + + maximum_residency[i] = ~0; + for (j = i + 1; j < cpu->nlevels; j++) { + mode_avail = probe_time || + lpm_cpu_mode_allow(cpu_id, j, true); + + if (mode_avail && + (maximum_residency[i] > pwr->residencies[j]) && + (pwr->residencies[j] != 0)) + maximum_residency[i] = pwr->residencies[j]; + } + + minimum_residency[i] = pwr->time_overhead_us; + for (j = i-1; j >= 0; j--) { + if (probe_time || lpm_cpu_mode_allow(cpu_id, j, true)) { + minimum_residency[i] = maximum_residency[j] + 1; + break; + } + } + } +} + +static void set_optimum_cluster_residency(struct lpm_cluster *cluster, + bool probe_time) +{ + int i, j; + bool mode_avail; + + for (i = 0; i < cluster->nlevels; i++) { + struct power_params *pwr = &cluster->levels[i].pwr; + + mode_avail = probe_time || + lpm_cluster_mode_allow(cluster, i, + true); + + if (!mode_avail) { + pwr->max_residency = 0; + pwr->min_residency = 0; + continue; + } + + pwr->max_residency = ~0; + for (j = i+1; j < cluster->nlevels; j++) { + mode_avail = probe_time || + lpm_cluster_mode_allow(cluster, j, + true); + if (mode_avail && + (pwr->max_residency > pwr->residencies[j]) && + (pwr->residencies[j] != 0)) + pwr->max_residency = pwr->residencies[j]; + } + + pwr->min_residency = pwr->time_overhead_us; + for (j = i-1; j >= 0; j--) { + if (probe_time || + lpm_cluster_mode_allow(cluster, j, true)) { + pwr->min_residency = + cluster->levels[j].pwr.max_residency + 1; + break; + } + } + } +} + +uint32_t *get_per_cpu_max_residency(int cpu) +{ + return per_cpu(max_residency, cpu); +} + +uint32_t *get_per_cpu_min_residency(int cpu) +{ + return per_cpu(min_residency, cpu); +} +ssize_t lpm_enable_show(struct kobject *kobj, struct kobj_attribute *attr, + char *buf) +{ + int ret = 0; + struct kernel_param kp; + + kp.arg = get_enabled_ptr(attr, get_avail_ptr(kobj, attr)); + ret = param_get_bool(buf, &kp); + if (ret > 0) { + strlcat(buf, "\n", PAGE_SIZE); + ret++; + } + + return ret; +} + +ssize_t lpm_enable_store(struct kobject *kobj, struct kobj_attribute *attr, + const char *buf, size_t len) +{ + int ret = 0; + struct kernel_param kp; + struct lpm_level_avail *avail; + + avail = get_avail_ptr(kobj, attr); + if (WARN_ON(!avail)) + return -EINVAL; + kp.arg = get_enabled_ptr(attr, avail); + ret = param_set_bool(buf, &kp); + + if (avail->cpu_node) + set_optimum_cpu_residency(avail->data, avail->idx, false); + else + set_optimum_cluster_residency(avail->data, false); + + return ret ? ret : len; +} + +static int create_lvl_avail_nodes(const char *name, + struct kobject *parent, struct lpm_level_avail *avail, + void *data, int index, bool cpu_node) +{ + struct attribute_group *attr_group = NULL; + struct attribute **attr = NULL; + struct kobject *kobj = NULL; + int ret = 0; + + kobj = kobject_create_and_add(name, parent); + if (!kobj) + return -ENOMEM; + + attr_group = devm_kzalloc(&lpm_pdev->dev, sizeof(*attr_group), + GFP_KERNEL); + if (!attr_group) { + ret = -ENOMEM; + goto failed; + } + + attr = devm_kzalloc(&lpm_pdev->dev, + sizeof(*attr) * (LPM_TYPE_NR + 1), GFP_KERNEL); + if (!attr) { + ret = -ENOMEM; + goto failed; + } + + sysfs_attr_init(&avail->idle_enabled_attr.attr); + avail->idle_enabled_attr.attr.name = lpm_types[IDLE].str; + avail->idle_enabled_attr.attr.mode = 0644; + avail->idle_enabled_attr.show = lpm_enable_show; + avail->idle_enabled_attr.store = lpm_enable_store; + + sysfs_attr_init(&avail->suspend_enabled_attr.attr); + avail->suspend_enabled_attr.attr.name = lpm_types[SUSPEND].str; + avail->suspend_enabled_attr.attr.mode = 0644; + avail->suspend_enabled_attr.show = lpm_enable_show; + avail->suspend_enabled_attr.store = lpm_enable_store; + + attr[0] = &avail->idle_enabled_attr.attr; + attr[1] = &avail->suspend_enabled_attr.attr; + attr[2] = NULL; + attr_group->attrs = attr; + + ret = sysfs_create_group(kobj, attr_group); + if (ret) { + ret = -ENOMEM; + goto failed; + } + + avail->idle_enabled = true; + avail->suspend_enabled = true; + avail->kobj = kobj; + avail->data = data; + avail->idx = index; + avail->cpu_node = cpu_node; + + return ret; + +failed: + kobject_put(kobj); + return ret; +} + +static int create_cpu_lvl_nodes(struct lpm_cluster *p, struct kobject *parent) +{ + int cpu; + int i, cpu_idx; + struct kobject **cpu_kobj = NULL; + struct lpm_level_avail *level_list = NULL; + char cpu_name[20] = {0}; + int ret = 0; + + cpu_kobj = devm_kzalloc(&lpm_pdev->dev, sizeof(*cpu_kobj) * + cpumask_weight(&p->child_cpus), GFP_KERNEL); + if (!cpu_kobj) + return -ENOMEM; + + cpu_idx = 0; + for_each_cpu(cpu, &p->child_cpus) { + snprintf(cpu_name, sizeof(cpu_name), "cpu%d", cpu); + cpu_kobj[cpu_idx] = kobject_create_and_add(cpu_name, parent); + if (!cpu_kobj[cpu_idx]) { + ret = -ENOMEM; + goto release_kobj; + } + + level_list = devm_kzalloc(&lpm_pdev->dev, + p->cpu->nlevels * sizeof(*level_list), + GFP_KERNEL); + if (!level_list) { + ret = -ENOMEM; + goto release_kobj; + } + + for (i = 0; i < p->cpu->nlevels; i++) { + + ret = create_lvl_avail_nodes(p->cpu->levels[i].name, + cpu_kobj[cpu_idx], &level_list[i], + (void *)p->cpu, cpu, true); + if (ret) + goto release_kobj; + } + + cpu_level_available[cpu] = level_list; + cpu_idx++; + } + + return ret; + +release_kobj: + for (i = 0; i < cpumask_weight(&p->child_cpus); i++) + kobject_put(cpu_kobj[i]); + + return ret; +} + +int create_cluster_lvl_nodes(struct lpm_cluster *p, struct kobject *kobj) +{ + int ret = 0; + struct lpm_cluster *child = NULL; + int i; + struct kobject *cluster_kobj = NULL; + + if (!p) + return -ENODEV; + + cluster_kobj = kobject_create_and_add(p->cluster_name, kobj); + if (!cluster_kobj) + return -ENOMEM; + + for (i = 0; i < p->nlevels; i++) { + ret = create_lvl_avail_nodes(p->levels[i].level_name, + cluster_kobj, &p->levels[i].available, + (void *)p, 0, false); + if (ret) + return ret; + } + + list_for_each_entry(child, &p->child, list) { + ret = create_cluster_lvl_nodes(child, cluster_kobj); + if (ret) + return ret; + } + + if (p->cpu) { + ret = create_cpu_lvl_nodes(p, cluster_kobj); + if (ret) + return ret; + } + + return 0; +} + +bool lpm_cpu_mode_allow(unsigned int cpu, + unsigned int index, bool from_idle) +{ + struct lpm_level_avail *avail = cpu_level_available[cpu]; + + if (!lpm_pdev || !avail) + return !from_idle; + + return !!(from_idle ? avail[index].idle_enabled : + avail[index].suspend_enabled); +} + +bool lpm_cluster_mode_allow(struct lpm_cluster *cluster, + unsigned int mode, bool from_idle) +{ + struct lpm_level_avail *avail = &cluster->levels[mode].available; + + if (!lpm_pdev || !avail) + return false; + + return !!(from_idle ? avail->idle_enabled : + avail->suspend_enabled); +} + +static int parse_legacy_cluster_params(struct device_node *node, + struct lpm_cluster *c) +{ + int i; + char *key; + int ret; + struct lpm_match { + char *devname; + int (*set_mode)(struct low_power_ops *, int, bool); + }; + struct lpm_match match_tbl[] = { + {"l2", set_l2_mode}, + {"cci", set_system_mode}, + {"l3", set_l3_mode}, + {"cbf", set_system_mode}, + }; + + + key = "qcom,spm-device-names"; + c->ndevices = of_property_count_strings(node, key); + + if (c->ndevices < 0) { + pr_info("%s(): Ignoring cluster params\n", __func__); + c->no_saw_devices = true; + c->ndevices = 0; + return 0; + } + + c->name = devm_kzalloc(&lpm_pdev->dev, c->ndevices * sizeof(*c->name), + GFP_KERNEL); + c->lpm_dev = devm_kzalloc(&lpm_pdev->dev, + c->ndevices * sizeof(*c->lpm_dev), + GFP_KERNEL); + if (!c->name || !c->lpm_dev) { + ret = -ENOMEM; + goto failed; + } + + for (i = 0; i < c->ndevices; i++) { + char device_name[20]; + int j; + + ret = of_property_read_string_index(node, key, i, &c->name[i]); + if (ret) + goto failed; + snprintf(device_name, sizeof(device_name), "%s-%s", + c->cluster_name, c->name[i]); + + c->lpm_dev[i].spm = msm_spm_get_device_by_name(device_name); + + if (IS_ERR_OR_NULL(c->lpm_dev[i].spm)) { + pr_err("Failed to get spm device by name:%s\n", + device_name); + ret = PTR_ERR(c->lpm_dev[i].spm); + goto failed; + } + for (j = 0; j < ARRAY_SIZE(match_tbl); j++) { + if (!strcmp(c->name[i], match_tbl[j].devname)) + c->lpm_dev[i].set_mode = match_tbl[j].set_mode; + } + + if (!c->lpm_dev[i].set_mode) { + ret = -ENODEV; + goto failed; + } + } + + key = "qcom,default-level"; + if (of_property_read_u32(node, key, &c->default_level)) + c->default_level = 0; + return 0; +failed: + pr_err("%s(): Failed reading %s\n", __func__, key); + return ret; +} + +static int parse_cluster_params(struct device_node *node, + struct lpm_cluster *c) +{ + char *key; + int ret; + + key = "label"; + ret = of_property_read_string(node, key, &c->cluster_name); + if (ret) { + pr_err("%s(): Cannot read required param %s\n", __func__, key); + return ret; + } + + if (use_psci) { + key = "qcom,psci-mode-shift"; + ret = of_property_read_u32(node, key, + &c->psci_mode_shift); + if (ret) { + pr_err("%s(): Failed to read param: %s\n", + __func__, key); + return ret; + } + + key = "qcom,psci-mode-mask"; + ret = of_property_read_u32(node, key, + &c->psci_mode_mask); + if (ret) { + pr_err("%s(): Failed to read param: %s\n", + __func__, key); + return ret; + } + + /* Set ndevice to 1 as default */ + c->ndevices = 1; + + return 0; + } else + return parse_legacy_cluster_params(node, c); +} + +static int parse_lpm_mode(const char *str) +{ + int i; + struct lpm_lookup_table mode_lookup[] = { + {MSM_SPM_MODE_POWER_COLLAPSE, "pc"}, + {MSM_SPM_MODE_STANDALONE_POWER_COLLAPSE, "spc"}, + {MSM_SPM_MODE_FASTPC, "fpc"}, + {MSM_SPM_MODE_GDHS, "gdhs"}, + {MSM_SPM_MODE_RETENTION, "retention"}, + {MSM_SPM_MODE_CLOCK_GATING, "wfi"}, + {MSM_SPM_MODE_DISABLED, "active"} + }; + + for (i = 0; i < ARRAY_SIZE(mode_lookup); i++) + if (!strcmp(str, mode_lookup[i].mode_name)) + return mode_lookup[i].modes; + return -EINVAL; +} + +static int parse_power_params(struct device_node *node, + struct power_params *pwr) +{ + char *key; + int ret; + + key = "qcom,latency-us"; + ret = of_property_read_u32(node, key, &pwr->latency_us); + if (ret) + goto fail; + + key = "qcom,ss-power"; + ret = of_property_read_u32(node, key, &pwr->ss_power); + if (ret) + goto fail; + + key = "qcom,energy-overhead"; + ret = of_property_read_u32(node, key, &pwr->energy_overhead); + if (ret) + goto fail; + + key = "qcom,time-overhead"; + ret = of_property_read_u32(node, key, &pwr->time_overhead_us); + if (ret) + goto fail; + +fail: + if (ret) + pr_err("%s(): %s Error reading %s\n", __func__, node->name, + key); + return ret; +} + +static int parse_cluster_level(struct device_node *node, + struct lpm_cluster *cluster) +{ + int i = 0; + struct lpm_cluster_level *level = &cluster->levels[cluster->nlevels]; + int ret = -ENOMEM; + char *key; + + key = "label"; + ret = of_property_read_string(node, key, &level->level_name); + if (ret) + goto failed; + + if (use_psci) { + char *k = "qcom,psci-mode"; + ret = of_property_read_u32(node, k, &level->psci_id); + if (ret) + goto failed; + + level->is_reset = of_property_read_bool(node, "qcom,is-reset"); + } else if (!cluster->no_saw_devices) { + key = "no saw-devices"; + + level->mode = devm_kzalloc(&lpm_pdev->dev, + cluster->ndevices * sizeof(*level->mode), + GFP_KERNEL); + if (!level->mode) { + pr_err("Memory allocation failed\n"); + goto failed; + } + + for (i = 0; i < cluster->ndevices; i++) { + const char *spm_mode; + char key[25] = {0}; + + snprintf(key, 25, "qcom,spm-%s-mode", cluster->name[i]); + ret = of_property_read_string(node, key, &spm_mode); + if (ret) + goto failed; + + level->mode[i] = parse_lpm_mode(spm_mode); + + if (level->mode[i] < 0) + goto failed; + + if (level->mode[i] == MSM_SPM_MODE_POWER_COLLAPSE + || level->mode[i] == + MSM_SPM_MODE_STANDALONE_POWER_COLLAPSE) + level->is_reset |= true; + } + } + + key = "label"; + ret = of_property_read_string(node, key, &level->level_name); + if (ret) + goto failed; + + if (cluster->nlevels != cluster->default_level) { + key = "min child idx"; + ret = of_property_read_u32(node, "qcom,min-child-idx", + &level->min_child_level); + if (ret) + goto failed; + + if (cluster->min_child_level > level->min_child_level) + cluster->min_child_level = level->min_child_level; + } + + level->notify_rpm = of_property_read_bool(node, "qcom,notify-rpm"); + level->disable_dynamic_routing = of_property_read_bool(node, + "qcom,disable-dynamic-int-routing"); + level->last_core_only = of_property_read_bool(node, + "qcom,last-core-only"); + + key = "parse_power_params"; + ret = parse_power_params(node, &level->pwr); + if (ret) + goto failed; + + key = "qcom,reset-level"; + ret = of_property_read_u32(node, key, &level->reset_level); + if (ret == -EINVAL) + level->reset_level = LPM_RESET_LVL_NONE; + else if (ret) + goto failed; + + cluster->nlevels++; + return 0; +failed: + pr_err("Failed %s() key = %s ret = %d\n", __func__, key, ret); + return ret; +} + +static int parse_cpu_spm_mode(const char *mode_name) +{ + struct lpm_lookup_table pm_sm_lookup[] = { + {MSM_PM_SLEEP_MODE_WAIT_FOR_INTERRUPT, + "wfi"}, + {MSM_PM_SLEEP_MODE_POWER_COLLAPSE_STANDALONE, + "standalone_pc"}, + {MSM_PM_SLEEP_MODE_POWER_COLLAPSE, + "pc"}, + {MSM_PM_SLEEP_MODE_RETENTION, + "retention"}, + {MSM_PM_SLEEP_MODE_FASTPC, + "fpc"}, + }; + int i; + int ret = -EINVAL; + + for (i = 0; i < ARRAY_SIZE(pm_sm_lookup); i++) { + if (!strcmp(mode_name, pm_sm_lookup[i].mode_name)) { + ret = pm_sm_lookup[i].modes; + break; + } + } + return ret; +} + +static int parse_cpu_mode(struct device_node *n, struct lpm_cpu_level *l) +{ + char *key; + int ret; + + key = "qcom,spm-cpu-mode"; + ret = of_property_read_string(n, key, &l->name); + if (ret) { + pr_err("Failed %s %d\n", n->name, __LINE__); + return ret; + } + + if (use_psci) { + key = "qcom,psci-cpu-mode"; + + ret = of_property_read_u32(n, key, &l->psci_id); + if (ret) { + pr_err("Failed reading %s on device %s\n", key, + n->name); + return ret; + } + key = "qcom,hyp-psci"; + + l->hyp_psci = of_property_read_bool(n, key); + } else { + l->mode = parse_cpu_spm_mode(l->name); + + if (l->mode < 0) + return l->mode; + } + return 0; + +} + +static int get_cpumask_for_node(struct device_node *node, struct cpumask *mask) +{ + struct device_node *cpu_node; + int cpu; + int idx = 0; + + cpu_node = of_parse_phandle(node, "qcom,cpu", idx++); + if (!cpu_node) { + pr_info("%s: No CPU phandle, assuming single cluster\n", + node->full_name); + /* + * Not all targets have the cpu node populated in the device + * tree. If cpu node is not populated assume all possible + * nodes belong to this cluster + */ + cpumask_copy(mask, cpu_possible_mask); + return 0; + } + + while (cpu_node) { + for_each_possible_cpu(cpu) { + if (of_get_cpu_node(cpu, NULL) == cpu_node) { + cpumask_set_cpu(cpu, mask); + break; + } + } + cpu_node = of_parse_phandle(node, "qcom,cpu", idx++); + } + + return 0; +} + +static int calculate_residency(struct power_params *base_pwr, + struct power_params *next_pwr) +{ + int32_t residency = (int32_t)(next_pwr->energy_overhead - + base_pwr->energy_overhead) - + ((int32_t)(next_pwr->ss_power * next_pwr->time_overhead_us) + - (int32_t)(base_pwr->ss_power * base_pwr->time_overhead_us)); + + residency /= (int32_t)(base_pwr->ss_power - next_pwr->ss_power); + + if (residency < 0) { + pr_err("%s: residency < 0 for LPM\n", + __func__); + return next_pwr->time_overhead_us; + } + + return residency < next_pwr->time_overhead_us ? + next_pwr->time_overhead_us : residency; +} + +static int parse_cpu_levels(struct device_node *node, struct lpm_cluster *c) +{ + struct device_node *n; + int ret = -ENOMEM; + int i, j; + char *key; + + c->cpu = devm_kzalloc(&lpm_pdev->dev, sizeof(*c->cpu), GFP_KERNEL); + if (!c->cpu) + return ret; + + c->cpu->parent = c; + if (use_psci) { + + key = "qcom,psci-mode-shift"; + + ret = of_property_read_u32(node, key, &c->cpu->psci_mode_shift); + if (ret) { + pr_err("Failed reading %s on device %s\n", key, + node->name); + return ret; + } + key = "qcom,psci-mode-mask"; + + ret = of_property_read_u32(node, key, &c->cpu->psci_mode_mask); + if (ret) { + pr_err("Failed reading %s on device %s\n", key, + node->name); + return ret; + } + } + for_each_child_of_node(node, n) { + struct lpm_cpu_level *l = &c->cpu->levels[c->cpu->nlevels]; + + c->cpu->nlevels++; + + ret = parse_cpu_mode(n, l); + if (ret < 0) { + pr_info("Failed %s\n", l->name); + goto failed; + } + + ret = parse_power_params(n, &l->pwr); + if (ret) + goto failed; + + key = "qcom,use-broadcast-timer"; + l->use_bc_timer = of_property_read_bool(n, key); + + l->is_reset = of_property_read_bool(n, "qcom,is-reset"); + + key = "qcom,jtag-save-restore"; + l->jtag_save_restore = of_property_read_bool(n, key); + + key = "qcom,reset-level"; + ret = of_property_read_u32(n, key, &l->reset_level); + if (ret == -EINVAL) + l->reset_level = LPM_RESET_LVL_NONE; + else if (ret) + goto failed; + } + for (i = 0; i < c->cpu->nlevels; i++) { + for (j = 0; j < c->cpu->nlevels; j++) { + if (i >= j) { + c->cpu->levels[i].pwr.residencies[j] = 0; + continue; + } + + c->cpu->levels[i].pwr.residencies[j] = + calculate_residency(&c->cpu->levels[i].pwr, + &c->cpu->levels[j].pwr); + + pr_err("%s: idx %d %u\n", __func__, j, + c->cpu->levels[i].pwr.residencies[j]); + } + } + + return 0; +failed: + pr_err("%s(): Failed with error code:%d\n", __func__, ret); + return ret; +} + +void free_cluster_node(struct lpm_cluster *cluster) +{ + struct lpm_cluster *cl, *m; + + list_for_each_entry_safe(cl, m, &cluster->child, list) { + list_del(&cl->list); + free_cluster_node(cl); + }; + + cluster->ndevices = 0; +} + +/* + * TODO: + * Expects a CPU or a cluster only. This ensures that affinity + * level of a cluster is consistent with reference to its + * child nodes. + */ +struct lpm_cluster *parse_cluster(struct device_node *node, + struct lpm_cluster *parent) +{ + struct lpm_cluster *c; + struct device_node *n; + char *key; + int ret = 0; + int i, j; + + c = devm_kzalloc(&lpm_pdev->dev, sizeof(*c), GFP_KERNEL); + if (!c) + return ERR_PTR(-ENOMEM); + + ret = parse_cluster_params(node, c); + + if (ret) + goto failed_parse_params; + + INIT_LIST_HEAD(&c->child); + c->parent = parent; + spin_lock_init(&c->sync_lock); + c->min_child_level = NR_LPM_LEVELS; + + for_each_child_of_node(node, n) { + + if (!n->name) + continue; + key = "qcom,pm-cluster-level"; + if (!of_node_cmp(n->name, key)) { + WARN_ON(!use_psci && c->no_saw_devices); + if (parse_cluster_level(n, c)) + goto failed_parse_cluster; + continue; + } + + key = "qcom,pm-cluster"; + if (!of_node_cmp(n->name, key)) { + struct lpm_cluster *child; + + WARN_ON(!use_psci && c->no_saw_devices); + child = parse_cluster(n, c); + if (!child) + goto failed_parse_cluster; + + list_add(&child->list, &c->child); + cpumask_or(&c->child_cpus, &c->child_cpus, + &child->child_cpus); + c->aff_level = child->aff_level + 1; + continue; + } + + key = "qcom,pm-cpu"; + if (!of_node_cmp(n->name, key)) { + /* + * Parse the the cpu node only if a pm-cpu node + * is available, though the mask is defined @ the + * cluster level + */ + if (get_cpumask_for_node(node, &c->child_cpus)) + goto failed_parse_cluster; + + if (parse_cpu_levels(n, c)) + goto failed_parse_cluster; + + c->aff_level = 1; + + for_each_cpu(i, &c->child_cpus) { + per_cpu(max_residency, i) = devm_kzalloc( + &lpm_pdev->dev, + sizeof(uint32_t) * c->cpu->nlevels, + GFP_KERNEL); + if (!per_cpu(max_residency, i)) + return ERR_PTR(-ENOMEM); + per_cpu(min_residency, i) = devm_kzalloc( + &lpm_pdev->dev, + sizeof(uint32_t) * c->cpu->nlevels, + GFP_KERNEL); + if (!per_cpu(min_residency, i)) + return ERR_PTR(-ENOMEM); + set_optimum_cpu_residency(c->cpu, i, true); + } + } + } + + if (cpumask_intersects(&c->child_cpus, cpu_online_mask)) + c->last_level = c->default_level; + else + c->last_level = c->nlevels-1; + + for (i = 0; i < c->nlevels; i++) { + for (j = 0; j < c->nlevels; j++) { + if (i >= j) { + c->levels[i].pwr.residencies[j] = 0; + continue; + } + c->levels[i].pwr.residencies[j] = calculate_residency( + &c->levels[i].pwr, &c->levels[j].pwr); + } + } + set_optimum_cluster_residency(c, true); + return c; + +failed_parse_cluster: + pr_err("Failed parse cluster:%s\n", key); + if (parent) + list_del(&c->list); + free_cluster_node(c); +failed_parse_params: + pr_err("Failed parse params\n"); + return NULL; +} +struct lpm_cluster *lpm_of_parse_cluster(struct platform_device *pdev) +{ + struct device_node *top = NULL; + + use_psci = of_property_read_bool(pdev->dev.of_node, "qcom,use-psci"); + + top = of_find_node_by_name(pdev->dev.of_node, "qcom,pm-cluster"); + if (!top) { + pr_err("Failed to find root node\n"); + return ERR_PTR(-ENODEV); + } + + lpm_pdev = pdev; + return parse_cluster(top, NULL); +} + +void cluster_dt_walkthrough(struct lpm_cluster *cluster) +{ + struct list_head *list; + int i, j; + static int id; + char str[10] = {0}; + + if (!cluster) + return; + + for (i = 0; i < id; i++) + snprintf(str+i, 10 - i, "\t"); + pr_info("%d\n", __LINE__); + + for (i = 0; i < cluster->nlevels; i++) { + struct lpm_cluster_level *l = &cluster->levels[i]; + pr_info("%d ndevices:%d\n", __LINE__, cluster->ndevices); + for (j = 0; j < cluster->ndevices; j++) + pr_info("%sDevice: %p id:%p\n", str, + &cluster->name[j], &l->mode[i]); + } + + if (cluster->cpu) { + pr_info("%d\n", __LINE__); + for (j = 0; j < cluster->cpu->nlevels; j++) + pr_info("%s\tCPU mode: %s id:%d\n", str, + cluster->cpu->levels[j].name, + cluster->cpu->levels[j].mode); + } + + id++; + + + list_for_each(list, &cluster->child) { + struct lpm_cluster *n; + pr_info("%d\n", __LINE__); + n = list_entry(list, typeof(*n), list); + cluster_dt_walkthrough(n); + } + id--; +} --- /dev/null 2019-10-24 16:47:25.704025805 +0200 +++ linux-4.4.115-fbx/drivers/cpuidle/lpm-workarounds.c 2019-01-22 16:16:23.095242712 +0100 @@ -0,0 +1,134 @@ +/* Copyright (c) 2014, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +static struct regulator *lpm_cx_reg; +static struct work_struct dummy_vote_work; +static struct workqueue_struct *lpm_wa_wq; +static bool lpm_wa_cx_turbo_unvote; + +/* While exiting from RPM assisted power collapse on some targets like MSM8939 + * the CX is bumped to turbo mode by RPM. To reduce the power impact, APSS + * low power driver need to remove the CX turbo vote. + */ +static void send_dummy_cx_vote(struct work_struct *w) +{ + if (lpm_cx_reg) { + regulator_set_voltage(lpm_cx_reg, + RPM_REGULATOR_CORNER_SUPER_TURBO, + RPM_REGULATOR_CORNER_SUPER_TURBO); + + regulator_set_voltage(lpm_cx_reg, + RPM_REGULATOR_CORNER_NONE, + RPM_REGULATOR_CORNER_SUPER_TURBO); + } +} + +/* + * lpm_wa_cx_unvote_send(): Unvote for CX turbo mode + */ +void lpm_wa_cx_unvote_send(void) +{ + if (lpm_wa_cx_turbo_unvote) + queue_work(lpm_wa_wq, &dummy_vote_work); +} +EXPORT_SYMBOL(lpm_wa_cx_unvote_send); + +static int lpm_wa_cx_unvote_init(struct platform_device *pdev) +{ + int ret = 0; + + lpm_cx_reg = devm_regulator_get(&pdev->dev, "lpm-cx"); + if (IS_ERR(lpm_cx_reg)) { + ret = PTR_ERR(lpm_cx_reg); + if (ret != -EPROBE_DEFER) + pr_err("Unable to get the CX regulator\n"); + return ret; + } + + INIT_WORK(&dummy_vote_work, send_dummy_cx_vote); + + lpm_wa_wq = alloc_workqueue("lpm-wa", + WQ_UNBOUND | WQ_MEM_RECLAIM | WQ_HIGHPRI, 1); + + return ret; +} + +static int lpm_wa_cx_unvote_exit(void) +{ + if (lpm_wa_wq) + destroy_workqueue(lpm_wa_wq); + + return 0; +} + +static int lpm_wa_probe(struct platform_device *pdev) +{ + int ret = 0; + + lpm_wa_cx_turbo_unvote = of_property_read_bool(pdev->dev.of_node, + "qcom,lpm-wa-cx-turbo-unvote"); + if (lpm_wa_cx_turbo_unvote) { + ret = lpm_wa_cx_unvote_init(pdev); + if (ret) { + pr_err("%s: Failed to initialize lpm_wa_cx_unvote (%d)\n", + __func__, ret); + return ret; + } + } + + return ret; +} + +static int lpm_wa_remove(struct platform_device *pdev) +{ + int ret = 0; + if (lpm_wa_cx_turbo_unvote) + ret = lpm_wa_cx_unvote_exit(); + + return ret; +} + +static struct of_device_id lpm_wa_mtch_tbl[] = { + {.compatible = "qcom,lpm-workarounds"}, + {}, +}; + +static struct platform_driver lpm_wa_driver = { + .probe = lpm_wa_probe, + .remove = lpm_wa_remove, + .driver = { + .name = "lpm-workarounds", + .owner = THIS_MODULE, + .of_match_table = lpm_wa_mtch_tbl, + }, +}; + +static int __init lpm_wa_module_init(void) +{ + int ret; + ret = platform_driver_register(&lpm_wa_driver); + if (ret) + pr_info("Error registering %s\n", lpm_wa_driver.driver.name); + + return ret; +} +late_initcall(lpm_wa_module_init); --- /dev/null 2019-10-24 16:47:25.704025805 +0200 +++ linux-4.4.115-fbx/drivers/cpuidle/lpm-workarounds.h 2019-01-22 16:16:23.095242712 +0100 @@ -0,0 +1,19 @@ +/* Copyright (c) 2014, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef __LPM_WA_H +#define __LPM_WA_H + +void lpm_wa_cx_unvote_send(void); + +#endif /* __LPM_WA_H */ diff -Nruw linux-4.4.115-fbx/drivers/crypto/msm./compat_qcedev.c linux-4.4.115-fbx/drivers/crypto/msm/compat_qcedev.c --- linux-4.4.115-fbx/drivers/crypto/msm./compat_qcedev.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-4.4.115-fbx/drivers/crypto/msm/compat_qcedev.c 2019-01-22 16:16:23.107242820 +0100 @@ -0,0 +1,424 @@ +/* + * QTI CE 32-bit compatibility syscall for 64-bit systems + * + * Copyright (c) 2014-2015, 2017, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#define pr_fmt(fmt) "COMPAT-QCEDEV: %s: " fmt, __func__ + +#include +#include +#include +#include +#include +#include "compat_qcedev.h" + +static int compat_get_qcedev_pmem_info( + struct compat_qcedev_pmem_info __user *pmem32, + struct qcedev_pmem_info __user *pmem) +{ + compat_ulong_t offset; + compat_int_t fd_src; + compat_int_t fd_dst; + int err = 0, i = 0; + uint32_t len; + + err |= get_user(fd_src, &pmem32->fd_src); + err |= put_user(fd_src, &pmem->fd_src); + + for (i = 0; i < QCEDEV_MAX_BUFFERS; i++) { + err |= get_user(offset, &pmem32->src[i].offset); + err |= put_user(offset, &pmem->src[i].offset); + err |= get_user(len, &pmem32->src[i].len); + err |= put_user(len, &pmem->src[i].len); + } + + err |= get_user(fd_dst, &pmem32->fd_dst); + err |= put_user(fd_dst, &pmem->fd_dst); + + for (i = 0; i < QCEDEV_MAX_BUFFERS; i++) { + err |= get_user(offset, &pmem32->dst[i].offset); + err |= put_user(offset, &pmem->dst[i].offset); + err |= get_user(len, &pmem32->dst[i].len); + err |= put_user(len, &pmem->dst[i].len); + } + + return err; +} + +static int compat_put_qcedev_pmem_info( + struct compat_qcedev_pmem_info __user *pmem32, + struct qcedev_pmem_info __user *pmem) +{ + compat_ulong_t offset; + compat_int_t fd_src; + compat_int_t fd_dst; + int err = 0, i = 0; + uint32_t len; + + err |= get_user(fd_src, &pmem->fd_src); + err |= put_user(fd_src, &pmem32->fd_src); + + for (i = 0; i < QCEDEV_MAX_BUFFERS; i++) { + err |= get_user(offset, &pmem->src[i].offset); + err |= put_user(offset, &pmem32->src[i].offset); + err |= get_user(len, &pmem->src[i].len); + err |= put_user(len, &pmem32->src[i].len); + } + + err |= get_user(fd_dst, &pmem->fd_dst); + err |= put_user(fd_dst, &pmem32->fd_dst); + + for (i = 0; i < QCEDEV_MAX_BUFFERS; i++) { + err |= get_user(offset, &pmem->dst[i].offset); + err |= put_user(offset, &pmem32->dst[i].offset); + err |= get_user(len, &pmem->dst[i].len); + err |= put_user(len, &pmem32->dst[i].len); + } + + return err; +} + +static int compat_get_qcedev_vbuf_info( + struct compat_qcedev_vbuf_info __user *vbuf32, + struct qcedev_vbuf_info __user *vbuf) +{ + compat_uptr_t vaddr; + int err = 0, i = 0; + uint32_t len; + + for (i = 0; i < QCEDEV_MAX_BUFFERS; i++) { + err |= get_user(vaddr, &vbuf32->src[i].vaddr); + err |= put_user(vaddr, (compat_uptr_t *)&vbuf->src[i].vaddr); + err |= get_user(len, &vbuf32->src[i].len); + err |= put_user(len, &vbuf->src[i].len); + } + + for (i = 0; i < QCEDEV_MAX_BUFFERS; i++) { + err |= get_user(vaddr, &vbuf32->dst[i].vaddr); + err |= put_user(vaddr, (compat_uptr_t *)&vbuf->dst[i].vaddr); + err |= get_user(len, &vbuf32->dst[i].len); + err |= put_user(len, &vbuf->dst[i].len); + } + return err; +} + +static int compat_put_qcedev_vbuf_info( + struct compat_qcedev_vbuf_info __user *vbuf32, + struct qcedev_vbuf_info __user *vbuf) +{ + compat_uptr_t vaddr; + int err = 0, i = 0; + uint32_t len; + + for (i = 0; i < QCEDEV_MAX_BUFFERS; i++) { + err |= get_user(vaddr, (compat_uptr_t *)&vbuf->src[i].vaddr); + err |= put_user(vaddr, &vbuf32->src[i].vaddr); + err |= get_user(len, &vbuf->src[i].len); + err |= put_user(len, &vbuf32->src[i].len); + } + + for (i = 0; i < QCEDEV_MAX_BUFFERS; i++) { + err |= get_user(vaddr, (compat_uptr_t *)&vbuf->dst[i].vaddr); + err |= put_user(vaddr, &vbuf32->dst[i].vaddr); + err |= get_user(len, &vbuf->dst[i].len); + err |= put_user(len, &vbuf32->dst[i].len); + } + return err; +} + +static int compat_get_qcedev_cipher_op_req( + struct compat_qcedev_cipher_op_req __user *data32, + struct qcedev_cipher_op_req __user *data) +{ + enum qcedev_cipher_mode_enum mode; + enum qcedev_cipher_alg_enum alg; + compat_ulong_t byteoffset; + enum qcedev_oper_enum op; + compat_ulong_t data_len; + compat_ulong_t encklen; + compat_ulong_t entries; + compat_ulong_t ivlen; + uint8_t in_place_op; + int err = 0, i = 0; + uint8_t use_pmem; + uint8_t enckey; + uint8_t iv; + + err |= get_user(use_pmem, &data32->use_pmem); + err |= put_user(use_pmem, &data->use_pmem); + + if (use_pmem) + err |= compat_get_qcedev_pmem_info(&data32->pmem, &data->pmem); + else + err |= compat_get_qcedev_vbuf_info(&data32->vbuf, &data->vbuf); + + err |= get_user(entries, &data32->entries); + err |= put_user(entries, &data->entries); + err |= get_user(data_len, &data32->data_len); + err |= put_user(data_len, &data->data_len); + err |= get_user(in_place_op, &data32->in_place_op); + err |= put_user(in_place_op, &data->in_place_op); + + for (i = 0; i < QCEDEV_MAX_KEY_SIZE; i++) { + err |= get_user(enckey, &(data32->enckey[i])); + err |= put_user(enckey, &(data->enckey[i])); + } + + err |= get_user(encklen, &data32->encklen); + err |= put_user(encklen, &data->encklen); + + for (i = 0; i < QCEDEV_MAX_IV_SIZE; i++) { + err |= get_user(iv, &(data32->iv[i])); + err |= put_user(iv, &(data->iv[i])); + } + + err |= get_user(ivlen, &data32->ivlen); + err |= put_user(ivlen, &data->ivlen); + err |= get_user(byteoffset, &data32->byteoffset); + err |= put_user(byteoffset, &data->byteoffset); + err |= get_user(alg, &data32->alg); + err |= put_user(alg, &data->alg); + err |= get_user(mode, &data32->mode); + err |= put_user(mode, &data->mode); + err |= get_user(op, &data32->op); + err |= put_user(op, &data->op); + + return err; +} + +static int compat_put_qcedev_cipher_op_req( + struct compat_qcedev_cipher_op_req __user *data32, + struct qcedev_cipher_op_req __user *data) +{ + enum qcedev_cipher_mode_enum mode; + enum qcedev_cipher_alg_enum alg; + compat_ulong_t byteoffset; + enum qcedev_oper_enum op; + compat_ulong_t data_len; + compat_ulong_t encklen; + compat_ulong_t entries; + compat_ulong_t ivlen; + uint8_t in_place_op; + int err = 0, i = 0; + uint8_t use_pmem; + uint8_t enckey; + uint8_t iv; + + err |= get_user(use_pmem, &data->use_pmem); + err |= put_user(use_pmem, &data32->use_pmem); + + if (use_pmem) + err |= compat_put_qcedev_pmem_info(&data32->pmem, &data->pmem); + else + err |= compat_put_qcedev_vbuf_info(&data32->vbuf, &data->vbuf); + + err |= get_user(entries, &data->entries); + err |= put_user(entries, &data32->entries); + err |= get_user(data_len, &data->data_len); + err |= put_user(data_len, &data32->data_len); + err |= get_user(in_place_op, &data->in_place_op); + err |= put_user(in_place_op, &data32->in_place_op); + + for (i = 0; i < QCEDEV_MAX_KEY_SIZE; i++) { + err |= get_user(enckey, &(data->enckey[i])); + err |= put_user(enckey, &(data32->enckey[i])); + } + + err |= get_user(encklen, &data->encklen); + err |= put_user(encklen, &data32->encklen); + + for (i = 0; i < QCEDEV_MAX_IV_SIZE; i++) { + err |= get_user(iv, &(data->iv[i])); + err |= put_user(iv, &(data32->iv[i])); + } + + err |= get_user(ivlen, &data->ivlen); + err |= put_user(ivlen, &data32->ivlen); + err |= get_user(byteoffset, &data->byteoffset); + err |= put_user(byteoffset, &data32->byteoffset); + err |= get_user(alg, &data->alg); + err |= put_user(alg, &data32->alg); + err |= get_user(mode, &data->mode); + err |= put_user(mode, &data32->mode); + err |= get_user(op, &data->op); + err |= put_user(op, &data32->op); + + return err; +} + +static int compat_get_qcedev_sha_op_req( + struct compat_qcedev_sha_op_req __user *data32, + struct qcedev_sha_op_req __user *data) +{ + enum qcedev_sha_alg_enum alg; + compat_ulong_t authklen; + compat_ulong_t data_len; + compat_ulong_t entries; + compat_ulong_t diglen; + compat_uptr_t authkey; + compat_uptr_t vaddr; + int err = 0, i = 0; + uint8_t digest; + uint32_t len; + + for (i = 0; i < QCEDEV_MAX_BUFFERS; i++) { + err |= get_user(vaddr, &data32->data[i].vaddr); + err |= put_user(vaddr, (compat_uptr_t *)&data->data[i].vaddr); + err |= get_user(len, &data32->data[i].len); + err |= put_user(len, &data->data[i].len); + } + + err |= get_user(entries, &data32->entries); + err |= put_user(entries, &data->entries); + err |= get_user(data_len, &data32->data_len); + err |= put_user(data_len, &data->data_len); + + for (i = 0; i < QCEDEV_MAX_SHA_DIGEST; i++) { + err |= get_user(digest, &(data32->digest[i])); + err |= put_user(digest, &(data->digest[i])); + } + + err |= get_user(diglen, &data32->diglen); + err |= put_user(diglen, &data->diglen); + err |= get_user(authkey, &data32->authkey); + err |= put_user(authkey, (compat_uptr_t *)&data->authkey); + err |= get_user(authklen, &data32->authklen); + err |= put_user(authklen, &data->authklen); + err |= get_user(alg, &data32->alg); + err |= put_user(alg, &data->alg); + + return err; +} + +static int compat_put_qcedev_sha_op_req( + struct compat_qcedev_sha_op_req __user *data32, + struct qcedev_sha_op_req __user *data) +{ + enum qcedev_sha_alg_enum alg; + compat_ulong_t authklen; + compat_ulong_t data_len; + compat_ulong_t entries; + compat_ulong_t diglen; + compat_uptr_t authkey; + compat_uptr_t vaddr; + int err = 0, i = 0; + uint8_t digest; + uint32_t len; + + for (i = 0; i < QCEDEV_MAX_BUFFERS; i++) { + err |= get_user(vaddr, (compat_uptr_t *)&data->data[i].vaddr); + err |= put_user(vaddr, &data32->data[i].vaddr); + err |= get_user(len, &data->data[i].len); + err |= put_user(len, &data32->data[i].len); + } + + err |= get_user(entries, &data->entries); + err |= put_user(entries, &data32->entries); + err |= get_user(data_len, &data->data_len); + err |= put_user(data_len, &data32->data_len); + + for (i = 0; i < QCEDEV_MAX_SHA_DIGEST; i++) { + err |= get_user(digest, &(data->digest[i])); + err |= put_user(digest, &(data32->digest[i])); + } + + err |= get_user(diglen, &data->diglen); + err |= put_user(diglen, &data32->diglen); + err |= get_user(authkey, (compat_uptr_t *)&data->authkey); + err |= put_user(authkey, &data32->authkey); + err |= get_user(authklen, &data->authklen); + err |= put_user(authklen, &data32->authklen); + err |= get_user(alg, &data->alg); + err |= put_user(alg, &data32->alg); + + return err; +} + +static unsigned int convert_cmd(unsigned int cmd) +{ + switch (cmd) { + case COMPAT_QCEDEV_IOCTL_ENC_REQ: + return QCEDEV_IOCTL_ENC_REQ; + case COMPAT_QCEDEV_IOCTL_DEC_REQ: + return QCEDEV_IOCTL_DEC_REQ; + case COMPAT_QCEDEV_IOCTL_SHA_INIT_REQ: + return QCEDEV_IOCTL_SHA_INIT_REQ; + case COMPAT_QCEDEV_IOCTL_SHA_UPDATE_REQ: + return QCEDEV_IOCTL_SHA_UPDATE_REQ; + case COMPAT_QCEDEV_IOCTL_SHA_FINAL_REQ: + return QCEDEV_IOCTL_SHA_FINAL_REQ; + case COMPAT_QCEDEV_IOCTL_GET_SHA_REQ: + return QCEDEV_IOCTL_GET_SHA_REQ; + case COMPAT_QCEDEV_IOCTL_GET_CMAC_REQ: + return QCEDEV_IOCTL_GET_CMAC_REQ; + default: + return cmd; + } + +} + +long compat_qcedev_ioctl(struct file *file, + unsigned int cmd, unsigned long arg) +{ + long ret; + + switch (cmd) { + case COMPAT_QCEDEV_IOCTL_ENC_REQ: + case COMPAT_QCEDEV_IOCTL_DEC_REQ: { + struct compat_qcedev_cipher_op_req __user *data32; + struct qcedev_cipher_op_req __user *data; + int err; + + data32 = compat_ptr(arg); + data = compat_alloc_user_space(sizeof(*data)); + if (!data) + return -EFAULT; + + err = compat_get_qcedev_cipher_op_req(data32, data); + if (err) + return err; + + ret = qcedev_ioctl(file, convert_cmd(cmd), (unsigned long)data); + err = compat_put_qcedev_cipher_op_req(data32, data); + return ret ? ret : err; + } + case COMPAT_QCEDEV_IOCTL_SHA_INIT_REQ: + case COMPAT_QCEDEV_IOCTL_SHA_UPDATE_REQ: + case COMPAT_QCEDEV_IOCTL_SHA_FINAL_REQ: + case COMPAT_QCEDEV_IOCTL_GET_CMAC_REQ: + case COMPAT_QCEDEV_IOCTL_GET_SHA_REQ: { + struct compat_qcedev_sha_op_req __user *data32; + struct qcedev_sha_op_req __user *data; + int err; + + data32 = compat_ptr(arg); + data = compat_alloc_user_space(sizeof(*data)); + if (!data) + return -EFAULT; + + err = compat_get_qcedev_sha_op_req(data32, data); + if (err) + return err; + + ret = qcedev_ioctl(file, convert_cmd(cmd), (unsigned long)data); + err = compat_put_qcedev_sha_op_req(data32, data); + return ret ? ret : err; + } + default: + return -ENOIOCTLCMD; + } + return 0; +} +EXPORT_SYMBOL(compat_qcedev_ioctl); + +MODULE_LICENSE("GPL v2"); +MODULE_DESCRIPTION("QTI 32-64 Compatibility for Crypto driver"); diff -Nruw linux-4.4.115-fbx/drivers/crypto/msm./compat_qcedev.h linux-4.4.115-fbx/drivers/crypto/msm/compat_qcedev.h --- linux-4.4.115-fbx/drivers/crypto/msm./compat_qcedev.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-4.4.115-fbx/drivers/crypto/msm/compat_qcedev.h 2019-01-22 16:16:23.107242820 +0100 @@ -0,0 +1,165 @@ +#ifndef _UAPI_COMPAT_QCEDEV__H +#define _UAPI_COMPAT_QCEDEV__H + +#include +#include + +#if IS_ENABLED(CONFIG_COMPAT) +#include + +/** +* struct compat_buf_info - Buffer information +* @offset: Offset from the base address of the buffer +* (Used when buffer is allocated using PMEM) +* @vaddr: Virtual buffer address pointer +* @len: Size of the buffer +*/ +struct compat_buf_info { + union { + compat_ulong_t offset; + compat_uptr_t vaddr; + }; + compat_ulong_t len; +}; + +/** +* struct compat_qcedev_vbuf_info - Source and destination Buffer information +* @src: Array of buf_info for input/source +* @dst: Array of buf_info for output/destination +*/ +struct compat_qcedev_vbuf_info { + struct compat_buf_info src[QCEDEV_MAX_BUFFERS]; + struct compat_buf_info dst[QCEDEV_MAX_BUFFERS]; +}; + +/** +* struct compat_qcedev_pmem_info - Stores PMEM buffer information +* @fd_src: Handle to /dev/adsp_pmem used to allocate +* memory for input/src buffer +* @src: Array of buf_info for input/source +* @fd_dst: Handle to /dev/adsp_pmem used to allocate +* memory for output/dst buffer +* @dst: Array of buf_info for output/destination +* @pmem_src_offset: The offset from input/src buffer +* (allocated by PMEM) +*/ +struct compat_qcedev_pmem_info { + compat_int_t fd_src; + struct compat_buf_info src[QCEDEV_MAX_BUFFERS]; + compat_int_t fd_dst; + struct compat_buf_info dst[QCEDEV_MAX_BUFFERS]; +}; + +/** +* struct compat_qcedev_cipher_op_req - Holds the ciphering request information +* @use_pmem (IN): Flag to indicate if buffer source is PMEM +* QCEDEV_USE_PMEM/QCEDEV_NO_PMEM +* @pmem (IN): Stores PMEM buffer information. +* Refer struct qcedev_pmem_info +* @vbuf (IN/OUT): Stores Source and destination Buffer information +* Refer to struct qcedev_vbuf_info +* @data_len (IN): Total Length of input/src and output/dst in bytes +* @in_place_op (IN): Indicates whether the operation is inplace where +* source == destination +* When using PMEM allocated memory, must set this to 1 +* @enckey (IN): 128 bits of confidentiality key +* enckey[0] bit 127-120, enckey[1] bit 119-112,.. +* enckey[15] bit 7-0 +* @encklen (IN): Length of the encryption key(set to 128 bits/16 +* bytes in the driver) +* @iv (IN/OUT): Initialisation vector data +* This is updated by the driver, incremented by +* number of blocks encrypted/decrypted. +* @ivlen (IN): Length of the IV +* @byteoffset (IN): Offset in the Cipher BLOCK (applicable and to be set +* for AES-128 CTR mode only) +* @alg (IN): Type of ciphering algorithm: AES/DES/3DES +* @mode (IN): Mode use when using AES algorithm: ECB/CBC/CTR +* Apllicabel when using AES algorithm only +* @op (IN): Type of operation: QCEDEV_OPER_DEC/QCEDEV_OPER_ENC or +* QCEDEV_OPER_ENC_NO_KEY/QCEDEV_OPER_DEC_NO_KEY +* +*If use_pmem is set to 0, the driver assumes that memory was not allocated +* via PMEM, and kernel will need to allocate memory and copy data from user +* space buffer (data_src/dta_dst) and process accordingly and copy data back +* to the user space buffer +* +* If use_pmem is set to 1, the driver assumes that memory was allocated via +* PMEM. +* The kernel driver will use the fd_src to determine the kernel virtual address +* base that maps to the user space virtual address base for the buffer +* allocated in user space. +* The final input/src and output/dst buffer pointer will be determined +* by adding the offsets to the kernel virtual addr. +* +* If use of hardware key is supported in the target, user can configure the +* key paramters (encklen, enckey) to use the hardware key. +* In order to use the hardware key, set encklen to 0 and set the enckey +* data array to 0. +*/ +struct compat_qcedev_cipher_op_req { + uint8_t use_pmem; + union { + struct compat_qcedev_pmem_info pmem; + struct compat_qcedev_vbuf_info vbuf; + }; + compat_ulong_t entries; + compat_ulong_t data_len; + uint8_t in_place_op; + uint8_t enckey[QCEDEV_MAX_KEY_SIZE]; + compat_ulong_t encklen; + uint8_t iv[QCEDEV_MAX_IV_SIZE]; + compat_ulong_t ivlen; + compat_ulong_t byteoffset; + enum qcedev_cipher_alg_enum alg; + enum qcedev_cipher_mode_enum mode; + enum qcedev_oper_enum op; +}; + +/** +* struct qcedev_sha_op_req - Holds the hashing request information +* @data (IN): Array of pointers to the data to be hashed +* @entries (IN): Number of buf_info entries in the data array +* @data_len (IN): Length of data to be hashed +* @digest (IN/OUT): Returns the hashed data information +* @diglen (OUT): Size of the hashed/digest data +* @authkey (IN): Pointer to authentication key for HMAC +* @authklen (IN): Size of the authentication key +* @alg (IN): Secure Hash algorithm +*/ +struct compat_qcedev_sha_op_req { + struct compat_buf_info data[QCEDEV_MAX_BUFFERS]; + compat_ulong_t entries; + compat_ulong_t data_len; + uint8_t digest[QCEDEV_MAX_SHA_DIGEST]; + compat_ulong_t diglen; + compat_uptr_t authkey; + compat_ulong_t authklen; + enum qcedev_sha_alg_enum alg; +}; + +struct file; +extern long compat_qcedev_ioctl(struct file *file, + unsigned int cmd, unsigned long arg); + +#define COMPAT_QCEDEV_IOCTL_ENC_REQ \ + _IOWR(QCEDEV_IOC_MAGIC, 1, struct compat_qcedev_cipher_op_req) +#define COMPAT_QCEDEV_IOCTL_DEC_REQ \ + _IOWR(QCEDEV_IOC_MAGIC, 2, struct compat_qcedev_cipher_op_req) +#define COMPAT_QCEDEV_IOCTL_SHA_INIT_REQ \ + _IOWR(QCEDEV_IOC_MAGIC, 3, struct compat_qcedev_sha_op_req) +#define COMPAT_QCEDEV_IOCTL_SHA_UPDATE_REQ \ + _IOWR(QCEDEV_IOC_MAGIC, 4, struct compat_qcedev_sha_op_req) +#define COMPAT_QCEDEV_IOCTL_SHA_FINAL_REQ \ + _IOWR(QCEDEV_IOC_MAGIC, 5, struct compat_qcedev_sha_op_req) +#define COMPAT_QCEDEV_IOCTL_GET_SHA_REQ \ + _IOWR(QCEDEV_IOC_MAGIC, 6, struct compat_qcedev_sha_op_req) +#define COMPAT_QCEDEV_IOCTL_LOCK_CE \ + _IO(QCEDEV_IOC_MAGIC, 7) +#define COMPAT_QCEDEV_IOCTL_UNLOCK_CE \ + _IO(QCEDEV_IOC_MAGIC, 8) +#define COMPAT_QCEDEV_IOCTL_GET_CMAC_REQ \ + _IOWR(QCEDEV_IOC_MAGIC, 9, struct compat_qcedev_sha_op_req) + +#endif /* CONFIG_COMPAT */ +#endif /* _UAPI_COMPAT_QCEDEV__H */ diff -Nruw linux-4.4.115-fbx/drivers/crypto/msm./Kconfig linux-4.4.115-fbx/drivers/crypto/msm/Kconfig --- linux-4.4.115-fbx/drivers/crypto/msm./Kconfig 1970-01-01 01:00:00.000000000 +0100 +++ linux-4.4.115-fbx/drivers/crypto/msm/Kconfig 2019-01-22 16:16:23.107242820 +0100 @@ -0,0 +1,10 @@ + +config CRYPTO_DEV_QCOM_ICE + tristate "Inline Crypto Module" + default n + depends on PFK && BLK_DEV_DM + help + This driver supports Inline Crypto Engine for QTI chipsets, MSM8994 + and later, to accelerate crypto operations for storage needs. + To compile this driver as a module, choose M here: the + module will be called ice. diff -Nruw linux-4.4.115-fbx/drivers/crypto/msm./Makefile linux-4.4.115-fbx/drivers/crypto/msm/Makefile --- linux-4.4.115-fbx/drivers/crypto/msm./Makefile 1970-01-01 01:00:00.000000000 +0100 +++ linux-4.4.115-fbx/drivers/crypto/msm/Makefile 2019-01-22 16:16:23.107242820 +0100 @@ -0,0 +1,12 @@ +obj-$(CONFIG_CRYPTO_DEV_QCEDEV) += qcedev.o +ifeq ($(CONFIG_CRYPTO_DEV_QCE50), y) + obj-$(CONFIG_CRYPTO_DEV_QCOM_MSM_QCE) += qce50.o +else + obj-$(CONFIG_CRYPTO_DEV_QCOM_MSM_QCE) += qce.o +endif +ifdef CONFIG_COMPAT +obj-$(CONFIG_CRYPTO_DEV_QCOM_MSM_QCE) += compat_qcedev.o +endif +obj-$(CONFIG_CRYPTO_DEV_QCRYPTO) += qcrypto.o +obj-$(CONFIG_CRYPTO_DEV_OTA_CRYPTO) += ota_crypto.o +obj-$(CONFIG_CRYPTO_DEV_QCOM_ICE) += ice.o diff -Nruw linux-4.4.115-fbx/drivers/crypto/msm./ota_crypto.c linux-4.4.115-fbx/drivers/crypto/msm/ota_crypto.c --- linux-4.4.115-fbx/drivers/crypto/msm./ota_crypto.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-4.4.115-fbx/drivers/crypto/msm/ota_crypto.c 2019-01-22 16:16:23.111242857 +0100 @@ -0,0 +1,980 @@ +/* Copyright (c) 2010-2014,2017 The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +/* Qualcomm Over the Air (OTA) Crypto driver */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + + +#include +#include "qce.h" +#include "qce_ota.h" + +enum qce_ota_oper_enum { + QCE_OTA_F8_OPER = 0, + QCE_OTA_MPKT_F8_OPER = 1, + QCE_OTA_F9_OPER = 2, + QCE_OTA_VAR_MPKT_F8_OPER = 3, + QCE_OTA_OPER_LAST +}; + +struct ota_dev_control; + +struct ota_async_req { + struct list_head rlist; + struct completion complete; + int err; + enum qce_ota_oper_enum op; + union { + struct qce_f9_req f9_req; + struct qce_f8_req f8_req; + struct qce_f8_multi_pkt_req f8_mp_req; + struct qce_f8_varible_multi_pkt_req f8_v_mp_req; + } req; + unsigned int steps; + struct ota_qce_dev *pqce; +}; + +/* + * Register ourselves as a misc device to be able to access the ota + * from userspace. + */ + + +#define QCOTA_DEV "qcota" + + +struct ota_dev_control { + + /* misc device */ + struct miscdevice miscdevice; + struct list_head ready_commands; + unsigned magic; + struct list_head qce_dev; + spinlock_t lock; + struct mutex register_lock; + bool registered; + uint32_t total_units; +}; + +struct ota_qce_dev { + struct list_head qlist; + /* qce handle */ + void *qce; + + /* platform device */ + struct platform_device *pdev; + + struct ota_async_req *active_command; + struct tasklet_struct done_tasklet; + struct ota_dev_control *podev; + uint32_t unit; + u64 total_req; + u64 err_req; +}; + +#define OTA_MAGIC 0x4f544143 + +static long qcota_ioctl(struct file *file, + unsigned cmd, unsigned long arg); +static int qcota_open(struct inode *inode, struct file *file); +static int qcota_release(struct inode *inode, struct file *file); +static int start_req(struct ota_qce_dev *pqce, struct ota_async_req *areq); +static void f8_cb(void *cookie, unsigned char *icv, unsigned char *iv, int ret); + +static const struct file_operations qcota_fops = { + .owner = THIS_MODULE, + .unlocked_ioctl = qcota_ioctl, + .open = qcota_open, + .release = qcota_release, +}; + +static struct ota_dev_control qcota_dev = { + .miscdevice = { + .minor = MISC_DYNAMIC_MINOR, + .name = "qcota0", + .fops = &qcota_fops, + }, + .magic = OTA_MAGIC, +}; + +#define DEBUG_MAX_FNAME 16 +#define DEBUG_MAX_RW_BUF 1024 + +struct qcota_stat { + u64 f8_req; + u64 f8_mp_req; + u64 f8_v_mp_req; + u64 f9_req; + u64 f8_op_success; + u64 f8_op_fail; + u64 f8_mp_op_success; + u64 f8_mp_op_fail; + u64 f8_v_mp_op_success; + u64 f8_v_mp_op_fail; + u64 f9_op_success; + u64 f9_op_fail; +}; +static struct qcota_stat _qcota_stat; +static struct dentry *_debug_dent; +static char _debug_read_buf[DEBUG_MAX_RW_BUF]; +static int _debug_qcota; + +static struct ota_dev_control *qcota_control(void) +{ + + return &qcota_dev; +} + +static int qcota_open(struct inode *inode, struct file *file) +{ + struct ota_dev_control *podev; + + podev = qcota_control(); + if (podev == NULL) { + pr_err("%s: no such device %d\n", __func__, + MINOR(inode->i_rdev)); + return -ENOENT; + } + + file->private_data = podev; + + return 0; +} + +static int qcota_release(struct inode *inode, struct file *file) +{ + struct ota_dev_control *podev; + + podev = file->private_data; + + if (podev != NULL && podev->magic != OTA_MAGIC) { + pr_err("%s: invalid handle %pK\n", + __func__, podev); + } + + file->private_data = NULL; + + return 0; +} + +static bool _next_v_mp_req(struct ota_async_req *areq) +{ + unsigned char *p; + + if (areq->err) + return false; + if (++areq->steps >= areq->req.f8_v_mp_req.num_pkt) + return false; + + p = areq->req.f8_v_mp_req.qce_f8_req.data_in; + p += areq->req.f8_v_mp_req.qce_f8_req.data_len; + p = (uint8_t *) ALIGN(((uintptr_t)p), L1_CACHE_BYTES); + + areq->req.f8_v_mp_req.qce_f8_req.data_out = p; + areq->req.f8_v_mp_req.qce_f8_req.data_in = p; + areq->req.f8_v_mp_req.qce_f8_req.data_len = + areq->req.f8_v_mp_req.cipher_iov[areq->steps].size; + + areq->req.f8_v_mp_req.qce_f8_req.count_c++; + return true; +} + +static void req_done(unsigned long data) +{ + struct ota_qce_dev *pqce = (struct ota_qce_dev *)data; + struct ota_dev_control *podev = pqce->podev; + struct ota_async_req *areq; + unsigned long flags; + struct ota_async_req *new_req = NULL; + int ret = 0; + bool schedule = true; + + spin_lock_irqsave(&podev->lock, flags); + areq = pqce->active_command; + if (unlikely(areq == NULL)) + pr_err("ota_crypto: req_done, no active request\n"); + else if (areq->op == QCE_OTA_VAR_MPKT_F8_OPER) { + if (_next_v_mp_req(areq)) { + /* execute next subcommand */ + spin_unlock_irqrestore(&podev->lock, flags); + ret = start_req(pqce, areq); + if (unlikely(ret)) { + areq->err = ret; + schedule = true; + spin_lock_irqsave(&podev->lock, flags); + } else { + areq = NULL; + schedule = false; + } + } else { + /* done with this variable mp req */ + schedule = true; + } + } + while (schedule) { + if (!list_empty(&podev->ready_commands)) { + new_req = container_of(podev->ready_commands.next, + struct ota_async_req, rlist); + if (!new_req) + break; + + list_del(&new_req->rlist); + pqce->active_command = new_req; + spin_unlock_irqrestore(&podev->lock, flags); + + new_req->err = 0; + /* start a new request */ + ret = start_req(pqce, new_req); + if (unlikely(new_req && ret)) { + new_req->err = ret; + complete(&new_req->complete); + ret = 0; + new_req = NULL; + spin_lock_irqsave(&podev->lock, flags); + } else { + schedule = false; + } + } else { + pqce->active_command = NULL; + spin_unlock_irqrestore(&podev->lock, flags); + schedule = false; + }; + } + if (areq) + complete(&areq->complete); + return; +} + +static void f9_cb(void *cookie, unsigned char *icv, unsigned char *iv, + int ret) +{ + struct ota_async_req *areq = (struct ota_async_req *) cookie; + struct ota_qce_dev *pqce; + + pqce = areq->pqce; + areq->req.f9_req.mac_i = *((uint32_t *)icv); + + if (ret) { + pqce->err_req++; + areq->err = -ENXIO; + } else + areq->err = 0; + + tasklet_schedule(&pqce->done_tasklet); +} + +static void f8_cb(void *cookie, unsigned char *icv, unsigned char *iv, + int ret) +{ + struct ota_async_req *areq = (struct ota_async_req *) cookie; + struct ota_qce_dev *pqce; + + pqce = areq->pqce; + + if (ret) { + pqce->err_req++; + areq->err = -ENXIO; + } else { + areq->err = 0; + } + + tasklet_schedule(&pqce->done_tasklet); +} + +static int start_req(struct ota_qce_dev *pqce, struct ota_async_req *areq) +{ + struct qce_f9_req *pf9; + struct qce_f8_multi_pkt_req *p_mp_f8; + struct qce_f8_req *pf8; + int ret = 0; + + /* command should be on the podev->active_command */ + areq->pqce = pqce; + + switch (areq->op) { + case QCE_OTA_F8_OPER: + pf8 = &areq->req.f8_req; + ret = qce_f8_req(pqce->qce, pf8, areq, f8_cb); + break; + case QCE_OTA_MPKT_F8_OPER: + p_mp_f8 = &areq->req.f8_mp_req; + ret = qce_f8_multi_pkt_req(pqce->qce, p_mp_f8, areq, f8_cb); + break; + + case QCE_OTA_F9_OPER: + pf9 = &areq->req.f9_req; + ret = qce_f9_req(pqce->qce, pf9, areq, f9_cb); + break; + + case QCE_OTA_VAR_MPKT_F8_OPER: + pf8 = &areq->req.f8_v_mp_req.qce_f8_req; + ret = qce_f8_req(pqce->qce, pf8, areq, f8_cb); + break; + + default: + ret = -ENOTSUPP; + break; + }; + areq->err = ret; + pqce->total_req++; + if (ret) + pqce->err_req++; + return ret; +} + +static struct ota_qce_dev *schedule_qce(struct ota_dev_control *podev) +{ + /* do this function with spinlock set */ + struct ota_qce_dev *p; + + if (unlikely(list_empty(&podev->qce_dev))) { + pr_err("%s: no valid qce to schedule\n", __func__); + return NULL; + } + + list_for_each_entry(p, &podev->qce_dev, qlist) { + if (p->active_command == NULL) + return p; + } + return NULL; +} + +static int submit_req(struct ota_async_req *areq, struct ota_dev_control *podev) +{ + unsigned long flags; + int ret = 0; + struct qcota_stat *pstat; + struct ota_qce_dev *pqce; + + areq->err = 0; + + spin_lock_irqsave(&podev->lock, flags); + pqce = schedule_qce(podev); + if (pqce) { + pqce->active_command = areq; + spin_unlock_irqrestore(&podev->lock, flags); + + ret = start_req(pqce, areq); + if (ret != 0) { + spin_lock_irqsave(&podev->lock, flags); + pqce->active_command = NULL; + spin_unlock_irqrestore(&podev->lock, flags); + } + + } else { + list_add_tail(&areq->rlist, &podev->ready_commands); + spin_unlock_irqrestore(&podev->lock, flags); + } + + if (ret == 0) + wait_for_completion(&areq->complete); + + pstat = &_qcota_stat; + switch (areq->op) { + case QCE_OTA_F8_OPER: + if (areq->err) + pstat->f8_op_fail++; + else + pstat->f8_op_success++; + break; + + case QCE_OTA_MPKT_F8_OPER: + + if (areq->err) + pstat->f8_mp_op_fail++; + else + pstat->f8_mp_op_success++; + break; + + case QCE_OTA_F9_OPER: + if (areq->err) + pstat->f9_op_fail++; + else + pstat->f9_op_success++; + break; + case QCE_OTA_VAR_MPKT_F8_OPER: + default: + if (areq->err) + pstat->f8_v_mp_op_fail++; + else + pstat->f8_v_mp_op_success++; + break; + }; + + return areq->err; +} + +static long qcota_ioctl(struct file *file, + unsigned cmd, unsigned long arg) +{ + int err = 0; + struct ota_dev_control *podev; + uint8_t *user_src; + uint8_t *user_dst; + uint8_t *k_buf = NULL; + struct ota_async_req areq; + uint32_t total, temp; + struct qcota_stat *pstat; + int i; + uint8_t *p = NULL; + + podev = file->private_data; + if (podev == NULL || podev->magic != OTA_MAGIC) { + pr_err("%s: invalid handle %pK\n", + __func__, podev); + return -ENOENT; + } + + /* Verify user arguments. */ + if (_IOC_TYPE(cmd) != QCOTA_IOC_MAGIC) + return -ENOTTY; + + init_completion(&areq.complete); + + pstat = &_qcota_stat; + + switch (cmd) { + case QCOTA_F9_REQ: + if (!access_ok(VERIFY_WRITE, (void __user *)arg, + sizeof(struct qce_f9_req))) + return -EFAULT; + if (__copy_from_user(&areq.req.f9_req, (void __user *)arg, + sizeof(struct qce_f9_req))) + return -EFAULT; + + user_src = areq.req.f9_req.message; + if (!access_ok(VERIFY_READ, (void __user *)user_src, + areq.req.f9_req.msize)) + return -EFAULT; + + if (areq.req.f9_req.msize == 0) + return 0; + k_buf = kmalloc(areq.req.f9_req.msize, GFP_KERNEL); + if (k_buf == NULL) + return -ENOMEM; + + if (__copy_from_user(k_buf, (void __user *)user_src, + areq.req.f9_req.msize)) { + kfree(k_buf); + return -EFAULT; + } + + areq.req.f9_req.message = k_buf; + areq.op = QCE_OTA_F9_OPER; + + pstat->f9_req++; + err = submit_req(&areq, podev); + + areq.req.f9_req.message = user_src; + if (err == 0 && __copy_to_user((void __user *)arg, + &areq.req.f9_req, sizeof(struct qce_f9_req))) { + err = -EFAULT; + } + kfree(k_buf); + break; + + case QCOTA_F8_REQ: + if (!access_ok(VERIFY_WRITE, (void __user *)arg, + sizeof(struct qce_f8_req))) + return -EFAULT; + if (__copy_from_user(&areq.req.f8_req, (void __user *)arg, + sizeof(struct qce_f8_req))) + return -EFAULT; + total = areq.req.f8_req.data_len; + user_src = areq.req.f8_req.data_in; + if (user_src != NULL) { + if (!access_ok(VERIFY_READ, (void __user *) + user_src, total)) + return -EFAULT; + + }; + + user_dst = areq.req.f8_req.data_out; + if (!access_ok(VERIFY_WRITE, (void __user *) + user_dst, total)) + return -EFAULT; + + if (!total) + return 0; + k_buf = kmalloc(total, GFP_KERNEL); + if (k_buf == NULL) + return -ENOMEM; + + /* k_buf returned from kmalloc should be cache line aligned */ + if (user_src && __copy_from_user(k_buf, + (void __user *)user_src, total)) { + kfree(k_buf); + return -EFAULT; + } + + if (user_src) + areq.req.f8_req.data_in = k_buf; + else + areq.req.f8_req.data_in = NULL; + areq.req.f8_req.data_out = k_buf; + + areq.op = QCE_OTA_F8_OPER; + + pstat->f8_req++; + err = submit_req(&areq, podev); + + if (err == 0 && __copy_to_user(user_dst, k_buf, total)) + err = -EFAULT; + kfree(k_buf); + + break; + + case QCOTA_F8_MPKT_REQ: + if (!access_ok(VERIFY_WRITE, (void __user *)arg, + sizeof(struct qce_f8_multi_pkt_req))) + return -EFAULT; + if (__copy_from_user(&areq.req.f8_mp_req, (void __user *)arg, + sizeof(struct qce_f8_multi_pkt_req))) + return -EFAULT; + temp = areq.req.f8_mp_req.qce_f8_req.data_len; + if (temp < (uint32_t) areq.req.f8_mp_req.cipher_start + + areq.req.f8_mp_req.cipher_size) + return -EINVAL; + total = (uint32_t) areq.req.f8_mp_req.num_pkt * + areq.req.f8_mp_req.qce_f8_req.data_len; + + user_src = areq.req.f8_mp_req.qce_f8_req.data_in; + if (!access_ok(VERIFY_READ, (void __user *) + user_src, total)) + return -EFAULT; + + user_dst = areq.req.f8_mp_req.qce_f8_req.data_out; + if (!access_ok(VERIFY_WRITE, (void __user *) + user_dst, total)) + return -EFAULT; + + if (!total) + return 0; + k_buf = kmalloc(total, GFP_KERNEL); + if (k_buf == NULL) + return -ENOMEM; + /* k_buf returned from kmalloc should be cache line aligned */ + if (__copy_from_user(k_buf, (void __user *)user_src, total)) { + kfree(k_buf); + + return -EFAULT; + } + + areq.req.f8_mp_req.qce_f8_req.data_out = k_buf; + areq.req.f8_mp_req.qce_f8_req.data_in = k_buf; + + areq.op = QCE_OTA_MPKT_F8_OPER; + + pstat->f8_mp_req++; + err = submit_req(&areq, podev); + + if (err == 0 && __copy_to_user(user_dst, k_buf, total)) + err = -EFAULT; + kfree(k_buf); + break; + + case QCOTA_F8_V_MPKT_REQ: + if (!access_ok(VERIFY_WRITE, (void __user *)arg, + sizeof(struct qce_f8_varible_multi_pkt_req))) + return -EFAULT; + if (__copy_from_user(&areq.req.f8_v_mp_req, (void __user *)arg, + sizeof(struct qce_f8_varible_multi_pkt_req))) + return -EFAULT; + + if (areq.req.f8_v_mp_req.num_pkt > MAX_NUM_V_MULTI_PKT) + return -EINVAL; + + for (i = 0, total = 0; i < areq.req.f8_v_mp_req.num_pkt; i++) { + if (!access_ok(VERIFY_WRITE, (void __user *) + areq.req.f8_v_mp_req.cipher_iov[i].addr, + areq.req.f8_v_mp_req.cipher_iov[i].size)) + return -EFAULT; + total += areq.req.f8_v_mp_req.cipher_iov[i].size; + total = ALIGN(total, L1_CACHE_BYTES); + } + + if (!total) + return 0; + k_buf = kmalloc(total, GFP_KERNEL); + if (k_buf == NULL) + return -ENOMEM; + + for (i = 0, p = k_buf; i < areq.req.f8_v_mp_req.num_pkt; i++) { + user_src = areq.req.f8_v_mp_req.cipher_iov[i].addr; + if (__copy_from_user(p, (void __user *)user_src, + areq.req.f8_v_mp_req.cipher_iov[i].size)) { + kfree(k_buf); + return -EFAULT; + } + p += areq.req.f8_v_mp_req.cipher_iov[i].size; + p = (uint8_t *) ALIGN(((uintptr_t)p), + L1_CACHE_BYTES); + } + + areq.req.f8_v_mp_req.qce_f8_req.data_out = k_buf; + areq.req.f8_v_mp_req.qce_f8_req.data_in = k_buf; + areq.req.f8_v_mp_req.qce_f8_req.data_len = + areq.req.f8_v_mp_req.cipher_iov[0].size; + areq.steps = 0; + areq.op = QCE_OTA_VAR_MPKT_F8_OPER; + + pstat->f8_v_mp_req++; + err = submit_req(&areq, podev); + + if (err != 0) { + kfree(k_buf); + return err; + } + + for (i = 0, p = k_buf; i < areq.req.f8_v_mp_req.num_pkt; i++) { + user_dst = areq.req.f8_v_mp_req.cipher_iov[i].addr; + if (__copy_to_user(user_dst, p, + areq.req.f8_v_mp_req.cipher_iov[i].size)) { + kfree(k_buf); + return -EFAULT; + } + p += areq.req.f8_v_mp_req.cipher_iov[i].size; + p = (uint8_t *) ALIGN(((uintptr_t)p), + L1_CACHE_BYTES); + } + kfree(k_buf); + break; + default: + return -ENOTTY; + } + + return err; +} + +static int qcota_probe(struct platform_device *pdev) +{ + void *handle = NULL; + int rc = 0; + struct ota_dev_control *podev; + struct ce_hw_support ce_support; + struct ota_qce_dev *pqce; + unsigned long flags; + + podev = &qcota_dev; + pqce = kzalloc(sizeof(*pqce), GFP_KERNEL); + if (!pqce) { + pr_err("qcota_probe: Memory allocation FAIL\n"); + return -ENOMEM; + } + + pqce->podev = podev; + pqce->active_command = NULL; + tasklet_init(&pqce->done_tasklet, req_done, (unsigned long)pqce); + + /* open qce */ + handle = qce_open(pdev, &rc); + if (handle == NULL) { + pr_err("%s: device %s, can not open qce\n", + __func__, pdev->name); + goto err; + } + if (qce_hw_support(handle, &ce_support) < 0 || + ce_support.ota == false) { + pr_err("%s: device %s, qce does not support ota capability\n", + __func__, pdev->name); + rc = -ENODEV; + goto err; + } + pqce->qce = handle; + pqce->pdev = pdev; + pqce->total_req = 0; + pqce->err_req = 0; + platform_set_drvdata(pdev, pqce); + + mutex_lock(&podev->register_lock); + rc = 0; + if (podev->registered == false) { + rc = misc_register(&podev->miscdevice); + if (rc == 0) { + pqce->unit = podev->total_units; + podev->total_units++; + podev->registered = true; + }; + } else { + pqce->unit = podev->total_units; + podev->total_units++; + } + mutex_unlock(&podev->register_lock); + if (rc) { + pr_err("ion: failed to register misc device.\n"); + goto err; + } + + spin_lock_irqsave(&podev->lock, flags); + list_add_tail(&pqce->qlist, &podev->qce_dev); + spin_unlock_irqrestore(&podev->lock, flags); + + return 0; +err: + if (handle) + qce_close(handle); + + platform_set_drvdata(pdev, NULL); + tasklet_kill(&pqce->done_tasklet); + kfree(pqce); + return rc; +} + +static int qcota_remove(struct platform_device *pdev) +{ + struct ota_dev_control *podev; + struct ota_qce_dev *pqce; + unsigned long flags; + + pqce = platform_get_drvdata(pdev); + if (!pqce) + return 0; + if (pqce->qce) + qce_close(pqce->qce); + + podev = pqce->podev; + if (!podev) + goto ret; + + spin_lock_irqsave(&podev->lock, flags); + list_del(&pqce->qlist); + spin_unlock_irqrestore(&podev->lock, flags); + + mutex_lock(&podev->register_lock); + if (--podev->total_units == 0) { + if (podev->miscdevice.minor != MISC_DYNAMIC_MINOR) + misc_deregister(&podev->miscdevice); + podev->registered = false; + } + mutex_unlock(&podev->register_lock); +ret: + + tasklet_kill(&pqce->done_tasklet); + kfree(pqce); + return 0; +} + +static struct of_device_id qcota_match[] = { + { .compatible = "qcom,qcota", + }, + {} +}; + +static struct platform_driver qcota_plat_driver = { + .probe = qcota_probe, + .remove = qcota_remove, + .driver = { + .name = "qcota", + .owner = THIS_MODULE, + .of_match_table = qcota_match, + }, +}; + +static int _disp_stats(void) +{ + struct qcota_stat *pstat; + int len = 0; + struct ota_dev_control *podev = &qcota_dev; + unsigned long flags; + struct ota_qce_dev *p; + + pstat = &_qcota_stat; + len = scnprintf(_debug_read_buf, DEBUG_MAX_RW_BUF - 1, + "\nQualcomm OTA crypto accelerator Statistics:\n"); + + len += scnprintf(_debug_read_buf + len, DEBUG_MAX_RW_BUF - len - 1, + " F8 request : %llu\n", + pstat->f8_req); + len += scnprintf(_debug_read_buf + len, DEBUG_MAX_RW_BUF - len - 1, + " F8 operation success : %llu\n", + pstat->f8_op_success); + len += scnprintf(_debug_read_buf + len, DEBUG_MAX_RW_BUF - len - 1, + " F8 operation fail : %llu\n", + pstat->f8_op_fail); + + len += scnprintf(_debug_read_buf + len, DEBUG_MAX_RW_BUF - len - 1, + " F8 MP request : %llu\n", + pstat->f8_mp_req); + len += scnprintf(_debug_read_buf + len, DEBUG_MAX_RW_BUF - len - 1, + " F8 MP operation success : %llu\n", + pstat->f8_mp_op_success); + len += scnprintf(_debug_read_buf + len, DEBUG_MAX_RW_BUF - len - 1, + " F8 MP operation fail : %llu\n", + pstat->f8_mp_op_fail); + + len += scnprintf(_debug_read_buf + len, DEBUG_MAX_RW_BUF - len - 1, + " F8 Variable MP request : %llu\n", + pstat->f8_v_mp_req); + len += scnprintf(_debug_read_buf + len, DEBUG_MAX_RW_BUF - len - 1, + " F8 Variable MP operation success: %llu\n", + pstat->f8_v_mp_op_success); + len += scnprintf(_debug_read_buf + len, DEBUG_MAX_RW_BUF - len - 1, + " F8 Variable MP operation fail : %llu\n", + pstat->f8_v_mp_op_fail); + + len += scnprintf(_debug_read_buf + len, DEBUG_MAX_RW_BUF - len - 1, + " F9 request : %llu\n", + pstat->f9_req); + len += scnprintf(_debug_read_buf + len, DEBUG_MAX_RW_BUF - len - 1, + " F9 operation success : %llu\n", + pstat->f9_op_success); + len += scnprintf(_debug_read_buf + len, DEBUG_MAX_RW_BUF - len - 1, + " F9 operation fail : %llu\n", + pstat->f9_op_fail); + + spin_lock_irqsave(&podev->lock, flags); + + list_for_each_entry(p, &podev->qce_dev, qlist) { + len += scnprintf( + _debug_read_buf + len, + DEBUG_MAX_RW_BUF - len - 1, + " Engine %4d Req : %llu\n", + p->unit, + p->total_req + ); + len += scnprintf( + _debug_read_buf + len, + DEBUG_MAX_RW_BUF - len - 1, + " Engine %4d Req Error : %llu\n", + p->unit, + p->err_req + ); + } + + spin_unlock_irqrestore(&podev->lock, flags); + + return len; +} + +static int _debug_stats_open(struct inode *inode, struct file *file) +{ + file->private_data = inode->i_private; + return 0; +} + +static ssize_t _debug_stats_read(struct file *file, char __user *buf, + size_t count, loff_t *ppos) +{ + int rc = -EINVAL; + int len; + + len = _disp_stats(); + if (len <= count) + rc = simple_read_from_buffer((void __user *) buf, len, + ppos, (void *) _debug_read_buf, len); + + return rc; +} + +static ssize_t _debug_stats_write(struct file *file, const char __user *buf, + size_t count, loff_t *ppos) +{ + struct ota_dev_control *podev = &qcota_dev; + unsigned long flags; + struct ota_qce_dev *p; + + memset((char *)&_qcota_stat, 0, sizeof(struct qcota_stat)); + + spin_lock_irqsave(&podev->lock, flags); + + list_for_each_entry(p, &podev->qce_dev, qlist) { + p->total_req = 0; + p->err_req = 0; + } + + spin_unlock_irqrestore(&podev->lock, flags); + + return count; +} + +static const struct file_operations _debug_stats_ops = { + .open = _debug_stats_open, + .read = _debug_stats_read, + .write = _debug_stats_write, +}; + +static int _qcota_debug_init(void) +{ + int rc; + char name[DEBUG_MAX_FNAME]; + struct dentry *dent; + + _debug_dent = debugfs_create_dir("qcota", NULL); + if (IS_ERR(_debug_dent)) { + pr_err("qcota debugfs_create_dir fail, error %ld\n", + PTR_ERR(_debug_dent)); + return PTR_ERR(_debug_dent); + } + + snprintf(name, DEBUG_MAX_FNAME-1, "stats-0"); + _debug_qcota = 0; + dent = debugfs_create_file(name, 0644, _debug_dent, + &_debug_qcota, &_debug_stats_ops); + if (dent == NULL) { + pr_err("qcota debugfs_create_file fail, error %ld\n", + PTR_ERR(dent)); + rc = PTR_ERR(dent); + goto err; + } + return 0; +err: + debugfs_remove_recursive(_debug_dent); + return rc; +} + +static int __init qcota_init(void) +{ + int rc; + struct ota_dev_control *podev; + + rc = _qcota_debug_init(); + if (rc) + return rc; + + podev = &qcota_dev; + INIT_LIST_HEAD(&podev->ready_commands); + INIT_LIST_HEAD(&podev->qce_dev); + spin_lock_init(&podev->lock); + mutex_init(&podev->register_lock); + podev->registered = false; + podev->total_units = 0; + + return platform_driver_register(&qcota_plat_driver); +} +static void __exit qcota_exit(void) +{ + debugfs_remove_recursive(_debug_dent); + platform_driver_unregister(&qcota_plat_driver); +} + +MODULE_LICENSE("GPL v2"); +MODULE_AUTHOR("Rohit Vaswani "); +MODULE_DESCRIPTION("Qualcomm Ota Crypto driver"); +MODULE_VERSION("1.02"); + +module_init(qcota_init); +module_exit(qcota_exit); diff -Nruw linux-4.4.115-fbx/drivers/crypto/msm./qce50.c linux-4.4.115-fbx/drivers/crypto/msm/qce50.c --- linux-4.4.115-fbx/drivers/crypto/msm./qce50.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-4.4.115-fbx/drivers/crypto/msm/qce50.c 2019-01-22 16:16:23.111242857 +0100 @@ -0,0 +1,6158 @@ +/* Qualcomm Crypto Engine driver. + * + * Copyright (c) 2012-2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#define pr_fmt(fmt) "QCE50: %s: " fmt, __func__ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "qce.h" +#include "qce50.h" +#include "qcryptohw_50.h" +#include "qce_ota.h" + +#define CRYPTO_CONFIG_RESET 0xE01EF +#define MAX_SPS_DESC_FIFO_SIZE 0xfff0 +#define QCE_MAX_NUM_DSCR 0x200 +#define QCE_SECTOR_SIZE 0x200 +#define CE_CLK_100MHZ 100000000 +#define CE_CLK_DIV 1000000 + +#define CRYPTO_CORE_MAJOR_VER_NUM 0x05 +#define CRYPTO_CORE_MINOR_VER_NUM 0x03 +#define CRYPTO_CORE_STEP_VER_NUM 0x1 + +#define CRYPTO_REQ_USER_PAT 0xdead0000 + +static DEFINE_MUTEX(bam_register_lock); +static DEFINE_MUTEX(qce_iomap_mutex); + +struct bam_registration_info { + struct list_head qlist; + unsigned long handle; + uint32_t cnt; + uint32_t bam_mem; + void __iomem *bam_iobase; + bool support_cmd_dscr; +}; +static LIST_HEAD(qce50_bam_list); + +/* Used to determine the mode */ +#define MAX_BUNCH_MODE_REQ 2 +/* Max number of request supported */ +#define MAX_QCE_BAM_REQ 8 +/* Interrupt flag will be set for every SET_INTR_AT_REQ request */ +#define SET_INTR_AT_REQ (MAX_QCE_BAM_REQ / 2) +/* To create extra request space to hold dummy request */ +#define MAX_QCE_BAM_REQ_WITH_DUMMY_REQ (MAX_QCE_BAM_REQ + 1) +/* Allocate the memory for MAX_QCE_BAM_REQ + 1 (for dummy request) */ +#define MAX_QCE_ALLOC_BAM_REQ MAX_QCE_BAM_REQ_WITH_DUMMY_REQ +/* QCE driver modes */ +#define IN_INTERRUPT_MODE 0 +#define IN_BUNCH_MODE 1 +/* Dummy request data length */ +#define DUMMY_REQ_DATA_LEN 64 +/* Delay timer to expire when in bunch mode */ +#define DELAY_IN_JIFFIES 5 +/* Index to point the dummy request */ +#define DUMMY_REQ_INDEX MAX_QCE_BAM_REQ + +#define TOTAL_IOVEC_SPACE_PER_PIPE (QCE_MAX_NUM_DSCR * sizeof(struct sps_iovec)) + +enum qce_owner { + QCE_OWNER_NONE = 0, + QCE_OWNER_CLIENT = 1, + QCE_OWNER_TIMEOUT = 2 +}; + +struct dummy_request { + struct qce_sha_req sreq; + struct scatterlist sg; + struct ahash_request areq; +}; + +/* + * CE HW device structure. + * Each engine has an instance of the structure. + * Each engine can only handle one crypto operation at one time. It is up to + * the sw above to ensure single threading of operation on an engine. + */ +struct qce_device { + struct device *pdev; /* Handle to platform_device structure */ + struct bam_registration_info *pbam; + + unsigned char *coh_vmem; /* Allocated coherent virtual memory */ + dma_addr_t coh_pmem; /* Allocated coherent physical memory */ + int memsize; /* Memory allocated */ + unsigned char *iovec_vmem; /* Allocate iovec virtual memory */ + int iovec_memsize; /* Memory allocated */ + uint32_t bam_mem; /* bam physical address, from DT */ + uint32_t bam_mem_size; /* bam io size, from DT */ + int is_shared; /* CE HW is shared */ + bool support_cmd_dscr; + bool support_hw_key; + bool support_clk_mgmt_sus_res; + bool support_only_core_src_clk; + + void __iomem *iobase; /* Virtual io base of CE HW */ + unsigned int phy_iobase; /* Physical io base of CE HW */ + + struct clk *ce_core_src_clk; /* Handle to CE src clk*/ + struct clk *ce_core_clk; /* Handle to CE clk */ + struct clk *ce_clk; /* Handle to CE clk */ + struct clk *ce_bus_clk; /* Handle to CE AXI clk*/ + bool no_get_around; + bool no_ccm_mac_status_get_around; + unsigned int ce_opp_freq_hz; + bool use_sw_aes_cbc_ecb_ctr_algo; + bool use_sw_aead_algo; + bool use_sw_aes_xts_algo; + bool use_sw_ahash_algo; + bool use_sw_hmac_algo; + bool use_sw_aes_ccm_algo; + uint32_t engines_avail; + struct qce_ce_cfg_reg_setting reg; + struct ce_bam_info ce_bam_info; + struct ce_request_info ce_request_info[MAX_QCE_ALLOC_BAM_REQ]; + unsigned int ce_request_index; + enum qce_owner owner; + atomic_t no_of_queued_req; + struct timer_list timer; + struct dummy_request dummyreq; + unsigned int mode; + unsigned int intr_cadence; + unsigned int dev_no; + struct qce_driver_stats qce_stats; + atomic_t bunch_cmd_seq; + atomic_t last_intr_seq; + bool cadence_flag; + uint8_t *dummyreq_in_buf; +}; + +static void print_notify_debug(struct sps_event_notify *notify); +static void _sps_producer_callback(struct sps_event_notify *notify); +static int qce_dummy_req(struct qce_device *pce_dev); + +static int _qce50_disp_stats; + +/* Standard initialization vector for SHA-1, source: FIPS 180-2 */ +static uint32_t _std_init_vector_sha1[] = { + 0x67452301, 0xEFCDAB89, 0x98BADCFE, 0x10325476, 0xC3D2E1F0 +}; + +/* Standard initialization vector for SHA-256, source: FIPS 180-2 */ +static uint32_t _std_init_vector_sha256[] = { + 0x6A09E667, 0xBB67AE85, 0x3C6EF372, 0xA54FF53A, + 0x510E527F, 0x9B05688C, 0x1F83D9AB, 0x5BE0CD19 +}; + +static void _byte_stream_to_net_words(uint32_t *iv, unsigned char *b, + unsigned int len) +{ + unsigned n; + + n = len / sizeof(uint32_t); + for (; n > 0; n--) { + *iv = ((*b << 24) & 0xff000000) | + (((*(b+1)) << 16) & 0xff0000) | + (((*(b+2)) << 8) & 0xff00) | + (*(b+3) & 0xff); + b += sizeof(uint32_t); + iv++; + } + + n = len % sizeof(uint32_t); + if (n == 3) { + *iv = ((*b << 24) & 0xff000000) | + (((*(b+1)) << 16) & 0xff0000) | + (((*(b+2)) << 8) & 0xff00); + } else if (n == 2) { + *iv = ((*b << 24) & 0xff000000) | + (((*(b+1)) << 16) & 0xff0000); + } else if (n == 1) { + *iv = ((*b << 24) & 0xff000000); + } +} + +static void _byte_stream_swap_to_net_words(uint32_t *iv, unsigned char *b, + unsigned int len) +{ + unsigned i, j; + unsigned char swap_iv[AES_IV_LENGTH]; + + memset(swap_iv, 0, AES_IV_LENGTH); + for (i = (AES_IV_LENGTH-len), j = len-1; i < AES_IV_LENGTH; i++, j--) + swap_iv[i] = b[j]; + _byte_stream_to_net_words(iv, swap_iv, AES_IV_LENGTH); +} + +static int count_sg(struct scatterlist *sg, int nbytes) +{ + int i; + + for (i = 0; nbytes > 0; i++, sg = sg_next(sg)) + nbytes -= sg->length; + return i; +} + +static int qce_dma_map_sg(struct device *dev, struct scatterlist *sg, int nents, + enum dma_data_direction direction) +{ + int i; + + for (i = 0; i < nents; ++i) { + dma_map_sg(dev, sg, 1, direction); + sg = sg_next(sg); + } + + return nents; +} + +static int qce_dma_unmap_sg(struct device *dev, struct scatterlist *sg, + int nents, enum dma_data_direction direction) +{ + int i; + + for (i = 0; i < nents; ++i) { + dma_unmap_sg(dev, sg, 1, direction); + sg = sg_next(sg); + } + + return nents; +} + +static int _probe_ce_engine(struct qce_device *pce_dev) +{ + unsigned int rev; + unsigned int maj_rev, min_rev, step_rev; + + rev = readl_relaxed(pce_dev->iobase + CRYPTO_VERSION_REG); + mb(); + maj_rev = (rev & CRYPTO_CORE_MAJOR_REV_MASK) >> CRYPTO_CORE_MAJOR_REV; + min_rev = (rev & CRYPTO_CORE_MINOR_REV_MASK) >> CRYPTO_CORE_MINOR_REV; + step_rev = (rev & CRYPTO_CORE_STEP_REV_MASK) >> CRYPTO_CORE_STEP_REV; + + if (maj_rev != CRYPTO_CORE_MAJOR_VER_NUM) { + pr_err("Unsupported Qualcomm crypto device at 0x%x, rev %d.%d.%d\n", + pce_dev->phy_iobase, maj_rev, min_rev, step_rev); + return -EIO; + } else { + /* + * The majority of crypto HW bugs have been fixed in 5.3.0 and + * above. That allows a single sps transfer of consumer + * pipe, and a single sps transfer of producer pipe + * for a crypto request. no_get_around flag indicates this. + * + * In 5.3.1, the CCM MAC_FAILED in result dump issue is + * fixed. no_ccm_mac_status_get_around flag indicates this. + */ + pce_dev->no_get_around = (min_rev >= + CRYPTO_CORE_MINOR_VER_NUM) ? true : false; + if (min_rev > CRYPTO_CORE_MINOR_VER_NUM) + pce_dev->no_ccm_mac_status_get_around = true; + else if ((min_rev == CRYPTO_CORE_MINOR_VER_NUM) && + (step_rev >= CRYPTO_CORE_STEP_VER_NUM)) + pce_dev->no_ccm_mac_status_get_around = true; + else + pce_dev->no_ccm_mac_status_get_around = false; + } + + pce_dev->ce_bam_info.minor_version = min_rev; + + pce_dev->engines_avail = readl_relaxed(pce_dev->iobase + + CRYPTO_ENGINES_AVAIL); + dev_info(pce_dev->pdev, "Qualcomm Crypto %d.%d.%d device found @0x%x\n", + maj_rev, min_rev, step_rev, pce_dev->phy_iobase); + + pce_dev->ce_bam_info.ce_burst_size = MAX_CE_BAM_BURST_SIZE; + + dev_info(pce_dev->pdev, + "CE device = 0x%x\n" + "IO base, CE = 0x%pK\n" + "Consumer (IN) PIPE %d, " + "Producer (OUT) PIPE %d\n" + "IO base BAM = 0x%pK\n" + "BAM IRQ %d\n" + "Engines Availability = 0x%x\n", + pce_dev->ce_bam_info.ce_device, + pce_dev->iobase, + pce_dev->ce_bam_info.dest_pipe_index, + pce_dev->ce_bam_info.src_pipe_index, + pce_dev->ce_bam_info.bam_iobase, + pce_dev->ce_bam_info.bam_irq, + pce_dev->engines_avail); + return 0; +}; + +static struct qce_cmdlist_info *_ce_get_hash_cmdlistinfo( + struct qce_device *pce_dev, + int req_info, struct qce_sha_req *sreq) +{ + struct ce_sps_data *pce_sps_data; + struct qce_cmdlistptr_ops *cmdlistptr; + + pce_sps_data = &pce_dev->ce_request_info[req_info].ce_sps; + cmdlistptr = &pce_sps_data->cmdlistptr; + switch (sreq->alg) { + case QCE_HASH_SHA1: + return &cmdlistptr->auth_sha1; + case QCE_HASH_SHA256: + return &cmdlistptr->auth_sha256; + case QCE_HASH_SHA1_HMAC: + return &cmdlistptr->auth_sha1_hmac; + case QCE_HASH_SHA256_HMAC: + return &cmdlistptr->auth_sha256_hmac; + case QCE_HASH_AES_CMAC: + if (sreq->authklen == AES128_KEY_SIZE) + return &cmdlistptr->auth_aes_128_cmac; + return &cmdlistptr->auth_aes_256_cmac; + default: + return NULL; + } + return NULL; +} + +static int _ce_setup_hash(struct qce_device *pce_dev, + struct qce_sha_req *sreq, + struct qce_cmdlist_info *cmdlistinfo) +{ + uint32_t auth32[SHA256_DIGEST_SIZE / sizeof(uint32_t)]; + uint32_t diglen; + int i; + uint32_t mackey32[SHA_HMAC_KEY_SIZE/sizeof(uint32_t)] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; + bool sha1 = false; + struct sps_command_element *pce = NULL; + bool use_hw_key = false; + bool use_pipe_key = false; + uint32_t authk_size_in_word = sreq->authklen/sizeof(uint32_t); + uint32_t auth_cfg; + + if ((sreq->alg == QCE_HASH_SHA1_HMAC) || + (sreq->alg == QCE_HASH_SHA256_HMAC) || + (sreq->alg == QCE_HASH_AES_CMAC)) { + + + /* no more check for null key. use flag */ + if ((sreq->flags & QCRYPTO_CTX_USE_HW_KEY) + == QCRYPTO_CTX_USE_HW_KEY) + use_hw_key = true; + else if ((sreq->flags & QCRYPTO_CTX_USE_PIPE_KEY) == + QCRYPTO_CTX_USE_PIPE_KEY) + use_pipe_key = true; + pce = cmdlistinfo->go_proc; + if (use_hw_key == true) { + pce->addr = (uint32_t)(CRYPTO_GOPROC_QC_KEY_REG + + pce_dev->phy_iobase); + } else { + pce->addr = (uint32_t)(CRYPTO_GOPROC_REG + + pce_dev->phy_iobase); + pce = cmdlistinfo->auth_key; + if (use_pipe_key == false) { + _byte_stream_to_net_words(mackey32, + sreq->authkey, + sreq->authklen); + for (i = 0; i < authk_size_in_word; i++, pce++) + pce->data = mackey32[i]; + } + } + } + + if (sreq->alg == QCE_HASH_AES_CMAC) + goto go_proc; + + /* if not the last, the size has to be on the block boundary */ + if (sreq->last_blk == 0 && (sreq->size % SHA256_BLOCK_SIZE)) + return -EIO; + + switch (sreq->alg) { + case QCE_HASH_SHA1: + case QCE_HASH_SHA1_HMAC: + diglen = SHA1_DIGEST_SIZE; + sha1 = true; + break; + case QCE_HASH_SHA256: + case QCE_HASH_SHA256_HMAC: + diglen = SHA256_DIGEST_SIZE; + break; + default: + return -EINVAL; + } + + /* write 20/32 bytes, 5/8 words into auth_iv for SHA1/SHA256 */ + if (sreq->first_blk) { + if (sha1) { + for (i = 0; i < 5; i++) + auth32[i] = _std_init_vector_sha1[i]; + } else { + for (i = 0; i < 8; i++) + auth32[i] = _std_init_vector_sha256[i]; + } + } else { + _byte_stream_to_net_words(auth32, sreq->digest, diglen); + } + + pce = cmdlistinfo->auth_iv; + for (i = 0; i < 5; i++, pce++) + pce->data = auth32[i]; + + if ((sreq->alg == QCE_HASH_SHA256) || + (sreq->alg == QCE_HASH_SHA256_HMAC)) { + for (i = 5; i < 8; i++, pce++) + pce->data = auth32[i]; + } + + /* write auth_bytecnt 0/1, start with 0 */ + pce = cmdlistinfo->auth_bytecount; + for (i = 0; i < 2; i++, pce++) + pce->data = sreq->auth_data[i]; + + /* Set/reset last bit in CFG register */ + pce = cmdlistinfo->auth_seg_cfg; + auth_cfg = pce->data & ~(1 << CRYPTO_LAST | + 1 << CRYPTO_FIRST | + 1 << CRYPTO_USE_PIPE_KEY_AUTH | + 1 << CRYPTO_USE_HW_KEY_AUTH); + if (sreq->last_blk) + auth_cfg |= 1 << CRYPTO_LAST; + if (sreq->first_blk) + auth_cfg |= 1 << CRYPTO_FIRST; + if (use_hw_key) + auth_cfg |= 1 << CRYPTO_USE_HW_KEY_AUTH; + if (use_pipe_key) + auth_cfg |= 1 << CRYPTO_USE_PIPE_KEY_AUTH; + pce->data = auth_cfg; +go_proc: + /* write auth seg size */ + pce = cmdlistinfo->auth_seg_size; + pce->data = sreq->size; + + pce = cmdlistinfo->encr_seg_cfg; + pce->data = 0; + + /* write auth seg size start*/ + pce = cmdlistinfo->auth_seg_start; + pce->data = 0; + + /* write seg size */ + pce = cmdlistinfo->seg_size; + + /* always ensure there is input data. ZLT does not work for bam-ndp */ + if (sreq->size) + pce->data = sreq->size; + else + pce->data = pce_dev->ce_bam_info.ce_burst_size; + + return 0; +} + +static struct qce_cmdlist_info *_ce_get_aead_cmdlistinfo( + struct qce_device *pce_dev, + int req_info, struct qce_req *creq) +{ + struct ce_sps_data *pce_sps_data; + struct qce_cmdlistptr_ops *cmdlistptr; + + pce_sps_data = &pce_dev->ce_request_info[req_info].ce_sps; + cmdlistptr = &pce_sps_data->cmdlistptr; + switch (creq->alg) { + case CIPHER_ALG_DES: + switch (creq->mode) { + case QCE_MODE_CBC: + if (creq->auth_alg == QCE_HASH_SHA1_HMAC) + return &cmdlistptr->aead_hmac_sha1_cbc_des; + else if (creq->auth_alg == QCE_HASH_SHA256_HMAC) + return &cmdlistptr->aead_hmac_sha256_cbc_des; + else + return NULL; + break; + default: + return NULL; + } + break; + case CIPHER_ALG_3DES: + switch (creq->mode) { + case QCE_MODE_CBC: + if (creq->auth_alg == QCE_HASH_SHA1_HMAC) + return &cmdlistptr->aead_hmac_sha1_cbc_3des; + else if (creq->auth_alg == QCE_HASH_SHA256_HMAC) + return &cmdlistptr->aead_hmac_sha256_cbc_3des; + else + return NULL; + break; + default: + return NULL; + } + break; + case CIPHER_ALG_AES: + switch (creq->mode) { + case QCE_MODE_CBC: + if (creq->encklen == AES128_KEY_SIZE) { + if (creq->auth_alg == QCE_HASH_SHA1_HMAC) + return &cmdlistptr-> + aead_hmac_sha1_cbc_aes_128; + else if (creq->auth_alg == + QCE_HASH_SHA256_HMAC) + return &cmdlistptr-> + aead_hmac_sha256_cbc_aes_128; + else + return NULL; + } else if (creq->encklen == AES256_KEY_SIZE) { + if (creq->auth_alg == QCE_HASH_SHA1_HMAC) + return &cmdlistptr-> + aead_hmac_sha1_cbc_aes_256; + else if (creq->auth_alg == + QCE_HASH_SHA256_HMAC) + return &cmdlistptr-> + aead_hmac_sha256_cbc_aes_256; + else + return NULL; + } else + return NULL; + break; + default: + return NULL; + } + break; + + default: + return NULL; + } + return NULL; +} + +static int _ce_setup_aead(struct qce_device *pce_dev, struct qce_req *q_req, + uint32_t totallen_in, uint32_t coffset, + struct qce_cmdlist_info *cmdlistinfo) +{ + int32_t authk_size_in_word = SHA_HMAC_KEY_SIZE/sizeof(uint32_t); + int i; + uint32_t mackey32[SHA_HMAC_KEY_SIZE/sizeof(uint32_t)] = {0}; + struct sps_command_element *pce; + uint32_t a_cfg; + uint32_t enckey32[(MAX_CIPHER_KEY_SIZE*2)/sizeof(uint32_t)] = {0}; + uint32_t enciv32[MAX_IV_LENGTH/sizeof(uint32_t)] = {0}; + uint32_t enck_size_in_word = 0; + uint32_t enciv_in_word; + uint32_t key_size; + uint32_t encr_cfg = 0; + uint32_t ivsize = q_req->ivsize; + + key_size = q_req->encklen; + enck_size_in_word = key_size/sizeof(uint32_t); + + switch (q_req->alg) { + case CIPHER_ALG_DES: + enciv_in_word = 2; + break; + case CIPHER_ALG_3DES: + enciv_in_word = 2; + break; + case CIPHER_ALG_AES: + if ((key_size != AES128_KEY_SIZE) && + (key_size != AES256_KEY_SIZE)) + return -EINVAL; + enciv_in_word = 4; + break; + default: + return -EINVAL; + } + + /* only support cbc mode */ + if (q_req->mode != QCE_MODE_CBC) + return -EINVAL; + + _byte_stream_to_net_words(enciv32, q_req->iv, ivsize); + pce = cmdlistinfo->encr_cntr_iv; + for (i = 0; i < enciv_in_word; i++, pce++) + pce->data = enciv32[i]; + + /* + * write encr key + * do not use hw key or pipe key + */ + _byte_stream_to_net_words(enckey32, q_req->enckey, key_size); + pce = cmdlistinfo->encr_key; + for (i = 0; i < enck_size_in_word; i++, pce++) + pce->data = enckey32[i]; + + /* write encr seg cfg */ + pce = cmdlistinfo->encr_seg_cfg; + encr_cfg = pce->data; + if (q_req->dir == QCE_ENCRYPT) + encr_cfg |= (1 << CRYPTO_ENCODE); + else + encr_cfg &= ~(1 << CRYPTO_ENCODE); + pce->data = encr_cfg; + + /* we only support sha1-hmac and sha256-hmac at this point */ + _byte_stream_to_net_words(mackey32, q_req->authkey, + q_req->authklen); + pce = cmdlistinfo->auth_key; + for (i = 0; i < authk_size_in_word; i++, pce++) + pce->data = mackey32[i]; + pce = cmdlistinfo->auth_iv; + + if (q_req->auth_alg == QCE_HASH_SHA1_HMAC) + for (i = 0; i < 5; i++, pce++) + pce->data = _std_init_vector_sha1[i]; + else + for (i = 0; i < 8; i++, pce++) + pce->data = _std_init_vector_sha256[i]; + + /* write auth_bytecnt 0/1, start with 0 */ + pce = cmdlistinfo->auth_bytecount; + for (i = 0; i < 2; i++, pce++) + pce->data = 0; + + pce = cmdlistinfo->auth_seg_cfg; + a_cfg = pce->data; + a_cfg &= ~(CRYPTO_AUTH_POS_MASK); + if (q_req->dir == QCE_ENCRYPT) + a_cfg |= (CRYPTO_AUTH_POS_AFTER << CRYPTO_AUTH_POS); + else + a_cfg |= (CRYPTO_AUTH_POS_BEFORE << CRYPTO_AUTH_POS); + pce->data = a_cfg; + + /* write auth seg size */ + pce = cmdlistinfo->auth_seg_size; + pce->data = totallen_in; + + /* write auth seg size start*/ + pce = cmdlistinfo->auth_seg_start; + pce->data = 0; + + /* write seg size */ + pce = cmdlistinfo->seg_size; + pce->data = totallen_in; + + /* write encr seg size */ + pce = cmdlistinfo->encr_seg_size; + pce->data = q_req->cryptlen; + + /* write encr seg start */ + pce = cmdlistinfo->encr_seg_start; + pce->data = (coffset & 0xffff); + + return 0; + +} + +static struct qce_cmdlist_info *_ce_get_cipher_cmdlistinfo( + struct qce_device *pce_dev, + int req_info, struct qce_req *creq) +{ + struct ce_request_info *preq_info; + struct ce_sps_data *pce_sps_data; + struct qce_cmdlistptr_ops *cmdlistptr; + + preq_info = &pce_dev->ce_request_info[req_info]; + pce_sps_data = &preq_info->ce_sps; + cmdlistptr = &pce_sps_data->cmdlistptr; + if (creq->alg != CIPHER_ALG_AES) { + switch (creq->alg) { + case CIPHER_ALG_DES: + if (creq->mode == QCE_MODE_ECB) + return &cmdlistptr->cipher_des_ecb; + return &cmdlistptr->cipher_des_cbc; + case CIPHER_ALG_3DES: + if (creq->mode == QCE_MODE_ECB) + return &cmdlistptr->cipher_3des_ecb; + return &cmdlistptr->cipher_3des_cbc; + default: + return NULL; + } + } else { + switch (creq->mode) { + case QCE_MODE_ECB: + if (creq->encklen == AES128_KEY_SIZE) + return &cmdlistptr->cipher_aes_128_ecb; + return &cmdlistptr->cipher_aes_256_ecb; + case QCE_MODE_CBC: + case QCE_MODE_CTR: + if (creq->encklen == AES128_KEY_SIZE) + return &cmdlistptr->cipher_aes_128_cbc_ctr; + return &cmdlistptr->cipher_aes_256_cbc_ctr; + case QCE_MODE_XTS: + if (creq->encklen/2 == AES128_KEY_SIZE) + return &cmdlistptr->cipher_aes_128_xts; + return &cmdlistptr->cipher_aes_256_xts; + case QCE_MODE_CCM: + if (creq->encklen == AES128_KEY_SIZE) + return &cmdlistptr->aead_aes_128_ccm; + return &cmdlistptr->aead_aes_256_ccm; + default: + return NULL; + } + } + return NULL; +} + +static int _ce_setup_cipher(struct qce_device *pce_dev, struct qce_req *creq, + uint32_t totallen_in, uint32_t coffset, + struct qce_cmdlist_info *cmdlistinfo) +{ + uint32_t enckey32[(MAX_CIPHER_KEY_SIZE * 2)/sizeof(uint32_t)] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; + uint32_t enciv32[MAX_IV_LENGTH / sizeof(uint32_t)] = { + 0, 0, 0, 0}; + uint32_t enck_size_in_word = 0; + uint32_t key_size; + bool use_hw_key = false; + bool use_pipe_key = false; + uint32_t encr_cfg = 0; + uint32_t ivsize = creq->ivsize; + int i; + struct sps_command_element *pce = NULL; + + if (creq->mode == QCE_MODE_XTS) + key_size = creq->encklen/2; + else + key_size = creq->encklen; + + pce = cmdlistinfo->go_proc; + if ((creq->flags & QCRYPTO_CTX_USE_HW_KEY) == QCRYPTO_CTX_USE_HW_KEY) { + use_hw_key = true; + } else { + if ((creq->flags & QCRYPTO_CTX_USE_PIPE_KEY) == + QCRYPTO_CTX_USE_PIPE_KEY) + use_pipe_key = true; + } + pce = cmdlistinfo->go_proc; + if (use_hw_key == true) + pce->addr = (uint32_t)(CRYPTO_GOPROC_QC_KEY_REG + + pce_dev->phy_iobase); + else + pce->addr = (uint32_t)(CRYPTO_GOPROC_REG + + pce_dev->phy_iobase); + if ((use_pipe_key == false) && (use_hw_key == false)) { + _byte_stream_to_net_words(enckey32, creq->enckey, key_size); + enck_size_in_word = key_size/sizeof(uint32_t); + } + + if ((creq->op == QCE_REQ_AEAD) && (creq->mode == QCE_MODE_CCM)) { + uint32_t authklen32 = creq->encklen/sizeof(uint32_t); + uint32_t noncelen32 = MAX_NONCE/sizeof(uint32_t); + uint32_t nonce32[MAX_NONCE/sizeof(uint32_t)] = {0, 0, 0, 0}; + uint32_t auth_cfg = 0; + + /* write nonce */ + _byte_stream_to_net_words(nonce32, creq->nonce, MAX_NONCE); + pce = cmdlistinfo->auth_nonce_info; + for (i = 0; i < noncelen32; i++, pce++) + pce->data = nonce32[i]; + + if (creq->authklen == AES128_KEY_SIZE) + auth_cfg = pce_dev->reg.auth_cfg_aes_ccm_128; + else { + if (creq->authklen == AES256_KEY_SIZE) + auth_cfg = pce_dev->reg.auth_cfg_aes_ccm_256; + } + if (creq->dir == QCE_ENCRYPT) + auth_cfg |= (CRYPTO_AUTH_POS_BEFORE << CRYPTO_AUTH_POS); + else + auth_cfg |= (CRYPTO_AUTH_POS_AFTER << CRYPTO_AUTH_POS); + auth_cfg |= ((creq->authsize - 1) << CRYPTO_AUTH_SIZE); + + if (use_hw_key == true) { + auth_cfg |= (1 << CRYPTO_USE_HW_KEY_AUTH); + } else { + auth_cfg &= ~(1 << CRYPTO_USE_HW_KEY_AUTH); + /* write auth key */ + pce = cmdlistinfo->auth_key; + for (i = 0; i < authklen32; i++, pce++) + pce->data = enckey32[i]; + } + + pce = cmdlistinfo->auth_seg_cfg; + pce->data = auth_cfg; + + pce = cmdlistinfo->auth_seg_size; + if (creq->dir == QCE_ENCRYPT) + pce->data = totallen_in; + else + pce->data = totallen_in - creq->authsize; + pce = cmdlistinfo->auth_seg_start; + pce->data = 0; + } else { + if (creq->op != QCE_REQ_AEAD) { + pce = cmdlistinfo->auth_seg_cfg; + pce->data = 0; + } + } + switch (creq->mode) { + case QCE_MODE_ECB: + if (key_size == AES128_KEY_SIZE) + encr_cfg = pce_dev->reg.encr_cfg_aes_ecb_128; + else + encr_cfg = pce_dev->reg.encr_cfg_aes_ecb_256; + break; + case QCE_MODE_CBC: + if (key_size == AES128_KEY_SIZE) + encr_cfg = pce_dev->reg.encr_cfg_aes_cbc_128; + else + encr_cfg = pce_dev->reg.encr_cfg_aes_cbc_256; + break; + case QCE_MODE_XTS: + if (key_size == AES128_KEY_SIZE) + encr_cfg = pce_dev->reg.encr_cfg_aes_xts_128; + else + encr_cfg = pce_dev->reg.encr_cfg_aes_xts_256; + break; + case QCE_MODE_CCM: + if (key_size == AES128_KEY_SIZE) + encr_cfg = pce_dev->reg.encr_cfg_aes_ccm_128; + else + encr_cfg = pce_dev->reg.encr_cfg_aes_ccm_256; + encr_cfg |= (CRYPTO_ENCR_MODE_CCM << CRYPTO_ENCR_MODE) | + (CRYPTO_LAST_CCM_XFR << CRYPTO_LAST_CCM); + break; + case QCE_MODE_CTR: + default: + if (key_size == AES128_KEY_SIZE) + encr_cfg = pce_dev->reg.encr_cfg_aes_ctr_128; + else + encr_cfg = pce_dev->reg.encr_cfg_aes_ctr_256; + break; + } + + switch (creq->alg) { + case CIPHER_ALG_DES: + if (creq->mode != QCE_MODE_ECB) { + _byte_stream_to_net_words(enciv32, creq->iv, ivsize); + pce = cmdlistinfo->encr_cntr_iv; + pce->data = enciv32[0]; + pce++; + pce->data = enciv32[1]; + } + if (use_hw_key == false) { + pce = cmdlistinfo->encr_key; + pce->data = enckey32[0]; + pce++; + pce->data = enckey32[1]; + } + break; + case CIPHER_ALG_3DES: + if (creq->mode != QCE_MODE_ECB) { + _byte_stream_to_net_words(enciv32, creq->iv, ivsize); + pce = cmdlistinfo->encr_cntr_iv; + pce->data = enciv32[0]; + pce++; + pce->data = enciv32[1]; + } + if (use_hw_key == false) { + /* write encr key */ + pce = cmdlistinfo->encr_key; + for (i = 0; i < 6; i++, pce++) + pce->data = enckey32[i]; + } + break; + case CIPHER_ALG_AES: + default: + if (creq->mode == QCE_MODE_XTS) { + uint32_t xtskey32[MAX_CIPHER_KEY_SIZE/sizeof(uint32_t)] + = {0, 0, 0, 0, 0, 0, 0, 0}; + uint32_t xtsklen = + creq->encklen/(2 * sizeof(uint32_t)); + + if ((use_hw_key == false) && (use_pipe_key == false)) { + _byte_stream_to_net_words(xtskey32, + (creq->enckey + creq->encklen/2), + creq->encklen/2); + /* write xts encr key */ + pce = cmdlistinfo->encr_xts_key; + for (i = 0; i < xtsklen; i++, pce++) + pce->data = xtskey32[i]; + } + /* write xts du size */ + pce = cmdlistinfo->encr_xts_du_size; + switch (creq->flags & QCRYPTO_CTX_XTS_MASK) { + case QCRYPTO_CTX_XTS_DU_SIZE_512B: + pce->data = min((unsigned int)QCE_SECTOR_SIZE, + creq->cryptlen); + break; + case QCRYPTO_CTX_XTS_DU_SIZE_1KB: + pce->data = + min((unsigned int)QCE_SECTOR_SIZE * 2, + creq->cryptlen); + break; + default: + pce->data = creq->cryptlen; + break; + } + } + if (creq->mode != QCE_MODE_ECB) { + if (creq->mode == QCE_MODE_XTS) + _byte_stream_swap_to_net_words(enciv32, + creq->iv, ivsize); + else + _byte_stream_to_net_words(enciv32, creq->iv, + ivsize); + /* write encr cntr iv */ + pce = cmdlistinfo->encr_cntr_iv; + for (i = 0; i < 4; i++, pce++) + pce->data = enciv32[i]; + + if (creq->mode == QCE_MODE_CCM) { + /* write cntr iv for ccm */ + pce = cmdlistinfo->encr_ccm_cntr_iv; + for (i = 0; i < 4; i++, pce++) + pce->data = enciv32[i]; + /* update cntr_iv[3] by one */ + pce = cmdlistinfo->encr_cntr_iv; + pce += 3; + pce->data += 1; + } + } + + if (creq->op == QCE_REQ_ABLK_CIPHER_NO_KEY) { + encr_cfg |= (CRYPTO_ENCR_KEY_SZ_AES128 << + CRYPTO_ENCR_KEY_SZ); + } else { + if (use_hw_key == false) { + /* write encr key */ + pce = cmdlistinfo->encr_key; + for (i = 0; i < enck_size_in_word; i++, pce++) + pce->data = enckey32[i]; + } + } /* else of if (creq->op == QCE_REQ_ABLK_CIPHER_NO_KEY) */ + break; + } /* end of switch (creq->mode) */ + + if (use_pipe_key) + encr_cfg |= (CRYPTO_USE_PIPE_KEY_ENCR_ENABLED + << CRYPTO_USE_PIPE_KEY_ENCR); + + /* write encr seg cfg */ + pce = cmdlistinfo->encr_seg_cfg; + if ((creq->alg == CIPHER_ALG_DES) || (creq->alg == CIPHER_ALG_3DES)) { + if (creq->dir == QCE_ENCRYPT) + pce->data |= (1 << CRYPTO_ENCODE); + else + pce->data &= ~(1 << CRYPTO_ENCODE); + encr_cfg = pce->data; + } else { + encr_cfg |= + ((creq->dir == QCE_ENCRYPT) ? 1 : 0) << CRYPTO_ENCODE; + } + if (use_hw_key == true) + encr_cfg |= (CRYPTO_USE_HW_KEY << CRYPTO_USE_HW_KEY_ENCR); + else + encr_cfg &= ~(CRYPTO_USE_HW_KEY << CRYPTO_USE_HW_KEY_ENCR); + pce->data = encr_cfg; + + /* write encr seg size */ + pce = cmdlistinfo->encr_seg_size; + if ((creq->mode == QCE_MODE_CCM) && (creq->dir == QCE_DECRYPT)) + pce->data = (creq->cryptlen + creq->authsize); + else + pce->data = creq->cryptlen; + + /* write encr seg start */ + pce = cmdlistinfo->encr_seg_start; + pce->data = (coffset & 0xffff); + + /* write seg size */ + pce = cmdlistinfo->seg_size; + pce->data = totallen_in; + + return 0; +}; + +static int _ce_f9_setup(struct qce_device *pce_dev, struct qce_f9_req *req, + struct qce_cmdlist_info *cmdlistinfo) +{ + uint32_t ikey32[OTA_KEY_SIZE/sizeof(uint32_t)]; + uint32_t key_size_in_word = OTA_KEY_SIZE/sizeof(uint32_t); + uint32_t cfg; + struct sps_command_element *pce; + int i; + + switch (req->algorithm) { + case QCE_OTA_ALGO_KASUMI: + cfg = pce_dev->reg.auth_cfg_kasumi; + break; + case QCE_OTA_ALGO_SNOW3G: + default: + cfg = pce_dev->reg.auth_cfg_snow3g; + break; + }; + + /* write key in CRYPTO_AUTH_IV0-3_REG */ + _byte_stream_to_net_words(ikey32, &req->ikey[0], OTA_KEY_SIZE); + pce = cmdlistinfo->auth_iv; + for (i = 0; i < key_size_in_word; i++, pce++) + pce->data = ikey32[i]; + + /* write last bits in CRYPTO_AUTH_IV4_REG */ + pce->data = req->last_bits; + + /* write fresh to CRYPTO_AUTH_BYTECNT0_REG */ + pce = cmdlistinfo->auth_bytecount; + pce->data = req->fresh; + + /* write count-i to CRYPTO_AUTH_BYTECNT1_REG */ + pce++; + pce->data = req->count_i; + + /* write auth seg cfg */ + pce = cmdlistinfo->auth_seg_cfg; + if (req->direction == QCE_OTA_DIR_DOWNLINK) + cfg |= BIT(CRYPTO_F9_DIRECTION); + pce->data = cfg; + + /* write auth seg size */ + pce = cmdlistinfo->auth_seg_size; + pce->data = req->msize; + + /* write auth seg start*/ + pce = cmdlistinfo->auth_seg_start; + pce->data = 0; + + /* write seg size */ + pce = cmdlistinfo->seg_size; + pce->data = req->msize; + + + /* write go */ + pce = cmdlistinfo->go_proc; + pce->addr = (uint32_t)(CRYPTO_GOPROC_REG + pce_dev->phy_iobase); + return 0; +} + +static int _ce_f8_setup(struct qce_device *pce_dev, struct qce_f8_req *req, + bool key_stream_mode, uint16_t npkts, uint16_t cipher_offset, + uint16_t cipher_size, + struct qce_cmdlist_info *cmdlistinfo) +{ + uint32_t ckey32[OTA_KEY_SIZE/sizeof(uint32_t)]; + uint32_t key_size_in_word = OTA_KEY_SIZE/sizeof(uint32_t); + uint32_t cfg; + struct sps_command_element *pce; + int i; + + switch (req->algorithm) { + case QCE_OTA_ALGO_KASUMI: + cfg = pce_dev->reg.encr_cfg_kasumi; + break; + case QCE_OTA_ALGO_SNOW3G: + default: + cfg = pce_dev->reg.encr_cfg_snow3g; + break; + }; + /* write key */ + _byte_stream_to_net_words(ckey32, &req->ckey[0], OTA_KEY_SIZE); + pce = cmdlistinfo->encr_key; + for (i = 0; i < key_size_in_word; i++, pce++) + pce->data = ckey32[i]; + + /* write encr seg cfg */ + pce = cmdlistinfo->encr_seg_cfg; + if (key_stream_mode) + cfg |= BIT(CRYPTO_F8_KEYSTREAM_ENABLE); + if (req->direction == QCE_OTA_DIR_DOWNLINK) + cfg |= BIT(CRYPTO_F8_DIRECTION); + pce->data = cfg; + + /* write encr seg start */ + pce = cmdlistinfo->encr_seg_start; + pce->data = (cipher_offset & 0xffff); + + /* write encr seg size */ + pce = cmdlistinfo->encr_seg_size; + pce->data = cipher_size; + + /* write seg size */ + pce = cmdlistinfo->seg_size; + pce->data = req->data_len; + + /* write cntr0_iv0 for countC */ + pce = cmdlistinfo->encr_cntr_iv; + pce->data = req->count_c; + /* write cntr1_iv1 for nPkts, and bearer */ + pce++; + if (npkts == 1) + npkts = 0; + pce->data = req->bearer << CRYPTO_CNTR1_IV1_REG_F8_BEARER | + npkts << CRYPTO_CNTR1_IV1_REG_F8_PKT_CNT; + + /* write go */ + pce = cmdlistinfo->go_proc; + pce->addr = (uint32_t)(CRYPTO_GOPROC_REG + pce_dev->phy_iobase); + + return 0; +} + +static void _qce_dump_descr_fifos(struct qce_device *pce_dev, int req_info) +{ + int i, j, ents; + struct ce_sps_data *pce_sps_data; + struct sps_iovec *iovec; + uint32_t cmd_flags = SPS_IOVEC_FLAG_CMD; + + pce_sps_data = &pce_dev->ce_request_info[req_info].ce_sps; + iovec = pce_sps_data->in_transfer.iovec; + pr_info("==============================================\n"); + pr_info("CONSUMER (TX/IN/DEST) PIPE DESCRIPTOR\n"); + pr_info("==============================================\n"); + for (i = 0; i < pce_sps_data->in_transfer.iovec_count; i++) { + pr_info(" [%d] addr=0x%x size=0x%x flags=0x%x\n", i, + iovec->addr, iovec->size, iovec->flags); + if (iovec->flags & cmd_flags) { + struct sps_command_element *pced; + + pced = (struct sps_command_element *) + (GET_VIRT_ADDR(iovec->addr)); + ents = iovec->size/(sizeof(struct sps_command_element)); + for (j = 0; j < ents; j++) { + pr_info(" [%d] [0x%x] 0x%x\n", j, + pced->addr, pced->data); + pced++; + } + } + iovec++; + } + + pr_info("==============================================\n"); + pr_info("PRODUCER (RX/OUT/SRC) PIPE DESCRIPTOR\n"); + pr_info("==============================================\n"); + iovec = pce_sps_data->out_transfer.iovec; + for (i = 0; i < pce_sps_data->out_transfer.iovec_count; i++) { + pr_info(" [%d] addr=0x%x size=0x%x flags=0x%x\n", i, + iovec->addr, iovec->size, iovec->flags); + iovec++; + } +} + +#ifdef QCE_DEBUG + +static void _qce_dump_descr_fifos_dbg(struct qce_device *pce_dev, int req_info) +{ + _qce_dump_descr_fifos(pce_dev, req_info); +} + +#define QCE_WRITE_REG(val, addr) \ +{ \ + pr_info(" [0x%pK] 0x%x\n", addr, (uint32_t)val); \ + writel_relaxed(val, addr); \ +} + +#else + +static void _qce_dump_descr_fifos_dbg(struct qce_device *pce_dev, int req_info) +{ +} + +#define QCE_WRITE_REG(val, addr) \ + writel_relaxed(val, addr) + +#endif + +static int _ce_setup_hash_direct(struct qce_device *pce_dev, + struct qce_sha_req *sreq) +{ + uint32_t auth32[SHA256_DIGEST_SIZE / sizeof(uint32_t)]; + uint32_t diglen; + bool use_hw_key = false; + bool use_pipe_key = false; + int i; + uint32_t mackey32[SHA_HMAC_KEY_SIZE/sizeof(uint32_t)] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; + uint32_t authk_size_in_word = sreq->authklen/sizeof(uint32_t); + bool sha1 = false; + uint32_t auth_cfg = 0; + + /* clear status */ + QCE_WRITE_REG(0, pce_dev->iobase + CRYPTO_STATUS_REG); + + QCE_WRITE_REG(pce_dev->reg.crypto_cfg_be, (pce_dev->iobase + + CRYPTO_CONFIG_REG)); + /* + * Ensure previous instructions (setting the CONFIG register) + * was completed before issuing starting to set other config register + * This is to ensure the configurations are done in correct endian-ness + * as set in the CONFIG registers + */ + mb(); + + if (sreq->alg == QCE_HASH_AES_CMAC) { + /* write seg_cfg */ + QCE_WRITE_REG(0, pce_dev->iobase + CRYPTO_AUTH_SEG_CFG_REG); + /* write seg_cfg */ + QCE_WRITE_REG(0, pce_dev->iobase + CRYPTO_ENCR_SEG_CFG_REG); + /* write seg_cfg */ + QCE_WRITE_REG(0, pce_dev->iobase + CRYPTO_ENCR_SEG_SIZE_REG); + + /* Clear auth_ivn, auth_keyn registers */ + for (i = 0; i < 16; i++) { + QCE_WRITE_REG(0, (pce_dev->iobase + + (CRYPTO_AUTH_IV0_REG + i*sizeof(uint32_t)))); + QCE_WRITE_REG(0, (pce_dev->iobase + + (CRYPTO_AUTH_KEY0_REG + i*sizeof(uint32_t)))); + } + /* write auth_bytecnt 0/1/2/3, start with 0 */ + for (i = 0; i < 4; i++) + QCE_WRITE_REG(0, pce_dev->iobase + + CRYPTO_AUTH_BYTECNT0_REG + + i * sizeof(uint32_t)); + + if (sreq->authklen == AES128_KEY_SIZE) + auth_cfg = pce_dev->reg.auth_cfg_cmac_128; + else + auth_cfg = pce_dev->reg.auth_cfg_cmac_256; + } + + if ((sreq->alg == QCE_HASH_SHA1_HMAC) || + (sreq->alg == QCE_HASH_SHA256_HMAC) || + (sreq->alg == QCE_HASH_AES_CMAC)) { + + _byte_stream_to_net_words(mackey32, sreq->authkey, + sreq->authklen); + + /* no more check for null key. use flag to check*/ + + if ((sreq->flags & QCRYPTO_CTX_USE_HW_KEY) == + QCRYPTO_CTX_USE_HW_KEY) { + use_hw_key = true; + } else if ((sreq->flags & QCRYPTO_CTX_USE_PIPE_KEY) == + QCRYPTO_CTX_USE_PIPE_KEY) { + use_pipe_key = true; + } else { + /* setup key */ + for (i = 0; i < authk_size_in_word; i++) + QCE_WRITE_REG(mackey32[i], (pce_dev->iobase + + (CRYPTO_AUTH_KEY0_REG + + i*sizeof(uint32_t)))); + } + } + + if (sreq->alg == QCE_HASH_AES_CMAC) + goto go_proc; + + /* if not the last, the size has to be on the block boundary */ + if (sreq->last_blk == 0 && (sreq->size % SHA256_BLOCK_SIZE)) + return -EIO; + + switch (sreq->alg) { + case QCE_HASH_SHA1: + auth_cfg = pce_dev->reg.auth_cfg_sha1; + diglen = SHA1_DIGEST_SIZE; + sha1 = true; + break; + case QCE_HASH_SHA1_HMAC: + auth_cfg = pce_dev->reg.auth_cfg_hmac_sha1; + diglen = SHA1_DIGEST_SIZE; + sha1 = true; + break; + case QCE_HASH_SHA256: + auth_cfg = pce_dev->reg.auth_cfg_sha256; + diglen = SHA256_DIGEST_SIZE; + break; + case QCE_HASH_SHA256_HMAC: + auth_cfg = pce_dev->reg.auth_cfg_hmac_sha256; + diglen = SHA256_DIGEST_SIZE; + break; + default: + return -EINVAL; + } + + /* write 20/32 bytes, 5/8 words into auth_iv for SHA1/SHA256 */ + if (sreq->first_blk) { + if (sha1) { + for (i = 0; i < 5; i++) + auth32[i] = _std_init_vector_sha1[i]; + } else { + for (i = 0; i < 8; i++) + auth32[i] = _std_init_vector_sha256[i]; + } + } else { + _byte_stream_to_net_words(auth32, sreq->digest, diglen); + } + + /* Set auth_ivn, auth_keyn registers */ + for (i = 0; i < 5; i++) + QCE_WRITE_REG(auth32[i], (pce_dev->iobase + + (CRYPTO_AUTH_IV0_REG + i*sizeof(uint32_t)))); + + if ((sreq->alg == QCE_HASH_SHA256) || + (sreq->alg == QCE_HASH_SHA256_HMAC)) { + for (i = 5; i < 8; i++) + QCE_WRITE_REG(auth32[i], (pce_dev->iobase + + (CRYPTO_AUTH_IV0_REG + i*sizeof(uint32_t)))); + } + + + /* write auth_bytecnt 0/1/2/3, start with 0 */ + for (i = 0; i < 2; i++) + QCE_WRITE_REG(sreq->auth_data[i], pce_dev->iobase + + CRYPTO_AUTH_BYTECNT0_REG + + i * sizeof(uint32_t)); + + /* Set/reset last bit in CFG register */ + if (sreq->last_blk) + auth_cfg |= 1 << CRYPTO_LAST; + else + auth_cfg &= ~(1 << CRYPTO_LAST); + if (sreq->first_blk) + auth_cfg |= 1 << CRYPTO_FIRST; + else + auth_cfg &= ~(1 << CRYPTO_FIRST); + if (use_hw_key) + auth_cfg |= 1 << CRYPTO_USE_HW_KEY_AUTH; + if (use_pipe_key) + auth_cfg |= 1 << CRYPTO_USE_PIPE_KEY_AUTH; +go_proc: + /* write seg_cfg */ + QCE_WRITE_REG(auth_cfg, pce_dev->iobase + CRYPTO_AUTH_SEG_CFG_REG); + /* write auth seg_size */ + QCE_WRITE_REG(sreq->size, pce_dev->iobase + CRYPTO_AUTH_SEG_SIZE_REG); + + /* write auth_seg_start */ + QCE_WRITE_REG(0, pce_dev->iobase + CRYPTO_AUTH_SEG_START_REG); + + /* reset encr seg_cfg */ + QCE_WRITE_REG(0, pce_dev->iobase + CRYPTO_ENCR_SEG_CFG_REG); + + /* write seg_size */ + QCE_WRITE_REG(sreq->size, pce_dev->iobase + CRYPTO_SEG_SIZE_REG); + + QCE_WRITE_REG(pce_dev->reg.crypto_cfg_le, (pce_dev->iobase + + CRYPTO_CONFIG_REG)); + /* issue go to crypto */ + if (use_hw_key == false) { + QCE_WRITE_REG(((1 << CRYPTO_GO) | (1 << CRYPTO_RESULTS_DUMP) | + (1 << CRYPTO_CLR_CNTXT)), + pce_dev->iobase + CRYPTO_GOPROC_REG); + } else { + QCE_WRITE_REG(((1 << CRYPTO_GO) | (1 << CRYPTO_RESULTS_DUMP)), + pce_dev->iobase + CRYPTO_GOPROC_QC_KEY_REG); + } + /* + * Ensure previous instructions (setting the GO register) + * was completed before issuing a DMA transfer request + */ + mb(); + return 0; +} + +static int _ce_setup_aead_direct(struct qce_device *pce_dev, + struct qce_req *q_req, uint32_t totallen_in, uint32_t coffset) +{ + int32_t authk_size_in_word = SHA_HMAC_KEY_SIZE/sizeof(uint32_t); + int i; + uint32_t mackey32[SHA_HMAC_KEY_SIZE/sizeof(uint32_t)] = {0}; + uint32_t a_cfg; + uint32_t enckey32[(MAX_CIPHER_KEY_SIZE*2)/sizeof(uint32_t)] = {0}; + uint32_t enciv32[MAX_IV_LENGTH/sizeof(uint32_t)] = {0}; + uint32_t enck_size_in_word = 0; + uint32_t enciv_in_word; + uint32_t key_size; + uint32_t ivsize = q_req->ivsize; + uint32_t encr_cfg; + + + /* clear status */ + QCE_WRITE_REG(0, pce_dev->iobase + CRYPTO_STATUS_REG); + + QCE_WRITE_REG(pce_dev->reg.crypto_cfg_be, (pce_dev->iobase + + CRYPTO_CONFIG_REG)); + /* + * Ensure previous instructions (setting the CONFIG register) + * was completed before issuing starting to set other config register + * This is to ensure the configurations are done in correct endian-ness + * as set in the CONFIG registers + */ + mb(); + + key_size = q_req->encklen; + enck_size_in_word = key_size/sizeof(uint32_t); + + switch (q_req->alg) { + + case CIPHER_ALG_DES: + + switch (q_req->mode) { + case QCE_MODE_CBC: + encr_cfg = pce_dev->reg.encr_cfg_des_cbc; + break; + default: + return -EINVAL; + } + + enciv_in_word = 2; + break; + + case CIPHER_ALG_3DES: + + switch (q_req->mode) { + case QCE_MODE_CBC: + encr_cfg = pce_dev->reg.encr_cfg_3des_cbc; + break; + default: + return -EINVAL; + } + + enciv_in_word = 2; + + break; + + case CIPHER_ALG_AES: + + switch (q_req->mode) { + case QCE_MODE_CBC: + if (key_size == AES128_KEY_SIZE) + encr_cfg = pce_dev->reg.encr_cfg_aes_cbc_128; + else if (key_size == AES256_KEY_SIZE) + encr_cfg = pce_dev->reg.encr_cfg_aes_cbc_256; + else + return -EINVAL; + break; + default: + return -EINVAL; + } + + enciv_in_word = 4; + break; + + default: + return -EINVAL; + } + + + + + /* write CNTR0_IV0_REG */ + if (q_req->mode != QCE_MODE_ECB) { + _byte_stream_to_net_words(enciv32, q_req->iv, ivsize); + for (i = 0; i < enciv_in_word; i++) + QCE_WRITE_REG(enciv32[i], pce_dev->iobase + + (CRYPTO_CNTR0_IV0_REG + i * sizeof(uint32_t))); + } + + /* + * write encr key + * do not use hw key or pipe key + */ + _byte_stream_to_net_words(enckey32, q_req->enckey, key_size); + for (i = 0; i < enck_size_in_word; i++) + QCE_WRITE_REG(enckey32[i], pce_dev->iobase + + (CRYPTO_ENCR_KEY0_REG + i * sizeof(uint32_t))); + + /* write encr seg cfg */ + if (q_req->dir == QCE_ENCRYPT) + encr_cfg |= (1 << CRYPTO_ENCODE); + QCE_WRITE_REG(encr_cfg, pce_dev->iobase + CRYPTO_ENCR_SEG_CFG_REG); + + /* we only support sha1-hmac and sha256-hmac at this point */ + _byte_stream_to_net_words(mackey32, q_req->authkey, + q_req->authklen); + for (i = 0; i < authk_size_in_word; i++) + QCE_WRITE_REG(mackey32[i], pce_dev->iobase + + (CRYPTO_AUTH_KEY0_REG + i * sizeof(uint32_t))); + + if (q_req->auth_alg == QCE_HASH_SHA1_HMAC) { + for (i = 0; i < 5; i++) + QCE_WRITE_REG(_std_init_vector_sha1[i], + pce_dev->iobase + + (CRYPTO_AUTH_IV0_REG + i * sizeof(uint32_t))); + } else { + for (i = 0; i < 8; i++) + QCE_WRITE_REG(_std_init_vector_sha256[i], + pce_dev->iobase + + (CRYPTO_AUTH_IV0_REG + i * sizeof(uint32_t))); + } + + /* write auth_bytecnt 0/1, start with 0 */ + QCE_WRITE_REG(0, pce_dev->iobase + CRYPTO_AUTH_BYTECNT0_REG); + QCE_WRITE_REG(0, pce_dev->iobase + CRYPTO_AUTH_BYTECNT1_REG); + + /* write encr seg size */ + QCE_WRITE_REG(q_req->cryptlen, pce_dev->iobase + + CRYPTO_ENCR_SEG_SIZE_REG); + + /* write encr start */ + QCE_WRITE_REG(coffset & 0xffff, pce_dev->iobase + + CRYPTO_ENCR_SEG_START_REG); + + if (q_req->auth_alg == QCE_HASH_SHA1_HMAC) + a_cfg = pce_dev->reg.auth_cfg_aead_sha1_hmac; + else + a_cfg = pce_dev->reg.auth_cfg_aead_sha256_hmac; + + if (q_req->dir == QCE_ENCRYPT) + a_cfg |= (CRYPTO_AUTH_POS_AFTER << CRYPTO_AUTH_POS); + else + a_cfg |= (CRYPTO_AUTH_POS_BEFORE << CRYPTO_AUTH_POS); + + /* write auth seg_cfg */ + QCE_WRITE_REG(a_cfg, pce_dev->iobase + CRYPTO_AUTH_SEG_CFG_REG); + + /* write auth seg_size */ + QCE_WRITE_REG(totallen_in, pce_dev->iobase + CRYPTO_AUTH_SEG_SIZE_REG); + + /* write auth_seg_start */ + QCE_WRITE_REG(0, pce_dev->iobase + CRYPTO_AUTH_SEG_START_REG); + + + /* write seg_size */ + QCE_WRITE_REG(totallen_in, pce_dev->iobase + CRYPTO_SEG_SIZE_REG); + + + QCE_WRITE_REG(pce_dev->reg.crypto_cfg_le, (pce_dev->iobase + + + CRYPTO_CONFIG_REG)); + /* issue go to crypto */ + QCE_WRITE_REG(((1 << CRYPTO_GO) | (1 << CRYPTO_RESULTS_DUMP) | + (1 << CRYPTO_CLR_CNTXT)), + pce_dev->iobase + CRYPTO_GOPROC_REG); + /* + * Ensure previous instructions (setting the GO register) + * was completed before issuing a DMA transfer request + */ + mb(); + return 0; +}; + +static int _ce_setup_cipher_direct(struct qce_device *pce_dev, + struct qce_req *creq, uint32_t totallen_in, uint32_t coffset) +{ + uint32_t enckey32[(MAX_CIPHER_KEY_SIZE * 2)/sizeof(uint32_t)] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; + uint32_t enciv32[MAX_IV_LENGTH / sizeof(uint32_t)] = { + 0, 0, 0, 0}; + uint32_t enck_size_in_word = 0; + uint32_t key_size; + bool use_hw_key = false; + bool use_pipe_key = false; + uint32_t encr_cfg = 0; + uint32_t ivsize = creq->ivsize; + int i; + + /* clear status */ + QCE_WRITE_REG(0, pce_dev->iobase + CRYPTO_STATUS_REG); + + QCE_WRITE_REG(pce_dev->reg.crypto_cfg_be, (pce_dev->iobase + + CRYPTO_CONFIG_REG)); + /* + * Ensure previous instructions (setting the CONFIG register) + * was completed before issuing starting to set other config register + * This is to ensure the configurations are done in correct endian-ness + * as set in the CONFIG registers + */ + mb(); + + if (creq->mode == QCE_MODE_XTS) + key_size = creq->encklen/2; + else + key_size = creq->encklen; + + if ((creq->flags & QCRYPTO_CTX_USE_HW_KEY) == QCRYPTO_CTX_USE_HW_KEY) { + use_hw_key = true; + } else { + if ((creq->flags & QCRYPTO_CTX_USE_PIPE_KEY) == + QCRYPTO_CTX_USE_PIPE_KEY) + use_pipe_key = true; + } + if ((use_pipe_key == false) && (use_hw_key == false)) { + _byte_stream_to_net_words(enckey32, creq->enckey, key_size); + enck_size_in_word = key_size/sizeof(uint32_t); + } + if ((creq->op == QCE_REQ_AEAD) && (creq->mode == QCE_MODE_CCM)) { + uint32_t authklen32 = creq->encklen/sizeof(uint32_t); + uint32_t noncelen32 = MAX_NONCE/sizeof(uint32_t); + uint32_t nonce32[MAX_NONCE/sizeof(uint32_t)] = {0, 0, 0, 0}; + uint32_t auth_cfg = 0; + + /* Clear auth_ivn, auth_keyn registers */ + for (i = 0; i < 16; i++) { + QCE_WRITE_REG(0, (pce_dev->iobase + + (CRYPTO_AUTH_IV0_REG + i*sizeof(uint32_t)))); + QCE_WRITE_REG(0, (pce_dev->iobase + + (CRYPTO_AUTH_KEY0_REG + i*sizeof(uint32_t)))); + } + /* write auth_bytecnt 0/1/2/3, start with 0 */ + for (i = 0; i < 4; i++) + QCE_WRITE_REG(0, pce_dev->iobase + + CRYPTO_AUTH_BYTECNT0_REG + + i * sizeof(uint32_t)); + /* write nonce */ + _byte_stream_to_net_words(nonce32, creq->nonce, MAX_NONCE); + for (i = 0; i < noncelen32; i++) + QCE_WRITE_REG(nonce32[i], pce_dev->iobase + + CRYPTO_AUTH_INFO_NONCE0_REG + + (i*sizeof(uint32_t))); + + if (creq->authklen == AES128_KEY_SIZE) + auth_cfg = pce_dev->reg.auth_cfg_aes_ccm_128; + else { + if (creq->authklen == AES256_KEY_SIZE) + auth_cfg = pce_dev->reg.auth_cfg_aes_ccm_256; + } + if (creq->dir == QCE_ENCRYPT) + auth_cfg |= (CRYPTO_AUTH_POS_BEFORE << CRYPTO_AUTH_POS); + else + auth_cfg |= (CRYPTO_AUTH_POS_AFTER << CRYPTO_AUTH_POS); + auth_cfg |= ((creq->authsize - 1) << CRYPTO_AUTH_SIZE); + + if (use_hw_key == true) { + auth_cfg |= (1 << CRYPTO_USE_HW_KEY_AUTH); + } else { + auth_cfg &= ~(1 << CRYPTO_USE_HW_KEY_AUTH); + /* write auth key */ + for (i = 0; i < authklen32; i++) + QCE_WRITE_REG(enckey32[i], pce_dev->iobase + + CRYPTO_AUTH_KEY0_REG + (i*sizeof(uint32_t))); + } + QCE_WRITE_REG(auth_cfg, pce_dev->iobase + + CRYPTO_AUTH_SEG_CFG_REG); + if (creq->dir == QCE_ENCRYPT) { + QCE_WRITE_REG(totallen_in, pce_dev->iobase + + CRYPTO_AUTH_SEG_SIZE_REG); + } else { + QCE_WRITE_REG((totallen_in - creq->authsize), + pce_dev->iobase + CRYPTO_AUTH_SEG_SIZE_REG); + } + QCE_WRITE_REG(0, pce_dev->iobase + CRYPTO_AUTH_SEG_START_REG); + } else { + if (creq->op != QCE_REQ_AEAD) + QCE_WRITE_REG(0, pce_dev->iobase + + CRYPTO_AUTH_SEG_CFG_REG); + } + /* + * Ensure previous instructions (write to all AUTH registers) + * was completed before accessing a register that is not in + * in the same 1K range. + */ + mb(); + switch (creq->mode) { + case QCE_MODE_ECB: + if (key_size == AES128_KEY_SIZE) + encr_cfg = pce_dev->reg.encr_cfg_aes_ecb_128; + else + encr_cfg = pce_dev->reg.encr_cfg_aes_ecb_256; + break; + case QCE_MODE_CBC: + if (key_size == AES128_KEY_SIZE) + encr_cfg = pce_dev->reg.encr_cfg_aes_cbc_128; + else + encr_cfg = pce_dev->reg.encr_cfg_aes_cbc_256; + break; + case QCE_MODE_XTS: + if (key_size == AES128_KEY_SIZE) + encr_cfg = pce_dev->reg.encr_cfg_aes_xts_128; + else + encr_cfg = pce_dev->reg.encr_cfg_aes_xts_256; + break; + case QCE_MODE_CCM: + if (key_size == AES128_KEY_SIZE) + encr_cfg = pce_dev->reg.encr_cfg_aes_ccm_128; + else + encr_cfg = pce_dev->reg.encr_cfg_aes_ccm_256; + break; + case QCE_MODE_CTR: + default: + if (key_size == AES128_KEY_SIZE) + encr_cfg = pce_dev->reg.encr_cfg_aes_ctr_128; + else + encr_cfg = pce_dev->reg.encr_cfg_aes_ctr_256; + break; + } + + switch (creq->alg) { + case CIPHER_ALG_DES: + if (creq->mode != QCE_MODE_ECB) { + encr_cfg = pce_dev->reg.encr_cfg_des_cbc; + _byte_stream_to_net_words(enciv32, creq->iv, ivsize); + QCE_WRITE_REG(enciv32[0], pce_dev->iobase + + CRYPTO_CNTR0_IV0_REG); + QCE_WRITE_REG(enciv32[1], pce_dev->iobase + + CRYPTO_CNTR1_IV1_REG); + } else { + encr_cfg = pce_dev->reg.encr_cfg_des_ecb; + } + if (use_hw_key == false) { + QCE_WRITE_REG(enckey32[0], pce_dev->iobase + + CRYPTO_ENCR_KEY0_REG); + QCE_WRITE_REG(enckey32[1], pce_dev->iobase + + CRYPTO_ENCR_KEY1_REG); + } + break; + case CIPHER_ALG_3DES: + if (creq->mode != QCE_MODE_ECB) { + _byte_stream_to_net_words(enciv32, creq->iv, ivsize); + QCE_WRITE_REG(enciv32[0], pce_dev->iobase + + CRYPTO_CNTR0_IV0_REG); + QCE_WRITE_REG(enciv32[1], pce_dev->iobase + + CRYPTO_CNTR1_IV1_REG); + encr_cfg = pce_dev->reg.encr_cfg_3des_cbc; + } else { + encr_cfg = pce_dev->reg.encr_cfg_3des_ecb; + } + if (use_hw_key == false) { + /* write encr key */ + for (i = 0; i < 6; i++) + QCE_WRITE_REG(enckey32[0], (pce_dev->iobase + + (CRYPTO_ENCR_KEY0_REG + i * sizeof(uint32_t)))); + } + break; + case CIPHER_ALG_AES: + default: + if (creq->mode == QCE_MODE_XTS) { + uint32_t xtskey32[MAX_CIPHER_KEY_SIZE/sizeof(uint32_t)] + = {0, 0, 0, 0, 0, 0, 0, 0}; + uint32_t xtsklen = + creq->encklen/(2 * sizeof(uint32_t)); + + if ((use_hw_key == false) && (use_pipe_key == false)) { + _byte_stream_to_net_words(xtskey32, + (creq->enckey + creq->encklen/2), + creq->encklen/2); + /* write xts encr key */ + for (i = 0; i < xtsklen; i++) + QCE_WRITE_REG(xtskey32[i], + pce_dev->iobase + + CRYPTO_ENCR_XTS_KEY0_REG + + (i * sizeof(uint32_t))); + } + /* write xts du size */ + switch (creq->flags & QCRYPTO_CTX_XTS_MASK) { + case QCRYPTO_CTX_XTS_DU_SIZE_512B: + QCE_WRITE_REG( + min((uint32_t)QCE_SECTOR_SIZE, + creq->cryptlen), pce_dev->iobase + + CRYPTO_ENCR_XTS_DU_SIZE_REG); + break; + case QCRYPTO_CTX_XTS_DU_SIZE_1KB: + QCE_WRITE_REG( + min((uint32_t)(QCE_SECTOR_SIZE * 2), + creq->cryptlen), pce_dev->iobase + + CRYPTO_ENCR_XTS_DU_SIZE_REG); + break; + default: + QCE_WRITE_REG(creq->cryptlen, + pce_dev->iobase + + CRYPTO_ENCR_XTS_DU_SIZE_REG); + break; + } + } + if (creq->mode != QCE_MODE_ECB) { + if (creq->mode == QCE_MODE_XTS) + _byte_stream_swap_to_net_words(enciv32, + creq->iv, ivsize); + else + _byte_stream_to_net_words(enciv32, creq->iv, + ivsize); + + /* write encr cntr iv */ + for (i = 0; i <= 3; i++) + QCE_WRITE_REG(enciv32[i], pce_dev->iobase + + CRYPTO_CNTR0_IV0_REG + + (i * sizeof(uint32_t))); + + if (creq->mode == QCE_MODE_CCM) { + /* write cntr iv for ccm */ + for (i = 0; i <= 3; i++) + QCE_WRITE_REG(enciv32[i], + pce_dev->iobase + + CRYPTO_ENCR_CCM_INT_CNTR0_REG + + (i * sizeof(uint32_t))); + /* update cntr_iv[3] by one */ + QCE_WRITE_REG((enciv32[3] + 1), + pce_dev->iobase + + CRYPTO_CNTR0_IV0_REG + + (3 * sizeof(uint32_t))); + } + } + + if (creq->op == QCE_REQ_ABLK_CIPHER_NO_KEY) { + encr_cfg |= (CRYPTO_ENCR_KEY_SZ_AES128 << + CRYPTO_ENCR_KEY_SZ); + } else { + if ((use_hw_key == false) && (use_pipe_key == false)) { + for (i = 0; i < enck_size_in_word; i++) + QCE_WRITE_REG(enckey32[i], + pce_dev->iobase + + CRYPTO_ENCR_KEY0_REG + + (i * sizeof(uint32_t))); + } + } /* else of if (creq->op == QCE_REQ_ABLK_CIPHER_NO_KEY) */ + break; + } /* end of switch (creq->mode) */ + + if (use_pipe_key) + encr_cfg |= (CRYPTO_USE_PIPE_KEY_ENCR_ENABLED + << CRYPTO_USE_PIPE_KEY_ENCR); + + /* write encr seg cfg */ + encr_cfg |= ((creq->dir == QCE_ENCRYPT) ? 1 : 0) << CRYPTO_ENCODE; + if (use_hw_key == true) + encr_cfg |= (CRYPTO_USE_HW_KEY << CRYPTO_USE_HW_KEY_ENCR); + else + encr_cfg &= ~(CRYPTO_USE_HW_KEY << CRYPTO_USE_HW_KEY_ENCR); + /* write encr seg cfg */ + QCE_WRITE_REG(encr_cfg, pce_dev->iobase + CRYPTO_ENCR_SEG_CFG_REG); + + /* write encr seg size */ + if ((creq->mode == QCE_MODE_CCM) && (creq->dir == QCE_DECRYPT)) { + QCE_WRITE_REG((creq->cryptlen + creq->authsize), + pce_dev->iobase + CRYPTO_ENCR_SEG_SIZE_REG); + } else { + QCE_WRITE_REG(creq->cryptlen, + pce_dev->iobase + CRYPTO_ENCR_SEG_SIZE_REG); + } + + /* write encr seg start */ + QCE_WRITE_REG((coffset & 0xffff), + pce_dev->iobase + CRYPTO_ENCR_SEG_START_REG); + + /* write encr counter mask */ + QCE_WRITE_REG(0xffffffff, + pce_dev->iobase + CRYPTO_CNTR_MASK_REG); + QCE_WRITE_REG(0xffffffff, + pce_dev->iobase + CRYPTO_CNTR_MASK_REG0); + QCE_WRITE_REG(0xffffffff, + pce_dev->iobase + CRYPTO_CNTR_MASK_REG1); + QCE_WRITE_REG(0xffffffff, + pce_dev->iobase + CRYPTO_CNTR_MASK_REG2); + + /* write seg size */ + QCE_WRITE_REG(totallen_in, pce_dev->iobase + CRYPTO_SEG_SIZE_REG); + + QCE_WRITE_REG(pce_dev->reg.crypto_cfg_le, (pce_dev->iobase + + CRYPTO_CONFIG_REG)); + /* issue go to crypto */ + if (use_hw_key == false) { + QCE_WRITE_REG(((1 << CRYPTO_GO) | (1 << CRYPTO_RESULTS_DUMP) | + (1 << CRYPTO_CLR_CNTXT)), + pce_dev->iobase + CRYPTO_GOPROC_REG); + } else { + QCE_WRITE_REG(((1 << CRYPTO_GO) | (1 << CRYPTO_RESULTS_DUMP)), + pce_dev->iobase + CRYPTO_GOPROC_QC_KEY_REG); + } + /* + * Ensure previous instructions (setting the GO register) + * was completed before issuing a DMA transfer request + */ + mb(); + return 0; +}; + +static int _ce_f9_setup_direct(struct qce_device *pce_dev, + struct qce_f9_req *req) +{ + uint32_t ikey32[OTA_KEY_SIZE/sizeof(uint32_t)]; + uint32_t key_size_in_word = OTA_KEY_SIZE/sizeof(uint32_t); + uint32_t auth_cfg; + int i; + + switch (req->algorithm) { + case QCE_OTA_ALGO_KASUMI: + auth_cfg = pce_dev->reg.auth_cfg_kasumi; + break; + case QCE_OTA_ALGO_SNOW3G: + default: + auth_cfg = pce_dev->reg.auth_cfg_snow3g; + break; + }; + + /* clear status */ + QCE_WRITE_REG(0, pce_dev->iobase + CRYPTO_STATUS_REG); + + /* set big endian configuration */ + QCE_WRITE_REG(pce_dev->reg.crypto_cfg_be, (pce_dev->iobase + + CRYPTO_CONFIG_REG)); + /* + * Ensure previous instructions (setting the CONFIG register) + * was completed before issuing starting to set other config register + * This is to ensure the configurations are done in correct endian-ness + * as set in the CONFIG registers + */ + mb(); + + /* write enc_seg_cfg */ + QCE_WRITE_REG(0, pce_dev->iobase + CRYPTO_ENCR_SEG_CFG_REG); + + /* write ecn_seg_size */ + QCE_WRITE_REG(0, pce_dev->iobase + CRYPTO_ENCR_SEG_SIZE_REG); + + /* write key in CRYPTO_AUTH_IV0-3_REG */ + _byte_stream_to_net_words(ikey32, &req->ikey[0], OTA_KEY_SIZE); + for (i = 0; i < key_size_in_word; i++) + QCE_WRITE_REG(ikey32[i], (pce_dev->iobase + + (CRYPTO_AUTH_IV0_REG + i*sizeof(uint32_t)))); + + /* write last bits in CRYPTO_AUTH_IV4_REG */ + QCE_WRITE_REG(req->last_bits, (pce_dev->iobase + + CRYPTO_AUTH_IV4_REG)); + + /* write fresh to CRYPTO_AUTH_BYTECNT0_REG */ + QCE_WRITE_REG(req->fresh, (pce_dev->iobase + + CRYPTO_AUTH_BYTECNT0_REG)); + + /* write count-i to CRYPTO_AUTH_BYTECNT1_REG */ + QCE_WRITE_REG(req->count_i, (pce_dev->iobase + + CRYPTO_AUTH_BYTECNT1_REG)); + + /* write auth seg cfg */ + if (req->direction == QCE_OTA_DIR_DOWNLINK) + auth_cfg |= BIT(CRYPTO_F9_DIRECTION); + QCE_WRITE_REG(auth_cfg, pce_dev->iobase + CRYPTO_AUTH_SEG_CFG_REG); + + /* write auth seg size */ + QCE_WRITE_REG(req->msize, pce_dev->iobase + CRYPTO_AUTH_SEG_SIZE_REG); + + /* write auth seg start*/ + QCE_WRITE_REG(0, pce_dev->iobase + CRYPTO_AUTH_SEG_START_REG); + + /* write seg size */ + QCE_WRITE_REG(req->msize, pce_dev->iobase + CRYPTO_SEG_SIZE_REG); + + /* set little endian configuration before go*/ + QCE_WRITE_REG(pce_dev->reg.crypto_cfg_le, (pce_dev->iobase + + CRYPTO_CONFIG_REG)); + /* write go */ + QCE_WRITE_REG(((1 << CRYPTO_GO) | (1 << CRYPTO_RESULTS_DUMP) | + (1 << CRYPTO_CLR_CNTXT)), + pce_dev->iobase + CRYPTO_GOPROC_REG); + /* + * Ensure previous instructions (setting the GO register) + * was completed before issuing a DMA transfer request + */ + mb(); + return 0; +} + +static int _ce_f8_setup_direct(struct qce_device *pce_dev, + struct qce_f8_req *req, bool key_stream_mode, + uint16_t npkts, uint16_t cipher_offset, uint16_t cipher_size) +{ + int i = 0; + uint32_t encr_cfg = 0; + uint32_t ckey32[OTA_KEY_SIZE/sizeof(uint32_t)]; + uint32_t key_size_in_word = OTA_KEY_SIZE/sizeof(uint32_t); + + switch (req->algorithm) { + case QCE_OTA_ALGO_KASUMI: + encr_cfg = pce_dev->reg.encr_cfg_kasumi; + break; + case QCE_OTA_ALGO_SNOW3G: + default: + encr_cfg = pce_dev->reg.encr_cfg_snow3g; + break; + }; + /* clear status */ + QCE_WRITE_REG(0, pce_dev->iobase + CRYPTO_STATUS_REG); + /* set big endian configuration */ + QCE_WRITE_REG(pce_dev->reg.crypto_cfg_be, (pce_dev->iobase + + CRYPTO_CONFIG_REG)); + /* write auth seg configuration */ + QCE_WRITE_REG(0, pce_dev->iobase + CRYPTO_AUTH_SEG_CFG_REG); + /* write auth seg size */ + QCE_WRITE_REG(0, pce_dev->iobase + CRYPTO_AUTH_SEG_SIZE_REG); + + /* write key */ + _byte_stream_to_net_words(ckey32, &req->ckey[0], OTA_KEY_SIZE); + + for (i = 0; i < key_size_in_word; i++) + QCE_WRITE_REG(ckey32[i], (pce_dev->iobase + + (CRYPTO_ENCR_KEY0_REG + i*sizeof(uint32_t)))); + /* write encr seg cfg */ + if (key_stream_mode) + encr_cfg |= BIT(CRYPTO_F8_KEYSTREAM_ENABLE); + if (req->direction == QCE_OTA_DIR_DOWNLINK) + encr_cfg |= BIT(CRYPTO_F8_DIRECTION); + QCE_WRITE_REG(encr_cfg, pce_dev->iobase + + CRYPTO_ENCR_SEG_CFG_REG); + + /* write encr seg start */ + QCE_WRITE_REG((cipher_offset & 0xffff), pce_dev->iobase + + CRYPTO_ENCR_SEG_START_REG); + /* write encr seg size */ + QCE_WRITE_REG(cipher_size, pce_dev->iobase + + CRYPTO_ENCR_SEG_SIZE_REG); + + /* write seg size */ + QCE_WRITE_REG(req->data_len, pce_dev->iobase + + CRYPTO_SEG_SIZE_REG); + + /* write cntr0_iv0 for countC */ + QCE_WRITE_REG(req->count_c, pce_dev->iobase + + CRYPTO_CNTR0_IV0_REG); + /* write cntr1_iv1 for nPkts, and bearer */ + if (npkts == 1) + npkts = 0; + QCE_WRITE_REG(req->bearer << CRYPTO_CNTR1_IV1_REG_F8_BEARER | + npkts << CRYPTO_CNTR1_IV1_REG_F8_PKT_CNT, + pce_dev->iobase + CRYPTO_CNTR1_IV1_REG); + + /* set little endian configuration before go*/ + QCE_WRITE_REG(pce_dev->reg.crypto_cfg_le, (pce_dev->iobase + + CRYPTO_CONFIG_REG)); + /* write go */ + QCE_WRITE_REG(((1 << CRYPTO_GO) | (1 << CRYPTO_RESULTS_DUMP) | + (1 << CRYPTO_CLR_CNTXT)), + pce_dev->iobase + CRYPTO_GOPROC_REG); + /* + * Ensure previous instructions (setting the GO register) + * was completed before issuing a DMA transfer request + */ + mb(); + return 0; +} + + +static int _qce_unlock_other_pipes(struct qce_device *pce_dev, int req_info) +{ + int rc = 0; + struct ce_sps_data *pce_sps_data = &pce_dev->ce_request_info + [req_info].ce_sps; + + if (pce_dev->no_get_around || pce_dev->support_cmd_dscr == false) + return rc; + + rc = sps_transfer_one(pce_dev->ce_bam_info.consumer.pipe, + GET_PHYS_ADDR(pce_sps_data-> + cmdlistptr.unlock_all_pipes.cmdlist), + 0, NULL, (SPS_IOVEC_FLAG_CMD | SPS_IOVEC_FLAG_UNLOCK)); + if (rc) { + pr_err("sps_xfr_one() fail rc=%d", rc); + rc = -EINVAL; + } + return rc; +} + +static inline void qce_free_req_info(struct qce_device *pce_dev, int req_info, + bool is_complete); + +static int _aead_complete(struct qce_device *pce_dev, int req_info) +{ + struct aead_request *areq; + unsigned char mac[SHA256_DIGEST_SIZE]; + uint32_t ccm_fail_status = 0; + uint32_t result_dump_status; + int32_t result_status = 0; + struct ce_request_info *preq_info; + struct ce_sps_data *pce_sps_data; + qce_comp_func_ptr_t qce_callback; + + preq_info = &pce_dev->ce_request_info[req_info]; + pce_sps_data = &preq_info->ce_sps; + qce_callback = preq_info->qce_cb; + areq = (struct aead_request *) preq_info->areq; + if (areq->src != areq->dst) { + qce_dma_unmap_sg(pce_dev->pdev, areq->dst, preq_info->dst_nents, + DMA_FROM_DEVICE); + } + qce_dma_unmap_sg(pce_dev->pdev, areq->src, preq_info->src_nents, + (areq->src == areq->dst) ? DMA_BIDIRECTIONAL : + DMA_TO_DEVICE); + + if (preq_info->asg) + qce_dma_unmap_sg(pce_dev->pdev, preq_info->asg, + preq_info->assoc_nents, DMA_TO_DEVICE); + /* check MAC */ + memcpy(mac, (char *)(&pce_sps_data->result->auth_iv[0]), + SHA256_DIGEST_SIZE); + + /* read status before unlock */ + if (preq_info->dir == QCE_DECRYPT) { + if (pce_dev->no_get_around) + if (pce_dev->no_ccm_mac_status_get_around) + ccm_fail_status = be32_to_cpu(pce_sps_data-> + result->status); + else + ccm_fail_status = be32_to_cpu(pce_sps_data-> + result_null->status); + else + ccm_fail_status = readl_relaxed(pce_dev->iobase + + CRYPTO_STATUS_REG); + } + if (_qce_unlock_other_pipes(pce_dev, req_info)) { + qce_free_req_info(pce_dev, req_info, true); + qce_callback(areq, mac, NULL, -ENXIO); + return -ENXIO; + } + result_dump_status = be32_to_cpu(pce_sps_data->result->status); + pce_sps_data->result->status = 0; + + if (result_dump_status & ((1 << CRYPTO_SW_ERR) | (1 << CRYPTO_AXI_ERR) + | (1 << CRYPTO_HSD_ERR))) { + pr_err("aead operation error. Status %x\n", result_dump_status); + result_status = -ENXIO; + } else if (pce_sps_data->consumer_status | + pce_sps_data->producer_status) { + pr_err("aead sps operation error. sps status %x %x\n", + pce_sps_data->consumer_status, + pce_sps_data->producer_status); + result_status = -ENXIO; + } + + if (preq_info->mode == QCE_MODE_CCM) { + /* + * Not from result dump, instead, use the status we just + * read of device for MAC_FAILED. + */ + if (result_status == 0 && (preq_info->dir == QCE_DECRYPT) && + (ccm_fail_status & (1 << CRYPTO_MAC_FAILED))) + result_status = -EBADMSG; + qce_free_req_info(pce_dev, req_info, true); + qce_callback(areq, mac, NULL, result_status); + + } else { + uint32_t ivsize = 0; + struct crypto_aead *aead; + unsigned char iv[NUM_OF_CRYPTO_CNTR_IV_REG * CRYPTO_REG_SIZE]; + aead = crypto_aead_reqtfm(areq); + ivsize = crypto_aead_ivsize(aead); + memcpy(iv, (char *)(pce_sps_data->result->encr_cntr_iv), + sizeof(iv)); + qce_free_req_info(pce_dev, req_info, true); + qce_callback(areq, mac, iv, result_status); + + } + return 0; +}; + +static int _sha_complete(struct qce_device *pce_dev, int req_info) +{ + struct ahash_request *areq; + unsigned char digest[SHA256_DIGEST_SIZE]; + uint32_t bytecount32[2]; + int32_t result_status = 0; + uint32_t result_dump_status; + struct ce_request_info *preq_info; + struct ce_sps_data *pce_sps_data; + qce_comp_func_ptr_t qce_callback; + + preq_info = &pce_dev->ce_request_info[req_info]; + pce_sps_data = &preq_info->ce_sps; + qce_callback = preq_info->qce_cb; + areq = (struct ahash_request *) preq_info->areq; + if (!areq) { + pr_err("sha operation error. areq is NULL\n"); + return -ENXIO; + } + qce_dma_unmap_sg(pce_dev->pdev, areq->src, preq_info->src_nents, + DMA_TO_DEVICE); + memcpy(digest, (char *)(&pce_sps_data->result->auth_iv[0]), + SHA256_DIGEST_SIZE); + _byte_stream_to_net_words(bytecount32, + (unsigned char *)pce_sps_data->result->auth_byte_count, + 2 * CRYPTO_REG_SIZE); + + if (_qce_unlock_other_pipes(pce_dev, req_info)) { + qce_free_req_info(pce_dev, req_info, true); + qce_callback(areq, digest, (char *)bytecount32, + -ENXIO); + return -ENXIO; + } + + result_dump_status = be32_to_cpu(pce_sps_data->result->status); + pce_sps_data->result->status = 0; + if (result_dump_status & ((1 << CRYPTO_SW_ERR) | (1 << CRYPTO_AXI_ERR) + | (1 << CRYPTO_HSD_ERR))) { + + pr_err("sha operation error. Status %x\n", result_dump_status); + result_status = -ENXIO; + } else if (pce_sps_data->consumer_status) { + pr_err("sha sps operation error. sps status %x\n", + pce_sps_data->consumer_status); + result_status = -ENXIO; + } + qce_free_req_info(pce_dev, req_info, true); + qce_callback(areq, digest, (char *)bytecount32, result_status); + return 0; +} + +static int _f9_complete(struct qce_device *pce_dev, int req_info) +{ + uint32_t mac_i; + int32_t result_status = 0; + uint32_t result_dump_status; + struct ce_request_info *preq_info; + struct ce_sps_data *pce_sps_data; + qce_comp_func_ptr_t qce_callback; + void *areq; + + preq_info = &pce_dev->ce_request_info[req_info]; + pce_sps_data = &preq_info->ce_sps; + qce_callback = preq_info->qce_cb; + areq = preq_info->areq; + dma_unmap_single(pce_dev->pdev, preq_info->phy_ota_src, + preq_info->ota_size, DMA_TO_DEVICE); + _byte_stream_to_net_words(&mac_i, + (char *)(&pce_sps_data->result->auth_iv[0]), + CRYPTO_REG_SIZE); + + if (_qce_unlock_other_pipes(pce_dev, req_info)) { + qce_free_req_info(pce_dev, req_info, true); + qce_callback(areq, NULL, NULL, -ENXIO); + return -ENXIO; + } + + result_dump_status = be32_to_cpu(pce_sps_data->result->status); + pce_sps_data->result->status = 0; + if (result_dump_status & ((1 << CRYPTO_SW_ERR) | (1 << CRYPTO_AXI_ERR) + | (1 << CRYPTO_HSD_ERR))) { + pr_err("f9 operation error. Status %x\n", result_dump_status); + result_status = -ENXIO; + } else if (pce_sps_data->consumer_status | + pce_sps_data->producer_status) { + pr_err("f9 sps operation error. sps status %x %x\n", + pce_sps_data->consumer_status, + pce_sps_data->producer_status); + result_status = -ENXIO; + } + qce_free_req_info(pce_dev, req_info, true); + qce_callback(areq, (char *)&mac_i, NULL, result_status); + + return 0; +} + +static int _ablk_cipher_complete(struct qce_device *pce_dev, int req_info) +{ + struct ablkcipher_request *areq; + unsigned char iv[NUM_OF_CRYPTO_CNTR_IV_REG * CRYPTO_REG_SIZE]; + int32_t result_status = 0; + uint32_t result_dump_status; + struct ce_request_info *preq_info; + struct ce_sps_data *pce_sps_data; + qce_comp_func_ptr_t qce_callback; + + preq_info = &pce_dev->ce_request_info[req_info]; + pce_sps_data = &preq_info->ce_sps; + qce_callback = preq_info->qce_cb; + areq = (struct ablkcipher_request *) preq_info->areq; + if (areq->src != areq->dst) { + qce_dma_unmap_sg(pce_dev->pdev, areq->dst, + preq_info->dst_nents, DMA_FROM_DEVICE); + } + qce_dma_unmap_sg(pce_dev->pdev, areq->src, preq_info->src_nents, + (areq->src == areq->dst) ? DMA_BIDIRECTIONAL : + DMA_TO_DEVICE); + + if (_qce_unlock_other_pipes(pce_dev, req_info)) { + qce_free_req_info(pce_dev, req_info, true); + qce_callback(areq, NULL, NULL, -ENXIO); + return -ENXIO; + } + result_dump_status = be32_to_cpu(pce_sps_data->result->status); + pce_sps_data->result->status = 0; + + if (result_dump_status & ((1 << CRYPTO_SW_ERR) | (1 << CRYPTO_AXI_ERR) + | (1 << CRYPTO_HSD_ERR))) { + pr_err("ablk_cipher operation error. Status %x\n", + result_dump_status); + result_status = -ENXIO; + } else if (pce_sps_data->consumer_status | + pce_sps_data->producer_status) { + pr_err("ablk_cipher sps operation error. sps status %x %x\n", + pce_sps_data->consumer_status, + pce_sps_data->producer_status); + result_status = -ENXIO; + } + + if (preq_info->mode == QCE_MODE_ECB) { + qce_free_req_info(pce_dev, req_info, true); + qce_callback(areq, NULL, NULL, pce_sps_data->consumer_status | + result_status); + } else { + if (pce_dev->ce_bam_info.minor_version == 0) { + if (preq_info->mode == QCE_MODE_CBC) { + if (preq_info->dir == QCE_DECRYPT) + memcpy(iv, (char *)preq_info->dec_iv, + sizeof(iv)); + else + memcpy(iv, (unsigned char *) + (sg_virt(areq->src) + + areq->src->length - 16), + sizeof(iv)); + } + if ((preq_info->mode == QCE_MODE_CTR) || + (preq_info->mode == QCE_MODE_XTS)) { + uint32_t num_blk = 0; + uint32_t cntr_iv3 = 0; + unsigned long long cntr_iv64 = 0; + unsigned char *b = (unsigned char *)(&cntr_iv3); + + memcpy(iv, areq->info, sizeof(iv)); + if (preq_info->mode != QCE_MODE_XTS) + num_blk = areq->nbytes/16; + else + num_blk = 1; + cntr_iv3 = ((*(iv + 12) << 24) & 0xff000000) | + (((*(iv + 13)) << 16) & 0xff0000) | + (((*(iv + 14)) << 8) & 0xff00) | + (*(iv + 15) & 0xff); + cntr_iv64 = + (((unsigned long long)cntr_iv3 & + (unsigned long long)0xFFFFFFFFULL) + + (unsigned long long)num_blk) % + (unsigned long long)(0x100000000ULL); + + cntr_iv3 = (u32)(cntr_iv64 & 0xFFFFFFFF); + *(iv + 15) = (char)(*b); + *(iv + 14) = (char)(*(b + 1)); + *(iv + 13) = (char)(*(b + 2)); + *(iv + 12) = (char)(*(b + 3)); + } + } else { + memcpy(iv, + (char *)(pce_sps_data->result->encr_cntr_iv), + sizeof(iv)); + } + qce_free_req_info(pce_dev, req_info, true); + qce_callback(areq, NULL, iv, result_status); + } + return 0; +} + +static int _f8_complete(struct qce_device *pce_dev, int req_info) +{ + int32_t result_status = 0; + uint32_t result_dump_status; + uint32_t result_dump_status2; + struct ce_request_info *preq_info; + struct ce_sps_data *pce_sps_data; + qce_comp_func_ptr_t qce_callback; + void *areq; + + preq_info = &pce_dev->ce_request_info[req_info]; + pce_sps_data = &preq_info->ce_sps; + qce_callback = preq_info->qce_cb; + areq = preq_info->areq; + if (preq_info->phy_ota_dst) + dma_unmap_single(pce_dev->pdev, preq_info->phy_ota_dst, + preq_info->ota_size, DMA_FROM_DEVICE); + if (preq_info->phy_ota_src) + dma_unmap_single(pce_dev->pdev, preq_info->phy_ota_src, + preq_info->ota_size, (preq_info->phy_ota_dst) ? + DMA_TO_DEVICE : DMA_BIDIRECTIONAL); + + if (_qce_unlock_other_pipes(pce_dev, req_info)) { + qce_free_req_info(pce_dev, req_info, true); + qce_callback(areq, NULL, NULL, -ENXIO); + return -ENXIO; + } + result_dump_status = be32_to_cpu(pce_sps_data->result->status); + result_dump_status2 = be32_to_cpu(pce_sps_data->result->status2); + + if ((result_dump_status & ((1 << CRYPTO_SW_ERR) | (1 << CRYPTO_AXI_ERR) + | (1 << CRYPTO_HSD_ERR)))) { + pr_err( + "f8 oper error. Dump Sta %x Sta2 %x req %d\n", + result_dump_status, result_dump_status2, req_info); + result_status = -ENXIO; + } else if (pce_sps_data->consumer_status | + pce_sps_data->producer_status) { + pr_err("f8 sps operation error. sps status %x %x\n", + pce_sps_data->consumer_status, + pce_sps_data->producer_status); + result_status = -ENXIO; + } + pce_sps_data->result->status = 0; + pce_sps_data->result->status2 = 0; + qce_free_req_info(pce_dev, req_info, true); + qce_callback(areq, NULL, NULL, result_status); + return 0; +} + +static void _qce_sps_iovec_count_init(struct qce_device *pce_dev, int req_info) +{ + struct ce_sps_data *pce_sps_data = &pce_dev->ce_request_info[req_info] + .ce_sps; + pce_sps_data->in_transfer.iovec_count = 0; + pce_sps_data->out_transfer.iovec_count = 0; +} + +static void _qce_set_flag(struct sps_transfer *sps_bam_pipe, uint32_t flag) +{ + struct sps_iovec *iovec; + + if (sps_bam_pipe->iovec_count == 0) + return; + iovec = sps_bam_pipe->iovec + (sps_bam_pipe->iovec_count - 1); + iovec->flags |= flag; +} + +static int _qce_sps_add_data(dma_addr_t paddr, uint32_t len, + struct sps_transfer *sps_bam_pipe) +{ + struct sps_iovec *iovec = sps_bam_pipe->iovec + + sps_bam_pipe->iovec_count; + uint32_t data_cnt; + + while (len > 0) { + if (sps_bam_pipe->iovec_count == QCE_MAX_NUM_DSCR) { + pr_err("Num of descrptor %d exceed max (%d)", + sps_bam_pipe->iovec_count, + (uint32_t)QCE_MAX_NUM_DSCR); + return -ENOMEM; + } + if (len > SPS_MAX_PKT_SIZE) + data_cnt = SPS_MAX_PKT_SIZE; + else + data_cnt = len; + iovec->size = data_cnt; + iovec->addr = SPS_GET_LOWER_ADDR(paddr); + iovec->flags = SPS_GET_UPPER_ADDR(paddr); + sps_bam_pipe->iovec_count++; + iovec++; + paddr += data_cnt; + len -= data_cnt; + } + return 0; +} + +static int _qce_sps_add_sg_data(struct qce_device *pce_dev, + struct scatterlist *sg_src, uint32_t nbytes, + struct sps_transfer *sps_bam_pipe) +{ + uint32_t data_cnt, len; + dma_addr_t addr; + struct sps_iovec *iovec = sps_bam_pipe->iovec + + sps_bam_pipe->iovec_count; + + if (!sg_src) + return -ENOENT; + + while (nbytes > 0) { + len = min(nbytes, sg_dma_len(sg_src)); + nbytes -= len; + addr = sg_dma_address(sg_src); + if (pce_dev->ce_bam_info.minor_version == 0) + len = ALIGN(len, pce_dev->ce_bam_info.ce_burst_size); + while (len > 0) { + if (sps_bam_pipe->iovec_count == QCE_MAX_NUM_DSCR) { + pr_err("Num of descrptor %d exceed max (%d)", + sps_bam_pipe->iovec_count, + (uint32_t)QCE_MAX_NUM_DSCR); + return -ENOMEM; + } + if (len > SPS_MAX_PKT_SIZE) { + data_cnt = SPS_MAX_PKT_SIZE; + iovec->size = data_cnt; + iovec->addr = SPS_GET_LOWER_ADDR(addr); + iovec->flags = SPS_GET_UPPER_ADDR(addr); + } else { + data_cnt = len; + iovec->size = data_cnt; + iovec->addr = SPS_GET_LOWER_ADDR(addr); + iovec->flags = SPS_GET_UPPER_ADDR(addr); + } + iovec++; + sps_bam_pipe->iovec_count++; + addr += data_cnt; + len -= data_cnt; + } + sg_src = sg_next(sg_src); + } + return 0; +} + +static int _qce_sps_add_sg_data_off(struct qce_device *pce_dev, + struct scatterlist *sg_src, uint32_t nbytes, uint32_t off, + struct sps_transfer *sps_bam_pipe) +{ + uint32_t data_cnt, len; + dma_addr_t addr; + struct sps_iovec *iovec = sps_bam_pipe->iovec + + sps_bam_pipe->iovec_count; + unsigned int res_within_sg; + + if (!sg_src) + return -ENOENT; + res_within_sg = sg_dma_len(sg_src); + + while (off > 0) { + if (!sg_src) { + pr_err("broken sg list off %d nbytes %d\n", + off, nbytes); + return -ENOENT; + } + len = sg_dma_len(sg_src); + if (off < len) { + res_within_sg = len - off; + break; + } + off -= len; + sg_src = sg_next(sg_src); + if (sg_src) + res_within_sg = sg_dma_len(sg_src); + } + while (nbytes > 0 && sg_src) { + len = min(nbytes, res_within_sg); + nbytes -= len; + addr = sg_dma_address(sg_src) + off; + if (pce_dev->ce_bam_info.minor_version == 0) + len = ALIGN(len, pce_dev->ce_bam_info.ce_burst_size); + while (len > 0) { + if (sps_bam_pipe->iovec_count == QCE_MAX_NUM_DSCR) { + pr_err("Num of descrptor %d exceed max (%d)", + sps_bam_pipe->iovec_count, + (uint32_t)QCE_MAX_NUM_DSCR); + return -ENOMEM; + } + if (len > SPS_MAX_PKT_SIZE) { + data_cnt = SPS_MAX_PKT_SIZE; + iovec->size = data_cnt; + iovec->addr = SPS_GET_LOWER_ADDR(addr); + iovec->flags = SPS_GET_UPPER_ADDR(addr); + } else { + data_cnt = len; + iovec->size = data_cnt; + iovec->addr = SPS_GET_LOWER_ADDR(addr); + iovec->flags = SPS_GET_UPPER_ADDR(addr); + } + iovec++; + sps_bam_pipe->iovec_count++; + addr += data_cnt; + len -= data_cnt; + } + if (nbytes) { + sg_src = sg_next(sg_src); + if (!sg_src) { + pr_err("more data bytes %d\n", nbytes); + return -ENOMEM; + } + res_within_sg = sg_dma_len(sg_src); + off = 0; + } + } + return 0; +} + +static int _qce_sps_add_cmd(struct qce_device *pce_dev, uint32_t flag, + struct qce_cmdlist_info *cmdptr, + struct sps_transfer *sps_bam_pipe) +{ + dma_addr_t paddr = GET_PHYS_ADDR(cmdptr->cmdlist); + struct sps_iovec *iovec = sps_bam_pipe->iovec + + sps_bam_pipe->iovec_count; + iovec->size = cmdptr->size; + iovec->addr = SPS_GET_LOWER_ADDR(paddr); + iovec->flags = SPS_GET_UPPER_ADDR(paddr) | SPS_IOVEC_FLAG_CMD | flag; + sps_bam_pipe->iovec_count++; + if (sps_bam_pipe->iovec_count >= QCE_MAX_NUM_DSCR) { + pr_err("Num of descrptor %d exceed max (%d)", + sps_bam_pipe->iovec_count, (uint32_t)QCE_MAX_NUM_DSCR); + return -ENOMEM; + } + return 0; +} + +static int _qce_sps_transfer(struct qce_device *pce_dev, int req_info) +{ + int rc = 0; + struct ce_sps_data *pce_sps_data; + + pce_sps_data = &pce_dev->ce_request_info[req_info].ce_sps; + pce_sps_data->out_transfer.user = + (void *)((uintptr_t)(CRYPTO_REQ_USER_PAT | + (unsigned int) req_info)); + pce_sps_data->in_transfer.user = + (void *)((uintptr_t)(CRYPTO_REQ_USER_PAT | + (unsigned int) req_info)); + _qce_dump_descr_fifos_dbg(pce_dev, req_info); + + if (pce_sps_data->in_transfer.iovec_count) { + rc = sps_transfer(pce_dev->ce_bam_info.consumer.pipe, + &pce_sps_data->in_transfer); + if (rc) { + pr_err("sps_xfr() fail (consumer pipe=0x%lx) rc = %d\n", + (uintptr_t)pce_dev->ce_bam_info.consumer.pipe, + rc); + goto ret; + } + } + rc = sps_transfer(pce_dev->ce_bam_info.producer.pipe, + &pce_sps_data->out_transfer); + if (rc) + pr_err("sps_xfr() fail (producer pipe=0x%lx) rc = %d\n", + (uintptr_t)pce_dev->ce_bam_info.producer.pipe, rc); +ret: + if (rc) + _qce_dump_descr_fifos(pce_dev, req_info); + return rc; +} + +/** + * Allocate and Connect a CE peripheral's SPS endpoint + * + * This function allocates endpoint context and + * connect it with memory endpoint by calling + * appropriate SPS driver APIs. + * + * Also registers a SPS callback function with + * SPS driver + * + * This function should only be called once typically + * during driver probe. + * + * @pce_dev - Pointer to qce_device structure + * @ep - Pointer to sps endpoint data structure + * @is_produce - 1 means Producer endpoint + * 0 means Consumer endpoint + * + * @return - 0 if successful else negative value. + * + */ +static int qce_sps_init_ep_conn(struct qce_device *pce_dev, + struct qce_sps_ep_conn_data *ep, + bool is_producer) +{ + int rc = 0; + struct sps_pipe *sps_pipe_info; + struct sps_connect *sps_connect_info = &ep->connect; + struct sps_register_event *sps_event = &ep->event; + + /* Allocate endpoint context */ + sps_pipe_info = sps_alloc_endpoint(); + if (!sps_pipe_info) { + pr_err("sps_alloc_endpoint() failed!!! is_producer=%d", + is_producer); + rc = -ENOMEM; + goto out; + } + /* Now save the sps pipe handle */ + ep->pipe = sps_pipe_info; + + /* Get default connection configuration for an endpoint */ + rc = sps_get_config(sps_pipe_info, sps_connect_info); + if (rc) { + pr_err("sps_get_config() fail pipe_handle=0x%lx, rc = %d\n", + (uintptr_t)sps_pipe_info, rc); + goto get_config_err; + } + + /* Modify the default connection configuration */ + if (is_producer) { + /* + * For CE producer transfer, source should be + * CE peripheral where as destination should + * be system memory. + */ + sps_connect_info->source = pce_dev->ce_bam_info.bam_handle; + sps_connect_info->destination = SPS_DEV_HANDLE_MEM; + /* Producer pipe will handle this connection */ + sps_connect_info->mode = SPS_MODE_SRC; + sps_connect_info->options = + SPS_O_AUTO_ENABLE | SPS_O_DESC_DONE; + } else { + /* For CE consumer transfer, source should be + * system memory where as destination should + * CE peripheral + */ + sps_connect_info->source = SPS_DEV_HANDLE_MEM; + sps_connect_info->destination = pce_dev->ce_bam_info.bam_handle; + sps_connect_info->mode = SPS_MODE_DEST; + sps_connect_info->options = + SPS_O_AUTO_ENABLE; + } + + /* Producer pipe index */ + sps_connect_info->src_pipe_index = + pce_dev->ce_bam_info.src_pipe_index; + /* Consumer pipe index */ + sps_connect_info->dest_pipe_index = + pce_dev->ce_bam_info.dest_pipe_index; + /* Set pipe group */ + sps_connect_info->lock_group = pce_dev->ce_bam_info.pipe_pair_index; + sps_connect_info->event_thresh = 0x10; + /* + * Max. no of scatter/gather buffers that can + * be passed by block layer = 32 (NR_SG). + * Each BAM descritor needs 64 bits (8 bytes). + * One BAM descriptor is required per buffer transfer. + * So we would require total 256 (32 * 8) bytes of descriptor FIFO. + * But due to HW limitation we need to allocate atleast one extra + * descriptor memory (256 bytes + 8 bytes). But in order to be + * in power of 2, we are allocating 512 bytes of memory. + */ + sps_connect_info->desc.size = QCE_MAX_NUM_DSCR * MAX_QCE_ALLOC_BAM_REQ * + sizeof(struct sps_iovec); + if (sps_connect_info->desc.size > MAX_SPS_DESC_FIFO_SIZE) + sps_connect_info->desc.size = MAX_SPS_DESC_FIFO_SIZE; + sps_connect_info->desc.base = dma_alloc_coherent(pce_dev->pdev, + sps_connect_info->desc.size, + &sps_connect_info->desc.phys_base, + GFP_KERNEL); + if (sps_connect_info->desc.base == NULL) { + rc = -ENOMEM; + pr_err("Can not allocate coherent memory for sps data\n"); + goto get_config_err; + } + + memset(sps_connect_info->desc.base, 0x00, sps_connect_info->desc.size); + + /* Establish connection between peripheral and memory endpoint */ + rc = sps_connect(sps_pipe_info, sps_connect_info); + if (rc) { + pr_err("sps_connect() fail pipe_handle=0x%lx, rc = %d\n", + (uintptr_t)sps_pipe_info, rc); + goto sps_connect_err; + } + + sps_event->mode = SPS_TRIGGER_CALLBACK; + sps_event->xfer_done = NULL; + sps_event->user = (void *)pce_dev; + if (is_producer) { + sps_event->options = SPS_O_EOT | SPS_O_DESC_DONE; + sps_event->callback = _sps_producer_callback; + rc = sps_register_event(ep->pipe, sps_event); + if (rc) { + pr_err("Producer callback registration failed rc=%d\n", + rc); + goto sps_connect_err; + } + } else { + sps_event->options = SPS_O_EOT; + sps_event->callback = NULL; + } + + pr_debug("success, %s : pipe_handle=0x%lx, desc fifo base (phy) = 0x%pK\n", + is_producer ? "PRODUCER(RX/OUT)" : "CONSUMER(TX/IN)", + (uintptr_t)sps_pipe_info, &sps_connect_info->desc.phys_base); + goto out; + +sps_connect_err: + dma_free_coherent(pce_dev->pdev, + sps_connect_info->desc.size, + sps_connect_info->desc.base, + sps_connect_info->desc.phys_base); +get_config_err: + sps_free_endpoint(sps_pipe_info); +out: + return rc; +} + +/** + * Disconnect and Deallocate a CE peripheral's SPS endpoint + * + * This function disconnect endpoint and deallocates + * endpoint context. + * + * This function should only be called once typically + * during driver remove. + * + * @pce_dev - Pointer to qce_device structure + * @ep - Pointer to sps endpoint data structure + * + */ +static void qce_sps_exit_ep_conn(struct qce_device *pce_dev, + struct qce_sps_ep_conn_data *ep) +{ + struct sps_pipe *sps_pipe_info = ep->pipe; + struct sps_connect *sps_connect_info = &ep->connect; + + sps_disconnect(sps_pipe_info); + dma_free_coherent(pce_dev->pdev, + sps_connect_info->desc.size, + sps_connect_info->desc.base, + sps_connect_info->desc.phys_base); + sps_free_endpoint(sps_pipe_info); +} + +static void qce_sps_release_bam(struct qce_device *pce_dev) +{ + struct bam_registration_info *pbam; + + mutex_lock(&bam_register_lock); + pbam = pce_dev->pbam; + if (pbam == NULL) + goto ret; + + pbam->cnt--; + if (pbam->cnt > 0) + goto ret; + + if (pce_dev->ce_bam_info.bam_handle) { + sps_deregister_bam_device(pce_dev->ce_bam_info.bam_handle); + + pr_debug("deregister bam handle 0x%lx\n", + pce_dev->ce_bam_info.bam_handle); + pce_dev->ce_bam_info.bam_handle = 0; + } + iounmap(pbam->bam_iobase); + pr_debug("delete bam 0x%x\n", pbam->bam_mem); + list_del(&pbam->qlist); + kfree(pbam); + +ret: + pce_dev->pbam = NULL; + mutex_unlock(&bam_register_lock); +} + +static int qce_sps_get_bam(struct qce_device *pce_dev) +{ + int rc = 0; + struct sps_bam_props bam = {0}; + struct bam_registration_info *pbam = NULL; + struct bam_registration_info *p; + uint32_t bam_cfg = 0; + + + mutex_lock(&bam_register_lock); + + list_for_each_entry(p, &qce50_bam_list, qlist) { + if (p->bam_mem == pce_dev->bam_mem) { + pbam = p; /* found */ + break; + } + } + + if (pbam) { + pr_debug("found bam 0x%x\n", pbam->bam_mem); + pbam->cnt++; + pce_dev->ce_bam_info.bam_handle = pbam->handle; + pce_dev->ce_bam_info.bam_mem = pbam->bam_mem; + pce_dev->ce_bam_info.bam_iobase = pbam->bam_iobase; + pce_dev->pbam = pbam; + pce_dev->support_cmd_dscr = pbam->support_cmd_dscr; + goto ret; + } + + pbam = kzalloc(sizeof(struct bam_registration_info), GFP_KERNEL); + if (!pbam) { + pr_err("qce50 Memory allocation of bam FAIL, error %ld\n", + PTR_ERR(pbam)); + + rc = -ENOMEM; + goto ret; + } + pbam->cnt = 1; + pbam->bam_mem = pce_dev->bam_mem; + pbam->bam_iobase = ioremap_nocache(pce_dev->bam_mem, + pce_dev->bam_mem_size); + if (!pbam->bam_iobase) { + kfree(pbam); + rc = -ENOMEM; + pr_err("Can not map BAM io memory\n"); + goto ret; + } + pce_dev->ce_bam_info.bam_mem = pbam->bam_mem; + pce_dev->ce_bam_info.bam_iobase = pbam->bam_iobase; + pbam->handle = 0; + pr_debug("allocate bam 0x%x\n", pbam->bam_mem); + bam_cfg = readl_relaxed(pce_dev->ce_bam_info.bam_iobase + + CRYPTO_BAM_CNFG_BITS_REG); + pbam->support_cmd_dscr = (bam_cfg & CRYPTO_BAM_CD_ENABLE_MASK) ? + true : false; + if (pbam->support_cmd_dscr == false) { + pr_info("qce50 don't support command descriptor. bam_cfg%x\n", + bam_cfg); + pce_dev->no_get_around = false; + } + pce_dev->support_cmd_dscr = pbam->support_cmd_dscr; + + bam.phys_addr = pce_dev->ce_bam_info.bam_mem; + bam.virt_addr = pce_dev->ce_bam_info.bam_iobase; + + /* + * This event thresold value is only significant for BAM-to-BAM + * transfer. It's ignored for BAM-to-System mode transfer. + */ + bam.event_threshold = 0x10; /* Pipe event threshold */ + /* + * This threshold controls when the BAM publish + * the descriptor size on the sideband interface. + * SPS HW will only be used when + * data transfer size > 64 bytes. + */ + bam.summing_threshold = 64; + /* SPS driver wll handle the crypto BAM IRQ */ + bam.irq = (u32)pce_dev->ce_bam_info.bam_irq; + /* + * Set flag to indicate BAM global device control is managed + * remotely. + */ + if ((pce_dev->support_cmd_dscr == false) || (pce_dev->is_shared)) + bam.manage = SPS_BAM_MGR_DEVICE_REMOTE; + else + bam.manage = SPS_BAM_MGR_LOCAL; + + bam.ee = pce_dev->ce_bam_info.bam_ee; + bam.ipc_loglevel = QCE_BAM_DEFAULT_IPC_LOGLVL; + bam.options |= SPS_BAM_CACHED_WP; + pr_debug("bam physical base=0x%lx\n", (uintptr_t)bam.phys_addr); + pr_debug("bam virtual base=0x%pK\n", bam.virt_addr); + + /* Register CE Peripheral BAM device to SPS driver */ + rc = sps_register_bam_device(&bam, &pbam->handle); + if (rc) { + pr_err("sps_register_bam_device() failed! err=%d", rc); + rc = -EIO; + iounmap(pbam->bam_iobase); + kfree(pbam); + goto ret; + } + + pce_dev->pbam = pbam; + list_add_tail(&pbam->qlist, &qce50_bam_list); + pce_dev->ce_bam_info.bam_handle = pbam->handle; + +ret: + mutex_unlock(&bam_register_lock); + + return rc; +} +/** + * Initialize SPS HW connected with CE core + * + * This function register BAM HW resources with + * SPS driver and then initialize 2 SPS endpoints + * + * This function should only be called once typically + * during driver probe. + * + * @pce_dev - Pointer to qce_device structure + * + * @return - 0 if successful else negative value. + * + */ +static int qce_sps_init(struct qce_device *pce_dev) +{ + int rc = 0; + + rc = qce_sps_get_bam(pce_dev); + if (rc) + return rc; + pr_debug("BAM device registered. bam_handle=0x%lx\n", + pce_dev->ce_bam_info.bam_handle); + + rc = qce_sps_init_ep_conn(pce_dev, + &pce_dev->ce_bam_info.producer, true); + if (rc) + goto sps_connect_producer_err; + rc = qce_sps_init_ep_conn(pce_dev, + &pce_dev->ce_bam_info.consumer, false); + if (rc) + goto sps_connect_consumer_err; + + pr_info(" Qualcomm MSM CE-BAM at 0x%016llx irq %d\n", + (unsigned long long)pce_dev->ce_bam_info.bam_mem, + (unsigned int)pce_dev->ce_bam_info.bam_irq); + return rc; + +sps_connect_consumer_err: + qce_sps_exit_ep_conn(pce_dev, &pce_dev->ce_bam_info.producer); +sps_connect_producer_err: + qce_sps_release_bam(pce_dev); + return rc; +} + +static inline int qce_alloc_req_info(struct qce_device *pce_dev) +{ + int i; + int request_index = pce_dev->ce_request_index; + + for (i = 0; i < MAX_QCE_BAM_REQ; i++) { + request_index++; + if (request_index >= MAX_QCE_BAM_REQ) + request_index = 0; + if (atomic_xchg(&pce_dev->ce_request_info[request_index]. + in_use, true) == false) { + pce_dev->ce_request_index = request_index; + return request_index; + } + } + pr_warn("pcedev %d no reqs available no_of_queued_req %d\n", + pce_dev->dev_no, atomic_read( + &pce_dev->no_of_queued_req)); + return -EBUSY; +} + +static inline void qce_free_req_info(struct qce_device *pce_dev, int req_info, + bool is_complete) +{ + pce_dev->ce_request_info[req_info].xfer_type = QCE_XFER_TYPE_LAST; + if (atomic_xchg(&pce_dev->ce_request_info[req_info].in_use, + false) == true) { + if (req_info < MAX_QCE_BAM_REQ && is_complete) + atomic_dec(&pce_dev->no_of_queued_req); + } else + pr_warn("request info %d free already\n", req_info); +} + +static void print_notify_debug(struct sps_event_notify *notify) +{ + phys_addr_t addr = + DESC_FULL_ADDR((phys_addr_t) notify->data.transfer.iovec.flags, + notify->data.transfer.iovec.addr); + pr_debug("sps ev_id=%d, addr=0x%pa, size=0x%x, flags=0x%x user=0x%pK\n", + notify->event_id, &addr, + notify->data.transfer.iovec.size, + notify->data.transfer.iovec.flags, + notify->data.transfer.user); +} + +static void _qce_req_complete(struct qce_device *pce_dev, unsigned int req_info) +{ + struct ce_request_info *preq_info; + + preq_info = &pce_dev->ce_request_info[req_info]; + + switch (preq_info->xfer_type) { + case QCE_XFER_CIPHERING: + _ablk_cipher_complete(pce_dev, req_info); + break; + case QCE_XFER_HASHING: + _sha_complete(pce_dev, req_info); + break; + case QCE_XFER_AEAD: + _aead_complete(pce_dev, req_info); + break; + case QCE_XFER_F8: + _f8_complete(pce_dev, req_info); + break; + case QCE_XFER_F9: + _f9_complete(pce_dev, req_info); + break; + default: + qce_free_req_info(pce_dev, req_info, true); + break; + } +} + +static void qce_multireq_timeout(unsigned long data) +{ + struct qce_device *pce_dev = (struct qce_device *)data; + int ret = 0; + int last_seq; + unsigned long flags; + + last_seq = atomic_read(&pce_dev->bunch_cmd_seq); + if (last_seq == 0 || + last_seq != atomic_read(&pce_dev->last_intr_seq)) { + atomic_set(&pce_dev->last_intr_seq, last_seq); + mod_timer(&(pce_dev->timer), (jiffies + DELAY_IN_JIFFIES)); + return; + } + /* last bunch mode command time out */ + + /* + * From here to dummy request finish sps request and set owner back + * to none, we disable interrupt. + * So it won't get preempted or interrupted. If bam inerrupts happen + * between, and completion callback gets called from BAM, a new + * request may be issued by the client driver. Deadlock may happen. + */ + local_irq_save(flags); + if (cmpxchg(&pce_dev->owner, QCE_OWNER_NONE, QCE_OWNER_TIMEOUT) + != QCE_OWNER_NONE) { + local_irq_restore(flags); + mod_timer(&(pce_dev->timer), (jiffies + DELAY_IN_JIFFIES)); + return; + } + + ret = qce_dummy_req(pce_dev); + if (ret) + pr_warn("pcedev %d: Failed to insert dummy req\n", + pce_dev->dev_no); + cmpxchg(&pce_dev->owner, QCE_OWNER_TIMEOUT, QCE_OWNER_NONE); + pce_dev->mode = IN_INTERRUPT_MODE; + local_irq_restore(flags); + + del_timer(&(pce_dev->timer)); + pce_dev->qce_stats.no_of_timeouts++; + pr_debug("pcedev %d mode switch to INTR\n", pce_dev->dev_no); +} + +void qce_get_driver_stats(void *handle) +{ + struct qce_device *pce_dev = (struct qce_device *) handle; + + if (!_qce50_disp_stats) + return; + pr_info("Engine %d timeout occuured %d\n", pce_dev->dev_no, + pce_dev->qce_stats.no_of_timeouts); + pr_info("Engine %d dummy request inserted %d\n", pce_dev->dev_no, + pce_dev->qce_stats.no_of_dummy_reqs); + if (pce_dev->mode) + pr_info("Engine %d is in BUNCH MODE\n", pce_dev->dev_no); + else + pr_info("Engine %d is in INTERRUPT MODE\n", pce_dev->dev_no); + pr_info("Engine %d outstanding request %d\n", pce_dev->dev_no, + atomic_read(&pce_dev->no_of_queued_req)); +} +EXPORT_SYMBOL(qce_get_driver_stats); + +void qce_clear_driver_stats(void *handle) +{ + struct qce_device *pce_dev = (struct qce_device *) handle; + + pce_dev->qce_stats.no_of_timeouts = 0; + pce_dev->qce_stats.no_of_dummy_reqs = 0; +} +EXPORT_SYMBOL(qce_clear_driver_stats); + +static void _sps_producer_callback(struct sps_event_notify *notify) +{ + struct qce_device *pce_dev = (struct qce_device *) + ((struct sps_event_notify *)notify)->user; + int rc = 0; + unsigned int req_info; + struct ce_sps_data *pce_sps_data; + struct ce_request_info *preq_info; + + print_notify_debug(notify); + + req_info = (unsigned int)((uintptr_t)notify->data.transfer.user); + if ((req_info & 0xffff0000) != CRYPTO_REQ_USER_PAT) { + pr_warn("request information %d out of range\n", req_info); + return; + } + + req_info = req_info & 0x00ff; + if (req_info < 0 || req_info >= MAX_QCE_ALLOC_BAM_REQ) { + pr_warn("request information %d out of range\n", req_info); + return; + } + + preq_info = &pce_dev->ce_request_info[req_info]; + + pce_sps_data = &preq_info->ce_sps; + if ((preq_info->xfer_type == QCE_XFER_CIPHERING || + preq_info->xfer_type == QCE_XFER_AEAD) && + pce_sps_data->producer_state == QCE_PIPE_STATE_IDLE) { + pce_sps_data->producer_state = QCE_PIPE_STATE_COMP; + pce_sps_data->out_transfer.iovec_count = 0; + _qce_sps_add_data(GET_PHYS_ADDR(pce_sps_data->result_dump), + CRYPTO_RESULT_DUMP_SIZE, + &pce_sps_data->out_transfer); + _qce_set_flag(&pce_sps_data->out_transfer, + SPS_IOVEC_FLAG_INT); + rc = sps_transfer(pce_dev->ce_bam_info.producer.pipe, + &pce_sps_data->out_transfer); + if (rc) { + pr_err("sps_xfr() fail (producer pipe=0x%lx) rc = %d\n", + (uintptr_t)pce_dev->ce_bam_info.producer.pipe, + rc); + } + return; + } + + _qce_req_complete(pce_dev, req_info); +} + +/** + * De-initialize SPS HW connected with CE core + * + * This function deinitialize SPS endpoints and then + * deregisters BAM resources from SPS driver. + * + * This function should only be called once typically + * during driver remove. + * + * @pce_dev - Pointer to qce_device structure + * + */ +static void qce_sps_exit(struct qce_device *pce_dev) +{ + qce_sps_exit_ep_conn(pce_dev, &pce_dev->ce_bam_info.consumer); + qce_sps_exit_ep_conn(pce_dev, &pce_dev->ce_bam_info.producer); + qce_sps_release_bam(pce_dev); +} + +static void qce_add_cmd_element(struct qce_device *pdev, + struct sps_command_element **cmd_ptr, u32 addr, + u32 data, struct sps_command_element **populate) +{ + (*cmd_ptr)->addr = (uint32_t)(addr + pdev->phy_iobase); + (*cmd_ptr)->command = 0; + (*cmd_ptr)->data = data; + (*cmd_ptr)->mask = 0xFFFFFFFF; + (*cmd_ptr)->reserved = 0; + if (populate != NULL) + *populate = *cmd_ptr; + (*cmd_ptr)++; +} + +static int _setup_cipher_aes_cmdlistptrs(struct qce_device *pdev, int cri_index, + unsigned char **pvaddr, enum qce_cipher_mode_enum mode, + bool key_128) +{ + struct sps_command_element *ce_vaddr; + uintptr_t ce_vaddr_start; + struct qce_cmdlistptr_ops *cmdlistptr; + struct qce_cmdlist_info *pcl_info = NULL; + int i = 0; + uint32_t encr_cfg = 0; + uint32_t key_reg = 0; + uint32_t xts_key_reg = 0; + uint32_t iv_reg = 0; + + cmdlistptr = &pdev->ce_request_info[cri_index].ce_sps.cmdlistptr; + *pvaddr = (unsigned char *)ALIGN(((uintptr_t)(*pvaddr)), + pdev->ce_bam_info.ce_burst_size); + ce_vaddr = (struct sps_command_element *)(*pvaddr); + ce_vaddr_start = (uintptr_t)(*pvaddr); + /* + * Designate chunks of the allocated memory to various + * command list pointers related to AES cipher operations defined + * in ce_cmdlistptrs_ops structure. + */ + switch (mode) { + case QCE_MODE_CBC: + case QCE_MODE_CTR: + if (key_128 == true) { + cmdlistptr->cipher_aes_128_cbc_ctr.cmdlist = + (uintptr_t)ce_vaddr; + pcl_info = &(cmdlistptr->cipher_aes_128_cbc_ctr); + if (mode == QCE_MODE_CBC) + encr_cfg = pdev->reg.encr_cfg_aes_cbc_128; + else + encr_cfg = pdev->reg.encr_cfg_aes_ctr_128; + iv_reg = 4; + key_reg = 4; + xts_key_reg = 0; + } else { + cmdlistptr->cipher_aes_256_cbc_ctr.cmdlist = + (uintptr_t)ce_vaddr; + pcl_info = &(cmdlistptr->cipher_aes_256_cbc_ctr); + + if (mode == QCE_MODE_CBC) + encr_cfg = pdev->reg.encr_cfg_aes_cbc_256; + else + encr_cfg = pdev->reg.encr_cfg_aes_ctr_256; + iv_reg = 4; + key_reg = 8; + xts_key_reg = 0; + } + break; + case QCE_MODE_ECB: + if (key_128 == true) { + cmdlistptr->cipher_aes_128_ecb.cmdlist = + (uintptr_t)ce_vaddr; + pcl_info = &(cmdlistptr->cipher_aes_128_ecb); + + encr_cfg = pdev->reg.encr_cfg_aes_ecb_128; + iv_reg = 0; + key_reg = 4; + xts_key_reg = 0; + } else { + cmdlistptr->cipher_aes_256_ecb.cmdlist = + (uintptr_t)ce_vaddr; + pcl_info = &(cmdlistptr->cipher_aes_256_ecb); + + encr_cfg = pdev->reg.encr_cfg_aes_ecb_256; + iv_reg = 0; + key_reg = 8; + xts_key_reg = 0; + } + break; + case QCE_MODE_XTS: + if (key_128 == true) { + cmdlistptr->cipher_aes_128_xts.cmdlist = + (uintptr_t)ce_vaddr; + pcl_info = &(cmdlistptr->cipher_aes_128_xts); + + encr_cfg = pdev->reg.encr_cfg_aes_xts_128; + iv_reg = 4; + key_reg = 4; + xts_key_reg = 4; + } else { + cmdlistptr->cipher_aes_256_xts.cmdlist = + (uintptr_t)ce_vaddr; + pcl_info = &(cmdlistptr->cipher_aes_256_xts); + + encr_cfg = pdev->reg.encr_cfg_aes_xts_256; + iv_reg = 4; + key_reg = 8; + xts_key_reg = 8; + } + break; + default: + pr_err("Unknown mode of operation %d received, exiting now\n", + mode); + return -EINVAL; + break; + } + + /* clear status register */ + qce_add_cmd_element(pdev, &ce_vaddr, CRYPTO_STATUS_REG, 0, NULL); + + qce_add_cmd_element(pdev, &ce_vaddr, CRYPTO_CONFIG_REG, + pdev->reg.crypto_cfg_be, &pcl_info->crypto_cfg); + + qce_add_cmd_element(pdev, &ce_vaddr, CRYPTO_SEG_SIZE_REG, 0, + &pcl_info->seg_size); + qce_add_cmd_element(pdev, &ce_vaddr, CRYPTO_ENCR_SEG_CFG_REG, encr_cfg, + &pcl_info->encr_seg_cfg); + qce_add_cmd_element(pdev, &ce_vaddr, CRYPTO_ENCR_SEG_SIZE_REG, 0, + &pcl_info->encr_seg_size); + qce_add_cmd_element(pdev, &ce_vaddr, CRYPTO_ENCR_SEG_START_REG, 0, + &pcl_info->encr_seg_start); + qce_add_cmd_element(pdev, &ce_vaddr, CRYPTO_CNTR_MASK_REG, + (uint32_t)0xffffffff, &pcl_info->encr_mask); + qce_add_cmd_element(pdev, &ce_vaddr, CRYPTO_CNTR_MASK_REG0, + (uint32_t)0xffffffff, NULL); + qce_add_cmd_element(pdev, &ce_vaddr, CRYPTO_CNTR_MASK_REG1, + (uint32_t)0xffffffff, NULL); + qce_add_cmd_element(pdev, &ce_vaddr, CRYPTO_CNTR_MASK_REG2, + (uint32_t)0xffffffff, NULL); + qce_add_cmd_element(pdev, &ce_vaddr, CRYPTO_AUTH_SEG_CFG_REG, 0, + &pcl_info->auth_seg_cfg); + qce_add_cmd_element(pdev, &ce_vaddr, CRYPTO_ENCR_KEY0_REG, 0, + &pcl_info->encr_key); + for (i = 1; i < key_reg; i++) + qce_add_cmd_element(pdev, &ce_vaddr, + (CRYPTO_ENCR_KEY0_REG + i * sizeof(uint32_t)), + 0, NULL); + if (xts_key_reg) { + qce_add_cmd_element(pdev, &ce_vaddr, CRYPTO_ENCR_XTS_KEY0_REG, + 0, &pcl_info->encr_xts_key); + for (i = 1; i < xts_key_reg; i++) + qce_add_cmd_element(pdev, &ce_vaddr, + (CRYPTO_ENCR_XTS_KEY0_REG + + i * sizeof(uint32_t)), 0, NULL); + qce_add_cmd_element(pdev, &ce_vaddr, + CRYPTO_ENCR_XTS_DU_SIZE_REG, 0, + &pcl_info->encr_xts_du_size); + } + if (iv_reg) { + qce_add_cmd_element(pdev, &ce_vaddr, CRYPTO_CNTR0_IV0_REG, 0, + &pcl_info->encr_cntr_iv); + for (i = 1; i < iv_reg; i++) + qce_add_cmd_element(pdev, &ce_vaddr, + (CRYPTO_CNTR0_IV0_REG + i * sizeof(uint32_t)), + 0, NULL); + } + /* Add dummy to align size to burst-size multiple */ + if (mode == QCE_MODE_XTS) { + qce_add_cmd_element(pdev, &ce_vaddr, CRYPTO_AUTH_SEG_SIZE_REG, + 0, &pcl_info->auth_seg_size); + } else { + qce_add_cmd_element(pdev, &ce_vaddr, CRYPTO_AUTH_SEG_SIZE_REG, + 0, &pcl_info->auth_seg_size); + qce_add_cmd_element(pdev, &ce_vaddr, CRYPTO_AUTH_SEG_START_REG, + 0, &pcl_info->auth_seg_size); + } + qce_add_cmd_element(pdev, &ce_vaddr, CRYPTO_CONFIG_REG, + pdev->reg.crypto_cfg_le, NULL); + + qce_add_cmd_element(pdev, &ce_vaddr, CRYPTO_GOPROC_REG, + ((1 << CRYPTO_GO) | (1 << CRYPTO_RESULTS_DUMP) | + (1 << CRYPTO_CLR_CNTXT)), &pcl_info->go_proc); + + pcl_info->size = (uintptr_t)ce_vaddr - (uintptr_t)ce_vaddr_start; + *pvaddr = (unsigned char *) ce_vaddr; + + return 0; +} + +static int _setup_cipher_des_cmdlistptrs(struct qce_device *pdev, int cri_index, + unsigned char **pvaddr, enum qce_cipher_alg_enum alg, + bool mode_cbc) +{ + + struct sps_command_element *ce_vaddr; + uintptr_t ce_vaddr_start; + struct qce_cmdlistptr_ops *cmdlistptr; + struct qce_cmdlist_info *pcl_info = NULL; + int i = 0; + uint32_t encr_cfg = 0; + uint32_t key_reg = 0; + uint32_t iv_reg = 0; + + cmdlistptr = &pdev->ce_request_info[cri_index].ce_sps.cmdlistptr; + *pvaddr = (unsigned char *)ALIGN(((uintptr_t)(*pvaddr)), + pdev->ce_bam_info.ce_burst_size); + ce_vaddr = (struct sps_command_element *)(*pvaddr); + ce_vaddr_start = (uintptr_t)(*pvaddr); + + /* + * Designate chunks of the allocated memory to various + * command list pointers related to cipher operations defined + * in ce_cmdlistptrs_ops structure. + */ + switch (alg) { + case CIPHER_ALG_DES: + if (mode_cbc) { + cmdlistptr->cipher_des_cbc.cmdlist = + (uintptr_t)ce_vaddr; + pcl_info = &(cmdlistptr->cipher_des_cbc); + + + encr_cfg = pdev->reg.encr_cfg_des_cbc; + iv_reg = 2; + key_reg = 2; + } else { + cmdlistptr->cipher_des_ecb.cmdlist = + (uintptr_t)ce_vaddr; + pcl_info = &(cmdlistptr->cipher_des_ecb); + + encr_cfg = pdev->reg.encr_cfg_des_ecb; + iv_reg = 0; + key_reg = 2; + } + break; + case CIPHER_ALG_3DES: + if (mode_cbc) { + cmdlistptr->cipher_3des_cbc.cmdlist = + (uintptr_t)ce_vaddr; + pcl_info = &(cmdlistptr->cipher_3des_cbc); + + encr_cfg = pdev->reg.encr_cfg_3des_cbc; + iv_reg = 2; + key_reg = 6; + } else { + cmdlistptr->cipher_3des_ecb.cmdlist = + (uintptr_t)ce_vaddr; + pcl_info = &(cmdlistptr->cipher_3des_ecb); + + encr_cfg = pdev->reg.encr_cfg_3des_ecb; + iv_reg = 0; + key_reg = 6; + } + break; + default: + pr_err("Unknown algorithms %d received, exiting now\n", alg); + return -EINVAL; + break; + } + + /* clear status register */ + qce_add_cmd_element(pdev, &ce_vaddr, CRYPTO_STATUS_REG, 0, NULL); + + qce_add_cmd_element(pdev, &ce_vaddr, CRYPTO_CONFIG_REG, + pdev->reg.crypto_cfg_be, &pcl_info->crypto_cfg); + + qce_add_cmd_element(pdev, &ce_vaddr, CRYPTO_SEG_SIZE_REG, 0, + &pcl_info->seg_size); + qce_add_cmd_element(pdev, &ce_vaddr, CRYPTO_ENCR_SEG_CFG_REG, encr_cfg, + &pcl_info->encr_seg_cfg); + qce_add_cmd_element(pdev, &ce_vaddr, CRYPTO_ENCR_SEG_SIZE_REG, 0, + &pcl_info->encr_seg_size); + qce_add_cmd_element(pdev, &ce_vaddr, CRYPTO_ENCR_SEG_START_REG, 0, + &pcl_info->encr_seg_start); + qce_add_cmd_element(pdev, &ce_vaddr, CRYPTO_AUTH_SEG_CFG_REG, 0, + &pcl_info->auth_seg_cfg); + + qce_add_cmd_element(pdev, &ce_vaddr, CRYPTO_ENCR_KEY0_REG, 0, + &pcl_info->encr_key); + for (i = 1; i < key_reg; i++) + qce_add_cmd_element(pdev, &ce_vaddr, + (CRYPTO_ENCR_KEY0_REG + i * sizeof(uint32_t)), + 0, NULL); + if (iv_reg) { + qce_add_cmd_element(pdev, &ce_vaddr, CRYPTO_CNTR0_IV0_REG, 0, + &pcl_info->encr_cntr_iv); + qce_add_cmd_element(pdev, &ce_vaddr, CRYPTO_CNTR1_IV1_REG, 0, + NULL); + } + + qce_add_cmd_element(pdev, &ce_vaddr, CRYPTO_CONFIG_REG, + pdev->reg.crypto_cfg_le, NULL); + + qce_add_cmd_element(pdev, &ce_vaddr, CRYPTO_GOPROC_REG, + ((1 << CRYPTO_GO) | (1 << CRYPTO_RESULTS_DUMP) | + (1 << CRYPTO_CLR_CNTXT)), &pcl_info->go_proc); + + pcl_info->size = (uintptr_t)ce_vaddr - (uintptr_t)ce_vaddr_start; + *pvaddr = (unsigned char *) ce_vaddr; + + return 0; +} + +static int _setup_cipher_null_cmdlistptrs(struct qce_device *pdev, + int cri_index, unsigned char **pvaddr) +{ + struct sps_command_element *ce_vaddr; + uintptr_t ce_vaddr_start; + struct qce_cmdlistptr_ops *cmdlistptr = &pdev->ce_request_info + [cri_index].ce_sps.cmdlistptr; + struct qce_cmdlist_info *pcl_info = NULL; + + *pvaddr = (unsigned char *)ALIGN(((uintptr_t)(*pvaddr)), + pdev->ce_bam_info.ce_burst_size); + ce_vaddr_start = (uintptr_t)(*pvaddr); + ce_vaddr = (struct sps_command_element *)(*pvaddr); + + cmdlistptr->cipher_null.cmdlist = (uintptr_t)ce_vaddr; + pcl_info = &(cmdlistptr->cipher_null); + + qce_add_cmd_element(pdev, &ce_vaddr, CRYPTO_SEG_SIZE_REG, + pdev->ce_bam_info.ce_burst_size, NULL); + + qce_add_cmd_element(pdev, &ce_vaddr, CRYPTO_ENCR_SEG_CFG_REG, + pdev->reg.encr_cfg_aes_ecb_128, NULL); + qce_add_cmd_element(pdev, &ce_vaddr, CRYPTO_ENCR_SEG_SIZE_REG, 0, + NULL); + qce_add_cmd_element(pdev, &ce_vaddr, CRYPTO_ENCR_SEG_START_REG, 0, + NULL); + + qce_add_cmd_element(pdev, &ce_vaddr, CRYPTO_AUTH_SEG_CFG_REG, + 0, NULL); + qce_add_cmd_element(pdev, &ce_vaddr, CRYPTO_AUTH_SEG_SIZE_REG, + 0, NULL); + qce_add_cmd_element(pdev, &ce_vaddr, CRYPTO_AUTH_SEG_START_REG, 0, + NULL); + + qce_add_cmd_element(pdev, &ce_vaddr, CRYPTO_GOPROC_REG, + ((1 << CRYPTO_GO) | (1 << CRYPTO_RESULTS_DUMP) | + (1 << CRYPTO_CLR_CNTXT)), &pcl_info->go_proc); + + pcl_info->size = (uintptr_t)ce_vaddr - (uintptr_t)ce_vaddr_start; + *pvaddr = (unsigned char *) ce_vaddr; + return 0; +} + +static int _setup_auth_cmdlistptrs(struct qce_device *pdev, int cri_index, + unsigned char **pvaddr, enum qce_hash_alg_enum alg, + bool key_128) +{ + struct sps_command_element *ce_vaddr; + uintptr_t ce_vaddr_start; + struct qce_cmdlistptr_ops *cmdlistptr; + struct qce_cmdlist_info *pcl_info = NULL; + int i = 0; + uint32_t key_reg = 0; + uint32_t auth_cfg = 0; + uint32_t iv_reg = 0; + + cmdlistptr = &pdev->ce_request_info[cri_index].ce_sps.cmdlistptr; + *pvaddr = (unsigned char *)ALIGN(((uintptr_t)(*pvaddr)), + pdev->ce_bam_info.ce_burst_size); + ce_vaddr_start = (uintptr_t)(*pvaddr); + ce_vaddr = (struct sps_command_element *)(*pvaddr); + + /* + * Designate chunks of the allocated memory to various + * command list pointers related to authentication operations + * defined in ce_cmdlistptrs_ops structure. + */ + switch (alg) { + case QCE_HASH_SHA1: + cmdlistptr->auth_sha1.cmdlist = (uintptr_t)ce_vaddr; + pcl_info = &(cmdlistptr->auth_sha1); + + auth_cfg = pdev->reg.auth_cfg_sha1; + iv_reg = 5; + + /* clear status register */ + qce_add_cmd_element(pdev, &ce_vaddr, CRYPTO_STATUS_REG, + 0, NULL); + + qce_add_cmd_element(pdev, &ce_vaddr, CRYPTO_CONFIG_REG, + pdev->reg.crypto_cfg_be, &pcl_info->crypto_cfg); + + break; + case QCE_HASH_SHA256: + cmdlistptr->auth_sha256.cmdlist = (uintptr_t)ce_vaddr; + pcl_info = &(cmdlistptr->auth_sha256); + + auth_cfg = pdev->reg.auth_cfg_sha256; + iv_reg = 8; + + /* clear status register */ + qce_add_cmd_element(pdev, &ce_vaddr, CRYPTO_STATUS_REG, + 0, NULL); + + qce_add_cmd_element(pdev, &ce_vaddr, CRYPTO_CONFIG_REG, + pdev->reg.crypto_cfg_be, &pcl_info->crypto_cfg); + /* 1 dummy write */ + qce_add_cmd_element(pdev, &ce_vaddr, CRYPTO_ENCR_SEG_SIZE_REG, + 0, NULL); + break; + case QCE_HASH_SHA1_HMAC: + cmdlistptr->auth_sha1_hmac.cmdlist = (uintptr_t)ce_vaddr; + pcl_info = &(cmdlistptr->auth_sha1_hmac); + + auth_cfg = pdev->reg.auth_cfg_hmac_sha1; + key_reg = 16; + iv_reg = 5; + + /* clear status register */ + qce_add_cmd_element(pdev, &ce_vaddr, CRYPTO_STATUS_REG, + 0, NULL); + + qce_add_cmd_element(pdev, &ce_vaddr, CRYPTO_CONFIG_REG, + pdev->reg.crypto_cfg_be, &pcl_info->crypto_cfg); + break; + case QCE_HASH_SHA256_HMAC: + cmdlistptr->auth_sha256_hmac.cmdlist = (uintptr_t)ce_vaddr; + pcl_info = &(cmdlistptr->auth_sha256_hmac); + + auth_cfg = pdev->reg.auth_cfg_hmac_sha256; + key_reg = 16; + iv_reg = 8; + + /* clear status register */ + qce_add_cmd_element(pdev, &ce_vaddr, CRYPTO_STATUS_REG, 0, + NULL); + + qce_add_cmd_element(pdev, &ce_vaddr, CRYPTO_CONFIG_REG, + pdev->reg.crypto_cfg_be, &pcl_info->crypto_cfg); + /* 1 dummy write */ + qce_add_cmd_element(pdev, &ce_vaddr, CRYPTO_ENCR_SEG_SIZE_REG, + 0, NULL); + break; + case QCE_HASH_AES_CMAC: + if (key_128 == true) { + cmdlistptr->auth_aes_128_cmac.cmdlist = + (uintptr_t)ce_vaddr; + pcl_info = &(cmdlistptr->auth_aes_128_cmac); + + auth_cfg = pdev->reg.auth_cfg_cmac_128; + key_reg = 4; + } else { + cmdlistptr->auth_aes_256_cmac.cmdlist = + (uintptr_t)ce_vaddr; + pcl_info = &(cmdlistptr->auth_aes_256_cmac); + + auth_cfg = pdev->reg.auth_cfg_cmac_256; + key_reg = 8; + } + + /* clear status register */ + qce_add_cmd_element(pdev, &ce_vaddr, CRYPTO_STATUS_REG, 0, + NULL); + + qce_add_cmd_element(pdev, &ce_vaddr, CRYPTO_CONFIG_REG, + pdev->reg.crypto_cfg_be, &pcl_info->crypto_cfg); + /* 1 dummy write */ + qce_add_cmd_element(pdev, &ce_vaddr, CRYPTO_ENCR_SEG_SIZE_REG, + 0, NULL); + break; + default: + pr_err("Unknown algorithms %d received, exiting now\n", alg); + return -EINVAL; + break; + } + + qce_add_cmd_element(pdev, &ce_vaddr, CRYPTO_SEG_SIZE_REG, 0, + &pcl_info->seg_size); + qce_add_cmd_element(pdev, &ce_vaddr, CRYPTO_ENCR_SEG_CFG_REG, 0, + &pcl_info->encr_seg_cfg); + qce_add_cmd_element(pdev, &ce_vaddr, CRYPTO_AUTH_SEG_CFG_REG, + auth_cfg, &pcl_info->auth_seg_cfg); + qce_add_cmd_element(pdev, &ce_vaddr, CRYPTO_AUTH_SEG_SIZE_REG, 0, + &pcl_info->auth_seg_size); + qce_add_cmd_element(pdev, &ce_vaddr, CRYPTO_AUTH_SEG_START_REG, 0, + &pcl_info->auth_seg_start); + + if (alg == QCE_HASH_AES_CMAC) { + /* reset auth iv, bytecount and key registers */ + for (i = 0; i < 16; i++) + qce_add_cmd_element(pdev, &ce_vaddr, + (CRYPTO_AUTH_IV0_REG + i * sizeof(uint32_t)), + 0, NULL); + for (i = 0; i < 16; i++) + qce_add_cmd_element(pdev, &ce_vaddr, + (CRYPTO_AUTH_KEY0_REG + i*sizeof(uint32_t)), + 0, NULL); + qce_add_cmd_element(pdev, &ce_vaddr, CRYPTO_AUTH_BYTECNT0_REG, + 0, NULL); + } else { + qce_add_cmd_element(pdev, &ce_vaddr, CRYPTO_AUTH_IV0_REG, 0, + &pcl_info->auth_iv); + for (i = 1; i < iv_reg; i++) + qce_add_cmd_element(pdev, &ce_vaddr, + (CRYPTO_AUTH_IV0_REG + i*sizeof(uint32_t)), + 0, NULL); + qce_add_cmd_element(pdev, &ce_vaddr, CRYPTO_AUTH_BYTECNT0_REG, + 0, &pcl_info->auth_bytecount); + } + qce_add_cmd_element(pdev, &ce_vaddr, CRYPTO_AUTH_BYTECNT1_REG, 0, NULL); + + if (key_reg) { + qce_add_cmd_element(pdev, &ce_vaddr, + CRYPTO_AUTH_KEY0_REG, 0, &pcl_info->auth_key); + for (i = 1; i < key_reg; i++) + qce_add_cmd_element(pdev, &ce_vaddr, + (CRYPTO_AUTH_KEY0_REG + i*sizeof(uint32_t)), + 0, NULL); + } + qce_add_cmd_element(pdev, &ce_vaddr, CRYPTO_CONFIG_REG, + pdev->reg.crypto_cfg_le, NULL); + + qce_add_cmd_element(pdev, &ce_vaddr, CRYPTO_GOPROC_REG, + ((1 << CRYPTO_GO) | (1 << CRYPTO_RESULTS_DUMP) | + (1 << CRYPTO_CLR_CNTXT)), &pcl_info->go_proc); + + pcl_info->size = (uintptr_t)ce_vaddr - (uintptr_t)ce_vaddr_start; + *pvaddr = (unsigned char *) ce_vaddr; + + return 0; +} + +static int _setup_aead_cmdlistptrs(struct qce_device *pdev, + int cri_index, + unsigned char **pvaddr, + uint32_t alg, + uint32_t mode, + uint32_t key_size, + bool sha1) +{ + struct sps_command_element *ce_vaddr; + uintptr_t ce_vaddr_start; + struct qce_cmdlistptr_ops *cmdlistptr; + struct qce_cmdlist_info *pcl_info = NULL; + uint32_t key_reg; + uint32_t iv_reg; + uint32_t i; + uint32_t enciv_in_word; + uint32_t encr_cfg; + + cmdlistptr = &pdev->ce_request_info[cri_index].ce_sps.cmdlistptr; + *pvaddr = (unsigned char *)ALIGN(((uintptr_t)(*pvaddr)), + pdev->ce_bam_info.ce_burst_size); + + ce_vaddr_start = (uintptr_t)(*pvaddr); + ce_vaddr = (struct sps_command_element *)(*pvaddr); + + switch (alg) { + + case CIPHER_ALG_DES: + + switch (mode) { + + case QCE_MODE_CBC: + if (sha1) { + cmdlistptr->aead_hmac_sha1_cbc_des.cmdlist = + (uintptr_t)ce_vaddr; + pcl_info = &(cmdlistptr-> + aead_hmac_sha1_cbc_des); + } else { + cmdlistptr->aead_hmac_sha256_cbc_des.cmdlist = + (uintptr_t)ce_vaddr; + pcl_info = &(cmdlistptr-> + aead_hmac_sha256_cbc_des); + } + encr_cfg = pdev->reg.encr_cfg_des_cbc; + break; + default: + return -EINVAL; + }; + + enciv_in_word = 2; + + break; + + case CIPHER_ALG_3DES: + switch (mode) { + + case QCE_MODE_CBC: + if (sha1) { + cmdlistptr->aead_hmac_sha1_cbc_3des.cmdlist = + (uintptr_t)ce_vaddr; + pcl_info = &(cmdlistptr-> + aead_hmac_sha1_cbc_3des); + } else { + cmdlistptr->aead_hmac_sha256_cbc_3des.cmdlist = + (uintptr_t)ce_vaddr; + pcl_info = &(cmdlistptr-> + aead_hmac_sha256_cbc_3des); + } + encr_cfg = pdev->reg.encr_cfg_3des_cbc; + break; + default: + return -EINVAL; + }; + + enciv_in_word = 2; + + break; + + case CIPHER_ALG_AES: + switch (mode) { + + case QCE_MODE_CBC: + if (key_size == AES128_KEY_SIZE) { + if (sha1) { + cmdlistptr-> + aead_hmac_sha1_cbc_aes_128. + cmdlist = (uintptr_t)ce_vaddr; + pcl_info = &(cmdlistptr-> + aead_hmac_sha1_cbc_aes_128); + } else { + cmdlistptr-> + aead_hmac_sha256_cbc_aes_128. + cmdlist = (uintptr_t)ce_vaddr; + pcl_info = &(cmdlistptr-> + aead_hmac_sha256_cbc_aes_128); + } + encr_cfg = pdev->reg.encr_cfg_aes_cbc_128; + } else if (key_size == AES256_KEY_SIZE) { + if (sha1) { + cmdlistptr-> + aead_hmac_sha1_cbc_aes_256. + cmdlist = (uintptr_t)ce_vaddr; + pcl_info = &(cmdlistptr-> + aead_hmac_sha1_cbc_aes_256); + } else { + cmdlistptr-> + aead_hmac_sha256_cbc_aes_256. + cmdlist = (uintptr_t)ce_vaddr; + pcl_info = &(cmdlistptr-> + aead_hmac_sha256_cbc_aes_256); + } + encr_cfg = pdev->reg.encr_cfg_aes_cbc_256; + } else { + return -EINVAL; + } + break; + default: + return -EINVAL; + }; + + enciv_in_word = 4; + + break; + + default: + return -EINVAL; + }; + + + qce_add_cmd_element(pdev, &ce_vaddr, CRYPTO_STATUS_REG, 0, NULL); + + qce_add_cmd_element(pdev, &ce_vaddr, CRYPTO_CONFIG_REG, + pdev->reg.crypto_cfg_be, &pcl_info->crypto_cfg); + + + key_reg = key_size/sizeof(uint32_t); + qce_add_cmd_element(pdev, &ce_vaddr, CRYPTO_ENCR_KEY0_REG, 0, + &pcl_info->encr_key); + for (i = 1; i < key_reg; i++) + qce_add_cmd_element(pdev, &ce_vaddr, + (CRYPTO_ENCR_KEY0_REG + i * sizeof(uint32_t)), + 0, NULL); + + if (mode != QCE_MODE_ECB) { + qce_add_cmd_element(pdev, &ce_vaddr, CRYPTO_CNTR0_IV0_REG, 0, + &pcl_info->encr_cntr_iv); + for (i = 1; i < enciv_in_word; i++) + qce_add_cmd_element(pdev, &ce_vaddr, + (CRYPTO_CNTR0_IV0_REG + i * sizeof(uint32_t)), + 0, NULL); + }; + + if (sha1) + iv_reg = 5; + else + iv_reg = 8; + qce_add_cmd_element(pdev, &ce_vaddr, CRYPTO_AUTH_IV0_REG, 0, + &pcl_info->auth_iv); + for (i = 1; i < iv_reg; i++) + qce_add_cmd_element(pdev, &ce_vaddr, + (CRYPTO_AUTH_IV0_REG + i*sizeof(uint32_t)), + 0, NULL); + + qce_add_cmd_element(pdev, &ce_vaddr, CRYPTO_AUTH_BYTECNT0_REG, + 0, &pcl_info->auth_bytecount); + qce_add_cmd_element(pdev, &ce_vaddr, CRYPTO_AUTH_BYTECNT1_REG, 0, NULL); + + key_reg = SHA_HMAC_KEY_SIZE/sizeof(uint32_t); + qce_add_cmd_element(pdev, &ce_vaddr, CRYPTO_AUTH_KEY0_REG, 0, + &pcl_info->auth_key); + for (i = 1; i < key_reg; i++) + qce_add_cmd_element(pdev, &ce_vaddr, + (CRYPTO_AUTH_KEY0_REG + i*sizeof(uint32_t)), 0, NULL); + + qce_add_cmd_element(pdev, &ce_vaddr, CRYPTO_SEG_SIZE_REG, 0, + &pcl_info->seg_size); + + qce_add_cmd_element(pdev, &ce_vaddr, CRYPTO_ENCR_SEG_CFG_REG, encr_cfg, + &pcl_info->encr_seg_cfg); + qce_add_cmd_element(pdev, &ce_vaddr, CRYPTO_ENCR_SEG_SIZE_REG, 0, + &pcl_info->encr_seg_size); + qce_add_cmd_element(pdev, &ce_vaddr, CRYPTO_ENCR_SEG_START_REG, 0, + &pcl_info->encr_seg_start); + + if (sha1) + qce_add_cmd_element( + pdev, + &ce_vaddr, + CRYPTO_AUTH_SEG_CFG_REG, + pdev->reg.auth_cfg_aead_sha1_hmac, + &pcl_info->auth_seg_cfg); + else + qce_add_cmd_element( + pdev, + &ce_vaddr, + CRYPTO_AUTH_SEG_CFG_REG, + pdev->reg.auth_cfg_aead_sha256_hmac, + &pcl_info->auth_seg_cfg); + + qce_add_cmd_element(pdev, &ce_vaddr, CRYPTO_AUTH_SEG_SIZE_REG, 0, + &pcl_info->auth_seg_size); + qce_add_cmd_element(pdev, &ce_vaddr, CRYPTO_AUTH_SEG_START_REG, 0, + &pcl_info->auth_seg_start); + + qce_add_cmd_element(pdev, &ce_vaddr, CRYPTO_CONFIG_REG, + pdev->reg.crypto_cfg_le, NULL); + + qce_add_cmd_element(pdev, &ce_vaddr, CRYPTO_GOPROC_REG, + ((1 << CRYPTO_GO) | (1 << CRYPTO_RESULTS_DUMP) | + (1 << CRYPTO_CLR_CNTXT)), &pcl_info->go_proc); + + pcl_info->size = (uintptr_t)ce_vaddr - (uintptr_t)ce_vaddr_start; + *pvaddr = (unsigned char *) ce_vaddr; + return 0; +} + +static int _setup_aead_ccm_cmdlistptrs(struct qce_device *pdev, int cri_index, + unsigned char **pvaddr, bool key_128) +{ + struct sps_command_element *ce_vaddr; + uintptr_t ce_vaddr_start; + struct qce_cmdlistptr_ops *cmdlistptr = &pdev->ce_request_info + [cri_index].ce_sps.cmdlistptr; + struct qce_cmdlist_info *pcl_info = NULL; + int i = 0; + uint32_t encr_cfg = 0; + uint32_t auth_cfg = 0; + uint32_t key_reg = 0; + + *pvaddr = (unsigned char *)ALIGN(((uintptr_t)(*pvaddr)), + pdev->ce_bam_info.ce_burst_size); + ce_vaddr_start = (uintptr_t)(*pvaddr); + ce_vaddr = (struct sps_command_element *)(*pvaddr); + + /* + * Designate chunks of the allocated memory to various + * command list pointers related to aead operations + * defined in ce_cmdlistptrs_ops structure. + */ + if (key_128 == true) { + cmdlistptr->aead_aes_128_ccm.cmdlist = + (uintptr_t)ce_vaddr; + pcl_info = &(cmdlistptr->aead_aes_128_ccm); + + auth_cfg = pdev->reg.auth_cfg_aes_ccm_128; + encr_cfg = pdev->reg.encr_cfg_aes_ccm_128; + key_reg = 4; + } else { + + cmdlistptr->aead_aes_256_ccm.cmdlist = + (uintptr_t)ce_vaddr; + pcl_info = &(cmdlistptr->aead_aes_256_ccm); + + auth_cfg = pdev->reg.auth_cfg_aes_ccm_256; + encr_cfg = pdev->reg.encr_cfg_aes_ccm_256; + + key_reg = 8; + } + + /* clear status register */ + qce_add_cmd_element(pdev, &ce_vaddr, CRYPTO_STATUS_REG, 0, NULL); + + qce_add_cmd_element(pdev, &ce_vaddr, CRYPTO_CONFIG_REG, + pdev->reg.crypto_cfg_be, &pcl_info->crypto_cfg); + + qce_add_cmd_element(pdev, &ce_vaddr, CRYPTO_ENCR_SEG_CFG_REG, 0, NULL); + qce_add_cmd_element(pdev, &ce_vaddr, CRYPTO_ENCR_SEG_START_REG, 0, + NULL); + qce_add_cmd_element(pdev, &ce_vaddr, CRYPTO_SEG_SIZE_REG, 0, + &pcl_info->seg_size); + qce_add_cmd_element(pdev, &ce_vaddr, CRYPTO_ENCR_SEG_CFG_REG, + encr_cfg, &pcl_info->encr_seg_cfg); + qce_add_cmd_element(pdev, &ce_vaddr, CRYPTO_ENCR_SEG_SIZE_REG, 0, + &pcl_info->encr_seg_size); + qce_add_cmd_element(pdev, &ce_vaddr, CRYPTO_ENCR_SEG_START_REG, 0, + &pcl_info->encr_seg_start); + qce_add_cmd_element(pdev, &ce_vaddr, CRYPTO_CNTR_MASK_REG, + (uint32_t)0xffffffff, &pcl_info->encr_mask); + qce_add_cmd_element(pdev, &ce_vaddr, CRYPTO_CNTR_MASK_REG0, + (uint32_t)0xffffffff, NULL); + qce_add_cmd_element(pdev, &ce_vaddr, CRYPTO_CNTR_MASK_REG1, + (uint32_t)0xffffffff, NULL); + qce_add_cmd_element(pdev, &ce_vaddr, CRYPTO_CNTR_MASK_REG2, + (uint32_t)0xffffffff, NULL); + qce_add_cmd_element(pdev, &ce_vaddr, CRYPTO_AUTH_SEG_CFG_REG, + auth_cfg, &pcl_info->auth_seg_cfg); + qce_add_cmd_element(pdev, &ce_vaddr, CRYPTO_AUTH_SEG_SIZE_REG, 0, + &pcl_info->auth_seg_size); + qce_add_cmd_element(pdev, &ce_vaddr, CRYPTO_AUTH_SEG_START_REG, 0, + &pcl_info->auth_seg_start); + /* reset auth iv, bytecount and key registers */ + for (i = 0; i < 8; i++) + qce_add_cmd_element(pdev, &ce_vaddr, + (CRYPTO_AUTH_IV0_REG + i * sizeof(uint32_t)), + 0, NULL); + qce_add_cmd_element(pdev, &ce_vaddr, CRYPTO_AUTH_BYTECNT0_REG, + 0, NULL); + qce_add_cmd_element(pdev, &ce_vaddr, CRYPTO_AUTH_BYTECNT1_REG, + 0, NULL); + for (i = 0; i < 16; i++) + qce_add_cmd_element(pdev, &ce_vaddr, + (CRYPTO_AUTH_KEY0_REG + i * sizeof(uint32_t)), + 0, NULL); + /* set auth key */ + qce_add_cmd_element(pdev, &ce_vaddr, CRYPTO_AUTH_KEY0_REG, 0, + &pcl_info->auth_key); + for (i = 1; i < key_reg; i++) + qce_add_cmd_element(pdev, &ce_vaddr, + (CRYPTO_AUTH_KEY0_REG + i * sizeof(uint32_t)), + 0, NULL); + /* set NONCE info */ + qce_add_cmd_element(pdev, &ce_vaddr, CRYPTO_AUTH_INFO_NONCE0_REG, 0, + &pcl_info->auth_nonce_info); + for (i = 1; i < 4; i++) + qce_add_cmd_element(pdev, &ce_vaddr, + (CRYPTO_AUTH_INFO_NONCE0_REG + + i * sizeof(uint32_t)), 0, NULL); + + qce_add_cmd_element(pdev, &ce_vaddr, CRYPTO_ENCR_KEY0_REG, 0, + &pcl_info->encr_key); + for (i = 1; i < key_reg; i++) + qce_add_cmd_element(pdev, &ce_vaddr, + (CRYPTO_ENCR_KEY0_REG + i * sizeof(uint32_t)), + 0, NULL); + qce_add_cmd_element(pdev, &ce_vaddr, CRYPTO_CNTR0_IV0_REG, 0, + &pcl_info->encr_cntr_iv); + for (i = 1; i < 4; i++) + qce_add_cmd_element(pdev, &ce_vaddr, + (CRYPTO_CNTR0_IV0_REG + i * sizeof(uint32_t)), + 0, NULL); + qce_add_cmd_element(pdev, &ce_vaddr, CRYPTO_ENCR_CCM_INT_CNTR0_REG, 0, + &pcl_info->encr_ccm_cntr_iv); + for (i = 1; i < 4; i++) + qce_add_cmd_element(pdev, &ce_vaddr, + (CRYPTO_ENCR_CCM_INT_CNTR0_REG + i * sizeof(uint32_t)), + 0, NULL); + + qce_add_cmd_element(pdev, &ce_vaddr, CRYPTO_CONFIG_REG, + pdev->reg.crypto_cfg_le, NULL); + + qce_add_cmd_element(pdev, &ce_vaddr, CRYPTO_GOPROC_REG, + ((1 << CRYPTO_GO) | (1 << CRYPTO_RESULTS_DUMP) | + (1 << CRYPTO_CLR_CNTXT)), &pcl_info->go_proc); + + pcl_info->size = (uintptr_t)ce_vaddr - (uintptr_t)ce_vaddr_start; + *pvaddr = (unsigned char *) ce_vaddr; + + return 0; +} + +static int _setup_f8_cmdlistptrs(struct qce_device *pdev, int cri_index, + unsigned char **pvaddr, enum qce_ota_algo_enum alg) +{ + struct sps_command_element *ce_vaddr; + uintptr_t ce_vaddr_start; + struct qce_cmdlistptr_ops *cmdlistptr; + struct qce_cmdlist_info *pcl_info = NULL; + int i = 0; + uint32_t encr_cfg = 0; + uint32_t key_reg = 4; + + cmdlistptr = &pdev->ce_request_info[cri_index].ce_sps.cmdlistptr; + *pvaddr = (unsigned char *)ALIGN(((uintptr_t)(*pvaddr)), + pdev->ce_bam_info.ce_burst_size); + ce_vaddr = (struct sps_command_element *)(*pvaddr); + ce_vaddr_start = (uintptr_t)(*pvaddr); + + /* + * Designate chunks of the allocated memory to various + * command list pointers related to f8 cipher algorithm defined + * in ce_cmdlistptrs_ops structure. + */ + + switch (alg) { + case QCE_OTA_ALGO_KASUMI: + cmdlistptr->f8_kasumi.cmdlist = (uintptr_t)ce_vaddr; + pcl_info = &(cmdlistptr->f8_kasumi); + encr_cfg = pdev->reg.encr_cfg_kasumi; + break; + + case QCE_OTA_ALGO_SNOW3G: + default: + cmdlistptr->f8_snow3g.cmdlist = (uintptr_t)ce_vaddr; + pcl_info = &(cmdlistptr->f8_snow3g); + encr_cfg = pdev->reg.encr_cfg_snow3g; + break; + } + /* clear status register */ + qce_add_cmd_element(pdev, &ce_vaddr, CRYPTO_STATUS_REG, + 0, NULL); + /* set config to big endian */ + qce_add_cmd_element(pdev, &ce_vaddr, CRYPTO_CONFIG_REG, + pdev->reg.crypto_cfg_be, &pcl_info->crypto_cfg); + + qce_add_cmd_element(pdev, &ce_vaddr, CRYPTO_SEG_SIZE_REG, 0, + &pcl_info->seg_size); + + qce_add_cmd_element(pdev, &ce_vaddr, CRYPTO_ENCR_SEG_CFG_REG, encr_cfg, + &pcl_info->encr_seg_cfg); + qce_add_cmd_element(pdev, &ce_vaddr, CRYPTO_ENCR_SEG_SIZE_REG, 0, + &pcl_info->encr_seg_size); + qce_add_cmd_element(pdev, &ce_vaddr, CRYPTO_ENCR_SEG_START_REG, 0, + &pcl_info->encr_seg_start); + + qce_add_cmd_element(pdev, &ce_vaddr, CRYPTO_AUTH_SEG_CFG_REG, 0, + &pcl_info->auth_seg_cfg); + + qce_add_cmd_element(pdev, &ce_vaddr, CRYPTO_AUTH_SEG_SIZE_REG, + 0, &pcl_info->auth_seg_size); + qce_add_cmd_element(pdev, &ce_vaddr, CRYPTO_AUTH_SEG_START_REG, + 0, &pcl_info->auth_seg_start); + + qce_add_cmd_element(pdev, &ce_vaddr, CRYPTO_ENCR_KEY0_REG, 0, + &pcl_info->encr_key); + for (i = 1; i < key_reg; i++) + qce_add_cmd_element(pdev, &ce_vaddr, + (CRYPTO_ENCR_KEY0_REG + i * sizeof(uint32_t)), + 0, NULL); + + qce_add_cmd_element(pdev, &ce_vaddr, CRYPTO_CNTR0_IV0_REG, 0, + &pcl_info->encr_cntr_iv); + qce_add_cmd_element(pdev, &ce_vaddr, CRYPTO_CNTR1_IV1_REG, 0, + NULL); + qce_add_cmd_element(pdev, &ce_vaddr, CRYPTO_CONFIG_REG, + pdev->reg.crypto_cfg_le, NULL); + + qce_add_cmd_element(pdev, &ce_vaddr, CRYPTO_GOPROC_REG, + ((1 << CRYPTO_GO) | (1 << CRYPTO_RESULTS_DUMP) | + (1 << CRYPTO_CLR_CNTXT)), &pcl_info->go_proc); + + pcl_info->size = (uintptr_t)ce_vaddr - (uintptr_t)ce_vaddr_start; + *pvaddr = (unsigned char *) ce_vaddr; + + return 0; +} + +static int _setup_f9_cmdlistptrs(struct qce_device *pdev, int cri_index, + unsigned char **pvaddr, enum qce_ota_algo_enum alg) +{ + struct sps_command_element *ce_vaddr; + uintptr_t ce_vaddr_start; + struct qce_cmdlistptr_ops *cmdlistptr; + struct qce_cmdlist_info *pcl_info = NULL; + int i = 0; + uint32_t auth_cfg = 0; + uint32_t iv_reg = 0; + + cmdlistptr = &pdev->ce_request_info[cri_index].ce_sps.cmdlistptr; + *pvaddr = (unsigned char *)ALIGN(((uintptr_t)(*pvaddr)), + pdev->ce_bam_info.ce_burst_size); + ce_vaddr_start = (uintptr_t)(*pvaddr); + ce_vaddr = (struct sps_command_element *)(*pvaddr); + + /* + * Designate chunks of the allocated memory to various + * command list pointers related to authentication operations + * defined in ce_cmdlistptrs_ops structure. + */ + switch (alg) { + case QCE_OTA_ALGO_KASUMI: + cmdlistptr->f9_kasumi.cmdlist = (uintptr_t)ce_vaddr; + pcl_info = &(cmdlistptr->f9_kasumi); + auth_cfg = pdev->reg.auth_cfg_kasumi; + break; + + case QCE_OTA_ALGO_SNOW3G: + default: + cmdlistptr->f9_snow3g.cmdlist = (uintptr_t)ce_vaddr; + pcl_info = &(cmdlistptr->f9_snow3g); + auth_cfg = pdev->reg.auth_cfg_snow3g; + }; + + /* clear status register */ + qce_add_cmd_element(pdev, &ce_vaddr, CRYPTO_STATUS_REG, + 0, NULL); + /* set config to big endian */ + qce_add_cmd_element(pdev, &ce_vaddr, CRYPTO_CONFIG_REG, + pdev->reg.crypto_cfg_be, &pcl_info->crypto_cfg); + + iv_reg = 5; + + qce_add_cmd_element(pdev, &ce_vaddr, CRYPTO_SEG_SIZE_REG, 0, + &pcl_info->seg_size); + + qce_add_cmd_element(pdev, &ce_vaddr, CRYPTO_ENCR_SEG_CFG_REG, 0, + &pcl_info->encr_seg_cfg); + + qce_add_cmd_element(pdev, &ce_vaddr, CRYPTO_AUTH_SEG_CFG_REG, + auth_cfg, &pcl_info->auth_seg_cfg); + qce_add_cmd_element(pdev, &ce_vaddr, CRYPTO_AUTH_SEG_SIZE_REG, 0, + &pcl_info->auth_seg_size); + qce_add_cmd_element(pdev, &ce_vaddr, CRYPTO_AUTH_SEG_START_REG, 0, + &pcl_info->auth_seg_start); + + qce_add_cmd_element(pdev, &ce_vaddr, CRYPTO_AUTH_IV0_REG, 0, + &pcl_info->auth_iv); + for (i = 1; i < iv_reg; i++) { + qce_add_cmd_element(pdev, &ce_vaddr, + (CRYPTO_AUTH_IV0_REG + i*sizeof(uint32_t)), + 0, NULL); + } + qce_add_cmd_element(pdev, &ce_vaddr, CRYPTO_AUTH_BYTECNT0_REG, + 0, &pcl_info->auth_bytecount); + qce_add_cmd_element(pdev, &ce_vaddr, CRYPTO_AUTH_BYTECNT1_REG, 0, NULL); + + qce_add_cmd_element(pdev, &ce_vaddr, CRYPTO_CONFIG_REG, + pdev->reg.crypto_cfg_le, NULL); + + qce_add_cmd_element(pdev, &ce_vaddr, CRYPTO_GOPROC_REG, + ((1 << CRYPTO_GO) | (1 << CRYPTO_RESULTS_DUMP) | + (1 << CRYPTO_CLR_CNTXT)), &pcl_info->go_proc); + + pcl_info->size = (uintptr_t)ce_vaddr - (uintptr_t)ce_vaddr_start; + *pvaddr = (unsigned char *) ce_vaddr; + + return 0; +} + +static int _setup_unlock_pipe_cmdlistptrs(struct qce_device *pdev, + int cri_index, unsigned char **pvaddr) +{ + struct sps_command_element *ce_vaddr; + uintptr_t ce_vaddr_start = (uintptr_t)(*pvaddr); + struct qce_cmdlistptr_ops *cmdlistptr; + struct qce_cmdlist_info *pcl_info = NULL; + + cmdlistptr = &pdev->ce_request_info[cri_index].ce_sps.cmdlistptr; + *pvaddr = (unsigned char *)ALIGN(((uintptr_t)(*pvaddr)), + pdev->ce_bam_info.ce_burst_size); + ce_vaddr = (struct sps_command_element *)(*pvaddr); + cmdlistptr->unlock_all_pipes.cmdlist = (uintptr_t)ce_vaddr; + pcl_info = &(cmdlistptr->unlock_all_pipes); + + /* + * Designate chunks of the allocated memory to command list + * to unlock pipes. + */ + qce_add_cmd_element(pdev, &ce_vaddr, CRYPTO_CONFIG_REG, + CRYPTO_CONFIG_RESET, NULL); + pcl_info->size = (uintptr_t)ce_vaddr - (uintptr_t)ce_vaddr_start; + *pvaddr = (unsigned char *) ce_vaddr; + + return 0; +} + +static int qce_setup_cmdlistptrs(struct qce_device *pdev, int cri_index, + unsigned char **pvaddr) +{ + struct sps_command_element *ce_vaddr = + (struct sps_command_element *)(*pvaddr); + /* + * Designate chunks of the allocated memory to various + * command list pointers related to operations defined + * in ce_cmdlistptrs_ops structure. + */ + ce_vaddr = + (struct sps_command_element *)ALIGN(((uintptr_t) ce_vaddr), + pdev->ce_bam_info.ce_burst_size); + *pvaddr = (unsigned char *) ce_vaddr; + + _setup_cipher_aes_cmdlistptrs(pdev, cri_index, pvaddr, QCE_MODE_CBC, + true); + _setup_cipher_aes_cmdlistptrs(pdev, cri_index, pvaddr, QCE_MODE_CTR, + true); + _setup_cipher_aes_cmdlistptrs(pdev, cri_index, pvaddr, QCE_MODE_ECB, + true); + _setup_cipher_aes_cmdlistptrs(pdev, cri_index, pvaddr, QCE_MODE_XTS, + true); + _setup_cipher_aes_cmdlistptrs(pdev, cri_index, pvaddr, QCE_MODE_CBC, + false); + _setup_cipher_aes_cmdlistptrs(pdev, cri_index, pvaddr, QCE_MODE_CTR, + false); + _setup_cipher_aes_cmdlistptrs(pdev, cri_index, pvaddr, QCE_MODE_ECB, + false); + _setup_cipher_aes_cmdlistptrs(pdev, cri_index, pvaddr, QCE_MODE_XTS, + false); + + _setup_cipher_des_cmdlistptrs(pdev, cri_index, pvaddr, CIPHER_ALG_DES, + true); + _setup_cipher_des_cmdlistptrs(pdev, cri_index, pvaddr, CIPHER_ALG_DES, + false); + _setup_cipher_des_cmdlistptrs(pdev, cri_index, pvaddr, CIPHER_ALG_3DES, + true); + _setup_cipher_des_cmdlistptrs(pdev, cri_index, pvaddr, CIPHER_ALG_3DES, + false); + + _setup_auth_cmdlistptrs(pdev, cri_index, pvaddr, QCE_HASH_SHA1, + false); + _setup_auth_cmdlistptrs(pdev, cri_index, pvaddr, QCE_HASH_SHA256, + false); + + _setup_auth_cmdlistptrs(pdev, cri_index, pvaddr, QCE_HASH_SHA1_HMAC, + false); + _setup_auth_cmdlistptrs(pdev, cri_index, pvaddr, QCE_HASH_SHA256_HMAC, + false); + + _setup_auth_cmdlistptrs(pdev, cri_index, pvaddr, QCE_HASH_AES_CMAC, + true); + _setup_auth_cmdlistptrs(pdev, cri_index, pvaddr, QCE_HASH_AES_CMAC, + false); + + _setup_aead_cmdlistptrs(pdev, cri_index, pvaddr, CIPHER_ALG_DES, + QCE_MODE_CBC, DES_KEY_SIZE, true); + _setup_aead_cmdlistptrs(pdev, cri_index, pvaddr, CIPHER_ALG_3DES, + QCE_MODE_CBC, DES3_EDE_KEY_SIZE, true); + _setup_aead_cmdlistptrs(pdev, cri_index, pvaddr, CIPHER_ALG_AES, + QCE_MODE_CBC, AES128_KEY_SIZE, true); + _setup_aead_cmdlistptrs(pdev, cri_index, pvaddr, CIPHER_ALG_AES, + QCE_MODE_CBC, AES256_KEY_SIZE, true); + _setup_aead_cmdlistptrs(pdev, cri_index, pvaddr, CIPHER_ALG_DES, + QCE_MODE_CBC, DES_KEY_SIZE, false); + _setup_aead_cmdlistptrs(pdev, cri_index, pvaddr, CIPHER_ALG_3DES, + QCE_MODE_CBC, DES3_EDE_KEY_SIZE, false); + _setup_aead_cmdlistptrs(pdev, cri_index, pvaddr, CIPHER_ALG_AES, + QCE_MODE_CBC, AES128_KEY_SIZE, false); + _setup_aead_cmdlistptrs(pdev, cri_index, pvaddr, CIPHER_ALG_AES, + QCE_MODE_CBC, AES256_KEY_SIZE, false); + + _setup_cipher_null_cmdlistptrs(pdev, cri_index, pvaddr); + + _setup_aead_ccm_cmdlistptrs(pdev, cri_index, pvaddr, true); + _setup_aead_ccm_cmdlistptrs(pdev, cri_index, pvaddr, false); + _setup_f8_cmdlistptrs(pdev, cri_index, pvaddr, QCE_OTA_ALGO_KASUMI); + _setup_f8_cmdlistptrs(pdev, cri_index, pvaddr, QCE_OTA_ALGO_SNOW3G); + _setup_f9_cmdlistptrs(pdev, cri_index, pvaddr, QCE_OTA_ALGO_KASUMI); + _setup_f9_cmdlistptrs(pdev, cri_index, pvaddr, QCE_OTA_ALGO_SNOW3G); + _setup_unlock_pipe_cmdlistptrs(pdev, cri_index, pvaddr); + + return 0; +} + +static int qce_setup_ce_sps_data(struct qce_device *pce_dev) +{ + unsigned char *vaddr; + int i; + unsigned char *iovec_vaddr; + int iovec_memsize; + + vaddr = pce_dev->coh_vmem; + vaddr = (unsigned char *)ALIGN(((uintptr_t)vaddr), + pce_dev->ce_bam_info.ce_burst_size); + iovec_vaddr = pce_dev->iovec_vmem; + iovec_memsize = pce_dev->iovec_memsize; + for (i = 0; i < MAX_QCE_ALLOC_BAM_REQ; i++) { + /* Allow for 256 descriptor (cmd and data) entries per pipe */ + pce_dev->ce_request_info[i].ce_sps.in_transfer.iovec = + (struct sps_iovec *)iovec_vaddr; + pce_dev->ce_request_info[i].ce_sps.in_transfer.iovec_phys = + virt_to_phys(pce_dev->ce_request_info[i]. + ce_sps.in_transfer.iovec); + iovec_vaddr += TOTAL_IOVEC_SPACE_PER_PIPE; + iovec_memsize -= TOTAL_IOVEC_SPACE_PER_PIPE; + pce_dev->ce_request_info[i].ce_sps.out_transfer.iovec = + (struct sps_iovec *)iovec_vaddr; + pce_dev->ce_request_info[i].ce_sps.out_transfer.iovec_phys = + virt_to_phys(pce_dev->ce_request_info[i]. + ce_sps.out_transfer.iovec); + iovec_vaddr += TOTAL_IOVEC_SPACE_PER_PIPE; + iovec_memsize -= TOTAL_IOVEC_SPACE_PER_PIPE; + if (pce_dev->support_cmd_dscr) + qce_setup_cmdlistptrs(pce_dev, i, &vaddr); + vaddr = (unsigned char *)ALIGN(((uintptr_t)vaddr), + pce_dev->ce_bam_info.ce_burst_size); + pce_dev->ce_request_info[i].ce_sps.result_dump = + (uintptr_t)vaddr; + pce_dev->ce_request_info[i].ce_sps.result_dump_phy = + GET_PHYS_ADDR((uintptr_t)vaddr); + pce_dev->ce_request_info[i].ce_sps.result = + (struct ce_result_dump_format *)vaddr; + vaddr += CRYPTO_RESULT_DUMP_SIZE; + + pce_dev->ce_request_info[i].ce_sps.result_dump_null = + (uintptr_t)vaddr; + pce_dev->ce_request_info[i].ce_sps.result_dump_null_phy = + GET_PHYS_ADDR((uintptr_t)vaddr); + pce_dev->ce_request_info[i].ce_sps.result_null = + (struct ce_result_dump_format *)vaddr; + vaddr += CRYPTO_RESULT_DUMP_SIZE; + + pce_dev->ce_request_info[i].ce_sps.ignore_buffer = + (uintptr_t)vaddr; + vaddr += pce_dev->ce_bam_info.ce_burst_size * 2; + } + if ((vaddr - pce_dev->coh_vmem) > pce_dev->memsize || + iovec_memsize < 0) + panic("qce50: Not enough coherent memory. Allocate %x , need %lx\n", + pce_dev->memsize, (uintptr_t)vaddr - + (uintptr_t)pce_dev->coh_vmem); + return 0; +} + +static int qce_init_ce_cfg_val(struct qce_device *pce_dev) +{ + uint32_t beats = (pce_dev->ce_bam_info.ce_burst_size >> 3) - 1; + uint32_t pipe_pair = pce_dev->ce_bam_info.pipe_pair_index; + + pce_dev->reg.crypto_cfg_be = (beats << CRYPTO_REQ_SIZE) | + BIT(CRYPTO_MASK_DOUT_INTR) | BIT(CRYPTO_MASK_DIN_INTR) | + BIT(CRYPTO_MASK_OP_DONE_INTR) | (0 << CRYPTO_HIGH_SPD_EN_N) | + (pipe_pair << CRYPTO_PIPE_SET_SELECT); + + pce_dev->reg.crypto_cfg_le = + (pce_dev->reg.crypto_cfg_be | CRYPTO_LITTLE_ENDIAN_MASK); + + /* Initialize encr_cfg register for AES alg */ + pce_dev->reg.encr_cfg_aes_cbc_128 = + (CRYPTO_ENCR_KEY_SZ_AES128 << CRYPTO_ENCR_KEY_SZ) | + (CRYPTO_ENCR_ALG_AES << CRYPTO_ENCR_ALG) | + (CRYPTO_ENCR_MODE_CBC << CRYPTO_ENCR_MODE); + + pce_dev->reg.encr_cfg_aes_cbc_256 = + (CRYPTO_ENCR_KEY_SZ_AES256 << CRYPTO_ENCR_KEY_SZ) | + (CRYPTO_ENCR_ALG_AES << CRYPTO_ENCR_ALG) | + (CRYPTO_ENCR_MODE_CBC << CRYPTO_ENCR_MODE); + + pce_dev->reg.encr_cfg_aes_ctr_128 = + (CRYPTO_ENCR_KEY_SZ_AES128 << CRYPTO_ENCR_KEY_SZ) | + (CRYPTO_ENCR_ALG_AES << CRYPTO_ENCR_ALG) | + (CRYPTO_ENCR_MODE_CTR << CRYPTO_ENCR_MODE); + + pce_dev->reg.encr_cfg_aes_ctr_256 = + (CRYPTO_ENCR_KEY_SZ_AES256 << CRYPTO_ENCR_KEY_SZ) | + (CRYPTO_ENCR_ALG_AES << CRYPTO_ENCR_ALG) | + (CRYPTO_ENCR_MODE_CTR << CRYPTO_ENCR_MODE); + + pce_dev->reg.encr_cfg_aes_xts_128 = + (CRYPTO_ENCR_KEY_SZ_AES128 << CRYPTO_ENCR_KEY_SZ) | + (CRYPTO_ENCR_ALG_AES << CRYPTO_ENCR_ALG) | + (CRYPTO_ENCR_MODE_XTS << CRYPTO_ENCR_MODE); + + pce_dev->reg.encr_cfg_aes_xts_256 = + (CRYPTO_ENCR_KEY_SZ_AES256 << CRYPTO_ENCR_KEY_SZ) | + (CRYPTO_ENCR_ALG_AES << CRYPTO_ENCR_ALG) | + (CRYPTO_ENCR_MODE_XTS << CRYPTO_ENCR_MODE); + + pce_dev->reg.encr_cfg_aes_ecb_128 = + (CRYPTO_ENCR_KEY_SZ_AES128 << CRYPTO_ENCR_KEY_SZ) | + (CRYPTO_ENCR_ALG_AES << CRYPTO_ENCR_ALG) | + (CRYPTO_ENCR_MODE_ECB << CRYPTO_ENCR_MODE); + + pce_dev->reg.encr_cfg_aes_ecb_256 = + (CRYPTO_ENCR_KEY_SZ_AES256 << CRYPTO_ENCR_KEY_SZ) | + (CRYPTO_ENCR_ALG_AES << CRYPTO_ENCR_ALG) | + (CRYPTO_ENCR_MODE_ECB << CRYPTO_ENCR_MODE); + + pce_dev->reg.encr_cfg_aes_ccm_128 = + (CRYPTO_ENCR_KEY_SZ_AES128 << CRYPTO_ENCR_KEY_SZ) | + (CRYPTO_ENCR_ALG_AES << CRYPTO_ENCR_ALG) | + (CRYPTO_ENCR_MODE_CCM << CRYPTO_ENCR_MODE)| + (CRYPTO_LAST_CCM_XFR << CRYPTO_LAST_CCM); + + pce_dev->reg.encr_cfg_aes_ccm_256 = + (CRYPTO_ENCR_KEY_SZ_AES256 << CRYPTO_ENCR_KEY_SZ) | + (CRYPTO_ENCR_ALG_AES << CRYPTO_ENCR_ALG) | + (CRYPTO_ENCR_MODE_CCM << CRYPTO_ENCR_MODE) | + (CRYPTO_LAST_CCM_XFR << CRYPTO_LAST_CCM); + + /* Initialize encr_cfg register for DES alg */ + pce_dev->reg.encr_cfg_des_ecb = + (CRYPTO_ENCR_KEY_SZ_DES << CRYPTO_ENCR_KEY_SZ) | + (CRYPTO_ENCR_ALG_DES << CRYPTO_ENCR_ALG) | + (CRYPTO_ENCR_MODE_ECB << CRYPTO_ENCR_MODE); + + pce_dev->reg.encr_cfg_des_cbc = + (CRYPTO_ENCR_KEY_SZ_DES << CRYPTO_ENCR_KEY_SZ) | + (CRYPTO_ENCR_ALG_DES << CRYPTO_ENCR_ALG) | + (CRYPTO_ENCR_MODE_CBC << CRYPTO_ENCR_MODE); + + pce_dev->reg.encr_cfg_3des_ecb = + (CRYPTO_ENCR_KEY_SZ_3DES << CRYPTO_ENCR_KEY_SZ) | + (CRYPTO_ENCR_ALG_DES << CRYPTO_ENCR_ALG) | + (CRYPTO_ENCR_MODE_ECB << CRYPTO_ENCR_MODE); + + pce_dev->reg.encr_cfg_3des_cbc = + (CRYPTO_ENCR_KEY_SZ_3DES << CRYPTO_ENCR_KEY_SZ) | + (CRYPTO_ENCR_ALG_DES << CRYPTO_ENCR_ALG) | + (CRYPTO_ENCR_MODE_CBC << CRYPTO_ENCR_MODE); + + /* Initialize encr_cfg register for kasumi/snow3g alg */ + pce_dev->reg.encr_cfg_kasumi = + (CRYPTO_ENCR_ALG_KASUMI << CRYPTO_ENCR_ALG); + + pce_dev->reg.encr_cfg_snow3g = + (CRYPTO_ENCR_ALG_SNOW_3G << CRYPTO_ENCR_ALG); + + /* Initialize auth_cfg register for CMAC alg */ + pce_dev->reg.auth_cfg_cmac_128 = + (1 << CRYPTO_LAST) | (1 << CRYPTO_FIRST) | + (CRYPTO_AUTH_MODE_CMAC << CRYPTO_AUTH_MODE)| + (CRYPTO_AUTH_SIZE_ENUM_16_BYTES << CRYPTO_AUTH_SIZE) | + (CRYPTO_AUTH_ALG_AES << CRYPTO_AUTH_ALG) | + (CRYPTO_AUTH_KEY_SZ_AES128 << CRYPTO_AUTH_KEY_SIZE); + + pce_dev->reg.auth_cfg_cmac_256 = + (1 << CRYPTO_LAST) | (1 << CRYPTO_FIRST) | + (CRYPTO_AUTH_MODE_CMAC << CRYPTO_AUTH_MODE)| + (CRYPTO_AUTH_SIZE_ENUM_16_BYTES << CRYPTO_AUTH_SIZE) | + (CRYPTO_AUTH_ALG_AES << CRYPTO_AUTH_ALG) | + (CRYPTO_AUTH_KEY_SZ_AES256 << CRYPTO_AUTH_KEY_SIZE); + + /* Initialize auth_cfg register for HMAC alg */ + pce_dev->reg.auth_cfg_hmac_sha1 = + (CRYPTO_AUTH_MODE_HMAC << CRYPTO_AUTH_MODE)| + (CRYPTO_AUTH_SIZE_SHA1 << CRYPTO_AUTH_SIZE) | + (CRYPTO_AUTH_ALG_SHA << CRYPTO_AUTH_ALG) | + (CRYPTO_AUTH_POS_BEFORE << CRYPTO_AUTH_POS); + + pce_dev->reg.auth_cfg_hmac_sha256 = + (CRYPTO_AUTH_MODE_HMAC << CRYPTO_AUTH_MODE)| + (CRYPTO_AUTH_SIZE_SHA256 << CRYPTO_AUTH_SIZE) | + (CRYPTO_AUTH_ALG_SHA << CRYPTO_AUTH_ALG) | + (CRYPTO_AUTH_POS_BEFORE << CRYPTO_AUTH_POS); + + /* Initialize auth_cfg register for SHA1/256 alg */ + pce_dev->reg.auth_cfg_sha1 = + (CRYPTO_AUTH_MODE_HASH << CRYPTO_AUTH_MODE)| + (CRYPTO_AUTH_SIZE_SHA1 << CRYPTO_AUTH_SIZE) | + (CRYPTO_AUTH_ALG_SHA << CRYPTO_AUTH_ALG) | + (CRYPTO_AUTH_POS_BEFORE << CRYPTO_AUTH_POS); + + pce_dev->reg.auth_cfg_sha256 = + (CRYPTO_AUTH_MODE_HASH << CRYPTO_AUTH_MODE)| + (CRYPTO_AUTH_SIZE_SHA256 << CRYPTO_AUTH_SIZE) | + (CRYPTO_AUTH_ALG_SHA << CRYPTO_AUTH_ALG) | + (CRYPTO_AUTH_POS_BEFORE << CRYPTO_AUTH_POS); + + /* Initialize auth_cfg register for AEAD alg */ + pce_dev->reg.auth_cfg_aead_sha1_hmac = + (CRYPTO_AUTH_MODE_HMAC << CRYPTO_AUTH_MODE)| + (CRYPTO_AUTH_SIZE_SHA1 << CRYPTO_AUTH_SIZE) | + (CRYPTO_AUTH_ALG_SHA << CRYPTO_AUTH_ALG) | + (1 << CRYPTO_LAST) | (1 << CRYPTO_FIRST); + + pce_dev->reg.auth_cfg_aead_sha256_hmac = + (CRYPTO_AUTH_MODE_HMAC << CRYPTO_AUTH_MODE)| + (CRYPTO_AUTH_SIZE_SHA256 << CRYPTO_AUTH_SIZE) | + (CRYPTO_AUTH_ALG_SHA << CRYPTO_AUTH_ALG) | + (1 << CRYPTO_LAST) | (1 << CRYPTO_FIRST); + + pce_dev->reg.auth_cfg_aes_ccm_128 = + (1 << CRYPTO_LAST) | (1 << CRYPTO_FIRST) | + (CRYPTO_AUTH_MODE_CCM << CRYPTO_AUTH_MODE)| + (CRYPTO_AUTH_ALG_AES << CRYPTO_AUTH_ALG) | + (CRYPTO_AUTH_KEY_SZ_AES128 << CRYPTO_AUTH_KEY_SIZE) | + ((MAX_NONCE/sizeof(uint32_t)) << CRYPTO_AUTH_NONCE_NUM_WORDS); + pce_dev->reg.auth_cfg_aes_ccm_128 &= ~(1 << CRYPTO_USE_HW_KEY_AUTH); + + pce_dev->reg.auth_cfg_aes_ccm_256 = + (1 << CRYPTO_LAST) | (1 << CRYPTO_FIRST) | + (CRYPTO_AUTH_MODE_CCM << CRYPTO_AUTH_MODE)| + (CRYPTO_AUTH_ALG_AES << CRYPTO_AUTH_ALG) | + (CRYPTO_AUTH_KEY_SZ_AES256 << CRYPTO_AUTH_KEY_SIZE) | + ((MAX_NONCE/sizeof(uint32_t)) << CRYPTO_AUTH_NONCE_NUM_WORDS); + pce_dev->reg.auth_cfg_aes_ccm_256 &= ~(1 << CRYPTO_USE_HW_KEY_AUTH); + + /* Initialize auth_cfg register for kasumi/snow3g */ + pce_dev->reg.auth_cfg_kasumi = + (CRYPTO_AUTH_ALG_KASUMI << CRYPTO_AUTH_ALG) | + BIT(CRYPTO_FIRST) | BIT(CRYPTO_LAST); + pce_dev->reg.auth_cfg_snow3g = + (CRYPTO_AUTH_ALG_SNOW3G << CRYPTO_AUTH_ALG) | + BIT(CRYPTO_FIRST) | BIT(CRYPTO_LAST); + return 0; +} + +static void _qce_ccm_get_around_input(struct qce_device *pce_dev, + struct ce_request_info *preq_info, enum qce_cipher_dir_enum dir) +{ + struct qce_cmdlist_info *cmdlistinfo; + struct ce_sps_data *pce_sps_data; + + pce_sps_data = &preq_info->ce_sps; + if ((dir == QCE_DECRYPT) && pce_dev->no_get_around && + !(pce_dev->no_ccm_mac_status_get_around)) { + cmdlistinfo = &pce_sps_data->cmdlistptr.cipher_null; + _qce_sps_add_cmd(pce_dev, 0, cmdlistinfo, + &pce_sps_data->in_transfer); + _qce_sps_add_data(GET_PHYS_ADDR(pce_sps_data->ignore_buffer), + pce_dev->ce_bam_info.ce_burst_size, + &pce_sps_data->in_transfer); + _qce_set_flag(&pce_sps_data->in_transfer, + SPS_IOVEC_FLAG_EOT | SPS_IOVEC_FLAG_NWD); + } +} + +static void _qce_ccm_get_around_output(struct qce_device *pce_dev, + struct ce_request_info *preq_info, enum qce_cipher_dir_enum dir) +{ + struct ce_sps_data *pce_sps_data; + + pce_sps_data = &preq_info->ce_sps; + + if ((dir == QCE_DECRYPT) && pce_dev->no_get_around && + !(pce_dev->no_ccm_mac_status_get_around)) { + _qce_sps_add_data(GET_PHYS_ADDR(pce_sps_data->ignore_buffer), + pce_dev->ce_bam_info.ce_burst_size, + &pce_sps_data->out_transfer); + _qce_sps_add_data(GET_PHYS_ADDR(pce_sps_data->result_dump_null), + CRYPTO_RESULT_DUMP_SIZE, &pce_sps_data->out_transfer); + } +} + +/* QCE_DUMMY_REQ */ +static void qce_dummy_complete(void *cookie, unsigned char *digest, + unsigned char *authdata, int ret) +{ + if (!cookie) + pr_err("invalid cookie\n"); +} + +static int qce_dummy_req(struct qce_device *pce_dev) +{ + int ret = 0; + + if (!(atomic_xchg(&pce_dev->ce_request_info[DUMMY_REQ_INDEX]. + in_use, true) == false)) + return -EBUSY; + ret = qce_process_sha_req(pce_dev, NULL); + pce_dev->qce_stats.no_of_dummy_reqs++; + return ret; +} + +static int select_mode(struct qce_device *pce_dev, + struct ce_request_info *preq_info) +{ + struct ce_sps_data *pce_sps_data = &preq_info->ce_sps; + unsigned int no_of_queued_req; + unsigned int cadence; + + if (!pce_dev->no_get_around) { + _qce_set_flag(&pce_sps_data->out_transfer, SPS_IOVEC_FLAG_INT); + return 0; + } + + /* + * claim ownership of device + */ +again: + if (cmpxchg(&pce_dev->owner, QCE_OWNER_NONE, QCE_OWNER_CLIENT) + != QCE_OWNER_NONE) { + ndelay(40); + goto again; + } + no_of_queued_req = atomic_inc_return(&pce_dev->no_of_queued_req); + if (pce_dev->mode == IN_INTERRUPT_MODE) { + if (no_of_queued_req >= MAX_BUNCH_MODE_REQ) { + pce_dev->mode = IN_BUNCH_MODE; + pr_debug("pcedev %d mode switch to BUNCH\n", + pce_dev->dev_no); + _qce_set_flag(&pce_sps_data->out_transfer, + SPS_IOVEC_FLAG_INT); + pce_dev->intr_cadence = 0; + atomic_set(&pce_dev->bunch_cmd_seq, 1); + atomic_set(&pce_dev->last_intr_seq, 1); + mod_timer(&(pce_dev->timer), + (jiffies + DELAY_IN_JIFFIES)); + } else { + _qce_set_flag(&pce_sps_data->out_transfer, + SPS_IOVEC_FLAG_INT); + } + } else { + pce_dev->intr_cadence++; + cadence = (preq_info->req_len >> 7) + 1; + if (cadence > SET_INTR_AT_REQ) + cadence = SET_INTR_AT_REQ; + if (pce_dev->intr_cadence < cadence || ((pce_dev->intr_cadence + == cadence) && pce_dev->cadence_flag)) + atomic_inc(&pce_dev->bunch_cmd_seq); + else { + _qce_set_flag(&pce_sps_data->out_transfer, + SPS_IOVEC_FLAG_INT); + pce_dev->intr_cadence = 0; + atomic_set(&pce_dev->bunch_cmd_seq, 0); + atomic_set(&pce_dev->last_intr_seq, 0); + pce_dev->cadence_flag = ~pce_dev->cadence_flag; + } + } + + return 0; +} + +static int _qce_aead_ccm_req(void *handle, struct qce_req *q_req) +{ + int rc = 0; + struct qce_device *pce_dev = (struct qce_device *) handle; + struct aead_request *areq = (struct aead_request *) q_req->areq; + uint32_t authsize = q_req->authsize; + uint32_t totallen_in, out_len; + uint32_t hw_pad_out = 0; + int ce_burst_size; + struct qce_cmdlist_info *cmdlistinfo = NULL; + int req_info = -1; + struct ce_request_info *preq_info; + struct ce_sps_data *pce_sps_data; + + req_info = qce_alloc_req_info(pce_dev); + if (req_info < 0) + return -EBUSY; + preq_info = &pce_dev->ce_request_info[req_info]; + pce_sps_data = &preq_info->ce_sps; + + ce_burst_size = pce_dev->ce_bam_info.ce_burst_size; + totallen_in = areq->cryptlen + q_req->assoclen; + if (q_req->dir == QCE_ENCRYPT) { + q_req->cryptlen = areq->cryptlen; + out_len = areq->cryptlen + authsize; + hw_pad_out = ALIGN(authsize, ce_burst_size) - authsize; + } else { + q_req->cryptlen = areq->cryptlen - authsize; + out_len = q_req->cryptlen; + hw_pad_out = authsize; + } + + /* + * For crypto 5.0 that has burst size alignment requirement + * for data descritpor, + * the agent above(qcrypto) prepares the src scatter list with + * memory starting with associated data, followed by + * data stream to be ciphered. + * The destination scatter list is pointing to the same + * data area as source. + */ + if (pce_dev->ce_bam_info.minor_version == 0) + preq_info->src_nents = count_sg(areq->src, totallen_in); + else + preq_info->src_nents = count_sg(areq->src, areq->cryptlen + + areq->assoclen); + + if (q_req->assoclen) { + preq_info->assoc_nents = count_sg(q_req->asg, q_req->assoclen); + + /* formatted associated data input */ + qce_dma_map_sg(pce_dev->pdev, q_req->asg, + preq_info->assoc_nents, DMA_TO_DEVICE); + preq_info->asg = q_req->asg; + } else { + preq_info->assoc_nents = 0; + preq_info->asg = NULL; + } + /* cipher input */ + qce_dma_map_sg(pce_dev->pdev, areq->src, preq_info->src_nents, + (areq->src == areq->dst) ? DMA_BIDIRECTIONAL : + DMA_TO_DEVICE); + /* cipher + mac output for encryption */ + if (areq->src != areq->dst) { + if (pce_dev->ce_bam_info.minor_version == 0) + /* + * The destination scatter list is pointing to the same + * data area as src. + * Note, the associated data will be pass-through + * at the begining of destination area. + */ + preq_info->dst_nents = count_sg(areq->dst, + out_len + areq->assoclen); + else + preq_info->dst_nents = count_sg(areq->dst, out_len + + areq->assoclen); + + qce_dma_map_sg(pce_dev->pdev, areq->dst, preq_info->dst_nents, + DMA_FROM_DEVICE); + } else { + preq_info->dst_nents = preq_info->src_nents; + } + + if (pce_dev->support_cmd_dscr) { + cmdlistinfo = _ce_get_cipher_cmdlistinfo(pce_dev, req_info, + q_req); + if (cmdlistinfo == NULL) { + pr_err("Unsupported cipher algorithm %d, mode %d\n", + q_req->alg, q_req->mode); + qce_free_req_info(pce_dev, req_info, false); + return -EINVAL; + } + /* set up crypto device */ + rc = _ce_setup_cipher(pce_dev, q_req, totallen_in, + q_req->assoclen, cmdlistinfo); + } else { + /* set up crypto device */ + rc = _ce_setup_cipher_direct(pce_dev, q_req, totallen_in, + q_req->assoclen); + } + + if (rc < 0) + goto bad; + + preq_info->mode = q_req->mode; + + /* setup for callback, and issue command to bam */ + preq_info->areq = q_req->areq; + preq_info->qce_cb = q_req->qce_cb; + preq_info->dir = q_req->dir; + + /* setup xfer type for producer callback handling */ + preq_info->xfer_type = QCE_XFER_AEAD; + preq_info->req_len = totallen_in; + + _qce_sps_iovec_count_init(pce_dev, req_info); + + if (pce_dev->support_cmd_dscr) + _qce_sps_add_cmd(pce_dev, SPS_IOVEC_FLAG_LOCK, cmdlistinfo, + &pce_sps_data->in_transfer); + + if (pce_dev->ce_bam_info.minor_version == 0) { + goto bad; + } else { + if (q_req->assoclen && (_qce_sps_add_sg_data( + pce_dev, q_req->asg, q_req->assoclen, + &pce_sps_data->in_transfer))) + goto bad; + if (_qce_sps_add_sg_data_off(pce_dev, areq->src, areq->cryptlen, + areq->assoclen, + &pce_sps_data->in_transfer)) + goto bad; + _qce_set_flag(&pce_sps_data->in_transfer, + SPS_IOVEC_FLAG_EOT|SPS_IOVEC_FLAG_NWD); + + _qce_ccm_get_around_input(pce_dev, preq_info, q_req->dir); + + if (pce_dev->no_get_around) + _qce_sps_add_cmd(pce_dev, SPS_IOVEC_FLAG_UNLOCK, + &pce_sps_data->cmdlistptr.unlock_all_pipes, + &pce_sps_data->in_transfer); + + /* Pass through to ignore associated data*/ + if (_qce_sps_add_data( + GET_PHYS_ADDR(pce_sps_data->ignore_buffer), + q_req->assoclen, + &pce_sps_data->out_transfer)) + goto bad; + if (_qce_sps_add_sg_data_off(pce_dev, areq->dst, out_len, + areq->assoclen, + &pce_sps_data->out_transfer)) + goto bad; + /* Pass through to ignore hw_pad (padding of the MAC data) */ + if (_qce_sps_add_data( + GET_PHYS_ADDR(pce_sps_data->ignore_buffer), + hw_pad_out, &pce_sps_data->out_transfer)) + goto bad; + if (pce_dev->no_get_around || + totallen_in <= SPS_MAX_PKT_SIZE) { + if (_qce_sps_add_data( + GET_PHYS_ADDR(pce_sps_data->result_dump), + CRYPTO_RESULT_DUMP_SIZE, + &pce_sps_data->out_transfer)) + goto bad; + pce_sps_data->producer_state = QCE_PIPE_STATE_COMP; + } else { + pce_sps_data->producer_state = QCE_PIPE_STATE_IDLE; + } + + _qce_ccm_get_around_output(pce_dev, preq_info, q_req->dir); + + select_mode(pce_dev, preq_info); + rc = _qce_sps_transfer(pce_dev, req_info); + cmpxchg(&pce_dev->owner, QCE_OWNER_CLIENT, QCE_OWNER_NONE); + } + if (rc) + goto bad; + return 0; + +bad: + if (preq_info->assoc_nents) { + qce_dma_unmap_sg(pce_dev->pdev, q_req->asg, + preq_info->assoc_nents, DMA_TO_DEVICE); + } + if (preq_info->src_nents) { + qce_dma_unmap_sg(pce_dev->pdev, areq->src, preq_info->src_nents, + (areq->src == areq->dst) ? DMA_BIDIRECTIONAL : + DMA_TO_DEVICE); + } + if (areq->src != areq->dst) { + qce_dma_unmap_sg(pce_dev->pdev, areq->dst, preq_info->dst_nents, + DMA_FROM_DEVICE); + } + qce_free_req_info(pce_dev, req_info, false); + return rc; +} + +static int _qce_suspend(void *handle) +{ + struct qce_device *pce_dev = (struct qce_device *)handle; + struct sps_pipe *sps_pipe_info; + + if (handle == NULL) + return -ENODEV; + + qce_enable_clk(pce_dev); + + sps_pipe_info = pce_dev->ce_bam_info.consumer.pipe; + sps_disconnect(sps_pipe_info); + + sps_pipe_info = pce_dev->ce_bam_info.producer.pipe; + sps_disconnect(sps_pipe_info); + + qce_disable_clk(pce_dev); + return 0; +} + +static int _qce_resume(void *handle) +{ + struct qce_device *pce_dev = (struct qce_device *)handle; + struct sps_pipe *sps_pipe_info; + struct sps_connect *sps_connect_info; + int rc; + + if (handle == NULL) + return -ENODEV; + + qce_enable_clk(pce_dev); + + sps_pipe_info = pce_dev->ce_bam_info.consumer.pipe; + sps_connect_info = &pce_dev->ce_bam_info.consumer.connect; + memset(sps_connect_info->desc.base, 0x00, sps_connect_info->desc.size); + rc = sps_connect(sps_pipe_info, sps_connect_info); + if (rc) { + pr_err("sps_connect() fail pipe_handle=0x%lx, rc = %d\n", + (uintptr_t)sps_pipe_info, rc); + return rc; + } + sps_pipe_info = pce_dev->ce_bam_info.producer.pipe; + sps_connect_info = &pce_dev->ce_bam_info.producer.connect; + memset(sps_connect_info->desc.base, 0x00, sps_connect_info->desc.size); + rc = sps_connect(sps_pipe_info, sps_connect_info); + if (rc) + pr_err("sps_connect() fail pipe_handle=0x%lx, rc = %d\n", + (uintptr_t)sps_pipe_info, rc); + + rc = sps_register_event(sps_pipe_info, + &pce_dev->ce_bam_info.producer.event); + if (rc) + pr_err("Producer callback registration failed rc = %d\n", rc); + + qce_disable_clk(pce_dev); + return rc; +} + +struct qce_pm_table qce_pm_table = {_qce_suspend, _qce_resume}; +EXPORT_SYMBOL(qce_pm_table); + +int qce_aead_req(void *handle, struct qce_req *q_req) +{ + struct qce_device *pce_dev = (struct qce_device *)handle; + struct aead_request *areq; + uint32_t authsize; + struct crypto_aead *aead; + uint32_t ivsize; + uint32_t totallen; + int rc = 0; + struct qce_cmdlist_info *cmdlistinfo = NULL; + int req_info = -1; + struct ce_sps_data *pce_sps_data; + struct ce_request_info *preq_info; + + if (q_req->mode == QCE_MODE_CCM) + return _qce_aead_ccm_req(handle, q_req); + + req_info = qce_alloc_req_info(pce_dev); + if (req_info < 0) + return -EBUSY; + preq_info = &pce_dev->ce_request_info[req_info]; + pce_sps_data = &preq_info->ce_sps; + areq = (struct aead_request *) q_req->areq; + aead = crypto_aead_reqtfm(areq); + ivsize = crypto_aead_ivsize(aead); + q_req->ivsize = ivsize; + authsize = q_req->authsize; + if (q_req->dir == QCE_ENCRYPT) + q_req->cryptlen = areq->cryptlen; + else + q_req->cryptlen = areq->cryptlen - authsize; + + if (q_req->cryptlen > UINT_MAX - areq->assoclen) { + pr_err("Integer overflow on total aead req length.\n"); + return -EINVAL; + } + + totallen = q_req->cryptlen + areq->assoclen; + + if (pce_dev->support_cmd_dscr) { + cmdlistinfo = _ce_get_aead_cmdlistinfo(pce_dev, + req_info, q_req); + if (cmdlistinfo == NULL) { + pr_err("Unsupported aead ciphering algorithm %d, mode %d, ciphering key length %d, auth digest size %d\n", + q_req->alg, q_req->mode, q_req->encklen, + q_req->authsize); + qce_free_req_info(pce_dev, req_info, false); + return -EINVAL; + } + /* set up crypto device */ + rc = _ce_setup_aead(pce_dev, q_req, totallen, + areq->assoclen, cmdlistinfo); + if (rc < 0) { + qce_free_req_info(pce_dev, req_info, false); + return -EINVAL; + } + } + + /* + * For crypto 5.0 that has burst size alignment requirement + * for data descritpor, + * the agent above(qcrypto) prepares the src scatter list with + * memory starting with associated data, followed by + * iv, and data stream to be ciphered. + */ + preq_info->src_nents = count_sg(areq->src, totallen); + + + /* cipher input */ + qce_dma_map_sg(pce_dev->pdev, areq->src, preq_info->src_nents, + (areq->src == areq->dst) ? DMA_BIDIRECTIONAL : + DMA_TO_DEVICE); + /* cipher output for encryption */ + if (areq->src != areq->dst) { + preq_info->dst_nents = count_sg(areq->dst, totallen); + + qce_dma_map_sg(pce_dev->pdev, areq->dst, preq_info->dst_nents, + DMA_FROM_DEVICE); + } + + + /* setup for callback, and issue command to bam */ + preq_info->areq = q_req->areq; + preq_info->qce_cb = q_req->qce_cb; + preq_info->dir = q_req->dir; + preq_info->asg = NULL; + + /* setup xfer type for producer callback handling */ + preq_info->xfer_type = QCE_XFER_AEAD; + preq_info->req_len = totallen; + + _qce_sps_iovec_count_init(pce_dev, req_info); + + if (pce_dev->support_cmd_dscr) { + _qce_sps_add_cmd(pce_dev, SPS_IOVEC_FLAG_LOCK, cmdlistinfo, + &pce_sps_data->in_transfer); + } else { + rc = _ce_setup_aead_direct(pce_dev, q_req, totallen, + areq->assoclen); + if (rc) + goto bad; + } + + preq_info->mode = q_req->mode; + + if (pce_dev->ce_bam_info.minor_version == 0) { + if (_qce_sps_add_sg_data(pce_dev, areq->src, totallen, + &pce_sps_data->in_transfer)) + goto bad; + + _qce_set_flag(&pce_sps_data->in_transfer, + SPS_IOVEC_FLAG_EOT|SPS_IOVEC_FLAG_NWD); + + if (_qce_sps_add_sg_data(pce_dev, areq->dst, totallen, + &pce_sps_data->out_transfer)) + goto bad; + if (totallen > SPS_MAX_PKT_SIZE) { + _qce_set_flag(&pce_sps_data->out_transfer, + SPS_IOVEC_FLAG_INT); + pce_sps_data->producer_state = QCE_PIPE_STATE_IDLE; + } else { + if (_qce_sps_add_data(GET_PHYS_ADDR( + pce_sps_data->result_dump), + CRYPTO_RESULT_DUMP_SIZE, + &pce_sps_data->out_transfer)) + goto bad; + _qce_set_flag(&pce_sps_data->out_transfer, + SPS_IOVEC_FLAG_INT); + pce_sps_data->producer_state = QCE_PIPE_STATE_COMP; + } + rc = _qce_sps_transfer(pce_dev, req_info); + } else { + if (_qce_sps_add_sg_data(pce_dev, areq->src, totallen, + &pce_sps_data->in_transfer)) + goto bad; + _qce_set_flag(&pce_sps_data->in_transfer, + SPS_IOVEC_FLAG_EOT|SPS_IOVEC_FLAG_NWD); + + if (pce_dev->no_get_around) + _qce_sps_add_cmd(pce_dev, SPS_IOVEC_FLAG_UNLOCK, + &pce_sps_data->cmdlistptr.unlock_all_pipes, + &pce_sps_data->in_transfer); + + if (_qce_sps_add_sg_data(pce_dev, areq->dst, totallen, + &pce_sps_data->out_transfer)) + goto bad; + + if (pce_dev->no_get_around || totallen <= SPS_MAX_PKT_SIZE) { + if (_qce_sps_add_data( + GET_PHYS_ADDR(pce_sps_data->result_dump), + CRYPTO_RESULT_DUMP_SIZE, + &pce_sps_data->out_transfer)) + goto bad; + pce_sps_data->producer_state = QCE_PIPE_STATE_COMP; + } else { + pce_sps_data->producer_state = QCE_PIPE_STATE_IDLE; + } + select_mode(pce_dev, preq_info); + rc = _qce_sps_transfer(pce_dev, req_info); + cmpxchg(&pce_dev->owner, QCE_OWNER_CLIENT, QCE_OWNER_NONE); + } + if (rc) + goto bad; + return 0; + +bad: + if (preq_info->src_nents) + qce_dma_unmap_sg(pce_dev->pdev, areq->src, preq_info->src_nents, + (areq->src == areq->dst) ? DMA_BIDIRECTIONAL : + DMA_TO_DEVICE); + if (areq->src != areq->dst) + qce_dma_unmap_sg(pce_dev->pdev, areq->dst, preq_info->dst_nents, + DMA_FROM_DEVICE); + qce_free_req_info(pce_dev, req_info, false); + + return rc; +} +EXPORT_SYMBOL(qce_aead_req); + +int qce_ablk_cipher_req(void *handle, struct qce_req *c_req) +{ + int rc = 0; + struct qce_device *pce_dev = (struct qce_device *) handle; + struct ablkcipher_request *areq = (struct ablkcipher_request *) + c_req->areq; + struct qce_cmdlist_info *cmdlistinfo = NULL; + int req_info = -1; + struct ce_sps_data *pce_sps_data; + struct ce_request_info *preq_info; + + req_info = qce_alloc_req_info(pce_dev); + if (req_info < 0) + return -EBUSY; + preq_info = &pce_dev->ce_request_info[req_info]; + pce_sps_data = &preq_info->ce_sps; + + preq_info->src_nents = 0; + preq_info->dst_nents = 0; + + /* cipher input */ + preq_info->src_nents = count_sg(areq->src, areq->nbytes); + + qce_dma_map_sg(pce_dev->pdev, areq->src, preq_info->src_nents, + (areq->src == areq->dst) ? DMA_BIDIRECTIONAL : + DMA_TO_DEVICE); + /* cipher output */ + if (areq->src != areq->dst) { + preq_info->dst_nents = count_sg(areq->dst, areq->nbytes); + qce_dma_map_sg(pce_dev->pdev, areq->dst, + preq_info->dst_nents, DMA_FROM_DEVICE); + } else { + preq_info->dst_nents = preq_info->src_nents; + } + preq_info->dir = c_req->dir; + if ((pce_dev->ce_bam_info.minor_version == 0) && + (preq_info->dir == QCE_DECRYPT) && + (c_req->mode == QCE_MODE_CBC)) { + memcpy(preq_info->dec_iv, (unsigned char *) + sg_virt(areq->src) + areq->src->length - 16, + NUM_OF_CRYPTO_CNTR_IV_REG * CRYPTO_REG_SIZE); + } + + /* set up crypto device */ + if (pce_dev->support_cmd_dscr) { + cmdlistinfo = _ce_get_cipher_cmdlistinfo(pce_dev, + req_info, c_req); + if (cmdlistinfo == NULL) { + pr_err("Unsupported cipher algorithm %d, mode %d\n", + c_req->alg, c_req->mode); + qce_free_req_info(pce_dev, req_info, false); + return -EINVAL; + } + rc = _ce_setup_cipher(pce_dev, c_req, areq->nbytes, 0, + cmdlistinfo); + } else { + rc = _ce_setup_cipher_direct(pce_dev, c_req, areq->nbytes, 0); + } + if (rc < 0) + goto bad; + + preq_info->mode = c_req->mode; + + /* setup for client callback, and issue command to BAM */ + preq_info->areq = areq; + preq_info->qce_cb = c_req->qce_cb; + + /* setup xfer type for producer callback handling */ + preq_info->xfer_type = QCE_XFER_CIPHERING; + preq_info->req_len = areq->nbytes; + + _qce_sps_iovec_count_init(pce_dev, req_info); + if (pce_dev->support_cmd_dscr) + _qce_sps_add_cmd(pce_dev, SPS_IOVEC_FLAG_LOCK, cmdlistinfo, + &pce_sps_data->in_transfer); + if (_qce_sps_add_sg_data(pce_dev, areq->src, areq->nbytes, + &pce_sps_data->in_transfer)) + goto bad; + _qce_set_flag(&pce_sps_data->in_transfer, + SPS_IOVEC_FLAG_EOT|SPS_IOVEC_FLAG_NWD); + + if (pce_dev->no_get_around) + _qce_sps_add_cmd(pce_dev, SPS_IOVEC_FLAG_UNLOCK, + &pce_sps_data->cmdlistptr.unlock_all_pipes, + &pce_sps_data->in_transfer); + + if (_qce_sps_add_sg_data(pce_dev, areq->dst, areq->nbytes, + &pce_sps_data->out_transfer)) + goto bad; + if (pce_dev->no_get_around || areq->nbytes <= SPS_MAX_PKT_SIZE) { + pce_sps_data->producer_state = QCE_PIPE_STATE_COMP; + if (_qce_sps_add_data( + GET_PHYS_ADDR(pce_sps_data->result_dump), + CRYPTO_RESULT_DUMP_SIZE, + &pce_sps_data->out_transfer)) + goto bad; + } else { + pce_sps_data->producer_state = QCE_PIPE_STATE_IDLE; + } + + select_mode(pce_dev, preq_info); + rc = _qce_sps_transfer(pce_dev, req_info); + cmpxchg(&pce_dev->owner, QCE_OWNER_CLIENT, QCE_OWNER_NONE); + if (rc) + goto bad; + + return 0; +bad: + if (areq->src != areq->dst) { + if (preq_info->dst_nents) { + qce_dma_unmap_sg(pce_dev->pdev, areq->dst, + preq_info->dst_nents, DMA_FROM_DEVICE); + } + } + if (preq_info->src_nents) { + qce_dma_unmap_sg(pce_dev->pdev, areq->src, + preq_info->src_nents, + (areq->src == areq->dst) ? + DMA_BIDIRECTIONAL : DMA_TO_DEVICE); + } + qce_free_req_info(pce_dev, req_info, false); + return rc; +} +EXPORT_SYMBOL(qce_ablk_cipher_req); + +int qce_process_sha_req(void *handle, struct qce_sha_req *sreq) +{ + struct qce_device *pce_dev = (struct qce_device *) handle; + int rc; + + struct ahash_request *areq; + struct qce_cmdlist_info *cmdlistinfo = NULL; + int req_info = -1; + struct ce_sps_data *pce_sps_data; + struct ce_request_info *preq_info; + bool is_dummy = false; + + if (!sreq) { + sreq = &(pce_dev->dummyreq.sreq); + req_info = DUMMY_REQ_INDEX; + is_dummy = true; + } else { + req_info = qce_alloc_req_info(pce_dev); + if (req_info < 0) + return -EBUSY; + } + + areq = (struct ahash_request *)sreq->areq; + preq_info = &pce_dev->ce_request_info[req_info]; + pce_sps_data = &preq_info->ce_sps; + + preq_info->src_nents = count_sg(sreq->src, sreq->size); + qce_dma_map_sg(pce_dev->pdev, sreq->src, preq_info->src_nents, + DMA_TO_DEVICE); + + if (pce_dev->support_cmd_dscr) { + cmdlistinfo = _ce_get_hash_cmdlistinfo(pce_dev, req_info, sreq); + if (cmdlistinfo == NULL) { + pr_err("Unsupported hash algorithm %d\n", sreq->alg); + qce_free_req_info(pce_dev, req_info, false); + return -EINVAL; + } + rc = _ce_setup_hash(pce_dev, sreq, cmdlistinfo); + } else { + rc = _ce_setup_hash_direct(pce_dev, sreq); + } + if (rc < 0) + goto bad; + + preq_info->areq = areq; + preq_info->qce_cb = sreq->qce_cb; + + /* setup xfer type for producer callback handling */ + preq_info->xfer_type = QCE_XFER_HASHING; + preq_info->req_len = sreq->size; + + _qce_sps_iovec_count_init(pce_dev, req_info); + + if (pce_dev->support_cmd_dscr) + _qce_sps_add_cmd(pce_dev, SPS_IOVEC_FLAG_LOCK, cmdlistinfo, + &pce_sps_data->in_transfer); + if (_qce_sps_add_sg_data(pce_dev, areq->src, areq->nbytes, + &pce_sps_data->in_transfer)) + goto bad; + + /* always ensure there is input data. ZLT does not work for bam-ndp */ + if (!areq->nbytes) + _qce_sps_add_data( + GET_PHYS_ADDR(pce_sps_data->ignore_buffer), + pce_dev->ce_bam_info.ce_burst_size, + &pce_sps_data->in_transfer); + _qce_set_flag(&pce_sps_data->in_transfer, + SPS_IOVEC_FLAG_EOT|SPS_IOVEC_FLAG_NWD); + if (pce_dev->no_get_around) + _qce_sps_add_cmd(pce_dev, SPS_IOVEC_FLAG_UNLOCK, + &pce_sps_data->cmdlistptr.unlock_all_pipes, + &pce_sps_data->in_transfer); + + if (_qce_sps_add_data(GET_PHYS_ADDR(pce_sps_data->result_dump), + CRYPTO_RESULT_DUMP_SIZE, + &pce_sps_data->out_transfer)) + goto bad; + + if (is_dummy) { + _qce_set_flag(&pce_sps_data->out_transfer, SPS_IOVEC_FLAG_INT); + rc = _qce_sps_transfer(pce_dev, req_info); + } else { + select_mode(pce_dev, preq_info); + rc = _qce_sps_transfer(pce_dev, req_info); + cmpxchg(&pce_dev->owner, QCE_OWNER_CLIENT, QCE_OWNER_NONE); + } + if (rc) + goto bad; + return 0; +bad: + if (preq_info->src_nents) { + qce_dma_unmap_sg(pce_dev->pdev, sreq->src, + preq_info->src_nents, DMA_TO_DEVICE); + } + qce_free_req_info(pce_dev, req_info, false); + return rc; +} +EXPORT_SYMBOL(qce_process_sha_req); + +int qce_f8_req(void *handle, struct qce_f8_req *req, + void *cookie, qce_comp_func_ptr_t qce_cb) +{ + struct qce_device *pce_dev = (struct qce_device *) handle; + bool key_stream_mode; + dma_addr_t dst; + int rc; + struct qce_cmdlist_info *cmdlistinfo; + int req_info = -1; + struct ce_request_info *preq_info; + struct ce_sps_data *pce_sps_data; + + req_info = qce_alloc_req_info(pce_dev); + if (req_info < 0) + return -EBUSY; + preq_info = &pce_dev->ce_request_info[req_info]; + pce_sps_data = &preq_info->ce_sps; + + switch (req->algorithm) { + case QCE_OTA_ALGO_KASUMI: + cmdlistinfo = &pce_sps_data->cmdlistptr.f8_kasumi; + break; + case QCE_OTA_ALGO_SNOW3G: + cmdlistinfo = &pce_sps_data->cmdlistptr.f8_snow3g; + break; + default: + qce_free_req_info(pce_dev, req_info, false); + return -EINVAL; + }; + + key_stream_mode = (req->data_in == NULL); + + /* don't support key stream mode */ + + if (key_stream_mode || (req->bearer >= QCE_OTA_MAX_BEARER)) { + qce_free_req_info(pce_dev, req_info, false); + return -EINVAL; + } + + /* F8 cipher input */ + preq_info->phy_ota_src = dma_map_single(pce_dev->pdev, + req->data_in, req->data_len, + (req->data_in == req->data_out) ? + DMA_BIDIRECTIONAL : DMA_TO_DEVICE); + + /* F8 cipher output */ + if (req->data_in != req->data_out) { + dst = dma_map_single(pce_dev->pdev, req->data_out, + req->data_len, DMA_FROM_DEVICE); + preq_info->phy_ota_dst = dst; + } else { + /* in place ciphering */ + dst = preq_info->phy_ota_src; + preq_info->phy_ota_dst = 0; + } + preq_info->ota_size = req->data_len; + + + /* set up crypto device */ + if (pce_dev->support_cmd_dscr) + rc = _ce_f8_setup(pce_dev, req, key_stream_mode, 1, 0, + req->data_len, cmdlistinfo); + else + rc = _ce_f8_setup_direct(pce_dev, req, key_stream_mode, 1, 0, + req->data_len); + if (rc < 0) + goto bad; + + /* setup for callback, and issue command to sps */ + preq_info->areq = cookie; + preq_info->qce_cb = qce_cb; + + /* setup xfer type for producer callback handling */ + preq_info->xfer_type = QCE_XFER_F8; + preq_info->req_len = req->data_len; + + _qce_sps_iovec_count_init(pce_dev, req_info); + + if (pce_dev->support_cmd_dscr) + _qce_sps_add_cmd(pce_dev, SPS_IOVEC_FLAG_LOCK, cmdlistinfo, + &pce_sps_data->in_transfer); + + _qce_sps_add_data((uint32_t)preq_info->phy_ota_src, req->data_len, + &pce_sps_data->in_transfer); + + _qce_set_flag(&pce_sps_data->in_transfer, + SPS_IOVEC_FLAG_EOT|SPS_IOVEC_FLAG_NWD); + + _qce_sps_add_cmd(pce_dev, SPS_IOVEC_FLAG_UNLOCK, + &pce_sps_data->cmdlistptr.unlock_all_pipes, + &pce_sps_data->in_transfer); + + _qce_sps_add_data((uint32_t)dst, req->data_len, + &pce_sps_data->out_transfer); + + _qce_sps_add_data(GET_PHYS_ADDR(pce_sps_data->result_dump), + CRYPTO_RESULT_DUMP_SIZE, + &pce_sps_data->out_transfer); + + select_mode(pce_dev, preq_info); + rc = _qce_sps_transfer(pce_dev, req_info); + cmpxchg(&pce_dev->owner, QCE_OWNER_CLIENT, QCE_OWNER_NONE); + if (rc) + goto bad; + return 0; +bad: + if (preq_info->phy_ota_dst != 0) + dma_unmap_single(pce_dev->pdev, preq_info->phy_ota_dst, + req->data_len, DMA_FROM_DEVICE); + if (preq_info->phy_ota_src != 0) + dma_unmap_single(pce_dev->pdev, preq_info->phy_ota_src, + req->data_len, + (req->data_in == req->data_out) ? + DMA_BIDIRECTIONAL : DMA_TO_DEVICE); + qce_free_req_info(pce_dev, req_info, false); + return rc; +} +EXPORT_SYMBOL(qce_f8_req); + +int qce_f8_multi_pkt_req(void *handle, struct qce_f8_multi_pkt_req *mreq, + void *cookie, qce_comp_func_ptr_t qce_cb) +{ + struct qce_device *pce_dev = (struct qce_device *) handle; + uint16_t num_pkt = mreq->num_pkt; + uint16_t cipher_start = mreq->cipher_start; + uint16_t cipher_size = mreq->cipher_size; + struct qce_f8_req *req = &mreq->qce_f8_req; + uint32_t total; + dma_addr_t dst = 0; + int rc = 0; + struct qce_cmdlist_info *cmdlistinfo; + int req_info = -1; + struct ce_request_info *preq_info; + struct ce_sps_data *pce_sps_data; + + req_info = qce_alloc_req_info(pce_dev); + if (req_info < 0) + return -EBUSY; + preq_info = &pce_dev->ce_request_info[req_info]; + pce_sps_data = &preq_info->ce_sps; + + switch (req->algorithm) { + case QCE_OTA_ALGO_KASUMI: + cmdlistinfo = &pce_sps_data->cmdlistptr.f8_kasumi; + break; + case QCE_OTA_ALGO_SNOW3G: + cmdlistinfo = &pce_sps_data->cmdlistptr.f8_snow3g; + break; + default: + qce_free_req_info(pce_dev, req_info, false); + return -EINVAL; + }; + + total = num_pkt * req->data_len; + + /* F8 cipher input */ + preq_info->phy_ota_src = dma_map_single(pce_dev->pdev, + req->data_in, total, + (req->data_in == req->data_out) ? + DMA_BIDIRECTIONAL : DMA_TO_DEVICE); + + /* F8 cipher output */ + if (req->data_in != req->data_out) { + dst = dma_map_single(pce_dev->pdev, req->data_out, total, + DMA_FROM_DEVICE); + preq_info->phy_ota_dst = dst; + } else { + /* in place ciphering */ + dst = preq_info->phy_ota_src; + preq_info->phy_ota_dst = 0; + } + + preq_info->ota_size = total; + + /* set up crypto device */ + if (pce_dev->support_cmd_dscr) + rc = _ce_f8_setup(pce_dev, req, false, num_pkt, cipher_start, + cipher_size, cmdlistinfo); + else + rc = _ce_f8_setup_direct(pce_dev, req, false, num_pkt, + cipher_start, cipher_size); + if (rc) + goto bad; + + /* setup for callback, and issue command to sps */ + preq_info->areq = cookie; + preq_info->qce_cb = qce_cb; + + /* setup xfer type for producer callback handling */ + preq_info->xfer_type = QCE_XFER_F8; + preq_info->req_len = total; + + _qce_sps_iovec_count_init(pce_dev, req_info); + + if (pce_dev->support_cmd_dscr) + _qce_sps_add_cmd(pce_dev, SPS_IOVEC_FLAG_LOCK, cmdlistinfo, + &pce_sps_data->in_transfer); + + _qce_sps_add_data((uint32_t)preq_info->phy_ota_src, total, + &pce_sps_data->in_transfer); + _qce_set_flag(&pce_sps_data->in_transfer, + SPS_IOVEC_FLAG_EOT|SPS_IOVEC_FLAG_NWD); + + _qce_sps_add_cmd(pce_dev, SPS_IOVEC_FLAG_UNLOCK, + &pce_sps_data->cmdlistptr.unlock_all_pipes, + &pce_sps_data->in_transfer); + + _qce_sps_add_data((uint32_t)dst, total, + &pce_sps_data->out_transfer); + + _qce_sps_add_data(GET_PHYS_ADDR(pce_sps_data->result_dump), + CRYPTO_RESULT_DUMP_SIZE, + &pce_sps_data->out_transfer); + + select_mode(pce_dev, preq_info); + rc = _qce_sps_transfer(pce_dev, req_info); + cmpxchg(&pce_dev->owner, QCE_OWNER_CLIENT, QCE_OWNER_NONE); + + if (rc == 0) + return 0; +bad: + if (preq_info->phy_ota_dst) + dma_unmap_single(pce_dev->pdev, preq_info->phy_ota_dst, total, + DMA_FROM_DEVICE); + dma_unmap_single(pce_dev->pdev, preq_info->phy_ota_src, total, + (req->data_in == req->data_out) ? + DMA_BIDIRECTIONAL : DMA_TO_DEVICE); + qce_free_req_info(pce_dev, req_info, false); + return rc; +} +EXPORT_SYMBOL(qce_f8_multi_pkt_req); + +int qce_f9_req(void *handle, struct qce_f9_req *req, void *cookie, + qce_comp_func_ptr_t qce_cb) +{ + struct qce_device *pce_dev = (struct qce_device *) handle; + int rc; + struct qce_cmdlist_info *cmdlistinfo; + int req_info = -1; + struct ce_sps_data *pce_sps_data; + struct ce_request_info *preq_info; + + req_info = qce_alloc_req_info(pce_dev); + if (req_info < 0) + return -EBUSY; + preq_info = &pce_dev->ce_request_info[req_info]; + pce_sps_data = &preq_info->ce_sps; + switch (req->algorithm) { + case QCE_OTA_ALGO_KASUMI: + cmdlistinfo = &pce_sps_data->cmdlistptr.f9_kasumi; + break; + case QCE_OTA_ALGO_SNOW3G: + cmdlistinfo = &pce_sps_data->cmdlistptr.f9_snow3g; + break; + default: + qce_free_req_info(pce_dev, req_info, false); + return -EINVAL; + }; + + preq_info->phy_ota_src = dma_map_single(pce_dev->pdev, req->message, + req->msize, DMA_TO_DEVICE); + + preq_info->ota_size = req->msize; + + if (pce_dev->support_cmd_dscr) + rc = _ce_f9_setup(pce_dev, req, cmdlistinfo); + else + rc = _ce_f9_setup_direct(pce_dev, req); + if (rc < 0) + goto bad; + + /* setup for callback, and issue command to sps */ + preq_info->areq = cookie; + preq_info->qce_cb = qce_cb; + + /* setup xfer type for producer callback handling */ + preq_info->xfer_type = QCE_XFER_F9; + preq_info->req_len = req->msize; + + _qce_sps_iovec_count_init(pce_dev, req_info); + if (pce_dev->support_cmd_dscr) + _qce_sps_add_cmd(pce_dev, SPS_IOVEC_FLAG_LOCK, cmdlistinfo, + &pce_sps_data->in_transfer); + _qce_sps_add_data((uint32_t)preq_info->phy_ota_src, req->msize, + &pce_sps_data->in_transfer); + _qce_set_flag(&pce_sps_data->in_transfer, + SPS_IOVEC_FLAG_EOT|SPS_IOVEC_FLAG_NWD); + + _qce_sps_add_cmd(pce_dev, SPS_IOVEC_FLAG_UNLOCK, + &pce_sps_data->cmdlistptr.unlock_all_pipes, + &pce_sps_data->in_transfer); + + _qce_sps_add_data(GET_PHYS_ADDR(pce_sps_data->result_dump), + CRYPTO_RESULT_DUMP_SIZE, + &pce_sps_data->out_transfer); + + select_mode(pce_dev, preq_info); + rc = _qce_sps_transfer(pce_dev, req_info); + cmpxchg(&pce_dev->owner, QCE_OWNER_CLIENT, QCE_OWNER_NONE); + if (rc) + goto bad; + return 0; +bad: + dma_unmap_single(pce_dev->pdev, preq_info->phy_ota_src, + req->msize, DMA_TO_DEVICE); + qce_free_req_info(pce_dev, req_info, false); + return rc; +} +EXPORT_SYMBOL(qce_f9_req); + +static int __qce_get_device_tree_data(struct platform_device *pdev, + struct qce_device *pce_dev) +{ + struct resource *resource; + int rc = 0; + + pce_dev->is_shared = of_property_read_bool((&pdev->dev)->of_node, + "qcom,ce-hw-shared"); + pce_dev->support_hw_key = of_property_read_bool((&pdev->dev)->of_node, + "qcom,ce-hw-key"); + + pce_dev->use_sw_aes_cbc_ecb_ctr_algo = + of_property_read_bool((&pdev->dev)->of_node, + "qcom,use-sw-aes-cbc-ecb-ctr-algo"); + pce_dev->use_sw_aead_algo = + of_property_read_bool((&pdev->dev)->of_node, + "qcom,use-sw-aead-algo"); + pce_dev->use_sw_aes_xts_algo = + of_property_read_bool((&pdev->dev)->of_node, + "qcom,use-sw-aes-xts-algo"); + pce_dev->use_sw_ahash_algo = + of_property_read_bool((&pdev->dev)->of_node, + "qcom,use-sw-ahash-algo"); + pce_dev->use_sw_hmac_algo = + of_property_read_bool((&pdev->dev)->of_node, + "qcom,use-sw-hmac-algo"); + pce_dev->use_sw_aes_ccm_algo = + of_property_read_bool((&pdev->dev)->of_node, + "qcom,use-sw-aes-ccm-algo"); + pce_dev->support_clk_mgmt_sus_res = of_property_read_bool( + (&pdev->dev)->of_node, "qcom,clk-mgmt-sus-res"); + pce_dev->support_only_core_src_clk = of_property_read_bool( + (&pdev->dev)->of_node, "qcom,support-core-clk-only"); + + if (of_property_read_u32((&pdev->dev)->of_node, + "qcom,bam-pipe-pair", + &pce_dev->ce_bam_info.pipe_pair_index)) { + pr_err("Fail to get bam pipe pair information.\n"); + return -EINVAL; + } + if (of_property_read_u32((&pdev->dev)->of_node, + "qcom,ce-device", + &pce_dev->ce_bam_info.ce_device)) { + pr_err("Fail to get CE device information.\n"); + return -EINVAL; + } + if (of_property_read_u32((&pdev->dev)->of_node, + "qcom,ce-hw-instance", + &pce_dev->ce_bam_info.ce_hw_instance)) { + pr_err("Fail to get CE hw instance information.\n"); + return -EINVAL; + } + if (of_property_read_u32((&pdev->dev)->of_node, + "qcom,bam-ee", + &pce_dev->ce_bam_info.bam_ee)) { + pr_info("BAM Apps EE is not defined, setting to default 1\n"); + pce_dev->ce_bam_info.bam_ee = 1; + } + if (of_property_read_u32((&pdev->dev)->of_node, + "qcom,ce-opp-freq", + &pce_dev->ce_opp_freq_hz)) { + pr_info("CE operating frequency is not defined, setting to default 100MHZ\n"); + pce_dev->ce_opp_freq_hz = CE_CLK_100MHZ; + } + pce_dev->ce_bam_info.dest_pipe_index = + 2 * pce_dev->ce_bam_info.pipe_pair_index; + pce_dev->ce_bam_info.src_pipe_index = + pce_dev->ce_bam_info.dest_pipe_index + 1; + + resource = platform_get_resource_byname(pdev, IORESOURCE_MEM, + "crypto-base"); + if (resource) { + pce_dev->phy_iobase = resource->start; + pce_dev->iobase = ioremap_nocache(resource->start, + resource_size(resource)); + if (!pce_dev->iobase) { + pr_err("Can not map CRYPTO io memory\n"); + return -ENOMEM; + } + } else { + pr_err("CRYPTO HW mem unavailable.\n"); + return -ENODEV; + } + + resource = platform_get_resource_byname(pdev, IORESOURCE_MEM, + "crypto-bam-base"); + if (resource) { + pce_dev->bam_mem = resource->start; + pce_dev->bam_mem_size = resource_size(resource); + } else { + pr_err("CRYPTO BAM mem unavailable.\n"); + rc = -ENODEV; + goto err_getting_bam_info; + } + + resource = platform_get_resource(pdev, IORESOURCE_IRQ, 0); + if (resource) { + pce_dev->ce_bam_info.bam_irq = resource->start; + } else { + pr_err("CRYPTO BAM IRQ unavailable.\n"); + goto err_dev; + } + return rc; +err_dev: + if (pce_dev->ce_bam_info.bam_iobase) + iounmap(pce_dev->ce_bam_info.bam_iobase); + +err_getting_bam_info: + if (pce_dev->iobase) + iounmap(pce_dev->iobase); + + return rc; +} + +static int __qce_init_clk(struct qce_device *pce_dev) +{ + int rc = 0; + + pce_dev->ce_core_src_clk = clk_get(pce_dev->pdev, "core_clk_src"); + if (!IS_ERR(pce_dev->ce_core_src_clk)) { + rc = clk_set_rate(pce_dev->ce_core_src_clk, + pce_dev->ce_opp_freq_hz); + if (rc) { + pr_err("Unable to set the core src clk @%uMhz.\n", + pce_dev->ce_opp_freq_hz/CE_CLK_DIV); + goto exit_put_core_src_clk; + } + } else { + if (pce_dev->support_only_core_src_clk) { + rc = PTR_ERR(pce_dev->ce_core_src_clk); + pce_dev->ce_core_src_clk = NULL; + pr_err("Unable to get CE core src clk\n"); + return rc; + } else { + pr_warn("Unable to get CE core src clk, set to NULL\n"); + pce_dev->ce_core_src_clk = NULL; + } + } + + if (pce_dev->support_only_core_src_clk) { + pce_dev->ce_core_clk = NULL; + pce_dev->ce_clk = NULL; + pce_dev->ce_bus_clk = NULL; + } else { + pce_dev->ce_core_clk = clk_get(pce_dev->pdev, "core_clk"); + if (IS_ERR(pce_dev->ce_core_clk)) { + rc = PTR_ERR(pce_dev->ce_core_clk); + pr_err("Unable to get CE core clk\n"); + goto exit_put_core_src_clk; + } + pce_dev->ce_clk = clk_get(pce_dev->pdev, "iface_clk"); + if (IS_ERR(pce_dev->ce_clk)) { + rc = PTR_ERR(pce_dev->ce_clk); + pr_err("Unable to get CE interface clk\n"); + goto exit_put_core_clk; + } + + pce_dev->ce_bus_clk = clk_get(pce_dev->pdev, "bus_clk"); + if (IS_ERR(pce_dev->ce_bus_clk)) { + rc = PTR_ERR(pce_dev->ce_bus_clk); + pr_err("Unable to get CE BUS interface clk\n"); + goto exit_put_iface_clk; + } + } + return rc; + +exit_put_iface_clk: + if (pce_dev->ce_clk) + clk_put(pce_dev->ce_clk); +exit_put_core_clk: + if (pce_dev->ce_core_clk) + clk_put(pce_dev->ce_core_clk); +exit_put_core_src_clk: + if (pce_dev->ce_core_src_clk) + clk_put(pce_dev->ce_core_src_clk); + pr_err("Unable to init CE clks, rc = %d\n", rc); + return rc; +} + +static void __qce_deinit_clk(struct qce_device *pce_dev) +{ + if (pce_dev->ce_bus_clk) + clk_put(pce_dev->ce_bus_clk); + if (pce_dev->ce_clk) + clk_put(pce_dev->ce_clk); + if (pce_dev->ce_core_clk) + clk_put(pce_dev->ce_core_clk); + if (pce_dev->ce_core_src_clk) + clk_put(pce_dev->ce_core_src_clk); +} + +int qce_enable_clk(void *handle) +{ + struct qce_device *pce_dev = (struct qce_device *)handle; + int rc = 0; + + if (pce_dev->ce_core_src_clk) { + rc = clk_prepare_enable(pce_dev->ce_core_src_clk); + if (rc) { + pr_err("Unable to enable/prepare CE core src clk\n"); + return rc; + } + } + + if (pce_dev->support_only_core_src_clk) + return rc; + + if (pce_dev->ce_core_clk) { + rc = clk_prepare_enable(pce_dev->ce_core_clk); + if (rc) { + pr_err("Unable to enable/prepare CE core clk\n"); + goto exit_disable_core_src_clk; + } + } + + if (pce_dev->ce_clk) { + rc = clk_prepare_enable(pce_dev->ce_clk); + if (rc) { + pr_err("Unable to enable/prepare CE iface clk\n"); + goto exit_disable_core_clk; + } + } + + if (pce_dev->ce_bus_clk) { + rc = clk_prepare_enable(pce_dev->ce_bus_clk); + if (rc) { + pr_err("Unable to enable/prepare CE BUS clk\n"); + goto exit_disable_ce_clk; + } + } + return rc; + +exit_disable_ce_clk: + if (pce_dev->ce_clk) + clk_disable_unprepare(pce_dev->ce_clk); +exit_disable_core_clk: + if (pce_dev->ce_core_clk) + clk_disable_unprepare(pce_dev->ce_core_clk); +exit_disable_core_src_clk: + if (pce_dev->ce_core_src_clk) + clk_disable_unprepare(pce_dev->ce_core_src_clk); + return rc; +} +EXPORT_SYMBOL(qce_enable_clk); + +int qce_disable_clk(void *handle) +{ + struct qce_device *pce_dev = (struct qce_device *) handle; + int rc = 0; + + if (pce_dev->ce_bus_clk) + clk_disable_unprepare(pce_dev->ce_bus_clk); + if (pce_dev->ce_clk) + clk_disable_unprepare(pce_dev->ce_clk); + if (pce_dev->ce_core_clk) + clk_disable_unprepare(pce_dev->ce_core_clk); + if (pce_dev->ce_core_src_clk) + clk_disable_unprepare(pce_dev->ce_core_src_clk); + + return rc; +} +EXPORT_SYMBOL(qce_disable_clk); + +/* dummy req setup */ +static int setup_dummy_req(struct qce_device *pce_dev) +{ + char *input = + "abcdbcdecdefdefgefghfghighijhijkijkljklmklmnlmnomnopnopqopqrpqrs"; + int len = DUMMY_REQ_DATA_LEN; + + memcpy(pce_dev->dummyreq_in_buf, input, len); + sg_init_table(&pce_dev->dummyreq.sg, 1); + sg_set_buf(&pce_dev->dummyreq.sg, pce_dev->dummyreq_in_buf, len); + sg_mark_end(&pce_dev->dummyreq.sg); + + pce_dev->dummyreq.sreq.alg = QCE_HASH_SHA1; + pce_dev->dummyreq.sreq.qce_cb = qce_dummy_complete; + pce_dev->dummyreq.sreq.src = &pce_dev->dummyreq.sg; + pce_dev->dummyreq.sreq.auth_data[0] = 0; + pce_dev->dummyreq.sreq.auth_data[1] = 0; + pce_dev->dummyreq.sreq.auth_data[2] = 0; + pce_dev->dummyreq.sreq.auth_data[3] = 0; + pce_dev->dummyreq.sreq.first_blk = 1; + pce_dev->dummyreq.sreq.last_blk = 1; + pce_dev->dummyreq.sreq.size = len; + pce_dev->dummyreq.sreq.areq = &pce_dev->dummyreq.areq; + pce_dev->dummyreq.sreq.flags = 0; + pce_dev->dummyreq.sreq.authkey = NULL; + + pce_dev->dummyreq.areq.src = pce_dev->dummyreq.sreq.src; + pce_dev->dummyreq.areq.nbytes = pce_dev->dummyreq.sreq.size; + + return 0; +} + +/* crypto engine open function. */ +void *qce_open(struct platform_device *pdev, int *rc) +{ + struct qce_device *pce_dev; + int i; + static int pcedev_no = 1; + + pce_dev = kzalloc(sizeof(struct qce_device), GFP_KERNEL); + if (!pce_dev) { + *rc = -ENOMEM; + pr_err("Can not allocate memory: %d\n", *rc); + return NULL; + } + pce_dev->pdev = &pdev->dev; + + mutex_lock(&qce_iomap_mutex); + if (pdev->dev.of_node) { + *rc = __qce_get_device_tree_data(pdev, pce_dev); + if (*rc) + goto err_pce_dev; + } else { + *rc = -EINVAL; + pr_err("Device Node not found.\n"); + goto err_pce_dev; + } + + for (i = 0; i < MAX_QCE_ALLOC_BAM_REQ; i++) + atomic_set(&pce_dev->ce_request_info[i].in_use, false); + pce_dev->ce_request_index = 0; + + pce_dev->memsize = 10 * PAGE_SIZE * MAX_QCE_ALLOC_BAM_REQ; + pce_dev->coh_vmem = dma_alloc_coherent(pce_dev->pdev, + pce_dev->memsize, &pce_dev->coh_pmem, GFP_KERNEL); + + if (pce_dev->coh_vmem == NULL) { + *rc = -ENOMEM; + pr_err("Can not allocate coherent memory for sps data\n"); + goto err_iobase; + } + + pce_dev->iovec_memsize = TOTAL_IOVEC_SPACE_PER_PIPE * + MAX_QCE_ALLOC_BAM_REQ * 2; + pce_dev->iovec_vmem = kzalloc(pce_dev->iovec_memsize, GFP_KERNEL); + if (pce_dev->iovec_vmem == NULL) + goto err_mem; + + pce_dev->dummyreq_in_buf = kzalloc(DUMMY_REQ_DATA_LEN, GFP_KERNEL); + if (pce_dev->dummyreq_in_buf == NULL) + goto err_mem; + + *rc = __qce_init_clk(pce_dev); + if (*rc) + goto err_mem; + *rc = qce_enable_clk(pce_dev); + if (*rc) + goto err_enable_clk; + + if (_probe_ce_engine(pce_dev)) { + *rc = -ENXIO; + goto err; + } + *rc = 0; + + qce_init_ce_cfg_val(pce_dev); + *rc = qce_sps_init(pce_dev); + if (*rc) + goto err; + qce_setup_ce_sps_data(pce_dev); + qce_disable_clk(pce_dev); + setup_dummy_req(pce_dev); + atomic_set(&pce_dev->no_of_queued_req, 0); + pce_dev->mode = IN_INTERRUPT_MODE; + init_timer(&(pce_dev->timer)); + pce_dev->timer.function = qce_multireq_timeout; + pce_dev->timer.data = (unsigned long)pce_dev; + pce_dev->timer.expires = jiffies + DELAY_IN_JIFFIES; + pce_dev->intr_cadence = 0; + pce_dev->dev_no = pcedev_no; + pcedev_no++; + pce_dev->owner = QCE_OWNER_NONE; + mutex_unlock(&qce_iomap_mutex); + return pce_dev; +err: + qce_disable_clk(pce_dev); + +err_enable_clk: + __qce_deinit_clk(pce_dev); + +err_mem: + kfree(pce_dev->dummyreq_in_buf); + kfree(pce_dev->iovec_vmem); + if (pce_dev->coh_vmem) + dma_free_coherent(pce_dev->pdev, pce_dev->memsize, + pce_dev->coh_vmem, pce_dev->coh_pmem); +err_iobase: + if (pce_dev->iobase) + iounmap(pce_dev->iobase); +err_pce_dev: + mutex_unlock(&qce_iomap_mutex); + kfree(pce_dev); + return NULL; +} +EXPORT_SYMBOL(qce_open); + +/* crypto engine close function. */ +int qce_close(void *handle) +{ + struct qce_device *pce_dev = (struct qce_device *) handle; + + if (handle == NULL) + return -ENODEV; + + mutex_lock(&qce_iomap_mutex); + qce_enable_clk(pce_dev); + qce_sps_exit(pce_dev); + + if (pce_dev->iobase) + iounmap(pce_dev->iobase); + if (pce_dev->coh_vmem) + dma_free_coherent(pce_dev->pdev, pce_dev->memsize, + pce_dev->coh_vmem, pce_dev->coh_pmem); + kfree(pce_dev->dummyreq_in_buf); + kfree(pce_dev->iovec_vmem); + + qce_disable_clk(pce_dev); + __qce_deinit_clk(pce_dev); + mutex_unlock(&qce_iomap_mutex); + kfree(handle); + + return 0; +} +EXPORT_SYMBOL(qce_close); + +#define OTA_SUPPORT_MASK (1 << CRYPTO_ENCR_SNOW3G_SEL |\ + 1 << CRYPTO_ENCR_KASUMI_SEL |\ + 1 << CRYPTO_AUTH_SNOW3G_SEL |\ + 1 << CRYPTO_AUTH_KASUMI_SEL) + +int qce_hw_support(void *handle, struct ce_hw_support *ce_support) +{ + struct qce_device *pce_dev = (struct qce_device *)handle; + + if (ce_support == NULL) + return -EINVAL; + + ce_support->sha1_hmac_20 = false; + ce_support->sha1_hmac = false; + ce_support->sha256_hmac = false; + ce_support->sha_hmac = true; + ce_support->cmac = true; + ce_support->aes_key_192 = false; + ce_support->aes_xts = true; + if ((pce_dev->engines_avail & OTA_SUPPORT_MASK) == OTA_SUPPORT_MASK) + ce_support->ota = true; + else + ce_support->ota = false; + ce_support->bam = true; + ce_support->is_shared = (pce_dev->is_shared == 1) ? true : false; + ce_support->hw_key = pce_dev->support_hw_key; + ce_support->aes_ccm = true; + ce_support->clk_mgmt_sus_res = pce_dev->support_clk_mgmt_sus_res; + if (pce_dev->ce_bam_info.minor_version) + ce_support->aligned_only = false; + else + ce_support->aligned_only = true; + + ce_support->use_sw_aes_cbc_ecb_ctr_algo = + pce_dev->use_sw_aes_cbc_ecb_ctr_algo; + ce_support->use_sw_aead_algo = + pce_dev->use_sw_aead_algo; + ce_support->use_sw_aes_xts_algo = + pce_dev->use_sw_aes_xts_algo; + ce_support->use_sw_ahash_algo = + pce_dev->use_sw_ahash_algo; + ce_support->use_sw_hmac_algo = + pce_dev->use_sw_hmac_algo; + ce_support->use_sw_aes_ccm_algo = + pce_dev->use_sw_aes_ccm_algo; + ce_support->ce_device = pce_dev->ce_bam_info.ce_device; + ce_support->ce_hw_instance = pce_dev->ce_bam_info.ce_hw_instance; + if (pce_dev->no_get_around) + ce_support->max_request = MAX_QCE_BAM_REQ; + else + ce_support->max_request = 1; + return 0; +} +EXPORT_SYMBOL(qce_hw_support); + +void qce_dump_req(void *handle) +{ + int i; + bool req_in_use; + struct qce_device *pce_dev = (struct qce_device *)handle; + + for (i = 0; i < MAX_QCE_BAM_REQ; i++) { + req_in_use = atomic_read(&pce_dev->ce_request_info[i].in_use); + pr_info("qce_dump_req %d %d\n", i, req_in_use); + if (req_in_use == true) + _qce_dump_descr_fifos(pce_dev, i); + } +} +EXPORT_SYMBOL(qce_dump_req); + +MODULE_LICENSE("GPL v2"); +MODULE_DESCRIPTION("Crypto Engine driver"); diff -Nruw linux-4.4.115-fbx/drivers/crypto/msm./qce50.h linux-4.4.115-fbx/drivers/crypto/msm/qce50.h --- linux-4.4.115-fbx/drivers/crypto/msm./qce50.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-4.4.115-fbx/drivers/crypto/msm/qce50.h 2019-01-22 16:16:23.111242857 +0100 @@ -0,0 +1,245 @@ +/* Copyright (c) 2013-2017, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#ifndef _DRIVERS_CRYPTO_MSM_QCE50_H_ +#define _DRIVERS_CRYPTO_MSM_QCE50_H_ + +#include + +/* MAX Data xfer block size between BAM and CE */ +#define MAX_CE_BAM_BURST_SIZE 0x40 +#define QCEBAM_BURST_SIZE MAX_CE_BAM_BURST_SIZE + +#define GET_VIRT_ADDR(x) \ + ((uintptr_t)pce_dev->coh_vmem + \ + ((uintptr_t)x - (uintptr_t)pce_dev->coh_pmem)) +#define GET_PHYS_ADDR(x) \ + (phys_addr_t)(((uintptr_t)pce_dev->coh_pmem + \ + ((uintptr_t)x - (uintptr_t)pce_dev->coh_vmem))) + +#define CRYPTO_REG_SIZE 4 +#define NUM_OF_CRYPTO_AUTH_IV_REG 16 +#define NUM_OF_CRYPTO_CNTR_IV_REG 4 +#define NUM_OF_CRYPTO_AUTH_BYTE_COUNT_REG 4 +#define CRYPTO_TOTAL_REGISTERS_DUMPED 26 +#define CRYPTO_RESULT_DUMP_SIZE \ + ALIGN((CRYPTO_TOTAL_REGISTERS_DUMPED * CRYPTO_REG_SIZE), \ + QCEBAM_BURST_SIZE) + +/* QCE max number of descriptor in a descriptor list */ +#define QCE_MAX_NUM_DESC 128 +#define SPS_MAX_PKT_SIZE (32 * 1024 - 64) + +/* default bam ipc log level */ +#define QCE_BAM_DEFAULT_IPC_LOGLVL 2 + +/* State of consumer/producer Pipe */ +enum qce_pipe_st_enum { + QCE_PIPE_STATE_IDLE = 0, + QCE_PIPE_STATE_IN_PROG = 1, + QCE_PIPE_STATE_COMP = 2, + QCE_PIPE_STATE_LAST +}; + +enum qce_xfer_type_enum { + QCE_XFER_HASHING, + QCE_XFER_CIPHERING, + QCE_XFER_AEAD, + QCE_XFER_F8, + QCE_XFER_F9, + QCE_XFER_TYPE_LAST +}; + +struct qce_sps_ep_conn_data { + struct sps_pipe *pipe; + struct sps_connect connect; + struct sps_register_event event; +}; + +/* CE Result DUMP format*/ +struct ce_result_dump_format { + uint32_t auth_iv[NUM_OF_CRYPTO_AUTH_IV_REG]; + uint32_t auth_byte_count[NUM_OF_CRYPTO_AUTH_BYTE_COUNT_REG]; + uint32_t encr_cntr_iv[NUM_OF_CRYPTO_CNTR_IV_REG]; + uint32_t status; + uint32_t status2; +}; + +struct qce_cmdlist_info { + + unsigned long cmdlist; + struct sps_command_element *crypto_cfg; + struct sps_command_element *encr_seg_cfg; + struct sps_command_element *encr_seg_size; + struct sps_command_element *encr_seg_start; + struct sps_command_element *encr_key; + struct sps_command_element *encr_xts_key; + struct sps_command_element *encr_cntr_iv; + struct sps_command_element *encr_ccm_cntr_iv; + struct sps_command_element *encr_mask; + struct sps_command_element *encr_xts_du_size; + + struct sps_command_element *auth_seg_cfg; + struct sps_command_element *auth_seg_size; + struct sps_command_element *auth_seg_start; + struct sps_command_element *auth_key; + struct sps_command_element *auth_iv; + struct sps_command_element *auth_nonce_info; + struct sps_command_element *auth_bytecount; + struct sps_command_element *seg_size; + struct sps_command_element *go_proc; + ptrdiff_t size; +}; + +struct qce_cmdlistptr_ops { + struct qce_cmdlist_info cipher_aes_128_cbc_ctr; + struct qce_cmdlist_info cipher_aes_256_cbc_ctr; + struct qce_cmdlist_info cipher_aes_128_ecb; + struct qce_cmdlist_info cipher_aes_256_ecb; + struct qce_cmdlist_info cipher_aes_128_xts; + struct qce_cmdlist_info cipher_aes_256_xts; + struct qce_cmdlist_info cipher_des_cbc; + struct qce_cmdlist_info cipher_des_ecb; + struct qce_cmdlist_info cipher_3des_cbc; + struct qce_cmdlist_info cipher_3des_ecb; + struct qce_cmdlist_info auth_sha1; + struct qce_cmdlist_info auth_sha256; + struct qce_cmdlist_info auth_sha1_hmac; + struct qce_cmdlist_info auth_sha256_hmac; + struct qce_cmdlist_info auth_aes_128_cmac; + struct qce_cmdlist_info auth_aes_256_cmac; + struct qce_cmdlist_info aead_hmac_sha1_cbc_aes_128; + struct qce_cmdlist_info aead_hmac_sha1_cbc_aes_256; + struct qce_cmdlist_info aead_hmac_sha1_cbc_des; + struct qce_cmdlist_info aead_hmac_sha1_cbc_3des; + struct qce_cmdlist_info aead_hmac_sha256_cbc_aes_128; + struct qce_cmdlist_info aead_hmac_sha256_cbc_aes_256; + struct qce_cmdlist_info aead_hmac_sha256_cbc_des; + struct qce_cmdlist_info aead_hmac_sha256_cbc_3des; + struct qce_cmdlist_info aead_aes_128_ccm; + struct qce_cmdlist_info aead_aes_256_ccm; + struct qce_cmdlist_info cipher_null; + struct qce_cmdlist_info f8_kasumi; + struct qce_cmdlist_info f8_snow3g; + struct qce_cmdlist_info f9_kasumi; + struct qce_cmdlist_info f9_snow3g; + struct qce_cmdlist_info unlock_all_pipes; +}; + +struct qce_ce_cfg_reg_setting { + uint32_t crypto_cfg_be; + uint32_t crypto_cfg_le; + + uint32_t encr_cfg_aes_cbc_128; + uint32_t encr_cfg_aes_cbc_256; + + uint32_t encr_cfg_aes_ecb_128; + uint32_t encr_cfg_aes_ecb_256; + + uint32_t encr_cfg_aes_xts_128; + uint32_t encr_cfg_aes_xts_256; + + uint32_t encr_cfg_aes_ctr_128; + uint32_t encr_cfg_aes_ctr_256; + + uint32_t encr_cfg_aes_ccm_128; + uint32_t encr_cfg_aes_ccm_256; + + uint32_t encr_cfg_des_cbc; + uint32_t encr_cfg_des_ecb; + + uint32_t encr_cfg_3des_cbc; + uint32_t encr_cfg_3des_ecb; + uint32_t encr_cfg_kasumi; + uint32_t encr_cfg_snow3g; + + uint32_t auth_cfg_cmac_128; + uint32_t auth_cfg_cmac_256; + + uint32_t auth_cfg_sha1; + uint32_t auth_cfg_sha256; + + uint32_t auth_cfg_hmac_sha1; + uint32_t auth_cfg_hmac_sha256; + + uint32_t auth_cfg_aes_ccm_128; + uint32_t auth_cfg_aes_ccm_256; + uint32_t auth_cfg_aead_sha1_hmac; + uint32_t auth_cfg_aead_sha256_hmac; + uint32_t auth_cfg_kasumi; + uint32_t auth_cfg_snow3g; +}; + +struct ce_bam_info { + uint32_t bam_irq; + uint32_t bam_mem; + void __iomem *bam_iobase; + uint32_t ce_device; + uint32_t ce_hw_instance; + uint32_t bam_ee; + unsigned int pipe_pair_index; + unsigned int src_pipe_index; + unsigned int dest_pipe_index; + unsigned long bam_handle; + int ce_burst_size; + uint32_t minor_version; + struct qce_sps_ep_conn_data producer; + struct qce_sps_ep_conn_data consumer; +}; + +/* SPS data structure with buffers, commandlists & commmand pointer lists */ +struct ce_sps_data { + enum qce_pipe_st_enum producer_state; /* Producer pipe state */ + int consumer_status; /* consumer pipe status */ + int producer_status; /* producer pipe status */ + struct sps_transfer in_transfer; + struct sps_transfer out_transfer; + struct qce_cmdlistptr_ops cmdlistptr; + uint32_t result_dump; /* reuslt dump virtual address */ + uint32_t result_dump_null; + uint32_t result_dump_phy; /* result dump physical address (32 bits) */ + uint32_t result_dump_null_phy; + + uint32_t ignore_buffer; /* ignore buffer virtual address */ + struct ce_result_dump_format *result; /* ponter to result dump */ + struct ce_result_dump_format *result_null; +}; + +struct ce_request_info { + atomic_t in_use; + bool in_prog; + enum qce_xfer_type_enum xfer_type; + struct ce_sps_data ce_sps; + qce_comp_func_ptr_t qce_cb; /* qce callback function pointer */ + void *user; + void *areq; + int assoc_nents; + struct scatterlist *asg; /* Formatted associated data sg */ + int src_nents; + int dst_nents; + dma_addr_t phy_iv_in; + unsigned char dec_iv[16]; + int dir; + enum qce_cipher_mode_enum mode; + dma_addr_t phy_ota_src; + dma_addr_t phy_ota_dst; + unsigned int ota_size; + unsigned int req_len; +}; + +struct qce_driver_stats { + int no_of_timeouts; + int no_of_dummy_reqs; + int current_mode; + int outstanding_reqs; +}; + +#endif /* _DRIVERS_CRYPTO_MSM_QCE50_H */ diff -Nruw linux-4.4.115-fbx/drivers/crypto/msm./qcedev.c linux-4.4.115-fbx/drivers/crypto/msm/qcedev.c --- linux-4.4.115-fbx/drivers/crypto/msm./qcedev.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-4.4.115-fbx/drivers/crypto/msm/qcedev.c 2019-10-29 09:26:23.505201828 +0100 @@ -0,0 +1,2109 @@ +/* Qualcomm CE device driver. + * + * Copyright (c) 2010-2017, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include "qcedevi.h" +#include "qce.h" + +#include +#include "compat_qcedev.h" + +#define CACHE_LINE_SIZE 32 +#define CE_SHA_BLOCK_SIZE SHA256_BLOCK_SIZE + +static uint8_t _std_init_vector_sha1_uint8[] = { + 0x67, 0x45, 0x23, 0x01, 0xEF, 0xCD, 0xAB, 0x89, + 0x98, 0xBA, 0xDC, 0xFE, 0x10, 0x32, 0x54, 0x76, + 0xC3, 0xD2, 0xE1, 0xF0 +}; +/* standard initialization vector for SHA-256, source: FIPS 180-2 */ +static uint8_t _std_init_vector_sha256_uint8[] = { + 0x6A, 0x09, 0xE6, 0x67, 0xBB, 0x67, 0xAE, 0x85, + 0x3C, 0x6E, 0xF3, 0x72, 0xA5, 0x4F, 0xF5, 0x3A, + 0x51, 0x0E, 0x52, 0x7F, 0x9B, 0x05, 0x68, 0x8C, + 0x1F, 0x83, 0xD9, 0xAB, 0x5B, 0xE0, 0xCD, 0x19 +}; + +static DEFINE_MUTEX(send_cmd_lock); +static DEFINE_MUTEX(qcedev_sent_bw_req); +static DEFINE_MUTEX(hash_access_lock); + +static void qcedev_ce_high_bw_req(struct qcedev_control *podev, + bool high_bw_req) +{ + int ret = 0; + + mutex_lock(&qcedev_sent_bw_req); + if (high_bw_req) { + if (podev->high_bw_req_count == 0) { + ret = qce_enable_clk(podev->qce); + if (ret) { + pr_err("%s Unable enable clk\n", __func__); + mutex_unlock(&qcedev_sent_bw_req); + return; + } + ret = msm_bus_scale_client_update_request( + podev->bus_scale_handle, 1); + if (ret) { + pr_err("%s Unable to set to high bandwidth\n", + __func__); + ret = qce_disable_clk(podev->qce); + mutex_unlock(&qcedev_sent_bw_req); + return; + } + } + podev->high_bw_req_count++; + } else { + if (podev->high_bw_req_count == 1) { + ret = msm_bus_scale_client_update_request( + podev->bus_scale_handle, 0); + if (ret) { + pr_err("%s Unable to set to low bandwidth\n", + __func__); + mutex_unlock(&qcedev_sent_bw_req); + return; + } + ret = qce_disable_clk(podev->qce); + if (ret) { + pr_err("%s Unable disable clk\n", __func__); + ret = msm_bus_scale_client_update_request( + podev->bus_scale_handle, 1); + if (ret) + pr_err("%s Unable to set to high bandwidth\n", + __func__); + mutex_unlock(&qcedev_sent_bw_req); + return; + } + } + podev->high_bw_req_count--; + } + mutex_unlock(&qcedev_sent_bw_req); +} + +#define QCEDEV_MAGIC 0x56434544 /* "qced" */ + +static int qcedev_open(struct inode *inode, struct file *file); +static int qcedev_release(struct inode *inode, struct file *file); +static int start_cipher_req(struct qcedev_control *podev); +static int start_sha_req(struct qcedev_control *podev); + +static const struct file_operations qcedev_fops = { + .owner = THIS_MODULE, + .unlocked_ioctl = qcedev_ioctl, +#ifdef CONFIG_COMPAT + .compat_ioctl = compat_qcedev_ioctl, +#endif + .open = qcedev_open, + .release = qcedev_release, +}; + +static struct qcedev_control qce_dev[] = { + { + .miscdevice = { + .minor = MISC_DYNAMIC_MINOR, + .name = "qce", + .fops = &qcedev_fops, + }, + .magic = QCEDEV_MAGIC, + }, +}; + +#define MAX_QCE_DEVICE ARRAY_SIZE(qce_dev) +#define DEBUG_MAX_FNAME 16 +#define DEBUG_MAX_RW_BUF 1024 + +struct qcedev_stat { + u32 qcedev_dec_success; + u32 qcedev_dec_fail; + u32 qcedev_enc_success; + u32 qcedev_enc_fail; + u32 qcedev_sha_success; + u32 qcedev_sha_fail; +}; + +static struct qcedev_stat _qcedev_stat; +static struct dentry *_debug_dent; +static char _debug_read_buf[DEBUG_MAX_RW_BUF]; +static int _debug_qcedev; + +static struct qcedev_control *qcedev_minor_to_control(unsigned n) +{ + int i; + + for (i = 0; i < MAX_QCE_DEVICE; i++) { + if (qce_dev[i].miscdevice.minor == n) + return &qce_dev[i]; + } + return NULL; +} + +static int qcedev_open(struct inode *inode, struct file *file) +{ + struct qcedev_handle *handle; + struct qcedev_control *podev; + + podev = qcedev_minor_to_control(MINOR(inode->i_rdev)); + if (podev == NULL) { + pr_err("%s: no such device %d\n", __func__, + MINOR(inode->i_rdev)); + return -ENOENT; + } + + handle = kzalloc(sizeof(struct qcedev_handle), GFP_KERNEL); + if (handle == NULL) { + pr_err("Failed to allocate memory %ld\n", + PTR_ERR(handle)); + return -ENOMEM; + } + + handle->cntl = podev; + file->private_data = handle; + if (podev->platform_support.bus_scale_table != NULL) + qcedev_ce_high_bw_req(podev, true); + return 0; +} + +static int qcedev_release(struct inode *inode, struct file *file) +{ + struct qcedev_control *podev; + struct qcedev_handle *handle; + + handle = file->private_data; + podev = handle->cntl; + if (podev != NULL && podev->magic != QCEDEV_MAGIC) { + pr_err("%s: invalid handle %pK\n", + __func__, podev); + } + kzfree(handle); + file->private_data = NULL; + if (podev != NULL && podev->platform_support.bus_scale_table != NULL) + qcedev_ce_high_bw_req(podev, false); + return 0; +} + +static void req_done(unsigned long data) +{ + struct qcedev_control *podev = (struct qcedev_control *)data; + struct qcedev_async_req *areq; + unsigned long flags = 0; + struct qcedev_async_req *new_req = NULL; + int ret = 0; + + spin_lock_irqsave(&podev->lock, flags); + areq = podev->active_command; + podev->active_command = NULL; + +again: + if (!list_empty(&podev->ready_commands)) { + new_req = container_of(podev->ready_commands.next, + struct qcedev_async_req, list); + list_del(&new_req->list); + podev->active_command = new_req; + new_req->err = 0; + if (new_req->op_type == QCEDEV_CRYPTO_OPER_CIPHER) + ret = start_cipher_req(podev); + else + ret = start_sha_req(podev); + } + + spin_unlock_irqrestore(&podev->lock, flags); + + if (areq) + complete(&areq->complete); + + if (new_req && ret) { + complete(&new_req->complete); + spin_lock_irqsave(&podev->lock, flags); + podev->active_command = NULL; + areq = NULL; + ret = 0; + new_req = NULL; + goto again; + } + + return; +} + +void qcedev_sha_req_cb(void *cookie, unsigned char *digest, + unsigned char *authdata, int ret) +{ + struct qcedev_sha_req *areq; + struct qcedev_control *pdev; + struct qcedev_handle *handle; + + uint32_t *auth32 = (uint32_t *)authdata; + + areq = (struct qcedev_sha_req *) cookie; + handle = (struct qcedev_handle *) areq->cookie; + pdev = handle->cntl; + + if (digest) + memcpy(&handle->sha_ctxt.digest[0], digest, 32); + + if (authdata) { + handle->sha_ctxt.auth_data[0] = auth32[0]; + handle->sha_ctxt.auth_data[1] = auth32[1]; + } + + tasklet_schedule(&pdev->done_tasklet); +}; + + +void qcedev_cipher_req_cb(void *cookie, unsigned char *icv, + unsigned char *iv, int ret) +{ + struct qcedev_cipher_req *areq; + struct qcedev_handle *handle; + struct qcedev_control *podev; + struct qcedev_async_req *qcedev_areq; + + areq = (struct qcedev_cipher_req *) cookie; + handle = (struct qcedev_handle *) areq->cookie; + podev = handle->cntl; + qcedev_areq = podev->active_command; + + if (iv) + memcpy(&qcedev_areq->cipher_op_req.iv[0], iv, + qcedev_areq->cipher_op_req.ivlen); + tasklet_schedule(&podev->done_tasklet); +}; + +static int start_cipher_req(struct qcedev_control *podev) +{ + struct qcedev_async_req *qcedev_areq; + struct qce_req creq; + int ret = 0; + + /* start the command on the podev->active_command */ + qcedev_areq = podev->active_command; + qcedev_areq->cipher_req.cookie = qcedev_areq->handle; + if (qcedev_areq->cipher_op_req.use_pmem == QCEDEV_USE_PMEM) { + pr_err("%s: Use of PMEM is not supported\n", __func__); + goto unsupported; + } + creq.pmem = NULL; + switch (qcedev_areq->cipher_op_req.alg) { + case QCEDEV_ALG_DES: + creq.alg = CIPHER_ALG_DES; + break; + case QCEDEV_ALG_3DES: + creq.alg = CIPHER_ALG_3DES; + break; + case QCEDEV_ALG_AES: + creq.alg = CIPHER_ALG_AES; + break; + default: + return -EINVAL; + }; + + switch (qcedev_areq->cipher_op_req.mode) { + case QCEDEV_AES_MODE_CBC: + case QCEDEV_DES_MODE_CBC: + creq.mode = QCE_MODE_CBC; + break; + case QCEDEV_AES_MODE_ECB: + case QCEDEV_DES_MODE_ECB: + creq.mode = QCE_MODE_ECB; + break; + case QCEDEV_AES_MODE_CTR: + creq.mode = QCE_MODE_CTR; + break; + case QCEDEV_AES_MODE_XTS: + creq.mode = QCE_MODE_XTS; + break; + default: + return -EINVAL; + }; + + if ((creq.alg == CIPHER_ALG_AES) && + (creq.mode == QCE_MODE_CTR)) { + creq.dir = QCE_ENCRYPT; + } else { + if (QCEDEV_OPER_ENC == qcedev_areq->cipher_op_req.op) + creq.dir = QCE_ENCRYPT; + else + creq.dir = QCE_DECRYPT; + } + + creq.iv = &qcedev_areq->cipher_op_req.iv[0]; + creq.ivsize = qcedev_areq->cipher_op_req.ivlen; + + creq.enckey = &qcedev_areq->cipher_op_req.enckey[0]; + creq.encklen = qcedev_areq->cipher_op_req.encklen; + + creq.cryptlen = qcedev_areq->cipher_op_req.data_len; + + if (qcedev_areq->cipher_op_req.encklen == 0) { + if ((qcedev_areq->cipher_op_req.op == QCEDEV_OPER_ENC_NO_KEY) + || (qcedev_areq->cipher_op_req.op == + QCEDEV_OPER_DEC_NO_KEY)) + creq.op = QCE_REQ_ABLK_CIPHER_NO_KEY; + else { + int i; + + for (i = 0; i < QCEDEV_MAX_KEY_SIZE; i++) { + if (qcedev_areq->cipher_op_req.enckey[i] != 0) + break; + } + + if ((podev->platform_support.hw_key_support == 1) && + (i == QCEDEV_MAX_KEY_SIZE)) + creq.op = QCE_REQ_ABLK_CIPHER; + else { + ret = -EINVAL; + goto unsupported; + } + } + } else { + creq.op = QCE_REQ_ABLK_CIPHER; + } + + creq.qce_cb = qcedev_cipher_req_cb; + creq.areq = (void *)&qcedev_areq->cipher_req; + creq.flags = 0; + ret = qce_ablk_cipher_req(podev->qce, &creq); +unsupported: + if (ret) + qcedev_areq->err = -ENXIO; + else + qcedev_areq->err = 0; + return ret; +}; + +static int start_sha_req(struct qcedev_control *podev) +{ + struct qcedev_async_req *qcedev_areq; + struct qce_sha_req sreq; + int ret = 0; + struct qcedev_handle *handle; + + /* start the command on the podev->active_command */ + qcedev_areq = podev->active_command; + handle = qcedev_areq->handle; + + switch (qcedev_areq->sha_op_req.alg) { + case QCEDEV_ALG_SHA1: + sreq.alg = QCE_HASH_SHA1; + break; + case QCEDEV_ALG_SHA256: + sreq.alg = QCE_HASH_SHA256; + break; + case QCEDEV_ALG_SHA1_HMAC: + if (podev->ce_support.sha_hmac) { + sreq.alg = QCE_HASH_SHA1_HMAC; + sreq.authkey = &handle->sha_ctxt.authkey[0]; + sreq.authklen = QCEDEV_MAX_SHA_BLOCK_SIZE; + + } else { + sreq.alg = QCE_HASH_SHA1; + sreq.authkey = NULL; + } + break; + case QCEDEV_ALG_SHA256_HMAC: + if (podev->ce_support.sha_hmac) { + sreq.alg = QCE_HASH_SHA256_HMAC; + sreq.authkey = &handle->sha_ctxt.authkey[0]; + sreq.authklen = QCEDEV_MAX_SHA_BLOCK_SIZE; + } else { + sreq.alg = QCE_HASH_SHA256; + sreq.authkey = NULL; + } + break; + case QCEDEV_ALG_AES_CMAC: + sreq.alg = QCE_HASH_AES_CMAC; + sreq.authkey = &handle->sha_ctxt.authkey[0]; + sreq.authklen = qcedev_areq->sha_op_req.authklen; + break; + default: + pr_err("Algorithm %d not supported, exiting\n", + qcedev_areq->sha_op_req.alg); + return -EINVAL; + break; + }; + + qcedev_areq->sha_req.cookie = handle; + + sreq.qce_cb = qcedev_sha_req_cb; + if (qcedev_areq->sha_op_req.alg != QCEDEV_ALG_AES_CMAC) { + sreq.auth_data[0] = handle->sha_ctxt.auth_data[0]; + sreq.auth_data[1] = handle->sha_ctxt.auth_data[1]; + sreq.auth_data[2] = handle->sha_ctxt.auth_data[2]; + sreq.auth_data[3] = handle->sha_ctxt.auth_data[3]; + sreq.digest = &handle->sha_ctxt.digest[0]; + sreq.first_blk = handle->sha_ctxt.first_blk; + sreq.last_blk = handle->sha_ctxt.last_blk; + } + sreq.size = qcedev_areq->sha_req.sreq.nbytes; + sreq.src = qcedev_areq->sha_req.sreq.src; + sreq.areq = (void *)&qcedev_areq->sha_req; + sreq.flags = 0; + + ret = qce_process_sha_req(podev->qce, &sreq); + + if (ret) + qcedev_areq->err = -ENXIO; + else + qcedev_areq->err = 0; + return ret; +}; + +static int submit_req(struct qcedev_async_req *qcedev_areq, + struct qcedev_handle *handle) +{ + struct qcedev_control *podev; + unsigned long flags = 0; + int ret = 0; + struct qcedev_stat *pstat; + + qcedev_areq->err = 0; + podev = handle->cntl; + + spin_lock_irqsave(&podev->lock, flags); + + if (podev->active_command == NULL) { + podev->active_command = qcedev_areq; + if (qcedev_areq->op_type == QCEDEV_CRYPTO_OPER_CIPHER) + ret = start_cipher_req(podev); + else + ret = start_sha_req(podev); + } else { + list_add_tail(&qcedev_areq->list, &podev->ready_commands); + } + + if (ret != 0) + podev->active_command = NULL; + + spin_unlock_irqrestore(&podev->lock, flags); + + if (ret == 0) + wait_for_completion(&qcedev_areq->complete); + + if (ret) + qcedev_areq->err = -EIO; + + pstat = &_qcedev_stat; + if (qcedev_areq->op_type == QCEDEV_CRYPTO_OPER_CIPHER) { + switch (qcedev_areq->cipher_op_req.op) { + case QCEDEV_OPER_DEC: + if (qcedev_areq->err) + pstat->qcedev_dec_fail++; + else + pstat->qcedev_dec_success++; + break; + case QCEDEV_OPER_ENC: + if (qcedev_areq->err) + pstat->qcedev_enc_fail++; + else + pstat->qcedev_enc_success++; + break; + default: + break; + }; + } else { + if (qcedev_areq->err) + pstat->qcedev_sha_fail++; + else + pstat->qcedev_sha_success++; + } + + return qcedev_areq->err; +} + +static int qcedev_sha_init(struct qcedev_async_req *areq, + struct qcedev_handle *handle) +{ + struct qcedev_sha_ctxt *sha_ctxt = &handle->sha_ctxt; + + memset(sha_ctxt, 0, sizeof(struct qcedev_sha_ctxt)); + sha_ctxt->first_blk = 1; + + if ((areq->sha_op_req.alg == QCEDEV_ALG_SHA1) || + (areq->sha_op_req.alg == QCEDEV_ALG_SHA1_HMAC)) { + memcpy(&sha_ctxt->digest[0], + &_std_init_vector_sha1_uint8[0], SHA1_DIGEST_SIZE); + sha_ctxt->diglen = SHA1_DIGEST_SIZE; + } else { + if ((areq->sha_op_req.alg == QCEDEV_ALG_SHA256) || + (areq->sha_op_req.alg == QCEDEV_ALG_SHA256_HMAC)) { + memcpy(&sha_ctxt->digest[0], + &_std_init_vector_sha256_uint8[0], + SHA256_DIGEST_SIZE); + sha_ctxt->diglen = SHA256_DIGEST_SIZE; + } + } + sha_ctxt->init_done = true; + return 0; +} + + +static int qcedev_sha_update_max_xfer(struct qcedev_async_req *qcedev_areq, + struct qcedev_handle *handle, + struct scatterlist *sg_src) +{ + int err = 0; + int i = 0; + uint32_t total; + + uint8_t *user_src = NULL; + uint8_t *k_src = NULL; + uint8_t *k_buf_src = NULL; + uint8_t *k_align_src = NULL; + + uint32_t sha_pad_len = 0; + uint32_t trailing_buf_len = 0; + uint32_t t_buf = handle->sha_ctxt.trailing_buf_len; + uint32_t sha_block_size; + + total = qcedev_areq->sha_op_req.data_len + t_buf; + + if (qcedev_areq->sha_op_req.alg == QCEDEV_ALG_SHA1) + sha_block_size = SHA1_BLOCK_SIZE; + else + sha_block_size = SHA256_BLOCK_SIZE; + + if (total <= sha_block_size) { + uint32_t len = qcedev_areq->sha_op_req.data_len; + + i = 0; + + k_src = &handle->sha_ctxt.trailing_buf[t_buf]; + + /* Copy data from user src(s) */ + while (len > 0) { + user_src = + (void __user *)qcedev_areq->sha_op_req.data[i].vaddr; + if (user_src && copy_from_user(k_src, + (void __user *)user_src, + qcedev_areq->sha_op_req.data[i].len)) + return -EFAULT; + + len -= qcedev_areq->sha_op_req.data[i].len; + k_src += qcedev_areq->sha_op_req.data[i].len; + i++; + } + handle->sha_ctxt.trailing_buf_len = total; + + return 0; + } + + + k_buf_src = kmalloc(total + CACHE_LINE_SIZE * 2, + GFP_KERNEL); + if (k_buf_src == NULL) { + pr_err("%s: Can't Allocate memory: k_buf_src 0x%lx\n", + __func__, (uintptr_t)k_buf_src); + return -ENOMEM; + } + + k_align_src = (uint8_t *)ALIGN(((uintptr_t)k_buf_src), + CACHE_LINE_SIZE); + k_src = k_align_src; + + /* check for trailing buffer from previous updates and append it */ + if (t_buf > 0) { + memcpy(k_src, &handle->sha_ctxt.trailing_buf[0], + t_buf); + k_src += t_buf; + } + + /* Copy data from user src(s) */ + user_src = (void __user *)qcedev_areq->sha_op_req.data[0].vaddr; + if (user_src && copy_from_user(k_src, + (void __user *)user_src, + qcedev_areq->sha_op_req.data[0].len)) { + kzfree(k_buf_src); + return -EFAULT; + } + k_src += qcedev_areq->sha_op_req.data[0].len; + for (i = 1; i < qcedev_areq->sha_op_req.entries; i++) { + user_src = (void __user *)qcedev_areq->sha_op_req.data[i].vaddr; + if (user_src && copy_from_user(k_src, + (void __user *)user_src, + qcedev_areq->sha_op_req.data[i].len)) { + kzfree(k_buf_src); + return -EFAULT; + } + k_src += qcedev_areq->sha_op_req.data[i].len; + } + + /* get new trailing buffer */ + sha_pad_len = ALIGN(total, CE_SHA_BLOCK_SIZE) - total; + trailing_buf_len = CE_SHA_BLOCK_SIZE - sha_pad_len; + + qcedev_areq->sha_req.sreq.src = sg_src; + sg_set_buf(qcedev_areq->sha_req.sreq.src, k_align_src, + total-trailing_buf_len); + sg_mark_end(qcedev_areq->sha_req.sreq.src); + + qcedev_areq->sha_req.sreq.nbytes = total - trailing_buf_len; + + /* update sha_ctxt trailing buf content to new trailing buf */ + if (trailing_buf_len > 0) { + memset(&handle->sha_ctxt.trailing_buf[0], 0, 64); + memcpy(&handle->sha_ctxt.trailing_buf[0], + (k_src - trailing_buf_len), + trailing_buf_len); + } + handle->sha_ctxt.trailing_buf_len = trailing_buf_len; + + err = submit_req(qcedev_areq, handle); + + handle->sha_ctxt.last_blk = 0; + handle->sha_ctxt.first_blk = 0; + + kzfree(k_buf_src); + return err; +} + +static int qcedev_sha_update(struct qcedev_async_req *qcedev_areq, + struct qcedev_handle *handle, + struct scatterlist *sg_src) +{ + int err = 0; + int i = 0; + int j = 0; + int k = 0; + int num_entries = 0; + uint32_t total = 0; + + if (handle->sha_ctxt.init_done == false) { + pr_err("%s Init was not called\n", __func__); + return -EINVAL; + } + + if (qcedev_areq->sha_op_req.data_len > QCE_MAX_OPER_DATA) { + + struct qcedev_sha_op_req *saved_req; + struct qcedev_sha_op_req req; + struct qcedev_sha_op_req *sreq = &qcedev_areq->sha_op_req; + + /* save the original req structure */ + saved_req = + kmalloc(sizeof(struct qcedev_sha_op_req), GFP_KERNEL); + if (saved_req == NULL) { + pr_err("%s:Can't Allocate mem:saved_req 0x%lx\n", + __func__, (uintptr_t)saved_req); + return -ENOMEM; + } + memcpy(&req, sreq, sizeof(struct qcedev_sha_op_req)); + memcpy(saved_req, sreq, sizeof(struct qcedev_sha_op_req)); + + i = 0; + /* Address 32 KB at a time */ + while ((i < req.entries) && (err == 0)) { + if (sreq->data[i].len > QCE_MAX_OPER_DATA) { + sreq->data[0].len = QCE_MAX_OPER_DATA; + if (i > 0) { + sreq->data[0].vaddr = + sreq->data[i].vaddr; + } + + sreq->data_len = QCE_MAX_OPER_DATA; + sreq->entries = 1; + + err = qcedev_sha_update_max_xfer(qcedev_areq, + handle, sg_src); + + sreq->data[i].len = req.data[i].len - + QCE_MAX_OPER_DATA; + sreq->data[i].vaddr = req.data[i].vaddr + + QCE_MAX_OPER_DATA; + req.data[i].vaddr = sreq->data[i].vaddr; + req.data[i].len = sreq->data[i].len; + } else { + total = 0; + for (j = i; j < req.entries; j++) { + num_entries++; + if ((total + sreq->data[j].len) >= + QCE_MAX_OPER_DATA) { + sreq->data[j].len = + (QCE_MAX_OPER_DATA - total); + total = QCE_MAX_OPER_DATA; + break; + } + total += sreq->data[j].len; + } + + sreq->data_len = total; + if (i > 0) + for (k = 0; k < num_entries; k++) { + sreq->data[k].len = + sreq->data[i+k].len; + sreq->data[k].vaddr = + sreq->data[i+k].vaddr; + } + sreq->entries = num_entries; + + i = j; + err = qcedev_sha_update_max_xfer(qcedev_areq, + handle, sg_src); + num_entries = 0; + + sreq->data[i].vaddr = req.data[i].vaddr + + sreq->data[i].len; + sreq->data[i].len = req.data[i].len - + sreq->data[i].len; + req.data[i].vaddr = sreq->data[i].vaddr; + req.data[i].len = sreq->data[i].len; + + if (sreq->data[i].len == 0) + i++; + } + } /* end of while ((i < req.entries) && (err == 0)) */ + + /* Restore the original req structure */ + for (i = 0; i < saved_req->entries; i++) { + sreq->data[i].len = saved_req->data[i].len; + sreq->data[i].vaddr = saved_req->data[i].vaddr; + } + sreq->entries = saved_req->entries; + sreq->data_len = saved_req->data_len; + kzfree(saved_req); + } else + err = qcedev_sha_update_max_xfer(qcedev_areq, handle, sg_src); + + return err; +} + +static int qcedev_sha_final(struct qcedev_async_req *qcedev_areq, + struct qcedev_handle *handle) +{ + int err = 0; + struct scatterlist sg_src; + uint32_t total; + uint8_t *k_buf_src = NULL; + uint8_t *k_align_src = NULL; + + if (handle->sha_ctxt.init_done == false) { + pr_err("%s Init was not called\n", __func__); + return -EINVAL; + } + + handle->sha_ctxt.last_blk = 1; + + total = handle->sha_ctxt.trailing_buf_len; + + if (total) { + k_buf_src = kmalloc(total + CACHE_LINE_SIZE * 2, + GFP_KERNEL); + if (k_buf_src == NULL) { + pr_err("%s: Can't Allocate memory: k_buf_src 0x%lx\n", + __func__, (uintptr_t)k_buf_src); + return -ENOMEM; + } + + k_align_src = (uint8_t *)ALIGN(((uintptr_t)k_buf_src), + CACHE_LINE_SIZE); + memcpy(k_align_src, &handle->sha_ctxt.trailing_buf[0], total); + } + qcedev_areq->sha_req.sreq.src = (struct scatterlist *) &sg_src; + sg_set_buf(qcedev_areq->sha_req.sreq.src, k_align_src, total); + sg_mark_end(qcedev_areq->sha_req.sreq.src); + + qcedev_areq->sha_req.sreq.nbytes = total; + + err = submit_req(qcedev_areq, handle); + + handle->sha_ctxt.first_blk = 0; + handle->sha_ctxt.last_blk = 0; + handle->sha_ctxt.auth_data[0] = 0; + handle->sha_ctxt.auth_data[1] = 0; + handle->sha_ctxt.trailing_buf_len = 0; + handle->sha_ctxt.init_done = false; + memset(&handle->sha_ctxt.trailing_buf[0], 0, 64); + + kzfree(k_buf_src); + return err; +} + +static int qcedev_hash_cmac(struct qcedev_async_req *qcedev_areq, + struct qcedev_handle *handle, + struct scatterlist *sg_src) +{ + int err = 0; + int i = 0; + uint32_t total; + + uint8_t *user_src = NULL; + uint8_t *k_src = NULL; + uint8_t *k_buf_src = NULL; + + total = qcedev_areq->sha_op_req.data_len; + + if (copy_from_user(&handle->sha_ctxt.authkey[0], + (void __user *)qcedev_areq->sha_op_req.authkey, + qcedev_areq->sha_op_req.authklen)) + return -EFAULT; + + + k_buf_src = kmalloc(total, GFP_KERNEL); + if (k_buf_src == NULL) { + pr_err("%s: Can't Allocate memory: k_buf_src 0x%lx\n", + __func__, (uintptr_t)k_buf_src); + return -ENOMEM; + } + + k_src = k_buf_src; + + /* Copy data from user src(s) */ + user_src = (void __user *)qcedev_areq->sha_op_req.data[0].vaddr; + for (i = 0; i < qcedev_areq->sha_op_req.entries; i++) { + user_src = + (void __user *)qcedev_areq->sha_op_req.data[i].vaddr; + if (user_src && copy_from_user(k_src, (void __user *)user_src, + qcedev_areq->sha_op_req.data[i].len)) { + kzfree(k_buf_src); + return -EFAULT; + } + k_src += qcedev_areq->sha_op_req.data[i].len; + } + + qcedev_areq->sha_req.sreq.src = sg_src; + sg_set_buf(qcedev_areq->sha_req.sreq.src, k_buf_src, total); + sg_mark_end(qcedev_areq->sha_req.sreq.src); + + qcedev_areq->sha_req.sreq.nbytes = total; + handle->sha_ctxt.diglen = qcedev_areq->sha_op_req.diglen; + err = submit_req(qcedev_areq, handle); + + kzfree(k_buf_src); + return err; +} + +static int qcedev_set_hmac_auth_key(struct qcedev_async_req *areq, + struct qcedev_handle *handle, + struct scatterlist *sg_src) +{ + int err = 0; + + if (areq->sha_op_req.authklen <= QCEDEV_MAX_KEY_SIZE) { + qcedev_sha_init(areq, handle); + if (copy_from_user(&handle->sha_ctxt.authkey[0], + (void __user *)areq->sha_op_req.authkey, + areq->sha_op_req.authklen)) + return -EFAULT; + } else { + struct qcedev_async_req authkey_areq; + uint8_t authkey[QCEDEV_MAX_SHA_BLOCK_SIZE]; + + init_completion(&authkey_areq.complete); + + authkey_areq.sha_op_req.entries = 1; + authkey_areq.sha_op_req.data[0].vaddr = + areq->sha_op_req.authkey; + authkey_areq.sha_op_req.data[0].len = areq->sha_op_req.authklen; + authkey_areq.sha_op_req.data_len = areq->sha_op_req.authklen; + authkey_areq.sha_op_req.diglen = 0; + authkey_areq.handle = handle; + + memset(&authkey_areq.sha_op_req.digest[0], 0, + QCEDEV_MAX_SHA_DIGEST); + if (areq->sha_op_req.alg == QCEDEV_ALG_SHA1_HMAC) + authkey_areq.sha_op_req.alg = QCEDEV_ALG_SHA1; + if (areq->sha_op_req.alg == QCEDEV_ALG_SHA256_HMAC) + authkey_areq.sha_op_req.alg = QCEDEV_ALG_SHA256; + + authkey_areq.op_type = QCEDEV_CRYPTO_OPER_SHA; + + qcedev_sha_init(&authkey_areq, handle); + err = qcedev_sha_update(&authkey_areq, handle, sg_src); + if (!err) + err = qcedev_sha_final(&authkey_areq, handle); + else + return err; + memcpy(&authkey[0], &handle->sha_ctxt.digest[0], + handle->sha_ctxt.diglen); + qcedev_sha_init(areq, handle); + + memcpy(&handle->sha_ctxt.authkey[0], &authkey[0], + handle->sha_ctxt.diglen); + } + return err; +} + +static int qcedev_hmac_get_ohash(struct qcedev_async_req *qcedev_areq, + struct qcedev_handle *handle) +{ + int err = 0; + struct scatterlist sg_src; + uint8_t *k_src = NULL; + uint32_t sha_block_size = 0; + uint32_t sha_digest_size = 0; + + if (qcedev_areq->sha_op_req.alg == QCEDEV_ALG_SHA1_HMAC) { + sha_digest_size = SHA1_DIGEST_SIZE; + sha_block_size = SHA1_BLOCK_SIZE; + } else { + if (qcedev_areq->sha_op_req.alg == QCEDEV_ALG_SHA256_HMAC) { + sha_digest_size = SHA256_DIGEST_SIZE; + sha_block_size = SHA256_BLOCK_SIZE; + } + } + k_src = kmalloc(sha_block_size, GFP_KERNEL); + if (k_src == NULL) { + pr_err("%s: Can't Allocate memory: k_src 0x%lx\n", + __func__, (uintptr_t)k_src); + return -ENOMEM; + } + + /* check for trailing buffer from previous updates and append it */ + memcpy(k_src, &handle->sha_ctxt.trailing_buf[0], + handle->sha_ctxt.trailing_buf_len); + + qcedev_areq->sha_req.sreq.src = (struct scatterlist *) &sg_src; + sg_set_buf(qcedev_areq->sha_req.sreq.src, k_src, sha_block_size); + sg_mark_end(qcedev_areq->sha_req.sreq.src); + + qcedev_areq->sha_req.sreq.nbytes = sha_block_size; + memset(&handle->sha_ctxt.trailing_buf[0], 0, sha_block_size); + memcpy(&handle->sha_ctxt.trailing_buf[0], &handle->sha_ctxt.digest[0], + sha_digest_size); + handle->sha_ctxt.trailing_buf_len = sha_digest_size; + + handle->sha_ctxt.first_blk = 1; + handle->sha_ctxt.last_blk = 0; + handle->sha_ctxt.auth_data[0] = 0; + handle->sha_ctxt.auth_data[1] = 0; + + if (qcedev_areq->sha_op_req.alg == QCEDEV_ALG_SHA1_HMAC) { + memcpy(&handle->sha_ctxt.digest[0], + &_std_init_vector_sha1_uint8[0], SHA1_DIGEST_SIZE); + handle->sha_ctxt.diglen = SHA1_DIGEST_SIZE; + } + + if (qcedev_areq->sha_op_req.alg == QCEDEV_ALG_SHA256_HMAC) { + memcpy(&handle->sha_ctxt.digest[0], + &_std_init_vector_sha256_uint8[0], SHA256_DIGEST_SIZE); + handle->sha_ctxt.diglen = SHA256_DIGEST_SIZE; + } + err = submit_req(qcedev_areq, handle); + + handle->sha_ctxt.last_blk = 0; + handle->sha_ctxt.first_blk = 0; + + kzfree(k_src); + return err; +} + +static int qcedev_hmac_update_iokey(struct qcedev_async_req *areq, + struct qcedev_handle *handle, bool ikey) +{ + int i; + uint32_t constant; + uint32_t sha_block_size; + + if (ikey) + constant = 0x36; + else + constant = 0x5c; + + if (areq->sha_op_req.alg == QCEDEV_ALG_SHA1_HMAC) + sha_block_size = SHA1_BLOCK_SIZE; + else + sha_block_size = SHA256_BLOCK_SIZE; + + memset(&handle->sha_ctxt.trailing_buf[0], 0, sha_block_size); + for (i = 0; i < sha_block_size; i++) + handle->sha_ctxt.trailing_buf[i] = + (handle->sha_ctxt.authkey[i] ^ constant); + + handle->sha_ctxt.trailing_buf_len = sha_block_size; + return 0; +} + +static int qcedev_hmac_init(struct qcedev_async_req *areq, + struct qcedev_handle *handle, + struct scatterlist *sg_src) +{ + int err; + struct qcedev_control *podev = handle->cntl; + + err = qcedev_set_hmac_auth_key(areq, handle, sg_src); + if (err) + return err; + if (!podev->ce_support.sha_hmac) + qcedev_hmac_update_iokey(areq, handle, true); + return 0; +} + +static int qcedev_hmac_final(struct qcedev_async_req *areq, + struct qcedev_handle *handle) +{ + int err; + struct qcedev_control *podev = handle->cntl; + + err = qcedev_sha_final(areq, handle); + if (podev->ce_support.sha_hmac) + return err; + + qcedev_hmac_update_iokey(areq, handle, false); + err = qcedev_hmac_get_ohash(areq, handle); + if (err) + return err; + err = qcedev_sha_final(areq, handle); + + return err; +} + +static int qcedev_hash_init(struct qcedev_async_req *areq, + struct qcedev_handle *handle, + struct scatterlist *sg_src) +{ + if ((areq->sha_op_req.alg == QCEDEV_ALG_SHA1) || + (areq->sha_op_req.alg == QCEDEV_ALG_SHA256)) + return qcedev_sha_init(areq, handle); + else + return qcedev_hmac_init(areq, handle, sg_src); +} + +static int qcedev_hash_update(struct qcedev_async_req *qcedev_areq, + struct qcedev_handle *handle, + struct scatterlist *sg_src) +{ + return qcedev_sha_update(qcedev_areq, handle, sg_src); +} + +static int qcedev_hash_final(struct qcedev_async_req *areq, + struct qcedev_handle *handle) +{ + if ((areq->sha_op_req.alg == QCEDEV_ALG_SHA1) || + (areq->sha_op_req.alg == QCEDEV_ALG_SHA256)) + return qcedev_sha_final(areq, handle); + else + return qcedev_hmac_final(areq, handle); +} + +static int qcedev_vbuf_ablk_cipher_max_xfer(struct qcedev_async_req *areq, + int *di, struct qcedev_handle *handle, + uint8_t *k_align_src) +{ + int err = 0; + int i = 0; + int dst_i = *di; + struct scatterlist sg_src; + uint32_t byteoffset = 0; + uint8_t *user_src = NULL; + uint8_t *k_align_dst = k_align_src; + struct qcedev_cipher_op_req *creq = &areq->cipher_op_req; + + + if (areq->cipher_op_req.mode == QCEDEV_AES_MODE_CTR) + byteoffset = areq->cipher_op_req.byteoffset; + + user_src = (void __user *)areq->cipher_op_req.vbuf.src[0].vaddr; + if (user_src && copy_from_user((k_align_src + byteoffset), + (void __user *)user_src, + areq->cipher_op_req.vbuf.src[0].len)) + return -EFAULT; + + k_align_src += byteoffset + areq->cipher_op_req.vbuf.src[0].len; + + for (i = 1; i < areq->cipher_op_req.entries; i++) { + user_src = + (void __user *)areq->cipher_op_req.vbuf.src[i].vaddr; + if (user_src && copy_from_user(k_align_src, + (void __user *)user_src, + areq->cipher_op_req.vbuf.src[i].len)) { + return -EFAULT; + } + k_align_src += areq->cipher_op_req.vbuf.src[i].len; + } + + /* restore src beginning */ + k_align_src = k_align_dst; + areq->cipher_op_req.data_len += byteoffset; + + areq->cipher_req.creq.src = (struct scatterlist *) &sg_src; + areq->cipher_req.creq.dst = (struct scatterlist *) &sg_src; + + /* In place encryption/decryption */ + sg_set_buf(areq->cipher_req.creq.src, + k_align_dst, + areq->cipher_op_req.data_len); + sg_mark_end(areq->cipher_req.creq.src); + + areq->cipher_req.creq.nbytes = areq->cipher_op_req.data_len; + areq->cipher_req.creq.info = areq->cipher_op_req.iv; + areq->cipher_op_req.entries = 1; + + err = submit_req(areq, handle); + + /* copy data to destination buffer*/ + creq->data_len -= byteoffset; + + while (creq->data_len > 0) { + if (creq->vbuf.dst[dst_i].len <= creq->data_len) { + if (err == 0 && copy_to_user( + (void __user *)creq->vbuf.dst[dst_i].vaddr, + (k_align_dst + byteoffset), + creq->vbuf.dst[dst_i].len)) + return -EFAULT; + + k_align_dst += creq->vbuf.dst[dst_i].len + + byteoffset; + creq->data_len -= creq->vbuf.dst[dst_i].len; + dst_i++; + } else { + if (err == 0 && copy_to_user( + (void __user *)creq->vbuf.dst[dst_i].vaddr, + (k_align_dst + byteoffset), + creq->data_len)) + return -EFAULT; + + k_align_dst += creq->data_len; + creq->vbuf.dst[dst_i].len -= creq->data_len; + creq->vbuf.dst[dst_i].vaddr += creq->data_len; + creq->data_len = 0; + } + } + *di = dst_i; + + return err; +}; + +static int qcedev_vbuf_ablk_cipher(struct qcedev_async_req *areq, + struct qcedev_handle *handle) +{ + int err = 0; + int di = 0; + int i = 0; + int j = 0; + int k = 0; + uint32_t byteoffset = 0; + int num_entries = 0; + uint32_t total = 0; + uint32_t len; + uint8_t *k_buf_src = NULL; + uint8_t *k_align_src = NULL; + uint32_t max_data_xfer; + struct qcedev_cipher_op_req *saved_req; + struct qcedev_cipher_op_req *creq = &areq->cipher_op_req; + + total = 0; + + if (areq->cipher_op_req.mode == QCEDEV_AES_MODE_CTR) + byteoffset = areq->cipher_op_req.byteoffset; + k_buf_src = kmalloc(QCE_MAX_OPER_DATA + CACHE_LINE_SIZE * 2, + GFP_KERNEL); + if (k_buf_src == NULL) { + pr_err("%s: Can't Allocate memory: k_buf_src 0x%lx\n", + __func__, (uintptr_t)k_buf_src); + return -ENOMEM; + } + k_align_src = (uint8_t *)ALIGN(((uintptr_t)k_buf_src), + CACHE_LINE_SIZE); + max_data_xfer = QCE_MAX_OPER_DATA - byteoffset; + + saved_req = kmalloc(sizeof(struct qcedev_cipher_op_req), GFP_KERNEL); + if (saved_req == NULL) { + pr_err("%s: Can't Allocate memory:saved_req 0x%lx\n", + __func__, (uintptr_t)saved_req); + kzfree(k_buf_src); + return -ENOMEM; + + } + memcpy(saved_req, creq, sizeof(struct qcedev_cipher_op_req)); + + if (areq->cipher_op_req.data_len > max_data_xfer) { + struct qcedev_cipher_op_req req; + + /* save the original req structure */ + memcpy(&req, creq, sizeof(struct qcedev_cipher_op_req)); + + i = 0; + /* Address 32 KB at a time */ + while ((i < req.entries) && (err == 0)) { + if (creq->vbuf.src[i].len > max_data_xfer) { + creq->vbuf.src[0].len = max_data_xfer; + if (i > 0) { + creq->vbuf.src[0].vaddr = + creq->vbuf.src[i].vaddr; + } + + creq->data_len = max_data_xfer; + creq->entries = 1; + + err = qcedev_vbuf_ablk_cipher_max_xfer(areq, + &di, handle, k_align_src); + if (err < 0) { + kzfree(k_buf_src); + kzfree(saved_req); + return err; + } + + creq->vbuf.src[i].len = req.vbuf.src[i].len - + max_data_xfer; + creq->vbuf.src[i].vaddr = + req.vbuf.src[i].vaddr + + max_data_xfer; + req.vbuf.src[i].vaddr = + creq->vbuf.src[i].vaddr; + req.vbuf.src[i].len = creq->vbuf.src[i].len; + + } else { + total = areq->cipher_op_req.byteoffset; + for (j = i; j < req.entries; j++) { + num_entries++; + if ((total + creq->vbuf.src[j].len) + >= max_data_xfer) { + creq->vbuf.src[j].len = + max_data_xfer - total; + total = max_data_xfer; + break; + } + total += creq->vbuf.src[j].len; + } + + creq->data_len = total; + if (i > 0) + for (k = 0; k < num_entries; k++) { + creq->vbuf.src[k].len = + creq->vbuf.src[i+k].len; + creq->vbuf.src[k].vaddr = + creq->vbuf.src[i+k].vaddr; + } + creq->entries = num_entries; + + i = j; + err = qcedev_vbuf_ablk_cipher_max_xfer(areq, + &di, handle, k_align_src); + if (err < 0) { + kzfree(k_buf_src); + kzfree(saved_req); + return err; + } + + num_entries = 0; + areq->cipher_op_req.byteoffset = 0; + + creq->vbuf.src[i].vaddr = req.vbuf.src[i].vaddr + + creq->vbuf.src[i].len; + creq->vbuf.src[i].len = req.vbuf.src[i].len - + creq->vbuf.src[i].len; + + req.vbuf.src[i].vaddr = + creq->vbuf.src[i].vaddr; + req.vbuf.src[i].len = creq->vbuf.src[i].len; + + if (creq->vbuf.src[i].len == 0) + i++; + } + + areq->cipher_op_req.byteoffset = 0; + max_data_xfer = QCE_MAX_OPER_DATA; + byteoffset = 0; + + } /* end of while ((i < req.entries) && (err == 0)) */ + } else + err = qcedev_vbuf_ablk_cipher_max_xfer(areq, &di, handle, + k_align_src); + + /* Restore the original req structure */ + for (i = 0; i < saved_req->entries; i++) { + creq->vbuf.src[i].len = saved_req->vbuf.src[i].len; + creq->vbuf.src[i].vaddr = saved_req->vbuf.src[i].vaddr; + } + for (len = 0, i = 0; len < saved_req->data_len; i++) { + creq->vbuf.dst[i].len = saved_req->vbuf.dst[i].len; + creq->vbuf.dst[i].vaddr = saved_req->vbuf.dst[i].vaddr; + len += saved_req->vbuf.dst[i].len; + } + creq->entries = saved_req->entries; + creq->data_len = saved_req->data_len; + creq->byteoffset = saved_req->byteoffset; + + kzfree(saved_req); + kzfree(k_buf_src); + return err; + +} + +static int qcedev_check_cipher_key(struct qcedev_cipher_op_req *req, + struct qcedev_control *podev) +{ + /* if intending to use HW key make sure key fields are set + * correctly and HW key is indeed supported in target + */ + if (req->encklen == 0) { + int i; + for (i = 0; i < QCEDEV_MAX_KEY_SIZE; i++) { + if (req->enckey[i]) { + pr_err("%s: Invalid key: non-zero key input\n", + __func__); + goto error; + } + } + if ((req->op != QCEDEV_OPER_ENC_NO_KEY) && + (req->op != QCEDEV_OPER_DEC_NO_KEY)) + if (!podev->platform_support.hw_key_support) { + pr_err("%s: Invalid op %d\n", __func__, + (uint32_t)req->op); + goto error; + } + } else { + if (req->encklen == QCEDEV_AES_KEY_192) { + if (!podev->ce_support.aes_key_192) { + pr_err("%s: AES-192 not supported\n", __func__); + goto error; + } + } else { + /* if not using HW key make sure key + * length is valid + */ + if (req->mode == QCEDEV_AES_MODE_XTS) { + if ((req->encklen != QCEDEV_AES_KEY_128*2) && + (req->encklen != QCEDEV_AES_KEY_256*2)) { + pr_err("%s: unsupported key size: %d\n", + __func__, req->encklen); + goto error; + } + } else { + if ((req->encklen != QCEDEV_AES_KEY_128) && + (req->encklen != QCEDEV_AES_KEY_256)) { + pr_err("%s: unsupported key size %d\n", + __func__, req->encklen); + goto error; + } + } + } + } + return 0; +error: + return -EINVAL; +} + +static int qcedev_check_cipher_params(struct qcedev_cipher_op_req *req, + struct qcedev_control *podev) +{ + uint32_t total = 0; + uint32_t i; + + if (req->use_pmem) { + pr_err("%s: Use of PMEM is not supported\n", __func__); + goto error; + } + if ((req->entries == 0) || (req->data_len == 0) || + (req->entries > QCEDEV_MAX_BUFFERS)) { + pr_err("%s: Invalid cipher length/entries\n", __func__); + goto error; + } + if ((req->alg >= QCEDEV_ALG_LAST) || + (req->mode >= QCEDEV_AES_DES_MODE_LAST)) { + pr_err("%s: Invalid algorithm %d\n", __func__, + (uint32_t)req->alg); + goto error; + } + if ((req->mode == QCEDEV_AES_MODE_XTS) && + (!podev->ce_support.aes_xts)) { + pr_err("%s: XTS algorithm is not supported\n", __func__); + goto error; + } + if (req->alg == QCEDEV_ALG_AES) { + if (qcedev_check_cipher_key(req, podev)) + goto error; + + } + /* if using a byteoffset, make sure it is CTR mode using vbuf */ + if (req->byteoffset) { + if (req->mode != QCEDEV_AES_MODE_CTR) { + pr_err("%s: Operation on byte offset not supported\n", + __func__); + goto error; + } + if (req->byteoffset >= AES_CE_BLOCK_SIZE) { + pr_err("%s: Invalid byte offset\n", __func__); + goto error; + } + total = req->byteoffset; + for (i = 0; i < req->entries; i++) { + if (total > U32_MAX - req->vbuf.src[i].len) { + pr_err("%s:Integer overflow on total src len\n", + __func__); + goto error; + } + total += req->vbuf.src[i].len; + } + } + + if (req->data_len < req->byteoffset) { + pr_err("%s: req data length %u is less than byteoffset %u\n", + __func__, req->data_len, req->byteoffset); + goto error; + } + + /* Ensure IV size */ + if (req->ivlen > QCEDEV_MAX_IV_SIZE) { + pr_err("%s: ivlen is not correct: %u\n", __func__, req->ivlen); + goto error; + } + + /* Ensure Key size */ + if (req->encklen > QCEDEV_MAX_KEY_SIZE) { + pr_err("%s: Klen is not correct: %u\n", __func__, req->encklen); + goto error; + } + + /* Ensure zer ivlen for ECB mode */ + if (req->ivlen > 0) { + if ((req->mode == QCEDEV_AES_MODE_ECB) || + (req->mode == QCEDEV_DES_MODE_ECB)) { + pr_err("%s: Expecting a zero length IV\n", __func__); + goto error; + } + } else { + if ((req->mode != QCEDEV_AES_MODE_ECB) && + (req->mode != QCEDEV_DES_MODE_ECB)) { + pr_err("%s: Expecting a non-zero ength IV\n", __func__); + goto error; + } + } + /* Check for sum of all dst length is equal to data_len */ + for (i = 0, total = 0; i < req->entries; i++) { + if (!req->vbuf.dst[i].vaddr && req->vbuf.dst[i].len) { + pr_err("%s: NULL req dst vbuf[%d] with length %d\n", + __func__, i, req->vbuf.dst[i].len); + goto error; + } + if (req->vbuf.dst[i].len >= U32_MAX - total) { + pr_err("%s: Integer overflow on total req dst vbuf length\n", + __func__); + goto error; + } + total += req->vbuf.dst[i].len; + } + if (total != req->data_len) { + pr_err("%s: Total (i=%d) dst(%d) buf size != data_len (%d)\n", + __func__, i, total, req->data_len); + goto error; + } + /* Check for sum of all src length is equal to data_len */ + for (i = 0, total = 0; i < req->entries; i++) { + if (!req->vbuf.src[i].vaddr && req->vbuf.src[i].len) { + pr_err("%s: NULL req src vbuf[%d] with length %d\n", + __func__, i, req->vbuf.src[i].len); + goto error; + } + if (req->vbuf.src[i].len > U32_MAX - total) { + pr_err("%s: Integer overflow on total req src vbuf length\n", + __func__); + goto error; + } + total += req->vbuf.src[i].len; + } + if (total != req->data_len) { + pr_err("%s: Total src(%d) buf size != data_len (%d)\n", + __func__, total, req->data_len); + goto error; + } + return 0; +error: + return -EINVAL; + +} + +static int qcedev_check_sha_params(struct qcedev_sha_op_req *req, + struct qcedev_control *podev) +{ + uint32_t total = 0; + uint32_t i; + + if ((req->alg == QCEDEV_ALG_AES_CMAC) && + (!podev->ce_support.cmac)) { + pr_err("%s: CMAC not supported\n", __func__); + goto sha_error; + } + if ((!req->entries) || (req->entries > QCEDEV_MAX_BUFFERS)) { + pr_err("%s: Invalid num entries (%d)\n", + __func__, req->entries); + goto sha_error; + } + + if (req->alg >= QCEDEV_ALG_SHA_ALG_LAST) { + pr_err("%s: Invalid algorithm (%d)\n", __func__, req->alg); + goto sha_error; + } + if ((req->alg == QCEDEV_ALG_SHA1_HMAC) || + (req->alg == QCEDEV_ALG_SHA1_HMAC)) { + if (req->authkey == NULL) { + pr_err("%s: Invalid authkey pointer\n", __func__); + goto sha_error; + } + if (req->authklen <= 0) { + pr_err("%s: Invalid authkey length (%d)\n", + __func__, req->authklen); + goto sha_error; + } + } + + if (req->alg == QCEDEV_ALG_AES_CMAC) { + if ((req->authklen != QCEDEV_AES_KEY_128) && + (req->authklen != QCEDEV_AES_KEY_256)) { + pr_err("%s: unsupported key length\n", __func__); + goto sha_error; + } + } + + /* Check for sum of all src length is equal to data_len */ + for (i = 0, total = 0; i < req->entries; i++) { + if (req->data[i].len > U32_MAX - total) { + pr_err("%s: Integer overflow on total req buf length\n", + __func__); + goto sha_error; + } + total += req->data[i].len; + } + + if (total != req->data_len) { + pr_err("%s: Total src(%d) buf size != data_len (%d)\n", + __func__, total, req->data_len); + goto sha_error; + } + return 0; +sha_error: + return -EINVAL; +} + +long qcedev_ioctl(struct file *file, unsigned cmd, unsigned long arg) +{ + int err = 0; + struct qcedev_handle *handle; + struct qcedev_control *podev; + struct qcedev_async_req qcedev_areq; + struct qcedev_stat *pstat; + + handle = file->private_data; + podev = handle->cntl; + qcedev_areq.handle = handle; + if (podev == NULL || podev->magic != QCEDEV_MAGIC) { + pr_err("%s: invalid handle %pK\n", + __func__, podev); + return -ENOENT; + } + + /* Verify user arguments. */ + if (_IOC_TYPE(cmd) != QCEDEV_IOC_MAGIC) + return -ENOTTY; + + init_completion(&qcedev_areq.complete); + pstat = &_qcedev_stat; + + switch (cmd) { + case QCEDEV_IOCTL_ENC_REQ: + case QCEDEV_IOCTL_DEC_REQ: + if (copy_from_user(&qcedev_areq.cipher_op_req, + (void __user *)arg, + sizeof(struct qcedev_cipher_op_req))) + return -EFAULT; + qcedev_areq.op_type = QCEDEV_CRYPTO_OPER_CIPHER; + + if (qcedev_check_cipher_params(&qcedev_areq.cipher_op_req, + podev)) + return -EINVAL; + + err = qcedev_vbuf_ablk_cipher(&qcedev_areq, handle); + if (err) + return err; + if (copy_to_user((void __user *)arg, + &qcedev_areq.cipher_op_req, + sizeof(struct qcedev_cipher_op_req))) + return -EFAULT; + break; + + case QCEDEV_IOCTL_SHA_INIT_REQ: + { + struct scatterlist sg_src; + + if (copy_from_user(&qcedev_areq.sha_op_req, + (void __user *)arg, + sizeof(struct qcedev_sha_op_req))) + return -EFAULT; + mutex_lock(&hash_access_lock); + if (qcedev_check_sha_params(&qcedev_areq.sha_op_req, podev)) { + mutex_unlock(&hash_access_lock); + return -EINVAL; + } + qcedev_areq.op_type = QCEDEV_CRYPTO_OPER_SHA; + err = qcedev_hash_init(&qcedev_areq, handle, &sg_src); + if (err) { + mutex_unlock(&hash_access_lock); + return err; + } + mutex_unlock(&hash_access_lock); + if (copy_to_user((void __user *)arg, &qcedev_areq.sha_op_req, + sizeof(struct qcedev_sha_op_req))) + return -EFAULT; + } + handle->sha_ctxt.init_done = true; + break; + case QCEDEV_IOCTL_GET_CMAC_REQ: + if (!podev->ce_support.cmac) + return -ENOTTY; + case QCEDEV_IOCTL_SHA_UPDATE_REQ: + { + struct scatterlist sg_src; + + if (copy_from_user(&qcedev_areq.sha_op_req, + (void __user *)arg, + sizeof(struct qcedev_sha_op_req))) + return -EFAULT; + mutex_lock(&hash_access_lock); + if (qcedev_check_sha_params(&qcedev_areq.sha_op_req, podev)) { + mutex_unlock(&hash_access_lock); + return -EINVAL; + } + qcedev_areq.op_type = QCEDEV_CRYPTO_OPER_SHA; + + if (qcedev_areq.sha_op_req.alg == QCEDEV_ALG_AES_CMAC) { + err = qcedev_hash_cmac(&qcedev_areq, handle, &sg_src); + if (err) { + mutex_unlock(&hash_access_lock); + return err; + } + } else { + if (handle->sha_ctxt.init_done == false) { + pr_err("%s Init was not called\n", __func__); + mutex_unlock(&hash_access_lock); + return -EINVAL; + } + err = qcedev_hash_update(&qcedev_areq, handle, &sg_src); + if (err) { + mutex_unlock(&hash_access_lock); + return err; + } + } + + if (handle->sha_ctxt.diglen > QCEDEV_MAX_SHA_DIGEST) { + pr_err("Invalid sha_ctxt.diglen %d\n", + handle->sha_ctxt.diglen); + mutex_unlock(&hash_access_lock); + return -EINVAL; + } + memcpy(&qcedev_areq.sha_op_req.digest[0], + &handle->sha_ctxt.digest[0], + handle->sha_ctxt.diglen); + mutex_unlock(&hash_access_lock); + if (copy_to_user((void __user *)arg, &qcedev_areq.sha_op_req, + sizeof(struct qcedev_sha_op_req))) + return -EFAULT; + } + break; + + case QCEDEV_IOCTL_SHA_FINAL_REQ: + + if (handle->sha_ctxt.init_done == false) { + pr_err("%s Init was not called\n", __func__); + return -EINVAL; + } + if (copy_from_user(&qcedev_areq.sha_op_req, + (void __user *)arg, + sizeof(struct qcedev_sha_op_req))) + return -EFAULT; + mutex_lock(&hash_access_lock); + if (qcedev_check_sha_params(&qcedev_areq.sha_op_req, podev)) { + mutex_unlock(&hash_access_lock); + return -EINVAL; + } + qcedev_areq.op_type = QCEDEV_CRYPTO_OPER_SHA; + err = qcedev_hash_final(&qcedev_areq, handle); + if (err) { + mutex_unlock(&hash_access_lock); + return err; + } + if (handle->sha_ctxt.diglen > QCEDEV_MAX_SHA_DIGEST) { + pr_err("Invalid sha_ctxt.diglen %d\n", + handle->sha_ctxt.diglen); + mutex_unlock(&hash_access_lock); + return -EINVAL; + } + qcedev_areq.sha_op_req.diglen = handle->sha_ctxt.diglen; + memcpy(&qcedev_areq.sha_op_req.digest[0], + &handle->sha_ctxt.digest[0], + handle->sha_ctxt.diglen); + mutex_unlock(&hash_access_lock); + if (copy_to_user((void __user *)arg, &qcedev_areq.sha_op_req, + sizeof(struct qcedev_sha_op_req))) + return -EFAULT; + handle->sha_ctxt.init_done = false; + break; + + case QCEDEV_IOCTL_GET_SHA_REQ: + { + struct scatterlist sg_src; + + if (copy_from_user(&qcedev_areq.sha_op_req, + (void __user *)arg, + sizeof(struct qcedev_sha_op_req))) + return -EFAULT; + mutex_lock(&hash_access_lock); + if (qcedev_check_sha_params(&qcedev_areq.sha_op_req, podev)) { + mutex_unlock(&hash_access_lock); + return -EINVAL; + } + qcedev_areq.op_type = QCEDEV_CRYPTO_OPER_SHA; + qcedev_hash_init(&qcedev_areq, handle, &sg_src); + err = qcedev_hash_update(&qcedev_areq, handle, &sg_src); + if (err) { + mutex_unlock(&hash_access_lock); + return err; + } + err = qcedev_hash_final(&qcedev_areq, handle); + if (err) { + mutex_unlock(&hash_access_lock); + return err; + } + if (handle->sha_ctxt.diglen > QCEDEV_MAX_SHA_DIGEST) { + pr_err("Invalid sha_ctxt.diglen %d\n", + handle->sha_ctxt.diglen); + mutex_unlock(&hash_access_lock); + return -EINVAL; + } + qcedev_areq.sha_op_req.diglen = handle->sha_ctxt.diglen; + memcpy(&qcedev_areq.sha_op_req.digest[0], + &handle->sha_ctxt.digest[0], + handle->sha_ctxt.diglen); + mutex_unlock(&hash_access_lock); + if (copy_to_user((void __user *)arg, &qcedev_areq.sha_op_req, + sizeof(struct qcedev_sha_op_req))) + return -EFAULT; + } + break; + + default: + return -ENOTTY; + } + + return err; +} +EXPORT_SYMBOL(qcedev_ioctl); + +static int qcedev_probe(struct platform_device *pdev) +{ + void *handle = NULL; + int rc = 0; + struct qcedev_control *podev; + struct msm_ce_hw_support *platform_support; + + podev = &qce_dev[0]; + + podev->high_bw_req_count = 0; + INIT_LIST_HEAD(&podev->ready_commands); + podev->active_command = NULL; + + spin_lock_init(&podev->lock); + + tasklet_init(&podev->done_tasklet, req_done, (unsigned long)podev); + + /* open qce */ + handle = qce_open(pdev, &rc); + if (handle == NULL) { + platform_set_drvdata(pdev, NULL); + return rc; + } + + podev->qce = handle; + podev->pdev = pdev; + platform_set_drvdata(pdev, podev); + + rc = misc_register(&podev->miscdevice); + qce_hw_support(podev->qce, &podev->ce_support); + if (podev->ce_support.bam) { + podev->platform_support.ce_shared = 0; + podev->platform_support.shared_ce_resource = 0; + podev->platform_support.hw_key_support = + podev->ce_support.hw_key; + podev->platform_support.bus_scale_table = NULL; + podev->platform_support.sha_hmac = 1; + + podev->platform_support.bus_scale_table = + (struct msm_bus_scale_pdata *) + msm_bus_cl_get_pdata(pdev); + if (!podev->platform_support.bus_scale_table) + pr_err("bus_scale_table is NULL\n"); + } else { + platform_support = + (struct msm_ce_hw_support *)pdev->dev.platform_data; + podev->platform_support.ce_shared = platform_support->ce_shared; + podev->platform_support.shared_ce_resource = + platform_support->shared_ce_resource; + podev->platform_support.hw_key_support = + platform_support->hw_key_support; + podev->platform_support.bus_scale_table = + platform_support->bus_scale_table; + podev->platform_support.sha_hmac = platform_support->sha_hmac; + } + if (podev->platform_support.bus_scale_table != NULL) { + podev->bus_scale_handle = + msm_bus_scale_register_client( + (struct msm_bus_scale_pdata *) + podev->platform_support.bus_scale_table); + if (!podev->bus_scale_handle) { + pr_err("%s not able to get bus scale\n", + __func__); + rc = -ENOMEM; + goto err; + } + } + + if (rc >= 0) + return 0; + else + if (podev->platform_support.bus_scale_table != NULL) + msm_bus_scale_unregister_client( + podev->bus_scale_handle); +err: + + if (handle) + qce_close(handle); + platform_set_drvdata(pdev, NULL); + podev->qce = NULL; + podev->pdev = NULL; + return rc; +}; + +static int qcedev_remove(struct platform_device *pdev) +{ + struct qcedev_control *podev; + + podev = platform_get_drvdata(pdev); + if (!podev) + return 0; + if (podev->qce) + qce_close(podev->qce); + + if (podev->platform_support.bus_scale_table != NULL) + msm_bus_scale_unregister_client(podev->bus_scale_handle); + + if (podev->miscdevice.minor != MISC_DYNAMIC_MINOR) + misc_deregister(&podev->miscdevice); + tasklet_kill(&podev->done_tasklet); + return 0; +}; + +static int qcedev_suspend(struct platform_device *pdev, pm_message_t state) +{ + struct qcedev_control *podev; + int ret; + podev = platform_get_drvdata(pdev); + + if (!podev || !podev->platform_support.bus_scale_table) + return 0; + + mutex_lock(&qcedev_sent_bw_req); + if (podev->high_bw_req_count) { + ret = msm_bus_scale_client_update_request( + podev->bus_scale_handle, 0); + if (ret) { + pr_err("%s Unable to set to low bandwidth\n", + __func__); + goto suspend_exit; + } + ret = qce_disable_clk(podev->qce); + if (ret) { + pr_err("%s Unable disable clk\n", __func__); + ret = msm_bus_scale_client_update_request( + podev->bus_scale_handle, 1); + if (ret) + pr_err("%s Unable to set to high bandwidth\n", + __func__); + goto suspend_exit; + } + } + +suspend_exit: + mutex_unlock(&qcedev_sent_bw_req); + return 0; +} + +static int qcedev_resume(struct platform_device *pdev) +{ + struct qcedev_control *podev; + int ret; + podev = platform_get_drvdata(pdev); + + if (!podev || !podev->platform_support.bus_scale_table) + return 0; + + mutex_lock(&qcedev_sent_bw_req); + if (podev->high_bw_req_count) { + ret = qce_enable_clk(podev->qce); + if (ret) { + pr_err("%s Unable enable clk\n", __func__); + goto resume_exit; + } + ret = msm_bus_scale_client_update_request( + podev->bus_scale_handle, 1); + if (ret) { + pr_err("%s Unable to set to high bandwidth\n", + __func__); + ret = qce_disable_clk(podev->qce); + if (ret) + pr_err("%s Unable enable clk\n", + __func__); + goto resume_exit; + } + } + +resume_exit: + mutex_unlock(&qcedev_sent_bw_req); + return 0; +} + +static struct of_device_id qcedev_match[] = { + { .compatible = "qcom,qcedev", + }, + {} +}; + +static struct platform_driver qcedev_plat_driver = { + .probe = qcedev_probe, + .remove = qcedev_remove, + .suspend = qcedev_suspend, + .resume = qcedev_resume, + .driver = { + .name = "qce", + .owner = THIS_MODULE, + .of_match_table = qcedev_match, + }, +}; + +static int _disp_stats(int id) +{ + struct qcedev_stat *pstat; + int len = 0; + + pstat = &_qcedev_stat; + len = scnprintf(_debug_read_buf, DEBUG_MAX_RW_BUF - 1, + "\nQualcomm QCE dev driver %d Statistics:\n", + id + 1); + + len += scnprintf(_debug_read_buf + len, DEBUG_MAX_RW_BUF - len - 1, + " Encryption operation success : %d\n", + pstat->qcedev_enc_success); + len += scnprintf(_debug_read_buf + len, DEBUG_MAX_RW_BUF - len - 1, + " Encryption operation fail : %d\n", + pstat->qcedev_enc_fail); + len += scnprintf(_debug_read_buf + len, DEBUG_MAX_RW_BUF - len - 1, + " Decryption operation success : %d\n", + pstat->qcedev_dec_success); + + len += scnprintf(_debug_read_buf + len, DEBUG_MAX_RW_BUF - len - 1, + " Encryption operation fail : %d\n", + pstat->qcedev_dec_fail); + + return len; +} + +static int _debug_stats_open(struct inode *inode, struct file *file) +{ + file->private_data = inode->i_private; + return 0; +} + +static ssize_t _debug_stats_read(struct file *file, char __user *buf, + size_t count, loff_t *ppos) +{ + ssize_t rc = -EINVAL; + int qcedev = *((int *) file->private_data); + int len; + + len = _disp_stats(qcedev); + + if (len <= count) + rc = simple_read_from_buffer((void __user *) buf, len, + ppos, (void *) _debug_read_buf, len); + return rc; +} + +static ssize_t _debug_stats_write(struct file *file, const char __user *buf, + size_t count, loff_t *ppos) +{ + memset((char *)&_qcedev_stat, 0, sizeof(struct qcedev_stat)); + return count; +}; + +static const struct file_operations _debug_stats_ops = { + .open = _debug_stats_open, + .read = _debug_stats_read, + .write = _debug_stats_write, +}; + +static int _qcedev_debug_init(void) +{ + int rc; + char name[DEBUG_MAX_FNAME]; + struct dentry *dent; + + _debug_dent = debugfs_create_dir("qcedev", NULL); + if (IS_ERR(_debug_dent)) { + pr_err("qcedev debugfs_create_dir fail, error %ld\n", + PTR_ERR(_debug_dent)); + return PTR_ERR(_debug_dent); + } + + snprintf(name, DEBUG_MAX_FNAME-1, "stats-%d", 1); + _debug_qcedev = 0; + dent = debugfs_create_file(name, 0644, _debug_dent, + &_debug_qcedev, &_debug_stats_ops); + if (dent == NULL) { + pr_err("qcedev debugfs_create_file fail, error %ld\n", + PTR_ERR(dent)); + rc = PTR_ERR(dent); + goto err; + } + return 0; +err: + debugfs_remove_recursive(_debug_dent); + return rc; +} + +static int qcedev_init(void) +{ + int rc; + + rc = _qcedev_debug_init(); + if (rc) + return rc; + return platform_driver_register(&qcedev_plat_driver); +} + +static void qcedev_exit(void) +{ + debugfs_remove_recursive(_debug_dent); + platform_driver_unregister(&qcedev_plat_driver); +} + +MODULE_LICENSE("GPL v2"); +MODULE_DESCRIPTION("Qualcomm DEV Crypto driver"); + +module_init(qcedev_init); +module_exit(qcedev_exit); diff -Nruw linux-4.4.115-fbx/drivers/crypto/msm./qcedevi.h linux-4.4.115-fbx/drivers/crypto/msm/qcedevi.h --- linux-4.4.115-fbx/drivers/crypto/msm./qcedevi.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-4.4.115-fbx/drivers/crypto/msm/qcedevi.h 2019-01-22 16:16:23.111242857 +0100 @@ -0,0 +1,124 @@ +/* QTI crypto Driver + * + * Copyright (c) 2014-2015, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __CRYPTO_MSM_QCEDEVI_H +#define __CRYPTO_MSM_QCEDEVI_H + +#include +#include +#include +#include +#include +#include "qce.h" + +#define CACHE_LINE_SIZE 32 +#define CE_SHA_BLOCK_SIZE SHA256_BLOCK_SIZE + +enum qcedev_crypto_oper_type { + QCEDEV_CRYPTO_OPER_CIPHER = 0, + QCEDEV_CRYPTO_OPER_SHA = 1, + QCEDEV_CRYPTO_OPER_LAST +}; + +struct qcedev_handle; + +struct qcedev_cipher_req { + struct ablkcipher_request creq; + void *cookie; +}; + +struct qcedev_sha_req { + struct ahash_request sreq; + void *cookie; +}; + +struct qcedev_sha_ctxt { + uint32_t auth_data[4]; + uint8_t digest[QCEDEV_MAX_SHA_DIGEST]; + uint32_t diglen; + uint8_t trailing_buf[64]; + uint32_t trailing_buf_len; + uint8_t first_blk; + uint8_t last_blk; + uint8_t authkey[QCEDEV_MAX_SHA_BLOCK_SIZE]; + bool init_done; +}; + +struct qcedev_async_req { + struct list_head list; + struct completion complete; + enum qcedev_crypto_oper_type op_type; + union { + struct qcedev_cipher_op_req cipher_op_req; + struct qcedev_sha_op_req sha_op_req; + }; + + union { + struct qcedev_cipher_req cipher_req; + struct qcedev_sha_req sha_req; + }; + struct qcedev_handle *handle; + int err; +}; + +/********************************************************************** + * Register ourselves as a misc device to be able to access the dev driver + * from userspace. */ + +#define QCEDEV_DEV "qcedev" + +struct qcedev_control { + + /* CE features supported by platform */ + struct msm_ce_hw_support platform_support; + + uint32_t ce_lock_count; + uint32_t high_bw_req_count; + + /* CE features/algorithms supported by HW engine*/ + struct ce_hw_support ce_support; + + uint32_t bus_scale_handle; + + /* misc device */ + struct miscdevice miscdevice; + + /* qce handle */ + void *qce; + + /* platform device */ + struct platform_device *pdev; + + unsigned magic; + + struct list_head ready_commands; + struct qcedev_async_req *active_command; + spinlock_t lock; + struct tasklet_struct done_tasklet; +}; + +struct qcedev_handle { + /* qcedev control handle */ + struct qcedev_control *cntl; + /* qce internal sha context*/ + struct qcedev_sha_ctxt sha_ctxt; +}; + +void qcedev_cipher_req_cb(void *cookie, unsigned char *icv, + unsigned char *iv, int ret); + +void qcedev_sha_req_cb(void *cookie, unsigned char *digest, + unsigned char *authdata, int ret); + +#endif /* __CRYPTO_MSM_QCEDEVI_H */ diff -Nruw linux-4.4.115-fbx/drivers/crypto/msm./qce.h linux-4.4.115-fbx/drivers/crypto/msm/qce.h --- linux-4.4.115-fbx/drivers/crypto/msm./qce.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-4.4.115-fbx/drivers/crypto/msm/qce.h 2019-01-22 16:16:23.111242857 +0100 @@ -0,0 +1,190 @@ +/* Qualcomm Crypto Engine driver API + * + * Copyright (c) 2010-2015, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +#ifndef __CRYPTO_MSM_QCE_H +#define __CRYPTO_MSM_QCE_H + +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +/* SHA digest size in bytes */ +#define SHA256_DIGESTSIZE 32 +#define SHA1_DIGESTSIZE 20 + +#define AES_CE_BLOCK_SIZE 16 + +/* key size in bytes */ +#define HMAC_KEY_SIZE (SHA1_DIGESTSIZE) /* hmac-sha1 */ +#define SHA_HMAC_KEY_SIZE 64 +#define DES_KEY_SIZE 8 +#define TRIPLE_DES_KEY_SIZE 24 +#define AES128_KEY_SIZE 16 +#define AES192_KEY_SIZE 24 +#define AES256_KEY_SIZE 32 +#define MAX_CIPHER_KEY_SIZE AES256_KEY_SIZE + +/* iv length in bytes */ +#define AES_IV_LENGTH 16 +#define DES_IV_LENGTH 8 +#define MAX_IV_LENGTH AES_IV_LENGTH + +/* Maximum number of bytes per transfer */ +#define QCE_MAX_OPER_DATA 0xFF00 + +/* Maximum Nonce bytes */ +#define MAX_NONCE 16 + +typedef void (*qce_comp_func_ptr_t)(void *areq, + unsigned char *icv, unsigned char *iv, int ret); + +/* Cipher algorithms supported */ +enum qce_cipher_alg_enum { + CIPHER_ALG_DES = 0, + CIPHER_ALG_3DES = 1, + CIPHER_ALG_AES = 2, + CIPHER_ALG_LAST +}; + +/* Hash and hmac algorithms supported */ +enum qce_hash_alg_enum { + QCE_HASH_SHA1 = 0, + QCE_HASH_SHA256 = 1, + QCE_HASH_SHA1_HMAC = 2, + QCE_HASH_SHA256_HMAC = 3, + QCE_HASH_AES_CMAC = 4, + QCE_HASH_LAST +}; + +/* Cipher encryption/decryption operations */ +enum qce_cipher_dir_enum { + QCE_ENCRYPT = 0, + QCE_DECRYPT = 1, + QCE_CIPHER_DIR_LAST +}; + +/* Cipher algorithms modes */ +enum qce_cipher_mode_enum { + QCE_MODE_CBC = 0, + QCE_MODE_ECB = 1, + QCE_MODE_CTR = 2, + QCE_MODE_XTS = 3, + QCE_MODE_CCM = 4, + QCE_CIPHER_MODE_LAST +}; + +/* Cipher operation type */ +enum qce_req_op_enum { + QCE_REQ_ABLK_CIPHER = 0, + QCE_REQ_ABLK_CIPHER_NO_KEY = 1, + QCE_REQ_AEAD = 2, + QCE_REQ_LAST +}; + +/* Algorithms/features supported in CE HW engine */ +struct ce_hw_support { + bool sha1_hmac_20; /* Supports 20 bytes of HMAC key*/ + bool sha1_hmac; /* supports max HMAC key of 64 bytes*/ + bool sha256_hmac; /* supports max HMAC key of 64 bytes*/ + bool sha_hmac; /* supports SHA1 and SHA256 MAX HMAC key of 64 bytes*/ + bool cmac; + bool aes_key_192; + bool aes_xts; + bool aes_ccm; + bool ota; + bool aligned_only; + bool bam; + bool is_shared; + bool hw_key; + bool use_sw_aes_cbc_ecb_ctr_algo; + bool use_sw_aead_algo; + bool use_sw_aes_xts_algo; + bool use_sw_ahash_algo; + bool use_sw_hmac_algo; + bool use_sw_aes_ccm_algo; + bool clk_mgmt_sus_res; + unsigned int ce_device; + unsigned int ce_hw_instance; + unsigned int max_request; +}; + +/* Sha operation parameters */ +struct qce_sha_req { + qce_comp_func_ptr_t qce_cb; /* call back */ + enum qce_hash_alg_enum alg; /* sha algorithm */ + unsigned char *digest; /* sha digest */ + struct scatterlist *src; /* pointer to scatter list entry */ + uint32_t auth_data[4]; /* byte count */ + unsigned char *authkey; /* auth key */ + unsigned int authklen; /* auth key length */ + bool first_blk; /* first block indicator */ + bool last_blk; /* last block indicator */ + unsigned int size; /* data length in bytes */ + void *areq; + unsigned int flags; +}; + +struct qce_req { + enum qce_req_op_enum op; /* operation type */ + qce_comp_func_ptr_t qce_cb; /* call back */ + void *areq; + enum qce_cipher_alg_enum alg; /* cipher algorithms*/ + enum qce_cipher_dir_enum dir; /* encryption? decryption? */ + enum qce_cipher_mode_enum mode; /* algorithm mode */ + enum qce_hash_alg_enum auth_alg;/* authentication algorithm for aead */ + unsigned char *authkey; /* authentication key */ + unsigned int authklen; /* authentication key kength */ + unsigned int authsize; /* authentication key kength */ + unsigned char nonce[MAX_NONCE];/* nonce for ccm mode */ + unsigned char *assoc; /* Ptr to formatted associated data */ + unsigned int assoclen; /* Formatted associated data length */ + struct scatterlist *asg; /* Formatted associated data sg */ + unsigned char *enckey; /* cipher key */ + unsigned int encklen; /* cipher key length */ + unsigned char *iv; /* initialization vector */ + unsigned int ivsize; /* initialization vector size*/ + unsigned int cryptlen; /* data length */ + unsigned int use_pmem; /* is source of data PMEM allocated? */ + struct qcedev_pmem_info *pmem; /* pointer to pmem_info structure*/ + unsigned int flags; +}; + +struct qce_pm_table { + int (*suspend)(void *handle); + int (*resume)(void *handle); +}; + +extern struct qce_pm_table qce_pm_table; + +void *qce_open(struct platform_device *pdev, int *rc); +int qce_close(void *handle); +int qce_aead_req(void *handle, struct qce_req *req); +int qce_ablk_cipher_req(void *handle, struct qce_req *req); +int qce_hw_support(void *handle, struct ce_hw_support *support); +int qce_process_sha_req(void *handle, struct qce_sha_req *s_req); +int qce_enable_clk(void *handle); +int qce_disable_clk(void *handle); +void qce_get_driver_stats(void *handle); +void qce_clear_driver_stats(void *handle); + +#endif /* __CRYPTO_MSM_QCE_H */ diff -Nruw linux-4.4.115-fbx/drivers/crypto/msm./qce_ota.h linux-4.4.115-fbx/drivers/crypto/msm/qce_ota.h --- linux-4.4.115-fbx/drivers/crypto/msm./qce_ota.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-4.4.115-fbx/drivers/crypto/msm/qce_ota.h 2019-01-22 16:16:23.111242857 +0100 @@ -0,0 +1,30 @@ +/* Copyright (c) 2010-2011, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +/* Qualcomm Crypto Engine driver OTA APIi */ + +#ifndef __CRYPTO_MSM_QCE_OTA_H +#define __CRYPTO_MSM_QCE_OTA_H + +#include +#include + + +int qce_f8_req(void *handle, struct qce_f8_req *req, + void *cookie, qce_comp_func_ptr_t qce_cb); +int qce_f8_multi_pkt_req(void *handle, struct qce_f8_multi_pkt_req *req, + void *cookie, qce_comp_func_ptr_t qce_cb); +int qce_f9_req(void *handle, struct qce_f9_req *req, + void *cookie, qce_comp_func_ptr_t qce_cb); + +#endif /* __CRYPTO_MSM_QCE_OTA_H */ diff -Nruw linux-4.4.115-fbx/drivers/crypto/msm./qcrypto.c linux-4.4.115-fbx/drivers/crypto/msm/qcrypto.c --- linux-4.4.115-fbx/drivers/crypto/msm./qcrypto.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-4.4.115-fbx/drivers/crypto/msm/qcrypto.c 2019-10-29 09:26:23.505201828 +0100 @@ -0,0 +1,5555 @@ +/* Qualcomm Crypto driver + * + * Copyright (c) 2010-2017, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "qce.h" + +#define DEBUG_MAX_FNAME 16 +#define DEBUG_MAX_RW_BUF 4096 +#define QCRYPTO_BIG_NUMBER 9999999 /* a big number */ + +/* + * For crypto 5.0 which has burst size alignment requirement. + */ +#define MAX_ALIGN_SIZE 0x40 + +#define QCRYPTO_HIGH_BANDWIDTH_TIMEOUT 1000 + + + +/* Status of response workq */ +enum resp_workq_sts { + NOT_SCHEDULED = 0, + IS_SCHEDULED = 1, + SCHEDULE_AGAIN = 2 +}; + +/* Status of req processing by CEs */ +enum req_processing_sts { + STOPPED = 0, + IN_PROGRESS = 1 +}; + +enum qcrypto_bus_state { + BUS_NO_BANDWIDTH = 0, + BUS_HAS_BANDWIDTH, + BUS_BANDWIDTH_RELEASING, + BUS_BANDWIDTH_ALLOCATING, + BUS_SUSPENDED, + BUS_SUSPENDING, +}; + +struct crypto_stat { + u64 aead_sha1_aes_enc; + u64 aead_sha1_aes_dec; + u64 aead_sha1_des_enc; + u64 aead_sha1_des_dec; + u64 aead_sha1_3des_enc; + u64 aead_sha1_3des_dec; + u64 aead_sha256_aes_enc; + u64 aead_sha256_aes_dec; + u64 aead_sha256_des_enc; + u64 aead_sha256_des_dec; + u64 aead_sha256_3des_enc; + u64 aead_sha256_3des_dec; + u64 aead_ccm_aes_enc; + u64 aead_ccm_aes_dec; + u64 aead_rfc4309_ccm_aes_enc; + u64 aead_rfc4309_ccm_aes_dec; + u64 aead_op_success; + u64 aead_op_fail; + u64 aead_bad_msg; + u64 ablk_cipher_aes_enc; + u64 ablk_cipher_aes_dec; + u64 ablk_cipher_des_enc; + u64 ablk_cipher_des_dec; + u64 ablk_cipher_3des_enc; + u64 ablk_cipher_3des_dec; + u64 ablk_cipher_op_success; + u64 ablk_cipher_op_fail; + u64 sha1_digest; + u64 sha256_digest; + u64 sha1_hmac_digest; + u64 sha256_hmac_digest; + u64 ahash_op_success; + u64 ahash_op_fail; +}; +static struct crypto_stat _qcrypto_stat; +static struct dentry *_debug_dent; +static char _debug_read_buf[DEBUG_MAX_RW_BUF]; +static bool _qcrypto_init_assign; +struct crypto_priv; +struct qcrypto_req_control { + unsigned int index; + bool in_use; + struct crypto_engine *pce; + struct crypto_async_request *req; + struct qcrypto_resp_ctx *arsp; + int res; /* execution result */ +}; + +struct crypto_engine { + struct list_head elist; + void *qce; /* qce handle */ + struct platform_device *pdev; /* platform device */ + struct crypto_priv *pcp; + uint32_t bus_scale_handle; + struct crypto_queue req_queue; /* + * request queue for those requests + * that have this engine assigned + * waiting to be executed + */ + u64 total_req; + u64 err_req; + u32 unit; + u32 ce_device; + u32 ce_hw_instance; + unsigned int signature; + + enum qcrypto_bus_state bw_state; + bool high_bw_req; + struct timer_list bw_reaper_timer; + struct work_struct bw_reaper_ws; + struct work_struct bw_allocate_ws; + + /* engine execution sequence number */ + u32 active_seq; + /* last QCRYPTO_HIGH_BANDWIDTH_TIMEOUT active_seq */ + u32 last_active_seq; + + bool check_flag; + /*Added to support multi-requests*/ + unsigned int max_req; + struct qcrypto_req_control *preq_pool; + atomic_t req_count; + bool issue_req; /* an request is being issued to qce */ + bool first_engine; /* this engine is the first engine or not */ + unsigned int irq_cpu; /* the cpu running the irq of this engine */ + unsigned int max_req_used; /* debug stats */ +}; + +#define MAX_SMP_CPU 8 + +struct crypto_priv { + /* CE features supported by target device*/ + struct msm_ce_hw_support platform_support; + + /* CE features/algorithms supported by HW engine*/ + struct ce_hw_support ce_support; + + /* the lock protects crypto queue and req */ + spinlock_t lock; + + /* list of registered algorithms */ + struct list_head alg_list; + + /* current active request */ + struct crypto_async_request *req; + + struct work_struct unlock_ce_ws; + struct list_head engine_list; /* list of qcrypto engines */ + int32_t total_units; /* total units of engines */ + struct mutex engine_lock; + + struct crypto_engine *next_engine; /* next assign engine */ + struct crypto_queue req_queue; /* + * request queue for those requests + * that waiting for an available + * engine. + */ + struct llist_head ordered_resp_list; /* Queue to maintain + * responses in sequence. + */ + atomic_t resp_cnt; + struct workqueue_struct *resp_wq; + struct work_struct resp_work; /* + * Workq to send responses + * in sequence. + */ + enum resp_workq_sts sched_resp_workq_status; + enum req_processing_sts ce_req_proc_sts; + int cpu_getting_irqs_frm_first_ce; + struct crypto_engine *first_engine; + struct crypto_engine *scheduled_eng; /* last engine scheduled */ + + /* debug stats */ + unsigned no_avail; + unsigned resp_stop; + unsigned resp_start; + unsigned max_qlen; + unsigned int queue_work_eng3; + unsigned int queue_work_not_eng3; + unsigned int queue_work_not_eng3_nz; + unsigned int max_resp_qlen; + unsigned int max_reorder_cnt; + unsigned int cpu_req[MAX_SMP_CPU+1]; +}; +static struct crypto_priv qcrypto_dev; +static struct crypto_engine *_qcrypto_static_assign_engine( + struct crypto_priv *cp); +static struct crypto_engine *_avail_eng(struct crypto_priv *cp); +static struct qcrypto_req_control *qcrypto_alloc_req_control( + struct crypto_engine *pce) +{ + int i; + struct qcrypto_req_control *pqcrypto_req_control = pce->preq_pool; + unsigned int req_count; + + for (i = 0; i < pce->max_req; i++) { + if (xchg(&pqcrypto_req_control->in_use, true) == false) { + req_count = atomic_inc_return(&pce->req_count); + if (req_count > pce->max_req_used) + pce->max_req_used = req_count; + return pqcrypto_req_control; + } + pqcrypto_req_control++; + } + return NULL; +} + +static void qcrypto_free_req_control(struct crypto_engine *pce, + struct qcrypto_req_control *preq) +{ + /* do this before free req */ + preq->req = NULL; + preq->arsp = NULL; + /* free req */ + if (xchg(&preq->in_use, false) == false) { + pr_warn("request info %pK free already\n", preq); + } else { + atomic_dec(&pce->req_count); + } +} + +static struct qcrypto_req_control *find_req_control_for_areq( + struct crypto_engine *pce, + struct crypto_async_request *areq) +{ + int i; + struct qcrypto_req_control *pqcrypto_req_control = pce->preq_pool; + + for (i = 0; i < pce->max_req; i++) { + if (pqcrypto_req_control->req == areq) + return pqcrypto_req_control; + pqcrypto_req_control++; + } + return NULL; +} + +static void qcrypto_init_req_control(struct crypto_engine *pce, + struct qcrypto_req_control *pqcrypto_req_control) +{ + int i; + + pce->preq_pool = pqcrypto_req_control; + atomic_set(&pce->req_count, 0); + for (i = 0; i < pce->max_req; i++) { + pqcrypto_req_control->index = i; + pqcrypto_req_control->in_use = false; + pqcrypto_req_control->pce = pce; + pqcrypto_req_control++; + } +} + +static struct crypto_engine *_qrypto_find_pengine_device(struct crypto_priv *cp, + unsigned int device) +{ + struct crypto_engine *entry = NULL; + unsigned long flags; + + spin_lock_irqsave(&cp->lock, flags); + list_for_each_entry(entry, &cp->engine_list, elist) { + if (entry->ce_device == device) + break; + } + spin_unlock_irqrestore(&cp->lock, flags); + + if (((entry != NULL) && (entry->ce_device != device)) || + (entry == NULL)) { + pr_err("Device node for CE device %d NOT FOUND!!\n", + device); + return NULL; + } + + return entry; +} + +static struct crypto_engine *_qrypto_find_pengine_device_hw + (struct crypto_priv *cp, + u32 device, + u32 hw_instance) +{ + struct crypto_engine *entry = NULL; + unsigned long flags; + + spin_lock_irqsave(&cp->lock, flags); + list_for_each_entry(entry, &cp->engine_list, elist) { + if ((entry->ce_device == device) && + (entry->ce_hw_instance == hw_instance)) + break; + } + spin_unlock_irqrestore(&cp->lock, flags); + + if (((entry != NULL) && + ((entry->ce_device != device) + || (entry->ce_hw_instance != hw_instance))) + || (entry == NULL)) { + pr_err("Device node for CE device %d NOT FOUND!!\n", + device); + return NULL; + } + return entry; +} + +int qcrypto_get_num_engines(void) +{ + struct crypto_priv *cp = &qcrypto_dev; + struct crypto_engine *entry = NULL; + int count = 0; + + list_for_each_entry(entry, &cp->engine_list, elist) { + count++; + } + return count; +} +EXPORT_SYMBOL(qcrypto_get_num_engines); + +void qcrypto_get_engine_list(size_t num_engines, + struct crypto_engine_entry *arr) +{ + struct crypto_priv *cp = &qcrypto_dev; + struct crypto_engine *entry = NULL; + size_t arr_index = 0; + + list_for_each_entry(entry, &cp->engine_list, elist) { + arr[arr_index].ce_device = entry->ce_device; + arr[arr_index].hw_instance = entry->ce_hw_instance; + arr_index++; + if (arr_index >= num_engines) + break; + } +} +EXPORT_SYMBOL(qcrypto_get_engine_list); + +enum qcrypto_alg_type { + QCRYPTO_ALG_CIPHER = 0, + QCRYPTO_ALG_SHA = 1, + QCRYPTO_ALG_AEAD = 2, + QCRYPTO_ALG_LAST +}; + +struct qcrypto_alg { + struct list_head entry; + struct crypto_alg cipher_alg; + struct ahash_alg sha_alg; + struct aead_alg aead_alg; + enum qcrypto_alg_type alg_type; + struct crypto_priv *cp; +}; + +#define QCRYPTO_MAX_KEY_SIZE 64 +/* max of AES_BLOCK_SIZE, DES3_EDE_BLOCK_SIZE */ +#define QCRYPTO_MAX_IV_LENGTH 16 + +#define QCRYPTO_CCM4309_NONCE_LEN 3 + +struct qcrypto_cipher_ctx { + struct list_head rsp_queue; /* response queue */ + struct crypto_engine *pengine; /* fixed engine assigned to this tfm */ + struct crypto_priv *cp; + unsigned int flags; + + enum qce_hash_alg_enum auth_alg; /* for aead */ + u8 auth_key[QCRYPTO_MAX_KEY_SIZE]; + u8 iv[QCRYPTO_MAX_IV_LENGTH]; + + u8 enc_key[QCRYPTO_MAX_KEY_SIZE]; + unsigned int enc_key_len; + + unsigned int authsize; + unsigned int auth_key_len; + + u8 ccm4309_nonce[QCRYPTO_CCM4309_NONCE_LEN]; + + struct crypto_ablkcipher *cipher_aes192_fb; + + struct crypto_ahash *ahash_aead_aes192_fb; +}; + +struct qcrypto_resp_ctx { + struct list_head list; + struct llist_node llist; + struct crypto_async_request *async_req; /* async req */ + int res; /* execution result */ +}; + +struct qcrypto_cipher_req_ctx { + struct qcrypto_resp_ctx rsp_entry;/* rsp entry. */ + struct crypto_engine *pengine; /* engine assigned to this request */ + u8 *iv; + u8 rfc4309_iv[QCRYPTO_MAX_IV_LENGTH]; + unsigned int ivsize; + int aead; + int ccmtype; /* default: 0, rfc4309: 1 */ + struct scatterlist asg; /* Formatted associated data sg */ + unsigned char *adata; /* Pointer to formatted assoc data */ + enum qce_cipher_alg_enum alg; + enum qce_cipher_dir_enum dir; + enum qce_cipher_mode_enum mode; + + struct scatterlist *orig_src; /* Original src sg ptr */ + struct scatterlist *orig_dst; /* Original dst sg ptr */ + struct scatterlist dsg; /* Dest Data sg */ + struct scatterlist ssg; /* Source Data sg */ + unsigned char *data; /* Incoming data pointer*/ + + struct aead_request *aead_req; + struct ahash_request *fb_hash_req; + uint8_t fb_ahash_digest[SHA256_DIGEST_SIZE]; + struct scatterlist fb_ablkcipher_src_sg[2]; + struct scatterlist fb_ablkcipher_dst_sg[2]; + char *fb_aes_iv; + unsigned int fb_ahash_length; + struct ablkcipher_request *fb_aes_req; + struct scatterlist *fb_aes_src; + struct scatterlist *fb_aes_dst; + unsigned int fb_aes_cryptlen; +}; + +#define SHA_MAX_BLOCK_SIZE SHA256_BLOCK_SIZE +#define SHA_MAX_STATE_SIZE (SHA256_DIGEST_SIZE / sizeof(u32)) +#define SHA_MAX_DIGEST_SIZE SHA256_DIGEST_SIZE + +#define MSM_QCRYPTO_REQ_QUEUE_LENGTH 768 +#define COMPLETION_CB_BACKLOG_LENGTH_STOP 400 +#define COMPLETION_CB_BACKLOG_LENGTH_START \ + (COMPLETION_CB_BACKLOG_LENGTH_STOP / 2) + +static uint8_t _std_init_vector_sha1_uint8[] = { + 0x67, 0x45, 0x23, 0x01, 0xEF, 0xCD, 0xAB, 0x89, + 0x98, 0xBA, 0xDC, 0xFE, 0x10, 0x32, 0x54, 0x76, + 0xC3, 0xD2, 0xE1, 0xF0 +}; + +/* standard initialization vector for SHA-256, source: FIPS 180-2 */ +static uint8_t _std_init_vector_sha256_uint8[] = { + 0x6A, 0x09, 0xE6, 0x67, 0xBB, 0x67, 0xAE, 0x85, + 0x3C, 0x6E, 0xF3, 0x72, 0xA5, 0x4F, 0xF5, 0x3A, + 0x51, 0x0E, 0x52, 0x7F, 0x9B, 0x05, 0x68, 0x8C, + 0x1F, 0x83, 0xD9, 0xAB, 0x5B, 0xE0, 0xCD, 0x19 +}; + +struct qcrypto_sha_ctx { + struct list_head rsp_queue; /* response queue */ + struct crypto_engine *pengine; /* fixed engine assigned to this tfm */ + struct crypto_priv *cp; + unsigned int flags; + enum qce_hash_alg_enum alg; + uint32_t diglen; + uint32_t authkey_in_len; + uint8_t authkey[SHA_MAX_BLOCK_SIZE]; + struct ahash_request *ahash_req; + struct completion ahash_req_complete; +}; + +struct qcrypto_sha_req_ctx { + struct qcrypto_resp_ctx rsp_entry;/* rsp entry. */ + struct crypto_engine *pengine; /* engine assigned to this request */ + + struct scatterlist *src; + uint32_t nbytes; + + struct scatterlist *orig_src; /* Original src sg ptr */ + struct scatterlist dsg; /* Data sg */ + unsigned char *data; /* Incoming data pointer*/ + unsigned char *data2; /* Updated data pointer*/ + + uint32_t byte_count[4]; + u64 count; + uint8_t first_blk; + uint8_t last_blk; + uint8_t trailing_buf[SHA_MAX_BLOCK_SIZE]; + uint32_t trailing_buf_len; + + /* dma buffer, Internal use */ + uint8_t staging_dmabuf + [SHA_MAX_BLOCK_SIZE+SHA_MAX_DIGEST_SIZE+MAX_ALIGN_SIZE]; + + uint8_t digest[SHA_MAX_DIGEST_SIZE]; + struct scatterlist sg[2]; +}; + +static void _byte_stream_to_words(uint32_t *iv, unsigned char *b, + unsigned int len) +{ + unsigned n; + + n = len / sizeof(uint32_t); + for (; n > 0; n--) { + *iv = ((*b << 24) & 0xff000000) | + (((*(b+1)) << 16) & 0xff0000) | + (((*(b+2)) << 8) & 0xff00) | + (*(b+3) & 0xff); + b += sizeof(uint32_t); + iv++; + } + + n = len % sizeof(uint32_t); + if (n == 3) { + *iv = ((*b << 24) & 0xff000000) | + (((*(b+1)) << 16) & 0xff0000) | + (((*(b+2)) << 8) & 0xff00); + } else if (n == 2) { + *iv = ((*b << 24) & 0xff000000) | + (((*(b+1)) << 16) & 0xff0000); + } else if (n == 1) { + *iv = ((*b << 24) & 0xff000000); + } +} + +static void _words_to_byte_stream(uint32_t *iv, unsigned char *b, + unsigned int len) +{ + unsigned n = len / sizeof(uint32_t); + + for (; n > 0; n--) { + *b++ = (unsigned char) ((*iv >> 24) & 0xff); + *b++ = (unsigned char) ((*iv >> 16) & 0xff); + *b++ = (unsigned char) ((*iv >> 8) & 0xff); + *b++ = (unsigned char) (*iv & 0xff); + iv++; + } + n = len % sizeof(uint32_t); + if (n == 3) { + *b++ = (unsigned char) ((*iv >> 24) & 0xff); + *b++ = (unsigned char) ((*iv >> 16) & 0xff); + *b = (unsigned char) ((*iv >> 8) & 0xff); + } else if (n == 2) { + *b++ = (unsigned char) ((*iv >> 24) & 0xff); + *b = (unsigned char) ((*iv >> 16) & 0xff); + } else if (n == 1) { + *b = (unsigned char) ((*iv >> 24) & 0xff); + } +} + +static void qcrypto_ce_set_bus(struct crypto_engine *pengine, + bool high_bw_req) +{ + int ret = 0; + + if (high_bw_req) { + ret = qce_enable_clk(pengine->qce); + if (ret) { + pr_err("%s Unable enable clk\n", __func__); + goto clk_err; + } + ret = msm_bus_scale_client_update_request( + pengine->bus_scale_handle, 1); + if (ret) { + pr_err("%s Unable to set to high bandwidth\n", + __func__); + qce_disable_clk(pengine->qce); + goto clk_err; + } + } else { + ret = msm_bus_scale_client_update_request( + pengine->bus_scale_handle, 0); + if (ret) { + pr_err("%s Unable to set to low bandwidth\n", + __func__); + goto clk_err; + } + ret = qce_disable_clk(pengine->qce); + if (ret) { + pr_err("%s Unable disable clk\n", __func__); + ret = msm_bus_scale_client_update_request( + pengine->bus_scale_handle, 1); + if (ret) + pr_err("%s Unable to set to high bandwidth\n", + __func__); + goto clk_err; + } + } +clk_err: + return; + +} + +static void qcrypto_bw_reaper_timer_callback(unsigned long data) +{ + struct crypto_engine *pengine = (struct crypto_engine *)data; + + schedule_work(&pengine->bw_reaper_ws); + + return; +} + +static void qcrypto_bw_set_timeout(struct crypto_engine *pengine) +{ + pengine->bw_reaper_timer.data = + (unsigned long)(pengine); + pengine->bw_reaper_timer.expires = jiffies + + msecs_to_jiffies(QCRYPTO_HIGH_BANDWIDTH_TIMEOUT); + mod_timer(&(pengine->bw_reaper_timer), + pengine->bw_reaper_timer.expires); +} + +static void qcrypto_ce_bw_allocate_req(struct crypto_engine *pengine) +{ + schedule_work(&pengine->bw_allocate_ws); +} + +static int _start_qcrypto_process(struct crypto_priv *cp, + struct crypto_engine *pengine); + +static void qcrypto_bw_allocate_work(struct work_struct *work) +{ + struct crypto_engine *pengine = container_of(work, + struct crypto_engine, bw_allocate_ws); + unsigned long flags; + struct crypto_priv *cp = pengine->pcp; + + spin_lock_irqsave(&cp->lock, flags); + pengine->bw_state = BUS_BANDWIDTH_ALLOCATING; + spin_unlock_irqrestore(&cp->lock, flags); + + qcrypto_ce_set_bus(pengine, true); + qcrypto_bw_set_timeout(pengine); + spin_lock_irqsave(&cp->lock, flags); + pengine->bw_state = BUS_HAS_BANDWIDTH; + pengine->high_bw_req = false; + pengine->active_seq++; + pengine->check_flag = true; + spin_unlock_irqrestore(&cp->lock, flags); + _start_qcrypto_process(cp, pengine); +}; + +static void qcrypto_bw_reaper_work(struct work_struct *work) +{ + struct crypto_engine *pengine = container_of(work, + struct crypto_engine, bw_reaper_ws); + struct crypto_priv *cp = pengine->pcp; + unsigned long flags; + u32 active_seq; + bool restart = false; + + spin_lock_irqsave(&cp->lock, flags); + active_seq = pengine->active_seq; + if (pengine->bw_state == BUS_HAS_BANDWIDTH && + (active_seq == pengine->last_active_seq)) { + + /* check if engine is stuck */ + if (atomic_read(&pengine->req_count) > 0) { + if (pengine->check_flag) + dev_warn(&pengine->pdev->dev, + "The engine appears to be stuck seq %d.\n", + active_seq); + pengine->check_flag = false; + goto ret; + } + if (cp->platform_support.bus_scale_table == NULL) + goto ret; + pengine->bw_state = BUS_BANDWIDTH_RELEASING; + spin_unlock_irqrestore(&cp->lock, flags); + + qcrypto_ce_set_bus(pengine, false); + + spin_lock_irqsave(&cp->lock, flags); + + if (pengine->high_bw_req == true) { + /* we got request while we are disabling clock */ + pengine->bw_state = BUS_BANDWIDTH_ALLOCATING; + spin_unlock_irqrestore(&cp->lock, flags); + + qcrypto_ce_set_bus(pengine, true); + + spin_lock_irqsave(&cp->lock, flags); + pengine->bw_state = BUS_HAS_BANDWIDTH; + pengine->high_bw_req = false; + restart = true; + } else + pengine->bw_state = BUS_NO_BANDWIDTH; + } +ret: + pengine->last_active_seq = active_seq; + spin_unlock_irqrestore(&cp->lock, flags); + if (restart) + _start_qcrypto_process(cp, pengine); + if (pengine->bw_state != BUS_NO_BANDWIDTH) + qcrypto_bw_set_timeout(pengine); +} + +static int qcrypto_count_sg(struct scatterlist *sg, int nbytes) +{ + int i; + + for (i = 0; nbytes > 0 && sg != NULL; i++, sg = sg_next(sg)) + nbytes -= sg->length; + + return i; +} + +static size_t qcrypto_sg_copy_from_buffer(struct scatterlist *sgl, + unsigned int nents, void *buf, size_t buflen) +{ + int i; + size_t offset, len; + + for (i = 0, offset = 0; i < nents; ++i) { + len = sg_copy_from_buffer(sgl, 1, buf, buflen); + buf += len; + buflen -= len; + offset += len; + sgl = sg_next(sgl); + } + + return offset; +} + +static size_t qcrypto_sg_copy_to_buffer(struct scatterlist *sgl, + unsigned int nents, void *buf, size_t buflen) +{ + int i; + size_t offset, len; + + for (i = 0, offset = 0; i < nents; ++i) { + len = sg_copy_to_buffer(sgl, 1, buf, buflen); + buf += len; + buflen -= len; + offset += len; + sgl = sg_next(sgl); + } + + return offset; +} +static struct qcrypto_alg *_qcrypto_sha_alg_alloc(struct crypto_priv *cp, + struct ahash_alg *template) +{ + struct qcrypto_alg *q_alg; + q_alg = kzalloc(sizeof(struct qcrypto_alg), GFP_KERNEL); + if (!q_alg) { + pr_err("qcrypto Memory allocation of q_alg FAIL, error %ld\n", + PTR_ERR(q_alg)); + return ERR_PTR(-ENOMEM); + } + + q_alg->alg_type = QCRYPTO_ALG_SHA; + q_alg->sha_alg = *template; + q_alg->cp = cp; + + return q_alg; +}; + +static struct qcrypto_alg *_qcrypto_cipher_alg_alloc(struct crypto_priv *cp, + struct crypto_alg *template) +{ + struct qcrypto_alg *q_alg; + + q_alg = kzalloc(sizeof(struct qcrypto_alg), GFP_KERNEL); + if (!q_alg) { + pr_err("qcrypto Memory allocation of q_alg FAIL, error %ld\n", + PTR_ERR(q_alg)); + return ERR_PTR(-ENOMEM); + } + + q_alg->alg_type = QCRYPTO_ALG_CIPHER; + q_alg->cipher_alg = *template; + q_alg->cp = cp; + + return q_alg; +}; + +static struct qcrypto_alg *_qcrypto_aead_alg_alloc(struct crypto_priv *cp, + struct aead_alg *template) +{ + struct qcrypto_alg *q_alg; + + q_alg = kzalloc(sizeof(struct qcrypto_alg), GFP_KERNEL); + if (!q_alg) + return ERR_PTR(-ENOMEM); + + q_alg->alg_type = QCRYPTO_ALG_AEAD; + q_alg->aead_alg = *template; + q_alg->cp = cp; + + return q_alg; +}; + +static int _qcrypto_cipher_ctx_init(struct qcrypto_cipher_ctx *ctx, + struct qcrypto_alg *q_alg) +{ + if (!ctx || !q_alg) { + pr_err("ctx or q_alg is NULL\n"); + return -EINVAL; + } + ctx->flags = 0; + /* update context with ptr to cp */ + ctx->cp = q_alg->cp; + /* random first IV */ + get_random_bytes(ctx->iv, QCRYPTO_MAX_IV_LENGTH); + if (_qcrypto_init_assign) { + ctx->pengine = _qcrypto_static_assign_engine(ctx->cp); + if (ctx->pengine == NULL) + return -ENODEV; + } else + ctx->pengine = NULL; + INIT_LIST_HEAD(&ctx->rsp_queue); + ctx->auth_alg = QCE_HASH_LAST; + return 0; +} + +static int _qcrypto_cipher_cra_init(struct crypto_tfm *tfm) +{ + struct crypto_alg *alg = tfm->__crt_alg; + struct qcrypto_alg *q_alg; + struct qcrypto_cipher_ctx *ctx = crypto_tfm_ctx(tfm); + + q_alg = container_of(alg, struct qcrypto_alg, cipher_alg); + return _qcrypto_cipher_ctx_init(ctx, q_alg); +}; + +static int _qcrypto_ahash_cra_init(struct crypto_tfm *tfm) +{ + struct crypto_ahash *ahash = __crypto_ahash_cast(tfm); + struct qcrypto_sha_ctx *sha_ctx = crypto_tfm_ctx(tfm); + struct ahash_alg *alg = container_of(crypto_hash_alg_common(ahash), + struct ahash_alg, halg); + struct qcrypto_alg *q_alg = container_of(alg, struct qcrypto_alg, + sha_alg); + + crypto_ahash_set_reqsize(ahash, sizeof(struct qcrypto_sha_req_ctx)); + /* update context with ptr to cp */ + sha_ctx->cp = q_alg->cp; + sha_ctx->flags = 0; + sha_ctx->ahash_req = NULL; + if (_qcrypto_init_assign) { + sha_ctx->pengine = _qcrypto_static_assign_engine(sha_ctx->cp); + if (sha_ctx->pengine == NULL) + return -ENODEV; + } else + sha_ctx->pengine = NULL; + INIT_LIST_HEAD(&sha_ctx->rsp_queue); + return 0; +}; + +static void _qcrypto_ahash_cra_exit(struct crypto_tfm *tfm) +{ + struct qcrypto_sha_ctx *sha_ctx = crypto_tfm_ctx(tfm); + + if (!list_empty(&sha_ctx->rsp_queue)) + pr_err("_qcrypto_ahash_cra_exit: requests still outstanding"); + if (sha_ctx->ahash_req != NULL) { + ahash_request_free(sha_ctx->ahash_req); + sha_ctx->ahash_req = NULL; + } +}; + + +static void _crypto_sha_hmac_ahash_req_complete( + struct crypto_async_request *req, int err); + +static int _qcrypto_ahash_hmac_cra_init(struct crypto_tfm *tfm) +{ + struct crypto_ahash *ahash = __crypto_ahash_cast(tfm); + struct qcrypto_sha_ctx *sha_ctx = crypto_tfm_ctx(tfm); + int ret = 0; + + ret = _qcrypto_ahash_cra_init(tfm); + if (ret) + return ret; + sha_ctx->ahash_req = ahash_request_alloc(ahash, GFP_KERNEL); + + if (sha_ctx->ahash_req == NULL) { + _qcrypto_ahash_cra_exit(tfm); + return -ENOMEM; + } + + init_completion(&sha_ctx->ahash_req_complete); + ahash_request_set_callback(sha_ctx->ahash_req, + CRYPTO_TFM_REQ_MAY_BACKLOG, + _crypto_sha_hmac_ahash_req_complete, + &sha_ctx->ahash_req_complete); + crypto_ahash_clear_flags(ahash, ~0); + + return 0; +}; + +static int _qcrypto_cra_ablkcipher_init(struct crypto_tfm *tfm) +{ + tfm->crt_ablkcipher.reqsize = sizeof(struct qcrypto_cipher_req_ctx); + return _qcrypto_cipher_cra_init(tfm); +}; + +static int _qcrypto_cra_aes_ablkcipher_init(struct crypto_tfm *tfm) +{ + const char *name = tfm->__crt_alg->cra_name; + struct qcrypto_cipher_ctx *ctx = crypto_tfm_ctx(tfm); + int ret; + struct crypto_priv *cp = &qcrypto_dev; + + if (cp->ce_support.use_sw_aes_cbc_ecb_ctr_algo) { + ctx->cipher_aes192_fb = NULL; + return _qcrypto_cra_ablkcipher_init(tfm); + } + ctx->cipher_aes192_fb = crypto_alloc_ablkcipher(name, 0, + CRYPTO_ALG_ASYNC | CRYPTO_ALG_NEED_FALLBACK); + if (IS_ERR(ctx->cipher_aes192_fb)) { + pr_err("Error allocating fallback algo %s\n", name); + ret = PTR_ERR(ctx->cipher_aes192_fb); + ctx->cipher_aes192_fb = NULL; + return ret; + } + return _qcrypto_cra_ablkcipher_init(tfm); +}; + +static int _qcrypto_aead_cra_init(struct crypto_aead *tfm) +{ + struct qcrypto_cipher_ctx *ctx = crypto_aead_ctx(tfm); + struct aead_alg *aeadalg = crypto_aead_alg(tfm); + struct qcrypto_alg *q_alg = container_of(aeadalg, struct qcrypto_alg, + aead_alg); + return _qcrypto_cipher_ctx_init(ctx, q_alg); +}; + +static int _qcrypto_cra_aead_sha1_init(struct crypto_aead *tfm) +{ + int rc; + struct qcrypto_cipher_ctx *ctx = crypto_aead_ctx(tfm); + + crypto_aead_set_reqsize(tfm, sizeof(struct qcrypto_cipher_req_ctx)); + rc = _qcrypto_aead_cra_init(tfm); + ctx->auth_alg = QCE_HASH_SHA1_HMAC; + return rc; +} + +static int _qcrypto_cra_aead_sha256_init(struct crypto_aead *tfm) +{ + int rc; + struct qcrypto_cipher_ctx *ctx = crypto_aead_ctx(tfm); + + crypto_aead_set_reqsize(tfm, sizeof(struct qcrypto_cipher_req_ctx)); + rc = _qcrypto_aead_cra_init(tfm); + ctx->auth_alg = QCE_HASH_SHA256_HMAC; + return rc; +} + +static int _qcrypto_cra_aead_ccm_init(struct crypto_aead *tfm) +{ + int rc; + struct qcrypto_cipher_ctx *ctx = crypto_aead_ctx(tfm); + + crypto_aead_set_reqsize(tfm, sizeof(struct qcrypto_cipher_req_ctx)); + rc = _qcrypto_aead_cra_init(tfm); + ctx->auth_alg = QCE_HASH_AES_CMAC; + return rc; +} + +static int _qcrypto_cra_aead_rfc4309_ccm_init(struct crypto_aead *tfm) +{ + int rc; + struct qcrypto_cipher_ctx *ctx = crypto_aead_ctx(tfm); + + crypto_aead_set_reqsize(tfm, sizeof(struct qcrypto_cipher_req_ctx)); + rc = _qcrypto_aead_cra_init(tfm); + ctx->auth_alg = QCE_HASH_AES_CMAC; + return rc; +} + +static int _qcrypto_cra_aead_aes_sha1_init(struct crypto_aead *tfm) +{ + int rc; + struct qcrypto_cipher_ctx *ctx = crypto_aead_ctx(tfm); + struct crypto_priv *cp = &qcrypto_dev; + + crypto_aead_set_reqsize(tfm, sizeof(struct qcrypto_cipher_req_ctx)); + rc = _qcrypto_aead_cra_init(tfm); + if (rc) + return rc; + ctx->cipher_aes192_fb = NULL; + ctx->ahash_aead_aes192_fb = NULL; + if (!cp->ce_support.aes_key_192) { + ctx->cipher_aes192_fb = crypto_alloc_ablkcipher( + "cbc(aes)", 0, 0); + if (IS_ERR(ctx->cipher_aes192_fb)) { + ctx->cipher_aes192_fb = NULL; + } else { + ctx->ahash_aead_aes192_fb = crypto_alloc_ahash( + "hmac(sha1)", 0, 0); + if (IS_ERR(ctx->ahash_aead_aes192_fb)) { + ctx->ahash_aead_aes192_fb = NULL; + crypto_free_ablkcipher(ctx->cipher_aes192_fb); + ctx->cipher_aes192_fb = NULL; + } + } + } + ctx->auth_alg = QCE_HASH_SHA1_HMAC; + return 0; +} + +static int _qcrypto_cra_aead_aes_sha256_init(struct crypto_aead *tfm) +{ + int rc; + struct qcrypto_cipher_ctx *ctx = crypto_aead_ctx(tfm); + struct crypto_priv *cp = &qcrypto_dev; + + crypto_aead_set_reqsize(tfm, sizeof(struct qcrypto_cipher_req_ctx)); + rc = _qcrypto_aead_cra_init(tfm); + if (rc) + return rc; + ctx->cipher_aes192_fb = NULL; + ctx->ahash_aead_aes192_fb = NULL; + if (!cp->ce_support.aes_key_192) { + ctx->cipher_aes192_fb = crypto_alloc_ablkcipher( + "cbc(aes)", 0, 0); + if (IS_ERR(ctx->cipher_aes192_fb)) { + ctx->cipher_aes192_fb = NULL; + } else { + ctx->ahash_aead_aes192_fb = crypto_alloc_ahash( + "hmac(sha256)", 0, 0); + if (IS_ERR(ctx->ahash_aead_aes192_fb)) { + ctx->ahash_aead_aes192_fb = NULL; + crypto_free_ablkcipher(ctx->cipher_aes192_fb); + ctx->cipher_aes192_fb = NULL; + } + } + } + ctx->auth_alg = QCE_HASH_SHA256_HMAC; + return 0; +} + +static void _qcrypto_cra_ablkcipher_exit(struct crypto_tfm *tfm) +{ + struct qcrypto_cipher_ctx *ctx = crypto_tfm_ctx(tfm); + + if (!list_empty(&ctx->rsp_queue)) + pr_err("_qcrypto__cra_ablkcipher_exit: requests still outstanding"); +}; + +static void _qcrypto_cra_aes_ablkcipher_exit(struct crypto_tfm *tfm) +{ + struct qcrypto_cipher_ctx *ctx = crypto_tfm_ctx(tfm); + + _qcrypto_cra_ablkcipher_exit(tfm); + if (ctx->cipher_aes192_fb) + crypto_free_ablkcipher(ctx->cipher_aes192_fb); + ctx->cipher_aes192_fb = NULL; +} + +static void _qcrypto_cra_aead_exit(struct crypto_aead *tfm) +{ + struct qcrypto_cipher_ctx *ctx = crypto_aead_ctx(tfm); + + if (!list_empty(&ctx->rsp_queue)) + pr_err("_qcrypto__cra_aead_exit: requests still outstanding"); +} + +static void _qcrypto_cra_aead_aes_exit(struct crypto_aead *tfm) +{ + struct qcrypto_cipher_ctx *ctx = crypto_aead_ctx(tfm); + + if (!list_empty(&ctx->rsp_queue)) + pr_err("_qcrypto__cra_aead_exit: requests still outstanding"); + if (ctx->cipher_aes192_fb) + crypto_free_ablkcipher(ctx->cipher_aes192_fb); + if (ctx->ahash_aead_aes192_fb) + crypto_free_ahash(ctx->ahash_aead_aes192_fb); + ctx->cipher_aes192_fb = NULL; + ctx->ahash_aead_aes192_fb = NULL; +} + +static int _disp_stats(int id) +{ + struct crypto_stat *pstat; + int len = 0; + unsigned long flags; + struct crypto_priv *cp = &qcrypto_dev; + struct crypto_engine *pe; + int i; + + pstat = &_qcrypto_stat; + len = scnprintf(_debug_read_buf, DEBUG_MAX_RW_BUF - 1, + "\nQualcomm crypto accelerator %d Statistics\n", + id + 1); + + len += scnprintf(_debug_read_buf + len, DEBUG_MAX_RW_BUF - len - 1, + " ABLK CIPHER AES encryption : %llu\n", + pstat->ablk_cipher_aes_enc); + len += scnprintf(_debug_read_buf + len, DEBUG_MAX_RW_BUF - len - 1, + " ABLK CIPHER AES decryption : %llu\n", + pstat->ablk_cipher_aes_dec); + + len += scnprintf(_debug_read_buf + len, DEBUG_MAX_RW_BUF - len - 1, + " ABLK CIPHER DES encryption : %llu\n", + pstat->ablk_cipher_des_enc); + len += scnprintf(_debug_read_buf + len, DEBUG_MAX_RW_BUF - len - 1, + " ABLK CIPHER DES decryption : %llu\n", + pstat->ablk_cipher_des_dec); + + len += scnprintf(_debug_read_buf + len, DEBUG_MAX_RW_BUF - len - 1, + " ABLK CIPHER 3DES encryption : %llu\n", + pstat->ablk_cipher_3des_enc); + + len += scnprintf(_debug_read_buf + len, DEBUG_MAX_RW_BUF - len - 1, + " ABLK CIPHER 3DES decryption : %llu\n", + pstat->ablk_cipher_3des_dec); + + len += scnprintf(_debug_read_buf + len, DEBUG_MAX_RW_BUF - len - 1, + " ABLK CIPHER operation success : %llu\n", + pstat->ablk_cipher_op_success); + len += scnprintf(_debug_read_buf + len, DEBUG_MAX_RW_BUF - len - 1, + " ABLK CIPHER operation fail : %llu\n", + pstat->ablk_cipher_op_fail); + len += scnprintf(_debug_read_buf + len, DEBUG_MAX_RW_BUF - len - 1, + "\n"); + + len += scnprintf(_debug_read_buf + len, DEBUG_MAX_RW_BUF - len - 1, + " AEAD SHA1-AES encryption : %llu\n", + pstat->aead_sha1_aes_enc); + len += scnprintf(_debug_read_buf + len, DEBUG_MAX_RW_BUF - len - 1, + " AEAD SHA1-AES decryption : %llu\n", + pstat->aead_sha1_aes_dec); + + len += scnprintf(_debug_read_buf + len, DEBUG_MAX_RW_BUF - len - 1, + " AEAD SHA1-DES encryption : %llu\n", + pstat->aead_sha1_des_enc); + len += scnprintf(_debug_read_buf + len, DEBUG_MAX_RW_BUF - len - 1, + " AEAD SHA1-DES decryption : %llu\n", + pstat->aead_sha1_des_dec); + + len += scnprintf(_debug_read_buf + len, DEBUG_MAX_RW_BUF - len - 1, + " AEAD SHA1-3DES encryption : %llu\n", + pstat->aead_sha1_3des_enc); + len += scnprintf(_debug_read_buf + len, DEBUG_MAX_RW_BUF - len - 1, + " AEAD SHA1-3DES decryption : %llu\n", + pstat->aead_sha1_3des_dec); + + len += scnprintf(_debug_read_buf + len, DEBUG_MAX_RW_BUF - len - 1, + " AEAD SHA256-AES encryption : %llu\n", + pstat->aead_sha256_aes_enc); + len += scnprintf(_debug_read_buf + len, DEBUG_MAX_RW_BUF - len - 1, + " AEAD SHA256-AES decryption : %llu\n", + pstat->aead_sha256_aes_dec); + + len += scnprintf(_debug_read_buf + len, DEBUG_MAX_RW_BUF - len - 1, + " AEAD SHA256-DES encryption : %llu\n", + pstat->aead_sha256_des_enc); + len += scnprintf(_debug_read_buf + len, DEBUG_MAX_RW_BUF - len - 1, + " AEAD SHA256-DES decryption : %llu\n", + pstat->aead_sha256_des_dec); + + len += scnprintf(_debug_read_buf + len, DEBUG_MAX_RW_BUF - len - 1, + " AEAD SHA256-3DES encryption : %llu\n", + pstat->aead_sha256_3des_enc); + len += scnprintf(_debug_read_buf + len, DEBUG_MAX_RW_BUF - len - 1, + " AEAD SHA256-3DES decryption : %llu\n", + pstat->aead_sha256_3des_dec); + + len += scnprintf(_debug_read_buf + len, DEBUG_MAX_RW_BUF - len - 1, + " AEAD CCM-AES encryption : %llu\n", + pstat->aead_ccm_aes_enc); + len += scnprintf(_debug_read_buf + len, DEBUG_MAX_RW_BUF - len - 1, + " AEAD CCM-AES decryption : %llu\n", + pstat->aead_ccm_aes_dec); + len += scnprintf(_debug_read_buf + len, DEBUG_MAX_RW_BUF - len - 1, + " AEAD RFC4309-CCM-AES encryption : %llu\n", + pstat->aead_rfc4309_ccm_aes_enc); + len += scnprintf(_debug_read_buf + len, DEBUG_MAX_RW_BUF - len - 1, + " AEAD RFC4309-CCM-AES decryption : %llu\n", + pstat->aead_rfc4309_ccm_aes_dec); + len += scnprintf(_debug_read_buf + len, DEBUG_MAX_RW_BUF - len - 1, + " AEAD operation success : %llu\n", + pstat->aead_op_success); + len += scnprintf(_debug_read_buf + len, DEBUG_MAX_RW_BUF - len - 1, + " AEAD operation fail : %llu\n", + pstat->aead_op_fail); + len += scnprintf(_debug_read_buf + len, DEBUG_MAX_RW_BUF - len - 1, + " AEAD bad message : %llu\n", + pstat->aead_bad_msg); + len += scnprintf(_debug_read_buf + len, DEBUG_MAX_RW_BUF - len - 1, + "\n"); + + len += scnprintf(_debug_read_buf + len, DEBUG_MAX_RW_BUF - len - 1, + " AHASH SHA1 digest : %llu\n", + pstat->sha1_digest); + len += scnprintf(_debug_read_buf + len, DEBUG_MAX_RW_BUF - len - 1, + " AHASH SHA256 digest : %llu\n", + pstat->sha256_digest); + len += scnprintf(_debug_read_buf + len, DEBUG_MAX_RW_BUF - len - 1, + " AHASH SHA1 HMAC digest : %llu\n", + pstat->sha1_hmac_digest); + len += scnprintf(_debug_read_buf + len, DEBUG_MAX_RW_BUF - len - 1, + " AHASH SHA256 HMAC digest : %llu\n", + pstat->sha256_hmac_digest); + len += scnprintf(_debug_read_buf + len, DEBUG_MAX_RW_BUF - len - 1, + " AHASH operation success : %llu\n", + pstat->ahash_op_success); + len += scnprintf(_debug_read_buf + len, DEBUG_MAX_RW_BUF - len - 1, + " AHASH operation fail : %llu\n", + pstat->ahash_op_fail); + len += scnprintf(_debug_read_buf + len, DEBUG_MAX_RW_BUF - len - 1, + " resp start, resp stop, max rsp queue reorder-cnt : %u %u %u %u\n", + cp->resp_start, cp->resp_stop, + cp->max_resp_qlen, cp->max_reorder_cnt); + len += scnprintf(_debug_read_buf + len, DEBUG_MAX_RW_BUF - len - 1, + " max queue legnth, no avail : %u %u\n", + cp->max_qlen, cp->no_avail); + len += scnprintf(_debug_read_buf + len, DEBUG_MAX_RW_BUF - len - 1, + " work queue : %u %u %u\n", + cp->queue_work_eng3, + cp->queue_work_not_eng3, + cp->queue_work_not_eng3_nz); + len += scnprintf(_debug_read_buf + len, DEBUG_MAX_RW_BUF - len - 1, + "\n"); + spin_lock_irqsave(&cp->lock, flags); + list_for_each_entry(pe, &cp->engine_list, elist) { + len += scnprintf( + _debug_read_buf + len, + DEBUG_MAX_RW_BUF - len - 1, + " Engine %4d Req max %d : %llu\n", + pe->unit, + pe->max_req_used, + pe->total_req + ); + len += scnprintf( + _debug_read_buf + len, + DEBUG_MAX_RW_BUF - len - 1, + " Engine %4d Req Error : %llu\n", + pe->unit, + pe->err_req + ); + qce_get_driver_stats(pe->qce); + } + spin_unlock_irqrestore(&cp->lock, flags); + + for (i = 0; i < MAX_SMP_CPU+1; i++) + if (cp->cpu_req[i]) + len += scnprintf( + _debug_read_buf + len, + DEBUG_MAX_RW_BUF - len - 1, + "CPU %d Issue Req : %d\n", + i, cp->cpu_req[i]); + return len; +} + +static void _qcrypto_remove_engine(struct crypto_engine *pengine) +{ + struct crypto_priv *cp; + struct qcrypto_alg *q_alg; + struct qcrypto_alg *n; + unsigned long flags; + struct crypto_engine *pe; + + cp = pengine->pcp; + + spin_lock_irqsave(&cp->lock, flags); + list_del(&pengine->elist); + if (pengine->first_engine) { + cp->first_engine = NULL; + pe = list_first_entry(&cp->engine_list, struct crypto_engine, + elist); + if (pe) { + pe->first_engine = true; + cp->first_engine = pe; + } + } + if (cp->next_engine == pengine) + cp->next_engine = NULL; + if (cp->scheduled_eng == pengine) + cp->scheduled_eng = NULL; + spin_unlock_irqrestore(&cp->lock, flags); + + cp->total_units--; + + cancel_work_sync(&pengine->bw_reaper_ws); + cancel_work_sync(&pengine->bw_allocate_ws); + del_timer_sync(&pengine->bw_reaper_timer); + + if (pengine->bus_scale_handle != 0) + msm_bus_scale_unregister_client(pengine->bus_scale_handle); + pengine->bus_scale_handle = 0; + + kzfree(pengine->preq_pool); + + if (cp->total_units) + return; + + list_for_each_entry_safe(q_alg, n, &cp->alg_list, entry) { + if (q_alg->alg_type == QCRYPTO_ALG_CIPHER) + crypto_unregister_alg(&q_alg->cipher_alg); + if (q_alg->alg_type == QCRYPTO_ALG_SHA) + crypto_unregister_ahash(&q_alg->sha_alg); + if (q_alg->alg_type == QCRYPTO_ALG_AEAD) + crypto_unregister_aead(&q_alg->aead_alg); + list_del(&q_alg->entry); + kzfree(q_alg); + } +} + +static int _qcrypto_remove(struct platform_device *pdev) +{ + struct crypto_engine *pengine; + struct crypto_priv *cp; + + pengine = platform_get_drvdata(pdev); + + if (!pengine) + return 0; + cp = pengine->pcp; + mutex_lock(&cp->engine_lock); + _qcrypto_remove_engine(pengine); + mutex_unlock(&cp->engine_lock); + if (pengine->qce) + qce_close(pengine->qce); + kzfree(pengine); + return 0; +} + +static int _qcrypto_check_aes_keylen(struct crypto_ablkcipher *cipher, + struct crypto_priv *cp, unsigned int len) +{ + + switch (len) { + case AES_KEYSIZE_128: + case AES_KEYSIZE_256: + break; + case AES_KEYSIZE_192: + if (cp->ce_support.aes_key_192) + break; + default: + crypto_ablkcipher_set_flags(cipher, CRYPTO_TFM_RES_BAD_KEY_LEN); + return -EINVAL; + }; + + return 0; +} + +static int _qcrypto_setkey_aes_192_fallback(struct crypto_ablkcipher *cipher, + const u8 *key) +{ + struct crypto_tfm *tfm = crypto_ablkcipher_tfm(cipher); + struct qcrypto_cipher_ctx *ctx = crypto_tfm_ctx(tfm); + int ret; + + ctx->enc_key_len = AES_KEYSIZE_192; + ctx->cipher_aes192_fb->base.crt_flags &= ~CRYPTO_TFM_REQ_MASK; + ctx->cipher_aes192_fb->base.crt_flags |= + (cipher->base.crt_flags & CRYPTO_TFM_REQ_MASK); + ret = crypto_ablkcipher_setkey(ctx->cipher_aes192_fb, key, + AES_KEYSIZE_192); + if (ret) { + tfm->crt_flags &= ~CRYPTO_TFM_RES_MASK; + tfm->crt_flags |= + (cipher->base.crt_flags & CRYPTO_TFM_RES_MASK); + } + return ret; +} + +static int _qcrypto_setkey_aes(struct crypto_ablkcipher *cipher, const u8 *key, + unsigned int len) +{ + struct crypto_tfm *tfm = crypto_ablkcipher_tfm(cipher); + struct qcrypto_cipher_ctx *ctx = crypto_tfm_ctx(tfm); + struct crypto_priv *cp = ctx->cp; + + if ((ctx->flags & QCRYPTO_CTX_USE_HW_KEY) == QCRYPTO_CTX_USE_HW_KEY) + return 0; + + if ((len == AES_KEYSIZE_192) && (!cp->ce_support.aes_key_192) + && ctx->cipher_aes192_fb) + return _qcrypto_setkey_aes_192_fallback(cipher, key); + + if (_qcrypto_check_aes_keylen(cipher, cp, len)) { + return -EINVAL; + } else { + ctx->enc_key_len = len; + if (!(ctx->flags & QCRYPTO_CTX_USE_PIPE_KEY)) { + if (key != NULL) { + memcpy(ctx->enc_key, key, len); + } else { + pr_err("%s Inavlid key pointer\n", __func__); + return -EINVAL; + } + } + } + return 0; +}; + +static int _qcrypto_setkey_aes_xts(struct crypto_ablkcipher *cipher, + const u8 *key, unsigned int len) +{ + struct crypto_tfm *tfm = crypto_ablkcipher_tfm(cipher); + struct qcrypto_cipher_ctx *ctx = crypto_tfm_ctx(tfm); + struct crypto_priv *cp = ctx->cp; + + if ((ctx->flags & QCRYPTO_CTX_USE_HW_KEY) == QCRYPTO_CTX_USE_HW_KEY) + return 0; + if (_qcrypto_check_aes_keylen(cipher, cp, len/2)) { + return -EINVAL; + } else { + ctx->enc_key_len = len; + if (!(ctx->flags & QCRYPTO_CTX_USE_PIPE_KEY)) { + if (key != NULL) { + memcpy(ctx->enc_key, key, len); + } else { + pr_err("%s Inavlid key pointer\n", __func__); + return -EINVAL; + } + } + } + return 0; +}; + +static int _qcrypto_setkey_des(struct crypto_ablkcipher *cipher, const u8 *key, + unsigned int len) +{ + struct crypto_tfm *tfm = crypto_ablkcipher_tfm(cipher); + struct qcrypto_cipher_ctx *ctx = crypto_tfm_ctx(tfm); + u32 tmp[DES_EXPKEY_WORDS]; + int ret; + + if (!key) { + pr_err("%s Inavlid key pointer\n", __func__); + return -EINVAL; + } + + ret = des_ekey(tmp, key); + + if ((ctx->flags & QCRYPTO_CTX_USE_HW_KEY) == QCRYPTO_CTX_USE_HW_KEY) { + pr_err("%s HW KEY usage not supported for DES algorithm\n", + __func__); + return 0; + }; + + if (len != DES_KEY_SIZE) { + crypto_ablkcipher_set_flags(cipher, CRYPTO_TFM_RES_BAD_KEY_LEN); + return -EINVAL; + }; + + if (unlikely(ret == 0) && (tfm->crt_flags & CRYPTO_TFM_REQ_WEAK_KEY)) { + tfm->crt_flags |= CRYPTO_TFM_RES_WEAK_KEY; + return -EINVAL; + } + + ctx->enc_key_len = len; + if (!(ctx->flags & QCRYPTO_CTX_USE_PIPE_KEY)) + memcpy(ctx->enc_key, key, len); + + return 0; +}; + +static int _qcrypto_setkey_3des(struct crypto_ablkcipher *cipher, const u8 *key, + unsigned int len) +{ + struct crypto_tfm *tfm = crypto_ablkcipher_tfm(cipher); + struct qcrypto_cipher_ctx *ctx = crypto_tfm_ctx(tfm); + + if ((ctx->flags & QCRYPTO_CTX_USE_HW_KEY) == QCRYPTO_CTX_USE_HW_KEY) { + pr_err("%s HW KEY usage not supported for 3DES algorithm\n", + __func__); + return 0; + }; + if (len != DES3_EDE_KEY_SIZE) { + crypto_ablkcipher_set_flags(cipher, CRYPTO_TFM_RES_BAD_KEY_LEN); + return -EINVAL; + }; + ctx->enc_key_len = len; + if (!(ctx->flags & QCRYPTO_CTX_USE_PIPE_KEY)) { + if (key != NULL) { + memcpy(ctx->enc_key, key, len); + } else { + pr_err("%s Inavlid key pointer\n", __func__); + return -EINVAL; + } + } + return 0; +}; + +static void seq_response(struct work_struct *work) +{ + struct crypto_priv *cp = container_of(work, struct crypto_priv, + resp_work); + struct llist_node *list; + struct llist_node *rev = NULL; + struct crypto_engine *pengine; + unsigned long flags; + int total_unit; + +again: + list = llist_del_all(&cp->ordered_resp_list); + + if (!list) + goto end; + + while (list) { + struct llist_node *t = list; + list = llist_next(list); + + t->next = rev; + rev = t; + } + + while (rev) { + struct qcrypto_resp_ctx *arsp; + struct crypto_async_request *areq; + + arsp = container_of(rev, struct qcrypto_resp_ctx, llist); + rev = llist_next(rev); + + areq = arsp->async_req; + local_bh_disable(); + areq->complete(areq, arsp->res); + local_bh_enable(); + atomic_dec(&cp->resp_cnt); + } + + if (atomic_read(&cp->resp_cnt) < COMPLETION_CB_BACKLOG_LENGTH_START && + (cmpxchg(&cp->ce_req_proc_sts, STOPPED, IN_PROGRESS) + == STOPPED)) { + cp->resp_start++; + for (total_unit = cp->total_units; total_unit-- > 0;) { + spin_lock_irqsave(&cp->lock, flags); + pengine = _avail_eng(cp); + spin_unlock_irqrestore(&cp->lock, flags); + if (pengine) + _start_qcrypto_process(cp, pengine); + else + break; + } + } +end: + if (cmpxchg(&cp->sched_resp_workq_status, SCHEDULE_AGAIN, + IS_SCHEDULED) == SCHEDULE_AGAIN) + goto again; + else if (cmpxchg(&cp->sched_resp_workq_status, IS_SCHEDULED, + NOT_SCHEDULED) == SCHEDULE_AGAIN) + goto end; +} + +#define SCHEUDLE_RSP_QLEN_THRESHOLD 64 + +static void _qcrypto_tfm_complete(struct crypto_engine *pengine, u32 type, + void *tfm_ctx, + struct qcrypto_resp_ctx *cur_arsp, + int res) +{ + struct crypto_priv *cp = pengine->pcp; + unsigned long flags; + struct qcrypto_resp_ctx *arsp; + struct list_head *plist; + unsigned int resp_qlen; + unsigned int cnt = 0; + + switch (type) { + case CRYPTO_ALG_TYPE_AHASH: + plist = &((struct qcrypto_sha_ctx *) tfm_ctx)->rsp_queue; + break; + case CRYPTO_ALG_TYPE_ABLKCIPHER: + case CRYPTO_ALG_TYPE_AEAD: + default: + plist = &((struct qcrypto_cipher_ctx *) tfm_ctx)->rsp_queue; + break; + } + + spin_lock_irqsave(&cp->lock, flags); + + cur_arsp->res = res; + while (!list_empty(plist)) { + arsp = list_first_entry(plist, + struct qcrypto_resp_ctx, list); + if (arsp->res == -EINPROGRESS) + break; + else { + list_del(&arsp->list); + llist_add(&arsp->llist, &cp->ordered_resp_list); + atomic_inc(&cp->resp_cnt); + cnt++; + } + } + resp_qlen = atomic_read(&cp->resp_cnt); + if (resp_qlen > cp->max_resp_qlen) + cp->max_resp_qlen = resp_qlen; + if (cnt > cp->max_reorder_cnt) + cp->max_reorder_cnt = cnt; + if ((resp_qlen >= COMPLETION_CB_BACKLOG_LENGTH_STOP) && + cmpxchg(&cp->ce_req_proc_sts, IN_PROGRESS, + STOPPED) == IN_PROGRESS) { + cp->resp_stop++; + } + + spin_unlock_irqrestore(&cp->lock, flags); + +retry: + if (!llist_empty(&cp->ordered_resp_list)) { + unsigned int cpu; + + if (pengine->first_engine) { + cpu = WORK_CPU_UNBOUND; + cp->queue_work_eng3++; + } else { + cp->queue_work_not_eng3++; + cpu = cp->cpu_getting_irqs_frm_first_ce; + /* + * If source not the first engine, and there + * are outstanding requests going on first engine, + * skip scheduling of work queue to anticipate + * more may be coming. If the response queue + * length exceeds threshold, to avoid further + * delay, schedule work queue immediately. + */ + if (cp->first_engine && atomic_read( + &cp->first_engine->req_count)) { + if (resp_qlen < SCHEUDLE_RSP_QLEN_THRESHOLD) + return; + cp->queue_work_not_eng3_nz++; + } + } + if (cmpxchg(&cp->sched_resp_workq_status, NOT_SCHEDULED, + IS_SCHEDULED) == NOT_SCHEDULED) + queue_work_on(cpu, cp->resp_wq, &cp->resp_work); + else if (cmpxchg(&cp->sched_resp_workq_status, IS_SCHEDULED, + SCHEDULE_AGAIN) == NOT_SCHEDULED) + goto retry; + } +} + +static void req_done(struct qcrypto_req_control *pqcrypto_req_control) +{ + struct crypto_engine *pengine; + struct crypto_async_request *areq; + struct crypto_priv *cp; + struct qcrypto_resp_ctx *arsp; + u32 type = 0; + void *tfm_ctx = NULL; + unsigned int cpu; + int res; + + pengine = pqcrypto_req_control->pce; + cp = pengine->pcp; + areq = pqcrypto_req_control->req; + arsp = pqcrypto_req_control->arsp; + res = pqcrypto_req_control->res; + qcrypto_free_req_control(pengine, pqcrypto_req_control); + + if (areq) { + type = crypto_tfm_alg_type(areq->tfm); + tfm_ctx = crypto_tfm_ctx(areq->tfm); + } + cpu = smp_processor_id(); + pengine->irq_cpu = cpu; + if (pengine->first_engine) { + if (cpu != cp->cpu_getting_irqs_frm_first_ce) + cp->cpu_getting_irqs_frm_first_ce = cpu; + } + if (areq) + _qcrypto_tfm_complete(pengine, type, tfm_ctx, arsp, res); + if (ACCESS_ONCE(cp->ce_req_proc_sts) == IN_PROGRESS) + _start_qcrypto_process(cp, pengine); +} + +static void _qce_ahash_complete(void *cookie, unsigned char *digest, + unsigned char *authdata, int ret) +{ + struct ahash_request *areq = (struct ahash_request *) cookie; + struct crypto_async_request *async_req; + struct crypto_ahash *ahash = crypto_ahash_reqtfm(areq); + struct qcrypto_sha_ctx *sha_ctx = crypto_tfm_ctx(areq->base.tfm); + struct qcrypto_sha_req_ctx *rctx = ahash_request_ctx(areq); + struct crypto_priv *cp = sha_ctx->cp; + struct crypto_stat *pstat; + uint32_t diglen = crypto_ahash_digestsize(ahash); + uint32_t *auth32 = (uint32_t *)authdata; + struct crypto_engine *pengine; + struct qcrypto_req_control *pqcrypto_req_control; + + async_req = &areq->base; + pstat = &_qcrypto_stat; + + pengine = rctx->pengine; + pqcrypto_req_control = find_req_control_for_areq(pengine, + async_req); + if (pqcrypto_req_control == NULL) { + pr_err("async request not found\n"); + return; + } + +#ifdef QCRYPTO_DEBUG + dev_info(&pengine->pdev->dev, "_qce_ahash_complete: %pK ret %d\n", + areq, ret); +#endif + if (digest) { + memcpy(rctx->digest, digest, diglen); + if (rctx->last_blk) + memcpy(areq->result, digest, diglen); + } + if (authdata) { + rctx->byte_count[0] = auth32[0]; + rctx->byte_count[1] = auth32[1]; + rctx->byte_count[2] = auth32[2]; + rctx->byte_count[3] = auth32[3]; + } + areq->src = rctx->src; + areq->nbytes = rctx->nbytes; + + rctx->last_blk = 0; + rctx->first_blk = 0; + + if (ret) { + pqcrypto_req_control->res = -ENXIO; + pstat->ahash_op_fail++; + } else { + pqcrypto_req_control->res = 0; + pstat->ahash_op_success++; + } + if (cp->ce_support.aligned_only) { + areq->src = rctx->orig_src; + kfree(rctx->data); + } + req_done(pqcrypto_req_control); +}; + +static void _qce_ablk_cipher_complete(void *cookie, unsigned char *icb, + unsigned char *iv, int ret) +{ + struct ablkcipher_request *areq = (struct ablkcipher_request *) cookie; + struct crypto_async_request *async_req; + struct crypto_ablkcipher *ablk = crypto_ablkcipher_reqtfm(areq); + struct qcrypto_cipher_ctx *ctx = crypto_tfm_ctx(areq->base.tfm); + struct crypto_priv *cp = ctx->cp; + struct crypto_stat *pstat; + struct qcrypto_cipher_req_ctx *rctx; + struct crypto_engine *pengine; + struct qcrypto_req_control *pqcrypto_req_control; + + async_req = &areq->base; + pstat = &_qcrypto_stat; + rctx = ablkcipher_request_ctx(areq); + pengine = rctx->pengine; + pqcrypto_req_control = find_req_control_for_areq(pengine, + async_req); + if (pqcrypto_req_control == NULL) { + pr_err("async request not found\n"); + return; + } + +#ifdef QCRYPTO_DEBUG + dev_info(&pengine->pdev->dev, "_qce_ablk_cipher_complete: %pK ret %d\n", + areq, ret); +#endif + if (iv) + memcpy(ctx->iv, iv, crypto_ablkcipher_ivsize(ablk)); + + if (ret) { + pqcrypto_req_control->res = -ENXIO; + pstat->ablk_cipher_op_fail++; + } else { + pqcrypto_req_control->res = 0; + pstat->ablk_cipher_op_success++; + } + + if (cp->ce_support.aligned_only) { + struct qcrypto_cipher_req_ctx *rctx; + uint32_t num_sg = 0; + uint32_t bytes = 0; + + rctx = ablkcipher_request_ctx(areq); + areq->src = rctx->orig_src; + areq->dst = rctx->orig_dst; + + num_sg = qcrypto_count_sg(areq->dst, areq->nbytes); + bytes = qcrypto_sg_copy_from_buffer(areq->dst, num_sg, + rctx->data, areq->nbytes); + if (bytes != areq->nbytes) + pr_warn("bytes copied=0x%x bytes to copy= 0x%x", bytes, + areq->nbytes); + kzfree(rctx->data); + } + req_done(pqcrypto_req_control); +}; + +static void _qce_aead_complete(void *cookie, unsigned char *icv, + unsigned char *iv, int ret) +{ + struct aead_request *areq = (struct aead_request *) cookie; + struct crypto_async_request *async_req; + struct crypto_aead *aead = crypto_aead_reqtfm(areq); + struct qcrypto_cipher_ctx *ctx = crypto_tfm_ctx(areq->base.tfm); + struct qcrypto_cipher_req_ctx *rctx; + struct crypto_stat *pstat; + struct crypto_engine *pengine; + struct qcrypto_req_control *pqcrypto_req_control; + + async_req = &areq->base; + pstat = &_qcrypto_stat; + rctx = aead_request_ctx(areq); + pengine = rctx->pengine; + pqcrypto_req_control = find_req_control_for_areq(pengine, + async_req); + if (pqcrypto_req_control == NULL) { + pr_err("async request not found\n"); + return; + } + + if (rctx->mode == QCE_MODE_CCM) { + kzfree(rctx->adata); + } else { + uint32_t ivsize = crypto_aead_ivsize(aead); + + if (ret == 0) { + if (rctx->dir == QCE_ENCRYPT) { + /* copy the icv to dst */ + scatterwalk_map_and_copy(icv, areq->dst, + areq->cryptlen + areq->assoclen, + ctx->authsize, 1); + + } else { + unsigned char tmp[SHA256_DIGESTSIZE] = {0}; + + /* compare icv from src */ + scatterwalk_map_and_copy(tmp, + areq->src, areq->assoclen + + areq->cryptlen - ctx->authsize, + ctx->authsize, 0); + ret = memcmp(icv, tmp, ctx->authsize); + if (ret != 0) + ret = -EBADMSG; + + } + } else { + ret = -ENXIO; + } + + if (iv) + memcpy(ctx->iv, iv, ivsize); + } + + if (ret == (-EBADMSG)) + pstat->aead_bad_msg++; + else if (ret) + pstat->aead_op_fail++; + else + pstat->aead_op_success++; + + pqcrypto_req_control->res = ret; + req_done(pqcrypto_req_control); +} + +static int aead_ccm_set_msg_len(u8 *block, unsigned int msglen, int csize) +{ + __be32 data; + + memset(block, 0, csize); + block += csize; + + if (csize >= 4) + csize = 4; + else if (msglen > (1 << (8 * csize))) + return -EOVERFLOW; + + data = cpu_to_be32(msglen); + memcpy(block - csize, (u8 *)&data + 4 - csize, csize); + + return 0; +} + +static int qccrypto_set_aead_ccm_nonce(struct qce_req *qreq, uint32_t assoclen) +{ + unsigned int i = ((unsigned int)qreq->iv[0]) + 1; + + memcpy(&qreq->nonce[0] , qreq->iv, qreq->ivsize); + /* + * Format control info per RFC 3610 and + * NIST Special Publication 800-38C + */ + qreq->nonce[0] |= (8 * ((qreq->authsize - 2) / 2)); + if (assoclen) + qreq->nonce[0] |= 64; + + if (i > MAX_NONCE) + return -EINVAL; + + return aead_ccm_set_msg_len(qreq->nonce + 16 - i, qreq->cryptlen, i); +} + +static int qcrypto_aead_ccm_format_adata(struct qce_req *qreq, uint32_t alen, + struct scatterlist *sg, unsigned char *adata) +{ + uint32_t len; + uint32_t bytes = 0; + uint32_t num_sg = 0; + + /* + * Add control info for associated data + * RFC 3610 and NIST Special Publication 800-38C + */ + if (alen < 65280) { + *(__be16 *)adata = cpu_to_be16(alen); + len = 2; + } else { + if ((alen >= 65280) && (alen <= 0xffffffff)) { + *(__be16 *)adata = cpu_to_be16(0xfffe); + *(__be32 *)&adata[2] = cpu_to_be32(alen); + len = 6; + } else { + *(__be16 *)adata = cpu_to_be16(0xffff); + *(__be32 *)&adata[6] = cpu_to_be32(alen); + len = 10; + } + } + adata += len; + qreq->assoclen = ALIGN((alen + len), 16); + + num_sg = qcrypto_count_sg(sg, alen); + bytes = qcrypto_sg_copy_to_buffer(sg, num_sg, adata, alen); + if (bytes != alen) + pr_warn("bytes copied=0x%x bytes to copy= 0x%x", bytes, alen); + + return 0; +} + +static int _qcrypto_process_ablkcipher(struct crypto_engine *pengine, + struct qcrypto_req_control *pqcrypto_req_control) +{ + struct crypto_async_request *async_req; + struct qce_req qreq; + int ret; + struct qcrypto_cipher_req_ctx *rctx; + struct qcrypto_cipher_ctx *cipher_ctx; + struct ablkcipher_request *req; + struct crypto_ablkcipher *tfm; + + async_req = pqcrypto_req_control->req; + req = container_of(async_req, struct ablkcipher_request, base); + cipher_ctx = crypto_tfm_ctx(async_req->tfm); + rctx = ablkcipher_request_ctx(req); + rctx->pengine = pengine; + tfm = crypto_ablkcipher_reqtfm(req); + if (pengine->pcp->ce_support.aligned_only) { + uint32_t bytes = 0; + uint32_t num_sg = 0; + + rctx->orig_src = req->src; + rctx->orig_dst = req->dst; + rctx->data = kzalloc((req->nbytes + 64), GFP_ATOMIC); + + if (rctx->data == NULL) { + pr_err("Mem Alloc fail rctx->data, err %ld for 0x%x\n", + PTR_ERR(rctx->data), (req->nbytes + 64)); + return -ENOMEM; + } + num_sg = qcrypto_count_sg(req->src, req->nbytes); + bytes = qcrypto_sg_copy_to_buffer(req->src, num_sg, rctx->data, + req->nbytes); + if (bytes != req->nbytes) + pr_warn("bytes copied=0x%x bytes to copy= 0x%x", bytes, + req->nbytes); + sg_set_buf(&rctx->dsg, rctx->data, req->nbytes); + sg_mark_end(&rctx->dsg); + rctx->iv = req->info; + + req->src = &rctx->dsg; + req->dst = &rctx->dsg; + } + qreq.op = QCE_REQ_ABLK_CIPHER; + qreq.qce_cb = _qce_ablk_cipher_complete; + qreq.areq = req; + qreq.alg = rctx->alg; + qreq.dir = rctx->dir; + qreq.mode = rctx->mode; + qreq.enckey = cipher_ctx->enc_key; + qreq.encklen = cipher_ctx->enc_key_len; + qreq.iv = req->info; + qreq.ivsize = crypto_ablkcipher_ivsize(tfm); + qreq.cryptlen = req->nbytes; + qreq.use_pmem = 0; + qreq.flags = cipher_ctx->flags; + + if ((cipher_ctx->enc_key_len == 0) && + (pengine->pcp->platform_support.hw_key_support == 0)) + ret = -EINVAL; + else + ret = qce_ablk_cipher_req(pengine->qce, &qreq); + + return ret; +} + +static int _qcrypto_process_ahash(struct crypto_engine *pengine, + struct qcrypto_req_control *pqcrypto_req_control) +{ + struct crypto_async_request *async_req; + struct ahash_request *req; + struct qce_sha_req sreq; + struct qcrypto_sha_req_ctx *rctx; + struct qcrypto_sha_ctx *sha_ctx; + int ret = 0; + + async_req = pqcrypto_req_control->req; + req = container_of(async_req, + struct ahash_request, base); + rctx = ahash_request_ctx(req); + sha_ctx = crypto_tfm_ctx(async_req->tfm); + rctx->pengine = pengine; + + sreq.qce_cb = _qce_ahash_complete; + sreq.digest = &rctx->digest[0]; + sreq.src = req->src; + sreq.auth_data[0] = rctx->byte_count[0]; + sreq.auth_data[1] = rctx->byte_count[1]; + sreq.auth_data[2] = rctx->byte_count[2]; + sreq.auth_data[3] = rctx->byte_count[3]; + sreq.first_blk = rctx->first_blk; + sreq.last_blk = rctx->last_blk; + sreq.size = req->nbytes; + sreq.areq = req; + sreq.flags = sha_ctx->flags; + + switch (sha_ctx->alg) { + case QCE_HASH_SHA1: + sreq.alg = QCE_HASH_SHA1; + sreq.authkey = NULL; + break; + case QCE_HASH_SHA256: + sreq.alg = QCE_HASH_SHA256; + sreq.authkey = NULL; + break; + case QCE_HASH_SHA1_HMAC: + sreq.alg = QCE_HASH_SHA1_HMAC; + sreq.authkey = &sha_ctx->authkey[0]; + sreq.authklen = SHA_HMAC_KEY_SIZE; + break; + case QCE_HASH_SHA256_HMAC: + sreq.alg = QCE_HASH_SHA256_HMAC; + sreq.authkey = &sha_ctx->authkey[0]; + sreq.authklen = SHA_HMAC_KEY_SIZE; + break; + default: + pr_err("Algorithm %d not supported, exiting", sha_ctx->alg); + ret = -1; + break; + }; + ret = qce_process_sha_req(pengine->qce, &sreq); + + return ret; +} + +static int _qcrypto_process_aead(struct crypto_engine *pengine, + struct qcrypto_req_control *pqcrypto_req_control) +{ + struct crypto_async_request *async_req; + struct qce_req qreq; + int ret = 0; + struct qcrypto_cipher_req_ctx *rctx; + struct qcrypto_cipher_ctx *cipher_ctx; + struct aead_request *req; + struct crypto_aead *aead; + + async_req = pqcrypto_req_control->req; + req = container_of(async_req, struct aead_request, base); + aead = crypto_aead_reqtfm(req); + rctx = aead_request_ctx(req); + rctx->pengine = pengine; + cipher_ctx = crypto_tfm_ctx(async_req->tfm); + + qreq.op = QCE_REQ_AEAD; + qreq.qce_cb = _qce_aead_complete; + + qreq.areq = req; + qreq.alg = rctx->alg; + qreq.dir = rctx->dir; + qreq.mode = rctx->mode; + qreq.iv = rctx->iv; + + qreq.enckey = cipher_ctx->enc_key; + qreq.encklen = cipher_ctx->enc_key_len; + qreq.authkey = cipher_ctx->auth_key; + qreq.authklen = cipher_ctx->auth_key_len; + qreq.authsize = crypto_aead_authsize(aead); + qreq.auth_alg = cipher_ctx->auth_alg; + if (qreq.mode == QCE_MODE_CCM) + qreq.ivsize = AES_BLOCK_SIZE; + else + qreq.ivsize = crypto_aead_ivsize(aead); + qreq.flags = cipher_ctx->flags; + + if (qreq.mode == QCE_MODE_CCM) { + uint32_t assoclen; + + if (qreq.dir == QCE_ENCRYPT) + qreq.cryptlen = req->cryptlen; + else + qreq.cryptlen = req->cryptlen - + qreq.authsize; + + /* if rfc4309 ccm, adjust assoclen */ + assoclen = req->assoclen; + if (rctx->ccmtype) + assoclen -= 8; + /* Get NONCE */ + ret = qccrypto_set_aead_ccm_nonce(&qreq, assoclen); + if (ret) + return ret; + + if (assoclen) { + rctx->adata = kzalloc((assoclen + 0x64), + GFP_ATOMIC); + if (!rctx->adata) + return -ENOMEM; + /* Format Associated data */ + ret = qcrypto_aead_ccm_format_adata(&qreq, + assoclen, + req->src, + rctx->adata); + } else { + qreq.assoclen = 0; + rctx->adata = NULL; + } + if (ret) { + kzfree(rctx->adata); + return ret; + } + + /* + * update req with new formatted associated + * data info + */ + qreq.asg = &rctx->asg; + if (rctx->adata) + sg_set_buf(qreq.asg, rctx->adata, + qreq.assoclen); + sg_mark_end(qreq.asg); + } + ret = qce_aead_req(pengine->qce, &qreq); + + return ret; +} + +static struct crypto_engine *_qcrypto_static_assign_engine( + struct crypto_priv *cp) +{ + struct crypto_engine *pengine; + unsigned long flags; + + spin_lock_irqsave(&cp->lock, flags); + if (cp->next_engine) + pengine = cp->next_engine; + else + pengine = list_first_entry(&cp->engine_list, + struct crypto_engine, elist); + + if (list_is_last(&pengine->elist, &cp->engine_list)) + cp->next_engine = list_first_entry( + &cp->engine_list, struct crypto_engine, elist); + else + cp->next_engine = list_next_entry(pengine, elist); + spin_unlock_irqrestore(&cp->lock, flags); + return pengine; +} + +static int _start_qcrypto_process(struct crypto_priv *cp, + struct crypto_engine *pengine) +{ + struct crypto_async_request *async_req = NULL; + struct crypto_async_request *backlog_eng = NULL; + struct crypto_async_request *backlog_cp = NULL; + unsigned long flags; + u32 type; + int ret = 0; + struct crypto_stat *pstat; + void *tfm_ctx; + struct qcrypto_cipher_req_ctx *cipher_rctx; + struct qcrypto_sha_req_ctx *ahash_rctx; + struct ablkcipher_request *ablkcipher_req; + struct ahash_request *ahash_req; + struct aead_request *aead_req; + struct qcrypto_resp_ctx *arsp; + struct qcrypto_req_control *pqcrypto_req_control; + unsigned int cpu = MAX_SMP_CPU; + + if (ACCESS_ONCE(cp->ce_req_proc_sts) == STOPPED) + return 0; + + if (in_interrupt()) { + cpu = smp_processor_id(); + if (cpu >= MAX_SMP_CPU) + cpu = MAX_SMP_CPU - 1; + } else + cpu = MAX_SMP_CPU; + + pstat = &_qcrypto_stat; + +again: + spin_lock_irqsave(&cp->lock, flags); + if (pengine->issue_req || + atomic_read(&pengine->req_count) >= (pengine->max_req)) { + spin_unlock_irqrestore(&cp->lock, flags); + return 0; + } + + backlog_eng = crypto_get_backlog(&pengine->req_queue); + + /* make sure it is in high bandwidth state */ + if (pengine->bw_state != BUS_HAS_BANDWIDTH) { + spin_unlock_irqrestore(&cp->lock, flags); + return 0; + } + + /* try to get request from request queue of the engine first */ + async_req = crypto_dequeue_request(&pengine->req_queue); + if (!async_req) { + /* + * if no request from the engine, + * try to get from request queue of driver + */ + backlog_cp = crypto_get_backlog(&cp->req_queue); + async_req = crypto_dequeue_request(&cp->req_queue); + if (!async_req) { + spin_unlock_irqrestore(&cp->lock, flags); + return 0; + } + } + pqcrypto_req_control = qcrypto_alloc_req_control(pengine); + if (pqcrypto_req_control == NULL) { + pr_err("Allocation of request failed\n"); + spin_unlock_irqrestore(&cp->lock, flags); + return 0; + } + + /* add associated rsp entry to tfm response queue */ + type = crypto_tfm_alg_type(async_req->tfm); + tfm_ctx = crypto_tfm_ctx(async_req->tfm); + switch (type) { + case CRYPTO_ALG_TYPE_AHASH: + ahash_req = container_of(async_req, + struct ahash_request, base); + ahash_rctx = ahash_request_ctx(ahash_req); + arsp = &ahash_rctx->rsp_entry; + list_add_tail( + &arsp->list, + &((struct qcrypto_sha_ctx *)tfm_ctx) + ->rsp_queue); + break; + case CRYPTO_ALG_TYPE_ABLKCIPHER: + ablkcipher_req = container_of(async_req, + struct ablkcipher_request, base); + cipher_rctx = ablkcipher_request_ctx(ablkcipher_req); + arsp = &cipher_rctx->rsp_entry; + list_add_tail( + &arsp->list, + &((struct qcrypto_cipher_ctx *)tfm_ctx) + ->rsp_queue); + break; + case CRYPTO_ALG_TYPE_AEAD: + default: + aead_req = container_of(async_req, + struct aead_request, base); + cipher_rctx = aead_request_ctx(aead_req); + arsp = &cipher_rctx->rsp_entry; + list_add_tail( + &arsp->list, + &((struct qcrypto_cipher_ctx *)tfm_ctx) + ->rsp_queue); + break; + } + + arsp->res = -EINPROGRESS; + arsp->async_req = async_req; + pqcrypto_req_control->pce = pengine; + pqcrypto_req_control->req = async_req; + pqcrypto_req_control->arsp = arsp; + pengine->active_seq++; + pengine->check_flag = true; + + pengine->issue_req = true; + cp->cpu_req[cpu]++; + smp_mb(); /* make it visible */ + + spin_unlock_irqrestore(&cp->lock, flags); + if (backlog_eng) + backlog_eng->complete(backlog_eng, -EINPROGRESS); + if (backlog_cp) + backlog_cp->complete(backlog_cp, -EINPROGRESS); + switch (type) { + case CRYPTO_ALG_TYPE_ABLKCIPHER: + ret = _qcrypto_process_ablkcipher(pengine, + pqcrypto_req_control); + break; + case CRYPTO_ALG_TYPE_AHASH: + ret = _qcrypto_process_ahash(pengine, pqcrypto_req_control); + break; + case CRYPTO_ALG_TYPE_AEAD: + ret = _qcrypto_process_aead(pengine, pqcrypto_req_control); + break; + default: + ret = -EINVAL; + }; + + pengine->issue_req = false; + smp_mb(); /* make it visible */ + + pengine->total_req++; + if (ret) { + pengine->err_req++; + qcrypto_free_req_control(pengine, pqcrypto_req_control); + + if (type == CRYPTO_ALG_TYPE_ABLKCIPHER) + pstat->ablk_cipher_op_fail++; + else + if (type == CRYPTO_ALG_TYPE_AHASH) + pstat->ahash_op_fail++; + else + pstat->aead_op_fail++; + + _qcrypto_tfm_complete(pengine, type, tfm_ctx, arsp, ret); + goto again; + }; + return ret; +} + +static inline struct crypto_engine *_next_eng(struct crypto_priv *cp, + struct crypto_engine *p) +{ + + if (p == NULL || list_is_last(&p->elist, &cp->engine_list)) + p = list_first_entry(&cp->engine_list, struct crypto_engine, + elist); + else + p = list_entry(p->elist.next, struct crypto_engine, elist); + return p; +} +static struct crypto_engine *_avail_eng(struct crypto_priv *cp) +{ + /* call this function with spinlock set */ + struct crypto_engine *q = NULL; + struct crypto_engine *p = cp->scheduled_eng; + struct crypto_engine *q1; + int eng_cnt = cp->total_units; + + if (unlikely(list_empty(&cp->engine_list))) { + pr_err("%s: no valid ce to schedule\n", __func__); + return NULL; + } + + p = _next_eng(cp, p); + q1 = p; + while (eng_cnt-- > 0) { + if (!p->issue_req && atomic_read(&p->req_count) < p->max_req) { + q = p; + break; + } + p = _next_eng(cp, p); + if (q1 == p) + break; + } + cp->scheduled_eng = q; + return q; +} + +static int _qcrypto_queue_req(struct crypto_priv *cp, + struct crypto_engine *pengine, + struct crypto_async_request *req) +{ + int ret; + unsigned long flags; + + spin_lock_irqsave(&cp->lock, flags); + + if (pengine) { + ret = crypto_enqueue_request(&pengine->req_queue, req); + } else { + ret = crypto_enqueue_request(&cp->req_queue, req); + pengine = _avail_eng(cp); + if (cp->req_queue.qlen > cp->max_qlen) + cp->max_qlen = cp->req_queue.qlen; + } + if (pengine) { + switch (pengine->bw_state) { + case BUS_NO_BANDWIDTH: + if (pengine->high_bw_req == false) { + qcrypto_ce_bw_allocate_req(pengine); + pengine->high_bw_req = true; + } + pengine = NULL; + break; + case BUS_HAS_BANDWIDTH: + break; + case BUS_BANDWIDTH_RELEASING: + pengine->high_bw_req = true; + pengine = NULL; + break; + case BUS_BANDWIDTH_ALLOCATING: + pengine = NULL; + break; + case BUS_SUSPENDED: + case BUS_SUSPENDING: + default: + pengine = NULL; + break; + } + } else { + cp->no_avail++; + } + spin_unlock_irqrestore(&cp->lock, flags); + if (pengine && (ACCESS_ONCE(cp->ce_req_proc_sts) == IN_PROGRESS)) + _start_qcrypto_process(cp, pengine); + return ret; +} + +static int _qcrypto_enc_aes_192_fallback(struct ablkcipher_request *req) +{ + struct crypto_tfm *tfm = + crypto_ablkcipher_tfm(crypto_ablkcipher_reqtfm(req)); + struct qcrypto_cipher_ctx *ctx = crypto_tfm_ctx(req->base.tfm); + int err; + + ablkcipher_request_set_tfm(req, ctx->cipher_aes192_fb); + err = crypto_ablkcipher_encrypt(req); + ablkcipher_request_set_tfm(req, __crypto_ablkcipher_cast(tfm)); + return err; +} + +static int _qcrypto_dec_aes_192_fallback(struct ablkcipher_request *req) +{ + struct crypto_tfm *tfm = + crypto_ablkcipher_tfm(crypto_ablkcipher_reqtfm(req)); + struct qcrypto_cipher_ctx *ctx = crypto_tfm_ctx(req->base.tfm); + int err; + + ablkcipher_request_set_tfm(req, ctx->cipher_aes192_fb); + err = crypto_ablkcipher_decrypt(req); + ablkcipher_request_set_tfm(req, __crypto_ablkcipher_cast(tfm)); + return err; +} + + +static int _qcrypto_enc_aes_ecb(struct ablkcipher_request *req) +{ + struct qcrypto_cipher_req_ctx *rctx; + struct qcrypto_cipher_ctx *ctx = crypto_tfm_ctx(req->base.tfm); + struct crypto_priv *cp = ctx->cp; + struct crypto_stat *pstat; + + pstat = &_qcrypto_stat; + + BUG_ON(crypto_tfm_alg_type(req->base.tfm) != + CRYPTO_ALG_TYPE_ABLKCIPHER); +#ifdef QCRYPTO_DEBUG + dev_info(&ctx->pengine->pdev->dev, "_qcrypto_enc_aes_ecb: %pK\n", req); +#endif + + if ((ctx->enc_key_len == AES_KEYSIZE_192) && + (!cp->ce_support.aes_key_192) && + ctx->cipher_aes192_fb) + return _qcrypto_enc_aes_192_fallback(req); + + rctx = ablkcipher_request_ctx(req); + rctx->aead = 0; + rctx->alg = CIPHER_ALG_AES; + rctx->dir = QCE_ENCRYPT; + rctx->mode = QCE_MODE_ECB; + + pstat->ablk_cipher_aes_enc++; + return _qcrypto_queue_req(cp, ctx->pengine, &req->base); +}; + +static int _qcrypto_enc_aes_cbc(struct ablkcipher_request *req) +{ + struct qcrypto_cipher_req_ctx *rctx; + struct qcrypto_cipher_ctx *ctx = crypto_tfm_ctx(req->base.tfm); + struct crypto_priv *cp = ctx->cp; + struct crypto_stat *pstat; + + pstat = &_qcrypto_stat; + + BUG_ON(crypto_tfm_alg_type(req->base.tfm) != + CRYPTO_ALG_TYPE_ABLKCIPHER); +#ifdef QCRYPTO_DEBUG + dev_info(&ctx->pengine->pdev->dev, "_qcrypto_enc_aes_cbc: %pK\n", req); +#endif + + if ((ctx->enc_key_len == AES_KEYSIZE_192) && + (!cp->ce_support.aes_key_192) && + ctx->cipher_aes192_fb) + return _qcrypto_enc_aes_192_fallback(req); + + rctx = ablkcipher_request_ctx(req); + rctx->aead = 0; + rctx->alg = CIPHER_ALG_AES; + rctx->dir = QCE_ENCRYPT; + rctx->mode = QCE_MODE_CBC; + + pstat->ablk_cipher_aes_enc++; + return _qcrypto_queue_req(cp, ctx->pengine, &req->base); +}; + +static int _qcrypto_enc_aes_ctr(struct ablkcipher_request *req) +{ + struct qcrypto_cipher_req_ctx *rctx; + struct qcrypto_cipher_ctx *ctx = crypto_tfm_ctx(req->base.tfm); + struct crypto_priv *cp = ctx->cp; + struct crypto_stat *pstat; + + pstat = &_qcrypto_stat; + + BUG_ON(crypto_tfm_alg_type(req->base.tfm) != + CRYPTO_ALG_TYPE_ABLKCIPHER); +#ifdef QCRYPTO_DEBUG + dev_info(&ctx->pengine->pdev->dev, "_qcrypto_enc_aes_ctr: %pK\n", req); +#endif + + if ((ctx->enc_key_len == AES_KEYSIZE_192) && + (!cp->ce_support.aes_key_192) && + ctx->cipher_aes192_fb) + return _qcrypto_enc_aes_192_fallback(req); + + rctx = ablkcipher_request_ctx(req); + rctx->aead = 0; + rctx->alg = CIPHER_ALG_AES; + rctx->dir = QCE_ENCRYPT; + rctx->mode = QCE_MODE_CTR; + + pstat->ablk_cipher_aes_enc++; + return _qcrypto_queue_req(cp, ctx->pengine, &req->base); +}; + +static int _qcrypto_enc_aes_xts(struct ablkcipher_request *req) +{ + struct qcrypto_cipher_req_ctx *rctx; + struct qcrypto_cipher_ctx *ctx = crypto_tfm_ctx(req->base.tfm); + struct crypto_priv *cp = ctx->cp; + struct crypto_stat *pstat; + + pstat = &_qcrypto_stat; + + BUG_ON(crypto_tfm_alg_type(req->base.tfm) != + CRYPTO_ALG_TYPE_ABLKCIPHER); + rctx = ablkcipher_request_ctx(req); + rctx->aead = 0; + rctx->alg = CIPHER_ALG_AES; + rctx->dir = QCE_ENCRYPT; + rctx->mode = QCE_MODE_XTS; + + pstat->ablk_cipher_aes_enc++; + return _qcrypto_queue_req(cp, ctx->pengine, &req->base); +}; + +static int _qcrypto_aead_encrypt_aes_ccm(struct aead_request *req) +{ + struct qcrypto_cipher_req_ctx *rctx; + struct qcrypto_cipher_ctx *ctx = crypto_tfm_ctx(req->base.tfm); + struct crypto_priv *cp = ctx->cp; + struct crypto_stat *pstat; + + if ((ctx->authsize > 16) || (ctx->authsize < 4) || (ctx->authsize & 1)) + return -EINVAL; + if ((ctx->auth_key_len != AES_KEYSIZE_128) && + (ctx->auth_key_len != AES_KEYSIZE_256)) + return -EINVAL; + + pstat = &_qcrypto_stat; + + rctx = aead_request_ctx(req); + rctx->aead = 1; + rctx->alg = CIPHER_ALG_AES; + rctx->dir = QCE_ENCRYPT; + rctx->mode = QCE_MODE_CCM; + rctx->iv = req->iv; + rctx->ccmtype = 0; + + pstat->aead_ccm_aes_enc++; + return _qcrypto_queue_req(cp, ctx->pengine, &req->base); +} + +static int _qcrypto_aead_rfc4309_enc_aes_ccm(struct aead_request *req) +{ + struct qcrypto_cipher_req_ctx *rctx; + struct qcrypto_cipher_ctx *ctx = crypto_tfm_ctx(req->base.tfm); + struct crypto_priv *cp = ctx->cp; + struct crypto_stat *pstat; + + pstat = &_qcrypto_stat; + + if (req->assoclen != 16 && req->assoclen != 20) + return -EINVAL; + rctx = aead_request_ctx(req); + rctx->aead = 1; + rctx->alg = CIPHER_ALG_AES; + rctx->dir = QCE_ENCRYPT; + rctx->mode = QCE_MODE_CCM; + memset(rctx->rfc4309_iv, 0, sizeof(rctx->rfc4309_iv)); + rctx->rfc4309_iv[0] = 3; /* L -1 */ + memcpy(&rctx->rfc4309_iv[1], ctx->ccm4309_nonce, 3); + memcpy(&rctx->rfc4309_iv[4], req->iv, 8); + rctx->ccmtype = 1; + rctx->iv = rctx->rfc4309_iv; + pstat->aead_rfc4309_ccm_aes_enc++; + return _qcrypto_queue_req(cp, ctx->pengine, &req->base); +} + +static int _qcrypto_enc_des_ecb(struct ablkcipher_request *req) +{ + struct qcrypto_cipher_req_ctx *rctx; + struct qcrypto_cipher_ctx *ctx = crypto_tfm_ctx(req->base.tfm); + struct crypto_priv *cp = ctx->cp; + struct crypto_stat *pstat; + + pstat = &_qcrypto_stat; + + BUG_ON(crypto_tfm_alg_type(req->base.tfm) != + CRYPTO_ALG_TYPE_ABLKCIPHER); + rctx = ablkcipher_request_ctx(req); + rctx->aead = 0; + rctx->alg = CIPHER_ALG_DES; + rctx->dir = QCE_ENCRYPT; + rctx->mode = QCE_MODE_ECB; + + pstat->ablk_cipher_des_enc++; + return _qcrypto_queue_req(cp, ctx->pengine, &req->base); +}; + +static int _qcrypto_enc_des_cbc(struct ablkcipher_request *req) +{ + struct qcrypto_cipher_req_ctx *rctx; + struct qcrypto_cipher_ctx *ctx = crypto_tfm_ctx(req->base.tfm); + struct crypto_priv *cp = ctx->cp; + struct crypto_stat *pstat; + + pstat = &_qcrypto_stat; + + BUG_ON(crypto_tfm_alg_type(req->base.tfm) != + CRYPTO_ALG_TYPE_ABLKCIPHER); + rctx = ablkcipher_request_ctx(req); + rctx->aead = 0; + rctx->alg = CIPHER_ALG_DES; + rctx->dir = QCE_ENCRYPT; + rctx->mode = QCE_MODE_CBC; + + pstat->ablk_cipher_des_enc++; + return _qcrypto_queue_req(cp, ctx->pengine, &req->base); +}; + +static int _qcrypto_enc_3des_ecb(struct ablkcipher_request *req) +{ + struct qcrypto_cipher_req_ctx *rctx; + struct qcrypto_cipher_ctx *ctx = crypto_tfm_ctx(req->base.tfm); + struct crypto_priv *cp = ctx->cp; + struct crypto_stat *pstat; + + pstat = &_qcrypto_stat; + + BUG_ON(crypto_tfm_alg_type(req->base.tfm) != + CRYPTO_ALG_TYPE_ABLKCIPHER); + rctx = ablkcipher_request_ctx(req); + rctx->aead = 0; + rctx->alg = CIPHER_ALG_3DES; + rctx->dir = QCE_ENCRYPT; + rctx->mode = QCE_MODE_ECB; + + pstat->ablk_cipher_3des_enc++; + return _qcrypto_queue_req(cp, ctx->pengine, &req->base); +}; + +static int _qcrypto_enc_3des_cbc(struct ablkcipher_request *req) +{ + struct qcrypto_cipher_req_ctx *rctx; + struct qcrypto_cipher_ctx *ctx = crypto_tfm_ctx(req->base.tfm); + struct crypto_priv *cp = ctx->cp; + struct crypto_stat *pstat; + + pstat = &_qcrypto_stat; + + BUG_ON(crypto_tfm_alg_type(req->base.tfm) != + CRYPTO_ALG_TYPE_ABLKCIPHER); + rctx = ablkcipher_request_ctx(req); + rctx->aead = 0; + rctx->alg = CIPHER_ALG_3DES; + rctx->dir = QCE_ENCRYPT; + rctx->mode = QCE_MODE_CBC; + + pstat->ablk_cipher_3des_enc++; + return _qcrypto_queue_req(cp, ctx->pengine, &req->base); +}; + +static int _qcrypto_dec_aes_ecb(struct ablkcipher_request *req) +{ + struct qcrypto_cipher_req_ctx *rctx; + struct qcrypto_cipher_ctx *ctx = crypto_tfm_ctx(req->base.tfm); + struct crypto_priv *cp = ctx->cp; + struct crypto_stat *pstat; + + pstat = &_qcrypto_stat; + + BUG_ON(crypto_tfm_alg_type(req->base.tfm) != + CRYPTO_ALG_TYPE_ABLKCIPHER); +#ifdef QCRYPTO_DEBUG + dev_info(&ctx->pengine->pdev->dev, "_qcrypto_dec_aes_ecb: %pK\n", req); +#endif + + if ((ctx->enc_key_len == AES_KEYSIZE_192) && + (!cp->ce_support.aes_key_192) && + ctx->cipher_aes192_fb) + return _qcrypto_dec_aes_192_fallback(req); + + rctx = ablkcipher_request_ctx(req); + rctx->aead = 0; + rctx->alg = CIPHER_ALG_AES; + rctx->dir = QCE_DECRYPT; + rctx->mode = QCE_MODE_ECB; + + pstat->ablk_cipher_aes_dec++; + return _qcrypto_queue_req(cp, ctx->pengine, &req->base); +}; + +static int _qcrypto_dec_aes_cbc(struct ablkcipher_request *req) +{ + struct qcrypto_cipher_req_ctx *rctx; + struct qcrypto_cipher_ctx *ctx = crypto_tfm_ctx(req->base.tfm); + struct crypto_priv *cp = ctx->cp; + struct crypto_stat *pstat; + + pstat = &_qcrypto_stat; + + BUG_ON(crypto_tfm_alg_type(req->base.tfm) != + CRYPTO_ALG_TYPE_ABLKCIPHER); +#ifdef QCRYPTO_DEBUG + dev_info(&ctx->pengine->pdev->dev, "_qcrypto_dec_aes_cbc: %pK\n", req); +#endif + + if ((ctx->enc_key_len == AES_KEYSIZE_192) && + (!cp->ce_support.aes_key_192) && + ctx->cipher_aes192_fb) + return _qcrypto_dec_aes_192_fallback(req); + + rctx = ablkcipher_request_ctx(req); + rctx->aead = 0; + rctx->alg = CIPHER_ALG_AES; + rctx->dir = QCE_DECRYPT; + rctx->mode = QCE_MODE_CBC; + + pstat->ablk_cipher_aes_dec++; + return _qcrypto_queue_req(cp, ctx->pengine, &req->base); +}; + +static int _qcrypto_dec_aes_ctr(struct ablkcipher_request *req) +{ + struct qcrypto_cipher_req_ctx *rctx; + struct qcrypto_cipher_ctx *ctx = crypto_tfm_ctx(req->base.tfm); + struct crypto_priv *cp = ctx->cp; + struct crypto_stat *pstat; + + pstat = &_qcrypto_stat; + + BUG_ON(crypto_tfm_alg_type(req->base.tfm) != + CRYPTO_ALG_TYPE_ABLKCIPHER); +#ifdef QCRYPTO_DEBUG + dev_info(&ctx->pengine->pdev->dev, "_qcrypto_dec_aes_ctr: %pK\n", req); +#endif + + if ((ctx->enc_key_len == AES_KEYSIZE_192) && + (!cp->ce_support.aes_key_192) && + ctx->cipher_aes192_fb) + return _qcrypto_dec_aes_192_fallback(req); + + rctx = ablkcipher_request_ctx(req); + rctx->aead = 0; + rctx->alg = CIPHER_ALG_AES; + rctx->mode = QCE_MODE_CTR; + + /* Note. There is no such thing as aes/counter mode, decrypt */ + rctx->dir = QCE_ENCRYPT; + + pstat->ablk_cipher_aes_dec++; + return _qcrypto_queue_req(cp, ctx->pengine, &req->base); +}; + +static int _qcrypto_dec_des_ecb(struct ablkcipher_request *req) +{ + struct qcrypto_cipher_req_ctx *rctx; + struct qcrypto_cipher_ctx *ctx = crypto_tfm_ctx(req->base.tfm); + struct crypto_priv *cp = ctx->cp; + struct crypto_stat *pstat; + + pstat = &_qcrypto_stat; + + BUG_ON(crypto_tfm_alg_type(req->base.tfm) != + CRYPTO_ALG_TYPE_ABLKCIPHER); + rctx = ablkcipher_request_ctx(req); + rctx->aead = 0; + rctx->alg = CIPHER_ALG_DES; + rctx->dir = QCE_DECRYPT; + rctx->mode = QCE_MODE_ECB; + + pstat->ablk_cipher_des_dec++; + return _qcrypto_queue_req(cp, ctx->pengine, &req->base); +}; + +static int _qcrypto_dec_des_cbc(struct ablkcipher_request *req) +{ + struct qcrypto_cipher_req_ctx *rctx; + struct qcrypto_cipher_ctx *ctx = crypto_tfm_ctx(req->base.tfm); + struct crypto_priv *cp = ctx->cp; + struct crypto_stat *pstat; + + pstat = &_qcrypto_stat; + + BUG_ON(crypto_tfm_alg_type(req->base.tfm) != + CRYPTO_ALG_TYPE_ABLKCIPHER); + rctx = ablkcipher_request_ctx(req); + rctx->aead = 0; + rctx->alg = CIPHER_ALG_DES; + rctx->dir = QCE_DECRYPT; + rctx->mode = QCE_MODE_CBC; + + pstat->ablk_cipher_des_dec++; + return _qcrypto_queue_req(cp, ctx->pengine, &req->base); +}; + +static int _qcrypto_dec_3des_ecb(struct ablkcipher_request *req) +{ + struct qcrypto_cipher_req_ctx *rctx; + struct qcrypto_cipher_ctx *ctx = crypto_tfm_ctx(req->base.tfm); + struct crypto_priv *cp = ctx->cp; + struct crypto_stat *pstat; + + pstat = &_qcrypto_stat; + + BUG_ON(crypto_tfm_alg_type(req->base.tfm) != + CRYPTO_ALG_TYPE_ABLKCIPHER); + rctx = ablkcipher_request_ctx(req); + rctx->aead = 0; + rctx->alg = CIPHER_ALG_3DES; + rctx->dir = QCE_DECRYPT; + rctx->mode = QCE_MODE_ECB; + + pstat->ablk_cipher_3des_dec++; + return _qcrypto_queue_req(cp, ctx->pengine, &req->base); +}; + +static int _qcrypto_dec_3des_cbc(struct ablkcipher_request *req) +{ + struct qcrypto_cipher_req_ctx *rctx; + struct qcrypto_cipher_ctx *ctx = crypto_tfm_ctx(req->base.tfm); + struct crypto_priv *cp = ctx->cp; + struct crypto_stat *pstat; + + pstat = &_qcrypto_stat; + + BUG_ON(crypto_tfm_alg_type(req->base.tfm) != + CRYPTO_ALG_TYPE_ABLKCIPHER); + rctx = ablkcipher_request_ctx(req); + rctx->aead = 0; + rctx->alg = CIPHER_ALG_3DES; + rctx->dir = QCE_DECRYPT; + rctx->mode = QCE_MODE_CBC; + + pstat->ablk_cipher_3des_dec++; + return _qcrypto_queue_req(cp, ctx->pengine, &req->base); +}; + +static int _qcrypto_dec_aes_xts(struct ablkcipher_request *req) +{ + struct qcrypto_cipher_req_ctx *rctx; + struct qcrypto_cipher_ctx *ctx = crypto_tfm_ctx(req->base.tfm); + struct crypto_priv *cp = ctx->cp; + struct crypto_stat *pstat; + + pstat = &_qcrypto_stat; + + BUG_ON(crypto_tfm_alg_type(req->base.tfm) != + CRYPTO_ALG_TYPE_ABLKCIPHER); + rctx = ablkcipher_request_ctx(req); + rctx->aead = 0; + rctx->alg = CIPHER_ALG_AES; + rctx->mode = QCE_MODE_XTS; + rctx->dir = QCE_DECRYPT; + + pstat->ablk_cipher_aes_dec++; + return _qcrypto_queue_req(cp, ctx->pengine, &req->base); +}; + +static int _qcrypto_aead_decrypt_aes_ccm(struct aead_request *req) +{ + struct qcrypto_cipher_req_ctx *rctx; + struct qcrypto_cipher_ctx *ctx = crypto_tfm_ctx(req->base.tfm); + struct crypto_priv *cp = ctx->cp; + struct crypto_stat *pstat; + + if ((ctx->authsize > 16) || (ctx->authsize < 4) || (ctx->authsize & 1)) + return -EINVAL; + if ((ctx->auth_key_len != AES_KEYSIZE_128) && + (ctx->auth_key_len != AES_KEYSIZE_256)) + return -EINVAL; + + pstat = &_qcrypto_stat; + + rctx = aead_request_ctx(req); + rctx->aead = 1; + rctx->alg = CIPHER_ALG_AES; + rctx->dir = QCE_DECRYPT; + rctx->mode = QCE_MODE_CCM; + rctx->iv = req->iv; + rctx->ccmtype = 0; + + pstat->aead_ccm_aes_dec++; + return _qcrypto_queue_req(cp, ctx->pengine, &req->base); +} + +static int _qcrypto_aead_rfc4309_dec_aes_ccm(struct aead_request *req) +{ + struct qcrypto_cipher_req_ctx *rctx; + struct qcrypto_cipher_ctx *ctx = crypto_tfm_ctx(req->base.tfm); + struct crypto_priv *cp = ctx->cp; + struct crypto_stat *pstat; + + pstat = &_qcrypto_stat; + if (req->assoclen != 16 && req->assoclen != 20) + return -EINVAL; + rctx = aead_request_ctx(req); + rctx->aead = 1; + rctx->alg = CIPHER_ALG_AES; + rctx->dir = QCE_DECRYPT; + rctx->mode = QCE_MODE_CCM; + memset(rctx->rfc4309_iv, 0, sizeof(rctx->rfc4309_iv)); + rctx->rfc4309_iv[0] = 3; /* L -1 */ + memcpy(&rctx->rfc4309_iv[1], ctx->ccm4309_nonce, 3); + memcpy(&rctx->rfc4309_iv[4], req->iv, 8); + rctx->ccmtype = 1; + rctx->iv = rctx->rfc4309_iv; + pstat->aead_rfc4309_ccm_aes_dec++; + return _qcrypto_queue_req(cp, ctx->pengine, &req->base); +} + +static int _qcrypto_aead_setauthsize(struct crypto_aead *authenc, + unsigned int authsize) +{ + struct qcrypto_cipher_ctx *ctx = crypto_aead_ctx(authenc); + + ctx->authsize = authsize; + return 0; +} + +static int _qcrypto_aead_ccm_setauthsize(struct crypto_aead *authenc, + unsigned int authsize) +{ + struct qcrypto_cipher_ctx *ctx = crypto_aead_ctx(authenc); + + switch (authsize) { + case 4: + case 6: + case 8: + case 10: + case 12: + case 14: + case 16: + break; + default: + return -EINVAL; + } + ctx->authsize = authsize; + return 0; +} + +static int _qcrypto_aead_rfc4309_ccm_setauthsize(struct crypto_aead *authenc, + unsigned int authsize) +{ + struct qcrypto_cipher_ctx *ctx = crypto_aead_ctx(authenc); + + switch (authsize) { + case 8: + case 12: + case 16: + break; + default: + return -EINVAL; + } + ctx->authsize = authsize; + return 0; +} + +static int _qcrypto_aead_setkey(struct crypto_aead *tfm, const u8 *key, + unsigned int keylen) +{ + struct qcrypto_cipher_ctx *ctx = crypto_aead_ctx(tfm); + struct rtattr *rta = (struct rtattr *)key; + struct crypto_authenc_key_param *param; + int ret; + + if (!RTA_OK(rta, keylen)) + goto badkey; + if (rta->rta_type != CRYPTO_AUTHENC_KEYA_PARAM) + goto badkey; + if (RTA_PAYLOAD(rta) < sizeof(*param)) + goto badkey; + + param = RTA_DATA(rta); + ctx->enc_key_len = be32_to_cpu(param->enckeylen); + + key += RTA_ALIGN(rta->rta_len); + keylen -= RTA_ALIGN(rta->rta_len); + + if (keylen < ctx->enc_key_len) + goto badkey; + + ctx->auth_key_len = keylen - ctx->enc_key_len; + if (ctx->enc_key_len >= QCRYPTO_MAX_KEY_SIZE || + ctx->auth_key_len >= QCRYPTO_MAX_KEY_SIZE) + goto badkey; + memset(ctx->auth_key, 0, QCRYPTO_MAX_KEY_SIZE); + memcpy(ctx->enc_key, key + ctx->auth_key_len, ctx->enc_key_len); + memcpy(ctx->auth_key, key, ctx->auth_key_len); + + if (ctx->enc_key_len == AES_KEYSIZE_192 && ctx->cipher_aes192_fb && + ctx->ahash_aead_aes192_fb) { + crypto_ahash_clear_flags(ctx->ahash_aead_aes192_fb, ~0); + ret = crypto_ahash_setkey(ctx->ahash_aead_aes192_fb, + ctx->auth_key, ctx->auth_key_len); + if (ret) + goto badkey; + crypto_ablkcipher_clear_flags(ctx->cipher_aes192_fb, ~0); + ret = crypto_ablkcipher_setkey(ctx->cipher_aes192_fb, + ctx->enc_key, ctx->enc_key_len); + if (ret) + goto badkey; + } + + return 0; +badkey: + ctx->enc_key_len = 0; + crypto_aead_set_flags(tfm, CRYPTO_TFM_RES_BAD_KEY_LEN); + return -EINVAL; +} + +static int _qcrypto_aead_ccm_setkey(struct crypto_aead *aead, const u8 *key, + unsigned int keylen) +{ + struct crypto_tfm *tfm = crypto_aead_tfm(aead); + struct qcrypto_cipher_ctx *ctx = crypto_tfm_ctx(tfm); + struct crypto_priv *cp = ctx->cp; + + switch (keylen) { + case AES_KEYSIZE_128: + case AES_KEYSIZE_256: + break; + case AES_KEYSIZE_192: + if (cp->ce_support.aes_key_192) + break; + default: + ctx->enc_key_len = 0; + crypto_aead_set_flags(aead, CRYPTO_TFM_RES_BAD_KEY_LEN); + return -EINVAL; + }; + ctx->enc_key_len = keylen; + memcpy(ctx->enc_key, key, keylen); + ctx->auth_key_len = keylen; + memcpy(ctx->auth_key, key, keylen); + + return 0; +} + +static int _qcrypto_aead_rfc4309_ccm_setkey(struct crypto_aead *aead, + const u8 *key, unsigned int key_len) +{ + struct crypto_tfm *tfm = crypto_aead_tfm(aead); + struct qcrypto_cipher_ctx *ctx = crypto_tfm_ctx(tfm); + int ret; + + if (key_len < QCRYPTO_CCM4309_NONCE_LEN) + return -EINVAL; + key_len -= QCRYPTO_CCM4309_NONCE_LEN; + memcpy(ctx->ccm4309_nonce, key + key_len, QCRYPTO_CCM4309_NONCE_LEN); + ret = _qcrypto_aead_ccm_setkey(aead, key, key_len); + return ret; +}; + +static void _qcrypto_aead_aes_192_fb_a_cb(struct qcrypto_cipher_req_ctx *rctx, + int res) +{ + struct aead_request *req; + struct crypto_async_request *areq; + + req = rctx->aead_req; + areq = &req->base; + if (rctx->fb_aes_req) + ablkcipher_request_free(rctx->fb_aes_req); + if (rctx->fb_hash_req) + ahash_request_free(rctx->fb_hash_req); + rctx->fb_aes_req = NULL; + rctx->fb_hash_req = NULL; + kfree(rctx->fb_aes_iv); + areq->complete(areq, res); +} + +static void _aead_aes_fb_stage2_ahash_complete( + struct crypto_async_request *base, int err) +{ + struct qcrypto_cipher_req_ctx *rctx; + struct aead_request *req; + struct qcrypto_cipher_ctx *ctx; + + rctx = base->data; + req = rctx->aead_req; + ctx = crypto_tfm_ctx(req->base.tfm); + /* copy icv */ + if (err == 0) + scatterwalk_map_and_copy(rctx->fb_ahash_digest, + rctx->fb_aes_dst, + req->cryptlen, + ctx->authsize, 1); + _qcrypto_aead_aes_192_fb_a_cb(rctx, err); +} + + +static int _start_aead_aes_fb_stage2_hmac(struct qcrypto_cipher_req_ctx *rctx) +{ + struct ahash_request *ahash_req; + + ahash_req = rctx->fb_hash_req; + ahash_request_set_callback(ahash_req, CRYPTO_TFM_REQ_MAY_BACKLOG, + _aead_aes_fb_stage2_ahash_complete, rctx); + + return crypto_ahash_digest(ahash_req); +} + +static void _aead_aes_fb_stage2_decrypt_complete( + struct crypto_async_request *base, int err) +{ + struct qcrypto_cipher_req_ctx *rctx; + + rctx = base->data; + _qcrypto_aead_aes_192_fb_a_cb(rctx, err); +} + +static int _start_aead_aes_fb_stage2_decrypt( + struct qcrypto_cipher_req_ctx *rctx) +{ + struct ablkcipher_request *aes_req; + + aes_req = rctx->fb_aes_req; + ablkcipher_request_set_callback(aes_req, CRYPTO_TFM_REQ_MAY_BACKLOG, + _aead_aes_fb_stage2_decrypt_complete, rctx); + return crypto_ablkcipher_decrypt(aes_req); +} + +static void _aead_aes_fb_stage1_ahash_complete( + struct crypto_async_request *base, int err) +{ + struct qcrypto_cipher_req_ctx *rctx; + struct aead_request *req; + struct qcrypto_cipher_ctx *ctx; + + rctx = base->data; + req = rctx->aead_req; + ctx = crypto_tfm_ctx(req->base.tfm); + + /* compare icv */ + if (err == 0) { + unsigned char tmp[ctx->authsize]; + + scatterwalk_map_and_copy(tmp, rctx->fb_aes_src, + req->cryptlen - ctx->authsize, ctx->authsize, 0); + if (memcmp(rctx->fb_ahash_digest, tmp, ctx->authsize) != 0) + err = -EBADMSG; + } + if (err) + _qcrypto_aead_aes_192_fb_a_cb(rctx, err); + else { + err = _start_aead_aes_fb_stage2_decrypt(rctx); + if (err != -EINPROGRESS && err != -EBUSY) + _qcrypto_aead_aes_192_fb_a_cb(rctx, err); + } +} + +static void _aead_aes_fb_stage1_encrypt_complete( + struct crypto_async_request *base, int err) +{ + struct qcrypto_cipher_req_ctx *rctx; + struct aead_request *req; + struct qcrypto_cipher_ctx *ctx; + + rctx = base->data; + req = rctx->aead_req; + ctx = crypto_tfm_ctx(req->base.tfm); + + memcpy(ctx->iv, rctx->fb_aes_iv, rctx->ivsize); + + if (err) { + _qcrypto_aead_aes_192_fb_a_cb(rctx, err); + return; + } + + err = _start_aead_aes_fb_stage2_hmac(rctx); + + /* copy icv */ + if (err == 0) { + scatterwalk_map_and_copy(rctx->fb_ahash_digest, + rctx->fb_aes_dst, + req->cryptlen, + ctx->authsize, 1); + } + if (err != -EINPROGRESS && err != -EBUSY) + _qcrypto_aead_aes_192_fb_a_cb(rctx, err); +} + +static int _qcrypto_aead_aes_192_fallback(struct aead_request *req, + bool is_encrypt) +{ + int rc = -EINVAL; + struct qcrypto_cipher_req_ctx *rctx = aead_request_ctx(req); + struct qcrypto_cipher_ctx *ctx = crypto_tfm_ctx(req->base.tfm); + struct crypto_aead *aead_tfm = crypto_aead_reqtfm(req); + struct ablkcipher_request *aes_req = NULL; + struct ahash_request *ahash_req = NULL; + int nbytes; + struct scatterlist *src, *dst; + + rctx->fb_aes_iv = NULL; + aes_req = ablkcipher_request_alloc(ctx->cipher_aes192_fb, GFP_KERNEL); + if (!aes_req) + return -ENOMEM; + ahash_req = ahash_request_alloc(ctx->ahash_aead_aes192_fb, GFP_KERNEL); + if (!ahash_req) + goto ret; + rctx->fb_aes_req = aes_req; + rctx->fb_hash_req = ahash_req; + rctx->aead_req = req; + /* assoc and iv are sitting in the beginning of src sg list */ + /* Similarly, assoc and iv are sitting in the beginning of dst list */ + src = scatterwalk_ffwd(rctx->fb_ablkcipher_src_sg, req->src, + req->assoclen); + dst = scatterwalk_ffwd(rctx->fb_ablkcipher_dst_sg, req->dst, + req->assoclen); + + nbytes = req->cryptlen; + if (!is_encrypt) + nbytes -= ctx->authsize; + rctx->fb_ahash_length = nbytes + req->assoclen; + rctx->fb_aes_src = src; + rctx->fb_aes_dst = dst; + rctx->fb_aes_cryptlen = nbytes; + rctx->ivsize = crypto_aead_ivsize(aead_tfm); + rctx->fb_aes_iv = kzalloc(rctx->ivsize, GFP_ATOMIC); + if (!rctx->fb_aes_iv) + goto ret; + memcpy(rctx->fb_aes_iv, req->iv, rctx->ivsize); + ablkcipher_request_set_crypt(aes_req, rctx->fb_aes_src, + rctx->fb_aes_dst, + rctx->fb_aes_cryptlen, rctx->fb_aes_iv); + if (is_encrypt) + ahash_request_set_crypt(ahash_req, req->dst, + rctx->fb_ahash_digest, + rctx->fb_ahash_length); + else + ahash_request_set_crypt(ahash_req, req->src, + rctx->fb_ahash_digest, + rctx->fb_ahash_length); + + if (is_encrypt) { + + ablkcipher_request_set_callback(aes_req, + CRYPTO_TFM_REQ_MAY_BACKLOG, + _aead_aes_fb_stage1_encrypt_complete, rctx); + + rc = crypto_ablkcipher_encrypt(aes_req); + if (rc == 0) { + memcpy(ctx->iv, rctx->fb_aes_iv, rctx->ivsize); + rc = _start_aead_aes_fb_stage2_hmac(rctx); + if (rc == 0) { + /* copy icv */ + scatterwalk_map_and_copy(rctx->fb_ahash_digest, + dst, + req->cryptlen, + ctx->authsize, 1); + } + } + if (rc == -EINPROGRESS || rc == -EBUSY) + return rc; + goto ret; + + } else { + ahash_request_set_callback(ahash_req, + CRYPTO_TFM_REQ_MAY_BACKLOG, + _aead_aes_fb_stage1_ahash_complete, rctx); + + rc = crypto_ahash_digest(ahash_req); + if (rc == 0) { + unsigned char tmp[ctx->authsize]; + + /* compare icv */ + scatterwalk_map_and_copy(tmp, + src, req->cryptlen - ctx->authsize, + ctx->authsize, 0); + if (memcmp(rctx->fb_ahash_digest, tmp, + ctx->authsize) != 0) + rc = -EBADMSG; + else + rc = _start_aead_aes_fb_stage2_decrypt(rctx); + } + if (rc == -EINPROGRESS || rc == -EBUSY) + return rc; + goto ret; + } +ret: + if (aes_req) + ablkcipher_request_free(aes_req); + if (ahash_req) + ahash_request_free(ahash_req); + kfree(rctx->fb_aes_iv); + return rc; +} + +static int _qcrypto_aead_encrypt_aes_cbc(struct aead_request *req) +{ + struct qcrypto_cipher_req_ctx *rctx; + struct qcrypto_cipher_ctx *ctx = crypto_tfm_ctx(req->base.tfm); + struct crypto_priv *cp = ctx->cp; + struct crypto_stat *pstat; + + pstat = &_qcrypto_stat; + +#ifdef QCRYPTO_DEBUG + dev_info(&ctx->pengine->pdev->dev, + "_qcrypto_aead_encrypt_aes_cbc: %pK\n", req); +#endif + + rctx = aead_request_ctx(req); + rctx->aead = 1; + rctx->alg = CIPHER_ALG_AES; + rctx->dir = QCE_ENCRYPT; + rctx->mode = QCE_MODE_CBC; + rctx->iv = req->iv; + rctx->aead_req = req; + if (ctx->auth_alg == QCE_HASH_SHA1_HMAC) + pstat->aead_sha1_aes_enc++; + else + pstat->aead_sha256_aes_enc++; + if (ctx->enc_key_len == AES_KEYSIZE_192 && ctx->cipher_aes192_fb && + ctx->ahash_aead_aes192_fb) + return _qcrypto_aead_aes_192_fallback(req, true); + return _qcrypto_queue_req(cp, ctx->pengine, &req->base); +} + +static int _qcrypto_aead_decrypt_aes_cbc(struct aead_request *req) +{ + struct qcrypto_cipher_req_ctx *rctx; + struct qcrypto_cipher_ctx *ctx = crypto_tfm_ctx(req->base.tfm); + struct crypto_priv *cp = ctx->cp; + struct crypto_stat *pstat; + + pstat = &_qcrypto_stat; + +#ifdef QCRYPTO_DEBUG + dev_info(&ctx->pengine->pdev->dev, + "_qcrypto_aead_decrypt_aes_cbc: %pK\n", req); +#endif + rctx = aead_request_ctx(req); + rctx->aead = 1; + rctx->alg = CIPHER_ALG_AES; + rctx->dir = QCE_DECRYPT; + rctx->mode = QCE_MODE_CBC; + rctx->iv = req->iv; + rctx->aead_req = req; + + if (ctx->auth_alg == QCE_HASH_SHA1_HMAC) + pstat->aead_sha1_aes_dec++; + else + pstat->aead_sha256_aes_dec++; + + if (ctx->enc_key_len == AES_KEYSIZE_192 && ctx->cipher_aes192_fb && + ctx->ahash_aead_aes192_fb) + return _qcrypto_aead_aes_192_fallback(req, false); + return _qcrypto_queue_req(cp, ctx->pengine, &req->base); +} + +static int _qcrypto_aead_encrypt_des_cbc(struct aead_request *req) +{ + struct qcrypto_cipher_req_ctx *rctx; + struct qcrypto_cipher_ctx *ctx = crypto_tfm_ctx(req->base.tfm); + struct crypto_priv *cp = ctx->cp; + struct crypto_stat *pstat; + + pstat = &_qcrypto_stat; + + rctx = aead_request_ctx(req); + rctx->aead = 1; + rctx->alg = CIPHER_ALG_DES; + rctx->dir = QCE_ENCRYPT; + rctx->mode = QCE_MODE_CBC; + rctx->iv = req->iv; + + if (ctx->auth_alg == QCE_HASH_SHA1_HMAC) + pstat->aead_sha1_des_enc++; + else + pstat->aead_sha256_des_enc++; + return _qcrypto_queue_req(cp, ctx->pengine, &req->base); +} + +static int _qcrypto_aead_decrypt_des_cbc(struct aead_request *req) +{ + struct qcrypto_cipher_req_ctx *rctx; + struct qcrypto_cipher_ctx *ctx = crypto_tfm_ctx(req->base.tfm); + struct crypto_priv *cp = ctx->cp; + struct crypto_stat *pstat; + + pstat = &_qcrypto_stat; + + rctx = aead_request_ctx(req); + rctx->aead = 1; + rctx->alg = CIPHER_ALG_DES; + rctx->dir = QCE_DECRYPT; + rctx->mode = QCE_MODE_CBC; + rctx->iv = req->iv; + + if (ctx->auth_alg == QCE_HASH_SHA1_HMAC) + pstat->aead_sha1_des_dec++; + else + pstat->aead_sha256_des_dec++; + return _qcrypto_queue_req(cp, ctx->pengine, &req->base); +} + +static int _qcrypto_aead_encrypt_3des_cbc(struct aead_request *req) +{ + struct qcrypto_cipher_req_ctx *rctx; + struct qcrypto_cipher_ctx *ctx = crypto_tfm_ctx(req->base.tfm); + struct crypto_priv *cp = ctx->cp; + struct crypto_stat *pstat; + + pstat = &_qcrypto_stat; + + rctx = aead_request_ctx(req); + rctx->aead = 1; + rctx->alg = CIPHER_ALG_3DES; + rctx->dir = QCE_ENCRYPT; + rctx->mode = QCE_MODE_CBC; + rctx->iv = req->iv; + + if (ctx->auth_alg == QCE_HASH_SHA1_HMAC) + pstat->aead_sha1_3des_enc++; + else + pstat->aead_sha256_3des_enc++; + return _qcrypto_queue_req(cp, ctx->pengine, &req->base); +} + +static int _qcrypto_aead_decrypt_3des_cbc(struct aead_request *req) +{ + struct qcrypto_cipher_req_ctx *rctx; + struct qcrypto_cipher_ctx *ctx = crypto_tfm_ctx(req->base.tfm); + struct crypto_priv *cp = ctx->cp; + struct crypto_stat *pstat; + + pstat = &_qcrypto_stat; + + rctx = aead_request_ctx(req); + rctx->aead = 1; + rctx->alg = CIPHER_ALG_3DES; + rctx->dir = QCE_DECRYPT; + rctx->mode = QCE_MODE_CBC; + rctx->iv = req->iv; + + if (ctx->auth_alg == QCE_HASH_SHA1_HMAC) + pstat->aead_sha1_3des_dec++; + else + pstat->aead_sha256_3des_dec++; + return _qcrypto_queue_req(cp, ctx->pengine, &req->base); +} + +static int _sha_init(struct ahash_request *req) +{ + struct qcrypto_sha_req_ctx *rctx = ahash_request_ctx(req); + + rctx->first_blk = 1; + rctx->last_blk = 0; + rctx->byte_count[0] = 0; + rctx->byte_count[1] = 0; + rctx->byte_count[2] = 0; + rctx->byte_count[3] = 0; + rctx->trailing_buf_len = 0; + rctx->count = 0; + + return 0; +}; + +static int _sha1_init(struct ahash_request *req) +{ + struct qcrypto_sha_ctx *sha_ctx = crypto_tfm_ctx(req->base.tfm); + struct crypto_stat *pstat; + struct qcrypto_sha_req_ctx *rctx = ahash_request_ctx(req); + + pstat = &_qcrypto_stat; + + _sha_init(req); + sha_ctx->alg = QCE_HASH_SHA1; + + memset(&rctx->trailing_buf[0], 0x00, SHA1_BLOCK_SIZE); + memcpy(&rctx->digest[0], &_std_init_vector_sha1_uint8[0], + SHA1_DIGEST_SIZE); + sha_ctx->diglen = SHA1_DIGEST_SIZE; + pstat->sha1_digest++; + return 0; +}; + +static int _sha256_init(struct ahash_request *req) +{ + struct qcrypto_sha_ctx *sha_ctx = crypto_tfm_ctx(req->base.tfm); + struct crypto_stat *pstat; + struct qcrypto_sha_req_ctx *rctx = ahash_request_ctx(req); + + pstat = &_qcrypto_stat; + + _sha_init(req); + sha_ctx->alg = QCE_HASH_SHA256; + + memset(&rctx->trailing_buf[0], 0x00, SHA256_BLOCK_SIZE); + memcpy(&rctx->digest[0], &_std_init_vector_sha256_uint8[0], + SHA256_DIGEST_SIZE); + sha_ctx->diglen = SHA256_DIGEST_SIZE; + pstat->sha256_digest++; + return 0; +}; + + +static int _sha1_export(struct ahash_request *req, void *out) +{ + struct qcrypto_sha_req_ctx *rctx = ahash_request_ctx(req); + struct sha1_state *out_ctx = (struct sha1_state *)out; + + out_ctx->count = rctx->count; + _byte_stream_to_words(out_ctx->state, rctx->digest, SHA1_DIGEST_SIZE); + memcpy(out_ctx->buffer, rctx->trailing_buf, SHA1_BLOCK_SIZE); + + return 0; +}; + +static int _sha1_hmac_export(struct ahash_request *req, void *out) +{ + return _sha1_export(req, out); +} + +/* crypto hw padding constant for hmac first operation */ +#define HMAC_PADDING 64 + +static int __sha1_import_common(struct ahash_request *req, const void *in, + bool hmac) +{ + struct qcrypto_sha_ctx *sha_ctx = crypto_tfm_ctx(req->base.tfm); + struct qcrypto_sha_req_ctx *rctx = ahash_request_ctx(req); + struct sha1_state *in_ctx = (struct sha1_state *)in; + u64 hw_count = in_ctx->count; + + rctx->count = in_ctx->count; + memcpy(rctx->trailing_buf, in_ctx->buffer, SHA1_BLOCK_SIZE); + if (in_ctx->count <= SHA1_BLOCK_SIZE) { + rctx->first_blk = 1; + } else { + rctx->first_blk = 0; + /* + * For hmac, there is a hardware padding done + * when first is set. So the byte_count will be + * incremened by 64 after the operstion of first + */ + if (hmac) + hw_count += HMAC_PADDING; + } + rctx->byte_count[0] = (uint32_t)(hw_count & 0xFFFFFFC0); + rctx->byte_count[1] = (uint32_t)(hw_count >> 32); + _words_to_byte_stream(in_ctx->state, rctx->digest, sha_ctx->diglen); + + rctx->trailing_buf_len = (uint32_t)(in_ctx->count & + (SHA1_BLOCK_SIZE-1)); + return 0; +} + +static int _sha1_import(struct ahash_request *req, const void *in) +{ + return __sha1_import_common(req, in, false); +} + +static int _sha1_hmac_import(struct ahash_request *req, const void *in) +{ + return __sha1_import_common(req, in, true); +} + +static int _sha256_export(struct ahash_request *req, void *out) +{ + struct qcrypto_sha_req_ctx *rctx = ahash_request_ctx(req); + struct sha256_state *out_ctx = (struct sha256_state *)out; + + out_ctx->count = rctx->count; + _byte_stream_to_words(out_ctx->state, rctx->digest, SHA256_DIGEST_SIZE); + memcpy(out_ctx->buf, rctx->trailing_buf, SHA256_BLOCK_SIZE); + + return 0; +}; + +static int _sha256_hmac_export(struct ahash_request *req, void *out) +{ + return _sha256_export(req, out); +} + +static int __sha256_import_common(struct ahash_request *req, const void *in, + bool hmac) +{ + struct qcrypto_sha_ctx *sha_ctx = crypto_tfm_ctx(req->base.tfm); + struct qcrypto_sha_req_ctx *rctx = ahash_request_ctx(req); + struct sha256_state *in_ctx = (struct sha256_state *)in; + u64 hw_count = in_ctx->count; + + rctx->count = in_ctx->count; + memcpy(rctx->trailing_buf, in_ctx->buf, SHA256_BLOCK_SIZE); + + if (in_ctx->count <= SHA256_BLOCK_SIZE) { + rctx->first_blk = 1; + } else { + rctx->first_blk = 0; + /* + * for hmac, there is a hardware padding done + * when first is set. So the byte_count will be + * incremened by 64 after the operstion of first + */ + if (hmac) + hw_count += HMAC_PADDING; + } + + rctx->byte_count[0] = (uint32_t)(hw_count & 0xFFFFFFC0); + rctx->byte_count[1] = (uint32_t)(hw_count >> 32); + _words_to_byte_stream(in_ctx->state, rctx->digest, sha_ctx->diglen); + + rctx->trailing_buf_len = (uint32_t)(in_ctx->count & + (SHA256_BLOCK_SIZE-1)); + + + return 0; +} + +static int _sha256_import(struct ahash_request *req, const void *in) +{ + return __sha256_import_common(req, in, false); +} + +static int _sha256_hmac_import(struct ahash_request *req, const void *in) +{ + return __sha256_import_common(req, in, true); +} + +static int _copy_source(struct ahash_request *req) +{ + struct qcrypto_sha_req_ctx *srctx = NULL; + uint32_t bytes = 0; + uint32_t num_sg = 0; + + srctx = ahash_request_ctx(req); + srctx->orig_src = req->src; + srctx->data = kzalloc((req->nbytes + 64), GFP_ATOMIC); + if (srctx->data == NULL) { + pr_err("Mem Alloc fail rctx->data, err %ld for 0x%x\n", + PTR_ERR(srctx->data), (req->nbytes + 64)); + return -ENOMEM; + } + + num_sg = qcrypto_count_sg(req->src, req->nbytes); + bytes = qcrypto_sg_copy_to_buffer(req->src, num_sg, srctx->data, + req->nbytes); + if (bytes != req->nbytes) + pr_warn("bytes copied=0x%x bytes to copy= 0x%x", bytes, + req->nbytes); + sg_set_buf(&srctx->dsg, srctx->data, + req->nbytes); + sg_mark_end(&srctx->dsg); + req->src = &srctx->dsg; + + return 0; +} + +static int _sha_update(struct ahash_request *req, uint32_t sha_block_size) +{ + struct qcrypto_sha_ctx *sha_ctx = crypto_tfm_ctx(req->base.tfm); + struct crypto_priv *cp = sha_ctx->cp; + struct qcrypto_sha_req_ctx *rctx = ahash_request_ctx(req); + uint32_t total, len, num_sg; + struct scatterlist *sg_last; + uint8_t *k_src = NULL; + uint32_t sha_pad_len = 0; + uint32_t trailing_buf_len = 0; + uint32_t nbytes; + uint32_t offset = 0; + uint32_t bytes = 0; + uint8_t *staging; + int ret = 0; + + /* check for trailing buffer from previous updates and append it */ + total = req->nbytes + rctx->trailing_buf_len; + len = req->nbytes; + + if (total <= sha_block_size) { + k_src = &rctx->trailing_buf[rctx->trailing_buf_len]; + num_sg = qcrypto_count_sg(req->src, len); + bytes = qcrypto_sg_copy_to_buffer(req->src, num_sg, k_src, len); + + rctx->trailing_buf_len = total; + return 0; + } + + /* save the original req structure fields*/ + rctx->src = req->src; + rctx->nbytes = req->nbytes; + + staging = (uint8_t *)ALIGN(((uintptr_t)rctx->staging_dmabuf), + L1_CACHE_BYTES); + memcpy(staging, rctx->trailing_buf, rctx->trailing_buf_len); + k_src = &rctx->trailing_buf[0]; + /* get new trailing buffer */ + sha_pad_len = ALIGN(total, sha_block_size) - total; + trailing_buf_len = sha_block_size - sha_pad_len; + offset = req->nbytes - trailing_buf_len; + + if (offset != req->nbytes) + scatterwalk_map_and_copy(k_src, req->src, offset, + trailing_buf_len, 0); + + nbytes = total - trailing_buf_len; + num_sg = qcrypto_count_sg(req->src, req->nbytes); + + len = rctx->trailing_buf_len; + sg_last = req->src; + + while (len < nbytes) { + if ((len + sg_last->length) > nbytes) + break; + len += sg_last->length; + sg_last = sg_next(sg_last); + } + if (rctx->trailing_buf_len) { + if (cp->ce_support.aligned_only) { + rctx->data2 = kzalloc((req->nbytes + 64), GFP_ATOMIC); + if (rctx->data2 == NULL) { + pr_err("Mem Alloc fail srctx->data2, err %ld\n", + PTR_ERR(rctx->data2)); + return -ENOMEM; + } + memcpy(rctx->data2, staging, + rctx->trailing_buf_len); + memcpy((rctx->data2 + rctx->trailing_buf_len), + rctx->data, req->src->length); + kzfree(rctx->data); + rctx->data = rctx->data2; + sg_set_buf(&rctx->sg[0], rctx->data, + (rctx->trailing_buf_len + + req->src->length)); + req->src = rctx->sg; + sg_mark_end(&rctx->sg[0]); + } else { + sg_mark_end(sg_last); + memset(rctx->sg, 0, sizeof(rctx->sg)); + sg_set_buf(&rctx->sg[0], staging, + rctx->trailing_buf_len); + sg_mark_end(&rctx->sg[1]); + sg_chain(rctx->sg, 2, req->src); + req->src = rctx->sg; + } + } else + sg_mark_end(sg_last); + + req->nbytes = nbytes; + rctx->trailing_buf_len = trailing_buf_len; + + ret = _qcrypto_queue_req(cp, sha_ctx->pengine, &req->base); + + return ret; +}; + +static int _sha1_update(struct ahash_request *req) +{ + struct qcrypto_sha_req_ctx *rctx = ahash_request_ctx(req); + struct qcrypto_sha_ctx *sha_ctx = crypto_tfm_ctx(req->base.tfm); + struct crypto_priv *cp = sha_ctx->cp; + + if (cp->ce_support.aligned_only) { + if (_copy_source(req)) + return -ENOMEM; + } + rctx->count += req->nbytes; + return _sha_update(req, SHA1_BLOCK_SIZE); +} + +static int _sha256_update(struct ahash_request *req) +{ + struct qcrypto_sha_req_ctx *rctx = ahash_request_ctx(req); + struct qcrypto_sha_ctx *sha_ctx = crypto_tfm_ctx(req->base.tfm); + struct crypto_priv *cp = sha_ctx->cp; + + if (cp->ce_support.aligned_only) { + if (_copy_source(req)) + return -ENOMEM; + } + + rctx->count += req->nbytes; + return _sha_update(req, SHA256_BLOCK_SIZE); +} + +static int _sha_final(struct ahash_request *req, uint32_t sha_block_size) +{ + struct qcrypto_sha_ctx *sha_ctx = crypto_tfm_ctx(req->base.tfm); + struct crypto_priv *cp = sha_ctx->cp; + struct qcrypto_sha_req_ctx *rctx = ahash_request_ctx(req); + int ret = 0; + uint8_t *staging; + + if (cp->ce_support.aligned_only) { + if (_copy_source(req)) + return -ENOMEM; + } + + rctx->last_blk = 1; + + /* save the original req structure fields*/ + rctx->src = req->src; + rctx->nbytes = req->nbytes; + + staging = (uint8_t *)ALIGN(((uintptr_t)rctx->staging_dmabuf), + L1_CACHE_BYTES); + memcpy(staging, rctx->trailing_buf, rctx->trailing_buf_len); + sg_set_buf(&rctx->sg[0], staging, rctx->trailing_buf_len); + sg_mark_end(&rctx->sg[0]); + + req->src = &rctx->sg[0]; + req->nbytes = rctx->trailing_buf_len; + + ret = _qcrypto_queue_req(cp, sha_ctx->pengine, &req->base); + + return ret; +}; + +static int _sha1_final(struct ahash_request *req) +{ + return _sha_final(req, SHA1_BLOCK_SIZE); +} + +static int _sha256_final(struct ahash_request *req) +{ + return _sha_final(req, SHA256_BLOCK_SIZE); +} + +static int _sha_digest(struct ahash_request *req) +{ + struct qcrypto_sha_ctx *sha_ctx = crypto_tfm_ctx(req->base.tfm); + struct qcrypto_sha_req_ctx *rctx = ahash_request_ctx(req); + struct crypto_priv *cp = sha_ctx->cp; + int ret = 0; + + if (cp->ce_support.aligned_only) { + if (_copy_source(req)) + return -ENOMEM; + } + + /* save the original req structure fields*/ + rctx->src = req->src; + rctx->nbytes = req->nbytes; + rctx->first_blk = 1; + rctx->last_blk = 1; + ret = _qcrypto_queue_req(cp, sha_ctx->pengine, &req->base); + + return ret; +} + +static int _sha1_digest(struct ahash_request *req) +{ + _sha1_init(req); + return _sha_digest(req); +} + +static int _sha256_digest(struct ahash_request *req) +{ + _sha256_init(req); + return _sha_digest(req); +} + +static void _crypto_sha_hmac_ahash_req_complete( + struct crypto_async_request *req, int err) +{ + struct completion *ahash_req_complete = req->data; + + if (err == -EINPROGRESS) + return; + complete(ahash_req_complete); +} + +static int _sha_hmac_setkey(struct crypto_ahash *tfm, const u8 *key, + unsigned int len) +{ + struct qcrypto_sha_ctx *sha_ctx = crypto_tfm_ctx(&tfm->base); + uint8_t *in_buf; + int ret = 0; + struct scatterlist sg; + struct ahash_request *ahash_req; + struct completion ahash_req_complete; + + ahash_req = ahash_request_alloc(tfm, GFP_KERNEL); + if (ahash_req == NULL) + return -ENOMEM; + init_completion(&ahash_req_complete); + ahash_request_set_callback(ahash_req, + CRYPTO_TFM_REQ_MAY_BACKLOG, + _crypto_sha_hmac_ahash_req_complete, + &ahash_req_complete); + crypto_ahash_clear_flags(tfm, ~0); + + in_buf = kzalloc(len + 64, GFP_KERNEL); + if (in_buf == NULL) { + pr_err("qcrypto Can't Allocate mem: in_buf, error %ld\n", + PTR_ERR(in_buf)); + ahash_request_free(ahash_req); + return -ENOMEM; + } + memcpy(in_buf, key, len); + sg_set_buf(&sg, in_buf, len); + sg_mark_end(&sg); + + ahash_request_set_crypt(ahash_req, &sg, + &sha_ctx->authkey[0], len); + + if (sha_ctx->alg == QCE_HASH_SHA1) + ret = _sha1_digest(ahash_req); + else + ret = _sha256_digest(ahash_req); + if (ret == -EINPROGRESS || ret == -EBUSY) { + ret = + wait_for_completion_interruptible( + &ahash_req_complete); + reinit_completion(&sha_ctx->ahash_req_complete); + } + + kzfree(in_buf); + ahash_request_free(ahash_req); + + return ret; +} + +static int _sha1_hmac_setkey(struct crypto_ahash *tfm, const u8 *key, + unsigned int len) +{ + struct qcrypto_sha_ctx *sha_ctx = crypto_tfm_ctx(&tfm->base); + int ret = 0; + memset(&sha_ctx->authkey[0], 0, SHA1_BLOCK_SIZE); + if (len <= SHA1_BLOCK_SIZE) { + memcpy(&sha_ctx->authkey[0], key, len); + sha_ctx->authkey_in_len = len; + } else { + sha_ctx->alg = QCE_HASH_SHA1; + sha_ctx->diglen = SHA1_DIGEST_SIZE; + ret = _sha_hmac_setkey(tfm, key, len); + if (ret) + pr_err("SHA1 hmac setkey failed\n"); + sha_ctx->authkey_in_len = SHA1_BLOCK_SIZE; + } + return ret; +} + +static int _sha256_hmac_setkey(struct crypto_ahash *tfm, const u8 *key, + unsigned int len) +{ + struct qcrypto_sha_ctx *sha_ctx = crypto_tfm_ctx(&tfm->base); + int ret = 0; + + memset(&sha_ctx->authkey[0], 0, SHA256_BLOCK_SIZE); + if (len <= SHA256_BLOCK_SIZE) { + memcpy(&sha_ctx->authkey[0], key, len); + sha_ctx->authkey_in_len = len; + } else { + sha_ctx->alg = QCE_HASH_SHA256; + sha_ctx->diglen = SHA256_DIGEST_SIZE; + ret = _sha_hmac_setkey(tfm, key, len); + if (ret) + pr_err("SHA256 hmac setkey failed\n"); + sha_ctx->authkey_in_len = SHA256_BLOCK_SIZE; + } + + return ret; +} + +static int _sha_hmac_init_ihash(struct ahash_request *req, + uint32_t sha_block_size) +{ + struct qcrypto_sha_ctx *sha_ctx = crypto_tfm_ctx(req->base.tfm); + struct qcrypto_sha_req_ctx *rctx = ahash_request_ctx(req); + int i; + + for (i = 0; i < sha_block_size; i++) + rctx->trailing_buf[i] = sha_ctx->authkey[i] ^ 0x36; + rctx->trailing_buf_len = sha_block_size; + + return 0; +} + +static int _sha1_hmac_init(struct ahash_request *req) +{ + struct qcrypto_sha_ctx *sha_ctx = crypto_tfm_ctx(req->base.tfm); + struct crypto_priv *cp = sha_ctx->cp; + struct crypto_stat *pstat; + int ret = 0; + struct qcrypto_sha_req_ctx *rctx = ahash_request_ctx(req); + + pstat = &_qcrypto_stat; + pstat->sha1_hmac_digest++; + + _sha_init(req); + memset(&rctx->trailing_buf[0], 0x00, SHA1_BLOCK_SIZE); + memcpy(&rctx->digest[0], &_std_init_vector_sha1_uint8[0], + SHA1_DIGEST_SIZE); + sha_ctx->diglen = SHA1_DIGEST_SIZE; + + if (cp->ce_support.sha_hmac) + sha_ctx->alg = QCE_HASH_SHA1_HMAC; + else { + sha_ctx->alg = QCE_HASH_SHA1; + ret = _sha_hmac_init_ihash(req, SHA1_BLOCK_SIZE); + } + + return ret; +} + +static int _sha256_hmac_init(struct ahash_request *req) +{ + struct qcrypto_sha_ctx *sha_ctx = crypto_tfm_ctx(req->base.tfm); + struct crypto_priv *cp = sha_ctx->cp; + struct crypto_stat *pstat; + int ret = 0; + struct qcrypto_sha_req_ctx *rctx = ahash_request_ctx(req); + + pstat = &_qcrypto_stat; + pstat->sha256_hmac_digest++; + + _sha_init(req); + + memset(&rctx->trailing_buf[0], 0x00, SHA256_BLOCK_SIZE); + memcpy(&rctx->digest[0], &_std_init_vector_sha256_uint8[0], + SHA256_DIGEST_SIZE); + sha_ctx->diglen = SHA256_DIGEST_SIZE; + + if (cp->ce_support.sha_hmac) + sha_ctx->alg = QCE_HASH_SHA256_HMAC; + else { + sha_ctx->alg = QCE_HASH_SHA256; + ret = _sha_hmac_init_ihash(req, SHA256_BLOCK_SIZE); + } + + return ret; +} + +static int _sha1_hmac_update(struct ahash_request *req) +{ + return _sha1_update(req); +} + +static int _sha256_hmac_update(struct ahash_request *req) +{ + return _sha256_update(req); +} + +static int _sha_hmac_outer_hash(struct ahash_request *req, + uint32_t sha_digest_size, uint32_t sha_block_size) +{ + struct qcrypto_sha_ctx *sha_ctx = crypto_tfm_ctx(req->base.tfm); + struct qcrypto_sha_req_ctx *rctx = ahash_request_ctx(req); + struct crypto_priv *cp = sha_ctx->cp; + int i; + uint8_t *staging; + uint8_t *p; + + staging = (uint8_t *)ALIGN(((uintptr_t)rctx->staging_dmabuf), + L1_CACHE_BYTES); + p = staging; + for (i = 0; i < sha_block_size; i++) + *p++ = sha_ctx->authkey[i] ^ 0x5c; + memcpy(p, &rctx->digest[0], sha_digest_size); + sg_set_buf(&rctx->sg[0], staging, sha_block_size + + sha_digest_size); + sg_mark_end(&rctx->sg[0]); + + /* save the original req structure fields*/ + rctx->src = req->src; + rctx->nbytes = req->nbytes; + + req->src = &rctx->sg[0]; + req->nbytes = sha_block_size + sha_digest_size; + + _sha_init(req); + if (sha_ctx->alg == QCE_HASH_SHA1) { + memcpy(&rctx->digest[0], &_std_init_vector_sha1_uint8[0], + SHA1_DIGEST_SIZE); + sha_ctx->diglen = SHA1_DIGEST_SIZE; + } else { + memcpy(&rctx->digest[0], &_std_init_vector_sha256_uint8[0], + SHA256_DIGEST_SIZE); + sha_ctx->diglen = SHA256_DIGEST_SIZE; + } + + rctx->last_blk = 1; + return _qcrypto_queue_req(cp, sha_ctx->pengine, &req->base); +} + +static int _sha_hmac_inner_hash(struct ahash_request *req, + uint32_t sha_digest_size, uint32_t sha_block_size) +{ + struct qcrypto_sha_ctx *sha_ctx = crypto_tfm_ctx(req->base.tfm); + struct ahash_request *areq = sha_ctx->ahash_req; + struct crypto_priv *cp = sha_ctx->cp; + int ret = 0; + struct qcrypto_sha_req_ctx *rctx = ahash_request_ctx(req); + uint8_t *staging; + + staging = (uint8_t *)ALIGN(((uintptr_t)rctx->staging_dmabuf), + L1_CACHE_BYTES); + memcpy(staging, rctx->trailing_buf, rctx->trailing_buf_len); + sg_set_buf(&rctx->sg[0], staging, rctx->trailing_buf_len); + sg_mark_end(&rctx->sg[0]); + + ahash_request_set_crypt(areq, &rctx->sg[0], &rctx->digest[0], + rctx->trailing_buf_len); + rctx->last_blk = 1; + ret = _qcrypto_queue_req(cp, sha_ctx->pengine, &areq->base); + + if (ret == -EINPROGRESS || ret == -EBUSY) { + ret = + wait_for_completion_interruptible(&sha_ctx->ahash_req_complete); + reinit_completion(&sha_ctx->ahash_req_complete); + } + + return ret; +} + +static int _sha1_hmac_final(struct ahash_request *req) +{ + struct qcrypto_sha_ctx *sha_ctx = crypto_tfm_ctx(req->base.tfm); + struct crypto_priv *cp = sha_ctx->cp; + int ret = 0; + + if (cp->ce_support.sha_hmac) + return _sha_final(req, SHA1_BLOCK_SIZE); + else { + ret = _sha_hmac_inner_hash(req, SHA1_DIGEST_SIZE, + SHA1_BLOCK_SIZE); + if (ret) + return ret; + return _sha_hmac_outer_hash(req, SHA1_DIGEST_SIZE, + SHA1_BLOCK_SIZE); + } +} + +static int _sha256_hmac_final(struct ahash_request *req) +{ + struct qcrypto_sha_ctx *sha_ctx = crypto_tfm_ctx(req->base.tfm); + struct crypto_priv *cp = sha_ctx->cp; + int ret = 0; + + if (cp->ce_support.sha_hmac) + return _sha_final(req, SHA256_BLOCK_SIZE); + else { + ret = _sha_hmac_inner_hash(req, SHA256_DIGEST_SIZE, + SHA256_BLOCK_SIZE); + if (ret) + return ret; + return _sha_hmac_outer_hash(req, SHA256_DIGEST_SIZE, + SHA256_BLOCK_SIZE); + } + return 0; +} + + +static int _sha1_hmac_digest(struct ahash_request *req) +{ + struct qcrypto_sha_ctx *sha_ctx = crypto_tfm_ctx(req->base.tfm); + struct crypto_stat *pstat; + struct qcrypto_sha_req_ctx *rctx = ahash_request_ctx(req); + + pstat = &_qcrypto_stat; + pstat->sha1_hmac_digest++; + + _sha_init(req); + memcpy(&rctx->digest[0], &_std_init_vector_sha1_uint8[0], + SHA1_DIGEST_SIZE); + sha_ctx->diglen = SHA1_DIGEST_SIZE; + sha_ctx->alg = QCE_HASH_SHA1_HMAC; + + return _sha_digest(req); +} + +static int _sha256_hmac_digest(struct ahash_request *req) +{ + struct qcrypto_sha_ctx *sha_ctx = crypto_tfm_ctx(req->base.tfm); + struct crypto_stat *pstat; + struct qcrypto_sha_req_ctx *rctx = ahash_request_ctx(req); + + pstat = &_qcrypto_stat; + pstat->sha256_hmac_digest++; + + _sha_init(req); + memcpy(&rctx->digest[0], &_std_init_vector_sha256_uint8[0], + SHA256_DIGEST_SIZE); + sha_ctx->diglen = SHA256_DIGEST_SIZE; + sha_ctx->alg = QCE_HASH_SHA256_HMAC; + + return _sha_digest(req); +} + +static int _qcrypto_prefix_alg_cra_name(char cra_name[], unsigned int size) +{ + char new_cra_name[CRYPTO_MAX_ALG_NAME] = "qcom-"; + if (size >= CRYPTO_MAX_ALG_NAME - strlen("qcom-")) + return -EINVAL; + strlcat(new_cra_name, cra_name, CRYPTO_MAX_ALG_NAME); + strlcpy(cra_name, new_cra_name, CRYPTO_MAX_ALG_NAME); + return 0; +} + + +int qcrypto_cipher_set_device(struct ablkcipher_request *req, unsigned int dev) +{ + struct qcrypto_cipher_ctx *ctx = crypto_tfm_ctx(req->base.tfm); + struct crypto_priv *cp = ctx->cp; + struct crypto_engine *pengine = NULL; + + pengine = _qrypto_find_pengine_device(cp, dev); + if (pengine == NULL) + return -ENODEV; + ctx->pengine = pengine; + + return 0; +}; +EXPORT_SYMBOL(qcrypto_cipher_set_device); + +int qcrypto_cipher_set_device_hw(struct ablkcipher_request *req, u32 dev, + u32 hw_inst) +{ + struct qcrypto_cipher_ctx *ctx = crypto_tfm_ctx(req->base.tfm); + struct crypto_priv *cp = ctx->cp; + struct crypto_engine *pengine = NULL; + + pengine = _qrypto_find_pengine_device_hw(cp, dev, hw_inst); + if (pengine == NULL) + return -ENODEV; + ctx->pengine = pengine; + + return 0; +} +EXPORT_SYMBOL(qcrypto_cipher_set_device_hw); + +int qcrypto_aead_set_device(struct aead_request *req, unsigned int dev) +{ + struct qcrypto_cipher_ctx *ctx = crypto_tfm_ctx(req->base.tfm); + struct crypto_priv *cp = ctx->cp; + struct crypto_engine *pengine = NULL; + + pengine = _qrypto_find_pengine_device(cp, dev); + if (pengine == NULL) + return -ENODEV; + ctx->pengine = pengine; + + return 0; +}; +EXPORT_SYMBOL(qcrypto_aead_set_device); + +int qcrypto_ahash_set_device(struct ahash_request *req, unsigned int dev) +{ + struct qcrypto_sha_ctx *ctx = crypto_tfm_ctx(req->base.tfm); + struct crypto_priv *cp = ctx->cp; + struct crypto_engine *pengine = NULL; + + pengine = _qrypto_find_pengine_device(cp, dev); + if (pengine == NULL) + return -ENODEV; + ctx->pengine = pengine; + + return 0; +}; +EXPORT_SYMBOL(qcrypto_ahash_set_device); + +int qcrypto_cipher_set_flag(struct ablkcipher_request *req, unsigned int flags) +{ + struct qcrypto_cipher_ctx *ctx = crypto_tfm_ctx(req->base.tfm); + struct crypto_priv *cp = ctx->cp; + + if ((flags & QCRYPTO_CTX_USE_HW_KEY) && + (cp->platform_support.hw_key_support == false)) { + pr_err("%s HW key usage not supported\n", __func__); + return -EINVAL; + } + if (((flags | ctx->flags) & QCRYPTO_CTX_KEY_MASK) == + QCRYPTO_CTX_KEY_MASK) { + pr_err("%s Cannot set all key flags\n", __func__); + return -EINVAL; + } + + ctx->flags |= flags; + return 0; +}; +EXPORT_SYMBOL(qcrypto_cipher_set_flag); + +int qcrypto_aead_set_flag(struct aead_request *req, unsigned int flags) +{ + struct qcrypto_cipher_ctx *ctx = crypto_tfm_ctx(req->base.tfm); + struct crypto_priv *cp = ctx->cp; + + if ((flags & QCRYPTO_CTX_USE_HW_KEY) && + (cp->platform_support.hw_key_support == false)) { + pr_err("%s HW key usage not supported\n", __func__); + return -EINVAL; + } + if (((flags | ctx->flags) & QCRYPTO_CTX_KEY_MASK) == + QCRYPTO_CTX_KEY_MASK) { + pr_err("%s Cannot set all key flags\n", __func__); + return -EINVAL; + } + + ctx->flags |= flags; + return 0; +}; +EXPORT_SYMBOL(qcrypto_aead_set_flag); + +int qcrypto_ahash_set_flag(struct ahash_request *req, unsigned int flags) +{ + struct qcrypto_sha_ctx *ctx = crypto_tfm_ctx(req->base.tfm); + struct crypto_priv *cp = ctx->cp; + + if ((flags & QCRYPTO_CTX_USE_HW_KEY) && + (cp->platform_support.hw_key_support == false)) { + pr_err("%s HW key usage not supported\n", __func__); + return -EINVAL; + } + if (((flags | ctx->flags) & QCRYPTO_CTX_KEY_MASK) == + QCRYPTO_CTX_KEY_MASK) { + pr_err("%s Cannot set all key flags\n", __func__); + return -EINVAL; + } + + ctx->flags |= flags; + return 0; +}; +EXPORT_SYMBOL(qcrypto_ahash_set_flag); + +int qcrypto_cipher_clear_flag(struct ablkcipher_request *req, + unsigned int flags) +{ + struct qcrypto_cipher_ctx *ctx = crypto_tfm_ctx(req->base.tfm); + + ctx->flags &= ~flags; + return 0; + +}; +EXPORT_SYMBOL(qcrypto_cipher_clear_flag); + +int qcrypto_aead_clear_flag(struct aead_request *req, unsigned int flags) +{ + struct qcrypto_cipher_ctx *ctx = crypto_tfm_ctx(req->base.tfm); + + ctx->flags &= ~flags; + return 0; + +}; +EXPORT_SYMBOL(qcrypto_aead_clear_flag); + +int qcrypto_ahash_clear_flag(struct ahash_request *req, unsigned int flags) +{ + struct qcrypto_sha_ctx *ctx = crypto_tfm_ctx(req->base.tfm); + + ctx->flags &= ~flags; + return 0; +}; +EXPORT_SYMBOL(qcrypto_ahash_clear_flag); + +static struct ahash_alg _qcrypto_ahash_algos[] = { + { + .init = _sha1_init, + .update = _sha1_update, + .final = _sha1_final, + .export = _sha1_export, + .import = _sha1_import, + .digest = _sha1_digest, + .halg = { + .digestsize = SHA1_DIGEST_SIZE, + .statesize = sizeof(struct sha1_state), + .base = { + .cra_name = "sha1", + .cra_driver_name = "qcrypto-sha1", + .cra_priority = 300, + .cra_flags = CRYPTO_ALG_TYPE_AHASH | + CRYPTO_ALG_ASYNC, + .cra_blocksize = SHA1_BLOCK_SIZE, + .cra_ctxsize = + sizeof(struct qcrypto_sha_ctx), + .cra_alignmask = 0, + .cra_type = &crypto_ahash_type, + .cra_module = THIS_MODULE, + .cra_init = _qcrypto_ahash_cra_init, + .cra_exit = _qcrypto_ahash_cra_exit, + }, + }, + }, + { + .init = _sha256_init, + .update = _sha256_update, + .final = _sha256_final, + .export = _sha256_export, + .import = _sha256_import, + .digest = _sha256_digest, + .halg = { + .digestsize = SHA256_DIGEST_SIZE, + .statesize = sizeof(struct sha256_state), + .base = { + .cra_name = "sha256", + .cra_driver_name = "qcrypto-sha256", + .cra_priority = 300, + .cra_flags = CRYPTO_ALG_TYPE_AHASH | + CRYPTO_ALG_ASYNC, + .cra_blocksize = SHA256_BLOCK_SIZE, + .cra_ctxsize = + sizeof(struct qcrypto_sha_ctx), + .cra_alignmask = 0, + .cra_type = &crypto_ahash_type, + .cra_module = THIS_MODULE, + .cra_init = _qcrypto_ahash_cra_init, + .cra_exit = _qcrypto_ahash_cra_exit, + }, + }, + }, +}; + +static struct ahash_alg _qcrypto_sha_hmac_algos[] = { + { + .init = _sha1_hmac_init, + .update = _sha1_hmac_update, + .final = _sha1_hmac_final, + .export = _sha1_hmac_export, + .import = _sha1_hmac_import, + .digest = _sha1_hmac_digest, + .setkey = _sha1_hmac_setkey, + .halg = { + .digestsize = SHA1_DIGEST_SIZE, + .statesize = sizeof(struct sha1_state), + .base = { + .cra_name = "hmac(sha1)", + .cra_driver_name = "qcrypto-hmac-sha1", + .cra_priority = 300, + .cra_flags = CRYPTO_ALG_TYPE_AHASH | + CRYPTO_ALG_ASYNC, + .cra_blocksize = SHA1_BLOCK_SIZE, + .cra_ctxsize = + sizeof(struct qcrypto_sha_ctx), + .cra_alignmask = 0, + .cra_type = &crypto_ahash_type, + .cra_module = THIS_MODULE, + .cra_init = _qcrypto_ahash_hmac_cra_init, + .cra_exit = _qcrypto_ahash_cra_exit, + }, + }, + }, + { + .init = _sha256_hmac_init, + .update = _sha256_hmac_update, + .final = _sha256_hmac_final, + .export = _sha256_hmac_export, + .import = _sha256_hmac_import, + .digest = _sha256_hmac_digest, + .setkey = _sha256_hmac_setkey, + .halg = { + .digestsize = SHA256_DIGEST_SIZE, + .statesize = sizeof(struct sha256_state), + .base = { + .cra_name = "hmac(sha256)", + .cra_driver_name = "qcrypto-hmac-sha256", + .cra_priority = 300, + .cra_flags = CRYPTO_ALG_TYPE_AHASH | + CRYPTO_ALG_ASYNC, + .cra_blocksize = SHA256_BLOCK_SIZE, + .cra_ctxsize = + sizeof(struct qcrypto_sha_ctx), + .cra_alignmask = 0, + .cra_type = &crypto_ahash_type, + .cra_module = THIS_MODULE, + .cra_init = _qcrypto_ahash_hmac_cra_init, + .cra_exit = _qcrypto_ahash_cra_exit, + }, + }, + }, +}; + +static struct crypto_alg _qcrypto_ablk_cipher_algos[] = { + { + .cra_name = "ecb(aes)", + .cra_driver_name = "qcrypto-ecb-aes", + .cra_priority = 300, + .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | + CRYPTO_ALG_NEED_FALLBACK | + CRYPTO_ALG_ASYNC, + .cra_blocksize = AES_BLOCK_SIZE, + .cra_ctxsize = sizeof(struct qcrypto_cipher_ctx), + .cra_alignmask = 0, + .cra_type = &crypto_ablkcipher_type, + .cra_module = THIS_MODULE, + .cra_init = _qcrypto_cra_aes_ablkcipher_init, + .cra_exit = _qcrypto_cra_aes_ablkcipher_exit, + .cra_u = { + .ablkcipher = { + .min_keysize = AES_MIN_KEY_SIZE, + .max_keysize = AES_MAX_KEY_SIZE, + .setkey = _qcrypto_setkey_aes, + .encrypt = _qcrypto_enc_aes_ecb, + .decrypt = _qcrypto_dec_aes_ecb, + }, + }, + }, + { + .cra_name = "cbc(aes)", + .cra_driver_name = "qcrypto-cbc-aes", + .cra_priority = 300, + .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | + CRYPTO_ALG_NEED_FALLBACK | + CRYPTO_ALG_ASYNC, + .cra_blocksize = AES_BLOCK_SIZE, + .cra_ctxsize = sizeof(struct qcrypto_cipher_ctx), + .cra_alignmask = 0, + .cra_type = &crypto_ablkcipher_type, + .cra_module = THIS_MODULE, + .cra_init = _qcrypto_cra_aes_ablkcipher_init, + .cra_exit = _qcrypto_cra_aes_ablkcipher_exit, + .cra_u = { + .ablkcipher = { + .ivsize = AES_BLOCK_SIZE, + .min_keysize = AES_MIN_KEY_SIZE, + .max_keysize = AES_MAX_KEY_SIZE, + .setkey = _qcrypto_setkey_aes, + .encrypt = _qcrypto_enc_aes_cbc, + .decrypt = _qcrypto_dec_aes_cbc, + }, + }, + }, + { + .cra_name = "ctr(aes)", + .cra_driver_name = "qcrypto-ctr-aes", + .cra_priority = 300, + .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | + CRYPTO_ALG_NEED_FALLBACK | + CRYPTO_ALG_ASYNC, + .cra_blocksize = AES_BLOCK_SIZE, + .cra_ctxsize = sizeof(struct qcrypto_cipher_ctx), + .cra_alignmask = 0, + .cra_type = &crypto_ablkcipher_type, + .cra_module = THIS_MODULE, + .cra_init = _qcrypto_cra_aes_ablkcipher_init, + .cra_exit = _qcrypto_cra_aes_ablkcipher_exit, + .cra_u = { + .ablkcipher = { + .ivsize = AES_BLOCK_SIZE, + .min_keysize = AES_MIN_KEY_SIZE, + .max_keysize = AES_MAX_KEY_SIZE, + .setkey = _qcrypto_setkey_aes, + .encrypt = _qcrypto_enc_aes_ctr, + .decrypt = _qcrypto_dec_aes_ctr, + }, + }, + }, + { + .cra_name = "ecb(des)", + .cra_driver_name = "qcrypto-ecb-des", + .cra_priority = 300, + .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC, + .cra_blocksize = DES_BLOCK_SIZE, + .cra_ctxsize = sizeof(struct qcrypto_cipher_ctx), + .cra_alignmask = 0, + .cra_type = &crypto_ablkcipher_type, + .cra_module = THIS_MODULE, + .cra_init = _qcrypto_cra_ablkcipher_init, + .cra_exit = _qcrypto_cra_ablkcipher_exit, + .cra_u = { + .ablkcipher = { + .min_keysize = DES_KEY_SIZE, + .max_keysize = DES_KEY_SIZE, + .setkey = _qcrypto_setkey_des, + .encrypt = _qcrypto_enc_des_ecb, + .decrypt = _qcrypto_dec_des_ecb, + }, + }, + }, + { + .cra_name = "cbc(des)", + .cra_driver_name = "qcrypto-cbc-des", + .cra_priority = 300, + .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC, + .cra_blocksize = DES_BLOCK_SIZE, + .cra_ctxsize = sizeof(struct qcrypto_cipher_ctx), + .cra_alignmask = 0, + .cra_type = &crypto_ablkcipher_type, + .cra_module = THIS_MODULE, + .cra_init = _qcrypto_cra_ablkcipher_init, + .cra_exit = _qcrypto_cra_ablkcipher_exit, + .cra_u = { + .ablkcipher = { + .ivsize = DES_BLOCK_SIZE, + .min_keysize = DES_KEY_SIZE, + .max_keysize = DES_KEY_SIZE, + .setkey = _qcrypto_setkey_des, + .encrypt = _qcrypto_enc_des_cbc, + .decrypt = _qcrypto_dec_des_cbc, + }, + }, + }, + { + .cra_name = "ecb(des3_ede)", + .cra_driver_name = "qcrypto-ecb-3des", + .cra_priority = 300, + .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC, + .cra_blocksize = DES3_EDE_BLOCK_SIZE, + .cra_ctxsize = sizeof(struct qcrypto_cipher_ctx), + .cra_alignmask = 0, + .cra_type = &crypto_ablkcipher_type, + .cra_module = THIS_MODULE, + .cra_init = _qcrypto_cra_ablkcipher_init, + .cra_exit = _qcrypto_cra_ablkcipher_exit, + .cra_u = { + .ablkcipher = { + .min_keysize = DES3_EDE_KEY_SIZE, + .max_keysize = DES3_EDE_KEY_SIZE, + .setkey = _qcrypto_setkey_3des, + .encrypt = _qcrypto_enc_3des_ecb, + .decrypt = _qcrypto_dec_3des_ecb, + }, + }, + }, + { + .cra_name = "cbc(des3_ede)", + .cra_driver_name = "qcrypto-cbc-3des", + .cra_priority = 300, + .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC, + .cra_blocksize = DES3_EDE_BLOCK_SIZE, + .cra_ctxsize = sizeof(struct qcrypto_cipher_ctx), + .cra_alignmask = 0, + .cra_type = &crypto_ablkcipher_type, + .cra_module = THIS_MODULE, + .cra_init = _qcrypto_cra_ablkcipher_init, + .cra_exit = _qcrypto_cra_ablkcipher_exit, + .cra_u = { + .ablkcipher = { + .ivsize = DES3_EDE_BLOCK_SIZE, + .min_keysize = DES3_EDE_KEY_SIZE, + .max_keysize = DES3_EDE_KEY_SIZE, + .setkey = _qcrypto_setkey_3des, + .encrypt = _qcrypto_enc_3des_cbc, + .decrypt = _qcrypto_dec_3des_cbc, + }, + }, + }, +}; + +static struct crypto_alg _qcrypto_ablk_cipher_xts_algo = { + .cra_name = "xts(aes)", + .cra_driver_name = "qcrypto-xts-aes", + .cra_priority = 300, + .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC, + .cra_blocksize = AES_BLOCK_SIZE, + .cra_ctxsize = sizeof(struct qcrypto_cipher_ctx), + .cra_alignmask = 0, + .cra_type = &crypto_ablkcipher_type, + .cra_module = THIS_MODULE, + .cra_init = _qcrypto_cra_ablkcipher_init, + .cra_exit = _qcrypto_cra_ablkcipher_exit, + .cra_u = { + .ablkcipher = { + .ivsize = AES_BLOCK_SIZE, + .min_keysize = AES_MIN_KEY_SIZE, + .max_keysize = AES_MAX_KEY_SIZE, + .setkey = _qcrypto_setkey_aes_xts, + .encrypt = _qcrypto_enc_aes_xts, + .decrypt = _qcrypto_dec_aes_xts, + }, + }, +}; + +static struct aead_alg _qcrypto_aead_sha1_hmac_algos[] = { + { + .base = { + .cra_name = "authenc(hmac(sha1),cbc(aes))", + .cra_driver_name = "qcrypto-aead-hmac-sha1-cbc-aes", + .cra_priority = 300, + .cra_flags = CRYPTO_ALG_ASYNC, + .cra_blocksize = AES_BLOCK_SIZE, + .cra_ctxsize = sizeof(struct qcrypto_cipher_ctx), + .cra_alignmask = 0, + .cra_module = THIS_MODULE, + }, + .ivsize = AES_BLOCK_SIZE, + .maxauthsize = SHA1_DIGEST_SIZE, + .setkey = _qcrypto_aead_setkey, + .setauthsize = _qcrypto_aead_setauthsize, + .encrypt = _qcrypto_aead_encrypt_aes_cbc, + .decrypt = _qcrypto_aead_decrypt_aes_cbc, + .init = _qcrypto_cra_aead_aes_sha1_init, + .exit = _qcrypto_cra_aead_aes_exit, + }, + { + .base = { + .cra_name = "authenc(hmac(sha1),cbc(des))", + .cra_driver_name = "qcrypto-aead-hmac-sha1-cbc-des", + .cra_priority = 300, + .cra_flags = CRYPTO_ALG_ASYNC, + .cra_blocksize = DES_BLOCK_SIZE, + .cra_ctxsize = sizeof(struct qcrypto_cipher_ctx), + .cra_alignmask = 0, + .cra_module = THIS_MODULE, + }, + .ivsize = DES_BLOCK_SIZE, + .maxauthsize = SHA1_DIGEST_SIZE, + .setkey = _qcrypto_aead_setkey, + .setauthsize = _qcrypto_aead_setauthsize, + .encrypt = _qcrypto_aead_encrypt_des_cbc, + .decrypt = _qcrypto_aead_decrypt_des_cbc, + .init = _qcrypto_cra_aead_sha1_init, + .exit = _qcrypto_cra_aead_exit, + }, + { + .base = { + .cra_name = "authenc(hmac(sha1),cbc(des3_ede))", + .cra_driver_name = "qcrypto-aead-hmac-sha1-cbc-3des", + .cra_priority = 300, + .cra_flags = CRYPTO_ALG_ASYNC, + .cra_blocksize = DES3_EDE_BLOCK_SIZE, + .cra_ctxsize = sizeof(struct qcrypto_cipher_ctx), + .cra_alignmask = 0, + .cra_module = THIS_MODULE, + }, + .ivsize = DES3_EDE_BLOCK_SIZE, + .maxauthsize = SHA1_DIGEST_SIZE, + .setkey = _qcrypto_aead_setkey, + .setauthsize = _qcrypto_aead_setauthsize, + .encrypt = _qcrypto_aead_encrypt_3des_cbc, + .decrypt = _qcrypto_aead_decrypt_3des_cbc, + .init = _qcrypto_cra_aead_sha1_init, + .exit = _qcrypto_cra_aead_exit, + }, +}; + +static struct aead_alg _qcrypto_aead_sha256_hmac_algos[] = { + { + .base = { + .cra_name = "authenc(hmac(sha256),cbc(aes))", + .cra_driver_name = "qcrypto-aead-hmac-sha256-cbc-aes", + .cra_priority = 300, + .cra_flags = CRYPTO_ALG_ASYNC, + .cra_blocksize = AES_BLOCK_SIZE, + .cra_ctxsize = sizeof(struct qcrypto_cipher_ctx), + .cra_alignmask = 0, + .cra_module = THIS_MODULE, + }, + .ivsize = AES_BLOCK_SIZE, + .maxauthsize = SHA256_DIGEST_SIZE, + .setkey = _qcrypto_aead_setkey, + .setauthsize = _qcrypto_aead_setauthsize, + .encrypt = _qcrypto_aead_encrypt_aes_cbc, + .decrypt = _qcrypto_aead_decrypt_aes_cbc, + .init = _qcrypto_cra_aead_aes_sha256_init, + .exit = _qcrypto_cra_aead_aes_exit, + }, + + { + .base = { + .cra_name = "authenc(hmac(sha256),cbc(des))", + .cra_driver_name = "qcrypto-aead-hmac-sha256-cbc-des", + .cra_priority = 300, + .cra_flags = CRYPTO_ALG_ASYNC, + .cra_blocksize = DES_BLOCK_SIZE, + .cra_ctxsize = sizeof(struct qcrypto_cipher_ctx), + .cra_alignmask = 0, + .cra_module = THIS_MODULE, + }, + .ivsize = DES_BLOCK_SIZE, + .maxauthsize = SHA256_DIGEST_SIZE, + .setkey = _qcrypto_aead_setkey, + .setauthsize = _qcrypto_aead_setauthsize, + .encrypt = _qcrypto_aead_encrypt_des_cbc, + .decrypt = _qcrypto_aead_decrypt_des_cbc, + .init = _qcrypto_cra_aead_sha256_init, + .exit = _qcrypto_cra_aead_exit, + }, + { + .base = { + .cra_name = "authenc(hmac(sha256),cbc(des3_ede))", + .cra_driver_name = "qcrypto-aead-hmac-sha256-cbc-3des", + .cra_priority = 300, + .cra_flags = CRYPTO_ALG_ASYNC, + .cra_blocksize = DES3_EDE_BLOCK_SIZE, + .cra_ctxsize = sizeof(struct qcrypto_cipher_ctx), + .cra_alignmask = 0, + .cra_module = THIS_MODULE, + }, + .ivsize = DES3_EDE_BLOCK_SIZE, + .maxauthsize = SHA256_DIGEST_SIZE, + .setkey = _qcrypto_aead_setkey, + .setauthsize = _qcrypto_aead_setauthsize, + .encrypt = _qcrypto_aead_encrypt_3des_cbc, + .decrypt = _qcrypto_aead_decrypt_3des_cbc, + .init = _qcrypto_cra_aead_sha256_init, + .exit = _qcrypto_cra_aead_exit, + }, +}; + +static struct aead_alg _qcrypto_aead_ccm_algo = { + .base = { + .cra_name = "ccm(aes)", + .cra_driver_name = "qcrypto-aes-ccm", + .cra_priority = 300, + .cra_flags = CRYPTO_ALG_ASYNC, + .cra_blocksize = AES_BLOCK_SIZE, + .cra_ctxsize = sizeof(struct qcrypto_cipher_ctx), + .cra_alignmask = 0, + .cra_module = THIS_MODULE, + }, + .ivsize = AES_BLOCK_SIZE, + .maxauthsize = AES_BLOCK_SIZE, + .setkey = _qcrypto_aead_ccm_setkey, + .setauthsize = _qcrypto_aead_ccm_setauthsize, + .encrypt = _qcrypto_aead_encrypt_aes_ccm, + .decrypt = _qcrypto_aead_decrypt_aes_ccm, + .init = _qcrypto_cra_aead_ccm_init, + .exit = _qcrypto_cra_aead_exit, +}; + +static struct aead_alg _qcrypto_aead_rfc4309_ccm_algo = { + .base = { + .cra_name = "rfc4309(ccm(aes))", + .cra_driver_name = "qcrypto-rfc4309-aes-ccm", + .cra_priority = 300, + .cra_flags = CRYPTO_ALG_ASYNC, + .cra_blocksize = 1, + .cra_ctxsize = sizeof(struct qcrypto_cipher_ctx), + .cra_alignmask = 0, + .cra_module = THIS_MODULE, + }, + .ivsize = 8, + .maxauthsize = 16, + .setkey = _qcrypto_aead_rfc4309_ccm_setkey, + .setauthsize = _qcrypto_aead_rfc4309_ccm_setauthsize, + .encrypt = _qcrypto_aead_rfc4309_enc_aes_ccm, + .decrypt = _qcrypto_aead_rfc4309_dec_aes_ccm, + .init = _qcrypto_cra_aead_rfc4309_ccm_init, + .exit = _qcrypto_cra_aead_exit, +}; + +static int _qcrypto_probe(struct platform_device *pdev) +{ + int rc = 0; + void *handle; + struct crypto_priv *cp = &qcrypto_dev; + int i; + struct msm_ce_hw_support *platform_support; + struct crypto_engine *pengine; + unsigned long flags; + struct qcrypto_req_control *pqcrypto_req_control = NULL; + + pengine = kzalloc(sizeof(*pengine), GFP_KERNEL); + if (!pengine) { + pr_err("qcrypto Memory allocation of q_alg FAIL, error %ld\n", + PTR_ERR(pengine)); + return -ENOMEM; + } + + /* open qce */ + handle = qce_open(pdev, &rc); + if (handle == NULL) { + kzfree(pengine); + platform_set_drvdata(pdev, NULL); + return rc; + } + + platform_set_drvdata(pdev, pengine); + pengine->qce = handle; + pengine->pcp = cp; + pengine->pdev = pdev; + pengine->signature = 0xdeadbeef; + + init_timer(&(pengine->bw_reaper_timer)); + INIT_WORK(&pengine->bw_reaper_ws, qcrypto_bw_reaper_work); + pengine->bw_reaper_timer.function = + qcrypto_bw_reaper_timer_callback; + INIT_WORK(&pengine->bw_allocate_ws, qcrypto_bw_allocate_work); + pengine->high_bw_req = false; + pengine->active_seq = 0; + pengine->last_active_seq = 0; + pengine->check_flag = false; + pengine->max_req_used = 0; + pengine->issue_req = false; + + crypto_init_queue(&pengine->req_queue, MSM_QCRYPTO_REQ_QUEUE_LENGTH); + + mutex_lock(&cp->engine_lock); + cp->total_units++; + pengine->unit = cp->total_units; + + spin_lock_irqsave(&cp->lock, flags); + pengine->first_engine = list_empty(&cp->engine_list); + if (pengine->first_engine) + cp->first_engine = pengine; + list_add_tail(&pengine->elist, &cp->engine_list); + cp->next_engine = pengine; + spin_unlock_irqrestore(&cp->lock, flags); + + qce_hw_support(pengine->qce, &cp->ce_support); + pengine->ce_hw_instance = cp->ce_support.ce_hw_instance; + pengine->max_req = cp->ce_support.max_request; + pqcrypto_req_control = kzalloc(sizeof(struct qcrypto_req_control) * + pengine->max_req, GFP_KERNEL); + if (pqcrypto_req_control == NULL) { + rc = -ENOMEM; + goto err; + } + qcrypto_init_req_control(pengine, pqcrypto_req_control); + if (cp->ce_support.bam) { + cp->platform_support.ce_shared = cp->ce_support.is_shared; + cp->platform_support.shared_ce_resource = 0; + cp->platform_support.hw_key_support = cp->ce_support.hw_key; + cp->platform_support.sha_hmac = 1; + + cp->platform_support.bus_scale_table = + (struct msm_bus_scale_pdata *) + msm_bus_cl_get_pdata(pdev); + if (!cp->platform_support.bus_scale_table) + pr_warn("bus_scale_table is NULL\n"); + + pengine->ce_device = cp->ce_support.ce_device; + + } else { + platform_support = + (struct msm_ce_hw_support *)pdev->dev.platform_data; + cp->platform_support.ce_shared = platform_support->ce_shared; + cp->platform_support.shared_ce_resource = + platform_support->shared_ce_resource; + cp->platform_support.hw_key_support = + platform_support->hw_key_support; + cp->platform_support.bus_scale_table = + platform_support->bus_scale_table; + cp->platform_support.sha_hmac = platform_support->sha_hmac; + } + + pengine->bus_scale_handle = 0; + + if (cp->platform_support.bus_scale_table != NULL) { + pengine->bus_scale_handle = + msm_bus_scale_register_client( + (struct msm_bus_scale_pdata *) + cp->platform_support.bus_scale_table); + if (!pengine->bus_scale_handle) { + pr_err("%s not able to get bus scale\n", + __func__); + rc = -ENOMEM; + goto err; + } + pengine->bw_state = BUS_NO_BANDWIDTH; + } else { + pengine->bw_state = BUS_HAS_BANDWIDTH; + } + + if (cp->total_units != 1) { + mutex_unlock(&cp->engine_lock); + return 0; + } + + /* register crypto cipher algorithms the device supports */ + for (i = 0; i < ARRAY_SIZE(_qcrypto_ablk_cipher_algos); i++) { + struct qcrypto_alg *q_alg; + + q_alg = _qcrypto_cipher_alg_alloc(cp, + &_qcrypto_ablk_cipher_algos[i]); + if (IS_ERR(q_alg)) { + rc = PTR_ERR(q_alg); + goto err; + } + if (cp->ce_support.use_sw_aes_cbc_ecb_ctr_algo) { + rc = _qcrypto_prefix_alg_cra_name( + q_alg->cipher_alg.cra_name, + strlen(q_alg->cipher_alg.cra_name)); + if (rc) { + dev_err(&pdev->dev, + "The algorithm name %s is too long.\n", + q_alg->cipher_alg.cra_name); + kfree(q_alg); + goto err; + } + } + rc = crypto_register_alg(&q_alg->cipher_alg); + if (rc) { + dev_err(&pdev->dev, "%s alg registration failed\n", + q_alg->cipher_alg.cra_driver_name); + kzfree(q_alg); + } else { + list_add_tail(&q_alg->entry, &cp->alg_list); + dev_info(&pdev->dev, "%s\n", + q_alg->cipher_alg.cra_driver_name); + } + } + + /* register crypto cipher algorithms the device supports */ + if (cp->ce_support.aes_xts) { + struct qcrypto_alg *q_alg; + + q_alg = _qcrypto_cipher_alg_alloc(cp, + &_qcrypto_ablk_cipher_xts_algo); + if (IS_ERR(q_alg)) { + rc = PTR_ERR(q_alg); + goto err; + } + if (cp->ce_support.use_sw_aes_xts_algo) { + rc = _qcrypto_prefix_alg_cra_name( + q_alg->cipher_alg.cra_name, + strlen(q_alg->cipher_alg.cra_name)); + if (rc) { + dev_err(&pdev->dev, + "The algorithm name %s is too long.\n", + q_alg->cipher_alg.cra_name); + kfree(q_alg); + goto err; + } + } + rc = crypto_register_alg(&q_alg->cipher_alg); + if (rc) { + dev_err(&pdev->dev, "%s alg registration failed\n", + q_alg->cipher_alg.cra_driver_name); + kzfree(q_alg); + } else { + list_add_tail(&q_alg->entry, &cp->alg_list); + dev_info(&pdev->dev, "%s\n", + q_alg->cipher_alg.cra_driver_name); + } + } + + /* + * Register crypto hash (sha1 and sha256) algorithms the + * device supports + */ + for (i = 0; i < ARRAY_SIZE(_qcrypto_ahash_algos); i++) { + struct qcrypto_alg *q_alg = NULL; + + q_alg = _qcrypto_sha_alg_alloc(cp, &_qcrypto_ahash_algos[i]); + + if (IS_ERR(q_alg)) { + rc = PTR_ERR(q_alg); + goto err; + } + if (cp->ce_support.use_sw_ahash_algo) { + rc = _qcrypto_prefix_alg_cra_name( + q_alg->sha_alg.halg.base.cra_name, + strlen(q_alg->sha_alg.halg.base.cra_name)); + if (rc) { + dev_err(&pdev->dev, + "The algorithm name %s is too long.\n", + q_alg->sha_alg.halg.base.cra_name); + kfree(q_alg); + goto err; + } + } + rc = crypto_register_ahash(&q_alg->sha_alg); + if (rc) { + dev_err(&pdev->dev, "%s alg registration failed\n", + q_alg->sha_alg.halg.base.cra_driver_name); + kzfree(q_alg); + } else { + list_add_tail(&q_alg->entry, &cp->alg_list); + dev_info(&pdev->dev, "%s\n", + q_alg->sha_alg.halg.base.cra_driver_name); + } + } + + /* register crypto aead (hmac-sha1) algorithms the device supports */ + if (cp->ce_support.sha1_hmac_20 || cp->ce_support.sha1_hmac + || cp->ce_support.sha_hmac) { + for (i = 0; i < ARRAY_SIZE(_qcrypto_aead_sha1_hmac_algos); + i++) { + struct qcrypto_alg *q_alg; + + q_alg = _qcrypto_aead_alg_alloc(cp, + &_qcrypto_aead_sha1_hmac_algos[i]); + if (IS_ERR(q_alg)) { + rc = PTR_ERR(q_alg); + goto err; + } + if (cp->ce_support.use_sw_aead_algo) { + rc = _qcrypto_prefix_alg_cra_name( + q_alg->aead_alg.base.cra_name, + strlen(q_alg->aead_alg.base.cra_name)); + if (rc) { + dev_err(&pdev->dev, + "The algorithm name %s is too long.\n", + q_alg->aead_alg.base.cra_name); + kfree(q_alg); + goto err; + } + } + rc = crypto_register_aead(&q_alg->aead_alg); + if (rc) { + dev_err(&pdev->dev, + "%s alg registration failed\n", + q_alg->aead_alg.base.cra_driver_name); + kfree(q_alg); + } else { + list_add_tail(&q_alg->entry, &cp->alg_list); + dev_info(&pdev->dev, "%s\n", + q_alg->aead_alg.base.cra_driver_name); + } + } + } + + /* register crypto aead (hmac-sha256) algorithms the device supports */ + if (cp->ce_support.sha_hmac) { + for (i = 0; i < ARRAY_SIZE(_qcrypto_aead_sha256_hmac_algos); + i++) { + struct qcrypto_alg *q_alg; + + q_alg = _qcrypto_aead_alg_alloc(cp, + &_qcrypto_aead_sha256_hmac_algos[i]); + if (IS_ERR(q_alg)) { + rc = PTR_ERR(q_alg); + goto err; + } + if (cp->ce_support.use_sw_aead_algo) { + rc = _qcrypto_prefix_alg_cra_name( + q_alg->aead_alg.base.cra_name, + strlen(q_alg->aead_alg.base.cra_name)); + if (rc) { + dev_err(&pdev->dev, + "The algorithm name %s is too long.\n", + q_alg->aead_alg.base.cra_name); + kfree(q_alg); + goto err; + } + } + rc = crypto_register_aead(&q_alg->aead_alg); + if (rc) { + dev_err(&pdev->dev, + "%s alg registration failed\n", + q_alg->aead_alg.base.cra_driver_name); + kfree(q_alg); + } else { + list_add_tail(&q_alg->entry, &cp->alg_list); + dev_info(&pdev->dev, "%s\n", + q_alg->aead_alg.base.cra_driver_name); + } + } + } + + if ((cp->ce_support.sha_hmac) || (cp->platform_support.sha_hmac)) { + /* register crypto hmac algorithms the device supports */ + for (i = 0; i < ARRAY_SIZE(_qcrypto_sha_hmac_algos); i++) { + struct qcrypto_alg *q_alg = NULL; + + q_alg = _qcrypto_sha_alg_alloc(cp, + &_qcrypto_sha_hmac_algos[i]); + + if (IS_ERR(q_alg)) { + rc = PTR_ERR(q_alg); + goto err; + } + if (cp->ce_support.use_sw_hmac_algo) { + rc = _qcrypto_prefix_alg_cra_name( + q_alg->sha_alg.halg.base.cra_name, + strlen( + q_alg->sha_alg.halg.base.cra_name)); + if (rc) { + dev_err(&pdev->dev, + "The algorithm name %s is too long.\n", + q_alg->sha_alg.halg.base.cra_name); + kfree(q_alg); + goto err; + } + } + rc = crypto_register_ahash(&q_alg->sha_alg); + if (rc) { + dev_err(&pdev->dev, + "%s alg registration failed\n", + q_alg->sha_alg.halg.base.cra_driver_name); + kzfree(q_alg); + } else { + list_add_tail(&q_alg->entry, &cp->alg_list); + dev_info(&pdev->dev, "%s\n", + q_alg->sha_alg.halg.base.cra_driver_name); + } + } + } + /* + * Register crypto cipher (aes-ccm) algorithms the + * device supports + */ + if (cp->ce_support.aes_ccm) { + struct qcrypto_alg *q_alg; + + q_alg = _qcrypto_aead_alg_alloc(cp, &_qcrypto_aead_ccm_algo); + if (IS_ERR(q_alg)) { + rc = PTR_ERR(q_alg); + goto err; + } + if (cp->ce_support.use_sw_aes_ccm_algo) { + rc = _qcrypto_prefix_alg_cra_name( + q_alg->aead_alg.base.cra_name, + strlen(q_alg->aead_alg.base.cra_name)); + if (rc) { + dev_err(&pdev->dev, + "The algorithm name %s is too long.\n", + q_alg->aead_alg.base.cra_name); + kfree(q_alg); + goto err; + } + } + rc = crypto_register_aead(&q_alg->aead_alg); + if (rc) { + dev_err(&pdev->dev, "%s alg registration failed\n", + q_alg->aead_alg.base.cra_driver_name); + kzfree(q_alg); + } else { + list_add_tail(&q_alg->entry, &cp->alg_list); + dev_info(&pdev->dev, "%s\n", + q_alg->aead_alg.base.cra_driver_name); + } + + q_alg = _qcrypto_aead_alg_alloc(cp, + &_qcrypto_aead_rfc4309_ccm_algo); + if (IS_ERR(q_alg)) { + rc = PTR_ERR(q_alg); + goto err; + } + + if (cp->ce_support.use_sw_aes_ccm_algo) { + rc = _qcrypto_prefix_alg_cra_name( + q_alg->aead_alg.base.cra_name, + strlen(q_alg->aead_alg.base.cra_name)); + if (rc) { + dev_err(&pdev->dev, + "The algorithm name %s is too long.\n", + q_alg->aead_alg.base.cra_name); + kfree(q_alg); + goto err; + } + } + rc = crypto_register_aead(&q_alg->aead_alg); + if (rc) { + dev_err(&pdev->dev, "%s alg registration failed\n", + q_alg->aead_alg.base.cra_driver_name); + kfree(q_alg); + } else { + list_add_tail(&q_alg->entry, &cp->alg_list); + dev_info(&pdev->dev, "%s\n", + q_alg->aead_alg.base.cra_driver_name); + } + } + mutex_unlock(&cp->engine_lock); + + + return 0; +err: + _qcrypto_remove_engine(pengine); + mutex_unlock(&cp->engine_lock); + if (pengine->qce) + qce_close(pengine->qce); + kzfree(pengine); + return rc; +}; + +static int _qcrypto_engine_in_use(struct crypto_engine *pengine) +{ + struct crypto_priv *cp = pengine->pcp; + + if ((atomic_read(&pengine->req_count) > 0) || pengine->req_queue.qlen + || cp->req_queue.qlen) + return 1; + return 0; +} + +static void _qcrypto_do_suspending(struct crypto_engine *pengine) +{ + struct crypto_priv *cp = pengine->pcp; + + if (cp->platform_support.bus_scale_table == NULL) + return; + del_timer_sync(&pengine->bw_reaper_timer); + qcrypto_ce_set_bus(pengine, false); +} + +static int _qcrypto_suspend(struct platform_device *pdev, pm_message_t state) +{ + int ret = 0; + struct crypto_engine *pengine; + struct crypto_priv *cp; + unsigned long flags; + + pengine = platform_get_drvdata(pdev); + if (!pengine) + return -EINVAL; + + /* + * Check if this platform supports clock management in suspend/resume + * If not, just simply return 0. + */ + cp = pengine->pcp; + if (!cp->ce_support.clk_mgmt_sus_res) + return 0; + spin_lock_irqsave(&cp->lock, flags); + switch (pengine->bw_state) { + case BUS_NO_BANDWIDTH: + if (pengine->high_bw_req == false) + pengine->bw_state = BUS_SUSPENDED; + else + ret = -EBUSY; + break; + case BUS_HAS_BANDWIDTH: + if (_qcrypto_engine_in_use(pengine)) { + ret = -EBUSY; + } else { + pengine->bw_state = BUS_SUSPENDING; + spin_unlock_irqrestore(&cp->lock, flags); + _qcrypto_do_suspending(pengine); + spin_lock_irqsave(&cp->lock, flags); + pengine->bw_state = BUS_SUSPENDED; + } + break; + case BUS_BANDWIDTH_RELEASING: + case BUS_BANDWIDTH_ALLOCATING: + case BUS_SUSPENDED: + case BUS_SUSPENDING: + default: + ret = -EBUSY; + break; + } + + spin_unlock_irqrestore(&cp->lock, flags); + if (ret) + return ret; + else { + if (qce_pm_table.suspend) + qce_pm_table.suspend(pengine->qce); + return 0; + } +} + +static int _qcrypto_resume(struct platform_device *pdev) +{ + struct crypto_engine *pengine; + struct crypto_priv *cp; + unsigned long flags; + int ret = 0; + + pengine = platform_get_drvdata(pdev); + + if (!pengine) + return -EINVAL; + cp = pengine->pcp; + if (!cp->ce_support.clk_mgmt_sus_res) + return 0; + spin_lock_irqsave(&cp->lock, flags); + if (pengine->bw_state == BUS_SUSPENDED) { + spin_unlock_irqrestore(&cp->lock, flags); + if (qce_pm_table.resume) + qce_pm_table.resume(pengine->qce); + + spin_lock_irqsave(&cp->lock, flags); + pengine->bw_state = BUS_NO_BANDWIDTH; + pengine->active_seq++; + pengine->check_flag = false; + if (cp->req_queue.qlen || pengine->req_queue.qlen) { + if (pengine->high_bw_req == false) { + qcrypto_ce_bw_allocate_req(pengine); + pengine->high_bw_req = true; + } + } + } else + ret = -EBUSY; + + spin_unlock_irqrestore(&cp->lock, flags); + return ret; +} + +static struct of_device_id qcrypto_match[] = { + { .compatible = "qcom,qcrypto", + }, + {} +}; + +static struct platform_driver _qualcomm_crypto = { + .probe = _qcrypto_probe, + .remove = _qcrypto_remove, + .suspend = _qcrypto_suspend, + .resume = _qcrypto_resume, + .driver = { + .owner = THIS_MODULE, + .name = "qcrypto", + .of_match_table = qcrypto_match, + }, +}; + +static int _debug_qcrypto; + +static int _debug_stats_open(struct inode *inode, struct file *file) +{ + file->private_data = inode->i_private; + return 0; +} + +static ssize_t _debug_stats_read(struct file *file, char __user *buf, + size_t count, loff_t *ppos) +{ + int rc = -EINVAL; + int qcrypto = *((int *) file->private_data); + int len; + + len = _disp_stats(qcrypto); + + if (len <= count) + rc = simple_read_from_buffer((void __user *) buf, len, + ppos, (void *) _debug_read_buf, len); + return rc; +} + +static ssize_t _debug_stats_write(struct file *file, const char __user *buf, + size_t count, loff_t *ppos) +{ + unsigned long flags; + struct crypto_priv *cp = &qcrypto_dev; + struct crypto_engine *pe; + int i; + + memset((char *)&_qcrypto_stat, 0, sizeof(struct crypto_stat)); + spin_lock_irqsave(&cp->lock, flags); + list_for_each_entry(pe, &cp->engine_list, elist) { + pe->total_req = 0; + pe->err_req = 0; + qce_clear_driver_stats(pe->qce); + pe->max_req_used = 0; + } + cp->max_qlen = 0; + cp->resp_start = 0; + cp->resp_stop = 0; + cp->no_avail = 0; + cp->max_resp_qlen = 0; + cp->queue_work_eng3 = 0; + cp->queue_work_not_eng3 = 0; + cp->queue_work_not_eng3_nz = 0; + cp->max_reorder_cnt = 0; + for (i = 0; i < MAX_SMP_CPU + 1; i++) + cp->cpu_req[i] = 0; + spin_unlock_irqrestore(&cp->lock, flags); + return count; +} + +static const struct file_operations _debug_stats_ops = { + .open = _debug_stats_open, + .read = _debug_stats_read, + .write = _debug_stats_write, +}; + +static int _qcrypto_debug_init(void) +{ + int rc; + char name[DEBUG_MAX_FNAME]; + struct dentry *dent; + + _debug_dent = debugfs_create_dir("qcrypto", NULL); + if (IS_ERR(_debug_dent)) { + pr_err("qcrypto debugfs_create_dir fail, error %ld\n", + PTR_ERR(_debug_dent)); + return PTR_ERR(_debug_dent); + } + + snprintf(name, DEBUG_MAX_FNAME-1, "stats-%d", 1); + _debug_qcrypto = 0; + dent = debugfs_create_file(name, 0644, _debug_dent, + &_debug_qcrypto, &_debug_stats_ops); + if (dent == NULL) { + pr_err("qcrypto debugfs_create_file fail, error %ld\n", + PTR_ERR(dent)); + rc = PTR_ERR(dent); + goto err; + } + return 0; +err: + debugfs_remove_recursive(_debug_dent); + return rc; +} + +static int __init _qcrypto_init(void) +{ + int rc; + struct crypto_priv *pcp = &qcrypto_dev; + + rc = _qcrypto_debug_init(); + if (rc) + return rc; + INIT_LIST_HEAD(&pcp->alg_list); + INIT_LIST_HEAD(&pcp->engine_list); + init_llist_head(&pcp->ordered_resp_list); + spin_lock_init(&pcp->lock); + mutex_init(&pcp->engine_lock); + pcp->resp_wq = alloc_workqueue("qcrypto_seq_response_wq", + WQ_MEM_RECLAIM | WQ_HIGHPRI | WQ_CPU_INTENSIVE, 1); + if (!pcp->resp_wq) { + pr_err("Error allocating workqueue\n"); + return -ENOMEM; + } + INIT_WORK(&pcp->resp_work, seq_response); + pcp->total_units = 0; + pcp->platform_support.bus_scale_table = NULL; + pcp->next_engine = NULL; + pcp->scheduled_eng = NULL; + pcp->ce_req_proc_sts = IN_PROGRESS; + crypto_init_queue(&pcp->req_queue, MSM_QCRYPTO_REQ_QUEUE_LENGTH); + return platform_driver_register(&_qualcomm_crypto); +} + +static void __exit _qcrypto_exit(void) +{ + pr_debug("%s Unregister QCRYPTO\n", __func__); + debugfs_remove_recursive(_debug_dent); + platform_driver_unregister(&_qualcomm_crypto); +} + +module_init(_qcrypto_init); +module_exit(_qcrypto_exit); + +MODULE_LICENSE("GPL v2"); +MODULE_DESCRIPTION("Qualcomm Crypto driver"); diff -Nruw linux-4.4.115-fbx/drivers/crypto/msm./qcryptohw_50.h linux-4.4.115-fbx/drivers/crypto/msm/qcryptohw_50.h --- linux-4.4.115-fbx/drivers/crypto/msm./qcryptohw_50.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-4.4.115-fbx/drivers/crypto/msm/qcryptohw_50.h 2019-01-22 16:16:23.115242893 +0100 @@ -0,0 +1,528 @@ +/* Copyright (c) 2012-2014, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _DRIVERS_CRYPTO_MSM_QCRYPTOHW_50_H_ +#define _DRIVERS_CRYPTO_MSM_QCRYPTOHW_50_H_ + + +#define CRYPTO_BAM_CNFG_BITS_REG 0x0007C +#define CRYPTO_BAM_CD_ENABLE 27 +#define CRYPTO_BAM_CD_ENABLE_MASK (1 << CRYPTO_BAM_CD_ENABLE) + +#define QCE_AUTH_REG_BYTE_COUNT 4 +#define CRYPTO_VERSION_REG 0x1A000 + +#define CRYPTO_DATA_IN0_REG 0x1A010 +#define CRYPTO_DATA_IN1_REG 0x1A014 +#define CRYPTO_DATA_IN2_REG 0x1A018 +#define CRYPTO_DATA_IN3_REG 0x1A01C + +#define CRYPTO_DATA_OUT0_REG 0x1A020 +#define CRYPTO_DATA_OUT1_REG 0x1A024 +#define CRYPTO_DATA_OUT2_REG 0x1A028 +#define CRYPTO_DATA_OUT3_REG 0x1A02C + +#define CRYPTO_STATUS_REG 0x1A100 +#define CRYPTO_STATUS2_REG 0x1A104 +#define CRYPTO_ENGINES_AVAIL 0x1A108 +#define CRYPTO_FIFO_SIZES_REG 0x1A10C + +#define CRYPTO_SEG_SIZE_REG 0x1A110 +#define CRYPTO_GOPROC_REG 0x1A120 +#define CRYPTO_GOPROC_QC_KEY_REG 0x1B000 +#define CRYPTO_GOPROC_OEM_KEY_REG 0x1C000 + +#define CRYPTO_ENCR_SEG_CFG_REG 0x1A200 +#define CRYPTO_ENCR_SEG_SIZE_REG 0x1A204 +#define CRYPTO_ENCR_SEG_START_REG 0x1A208 + +#define CRYPTO_ENCR_KEY0_REG 0x1D000 +#define CRYPTO_ENCR_KEY1_REG 0x1D004 +#define CRYPTO_ENCR_KEY2_REG 0x1D008 +#define CRYPTO_ENCR_KEY3_REG 0x1D00C +#define CRYPTO_ENCR_KEY4_REG 0x1D010 +#define CRYPTO_ENCR_KEY5_REG 0x1D014 +#define CRYPTO_ENCR_KEY6_REG 0x1D018 +#define CRYPTO_ENCR_KEY7_REG 0x1D01C + +#define CRYPTO_ENCR_XTS_KEY0_REG 0x1D020 +#define CRYPTO_ENCR_XTS_KEY1_REG 0x1D024 +#define CRYPTO_ENCR_XTS_KEY2_REG 0x1D028 +#define CRYPTO_ENCR_XTS_KEY3_REG 0x1D02C +#define CRYPTO_ENCR_XTS_KEY4_REG 0x1D030 +#define CRYPTO_ENCR_XTS_KEY5_REG 0x1D034 +#define CRYPTO_ENCR_XTS_KEY6_REG 0x1D038 +#define CRYPTO_ENCR_XTS_KEY7_REG 0x1D03C + +#define CRYPTO_ENCR_PIPE0_KEY0_REG 0x1E000 +#define CRYPTO_ENCR_PIPE0_KEY1_REG 0x1E004 +#define CRYPTO_ENCR_PIPE0_KEY2_REG 0x1E008 +#define CRYPTO_ENCR_PIPE0_KEY3_REG 0x1E00C +#define CRYPTO_ENCR_PIPE0_KEY4_REG 0x1E010 +#define CRYPTO_ENCR_PIPE0_KEY5_REG 0x1E014 +#define CRYPTO_ENCR_PIPE0_KEY6_REG 0x1E018 +#define CRYPTO_ENCR_PIPE0_KEY7_REG 0x1E01C + +#define CRYPTO_ENCR_PIPE1_KEY0_REG 0x1E020 +#define CRYPTO_ENCR_PIPE1_KEY1_REG 0x1E024 +#define CRYPTO_ENCR_PIPE1_KEY2_REG 0x1E028 +#define CRYPTO_ENCR_PIPE1_KEY3_REG 0x1E02C +#define CRYPTO_ENCR_PIPE1_KEY4_REG 0x1E030 +#define CRYPTO_ENCR_PIPE1_KEY5_REG 0x1E034 +#define CRYPTO_ENCR_PIPE1_KEY6_REG 0x1E038 +#define CRYPTO_ENCR_PIPE1_KEY7_REG 0x1E03C + +#define CRYPTO_ENCR_PIPE2_KEY0_REG 0x1E040 +#define CRYPTO_ENCR_PIPE2_KEY1_REG 0x1E044 +#define CRYPTO_ENCR_PIPE2_KEY2_REG 0x1E048 +#define CRYPTO_ENCR_PIPE2_KEY3_REG 0x1E04C +#define CRYPTO_ENCR_PIPE2_KEY4_REG 0x1E050 +#define CRYPTO_ENCR_PIPE2_KEY5_REG 0x1E054 +#define CRYPTO_ENCR_PIPE2_KEY6_REG 0x1E058 +#define CRYPTO_ENCR_PIPE2_KEY7_REG 0x1E05C + +#define CRYPTO_ENCR_PIPE3_KEY0_REG 0x1E060 +#define CRYPTO_ENCR_PIPE3_KEY1_REG 0x1E064 +#define CRYPTO_ENCR_PIPE3_KEY2_REG 0x1E068 +#define CRYPTO_ENCR_PIPE3_KEY3_REG 0x1E06C +#define CRYPTO_ENCR_PIPE3_KEY4_REG 0x1E070 +#define CRYPTO_ENCR_PIPE3_KEY5_REG 0x1E074 +#define CRYPTO_ENCR_PIPE3_KEY6_REG 0x1E078 +#define CRYPTO_ENCR_PIPE3_KEY7_REG 0x1E07C + + +#define CRYPTO_ENCR_PIPE0_XTS_KEY0_REG 0x1E200 +#define CRYPTO_ENCR_PIPE0_XTS_KEY1_REG 0x1E204 +#define CRYPTO_ENCR_PIPE0_XTS_KEY2_REG 0x1E208 +#define CRYPTO_ENCR_PIPE0_XTS_KEY3_REG 0x1E20C +#define CRYPTO_ENCR_PIPE0_XTS_KEY4_REG 0x1E210 +#define CRYPTO_ENCR_PIPE0_XTS_KEY5_REG 0x1E214 +#define CRYPTO_ENCR_PIPE0_XTS_KEY6_REG 0x1E218 +#define CRYPTO_ENCR_PIPE0_XTS_KEY7_REG 0x1E21C + +#define CRYPTO_ENCR_PIPE1_XTS_KEY0_REG 0x1E220 +#define CRYPTO_ENCR_PIPE1_XTS_KEY1_REG 0x1E224 +#define CRYPTO_ENCR_PIPE1_XTS_KEY2_REG 0x1E228 +#define CRYPTO_ENCR_PIPE1_XTS_KEY3_REG 0x1E22C +#define CRYPTO_ENCR_PIPE1_XTS_KEY4_REG 0x1E230 +#define CRYPTO_ENCR_PIPE1_XTS_KEY5_REG 0x1E234 +#define CRYPTO_ENCR_PIPE1_XTS_KEY6_REG 0x1E238 +#define CRYPTO_ENCR_PIPE1_XTS_KEY7_REG 0x1E23C + +#define CRYPTO_ENCR_PIPE2_XTS_KEY0_REG 0x1E240 +#define CRYPTO_ENCR_PIPE2_XTS_KEY1_REG 0x1E244 +#define CRYPTO_ENCR_PIPE2_XTS_KEY2_REG 0x1E248 +#define CRYPTO_ENCR_PIPE2_XTS_KEY3_REG 0x1E24C +#define CRYPTO_ENCR_PIPE2_XTS_KEY4_REG 0x1E250 +#define CRYPTO_ENCR_PIPE2_XTS_KEY5_REG 0x1E254 +#define CRYPTO_ENCR_PIPE2_XTS_KEY6_REG 0x1E258 +#define CRYPTO_ENCR_PIPE2_XTS_KEY7_REG 0x1E25C + +#define CRYPTO_ENCR_PIPE3_XTS_KEY0_REG 0x1E260 +#define CRYPTO_ENCR_PIPE3_XTS_KEY1_REG 0x1E264 +#define CRYPTO_ENCR_PIPE3_XTS_KEY2_REG 0x1E268 +#define CRYPTO_ENCR_PIPE3_XTS_KEY3_REG 0x1E26C +#define CRYPTO_ENCR_PIPE3_XTS_KEY4_REG 0x1E270 +#define CRYPTO_ENCR_PIPE3_XTS_KEY5_REG 0x1E274 +#define CRYPTO_ENCR_PIPE3_XTS_KEY6_REG 0x1E278 +#define CRYPTO_ENCR_PIPE3_XTS_KEY7_REG 0x1E27C + + +#define CRYPTO_CNTR0_IV0_REG 0x1A20C +#define CRYPTO_CNTR1_IV1_REG 0x1A210 +#define CRYPTO_CNTR2_IV2_REG 0x1A214 +#define CRYPTO_CNTR3_IV3_REG 0x1A218 + +#define CRYPTO_CNTR_MASK_REG0 0x1A23C +#define CRYPTO_CNTR_MASK_REG1 0x1A238 +#define CRYPTO_CNTR_MASK_REG2 0x1A234 +#define CRYPTO_CNTR_MASK_REG 0x1A21C + +#define CRYPTO_ENCR_CCM_INT_CNTR0_REG 0x1A220 +#define CRYPTO_ENCR_CCM_INT_CNTR1_REG 0x1A224 +#define CRYPTO_ENCR_CCM_INT_CNTR2_REG 0x1A228 +#define CRYPTO_ENCR_CCM_INT_CNTR3_REG 0x1A22C + +#define CRYPTO_ENCR_XTS_DU_SIZE_REG 0x1A230 + +#define CRYPTO_AUTH_SEG_CFG_REG 0x1A300 +#define CRYPTO_AUTH_SEG_SIZE_REG 0x1A304 +#define CRYPTO_AUTH_SEG_START_REG 0x1A308 + +#define CRYPTO_AUTH_KEY0_REG 0x1D040 +#define CRYPTO_AUTH_KEY1_REG 0x1D044 +#define CRYPTO_AUTH_KEY2_REG 0x1D048 +#define CRYPTO_AUTH_KEY3_REG 0x1D04C +#define CRYPTO_AUTH_KEY4_REG 0x1D050 +#define CRYPTO_AUTH_KEY5_REG 0x1D054 +#define CRYPTO_AUTH_KEY6_REG 0x1D058 +#define CRYPTO_AUTH_KEY7_REG 0x1D05C +#define CRYPTO_AUTH_KEY8_REG 0x1D060 +#define CRYPTO_AUTH_KEY9_REG 0x1D064 +#define CRYPTO_AUTH_KEY10_REG 0x1D068 +#define CRYPTO_AUTH_KEY11_REG 0x1D06C +#define CRYPTO_AUTH_KEY12_REG 0x1D070 +#define CRYPTO_AUTH_KEY13_REG 0x1D074 +#define CRYPTO_AUTH_KEY14_REG 0x1D078 +#define CRYPTO_AUTH_KEY15_REG 0x1D07C + +#define CRYPTO_AUTH_PIPE0_KEY0_REG 0x1E800 +#define CRYPTO_AUTH_PIPE0_KEY1_REG 0x1E804 +#define CRYPTO_AUTH_PIPE0_KEY2_REG 0x1E808 +#define CRYPTO_AUTH_PIPE0_KEY3_REG 0x1E80C +#define CRYPTO_AUTH_PIPE0_KEY4_REG 0x1E810 +#define CRYPTO_AUTH_PIPE0_KEY5_REG 0x1E814 +#define CRYPTO_AUTH_PIPE0_KEY6_REG 0x1E818 +#define CRYPTO_AUTH_PIPE0_KEY7_REG 0x1E81C +#define CRYPTO_AUTH_PIPE0_KEY8_REG 0x1E820 +#define CRYPTO_AUTH_PIPE0_KEY9_REG 0x1E824 +#define CRYPTO_AUTH_PIPE0_KEY10_REG 0x1E828 +#define CRYPTO_AUTH_PIPE0_KEY11_REG 0x1E82C +#define CRYPTO_AUTH_PIPE0_KEY12_REG 0x1E830 +#define CRYPTO_AUTH_PIPE0_KEY13_REG 0x1E834 +#define CRYPTO_AUTH_PIPE0_KEY14_REG 0x1E838 +#define CRYPTO_AUTH_PIPE0_KEY15_REG 0x1E83C + +#define CRYPTO_AUTH_PIPE1_KEY0_REG 0x1E880 +#define CRYPTO_AUTH_PIPE1_KEY1_REG 0x1E884 +#define CRYPTO_AUTH_PIPE1_KEY2_REG 0x1E888 +#define CRYPTO_AUTH_PIPE1_KEY3_REG 0x1E88C +#define CRYPTO_AUTH_PIPE1_KEY4_REG 0x1E890 +#define CRYPTO_AUTH_PIPE1_KEY5_REG 0x1E894 +#define CRYPTO_AUTH_PIPE1_KEY6_REG 0x1E898 +#define CRYPTO_AUTH_PIPE1_KEY7_REG 0x1E89C +#define CRYPTO_AUTH_PIPE1_KEY8_REG 0x1E8A0 +#define CRYPTO_AUTH_PIPE1_KEY9_REG 0x1E8A4 +#define CRYPTO_AUTH_PIPE1_KEY10_REG 0x1E8A8 +#define CRYPTO_AUTH_PIPE1_KEY11_REG 0x1E8AC +#define CRYPTO_AUTH_PIPE1_KEY12_REG 0x1E8B0 +#define CRYPTO_AUTH_PIPE1_KEY13_REG 0x1E8B4 +#define CRYPTO_AUTH_PIPE1_KEY14_REG 0x1E8B8 +#define CRYPTO_AUTH_PIPE1_KEY15_REG 0x1E8BC + +#define CRYPTO_AUTH_PIPE2_KEY0_REG 0x1E900 +#define CRYPTO_AUTH_PIPE2_KEY1_REG 0x1E904 +#define CRYPTO_AUTH_PIPE2_KEY2_REG 0x1E908 +#define CRYPTO_AUTH_PIPE2_KEY3_REG 0x1E90C +#define CRYPTO_AUTH_PIPE2_KEY4_REG 0x1E910 +#define CRYPTO_AUTH_PIPE2_KEY5_REG 0x1E914 +#define CRYPTO_AUTH_PIPE2_KEY6_REG 0x1E918 +#define CRYPTO_AUTH_PIPE2_KEY7_REG 0x1E91C +#define CRYPTO_AUTH_PIPE2_KEY8_REG 0x1E920 +#define CRYPTO_AUTH_PIPE2_KEY9_REG 0x1E924 +#define CRYPTO_AUTH_PIPE2_KEY10_REG 0x1E928 +#define CRYPTO_AUTH_PIPE2_KEY11_REG 0x1E92C +#define CRYPTO_AUTH_PIPE2_KEY12_REG 0x1E930 +#define CRYPTO_AUTH_PIPE2_KEY13_REG 0x1E934 +#define CRYPTO_AUTH_PIPE2_KEY14_REG 0x1E938 +#define CRYPTO_AUTH_PIPE2_KEY15_REG 0x1E93C + +#define CRYPTO_AUTH_PIPE3_KEY0_REG 0x1E980 +#define CRYPTO_AUTH_PIPE3_KEY1_REG 0x1E984 +#define CRYPTO_AUTH_PIPE3_KEY2_REG 0x1E988 +#define CRYPTO_AUTH_PIPE3_KEY3_REG 0x1E98C +#define CRYPTO_AUTH_PIPE3_KEY4_REG 0x1E990 +#define CRYPTO_AUTH_PIPE3_KEY5_REG 0x1E994 +#define CRYPTO_AUTH_PIPE3_KEY6_REG 0x1E998 +#define CRYPTO_AUTH_PIPE3_KEY7_REG 0x1E99C +#define CRYPTO_AUTH_PIPE3_KEY8_REG 0x1E9A0 +#define CRYPTO_AUTH_PIPE3_KEY9_REG 0x1E9A4 +#define CRYPTO_AUTH_PIPE3_KEY10_REG 0x1E9A8 +#define CRYPTO_AUTH_PIPE3_KEY11_REG 0x1E9AC +#define CRYPTO_AUTH_PIPE3_KEY12_REG 0x1E9B0 +#define CRYPTO_AUTH_PIPE3_KEY13_REG 0x1E9B4 +#define CRYPTO_AUTH_PIPE3_KEY14_REG 0x1E9B8 +#define CRYPTO_AUTH_PIPE3_KEY15_REG 0x1E9BC + + +#define CRYPTO_AUTH_IV0_REG 0x1A310 +#define CRYPTO_AUTH_IV1_REG 0x1A314 +#define CRYPTO_AUTH_IV2_REG 0x1A318 +#define CRYPTO_AUTH_IV3_REG 0x1A31C +#define CRYPTO_AUTH_IV4_REG 0x1A320 +#define CRYPTO_AUTH_IV5_REG 0x1A324 +#define CRYPTO_AUTH_IV6_REG 0x1A328 +#define CRYPTO_AUTH_IV7_REG 0x1A32C +#define CRYPTO_AUTH_IV8_REG 0x1A330 +#define CRYPTO_AUTH_IV9_REG 0x1A334 +#define CRYPTO_AUTH_IV10_REG 0x1A338 +#define CRYPTO_AUTH_IV11_REG 0x1A33C +#define CRYPTO_AUTH_IV12_REG 0x1A340 +#define CRYPTO_AUTH_IV13_REG 0x1A344 +#define CRYPTO_AUTH_IV14_REG 0x1A348 +#define CRYPTO_AUTH_IV15_REG 0x1A34C + +#define CRYPTO_AUTH_INFO_NONCE0_REG 0x1A350 +#define CRYPTO_AUTH_INFO_NONCE1_REG 0x1A354 +#define CRYPTO_AUTH_INFO_NONCE2_REG 0x1A358 +#define CRYPTO_AUTH_INFO_NONCE3_REG 0x1A35C + +#define CRYPTO_AUTH_BYTECNT0_REG 0x1A390 +#define CRYPTO_AUTH_BYTECNT1_REG 0x1A394 +#define CRYPTO_AUTH_BYTECNT2_REG 0x1A398 +#define CRYPTO_AUTH_BYTECNT3_REG 0x1A39C + +#define CRYPTO_AUTH_EXP_MAC0_REG 0x1A3A0 +#define CRYPTO_AUTH_EXP_MAC1_REG 0x1A3A4 +#define CRYPTO_AUTH_EXP_MAC2_REG 0x1A3A8 +#define CRYPTO_AUTH_EXP_MAC3_REG 0x1A3AC +#define CRYPTO_AUTH_EXP_MAC4_REG 0x1A3B0 +#define CRYPTO_AUTH_EXP_MAC5_REG 0x1A3B4 +#define CRYPTO_AUTH_EXP_MAC6_REG 0x1A3B8 +#define CRYPTO_AUTH_EXP_MAC7_REG 0x1A3BC + +#define CRYPTO_CONFIG_REG 0x1A400 +#define CRYPTO_DEBUG_ENABLE_REG 0x1AF00 +#define CRYPTO_DEBUG_REG 0x1AF04 + + + +/* Register bits */ +#define CRYPTO_CORE_STEP_REV_MASK 0xFFFF +#define CRYPTO_CORE_STEP_REV 0 /* bit 15-0 */ +#define CRYPTO_CORE_MAJOR_REV_MASK 0xFF000000 +#define CRYPTO_CORE_MAJOR_REV 24 /* bit 31-24 */ +#define CRYPTO_CORE_MINOR_REV_MASK 0xFF0000 +#define CRYPTO_CORE_MINOR_REV 16 /* bit 23-16 */ + +/* status reg */ +#define CRYPTO_MAC_FAILED 31 +#define CRYPTO_DOUT_SIZE_AVAIL 26 /* bit 30-26 */ +#define CRYPTO_DOUT_SIZE_AVAIL_MASK (0x1F << CRYPTO_DOUT_SIZE_AVAIL) +#define CRYPTO_DIN_SIZE_AVAIL 21 /* bit 21-25 */ +#define CRYPTO_DIN_SIZE_AVAIL_MASK (0x1F << CRYPTO_DIN_SIZE_AVAIL) +#define CRYPTO_HSD_ERR 20 +#define CRYPTO_ACCESS_VIOL 19 +#define CRYPTO_PIPE_ACTIVE_ERR 18 +#define CRYPTO_CFG_CHNG_ERR 17 +#define CRYPTO_DOUT_ERR 16 +#define CRYPTO_DIN_ERR 15 +#define CRYPTO_AXI_ERR 14 +#define CRYPTO_CRYPTO_STATE 10 /* bit 13-10 */ +#define CRYPTO_CRYPTO_STATE_MASK (0xF << CRYPTO_CRYPTO_STATE) +#define CRYPTO_ENCR_BUSY 9 +#define CRYPTO_AUTH_BUSY 8 +#define CRYPTO_DOUT_INTR 7 +#define CRYPTO_DIN_INTR 6 +#define CRYPTO_OP_DONE_INTR 5 +#define CRYPTO_ERR_INTR 4 +#define CRYPTO_DOUT_RDY 3 +#define CRYPTO_DIN_RDY 2 +#define CRYPTO_OPERATION_DONE 1 +#define CRYPTO_SW_ERR 0 + +/* status2 reg */ +#define CRYPTO_AXI_EXTRA 1 +#define CRYPTO_LOCKED 2 + +/* config reg */ +#define CRYPTO_REQ_SIZE 17 /* bit 20-17 */ +#define CRYPTO_REQ_SIZE_MASK (0xF << CRYPTO_REQ_SIZE) +#define CRYPTO_REQ_SIZE_ENUM_1_BEAT 0 +#define CRYPTO_REQ_SIZE_ENUM_2_BEAT 1 +#define CRYPTO_REQ_SIZE_ENUM_3_BEAT 2 +#define CRYPTO_REQ_SIZE_ENUM_4_BEAT 3 +#define CRYPTO_REQ_SIZE_ENUM_5_BEAT 4 +#define CRYPTO_REQ_SIZE_ENUM_6_BEAT 5 +#define CRYPTO_REQ_SIZE_ENUM_7_BEAT 6 +#define CRYPTO_REQ_SIZE_ENUM_8_BEAT 7 +#define CRYPTO_REQ_SIZE_ENUM_9_BEAT 8 +#define CRYPTO_REQ_SIZE_ENUM_10_BEAT 9 +#define CRYPTO_REQ_SIZE_ENUM_11_BEAT 10 +#define CRYPTO_REQ_SIZE_ENUM_12_BEAT 11 +#define CRYPTO_REQ_SIZE_ENUM_13_BEAT 12 +#define CRYPTO_REQ_SIZE_ENUM_14_BEAT 13 +#define CRYPTO_REQ_SIZE_ENUM_15_BEAT 14 +#define CRYPTO_REQ_SIZE_ENUM_16_BEAT 15 + +#define CRYPTO_MAX_QUEUED_REQ 14 /* bit 16-14 */ +#define CRYPTO_MAX_QUEUED_REQ_MASK (0x7 << CRYPTO_MAX_QUEUED_REQ) +#define CRYPTO_ENUM_1_QUEUED_REQS 0 +#define CRYPTO_ENUM_2_QUEUED_REQS 1 +#define CRYPTO_ENUM_3_QUEUED_REQS 2 + +#define CRYPTO_IRQ_ENABLES 10 /* bit 13-10 */ +#define CRYPTO_IRQ_ENABLES_MASK (0xF << CRYPTO_IRQ_ENABLES) + +#define CRYPTO_LITTLE_ENDIAN_MODE 9 +#define CRYPTO_LITTLE_ENDIAN_MASK (1 << CRYPTO_LITTLE_ENDIAN_MODE) +#define CRYPTO_PIPE_SET_SELECT 5 /* bit 8-5 */ +#define CRYPTO_PIPE_SET_SELECT_MASK (0xF << CRYPTO_PIPE_SET_SELECT) + +#define CRYPTO_HIGH_SPD_EN_N 4 + +#define CRYPTO_MASK_DOUT_INTR 3 +#define CRYPTO_MASK_DIN_INTR 2 +#define CRYPTO_MASK_OP_DONE_INTR 1 +#define CRYPTO_MASK_ERR_INTR 0 + +/* auth_seg_cfg reg */ +#define CRYPTO_COMP_EXP_MAC 24 +#define CRYPTO_COMP_EXP_MAC_DISABLED 0 +#define CRYPTO_COMP_EXP_MAC_ENABLED 1 + +#define CRYPTO_F9_DIRECTION 23 +#define CRYPTO_F9_DIRECTION_UPLINK 0 +#define CRYPTO_F9_DIRECTION_DOWNLINK 1 + +#define CRYPTO_AUTH_NONCE_NUM_WORDS 20 /* bit 22-20 */ +#define CRYPTO_AUTH_NONCE_NUM_WORDS_MASK \ + (0x7 << CRYPTO_AUTH_NONCE_NUM_WORDS) + +#define CRYPTO_USE_PIPE_KEY_AUTH 19 +#define CRYPTO_USE_HW_KEY_AUTH 18 +#define CRYPTO_FIRST 17 +#define CRYPTO_LAST 16 + +#define CRYPTO_AUTH_POS 14 /* bit 15 .. 14*/ +#define CRYPTO_AUTH_POS_MASK (0x3 << CRYPTO_AUTH_POS) +#define CRYPTO_AUTH_POS_BEFORE 0 +#define CRYPTO_AUTH_POS_AFTER 1 + +#define CRYPTO_AUTH_SIZE 9 /* bits 13 .. 9*/ +#define CRYPTO_AUTH_SIZE_MASK (0x1F << CRYPTO_AUTH_SIZE) +#define CRYPTO_AUTH_SIZE_SHA1 0 +#define CRYPTO_AUTH_SIZE_SHA256 1 +#define CRYPTO_AUTH_SIZE_ENUM_1_BYTES 0 +#define CRYPTO_AUTH_SIZE_ENUM_2_BYTES 1 +#define CRYPTO_AUTH_SIZE_ENUM_3_BYTES 2 +#define CRYPTO_AUTH_SIZE_ENUM_4_BYTES 3 +#define CRYPTO_AUTH_SIZE_ENUM_5_BYTES 4 +#define CRYPTO_AUTH_SIZE_ENUM_6_BYTES 5 +#define CRYPTO_AUTH_SIZE_ENUM_7_BYTES 6 +#define CRYPTO_AUTH_SIZE_ENUM_8_BYTES 7 +#define CRYPTO_AUTH_SIZE_ENUM_9_BYTES 8 +#define CRYPTO_AUTH_SIZE_ENUM_10_BYTES 9 +#define CRYPTO_AUTH_SIZE_ENUM_11_BYTES 10 +#define CRYPTO_AUTH_SIZE_ENUM_12_BYTES 11 +#define CRYPTO_AUTH_SIZE_ENUM_13_BYTES 12 +#define CRYPTO_AUTH_SIZE_ENUM_14_BYTES 13 +#define CRYPTO_AUTH_SIZE_ENUM_15_BYTES 14 +#define CRYPTO_AUTH_SIZE_ENUM_16_BYTES 15 + + +#define CRYPTO_AUTH_MODE 6 /* bit 8 .. 6*/ +#define CRYPTO_AUTH_MODE_MASK (0x7 << CRYPTO_AUTH_MODE) +#define CRYPTO_AUTH_MODE_HASH 0 +#define CRYPTO_AUTH_MODE_HMAC 1 +#define CRYPTO_AUTH_MODE_CCM 0 +#define CRYPTO_AUTH_MODE_CMAC 1 + +#define CRYPTO_AUTH_KEY_SIZE 3 /* bit 5 .. 3*/ +#define CRYPTO_AUTH_KEY_SIZE_MASK (0x7 << CRYPTO_AUTH_KEY_SIZE) +#define CRYPTO_AUTH_KEY_SZ_AES128 0 +#define CRYPTO_AUTH_KEY_SZ_AES256 2 + +#define CRYPTO_AUTH_ALG 0 /* bit 2 .. 0*/ +#define CRYPTO_AUTH_ALG_MASK 7 +#define CRYPTO_AUTH_ALG_NONE 0 +#define CRYPTO_AUTH_ALG_SHA 1 +#define CRYPTO_AUTH_ALG_AES 2 +#define CRYPTO_AUTH_ALG_KASUMI 3 +#define CRYPTO_AUTH_ALG_SNOW3G 4 +#define CRYPTO_AUTH_ALG_ZUC 5 + +/* encr_xts_du_size reg */ +#define CRYPTO_ENCR_XTS_DU_SIZE 0 /* bit 19-0 */ +#define CRYPTO_ENCR_XTS_DU_SIZE_MASK 0xfffff + +/* encr_seg_cfg reg */ +#define CRYPTO_F8_KEYSTREAM_ENABLE 17/* bit */ +#define CRYPTO_F8_KEYSTREAM_DISABLED 0 +#define CRYPTO_F8_KEYSTREAM_ENABLED 1 + +#define CRYPTO_F8_DIRECTION 16 /* bit */ +#define CRYPTO_F8_DIRECTION_UPLINK 0 +#define CRYPTO_F8_DIRECTION_DOWNLINK 1 + + +#define CRYPTO_USE_PIPE_KEY_ENCR 15 /* bit */ +#define CRYPTO_USE_PIPE_KEY_ENCR_ENABLED 1 +#define CRYPTO_USE_KEY_REGISTERS 0 + + +#define CRYPTO_USE_HW_KEY_ENCR 14 +#define CRYPTO_USE_KEY_REG 0 +#define CRYPTO_USE_HW_KEY 1 + +#define CRYPTO_LAST_CCM 13 +#define CRYPTO_LAST_CCM_XFR 1 +#define CRYPTO_INTERM_CCM_XFR 0 + + +#define CRYPTO_CNTR_ALG 11 /* bit 12-11 */ +#define CRYPTO_CNTR_ALG_MASK (3 << CRYPTO_CNTR_ALG) +#define CRYPTO_CNTR_ALG_NIST 0 + +#define CRYPTO_ENCODE 10 + +#define CRYPTO_ENCR_MODE 6 /* bit 9-6 */ +#define CRYPTO_ENCR_MODE_MASK (0xF << CRYPTO_ENCR_MODE) +/* only valid when AES */ +#define CRYPTO_ENCR_MODE_ECB 0 +#define CRYPTO_ENCR_MODE_CBC 1 +#define CRYPTO_ENCR_MODE_CTR 2 +#define CRYPTO_ENCR_MODE_XTS 3 +#define CRYPTO_ENCR_MODE_CCM 4 + +#define CRYPTO_ENCR_KEY_SZ 3 /* bit 5-3 */ +#define CRYPTO_ENCR_KEY_SZ_MASK (7 << CRYPTO_ENCR_KEY_SZ) +#define CRYPTO_ENCR_KEY_SZ_DES 0 +#define CRYPTO_ENCR_KEY_SZ_3DES 1 +#define CRYPTO_ENCR_KEY_SZ_AES128 0 +#define CRYPTO_ENCR_KEY_SZ_AES256 2 + +#define CRYPTO_ENCR_ALG 0 /* bit 2-0 */ +#define CRYPTO_ENCR_ALG_MASK (7 << CRYPTO_ENCR_ALG) +#define CRYPTO_ENCR_ALG_NONE 0 +#define CRYPTO_ENCR_ALG_DES 1 +#define CRYPTO_ENCR_ALG_AES 2 +#define CRYPTO_ENCR_ALG_KASUMI 4 +#define CRYPTO_ENCR_ALG_SNOW_3G 5 +#define CRYPTO_ENCR_ALG_ZUC 6 + +/* goproc reg */ +#define CRYPTO_GO 0 +#define CRYPTO_CLR_CNTXT 1 +#define CRYPTO_RESULTS_DUMP 2 + +/* F8 definition of CRYPTO_ENCR_CNTR1_IV1 REG */ +#define CRYPTO_CNTR1_IV1_REG_F8_PKT_CNT 16 /* bit 31 - 16 */ +#define CRYPTO_CNTR1_IV1_REG_F8_PKT_CNT_MASK \ + (0xffff << CRYPTO_CNTR1_IV1_REG_F8_PKT_CNT) + +#define CRYPTO_CNTR1_IV1_REG_F8_BEARER 0 /* bit 4 - 0 */ +#define CRYPTO_CNTR1_IV1_REG_F8_BEARER_MASK \ + (0x1f << CRYPTO_CNTR1_IV1_REG_F8_BEARER) + +/* F9 definition of CRYPTO_AUTH_IV4 REG */ +#define CRYPTO_AUTH_IV4_REG_F9_VALID_BIS 0 /* bit 2 - 0 */ +#define CRYPTO_AUTH_IV4_REG_F9_VALID_BIS_MASK \ + (0x7 << CRYPTO_AUTH_IV4_REG_F9_VALID_BIS) + +/* engines_avail */ +#define CRYPTO_ENCR_AES_SEL 0 +#define CRYPTO_DES_SEL 1 +#define CRYPTO_ENCR_SNOW3G_SEL 2 +#define CRYPTO_ENCR_KASUMI_SEL 3 +#define CRYPTO_SHA_SEL 4 +#define CRYPTO_SHA512_SEL 5 +#define CRYPTO_AUTH_AES_SEL 6 +#define CRYPTO_AUTH_SNOW3G_SEL 7 +#define CRYPTO_AUTH_KASUMI_SEL 8 +#define CRYPTO_BAM_PIPE_SETS 9 /* bit 12 - 9 */ +#define CRYPTO_AXI_WR_BEATS 13 /* bit 18 - 13 */ +#define CRYPTO_AXI_RD_BEATS 19 /* bit 24 - 19 */ +#define CRYPTO_ENCR_ZUC_SEL 26 +#define CRYPTO_AUTH_ZUC_SEL 27 +#define CRYPTO_ZUC_ENABLE 28 +#endif /* _DRIVERS_CRYPTO_MSM_QCRYPTOHW_50_H_ */ --- /dev/null 2019-10-24 16:47:25.704025805 +0200 +++ linux-4.4.115-fbx/drivers/devfreq/arm-memlat-mon.c 2019-10-29 09:26:23.513201906 +0100 @@ -0,0 +1,368 @@ +/* + * Copyright (c) 2014-2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define pr_fmt(fmt) "arm-memlat-mon: " fmt + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "governor.h" +#include "governor_memlat.h" +#include + +enum ev_index { + INST_IDX, + L2DM_IDX, + CYC_IDX, + NUM_EVENTS +}; +#define INST_EV 0x08 +#define L2DM_EV 0x17 +#define CYC_EV 0x11 + +struct event_data { + struct perf_event *pevent; + unsigned long prev_count; +}; + +struct memlat_hwmon_data { + struct event_data events[NUM_EVENTS]; + ktime_t prev_ts; + bool init_pending; +}; +static DEFINE_PER_CPU(struct memlat_hwmon_data, pm_data); + +struct cpu_grp_info { + cpumask_t cpus; + struct memlat_hwmon hw; + struct notifier_block arm_memlat_cpu_notif; +}; + +static unsigned long compute_freq(struct memlat_hwmon_data *hw_data, + unsigned long cyc_cnt) +{ + ktime_t ts; + unsigned int diff; + unsigned long freq = 0; + + ts = ktime_get(); + diff = ktime_to_us(ktime_sub(ts, hw_data->prev_ts)); + if (!diff) + diff = 1; + hw_data->prev_ts = ts; + freq = cyc_cnt; + do_div(freq, diff); + + return freq; +} + +#define MAX_COUNT_LIM 0xFFFFFFFFFFFFFFFF +static inline unsigned long read_event(struct event_data *event) +{ + unsigned long ev_count; + u64 total, enabled, running; + + total = perf_event_read_value(event->pevent, &enabled, &running); + if (total >= event->prev_count) + ev_count = total - event->prev_count; + else + ev_count = (MAX_COUNT_LIM - event->prev_count) + total; + + event->prev_count = total; + + return ev_count; +} + +static void read_perf_counters(int cpu, struct cpu_grp_info *cpu_grp) +{ + int cpu_idx; + struct memlat_hwmon_data *hw_data = &per_cpu(pm_data, cpu); + struct memlat_hwmon *hw = &cpu_grp->hw; + unsigned long cyc_cnt; + + if (hw_data->init_pending) + return; + + cpu_idx = cpu - cpumask_first(&cpu_grp->cpus); + + hw->core_stats[cpu_idx].inst_count = + read_event(&hw_data->events[INST_IDX]); + + hw->core_stats[cpu_idx].mem_count = + read_event(&hw_data->events[L2DM_IDX]); + + cyc_cnt = read_event(&hw_data->events[CYC_IDX]); + hw->core_stats[cpu_idx].freq = compute_freq(hw_data, cyc_cnt); +} + +static unsigned long get_cnt(struct memlat_hwmon *hw) +{ + int cpu; + struct cpu_grp_info *cpu_grp = container_of(hw, + struct cpu_grp_info, hw); + + for_each_cpu(cpu, &cpu_grp->cpus) + read_perf_counters(cpu, cpu_grp); + + return 0; +} + +static void delete_events(struct memlat_hwmon_data *hw_data) +{ + int i; + + for (i = 0; i < NUM_EVENTS; i++) { + hw_data->events[i].prev_count = 0; + perf_event_release_kernel(hw_data->events[i].pevent); + } +} + +static void stop_hwmon(struct memlat_hwmon *hw) +{ + int cpu, idx; + struct memlat_hwmon_data *hw_data; + struct cpu_grp_info *cpu_grp = container_of(hw, + struct cpu_grp_info, hw); + + get_online_cpus(); + for_each_cpu(cpu, &cpu_grp->cpus) { + hw_data = &per_cpu(pm_data, cpu); + if (hw_data->init_pending) + hw_data->init_pending = false; + else + delete_events(hw_data); + + /* Clear governor data */ + idx = cpu - cpumask_first(&cpu_grp->cpus); + hw->core_stats[idx].inst_count = 0; + hw->core_stats[idx].mem_count = 0; + hw->core_stats[idx].freq = 0; + } + put_online_cpus(); + + unregister_cpu_notifier(&cpu_grp->arm_memlat_cpu_notif); +} + +static struct perf_event_attr *alloc_attr(void) +{ + struct perf_event_attr *attr; + + attr = kzalloc(sizeof(struct perf_event_attr), GFP_KERNEL); + if (!attr) + return ERR_PTR(-ENOMEM); + + attr->type = PERF_TYPE_RAW; + attr->size = sizeof(struct perf_event_attr); + attr->pinned = 1; + attr->exclude_idle = 1; + + return attr; +} + +static int set_events(struct memlat_hwmon_data *hw_data, int cpu) +{ + struct perf_event *pevent; + struct perf_event_attr *attr; + int err; + + /* Allocate an attribute for event initialization */ + attr = alloc_attr(); + if (IS_ERR(attr)) + return PTR_ERR(attr); + + attr->config = INST_EV; + pevent = perf_event_create_kernel_counter(attr, cpu, NULL, NULL, NULL); + if (IS_ERR(pevent)) + goto err_out; + hw_data->events[INST_IDX].pevent = pevent; + perf_event_enable(hw_data->events[INST_IDX].pevent); + + attr->config = L2DM_EV; + pevent = perf_event_create_kernel_counter(attr, cpu, NULL, NULL, NULL); + if (IS_ERR(pevent)) + goto err_out; + hw_data->events[L2DM_IDX].pevent = pevent; + perf_event_enable(hw_data->events[L2DM_IDX].pevent); + + attr->config = CYC_EV; + pevent = perf_event_create_kernel_counter(attr, cpu, NULL, NULL, NULL); + if (IS_ERR(pevent)) + goto err_out; + hw_data->events[CYC_IDX].pevent = pevent; + perf_event_enable(hw_data->events[CYC_IDX].pevent); + + kfree(attr); + return 0; + +err_out: + err = PTR_ERR(pevent); + kfree(attr); + return err; +} + +static int arm_memlat_cpu_callback(struct notifier_block *nb, + unsigned long action, void *hcpu) +{ + unsigned long cpu = (unsigned long)hcpu; + struct memlat_hwmon_data *hw_data = &per_cpu(pm_data, cpu); + + if ((action != CPU_ONLINE) || !hw_data->init_pending) + return NOTIFY_OK; + + if (set_events(hw_data, cpu)) + pr_warn("Failed to create perf event for CPU%lu\n", cpu); + + hw_data->init_pending = false; + + return NOTIFY_OK; +} + +static int start_hwmon(struct memlat_hwmon *hw) +{ + int cpu, ret = 0; + struct memlat_hwmon_data *hw_data; + struct cpu_grp_info *cpu_grp = container_of(hw, + struct cpu_grp_info, hw); + + register_cpu_notifier(&cpu_grp->arm_memlat_cpu_notif); + + get_online_cpus(); + for_each_cpu(cpu, &cpu_grp->cpus) { + hw_data = &per_cpu(pm_data, cpu); + ret = set_events(hw_data, cpu); + if (ret) { + if (!cpu_online(cpu)) { + hw_data->init_pending = true; + ret = 0; + } else { + pr_warn("Perf event init failed on CPU%d\n", + cpu); + break; + } + } + } + + put_online_cpus(); + return ret; +} + +static int get_mask_from_dev_handle(struct platform_device *pdev, + cpumask_t *mask) +{ + struct device *dev = &pdev->dev; + struct device_node *dev_phandle; + struct device *cpu_dev; + int cpu, i = 0; + int ret = -ENOENT; + + dev_phandle = of_parse_phandle(dev->of_node, "qcom,cpulist", i++); + while (dev_phandle) { + for_each_possible_cpu(cpu) { + cpu_dev = get_cpu_device(cpu); + if (cpu_dev && cpu_dev->of_node == dev_phandle) { + cpumask_set_cpu(cpu, mask); + ret = 0; + break; + } + } + dev_phandle = of_parse_phandle(dev->of_node, + "qcom,cpulist", i++); + } + + return ret; +} + +static int arm_memlat_mon_driver_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct memlat_hwmon *hw; + struct cpu_grp_info *cpu_grp; + int cpu, ret; + + cpu_grp = devm_kzalloc(dev, sizeof(*cpu_grp), GFP_KERNEL); + if (!cpu_grp) + return -ENOMEM; + cpu_grp->arm_memlat_cpu_notif.notifier_call = arm_memlat_cpu_callback; + hw = &cpu_grp->hw; + + hw->dev = dev; + hw->of_node = of_parse_phandle(dev->of_node, "qcom,target-dev", 0); + if (!hw->of_node) { + dev_err(dev, "Couldn't find a target device\n"); + return -ENODEV; + } + + if (get_mask_from_dev_handle(pdev, &cpu_grp->cpus)) { + dev_err(dev, "CPU list is empty\n"); + return -ENODEV; + } + + hw->num_cores = cpumask_weight(&cpu_grp->cpus); + hw->core_stats = devm_kzalloc(dev, hw->num_cores * + sizeof(*(hw->core_stats)), GFP_KERNEL); + if (!hw->core_stats) + return -ENOMEM; + + for_each_cpu(cpu, &cpu_grp->cpus) + hw->core_stats[cpu - cpumask_first(&cpu_grp->cpus)].id = cpu; + + hw->start_hwmon = &start_hwmon; + hw->stop_hwmon = &stop_hwmon; + hw->get_cnt = &get_cnt; + + ret = register_memlat(dev, hw); + if (ret) { + pr_err("Mem Latency Gov registration failed\n"); + return ret; + } + + return 0; +} + +static struct of_device_id match_table[] = { + { .compatible = "qcom,arm-memlat-mon" }, + {} +}; + +static struct platform_driver arm_memlat_mon_driver = { + .probe = arm_memlat_mon_driver_probe, + .driver = { + .name = "arm-memlat-mon", + .of_match_table = match_table, + .owner = THIS_MODULE, + }, +}; + +static int __init arm_memlat_mon_init(void) +{ + return platform_driver_register(&arm_memlat_mon_driver); +} +module_init(arm_memlat_mon_init); + +static void __exit arm_memlat_mon_exit(void) +{ + platform_driver_unregister(&arm_memlat_mon_driver); +} +module_exit(arm_memlat_mon_exit); --- /dev/null 2019-10-24 16:47:25.704025805 +0200 +++ linux-4.4.115-fbx/drivers/devfreq/bimc-bwmon.c 2019-10-29 09:26:23.513201906 +0100 @@ -0,0 +1,688 @@ +/* + * Copyright (c) 2014-2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define pr_fmt(fmt) "bimc-bwmon: " fmt + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "governor_bw_hwmon.h" + +#define GLB_INT_STATUS(m) ((m)->global_base + 0x100) +#define GLB_INT_CLR(m) ((m)->global_base + 0x108) +#define GLB_INT_EN(m) ((m)->global_base + 0x10C) +#define MON_INT_STATUS(m) ((m)->base + 0x100) +#define MON_INT_CLR(m) ((m)->base + 0x108) +#define MON_INT_EN(m) ((m)->base + 0x10C) +#define MON_EN(m) ((m)->base + 0x280) +#define MON_CLEAR(m) ((m)->base + 0x284) +#define MON_CNT(m) ((m)->base + 0x288) +#define MON_THRES(m) ((m)->base + 0x290) +#define MON_MASK(m) ((m)->base + 0x298) +#define MON_MATCH(m) ((m)->base + 0x29C) + +#define MON2_EN(m) ((m)->base + 0x2A0) +#define MON2_CLEAR(m) ((m)->base + 0x2A4) +#define MON2_SW(m) ((m)->base + 0x2A8) +#define MON2_THRES_HI(m) ((m)->base + 0x2AC) +#define MON2_THRES_MED(m) ((m)->base + 0x2B0) +#define MON2_THRES_LO(m) ((m)->base + 0x2B4) +#define MON2_ZONE_ACTIONS(m) ((m)->base + 0x2B8) +#define MON2_ZONE_CNT_THRES(m) ((m)->base + 0x2BC) +#define MON2_BYTE_CNT(m) ((m)->base + 0x2D0) +#define MON2_WIN_TIMER(m) ((m)->base + 0x2D4) +#define MON2_ZONE_CNT(m) ((m)->base + 0x2D8) +#define MON2_ZONE_MAX(m, zone) ((m)->base + 0x2E0 + 0x4 * zone) + +struct bwmon_spec { + bool wrap_on_thres; + bool overflow; + bool throt_adj; + bool hw_sampling; +}; + +struct bwmon { + void __iomem *base; + void __iomem *global_base; + unsigned int mport; + unsigned int irq; + const struct bwmon_spec *spec; + struct device *dev; + struct bw_hwmon hw; + u32 hw_timer_hz; + u32 throttle_adj; + u32 sample_size_ms; + u32 intr_status; +}; + +#define to_bwmon(ptr) container_of(ptr, struct bwmon, hw) +#define has_hw_sampling(m) (m->spec->hw_sampling) + +#define ENABLE_MASK BIT(0) +#define THROTTLE_MASK 0x1F +#define THROTTLE_SHIFT 16 +#define INT_ENABLE_V1 0x1 +#define INT_STATUS_MASK 0x03 +#define INT_STATUS_MASK_HWS 0xF0 + +static DEFINE_SPINLOCK(glb_lock); +static void mon_enable(struct bwmon *m) +{ + if (has_hw_sampling(m)) + writel_relaxed((ENABLE_MASK | m->throttle_adj), MON2_EN(m)); + else + writel_relaxed((ENABLE_MASK | m->throttle_adj), MON_EN(m)); +} + +static void mon_disable(struct bwmon *m) +{ + if (has_hw_sampling(m)) + writel_relaxed(m->throttle_adj, MON2_EN(m)); + else + writel_relaxed(m->throttle_adj, MON_EN(m)); + /* + * mon_disable() and mon_irq_clear(), + * If latter goes first and count happen to trigger irq, we would + * have the irq line high but no one handling it. + */ + mb(); +} + +#define MON_CLEAR_BIT 0x1 +#define MON_CLEAR_ALL_BIT 0x2 +static void mon_clear(struct bwmon *m, bool clear_all) +{ + if (!has_hw_sampling(m)) { + writel_relaxed(MON_CLEAR_BIT, MON_CLEAR(m)); + goto out; + } + + if (clear_all) + writel_relaxed(MON_CLEAR_ALL_BIT, MON2_CLEAR(m)); + else + writel_relaxed(MON_CLEAR_BIT, MON2_CLEAR(m)); + + /* + * The counter clear and IRQ clear bits are not in the same 4KB + * region. So, we need to make sure the counter clear is completed + * before we try to clear the IRQ or do any other counter operations. + */ +out: + mb(); +} + +#define SAMPLE_WIN_LIM 0xFFFFF +static void mon_set_hw_sampling_window(struct bwmon *m, unsigned int sample_ms) +{ + u32 rate; + + if (unlikely(sample_ms != m->sample_size_ms)) { + rate = mult_frac(sample_ms, m->hw_timer_hz, MSEC_PER_SEC); + m->sample_size_ms = sample_ms; + if (unlikely(rate > SAMPLE_WIN_LIM)) { + rate = SAMPLE_WIN_LIM; + pr_warn("Sample window %u larger than hw limit: %u\n", + rate, SAMPLE_WIN_LIM); + } + writel_relaxed(rate, MON2_SW(m)); + } +} + +static void mon_irq_enable(struct bwmon *m) +{ + u32 val; + + spin_lock(&glb_lock); + val = readl_relaxed(GLB_INT_EN(m)); + val |= 1 << m->mport; + writel_relaxed(val, GLB_INT_EN(m)); + + val = readl_relaxed(MON_INT_EN(m)); + val |= has_hw_sampling(m) ? INT_STATUS_MASK_HWS : INT_ENABLE_V1; + writel_relaxed(val, MON_INT_EN(m)); + spin_unlock(&glb_lock); + /* + * make Sure irq enable complete for local and global + * to avoid race with other monitor calls + */ + mb(); +} + +static void mon_irq_disable(struct bwmon *m) +{ + u32 val; + + spin_lock(&glb_lock); + val = readl_relaxed(GLB_INT_EN(m)); + val &= ~(1 << m->mport); + writel_relaxed(val, GLB_INT_EN(m)); + + val = readl_relaxed(MON_INT_EN(m)); + val &= has_hw_sampling(m) ? ~INT_STATUS_MASK_HWS : ~INT_ENABLE_V1; + writel_relaxed(val, MON_INT_EN(m)); + spin_unlock(&glb_lock); + /* + * make Sure irq disable complete for local and global + * to avoid race with other monitor calls + */ + mb(); +} + +static unsigned int mon_irq_status(struct bwmon *m) +{ + u32 mval; + + mval = readl_relaxed(MON_INT_STATUS(m)); + + dev_dbg(m->dev, "IRQ status p:%x, g:%x\n", mval, + readl_relaxed(GLB_INT_STATUS(m))); + + mval &= has_hw_sampling(m) ? INT_STATUS_MASK_HWS : INT_STATUS_MASK; + + return mval; +} + +static void mon_irq_clear(struct bwmon *m) +{ + u32 intclr; + + intclr = has_hw_sampling(m) ? INT_STATUS_MASK_HWS : INT_STATUS_MASK; + + writel_relaxed(intclr, MON_INT_CLR(m)); + mb(); + writel_relaxed(1 << m->mport, GLB_INT_CLR(m)); + mb(); +} + +static int mon_set_throttle_adj(struct bw_hwmon *hw, uint adj) +{ + struct bwmon *m = to_bwmon(hw); + + if (adj > THROTTLE_MASK) + return -EINVAL; + + adj = (adj & THROTTLE_MASK) << THROTTLE_SHIFT; + m->throttle_adj = adj; + + return 0; +} + +static u32 mon_get_throttle_adj(struct bw_hwmon *hw) +{ + struct bwmon *m = to_bwmon(hw); + + return m->throttle_adj >> THROTTLE_SHIFT; +} + +#define ZONE1_SHIFT 8 +#define ZONE2_SHIFT 16 +#define ZONE3_SHIFT 24 +#define ZONE0_ACTION 0x01 /* Increment zone 0 count */ +#define ZONE1_ACTION 0x09 /* Increment zone 1 & clear lower zones */ +#define ZONE2_ACTION 0x25 /* Increment zone 2 & clear lower zones */ +#define ZONE3_ACTION 0x95 /* Increment zone 3 & clear lower zones */ +static u32 calc_zone_actions(void) +{ + u32 zone_actions; + + zone_actions = ZONE0_ACTION; + zone_actions |= ZONE1_ACTION << ZONE1_SHIFT; + zone_actions |= ZONE2_ACTION << ZONE2_SHIFT; + zone_actions |= ZONE3_ACTION << ZONE3_SHIFT; + + return zone_actions; +} + +#define ZONE_CNT_LIM 0xFFU +#define UP_CNT_1 1 +static u32 calc_zone_counts(struct bw_hwmon *hw) +{ + u32 zone_counts; + + zone_counts = ZONE_CNT_LIM; + zone_counts |= min(hw->down_cnt, ZONE_CNT_LIM) << ZONE1_SHIFT; + zone_counts |= ZONE_CNT_LIM << ZONE2_SHIFT; + zone_counts |= UP_CNT_1 << ZONE3_SHIFT; + + return zone_counts; +} + +static unsigned int mbps_to_mb(unsigned long mbps, unsigned int ms) +{ + mbps *= ms; + mbps = DIV_ROUND_UP(mbps, MSEC_PER_SEC); + return mbps; +} + +/* + * Define the 4 zones using HI, MED & LO thresholds: + * Zone 0: byte count < THRES_LO + * Zone 1: THRES_LO < byte count < THRES_MED + * Zone 2: THRES_MED < byte count < THRES_HI + * Zone 3: byte count > THRES_HI + */ +#define THRES_LIM 0x7FFU +static void set_zone_thres(struct bwmon *m, unsigned int sample_ms) +{ + struct bw_hwmon *hw = &(m->hw); + u32 hi, med, lo; + + hi = mbps_to_mb(hw->up_wake_mbps, sample_ms); + med = mbps_to_mb(hw->down_wake_mbps, sample_ms); + lo = 0; + + if (unlikely((hi > THRES_LIM) || (med > hi) || (lo > med))) { + pr_warn("Zone thres larger than hw limit: hi:%u med:%u lo:%u\n", + hi, med, lo); + hi = min(hi, THRES_LIM); + med = min(med, hi - 1); + lo = min(lo, med-1); + } + + writel_relaxed(hi, MON2_THRES_HI(m)); + writel_relaxed(med, MON2_THRES_MED(m)); + writel_relaxed(lo, MON2_THRES_LO(m)); + dev_dbg(m->dev, "Thres: hi:%u med:%u lo:%u\n", hi, med, lo); +} + +static void mon_set_zones(struct bwmon *m, unsigned int sample_ms) +{ + struct bw_hwmon *hw = &(m->hw); + u32 zone_cnt_thres = calc_zone_counts(hw); + + mon_set_hw_sampling_window(m, sample_ms); + set_zone_thres(m, sample_ms); + /* Set the zone count thresholds for interrupts */ + writel_relaxed(zone_cnt_thres, MON2_ZONE_CNT_THRES(m)); + + dev_dbg(m->dev, "Zone Count Thres: %0x\n", zone_cnt_thres); +} + +static void mon_set_limit(struct bwmon *m, u32 count) +{ + writel_relaxed(count, MON_THRES(m)); + dev_dbg(m->dev, "Thres: %08x\n", count); +} + +static u32 mon_get_limit(struct bwmon *m) +{ + return readl_relaxed(MON_THRES(m)); +} + +#define THRES_HIT(status) (status & BIT(0)) +#define OVERFLOW(status) (status & BIT(1)) +static unsigned long mon_get_count(struct bwmon *m) +{ + unsigned long count, status; + + count = readl_relaxed(MON_CNT(m)); + status = mon_irq_status(m); + + dev_dbg(m->dev, "Counter: %08lx\n", count); + + if (OVERFLOW(status) && m->spec->overflow) + count += 0xFFFFFFFF; + if (THRES_HIT(status) && m->spec->wrap_on_thres) + count += mon_get_limit(m); + + dev_dbg(m->dev, "Actual Count: %08lx\n", count); + + return count; +} + +static unsigned int get_zone(struct bwmon *m) +{ + u32 zone_counts; + u32 zone; + + zone = get_bitmask_order((m->intr_status & INT_STATUS_MASK_HWS) >> 4); + if (zone) { + zone--; + } else { + zone_counts = readl_relaxed(MON2_ZONE_CNT(m)); + if (zone_counts) { + zone = get_bitmask_order(zone_counts) - 1; + zone /= 8; + } + } + + m->intr_status = 0; + return zone; +} + +static unsigned long mon_get_zone_stats(struct bwmon *m) +{ + unsigned int zone; + unsigned long count = 0; + + zone = get_zone(m); + + count = readl_relaxed(MON2_ZONE_MAX(m, zone)) + 1; + count *= SZ_1M; + + dev_dbg(m->dev, "Zone%d Max byte count: %08lx\n", zone, count); + + return count; +} + +/* ********** CPUBW specific code ********** */ + +/* Returns MBps of read/writes for the sampling window. */ +static unsigned int mbps_to_bytes(unsigned long mbps, unsigned int ms, + unsigned int tolerance_percent) +{ + mbps *= (100 + tolerance_percent) * ms; + mbps /= 100; + mbps = DIV_ROUND_UP(mbps, MSEC_PER_SEC); + mbps *= SZ_1M; + return mbps; +} + +static unsigned long get_bytes_and_clear(struct bw_hwmon *hw) +{ + struct bwmon *m = to_bwmon(hw); + unsigned long count; + + mon_disable(m); + count = has_hw_sampling(m) ? mon_get_zone_stats(m) : mon_get_count(m); + mon_clear(m, false); + mon_irq_clear(m); + mon_enable(m); + + return count; +} + +static unsigned long set_thres(struct bw_hwmon *hw, unsigned long bytes) +{ + unsigned long count; + u32 limit; + struct bwmon *m = to_bwmon(hw); + + mon_disable(m); + count = mon_get_count(m); + mon_clear(m, false); + mon_irq_clear(m); + + if (likely(!m->spec->wrap_on_thres)) + limit = bytes; + else + limit = max(bytes, 500000UL); + + mon_set_limit(m, limit); + mon_enable(m); + + return count; +} + +static unsigned long set_hw_events(struct bw_hwmon *hw, unsigned sample_ms) +{ + struct bwmon *m = to_bwmon(hw); + + mon_disable(m); + mon_clear(m, false); + mon_irq_clear(m); + + mon_set_zones(m, sample_ms); + mon_enable(m); + + return 0; +} + +static irqreturn_t bwmon_intr_handler(int irq, void *dev) +{ + struct bwmon *m = dev; + + m->intr_status = mon_irq_status(m); + if (!m->intr_status) + return IRQ_NONE; + + if (bw_hwmon_sample_end(&m->hw) > 0) + return IRQ_WAKE_THREAD; + + return IRQ_HANDLED; +} + +static irqreturn_t bwmon_intr_thread(int irq, void *dev) +{ + struct bwmon *m = dev; + + update_bw_hwmon(&m->hw); + return IRQ_HANDLED; +} + +static int start_bw_hwmon(struct bw_hwmon *hw, unsigned long mbps) +{ + struct bwmon *m = to_bwmon(hw); + u32 limit; + u32 zone_actions = calc_zone_actions(); + int ret; + + ret = request_threaded_irq(m->irq, bwmon_intr_handler, + bwmon_intr_thread, + IRQF_ONESHOT | IRQF_SHARED, + dev_name(m->dev), m); + if (ret) { + dev_err(m->dev, "Unable to register interrupt handler! (%d)\n", + ret); + return ret; + } + + mon_disable(m); + + mon_clear(m, true); + limit = mbps_to_bytes(mbps, hw->df->profile->polling_ms, 0); + if (has_hw_sampling(m)) { + mon_set_zones(m, hw->df->profile->polling_ms); + /* Set the zone actions to increment appropriate counters */ + writel_relaxed(zone_actions, MON2_ZONE_ACTIONS(m)); + } else { + mon_set_limit(m, limit); + } + + mon_irq_clear(m); + mon_irq_enable(m); + mon_enable(m); + + return 0; +} + +static void stop_bw_hwmon(struct bw_hwmon *hw) +{ + struct bwmon *m = to_bwmon(hw); + + mon_irq_disable(m); + free_irq(m->irq, m); + mon_disable(m); + mon_clear(m, true); + mon_irq_clear(m); +} + +static int suspend_bw_hwmon(struct bw_hwmon *hw) +{ + struct bwmon *m = to_bwmon(hw); + + mon_irq_disable(m); + free_irq(m->irq, m); + mon_disable(m); + mon_irq_clear(m); + + return 0; +} + +static int resume_bw_hwmon(struct bw_hwmon *hw) +{ + struct bwmon *m = to_bwmon(hw); + int ret; + + mon_clear(m, false); + ret = request_threaded_irq(m->irq, bwmon_intr_handler, + bwmon_intr_thread, + IRQF_ONESHOT | IRQF_SHARED, + dev_name(m->dev), m); + if (ret) { + dev_err(m->dev, "Unable to register interrupt handler! (%d)\n", + ret); + return ret; + } + + mon_irq_enable(m); + mon_enable(m); + + return 0; +} + +/*************************************************************************/ + +static const struct bwmon_spec spec[] = { + { .wrap_on_thres = true, .overflow = false, .throt_adj = false, + .hw_sampling = false}, + { .wrap_on_thres = false, .overflow = true, .throt_adj = false, + .hw_sampling = false}, + { .wrap_on_thres = false, .overflow = true, .throt_adj = true, + .hw_sampling = false}, + { .wrap_on_thres = false, .overflow = true, .throt_adj = true, + .hw_sampling = true}, +}; + +static struct of_device_id match_table[] = { + { .compatible = "qcom,bimc-bwmon", .data = &spec[0] }, + { .compatible = "qcom,bimc-bwmon2", .data = &spec[1] }, + { .compatible = "qcom,bimc-bwmon3", .data = &spec[2] }, + { .compatible = "qcom,bimc-bwmon4", .data = &spec[3] }, + {} +}; + +static int bimc_bwmon_driver_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct resource *res; + struct bwmon *m; + const struct of_device_id *id; + int ret; + u32 data; + + m = devm_kzalloc(dev, sizeof(*m), GFP_KERNEL); + if (!m) + return -ENOMEM; + m->dev = dev; + + ret = of_property_read_u32(dev->of_node, "qcom,mport", &data); + if (ret) { + dev_err(dev, "mport not found!\n"); + return ret; + } + m->mport = data; + + id = of_match_device(match_table, dev); + if (!id) { + dev_err(dev, "Unknown device type!\n"); + return -ENODEV; + } + m->spec = id->data; + + if (has_hw_sampling(m)) { + ret = of_property_read_u32(dev->of_node, + "qcom,hw-timer-hz", &data); + if (ret) { + dev_err(dev, "HW sampling rate not specified!\n"); + return ret; + } + m->hw_timer_hz = data; + } + + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "base"); + if (!res) { + dev_err(dev, "base not found!\n"); + return -EINVAL; + } + m->base = devm_ioremap(dev, res->start, resource_size(res)); + if (!m->base) { + dev_err(dev, "Unable map base!\n"); + return -ENOMEM; + } + + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "global_base"); + if (!res) { + dev_err(dev, "global_base not found!\n"); + return -EINVAL; + } + m->global_base = devm_ioremap(dev, res->start, resource_size(res)); + if (!m->global_base) { + dev_err(dev, "Unable map global_base!\n"); + return -ENOMEM; + } + + m->irq = platform_get_irq(pdev, 0); + if (m->irq < 0) { + dev_err(dev, "Unable to get IRQ number\n"); + return m->irq; + } + + m->hw.of_node = of_parse_phandle(dev->of_node, "qcom,target-dev", 0); + if (!m->hw.of_node) + return -EINVAL; + m->hw.start_hwmon = &start_bw_hwmon; + m->hw.stop_hwmon = &stop_bw_hwmon; + m->hw.suspend_hwmon = &suspend_bw_hwmon; + m->hw.resume_hwmon = &resume_bw_hwmon; + m->hw.get_bytes_and_clear = &get_bytes_and_clear; + m->hw.set_thres = &set_thres; + if (has_hw_sampling(m)) + m->hw.set_hw_events = &set_hw_events; + if (m->spec->throt_adj) { + m->hw.set_throttle_adj = &mon_set_throttle_adj; + m->hw.get_throttle_adj = &mon_get_throttle_adj; + } + + ret = register_bw_hwmon(dev, &m->hw); + if (ret) { + dev_err(dev, "Dev BW hwmon registration failed\n"); + return ret; + } + + return 0; +} + +static struct platform_driver bimc_bwmon_driver = { + .probe = bimc_bwmon_driver_probe, + .driver = { + .name = "bimc-bwmon", + .of_match_table = match_table, + .owner = THIS_MODULE, + }, +}; + +static int __init bimc_bwmon_init(void) +{ + return platform_driver_register(&bimc_bwmon_driver); +} +module_init(bimc_bwmon_init); + +static void __exit bimc_bwmon_exit(void) +{ + platform_driver_unregister(&bimc_bwmon_driver); +} +module_exit(bimc_bwmon_exit); + +MODULE_DESCRIPTION("BIMC bandwidth monitor driver"); +MODULE_LICENSE("GPL v2"); --- /dev/null 2019-10-24 16:47:25.704025805 +0200 +++ linux-4.4.115-fbx/drivers/devfreq/devfreq_devbw.c 2019-01-22 16:16:23.135243074 +0100 @@ -0,0 +1,290 @@ +/* + * Copyright (c) 2013-2014, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define pr_fmt(fmt) "devbw: " fmt + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* Has to be ULL to prevent overflow where this macro is used. */ +#define MBYTE (1ULL << 20) +#define MAX_PATHS 2 +#define DBL_BUF 2 + +struct dev_data { + struct msm_bus_vectors vectors[MAX_PATHS * DBL_BUF]; + struct msm_bus_paths bw_levels[DBL_BUF]; + struct msm_bus_scale_pdata bw_data; + int num_paths; + u32 bus_client; + int cur_idx; + int cur_ab; + int cur_ib; + long gov_ab; + unsigned int ab_percent; + struct devfreq *df; + struct devfreq_dev_profile dp; +}; + +static int set_bw(struct device *dev, int new_ib, int new_ab) +{ + struct dev_data *d = dev_get_drvdata(dev); + int i, ret; + + if (d->cur_ib == new_ib && d->cur_ab == new_ab) + return 0; + + i = (d->cur_idx + 1) % DBL_BUF; + + d->bw_levels[i].vectors[0].ib = new_ib * MBYTE; + d->bw_levels[i].vectors[0].ab = new_ab / d->num_paths * MBYTE; + d->bw_levels[i].vectors[1].ib = new_ib * MBYTE; + d->bw_levels[i].vectors[1].ab = new_ab / d->num_paths * MBYTE; + + dev_dbg(dev, "BW MBps: AB: %d IB: %d\n", new_ab, new_ib); + + ret = msm_bus_scale_client_update_request(d->bus_client, i); + if (ret) { + dev_err(dev, "bandwidth request failed (%d)\n", ret); + } else { + d->cur_idx = i; + d->cur_ib = new_ib; + d->cur_ab = new_ab; + } + + return ret; +} + +static unsigned int find_ab(struct dev_data *d, unsigned long *freq) +{ + return (d->ab_percent * (*freq)) / 100; +} + +static void find_freq(struct devfreq_dev_profile *p, unsigned long *freq, + u32 flags) +{ + int i; + unsigned long atmost, atleast, f; + + atmost = p->freq_table[0]; + atleast = p->freq_table[p->max_state-1]; + for (i = 0; i < p->max_state; i++) { + f = p->freq_table[i]; + if (f <= *freq) + atmost = max(f, atmost); + if (f >= *freq) + atleast = min(f, atleast); + } + + if (flags & DEVFREQ_FLAG_LEAST_UPPER_BOUND) + *freq = atmost; + else + *freq = atleast; +} + +static int devbw_target(struct device *dev, unsigned long *freq, u32 flags) +{ + struct dev_data *d = dev_get_drvdata(dev); + + find_freq(&d->dp, freq, flags); + + if (!d->gov_ab) + return set_bw(dev, *freq, find_ab(d, freq)); + else + return set_bw(dev, *freq, d->gov_ab); +} + +static int devbw_get_dev_status(struct device *dev, + struct devfreq_dev_status *stat) +{ + struct dev_data *d = dev_get_drvdata(dev); + + stat->private_data = &d->gov_ab; + return 0; +} + +#define PROP_PORTS "qcom,src-dst-ports" +#define PROP_TBL "qcom,bw-tbl" +#define PROP_AB_PER "qcom,ab-percent" +#define PROP_ACTIVE "qcom,active-only" + +int devfreq_add_devbw(struct device *dev) +{ + struct dev_data *d; + struct devfreq_dev_profile *p; + u32 *data, ports[MAX_PATHS * 2]; + const char *gov_name; + int ret, len, i, num_paths; + + d = devm_kzalloc(dev, sizeof(*d), GFP_KERNEL); + if (!d) + return -ENOMEM; + dev_set_drvdata(dev, d); + + if (of_find_property(dev->of_node, PROP_PORTS, &len)) { + len /= sizeof(ports[0]); + if (len % 2 || len > ARRAY_SIZE(ports)) { + dev_err(dev, "Unexpected number of ports\n"); + return -EINVAL; + } + + ret = of_property_read_u32_array(dev->of_node, PROP_PORTS, + ports, len); + if (ret) + return ret; + + num_paths = len / 2; + } else { + return -EINVAL; + } + + d->bw_levels[0].vectors = &d->vectors[0]; + d->bw_levels[1].vectors = &d->vectors[MAX_PATHS]; + d->bw_data.usecase = d->bw_levels; + d->bw_data.num_usecases = ARRAY_SIZE(d->bw_levels); + d->bw_data.name = dev_name(dev); + d->bw_data.active_only = of_property_read_bool(dev->of_node, + PROP_ACTIVE); + + for (i = 0; i < num_paths; i++) { + d->bw_levels[0].vectors[i].src = ports[2 * i]; + d->bw_levels[0].vectors[i].dst = ports[2 * i + 1]; + d->bw_levels[1].vectors[i].src = ports[2 * i]; + d->bw_levels[1].vectors[i].dst = ports[2 * i + 1]; + } + d->bw_levels[0].num_paths = num_paths; + d->bw_levels[1].num_paths = num_paths; + d->num_paths = num_paths; + + p = &d->dp; + p->polling_ms = 50; + p->target = devbw_target; + p->get_dev_status = devbw_get_dev_status; + + if (of_find_property(dev->of_node, PROP_TBL, &len)) { + len /= sizeof(*data); + data = devm_kzalloc(dev, len * sizeof(*data), GFP_KERNEL); + if (!data) + return -ENOMEM; + + p->freq_table = devm_kzalloc(dev, + len * sizeof(*p->freq_table), + GFP_KERNEL); + if (!p->freq_table) + return -ENOMEM; + + ret = of_property_read_u32_array(dev->of_node, PROP_TBL, + data, len); + if (ret) + return ret; + + for (i = 0; i < len; i++) + p->freq_table[i] = data[i]; + p->max_state = len; + } + + if (of_find_property(dev->of_node, PROP_AB_PER, &len)) { + ret = of_property_read_u32(dev->of_node, PROP_AB_PER, + &d->ab_percent); + if (ret) + return ret; + + dev_dbg(dev, "ab-percent used %u\n", d->ab_percent); + } + + d->bus_client = msm_bus_scale_register_client(&d->bw_data); + if (!d->bus_client) { + dev_err(dev, "Unable to register bus client\n"); + return -ENODEV; + } + + if (of_property_read_string(dev->of_node, "governor", &gov_name)) + gov_name = "performance"; + + d->df = devfreq_add_device(dev, p, gov_name, NULL); + if (IS_ERR(d->df)) { + msm_bus_scale_unregister_client(d->bus_client); + return PTR_ERR(d->df); + } + + return 0; +} + +int devfreq_remove_devbw(struct device *dev) +{ + struct dev_data *d = dev_get_drvdata(dev); + msm_bus_scale_unregister_client(d->bus_client); + devfreq_remove_device(d->df); + return 0; +} + +int devfreq_suspend_devbw(struct device *dev) +{ + struct dev_data *d = dev_get_drvdata(dev); + return devfreq_suspend_device(d->df); +} + +int devfreq_resume_devbw(struct device *dev) +{ + struct dev_data *d = dev_get_drvdata(dev); + return devfreq_resume_device(d->df); +} + +static int devfreq_devbw_probe(struct platform_device *pdev) +{ + return devfreq_add_devbw(&pdev->dev); +} + +static int devfreq_devbw_remove(struct platform_device *pdev) +{ + return devfreq_remove_devbw(&pdev->dev); +} + +static struct of_device_id match_table[] = { + { .compatible = "qcom,devbw" }, + {} +}; + +static struct platform_driver devbw_driver = { + .probe = devfreq_devbw_probe, + .remove = devfreq_devbw_remove, + .driver = { + .name = "devbw", + .of_match_table = match_table, + .owner = THIS_MODULE, + }, +}; + +static int __init devbw_init(void) +{ + platform_driver_register(&devbw_driver); + return 0; +} +device_initcall(devbw_init); + +MODULE_DESCRIPTION("Device DDR bandwidth voting driver MSM SoCs"); +MODULE_LICENSE("GPL v2"); --- /dev/null 2019-10-24 16:47:25.704025805 +0200 +++ linux-4.4.115-fbx/drivers/devfreq/devfreq_spdm.c 2019-10-29 09:26:23.513201906 +0100 @@ -0,0 +1,443 @@ +/* +*Copyright (c) 2014-2015, The Linux Foundation. All rights reserved. +* +*This program is free software; you can redistribute it and/or modify +*it under the terms of the GNU General Public License version 2 and +*only version 2 as published by the Free Software Foundation. +* +*This program is distributed in the hope that it will be useful, +*but WITHOUT ANY WARRANTY; without even the implied warranty of +*MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +*GNU General Public License for more details. +*/ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "governor.h" +#include "devfreq_spdm.h" + +static void *spdm_ipc_log_ctxt; +#define DEVFREQ_SPDM_DEFAULT_WINDOW_MS 100 +#define SPDM_IPC_LOG_PAGES 5 + +#define SPDM_IPC_LOG(x...) do { \ + pr_debug(x); \ + if (spdm_ipc_log_ctxt) \ + ipc_log_string(spdm_ipc_log_ctxt, x); \ +} while (0) + +#define COPY_SIZE(x, y) ((x) <= (y) ? (x) : (y)) + +static int change_bw(struct device *dev, unsigned long *freq, u32 flags) +{ + struct spdm_data *data = 0; + int i; + int next_idx; + int ret = 0; + struct spdm_args desc = { { 0 } }; + int ext_status = 0; + + if (!dev || !freq) + return -EINVAL; + + data = dev_get_drvdata(dev); + if (!data) + return -EINVAL; + + if (data->devfreq->previous_freq == *freq) + goto update_thresholds; + + next_idx = data->cur_idx + 1; + next_idx = next_idx % 2; + + for (i = 0; i < data->pdata->usecase[next_idx].num_paths; i++) + data->pdata->usecase[next_idx].vectors[i].ab = (*freq) << 6; + + data->cur_idx = next_idx; + ret = msm_bus_scale_client_update_request(data->bus_scale_client_id, + data->cur_idx); + +update_thresholds: + desc.arg[0] = SPDM_CMD_ENABLE; + desc.arg[1] = data->spdm_client; + + if (data->cci_clk) + desc.arg[2] = (clk_get_rate(data->cci_clk)) / 1000; + else + desc.arg[2] = 0; + + ext_status = spdm_ext_call(&desc, 3); + if (ext_status) + pr_err("External command %u failed with error %u", + (int)desc.arg[0], ext_status); + return ret; +} + +static int get_cur_bw(struct device *dev, unsigned long *freq) +{ + struct spdm_data *data = 0; + + if (!dev || !freq) + return -EINVAL; + + data = dev_get_drvdata(dev); + if (!data) + return -EINVAL; + + *freq = data->pdata->usecase[data->cur_idx].vectors[0].ab >> 6; + + return 0; +} + +static int get_dev_status(struct device *dev, struct devfreq_dev_status *status) +{ + struct spdm_data *data = 0; + int ret; + + if (!dev || !status) + return -EINVAL; + + data = dev_get_drvdata(dev); + if (!data) + return -EINVAL; + + /* determine if we want to go up or down based on the notification */ + if (data->action == SPDM_UP) + status->busy_time = 255; + else + status->busy_time = 0; + status->total_time = 255; + ret = get_cur_bw(dev, &status->current_frequency); + if (ret) + return ret; + + return 0; + +} + +static int populate_config_data(struct spdm_data *data, + struct platform_device *pdev) +{ + int ret = -EINVAL; + struct device_node *node = pdev->dev.of_node; + struct property *prop = 0; + + ret = of_property_read_u32(node, "qcom,max-vote", + &data->config_data.max_vote); + if (ret) + return ret; + + ret = of_property_read_u32(node, "qcom,bw-upstep", + &data->config_data.upstep); + if (ret) + return ret; + + ret = of_property_read_u32(node, "qcom,bw-dwnstep", + &data->config_data.downstep); + if (ret) + return ret; + + ret = of_property_read_u32(node, "qcom,alpha-up", + &data->config_data.aup); + if (ret) + return ret; + + ret = of_property_read_u32(node, "qcom,alpha-down", + &data->config_data.adown); + if (ret) + return ret; + + ret = of_property_read_u32(node, "qcom,bucket-size", + &data->config_data.bucket_size); + if (ret) + return ret; + + ret = of_property_read_u32_array(node, "qcom,pl-freqs", + data->config_data.pl_freqs, + SPDM_PL_COUNT - 1); + if (ret) + return ret; + + ret = of_property_read_u32_array(node, "qcom,reject-rate", + data->config_data.reject_rate, + SPDM_PL_COUNT * 2); + if (ret) + return ret; + + ret = of_property_read_u32_array(node, "qcom,response-time-us", + data->config_data.response_time_us, + SPDM_PL_COUNT * 2); + if (ret) + return ret; + + ret = of_property_read_u32_array(node, "qcom,cci-response-time-us", + data->config_data.cci_response_time_us, + SPDM_PL_COUNT * 2); + if (ret) + return ret; + + ret = of_property_read_u32(node, "qcom,max-cci-freq", + &data->config_data.max_cci_freq); + if (ret) + return ret; + ret = of_property_read_u32(node, "qcom,up-step-multp", + &data->config_data.up_step_multp); + if (ret) + return ret; + + prop = of_find_property(node, "qcom,ports", 0); + if (!prop) + return -EINVAL; + data->config_data.num_ports = prop->length / sizeof(u32); + data->config_data.ports = + devm_kzalloc(&pdev->dev, prop->length, GFP_KERNEL); + if (!data->config_data.ports) + return -ENOMEM; + ret = of_property_read_u32_array(node, "qcom,ports", + data->config_data.ports, + data->config_data.num_ports); + if (ret) { + devm_kfree(&pdev->dev, data->config_data.ports); + data->config_data.ports = NULL; + return ret; + } + + return 0; +} + +static int populate_spdm_data(struct spdm_data *data, + struct platform_device *pdev) +{ + int ret = -EINVAL; + struct device_node *node = pdev->dev.of_node; + + ret = populate_config_data(data, pdev); + if (ret) + return ret; + + ret = + of_property_read_u32(node, "qcom,spdm-client", &data->spdm_client); + if (ret) + goto no_client; + + ret = of_property_read_u32(node, "qcom,spdm-interval", &data->window); + if (ret) + data->window = DEVFREQ_SPDM_DEFAULT_WINDOW_MS; + + data->pdata = msm_bus_cl_get_pdata(pdev); + if (!data->pdata) { + ret = -EINVAL; + goto no_pdata; + } + + return 0; + +no_client: +no_pdata: + devm_kfree(&pdev->dev, data->config_data.ports); + data->config_data.ports = NULL; + return ret; +} + +int __spdm_hyp_call(struct spdm_args *args, int num_args) +{ + struct hvc_desc desc = { { 0 } }; + int status; + + memcpy(desc.arg, args->arg, + COPY_SIZE(sizeof(desc.arg), sizeof(args->arg))); + SPDM_IPC_LOG("hvc call fn:0x%x, cmd:%llu, num_args:%d\n", + HVC_FN_SIP(SPDM_HYP_FNID), desc.arg[0], num_args); + + status = hvc(HVC_FN_SIP(SPDM_HYP_FNID), &desc); + + memcpy(args->ret, desc.ret, + COPY_SIZE(sizeof(args->ret), sizeof(desc.ret))); + SPDM_IPC_LOG("hvc return fn:0x%x cmd:%llu Ret[0]:%llu Ret[1]:%llu\n", + HVC_FN_SIP(SPDM_HYP_FNID), desc.arg[0], + desc.ret[0], desc.ret[1]); + return status; +} + +int __spdm_scm_call(struct spdm_args *args, int num_args) +{ + int status = 0; + + SPDM_IPC_LOG("%s:svc_id:%d,cmd_id:%d,cmd:%llu,num_args:%d\n", + __func__, SPDM_SCM_SVC_ID, SPDM_SCM_CMD_ID, + args->arg[0], num_args); + + if (!is_scm_armv8()) { + status = scm_call(SPDM_SCM_SVC_ID, SPDM_SCM_CMD_ID, args->arg, + sizeof(args->arg), args->ret, + sizeof(args->ret)); + } else { + struct scm_desc desc = {0}; + /* + * Need to hard code this, this is a requirement from TZ syscall + * interface. + */ + desc.arginfo = SCM_ARGS(6); + memcpy(desc.args, args->arg, + COPY_SIZE(sizeof(desc.args), sizeof(args->arg))); + + status = scm_call2(SCM_SIP_FNID(SPDM_SCM_SVC_ID, + SPDM_SCM_CMD_ID), &desc); + + memcpy(args->ret, desc.ret, + COPY_SIZE(sizeof(args->ret), sizeof(desc.ret))); + } + SPDM_IPC_LOG("%s:svc_id:%d,cmd_id:%d,cmd:%llu,Ret[0]:%llu,Ret[1]:%llu\n" + , __func__, SPDM_SCM_SVC_ID, SPDM_SCM_CMD_ID, args->arg[0], + args->ret[0], args->ret[1]); + return status; +} + +static int probe(struct platform_device *pdev) +{ + struct spdm_data *data = 0; + int ret = -EINVAL; + struct spdm_args desc = { { 0 } }; + int ext_status = 0; + + data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL); + if (!data) + return -ENOMEM; + + data->action = SPDM_DOWN; + + platform_set_drvdata(pdev, data); + + ret = populate_spdm_data(data, pdev); + if (ret) + goto bad_of; + + desc.arg[0] = SPDM_CMD_GET_VERSION; + ext_status = spdm_ext_call(&desc, 1); + if (ext_status) { + pr_err("%s:External command %u failed with error %u\n", + __func__, (int)desc.arg[0], ext_status); + goto bad_of; + } + + if (desc.ret[0] < SPDM_TZ_VERSION) { + pr_err("%s: Version mismatch expected 0x%x got 0x%x", __func__, + SPDM_TZ_VERSION, (int)desc.arg[0]); + goto bad_of; + } + + data->bus_scale_client_id = msm_bus_scale_register_client(data->pdata); + if (!data->bus_scale_client_id) { + ret = -EINVAL; + goto no_bus_scaling; + } + + data->cci_clk = clk_get(&pdev->dev, "cci_clk"); + if (IS_ERR(data->cci_clk)) { + data->cci_clk = NULL; + } + + data->profile = + devm_kzalloc(&pdev->dev, sizeof(*(data->profile)), GFP_KERNEL); + if (!data->profile) { + ret = -ENOMEM; + goto no_profile; + } + data->profile->target = change_bw; + data->profile->get_dev_status = get_dev_status; + data->profile->get_cur_freq = get_cur_bw; + data->profile->polling_ms = data->window; + + data->devfreq = + devfreq_add_device(&pdev->dev, data->profile, "spdm_bw_hyp", data); + if (IS_ERR(data->devfreq)) { + ret = PTR_ERR(data->devfreq); + goto no_spdm_device; + } + + spdm_init_debugfs(&pdev->dev); + spdm_ipc_log_ctxt = ipc_log_context_create(SPDM_IPC_LOG_PAGES, + "devfreq_spdm", 0); + + if (IS_ERR_OR_NULL(spdm_ipc_log_ctxt)) { + pr_err("%s: Failed to create IPC log context\n", __func__); + spdm_ipc_log_ctxt = NULL; + } + + + return 0; + +no_spdm_device: + devm_kfree(&pdev->dev, data->profile); +no_profile: + msm_bus_scale_unregister_client(data->bus_scale_client_id); +no_bus_scaling: + devm_kfree(&pdev->dev, data->config_data.ports); +bad_of: + devm_kfree(&pdev->dev, data); + platform_set_drvdata(pdev, NULL); + return ret; +} + +static int remove(struct platform_device *pdev) +{ + struct spdm_data *data = 0; + + data = platform_get_drvdata(pdev); + + spdm_remove_debugfs(data); + + if (data->devfreq) + devfreq_remove_device(data->devfreq); + + if (data->profile) + devm_kfree(&pdev->dev, data->profile); + + if (data->bus_scale_client_id) + msm_bus_scale_unregister_client(data->bus_scale_client_id); + + if (data->config_data.ports) + devm_kfree(&pdev->dev, data->config_data.ports); + + devm_kfree(&pdev->dev, data); + platform_set_drvdata(pdev, NULL); + + if (spdm_ipc_log_ctxt) + ipc_log_context_destroy(spdm_ipc_log_ctxt); + + return 0; +} + +static const struct of_device_id devfreq_spdm_match[] = { + {.compatible = "qcom,devfreq_spdm"}, + {} +}; + +static struct platform_driver devfreq_spdm_drvr = { + .driver = { + .name = "devfreq_spdm", + .owner = THIS_MODULE, + .of_match_table = devfreq_spdm_match, + }, + .probe = probe, + .remove = remove, +}; + +static int __init devfreq_spdm_init(void) +{ + return platform_driver_register(&devfreq_spdm_drvr); +} + +module_init(devfreq_spdm_init); + +MODULE_LICENSE("GPL v2"); --- /dev/null 2019-10-24 16:47:25.704025805 +0200 +++ linux-4.4.115-fbx/drivers/devfreq/devfreq_spdm_debugfs.c 2019-01-22 16:16:23.135243074 +0100 @@ -0,0 +1,884 @@ +/* +*Copyright (c) 2014-2015, The Linux Foundation. All rights reserved. +* +*This program is free software; you can redistribute it and/or modify +*it under the terms of the GNU General Public License version 2 and +*only version 2 as published by the Free Software Foundation. +* +*This program is distributed in the hope that it will be useful, +*but WITHOUT ANY WARRANTY; without even the implied warranty of +*MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +*GNU General Public License for more details. +*/ +#include +#include +#include +#include +#include +#include +#include "devfreq_spdm.h" +#include "governor.h" + +static int spdm_open(struct inode *inode, struct file *file) +{ + file->private_data = inode->i_private; + return 0; +} + +static char buf[PAGE_SIZE]; + +static ssize_t enable_write(struct file *file, const char __user *data, + size_t size, loff_t *offset) +{ + struct spdm_data *spdm_data = file->private_data; + int i; + int next_idx; + + if (size > sizeof(buf) - 1) + return -EINVAL; + + if (copy_from_user(buf, data, size)) { + goto err; + size = -EINVAL; + } + + buf[size] = '\0'; + + if (sscanf(buf, "%u\n", &i) != 1) { + size = -EINVAL; + goto err; + } + i = !!i; + + if (i == spdm_data->enabled) + goto out; + + spdm_data->devfreq->governor->event_handler(spdm_data->devfreq, + i ? DEVFREQ_GOV_START : + DEVFREQ_GOV_STOP, NULL); + + if (!i) { + next_idx = spdm_data->cur_idx + 1; + next_idx = next_idx % 2; + + for (i = 0; i < spdm_data->pdata->usecase[next_idx].num_paths; + i++) + spdm_data->pdata->usecase[next_idx].vectors[i].ab = 0; + + spdm_data->cur_idx = next_idx; + msm_bus_scale_client_update_request + (spdm_data->bus_scale_client_id, spdm_data->cur_idx); + } + +out: + *offset += size; +err: + memset(buf, 0, sizeof(buf)); + return size; +} + +static ssize_t enable_read(struct file *file, char __user *data, + size_t size, loff_t *offset) +{ + struct spdm_data *spdm_data = file->private_data; + int len = 32; + + if (size > sizeof(buf)) + return -EINVAL; + + len = scnprintf(buf, size, "%u\n", spdm_data->enabled); + len = simple_read_from_buffer(data, size, offset, buf, len); + + memset(buf, 0, sizeof(buf)); + return len; +} + +static const struct file_operations enable_fops = { + .open = spdm_open, + .write = enable_write, + .read = enable_read, +}; + +static ssize_t pl_write(struct file *file, const char __user *data, + size_t size, loff_t *offset) +{ + struct spdm_data *spdm_data = file->private_data; + struct spdm_args desc = { { 0 } }; + int ext_status = 0; + int i; + + if (size > sizeof(buf) - 1) + return -EINVAL; + + if (copy_from_user(buf, data, size)) { + size = -EINVAL; + goto out; + } + + buf[size] = '\0'; + + if (sscanf(buf, "%u %u\n", &spdm_data->config_data.pl_freqs[0], + &spdm_data->config_data.pl_freqs[1]) != 2) { + size = -EINVAL; + goto out; + } + + desc.arg[0] = SPDM_CMD_CFG_PL; + desc.arg[1] = spdm_data->spdm_client; + for (i = 0; i < SPDM_PL_COUNT - 1; i++) + desc.arg[i+2] = spdm_data->config_data.pl_freqs[i]; + ext_status = spdm_ext_call(&desc, SPDM_PL_COUNT + 1); + if (ext_status) + pr_err("External command %u failed with error %u", + (int)desc.arg[0], ext_status); + *offset += size; +out: + memset(buf, 0, sizeof(buf)); + return size; + +} + +static ssize_t pl_read(struct file *file, char __user *data, + size_t size, loff_t *offset) +{ + struct spdm_data *spdm_data = file->private_data; + int i = 32; + + if (size > sizeof(buf)) + return -EINVAL; + + i = scnprintf(buf, size, "%u %u\n", spdm_data->config_data.pl_freqs[0], + spdm_data->config_data.pl_freqs[1]); + i = simple_read_from_buffer(data, size, offset, buf, i); + + memset(buf, 0, sizeof(buf)); + return i; +} + +static const struct file_operations pl_fops = { + .open = spdm_open, + .write = pl_write, + .read = pl_read, +}; + +static ssize_t rejrate_low_write(struct file *file, const char __user *data, + size_t size, loff_t *offset) +{ + struct spdm_data *spdm_data = file->private_data; + struct spdm_args desc = { { 0 } }; + int ext_status = 0; + + if (size > sizeof(buf) - 1) + return -EINVAL; + + if (copy_from_user(buf, data, size)) { + size = -EINVAL; + goto out; + } + + buf[size] = '\0'; + + if (sscanf(buf, "%u %u\n", &spdm_data->config_data.reject_rate[0], + &spdm_data->config_data.reject_rate[1]) != 2) { + size = -EINVAL; + goto out; + } + + desc.arg[0] = SPDM_CMD_CFG_REJRATE_LOW; + desc.arg[1] = spdm_data->spdm_client; + desc.arg[2] = spdm_data->config_data.reject_rate[0]; + desc.arg[3] = spdm_data->config_data.reject_rate[1]; + ext_status = spdm_ext_call(&desc, 4); + if (ext_status) + pr_err("External command %u failed with error %u", + (int)desc.arg[0], ext_status); + *offset += size; +out: + memset(buf, 0, sizeof(buf)); + return size; +} + +static ssize_t rejrate_low_read(struct file *file, char __user *data, + size_t size, loff_t *offset) +{ + struct spdm_data *spdm_data = file->private_data; + int i = 32; + + if (size > sizeof(buf)) + return -EINVAL; + + i = scnprintf(buf, size, "%u %u\n", + spdm_data->config_data.reject_rate[0], + spdm_data->config_data.reject_rate[1]); + + i = simple_read_from_buffer(data, size, offset, buf, i); + + memset(buf, 0, sizeof(buf)); + return i; +} + +static const struct file_operations rrl_fops = { + .open = spdm_open, + .write = rejrate_low_write, + .read = rejrate_low_read, +}; + +static ssize_t rejrate_med_write(struct file *file, const char __user *data, + size_t size, loff_t *offset) +{ + struct spdm_data *spdm_data = file->private_data; + struct spdm_args desc = { { 0 } }; + int ext_status = 0; + + if (size > sizeof(buf) - 1) + return -EINVAL; + + if (copy_from_user(buf, data, size)) { + size = -EINVAL; + goto out; + } + + buf[size] = '\0'; + + if (sscanf(buf, "%u %u\n", &spdm_data->config_data.reject_rate[2], + &spdm_data->config_data.reject_rate[3]) != 2) { + size = -EINVAL; + goto out; + } + + desc.arg[0] = SPDM_CMD_CFG_REJRATE_MED; + desc.arg[1] = spdm_data->spdm_client; + desc.arg[2] = spdm_data->config_data.reject_rate[2]; + desc.arg[3] = spdm_data->config_data.reject_rate[3]; + ext_status = spdm_ext_call(&desc, 4); + if (ext_status) + pr_err("External command %u failed with error %u", + (int)desc.arg[0], ext_status); + *offset += size; +out: + memset(buf, 0, sizeof(buf)); + return size; +} + +static ssize_t rejrate_med_read(struct file *file, char __user *data, + size_t size, loff_t *offset) +{ + struct spdm_data *spdm_data = file->private_data; + int i = 32; + + if (size > sizeof(buf)) + return -EINVAL; + + i = scnprintf(buf, size, "%u %u\n", + spdm_data->config_data.reject_rate[2], + spdm_data->config_data.reject_rate[3]); + + i = simple_read_from_buffer(data, size, offset, buf, i); + memset(buf, 0, sizeof(buf)); + return i; +} + +static const struct file_operations rrm_fops = { + .open = spdm_open, + .write = rejrate_med_write, + .read = rejrate_med_read, +}; + +static ssize_t rejrate_high_write(struct file *file, const char __user *data, + size_t size, loff_t *offset) +{ + struct spdm_data *spdm_data = file->private_data; + struct spdm_args desc = { { 0 } }; + int ext_status = 0; + + if (size > sizeof(buf) - 1) + return -EINVAL; + + if (copy_from_user(buf, data, size)) { + size = -EINVAL; + goto out; + } + + buf[size] = '\0'; + + if (sscanf(buf, "%u %u\n", &spdm_data->config_data.reject_rate[4], + &spdm_data->config_data.reject_rate[5]) != 2) { + size = -EINVAL; + goto out; + } + + desc.arg[0] = SPDM_CMD_CFG_REJRATE_HIGH; + desc.arg[1] = spdm_data->spdm_client; + desc.arg[2] = spdm_data->config_data.reject_rate[4]; + desc.arg[3] = spdm_data->config_data.reject_rate[5]; + ext_status = spdm_ext_call(&desc, 4); + if (ext_status) + pr_err("External command %u failed with error %u", + (int)desc.arg[0], ext_status); + *offset += size; +out: + memset(buf, 0, sizeof(buf)); + return size; +} + +static ssize_t rejrate_high_read(struct file *file, char __user *data, + size_t size, loff_t *offset) +{ + struct spdm_data *spdm_data = file->private_data; + int i = 32; + + if (size > sizeof(buf)) + return -EINVAL; + + i = scnprintf(buf, size, "%u %u\n", + spdm_data->config_data.reject_rate[4], + spdm_data->config_data.reject_rate[5]); + + i = simple_read_from_buffer(data, size, offset, buf, i); + memset(buf, 0, sizeof(buf)); + return i; +} + +static const struct file_operations rrh_fops = { + .open = spdm_open, + .write = rejrate_high_write, + .read = rejrate_high_read, +}; + +static ssize_t resptime_low_write(struct file *file, const char __user *data, + size_t size, loff_t *offset) +{ + struct spdm_data *spdm_data = file->private_data; + struct spdm_args desc = { { 0 } }; + int ext_status = 0; + + if (size > sizeof(buf) - 1) + return -EINVAL; + + if (copy_from_user(buf, data, size)) { + size = -EINVAL; + goto out; + } + + buf[size] = '\0'; + + if (sscanf(buf, "%u %u\n", &spdm_data->config_data.response_time_us[0], + &spdm_data->config_data.response_time_us[1]) != 2) { + size = -EINVAL; + goto out; + } + + desc.arg[0] = SPDM_CMD_CFG_RESPTIME_LOW; + desc.arg[1] = spdm_data->spdm_client; + desc.arg[2] = spdm_data->config_data.response_time_us[0]; + desc.arg[3] = spdm_data->config_data.response_time_us[1]; + ext_status = spdm_ext_call(&desc, 4); + if (ext_status) + pr_err("External command %u failed with error %u", + (int)desc.arg[0], ext_status); + *offset += size; +out: + memset(buf, 0, sizeof(buf)); + return size; +} + +static ssize_t resptime_low_read(struct file *file, char __user *data, + size_t size, loff_t *offset) +{ + struct spdm_data *spdm_data = file->private_data; + int i = 32; + + if (size > sizeof(buf)) + return -EINVAL; + + i = scnprintf(buf, size, "%u %u\n", + spdm_data->config_data.response_time_us[0], + spdm_data->config_data.response_time_us[1]); + + i = simple_read_from_buffer(data, size, offset, buf, i); + memset(buf, 0, sizeof(buf)); + return i; +} + +static const struct file_operations rtl_fops = { + .open = spdm_open, + .write = resptime_low_write, + .read = resptime_low_read, +}; + +static ssize_t resptime_med_write(struct file *file, const char __user *data, + size_t size, loff_t *offset) +{ + struct spdm_data *spdm_data = file->private_data; + struct spdm_args desc = { { 0 } }; + int ext_status = 0; + + if (size > sizeof(buf) - 1) + return -EINVAL; + + if (copy_from_user(buf, data, size)) { + size = -EINVAL; + goto out; + } + + buf[size] = '\0'; + + if (sscanf(buf, "%u %u\n", &spdm_data->config_data.response_time_us[2], + &spdm_data->config_data.response_time_us[3]) != 2) { + size = -EINVAL; + goto out; + } + + desc.arg[0] = SPDM_CMD_CFG_RESPTIME_MED; + desc.arg[1] = spdm_data->spdm_client; + desc.arg[2] = spdm_data->config_data.response_time_us[2]; + desc.arg[3] = spdm_data->config_data.response_time_us[3]; + ext_status = spdm_ext_call(&desc, 4); + if (ext_status) + pr_err("External command %u failed with error %u", + (int)desc.arg[0], ext_status); + *offset += size; +out: + memset(buf, 0, sizeof(buf)); + return size; +} + +static ssize_t resptime_med_read(struct file *file, char __user *data, + size_t size, loff_t *offset) +{ + struct spdm_data *spdm_data = file->private_data; + int i = 32; + + if (size > sizeof(buf)) + return -EINVAL; + + i = scnprintf(buf, size, "%u %u\n", + spdm_data->config_data.response_time_us[2], + spdm_data->config_data.response_time_us[3]); + + i = simple_read_from_buffer(data, size, offset, buf, i); + memset(buf, 0, sizeof(buf)); + return i; +} + +static const struct file_operations rtm_fops = { + .open = spdm_open, + .write = resptime_med_write, + .read = resptime_med_read, +}; + +static ssize_t resptime_high_write(struct file *file, const char __user *data, + size_t size, loff_t *offset) +{ + struct spdm_data *spdm_data = file->private_data; + struct spdm_args desc = { { 0 } }; + int ext_status = 0; + + if (size > sizeof(buf) - 1) + return -EINVAL; + + if (copy_from_user(buf, data, size)) { + size = -EINVAL; + goto out; + } + + buf[size] = '\0'; + + if (sscanf(buf, "%u %u\n", &spdm_data->config_data.response_time_us[4], + &spdm_data->config_data.response_time_us[5]) != 2) { + size = -EINVAL; + goto out; + } + + desc.arg[0] = SPDM_CMD_CFG_RESPTIME_HIGH; + desc.arg[1] = spdm_data->spdm_client; + desc.arg[2] = spdm_data->config_data.response_time_us[4]; + desc.arg[3] = spdm_data->config_data.response_time_us[5]; + ext_status = spdm_ext_call(&desc, 4); + if (ext_status) + pr_err("External command %u failed with error %u", + (int)desc.arg[0], ext_status); + *offset += size; +out: + memset(buf, 0, sizeof(buf)); + return size; +} + +static ssize_t resptime_high_read(struct file *file, char __user *data, + size_t size, loff_t *offset) +{ + struct spdm_data *spdm_data = file->private_data; + int i = 32; + + if (size > sizeof(buf)) + return -EINVAL; + + i = scnprintf(buf, size, "%u %u\n", + spdm_data->config_data.response_time_us[4], + spdm_data->config_data.response_time_us[5]); + + i = simple_read_from_buffer(data, size, offset, buf, i); + memset(buf, 0, sizeof(buf)); + return i; +} + +static const struct file_operations rth_fops = { + .open = spdm_open, + .write = resptime_high_write, + .read = resptime_high_read, +}; + +static ssize_t cciresptime_low_write(struct file *file, + const char __user *data, size_t size, + loff_t *offset) +{ + struct spdm_data *spdm_data = file->private_data; + struct spdm_args desc = { { 0 } }; + int ext_status = 0; + + if (size > sizeof(buf) - 1) + return -EINVAL; + + if (copy_from_user(buf, data, size)) { + size = -EINVAL; + goto out; + } + + buf[size] = '\0'; + + if (sscanf(buf, "%u %u\n", + &spdm_data->config_data.cci_response_time_us[0], + &spdm_data->config_data.cci_response_time_us[1]) != 2) { + size = -EINVAL; + goto out; + } + + desc.arg[0] = SPDM_CMD_CFG_CCIRESPTIME_LOW; + desc.arg[1] = spdm_data->spdm_client; + desc.arg[2] = spdm_data->config_data.cci_response_time_us[0]; + desc.arg[3] = spdm_data->config_data.cci_response_time_us[1]; + ext_status = spdm_ext_call(&desc, 4); + if (ext_status) + pr_err("External command %u failed with error %u", + (int)desc.arg[0], ext_status); + *offset += size; +out: + memset(buf, 0, sizeof(buf)); + return size; +} + +static ssize_t cciresptime_low_read(struct file *file, char __user *data, + size_t size, loff_t *offset) +{ + struct spdm_data *spdm_data = file->private_data; + int i = 32; + + if (size > sizeof(buf)) + return -EINVAL; + + i = scnprintf(buf, size, "%u %u\n", + spdm_data->config_data.cci_response_time_us[0], + spdm_data->config_data.cci_response_time_us[1]); + + i = simple_read_from_buffer(data, size, offset, buf, i); + memset(buf, 0, sizeof(buf)); + return i; +} + +static const struct file_operations ccil_fops = { + .open = spdm_open, + .write = cciresptime_low_write, + .read = cciresptime_low_read, +}; + +static ssize_t cciresptime_med_write(struct file *file, + const char __user *data, size_t size, + loff_t *offset) +{ + struct spdm_data *spdm_data = file->private_data; + struct spdm_args desc = { { 0 } }; + int ext_status = 0; + + if (size > sizeof(buf) - 1) + return -EINVAL; + + if (copy_from_user(buf, data, size)) { + size = -EINVAL; + goto out; + } + + buf[size] = '\0'; + + if (sscanf(buf, "%u %u\n", + &spdm_data->config_data.cci_response_time_us[2], + &spdm_data->config_data.cci_response_time_us[3]) != 2) { + size = -EINVAL; + goto out; + } + + desc.arg[0] = SPDM_CMD_CFG_CCIRESPTIME_MED; + desc.arg[1] = spdm_data->spdm_client; + desc.arg[2] = spdm_data->config_data.cci_response_time_us[2]; + desc.arg[3] = spdm_data->config_data.cci_response_time_us[3]; + ext_status = spdm_ext_call(&desc, 4); + if (ext_status) + pr_err("External command %u failed with error %u", + (int)desc.arg[0], ext_status); + *offset += size; +out: + memset(buf, 0, sizeof(buf)); + return size; +} + +static ssize_t cciresptime_med_read(struct file *file, char __user *data, + size_t size, loff_t *offset) +{ + struct spdm_data *spdm_data = file->private_data; + int i = 32; + + if (size > sizeof(buf)) + return -EINVAL; + + i = scnprintf(buf, size, "%u %u\n", + spdm_data->config_data.cci_response_time_us[2], + spdm_data->config_data.cci_response_time_us[3]); + + i = simple_read_from_buffer(data, size, offset, buf, i); + memset(buf, 0, sizeof(buf)); + return i; +} + +static const struct file_operations ccim_fops = { + .open = spdm_open, + .write = cciresptime_med_write, + .read = cciresptime_med_read, +}; + +static ssize_t cciresptime_high_write(struct file *file, + const char __user *data, + size_t size, loff_t *offset) +{ + struct spdm_data *spdm_data = file->private_data; + struct spdm_args desc = { { 0 } }; + int ext_status = 0; + + if (size > sizeof(buf) - 1) + return -EINVAL; + + if (copy_from_user(buf, data, size)) { + size = -EINVAL; + goto out; + } + + buf[size] = '\0'; + + if (sscanf(buf, "%u %u\n", + &spdm_data->config_data.cci_response_time_us[4], + &spdm_data->config_data.cci_response_time_us[5]) != 2){ + size = -EINVAL; + goto out; + } + + desc.arg[0] = SPDM_CMD_CFG_CCIRESPTIME_HIGH; + desc.arg[1] = spdm_data->spdm_client; + desc.arg[2] = spdm_data->config_data.cci_response_time_us[4]; + desc.arg[3] = spdm_data->config_data.cci_response_time_us[5]; + ext_status = spdm_ext_call(&desc, 4); + if (ext_status) + pr_err("External command %u failed with error %u", + (int)desc.arg[0], ext_status); + *offset += size; +out: + memset(buf, 0, sizeof(buf)); + return size; +} + +static ssize_t cciresptime_high_read(struct file *file, char __user *data, + size_t size, loff_t *offset) +{ + struct spdm_data *spdm_data = file->private_data; + int i = 32; + + if (size > sizeof(buf)) + return -EINVAL; + + i = scnprintf(buf, size, "%u %u\n", + spdm_data->config_data.cci_response_time_us[4], + spdm_data->config_data.cci_response_time_us[5]); + + i = simple_read_from_buffer(data, size, offset, buf, i); + memset(buf, 0, sizeof(buf)); + return i; +} + +static const struct file_operations ccih_fops = { + .open = spdm_open, + .write = cciresptime_high_write, + .read = cciresptime_high_read, +}; + +static ssize_t cci_max_write(struct file *file, const char __user *data, + size_t size, loff_t *offset) +{ + struct spdm_data *spdm_data = file->private_data; + struct spdm_args desc = { { 0 } }; + int ext_status = 0; + + if (size > sizeof(buf) - 1) + return -EINVAL; + + if (copy_from_user(buf, data, size)) { + size = -EINVAL; + goto out; + } + + buf[size] = '\0'; + + if (sscanf(buf, "%u\n", &spdm_data->config_data.max_cci_freq) != 1) { + size = -EINVAL; + goto out; + } + + desc.arg[0] = SPDM_CMD_CFG_MAXCCI; + desc.arg[1] = spdm_data->spdm_client; + desc.arg[2] = spdm_data->config_data.max_cci_freq; + ext_status = spdm_ext_call(&desc, 3); + if (ext_status) + pr_err("External command %u failed with error %u", + (int)desc.arg[0], ext_status); + *offset += size; +out: + memset(buf, 0, sizeof(buf)); + return size; +} + +static ssize_t cci_max_read(struct file *file, char __user *data, + size_t size, loff_t *offset) +{ + struct spdm_data *spdm_data = file->private_data; + int i = 32; + + if (size > sizeof(buf)) + return -EINVAL; + + i = scnprintf(buf, size, "%u\n", spdm_data->config_data.max_cci_freq); + + i = simple_read_from_buffer(data, size, offset, buf, i); + memset(buf, 0, sizeof(buf)); + return i; +} + +static const struct file_operations ccimax_fops = { + .open = spdm_open, + .write = cci_max_write, + .read = cci_max_read, +}; + +static ssize_t vote_cfg_write(struct file *file, const char __user *data, + size_t size, loff_t *offset) +{ + struct spdm_data *spdm_data = file->private_data; + struct spdm_args desc = { { 0 } }; + int ext_status = 0; + + if (size > sizeof(buf) - 1) + return -EINVAL; + + if (copy_from_user(buf, data, size)) { + size = -EINVAL; + goto out; + } + + buf[size] = '\0'; + + if (sscanf(buf, "%u %u %u %u\n", &spdm_data->config_data.upstep, + &spdm_data->config_data.downstep, + &spdm_data->config_data.max_vote, + &spdm_data->config_data.up_step_multp) != 4) { + size = -EINVAL; + goto out; + } + + desc.arg[0] = SPDM_CMD_CFG_VOTES; + desc.arg[1] = spdm_data->spdm_client; + desc.arg[2] = spdm_data->config_data.upstep; + desc.arg[3] = spdm_data->config_data.downstep; + desc.arg[4] = spdm_data->config_data.max_vote; + desc.arg[5] = spdm_data->config_data.up_step_multp; + ext_status = spdm_ext_call(&desc, 6); + if (ext_status) + pr_err("External command %u failed with error %u", + (int)desc.arg[0], ext_status); + *offset += size; +out: + memset(buf, 0, sizeof(buf)); + return size; +} + +static ssize_t vote_cfg_read(struct file *file, char __user *data, + size_t size, loff_t *offset) +{ + struct spdm_data *spdm_data = file->private_data; + int i = 32; + + if (size > sizeof(buf)) + return -EINVAL; + + i = scnprintf(buf, size, "%u %u %u %u\n", + spdm_data->config_data.upstep, + spdm_data->config_data.downstep, + spdm_data->config_data.max_vote, + spdm_data->config_data.up_step_multp); + + i = simple_read_from_buffer(data, size, offset, buf, i); + memset(buf, 0, sizeof(buf)); + return i; +} + +static const struct file_operations vote_fops = { + .open = spdm_open, + .write = vote_cfg_write, + .read = vote_cfg_read, +}; + +void spdm_init_debugfs(struct device *dev) +{ + struct spdm_data *data = 0; + + data = dev_get_drvdata(dev); + data->debugfs_dir = debugfs_create_dir(dev_name(dev), NULL); + + debugfs_create_file("enable", 0600, data->debugfs_dir, data, + &enable_fops); + debugfs_create_file("pl_freqs", 0600, data->debugfs_dir, data, + &pl_fops); + debugfs_create_file("rej_rate_low", 0600, data->debugfs_dir, data, + &rrl_fops); + debugfs_create_file("rej_rate_med", 0600, data->debugfs_dir, data, + &rrm_fops); + debugfs_create_file("rej_rate_high", 0600, data->debugfs_dir, data, + &rrh_fops); + debugfs_create_file("resp_time_low", 0600, data->debugfs_dir, data, + &rtl_fops); + debugfs_create_file("resp_time_med", 0600, data->debugfs_dir, data, + &rtm_fops); + debugfs_create_file("resp_time_high", 0600, data->debugfs_dir, data, + &rth_fops); + debugfs_create_file("cci_resp_time_low", 0600, data->debugfs_dir, data, + &ccil_fops); + debugfs_create_file("cci_resp_time_med", 0600, data->debugfs_dir, data, + &ccim_fops); + debugfs_create_file("cci_resp_time_high", 0600, data->debugfs_dir, + data, &ccih_fops); + debugfs_create_file("cci_max", 0600, data->debugfs_dir, data, + &ccimax_fops); + debugfs_create_file("vote_cfg", 0600, data->debugfs_dir, data, + &vote_fops); +} + +void spdm_remove_debugfs(struct spdm_data *data) +{ + debugfs_remove_recursive(data->debugfs_dir); +} + +MODULE_LICENSE("GPL v2"); --- /dev/null 2019-10-24 16:47:25.704025805 +0200 +++ linux-4.4.115-fbx/drivers/devfreq/devfreq_spdm.h 2019-01-22 16:16:23.135243074 +0100 @@ -0,0 +1,130 @@ +/* +*Copyright (c) 2014-2015, The Linux Foundation. All rights reserved. +* +*This program is free software; you can redistribute it and/or modify +*it under the terms of the GNU General Public License version 2 and +*only version 2 as published by the Free Software Foundation. +* +*This program is distributed in the hope that it will be useful, +*but WITHOUT ANY WARRANTY; without even the implied warranty of +*MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +*GNU General Public License for more details. +*/ + +#ifndef DEVFREQ_SPDM_H +#define DEVFREQ_SPDM_H + +#include +#include +#include + +enum pl_levels { SPDM_PL1, SPDM_PL2, SPDM_PL3, SPDM_PL_COUNT }; +enum actions { SPDM_UP, SPDM_DOWN }; +enum spdm_client { SPDM_CLIENT_CPU, SPDM_CLIENT_GPU, SPDM_CLIENT_COUNT }; + +struct spdm_config_data { + /* in MB/s */ + u32 upstep; + u32 downstep; + u32 up_step_multp; + + u32 num_ports; + u32 *ports; + u32 aup; + u32 adown; + u32 bucket_size; + + /* + * If We define n PL levels we need n-1 frequencies to tell + * where to change from one pl to another + */ + /* hz */ + u32 pl_freqs[SPDM_PL_COUNT - 1]; + /* + * We have a low threshold and a high threhold for each pl to support + * the two port solution so we need twice as many entries as + * performance levels + */ + /* in 100th's of a percent */ + u32 reject_rate[SPDM_PL_COUNT * 2]; + u32 response_time_us[SPDM_PL_COUNT * 2]; + u32 cci_response_time_us[SPDM_PL_COUNT * 2]; + /* hz */ + u32 max_cci_freq; + /* in MB/s */ + u32 max_vote; + +}; + +struct spdm_data { + /* bus scaling data */ + int cur_idx; + struct msm_bus_scale_pdata *pdata; + u32 bus_scale_client_id; + /* in mb/s */ + u32 new_bw; + + /* devfreq data */ + struct devfreq *devfreq; + struct devfreq_dev_profile *profile; + unsigned long action; + int window; + struct clk *cci_clk; + + /* spdm hw/gov data */ + struct spdm_config_data config_data; + + enum spdm_client spdm_client; + /* list used by governor to keep track of spdm devices */ + struct list_head list; + + struct dentry *debugfs_dir; + + bool enabled; +}; + +extern void spdm_init_debugfs(struct device *dev); +extern void spdm_remove_debugfs(struct spdm_data *data); + +#define SPDM_HYP_FNID 5 +#define SPDM_SCM_SVC_ID 0x9 +#define SPDM_SCM_CMD_ID 0x4 +#define SPDM_TZ_VERSION 0x20000 /* TZ SPDM driver version */ +/* SPDM CMD ID's for hypervisor/SCM */ +#define SPDM_CMD_GET_VERSION 0 +#define SPDM_CMD_GET_BW_ALL 1 +#define SPDM_CMD_GET_BW_SPECIFIC 2 +#define SPDM_CMD_ENABLE 3 +#define SPDM_CMD_DISABLE 4 +#define SPDM_CMD_CFG_PORTS 5 +#define SPDM_CMD_CFG_FLTR 6 +#define SPDM_CMD_CFG_PL 7 +#define SPDM_CMD_CFG_REJRATE_LOW 8 +#define SPDM_CMD_CFG_REJRATE_MED 9 +#define SPDM_CMD_CFG_REJRATE_HIGH 10 +#define SPDM_CMD_CFG_RESPTIME_LOW 11 +#define SPDM_CMD_CFG_RESPTIME_MED 12 +#define SPDM_CMD_CFG_RESPTIME_HIGH 13 +#define SPDM_CMD_CFG_CCIRESPTIME_LOW 14 +#define SPDM_CMD_CFG_CCIRESPTIME_MED 15 +#define SPDM_CMD_CFG_CCIRESPTIME_HIGH 16 +#define SPDM_CMD_CFG_MAXCCI 17 +#define SPDM_CMD_CFG_VOTES 18 + +#define SPDM_MAX_ARGS 6 +#define SPDM_MAX_RETS 3 + +struct spdm_args { + u64 arg[SPDM_MAX_ARGS]; + u64 ret[SPDM_MAX_RETS]; +}; + +extern int __spdm_hyp_call(struct spdm_args *args, int num_args); +extern int __spdm_scm_call(struct spdm_args *args, int num_args); + +#ifdef CONFIG_SPDM_SCM +#define spdm_ext_call __spdm_scm_call +#else +#define spdm_ext_call __spdm_hyp_call +#endif +#endif --- /dev/null 2019-10-24 16:47:25.704025805 +0200 +++ linux-4.4.115-fbx/drivers/devfreq/governor_bw_hwmon.c 2019-01-22 16:16:23.135243074 +0100 @@ -0,0 +1,983 @@ +/* + * Copyright (c) 2013-2017, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define pr_fmt(fmt) "bw-hwmon: " fmt + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "governor.h" +#include "governor_bw_hwmon.h" + +#define NUM_MBPS_ZONES 10 +struct hwmon_node { + unsigned int guard_band_mbps; + unsigned int decay_rate; + unsigned int io_percent; + unsigned int bw_step; + unsigned int sample_ms; + unsigned int up_scale; + unsigned int up_thres; + unsigned int down_thres; + unsigned int down_count; + unsigned int hist_memory; + unsigned int hyst_trigger_count; + unsigned int hyst_length; + unsigned int idle_mbps; + unsigned int low_power_ceil_mbps; + unsigned int low_power_io_percent; + unsigned int low_power_delay; + unsigned int mbps_zones[NUM_MBPS_ZONES]; + + unsigned long prev_ab; + unsigned long *dev_ab; + unsigned long resume_freq; + unsigned long resume_ab; + unsigned long bytes; + unsigned long max_mbps; + unsigned long hist_max_mbps; + unsigned long hist_mem; + unsigned long hyst_peak; + unsigned long hyst_mbps; + unsigned long hyst_trig_win; + unsigned long hyst_en; + unsigned long above_low_power; + unsigned long prev_req; + unsigned int wake; + unsigned int down_cnt; + ktime_t prev_ts; + ktime_t hist_max_ts; + bool sampled; + bool mon_started; + struct list_head list; + void *orig_data; + struct bw_hwmon *hw; + struct devfreq_governor *gov; + struct attribute_group *attr_grp; +}; + +#define UP_WAKE 1 +#define DOWN_WAKE 2 +static DEFINE_SPINLOCK(irq_lock); + +static LIST_HEAD(hwmon_list); +static DEFINE_MUTEX(list_lock); +static DEFINE_MUTEX(sync_lock); + + +static int use_cnt; +static DEFINE_MUTEX(state_lock); + +#define show_attr(name) \ +static ssize_t show_##name(struct device *dev, \ + struct device_attribute *attr, char *buf) \ +{ \ + struct devfreq *df = to_devfreq(dev); \ + struct hwmon_node *hw = df->data; \ + return snprintf(buf, PAGE_SIZE, "%u\n", hw->name); \ +} + +#define store_attr(name, _min, _max) \ +static ssize_t store_##name(struct device *dev, \ + struct device_attribute *attr, const char *buf, \ + size_t count) \ +{ \ + struct devfreq *df = to_devfreq(dev); \ + struct hwmon_node *hw = df->data; \ + int ret; \ + unsigned int val; \ + ret = sscanf(buf, "%u", &val); \ + if (ret != 1) \ + return -EINVAL; \ + val = max(val, _min); \ + val = min(val, _max); \ + hw->name = val; \ + return count; \ +} + +#define gov_attr(__attr, min, max) \ +show_attr(__attr) \ +store_attr(__attr, min, max) \ +static DEVICE_ATTR(__attr, 0644, show_##__attr, store_##__attr) + +#define show_list_attr(name, n) \ +static ssize_t show_list_##name(struct device *dev, \ + struct device_attribute *attr, char *buf) \ +{ \ + struct devfreq *df = to_devfreq(dev); \ + struct hwmon_node *hw = df->data; \ + unsigned int i, cnt = 0; \ + \ + for (i = 0; i < n && hw->name[i]; i++) \ + cnt += snprintf(buf + cnt, PAGE_SIZE, "%u ", hw->name[i]);\ + cnt += snprintf(buf + cnt, PAGE_SIZE, "\n"); \ + return cnt; \ +} + +#define store_list_attr(name, n, _min, _max) \ +static ssize_t store_list_##name(struct device *dev, \ + struct device_attribute *attr, const char *buf, \ + size_t count) \ +{ \ + struct devfreq *df = to_devfreq(dev); \ + struct hwmon_node *hw = df->data; \ + int ret; \ + unsigned int i = 0, val; \ + \ + do { \ + ret = sscanf(buf, "%u", &val); \ + if (ret != 1) \ + break; \ + buf = strnchr(buf, PAGE_SIZE, ' '); \ + if (buf) \ + buf++; \ + val = max(val, _min); \ + val = min(val, _max); \ + hw->name[i] = val; \ + i++; \ + } while (buf && i < n - 1); \ + if (i < 1) \ + return -EINVAL; \ + hw->name[i] = 0; \ + return count; \ +} + +#define gov_list_attr(__attr, n, min, max) \ +show_list_attr(__attr, n) \ +store_list_attr(__attr, n, min, max) \ +static DEVICE_ATTR(__attr, 0644, show_list_##__attr, store_list_##__attr) + +#define MIN_MS 10U +#define MAX_MS 500U + +/* Returns MBps of read/writes for the sampling window. */ +static unsigned int bytes_to_mbps(long long bytes, unsigned int us) +{ + bytes *= USEC_PER_SEC; + do_div(bytes, us); + bytes = DIV_ROUND_UP_ULL(bytes, SZ_1M); + return bytes; +} + +static unsigned int mbps_to_bytes(unsigned long mbps, unsigned int ms) +{ + mbps *= ms; + mbps = DIV_ROUND_UP(mbps, MSEC_PER_SEC); + mbps *= SZ_1M; + return mbps; +} + +static int __bw_hwmon_sw_sample_end(struct bw_hwmon *hwmon) +{ + struct devfreq *df; + struct hwmon_node *node; + ktime_t ts; + unsigned long bytes, mbps; + unsigned int us; + int wake = 0; + + df = hwmon->df; + node = df->data; + + ts = ktime_get(); + us = ktime_to_us(ktime_sub(ts, node->prev_ts)); + + bytes = hwmon->get_bytes_and_clear(hwmon); + bytes += node->bytes; + node->bytes = 0; + + mbps = bytes_to_mbps(bytes, us); + node->max_mbps = max(node->max_mbps, mbps); + + /* + * If the measured bandwidth in a micro sample is greater than the + * wake up threshold, it indicates an increase in load that's non + * trivial. So, have the governor ignore historical idle time or low + * bandwidth usage and do the bandwidth calculation based on just + * this micro sample. + */ + if (mbps > node->hw->up_wake_mbps) { + wake = UP_WAKE; + } else if (mbps < node->hw->down_wake_mbps) { + if (node->down_cnt) + node->down_cnt--; + if (node->down_cnt <= 0) + wake = DOWN_WAKE; + } + + node->prev_ts = ts; + node->wake = wake; + node->sampled = true; + + trace_bw_hwmon_meas(dev_name(df->dev.parent), + mbps, + us, + wake); + + return wake; +} + +static int __bw_hwmon_hw_sample_end(struct bw_hwmon *hwmon) +{ + struct devfreq *df; + struct hwmon_node *node; + unsigned long bytes, mbps; + int wake = 0; + + df = hwmon->df; + node = df->data; + + /* + * If this read is in response to an IRQ, the HW monitor should + * return the measurement in the micro sample that triggered the IRQ. + * Otherwise, it should return the maximum measured value in any + * micro sample since the last time we called get_bytes_and_clear() + */ + bytes = hwmon->get_bytes_and_clear(hwmon); + mbps = bytes_to_mbps(bytes, node->sample_ms * USEC_PER_MSEC); + node->max_mbps = mbps; + + if (mbps > node->hw->up_wake_mbps) + wake = UP_WAKE; + else if (mbps < node->hw->down_wake_mbps) + wake = DOWN_WAKE; + + node->wake = wake; + node->sampled = true; + + trace_bw_hwmon_meas(dev_name(df->dev.parent), + mbps, + node->sample_ms * USEC_PER_MSEC, + wake); + + return 1; +} + +static int __bw_hwmon_sample_end(struct bw_hwmon *hwmon) +{ + if (hwmon->set_hw_events) + return __bw_hwmon_hw_sample_end(hwmon); + else + return __bw_hwmon_sw_sample_end(hwmon); +} + +int bw_hwmon_sample_end(struct bw_hwmon *hwmon) +{ + unsigned long flags; + int wake; + + spin_lock_irqsave(&irq_lock, flags); + wake = __bw_hwmon_sample_end(hwmon); + spin_unlock_irqrestore(&irq_lock, flags); + + return wake; +} + +unsigned long to_mbps_zone(struct hwmon_node *node, unsigned long mbps) +{ + int i; + + for (i = 0; i < NUM_MBPS_ZONES && node->mbps_zones[i]; i++) + if (node->mbps_zones[i] >= mbps) + return node->mbps_zones[i]; + + return node->hw->df->max_freq; +} + +#define MIN_MBPS 500UL +#define HIST_PEAK_TOL 60 +static unsigned long get_bw_and_set_irq(struct hwmon_node *node, + unsigned long *freq, unsigned long *ab) +{ + unsigned long meas_mbps, thres, flags, req_mbps, adj_mbps; + unsigned long meas_mbps_zone; + unsigned long hist_lo_tol, hyst_lo_tol; + struct bw_hwmon *hw = node->hw; + unsigned int new_bw, io_percent; + ktime_t ts; + unsigned int ms = 0; + + spin_lock_irqsave(&irq_lock, flags); + + if (!hw->set_hw_events) { + ts = ktime_get(); + ms = ktime_to_ms(ktime_sub(ts, node->prev_ts)); + } + if (!node->sampled || ms >= node->sample_ms) + __bw_hwmon_sample_end(node->hw); + node->sampled = false; + + req_mbps = meas_mbps = node->max_mbps; + node->max_mbps = 0; + + hist_lo_tol = (node->hist_max_mbps * HIST_PEAK_TOL) / 100; + /* Remember historic peak in the past hist_mem decision windows. */ + if (meas_mbps > node->hist_max_mbps || !node->hist_mem) { + /* If new max or no history */ + node->hist_max_mbps = meas_mbps; + node->hist_mem = node->hist_memory; + } else if (meas_mbps >= hist_lo_tol) { + /* + * If subsequent peaks come close (within tolerance) to but + * less than the historic peak, then reset the history start, + * but not the peak value. + */ + node->hist_mem = node->hist_memory; + } else { + /* Count down history expiration. */ + if (node->hist_mem) + node->hist_mem--; + } + + /* Keep track of whether we are in low power mode consistently. */ + if (meas_mbps > node->low_power_ceil_mbps) + node->above_low_power = node->low_power_delay; + if (node->above_low_power) + node->above_low_power--; + + if (node->above_low_power) + io_percent = node->io_percent; + else + io_percent = node->low_power_io_percent; + + /* + * The AB value that corresponds to the lowest mbps zone greater than + * or equal to the "frequency" the current measurement will pick. + * This upper limit is useful for balancing out any prediction + * mechanisms to be power friendly. + */ + meas_mbps_zone = (meas_mbps * 100) / io_percent; + meas_mbps_zone = to_mbps_zone(node, meas_mbps_zone); + meas_mbps_zone = (meas_mbps_zone * io_percent) / 100; + meas_mbps_zone = max(meas_mbps, meas_mbps_zone); + + /* + * If this is a wake up due to BW increase, vote much higher BW than + * what we measure to stay ahead of increasing traffic and then set + * it up to vote for measured BW if we see down_count short sample + * windows of low traffic. + */ + if (node->wake == UP_WAKE) { + req_mbps += ((meas_mbps - node->prev_req) + * node->up_scale) / 100; + /* + * However if the measured load is less than the historic + * peak, but the over request is higher than the historic + * peak, then we could limit the over requesting to the + * historic peak. + */ + if (req_mbps > node->hist_max_mbps + && meas_mbps < node->hist_max_mbps) + req_mbps = node->hist_max_mbps; + + req_mbps = min(req_mbps, meas_mbps_zone); + } + + hyst_lo_tol = (node->hyst_mbps * HIST_PEAK_TOL) / 100; + if (meas_mbps > node->hyst_mbps && meas_mbps > MIN_MBPS) { + hyst_lo_tol = (meas_mbps * HIST_PEAK_TOL) / 100; + node->hyst_peak = 0; + node->hyst_trig_win = node->hyst_length; + node->hyst_mbps = meas_mbps; + } + + /* + * Check node->max_mbps to avoid double counting peaks that cause + * early termination of a window. + */ + if (meas_mbps >= hyst_lo_tol && meas_mbps > MIN_MBPS + && !node->max_mbps) { + node->hyst_peak++; + if (node->hyst_peak >= node->hyst_trigger_count + || node->hyst_en) + node->hyst_en = node->hyst_length; + } + + if (node->hyst_trig_win) + node->hyst_trig_win--; + if (node->hyst_en) + node->hyst_en--; + + if (!node->hyst_trig_win && !node->hyst_en) { + node->hyst_peak = 0; + node->hyst_mbps = 0; + } + + if (node->hyst_en) { + if (meas_mbps > node->idle_mbps) + req_mbps = max(req_mbps, node->hyst_mbps); + } + + /* Stretch the short sample window size, if the traffic is too low */ + if (meas_mbps < MIN_MBPS) { + hw->up_wake_mbps = (max(MIN_MBPS, req_mbps) + * (100 + node->up_thres)) / 100; + hw->down_wake_mbps = 0; + hw->undo_over_req_mbps = 0; + thres = mbps_to_bytes(max(MIN_MBPS, req_mbps / 2), + node->sample_ms); + } else { + /* + * Up wake vs down wake are intentionally a percentage of + * req_mbps vs meas_mbps to make sure the over requesting + * phase is handled properly. We only want to wake up and + * reduce the vote based on the measured mbps being less than + * the previous measurement that caused the "over request". + */ + hw->up_wake_mbps = (req_mbps * (100 + node->up_thres)) / 100; + hw->down_wake_mbps = (meas_mbps * node->down_thres) / 100; + if (node->wake == UP_WAKE) + hw->undo_over_req_mbps = min(req_mbps, meas_mbps_zone); + else + hw->undo_over_req_mbps = 0; + thres = mbps_to_bytes(meas_mbps, node->sample_ms); + } + + if (hw->set_hw_events) { + hw->down_cnt = node->down_count; + hw->set_hw_events(hw, node->sample_ms); + } else { + node->down_cnt = node->down_count; + node->bytes = hw->set_thres(hw, thres); + } + + node->wake = 0; + node->prev_req = req_mbps; + + spin_unlock_irqrestore(&irq_lock, flags); + + adj_mbps = req_mbps + node->guard_band_mbps; + + if (adj_mbps > node->prev_ab) { + new_bw = adj_mbps; + } else { + new_bw = adj_mbps * node->decay_rate + + node->prev_ab * (100 - node->decay_rate); + new_bw /= 100; + } + + node->prev_ab = new_bw; + if (ab) + *ab = roundup(new_bw, node->bw_step); + + *freq = (new_bw * 100) / io_percent; + trace_bw_hwmon_update(dev_name(node->hw->df->dev.parent), + new_bw, + *freq, + hw->up_wake_mbps, + hw->down_wake_mbps); + return req_mbps; +} + +static struct hwmon_node *find_hwmon_node(struct devfreq *df) +{ + struct hwmon_node *node, *found = NULL; + + mutex_lock(&list_lock); + list_for_each_entry(node, &hwmon_list, list) + if (node->hw->dev == df->dev.parent || + node->hw->of_node == df->dev.parent->of_node || + (!node->hw->dev && !node->hw->of_node && + node->gov == df->governor)) { + found = node; + break; + } + mutex_unlock(&list_lock); + + return found; +} + +int update_bw_hwmon(struct bw_hwmon *hwmon) +{ + struct devfreq *df; + struct hwmon_node *node; + int ret; + + if (!hwmon) + return -EINVAL; + df = hwmon->df; + if (!df) + return -ENODEV; + node = df->data; + if (!node) + return -ENODEV; + + if (!node->mon_started) + return -EBUSY; + + dev_dbg(df->dev.parent, "Got update request\n"); + devfreq_monitor_stop(df); + + mutex_lock(&df->lock); + ret = update_devfreq(df); + if (ret) + dev_err(df->dev.parent, + "Unable to update freq on request!\n"); + mutex_unlock(&df->lock); + + devfreq_monitor_start(df); + + return 0; +} + +static int start_monitor(struct devfreq *df, bool init) +{ + struct hwmon_node *node = df->data; + struct bw_hwmon *hw = node->hw; + struct device *dev = df->dev.parent; + unsigned long mbps; + int ret; + + node->prev_ts = ktime_get(); + + if (init) { + node->prev_ab = 0; + node->resume_freq = 0; + node->resume_ab = 0; + mbps = (df->previous_freq * node->io_percent) / 100; + hw->up_wake_mbps = mbps; + hw->down_wake_mbps = MIN_MBPS; + hw->undo_over_req_mbps = 0; + ret = hw->start_hwmon(hw, mbps); + } else { + ret = hw->resume_hwmon(hw); + } + + if (ret) { + dev_err(dev, "Unable to start HW monitor! (%d)\n", ret); + return ret; + } + + if (init) + devfreq_monitor_start(df); + else + devfreq_monitor_resume(df); + + node->mon_started = true; + + return 0; +} + +static void stop_monitor(struct devfreq *df, bool init) +{ + struct hwmon_node *node = df->data; + struct bw_hwmon *hw = node->hw; + + node->mon_started = false; + + if (init) { + devfreq_monitor_stop(df); + hw->stop_hwmon(hw); + } else { + devfreq_monitor_suspend(df); + hw->suspend_hwmon(hw); + } + +} + +static int gov_start(struct devfreq *df) +{ + int ret = 0; + struct device *dev = df->dev.parent; + struct hwmon_node *node; + struct bw_hwmon *hw; + struct devfreq_dev_status stat; + + node = find_hwmon_node(df); + if (!node) { + dev_err(dev, "Unable to find HW monitor!\n"); + return -ENODEV; + } + hw = node->hw; + + stat.private_data = NULL; + if (df->profile->get_dev_status) + ret = df->profile->get_dev_status(df->dev.parent, &stat); + if (ret || !stat.private_data) + dev_warn(dev, "Device doesn't take AB votes!\n"); + else + node->dev_ab = stat.private_data; + + hw->df = df; + node->orig_data = df->data; + df->data = node; + + if (start_monitor(df, true)) + goto err_start; + + ret = sysfs_create_group(&df->dev.kobj, node->attr_grp); + if (ret) + goto err_sysfs; + + return 0; + +err_sysfs: + stop_monitor(df, true); +err_start: + df->data = node->orig_data; + node->orig_data = NULL; + hw->df = NULL; + node->dev_ab = NULL; + return ret; +} + +static void gov_stop(struct devfreq *df) +{ + struct hwmon_node *node = df->data; + struct bw_hwmon *hw = node->hw; + + sysfs_remove_group(&df->dev.kobj, node->attr_grp); + stop_monitor(df, true); + df->data = node->orig_data; + node->orig_data = NULL; + hw->df = NULL; + /* + * Not all governors know about this additional extended device + * configuration. To avoid leaving the extended configuration at a + * stale state, set it to 0 and let the next governor take it from + * there. + */ + if (node->dev_ab) + *node->dev_ab = 0; + node->dev_ab = NULL; +} + +static int gov_suspend(struct devfreq *df) +{ + struct hwmon_node *node = df->data; + unsigned long resume_freq = df->previous_freq; + unsigned long resume_ab = *node->dev_ab; + + if (!node->hw->suspend_hwmon) + return -ENOSYS; + + if (node->resume_freq) { + dev_warn(df->dev.parent, "Governor already suspended!\n"); + return -EBUSY; + } + + stop_monitor(df, false); + + mutex_lock(&df->lock); + update_devfreq(df); + mutex_unlock(&df->lock); + + node->resume_freq = resume_freq; + node->resume_ab = resume_ab; + + return 0; +} + +static int gov_resume(struct devfreq *df) +{ + struct hwmon_node *node = df->data; + + if (!node->hw->resume_hwmon) + return -ENOSYS; + + if (!node->resume_freq) { + dev_warn(df->dev.parent, "Governor already resumed!\n"); + return -EBUSY; + } + + mutex_lock(&df->lock); + update_devfreq(df); + mutex_unlock(&df->lock); + + node->resume_freq = 0; + node->resume_ab = 0; + + return start_monitor(df, false); +} + +static int devfreq_bw_hwmon_get_freq(struct devfreq *df, + unsigned long *freq, + u32 *flag) +{ + struct hwmon_node *node = df->data; + + /* Suspend/resume sequence */ + if (!node->mon_started) { + *freq = node->resume_freq; + *node->dev_ab = node->resume_ab; + return 0; + } + + get_bw_and_set_irq(node, freq, node->dev_ab); + + return 0; +} + +static ssize_t store_throttle_adj(struct device *dev, + struct device_attribute *attr, const char *buf, size_t count) +{ + struct devfreq *df = to_devfreq(dev); + struct hwmon_node *node = df->data; + int ret; + unsigned int val; + + if (!node->hw->set_throttle_adj) + return -ENOSYS; + + ret = kstrtouint(buf, 10, &val); + if (ret) + return ret; + + ret = node->hw->set_throttle_adj(node->hw, val); + + if (!ret) + return count; + else + return ret; +} + +static ssize_t show_throttle_adj(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct devfreq *df = to_devfreq(dev); + struct hwmon_node *node = df->data; + unsigned int val; + + if (!node->hw->get_throttle_adj) + val = 0; + else + val = node->hw->get_throttle_adj(node->hw); + + return snprintf(buf, PAGE_SIZE, "%u\n", val); +} + +static DEVICE_ATTR(throttle_adj, 0644, show_throttle_adj, + store_throttle_adj); + +gov_attr(guard_band_mbps, 0U, 2000U); +gov_attr(decay_rate, 0U, 100U); +gov_attr(io_percent, 1U, 100U); +gov_attr(bw_step, 50U, 1000U); +gov_attr(sample_ms, 1U, 50U); +gov_attr(up_scale, 0U, 500U); +gov_attr(up_thres, 1U, 100U); +gov_attr(down_thres, 0U, 90U); +gov_attr(down_count, 0U, 90U); +gov_attr(hist_memory, 0U, 90U); +gov_attr(hyst_trigger_count, 0U, 90U); +gov_attr(hyst_length, 0U, 90U); +gov_attr(idle_mbps, 0U, 2000U); +gov_attr(low_power_ceil_mbps, 0U, 2500U); +gov_attr(low_power_io_percent, 1U, 100U); +gov_attr(low_power_delay, 1U, 60U); +gov_list_attr(mbps_zones, NUM_MBPS_ZONES, 0U, UINT_MAX); + +static struct attribute *dev_attr[] = { + &dev_attr_guard_band_mbps.attr, + &dev_attr_decay_rate.attr, + &dev_attr_io_percent.attr, + &dev_attr_bw_step.attr, + &dev_attr_sample_ms.attr, + &dev_attr_up_scale.attr, + &dev_attr_up_thres.attr, + &dev_attr_down_thres.attr, + &dev_attr_down_count.attr, + &dev_attr_hist_memory.attr, + &dev_attr_hyst_trigger_count.attr, + &dev_attr_hyst_length.attr, + &dev_attr_idle_mbps.attr, + &dev_attr_low_power_ceil_mbps.attr, + &dev_attr_low_power_io_percent.attr, + &dev_attr_low_power_delay.attr, + &dev_attr_mbps_zones.attr, + &dev_attr_throttle_adj.attr, + NULL, +}; + +static struct attribute_group dev_attr_group = { + .name = "bw_hwmon", + .attrs = dev_attr, +}; + +static int devfreq_bw_hwmon_ev_handler(struct devfreq *df, + unsigned int event, void *data) +{ + int ret; + unsigned int sample_ms; + struct hwmon_node *node; + struct bw_hwmon *hw; + + switch (event) { + case DEVFREQ_GOV_START: + sample_ms = df->profile->polling_ms; + sample_ms = max(MIN_MS, sample_ms); + sample_ms = min(MAX_MS, sample_ms); + df->profile->polling_ms = sample_ms; + + ret = gov_start(df); + if (ret) + return ret; + + dev_dbg(df->dev.parent, + "Enabled dev BW HW monitor governor\n"); + break; + + case DEVFREQ_GOV_STOP: + gov_stop(df); + dev_dbg(df->dev.parent, + "Disabled dev BW HW monitor governor\n"); + break; + + case DEVFREQ_GOV_INTERVAL: + mutex_lock(&sync_lock); + sample_ms = *(unsigned int *)data; + sample_ms = max(MIN_MS, sample_ms); + sample_ms = min(MAX_MS, sample_ms); + /* + * Suspend/resume the HW monitor around the interval update + * to prevent the HW monitor IRQ from trying to change + * stop/start the delayed workqueue while the interval update + * is happening. + */ + node = df->data; + hw = node->hw; + hw->suspend_hwmon(hw); + devfreq_interval_update(df, &sample_ms); + ret = hw->resume_hwmon(hw); + if (ret) { + dev_err(df->dev.parent, + "Unable to resume HW monitor (%d)\n", ret); + return ret; + } + mutex_unlock(&sync_lock); + break; + + case DEVFREQ_GOV_SUSPEND: + ret = gov_suspend(df); + if (ret) { + dev_err(df->dev.parent, + "Unable to suspend BW HW mon governor (%d)\n", + ret); + return ret; + } + + dev_dbg(df->dev.parent, "Suspended BW HW mon governor\n"); + break; + + case DEVFREQ_GOV_RESUME: + ret = gov_resume(df); + if (ret) { + dev_err(df->dev.parent, + "Unable to resume BW HW mon governor (%d)\n", + ret); + return ret; + } + + dev_dbg(df->dev.parent, "Resumed BW HW mon governor\n"); + break; + } + + return 0; +} + +static struct devfreq_governor devfreq_gov_bw_hwmon = { + .name = "bw_hwmon", + .get_target_freq = devfreq_bw_hwmon_get_freq, + .event_handler = devfreq_bw_hwmon_ev_handler, +}; + +int register_bw_hwmon(struct device *dev, struct bw_hwmon *hwmon) +{ + int ret = 0; + struct hwmon_node *node; + struct attribute_group *attr_grp; + + if (!hwmon->gov && !hwmon->dev && !hwmon->of_node) + return -EINVAL; + + node = devm_kzalloc(dev, sizeof(*node), GFP_KERNEL); + if (!node) { + dev_err(dev, "Unable to register gov. Out of memory!\n"); + return -ENOMEM; + } + + if (hwmon->gov) { + attr_grp = devm_kzalloc(dev, sizeof(*attr_grp), GFP_KERNEL); + if (!attr_grp) + return -ENOMEM; + + hwmon->gov->get_target_freq = devfreq_bw_hwmon_get_freq; + hwmon->gov->event_handler = devfreq_bw_hwmon_ev_handler; + attr_grp->name = hwmon->gov->name; + attr_grp->attrs = dev_attr; + + node->gov = hwmon->gov; + node->attr_grp = attr_grp; + } else { + node->gov = &devfreq_gov_bw_hwmon; + node->attr_grp = &dev_attr_group; + } + + node->guard_band_mbps = 100; + node->decay_rate = 90; + node->io_percent = 16; + node->low_power_ceil_mbps = 0; + node->low_power_io_percent = 16; + node->low_power_delay = 60; + node->bw_step = 190; + node->sample_ms = 50; + node->up_scale = 0; + node->up_thres = 10; + node->down_thres = 0; + node->down_count = 3; + node->hist_memory = 0; + node->hyst_trigger_count = 3; + node->hyst_length = 0; + node->idle_mbps = 400; + node->mbps_zones[0] = 0; + node->hw = hwmon; + + mutex_lock(&list_lock); + list_add_tail(&node->list, &hwmon_list); + mutex_unlock(&list_lock); + + if (hwmon->gov) { + ret = devfreq_add_governor(hwmon->gov); + } else { + mutex_lock(&state_lock); + if (!use_cnt) + ret = devfreq_add_governor(&devfreq_gov_bw_hwmon); + if (!ret) + use_cnt++; + mutex_unlock(&state_lock); + } + + if (!ret) + dev_info(dev, "BW HWmon governor registered.\n"); + else + dev_err(dev, "BW HWmon governor registration failed!\n"); + + return ret; +} + +MODULE_DESCRIPTION("HW monitor based dev DDR bandwidth voting driver"); +MODULE_LICENSE("GPL v2"); --- /dev/null 2019-10-24 16:47:25.704025805 +0200 +++ linux-4.4.115-fbx/drivers/devfreq/governor_bw_hwmon.h 2019-01-22 16:16:23.135243074 +0100 @@ -0,0 +1,88 @@ +/* + * Copyright (c) 2014-2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _GOVERNOR_BW_HWMON_H +#define _GOVERNOR_BW_HWMON_H + +#include +#include + +/** + * struct bw_hwmon - dev BW HW monitor info + * @start_hwmon: Start the HW monitoring of the dev BW + * @stop_hwmon: Stop the HW monitoring of dev BW + * @set_thres: Set the count threshold to generate an IRQ + * @get_bytes_and_clear: Get the bytes transferred since the last call + * and reset the counter to start over. + * @set_throttle_adj: Set throttle adjust field to the given value + * @get_throttle_adj: Get the value written to throttle adjust field + * @dev: Pointer to device that this HW monitor can + * monitor. + * @of_node: OF node of device that this HW monitor can + * monitor. + * @gov: devfreq_governor struct that should be used + * when registering this HW monitor with devfreq. + * Only the name field is expected to be + * initialized. + * @df: Devfreq node that this HW monitor is being + * used for. NULL when not actively in use and + * non-NULL when in use. + * + * One of dev, of_node or governor_name needs to be specified for a + * successful registration. + * + */ +struct bw_hwmon { + int (*start_hwmon)(struct bw_hwmon *hw, unsigned long mbps); + void (*stop_hwmon)(struct bw_hwmon *hw); + int (*suspend_hwmon)(struct bw_hwmon *hw); + int (*resume_hwmon)(struct bw_hwmon *hw); + unsigned long (*set_thres)(struct bw_hwmon *hw, unsigned long bytes); + unsigned long (*set_hw_events)(struct bw_hwmon *hw, + unsigned int sample_ms); + unsigned long (*get_bytes_and_clear)(struct bw_hwmon *hw); + int (*set_throttle_adj)(struct bw_hwmon *hw, uint adj); + u32 (*get_throttle_adj)(struct bw_hwmon *hw); + struct device *dev; + struct device_node *of_node; + struct devfreq_governor *gov; + + unsigned long up_wake_mbps; + unsigned long undo_over_req_mbps; + unsigned long down_wake_mbps; + unsigned int down_cnt; + + struct devfreq *df; +}; + +#ifdef CONFIG_DEVFREQ_GOV_QCOM_BW_HWMON +int register_bw_hwmon(struct device *dev, struct bw_hwmon *hwmon); +int update_bw_hwmon(struct bw_hwmon *hwmon); +int bw_hwmon_sample_end(struct bw_hwmon *hwmon); +#else +static inline int register_bw_hwmon(struct device *dev, + struct bw_hwmon *hwmon) +{ + return 0; +} +static inline int update_bw_hwmon(struct bw_hwmon *hwmon) +{ + return 0; +} +static inline int bw_hwmon_sample_end(struct bw_hwmon *hwmon) +{ + return 0; +} +#endif + +#endif /* _GOVERNOR_BW_HWMON_H */ --- /dev/null 2019-10-24 16:47:25.704025805 +0200 +++ linux-4.4.115-fbx/drivers/devfreq/governor_cpufreq.c 2019-01-22 16:16:23.135243074 +0100 @@ -0,0 +1,712 @@ +/* + * Copyright (c) 2014-2015, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define pr_fmt(fmt) "dev-cpufreq: " fmt + +#include +#include +#include +#include +#include +#include +#include +#include +#include "governor.h" + +struct cpu_state { + unsigned int freq; + unsigned int min_freq; + unsigned int max_freq; + bool on; + unsigned int first_cpu; +}; +static struct cpu_state *state[NR_CPUS]; +static int cpufreq_cnt; + +struct freq_map { + unsigned int cpu_khz; + unsigned int target_freq; +}; + +struct devfreq_node { + struct devfreq *df; + void *orig_data; + struct device *dev; + struct device_node *of_node; + struct list_head list; + struct freq_map **map; + struct freq_map *common_map; + unsigned int timeout; + struct delayed_work dwork; + bool drop; + unsigned long prev_tgt; +}; +static LIST_HEAD(devfreq_list); +static DEFINE_MUTEX(state_lock); +static DEFINE_MUTEX(cpufreq_reg_lock); + +#define show_attr(name) \ +static ssize_t show_##name(struct device *dev, \ + struct device_attribute *attr, char *buf) \ +{ \ + struct devfreq *df = to_devfreq(dev); \ + struct devfreq_node *n = df->data; \ + return snprintf(buf, PAGE_SIZE, "%u\n", n->name); \ +} + +#define store_attr(name, _min, _max) \ +static ssize_t store_##name(struct device *dev, \ + struct device_attribute *attr, const char *buf, \ + size_t count) \ +{ \ + struct devfreq *df = to_devfreq(dev); \ + struct devfreq_node *n = df->data; \ + int ret; \ + unsigned int val; \ + ret = sscanf(buf, "%u", &val); \ + if (ret != 1) \ + return -EINVAL; \ + val = max(val, _min); \ + val = min(val, _max); \ + n->name = val; \ + return count; \ +} + +#define gov_attr(__attr, min, max) \ +show_attr(__attr) \ +store_attr(__attr, min, max) \ +static DEVICE_ATTR(__attr, 0644, show_##__attr, store_##__attr) + +static int update_node(struct devfreq_node *node) +{ + int ret; + struct devfreq *df = node->df; + + if (!df) + return 0; + + cancel_delayed_work_sync(&node->dwork); + + mutex_lock(&df->lock); + node->drop = false; + ret = update_devfreq(df); + if (ret) { + dev_err(df->dev.parent, "Unable to update frequency\n"); + goto out; + } + + if (!node->timeout) + goto out; + + if (df->previous_freq <= df->min_freq) + goto out; + + schedule_delayed_work(&node->dwork, + msecs_to_jiffies(node->timeout)); +out: + mutex_unlock(&df->lock); + return ret; +} + +static void update_all_devfreqs(void) +{ + struct devfreq_node *node; + + list_for_each_entry(node, &devfreq_list, list) { + update_node(node); + } +} + +static void do_timeout(struct work_struct *work) +{ + struct devfreq_node *node = container_of(to_delayed_work(work), + struct devfreq_node, dwork); + struct devfreq *df = node->df; + + mutex_lock(&df->lock); + node->drop = true; + update_devfreq(df); + mutex_unlock(&df->lock); +} + +static struct devfreq_node *find_devfreq_node(struct device *dev) +{ + struct devfreq_node *node; + + list_for_each_entry(node, &devfreq_list, list) + if (node->dev == dev || node->of_node == dev->of_node) + return node; + + return NULL; +} + +/* ==================== cpufreq part ==================== */ +static void add_policy(struct cpufreq_policy *policy) +{ + struct cpu_state *new_state; + unsigned int cpu, first_cpu; + + if (state[policy->cpu]) { + state[policy->cpu]->freq = policy->cur; + state[policy->cpu]->on = true; + } else { + new_state = kzalloc(sizeof(struct cpu_state), GFP_KERNEL); + if (!new_state) + return; + + first_cpu = cpumask_first(policy->related_cpus); + new_state->first_cpu = first_cpu; + new_state->freq = policy->cur; + new_state->min_freq = policy->cpuinfo.min_freq; + new_state->max_freq = policy->cpuinfo.max_freq; + new_state->on = true; + + for_each_cpu(cpu, policy->related_cpus) + state[cpu] = new_state; + } +} + +static int cpufreq_policy_notifier(struct notifier_block *nb, + unsigned long event, void *data) +{ + struct cpufreq_policy *policy = data; + + switch (event) { + case CPUFREQ_CREATE_POLICY: + mutex_lock(&state_lock); + add_policy(policy); + update_all_devfreqs(); + mutex_unlock(&state_lock); + break; + + case CPUFREQ_REMOVE_POLICY: + mutex_lock(&state_lock); + if (state[policy->cpu]) { + state[policy->cpu]->on = false; + update_all_devfreqs(); + } + mutex_unlock(&state_lock); + break; + } + + return 0; +} + +static struct notifier_block cpufreq_policy_nb = { + .notifier_call = cpufreq_policy_notifier +}; + +static int cpufreq_trans_notifier(struct notifier_block *nb, + unsigned long event, void *data) +{ + struct cpufreq_freqs *freq = data; + struct cpu_state *s; + + if (event != CPUFREQ_POSTCHANGE) + return 0; + + mutex_lock(&state_lock); + + s = state[freq->cpu]; + if (!s) + goto out; + + if (s->freq != freq->new) { + s->freq = freq->new; + update_all_devfreqs(); + } + +out: + mutex_unlock(&state_lock); + return 0; +} + +static struct notifier_block cpufreq_trans_nb = { + .notifier_call = cpufreq_trans_notifier +}; + +static int register_cpufreq(void) +{ + int ret = 0; + unsigned int cpu; + struct cpufreq_policy *policy; + + mutex_lock(&cpufreq_reg_lock); + + if (cpufreq_cnt) + goto cnt_not_zero; + + get_online_cpus(); + ret = cpufreq_register_notifier(&cpufreq_policy_nb, + CPUFREQ_POLICY_NOTIFIER); + if (ret) + goto out; + + ret = cpufreq_register_notifier(&cpufreq_trans_nb, + CPUFREQ_TRANSITION_NOTIFIER); + if (ret) { + cpufreq_unregister_notifier(&cpufreq_policy_nb, + CPUFREQ_POLICY_NOTIFIER); + goto out; + } + + for_each_online_cpu(cpu) { + policy = cpufreq_cpu_get(cpu); + if (policy) { + add_policy(policy); + cpufreq_cpu_put(policy); + } + } +out: + put_online_cpus(); +cnt_not_zero: + if (!ret) + cpufreq_cnt++; + mutex_unlock(&cpufreq_reg_lock); + return ret; +} + +static int unregister_cpufreq(void) +{ + int ret = 0; + int cpu; + + mutex_lock(&cpufreq_reg_lock); + + if (cpufreq_cnt > 1) + goto out; + + cpufreq_unregister_notifier(&cpufreq_policy_nb, + CPUFREQ_POLICY_NOTIFIER); + cpufreq_unregister_notifier(&cpufreq_trans_nb, + CPUFREQ_TRANSITION_NOTIFIER); + + for (cpu = ARRAY_SIZE(state) - 1; cpu >= 0; cpu--) { + if (!state[cpu]) + continue; + if (state[cpu]->first_cpu == cpu) + kfree(state[cpu]); + state[cpu] = NULL; + } + +out: + cpufreq_cnt--; + mutex_unlock(&cpufreq_reg_lock); + return ret; +} + +/* ==================== devfreq part ==================== */ + +static unsigned int interpolate_freq(struct devfreq *df, unsigned int cpu) +{ + unsigned int *freq_table = df->profile->freq_table; + unsigned int cpu_min = state[cpu]->min_freq; + unsigned int cpu_max = state[cpu]->max_freq; + unsigned int cpu_freq = state[cpu]->freq; + unsigned int dev_min, dev_max, cpu_percent; + + if (freq_table) { + dev_min = freq_table[0]; + dev_max = freq_table[df->profile->max_state - 1]; + } else { + if (df->max_freq <= df->min_freq) + return 0; + dev_min = df->min_freq; + dev_max = df->max_freq; + } + + cpu_percent = ((cpu_freq - cpu_min) * 100) / (cpu_max - cpu_min); + return dev_min + mult_frac(dev_max - dev_min, cpu_percent, 100); +} + +static unsigned int cpu_to_dev_freq(struct devfreq *df, unsigned int cpu) +{ + struct freq_map *map = NULL; + unsigned int cpu_khz = 0, freq; + struct devfreq_node *n = df->data; + + if (!state[cpu] || !state[cpu]->on || state[cpu]->first_cpu != cpu) { + freq = 0; + goto out; + } + + if (n->common_map) + map = n->common_map; + else if (n->map) + map = n->map[cpu]; + + cpu_khz = state[cpu]->freq; + + if (!map) { + freq = interpolate_freq(df, cpu); + goto out; + } + + while (map->cpu_khz && map->cpu_khz < cpu_khz) + map++; + if (!map->cpu_khz) + map--; + freq = map->target_freq; + +out: + dev_dbg(df->dev.parent, "CPU%u: %d -> dev: %u\n", cpu, cpu_khz, freq); + return freq; +} + +static int devfreq_cpufreq_get_freq(struct devfreq *df, + unsigned long *freq, + u32 *flag) +{ + unsigned int cpu, tgt_freq = 0; + struct devfreq_node *node; + + node = df->data; + if (!node) { + pr_err("Unable to find devfreq node!\n"); + return -ENODEV; + } + + if (node->drop) { + *freq = 0; + return 0; + } + + for_each_possible_cpu(cpu) + tgt_freq = max(tgt_freq, cpu_to_dev_freq(df, cpu)); + + if (node->timeout && tgt_freq < node->prev_tgt) + *freq = 0; + else + *freq = tgt_freq; + + node->prev_tgt = tgt_freq; + + return 0; +} + +static unsigned int show_table(char *buf, unsigned int len, + struct freq_map *map) +{ + unsigned int cnt = 0; + + cnt += snprintf(buf + cnt, len - cnt, "CPU freq\tDevice freq\n"); + + while (map->cpu_khz && cnt < len) { + cnt += snprintf(buf + cnt, len - cnt, "%8u\t%11u\n", + map->cpu_khz, map->target_freq); + map++; + } + if (cnt < len) + cnt += snprintf(buf + cnt, len - cnt, "\n"); + + return cnt; +} + +static ssize_t show_map(struct device *dev, struct device_attribute *attr, + char *buf) +{ + struct devfreq *df = to_devfreq(dev); + struct devfreq_node *n = df->data; + struct freq_map *map; + unsigned int cnt = 0, cpu; + + mutex_lock(&state_lock); + if (n->common_map) { + map = n->common_map; + cnt += snprintf(buf + cnt, PAGE_SIZE - cnt, + "Common table for all CPUs:\n"); + cnt += show_table(buf + cnt, PAGE_SIZE - cnt, map); + } else if (n->map) { + for_each_possible_cpu(cpu) { + map = n->map[cpu]; + if (!map) + continue; + cnt += snprintf(buf + cnt, PAGE_SIZE - cnt, + "CPU %u:\n", cpu); + if (cnt >= PAGE_SIZE) + break; + cnt += show_table(buf + cnt, PAGE_SIZE - cnt, map); + if (cnt >= PAGE_SIZE) + break; + } + } else { + cnt += snprintf(buf + cnt, PAGE_SIZE - cnt, + "Device freq interpolated based on CPU freq\n"); + } + mutex_unlock(&state_lock); + + return cnt; +} + +static DEVICE_ATTR(freq_map, 0444, show_map, NULL); +gov_attr(timeout, 0U, 100U); + +static struct attribute *dev_attr[] = { + &dev_attr_freq_map.attr, + &dev_attr_timeout.attr, + NULL, +}; + +static struct attribute_group dev_attr_group = { + .name = "cpufreq", + .attrs = dev_attr, +}; + +static int devfreq_cpufreq_gov_start(struct devfreq *devfreq) +{ + int ret = 0; + struct devfreq_node *node; + bool alloc = false; + + ret = register_cpufreq(); + if (ret) + return ret; + + ret = sysfs_create_group(&devfreq->dev.kobj, &dev_attr_group); + if (ret) { + unregister_cpufreq(); + return ret; + } + + mutex_lock(&state_lock); + + node = find_devfreq_node(devfreq->dev.parent); + if (node == NULL) { + node = kzalloc(sizeof(struct devfreq_node), GFP_KERNEL); + if (!node) { + pr_err("Out of memory!\n"); + ret = -ENOMEM; + goto alloc_fail; + } + alloc = true; + node->dev = devfreq->dev.parent; + list_add_tail(&node->list, &devfreq_list); + } + + INIT_DELAYED_WORK(&node->dwork, do_timeout); + + node->df = devfreq; + node->orig_data = devfreq->data; + devfreq->data = node; + + ret = update_node(node); + if (ret) + goto update_fail; + + mutex_unlock(&state_lock); + return 0; + +update_fail: + devfreq->data = node->orig_data; + if (alloc) { + list_del(&node->list); + kfree(node); + } +alloc_fail: + mutex_unlock(&state_lock); + sysfs_remove_group(&devfreq->dev.kobj, &dev_attr_group); + unregister_cpufreq(); + return ret; +} + +static void devfreq_cpufreq_gov_stop(struct devfreq *devfreq) +{ + struct devfreq_node *node = devfreq->data; + + cancel_delayed_work_sync(&node->dwork); + + mutex_lock(&state_lock); + devfreq->data = node->orig_data; + if (node->map || node->common_map) { + node->df = NULL; + } else { + list_del(&node->list); + kfree(node); + } + mutex_unlock(&state_lock); + + sysfs_remove_group(&devfreq->dev.kobj, &dev_attr_group); + unregister_cpufreq(); +} + +static int devfreq_cpufreq_ev_handler(struct devfreq *devfreq, + unsigned int event, void *data) +{ + int ret; + + switch (event) { + case DEVFREQ_GOV_START: + + ret = devfreq_cpufreq_gov_start(devfreq); + if (ret) { + pr_err("Governor start failed!\n"); + return ret; + } + pr_debug("Enabled dev CPUfreq governor\n"); + break; + + case DEVFREQ_GOV_STOP: + + devfreq_cpufreq_gov_stop(devfreq); + pr_debug("Disabled dev CPUfreq governor\n"); + break; + } + + return 0; +} + +static struct devfreq_governor devfreq_cpufreq = { + .name = "cpufreq", + .get_target_freq = devfreq_cpufreq_get_freq, + .event_handler = devfreq_cpufreq_ev_handler, +}; + +#define NUM_COLS 2 +static struct freq_map *read_tbl(struct device_node *of_node, char *prop_name) +{ + int len, nf, i, j; + u32 data; + struct freq_map *tbl; + + if (!of_find_property(of_node, prop_name, &len)) + return NULL; + len /= sizeof(data); + + if (len % NUM_COLS || len == 0) + return NULL; + nf = len / NUM_COLS; + + tbl = kzalloc((nf + 1) * sizeof(*tbl), GFP_KERNEL); + if (!tbl) + return NULL; + + for (i = 0, j = 0; i < nf; i++, j += 2) { + of_property_read_u32_index(of_node, prop_name, j, &data); + tbl[i].cpu_khz = data; + + of_property_read_u32_index(of_node, prop_name, j + 1, &data); + tbl[i].target_freq = data; + } + tbl[i].cpu_khz = 0; + + return tbl; +} + +#define PROP_TARGET "target-dev" +#define PROP_TABLE "cpu-to-dev-map" +static int add_table_from_of(struct device_node *of_node) +{ + struct device_node *target_of_node; + struct devfreq_node *node; + struct freq_map *common_tbl; + struct freq_map **tbl_list = NULL; + static char prop_name[] = PROP_TABLE "-999999"; + int cpu, ret, cnt = 0, prop_sz = ARRAY_SIZE(prop_name); + + target_of_node = of_parse_phandle(of_node, PROP_TARGET, 0); + if (!target_of_node) + return -EINVAL; + + node = kzalloc(sizeof(struct devfreq_node), GFP_KERNEL); + if (!node) + return -ENOMEM; + + common_tbl = read_tbl(of_node, PROP_TABLE); + if (!common_tbl) { + tbl_list = kzalloc(sizeof(*tbl_list) * NR_CPUS, GFP_KERNEL); + if (!tbl_list) + return -ENOMEM; + + for_each_possible_cpu(cpu) { + ret = snprintf(prop_name, prop_sz, "%s-%d", + PROP_TABLE, cpu); + if (ret >= prop_sz) { + pr_warn("More CPUs than I can handle!\n"); + pr_warn("Skipping rest of the tables!\n"); + break; + } + tbl_list[cpu] = read_tbl(of_node, prop_name); + if (tbl_list[cpu]) + cnt++; + } + } + if (!common_tbl && !cnt) { + kfree(tbl_list); + return -EINVAL; + } + + mutex_lock(&state_lock); + node->of_node = target_of_node; + node->map = tbl_list; + node->common_map = common_tbl; + list_add_tail(&node->list, &devfreq_list); + mutex_unlock(&state_lock); + + return 0; +} + +static int __init devfreq_cpufreq_init(void) +{ + int ret; + struct device_node *of_par, *of_child; + + of_par = of_find_node_by_name(NULL, "devfreq-cpufreq"); + if (of_par) { + for_each_child_of_node(of_par, of_child) { + ret = add_table_from_of(of_child); + if (ret) + pr_err("Parsing %s failed!\n", of_child->name); + else + pr_debug("Parsed %s.\n", of_child->name); + } + of_node_put(of_par); + } else { + pr_info("No tables parsed from DT.\n"); + } + + ret = devfreq_add_governor(&devfreq_cpufreq); + if (ret) { + pr_err("Governor add failed!\n"); + return ret; + } + + return 0; +} +subsys_initcall(devfreq_cpufreq_init); + +static void __exit devfreq_cpufreq_exit(void) +{ + int ret, cpu; + struct devfreq_node *node, *tmp; + + ret = devfreq_remove_governor(&devfreq_cpufreq); + if (ret) + pr_err("Governor remove failed!\n"); + + mutex_lock(&state_lock); + list_for_each_entry_safe(node, tmp, &devfreq_list, list) { + kfree(node->common_map); + for_each_possible_cpu(cpu) + kfree(node->map[cpu]); + kfree(node->map); + list_del(&node->list); + kfree(node); + } + mutex_unlock(&state_lock); + + return; +} +module_exit(devfreq_cpufreq_exit); + +MODULE_DESCRIPTION("CPU freq based generic governor for devfreq devices"); +MODULE_LICENSE("GPL v2"); --- /dev/null 2019-10-24 16:47:25.704025805 +0200 +++ linux-4.4.115-fbx/drivers/devfreq/governor_memlat.c 2019-01-22 16:16:23.135243074 +0100 @@ -0,0 +1,414 @@ +/* + * Copyright (c) 2015-2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define pr_fmt(fmt) "mem_lat: " fmt + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "governor.h" +#include "governor_memlat.h" + +#include + +struct memlat_node { + unsigned int ratio_ceil; + bool mon_started; + struct list_head list; + void *orig_data; + struct memlat_hwmon *hw; + struct devfreq_governor *gov; + struct attribute_group *attr_grp; +}; + +static LIST_HEAD(memlat_list); +static DEFINE_MUTEX(list_lock); + +static int use_cnt; +static DEFINE_MUTEX(state_lock); + +#define show_attr(name) \ +static ssize_t show_##name(struct device *dev, \ + struct device_attribute *attr, char *buf) \ +{ \ + struct devfreq *df = to_devfreq(dev); \ + struct memlat_node *hw = df->data; \ + return snprintf(buf, PAGE_SIZE, "%u\n", hw->name); \ +} + +#define store_attr(name, _min, _max) \ +static ssize_t store_##name(struct device *dev, \ + struct device_attribute *attr, const char *buf, \ + size_t count) \ +{ \ + struct devfreq *df = to_devfreq(dev); \ + struct memlat_node *hw = df->data; \ + int ret; \ + unsigned int val; \ + ret = kstrtouint(buf, 10, &val); \ + if (ret) \ + return ret; \ + val = max(val, _min); \ + val = min(val, _max); \ + hw->name = val; \ + return count; \ +} + +#define gov_attr(__attr, min, max) \ +show_attr(__attr) \ +store_attr(__attr, min, max) \ +static DEVICE_ATTR(__attr, 0644, show_##__attr, store_##__attr) + +static ssize_t show_map(struct device *dev, struct device_attribute *attr, + char *buf) +{ + struct devfreq *df = to_devfreq(dev); + struct memlat_node *n = df->data; + struct core_dev_map *map = n->hw->freq_map; + unsigned int cnt = 0; + + cnt += snprintf(buf, PAGE_SIZE, "Core freq (MHz)\tDevice BW\n"); + + while (map->core_mhz && cnt < PAGE_SIZE) { + cnt += snprintf(buf + cnt, PAGE_SIZE - cnt, "%15u\t%9u\n", + map->core_mhz, map->target_freq); + map++; + } + if (cnt < PAGE_SIZE) + cnt += snprintf(buf + cnt, PAGE_SIZE - cnt, "\n"); + + return cnt; +} + +static DEVICE_ATTR(freq_map, 0444, show_map, NULL); + +static unsigned long core_to_dev_freq(struct memlat_node *node, + unsigned long coref) +{ + struct memlat_hwmon *hw = node->hw; + struct core_dev_map *map = hw->freq_map; + unsigned long freq = 0; + + if (!map) + goto out; + + while (map->core_mhz && map->core_mhz < coref) + map++; + if (!map->core_mhz) + map--; + freq = map->target_freq; + +out: + pr_debug("freq: %lu -> dev: %lu\n", coref, freq); + return freq; +} + +static struct memlat_node *find_memlat_node(struct devfreq *df) +{ + struct memlat_node *node, *found = NULL; + + mutex_lock(&list_lock); + list_for_each_entry(node, &memlat_list, list) + if (node->hw->dev == df->dev.parent || + node->hw->of_node == df->dev.parent->of_node) { + found = node; + break; + } + mutex_unlock(&list_lock); + + return found; +} + +static int start_monitor(struct devfreq *df) +{ + struct memlat_node *node = df->data; + struct memlat_hwmon *hw = node->hw; + struct device *dev = df->dev.parent; + int ret; + + ret = hw->start_hwmon(hw); + + if (ret) { + dev_err(dev, "Unable to start HW monitor! (%d)\n", ret); + return ret; + } + + devfreq_monitor_start(df); + + node->mon_started = true; + + return 0; +} + +static void stop_monitor(struct devfreq *df) +{ + struct memlat_node *node = df->data; + struct memlat_hwmon *hw = node->hw; + + node->mon_started = false; + + devfreq_monitor_stop(df); + hw->stop_hwmon(hw); +} + +static int gov_start(struct devfreq *df) +{ + int ret = 0; + struct device *dev = df->dev.parent; + struct memlat_node *node; + struct memlat_hwmon *hw; + + node = find_memlat_node(df); + if (!node) { + dev_err(dev, "Unable to find HW monitor!\n"); + return -ENODEV; + } + hw = node->hw; + + hw->df = df; + node->orig_data = df->data; + df->data = node; + + if (start_monitor(df)) + goto err_start; + + ret = sysfs_create_group(&df->dev.kobj, node->attr_grp); + if (ret) + goto err_sysfs; + + return 0; + +err_sysfs: + stop_monitor(df); +err_start: + df->data = node->orig_data; + node->orig_data = NULL; + hw->df = NULL; + return ret; +} + +static void gov_stop(struct devfreq *df) +{ + struct memlat_node *node = df->data; + struct memlat_hwmon *hw = node->hw; + + sysfs_remove_group(&df->dev.kobj, node->attr_grp); + stop_monitor(df); + df->data = node->orig_data; + node->orig_data = NULL; + hw->df = NULL; +} + +static int devfreq_memlat_get_freq(struct devfreq *df, + unsigned long *freq, + u32 *flag) +{ + int i, lat_dev; + struct memlat_node *node = df->data; + struct memlat_hwmon *hw = node->hw; + unsigned long max_freq = 0; + unsigned int ratio; + + hw->get_cnt(hw); + + for (i = 0; i < hw->num_cores; i++) { + ratio = hw->core_stats[i].inst_count; + + if (hw->core_stats[i].mem_count) + ratio /= hw->core_stats[i].mem_count; + + trace_memlat_dev_meas(dev_name(df->dev.parent), + hw->core_stats[i].id, + hw->core_stats[i].inst_count, + hw->core_stats[i].mem_count, + hw->core_stats[i].freq, ratio); + + if (ratio && ratio <= node->ratio_ceil + && hw->core_stats[i].freq > max_freq) { + lat_dev = i; + max_freq = hw->core_stats[i].freq; + } + } + + if (max_freq) { + max_freq = core_to_dev_freq(node, max_freq); + trace_memlat_dev_update(dev_name(df->dev.parent), + hw->core_stats[lat_dev].id, + hw->core_stats[lat_dev].inst_count, + hw->core_stats[lat_dev].mem_count, + hw->core_stats[lat_dev].freq, + max_freq); + } + + *freq = max_freq; + return 0; +} + +gov_attr(ratio_ceil, 1U, 10000U); + +static struct attribute *dev_attr[] = { + &dev_attr_ratio_ceil.attr, + &dev_attr_freq_map.attr, + NULL, +}; + +static struct attribute_group dev_attr_group = { + .name = "mem_latency", + .attrs = dev_attr, +}; + +#define MIN_MS 10U +#define MAX_MS 500U +static int devfreq_memlat_ev_handler(struct devfreq *df, + unsigned int event, void *data) +{ + int ret; + unsigned int sample_ms; + + switch (event) { + case DEVFREQ_GOV_START: + sample_ms = df->profile->polling_ms; + sample_ms = max(MIN_MS, sample_ms); + sample_ms = min(MAX_MS, sample_ms); + df->profile->polling_ms = sample_ms; + + ret = gov_start(df); + if (ret) + return ret; + + dev_dbg(df->dev.parent, + "Enabled Memory Latency governor\n"); + break; + + case DEVFREQ_GOV_STOP: + gov_stop(df); + dev_dbg(df->dev.parent, + "Disabled Memory Latency governor\n"); + break; + + case DEVFREQ_GOV_INTERVAL: + sample_ms = *(unsigned int *)data; + sample_ms = max(MIN_MS, sample_ms); + sample_ms = min(MAX_MS, sample_ms); + devfreq_interval_update(df, &sample_ms); + break; + } + + return 0; +} + +static struct devfreq_governor devfreq_gov_memlat = { + .name = "mem_latency", + .get_target_freq = devfreq_memlat_get_freq, + .event_handler = devfreq_memlat_ev_handler, +}; + +#define NUM_COLS 2 +static struct core_dev_map *init_core_dev_map(struct device *dev, + char *prop_name) +{ + int len, nf, i, j; + u32 data; + struct core_dev_map *tbl; + int ret; + + if (!of_find_property(dev->of_node, prop_name, &len)) + return NULL; + len /= sizeof(data); + + if (len % NUM_COLS || len == 0) + return NULL; + nf = len / NUM_COLS; + + tbl = devm_kzalloc(dev, (nf + 1) * sizeof(struct core_dev_map), + GFP_KERNEL); + if (!tbl) + return NULL; + + for (i = 0, j = 0; i < nf; i++, j += 2) { + ret = of_property_read_u32_index(dev->of_node, prop_name, j, + &data); + if (ret) + return NULL; + tbl[i].core_mhz = data / 1000; + + ret = of_property_read_u32_index(dev->of_node, prop_name, j + 1, + &data); + if (ret) + return NULL; + tbl[i].target_freq = data; + pr_debug("Entry%d CPU:%u, Dev:%u\n", i, tbl[i].core_mhz, + tbl[i].target_freq); + } + tbl[i].core_mhz = 0; + + return tbl; +} + +int register_memlat(struct device *dev, struct memlat_hwmon *hw) +{ + int ret = 0; + struct memlat_node *node; + + if (!hw->dev && !hw->of_node) + return -EINVAL; + + node = devm_kzalloc(dev, sizeof(*node), GFP_KERNEL); + if (!node) + return -ENOMEM; + + node->gov = &devfreq_gov_memlat; + node->attr_grp = &dev_attr_group; + + node->ratio_ceil = 10; + node->hw = hw; + + hw->freq_map = init_core_dev_map(dev, "qcom,core-dev-table"); + if (!hw->freq_map) { + dev_err(dev, "Couldn't find the core-dev freq table!\n"); + return -EINVAL; + } + + mutex_lock(&list_lock); + list_add_tail(&node->list, &memlat_list); + mutex_unlock(&list_lock); + + mutex_lock(&state_lock); + if (!use_cnt) + ret = devfreq_add_governor(&devfreq_gov_memlat); + if (!ret) + use_cnt++; + mutex_unlock(&state_lock); + + if (!ret) + dev_info(dev, "Memory Latency governor registered.\n"); + else + dev_err(dev, "Memory Latency governor registration failed!\n"); + + return ret; +} + +MODULE_DESCRIPTION("HW monitor based dev DDR bandwidth voting driver"); +MODULE_LICENSE("GPL v2"); --- /dev/null 2019-10-24 16:47:25.704025805 +0200 +++ linux-4.4.115-fbx/drivers/devfreq/governor_memlat.h 2019-01-22 16:16:23.135243074 +0100 @@ -0,0 +1,89 @@ +/* + * Copyright (c) 2015-2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _GOVERNOR_BW_HWMON_H +#define _GOVERNOR_BW_HWMON_H + +#include +#include + +/** + * struct dev_stats - Device stats + * @inst_count: Number of instructions executed. + * @mem_count: Number of memory accesses made. + * @freq: Effective frequency of the device in the + * last interval. + */ +struct dev_stats { + int id; + unsigned long inst_count; + unsigned long mem_count; + unsigned long freq; +}; + +struct core_dev_map { + unsigned int core_mhz; + unsigned int target_freq; +}; + +/** + * struct memlat_hwmon - Memory Latency HW monitor info + * @start_hwmon: Start the HW monitoring + * @stop_hwmon: Stop the HW monitoring + * @get_cnt: Return the number of intructions executed, + * memory accesses and effective frequency + * @dev: Pointer to device that this HW monitor can + * monitor. + * @of_node: OF node of device that this HW monitor can + * monitor. + * @df: Devfreq node that this HW monitor is being + * used for. NULL when not actively in use and + * non-NULL when in use. + * @num_cores: Number of cores that are monitored by the + * hardware monitor. + * @core_stats: Array containing instruction count, memory + * accesses and effective frequency for each core. + * + * One of dev or of_node needs to be specified for a successful registration. + * + */ +struct memlat_hwmon { + int (*start_hwmon)(struct memlat_hwmon *hw); + void (*stop_hwmon)(struct memlat_hwmon *hw); + unsigned long (*get_cnt)(struct memlat_hwmon *hw); + struct device *dev; + struct device_node *of_node; + + unsigned int num_cores; + struct dev_stats *core_stats; + + struct devfreq *df; + struct core_dev_map *freq_map; +}; + +#ifdef CONFIG_DEVFREQ_GOV_MEMLAT +int register_memlat(struct device *dev, struct memlat_hwmon *hw); +int update_memlat(struct memlat_hwmon *hw); +#else +static inline int register_memlat(struct device *dev, + struct memlat_hwmon *hw) +{ + return 0; +} +static inline int update_memlat(struct memlat_hwmon *hw) +{ + return 0; +} +#endif + +#endif /* _GOVERNOR_BW_HWMON_H */ --- /dev/null 2019-10-24 16:47:25.704025805 +0200 +++ linux-4.4.115-fbx/drivers/devfreq/governor_spdm_bw_hyp.c 2019-01-22 16:16:23.135243074 +0100 @@ -0,0 +1,417 @@ +/* +*Copyright (c) 2014-2016, The Linux Foundation. All rights reserved. +* +*This program is free software; you can redistribute it and/or modify +*it under the terms of the GNU General Public License version 2 and +*only version 2 as published by the Free Software Foundation. +* +*This program is distributed in the hope that it will be useful, +*but WITHOUT ANY WARRANTY; without even the implied warranty of +*MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +*GNU General Public License for more details. +*/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "governor.h" +#include "devfreq_spdm.h" + +enum msm_spdm_rt_res { + SPDM_RES_ID = 1, + SPDM_RES_TYPE = 0x63707362, + SPDM_KEY = 0x00006e65, + SPDM_SIZE = 4, +}; + +static LIST_HEAD(devfreqs); +static DEFINE_MUTEX(devfreqs_lock); + +static int enable_clocks(void) +{ + struct msm_rpm_request *rpm_req; + int id; + const int one = 1; + rpm_req = msm_rpm_create_request(MSM_RPM_CTX_ACTIVE_SET, SPDM_RES_TYPE, + SPDM_RES_ID, 1); + if (!rpm_req) + return -ENODEV; + msm_rpm_add_kvp_data(rpm_req, SPDM_KEY, (const uint8_t *)&one, + sizeof(int)); + id = msm_rpm_send_request(rpm_req); + msm_rpm_wait_for_ack(id); + msm_rpm_free_request(rpm_req); + + return 0; +} + +static int disable_clocks(void) +{ + struct msm_rpm_request *rpm_req; + int id; + const int zero = 0; + rpm_req = msm_rpm_create_request(MSM_RPM_CTX_ACTIVE_SET, SPDM_RES_TYPE, + SPDM_RES_ID, 1); + if (!rpm_req) + return -ENODEV; + msm_rpm_add_kvp_data(rpm_req, SPDM_KEY, (const uint8_t *)&zero, + sizeof(int)); + id = msm_rpm_send_request(rpm_req); + msm_rpm_wait_for_ack(id); + msm_rpm_free_request(rpm_req); + + return 0; +} + +static irqreturn_t threaded_isr(int irq, void *dev_id) +{ + struct spdm_data *data; + struct spdm_args desc = { { 0 } }; + int ext_status = 0; + + /* call hyp to get bw_vote */ + desc.arg[0] = SPDM_CMD_GET_BW_ALL; + ext_status = spdm_ext_call(&desc, 1); + if (ext_status) + pr_err("External command %u failed with error %u", + (int)desc.arg[0], ext_status); + mutex_lock(&devfreqs_lock); + list_for_each_entry(data, &devfreqs, list) { + if (data == NULL || data->devfreq == NULL) { + pr_err("Spurious interrupts\n"); + break; + } + if (data->spdm_client == desc.ret[0]) { + devfreq_monitor_suspend(data->devfreq); + mutex_lock(&data->devfreq->lock); + data->action = SPDM_UP; + data->new_bw = + (desc.ret[1] * 1000) >> 6; + update_devfreq(data->devfreq); + data->action = SPDM_DOWN; + mutex_unlock(&data->devfreq->lock); + devfreq_monitor_resume(data->devfreq); + break; + } + } + mutex_unlock(&devfreqs_lock); + return IRQ_HANDLED; +} + +static irqreturn_t isr(int irq, void *dev_id) +{ + return IRQ_WAKE_THREAD; +} + +static int gov_spdm_hyp_target_bw(struct devfreq *devfreq, unsigned long *freq, + u32 *flag) +{ + struct devfreq_dev_status status; + int ret = -EINVAL; + int usage; + struct spdm_args desc = { { 0 } }; + int ext_status = 0; + u64 bw_ret; + + if (!devfreq || !devfreq->profile || !devfreq->profile->get_dev_status) + return ret; + + ret = devfreq->profile->get_dev_status(devfreq->dev.parent, &status); + if (ret) + return ret; + + usage = (status.busy_time * 100) / status.total_time; + + if (usage > 0) { + /* up was already called as part of hyp, so just use the + * already stored values */ + *freq = ((struct spdm_data *)devfreq->data)->new_bw; + } else { + desc.arg[0] = SPDM_CMD_GET_BW_SPECIFIC; + desc.arg[1] = ((struct spdm_data *)devfreq->data)->spdm_client; + ext_status = spdm_ext_call(&desc, 2); + if (ext_status) + pr_err("External command %u failed with error %u", + (int)desc.arg[0], ext_status); + bw_ret = desc.ret[0] * 1000; + *freq = bw_ret >> 6; + } + + return 0; +} + +static int gov_spdm_hyp_eh(struct devfreq *devfreq, unsigned int event, + void *data) +{ + struct spdm_args desc = { { 0 } }; + int ext_status = 0; + struct spdm_data *spdm_data = (struct spdm_data *)devfreq->data; + int i; + + switch (event) { + case DEVFREQ_GOV_START: + mutex_lock(&devfreqs_lock); + list_add(&spdm_data->list, &devfreqs); + mutex_unlock(&devfreqs_lock); + /* call hyp with config data */ + desc.arg[0] = SPDM_CMD_CFG_PORTS; + desc.arg[1] = spdm_data->spdm_client; + desc.arg[2] = spdm_data->config_data.num_ports; + for (i = 0; i < spdm_data->config_data.num_ports; i++) + desc.arg[i+3] = spdm_data->config_data.ports[i]; + ext_status = spdm_ext_call(&desc, + spdm_data->config_data.num_ports + 3); + if (ext_status) + pr_err("External command %u failed with error %u", + (int)desc.arg[0], ext_status); + + desc.arg[0] = SPDM_CMD_CFG_FLTR; + desc.arg[1] = spdm_data->spdm_client; + desc.arg[2] = spdm_data->config_data.aup; + desc.arg[3] = spdm_data->config_data.adown; + desc.arg[4] = spdm_data->config_data.bucket_size; + ext_status = spdm_ext_call(&desc, 5); + if (ext_status) + pr_err("External command %u failed with error %u", + (int)desc.arg[0], ext_status); + + desc.arg[0] = SPDM_CMD_CFG_PL; + desc.arg[1] = spdm_data->spdm_client; + for (i = 0; i < SPDM_PL_COUNT - 1; i++) + desc.arg[i+2] = spdm_data->config_data.pl_freqs[i]; + ext_status = spdm_ext_call(&desc, SPDM_PL_COUNT + 1); + if (ext_status) + pr_err("External command %u failed with error %u", + (int)desc.arg[0], ext_status); + + desc.arg[0] = SPDM_CMD_CFG_REJRATE_LOW; + desc.arg[1] = spdm_data->spdm_client; + desc.arg[2] = spdm_data->config_data.reject_rate[0]; + desc.arg[3] = spdm_data->config_data.reject_rate[1]; + ext_status = spdm_ext_call(&desc, 4); + if (ext_status) + pr_err("External command %u failed with error %u", + (int)desc.arg[0], ext_status); + desc.arg[0] = SPDM_CMD_CFG_REJRATE_MED; + desc.arg[1] = spdm_data->spdm_client; + desc.arg[2] = spdm_data->config_data.reject_rate[2]; + desc.arg[3] = spdm_data->config_data.reject_rate[3]; + ext_status = spdm_ext_call(&desc, 4); + if (ext_status) + pr_err("External command %u failed with error %u", + (int)desc.arg[0], ext_status); + desc.arg[0] = SPDM_CMD_CFG_REJRATE_HIGH; + desc.arg[1] = spdm_data->spdm_client; + desc.arg[2] = spdm_data->config_data.reject_rate[4]; + desc.arg[3] = spdm_data->config_data.reject_rate[5]; + ext_status = spdm_ext_call(&desc, 4); + if (ext_status) + pr_err("External command %u failed with error %u", + (int)desc.arg[0], ext_status); + + desc.arg[0] = SPDM_CMD_CFG_RESPTIME_LOW; + desc.arg[1] = spdm_data->spdm_client; + desc.arg[2] = spdm_data->config_data.response_time_us[0]; + desc.arg[3] = spdm_data->config_data.response_time_us[1]; + ext_status = spdm_ext_call(&desc, 4); + if (ext_status) + pr_err("External command %u failed with error %u", + (int)desc.arg[0], ext_status); + desc.arg[0] = SPDM_CMD_CFG_RESPTIME_MED; + desc.arg[1] = spdm_data->spdm_client; + desc.arg[2] = spdm_data->config_data.response_time_us[2]; + desc.arg[3] = spdm_data->config_data.response_time_us[3]; + ext_status = spdm_ext_call(&desc, 4); + if (ext_status) + pr_err("External command %u failed with error %u", + (int)desc.arg[0], ext_status); + desc.arg[0] = SPDM_CMD_CFG_RESPTIME_HIGH; + desc.arg[1] = spdm_data->spdm_client; + desc.arg[2] = spdm_data->config_data.response_time_us[4]; + desc.arg[3] = spdm_data->config_data.response_time_us[5]; + ext_status = spdm_ext_call(&desc, 4); + if (ext_status) + pr_err("External command %u failed with error %u", + (int)desc.arg[0], ext_status); + + desc.arg[0] = SPDM_CMD_CFG_CCIRESPTIME_LOW; + desc.arg[1] = spdm_data->spdm_client; + desc.arg[2] = spdm_data->config_data.cci_response_time_us[0]; + desc.arg[3] = spdm_data->config_data.cci_response_time_us[1]; + ext_status = spdm_ext_call(&desc, 4); + if (ext_status) + pr_err("External command %u failed with error %u", + (int)desc.arg[0], ext_status); + desc.arg[0] = SPDM_CMD_CFG_CCIRESPTIME_MED; + desc.arg[1] = spdm_data->spdm_client; + desc.arg[2] = spdm_data->config_data.cci_response_time_us[2]; + desc.arg[3] = spdm_data->config_data.cci_response_time_us[3]; + ext_status = spdm_ext_call(&desc, 4); + if (ext_status) + pr_err("External command %u failed with error %u", + (int)desc.arg[0], ext_status); + desc.arg[0] = SPDM_CMD_CFG_CCIRESPTIME_HIGH; + desc.arg[1] = spdm_data->spdm_client; + desc.arg[2] = spdm_data->config_data.cci_response_time_us[4]; + desc.arg[3] = spdm_data->config_data.cci_response_time_us[5]; + ext_status = spdm_ext_call(&desc, 4); + if (ext_status) + pr_err("External command %u failed with error %u", + (int)desc.arg[0], ext_status); + + desc.arg[0] = SPDM_CMD_CFG_MAXCCI; + desc.arg[1] = spdm_data->spdm_client; + desc.arg[2] = spdm_data->config_data.max_cci_freq; + ext_status = spdm_ext_call(&desc, 3); + if (ext_status) + pr_err("External command %u failed with error %u", + (int)desc.arg[0], ext_status); + + desc.arg[0] = SPDM_CMD_CFG_VOTES; + desc.arg[1] = spdm_data->spdm_client; + desc.arg[2] = spdm_data->config_data.upstep; + desc.arg[3] = spdm_data->config_data.downstep; + desc.arg[4] = spdm_data->config_data.max_vote; + desc.arg[5] = spdm_data->config_data.up_step_multp; + ext_status = spdm_ext_call(&desc, 6); + if (ext_status) + pr_err("External command %u failed with error %u", + (int)desc.arg[0], ext_status); + + /* call hyp enable/commit */ + desc.arg[0] = SPDM_CMD_ENABLE; + desc.arg[1] = spdm_data->spdm_client; + desc.arg[2] = 0; + ext_status = spdm_ext_call(&desc, 3); + if (ext_status) { + pr_err("External command %u failed with error %u", + (int)desc.arg[0], ext_status); + mutex_lock(&devfreqs_lock); + /* + * the spdm device probe will fail so remove it from + * the list to prevent accessing a deleted pointer in + * the future + * */ + list_del(&spdm_data->list); + mutex_unlock(&devfreqs_lock); + return -EINVAL; + } + spdm_data->enabled = true; + devfreq_monitor_start(devfreq); + break; + + case DEVFREQ_GOV_STOP: + devfreq_monitor_stop(devfreq); + /* find devfreq in list and remove it */ + mutex_lock(&devfreqs_lock); + list_del(&spdm_data->list); + mutex_unlock(&devfreqs_lock); + + /* call hypvervisor to disable */ + desc.arg[0] = SPDM_CMD_DISABLE; + desc.arg[1] = spdm_data->spdm_client; + ext_status = spdm_ext_call(&desc, 2); + if (ext_status) + pr_err("External command %u failed with error %u", + (int)desc.arg[0], ext_status); + spdm_data->enabled = false; + break; + + case DEVFREQ_GOV_INTERVAL: + devfreq_interval_update(devfreq, (unsigned int *)data); + break; + + case DEVFREQ_GOV_SUSPEND: + devfreq_monitor_suspend(devfreq); + break; + + case DEVFREQ_GOV_RESUME: + devfreq_monitor_resume(devfreq); + break; + + default: + break; + } + + return 0; +} + +static struct devfreq_governor spdm_hyp_gov = { + .name = "spdm_bw_hyp", + .get_target_freq = gov_spdm_hyp_target_bw, + .event_handler = gov_spdm_hyp_eh, +}; + +static int probe(struct platform_device *pdev) +{ + int ret = -EINVAL; + int *irq = 0; + + irq = devm_kzalloc(&pdev->dev, sizeof(int), GFP_KERNEL); + if (!irq) + return -ENOMEM; + platform_set_drvdata(pdev, irq); + + ret = devfreq_add_governor(&spdm_hyp_gov); + if (ret) + goto nogov; + + *irq = platform_get_irq_byname(pdev, "spdm-irq"); + ret = request_threaded_irq(*irq, isr, threaded_isr, + IRQF_ONESHOT, + spdm_hyp_gov.name, pdev); + if (ret) + goto no_irq; + + enable_clocks(); + return 0; + +no_irq: + devfreq_remove_governor(&spdm_hyp_gov); +nogov: + devm_kfree(&pdev->dev, irq); + return ret; +} + +static int remove(struct platform_device *pdev) +{ + int *irq = 0; + + disable_clocks(); + irq = platform_get_drvdata(pdev); + free_irq(*irq, pdev); + devfreq_remove_governor(&spdm_hyp_gov); + devm_kfree(&pdev->dev, irq); + return 0; +} + +static const struct of_device_id gov_spdm_match[] = { + {.compatible = "qcom,gov_spdm_hyp"}, + {} +}; + +static struct platform_driver gov_spdm_hyp_drvr = { + .driver = { + .name = "gov_spdm_hyp", + .owner = THIS_MODULE, + .of_match_table = gov_spdm_match, + }, + .probe = probe, + .remove = remove, +}; + +static int __init governor_spdm_bw_hyp(void) +{ + return platform_driver_register(&gov_spdm_hyp_drvr); +} + +module_init(governor_spdm_bw_hyp); + +MODULE_LICENSE("GPL v2"); --- /dev/null 2019-10-24 16:47:25.704025805 +0200 +++ linux-4.4.115-fbx/drivers/dma/qcom-sps-dma.c 2019-01-22 16:16:23.159243291 +0100 @@ -0,0 +1,724 @@ +/* + * Copyright (c) 2014-2015, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +/* + * Qualcomm technologies inc, DMA API for BAM (Bus Access Manager). + * This DMA driver uses sps-BAM API to access the HW, thus it is effectively a + * DMA engine wrapper of the sps-BAM API. + * + * Client channel configuration example: + * struct dma_slave_config config { + * .direction = DMA_MEM_TO_DEV; + * }; + * + * chan = dma_request_slave_channel(client_dev, "rx"); + * dmaengine_slave_config(chan, &config); + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "dmaengine.h" + +#define QBAM_OF_SLAVE_N_ARGS (4) +#define QBAM_OF_MANAGE_LOCAL "qcom,managed-locally" +#define QBAM_OF_SUM_THRESHOLD "qcom,summing-threshold" +#define QBAM_MAX_DESCRIPTORS (0x100) +#define QBAM_MAX_CHANNELS (32) + +/* + * qbam_async_tx_descriptor - dma descriptor plus a list of xfer_bufs + * + * @sgl scatterlist of transfer buffers + * @sg_len size of that list + * @flags dma xfer flags + */ +struct qbam_async_tx_descriptor { + struct dma_async_tx_descriptor dma_desc; + struct scatterlist *sgl; + unsigned int sg_len; + unsigned long flags; +}; + +#define DMA_TO_QBAM_ASYNC_DESC(dma_async_desc) \ + container_of(dma_async_desc, struct qbam_async_tx_descriptor, dma_desc) + +struct qbam_channel; +/* + * qbam_device - top level device of current driver + * @handle bam sps handle. + * @regs bam register space virtual base address. + * @mem_resource bam register space resource. + * @deregister_required if bam is registered by this driver it need to be + * unregistered by this driver. + * @manage is bame managed locally or remotely, + * @summing_threshold event threshold. + * @irq bam interrupt line. + * @channels has the same channels as qbam_dev->dma_dev.channels but + * supports fast access by pipe index. + */ +struct qbam_device { + struct dma_device dma_dev; + void __iomem *regs; + struct resource *mem_resource; + ulong handle; + bool deregister_required; + u32 summing_threshold; + u32 manage; + int irq; + struct qbam_channel *channels[QBAM_MAX_CHANNELS]; +}; + +/* qbam_pipe: aggregate of bam pipe related entries of qbam_channel */ +struct qbam_pipe { + u32 index; + struct sps_pipe *handle; + struct sps_connect cfg; + u32 num_descriptors; + u32 sps_connect_flags; + u32 sps_register_event_flags; +}; + +/* + * qbam_channel - dma channel plus bam pipe info and current pending transfers + * + * @direction is a producer or consumer (MEM => DEV or DEV => MEM) + * @pending_desc next set of transfer to process + * @error last error that took place on the current pending_desc + */ +struct qbam_channel { + struct qbam_pipe bam_pipe; + + struct dma_chan chan; + enum dma_transfer_direction direction; + struct qbam_async_tx_descriptor pending_desc; + + struct qbam_device *qbam_dev; + struct mutex lock; + int error; +}; +#define DMA_TO_QBAM_CHAN(dma_chan) \ + container_of(dma_chan, struct qbam_channel, chan) +#define qbam_err(qbam_dev, fmt ...) dev_err(qbam_dev->dma_dev.dev, fmt) + +/* qbam_disconnect_chan - disconnect a channel */ +static int qbam_disconnect_chan(struct qbam_channel *qbam_chan) +{ + struct qbam_device *qbam_dev = qbam_chan->qbam_dev; + struct sps_pipe *pipe_handle = qbam_chan->bam_pipe.handle; + struct sps_connect pipe_config_no_irq = {.options = SPS_O_POLL}; + int ret; + + /* + * SW workaround: + * When disconnecting BAM pipe a spurious interrupt sometimes appears. + * To avoid that, we change the pipe setting from interrupt (default) + * to polling (SPS_O_POLL) before diconnecting the pipe. + */ + ret = sps_set_config(pipe_handle, &pipe_config_no_irq); + if (ret) + qbam_err(qbam_dev, + "error:%d sps_set_config(pipe:%d) before disconnect\n", + ret, qbam_chan->bam_pipe.index); + + ret = sps_disconnect(pipe_handle); + if (ret) + qbam_err(qbam_dev, "error:%d sps_disconnect(pipe:%d)\n", + ret, qbam_chan->bam_pipe.index); + + return ret; +} + +/* qbam_free_chan - disconnect channel and free its resources */ +static void qbam_free_chan(struct dma_chan *chan) +{ + struct qbam_channel *qbam_chan = DMA_TO_QBAM_CHAN(chan); + struct qbam_device *qbam_dev = qbam_chan->qbam_dev; + + mutex_lock(&qbam_chan->lock); + if (qbam_disconnect_chan(qbam_chan)) + qbam_err(qbam_dev, + "error free_chan() failed to disconnect(pipe:%d)\n", + qbam_chan->bam_pipe.index); + qbam_chan->pending_desc.sgl = NULL; + qbam_chan->pending_desc.sg_len = 0; + mutex_unlock(&qbam_chan->lock); +} + +static struct dma_chan *qbam_dma_xlate(struct of_phandle_args *dma_spec, + struct of_dma *of) +{ + struct qbam_device *qbam_dev = of->of_dma_data; + struct qbam_channel *qbam_chan; + u32 channel_index; + u32 num_descriptors; + + if (dma_spec->args_count != QBAM_OF_SLAVE_N_ARGS) { + qbam_err(qbam_dev, + "invalid number of dma arguments, expect:%d got:%d\n", + QBAM_OF_SLAVE_N_ARGS, dma_spec->args_count); + return NULL; + }; + + channel_index = dma_spec->args[0]; + + if (channel_index >= QBAM_MAX_CHANNELS) { + qbam_err(qbam_dev, + "error: channel_index:%d out of bounds", + channel_index); + return NULL; + } + qbam_chan = qbam_dev->channels[channel_index]; + /* return qbam_chan if exists, or create one */ + if (qbam_chan) { + qbam_chan->chan.client_count = 1; + return &qbam_chan->chan; + } + + num_descriptors = dma_spec->args[1]; + if (!num_descriptors || (num_descriptors > QBAM_MAX_DESCRIPTORS)) { + qbam_err(qbam_dev, + "invalid number of descriptors, range[1..%d] got:%d\n", + QBAM_MAX_DESCRIPTORS, num_descriptors); + return NULL; + } + + /* allocate a channel */ + qbam_chan = kzalloc(sizeof(*qbam_chan), GFP_KERNEL); + if (!qbam_chan) { + qbam_err(qbam_dev, "error kmalloc(size:%llu) failed\n", + (u64) sizeof(*qbam_chan)); + return NULL; + } + + /* allocate BAM resources for that channel */ + qbam_chan->bam_pipe.handle = sps_alloc_endpoint(); + if (!qbam_chan->bam_pipe.handle) { + qbam_err(qbam_dev, "error: sps_alloc_endpoint() return NULL\n"); + kfree(qbam_chan); + return NULL; + } + + /* init dma_chan */ + qbam_chan->chan.device = &qbam_dev->dma_dev; + dma_cookie_init(&qbam_chan->chan); + qbam_chan->chan.client_count = 1; + /* init qbam_chan */ + qbam_chan->bam_pipe.index = channel_index; + qbam_chan->bam_pipe.num_descriptors = num_descriptors; + qbam_chan->bam_pipe.sps_connect_flags = dma_spec->args[2]; + qbam_chan->bam_pipe.sps_register_event_flags = dma_spec->args[3]; + qbam_chan->qbam_dev = qbam_dev; + mutex_init(&qbam_chan->lock); + + /* add to dma_device list of channels */ + list_add(&qbam_chan->chan.device_node, &qbam_dev->dma_dev.channels); + qbam_dev->channels[channel_index] = qbam_chan; + + return &qbam_chan->chan; +} + +static enum dma_status qbam_tx_status(struct dma_chan *chan, + dma_cookie_t cookie, struct dma_tx_state *state) +{ + struct qbam_channel *qbam_chan = DMA_TO_QBAM_CHAN(chan); + struct qbam_async_tx_descriptor *qbam_desc = &qbam_chan->pending_desc; + enum dma_status ret; + + mutex_lock(&qbam_chan->lock); + + if (qbam_chan->error) { + mutex_unlock(&qbam_chan->lock); + return DMA_ERROR; + } + + ret = dma_cookie_status(chan, cookie, state); + if (ret == DMA_IN_PROGRESS) { + struct scatterlist *sg; + int i; + u32 transfer_size = 0; + + for_each_sg(qbam_desc->sgl, sg, qbam_desc->sg_len, i) + transfer_size += sg_dma_len(sg); + + dma_set_residue(state, transfer_size); + } + mutex_unlock(&qbam_chan->lock); + + return ret; +} + +/* + * qbam_init_bam_handle - find or create bam handle. + * + * BAM device needs to be registerd for each BLSP once and only once. if it was + * registred, then we find the handle to the registerd bam and return it, + * otherwise we register it here. + * The module which registerd BAM is responsible for deregistering it. + */ +static int qbam_init_bam_handle(struct qbam_device *qbam_dev) +{ + int ret = 0; + struct sps_bam_props bam_props = {0}; + + /* + * Check if BAM is already registred with SPS on the current + * BLSP. If it isn't then go ahead and register it. + */ + ret = sps_phy2h(qbam_dev->mem_resource->start, &qbam_dev->handle); + if (qbam_dev->handle) + return 0; + + qbam_dev->regs = devm_ioremap_resource(qbam_dev->dma_dev.dev, + qbam_dev->mem_resource); + if (IS_ERR(qbam_dev->regs)) { + qbam_err(qbam_dev, "error:%ld ioremap(phy:0x%lx len:0x%lx)\n", + PTR_ERR(qbam_dev->regs), + (ulong) qbam_dev->mem_resource->start, + (ulong) resource_size(qbam_dev->mem_resource)); + return PTR_ERR(qbam_dev->regs); + }; + + bam_props.phys_addr = qbam_dev->mem_resource->start; + bam_props.virt_addr = qbam_dev->regs; + bam_props.summing_threshold = qbam_dev->summing_threshold; + bam_props.manage = qbam_dev->manage; + bam_props.irq = qbam_dev->irq; + + ret = sps_register_bam_device(&bam_props, &qbam_dev->handle); + if (ret) + qbam_err(qbam_dev, "error:%d sps_register_bam_device\n" + "(phy:0x%lx virt:0x%lx irq:%d)\n", + ret, (ulong) bam_props.phys_addr, + (ulong) bam_props.virt_addr, qbam_dev->irq); + else + qbam_dev->deregister_required = true; + + return ret; +} + + +static int qbam_alloc_chan(struct dma_chan *chan) +{ + return 0; +} + +static void qbam_eot_callback(struct sps_event_notify *notify) +{ + struct qbam_async_tx_descriptor *qbam_desc = notify->data.transfer.user; + struct dma_async_tx_descriptor *dma_desc = &qbam_desc->dma_desc; + dma_async_tx_callback callback = dma_desc->callback; + void *param = dma_desc->callback_param; + + if (callback) + callback(param); +} + +static void qbam_error_callback(struct sps_event_notify *notify) +{ + struct qbam_channel *qbam_chan = notify->user; + qbam_err(qbam_chan->qbam_dev, "error: qbam_error_callback(pipe:%d\n)", + qbam_chan->bam_pipe.index); +} + +static int qbam_connect_chan(struct qbam_channel *qbam_chan) +{ + int ret = 0; + struct qbam_device *qbam_dev = qbam_chan->qbam_dev; + struct sps_register_event bam_eot_event = { + .mode = SPS_TRIGGER_CALLBACK, + .options = qbam_chan->bam_pipe.sps_register_event_flags, + .callback = qbam_eot_callback, + }; + struct sps_register_event bam_error_event = { + .mode = SPS_TRIGGER_CALLBACK, + .options = SPS_O_ERROR, + .callback = qbam_error_callback, + .user = qbam_chan, + }; + + ret = sps_connect(qbam_chan->bam_pipe.handle, &qbam_chan->bam_pipe.cfg); + if (ret) { + qbam_err(qbam_dev, "error:%d sps_connect(pipe:%d)\n", ret, + qbam_chan->bam_pipe.index); + return ret; + } + + ret = sps_register_event(qbam_chan->bam_pipe.handle, &bam_eot_event); + if (ret) { + qbam_err(qbam_dev, "error:%d sps_register_event(eot@pipe:%d)\n", + ret, qbam_chan->bam_pipe.index); + goto need_disconnect; + } + + ret = sps_register_event(qbam_chan->bam_pipe.handle, &bam_error_event); + if (ret) { + qbam_err(qbam_dev, "error:%d sps_register_event(err@pipe:%d)\n", + ret, qbam_chan->bam_pipe.index); + goto need_disconnect; + } + + return 0; + +need_disconnect: + ret = sps_disconnect(qbam_chan->bam_pipe.handle); + if (ret) + qbam_err(qbam_dev, "error:%d sps_disconnect(pipe:%d)\n", ret, + qbam_chan->bam_pipe.index); + return ret; +} + +/* + * qbam_slave_cfg - configure and connect a BAM pipe + * + * @cfg only cares about cfg->direction + */ +static int qbam_slave_cfg(struct dma_chan *chan, + struct dma_slave_config *cfg) +{ + int ret = 0; + struct qbam_channel *qbam_chan = DMA_TO_QBAM_CHAN(chan); + struct qbam_device *qbam_dev = qbam_chan->qbam_dev; + struct sps_connect *pipe_cfg = &qbam_chan->bam_pipe.cfg; + + if (!qbam_dev->handle) { + ret = qbam_init_bam_handle(qbam_dev); + if (ret) + return ret; + } + + if (qbam_chan->bam_pipe.cfg.desc.base) + goto cfg_done; + + ret = sps_get_config(qbam_chan->bam_pipe.handle, + &qbam_chan->bam_pipe.cfg); + if (ret) { + qbam_err(qbam_dev, "error:%d sps_get_config(0x%p)\n", + ret, qbam_chan->bam_pipe.handle); + return ret; + } + + qbam_chan->direction = cfg->direction; + if (cfg->direction == DMA_MEM_TO_DEV) { + pipe_cfg->source = SPS_DEV_HANDLE_MEM; + pipe_cfg->destination = qbam_dev->handle; + pipe_cfg->mode = SPS_MODE_DEST; + pipe_cfg->src_pipe_index = 0; + pipe_cfg->dest_pipe_index = qbam_chan->bam_pipe.index; + } else { + pipe_cfg->source = qbam_dev->handle; + pipe_cfg->destination = SPS_DEV_HANDLE_MEM; + pipe_cfg->mode = SPS_MODE_SRC; + pipe_cfg->src_pipe_index = qbam_chan->bam_pipe.index; + pipe_cfg->dest_pipe_index = 0; + } + pipe_cfg->options = qbam_chan->bam_pipe.sps_connect_flags; + pipe_cfg->desc.size = (qbam_chan->bam_pipe.num_descriptors + 1) * + sizeof(struct sps_iovec); + /* managed dma_alloc_coherent() */ + pipe_cfg->desc.base = dmam_alloc_coherent(qbam_dev->dma_dev.dev, + pipe_cfg->desc.size, + &pipe_cfg->desc.phys_base, + GFP_KERNEL); + if (!pipe_cfg->desc.base) { + qbam_err(qbam_dev, + "error dma_alloc_coherent(desc-sz:%llu * n-descs:%d)\n", + (u64) sizeof(struct sps_iovec), + qbam_chan->bam_pipe.num_descriptors); + return -ENOMEM; + } +cfg_done: + ret = qbam_connect_chan(qbam_chan); + if (ret) + dmam_free_coherent(qbam_dev->dma_dev.dev, pipe_cfg->desc.size, + pipe_cfg->desc.base, pipe_cfg->desc.phys_base); + + return ret; +} + +static int qbam_flush_chan(struct dma_chan *chan) +{ + struct qbam_channel *qbam_chan = DMA_TO_QBAM_CHAN(chan); + int ret = qbam_disconnect_chan(qbam_chan); + if (ret) { + qbam_err(qbam_chan->qbam_dev, + "error: disconnect flush(pipe:%d\n)", + qbam_chan->bam_pipe.index); + return ret; + } + ret = qbam_connect_chan(qbam_chan); + if (ret) + qbam_err(qbam_chan->qbam_dev, + "error: reconnect flush(pipe:%d\n)", + qbam_chan->bam_pipe.index); + return ret; +} + +/* qbam_tx_submit - sets the descriptor as the next one to be executed */ +static dma_cookie_t qbam_tx_submit(struct dma_async_tx_descriptor *dma_desc) +{ + struct qbam_channel *qbam_chan = DMA_TO_QBAM_CHAN(dma_desc->chan); + dma_cookie_t ret; + mutex_lock(&qbam_chan->lock); + + ret = dma_cookie_assign(dma_desc); + + mutex_unlock(&qbam_chan->lock); + + return ret; +} + +/* + * qbam_prep_slave_sg - creates qbam_xfer_buf from a list of sg + * + * @chan: dma channel + * @sgl: scatter gather list + * @sg_len: length of sg + * @direction: DMA transfer direction + * @flags: DMA flags + * @context: transfer context (unused) + * @return the newly created descriptor or negative ERR_PTR() on error + */ +static struct dma_async_tx_descriptor *qbam_prep_slave_sg(struct dma_chan *chan, + struct scatterlist *sgl, unsigned int sg_len, + enum dma_transfer_direction direction, unsigned long flags, + void *context) +{ + struct qbam_channel *qbam_chan = DMA_TO_QBAM_CHAN(chan); + struct qbam_device *qbam_dev = qbam_chan->qbam_dev; + struct qbam_async_tx_descriptor *qbam_desc = &qbam_chan->pending_desc; + + if (qbam_chan->direction != direction) { + qbam_err(qbam_dev, + "invalid dma transfer direction expected:%d given:%d\n", + qbam_chan->direction, direction); + return ERR_PTR(-EINVAL); + } + + qbam_desc->dma_desc.chan = &qbam_chan->chan; + qbam_desc->dma_desc.tx_submit = qbam_tx_submit; + qbam_desc->sgl = sgl; + qbam_desc->sg_len = sg_len; + qbam_desc->flags = flags; + return &qbam_desc->dma_desc; +} + +/* + * qbam_issue_pending - queue pending descriptor to BAM + * + * Iterate over the transfers of the pending descriptor and push them to bam + */ +static void qbam_issue_pending(struct dma_chan *chan) +{ + int i; + int ret = 0; + struct qbam_channel *qbam_chan = DMA_TO_QBAM_CHAN(chan); + struct qbam_device *qbam_dev = qbam_chan->qbam_dev; + struct qbam_async_tx_descriptor *qbam_desc = &qbam_chan->pending_desc; + struct scatterlist *sg; + mutex_lock(&qbam_chan->lock); + if (!qbam_chan->pending_desc.sgl) { + qbam_err(qbam_dev, + "error qbam_issue_pending() no pending descriptor pipe:%d\n", + qbam_chan->bam_pipe.index); + mutex_unlock(&qbam_chan->lock); + return; + } + + for_each_sg(qbam_desc->sgl, sg, qbam_desc->sg_len, i) { + + /* Add BAM flags only on the last buffer */ + bool is_last_buf = (i == ((qbam_desc->sg_len) - 1)); + + ret = sps_transfer_one(qbam_chan->bam_pipe.handle, + sg_dma_address(sg), sg_dma_len(sg), + qbam_desc, + (is_last_buf ? qbam_desc->flags : 0)); + if (ret < 0) { + qbam_chan->error = ret; + + qbam_err(qbam_dev, "erorr:%d sps_transfer_one\n" + "(addr:0x%lx len:%d flags:0x%lx pipe:%d)\n", + ret, (ulong) sg_dma_address(sg), sg_dma_len(sg), + qbam_desc->flags, qbam_chan->bam_pipe.index); + break; + } + } + + dma_cookie_complete(&qbam_desc->dma_desc); + qbam_chan->error = 0; + qbam_desc->sgl = NULL; + qbam_desc->sg_len = 0; + mutex_unlock(&qbam_chan->lock); +}; + +static int qbam_deregister_bam_dev(struct qbam_device *qbam_dev) +{ + int ret; + + if (!qbam_dev->handle) + return 0; + + ret = sps_deregister_bam_device(qbam_dev->handle); + if (ret) + qbam_err(qbam_dev, + "error:%d sps_deregister_bam_device(hndl:0x%lx) failed", + ret, qbam_dev->handle); + return ret; +} + +static void qbam_pipes_free(struct qbam_device *qbam_dev) +{ + struct qbam_channel *qbam_chan_cur, *qbam_chan_next; + + list_for_each_entry_safe(qbam_chan_cur, qbam_chan_next, + &qbam_dev->dma_dev.channels, chan.device_node) { + mutex_lock(&qbam_chan_cur->lock); + qbam_free_chan(&qbam_chan_cur->chan); + sps_free_endpoint(qbam_chan_cur->bam_pipe.handle); + list_del(&qbam_chan_cur->chan.device_node); + mutex_unlock(&qbam_chan_cur->lock); + kfree(qbam_chan_cur); + } +} + +static int qbam_probe(struct platform_device *pdev) +{ + struct qbam_device *qbam_dev; + int ret; + bool managed_locally; + struct device_node *of_node = pdev->dev.of_node; + + qbam_dev = devm_kzalloc(&pdev->dev, sizeof(*qbam_dev), GFP_KERNEL); + if (!qbam_dev) { + qbam_err(qbam_dev, "error kmalloc(size:%llu) failed", + (u64) sizeof(*qbam_dev)); + return -ENOMEM; + } + qbam_dev->dma_dev.dev = &pdev->dev; + platform_set_drvdata(pdev, qbam_dev); + + qbam_dev->mem_resource = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!qbam_dev->mem_resource) { + qbam_err(qbam_dev, "missing 'reg' DT entry"); + return -ENODEV; + } + + qbam_dev->irq = platform_get_irq(pdev, 0); + if (qbam_dev->irq < 0) { + qbam_err(qbam_dev, "missing DT IRQ resource entry"); + return -EINVAL; + } + + ret = of_property_read_u32(of_node, QBAM_OF_SUM_THRESHOLD, + &qbam_dev->summing_threshold); + if (ret) { + qbam_err(qbam_dev, "missing '%s' DT entry", + QBAM_OF_SUM_THRESHOLD); + return ret; + } + + /* read from DT and set sps_bam_props.manage */ + managed_locally = of_property_read_bool(of_node, QBAM_OF_MANAGE_LOCAL); + qbam_dev->manage = managed_locally ? SPS_BAM_MGR_LOCAL : + SPS_BAM_MGR_DEVICE_REMOTE; + + /* Init channels */ + INIT_LIST_HEAD(&qbam_dev->dma_dev.channels); + + /* Set capabilities */ + dma_cap_zero(qbam_dev->dma_dev.cap_mask); + dma_cap_set(DMA_SLAVE, qbam_dev->dma_dev.cap_mask); + dma_cap_set(DMA_PRIVATE, qbam_dev->dma_dev.cap_mask); + + /* Initialize dmaengine callback apis */ + qbam_dev->dma_dev.device_alloc_chan_resources = qbam_alloc_chan; + qbam_dev->dma_dev.device_free_chan_resources = qbam_free_chan; + qbam_dev->dma_dev.device_prep_slave_sg = qbam_prep_slave_sg; + qbam_dev->dma_dev.device_terminate_all = qbam_flush_chan; + qbam_dev->dma_dev.device_config = qbam_slave_cfg; + qbam_dev->dma_dev.device_issue_pending = qbam_issue_pending; + qbam_dev->dma_dev.device_tx_status = qbam_tx_status; + + /* Regiser to DMA framework */ + ret = dma_async_device_register(&qbam_dev->dma_dev); + if (ret) { + qbam_err(qbam_dev, "error:%d dma_async_device_register()\n", + ret); + goto err_unregister_bam; + } + + ret = of_dma_controller_register(of_node, qbam_dma_xlate, qbam_dev); + if (ret) { + qbam_err(qbam_dev, "error:%d of_dma_controller_register()\n", + ret); + goto err_unregister_dma; + } + return 0; + +err_unregister_dma: + dma_async_device_unregister(&qbam_dev->dma_dev); +err_unregister_bam: + if (qbam_dev->deregister_required) + return qbam_deregister_bam_dev(qbam_dev); + + return ret; +} + +static int qbam_remove(struct platform_device *pdev) +{ + struct qbam_device *qbam_dev = platform_get_drvdata(pdev); + + dma_async_device_unregister(&qbam_dev->dma_dev); + + /* free BAM pipes resources */ + qbam_pipes_free(qbam_dev); + + if (qbam_dev->deregister_required) + return qbam_deregister_bam_dev(qbam_dev); + + return 0; +} + +static const struct of_device_id qbam_of_match[] = { + { .compatible = "qcom,sps-dma" }, + {} +}; +MODULE_DEVICE_TABLE(of, qbam_of_match); + +static struct platform_driver qbam_driver = { + .probe = qbam_probe, + .remove = qbam_remove, + .driver = { + .name = "qcom-sps-dma", + .owner = THIS_MODULE, + .of_match_table = qbam_of_match, + }, +}; + +module_platform_driver(qbam_driver); + +MODULE_DESCRIPTION("DMA-API driver to qcom BAM"); +MODULE_LICENSE("GPL v2"); +MODULE_ALIAS("platform:qcom-sps-dma"); --- /dev/null 2019-10-24 16:47:25.704025805 +0200 +++ linux-4.4.115-fbx/drivers/edac/cortex_arm64_edac.c 2019-01-22 16:16:23.167243364 +0100 @@ -0,0 +1,1002 @@ +/* Copyright (c) 2014-2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include "edac_core.h" + +#define A53_CPUMERRSR_FATAL(a) ((a) & (1LL << 63)) +#define A53_CPUMERRSR_OTHER(a) (((a) >> 40) & 0xff) +#define A53_CPUMERRSR_REPT(a) (((a) >> 32) & 0xff) +#define A53_CPUMERRSR_VALID(a) ((a) & (1 << 31)) +#define A53_CPUMERRSR_RAMID(a) (((a) >> 24) & 0x7f) +#define A53_CPUMERRSR_CPUID(a) (((a) >> 18) & 0x07) +#define A53_CPUMERRSR_ADDR(a) ((a) & 0xfff) + +#define A53_L2MERRSR_FATAL(a) ((a) & (1LL << 63)) +#define A53_L2MERRSR_OTHER(a) (((a) >> 40) & 0xff) +#define A53_L2MERRSR_REPT(a) (((a) >> 32) & 0xff) +#define A53_L2MERRSR_VALID(a) ((a) & (1 << 31)) +#define A53_L2MERRSR_RAMID(a) (((a) >> 24) & 0x7f) +#define A53_L2MERRSR_CPUID(a) (((a) >> 18) & 0x0f) +#define A53_L2MERRSR_INDEX(a) (((a) >> 3) & 0x3fff) + +#define A57_CPUMERRSR_FATAL(a) ((a) & (1LL << 63)) +#define A57_CPUMERRSR_OTHER(a) (((a) >> 40) & 0xff) +#define A57_CPUMERRSR_REPT(a) (((a) >> 32) & 0xff) +#define A57_CPUMERRSR_VALID(a) ((a) & (1 << 31)) +#define A57_CPUMERRSR_RAMID(a) (((a) >> 24) & 0x7f) +#define A57_CPUMERRSR_BANK(a) (((a) >> 18) & 0x1f) +#define A57_CPUMERRSR_INDEX(a) ((a) & 0x1ffff) + +#define A57_L2MERRSR_FATAL(a) ((a) & (1LL << 63)) +#define A57_L2MERRSR_OTHER(a) (((a) >> 40) & 0xff) +#define A57_L2MERRSR_REPT(a) (((a) >> 32) & 0xff) +#define A57_L2MERRSR_VALID(a) ((a) & (1 << 31)) +#define A57_L2MERRSR_RAMID(a) (((a) >> 24) & 0x7f) +#define A57_L2MERRSR_CPUID(a) (((a) >> 18) & 0x0f) +#define A57_L2MERRSR_INDEX(a) ((a) & 0x1ffff) + +#define KRYO2XX_GOLD_L2MERRSR_FATAL(a) ((a) & (1LL << 63)) +#define KRYO2XX_GOLD_L2MERRSR_OTHER(a) (((a) >> 40) & 0x3f) +#define KRYO2XX_GOLD_L2MERRSR_REPT(a) (((a) >> 32) & 0x3f) +#define KRYO2XX_GOLD_L2MERRSR_VALID(a) ((a) & (1 << 31)) +#define KRYO2XX_GOLD_L2MERRSR_RAMID(a) ((a) & (1 << 24)) +#define KRYO2XX_GOLD_L2MERRSR_WAY(a) (((a) >> 18) & 0x0f) +#define KRYO2XX_GOLD_L2MERRSR_INDEX(a) (((a) >> 3) & 0x3fff) + +#define L2ECTLR_INT_ERR (1 << 30) +#define L2ECTLR_EXT_ERR (1 << 29) + +#define ESR_SERROR(a) ((a) >> ESR_ELx_EC_SHIFT == ESR_ELx_EC_SERROR) +#define ESR_VALID(a) ((a) & BIT(24)) +#define ESR_L2_DBE(a) (ESR_SERROR(a) && ESR_VALID(a) && \ + (((a) & 0x00C00003) == 0x1)) + +#define CCI_IMPRECISEERROR_REG 0x10 + +#define L1_CACHE 0 +#define L2_CACHE 1 +#define CCI 2 + +#define A53_L1_CE 0 +#define A53_L1_UE 1 +#define A53_L2_CE 2 +#define A53_L2_UE 3 +#define A57_L1_CE 4 +#define A57_L1_UE 5 +#define A57_L2_CE 6 +#define A57_L2_UE 7 +#define L2_EXT_UE 8 +#define CCI_UE 9 +#define KRYO2XX_SILVER_L1_CE 10 +#define KRYO2XX_SILVER_L1_UE 11 +#define KRYO2XX_SILVER_L2_CE 12 +#define KRYO2XX_SILVER_L2_UE 13 +#define KRYO2XX_GOLD_L2_CE 14 +#define KRYO2XX_GOLD_L2_UE 15 + +#ifdef CONFIG_EDAC_CORTEX_ARM64_PANIC_ON_UE +#define ARM64_ERP_PANIC_ON_UE 1 +#else +#define ARM64_ERP_PANIC_ON_UE 0 +#endif + +#ifdef CONFIG_EDAC_CORTEX_ARM64_PANIC_ON_CE +static int panic_on_ce = 1; +#else +static int panic_on_ce; +#endif +module_param(panic_on_ce, int, 0); + +#define EDAC_CPU "arm64" + +enum error_type { + SBE, + DBE, +}; + +const char *err_name[] = { + "Single-bit", + "Double-bit", +}; + +struct erp_drvdata { + struct edac_device_ctl_info *edev_ctl; + void __iomem *cci_base; + struct notifier_block nb_pm; + struct notifier_block nb_cpu; + struct notifier_block nb_panic; + struct work_struct work; + struct perf_event *memerr_counters[NR_CPUS]; +}; + +static struct erp_drvdata *panic_handler_drvdata; + +struct erp_local_data { + struct erp_drvdata *drv; + enum error_type err; +}; + +#define MEM_ERROR_EVENT 0x1A + +struct errors_edac { + const char * const msg; + void (*func)(struct edac_device_ctl_info *edac_dev, + int inst_nr, int block_nr, const char *msg); +}; + +static const struct errors_edac errors[] = { + {"A53 L1 Correctable Error", edac_device_handle_ce }, + {"A53 L1 Uncorrectable Error", edac_device_handle_ue }, + {"A53 L2 Correctable Error", edac_device_handle_ce }, + {"A53 L2 Uncorrectable Error", edac_device_handle_ue }, + {"A57 L1 Correctable Error", edac_device_handle_ce }, + {"A57 L1 Uncorrectable Error", edac_device_handle_ue }, + {"A57 L2 Correctable Error", edac_device_handle_ce }, + {"A57 L2 Uncorrectable Error", edac_device_handle_ue }, + {"L2 External Error", edac_device_handle_ue }, + {"CCI Error", edac_device_handle_ue }, + {"Kryo2xx Silver L1 Correctable Error", edac_device_handle_ce }, + {"Kryo2xx Silver L1 Uncorrectable Error", edac_device_handle_ue }, + {"Kryo2xx Silver L2 Correctable Error", edac_device_handle_ce }, + {"Kryo2xx Silver L2 Uncorrectable Error", edac_device_handle_ue }, + {"Kryo2xx Gold L2 Correctable Error", edac_device_handle_ce }, + {"Kryo2xx Gold L2 Uncorrectable Error", edac_device_handle_ue }, +}; + +#define read_l2merrsr_el1 ({ \ + u64 __val; \ + asm("mrs %0, s3_1_c15_c2_3" : "=r" (__val)); \ + __val; \ +}) + +#define read_l2ectlr_el1 ({ \ + u32 __val; \ + asm("mrs %0, s3_1_c11_c0_3" : "=r" (__val)); \ + __val; \ +}) + +#define read_cpumerrsr_el1 ({ \ + u64 __val; \ + asm("mrs %0, s3_1_c15_c2_2" : "=r" (__val)); \ + __val; \ +}) + +#define read_esr_el1 ({ \ + u64 __val; \ + asm("mrs %0, esr_el1" : "=r" (__val)); \ + __val; \ +}) + +#define write_l2merrsr_el1(val) ({ \ + asm("msr s3_1_c15_c2_3, %0" : : "r" (val)); \ +}) + +#define write_l2ectlr_el1(val) ({ \ + asm("msr s3_1_c11_c0_3, %0" : : "r" (val)); \ +}) + +#define write_cpumerrsr_el1(val) ({ \ + asm("msr s3_1_c15_c2_2, %0" : : "r" (val)); \ +}) + +static void kryo2xx_print_error_state_regs(void) +{ + u64 l2merrsr; + u64 cpumerrsr; + u32 esr_el1; + u32 l2ectlr; + + cpumerrsr = read_cpumerrsr_el1; + l2merrsr = read_l2merrsr_el1; + esr_el1 = read_esr_el1; + l2ectlr = read_l2ectlr_el1; + + /* store data in uncached rtb logs */ + uncached_logk_pc(LOGK_READL, __builtin_return_address(0), + (void *)cpumerrsr); + uncached_logk_pc(LOGK_READL, __builtin_return_address(0), + (void *)l2merrsr); + uncached_logk_pc(LOGK_READL, __builtin_return_address(0), + (void *)((u64)esr_el1)); + uncached_logk_pc(LOGK_READL, __builtin_return_address(0), + (void *)((u64)l2ectlr)); + + edac_printk(KERN_CRIT, EDAC_CPU, "CPUMERRSR value = %#llx\n", + cpumerrsr); + edac_printk(KERN_CRIT, EDAC_CPU, "L2MERRSR value = %#llx\n", l2merrsr); + + edac_printk(KERN_CRIT, EDAC_CPU, "ESR value = %#x\n", esr_el1); + edac_printk(KERN_CRIT, EDAC_CPU, "L2ECTLR value = %#x\n", l2ectlr); + if (ESR_L2_DBE(esr_el1)) + edac_printk(KERN_CRIT, EDAC_CPU, + "Double bit error on dirty L2 cacheline\n"); +} + +static void kryo2xx_gold_print_error_state_regs(void) +{ + u64 l2merrsr; + u32 esr_el1; + u32 l2ectlr; + + l2merrsr = read_l2merrsr_el1; + esr_el1 = read_esr_el1; + l2ectlr = read_l2ectlr_el1; + + uncached_logk_pc(LOGK_READL, __builtin_return_address(0), + (void *)l2merrsr); + uncached_logk_pc(LOGK_READL, __builtin_return_address(0), + (void *)((u64)esr_el1)); + uncached_logk_pc(LOGK_READL, __builtin_return_address(0), + (void *)((u64)l2ectlr)); + + edac_printk(KERN_CRIT, EDAC_CPU, "L2MERRSR value = %#llx\n", l2merrsr); + + edac_printk(KERN_CRIT, EDAC_CPU, "ESR value = %#x\n", esr_el1); + edac_printk(KERN_CRIT, EDAC_CPU, "L2ECTLR value = %#x\n", l2ectlr); + if (ESR_L2_DBE(esr_el1)) + edac_printk(KERN_CRIT, EDAC_CPU, + "Double bit error on dirty L2 cacheline\n"); +} + +static void kryo2xx_silver_parse_cpumerrsr(struct erp_local_data *ed) +{ + u64 cpumerrsr; + int cpuid; + + cpumerrsr = read_cpumerrsr_el1; + + if (!A53_CPUMERRSR_VALID(cpumerrsr)) + return; + + if (A53_CPUMERRSR_FATAL(cpumerrsr)) + ed->err = DBE; + + edac_printk(KERN_CRIT, EDAC_CPU, + "Kryo2xx Silver CPU%d L1 %s Error detected\n", + smp_processor_id(), err_name[ed->err]); + + kryo2xx_print_error_state_regs(); + if (ed->err == DBE) + edac_printk(KERN_CRIT, EDAC_CPU, "Fatal error\n"); + + cpuid = A53_CPUMERRSR_CPUID(cpumerrsr); + + switch (A53_CPUMERRSR_RAMID(cpumerrsr)) { + case 0x0: + edac_printk(KERN_CRIT, EDAC_CPU, + "L1 Instruction tag RAM way is %d\n", cpuid); + break; + case 0x1: + edac_printk(KERN_CRIT, EDAC_CPU, + "L1 Instruction data RAM bank is %d\n", cpuid); + break; + case 0x8: + edac_printk(KERN_CRIT, EDAC_CPU, + "L1 Data tag RAM cpu %d way is %d\n", + cpuid / 4, cpuid % 4); + break; + case 0x9: + edac_printk(KERN_CRIT, EDAC_CPU, + "L1 Data data RAM cpu %d way is %d\n", + cpuid / 4, cpuid % 4); + break; + case 0xA: + edac_printk(KERN_CRIT, EDAC_CPU, + "L1 Data dirty RAM cpu %d way is %d\n", + cpuid / 4, cpuid % 4); + break; + case 0x18: + edac_printk(KERN_CRIT, EDAC_CPU, "TLB RAM way is %d\n", cpuid); + break; + default: + edac_printk(KERN_CRIT, EDAC_CPU, + "Error in unknown RAM ID: %d\n", + (int) A53_CPUMERRSR_RAMID(cpumerrsr)); + break; + } + + edac_printk(KERN_CRIT, EDAC_CPU, "Repeated error count: %d\n", + (int) A53_CPUMERRSR_REPT(cpumerrsr)); + edac_printk(KERN_CRIT, EDAC_CPU, "Other error count: %d\n", + (int) A53_CPUMERRSR_OTHER(cpumerrsr)); + + if (ed->err == SBE) + errors[KRYO2XX_SILVER_L1_CE].func(ed->drv->edev_ctl, smp_processor_id(), + L1_CACHE, errors[KRYO2XX_SILVER_L1_CE].msg); + else if (ed->err == DBE) + errors[KRYO2XX_SILVER_L1_UE].func(ed->drv->edev_ctl, smp_processor_id(), + L1_CACHE, errors[KRYO2XX_SILVER_L1_UE].msg); + write_cpumerrsr_el1(0); +} + +static void kryo2xx_silver_parse_l2merrsr(struct erp_local_data *ed) +{ + u64 l2merrsr; + u32 l2ectlr; + int cpuid; + + l2merrsr = read_l2merrsr_el1; + l2ectlr = read_l2ectlr_el1; + + if (!A53_L2MERRSR_VALID(l2merrsr)) + return; + + if (A53_L2MERRSR_FATAL(l2merrsr)) + ed->err = DBE; + + edac_printk(KERN_CRIT, EDAC_CPU, "Kyro2xx Silver L2 %s Error detected\n", + err_name[ed->err]); + kryo2xx_print_error_state_regs(); + if (ed->err == DBE) + edac_printk(KERN_CRIT, EDAC_CPU, "Fatal error\n"); + + cpuid = A53_L2MERRSR_CPUID(l2merrsr); + + switch (A53_L2MERRSR_RAMID(l2merrsr)) { + case 0x10: + edac_printk(KERN_CRIT, EDAC_CPU, + "L2 tag RAM way is %d\n", cpuid); + break; + case 0x11: + edac_printk(KERN_CRIT, EDAC_CPU, + "L2 data RAM bank is %d\n", cpuid); + break; + case 0x12: + edac_printk(KERN_CRIT, EDAC_CPU, + "SCU snoop filter RAM cpu %d way is %d\n", + cpuid / 4, cpuid % 4); + break; + default: + edac_printk(KERN_CRIT, EDAC_CPU, + "Error in unknown RAM ID: %d\n", + (int) A53_L2MERRSR_RAMID(l2merrsr)); + break; + } + + edac_printk(KERN_CRIT, EDAC_CPU, "Repeated error count: %d\n", + (int) A53_L2MERRSR_REPT(l2merrsr)); + edac_printk(KERN_CRIT, EDAC_CPU, "Other error count: %d\n", + (int) A53_L2MERRSR_OTHER(l2merrsr)); + + if (ed->err == SBE) + errors[KRYO2XX_SILVER_L2_CE].func(ed->drv->edev_ctl, smp_processor_id(), + L2_CACHE, errors[KRYO2XX_SILVER_L2_CE].msg); + else if (ed->err == DBE) + errors[KRYO2XX_SILVER_L2_UE].func(ed->drv->edev_ctl, smp_processor_id(), + L2_CACHE, errors[KRYO2XX_SILVER_L2_UE].msg); + write_l2merrsr_el1(0); +} + + +static void ca57_parse_cpumerrsr(struct erp_local_data *ed) +{ + u64 cpumerrsr; + int bank; + + cpumerrsr = read_cpumerrsr_el1; + + if (!A57_CPUMERRSR_VALID(cpumerrsr)) + return; + + if (A57_CPUMERRSR_FATAL(cpumerrsr)) + ed->err = DBE; + + edac_printk(KERN_CRIT, EDAC_CPU, "Cortex A57 CPU%d L1 %s Error detected\n", + smp_processor_id(), err_name[ed->err]); + kryo2xx_print_error_state_regs(); + if (ed->err == DBE) + edac_printk(KERN_CRIT, EDAC_CPU, "Fatal error\n"); + + bank = A57_CPUMERRSR_BANK(cpumerrsr); + + switch (A57_CPUMERRSR_RAMID(cpumerrsr)) { + case 0x0: + edac_printk(KERN_CRIT, EDAC_CPU, + "L1 Instruction tag RAM bank %d\n", bank); + break; + case 0x1: + edac_printk(KERN_CRIT, EDAC_CPU, + "L1 Instruction data RAM bank %d\n", bank); + break; + case 0x8: + edac_printk(KERN_CRIT, EDAC_CPU, + "L1 Data tag RAM bank %d\n", bank); + break; + case 0x9: + edac_printk(KERN_CRIT, EDAC_CPU, + "L1 Data data RAM bank %d\n", bank); + break; + case 0x18: + edac_printk(KERN_CRIT, EDAC_CPU, + "TLB RAM bank %d\n", bank); + break; + default: + edac_printk(KERN_CRIT, EDAC_CPU, + "Error in unknown RAM ID: %d\n", + (int) A57_CPUMERRSR_RAMID(cpumerrsr)); + break; + } + + edac_printk(KERN_CRIT, EDAC_CPU, "Repeated error count: %d\n", + (int) A57_CPUMERRSR_REPT(cpumerrsr)); + edac_printk(KERN_CRIT, EDAC_CPU, "Other error count: %d\n", + (int) A57_CPUMERRSR_OTHER(cpumerrsr)); + + if (ed->err == SBE) + errors[A57_L1_CE].func(ed->drv->edev_ctl, smp_processor_id(), + L1_CACHE, errors[A57_L1_CE].msg); + else if (ed->err == DBE) + errors[A57_L1_UE].func(ed->drv->edev_ctl, smp_processor_id(), + L1_CACHE, errors[A57_L1_UE].msg); + write_cpumerrsr_el1(0); +} + +static void ca57_parse_l2merrsr(struct erp_local_data *ed) +{ + u64 l2merrsr; + u32 l2ectlr; + int cpuid; + + l2merrsr = read_l2merrsr_el1; + l2ectlr = read_l2ectlr_el1; + + if (!A57_L2MERRSR_VALID(l2merrsr)) + return; + + if (A57_L2MERRSR_FATAL(l2merrsr)) + ed->err = DBE; + + edac_printk(KERN_CRIT, EDAC_CPU, "CortexA57 L2 %s Error detected\n", + err_name[ed->err]); + kryo2xx_print_error_state_regs(); + if (ed->err == DBE) + edac_printk(KERN_CRIT, EDAC_CPU, "Fatal error\n"); + + cpuid = A57_L2MERRSR_CPUID(l2merrsr); + + switch (A57_L2MERRSR_RAMID(l2merrsr)) { + case 0x10: + edac_printk(KERN_CRIT, EDAC_CPU, + "L2 tag RAM cpu %d way is %d\n", + cpuid / 2, cpuid % 2); + break; + case 0x11: + edac_printk(KERN_CRIT, EDAC_CPU, + "L2 data RAM cpu %d bank is %d\n", + cpuid / 2, cpuid % 2); + break; + case 0x12: + edac_printk(KERN_CRIT, EDAC_CPU, + "SCU snoop tag RAM bank is %d\n", cpuid); + break; + case 0x14: + edac_printk(KERN_CRIT, EDAC_CPU, + "L2 dirty RAM cpu %d bank is %d\n", + cpuid / 2, cpuid % 2); + break; + case 0x18: + edac_printk(KERN_CRIT, EDAC_CPU, + "L2 inclusion PF RAM bank is %d\n", cpuid); + break; + default: + edac_printk(KERN_CRIT, EDAC_CPU, + "Error in unknown RAM ID: %d\n", + (int) A57_L2MERRSR_RAMID(l2merrsr)); + break; + } + + edac_printk(KERN_CRIT, EDAC_CPU, "Repeated error count: %d\n", + (int) A57_L2MERRSR_REPT(l2merrsr)); + edac_printk(KERN_CRIT, EDAC_CPU, "Other error count: %d\n", + (int) A57_L2MERRSR_OTHER(l2merrsr)); + + if (ed->err == SBE) { + errors[A57_L2_CE].func(ed->drv->edev_ctl, smp_processor_id(), + L2_CACHE, errors[A57_L2_CE].msg); + } else if (ed->err == DBE) { + errors[A57_L2_UE].func(ed->drv->edev_ctl, smp_processor_id(), + L2_CACHE, errors[A57_L2_UE].msg); + } + write_l2merrsr_el1(0); +} + + +static void kryo2xx_gold_parse_l2merrsr(struct erp_local_data *ed) +{ + u64 l2merrsr; + int ramid, way; + + l2merrsr = read_l2merrsr_el1; + + if (!KRYO2XX_GOLD_L2MERRSR_VALID(l2merrsr)) + return; + + if (KRYO2XX_GOLD_L2MERRSR_FATAL(l2merrsr)) + ed->err = DBE; + + edac_printk(KERN_CRIT, EDAC_CPU, "Kryo2xx Gold L2 %s Error detected\n", + err_name[ed->err]); + kryo2xx_gold_print_error_state_regs(); + if (ed->err == DBE) + edac_printk(KERN_CRIT, EDAC_CPU, "Fatal error\n"); + + way = KRYO2XX_GOLD_L2MERRSR_WAY(l2merrsr); + ramid = KRYO2XX_GOLD_L2MERRSR_RAMID(l2merrsr); + + edac_printk(KERN_CRIT, EDAC_CPU, + "L2 %s RAM error in way 0x%02x, index 0x%04x\n", + ramid ? "data" : "tag", + (int) KRYO2XX_GOLD_L2MERRSR_WAY(l2merrsr), + (int) KRYO2XX_GOLD_L2MERRSR_INDEX(l2merrsr)); + + edac_printk(KERN_CRIT, EDAC_CPU, "Repeated error count: %d\n", + (int) KRYO2XX_GOLD_L2MERRSR_REPT(l2merrsr)); + edac_printk(KERN_CRIT, EDAC_CPU, "Other error count: %d\n", + (int) KRYO2XX_GOLD_L2MERRSR_OTHER(l2merrsr)); + + if (ed->err == SBE) { + errors[KRYO2XX_GOLD_L2_CE].func(ed->drv->edev_ctl, smp_processor_id(), + L2_CACHE, errors[KRYO2XX_GOLD_L2_CE].msg); + } else if (ed->err == DBE) { + errors[KRYO2XX_GOLD_L2_UE].func(ed->drv->edev_ctl, smp_processor_id(), + L2_CACHE, errors[KRYO2XX_GOLD_L2_UE].msg); + } + write_l2merrsr_el1(0); +} + +static DEFINE_SPINLOCK(local_handler_lock); +static DEFINE_SPINLOCK(l2ectlr_lock); + +static void arm64_erp_local_handler(void *info) +{ + struct erp_local_data *errdata = info; + unsigned int cpuid = read_cpuid_id(); + unsigned int partnum = read_cpuid_part_number(); + unsigned long flags, flags2; + u32 l2ectlr; + + spin_lock_irqsave(&local_handler_lock, flags); + edac_printk(KERN_CRIT, EDAC_CPU, "%s error information from CPU %d, MIDR=%#08x:\n", + err_name[errdata->err], raw_smp_processor_id(), cpuid); + + switch (partnum) { + case ARM_CPU_PART_CORTEX_A53: + case ARM_CPU_PART_KRYO2XX_SILVER: + kryo2xx_silver_parse_cpumerrsr(errdata); + kryo2xx_silver_parse_l2merrsr(errdata); + break; + + case ARM_CPU_PART_CORTEX_A72: + case ARM_CPU_PART_CORTEX_A57: + ca57_parse_cpumerrsr(errdata); + ca57_parse_l2merrsr(errdata); + break; + + case ARM_CPU_PART_KRYO2XX_GOLD: + kryo2xx_gold_parse_l2merrsr(errdata); + break; + + default: + edac_printk(KERN_CRIT, EDAC_CPU, "Unknown CPU Part Number in MIDR: %#04x (%#08x)\n", + partnum, cpuid); + }; + + /* Acklowledge internal error in L2ECTLR */ + spin_lock_irqsave(&l2ectlr_lock, flags2); + + l2ectlr = read_l2ectlr_el1; + + if (l2ectlr & L2ECTLR_INT_ERR) { + l2ectlr &= ~L2ECTLR_INT_ERR; + write_l2ectlr_el1(l2ectlr); + } + + spin_unlock_irqrestore(&l2ectlr_lock, flags2); + spin_unlock_irqrestore(&local_handler_lock, flags); +} + +static irqreturn_t arm64_dbe_handler(int irq, void *drvdata) +{ + struct erp_local_data errdata; + + errdata.drv = drvdata; + errdata.err = DBE; + edac_printk(KERN_CRIT, EDAC_CPU, "ARM64 CPU ERP: Double-bit error interrupt received!\n"); + + on_each_cpu(arm64_erp_local_handler, &errdata, 1); + + return IRQ_HANDLED; +} + +static void arm64_ext_local_handler(void *info) +{ + struct erp_drvdata *drv = info; + unsigned long flags, flags2; + u32 l2ectlr; + + spin_lock_irqsave(&local_handler_lock, flags); + + /* TODO: Shared locking for L2ECTLR access */ + spin_lock_irqsave(&l2ectlr_lock, flags2); + + l2ectlr = read_l2ectlr_el1; + + if (l2ectlr & L2ECTLR_EXT_ERR) { + edac_printk(KERN_CRIT, EDAC_CPU, + "L2 external error detected by CPU%d\n", + smp_processor_id()); + + errors[L2_EXT_UE].func(drv->edev_ctl, smp_processor_id(), + L2_CACHE, errors[L2_EXT_UE].msg); + + l2ectlr &= ~L2ECTLR_EXT_ERR; + write_l2ectlr_el1(l2ectlr); + } + + spin_unlock_irqrestore(&l2ectlr_lock, flags2); + spin_unlock_irqrestore(&local_handler_lock, flags); +} + +static irqreturn_t arm64_ext_handler(int irq, void *drvdata) +{ + edac_printk(KERN_CRIT, EDAC_CPU, "External error interrupt received!\n"); + + on_each_cpu(arm64_ext_local_handler, drvdata, 1); + + return IRQ_HANDLED; +} + +static irqreturn_t arm64_cci_handler(int irq, void *drvdata) +{ + struct erp_drvdata *drv = drvdata; + u32 cci_err_reg; + + edac_printk(KERN_CRIT, EDAC_CPU, "CCI error interrupt received!\n"); + + if (drv->cci_base) { + cci_err_reg = readl_relaxed(drv->cci_base + + CCI_IMPRECISEERROR_REG); + + edac_printk(KERN_CRIT, EDAC_CPU, "CCI imprecise error register: %#08x.\n", + cci_err_reg); + + /* This register has write-clear semantics */ + writel_relaxed(cci_err_reg, drv->cci_base + + CCI_IMPRECISEERROR_REG); + + /* Ensure error bits cleared before exiting ISR */ + mb(); + } else { + edac_printk(KERN_CRIT, EDAC_CPU, "CCI registers not available.\n"); + } + + errors[CCI_UE].func(drv->edev_ctl, 0, CCI, errors[CCI_UE].msg); + + return IRQ_HANDLED; +} +#ifndef CONFIG_EDAC_CORTEX_ARM64_DBE_IRQ_ONLY +static void arm64_sbe_handler(struct perf_event *event, + struct perf_sample_data *data, + struct pt_regs *regs) +{ + struct erp_local_data errdata; + int cpu = raw_smp_processor_id(); + + errdata.drv = event->overflow_handler_context; + errdata.err = SBE; + edac_printk(KERN_CRIT, EDAC_CPU, "ARM64 CPU ERP: Single-bit error interrupt received on CPU %d!\n", + cpu); + arm64_erp_local_handler(&errdata); +} +#endif + +static int request_erp_irq(struct platform_device *pdev, const char *propname, + const char *desc, irq_handler_t handler, + void *ed) +{ + int rc; + struct resource *r; + + r = platform_get_resource_byname(pdev, IORESOURCE_IRQ, propname); + + if (!r) { + pr_err("ARM64 CPU ERP: Could not find <%s> IRQ property. Proceeding anyway.\n", + propname); + return -EINVAL; + } + + rc = devm_request_threaded_irq(&pdev->dev, r->start, NULL, + handler, + IRQF_ONESHOT | IRQF_TRIGGER_RISING, + desc, + ed); + + if (rc) { + pr_err("ARM64 CPU ERP: Failed to request IRQ %d: %d (%s / %s). Proceeding anyway.\n", + (int) r->start, rc, propname, desc); + return -EINVAL; + } + + return 0; +} + +static void check_sbe_event(struct erp_drvdata *drv) +{ + unsigned int partnum = read_cpuid_part_number(); + struct erp_local_data errdata; + unsigned long flags; + + errdata.drv = drv; + errdata.err = SBE; + + spin_lock_irqsave(&local_handler_lock, flags); + switch (partnum) { + case ARM_CPU_PART_CORTEX_A53: + case ARM_CPU_PART_KRYO2XX_SILVER: + kryo2xx_silver_parse_cpumerrsr(&errdata); + kryo2xx_silver_parse_l2merrsr(&errdata); + break; + + case ARM_CPU_PART_CORTEX_A72: + case ARM_CPU_PART_CORTEX_A57: + ca57_parse_cpumerrsr(&errdata); + ca57_parse_l2merrsr(&errdata); + break; + + case ARM_CPU_PART_KRYO2XX_GOLD: + kryo2xx_gold_parse_l2merrsr(&errdata); + break; + }; + spin_unlock_irqrestore(&local_handler_lock, flags); +} + +#ifdef CONFIG_EDAC_CORTEX_ARM64_DBE_IRQ_ONLY +static void create_sbe_counter(int cpu, void *info) +{ } +#else +static void create_sbe_counter(int cpu, void *info) +{ + struct erp_drvdata *drv = info; + struct perf_event *event = drv->memerr_counters[cpu]; + struct perf_event_attr attr = { + .pinned = 1, + .disabled = 0, /* 0 will enable the counter upon creation */ + .sample_period = 1, /* 1 will set the counter to max int */ + .type = PERF_TYPE_RAW, + .config = MEM_ERROR_EVENT, + .size = sizeof(struct perf_event_attr), + }; + + if (event) + return; + + /* Fails if cpu is not online */ + event = perf_event_create_kernel_counter(&attr, cpu, NULL, + arm64_sbe_handler, + drv); + if (IS_ERR(event)) { + pr_err("PERF Event creation failed on cpu %d ptr_err %ld\n", + cpu, PTR_ERR(event)); + return; + } + drv->memerr_counters[cpu] = event; +} +#endif + +static int arm64_pmu_cpu_pm_notify(struct notifier_block *self, + unsigned long action, void *v) +{ + struct erp_drvdata *drv = container_of(self, struct erp_drvdata, nb_pm); + + switch (action) { + case CPU_PM_EXIT: + check_sbe_event(drv); + break; + } + + return NOTIFY_OK; +} + +static int arm64_edac_pmu_cpu_notify(struct notifier_block *self, + unsigned long action, void *hcpu) +{ + struct erp_drvdata *drv = container_of(self, struct erp_drvdata, + nb_cpu); + unsigned long cpu = (unsigned long)hcpu; + + switch (action & ~CPU_TASKS_FROZEN) { + case CPU_ONLINE: + create_sbe_counter(cpu, drv); + break; + }; + + return NOTIFY_OK; +} + +#ifndef CONFIG_EDAC_CORTEX_ARM64_DBE_IRQ_ONLY +void arm64_check_cache_ecc(void *info) +{ + if (panic_handler_drvdata) + check_sbe_event(panic_handler_drvdata); +} +#else +static inline void arm64_check_cache_ecc(void *info) {} +#endif + +static int arm64_erp_panic_notify(struct notifier_block *this, + unsigned long event, void *ptr) +{ + arm64_check_cache_ecc(NULL); + + return NOTIFY_OK; +} + +static void arm64_monitor_cache_errors(struct edac_device_ctl_info *edev) +{ + struct cpumask cluster_mask, old_mask; + int cpu; + + cpumask_clear(&cluster_mask); + cpumask_clear(&old_mask); + + for_each_possible_cpu(cpu) { + cpumask_copy(&cluster_mask, topology_core_cpumask(cpu)); + if (cpumask_equal(&cluster_mask, &old_mask)) + continue; + cpumask_copy(&old_mask, &cluster_mask); + smp_call_function_any(&cluster_mask, + arm64_check_cache_ecc, NULL, 0); + } +} + +static int arm64_cpu_erp_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct erp_drvdata *drv; + struct resource *r; + int cpu; + u32 poll_msec; + + int rc, fail = 0; + + drv = devm_kzalloc(dev, sizeof(*drv), GFP_KERNEL); + + if (!drv) + return -ENOMEM; + + drv->edev_ctl = edac_device_alloc_ctl_info(0, "cpu", + num_possible_cpus(), "L", 3, 1, NULL, 0, + edac_device_alloc_index()); + + if (!drv->edev_ctl) + return -ENOMEM; + + rc = of_property_read_u32(pdev->dev.of_node, "poll-delay-ms", + &poll_msec); + if (!rc && !IS_ENABLED(CONFIG_EDAC_CORTEX_ARM64_DBE_IRQ_ONLY)) { + drv->edev_ctl->edac_check = arm64_monitor_cache_errors; + drv->edev_ctl->poll_msec = poll_msec; + drv->edev_ctl->defer_work = 1; + } + drv->edev_ctl->dev = dev; + drv->edev_ctl->mod_name = dev_name(dev); + drv->edev_ctl->dev_name = dev_name(dev); + drv->edev_ctl->ctl_name = "cache"; + drv->edev_ctl->panic_on_ce = panic_on_ce; + drv->edev_ctl->panic_on_ue = ARM64_ERP_PANIC_ON_UE; + + rc = edac_device_add_device(drv->edev_ctl); + if (rc) + goto out_mem; + + r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cci"); + if (r) + drv->cci_base = devm_ioremap_resource(dev, r); + + if (request_erp_irq(pdev, "pri-dbe-irq", "ARM64 primary DBE IRQ", + arm64_dbe_handler, drv)) + fail++; + + if (request_erp_irq(pdev, "sec-dbe-irq", "ARM64 secondary DBE IRQ", + arm64_dbe_handler, drv)) + fail++; + + if (request_erp_irq(pdev, "pri-ext-irq", "ARM64 primary ext IRQ", + arm64_ext_handler, drv)) + fail++; + + if (request_erp_irq(pdev, "sec-ext-irq", "ARM64 secondary ext IRQ", + arm64_ext_handler, drv)) + fail++; + + /* + * We still try to register a handler for CCI errors even if we don't + * have access to cci_base, but error reporting becomes best-effort in + * that case. + */ + if (request_erp_irq(pdev, "cci-irq", "CCI error IRQ", + arm64_cci_handler, drv)) + fail++; + + if (IS_ENABLED(CONFIG_EDAC_CORTEX_ARM64_DBE_IRQ_ONLY)) { + pr_err("ARM64 CPU ERP: SBE detection is disabled.\n"); + goto out_irq; + } + + drv->nb_pm.notifier_call = arm64_pmu_cpu_pm_notify; + cpu_pm_register_notifier(&(drv->nb_pm)); + drv->nb_panic.notifier_call = arm64_erp_panic_notify; + atomic_notifier_chain_register(&panic_notifier_list, + &drv->nb_panic); + drv->nb_cpu.notifier_call = arm64_edac_pmu_cpu_notify; + register_cpu_notifier(&drv->nb_cpu); + get_online_cpus(); + for_each_online_cpu(cpu) + create_sbe_counter(cpu, drv); + put_online_cpus(); + +out_irq: + if (fail == of_irq_count(dev->of_node)) { + pr_err("ARM64 CPU ERP: Could not request any IRQs. Giving up.\n"); + rc = -ENODEV; + goto out_dev; + } + + panic_handler_drvdata = drv; + + return 0; + +out_dev: + edac_device_del_device(dev); +out_mem: + edac_device_free_ctl_info(drv->edev_ctl); + return rc; +} + +static const struct of_device_id arm64_cpu_erp_match_table[] = { + { .compatible = "arm,arm64-cpu-erp" }, + { } +}; + +static struct platform_driver arm64_cpu_erp_driver = { + .probe = arm64_cpu_erp_probe, + .driver = { + .name = "arm64_cpu_cache_erp", + .owner = THIS_MODULE, + .of_match_table = of_match_ptr(arm64_cpu_erp_match_table), + }, +}; + +static int __init arm64_cpu_erp_init(void) +{ + return platform_driver_register(&arm64_cpu_erp_driver); +} +device_initcall_sync(arm64_cpu_erp_init); diff -Nruw linux-4.4.115-fbx/drivers/esoc./Kconfig linux-4.4.115-fbx/drivers/esoc/Kconfig --- linux-4.4.115-fbx/drivers/esoc./Kconfig 1970-01-01 01:00:00.000000000 +0100 +++ linux-4.4.115-fbx/drivers/esoc/Kconfig 2019-01-22 16:16:23.179243472 +0100 @@ -0,0 +1,69 @@ +# +# External soc control infrastructure and drivers +# +menuconfig ESOC + bool "External SOCs Control" + help + External SOCs can be powered on and monitored by user + space or kernel drivers. Additionally they can be controlled + to respond to control commands. This framework provides an + interface to track events related to the external slave socs. + +if ESOC + +config ESOC_DEV + bool "ESOC userspace interface" + help + Say yes here to enable a userspace representation of the control + link. Userspace can register a request engine or a command engine + for the external soc. It can receive event notifications from the + control link. + +config ESOC_CLIENT + bool "ESOC client interface" + depends on OF + help + Say yes here to enable client interface for external socs. + Clients can specify the external soc that they are interested in + by using device tree phandles. Based on this, clients can register + for notifications from a specific soc. + +config ESOC_DEBUG + bool "ESOC debug support" + help + Say yes here to enable debugging support in the ESOC framework + and individual esoc drivers. + +config ESOC_MDM_4x + bool "Add support for external mdm9x25/mdm9x35/mdm9x45/mdm9x55" + help + In some qualcomm boards, an external modem such as mdm9x25 or mdm9x35 + is connected to a primary msm. The primary soc can control/monitor + the modem via gpios. The data communication with such modems can + occur over PCIE or HSIC. + +config ESOC_MDM_DRV + tristate "Command engine for 4x series external modems" + help + Provides a command engine to control the behavior of an external modem + such as mdm9x25/mdm9x35/mdm9x45/mdm9x55/QSC. Allows the primary soc to put the + external modem in a specific mode. Also listens for events on the + external modem. + +config ESOC_MDM_DBG_ENG + tristate "debug engine for 4x series external modems" + depends on ESOC_MDM_DRV + help + Provides a user interface to mask out certain commands sent + by command engine to the external modem. Also allows masking + of certain notifications being sent to the external modem. + +config MDM_DBG_REQ_ENG + tristate "manual request engine for 4x series external modems" + depends on ESOC_MDM_DBG_ENG + help + Provides a user interface to handle incoming requests from + the external modem. Allows for debugging of IPC mechanism + between the external modem and the primary soc. + +endif diff -Nruw linux-4.4.115-fbx/drivers/esoc./Makefile linux-4.4.115-fbx/drivers/esoc/Makefile --- linux-4.4.115-fbx/drivers/esoc./Makefile 1970-01-01 01:00:00.000000000 +0100 +++ linux-4.4.115-fbx/drivers/esoc/Makefile 2019-01-22 16:16:23.179243472 +0100 @@ -0,0 +1,9 @@ +# generic external soc control support + +ccflags-$(CONFIG_ESOC_DEBUG) := -DDEBUG +obj-$(CONFIG_ESOC) += esoc_bus.o +obj-$(CONFIG_ESOC_DEV) += esoc_dev.o +obj-$(CONFIG_ESOC_CLIENT) += esoc_client.o +obj-$(CONFIG_ESOC_MDM_4x) += esoc-mdm-pon.o esoc-mdm-4x.o +obj-$(CONFIG_ESOC_MDM_DRV) += esoc-mdm-drv.o +obj-$(CONFIG_ESOC_MDM_DBG_ENG) += esoc-mdm-dbg-eng.o diff -Nruw linux-4.4.115-fbx/drivers/fbxgpio./fbxgpio_core.c linux-4.4.115-fbx/drivers/fbxgpio/fbxgpio_core.c --- linux-4.4.115-fbx/drivers/fbxgpio./fbxgpio_core.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-4.4.115-fbx/drivers/fbxgpio/fbxgpio_core.c 2019-01-22 16:16:23.183243509 +0100 @@ -0,0 +1,360 @@ +#include +#include +#include +#include +#include +#include +#include +#include + +#define PFX "fbxgpio_core: " + +/* #define DEBUG */ +#ifdef DEBUG +#define dprint(Fmt, Arg...) printk(PFX Fmt, Arg) +#else +#define dprint(Fmt, Arg...) do { } while (0) +#endif + +static struct class *fbxgpio_class; + +/* + * retrieval of a struct fbxgpio_pin from a phandle in the device + * tree. + */ +struct fbxgpio_of_mach_data { + struct fbxgpio_pin *match; + struct device_node *np; +}; + +static int match_fbxgpio_of_node(struct device *dev, void *data) +{ + struct fbxgpio_of_mach_data *md = data; + struct fbxgpio_pin *pin = dev_get_drvdata(dev); + + if (pin->of_node == md->np) { + md->match = pin; + return 1; + } + return 0; +} + +struct fbxgpio_pin *fbxgpio_of_get(struct device_node *np, const char *propname, + int index) +{ + struct fbxgpio_of_mach_data md; + + /* + * get the pin device_node. + */ + md.match = NULL; + md.np = of_parse_phandle(np, propname, index); + if (!md.np) + return ERR_PTR(-ENOENT); + + /* + * find the struct fbxgpio_pin behind that device_node. + */ + class_for_each_device(fbxgpio_class, NULL, &md, + match_fbxgpio_of_node); + + return md.match ? md.match : ERR_PTR(-ENOENT); +} +EXPORT_SYMBOL(fbxgpio_of_get); + +/* + * show direction in for gpio associated with class_device dev. + */ +static ssize_t show_direction(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct fbxgpio_pin *p; + int dir, ret = 0; + + p = dev_get_drvdata(dev); + + if (p->ops->get_direction) + dir = p->ops->get_direction(p->pin_num); + else + dir = p->direction; + + switch (dir) { + case GPIO_DIR_IN: + ret += sprintf(buf, "input\n"); + break; + case GPIO_DIR_OUT: + ret += sprintf(buf, "output\n"); + break; + default: + ret += sprintf(buf, "unknown\n"); + break; + } + return ret; +} + +/* + * store direction. return -EINVAL if direction string is bad. return + * -EPERM if flag FBXGPIO_PIN_DIR_RW is set in flags. + */ +static ssize_t store_direction(struct device *dev, + struct device_attribute *attr, const char *buf, size_t size) +{ + int dir; + struct fbxgpio_pin *p; + int match_len = 0; + int i, ret; + static const char *word_match[] = { + [GPIO_DIR_IN] = "input", + [GPIO_DIR_OUT] = "output", + }; + + if (*buf == ' ' || *buf == '\t' || *buf == '\r' || *buf == '\n') + /* silently eat any spaces/tab/linefeed/carriagereturn */ + return 1; + + p = dev_get_drvdata(dev); + if (!(p->flags & FBXGPIO_PIN_DIR_RW)) { + dprint("pin %s direction is read only.\n", p->pin_name); + return -EPERM; + } + dir = 0; + for (i = 0; i < 2; ++i) { + if (size >= strlen(word_match[i]) && + !strncmp(buf, word_match[i], strlen(word_match[i]))) { + dir = i; + match_len = strlen(word_match[i]); + break ; + } + } + if (i == 2) + return -EINVAL; + + ret = p->ops->set_direction(p->pin_num, dir); + if (ret) + return ret; + + return match_len; +} + +/* + * show input data for input gpio pins. + */ +static ssize_t show_datain(struct device *dev, + struct device_attribute *attr, char *buf) +{ + int val; + struct fbxgpio_pin *p; + + p = dev_get_drvdata(dev); + if (p->direction == GPIO_DIR_OUT) + return -EINVAL; + val = p->ops->get_datain(p->pin_num); + + if (p->flags & FBXGPIO_PIN_REVERSE_POL) + val = 1 - val; + return sprintf(buf, "%i\n", val); +} + +/* + * show output data for output gpio pins. + */ +static ssize_t show_dataout(struct device *dev, + struct device_attribute *attr, char *buf) +{ + int val; + struct fbxgpio_pin *p; + + p = dev_get_drvdata(dev); + if (p->direction == GPIO_DIR_IN) + return -EINVAL; + if (p->ops->get_dataout) + val = p->ops->get_dataout(p->pin_num); + else + val = p->cur_dataout; + + if (p->flags & FBXGPIO_PIN_REVERSE_POL) + val = 1 - val; + return sprintf(buf, "%i\n", val); +} + +/* + * store new dataout value for output gpio pins. + */ +static ssize_t store_dataout(struct device *dev, + struct device_attribute *attr, const char *buf, size_t size) +{ + int val; + struct fbxgpio_pin *p; + + if (*buf == ' ' || *buf == '\t' || *buf == '\r' || *buf == '\n') + /* silently eat any spaces/tab/linefeed/carriagereturn */ + return 1; + + p = dev_get_drvdata(dev); + + if (p->direction != GPIO_DIR_OUT) + return -EINVAL; + + switch (*buf) { + case '0': + val = 0; + break ; + case '1': + val = 1; + break ; + default: + return -EINVAL; + } + + p->cur_dataout = val; + + if (p->flags & FBXGPIO_PIN_REVERSE_POL) + val = 1 - val; + p->ops->set_dataout(p->pin_num, val); + return 1; +} + +/* + * show pin number associated with gpio pin. + */ +static ssize_t show_pinnum(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct fbxgpio_pin *p; + + p = dev_get_drvdata(dev); + return sprintf(buf, "%i\n", p->pin_num); +} + +/* + * attribute list associated with each class device. + */ +static struct device_attribute gpio_attributes[] = { + __ATTR(direction, 0600, show_direction, store_direction), + __ATTR(data_in, 0400, show_datain, NULL), + __ATTR(data_out, 0600, show_dataout, store_dataout), + __ATTR(pin_num, 0400, show_pinnum, NULL), +}; + +static int fbxgpio_register_pin(struct platform_device *ppdev, + struct fbxgpio_pin *pin) +{ + struct device *dev; + int i, ret; + + dprint("registering pin %s\n", pin->pin_name); + + /* ensure ops is valid */ + if (!pin->ops) { + printk(KERN_ERR PFX "no operation set for pin %s\n", + pin->pin_name); + return -EINVAL; + } + + dev = device_create(fbxgpio_class, &ppdev->dev, 0, pin, + "%s", pin->pin_name); + if (IS_ERR(dev)) + return PTR_ERR(dev); + + for (i = 0; i < ARRAY_SIZE(gpio_attributes); i++) { + ret = device_create_file(dev, &gpio_attributes[i]); + if (ret) + goto err_out; + } + + /* ensure pin direction matches hardware state */ + if (pin->ops->get_direction && + pin->direction != pin->ops->get_direction(pin->pin_num)) { + printk(KERN_WARNING PFX "pin %s default direction does not " + "match current hardware state, fixing.\n", + pin->pin_name); + pin->ops->set_direction(pin->pin_num, pin->direction); + } + pin->dev = dev; + return 0; + +err_out: + for (; i >= 0; i--) + device_remove_file(dev, &gpio_attributes[i]); + device_unregister(dev); + return ret; +} + +static void fbxgpio_unregister_pin(struct fbxgpio_pin *pin) +{ + struct device *dev; + int i; + + dprint("unregistering pin %s\n", pin->pin_name); + dev = pin->dev; + pin->dev = NULL; + + for (i = 0; i < ARRAY_SIZE(gpio_attributes); i++) + device_remove_file(dev, &gpio_attributes[i]); + device_unregister(dev); +} + +static int fbxgpio_platform_probe(struct platform_device *pdev) +{ + struct fbxgpio_pin *p; + int err = 0; + + p = pdev->dev.platform_data; + while (p->pin_name) { + err = fbxgpio_register_pin(pdev, p); + if (err) + return err; + ++p; + } + return 0; +} + +static int fbxgpio_platform_remove(struct platform_device *pdev) +{ + struct fbxgpio_pin *p; + + p = pdev->dev.platform_data; + while (p->pin_name) { + fbxgpio_unregister_pin(p); + ++p; + } + return 0; +} + +static struct platform_driver fbxgpio_platform_driver = +{ + .probe = fbxgpio_platform_probe, + .remove = fbxgpio_platform_remove, + .driver = { + .name = "fbxgpio", + } +}; + +static int __init fbxgpio_init(void) +{ + int ret; + + fbxgpio_class = class_create(THIS_MODULE, "fbxgpio"); + if (IS_ERR(fbxgpio_class)) + return PTR_ERR(fbxgpio_class); + + ret = platform_driver_register(&fbxgpio_platform_driver); + if (ret) { + printk(KERN_ERR PFX "unable to register fbxgpio driver.\n"); + class_destroy(fbxgpio_class); + return ret; + } + return 0; +} + +static void __exit fbxgpio_exit(void) +{ + platform_driver_unregister(&fbxgpio_platform_driver); + class_destroy(fbxgpio_class); +} + +subsys_initcall(fbxgpio_init); +module_exit(fbxgpio_exit); + +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Nicolas Schichan "); diff -Nruw linux-4.4.115-fbx/drivers/fbxgpio./fbxgpio_dt.c linux-4.4.115-fbx/drivers/fbxgpio/fbxgpio_dt.c --- linux-4.4.115-fbx/drivers/fbxgpio./fbxgpio_dt.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-4.4.115-fbx/drivers/fbxgpio/fbxgpio_dt.c 2019-01-22 16:16:23.183243509 +0100 @@ -0,0 +1,254 @@ +/* + * fbxgpio_dt.c for fbxgpio + * Created by on Tue Aug 1 14:01:01 2017 + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static atomic_t last_id = ATOMIC_INIT(0); + +/* + * fbxgpio driver fetching gpios names and configuration from + * device-tree. + */ + +struct fbxgpio_dt_priv { + struct fbxgpio_pin *pins; + unsigned int npins; + + /* dynamically created platform_device for fbxgpio_core */ + struct platform_device *top_pdev; +}; + + +/* + * small shim layer for gpiolib <-> fbxgpio_operations. + * + * gpio direction change is unsupported, does userspace really need + * it? + */ +static int fbxgpio_dt_get_data(int gpio) +{ + return gpio_get_value_cansleep(gpio); +} + +static void fbxgpio_dt_set_dataout(int gpio, int value) +{ + gpio_set_value_cansleep(gpio, value); +} + +static int fbxgpio_dt_set_direction(int gpio, int dir) +{ + if (dir == GPIO_DIR_OUT) + return gpio_direction_output(gpio, 0); + else + return gpio_direction_input(gpio); +} + +static const struct fbxgpio_operations fbxgpio_dt_ops = { + .get_datain = fbxgpio_dt_get_data, + .get_dataout = fbxgpio_dt_get_data, + .set_dataout = fbxgpio_dt_set_dataout, + .set_direction = fbxgpio_dt_set_direction, +}; + +/* + * fill an fbxgpio_pin with the configuration found in a device tree + * node. + * + * required properties are: + * - gpio: a phandle to a standard linux gpio. + * + * - the name of the node: the name of the gpio as it will appear under + * /sys/class/fbxgpio/ + * + * - //: how to declare gpio and + * actually setup it unless no-claim is given + * + * - : just declare gpio, but don't request & setup it + */ +static int fbxgpio_dt_fill_gpio(struct platform_device *pdev, + struct device_node *np, + struct fbxgpio_pin *pin) +{ + int error; + + error = of_property_read_string(np, "name", &pin->pin_name); + if (error) { + dev_err(&pdev->dev, "gpio has no name.\n"); + return error; + } + + pin->pin_num = of_get_named_gpio(np, "gpio", 0); + if (pin->pin_num < 0) { + if (pin->pin_num != -EPROBE_DEFER) + dev_err(&pdev->dev, + "unable to get gpio desc for %s: %d.\n", + pin->pin_name, pin->pin_num); + return pin->pin_num; + } + + if (of_property_read_bool(np, "input")) { + pin->direction = GPIO_DIR_IN; + } else if (of_property_read_bool(np, "output-low")) { + pin->direction = GPIO_DIR_OUT; + pin->cur_dataout = 0; + } else if (of_property_read_bool(np, "output-high")) { + pin->direction = GPIO_DIR_OUT; + pin->cur_dataout = 1; + } else { + dev_err(&pdev->dev, + "no state specified for %s\n", + pin->pin_name); + return -EINVAL; + } + + if (!of_property_read_bool(np, "no-claim")) { + error = gpio_request(pin->pin_num, "fbxgpio-dt"); + if (error) { + dev_err(&pdev->dev, "unable to request gpio%d (%s): %d\n", + pin->pin_num, pin->pin_name, error); + return error; + } + pin->claimed = true; + + if (pin->direction == GPIO_DIR_OUT) + gpio_direction_output(pin->pin_num, pin->cur_dataout); + else + gpio_direction_input(pin->pin_num); + } + + pin->of_node = np; + pin->ops = &fbxgpio_dt_ops; + return 0; +} + +static int fbxgpio_dt_probe(struct platform_device *pdev) +{ + struct fbxgpio_dt_priv *priv; + struct device_node *fbxgpio_node; + u32 cur_gpio; + int error = 0; + size_t priv_alloc_size; + int i; + + priv = devm_kzalloc(&pdev->dev, sizeof (*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + dev_set_drvdata(&pdev->dev, priv); + + /* + * first pass to get the number of struct fbxgpio_pin to + * allocate. + */ + for_each_available_child_of_node(pdev->dev.of_node, fbxgpio_node) { + ++priv->npins; + } + + /* + * allocate pins: use npins + 1 for zeroed end sentinel. + */ + priv_alloc_size = (priv->npins + 1) * sizeof (struct fbxgpio_pin); + priv->pins = devm_kzalloc(&pdev->dev, priv_alloc_size, GFP_KERNEL); + if (!priv->pins) + return -ENOMEM; + + /* + * second pass to fill the priv->pins array. + */ + cur_gpio = 0; + for_each_available_child_of_node(pdev->dev.of_node, fbxgpio_node) { + error = fbxgpio_dt_fill_gpio(pdev, fbxgpio_node, + &priv->pins[cur_gpio]); + if (error) + goto out_free_gpios; + ++cur_gpio; + } + + dev_info(&pdev->dev, "%u gpios.\n", priv->npins); + + /* + * create and register a platform device for fbxgpio_core. + */ + priv->top_pdev = platform_device_register_data(&pdev->dev, + "fbxgpio", + atomic_inc_return(&last_id), + priv->pins, + priv_alloc_size); + + if (IS_ERR(priv->top_pdev)) { + dev_err(&pdev->dev, "unable to register fbxgpio platform " + "device: %ld\n", PTR_ERR(priv->top_pdev)); + return PTR_ERR(priv->top_pdev); + } + + for (i = 0; i < priv->npins; i++) { + struct fbxgpio_pin *pin = &priv->pins[i]; + + if (pin->direction == GPIO_DIR_OUT) + dev_dbg(&pdev->dev, + "%sgpio %d (%s) is output, default %d\n", + pin->claimed ? "unclaimed " : "", + pin->pin_num, pin->pin_name, pin->cur_dataout); + else + dev_dbg(&pdev->dev, + "%sgpio %d (%s) is input\n", + pin->claimed ? "unclaimed " : "", + pin->pin_num, pin->pin_name); + } + + return 0; + +out_free_gpios: + while (cur_gpio) { + --cur_gpio; + if (priv->pins[cur_gpio].claimed) + gpio_free(priv->pins[cur_gpio].pin_num); + } + return error; +} + +static int fbxgpio_dt_remove(struct platform_device *pdev) +{ + struct fbxgpio_dt_priv *priv = dev_get_drvdata(&pdev->dev); + unsigned int i; + + platform_device_unregister(priv->top_pdev); + + for (i = 0; i < priv->npins; ++i) { + if (priv->pins[i].claimed) + gpio_free(priv->pins[i].pin_num); + } + + return 0; +} + +static const struct of_device_id fbxgpio_dt_of_match_table[] = { + { .compatible = "fbx,fbxgpio" }, + { }, +}; +MODULE_DEVICE_TABLE(of, fbxgpio_dt_of_match_table); + +static struct platform_driver fbxgpio_dt_platform_driver = { + .probe = fbxgpio_dt_probe, + .remove = fbxgpio_dt_remove, + .driver = { + .name = "fbxgpio-dt", + .of_match_table = fbxgpio_dt_of_match_table, + }, +}; + +module_platform_driver(fbxgpio_dt_platform_driver); + +MODULE_AUTHOR("Nicolas Schichan "); +MODULE_DESCRIPTION("DT Freebox GPIO Driver"); +MODULE_LICENSE("GPL v2"); diff -Nruw linux-4.4.115-fbx/drivers/fbxgpio./Kconfig linux-4.4.115-fbx/drivers/fbxgpio/Kconfig --- linux-4.4.115-fbx/drivers/fbxgpio./Kconfig 1970-01-01 01:00:00.000000000 +0100 +++ linux-4.4.115-fbx/drivers/fbxgpio/Kconfig 2019-01-22 16:16:23.183243509 +0100 @@ -0,0 +1,7 @@ +config FREEBOX_GPIO + tristate "Freebox GPIO control interface" + default n + +config FREEBOX_GPIO_DT + tristate "Freebox GPIO DT binding." + default n diff -Nruw linux-4.4.115-fbx/drivers/fbxgpio./Makefile linux-4.4.115-fbx/drivers/fbxgpio/Makefile --- linux-4.4.115-fbx/drivers/fbxgpio./Makefile 1970-01-01 01:00:00.000000000 +0100 +++ linux-4.4.115-fbx/drivers/fbxgpio/Makefile 2019-01-22 16:16:23.183243509 +0100 @@ -0,0 +1,2 @@ +obj-$(CONFIG_FREEBOX_GPIO) += fbxgpio_core.o +obj-$(CONFIG_FREEBOX_GPIO_DT) += fbxgpio_dt.o diff -Nruw linux-4.4.115-fbx/drivers/fbxprocfs./fbxprocfs.c linux-4.4.115-fbx/drivers/fbxprocfs/fbxprocfs.c --- linux-4.4.115-fbx/drivers/fbxprocfs./fbxprocfs.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-4.4.115-fbx/drivers/fbxprocfs/fbxprocfs.c 2019-01-22 16:16:23.183243509 +0100 @@ -0,0 +1,299 @@ +/* + * Freebox ProcFs interface + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#define PFX "fbxprocfs: " + + +static struct list_head clients; +static struct mutex clients_mutex; + +static struct proc_dir_entry *root; + +/* + * register a fbxprocfs client with given dirname, caller should + * consider returned struct opaque + */ +struct fbxprocfs_client *fbxprocfs_add_client(const char *dirname, + struct module *owner) +{ + struct fbxprocfs_client *ret, *p; + + ret = NULL; + mutex_lock(&clients_mutex); + + /* check for duplicate */ + list_for_each_entry(p, &clients, list) { + if (!strcmp(dirname, p->dirname)) + goto out; + } + + if (!(ret = kmalloc(sizeof (*ret), GFP_KERNEL))) { + printk(KERN_ERR PFX "kmalloc failed\n"); + goto out; + } + + /* try to create client directory */ + if (!(ret->dir = proc_mkdir(dirname, root))) { + printk(KERN_ERR PFX "can't create %s dir\n", dirname); + kfree(ret); + ret = NULL; + goto out; + } + + atomic_set(&ret->refcount, 1); + ret->dirname = dirname; + list_add(&ret->list, &clients); + +out: + mutex_unlock(&clients_mutex); + return ret; +} + +/* + * unregister a fbxprocfs client, make sure usage count is zero + */ +int fbxprocfs_remove_client(struct fbxprocfs_client *client) +{ + int ret; + + mutex_lock(&clients_mutex); + + ret = 0; + if (atomic_read(&client->refcount) > 1) { + ret = -EBUSY; + goto out; + } + + remove_proc_entry(client->dirname, root); + list_del(&client->list); + kfree(client); + +out: + mutex_unlock(&clients_mutex); + return ret; +} + +/* + * remove given entries from client directory + */ +static int +__remove_entries(struct fbxprocfs_client *client, + const struct fbxprocfs_desc *ro_desc, + const struct fbxprocfs_desc *rw_desc) +{ + int i; + + for (i = 0; ro_desc && ro_desc[i].name; i++) { + remove_proc_entry(ro_desc[i].name, client->dir); + atomic_dec(&client->refcount); + } + + for (i = 0; rw_desc && rw_desc[i].name; i++) { + remove_proc_entry(rw_desc[i].name, client->dir); + atomic_dec(&client->refcount); + } + + return 0; +} + +/* + * replacement for NULL rfunc. + */ +static int bad_rfunc(struct seq_file *m, void *ptr) +{ + return -EACCES; +} + +/* + * fbxprocfs write path is now handled by seq_file code. this + * simplifies client code greatly. + */ +static int fbxprocfs_open(struct inode *inode, struct file *file) +{ + const struct fbxprocfs_desc *desc = PDE_DATA(inode); + + return single_open(file, desc->rfunc ? desc->rfunc : bad_rfunc, + (void*)desc->id); +} + +/* + * no particular help from kernel in the write path, fetch user buffer + * in a kernel buffer and call write func. + */ +static ssize_t fbxprocfs_write(struct file *file, const char __user *ubuf, + size_t len, loff_t *off) +{ + /* + * get fbxprocfs desc via the proc_dir_entry in file inode + */ + struct fbxprocfs_desc *d = PDE_DATA(file_inode(file)); + char *kbuf; + ssize_t ret; + + /* + * must have a wfunc callback. + */ + if (!d->wfunc) + return -EACCES; + + /* + * allow up to SZ_4K bytes to be written. + */ + if (len > SZ_4K) + return -EOVERFLOW; + + /* + * alloc and fetch kernel buffer containing user data. + */ + kbuf = kmalloc(SZ_4K, GFP_KERNEL); + if (!kbuf) + return -ENOMEM; + + ret = -EFAULT; + if (copy_from_user(kbuf, ubuf, len)) + goto kfree; + + ret = d->wfunc(file, kbuf, len, (void*)d->id); + +kfree: + kfree(kbuf); + return ret; +} + +/* + * fbxprocfs file operations, read stuff is handled by seq_file code. + */ +static const struct file_operations fbxprocfs_fops = { + .open = fbxprocfs_open, + .llseek = seq_lseek, + .read = seq_read, + .release = seq_release, + .write = fbxprocfs_write, +}; + +/* + * replaces create_proc_read_entry removed in latest kernels. + */ +static struct proc_dir_entry *__create_proc_read_entry( + const struct fbxprocfs_desc *desc, + struct proc_dir_entry *base) +{ + return proc_create_data(desc->name, 0, base, &fbxprocfs_fops, + (void*)desc); +} + +/* + * replaces create_proc_entry removed in latest kernels. + */ +static struct proc_dir_entry *__create_proc_entry( + const struct fbxprocfs_desc *desc, + struct proc_dir_entry *base) +{ + return proc_create_data(desc->name, S_IFREG | S_IWUSR | S_IRUGO, + base, &fbxprocfs_fops, (void*)desc); +} + +/* + * create given entries in client directory + */ +static int +__create_entries(struct fbxprocfs_client *client, + const struct fbxprocfs_desc *ro_desc, + const struct fbxprocfs_desc *rw_desc) +{ + struct proc_dir_entry *proc; + int i; + + for (i = 0; ro_desc && ro_desc[i].name; i++) { + if (!(proc = __create_proc_read_entry(&ro_desc[i], + client->dir))) { + printk(KERN_ERR PFX "can't create %s/%s entry\n", + client->dirname, ro_desc[i].name); + goto err; + } + atomic_inc(&client->refcount); + } + + for (i = 0; rw_desc && rw_desc[i].name; i++) { + if (!(proc = __create_proc_entry(&rw_desc[i], client->dir))) { + printk(KERN_ERR PFX "can't create %s/%s entry\n", + client->dirname, ro_desc[i].name); + goto err; + } + atomic_inc(&client->refcount); + } + + return 0; + +err: + __remove_entries(client, ro_desc, rw_desc); + return -1; +} + +int +fbxprocfs_create_entries(struct fbxprocfs_client *client, + const struct fbxprocfs_desc *ro_desc, + const struct fbxprocfs_desc *rw_desc) +{ + int ret; + + ret = __create_entries(client, ro_desc, rw_desc); + return ret; +} + +int +fbxprocfs_remove_entries(struct fbxprocfs_client *client, + const struct fbxprocfs_desc *ro_desc, + const struct fbxprocfs_desc *rw_desc) +{ + int ret; + + ret = __remove_entries(client, ro_desc, rw_desc); + return ret; +} + + +static int __init +fbxprocfs_init(void) +{ + INIT_LIST_HEAD(&clients); + mutex_init(&clients_mutex); + + /* create freebox directory */ + if (!(root = proc_mkdir("freebox", NULL))) { + printk(KERN_ERR PFX "can't create freebox/ dir\n"); + return -EIO; + } + return 0; +} + +static void __exit +fbxprocfs_exit(void) +{ + remove_proc_entry("freebox", NULL); +} + +module_init(fbxprocfs_init); +module_exit(fbxprocfs_exit); + +EXPORT_SYMBOL(fbxprocfs_create_entries); +EXPORT_SYMBOL(fbxprocfs_remove_entries); +EXPORT_SYMBOL(fbxprocfs_add_client); +EXPORT_SYMBOL(fbxprocfs_remove_client); + +MODULE_LICENSE("GPL"); +MODULE_VERSION("1.0"); +MODULE_AUTHOR("Maxime Bizon "); + diff -Nruw linux-4.4.115-fbx/drivers/fbxprocfs./Kconfig linux-4.4.115-fbx/drivers/fbxprocfs/Kconfig --- linux-4.4.115-fbx/drivers/fbxprocfs./Kconfig 1970-01-01 01:00:00.000000000 +0100 +++ linux-4.4.115-fbx/drivers/fbxprocfs/Kconfig 2019-01-22 16:16:23.183243509 +0100 @@ -0,0 +1,2 @@ +config FREEBOX_PROCFS + tristate "Freebox procfs interface" diff -Nruw linux-4.4.115-fbx/drivers/fbxprocfs./Makefile linux-4.4.115-fbx/drivers/fbxprocfs/Makefile --- linux-4.4.115-fbx/drivers/fbxprocfs./Makefile 1970-01-01 01:00:00.000000000 +0100 +++ linux-4.4.115-fbx/drivers/fbxprocfs/Makefile 2019-01-22 16:16:23.183243509 +0100 @@ -0,0 +1 @@ +obj-$(CONFIG_FREEBOX_PROCFS) += fbxprocfs.o diff -Nruw linux-4.4.115-fbx/drivers/firmware/qcom./Kconfig linux-4.4.115-fbx/drivers/firmware/qcom/Kconfig --- linux-4.4.115-fbx/drivers/firmware/qcom./Kconfig 1970-01-01 01:00:00.000000000 +0100 +++ linux-4.4.115-fbx/drivers/firmware/qcom/Kconfig 2019-01-22 16:16:23.195243617 +0100 @@ -0,0 +1,7 @@ +config MSM_TZ_LOG + tristate "MSM Trust Zone (TZ) Log Driver" + depends on DEBUG_FS + help + This option enables a driver with a debugfs interface for messages + produced by the Secure code (Trust zone). These messages provide + diagnostic information about TZ operation. diff -Nruw linux-4.4.115-fbx/drivers/firmware/qcom./Makefile linux-4.4.115-fbx/drivers/firmware/qcom/Makefile --- linux-4.4.115-fbx/drivers/firmware/qcom./Makefile 1970-01-01 01:00:00.000000000 +0100 +++ linux-4.4.115-fbx/drivers/firmware/qcom/Makefile 2019-01-22 16:16:23.195243617 +0100 @@ -0,0 +1 @@ +obj-$(CONFIG_MSM_TZ_LOG) += tz_log.o diff -Nruw linux-4.4.115-fbx/drivers/firmware/qcom./tz_log.c linux-4.4.115-fbx/drivers/firmware/qcom/tz_log.c --- linux-4.4.115-fbx/drivers/firmware/qcom./tz_log.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-4.4.115-fbx/drivers/firmware/qcom/tz_log.c 2019-01-22 16:16:23.195243617 +0100 @@ -0,0 +1,1211 @@ +/* Copyright (c) 2011-2015,2017 The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +/* QSEE_LOG_BUF_SIZE = 32K */ +#define QSEE_LOG_BUF_SIZE 0x8000 + + +/* TZ Diagnostic Area legacy version number */ +#define TZBSP_DIAG_MAJOR_VERSION_LEGACY 2 +/* + * Preprocessor Definitions and Constants + */ +#define TZBSP_MAX_CPU_COUNT 0x08 +/* + * Number of VMID Tables + */ +#define TZBSP_DIAG_NUM_OF_VMID 16 +/* + * VMID Description length + */ +#define TZBSP_DIAG_VMID_DESC_LEN 7 +/* + * Number of Interrupts + */ +#define TZBSP_DIAG_INT_NUM 32 +/* + * Length of descriptive name associated with Interrupt + */ +#define TZBSP_MAX_INT_DESC 16 +/* + * TZ 3.X version info + */ +#define QSEE_VERSION_TZ_3_X 0x800000 +/* + * TZ 4.X version info + */ +#define QSEE_VERSION_TZ_4_X 0x1000000 + +#define TZBSP_AES_256_ENCRYPTED_KEY_SIZE 256 +#define TZBSP_NONCE_LEN 12 +#define TZBSP_TAG_LEN 16 + +/* + * VMID Table + */ +struct tzdbg_vmid_t { + uint8_t vmid; /* Virtual Machine Identifier */ + uint8_t desc[TZBSP_DIAG_VMID_DESC_LEN]; /* ASCII Text */ +}; +/* + * Boot Info Table + */ +struct tzdbg_boot_info_t { + uint32_t wb_entry_cnt; /* Warmboot entry CPU Counter */ + uint32_t wb_exit_cnt; /* Warmboot exit CPU Counter */ + uint32_t pc_entry_cnt; /* Power Collapse entry CPU Counter */ + uint32_t pc_exit_cnt; /* Power Collapse exit CPU counter */ + uint32_t warm_jmp_addr; /* Last Warmboot Jump Address */ + uint32_t spare; /* Reserved for future use. */ +}; +/* + * Boot Info Table for 64-bit + */ +struct tzdbg_boot_info64_t { + uint32_t wb_entry_cnt; /* Warmboot entry CPU Counter */ + uint32_t wb_exit_cnt; /* Warmboot exit CPU Counter */ + uint32_t pc_entry_cnt; /* Power Collapse entry CPU Counter */ + uint32_t pc_exit_cnt; /* Power Collapse exit CPU counter */ + uint32_t psci_entry_cnt;/* PSCI syscall entry CPU Counter */ + uint32_t psci_exit_cnt; /* PSCI syscall exit CPU Counter */ + uint64_t warm_jmp_addr; /* Last Warmboot Jump Address */ + uint32_t warm_jmp_instr; /* Last Warmboot Jump Address Instruction */ +}; +/* + * Reset Info Table + */ +struct tzdbg_reset_info_t { + uint32_t reset_type; /* Reset Reason */ + uint32_t reset_cnt; /* Number of resets occured/CPU */ +}; +/* + * Interrupt Info Table + */ +struct tzdbg_int_t { + /* + * Type of Interrupt/exception + */ + uint16_t int_info; + /* + * Availability of the slot + */ + uint8_t avail; + /* + * Reserved for future use + */ + uint8_t spare; + /* + * Interrupt # for IRQ and FIQ + */ + uint32_t int_num; + /* + * ASCII text describing type of interrupt e.g: + * Secure Timer, EBI XPU. This string is always null terminated, + * supporting at most TZBSP_MAX_INT_DESC characters. + * Any additional characters are truncated. + */ + uint8_t int_desc[TZBSP_MAX_INT_DESC]; + uint64_t int_count[TZBSP_MAX_CPU_COUNT]; /* # of times seen per CPU */ +}; + +/* + * Interrupt Info Table used in tz version >=4.X + */ +struct tzdbg_int_t_tz40 { + uint16_t int_info; + uint8_t avail; + uint8_t spare; + uint32_t int_num; + uint8_t int_desc[TZBSP_MAX_INT_DESC]; + uint32_t int_count[TZBSP_MAX_CPU_COUNT]; /* uint32_t in TZ ver >= 4.x*/ +}; + +/* warm boot reason for cores */ +struct tzbsp_diag_wakeup_info_t { + /* Wake source info : APCS_GICC_HPPIR */ + uint32_t HPPIR; + /* Wake source info : APCS_GICC_AHPPIR */ + uint32_t AHPPIR; +}; + +/* + * Log ring buffer position + */ +struct tzdbg_log_pos_t { + uint16_t wrap; + uint16_t offset; +}; + + /* + * Log ring buffer + */ +struct tzdbg_log_t { + struct tzdbg_log_pos_t log_pos; + /* open ended array to the end of the 4K IMEM buffer */ + uint8_t log_buf[]; +}; + +/* + * Diagnostic Table + * Note: This is the reference data structure for tz diagnostic table + * supporting TZBSP_MAX_CPU_COUNT, the real diagnostic data is directly + * copied into buffer from i/o memory. + */ +struct tzdbg_t { + uint32_t magic_num; + uint32_t version; + /* + * Number of CPU's + */ + uint32_t cpu_count; + /* + * Offset of VMID Table + */ + uint32_t vmid_info_off; + /* + * Offset of Boot Table + */ + uint32_t boot_info_off; + /* + * Offset of Reset info Table + */ + uint32_t reset_info_off; + /* + * Offset of Interrupt info Table + */ + uint32_t int_info_off; + /* + * Ring Buffer Offset + */ + uint32_t ring_off; + /* + * Ring Buffer Length + */ + uint32_t ring_len; + + /* Offset for Wakeup info */ + uint32_t wakeup_info_off; + + /* + * VMID to EE Mapping + */ + struct tzdbg_vmid_t vmid_info[TZBSP_DIAG_NUM_OF_VMID]; + /* + * Boot Info + */ + struct tzdbg_boot_info_t boot_info[TZBSP_MAX_CPU_COUNT]; + /* + * Reset Info + */ + struct tzdbg_reset_info_t reset_info[TZBSP_MAX_CPU_COUNT]; + uint32_t num_interrupts; + struct tzdbg_int_t int_info[TZBSP_DIAG_INT_NUM]; + + /* Wake up info */ + struct tzbsp_diag_wakeup_info_t wakeup_info[TZBSP_MAX_CPU_COUNT]; + + uint8_t key[TZBSP_AES_256_ENCRYPTED_KEY_SIZE]; + + uint8_t nonce[TZBSP_NONCE_LEN]; + + uint8_t tag[TZBSP_TAG_LEN]; + + /* + * We need at least 2K for the ring buffer + */ + struct tzdbg_log_t ring_buffer; /* TZ Ring Buffer */ +}; + +struct hypdbg_log_pos_t { + uint16_t wrap; + uint16_t offset; +}; + +struct hypdbg_boot_info_t { + uint32_t warm_entry_cnt; + uint32_t warm_exit_cnt; +}; + +struct hypdbg_t { + /* Magic Number */ + uint32_t magic_num; + + /* Number of CPU's */ + uint32_t cpu_count; + + /* Ring Buffer Offset */ + uint32_t ring_off; + + /* Ring buffer position mgmt */ + struct hypdbg_log_pos_t log_pos; + uint32_t log_len; + + /* S2 fault numbers */ + uint32_t s2_fault_counter; + + /* Boot Info */ + struct hypdbg_boot_info_t boot_info[TZBSP_MAX_CPU_COUNT]; + + /* Ring buffer pointer */ + uint8_t log_buf_p[]; +}; + +/* + * Enumeration order for VMID's + */ +enum tzdbg_stats_type { + TZDBG_BOOT = 0, + TZDBG_RESET, + TZDBG_INTERRUPT, + TZDBG_VMID, + TZDBG_GENERAL, + TZDBG_LOG, + TZDBG_QSEE_LOG, + TZDBG_HYP_GENERAL, + TZDBG_HYP_LOG, + TZDBG_STATS_MAX +}; + +struct tzdbg_stat { + char *name; + char *data; +}; + +struct tzdbg { + void __iomem *virt_iobase; + void __iomem *hyp_virt_iobase; + struct tzdbg_t *diag_buf; + struct hypdbg_t *hyp_diag_buf; + char *disp_buf; + int debug_tz[TZDBG_STATS_MAX]; + struct tzdbg_stat stat[TZDBG_STATS_MAX]; + uint32_t hyp_debug_rw_buf_size; + bool is_hyplog_enabled; + uint32_t tz_version; +}; + +static struct tzdbg tzdbg = { + .stat[TZDBG_BOOT].name = "boot", + .stat[TZDBG_RESET].name = "reset", + .stat[TZDBG_INTERRUPT].name = "interrupt", + .stat[TZDBG_VMID].name = "vmid", + .stat[TZDBG_GENERAL].name = "general", + .stat[TZDBG_LOG].name = "log", + .stat[TZDBG_QSEE_LOG].name = "qsee_log", + .stat[TZDBG_HYP_GENERAL].name = "hyp_general", + .stat[TZDBG_HYP_LOG].name = "hyp_log", +}; + +static struct tzdbg_log_t *g_qsee_log; +static uint32_t debug_rw_buf_size; + +/* + * Debugfs data structure and functions + */ + +static int _disp_tz_general_stats(void) +{ + int len = 0; + + len += snprintf(tzdbg.disp_buf + len, debug_rw_buf_size - 1, + " Version : 0x%x\n" + " Magic Number : 0x%x\n" + " Number of CPU : %d\n", + tzdbg.diag_buf->version, + tzdbg.diag_buf->magic_num, + tzdbg.diag_buf->cpu_count); + tzdbg.stat[TZDBG_GENERAL].data = tzdbg.disp_buf; + return len; +} + +static int _disp_tz_vmid_stats(void) +{ + int i, num_vmid; + int len = 0; + struct tzdbg_vmid_t *ptr; + + ptr = (struct tzdbg_vmid_t *)((unsigned char *)tzdbg.diag_buf + + tzdbg.diag_buf->vmid_info_off); + num_vmid = ((tzdbg.diag_buf->boot_info_off - + tzdbg.diag_buf->vmid_info_off)/ + (sizeof(struct tzdbg_vmid_t))); + + for (i = 0; i < num_vmid; i++) { + if (ptr->vmid < 0xFF) { + len += snprintf(tzdbg.disp_buf + len, + (debug_rw_buf_size - 1) - len, + " 0x%x %s\n", + (uint32_t)ptr->vmid, (uint8_t *)ptr->desc); + } + if (len > (debug_rw_buf_size - 1)) { + pr_warn("%s: Cannot fit all info into the buffer\n", + __func__); + break; + } + ptr++; + } + + tzdbg.stat[TZDBG_VMID].data = tzdbg.disp_buf; + return len; +} + +static int _disp_tz_boot_stats(void) +{ + int i; + int len = 0; + struct tzdbg_boot_info_t *ptr = NULL; + struct tzdbg_boot_info64_t *ptr_64 = NULL; + + pr_info("qsee_version = 0x%x\n", tzdbg.tz_version); + if (tzdbg.tz_version >= QSEE_VERSION_TZ_3_X) { + ptr_64 = (struct tzdbg_boot_info64_t *)((unsigned char *) + tzdbg.diag_buf + tzdbg.diag_buf->boot_info_off); + } else { + ptr = (struct tzdbg_boot_info_t *)((unsigned char *) + tzdbg.diag_buf + tzdbg.diag_buf->boot_info_off); + } + + for (i = 0; i < tzdbg.diag_buf->cpu_count; i++) { + if (tzdbg.tz_version >= QSEE_VERSION_TZ_3_X) { + len += snprintf(tzdbg.disp_buf + len, + (debug_rw_buf_size - 1) - len, + " CPU #: %d\n" + " Warmboot jump address : 0x%llx\n" + " Warmboot entry CPU counter : 0x%x\n" + " Warmboot exit CPU counter : 0x%x\n" + " Power Collapse entry CPU counter : 0x%x\n" + " Power Collapse exit CPU counter : 0x%x\n" + " Psci entry CPU counter : 0x%x\n" + " Psci exit CPU counter : 0x%x\n" + " Warmboot Jump Address Instruction : 0x%x\n", + i, (uint64_t)ptr_64->warm_jmp_addr, + ptr_64->wb_entry_cnt, + ptr_64->wb_exit_cnt, + ptr_64->pc_entry_cnt, + ptr_64->pc_exit_cnt, + ptr_64->psci_entry_cnt, + ptr_64->psci_exit_cnt, + ptr_64->warm_jmp_instr); + + if (len > (debug_rw_buf_size - 1)) { + pr_warn("%s: Cannot fit all info into the buffer\n", + __func__); + break; + } + ptr_64++; + } else { + len += snprintf(tzdbg.disp_buf + len, + (debug_rw_buf_size - 1) - len, + " CPU #: %d\n" + " Warmboot jump address : 0x%x\n" + " Warmboot entry CPU counter: 0x%x\n" + " Warmboot exit CPU counter : 0x%x\n" + " Power Collapse entry CPU counter: 0x%x\n" + " Power Collapse exit CPU counter : 0x%x\n", + i, ptr->warm_jmp_addr, + ptr->wb_entry_cnt, + ptr->wb_exit_cnt, + ptr->pc_entry_cnt, + ptr->pc_exit_cnt); + + if (len > (debug_rw_buf_size - 1)) { + pr_warn("%s: Cannot fit all info into the buffer\n", + __func__); + break; + } + ptr++; + } + } + tzdbg.stat[TZDBG_BOOT].data = tzdbg.disp_buf; + return len; +} + +static int _disp_tz_reset_stats(void) +{ + int i; + int len = 0; + struct tzdbg_reset_info_t *ptr; + + ptr = (struct tzdbg_reset_info_t *)((unsigned char *)tzdbg.diag_buf + + tzdbg.diag_buf->reset_info_off); + + for (i = 0; i < tzdbg.diag_buf->cpu_count; i++) { + len += snprintf(tzdbg.disp_buf + len, + (debug_rw_buf_size - 1) - len, + " CPU #: %d\n" + " Reset Type (reason) : 0x%x\n" + " Reset counter : 0x%x\n", + i, ptr->reset_type, ptr->reset_cnt); + + if (len > (debug_rw_buf_size - 1)) { + pr_warn("%s: Cannot fit all info into the buffer\n", + __func__); + break; + } + + ptr++; + } + tzdbg.stat[TZDBG_RESET].data = tzdbg.disp_buf; + return len; +} + +static int _disp_tz_interrupt_stats(void) +{ + int i, j; + int len = 0; + int *num_int; + void *ptr; + struct tzdbg_int_t *tzdbg_ptr; + struct tzdbg_int_t_tz40 *tzdbg_ptr_tz40; + + num_int = (uint32_t *)((unsigned char *)tzdbg.diag_buf + + (tzdbg.diag_buf->int_info_off - sizeof(uint32_t))); + ptr = ((unsigned char *)tzdbg.diag_buf + + tzdbg.diag_buf->int_info_off); + + pr_info("qsee_version = 0x%x\n", tzdbg.tz_version); + + if (tzdbg.tz_version < QSEE_VERSION_TZ_4_X) { + tzdbg_ptr = ptr; + for (i = 0; i < (*num_int); i++) { + len += snprintf(tzdbg.disp_buf + len, + (debug_rw_buf_size - 1) - len, + " Interrupt Number : 0x%x\n" + " Type of Interrupt : 0x%x\n" + " Description of interrupt : %s\n", + tzdbg_ptr->int_num, + (uint32_t)tzdbg_ptr->int_info, + (uint8_t *)tzdbg_ptr->int_desc); + for (j = 0; j < tzdbg.diag_buf->cpu_count; j++) { + len += snprintf(tzdbg.disp_buf + len, + (debug_rw_buf_size - 1) - len, + " int_count on CPU # %d : %u\n", + (uint32_t)j, + (uint32_t)tzdbg_ptr->int_count[j]); + } + len += snprintf(tzdbg.disp_buf + len, + debug_rw_buf_size - 1, "\n"); + + if (len > (debug_rw_buf_size - 1)) { + pr_warn("%s: Cannot fit all info into buf\n", + __func__); + break; + } + tzdbg_ptr++; + } + } else { + tzdbg_ptr_tz40 = ptr; + for (i = 0; i < (*num_int); i++) { + len += snprintf(tzdbg.disp_buf + len, + (debug_rw_buf_size - 1) - len, + " Interrupt Number : 0x%x\n" + " Type of Interrupt : 0x%x\n" + " Description of interrupt : %s\n", + tzdbg_ptr_tz40->int_num, + (uint32_t)tzdbg_ptr_tz40->int_info, + (uint8_t *)tzdbg_ptr_tz40->int_desc); + for (j = 0; j < tzdbg.diag_buf->cpu_count; j++) { + len += snprintf(tzdbg.disp_buf + len, + (debug_rw_buf_size - 1) - len, + " int_count on CPU # %d : %u\n", + (uint32_t)j, + (uint32_t)tzdbg_ptr_tz40->int_count[j]); + } + len += snprintf(tzdbg.disp_buf + len, + debug_rw_buf_size - 1, "\n"); + + if (len > (debug_rw_buf_size - 1)) { + pr_warn("%s: Cannot fit all info into buf\n", + __func__); + break; + } + tzdbg_ptr_tz40++; + } + } + + tzdbg.stat[TZDBG_INTERRUPT].data = tzdbg.disp_buf; + return len; +} + +static int _disp_tz_log_stats_legacy(void) +{ + int len = 0; + unsigned char *ptr; + + ptr = (unsigned char *)tzdbg.diag_buf + + tzdbg.diag_buf->ring_off; + len += snprintf(tzdbg.disp_buf, (debug_rw_buf_size - 1) - len, + "%s\n", ptr); + + tzdbg.stat[TZDBG_LOG].data = tzdbg.disp_buf; + return len; +} + +static int _disp_log_stats(struct tzdbg_log_t *log, + struct tzdbg_log_pos_t *log_start, uint32_t log_len, + size_t count, uint32_t buf_idx) +{ + uint32_t wrap_start; + uint32_t wrap_end; + uint32_t wrap_cnt; + int max_len; + int len = 0; + int i = 0; + + wrap_start = log_start->wrap; + wrap_end = log->log_pos.wrap; + + /* Calculate difference in # of buffer wrap-arounds */ + if (wrap_end >= wrap_start) { + wrap_cnt = wrap_end - wrap_start; + } else { + /* wrap counter has wrapped around, invalidate start position */ + wrap_cnt = 2; + } + + if (wrap_cnt > 1) { + /* end position has wrapped around more than once, */ + /* current start no longer valid */ + log_start->wrap = log->log_pos.wrap - 1; + log_start->offset = (log->log_pos.offset + 1) % log_len; + } else if ((wrap_cnt == 1) && + (log->log_pos.offset > log_start->offset)) { + /* end position has overwritten start */ + log_start->offset = (log->log_pos.offset + 1) % log_len; + } + + while (log_start->offset == log->log_pos.offset) { + /* + * No data in ring buffer, + * so we'll hang around until something happens + */ + unsigned long t = msleep_interruptible(50); + if (t != 0) { + /* Some event woke us up, so let's quit */ + return 0; + } + + if (buf_idx == TZDBG_LOG) + memcpy_fromio((void *)tzdbg.diag_buf, tzdbg.virt_iobase, + debug_rw_buf_size); + + } + + max_len = (count > debug_rw_buf_size) ? debug_rw_buf_size : count; + + /* + * Read from ring buff while there is data and space in return buff + */ + while ((log_start->offset != log->log_pos.offset) && (len < max_len)) { + tzdbg.disp_buf[i++] = log->log_buf[log_start->offset]; + log_start->offset = (log_start->offset + 1) % log_len; + if (0 == log_start->offset) + ++log_start->wrap; + ++len; + } + + /* + * return buffer to caller + */ + tzdbg.stat[buf_idx].data = tzdbg.disp_buf; + return len; +} + +static int __disp_hyp_log_stats(uint8_t *log, + struct hypdbg_log_pos_t *log_start, uint32_t log_len, + size_t count, uint32_t buf_idx) +{ + struct hypdbg_t *hyp = tzdbg.hyp_diag_buf; + unsigned long t = 0; + uint32_t wrap_start; + uint32_t wrap_end; + uint32_t wrap_cnt; + int max_len; + int len = 0; + int i = 0; + + wrap_start = log_start->wrap; + wrap_end = hyp->log_pos.wrap; + + /* Calculate difference in # of buffer wrap-arounds */ + if (wrap_end >= wrap_start) { + wrap_cnt = wrap_end - wrap_start; + } else { + /* wrap counter has wrapped around, invalidate start position */ + wrap_cnt = 2; + } + + if (wrap_cnt > 1) { + /* end position has wrapped around more than once, */ + /* current start no longer valid */ + log_start->wrap = hyp->log_pos.wrap - 1; + log_start->offset = (hyp->log_pos.offset + 1) % log_len; + } else if ((wrap_cnt == 1) && + (hyp->log_pos.offset > log_start->offset)) { + /* end position has overwritten start */ + log_start->offset = (hyp->log_pos.offset + 1) % log_len; + } + + while (log_start->offset == hyp->log_pos.offset) { + /* + * No data in ring buffer, + * so we'll hang around until something happens + */ + t = msleep_interruptible(50); + if (t != 0) { + /* Some event woke us up, so let's quit */ + return 0; + } + + /* TZDBG_HYP_LOG */ + memcpy_fromio((void *)tzdbg.hyp_diag_buf, tzdbg.hyp_virt_iobase, + tzdbg.hyp_debug_rw_buf_size); + } + + max_len = (count > tzdbg.hyp_debug_rw_buf_size) ? + tzdbg.hyp_debug_rw_buf_size : count; + + /* + * Read from ring buff while there is data and space in return buff + */ + while ((log_start->offset != hyp->log_pos.offset) && (len < max_len)) { + tzdbg.disp_buf[i++] = log[log_start->offset]; + log_start->offset = (log_start->offset + 1) % log_len; + if (0 == log_start->offset) + ++log_start->wrap; + ++len; + } + + /* + * return buffer to caller + */ + tzdbg.stat[buf_idx].data = tzdbg.disp_buf; + return len; +} + +static int _disp_tz_log_stats(size_t count) +{ + static struct tzdbg_log_pos_t log_start = {0}; + struct tzdbg_log_t *log_ptr; + log_ptr = (struct tzdbg_log_t *)((unsigned char *)tzdbg.diag_buf + + tzdbg.diag_buf->ring_off - + offsetof(struct tzdbg_log_t, log_buf)); + + return _disp_log_stats(log_ptr, &log_start, + tzdbg.diag_buf->ring_len, count, TZDBG_LOG); +} + +static int _disp_hyp_log_stats(size_t count) +{ + static struct hypdbg_log_pos_t log_start = {0}; + uint8_t *log_ptr; + + log_ptr = (uint8_t *)((unsigned char *)tzdbg.hyp_diag_buf + + tzdbg.hyp_diag_buf->ring_off); + + return __disp_hyp_log_stats(log_ptr, &log_start, + tzdbg.hyp_debug_rw_buf_size, count, TZDBG_HYP_LOG); +} + +static int _disp_qsee_log_stats(size_t count) +{ + static struct tzdbg_log_pos_t log_start = {0}; + + return _disp_log_stats(g_qsee_log, &log_start, + QSEE_LOG_BUF_SIZE - sizeof(struct tzdbg_log_pos_t), + count, TZDBG_QSEE_LOG); +} + +static int _disp_hyp_general_stats(size_t count) +{ + int len = 0; + int i; + struct hypdbg_boot_info_t *ptr = NULL; + + len += snprintf((unsigned char *)tzdbg.disp_buf + len, + tzdbg.hyp_debug_rw_buf_size - 1, + " Magic Number : 0x%x\n" + " CPU Count : 0x%x\n" + " S2 Fault Counter: 0x%x\n", + tzdbg.hyp_diag_buf->magic_num, + tzdbg.hyp_diag_buf->cpu_count, + tzdbg.hyp_diag_buf->s2_fault_counter); + + ptr = tzdbg.hyp_diag_buf->boot_info; + for (i = 0; i < tzdbg.hyp_diag_buf->cpu_count; i++) { + len += snprintf((unsigned char *)tzdbg.disp_buf + len, + (tzdbg.hyp_debug_rw_buf_size - 1) - len, + " CPU #: %d\n" + " Warmboot entry CPU counter: 0x%x\n" + " Warmboot exit CPU counter : 0x%x\n", + i, ptr->warm_entry_cnt, ptr->warm_exit_cnt); + + if (len > (tzdbg.hyp_debug_rw_buf_size - 1)) { + pr_warn("%s: Cannot fit all info into the buffer\n", + __func__); + break; + } + ptr++; + } + + tzdbg.stat[TZDBG_HYP_GENERAL].data = (char *)tzdbg.disp_buf; + return len; +} + +static ssize_t tzdbgfs_read(struct file *file, char __user *buf, + size_t count, loff_t *offp) +{ + int len = 0; + int *tz_id = file->private_data; + + if (*tz_id == TZDBG_BOOT || *tz_id == TZDBG_RESET || + *tz_id == TZDBG_INTERRUPT || *tz_id == TZDBG_GENERAL || + *tz_id == TZDBG_VMID || *tz_id == TZDBG_LOG) + memcpy_fromio((void *)tzdbg.diag_buf, tzdbg.virt_iobase, + debug_rw_buf_size); + + if (*tz_id == TZDBG_HYP_GENERAL || *tz_id == TZDBG_HYP_LOG) + memcpy_fromio((void *)tzdbg.hyp_diag_buf, tzdbg.hyp_virt_iobase, + tzdbg.hyp_debug_rw_buf_size); + + switch (*tz_id) { + case TZDBG_BOOT: + len = _disp_tz_boot_stats(); + break; + case TZDBG_RESET: + len = _disp_tz_reset_stats(); + break; + case TZDBG_INTERRUPT: + len = _disp_tz_interrupt_stats(); + break; + case TZDBG_GENERAL: + len = _disp_tz_general_stats(); + break; + case TZDBG_VMID: + len = _disp_tz_vmid_stats(); + break; + case TZDBG_LOG: + if (TZBSP_DIAG_MAJOR_VERSION_LEGACY < + (tzdbg.diag_buf->version >> 16)) { + len = _disp_tz_log_stats(count); + *offp = 0; + } else { + len = _disp_tz_log_stats_legacy(); + } + break; + case TZDBG_QSEE_LOG: + len = _disp_qsee_log_stats(count); + *offp = 0; + break; + case TZDBG_HYP_GENERAL: + len = _disp_hyp_general_stats(count); + break; + case TZDBG_HYP_LOG: + len = _disp_hyp_log_stats(count); + *offp = 0; + break; + default: + break; + } + + if (len > count) + len = count; + + return simple_read_from_buffer(buf, len, offp, + tzdbg.stat[(*tz_id)].data, len); +} + +static int tzdbgfs_open(struct inode *inode, struct file *pfile) +{ + pfile->private_data = inode->i_private; + return 0; +} + +const struct file_operations tzdbg_fops = { + .owner = THIS_MODULE, + .read = tzdbgfs_read, + .open = tzdbgfs_open, +}; + +static struct ion_client *g_ion_clnt; +static struct ion_handle *g_ihandle; + +/* + * Allocates log buffer from ION, registers the buffer at TZ + */ +static void tzdbg_register_qsee_log_buf(void) +{ + /* register log buffer scm request */ + struct qseecom_reg_log_buf_ireq req; + + /* scm response */ + struct qseecom_command_scm_resp resp = {}; + ion_phys_addr_t pa = 0; + size_t len; + int ret = 0; + + /* Create ION msm client */ + g_ion_clnt = msm_ion_client_create("qsee_log"); + if (g_ion_clnt == NULL) { + pr_err("%s: Ion client cannot be created\n", __func__); + return; + } + + g_ihandle = ion_alloc(g_ion_clnt, QSEE_LOG_BUF_SIZE, + 4096, ION_HEAP(ION_QSECOM_HEAP_ID), 0); + if (IS_ERR_OR_NULL(g_ihandle)) { + pr_err("%s: Ion client could not retrieve the handle\n", + __func__); + goto err1; + } + + ret = ion_phys(g_ion_clnt, g_ihandle, &pa, &len); + if (ret) { + pr_err("%s: Ion conversion to physical address failed\n", + __func__); + goto err2; + } + + req.qsee_cmd_id = QSEOS_REGISTER_LOG_BUF_COMMAND; + req.phy_addr = (uint32_t)pa; + req.len = len; + + if (!is_scm_armv8()) { + /* SCM_CALL to register the log buffer */ + ret = scm_call(SCM_SVC_TZSCHEDULER, 1, &req, sizeof(req), + &resp, sizeof(resp)); + } else { + struct scm_desc desc = {0}; + desc.args[0] = pa; + desc.args[1] = len; + desc.arginfo = 0x22; + ret = scm_call2(SCM_QSEEOS_FNID(1, 6), &desc); + resp.result = desc.ret[0]; + } + + if (ret) { + pr_err("%s: scm_call to register log buffer failed\n", + __func__); + goto err2; + } + + if (resp.result != QSEOS_RESULT_SUCCESS) { + pr_err( + "%s: scm_call to register log buf failed, resp result =%d\n", + __func__, resp.result); + goto err2; + } + + g_qsee_log = + (struct tzdbg_log_t *)ion_map_kernel(g_ion_clnt, g_ihandle); + + if (IS_ERR(g_qsee_log)) { + pr_err("%s: Couldn't map ion buffer to kernel\n", + __func__); + goto err2; + } + + g_qsee_log->log_pos.wrap = g_qsee_log->log_pos.offset = 0; + return; + +err2: + ion_free(g_ion_clnt, g_ihandle); + g_ihandle = NULL; +err1: + ion_client_destroy(g_ion_clnt); + g_ion_clnt = NULL; +} + +static int tzdbgfs_init(struct platform_device *pdev) +{ + int rc = 0; + int i; + struct dentry *dent_dir; + struct dentry *dent; + + dent_dir = debugfs_create_dir("tzdbg", NULL); + if (dent_dir == NULL) { + dev_err(&pdev->dev, "tzdbg debugfs_create_dir failed\n"); + return -ENOMEM; + } + + for (i = 0; i < TZDBG_STATS_MAX; i++) { + tzdbg.debug_tz[i] = i; + dent = debugfs_create_file(tzdbg.stat[i].name, + S_IRUGO, dent_dir, + &tzdbg.debug_tz[i], &tzdbg_fops); + if (dent == NULL) { + dev_err(&pdev->dev, "TZ debugfs_create_file failed\n"); + rc = -ENOMEM; + goto err; + } + } + tzdbg.disp_buf = kzalloc(max(debug_rw_buf_size, + tzdbg.hyp_debug_rw_buf_size), GFP_KERNEL); + if (tzdbg.disp_buf == NULL) { + pr_err("%s: Can't Allocate memory for tzdbg.disp_buf\n", + __func__); + + goto err; + } + platform_set_drvdata(pdev, dent_dir); + return 0; +err: + debugfs_remove_recursive(dent_dir); + + return rc; +} + +static void tzdbgfs_exit(struct platform_device *pdev) +{ + struct dentry *dent_dir; + + kzfree(tzdbg.disp_buf); + dent_dir = platform_get_drvdata(pdev); + debugfs_remove_recursive(dent_dir); + if (g_ion_clnt != NULL) { + if (!IS_ERR_OR_NULL(g_ihandle)) { + ion_unmap_kernel(g_ion_clnt, g_ihandle); + ion_free(g_ion_clnt, g_ihandle); + } + ion_client_destroy(g_ion_clnt); + } +} + +static int __update_hypdbg_base(struct platform_device *pdev, + void __iomem *virt_iobase) +{ + phys_addr_t hypdiag_phy_iobase; + uint32_t hyp_address_offset; + uint32_t hyp_size_offset; + struct hypdbg_t *hyp; + uint32_t *ptr = NULL; + + if (of_property_read_u32((&pdev->dev)->of_node, "hyplog-address-offset", + &hyp_address_offset)) { + dev_err(&pdev->dev, "hyplog address offset is not defined\n"); + return -EINVAL; + } + if (of_property_read_u32((&pdev->dev)->of_node, "hyplog-size-offset", + &hyp_size_offset)) { + dev_err(&pdev->dev, "hyplog size offset is not defined\n"); + return -EINVAL; + } + + hypdiag_phy_iobase = readl_relaxed(virt_iobase + hyp_address_offset); + tzdbg.hyp_debug_rw_buf_size = readl_relaxed(virt_iobase + + hyp_size_offset); + + tzdbg.hyp_virt_iobase = devm_ioremap_nocache(&pdev->dev, + hypdiag_phy_iobase, + tzdbg.hyp_debug_rw_buf_size); + if (!tzdbg.hyp_virt_iobase) { + dev_err(&pdev->dev, "ERROR could not ioremap: start=%pr, len=%u\n", + &hypdiag_phy_iobase, tzdbg.hyp_debug_rw_buf_size); + return -ENXIO; + } + + ptr = kzalloc(tzdbg.hyp_debug_rw_buf_size, GFP_KERNEL); + if (!ptr) + return -ENOMEM; + + tzdbg.hyp_diag_buf = (struct hypdbg_t *)ptr; + hyp = tzdbg.hyp_diag_buf; + hyp->log_pos.wrap = hyp->log_pos.offset = 0; + return 0; +} + +static void tzdbg_get_tz_version(void) +{ + uint32_t smc_id = 0; + uint32_t feature = 10; + struct qseecom_command_scm_resp resp = {0}; + struct scm_desc desc = {0}; + int ret = 0; + + if (!is_scm_armv8()) { + ret = scm_call(SCM_SVC_INFO, SCM_SVC_UTIL, &feature, + sizeof(feature), &resp, sizeof(resp)); + } else { + smc_id = TZ_INFO_GET_FEATURE_VERSION_ID; + desc.arginfo = TZ_INFO_GET_FEATURE_VERSION_ID_PARAM_ID; + desc.args[0] = feature; + ret = scm_call2(smc_id, &desc); + resp.result = desc.ret[0]; + } + + if (ret) + pr_err("%s: scm_call to get tz version failed\n", + __func__); + else + tzdbg.tz_version = resp.result; + +} + +/* + * Driver functions + */ +static int tz_log_probe(struct platform_device *pdev) +{ + struct resource *resource; + void __iomem *virt_iobase; + phys_addr_t tzdiag_phy_iobase; + uint32_t *ptr = NULL; + int ret = 0; + + /* + * Get address that stores the physical location diagnostic data + */ + resource = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!resource) { + dev_err(&pdev->dev, + "%s: ERROR Missing MEM resource\n", __func__); + return -ENXIO; + }; + + /* + * Get the debug buffer size + */ + debug_rw_buf_size = resource->end - resource->start + 1; + + /* + * Map address that stores the physical location diagnostic data + */ + virt_iobase = devm_ioremap_nocache(&pdev->dev, resource->start, + debug_rw_buf_size); + if (!virt_iobase) { + dev_err(&pdev->dev, + "%s: ERROR could not ioremap: start=%pr, len=%u\n", + __func__, &resource->start, + (unsigned int)(debug_rw_buf_size)); + return -ENXIO; + } + + if (pdev->dev.of_node) { + tzdbg.is_hyplog_enabled = of_property_read_bool( + (&pdev->dev)->of_node, "qcom,hyplog-enabled"); + if (tzdbg.is_hyplog_enabled) { + ret = __update_hypdbg_base(pdev, virt_iobase); + if (ret) { + dev_err(&pdev->dev, "%s() failed to get device tree data ret = %d\n", + __func__, ret); + return -EINVAL; + } + } else { + dev_info(&pdev->dev, "Hyp log service is not supported\n"); + } + } else { + dev_dbg(&pdev->dev, "Device tree data is not found\n"); + } + + /* + * Retrieve the address of diagnostic data + */ + tzdiag_phy_iobase = readl_relaxed(virt_iobase); + + /* + * Map the diagnostic information area + */ + tzdbg.virt_iobase = devm_ioremap_nocache(&pdev->dev, + tzdiag_phy_iobase, debug_rw_buf_size); + + if (!tzdbg.virt_iobase) { + dev_err(&pdev->dev, + "%s: ERROR could not ioremap: start=%pr, len=%u\n", + __func__, &tzdiag_phy_iobase, + debug_rw_buf_size); + return -ENXIO; + } + + ptr = kzalloc(debug_rw_buf_size, GFP_KERNEL); + if (ptr == NULL) { + pr_err("%s: Can't Allocate memory: ptr\n", + __func__); + return -ENXIO; + } + + tzdbg.diag_buf = (struct tzdbg_t *)ptr; + + if (tzdbgfs_init(pdev)) + goto err; + + tzdbg_register_qsee_log_buf(); + + tzdbg_get_tz_version(); + + return 0; +err: + kfree(tzdbg.diag_buf); + return -ENXIO; +} + + +static int tz_log_remove(struct platform_device *pdev) +{ + kzfree(tzdbg.diag_buf); + if (tzdbg.hyp_diag_buf) + kzfree(tzdbg.hyp_diag_buf); + tzdbgfs_exit(pdev); + + return 0; +} + +static struct of_device_id tzlog_match[] = { + { .compatible = "qcom,tz-log", + }, + {} +}; + +static struct platform_driver tz_log_driver = { + .probe = tz_log_probe, + .remove = tz_log_remove, + .driver = { + .name = "tz_log", + .owner = THIS_MODULE, + .of_match_table = tzlog_match, + .probe_type = PROBE_PREFER_ASYNCHRONOUS, + }, +}; + +static int __init tz_log_init(void) +{ + return platform_driver_register(&tz_log_driver); +} + +static void __exit tz_log_exit(void) +{ + platform_driver_unregister(&tz_log_driver); +} + +module_init(tz_log_init); +module_exit(tz_log_exit); + +MODULE_LICENSE("GPL v2"); +MODULE_DESCRIPTION("TZ Log driver"); +MODULE_ALIAS("platform:tz_log"); --- /dev/null 2019-10-24 16:47:25.704025805 +0200 +++ linux-4.4.115-fbx/drivers/gpio/gpio-msm-smp2p.c 2019-01-22 16:16:23.203243690 +0100 @@ -0,0 +1,835 @@ +/* drivers/gpio/gpio-msm-smp2p.c + * + * Copyright (c) 2013-2014, 2016 The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "../soc/qcom/smp2p_private_api.h" +#include "../soc/qcom/smp2p_private.h" + +/* GPIO device - one per SMP2P entry. */ +struct smp2p_chip_dev { + struct list_head entry_list; + char name[SMP2P_MAX_ENTRY_NAME]; + int remote_pid; + bool is_inbound; + bool is_open; + bool in_shadow; + uint32_t shadow_value; + struct work_struct shadow_work; + spinlock_t shadow_lock; + struct notifier_block out_notifier; + struct notifier_block in_notifier; + struct msm_smp2p_out *out_handle; + + struct gpio_chip gpio; + struct irq_domain *irq_domain; + int irq_base; + + spinlock_t irq_lock; + DECLARE_BITMAP(irq_enabled, SMP2P_BITS_PER_ENTRY); + DECLARE_BITMAP(irq_rising_edge, SMP2P_BITS_PER_ENTRY); + DECLARE_BITMAP(irq_falling_edge, SMP2P_BITS_PER_ENTRY); +}; + +static struct platform_driver smp2p_gpio_driver; +static struct lock_class_key smp2p_gpio_lock_class; +static struct irq_chip smp2p_gpio_irq_chip; +static DEFINE_SPINLOCK(smp2p_entry_lock_lha1); +static LIST_HEAD(smp2p_entry_list); + +/* Used for mapping edge to name for logging. */ +static const char * const edge_names[] = { + "-", + "0->1", + "1->0", + "-", +}; + +/* Used for mapping edge to value for logging. */ +static const char * const edge_name_rising[] = { + "-", + "0->1", +}; + +/* Used for mapping edge to value for logging. */ +static const char * const edge_name_falling[] = { + "-", + "1->0", +}; + +static int smp2p_gpio_to_irq(struct gpio_chip *cp, + unsigned offset); + +/** + * smp2p_get_value - Retrieves GPIO value. + * + * @cp: GPIO chip pointer + * @offset: Pin offset + * @returns: >=0: value of GPIO Pin; < 0 for error + * + * Error codes: + * -ENODEV - chip/entry invalid + * -ENETDOWN - valid entry, but entry not yet created + */ +static int smp2p_get_value(struct gpio_chip *cp, + unsigned offset) +{ + struct smp2p_chip_dev *chip; + int ret = 0; + uint32_t data; + + if (!cp) + return -ENODEV; + + chip = container_of(cp, struct smp2p_chip_dev, gpio); + if (!chip->is_open) + return -ENETDOWN; + + if (chip->is_inbound) + ret = msm_smp2p_in_read(chip->remote_pid, chip->name, &data); + else + ret = msm_smp2p_out_read(chip->out_handle, &data); + + if (!ret) + ret = (data & (1 << offset)) ? 1 : 0; + + return ret; +} + +/** + * smp2p_set_value - Sets GPIO value. + * + * @cp: GPIO chip pointer + * @offset: Pin offset + * @value: New value + */ +static void smp2p_set_value(struct gpio_chip *cp, unsigned offset, int value) +{ + struct smp2p_chip_dev *chip; + uint32_t data_set; + uint32_t data_clear; + bool send_irq; + int ret; + unsigned long flags; + + if (!cp) + return; + + chip = container_of(cp, struct smp2p_chip_dev, gpio); + + if (chip->is_inbound) { + SMP2P_INFO("%s: '%s':%d virq %d invalid operation\n", + __func__, chip->name, chip->remote_pid, + chip->irq_base + offset); + return; + } + + if (value & SMP2P_GPIO_NO_INT) { + value &= ~SMP2P_GPIO_NO_INT; + send_irq = false; + } else { + send_irq = true; + } + + if (value) { + data_set = 1 << offset; + data_clear = 0; + } else { + data_set = 0; + data_clear = 1 << offset; + } + + spin_lock_irqsave(&chip->shadow_lock, flags); + if (!chip->is_open) { + chip->in_shadow = true; + chip->shadow_value &= ~data_clear; + chip->shadow_value |= data_set; + spin_unlock_irqrestore(&chip->shadow_lock, flags); + return; + } + + if (chip->in_shadow) { + chip->in_shadow = false; + chip->shadow_value &= ~data_clear; + chip->shadow_value |= data_set; + ret = msm_smp2p_out_modify(chip->out_handle, + chip->shadow_value, 0x0, send_irq); + chip->shadow_value = 0x0; + } else { + ret = msm_smp2p_out_modify(chip->out_handle, + data_set, data_clear, send_irq); + } + spin_unlock_irqrestore(&chip->shadow_lock, flags); + + if (ret) + SMP2P_GPIO("'%s':%d gpio %d set to %d failed (%d)\n", + chip->name, chip->remote_pid, + chip->gpio.base + offset, value, ret); + else + SMP2P_GPIO("'%s':%d gpio %d set to %d\n", + chip->name, chip->remote_pid, + chip->gpio.base + offset, value); +} + +/** + * smp2p_direction_input - Sets GPIO direction to input. + * + * @cp: GPIO chip pointer + * @offset: Pin offset + * @returns: 0 for success; < 0 for failure + */ +static int smp2p_direction_input(struct gpio_chip *cp, unsigned offset) +{ + struct smp2p_chip_dev *chip; + + if (!cp) + return -ENODEV; + + chip = container_of(cp, struct smp2p_chip_dev, gpio); + if (!chip->is_inbound) + return -EPERM; + + return 0; +} + +/** + * smp2p_direction_output - Sets GPIO direction to output. + * + * @cp: GPIO chip pointer + * @offset: Pin offset + * @value: Direction + * @returns: 0 for success; < 0 for failure + */ +static int smp2p_direction_output(struct gpio_chip *cp, + unsigned offset, int value) +{ + struct smp2p_chip_dev *chip; + + if (!cp) + return -ENODEV; + + chip = container_of(cp, struct smp2p_chip_dev, gpio); + if (chip->is_inbound) + return -EPERM; + + return 0; +} + +/** + * smp2p_gpio_to_irq - Convert GPIO pin to virtual IRQ pin. + * + * @cp: GPIO chip pointer + * @offset: Pin offset + * @returns: >0 for virtual irq value; < 0 for failure + */ +static int smp2p_gpio_to_irq(struct gpio_chip *cp, unsigned offset) +{ + struct smp2p_chip_dev *chip; + + chip = container_of(cp, struct smp2p_chip_dev, gpio); + if (!cp || chip->irq_base <= 0) + return -ENODEV; + + return chip->irq_base + offset; +} + +/** + * smp2p_gpio_irq_mask_helper - Mask/Unmask interrupt. + * + * @d: IRQ data + * @mask: true to mask (disable), false to unmask (enable) + */ +static void smp2p_gpio_irq_mask_helper(struct irq_data *d, bool mask) +{ + struct smp2p_chip_dev *chip; + int offset; + unsigned long flags; + + chip = (struct smp2p_chip_dev *)irq_get_chip_data(d->irq); + if (!chip || chip->irq_base <= 0) + return; + + offset = d->irq - chip->irq_base; + spin_lock_irqsave(&chip->irq_lock, flags); + if (mask) + clear_bit(offset, chip->irq_enabled); + else + set_bit(offset, chip->irq_enabled); + spin_unlock_irqrestore(&chip->irq_lock, flags); +} + +/** + * smp2p_gpio_irq_mask - Mask interrupt. + * + * @d: IRQ data + */ +static void smp2p_gpio_irq_mask(struct irq_data *d) +{ + smp2p_gpio_irq_mask_helper(d, true); +} + +/** + * smp2p_gpio_irq_unmask - Unmask interrupt. + * + * @d: IRQ data + */ +static void smp2p_gpio_irq_unmask(struct irq_data *d) +{ + smp2p_gpio_irq_mask_helper(d, false); +} + +/** + * smp2p_gpio_irq_set_type - Set interrupt edge type. + * + * @d: IRQ data + * @type: Edge type for interrupt + * @returns 0 for success; < 0 for failure + */ +static int smp2p_gpio_irq_set_type(struct irq_data *d, unsigned int type) +{ + struct smp2p_chip_dev *chip; + int offset; + unsigned long flags; + int ret = 0; + + chip = (struct smp2p_chip_dev *)irq_get_chip_data(d->irq); + if (!chip) + return -ENODEV; + + if (chip->irq_base <= 0) { + SMP2P_ERR("%s: '%s':%d virqbase %d invalid\n", + __func__, chip->name, chip->remote_pid, + chip->irq_base); + return -ENODEV; + } + + offset = d->irq - chip->irq_base; + + spin_lock_irqsave(&chip->irq_lock, flags); + clear_bit(offset, chip->irq_rising_edge); + clear_bit(offset, chip->irq_falling_edge); + switch (type) { + case IRQ_TYPE_EDGE_RISING: + set_bit(offset, chip->irq_rising_edge); + break; + + case IRQ_TYPE_EDGE_FALLING: + set_bit(offset, chip->irq_falling_edge); + break; + + case IRQ_TYPE_NONE: + case IRQ_TYPE_DEFAULT: + case IRQ_TYPE_EDGE_BOTH: + set_bit(offset, chip->irq_rising_edge); + set_bit(offset, chip->irq_falling_edge); + break; + + default: + SMP2P_ERR("%s: unsupported interrupt type 0x%x\n", + __func__, type); + ret = -EINVAL; + break; + } + spin_unlock_irqrestore(&chip->irq_lock, flags); + return ret; +} + +/** + * smp2p_irq_map - Creates or updates binding of virtual IRQ + * + * @domain_ptr: Interrupt domain pointer + * @virq: Virtual IRQ + * @hw: Hardware IRQ (same as virq for nomap) + * @returns: 0 for success + */ +static int smp2p_irq_map(struct irq_domain *domain_ptr, unsigned int virq, + irq_hw_number_t hw) +{ + struct smp2p_chip_dev *chip; + + chip = domain_ptr->host_data; + if (!chip) { + SMP2P_ERR("%s: invalid domain ptr\n", __func__); + return -ENODEV; + } + + /* map chip structures to device */ + irq_set_lockdep_class(virq, &smp2p_gpio_lock_class); + irq_set_chip_and_handler(virq, &smp2p_gpio_irq_chip, + handle_level_irq); + irq_set_chip_data(virq, chip); + + return 0; +} + +static struct irq_chip smp2p_gpio_irq_chip = { + .name = "smp2p_gpio", + .irq_mask = smp2p_gpio_irq_mask, + .irq_unmask = smp2p_gpio_irq_unmask, + .irq_set_type = smp2p_gpio_irq_set_type, +}; + +/* No-map interrupt Domain */ +static const struct irq_domain_ops smp2p_irq_domain_ops = { + .map = smp2p_irq_map, +}; + +/** + * msm_summary_irq_handler - Handles inbound entry change notification. + * + * @chip: GPIO chip pointer + * @entry: Change notification data + * + * Whenever an entry changes, this callback is triggered to determine + * which bits changed and if the corresponding interrupts need to be + * triggered. + */ +static void msm_summary_irq_handler(struct smp2p_chip_dev *chip, + struct msm_smp2p_update_notif *entry) +{ + int i; + uint32_t cur_val; + uint32_t prev_val; + uint32_t edge; + unsigned long flags; + bool trigger_interrrupt; + bool irq_rising; + bool irq_falling; + + cur_val = entry->current_value; + prev_val = entry->previous_value; + + if (chip->irq_base <= 0) + return; + + SMP2P_GPIO("'%s':%d GPIO Summary IRQ Change %08x->%08x\n", + chip->name, chip->remote_pid, prev_val, cur_val); + + for (i = 0; i < SMP2P_BITS_PER_ENTRY; ++i) { + spin_lock_irqsave(&chip->irq_lock, flags); + trigger_interrrupt = false; + edge = (prev_val & 0x1) << 1 | (cur_val & 0x1); + irq_rising = test_bit(i, chip->irq_rising_edge); + irq_falling = test_bit(i, chip->irq_falling_edge); + + if (test_bit(i, chip->irq_enabled)) { + if (edge == 0x1 && irq_rising) + /* 0->1 transition */ + trigger_interrrupt = true; + else if (edge == 0x2 && irq_falling) + /* 1->0 transition */ + trigger_interrrupt = true; + } else { + SMP2P_GPIO( + "'%s':%d GPIO bit %d virq %d (%s,%s) - edge %s disabled\n", + chip->name, chip->remote_pid, i, + chip->irq_base + i, + edge_name_rising[irq_rising], + edge_name_falling[irq_falling], + edge_names[edge]); + } + spin_unlock_irqrestore(&chip->irq_lock, flags); + + if (trigger_interrrupt) { + SMP2P_INFO( + "'%s':%d GPIO bit %d virq %d (%s,%s) - edge %s triggering\n", + chip->name, chip->remote_pid, i, + chip->irq_base + i, + edge_name_rising[irq_rising], + edge_name_falling[irq_falling], + edge_names[edge]); + (void)generic_handle_irq(chip->irq_base + i); + } + + cur_val >>= 1; + prev_val >>= 1; + } +} + +/** + * Adds an interrupt domain based upon the DT node. + * + * @chip: pointer to GPIO chip + * @node: pointer to Device Tree node + */ +static void smp2p_add_irq_domain(struct smp2p_chip_dev *chip, + struct device_node *node) +{ + int irq_base; + + /* map GPIO pins to interrupts */ + chip->irq_domain = irq_domain_add_linear(node, SMP2P_BITS_PER_ENTRY, + &smp2p_irq_domain_ops, chip); + if (!chip->irq_domain) { + SMP2P_ERR("%s: unable to create interrupt domain '%s':%d\n", + __func__, chip->name, chip->remote_pid); + goto domain_fail; + } + + /* alloc a contiguous set of virt irqs from anywhere in the irq space */ + irq_base = irq_alloc_descs_from(0, SMP2P_BITS_PER_ENTRY, of_node_to_nid( + irq_domain_get_of_node(chip->irq_domain))); + if (irq_base < 0) { + SMP2P_ERR("alloc virt irqs failed:%d name:%s pid%d\n", irq_base, + chip->name, chip->remote_pid); + goto irq_alloc_fail; + } + + /* map the allocated irqs to gpios */ + irq_domain_associate_many(chip->irq_domain, irq_base, 0, + SMP2P_BITS_PER_ENTRY); + + chip->irq_base = irq_base; + SMP2P_DBG("create mapping:%d naem:%s pid:%d\n", chip->irq_base, + chip->name, chip->remote_pid); + return; + +irq_alloc_fail: + irq_domain_remove(chip->irq_domain); +domain_fail: + return; +} + +/** + * Notifier function passed into smp2p API for out bound entries. + * + * @self: Pointer to calling notifier block + * @event: Event + * @data: Event-specific data + * @returns: 0 + */ +static int smp2p_gpio_out_notify(struct notifier_block *self, + unsigned long event, void *data) +{ + struct smp2p_chip_dev *chip; + + chip = container_of(self, struct smp2p_chip_dev, out_notifier); + + switch (event) { + case SMP2P_OPEN: + chip->is_open = 1; + SMP2P_GPIO("%s: Opened out '%s':%d in_shadow[%d]\n", __func__, + chip->name, chip->remote_pid, chip->in_shadow); + if (chip->in_shadow) + schedule_work(&chip->shadow_work); + break; + case SMP2P_ENTRY_UPDATE: + break; + default: + SMP2P_ERR("%s: Unknown event\n", __func__); + break; + } + return 0; +} + +/** + * Notifier function passed into smp2p API for in bound entries. + * + * @self: Pointer to calling notifier block + * @event: Event + * @data: Event-specific data + * @returns: 0 + */ +static int smp2p_gpio_in_notify(struct notifier_block *self, + unsigned long event, void *data) +{ + struct smp2p_chip_dev *chip; + + chip = container_of(self, struct smp2p_chip_dev, in_notifier); + + switch (event) { + case SMP2P_OPEN: + chip->is_open = 1; + SMP2P_GPIO("%s: Opened in '%s':%d\n", __func__, + chip->name, chip->remote_pid); + break; + case SMP2P_ENTRY_UPDATE: + msm_summary_irq_handler(chip, data); + break; + default: + SMP2P_ERR("%s: Unknown event\n", __func__); + break; + } + return 0; +} + +/** + * smp2p_gpio_shadow_worker - Handles shadow updates of an entry. + * + * @work: Work Item scheduled to handle the shadow updates. + */ +static void smp2p_gpio_shadow_worker(struct work_struct *work) +{ + struct smp2p_chip_dev *chip; + int ret; + unsigned long flags; + + chip = container_of(work, struct smp2p_chip_dev, shadow_work); + spin_lock_irqsave(&chip->shadow_lock, flags); + if (chip->in_shadow) { + ret = msm_smp2p_out_modify(chip->out_handle, + chip->shadow_value, 0x0, true); + + if (ret) + SMP2P_GPIO("'%s':%d shadow val[0x%x] failed(%d)\n", + chip->name, chip->remote_pid, + chip->shadow_value, ret); + else + SMP2P_GPIO("'%s':%d shadow val[0x%x]\n", + chip->name, chip->remote_pid, + chip->shadow_value); + chip->shadow_value = 0; + chip->in_shadow = false; + } + spin_unlock_irqrestore(&chip->shadow_lock, flags); +} + +/** + * Device tree probe function. + * + * @pdev: Pointer to device tree data. + * @returns: 0 on success; -ENODEV otherwise + * + * Called for each smp2pgpio entry in the device tree. + */ +static int smp2p_gpio_probe(struct platform_device *pdev) +{ + struct device_node *node; + char *key; + struct smp2p_chip_dev *chip; + const char *name_tmp; + unsigned long flags; + bool is_test_entry = false; + int ret; + + chip = kzalloc(sizeof(struct smp2p_chip_dev), GFP_KERNEL); + if (!chip) { + SMP2P_ERR("%s: out of memory\n", __func__); + ret = -ENOMEM; + goto fail; + } + spin_lock_init(&chip->irq_lock); + spin_lock_init(&chip->shadow_lock); + INIT_WORK(&chip->shadow_work, smp2p_gpio_shadow_worker); + + /* parse device tree */ + node = pdev->dev.of_node; + key = "qcom,entry-name"; + ret = of_property_read_string(node, key, &name_tmp); + if (ret) { + SMP2P_ERR("%s: missing DT key '%s'\n", __func__, key); + goto fail; + } + strlcpy(chip->name, name_tmp, sizeof(chip->name)); + + key = "qcom,remote-pid"; + ret = of_property_read_u32(node, key, &chip->remote_pid); + if (ret) { + SMP2P_ERR("%s: missing DT key '%s'\n", __func__, key); + goto fail; + } + + key = "qcom,is-inbound"; + chip->is_inbound = of_property_read_bool(node, key); + + /* create virtual GPIO controller */ + chip->gpio.label = chip->name; + chip->gpio.dev = &pdev->dev; + chip->gpio.owner = THIS_MODULE; + chip->gpio.direction_input = smp2p_direction_input, + chip->gpio.get = smp2p_get_value; + chip->gpio.direction_output = smp2p_direction_output, + chip->gpio.set = smp2p_set_value; + chip->gpio.to_irq = smp2p_gpio_to_irq, + chip->gpio.base = -1; /* use dynamic GPIO pin allocation */ + chip->gpio.ngpio = SMP2P_BITS_PER_ENTRY; + ret = gpiochip_add(&chip->gpio); + if (ret) { + SMP2P_ERR("%s: unable to register GPIO '%s' ret %d\n", + __func__, chip->name, ret); + goto fail; + } + + /* + * Test entries opened by GPIO Test conflict with loopback + * support, so the test entries must be explicitly opened + * in the unit test framework. + */ + if (strncmp("smp2p", chip->name, SMP2P_MAX_ENTRY_NAME) == 0) + is_test_entry = true; + + if (!chip->is_inbound) { + chip->out_notifier.notifier_call = smp2p_gpio_out_notify; + if (!is_test_entry) { + ret = msm_smp2p_out_open(chip->remote_pid, chip->name, + &chip->out_notifier, + &chip->out_handle); + if (ret < 0) + goto error; + } + } else { + chip->in_notifier.notifier_call = smp2p_gpio_in_notify; + if (!is_test_entry) { + ret = msm_smp2p_in_register(chip->remote_pid, + chip->name, + &chip->in_notifier); + if (ret < 0) + goto error; + } + } + + spin_lock_irqsave(&smp2p_entry_lock_lha1, flags); + list_add(&chip->entry_list, &smp2p_entry_list); + spin_unlock_irqrestore(&smp2p_entry_lock_lha1, flags); + + /* + * Create interrupt domain - note that chip can't be removed from the + * interrupt domain, so chip cannot be deleted after this point. + */ + if (chip->is_inbound) + smp2p_add_irq_domain(chip, node); + else + chip->irq_base = -1; + + SMP2P_GPIO("%s: added %s%s entry '%s':%d gpio %d irq %d", + __func__, + is_test_entry ? "test " : "", + chip->is_inbound ? "in" : "out", + chip->name, chip->remote_pid, + chip->gpio.base, chip->irq_base); + + return 0; +error: + gpiochip_remove(&chip->gpio); + +fail: + kfree(chip); + return ret; +} + +/** + * smp2p_gpio_open_close - Opens or closes entry. + * + * @entry: Entry to open or close + * @do_open: true = open port; false = close + */ +static void smp2p_gpio_open_close(struct smp2p_chip_dev *entry, + bool do_open) +{ + int ret; + + if (do_open) { + /* open entry */ + if (entry->is_inbound) + ret = msm_smp2p_in_register(entry->remote_pid, + entry->name, &entry->in_notifier); + else + ret = msm_smp2p_out_open(entry->remote_pid, + entry->name, &entry->out_notifier, + &entry->out_handle); + SMP2P_GPIO("%s: opened %s '%s':%d ret %d\n", + __func__, + entry->is_inbound ? "in" : "out", + entry->name, entry->remote_pid, + ret); + } else { + /* close entry */ + if (entry->is_inbound) + ret = msm_smp2p_in_unregister(entry->remote_pid, + entry->name, &entry->in_notifier); + else + ret = msm_smp2p_out_close(&entry->out_handle); + entry->is_open = false; + SMP2P_GPIO("%s: closed %s '%s':%d ret %d\n", + __func__, + entry->is_inbound ? "in" : "out", + entry->name, entry->remote_pid, ret); + } +} + +/** + * smp2p_gpio_open_test_entry - Opens or closes test entries for unit testing. + * + * @name: Name of the entry + * @remote_pid: Remote processor ID + * @do_open: true = open port; false = close + */ +void smp2p_gpio_open_test_entry(const char *name, int remote_pid, bool do_open) +{ + struct smp2p_chip_dev *entry; + struct smp2p_chip_dev *start_entry; + unsigned long flags; + + spin_lock_irqsave(&smp2p_entry_lock_lha1, flags); + if (list_empty(&smp2p_entry_list)) { + spin_unlock_irqrestore(&smp2p_entry_lock_lha1, flags); + return; + } + start_entry = list_first_entry(&smp2p_entry_list, + struct smp2p_chip_dev, + entry_list); + entry = start_entry; + do { + if (!strncmp(entry->name, name, SMP2P_MAX_ENTRY_NAME) + && entry->remote_pid == remote_pid) { + /* found entry to change */ + spin_unlock_irqrestore(&smp2p_entry_lock_lha1, flags); + smp2p_gpio_open_close(entry, do_open); + spin_lock_irqsave(&smp2p_entry_lock_lha1, flags); + } + list_rotate_left(&smp2p_entry_list); + entry = list_first_entry(&smp2p_entry_list, + struct smp2p_chip_dev, + entry_list); + } while (entry != start_entry); + spin_unlock_irqrestore(&smp2p_entry_lock_lha1, flags); +} + +static struct of_device_id msm_smp2p_match_table[] = { + {.compatible = "qcom,smp2pgpio", }, + {}, +}; + +static struct platform_driver smp2p_gpio_driver = { + .probe = smp2p_gpio_probe, + .driver = { + .name = "smp2pgpio", + .owner = THIS_MODULE, + .of_match_table = msm_smp2p_match_table, + }, +}; + +static int smp2p_init(void) +{ + INIT_LIST_HEAD(&smp2p_entry_list); + return platform_driver_register(&smp2p_gpio_driver); +} +module_init(smp2p_init); + +static void __exit smp2p_exit(void) +{ + platform_driver_unregister(&smp2p_gpio_driver); +} +module_exit(smp2p_exit); + +MODULE_DESCRIPTION("SMP2P GPIO"); +MODULE_LICENSE("GPL v2"); --- /dev/null 2019-10-24 16:47:25.704025805 +0200 +++ linux-4.4.115-fbx/drivers/gpio/qpnp-pin.c 2019-01-22 16:16:23.215243798 +0100 @@ -0,0 +1,1714 @@ +/* Copyright (c) 2012-2017, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define pr_fmt(fmt) "%s: " fmt, __func__ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define Q_REG_ADDR(q_spec, reg_index) \ + ((q_spec)->offset + reg_index) + +#define Q_REG_STATUS1 0x8 +#define Q_REG_STATUS1_VAL_MASK 0x1 +#define Q_REG_STATUS1_GPIO_EN_REV0_MASK 0x2 +#define Q_REG_STATUS1_GPIO_EN_MASK 0x80 +#define Q_REG_STATUS1_MPP_EN_MASK 0x80 + +#define Q_NUM_CTL_REGS 0xD + +/* revision registers base address offsets */ +#define Q_REG_DIG_MINOR_REV 0x0 +#define Q_REG_DIG_MAJOR_REV 0x1 +#define Q_REG_ANA_MINOR_REV 0x2 + +/* type registers base address offsets */ +#define Q_REG_TYPE 0x4 +#define Q_REG_SUBTYPE 0x5 + +/* gpio peripheral type and subtype values */ +#define Q_GPIO_TYPE 0x10 +#define Q_GPIO_SUBTYPE_GPIO_4CH 0x1 +#define Q_GPIO_SUBTYPE_GPIOC_4CH 0x5 +#define Q_GPIO_SUBTYPE_GPIO_8CH 0x9 +#define Q_GPIO_SUBTYPE_GPIOC_8CH 0xD +#define Q_GPIO_SUBTYPE_GPIO_LV 0x10 +#define Q_GPIO_SUBTYPE_GPIO_MV 0x11 + +/* mpp peripheral type and subtype values */ +#define Q_MPP_TYPE 0x11 +#define Q_MPP_SUBTYPE_4CH_NO_ANA_OUT 0x3 +#define Q_MPP_SUBTYPE_ULT_4CH_NO_ANA_OUT 0x4 +#define Q_MPP_SUBTYPE_4CH_NO_SINK 0x5 +#define Q_MPP_SUBTYPE_ULT_4CH_NO_SINK 0x6 +#define Q_MPP_SUBTYPE_4CH_FULL_FUNC 0x7 +#define Q_MPP_SUBTYPE_8CH_FULL_FUNC 0xF + +/* control register base address offsets */ +#define Q_REG_MODE_CTL 0x40 +#define Q_REG_DIG_VIN_CTL 0x41 +#define Q_REG_DIG_PULL_CTL 0x42 +#define Q_REG_DIG_IN_CTL 0x43 +#define Q_REG_DIG_OUT_SRC_CTL 0x44 +#define Q_REG_DIG_OUT_CTL 0x45 +#define Q_REG_EN_CTL 0x46 +#define Q_REG_AOUT_CTL 0x48 +#define Q_REG_AIN_CTL 0x4A +#define Q_REG_APASS_SEL_CTL 0x4A +#define Q_REG_SINK_CTL 0x4C + +/* control register regs array indices */ +#define Q_REG_I_MODE_CTL 0 +#define Q_REG_I_DIG_VIN_CTL 1 +#define Q_REG_I_DIG_PULL_CTL 2 +#define Q_REG_I_DIG_IN_CTL 3 +#define Q_REG_I_DIG_OUT_SRC_CTL 4 +#define Q_REG_I_DIG_OUT_CTL 5 +#define Q_REG_I_EN_CTL 6 +#define Q_REG_I_AOUT_CTL 8 +#define Q_REG_I_APASS_SEL_CTL 10 +#define Q_REG_I_AIN_CTL 10 +#define Q_REG_I_SINK_CTL 12 + +/* control reg: mode */ +#define Q_REG_OUT_INVERT_SHIFT 0 +#define Q_REG_OUT_INVERT_MASK 0x1 +#define Q_REG_SRC_SEL_SHIFT 1 +#define Q_REG_SRC_SEL_MASK 0xE +#define Q_REG_MODE_SEL_SHIFT 4 +#define Q_REG_MODE_SEL_MASK 0x70 +#define Q_REG_LV_MV_MODE_SEL_SHIFT 0 +#define Q_REG_LV_MV_MODE_SEL_MASK 0x3 + +/* control reg: dig_out_src (GPIO LV/MV only) */ +#define Q_REG_DIG_OUT_SRC_SRC_SEL_SHIFT 0 +#define Q_REG_DIG_OUT_SRC_SRC_SEL_MASK 0xF +#define Q_REG_DIG_OUT_SRC_INVERT_SHIFT 7 +#define Q_REG_DIG_OUT_SRC_INVERT_MASK 0x80 + +/* control reg: dig_vin */ +#define Q_REG_VIN_SHIFT 0 +#define Q_REG_VIN_MASK 0x7 + +/* control reg: dig_pull */ +#define Q_REG_PULL_SHIFT 0 +#define Q_REG_PULL_MASK 0x7 + +/* control reg: dig_out */ +#define Q_REG_OUT_STRENGTH_SHIFT 0 +#define Q_REG_OUT_STRENGTH_MASK 0x3 +#define Q_REG_OUT_TYPE_SHIFT 4 +#define Q_REG_OUT_TYPE_MASK 0x30 + +/* control reg: dig_in_ctl */ +#define Q_REG_DTEST_SEL_SHIFT 0 +#define Q_REG_DTEST_SEL_MASK 0xF +#define Q_REG_LV_MV_DTEST_SEL_CFG_SHIFT 0 +#define Q_REG_LV_MV_DTEST_SEL_CFG_MASK 0x7 +#define Q_REG_LV_MV_DTEST_SEL_EN_SHIFT 7 +#define Q_REG_LV_MV_DTEST_SEL_EN_MASK 0x80 + +/* control reg: en */ +#define Q_REG_MASTER_EN_SHIFT 7 +#define Q_REG_MASTER_EN_MASK 0x80 + +/* control reg: ana_out */ +#define Q_REG_AOUT_REF_SHIFT 0 +#define Q_REG_AOUT_REF_MASK 0x7 + +/* control reg: ana_in */ +#define Q_REG_AIN_ROUTE_SHIFT 0 +#define Q_REG_AIN_ROUTE_MASK 0x7 + +/* control reg: sink */ +#define Q_REG_CS_OUT_SHIFT 0 +#define Q_REG_CS_OUT_MASK 0x7 + +/* control ref: apass_sel */ +#define Q_REG_APASS_SEL_SHIFT 0 +#define Q_REG_APASS_SEL_MASK 0x3 + +enum qpnp_pin_param_type { + Q_PIN_CFG_MODE, + Q_PIN_CFG_OUTPUT_TYPE, + Q_PIN_CFG_INVERT, + Q_PIN_CFG_PULL, + Q_PIN_CFG_VIN_SEL, + Q_PIN_CFG_OUT_STRENGTH, + Q_PIN_CFG_SRC_SEL, + Q_PIN_CFG_MASTER_EN, + Q_PIN_CFG_AOUT_REF, + Q_PIN_CFG_AIN_ROUTE, + Q_PIN_CFG_CS_OUT, + Q_PIN_CFG_APASS_SEL, + Q_PIN_CFG_DTEST_SEL, + Q_PIN_CFG_INVALID, +}; + +#define Q_NUM_PARAMS Q_PIN_CFG_INVALID + +/* param error checking */ +#define QPNP_PIN_GPIO_MODE_INVALID 3 +#define QPNP_PIN_GPIO_LV_MV_MODE_INVALID 4 +#define QPNP_PIN_MPP_MODE_INVALID 7 +#define QPNP_PIN_INVERT_INVALID 2 +#define QPNP_PIN_OUT_BUF_INVALID 3 +#define QPNP_PIN_GPIO_LV_MV_OUT_BUF_INVALID 4 +#define QPNP_PIN_VIN_4CH_INVALID 5 +#define QPNP_PIN_VIN_8CH_INVALID 8 +#define QPNP_PIN_GPIO_LV_VIN_INVALID 1 +#define QPNP_PIN_GPIO_MV_VIN_INVALID 2 +#define QPNP_PIN_GPIO_PULL_INVALID 6 +#define QPNP_PIN_MPP_PULL_INVALID 4 +#define QPNP_PIN_OUT_STRENGTH_INVALID 4 +#define QPNP_PIN_SRC_INVALID 8 +#define QPNP_PIN_GPIO_LV_MV_SRC_INVALID 16 +#define QPNP_PIN_MASTER_INVALID 2 +#define QPNP_PIN_AOUT_REF_INVALID 8 +#define QPNP_PIN_AIN_ROUTE_INVALID 8 +#define QPNP_PIN_CS_OUT_INVALID 8 +#define QPNP_PIN_APASS_SEL_INVALID 4 +#define QPNP_PIN_DTEST_SEL_INVALID 4 + +struct qpnp_pin_spec { + uint8_t slave; /* 0-15 */ + uint16_t offset; /* 0-255 */ + uint32_t gpio_chip_idx; /* offset from gpio_chip base */ + uint32_t pmic_pin; /* PMIC pin number */ + int irq; /* logical IRQ number */ + u8 regs[Q_NUM_CTL_REGS]; /* Control regs */ + u8 num_ctl_regs; /* usable number on this pin */ + u8 type; /* peripheral type */ + u8 subtype; /* peripheral subtype */ + u8 dig_major_rev; + struct device_node *node; + enum qpnp_pin_param_type params[Q_NUM_PARAMS]; + struct qpnp_pin_chip *q_chip; +}; + +struct qpnp_pin_chip { + struct gpio_chip gpio_chip; + struct platform_device *pdev; + struct regmap *regmap; + struct qpnp_pin_spec **pmic_pins; + struct qpnp_pin_spec **chip_gpios; + uint32_t pmic_pin_lowest; + uint32_t pmic_pin_highest; + struct device_node *int_ctrl; + struct list_head chip_list; + struct dentry *dfs_dir; + bool chip_registered; +}; + +static LIST_HEAD(qpnp_pin_chips); +static DEFINE_MUTEX(qpnp_pin_chips_lock); + +static inline void qpnp_pmic_pin_set_spec(struct qpnp_pin_chip *q_chip, + uint32_t pmic_pin, + struct qpnp_pin_spec *spec) +{ + q_chip->pmic_pins[pmic_pin - q_chip->pmic_pin_lowest] = spec; +} + +static inline struct qpnp_pin_spec *qpnp_pmic_pin_get_spec( + struct qpnp_pin_chip *q_chip, + uint32_t pmic_pin) +{ + if (pmic_pin < q_chip->pmic_pin_lowest || + pmic_pin > q_chip->pmic_pin_highest) + return NULL; + + return q_chip->pmic_pins[pmic_pin - q_chip->pmic_pin_lowest]; +} + +static inline struct qpnp_pin_spec *qpnp_chip_gpio_get_spec( + struct qpnp_pin_chip *q_chip, + uint32_t chip_gpio) +{ + if (chip_gpio >= q_chip->gpio_chip.ngpio) + return NULL; + + return q_chip->chip_gpios[chip_gpio]; +} + +static inline void qpnp_chip_gpio_set_spec(struct qpnp_pin_chip *q_chip, + uint32_t chip_gpio, + struct qpnp_pin_spec *spec) +{ + q_chip->chip_gpios[chip_gpio] = spec; +} + +static bool is_gpio_lv_mv(struct qpnp_pin_spec *q_spec) +{ + if ((q_spec->type == Q_GPIO_TYPE) && + (q_spec->subtype == Q_GPIO_SUBTYPE_GPIO_LV || + q_spec->subtype == Q_GPIO_SUBTYPE_GPIO_MV)) + return true; + + return false; +} + +/* + * Determines whether a specified param's configuration is correct. + * This check is two tier. First a check is done whether the hardware + * supports this param and value requested. The second check validates + * that the configuration is correct, given the fact that the hardware + * supports it. + * + * Returns + * -ENXIO is the hardware does not support this param. + * -EINVAL if the the hardware does support this param, but the + * requested value is outside the supported range. + */ +static int qpnp_pin_check_config(enum qpnp_pin_param_type idx, + struct qpnp_pin_spec *q_spec, uint32_t val) +{ + u8 subtype = q_spec->subtype; + + switch (idx) { + case Q_PIN_CFG_MODE: + if (q_spec->type == Q_GPIO_TYPE) { + if (is_gpio_lv_mv(q_spec)) { + if (val >= QPNP_PIN_GPIO_LV_MV_MODE_INVALID) + return -EINVAL; + } else if (val >= QPNP_PIN_GPIO_MODE_INVALID) { + return -EINVAL; + } + } else if (q_spec->type == Q_MPP_TYPE) { + if (val >= QPNP_PIN_MPP_MODE_INVALID) + return -EINVAL; + if ((subtype == Q_MPP_SUBTYPE_ULT_4CH_NO_ANA_OUT || + subtype == Q_MPP_SUBTYPE_ULT_4CH_NO_SINK) && + (val == QPNP_PIN_MODE_BIDIR)) + return -ENXIO; + } + break; + case Q_PIN_CFG_OUTPUT_TYPE: + if (q_spec->type != Q_GPIO_TYPE) + return -ENXIO; + if ((val == QPNP_PIN_OUT_BUF_OPEN_DRAIN_NMOS || + val == QPNP_PIN_OUT_BUF_OPEN_DRAIN_PMOS) && + (subtype == Q_GPIO_SUBTYPE_GPIOC_4CH || + (subtype == Q_GPIO_SUBTYPE_GPIOC_8CH))) + return -EINVAL; + else if (is_gpio_lv_mv(q_spec) && + val >= QPNP_PIN_GPIO_LV_MV_OUT_BUF_INVALID) + return -EINVAL; + else if (val >= QPNP_PIN_OUT_BUF_INVALID) + return -EINVAL; + break; + case Q_PIN_CFG_INVERT: + if (val >= QPNP_PIN_INVERT_INVALID) + return -EINVAL; + break; + case Q_PIN_CFG_PULL: + if (q_spec->type == Q_GPIO_TYPE && + val >= QPNP_PIN_GPIO_PULL_INVALID) + return -EINVAL; + if (q_spec->type == Q_MPP_TYPE) { + if (val >= QPNP_PIN_MPP_PULL_INVALID) + return -EINVAL; + if (subtype == Q_MPP_SUBTYPE_ULT_4CH_NO_ANA_OUT || + subtype == Q_MPP_SUBTYPE_ULT_4CH_NO_SINK) + return -ENXIO; + } + break; + case Q_PIN_CFG_VIN_SEL: + if (is_gpio_lv_mv(q_spec)) { + if (subtype == Q_GPIO_SUBTYPE_GPIO_LV) { + if (val >= QPNP_PIN_GPIO_LV_VIN_INVALID) + return -EINVAL; + } else { + if (val >= QPNP_PIN_GPIO_MV_VIN_INVALID) + return -EINVAL; + } + } else if (val >= QPNP_PIN_VIN_8CH_INVALID) { + return -EINVAL; + } else if (val >= QPNP_PIN_VIN_4CH_INVALID) { + if (q_spec->type == Q_GPIO_TYPE && + (subtype == Q_GPIO_SUBTYPE_GPIO_4CH || + subtype == Q_GPIO_SUBTYPE_GPIOC_4CH)) + return -EINVAL; + if (q_spec->type == Q_MPP_TYPE && + (subtype == Q_MPP_SUBTYPE_4CH_NO_ANA_OUT || + subtype == Q_MPP_SUBTYPE_4CH_NO_SINK || + subtype == Q_MPP_SUBTYPE_4CH_FULL_FUNC || + subtype == Q_MPP_SUBTYPE_ULT_4CH_NO_ANA_OUT || + subtype == Q_MPP_SUBTYPE_ULT_4CH_NO_SINK)) + return -EINVAL; + } + break; + case Q_PIN_CFG_OUT_STRENGTH: + if (q_spec->type != Q_GPIO_TYPE) + return -ENXIO; + if (val >= QPNP_PIN_OUT_STRENGTH_INVALID || + val == 0) + return -EINVAL; + break; + case Q_PIN_CFG_SRC_SEL: + if (q_spec->type == Q_MPP_TYPE && + (val == QPNP_PIN_SEL_FUNC_1 || + val == QPNP_PIN_SEL_FUNC_2)) + return -EINVAL; + if (is_gpio_lv_mv(q_spec)) { + if (val >= QPNP_PIN_GPIO_LV_MV_SRC_INVALID) + return -EINVAL; + } else if (val >= QPNP_PIN_SRC_INVALID) { + return -EINVAL; + } + break; + case Q_PIN_CFG_MASTER_EN: + if (val >= QPNP_PIN_MASTER_INVALID) + return -EINVAL; + break; + case Q_PIN_CFG_AOUT_REF: + if (q_spec->type != Q_MPP_TYPE) + return -ENXIO; + if (subtype == Q_MPP_SUBTYPE_4CH_NO_ANA_OUT || + subtype == Q_MPP_SUBTYPE_ULT_4CH_NO_ANA_OUT) + return -ENXIO; + if (val >= QPNP_PIN_AOUT_REF_INVALID) + return -EINVAL; + break; + case Q_PIN_CFG_AIN_ROUTE: + if (q_spec->type != Q_MPP_TYPE) + return -ENXIO; + if (val >= QPNP_PIN_AIN_ROUTE_INVALID) + return -EINVAL; + break; + case Q_PIN_CFG_CS_OUT: + if (q_spec->type != Q_MPP_TYPE) + return -ENXIO; + if (subtype == Q_MPP_SUBTYPE_4CH_NO_SINK || + subtype == Q_MPP_SUBTYPE_ULT_4CH_NO_SINK) + return -ENXIO; + if (val >= QPNP_PIN_CS_OUT_INVALID) + return -EINVAL; + break; + case Q_PIN_CFG_APASS_SEL: + if (!is_gpio_lv_mv(q_spec)) + return -ENXIO; + if (val >= QPNP_PIN_APASS_SEL_INVALID) + return -EINVAL; + break; + case Q_PIN_CFG_DTEST_SEL: + if (val > QPNP_PIN_DTEST_SEL_INVALID) + return -EINVAL; + break; + default: + pr_err("invalid param type %u specified\n", idx); + return -EINVAL; + } + return 0; +} + +#define Q_CHK_INVALID(idx, q_spec, val) \ + (qpnp_pin_check_config(idx, q_spec, val) == -EINVAL) + +static int qpnp_pin_check_constraints(struct qpnp_pin_spec *q_spec, + struct qpnp_pin_cfg *param) +{ + int pin = q_spec->pmic_pin; + const char *name; + + name = (q_spec->type == Q_GPIO_TYPE) ? "gpio" : "mpp"; + + if (Q_CHK_INVALID(Q_PIN_CFG_MODE, q_spec, param->mode)) + pr_err("invalid direction value %d for %s %d\n", + param->mode, name, pin); + else if (Q_CHK_INVALID(Q_PIN_CFG_INVERT, q_spec, param->invert)) + pr_err("invalid invert polarity value %d for %s %d\n", + param->invert, name, pin); + else if (Q_CHK_INVALID(Q_PIN_CFG_SRC_SEL, q_spec, param->src_sel)) + pr_err("invalid source select value %d for %s %d\n", + param->src_sel, name, pin); + else if (Q_CHK_INVALID(Q_PIN_CFG_OUT_STRENGTH, + q_spec, param->out_strength)) + pr_err("invalid out strength value %d for %s %d\n", + param->out_strength, name, pin); + else if (Q_CHK_INVALID(Q_PIN_CFG_OUTPUT_TYPE, + q_spec, param->output_type)) + pr_err("invalid out type value %d for %s %d\n", + param->output_type, name, pin); + else if (Q_CHK_INVALID(Q_PIN_CFG_VIN_SEL, q_spec, param->vin_sel)) + pr_err("invalid vin select %d value for %s %d\n", + param->vin_sel, name, pin); + else if (Q_CHK_INVALID(Q_PIN_CFG_PULL, q_spec, param->pull)) + pr_err("invalid pull value %d for pin %s %d\n", + param->pull, name, pin); + else if (Q_CHK_INVALID(Q_PIN_CFG_MASTER_EN, q_spec, param->master_en)) + pr_err("invalid master_en value %d for %s %d\n", + param->master_en, name, pin); + else if (Q_CHK_INVALID(Q_PIN_CFG_AOUT_REF, q_spec, param->aout_ref)) + pr_err("invalid aout_reg value %d for %s %d\n", + param->aout_ref, name, pin); + else if (Q_CHK_INVALID(Q_PIN_CFG_AIN_ROUTE, q_spec, param->ain_route)) + pr_err("invalid ain_route value %d for %s %d\n", + param->ain_route, name, pin); + else if (Q_CHK_INVALID(Q_PIN_CFG_CS_OUT, q_spec, param->cs_out)) + pr_err("invalid cs_out value %d for %s %d\n", + param->cs_out, name, pin); + else if (Q_CHK_INVALID(Q_PIN_CFG_APASS_SEL, q_spec, param->apass_sel)) + pr_err("invalid apass_sel value %d for %s %d\n", + param->apass_sel, name, pin); + else if (Q_CHK_INVALID(Q_PIN_CFG_DTEST_SEL, q_spec, param->dtest_sel)) + pr_err("invalid dtest_sel value %d for %s %d\n", + param->dtest_sel, name, pin); + else + return 0; + + return -EINVAL; +} + +static inline u8 q_reg_get(u8 *reg, int shift, int mask) +{ + return (*reg & mask) >> shift; +} + +static inline void q_reg_set(u8 *reg, int shift, int mask, int value) +{ + *reg |= (value << shift) & mask; +} + +static inline void q_reg_clr_set(u8 *reg, int shift, int mask, int value) +{ + *reg &= ~mask; + *reg |= (value << shift) & mask; +} + +/* + * Calculate the minimum number of registers that must be read / written + * in order to satisfy the full feature set of the given pin. + */ +static int qpnp_pin_ctl_regs_init(struct qpnp_pin_spec *q_spec) +{ + if (q_spec->type == Q_GPIO_TYPE) { + if (is_gpio_lv_mv(q_spec)) + q_spec->num_ctl_regs = 11; + else + q_spec->num_ctl_regs = 7; + } else if (q_spec->type == Q_MPP_TYPE) { + switch (q_spec->subtype) { + case Q_MPP_SUBTYPE_4CH_NO_SINK: + case Q_MPP_SUBTYPE_ULT_4CH_NO_SINK: + q_spec->num_ctl_regs = 12; + break; + case Q_MPP_SUBTYPE_4CH_NO_ANA_OUT: + case Q_MPP_SUBTYPE_ULT_4CH_NO_ANA_OUT: + case Q_MPP_SUBTYPE_4CH_FULL_FUNC: + case Q_MPP_SUBTYPE_8CH_FULL_FUNC: + q_spec->num_ctl_regs = 13; + break; + default: + pr_err("Invalid MPP subtype 0x%x\n", q_spec->subtype); + return -EINVAL; + } + } else { + pr_err("Invalid type 0x%x\n", q_spec->type); + return -EINVAL; + } + return 0; +} + +static int qpnp_pin_read_regs(struct qpnp_pin_chip *q_chip, + struct qpnp_pin_spec *q_spec) +{ + int bytes_left = q_spec->num_ctl_regs; + int rc; + char *buf_p = &q_spec->regs[0]; + u16 reg_addr = Q_REG_ADDR(q_spec, Q_REG_MODE_CTL); + + while (bytes_left > 0) { + rc = regmap_bulk_read(q_chip->regmap, reg_addr, buf_p, + bytes_left < 8 ? bytes_left : 8); + if (rc) + return rc; + bytes_left -= 8; + buf_p += 8; + reg_addr += 8; + } + return 0; +} + +static int qpnp_pin_write_regs(struct qpnp_pin_chip *q_chip, + struct qpnp_pin_spec *q_spec) +{ + int bytes_left = q_spec->num_ctl_regs; + int rc; + char *buf_p = &q_spec->regs[0]; + u16 reg_addr = Q_REG_ADDR(q_spec, Q_REG_MODE_CTL); + + while (bytes_left > 0) { + rc = regmap_bulk_write(q_chip->regmap, reg_addr, buf_p, + bytes_left < 8 ? bytes_left : 8); + if (rc) + return rc; + bytes_left -= 8; + buf_p += 8; + reg_addr += 8; + } + return 0; +} + +static int qpnp_pin_cache_regs(struct qpnp_pin_chip *q_chip, + struct qpnp_pin_spec *q_spec) +{ + int rc; + struct device *dev = &q_chip->pdev->dev; + + rc = qpnp_pin_read_regs(q_chip, q_spec); + if (rc) + dev_err(dev, "%s: unable to read control regs\n", __func__); + + return rc; +} + +#define Q_HAVE_HW_SP(idx, q_spec, val) \ + (qpnp_pin_check_config(idx, q_spec, val) == 0) + +static int _qpnp_pin_config(struct qpnp_pin_chip *q_chip, + struct qpnp_pin_spec *q_spec, + struct qpnp_pin_cfg *param) +{ + struct device *dev = &q_chip->pdev->dev; + int rc; + u8 shift, mask, *reg; + + rc = qpnp_pin_check_constraints(q_spec, param); + if (rc) + goto gpio_cfg; + + /* set mode */ + if (Q_HAVE_HW_SP(Q_PIN_CFG_MODE, q_spec, param->mode)) { + if (is_gpio_lv_mv(q_spec)) { + shift = Q_REG_LV_MV_MODE_SEL_SHIFT; + mask = Q_REG_LV_MV_MODE_SEL_MASK; + } else { + shift = Q_REG_MODE_SEL_SHIFT; + mask = Q_REG_MODE_SEL_MASK; + } + q_reg_clr_set(&q_spec->regs[Q_REG_I_MODE_CTL], + shift, mask, param->mode); + } + + /* output specific configuration */ + if (Q_HAVE_HW_SP(Q_PIN_CFG_INVERT, q_spec, param->invert)) { + if (is_gpio_lv_mv(q_spec)) { + shift = Q_REG_DIG_OUT_SRC_INVERT_SHIFT; + mask = Q_REG_DIG_OUT_SRC_INVERT_MASK; + reg = &q_spec->regs[Q_REG_I_DIG_OUT_SRC_CTL]; + } else { + shift = Q_REG_OUT_INVERT_SHIFT; + mask = Q_REG_OUT_INVERT_MASK; + reg = &q_spec->regs[Q_REG_I_MODE_CTL]; + } + q_reg_clr_set(reg, shift, mask, param->invert); + } + + if (Q_HAVE_HW_SP(Q_PIN_CFG_SRC_SEL, q_spec, param->src_sel)) { + if (is_gpio_lv_mv(q_spec)) { + shift = Q_REG_DIG_OUT_SRC_SRC_SEL_SHIFT; + mask = Q_REG_DIG_OUT_SRC_SRC_SEL_MASK; + reg = &q_spec->regs[Q_REG_I_DIG_OUT_SRC_CTL]; + } else { + shift = Q_REG_SRC_SEL_SHIFT; + mask = Q_REG_SRC_SEL_MASK; + reg = &q_spec->regs[Q_REG_I_MODE_CTL]; + } + q_reg_clr_set(reg, shift, mask, param->src_sel); + } + + if (Q_HAVE_HW_SP(Q_PIN_CFG_OUT_STRENGTH, q_spec, param->out_strength)) + q_reg_clr_set(&q_spec->regs[Q_REG_I_DIG_OUT_CTL], + Q_REG_OUT_STRENGTH_SHIFT, Q_REG_OUT_STRENGTH_MASK, + param->out_strength); + if (Q_HAVE_HW_SP(Q_PIN_CFG_OUTPUT_TYPE, q_spec, param->output_type)) + q_reg_clr_set(&q_spec->regs[Q_REG_I_DIG_OUT_CTL], + Q_REG_OUT_TYPE_SHIFT, Q_REG_OUT_TYPE_MASK, + param->output_type); + + /* input config */ + if (Q_HAVE_HW_SP(Q_PIN_CFG_DTEST_SEL, q_spec, param->dtest_sel) + && param->dtest_sel) { + if (is_gpio_lv_mv(q_spec)) { + q_reg_clr_set(&q_spec->regs[Q_REG_I_DIG_IN_CTL], + Q_REG_LV_MV_DTEST_SEL_CFG_SHIFT, + Q_REG_LV_MV_DTEST_SEL_CFG_MASK, + param->dtest_sel - 1); + q_reg_clr_set(&q_spec->regs[Q_REG_I_DIG_IN_CTL], + Q_REG_LV_MV_DTEST_SEL_EN_SHIFT, + Q_REG_LV_MV_DTEST_SEL_EN_MASK, 0x1); + } else { + q_reg_clr_set(&q_spec->regs[Q_REG_I_DIG_IN_CTL], + Q_REG_DTEST_SEL_SHIFT, + Q_REG_DTEST_SEL_MASK, + BIT(param->dtest_sel - 1)); + } + } + + /* config applicable for both input / output */ + if (Q_HAVE_HW_SP(Q_PIN_CFG_VIN_SEL, q_spec, param->vin_sel)) + q_reg_clr_set(&q_spec->regs[Q_REG_I_DIG_VIN_CTL], + Q_REG_VIN_SHIFT, Q_REG_VIN_MASK, + param->vin_sel); + if (Q_HAVE_HW_SP(Q_PIN_CFG_PULL, q_spec, param->pull)) + q_reg_clr_set(&q_spec->regs[Q_REG_I_DIG_PULL_CTL], + Q_REG_PULL_SHIFT, Q_REG_PULL_MASK, + param->pull); + if (Q_HAVE_HW_SP(Q_PIN_CFG_MASTER_EN, q_spec, param->master_en)) + q_reg_clr_set(&q_spec->regs[Q_REG_I_EN_CTL], + Q_REG_MASTER_EN_SHIFT, Q_REG_MASTER_EN_MASK, + param->master_en); + + /* mpp specific config */ + if (Q_HAVE_HW_SP(Q_PIN_CFG_AOUT_REF, q_spec, param->aout_ref)) + q_reg_clr_set(&q_spec->regs[Q_REG_I_AOUT_CTL], + Q_REG_AOUT_REF_SHIFT, Q_REG_AOUT_REF_MASK, + param->aout_ref); + if (Q_HAVE_HW_SP(Q_PIN_CFG_AIN_ROUTE, q_spec, param->ain_route)) + q_reg_clr_set(&q_spec->regs[Q_REG_I_AIN_CTL], + Q_REG_AIN_ROUTE_SHIFT, Q_REG_AIN_ROUTE_MASK, + param->ain_route); + if (Q_HAVE_HW_SP(Q_PIN_CFG_CS_OUT, q_spec, param->cs_out)) + q_reg_clr_set(&q_spec->regs[Q_REG_I_SINK_CTL], + Q_REG_CS_OUT_SHIFT, Q_REG_CS_OUT_MASK, + param->cs_out); + if (Q_HAVE_HW_SP(Q_PIN_CFG_APASS_SEL, q_spec, param->apass_sel)) + q_reg_clr_set(&q_spec->regs[Q_REG_I_APASS_SEL_CTL], + Q_REG_APASS_SEL_SHIFT, Q_REG_APASS_SEL_MASK, + param->apass_sel); + + rc = qpnp_pin_write_regs(q_chip, q_spec); + if (rc) { + dev_err(&q_chip->pdev->dev, + "%s: unable to write master enable\n", + __func__); + goto gpio_cfg; + } + + return 0; + +gpio_cfg: + dev_err(dev, "%s: unable to set default config for pmic pin %d\n", + __func__, q_spec->pmic_pin); + + return rc; +} + +int qpnp_pin_config(int gpio, struct qpnp_pin_cfg *param) +{ + int rc, chip_offset; + struct qpnp_pin_chip *q_chip; + struct qpnp_pin_spec *q_spec = NULL; + struct gpio_chip *gpio_chip; + + if (param == NULL) + return -EINVAL; + + mutex_lock(&qpnp_pin_chips_lock); + list_for_each_entry(q_chip, &qpnp_pin_chips, chip_list) { + gpio_chip = &q_chip->gpio_chip; + if (gpio >= gpio_chip->base + && gpio < gpio_chip->base + gpio_chip->ngpio) { + chip_offset = gpio - gpio_chip->base; + q_spec = qpnp_chip_gpio_get_spec(q_chip, chip_offset); + if (WARN_ON(!q_spec)) { + mutex_unlock(&qpnp_pin_chips_lock); + return -ENODEV; + } + break; + } + } + mutex_unlock(&qpnp_pin_chips_lock); + + if (!q_spec) + return -ENODEV; + + rc = _qpnp_pin_config(q_chip, q_spec, param); + + return rc; +} +EXPORT_SYMBOL(qpnp_pin_config); + +int qpnp_pin_map(const char *name, uint32_t pmic_pin) +{ + struct qpnp_pin_chip *q_chip; + struct qpnp_pin_spec *q_spec = NULL; + + if (!name) + return -EINVAL; + + mutex_lock(&qpnp_pin_chips_lock); + list_for_each_entry(q_chip, &qpnp_pin_chips, chip_list) { + if (strcmp(q_chip->gpio_chip.label, name) != 0) + continue; + if (q_chip->pmic_pin_lowest <= pmic_pin && + q_chip->pmic_pin_highest >= pmic_pin) { + q_spec = qpnp_pmic_pin_get_spec(q_chip, pmic_pin); + mutex_unlock(&qpnp_pin_chips_lock); + if (WARN_ON(!q_spec)) + return -ENODEV; + return q_chip->gpio_chip.base + q_spec->gpio_chip_idx; + } + } + mutex_unlock(&qpnp_pin_chips_lock); + return -EINVAL; +} +EXPORT_SYMBOL(qpnp_pin_map); + +static int qpnp_pin_to_irq(struct gpio_chip *gpio_chip, unsigned int offset) +{ + struct qpnp_pin_chip *q_chip = dev_get_drvdata(gpio_chip->dev); + struct qpnp_pin_spec *q_spec; + struct of_phandle_args oirq; + + q_spec = qpnp_chip_gpio_get_spec(q_chip, offset); + if (!q_spec) + return -EINVAL; + + /* if we have mapped this pin previously return the virq */ + if (q_spec->irq) + return q_spec->irq; + + /* call into irq_domain to get irq mapping */ + oirq.np = q_chip->int_ctrl; + oirq.args[0] = to_spmi_device(q_chip->pdev->dev.parent)->usid; + oirq.args[1] = (q_spec->offset >> 8) & 0xFF; + oirq.args[2] = 0; + oirq.args[3] = IRQ_TYPE_NONE; + oirq.args_count = 4; + + q_spec->irq = irq_create_of_mapping(&oirq); + if (!q_spec->irq) { + dev_err(&q_chip->pdev->dev, "%s: invalid irq for gpio %u\n", + __func__, q_spec->pmic_pin); + WARN_ON(1); + return -EINVAL; + } + + return q_spec->irq; +} + +static int qpnp_pin_get(struct gpio_chip *gpio_chip, unsigned int offset) +{ + struct qpnp_pin_chip *q_chip = dev_get_drvdata(gpio_chip->dev); + struct qpnp_pin_spec *q_spec = NULL; + u8 buf, en_mask, shift, mask, reg; + unsigned int val; + int rc; + + if (WARN_ON(!q_chip)) + return -ENODEV; + + q_spec = qpnp_chip_gpio_get_spec(q_chip, offset); + if (WARN_ON(!q_spec)) + return -ENODEV; + + if (is_gpio_lv_mv(q_spec)) { + mask = Q_REG_LV_MV_MODE_SEL_MASK; + shift = Q_REG_LV_MV_MODE_SEL_SHIFT; + } else { + mask = Q_REG_MODE_SEL_MASK; + shift = Q_REG_MODE_SEL_SHIFT; + } + + /* gpio val is from RT status iff input is enabled */ + if (q_reg_get(&q_spec->regs[Q_REG_I_MODE_CTL], shift, mask) + == QPNP_PIN_MODE_DIG_IN) { + rc = regmap_read(q_chip->regmap, + Q_REG_ADDR(q_spec, Q_REG_STATUS1), &val); + if (rc) + return rc; + buf = val; + + if (q_spec->type == Q_GPIO_TYPE && q_spec->dig_major_rev == 0) + en_mask = Q_REG_STATUS1_GPIO_EN_REV0_MASK; + else if (q_spec->type == Q_GPIO_TYPE && + q_spec->dig_major_rev > 0) + en_mask = Q_REG_STATUS1_GPIO_EN_MASK; + else /* MPP */ + en_mask = Q_REG_STATUS1_MPP_EN_MASK; + + if (!(buf & en_mask)) + return -EPERM; + + return buf & Q_REG_STATUS1_VAL_MASK; + } + + if (is_gpio_lv_mv(q_spec)) { + shift = Q_REG_DIG_OUT_SRC_INVERT_SHIFT; + mask = Q_REG_DIG_OUT_SRC_INVERT_MASK; + reg = q_spec->regs[Q_REG_I_DIG_OUT_SRC_CTL]; + } else { + shift = Q_REG_OUT_INVERT_SHIFT; + mask = Q_REG_OUT_INVERT_MASK; + reg = q_spec->regs[Q_REG_I_MODE_CTL]; + } + + return (reg & mask) >> shift; +} + +static int __qpnp_pin_set(struct qpnp_pin_chip *q_chip, + struct qpnp_pin_spec *q_spec, int value) +{ + int rc; + u8 shift, mask, *reg; + u16 address; + + if (!q_chip || !q_spec) + return -EINVAL; + + if (is_gpio_lv_mv(q_spec)) { + shift = Q_REG_DIG_OUT_SRC_INVERT_SHIFT; + mask = Q_REG_DIG_OUT_SRC_INVERT_MASK; + reg = &q_spec->regs[Q_REG_I_DIG_OUT_SRC_CTL]; + address = Q_REG_ADDR(q_spec, Q_REG_DIG_OUT_SRC_CTL); + } else { + shift = Q_REG_OUT_INVERT_SHIFT; + mask = Q_REG_OUT_INVERT_MASK; + reg = &q_spec->regs[Q_REG_I_MODE_CTL]; + address = Q_REG_ADDR(q_spec, Q_REG_MODE_CTL); + } + + q_reg_clr_set(reg, shift, mask, !!value); + + rc = regmap_write(q_chip->regmap, address, *reg); + if (rc) + dev_err(&q_chip->pdev->dev, "%s: spmi write failed\n", + __func__); + return rc; +} + + +static void qpnp_pin_set(struct gpio_chip *gpio_chip, + unsigned int offset, int value) +{ + struct qpnp_pin_chip *q_chip = dev_get_drvdata(gpio_chip->dev); + struct qpnp_pin_spec *q_spec; + + if (WARN_ON(!q_chip)) + return; + + q_spec = qpnp_chip_gpio_get_spec(q_chip, offset); + if (WARN_ON(!q_spec)) + return; + + __qpnp_pin_set(q_chip, q_spec, value); +} + +static int qpnp_pin_set_mode(struct qpnp_pin_chip *q_chip, + struct qpnp_pin_spec *q_spec, int mode) +{ + int rc; + u8 shift, mask; + + if (!q_chip || !q_spec) + return -EINVAL; + + if (qpnp_pin_check_config(Q_PIN_CFG_MODE, q_spec, mode)) { + pr_err("invalid mode specification %d\n", mode); + return -EINVAL; + } + + if (is_gpio_lv_mv(q_spec)) { + shift = Q_REG_LV_MV_MODE_SEL_SHIFT; + mask = Q_REG_LV_MV_MODE_SEL_MASK; + } else { + shift = Q_REG_MODE_SEL_SHIFT; + mask = Q_REG_MODE_SEL_MASK; + } + + q_reg_clr_set(&q_spec->regs[Q_REG_I_MODE_CTL], shift, mask, mode); + + rc = regmap_write(q_chip->regmap, Q_REG_ADDR(q_spec, Q_REG_MODE_CTL), + *&q_spec->regs[Q_REG_I_MODE_CTL]); + return rc; +} + +static int qpnp_pin_direction_input(struct gpio_chip *gpio_chip, + unsigned int offset) +{ + struct qpnp_pin_chip *q_chip = dev_get_drvdata(gpio_chip->dev); + struct qpnp_pin_spec *q_spec; + + if (WARN_ON(!q_chip)) + return -ENODEV; + + q_spec = qpnp_chip_gpio_get_spec(q_chip, offset); + if (WARN_ON(!q_spec)) + return -ENODEV; + + return qpnp_pin_set_mode(q_chip, q_spec, QPNP_PIN_MODE_DIG_IN); +} + +static int qpnp_pin_direction_output(struct gpio_chip *gpio_chip, + unsigned int offset, int val) +{ + int rc; + struct qpnp_pin_chip *q_chip = dev_get_drvdata(gpio_chip->dev); + struct qpnp_pin_spec *q_spec; + + if (WARN_ON(!q_chip)) + return -ENODEV; + + q_spec = qpnp_chip_gpio_get_spec(q_chip, offset); + if (WARN_ON(!q_spec)) + return -ENODEV; + + rc = __qpnp_pin_set(q_chip, q_spec, val); + if (rc) + return rc; + + rc = qpnp_pin_set_mode(q_chip, q_spec, QPNP_PIN_MODE_DIG_OUT); + + return rc; +} + +static int qpnp_pin_of_gpio_xlate(struct gpio_chip *gpio_chip, + const struct of_phandle_args *gpio_spec, + u32 *flags) +{ + struct qpnp_pin_chip *q_chip = dev_get_drvdata(gpio_chip->dev); + struct qpnp_pin_spec *q_spec; + + if (WARN_ON(gpio_chip->of_gpio_n_cells < 2)) { + pr_err("of_gpio_n_cells < 2\n"); + return -EINVAL; + } + + q_spec = qpnp_pmic_pin_get_spec(q_chip, gpio_spec->args[0]); + if (!q_spec) { + pr_err("no such PMIC gpio %u in device topology\n", + gpio_spec->args[0]); + return -EINVAL; + } + + if (flags) + *flags = gpio_spec->args[1]; + + return q_spec->gpio_chip_idx; +} + +static int qpnp_pin_apply_config(struct qpnp_pin_chip *q_chip, + struct qpnp_pin_spec *q_spec) +{ + struct qpnp_pin_cfg param; + struct device_node *node = q_spec->node; + int rc; + u8 shift, mask, *reg; + + if (is_gpio_lv_mv(q_spec)) { + shift = Q_REG_LV_MV_MODE_SEL_SHIFT; + mask = Q_REG_LV_MV_MODE_SEL_MASK; + } else { + shift = Q_REG_MODE_SEL_SHIFT; + mask = Q_REG_MODE_SEL_MASK; + } + param.mode = q_reg_get(&q_spec->regs[Q_REG_I_MODE_CTL], + shift, mask); + + param.output_type = q_reg_get(&q_spec->regs[Q_REG_I_DIG_OUT_CTL], + Q_REG_OUT_TYPE_SHIFT, + Q_REG_OUT_TYPE_MASK); + + if (is_gpio_lv_mv(q_spec)) { + shift = Q_REG_DIG_OUT_SRC_INVERT_SHIFT; + mask = Q_REG_DIG_OUT_SRC_INVERT_MASK; + reg = &q_spec->regs[Q_REG_I_DIG_OUT_SRC_CTL]; + } else { + shift = Q_REG_OUT_INVERT_SHIFT; + mask = Q_REG_OUT_INVERT_MASK; + reg = &q_spec->regs[Q_REG_I_MODE_CTL]; + } + param.invert = q_reg_get(reg, shift, mask); + + param.pull = q_reg_get(&q_spec->regs[Q_REG_I_DIG_PULL_CTL], + Q_REG_PULL_SHIFT, Q_REG_PULL_MASK); + param.vin_sel = q_reg_get(&q_spec->regs[Q_REG_I_DIG_VIN_CTL], + Q_REG_VIN_SHIFT, Q_REG_VIN_MASK); + param.out_strength = q_reg_get(&q_spec->regs[Q_REG_I_DIG_OUT_CTL], + Q_REG_OUT_STRENGTH_SHIFT, + Q_REG_OUT_STRENGTH_MASK); + + if (is_gpio_lv_mv(q_spec)) { + shift = Q_REG_DIG_OUT_SRC_SRC_SEL_SHIFT; + mask = Q_REG_DIG_OUT_SRC_SRC_SEL_MASK; + reg = &q_spec->regs[Q_REG_I_DIG_OUT_SRC_CTL]; + } else { + shift = Q_REG_SRC_SEL_SHIFT; + mask = Q_REG_SRC_SEL_MASK; + reg = &q_spec->regs[Q_REG_I_MODE_CTL]; + } + param.src_sel = q_reg_get(reg, shift, mask); + + param.master_en = q_reg_get(&q_spec->regs[Q_REG_I_EN_CTL], + Q_REG_MASTER_EN_SHIFT, + Q_REG_MASTER_EN_MASK); + param.aout_ref = q_reg_get(&q_spec->regs[Q_REG_I_AOUT_CTL], + Q_REG_AOUT_REF_SHIFT, + Q_REG_AOUT_REF_MASK); + param.ain_route = q_reg_get(&q_spec->regs[Q_REG_I_AIN_CTL], + Q_REG_AIN_ROUTE_SHIFT, + Q_REG_AIN_ROUTE_MASK); + param.cs_out = q_reg_get(&q_spec->regs[Q_REG_I_SINK_CTL], + Q_REG_CS_OUT_SHIFT, + Q_REG_CS_OUT_MASK); + param.apass_sel = q_reg_get(&q_spec->regs[Q_REG_I_APASS_SEL_CTL], + Q_REG_APASS_SEL_SHIFT, + Q_REG_APASS_SEL_MASK); + if (is_gpio_lv_mv(q_spec)) { + param.dtest_sel = q_reg_get(&q_spec->regs[Q_REG_I_DIG_IN_CTL], + Q_REG_LV_MV_DTEST_SEL_CFG_SHIFT, + Q_REG_LV_MV_DTEST_SEL_CFG_MASK); + } else { + param.dtest_sel = q_reg_get(&q_spec->regs[Q_REG_I_DIG_IN_CTL], + Q_REG_DTEST_SEL_SHIFT, + Q_REG_DTEST_SEL_MASK); + } + + of_property_read_u32(node, "qcom,mode", + ¶m.mode); + of_property_read_u32(node, "qcom,output-type", + ¶m.output_type); + of_property_read_u32(node, "qcom,invert", + ¶m.invert); + of_property_read_u32(node, "qcom,pull", + ¶m.pull); + of_property_read_u32(node, "qcom,vin-sel", + ¶m.vin_sel); + of_property_read_u32(node, "qcom,out-strength", + ¶m.out_strength); + of_property_read_u32(node, "qcom,src-sel", + ¶m.src_sel); + of_property_read_u32(node, "qcom,master-en", + ¶m.master_en); + of_property_read_u32(node, "qcom,aout-ref", + ¶m.aout_ref); + of_property_read_u32(node, "qcom,ain-route", + ¶m.ain_route); + of_property_read_u32(node, "qcom,cs-out", + ¶m.cs_out); + of_property_read_u32(node, "qcom,apass-sel", + ¶m.apass_sel); + of_property_read_u32(node, "qcom,dtest-sel", + ¶m.dtest_sel); + + rc = _qpnp_pin_config(q_chip, q_spec, ¶m); + + return rc; +} + +static int qpnp_pin_free_chip(struct qpnp_pin_chip *q_chip) +{ + int i, rc = 0; + + if (q_chip->chip_gpios) + for (i = 0; i < q_chip->gpio_chip.ngpio; i++) + kfree(q_chip->chip_gpios[i]); + + mutex_lock(&qpnp_pin_chips_lock); + list_del(&q_chip->chip_list); + mutex_unlock(&qpnp_pin_chips_lock); + if (q_chip->chip_registered) + gpiochip_remove(&q_chip->gpio_chip); + + kfree(q_chip->chip_gpios); + kfree(q_chip->pmic_pins); + kfree(q_chip); + return rc; +} + +#ifdef CONFIG_GPIO_QPNP_PIN_DEBUG +struct qpnp_pin_reg { + uint32_t addr; + uint32_t idx; + uint32_t shift; + uint32_t mask; +}; + +static struct dentry *driver_dfs_dir; + +static int qpnp_pin_reg_attr(enum qpnp_pin_param_type type, + struct qpnp_pin_reg *cfg, + struct qpnp_pin_spec *q_spec) +{ + switch (type) { + case Q_PIN_CFG_MODE: + if (is_gpio_lv_mv(q_spec)) { + cfg->shift = Q_REG_LV_MV_MODE_SEL_SHIFT; + cfg->mask = Q_REG_LV_MV_MODE_SEL_MASK; + } else { + cfg->shift = Q_REG_MODE_SEL_SHIFT; + cfg->mask = Q_REG_MODE_SEL_MASK; + } + cfg->addr = Q_REG_MODE_CTL; + cfg->idx = Q_REG_I_MODE_CTL; + break; + case Q_PIN_CFG_OUTPUT_TYPE: + cfg->addr = Q_REG_DIG_OUT_CTL; + cfg->idx = Q_REG_I_DIG_OUT_CTL; + cfg->shift = Q_REG_OUT_TYPE_SHIFT; + cfg->mask = Q_REG_OUT_TYPE_MASK; + break; + case Q_PIN_CFG_INVERT: + if (is_gpio_lv_mv(q_spec)) { + cfg->addr = Q_REG_DIG_OUT_SRC_CTL; + cfg->idx = Q_REG_I_DIG_OUT_SRC_CTL; + cfg->shift = Q_REG_DIG_OUT_SRC_INVERT_SHIFT; + cfg->mask = Q_REG_DIG_OUT_SRC_INVERT_MASK; + } else { + cfg->addr = Q_REG_MODE_CTL; + cfg->idx = Q_REG_I_MODE_CTL; + cfg->shift = Q_REG_OUT_INVERT_SHIFT; + cfg->mask = Q_REG_OUT_INVERT_MASK; + } + break; + case Q_PIN_CFG_PULL: + cfg->addr = Q_REG_DIG_PULL_CTL; + cfg->idx = Q_REG_I_DIG_PULL_CTL; + cfg->shift = Q_REG_PULL_SHIFT; + cfg->mask = Q_REG_PULL_MASK; + break; + case Q_PIN_CFG_VIN_SEL: + cfg->addr = Q_REG_DIG_VIN_CTL; + cfg->idx = Q_REG_I_DIG_VIN_CTL; + cfg->shift = Q_REG_VIN_SHIFT; + cfg->mask = Q_REG_VIN_MASK; + break; + case Q_PIN_CFG_OUT_STRENGTH: + cfg->addr = Q_REG_DIG_OUT_CTL; + cfg->idx = Q_REG_I_DIG_OUT_CTL; + cfg->shift = Q_REG_OUT_STRENGTH_SHIFT; + cfg->mask = Q_REG_OUT_STRENGTH_MASK; + break; + case Q_PIN_CFG_SRC_SEL: + if (is_gpio_lv_mv(q_spec)) { + cfg->addr = Q_REG_DIG_OUT_SRC_CTL; + cfg->idx = Q_REG_I_DIG_OUT_SRC_CTL; + cfg->shift = Q_REG_DIG_OUT_SRC_SRC_SEL_SHIFT; + cfg->mask = Q_REG_DIG_OUT_SRC_SRC_SEL_MASK; + } else { + cfg->addr = Q_REG_MODE_CTL; + cfg->idx = Q_REG_I_MODE_CTL; + cfg->shift = Q_REG_SRC_SEL_SHIFT; + cfg->mask = Q_REG_SRC_SEL_MASK; + } + break; + case Q_PIN_CFG_MASTER_EN: + cfg->addr = Q_REG_EN_CTL; + cfg->idx = Q_REG_I_EN_CTL; + cfg->shift = Q_REG_MASTER_EN_SHIFT; + cfg->mask = Q_REG_MASTER_EN_MASK; + break; + case Q_PIN_CFG_AOUT_REF: + cfg->addr = Q_REG_AOUT_CTL; + cfg->idx = Q_REG_I_AOUT_CTL; + cfg->shift = Q_REG_AOUT_REF_SHIFT; + cfg->mask = Q_REG_AOUT_REF_MASK; + break; + case Q_PIN_CFG_AIN_ROUTE: + cfg->addr = Q_REG_AIN_CTL; + cfg->idx = Q_REG_I_AIN_CTL; + cfg->shift = Q_REG_AIN_ROUTE_SHIFT; + cfg->mask = Q_REG_AIN_ROUTE_MASK; + break; + case Q_PIN_CFG_CS_OUT: + cfg->addr = Q_REG_SINK_CTL; + cfg->idx = Q_REG_I_SINK_CTL; + cfg->shift = Q_REG_CS_OUT_SHIFT; + cfg->mask = Q_REG_CS_OUT_MASK; + break; + case Q_PIN_CFG_APASS_SEL: + cfg->addr = Q_REG_APASS_SEL_CTL; + cfg->idx = Q_REG_I_APASS_SEL_CTL; + cfg->shift = Q_REG_APASS_SEL_SHIFT; + cfg->mask = Q_REG_APASS_SEL_MASK; + break; + case Q_PIN_CFG_DTEST_SEL: + if (is_gpio_lv_mv(q_spec)) { + cfg->shift = Q_REG_LV_MV_DTEST_SEL_CFG_SHIFT; + cfg->mask = Q_REG_LV_MV_DTEST_SEL_CFG_MASK; + } else { + cfg->shift = Q_REG_DTEST_SEL_SHIFT; + cfg->mask = Q_REG_DTEST_SEL_MASK; + } + cfg->addr = Q_REG_DIG_IN_CTL; + cfg->idx = Q_REG_I_DIG_IN_CTL; + break; + default: + return -EINVAL; + } + + return 0; +} + +static int qpnp_pin_debugfs_get(void *data, u64 *val) +{ + enum qpnp_pin_param_type *idx = data; + struct qpnp_pin_spec *q_spec; + struct qpnp_pin_reg cfg = {}; + int rc; + + q_spec = container_of(idx, struct qpnp_pin_spec, params[*idx]); + + rc = qpnp_pin_reg_attr(*idx, &cfg, q_spec); + if (rc) + return rc; + + *val = q_reg_get(&q_spec->regs[cfg.idx], cfg.shift, cfg.mask); + return 0; +} + +static int qpnp_pin_debugfs_set(void *data, u64 val) +{ + enum qpnp_pin_param_type *idx = data; + struct qpnp_pin_spec *q_spec; + struct qpnp_pin_chip *q_chip; + struct qpnp_pin_reg cfg = {}; + int rc; + + q_spec = container_of(idx, struct qpnp_pin_spec, params[*idx]); + q_chip = q_spec->q_chip; + + /* + * special handling for GPIO_LV/MV 'dtest-sel' + * if (dtest_sel == 0) then disable dtest-sel + * else enable and set dtest. + */ + if ((q_spec->subtype == Q_GPIO_SUBTYPE_GPIO_LV || + q_spec->subtype == Q_GPIO_SUBTYPE_GPIO_MV) && + *idx == Q_PIN_CFG_DTEST_SEL) { + /* enable/disable DTEST */ + cfg.shift = Q_REG_LV_MV_DTEST_SEL_EN_SHIFT; + cfg.mask = Q_REG_LV_MV_DTEST_SEL_EN_MASK; + cfg.addr = Q_REG_DIG_IN_CTL; + cfg.idx = Q_REG_I_DIG_IN_CTL; + q_reg_clr_set(&q_spec->regs[cfg.idx], + cfg.shift, cfg.mask, !!val); + } + + rc = qpnp_pin_check_config(*idx, q_spec, val); + if (rc) + return rc; + + rc = qpnp_pin_reg_attr(*idx, &cfg, q_spec); + if (rc) + return rc; + + if (*idx == Q_PIN_CFG_DTEST_SEL && val) { + if (is_gpio_lv_mv(q_spec)) + val -= 1; + else + val = BIT(val - 1); + } + + q_reg_clr_set(&q_spec->regs[cfg.idx], cfg.shift, cfg.mask, val); + rc = regmap_write(q_chip->regmap, Q_REG_ADDR(q_spec, cfg.addr), + *&q_spec->regs[cfg.idx]); + + return rc; +} +DEFINE_SIMPLE_ATTRIBUTE(qpnp_pin_fops, qpnp_pin_debugfs_get, + qpnp_pin_debugfs_set, "%llu\n"); + +#define DEBUGFS_BUF_SIZE 11 /* supports 2^32 in decimal */ + +struct qpnp_pin_debugfs_args { + enum qpnp_pin_param_type type; + const char *filename; +}; + +static struct qpnp_pin_debugfs_args dfs_args[Q_NUM_PARAMS] = { + { Q_PIN_CFG_MODE, "mode" }, + { Q_PIN_CFG_OUTPUT_TYPE, "output_type" }, + { Q_PIN_CFG_INVERT, "invert" }, + { Q_PIN_CFG_PULL, "pull" }, + { Q_PIN_CFG_VIN_SEL, "vin_sel" }, + { Q_PIN_CFG_OUT_STRENGTH, "out_strength" }, + { Q_PIN_CFG_SRC_SEL, "src_sel" }, + { Q_PIN_CFG_MASTER_EN, "master_en" }, + { Q_PIN_CFG_AOUT_REF, "aout_ref" }, + { Q_PIN_CFG_AIN_ROUTE, "ain_route" }, + { Q_PIN_CFG_CS_OUT, "cs_out" }, + { Q_PIN_CFG_APASS_SEL, "apass_sel" }, + { Q_PIN_CFG_DTEST_SEL, "dtest-sel" }, +}; + +static int qpnp_pin_debugfs_create(struct qpnp_pin_chip *q_chip) +{ + struct platform_device *pdev = q_chip->pdev; + struct device *dev = &pdev->dev; + struct qpnp_pin_spec *q_spec; + enum qpnp_pin_param_type *params; + enum qpnp_pin_param_type type; + char pmic_pin[DEBUGFS_BUF_SIZE]; + const char *filename; + struct dentry *dfs, *dfs_io_dir; + int i, j, rc; + + q_chip->dfs_dir = debugfs_create_dir(q_chip->gpio_chip.label, + driver_dfs_dir); + if (q_chip->dfs_dir == NULL) { + dev_err(dev, "%s: cannot register chip debugfs directory %s\n", + __func__, dev->of_node->name); + return -ENODEV; + } + + for (i = 0; i < q_chip->gpio_chip.ngpio; i++) { + q_spec = qpnp_chip_gpio_get_spec(q_chip, i); + params = q_spec->params; + snprintf(pmic_pin, DEBUGFS_BUF_SIZE, "%u", q_spec->pmic_pin); + dfs_io_dir = debugfs_create_dir(pmic_pin, q_chip->dfs_dir); + if (dfs_io_dir == NULL) + goto dfs_err; + + for (j = 0; j < Q_NUM_PARAMS; j++) { + type = dfs_args[j].type; + filename = dfs_args[j].filename; + + /* + * Use a value of '0' to see if the pin has even basic + * support for a function. Do not create a file if + * it doesn't. + */ + rc = qpnp_pin_check_config(type, q_spec, 0); + if (rc == -ENXIO) + continue; + + params[type] = type; + dfs = debugfs_create_file(filename, 0644, dfs_io_dir, + &q_spec->params[type], &qpnp_pin_fops); + if (dfs == NULL) + goto dfs_err; + } + } + return 0; +dfs_err: + dev_err(dev, "%s: cannot register debugfs for pmic gpio %u on chip %s\n", + __func__, q_spec->pmic_pin, dev->of_node->name); + debugfs_remove_recursive(q_chip->dfs_dir); + return -ENFILE; +} +#else +static int qpnp_pin_debugfs_create(struct qpnp_pin_chip *q_chip) +{ + return 0; +} +#endif + +static int qpnp_pin_is_valid_pin(struct qpnp_pin_spec *q_spec) +{ + if (q_spec->type == Q_GPIO_TYPE) + switch (q_spec->subtype) { + case Q_GPIO_SUBTYPE_GPIO_4CH: + case Q_GPIO_SUBTYPE_GPIOC_4CH: + case Q_GPIO_SUBTYPE_GPIO_8CH: + case Q_GPIO_SUBTYPE_GPIOC_8CH: + case Q_GPIO_SUBTYPE_GPIO_LV: + case Q_GPIO_SUBTYPE_GPIO_MV: + return 1; + } + else if (q_spec->type == Q_MPP_TYPE) + switch (q_spec->subtype) { + case Q_MPP_SUBTYPE_4CH_NO_ANA_OUT: + case Q_MPP_SUBTYPE_ULT_4CH_NO_ANA_OUT: + case Q_MPP_SUBTYPE_4CH_NO_SINK: + case Q_MPP_SUBTYPE_ULT_4CH_NO_SINK: + case Q_MPP_SUBTYPE_4CH_FULL_FUNC: + case Q_MPP_SUBTYPE_8CH_FULL_FUNC: + return 1; + } + + return 0; +} + +static int qpnp_pin_probe(struct platform_device *pdev) +{ + struct qpnp_pin_chip *q_chip; + struct qpnp_pin_spec *q_spec; + unsigned int base; + struct device_node *child; + int i, rc; + u32 lowest_gpio = UINT_MAX, highest_gpio = 0; + u32 gpio; + char version[Q_REG_SUBTYPE - Q_REG_DIG_MAJOR_REV + 1]; + const char *pin_dev_name; + + pin_dev_name = dev_name(&pdev->dev); + if (!pin_dev_name) { + dev_err(&pdev->dev, + "%s: label binding undefined for node %s\n", + __func__, + pdev->dev.of_node->full_name); + return -EINVAL; + } + + q_chip = kzalloc(sizeof(*q_chip), GFP_KERNEL); + if (!q_chip) + return -ENOMEM; + + q_chip->regmap = dev_get_regmap(pdev->dev.parent, NULL); + if (!q_chip->regmap) { + dev_err(&pdev->dev, "Couldn't get parent's regmap\n"); + return -EINVAL; + } + q_chip->pdev = pdev; + dev_set_drvdata(&pdev->dev, q_chip); + + mutex_lock(&qpnp_pin_chips_lock); + list_add(&q_chip->chip_list, &qpnp_pin_chips); + mutex_unlock(&qpnp_pin_chips_lock); + + /* first scan through nodes to find the range required for allocation */ + i = 0; + for_each_available_child_of_node(pdev->dev.of_node, child) { + rc = of_property_read_u32(child, "qcom,pin-num", &gpio); + if (rc) { + dev_err(&pdev->dev, + "%s: unable to get qcom,pin-num property\n", + __func__); + goto err_probe; + } + + if (gpio < lowest_gpio) + lowest_gpio = gpio; + if (gpio > highest_gpio) + highest_gpio = gpio; + i++; + } + q_chip->gpio_chip.ngpio = i; + + if (highest_gpio < lowest_gpio) { + dev_err(&pdev->dev, + "%s: no device nodes specified in topology\n", + __func__); + rc = -EINVAL; + goto err_probe; + } else if (lowest_gpio == 0) { + dev_err(&pdev->dev, "%s: 0 is not a valid PMIC GPIO\n", + __func__); + rc = -EINVAL; + goto err_probe; + } + + q_chip->pmic_pin_lowest = lowest_gpio; + q_chip->pmic_pin_highest = highest_gpio; + + /* allocate gpio lookup tables */ + q_chip->pmic_pins = kzalloc(sizeof(struct qpnp_pin_spec *) * + (highest_gpio - lowest_gpio + 1), + GFP_KERNEL); + q_chip->chip_gpios = kzalloc(sizeof(struct qpnp_pin_spec *) * + q_chip->gpio_chip.ngpio, + GFP_KERNEL); + if (!q_chip->pmic_pins || !q_chip->chip_gpios) { + dev_err(&pdev->dev, "%s: unable to allocate memory\n", + __func__); + rc = -ENOMEM; + goto err_probe; + } + + /* get interrupt controller device_node */ + q_chip->int_ctrl = of_irq_find_parent(pdev->dev.of_node); + if (!q_chip->int_ctrl) { + dev_err(&pdev->dev, "%s: Can't find interrupt parent\n", + __func__); + rc = -EINVAL; + goto err_probe; + } + i = 0; + /* now scan through again and populate the lookup table */ + for_each_available_child_of_node(pdev->dev.of_node, child) { + rc = of_property_read_u32(child, "reg", &base); + if (rc < 0) { + dev_err(&pdev->dev, + "Couldn't find reg in node = %s rc = %d\n", + child->full_name, rc); + goto err_probe; + } + + rc = of_property_read_u32(child, "qcom,pin-num", &gpio); + if (rc) { + dev_err(&pdev->dev, + "%s: unable to get qcom,pin-num property\n", + __func__); + goto err_probe; + } + + q_spec = kzalloc(sizeof(struct qpnp_pin_spec), GFP_KERNEL); + if (!q_spec) { + rc = -ENOMEM; + goto err_probe; + } + + q_spec->slave = to_spmi_device(pdev->dev.parent)->usid; + q_spec->offset = base; + q_spec->gpio_chip_idx = i; + q_spec->pmic_pin = gpio; + q_spec->node = child; + q_spec->q_chip = q_chip; + + rc = regmap_bulk_read(q_chip->regmap, + Q_REG_ADDR(q_spec, Q_REG_DIG_MAJOR_REV), + &version[0], + ARRAY_SIZE(version)); + if (rc) { + dev_err(&pdev->dev, "%s: unable to read type regs\n", + __func__); + goto err_probe; + } + q_spec->dig_major_rev = version[Q_REG_DIG_MAJOR_REV - + Q_REG_DIG_MAJOR_REV]; + q_spec->type = version[Q_REG_TYPE - Q_REG_DIG_MAJOR_REV]; + q_spec->subtype = version[Q_REG_SUBTYPE - Q_REG_DIG_MAJOR_REV]; + + if (!qpnp_pin_is_valid_pin(q_spec)) { + dev_err(&pdev->dev, + "%s: invalid pin type (type=0x%x subtype=0x%x)\n", + __func__, q_spec->type, q_spec->subtype); + goto err_probe; + } + + rc = qpnp_pin_ctl_regs_init(q_spec); + if (rc) + goto err_probe; + + /* initialize lookup table params */ + qpnp_pmic_pin_set_spec(q_chip, gpio, q_spec); + qpnp_chip_gpio_set_spec(q_chip, i, q_spec); + i++; + } + + q_chip->gpio_chip.base = -1; + q_chip->gpio_chip.label = pin_dev_name; + q_chip->gpio_chip.direction_input = qpnp_pin_direction_input; + q_chip->gpio_chip.direction_output = qpnp_pin_direction_output; + q_chip->gpio_chip.to_irq = qpnp_pin_to_irq; + q_chip->gpio_chip.get = qpnp_pin_get; + q_chip->gpio_chip.set = qpnp_pin_set; + q_chip->gpio_chip.dev = &pdev->dev; + q_chip->gpio_chip.of_xlate = qpnp_pin_of_gpio_xlate; + q_chip->gpio_chip.of_gpio_n_cells = 2; + q_chip->gpio_chip.can_sleep = 0; + + rc = gpiochip_add(&q_chip->gpio_chip); + if (rc) { + dev_err(&pdev->dev, "%s: Can't add gpio chip, rc = %d\n", + __func__, rc); + goto err_probe; + } + + q_chip->chip_registered = true; + /* now configure gpio config defaults if they exist */ + for (i = 0; i < q_chip->gpio_chip.ngpio; i++) { + q_spec = qpnp_chip_gpio_get_spec(q_chip, i); + if (WARN_ON(!q_spec)) { + rc = -ENODEV; + goto err_probe; + } + + rc = qpnp_pin_cache_regs(q_chip, q_spec); + if (rc) + goto err_probe; + + rc = qpnp_pin_apply_config(q_chip, q_spec); + if (rc) + goto err_probe; + } + + dev_dbg(&pdev->dev, "%s: gpio_chip registered between %d-%u\n", + __func__, q_chip->gpio_chip.base, + (q_chip->gpio_chip.base + q_chip->gpio_chip.ngpio) - 1); + + rc = qpnp_pin_debugfs_create(q_chip); + if (rc) { + dev_err(&pdev->dev, "%s: debugfs creation failed\n", + __func__); + goto err_probe; + } + + return 0; + +err_probe: + qpnp_pin_free_chip(q_chip); + return rc; +} + +static int qpnp_pin_remove(struct platform_device *pdev) +{ + struct qpnp_pin_chip *q_chip = dev_get_drvdata(&pdev->dev); + + debugfs_remove_recursive(q_chip->dfs_dir); + + return qpnp_pin_free_chip(q_chip); +} + +static const struct of_device_id spmi_match_table[] = { + { .compatible = "qcom,qpnp-pin", + }, + {} +}; + +static const struct platform_device_id qpnp_pin_id[] = { + { "qcom,qpnp-pin", 0 }, + { } +}; +MODULE_DEVICE_TABLE(spmi, qpnp_pin_id); + +static struct platform_driver qpnp_pin_driver = { + .driver = { + .name = "qcom,qpnp-pin", + .of_match_table = spmi_match_table, + }, + .probe = qpnp_pin_probe, + .remove = qpnp_pin_remove, + .id_table = qpnp_pin_id, +}; + +static int __init qpnp_pin_init(void) +{ +#ifdef CONFIG_GPIO_QPNP_PIN_DEBUG + driver_dfs_dir = debugfs_create_dir("qpnp_pin", NULL); + if (driver_dfs_dir == NULL) + pr_err("Cannot register top level debugfs directory\n"); +#endif + + return platform_driver_register(&qpnp_pin_driver); +} + +static void __exit qpnp_pin_exit(void) +{ +#ifdef CONFIG_GPIO_QPNP_PIN_DEBUG + debugfs_remove_recursive(driver_dfs_dir); +#endif + platform_driver_unregister(&qpnp_pin_driver); +} + +MODULE_DESCRIPTION("QPNP PMIC gpio driver"); +MODULE_LICENSE("GPL v2"); + +subsys_initcall(qpnp_pin_init); +module_exit(qpnp_pin_exit); --- /dev/null 2019-10-24 16:47:25.704025805 +0200 +++ linux-4.4.115-fbx/drivers/gpu/drm/msm/adreno/a5xx_counters.c 2019-01-22 16:16:23.483246225 +0100 @@ -0,0 +1,825 @@ +/* Copyright (c) 2017-2018 The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include "a5xx_gpu.h" + +/* + * Fixed counters are not selectable, they always count the same thing. + * The countable is an index into the group: countable 0 = register 0, + * etc and they have no select register + */ +static int a5xx_counter_get_fixed(struct msm_gpu *gpu, + struct adreno_counter_group *group, + u32 countable, u32 *lo, u32 *hi) +{ + if (countable >= group->nr_counters) + return -EINVAL; + + if (lo) + *lo = group->counters[countable].lo; + if (hi) + *hi = group->counters[countable].hi; + + return countable; +} + +/* + * Most counters are selectable in that they can be programmed to count + * different events; in most cases there are many more countables than + * counters. When a new counter is requested, first walk the list to see if any + * other counters in that group are counting the same countable and if so reuse + * that counter. If not find the first empty counter in the list and register + * that for the desired countable. If we are out of counters too bad so sad. + */ +static int a5xx_counter_get(struct msm_gpu *gpu, + struct adreno_counter_group *group, + u32 countable, u32 *lo, u32 *hi) +{ + struct adreno_counter *counter; + int i, empty = -1; + + spin_lock(&group->lock); + + for (i = 0; i < group->nr_counters; i++) { + counter = &group->counters[i]; + + if (counter->refcount) { + if (counter->countable == countable) { + counter->refcount++; + + if (lo) + *lo = counter->lo; + if (hi) + *hi = counter->hi; + + spin_unlock(&group->lock); + return i; + } + } else + empty = (empty == -1) ? i : empty; + } + + if (empty == -1) { + spin_unlock(&group->lock); + return -EBUSY; + } + + counter = &group->counters[empty]; + + counter->refcount = 1; + counter->countable = countable; + + if (lo) + *lo = counter->lo; + if (hi) + *hi = counter->hi; + + spin_unlock(&group->lock); + + if (pm_runtime_active(&gpu->pdev->dev) && group->funcs.enable) + group->funcs.enable(gpu, group, empty, false); + + return empty; +} + +/* The majority of the non-fixed counter selects can be programmed by the CPU */ +static void a5xx_counter_enable_cpu(struct msm_gpu *gpu, + struct adreno_counter_group *group, int counterid, bool restore) +{ + struct adreno_counter *counter = &group->counters[counterid]; + + gpu_write(gpu, counter->sel, counter->countable); +} + +static void a5xx_counter_enable_pm4(struct msm_gpu *gpu, + struct adreno_counter_group *group, int counterid, bool restore) +{ + struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); + struct a5xx_gpu *a5xx_gpu = to_a5xx_gpu(adreno_gpu); + struct msm_ringbuffer *ring = gpu->rb[0]; + struct adreno_counter *counter = &group->counters[counterid]; + + /* + * If we are restoring the counters after a power cycle we can safely + * use AHB to enable the counters because we know SP/TP power collapse + * isn't active + */ + if (restore) { + a5xx_counter_enable_cpu(gpu, group, counterid, true); + return; + } + + mutex_lock(&gpu->dev->struct_mutex); + + /* + * If HW init hasn't run yet we can use the CPU to program the counter + * (and indeed we must because we can't submit commands to the + * GPU if it isn't initalized) + */ + if (gpu->needs_hw_init) { + a5xx_counter_enable_cpu(gpu, group, counterid, true); + mutex_unlock(&gpu->dev->struct_mutex); + return; + } + + /* Turn off preemption for the duration of this command */ + OUT_PKT7(ring, CP_PREEMPT_ENABLE_GLOBAL, 1); + OUT_RING(ring, 0x02); + + /* Turn off protected mode to write to special registers */ + OUT_PKT7(ring, CP_SET_PROTECTED_MODE, 1); + OUT_RING(ring, 0); + + /* Set the save preemption record for the ring/command */ + OUT_PKT4(ring, REG_A5XX_CP_CONTEXT_SWITCH_SAVE_ADDR_LO, 2); + OUT_RING(ring, lower_32_bits(a5xx_gpu->preempt_iova[ring->id])); + OUT_RING(ring, upper_32_bits(a5xx_gpu->preempt_iova[ring->id])); + + /* Turn back on protected mode */ + OUT_PKT7(ring, CP_SET_PROTECTED_MODE, 1); + OUT_RING(ring, 1); + + /* Idle the GPU */ + OUT_PKT7(ring, CP_WAIT_FOR_IDLE, 0); + + /* Enable the counter */ + OUT_PKT4(ring, counter->sel, 1); + OUT_RING(ring, counter->countable); + + /* Re-enable preemption */ + OUT_PKT7(ring, CP_PREEMPT_ENABLE_GLOBAL, 1); + OUT_RING(ring, 0x00); + + OUT_PKT7(ring, CP_PREEMPT_ENABLE_LOCAL, 1); + OUT_RING(ring, 0x01); + + OUT_PKT7(ring, CP_YIELD_ENABLE, 1); + OUT_RING(ring, 0x01); + + /* Yield */ + OUT_PKT7(ring, CP_CONTEXT_SWITCH_YIELD, 4); + OUT_RING(ring, 0x00); + OUT_RING(ring, 0x00); + OUT_RING(ring, 0x01); + OUT_RING(ring, 0x01); + + gpu->funcs->flush(gpu, ring); + + /* Preempt into our ring if we need to */ + a5xx_preempt_trigger(gpu); + + /* wait for the operation to complete */ + a5xx_idle(gpu, ring); + + mutex_unlock(&gpu->dev->struct_mutex); +} + +/* + * GPMU counters are selectable but the selects are muxed together in two + * registers + */ +static void a5xx_counter_enable_gpmu(struct msm_gpu *gpu, + struct adreno_counter_group *group, int counterid, bool restore) +{ + struct adreno_counter *counter = &group->counters[counterid]; + u32 reg; + int shift; + + /* + * The selects for the GPMU counters are grouped together in two + * registers, a nibble for each counter. Counters 0-3 are located in + * GPMU_POWER_COUNTER_SELECT0 and 4-5 are in GPMU_POWER_COUNTER_SELECT1 + */ + if (counterid <= 3) { + shift = counterid << 3; + reg = REG_A5XX_GPMU_POWER_COUNTER_SELECT_0; + } else { + shift = (counterid - 4) << 3; + reg = REG_A5XX_GPMU_POWER_COUNTER_SELECT_1; + } + + gpu_rmw(gpu, reg, 0xFF << shift, (counter->countable & 0xff) << shift); +} + +/* VBIF counters are selectable but have their own programming process */ +static void a5xx_counter_enable_vbif(struct msm_gpu *gpu, + struct adreno_counter_group *group, int counterid, bool restore) +{ + struct adreno_counter *counter = &group->counters[counterid]; + + gpu_write(gpu, REG_A5XX_VBIF_PERF_CNT_CLR(counterid), 1); + gpu_write(gpu, REG_A5XX_VBIF_PERF_CNT_CLR(counterid), 0); + gpu_write(gpu, REG_A5XX_VBIF_PERF_CNT_SEL(counterid), + counter->countable); + gpu_write(gpu, REG_A5XX_VBIF_PERF_CNT_EN(counterid), 1); +} + +/* + * VBIF power counters are not slectable but need to be cleared/enabled before + * use + */ +static void a5xx_counter_enable_vbif_power(struct msm_gpu *gpu, + struct adreno_counter_group *group, int counterid, bool restore) +{ + gpu_write(gpu, REG_A5XX_VBIF_PERF_PWR_CNT_CLR(counterid), 1); + gpu_write(gpu, REG_A5XX_VBIF_PERF_PWR_CNT_CLR(counterid), 0); + gpu_write(gpu, REG_A5XX_VBIF_PERF_PWR_CNT_EN(counterid), 1); +} + +/* GPMU always on counter needs to be enabled before use */ +static void a5xx_counter_enable_alwayson_power(struct msm_gpu *gpu, + struct adreno_counter_group *group, int counterid, bool restore) +{ + gpu_write(gpu, REG_A5XX_GPMU_ALWAYS_ON_COUNTER_RESET, 1); +} + +static u64 a5xx_counter_read(struct msm_gpu *gpu, + struct adreno_counter_group *group, int counterid) +{ + if (counterid < 0 || counterid >= group->nr_counters) + return 0; + + /* If the power is off, return the shadow value */ + if (!pm_runtime_active(&gpu->pdev->dev)) + return group->counters[counterid].value; + + return gpu_read64(gpu, group->counters[counterid].lo, + group->counters[counterid].hi); +} + +/* + * Selectable counters that are no longer used reset the countable to 0 to mark + * the counter as free + */ +static void a5xx_counter_put(struct msm_gpu *gpu, + struct adreno_counter_group *group, int counterid) +{ + struct adreno_counter *counter; + + if (counterid >= group->nr_counters) + return; + + counter = &group->counters[counterid]; + + spin_lock(&group->lock); + if (counter->refcount > 0) + counter->refcount--; + spin_unlock(&group->lock); +} + +static void a5xx_counter_group_enable(struct msm_gpu *gpu, + struct adreno_counter_group *group, bool restore) +{ + int i; + + if (!group || !group->funcs.enable) + return; + + spin_lock(&group->lock); + + for (i = 0; i < group->nr_counters; i++) { + if (!group->counters[i].refcount) + continue; + + group->funcs.enable(gpu, group, i, restore); + } + spin_unlock(&group->lock); +} + +static void a5xx_counter_restore(struct msm_gpu *gpu, + struct adreno_counter_group *group) +{ + int i; + + spin_lock(&group->lock); + for (i = 0; i < group->nr_counters; i++) { + struct adreno_counter *counter = &group->counters[i]; + uint32_t bit, offset = counter->load_bit; + + /* Don't load if the counter isn't active or can't be loaded */ + if (!counter->refcount) + continue; + + /* + * Each counter has a specific bit in one of four load command + * registers. Figure out which register / relative bit to use + * for the counter + */ + bit = do_div(offset, 32); + + /* Write the counter value */ + gpu_write64(gpu, REG_A5XX_RBBM_PERFCTR_LOAD_VALUE_LO, + REG_A5XX_RBBM_PERFCTR_LOAD_VALUE_HI, + counter->value); + + /* + * Write the load bit to load the counter - the command register + * will get reset to 0 after the operation completes + */ + gpu_write(gpu, REG_A5XX_RBBM_PERFCTR_LOAD_CMD0 + offset, + (1 << bit)); + } + spin_unlock(&group->lock); +} + +static void a5xx_counter_save(struct msm_gpu *gpu, + struct adreno_counter_group *group) +{ + int i; + + spin_lock(&group->lock); + for (i = 0; i < group->nr_counters; i++) { + struct adreno_counter *counter = &group->counters[i]; + + if (counter->refcount > 0) + counter->value = gpu_read64(gpu, counter->lo, + counter->hi); + } + spin_unlock(&group->lock); +} + +static struct adreno_counter a5xx_counters_alwayson[1] = { + { REG_A5XX_RBBM_ALWAYSON_COUNTER_LO, + REG_A5XX_RBBM_ALWAYSON_COUNTER_HI }, +}; + +static struct adreno_counter a5xx_counters_ccu[] = { + { REG_A5XX_RBBM_PERFCTR_CCU_0_LO, REG_A5XX_RBBM_PERFCTR_CCU_0_HI, + REG_A5XX_RB_PERFCTR_CCU_SEL_0, 40 }, + { REG_A5XX_RBBM_PERFCTR_CCU_1_LO, REG_A5XX_RBBM_PERFCTR_CCU_1_HI, + REG_A5XX_RB_PERFCTR_CCU_SEL_1, 41 }, + { REG_A5XX_RBBM_PERFCTR_CCU_2_LO, REG_A5XX_RBBM_PERFCTR_CCU_2_HI, + REG_A5XX_RB_PERFCTR_CCU_SEL_2, 42 }, + { REG_A5XX_RBBM_PERFCTR_CCU_3_LO, REG_A5XX_RBBM_PERFCTR_CCU_3_HI, + REG_A5XX_RB_PERFCTR_CCU_SEL_3, 43 }, +}; + +static struct adreno_counter a5xx_counters_cmp[] = { + { REG_A5XX_RBBM_PERFCTR_CMP_0_LO, REG_A5XX_RBBM_PERFCTR_CMP_0_HI, + REG_A5XX_RB_PERFCTR_CMP_SEL_0, 94 }, + { REG_A5XX_RBBM_PERFCTR_CMP_1_LO, REG_A5XX_RBBM_PERFCTR_CMP_1_HI, + REG_A5XX_RB_PERFCTR_CMP_SEL_1, 95 }, + { REG_A5XX_RBBM_PERFCTR_CMP_2_LO, REG_A5XX_RBBM_PERFCTR_CMP_2_HI, + REG_A5XX_RB_PERFCTR_CMP_SEL_2, 96 }, + { REG_A5XX_RBBM_PERFCTR_CMP_3_LO, REG_A5XX_RBBM_PERFCTR_CMP_3_HI, + REG_A5XX_RB_PERFCTR_CMP_SEL_3, 97 }, +}; + +static struct adreno_counter a5xx_counters_cp[] = { + { REG_A5XX_RBBM_PERFCTR_CP_0_LO, REG_A5XX_RBBM_PERFCTR_CP_0_HI, + REG_A5XX_CP_PERFCTR_CP_SEL_0, 0 }, + { REG_A5XX_RBBM_PERFCTR_CP_1_LO, REG_A5XX_RBBM_PERFCTR_CP_1_HI, + REG_A5XX_CP_PERFCTR_CP_SEL_1, 1}, + { REG_A5XX_RBBM_PERFCTR_CP_2_LO, REG_A5XX_RBBM_PERFCTR_CP_2_HI, + REG_A5XX_CP_PERFCTR_CP_SEL_2, 2 }, + { REG_A5XX_RBBM_PERFCTR_CP_3_LO, REG_A5XX_RBBM_PERFCTR_CP_3_HI, + REG_A5XX_CP_PERFCTR_CP_SEL_3, 3 }, + { REG_A5XX_RBBM_PERFCTR_CP_4_LO, REG_A5XX_RBBM_PERFCTR_CP_4_HI, + REG_A5XX_CP_PERFCTR_CP_SEL_4, 4 }, + { REG_A5XX_RBBM_PERFCTR_CP_5_LO, REG_A5XX_RBBM_PERFCTR_CP_5_HI, + REG_A5XX_CP_PERFCTR_CP_SEL_5, 5 }, + { REG_A5XX_RBBM_PERFCTR_CP_6_LO, REG_A5XX_RBBM_PERFCTR_CP_6_HI, + REG_A5XX_CP_PERFCTR_CP_SEL_6, 6 }, + { REG_A5XX_RBBM_PERFCTR_CP_7_LO, REG_A5XX_RBBM_PERFCTR_CP_7_HI, + REG_A5XX_CP_PERFCTR_CP_SEL_7, 7 }, +}; + +static struct adreno_counter a5xx_counters_hlsq[] = { + { REG_A5XX_RBBM_PERFCTR_HLSQ_0_LO, REG_A5XX_RBBM_PERFCTR_HLSQ_0_HI, + REG_A5XX_HLSQ_PERFCTR_HLSQ_SEL_0, 28 }, + { REG_A5XX_RBBM_PERFCTR_HLSQ_1_LO, REG_A5XX_RBBM_PERFCTR_HLSQ_1_HI, + REG_A5XX_HLSQ_PERFCTR_HLSQ_SEL_1, 29 }, + { REG_A5XX_RBBM_PERFCTR_HLSQ_2_LO, REG_A5XX_RBBM_PERFCTR_HLSQ_2_HI, + REG_A5XX_HLSQ_PERFCTR_HLSQ_SEL_2, 30 }, + { REG_A5XX_RBBM_PERFCTR_HLSQ_3_LO, REG_A5XX_RBBM_PERFCTR_HLSQ_3_HI, + REG_A5XX_HLSQ_PERFCTR_HLSQ_SEL_3, 31 }, + { REG_A5XX_RBBM_PERFCTR_HLSQ_4_LO, REG_A5XX_RBBM_PERFCTR_HLSQ_4_HI, + REG_A5XX_HLSQ_PERFCTR_HLSQ_SEL_4, 32 }, + { REG_A5XX_RBBM_PERFCTR_HLSQ_5_LO, REG_A5XX_RBBM_PERFCTR_HLSQ_5_HI, + REG_A5XX_HLSQ_PERFCTR_HLSQ_SEL_5, 33 }, + { REG_A5XX_RBBM_PERFCTR_HLSQ_6_LO, REG_A5XX_RBBM_PERFCTR_HLSQ_6_HI, + REG_A5XX_HLSQ_PERFCTR_HLSQ_SEL_6, 34 }, + { REG_A5XX_RBBM_PERFCTR_HLSQ_7_LO, REG_A5XX_RBBM_PERFCTR_HLSQ_7_HI, + REG_A5XX_HLSQ_PERFCTR_HLSQ_SEL_7, 35 }, +}; + +static struct adreno_counter a5xx_counters_lrz[] = { + { REG_A5XX_RBBM_PERFCTR_LRZ_0_LO, REG_A5XX_RBBM_PERFCTR_LRZ_0_HI, + REG_A5XX_GRAS_PERFCTR_LRZ_SEL_0, 90 }, + { REG_A5XX_RBBM_PERFCTR_LRZ_1_LO, REG_A5XX_RBBM_PERFCTR_LRZ_1_HI, + REG_A5XX_GRAS_PERFCTR_LRZ_SEL_1, 91 }, + { REG_A5XX_RBBM_PERFCTR_LRZ_2_LO, REG_A5XX_RBBM_PERFCTR_LRZ_2_HI, + REG_A5XX_GRAS_PERFCTR_LRZ_SEL_2, 92 }, + { REG_A5XX_RBBM_PERFCTR_LRZ_3_LO, REG_A5XX_RBBM_PERFCTR_LRZ_3_HI, + REG_A5XX_GRAS_PERFCTR_LRZ_SEL_3, 93 }, +}; + +static struct adreno_counter a5xx_counters_pc[] = { + { REG_A5XX_RBBM_PERFCTR_PC_0_LO, REG_A5XX_RBBM_PERFCTR_PC_0_HI, + REG_A5XX_PC_PERFCTR_PC_SEL_0, 12 }, + { REG_A5XX_RBBM_PERFCTR_PC_1_LO, REG_A5XX_RBBM_PERFCTR_PC_1_HI, + REG_A5XX_PC_PERFCTR_PC_SEL_1, 13 }, + { REG_A5XX_RBBM_PERFCTR_PC_2_LO, REG_A5XX_RBBM_PERFCTR_PC_2_HI, + REG_A5XX_PC_PERFCTR_PC_SEL_2, 14 }, + { REG_A5XX_RBBM_PERFCTR_PC_3_LO, REG_A5XX_RBBM_PERFCTR_PC_3_HI, + REG_A5XX_PC_PERFCTR_PC_SEL_3, 15 }, + { REG_A5XX_RBBM_PERFCTR_PC_4_LO, REG_A5XX_RBBM_PERFCTR_PC_4_HI, + REG_A5XX_PC_PERFCTR_PC_SEL_4, 16 }, + { REG_A5XX_RBBM_PERFCTR_PC_5_LO, REG_A5XX_RBBM_PERFCTR_PC_5_HI, + REG_A5XX_PC_PERFCTR_PC_SEL_5, 17 }, + { REG_A5XX_RBBM_PERFCTR_PC_6_LO, REG_A5XX_RBBM_PERFCTR_PC_6_HI, + REG_A5XX_PC_PERFCTR_PC_SEL_6, 18 }, + { REG_A5XX_RBBM_PERFCTR_PC_7_LO, REG_A5XX_RBBM_PERFCTR_PC_7_HI, + REG_A5XX_PC_PERFCTR_PC_SEL_7, 19 }, +}; + +static struct adreno_counter a5xx_counters_ras[] = { + { REG_A5XX_RBBM_PERFCTR_RAS_0_LO, REG_A5XX_RBBM_PERFCTR_RAS_0_HI, + REG_A5XX_GRAS_PERFCTR_RAS_SEL_0, 48 }, + { REG_A5XX_RBBM_PERFCTR_RAS_1_LO, REG_A5XX_RBBM_PERFCTR_RAS_1_HI, + REG_A5XX_GRAS_PERFCTR_RAS_SEL_1, 49 }, + { REG_A5XX_RBBM_PERFCTR_RAS_2_LO, REG_A5XX_RBBM_PERFCTR_RAS_2_HI, + REG_A5XX_GRAS_PERFCTR_RAS_SEL_2, 50 }, + { REG_A5XX_RBBM_PERFCTR_RAS_3_LO, REG_A5XX_RBBM_PERFCTR_RAS_3_HI, + REG_A5XX_GRAS_PERFCTR_RAS_SEL_3, 51 }, +}; + +static struct adreno_counter a5xx_counters_rb[] = { + { REG_A5XX_RBBM_PERFCTR_RB_0_LO, REG_A5XX_RBBM_PERFCTR_RB_0_HI, + REG_A5XX_RB_PERFCTR_RB_SEL_0, 80 }, + { REG_A5XX_RBBM_PERFCTR_RB_1_LO, REG_A5XX_RBBM_PERFCTR_RB_1_HI, + REG_A5XX_RB_PERFCTR_RB_SEL_1, 81 }, + { REG_A5XX_RBBM_PERFCTR_RB_2_LO, REG_A5XX_RBBM_PERFCTR_RB_2_HI, + REG_A5XX_RB_PERFCTR_RB_SEL_2, 82 }, + { REG_A5XX_RBBM_PERFCTR_RB_3_LO, REG_A5XX_RBBM_PERFCTR_RB_3_HI, + REG_A5XX_RB_PERFCTR_RB_SEL_3, 83 }, + { REG_A5XX_RBBM_PERFCTR_RB_4_LO, REG_A5XX_RBBM_PERFCTR_RB_4_HI, + REG_A5XX_RB_PERFCTR_RB_SEL_4, 84 }, + { REG_A5XX_RBBM_PERFCTR_RB_5_LO, REG_A5XX_RBBM_PERFCTR_RB_5_HI, + REG_A5XX_RB_PERFCTR_RB_SEL_5, 85 }, + { REG_A5XX_RBBM_PERFCTR_RB_6_LO, REG_A5XX_RBBM_PERFCTR_RB_6_HI, + REG_A5XX_RB_PERFCTR_RB_SEL_6, 86 }, + { REG_A5XX_RBBM_PERFCTR_RB_7_LO, REG_A5XX_RBBM_PERFCTR_RB_7_HI, + REG_A5XX_RB_PERFCTR_RB_SEL_7, 87 }, +}; + +static struct adreno_counter a5xx_counters_rbbm[] = { + { REG_A5XX_RBBM_PERFCTR_RBBM_0_LO, REG_A5XX_RBBM_PERFCTR_RBBM_0_HI, + REG_A5XX_RBBM_PERFCTR_RBBM_SEL_0, 8 }, + { REG_A5XX_RBBM_PERFCTR_RBBM_1_LO, REG_A5XX_RBBM_PERFCTR_RBBM_1_HI, + REG_A5XX_RBBM_PERFCTR_RBBM_SEL_1, 9 }, + { REG_A5XX_RBBM_PERFCTR_RBBM_2_LO, REG_A5XX_RBBM_PERFCTR_RBBM_2_HI, + REG_A5XX_RBBM_PERFCTR_RBBM_SEL_2, 10 }, + { REG_A5XX_RBBM_PERFCTR_RBBM_3_LO, REG_A5XX_RBBM_PERFCTR_RBBM_3_HI, + REG_A5XX_RBBM_PERFCTR_RBBM_SEL_3, 11 }, +}; + +static struct adreno_counter a5xx_counters_sp[] = { + { REG_A5XX_RBBM_PERFCTR_SP_0_LO, REG_A5XX_RBBM_PERFCTR_SP_0_HI, + REG_A5XX_SP_PERFCTR_SP_SEL_0, 68 }, + { REG_A5XX_RBBM_PERFCTR_SP_1_LO, REG_A5XX_RBBM_PERFCTR_SP_1_HI, + REG_A5XX_SP_PERFCTR_SP_SEL_1, 69 }, + { REG_A5XX_RBBM_PERFCTR_SP_2_LO, REG_A5XX_RBBM_PERFCTR_SP_2_HI, + REG_A5XX_SP_PERFCTR_SP_SEL_2, 70 }, + { REG_A5XX_RBBM_PERFCTR_SP_3_LO, REG_A5XX_RBBM_PERFCTR_SP_3_HI, + REG_A5XX_SP_PERFCTR_SP_SEL_3, 71 }, + { REG_A5XX_RBBM_PERFCTR_SP_4_LO, REG_A5XX_RBBM_PERFCTR_SP_4_HI, + REG_A5XX_SP_PERFCTR_SP_SEL_4, 72 }, + { REG_A5XX_RBBM_PERFCTR_SP_5_LO, REG_A5XX_RBBM_PERFCTR_SP_5_HI, + REG_A5XX_SP_PERFCTR_SP_SEL_5, 73 }, + { REG_A5XX_RBBM_PERFCTR_SP_6_LO, REG_A5XX_RBBM_PERFCTR_SP_6_HI, + REG_A5XX_SP_PERFCTR_SP_SEL_6, 74 }, + { REG_A5XX_RBBM_PERFCTR_SP_7_LO, REG_A5XX_RBBM_PERFCTR_SP_7_HI, + REG_A5XX_SP_PERFCTR_SP_SEL_7, 75 }, + { REG_A5XX_RBBM_PERFCTR_SP_8_LO, REG_A5XX_RBBM_PERFCTR_SP_8_HI, + REG_A5XX_SP_PERFCTR_SP_SEL_8, 76 }, + { REG_A5XX_RBBM_PERFCTR_SP_9_LO, REG_A5XX_RBBM_PERFCTR_SP_9_HI, + REG_A5XX_SP_PERFCTR_SP_SEL_9, 77 }, + { REG_A5XX_RBBM_PERFCTR_SP_10_LO, REG_A5XX_RBBM_PERFCTR_SP_10_HI, + REG_A5XX_SP_PERFCTR_SP_SEL_10, 78 }, + { REG_A5XX_RBBM_PERFCTR_SP_11_LO, REG_A5XX_RBBM_PERFCTR_SP_11_HI, + REG_A5XX_SP_PERFCTR_SP_SEL_11, 79 }, +}; + +static struct adreno_counter a5xx_counters_tp[] = { + { REG_A5XX_RBBM_PERFCTR_TP_0_LO, REG_A5XX_RBBM_PERFCTR_TP_0_HI, + REG_A5XX_TPL1_PERFCTR_TP_SEL_0, 60 }, + { REG_A5XX_RBBM_PERFCTR_TP_1_LO, REG_A5XX_RBBM_PERFCTR_TP_1_HI, + REG_A5XX_TPL1_PERFCTR_TP_SEL_1, 61 }, + { REG_A5XX_RBBM_PERFCTR_TP_2_LO, REG_A5XX_RBBM_PERFCTR_TP_2_HI, + REG_A5XX_TPL1_PERFCTR_TP_SEL_2, 62 }, + { REG_A5XX_RBBM_PERFCTR_TP_3_LO, REG_A5XX_RBBM_PERFCTR_TP_3_HI, + REG_A5XX_TPL1_PERFCTR_TP_SEL_3, 63 }, + { REG_A5XX_RBBM_PERFCTR_TP_4_LO, REG_A5XX_RBBM_PERFCTR_TP_4_HI, + REG_A5XX_TPL1_PERFCTR_TP_SEL_4, 64 }, + { REG_A5XX_RBBM_PERFCTR_TP_5_LO, REG_A5XX_RBBM_PERFCTR_TP_5_HI, + REG_A5XX_TPL1_PERFCTR_TP_SEL_5, 65 }, + { REG_A5XX_RBBM_PERFCTR_TP_6_LO, REG_A5XX_RBBM_PERFCTR_TP_6_HI, + REG_A5XX_TPL1_PERFCTR_TP_SEL_6, 66 }, + { REG_A5XX_RBBM_PERFCTR_TP_7_LO, REG_A5XX_RBBM_PERFCTR_TP_7_HI, + REG_A5XX_TPL1_PERFCTR_TP_SEL_7, 67 }, +}; + +static struct adreno_counter a5xx_counters_tse[] = { + { REG_A5XX_RBBM_PERFCTR_TSE_0_LO, REG_A5XX_RBBM_PERFCTR_TSE_0_HI, + REG_A5XX_GRAS_PERFCTR_TSE_SEL_0, 44 }, + { REG_A5XX_RBBM_PERFCTR_TSE_1_LO, REG_A5XX_RBBM_PERFCTR_TSE_1_HI, + REG_A5XX_GRAS_PERFCTR_TSE_SEL_1, 45 }, + { REG_A5XX_RBBM_PERFCTR_TSE_2_LO, REG_A5XX_RBBM_PERFCTR_TSE_2_HI, + REG_A5XX_GRAS_PERFCTR_TSE_SEL_2, 46 }, + { REG_A5XX_RBBM_PERFCTR_TSE_3_LO, REG_A5XX_RBBM_PERFCTR_TSE_3_HI, + REG_A5XX_GRAS_PERFCTR_TSE_SEL_3, 47 }, +}; + +static struct adreno_counter a5xx_counters_uche[] = { + { REG_A5XX_RBBM_PERFCTR_UCHE_0_LO, REG_A5XX_RBBM_PERFCTR_UCHE_0_HI, + REG_A5XX_UCHE_PERFCTR_UCHE_SEL_0, 52 }, + { REG_A5XX_RBBM_PERFCTR_UCHE_1_LO, REG_A5XX_RBBM_PERFCTR_UCHE_1_HI, + REG_A5XX_UCHE_PERFCTR_UCHE_SEL_1, 53 }, + { REG_A5XX_RBBM_PERFCTR_UCHE_2_LO, REG_A5XX_RBBM_PERFCTR_UCHE_2_HI, + REG_A5XX_UCHE_PERFCTR_UCHE_SEL_2, 54 }, + { REG_A5XX_RBBM_PERFCTR_UCHE_3_LO, REG_A5XX_RBBM_PERFCTR_UCHE_3_HI, + REG_A5XX_UCHE_PERFCTR_UCHE_SEL_3, 55 }, + { REG_A5XX_RBBM_PERFCTR_UCHE_4_LO, REG_A5XX_RBBM_PERFCTR_UCHE_4_HI, + REG_A5XX_UCHE_PERFCTR_UCHE_SEL_4, 56 }, + { REG_A5XX_RBBM_PERFCTR_UCHE_5_LO, REG_A5XX_RBBM_PERFCTR_UCHE_5_HI, + REG_A5XX_UCHE_PERFCTR_UCHE_SEL_5, 57 }, + { REG_A5XX_RBBM_PERFCTR_UCHE_6_LO, REG_A5XX_RBBM_PERFCTR_UCHE_6_HI, + REG_A5XX_UCHE_PERFCTR_UCHE_SEL_6, 58 }, + { REG_A5XX_RBBM_PERFCTR_UCHE_7_LO, REG_A5XX_RBBM_PERFCTR_UCHE_7_HI, + REG_A5XX_UCHE_PERFCTR_UCHE_SEL_7, 59 }, +}; + +static struct adreno_counter a5xx_counters_vfd[] = { + { REG_A5XX_RBBM_PERFCTR_VFD_0_LO, REG_A5XX_RBBM_PERFCTR_VFD_0_HI, + REG_A5XX_VFD_PERFCTR_VFD_SEL_0, 20 }, + { REG_A5XX_RBBM_PERFCTR_VFD_1_LO, REG_A5XX_RBBM_PERFCTR_VFD_1_HI, + REG_A5XX_VFD_PERFCTR_VFD_SEL_1, 21 }, + { REG_A5XX_RBBM_PERFCTR_VFD_2_LO, REG_A5XX_RBBM_PERFCTR_VFD_2_HI, + REG_A5XX_VFD_PERFCTR_VFD_SEL_2, 22 }, + { REG_A5XX_RBBM_PERFCTR_VFD_3_LO, REG_A5XX_RBBM_PERFCTR_VFD_3_HI, + REG_A5XX_VFD_PERFCTR_VFD_SEL_3, 23 }, + { REG_A5XX_RBBM_PERFCTR_VFD_4_LO, REG_A5XX_RBBM_PERFCTR_VFD_4_HI, + REG_A5XX_VFD_PERFCTR_VFD_SEL_4, 24 }, + { REG_A5XX_RBBM_PERFCTR_VFD_5_LO, REG_A5XX_RBBM_PERFCTR_VFD_5_HI, + REG_A5XX_VFD_PERFCTR_VFD_SEL_5, 25 }, + { REG_A5XX_RBBM_PERFCTR_VFD_6_LO, REG_A5XX_RBBM_PERFCTR_VFD_6_HI, + REG_A5XX_VFD_PERFCTR_VFD_SEL_6, 26 }, + { REG_A5XX_RBBM_PERFCTR_VFD_7_LO, REG_A5XX_RBBM_PERFCTR_VFD_7_HI, + REG_A5XX_VFD_PERFCTR_VFD_SEL_7, 27 }, +}; + +static struct adreno_counter a5xx_counters_vpc[] = { + { REG_A5XX_RBBM_PERFCTR_VPC_0_LO, REG_A5XX_RBBM_PERFCTR_VPC_0_HI, + REG_A5XX_VPC_PERFCTR_VPC_SEL_0, 36 }, + { REG_A5XX_RBBM_PERFCTR_VPC_1_LO, REG_A5XX_RBBM_PERFCTR_VPC_1_HI, + REG_A5XX_VPC_PERFCTR_VPC_SEL_1, 37 }, + { REG_A5XX_RBBM_PERFCTR_VPC_2_LO, REG_A5XX_RBBM_PERFCTR_VPC_2_HI, + REG_A5XX_VPC_PERFCTR_VPC_SEL_2, 38 }, + { REG_A5XX_RBBM_PERFCTR_VPC_3_LO, REG_A5XX_RBBM_PERFCTR_VPC_3_HI, + REG_A5XX_VPC_PERFCTR_VPC_SEL_3, 39 }, +}; + +static struct adreno_counter a5xx_counters_vsc[] = { + { REG_A5XX_RBBM_PERFCTR_VSC_0_LO, REG_A5XX_RBBM_PERFCTR_VSC_0_HI, + REG_A5XX_VSC_PERFCTR_VSC_SEL_0, 88 }, + { REG_A5XX_RBBM_PERFCTR_VSC_1_LO, REG_A5XX_RBBM_PERFCTR_VSC_1_HI, + REG_A5XX_VSC_PERFCTR_VSC_SEL_1, 89 }, +}; + +static struct adreno_counter a5xx_counters_power_ccu[] = { + { REG_A5XX_CCU_POWER_COUNTER_0_LO, REG_A5XX_CCU_POWER_COUNTER_0_HI, + REG_A5XX_RB_POWERCTR_CCU_SEL_0 }, + { REG_A5XX_CCU_POWER_COUNTER_1_LO, REG_A5XX_CCU_POWER_COUNTER_1_HI, + REG_A5XX_RB_POWERCTR_CCU_SEL_1 }, +}; + +static struct adreno_counter a5xx_counters_power_cp[] = { + { REG_A5XX_CP_POWER_COUNTER_0_LO, REG_A5XX_CP_POWER_COUNTER_0_HI, + REG_A5XX_CP_POWERCTR_CP_SEL_0 }, + { REG_A5XX_CP_POWER_COUNTER_1_LO, REG_A5XX_CP_POWER_COUNTER_1_HI, + REG_A5XX_CP_POWERCTR_CP_SEL_1 }, + { REG_A5XX_CP_POWER_COUNTER_2_LO, REG_A5XX_CP_POWER_COUNTER_2_HI, + REG_A5XX_CP_POWERCTR_CP_SEL_2 }, + { REG_A5XX_CP_POWER_COUNTER_3_LO, REG_A5XX_CP_POWER_COUNTER_3_HI, + REG_A5XX_CP_POWERCTR_CP_SEL_3 }, +}; + +static struct adreno_counter a5xx_counters_power_rb[] = { + { REG_A5XX_RB_POWER_COUNTER_0_LO, REG_A5XX_RB_POWER_COUNTER_0_HI, + REG_A5XX_RB_POWERCTR_RB_SEL_0 }, + { REG_A5XX_RB_POWER_COUNTER_1_LO, REG_A5XX_RB_POWER_COUNTER_1_HI, + REG_A5XX_RB_POWERCTR_RB_SEL_1 }, + { REG_A5XX_RB_POWER_COUNTER_2_LO, REG_A5XX_RB_POWER_COUNTER_2_HI, + REG_A5XX_RB_POWERCTR_RB_SEL_2 }, + { REG_A5XX_RB_POWER_COUNTER_3_LO, REG_A5XX_RB_POWER_COUNTER_3_HI, + REG_A5XX_RB_POWERCTR_RB_SEL_3 }, +}; + +static struct adreno_counter a5xx_counters_power_sp[] = { + { REG_A5XX_SP_POWER_COUNTER_0_LO, REG_A5XX_SP_POWER_COUNTER_0_HI, + REG_A5XX_SP_POWERCTR_SP_SEL_0 }, + { REG_A5XX_SP_POWER_COUNTER_1_LO, REG_A5XX_SP_POWER_COUNTER_1_HI, + REG_A5XX_SP_POWERCTR_SP_SEL_1 }, + { REG_A5XX_SP_POWER_COUNTER_2_LO, REG_A5XX_SP_POWER_COUNTER_2_HI, + REG_A5XX_SP_POWERCTR_SP_SEL_2 }, + { REG_A5XX_SP_POWER_COUNTER_3_LO, REG_A5XX_SP_POWER_COUNTER_3_HI, + REG_A5XX_SP_POWERCTR_SP_SEL_3 }, +}; + +static struct adreno_counter a5xx_counters_power_tp[] = { + { REG_A5XX_TP_POWER_COUNTER_0_LO, REG_A5XX_TP_POWER_COUNTER_0_HI, + REG_A5XX_TPL1_POWERCTR_TP_SEL_0 }, + { REG_A5XX_TP_POWER_COUNTER_1_LO, REG_A5XX_TP_POWER_COUNTER_1_HI, + REG_A5XX_TPL1_POWERCTR_TP_SEL_1 }, + { REG_A5XX_TP_POWER_COUNTER_2_LO, REG_A5XX_TP_POWER_COUNTER_2_HI, + REG_A5XX_TPL1_POWERCTR_TP_SEL_2 }, + { REG_A5XX_TP_POWER_COUNTER_3_LO, REG_A5XX_TP_POWER_COUNTER_3_HI, + REG_A5XX_TPL1_POWERCTR_TP_SEL_3 }, +}; + +static struct adreno_counter a5xx_counters_power_uche[] = { + { REG_A5XX_UCHE_POWER_COUNTER_0_LO, REG_A5XX_UCHE_POWER_COUNTER_0_HI, + REG_A5XX_UCHE_POWERCTR_UCHE_SEL_0 }, + { REG_A5XX_UCHE_POWER_COUNTER_1_LO, REG_A5XX_UCHE_POWER_COUNTER_1_HI, + REG_A5XX_UCHE_POWERCTR_UCHE_SEL_1 }, + { REG_A5XX_UCHE_POWER_COUNTER_2_LO, REG_A5XX_UCHE_POWER_COUNTER_2_HI, + REG_A5XX_UCHE_POWERCTR_UCHE_SEL_2 }, + { REG_A5XX_UCHE_POWER_COUNTER_3_LO, REG_A5XX_UCHE_POWER_COUNTER_3_HI, + REG_A5XX_UCHE_POWERCTR_UCHE_SEL_3 }, +}; + +static struct adreno_counter a5xx_counters_vbif[] = { + { REG_A5XX_VBIF_PERF_CNT_LOW0, REG_A5XX_VBIF_PERF_CNT_HIGH0 }, + { REG_A5XX_VBIF_PERF_CNT_LOW1, REG_A5XX_VBIF_PERF_CNT_HIGH1 }, + { REG_A5XX_VBIF_PERF_CNT_LOW2, REG_A5XX_VBIF_PERF_CNT_HIGH2 }, + { REG_A5XX_VBIF_PERF_CNT_LOW3, REG_A5XX_VBIF_PERF_CNT_HIGH3 }, +}; + +static struct adreno_counter a5xx_counters_gpmu[] = { + { REG_A5XX_GPMU_POWER_COUNTER_0_LO, REG_A5XX_GPMU_POWER_COUNTER_0_HI }, + { REG_A5XX_GPMU_POWER_COUNTER_1_LO, REG_A5XX_GPMU_POWER_COUNTER_1_HI }, + { REG_A5XX_GPMU_POWER_COUNTER_2_LO, REG_A5XX_GPMU_POWER_COUNTER_2_HI }, + { REG_A5XX_GPMU_POWER_COUNTER_3_LO, REG_A5XX_GPMU_POWER_COUNTER_3_HI }, + { REG_A5XX_GPMU_POWER_COUNTER_4_LO, REG_A5XX_GPMU_POWER_COUNTER_4_HI }, + { REG_A5XX_GPMU_POWER_COUNTER_5_LO, REG_A5XX_GPMU_POWER_COUNTER_5_HI }, +}; + +static struct adreno_counter a5xx_counters_vbif_power[] = { + { REG_A5XX_VBIF_PERF_PWR_CNT_LOW0, REG_A5XX_VBIF_PERF_PWR_CNT_HIGH0 }, + { REG_A5XX_VBIF_PERF_PWR_CNT_LOW1, REG_A5XX_VBIF_PERF_PWR_CNT_HIGH1 }, + { REG_A5XX_VBIF_PERF_PWR_CNT_LOW2, REG_A5XX_VBIF_PERF_PWR_CNT_HIGH2 }, +}; + +static struct adreno_counter a5xx_counters_alwayson_power[] = { + { REG_A5XX_GPMU_ALWAYS_ON_COUNTER_LO, + REG_A5XX_GPMU_ALWAYS_ON_COUNTER_HI }, +}; + +#define DEFINE_COUNTER_GROUP(_n, _a, _get, _enable, _put, _save, _restore) \ +static struct adreno_counter_group _n = { \ + .counters = _a, \ + .nr_counters = ARRAY_SIZE(_a), \ + .lock = __SPIN_LOCK_UNLOCKED(_name.lock), \ + .funcs = { \ + .get = _get, \ + .enable = _enable, \ + .read = a5xx_counter_read, \ + .put = _put, \ + .save = _save, \ + .restore = _restore \ + }, \ +} + +#define COUNTER_GROUP(_name, _array) DEFINE_COUNTER_GROUP(_name, \ + _array, a5xx_counter_get, a5xx_counter_enable_cpu, a5xx_counter_put, \ + a5xx_counter_save, a5xx_counter_restore) + +#define SPTP_COUNTER_GROUP(_name, _array) DEFINE_COUNTER_GROUP(_name, \ + _array, a5xx_counter_get, a5xx_counter_enable_pm4, a5xx_counter_put, \ + a5xx_counter_save, a5xx_counter_restore) + +#define POWER_COUNTER_GROUP(_name, _array) DEFINE_COUNTER_GROUP(_name, \ + _array, a5xx_counter_get, a5xx_counter_enable_cpu, a5xx_counter_put, \ + NULL, NULL) + +/* "standard" counters */ +COUNTER_GROUP(a5xx_counter_group_cp, a5xx_counters_cp); +COUNTER_GROUP(a5xx_counter_group_rbbm, a5xx_counters_rbbm); +COUNTER_GROUP(a5xx_counter_group_pc, a5xx_counters_pc); +COUNTER_GROUP(a5xx_counter_group_vfd, a5xx_counters_vfd); +COUNTER_GROUP(a5xx_counter_group_vpc, a5xx_counters_vpc); +COUNTER_GROUP(a5xx_counter_group_ccu, a5xx_counters_ccu); +COUNTER_GROUP(a5xx_counter_group_cmp, a5xx_counters_cmp); +COUNTER_GROUP(a5xx_counter_group_tse, a5xx_counters_tse); +COUNTER_GROUP(a5xx_counter_group_ras, a5xx_counters_ras); +COUNTER_GROUP(a5xx_counter_group_uche, a5xx_counters_uche); +COUNTER_GROUP(a5xx_counter_group_rb, a5xx_counters_rb); +COUNTER_GROUP(a5xx_counter_group_vsc, a5xx_counters_vsc); +COUNTER_GROUP(a5xx_counter_group_lrz, a5xx_counters_lrz); + +/* SP/TP counters */ +SPTP_COUNTER_GROUP(a5xx_counter_group_hlsq, a5xx_counters_hlsq); +SPTP_COUNTER_GROUP(a5xx_counter_group_tp, a5xx_counters_tp); +SPTP_COUNTER_GROUP(a5xx_counter_group_sp, a5xx_counters_sp); + +/* Power counters */ +POWER_COUNTER_GROUP(a5xx_counter_group_power_ccu, a5xx_counters_power_ccu); +POWER_COUNTER_GROUP(a5xx_counter_group_power_cp, a5xx_counters_power_cp); +POWER_COUNTER_GROUP(a5xx_counter_group_power_rb, a5xx_counters_power_rb); +POWER_COUNTER_GROUP(a5xx_counter_group_power_sp, a5xx_counters_power_sp); +POWER_COUNTER_GROUP(a5xx_counter_group_power_tp, a5xx_counters_power_tp); +POWER_COUNTER_GROUP(a5xx_counter_group_power_uche, a5xx_counters_power_uche); + +DEFINE_COUNTER_GROUP(a5xx_counter_group_alwayson, a5xx_counters_alwayson, + a5xx_counter_get_fixed, NULL, NULL, NULL, NULL); +DEFINE_COUNTER_GROUP(a5xx_counter_group_vbif, a5xx_counters_vbif, + a5xx_counter_get, a5xx_counter_enable_vbif, a5xx_counter_put, + NULL, NULL); +DEFINE_COUNTER_GROUP(a5xx_counter_group_gpmu, a5xx_counters_gpmu, + a5xx_counter_get, a5xx_counter_enable_gpmu, a5xx_counter_put, + NULL, NULL); +DEFINE_COUNTER_GROUP(a5xx_counter_group_vbif_power, a5xx_counters_vbif_power, + a5xx_counter_get_fixed, a5xx_counter_enable_vbif_power, NULL, NULL, + NULL); +DEFINE_COUNTER_GROUP(a5xx_counter_group_alwayson_power, + a5xx_counters_alwayson_power, a5xx_counter_get_fixed, + a5xx_counter_enable_alwayson_power, NULL, NULL, NULL); + +static const struct adreno_counter_group *a5xx_counter_groups[] = { + [MSM_COUNTER_GROUP_ALWAYSON] = &a5xx_counter_group_alwayson, + [MSM_COUNTER_GROUP_CCU] = &a5xx_counter_group_ccu, + [MSM_COUNTER_GROUP_CMP] = &a5xx_counter_group_cmp, + [MSM_COUNTER_GROUP_CP] = &a5xx_counter_group_cp, + [MSM_COUNTER_GROUP_HLSQ] = &a5xx_counter_group_hlsq, + [MSM_COUNTER_GROUP_LRZ] = &a5xx_counter_group_lrz, + [MSM_COUNTER_GROUP_PC] = &a5xx_counter_group_pc, + [MSM_COUNTER_GROUP_RAS] = &a5xx_counter_group_ras, + [MSM_COUNTER_GROUP_RB] = &a5xx_counter_group_rb, + [MSM_COUNTER_GROUP_RBBM] = &a5xx_counter_group_rbbm, + [MSM_COUNTER_GROUP_SP] = &a5xx_counter_group_sp, + [MSM_COUNTER_GROUP_TP] = &a5xx_counter_group_tp, + [MSM_COUNTER_GROUP_TSE] = &a5xx_counter_group_tse, + [MSM_COUNTER_GROUP_UCHE] = &a5xx_counter_group_uche, + [MSM_COUNTER_GROUP_VFD] = &a5xx_counter_group_vfd, + [MSM_COUNTER_GROUP_VPC] = &a5xx_counter_group_vpc, + [MSM_COUNTER_GROUP_VSC] = &a5xx_counter_group_vsc, + [MSM_COUNTER_GROUP_VBIF] = &a5xx_counter_group_vbif, + [MSM_COUNTER_GROUP_GPMU_PWR] = &a5xx_counter_group_gpmu, + [MSM_COUNTER_GROUP_CCU_PWR] = &a5xx_counter_group_power_ccu, + [MSM_COUNTER_GROUP_CP_PWR] = &a5xx_counter_group_power_cp, + [MSM_COUNTER_GROUP_RB_PWR] = &a5xx_counter_group_power_rb, + [MSM_COUNTER_GROUP_SP_PWR] = &a5xx_counter_group_power_sp, + [MSM_COUNTER_GROUP_TP_PWR] = &a5xx_counter_group_power_tp, + [MSM_COUNTER_GROUP_UCHE_PWR] = &a5xx_counter_group_power_uche, + [MSM_COUNTER_GROUP_VBIF_PWR] = &a5xx_counter_group_vbif_power, + [MSM_COUNTER_GROUP_ALWAYSON_PWR] = + &a5xx_counter_group_alwayson_power, +}; + +void a5xx_counters_restore(struct msm_gpu *gpu) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(a5xx_counter_groups); i++) { + struct adreno_counter_group *group = + (struct adreno_counter_group *) a5xx_counter_groups[i]; + + if (group && group->funcs.restore) + group->funcs.restore(gpu, group); + + a5xx_counter_group_enable(gpu, group, true); + } +} + + +void a5xx_counters_save(struct msm_gpu *gpu) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(a5xx_counter_groups); i++) { + struct adreno_counter_group *group = + (struct adreno_counter_group *) a5xx_counter_groups[i]; + + if (group && group->funcs.save) + group->funcs.save(gpu, group); + } +} + +int a5xx_counters_init(struct adreno_gpu *adreno_gpu) +{ + adreno_gpu->counter_groups = a5xx_counter_groups; + adreno_gpu->nr_counter_groups = ARRAY_SIZE(a5xx_counter_groups); + + return 0; +} --- /dev/null 2019-10-24 16:47:25.704025805 +0200 +++ linux-4.4.115-fbx/drivers/gpu/drm/msm/adreno/a5xx_gpu.c 2019-01-22 16:16:23.483246225 +0100 @@ -0,0 +1,1439 @@ +/* Copyright (c) 2016-2018 The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include "msm_gem.h" +#include "msm_iommu.h" +#include "msm_trace.h" +#include "a5xx_gpu.h" + +#define SECURE_VA_START 0xc0000000 +#define SECURE_VA_SIZE SZ_256M + +static void a5xx_flush(struct msm_gpu *gpu, struct msm_ringbuffer *ring) +{ + struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); + struct a5xx_gpu *a5xx_gpu = to_a5xx_gpu(adreno_gpu); + uint32_t wptr; + unsigned long flags; + + spin_lock_irqsave(&ring->lock, flags); + + /* Copy the shadow to the actual register */ + ring->cur = ring->next; + + /* Make sure to wrap wptr if we need to */ + wptr = get_wptr(ring); + + spin_unlock_irqrestore(&ring->lock, flags); + + /* Make sure everything is posted before making a decision */ + mb(); + + /* Update HW if this is the current ring and we are not in preempt */ + if (a5xx_gpu->cur_ring == ring && !a5xx_in_preempt(a5xx_gpu)) + gpu_write(gpu, REG_A5XX_CP_RB_WPTR, wptr); +} + +static void a5xx_set_pagetable(struct msm_gpu *gpu, struct msm_ringbuffer *ring, + struct msm_gem_address_space *aspace) +{ + struct msm_mmu *mmu = aspace->mmu; + struct msm_iommu *iommu = to_msm_iommu(mmu); + + if (!iommu->ttbr0) + return; + + /* Turn off protected mode */ + OUT_PKT7(ring, CP_SET_PROTECTED_MODE, 1); + OUT_RING(ring, 0); + + /* Turn on APIV mode to access critical regions */ + OUT_PKT4(ring, REG_A5XX_CP_CNTL, 1); + OUT_RING(ring, 1); + + /* Make sure the ME is syncronized before staring the update */ + OUT_PKT7(ring, CP_WAIT_FOR_ME, 0); + + /* Execute the table update */ + OUT_PKT7(ring, CP_SMMU_TABLE_UPDATE, 3); + OUT_RING(ring, lower_32_bits(iommu->ttbr0)); + OUT_RING(ring, upper_32_bits(iommu->ttbr0)); + OUT_RING(ring, iommu->contextidr); + + /* + * Write the new TTBR0 to the preemption records - this will be used to + * reload the pagetable if the current ring gets preempted out. + */ + OUT_PKT7(ring, CP_MEM_WRITE, 4); + OUT_RING(ring, lower_32_bits(rbmemptr(ring, ttbr0))); + OUT_RING(ring, upper_32_bits(rbmemptr(ring, ttbr0))); + OUT_RING(ring, lower_32_bits(iommu->ttbr0)); + OUT_RING(ring, upper_32_bits(iommu->ttbr0)); + + /* Also write the current contextidr (ASID) */ + OUT_PKT7(ring, CP_MEM_WRITE, 3); + OUT_RING(ring, lower_32_bits(rbmemptr(ring, contextidr))); + OUT_RING(ring, upper_32_bits(rbmemptr(ring, contextidr))); + OUT_RING(ring, iommu->contextidr); + + /* Invalidate the draw state so we start off fresh */ + OUT_PKT7(ring, CP_SET_DRAW_STATE, 3); + OUT_RING(ring, 0x40000); + OUT_RING(ring, 1); + OUT_RING(ring, 0); + + /* Turn off APRIV */ + OUT_PKT4(ring, REG_A5XX_CP_CNTL, 1); + OUT_RING(ring, 0); + + /* Turn off protected mode */ + OUT_PKT7(ring, CP_SET_PROTECTED_MODE, 1); + OUT_RING(ring, 1); +} + +/* Inline PM4 code to get the current value of the 19.2 Mhz always on counter */ +static void a5xx_get_ticks(struct msm_ringbuffer *ring, uint64_t iova) +{ + /* + * Set bit[30] to make this command a 64 bit write operation. + * bits[18-29] is to specify number of consecutive registers + * to copy, so set this space with 2, since we want to copy + * data from REG_A5XX_RBBM_ALWAYSON_COUNTER_LO and [HI]. + */ + + OUT_PKT7(ring, CP_REG_TO_MEM, 3); + OUT_RING(ring, REG_A5XX_RBBM_ALWAYSON_COUNTER_LO | + (1 << 30) | (2 << 18)); + OUT_RING(ring, lower_32_bits(iova)); + OUT_RING(ring, upper_32_bits(iova)); +} + +static void a5xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit) +{ + struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); + struct a5xx_gpu *a5xx_gpu = to_a5xx_gpu(adreno_gpu); + struct msm_ringbuffer *ring = gpu->rb[submit->ring]; + unsigned int i, ibs = 0; + unsigned long flags; + u64 ticks; + ktime_t time; + + a5xx_set_pagetable(gpu, ring, submit->aspace); + + OUT_PKT7(ring, CP_PREEMPT_ENABLE_GLOBAL, 1); + OUT_RING(ring, 0x02); + + /* Turn off protected mode to write to special registers */ + OUT_PKT7(ring, CP_SET_PROTECTED_MODE, 1); + OUT_RING(ring, 0); + + /* Set the save preemption record for the ring/command */ + OUT_PKT4(ring, REG_A5XX_CP_CONTEXT_SWITCH_SAVE_ADDR_LO, 2); + OUT_RING(ring, lower_32_bits(a5xx_gpu->preempt_iova[submit->ring])); + OUT_RING(ring, upper_32_bits(a5xx_gpu->preempt_iova[submit->ring])); + + /* Turn back on protected mode */ + OUT_PKT7(ring, CP_SET_PROTECTED_MODE, 1); + OUT_RING(ring, 1); + + /* Enable local preemption for finegrain preemption */ + OUT_PKT7(ring, CP_PREEMPT_ENABLE_GLOBAL, 1); + OUT_RING(ring, 0x02); + + /* Allow CP_CONTEXT_SWITCH_YIELD packets in the IB2 */ + OUT_PKT7(ring, CP_YIELD_ENABLE, 1); + OUT_RING(ring, 0x02); + + /* Turn on secure mode if the submission is secure */ + if (submit->secure) { + OUT_PKT7(ring, CP_SET_SECURE_MODE, 1); + OUT_RING(ring, 1); + } + + /* Record the GPU ticks at command start for kernel side profiling */ + a5xx_get_ticks(ring, + RING_TICKS_IOVA(ring, submit->tick_index, started)); + + /* And for the user profiling too if it is enabled */ + if (submit->profile_buf_iova) + a5xx_get_ticks(ring, submit->profile_buf_iova + + offsetof(struct drm_msm_gem_submit_profile_buffer, + ticks_submitted)); + + /* Submit the commands */ + for (i = 0; i < submit->nr_cmds; i++) { + switch (submit->cmd[i].type) { + case MSM_SUBMIT_CMD_IB_TARGET_BUF: + case MSM_SUBMIT_CMD_PROFILE_BUF: + break; + case MSM_SUBMIT_CMD_BUF: + OUT_PKT7(ring, CP_INDIRECT_BUFFER_PFE, 3); + OUT_RING(ring, lower_32_bits(submit->cmd[i].iova)); + OUT_RING(ring, upper_32_bits(submit->cmd[i].iova)); + OUT_RING(ring, submit->cmd[i].size); + ibs++; + break; + } + } + + /* + * Write the render mode to NULL (0) to indicate to the CP that the IBs + * are done rendering - otherwise a lucky preemption would start + * replaying from the last checkpoint + */ + OUT_PKT7(ring, CP_SET_RENDER_MODE, 5); + OUT_RING(ring, 0); + OUT_RING(ring, 0); + OUT_RING(ring, 0); + OUT_RING(ring, 0); + OUT_RING(ring, 0); + + /* Turn off IB level preemptions */ + OUT_PKT7(ring, CP_YIELD_ENABLE, 1); + OUT_RING(ring, 0x01); + + /* Record the GPU ticks at command retire for kernel side profiling */ + a5xx_get_ticks(ring, + RING_TICKS_IOVA(ring, submit->tick_index, retired)); + + /* Record the always on counter after command execution */ + if (submit->profile_buf_iova) + a5xx_get_ticks(ring, submit->profile_buf_iova + + offsetof(struct drm_msm_gem_submit_profile_buffer, + ticks_retired)); + + /* Write the fence to the scratch register */ + OUT_PKT4(ring, REG_A5XX_CP_SCRATCH_REG(2), 1); + OUT_RING(ring, submit->fence); + + /* + * Execute a CACHE_FLUSH_TS event. This will ensure that the + * timestamp is written to the memory and then triggers the interrupt + */ + OUT_PKT7(ring, CP_EVENT_WRITE, 4); + OUT_RING(ring, CACHE_FLUSH_TS | (1 << 31)); + + OUT_RING(ring, lower_32_bits(rbmemptr(ring, fence))); + OUT_RING(ring, upper_32_bits(rbmemptr(ring, fence))); + OUT_RING(ring, submit->fence); + + if (submit->secure) { + OUT_PKT7(ring, CP_SET_SECURE_MODE, 1); + OUT_RING(ring, 0); + } + + /* Yield the floor on command completion */ + OUT_PKT7(ring, CP_CONTEXT_SWITCH_YIELD, 4); + /* + * If dword[2:1] are non zero, they specify an address for the CP to + * write the value of dword[3] to on preemption complete. Write 0 to + * skip the write + */ + OUT_RING(ring, 0x00); + OUT_RING(ring, 0x00); + /* Data value - not used if the address above is 0 */ + OUT_RING(ring, 0x01); + /* Set bit 0 to trigger an interrupt on preempt complete */ + OUT_RING(ring, 0x01); + + /* + * Get the current kernel time and ticks with interrupts off so we don't + * get interrupted between the operations and skew the numbers + */ + + local_irq_save(flags); + ticks = gpu_read64(gpu, REG_A5XX_RBBM_ALWAYSON_COUNTER_LO, + REG_A5XX_RBBM_ALWAYSON_COUNTER_HI); + time = ktime_get_raw(); + local_irq_restore(flags); + + if (submit->profile_buf) { + struct timespec64 ts = ktime_to_timespec64(time); + + /* Write the data into the user-specified profile buffer */ + submit->profile_buf->time.tv_sec = ts.tv_sec; + submit->profile_buf->time.tv_nsec = ts.tv_nsec; + submit->profile_buf->ticks_queued = ticks; + } + + trace_msm_submitted(submit, ticks, ktime_to_ns(time)); + + a5xx_flush(gpu, ring); + + /* Check to see if we need to start preemption */ + a5xx_preempt_trigger(gpu); +} + +static const struct { + u32 offset; + u32 value; +} a5xx_hwcg[] = { + {REG_A5XX_RBBM_CLOCK_CNTL_SP0, 0x02222222}, + {REG_A5XX_RBBM_CLOCK_CNTL_SP1, 0x02222222}, + {REG_A5XX_RBBM_CLOCK_CNTL_SP2, 0x02222222}, + {REG_A5XX_RBBM_CLOCK_CNTL_SP3, 0x02222222}, + {REG_A5XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220}, + {REG_A5XX_RBBM_CLOCK_CNTL2_SP1, 0x02222220}, + {REG_A5XX_RBBM_CLOCK_CNTL2_SP2, 0x02222220}, + {REG_A5XX_RBBM_CLOCK_CNTL2_SP3, 0x02222220}, + {REG_A5XX_RBBM_CLOCK_HYST_SP0, 0x0000F3CF}, + {REG_A5XX_RBBM_CLOCK_HYST_SP1, 0x0000F3CF}, + {REG_A5XX_RBBM_CLOCK_HYST_SP2, 0x0000F3CF}, + {REG_A5XX_RBBM_CLOCK_HYST_SP3, 0x0000F3CF}, + {REG_A5XX_RBBM_CLOCK_DELAY_SP0, 0x00000080}, + {REG_A5XX_RBBM_CLOCK_DELAY_SP1, 0x00000080}, + {REG_A5XX_RBBM_CLOCK_DELAY_SP2, 0x00000080}, + {REG_A5XX_RBBM_CLOCK_DELAY_SP3, 0x00000080}, + {REG_A5XX_RBBM_CLOCK_CNTL_TP0, 0x22222222}, + {REG_A5XX_RBBM_CLOCK_CNTL_TP1, 0x22222222}, + {REG_A5XX_RBBM_CLOCK_CNTL_TP2, 0x22222222}, + {REG_A5XX_RBBM_CLOCK_CNTL_TP3, 0x22222222}, + {REG_A5XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222}, + {REG_A5XX_RBBM_CLOCK_CNTL2_TP1, 0x22222222}, + {REG_A5XX_RBBM_CLOCK_CNTL2_TP2, 0x22222222}, + {REG_A5XX_RBBM_CLOCK_CNTL2_TP3, 0x22222222}, + {REG_A5XX_RBBM_CLOCK_CNTL3_TP0, 0x00002222}, + {REG_A5XX_RBBM_CLOCK_CNTL3_TP1, 0x00002222}, + {REG_A5XX_RBBM_CLOCK_CNTL3_TP2, 0x00002222}, + {REG_A5XX_RBBM_CLOCK_CNTL3_TP3, 0x00002222}, + {REG_A5XX_RBBM_CLOCK_HYST_TP0, 0x77777777}, + {REG_A5XX_RBBM_CLOCK_HYST_TP1, 0x77777777}, + {REG_A5XX_RBBM_CLOCK_HYST_TP2, 0x77777777}, + {REG_A5XX_RBBM_CLOCK_HYST_TP3, 0x77777777}, + {REG_A5XX_RBBM_CLOCK_HYST2_TP0, 0x77777777}, + {REG_A5XX_RBBM_CLOCK_HYST2_TP1, 0x77777777}, + {REG_A5XX_RBBM_CLOCK_HYST2_TP2, 0x77777777}, + {REG_A5XX_RBBM_CLOCK_HYST2_TP3, 0x77777777}, + {REG_A5XX_RBBM_CLOCK_HYST3_TP0, 0x00007777}, + {REG_A5XX_RBBM_CLOCK_HYST3_TP1, 0x00007777}, + {REG_A5XX_RBBM_CLOCK_HYST3_TP2, 0x00007777}, + {REG_A5XX_RBBM_CLOCK_HYST3_TP3, 0x00007777}, + {REG_A5XX_RBBM_CLOCK_DELAY_TP0, 0x11111111}, + {REG_A5XX_RBBM_CLOCK_DELAY_TP1, 0x11111111}, + {REG_A5XX_RBBM_CLOCK_DELAY_TP2, 0x11111111}, + {REG_A5XX_RBBM_CLOCK_DELAY_TP3, 0x11111111}, + {REG_A5XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111}, + {REG_A5XX_RBBM_CLOCK_DELAY2_TP1, 0x11111111}, + {REG_A5XX_RBBM_CLOCK_DELAY2_TP2, 0x11111111}, + {REG_A5XX_RBBM_CLOCK_DELAY2_TP3, 0x11111111}, + {REG_A5XX_RBBM_CLOCK_DELAY3_TP0, 0x00001111}, + {REG_A5XX_RBBM_CLOCK_DELAY3_TP1, 0x00001111}, + {REG_A5XX_RBBM_CLOCK_DELAY3_TP2, 0x00001111}, + {REG_A5XX_RBBM_CLOCK_DELAY3_TP3, 0x00001111}, + {REG_A5XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222}, + {REG_A5XX_RBBM_CLOCK_CNTL2_UCHE, 0x22222222}, + {REG_A5XX_RBBM_CLOCK_CNTL3_UCHE, 0x22222222}, + {REG_A5XX_RBBM_CLOCK_CNTL4_UCHE, 0x00222222}, + {REG_A5XX_RBBM_CLOCK_HYST_UCHE, 0x00444444}, + {REG_A5XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002}, + {REG_A5XX_RBBM_CLOCK_CNTL_RB0, 0x22222222}, + {REG_A5XX_RBBM_CLOCK_CNTL_RB1, 0x22222222}, + {REG_A5XX_RBBM_CLOCK_CNTL_RB2, 0x22222222}, + {REG_A5XX_RBBM_CLOCK_CNTL_RB3, 0x22222222}, + {REG_A5XX_RBBM_CLOCK_CNTL2_RB0, 0x00222222}, + {REG_A5XX_RBBM_CLOCK_CNTL2_RB1, 0x00222222}, + {REG_A5XX_RBBM_CLOCK_CNTL2_RB2, 0x00222222}, + {REG_A5XX_RBBM_CLOCK_CNTL2_RB3, 0x00222222}, + {REG_A5XX_RBBM_CLOCK_CNTL_CCU0, 0x00022220}, + {REG_A5XX_RBBM_CLOCK_CNTL_CCU1, 0x00022220}, + {REG_A5XX_RBBM_CLOCK_CNTL_CCU2, 0x00022220}, + {REG_A5XX_RBBM_CLOCK_CNTL_CCU3, 0x00022220}, + {REG_A5XX_RBBM_CLOCK_CNTL_RAC, 0x05522222}, + {REG_A5XX_RBBM_CLOCK_CNTL2_RAC, 0x00505555}, + {REG_A5XX_RBBM_CLOCK_HYST_RB_CCU0, 0x04040404}, + {REG_A5XX_RBBM_CLOCK_HYST_RB_CCU1, 0x04040404}, + {REG_A5XX_RBBM_CLOCK_HYST_RB_CCU2, 0x04040404}, + {REG_A5XX_RBBM_CLOCK_HYST_RB_CCU3, 0x04040404}, + {REG_A5XX_RBBM_CLOCK_HYST_RAC, 0x07444044}, + {REG_A5XX_RBBM_CLOCK_DELAY_RB_CCU_L1_0, 0x00000002}, + {REG_A5XX_RBBM_CLOCK_DELAY_RB_CCU_L1_1, 0x00000002}, + {REG_A5XX_RBBM_CLOCK_DELAY_RB_CCU_L1_2, 0x00000002}, + {REG_A5XX_RBBM_CLOCK_DELAY_RB_CCU_L1_3, 0x00000002}, + {REG_A5XX_RBBM_CLOCK_DELAY_RAC, 0x00010011}, + {REG_A5XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222}, + {REG_A5XX_RBBM_CLOCK_MODE_GPC, 0x02222222}, + {REG_A5XX_RBBM_CLOCK_MODE_VFD, 0x00002222}, + {REG_A5XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000}, + {REG_A5XX_RBBM_CLOCK_HYST_GPC, 0x04104004}, + {REG_A5XX_RBBM_CLOCK_HYST_VFD, 0x00000000}, + {REG_A5XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000}, + {REG_A5XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000}, + {REG_A5XX_RBBM_CLOCK_DELAY_GPC, 0x00000200}, + {REG_A5XX_RBBM_CLOCK_DELAY_VFD, 0x00002222} +}; + +void a5xx_set_hwcg(struct msm_gpu *gpu, bool state) +{ + struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); + struct a5xx_gpu *a5xx_gpu = to_a5xx_gpu(adreno_gpu); + unsigned int i; + + for (i = 0; i < ARRAY_SIZE(a5xx_hwcg); i++) + gpu_write(gpu, a5xx_hwcg[i].offset, + state ? a5xx_hwcg[i].value : 0); + + /* There are a few additional registers just for A540 */ + if (adreno_is_a540(adreno_gpu)) { + gpu_write(gpu, REG_A5XX_RBBM_CLOCK_DELAY_GPMU, + state ? 0x770 : 0); + gpu_write(gpu, REG_A5XX_RBBM_CLOCK_HYST_GPMU, + state ? 0x004 : 0); + } + + gpu_write(gpu, REG_A5XX_RBBM_CLOCK_CNTL, state ? 0xAAA8AA00 : 0); + gpu_write(gpu, REG_A5XX_RBBM_ISDB_CNT, state ? 0x182 : 0x180); + + if (state) + set_bit(A5XX_HWCG_ENABLED, &a5xx_gpu->flags); + else + clear_bit(A5XX_HWCG_ENABLED, &a5xx_gpu->flags); +} + +static int a5xx_me_init(struct msm_gpu *gpu) +{ + struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); + struct msm_ringbuffer *ring = gpu->rb[0]; + + OUT_PKT7(ring, CP_ME_INIT, 8); + + OUT_RING(ring, 0x0000002F); + + /* Enable multiple hardware contexts */ + OUT_RING(ring, 0x00000003); + + /* Enable error detection */ + OUT_RING(ring, 0x20000000); + + /* Don't enable header dump */ + OUT_RING(ring, 0x00000000); + OUT_RING(ring, 0x00000000); + + /* Specify workarounds for various microcode issues */ + if (adreno_is_a530(adreno_gpu)) { + /* Workaround for token end syncs + * Force a WFI after every direct-render 3D mode draw and every + * 2D mode 3 draw + */ + OUT_RING(ring, 0x0000000B); + } else { + /* No workarounds enabled */ + OUT_RING(ring, 0x00000000); + } + + OUT_RING(ring, 0x00000000); + OUT_RING(ring, 0x00000000); + + gpu->funcs->flush(gpu, ring); + return a5xx_idle(gpu, ring) ? 0 : -EINVAL; +} + +static int a5xx_preempt_start(struct msm_gpu *gpu) +{ + struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); + struct a5xx_gpu *a5xx_gpu = to_a5xx_gpu(adreno_gpu); + struct msm_ringbuffer *ring = gpu->rb[0]; + + if (gpu->nr_rings == 1) + return 0; + + /* Turn off protected mode to write to special registers */ + OUT_PKT7(ring, CP_SET_PROTECTED_MODE, 1); + OUT_RING(ring, 0); + + /* Set the save preemption record for the ring/command */ + OUT_PKT4(ring, REG_A5XX_CP_CONTEXT_SWITCH_SAVE_ADDR_LO, 2); + OUT_RING(ring, lower_32_bits(a5xx_gpu->preempt_iova[ring->id])); + OUT_RING(ring, upper_32_bits(a5xx_gpu->preempt_iova[ring->id])); + + /* Turn back on protected mode */ + OUT_PKT7(ring, CP_SET_PROTECTED_MODE, 1); + OUT_RING(ring, 1); + + OUT_PKT7(ring, CP_PREEMPT_ENABLE_GLOBAL, 1); + OUT_RING(ring, 0x00); + + OUT_PKT7(ring, CP_PREEMPT_ENABLE_LOCAL, 1); + OUT_RING(ring, 0x01); + + OUT_PKT7(ring, CP_YIELD_ENABLE, 1); + OUT_RING(ring, 0x01); + + /* Yield the floor on command completion */ + OUT_PKT7(ring, CP_CONTEXT_SWITCH_YIELD, 4); + OUT_RING(ring, 0x00); + OUT_RING(ring, 0x00); + OUT_RING(ring, 0x01); + OUT_RING(ring, 0x01); + + gpu->funcs->flush(gpu, ring); + + return a5xx_idle(gpu, ring) ? 0 : -EINVAL; +} + + +static struct drm_gem_object *a5xx_ucode_load_bo(struct msm_gpu *gpu, + const struct firmware *fw, u64 *iova) +{ + struct drm_gem_object *bo; + void *ptr; + + ptr = msm_gem_kernel_new(gpu->dev, fw->size - 4, + MSM_BO_UNCACHED | MSM_BO_GPU_READONLY, gpu->aspace, &bo, iova); + + if (IS_ERR(ptr)) + return ERR_CAST(ptr); + + memcpy(ptr, &fw->data[4], fw->size - 4); + return bo; +} + +static int a5xx_ucode_init(struct msm_gpu *gpu) +{ + struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); + struct a5xx_gpu *a5xx_gpu = to_a5xx_gpu(adreno_gpu); + int ret; + + if (!a5xx_gpu->pm4_bo) { + a5xx_gpu->pm4_bo = a5xx_ucode_load_bo(gpu, adreno_gpu->pm4, + &a5xx_gpu->pm4_iova); + + if (IS_ERR(a5xx_gpu->pm4_bo)) { + ret = PTR_ERR(a5xx_gpu->pm4_bo); + a5xx_gpu->pm4_bo = NULL; + dev_err(gpu->dev->dev, "could not allocate PM4: %d\n", + ret); + return ret; + } + } + + if (!a5xx_gpu->pfp_bo) { + a5xx_gpu->pfp_bo = a5xx_ucode_load_bo(gpu, adreno_gpu->pfp, + &a5xx_gpu->pfp_iova); + + if (IS_ERR(a5xx_gpu->pfp_bo)) { + ret = PTR_ERR(a5xx_gpu->pfp_bo); + a5xx_gpu->pfp_bo = NULL; + dev_err(gpu->dev->dev, "could not allocate PFP: %d\n", + ret); + return ret; + } + } + + gpu_write64(gpu, REG_A5XX_CP_ME_INSTR_BASE_LO, + REG_A5XX_CP_ME_INSTR_BASE_HI, a5xx_gpu->pm4_iova); + + gpu_write64(gpu, REG_A5XX_CP_PFP_INSTR_BASE_LO, + REG_A5XX_CP_PFP_INSTR_BASE_HI, a5xx_gpu->pfp_iova); + + return 0; +} + +#ifdef CONFIG_MSM_SUBSYSTEM_RESTART + +#include +#include + +static void a5xx_zap_shader_init(struct msm_gpu *gpu) +{ + struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); + struct a5xx_gpu *a5xx_gpu = to_a5xx_gpu(adreno_gpu); + const char *name; + void *ptr; + + /* If no zap shader was defined, we'll assume that none is needed */ + if (of_property_read_string(GPU_OF_NODE(gpu), "qcom,zap-shader", &name)) + return; + + /* + * If the zap shader has already been loaded then just ask the SCM to + * re-initialize the registers (not needed if CPZ retention is a thing) + */ + if (test_bit(A5XX_ZAP_SHADER_LOADED, &a5xx_gpu->flags)) { + int ret; + struct scm_desc desc = { 0 }; + + if (of_property_read_bool(GPU_OF_NODE(gpu), + "qcom,cpz-retention")) + return; + + desc.args[0] = 0; + desc.args[1] = 13; + desc.arginfo = SCM_ARGS(2); + + ret = scm_call2(SCM_SIP_FNID(SCM_SVC_BOOT, 0x0A), &desc); + if (ret) + DRM_ERROR( + "%s: zap-shader resume failed with error %d\n", + gpu->name, ret); + + return; + } + + ptr = subsystem_get(name); + + if (IS_ERR_OR_NULL(ptr)) { + DRM_ERROR("%s: Unable to load the zap shader: %ld\n", gpu->name, + IS_ERR(ptr) ? PTR_ERR(ptr) : -ENODEV); + } else { + set_bit(A5XX_ZAP_SHADER_LOADED, &a5xx_gpu->flags); + } +} +#else +static void a5xx_zap_shader_init(struct msm_gpu *gpu) +{ + if (of_find_property(GPU_OF_NODE(gpu), "qcom,zap-shader", NULL)) + return; + + DRM_INFO_ONCE("%s: Zap shader is defined but loader isn't available\n", + gpu->name); +} +#endif + +#define A5XX_INT_MASK (A5XX_RBBM_INT_0_MASK_RBBM_AHB_ERROR | \ + A5XX_RBBM_INT_0_MASK_RBBM_TRANSFER_TIMEOUT | \ + A5XX_RBBM_INT_0_MASK_RBBM_ME_MS_TIMEOUT | \ + A5XX_RBBM_INT_0_MASK_RBBM_PFP_MS_TIMEOUT | \ + A5XX_RBBM_INT_0_MASK_RBBM_ETS_MS_TIMEOUT | \ + A5XX_RBBM_INT_0_MASK_RBBM_ATB_ASYNC_OVERFLOW | \ + A5XX_RBBM_INT_0_MASK_CP_HW_ERROR | \ + A5XX_RBBM_INT_0_MASK_MISC_HANG_DETECT | \ + A5XX_RBBM_INT_0_MASK_CP_SW | \ + A5XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS | \ + A5XX_RBBM_INT_0_MASK_UCHE_OOB_ACCESS | \ + A5XX_RBBM_INT_0_MASK_GPMU_VOLTAGE_DROOP) + +static int a5xx_hw_init(struct msm_gpu *gpu) +{ + struct msm_drm_private *priv = gpu->dev->dev_private; + struct platform_device *pdev = priv->gpu_pdev; + struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); + struct a5xx_gpu *a5xx_gpu = to_a5xx_gpu(adreno_gpu); + int ret, bit = 0; + + pm_qos_update_request(&gpu->pm_qos_req_dma, 101); + + gpu_write(gpu, REG_A5XX_VBIF_ROUND_ROBIN_QOS_ARB, 0x00000003); + if (adreno_is_a540(adreno_gpu)) + gpu_write(gpu, REG_A5XX_VBIF_GATE_OFF_WRREQ_EN, 0x00000009); + + /* Make all blocks contribute to the GPU BUSY perf counter */ + gpu_write(gpu, REG_A5XX_RBBM_PERFCTR_GPU_BUSY_MASKED, 0xFFFFFFFF); + + /* Enable RBBM error reporting bits */ + gpu_write(gpu, REG_A5XX_RBBM_AHB_CNTL0, 0x00000001); + + if (adreno_gpu->quirks & ADRENO_QUIRK_FAULT_DETECT_MASK) { + /* + * Mask out the activity signals from RB1-3 to avoid false + * positives + */ + + gpu_write(gpu, REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL11, + 0xF0000000); + gpu_write(gpu, REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL12, + 0xFFFFFFFF); + gpu_write(gpu, REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL13, + 0xFFFFFFFF); + gpu_write(gpu, REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL14, + 0xFFFFFFFF); + gpu_write(gpu, REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL15, + 0xFFFFFFFF); + gpu_write(gpu, REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL16, + 0xFFFFFFFF); + gpu_write(gpu, REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL17, + 0xFFFFFFFF); + gpu_write(gpu, REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL18, + 0xFFFFFFFF); + } + + /* Enable fault detection */ + gpu_write(gpu, REG_A5XX_RBBM_INTERFACE_HANG_INT_CNTL, + (1 << 30) | 0xFFFF); + + /* Turn on performance counters */ + gpu_write(gpu, REG_A5XX_RBBM_PERFCTR_CNTL, 0x01); + + /* Increase VFD cache access so LRZ and other data gets evicted less */ + gpu_write(gpu, REG_A5XX_UCHE_CACHE_WAYS, 0x02); + + /* Disable L2 bypass in the UCHE */ + gpu_write(gpu, REG_A5XX_UCHE_TRAP_BASE_LO, 0xFFFF0000); + gpu_write(gpu, REG_A5XX_UCHE_TRAP_BASE_HI, 0x0001FFFF); + gpu_write(gpu, REG_A5XX_UCHE_WRITE_THRU_BASE_LO, 0xFFFF0000); + gpu_write(gpu, REG_A5XX_UCHE_WRITE_THRU_BASE_HI, 0x0001FFFF); + + /* Set the GMEM VA range [0x100000:0x100000 + gpu->gmem - 1] */ + gpu_write64(gpu, REG_A5XX_UCHE_GMEM_RANGE_MIN_LO, + REG_A5XX_UCHE_GMEM_RANGE_MIN_HI, 0x00100000); + + gpu_write64(gpu, REG_A5XX_UCHE_GMEM_RANGE_MAX_LO, + REG_A5XX_UCHE_GMEM_RANGE_MAX_HI, + 0x00100000 + adreno_gpu->gmem - 1); + + gpu_write(gpu, REG_A5XX_CP_MEQ_THRESHOLDS, 0x40); + gpu_write(gpu, REG_A5XX_CP_MERCIU_SIZE, 0x40); + gpu_write(gpu, REG_A5XX_CP_ROQ_THRESHOLDS_2, 0x80000060); + gpu_write(gpu, REG_A5XX_CP_ROQ_THRESHOLDS_1, 0x40201B16); + + gpu_write(gpu, REG_A5XX_PC_DBG_ECO_CNTL, (0x400 << 11 | 0x300 << 22)); + + if (adreno_gpu->quirks & ADRENO_QUIRK_TWO_PASS_USE_WFI) + gpu_rmw(gpu, REG_A5XX_PC_DBG_ECO_CNTL, 0, (1 << 8)); + + gpu_write(gpu, REG_A5XX_PC_DBG_ECO_CNTL, 0xc0200100); + + /* Enable USE_RETENTION_FLOPS */ + gpu_write(gpu, REG_A5XX_CP_CHICKEN_DBG, 0x02000000); + + /* Enable ME/PFP split notification */ + gpu_write(gpu, REG_A5XX_RBBM_AHB_CNTL1, 0xA6FFFFFF); + + /* Enable HWCG */ + a5xx_set_hwcg(gpu, true); + + gpu_write(gpu, REG_A5XX_RBBM_AHB_CNTL2, 0x0000003F); + + /* Set the highest bank bit if specified in the device tree */ + if (!of_property_read_u32(pdev->dev.of_node, "qcom,highest-bank-bit", + &bit)) { + if (bit >= 13 && bit <= 16) { + bit -= 13; + + gpu_write(gpu, REG_A5XX_TPL1_MODE_CNTL, bit << 7); + gpu_write(gpu, REG_A5XX_RB_MODE_CNTL, bit << 1); + + if (adreno_is_a540(adreno_gpu)) + gpu_write(gpu, REG_A5XX_UCHE_DBG_ECO_CNTL_2, + bit); + } + } + + /* Try to load and initialize the zap shader if applicable */ + a5xx_zap_shader_init(gpu); + + /* Protect registers from the CP */ + gpu_write(gpu, REG_A5XX_CP_PROTECT_CNTL, 0x00000007); + + /* RBBM */ + gpu_write(gpu, REG_A5XX_CP_PROTECT(0), ADRENO_PROTECT_RW(0x04, 4)); + gpu_write(gpu, REG_A5XX_CP_PROTECT(1), ADRENO_PROTECT_RW(0x08, 8)); + gpu_write(gpu, REG_A5XX_CP_PROTECT(2), ADRENO_PROTECT_RW(0x10, 16)); + gpu_write(gpu, REG_A5XX_CP_PROTECT(3), ADRENO_PROTECT_RW(0x20, 32)); + gpu_write(gpu, REG_A5XX_CP_PROTECT(4), ADRENO_PROTECT_RW(0x40, 64)); + gpu_write(gpu, REG_A5XX_CP_PROTECT(5), ADRENO_PROTECT_RW(0x80, 64)); + + /* Content protect */ + gpu_write(gpu, REG_A5XX_CP_PROTECT(6), + ADRENO_PROTECT_RW(REG_A5XX_RBBM_SECVID_TSB_TRUSTED_BASE_LO, + 16)); + gpu_write(gpu, REG_A5XX_CP_PROTECT(7), + ADRENO_PROTECT_RW(REG_A5XX_RBBM_SECVID_TRUST_CNTL, 2)); + + /* CP */ + gpu_write(gpu, REG_A5XX_CP_PROTECT(8), ADRENO_PROTECT_RW(0x800, 64)); + gpu_write(gpu, REG_A5XX_CP_PROTECT(9), ADRENO_PROTECT_RW(0x840, 8)); + gpu_write(gpu, REG_A5XX_CP_PROTECT(10), ADRENO_PROTECT_RW(0x880, 32)); + gpu_write(gpu, REG_A5XX_CP_PROTECT(11), ADRENO_PROTECT_RW(0xAA0, 1)); + + /* RB */ + gpu_write(gpu, REG_A5XX_CP_PROTECT(12), ADRENO_PROTECT_RW(0xCC0, 1)); + gpu_write(gpu, REG_A5XX_CP_PROTECT(13), ADRENO_PROTECT_RW(0xCF0, 2)); + + /* VPC */ + gpu_write(gpu, REG_A5XX_CP_PROTECT(14), ADRENO_PROTECT_RW(0xE68, 8)); + gpu_write(gpu, REG_A5XX_CP_PROTECT(15), ADRENO_PROTECT_RW(0xE70, 4)); + + /* UCHE */ + gpu_write(gpu, REG_A5XX_CP_PROTECT(16), ADRENO_PROTECT_RW(0xE80, 16)); + + if (adreno_is_a530(adreno_gpu)) + gpu_write(gpu, REG_A5XX_CP_PROTECT(17), + ADRENO_PROTECT_RW(0x10000, 0x8000)); + + gpu_write(gpu, REG_A5XX_RBBM_SECVID_TSB_CNTL, 0); + + gpu_write64(gpu, REG_A5XX_RBBM_SECVID_TSB_TRUSTED_BASE_LO, + REG_A5XX_RBBM_SECVID_TSB_TRUSTED_BASE_HI, SECURE_VA_START); + gpu_write(gpu, REG_A5XX_RBBM_SECVID_TSB_TRUSTED_SIZE, SECURE_VA_SIZE); + + /* Put the GPU into 64 bit by default */ + gpu_write(gpu, REG_A5XX_CP_ADDR_MODE_CNTL, 0x1); + gpu_write(gpu, REG_A5XX_VSC_ADDR_MODE_CNTL, 0x1); + gpu_write(gpu, REG_A5XX_GRAS_ADDR_MODE_CNTL, 0x1); + gpu_write(gpu, REG_A5XX_RB_ADDR_MODE_CNTL, 0x1); + gpu_write(gpu, REG_A5XX_PC_ADDR_MODE_CNTL, 0x1); + gpu_write(gpu, REG_A5XX_HLSQ_ADDR_MODE_CNTL, 0x1); + gpu_write(gpu, REG_A5XX_VFD_ADDR_MODE_CNTL, 0x1); + gpu_write(gpu, REG_A5XX_VPC_ADDR_MODE_CNTL, 0x1); + gpu_write(gpu, REG_A5XX_UCHE_ADDR_MODE_CNTL, 0x1); + gpu_write(gpu, REG_A5XX_SP_ADDR_MODE_CNTL, 0x1); + gpu_write(gpu, REG_A5XX_TPL1_ADDR_MODE_CNTL, 0x1); + gpu_write(gpu, REG_A5XX_RBBM_SECVID_TSB_ADDR_MODE_CNTL, 0x1); + + a5xx_gpu->timestamp_counter = adreno_get_counter(gpu, + MSM_COUNTER_GROUP_CP, 0, NULL, NULL); + + /* Get RBBM performance counter countable 6 to read GPU busy cycles */ + a5xx_gpu->gpu_busy_counter = adreno_get_counter(gpu, + MSM_COUNTER_GROUP_RBBM, 6, NULL, NULL); + + /* Load the GPMU firmware before starting the HW init */ + a5xx_gpmu_ucode_init(gpu); + + ret = adreno_hw_init(gpu); + if (ret) + return ret; + + a5xx_preempt_hw_init(gpu); + + ret = a5xx_ucode_init(gpu); + if (ret) + return ret; + + /* Disable the interrupts through the initial bringup stage */ + gpu_write(gpu, REG_A5XX_RBBM_INT_0_MASK, A5XX_INT_MASK); + + /* Clear ME_HALT to start the micro engine */ + gpu_write(gpu, REG_A5XX_CP_PFP_ME_CNTL, 0); + ret = a5xx_me_init(gpu); + if (ret) + return ret; + + /* + * Send a pipeline event stat to get misbehaving counters to start + * ticking correctly + */ + if (adreno_is_a530(adreno_gpu)) { + OUT_PKT7(gpu->rb[0], CP_EVENT_WRITE, 1); + OUT_RING(gpu->rb[0], 0x0F); + + gpu->funcs->flush(gpu, gpu->rb[0]); + if (!a5xx_idle(gpu, gpu->rb[0])) + return -EINVAL; + } + + /* + * If a zap shader was specified in the device tree, assume that we are + * on a secure device that blocks access to the RBBM_SECVID registers + * so we need to use the CP to switch out of secure mode. If a zap + * shader was NOT specified then we assume we are on an unlocked device. + * If we guessed wrong then the access to the register will probably + * cause a XPU violation. + */ + if (test_bit(A5XX_ZAP_SHADER_LOADED, &a5xx_gpu->flags)) { + struct msm_ringbuffer *ring = gpu->rb[0]; + + OUT_PKT7(ring, CP_SET_SECURE_MODE, 1); + OUT_RING(ring, 0x00000000); + + gpu->funcs->flush(gpu, gpu->rb[0]); + if (!a5xx_idle(gpu, gpu->rb[0])) + return -EINVAL; + } else { + /* Print a warning so if we die, we know why */ + dev_warn_once(gpu->dev->dev, + "Zap shader not enabled - using SECVID_TRUST_CNTL instead\n"); + gpu_write(gpu, REG_A5XX_RBBM_SECVID_TRUST_CNTL, 0x0); + } + + /* Next, start the power */ + ret = a5xx_power_init(gpu); + if (ret) + return ret; + + + /* Last step - yield the ringbuffer */ + a5xx_preempt_start(gpu); + + pm_qos_update_request(&gpu->pm_qos_req_dma, 501); + + return 0; +} + +static void a5xx_recover(struct msm_gpu *gpu) +{ + adreno_dump_info(gpu); + + msm_gpu_snapshot(gpu, gpu->snapshot); + + /* Reset the GPU so it can work again */ + gpu_write(gpu, REG_A5XX_RBBM_SW_RESET_CMD, 1); + gpu_read(gpu, REG_A5XX_RBBM_SW_RESET_CMD); + gpu_write(gpu, REG_A5XX_RBBM_SW_RESET_CMD, 0); + + adreno_recover(gpu); +} + +static void a5xx_destroy(struct msm_gpu *gpu) +{ + struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); + struct a5xx_gpu *a5xx_gpu = to_a5xx_gpu(adreno_gpu); + + DBG("%s", gpu->name); + + a5xx_preempt_fini(gpu); + + if (a5xx_gpu->pm4_bo) { + if (a5xx_gpu->pm4_iova) + msm_gem_put_iova(a5xx_gpu->pm4_bo, gpu->aspace); + drm_gem_object_unreference_unlocked(a5xx_gpu->pm4_bo); + } + + if (a5xx_gpu->pfp_bo) { + if (a5xx_gpu->pfp_iova) + msm_gem_put_iova(a5xx_gpu->pfp_bo, gpu->aspace); + drm_gem_object_unreference_unlocked(a5xx_gpu->pfp_bo); + } + + if (a5xx_gpu->gpmu_bo) { + if (a5xx_gpu->gpmu_iova) + msm_gem_put_iova(a5xx_gpu->gpmu_bo, gpu->aspace); + drm_gem_object_unreference_unlocked(a5xx_gpu->gpmu_bo); + } + + adreno_gpu_cleanup(adreno_gpu); + kfree(a5xx_gpu); +} + +static inline bool _a5xx_check_idle(struct msm_gpu *gpu) +{ + if (gpu_read(gpu, REG_A5XX_RBBM_STATUS) & ~A5XX_RBBM_STATUS_HI_BUSY) + return false; + + /* + * Nearly every abnormality ends up pausing the GPU and triggering a + * fault so we can safely just watch for this one interrupt to fire + */ + return !(gpu_read(gpu, REG_A5XX_RBBM_INT_0_STATUS) & + A5XX_RBBM_INT_0_MASK_MISC_HANG_DETECT); +} + +bool a5xx_idle(struct msm_gpu *gpu, struct msm_ringbuffer *ring) +{ + /* wait for CP to drain ringbuffer: */ + if (!adreno_idle(gpu, ring)) + return false; + + if (spin_until(_a5xx_check_idle(gpu))) { + DRM_ERROR( + "%s: timeout waiting for GPU RB %d to idle: status %8.8X rptr/wptr: %4.4X/%4.4X irq %8.8X\n", + gpu->name, ring->id, + gpu_read(gpu, REG_A5XX_RBBM_STATUS), + gpu_read(gpu, REG_A5XX_CP_RB_RPTR), + gpu_read(gpu, REG_A5XX_CP_RB_WPTR), + gpu_read(gpu, REG_A5XX_RBBM_INT_0_STATUS)); + + return false; + } + + return true; +} + +static void a5xx_cp_err_irq(struct msm_gpu *gpu) +{ + u32 status = gpu_read(gpu, REG_A5XX_CP_INTERRUPT_STATUS); + + if (status & A5XX_CP_INT_CP_OPCODE_ERROR) { + u32 val; + + gpu_write(gpu, REG_A5XX_CP_PFP_STAT_ADDR, 0); + + /* + * REG_A5XX_CP_PFP_STAT_DATA is indexed, and we want index 1 so + * read it twice + */ + + gpu_read(gpu, REG_A5XX_CP_PFP_STAT_DATA); + val = gpu_read(gpu, REG_A5XX_CP_PFP_STAT_DATA); + + dev_err_ratelimited(gpu->dev->dev, "CP | opcode error | possible opcode=0x%8.8X\n", + val); + } + + if (status & A5XX_CP_INT_CP_HW_FAULT_ERROR) + dev_err_ratelimited(gpu->dev->dev, "CP | HW fault | status=0x%8.8X\n", + gpu_read(gpu, REG_A5XX_CP_HW_FAULT)); + + if (status & A5XX_CP_INT_CP_DMA_ERROR) + dev_err_ratelimited(gpu->dev->dev, "CP | DMA error\n"); + + if (status & A5XX_CP_INT_CP_REGISTER_PROTECTION_ERROR) { + u32 val = gpu_read(gpu, REG_A5XX_CP_PROTECT_STATUS); + + dev_err_ratelimited(gpu->dev->dev, + "CP | protected mode error | %s | addr=0x%8.8X | status=0x%8.8X\n", + val & (1 << 24) ? "WRITE" : "READ", + (val & 0xFFFFF) >> 2, val); + } + + if (status & A5XX_CP_INT_CP_AHB_ERROR) { + u32 status = gpu_read(gpu, REG_A5XX_CP_AHB_FAULT); + const char *access[16] = { "reserved", "reserved", + "timestamp lo", "timestamp hi", "pfp read", "pfp write", + "", "", "me read", "me write", "", "", "crashdump read", + "crashdump write" }; + + dev_err_ratelimited(gpu->dev->dev, + "CP | AHB error | addr=%X access=%s error=%d | status=0x%8.8X\n", + status & 0xFFFFF, access[(status >> 24) & 0xF], + (status & (1 << 31)), status); + } +} + +static void a5xx_rbbm_err_irq(struct msm_gpu *gpu, u32 status) +{ + if (status & A5XX_RBBM_INT_0_MASK_RBBM_AHB_ERROR) { + u32 val = gpu_read(gpu, REG_A5XX_RBBM_AHB_ERROR_STATUS); + + dev_err_ratelimited(gpu->dev->dev, + "RBBM | AHB bus error | %s | addr=0x%X | ports=0x%X:0x%X\n", + val & (1 << 28) ? "WRITE" : "READ", + (val & 0xFFFFF) >> 2, (val >> 20) & 0x3, + (val >> 24) & 0xF); + + /* Clear the error */ + gpu_write(gpu, REG_A5XX_RBBM_AHB_CMD, (1 << 4)); + + /* Clear the interrupt */ + gpu_write(gpu, REG_A5XX_RBBM_INT_CLEAR_CMD, + A5XX_RBBM_INT_0_MASK_RBBM_AHB_ERROR); + } + + if (status & A5XX_RBBM_INT_0_MASK_RBBM_TRANSFER_TIMEOUT) + dev_err_ratelimited(gpu->dev->dev, "RBBM | AHB transfer timeout\n"); + + if (status & A5XX_RBBM_INT_0_MASK_RBBM_ME_MS_TIMEOUT) + dev_err_ratelimited(gpu->dev->dev, "RBBM | ME master split | status=0x%X\n", + gpu_read(gpu, REG_A5XX_RBBM_AHB_ME_SPLIT_STATUS)); + + if (status & A5XX_RBBM_INT_0_MASK_RBBM_PFP_MS_TIMEOUT) + dev_err_ratelimited(gpu->dev->dev, "RBBM | PFP master split | status=0x%X\n", + gpu_read(gpu, REG_A5XX_RBBM_AHB_PFP_SPLIT_STATUS)); + + if (status & A5XX_RBBM_INT_0_MASK_RBBM_ETS_MS_TIMEOUT) + dev_err_ratelimited(gpu->dev->dev, "RBBM | ETS master split | status=0x%X\n", + gpu_read(gpu, REG_A5XX_RBBM_AHB_ETS_SPLIT_STATUS)); + + if (status & A5XX_RBBM_INT_0_MASK_RBBM_ATB_ASYNC_OVERFLOW) + dev_err_ratelimited(gpu->dev->dev, "RBBM | ATB ASYNC overflow\n"); + + if (status & A5XX_RBBM_INT_0_MASK_RBBM_ATB_BUS_OVERFLOW) + dev_err_ratelimited(gpu->dev->dev, "RBBM | ATB bus overflow\n"); +} + +static void a5xx_uche_err_irq(struct msm_gpu *gpu) +{ + uint64_t addr = (uint64_t) gpu_read(gpu, REG_A5XX_UCHE_TRAP_LOG_HI); + + addr |= gpu_read(gpu, REG_A5XX_UCHE_TRAP_LOG_LO); + + dev_err_ratelimited(gpu->dev->dev, "UCHE | Out of bounds access | addr=0x%llX\n", + addr); +} + +static void a5xx_gpmu_err_irq(struct msm_gpu *gpu) +{ + dev_err_ratelimited(gpu->dev->dev, "GPMU | voltage droop\n"); +} + +static void a5xx_fault_detect_irq(struct msm_gpu *gpu) +{ + struct drm_device *dev = gpu->dev; + struct msm_drm_private *priv = dev->dev_private; + struct msm_ringbuffer *ring = gpu->funcs->active_ring(gpu); + + dev_err(dev->dev, "gpu fault ring %d fence %x status %8.8X rb %4.4x/%4.4x ib1 %16.16llX/%4.4x ib2 %16.16llX/%4.4x\n", + ring ? ring->id : -1, adreno_submitted_fence(gpu, ring), + gpu_read(gpu, REG_A5XX_RBBM_STATUS), + gpu_read(gpu, REG_A5XX_CP_RB_RPTR), + gpu_read(gpu, REG_A5XX_CP_RB_WPTR), + gpu_read64(gpu, REG_A5XX_CP_IB1_BASE, REG_A5XX_CP_IB1_BASE_HI), + gpu_read(gpu, REG_A5XX_CP_IB1_BUFSZ), + gpu_read64(gpu, REG_A5XX_CP_IB2_BASE, REG_A5XX_CP_IB2_BASE_HI), + gpu_read(gpu, REG_A5XX_CP_IB2_BUFSZ)); + + /* Turn off the hangcheck timer to keep it from bothering us */ + del_timer(&gpu->hangcheck_timer); + + queue_work(priv->wq, &gpu->recover_work); +} + +#define RBBM_ERROR_MASK \ + (A5XX_RBBM_INT_0_MASK_RBBM_AHB_ERROR | \ + A5XX_RBBM_INT_0_MASK_RBBM_TRANSFER_TIMEOUT | \ + A5XX_RBBM_INT_0_MASK_RBBM_ME_MS_TIMEOUT | \ + A5XX_RBBM_INT_0_MASK_RBBM_PFP_MS_TIMEOUT | \ + A5XX_RBBM_INT_0_MASK_RBBM_ETS_MS_TIMEOUT | \ + A5XX_RBBM_INT_0_MASK_RBBM_ATB_ASYNC_OVERFLOW) + +static irqreturn_t a5xx_irq(struct msm_gpu *gpu) +{ + u32 status = gpu_read(gpu, REG_A5XX_RBBM_INT_0_STATUS); + + /* + * Clear all the interrupts except for RBBM_AHB_ERROR + * which needs to be cleared after the error condition + * is cleared otherwise it will storm + */ + gpu_write(gpu, REG_A5XX_RBBM_INT_CLEAR_CMD, + status & ~A5XX_RBBM_INT_0_MASK_RBBM_AHB_ERROR); + + if (status & RBBM_ERROR_MASK) + a5xx_rbbm_err_irq(gpu, status); + + if (status & A5XX_RBBM_INT_0_MASK_CP_HW_ERROR) + a5xx_cp_err_irq(gpu); + + if (status & A5XX_RBBM_INT_0_MASK_MISC_HANG_DETECT) + a5xx_fault_detect_irq(gpu); + + if (status & A5XX_RBBM_INT_0_MASK_UCHE_OOB_ACCESS) + a5xx_uche_err_irq(gpu); + + if (status & A5XX_RBBM_INT_0_MASK_GPMU_VOLTAGE_DROOP) + a5xx_gpmu_err_irq(gpu); + + if (status & A5XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS) { + a5xx_preempt_trigger(gpu); + msm_gpu_retire(gpu); + } + + if (status & A5XX_RBBM_INT_0_MASK_CP_SW) + a5xx_preempt_irq(gpu); + + return IRQ_HANDLED; +} + +static const u32 a5xx_register_offsets[REG_ADRENO_REGISTER_MAX] = { + REG_ADRENO_DEFINE(REG_ADRENO_CP_RB_BASE, REG_A5XX_CP_RB_BASE), + REG_ADRENO_DEFINE(REG_ADRENO_CP_RB_BASE_HI, REG_A5XX_CP_RB_BASE_HI), + REG_ADRENO_DEFINE(REG_ADRENO_CP_RB_RPTR_ADDR, REG_A5XX_CP_RB_RPTR_ADDR), + REG_ADRENO_DEFINE(REG_ADRENO_CP_RB_RPTR_ADDR_HI, + REG_A5XX_CP_RB_RPTR_ADDR_HI), + REG_ADRENO_DEFINE(REG_ADRENO_CP_RB_RPTR, REG_A5XX_CP_RB_RPTR), + REG_ADRENO_DEFINE(REG_ADRENO_CP_RB_WPTR, REG_A5XX_CP_RB_WPTR), + REG_ADRENO_DEFINE(REG_ADRENO_CP_RB_CNTL, REG_A5XX_CP_RB_CNTL), +}; + +static const u32 a5xx_registers[] = { + 0x0000, 0x0002, 0x0004, 0x0020, 0x0022, 0x0026, 0x0029, 0x002b, + 0x002e, 0x0035, 0x0038, 0x0042, 0x0044, 0x0044, 0x0047, 0x0095, + 0x0097, 0x00bb, 0x03a0, 0x0464, 0x0469, 0x046f, 0x04d2, 0x04d3, + 0x04e0, 0x0533, 0x0540, 0x0555, 0x0800, 0x081a, 0x081f, 0x0841, + 0x0860, 0x0860, 0x0880, 0x08a0, 0x0b00, 0x0b12, 0x0b14, 0x0b28, + 0x0b78, 0x0b7f, 0x0bb0, 0x0bbd, 0x0bc0, 0x0bc6, 0x0bd0, 0x0c53, + 0x0c60, 0x0c61, 0x0c80, 0x0c82, 0x0c84, 0x0c85, 0x0c90, 0x0c9b, + 0x0ca0, 0x0ca0, 0x0cb0, 0x0cb2, 0x0cc1, 0x0cc1, 0x0cc4, 0x0cc7, + 0x0ccc, 0x0ccc, 0x0cd0, 0x0cdb, 0x0ce0, 0x0ce5, 0x0ce8, 0x0ce8, + 0x0cec, 0x0cf1, 0x0cfb, 0x0d0e, 0x0d10, 0x0d17, 0x0d20, 0x0d23, + 0x0d30, 0x0d30, 0x0e40, 0x0e43, 0x0e4a, 0x0e4a, 0x0e50, 0x0e57, + 0x0e60, 0x0e7c, 0x0e80, 0x0e8e, 0x0e90, 0x0e96, 0x0ea0, 0x0eab, + 0x0eb0, 0x0eb2, 0x2100, 0x211e, 0x2140, 0x2145, 0x2180, 0x2185, + 0x2500, 0x251e, 0x2540, 0x2545, 0x2580, 0x2585, 0x3000, 0x3014, + 0x3018, 0x302c, 0x3030, 0x3030, 0x3034, 0x3036, 0x303c, 0x303d, + 0x3040, 0x3040, 0x3042, 0x3042, 0x3049, 0x3049, 0x3058, 0x3058, + 0x305a, 0x3061, 0x3064, 0x3068, 0x306c, 0x306d, 0x3080, 0x3088, + 0x308b, 0x308c, 0x3090, 0x3094, 0x3098, 0x3098, 0x309c, 0x309c, + 0x3124, 0x3124, 0x340c, 0x340c, 0x3410, 0x3410, 0x3800, 0x3801, + 0xa800, 0xa800, 0xa820, 0xa828, 0xa840, 0xa87d, 0xa880, 0xa88d, + 0xa890, 0xa8a3, 0xa8a8, 0xa8aa, 0xa8c0, 0xa8c3, 0xa8c6, 0xa8ca, + 0xa8cc, 0xa8cf, 0xa8d1, 0xa8d8, 0xa8dc, 0xa8dc, 0xa8e0, 0xa8f5, + 0xac00, 0xac06, 0xac40, 0xac47, 0xac60, 0xac62, 0xac80, 0xac82, + 0xb800, 0xb808, 0xb80c, 0xb812, 0xb814, 0xb817, 0xb900, 0xb904, + 0xb906, 0xb90a, 0xb90c, 0xb90f, 0xb920, 0xb924, 0xb926, 0xb92a, + 0xb92c, 0xb92f, 0xb940, 0xb944, 0xb946, 0xb94a, 0xb94c, 0xb94f, + 0xb960, 0xb964, 0xb966, 0xb96a, 0xb96c, 0xb96f, 0xb980, 0xb984, + 0xb986, 0xb98a, 0xb98c, 0xb98f, 0xb9a0, 0xb9b0, 0xb9b8, 0xb9ba, + 0xd200, 0xd23f, 0xe000, 0xe006, 0xe010, 0xe09a, 0xe0a0, 0xe0a4, + 0xe0aa, 0xe0eb, 0xe100, 0xe105, 0xe140, 0xe147, 0xe150, 0xe187, + 0xe1a0, 0xe1a9, 0xe1b0, 0xe1b6, 0xe1c0, 0xe1c7, 0xe1d0, 0xe1d1, + 0xe200, 0xe201, 0xe210, 0xe21c, 0xe240, 0xe268, 0xe280, 0xe280, + 0xe282, 0xe2a3, 0xe2a5, 0xe2c2, 0xe380, 0xe38f, 0xe3b0, 0xe3b0, + 0xe400, 0xe405, 0xe408, 0xe4e9, 0xe4f0, 0xe4f0, 0xe800, 0xe806, + 0xe810, 0xe89a, 0xe8a0, 0xe8a4, 0xe8aa, 0xe8eb, 0xe900, 0xe905, + 0xe940, 0xe947, 0xe950, 0xe987, 0xe9a0, 0xe9a9, 0xe9b0, 0xe9b6, + 0xe9c0, 0xe9c7, 0xe9d0, 0xe9d1, 0xea00, 0xea01, 0xea10, 0xea1c, + 0xea40, 0xea68, 0xea80, 0xea80, 0xea82, 0xeaa3, 0xeaa5, 0xeac2, + 0xeb80, 0xeb8f, 0xebb0, 0xebb0, 0xec00, 0xec05, 0xec08, 0xece9, + 0xecf0, 0xecf0, 0xf800, 0xf807, + ~0 +}; + +static int a5xx_pm_resume(struct msm_gpu *gpu) +{ + int ret; + + /* Turn on the core power */ + ret = msm_gpu_pm_resume(gpu); + if (ret) + return ret; + + /* Turn the RBCCU domain first to limit the chances of voltage droop */ + gpu_write(gpu, REG_A5XX_GPMU_RBCCU_POWER_CNTL, 0x778000); + + /* Wait 3 usecs before polling */ + udelay(3); + + ret = spin_usecs(gpu, 20, REG_A5XX_GPMU_RBCCU_PWR_CLK_STATUS, + (1 << 20), (1 << 20)); + if (ret) { + DRM_ERROR("%s: timeout waiting for RBCCU GDSC enable: %X\n", + gpu->name, + gpu_read(gpu, REG_A5XX_GPMU_RBCCU_PWR_CLK_STATUS)); + return ret; + } + + /* Turn on the SP domain */ + gpu_write(gpu, REG_A5XX_GPMU_SP_POWER_CNTL, 0x778000); + ret = spin_usecs(gpu, 20, REG_A5XX_GPMU_SP_PWR_CLK_STATUS, + (1 << 20), (1 << 20)); + if (ret) + DRM_ERROR("%s: timeout waiting for SP GDSC enable\n", + gpu->name); + + a5xx_counters_restore(gpu); + + return ret; +} + +static int a5xx_pm_suspend(struct msm_gpu *gpu) +{ + struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); + + /* Clear the VBIF pipe before shutting down */ + gpu_write(gpu, REG_A5XX_VBIF_XIN_HALT_CTRL0, 0xF); + spin_until((gpu_read(gpu, REG_A5XX_VBIF_XIN_HALT_CTRL1) & 0xF) + == 0xF); + + gpu_write(gpu, REG_A5XX_VBIF_XIN_HALT_CTRL0, 0); + + /* Save the counters before going down */ + a5xx_counters_save(gpu); + + /* + * Reset the VBIF before power collapse to avoid issue with FIFO + * entries + */ + if (adreno_is_a530(adreno_gpu)) { + /* These only need to be done for A530 */ + gpu_write(gpu, REG_A5XX_RBBM_BLOCK_SW_RESET_CMD, + 0x003C0000); + gpu_write(gpu, REG_A5XX_RBBM_BLOCK_SW_RESET_CMD, + 0x00000000); + } + + return msm_gpu_pm_suspend(gpu); +} + +static int a5xx_get_timestamp(struct msm_gpu *gpu, uint64_t *value) +{ + struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); + struct a5xx_gpu *a5xx_gpu = to_a5xx_gpu(adreno_gpu); + + *value = adreno_read_counter(gpu, MSM_COUNTER_GROUP_CP, + a5xx_gpu->timestamp_counter); + + return 0; +} + +#ifdef CONFIG_DEBUG_FS +static void a5xx_show(struct msm_gpu *gpu, struct seq_file *m) +{ + seq_printf(m, "status: %08x\n", + gpu_read(gpu, REG_A5XX_RBBM_STATUS)); + adreno_show(gpu, m); + +} +#endif + +static struct msm_ringbuffer *a5xx_active_ring(struct msm_gpu *gpu) +{ + struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); + struct a5xx_gpu *a5xx_gpu = to_a5xx_gpu(adreno_gpu); + + return a5xx_gpu->cur_ring; +} + +static u64 a5xx_gpu_busy(struct msm_gpu *gpu) +{ + struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); + struct a5xx_gpu *a5xx_gpu = to_a5xx_gpu(adreno_gpu); + + return adreno_read_counter(gpu, MSM_COUNTER_GROUP_RBBM, + a5xx_gpu->gpu_busy_counter); +} + +static const struct adreno_gpu_funcs funcs = { + .base = { + .get_param = adreno_get_param, + .hw_init = a5xx_hw_init, + .pm_suspend = a5xx_pm_suspend, + .pm_resume = a5xx_pm_resume, + .recover = a5xx_recover, + .submitted_fence = adreno_submitted_fence, + .submit = a5xx_submit, + .flush = a5xx_flush, + .active_ring = a5xx_active_ring, + .irq = a5xx_irq, + .destroy = a5xx_destroy, +#ifdef CONFIG_DEBUG_FS + .show = a5xx_show, +#endif + .snapshot = a5xx_snapshot, + .get_counter = adreno_get_counter, + .read_counter = adreno_read_counter, + .put_counter = adreno_put_counter, + .gpu_busy = a5xx_gpu_busy, + }, + .get_timestamp = a5xx_get_timestamp, +}; + +/* Read the limits management leakage from the efuses */ +static void a530_efuse_leakage(struct platform_device *pdev, + struct adreno_gpu *adreno_gpu, void *base, + size_t size) +{ + struct a5xx_gpu *a5xx_gpu = to_a5xx_gpu(adreno_gpu); + unsigned int row0, row2; + unsigned int leakage_pwr_on, coeff; + + if (size < 0x148) + return; + + /* Leakage */ + row0 = readl_relaxed(base + 0x134); + row2 = readl_relaxed(base + 0x144); + + /* Read barrier to get the previous two reads */ + rmb(); + + /* Get the leakage coefficient from device tree */ + if (of_property_read_u32(pdev->dev.of_node, + "qcom,base-leakage-coefficent", &coeff)) + return; + + leakage_pwr_on = ((row2 >> 2) & 0xFF) * (1 << (row0 >> 1) & 0x03); + a5xx_gpu->lm_leakage = (leakage_pwr_on << 16) | + ((leakage_pwr_on * coeff) / 100); +} + +/* Read the speed bin from the efuses */ +static void a530_efuse_bin(struct platform_device *pdev, + struct adreno_gpu *adreno_gpu, void *base, + size_t size) +{ + uint32_t speed_bin[3]; + uint32_t val; + + if (of_property_read_u32_array(pdev->dev.of_node, + "qcom,gpu-speed-bin", speed_bin, 3)) + return; + + if (size < speed_bin[0] + 4) + return; + + val = readl_relaxed(base + speed_bin[0]); + + adreno_gpu->speed_bin = (val & speed_bin[1]) >> speed_bin[2]; +} + +/* Read target specific configuration from the efuses */ +static void a5xx_efuses_read(struct platform_device *pdev, + struct adreno_gpu *adreno_gpu) +{ + struct adreno_platform_config *config = pdev->dev.platform_data; + const struct adreno_info *info = adreno_info(config->rev); + struct resource *res; + void *base; + + /* + * The adreno_gpu->revn mechanism isn't set up yet so we need to check + * it directly here + */ + if (info->revn != 530) + return; + + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, + "qfprom_memory"); + if (!res) + return; + + base = ioremap(res->start, resource_size(res)); + if (!base) + return; + + a530_efuse_bin(pdev, adreno_gpu, base, resource_size(res)); + a530_efuse_leakage(pdev, adreno_gpu, base, resource_size(res)); + + iounmap(base); +} + +struct msm_gpu *a5xx_gpu_init(struct drm_device *dev) +{ + struct msm_drm_private *priv = dev->dev_private; + struct platform_device *pdev = priv->gpu_pdev; + struct a5xx_gpu *a5xx_gpu = NULL; + struct adreno_gpu *adreno_gpu; + struct msm_gpu *gpu; + struct msm_gpu_config a5xx_config = { 0 }; + int ret; + + if (!pdev) { + dev_err(dev->dev, "No A5XX device is defined\n"); + return ERR_PTR(-ENXIO); + } + + a5xx_gpu = kzalloc(sizeof(*a5xx_gpu), GFP_KERNEL); + if (!a5xx_gpu) + return ERR_PTR(-ENOMEM); + + adreno_gpu = &a5xx_gpu->base; + gpu = &adreno_gpu->base; + + adreno_gpu->registers = a5xx_registers; + adreno_gpu->reg_offsets = a5xx_register_offsets; + + a5xx_gpu->lm_leakage = 0x4E001A; + + /* Check the efuses for some configuration */ + a5xx_efuses_read(pdev, adreno_gpu); + + a5xx_config.ioname = MSM_GPU_DEFAULT_IONAME; + a5xx_config.irqname = MSM_GPU_DEFAULT_IRQNAME; + + /* Set the number of rings to 4 - yay preemption */ + a5xx_config.nr_rings = 4; + + /* + * Set the user domain range to fall into the TTBR1 region for global + * objects + */ + a5xx_config.va_start = 0xfffffff000000000ULL; + a5xx_config.va_end = 0xffffffffffffffffULL; + + a5xx_config.secure_va_start = SECURE_VA_START; + a5xx_config.secure_va_end = SECURE_VA_START + SECURE_VA_SIZE - 1; + + ret = adreno_gpu_init(dev, pdev, adreno_gpu, &funcs, &a5xx_config); + if (ret) { + a5xx_destroy(&(a5xx_gpu->base.base)); + return ERR_PTR(ret); + } + + /* Set up the preemption specific bits and pieces for each ringbuffer */ + a5xx_preempt_init(gpu); + + a5xx_counters_init(adreno_gpu); + + return gpu; +} --- /dev/null 2019-10-24 16:47:25.704025805 +0200 +++ linux-4.4.115-fbx/drivers/gpu/drm/msm/adreno/a5xx_gpu.h 2019-01-22 16:16:23.483246225 +0100 @@ -0,0 +1,200 @@ +/* Copyright (c) 2016-2018 The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ +#ifndef __A5XX_GPU_H__ +#define __A5XX_GPU_H__ + +#include "adreno_gpu.h" + +/* Bringing over the hack from the previous targets */ +#undef ROP_COPY +#undef ROP_XOR + +#include "a5xx.xml.h" + +enum { + A5XX_ZAP_SHADER_LOADED = 1, + A5XX_HWCG_ENABLED = 2, +}; + +struct a5xx_gpu { + unsigned long flags; + + struct adreno_gpu base; + + struct drm_gem_object *pm4_bo; + uint64_t pm4_iova; + + struct drm_gem_object *pfp_bo; + uint64_t pfp_iova; + + struct drm_gem_object *gpmu_bo; + uint64_t gpmu_iova; + uint32_t gpmu_dwords; + + uint32_t lm_leakage; + + struct msm_ringbuffer *cur_ring; + struct msm_ringbuffer *next_ring; + + struct drm_gem_object *preempt_bo[MSM_GPU_MAX_RINGS]; + struct a5xx_preempt_record *preempt[MSM_GPU_MAX_RINGS]; + uint64_t preempt_iova[MSM_GPU_MAX_RINGS]; + + atomic_t preempt_state; + struct timer_list preempt_timer; + + struct a5xx_smmu_info *smmu_info; + struct drm_gem_object *smmu_info_bo; + uint64_t smmu_info_iova; + + int timestamp_counter; + int gpu_busy_counter; +}; + +#define to_a5xx_gpu(x) container_of(x, struct a5xx_gpu, base) + +/* + * In order to do lockless preemption we use a simple state machine to progress + * through the process. + * + * PREEMPT_NONE - no preemption in progress. Next state START. + * PREEMPT_START - The trigger is evaulating if preemption is possible. Next + * states: TRIGGERED, NONE + * PREEMPT_ABORT - An intermediate state before moving back to NONE. Next + * state: NONE. + * PREEMPT_TRIGGERED: A preemption has been executed on the hardware. Next + * states: FAULTED, PENDING + * PREEMPT_FAULTED: A preemption timed out (never completed). This will trigger + * recovery. Next state: N/A + * PREEMPT_PENDING: Preemption complete interrupt fired - the callback is + * checking the success of the operation. Next state: FAULTED, NONE. + */ + +enum preempt_state { + PREEMPT_NONE = 0, + PREEMPT_START, + PREEMPT_ABORT, + PREEMPT_TRIGGERED, + PREEMPT_FAULTED, + PREEMPT_PENDING, +}; + +/* + * struct a5xx_preempt_record is a shared buffer between the microcode and the + * CPU to store the state for preemption. The record itself is much larger + * (64k) but most of that is used by the CP for storage. + * + * There is a preemption record assigned per ringbuffer. When the CPU triggers a + * preemption, it fills out the record with the useful information (wptr, ring + * base, etc) and the microcode uses that information to set up the CP following + * the preemption. When a ring is switched out, the CP will save the ringbuffer + * state back to the record. In this way, once the records are properly set up + * the CPU can quickly switch back and forth between ringbuffers by only + * updating a few registers (often only the wptr). + * + * These are the CPU aware registers in the record: + * @magic: Must always be 0x27C4BAFC + * @info: Type of the record - written 0 by the CPU, updated by the CP + * @data: Data field from SET_RENDER_MODE or a checkpoint. Written and used by + * the CP + * @cntl: Value of RB_CNTL written by CPU, save/restored by CP + * @rptr: Value of RB_RPTR written by CPU, save/restored by CP + * @wptr: Value of RB_WPTR written by CPU, save/restored by CP + * @rptr_addr: Value of RB_RPTR_ADDR written by CPU, save/restored by CP + * @rbase: Value of RB_BASE written by CPU, save/restored by CP + * @counter: GPU address of the storage area for the performance counters + */ +struct a5xx_preempt_record { + uint32_t magic; + uint32_t info; + uint32_t data; + uint32_t cntl; + uint32_t rptr; + uint32_t wptr; + uint64_t rptr_addr; + uint64_t rbase; + uint64_t counter; +}; + +/* Magic identifier for the preemption record */ +#define A5XX_PREEMPT_RECORD_MAGIC 0x27C4BAFCUL + +/* + * Even though the structure above is only a few bytes, we need a full 64k to + * store the entire preemption record from the CP + */ +#define A5XX_PREEMPT_RECORD_SIZE (64 * 1024) + +/* + * The preemption counter block is a storage area for the value of the + * preemption counters that are saved immediately before context switch. We + * append it on to the end of the allocadtion for the preemption record. + */ +#define A5XX_PREEMPT_COUNTER_SIZE (16 * 4) + +/* + * This is a global structure that the preemption code uses to switch in the + * pagetable for the preempted process - the code switches in whatever we + * after preempting in a new ring. + */ +struct a5xx_smmu_info { + uint32_t magic; + uint32_t _pad4; + uint64_t ttbr0; + uint32_t asid; + uint32_t contextidr; +}; + +#define A5XX_SMMU_INFO_MAGIC 0x3618CDA3UL + +int a5xx_power_init(struct msm_gpu *gpu); +void a5xx_gpmu_ucode_init(struct msm_gpu *gpu); + +static inline int spin_usecs(struct msm_gpu *gpu, uint32_t usecs, + uint32_t reg, uint32_t mask, uint32_t value) +{ + while (usecs--) { + udelay(1); + if ((gpu_read(gpu, reg) & mask) == value) + return 0; + cpu_relax(); + } + + return -ETIMEDOUT; +} + +void a5xx_set_hwcg(struct msm_gpu *gpu, bool state); +bool a5xx_idle(struct msm_gpu *gpu, struct msm_ringbuffer *ring); + +void a5xx_preempt_init(struct msm_gpu *gpu); +void a5xx_preempt_hw_init(struct msm_gpu *gpu); +void a5xx_preempt_trigger(struct msm_gpu *gpu); +void a5xx_preempt_irq(struct msm_gpu *gpu); +void a5xx_preempt_fini(struct msm_gpu *gpu); + +int a5xx_snapshot(struct msm_gpu *gpu, struct msm_snapshot *snapshot); + +/* Return true if we are in a preempt state */ +static inline bool a5xx_in_preempt(struct a5xx_gpu *a5xx_gpu) +{ + int preempt_state = atomic_read(&a5xx_gpu->preempt_state); + + return !(preempt_state == PREEMPT_NONE || + preempt_state == PREEMPT_ABORT); +} + +int a5xx_counters_init(struct adreno_gpu *adreno_gpu); +void a5xx_counters_save(struct msm_gpu *gpu); +void a5xx_counters_restore(struct msm_gpu *gpu); + +#endif /* __A5XX_GPU_H__ */ --- /dev/null 2019-10-24 16:47:25.704025805 +0200 +++ linux-4.4.115-fbx/drivers/gpu/drm/msm/adreno/a5xx_power.c 2019-01-22 16:16:23.483246225 +0100 @@ -0,0 +1,491 @@ +/* Copyright (c) 2016-2018 The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include +#include "a5xx_gpu.h" + +/* + * The GPMU data block is a block of shared registers that can be used to + * communicate back and forth. These "registers" are by convention with the GPMU + * firwmare and not bound to any specific hardware design + */ + +#define AGC_INIT_BASE REG_A5XX_GPMU_DATA_RAM_BASE +#define AGC_INIT_MSG_MAGIC (AGC_INIT_BASE + 5) +#define AGC_MSG_BASE (AGC_INIT_BASE + 7) + +#define AGC_MSG_STATE (AGC_MSG_BASE + 0) +#define AGC_MSG_COMMAND (AGC_MSG_BASE + 1) +#define AGC_MSG_PAYLOAD_SIZE (AGC_MSG_BASE + 3) +#define AGC_MSG_PAYLOAD(_o) ((AGC_MSG_BASE + 5) + (_o)) + +#define AGC_POWER_CONFIG_PRODUCTION_ID 1 +#define AGC_INIT_MSG_VALUE 0xBABEFACE + +/* AGC_LM_CONFIG (A540+) */ +#define AGC_LM_CONFIG (136/4) +#define AGC_LM_CONFIG_GPU_VERSION_SHIFT 17 +#define AGC_LM_CONFIG_ENABLE_GPMU_ADAPTIVE 1 +#define AGC_LM_CONFIG_THROTTLE_DISABLE (2 << 8) +#define AGC_LM_CONFIG_ISENSE_ENABLE (1 << 4) +#define AGC_LM_CONFIG_ENABLE_ERROR (3 << 4) +#define AGC_LM_CONFIG_LLM_ENABLED (1 << 16) +#define AGC_LM_CONFIG_BCL_DISABLED (1 << 24) + +#define AGC_LEVEL_CONFIG (140/4) + +static struct { + uint32_t reg; + uint32_t value; +} a5xx_sequence_regs[] = { + { 0xB9A1, 0x00010303 }, + { 0xB9A2, 0x13000000 }, + { 0xB9A3, 0x00460020 }, + { 0xB9A4, 0x10000000 }, + { 0xB9A5, 0x040A1707 }, + { 0xB9A6, 0x00010000 }, + { 0xB9A7, 0x0E000904 }, + { 0xB9A8, 0x10000000 }, + { 0xB9A9, 0x01165000 }, + { 0xB9AA, 0x000E0002 }, + { 0xB9AB, 0x03884141 }, + { 0xB9AC, 0x10000840 }, + { 0xB9AD, 0x572A5000 }, + { 0xB9AE, 0x00000003 }, + { 0xB9AF, 0x00000000 }, + { 0xB9B0, 0x10000000 }, + { 0xB828, 0x6C204010 }, + { 0xB829, 0x6C204011 }, + { 0xB82A, 0x6C204012 }, + { 0xB82B, 0x6C204013 }, + { 0xB82C, 0x6C204014 }, + { 0xB90F, 0x00000004 }, + { 0xB910, 0x00000002 }, + { 0xB911, 0x00000002 }, + { 0xB912, 0x00000002 }, + { 0xB913, 0x00000002 }, + { 0xB92F, 0x00000004 }, + { 0xB930, 0x00000005 }, + { 0xB931, 0x00000005 }, + { 0xB932, 0x00000005 }, + { 0xB933, 0x00000005 }, + { 0xB96F, 0x00000001 }, + { 0xB970, 0x00000003 }, + { 0xB94F, 0x00000004 }, + { 0xB950, 0x0000000B }, + { 0xB951, 0x0000000B }, + { 0xB952, 0x0000000B }, + { 0xB953, 0x0000000B }, + { 0xB907, 0x00000019 }, + { 0xB927, 0x00000019 }, + { 0xB947, 0x00000019 }, + { 0xB967, 0x00000019 }, + { 0xB987, 0x00000019 }, + { 0xB906, 0x00220001 }, + { 0xB926, 0x00220001 }, + { 0xB946, 0x00220001 }, + { 0xB966, 0x00220001 }, + { 0xB986, 0x00300000 }, + { 0xAC40, 0x0340FF41 }, + { 0xAC41, 0x03BEFED0 }, + { 0xAC42, 0x00331FED }, + { 0xAC43, 0x021FFDD3 }, + { 0xAC44, 0x5555AAAA }, + { 0xAC45, 0x5555AAAA }, + { 0xB9BA, 0x00000008 }, +}; + +/* + * Get the actual voltage value for the operating point at the specified + * frequency + */ +static inline uint32_t _get_mvolts(struct msm_gpu *gpu, uint32_t freq) +{ + struct drm_device *dev = gpu->dev; + struct msm_drm_private *priv = dev->dev_private; + struct platform_device *pdev = priv->gpu_pdev; + struct dev_pm_opp *opp; + + opp = dev_pm_opp_find_freq_exact(&pdev->dev, freq, true); + + return (!IS_ERR(opp)) ? dev_pm_opp_get_voltage(opp) / 1000 : 0; +} + +#define PAYLOAD_SIZE(_size) ((_size) * sizeof(u32)) +#define LM_DCVS_LIMIT 1 +#define LEVEL_CONFIG ~(0x303) + +/* Setup thermal limit management for A540 */ +static void a540_lm_setup(struct msm_gpu *gpu) +{ + struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); + u32 max_power = 0; + u32 rate = gpu->gpufreq[0]; + u32 config; + + /* The battery current limiter isn't enabled for A540 */ + config = AGC_LM_CONFIG_BCL_DISABLED; + config |= adreno_gpu->rev.patchid << AGC_LM_CONFIG_GPU_VERSION_SHIFT; + + /* For now disable GPMU side throttling */ + config |= AGC_LM_CONFIG_THROTTLE_DISABLE; + + /* Get the max-power from the device tree */ + of_property_read_u32(GPU_OF_NODE(gpu), "qcom,lm-max-power", &max_power); + + gpu_write(gpu, AGC_MSG_STATE, 0x80000001); + gpu_write(gpu, AGC_MSG_COMMAND, AGC_POWER_CONFIG_PRODUCTION_ID); + + gpu_write(gpu, AGC_MSG_PAYLOAD(0), max_power); + gpu_write(gpu, AGC_MSG_PAYLOAD(1), 1); + + gpu_write(gpu, AGC_MSG_PAYLOAD(2), _get_mvolts(gpu, rate)); + gpu_write(gpu, AGC_MSG_PAYLOAD(3), rate / 1000000); + + gpu_write(gpu, AGC_MSG_PAYLOAD(AGC_LM_CONFIG), config); + gpu_write(gpu, AGC_MSG_PAYLOAD(AGC_LEVEL_CONFIG), LEVEL_CONFIG); + gpu_write(gpu, AGC_MSG_PAYLOAD_SIZE, + PAYLOAD_SIZE(AGC_LEVEL_CONFIG + 1)); + + gpu_write(gpu, AGC_INIT_MSG_MAGIC, AGC_INIT_MSG_VALUE); +} + +/* Setup thermal limit management for A530 */ +static void a530_lm_setup(struct msm_gpu *gpu) +{ + struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); + struct a5xx_gpu *a5xx_gpu = to_a5xx_gpu(adreno_gpu); + uint32_t rate = gpu->gpufreq[0]; + uint32_t tsens = 0; + uint32_t max_power = 0; + unsigned int i; + + /* Write the block of sequence registers */ + for (i = 0; i < ARRAY_SIZE(a5xx_sequence_regs); i++) + gpu_write(gpu, a5xx_sequence_regs[i].reg, + a5xx_sequence_regs[i].value); + + of_property_read_u32(GPU_OF_NODE(gpu), "qcom,gpmu-tsens", &tsens); + + gpu_write(gpu, REG_A5XX_GPMU_TEMP_SENSOR_ID, tsens); + gpu_write(gpu, REG_A5XX_GPMU_DELTA_TEMP_THRESHOLD, 0x01); + gpu_write(gpu, REG_A5XX_GPMU_TEMP_SENSOR_CONFIG, 0x01); + + gpu_write(gpu, REG_A5XX_GPMU_BASE_LEAKAGE, a5xx_gpu->lm_leakage); + + gpu_write(gpu, REG_A5XX_GPMU_BEC_ENABLE, 0x10001FFF); + gpu_write(gpu, REG_A5XX_GDPM_CONFIG1, 0x00201FF1); + + /* Write the voltage table */ + + /* Get the max-power from the device tree */ + of_property_read_u32(GPU_OF_NODE(gpu), "qcom,lm-max-power", &max_power); + + gpu_write(gpu, REG_A5XX_GPMU_BEC_ENABLE, 0x10001FFF); + gpu_write(gpu, REG_A5XX_GDPM_CONFIG1, 0x201FF1); + + gpu_write(gpu, AGC_MSG_STATE, 1); + gpu_write(gpu, AGC_MSG_COMMAND, AGC_POWER_CONFIG_PRODUCTION_ID); + + gpu_write(gpu, AGC_MSG_PAYLOAD(0), max_power); + gpu_write(gpu, AGC_MSG_PAYLOAD(1), 1); + + gpu_write(gpu, AGC_MSG_PAYLOAD(2), _get_mvolts(gpu, rate)); + gpu_write(gpu, AGC_MSG_PAYLOAD(3), rate / 1000000); + + gpu_write(gpu, AGC_MSG_PAYLOAD_SIZE, 4 * sizeof(uint32_t)); + gpu_write(gpu, AGC_INIT_MSG_MAGIC, AGC_INIT_MSG_VALUE); +} + +/* Enable SP/TP cpower collapse */ +static void a5xx_pc_init(struct msm_gpu *gpu) +{ + gpu_write(gpu, REG_A5XX_GPMU_PWR_COL_INTER_FRAME_CTRL, 0x7F); + gpu_write(gpu, REG_A5XX_GPMU_PWR_COL_BINNING_CTRL, 0); + gpu_write(gpu, REG_A5XX_GPMU_PWR_COL_INTER_FRAME_HYST, 0xA0080); + gpu_write(gpu, REG_A5XX_GPMU_PWR_COL_STAGGER_DELAY, 0x600040); +} + +/* Enable the GPMU microcontroller */ +static int a5xx_gpmu_init(struct msm_gpu *gpu) +{ + struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); + struct a5xx_gpu *a5xx_gpu = to_a5xx_gpu(adreno_gpu); + struct msm_ringbuffer *ring = gpu->rb[0]; + + if (!a5xx_gpu->gpmu_dwords) + return 0; + + /* Turn off protected mode for this operation */ + OUT_PKT7(ring, CP_SET_PROTECTED_MODE, 1); + OUT_RING(ring, 0); + + /* Kick off the IB to load the GPMU microcode */ + OUT_PKT7(ring, CP_INDIRECT_BUFFER_PFE, 3); + OUT_RING(ring, lower_32_bits(a5xx_gpu->gpmu_iova)); + OUT_RING(ring, upper_32_bits(a5xx_gpu->gpmu_iova)); + OUT_RING(ring, a5xx_gpu->gpmu_dwords); + + /* Turn back on protected mode */ + OUT_PKT7(ring, CP_SET_PROTECTED_MODE, 1); + OUT_RING(ring, 1); + + gpu->funcs->flush(gpu, ring); + + /* This is "fatal" because the CP is left in a bad state */ + if (!a5xx_idle(gpu, ring)) { + DRM_ERROR("%s: Unable to load GPMU firmwaren", + gpu->name); + return -EINVAL; + } + + /* Clock gating setup for A530 targets */ + if (adreno_is_a530(adreno_gpu)) + gpu_write(gpu, REG_A5XX_GPMU_WFI_CONFIG, 0x4014); + + /* Kick off the GPMU */ + gpu_write(gpu, REG_A5XX_GPMU_CM3_SYSRESET, 0x0); + + /* + * Wait for the GPMU to respond. It isn't fatal if it doesn't, we just + * won't have advanced power collapse. + */ + if (spin_usecs(gpu, 25, REG_A5XX_GPMU_GENERAL_0, 0xFFFFFFFF, + 0xBABEFACE)) { + DRM_ERROR("%s: GPMU firmware initialization timed out\n", + gpu->name); + return 0; + } + + if (!adreno_is_a530(adreno_gpu)) { + u32 val = gpu_read(gpu, REG_A5XX_GPMU_GENERAL_1); + + if (val) + DRM_ERROR("%s: GPMU firmare initialization failed: %d\n", + gpu->name, val); + } + + /* FIXME: Clear GPMU interrupts? */ + return 0; +} + +/* Enable limits management */ +static void a5xx_lm_enable(struct msm_gpu *gpu) +{ + struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); + + /* This init sequence only applies to A530 */ + if (!adreno_is_a530(adreno_gpu)) + return; + + gpu_write(gpu, REG_A5XX_GDPM_INT_MASK, 0x0); + gpu_write(gpu, REG_A5XX_GDPM_INT_EN, 0x0A); + gpu_write(gpu, REG_A5XX_GPMU_GPMU_VOLTAGE_INTR_EN_MASK, 0x01); + gpu_write(gpu, REG_A5XX_GPMU_TEMP_THRESHOLD_INTR_EN_MASK, 0x50000); + gpu_write(gpu, REG_A5XX_GPMU_THROTTLE_UNMASK_FORCE_CTRL, 0x30000); + + gpu_write(gpu, REG_A5XX_GPMU_CLOCK_THROTTLE_CTRL, 0x011); +} + +int a5xx_power_init(struct msm_gpu *gpu) +{ + struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); + int ret; + u32 lm_limit = 6000; + + /* + * Set up the limit management + * first, do some generic setup: + */ + gpu_write(gpu, REG_A5XX_GPMU_GPMU_VOLTAGE, 0x80000000 | 0); + + of_property_read_u32(GPU_OF_NODE(gpu), "qcom,lm-limit", &lm_limit); + gpu_write(gpu, REG_A5XX_GPMU_GPMU_PWR_THRESHOLD, 0x80000000 | lm_limit); + + /* Now do the target specific setup */ + if (adreno_is_a530(adreno_gpu)) + a530_lm_setup(gpu); + else + a540_lm_setup(gpu); + + /* Set up SP/TP power collpase */ + a5xx_pc_init(gpu); + + /* Start the GPMU */ + ret = a5xx_gpmu_init(gpu); + if (ret) + return ret; + + /* Start the limits management */ + a5xx_lm_enable(gpu); + + return 0; +} + +static int _read_header(unsigned int *data, uint32_t fwsize, + unsigned int *major, unsigned int *minor) +{ + uint32_t size; + unsigned int i; + + /* First dword of the header is the header size */ + if (fwsize < 4) + return -EINVAL; + + size = data[0]; + + /* Make sure the header isn't too big and is a multiple of two */ + if ((size % 2) || (size > 10) || size > (fwsize >> 2)) + return -EINVAL; + + /* Read the values in pairs */ + for (i = 1; i < size; i += 2) { + switch (data[i]) { + case 1: + *major = data[i + 1]; + break; + case 2: + *minor = data[i + 1]; + break; + default: + /* Invalid values are non fatal */ + break; + } + } + + return 0; +} + +/* + * Make sure cur_major and cur_minor are greater than or equal to the minimum + * allowable major/minor + */ +static inline bool _check_gpmu_version(uint32_t cur_major, uint32_t cur_minor, + uint32_t min_major, uint32_t min_minor) +{ + return ((cur_major > min_major) || + ((cur_major == min_major) && (cur_minor >= min_minor))); +} + +void a5xx_gpmu_ucode_init(struct msm_gpu *gpu) +{ + struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); + struct a5xx_gpu *a5xx_gpu = to_a5xx_gpu(adreno_gpu); + struct drm_device *drm = gpu->dev; + const char *name; + const struct firmware *fw; + uint32_t version[2] = { 0, 0 }; + uint32_t dwords = 0, offset = 0; + uint32_t major = 0, minor = 0, bosize; + unsigned int *data, *ptr, *cmds; + unsigned int cmds_size; + + if (a5xx_gpu->gpmu_bo) + return; + + /* + * Read the firmware name from the device tree - if it doesn't exist + * then don't initialize the GPMU for this target + */ + if (of_property_read_string(GPU_OF_NODE(gpu), "qcom,gpmu-firmware", + &name)) + return; + + /* + * The version isn't mandatory, but if it exists, we need to enforce + * that the version of the GPMU firmware matches or is newer than the + * value + */ + of_property_read_u32_array(GPU_OF_NODE(gpu), "qcom,gpmu-version", + version, 2); + + /* Get the firmware */ + if (request_firmware(&fw, name, drm->dev)) { + DRM_ERROR("%s: Could not get GPMU firmware. GPMU will not be active\n", + gpu->name); + return; + } + + data = (unsigned int *) fw->data; + + /* + * The first dword is the size of the remaining data in dwords. Use it + * as a checksum of sorts and make sure it matches the actual size of + * the firmware that we read + */ + + if (fw->size < 8 || (data[0] < 2) || (data[0] >= (fw->size >> 2))) + goto out; + + /* The second dword is an ID - look for 2 (GPMU_FIRMWARE_ID) */ + if (data[1] != 2) + goto out; + + /* Read the header and get the major/minor of the read firmware */ + if (_read_header(&data[2], fw->size - 8, &major, &minor)) + goto out; + + if (!_check_gpmu_version(major, minor, version[0], version[1])) { + DRM_ERROR("%s: Loaded GPMU version %d.%d is too old\n", + gpu->name, major, minor); + goto out; + } + + cmds = data + data[2] + 3; + cmds_size = data[0] - data[2] - 2; + + /* + * A single type4 opcode can only have so many values attached so + * add enough opcodes to load the all the commands + */ + bosize = (cmds_size + (cmds_size / TYPE4_MAX_PAYLOAD) + 1) << 2; + + ptr = msm_gem_kernel_new(drm, bosize, + MSM_BO_UNCACHED | MSM_BO_GPU_READONLY, gpu->aspace, + &a5xx_gpu->gpmu_bo, &a5xx_gpu->gpmu_iova); + if (IS_ERR(ptr)) + goto err; + + while (cmds_size > 0) { + int i; + uint32_t _size = cmds_size > TYPE4_MAX_PAYLOAD ? + TYPE4_MAX_PAYLOAD : cmds_size; + + ptr[dwords++] = PKT4(REG_A5XX_GPMU_INST_RAM_BASE + offset, + _size); + + for (i = 0; i < _size; i++) + ptr[dwords++] = *cmds++; + + offset += _size; + cmds_size -= _size; + } + + a5xx_gpu->gpmu_dwords = dwords; + + goto out; + +err: + if (a5xx_gpu->gpmu_iova) + msm_gem_put_iova(a5xx_gpu->gpmu_bo, gpu->aspace); + if (a5xx_gpu->gpmu_bo) + drm_gem_object_unreference_unlocked(a5xx_gpu->gpmu_bo); + + a5xx_gpu->gpmu_bo = NULL; + a5xx_gpu->gpmu_iova = 0; + a5xx_gpu->gpmu_dwords = 0; + +out: + /* No need to keep that firmware laying around anymore */ + release_firmware(fw); +} --- /dev/null 2019-10-24 16:47:25.704025805 +0200 +++ linux-4.4.115-fbx/drivers/gpu/drm/msm/adreno/a5xx_preempt.c 2019-01-22 16:16:23.483246225 +0100 @@ -0,0 +1,359 @@ +/* Copyright (c) 2016-2017 The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include "msm_gem.h" +#include "msm_iommu.h" +#include "a5xx_gpu.h" + +/* + * Try to transition the preemption state from old to new. Return + * true on success or false if the original state wasn't 'old' + */ +static inline bool try_preempt_state(struct a5xx_gpu *a5xx_gpu, + enum preempt_state old, enum preempt_state new) +{ + enum preempt_state cur = atomic_cmpxchg(&a5xx_gpu->preempt_state, + old, new); + + return (cur == old); +} + +/* + * Force the preemption state to the specified state. This is used in cases + * where the current state is known and won't change + */ +static inline void set_preempt_state(struct a5xx_gpu *gpu, + enum preempt_state new) +{ + /* + * preempt_state may be read by other cores trying to trigger a + * preemption or in the interrupt handler so barriers are needed + * before... + */ + smp_mb__before_atomic(); + atomic_set(&gpu->preempt_state, new); + /* ... and after*/ + smp_mb__after_atomic(); +} + +/* Write the most recent wptr for the given ring into the hardware */ +static inline void update_wptr(struct msm_gpu *gpu, struct msm_ringbuffer *ring) +{ + unsigned long flags; + uint32_t wptr; + + if (!ring) + return; + + spin_lock_irqsave(&ring->lock, flags); + wptr = get_wptr(ring); + spin_unlock_irqrestore(&ring->lock, flags); + + gpu_write(gpu, REG_A5XX_CP_RB_WPTR, wptr); +} + +/* Return the highest priority ringbuffer with something in it */ +static struct msm_ringbuffer *get_next_ring(struct msm_gpu *gpu) +{ + unsigned long flags; + int i; + + /* + * Find the highest prority ringbuffer that isn't empty and jump + * to it (0 being the highest and gpu->nr_rings - 1 being the + * lowest) + */ + for (i = 0; i < gpu->nr_rings; i++) { + bool empty; + struct msm_ringbuffer *ring = gpu->rb[i]; + + spin_lock_irqsave(&ring->lock, flags); + empty = (get_wptr(ring) == ring->memptrs->rptr); + spin_unlock_irqrestore(&ring->lock, flags); + + if (!empty) + return ring; + } + + return NULL; +} + +static void a5xx_preempt_timer(unsigned long data) +{ + struct a5xx_gpu *a5xx_gpu = (struct a5xx_gpu *) data; + struct msm_gpu *gpu = &a5xx_gpu->base.base; + struct drm_device *dev = gpu->dev; + struct msm_drm_private *priv = dev->dev_private; + + if (!try_preempt_state(a5xx_gpu, PREEMPT_TRIGGERED, PREEMPT_FAULTED)) + return; + + dev_err(dev->dev, "%s: preemption timed out\n", gpu->name); + queue_work(priv->wq, &gpu->recover_work); +} + +/* Try to trigger a preemption switch */ +void a5xx_preempt_trigger(struct msm_gpu *gpu) +{ + struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); + struct a5xx_gpu *a5xx_gpu = to_a5xx_gpu(adreno_gpu); + unsigned long flags; + struct msm_ringbuffer *ring; + + if (gpu->nr_rings == 1) + return; + + /* + * Try to start preemption by moving from NONE to START. If + * unsuccessful, a preemption is already in flight + */ + if (!try_preempt_state(a5xx_gpu, PREEMPT_NONE, PREEMPT_START)) + return; + + /* Get the next ring to preempt to */ + ring = get_next_ring(gpu); + + /* + * If no ring is populated or the highest priority ring is the current + * one do nothing except to update the wptr to the latest and greatest + */ + if (!ring || (a5xx_gpu->cur_ring == ring)) { + /* + * Its possible that while a preemption request is in progress + * from an irq context, a user context trying to submit might + * fail to update the write pointer, because it determines + * that the preempt state is not PREEMPT_NONE. + * + * Close the race by introducing an intermediate + * state PREEMPT_ABORT to let the submit path + * know that the ringbuffer is not going to change + * and can safely update the write pointer. + */ + + set_preempt_state(a5xx_gpu, PREEMPT_ABORT); + update_wptr(gpu, a5xx_gpu->cur_ring); + set_preempt_state(a5xx_gpu, PREEMPT_NONE); + return; + } + + /* Make sure the wptr doesn't update while we're in motion */ + spin_lock_irqsave(&ring->lock, flags); + a5xx_gpu->preempt[ring->id]->wptr = get_wptr(ring); + spin_unlock_irqrestore(&ring->lock, flags); + + /* Do read barrier to make sure we have updated pagetable info */ + rmb(); + + /* Set the SMMU info for the preemption */ + if (a5xx_gpu->smmu_info) { + a5xx_gpu->smmu_info->ttbr0 = ring->memptrs->ttbr0; + a5xx_gpu->smmu_info->contextidr = ring->memptrs->contextidr; + } + + /* Set the address of the incoming preemption record */ + gpu_write64(gpu, REG_A5XX_CP_CONTEXT_SWITCH_RESTORE_ADDR_LO, + REG_A5XX_CP_CONTEXT_SWITCH_RESTORE_ADDR_HI, + a5xx_gpu->preempt_iova[ring->id]); + + a5xx_gpu->next_ring = ring; + + /* Start a timer to catch a stuck preemption */ + mod_timer(&a5xx_gpu->preempt_timer, jiffies + msecs_to_jiffies(10000)); + + /* Set the preemption state to triggered */ + set_preempt_state(a5xx_gpu, PREEMPT_TRIGGERED); + + /* Make sure everything is written before hitting the button */ + wmb(); + + /* And actually start the preemption */ + gpu_write(gpu, REG_A5XX_CP_CONTEXT_SWITCH_CNTL, 1); +} + +void a5xx_preempt_irq(struct msm_gpu *gpu) +{ + uint32_t status; + struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); + struct a5xx_gpu *a5xx_gpu = to_a5xx_gpu(adreno_gpu); + struct drm_device *dev = gpu->dev; + struct msm_drm_private *priv = dev->dev_private; + + if (!try_preempt_state(a5xx_gpu, PREEMPT_TRIGGERED, PREEMPT_PENDING)) + return; + + /* Delete the preemption watchdog timer */ + del_timer(&a5xx_gpu->preempt_timer); + + /* + * The hardware should be setting CP_CONTEXT_SWITCH_CNTL to zero before + * firing the interrupt, but there is a non zero chance of a hardware + * condition or a software race that could set it again before we have a + * chance to finish. If that happens, log and go for recovery + */ + status = gpu_read(gpu, REG_A5XX_CP_CONTEXT_SWITCH_CNTL); + if (unlikely(status)) { + set_preempt_state(a5xx_gpu, PREEMPT_FAULTED); + dev_err(dev->dev, "%s: Preemption failed to complete\n", + gpu->name); + queue_work(priv->wq, &gpu->recover_work); + return; + } + + a5xx_gpu->cur_ring = a5xx_gpu->next_ring; + a5xx_gpu->next_ring = NULL; + + update_wptr(gpu, a5xx_gpu->cur_ring); + + set_preempt_state(a5xx_gpu, PREEMPT_NONE); +} + +void a5xx_preempt_hw_init(struct msm_gpu *gpu) +{ + struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); + struct a5xx_gpu *a5xx_gpu = to_a5xx_gpu(adreno_gpu); + struct msm_ringbuffer *ring; + int i; + + if (gpu->nr_rings > 1) { + /* Clear the preemption records */ + FOR_EACH_RING(gpu, ring, i) { + if (ring) { + a5xx_gpu->preempt[ring->id]->wptr = 0; + a5xx_gpu->preempt[ring->id]->rptr = 0; + a5xx_gpu->preempt[ring->id]->rbase = ring->iova; + } + } + } + + /* Tell the CP where to find the smmu_info buffer */ + gpu_write64(gpu, REG_A5XX_CP_CONTEXT_SWITCH_SMMU_INFO_LO, + REG_A5XX_CP_CONTEXT_SWITCH_SMMU_INFO_HI, + a5xx_gpu->smmu_info_iova); + + /* Reset the preemption state */ + set_preempt_state(a5xx_gpu, PREEMPT_NONE); + + /* Always come up on rb 0 */ + a5xx_gpu->cur_ring = gpu->rb[0]; +} + +static int preempt_init_ring(struct a5xx_gpu *a5xx_gpu, + struct msm_ringbuffer *ring) +{ + struct adreno_gpu *adreno_gpu = &a5xx_gpu->base; + struct msm_gpu *gpu = &adreno_gpu->base; + struct a5xx_preempt_record *ptr; + struct drm_gem_object *bo; + u64 iova; + + ptr = msm_gem_kernel_new(gpu->dev, + A5XX_PREEMPT_RECORD_SIZE + A5XX_PREEMPT_COUNTER_SIZE, + MSM_BO_UNCACHED | MSM_BO_PRIVILEGED, + gpu->aspace, &bo, &iova); + + if (IS_ERR(ptr)) + return PTR_ERR(ptr); + + a5xx_gpu->preempt_bo[ring->id] = bo; + a5xx_gpu->preempt_iova[ring->id] = iova; + a5xx_gpu->preempt[ring->id] = ptr; + + /* Set up the defaults on the preemption record */ + + ptr->magic = A5XX_PREEMPT_RECORD_MAGIC; + ptr->info = 0; + ptr->data = 0; + ptr->cntl = MSM_GPU_RB_CNTL_DEFAULT; + ptr->rptr_addr = rbmemptr(ring, rptr); + ptr->counter = iova + A5XX_PREEMPT_RECORD_SIZE; + + return 0; +} + +void a5xx_preempt_fini(struct msm_gpu *gpu) +{ + struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); + struct a5xx_gpu *a5xx_gpu = to_a5xx_gpu(adreno_gpu); + struct msm_ringbuffer *ring; + int i; + + FOR_EACH_RING(gpu, ring, i) { + if (!ring || !a5xx_gpu->preempt_bo[i]) + continue; + + if (a5xx_gpu->preempt_iova[i]) + msm_gem_put_iova(a5xx_gpu->preempt_bo[i], gpu->aspace); + + drm_gem_object_unreference_unlocked(a5xx_gpu->preempt_bo[i]); + + a5xx_gpu->preempt_bo[i] = NULL; + } + + if (a5xx_gpu->smmu_info_bo) { + if (a5xx_gpu->smmu_info_iova) + msm_gem_put_iova(a5xx_gpu->smmu_info_bo, gpu->aspace); + drm_gem_object_unreference_unlocked(a5xx_gpu->smmu_info_bo); + a5xx_gpu->smmu_info_bo = NULL; + } +} + +void a5xx_preempt_init(struct msm_gpu *gpu) +{ + struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); + struct a5xx_gpu *a5xx_gpu = to_a5xx_gpu(adreno_gpu); + struct msm_ringbuffer *ring; + struct a5xx_smmu_info *ptr; + struct drm_gem_object *bo; + uint64_t iova; + int i; + + /* No preemption if we only have one ring */ + if (gpu->nr_rings <= 1) + return; + + FOR_EACH_RING(gpu, ring, i) { + if (!ring) + continue; + + if (preempt_init_ring(a5xx_gpu, ring)) + goto fail; + } + + if (msm_iommu_allow_dynamic(gpu->aspace->mmu)) { + ptr = msm_gem_kernel_new(gpu->dev, + sizeof(struct a5xx_smmu_info), + MSM_BO_UNCACHED | MSM_BO_PRIVILEGED, + gpu->aspace, &bo, &iova); + + if (IS_ERR(ptr)) + goto fail; + + ptr->magic = A5XX_SMMU_INFO_MAGIC; + + a5xx_gpu->smmu_info_bo = bo; + a5xx_gpu->smmu_info_iova = iova; + a5xx_gpu->smmu_info = ptr; + } + + setup_timer(&a5xx_gpu->preempt_timer, a5xx_preempt_timer, + (unsigned long) a5xx_gpu); + + return; +fail: + /* + * On any failure our adventure is over. Clean up and + * set nr_rings to 1 to force preemption off + */ + a5xx_preempt_fini(gpu); + gpu->nr_rings = 1; +} --- /dev/null 2019-10-24 16:47:25.704025805 +0200 +++ linux-4.4.115-fbx/drivers/gpu/drm/msm/adreno/a5xx_snapshot.c 2019-01-22 16:16:23.483246225 +0100 @@ -0,0 +1,815 @@ +/* Copyright (c) 2016-2017 The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include "msm_gpu.h" +#include "msm_gem.h" +#include "a5xx_gpu.h" +#include "msm_snapshot_api.h" + +#define A5XX_NR_SHADER_BANKS 4 + +/* + * These are a list of the registers that need to be read through the HLSQ + * aperture through the crashdumper. These are not nominally accessible from + * the CPU on a secure platform. + */ +static const struct { + u32 type; + u32 regoffset; + u32 count; +} a5xx_hlsq_aperture_regs[] = { + { 0x35, 0xE00, 0x32 }, /* HSLQ non-context */ + { 0x31, 0x2080, 0x1 }, /* HLSQ 2D context 0 */ + { 0x33, 0x2480, 0x1 }, /* HLSQ 2D context 1 */ + { 0x32, 0xE780, 0x62 }, /* HLSQ 3D context 0 */ + { 0x34, 0xEF80, 0x62 }, /* HLSQ 3D context 1 */ + { 0x3f, 0x0EC0, 0x40 }, /* SP non-context */ + { 0x3d, 0x2040, 0x1 }, /* SP 2D context 0 */ + { 0x3b, 0x2440, 0x1 }, /* SP 2D context 1 */ + { 0x3e, 0xE580, 0x180 }, /* SP 3D context 0 */ + { 0x3c, 0xED80, 0x180 }, /* SP 3D context 1 */ + { 0x3a, 0x0F00, 0x1c }, /* TP non-context */ + { 0x38, 0x2000, 0xa }, /* TP 2D context 0 */ + { 0x36, 0x2400, 0xa }, /* TP 2D context 1 */ + { 0x39, 0xE700, 0x80 }, /* TP 3D context 0 */ + { 0x37, 0xEF00, 0x80 }, /* TP 3D context 1 */ +}; + +/* + * The debugbus registers contain device state that presumably makes + * sense to the hardware designers. 'count' is the number of indexes to read, + * each index value is 64 bits + */ +static const struct { + enum a5xx_debugbus id; + u32 count; +} a5xx_debugbus_blocks[] = { + { A5XX_RBBM_DBGBUS_CP, 0x100, }, + { A5XX_RBBM_DBGBUS_RBBM, 0x100, }, + { A5XX_RBBM_DBGBUS_HLSQ, 0x100, }, + { A5XX_RBBM_DBGBUS_UCHE, 0x100, }, + { A5XX_RBBM_DBGBUS_DPM, 0x100, }, + { A5XX_RBBM_DBGBUS_TESS, 0x100, }, + { A5XX_RBBM_DBGBUS_PC, 0x100, }, + { A5XX_RBBM_DBGBUS_VFDP, 0x100, }, + { A5XX_RBBM_DBGBUS_VPC, 0x100, }, + { A5XX_RBBM_DBGBUS_TSE, 0x100, }, + { A5XX_RBBM_DBGBUS_RAS, 0x100, }, + { A5XX_RBBM_DBGBUS_VSC, 0x100, }, + { A5XX_RBBM_DBGBUS_COM, 0x100, }, + { A5XX_RBBM_DBGBUS_DCOM, 0x100, }, + { A5XX_RBBM_DBGBUS_LRZ, 0x100, }, + { A5XX_RBBM_DBGBUS_A2D_DSP, 0x100, }, + { A5XX_RBBM_DBGBUS_CCUFCHE, 0x100, }, + { A5XX_RBBM_DBGBUS_GPMU, 0x100, }, + { A5XX_RBBM_DBGBUS_RBP, 0x100, }, + { A5XX_RBBM_DBGBUS_HM, 0x100, }, + { A5XX_RBBM_DBGBUS_RBBM_CFG, 0x100, }, + { A5XX_RBBM_DBGBUS_VBIF_CX, 0x100, }, + { A5XX_RBBM_DBGBUS_GPC, 0x100, }, + { A5XX_RBBM_DBGBUS_LARC, 0x100, }, + { A5XX_RBBM_DBGBUS_HLSQ_SPTP, 0x100, }, + { A5XX_RBBM_DBGBUS_RB_0, 0x100, }, + { A5XX_RBBM_DBGBUS_RB_1, 0x100, }, + { A5XX_RBBM_DBGBUS_RB_2, 0x100, }, + { A5XX_RBBM_DBGBUS_RB_3, 0x100, }, + { A5XX_RBBM_DBGBUS_CCU_0, 0x100, }, + { A5XX_RBBM_DBGBUS_CCU_1, 0x100, }, + { A5XX_RBBM_DBGBUS_CCU_2, 0x100, }, + { A5XX_RBBM_DBGBUS_CCU_3, 0x100, }, + { A5XX_RBBM_DBGBUS_A2D_RAS_0, 0x100, }, + { A5XX_RBBM_DBGBUS_A2D_RAS_1, 0x100, }, + { A5XX_RBBM_DBGBUS_A2D_RAS_2, 0x100, }, + { A5XX_RBBM_DBGBUS_A2D_RAS_3, 0x100, }, + { A5XX_RBBM_DBGBUS_VFD_0, 0x100, }, + { A5XX_RBBM_DBGBUS_VFD_1, 0x100, }, + { A5XX_RBBM_DBGBUS_VFD_2, 0x100, }, + { A5XX_RBBM_DBGBUS_VFD_3, 0x100, }, + { A5XX_RBBM_DBGBUS_SP_0, 0x100, }, + { A5XX_RBBM_DBGBUS_SP_1, 0x100, }, + { A5XX_RBBM_DBGBUS_SP_2, 0x100, }, + { A5XX_RBBM_DBGBUS_SP_3, 0x100, }, + { A5XX_RBBM_DBGBUS_TPL1_0, 0x100, }, + { A5XX_RBBM_DBGBUS_TPL1_1, 0x100, }, + { A5XX_RBBM_DBGBUS_TPL1_2, 0x100, }, + { A5XX_RBBM_DBGBUS_TPL1_3, 0x100, }, +}; + +/* + * The shader blocks are read from the HLSQ aperture - each one has its own + * identifier for the aperture read + */ +static const struct { + enum a5xx_shader_blocks id; + u32 size; +} a5xx_shader_blocks[] = { + {A5XX_TP_W_MEMOBJ, 0x200}, + {A5XX_TP_W_MIPMAP_BASE, 0x3C0}, + {A5XX_TP_W_SAMPLER_TAG, 0x40}, + {A5XX_TP_S_3D_SAMPLER, 0x80}, + {A5XX_TP_S_3D_SAMPLER_TAG, 0x20}, + {A5XX_TP_S_CS_SAMPLER, 0x40}, + {A5XX_TP_S_CS_SAMPLER_TAG, 0x10}, + {A5XX_SP_W_CONST, 0x800}, + {A5XX_SP_W_CB_SIZE, 0x30}, + {A5XX_SP_W_CB_BASE, 0xF0}, + {A5XX_SP_W_STATE, 0x1}, + {A5XX_SP_S_3D_CONST, 0x800}, + {A5XX_SP_S_3D_CB_SIZE, 0x28}, + {A5XX_SP_S_3D_UAV_SIZE, 0x80}, + {A5XX_SP_S_CS_CONST, 0x400}, + {A5XX_SP_S_CS_CB_SIZE, 0x8}, + {A5XX_SP_S_CS_UAV_SIZE, 0x80}, + {A5XX_SP_S_3D_CONST_DIRTY, 0x12}, + {A5XX_SP_S_3D_CB_SIZE_DIRTY, 0x1}, + {A5XX_SP_S_3D_UAV_SIZE_DIRTY, 0x2}, + {A5XX_SP_S_CS_CONST_DIRTY, 0xA}, + {A5XX_SP_S_CS_CB_SIZE_DIRTY, 0x1}, + {A5XX_SP_S_CS_UAV_SIZE_DIRTY, 0x2}, + {A5XX_HLSQ_ICB_DIRTY, 0xB}, + {A5XX_SP_POWER_RESTORE_RAM_TAG, 0xA}, + {A5XX_TP_POWER_RESTORE_RAM_TAG, 0xA}, + {A5XX_TP_W_SAMPLER, 0x80}, + {A5XX_TP_W_MEMOBJ_TAG, 0x40}, + {A5XX_TP_S_3D_MEMOBJ, 0x200}, + {A5XX_TP_S_3D_MEMOBJ_TAG, 0x20}, + {A5XX_TP_S_CS_MEMOBJ, 0x100}, + {A5XX_TP_S_CS_MEMOBJ_TAG, 0x10}, + {A5XX_SP_W_INSTR, 0x800}, + {A5XX_SP_W_UAV_SIZE, 0x80}, + {A5XX_SP_W_UAV_BASE, 0x80}, + {A5XX_SP_W_INST_TAG, 0x40}, + {A5XX_SP_S_3D_INSTR, 0x800}, + {A5XX_SP_S_3D_CB_BASE, 0xC8}, + {A5XX_SP_S_3D_UAV_BASE, 0x80}, + {A5XX_SP_S_CS_INSTR, 0x400}, + {A5XX_SP_S_CS_CB_BASE, 0x28}, + {A5XX_SP_S_CS_UAV_BASE, 0x80}, + {A5XX_SP_S_3D_INSTR_DIRTY, 0x1}, + {A5XX_SP_S_3D_CB_BASE_DIRTY, 0x5}, + {A5XX_SP_S_3D_UAV_BASE_DIRTY, 0x2}, + {A5XX_SP_S_CS_INSTR_DIRTY, 0x1}, + {A5XX_SP_S_CS_CB_BASE_DIRTY, 0x1}, + {A5XX_SP_S_CS_UAV_BASE_DIRTY, 0x2}, + {A5XX_HLSQ_ICB, 0x200}, + {A5XX_HLSQ_ICB_CB_BASE_DIRTY, 0x4}, + {A5XX_SP_POWER_RESTORE_RAM, 0x140}, + {A5XX_TP_POWER_RESTORE_RAM, 0x40}, +}; + +/* + * The A5XX architecture has a a built in engine to asynchronously dump + * registers from the GPU. It is used to accelerate the copy of hundreds + * (thousands) of registers and as a safe way to access registers that might + * have secure data in them (if the GPU is in secure, the crashdumper returns + * bogus values for those registers). On a fully secured device the CPU will be + * blocked from accessing those registers directly and so the crashdump is the + * only way that we can access context registers and the shader banks for debug + * purposes. + * + * The downside of the crashdump is that it requires access to GPU accessible + * memory (so the VBIF and the bus and the SMMU need to be up and working) and + * you need enough memory to write the script for the crashdumper and to store + * the data that you are dumping so there is a balancing act between the work to + * set up a crash dumper and the value we get out of it. + */ + +/* + * The crashdump uses a pseudo-script format to read and write registers. Each + * operation is two 64 bit values. + * + * READ: + * [qword 0] [64:00] - The absolute IOVA address target for the register value + * [qword 1] [63:44] - the dword address of the register offset to read + * [15:00] - Number of dwords to read at once + * + * WRITE: + * [qword 0] [31:0] 32 bit value to write to the register + * [qword 1] [63:44] - the dword address of the register offset to write + * [21:21] - set 1 to write + * [15:00] - Number of dwords to write (usually 1) + * + * At the bottom of the script, write quadword zeros to trigger the end. + */ +struct crashdump { + struct drm_gem_object *bo; + void *ptr; + u64 iova; + u32 index; +}; + +#define CRASHDUMP_BO_SIZE (SZ_1M) +#define CRASHDUMP_SCRIPT_SIZE (256 * SZ_1K) +#define CRASHDUMP_DATA_SIZE (CRASHDUMP_BO_SIZE - CRASHDUMP_SCRIPT_SIZE) + +static int crashdump_init(struct msm_gpu *gpu, struct crashdump *crashdump) +{ + int ret = 0; + + crashdump->ptr = msm_gem_kernel_new_locked(gpu->dev, + CRASHDUMP_BO_SIZE, MSM_BO_UNCACHED, + gpu->aspace, &crashdump->bo, &crashdump->iova); + if (IS_ERR(crashdump->ptr)) { + ret = PTR_ERR(crashdump->ptr); + crashdump->ptr = NULL; + } + + return ret; +} + +static int crashdump_run(struct msm_gpu *gpu, struct crashdump *crashdump) +{ + if (!crashdump->ptr || !crashdump->index) + return -EINVAL; + + gpu_write(gpu, REG_A5XX_CP_CRASH_SCRIPT_BASE_LO, + lower_32_bits(crashdump->iova)); + gpu_write(gpu, REG_A5XX_CP_CRASH_SCRIPT_BASE_HI, + upper_32_bits(crashdump->iova)); + + gpu_write(gpu, REG_A5XX_CP_CRASH_DUMP_CNTL, 1); + + return spin_until(gpu_read(gpu, REG_A5XX_CP_CRASH_DUMP_CNTL) & 0x04); +} + +static void crashdump_destroy(struct msm_gpu *gpu, struct crashdump *crashdump) +{ + if (!crashdump->bo) + return; + + if (crashdump->iova) + msm_gem_put_iova(crashdump->bo, gpu->aspace); + + drm_gem_object_unreference(crashdump->bo); + + memset(crashdump, 0, sizeof(*crashdump)); +} + +static inline void CRASHDUMP_SCRIPT_WRITE(struct crashdump *crashdump, + u32 reg, u32 val) +{ + u64 *ptr = crashdump->ptr + crashdump->index; + + if (WARN_ON(crashdump->index + (2 * sizeof(u64)) + >= CRASHDUMP_SCRIPT_SIZE)) + return; + + /* This is the value to write */ + ptr[0] = (u64) val; + + /* + * This triggers a write to the specified register. 1 is the size of + * the write in dwords + */ + ptr[1] = (((u64) reg) << 44) | (1 << 21) | 1; + + crashdump->index += 2 * sizeof(u64); +} + +static inline void CRASHDUMP_SCRIPT_READ(struct crashdump *crashdump, + u32 reg, u32 count, u32 offset) +{ + u64 *ptr = crashdump->ptr + crashdump->index; + + if (WARN_ON(crashdump->index + (2 * sizeof(u64)) + >= CRASHDUMP_SCRIPT_SIZE)) + return; + + if (WARN_ON(offset + (count * sizeof(u32)) >= CRASHDUMP_DATA_SIZE)) + return; + + ptr[0] = (u64) crashdump->iova + CRASHDUMP_SCRIPT_SIZE + offset; + ptr[1] = (((u64) reg) << 44) | count; + + crashdump->index += 2 * sizeof(u64); +} + +static inline void *CRASHDUMP_DATA_PTR(struct crashdump *crashdump, u32 offset) +{ + if (WARN_ON(!crashdump->ptr || offset >= CRASHDUMP_DATA_SIZE)) + return NULL; + + return crashdump->ptr + CRASHDUMP_SCRIPT_SIZE + offset; +} + +static inline u32 CRASHDUMP_DATA_READ(struct crashdump *crashdump, u32 offset) +{ + return *((u32 *) CRASHDUMP_DATA_PTR(crashdump, offset)); +} + +static inline void CRASHDUMP_RESET(struct crashdump *crashdump) +{ + crashdump->index = 0; +} + +static inline void CRASHDUMP_END(struct crashdump *crashdump) +{ + u64 *ptr = crashdump->ptr + crashdump->index; + + if (WARN_ON((crashdump->index + (2 * sizeof(u64))) + >= CRASHDUMP_SCRIPT_SIZE)) + return; + + ptr[0] = 0; + ptr[1] = 0; + + crashdump->index += 2 * sizeof(u64); +} + +static u32 _crashdump_read_hlsq_aperture(struct crashdump *crashdump, + u32 offset, u32 statetype, u32 bank, + u32 count) +{ + CRASHDUMP_SCRIPT_WRITE(crashdump, REG_A5XX_HLSQ_DBG_READ_SEL, + A5XX_HLSQ_DBG_READ_SEL_STATETYPE(statetype) | bank); + + CRASHDUMP_SCRIPT_READ(crashdump, REG_A5XX_HLSQ_DBG_AHB_READ_APERTURE, + count, offset); + + return count * sizeof(u32); +} + +static u32 _copy_registers(struct msm_snapshot *snapshot, + struct crashdump *crashdump, u32 reg, u32 count, + u32 offset) +{ + int i; + u32 *ptr = (u32 *) (crashdump->ptr + CRASHDUMP_SCRIPT_SIZE + offset); + /* + * Write the offset of the first register of the group and the number of + * registers in the group + */ + SNAPSHOT_WRITE_U32(snapshot, ((count << 16) | reg)); + + /* Followed by each register value in the group */ + for (i = 0; i < count; i++) + SNAPSHOT_WRITE_U32(snapshot, ptr[i]); + + return count * sizeof(u32); +} + +/* + * Return the number of registers in each register group from the + * adreno_gpu->rgisters + */ +static inline u32 REG_COUNT(const unsigned int *ptr) +{ + return (ptr[1] - ptr[0]) + 1; +} + +/* + * Capture what registers we can from the CPU in case the crashdumper is + * unavailable or broken. This will omit the SP,TP and HLSQ registers, but + * you'll get everything else and that ain't bad + */ +static void a5xx_snapshot_registers_cpu(struct msm_gpu *gpu, + struct msm_snapshot *snapshot) +{ + struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); + struct msm_snapshot_regs header; + u32 regcount = 0, groups = 0; + int i; + + /* + * Before we write the section we need to figure out how big our data + * section will be + */ + for (i = 0; adreno_gpu->registers[i] != ~0; i += 2) { + regcount += REG_COUNT(&(adreno_gpu->registers[i])); + groups++; + } + + header.count = groups; + + /* + * We need one dword for each group and then one dword for each register + * value in that group + */ + if (!SNAPSHOT_HEADER(snapshot, header, SNAPSHOT_SECTION_REGS_V2, + regcount + groups)) + return; + + for (i = 0; adreno_gpu->registers[i] != ~0; i += 2) { + u32 count = REG_COUNT(&(adreno_gpu->registers[i])); + u32 reg = adreno_gpu->registers[i]; + int j; + + /* Write the offset and count for the group */ + SNAPSHOT_WRITE_U32(snapshot, (count << 16) | reg); + + /* Write each value in the group */ + for (j = 0; j < count; j++) + SNAPSHOT_WRITE_U32(snapshot, gpu_read(gpu, reg++)); + } +} + +static void a5xx_snapshot_registers(struct msm_gpu *gpu, + struct msm_snapshot *snapshot) +{ + struct msm_snapshot_regs header; + struct crashdump *crashdump = snapshot->priv; + u32 offset = 0, regcount = 0, groups = 0; + int i; + + /* + * First snapshot all the registers that we can from the CPU. Do this + * because the crashdumper has a tendency to "taint" the value of some + * of the registers (because the GPU implements the crashdumper) so we + * only want to use the crash dump facility if we have to + */ + a5xx_snapshot_registers_cpu(gpu, snapshot); + + if (!crashdump) + return; + + CRASHDUMP_RESET(crashdump); + + /* HLSQ and context registers behind the aperture */ + for (i = 0; i < ARRAY_SIZE(a5xx_hlsq_aperture_regs); i++) { + u32 count = a5xx_hlsq_aperture_regs[i].count; + + offset += _crashdump_read_hlsq_aperture(crashdump, offset, + a5xx_hlsq_aperture_regs[i].type, 0, count); + regcount += count; + + groups++; + } + + CRASHDUMP_END(crashdump); + + if (crashdump_run(gpu, crashdump)) + return; + + header.count = groups; + + /* + * The size of the data will be one dword for each "group" of registers, + * and then one dword for each of the registers in that group + */ + if (!SNAPSHOT_HEADER(snapshot, header, SNAPSHOT_SECTION_REGS_V2, + groups + regcount)) + return; + + /* Copy the registers to the snapshot */ + for (i = 0; i < ARRAY_SIZE(a5xx_hlsq_aperture_regs); i++) + offset += _copy_registers(snapshot, crashdump, + a5xx_hlsq_aperture_regs[i].regoffset, + a5xx_hlsq_aperture_regs[i].count, offset); +} + +static void _a5xx_snapshot_shader_bank(struct msm_snapshot *snapshot, + struct crashdump *crashdump, u32 block, u32 bank, + u32 size, u32 offset) +{ + void *src; + + struct msm_snapshot_shader header = { + .type = block, + .index = bank, + .size = size, + }; + + if (!SNAPSHOT_HEADER(snapshot, header, SNAPSHOT_SECTION_SHADER, size)) + return; + + src = CRASHDUMP_DATA_PTR(crashdump, offset); + + if (src) + SNAPSHOT_MEMCPY(snapshot, src, size * sizeof(u32)); +} + +static void a5xx_snapshot_shader_memory(struct msm_gpu *gpu, + struct msm_snapshot *snapshot) +{ + struct crashdump *crashdump = snapshot->priv; + u32 offset = 0; + int i; + + /* We can only get shader memory through the crashdump */ + if (!crashdump) + return; + + CRASHDUMP_RESET(crashdump); + + /* For each shader block */ + for (i = 0; i < ARRAY_SIZE(a5xx_shader_blocks); i++) { + int j; + + /* For each block, dump 4 banks */ + for (j = 0; j < A5XX_NR_SHADER_BANKS; j++) + offset += _crashdump_read_hlsq_aperture(crashdump, + offset, a5xx_shader_blocks[i].id, j, + a5xx_shader_blocks[i].size); + } + + CRASHDUMP_END(crashdump); + + /* If the crashdump fails we can't get shader memory any other way */ + if (crashdump_run(gpu, crashdump)) + return; + + /* Each bank of each shader gets its own snapshot section */ + for (offset = 0, i = 0; i < ARRAY_SIZE(a5xx_shader_blocks); i++) { + int j; + + for (j = 0; j < A5XX_NR_SHADER_BANKS; j++) { + _a5xx_snapshot_shader_bank(snapshot, crashdump, + a5xx_shader_blocks[i].id, j, + a5xx_shader_blocks[i].size, offset); + offset += a5xx_shader_blocks[i].size * sizeof(u32); + } + } +} + +#define A5XX_NUM_AXI_ARB_BLOCKS 2 +#define A5XX_NUM_XIN_BLOCKS 4 +#define VBIF_DATA_SIZE ((16 * A5XX_NUM_AXI_ARB_BLOCKS) + \ + (18 * A5XX_NUM_XIN_BLOCKS) + (12 * A5XX_NUM_XIN_BLOCKS)) + +static void a5xx_snapshot_debugbus_vbif(struct msm_gpu *gpu, + struct msm_snapshot *snapshot) +{ + int i; + struct msm_snapshot_debugbus header = { + .id = A5XX_RBBM_DBGBUS_VBIF, + .count = VBIF_DATA_SIZE, + }; + + if (!SNAPSHOT_HEADER(snapshot, header, SNAPSHOT_SECTION_DEBUGBUS, + VBIF_DATA_SIZE)) + return; + + gpu_rmw(gpu, REG_A5XX_VBIF_CLKON, A5XX_VBIF_CLKON_FORCE_ON_TESTBUS, + A5XX_VBIF_CLKON_FORCE_ON_TESTBUS); + + gpu_write(gpu, REG_A5XX_VBIF_TEST_BUS1_CTRL0, 0); + gpu_write(gpu, REG_A5XX_VBIF_TEST_BUS_OUT_CTRL, + A5XX_VBIF_TEST_BUS_OUT_CTRL_TEST_BUS_CTRL_EN); + + for (i = 0; i < A5XX_NUM_AXI_ARB_BLOCKS; i++) { + int j; + + gpu_write(gpu, REG_A5XX_VBIF_TEST_BUS2_CTRL0, 1 << (i + 16)); + for (j = 0; j < 16; j++) { + gpu_write(gpu, REG_A5XX_VBIF_TEST_BUS2_CTRL1, + A5XX_VBIF_TEST_BUS2_CTRL1_TEST_BUS2_DATA_SEL(j)); + SNAPSHOT_WRITE_U32(snapshot, gpu_read(gpu, + REG_A5XX_VBIF_TEST_BUS_OUT)); + } + } + + for (i = 0; i < A5XX_NUM_XIN_BLOCKS; i++) { + int j; + + gpu_write(gpu, REG_A5XX_VBIF_TEST_BUS2_CTRL0, 1 << i); + for (j = 0; j < 18; j++) { + gpu_write(gpu, REG_A5XX_VBIF_TEST_BUS2_CTRL1, + A5XX_VBIF_TEST_BUS2_CTRL1_TEST_BUS2_DATA_SEL(j)); + SNAPSHOT_WRITE_U32(snapshot, + gpu_read(gpu, REG_A5XX_VBIF_TEST_BUS_OUT)); + } + } + + for (i = 0; i < A5XX_NUM_XIN_BLOCKS; i++) { + int j; + + gpu_write(gpu, REG_A5XX_VBIF_TEST_BUS1_CTRL0, 1 << i); + for (j = 0; j < 12; j++) { + gpu_write(gpu, REG_A5XX_VBIF_TEST_BUS1_CTRL1, + A5XX_VBIF_TEST_BUS1_CTRL1_TEST_BUS1_DATA_SEL(j)); + SNAPSHOT_WRITE_U32(snapshot, gpu_read(gpu, + REG_A5XX_VBIF_TEST_BUS_OUT)); + } + } + +} + +static void a5xx_snapshot_debugbus_block(struct msm_gpu *gpu, + struct msm_snapshot *snapshot, u32 block, u32 count) +{ + int i; + struct msm_snapshot_debugbus header = { + .id = block, + .count = count * 2, /* Each value is 2 dwords */ + }; + + if (!SNAPSHOT_HEADER(snapshot, header, SNAPSHOT_SECTION_DEBUGBUS, + (count * 2))) + return; + + for (i = 0; i < count; i++) { + u32 reg = A5XX_RBBM_CFG_DBGBUS_SEL_A_PING_INDEX(i) | + A5XX_RBBM_CFG_DBGBUS_SEL_A_PING_BLK_SEL(block); + + gpu_write(gpu, REG_A5XX_RBBM_CFG_DBGBUS_SEL_A, reg); + gpu_write(gpu, REG_A5XX_RBBM_CFG_DBGBUS_SEL_B, reg); + gpu_write(gpu, REG_A5XX_RBBM_CFG_DBGBUS_SEL_C, reg); + gpu_write(gpu, REG_A5XX_RBBM_CFG_DBGBUS_SEL_D, reg); + + /* Each debugbus entry is a quad word */ + SNAPSHOT_WRITE_U32(snapshot, gpu_read(gpu, + REG_A5XX_RBBM_CFG_DBGBUS_TRACE_BUF2)); + SNAPSHOT_WRITE_U32(snapshot, + gpu_read(gpu, REG_A5XX_RBBM_CFG_DBGBUS_TRACE_BUF1)); + } +} + +static void a5xx_snapshot_debugbus(struct msm_gpu *gpu, + struct msm_snapshot *snapshot) +{ + int i; + + gpu_write(gpu, REG_A5XX_RBBM_CFG_DBGBUS_CNTLM, + A5XX_RBBM_CFG_DBGBUS_CNTLM_ENABLE(0xF)); + + for (i = 0; i < ARRAY_SIZE(a5xx_debugbus_blocks); i++) + a5xx_snapshot_debugbus_block(gpu, snapshot, + a5xx_debugbus_blocks[i].id, + a5xx_debugbus_blocks[i].count); + + /* VBIF is special and not in a good way */ + a5xx_snapshot_debugbus_vbif(gpu, snapshot); +} + +static void a5xx_snapshot_cp_merciu(struct msm_gpu *gpu, + struct msm_snapshot *snapshot) +{ + unsigned int i; + struct msm_snapshot_debug header = { + .type = SNAPSHOT_DEBUG_CP_MERCIU, + .size = 64 << 1, /* Data size is 2 dwords per entry */ + }; + + if (!SNAPSHOT_HEADER(snapshot, header, SNAPSHOT_SECTION_DEBUG, 64 << 1)) + return; + + gpu_write(gpu, REG_A5XX_CP_MERCIU_DBG_ADDR, 0); + for (i = 0; i < 64; i++) { + SNAPSHOT_WRITE_U32(snapshot, + gpu_read(gpu, REG_A5XX_CP_MERCIU_DBG_DATA_1)); + SNAPSHOT_WRITE_U32(snapshot, + gpu_read(gpu, REG_A5XX_CP_MERCIU_DBG_DATA_2)); + } +} + +static void a5xx_snapshot_cp_roq(struct msm_gpu *gpu, + struct msm_snapshot *snapshot) +{ + int i; + struct msm_snapshot_debug header = { + .type = SNAPSHOT_DEBUG_CP_ROQ, + .size = 512, + }; + + if (!SNAPSHOT_HEADER(snapshot, header, SNAPSHOT_SECTION_DEBUG, 512)) + return; + + gpu_write(gpu, REG_A5XX_CP_ROQ_DBG_ADDR, 0); + for (i = 0; i < 512; i++) + SNAPSHOT_WRITE_U32(snapshot, + gpu_read(gpu, REG_A5XX_CP_ROQ_DBG_DATA)); +} + +static void a5xx_snapshot_cp_meq(struct msm_gpu *gpu, + struct msm_snapshot *snapshot) +{ + int i; + struct msm_snapshot_debug header = { + .type = SNAPSHOT_DEBUG_CP_MEQ, + .size = 64, + }; + + if (!SNAPSHOT_HEADER(snapshot, header, SNAPSHOT_SECTION_DEBUG, 64)) + return; + + gpu_write(gpu, REG_A5XX_CP_MEQ_DBG_ADDR, 0); + for (i = 0; i < 64; i++) + SNAPSHOT_WRITE_U32(snapshot, + gpu_read(gpu, REG_A5XX_CP_MEQ_DBG_DATA)); +} + +static void a5xx_snapshot_indexed_registers(struct msm_gpu *gpu, + struct msm_snapshot *snapshot, u32 addr, u32 data, + u32 count) +{ + unsigned int i; + struct msm_snapshot_indexed_regs header = { + .index_reg = addr, + .data_reg = data, + .start = 0, + .count = count, + }; + + if (!SNAPSHOT_HEADER(snapshot, header, SNAPSHOT_SECTION_INDEXED_REGS, + count)) + return; + + for (i = 0; i < count; i++) { + gpu_write(gpu, addr, i); + SNAPSHOT_WRITE_U32(snapshot, gpu_read(gpu, data)); + } +} + +static void a5xx_snapshot_preemption(struct msm_gpu *gpu, struct msm_snapshot + *snapshot) +{ + struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); + struct a5xx_gpu *a5xx_gpu = to_a5xx_gpu(adreno_gpu); + struct msm_snapshot_gpu_object header = { + .type = SNAPSHOT_GPU_OBJECT_GLOBAL, + .size = A5XX_PREEMPT_RECORD_SIZE >> 2, + .pt_base = 0, + }; + int index; + + if (gpu->nr_rings <= 1) + return; + + for (index = 0; index < gpu->nr_rings; index++) { + + header.gpuaddr = a5xx_gpu->preempt_iova[index]; + + if (!SNAPSHOT_HEADER(snapshot, header, + SNAPSHOT_SECTION_GPU_OBJECT_V2, + A5XX_PREEMPT_RECORD_SIZE >> 2)) + return; + + SNAPSHOT_MEMCPY(snapshot, a5xx_gpu->preempt[index], + A5XX_PREEMPT_RECORD_SIZE); + } +} + +int a5xx_snapshot(struct msm_gpu *gpu, struct msm_snapshot *snapshot) +{ + struct crashdump crashdump = { 0 }; + + if (!crashdump_init(gpu, &crashdump)) + snapshot->priv = &crashdump; + + /* To accurately read all registers, disable hardware clock gating */ + a5xx_set_hwcg(gpu, false); + + /* Kick it up to the generic level */ + adreno_snapshot(gpu, snapshot); + + /* Read the GPU registers */ + a5xx_snapshot_registers(gpu, snapshot); + + /* Read the shader memory banks */ + a5xx_snapshot_shader_memory(gpu, snapshot); + + /* Read the debugbus registers */ + a5xx_snapshot_debugbus(gpu, snapshot); + + /* PFP data */ + a5xx_snapshot_indexed_registers(gpu, snapshot, + REG_A5XX_CP_PFP_STAT_ADDR, REG_A5XX_CP_PFP_STAT_DATA, 36); + + /* ME data */ + a5xx_snapshot_indexed_registers(gpu, snapshot, + REG_A5XX_CP_ME_STAT_ADDR, REG_A5XX_CP_ME_STAT_DATA, 29); + + /* DRAW_STATE data */ + a5xx_snapshot_indexed_registers(gpu, snapshot, + REG_A5XX_CP_DRAW_STATE_ADDR, REG_A5XX_CP_DRAW_STATE_DATA, + 256); + + /* ME cache */ + a5xx_snapshot_indexed_registers(gpu, snapshot, + REG_A5XX_CP_ME_UCODE_DBG_ADDR, REG_A5XX_CP_ME_UCODE_DBG_DATA, + 0x53F); + + /* PFP cache */ + a5xx_snapshot_indexed_registers(gpu, snapshot, + REG_A5XX_CP_PFP_UCODE_DBG_ADDR, REG_A5XX_CP_PFP_UCODE_DBG_DATA, + 0x53F); + + /* ME queue */ + a5xx_snapshot_cp_meq(gpu, snapshot); + + /* CP ROQ */ + a5xx_snapshot_cp_roq(gpu, snapshot); + + /* CP MERCIU */ + a5xx_snapshot_cp_merciu(gpu, snapshot); + + /* Preemption records*/ + a5xx_snapshot_preemption(gpu, snapshot); + + crashdump_destroy(gpu, &crashdump); + snapshot->priv = NULL; + + /* Re-enable HWCG */ + a5xx_set_hwcg(gpu, true); + return 0; +} --- /dev/null 2019-10-24 16:47:25.704025805 +0200 +++ linux-4.4.115-fbx/drivers/gpu/drm/msm/adreno/a5xx.xml.h 2019-01-22 16:16:23.483246225 +0100 @@ -0,0 +1,3493 @@ +#ifndef A5XX_XML +#define A5XX_XML + +/* Autogenerated file, DO NOT EDIT manually! + +This file was generated by the rules-ng-ng headergen tool in this git repository: +http://github.com/freedreno/envytools/ +git clone https://github.com/freedreno/envytools.git + +The rules-ng-ng source files this header was generated from are: +- ./rnndb/adreno.xml ( 431 bytes, from 2016-10-24 21:12:27) +- ./rnndb/freedreno_copyright.xml ( 1572 bytes, from 2016-10-24 21:12:27) +- ./rnndb/adreno/a2xx.xml ( 32901 bytes, from 2016-10-24 21:12:27) +- ./rnndb/adreno/adreno_common.xml ( 12025 bytes, from 2016-10-24 21:12:27) +- ./rnndb/adreno/adreno_pm4.xml ( 19684 bytes, from 2016-10-24 21:12:27) +- ./rnndb/adreno/a3xx.xml ( 83840 bytes, from 2016-10-24 21:12:27) +- ./rnndb/adreno/a4xx.xml ( 110708 bytes, from 2016-10-24 21:12:27) +- ./rnndb/adreno/a5xx.xml ( 86963 bytes, from 2017-03-03 16:01:09) +- ./rnndb/adreno/ocmem.xml ( 1773 bytes, from 2016-10-24 21:12:27) + +Copyright (C) 2013-2017 by the following authors: +- Rob Clark (robclark) +- Ilia Mirkin (imirkin) + +Permission is hereby granted, free of charge, to any person obtaining +a copy of this software and associated documentation files (the +"Software"), to deal in the Software without restriction, including +without limitation the rights to use, copy, modify, merge, publish, +distribute, sublicense, and/or sell copies of the Software, and to +permit persons to whom the Software is furnished to do so, subject to +the following conditions: + +The above copyright notice and this permission notice (including the +next paragraph) shall be included in all copies or substantial +portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE +LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION +OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION +WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +*/ + + +enum a5xx_color_fmt { + RB5_R8_UNORM = 3, + RB5_R5G5B5A1_UNORM = 10, + RB5_R8G8B8A8_UNORM = 48, + RB5_R8G8B8_UNORM = 49, + RB5_R8G8B8A8_UINT = 51, + RB5_R10G10B10A2_UINT = 58, + RB5_R16G16B16A16_FLOAT = 98, +}; + +enum a5xx_tile_mode { + TILE5_LINEAR = 0, + TILE5_2 = 2, + TILE5_3 = 3, +}; + +enum a5xx_vtx_fmt { + VFMT5_8_UNORM = 3, + VFMT5_8_SNORM = 4, + VFMT5_8_UINT = 5, + VFMT5_8_SINT = 6, + VFMT5_8_8_UNORM = 15, + VFMT5_8_8_SNORM = 16, + VFMT5_8_8_UINT = 17, + VFMT5_8_8_SINT = 18, + VFMT5_16_UNORM = 21, + VFMT5_16_SNORM = 22, + VFMT5_16_FLOAT = 23, + VFMT5_16_UINT = 24, + VFMT5_16_SINT = 25, + VFMT5_8_8_8_UNORM = 33, + VFMT5_8_8_8_SNORM = 34, + VFMT5_8_8_8_UINT = 35, + VFMT5_8_8_8_SINT = 36, + VFMT5_8_8_8_8_UNORM = 48, + VFMT5_8_8_8_8_SNORM = 50, + VFMT5_8_8_8_8_UINT = 51, + VFMT5_8_8_8_8_SINT = 52, + VFMT5_16_16_UNORM = 67, + VFMT5_16_16_SNORM = 68, + VFMT5_16_16_FLOAT = 69, + VFMT5_16_16_UINT = 70, + VFMT5_16_16_SINT = 71, + VFMT5_32_UNORM = 72, + VFMT5_32_SNORM = 73, + VFMT5_32_FLOAT = 74, + VFMT5_32_UINT = 75, + VFMT5_32_SINT = 76, + VFMT5_32_FIXED = 77, + VFMT5_16_16_16_UNORM = 88, + VFMT5_16_16_16_SNORM = 89, + VFMT5_16_16_16_FLOAT = 90, + VFMT5_16_16_16_UINT = 91, + VFMT5_16_16_16_SINT = 92, + VFMT5_16_16_16_16_UNORM = 96, + VFMT5_16_16_16_16_SNORM = 97, + VFMT5_16_16_16_16_FLOAT = 98, + VFMT5_16_16_16_16_UINT = 99, + VFMT5_16_16_16_16_SINT = 100, + VFMT5_32_32_UNORM = 101, + VFMT5_32_32_SNORM = 102, + VFMT5_32_32_FLOAT = 103, + VFMT5_32_32_UINT = 104, + VFMT5_32_32_SINT = 105, + VFMT5_32_32_FIXED = 106, + VFMT5_32_32_32_UNORM = 112, + VFMT5_32_32_32_SNORM = 113, + VFMT5_32_32_32_UINT = 114, + VFMT5_32_32_32_SINT = 115, + VFMT5_32_32_32_FLOAT = 116, + VFMT5_32_32_32_FIXED = 117, + VFMT5_32_32_32_32_UNORM = 128, + VFMT5_32_32_32_32_SNORM = 129, + VFMT5_32_32_32_32_FLOAT = 130, + VFMT5_32_32_32_32_UINT = 131, + VFMT5_32_32_32_32_SINT = 132, + VFMT5_32_32_32_32_FIXED = 133, +}; + +enum a5xx_tex_fmt { + TFMT5_A8_UNORM = 2, + TFMT5_8_UNORM = 3, + TFMT5_4_4_4_4_UNORM = 8, + TFMT5_5_6_5_UNORM = 14, + TFMT5_L8_A8_UNORM = 19, + TFMT5_16_FLOAT = 23, + TFMT5_8_8_8_8_UNORM = 48, + TFMT5_10_10_10_2_UNORM = 54, + TFMT5_16_16_FLOAT = 69, + TFMT5_32_FLOAT = 74, + TFMT5_16_16_16_16_FLOAT = 98, + TFMT5_32_32_FLOAT = 103, + TFMT5_32_32_32_32_FLOAT = 130, + TFMT5_X8Z24_UNORM = 160, +}; + +enum a5xx_tex_fetchsize { + TFETCH5_1_BYTE = 0, + TFETCH5_2_BYTE = 1, + TFETCH5_4_BYTE = 2, + TFETCH5_8_BYTE = 3, + TFETCH5_16_BYTE = 4, +}; + +enum a5xx_depth_format { + DEPTH5_NONE = 0, + DEPTH5_16 = 1, + DEPTH5_24_8 = 2, + DEPTH5_32 = 4, +}; + +enum a5xx_debugbus { + A5XX_RBBM_DBGBUS_CP = 1, + A5XX_RBBM_DBGBUS_RBBM = 2, + A5XX_RBBM_DBGBUS_VBIF = 3, + A5XX_RBBM_DBGBUS_HLSQ = 4, + A5XX_RBBM_DBGBUS_UCHE = 5, + A5XX_RBBM_DBGBUS_DPM = 6, + A5XX_RBBM_DBGBUS_TESS = 7, + A5XX_RBBM_DBGBUS_PC = 8, + A5XX_RBBM_DBGBUS_VFDP = 9, + A5XX_RBBM_DBGBUS_VPC = 10, + A5XX_RBBM_DBGBUS_TSE = 11, + A5XX_RBBM_DBGBUS_RAS = 12, + A5XX_RBBM_DBGBUS_VSC = 13, + A5XX_RBBM_DBGBUS_COM = 14, + A5XX_RBBM_DBGBUS_DCOM = 15, + A5XX_RBBM_DBGBUS_LRZ = 16, + A5XX_RBBM_DBGBUS_A2D_DSP = 17, + A5XX_RBBM_DBGBUS_CCUFCHE = 18, + A5XX_RBBM_DBGBUS_GPMU = 19, + A5XX_RBBM_DBGBUS_RBP = 20, + A5XX_RBBM_DBGBUS_HM = 21, + A5XX_RBBM_DBGBUS_RBBM_CFG = 22, + A5XX_RBBM_DBGBUS_VBIF_CX = 23, + A5XX_RBBM_DBGBUS_GPC = 29, + A5XX_RBBM_DBGBUS_LARC = 30, + A5XX_RBBM_DBGBUS_HLSQ_SPTP = 31, + A5XX_RBBM_DBGBUS_RB_0 = 32, + A5XX_RBBM_DBGBUS_RB_1 = 33, + A5XX_RBBM_DBGBUS_RB_2 = 34, + A5XX_RBBM_DBGBUS_RB_3 = 35, + A5XX_RBBM_DBGBUS_CCU_0 = 40, + A5XX_RBBM_DBGBUS_CCU_1 = 41, + A5XX_RBBM_DBGBUS_CCU_2 = 42, + A5XX_RBBM_DBGBUS_CCU_3 = 43, + A5XX_RBBM_DBGBUS_A2D_RAS_0 = 48, + A5XX_RBBM_DBGBUS_A2D_RAS_1 = 49, + A5XX_RBBM_DBGBUS_A2D_RAS_2 = 50, + A5XX_RBBM_DBGBUS_A2D_RAS_3 = 51, + A5XX_RBBM_DBGBUS_VFD_0 = 56, + A5XX_RBBM_DBGBUS_VFD_1 = 57, + A5XX_RBBM_DBGBUS_VFD_2 = 58, + A5XX_RBBM_DBGBUS_VFD_3 = 59, + A5XX_RBBM_DBGBUS_SP_0 = 64, + A5XX_RBBM_DBGBUS_SP_1 = 65, + A5XX_RBBM_DBGBUS_SP_2 = 66, + A5XX_RBBM_DBGBUS_SP_3 = 67, + A5XX_RBBM_DBGBUS_TPL1_0 = 72, + A5XX_RBBM_DBGBUS_TPL1_1 = 73, + A5XX_RBBM_DBGBUS_TPL1_2 = 74, + A5XX_RBBM_DBGBUS_TPL1_3 = 75, +}; + +enum a5xx_shader_blocks { + A5XX_TP_W_MEMOBJ = 1, + A5XX_TP_W_SAMPLER = 2, + A5XX_TP_W_MIPMAP_BASE = 3, + A5XX_TP_W_MEMOBJ_TAG = 4, + A5XX_TP_W_SAMPLER_TAG = 5, + A5XX_TP_S_3D_MEMOBJ = 6, + A5XX_TP_S_3D_SAMPLER = 7, + A5XX_TP_S_3D_MEMOBJ_TAG = 8, + A5XX_TP_S_3D_SAMPLER_TAG = 9, + A5XX_TP_S_CS_MEMOBJ = 10, + A5XX_TP_S_CS_SAMPLER = 11, + A5XX_TP_S_CS_MEMOBJ_TAG = 12, + A5XX_TP_S_CS_SAMPLER_TAG = 13, + A5XX_SP_W_INSTR = 14, + A5XX_SP_W_CONST = 15, + A5XX_SP_W_UAV_SIZE = 16, + A5XX_SP_W_CB_SIZE = 17, + A5XX_SP_W_UAV_BASE = 18, + A5XX_SP_W_CB_BASE = 19, + A5XX_SP_W_INST_TAG = 20, + A5XX_SP_W_STATE = 21, + A5XX_SP_S_3D_INSTR = 22, + A5XX_SP_S_3D_CONST = 23, + A5XX_SP_S_3D_CB_BASE = 24, + A5XX_SP_S_3D_CB_SIZE = 25, + A5XX_SP_S_3D_UAV_BASE = 26, + A5XX_SP_S_3D_UAV_SIZE = 27, + A5XX_SP_S_CS_INSTR = 28, + A5XX_SP_S_CS_CONST = 29, + A5XX_SP_S_CS_CB_BASE = 30, + A5XX_SP_S_CS_CB_SIZE = 31, + A5XX_SP_S_CS_UAV_BASE = 32, + A5XX_SP_S_CS_UAV_SIZE = 33, + A5XX_SP_S_3D_INSTR_DIRTY = 34, + A5XX_SP_S_3D_CONST_DIRTY = 35, + A5XX_SP_S_3D_CB_BASE_DIRTY = 36, + A5XX_SP_S_3D_CB_SIZE_DIRTY = 37, + A5XX_SP_S_3D_UAV_BASE_DIRTY = 38, + A5XX_SP_S_3D_UAV_SIZE_DIRTY = 39, + A5XX_SP_S_CS_INSTR_DIRTY = 40, + A5XX_SP_S_CS_CONST_DIRTY = 41, + A5XX_SP_S_CS_CB_BASE_DIRTY = 42, + A5XX_SP_S_CS_CB_SIZE_DIRTY = 43, + A5XX_SP_S_CS_UAV_BASE_DIRTY = 44, + A5XX_SP_S_CS_UAV_SIZE_DIRTY = 45, + A5XX_HLSQ_ICB = 46, + A5XX_HLSQ_ICB_DIRTY = 47, + A5XX_HLSQ_ICB_CB_BASE_DIRTY = 48, + A5XX_SP_POWER_RESTORE_RAM = 64, + A5XX_SP_POWER_RESTORE_RAM_TAG = 65, + A5XX_TP_POWER_RESTORE_RAM = 66, + A5XX_TP_POWER_RESTORE_RAM_TAG = 67, +}; + +enum a5xx_tex_filter { + A5XX_TEX_NEAREST = 0, + A5XX_TEX_LINEAR = 1, + A5XX_TEX_ANISO = 2, +}; + +enum a5xx_tex_clamp { + A5XX_TEX_REPEAT = 0, + A5XX_TEX_CLAMP_TO_EDGE = 1, + A5XX_TEX_MIRROR_REPEAT = 2, + A5XX_TEX_CLAMP_TO_BORDER = 3, + A5XX_TEX_MIRROR_CLAMP = 4, +}; + +enum a5xx_tex_aniso { + A5XX_TEX_ANISO_1 = 0, + A5XX_TEX_ANISO_2 = 1, + A5XX_TEX_ANISO_4 = 2, + A5XX_TEX_ANISO_8 = 3, + A5XX_TEX_ANISO_16 = 4, +}; + +enum a5xx_tex_swiz { + A5XX_TEX_X = 0, + A5XX_TEX_Y = 1, + A5XX_TEX_Z = 2, + A5XX_TEX_W = 3, + A5XX_TEX_ZERO = 4, + A5XX_TEX_ONE = 5, +}; + +enum a5xx_tex_type { + A5XX_TEX_1D = 0, + A5XX_TEX_2D = 1, + A5XX_TEX_CUBE = 2, + A5XX_TEX_3D = 3, +}; + +#define A5XX_INT0_RBBM_GPU_IDLE 0x00000001 +#define A5XX_INT0_RBBM_AHB_ERROR 0x00000002 +#define A5XX_INT0_RBBM_TRANSFER_TIMEOUT 0x00000004 +#define A5XX_INT0_RBBM_ME_MS_TIMEOUT 0x00000008 +#define A5XX_INT0_RBBM_PFP_MS_TIMEOUT 0x00000010 +#define A5XX_INT0_RBBM_ETS_MS_TIMEOUT 0x00000020 +#define A5XX_INT0_RBBM_ATB_ASYNC_OVERFLOW 0x00000040 +#define A5XX_INT0_RBBM_GPC_ERROR 0x00000080 +#define A5XX_INT0_CP_SW 0x00000100 +#define A5XX_INT0_CP_HW_ERROR 0x00000200 +#define A5XX_INT0_CP_CCU_FLUSH_DEPTH_TS 0x00000400 +#define A5XX_INT0_CP_CCU_FLUSH_COLOR_TS 0x00000800 +#define A5XX_INT0_CP_CCU_RESOLVE_TS 0x00001000 +#define A5XX_INT0_CP_IB2 0x00002000 +#define A5XX_INT0_CP_IB1 0x00004000 +#define A5XX_INT0_CP_RB 0x00008000 +#define A5XX_INT0_CP_UNUSED_1 0x00010000 +#define A5XX_INT0_CP_RB_DONE_TS 0x00020000 +#define A5XX_INT0_CP_WT_DONE_TS 0x00040000 +#define A5XX_INT0_UNKNOWN_1 0x00080000 +#define A5XX_INT0_CP_CACHE_FLUSH_TS 0x00100000 +#define A5XX_INT0_UNUSED_2 0x00200000 +#define A5XX_INT0_RBBM_ATB_BUS_OVERFLOW 0x00400000 +#define A5XX_INT0_MISC_HANG_DETECT 0x00800000 +#define A5XX_INT0_UCHE_OOB_ACCESS 0x01000000 +#define A5XX_INT0_UCHE_TRAP_INTR 0x02000000 +#define A5XX_INT0_DEBBUS_INTR_0 0x04000000 +#define A5XX_INT0_DEBBUS_INTR_1 0x08000000 +#define A5XX_INT0_GPMU_VOLTAGE_DROOP 0x10000000 +#define A5XX_INT0_GPMU_FIRMWARE 0x20000000 +#define A5XX_INT0_ISDB_CPU_IRQ 0x40000000 +#define A5XX_INT0_ISDB_UNDER_DEBUG 0x80000000 +#define A5XX_CP_INT_CP_OPCODE_ERROR 0x00000001 +#define A5XX_CP_INT_CP_RESERVED_BIT_ERROR 0x00000002 +#define A5XX_CP_INT_CP_HW_FAULT_ERROR 0x00000004 +#define A5XX_CP_INT_CP_DMA_ERROR 0x00000008 +#define A5XX_CP_INT_CP_REGISTER_PROTECTION_ERROR 0x00000010 +#define A5XX_CP_INT_CP_AHB_ERROR 0x00000020 +#define REG_A5XX_CP_RB_BASE 0x00000800 + +#define REG_A5XX_CP_RB_BASE_HI 0x00000801 + +#define REG_A5XX_CP_RB_CNTL 0x00000802 + +#define REG_A5XX_CP_RB_RPTR_ADDR 0x00000804 + +#define REG_A5XX_CP_RB_RPTR_ADDR_HI 0x00000805 + +#define REG_A5XX_CP_RB_RPTR 0x00000806 + +#define REG_A5XX_CP_RB_WPTR 0x00000807 + +#define REG_A5XX_CP_PFP_STAT_ADDR 0x00000808 + +#define REG_A5XX_CP_PFP_STAT_DATA 0x00000809 + +#define REG_A5XX_CP_DRAW_STATE_ADDR 0x0000080b + +#define REG_A5XX_CP_DRAW_STATE_DATA 0x0000080c + +#define REG_A5XX_CP_CRASH_SCRIPT_BASE_LO 0x00000817 + +#define REG_A5XX_CP_CRASH_SCRIPT_BASE_HI 0x00000818 + +#define REG_A5XX_CP_CRASH_DUMP_CNTL 0x00000819 + +#define REG_A5XX_CP_ME_STAT_ADDR 0x0000081a + +#define REG_A5XX_CP_ROQ_THRESHOLDS_1 0x0000081f + +#define REG_A5XX_CP_ROQ_THRESHOLDS_2 0x00000820 + +#define REG_A5XX_CP_ROQ_DBG_ADDR 0x00000821 + +#define REG_A5XX_CP_ROQ_DBG_DATA 0x00000822 + +#define REG_A5XX_CP_MEQ_DBG_ADDR 0x00000823 + +#define REG_A5XX_CP_MEQ_DBG_DATA 0x00000824 + +#define REG_A5XX_CP_MEQ_THRESHOLDS 0x00000825 + +#define REG_A5XX_CP_MERCIU_SIZE 0x00000826 + +#define REG_A5XX_CP_MERCIU_DBG_ADDR 0x00000827 + +#define REG_A5XX_CP_MERCIU_DBG_DATA_1 0x00000828 + +#define REG_A5XX_CP_MERCIU_DBG_DATA_2 0x00000829 + +#define REG_A5XX_CP_PFP_UCODE_DBG_ADDR 0x0000082a + +#define REG_A5XX_CP_PFP_UCODE_DBG_DATA 0x0000082b + +#define REG_A5XX_CP_ME_UCODE_DBG_ADDR 0x0000082f + +#define REG_A5XX_CP_ME_UCODE_DBG_DATA 0x00000830 + +#define REG_A5XX_CP_CNTL 0x00000831 + +#define REG_A5XX_CP_PFP_ME_CNTL 0x00000832 + +#define REG_A5XX_CP_CHICKEN_DBG 0x00000833 + +#define REG_A5XX_CP_PFP_INSTR_BASE_LO 0x00000835 + +#define REG_A5XX_CP_PFP_INSTR_BASE_HI 0x00000836 + +#define REG_A5XX_CP_ME_INSTR_BASE_LO 0x00000838 + +#define REG_A5XX_CP_ME_INSTR_BASE_HI 0x00000839 + +#define REG_A5XX_CP_CONTEXT_SWITCH_CNTL 0x0000083b + +#define REG_A5XX_CP_CONTEXT_SWITCH_RESTORE_ADDR_LO 0x0000083c + +#define REG_A5XX_CP_CONTEXT_SWITCH_RESTORE_ADDR_HI 0x0000083d + +#define REG_A5XX_CP_CONTEXT_SWITCH_SAVE_ADDR_LO 0x0000083e + +#define REG_A5XX_CP_CONTEXT_SWITCH_SAVE_ADDR_HI 0x0000083f + +#define REG_A5XX_CP_CONTEXT_SWITCH_SMMU_INFO_LO 0x00000840 + +#define REG_A5XX_CP_CONTEXT_SWITCH_SMMU_INFO_HI 0x00000841 + +#define REG_A5XX_CP_ADDR_MODE_CNTL 0x00000860 + +#define REG_A5XX_CP_ME_STAT_DATA 0x00000b14 + +#define REG_A5XX_CP_WFI_PEND_CTR 0x00000b15 + +#define REG_A5XX_CP_INTERRUPT_STATUS 0x00000b18 + +#define REG_A5XX_CP_HW_FAULT 0x00000b1a + +#define REG_A5XX_CP_PROTECT_STATUS 0x00000b1c + +#define REG_A5XX_CP_IB1_BASE 0x00000b1f + +#define REG_A5XX_CP_IB1_BASE_HI 0x00000b20 + +#define REG_A5XX_CP_IB1_BUFSZ 0x00000b21 + +#define REG_A5XX_CP_IB2_BASE 0x00000b22 + +#define REG_A5XX_CP_IB2_BASE_HI 0x00000b23 + +#define REG_A5XX_CP_IB2_BUFSZ 0x00000b24 + +static inline uint32_t REG_A5XX_CP_SCRATCH(uint32_t i0) { return 0x00000b78 + 0x1*i0; } + +static inline uint32_t REG_A5XX_CP_SCRATCH_REG(uint32_t i0) { return 0x00000b78 + 0x1*i0; } + +static inline uint32_t REG_A5XX_CP_PROTECT(uint32_t i0) { return 0x00000880 + 0x1*i0; } + +static inline uint32_t REG_A5XX_CP_PROTECT_REG(uint32_t i0) { return 0x00000880 + 0x1*i0; } +#define A5XX_CP_PROTECT_REG_BASE_ADDR__MASK 0x0001ffff +#define A5XX_CP_PROTECT_REG_BASE_ADDR__SHIFT 0 +static inline uint32_t A5XX_CP_PROTECT_REG_BASE_ADDR(uint32_t val) +{ + return ((val) << A5XX_CP_PROTECT_REG_BASE_ADDR__SHIFT) & A5XX_CP_PROTECT_REG_BASE_ADDR__MASK; +} +#define A5XX_CP_PROTECT_REG_MASK_LEN__MASK 0x1f000000 +#define A5XX_CP_PROTECT_REG_MASK_LEN__SHIFT 24 +static inline uint32_t A5XX_CP_PROTECT_REG_MASK_LEN(uint32_t val) +{ + return ((val) << A5XX_CP_PROTECT_REG_MASK_LEN__SHIFT) & A5XX_CP_PROTECT_REG_MASK_LEN__MASK; +} +#define A5XX_CP_PROTECT_REG_TRAP_WRITE 0x20000000 +#define A5XX_CP_PROTECT_REG_TRAP_READ 0x40000000 + +#define REG_A5XX_CP_PROTECT_CNTL 0x000008a0 + +#define REG_A5XX_CP_AHB_FAULT 0x00000b1b + +#define REG_A5XX_CP_PERFCTR_CP_SEL_0 0x00000bb0 + +#define REG_A5XX_CP_PERFCTR_CP_SEL_1 0x00000bb1 + +#define REG_A5XX_CP_PERFCTR_CP_SEL_2 0x00000bb2 + +#define REG_A5XX_CP_PERFCTR_CP_SEL_3 0x00000bb3 + +#define REG_A5XX_CP_PERFCTR_CP_SEL_4 0x00000bb4 + +#define REG_A5XX_CP_PERFCTR_CP_SEL_5 0x00000bb5 + +#define REG_A5XX_CP_PERFCTR_CP_SEL_6 0x00000bb6 + +#define REG_A5XX_CP_PERFCTR_CP_SEL_7 0x00000bb7 + +#define REG_A5XX_VSC_ADDR_MODE_CNTL 0x00000bc1 + +#define REG_A5XX_CP_POWERCTR_CP_SEL_0 0x00000bba + +#define REG_A5XX_CP_POWERCTR_CP_SEL_1 0x00000bbb + +#define REG_A5XX_CP_POWERCTR_CP_SEL_2 0x00000bbc + +#define REG_A5XX_CP_POWERCTR_CP_SEL_3 0x00000bbd + +#define REG_A5XX_RBBM_CFG_DBGBUS_SEL_A 0x00000004 +#define A5XX_RBBM_CFG_DBGBUS_SEL_A_PING_INDEX__MASK 0x000000ff +#define A5XX_RBBM_CFG_DBGBUS_SEL_A_PING_INDEX__SHIFT 0 +static inline uint32_t A5XX_RBBM_CFG_DBGBUS_SEL_A_PING_INDEX(uint32_t val) +{ + return ((val) << A5XX_RBBM_CFG_DBGBUS_SEL_A_PING_INDEX__SHIFT) & A5XX_RBBM_CFG_DBGBUS_SEL_A_PING_INDEX__MASK; +} +#define A5XX_RBBM_CFG_DBGBUS_SEL_A_PING_BLK_SEL__MASK 0x0000ff00 +#define A5XX_RBBM_CFG_DBGBUS_SEL_A_PING_BLK_SEL__SHIFT 8 +static inline uint32_t A5XX_RBBM_CFG_DBGBUS_SEL_A_PING_BLK_SEL(uint32_t val) +{ + return ((val) << A5XX_RBBM_CFG_DBGBUS_SEL_A_PING_BLK_SEL__SHIFT) & A5XX_RBBM_CFG_DBGBUS_SEL_A_PING_BLK_SEL__MASK; +} + +#define REG_A5XX_RBBM_CFG_DBGBUS_SEL_B 0x00000005 + +#define REG_A5XX_RBBM_CFG_DBGBUS_SEL_C 0x00000006 + +#define REG_A5XX_RBBM_CFG_DBGBUS_SEL_D 0x00000007 + +#define REG_A5XX_RBBM_CFG_DBGBUS_CNTLT 0x00000008 + +#define REG_A5XX_RBBM_CFG_DBGBUS_CNTLM 0x00000009 +#define A5XX_RBBM_CFG_DBGBUS_CNTLM_ENABLE__MASK 0x0f000000 +#define A5XX_RBBM_CFG_DBGBUS_CNTLM_ENABLE__SHIFT 24 +static inline uint32_t A5XX_RBBM_CFG_DBGBUS_CNTLM_ENABLE(uint32_t val) +{ + return ((val) << A5XX_RBBM_CFG_DBGBUS_CNTLM_ENABLE__SHIFT) & A5XX_RBBM_CFG_DBGBUS_CNTLM_ENABLE__MASK; +} + +#define REG_A5XX_RBBM_CFG_DEBBUS_CTLTM_ENABLE_SHIFT 0x00000018 + +#define REG_A5XX_RBBM_CFG_DBGBUS_OPL 0x0000000a + +#define REG_A5XX_RBBM_CFG_DBGBUS_OPE 0x0000000b + +#define REG_A5XX_RBBM_CFG_DBGBUS_IVTL_0 0x0000000c + +#define REG_A5XX_RBBM_CFG_DBGBUS_IVTL_1 0x0000000d + +#define REG_A5XX_RBBM_CFG_DBGBUS_IVTL_2 0x0000000e + +#define REG_A5XX_RBBM_CFG_DBGBUS_IVTL_3 0x0000000f + +#define REG_A5XX_RBBM_CFG_DBGBUS_MASKL_0 0x00000010 + +#define REG_A5XX_RBBM_CFG_DBGBUS_MASKL_1 0x00000011 + +#define REG_A5XX_RBBM_CFG_DBGBUS_MASKL_2 0x00000012 + +#define REG_A5XX_RBBM_CFG_DBGBUS_MASKL_3 0x00000013 + +#define REG_A5XX_RBBM_CFG_DBGBUS_BYTEL_0 0x00000014 + +#define REG_A5XX_RBBM_CFG_DBGBUS_BYTEL_1 0x00000015 + +#define REG_A5XX_RBBM_CFG_DBGBUS_IVTE_0 0x00000016 + +#define REG_A5XX_RBBM_CFG_DBGBUS_IVTE_1 0x00000017 + +#define REG_A5XX_RBBM_CFG_DBGBUS_IVTE_2 0x00000018 + +#define REG_A5XX_RBBM_CFG_DBGBUS_IVTE_3 0x00000019 + +#define REG_A5XX_RBBM_CFG_DBGBUS_MASKE_0 0x0000001a + +#define REG_A5XX_RBBM_CFG_DBGBUS_MASKE_1 0x0000001b + +#define REG_A5XX_RBBM_CFG_DBGBUS_MASKE_2 0x0000001c + +#define REG_A5XX_RBBM_CFG_DBGBUS_MASKE_3 0x0000001d + +#define REG_A5XX_RBBM_CFG_DBGBUS_NIBBLEE 0x0000001e + +#define REG_A5XX_RBBM_CFG_DBGBUS_PTRC0 0x0000001f + +#define REG_A5XX_RBBM_CFG_DBGBUS_PTRC1 0x00000020 + +#define REG_A5XX_RBBM_CFG_DBGBUS_LOADREG 0x00000021 + +#define REG_A5XX_RBBM_CFG_DBGBUS_IDX 0x00000022 + +#define REG_A5XX_RBBM_CFG_DBGBUS_CLRC 0x00000023 + +#define REG_A5XX_RBBM_CFG_DBGBUS_LOADIVT 0x00000024 + +#define REG_A5XX_RBBM_INTERFACE_HANG_INT_CNTL 0x0000002f + +#define REG_A5XX_RBBM_INT_CLEAR_CMD 0x00000037 + +#define REG_A5XX_RBBM_INT_0_MASK 0x00000038 +#define A5XX_RBBM_INT_0_MASK_RBBM_GPU_IDLE 0x00000001 +#define A5XX_RBBM_INT_0_MASK_RBBM_AHB_ERROR 0x00000002 +#define A5XX_RBBM_INT_0_MASK_RBBM_TRANSFER_TIMEOUT 0x00000004 +#define A5XX_RBBM_INT_0_MASK_RBBM_ME_MS_TIMEOUT 0x00000008 +#define A5XX_RBBM_INT_0_MASK_RBBM_PFP_MS_TIMEOUT 0x00000010 +#define A5XX_RBBM_INT_0_MASK_RBBM_ETS_MS_TIMEOUT 0x00000020 +#define A5XX_RBBM_INT_0_MASK_RBBM_ATB_ASYNC_OVERFLOW 0x00000040 +#define A5XX_RBBM_INT_0_MASK_RBBM_GPC_ERROR 0x00000080 +#define A5XX_RBBM_INT_0_MASK_CP_SW 0x00000100 +#define A5XX_RBBM_INT_0_MASK_CP_HW_ERROR 0x00000200 +#define A5XX_RBBM_INT_0_MASK_CP_CCU_FLUSH_DEPTH_TS 0x00000400 +#define A5XX_RBBM_INT_0_MASK_CP_CCU_FLUSH_COLOR_TS 0x00000800 +#define A5XX_RBBM_INT_0_MASK_CP_CCU_RESOLVE_TS 0x00001000 +#define A5XX_RBBM_INT_0_MASK_CP_IB2 0x00002000 +#define A5XX_RBBM_INT_0_MASK_CP_IB1 0x00004000 +#define A5XX_RBBM_INT_0_MASK_CP_RB 0x00008000 +#define A5XX_RBBM_INT_0_MASK_CP_RB_DONE_TS 0x00020000 +#define A5XX_RBBM_INT_0_MASK_CP_WT_DONE_TS 0x00040000 +#define A5XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS 0x00100000 +#define A5XX_RBBM_INT_0_MASK_RBBM_ATB_BUS_OVERFLOW 0x00400000 +#define A5XX_RBBM_INT_0_MASK_MISC_HANG_DETECT 0x00800000 +#define A5XX_RBBM_INT_0_MASK_UCHE_OOB_ACCESS 0x01000000 +#define A5XX_RBBM_INT_0_MASK_UCHE_TRAP_INTR 0x02000000 +#define A5XX_RBBM_INT_0_MASK_DEBBUS_INTR_0 0x04000000 +#define A5XX_RBBM_INT_0_MASK_DEBBUS_INTR_1 0x08000000 +#define A5XX_RBBM_INT_0_MASK_GPMU_VOLTAGE_DROOP 0x10000000 +#define A5XX_RBBM_INT_0_MASK_GPMU_FIRMWARE 0x20000000 +#define A5XX_RBBM_INT_0_MASK_ISDB_CPU_IRQ 0x40000000 +#define A5XX_RBBM_INT_0_MASK_ISDB_UNDER_DEBUG 0x80000000 + +#define REG_A5XX_RBBM_AHB_DBG_CNTL 0x0000003f + +#define REG_A5XX_RBBM_EXT_VBIF_DBG_CNTL 0x00000041 + +#define REG_A5XX_RBBM_SW_RESET_CMD 0x00000043 + +#define REG_A5XX_RBBM_BLOCK_SW_RESET_CMD 0x00000045 + +#define REG_A5XX_RBBM_BLOCK_SW_RESET_CMD2 0x00000046 + +#define REG_A5XX_RBBM_DBG_LO_HI_GPIO 0x00000048 + +#define REG_A5XX_RBBM_EXT_TRACE_BUS_CNTL 0x00000049 + +#define REG_A5XX_RBBM_CLOCK_CNTL_TP0 0x0000004a + +#define REG_A5XX_RBBM_CLOCK_CNTL_TP1 0x0000004b + +#define REG_A5XX_RBBM_CLOCK_CNTL_TP2 0x0000004c + +#define REG_A5XX_RBBM_CLOCK_CNTL_TP3 0x0000004d + +#define REG_A5XX_RBBM_CLOCK_CNTL2_TP0 0x0000004e + +#define REG_A5XX_RBBM_CLOCK_CNTL2_TP1 0x0000004f + +#define REG_A5XX_RBBM_CLOCK_CNTL2_TP2 0x00000050 + +#define REG_A5XX_RBBM_CLOCK_CNTL2_TP3 0x00000051 + +#define REG_A5XX_RBBM_CLOCK_CNTL3_TP0 0x00000052 + +#define REG_A5XX_RBBM_CLOCK_CNTL3_TP1 0x00000053 + +#define REG_A5XX_RBBM_CLOCK_CNTL3_TP2 0x00000054 + +#define REG_A5XX_RBBM_CLOCK_CNTL3_TP3 0x00000055 + +#define REG_A5XX_RBBM_READ_AHB_THROUGH_DBG 0x00000059 + +#define REG_A5XX_RBBM_CLOCK_CNTL_UCHE 0x0000005a + +#define REG_A5XX_RBBM_CLOCK_CNTL2_UCHE 0x0000005b + +#define REG_A5XX_RBBM_CLOCK_CNTL3_UCHE 0x0000005c + +#define REG_A5XX_RBBM_CLOCK_CNTL4_UCHE 0x0000005d + +#define REG_A5XX_RBBM_CLOCK_HYST_UCHE 0x0000005e + +#define REG_A5XX_RBBM_CLOCK_DELAY_UCHE 0x0000005f + +#define REG_A5XX_RBBM_CLOCK_MODE_GPC 0x00000060 + +#define REG_A5XX_RBBM_CLOCK_DELAY_GPC 0x00000061 + +#define REG_A5XX_RBBM_CLOCK_HYST_GPC 0x00000062 + +#define REG_A5XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM 0x00000063 + +#define REG_A5XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM 0x00000064 + +#define REG_A5XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM 0x00000065 + +#define REG_A5XX_RBBM_CLOCK_DELAY_HLSQ 0x00000066 + +#define REG_A5XX_RBBM_CLOCK_CNTL 0x00000067 + +#define REG_A5XX_RBBM_CLOCK_CNTL_SP0 0x00000068 + +#define REG_A5XX_RBBM_CLOCK_CNTL_SP1 0x00000069 + +#define REG_A5XX_RBBM_CLOCK_CNTL_SP2 0x0000006a + +#define REG_A5XX_RBBM_CLOCK_CNTL_SP3 0x0000006b + +#define REG_A5XX_RBBM_CLOCK_CNTL2_SP0 0x0000006c + +#define REG_A5XX_RBBM_CLOCK_CNTL2_SP1 0x0000006d + +#define REG_A5XX_RBBM_CLOCK_CNTL2_SP2 0x0000006e + +#define REG_A5XX_RBBM_CLOCK_CNTL2_SP3 0x0000006f + +#define REG_A5XX_RBBM_CLOCK_HYST_SP0 0x00000070 + +#define REG_A5XX_RBBM_CLOCK_HYST_SP1 0x00000071 + +#define REG_A5XX_RBBM_CLOCK_HYST_SP2 0x00000072 + +#define REG_A5XX_RBBM_CLOCK_HYST_SP3 0x00000073 + +#define REG_A5XX_RBBM_CLOCK_DELAY_SP0 0x00000074 + +#define REG_A5XX_RBBM_CLOCK_DELAY_SP1 0x00000075 + +#define REG_A5XX_RBBM_CLOCK_DELAY_SP2 0x00000076 + +#define REG_A5XX_RBBM_CLOCK_DELAY_SP3 0x00000077 + +#define REG_A5XX_RBBM_CLOCK_CNTL_RB0 0x00000078 + +#define REG_A5XX_RBBM_CLOCK_CNTL_RB1 0x00000079 + +#define REG_A5XX_RBBM_CLOCK_CNTL_RB2 0x0000007a + +#define REG_A5XX_RBBM_CLOCK_CNTL_RB3 0x0000007b + +#define REG_A5XX_RBBM_CLOCK_CNTL2_RB0 0x0000007c + +#define REG_A5XX_RBBM_CLOCK_CNTL2_RB1 0x0000007d + +#define REG_A5XX_RBBM_CLOCK_CNTL2_RB2 0x0000007e + +#define REG_A5XX_RBBM_CLOCK_CNTL2_RB3 0x0000007f + +#define REG_A5XX_RBBM_CLOCK_HYST_RAC 0x00000080 + +#define REG_A5XX_RBBM_CLOCK_DELAY_RAC 0x00000081 + +#define REG_A5XX_RBBM_CLOCK_CNTL_CCU0 0x00000082 + +#define REG_A5XX_RBBM_CLOCK_CNTL_CCU1 0x00000083 + +#define REG_A5XX_RBBM_CLOCK_CNTL_CCU2 0x00000084 + +#define REG_A5XX_RBBM_CLOCK_CNTL_CCU3 0x00000085 + +#define REG_A5XX_RBBM_CLOCK_HYST_RB_CCU0 0x00000086 + +#define REG_A5XX_RBBM_CLOCK_HYST_RB_CCU1 0x00000087 + +#define REG_A5XX_RBBM_CLOCK_HYST_RB_CCU2 0x00000088 + +#define REG_A5XX_RBBM_CLOCK_HYST_RB_CCU3 0x00000089 + +#define REG_A5XX_RBBM_CLOCK_CNTL_RAC 0x0000008a + +#define REG_A5XX_RBBM_CLOCK_CNTL2_RAC 0x0000008b + +#define REG_A5XX_RBBM_CLOCK_DELAY_RB_CCU_L1_0 0x0000008c + +#define REG_A5XX_RBBM_CLOCK_DELAY_RB_CCU_L1_1 0x0000008d + +#define REG_A5XX_RBBM_CLOCK_DELAY_RB_CCU_L1_2 0x0000008e + +#define REG_A5XX_RBBM_CLOCK_DELAY_RB_CCU_L1_3 0x0000008f + +#define REG_A5XX_RBBM_CLOCK_HYST_VFD 0x00000090 + +#define REG_A5XX_RBBM_CLOCK_MODE_VFD 0x00000091 + +#define REG_A5XX_RBBM_CLOCK_DELAY_VFD 0x00000092 + +#define REG_A5XX_RBBM_AHB_CNTL0 0x00000093 + +#define REG_A5XX_RBBM_AHB_CNTL1 0x00000094 + +#define REG_A5XX_RBBM_AHB_CNTL2 0x00000095 + +#define REG_A5XX_RBBM_AHB_CMD 0x00000096 + +#define REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL11 0x0000009c + +#define REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL12 0x0000009d + +#define REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL13 0x0000009e + +#define REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL14 0x0000009f + +#define REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL15 0x000000a0 + +#define REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL16 0x000000a1 + +#define REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL17 0x000000a2 + +#define REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL18 0x000000a3 + +#define REG_A5XX_RBBM_CLOCK_DELAY_TP0 0x000000a4 + +#define REG_A5XX_RBBM_CLOCK_DELAY_TP1 0x000000a5 + +#define REG_A5XX_RBBM_CLOCK_DELAY_TP2 0x000000a6 + +#define REG_A5XX_RBBM_CLOCK_DELAY_TP3 0x000000a7 + +#define REG_A5XX_RBBM_CLOCK_DELAY2_TP0 0x000000a8 + +#define REG_A5XX_RBBM_CLOCK_DELAY2_TP1 0x000000a9 + +#define REG_A5XX_RBBM_CLOCK_DELAY2_TP2 0x000000aa + +#define REG_A5XX_RBBM_CLOCK_DELAY2_TP3 0x000000ab + +#define REG_A5XX_RBBM_CLOCK_DELAY3_TP0 0x000000ac + +#define REG_A5XX_RBBM_CLOCK_DELAY3_TP1 0x000000ad + +#define REG_A5XX_RBBM_CLOCK_DELAY3_TP2 0x000000ae + +#define REG_A5XX_RBBM_CLOCK_DELAY3_TP3 0x000000af + +#define REG_A5XX_RBBM_CLOCK_HYST_TP0 0x000000b0 + +#define REG_A5XX_RBBM_CLOCK_HYST_TP1 0x000000b1 + +#define REG_A5XX_RBBM_CLOCK_HYST_TP2 0x000000b2 + +#define REG_A5XX_RBBM_CLOCK_HYST_TP3 0x000000b3 + +#define REG_A5XX_RBBM_CLOCK_HYST2_TP0 0x000000b4 + +#define REG_A5XX_RBBM_CLOCK_HYST2_TP1 0x000000b5 + +#define REG_A5XX_RBBM_CLOCK_HYST2_TP2 0x000000b6 + +#define REG_A5XX_RBBM_CLOCK_HYST2_TP3 0x000000b7 + +#define REG_A5XX_RBBM_CLOCK_HYST3_TP0 0x000000b8 + +#define REG_A5XX_RBBM_CLOCK_HYST3_TP1 0x000000b9 + +#define REG_A5XX_RBBM_CLOCK_HYST3_TP2 0x000000ba + +#define REG_A5XX_RBBM_CLOCK_HYST3_TP3 0x000000bb + +#define REG_A5XX_RBBM_CLOCK_CNTL_GPMU 0x000000c8 + +#define REG_A5XX_RBBM_CLOCK_DELAY_GPMU 0x000000c9 + +#define REG_A5XX_RBBM_CLOCK_HYST_GPMU 0x000000ca + +#define REG_A5XX_RBBM_PERFCTR_CP_0_LO 0x000003a0 + +#define REG_A5XX_RBBM_PERFCTR_CP_0_HI 0x000003a1 + +#define REG_A5XX_RBBM_PERFCTR_CP_1_LO 0x000003a2 + +#define REG_A5XX_RBBM_PERFCTR_CP_1_HI 0x000003a3 + +#define REG_A5XX_RBBM_PERFCTR_CP_2_LO 0x000003a4 + +#define REG_A5XX_RBBM_PERFCTR_CP_2_HI 0x000003a5 + +#define REG_A5XX_RBBM_PERFCTR_CP_3_LO 0x000003a6 + +#define REG_A5XX_RBBM_PERFCTR_CP_3_HI 0x000003a7 + +#define REG_A5XX_RBBM_PERFCTR_CP_4_LO 0x000003a8 + +#define REG_A5XX_RBBM_PERFCTR_CP_4_HI 0x000003a9 + +#define REG_A5XX_RBBM_PERFCTR_CP_5_LO 0x000003aa + +#define REG_A5XX_RBBM_PERFCTR_CP_5_HI 0x000003ab + +#define REG_A5XX_RBBM_PERFCTR_CP_6_LO 0x000003ac + +#define REG_A5XX_RBBM_PERFCTR_CP_6_HI 0x000003ad + +#define REG_A5XX_RBBM_PERFCTR_CP_7_LO 0x000003ae + +#define REG_A5XX_RBBM_PERFCTR_CP_7_HI 0x000003af + +#define REG_A5XX_RBBM_PERFCTR_RBBM_0_LO 0x000003b0 + +#define REG_A5XX_RBBM_PERFCTR_RBBM_0_HI 0x000003b1 + +#define REG_A5XX_RBBM_PERFCTR_RBBM_1_LO 0x000003b2 + +#define REG_A5XX_RBBM_PERFCTR_RBBM_1_HI 0x000003b3 + +#define REG_A5XX_RBBM_PERFCTR_RBBM_2_LO 0x000003b4 + +#define REG_A5XX_RBBM_PERFCTR_RBBM_2_HI 0x000003b5 + +#define REG_A5XX_RBBM_PERFCTR_RBBM_3_LO 0x000003b6 + +#define REG_A5XX_RBBM_PERFCTR_RBBM_3_HI 0x000003b7 + +#define REG_A5XX_RBBM_PERFCTR_PC_0_LO 0x000003b8 + +#define REG_A5XX_RBBM_PERFCTR_PC_0_HI 0x000003b9 + +#define REG_A5XX_RBBM_PERFCTR_PC_1_LO 0x000003ba + +#define REG_A5XX_RBBM_PERFCTR_PC_1_HI 0x000003bb + +#define REG_A5XX_RBBM_PERFCTR_PC_2_LO 0x000003bc + +#define REG_A5XX_RBBM_PERFCTR_PC_2_HI 0x000003bd + +#define REG_A5XX_RBBM_PERFCTR_PC_3_LO 0x000003be + +#define REG_A5XX_RBBM_PERFCTR_PC_3_HI 0x000003bf + +#define REG_A5XX_RBBM_PERFCTR_PC_4_LO 0x000003c0 + +#define REG_A5XX_RBBM_PERFCTR_PC_4_HI 0x000003c1 + +#define REG_A5XX_RBBM_PERFCTR_PC_5_LO 0x000003c2 + +#define REG_A5XX_RBBM_PERFCTR_PC_5_HI 0x000003c3 + +#define REG_A5XX_RBBM_PERFCTR_PC_6_LO 0x000003c4 + +#define REG_A5XX_RBBM_PERFCTR_PC_6_HI 0x000003c5 + +#define REG_A5XX_RBBM_PERFCTR_PC_7_LO 0x000003c6 + +#define REG_A5XX_RBBM_PERFCTR_PC_7_HI 0x000003c7 + +#define REG_A5XX_RBBM_PERFCTR_VFD_0_LO 0x000003c8 + +#define REG_A5XX_RBBM_PERFCTR_VFD_0_HI 0x000003c9 + +#define REG_A5XX_RBBM_PERFCTR_VFD_1_LO 0x000003ca + +#define REG_A5XX_RBBM_PERFCTR_VFD_1_HI 0x000003cb + +#define REG_A5XX_RBBM_PERFCTR_VFD_2_LO 0x000003cc + +#define REG_A5XX_RBBM_PERFCTR_VFD_2_HI 0x000003cd + +#define REG_A5XX_RBBM_PERFCTR_VFD_3_LO 0x000003ce + +#define REG_A5XX_RBBM_PERFCTR_VFD_3_HI 0x000003cf + +#define REG_A5XX_RBBM_PERFCTR_VFD_4_LO 0x000003d0 + +#define REG_A5XX_RBBM_PERFCTR_VFD_4_HI 0x000003d1 + +#define REG_A5XX_RBBM_PERFCTR_VFD_5_LO 0x000003d2 + +#define REG_A5XX_RBBM_PERFCTR_VFD_5_HI 0x000003d3 + +#define REG_A5XX_RBBM_PERFCTR_VFD_6_LO 0x000003d4 + +#define REG_A5XX_RBBM_PERFCTR_VFD_6_HI 0x000003d5 + +#define REG_A5XX_RBBM_PERFCTR_VFD_7_LO 0x000003d6 + +#define REG_A5XX_RBBM_PERFCTR_VFD_7_HI 0x000003d7 + +#define REG_A5XX_RBBM_PERFCTR_HLSQ_0_LO 0x000003d8 + +#define REG_A5XX_RBBM_PERFCTR_HLSQ_0_HI 0x000003d9 + +#define REG_A5XX_RBBM_PERFCTR_HLSQ_1_LO 0x000003da + +#define REG_A5XX_RBBM_PERFCTR_HLSQ_1_HI 0x000003db + +#define REG_A5XX_RBBM_PERFCTR_HLSQ_2_LO 0x000003dc + +#define REG_A5XX_RBBM_PERFCTR_HLSQ_2_HI 0x000003dd + +#define REG_A5XX_RBBM_PERFCTR_HLSQ_3_LO 0x000003de + +#define REG_A5XX_RBBM_PERFCTR_HLSQ_3_HI 0x000003df + +#define REG_A5XX_RBBM_PERFCTR_HLSQ_4_LO 0x000003e0 + +#define REG_A5XX_RBBM_PERFCTR_HLSQ_4_HI 0x000003e1 + +#define REG_A5XX_RBBM_PERFCTR_HLSQ_5_LO 0x000003e2 + +#define REG_A5XX_RBBM_PERFCTR_HLSQ_5_HI 0x000003e3 + +#define REG_A5XX_RBBM_PERFCTR_HLSQ_6_LO 0x000003e4 + +#define REG_A5XX_RBBM_PERFCTR_HLSQ_6_HI 0x000003e5 + +#define REG_A5XX_RBBM_PERFCTR_HLSQ_7_LO 0x000003e6 + +#define REG_A5XX_RBBM_PERFCTR_HLSQ_7_HI 0x000003e7 + +#define REG_A5XX_RBBM_PERFCTR_VPC_0_LO 0x000003e8 + +#define REG_A5XX_RBBM_PERFCTR_VPC_0_HI 0x000003e9 + +#define REG_A5XX_RBBM_PERFCTR_VPC_1_LO 0x000003ea + +#define REG_A5XX_RBBM_PERFCTR_VPC_1_HI 0x000003eb + +#define REG_A5XX_RBBM_PERFCTR_VPC_2_LO 0x000003ec + +#define REG_A5XX_RBBM_PERFCTR_VPC_2_HI 0x000003ed + +#define REG_A5XX_RBBM_PERFCTR_VPC_3_LO 0x000003ee + +#define REG_A5XX_RBBM_PERFCTR_VPC_3_HI 0x000003ef + +#define REG_A5XX_RBBM_PERFCTR_CCU_0_LO 0x000003f0 + +#define REG_A5XX_RBBM_PERFCTR_CCU_0_HI 0x000003f1 + +#define REG_A5XX_RBBM_PERFCTR_CCU_1_LO 0x000003f2 + +#define REG_A5XX_RBBM_PERFCTR_CCU_1_HI 0x000003f3 + +#define REG_A5XX_RBBM_PERFCTR_CCU_2_LO 0x000003f4 + +#define REG_A5XX_RBBM_PERFCTR_CCU_2_HI 0x000003f5 + +#define REG_A5XX_RBBM_PERFCTR_CCU_3_LO 0x000003f6 + +#define REG_A5XX_RBBM_PERFCTR_CCU_3_HI 0x000003f7 + +#define REG_A5XX_RBBM_PERFCTR_TSE_0_LO 0x000003f8 + +#define REG_A5XX_RBBM_PERFCTR_TSE_0_HI 0x000003f9 + +#define REG_A5XX_RBBM_PERFCTR_TSE_1_LO 0x000003fa + +#define REG_A5XX_RBBM_PERFCTR_TSE_1_HI 0x000003fb + +#define REG_A5XX_RBBM_PERFCTR_TSE_2_LO 0x000003fc + +#define REG_A5XX_RBBM_PERFCTR_TSE_2_HI 0x000003fd + +#define REG_A5XX_RBBM_PERFCTR_TSE_3_LO 0x000003fe + +#define REG_A5XX_RBBM_PERFCTR_TSE_3_HI 0x000003ff + +#define REG_A5XX_RBBM_PERFCTR_RAS_0_LO 0x00000400 + +#define REG_A5XX_RBBM_PERFCTR_RAS_0_HI 0x00000401 + +#define REG_A5XX_RBBM_PERFCTR_RAS_1_LO 0x00000402 + +#define REG_A5XX_RBBM_PERFCTR_RAS_1_HI 0x00000403 + +#define REG_A5XX_RBBM_PERFCTR_RAS_2_LO 0x00000404 + +#define REG_A5XX_RBBM_PERFCTR_RAS_2_HI 0x00000405 + +#define REG_A5XX_RBBM_PERFCTR_RAS_3_LO 0x00000406 + +#define REG_A5XX_RBBM_PERFCTR_RAS_3_HI 0x00000407 + +#define REG_A5XX_RBBM_PERFCTR_UCHE_0_LO 0x00000408 + +#define REG_A5XX_RBBM_PERFCTR_UCHE_0_HI 0x00000409 + +#define REG_A5XX_RBBM_PERFCTR_UCHE_1_LO 0x0000040a + +#define REG_A5XX_RBBM_PERFCTR_UCHE_1_HI 0x0000040b + +#define REG_A5XX_RBBM_PERFCTR_UCHE_2_LO 0x0000040c + +#define REG_A5XX_RBBM_PERFCTR_UCHE_2_HI 0x0000040d + +#define REG_A5XX_RBBM_PERFCTR_UCHE_3_LO 0x0000040e + +#define REG_A5XX_RBBM_PERFCTR_UCHE_3_HI 0x0000040f + +#define REG_A5XX_RBBM_PERFCTR_UCHE_4_LO 0x00000410 + +#define REG_A5XX_RBBM_PERFCTR_UCHE_4_HI 0x00000411 + +#define REG_A5XX_RBBM_PERFCTR_UCHE_5_LO 0x00000412 + +#define REG_A5XX_RBBM_PERFCTR_UCHE_5_HI 0x00000413 + +#define REG_A5XX_RBBM_PERFCTR_UCHE_6_LO 0x00000414 + +#define REG_A5XX_RBBM_PERFCTR_UCHE_6_HI 0x00000415 + +#define REG_A5XX_RBBM_PERFCTR_UCHE_7_LO 0x00000416 + +#define REG_A5XX_RBBM_PERFCTR_UCHE_7_HI 0x00000417 + +#define REG_A5XX_RBBM_PERFCTR_TP_0_LO 0x00000418 + +#define REG_A5XX_RBBM_PERFCTR_TP_0_HI 0x00000419 + +#define REG_A5XX_RBBM_PERFCTR_TP_1_LO 0x0000041a + +#define REG_A5XX_RBBM_PERFCTR_TP_1_HI 0x0000041b + +#define REG_A5XX_RBBM_PERFCTR_TP_2_LO 0x0000041c + +#define REG_A5XX_RBBM_PERFCTR_TP_2_HI 0x0000041d + +#define REG_A5XX_RBBM_PERFCTR_TP_3_LO 0x0000041e + +#define REG_A5XX_RBBM_PERFCTR_TP_3_HI 0x0000041f + +#define REG_A5XX_RBBM_PERFCTR_TP_4_LO 0x00000420 + +#define REG_A5XX_RBBM_PERFCTR_TP_4_HI 0x00000421 + +#define REG_A5XX_RBBM_PERFCTR_TP_5_LO 0x00000422 + +#define REG_A5XX_RBBM_PERFCTR_TP_5_HI 0x00000423 + +#define REG_A5XX_RBBM_PERFCTR_TP_6_LO 0x00000424 + +#define REG_A5XX_RBBM_PERFCTR_TP_6_HI 0x00000425 + +#define REG_A5XX_RBBM_PERFCTR_TP_7_LO 0x00000426 + +#define REG_A5XX_RBBM_PERFCTR_TP_7_HI 0x00000427 + +#define REG_A5XX_RBBM_PERFCTR_SP_0_LO 0x00000428 + +#define REG_A5XX_RBBM_PERFCTR_SP_0_HI 0x00000429 + +#define REG_A5XX_RBBM_PERFCTR_SP_1_LO 0x0000042a + +#define REG_A5XX_RBBM_PERFCTR_SP_1_HI 0x0000042b + +#define REG_A5XX_RBBM_PERFCTR_SP_2_LO 0x0000042c + +#define REG_A5XX_RBBM_PERFCTR_SP_2_HI 0x0000042d + +#define REG_A5XX_RBBM_PERFCTR_SP_3_LO 0x0000042e + +#define REG_A5XX_RBBM_PERFCTR_SP_3_HI 0x0000042f + +#define REG_A5XX_RBBM_PERFCTR_SP_4_LO 0x00000430 + +#define REG_A5XX_RBBM_PERFCTR_SP_4_HI 0x00000431 + +#define REG_A5XX_RBBM_PERFCTR_SP_5_LO 0x00000432 + +#define REG_A5XX_RBBM_PERFCTR_SP_5_HI 0x00000433 + +#define REG_A5XX_RBBM_PERFCTR_SP_6_LO 0x00000434 + +#define REG_A5XX_RBBM_PERFCTR_SP_6_HI 0x00000435 + +#define REG_A5XX_RBBM_PERFCTR_SP_7_LO 0x00000436 + +#define REG_A5XX_RBBM_PERFCTR_SP_7_HI 0x00000437 + +#define REG_A5XX_RBBM_PERFCTR_SP_8_LO 0x00000438 + +#define REG_A5XX_RBBM_PERFCTR_SP_8_HI 0x00000439 + +#define REG_A5XX_RBBM_PERFCTR_SP_9_LO 0x0000043a + +#define REG_A5XX_RBBM_PERFCTR_SP_9_HI 0x0000043b + +#define REG_A5XX_RBBM_PERFCTR_SP_10_LO 0x0000043c + +#define REG_A5XX_RBBM_PERFCTR_SP_10_HI 0x0000043d + +#define REG_A5XX_RBBM_PERFCTR_SP_11_LO 0x0000043e + +#define REG_A5XX_RBBM_PERFCTR_SP_11_HI 0x0000043f + +#define REG_A5XX_RBBM_PERFCTR_RB_0_LO 0x00000440 + +#define REG_A5XX_RBBM_PERFCTR_RB_0_HI 0x00000441 + +#define REG_A5XX_RBBM_PERFCTR_RB_1_LO 0x00000442 + +#define REG_A5XX_RBBM_PERFCTR_RB_1_HI 0x00000443 + +#define REG_A5XX_RBBM_PERFCTR_RB_2_LO 0x00000444 + +#define REG_A5XX_RBBM_PERFCTR_RB_2_HI 0x00000445 + +#define REG_A5XX_RBBM_PERFCTR_RB_3_LO 0x00000446 + +#define REG_A5XX_RBBM_PERFCTR_RB_3_HI 0x00000447 + +#define REG_A5XX_RBBM_PERFCTR_RB_4_LO 0x00000448 + +#define REG_A5XX_RBBM_PERFCTR_RB_4_HI 0x00000449 + +#define REG_A5XX_RBBM_PERFCTR_RB_5_LO 0x0000044a + +#define REG_A5XX_RBBM_PERFCTR_RB_5_HI 0x0000044b + +#define REG_A5XX_RBBM_PERFCTR_RB_6_LO 0x0000044c + +#define REG_A5XX_RBBM_PERFCTR_RB_6_HI 0x0000044d + +#define REG_A5XX_RBBM_PERFCTR_RB_7_LO 0x0000044e + +#define REG_A5XX_RBBM_PERFCTR_RB_7_HI 0x0000044f + +#define REG_A5XX_RBBM_PERFCTR_VSC_0_LO 0x00000450 + +#define REG_A5XX_RBBM_PERFCTR_VSC_0_HI 0x00000451 + +#define REG_A5XX_RBBM_PERFCTR_VSC_1_LO 0x00000452 + +#define REG_A5XX_RBBM_PERFCTR_VSC_1_HI 0x00000453 + +#define REG_A5XX_RBBM_PERFCTR_LRZ_0_LO 0x00000454 + +#define REG_A5XX_RBBM_PERFCTR_LRZ_0_HI 0x00000455 + +#define REG_A5XX_RBBM_PERFCTR_LRZ_1_LO 0x00000456 + +#define REG_A5XX_RBBM_PERFCTR_LRZ_1_HI 0x00000457 + +#define REG_A5XX_RBBM_PERFCTR_LRZ_2_LO 0x00000458 + +#define REG_A5XX_RBBM_PERFCTR_LRZ_2_HI 0x00000459 + +#define REG_A5XX_RBBM_PERFCTR_LRZ_3_LO 0x0000045a + +#define REG_A5XX_RBBM_PERFCTR_LRZ_3_HI 0x0000045b + +#define REG_A5XX_RBBM_PERFCTR_CMP_0_LO 0x0000045c + +#define REG_A5XX_RBBM_PERFCTR_CMP_0_HI 0x0000045d + +#define REG_A5XX_RBBM_PERFCTR_CMP_1_LO 0x0000045e + +#define REG_A5XX_RBBM_PERFCTR_CMP_1_HI 0x0000045f + +#define REG_A5XX_RBBM_PERFCTR_CMP_2_LO 0x00000460 + +#define REG_A5XX_RBBM_PERFCTR_CMP_2_HI 0x00000461 + +#define REG_A5XX_RBBM_PERFCTR_CMP_3_LO 0x00000462 + +#define REG_A5XX_RBBM_PERFCTR_CMP_3_HI 0x00000463 + +#define REG_A5XX_RBBM_PERFCTR_RBBM_SEL_0 0x0000046b + +#define REG_A5XX_RBBM_PERFCTR_RBBM_SEL_1 0x0000046c + +#define REG_A5XX_RBBM_PERFCTR_RBBM_SEL_2 0x0000046d + +#define REG_A5XX_RBBM_PERFCTR_RBBM_SEL_3 0x0000046e + +#define REG_A5XX_RBBM_ALWAYSON_COUNTER_LO 0x000004d2 + +#define REG_A5XX_RBBM_ALWAYSON_COUNTER_HI 0x000004d3 + +#define REG_A5XX_RBBM_STATUS 0x000004f5 +#define A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB 0x80000000 +#define A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB_CP 0x40000000 +#define A5XX_RBBM_STATUS_HLSQ_BUSY 0x20000000 +#define A5XX_RBBM_STATUS_VSC_BUSY 0x10000000 +#define A5XX_RBBM_STATUS_TPL1_BUSY 0x08000000 +#define A5XX_RBBM_STATUS_SP_BUSY 0x04000000 +#define A5XX_RBBM_STATUS_UCHE_BUSY 0x02000000 +#define A5XX_RBBM_STATUS_VPC_BUSY 0x01000000 +#define A5XX_RBBM_STATUS_VFDP_BUSY 0x00800000 +#define A5XX_RBBM_STATUS_VFD_BUSY 0x00400000 +#define A5XX_RBBM_STATUS_TESS_BUSY 0x00200000 +#define A5XX_RBBM_STATUS_PC_VSD_BUSY 0x00100000 +#define A5XX_RBBM_STATUS_PC_DCALL_BUSY 0x00080000 +#define A5XX_RBBM_STATUS_GPMU_SLAVE_BUSY 0x00040000 +#define A5XX_RBBM_STATUS_DCOM_BUSY 0x00020000 +#define A5XX_RBBM_STATUS_COM_BUSY 0x00010000 +#define A5XX_RBBM_STATUS_LRZ_BUZY 0x00008000 +#define A5XX_RBBM_STATUS_A2D_DSP_BUSY 0x00004000 +#define A5XX_RBBM_STATUS_CCUFCHE_BUSY 0x00002000 +#define A5XX_RBBM_STATUS_RB_BUSY 0x00001000 +#define A5XX_RBBM_STATUS_RAS_BUSY 0x00000800 +#define A5XX_RBBM_STATUS_TSE_BUSY 0x00000400 +#define A5XX_RBBM_STATUS_VBIF_BUSY 0x00000200 +#define A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB_HYST 0x00000100 +#define A5XX_RBBM_STATUS_CP_BUSY_IGN_HYST 0x00000080 +#define A5XX_RBBM_STATUS_CP_BUSY 0x00000040 +#define A5XX_RBBM_STATUS_GPMU_MASTER_BUSY 0x00000020 +#define A5XX_RBBM_STATUS_CP_CRASH_BUSY 0x00000010 +#define A5XX_RBBM_STATUS_CP_ETS_BUSY 0x00000008 +#define A5XX_RBBM_STATUS_CP_PFP_BUSY 0x00000004 +#define A5XX_RBBM_STATUS_CP_ME_BUSY 0x00000002 +#define A5XX_RBBM_STATUS_HI_BUSY 0x00000001 + +#define REG_A5XX_RBBM_STATUS3 0x00000530 + +#define REG_A5XX_RBBM_INT_0_STATUS 0x000004e1 + +#define REG_A5XX_RBBM_AHB_ME_SPLIT_STATUS 0x000004f0 + +#define REG_A5XX_RBBM_AHB_PFP_SPLIT_STATUS 0x000004f1 + +#define REG_A5XX_RBBM_AHB_ETS_SPLIT_STATUS 0x000004f3 + +#define REG_A5XX_RBBM_AHB_ERROR_STATUS 0x000004f4 + +#define REG_A5XX_RBBM_PERFCTR_CNTL 0x00000464 + +#define REG_A5XX_RBBM_PERFCTR_LOAD_CMD0 0x00000465 + +#define REG_A5XX_RBBM_PERFCTR_LOAD_CMD1 0x00000466 + +#define REG_A5XX_RBBM_PERFCTR_LOAD_CMD2 0x00000467 + +#define REG_A5XX_RBBM_PERFCTR_LOAD_CMD3 0x00000468 + +#define REG_A5XX_RBBM_PERFCTR_LOAD_VALUE_LO 0x00000469 + +#define REG_A5XX_RBBM_PERFCTR_LOAD_VALUE_HI 0x0000046a + +#define REG_A5XX_RBBM_PERFCTR_RBBM_SEL_0 0x0000046b + +#define REG_A5XX_RBBM_PERFCTR_RBBM_SEL_1 0x0000046c + +#define REG_A5XX_RBBM_PERFCTR_RBBM_SEL_2 0x0000046d + +#define REG_A5XX_RBBM_PERFCTR_RBBM_SEL_3 0x0000046e + +#define REG_A5XX_RBBM_PERFCTR_GPU_BUSY_MASKED 0x0000046f + +#define REG_A5XX_RBBM_CFG_DBGBUS_EVENT_LOGIC 0x00000504 + +#define REG_A5XX_RBBM_CFG_DBGBUS_OVER 0x00000505 + +#define REG_A5XX_RBBM_CFG_DBGBUS_COUNT0 0x00000506 + +#define REG_A5XX_RBBM_CFG_DBGBUS_COUNT1 0x00000507 + +#define REG_A5XX_RBBM_CFG_DBGBUS_COUNT2 0x00000508 + +#define REG_A5XX_RBBM_CFG_DBGBUS_COUNT3 0x00000509 + +#define REG_A5XX_RBBM_CFG_DBGBUS_COUNT4 0x0000050a + +#define REG_A5XX_RBBM_CFG_DBGBUS_COUNT5 0x0000050b + +#define REG_A5XX_RBBM_CFG_DBGBUS_TRACE_ADDR 0x0000050c + +#define REG_A5XX_RBBM_CFG_DBGBUS_TRACE_BUF0 0x0000050d + +#define REG_A5XX_RBBM_CFG_DBGBUS_TRACE_BUF1 0x0000050e + +#define REG_A5XX_RBBM_CFG_DBGBUS_TRACE_BUF2 0x0000050f + +#define REG_A5XX_RBBM_CFG_DBGBUS_TRACE_BUF3 0x00000510 + +#define REG_A5XX_RBBM_CFG_DBGBUS_TRACE_BUF4 0x00000511 + +#define REG_A5XX_RBBM_CFG_DBGBUS_MISR0 0x00000512 + +#define REG_A5XX_RBBM_CFG_DBGBUS_MISR1 0x00000513 + +#define REG_A5XX_RBBM_ISDB_CNT 0x00000533 + +#define REG_A5XX_RBBM_SECVID_TRUST_CONFIG 0x0000f000 + +#define REG_A5XX_RBBM_SECVID_TRUST_CNTL 0x0000f400 + +#define REG_A5XX_RBBM_SECVID_TSB_TRUSTED_BASE_LO 0x0000f800 + +#define REG_A5XX_RBBM_SECVID_TSB_TRUSTED_BASE_HI 0x0000f801 + +#define REG_A5XX_RBBM_SECVID_TSB_TRUSTED_SIZE 0x0000f802 + +#define REG_A5XX_RBBM_SECVID_TSB_CNTL 0x0000f803 + +#define REG_A5XX_RBBM_SECVID_TSB_COMP_STATUS_LO 0x0000f804 + +#define REG_A5XX_RBBM_SECVID_TSB_COMP_STATUS_HI 0x0000f805 + +#define REG_A5XX_RBBM_SECVID_TSB_UCHE_STATUS_LO 0x0000f806 + +#define REG_A5XX_RBBM_SECVID_TSB_UCHE_STATUS_HI 0x0000f807 + +#define REG_A5XX_RBBM_SECVID_TSB_ADDR_MODE_CNTL 0x0000f810 + +#define REG_A5XX_VSC_PIPE_DATA_LENGTH_0 0x00000c00 + +#define REG_A5XX_VSC_PERFCTR_VSC_SEL_0 0x00000c60 + +#define REG_A5XX_VSC_PERFCTR_VSC_SEL_1 0x00000c61 + +#define REG_A5XX_VSC_BIN_SIZE 0x00000cdd +#define A5XX_VSC_BIN_SIZE_WINDOW_OFFSET_DISABLE 0x80000000 +#define A5XX_VSC_BIN_SIZE_X__MASK 0x00007fff +#define A5XX_VSC_BIN_SIZE_X__SHIFT 0 +static inline uint32_t A5XX_VSC_BIN_SIZE_X(uint32_t val) +{ + return ((val) << A5XX_VSC_BIN_SIZE_X__SHIFT) & A5XX_VSC_BIN_SIZE_X__MASK; +} +#define A5XX_VSC_BIN_SIZE_Y__MASK 0x7fff0000 +#define A5XX_VSC_BIN_SIZE_Y__SHIFT 16 +static inline uint32_t A5XX_VSC_BIN_SIZE_Y(uint32_t val) +{ + return ((val) << A5XX_VSC_BIN_SIZE_Y__SHIFT) & A5XX_VSC_BIN_SIZE_Y__MASK; +} + +#define REG_A5XX_GRAS_ADDR_MODE_CNTL 0x00000c81 + +#define REG_A5XX_GRAS_PERFCTR_TSE_SEL_0 0x00000c90 + +#define REG_A5XX_GRAS_PERFCTR_TSE_SEL_1 0x00000c91 + +#define REG_A5XX_GRAS_PERFCTR_TSE_SEL_2 0x00000c92 + +#define REG_A5XX_GRAS_PERFCTR_TSE_SEL_3 0x00000c93 + +#define REG_A5XX_GRAS_PERFCTR_RAS_SEL_0 0x00000c94 + +#define REG_A5XX_GRAS_PERFCTR_RAS_SEL_1 0x00000c95 + +#define REG_A5XX_GRAS_PERFCTR_RAS_SEL_2 0x00000c96 + +#define REG_A5XX_GRAS_PERFCTR_RAS_SEL_3 0x00000c97 + +#define REG_A5XX_GRAS_PERFCTR_LRZ_SEL_0 0x00000c98 + +#define REG_A5XX_GRAS_PERFCTR_LRZ_SEL_1 0x00000c99 + +#define REG_A5XX_GRAS_PERFCTR_LRZ_SEL_2 0x00000c9a + +#define REG_A5XX_GRAS_PERFCTR_LRZ_SEL_3 0x00000c9b + +#define REG_A5XX_RB_DBG_ECO_CNTL 0x00000cc4 + +#define REG_A5XX_RB_ADDR_MODE_CNTL 0x00000cc5 + +#define REG_A5XX_RB_MODE_CNTL 0x00000cc6 + +#define REG_A5XX_RB_CCU_CNTL 0x00000cc7 + +#define REG_A5XX_RB_PERFCTR_RB_SEL_0 0x00000cd0 + +#define REG_A5XX_RB_PERFCTR_RB_SEL_1 0x00000cd1 + +#define REG_A5XX_RB_PERFCTR_RB_SEL_2 0x00000cd2 + +#define REG_A5XX_RB_PERFCTR_RB_SEL_3 0x00000cd3 + +#define REG_A5XX_RB_PERFCTR_RB_SEL_4 0x00000cd4 + +#define REG_A5XX_RB_PERFCTR_RB_SEL_5 0x00000cd5 + +#define REG_A5XX_RB_PERFCTR_RB_SEL_6 0x00000cd6 + +#define REG_A5XX_RB_PERFCTR_RB_SEL_7 0x00000cd7 + +#define REG_A5XX_RB_PERFCTR_CCU_SEL_0 0x00000cd8 + +#define REG_A5XX_RB_PERFCTR_CCU_SEL_1 0x00000cd9 + +#define REG_A5XX_RB_PERFCTR_CCU_SEL_2 0x00000cda + +#define REG_A5XX_RB_PERFCTR_CCU_SEL_3 0x00000cdb + +#define REG_A5XX_RB_POWERCTR_RB_SEL_0 0x00000ce0 + +#define REG_A5XX_RB_POWERCTR_RB_SEL_1 0x00000ce1 + +#define REG_A5XX_RB_POWERCTR_RB_SEL_2 0x00000ce2 + +#define REG_A5XX_RB_POWERCTR_RB_SEL_3 0x00000ce3 + +#define REG_A5XX_RB_POWERCTR_CCU_SEL_0 0x00000ce4 + +#define REG_A5XX_RB_POWERCTR_CCU_SEL_1 0x00000ce5 + +#define REG_A5XX_RB_PERFCTR_CMP_SEL_0 0x00000cec + +#define REG_A5XX_RB_PERFCTR_CMP_SEL_1 0x00000ced + +#define REG_A5XX_RB_PERFCTR_CMP_SEL_2 0x00000cee + +#define REG_A5XX_RB_PERFCTR_CMP_SEL_3 0x00000cef + +#define REG_A5XX_PC_DBG_ECO_CNTL 0x00000d00 +#define A5XX_PC_DBG_ECO_CNTL_TWOPASSUSEWFI 0x00000100 + +#define REG_A5XX_PC_ADDR_MODE_CNTL 0x00000d01 + +#define REG_A5XX_PC_MODE_CNTL 0x00000d02 + +#define REG_A5XX_UNKNOWN_0D08 0x00000d08 + +#define REG_A5XX_UNKNOWN_0D09 0x00000d09 + +#define REG_A5XX_PC_PERFCTR_PC_SEL_0 0x00000d10 + +#define REG_A5XX_PC_PERFCTR_PC_SEL_1 0x00000d11 + +#define REG_A5XX_PC_PERFCTR_PC_SEL_2 0x00000d12 + +#define REG_A5XX_PC_PERFCTR_PC_SEL_3 0x00000d13 + +#define REG_A5XX_PC_PERFCTR_PC_SEL_4 0x00000d14 + +#define REG_A5XX_PC_PERFCTR_PC_SEL_5 0x00000d15 + +#define REG_A5XX_PC_PERFCTR_PC_SEL_6 0x00000d16 + +#define REG_A5XX_PC_PERFCTR_PC_SEL_7 0x00000d17 + +#define REG_A5XX_HLSQ_TIMEOUT_THRESHOLD_0 0x00000e00 + +#define REG_A5XX_HLSQ_TIMEOUT_THRESHOLD_1 0x00000e01 + +#define REG_A5XX_HLSQ_ADDR_MODE_CNTL 0x00000e05 + +#define REG_A5XX_HLSQ_MODE_CNTL 0x00000e06 + +#define REG_A5XX_HLSQ_PERFCTR_HLSQ_SEL_0 0x00000e10 + +#define REG_A5XX_HLSQ_PERFCTR_HLSQ_SEL_1 0x00000e11 + +#define REG_A5XX_HLSQ_PERFCTR_HLSQ_SEL_2 0x00000e12 + +#define REG_A5XX_HLSQ_PERFCTR_HLSQ_SEL_3 0x00000e13 + +#define REG_A5XX_HLSQ_PERFCTR_HLSQ_SEL_4 0x00000e14 + +#define REG_A5XX_HLSQ_PERFCTR_HLSQ_SEL_5 0x00000e15 + +#define REG_A5XX_HLSQ_PERFCTR_HLSQ_SEL_6 0x00000e16 + +#define REG_A5XX_HLSQ_PERFCTR_HLSQ_SEL_7 0x00000e17 + +#define REG_A5XX_HLSQ_SPTP_RDSEL 0x00000f08 + +#define REG_A5XX_HLSQ_DBG_READ_SEL 0x0000bc00 +#define A5XX_HLSQ_DBG_READ_SEL_STATETYPE__MASK 0x0000ff00 +#define A5XX_HLSQ_DBG_READ_SEL_STATETYPE__SHIFT 8 +static inline uint32_t A5XX_HLSQ_DBG_READ_SEL_STATETYPE(uint32_t val) +{ + return ((val) << A5XX_HLSQ_DBG_READ_SEL_STATETYPE__SHIFT) & A5XX_HLSQ_DBG_READ_SEL_STATETYPE__MASK; +} + +#define REG_A5XX_HLSQ_DBG_AHB_READ_APERTURE 0x0000a000 + +#define REG_A5XX_VFD_ADDR_MODE_CNTL 0x00000e41 + +#define REG_A5XX_VFD_MODE_CNTL 0x00000e42 + +#define REG_A5XX_VFD_PERFCTR_VFD_SEL_0 0x00000e50 + +#define REG_A5XX_VFD_PERFCTR_VFD_SEL_1 0x00000e51 + +#define REG_A5XX_VFD_PERFCTR_VFD_SEL_2 0x00000e52 + +#define REG_A5XX_VFD_PERFCTR_VFD_SEL_3 0x00000e53 + +#define REG_A5XX_VFD_PERFCTR_VFD_SEL_4 0x00000e54 + +#define REG_A5XX_VFD_PERFCTR_VFD_SEL_5 0x00000e55 + +#define REG_A5XX_VFD_PERFCTR_VFD_SEL_6 0x00000e56 + +#define REG_A5XX_VFD_PERFCTR_VFD_SEL_7 0x00000e57 + +#define REG_A5XX_VPC_DBG_ECO_CNTL 0x00000e60 + +#define REG_A5XX_VPC_ADDR_MODE_CNTL 0x00000e61 + +#define REG_A5XX_VPC_MODE_CNTL 0x00000e62 + +#define REG_A5XX_VPC_PERFCTR_VPC_SEL_0 0x00000e64 + +#define REG_A5XX_VPC_PERFCTR_VPC_SEL_1 0x00000e65 + +#define REG_A5XX_VPC_PERFCTR_VPC_SEL_2 0x00000e66 + +#define REG_A5XX_VPC_PERFCTR_VPC_SEL_3 0x00000e67 + +#define REG_A5XX_UCHE_ADDR_MODE_CNTL 0x00000e80 + +#define REG_A5XX_UCHE_SVM_CNTL 0x00000e82 + +#define REG_A5XX_UCHE_WRITE_THRU_BASE_LO 0x00000e87 + +#define REG_A5XX_UCHE_WRITE_THRU_BASE_HI 0x00000e88 + +#define REG_A5XX_UCHE_TRAP_BASE_LO 0x00000e89 + +#define REG_A5XX_UCHE_TRAP_BASE_HI 0x00000e8a + +#define REG_A5XX_UCHE_GMEM_RANGE_MIN_LO 0x00000e8b + +#define REG_A5XX_UCHE_GMEM_RANGE_MIN_HI 0x00000e8c + +#define REG_A5XX_UCHE_GMEM_RANGE_MAX_LO 0x00000e8d + +#define REG_A5XX_UCHE_GMEM_RANGE_MAX_HI 0x00000e8e + +#define REG_A5XX_UCHE_DBG_ECO_CNTL_2 0x00000e8f + +#define REG_A5XX_UCHE_DBG_ECO_CNTL 0x00000e90 + +#define REG_A5XX_UCHE_CACHE_INVALIDATE_MIN_LO 0x00000e91 + +#define REG_A5XX_UCHE_CACHE_INVALIDATE_MIN_HI 0x00000e92 + +#define REG_A5XX_UCHE_CACHE_INVALIDATE_MAX_LO 0x00000e93 + +#define REG_A5XX_UCHE_CACHE_INVALIDATE_MAX_HI 0x00000e94 + +#define REG_A5XX_UCHE_CACHE_INVALIDATE 0x00000e95 + +#define REG_A5XX_UCHE_CACHE_WAYS 0x00000e96 + +#define REG_A5XX_UCHE_PERFCTR_UCHE_SEL_0 0x00000ea0 + +#define REG_A5XX_UCHE_PERFCTR_UCHE_SEL_1 0x00000ea1 + +#define REG_A5XX_UCHE_PERFCTR_UCHE_SEL_2 0x00000ea2 + +#define REG_A5XX_UCHE_PERFCTR_UCHE_SEL_3 0x00000ea3 + +#define REG_A5XX_UCHE_PERFCTR_UCHE_SEL_4 0x00000ea4 + +#define REG_A5XX_UCHE_PERFCTR_UCHE_SEL_5 0x00000ea5 + +#define REG_A5XX_UCHE_PERFCTR_UCHE_SEL_6 0x00000ea6 + +#define REG_A5XX_UCHE_PERFCTR_UCHE_SEL_7 0x00000ea7 + +#define REG_A5XX_UCHE_POWERCTR_UCHE_SEL_0 0x00000ea8 + +#define REG_A5XX_UCHE_POWERCTR_UCHE_SEL_1 0x00000ea9 + +#define REG_A5XX_UCHE_POWERCTR_UCHE_SEL_2 0x00000eaa + +#define REG_A5XX_UCHE_POWERCTR_UCHE_SEL_3 0x00000eab + +#define REG_A5XX_UCHE_TRAP_LOG_LO 0x00000eb1 + +#define REG_A5XX_UCHE_TRAP_LOG_HI 0x00000eb2 + +#define REG_A5XX_SP_DBG_ECO_CNTL 0x00000ec0 + +#define REG_A5XX_SP_ADDR_MODE_CNTL 0x00000ec1 + +#define REG_A5XX_SP_MODE_CNTL 0x00000ec2 + +#define REG_A5XX_SP_PERFCTR_SP_SEL_0 0x00000ed0 + +#define REG_A5XX_SP_PERFCTR_SP_SEL_1 0x00000ed1 + +#define REG_A5XX_SP_PERFCTR_SP_SEL_2 0x00000ed2 + +#define REG_A5XX_SP_PERFCTR_SP_SEL_3 0x00000ed3 + +#define REG_A5XX_SP_PERFCTR_SP_SEL_4 0x00000ed4 + +#define REG_A5XX_SP_PERFCTR_SP_SEL_5 0x00000ed5 + +#define REG_A5XX_SP_PERFCTR_SP_SEL_6 0x00000ed6 + +#define REG_A5XX_SP_PERFCTR_SP_SEL_7 0x00000ed7 + +#define REG_A5XX_SP_PERFCTR_SP_SEL_8 0x00000ed8 + +#define REG_A5XX_SP_PERFCTR_SP_SEL_9 0x00000ed9 + +#define REG_A5XX_SP_PERFCTR_SP_SEL_10 0x00000eda + +#define REG_A5XX_SP_PERFCTR_SP_SEL_11 0x00000edb + +#define REG_A5XX_SP_POWERCTR_SP_SEL_0 0x00000edc + +#define REG_A5XX_SP_POWERCTR_SP_SEL_1 0x00000edd + +#define REG_A5XX_SP_POWERCTR_SP_SEL_2 0x00000ede + +#define REG_A5XX_SP_POWERCTR_SP_SEL_3 0x00000edf + +#define REG_A5XX_TPL1_ADDR_MODE_CNTL 0x00000f01 + +#define REG_A5XX_TPL1_MODE_CNTL 0x00000f02 + +#define REG_A5XX_TPL1_PERFCTR_TP_SEL_0 0x00000f10 + +#define REG_A5XX_TPL1_PERFCTR_TP_SEL_1 0x00000f11 + +#define REG_A5XX_TPL1_PERFCTR_TP_SEL_2 0x00000f12 + +#define REG_A5XX_TPL1_PERFCTR_TP_SEL_3 0x00000f13 + +#define REG_A5XX_TPL1_PERFCTR_TP_SEL_4 0x00000f14 + +#define REG_A5XX_TPL1_PERFCTR_TP_SEL_5 0x00000f15 + +#define REG_A5XX_TPL1_PERFCTR_TP_SEL_6 0x00000f16 + +#define REG_A5XX_TPL1_PERFCTR_TP_SEL_7 0x00000f17 + +#define REG_A5XX_TPL1_POWERCTR_TP_SEL_0 0x00000f18 + +#define REG_A5XX_TPL1_POWERCTR_TP_SEL_1 0x00000f19 + +#define REG_A5XX_TPL1_POWERCTR_TP_SEL_2 0x00000f1a + +#define REG_A5XX_TPL1_POWERCTR_TP_SEL_3 0x00000f1b + +#define REG_A5XX_VBIF_VERSION 0x00003000 + +#define REG_A5XX_VBIF_CLKON 0x00003001 +#define A5XX_VBIF_CLKON_FORCE_ON 0x00000001 +#define A5XX_VBIF_CLKON_FORCE_ON_TESTBUS 0x00000002 + +#define REG_A5XX_VBIF_ABIT_SORT 0x00003028 + +#define REG_A5XX_VBIF_ABIT_SORT_CONF 0x00003029 + +#define REG_A5XX_VBIF_ROUND_ROBIN_QOS_ARB 0x00003049 + +#define REG_A5XX_VBIF_GATE_OFF_WRREQ_EN 0x0000302a + +#define REG_A5XX_VBIF_IN_RD_LIM_CONF0 0x0000302c + +#define REG_A5XX_VBIF_IN_RD_LIM_CONF1 0x0000302d + +#define REG_A5XX_VBIF_XIN_HALT_CTRL0 0x00003080 + +#define REG_A5XX_VBIF_XIN_HALT_CTRL1 0x00003081 + +#define REG_A5XX_VBIF_TEST_BUS_OUT_CTRL 0x00003084 +#define A5XX_VBIF_TEST_BUS_OUT_CTRL_TEST_BUS_CTRL_EN 0x00000001 + +#define REG_A5XX_VBIF_TEST_BUS1_CTRL0 0x00003085 + +#define REG_A5XX_VBIF_TEST_BUS1_CTRL1 0x00003086 +#define A5XX_VBIF_TEST_BUS1_CTRL1_TEST_BUS1_DATA_SEL__MASK 0x0000000f +#define A5XX_VBIF_TEST_BUS1_CTRL1_TEST_BUS1_DATA_SEL__SHIFT 0 +static inline uint32_t A5XX_VBIF_TEST_BUS1_CTRL1_TEST_BUS1_DATA_SEL(uint32_t val) +{ + return ((val) << A5XX_VBIF_TEST_BUS1_CTRL1_TEST_BUS1_DATA_SEL__SHIFT) & A5XX_VBIF_TEST_BUS1_CTRL1_TEST_BUS1_DATA_SEL__MASK; +} + +#define REG_A5XX_VBIF_TEST_BUS2_CTRL0 0x00003087 + +#define REG_A5XX_VBIF_TEST_BUS2_CTRL1 0x00003088 +#define A5XX_VBIF_TEST_BUS2_CTRL1_TEST_BUS2_DATA_SEL__MASK 0x0000001f +#define A5XX_VBIF_TEST_BUS2_CTRL1_TEST_BUS2_DATA_SEL__SHIFT 0 +static inline uint32_t A5XX_VBIF_TEST_BUS2_CTRL1_TEST_BUS2_DATA_SEL(uint32_t val) +{ + return ((val) << A5XX_VBIF_TEST_BUS2_CTRL1_TEST_BUS2_DATA_SEL__SHIFT) & A5XX_VBIF_TEST_BUS2_CTRL1_TEST_BUS2_DATA_SEL__MASK; +} + +#define REG_A5XX_VBIF_TEST_BUS_OUT 0x0000308c + +static inline uint32_t REG_A5XX_VBIF_PERF_CNT_EN(uint32_t i0) { return 0x000030c0 + 0x1*i0; } + +static inline uint32_t REG_A5XX_VBIF_PERF_CNT_CLR(uint32_t i0) { return 0x000030c8 + 0x1*i0; } + +static inline uint32_t REG_A5XX_VBIF_PERF_CNT_SEL(uint32_t i0) { return 0x000030d0 + 0x1*i0; } + +#define REG_A5XX_VBIF_PERF_CNT_LOW0 0x000030d8 + +#define REG_A5XX_VBIF_PERF_CNT_LOW1 0x000030d9 + +#define REG_A5XX_VBIF_PERF_CNT_LOW2 0x000030da + +#define REG_A5XX_VBIF_PERF_CNT_LOW3 0x000030db + +#define REG_A5XX_VBIF_PERF_CNT_HIGH0 0x000030e0 + +#define REG_A5XX_VBIF_PERF_CNT_HIGH1 0x000030e1 + +#define REG_A5XX_VBIF_PERF_CNT_HIGH2 0x000030e2 + +#define REG_A5XX_VBIF_PERF_CNT_HIGH3 0x000030e3 + +static inline uint32_t REG_A5XX_VBIF_PERF_PWR_CNT_EN(uint32_t i0) { return 0x00003100 + 0x1*i0; } + +static inline uint32_t REG_A5XX_VBIF_PERF_PWR_CNT_CLR(uint32_t i0) { return 0x00003108 + 0x1*i0; } + +#define REG_A5XX_VBIF_PERF_PWR_CNT_LOW0 0x00003110 + +#define REG_A5XX_VBIF_PERF_PWR_CNT_LOW1 0x00003111 + +#define REG_A5XX_VBIF_PERF_PWR_CNT_LOW2 0x00003112 + +#define REG_A5XX_VBIF_PERF_PWR_CNT_HIGH0 0x00003118 + +#define REG_A5XX_VBIF_PERF_PWR_CNT_HIGH1 0x00003119 + +#define REG_A5XX_VBIF_PERF_PWR_CNT_HIGH2 0x0000311a + +#define REG_A5XX_GPMU_INST_RAM_BASE 0x00008800 + +#define REG_A5XX_GPMU_DATA_RAM_BASE 0x00009800 + +#define REG_A5XX_GPMU_SP_POWER_CNTL 0x0000a881 + +#define REG_A5XX_GPMU_RBCCU_CLOCK_CNTL 0x0000a886 + +#define REG_A5XX_GPMU_RBCCU_POWER_CNTL 0x0000a887 + +#define REG_A5XX_GPMU_SP_PWR_CLK_STATUS 0x0000a88b +#define A5XX_GPMU_SP_PWR_CLK_STATUS_PWR_ON 0x00100000 + +#define REG_A5XX_GPMU_RBCCU_PWR_CLK_STATUS 0x0000a88d +#define A5XX_GPMU_RBCCU_PWR_CLK_STATUS_PWR_ON 0x00100000 + +#define REG_A5XX_GPMU_PWR_COL_STAGGER_DELAY 0x0000a891 + +#define REG_A5XX_GPMU_PWR_COL_INTER_FRAME_CTRL 0x0000a892 + +#define REG_A5XX_GPMU_PWR_COL_INTER_FRAME_HYST 0x0000a893 + +#define REG_A5XX_GPMU_PWR_COL_BINNING_CTRL 0x0000a894 + +#define REG_A5XX_GPMU_CLOCK_THROTTLE_CTRL 0x0000a8a3 + +#define REG_A5XX_GPMU_WFI_CONFIG 0x0000a8c1 + +#define REG_A5XX_GPMU_RBBM_INTR_INFO 0x0000a8d6 + +#define REG_A5XX_GPMU_CM3_SYSRESET 0x0000a8d8 + +#define REG_A5XX_GPMU_GENERAL_0 0x0000a8e0 + +#define REG_A5XX_GPMU_GENERAL_1 0x0000a8e1 + +#define REG_A5XX_SP_POWER_COUNTER_0_LO 0x0000a840 + +#define REG_A5XX_SP_POWER_COUNTER_0_HI 0x0000a841 + +#define REG_A5XX_SP_POWER_COUNTER_1_LO 0x0000a842 + +#define REG_A5XX_SP_POWER_COUNTER_1_HI 0x0000a843 + +#define REG_A5XX_SP_POWER_COUNTER_2_LO 0x0000a844 + +#define REG_A5XX_SP_POWER_COUNTER_2_HI 0x0000a845 + +#define REG_A5XX_SP_POWER_COUNTER_3_LO 0x0000a846 + +#define REG_A5XX_SP_POWER_COUNTER_3_HI 0x0000a847 + +#define REG_A5XX_TP_POWER_COUNTER_0_LO 0x0000a848 + +#define REG_A5XX_TP_POWER_COUNTER_0_HI 0x0000a849 + +#define REG_A5XX_TP_POWER_COUNTER_1_LO 0x0000a84a + +#define REG_A5XX_TP_POWER_COUNTER_1_HI 0x0000a84b + +#define REG_A5XX_TP_POWER_COUNTER_2_LO 0x0000a84c + +#define REG_A5XX_TP_POWER_COUNTER_2_HI 0x0000a84d + +#define REG_A5XX_TP_POWER_COUNTER_3_LO 0x0000a84e + +#define REG_A5XX_TP_POWER_COUNTER_3_HI 0x0000a84f + +#define REG_A5XX_RB_POWER_COUNTER_0_LO 0x0000a850 + +#define REG_A5XX_RB_POWER_COUNTER_0_HI 0x0000a851 + +#define REG_A5XX_RB_POWER_COUNTER_1_LO 0x0000a852 + +#define REG_A5XX_RB_POWER_COUNTER_1_HI 0x0000a853 + +#define REG_A5XX_RB_POWER_COUNTER_2_LO 0x0000a854 + +#define REG_A5XX_RB_POWER_COUNTER_2_HI 0x0000a855 + +#define REG_A5XX_RB_POWER_COUNTER_3_LO 0x0000a856 + +#define REG_A5XX_RB_POWER_COUNTER_3_HI 0x0000a857 + +#define REG_A5XX_CCU_POWER_COUNTER_0_LO 0x0000a858 + +#define REG_A5XX_CCU_POWER_COUNTER_0_HI 0x0000a859 + +#define REG_A5XX_CCU_POWER_COUNTER_1_LO 0x0000a85a + +#define REG_A5XX_CCU_POWER_COUNTER_1_HI 0x0000a85b + +#define REG_A5XX_UCHE_POWER_COUNTER_0_LO 0x0000a85c + +#define REG_A5XX_UCHE_POWER_COUNTER_0_HI 0x0000a85d + +#define REG_A5XX_UCHE_POWER_COUNTER_1_LO 0x0000a85e + +#define REG_A5XX_UCHE_POWER_COUNTER_1_HI 0x0000a85f + +#define REG_A5XX_UCHE_POWER_COUNTER_2_LO 0x0000a860 + +#define REG_A5XX_UCHE_POWER_COUNTER_2_HI 0x0000a861 + +#define REG_A5XX_UCHE_POWER_COUNTER_3_LO 0x0000a862 + +#define REG_A5XX_UCHE_POWER_COUNTER_3_HI 0x0000a863 + +#define REG_A5XX_CP_POWER_COUNTER_0_LO 0x0000a864 + +#define REG_A5XX_CP_POWER_COUNTER_0_HI 0x0000a865 + +#define REG_A5XX_CP_POWER_COUNTER_1_LO 0x0000a866 + +#define REG_A5XX_CP_POWER_COUNTER_1_HI 0x0000a867 + +#define REG_A5XX_CP_POWER_COUNTER_2_LO 0x0000a868 + +#define REG_A5XX_CP_POWER_COUNTER_2_HI 0x0000a869 + +#define REG_A5XX_CP_POWER_COUNTER_3_LO 0x0000a86a + +#define REG_A5XX_CP_POWER_COUNTER_3_HI 0x0000a86b + +#define REG_A5XX_GPMU_POWER_COUNTER_0_LO 0x0000a86c + +#define REG_A5XX_GPMU_POWER_COUNTER_0_HI 0x0000a86d + +#define REG_A5XX_GPMU_POWER_COUNTER_1_LO 0x0000a86e + +#define REG_A5XX_GPMU_POWER_COUNTER_1_HI 0x0000a86f + +#define REG_A5XX_GPMU_POWER_COUNTER_2_LO 0x0000a870 + +#define REG_A5XX_GPMU_POWER_COUNTER_2_HI 0x0000a871 + +#define REG_A5XX_GPMU_POWER_COUNTER_3_LO 0x0000a872 + +#define REG_A5XX_GPMU_POWER_COUNTER_3_HI 0x0000a873 + +#define REG_A5XX_GPMU_POWER_COUNTER_4_LO 0x0000a874 + +#define REG_A5XX_GPMU_POWER_COUNTER_4_HI 0x0000a875 + +#define REG_A5XX_GPMU_POWER_COUNTER_5_LO 0x0000a876 + +#define REG_A5XX_GPMU_POWER_COUNTER_5_HI 0x0000a877 + +#define REG_A5XX_GPMU_POWER_COUNTER_ENABLE 0x0000a878 + +#define REG_A5XX_GPMU_ALWAYS_ON_COUNTER_LO 0x0000a879 + +#define REG_A5XX_GPMU_ALWAYS_ON_COUNTER_HI 0x0000a87a + +#define REG_A5XX_GPMU_ALWAYS_ON_COUNTER_RESET 0x0000a87b + +#define REG_A5XX_GPMU_POWER_COUNTER_SELECT_0 0x0000a87c + +#define REG_A5XX_GPMU_POWER_COUNTER_SELECT_1 0x0000a87d + +#define REG_A5XX_GPMU_CLOCK_THROTTLE_CTRL 0x0000a8a3 + +#define REG_A5XX_GPMU_THROTTLE_UNMASK_FORCE_CTRL 0x0000a8a8 + +#define REG_A5XX_GPMU_TEMP_SENSOR_ID 0x0000ac00 + +#define REG_A5XX_GPMU_TEMP_SENSOR_CONFIG 0x0000ac01 +#define A5XX_GPMU_TEMP_SENSOR_CONFIG_ISENSE_STATUS__MASK 0x0000000f +#define A5XX_GPMU_TEMP_SENSOR_CONFIG_ISENSE_STATUS__SHIFT 0 +static inline uint32_t A5XX_GPMU_TEMP_SENSOR_CONFIG_ISENSE_STATUS(uint32_t val) +{ + return ((val) << A5XX_GPMU_TEMP_SENSOR_CONFIG_ISENSE_STATUS__SHIFT) & A5XX_GPMU_TEMP_SENSOR_CONFIG_ISENSE_STATUS__MASK; +} +#define A5XX_GPMU_TEMP_SENSOR_CONFIG_BCL_ENABLED 0x00000002 +#define A5XX_GPMU_TEMP_SENSOR_CONFIG_LLM_ENABLED 0x00000200 + +#define REG_A5XX_GPMU_TEMP_VAL 0x0000ac02 + +#define REG_A5XX_GPMU_DELTA_TEMP_THRESHOLD 0x0000ac03 + +#define REG_A5XX_GPMU_TEMP_THRESHOLD_INTR_STATUS 0x0000ac05 + +#define REG_A5XX_GPMU_TEMP_THRESHOLD_INTR_EN_MASK 0x0000ac06 + +#define REG_A5XX_GPMU_LEAKAGE_TEMP_COEFF_0_1 0x0000ac40 + +#define REG_A5XX_GPMU_LEAKAGE_TEMP_COEFF_2_3 0x0000ac41 + +#define REG_A5XX_GPMU_LEAKAGE_VTG_COEFF_0_1 0x0000ac42 + +#define REG_A5XX_GPMU_LEAKAGE_VTG_COEFF_2_3 0x0000ac43 + +#define REG_A5XX_GPMU_BASE_LEAKAGE 0x0000ac46 + +#define REG_A5XX_GPMU_GPMU_VOLTAGE 0x0000ac60 + +#define REG_A5XX_GPMU_GPMU_VOLTAGE_INTR_STATUS 0x0000ac61 + +#define REG_A5XX_GPMU_GPMU_VOLTAGE_INTR_EN_MASK 0x0000ac62 + +#define REG_A5XX_GPMU_GPMU_PWR_THRESHOLD 0x0000ac80 + +#define REG_A5XX_GPMU_GPMU_LLM_GLM_SLEEP_CTRL 0x0000acc4 +#define A5XX_GPMU_GPMU_LLM_GLM_SLEEP_CTRL_IDLE_FULL_LM 0x00000001 +#define A5XX_GPMU_GPMU_LLM_GLM_SLEEP_CTRL_STATE_OF_CHILD__MASK 0x00000030 +#define A5XX_GPMU_GPMU_LLM_GLM_SLEEP_CTRL_STATE_OF_CHILD__SHIFT 4 +static inline uint32_t A5XX_GPMU_GPMU_LLM_GLM_SLEEP_CTRL_STATE_OF_CHILD(uint32_t val) +{ + return ((val) << A5XX_GPMU_GPMU_LLM_GLM_SLEEP_CTRL_STATE_OF_CHILD__SHIFT) & A5XX_GPMU_GPMU_LLM_GLM_SLEEP_CTRL_STATE_OF_CHILD__MASK; +} + +#define REG_A5XX_GPMU_GPMU_LLM_GLM_SLEEP_STATUS 0x0000acc5 +#define A5XX_GPMU_GPMU_LLM_GLM_SLEEP_STATUS_IDLE_FULL_ACK 0x00000001 +#define A5XX_GPMU_GPMU_LLM_GLM_SLEEP_STATUS_WAKEUP_ACK 0x00000002 + +#define REG_A5XX_GDPM_CONFIG1 0x0000b80c + +#define REG_A5XX_GDPM_CONFIG2 0x0000b80d + +#define REG_A5XX_GDPM_INT_EN 0x0000b80f + +#define REG_A5XX_GDPM_INT_MASK 0x0000b811 + +#define REG_A5XX_GPMU_BEC_ENABLE 0x0000b9a0 + +#define REG_A5XX_GPU_CS_SENSOR_GENERAL_STATUS 0x0000c41a + +#define REG_A5XX_GPU_CS_AMP_CALIBRATION_STATUS1_0 0x0000c41d + +#define REG_A5XX_GPU_CS_AMP_CALIBRATION_STATUS1_2 0x0000c41f + +#define REG_A5XX_GPU_CS_AMP_CALIBRATION_STATUS1_4 0x0000c421 + +#define REG_A5XX_GPU_CS_ENABLE_REG 0x0000c520 + +#define REG_A5XX_GPU_CS_AMP_CALIBRATION_CONTROL1 0x0000c557 + +#define REG_A5XX_GRAS_CL_CNTL 0x0000e000 + +#define REG_A5XX_UNKNOWN_E001 0x0000e001 + +#define REG_A5XX_UNKNOWN_E004 0x0000e004 + +#define REG_A5XX_GRAS_CLEAR_CNTL 0x0000e005 +#define A5XX_GRAS_CLEAR_CNTL_NOT_FASTCLEAR 0x00000001 + +#define REG_A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ 0x0000e006 +#define A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__MASK 0x000003ff +#define A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__SHIFT 0 +static inline uint32_t A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ(uint32_t val) +{ + return ((val) << A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__SHIFT) & A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__MASK; +} +#define A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__MASK 0x000ffc00 +#define A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__SHIFT 10 +static inline uint32_t A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT(uint32_t val) +{ + return ((val) << A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__SHIFT) & A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__MASK; +} + +#define REG_A5XX_GRAS_CL_VPORT_XOFFSET_0 0x0000e010 +#define A5XX_GRAS_CL_VPORT_XOFFSET_0__MASK 0xffffffff +#define A5XX_GRAS_CL_VPORT_XOFFSET_0__SHIFT 0 +static inline uint32_t A5XX_GRAS_CL_VPORT_XOFFSET_0(float val) +{ + return ((fui(val)) << A5XX_GRAS_CL_VPORT_XOFFSET_0__SHIFT) & A5XX_GRAS_CL_VPORT_XOFFSET_0__MASK; +} + +#define REG_A5XX_GRAS_CL_VPORT_XSCALE_0 0x0000e011 +#define A5XX_GRAS_CL_VPORT_XSCALE_0__MASK 0xffffffff +#define A5XX_GRAS_CL_VPORT_XSCALE_0__SHIFT 0 +static inline uint32_t A5XX_GRAS_CL_VPORT_XSCALE_0(float val) +{ + return ((fui(val)) << A5XX_GRAS_CL_VPORT_XSCALE_0__SHIFT) & A5XX_GRAS_CL_VPORT_XSCALE_0__MASK; +} + +#define REG_A5XX_GRAS_CL_VPORT_YOFFSET_0 0x0000e012 +#define A5XX_GRAS_CL_VPORT_YOFFSET_0__MASK 0xffffffff +#define A5XX_GRAS_CL_VPORT_YOFFSET_0__SHIFT 0 +static inline uint32_t A5XX_GRAS_CL_VPORT_YOFFSET_0(float val) +{ + return ((fui(val)) << A5XX_GRAS_CL_VPORT_YOFFSET_0__SHIFT) & A5XX_GRAS_CL_VPORT_YOFFSET_0__MASK; +} + +#define REG_A5XX_GRAS_CL_VPORT_YSCALE_0 0x0000e013 +#define A5XX_GRAS_CL_VPORT_YSCALE_0__MASK 0xffffffff +#define A5XX_GRAS_CL_VPORT_YSCALE_0__SHIFT 0 +static inline uint32_t A5XX_GRAS_CL_VPORT_YSCALE_0(float val) +{ + return ((fui(val)) << A5XX_GRAS_CL_VPORT_YSCALE_0__SHIFT) & A5XX_GRAS_CL_VPORT_YSCALE_0__MASK; +} + +#define REG_A5XX_GRAS_CL_VPORT_ZOFFSET_0 0x0000e014 +#define A5XX_GRAS_CL_VPORT_ZOFFSET_0__MASK 0xffffffff +#define A5XX_GRAS_CL_VPORT_ZOFFSET_0__SHIFT 0 +static inline uint32_t A5XX_GRAS_CL_VPORT_ZOFFSET_0(float val) +{ + return ((fui(val)) << A5XX_GRAS_CL_VPORT_ZOFFSET_0__SHIFT) & A5XX_GRAS_CL_VPORT_ZOFFSET_0__MASK; +} + +#define REG_A5XX_GRAS_CL_VPORT_ZSCALE_0 0x0000e015 +#define A5XX_GRAS_CL_VPORT_ZSCALE_0__MASK 0xffffffff +#define A5XX_GRAS_CL_VPORT_ZSCALE_0__SHIFT 0 +static inline uint32_t A5XX_GRAS_CL_VPORT_ZSCALE_0(float val) +{ + return ((fui(val)) << A5XX_GRAS_CL_VPORT_ZSCALE_0__SHIFT) & A5XX_GRAS_CL_VPORT_ZSCALE_0__MASK; +} + +#define REG_A5XX_GRAS_SU_CNTL 0x0000e090 +#define A5XX_GRAS_SU_CNTL_FRONT_CW 0x00000004 +#define A5XX_GRAS_SU_CNTL_POLY_OFFSET 0x00000800 + +#define REG_A5XX_GRAS_SU_POINT_MINMAX 0x0000e091 +#define A5XX_GRAS_SU_POINT_MINMAX_MIN__MASK 0x0000ffff +#define A5XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT 0 +static inline uint32_t A5XX_GRAS_SU_POINT_MINMAX_MIN(float val) +{ + return ((((uint32_t)(val * 16.0))) << A5XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT) & A5XX_GRAS_SU_POINT_MINMAX_MIN__MASK; +} +#define A5XX_GRAS_SU_POINT_MINMAX_MAX__MASK 0xffff0000 +#define A5XX_GRAS_SU_POINT_MINMAX_MAX__SHIFT 16 +static inline uint32_t A5XX_GRAS_SU_POINT_MINMAX_MAX(float val) +{ + return ((((uint32_t)(val * 16.0))) << A5XX_GRAS_SU_POINT_MINMAX_MAX__SHIFT) & A5XX_GRAS_SU_POINT_MINMAX_MAX__MASK; +} + +#define REG_A5XX_GRAS_SU_POINT_SIZE 0x0000e092 +#define A5XX_GRAS_SU_POINT_SIZE__MASK 0xffffffff +#define A5XX_GRAS_SU_POINT_SIZE__SHIFT 0 +static inline uint32_t A5XX_GRAS_SU_POINT_SIZE(float val) +{ + return ((((int32_t)(val * 16.0))) << A5XX_GRAS_SU_POINT_SIZE__SHIFT) & A5XX_GRAS_SU_POINT_SIZE__MASK; +} + +#define REG_A5XX_UNKNOWN_E093 0x0000e093 + +#define REG_A5XX_GRAS_SU_DEPTH_PLANE_CNTL 0x0000e094 +#define A5XX_GRAS_SU_DEPTH_PLANE_CNTL_ALPHA_TEST_ENABLE 0x00000001 + +#define REG_A5XX_GRAS_SU_POLY_OFFSET_SCALE 0x0000e095 +#define A5XX_GRAS_SU_POLY_OFFSET_SCALE__MASK 0xffffffff +#define A5XX_GRAS_SU_POLY_OFFSET_SCALE__SHIFT 0 +static inline uint32_t A5XX_GRAS_SU_POLY_OFFSET_SCALE(float val) +{ + return ((fui(val)) << A5XX_GRAS_SU_POLY_OFFSET_SCALE__SHIFT) & A5XX_GRAS_SU_POLY_OFFSET_SCALE__MASK; +} + +#define REG_A5XX_GRAS_SU_POLY_OFFSET_OFFSET 0x0000e096 +#define A5XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK 0xffffffff +#define A5XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT 0 +static inline uint32_t A5XX_GRAS_SU_POLY_OFFSET_OFFSET(float val) +{ + return ((fui(val)) << A5XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT) & A5XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK; +} + +#define REG_A5XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP 0x0000e097 +#define A5XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__MASK 0xffffffff +#define A5XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__SHIFT 0 +static inline uint32_t A5XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP(float val) +{ + return ((fui(val)) << A5XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__SHIFT) & A5XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__MASK; +} + +#define REG_A5XX_GRAS_SU_DEPTH_BUFFER_INFO 0x0000e098 +#define A5XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK 0x00000007 +#define A5XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT 0 +static inline uint32_t A5XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT(enum a5xx_depth_format val) +{ + return ((val) << A5XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT) & A5XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK; +} + +#define REG_A5XX_GRAS_SU_CONSERVATIVE_RAS_CNTL 0x0000e099 + +#define REG_A5XX_GRAS_SC_CNTL 0x0000e0a0 + +#define REG_A5XX_GRAS_SC_BIN_CNTL 0x0000e0a1 + +#define REG_A5XX_GRAS_SC_RAS_MSAA_CNTL 0x0000e0a2 +#define A5XX_GRAS_SC_RAS_MSAA_CNTL_SAMPLES__MASK 0x00000003 +#define A5XX_GRAS_SC_RAS_MSAA_CNTL_SAMPLES__SHIFT 0 +static inline uint32_t A5XX_GRAS_SC_RAS_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val) +{ + return ((val) << A5XX_GRAS_SC_RAS_MSAA_CNTL_SAMPLES__SHIFT) & A5XX_GRAS_SC_RAS_MSAA_CNTL_SAMPLES__MASK; +} + +#define REG_A5XX_GRAS_SC_DEST_MSAA_CNTL 0x0000e0a3 +#define A5XX_GRAS_SC_DEST_MSAA_CNTL_SAMPLES__MASK 0x00000003 +#define A5XX_GRAS_SC_DEST_MSAA_CNTL_SAMPLES__SHIFT 0 +static inline uint32_t A5XX_GRAS_SC_DEST_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val) +{ + return ((val) << A5XX_GRAS_SC_DEST_MSAA_CNTL_SAMPLES__SHIFT) & A5XX_GRAS_SC_DEST_MSAA_CNTL_SAMPLES__MASK; +} +#define A5XX_GRAS_SC_DEST_MSAA_CNTL_MSAA_DISABLE 0x00000004 + +#define REG_A5XX_GRAS_SC_SCREEN_SCISSOR_CNTL 0x0000e0a4 + +#define REG_A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0 0x0000e0aa +#define A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_WINDOW_OFFSET_DISABLE 0x80000000 +#define A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X__MASK 0x00007fff +#define A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X__SHIFT 0 +static inline uint32_t A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X(uint32_t val) +{ + return ((val) << A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X__SHIFT) & A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X__MASK; +} +#define A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y__MASK 0x7fff0000 +#define A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y__SHIFT 16 +static inline uint32_t A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y(uint32_t val) +{ + return ((val) << A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y__SHIFT) & A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y__MASK; +} + +#define REG_A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0 0x0000e0ab +#define A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_WINDOW_OFFSET_DISABLE 0x80000000 +#define A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_X__MASK 0x00007fff +#define A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_X__SHIFT 0 +static inline uint32_t A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_X(uint32_t val) +{ + return ((val) << A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_X__SHIFT) & A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_X__MASK; +} +#define A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_Y__MASK 0x7fff0000 +#define A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_Y__SHIFT 16 +static inline uint32_t A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_Y(uint32_t val) +{ + return ((val) << A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_Y__SHIFT) & A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_Y__MASK; +} + +#define REG_A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0 0x0000e0ca +#define A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_WINDOW_OFFSET_DISABLE 0x80000000 +#define A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X__MASK 0x00007fff +#define A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X__SHIFT 0 +static inline uint32_t A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X(uint32_t val) +{ + return ((val) << A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X__SHIFT) & A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X__MASK; +} +#define A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y__MASK 0x7fff0000 +#define A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y__SHIFT 16 +static inline uint32_t A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y(uint32_t val) +{ + return ((val) << A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y__SHIFT) & A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y__MASK; +} + +#define REG_A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0 0x0000e0cb +#define A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_WINDOW_OFFSET_DISABLE 0x80000000 +#define A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_X__MASK 0x00007fff +#define A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_X__SHIFT 0 +static inline uint32_t A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_X(uint32_t val) +{ + return ((val) << A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_X__SHIFT) & A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_X__MASK; +} +#define A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_Y__MASK 0x7fff0000 +#define A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_Y__SHIFT 16 +static inline uint32_t A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_Y(uint32_t val) +{ + return ((val) << A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_Y__SHIFT) & A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_Y__MASK; +} + +#define REG_A5XX_GRAS_SC_WINDOW_SCISSOR_TL 0x0000e0ea +#define A5XX_GRAS_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE 0x80000000 +#define A5XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK 0x00007fff +#define A5XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT 0 +static inline uint32_t A5XX_GRAS_SC_WINDOW_SCISSOR_TL_X(uint32_t val) +{ + return ((val) << A5XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT) & A5XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK; +} +#define A5XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK 0x7fff0000 +#define A5XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT 16 +static inline uint32_t A5XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(uint32_t val) +{ + return ((val) << A5XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT) & A5XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK; +} + +#define REG_A5XX_GRAS_SC_WINDOW_SCISSOR_BR 0x0000e0eb +#define A5XX_GRAS_SC_WINDOW_SCISSOR_BR_WINDOW_OFFSET_DISABLE 0x80000000 +#define A5XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK 0x00007fff +#define A5XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT 0 +static inline uint32_t A5XX_GRAS_SC_WINDOW_SCISSOR_BR_X(uint32_t val) +{ + return ((val) << A5XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT) & A5XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK; +} +#define A5XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK 0x7fff0000 +#define A5XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT 16 +static inline uint32_t A5XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(uint32_t val) +{ + return ((val) << A5XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT) & A5XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK; +} + +#define REG_A5XX_GRAS_LRZ_CNTL 0x0000e100 + +#define REG_A5XX_GRAS_LRZ_BUFFER_BASE_LO 0x0000e101 + +#define REG_A5XX_GRAS_LRZ_BUFFER_BASE_HI 0x0000e102 + +#define REG_A5XX_GRAS_LRZ_BUFFER_PITCH 0x0000e103 + +#define REG_A5XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_LO 0x0000e104 + +#define REG_A5XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_HI 0x0000e105 + +#define REG_A5XX_RB_CNTL 0x0000e140 +#define A5XX_RB_CNTL_WIDTH__MASK 0x000000ff +#define A5XX_RB_CNTL_WIDTH__SHIFT 0 +static inline uint32_t A5XX_RB_CNTL_WIDTH(uint32_t val) +{ + return ((val >> 5) << A5XX_RB_CNTL_WIDTH__SHIFT) & A5XX_RB_CNTL_WIDTH__MASK; +} +#define A5XX_RB_CNTL_HEIGHT__MASK 0x0001fe00 +#define A5XX_RB_CNTL_HEIGHT__SHIFT 9 +static inline uint32_t A5XX_RB_CNTL_HEIGHT(uint32_t val) +{ + return ((val >> 5) << A5XX_RB_CNTL_HEIGHT__SHIFT) & A5XX_RB_CNTL_HEIGHT__MASK; +} +#define A5XX_RB_CNTL_BYPASS 0x00020000 + +#define REG_A5XX_RB_RENDER_CNTL 0x0000e141 +#define A5XX_RB_RENDER_CNTL_ENABLED_MRTS__MASK 0x00ff0000 +#define A5XX_RB_RENDER_CNTL_ENABLED_MRTS__SHIFT 16 +static inline uint32_t A5XX_RB_RENDER_CNTL_ENABLED_MRTS(uint32_t val) +{ + return ((val) << A5XX_RB_RENDER_CNTL_ENABLED_MRTS__SHIFT) & A5XX_RB_RENDER_CNTL_ENABLED_MRTS__MASK; +} +#define A5XX_RB_RENDER_CNTL_ENABLED_MRTS2__MASK 0xff000000 +#define A5XX_RB_RENDER_CNTL_ENABLED_MRTS2__SHIFT 24 +static inline uint32_t A5XX_RB_RENDER_CNTL_ENABLED_MRTS2(uint32_t val) +{ + return ((val) << A5XX_RB_RENDER_CNTL_ENABLED_MRTS2__SHIFT) & A5XX_RB_RENDER_CNTL_ENABLED_MRTS2__MASK; +} + +#define REG_A5XX_RB_RAS_MSAA_CNTL 0x0000e142 +#define A5XX_RB_RAS_MSAA_CNTL_SAMPLES__MASK 0x00000003 +#define A5XX_RB_RAS_MSAA_CNTL_SAMPLES__SHIFT 0 +static inline uint32_t A5XX_RB_RAS_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val) +{ + return ((val) << A5XX_RB_RAS_MSAA_CNTL_SAMPLES__SHIFT) & A5XX_RB_RAS_MSAA_CNTL_SAMPLES__MASK; +} + +#define REG_A5XX_RB_DEST_MSAA_CNTL 0x0000e143 +#define A5XX_RB_DEST_MSAA_CNTL_SAMPLES__MASK 0x00000003 +#define A5XX_RB_DEST_MSAA_CNTL_SAMPLES__SHIFT 0 +static inline uint32_t A5XX_RB_DEST_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val) +{ + return ((val) << A5XX_RB_DEST_MSAA_CNTL_SAMPLES__SHIFT) & A5XX_RB_DEST_MSAA_CNTL_SAMPLES__MASK; +} +#define A5XX_RB_DEST_MSAA_CNTL_MSAA_DISABLE 0x00000004 + +#define REG_A5XX_RB_RENDER_CONTROL0 0x0000e144 +#define A5XX_RB_RENDER_CONTROL0_VARYING 0x00000001 +#define A5XX_RB_RENDER_CONTROL0_XCOORD 0x00000040 +#define A5XX_RB_RENDER_CONTROL0_YCOORD 0x00000080 +#define A5XX_RB_RENDER_CONTROL0_ZCOORD 0x00000100 +#define A5XX_RB_RENDER_CONTROL0_WCOORD 0x00000200 + +#define REG_A5XX_RB_RENDER_CONTROL1 0x0000e145 +#define A5XX_RB_RENDER_CONTROL1_FACENESS 0x00000002 + +#define REG_A5XX_RB_FS_OUTPUT_CNTL 0x0000e146 +#define A5XX_RB_FS_OUTPUT_CNTL_MRT__MASK 0x0000000f +#define A5XX_RB_FS_OUTPUT_CNTL_MRT__SHIFT 0 +static inline uint32_t A5XX_RB_FS_OUTPUT_CNTL_MRT(uint32_t val) +{ + return ((val) << A5XX_RB_FS_OUTPUT_CNTL_MRT__SHIFT) & A5XX_RB_FS_OUTPUT_CNTL_MRT__MASK; +} +#define A5XX_RB_FS_OUTPUT_CNTL_FRAG_WRITES_Z 0x00000020 + +static inline uint32_t REG_A5XX_RB_MRT(uint32_t i0) { return 0x0000e150 + 0x7*i0; } + +static inline uint32_t REG_A5XX_RB_MRT_CONTROL(uint32_t i0) { return 0x0000e150 + 0x7*i0; } +#define A5XX_RB_MRT_CONTROL_BLEND 0x00000001 +#define A5XX_RB_MRT_CONTROL_BLEND2 0x00000002 +#define A5XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK 0x00000780 +#define A5XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT 7 +static inline uint32_t A5XX_RB_MRT_CONTROL_COMPONENT_ENABLE(uint32_t val) +{ + return ((val) << A5XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT) & A5XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK; +} + +static inline uint32_t REG_A5XX_RB_MRT_BLEND_CONTROL(uint32_t i0) { return 0x0000e151 + 0x7*i0; } +#define A5XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK 0x0000001f +#define A5XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT 0 +static inline uint32_t A5XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(enum adreno_rb_blend_factor val) +{ + return ((val) << A5XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT) & A5XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK; +} +#define A5XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK 0x000000e0 +#define A5XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT 5 +static inline uint32_t A5XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(enum a3xx_rb_blend_opcode val) +{ + return ((val) << A5XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT) & A5XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK; +} +#define A5XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK 0x00001f00 +#define A5XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__SHIFT 8 +static inline uint32_t A5XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(enum adreno_rb_blend_factor val) +{ + return ((val) << A5XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__SHIFT) & A5XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK; +} +#define A5XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK 0x001f0000 +#define A5XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__SHIFT 16 +static inline uint32_t A5XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(enum adreno_rb_blend_factor val) +{ + return ((val) << A5XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__SHIFT) & A5XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK; +} +#define A5XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK 0x00e00000 +#define A5XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT 21 +static inline uint32_t A5XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(enum a3xx_rb_blend_opcode val) +{ + return ((val) << A5XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT) & A5XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK; +} +#define A5XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK 0x1f000000 +#define A5XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT 24 +static inline uint32_t A5XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(enum adreno_rb_blend_factor val) +{ + return ((val) << A5XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT) & A5XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK; +} + +static inline uint32_t REG_A5XX_RB_MRT_BUF_INFO(uint32_t i0) { return 0x0000e152 + 0x7*i0; } +#define A5XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK 0x0000007f +#define A5XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT 0 +static inline uint32_t A5XX_RB_MRT_BUF_INFO_COLOR_FORMAT(enum a5xx_color_fmt val) +{ + return ((val) << A5XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT) & A5XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK; +} +#define A5XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK 0x00000300 +#define A5XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT 8 +static inline uint32_t A5XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(enum a5xx_tile_mode val) +{ + return ((val) << A5XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT) & A5XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK; +} +#define A5XX_RB_MRT_BUF_INFO_COLOR_SRGB 0x00008000 + +static inline uint32_t REG_A5XX_RB_MRT_PITCH(uint32_t i0) { return 0x0000e153 + 0x7*i0; } +#define A5XX_RB_MRT_PITCH_COLOR_BUF_PITCH__MASK 0x0007ffff +#define A5XX_RB_MRT_PITCH_COLOR_BUF_PITCH__SHIFT 0 +static inline uint32_t A5XX_RB_MRT_PITCH_COLOR_BUF_PITCH(uint32_t val) +{ + return ((val >> 4) << A5XX_RB_MRT_PITCH_COLOR_BUF_PITCH__SHIFT) & A5XX_RB_MRT_PITCH_COLOR_BUF_PITCH__MASK; +} + +static inline uint32_t REG_A5XX_RB_MRT_ARRAY_PITCH(uint32_t i0) { return 0x0000e154 + 0x7*i0; } +#define A5XX_RB_MRT_ARRAY_PITCH_COLOR_BUF_SIZE__MASK 0x01ffffff +#define A5XX_RB_MRT_ARRAY_PITCH_COLOR_BUF_SIZE__SHIFT 0 +static inline uint32_t A5XX_RB_MRT_ARRAY_PITCH_COLOR_BUF_SIZE(uint32_t val) +{ + return ((val >> 6) << A5XX_RB_MRT_ARRAY_PITCH_COLOR_BUF_SIZE__SHIFT) & A5XX_RB_MRT_ARRAY_PITCH_COLOR_BUF_SIZE__MASK; +} + +static inline uint32_t REG_A5XX_RB_MRT_BASE_LO(uint32_t i0) { return 0x0000e155 + 0x7*i0; } + +static inline uint32_t REG_A5XX_RB_MRT_BASE_HI(uint32_t i0) { return 0x0000e156 + 0x7*i0; } + +#define REG_A5XX_RB_BLEND_RED 0x0000e1a0 +#define A5XX_RB_BLEND_RED_UINT__MASK 0x000000ff +#define A5XX_RB_BLEND_RED_UINT__SHIFT 0 +static inline uint32_t A5XX_RB_BLEND_RED_UINT(uint32_t val) +{ + return ((val) << A5XX_RB_BLEND_RED_UINT__SHIFT) & A5XX_RB_BLEND_RED_UINT__MASK; +} +#define A5XX_RB_BLEND_RED_SINT__MASK 0x0000ff00 +#define A5XX_RB_BLEND_RED_SINT__SHIFT 8 +static inline uint32_t A5XX_RB_BLEND_RED_SINT(uint32_t val) +{ + return ((val) << A5XX_RB_BLEND_RED_SINT__SHIFT) & A5XX_RB_BLEND_RED_SINT__MASK; +} +#define A5XX_RB_BLEND_RED_FLOAT__MASK 0xffff0000 +#define A5XX_RB_BLEND_RED_FLOAT__SHIFT 16 +static inline uint32_t A5XX_RB_BLEND_RED_FLOAT(float val) +{ + return ((util_float_to_half(val)) << A5XX_RB_BLEND_RED_FLOAT__SHIFT) & A5XX_RB_BLEND_RED_FLOAT__MASK; +} + +#define REG_A5XX_RB_BLEND_RED_F32 0x0000e1a1 +#define A5XX_RB_BLEND_RED_F32__MASK 0xffffffff +#define A5XX_RB_BLEND_RED_F32__SHIFT 0 +static inline uint32_t A5XX_RB_BLEND_RED_F32(float val) +{ + return ((fui(val)) << A5XX_RB_BLEND_RED_F32__SHIFT) & A5XX_RB_BLEND_RED_F32__MASK; +} + +#define REG_A5XX_RB_BLEND_GREEN 0x0000e1a2 +#define A5XX_RB_BLEND_GREEN_UINT__MASK 0x000000ff +#define A5XX_RB_BLEND_GREEN_UINT__SHIFT 0 +static inline uint32_t A5XX_RB_BLEND_GREEN_UINT(uint32_t val) +{ + return ((val) << A5XX_RB_BLEND_GREEN_UINT__SHIFT) & A5XX_RB_BLEND_GREEN_UINT__MASK; +} +#define A5XX_RB_BLEND_GREEN_SINT__MASK 0x0000ff00 +#define A5XX_RB_BLEND_GREEN_SINT__SHIFT 8 +static inline uint32_t A5XX_RB_BLEND_GREEN_SINT(uint32_t val) +{ + return ((val) << A5XX_RB_BLEND_GREEN_SINT__SHIFT) & A5XX_RB_BLEND_GREEN_SINT__MASK; +} +#define A5XX_RB_BLEND_GREEN_FLOAT__MASK 0xffff0000 +#define A5XX_RB_BLEND_GREEN_FLOAT__SHIFT 16 +static inline uint32_t A5XX_RB_BLEND_GREEN_FLOAT(float val) +{ + return ((util_float_to_half(val)) << A5XX_RB_BLEND_GREEN_FLOAT__SHIFT) & A5XX_RB_BLEND_GREEN_FLOAT__MASK; +} + +#define REG_A5XX_RB_BLEND_GREEN_F32 0x0000e1a3 +#define A5XX_RB_BLEND_GREEN_F32__MASK 0xffffffff +#define A5XX_RB_BLEND_GREEN_F32__SHIFT 0 +static inline uint32_t A5XX_RB_BLEND_GREEN_F32(float val) +{ + return ((fui(val)) << A5XX_RB_BLEND_GREEN_F32__SHIFT) & A5XX_RB_BLEND_GREEN_F32__MASK; +} + +#define REG_A5XX_RB_BLEND_BLUE 0x0000e1a4 +#define A5XX_RB_BLEND_BLUE_UINT__MASK 0x000000ff +#define A5XX_RB_BLEND_BLUE_UINT__SHIFT 0 +static inline uint32_t A5XX_RB_BLEND_BLUE_UINT(uint32_t val) +{ + return ((val) << A5XX_RB_BLEND_BLUE_UINT__SHIFT) & A5XX_RB_BLEND_BLUE_UINT__MASK; +} +#define A5XX_RB_BLEND_BLUE_SINT__MASK 0x0000ff00 +#define A5XX_RB_BLEND_BLUE_SINT__SHIFT 8 +static inline uint32_t A5XX_RB_BLEND_BLUE_SINT(uint32_t val) +{ + return ((val) << A5XX_RB_BLEND_BLUE_SINT__SHIFT) & A5XX_RB_BLEND_BLUE_SINT__MASK; +} +#define A5XX_RB_BLEND_BLUE_FLOAT__MASK 0xffff0000 +#define A5XX_RB_BLEND_BLUE_FLOAT__SHIFT 16 +static inline uint32_t A5XX_RB_BLEND_BLUE_FLOAT(float val) +{ + return ((util_float_to_half(val)) << A5XX_RB_BLEND_BLUE_FLOAT__SHIFT) & A5XX_RB_BLEND_BLUE_FLOAT__MASK; +} + +#define REG_A5XX_RB_BLEND_BLUE_F32 0x0000e1a5 +#define A5XX_RB_BLEND_BLUE_F32__MASK 0xffffffff +#define A5XX_RB_BLEND_BLUE_F32__SHIFT 0 +static inline uint32_t A5XX_RB_BLEND_BLUE_F32(float val) +{ + return ((fui(val)) << A5XX_RB_BLEND_BLUE_F32__SHIFT) & A5XX_RB_BLEND_BLUE_F32__MASK; +} + +#define REG_A5XX_RB_BLEND_ALPHA 0x0000e1a6 +#define A5XX_RB_BLEND_ALPHA_UINT__MASK 0x000000ff +#define A5XX_RB_BLEND_ALPHA_UINT__SHIFT 0 +static inline uint32_t A5XX_RB_BLEND_ALPHA_UINT(uint32_t val) +{ + return ((val) << A5XX_RB_BLEND_ALPHA_UINT__SHIFT) & A5XX_RB_BLEND_ALPHA_UINT__MASK; +} +#define A5XX_RB_BLEND_ALPHA_SINT__MASK 0x0000ff00 +#define A5XX_RB_BLEND_ALPHA_SINT__SHIFT 8 +static inline uint32_t A5XX_RB_BLEND_ALPHA_SINT(uint32_t val) +{ + return ((val) << A5XX_RB_BLEND_ALPHA_SINT__SHIFT) & A5XX_RB_BLEND_ALPHA_SINT__MASK; +} +#define A5XX_RB_BLEND_ALPHA_FLOAT__MASK 0xffff0000 +#define A5XX_RB_BLEND_ALPHA_FLOAT__SHIFT 16 +static inline uint32_t A5XX_RB_BLEND_ALPHA_FLOAT(float val) +{ + return ((util_float_to_half(val)) << A5XX_RB_BLEND_ALPHA_FLOAT__SHIFT) & A5XX_RB_BLEND_ALPHA_FLOAT__MASK; +} + +#define REG_A5XX_RB_BLEND_ALPHA_F32 0x0000e1a7 +#define A5XX_RB_BLEND_ALPHA_F32__MASK 0xffffffff +#define A5XX_RB_BLEND_ALPHA_F32__SHIFT 0 +static inline uint32_t A5XX_RB_BLEND_ALPHA_F32(float val) +{ + return ((fui(val)) << A5XX_RB_BLEND_ALPHA_F32__SHIFT) & A5XX_RB_BLEND_ALPHA_F32__MASK; +} + +#define REG_A5XX_RB_ALPHA_CONTROL 0x0000e1a8 +#define A5XX_RB_ALPHA_CONTROL_ALPHA_REF__MASK 0x000000ff +#define A5XX_RB_ALPHA_CONTROL_ALPHA_REF__SHIFT 0 +static inline uint32_t A5XX_RB_ALPHA_CONTROL_ALPHA_REF(uint32_t val) +{ + return ((val) << A5XX_RB_ALPHA_CONTROL_ALPHA_REF__SHIFT) & A5XX_RB_ALPHA_CONTROL_ALPHA_REF__MASK; +} +#define A5XX_RB_ALPHA_CONTROL_ALPHA_TEST 0x00000100 +#define A5XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__MASK 0x00000e00 +#define A5XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__SHIFT 9 +static inline uint32_t A5XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC(enum adreno_compare_func val) +{ + return ((val) << A5XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__SHIFT) & A5XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__MASK; +} + +#define REG_A5XX_RB_BLEND_CNTL 0x0000e1a9 +#define A5XX_RB_BLEND_CNTL_ENABLE_BLEND__MASK 0x000000ff +#define A5XX_RB_BLEND_CNTL_ENABLE_BLEND__SHIFT 0 +static inline uint32_t A5XX_RB_BLEND_CNTL_ENABLE_BLEND(uint32_t val) +{ + return ((val) << A5XX_RB_BLEND_CNTL_ENABLE_BLEND__SHIFT) & A5XX_RB_BLEND_CNTL_ENABLE_BLEND__MASK; +} +#define A5XX_RB_BLEND_CNTL_INDEPENDENT_BLEND 0x00000100 +#define A5XX_RB_BLEND_CNTL_SAMPLE_MASK__MASK 0xffff0000 +#define A5XX_RB_BLEND_CNTL_SAMPLE_MASK__SHIFT 16 +static inline uint32_t A5XX_RB_BLEND_CNTL_SAMPLE_MASK(uint32_t val) +{ + return ((val) << A5XX_RB_BLEND_CNTL_SAMPLE_MASK__SHIFT) & A5XX_RB_BLEND_CNTL_SAMPLE_MASK__MASK; +} + +#define REG_A5XX_RB_DEPTH_PLANE_CNTL 0x0000e1b0 +#define A5XX_RB_DEPTH_PLANE_CNTL_FRAG_WRITES_Z 0x00000001 + +#define REG_A5XX_RB_DEPTH_CNTL 0x0000e1b1 +#define A5XX_RB_DEPTH_CNTL_Z_ENABLE 0x00000001 +#define A5XX_RB_DEPTH_CNTL_Z_WRITE_ENABLE 0x00000002 +#define A5XX_RB_DEPTH_CNTL_ZFUNC__MASK 0x0000001c +#define A5XX_RB_DEPTH_CNTL_ZFUNC__SHIFT 2 +static inline uint32_t A5XX_RB_DEPTH_CNTL_ZFUNC(enum adreno_compare_func val) +{ + return ((val) << A5XX_RB_DEPTH_CNTL_ZFUNC__SHIFT) & A5XX_RB_DEPTH_CNTL_ZFUNC__MASK; +} +#define A5XX_RB_DEPTH_CNTL_Z_TEST_ENABLE 0x00000040 + +#define REG_A5XX_RB_DEPTH_BUFFER_INFO 0x0000e1b2 +#define A5XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK 0x00000007 +#define A5XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT 0 +static inline uint32_t A5XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT(enum a5xx_depth_format val) +{ + return ((val) << A5XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT) & A5XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK; +} + +#define REG_A5XX_RB_DEPTH_BUFFER_BASE_LO 0x0000e1b3 + +#define REG_A5XX_RB_DEPTH_BUFFER_BASE_HI 0x0000e1b4 + +#define REG_A5XX_RB_DEPTH_BUFFER_PITCH 0x0000e1b5 +#define A5XX_RB_DEPTH_BUFFER_PITCH__MASK 0xffffffff +#define A5XX_RB_DEPTH_BUFFER_PITCH__SHIFT 0 +static inline uint32_t A5XX_RB_DEPTH_BUFFER_PITCH(uint32_t val) +{ + return ((val >> 5) << A5XX_RB_DEPTH_BUFFER_PITCH__SHIFT) & A5XX_RB_DEPTH_BUFFER_PITCH__MASK; +} + +#define REG_A5XX_RB_DEPTH_BUFFER_ARRAY_PITCH 0x0000e1b6 +#define A5XX_RB_DEPTH_BUFFER_ARRAY_PITCH__MASK 0xffffffff +#define A5XX_RB_DEPTH_BUFFER_ARRAY_PITCH__SHIFT 0 +static inline uint32_t A5XX_RB_DEPTH_BUFFER_ARRAY_PITCH(uint32_t val) +{ + return ((val >> 5) << A5XX_RB_DEPTH_BUFFER_ARRAY_PITCH__SHIFT) & A5XX_RB_DEPTH_BUFFER_ARRAY_PITCH__MASK; +} + +#define REG_A5XX_RB_STENCIL_CONTROL 0x0000e1c0 +#define A5XX_RB_STENCIL_CONTROL_STENCIL_ENABLE 0x00000001 +#define A5XX_RB_STENCIL_CONTROL_STENCIL_ENABLE_BF 0x00000002 +#define A5XX_RB_STENCIL_CONTROL_STENCIL_READ 0x00000004 +#define A5XX_RB_STENCIL_CONTROL_FUNC__MASK 0x00000700 +#define A5XX_RB_STENCIL_CONTROL_FUNC__SHIFT 8 +static inline uint32_t A5XX_RB_STENCIL_CONTROL_FUNC(enum adreno_compare_func val) +{ + return ((val) << A5XX_RB_STENCIL_CONTROL_FUNC__SHIFT) & A5XX_RB_STENCIL_CONTROL_FUNC__MASK; +} +#define A5XX_RB_STENCIL_CONTROL_FAIL__MASK 0x00003800 +#define A5XX_RB_STENCIL_CONTROL_FAIL__SHIFT 11 +static inline uint32_t A5XX_RB_STENCIL_CONTROL_FAIL(enum adreno_stencil_op val) +{ + return ((val) << A5XX_RB_STENCIL_CONTROL_FAIL__SHIFT) & A5XX_RB_STENCIL_CONTROL_FAIL__MASK; +} +#define A5XX_RB_STENCIL_CONTROL_ZPASS__MASK 0x0001c000 +#define A5XX_RB_STENCIL_CONTROL_ZPASS__SHIFT 14 +static inline uint32_t A5XX_RB_STENCIL_CONTROL_ZPASS(enum adreno_stencil_op val) +{ + return ((val) << A5XX_RB_STENCIL_CONTROL_ZPASS__SHIFT) & A5XX_RB_STENCIL_CONTROL_ZPASS__MASK; +} +#define A5XX_RB_STENCIL_CONTROL_ZFAIL__MASK 0x000e0000 +#define A5XX_RB_STENCIL_CONTROL_ZFAIL__SHIFT 17 +static inline uint32_t A5XX_RB_STENCIL_CONTROL_ZFAIL(enum adreno_stencil_op val) +{ + return ((val) << A5XX_RB_STENCIL_CONTROL_ZFAIL__SHIFT) & A5XX_RB_STENCIL_CONTROL_ZFAIL__MASK; +} +#define A5XX_RB_STENCIL_CONTROL_FUNC_BF__MASK 0x00700000 +#define A5XX_RB_STENCIL_CONTROL_FUNC_BF__SHIFT 20 +static inline uint32_t A5XX_RB_STENCIL_CONTROL_FUNC_BF(enum adreno_compare_func val) +{ + return ((val) << A5XX_RB_STENCIL_CONTROL_FUNC_BF__SHIFT) & A5XX_RB_STENCIL_CONTROL_FUNC_BF__MASK; +} +#define A5XX_RB_STENCIL_CONTROL_FAIL_BF__MASK 0x03800000 +#define A5XX_RB_STENCIL_CONTROL_FAIL_BF__SHIFT 23 +static inline uint32_t A5XX_RB_STENCIL_CONTROL_FAIL_BF(enum adreno_stencil_op val) +{ + return ((val) << A5XX_RB_STENCIL_CONTROL_FAIL_BF__SHIFT) & A5XX_RB_STENCIL_CONTROL_FAIL_BF__MASK; +} +#define A5XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK 0x1c000000 +#define A5XX_RB_STENCIL_CONTROL_ZPASS_BF__SHIFT 26 +static inline uint32_t A5XX_RB_STENCIL_CONTROL_ZPASS_BF(enum adreno_stencil_op val) +{ + return ((val) << A5XX_RB_STENCIL_CONTROL_ZPASS_BF__SHIFT) & A5XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK; +} +#define A5XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK 0xe0000000 +#define A5XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT 29 +static inline uint32_t A5XX_RB_STENCIL_CONTROL_ZFAIL_BF(enum adreno_stencil_op val) +{ + return ((val) << A5XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT) & A5XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK; +} + +#define REG_A5XX_RB_STENCIL_INFO 0x0000e1c2 +#define A5XX_RB_STENCIL_INFO_SEPARATE_STENCIL 0x00000001 +#define A5XX_RB_STENCIL_INFO_STENCIL_BASE__MASK 0xfffff000 +#define A5XX_RB_STENCIL_INFO_STENCIL_BASE__SHIFT 12 +static inline uint32_t A5XX_RB_STENCIL_INFO_STENCIL_BASE(uint32_t val) +{ + return ((val >> 12) << A5XX_RB_STENCIL_INFO_STENCIL_BASE__SHIFT) & A5XX_RB_STENCIL_INFO_STENCIL_BASE__MASK; +} + +#define REG_A5XX_UNKNOWN_E1C3 0x0000e1c3 + +#define REG_A5XX_RB_STENCILREFMASK 0x0000e1c6 +#define A5XX_RB_STENCILREFMASK_STENCILREF__MASK 0x000000ff +#define A5XX_RB_STENCILREFMASK_STENCILREF__SHIFT 0 +static inline uint32_t A5XX_RB_STENCILREFMASK_STENCILREF(uint32_t val) +{ + return ((val) << A5XX_RB_STENCILREFMASK_STENCILREF__SHIFT) & A5XX_RB_STENCILREFMASK_STENCILREF__MASK; +} +#define A5XX_RB_STENCILREFMASK_STENCILMASK__MASK 0x0000ff00 +#define A5XX_RB_STENCILREFMASK_STENCILMASK__SHIFT 8 +static inline uint32_t A5XX_RB_STENCILREFMASK_STENCILMASK(uint32_t val) +{ + return ((val) << A5XX_RB_STENCILREFMASK_STENCILMASK__SHIFT) & A5XX_RB_STENCILREFMASK_STENCILMASK__MASK; +} +#define A5XX_RB_STENCILREFMASK_STENCILWRITEMASK__MASK 0x00ff0000 +#define A5XX_RB_STENCILREFMASK_STENCILWRITEMASK__SHIFT 16 +static inline uint32_t A5XX_RB_STENCILREFMASK_STENCILWRITEMASK(uint32_t val) +{ + return ((val) << A5XX_RB_STENCILREFMASK_STENCILWRITEMASK__SHIFT) & A5XX_RB_STENCILREFMASK_STENCILWRITEMASK__MASK; +} + +#define REG_A5XX_RB_WINDOW_OFFSET 0x0000e1d0 +#define A5XX_RB_WINDOW_OFFSET_WINDOW_OFFSET_DISABLE 0x80000000 +#define A5XX_RB_WINDOW_OFFSET_X__MASK 0x00007fff +#define A5XX_RB_WINDOW_OFFSET_X__SHIFT 0 +static inline uint32_t A5XX_RB_WINDOW_OFFSET_X(uint32_t val) +{ + return ((val) << A5XX_RB_WINDOW_OFFSET_X__SHIFT) & A5XX_RB_WINDOW_OFFSET_X__MASK; +} +#define A5XX_RB_WINDOW_OFFSET_Y__MASK 0x7fff0000 +#define A5XX_RB_WINDOW_OFFSET_Y__SHIFT 16 +static inline uint32_t A5XX_RB_WINDOW_OFFSET_Y(uint32_t val) +{ + return ((val) << A5XX_RB_WINDOW_OFFSET_Y__SHIFT) & A5XX_RB_WINDOW_OFFSET_Y__MASK; +} + +#define REG_A5XX_RB_RESOLVE_CNTL_1 0x0000e211 +#define A5XX_RB_RESOLVE_CNTL_1_WINDOW_OFFSET_DISABLE 0x80000000 +#define A5XX_RB_RESOLVE_CNTL_1_X__MASK 0x00007fff +#define A5XX_RB_RESOLVE_CNTL_1_X__SHIFT 0 +static inline uint32_t A5XX_RB_RESOLVE_CNTL_1_X(uint32_t val) +{ + return ((val) << A5XX_RB_RESOLVE_CNTL_1_X__SHIFT) & A5XX_RB_RESOLVE_CNTL_1_X__MASK; +} +#define A5XX_RB_RESOLVE_CNTL_1_Y__MASK 0x7fff0000 +#define A5XX_RB_RESOLVE_CNTL_1_Y__SHIFT 16 +static inline uint32_t A5XX_RB_RESOLVE_CNTL_1_Y(uint32_t val) +{ + return ((val) << A5XX_RB_RESOLVE_CNTL_1_Y__SHIFT) & A5XX_RB_RESOLVE_CNTL_1_Y__MASK; +} + +#define REG_A5XX_RB_RESOLVE_CNTL_2 0x0000e212 +#define A5XX_RB_RESOLVE_CNTL_2_WINDOW_OFFSET_DISABLE 0x80000000 +#define A5XX_RB_RESOLVE_CNTL_2_X__MASK 0x00007fff +#define A5XX_RB_RESOLVE_CNTL_2_X__SHIFT 0 +static inline uint32_t A5XX_RB_RESOLVE_CNTL_2_X(uint32_t val) +{ + return ((val) << A5XX_RB_RESOLVE_CNTL_2_X__SHIFT) & A5XX_RB_RESOLVE_CNTL_2_X__MASK; +} +#define A5XX_RB_RESOLVE_CNTL_2_Y__MASK 0x7fff0000 +#define A5XX_RB_RESOLVE_CNTL_2_Y__SHIFT 16 +static inline uint32_t A5XX_RB_RESOLVE_CNTL_2_Y(uint32_t val) +{ + return ((val) << A5XX_RB_RESOLVE_CNTL_2_Y__SHIFT) & A5XX_RB_RESOLVE_CNTL_2_Y__MASK; +} + +#define REG_A5XX_RB_DEPTH_FLAG_BUFFER_BASE_LO 0x0000e240 + +#define REG_A5XX_RB_DEPTH_FLAG_BUFFER_BASE_HI 0x0000e241 + +#define REG_A5XX_RB_DEPTH_FLAG_BUFFER_PITCH 0x0000e242 + +#define REG_A5XX_VPC_CNTL_0 0x0000e280 +#define A5XX_VPC_CNTL_0_STRIDE_IN_VPC__MASK 0x0000007f +#define A5XX_VPC_CNTL_0_STRIDE_IN_VPC__SHIFT 0 +static inline uint32_t A5XX_VPC_CNTL_0_STRIDE_IN_VPC(uint32_t val) +{ + return ((val) << A5XX_VPC_CNTL_0_STRIDE_IN_VPC__SHIFT) & A5XX_VPC_CNTL_0_STRIDE_IN_VPC__MASK; +} + +static inline uint32_t REG_A5XX_VPC_VARYING_INTERP(uint32_t i0) { return 0x0000e282 + 0x1*i0; } + +static inline uint32_t REG_A5XX_VPC_VARYING_INTERP_MODE(uint32_t i0) { return 0x0000e282 + 0x1*i0; } + +static inline uint32_t REG_A5XX_VPC_VARYING_PS_REPL(uint32_t i0) { return 0x0000e28a + 0x1*i0; } + +static inline uint32_t REG_A5XX_VPC_VARYING_PS_REPL_MODE(uint32_t i0) { return 0x0000e28a + 0x1*i0; } + +static inline uint32_t REG_A5XX_VPC_VAR(uint32_t i0) { return 0x0000e294 + 0x1*i0; } + +static inline uint32_t REG_A5XX_VPC_VAR_DISABLE(uint32_t i0) { return 0x0000e294 + 0x1*i0; } + +#define REG_A5XX_VPC_GS_SIV_CNTL 0x0000e298 + +#define REG_A5XX_VPC_PACK 0x0000e29d +#define A5XX_VPC_PACK_NUMNONPOSVAR__MASK 0x000000ff +#define A5XX_VPC_PACK_NUMNONPOSVAR__SHIFT 0 +static inline uint32_t A5XX_VPC_PACK_NUMNONPOSVAR(uint32_t val) +{ + return ((val) << A5XX_VPC_PACK_NUMNONPOSVAR__SHIFT) & A5XX_VPC_PACK_NUMNONPOSVAR__MASK; +} + +#define REG_A5XX_VPC_FS_PRIMITIVEID_CNTL 0x0000e2a0 + +#define REG_A5XX_VPC_SO_OVERRIDE 0x0000e2a2 + +#define REG_A5XX_VPC_SO_BUFFER_BASE_LO_0 0x0000e2a7 + +#define REG_A5XX_VPC_SO_BUFFER_BASE_HI_0 0x0000e2a8 + +#define REG_A5XX_VPC_SO_BUFFER_SIZE_0 0x0000e2a9 + +#define REG_A5XX_VPC_SO_FLUSH_BASE_LO_0 0x0000e2ac + +#define REG_A5XX_VPC_SO_FLUSH_BASE_HI_0 0x0000e2ad + +#define REG_A5XX_PC_PRIMITIVE_CNTL 0x0000e384 +#define A5XX_PC_PRIMITIVE_CNTL_STRIDE_IN_VPC__MASK 0x0000007f +#define A5XX_PC_PRIMITIVE_CNTL_STRIDE_IN_VPC__SHIFT 0 +static inline uint32_t A5XX_PC_PRIMITIVE_CNTL_STRIDE_IN_VPC(uint32_t val) +{ + return ((val) << A5XX_PC_PRIMITIVE_CNTL_STRIDE_IN_VPC__SHIFT) & A5XX_PC_PRIMITIVE_CNTL_STRIDE_IN_VPC__MASK; +} + +#define REG_A5XX_PC_RASTER_CNTL 0x0000e388 + +#define REG_A5XX_PC_RESTART_INDEX 0x0000e38c + +#define REG_A5XX_PC_GS_PARAM 0x0000e38e + +#define REG_A5XX_PC_HS_PARAM 0x0000e38f + +#define REG_A5XX_PC_POWER_CNTL 0x0000e3b0 + +#define REG_A5XX_VFD_CONTROL_0 0x0000e400 +#define A5XX_VFD_CONTROL_0_STRMDECINSTRCNT__MASK 0x0000003f +#define A5XX_VFD_CONTROL_0_STRMDECINSTRCNT__SHIFT 0 +static inline uint32_t A5XX_VFD_CONTROL_0_STRMDECINSTRCNT(uint32_t val) +{ + return ((val) << A5XX_VFD_CONTROL_0_STRMDECINSTRCNT__SHIFT) & A5XX_VFD_CONTROL_0_STRMDECINSTRCNT__MASK; +} + +#define REG_A5XX_VFD_CONTROL_1 0x0000e401 +#define A5XX_VFD_CONTROL_1_REGID4INST__MASK 0x0000ff00 +#define A5XX_VFD_CONTROL_1_REGID4INST__SHIFT 8 +static inline uint32_t A5XX_VFD_CONTROL_1_REGID4INST(uint32_t val) +{ + return ((val) << A5XX_VFD_CONTROL_1_REGID4INST__SHIFT) & A5XX_VFD_CONTROL_1_REGID4INST__MASK; +} +#define A5XX_VFD_CONTROL_1_REGID4VTX__MASK 0x00ff0000 +#define A5XX_VFD_CONTROL_1_REGID4VTX__SHIFT 16 +static inline uint32_t A5XX_VFD_CONTROL_1_REGID4VTX(uint32_t val) +{ + return ((val) << A5XX_VFD_CONTROL_1_REGID4VTX__SHIFT) & A5XX_VFD_CONTROL_1_REGID4VTX__MASK; +} + +#define REG_A5XX_VFD_CONTROL_2 0x0000e402 + +#define REG_A5XX_VFD_CONTROL_3 0x0000e403 + +#define REG_A5XX_VFD_CONTROL_4 0x0000e404 + +#define REG_A5XX_VFD_CONTROL_5 0x0000e405 + +#define REG_A5XX_VFD_INDEX_OFFSET 0x0000e408 + +#define REG_A5XX_VFD_INSTANCE_START_OFFSET 0x0000e409 + +static inline uint32_t REG_A5XX_VFD_FETCH(uint32_t i0) { return 0x0000e40a + 0x4*i0; } + +static inline uint32_t REG_A5XX_VFD_FETCH_BASE_LO(uint32_t i0) { return 0x0000e40a + 0x4*i0; } + +static inline uint32_t REG_A5XX_VFD_FETCH_BASE_HI(uint32_t i0) { return 0x0000e40b + 0x4*i0; } + +static inline uint32_t REG_A5XX_VFD_FETCH_SIZE(uint32_t i0) { return 0x0000e40c + 0x4*i0; } + +static inline uint32_t REG_A5XX_VFD_FETCH_STRIDE(uint32_t i0) { return 0x0000e40d + 0x4*i0; } + +static inline uint32_t REG_A5XX_VFD_DECODE(uint32_t i0) { return 0x0000e48a + 0x2*i0; } + +static inline uint32_t REG_A5XX_VFD_DECODE_INSTR(uint32_t i0) { return 0x0000e48a + 0x2*i0; } +#define A5XX_VFD_DECODE_INSTR_IDX__MASK 0x0000001f +#define A5XX_VFD_DECODE_INSTR_IDX__SHIFT 0 +static inline uint32_t A5XX_VFD_DECODE_INSTR_IDX(uint32_t val) +{ + return ((val) << A5XX_VFD_DECODE_INSTR_IDX__SHIFT) & A5XX_VFD_DECODE_INSTR_IDX__MASK; +} +#define A5XX_VFD_DECODE_INSTR_FORMAT__MASK 0x3ff00000 +#define A5XX_VFD_DECODE_INSTR_FORMAT__SHIFT 20 +static inline uint32_t A5XX_VFD_DECODE_INSTR_FORMAT(enum a5xx_vtx_fmt val) +{ + return ((val) << A5XX_VFD_DECODE_INSTR_FORMAT__SHIFT) & A5XX_VFD_DECODE_INSTR_FORMAT__MASK; +} + +static inline uint32_t REG_A5XX_VFD_DECODE_STEP_RATE(uint32_t i0) { return 0x0000e48b + 0x2*i0; } + +static inline uint32_t REG_A5XX_VFD_DEST_CNTL(uint32_t i0) { return 0x0000e4ca + 0x1*i0; } + +static inline uint32_t REG_A5XX_VFD_DEST_CNTL_INSTR(uint32_t i0) { return 0x0000e4ca + 0x1*i0; } +#define A5XX_VFD_DEST_CNTL_INSTR_WRITEMASK__MASK 0x0000000f +#define A5XX_VFD_DEST_CNTL_INSTR_WRITEMASK__SHIFT 0 +static inline uint32_t A5XX_VFD_DEST_CNTL_INSTR_WRITEMASK(uint32_t val) +{ + return ((val) << A5XX_VFD_DEST_CNTL_INSTR_WRITEMASK__SHIFT) & A5XX_VFD_DEST_CNTL_INSTR_WRITEMASK__MASK; +} +#define A5XX_VFD_DEST_CNTL_INSTR_REGID__MASK 0x00000ff0 +#define A5XX_VFD_DEST_CNTL_INSTR_REGID__SHIFT 4 +static inline uint32_t A5XX_VFD_DEST_CNTL_INSTR_REGID(uint32_t val) +{ + return ((val) << A5XX_VFD_DEST_CNTL_INSTR_REGID__SHIFT) & A5XX_VFD_DEST_CNTL_INSTR_REGID__MASK; +} + +#define REG_A5XX_VFD_POWER_CNTL 0x0000e4f0 + +#define REG_A5XX_SP_SP_CNTL 0x0000e580 + +#define REG_A5XX_SP_VS_CONTROL_REG 0x0000e584 +#define A5XX_SP_VS_CONTROL_REG_ENABLED 0x00000001 +#define A5XX_SP_VS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x000000fe +#define A5XX_SP_VS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT 1 +static inline uint32_t A5XX_SP_VS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val) +{ + return ((val) << A5XX_SP_VS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A5XX_SP_VS_CONTROL_REG_CONSTOBJECTOFFSET__MASK; +} +#define A5XX_SP_VS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00007f00 +#define A5XX_SP_VS_CONTROL_REG_SHADEROBJOFFSET__SHIFT 8 +static inline uint32_t A5XX_SP_VS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val) +{ + return ((val) << A5XX_SP_VS_CONTROL_REG_SHADEROBJOFFSET__SHIFT) & A5XX_SP_VS_CONTROL_REG_SHADEROBJOFFSET__MASK; +} + +#define REG_A5XX_SP_FS_CONTROL_REG 0x0000e585 +#define A5XX_SP_FS_CONTROL_REG_ENABLED 0x00000001 +#define A5XX_SP_FS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x000000fe +#define A5XX_SP_FS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT 1 +static inline uint32_t A5XX_SP_FS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val) +{ + return ((val) << A5XX_SP_FS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A5XX_SP_FS_CONTROL_REG_CONSTOBJECTOFFSET__MASK; +} +#define A5XX_SP_FS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00007f00 +#define A5XX_SP_FS_CONTROL_REG_SHADEROBJOFFSET__SHIFT 8 +static inline uint32_t A5XX_SP_FS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val) +{ + return ((val) << A5XX_SP_FS_CONTROL_REG_SHADEROBJOFFSET__SHIFT) & A5XX_SP_FS_CONTROL_REG_SHADEROBJOFFSET__MASK; +} + +#define REG_A5XX_SP_HS_CONTROL_REG 0x0000e586 +#define A5XX_SP_HS_CONTROL_REG_ENABLED 0x00000001 +#define A5XX_SP_HS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x000000fe +#define A5XX_SP_HS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT 1 +static inline uint32_t A5XX_SP_HS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val) +{ + return ((val) << A5XX_SP_HS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A5XX_SP_HS_CONTROL_REG_CONSTOBJECTOFFSET__MASK; +} +#define A5XX_SP_HS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00007f00 +#define A5XX_SP_HS_CONTROL_REG_SHADEROBJOFFSET__SHIFT 8 +static inline uint32_t A5XX_SP_HS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val) +{ + return ((val) << A5XX_SP_HS_CONTROL_REG_SHADEROBJOFFSET__SHIFT) & A5XX_SP_HS_CONTROL_REG_SHADEROBJOFFSET__MASK; +} + +#define REG_A5XX_SP_DS_CONTROL_REG 0x0000e587 +#define A5XX_SP_DS_CONTROL_REG_ENABLED 0x00000001 +#define A5XX_SP_DS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x000000fe +#define A5XX_SP_DS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT 1 +static inline uint32_t A5XX_SP_DS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val) +{ + return ((val) << A5XX_SP_DS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A5XX_SP_DS_CONTROL_REG_CONSTOBJECTOFFSET__MASK; +} +#define A5XX_SP_DS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00007f00 +#define A5XX_SP_DS_CONTROL_REG_SHADEROBJOFFSET__SHIFT 8 +static inline uint32_t A5XX_SP_DS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val) +{ + return ((val) << A5XX_SP_DS_CONTROL_REG_SHADEROBJOFFSET__SHIFT) & A5XX_SP_DS_CONTROL_REG_SHADEROBJOFFSET__MASK; +} + +#define REG_A5XX_SP_GS_CONTROL_REG 0x0000e588 +#define A5XX_SP_GS_CONTROL_REG_ENABLED 0x00000001 +#define A5XX_SP_GS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x000000fe +#define A5XX_SP_GS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT 1 +static inline uint32_t A5XX_SP_GS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val) +{ + return ((val) << A5XX_SP_GS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A5XX_SP_GS_CONTROL_REG_CONSTOBJECTOFFSET__MASK; +} +#define A5XX_SP_GS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00007f00 +#define A5XX_SP_GS_CONTROL_REG_SHADEROBJOFFSET__SHIFT 8 +static inline uint32_t A5XX_SP_GS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val) +{ + return ((val) << A5XX_SP_GS_CONTROL_REG_SHADEROBJOFFSET__SHIFT) & A5XX_SP_GS_CONTROL_REG_SHADEROBJOFFSET__MASK; +} + +#define REG_A5XX_SP_CS_CONFIG 0x0000e589 + +#define REG_A5XX_SP_VS_CONFIG_MAX_CONST 0x0000e58a + +#define REG_A5XX_SP_FS_CONFIG_MAX_CONST 0x0000e58b + +#define REG_A5XX_SP_VS_CTRL_REG0 0x0000e590 +#define A5XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x000003f0 +#define A5XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 4 +static inline uint32_t A5XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) +{ + return ((val) << A5XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A5XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK; +} +#define A5XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x0000fc00 +#define A5XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 10 +static inline uint32_t A5XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) +{ + return ((val) << A5XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A5XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK; +} +#define A5XX_SP_VS_CTRL_REG0_VARYING 0x00010000 +#define A5XX_SP_VS_CTRL_REG0_PIXLODENABLE 0x00100000 + +static inline uint32_t REG_A5XX_SP_VS_OUT(uint32_t i0) { return 0x0000e593 + 0x1*i0; } + +static inline uint32_t REG_A5XX_SP_VS_OUT_REG(uint32_t i0) { return 0x0000e593 + 0x1*i0; } +#define A5XX_SP_VS_OUT_REG_A_REGID__MASK 0x000000ff +#define A5XX_SP_VS_OUT_REG_A_REGID__SHIFT 0 +static inline uint32_t A5XX_SP_VS_OUT_REG_A_REGID(uint32_t val) +{ + return ((val) << A5XX_SP_VS_OUT_REG_A_REGID__SHIFT) & A5XX_SP_VS_OUT_REG_A_REGID__MASK; +} +#define A5XX_SP_VS_OUT_REG_A_COMPMASK__MASK 0x00000f00 +#define A5XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT 8 +static inline uint32_t A5XX_SP_VS_OUT_REG_A_COMPMASK(uint32_t val) +{ + return ((val) << A5XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT) & A5XX_SP_VS_OUT_REG_A_COMPMASK__MASK; +} +#define A5XX_SP_VS_OUT_REG_B_REGID__MASK 0x00ff0000 +#define A5XX_SP_VS_OUT_REG_B_REGID__SHIFT 16 +static inline uint32_t A5XX_SP_VS_OUT_REG_B_REGID(uint32_t val) +{ + return ((val) << A5XX_SP_VS_OUT_REG_B_REGID__SHIFT) & A5XX_SP_VS_OUT_REG_B_REGID__MASK; +} +#define A5XX_SP_VS_OUT_REG_B_COMPMASK__MASK 0x0f000000 +#define A5XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT 24 +static inline uint32_t A5XX_SP_VS_OUT_REG_B_COMPMASK(uint32_t val) +{ + return ((val) << A5XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT) & A5XX_SP_VS_OUT_REG_B_COMPMASK__MASK; +} + +static inline uint32_t REG_A5XX_SP_VS_VPC_DST(uint32_t i0) { return 0x0000e5a3 + 0x1*i0; } + +static inline uint32_t REG_A5XX_SP_VS_VPC_DST_REG(uint32_t i0) { return 0x0000e5a3 + 0x1*i0; } +#define A5XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK 0x000000ff +#define A5XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT 0 +static inline uint32_t A5XX_SP_VS_VPC_DST_REG_OUTLOC0(uint32_t val) +{ + return ((val) << A5XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT) & A5XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK; +} +#define A5XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK 0x0000ff00 +#define A5XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT 8 +static inline uint32_t A5XX_SP_VS_VPC_DST_REG_OUTLOC1(uint32_t val) +{ + return ((val) << A5XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT) & A5XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK; +} +#define A5XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK 0x00ff0000 +#define A5XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT 16 +static inline uint32_t A5XX_SP_VS_VPC_DST_REG_OUTLOC2(uint32_t val) +{ + return ((val) << A5XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT) & A5XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK; +} +#define A5XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK 0xff000000 +#define A5XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT 24 +static inline uint32_t A5XX_SP_VS_VPC_DST_REG_OUTLOC3(uint32_t val) +{ + return ((val) << A5XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT) & A5XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK; +} + +#define REG_A5XX_SP_VS_OBJ_START_LO 0x0000e5ac + +#define REG_A5XX_SP_VS_OBJ_START_HI 0x0000e5ad + +#define REG_A5XX_SP_FS_CTRL_REG0 0x0000e5c0 +#define A5XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x000003f0 +#define A5XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 4 +static inline uint32_t A5XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) +{ + return ((val) << A5XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A5XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK; +} +#define A5XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x0000fc00 +#define A5XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 10 +static inline uint32_t A5XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) +{ + return ((val) << A5XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A5XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK; +} +#define A5XX_SP_FS_CTRL_REG0_VARYING 0x00010000 +#define A5XX_SP_FS_CTRL_REG0_PIXLODENABLE 0x00100000 + +#define REG_A5XX_SP_FS_OBJ_START_LO 0x0000e5c3 + +#define REG_A5XX_SP_FS_OBJ_START_HI 0x0000e5c4 + +#define REG_A5XX_SP_BLEND_CNTL 0x0000e5c9 + +#define REG_A5XX_SP_FS_OUTPUT_CNTL 0x0000e5ca +#define A5XX_SP_FS_OUTPUT_CNTL_MRT__MASK 0x0000000f +#define A5XX_SP_FS_OUTPUT_CNTL_MRT__SHIFT 0 +static inline uint32_t A5XX_SP_FS_OUTPUT_CNTL_MRT(uint32_t val) +{ + return ((val) << A5XX_SP_FS_OUTPUT_CNTL_MRT__SHIFT) & A5XX_SP_FS_OUTPUT_CNTL_MRT__MASK; +} +#define A5XX_SP_FS_OUTPUT_CNTL_DEPTH_REGID__MASK 0x00001fe0 +#define A5XX_SP_FS_OUTPUT_CNTL_DEPTH_REGID__SHIFT 5 +static inline uint32_t A5XX_SP_FS_OUTPUT_CNTL_DEPTH_REGID(uint32_t val) +{ + return ((val) << A5XX_SP_FS_OUTPUT_CNTL_DEPTH_REGID__SHIFT) & A5XX_SP_FS_OUTPUT_CNTL_DEPTH_REGID__MASK; +} +#define A5XX_SP_FS_OUTPUT_CNTL_SAMPLEMASK_REGID__MASK 0x001fe000 +#define A5XX_SP_FS_OUTPUT_CNTL_SAMPLEMASK_REGID__SHIFT 13 +static inline uint32_t A5XX_SP_FS_OUTPUT_CNTL_SAMPLEMASK_REGID(uint32_t val) +{ + return ((val) << A5XX_SP_FS_OUTPUT_CNTL_SAMPLEMASK_REGID__SHIFT) & A5XX_SP_FS_OUTPUT_CNTL_SAMPLEMASK_REGID__MASK; +} + +static inline uint32_t REG_A5XX_SP_FS_OUTPUT(uint32_t i0) { return 0x0000e5cb + 0x1*i0; } + +static inline uint32_t REG_A5XX_SP_FS_OUTPUT_REG(uint32_t i0) { return 0x0000e5cb + 0x1*i0; } +#define A5XX_SP_FS_OUTPUT_REG_REGID__MASK 0x000000ff +#define A5XX_SP_FS_OUTPUT_REG_REGID__SHIFT 0 +static inline uint32_t A5XX_SP_FS_OUTPUT_REG_REGID(uint32_t val) +{ + return ((val) << A5XX_SP_FS_OUTPUT_REG_REGID__SHIFT) & A5XX_SP_FS_OUTPUT_REG_REGID__MASK; +} +#define A5XX_SP_FS_OUTPUT_REG_HALF_PRECISION 0x00000100 + +static inline uint32_t REG_A5XX_SP_FS_MRT(uint32_t i0) { return 0x0000e5d3 + 0x1*i0; } + +static inline uint32_t REG_A5XX_SP_FS_MRT_REG(uint32_t i0) { return 0x0000e5d3 + 0x1*i0; } +#define A5XX_SP_FS_MRT_REG_COLOR_FORMAT__MASK 0x0000007f +#define A5XX_SP_FS_MRT_REG_COLOR_FORMAT__SHIFT 0 +static inline uint32_t A5XX_SP_FS_MRT_REG_COLOR_FORMAT(enum a5xx_color_fmt val) +{ + return ((val) << A5XX_SP_FS_MRT_REG_COLOR_FORMAT__SHIFT) & A5XX_SP_FS_MRT_REG_COLOR_FORMAT__MASK; +} + +#define REG_A5XX_SP_CS_CNTL_0 0x0000e5f0 + +#define REG_A5XX_TPL1_TP_RAS_MSAA_CNTL 0x0000e704 + +#define REG_A5XX_TPL1_TP_DEST_MSAA_CNTL 0x0000e705 + +#define REG_A5XX_TPL1_VS_TEX_SAMP_LO 0x0000e722 + +#define REG_A5XX_TPL1_VS_TEX_SAMP_HI 0x0000e723 + +#define REG_A5XX_TPL1_VS_TEX_CONST_LO 0x0000e72a + +#define REG_A5XX_TPL1_VS_TEX_CONST_HI 0x0000e72b + +#define REG_A5XX_TPL1_FS_TEX_CONST_LO 0x0000e75a + +#define REG_A5XX_TPL1_FS_TEX_CONST_HI 0x0000e75b + +#define REG_A5XX_TPL1_FS_TEX_SAMP_LO 0x0000e75e + +#define REG_A5XX_TPL1_FS_TEX_SAMP_HI 0x0000e75f + +#define REG_A5XX_TPL1_TP_FS_ROTATION_CNTL 0x0000e764 + +#define REG_A5XX_HLSQ_CONTROL_0_REG 0x0000e784 + +#define REG_A5XX_HLSQ_CONTROL_1_REG 0x0000e785 + +#define REG_A5XX_HLSQ_CONTROL_2_REG 0x0000e786 +#define A5XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK 0x000000ff +#define A5XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT 0 +static inline uint32_t A5XX_HLSQ_CONTROL_2_REG_FACEREGID(uint32_t val) +{ + return ((val) << A5XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT) & A5XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK; +} + +#define REG_A5XX_HLSQ_CONTROL_3_REG 0x0000e787 +#define A5XX_HLSQ_CONTROL_3_REG_REGID__MASK 0x000000ff +#define A5XX_HLSQ_CONTROL_3_REG_REGID__SHIFT 0 +static inline uint32_t A5XX_HLSQ_CONTROL_3_REG_REGID(uint32_t val) +{ + return ((val) << A5XX_HLSQ_CONTROL_3_REG_REGID__SHIFT) & A5XX_HLSQ_CONTROL_3_REG_REGID__MASK; +} + +#define REG_A5XX_HLSQ_CONTROL_4_REG 0x0000e788 +#define A5XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__MASK 0x00ff0000 +#define A5XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__SHIFT 16 +static inline uint32_t A5XX_HLSQ_CONTROL_4_REG_XYCOORDREGID(uint32_t val) +{ + return ((val) << A5XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__SHIFT) & A5XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__MASK; +} +#define A5XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__MASK 0xff000000 +#define A5XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__SHIFT 24 +static inline uint32_t A5XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID(uint32_t val) +{ + return ((val) << A5XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__SHIFT) & A5XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__MASK; +} + +#define REG_A5XX_HLSQ_UPDATE_CNTL 0x0000e78a + +#define REG_A5XX_HLSQ_VS_CONTROL_REG 0x0000e78b +#define A5XX_HLSQ_VS_CONTROL_REG_ENABLED 0x00000001 +#define A5XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x000000fe +#define A5XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT 1 +static inline uint32_t A5XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val) +{ + return ((val) << A5XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A5XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET__MASK; +} +#define A5XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00007f00 +#define A5XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET__SHIFT 8 +static inline uint32_t A5XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val) +{ + return ((val) << A5XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET__SHIFT) & A5XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET__MASK; +} + +#define REG_A5XX_HLSQ_FS_CONTROL_REG 0x0000e78c +#define A5XX_HLSQ_FS_CONTROL_REG_ENABLED 0x00000001 +#define A5XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x000000fe +#define A5XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT 1 +static inline uint32_t A5XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val) +{ + return ((val) << A5XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A5XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET__MASK; +} +#define A5XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00007f00 +#define A5XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET__SHIFT 8 +static inline uint32_t A5XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val) +{ + return ((val) << A5XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET__SHIFT) & A5XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET__MASK; +} + +#define REG_A5XX_HLSQ_HS_CONTROL_REG 0x0000e78d +#define A5XX_HLSQ_HS_CONTROL_REG_ENABLED 0x00000001 +#define A5XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x000000fe +#define A5XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT 1 +static inline uint32_t A5XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val) +{ + return ((val) << A5XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A5XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET__MASK; +} +#define A5XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00007f00 +#define A5XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET__SHIFT 8 +static inline uint32_t A5XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val) +{ + return ((val) << A5XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET__SHIFT) & A5XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET__MASK; +} + +#define REG_A5XX_HLSQ_DS_CONTROL_REG 0x0000e78e +#define A5XX_HLSQ_DS_CONTROL_REG_ENABLED 0x00000001 +#define A5XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x000000fe +#define A5XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT 1 +static inline uint32_t A5XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val) +{ + return ((val) << A5XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A5XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET__MASK; +} +#define A5XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00007f00 +#define A5XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET__SHIFT 8 +static inline uint32_t A5XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val) +{ + return ((val) << A5XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET__SHIFT) & A5XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET__MASK; +} + +#define REG_A5XX_HLSQ_GS_CONTROL_REG 0x0000e78f +#define A5XX_HLSQ_GS_CONTROL_REG_ENABLED 0x00000001 +#define A5XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x000000fe +#define A5XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT 1 +static inline uint32_t A5XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val) +{ + return ((val) << A5XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A5XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET__MASK; +} +#define A5XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00007f00 +#define A5XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET__SHIFT 8 +static inline uint32_t A5XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val) +{ + return ((val) << A5XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET__SHIFT) & A5XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET__MASK; +} + +#define REG_A5XX_HLSQ_CS_CONFIG 0x0000e790 + +#define REG_A5XX_HLSQ_VS_CNTL 0x0000e791 + +#define REG_A5XX_HLSQ_FS_CNTL 0x0000e792 + +#define REG_A5XX_HLSQ_CS_CNTL 0x0000e796 + +#define REG_A5XX_HLSQ_CS_KERNEL_GROUP_X 0x0000e7b9 + +#define REG_A5XX_HLSQ_CS_KERNEL_GROUP_Y 0x0000e7ba + +#define REG_A5XX_HLSQ_CS_KERNEL_GROUP_Z 0x0000e7bb + +#define REG_A5XX_HLSQ_CS_NDRANGE_0 0x0000e7b0 + +#define REG_A5XX_HLSQ_CS_NDRANGE_1 0x0000e7b1 + +#define REG_A5XX_HLSQ_CS_NDRANGE_2 0x0000e7b2 + +#define REG_A5XX_HLSQ_CS_NDRANGE_3 0x0000e7b3 + +#define REG_A5XX_HLSQ_CS_NDRANGE_4 0x0000e7b4 + +#define REG_A5XX_HLSQ_CS_NDRANGE_5 0x0000e7b5 + +#define REG_A5XX_HLSQ_CS_NDRANGE_6 0x0000e7b6 + +#define REG_A5XX_HLSQ_CS_CNTL_0 0x0000e7b7 + +#define REG_A5XX_HLSQ_CS_CNTL_1 0x0000e7b8 + +#define REG_A5XX_HLSQ_VS_CONSTLEN 0x0000e7c3 + +#define REG_A5XX_HLSQ_VS_INSTRLEN 0x0000e7c4 + +#define REG_A5XX_HLSQ_FS_CONSTLEN 0x0000e7d7 + +#define REG_A5XX_HLSQ_FS_INSTRLEN 0x0000e7d8 + +#define REG_A5XX_HLSQ_CONTEXT_SWITCH_CS_SW_3 0x0000e7dc + +#define REG_A5XX_HLSQ_CONTEXT_SWITCH_CS_SW_4 0x0000e7dd + +#define REG_A5XX_TEX_SAMP_0 0x00000000 +#define A5XX_TEX_SAMP_0_MIPFILTER_LINEAR_NEAR 0x00000001 +#define A5XX_TEX_SAMP_0_XY_MAG__MASK 0x00000006 +#define A5XX_TEX_SAMP_0_XY_MAG__SHIFT 1 +static inline uint32_t A5XX_TEX_SAMP_0_XY_MAG(enum a5xx_tex_filter val) +{ + return ((val) << A5XX_TEX_SAMP_0_XY_MAG__SHIFT) & A5XX_TEX_SAMP_0_XY_MAG__MASK; +} +#define A5XX_TEX_SAMP_0_XY_MIN__MASK 0x00000018 +#define A5XX_TEX_SAMP_0_XY_MIN__SHIFT 3 +static inline uint32_t A5XX_TEX_SAMP_0_XY_MIN(enum a5xx_tex_filter val) +{ + return ((val) << A5XX_TEX_SAMP_0_XY_MIN__SHIFT) & A5XX_TEX_SAMP_0_XY_MIN__MASK; +} +#define A5XX_TEX_SAMP_0_WRAP_S__MASK 0x000000e0 +#define A5XX_TEX_SAMP_0_WRAP_S__SHIFT 5 +static inline uint32_t A5XX_TEX_SAMP_0_WRAP_S(enum a5xx_tex_clamp val) +{ + return ((val) << A5XX_TEX_SAMP_0_WRAP_S__SHIFT) & A5XX_TEX_SAMP_0_WRAP_S__MASK; +} +#define A5XX_TEX_SAMP_0_WRAP_T__MASK 0x00000700 +#define A5XX_TEX_SAMP_0_WRAP_T__SHIFT 8 +static inline uint32_t A5XX_TEX_SAMP_0_WRAP_T(enum a5xx_tex_clamp val) +{ + return ((val) << A5XX_TEX_SAMP_0_WRAP_T__SHIFT) & A5XX_TEX_SAMP_0_WRAP_T__MASK; +} +#define A5XX_TEX_SAMP_0_WRAP_R__MASK 0x00003800 +#define A5XX_TEX_SAMP_0_WRAP_R__SHIFT 11 +static inline uint32_t A5XX_TEX_SAMP_0_WRAP_R(enum a5xx_tex_clamp val) +{ + return ((val) << A5XX_TEX_SAMP_0_WRAP_R__SHIFT) & A5XX_TEX_SAMP_0_WRAP_R__MASK; +} +#define A5XX_TEX_SAMP_0_ANISO__MASK 0x0001c000 +#define A5XX_TEX_SAMP_0_ANISO__SHIFT 14 +static inline uint32_t A5XX_TEX_SAMP_0_ANISO(enum a5xx_tex_aniso val) +{ + return ((val) << A5XX_TEX_SAMP_0_ANISO__SHIFT) & A5XX_TEX_SAMP_0_ANISO__MASK; +} +#define A5XX_TEX_SAMP_0_LOD_BIAS__MASK 0xfff80000 +#define A5XX_TEX_SAMP_0_LOD_BIAS__SHIFT 19 +static inline uint32_t A5XX_TEX_SAMP_0_LOD_BIAS(float val) +{ + return ((((int32_t)(val * 256.0))) << A5XX_TEX_SAMP_0_LOD_BIAS__SHIFT) & A5XX_TEX_SAMP_0_LOD_BIAS__MASK; +} + +#define REG_A5XX_TEX_SAMP_1 0x00000001 +#define A5XX_TEX_SAMP_1_COMPARE_FUNC__MASK 0x0000000e +#define A5XX_TEX_SAMP_1_COMPARE_FUNC__SHIFT 1 +static inline uint32_t A5XX_TEX_SAMP_1_COMPARE_FUNC(enum adreno_compare_func val) +{ + return ((val) << A5XX_TEX_SAMP_1_COMPARE_FUNC__SHIFT) & A5XX_TEX_SAMP_1_COMPARE_FUNC__MASK; +} +#define A5XX_TEX_SAMP_1_CUBEMAPSEAMLESSFILTOFF 0x00000010 +#define A5XX_TEX_SAMP_1_UNNORM_COORDS 0x00000020 +#define A5XX_TEX_SAMP_1_MIPFILTER_LINEAR_FAR 0x00000040 +#define A5XX_TEX_SAMP_1_MAX_LOD__MASK 0x000fff00 +#define A5XX_TEX_SAMP_1_MAX_LOD__SHIFT 8 +static inline uint32_t A5XX_TEX_SAMP_1_MAX_LOD(float val) +{ + return ((((uint32_t)(val * 256.0))) << A5XX_TEX_SAMP_1_MAX_LOD__SHIFT) & A5XX_TEX_SAMP_1_MAX_LOD__MASK; +} +#define A5XX_TEX_SAMP_1_MIN_LOD__MASK 0xfff00000 +#define A5XX_TEX_SAMP_1_MIN_LOD__SHIFT 20 +static inline uint32_t A5XX_TEX_SAMP_1_MIN_LOD(float val) +{ + return ((((uint32_t)(val * 256.0))) << A5XX_TEX_SAMP_1_MIN_LOD__SHIFT) & A5XX_TEX_SAMP_1_MIN_LOD__MASK; +} + +#define REG_A5XX_TEX_SAMP_2 0x00000002 + +#define REG_A5XX_TEX_SAMP_3 0x00000003 + +#define REG_A5XX_TEX_CONST_0 0x00000000 +#define A5XX_TEX_CONST_0_TILED 0x00000001 +#define A5XX_TEX_CONST_0_SRGB 0x00000004 +#define A5XX_TEX_CONST_0_SWIZ_X__MASK 0x00000070 +#define A5XX_TEX_CONST_0_SWIZ_X__SHIFT 4 +static inline uint32_t A5XX_TEX_CONST_0_SWIZ_X(enum a5xx_tex_swiz val) +{ + return ((val) << A5XX_TEX_CONST_0_SWIZ_X__SHIFT) & A5XX_TEX_CONST_0_SWIZ_X__MASK; +} +#define A5XX_TEX_CONST_0_SWIZ_Y__MASK 0x00000380 +#define A5XX_TEX_CONST_0_SWIZ_Y__SHIFT 7 +static inline uint32_t A5XX_TEX_CONST_0_SWIZ_Y(enum a5xx_tex_swiz val) +{ + return ((val) << A5XX_TEX_CONST_0_SWIZ_Y__SHIFT) & A5XX_TEX_CONST_0_SWIZ_Y__MASK; +} +#define A5XX_TEX_CONST_0_SWIZ_Z__MASK 0x00001c00 +#define A5XX_TEX_CONST_0_SWIZ_Z__SHIFT 10 +static inline uint32_t A5XX_TEX_CONST_0_SWIZ_Z(enum a5xx_tex_swiz val) +{ + return ((val) << A5XX_TEX_CONST_0_SWIZ_Z__SHIFT) & A5XX_TEX_CONST_0_SWIZ_Z__MASK; +} +#define A5XX_TEX_CONST_0_SWIZ_W__MASK 0x0000e000 +#define A5XX_TEX_CONST_0_SWIZ_W__SHIFT 13 +static inline uint32_t A5XX_TEX_CONST_0_SWIZ_W(enum a5xx_tex_swiz val) +{ + return ((val) << A5XX_TEX_CONST_0_SWIZ_W__SHIFT) & A5XX_TEX_CONST_0_SWIZ_W__MASK; +} +#define A5XX_TEX_CONST_0_FMT__MASK 0x3fc00000 +#define A5XX_TEX_CONST_0_FMT__SHIFT 22 +static inline uint32_t A5XX_TEX_CONST_0_FMT(enum a5xx_tex_fmt val) +{ + return ((val) << A5XX_TEX_CONST_0_FMT__SHIFT) & A5XX_TEX_CONST_0_FMT__MASK; +} + +#define REG_A5XX_TEX_CONST_1 0x00000001 +#define A5XX_TEX_CONST_1_WIDTH__MASK 0x00007fff +#define A5XX_TEX_CONST_1_WIDTH__SHIFT 0 +static inline uint32_t A5XX_TEX_CONST_1_WIDTH(uint32_t val) +{ + return ((val) << A5XX_TEX_CONST_1_WIDTH__SHIFT) & A5XX_TEX_CONST_1_WIDTH__MASK; +} +#define A5XX_TEX_CONST_1_HEIGHT__MASK 0x3fff8000 +#define A5XX_TEX_CONST_1_HEIGHT__SHIFT 15 +static inline uint32_t A5XX_TEX_CONST_1_HEIGHT(uint32_t val) +{ + return ((val) << A5XX_TEX_CONST_1_HEIGHT__SHIFT) & A5XX_TEX_CONST_1_HEIGHT__MASK; +} + +#define REG_A5XX_TEX_CONST_2 0x00000002 +#define A5XX_TEX_CONST_2_FETCHSIZE__MASK 0x0000000f +#define A5XX_TEX_CONST_2_FETCHSIZE__SHIFT 0 +static inline uint32_t A5XX_TEX_CONST_2_FETCHSIZE(enum a5xx_tex_fetchsize val) +{ + return ((val) << A5XX_TEX_CONST_2_FETCHSIZE__SHIFT) & A5XX_TEX_CONST_2_FETCHSIZE__MASK; +} +#define A5XX_TEX_CONST_2_PITCH__MASK 0x1fffff00 +#define A5XX_TEX_CONST_2_PITCH__SHIFT 8 +static inline uint32_t A5XX_TEX_CONST_2_PITCH(uint32_t val) +{ + return ((val) << A5XX_TEX_CONST_2_PITCH__SHIFT) & A5XX_TEX_CONST_2_PITCH__MASK; +} +#define A5XX_TEX_CONST_2_TYPE__MASK 0x60000000 +#define A5XX_TEX_CONST_2_TYPE__SHIFT 29 +static inline uint32_t A5XX_TEX_CONST_2_TYPE(enum a5xx_tex_type val) +{ + return ((val) << A5XX_TEX_CONST_2_TYPE__SHIFT) & A5XX_TEX_CONST_2_TYPE__MASK; +} + +#define REG_A5XX_TEX_CONST_3 0x00000003 +#define A5XX_TEX_CONST_3_LAYERSZ__MASK 0x00003fff +#define A5XX_TEX_CONST_3_LAYERSZ__SHIFT 0 +static inline uint32_t A5XX_TEX_CONST_3_LAYERSZ(uint32_t val) +{ + return ((val >> 12) << A5XX_TEX_CONST_3_LAYERSZ__SHIFT) & A5XX_TEX_CONST_3_LAYERSZ__MASK; +} +#define A5XX_TEX_CONST_3_LAYERSZ2__MASK 0xff800000 +#define A5XX_TEX_CONST_3_LAYERSZ2__SHIFT 23 +static inline uint32_t A5XX_TEX_CONST_3_LAYERSZ2(uint32_t val) +{ + return ((val >> 12) << A5XX_TEX_CONST_3_LAYERSZ2__SHIFT) & A5XX_TEX_CONST_3_LAYERSZ2__MASK; +} + +#define REG_A5XX_TEX_CONST_4 0x00000004 +#define A5XX_TEX_CONST_4_BASE__MASK 0xffffffe0 +#define A5XX_TEX_CONST_4_BASE__SHIFT 5 +static inline uint32_t A5XX_TEX_CONST_4_BASE(uint32_t val) +{ + return ((val >> 5) << A5XX_TEX_CONST_4_BASE__SHIFT) & A5XX_TEX_CONST_4_BASE__MASK; +} + +#define REG_A5XX_TEX_CONST_5 0x00000005 +#define A5XX_TEX_CONST_5_DEPTH__MASK 0x3ffe0000 +#define A5XX_TEX_CONST_5_DEPTH__SHIFT 17 +static inline uint32_t A5XX_TEX_CONST_5_DEPTH(uint32_t val) +{ + return ((val) << A5XX_TEX_CONST_5_DEPTH__SHIFT) & A5XX_TEX_CONST_5_DEPTH__MASK; +} + +#define REG_A5XX_TEX_CONST_6 0x00000006 + +#define REG_A5XX_TEX_CONST_7 0x00000007 + +#define REG_A5XX_TEX_CONST_8 0x00000008 + +#define REG_A5XX_TEX_CONST_9 0x00000009 + +#define REG_A5XX_TEX_CONST_10 0x0000000a + +#define REG_A5XX_TEX_CONST_11 0x0000000b + + +#endif /* A5XX_XML */ --- /dev/null 2019-10-24 16:47:25.704025805 +0200 +++ linux-4.4.115-fbx/drivers/gpu/drm/msm/dba_bridge.c 2019-10-29 09:26:23.621202963 +0100 @@ -0,0 +1,367 @@ +/* + * Copyright (c) 2016-2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include